From: Rafał Miłecki <rafal@milecki.pl>
Date: Tue, 22 Feb 2022 09:56:49 +0000 (+0100)
Subject: Add Broadcom / Netgear changes from RAXE 1.0.0.48
X-Git-Url: http://git.openwrt.org/%22https:/collectd.org///%22https:/collectd.org/?a=commitdiff_plain;h=9ba3026e1ed91f34f27c288355103ca10edfd739;p=project%2Fbcm63xx%2Fu-boot.git

Add Broadcom / Netgear changes from RAXE 1.0.0.48

U-Boot changes from RAXE500_V1.0.0.48_5.04L.02_GPL.tar.gz

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
---

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f5a7630e4f..468d6c4dd9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -247,7 +247,8 @@ config CPU_V7A
 	bool
 	select HAS_THUMB2
 	select HAS_VBAR
-	select SYS_CACHE_SHIFT_6
+	select SYS_CACHE_SHIFT_5 if BCM63138
+	select SYS_CACHE_SHIFT_6 if !BCM63138
 	imply SYS_ARM_MMU
 
 config CPU_V7M
@@ -613,6 +614,44 @@ config ARCH_BCMSTB
 	  This enables support for Broadcom ARM-based set-top box
 	  chipsets, including the 7445 family of chips.
 
+config ARCH_BCMBCA
+	bool "Broadcom broadband chip family"
+	select DM
+	select OF_CONTROL
+	select DM_GPIO
+	select LED
+	select OF_BOARD_SETUP
+	select AES
+	select SPI
+	select DM_SPI
+	select BCM63XX_HSSPI
+	select BCMBCA_GPIO if PINCTRL_BCMBCA
+	select OF_SEPARATE
+	select SPL_OF_CONTROL if SPL
+	select TPL_OF_CONTROL if SPL
+	select SPL_DM if SPL
+	select SPL_DM_SERIAL if SPL
+	select SPL_BOARD_INIT if SPL
+	select TPL_BOARD_INIT if SPL
+	select TPL_LOAD_FIT if SPL
+	select TPL_FIT_SIGNATURE if SPL
+	select TPL_HASH_SUPPORT if SPL
+	select TPL_CRYPTO_SUPPORT if SPL
+	select TPL_SHA256_SUPPORT if SPL
+	select SPL_DM_SEQ_ALIAS if SPL
+	select TPL_DM_SEQ_ALIAS if SPL
+	select SPL_SPI_SUPPORT if SPL
+	select TPL_SPI_SUPPORT if SPL
+	select SPL_MTD_SUPPORT if SPL
+	select TPL_MTD_SUPPORT if SPL
+	select ARMV8_SPIN_TABLE if !TPL_ATF && ARM64
+	select ARMV8_MULTIENTRY if !TPL_ATF && ARM64
+	select ARMV8_SET_SMPEN if !TPL_ATF && ARM64
+	select BCM_BCA_LED
+	select OF_BOARD_FIXUP
+
+	imply CMD_DM
+
 config TARGET_VEXPRESS_CA5X2
 	bool "Support vexpress_ca5x2"
 	select CPU_V7A
@@ -1586,6 +1625,8 @@ source "arch/arm/mach-bcm283x/Kconfig"
 
 source "arch/arm/mach-bcmstb/Kconfig"
 
+source "arch/arm/mach-bcmbca/Kconfig"
+
 source "arch/arm/mach-davinci/Kconfig"
 
 source "arch/arm/mach-exynos/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5384981c17..80ebcc4a34 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -84,6 +84,7 @@ machine-$(CONFIG_ARCH_ZYNQ)		+= zynq
 machine-$(CONFIG_ARCH_ZYNQMP)		+= zynqmp
 machine-$(CONFIG_ARCH_VERSAL)		+= versal
 machine-$(CONFIG_ARCH_ZYNQMP_R5)	+= zynqmp-r5
+machine-$(CONFIG_ARCH_BCMBCA)		+= bcmbca
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 20dbc2ff84..bcc8548033 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -757,6 +757,49 @@ dtb-$(CONFIG_ARCH_BCM63158) += \
 dtb-$(CONFIG_ARCH_BCM6858) += \
 	bcm968580xref.dtb
 
+dtb-$(CONFIG_BCM63158) += \
+	bcm963158.dtb
+
+dtb-$(CONFIG_BCM6858) += \
+	bcm96858.dtb
+
+dtb-$(CONFIG_BCM6856) += \
+	bcm96856.dtb
+
+dtb-$(CONFIG_BCM63178) += \
+	bcm963178.dtb
+
+dtb-$(CONFIG_BCM47622) += \
+	bcm947622.dtb \
+	bcm947622ref1sg.dtb
+
+dtb-$(CONFIG_BCM6756) += \
+	bcm96756.dtb
+
+dtb-$(CONFIG_BCM4908) += \
+	bcm94908.dtb
+
+dtb-$(CONFIG_BCM4912) += \
+	bcm94912.dtb
+
+dtb-$(CONFIG_BCM63138) += \
+	bcm963138.dtb
+
+dtb-$(CONFIG_BCM63148) += \
+	bcm963148.dtb
+
+dtb-$(CONFIG_BCM63146) += \
+	bcm963146.dtb
+
+dtb-$(CONFIG_BCM6846) += \
+	bcm96846.dtb
+
+dtb-$(CONFIG_BCM6878) += \
+	bcm96878.dtb
+
+dtb-$(CONFIG_BCM6855) += \
+	bcm96855.dtb
+
 dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
 
 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
diff --git a/arch/arm/dts/bcm47622-pinctrl.dtsi b/arch/arm/dts/bcm47622-pinctrl.dtsi
new file mode 100644
index 0000000000..67859fcce1
--- /dev/null
+++ b/arch/arm/dts/bcm47622-pinctrl.dtsi
@@ -0,0 +1,18 @@
+
+/ {
+
+    usb0_pwr_pins: usb0_pwr_pinmux {
+        pins = <79 80>;
+        function = <1>;
+    };
+
+    usb1_pwr_pins: usb1_pwr_pinmux {
+        pins = <81 82>;
+        function = <1>;
+    };
+
+	xmii_1_pins: xmii_1_pins {
+		pins = <10 56 57 58 59 60 61 62 63 64 65 66 67 68 69>;
+		function = <1>;
+	};
+};
diff --git a/arch/arm/dts/bcm4908-pinctrl.dtsi b/arch/arm/dts/bcm4908-pinctrl.dtsi
new file mode 100644
index 0000000000..b39518750d
--- /dev/null
+++ b/arch/arm/dts/bcm4908-pinctrl.dtsi
@@ -0,0 +1,12 @@
+/ {
+
+    usb0a_pwrflt_pins: usb0a_pwrflt_pinmux {
+        pins = <63 66>;
+        function = <0>;
+    };
+
+    usb0a_pwron_pins: usb0a_pwron_pinmux {
+        pins = <64 67>;
+        function = <0>;
+    };
+};
diff --git a/arch/arm/dts/bcm4908.dtsi b/arch/arm/dts/bcm4908.dtsi
new file mode 100644
index 0000000000..3060a52bd9
--- /dev/null
+++ b/arch/arm/dts/bcm4908.dtsi
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include "skeleton64.dtsi"
+#include "bcm4908-pinctrl.dtsi"
+#include "bcmbca-sf2net.dtsi"
+
+/ {
+	compatible = "brcm,bcm4908";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		spi1 = &hsspi;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		        u-boot,dm-pre-reloc;
+		};
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <2>;
+			clock-div = <1>;
+		        u-boot,dm-pre-reloc;			
+		};
+	};
+
+	boot_state {
+		u-boot,dm-pre-reloc; 
+		compatible = "brcm,bcmbca-bootstate-v2";
+		reg-names = "reset_status", "reset_reason";
+		reg =   <0x0 0xff800438 0x0 0x04>,
+			<0x0 0xFF802628 0x0 0x04>;
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+
+
+		uart0: serial@ff800640 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x0 0xff800640 0x0 0x1000>;
+			clocks = <&refclk50mhz>;
+			u-boot,dm-pre-reloc;
+		};
+		leds: led-controller@ff800800 {
+			compatible = "brcm,bcm6858-leds";
+			reg = <0x0 0xff800800 0x0 0xe4>;
+
+			status = "disabled";
+		};
+
+		wdt1: watchdog@ff800480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x0 0xff800428 0x0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+
+		sf2gmac_eth {
+			compatible = "brcm,bcmbca-sf2gmac";
+			reg-names = "gmac-intf-base",
+						"gmac-mac-base",
+						"gmac-dma-base";
+
+		reg = <0x0 0x80002000 0x0 0x48>,
+			<0x0 0x80002400 0x0 0x340>,
+			<0x0 0x80002800 0x0 0x420>;
+
+			ethsw = <&switchsf2>;
+		};
+
+		switchsf2: sf2@0x80080000 {
+		compatible = "brcm,bcmbca-sf2";
+		phy_base = <0x8>;
+		reg-names = "switchcore-base",
+					"switchreg-base",
+					"switchmdio-base",
+					"qphy-ctrl",
+					"sphy-ctrl",
+					"phy-test-ctrl";
+
+		reg = <0x0 0x80080000 0x0 0x286B0>,
+			<0x0 0x800C0000 0x0 0x3F4>,
+			<0x0 0x800C05C0 0x0 0x8>,
+			<0x0 0x800C001C 0x0 0x04>,
+			<0x0 0x800C0024 0x0 0x04>,
+			<0x0 0x800C0018 0x0 0x04>;
+		};
+
+		pinctrl: pinctrl {
+		compatible = "brcm,bcmbca-pinctrl";
+		reg = <0x0 0xff800564 0x0 0x14>;
+		};
+
+		usb_ctrl:usb_ctrl {
+		compatible = "brcm,bcmbca-usb-ctrl";
+		reg-names = "usb-ctrl";
+		reg = <0x0 0x8000c200 0x0 0x100>;
+		status = "okay";
+		};
+
+		usb0: usb@0x8000c300 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x0 0x8000c300 0x0 0x100>;
+		};
+
+		usb_ohci0: usb_ohci@0x8000c400 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x0 0x8000c400 0x0 0x100>;
+		};
+
+		hsspi: spi-controller@ff801000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			u-boot,dm-pre-reloc;			
+			reg = <0x0 0xff801000 0x0 0x600>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <100000000>;
+			num-cs = <8>;
+			status = "disabled";			
+		};
+
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.1",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0x0 0xff801800 0x0 0x400>,
+			      <0x0 0xff802000 0x0 0x10>,
+			      <0x0 0xff801c00 0x0 0x200>;
+			parameter-page-big-endian = <0>;
+
+			status = "disabled";
+		};
+
+		sdhci: sdhci@ff858000 {
+			compatible = "brcm,bcm63xx-sdhci",
+			             "brcm,sdhci-brcmbca";
+			reg-names = "sdhci-base", "sdhci-boot";
+			reg = <0x0 0xff858000 0x0 0x100>,
+			      <0x0 0xff858200 0x0 0x40>;	
+			bus-width = <8>;
+			u-boot,dm-pre-reloc;
+		};
+		
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0x0 0xff800b80 0x0 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/arm/dts/bcm4912.dtsi b/arch/arm/dts/bcm4912.dtsi
new file mode 100644
index 0000000000..1ba433020a
--- /dev/null
+++ b/arch/arm/dts/bcm4912.dtsi
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#include "skeleton64.dtsi"
+
+/ {
+	compatible = "brcm,bcm4912";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <1>;
+			clock-div = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@ff812000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xff812000 0x0 0x1000>;
+			clock = <50000000>;
+
+			status = "disabled";
+		};
+
+		wdt1: watchdog@ff800480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x0 0xff800480 0x0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt2: watchdog@ff8004c0 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x0 0xff8004c0 0x0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.1",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0x0 0xff801800 0x0 0x400>,
+			      <0x0 0xff802000 0x0 0x10>,
+			      <0x0 0xff801c00 0x0 0x200>;
+			parameter-page-big-endian = <0>;
+
+			status = "disabled";
+		};
+		
+		hsspi: hsspi@ff801000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			u-boot,dm-pre-reloc;
+			
+			reg = <0x0 0xff801000 0x0 0x1000>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <100000000>;
+			num-cs = <8>;
+			status = "disabled";
+		};
+
+		sdhci: sdhci@ff810000 {
+			compatible = "brcm,bcm63xx-sdhci",
+				     "brcm,sdhci-brcmbca";
+			reg-names = "sdhci-base", "sdhci-boot";
+			reg = <0x0 0xff810000 0x0 0x100>,
+			      <0x0 0xff810200 0x0 0x40>;
+			bus-width = <8>;
+			u-boot,dm-pre-reloc;
+		};
+
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0x0 0xff800b80 0x0 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+	unimac {
+		compatible = "brcm,unimac";
+		reg = <0x0 0x828a8000 0x0 0x8000>,
+		      <0x0 0x828b0000 0x0 0x2000>;
+		conf_offset = <0x1000>;
+		mib_offset = <0x400>;
+		top_offset = <0x400>;
+		mib_step = <0x2>;
+	};
+
+	egphy {
+		compatible = "brcm,egphy";
+		reg = <0x0 0x837FF00C 0x0 0x10>;
+	};
+
+	mdio5 {
+		compatible = "brcm,mdio5";
+		reg = <0x0 0x837FFD00 0x0 0x10>,
+		      <0x0 0xff85a024 0x0 0x4>;
+	};
+
+	xrdp {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x0 0x0 0x0 0x82000000 0x0 0xcd0000
+			  0x1 0x0 0x0 0xff800000 0x0 0x62000>;
+
+		mdio: mdio {
+			compatible = "simple-bus";
+			bus-type = "MDIO_V1_INT";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			phy1:1 {
+				compatible = "brcm,bcaphy";
+				phy-type = "EGPHY";
+				reg = <1>;
+				status = "disabled";
+			};
+
+			phy2:2 {
+				compatible = "brcm,bcaphy";
+				phy-type = "EGPHY";
+				reg = <2>;
+				status = "disabled";
+			};
+
+			phy3:3 {
+				compatible = "brcm,bcaphy";
+				phy-type = "EGPHY";
+				reg = <3>;
+				status = "disabled";
+			};
+
+			phy4:4 {
+				compatible = "brcm,bcaphy";
+				phy-type = "EGPHY";
+				reg = <4>;
+				status = "disabled";
+			};
+		};
+
+		/* FIXME!
+		rgmii: rgmii {
+			compatible = "brcm,rgmii1";
+			reg = <0x0 0x828A0300 0x0 0x44
+			       0x0 0xff800500 0x0 0x78>;
+			status = "disabled";
+		};
+		*/
+
+		switch0: switch0 {
+		};
+	};
+
+	boot_state {
+		u-boot,dm-pre-reloc;
+		compatible = "brcm,bcmbca-bootstate-v2";
+		reg-names = "reset_reason", "reset_status";
+		reg =   <0x0 0xff802628 0x0 0x04>,
+			<0x0 0xff85a01c 0x0 0x04>;
+	};
+};
+
+&switch0 {
+	compatible = "brcm,enet";
+	label = "bcmsw";
+	sw-type = "RUNNER_SW";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			reg = <0>;
+			mac-type = "UNIMAC";
+			phy-handle = <&phy1>;
+			phy-mode = "gmii";
+			gmii-direct;
+			status = "disabled";
+		};
+
+		port1@1 {
+			reg = <1>;
+			mac-type = "UNIMAC";
+			phy-handle = <&phy2>;
+			phy-mode = "gmii";
+			gmii-direct;
+			status = "disabled";
+		};
+
+		port2@2 {
+			reg = <2>;
+			mac-type = "UNIMAC";
+			phy-handle = <&phy3>;
+			phy-mode = "gmii";
+			gmii-direct;
+			status = "disabled";
+		};
+
+		port3@3 {
+			reg = <3>;
+			mac-type = "UNIMAC";
+			phy-handle = <&phy4>;
+			phy-mode = "gmii";
+			gmii-direct;
+			status = "disabled";
+		};
+
+		/* FIXME
+		port4@4 {
+			reg = <4>;
+			mac-type = "UNIMAC";
+			phy-handle = <&phy_rgmii>;
+			phy-mode = "rgmii";
+			gmii-direct;
+			status = "disabled";
+		}; */
+	};
+};
+
diff --git a/arch/arm/dts/bcm63138-pinctrl.dtsi b/arch/arm/dts/bcm63138-pinctrl.dtsi
new file mode 100644
index 0000000000..be2ac57aaf
--- /dev/null
+++ b/arch/arm/dts/bcm63138-pinctrl.dtsi
@@ -0,0 +1,13 @@
+
+/ {
+
+    usb0a_pwrflt_pins: usb0a_pwrflt_pinmux {
+        pins = <132>;
+        function = <1>;
+    };
+
+    usb0a_pwron_pins: usb0a_pwron_pinmux {
+        pins = <133>;
+        function = <1>;
+    };
+};
diff --git a/arch/arm/dts/bcm63138.dtsi b/arch/arm/dts/bcm63138.dtsi
new file mode 100644
index 0000000000..bd36139649
--- /dev/null
+++ b/arch/arm/dts/bcm63138.dtsi
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include "skeleton.dtsi"
+#include "bcm63138-pinctrl.dtsi"
+#include "bcmbca-sf2net.dtsi"
+
+
+/ {
+	compatible = "brcm,bcm63138";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+		
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&refclk50mhz>;
+			clock-mult = <8>;
+			clock-div = <1>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	ubus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@fffe8600 {	
+			u-boot,dm-pre-reloc;
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe8600 0x20>;
+			clocks = <&refclk50mhz>;
+			status = "disabled";
+		};
+
+		timer0: timer@fffe8080 {
+			u-boot,dm-pre-reloc;
+			compatible = "brcm,bcm6xxx-timer";
+			reg = <0xfffe8080 0x28>;
+			clocks = <&refclk50mhz>;
+			status = "disabled";
+		};
+
+		wdt1: watchdog@fffe80a8 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xfffe80a8 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+
+		rdp_eth {
+			compatible = "brcm,bcmbca-rdp";
+			ethsw = <&switchsf2>;
+		};
+
+		switchsf2: sf2@0x80080000 {
+			compatible = "brcm,bcmbca-sf2";
+			phy_base = <0x8>;
+			reg-names = "switchcore-base",
+						"switchreg-base",
+						"switchmdio-base",
+						"qphy-ctrl",
+						"sphy-ctrl",
+						"phy-test-ctrl";
+			reg = <0x80080000 0x40000>,
+					<0x800c0000 0x1a8>,
+					<0x800c03c0 0x8>,
+					<0x800c0024 0x4>,
+					<0x800c002c 0x4>,
+					<0x800c0020 0x4>;
+		};
+
+		nand: nand-controller@fffea000 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.0",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0xfffea000 0x400>,
+			      <0xfffe80f0 0x10>,
+			      <0xfffea400 0x200>;
+			parameter-page-big-endian = <0>;
+
+			status = "disabled";
+		};
+
+		hsspi: hsspi@ff801000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			u-boot,dm-pre-reloc;
+			
+			reg = <0xfffe9000 0x1000>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <100000000>;
+			num-cs = <8>;
+			status = "disabled";
+		};
+
+		sdhci: sdhci@fffec000 {
+			compatible = "brcm,bcm63xx-sdhci",
+			             "brcm,sdhci-brcmbca";
+			reg-names = "sdhci-base", "sdhci-boot";
+			reg = <0xfffec000 0x100>,
+			      <0xfffec200 0x40>;	
+			bus-width = <8>;
+			u-boot,dm-pre-reloc;
+		};
+
+		rng: rng@fffe8300 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0xfffe8300 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+
+		pinctrl: pinctrl {
+			compatible = "brcm,bcmbca-pinctrl";
+			reg = <0xfffe813c 0x14>;
+		};
+
+		usb_ctrl:usb_ctrl {
+			compatible = "brcm,bcmbca-usb-ctrl";
+			reg-names = "usb-ctrl";
+			reg = <0x8000c200 0x100>;
+			status = "okay";
+		};
+
+		usb0: usb@0x8000c300 {
+			compatible = "brcm,bcmbca-ehci";
+			reg-names = "usb-ehci";
+			reg = <0x8000c300 0x100>;
+		};
+
+		usb_ohci0: usb_ohci@0x8000c400 {
+			compatible = "brcm,bcmbca-ohci";
+			reg-names = "usb-ohci";
+			reg = <0x8000c400 0x100>;
+		};
+
+		boot_state {
+                u-boot,dm-pre-reloc;
+                compatible = "brcm,bcmbca-bootstate-v1";
+                reg-names = "reset_status", "global_control",
+				"flash_control", "mode_control";
+		reg = <0xfffe80b8 0x04>,
+			<0xfffe9000 0x04>,
+			<0xfffe9014 0x04>,
+			<0xfffe91e8 0x04>;
+		};
+	};
+};
diff --git a/arch/arm/dts/bcm63146.dtsi b/arch/arm/dts/bcm63146.dtsi
new file mode 100644
index 0000000000..6e2050e8e5
--- /dev/null
+++ b/arch/arm/dts/bcm63146.dtsi
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include "skeleton64.dtsi"
+
+/ {
+	compatible = "brcm,bcm63146";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <1>;
+			clock-div = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@ff812000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xff812000 0x0 0x1000>;
+			clock = <50000000>;
+
+			status = "disabled";
+		};
+
+		hsspi: hsspi@ff801000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			u-boot,dm-pre-reloc;
+			
+			reg = <0x0 0xff801000 0x0 0x1000>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <100000000>;
+			num-cs = <8>;
+			status = "disabled";
+		};
+		
+		wdt1: watchdog@ff800480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x0 0xff800480 0x0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt2: watchdog@ff8004c0 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x0 0xff8004c0 0x0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.1",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0x0 0xff801800 0x0 0x400>,
+			      <0x0 0xff802000 0x0 0x10>,
+			      <0x0 0xff801c00 0x0 0x200>;
+			parameter-page-big-endian = <0>;
+
+			status = "disabled";
+		};
+
+		sdhci: sdhci@ff810000 {
+			compatible = "brcm,bcm63xx-sdhci",
+				     "brcm,sdhci-brcmbca";
+			reg-names = "sdhci-base", "sdhci-boot";
+			reg = <0x0 0xff810000 0x0 0x100>,
+			      <0x0 0xff810200 0x0 0x40>;
+			bus-width = <8>;
+			u-boot,dm-pre-reloc;
+		};
+
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0x0 0xff800b80 0x0 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	unimac {
+		compatible = "brcm,unimac";
+		reg = <0x0 0x828a8000 0x0 0x8000>,
+		      <0x0 0x828b0000 0x0 0x2000>;
+		conf_offset = <0x1000>;
+		mib_offset = <0x400>;
+		top_offset = <0x400>;
+		mib_step = <0x2>;
+	};
+
+	egphy {
+		compatible = "brcm,egphy";
+		reg = <0x0 0x837FF00C 0x0 0x20>;
+	};
+
+	mdio5 {
+		compatible = "brcm,mdio5";
+		reg = <0x0 0x837FFD00 0x0 0x10>,
+		      <0x0 0xff85a024 0x0 0x4>;
+	};
+
+	xrdp {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x0 0x0 0x0 0x82000000 0x0 0xcd0000
+			  0x1 0x0 0x0 0xff800000 0x0 0x62000>;
+
+		mdio: mdio {
+			compatible = "simple-bus";
+			bus-type = "MDIO_V1_INT";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			phy1:1 {
+				compatible = "brcm,bcaphy";
+				phy-type = "EGPHY";
+				reg = <1>;
+				status = "disabled";
+			};
+
+			phy2:2 {
+				compatible = "brcm,bcaphy";
+				phy-type = "EGPHY";
+				reg = <2>;
+				status = "disabled";
+			};
+
+			phy3:3 {
+				compatible = "brcm,bcaphy";
+				phy-type = "EGPHY";
+				reg = <3>;
+				status = "disabled";
+			};
+
+			phy4:4 {
+				compatible = "brcm,bcaphy";
+				phy-type = "EGPHY";
+				reg = <4>;
+				status = "disabled";
+			};
+
+			phy5:5 {
+				compatible = "brcm,bcaphy";
+				phy-type = "EGPHY";
+				reg = <5>;
+				status = "disabled";
+			};
+
+			/* FIXME!
+			phy_rgmii:rgmii {
+				compatible = "brcm,bcaphy";
+				phy-type = "EXT1";
+				reg = <7>;
+				status = "disabled";
+			};
+			*/
+		};
+
+		/* FIXME!
+		rgmii: rgmii {
+			compatible = "brcm,rgmii1";
+			reg = <0x0 0x828A0300 0x0 0x44
+			       0x0 0xff800500 0x0 0x78>;
+			status = "disabled";
+		};
+		*/
+
+		switch0: switch0 {
+		};
+	};
+};
+
+&switch0 {
+	compatible = "brcm,enet";
+	label = "bcmsw";
+	sw-type = "RUNNER_SW";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port0@0 {
+			reg = <0>;
+			mac-type = "UNIMAC";
+			phy-handle = <&phy1>;
+			phy-mode = "gmii";
+			gmii-direct;
+			status = "disabled";
+		};
+
+		port1@1 {
+			reg = <1>;
+			mac-type = "UNIMAC";
+			phy-handle = <&phy2>;
+			phy-mode = "gmii";
+			gmii-direct;
+			status = "disabled";
+		};
+
+		port2@2 {
+			reg = <2>;
+			mac-type = "UNIMAC";
+			phy-handle = <&phy3>;
+			phy-mode = "gmii";
+			gmii-direct;
+			status = "disabled";
+		};
+
+		port3@3 {
+			reg = <3>;
+			mac-type = "UNIMAC";
+			phy-handle = <&phy4>;
+			phy-mode = "gmii";
+			gmii-direct;
+			status = "disabled";
+		};
+
+		port4@4 {
+			reg = <4>;
+			mac-type = "UNIMAC";
+			phy-handle = <&phy5>;
+			phy-mode = "gmii";
+			gmii-direct;
+			status = "disabled";
+		};
+
+		/* FIXME
+		port5@5 {
+			reg = <5>;
+			mac-type = "UNIMAC";
+			phy-handle = <&phy_serdes>;
+			phy-mode = "hsgmii";
+			gmii-direct;
+			status = "disabled";
+		}; */
+	};
+};
diff --git a/arch/arm/dts/bcm63148.dtsi b/arch/arm/dts/bcm63148.dtsi
new file mode 100644
index 0000000000..f59eb24cdb
--- /dev/null
+++ b/arch/arm/dts/bcm63148.dtsi
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include "skeleton.dtsi"
+/* #include "bcm63138-pinctrl.dtsi" */
+#include "bcmbca-sf2net.dtsi"
+
+
+/ {
+	compatible = "brcm,bcm63148";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	ubus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@fffe8600 {	
+			u-boot,dm-pre-reloc;
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe8600 0x20>;
+			clocks = <&refclk50mhz>;
+			status = "disabled";
+		};
+
+		timer0: timer@fffe8080 {
+			u-boot,dm-pre-reloc;
+			compatible = "brcm,bcm6xxx-timer";
+			reg = <0xfffe8080 0x28>;
+			clocks = <&refclk50mhz>;
+			status = "disabled";
+		};
+
+		wdt1: watchdog@fffe80a8 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xfffe80a8 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+
+		rdp_eth {
+			compatible = "brcm,bcmbca-rdp";
+			ethsw = <&switchsf2>;
+		};
+
+		switchsf2: sf2@0x80080000 {
+			compatible = "brcm,bcmbca-sf2";
+			phy_base = <0x8>;
+			reg-names = "switchcore-base",
+						"switchreg-base",
+						"switchmdio-base",
+						"qphy-ctrl",
+						"sphy-ctrl",
+						"phy-test-ctrl";
+			reg = <0x80080000 0x40000>,
+					<0x800c0000 0x1a8>,
+					<0x800c03c0 0x8>,
+					<0x800c0024 0x4>,
+					<0x800c002c 0x4>,
+					<0x800c0020 0x4>;
+		};
+
+		nand: nand-controller@fffea000 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.1",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0xfffea000 0x400>,
+			      <0xfffe80f0 0x10>,
+			      <0xfffea400 0x200>;
+			parameter-page-big-endian = <0>;
+
+			status = "disabled";
+		};
+
+		rng: rng@fffe8300 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0xfffe8300 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+
+		pinctrl: pinctrl {
+			compatible = "brcm,bcmbca-pinctrl";
+			reg = <0xfffe813c 0x14>;
+		};
+
+		usb_ctrl:usb_ctrl {
+			compatible = "brcm,bcmbca-usb-ctrl";
+			reg-names = "usb-ctrl";
+			reg = <0x8000c200 0x100>;
+			status = "okay";
+		};
+
+		usb0: usb@0x8000c300 {
+			compatible = "brcm,bcmbca-ehci";
+			reg-names = "usb-ehci";
+			reg = <0x8000c300 0x100>;
+		};
+
+		usb_ohci0: usb_ohci@0x8000c400 {
+			compatible = "brcm,bcmbca-ohci";
+			reg-names = "usb-ohci";
+			reg = <0x8000c400 0x100>;
+		};
+
+		boot_state {
+		u-boot,dm-pre-reloc;
+		compatible = "brcm,bcmbca-bootstate-v1";
+                reg-names = "reset_status", "global_control",
+				"flash_control", "mode_control";
+		reg = <0xfffe80b8 0x04>,
+			<0xfffe9000 0x04>,
+			<0xfffe9014 0x04>,
+			<0xfffe91e8 0x04>;
+		};
+
+
+	};
+};
diff --git a/arch/arm/dts/bcm63158-pinctrl.dtsi b/arch/arm/dts/bcm63158-pinctrl.dtsi
new file mode 100644
index 0000000000..87757e727d
--- /dev/null
+++ b/arch/arm/dts/bcm63158-pinctrl.dtsi
@@ -0,0 +1,44 @@
+
+/ {
+
+    usb0a_pwrflt_pins: usb0a_pwrflt_pinmux {
+        pins = <121>;
+        function = <1>;
+    };
+
+    usb0a_pwron_pins: usb0a_pwron_pinmux {
+        pins = <122>;
+        function = <1>;
+    };
+
+    usb0b_pwrflt_pins: usb0b_pwrflt_pinmux {
+        pins = <123>;
+        function = <2>;
+    };
+
+    usb0b_pwron_pins: usb0b_pwron_pinmux {
+        pins = <124>;
+        function = <2>;
+    };
+
+    usb1a_pwrflt_pins: usb1a_pwrflt_pinmux {
+        pins = <123>;
+        function = <1>;
+    };
+
+    usb1a_pwron_pins: usb1a_pwron_pinmux {
+        pins = <124>;
+        function = <1>;
+    };
+
+    usb1b_pwrflt_pins: usb1b_pwrflt_pinmux {
+        pins = <121>;
+        function = <2>;
+    };
+
+    usb1b_pwron_pins: usb1b_pwron_pinmux {
+        pins = <122>;
+        function = <2>;
+    };
+
+};
diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi
index 175af38018..ee023f1f4a 100644
--- a/arch/arm/dts/bcm63158.dtsi
+++ b/arch/arm/dts/bcm63158.dtsi
@@ -4,12 +4,18 @@
  */
 
 #include "skeleton64.dtsi"
+#include "bcm63158-pinctrl.dtsi"
+#include "bcmbca-sf2net.dtsi"
 
 / {
 	compatible = "brcm,bcm63158";
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		spi1 = &hsspi;
+	};
+
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
@@ -63,10 +69,19 @@
 		periph_osc: periph-osc {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <0xbebc200>;
+			clock-frequency = <200000000>;
 			u-boot,dm-pre-reloc;
 		};
 
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <2>;
+			clock-div = <1>;
+			u-boot,dm-pre-reloc;			
+		};
+
 		refclk50mhz: refclk50mhz {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
@@ -112,97 +127,125 @@
 			wdt = <&wdt1>;
 		};
 
-		gpio0: gpio-controller@0xff800500 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800500 0x0 0x4>,
-			      <0x0 0xff800520 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
+		hsspi: spi-controller@ff801000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			u-boot,dm-pre-reloc;			
+			reg = <0x0 0xff801000 0x0 0x600>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <100000000>;
+			num-cs = <8>;
 
 			status = "disabled";
 		};
 
-		gpio1: gpio-controller@0xff800504 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800504 0x0 0x4>,
-			      <0x0 0xff800524 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.1",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0x0 0xff801800 0x0 0x400>,
+			      <0x0 0xff802000 0x0 0x10>,
+			      <0x0 0xff801c00 0x0 0x200>;
+			parameter-page-big-endian = <0>;
 
 			status = "disabled";
 		};
 
-		gpio2: gpio-controller@0xff800508 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800508 0x0 0x4>,
-			      <0x0 0xff800528 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
+		sdhci: sdhci@ff810000 {
+			compatible = "brcm,bcm63xx-sdhci",
+			             "brcm,sdhci-brcmbca";
+			reg-names = "sdhci-base", "sdhci-boot";
+			reg = <0x0 0xff810000 0x0 0x100>,
+			      <0x0 0xff810200 0x0 0x40>;	
+			bus-width = <8>;
+			u-boot,dm-pre-reloc;
 		};
 
-		gpio3: gpio-controller@0xff80050c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff80050c 0x0 0x4>,
-			      <0x0 0xff80052c 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0x0 0xff800b80 0x0 0x28>;
+			u-boot,dm-pre-reloc;
 		};
-
-		gpio4: gpio-controller@0xff800510 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800510 0x0 0x4>,
-			      <0x0 0xff800530 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
+		sysport: systemport@0x80490000 {
+		compatible = "brcm,bcmbca-systemport-v-1.0";
+		qphy-avaiable=<0x01>;
+		sphy-available=<0x01>;
+		reg-names = "systemport-rbuf-base", "systemport-rdma-base",
+				"systemport-tdma-base",
+				"systemport-umac-base",
+				"systemport-topctrl-base";
+		reg =	<0x0 0x80490400 0x0 0x14>,
+			<0x0 0x80492000 0x0 0x1060>,
+			<0x0 0x80494000 0x0 0x650>,
+			<0x0 0x80490800 0x0 0x650>,
+			<0x0 0x80490000 0x0 0x10>;
+		ethsw = <&switchsf2>;
 		};
 
-		gpio5: gpio-controller@0xff800514 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800514 0x0 0x4>,
-			      <0x0 0xff800534 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
+		switchsf2: sf2@80400000 {
+		compatible = "brcm,bcmbca-sf2";
+		phy_base = <0x8>;
+		phy_wkard_timeout = <25000>;
+		reg-names = "switchcore-base",
+					"switchreg-base",
+					"switchmdio-base",
+					"qphy-ctrl",
+					"sphy-ctrl",
+					"phy-test-ctrl";
 
-			status = "disabled";
+		reg = <0x0 0x80400000 0x0 0x72724>,
+			<0x0 0x80480000 0x0 0x458>,
+			<0x0 0x804805c0 0x0 0x10>,
+			<0x0 0x8048001c 0x0 0x04>,
+			<0x0 0x80480024 0x0 0x04>,
+			<0x0 0x80480018 0x0 0x04>;
 		};
 
-		gpio6: gpio-controller@0xff800518 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800518 0x0 0x4>,
-			      <0x0 0xff800538 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
+		pinctrl: pinctrl {
+		compatible = "brcm,bcmbca-pinctrl";
+		reg = <0x0 0xff800554 0x0 0x14>;
+		};
 
-			status = "disabled";
+		usb_ctrl:usb_ctrl {
+		compatible = "brcm,bcmbca-usb-ctrl";
+		reg-names = "usb-ctrl";
+		reg = <0x0 0x8000c200 0x0 0x100>;
+		status = "okay";
 		};
 
-		gpio7: gpio-controller@0xff80051c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff80051c 0x0 0x4>,
-			      <0x0 0xff80053c 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
+		usb0: usb@0x8000c300 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x0 0x8000c300 0x0 0x100>;
+		};
 
-			status = "disabled";
+		usb1: usb@0x8000c500 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x0 0x8000c500 0x0 0x100>;
 		};
 
-		nand: nand-controller@ff801800 {
-			compatible = "brcm,nand-bcm63158",
-				     "brcm,brcmnand-v5.0",
-				     "brcm,brcmnand";
-			reg-names = "nand", "nand-int-base", "nand-cache";
-			reg = <0x0 0xff801800 0x0 0x180>,
-			      <0x0 0xff802000 0x0 0x10>,
-			      <0x0 0xff801c00 0x0 0x200>;
-			parameter-page-big-endian = <0>;
+		usb_ohci0: usb_ohci@0x8000c400 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x0 0x8000c400 0x0 0x100>;
+		};
 
-			status = "disabled";
+		usb_ohci1: usb_ohci@0x8000c600 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x0 0x8000c600 0x0 0x100>;
 		};
+
+		boot_state {
+		u-boot,dm-pre-reloc;
+		compatible = "brcm,bcmbca-bootstate-v2";
+		reg-names = "reset_reason", "reset_status";
+		reg =   <0x00 0xff802628 0x00 0x04>,
+			<0x00 0xff85a03c 0x00 0x04>;
+		};		
 	};
 };
diff --git a/arch/arm/dts/bcm63178-pinctrl.dtsi b/arch/arm/dts/bcm63178-pinctrl.dtsi
new file mode 100644
index 0000000000..41b462a83a
--- /dev/null
+++ b/arch/arm/dts/bcm63178-pinctrl.dtsi
@@ -0,0 +1,14 @@
+
+/ {
+
+    usb0_pwr_pins: usb0_pwr_pinmux {
+        pins = <83 84>;
+        function = <1>;
+    };
+
+    usb1_pwr_pins: usb1_pwr_pinmux {
+        pins = <85 86>;
+        function = <1>;
+    };
+
+};
diff --git a/arch/arm/dts/bcm6756-pinctrl.dtsi b/arch/arm/dts/bcm6756-pinctrl.dtsi
new file mode 100644
index 0000000000..67859fcce1
--- /dev/null
+++ b/arch/arm/dts/bcm6756-pinctrl.dtsi
@@ -0,0 +1,18 @@
+
+/ {
+
+    usb0_pwr_pins: usb0_pwr_pinmux {
+        pins = <79 80>;
+        function = <1>;
+    };
+
+    usb1_pwr_pins: usb1_pwr_pinmux {
+        pins = <81 82>;
+        function = <1>;
+    };
+
+	xmii_1_pins: xmii_1_pins {
+		pins = <10 56 57 58 59 60 61 62 63 64 65 66 67 68 69>;
+		function = <1>;
+	};
+};
diff --git a/arch/arm/dts/bcm6856.dtsi b/arch/arm/dts/bcm6856.dtsi
new file mode 100644
index 0000000000..80a1ccee80
--- /dev/null
+++ b/arch/arm/dts/bcm6856.dtsi
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include "skeleton64.dtsi"
+
+/ {
+	compatible = "brcm,bcm6856";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <2>;
+			clock-div = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	boot_state {
+		u-boot,dm-pre-reloc;
+		compatible = "brcm,bcmbca-bootstate-v2";
+		reg-names = "reset_reason", "reset_status";
+		reg =   <0x00 0xff80263c 0x00 0x04>,
+			<0x00 0xff85a03c 0x00 0x04>;
+		};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@ff800640 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x0 0xff800640 0x0 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		leds: led-controller@ff800800 {
+			compatible = "brcm,bcm6858-leds";
+			reg = <0x0 0xff800800 0x0 0xe4>;
+
+			status = "disabled";
+		};
+
+		wdt1: watchdog@ff800480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x0 0xff800480 0x0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt2: watchdog@ff8004c0 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x0 0xff8004c0 0x0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.1",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0x0 0xff801800 0x0 0x400>,
+			      <0x0 0xff802000 0x0 0x10>,
+			      <0x0 0xff801c00 0x0 0x200>;
+			parameter-page-big-endian = <0>;
+
+			status = "disabled";
+		};
+
+		hsspi: hsspi@ff801000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			u-boot,dm-pre-reloc;
+			
+			reg = <0x0 0xff801000 0x0 0x1000>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <100000000>;
+			num-cs = <8>;
+			status = "disabled";
+		};
+
+		sdhci: sdhci@ff858000 {
+			compatible = "brcm,bcm63xx-sdhci",
+			             "brcm,sdhci-brcmbca";
+			reg-names = "sdhci-base", "sdhci-boot";
+			reg = <0x0 0xff858000 0x0 0x100>,
+			      <0x0 0xff858200 0x0 0x40>;	
+			bus-width = <8>;
+			u-boot,dm-pre-reloc;
+		};
+
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0x0 0xff800b80 0x0 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+
+		pinctrl: pinctrl {
+		    compatible = "brcm,bcmbca-pinctrl";
+            reg = <0x0 0xff800554 0x0 0x14>;
+            gpio-mux = <4>;
+		};
+
+        gpioc: gpioc {
+			compatible = "brcm,bca-gpio";
+            gpio-controller;
+            #gpio-cells = <2>;
+            reg = <0x0 0xff800500 0x0 0x20>, <0x0 0xff800520 0x0 0x20>;
+            reg-names = "gpio-dir", "gpio-data";
+            ngpios = <84>;
+            gpio-ranges = <&pinctrl 0 0 84>;
+        };
+
+		usb_ctrl:usb_ctrl {
+		compatible = "brcm,bcmbca-usb-ctrl";
+		reg-names = "usb-ctrl";
+		reg = <0x0 0x8000c200 0x0 0x100>;
+		status = "okay";
+		};
+
+		usb0: usb@0x8000c300 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x0 0x8000c300 0x0 0x100>;
+		};
+
+		usb1: usb@0x8000c500 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x0 0x8000c500 0x0 0x100>;
+		};
+
+		usb_ohci0: usb_ohci@0x8000c400 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x0 0x8000c400 0x0 0x100>;
+		};
+
+		usb_ohci1: usb_ohci@0x8000c600 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x0 0x8000c600 0x0 0x100>;
+		};
+	};
+};
diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi
index 91f7787eb9..aaf1060640 100644
--- a/arch/arm/dts/bcm6858.dtsi
+++ b/arch/arm/dts/bcm6858.dtsi
@@ -10,6 +10,10 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		spi0 = &hsspi;
+	};
+
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
@@ -67,6 +71,15 @@
 			u-boot,dm-pre-reloc;
 		};
 
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <2>;
+			clock-div = <1>;
+			u-boot,dm-pre-reloc;			
+		};
+
 		refclk50mhz: refclk50mhz {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
@@ -74,6 +87,14 @@
 		};
 	};
 
+	boot_state {
+		u-boot,dm-pre-reloc;
+		compatible = "brcm,bcmbca-bootstate-v2";
+		reg-names = "reset_reason", "reset_status";
+		reg =   <0x00 0xff802624 0x00 0x04>,
+			<0x00 0xff802748 0x00 0x04>;
+		};
+
 	ubus {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -112,97 +133,95 @@
 			wdt = <&wdt1>;
 		};
 
-		gpio0: gpio-controller@0xff800500 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800500 0x0 0x4>,
-			      <0x0 0xff800520 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
-		};
+		hsspi: spi-controller@ff801000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			u-boot,dm-pre-reloc;
 
-		gpio1: gpio-controller@0xff800504 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800504 0x0 0x4>,
-			      <0x0 0xff800524 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
+			reg = <0x0 0xff801000 0x0 0x600>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <100000000>;
+			num-cs = <8>;
 
 			status = "disabled";
 		};
 
-		gpio2: gpio-controller@0xff800508 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800508 0x0 0x4>,
-			      <0x0 0xff800528 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.1",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0x0 0xff801800 0x0 0x400>,
+			      <0x0 0xff802000 0x0 0x10>,
+			      <0x0 0xff801c00 0x0 0x200>;
+			parameter-page-big-endian = <0>;
 
 			status = "disabled";
 		};
 
-		gpio3: gpio-controller@0xff80050c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff80050c 0x0 0x4>,
-			      <0x0 0xff80052c 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
+		sdhci: sdhci@ff858000 {
+			compatible = "brcm,bcm63xx-sdhci",
+			             "brcm,sdhci-brcmbca";
+			reg-names = "sdhci-base", "sdhci-boot";
+			reg = <0x0 0xff858000 0x0 0x100>,
+			      <0x0 0xff858200 0x0 0x40>;	
+			bus-width = <8>;
+			u-boot,dm-pre-reloc;
 		};
 
-		gpio4: gpio-controller@0xff800510 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800510 0x0 0x4>,
-			      <0x0 0xff800530 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0x0 0xff800b80 0x0 0x28>;
+			u-boot,dm-pre-reloc;
 		};
 
-		gpio5: gpio-controller@0xff800514 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800514 0x0 0x4>,
-			      <0x0 0xff800534 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			status = "disabled";
+		pinctrl: pinctrl {
+		    compatible = "brcm,bcmbca-pinctrl";
+		    reg = <0x0 0xff800554 0x0 0x14>;
+            gpio-mux = <5>;
 		};
 
-		gpio6: gpio-controller@0xff800518 {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff800518 0x0 0x4>,
-			      <0x0 0xff800538 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
+        gpioc: gpioc {
+			compatible = "brcm,bca-gpio";
+            gpio-controller;
+            #gpio-cells = <2>;
+            reg = <0x0 0xff800500 0x0 0x20>, <0x0 0xff800520 0x0 0x20>;
+            reg-names = "gpio-dir", "gpio-data";
+            ngpios = <118>;
+            gpio-ranges = <&pinctrl 0 0 118>;
+        };
 
-			status = "disabled";
+		usb_ctrl:usb_ctrl {
+		compatible = "brcm,bcmbca-usb-ctrl";
+		reg-names = "usb-ctrl";
+		reg = <0x0 0x8000c200 0x0 0x100>;
+		status = "okay";
 		};
 
-		gpio7: gpio-controller@0xff80051c {
-			compatible = "brcm,bcm6345-gpio";
-			reg = <0x0 0xff80051c 0x0 0x4>,
-			      <0x0 0xff80053c 0x0 0x4>;
-			gpio-controller;
-			#gpio-cells = <2>;
+		usb0: usb@8000c300 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x0 0x8000c300 0x0 0x100>;
+		};
 
-			status = "disabled";
+		usb1: usb@8000c500 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x0 0x8000c500 0x0 0x100>;
 		};
 
-		nand: nand-controller@ff801800 {
-			compatible = "brcm,nand-bcm6858",
-				     "brcm,brcmnand-v5.0",
-				     "brcm,brcmnand";
-			reg-names = "nand", "nand-int-base", "nand-cache";
-			reg = <0x0 0xff801800 0x0 0x180>,
-			      <0x0 0xff802000 0x0 0x10>,
-			      <0x0 0xff801c00 0x0 0x200>;
-			parameter-page-big-endian = <0>;
+		usb_ohci0: usb_ohci@8000c400 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x0 0x8000c400 0x0 0x100>;
+		};
 
-			status = "disabled";
+		usb_ohci1: usb_ohci@8000c600 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x0 0x8000c600 0x0 0x100>;
 		};
 	};
 };
diff --git a/arch/arm/dts/bcm947622.dts b/arch/arm/dts/bcm947622.dts
new file mode 100644
index 0000000000..1848389095
--- /dev/null
+++ b/arch/arm/dts/bcm947622.dts
@@ -0,0 +1,222 @@
+/dts-v1/;
+
+#include "bcm47622-pinctrl.dtsi"
+
+/ {
+	model = "Broadcom bcm947622";
+	compatible = "broadcom,bcm947622", "brcm,brcm-v7";
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+
+	aliases {
+		serial0 = &uart0;
+		spi1 = &hsspi;
+	};
+
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <1>;
+			clock-div = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	ubus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@ff812000 {	
+			u-boot,dm-pre-reloc;
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xff812000 0x1000>;
+			clock = <50000000>;
+			status = "okay";
+		};
+
+		wdt1: watchdog@ff800480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xff800480 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt2: watchdog@ff8004c0 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xff8004c0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+
+		hsspi: spi@ff801000 {
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			u-boot,dm-pre-reloc;
+			compatible = "brcm,bcm6328-hsspi";
+			reg = <0xff801000 0x600>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <100000000>;
+			num-cs = <0x8>;
+			cs-gpios = <0x0 0x0>;
+			status = "disabled";
+		};
+
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.1",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0xff801800 0x400>,
+			      <0xff802000 0x10>,
+			      <0xff801c00 0x200>;
+			parameter-page-big-endian = <0>;
+			status = "okay";
+			write-protect = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			nandcs@0 {
+				compatible = "brcm,nandcs";
+				reg = <0>;
+			};
+		};
+
+		sdhci: sdhci@ff810000 {
+			compatible = "brcm,bcm63xx-sdhci",
+			             "brcm,sdhci-brcmbca";
+			reg-names = "sdhci-base", "sdhci-boot";
+			reg = <0xff810000 0x100>,
+			      <0xff810200 0x40>;	
+			bus-width = <8>;
+			u-boot,dm-pre-reloc;
+		};
+
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0xff800b80 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+	sysport: systemport@0x80400000 {
+		compatible = "brcm,bcmbca-systemport-v2.0";
+		sphy-available=<0x01>;
+		reg-names =
+		"systemport-rbuf-base",
+		"systemport-rdma-base",
+		"systemport-tdma-base",
+		"systemport-umac-base",
+		"systemport-topctrl-base",
+		"systemport-switchmdio-base",
+		"sphy-ctrl",
+		"phy-test-ctrl";
+		reg =   <0x80400400 0x14>,
+			<0x80402000 0x1300>,
+			<0x80404000 0x8ff>,
+			<0x80400800 0x350>,
+			<0x80400000 0x40>,
+			<0x80411300 0x10>,
+			<0x804110c0 0x04>,
+			<0x804110bc 0x04>;
+		phy_base = <0x8>;
+		phy_wkard_timeout = <25000>;
+		};
+
+	boot_state {
+		u-boot,dm-pre-reloc;
+		compatible = "brcm,bcmbca-bootstate-v2";
+		reg-names = "reset_reason", "reset_status";
+		reg =   <0xff802628 0x04>,
+			<0xff85a03c 0x04>;
+		};
+
+		pinctrl: pinctrl {
+			compatible = "brcm,bcmbca-pinctrl";
+			reg = <0xff800554 0x14>;
+		};
+
+		usb_ctrl:usb_ctrl {
+		compatible = "brcm,bcmbca-usb-ctrl";
+		reg-names = "usb-ctrl";
+		reg = <0x8000c200 0x100>;
+		status = "okay";
+		};
+
+		usb0: usb@0x8000c300 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c300 0x100>;
+		status = "okay";
+		pinctrl-0 = <&usb0_pwr_pins>;
+		pinctrl-names="default";
+		};
+
+		usb1: usb@0x8000c500 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c500 0x100>;
+		status = "okay";
+		pinctrl-0 = <&usb1_pwr_pins>;
+		pinctrl-names="default";
+		};
+
+		usb_ohci0: usb_ohci@0x8000c400 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c400 0x100>;
+		};
+
+		usb_ohci1: usb_ohci@0x8000c600 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c600 0x100>;
+		};
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <100000000>;
+	};
+};
diff --git a/arch/arm/dts/bcm947622ref1sg.dts b/arch/arm/dts/bcm947622ref1sg.dts
new file mode 100644
index 0000000000..4bbbc24fd2
--- /dev/null
+++ b/arch/arm/dts/bcm947622ref1sg.dts
@@ -0,0 +1,228 @@
+
+/dts-v1/;
+
+#include "bcm47622-pinctrl.dtsi"
+
+/ {
+	model = "Broadcom bcm947622";
+	compatible = "broadcom,bcm947622" ,"bcmbrcm,brcm-v7";
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+
+	aliases {
+		serial0 = &uart0;
+		spi0 = &hsspi;
+	};
+
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x20000000>;
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <1>;
+			clock-div = <1>;
+		};
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	ubus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@ff812000 {	
+			u-boot,dm-pre-reloc;
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xff812000 0x1000>;
+			clock = <50000000>;
+			status = "okay";
+		};
+
+		wdt1: watchdog@ff800480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xff800480 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt2: watchdog@ff8004c0 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xff8004c0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+
+		hsspi: spi@ff801000 {
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			compatible = "brcm,bcm6328-hsspi";
+			reg = <0xff801000 0x600>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <67000000>;
+			num-cs = <0x8>;
+			cs-gpios = <0x0 0x0>;
+			status = "okay";
+		};
+
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.1",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0xff801800 0x400>,
+			      <0xff802000 0x10>,
+			      <0xff801c00 0x200>;
+			parameter-page-big-endian = <0>;
+			status = "okay";
+			write-protect = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			nandcs@0 {
+				compatible = "brcm,nandcs";
+				reg = <0>;
+				nand-ecc-strength = <4>;
+				nand-ecc-step-size = <512>;
+				brcm,nand-oob-sector-size = <16>;
+			};
+		};
+
+		sdhci: sdhci@ff810000 {
+			compatible = "brcm,bcm63xx-sdhci",
+			             "brcm,sdhci-brcmbca";
+			reg-names = "sdhci-base", "sdhci-boot";
+			reg = <0xff810000 0x100>,
+			      <0xff810200 0x40>;	
+			bus-width = <8>;
+			u-boot,dm-pre-reloc;
+		};
+	sysport: systemport@0x80400000 {
+		compatible = "brcm,bcmbca-systemport-v2.0";
+		sphy-available=<0x01>;
+		reg-names =
+		"systemport-rbuf-base",
+		"systemport-rdma-base",
+		"systemport-tdma-base",
+		"systemport-umac-base",
+		"systemport-topctrl-base",
+		"systemport1-rbuf-base",
+		"systemport1-rdma-base",
+		"systemport1-tdma-base",
+		"systemport1-umac-base",
+		"systemport1-topctrl-base",
+		"systemport-switchmdio-base",
+		"sphy-ctrl",
+		"phy-test-ctrl";
+		reg =   <0x80400400 0x14>,
+			<0x80402000 0x1300>,
+			<0x80404000 0x8ff>,
+			<0x80400800 0x350>,
+			<0x80400000 0x40>,
+		    <0x80500400 0x14>,
+			<0x80502000 0x1300>,
+			<0x80504000 0x8ff>,
+			<0x80500800 0x350>,
+			<0x80500000 0x40>,
+			<0x80411300 0x10>,
+			<0x804110c0 0x04>,
+			<0x804110bc 0x04>;
+		phy_base = <0x8>;
+		phy_wkard_timeout = <25000>;
+		ethsw = <&switch_ext>;
+		};
+
+	switch_ext:switch_ext {
+		compatible = "brcm,bcmbca-extsw";
+		pinctrl-0 = <&xmii_1_pins>;
+		pinctrl-names="default";
+		reg-names ="systemport-serdes-cntrl";
+		reg = <0x804110a8 0x8>;
+		extswsgmii_addr = <0x6>;
+	};
+
+	pinctrl: pinctrl {
+		compatible = "brcm,bcmbca-pinctrl";
+		reg = <0xff800554 0x14>;
+		};
+
+	boot_state {
+		u-boot,dm-pre-reloc;
+		compatible = "brcm,bcmbca-bootstate-v2";
+		reg-names = "reset_reason", "reset_status";
+		reg =   <0x00 0xff802628 0x00 0x04>,
+			<0x00 0xff85a03c 0x00 0x04>;
+		};
+
+	usb_ctrl:usb_ctrl {
+		compatible = "brcm,bcmbca-usb-ctrl";
+		reg-names = "usb-ctrl";
+		reg = <0x8000c200 0x100>;
+		pwron-bias-pull-up;
+		status = "okay";
+		};
+
+	usb0: usb@0x8000c300 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c300 0x100>;
+		status = "okay";
+		pinctrl-0 = <&usb0_pwr_pins>;
+		pinctrl-names="default";
+		};
+
+	usb1: usb@0x8000c500 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c500 0x100>;
+		status = "okay";
+		pinctrl-0 = <&usb1_pwr_pins>;
+		pinctrl-names="default";
+		};
+
+	usb_ohci0: usb_ohci@0x8000c400 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c400 0x100>;
+		};
+
+	usb_ohci1: usb_ohci@0x8000c600 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c600 0x100>;
+		};
+	};
+
+};
diff --git a/arch/arm/dts/bcm94908.dts b/arch/arm/dts/bcm94908.dts
new file mode 100644
index 0000000000..41f27169fb
--- /dev/null
+++ b/arch/arm/dts/bcm94908.dts
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+/dts-v1/;
+
+#include "bcm4908.dtsi"
+
+/ {
+	model = "Broadcom bcm94908";
+	compatible = "broadcom,bcm94908", "brcm,bcm4908";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&nand {
+	status = "okay";
+	write-protect = <0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <100000000>;
+	};
+};
+
+&leds {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	brcm,serial-led-en-pol;
+	brcm,serial-led-data-ppol;
+
+	led@16 {
+		reg = <16>;
+		label = "red:dsl2";
+	};
+
+	led@17 {
+		reg = <17>;
+		label = "green:dsl1";
+	};
+
+	led@18 {
+		reg = <18>;
+		label = "green:fxs2";
+	};
+
+	led@19 {
+		reg = <19>;
+		label = "green:fxs1";
+	};
+
+	led@26 {
+		reg = <26>;
+		label = "green:wan1_act";
+	};
+
+	led@27 {
+		reg = <27>;
+		label = "green:wps";
+	};
+
+	led@28 {
+		reg = <28>;
+		active-low;
+		label = "green:aggregate_act";
+	};
+
+	led@29 {
+		reg = <29>;
+		label = "green:aggregate_link";
+	};
+};
+
+&usb0 {
+	status = "okay";
+	pinctrl-0 = <&usb0a_pwrflt_pins &usb0a_pwron_pins>;
+	pinctrl-names="default";
+};
+
+&switchsf2 {
+	status = "okay";
+	phy_base = <0x8>;
+	ports {
+		port0@0 {
+			phy-handle = <&gphy8>;
+		};
+		port1@1 {
+			phy-handle = <&gphy9>;
+		};
+		port2@2 {
+			phy-handle = <&gphya>;
+		};
+		port3@3 {
+			phy-handle = <&gphyb>;
+		};
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		spi-max-frequency = <50000000>;
+		u-boot,dm-pre-reloc;
+	};
+};
+
diff --git a/arch/arm/dts/bcm94912.dts b/arch/arm/dts/bcm94912.dts
new file mode 100644
index 0000000000..cee5b94cad
--- /dev/null
+++ b/arch/arm/dts/bcm94912.dts
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm4912.dtsi"
+
+/ {
+	model = "Broadcom bcm94912";
+	compatible = "broadcom,bcm94912", "brcm,bcm4912";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x08000000>;
+	};
+	boot_state {
+		u-boot,dm-pre-reloc;
+		compatible = "brcm,bcmbca-bootstate-v2";
+		reg-names = "reset_reason", "reset_status";
+		reg =   <0x0 0xff802628 0x0 0x04>,
+			<0x0 0xff85a01c 0x0 0x04>;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <100000000>;
+	};
+};
+
+&nand {
+	status = "okay";
+	write-protect = <1>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+	};
+};
+
+/* FIXME!
+&rgmii {
+	status = "okay";
+};
+*/
+
+&mdio {
+	phy1:1 {
+		status = "okay";
+	};
+
+	phy2:2 {
+		status = "okay";
+	};
+
+	phy3:3 {
+		status = "okay";
+	};
+
+	phy4:4 {
+		status = "okay";
+	};
+
+	/* FIXME
+	phy_rgmii: phy_rgmii {
+		reg = <7>;
+		tx-delay;
+		status = "okay";
+	};
+
+	phy_ext_serdes: ext_serdes {
+		reg = <0x1e>;
+		phy-type = "EXT1";
+		enet-phy-lane-swap;
+		status = "okay";
+	};
+
+	phy_serdes: serdes {
+		phy-handle = <&phy_ext_serdes>;
+		status = "okay";
+	}; */
+};
+
+&switch0 {
+	ports {
+		port0@0 {
+			status = "okay";
+		};
+
+		port1@1 {
+			status = "okay";
+		};
+
+		port2@2 {
+			status = "okay";
+		};
+
+		port3@3 {
+			status = "okay";
+		};
+	};
+};
+
diff --git a/arch/arm/dts/bcm963138.dts b/arch/arm/dts/bcm963138.dts
new file mode 100644
index 0000000000..7969880102
--- /dev/null
+++ b/arch/arm/dts/bcm963138.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+
+/dts-v1/;
+
+#include "bcm63138.dtsi"
+
+/ {
+	model = "Broadcom bcm963138";
+	compatible = "broadcom,bcm963138", "brcm,bcm963138";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		tick-timer = &timer0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&timer0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&nand {
+	status = "okay";
+	write-protect = <0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <100000000>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+	pinctrl-0 = <&usb0a_pwrflt_pins &usb0a_pwron_pins>;
+	pinctrl-names = "default";
+};
+
+&switchsf2 {
+	status = "okay";
+	phy_base = <0x8>;
+	ports {
+		port0@0 {
+			phy-handle = <&gphy8>;
+		};
+		port1@1 {
+			phy-handle = <&gphy9>;
+		};
+		port2@2 {
+			phy-handle = <&gphya>;
+		};
+		port3@3 {
+			phy-handle = <&gphyb>;
+		};
+	};
+};
+
diff --git a/arch/arm/dts/bcm963146.dts b/arch/arm/dts/bcm963146.dts
new file mode 100644
index 0000000000..bc81d1dff2
--- /dev/null
+++ b/arch/arm/dts/bcm963146.dts
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+/dts-v1/;
+
+#include "bcm63146.dtsi"
+
+/ {
+	model = "Broadcom bcm963146";
+	compatible = "broadcom,bcm963146", "brcm,bcm63146";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x08000000>;
+	};
+
+	boot_state {
+		u-boot,dm-pre-reloc;
+		compatible = "brcm,bcmbca-bootstate-v2";
+		reg-names = "reset_reason", "reset_status";
+		reg =   <0x0 0xff802628 0x0 0x04>,
+			<0x0 0xff85a01c 0x0 0x04>;
+	};
+
+
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <100000000>;
+	};
+};
+
+&nand {
+	status = "okay";
+	write-protect = <1>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+	};
+};
+
+/* FIXME!
+&rgmii {
+	status = "okay";
+};
+*/
+
+&mdio {
+	phy1:1 {
+		status = "okay";
+	};
+
+	phy2:2 {
+		status = "okay";
+	};
+
+	phy3:3 {
+		status = "okay";
+	};
+
+	phy4:4 {
+		status = "okay";
+	};
+
+	phy5:5 {
+		status = "okay";
+	};
+
+	/* FIXME
+	phy_rgmii: phy_rgmii {
+		tx-delay;
+		status = "okay";
+	};
+
+	phy_ext_serdes: ext_serdes {
+		reg = <0x1e>;
+		phy-type = "EXT1";
+		enet-phy-lane-swap;
+		status = "okay";
+	};
+
+	phy_serdes: serdes {
+		phy-handle = <&phy_ext_serdes>;
+		status = "okay";
+	}; */
+};
+
+&switch0 {
+	ports {
+		port0@0 {
+			status = "okay";
+		};
+
+		port1@1 {
+			status = "okay";
+		};
+
+		port2@2 {
+			status = "okay";
+		};
+
+		port3@3 {
+			status = "okay";
+		};
+
+		port4@4 {
+			status = "okay";
+		};
+
+/* FIXME
+		port5@5 {
+			status = "okay";
+		};
+*/
+	};
+};
+
diff --git a/arch/arm/dts/bcm963148.dts b/arch/arm/dts/bcm963148.dts
new file mode 100644
index 0000000000..0990da7e0f
--- /dev/null
+++ b/arch/arm/dts/bcm963148.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+
+/dts-v1/;
+
+#include "bcm63148.dtsi"
+
+/ {
+	model = "Broadcom bcm963148";
+	compatible = "broadcom,bcm963148", "brcm,bcm963148";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		tick-timer = &timer0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&timer0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&nand {
+	status = "okay";
+	write-protect = <0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+	};
+};
+
+/* usb0 {
+	status = "okay";
+	pinctrl-0 = <&usb0a_pwrflt_pins &usb0a_pwron_pins>;
+	pinctrl-names = "default";
+}; */
+
+&switchsf2 {
+	status = "okay";
+	phy_base = <0x8>;
+	ports {
+		port0@0 {
+			phy-handle = <&gphy8>;
+		};
+		port1@1 {
+			phy-handle = <&gphy9>;
+		};
+		port2@2 {
+			phy-handle = <&gphya>;
+		};
+		port3@3 {
+			phy-handle = <&gphyb>;
+		};
+	};
+};
+
diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts
index 85659440da..f1a6adc585 100644
--- a/arch/arm/dts/bcm963158.dts
+++ b/arch/arm/dts/bcm963158.dts
@@ -21,7 +21,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x40000000>;
+		reg = <0x0 0x0 0x0 0x08000000>;
 	};
 };
 
@@ -30,38 +30,6 @@
 	status = "okay";
 };
 
-&gpio0 {
-	status = "okay";
-};
-
-&gpio1 {
-	status = "okay";
-};
-
-&gpio2 {
-	status = "okay";
-};
-
-&gpio3 {
-	status = "okay";
-};
-
-&gpio4 {
-	status = "okay";
-};
-
-&gpio5 {
-	status = "okay";
-};
-
-&gpio6 {
-	status = "okay";
-};
-
-&gpio7 {
-	status = "okay";
-};
-
 &nand {
 	status = "okay";
 	write-protect = <0>;
@@ -71,9 +39,18 @@
 	nandcs@0 {
 		compatible = "brcm,nandcs";
 		reg = <0>;
-		nand-ecc-strength = <4>;
-		nand-ecc-step-size = <512>;
-		brcm,nand-oob-sector-size = <16>;
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <100000000>;
 	};
 };
 
@@ -125,3 +102,34 @@
 		label = "green:aggregate_link";
 	};
 };
+
+&usb0 {
+	status = "okay";
+	pinctrl-0 = <&usb0a_pwrflt_pins &usb0a_pwron_pins>;
+	pinctrl-names="default";
+};
+
+&usb1 {
+	status = "okay";
+	pinctrl-0 = <&usb1a_pwrflt_pins &usb1a_pwron_pins>;
+	pinctrl-names="default";
+};
+
+&switchsf2 {
+	status = "okay";
+	phy_base = <0x8>;
+	ports {
+		port0@0 {
+			phy-handle = <&gphy8>;
+		};
+		port1@1 {
+			phy-handle = <&gphy9>;
+		};
+		port2@2 {
+			phy-handle = <&gphya>;
+		};
+		port3@3 {
+			phy-handle = <&gphyb>;
+		};
+	};
+};
diff --git a/arch/arm/dts/bcm963178.dts b/arch/arm/dts/bcm963178.dts
new file mode 100644
index 0000000000..aba154cd0d
--- /dev/null
+++ b/arch/arm/dts/bcm963178.dts
@@ -0,0 +1,252 @@
+/dts-v1/;
+
+#include "bcmbca-sf2net.dtsi"
+#include "bcm63178-pinctrl.dtsi"
+
+/ {
+	model = "Broadcom bcm963178";
+	compatible = "broadcom,bcm963178", "brcm,brcm-v7";
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+
+	aliases {
+		serial0 = &uart0;
+		spi1 = &hsspi;
+	};
+
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <1>;
+			clock-div = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	ubus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		u-boot,dm-pre-reloc;
+
+		hsspi: hsspi@ff801000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			u-boot,dm-pre-reloc;
+			
+			reg = <0xff801000 0x1000>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <100000000>;
+			num-cs = <8>;
+			status = "okay";
+		};
+
+		uart0: serial@ff812000 {
+			u-boot,dm-pre-reloc;
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xff812000 0x1000>;
+			clock = <50000000>;
+			status = "okay";
+		};
+
+		wdt1: watchdog@ff800480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xff800480 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt2: watchdog@ff8004c0 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xff8004c0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.1",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0xff801800 0x400>,
+			      <0xff802000 0x10>,
+			      <0xff801c00 0x200>;
+			parameter-page-big-endian = <0>;
+			status = "okay";
+			write-protect = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			nandcs@0 {
+				compatible = "brcm,nandcs";
+				reg = <0>;
+			};
+		};
+
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0xff800b80 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+		sysport: systemport@0x80490000 {
+		compatible = "brcm,bcmbca-systemport-v2.0";
+		qphy-avaiable=<0x01>;
+		sphy-available=<0x01>;
+		reg-names = "systemport-rbuf-base", "systemport-rdma-base",
+				"systemport-tdma-base",
+				"systemport-gib-base",
+				"systemport-umac-base",
+				"systemport-topctrl-base";
+		reg =		<0x80490400 0x14>,
+				<0x80492000 0x1060>,
+				<0x80494000 0x650>,
+				<0x80498000 0x10>,
+				<0x00000000 0x00>,  
+				<0x80490000 0x10>;
+		ethsw = <&switchsf2>;
+		};
+
+		switchsf2: sf2@80400000 {
+		compatible = "brcm,bcmbca-sf2";
+		phy_base = <0x8>;
+		phy_wkard_timeout = <25000>;
+		reg-names = "switchcore-base",
+					"switchreg-base",
+					"switchmdio-base",
+					"qphy-ctrl",
+					"sphy-ctrl",
+					"phy-test-ctrl";
+
+		reg = <0x80400000 0x72724>,
+			<0x80480000 0x458>,
+			<0x804805c0 0x10>,
+			<0x8048001c 0x04>,
+			<0x80480024 0x04>,
+			<0x80480018 0x04>;
+			ports {
+				port0@0 {
+					phy-handle = <&gphy8>;
+				};
+				port1@1 {
+					phy-handle = <&gphy9>;
+				};
+				port2@2 {
+					phy-handle = <&gphya>;
+				};
+				port3@3 {
+					phy-handle = <&gphyb>;
+				};
+			};
+		};
+		boot_state {
+			u-boot,dm-pre-reloc;
+			compatible = "brcm,bcmbca-bootstate-v2";
+			reg-names = "reset_reason", "reset_status";
+			reg =   <0xff802628 0x04>,
+				<0xff85a03c 0x04>;
+		};
+
+		pinctrl: pinctrl {
+			compatible = "brcm,bcmbca-pinctrl";
+			reg = <0xff800554 0x14>;
+		};
+
+		usb_ctrl:usb_ctrl {
+		compatible = "brcm,bcmbca-usb-ctrl";
+		reg-names = "usb-ctrl";
+		reg = <0x8000c200 0x100>;
+		status = "okay";
+		};
+
+		usb0: usb@0x8000c300 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c300 0x100>;
+		status = "okay";
+		pinctrl-0 = <&usb0_pwr_pins>;
+		pinctrl-names="default";
+		};
+
+		usb1: usb@0x8000c500 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c500 0x100>;
+		status = "okay";
+		pinctrl-0 = <&usb1_pwr_pins>;
+		pinctrl-names="default";
+		};
+
+		usb_ohci0: usb_ohci@0x8000c400 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c400 0x100>;
+		};
+
+		usb_ohci1: usb_ohci@0x8000c600 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c600 0x100>;
+		};
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <100000000>;
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		spi-max-frequency = <50000000>;
+		u-boot,dm-pre-reloc;
+	};
+};
+
+
diff --git a/arch/arm/dts/bcm96756.dts b/arch/arm/dts/bcm96756.dts
new file mode 100644
index 0000000000..6ea73d6be8
--- /dev/null
+++ b/arch/arm/dts/bcm96756.dts
@@ -0,0 +1,236 @@
+/dts-v1/;
+
+#include "bcmbca-sf2net.dtsi"
+#include "bcm6756-pinctrl.dtsi"
+
+/ {
+	model = "Broadcom bcm96756";
+	compatible = "broadcom,bcm96756", "brcm,brcm-v7";
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+
+	aliases {
+		serial0 = &uart0;
+		spi1 = &hsspi;
+	};
+
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <1>;
+			clock-div = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	ubus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@ff812000 {	
+			u-boot,dm-pre-reloc;
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xff812000 0x1000>;
+			clock = <50000000>;
+			status = "okay";
+		};
+
+		wdt1: watchdog@ff800480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xff800480 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt2: watchdog@ff8004c0 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xff8004c0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+
+		hsspi: spi@ff801000 {
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			u-boot,dm-pre-reloc;
+			compatible = "brcm,bcm6328-hsspi";
+			reg = <0xff801000 0x600>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <100000000>;
+			num-cs = <0x8>;
+			cs-gpios = <0x0 0x0>;
+			status = "disabled";
+		};
+
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca",
+				     "brcm,brcmnand-v7.1",
+				     "brcm,brcmnand";
+			reg-names = "nand", "nand-int-base", "nand-cache";
+			reg = <0xff801800 0x400>,
+			      <0xff802000 0x10>,
+			      <0xff801c00 0x200>;
+			parameter-page-big-endian = <0>;
+			status = "okay";
+			write-protect = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			nandcs@0 {
+				compatible = "brcm,nandcs";
+				reg = <0>;
+			};
+		};
+
+		sdhci: sdhci@ff810000 {
+			compatible = "brcm,bcm63xx-sdhci",
+			             "brcm,sdhci-brcmbca";
+			reg-names = "sdhci-base", "sdhci-boot";
+			reg = <0xff810000 0x100>,
+			      <0xff810200 0x40>;	
+			bus-width = <8>;
+			u-boot,dm-pre-reloc;
+		};
+
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0xff800b80 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+		sysport: systemport@0x80490000 {
+		compatible = "brcm,bcmbca-systemport-v2.0";
+		reg-names = "systemport-rbuf-base", "systemport-rdma-base",
+				"systemport-tdma-base",
+				"systemport-gib-base",
+				"systemport-umac-base",
+				"systemport-topctrl-base";
+		reg =		<0x80490400 0x14>,
+				<0x80492000 0x1258>,
+				<0x80494000 0x9ac>,
+				<0x80498000 0x18>,
+				<0x00000000 0x00>,  
+				<0x80490000 0x34>;
+		ethsw = <&switchsf2>;
+		};
+
+		switchsf2: sf2@80400000 {
+		compatible = "brcm,bcmbca-sf2";
+		phy_base = <0x8>;
+		phy_wkard_timeout = <25000>;
+		reg-names = "switchcore-base",
+					"switchreg-base",
+					"switchmdio-base",
+					"sphy-ctrl",
+					"phy-test-ctrl";
+
+		reg = <0x80400000 0x72724>,
+			<0x80480000 0x444>,
+			<0x804805c0 0x10>,
+			<0x80480024 0x04>,
+			<0x80480018 0x04>;
+			ports {
+				port0@0 {
+					phy-handle = <&phy_ge>;
+				};
+			};
+		};		
+		boot_state {
+		u-boot,dm-pre-reloc;
+		compatible = "brcm,bcmbca-bootstate-v2";
+		reg-names = "reset_reason", "reset_status";
+		reg =   <0xff802628 0x04>,
+			<0xff85a03c 0x04>;
+		};
+
+		pinctrl: pinctrl {
+			compatible = "brcm,bcmbca-pinctrl";
+			reg = <0xff800554 0x14>;
+		};
+
+		usb_ctrl:usb_ctrl {
+		compatible = "brcm,bcmbca-usb-ctrl";
+		reg-names = "usb-ctrl";
+		reg = <0x8000c200 0x100>;
+		status = "okay";
+		};
+
+		usb0: usb@0x8000c300 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c300 0x100>;
+		status = "okay";
+		pinctrl-0 = <&usb0_pwr_pins>;
+		pinctrl-names="default";
+		};
+
+		usb1: usb@0x8000c500 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c500 0x100>;
+		status = "okay";
+		pinctrl-0 = <&usb1_pwr_pins>;
+		pinctrl-names="default";
+		};
+
+		usb_ohci0: usb_ohci@0x8000c400 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c400 0x100>;
+		};
+
+		usb_ohci1: usb_ohci@0x8000c600 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c600 0x100>;
+		};
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <100000000>;
+	};
+};
diff --git a/arch/arm/dts/bcm96846.dts b/arch/arm/dts/bcm96846.dts
new file mode 100644
index 0000000000..3b402cb9a1
--- /dev/null
+++ b/arch/arm/dts/bcm96846.dts
@@ -0,0 +1,245 @@
+/dts-v1/;
+
+
+
+/ {
+	model = "Broadcom-v7";
+	compatible = "brcm,brcm-v7";
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+    memory {
+        device_type = "memory";
+        reg = <0x0 0x08000000>;
+    };
+
+    boot_state {
+        u-boot,dm-pre-reloc;
+        compatible = "brcm,bcmbca-bootstate-v2";
+        reg-names = "reset_reason", "reset_status";
+        reg =   <0xff80263c 0x04>,
+            <0xff85a03c 0x04>;
+    };
+
+    clocks {
+        compatible = "simple-bus";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        u-boot,dm-pre-reloc;
+
+        periph_osc: periph-osc {
+            compatible = "fixed-clock";
+            #clock-cells = <0>;
+            clock-frequency = <200000000>;
+            u-boot,dm-pre-reloc;
+        };
+
+        refclk50mhz: refclk50mhz {
+            compatible = "fixed-clock";
+            #clock-cells = <0>;
+            clock-frequency = <50000000>;
+        };
+
+	hsspi_pll: hsspi-pll {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&periph_osc>;
+		clock-mult = <2>;
+		clock-div = <1>;
+		u-boot,dm-pre-reloc;
+	};
+    };
+
+	ubus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@ff800640 {
+		    compatible = "brcm,bcm6345-uart";
+		    reg = <0xff800640 0x18>;
+		    clocks = <&periph_osc>;
+		    status = "disabled";
+		};
+
+		wdt1: watchdog@ff802780 {
+		    compatible = "brcm,bcm6345-wdt";
+		    reg = <0xff800480 0x14>;
+		    clocks = <&refclk50mhz>;
+		};
+
+		wdt2: watchdog@ff8027c0 {
+		    compatible = "brcm,bcm6345-wdt";
+		    reg = <0xff8004c0 0x14>;
+		    clocks = <&refclk50mhz>;
+		};
+
+
+		wdt-reboot {
+		    compatible = "wdt-reboot";
+		    wdt = <&wdt1>;
+		};
+
+		hsspi: hsspi@ff801000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			u-boot,dm-pre-reloc;
+			
+			reg = <0x0 0xff801000 0x0 0x1000>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <67000000>;
+			num-cs = <8>;
+			status = "disabled";
+		};
+		
+
+		nand: nand-controller@ff801800 {
+		    compatible = "brcm,nand-bcmbca", "brcm,brcmnand-v7.1";
+		    reg-names = "nand", "nand-int-base";
+		    reg = <0xff801800 0x600>, <0xff802000 0x10>;
+		    parameter-page-big-endian = <0>;
+		    status = "disabled";
+		}; 
+
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0xff800b80 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+
+		pinctrl: pinctrl {
+		compatible = "brcm,bcmbca-pinctrl";
+		reg = <0xff800554 0x14>;
+        gpio-mux = <4>;
+		};
+
+        gpioc: gpioc {
+			compatible = "brcm,bca-gpio";
+            gpio-controller;
+            #gpio-cells = <2>;
+            reg = <0x0 0xff800500 0x0 0x20>, <0x0 0xff800520 0x0 0x20>;
+            reg-names = "gpio-dir", "gpio-data";
+            ngpios = <79>;
+            gpio-ranges = <&pinctrl 0 0 79>;
+        };
+
+		usb_ctrl:usb_ctrl {
+		compatible = "brcm,bcmbca-usb-ctrl";
+		reg-names = "usb-ctrl";
+		reg = <0x8000c200 0x100>;
+		status = "okay";
+		};
+
+		usb0: usb@0x8000c300 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c300 0x100>;
+		};
+
+		usb1: usb@0x8000c500 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c500 0x100>;
+		};
+
+		usb_ohci0: usb_ohci@0x8000c400 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c400 0x100>;
+		};
+
+		usb_ohci1: usb_ohci@0x8000c600 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c600 0x100>;
+		};
+	}; 
+};
+
+&uart0 {
+    u-boot,dm-pre-reloc;
+    status = "okay";
+};
+
+&nand {
+    status = "okay";
+    write-protect = <0>;
+    #address-cells = <1>;
+    #size-cells = <0>;
+
+    nandcs@0 {
+        compatible = "brcm,nandcs";
+        reg = <0>;
+    };
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <67000000>;
+	};
+};
+
+/* &hsspi {
+	status = "okay";
+	spi-flash@0 {
+		compatible = "spi-flash";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <20000000>;
+	};
+}; */
+
+/* pinmux */
+/ {
+	usb0a_pwrflt_pins: usb0a_pwrflt_pinmux {
+	    pins = <74>;
+	    function = <1>;
+	};
+
+	usb0a_pwron_pins: usb0a_pwron_pinmux {
+	    pins = <75>;
+	    function = <1>;
+	};
+
+	usb1a_pwrflt_pins: usb1a_pwrflt_pinmux {
+	    pins = <76>;
+	    function = <1>;
+	};
+
+	usb1a_pwron_pins: usb1a_pwron_pinmux {
+	    pins = <77>;
+	    function = <1>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+	pinctrl-0 = <&usb0a_pwrflt_pins &usb0a_pwron_pins>;
+	pinctrl-names="default";
+};
+
+&usb1 {
+	status = "okay";
+	pinctrl-0 = <&usb1a_pwrflt_pins &usb1a_pwron_pins>;
+	pinctrl-names="default";
+};
diff --git a/arch/arm/dts/bcm96855.dts b/arch/arm/dts/bcm96855.dts
new file mode 100644
index 0000000000..5af36e30e5
--- /dev/null
+++ b/arch/arm/dts/bcm96855.dts
@@ -0,0 +1,136 @@
+/dts-v1/;
+
+
+
+/ {
+	model = "Broadcom-v7";
+	compatible = "brcm,brcm-v7";
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+
+    boot_state {
+        u-boot,dm-pre-reloc;
+        compatible = "brcm,bcmbca-bootstate-v2";
+        reg-names = "reset_reason", "reset_status";
+        reg =   <0xff802628 0x04>,
+            <0xff85a018 0x04>;
+    };
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <1>;
+			clock-div = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	ubus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@ff812000 {
+			u-boot,dm-pre-reloc;
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xff812000 0x1000>;
+			clock = <50000000>;
+			status = "okay";
+		};
+
+		hsspi: hsspi@ff801000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			u-boot,dm-pre-reloc;
+			
+			reg = <0xff801000 0x1000>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <50000000>;
+			num-cs = <8>;
+			status = "disabled";
+		};
+
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca", "brcm,brcmnand-v7.1";
+			reg-names = "nand", "nand-int-base";
+			reg = <0xff801800 0x600>, <0xff802000 0x10>;
+			parameter-page-big-endian = <0>;
+			status = "disabled";
+		};
+
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0xff800b80 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+
+		pinctrl: pinctrl {
+		compatible = "brcm,bcmbca-pinctrl";
+		reg = <0xff800554 0x14>;
+		};
+	}; 
+};
+
+&nand {
+	status = "okay";
+	write-protect = <0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <50000000>;
+	};
+};
+
+
diff --git a/arch/arm/dts/bcm96856.dts b/arch/arm/dts/bcm96856.dts
new file mode 100644
index 0000000000..90f9d0c904
--- /dev/null
+++ b/arch/arm/dts/bcm96856.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ *
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6856.dtsi"
+
+/ {
+	model = "Broadcom bcm96856";
+	compatible = "broadcom,bcm96856", "brcm,bcm6856";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&nand {
+	status = "okay";
+	write-protect = <0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <100000000>;
+	};
+};
+
+&leds {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	brcm,serial-led-en-pol;
+	brcm,serial-led-data-ppol;
+
+	led@2 {
+		reg = <2>;
+		label = "green:inet";
+	};
+
+	led@5 {
+		reg = <5>;
+		label = "red:alarm";
+	};
+
+	led@8 {
+		reg = <8>;
+		label = "green:wlan_link";
+	};
+
+	led@11 {
+		reg = <11>;
+		label = "green:fxs1";
+	};
+
+	led@14 {
+		reg = <14>;
+		label = "green:fxs2";
+	};
+
+	led@15 {
+		reg = <15>;
+		label = "green:usb0";
+	};
+
+	led@16 {
+		reg = <16>;
+		label = "green:usb1";
+	};
+
+	led@17 {
+		reg = <17>;
+		label = "green:wps";
+	};
+};
+
+/* pinmux */
+/ {
+	usb0a_pwrflt_pins: usb0a_pwrflt_pinmux {
+	    pins = <76>;
+	    function = <1>;
+	};
+
+	usb0a_pwron_pins: usb0a_pwron_pinmux {
+	    pins = <77>;
+	    function = <1>;
+	};
+
+	usb1a_pwrflt_pins: usb1a_pwrflt_pinmux {
+	    pins = <78>;
+	    function = <1>;
+	};
+
+	usb1a_pwron_pins: usb1a_pwron_pinmux {
+	    pins = <79>;
+	    function = <1>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+	pinctrl-0 = <&usb0a_pwrflt_pins &usb0a_pwron_pins>;
+	pinctrl-names="default";
+};
+
+&usb1 {
+	status = "okay";
+	pinctrl-0 = <&usb1a_pwrflt_pins &usb1a_pwron_pins>;
+	pinctrl-names="default";
+};
diff --git a/arch/arm/dts/bcm96858.dts b/arch/arm/dts/bcm96858.dts
new file mode 100644
index 0000000000..3909317f14
--- /dev/null
+++ b/arch/arm/dts/bcm96858.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ *
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6858.dtsi"
+
+/ {
+	model = "Broadcom bcm96858";
+	compatible = "broadcom,bcm96858", "brcm,bcm6858";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x08000000>;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
+
+&nand {
+	status = "okay";
+	write-protect = <0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <100000000>;
+	};
+};
+
+&leds {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	brcm,serial-led-en-pol;
+	brcm,serial-led-data-ppol;
+
+	led@2 {
+		reg = <2>;
+		label = "green:inet";
+	};
+
+	led@5 {
+		reg = <5>;
+		label = "red:alarm";
+	};
+
+	led@8 {
+		reg = <8>;
+		label = "green:wlan_link";
+	};
+
+	led@11 {
+		reg = <11>;
+		label = "green:fxs1";
+	};
+
+	led@14 {
+		reg = <14>;
+		label = "green:fxs2";
+	};
+
+	led@15 {
+		reg = <15>;
+		label = "green:usb0";
+	};
+
+	led@16 {
+		reg = <16>;
+		label = "green:usb1";
+	};
+
+	led@17 {
+		reg = <17>;
+		label = "green:wps";
+	};
+};
+
+/* pinmux */
+/ {
+	usb0a_pwrflt_pins: usb0a_pwrflt_pinmux {
+	    pins = <113>;
+	    function = <1>;
+	};
+
+	usb0a_pwron_pins: usb0a_pwron_pinmux {
+	    pins = <114>;
+	    function = <1>;
+	};
+
+	usb1a_pwrflt_pins: usb1a_pwrflt_pinmux {
+	    pins = <115>;
+	    function = <1>;
+	};
+
+	usb1a_pwron_pins: usb1a_pwron_pinmux {
+	    pins = <116>;
+	    function = <1>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+	pinctrl-0 = <&usb0a_pwrflt_pins &usb0a_pwron_pins>;
+	pinctrl-names="default";
+};
+
+&usb1 {
+	status = "okay";
+	pinctrl-0 = <&usb1a_pwrflt_pins &usb1a_pwron_pins>;
+	pinctrl-names="default";
+};
diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts
index 861e9891a7..54ffba315d 100644
--- a/arch/arm/dts/bcm968580xref.dts
+++ b/arch/arm/dts/bcm968580xref.dts
@@ -30,38 +30,6 @@
 	status = "okay";
 };
 
-&gpio0 {
-	status = "okay";
-};
-
-&gpio1 {
-	status = "okay";
-};
-
-&gpio2 {
-	status = "okay";
-};
-
-&gpio3 {
-	status = "okay";
-};
-
-&gpio4 {
-	status = "okay";
-};
-
-&gpio5 {
-	status = "okay";
-};
-
-&gpio6 {
-	status = "okay";
-};
-
-&gpio7 {
-	status = "okay";
-};
-
 &nand {
 	status = "okay";
 	write-protect = <0>;
@@ -124,3 +92,15 @@
 		label = "green:wps";
 	};
 };
+
+&hsspi {
+	status = "okay";
+
+	flash: mt25@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+	};
+};
diff --git a/arch/arm/dts/bcm96878.dts b/arch/arm/dts/bcm96878.dts
new file mode 100644
index 0000000000..81990c6c80
--- /dev/null
+++ b/arch/arm/dts/bcm96878.dts
@@ -0,0 +1,229 @@
+/dts-v1/;
+
+
+
+/ {
+	model = "Broadcom-v7";
+	compatible = "brcm,brcm-v7";
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x08000000>;
+	};
+
+    boot_state {
+        u-boot,dm-pre-reloc;
+        compatible = "brcm,bcmbca-bootstate-v2";
+        reg-names = "reset_reason", "reset_status";
+        reg =   <0xff802628 0x04>,
+            <0xff85a03c 0x04>;
+    };
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <200000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		hsspi_pll: hsspi-pll {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clocks = <&periph_osc>;
+			clock-mult = <1>;
+			clock-div = <1>;
+			u-boot,dm-pre-reloc;
+		};
+
+		refclk50mhz: refclk50mhz {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	ubus@ff800000 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@ff812000 {
+			u-boot,dm-pre-reloc;
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xff812000 0x1000>;
+			clock = <50000000>;
+			status = "okay";
+		};
+
+		wdt1: watchdog@ff800480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xff800480 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+		wdt2: watchdog@ff8004c0 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xff8004c0 0x14>;
+			clocks = <&refclk50mhz>;
+		};
+
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+
+		hsspi: hsspi@ff801000 {
+			compatible = "brcm,bcm6328-hsspi";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			u-boot,dm-pre-reloc;
+			
+			reg = <0xff801000 0x1000>;
+			clocks = <&hsspi_pll>, <&hsspi_pll>;
+			clock-names = "hsspi", "pll";
+			spi-max-frequency = <50000000>;
+			num-cs = <8>;
+			status = "disabled";
+		};
+
+		nand: nand-controller@ff801800 {
+			compatible = "brcm,nand-bcmbca", "brcm,brcmnand-v7.1";
+			reg-names = "nand", "nand-int-base";
+			reg = <0xff801800 0x600>, <0xff802000 0x10>;
+			parameter-page-big-endian = <0>;
+			status = "disabled";
+		};
+
+		rng: rng@ff800b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0xff800b80 0x28>;
+			u-boot,dm-pre-reloc;
+		};
+
+		pinctrl: pinctrl {
+		compatible = "brcm,bcmbca-pinctrl";
+		reg = <0xff800554 0x14>;
+		};
+
+		usb_ctrl:usb_ctrl {
+		compatible = "brcm,bcmbca-usb-ctrl";
+		reg-names = "usb-ctrl";
+		reg = <0x8000c200 0x100>;
+		status = "okay";
+		};
+
+		usb0: usb@0x8000c300 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c300 0x100>;
+		};
+
+		usb1: usb@0x8000c500 {
+		compatible = "brcm,bcmbca-ehci";
+		reg-names = "usb-ehci";
+		reg = <0x8000c500 0x100>;
+		};
+
+		usb_ohci0: usb_ohci@0x8000c400 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c400 0x100>;
+		};
+
+		usb_ohci1: usb_ohci@0x8000c600 {
+		compatible = "brcm,bcmbca-ohci";
+		reg-names = "usb-ohci";
+		reg = <0x8000c600 0x100>;
+		};
+	}; 
+};
+
+&nand {
+	status = "okay";
+	write-protect = <0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		compatible = "brcm,nandcs";
+		reg = <0>;
+	};
+};
+
+&hsspi {
+	status = "okay";
+	spi-nand {
+		compatible = "spi-nand";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;				
+		spi-max-frequency = <50000000>;
+	};
+};
+
+/* &hsspi {
+	status = "okay";
+	spi-flash@0 {
+		compatible = "spi-flash";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <20000000>;
+	}
+}; */
+
+/* pinmux */
+/ {
+	usb0a_pwrflt_pins: usb0a_pwrflt_pinmux {
+	    pins = <66>;
+	    function = <1>;
+	};
+
+	usb0a_pwron_pins: usb0a_pwron_pinmux {
+	    pins = <67>;
+	    function = <1>;
+	};
+
+	usb1a_pwrflt_pins: usb1a_pwrflt_pinmux {
+	    pins = <68>;
+	    function = <1>;
+	};
+
+	usb1a_pwron_pins: usb1a_pwron_pinmux {
+	    pins = <69>;
+	    function = <1>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+	pinctrl-0 = <&usb0a_pwrflt_pins &usb0a_pwron_pins>;
+	pinctrl-names="default";
+};
+
+&usb1 {
+	status = "okay";
+	pinctrl-0 = <&usb1a_pwrflt_pins &usb1a_pwron_pins>;
+	pinctrl-names="default";
+};
diff --git a/arch/arm/dts/bcmbca-sf2net.dtsi b/arch/arm/dts/bcmbca-sf2net.dtsi
new file mode 100644
index 0000000000..5b7853b1ec
--- /dev/null
+++ b/arch/arm/dts/bcmbca-sf2net.dtsi
@@ -0,0 +1,42 @@
+/ {
+	periph {
+		mdio_sf2: mdio_sf2 {
+			compatible = "simple-bus";
+		};
+		serdes_sf2: serdes_sf2 {
+			compatible = "simple-bus";
+		};
+	};
+};
+
+&mdio_sf2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	gphy8:8 {
+		reg = <0x8>;
+		phy-type = "EGPHY";
+	};
+	gphy9:9 {
+		reg = <0x9>;
+		phy-type = "EGPHY";
+	};
+	gphya:a {
+		reg = <0xa>;
+		phy-type = "EGPHY";
+	};
+	gphyb:b {
+		reg = <0xb>;
+		phy-type = "EGPHY";
+	};
+	gphyc:c {
+		reg = <0xc>;
+		phy-type = "EGPHY";
+	};
+	phy_ge:8 {
+		reg = <0x8>;
+		phy-type = "EGPHY";
+	};
+
+};
+
diff --git a/arch/arm/include/asm/arch-bcm47622/BPCM.h b/arch/arm/include/asm/arch-bcm47622/BPCM.h
new file mode 100644
index 0000000000..9507387edd
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/BPCM.h
@@ -0,0 +1,761 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t sw_strap:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+// types of PMB devices
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu_reset_n:8;	// 07:00    R/W
+		uint32_t c0l2_reset:1;	// 08:08    R/W
+		uint32_t c1l2_reset:1;	// 09:09    R/W
+		uint32_t reserved0:6;	// 15:10    R/O
+		uint32_t cpu_bpcm_init_on:8;	// 23:16    R/W
+		uint32_t c0l2_bpcm_init_on:1;	// 24:24    R/W
+		uint32_t c1l2_bpcm_init_on:1;	// 25:25    R/W
+		uint32_t ubus_sr:1;	// 26:26    R/W
+		uint32_t cci_sr:1;	// 27:27    R/W
+		uint32_t webcores_sr:1;	// 28:28    R/W
+		uint32_t hw_done:1;	// 29:29    R/O
+		uint32_t sw_done:1;	// 30:30    R/W
+		uint32_t start:1;	// 31:31    R/W
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t reserved0:2;	// 11:10
+		uint32_t ndiv_frac:20;	// 31:12    
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECNDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t reserved0:12;	// 15:04
+		uint32_t mdiv0:8;	// 23:16
+		uint32_t mdiv1:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECPDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv2:8;	// 07:00
+		uint32_t mdiv3:8;	// 15:08
+		uint32_t mdiv4:8;	// 23:16
+		uint32_t mdiv5:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECCH25_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	uint32_t reserved0;
+	uint32_t timer_control;
+	uint32_t timer_status;
+	uint32_t reserved1[2];
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+typedef union {
+	struct {
+		uint32_t ubus_soft_rst:1;
+		uint32_t alt_ubus_clk_sel:1;
+		uint32_t obsv_clk_swinit:1;
+		uint32_t reserved0:17;
+		uint32_t wl0_rf_enable:1;
+		uint32_t wl1_rf_enable:1;
+		uint32_t reserved1:10;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CLKRST_CONTROL;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	// BPCM
+	uint32_t control;	// offset 0x10, PMB reg index 4
+	BPCM_SR_CONTROL sr_control;	// offset 0x14, PMB reg index 5
+	uint32_t reserved1[2];	// offset 0x18, PMB reg index 6/7
+	// Client-specific registers
+	uint32_t client_specific[24];	// offset 0x20, PMB reg index 8..31
+	// Zones
+	BPCM_ZONE zones[];	// offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1))
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCM_OFFSET(reg) (offsetof(BPCM_REGS,reg)>>2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	uint32_t rvrsd[2];
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_VDSL_REGS;		// total offset space = 4096
+
+#define BPCMVDSLOffset(reg)	offsetof(BPCM_VDSL_REGS,reg)
+#define BPCMVDSLRegOffset(reg)	(BPCMVDSLOffset(reg) >> 2)
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08, actual offset = 2
+	uint32_t cfg_control;	// offset = 0x10, actual offset = 4
+	BPCM_SR_CONTROL sr_control;	// offset = 0x14, actual offset = 5
+	uint32_t reserved1[6];	// offset = 0x18, actual offset = 6
+	ARM_CONTROL_REG arm_control;	// offset = 0x30, actual offset = 12
+	uint32_t biu_clk_control0;	// offset = 0x34, actual offset = 13
+	uint32_t tbd[18];	// offset = 0x38, actual offset = 14
+	BPCM_ZONE zones;	// offset = 0x80, actual offset = 32
+} ARM_BPCM_REGS;
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	PLL_DECNDIV_REG decndiv;	// offset = 0x44, actual offset = 0x11
+	PLL_DECPDIV_REG decpdiv;	// offset = 0x48, actual offset = 0x12
+	PLL_DECCH25_REG decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[7];	// offset 0x08-0x20, PMB reg index 2-8
+	uint32_t control;	// offset 0x24, PMB reg index 9
+	uint32_t observe_cntrl;	// offset 0x28, PMB reg index 10
+	uint32_t observe_div;	// offset 0x2c, PMB reg index 11
+	uint32_t observe_enable;	// offset 0x30, PMB reg index 12
+	BPCM_CLKRST_CONTROL clkrst_control;	// offset 0x34, PMB reg index 13
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	// BPCM
+	uint32_t control;	// offset 0x10, PMB reg index 4
+	BPCM_SR_CONTROL sr_control;	// offset 0x14, PMB reg index 5
+
+	uint32_t z0_pm_cntl;	// offset 0x18
+	uint32_t z0_pm_status;	// offset 0x1c
+	uint32_t z1_pm_cntl;	// offset 0x20
+	uint32_t z2_pm_cntl;	// offset 0x24
+	uint32_t reserved1[22];	// reserved from 0x28 to 0x7F
+	BPCM_ZONE zones[];
+
+} BPCM_SYSPORT_REGS;
+
+#define SYSPOffset(reg)		offsetof(BPCM_SYSPORT_REGS,reg)
+#define SYSPRegOffset(reg)	(SYSPOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm47622/brom.h b/arch/arm/include/asm/arch-bcm47622/brom.h
new file mode 100644
index 0000000000..cbc27aa1cb
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _47622_BROM_H
+#define _47622_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm47622/cpu.h b/arch/arm/include/asm/arch-bcm47622/cpu.h
new file mode 100644
index 0000000000..63ed4f3ee6
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/cpu.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _47622_CPU_H
+#define _47622_CPU_H
+
+#define BIUCFG_BASE	0x81060000
+#define CCI500_BASE	0x81100000
+
+
+typedef struct BIUCFG_Access {
+	uint32_t permission;	/* 0x0 */
+	uint32_t sbox;		/* 0x4 */
+	uint32_t cpu_defeature;	/* 0x8 */
+	uint32_t dbg_security;	/* 0xc */
+	uint32_t rsvd1[32];	/* 0x10 - 0x8f */
+	uint64_t violation[2];	/* 0x90 - 0x9f */
+	uint32_t ts_access[2];	/* 0xa0 - 0xa7 */
+	uint32_t rsvd2[22];	/* 0xa8 - 0xff */
+} BIUCFG_Access;
+
+typedef struct BIUCFG_Cluster {
+	uint32_t permission;	/* 0x0 */
+	uint32_t config;	/* 0x4 */
+	uint32_t status;	/* 0x8 */
+	uint32_t control;	/* 0xc */
+	uint32_t cpucfg;	/* 0x10 */
+	uint32_t dbgrom;	/* 0x14 */
+	uint32_t rsvd1[2];	/* 0x18 - 0x1f */
+	uint32_t rvbar_addr[4];	/* 0x20 - 0x2f */
+	uint32_t rsvd2[52];	/* 0x30 - 0xff */
+} BIUCFG_Cluster;
+
+typedef struct BIUCFG_AuxClkCtrl {
+	uint32_t clk_control;	/* 0x0 */
+	uint32_t clk_ramp;	/* 0x4 */
+	uint32_t clk_pattern;	/* 0x8 */
+	uint32_t rsvd;		/* 0xC */
+} BIUCFG_AuxClkCtrl;
+
+typedef struct BIUCFGux {
+	uint32_t permission;	/* 0 */
+	uint32_t rsvd1[3];	/* 0x04 - 0x0c */
+	BIUCFG_AuxClkCtrl cluster_clkctrl[2];	/* 0x10 - 0x2c */
+	uint32_t rsvd2[52];	/* 0x30 - 0xFF */
+} BIUCFG_Aux;
+
+typedef struct BIUCFG_Bac {
+	uint32_t bac_permission;	/* 0x00 */
+	uint32_t bac_periphbase;	/* 0x04 */
+	uint32_t rsvd[2];		/* 0x08 - 0x0f */
+	uint32_t bac_event;		/* 0x10 */
+	uint32_t rsvd_1[3];		/* 0x14 - 0x1f */
+	uint32_t bac_ccicfg;		/* 0x20 */
+	uint32_t bac_cciaddr;		/* 0x24 */
+	uint32_t rsvd_2[4];		/* 0x28 - 0x37 */
+	uint32_t bac_ccievs2;		/* 0x38 */
+	uint32_t bac_ccievs3;		/* 0x3c */
+	uint32_t bac_ccievs4;		/* 0x40 */
+	uint32_t rsvd_3[3];		/* 0x44 - 0x4f */
+	uint32_t bac_ccievm0;		/* 0x50 */
+	uint32_t bac_ccievm1;		/* 0x54 */
+	uint32_t rsvd_4[2];		/* 0x58 - 0x5f */
+	uint32_t bac_dapapbcfg;		/* 0x60 */
+	uint32_t bac_status;		/* 0x64 */
+	uint32_t rsvd_5[2];		/* 0x68 - 0x6f */
+	uint32_t cpu_therm_irq_cfg; 	/* 0x70 */
+	uint32_t cpu_therm_threshold_cfg; /* 0x74 */
+	uint32_t rsvd_6;		/* 0x78 */
+	uint32_t cpu_therm_temp;	/* 0x7c */
+	uint32_t rsvd_7[32];		/* 0x80 - 0xff */
+} BIUCFG_Bac;
+
+typedef struct BIUCFG {
+	BIUCFG_Access access;	/* 0x0 - 0xff */
+	BIUCFG_Cluster cluster[2];	/* 0x100 - 0x2ff */
+	BIUCFG_Bac bac;		/* 0x300 - 0x3ff */
+	uint32_t rsvd1[192];	/* 0x400 - 0x6ff */
+	BIUCFG_Aux aux;		/* 0x700 - 0x7ff */
+	uint32_t rsrvd2[512];	/* 0x800 - 0xfff */
+	uint32_t TSO_CNTCR;	/* 0x1000 */
+	uint32_t rsvd2[2047];	/* 0x1004 - 0x2fff */
+} BIUCFG;
+
+#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
+
+typedef struct CCI500_SlaveIntf {
+#define SNOOP_CTRL_ENABLE_SNOOP		0x1
+	uint32_t snoop_ctrl;		/* 0x0 */
+#define SHARE_OVR_SHAREABLE_OVR_SHIFT	0x0
+#define SHARE_OVR_SHAREABLE_OVR_MASK	0x3
+#define SHARE_OVR_SHAREABLE_OVR_NONSHR	0x2
+#define SHARE_OVR_SHAREABLE_OVR_SHR	0x3
+	uint32_t share_ovr;		/* 0x4 */
+	uint32_t rsvd1[62];		/* 0x8 - 0xff */
+	uint32_t arqos_ovr;		/* 0x100 */
+	uint32_t awqos_ovr;		/* 0x104 */
+	uint32_t rsvd2[2];		 /* 0x108 - 0x10f */
+	uint32_t qos_max_ot;		/* 0x110 */
+	uint32_t rsvd3[955];		/* 0x114 - 0xfff */
+}CCI500_SlaveIntf;
+
+typedef struct CCI500_EventCounter {
+	uint32_t sel;	/* 0x0 */
+	uint32_t data;	/* 0x4 */
+	uint32_t ctrl;	/* 0x8 */
+	uint32_t clr_ovfl;/* 0xC */
+	uint32_t rsvd[16380];/* 0x10 - 0xffff */
+}CCI500_EventCounter;
+
+typedef struct CCI500 {
+#define CONTROL_OVERRIDE_SNOOP_DISABLE	0x1
+#define CONTROL_OVERRIDE_SNOOP_FLT_DISABLE 0x4
+	uint32_t ctrl_ovr;	/* 0x0 */
+	uint32_t rsvd1;		/* 0x4 */
+#define SECURE_ACCESS_UNSECURE_ENABLE	0x1
+	uint32_t secr_acc;	/* 0x8 */
+	uint32_t status;	 /* 0xc */
+#define STATUS_CHANGE_PENDING		0x1
+	uint32_t impr_err;	/* 0x10 */
+	uint32_t qos_threshold;	/* 0x14 */
+	uint32_t rsvd2[58];	/* 0x18 - 0xff */
+	uint32_t pmu_ctrl;	/* 0x100 */
+#define DBG_CTRL_EN_INTF_MON		0x1
+	uint32_t debug_ctrl;	/* 0x104 */
+	uint32_t rsvd3[958];	/* 0x108 - 0xfff */
+#define SLAVEINTF_COHERENCY_PORT	0x0
+#define SLAVEINTF_CPU_CLUSTER		0x1
+	CCI500_SlaveIntf si[7];	/* 0x1000 - 0x7fff */
+	uint32_t rsvd4[8192];	/* 0x8000 - 0xffff */
+	CCI500_EventCounter evt_cntr[8]; /* 0x10000 - 0x8ffff */
+}CCI500;
+#define CCI500 ((volatile CCI500 * const) CCI500_BASE)
+
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm47622/ddr.h b/arch/arm/include/asm/arch-bcm47622/ddr.h
new file mode 100644
index 0000000000..9849d5a263
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/ddr.h
@@ -0,0 +1,616 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _47622_DDR_H
+#define _47622_DDR_H
+
+#define MEMC_BASE	0x80180000	/* DDR IO Buf Control */
+
+typedef struct AXIInterface {
+	uint32_t CFG;			/* 0x00 */
+	uint32_t REP_ARB_MODE;		/* 0x04 */
+	uint32_t QUEUE_CFG;		/* 0x08 */
+	uint32_t ESRCID_CFG;		/* 0x0c */
+	uint32_t SRC_QUEUE_CTRL[8];	/* 0x10 */
+	uint32_t SRC_ID_4_QUEUE_CTRL;	/* 0x30 */
+	uint32_t SCRATCH;		/* 0x34 */
+	uint32_t AXI_DEBUG[2];		/* 0x38 */
+} AXIInterface;
+
+typedef struct EDISEngine {
+	uint32_t REV_ID;		/* 0x00 */
+	uint32_t CTRL_TRIG;		/* 0x04 */
+	uint32_t CTRL_MODE;		/* 0x08 */
+	uint32_t CTRL_SIZE;		/* 0x0c */
+	uint32_t CTRL_ADDR_START;	/* 0x10 */
+	uint32_t CTRL_ADDR_START_EXT;	/* 0x14 */
+	uint32_t CTRL_ADDR_END;		/* 0x18 */
+	uint32_t CTRL_ADDR_END_EXT;	/* 0x1c */
+	uint32_t CTRL_WRITE_MASKS;	/* 0x20 */
+	uint32_t CTRL_INT_ENABLES;	/* 0x24 */
+	uint32_t unused0[6];		/* 0x28-0x3f */
+	uint32_t STAT_MAIN;		/* 0x40 */
+	uint32_t STAT_WORDS_WRITTEN;	/* 0x44 */
+	uint32_t STAT_WORDS_READ;	/* 0x48 */
+	uint32_t STAT_ERROR_COUNT;	/* 0x4c */
+	uint32_t STAT_ERROR_BITS;	/* 0x50 */
+	uint32_t STAT_ADDR_LAST;	/* 0x54 */
+	uint32_t STAT_ADDR_LAST_EXT;	/* 0x58 */
+	uint32_t STAT_CLOCK_CYCLES;	/* 0x5c */
+	uint32_t unused1[7];		/* 0x60-0x7b */
+	uint32_t STAT_DEBUG;		/* 0x7c */
+	uint32_t STAT_DATA_PORT[8];	/* 0x80-0x9c */
+	uint32_t GEN_LFSR_STATE[4];	/* 0xa0-0xac */
+	uint32_t GEN_CLOCK;		/* 0xb0 */
+	uint32_t GEN_PATTERN;		/* 0xb4 */
+	uint32_t unused2[2];		/* 0xb8-0xbf */
+	uint32_t BYTELANE_0_CTRL_LO;	/* 0xc0 */
+	uint32_t BYTELANE_0_CTRL_HI;	/* 0xc4 */
+	uint32_t BYTELANE_1_CTRL_LO;	/* 0xc8 */
+	uint32_t BYTELANE_1_CTRL_HI;	/* 0xcc */
+	uint32_t BYTELANE_2_CTRL_LO;	/* 0xd0 */
+	uint32_t BYTELANE_2_CTRL_HI;	/* 0xd4 */
+	uint32_t BYTELANE_3_CTRL_LO;	/* 0xd8 */
+	uint32_t BYTELANE_3_CTRL_HI;	/* 0xdc */
+	uint32_t BYTELANE_0_STAT_LO;	/* 0xe0 */
+	uint32_t BYTELANE_0_STAT_HI;	/* 0xe4 */
+	uint32_t BYTELANE_1_STAT_LO;	/* 0xe8 */
+	uint32_t BYTELANE_1_STAT_HI;	/* 0xec */
+	uint32_t BYTELANE_2_STAT_LO;	/* 0xf0 */
+	uint32_t BYTELANE_2_STAT_HI;	/* 0xf4 */
+	uint32_t BYTELANE_3_STAT_LO;	/* 0xf8 */
+	uint32_t BYTELANE_3_STAT_HI;	/* 0xfc */
+} EDISEngine;
+
+typedef struct RangeCtrl {
+	uint32_t CTRL;			/* 0x00 */
+	uint32_t UBUS0_PORT;		/* 0x04 */
+	uint32_t UBUS0_PORT_UPPER;	/* 0x08 */
+	uint32_t BASE;			/* 0x0c */
+	uint32_t BASE_UPPER;		/* 0x10 */
+	uint32_t SECLEC_EN;		/* 0x14 */
+} RangeCtrl;
+
+typedef struct SecureRangeCheckers {
+	uint32_t LOCK;			/* 0x00 */
+	uint32_t LOG_INFO[3];		/* 0x04 - 0x0c */
+	RangeCtrl RANGE_CTRL[8];	/* 0x10 - 0xcf */
+	uint32_t unused[12];		/* 0xd0 - 0xff */
+} SecureRangeCheckers;
+
+typedef struct DDRPhyControl {
+	uint32_t PRIMARY_REVISION;	/* 0x00 */
+	uint32_t SECONDARY_REVISION;	/* 0x04 */
+	uint32_t FEATURE;		/* 0x08 */
+	uint32_t PLL_STATUS;		/* 0x0c */
+	uint32_t PLL_CONFIG;		/* 0x10 */
+	uint32_t PLL_CONTROL1;		/* 0x14 */
+	uint32_t PLL_CONTROL2;		/* 0x18 */
+	uint32_t PLL_CONTROL3;		/* 0x1c */
+	uint32_t PLL_DIVIDER;		/* 0x20 */
+	uint32_t PLL_PRE_DIVIDER;	/* 0x24 */
+	uint32_t PLL_SS_EN;		/* 0x28 */
+	uint32_t PLL_SS_CFG;		/* 0x2c */
+	uint32_t AUX_CONTROL;		/* 0x30 */
+	uint32_t IDLE_PAD_CONTROL;	/* 0x34 */
+	uint32_t IDLE_PAD_EN0;		/* 0x38 */
+	uint32_t IDLE_PAD_EN1;		/* 0x3c */
+	uint32_t DRIVE_PAD_CTL;		/* 0x40 */
+	uint32_t DRIVE_PAD_CTL_2T;	/* 0x44 */
+	uint32_t DRIVE_PAD_CTL_2T_A;	/* 0x48 */
+	uint32_t STATIC_PAD_CTL;	/* 0x4c */
+	uint32_t STATIC_PAD_CTL_2T;	/* 0x50 */
+	uint32_t STATIC_PAD_CTL_2T_A;	/* 0x54 */
+	uint32_t RX_TRIM;		/* 0x58 */
+	uint32_t DRAM_CFG;		/* 0x5c */
+	uint32_t DRAM_TIMING2;		/* 0x60 */
+	uint32_t DRAM_TIMING3;		/* 0x64 */
+	uint32_t VDL_REGS[45];		/* 0x68-0x11b */
+	uint32_t UPDATE_VDL;		/* 0x11c */
+	uint32_t UPDATE_VDL_SNOOP1;	/* 0x120 */
+	uint32_t UPDATE_VDL_SNOOP2;	/* 0x124 */
+	uint32_t CMND_REG1;		/* 0x128 */
+	uint32_t CMND_AUX_REG1;		/* 0x12c */
+	uint32_t CMND_REG2;		/* 0x130 */
+	uint32_t CMND_AUX_REG2;		/* 0x134 */
+	uint32_t CMND_REG3;		/* 0x138 */
+	uint32_t CMND_AUX_REG3;		/* 0x13c */
+	uint32_t CMND_REG4;		/* 0x140 */
+	uint32_t CMND_AUX_REG4;		/* 0x144 */
+	uint32_t MODE_REG[8];		/* 0x148-167 */
+	uint32_t ALERT_CLEAR;		/* 0x168 */
+	uint32_t ALERT_STATUS;		/* 0x16c */
+	uint32_t ALERT_DF1;		/* 0x170 */
+	uint32_t WRITE_LEVEL_CTRL;	/* 0x174 */
+	uint32_t WRITE_LEVEL_STATUS;	/* 0x178 */
+	uint32_t READ_EN_CTRL;		/* 0x17c */
+	uint32_t READ_EN_STATUS;	/* 0x180 */
+	uint32_t VIRT_VTT_CTRL;		/* 0x184 */
+	uint32_t VIRT_VTT_STATUS;	/* 0x188 */
+	uint32_t VIRT_VTT_CONNECTION;	/* 0x18c */
+	uint32_t VIRT_VTT_OVERRIDE;	/* 0x190 */
+	uint32_t VREF_DAC_CTRL;		/* 0x194 */
+#define DDRPHY_VREF_DAC_CTRL_PDN_SHIFT             12
+#define DDRPHY_VREF_DAC_CTRL_PDN_MASK              (0xf << DDRPHY_VREF_DAC_CTRL_PDN_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT            6
+#define DDRPHY_VREF_DAC_CTRL_DAC1_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT            0
+#define DDRPHY_VREF_DAC_CTRL_DAC0_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT)
+	uint32_t STANDBY_CTRL;		/* 0x198 */
+	uint32_t DEBUG_FREEZE_EN;	/* 0x19c */
+	uint32_t DEBUG_MUX_CTRL;	/* 0x1a0 */
+	uint32_t DFI_CTRL;		/* 0x1a4 */
+	uint32_t WRITE_ODT_CTRL;	/* 0x1a8 */
+	uint32_t ABI_PAR_CTRL;		/* 0x1ac */
+	uint32_t ZQ_CAL;		/* 0x1b0 */
+	uint32_t ZQ_CAL2;		/* 0x1b4 */
+	uint32_t unused6[14];		/* 0x1b8-0x1ef */
+	uint32_t CLOCK_IDLE;		/* 0x1f0 */
+	uint32_t unused7[131];		/* 0x1f4-0x3ff */
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+	uint32_t VDL_CTRL_WR[10];	/* 0x00 - 0x27 */
+	uint32_t VDL_CTRL_RD[22];	/* 0x28 - 0x7f */
+	uint32_t VDL_CLK_CTRL;		/* 0x80 */
+	uint32_t VDL_LDE_CTRL;		/* 0x84 */
+	uint32_t RD_EN_DLY_CYC;		/* 0x88 */
+#define RD_EN_DLY_CYC_CS0_CYCLES_SHIFT      0x0
+#define RD_EN_DLY_CYC_CS0_CYCLES_MASK       (0xf<<RD_EN_DLY_CYC_CS0_CYCLES_SHIFT)
+	uint32_t WR_CHAN_DLY_CYC;	/* 0x8c */
+	uint32_t RD_CTRL;		/* 0x90 */
+	uint32_t RD_FIFO_ADDR;		/* 0x94 */
+	uint32_t RD_FIFO_DATA;		/* 0x98 */
+	uint32_t RD_FIFO_DM_DBI;	/* 0x9c */
+	uint32_t RD_FIFO_STATUS;	/* 0xa0 */
+	uint32_t RD_FIFO_CLR;		/* 0xa4 */
+	uint32_t DYNAMIC_CLK_CTRL;	/* 0xa8 */
+	uint32_t IDLE_PAD_CTRL;		/* 0xac */
+	uint32_t DRIVE_PAD_CTRL;	/* 0xb0 */
+	uint32_t DQSP_DRIVE_PAD_CTRL;	/* 0xb4 */
+	uint32_t DQSN_DRIVE_PAD_CTRL;	/* 0xb8 */
+	uint32_t RD_EN_DRIVE_PAD_CTRL;	/* 0xbc */
+	uint32_t STATIC_PAD_CTRL;	/* 0xc0 */
+	uint32_t DQ_RX_TRIM;		/* 0xc4 */
+	uint32_t MISC_RX_TRIM;		/* 0xc8 */
+	uint32_t DQS_RX_TRIM;		/* 0xcc */
+	uint32_t WR_PREAMBLE_MODE;	/* 0xd0 */
+	uint32_t ODT_CTRL;		/* 0xd4 */
+	uint32_t LDO_CONFIG;		/* 0xd8 */
+	uint32_t CLOCK_ENABLE;		/* 0xdc */
+	uint32_t CLOCK_IDLE;		/* 0xe0 */
+	uint32_t RD_CHAN_FIFO_CLR;	/* 0xe4 */
+	uint32_t BL_SPARE_REG;		/* 0xe8 */
+	uint32_t unused[69];		/* 0xec-0x1ff */
+} DDRPhyByteLaneControl;
+
+
+typedef struct MEMCControl {
+	uint32_t GLB_VERS;		/* 0x000 */
+	uint32_t GLB_GCFG;		/* 0x004 */
+#define MEMC_GLB_GCFG_DRAM_EN_SHIFT        31
+#define MEMC_GLB_GCFG_DRAM_EN_MASK         (0x1<<MEMC_GLB_GCFG_DRAM_EN_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ_SHIFT      30
+#define MEMC_GLB_GCFG_FORCE_SEQ_MASK       (0x1<<MEMC_GLB_GCFG_FORCE_SEQ_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT     29
+#define MEMC_GLB_GCFG_FORCE_SEQ2_MASK      (1<<MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT)
+#define MEMC_GLB_GCFG_RBF_REORDER_SHIFT    28
+#define MEMC_GLB_GCFG_RBF_REORDER_MASK     (1<<MEMC_GLB_GCFG_RBF_REORDER_SHIFT)
+#define MEMC_GLB_GCFG_SREF_SLOW_CLK_SHIFT  26
+#define MEMC_GLB_GCFG_SREF_SLOW_CLK_MASK   (1<<MEMC_GLB_GCFG_SREF_SLOW_CLK_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT   24
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_MASK    (0x3<<MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_2X           0x0
+#define MEMC_GLB_GCFG_PHY_DFI_4X           0x1
+#define MEMC_GLB_GCFG_PHY_DFI_8X           0x2
+#define MEMC_GLB_GCFG_ALT_CHN_ARB_SHIFT    21
+#define MEMC_GLB_GCFG_ALT_CHN_ARB_MASK     (0x1<<MEMC_GLB_GCFG_ALT_CHN_ARB_SHIFT)
+#define MEMC_GLB_GCFG_DFI_EN_SHIFT         10
+#define MEMC_GLB_GCFG_DFI_EN_MASK          (0x1<<MEMC_GLB_GCFG_DFI_EN_SHIFT)
+#define MEMC_GLB_GCFG_MCLKSRC_SHIFT        9
+#define MEMC_GLB_GCFG_MCLKSRC_MASK         (0x1<<MEMC_GLB_GCFG_MCLKSRC_SHIFT)
+#define MEMC_GLB_GCFG_MEMINITDONE_SHIFT    8
+#define MEMC_GLB_GCFG_MEMINITDONE_MASK     (0x1<<MEMC_GLB_GCFG_MEMINITDONE_SHIFT)
+#define MEMC_GLB_GCFG_MRQSIZE_SHIFT        0
+#define MEMC_GLB_GCFG_MRQSIZE_MASK         (0x1f<<MEMC_GLB_GCFG_MRQSIZE_SHIFT)
+	uint32_t GLB_MRQ_CFG;		/* 0x008 */
+	uint32_t unused0;		/* 0x00c */
+	uint32_t GLB_FSBL_STATE;	/* 0x010 */
+#define MEMC_GLB_FSBL_DRAM_SIZE_SHIFT      0
+#define MEMC_GLB_FSBL_DRAM_SIZE_MASK       (0xf << MEMC_GLB_FSBL_DRAM_SIZE_SHIFT)
+	uint32_t unused1[3];		/* 0x014 - 0x01f */
+
+	uint32_t SRAM_REMAP_CTRL;	/* 0x020 */
+	uint32_t SRAM_REMAP_CTRL_UPPER;	/* 0x024 */
+	uint32_t SRAM_REMAP_INIT;	/* 0x028 */
+	uint32_t SRAM_REMAP_LOG_INFO_0;	/* 0x02c */
+	uint32_t SRAM_REMAP_LOG_INFO_1;	/* 0x030 */
+	uint32_t SRAM_REMAP_LOG_INFO_2;	/* 0x034 */
+	uint32_t unused2[2];		/* 0x038-0x03f */
+
+	uint32_t RBF_REORDER_0_CFG[16];	/* 0x040 - 0x07f */
+
+	uint32_t INTR2_CPU_STATUS;	/* 0x080 */
+	uint32_t INTR2_CPU_SET;		/* 0x084 */
+	uint32_t INTR2_CPU_CLEAR;	/* 0x088 */
+	uint32_t INTR2_CPU_MASK_STATUS;	/* 0x08c */
+	uint32_t INTR2_CPU_MASK_SET;	/* 0x090 */
+	uint32_t INTR2_CPU_MASK_CLEAR;	/* 0x094 */
+	uint32_t unused3[26];		/* 0x098-0x0ff */
+
+	uint32_t CHN_CFG_CNFG;		/* 0x100 */
+#define MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT            16
+#define MEMC_CHN_CFG_CNFG_CS_MODE_MASK             (0x3 << MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT)
+	uint32_t CHN_CFG_CSST;		/* 0x104 */
+	uint32_t unused4[2];		/* 0x108-0x10f */
+	uint32_t CHN_CFG_ROW00_0;	/* 0x110 */
+	uint32_t CHN_CFG_ROW00_1;	/* 0x114 */
+	uint32_t CHN_CFG_ROW01_0;	/* 0x118 */
+	uint32_t CHN_CFG_ROW01_1;	/* 0x11c */
+	uint32_t CHN_CFG_ROW02_0;	/* 0x120 */
+	uint32_t CHN_CFG_COL00_0;	/* 0x124 */
+	uint32_t CHN_CFG_COL00_1;	/* 0x128 */
+	uint32_t CHN_CFG_COL01_0;	/* 0x12c */
+	uint32_t CHN_CFG_COL01_1;	/* 0x130 */
+	uint32_t CHN_CFG_BNK10;		/* 0x134 */
+	uint32_t CHN_CFG_BG0;		/* 0x138 */
+	uint32_t unused5;		/* 0x13c */
+	uint32_t CHN_CFG_DRAM_SZ_CHK;	/* 0x140 */
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT  4
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_MASK   (0xf<<MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT)
+	uint32_t CHN_CFG_DIAG_SEL;	/* 0x144 */
+	uint32_t unused6[46];		/* 0x148-0x1ff */
+
+	uint32_t CHN_TIM_DCMD;		/* 0x200 */
+	uint32_t CHN_TIM_DMODE_0;	/* 0x204 */
+	uint32_t CHN_TIM_DMODE_2;	/* 0x208 */
+	uint32_t CHN_TIM_CLKS;		/* 0x20c */
+#define MEMC_CHN_TIM_CLKS_REF_RATE_SHIFT          8
+#define MEMC_CHN_TIM_CLKS_REF_DISABLE_SHIFT       31
+	uint32_t CHN_TIM_ODT;		/* 0x210 */
+	uint32_t CHN_TIM_TIM1_0;	/* 0x214 */
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tWL [31:24] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_MASK                            0xff000000
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_SHIFT                           24
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_DEFAULT                         0x00000004
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRP [23:16] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_MASK                            0x00ff0000
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_SHIFT                           16
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_DEFAULT                         0x00000006
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tCL [15:08] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_MASK                            0x0000ff00
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_SHIFT                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_DEFAULT                         0x00000005
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRCD [07:00] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_MASK                           0x000000ff
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_ALIGN                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_BITS                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_SHIFT                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_DEFAULT                        0x00000006
+
+	uint32_t CHN_TIM_TIM1_1;	/* 0x218 */
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_L [31:24] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_S [23:16] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_L [15:08] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_MASK                         0x0000ff00
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_SHIFT                        8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_S [07:00] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_MASK                         0x000000ff
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_SHIFT                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_DEFAULT                      0x00000002
+
+	uint32_t CHN_TIM_TIM1_2;	/* 0x21c */
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tFAW [31:24] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_MASK                           0xff000000
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_SHIFT                          24
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_DEFAULT                        0x00000000
+/* MC_CHN_TIM :: TIM1_2 :: reserved0 [23:16] */
+#define MC_CHN_TIM_TIM1_2_reserved0_MASK                           0x00ff0000
+#define MC_CHN_TIM_TIM1_2_reserved0_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_reserved0_BITS                           8
+#define MC_CHN_TIM_TIM1_2_reserved0_SHIFT                          16
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRTP [15:08] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_MASK                           0x0000ff00
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_SHIFT                          8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_DEFAULT                        0x00000002
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRC [07:00] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_ALIGN                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_BITS                            8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_SHIFT                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_DEFAULT                         0x00000011
+
+	uint32_t CHN_TIM_TIM1_3;	/* 0x220 */
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_L [31:24] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_S [23:16] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: reserved_for_padding0 [15:12] */
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_MASK               0x0000f000
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_ALIGN              0
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_BITS               4
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_SHIFT              12
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_L [11:08] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_MASK                          0x00000f00
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_BITS                          4
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_SHIFT                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_DEFAULT                       0x00000004
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_S [07:00] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_MASK                          0x000000ff
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_BITS                          8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_SHIFT                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_DEFAULT                       0x00000004
+
+	uint32_t CHN_TIM_TIM2;		/* 0x224 */
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2R [31:30] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_MASK                             0xc0000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_BITS                             2
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_SHIFT                            30
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2W [29:27] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_MASK                             0x38000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_SHIFT                            27
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2R [26:24] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_MASK                             0x07000000
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_SHIFT                            24
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: reserved_for_padding0 [23:22] */
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_MASK                 0x00c00000
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_ALIGN                0
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_BITS                 2
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_SHIFT                22
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2W [21:18] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_MASK                             0x003c0000
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_BITS                             4
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_SHIFT                            18
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: reserved1 [17:16] */
+#define MC_CHN_TIM_TIM2_reserved1_MASK                             0x00030000
+#define MC_CHN_TIM_TIM2_reserved1_ALIGN                            0
+#define MC_CHN_TIM_TIM2_reserved1_BITS                             2
+#define MC_CHN_TIM_TIM2_reserved1_SHIFT                            16
+/* MC_CHN_TIM :: TIM2 :: TIM2_tAL [15:12] */
+#define MC_CHN_TIM_TIM2_TIM2_tAL_MASK                              0x0000f000
+#define MC_CHN_TIM_TIM2_TIM2_tAL_ALIGN                             0
+#define MC_CHN_TIM_TIM2_TIM2_tAL_BITS                              4
+#define MC_CHN_TIM_TIM2_TIM2_tAL_SHIFT                             12
+#define MC_CHN_TIM_TIM2_TIM2_tAL_DEFAULT                           0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tRFC [11:00] */
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_MASK                             0x00000fff
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_BITS                             12
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_SHIFT                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_DEFAULT                          0x00000014
+
+	uint32_t unused7[2];		/* 0x228 - 0x22f */
+	uint32_t CHN_TIM_PHY_ST;	/* 0x230 */
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP       0x1
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_HW_RESET       0x2
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_SW_RESET       0x4
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_READY          0x10
+	uint32_t CHN_TIM_DRAM_CFG;	/* 0x234 */
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT           12
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_MASK            (0x1<<MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT     10
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_MASK      (0x1<<MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT      0
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_MASK       (0xf<<MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT)
+#define MC_DRAM_CFG_DDR3                          0x1
+#define MC_DRAM_CFG_DDR4                          0x2
+	uint32_t CHN_TIM_STAT;		/* 0x238 */
+	uint32_t CHN_TIM_PERF;		/* 0x23c */
+
+	uint32_t CHN_TIM_PKM_CFG;	/* 0x240 */
+	uint32_t CHN_TIM_AB4_CFG;	/* 0x244 */
+	uint32_t unused8[2];		/* 0x248 */
+	uint32_t CHN_TIM_AB4_ACT_PRI;	/* 0x250 */
+	uint32_t CHN_TIM_AB4_PRI_OPEN;	/* 0x254 */
+	uint32_t CHN_TIM_AB4_PRI_CLOSED;/* 0x258 */
+	uint32_t CHN_TIM_AUTO_SELF_REFRESH;/* 0x25c */
+#define MEMC_DDR_AUTO_SELFREFRESH_EN              (1 << 31)
+#define MEMC_DDR_AUTO_SR_IDLE_CNT_MASK            (0x7FFFFFFF)
+	uint32_t CHN_TIM_AUTO_ZQCS;	/* 0x260 */
+	uint32_t CHN_TIM_TIM3;		/* 0x264 */
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_MASK                            0x0fff0000
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_ALIGN                           0
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_BITS                            12
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_SHIFT                           16
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_DEFAULT                         0x00000100
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_ALIGN                           0
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_BITS                            8
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_SHIFT                           0
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_DEFAULT                         0x00000040
+
+	uint32_t unused9[38];		/* 0x268-0x2ff */
+
+	uint32_t ARB_CFG;		/* 0x300 */
+	uint32_t ARB_QUE_DIS[2];	/* 0x304 */
+	uint32_t unused10;		/* 0x30c */
+	uint32_t ARB_BKT_CFG_CPU_WR[4];	/* 0x310 */
+	uint32_t ARB_BKT_CFG_CPU_RD[4];	/* 0x320 */
+	uint32_t ARB_BKT_CFG_CPQ_RD[4];	/* 0x330 */
+	uint32_t ARB_BKT_CFG_CPQ_WR[4];	/* 0x340 */
+	uint32_t ARB_BKT_CFG_EDIS[4];	/* 0x350 */
+	uint32_t unused11[32];		/* 0x360 */
+	uint32_t ARB_QUEUE_PRI[3];	/* 0x3e0 */
+	uint32_t ARB_WRR_QUEUE_PRI;	/* 0x3ec */
+	uint32_t ARB_RATE_OK_WEIGHT[2];	/* 0x3f0 */
+	uint32_t ARB_RATE_FAIL_WEIGHT[2];/* 0x3f8 */
+
+	uint32_t unused12[48];		/* 0x400 */
+	AXIInterface AXIWIF;		/* 0x4c0 */
+
+	uint32_t unused13[192];		/* 0x500-0x7ff */
+
+	EDISEngine EDIS_0;		/* 0x800 */
+	uint32_t unused14[64];		/* 0x900 */
+
+	uint32_t STATS_CTRL;		/* 0xa00 */
+	uint32_t STATS_TIMER_CFG;	/* 0xa04 */
+	uint32_t STATS_TIMER_COUNT;	/* 0xa08 */
+	uint32_t STATS_TOTAL_SLICE;	/* 0xa0c */
+	uint32_t STATS_TOTAL_PACKET;	/* 0xa10 */
+	uint32_t STATS_TOTAL_READ_SLICE;/* 0xa14 */
+	uint32_t STATS_TOTAL_READ_PACKET;/* 0xa18 */
+	uint32_t STATS_TOTAL_LATENCY;	/* 0xa1c */
+	uint32_t STAT_MAX_LATENCY;	/* 0xa20 */
+	uint32_t STATS_SLICE_REORDER;	/* 0xa24 */
+	uint32_t STATS_TOTAL_DDR_CMD;	/* 0xa28 */
+	uint32_t STATS_TOTAL_DDR_ACT;	/* 0xa2c */
+	uint32_t STATS_TOTAL_DDR_RDWR;	/* 0xa30 */
+	uint32_t STATS_TOTAL_DDR_WRRD;	/* 0xa34 */
+	uint32_t STATS_TOTAL_MRQ_CHN_FULL;/* 0xa38 */
+	uint32_t STATS_TOTAL_SELF_REF;	/* 0xa3c */
+	uint32_t STATS_ARB_GRANT_MATCH0;/* 0xa40 */
+	uint32_t STATS_TOTAL_QUEUE_FULL;/* 0xa44 */
+	uint32_t STATS_TOTAL_ARB_GRANT;	/* 0xa48 */
+	uint32_t STATS_TOTAL_RATE_OK_GRANT;/* 0xa4c*/
+	uint32_t STATS_FILTER_CFG_0;	/* 0xa50 */
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT  25
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_MASK   (0x1<<MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_EN     0x02000000
+#define MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT     16
+#define MEMC_STATS_FILTER_CFG_SRC_ID_MASK      (0x1FF<<MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_SHIFT 0
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_MASK  0x0000FFFF
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS        0x00000001
+#define MEMC_STATS_FILTER_CFG_INTF_AXI         0x00000002
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS0       0x00000004
+#define MEMC_STATS_FILTER_CFG_INTF_UNUSED      0x00000008
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS0       MEMC_STATS_FILTER_CFG_INTF_UBUS
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_MCP         MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+	uint32_t STATS_PROG0_SLICE;	/* 0xa54 */
+	uint32_t STATS_PROG0_PACKET;	/* 0xa58 */
+	uint32_t STATS_PROG0_READ_SLICE;/* 0xa5c */
+	uint32_t STATS_PROG0_READ_PACKET;/* 0xa60 */
+	uint32_t STATS_PROG0_LATENCY;	/* 0xa64 */ 
+	uint32_t STATS_PROG0_MAX_LETANCY;/* 0xa68 */
+
+	// uint32_t unused15[37];	/* 0xa6c */
+	uint32_t unused15_0;		/* 0xa6c */
+	uint32_t STATS_FILTER_CFG_1;	/* 0xa70 */
+	uint32_t STATS_PROG1_SLICE;	/* 0xa74 */
+	uint32_t STATS_PROG1_PACKET;	/* 0xa78 */ 
+	uint32_t STATS_PROG1_READ_SLICE;/* 0xa7c */  
+	uint32_t STATS_PROG1_READ_PACKET;/* 0xa80 */
+	uint32_t STATS_PROG1_LATENCY;	/* 0xa84 */ 
+	uint32_t unused15_1[2];		/* 0xa88 - 0xa8c */   
+	uint32_t STATS_FILTER_CFG_2;	/* 0xa90 */
+	uint32_t STATS_PROG2_SLICE;	/* 0xa94 */
+	uint32_t STATS_PROG2_PACKET;	/* 0xa98 */ 
+	uint32_t STATS_PROG2_READ_SLICE;/* 0xa9c */  
+	uint32_t STATS_PROG2_READ_PACKET;/* 0xaa0 */
+	uint32_t STATS_PROG2_LATENCY;	/* 0xaa4 */ 
+	uint32_t unused15_2[2];		/* 0xaa8 - 0xaac */
+	uint32_t STATS_FILTER_CFG_3;	/* 0xab0 */
+	uint32_t STATS_PROG3_SLICE;	/* 0xab4 */
+	uint32_t STATS_PROG3_PACKET;	/* 0xab8 */ 
+	uint32_t STATS_PROG3_READ_SLICE;/* 0xabc */  
+	uint32_t STATS_PROG3_READ_PACKET;/* 0xac0 */
+	uint32_t STATS_PROG3_LATENCY;	/* 0xac4 */
+	uint32_t unused15_3[2];		/* 0xac8 - 0xacc */
+	uint32_t STATS_AXI_BLOCK_CPU_RD;/* 0xad0 */    
+	uint32_t STATS_AXI_BLOCK_CPQ_RD;/* 0xad4 */    
+	uint32_t unused15_4[10];	/* 0xad8 - 0xaff */
+   
+	uint32_t CAP_CAPTURE_CFG;	/* 0xb00 */
+	uint32_t CAP_TRIGGER_ADDR;	/* 0xb04 */
+	uint32_t CAP_READ_CTRL;		/* 0xb08 */
+	uint32_t unused16;		/* 0xb0c */
+	uint32_t CAP_CAPTURE_MATCH0;	/* 0xb10 */
+	uint32_t CAP_CAPTURE_MATCH1;	/* 0xb14 */
+	uint32_t CAP_CAPTURE_MATCH2;	/* 0xb18 */
+	uint32_t unused17;		/* 0xb1c */
+	uint32_t CAP_CAPTURE_MASK0;	/* 0xb20 */
+	uint32_t CAP_CAPTURE_MASK1;	/* 0xb24 */
+	uint32_t CAP_CAPTURE_MASK2;	/* 0xb28 */
+	uint32_t unused18;		/* 0xb2c */
+	uint32_t CAP_TRIGGER_MATCH0;	/* 0xb30 */
+	uint32_t CAP_TRIGGER_MATCH1;	/* 0xb34 */
+	uint32_t CAP_TRIGGER_MATCH2;	/* 0xb38 */
+	uint32_t unused19;		/* 0xb3c */
+	uint32_t CAP_TRIGGER_MASK0;	/* 0xb40 */
+	uint32_t CAP_TRIGGER_MASK1;	/* 0xb44 */
+	uint32_t CAP_TRIGGER_MASK2;	/* 0xb48 */
+	uint32_t unused20;		/* 0xb4c */
+	uint32_t CAP_READ_DATA[8];	/* 0xb50-0xb6f */
+	uint32_t unused21[164];		/* 0xb70-0xdff */
+
+	uint32_t SEC_INTR2_CPU_STATUS;	/* 0xe00 */
+	uint32_t SEC_INTR2_CPU_SET;	/* 0xe04 */
+	uint32_t SEC_INTR2_CPU_CLEAR;	/* 0xe08 */
+	uint32_t SEC_INTR2_CPU_MASK_STATUS;/* 0xe0c */
+	uint32_t SEC_INTR2_CPU_MASK_SET;/* 0xe10 */
+	uint32_t SEC_INTR2_CPU_MASK_CLEAR;/* 0xe14 */
+	uint32_t unused22[58];		/* 0xe18-0xeff */
+
+	uint32_t UBUSIF0_PERMCTL;	/* 0xf00 */
+	uint32_t UBUSIF1_PERMCTL;	/* 0xf04 */
+	uint32_t SRAM_REMAP_PERMCTL;	/* 0xf08 */
+	uint32_t AXIWIF_PERMCTL;	/* 0xf0c */
+	uint32_t CHNCFG_PERMCTL;	/* 0xf10 */
+	uint32_t MCCAP_PERMCTL;		/* 0xf14 */
+	uint32_t SCRAM_PERMCTL;		/* 0xf18 */
+	uint32_t RNG_PERMCTL;		/* 0xf1c */
+	uint32_t RNGCHK_PERMCTL;	/* 0xf20 */
+	uint32_t unused23[567];		/* 0xf24-0x17ff */
+
+	SecureRangeCheckers SEC_RANGE_CHK;/* 0x1800-0x18ff */
+	uint32_t unused24[31168];	/* 0x1900-0x1ffff */
+
+	DDRPhyControl PhyControl;	/* 0x20000 */
+	DDRPhyByteLaneControl PhyByteLane0Control;/* 0x20400 - 0x205ff */
+	DDRPhyByteLaneControl PhyByteLane1Control;/* 0x20600 - 0x207ff */
+} MEMCControl;
+
+
+#define MEMC ((volatile MEMCControl * const) MEMC_BASE)
+
+#endif /* _47622_DDR_H */
diff --git a/arch/arm/include/asm/arch-bcm47622/ethsw.h b/arch/arm/include/asm/arch-bcm47622/ethsw.h
new file mode 100644
index 0000000000..d871bfc463
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/ethsw.h
@@ -0,0 +1,40 @@
+
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT     12
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_MASK      (0x1f<<ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT)
+#define ETHSW_QPHY_CTRL_RESET_SHIFT          8
+#define ETHSW_QPHY_CTRL_RESET_MASK           (0x1<<ETHSW_QPHY_CTRL_RESET_SHIFT )
+#define ETHSW_QPHY_CTRL_CK25_DIS_SHIFT       7
+#define ETHSW_QPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_QPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_MASK    (0xf<<ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      6
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+
+#define ETHSW_SPHY_CTRL_PHYAD_SHIFT          8
+#define ETHSW_SPHY_CTRL_PHYAD_MASK           (0x1f<<ETHSW_SPHY_CTRL_PHYAD_SHIFT)
+#define ETHSW_SPHY_CTRL_RESET_SHIFT          5
+#define ETHSW_SPHY_CTRL_RESET_MASK           (0x1<<ETHSW_SPHY_CTRL_RESET_SHIFT )
+#define ETHSW_SPHY_CTRL_CK25_DIS_SHIFT       4
+#define ETHSW_SPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_SPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_MASK    (0x1<<ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      3
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+
+#define ETHSW_MDIO_BUSY                       (1 << 29)
+#define ETHSW_MDIO_FAIL                       (1 << 28)
+#define ETHSW_MDIO_CMD_SHIFT                  26
+#define ETHSW_MDIO_CMD_MASK                   (0x3<<ETHSW_MDIO_CMD_SHIFT) 
+#define ETHSW_MDIO_CMD_C22_READ               2
+#define ETHSW_MDIO_CMD_C22_WRITE              1
+#define ETHSW_MDIO_C22_PHY_ADDR_SHIFT         21
+#define ETHSW_MDIO_C22_PHY_ADDR_MASK          (0x1f<<ETHSW_MDIO_C22_PHY_ADDR_SHIFT)
+#define ETHSW_MDIO_C22_PHY_REG_SHIFT          16
+#define ETHSW_MDIO_C22_PHY_REG_MASK           (0x1f<<ETHSW_MDIO_C22_PHY_REG_SHIFT)
+#define ETHSW_MDIO_PHY_DATA_SHIFT             0
+#define ETHSW_MDIO_PHY_DATA_MASK              (0xffff<<ETHSW_MDIO_PHY_DATA_SHIFT)
+
diff --git a/arch/arm/include/asm/arch-bcm47622/misc.h b/arch/arm/include/asm/arch-bcm47622/misc.h
new file mode 100644
index 0000000000..ced098ff16
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/misc.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _47622_MISC_H
+#define _47622_MISC_H
+
+#define MISC_BASE          0xff802600
+
+/*
+ * Misc Register Set Definitions.
+ */
+typedef struct Misc {
+    uint32_t  miscStrapBus;                       /* 0x00 */
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           0
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_PCIE0_RC_MODE            (0x1 << 6)
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT      9
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ            (0x1 << MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT)
+#define MISC_STRAP_BUS_BOOTROM_BOOT             (0x1 << 12)
+    uint32_t  miscStrapOverride;                  /* 0x04 */
+    uint32_t  miscMaskUBUSErr;                    /* 0x08 */
+    uint32_t  miscPeriphCtrl;                     /* 0x0c */
+    uint32_t  miscSPImasterCtrl;                  /* 0x10 */
+    uint32_t  miscDierevid;                       /* 0x14 */
+    uint32_t  miscPeriphMiscCtrl;                 /* 0x18 */
+    uint32_t  miscPeriphMiscStat;                 /* 0x1c */
+    uint32_t  miscSoftResetB;                     /* 0x20 */
+    uint32_t  reserved0;                          /* 0x24 */
+    uint32_t  miscSWdebugNW[2];                   /* 0x28 */
+    uint32_t  miscWDresetCtrl;                    /* 0x30 */
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+typedef struct TopControl {
+   uint32_t      MiiPadCtl;          // 0x0
+   uint32_t      Rgmii1PadCtl;       // 0x4
+   uint32_t      Rgmii2PadCtl;       // 0x8
+   uint32_t      Rgmii3PadCtl;       // 0xc
+   uint32_t      MiiPullCtl;         // 0x10
+   uint32_t      Rgmii1PullCtl;      // 0x14
+   uint32_t      Rgmii2PullCtl;      // 0x18
+   uint32_t      Rgmii3PullCtl;      // 0x1c
+   uint32_t      SgmiiFiberDetect;   // 0x20
+   uint32_t      DgSensePadCtl;      // 0x24
+#define DG_CTRL_SHIFT   4
+#define DG_CTRL_MASK    0x00000030   
+#define DG_EN_SHIFT     3
+#define DG_TRIM_SHIFT   0
+#define DG_TRIM_MASK    0x00000007   
+   uint32_t      TpDirOverride0;     // 0x28
+   uint32_t      TpDirOverride1;     // 0x2c
+   uint32_t      RescalReadData0;    // 0x30
+   uint32_t      RescalReadData1;    // 0x34
+   uint32_t      reserved0;          // 0x38 
+   uint32_t      ResetStatus;        // 0x3c 
+#define PCIE_RESET_STATUS       0x10000000
+#define SW_RESET_STATUS         0x20000000
+#define HW_RESET_STATUS         0x40000000
+#define POR_RESET_STATUS        0x80000000
+#define RESET_STATUS_MASK       0xF0000000
+   uint32_t      TodSync;            // 0x40
+   uint32_t      Pm0Pm1RescalSts;    // 0x44
+   uint32_t      Pm2Pm3RescalSts;    // 0x48
+   uint32_t      SgbRescalSts;       // 0x4c
+   uint32_t      Pm0Pm1RescalCfg;    // 0x50
+   uint32_t      Pm2Pm3RescalCfg;    // 0x54
+   uint32_t      SgbRescalCfg;       // 0x58
+   uint32_t      Pm0Pm1TmonCfg;      // 0x5c
+   uint32_t      Pm2Pm3TmonCfg;      // 0x60
+   uint32_t      SgbTmonCfg;         // 0x64
+   uint32_t      MdioMasterSelect;   // 0x68
+   uint32_t      SwControlReg;       // 0x6c
+   uint32_t      Reg2P5VDectCtrl;    // 0x70
+   uint32_t      OrionIntPending;    // 0x74
+   uint32_t      DslClockSample;     // 0x78
+   uint32_t      LdoCtl;             // 0x7c
+#define LDO_VREG_CTRL_EN           0x400000
+#define LDO_VREG_CTRL_SHIFT        1
+#define LDO_VREG_CTRL_MASK         (0x1fffff << LDO_VREG_CTRL_SHIFT)
+#define LDO_VREG_CTRL_TRIM_SHIFT   2
+#define LDO_VREG_CTRL_TRIM_MASK    (0xf << LDO_VREG_CTRL_TRIM_SHIFT)
+#define LDO_VREG_CTRL_SELECT_SHIFT 6
+#define LDO_VREG_CTRL_SELECT_MASK  (0xf << LDO_VREG_CTRL_SELECT_SHIFT)
+#define LDO_VREG_CTRL_PWRDN        0x1
+} TopControl;
+
+#define TOP_CONTROL_BASE           0xff85a000
+#define TOPCTRL ((volatile TopControl * const) TOP_CONTROL_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm47622/otp.h b/arch/arm/include/asm/arch-bcm47622/otp.h
new file mode 100644
index 0000000000..38ad685399
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/otp.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _47622_OTP_H
+#define _47622_OTP_H
+
+
+#define JTAG_OTP_BASE   0xff802800
+
+/* row 8 */
+#define OTP_CPU_CORE_CFG_ROW            8
+#define OTP_CPU_CORE_CFG_SHIFT          28
+#define OTP_CPU_CORE_CFG_MASK           0x7
+
+/* row 9 */
+#define OTP_CPU_CLOCK_FREQ_ROW          9
+#define OTP_CPU_CLOCK_FREQ_SHIFT        0
+#define OTP_CPU_CLOCK_FREQ_MASK         0x7
+
+#define OTP_LDO_TRIM_ROW                9
+#define OTP_LDO_TRIM_SHIFT              28
+#define OTP_LDO_TRIM_MASK               0xf
+
+/* row 14 */
+#define OTP_SGMII_DISABLE_ROW           14
+#define OTP_SGMII_DISABLE_SHIFT         5
+#define OTP_SGMII_DISABLE_MASK          0x1
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          7
+
+/* row 23 */
+#define OTP_CUST_MFG_MRKTID_ROW                 23
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+/* row 9 */
+#define OTP_LDO_TRIM_ROW                9
+#define OTP_LDO_TRIM_SHIFT              28
+#define OTP_LDO_TRIM_MASK               0xf
+
+/* row 14 */
+#define OTP_SGMII_DISABLE_ROW           14
+#define OTP_SGMII_DISABLE_SHIFT         5
+#define OTP_SGMII_DISABLE_MASK          0x1
+
+
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_CPU_CORE_CFG, OTP_CPU_CORE_CFG_ROW, OTP_CPU_CORE_CFG_MASK, OTP_CPU_CORE_CFG_SHIFT, 1},				\
+	{OTP_MAP_LDO_TRIM, OTP_LDO_TRIM_ROW, OTP_LDO_TRIM_MASK, OTP_LDO_TRIM_SHIFT, 1},				\
+	}
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm47622/pmc.h b/arch/arm/include/asm/arch-bcm47622/pmc.h
new file mode 100644
index 0000000000..b7402bd156
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/pmc.h
@@ -0,0 +1,336 @@
+#ifndef PMC_H
+#define PMC_H 
+/*
+ * Power Management Control
+ */
+typedef struct PmcCtrlReg {
+    uint32_t gpTmr0Ctl;           /* 0x018 */
+    uint32_t gpTmr0Cnt;           /* 0x01c */
+    uint32_t gpTmr1Ctl;           /* 0x020 */
+    uint32_t gpTmr1Cnt;           /* 0x024 */
+    uint32_t hostMboxIn;          /* 0x028 */
+    uint32_t hostMboxOut;         /* 0x02c */
+    uint32_t reserved[4];         /* 0x030 */
+    uint32_t dmaCtrl;             /* 0x040 */
+    uint32_t dmaStatus;           /* 0x044 */
+    uint32_t dma0_3FifoStatus;    /* 0x048 */
+    uint32_t reserved1[4];	    /* 0x04c */
+    uint32_t diagControl;         /* 0x05c */
+    uint32_t diagHigh;            /* 0x060 */
+    uint32_t diagLow;             /* 0x064 */
+    uint32_t reserved8;           /* 0x068 */
+    uint32_t addr1WndwMask;       /* 0x06c */
+    uint32_t addr1WndwBaseIn;     /* 0x070 */
+    uint32_t addr1WndwBaseOut;    /* 0x074 */
+    uint32_t addr2WndwMask;       /* 0x078 */
+    uint32_t addr2WndwBaseIn;     /* 0x07c */
+    uint32_t addr2WndwBaseOut;    /* 0x080 */
+    uint32_t scratch;             /* 0x084 */
+    uint32_t reserved9;           /* 0x088 */
+    uint32_t softResets;          /* 0x08c */
+    uint32_t reserved2;           /* 0x090 */
+    uint32_t m4keCoreStatus;      /* 0x094 */
+    uint32_t reserved3;           /* 0x098 */
+    uint32_t ubSlaveTimeout;      /* 0x09c */
+    uint32_t diagEn;              /* 0x0a0 */
+    uint32_t devTimeout;          /* 0x0a4 */
+    uint32_t ubusErrorOutMask;    /* 0x0a8 */
+    uint32_t diagCaptStopMask;    /* 0x0ac */
+    uint32_t revId;               /* 0x0b0 */
+    uint32_t reserved4[4];        /* 0x0b4 */
+    uint32_t diagCtrl;            /* 0x0c4 */
+    uint32_t diagStat;            /* 0x0c8 */
+    uint32_t diagMask;            /* 0x0cc */
+    uint32_t diagRslt;            /* 0x0d0 */
+    uint32_t diagCmp;             /* 0x0d4 */
+    uint32_t diagCapt;            /* 0x0d8 */    
+    uint32_t diagCnt;             /* 0x0dc */
+    uint32_t diagEdgeCnt;         /* 0x0e0 */
+    uint32_t reserved5[4];	    /* 0x0e4 */
+    uint32_t smisc_bus_config;    /* 0x0f4 */
+    uint32_t lfsr;                /* 0x0f8 */
+    uint32_t dqm_pac_lock;        /* 0x0fc */
+    uint32_t l1_irq_4ke_mask;     /* 0x100 */
+    uint32_t l1_irq_4ke_status;   /* 0x104 */
+    uint32_t l1_irq_mips_mask;    /* 0x108 */
+    uint32_t l1_irq_mips_status;  /* 0x10c */
+    uint32_t l1_irq_mips1_mask;   /* 0x110 */
+    uint32_t reserved6[3];        /* 0x114 */
+    uint32_t l2_irq_gp_mask;      /* 0x120 */
+    uint32_t l2_irq_gp_status;    /* 0x124 */
+    uint32_t l2_irq_gp_set;       /* 0x128 */
+    uint32_t reserved7;           /* 0x12c */
+    uint32_t gp_in_irq_mask;      /* 0x130 */
+    uint32_t gp_in_irq_status;    /* 0x134 */
+    uint32_t gp_in_irq_set;       /* 0x138 */
+    uint32_t gp_in_irq_sense;     /* 0x13c */
+    uint32_t gp_in;               /* 0x140 */
+    uint32_t gp_out;              /* 0x144 */
+} PmcCtrlReg;
+
+typedef struct PmcDmaReg {
+	/* 0x00 */
+	uint32_t src;
+	uint32_t dest;
+	uint32_t cmdList;
+	uint32_t lenCtl;
+	/* 0x10 */
+	uint32_t rsltSrc;
+	uint32_t rsltDest;
+	uint32_t rsltHcs;
+	uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+	/* 0x00 */
+	uint32_t bufSize;
+	uint32_t bufBase;
+	uint32_t idx2ptrIdx;
+	uint32_t idx2ptrPtr;
+	/* 0x10 */
+	uint32_t unused[2];
+	uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+	uint32_t freqScalarCtrl; /* 0x3c */
+	uint32_t freqScalarMask; /* 0x40 */
+} PmcPerfPowReg;
+
+typedef struct PmcDQMPac {
+    uint32_t dqmPac[32];
+} PmcDQMPac;
+
+typedef struct PmcDQMReg {
+	uint32_t cfg;                     /* 0x1c00 */
+	uint32_t _4keLowWtmkIrqMask;      /* 0x1c04 */
+	uint32_t mipsLowWtmkIrqMask;      /* 0x1c08 */
+	uint32_t lowWtmkIrqMask;          /* 0x1c0c */
+	uint32_t _4keNotEmptyIrqMask;     /* 0x1c10 */
+	uint32_t mipsNotEmptyIrqMask;     /* 0x1c14 */
+	uint32_t notEmptyIrqSts;          /* 0x1c18 */
+	uint32_t queueRst;                /* 0x1c1c */
+	uint32_t notEmptySts;             /* 0x1c20 */
+	uint32_t nextAvailMask;           /* 0x1c24 */
+	uint32_t nextAvailQueue;          /* 0x1c28 */
+	uint32_t mips1LowWtmkIrqMask;     /* 0x1c2c */
+	uint32_t mips1NotEmptyIrqMask;    /* 0x1c30 */
+	uint32_t autoSrcPidInsert;        /* 0x1c34 */
+    uint32_t timerIrqStatus;          /* 0x1c38 */
+    uint32_t timerStatus;             /* 0x1c3c */
+    uint32_t _4keTimerIrqMask;        /* 0x1c40 */
+    uint32_t mipsTimerIrqMask;        /* 0x1c44 */
+    uint32_t mips1TimerIrqMask;       /* 0x1c48 */
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+	uint32_t cntr[10];
+	uint32_t unused[6];	/* 0x28-0x3f */
+	uint32_t cntrIrqMask;
+	uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+	uint32_t size;
+	uint32_t cfga;
+	uint32_t cfgb;
+	uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+	uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+	uint32_t qNumFull[32];
+	uint32_t qNumEmpty[32];
+	uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+typedef struct SSBMaster {
+    uint32_t ssbmControl;     /* 0x0060 */
+    uint32_t ssbmWrData;      /* 0x0064 */
+    uint32_t ssbmRdData;      /* 0x0068 */
+    uint32_t ssbmStatus;      /* 0x006c */
+} SSBMaster;
+
+typedef struct PmmReg {
+    uint32_t memPowerCtrl;            /* 0x0000 */
+    uint32_t regSecurityConfig;       /* 0x0004 */
+} PmmReg;
+
+typedef struct keyholeReg {
+    uint32_t ctrlSts;
+    uint32_t wrData;
+    uint32_t mutex;
+    uint32_t rdData;
+} keyholeReg;
+
+typedef struct PmbBus {
+    uint32_t config;          /* 0x0100 */
+    uint32_t arbiter;         /* 0x0104 */
+    uint32_t timeout;         /* 0x0108 */
+    uint32_t unused1;         /* 0x010c */
+    keyholeReg keyhole[4];  /* 0x0110-0x014f */
+    uint32_t unused2[44];     /* 0x0150-0x01ff */
+    uint32_t map[64];         /* 0x0200-0x02ff */ 
+}PmbBus;
+
+typedef struct  CoreCtrl {
+    uint32_t  coreEnable;         /* 0x0400 */
+    uint32_t  autoresetControl;   /* 0x0404 */
+    uint32_t  coreIdle;           /* 0x0408 */
+    uint32_t  coreResetCause;     /* 0x040c */
+    uint32_t  memPwrDownCtrl0;    /* 0x0410 */
+    uint32_t  memPwrDownSts0;     /* 0x0414 */
+    uint32_t  memPwrDownCtrl1;    /* 0x0418 */
+    uint32_t  memPwrDownSts1;     /* 0x041c */
+    uint32_t  sysFlg0Status;      /* 0x0420 */
+    uint32_t  sysFlg0Set;         /* 0x0424 */
+    uint32_t  sysFlg0Clear;       /* 0x0428 */
+    uint32_t  unused1;            /* 0x042c */
+    uint32_t  usrFlg0Status;      /* 0x0430 */
+    uint32_t  usrFlg0Set;         /* 0x0434 */
+    uint32_t  usrFlg0Clear;       /* 0x0438 */
+    uint32_t  unused2;            /* 0x043c */
+    uint32_t  subsystemRev;       /* 0x0440 */
+    uint32_t  resetVector;        /* 0x0444 */
+} CoreCtrl;
+
+typedef struct  CoreState {
+    uint32_t  sysMbx[8];          /* 0x0480 */
+    uint32_t  usrMbx[8];          /* 0x04a0 */
+    uint32_t  sysMtx[4];          /* 0x04c0 */
+    uint32_t  usrMtx[8];          /* 0x04d0 */
+} CoreState;
+
+typedef struct  CoreIntr {
+    uint32_t  irqStatus;          /* 0x0500 */
+    uint32_t  irqSet;             /* 0x0504 */
+    uint32_t  irqClear;           /* 0x0508 */
+    uint32_t  unused1;            /* 0x050c */
+    uint32_t  srqStatus;          /* 0x0510 */
+    uint32_t  srqSet;             /* 0x0514 */
+    uint32_t  srqClear;           /* 0x0518 */
+    uint32_t  unused2;            /* 0x051c */
+    uint32_t  drqStatus;          /* 0x0520 */
+    uint32_t  drqSet;             /* 0x0524 */
+    uint32_t  drqClear;           /* 0x0528 */
+    uint32_t  unused3;            /* 0x052c */
+    uint32_t  frqStatus;          /* 0x0530 */
+    uint32_t  frqSet;             /* 0x0534 */
+    uint32_t  frqClear;           /* 0x0538 */
+    uint32_t  unused4;            /* 0x053c */
+    uint32_t  hostIrqLatched;     /* 0x0540 */
+    uint32_t  hostIrqSet;         /* 0x0544 */
+    uint32_t  hostIrqClear;       /* 0x0548 */
+    uint32_t  hostIrqEnable;      /* 0x054c */
+    uint32_t  obusFaultStatus;    /* 0x0550 */
+    uint32_t  obusFaultClear;     /* 0x0554 */
+    uint32_t  obusFaultAddr;      /* 0x0558 */
+} CoreIntr;
+
+typedef struct CoreProfile {
+    uint32_t  mutex;              /* 0x0580 */
+    uint32_t  lastConfPcLo;       /* 0x0584 */
+    uint32_t  lastConfPcHi;       /* 0x0588 */
+    uint32_t  lastPcLo;           /* 0x058c */
+    uint32_t  lastPcHi;           /* 0x0590 */
+    uint32_t  braTargetPc0Lo;     /* 0x0594 */
+    uint32_t  braTargetPc0Hi;     /* 0x0598 */
+    uint32_t  braTargetPc1Lo;     /* 0x059c */
+    uint32_t  braTargetPc1Hi;     /* 0x05a0 */
+    uint32_t  braTargetPc2Lo;     /* 0x05a4 */
+    uint32_t  braTargetPc2Hi;     /* 0x05a8 */
+    uint32_t  braTargetPc3Lo;     /* 0x05ac */
+    uint32_t  braTargetPc3Hi;     /* 0x05b0 */
+    uint32_t  unused[3];          /* 0x05b4-0x05bf */
+    uint32_t  profSampleW[4];     /* 0x05c0 */
+} CoreProfile;
+
+typedef struct MaestroMisc {
+    CoreCtrl coreCtrl;          /* 0x0400 */
+    uint32_t   unused1[14];       /* 0x0448-0x047f */
+    CoreState coreState;        /* 0x0480 */
+    uint32_t   unused2[4];        /* 0x04f0-0x04ff */
+    CoreIntr interrupt;         /* 0x0500 */
+    uint32_t   unused3[9];        /* 0x055c-0x057f */
+    CoreProfile profile;        /* 0x0580 */
+} MaestroMisc;
+
+typedef struct Pmc {
+    uint32_t unused0[1030];
+    PmcCtrlReg ctrl;		            /* 0x1018 */
+    uint32_t unused1[622];	            /* 0x1148-0x1cff */
+    PmcDQMPac dqmPac;                   /* 0x1b00 */
+    uint32_t unused5[32];                 /* 0x1b80-0x1bff */
+    PmcDQMReg dqm;			            /* 0x1c00 */
+    uint32_t unused6[749];		        /* 0x1c4c-0x27ff */
+    uint32_t qStatus[32];		            /* 0x2800 */
+    uint32_t unused7[480];	            /* 0x2880-0x2fff */
+    PmcDqmQMibReg qMib;		            /* 0x3000 */
+    uint32_t unused8[928];	            /* 0x3180-0x3fff */
+    PmcDqmQCtrlReg dqmQCtrl[8]; 	    /* 0x4000 */
+    uint32_t unused9[992];                /* 0x4080-0x4fff */
+    PmcDqmQDataReg dqmQData[8]; 	    /* 0x5000 */
+} Pmc;
+
+#define PMC_BASE 0x80300000
+#define PMC ((volatile Pmc * const) PMC_BASE)
+
+typedef struct Procmon {
+    uint32_t unused00[256];
+    MaestroMisc maestroReg;             /* 0x00400 */
+    uint32_t unused10[32396];             /* 0x005d0-0x1ffff */
+    PmmReg  pmm;                        /* 0x20000 */
+    uint32_t unused11[22];                /* 0x20008-0x2005f */
+    SSBMaster ssbMasterCtrl;            /* 0x20060 */
+    uint32_t unused12[36];                /* 0x20070-0x200ff */
+    PmbBus pmb;                         /* 0x20100 */
+    uint32_t unused13[32576];             /* 0x20300-0x3ffff */
+    uint32_t qsm[128];                    /* 0x40000-0x401ff */
+    uint32_t unused14[65408];             /* 0x40200-0x7ffff */
+    uint32_t dtcm[1024];                  /* 0x80000-0x80fff */
+} Procmon;
+#define PROC_MON_BASE 0x80300000
+#define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
+
+typedef struct PMSSBMasterControl {
+        uint32_t control;
+        uint32_t wr_data;
+        uint32_t rd_data;
+} PMSSBMasterControl;
+
+typedef struct
+{
+    uint32_t  control;
+#define PMC_PMBM_START                      (1 << 31)
+#define PMC_PMBM_TIMEOUT                    (1 << 30)
+#define PMC_PMBM_SLAVE_ERR                  (1 << 29)
+#define PMC_PMBM_BUSY                       (1 << 28)
+#define PMC_PMBM_BUS_SHIFT              (20)
+#define PMC_PMBM_Read                       (0 << 24)
+#define PMC_PMBM_Write                      (1 << 24)
+    uint32_t  wr_data;
+    uint32_t  mutex;
+    uint32_t  rd_data;
+} PMB_keyhole_reg;
+
+typedef struct PMBMaster {
+    uint32_t config;
+#define PMB_NUM_REGS_SHIFT (20)
+#define PMB_NUM_REGS_MASK  (0x3ff)
+    uint32_t arbitger;
+    uint32_t timeout;
+    uint32_t reserved;
+    PMB_keyhole_reg keyhole[4];
+    uint32_t reserved1[44];
+    uint32_t map[64];
+} PMBMaster;
+#define PMB_BASE (0x80200000+0x00120100)
+#define PMB ((volatile PMBMaster * const) PMB_BASE)
+
+
+#define PERF_PHYS_BASE              0xff800000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm47622/pmc_addr.h b/arch/arm/include/asm/arch-bcm47622/pmc_addr.h
new file mode 100644
index 0000000000..1908b73159
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/pmc_addr.h
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ 
+*/
+
+#ifndef PMC_ADDR_47622_H__
+#define PMC_ADDR_47622_H__
+
+#define PMB_BUS_ID_SHIFT         12
+
+#define PMB_BUS_PERIPH           1
+#define PMB_ADDR_PERIPH          (16 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH         4
+
+#define PMB_BUS_CRYPTO           0
+#define PMB_ADDR_CRYPTO          (1 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CRYPTO         1
+
+#define PMB_BUS_PVTMON           0
+#define PMB_ADDR_PVTMON          (2 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON         0
+
+#define PMB_BUS_CHIP_CLKRST      0
+#define PMB_ADDR_CHIP_CLKRST     (3 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST    0
+
+#define PMB_BUS_USB31_20         0
+#define PMB_ADDR_USB31_20        (4 | PMB_BUS_USB31_20 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB31_20       3
+
+#define PMB_BUS_WLAN0            0
+#define PMB_ADDR_WLAN0           (5 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0          1
+
+#define PMB_BUS_WLAN0_PHY1       0
+#define PMB_ADDR_WLAN0_PHY1      (6 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY1     1
+
+#define PMB_BUS_WLAN0_PHY2       0
+#define PMB_ADDR_WLAN0_PHY2      (7 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY2     1
+
+#define PMB_BUS_WLAN1            0
+#define PMB_ADDR_WLAN1           (8 | PMB_BUS_WLAN1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1          1
+
+#define PMB_BUS_WLAN1_PHY1       0
+#define PMB_ADDR_WLAN1_PHY1      (9 | PMB_BUS_WLAN1_PHY1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1_PHY1     1
+
+#define PMB_BUS_WLAN1_PHY2       0
+#define PMB_ADDR_WLAN1_PHY2      (10 | PMB_BUS_WLAN1_PHY2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1_PHY2     1
+
+#define PMB_BUS_MEMC             0
+#define PMB_ADDR_MEMC            (11 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC           1
+
+#define PMB_BUS_SYSP             0
+#define PMB_ADDR_SYSP            (0 | PMB_BUS_SYSP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSP           3
+
+#define PMB_BUS_PCIE0            1
+#define PMB_ADDR_PCIE0           (17 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0          1
+
+#define PMB_BUS_ORION_CPU0       0
+#define PMB_ADDR_ORION_CPU0      (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0     1
+
+#define PMB_BUS_ORION_CPU1       0
+#define PMB_ADDR_ORION_CPU1      (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1     1
+
+#define PMB_BUS_ORION_CPU2       0
+#define PMB_ADDR_ORION_CPU2      (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU2     1
+
+#define PMB_BUS_ORION_CPU3       0
+#define PMB_ADDR_ORION_CPU3      (35 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU3     1
+
+#define PMB_BUS_ORION_NONCPU     0
+#define PMB_ADDR_ORION_NONCPU    (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU   1
+
+#define PMB_BUS_BIU_PLL          0
+#define PMB_ADDR_BIU_PLL         (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL        0
+
+#define PMB_BUS_BIU_BPCM         0
+#define PMB_ADDR_BIU_BPCM        (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM       1
+
+#define PMB_BUS_PCM              PMB_BUS_PERIPH
+#define PMB_ADDR_PCM             (16 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCM            4
+
+enum {
+	PCM_Zone_Main,
+	PCM_Zone_PCM = 3
+};
+
+//--------- SOFT Reset bits for PCM ------------------------
+#define   BPCM_PCM_SRESET_PCM_N       0x00000040
+
+#define RCAL_0P25UM_HORZ          0
+#define RCAL_0P25UM_VERT          1
+#define RCAL_0P5UM_HORZ           2
+#define RCAL_0P5UM_VERT           3
+#define RCAL_1UM_HORZ             4
+#define RCAL_1UM_VERT             5
+#define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
+#define PMMISC_RMON_VALID_MASK    (0x1<<16)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm47622/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm47622/pmc_drv_cfg.h
new file mode 100644
index 0000000000..ac92fbd4c0
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/pmc_drv_cfg.h
@@ -0,0 +1,40 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_3_X
+#define PMC_IMPL_3_2
+
+#define PMC_LOG_IN_DTCM		1
+#define PMC_GETRCAL_SUPPORT 1
+#define PMC_CPUTEMP_SUPPORT 1
+#define PMC_RAM_BOOT 1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm47622/rng.h b/arch/arm/include/asm/arch-bcm47622/rng.h
new file mode 100644
index 0000000000..63e66ddbcf
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _47622_RNG_H
+#define _47622_RNG_H
+
+#define RNG_BASE	0xff800b80
+
+typedef struct Rng {
+	uint32_t ctrl0;			/* 0x00 */
+	uint32_t rngSoftReset;		/* 0x04 */
+	uint32_t rbgSoftReset;		/* 0x08 */
+	uint32_t totalBitCnt;		/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;			/* 0x14 */
+	uint32_t intStatus;		/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL	(0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL	(0x1<<2)
+	uint32_t intEn;			/* 0x1c */
+	uint32_t rngFifoData;		/* 0x20 */
+	uint32_t fifoCnt;		/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS	0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS	0x33
+	uint32_t perm;			/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm47622/ubus4.h b/arch/arm/include/asm/arch-bcm47622/ubus4.h
new file mode 100644
index 0000000000..dd927469b2
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm47622/ubus4.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _47622_UBUS4_H
+#define _47622_UBUS4_H
+
+#define MST_PORT_NODE_PER_PHYS_BASE         0x83010000
+#define MST_PORT_NODE_USB_PHYS_BASE         0x83018000
+#define MST_PORT_NODE_CPU_PHYS_BASE         0x83020000
+#define MST_PORT_NODE_PMC_PHYS_BASE         0x83028000 
+#define MST_PORT_NODE_PCIE0_PHYS_BASE       0x83030000
+#define MST_PORT_NODE_SYSPORT_PHYS_BASE     0x83038000
+#define MST_PORT_NODE_SYSPORT1_PHYS_BASE    0x83040000
+#define MST_PORT_NODE_SPU_PHYS_BASE         0x83048000
+#define MST_PORT_NODE_WIFI_PHYS_BASE        0x83050000
+#define MST_PORT_NODE_WIFI1_PHYS_BASE       0x83058000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4908/BPCM.h b/arch/arm/include/asm/arch-bcm4908/BPCM.h
new file mode 100644
index 0000000000..3c52f18be4
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/BPCM.h
@@ -0,0 +1,702 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t sw_strap:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t z2_p_wan_phy_sel:3;	/* 0-2 */
+		uint32_t reserved0:1;	/* 3 */
+		uint32_t z2_switch_p3_phy_sel:3;	/* 4-6 */
+		uint32_t reserved1:1;	/* 7 */
+		uint32_t z2_switch_p4_phy_sel:3;	/* 8-10 */
+		uint32_t reserved2:1;	/* 11 */
+		uint32_t z0_mux_sel:1;	/* 12 */
+		uint32_t z1_gphy_mux_sel:1;	/* 13 */
+		uint32_t z2_gphy_mux_sel:1;	/* 14 */
+		uint32_t z2_crossbar_mux_sel:1;	/* 15 */
+		uint32_t reserved3:1;	/* 16 */
+		uint32_t z1_pda_en:1;	/* 17 */
+		uint32_t z1_ck250_clk_en:1;	/* 18 */
+		uint32_t z1_ck25_clk_dis:1;	/* 19 */
+		uint32_t reserved4:2;	/* 20-21 */
+		uint32_t z2_ck250_clk_en:1;	/* 22 */
+		uint32_t z2_ck25_clk_dis:1;	/* 23 */
+		uint32_t z2_serdes_clk_en:1;	/* 24 */
+		uint32_t z2_serdes_reset_mdioregs:1;	/* 25 */
+		uint32_t z2_sedes_reset_pll:1;	/* 26 */
+		uint32_t z2_serdes_reset:1;	/* 27 */
+		uint32_t z2_serdes_mux_sel:1;	/* 28 */
+		uint32_t reserved5:1;	/* 29 */
+		uint32_t z1_gphy_reset:1;	/* 30 */
+		uint32_t z2_gphy_reset:1;	/* 31 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+        uint32_t reserved:32;
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	BPCM_ZONE_N_FREQ_SCALAR_CONTROL freq_scalar_control;
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	BPCM_SGPHY_CNTL sgphy_cntl;	// offset = 0x38, actual offset = 14
+	BPCM_SGPHY_STATUS sgphy_status;	// offset = 0x3c, actual offset = 15
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	uint32_t rvrsd[2];
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_VDSL_REGS;		// total offset space = 4096
+
+#define BPCMVDSLOffset(reg)	offsetof(BPCM_VDSL_REGS,reg)
+#define BPCMVDSLRegOffset(reg)	(BPCMVDSLOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	uint32_t decndiv;	// offset = 0x44, actual offset = 0x11
+	uint32_t decpdiv;	// offset = 0x48, actual offset = 0x12
+	uint32_t decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved1;	// offset = 0x2c, actual offset = 11
+	uint32_t clkrst_cfg;	// offset = 0x30, actual offset = 12
+	uint32_t clkrst_control;	// offset = 0x34, actual offset = 13
+	uint32_t xtal_control;	// offset = 0x38, actual offset = 14
+	uint32_t clkrst_stat;	// offset = 0x3c, actual offset = 15
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4908/brom.h b/arch/arm/include/asm/arch-bcm4908/brom.h
new file mode 100644
index 0000000000..f35d6d054b
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4908_BROM_H
+#define _4908_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4908/cpu.h b/arch/arm/include/asm/arch-bcm4908/cpu.h
new file mode 100644
index 0000000000..9f157db504
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/cpu.h
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+
+#define BIUCTRL_BASE                0x81062000
+#define BOOTLUT_BASE                0xffff0000
+
+typedef struct BIUArchRegion {
+	uint32_t addr_ulimit;
+	uint32_t addr_llimit;
+	uint32_t permission;
+	uint32_t access_right_ctrl;
+} BIUArchRegion;
+
+typedef struct BIUArch {
+	BIUArchRegion region[8];	/* 0x0 */
+	uint32_t unused[95];	/* 0x80 */
+	uint32_t scratch;	/* 0x1fc */
+} BIUArch;
+
+#define BIUARCH ((volatile BIUArch * const) BIUARCH_BASE)
+
+typedef struct BIUCpuBusRange {
+#define ULIMIT_SHIFT 4
+#define BUSNUM_MASK 0x0000000FU
+
+#define BUSNUM_UBUS 1
+#define BUSNUM_RBUS 2
+#define BUSNUM_RSVD 3
+#define BUSNUM_MCP0 4
+#define BUSNUM_MCP1 5
+#define BUSNUM_MCP2 6
+
+	uint32_t ulimit;
+	uint32_t llimit;
+} BIUCpuBusRange;
+
+typedef struct BIUCpuAccessRightViol {
+	uint32_t addr;
+	uint32_t upper_addr;
+	uint32_t detail_addr;
+} BIUCpuAccessRightViol;
+
+typedef struct BIUCpuBPCMAVS {
+	uint32_t bpcm_id;
+	uint32_t bpcm_capability;
+} BIUCpuBPCMAVS;
+
+typedef struct BIUCtrl {
+	BIUCpuBusRange bus_range[11];	/* 0x0 */
+	uint32_t secure_reset_hndshake;
+	uint32_t secure_soft_reset;
+	BIUCpuAccessRightViol access_right_viol[2];	/* 0x60 */
+	uint32_t rac_cfg0;
+	uint32_t rac_cfg1;
+	uint32_t rac_cfg2;	/* 0x80 */
+	uint32_t rac_flush;
+	uint32_t power_cfg;
+#define BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON_SHIFT 4
+#define BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON      (0x1<<BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON_SHIFT)
+	uint32_t reset_cfg;
+#define BIU_CPU_CTRL_RST_CFG_CPU0_RESET_SHIFT       0
+#define BIU_CPU_CTRL_RST_CFG_CPU0_RESET             (0x1<<BIU_CPU_CTRL_RST_CFG_CPU0_RESET_SHIFT)
+	uint32_t clock_cfg;	/* 0x90 */
+#define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT    8
+#define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_MASK     (0xf<<BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT)
+#define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_DIV1     (0<<BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT)
+#define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_DIV2     (1<<BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT)
+#define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_DIV3     (2<<BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT)
+#define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_DIV4     (3<<BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT)
+#define BIU_CPU_CTRL_CLK_CFG_SAFE_CLOCK_MODE_SHIFT  4
+#define BIU_CPU_CTRL_CLK_CFG_SAFE_CLOCK_MODE_MASK   (1<<BIU_CPU_CTRL_CLK_CFG_SAFE_CLOCK_MODE_SHIFT)
+#define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT        0
+#define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_MASK         (0xf<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
+#define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_DIV1         (0<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
+#define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_DIV2         (1<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
+#define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_DIV4         (2<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
+#define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_DIV8         (3<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
+#define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_DIV16        (4<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
+	uint32_t cluster_clk_ctrl[2];
+	uint32_t cluster_clk_pattern[2];
+	uint32_t cluster_clk_ramp[2];
+	uint32_t misc_cfg;
+	uint32_t credit;	/* 0xb0 */
+	uint32_t mcp_flow;
+	uint32_t periphbase_gic;
+	uint32_t periphbase_gic_web;
+	uint32_t wfx_state;	/* 0xc0 */
+	uint32_t cpu_pwr_zone_ctrl[8];
+#define BIU_CPU_CTRL_PWR_ZONE_CTRL_ZONE_RESET_SHIFT 31
+#define BIU_CPU_CTRL_PWR_ZONE_CTRL_ZONE_RESET       (1<<BIU_CPU_CTRL_PWR_ZONE_CTRL_ZONE_RESET_SHIFT)
+#define BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_UP_REQ_SHIFT 10
+#define BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_UP_REQ       (1<<BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_UP_REQ_SHIFT)
+#define BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_DN_REQ_SHIFT 9
+#define BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_DN_REQ       (1<<BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_DN_REQ_SHIFT)
+	uint32_t cpu_pwr_zone_cfg1[8];
+	uint32_t cpu_pwr_zone_cfg2[8];
+	uint32_t c0l2_pwr_zone_ctrl;	/* 0x124 */
+	uint32_t c0l2_pwr_zone_cfg1;
+	uint32_t c0l2_pwr_zone_cfg2;
+	uint32_t c1l2_pwr_zone_ctrl;
+	uint32_t c1l2_pwr_zone_cfg1;
+	uint32_t c1l2_pwr_zone_cfg2;
+	uint32_t sysif_pwr_zone_ctrl;
+	uint32_t sysif_pwr_zone_cfg1;
+	uint32_t sysif_pwr_zone_cfg2;
+	BIUCpuBPCMAVS cpu_bpcm_avs[8];	/* 0x148 */
+	BIUCpuBPCMAVS l2biu_bpcm_avs[3];	/* 0x188 */
+	uint32_t therm_throttle_temp;	/* 0x1a0 */
+	uint32_t term_throttle_irq_cfg;
+	uint32_t therm_irq_high;
+	uint32_t therm_irq_low;
+	uint32_t therm_misc_threshold;	/* 0x1b0 */
+	uint32_t therm_irq_misc;
+	uint32_t defeature;
+	uint32_t defeature2;
+	uint32_t defeature_key;	/* 0x1c0 */
+	uint32_t debug_rom_addr;
+	uint32_t debug_tracectrl;
+	uint32_t axi_cfg;
+	uint32_t revision;	/* 0x1d0 */
+	uint32_t patchlevel;
+	uint32_t ubus_cfg;	/* 0x1d8 */
+	uint32_t ubus_cfg_window[8];
+	uint32_t power_state;
+	uint32_t phys_config;	/* 0x200 */
+	uint32_t unused[126];	/* 0x204 */
+	uint32_t scratch;	/* 0x3fc */
+} BIUCtrl;
+
+#define BIUCTRL ((volatile BIUCtrl * const) BIUCTRL_BASE)
+
+typedef struct Boot_LUT {
+	uint32_t bootLut[8];	/* 0x00 */
+	uint32_t bootLutRst;	/* 0x20 */
+	uint32_t bootLutUnd;	/* 0x24 */
+	uint32_t bootLutSwi;	/* 0x28 */
+	uint32_t bootLutPrf;	/* 0x2c */
+	uint32_t bootLutAbt;	/* 0x30 */
+	uint32_t bootLutUnu;	/* 0x34 */
+	uint32_t bootLutIrq;	/* 0x38 */
+	uint32_t bootLutFiq;	/* 0x3c */
+	uint32_t bootLutPer;	/* 0x40 */
+} Boot_LUT;
+#define BOOT_LUT ((volatile Boot_LUT * const) BOOTLUT_BASE)
diff --git a/arch/arm/include/asm/arch-bcm4908/ddr.h b/arch/arm/include/asm/arch-bcm4908/ddr.h
new file mode 100644
index 0000000000..0f2c2c3c77
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/ddr.h
@@ -0,0 +1,587 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4908_DDR_H
+#define _4908_DDR_H
+
+#define MEMC_BASE        0x80018000	/* DDR IO Buf Control */
+
+typedef struct UBUSInterface {
+	uint32_t CFG;		/* 0x00 */
+	uint32_t ESRCID_CFG;	/* 0x04 */
+#define UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT   0x0
+#define UBUSIF_CFG_WRITE_REPLY_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT)
+#define UBUSIF_CFG_WRITE_BURST_MODE_SHIFT   0x1
+#define UBUSIF_CFG_WRITE_BURST_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_BURST_MODE_SHIFT)
+#define UBUSIF_CFG_INBAND_ERR_MASK_SHIFT    0x2
+#define UBUSIF_CFG_INBAND_ERR_MASK_MASK     (0x1<< UBUSIF_CFG_INBAND_ERR_MASK_SHIFT)
+#define UBUSIF_CFG_OOB_ERR_MASK_SHIFT       0x3
+#define UBUSIF_CFG_OOB_ERR_MASK_MASK        (0x1<< UBUSIF_CFG_OOB_ERR_MASK_SHIFT)
+	uint32_t SRC_QUEUE_CTRL[8];	/* 0x08 - 0x24 */
+	uint32_t REP_ARB_MODE;	/* 0x28 */
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT 0x0
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_MASK  (0x1<<UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT)
+	uint32_t SCRATCH;	/* 0x2c */
+	uint32_t DEBUG_R0;	/* 0x30 */
+	uint32_t unused[3];	/* 0x34-0x3f */
+} UBUSInterface;
+
+typedef struct RangeCtrl {
+	uint32_t CTRL;		/* 0x00 */
+	uint32_t UBUS0_PORT;	/* 0x04 */
+	uint32_t UBUS0_PORT_UPPER;	/* 0x08 */
+	uint32_t BASE;		/* 0x0c */
+	uint32_t BASE_UPPER;	/* 0x10 */
+} RangeCtrl;
+
+typedef struct SecureRangeCheckers {
+	uint32_t LOCK;		/* 0x00 */
+	uint32_t LOG_INFO[3];	/* 0x04 - 0x0c */
+	RangeCtrl RANGE_CTRL[8];	/* 0x10 - 0xac */
+	uint32_t unused[20];	/* 0xb0 - 0xff */
+} SecureRangeCheckers;
+
+typedef struct EDISEngine {
+	uint32_t REV_ID;	/* 0x00 */
+	uint32_t CTRL_TRIG;	/* 0x04 */
+	uint32_t CTRL_MODE;	/* 0x08 */
+	uint32_t CTRL_SIZE;	/* 0x0c */
+	uint32_t CTRL_ADDR_START;	/* 0x10 */
+	uint32_t CTRL_ADDR_START_EXT;	/* 0x14 */
+	uint32_t CTRL_ADDR_END;	/* 0x18 */
+	uint32_t CTRL_ADDR_END_EXT;	/* 0x1c */
+	uint32_t CTRL_WRITE_MASKS;	/* 0x20 */
+	uint32_t CTRL_INT_ENABLES;	/* 0x24 */
+	uint32_t unused0[6];	/* 0x28-0x3f */
+	uint32_t STAT_MAIN;	/* 0x40 */
+	uint32_t STAT_WORDS_WRITTEN;	/* 0x44 */
+	uint32_t STAT_WORDS_READ;	/* 0x48 */
+	uint32_t STAT_ERROR_COUNT;	/* 0x4c */
+	uint32_t STAT_ERROR_BITS;	/* 0x50 */
+	uint32_t STAT_ADDR_LAST;	/* 0x54 */
+	uint32_t STAT_ADDR_LAST_EXT;	/* 0x58 */
+	uint32_t STAT_CLOCK_CYCLES;	/* 0x5c */
+	uint32_t unused1[7];	/* 0x60-0x7b */
+	uint32_t STAT_DEBUG;	/* 0x7c */
+	uint32_t STAT_DATA_PORT[8];	/* 0x80-0x9c */
+	uint32_t GEN_LFSR_STATE[4];	/* 0xa0-0xac */
+	uint32_t GEN_CLOCK;	/* 0xb0 */
+	uint32_t GEN_PATTERN;	/* 0xb4 */
+	uint32_t unused2[2];	/* 0xb8-0xbf */
+	uint32_t BYTELANE_0_CTRL_LO;	/* 0xc0 */
+	uint32_t BYTELANE_0_CTRL_HI;	/* 0xc4 */
+	uint32_t BYTELANE_1_CTRL_LO;	/* 0xc8 */
+	uint32_t BYTELANE_1_CTRL_HI;	/* 0xcc */
+	uint32_t BYTELANE_2_CTRL_LO;	/* 0xd0 */
+	uint32_t BYTELANE_2_CTRL_HI;	/* 0xd4 */
+	uint32_t BYTELANE_3_CTRL_LO;	/* 0xd8 */
+	uint32_t BYTELANE_3_CTRL_HI;	/* 0xdc */
+	uint32_t BYTELANE_0_STAT_LO;	/* 0xe0 */
+	uint32_t BYTELANE_0_STAT_HI;	/* 0xe4 */
+	uint32_t BYTELANE_1_STAT_LO;	/* 0xe8 */
+	uint32_t BYTELANE_1_STAT_HI;	/* 0xec */
+	uint32_t BYTELANE_2_STAT_LO;	/* 0xf0 */
+	uint32_t BYTELANE_2_STAT_HI;	/* 0xf4 */
+	uint32_t BYTELANE_3_STAT_LO;	/* 0xf8 */
+	uint32_t BYTELANE_3_STAT_HI;	/* 0xfc */
+} EDISEngine;
+
+typedef struct DDRPhyControl {
+	uint32_t REVISION;	/* 0x00 */
+	uint32_t PLL_STATUS;	/* 0x04 */
+	uint32_t PLL_CONFIG;	/* 0x08 */
+	uint32_t PLL_CONTROL1;	/* 0x0c */
+	uint32_t PLL_CONTROL2;	/* 0x10 */
+	uint32_t PLL_CONTROL3;	/* 0x14 */
+	uint32_t PLL_DIVIDER;	/* 0x18 */
+	uint32_t PLL_PRE_DIVIDER;	/* 0x1c */
+	uint32_t PLL_SS_EN;	/* 0x20 */
+	uint32_t PLL_SS_CFG;	/* 0x24 */
+	uint32_t AUX_CONTROL;	/* 0x28 */
+	uint32_t IDLE_PAD_CONTROL;	/* 0x2c */
+	uint32_t IDLE_PAD_EN0;	/* 0x30 */
+	uint32_t IDLE_PAD_EN1;	/* 0x34 */
+	uint32_t DRIVE_PAD_CTL;	/* 0x38 */
+	uint32_t DRIVE_PAD_CTL_2T;	/* 0x3c */
+	uint32_t STATIC_PAD_CTL;	/* 0x40 */
+	uint32_t DRAM_CFG;	/* 0x44 */
+	uint32_t DRAM_TIMING1;	/* 0x48 */
+	uint32_t DRAM_TIMING2;	/* 0x4c */
+	uint32_t DRAM_TIMING3;	/* 0x50 */
+	uint32_t DRAM_TIMING4;	/* 0x54 */
+	uint32_t VDL_REGS[45];	/* 0x58-0x10b */
+	uint32_t UPDATE_VDL;	/* 0x10c */
+	uint32_t UPDATE_VDL_SNOOP1;	/* 0x110 */
+	uint32_t UPDATE_VDL_SNOOP2;	/* 0x114 */
+	uint32_t CMND_REG1;	/* 0x118 */
+	uint32_t CMND_AUX_REG1;	/* 0x11c */
+	uint32_t CMND_REG2;	/* 0x120 */
+	uint32_t CMND_AUX_REG2;	/* 0x124 */
+	uint32_t CMND_REG3;	/* 0x128 */
+	uint32_t CMND_AUX_REG3;	/* 0x12c */
+	uint32_t CMND_REG4;	/* 0x130 */
+	uint32_t CMND_AUX_REG4;	/* 0x134 */
+	uint32_t MODE_REG[9];	/* 0x138-15b */
+	uint32_t MODE_REG15;	/* 0x15c */
+	uint32_t MODE_REG63;	/* 0x160 */
+	uint32_t ALERT_CLEAR;	/* 0x164 */
+	uint32_t ALERT_STATUS;	/* 0x168 */
+	uint32_t ALERT_DF1;	/* 0x16c */
+	uint32_t CA_PLAYBACK_CTRL;	/* 0x170 */
+	uint32_t CA_PLAYBACK_STATUS0;	/* 0x174 */
+	uint32_t CA_PLAYBACK_STATUS1;	/* 0x178 */
+	uint32_t WRITE_LEVEL_CTRL;	/* 0x17c */
+	uint32_t WRITE_LEVEL_STATUS;	/* 0x180 */
+	uint32_t READ_EN_CTRL;	/* 0x184 */
+	uint32_t READ_EN_STATUS;	/* 0x188 */
+	uint32_t VIRT_VTT_CTRL;	/* 0x18c */
+	uint32_t VIRT_VTT_STATUS;	/* 0x190 */
+	uint32_t VIRT_VTT_CONNECTION;	/* 0x194 */
+	uint32_t VIRT_VTT_OVERRIDE;	/* 0x198 */
+	uint32_t VREF_DAC_CTRL;	/* 0x19c */
+#define DDRPHY_VREF_DAC_CTRL_PDN_SHIFT             12
+#define DDRPHY_VREF_DAC_CTRL_PDN_MASK              (0xf << DDRPHY_VREF_DAC_CTRL_PDN_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT            6
+#define DDRPHY_VREF_DAC_CTRL_DAC1_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT            0
+#define DDRPHY_VREF_DAC_CTRL_DAC0_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT)
+	uint32_t PHYBIST[12];	/* 0x1a0-0x1cf */
+	uint32_t STANDBY_CTRL;	/* 0x1d0 */
+	uint32_t DEBUG_FREEZE_EN;	/* 0x1d4 */
+	uint32_t DEBUG_MUX_CTRL;	/* 0x1d8 */
+	uint32_t DFI_CTRL;	/* 0x1dc */
+	uint32_t WRITE_ODT_CTRL;	/* 0x1e0 */
+	uint32_t ABI_PAR_CTRL;	/* 0x1e4 */
+	uint32_t ZQ_CAL;	/* 0x1e8 */
+	uint32_t unused5[7];	/* 0x1ec-0x207 */
+	uint32_t unused6[126];	/* 0x208-0x3ff */
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+	uint32_t VDL_CTRL_WR[11];	/* 0x00 - 0x2c */
+	uint32_t VDL_CTRL_RD[22];	/* 0x2c - 0x83 */
+	uint32_t VDL_CLK_CTRL;	/* 0x84 */
+	uint32_t VDL_LDE_CTRL;	/* 0x88 */
+	uint32_t RD_EN_DLY_CYC;	/* 0x8c */
+	uint32_t WR_CHAN_DLY_CYC;	/* 0x90 */
+	uint32_t RD_CTRL;	/* 0x94 */
+	uint32_t RD_FIFO_ADDR;	/* 0x98 */
+	uint32_t RD_FIFO_DATA;	/* 0x9c */
+	uint32_t RD_FIFO_DM_DBI;	/* 0xa0 */
+	uint32_t RD_FIFO_STATUS;	/* 0xa4 */
+	uint32_t RD_FIFO_CLR;	/* 0xa8 */
+	uint32_t IDLE_PAD_CTRL;	/* 0xac */
+	uint32_t DRIVE_PAD_CTRL;	/* 0xb0 */
+	uint32_t DQSP_DRIVE_PAD_CTRL;	/* 0xb4 */
+	uint32_t DQSN_DRIVE_PAD_CTRL;	/* 0xb8 */
+	uint32_t ALERT_DRIVE_PAD_CTRL;	/* 0xbc */
+	uint32_t RD_EN_DRIVE_PAD_CTRL;	/* 0xc0 */
+	uint32_t STATIC_PAD_CTRL;	/* 0xc4 */
+	uint32_t WR_PREAMBLE_MODE;	/* 0xc8 */
+	uint32_t ODT_CTRL;	/* 0xcc */
+	uint32_t CLOCK_ENABLE;	/* 0xd0 */
+	uint32_t CLOCK_IDLE;	/* 0xd4 */
+	uint32_t BL_SPARE_REG;	/* 0xd8 */
+	uint32_t unused[73];	/* 0xdc-0x1ff */
+} DDRPhyByteLaneControl;
+
+typedef struct MEMCControl {
+	uint32_t GLB_VERS;	/* 0x000 */
+	uint32_t GLB_GCFG;	/* 0x004 */
+#define MEMC_GLB_GCFG_DRAM_EN_SHIFT        31
+#define MEMC_GLB_GCFG_DRAM_EN_MASK         (0x1<<MEMC_GLB_GCFG_DRAM_EN_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ_SHIFT      30
+#define MEMC_GLB_GCFG_FORCE_SEQ_MASK       (0x1<<MEMC_GLB_GCFG_FORCE_SEQ_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT     29
+#define MEMC_GLB_GCFG_FORCE_SEQ2_MASK      (1<<MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT)
+#define MEMC_GLB_GCFG_RBF_REORDER_SHIFT    28
+#define MEMC_GLB_GCFG_RBF_REORDER_MASK     (1<<MEMC_GLB_GCFG_RBF_REORDER_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT   24
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_MASK    (0x3<<MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_2X           0x0
+#define MEMC_GLB_GCFG_PHY_DFI_4X           0x1
+#define MEMC_GLB_GCFG_PHY_DFI_8X           0x2
+#define MEMC_GLB_GCFG_DFI_EN_SHIFT         10
+#define MEMC_GLB_GCFG_DFI_EN_MASK          (0x1<<MEMC_GLB_GCFG_DFI_EN_SHIFT)
+#define MEMC_GLB_GCFG_MCLKSRC_SHIFT        9
+#define MEMC_GLB_GCFG_MCLKSRC_MASK         (0x1<<MEMC_GLB_GCFG_MCLKSRC_SHIFT)
+#define MEMC_GLB_GCFG_MEMINITDONE_SHIFT    8
+#define MEMC_GLB_GCFG_MEMINITDONE_MASK     (0x1<<MEMC_GLB_GCFG_MEMINITDONE_SHIFT)
+#define MEMC_GLB_GCFG_SIZE1_SHIFT          0
+#define MEMC_GLB_GCFG_SIZE1_MASK           (0xf<<MEMC_GLB_GCFG_SIZE1_SHIFT)
+	uint32_t GLB_MRQ_CFG;	/* 0x008 */
+	uint32_t unused0;	/* 0x00c */
+	uint32_t GLB_FSBL_STATE;	/* 0x010 */
+	uint32_t unused1[3];	/* 0x014 - 0x01f */
+
+	uint32_t SRAM_REMAP_CTRL;	/* 0x020 */
+	uint32_t SRAM_REMAP_CTRL_UPPER;	/* 0x024 */
+	uint32_t SRAM_REMAP_INIT;	/* 0x028 */
+	uint32_t SRAM_REMAP_LOG_INFO_0;	/* 0x02c */
+	uint32_t SRAM_REMAP_LOG_INFO_1;	/* 0x030 */
+	uint32_t SRAM_REMAP_LOG_INFO_2;	/* 0x034 */
+	uint32_t unused2[2];	/* 0x038-0x03f */
+
+	uint32_t RBF_REORDER_0_CFG[16];	/* 0x040 - 0x07f */
+
+	uint32_t INTR2_CPU_STATUS;	/* 0x080 */
+	uint32_t INTR2_CPU_SET;	/* 0x084 */
+	uint32_t INTR2_CPU_CLEAR;	/* 0x088 */
+	uint32_t INTR2_CPU_MASK_STATUS;	/* 0x08c */
+	uint32_t INTR2_CPU_MASK_SET;	/* 0x090 */
+	uint32_t INTR2_CPU_MASK_CLEAR;	/* 0x094 */
+	uint32_t unused3[26];	/* 0x098-0x0ff */
+
+	uint32_t CHN_CFG_CNFG;	/* 0x100 */
+#define MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT            16
+#define MEMC_CHN_CFG_CNFG_CS_MODE_MASK             (0x3 << MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT)
+	uint32_t CHN_CFG_CSST;	/* 0x104 */
+	uint32_t unused4[2];	/* 0x108-0x10f */
+	uint32_t CHN_CFG_ROW00_0;	/* 0x110 */
+	uint32_t CHN_CFG_ROW00_1;	/* 0x114 */
+	uint32_t CHN_CFG_ROW01_0;	/* 0x118 */
+	uint32_t CHN_CFG_ROW01_1;	/* 0x11c */
+	uint32_t CHN_CFG_ROW02_0;	/* 0x120 */
+	uint32_t CHN_CFG_COL00_0;	/* 0x124 */
+	uint32_t CHN_CFG_COL00_1;	/* 0x128 */
+	uint32_t CHN_CFG_COL01_0;	/* 0x12c */
+	uint32_t CHN_CFG_COL01_1;	/* 0x130 */
+	uint32_t CHN_CFG_BNK10;	/* 0x134 */
+	uint32_t CHN_CFG_BG0;	/* 0x138 */
+	uint32_t unused5;	/* 0x13c */
+	uint32_t CHN_CFG_DRAM_SZ_CHK;	/* 0x140 */
+	uint32_t CHN_CFG_DIAG_SEL;	/* 0x144 */
+	uint32_t unused6[46];	/* 0x148-0x1ff */
+
+	uint32_t CHN_TIM_DCMD;	/* 0x200 */
+	uint32_t CHN_TIM_DMODE_0;	/* 0x204 */
+	uint32_t CHN_TIM_DMODE_2;	/* 0x208 */
+	uint32_t CHN_TIM_CLKS;	/* 0x20c */
+#define MEMC_CHN_TIM_CLKS_REF_RATE_SHIFT          8
+#define MEMC_CHN_TIM_CLKS_REF_DISABLE_SHIFT       31
+	uint32_t CHN_TIM_ODT;	/* 0x210 */
+	uint32_t CHN_TIM_TIM1_0;	/* 0x214 */
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tWL [31:24] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_MASK                            0xff000000
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_SHIFT                           24
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_DEFAULT                         0x00000004
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRP [23:16] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_MASK                            0x00ff0000
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_SHIFT                           16
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_DEFAULT                         0x00000006
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tCL [15:08] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_MASK                            0x0000ff00
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_SHIFT                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_DEFAULT                         0x00000005
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRCD [07:00] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_MASK                           0x000000ff
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_ALIGN                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_BITS                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_SHIFT                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_DEFAULT                        0x00000006
+
+	uint32_t CHN_TIM_TIM1_1;	/* 0x218 */
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_L [31:24] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_S [23:16] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_L [15:08] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_MASK                         0x0000ff00
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_SHIFT                        8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_S [07:00] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_MASK                         0x000000ff
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_SHIFT                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_DEFAULT                      0x00000002
+
+	uint32_t CHN_TIM_TIM1_2;	/* 0x21c */
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tFAW [31:24] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_MASK                           0xff000000
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_SHIFT                          24
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_DEFAULT                        0x00000000
+/* MC_CHN_TIM :: TIM1_2 :: reserved0 [23:16] */
+#define MC_CHN_TIM_TIM1_2_reserved0_MASK                           0x00ff0000
+#define MC_CHN_TIM_TIM1_2_reserved0_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_reserved0_BITS                           8
+#define MC_CHN_TIM_TIM1_2_reserved0_SHIFT                          16
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRTP [15:08] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_MASK                           0x0000ff00
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_SHIFT                          8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_DEFAULT                        0x00000002
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRC [07:00] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_ALIGN                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_BITS                            8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_SHIFT                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_DEFAULT                         0x00000011
+
+	uint32_t CHN_TIM_TIM1_3;	/* 0x220 */
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_L [31:24] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_S [23:16] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: reserved_for_padding0 [15:12] */
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_MASK               0x0000f000
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_ALIGN              0
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_BITS               4
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_SHIFT              12
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_L [11:08] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_MASK                          0x00000f00
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_BITS                          4
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_SHIFT                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_DEFAULT                       0x00000004
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_S [07:00] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_MASK                          0x000000ff
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_BITS                          8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_SHIFT                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_DEFAULT                       0x00000004
+
+	uint32_t CHN_TIM_TIM2;	/* 0x224 */
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2R [31:30] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_MASK                             0xc0000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_BITS                             2
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_SHIFT                            30
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2W [29:27] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_MASK                             0x38000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_SHIFT                            27
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2R [26:24] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_MASK                             0x07000000
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_SHIFT                            24
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: reserved_for_padding0 [23:22] */
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_MASK                 0x00c00000
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_ALIGN                0
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_BITS                 2
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_SHIFT                22
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2W [21:18] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_MASK                             0x003c0000
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_BITS                             4
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_SHIFT                            18
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: reserved1 [17:16] */
+#define MC_CHN_TIM_TIM2_reserved1_MASK                             0x00030000
+#define MC_CHN_TIM_TIM2_reserved1_ALIGN                            0
+#define MC_CHN_TIM_TIM2_reserved1_BITS                             2
+#define MC_CHN_TIM_TIM2_reserved1_SHIFT                            16
+/* MC_CHN_TIM :: TIM2 :: TIM2_tAL [15:12] */
+#define MC_CHN_TIM_TIM2_TIM2_tAL_MASK                              0x0000f000
+#define MC_CHN_TIM_TIM2_TIM2_tAL_ALIGN                             0
+#define MC_CHN_TIM_TIM2_TIM2_tAL_BITS                              4
+#define MC_CHN_TIM_TIM2_TIM2_tAL_SHIFT                             12
+#define MC_CHN_TIM_TIM2_TIM2_tAL_DEFAULT                           0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tRFC [11:00] */
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_MASK                             0x00000fff
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_BITS                             12
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_SHIFT                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_DEFAULT                          0x00000014
+
+	uint32_t unused7[2];	/* 0x228 - 0x22f */
+	uint32_t CHN_TIM_PHY_ST;	/* 0x230 */
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP       0x1
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_HW_RESET       0x2
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_SW_RESET       0x4
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_READY          0x10
+	uint32_t CHN_TIM_DRAM_CFG;	/* 0x234 */
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT           12
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_MASK            (0x1<<MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT)
+#define DRAM_CFG_DRAMSLEEP                        (1<<11)
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT     10
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_MASK      (0x1<<MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT      0
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_MASK       (0xf<<MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT)
+#define MC_DRAM_CFG_DDR3                          0x1
+	uint32_t CHN_TIM_STAT;	/* 0x238 */
+	uint32_t CHN_TIM_PERF;	/* 0x23c */
+	uint32_t unused8[48];	/* 0x240-0x2ff */
+
+	uint32_t ARB_CFG;	/* 0x300 */
+#define MEMC_ARB_CFG_RR_MODE_SHIFT      0x0
+#define MEMC_ARB_CFG_RR_MODE_MASK       (0x1<<MEMC_ARB_CFG_RR_MODE_SHIFT)
+#define MEMC_ARB_CFG_BURST_MODE_SHIFT   0x1
+#define MEMC_ARB_CFG_BURST_MODE_MASK    (0x1<<MEMC_ARB_CFG_BURST_MODE_SHIFT)
+	uint32_t ARB_QUE_DIS[2];	/* 0x304 */
+	uint32_t ARB_SP_SEL[2];	/* 0x30c */
+	uint32_t ARB_RDWR_QUANTUM;	/* 0x314 */
+	uint32_t unused9[2];	/* 0x318 - 0x31f */
+	uint32_t ARB_SP_PRI[9];	/* 0x320 */
+	uint32_t unused10[3];	/* 0x344-0x34f */
+	uint32_t ARB_RR_QUANTUM[18];	/* 0x350 */
+	uint32_t unused11[26];	/* 0x398 - 0x3ff */
+
+	UBUSInterface UBUSIF0;	/* 0x400-0x43f */
+	UBUSInterface UBUSIF1;	/* 0x440-0x47f */
+	uint32_t unused12[32];	/* 0x480-0x4ff */
+
+	uint32_t MCPIF0_REV;	/* 0x500 */
+	uint32_t MCPIF0_CFG;	/* 0x504 */
+	uint32_t MCPIF0_REP_ARB_MODE;	/* 0x508 */
+	uint32_t unused13;	/* 0x50c */
+	uint32_t MCPIF0_WR_CDT;	/* 0x510 */
+	uint32_t MCPIF0_RD_CDT;	/* 0x514 */
+	uint32_t MCPIF0_SCRATCH;	/* 0x518 */
+	uint32_t MCPIF0_DEBUG;	/* 0x51c */
+	uint32_t MCPIF0_DEBUG_STS;	/* 0x520 */
+	uint32_t unused14[23];	/* 0x524 - 0x57f */
+
+	uint32_t EXACC_Status_LSB[4];	/* 0x580 - 0x58f */
+	uint32_t EXACC_Status_MSB[4];	/* 0x590 - 0x59f */
+	uint32_t EXACC_Status_Count[4];	/* 0x5a0 - 0x5af */
+	uint32_t EXACC_Status_Dis_LSB[4];	/* 0x5b0 - 0x5bf */
+	uint32_t EXACC_Status_Dis_MSB[4];	/* 0x5c0 - 0x5cf */
+	uint32_t EXACC_Status_Clear[4];	/* 0x5d0 - 0x5df */
+	uint32_t unused15[136];	/* 0x5e0 - 0x7ff */
+
+	EDISEngine EDIS_0;	/* 0x800 */
+	EDISEngine EDIS_1;	/* 0x900 */
+
+	uint32_t STATS_CTRL;	/* 0xa00 */
+	uint32_t STATS_TIMER_CFG;	/* 0xa04 */
+	uint32_t STATS_TIMER_COUNT;	/* 0xa08 */
+	uint32_t STATS_TOTAL_SLICE;	/* 0xa0c */
+	uint32_t STATS_TOTAL_PACKET;	/* 0xa10 */
+	uint32_t STATS_TOTAL_READ_SLICE;	/* 0xa14 */
+	uint32_t STATS_TOTAL_READ_PACKET;	/* 0xa18 */
+	uint32_t STATS_TOTAL_LATENCY;	/* 0xa1c */
+	uint32_t STATS_SLICE_REORDER;	/* 0xa20 */
+	uint32_t STATS_TOTAL_DDR_CMD;	/* 0xa24 */
+	uint32_t STATS_TOTAL_DDR_ACT;	/* 0xa28 */
+	uint32_t STATS_TOTAL_DDR_RDWR;	/* 0xa2c */
+	uint32_t STATS_TOTAL_DDR_WRRD;	/* 0xa30 */
+	uint32_t STATS_ARB_GRANT_MATCH0;	/* 0xa34 */
+	uint32_t STATS_ARB_GRANT_MATCH1;	/* 0xa38 */
+	uint32_t STATS_TOTAL_ARB_GRANT;	/* 0xa3c */
+	uint32_t STATS_FILTER_CFG_0;	/* 0xa40 */
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT  25
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_MASK   (0x1<<MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_EN     0x02000000
+#define MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT     16
+#define MEMC_STATS_FILTER_CFG_SRC_ID_MASK      (0x1FF<<MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_SHIFT 0
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_MASK  0x0000FFFF
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS0       0x00000001
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS1       0x00000002
+#define MEMC_STATS_FILTER_CFG_INTF_MCP         0x00000004
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS0       0x00000008
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS1       0x00000010
+	uint32_t STATS_PROG0_SLICE;	/* 0xa44 */
+	uint32_t STATS_PROG0_PACKET;	/* 0xa48 */
+	uint32_t STATS_PROG0_READ_SLICE;	/* 0xa4c */
+	uint32_t STATS_PROG0_READ_PACKET;	/* 0xa50 */
+	uint32_t STATS_PROG0_LATENCY;	/* 0xa54 */
+	uint32_t unused16[2];	/* 0xa58 - 0xa5c */
+	uint32_t STATS_FILTER_CFG_1;	/* 0xa60 */
+	uint32_t STATS_PROG1_SLICE;	/* 0xa64 */
+	uint32_t STATS_PROG1_PACKET;	/* 0xa68 */
+	uint32_t STATS_PROG1_READ_SLICE;	/* 0xa6c */
+	uint32_t STATS_PROG1_READ_PACKET;	/* 0xa70 */
+	uint32_t STATS_PROG1_LATENCY;	/* 0xa74 */
+	uint32_t unused17[2];	/* 0xa78 - 0xa7c */
+	uint32_t STATS_FILTER_CFG_2;	/* 0xa80 */
+	uint32_t STATS_PROG2_SLICE;	/* 0xa84 */
+	uint32_t STATS_PROG2_PACKET;	/* 0xa88 */
+	uint32_t STATS_PROG2_READ_SLICE;	/* 0xa8c */
+	uint32_t STATS_PROG2_READ_PACKET;	/* 0xa90 */
+	uint32_t STATS_PROG2_LATENCY;	/* 0xa94 */
+	uint32_t unused18[2];	/* 0xa98 - 0xa9c */
+	uint32_t STATS_FILTER_CFG_3;	/* 0xaa0 */
+	uint32_t STATS_PROG3_SLICE;	/* 0xaa4 */
+	uint32_t STATS_PROG3_PACKET;	/* 0xaa8 */
+	uint32_t STATS_PROG3_READ_SLICE;	/* 0xaac */
+	uint32_t STATS_PROG3_READ_PACKET;	/* 0xab0 */
+	uint32_t STATS_PROG3_LATENCY;	/* 0xab4 */
+	uint32_t unused19[18];	/* 0xab8 - 0xaff */
+
+	uint32_t CAP_CAPTURE_CFG;	/* 0xb00 */
+	uint32_t CAP_TRIGGER_ADDR;	/* 0xb04 */
+	uint32_t CAP_READ_CTRL;	/* 0xb08 */
+	uint32_t unused20;	/* 0xb0c */
+	uint32_t CAP_CAPTURE_MATCH0;	/* 0xb10 */
+	uint32_t CAP_CAPTURE_MATCH1;	/* 0xb14 */
+	uint32_t CAP_CAPTURE_MATCH2;	/* 0xb18 */
+	uint32_t unused21;	/* 0xb1c */
+	uint32_t CAP_CAPTURE_MASK0;	/* 0xb20 */
+	uint32_t CAP_CAPTURE_MASK1;	/* 0xb24 */
+	uint32_t CAP_CAPTURE_MASK2;	/* 0xb28 */
+	uint32_t unused22;	/* 0xb2c */
+	uint32_t CAP_TRIGGER_START_MATCH0;	/* 0xb30 */
+	uint32_t CAP_TRIGGER_START_MATCH1;	/* 0xb34 */
+	uint32_t CAP_TRIGGER_START_MATCH2;	/* 0xb38 */
+	uint32_t unused23;	/* 0xb3c */
+	uint32_t CAP_TRIGGER_START_MASK0;	/* 0xb40 */
+	uint32_t CAP_TRIGGER_START_MASK1;	/* 0xb44 */
+	uint32_t CAP_TRIGGER_START_MASK2;	/* 0xb48 */
+	uint32_t unused24;	/* 0xb4c */
+	uint32_t CAP_READ_DATA[8];	/* 0xb50-0xb6f */
+	uint32_t CAP_TRIGGER_STOP_MATCH0;	/* 0xb70 */
+	uint32_t CAP_TRIGGER_STOP_MATCH1;	/* 0xb74 */
+	uint32_t CAP_TRIGGER_STOP_MATCH2;	/* 0xb78 */
+	uint32_t unused25_0;	/* 0xb7c */
+	uint32_t CAP_TRIGGER_STOP_MASK0;	/* 0xb80 */
+	uint32_t CAP_TRIGGER_STOP_MASK1;	/* 0xb84 */
+	uint32_t CAP_TRIGGER_STOP_MASK2;	/* 0xb88 */
+	uint32_t unused25_1[157];	/* 0xb8c-0xdff */
+
+	uint32_t SEC_INTR2_CPU_STATUS;	/* 0xe00 */
+	uint32_t SEC_INTR2_CPU_SET;	/* 0xe04 */
+	uint32_t SEC_INTR2_CPU_CLEAR;	/* 0xe08 */
+	uint32_t SEC_INTR2_CPU_MASK_STATUS;	/* 0xe0c */
+	uint32_t SEC_INTR2_CPU_MASK_SET;	/* 0xe10 */
+	uint32_t SEC_INTR2_CPU_MASK_CLEAR;	/* 0xe14 */
+	uint32_t unused26[634];	/* 0xe18-0x17ff */
+
+	SecureRangeCheckers SEC_RANGE_CHK;	/* 0x1800-0x18ff */
+	uint32_t unused27[448];	/* 0x1900-0x1fff */
+
+	DDRPhyControl PhyControl;	/* 0x2000 */
+	DDRPhyByteLaneControl PhyByteLane0Control;	/* 0x2400 */
+	DDRPhyByteLaneControl PhyByteLane1Control;	/* 0x2600 */
+	DDRPhyByteLaneControl PhyByteLane2Control;	/* 0x2400 */
+	DDRPhyByteLaneControl PhyByteLane3Control;	/* 0x2600 */
+} MEMCControl;
+
+#define MEMC ((volatile MEMCControl * const) MEMC_BASE)
+
+#endif /* _4908_DDR_H */
diff --git a/arch/arm/include/asm/arch-bcm4908/ethsw.h b/arch/arm/include/asm/arch-bcm4908/ethsw.h
new file mode 100644
index 0000000000..a0a6c47ebb
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/ethsw.h
@@ -0,0 +1,201 @@
+#include <config.h>
+#include <common.h>
+#include <stdlib.h>
+
+#define uint32 uint32_t
+/*
+** Eth Switch Registers
+*/
+typedef struct {
+    unsigned int led_f;
+    unsigned int reserved;
+} LED_F;
+
+typedef struct EthernetSwitchCore
+{
+    unsigned int port_traffic_ctrl[9];            /* 0x00 - 0x08 */
+    unsigned int reserved1[2];                    /* 0x09 - 0x0a */
+    unsigned int switch_mode;                     /* 0x0b */
+#define ETHSW_SM_RETRY_LIMIT_DIS                  0x04
+#define ETHSW_SM_FORWARDING_EN                    0x02
+#define ETHSW_SM_MANAGED_MODE                     0x01
+    unsigned int pause_quanta;                    /* 0x0c */
+    unsigned int reserved33; 
+    unsigned int imp_port_state;                  /*0x0e */
+#define ETHSW_IPS_USE_MII_HW_STS                  0x00
+#define ETHSW_IPS_USE_REG_CONTENTS                0x80
+#define ETHSW_IPS_GMII_SPEED_UP_NORMAL            0x00
+#define ETHSW_IPS_GMII_SPEED_UP_2G                0x40
+#define ETHSW_IPS_TXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_TXFLOW_PAUSE_CAPABLE            0x20
+#define ETHSW_IPS_RXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_RXFLOW_PAUSE_CAPABLE            0x10
+#define ETHSW_IPS_SW_PORT_SPEED_1000M_2000M       0x08
+#define ETHSW_IPS_DUPLEX_MODE                     0x02
+#define ETHSW_IPS_LINK_FAIL                       0x00
+#define ETHSW_IPS_LINK_PASS                       0x01
+    unsigned int led_refresh;                     /* 0x0f */
+    LED_F        led_function[2];                 /* 0x10 */
+    unsigned int led_function_map;                /* 0x14 */
+    unsigned int reserved14; 
+    unsigned int led_enable_map;                  /* 0x16 */
+    unsigned int reserved15; 
+    unsigned int led_mode_map0;                   /* 0x18 */
+    unsigned int reserved16; 
+    unsigned int led_function_map1;               /* 0x1a */
+    unsigned int reserved17; 
+    unsigned int reserved2[5];                    /* 0x1c - 0x20 */
+    unsigned int port_forward_ctrl;               /* 0x21 */
+    unsigned int switch_ctrl;                     /* 0x22 */
+#define ETHSW_SC_MII_DUMP_FORWARDING_EN           0x40
+#define ETHSW_SC_MII2_VOL_SEL                     0x02
+    unsigned int reserved3;                       /* 0x23 */
+    unsigned int protected_port_selection;        /* 0x24 */
+    unsigned int reserved18; 
+    unsigned int wan_port_select;                 /* 0x26 */
+    unsigned int reserved19; 
+    unsigned int pause_capability;                /* 0x28 */
+    unsigned int reserved20[3]; 
+    unsigned int reserved4[3];                    /* 0x2c - 0x2e */
+    unsigned int reserved_multicast_control;      /* 0x2f */
+    unsigned int reserved5;                       /* 0x30 */
+    unsigned int txq_flush_mode_control;          /* 0x31 */
+    unsigned int ulf_forward_map;                 /* 0x32 */
+    unsigned int reserved21; 
+    unsigned int mlf_forward_map;                 /* 0x34 */
+    unsigned int reserved22; 
+    unsigned int mlf_impc_forward_map;            /* 0x36 */
+    unsigned int reserved23; 
+    unsigned int pause_pass_through_for_rx;       /* 0x38 */
+    unsigned int reserved24; 
+    unsigned int pause_pass_through_for_tx;       /* 0x3a */
+    unsigned int reserved25; 
+    unsigned int disable_learning;                /* 0x3c */
+    unsigned int reserved26; 
+    unsigned int reserved6[26];                   /* 0x3e - 0x57 */
+    unsigned int port_state_override[8];          /* 0x58 - 0x5f */
+#define ETHSW_PS_SW_OVERRIDE                      0x40
+#define ETHSW_PS_SW_TX_FLOW_CTRL_EN               0x20
+#define ETHSW_PS_SW_RX_FLOW_CTRL_EN               0x10
+#define ETHSW_PS_SW_PORT_SPEED_1000M              0x08
+#define ETHSW_PS_SW_PORT_SPEED_100M               0x04
+#define ETHSW_PS_SW_PORT_SPEED_10M                0x00
+#define ETHSW_PS_DUPLEX_MODE                      0x02
+#define ETHSW_PS_LINK_DOWN                        0x00
+#define ETHSW_PS_LINK_UP                          0x01
+    unsigned int reserved7[4];                    /* 0x60 - 0x63 */
+    unsigned int imp_rgmii_ctrl_p4;               /* 0x64 */
+    unsigned int imp_rgmii_ctrl_p5;               /* 0x65 */
+    unsigned int reserved8[6];                    /* 0x66 - 0x6b */
+    unsigned int rgmii_timing_delay_p4;           /* 0x6c */
+    unsigned int gmii_timing_delay_p5;            /* 0x6d */
+    unsigned int reserved9[11];                   /* 0x6e - 0x78 */
+    unsigned int software_reset;                  /* 0x79 */
+    unsigned int reserved13[6];                   /* 0x7a - 0x7f */
+    unsigned int pause_frame_detection;           /* 0x80 */
+    unsigned int reserved10[7];                   /* 0x81 - 0x87 */
+    unsigned int fast_aging_ctrl;                 /* 0x88 */
+    unsigned int fast_aging_port;                 /* 0x89 */
+    unsigned int fast_aging_vid;                  /* 0x8a */
+    unsigned int anonymous1[376];                 /* 0x8b */
+    unsigned int brcm_hdr_ctrl;                   /* 0x203 */
+    unsigned int anonymous2[0x2efc];              /* 0x204 */
+    unsigned int port_vlan_ctrl[9*2];               /* 0x3100 */
+} EthernetSwitchCore;
+
+#define PBMAP_MIPS 0x100
+
+typedef struct {
+    uint32 led_ctrl;
+    uint32 led_encoding_sel;
+    uint32 led_encoding;
+}LED_CFG;
+
+typedef struct EthernetSwitchReg
+{
+    uint32 switch_ctrl;                      /* 0x0000 */
+    uint32 switch_status;                    /* 0x0004 */
+    uint32 dir_data_write_reg;               /* 0x0008 */
+    uint32 dir_data_read_reg;                /* 0x000c */
+    uint32 switch_rev;                       /* 0x0010 */
+    uint32 phy_rev;                          /* 0x0014 */
+    uint32 phy_test_ctrl;                    /* 0x0018 */
+    uint32 qphy_ctrl;                        /* 0x001c */
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT     12
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_MASK      (0x1f<<ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT)
+#define ETHSW_QPHY_CTRL_RESET_SHIFT          8
+#define ETHSW_QPHY_CTRL_RESET_MASK           (0x1<<ETHSW_QPHY_CTRL_RESET_SHIFT )
+#define ETHSW_QPHY_CTRL_CK25_DIS_SHIFT       7
+#define ETHSW_QPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_QPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_MASK    (0xf<<ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      6
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+
+
+    uint32 qphy_status;                      /* 0x0020 */
+    uint32 sphy_ctrl;                        /* 0x0024 */
+#define ETHSW_SPHY_CTRL_PHYAD_SHIFT          8
+#define ETHSW_SPHY_CTRL_PHYAD_MASK           (0x1f<<ETHSW_SPHY_CTRL_PHYAD_SHIFT)
+#define ETHSW_SPHY_CTRL_RESET_SHIFT          5
+#define ETHSW_SPHY_CTRL_RESET_MASK           (0x1<<ETHSW_SPHY_CTRL_RESET_SHIFT )
+#define ETHSW_SPHY_CTRL_CK25_DIS_SHIFT       4
+#define ETHSW_SPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_SPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_MASK    (0x1<<ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      3
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+    uint32 sphy_status;                      /* 0x0028 */
+    uint32 switch_phy_intr_ctrl;             /* 0x002c */
+    uint32 moca_bp_qsel_ctrl;                /* 0x0030 */
+    uint32 reserved2[3];                     /* 0x0034 - 0x003f */
+    LED_CFG led_ctrl[8];                     /* 0x0040 - 0x009f */
+    LED_CFG led_wan_ctrl;                    /* 0x00a0 - 0x00ab */
+#define ETHSW_LED_CTRL_SPD0_ON               0x0
+#define ETHSW_LED_CTRL_SPD0_OFF              0x1
+#define ETHSW_LED_CTRL_SPD1_ON               0x0
+#define ETHSW_LED_CTRL_SPD1_OFF              0x2
+#define ETHSW_LED_CTRL_1000M_SHIFT           9
+#define ETHSW_LED_CTRL_100M_SHIFT            6
+#define ETHSW_LED_CTRL_10M_SHIFT             3
+#define ETHSW_LED_CTRL_NOLINK_SHIFT          0
+#define ETHSW_LED_CTRL_ALL_SPEED_MASK        0x3ffff
+#define ETHSW_LED_CTRL_SPEED_MASK            0x7
+    uint32 led_blink_rate_ctrl;              /* 0x00ac */
+    uint32 led_serial_ctrl;                  /* 0x00b0 */
+    uint32 led_refresh_period_ctrl;          /* 0x00b4 */
+    uint32 aggregate_led_ctrl;               /* 0x00b8 */
+#define ETHSW_AGGREGATE_LED_CTRL_PORT_EN_MASK            0xffff
+#define ETHSW_AGGREGATE_LED_CTRL_ACT_SEL_MASK            0x10000
+#define ETHSW_AGGREGATE_LED_CTRL_ACT_POL_SEL_MASK        0x20000
+#define ETHSW_AGGREGATE_LED_CTRL_LNK_POL_SEL_MASK        0x40000
+    uint32 aggregate_blink_rate_ctrl;        /* 0x00bc */
+    uint32 reserved3[2];                     /* 0x00c0 - 0x00c7 */
+    uint32 crossbar_switch_ctrl;             /* 0x00c8 */
+    uint32 reserved4[32];                    /* 0x00cc - 0x014b */
+    uint32 rgmii_11_ctrl;                    /* 0x014c */
+#define ETHSW_RC_MII_MODE_MASK               0x1c
+#define ETHSW_RC_EXT_RVMII                   0x10
+#define ETHSW_RC_EXT_GPHY                    0x0c
+#define ETHSW_RC_EXT_EPHY                    0x08
+#define ETHSW_RC_INT_GPHY                    0x04
+#define ETHSW_RC_INT_EPHY                    0x00
+#define ETHSW_RC_ID_MODE_DIS                 0x02
+#define ETHSW_RC_RGMII_EN                    0x01
+    uint32 rgmii_11_ib_status;               /* 0x0150 */
+    uint32 rgmii_11_rx_clk_delay_ctrl;       /* 0x0154 */
+#define ETHSW_RXCLK_IDDQ                    (1<<4)
+#define ETHSW_RXCLK_BYPASS                  (1<<5)
+    uint32 anonymous1[154];                  /* 0x0158 - 0x03bf*/
+    uint32 single_serdes_rev;                /* 0x03c0 */
+    uint32 single_serdes_ctrl;               /* 0x03c4 */
+    uint32 single_serdes_stat;               /* 0x03c8 */
+    uint32 single_serdes_apd_ctrl;           /* 0x03cc */
+    uint32 single_serdes_apd_fsm_ctrl;       /* 0x03d0 */
+} EthernetSwitchReg;
+
+
diff --git a/arch/arm/include/asm/arch-bcm4908/gmac.h b/arch/arm/include/asm/arch-bcm4908/gmac.h
new file mode 100644
index 0000000000..596a955a57
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/gmac.h
@@ -0,0 +1,424 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Corporation.
+ */
+
+#ifndef _BCM_SF2_ETH_GMAC_H_
+#define _BCM_SF2_ETH_GMAC_H_
+
+/*
+ * GMAC(UNIMAC) module 
+ */
+
+typedef union MibCtrlReg_s {
+    uint32_t word;
+    struct {
+        uint32_t    clrMib:  1;
+        uint32_t    unused: 31;
+    };
+} MibCtrlReg_t;
+
+typedef union MibMaxPktSizeReg_s {
+    uint32_t word;
+    struct {
+        uint32_t    max_pkt_size: 14;
+        uint32_t    unused      : 18;
+    };
+} MibMaxPktSizeReg_t;
+
+typedef union RxBpThreshReg_s {
+    uint32_t word;
+    struct {
+        uint32_t    rx_thresh : 11;
+        uint32_t    unused    : 21;
+    };
+} RxBpThreshReg_t;
+
+typedef union RxFlowCtrlReg_s {
+    uint32_t word;
+    struct {
+        uint32_t    fc_en     :  1;
+        uint32_t    pause_en  :  1;
+        uint32_t    unused    : 20;
+    };
+} RxFlowCtrlReg_t;
+
+typedef union BpForceReg_s {
+    uint32_t word;
+    struct {
+        uint32_t    force :  1;
+        uint32_t    unused: 31;
+    };
+} BpForceReg_t;
+
+typedef union IrqEnableReg_s {
+    uint32_t word;
+    struct {
+        uint32_t    ovfl  :  1;
+        uint32_t    unused: 31;
+    };
+} IrqEnableReg_t;
+
+typedef union IrqStatusReg_s {
+    uint32_t word;
+    struct {
+        uint32_t    ovfl  :  1;
+        uint32_t    unused: 31;
+    };
+} IrqStatusReg_t;
+
+typedef union GmacStatusReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t  eth_speed   : 2;
+#define GMAC_STATUS_SPEED_10        0
+#define GMAC_STATUS_SPEED_100       1
+#define GMAC_STATUS_SPEED_1000      2
+        uint32_t  hd          : 1;
+        uint32_t  auto_cfg_en : 1;
+        uint32_t  link_up     : 1;
+        uint32_t  unused      :27;
+    };
+} GmacStatusReg_t;
+
+typedef union FlushReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t  rxfifo_flush : 1;
+        uint32_t  txfifo_flush : 1;
+        uint32_t  unused       :30;
+    };
+} FlushReg_t;
+
+typedef union DmaRxStatusSelReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t  rx_err    : 1;
+        uint32_t  crc_err   : 1;
+        uint32_t  mcast_det : 1;
+        uint32_t  bcast_det : 1;
+        uint32_t  ctrl_frm  : 1;
+        uint32_t  vlan      : 1;
+        uint32_t  ucast_det : 1;
+        uint32_t  frm_trunc : 1;
+        uint32_t  runt_det  : 1;
+        uint32_t  unused    :23;
+    };
+} DmaRxStatusSelReg_t;
+
+typedef union DmaRxOkToSendCountReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t  ok_to_send_count : 4;
+        uint32_t  unused           :28;
+    };
+} DmaRxOkToSendCountReg_t;
+
+typedef struct GmacIntf {
+/*0x00*/    uint32_t                Control; 
+/*0x04*/    MibCtrlReg_t            MibCtrl;
+/*0x08*/    uint32_t                RxErrMask; 
+/*0x0C*/    MibMaxPktSizeReg_t      MibMaxPktSize;
+/*0x10*/    uint32_t                reserved1[3];
+/*0x1C*/    uint32_t                DiagOut; 
+/*0x20*/    uint32_t                EnableDropPkt;
+/*0x24*/    IrqEnableReg_t          IrqEnable;
+/*0x28*/    GmacStatusReg_t         GmacStatus;
+/*0x2C*/    IrqStatusReg_t          IrqStatus; 
+/*0x30*/    uint32_t                OverFlowCounter; 
+/*0x34*/    FlushReg_t              Flush;
+/*0x38*/    uint32_t                RsvSelect;  
+/*0x3C*/    BpForceReg_t            BpForce;
+/*0x40*/    DmaRxOkToSendCountReg_t DmaRxOkToSendCount;
+/*0x44*/    uint32_t                TxCrcCtrl;  
+} GmacIntf;
+
+typedef union CmdReg_s {
+    uint32_t word;
+    struct {
+        uint32_t tx_ena        : 1;   /* bit  0 */
+        uint32_t rx_ena        : 1;   /* bit  1 */
+        uint32_t eth_speed     : 2;   /* bit 3:2 */
+#define CMD_ETH_SPEED_10            0
+#define CMD_ETH_SPEED_100           1
+#define CMD_ETH_SPEED_1000          2
+#define CMD_ETH_SPEED_2500          3
+        uint32_t promis_en     : 1;   /* bit  4 */
+        uint32_t pad_rem_en    : 1;   /* bit  5 */
+        uint32_t crc_fwd       : 1;   /* bit  6 */
+        uint32_t pause_fwd     : 1;   /* bit  7 */
+        uint32_t rx_pause_ign  : 1;   /* bit  8 */
+        uint32_t tx_addr_ins   : 1;   /* bit  9 */
+        uint32_t hd_ena        : 1;   /* bit 10 */
+        uint32_t unused0       : 2;   /* bit 12:11 */
+        uint32_t sw_reset      : 1;   /* bit 13 */
+        uint32_t unused1       : 1;   /* bit 14 */
+        uint32_t lcl_loop_ena  : 1;   /* bit 15 */
+        uint32_t unused2       : 6;   /* bit 21:16 */
+        uint32_t ena_ext_cfg   : 1;   /* bit 22 */
+        uint32_t ctrl_frm_ena  : 1;   /* bit 23 */
+        uint32_t len_chk_dis   : 1;   /* bit 24 */
+        uint32_t rmt_loop_ena  : 1;   /* bit 25 */
+        uint32_t rx_err_disc   : 1;   /* bit 26 */
+        uint32_t prbl_ena      : 1;   /* bit 27 */
+        uint32_t tx_pause_ign  : 1;   /* bit 28 */
+        uint32_t txrx_en_cfg   : 1;   /* bit 29 */
+        uint32_t runt_filt_dis : 1;   /* bit 30 */
+        uint32_t unused3       : 1;   /* bit 31 */
+    };
+} CmdReg_t;
+
+typedef union FrmLenReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t frm_len : 14;   /* bit 13:0 */
+        uint32_t unused  : 18;   
+    };
+} FrmLenReg_t;
+
+typedef union PauseQuantaReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t pause_quanta : 16;   /* bit 15:0 */
+        uint32_t unused       : 16;   
+    };
+} PauseQuantaReg_t;
+
+typedef union ModeReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t mac_speed    : 2;   /* bit 1:0 */
+        uint32_t mac_dplx     : 1;   /* bit  2 */
+        uint32_t mac_rx_pause : 1;   /* bit  3 */
+        uint32_t mac_tx_pause : 1;   /* bit  4 */
+        uint32_t mac_link_up  : 1;   /* bit  5 */
+        uint32_t unused       : 26;   
+    };
+} ModeReg_t;
+
+typedef union FrmTagReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t tag     : 16;    /* bit 15:0 */
+        uint32_t tpid_en :  1;    /* bit 16 */
+        uint32_t unused  : 15;   
+    };
+} FrmTagReg_t;
+
+typedef union TxIpgLenReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t tx_ipg_len     : 7;  /* bit 6:0 */
+        uint32_t unused2        : 1;  /* bit 7 */
+        uint32_t tx_min_pkt_len : 7;  /* bit 14:8 */
+        uint32_t unused1        : 17; /* bit 31:15 */
+    };
+
+} TxIpgLenReg_t;
+
+typedef union RxIpgInvReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t rx_ipg_inv : 1;  /* bit 0 */
+        uint32_t unused     :31;   
+    };
+} RxIpgInvReg_t;
+
+typedef union RepPauseCtrlReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t pause_timer :17; /* bit 16:0 */
+        uint32_t pause_en    : 1; /* bit 17 */
+        uint32_t unused      :14;   
+    };
+} RepPauseCtrlReg_t;
+
+typedef union TxFifoFlushReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t tx_flush : 1; /* bit 0 */
+        uint32_t unused   :31;   
+    };
+} TxFifoFlushReg_t;
+
+typedef struct RxFifoStatusReg_s {
+    uint32_t  word;
+    struct {
+        uint32_t rxfifo_underrun : 1; /* bit 0 */
+        uint32_t rxfifo_overrun  : 1; /* bit 1 */
+        uint32_t unused          :30;   
+    };
+} RxFifoStatusReg_t;
+
+typedef union TxFifoStatusReg_s {
+    uint32_t word;
+    struct {
+        uint32_t txfifo_underrun : 1; /* bit 0 */
+        uint32_t txfifo_overrun  : 1; /* bit 1 */
+        uint32_t unused          :30;   
+    };
+} TxFifoStatusReg_t;
+
+
+typedef struct GmacMac {
+    uint32_t UmacDummy;             /* 0x00 */
+    uint32_t HdBkpCntl;             /* 0x04 */
+    CmdReg_t Cmd;                   /* 0x08 */
+    uint32_t Mac0;                  /* 0x0c */
+    uint32_t Mac1;                  /* 0x10 */
+    FrmLenReg_t FrmLen;             /* 0x14 */
+    PauseQuantaReg_t PauseQuanta;   /* 0x18 */
+    uint32_t unused1[9];            /* 0x1c - 0x3c */
+    uint32_t SfdOffset;             /* 0x40 */
+    ModeReg_t Mode;                 /* 0x44 */
+    FrmTagReg_t FrmTag0;            /* 0x48 */
+    FrmTagReg_t FrmTag1;            /* 0x4c */
+    uint32_t unused2[3];            /* 0x50 - 0x58 */
+    TxIpgLenReg_t TxIpgLen;         /* 0x5c */
+    uint32_t unused3[6];            /* 0x60 - 0x74 */
+    RxIpgInvReg_t RxIpgInv;         /* 0x78 */
+    uint32_t unused4[165];          /* 0x7c - 0x30c */
+    uint32_t MacsecProgTxCrc;       /* 0x310 */
+    uint32_t MacsecCtrl;            /* 0x314 */
+    uint32_t unused5[6];            /* 0x318 - 0x32c */
+    RepPauseCtrlReg_t PauseCtrl;    /* 0x330 */
+    TxFifoFlushReg_t TxFifoFlush;   /* 0x334 */
+    RxFifoStatusReg_t RxFifoStatus; /* 0x338 */
+    TxFifoStatusReg_t TxFifoStatus; /* 0x33c */
+} GmacMac;
+
+
+#define GMAC_IUDMA_MAX_CHANNELS          2
+/*
+** DMA Channel Configuration (1 .. 32)
+*/
+typedef struct DmaChannelCfg {
+  uint32_t        cfg;                    /* (00) assorted configuration */
+#define         DMA_ENABLE      0x00000001  /* set to enable channel */
+#define         DMA_PKT_HALT    0x00000002  /* idle after an EOP flag is detected */
+#define         DMA_BURST_HALT  0x00000004  /* idle after finish current memory burst */
+  uint32_t        intStat;                /* (04) interrupts control and status */
+  uint32_t        intMask;                /* (08) interrupts mask */
+#define         DMA_BUFF_DONE   0x00000001  /* buffer done */
+#define         DMA_DONE        0x00000002  /* packet xfer complete */
+#define         DMA_NO_DESC     0x00000004  /* no valid descriptors */
+#define         DMA_RX_ERROR    0x00000008  /* rxdma detect client protocol error */
+  uint32_t        maxBurst;               /* (0C) max burst length permitted */
+#define         DMA_DESCSIZE_SEL 0x00040000  /* DMA Descriptor Size Selection */
+} DmaChannelCfg;
+
+/*
+** DMA State RAM (1 .. 16)
+*/
+typedef struct DmaStateRam {
+  uint32_t        baseDescPtr;            /* (00) descriptor ring start address */
+#define			RING_OFFSET_MASK 0x00001FFF
+  uint32_t        state_data;             /* (04) state/bytes done/ring offset */
+  uint32_t        desc_len_status;        /* (08) buffer descriptor status and len */
+  uint32_t        desc_base_bufptr;       /* (0C) buffer descrpitor current processing */
+} DmaStateRam;
+
+
+/*
+** DMA Registers
+*/
+typedef struct DmaRegs {
+    uint32_t controller_cfg;              /* (00) controller configuration */
+#define DMA_MASTER_EN           0x00000001
+#define DMA_FLOWC_CH1_EN        0x00000002
+#define DMA_FLOWC_CH3_EN        0x00000004
+
+    // Flow control Ch1
+    uint32_t flowctl_ch1_thresh_lo;           /* 004 */
+    uint32_t flowctl_ch1_thresh_hi;           /* 008 */
+    uint32_t flowctl_ch1_alloc;               /* 00c */
+#define DMA_BUF_ALLOC_FORCE     0x80000000
+
+    // Flow control Ch3
+    uint32_t flowctl_ch3_thresh_lo;           /* 010 */
+    uint32_t flowctl_ch3_thresh_hi;           /* 014 */
+    uint32_t flowctl_ch3_alloc;               /* 018 */
+
+    // Flow control Ch5
+    uint32_t flowctl_ch5_thresh_lo;           /* 01C */
+    uint32_t flowctl_ch5_thresh_hi;           /* 020 */
+    uint32_t flowctl_ch5_alloc;               /* 024 */
+
+    // Flow control Ch7
+    uint32_t flowctl_ch7_thresh_lo;           /* 028 */
+    uint32_t flowctl_ch7_thresh_hi;           /* 02C */
+    uint32_t flowctl_ch7_alloc;               /* 030 */
+
+    uint32_t ctrl_channel_reset;              /* 034 */
+    uint32_t ctrl_channel_debug;              /* 038 */
+    uint32_t reserved1;                       /* 03C */
+    uint32_t ctrl_global_interrupt_status;    /* 040 */
+    uint32_t ctrl_global_interrupt_mask;      /* 044 */
+
+    // Unused words
+    uint8_t reserved2[0x200-0x48];
+
+    // Per channel registers/state ram
+    DmaChannelCfg chcfg[GMAC_IUDMA_MAX_CHANNELS];/* (0x200-0x21f) Channel configuration */
+    // Unused words
+    uint8_t reserved3[0x200-0x20];
+    union {
+        DmaStateRam     s[GMAC_IUDMA_MAX_CHANNELS];
+        uint32_t          u32[4 * GMAC_IUDMA_MAX_CHANNELS];
+    } stram;                                /* (400-5FF) state ram */
+} DmaRegs;
+
+/*
+** DMA Buffer
+*/
+typedef struct DmaDesc {
+  union {
+    struct {
+        uint16_t        status;                 /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+        uint16_t        length;                 /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM    0x8000
+#define          DMA_DESC_MULTICAST 0x4000
+#define          DMA_DESC_BUFLENGTH 0x0fff
+    };
+    uint32_t      word0;
+  };
+  uint32_t        address;                /* address of data */
+} DmaDesc;
+
+/*
+** 16 Byte DMA Buffer
+*/
+typedef struct {
+  union {
+    struct {
+        uint16_t        status;                 /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+        uint16_t        length;                 /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM    0x8000
+#define          DMA_DESC_MULTICAST 0x4000
+#define          DMA_DESC_BUFLENGTH 0x0fff
+    };
+    uint32_t      word0;
+  };
+  uint32_t        address;                 /* address of data */
+  uint32_t        control;
+#define         GEM_ID_MASK             0x001F
+  uint32_t        reserved;
+} DmaDesc16;
+
+#endif /* _BCM_SF2_ETH_GMAC_H_ */
diff --git a/arch/arm/include/asm/arch-bcm4908/misc.h b/arch/arm/include/asm/arch-bcm4908/misc.h
new file mode 100644
index 0000000000..a21d3cf5b5
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/misc.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4908_MISC_H
+#define _4908_MISC_H
+
+#define MISC_BASE             0xFF802600
+
+/*
+ * Misc Register Set Definitions.
+ */
+typedef struct Misc {
+   uint32_t miscStrapBus; /* 0x00 */
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           0
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_B53_BOOT_N               (0x1 << 6)
+#define MISC_STRAP_BUS_BOOTROM_BOOT_N           (0x1 << 7)
+#define MISC_STRAP_BUS_LS_SPI_SLAVE_DISABLE     (0x1 << 8)
+#define MISC_STRAP_BUS_PMC_BOOT_AVS             (0x1 << 9)
+#define MISC_STRAP_BUS_PMC_BOOT_FLASH           (0x1 << 10)
+#define MISC_STRAP_BUS_PMC_ROM_BOOT             (0x1 << 11)
+#define MISC_STRAP_BUS_PCIE0_RC_MODE            (0x1 << 12)
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT    13
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_MASK     (0x1 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT)
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_20US     (0x1 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT)
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_10MS     (0x0 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT)
+#define MISC_STRAP_BUS_XTAL_BYPASS_N            (0x1 << 14)
+#define MISC_STRAP_BUS_UBUS_CLOCK_SHIFT         15
+#define MISC_STRAP_BUS_UBUS_CLOCK_MASK          (0x1 << MISC_STRAP_BUS_UBUS_CLOCK_SHIFT)
+#define MISC_STRAP_BUS_UBUS_CLOCK_400MHZ        (0x1 << MISC_STRAP_BUS_UBUS_CLOCK_SHIFT)
+#define MISC_STRAP_BUS_UBUS_CLOCK_50MHZ         (0x0 << MISC_STRAP_BUS_UBUS_CLOCK_SHIFT)
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ            (0x1 << 16)
+#define MISC_STRAP_BUS_SW_RESERVE_MASK          (0x3 << 17)
+   uint32_t miscStrapOverride;     /* 0x04 */
+   uint32_t miscSoftwareDebug[6];  /* 0x08 */
+   uint32_t miscWDResetCtrl;       /* 0x20 */
+   uint32_t miscSWdebugNW[2];      /* 0x24 */
+   uint32_t miscSoftResetB;        /* 0x2c */
+   uint32_t miscQAMPllStatus;      /* 0x30 */
+   uint32_t miscRsvd1;             /* 0x34 */
+   uint32_t miscSpiMasterCtrl;     /* 0x38 */
+   uint32_t miscAltBootVector;     /* 0x3c */
+   uint32_t miscPeriphCtrl;        /* 0x40 */
+#define MISC_PCIE_CTRL_CORE_SOFT_RESET_MASK     (0x7)
+   uint32_t miscPCIECtrl;          /* 0x44 */
+   uint32_t miscAdsl_clock_sample; /* 0x48 */
+   uint32_t miscRngCtrl;           /* 0x4c */
+   uint32_t miscMbox_data[4];      /* 0x50 */
+   uint32_t miscMbox_ctrl;         /* 0x60 */
+   uint32_t miscxMIIPadCtrl[4];    /* 0x64 */
+#define MISC_XMII_PAD_MODEHV                    (1 << 6)
+#define MISC_XMII_PAD_SEL_GMII                  (1 << 4)
+#define MISC_XMII_PAD_AMP_EN                    (1 << 3)
+   uint32_t miscxMIIPullCtrl[4];    /* 0x74 */
+   uint32_t miscWDResetEn;          /* 0x84 */
+   uint32_t miscBootOverlayEn;      /* 0x88 */
+   uint32_t miscSGMIIFiberDetect;   /* 0x8c */
+#define MISC_SGMII_FIBER_GPIO36     (1<<0)
+   uint32_t miscUniMacCtrl;         /* 0x90 */
+   uint32_t miscMaskUBUSErr;        /* 0x94 */
+   uint32_t miscTOSsync;            /* 0x98 */
+   uint32_t miscPM0_1_status;       /* 0x9c */
+   uint32_t miscPM2_3_status;       /* 0xa0 */
+   uint32_t miscSGB_status;         /* 0xa4 */
+   uint32_t miscPM0_1_config;       /* 0xa8 */
+   uint32_t miscPM2_3_config;       /* 0xac */
+   uint32_t miscSGB_config;         /* 0xb0 */
+   uint32_t miscPM0_1_tmon_config;  /* 0xb4 */
+   uint32_t miscPM2_3_tmon_config;  /* 0xb8 */
+   uint32_t miscSGB_tmon_config;    /* 0xbc */
+   uint32_t miscMDIOmasterSelect;   /* 0xc0 */
+   uint32_t miscUSIMCtrl;           /* 0xc4 */
+   uint32_t miscUSIMPadCtrl;        /* 0xc8 */
+   uint32_t miscPerSpareReg[3];     /* 0xcc - 0xd4 */
+   uint32_t miscDgSensePadCtrl;     /* 0xd8 */
+#define DG_CTRL_SHIFT   4
+#define DG_EN_SHIFT     3
+#define DG_TRIM_SHIFT   0
+   uint32_t miscPeriphMiscCtrl;     /* 0xdc */
+   uint32_t miscPeriphMiscStat;     /* 0xe0 */
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4908/otp.h b/arch/arm/include/asm/arch-bcm4908/otp.h
new file mode 100644
index 0000000000..0205626333
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/otp.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _4908_OTP_H
+#define _4908_OTP_H
+
+#define JTAG_OTP_BASE    0xff800e00
+
+/* row 14 */
+#define OTP_CPU_CORE_CFG_ROW			14
+#define OTP_CPU_CORE_CFG_SHIFT			14
+#define OTP_CPU_CORE_CFG_MASK			0x3
+
+#define OTP_SGMII_DISABLE_ROW			14
+#define OTP_SGMII_DISABLE_SHIFT			17
+#define OTP_SGMII_DISABLE_MASK			0x1
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          0x1
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          0x7
+
+/* row 24 */
+#define OTP_CUST_MFG_MRKTID_ROW                 24
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_CPU_CORE_CFG, OTP_CPU_CORE_CFG_ROW, OTP_CPU_CORE_CFG_MASK, OTP_CPU_CORE_CFG_SHIFT, 1},				\
+	{OTP_MAP_SGMII_DISABLE, OTP_SGMII_DISABLE_ROW, OTP_SGMII_DISABLE_MASK, OTP_SGMII_DISABLE_SHIFT, 1},				\
+	}
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4908/pmc.h b/arch/arm/include/asm/arch-bcm4908/pmc.h
new file mode 100644
index 0000000000..a7f53c500f
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/pmc.h
@@ -0,0 +1,347 @@
+#ifndef PMC_H
+#define PMC_H 
+
+#define PMC_BASE        0x80200000
+#define PROC_MON_BASE   0x80280000
+#define JTAG_OTP_BASE   0xff800e00
+/*
+ * Power Management Control
+ */
+typedef struct PmcCtrlReg {
+   /* 0x00 */
+   uint32_t l1Irq4keMask;
+   uint32_t l1Irq4keStatus;
+   uint32_t l1IrqMipsMask;
+   uint32_t l1IrqMipsStatus;
+   /* 0x10 */
+   uint32_t l2IrqGpMask;
+   uint32_t l2IrqGpStatus;
+   uint32_t gpTmr0Ctl;
+   uint32_t gpTmr0Cnt;
+   /* 0x20 */
+   uint32_t gpTmr1Ctl;
+   uint32_t gpTmr1Cnt;
+   uint32_t hostMboxIn;
+   uint32_t hostMboxOut;
+   /* 0x30 */
+#define PMC_CTRL_GP_FLASH_BOOT_STALL                  0x00000080
+   uint32_t gpOut;
+   uint32_t gpIn;
+   uint32_t gpInIrqMask;
+   uint32_t gpInIrqStatus;
+   /* 0x40 */
+   uint32_t dmaCtrl;
+   uint32_t dmaStatus;
+   uint32_t dma0_3FifoStatus;
+   uint32_t unused0[3];   /* 0x4c-0x57 */
+   /* 0x58 */
+   uint32_t l1IrqMips1Mask;
+   uint32_t diagControl;
+   /* 0x60 */
+   uint32_t diagHigh;
+   uint32_t diagLow;
+   uint32_t badAddr;
+   uint32_t addr1WndwMask;
+   /* 0x70 */
+   uint32_t addr1WndwBaseIn;
+   uint32_t addr1WndwBaseOut;
+   uint32_t addr2WndwMask;
+   uint32_t addr2WndwBaseIn;
+   /* 0x80 */
+   uint32_t addr2WndwBaseOut;
+   uint32_t scratch;
+   uint32_t tm;
+   uint32_t softResets;
+   /* 0x90 */
+   uint32_t eb2ubusTimeout;
+   uint32_t m4keCoreStatus;
+   uint32_t gpInIrqSense;
+   uint32_t ubSlaveTimeout;
+   /* 0xa0 */
+   uint32_t diagEn;
+   uint32_t devTimeout;
+   uint32_t ubusErrorOutMask;
+   uint32_t diagCaptStopMask;
+   /* 0xb0 */
+   uint32_t revId;
+   uint32_t gpTmr2Ctl;
+   uint32_t gpTmr2Cnt;
+   uint32_t legacyMode;
+   /* 0xc0 */
+   uint32_t smisbMonitor;
+   uint32_t diagCtrl;
+   uint32_t diagStat;
+   uint32_t diagMask;
+   /* 0xd0 */
+   uint32_t diagRslt;
+   uint32_t diagCmp;
+   uint32_t diagCapt;
+   uint32_t diagCnt;
+   /* 0xe0 */
+   uint32_t diagEdgeCnt;
+   uint32_t unused1[4];   /* 0xe4-0xf3 */
+   /* 0xf4 */
+   uint32_t iopPeriphBaseAddr;
+   uint32_t lfsr;
+   uint32_t unused2;      /* 0xfc-0xff */
+} PmcCtrlReg;
+
+typedef struct PmcOutFifoReg {
+   uint32_t msgCtrl;      /* 0x00 */
+   uint32_t msgSts;       /* 0x04 */
+   uint32_t unused[14];   /* 0x08-0x3f */
+   uint32_t msgData[16];  /* 0x40-0x7c */
+} PmcOutFifoReg;
+
+typedef struct PmcInFifoReg {
+   uint32_t msgCtrl;      /* 0x00 */
+   uint32_t msgSts;       /* 0x04 */
+   uint32_t unused[13];   /* 0x08-0x3b */
+   uint32_t msgLast;      /* 0x3c */
+   uint32_t msgData[16];  /* 0x40-0x7c */
+} PmcInFifoReg;
+
+typedef struct PmcDmaReg {
+   /* 0x00 */
+   uint32_t src;
+   uint32_t dest;
+   uint32_t cmdList;
+   uint32_t lenCtl;
+   /* 0x10 */
+   uint32_t rsltSrc;
+   uint32_t rsltDest;
+   uint32_t rsltHcs;
+   uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+   /* 0x00 */
+   uint32_t bufSize;
+   uint32_t bufBase;
+   uint32_t idx2ptrIdx;
+   uint32_t idx2ptrPtr;
+   /* 0x10 */
+   uint32_t unused[2];
+   uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+   /* 0x00 */
+   uint32_t dcacheHit;
+   uint32_t dcacheMiss;
+   uint32_t icacheHit;
+   uint32_t icacheMiss;
+   /* 0x10 */
+   uint32_t instnComplete;
+   uint32_t wtbMerge;
+   uint32_t wtbNoMerge;
+   uint32_t itlbHit;
+   /* 0x20 */
+   uint32_t itlbMiss;
+   uint32_t dtlbHit;
+   uint32_t dtlbMiss;
+   uint32_t jtlbHit;
+   /* 0x30 */
+   uint32_t jtlbMiss;
+   uint32_t powerSubZone;
+   uint32_t powerMemPda;
+   uint32_t freqScalarCtrl;
+   /* 0x40 */
+   uint32_t freqScalarMask;
+} PmcPerfPowReg;
+
+typedef struct PmcDQMReg {
+   /* 0x00 */
+   uint32_t cfg;
+   uint32_t _4keLowWtmkIrqMask;
+   uint32_t mipsLowWtmkIrqMask;
+   uint32_t lowWtmkIrqMask;
+   /* 0x10 */
+   uint32_t _4keNotEmptyIrqMask;
+   uint32_t mipsNotEmptyIrqMask;
+   uint32_t notEmptyIrqSts;
+   uint32_t queueRst;
+   /* 0x20 */
+   uint32_t notEmptySts;
+   uint32_t nextAvailMask;
+   uint32_t nextAvailQueue;
+   uint32_t mips1LowWtmkIrqMask;
+   /* 0x30 */
+   uint32_t mips1NotEmptyIrqMask;
+   uint32_t autoSrcPidInsert;
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+   uint32_t cntr[10];
+   uint32_t unused[6]; /* 0x28-0x3f */
+   uint32_t cntrIrqMask;
+   uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+   uint32_t size;
+   uint32_t cfga;
+   uint32_t cfgb;
+   uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+   uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+   uint32_t qNumFull[32];
+   uint32_t qNumEmpty[32];
+   uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+typedef struct Pmc {
+   uint32_t baseReserved;    /* 0x0000 */
+   uint32_t unused0[1023];
+   PmcCtrlReg ctrl;     /* 0x1000 */
+
+   PmcOutFifoReg outFifo;     /* 0x1100 */
+   uint32_t unused1[32];     /* 0x1180-0x11ff */
+   PmcInFifoReg inFifo;    /* 0x1200 */
+   uint32_t unused2[32];     /* 0x1280-0x12ff */
+
+   PmcDmaReg dma[2];    /* 0x1300 */
+   uint32_t unused3[48];     /* 0x1340-0x13ff */
+
+   PmcTokenReg token;      /* 0x1400 */
+   uint32_t unused4[121];    /* 0x141c-0x15ff */
+
+   PmcPerfPowReg perfPower;   /* 0x1600 */
+   uint32_t unused5[47];     /* 0x1644-0x16ff */
+
+   uint32_t msgId[32];    /* 0x1700 */
+   uint32_t unused6[32];     /* 0x1780-0x17ff */
+
+   PmcDQMReg dqm;       /* 0x1800 */
+   uint32_t unused7[50];     /* 0x1838-0x18ff */
+
+   PmcCntReg hwCounter;    /* 0x1900 */
+   uint32_t unused8[46];     /* 0x1948-0x19ff */
+
+   PmcDqmQCtrlReg dqmQCtrl[32];  /* 0x1a00 */
+   PmcDqmQDataReg dqmQData[32];  /* 0x1c00 */
+   uint32_t unused9[64];     /* 0x1e00-0x1eff */
+
+   uint32_t qStatus[32];     /* 0x1f00 */
+   uint32_t unused10[32];    /* 0x1f80-0x1fff */
+
+   PmcDqmQMibReg qMib;     /* 0x2000 */
+   uint32_t unused11[1952];     /* 0x2180-0x3ffff */
+
+   uint32_t sharedMem[512];    /* 0x4000-0x47ff */
+} Pmc;
+
+#define PMC ((volatile Pmc * const) PMC_BASE)
+
+/*
+ * Process Monitor Module
+ */
+typedef struct PMRingOscillatorControl {
+   uint32_t control;
+   uint32_t en_lo;
+   uint32_t en_mid;
+   uint32_t en_hi;
+   uint32_t idle_lo;
+   uint32_t idle_mid;
+   uint32_t idle_hi;
+} PMRingOscillatorControl;
+
+#define RCAL_0P25UM_HORZ          0
+#define RCAL_0P25UM_VERT          1
+#define RCAL_0P5UM_HORZ           2
+#define RCAL_0P5UM_VERT           3
+#define RCAL_1UM_HORZ             4
+#define RCAL_1UM_VERT             5
+#define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
+#define PMMISC_RMON_VALID_MASK    (0x1<<16)
+typedef struct PMMiscControl {
+   uint32_t gp_out;
+   uint32_t clock_select;
+   uint32_t unused[2];
+   uint32_t misc[4];
+} PMMiscControl;
+
+typedef struct PMSSBMasterControl {
+   uint32_t control;
+#define PMC_SSBM_CONTROL_SSB_START  (1<<15)
+#define PMC_SSBM_CONTROL_SSB_ADPRE  (1<<13)
+#define PMC_SSBM_CONTROL_SSB_EN     (1<<12)
+#define PMC_SSBM_CONTROL_SSB_CMD_SHIFT (10)
+#define PMC_SSBM_CONTROL_SSB_CMD_MASK  (0x3 << PMC_SSBM_CONTROL_SSB_CMD_SHIFT)
+#define PMC_SSBM_CONTROL_SSB_CMD_READ  (2)
+#define PMC_SSBM_CONTROL_SSB_CMD_WRITE (1)
+#define PMC_SSBM_CONTROL_SSB_ADDR_SHIFT   (0)
+#define PMC_SSBM_CONTROL_SSB_ADDR_MASK (0x3ff << PMC_SSBM_CONTROL_SSB_ADDR_SHIFT)
+   uint32_t wr_data;
+   uint32_t rd_data;
+} PMSSBMasterControl;
+
+typedef struct PMEctrControl {
+   uint32_t control;
+   uint32_t interval;
+   uint32_t thresh_lo;
+   uint32_t thresh_hi;
+   uint32_t count;
+} PMEctrControl;
+
+typedef struct PMBMaster {
+   uint32_t ctrl;
+#define PMC_PMBM_START     (1 << 31)
+#define PMC_PMBM_TIMEOUT   (1 << 30)
+#define PMC_PMBM_SLAVE_ERR (1 << 29)
+#define PMC_PMBM_BUSY      (1 << 28)
+#define PMC_PMBM_Read      (0 << 20)
+#define PMC_PMBM_Write     (1 << 20)
+   uint32_t wr_data;
+   uint32_t timeout;
+   uint32_t rd_data;
+   uint32_t unused[4];
+} PMBMaster;
+
+typedef struct PMAPVTMONControl {
+   uint32_t control;
+   uint32_t reserved;
+   uint32_t cfg_lo;
+   uint32_t cfg_hi;
+   uint32_t data;
+   uint32_t vref_data;
+   uint32_t unused[2];
+   uint32_t ascan_cfg;
+   uint32_t warn_temp;
+   uint32_t reset_temp;
+   uint32_t temp_value;
+   uint32_t data1_value;
+   uint32_t data2_value;
+   uint32_t data3_value;
+} PMAPVTMONControl;
+
+typedef struct PMUBUSCfg {
+   uint32_t window[8];
+   uint32_t control;
+} PMUBUSCfg;
+
+typedef struct ProcessMonitorRegs {
+   uint32_t MonitorCtrl;     /* 0x00 */
+   uint32_t unused0[7];
+   PMRingOscillatorControl ROSC; /* 0x20 */
+   uint32_t unused1;
+   PMMiscControl Misc;     /* 0x40 */
+   PMSSBMasterControl SSBMaster; /* 0x60 */
+   uint32_t unused2[5];
+   PMEctrControl Ectr;     /* 0x80 */
+   uint32_t unused3[11];
+   PMBMaster PMBM[2];      /* 0xc0 */
+   PMAPVTMONControl APvtmonCtrl; /* 0x100 */
+   uint32_t unused4[9];
+   PMUBUSCfg UBUSCfg;      /* 0x160 */
+} ProcessMonitorRegs;
+
+#define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE)
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4908/pmc_addr.h b/arch/arm/include/asm/arch-bcm4908/pmc_addr.h
new file mode 100644
index 0000000000..970d5540f6
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/pmc_addr.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef PMC_ADDR_4908_H__
+#define PMC_ADDR_4908_H__
+
+#define PMB_BUS_MAX			2
+#define PMB_BUS_ID_SHIFT		8
+
+#define PMB_BUS_PERIPH			0
+#define PMB_ADDR_PERIPH			(0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH		4
+
+#define PMB_BUS_CRYPTO                  0
+#define PMB_ADDR_CRYPTO                 (1 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CRYPTO                1
+
+#define PMB_BUS_PCIE2			0
+#define PMB_ADDR_PCIE2			(2 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE2			1
+
+#define PMB_BUS_RDP			0
+#define PMB_ADDR_RDP			(3 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_RDP			2
+
+#define PMB_BUS_FPM			0
+#define PMB_ADDR_FPM			(4 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_FPM			1
+
+#define PMB_BUS_DQM			0
+#define PMB_ADDR_DQM			(5 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_DQM			1
+
+#define PMB_BUS_URB			0
+#define PMB_ADDR_URB			(6 | PMB_BUS_URB << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_URB			1
+
+#define PMB_BUS_MEMC			0
+#define PMB_ADDR_MEMC			(7 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC			1
+
+#define PMB_BUS_RDPPLL			0
+#define PMB_ADDR_RDPPLL			(8 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_RDPPLL		0
+
+#define PMB_BUS_B53PLL			0
+#define PMB_ADDR_B53PLL			(9 | PMB_BUS_B53PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_B53PLL		0
+
+#define PMB_BUS_SWITCH			1
+#define PMB_ADDR_SWITCH			(10 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SWITCH		3
+
+#define PMB_BUS_PCM			1
+#define PMB_ADDR_PCM			(11 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCM			2
+enum {
+	PCM_Zone_Main,
+	PCM_Zone_PCM,
+};
+//--------- SOFT Reset bits for PCM ------------------------
+#define   BPCM_PCM_SRESET_HARDRST_N   0x00000004
+#define   BPCM_PCM_SRESET_PCM_N       0x00000002
+#define   BPCM_PCM_SRESET_200_N       0x00000001
+
+#define PMB_BUS_SGMII  			1
+#define PMB_ADDR_SGMII			(12 | PMB_BUS_SGMII << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SGMII			0
+
+#define PMB_BUS_CHIP_CLKRST		1
+#define PMB_ADDR_CHIP_CLKRST		(13 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST		0
+
+#define PMB_BUS_PCIE0			1
+#define PMB_ADDR_PCIE0			(14 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0			1
+
+#define PMB_BUS_PCIE1			1
+#define PMB_ADDR_PCIE1			(15 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1			1
+
+#define PMB_BUS_SATA			1
+#define PMB_ADDR_SATA			(16 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SATA			1
+
+#define PMB_BUS_USB				1
+#define PMB_ADDR_USB30_2X		(17 | PMB_BUS_USB << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB			4
+
+#define PMB_BUS_SYSPLL			1
+#define PMB_ADDR_SYSPLL			(18 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL		0
+
+#define PMB_BUS_SWTPLL			1
+#define PMB_ADDR_SWTPLL			(19 | PMB_BUS_SWTPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SWTPLL		0
+
+#define PMB_BUS_I2SPLL			1
+#define PMB_ADDR_I2SPLL			(20 | PMB_BUS_I2SPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_I2SPLL		0
+
+#define PMB_BUS_GMAC			1
+#define PMB_ADDR_GMAC			(21 | PMB_BUS_GMAC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_GMAC			1
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-bcm4908/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm4908/pmc_drv_cfg.h
new file mode 100644
index 0000000000..1c44eeaf44
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/pmc_drv_cfg.h
@@ -0,0 +1,39 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_1_X
+
+#define PMC_CPU_BIG_ENDIAN   1
+#define PMC_GETRCAL_SUPPORT  1
+#define PMC_RECLOSE_SUPPORT  1
+#define PMC_STALL_SUPPORT    1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm4908/rng.h b/arch/arm/include/asm/arch-bcm4908/rng.h
new file mode 100644
index 0000000000..39aacee946
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4908/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4908_RNG_H
+#define _4908_RNG_H
+
+#define RNG_BASE	0xff800b80
+
+typedef struct Rng {
+   uint32_t ctrl0;                 /* 0x00 */
+   uint32_t rngSoftReset;          /* 0x04 */
+   uint32_t rbgSoftReset;          /* 0x08 */
+   uint32_t totalBitCnt;           /* 0x0c */
+   uint32_t totalBitCntThreshold;  /* 0x10 */
+   uint32_t revId;                 /* 0x14 */
+   uint32_t intStatus;             /* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL       (0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL       (0x1<<2)
+   uint32_t intEn;                 /* 0x1c */
+   uint32_t rngFifoData;           /* 0x20 */
+   uint32_t fifoCnt;               /* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS           0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS           0x33
+   uint32_t perm;                  /* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4912/BPCM.h b/arch/arm/include/asm/arch-bcm4912/BPCM.h
new file mode 100644
index 0000000000..28f420de4f
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/BPCM.h
@@ -0,0 +1,806 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmbAddr:12;	// [11:00]
+		uint32_t map_rev:4;	// [15:12] always non-zero for AVS3 devices (see CLASSIC_BPCM_ID_REG below)
+		uint32_t island:4;	// [19:16]
+		uint32_t devType:4;	// [23:20] see enum above
+		uint32_t hw_rev:8;	// [31:24]
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+// types of PMB devices
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:6;
+		uint32_t reserved0:2;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu_reset_n:8;	// 07:00    R/W
+		uint32_t c0l2_reset:1;	// 08:08    R/W
+		uint32_t c1l2_reset:1;	// 09:09    R/W
+		uint32_t reserved0:6;	// 15:10    R/O
+		uint32_t cpu_bpcm_init_on:8;	// 23:16    R/W
+		uint32_t c0l2_bpcm_init_on:1;	// 24:24    R/W
+		uint32_t c1l2_bpcm_init_on:1;	// 25:25    R/W
+		uint32_t ubus_sr:1;	// 26:26    R/W
+		uint32_t cci_sr:1;	// 27:27    R/W
+		uint32_t webcores_sr:1;	// 28:28    R/W
+		uint32_t hw_done:1;	// 29:29    R/O
+		uint32_t sw_done:1;	// 30:30    R/W
+		uint32_t start:1;	// 31:31    R/W
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;		// 09:00
+		uint32_t reserved0:2;		// 11:10
+		uint32_t fref_eff_info:8;	// 19:12
+		uint32_t auto_cnfg_dsbl:8;	// 27:20
+		uint32_t reserved1:3;		// 30:28
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t ndiv_frac:24;	// 27:04
+		uint32_t reserved0:3;	// 30:28
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:9;	// 08:00  
+		uint32_t enableb_ch0:1;	// 09:09
+		uint32_t hold_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:9;	// 24:16
+		uint32_t enableb_ch1:1;	// 25:25
+		uint32_t hold_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:8;	// 07:00
+		uint32_t stat_select:3;	// 10:08
+		uint32_t pq_mode:1;	// 11:11
+		uint32_t stat_mode:2;	// 13:12
+		uint32_t stat_reset:1;	// 14:14  
+		uint32_t stat_update:1;	// 15:15  
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 9:0	  
+		uint32_t ndiv_frac:22;	// 31:10
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECNDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t mdiv5:9;	// 12:04
+		uint32_t mdiv0:9;	// 21:13
+		uint32_t mdiv1:9;	// 30:22
+		uint32_t reserved0:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECPDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv2:9;	// 08:00
+		uint32_t mdiv3:9;	// 17:09
+		uint32_t mdiv4:9;	// 26:18
+		uint32_t reserved0:5;	// 31:27
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECCH25_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	uint32_t reserved0;
+	uint32_t timer_control;
+	uint32_t timer_status;
+	uint32_t reserved1[2];
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+typedef union {
+	struct {
+		uint32_t ubus_soft_reset:1;
+		uint32_t alt_ubus_clk_sel:1;
+		uint32_t observe_clk_sw_init:1;
+		uint32_t alt_emmc_clk_sel:1;
+		uint32_t reserved:5;
+		uint32_t enable:1;
+		uint32_t counter:8;
+		uint32_t reserved2:14;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CLKRST_VREG_CONTROL;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	// BPCM
+	uint32_t control;	// offset 0x10, PMB reg index 4
+	BPCM_SR_CONTROL sr_control;	// offset 0x14, PMB reg index 5
+	uint32_t reserved1[2];	// offset 0x18, PMB reg index 6/7
+	// Client-specific registers
+	uint32_t client_specific[24];	// offset 0x20, PMB reg index 8..31
+	// Zones
+	BPCM_ZONE zones[];	// offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1))
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	uint32_t rvrsd[2];
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_VDSL_REGS;		// total offset space = 4096
+
+#define BPCMVDSLOffset(reg)	offsetof(BPCM_VDSL_REGS,reg)
+#define BPCMVDSLRegOffset(reg)	(BPCMVDSLOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08, actual offset = 2
+	uint32_t cfg_control;	// offset = 0x10, actual offset = 4
+	BPCM_SR_CONTROL sr_control;	// offset = 0x14, actual offset = 5
+	uint32_t reserved1[2];	// offset = 0x18, actual offset = 6
+	BPCM_ZONE zones;	// offset = 0x20, actual offset = 8
+	ARM_CONTROL_REG arm_control;	// offset = 0x40, actual offset = 16
+} ARM_BPCM_REGS;
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	/* BIU PLL BCPM definition */  
+	BPCM_ID_REG id_reg;	// offset = 0x00 
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04
+	uint32_t reserved0[2];	// offset = 0x08..0x0c
+	PLL_CTRL_REG resets;	// offset = 0x10
+	uint32_t reserved1[2];	// offset = 0x14
+	PLL_NDIV_REG ndiv;	// offset = 0x1c
+	PLL_PDIV_REG pdiv;	// offset = 0x20
+	PLL_LOOP0_REG loop0;	// offset = 0x24
+	PLL_LOOP1_REG loop1;	// offset = 0x28
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34
+	uint32_t reserved2;	// offset = 0x38
+	PLL_STAT_REG stat;	// offset = 0x3c
+	uint32_t strap;		// offset = 0x40
+	PLL_DECNDIV_REG decndiv;// offset = 0x44
+	PLL_DECPDIV_REG decpdiv;// offset = 0x48
+	PLL_DECCH25_REG decch25;// offset = 0x4c
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04
+	uint32_t reserved0[2];	// offset = 0x08..0x0c
+	PLL_CTRL_REG resets;	// offset = 0x10
+	uint32_t reserved1[5];	// offset = 0x14
+	PLL_NDIV_REG ndiv;	// offset = 0x28
+	PLL_PDIV_REG pdiv;	// offset = 0x2c
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x30
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x34
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x38
+	PLL_STAT_REG stat;	// offset = 0x3c
+	uint32_t strap;		// offset = 0x40
+	PLL_DECNDIV_REG decndiv;// offset = 0x44
+	PLL_DECPDIV_REG decpdiv;// offset = 0x48
+	PLL_DECCH25_REG decch25;// offset = 0x4c
+} RDPPLL_BPCM_REGS;
+
+#define RDPPLLBPCMOffset(reg)		offsetof(RDPPLL_BPCM_REGS,reg)
+#define RDPPLLBPCMRegOffset(reg)	(RDPPLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved1;	// offset = 0x2c, actual offset = 11
+	uint32_t clkrst_cfg;	// offset = 0x30, actual offset = 12
+	BPCM_CLKRST_VREG_CONTROL vreg_control;  // offset = 0x34, actual offset = 13
+	uint32_t xtal_control;	// offset = 0x38, actual offset = 14
+	uint32_t clkrst_stat;	// offset = 0x3c, actual offset = 15
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+typedef struct {
+    // ETH_PMB
+	BPCM_ID_REG id_reg;	    // offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved8[2];	// offset 0x08, PMB reg index 2/3
+	// ETH_CFG
+	uint32_t dpg_zones;	    // offset 0x10, PMB reg index 4
+	uint32_t soft_rst;;	    // offset 0x14, PMB reg index 5
+	uint32_t reserved18[2];	// offset 0x18, PMB reg index 6/7
+    // ETH_CORE
+	uint32_t qphy_cntrl;	// offset 0x20
+	uint32_t qphy_status;	// offset 0x24
+	uint32_t reserved28[2];
+	uint32_t serdes0_cntrl;	// offset 0x30
+	uint32_t serdes0_status;// offset 0x34
+	uint32_t serdes0_an_st; // offset 0x38
+	uint32_t serdes1_cntrl;	// offset 0x3c
+	uint32_t serdes1_status;// offset 0x40
+	uint32_t serdes1_an_st; // offset 0x44
+	uint32_t serdes2_cntrl;	// offset 0x48
+	uint32_t serdes2_status;// offset 0x4c
+	uint32_t serdes2_an_st; // offset 0x50
+	uint32_t rgmii_cntrl;   // offset 0x54
+	uint32_t xport0_cntrl;  // offset 0x58
+	uint32_t xport1_cntrl;  // offset 0x5c
+	uint32_t serdes0_st1;   // offset 0x60
+	uint32_t serdes1_st1;   // offset 0x64
+	uint32_t serdes2_st1;   // offset 0x68
+	uint32_t serdes0_pwr_cntrl;// offset 0x6c
+	uint32_t serdes1_pwr_cntrl;// offset 0x70
+	uint32_t serdes2_pwr_cntrl;// offset 0x74
+} BPCM_ETH_REGS;
+
+#define BPCMETHOffset(reg)		offsetof(BPCM_ETH_REGS,reg)
+#define BPCMETHRegOffset(reg)	(BPCMETHOffset(reg) >> 2)
+
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4912/boot0.h b/arch/arm/include/asm/arch-bcm4912/boot0.h
new file mode 100644
index 0000000000..4e65b99e1a
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/boot0.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4912_BOOT0_H
+#define _4912_BOOT0_H
+
+#include <asm-offsets.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+_bcm_boot:
+	tlbi	alle3			/* Invalidate TLB */
+	dsb	sy
+	isb
+
+	ic	ialluis			/* Invalidate icache */
+	isb
+
+	/* Initialize system control register enable i-cache */
+	mrs	x0, sctlr_el3
+	movn	x1, #(CR_M | CR_C)
+	and	x0, x1, x0
+	orr	x0, x0, #CR_I
+	msr	sctlr_el3, x0
+	isb
+
+	/* relocate the code, init'ed data from flash to lmem  */	
+relo_image:
+	adr     x1, _bcm_boot		/* x1 source address in flash */
+	ldr	x0, =__image_copy_start	/* x0 dest address in sram */
+	subs	x4, x1, x0		/* x4 relocation offset */
+	beq	relo_dtb		/* skip relocation */
+	ldr	x2, =__image_copy_end	/* x2 dest ending address in flash */
+
+relo_loop:
+	ldp	x5, x6, [x1], #16
+	stp	x5, x6, [x0], #16
+	cmp	x0, x2
+	blo	relo_loop
+
+	/* if we attached dtb after bss, need to relocate dtb as well */	
+relo_dtb:
+#if defined(CONFIG_SPL_OF_CONTROL) && defined(CONFIG_OF_SEPARATE)
+
+#ifdef CONFIG_OF_SPL_SEPARATE_BSS
+	ldr	x3, =__image_binary_end
+#else
+	ldr	x3, =_end
+#endif
+	add	x1, x3, x4       /* r1 source address in flash */
+	mov	x0, xzr
+	mov	x2, xzr
+	/* check ftd size ... */
+	/* struct fdt_header {
+	fdt32_t magic;
+	fdt32_t totalsize; */
+	ldr	w0, [x1, #4]	/* r0 total size */
+	rev	w0, w0          /* byte order from fdt to little endian */
+	lsr	w0, w0, #2      /* in the order of 4 bytes aligned */
+	add	w0, w0, #1
+	lsl	w0, w0, #2 
+	add	x2, x1, x0       /* r2 dest ending address in flash */
+	mov	x0, x3           /* r0 dest address in sram */
+
+dtb_loop:
+	ldp	x5, x6, [x1], #16
+	stp	x5, x6, [x0], #16
+	cmp	x1, x2
+	blo	dtb_loop
+#endif
+	ldr	x0, =reset
+	br	x0
+
+#else
+	b	reset
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4912/brom.h b/arch/arm/include/asm/arch-bcm4912/brom.h
new file mode 100644
index 0000000000..ad3b8516c7
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4912_BROM_H
+#define _4912_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4912/cpu.h b/arch/arm/include/asm/arch-bcm4912/cpu.h
new file mode 100644
index 0000000000..327c70a79f
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/cpu.h
@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4912_CPU_H
+#define _4912_CPU_H
+
+#include <common.h>
+
+
+typedef struct CCI500_SlaveIntf {
+	#define SNOOP_CTRL_ENABLE_SNOOP            0x1
+	uint32_t snoop_ctrl;	/* 0x0 */
+	#define SHARE_OVR_SHAREABLE_OVR_SHIFT      0x0
+	#define SHARE_OVR_SHAREABLE_OVR_MASK       0x3
+	#define SHARE_OVR_SHAREABLE_OVR_NONSHR     0x2
+	#define SHARE_OVR_SHAREABLE_OVR_SHR        0x3
+	uint32_t share_ovr;	/* 0x4 */
+	uint32_t rsvd1[62];	/* 0x8 - 0xff */
+	uint32_t arqos_ovr;	/* 0x100 */
+	uint32_t awqos_ovr;	/* 0x104 */
+	uint32_t rsvd2[2];	/* 0x108 - 0x10f */
+	uint32_t qos_max_ot;	/* 0x110 */
+	uint32_t rsvd3[955];	/* 0x114 - 0xfff */
+}CCI500_SlaveIntf;
+
+typedef struct CCI500_EventCounter {
+	uint32_t sel;	/* 0x0 */
+	uint32_t data;	/* 0x4 */
+	uint32_t ctrl;	/* 0x8 */
+	uint32_t clr_ovfl;	/* 0xC */
+	uint32_t rsvd[16380];	/* 0x10 - 0xffff */
+}CCI500_EventCounter;
+
+typedef struct CCI500 {
+	#define CONTROL_OVERRIDE_SNOOP_DISABLE     0x1
+	#define CONTROL_OVERRIDE_SNOOP_FLT_DISABLE 0x4
+	uint32_t ctrl_ovr;	/* 0x0 */
+	uint32_t rsvd1;	/* 0x4 */
+	#define SECURE_ACCESS_UNSECURE_ENABLE      0x1
+	uint32_t secr_acc;	/* 0x8 */
+	uint32_t status;	/* 0xc */
+	#define STATUS_CHANGE_PENDING              0x1
+	uint32_t impr_err;	/* 0x10 */
+	uint32_t qos_threshold;	/* 0x14 */
+	uint32_t rsvd2[58];	/* 0x18 - 0xff */
+	uint32_t pmu_ctrl;	/* 0x100 */
+	#define DBG_CTRL_EN_INTF_MON               0x1
+	uint32_t debug_ctrl;	/* 0x104 */
+	uint32_t rsvd3[958];	/* 0x108 - 0xfff */
+	#define SLAVEINTF_COHERENCY_PORT           0x0
+	#define SLAVEINTF_CPU_CLUSTER              0x1
+	CCI500_SlaveIntf si[7];	/* 0x1000 - 0x7fff */
+	uint32_t rsvd4[8192];	/* 0x8000 - 0xffff */
+	CCI500_EventCounter evt_cntr[8];	/* 0x10000 - 0x8ffff */
+}CCI500;
+
+#define CCI500_BASE	0x81100000
+#define CCI500 ((volatile CCI500 * const) CCI500_BASE)
+
+typedef struct UBUS4_RANGE_CHK_CFG {
+	uint32_t control;	/* 0x0 */
+	uint32_t srcpid[8];	/* 0x4 - 0x23 */
+	uint32_t seclev;	/* 0x24 */
+	uint32_t base;		/* 0x28 */
+	uint32_t base_up;  	/* 0x2c */
+}UBUS4_RANGE_CHK_CFG;
+
+typedef struct UBUS4_RANGE_CHK_SETUP {
+	uint32_t lock;			/* 0x0 */
+	uint32_t log_inf[3];  		/* 0x4 - 0xf */
+	UBUS4_RANGE_CHK_CFG cfg[16];	/* 0x10 - 0x30f */
+}UBUS4_RANGE_CHK_SETUP;
+
+#define UBUS4_COHERENCY_PORT_BASE	0x810A0000
+#define UBUS4_RANGE_CHK_SETUP_OFFSET    0x0
+#define UBUS4_RANGE_CHK_SETUP_BASE	(UBUS4_COHERENCY_PORT_BASE+UBUS4_RANGE_CHK_SETUP_OFFSET)
+#define UBUS4_RANGE_CHK_SETUP 		((volatile UBUS4_RANGE_CHK_SETUP * const) UBUS4_RANGE_CHK_SETUP_BASE)
+
+typedef struct BIUCFG_Access {
+	uint32_t permission;	/* 0x0 */
+	uint32_t sbox;	/* 0x4 */
+	uint32_t cpu_defeature;	/* 0x8 */
+	uint32_t dbg_security;	/* 0xc */
+	uint32_t rsvd1[32];	/* 0x10 - 0x8f */
+	uint64_t violation[2];	/* 0x90 - 0x9f */
+	uint32_t ts_access[2];	/* 0xa0 - 0xa7 */
+	uint32_t rsvd2[22];	/* 0xa8 - 0xff */
+}BIUCFG_Access;
+
+typedef struct BIUCFG_Cluster {
+	uint32_t permission;	/* 0x0 */
+	uint32_t config;	/* 0x4 */
+	uint32_t status;	/* 0x8 */
+	uint32_t control;	/* 0xc */
+	uint32_t cpucfg;	/* 0x10 */
+	uint32_t dbgrom;	/* 0x14 */
+	uint32_t rsvd1[2];	/* 0x18 - 0x1f */
+	uint64_t rvbar_addr[4];	/* 0x20 - 0x3f */
+	uint32_t rsvd2[48];	/* 0x40 - 0xff */
+}BIUCFG_Cluster;
+
+typedef struct BIUCFG_Bac {
+	uint32_t bac_permission;	/* 0x00 */
+	uint32_t bac_periphbase;	/* 0x04 */
+	uint32_t rsvd[2];	/* 0x08 - 0x0f */
+	uint32_t bac_event;	/* 0x10 */
+	uint32_t rsvd_1[3];	/* 0x14 - 0x1f */
+	uint32_t bac_ccicfg;	/* 0x20 */
+	uint32_t bac_cciaddr;	/* 0x24 */
+	uint32_t rsvd_2[4];	/* 0x28 - 0x37 */
+	uint32_t bac_ccievs2;	/* 0x38 */
+	uint32_t bac_ccievs3;	/* 0x3c */
+	uint32_t bac_ccievs4;	/* 0x40 */
+	uint32_t rsvd_3[3];	/* 0x44 - 0x4f */
+	uint32_t bac_ccievm0;	/* 0x50 */
+	uint32_t bac_ccievm1;	/* 0x54 */
+	uint32_t rsvd_4[2];	/* 0x58 - 0x5f */
+	uint32_t bac_dapapbcfg;	/* 0x60 */
+	uint32_t bac_status;	/* 0x64 */
+	uint32_t rsvd_5[2];	/* 0x68 - 0x6f */
+	uint32_t cpu_therm_irq_cfg;	/* 0x70 */
+	uint32_t cpu_therm_threshold_cfg;	/* 0x74 */
+	uint32_t rsvd_6;	/* 0x78 */
+	uint32_t cpu_therm_temp;	/* 0x7c */
+	uint32_t rsvd_7[32];	/* 0x80 - 0xff */
+} BIUCFG_Bac;
+
+typedef struct BIUCFG_Aux {
+	uint32_t aux_permission;	/* 0x00 */
+	uint32_t rsvd[3];	/* 0x04 - 0x0f */
+	uint32_t c0_clk_control;	/* 0x10 */
+	uint32_t c0_clk_ramp;	/* 0x14 */
+	uint32_t c0_clk_pattern;	/* 0x18 */
+	uint32_t rsvd_1;	/* 0x1c */
+	uint32_t c1_clk_control;	/* 0x20 */
+	uint32_t c1_clk_ramp;	/* 0x24 */
+	uint32_t c1_clk_pattern;	/* 0x28 */
+	uint32_t rsvd_2[53];	/* 0x2c - 0xff */
+} BIUCFG_Aux;
+
+typedef struct BIUCFG_TS0_CTRL {
+	uint32_t CNTCR;		/* 0x00 */
+	uint32_t CNTSR;		/* 0x04 */
+	uint32_t CNTCVL;	/* 0x08 */
+	uint32_t CNTCVU;	/* 0x0c */
+	uint32_t rsvd_0[4];	/* 0x10 - 0x1f */
+	uint32_t CNTFID0;	/* 0x20 */
+	uint32_t rsvd_1[1015];	/* 0x24 - 0xfff */
+} BIUCFG_TS0_CTRL;
+
+typedef struct BIUCFG {
+	BIUCFG_Access access;	/* 0x0 - 0xff*/
+	BIUCFG_Cluster cluster[2];	/* 0x100 - 0x2ff*/
+	BIUCFG_Bac bac;	/* 0x300 - 0x3ff */
+	uint32_t anonymous[192];	/* 0x400 - 0x6ff */
+	BIUCFG_Aux aux;	/* 0x700 - 0x7ff */
+	uint32_t anonymous_1[512];	/* 0x800 - 0xfff */
+	BIUCFG_TS0_CTRL ts0_ctrl;	/* 0x1000 - 0x1fff */
+}BIUCFG;
+
+#define BIUCFG_BASE 0x81060000
+#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4912/ddr.h b/arch/arm/include/asm/arch-bcm4912/ddr.h
new file mode 100644
index 0000000000..1d7980b042
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/ddr.h
@@ -0,0 +1,3242 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4912_DDR_H
+#define _4912_DDR_H
+
+#define MEMC_BASE        0x80040000      /* DDR IO Buf Control */
+#define PHY_BASE         0x80060000      /* DDR PHY base */
+
+
+#define mc2_glb_acc                              0x00000000 
+#define mc2_glb_vers                             0x00000004 
+#define mc2_glb_gcfg                             0x00000008 
+#define mc2_glb_auto_self_refresh                0x0000000c 
+#define mc2_glb_pwr_mgr                          0x00000010 
+
+
+
+#define mc2_axi_acc                              0x00000040 
+#define mc2_axi_ver                              0x00000044 
+#define mc2_axi_CFG                              0x00000048 
+#define mc2_axi_REP_ARB_MODE                     0x0000004c 
+#define mc2_axi_queue_cfg                        0x00000050 
+#define mc2_axi_queue_size0                      0x00000054 
+#define mc2_axi_queue_map0                       0x00000058 
+#define mc2_axi_SCRATCH                          0x00000060 
+#define mc2_axi_AXI_DEBUG_0_0                    0x00000064 
+#define mc2_axi_AXI_DEBUG_1_0                    0x00000068 
+#define mc2_axi_AXI_DEBUG_MISC                   0x0000006c 
+
+
+
+#define mc2_ubus_acc                             0x00000080 
+#define mc2_ubus_CFG                             0x00000084 
+#define mc2_ubus_ESRCID_CFG                      0x00000088 
+#define mc2_ubus_queue_cfg_queue_cfg             0x0000008c 
+#define mc2_ubus_queue_cfg_queue_map0            0x00000090 
+#define mc2_ubus_queue_cfg_queue_map1            0x00000094 
+#define mc2_ubus_queue_cfg_queue_map2            0x00000098 
+#define mc2_ubus_queue_cfg_queue_map3            0x0000009c 
+#define mc2_ubus_queue_cfg_queue_size0           0x000000a0 
+#define mc2_ubus_queue_cfg_queue_size1           0x000000a4 
+#define mc2_ubus_queue_cfg_queue_size2           0x000000a8 
+#define mc2_ubus_queue_cfg_queue_size3           0x000000ac 
+#define mc2_ubus_diag_ctrl                       0x000000b0 
+#define mc2_ubus_scratch                         0x000000b8 
+#define mc2_ubus_debug_ro                        0x000000bc 
+
+
+
+#define mc2_misc_acc                             0x00000200 
+#define mc2_misc_ver                             0x00000204 
+#define mc2_misc_cfg                             0x00000208 
+#define mc2_misc_vq_cfg                          0x0000020c 
+#define mc2_misc_edis_addr_rand                  0x00000210 
+#define mc2_misc_misc_dbg                        0x00000214 
+
+
+
+#define mc2_afx_acc                              0x00000300 
+#define mc2_afx_ver                              0x00000304 
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi 0x00000310 
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo 0x00000314 
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi  0x00000318 
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo  0x0000031c 
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi     0x00000320 
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo     0x00000324 
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi       0x00000328 
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo       0x0000032c 
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi     0x00000330 
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo     0x00000334 
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi       0x00000338 
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo       0x0000033c 
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi     0x00000340 
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo     0x00000344 
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi       0x00000348 
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo       0x0000034c 
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi     0x00000350 
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo     0x00000354 
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi       0x00000358 
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo       0x0000035c 
+#define mc2_afx_srcid_fltr_cfg0_srcid            0x00000360 
+#define mc2_afx_srcid_fltr_cfg1_srcid            0x00000364 
+#define mc2_afx_srcid_fltr_cfg2_srcid            0x00000368 
+#define mc2_afx_srcid_fltr_cfg3_srcid            0x0000036c 
+#define mc2_afx_row_xtr_cfg_row_19_16            0x00000380 
+#define mc2_afx_row_xtr_cfg_row_15_12            0x00000384 
+#define mc2_afx_row_xtr_cfg_row_11_8             0x00000388 
+#define mc2_afx_row_xtr_cfg_row_7_4              0x0000038c 
+#define mc2_afx_row_xtr_cfg_row_3_0              0x00000390 
+#define mc2_afx_bg_xtr_cfg_bg_3_0                0x000003a0 
+#define mc2_afx_bk_xtr_cfg_bk_3_0                0x000003a4 
+#define mc2_afx_col_xtr_cfg_col_cfg              0x000003a8 
+#define mc2_afx_cs_xtr_cfg_cs_3_0                0x000003b4 
+#define mc2_afx_chn_xtr_cfg_chn_bit              0x000003b8 
+#define mc2_afx_ddr_sz_chk                       0x000003bc 
+
+
+
+#define mc2_rchk_acc                             0x00000400 
+#define mc2_rchk_ver                             0x00000404 
+#define mc2_rchk_range_lock                      0x00000410 
+#define mc2_rchk_range_0_control                 0x00000420 
+#define mc2_rchk_range_0_persrcid_port           0x00000424 
+#define mc2_rchk_range_0_persrcid_port_upper     0x00000428 
+#define mc2_rchk_range_0_base                    0x0000042c 
+#define mc2_rchk_range_0_base_upper              0x00000430 
+#define mc2_rchk_range_0_seclev_en               0x00000434 
+#define mc2_rchk_range_1_control                 0x00000440 
+#define mc2_rchk_range_1_persrcid_port           0x00000444 
+#define mc2_rchk_range_1_persrcid_port_upper     0x00000448 
+#define mc2_rchk_range_1_base                    0x0000044c 
+#define mc2_rchk_range_1_base_upper              0x00000450 
+#define mc2_rchk_range_1_seclev_en               0x00000454 
+#define mc2_rchk_range_2_control                 0x00000460 
+#define mc2_rchk_range_2_persrcid_port           0x00000464 
+#define mc2_rchk_range_2_persrcid_port_upper     0x00000468 
+#define mc2_rchk_range_2_base                    0x0000046c 
+#define mc2_rchk_range_2_base_upper              0x00000470 
+#define mc2_rchk_range_2_seclev_en               0x00000474 
+#define mc2_rchk_range_3_control                 0x00000480 
+#define mc2_rchk_range_3_persrcid_port           0x00000484 
+#define mc2_rchk_range_3_persrcid_port_upper     0x00000488 
+#define mc2_rchk_range_3_base                    0x0000048c 
+#define mc2_rchk_range_3_base_upper              0x00000490 
+#define mc2_rchk_range_3_seclev_en               0x00000494 
+#define mc2_rchk_range_4_control                 0x000004a0 
+#define mc2_rchk_range_4_persrcid_port           0x000004a4 
+#define mc2_rchk_range_4_persrcid_port_upper     0x000004a8 
+#define mc2_rchk_range_4_base                    0x000004ac 
+#define mc2_rchk_range_4_base_upper              0x000004b0 
+#define mc2_rchk_range_4_seclev_en               0x000004b4 
+#define mc2_rchk_range_5_control                 0x000004c0 
+#define mc2_rchk_range_5_persrcid_port           0x000004c4 
+#define mc2_rchk_range_5_persrcid_port_upper     0x000004c8 
+#define mc2_rchk_range_5_base                    0x000004cc 
+#define mc2_rchk_range_5_base_upper              0x000004d0 
+#define mc2_rchk_range_5_seclev_en               0x000004d4 
+#define mc2_rchk_range_6_control                 0x000004e0 
+#define mc2_rchk_range_6_persrcid_port           0x000004e4 
+#define mc2_rchk_range_6_persrcid_port_upper     0x000004e8 
+#define mc2_rchk_range_6_base                    0x000004ec 
+#define mc2_rchk_range_6_base_upper              0x000004f0 
+#define mc2_rchk_range_6_seclev_en               0x000004f4 
+#define mc2_rchk_range_7_control                 0x00000500 
+#define mc2_rchk_range_7_persrcid_port           0x00000504 
+#define mc2_rchk_range_7_persrcid_port_upper     0x00000508 
+#define mc2_rchk_range_7_base                    0x0000050c 
+#define mc2_rchk_range_7_base_upper              0x00000510 
+#define mc2_rchk_range_7_seclev_en               0x00000514 
+#define mc2_rchk_log_info_0                      0x00000520 
+#define mc2_rchk_log_info_1                      0x00000524 
+#define mc2_rchk_log_info_2                      0x00000528 
+#define mc2_rlt_acc                              0x00000600 
+#define mc2_rlt_vers                             0x00000604 
+#define mc2_rlt_rate_limiter0_cfg_0              0x00000610 
+#define mc2_rlt_rate_limiter0_cfg_1              0x00000614 
+#define mc2_rlt_rate_limiter1_cfg_0              0x00000618 
+#define mc2_rlt_rate_limiter1_cfg_1              0x0000061c 
+#define mc2_rlt_rate_limiter2_cfg_0              0x00000620 
+#define mc2_rlt_rate_limiter2_cfg_1              0x00000624 
+#define mc2_rlt_rate_limiter3_cfg_0              0x00000628 
+#define mc2_rlt_rate_limiter3_cfg_1              0x0000062c 
+#define mc2_rlt_rate_limiter4_cfg_0              0x00000630 
+#define mc2_rlt_rate_limiter4_cfg_1              0x00000634 
+#define mc2_rlt_rate_limiter5_cfg_0              0x00000638 
+#define mc2_rlt_rate_limiter5_cfg_1              0x0000063c 
+#define mc2_rlt_monitor0_mon_0                   0x00000690 
+#define mc2_rlt_monitor0_mon_1                   0x00000694 
+#define mc2_rlt_monitor1_mon_0                   0x00000698 
+#define mc2_rlt_monitor1_mon_1                   0x0000069c 
+#define mc2_rlt_monitor2_mon_0                   0x000006a0 
+#define mc2_rlt_monitor2_mon_1                   0x000006a4 
+#define mc2_rlt_monitor3_mon_0                   0x000006a8 
+#define mc2_rlt_monitor3_mon_1                   0x000006ac 
+#define mc2_rlt_monitor4_mon_0                   0x000006b0 
+#define mc2_rlt_monitor4_mon_1                   0x000006b4 
+#define mc2_rlt_monitor5_mon_0                   0x000006b8 
+#define mc2_rlt_monitor5_mon_1                   0x000006bc 
+
+#define mc2_chn_ddr_acc                          0x00000900 
+#define mc2_chn_ddr_ver                          0x00000904 
+#define mc2_chn_ddr_chn_arb_cfg                  0x00000908 
+#define mc2_chn_ddr_chn_arb_param                0x0000090c 
+#define mc2_chn_ddr_chn_sch_cfg                  0x00000910 
+#define mc2_chn_ddr_phy_st                       0x00000914 
+#define mc2_chn_ddr_dram_cfg                     0x00000918 
+#define mc2_chn_ddr_dcmd                         0x0000091c 
+#define mc2_chn_ddr_dmode_0                      0x00000920 
+#define mc2_chn_ddr_dmode_2                      0x00000924 
+#define mc2_chn_ddr_odt                          0x00000928 
+#define mc2_chn_ddr_ddr_param_cmd0               0x0000092c 
+#define mc2_chn_ddr_ddr_param_cmd1               0x00000930 
+#define mc2_chn_ddr_ddr_param_cmd2               0x00000934 
+#define mc2_chn_ddr_ddr_param_cmd3               0x00000938 
+#define mc2_chn_ddr_ddr_param_dat0               0x0000093c 
+#define mc2_chn_ddr_ddr_param_dat1               0x00000940 
+#define mc2_chn_ddr_ddr_param_pre0               0x00000944 
+#define mc2_chn_ddr_ddr_param_pwr0               0x00000948 
+#define mc2_chn_ddr_ddr_param_zqc0               0x0000094c 
+#define mc2_chn_ddr_refresh_aref0                0x00000954 
+#define mc2_chn_ddr_refresh_aref1                0x00000958 
+#define mc2_chn_ddr_auto_self_refresh            0x0000095c 
+#define mc2_chn_ddr_auto_zqcs                    0x00000968 
+#define mc2_chn_ddr_dfi_error                    0x0000096c 
+
+
+#define mc2_chn_sram_acc                         0x00000a20 
+#define mc2_chn_sram_ver                         0x00000a24 
+#define mc2_chn_sram_ind_ctrl                    0x00000a28 
+#define mc2_chn_sram_init                        0x00000a2c 
+#define mc2_chn_sram_ind_data0                   0x00000a30 
+#define mc2_chn_sram_ind_data1                   0x00000a34 
+#define mc2_chn_sram_ind_data2                   0x00000a38 
+#define mc2_chn_sram_ind_data3                   0x00000a3c 
+
+
+#define mc2_wbf_acc                              0x00000e80 
+#define mc2_wbf_ver                              0x00000e84 
+#define mc2_wbf_pri_cfg                          0x00000e88 
+#define mc2_wbf_sta                              0x00000e8c 
+#define mc2_wbf_bkdr_bkdr_cmd                    0x00000e90 
+#define mc2_wbf_bkdr_bkdr_data0                  0x00000e94 
+#define mc2_wbf_bkdr_bkdr_data1                  0x00000e98 
+#define mc2_wbf_bkdr_bkdr_data2                  0x00000e9c 
+#define mc2_wbf_bkdr_bkdr_data3                  0x00000ea0 
+#define mc2_wbf_bkdr_bkdr_data4                  0x00000ea4 
+#define mc2_wbf_bkdr_bkdr_data5                  0x00000ea8 
+#define mc2_wbf_bkdr_bkdr_data6                  0x00000eac 
+#define mc2_wbf_bkdr_bkdr_data7                  0x00000eb0 
+#define mc2_wbf_id_bkdr_id_cmd                   0x00000ec0 
+#define mc2_wbf_id_bkdr_id_data                  0x00000ec4 
+
+
+
+#define mc2_rmx_acc                              0x00000ed0 
+#define mc2_rmx_ver                              0x00000ed4 
+#define mc2_rmx_pri_cfg                          0x00000ed8 
+
+
+#define mc2_glb_acc_acc_eack_MASK                                  0x80000000
+#define mc2_glb_acc_acc_eack_ALIGN                                 0
+#define mc2_glb_acc_acc_eack_BITS                                  1
+#define mc2_glb_acc_acc_eack_SHIFT                                 31
+#define mc2_glb_acc_acc_eack_DEFAULT                               0x00000000
+
+
+#define mc2_glb_acc_reserved0_MASK                                 0x7fffff00
+#define mc2_glb_acc_reserved0_ALIGN                                0
+#define mc2_glb_acc_reserved0_BITS                                 23
+#define mc2_glb_acc_reserved0_SHIFT                                8
+
+
+#define mc2_glb_acc_acc_sw_MASK                                    0x00000080
+#define mc2_glb_acc_acc_sw_ALIGN                                   0
+#define mc2_glb_acc_acc_sw_BITS                                    1
+#define mc2_glb_acc_acc_sw_SHIFT                                   7
+#define mc2_glb_acc_acc_sw_DEFAULT                                 0x00000001
+
+
+#define mc2_glb_acc_acc_sr_MASK                                    0x00000040
+#define mc2_glb_acc_acc_sr_ALIGN                                   0
+#define mc2_glb_acc_acc_sr_BITS                                    1
+#define mc2_glb_acc_acc_sr_SHIFT                                   6
+#define mc2_glb_acc_acc_sr_DEFAULT                                 0x00000001
+
+
+#define mc2_glb_acc_acc_nsw_MASK                                   0x00000020
+#define mc2_glb_acc_acc_nsw_ALIGN                                  0
+#define mc2_glb_acc_acc_nsw_BITS                                   1
+#define mc2_glb_acc_acc_nsw_SHIFT                                  5
+#define mc2_glb_acc_acc_nsw_DEFAULT                                0x00000001
+
+
+#define mc2_glb_acc_acc_nsr_MASK                                   0x00000010
+#define mc2_glb_acc_acc_nsr_ALIGN                                  0
+#define mc2_glb_acc_acc_nsr_BITS                                   1
+#define mc2_glb_acc_acc_nsr_SHIFT                                  4
+#define mc2_glb_acc_acc_nsr_DEFAULT                                0x00000001
+
+
+#define mc2_glb_acc_perm_sw_MASK                                   0x00000008
+#define mc2_glb_acc_perm_sw_ALIGN                                  0
+#define mc2_glb_acc_perm_sw_BITS                                   1
+#define mc2_glb_acc_perm_sw_SHIFT                                  3
+#define mc2_glb_acc_perm_sw_DEFAULT                                0x00000001
+
+
+#define mc2_glb_acc_perm_sr_MASK                                   0x00000004
+#define mc2_glb_acc_perm_sr_ALIGN                                  0
+#define mc2_glb_acc_perm_sr_BITS                                   1
+#define mc2_glb_acc_perm_sr_SHIFT                                  2
+#define mc2_glb_acc_perm_sr_DEFAULT                                0x00000001
+
+
+#define mc2_glb_acc_perm_nsw_MASK                                  0x00000002
+#define mc2_glb_acc_perm_nsw_ALIGN                                 0
+#define mc2_glb_acc_perm_nsw_BITS                                  1
+#define mc2_glb_acc_perm_nsw_SHIFT                                 1
+#define mc2_glb_acc_perm_nsw_DEFAULT                               0x00000001
+
+
+#define mc2_glb_acc_perm_nsr_MASK                                  0x00000001
+#define mc2_glb_acc_perm_nsr_ALIGN                                 0
+#define mc2_glb_acc_perm_nsr_BITS                                  1
+#define mc2_glb_acc_perm_nsr_SHIFT                                 0
+#define mc2_glb_acc_perm_nsr_DEFAULT                               0x00000001
+
+
+
+
+#define mc2_glb_vers_reserved0_MASK                                0xffff0000
+#define mc2_glb_vers_reserved0_ALIGN                               0
+#define mc2_glb_vers_reserved0_BITS                                16
+#define mc2_glb_vers_reserved0_SHIFT                               16
+
+
+#define mc2_glb_vers_VERSION_MAJOR_MASK                            0x0000ff00
+#define mc2_glb_vers_VERSION_MAJOR_ALIGN                           0
+#define mc2_glb_vers_VERSION_MAJOR_BITS                            8
+#define mc2_glb_vers_VERSION_MAJOR_SHIFT                           8
+#define mc2_glb_vers_VERSION_MAJOR_DEFAULT                         0x00000005
+
+
+#define mc2_glb_vers_VERSION_MINOR_MASK                            0x000000ff
+#define mc2_glb_vers_VERSION_MINOR_ALIGN                           0
+#define mc2_glb_vers_VERSION_MINOR_BITS                            8
+#define mc2_glb_vers_VERSION_MINOR_SHIFT                           0
+#define mc2_glb_vers_VERSION_MINOR_DEFAULT                         0x00000002
+
+
+
+
+#define mc2_glb_gcfg_dram_en_MASK                                  0x80000000
+#define mc2_glb_gcfg_dram_en_ALIGN                                 0
+#define mc2_glb_gcfg_dram_en_BITS                                  1
+#define mc2_glb_gcfg_dram_en_SHIFT                                 31
+#define mc2_glb_gcfg_dram_en_DEFAULT                               0x00000000
+
+
+#define mc2_glb_gcfg_reserved0_MASK                                0x78000000
+#define mc2_glb_gcfg_reserved0_ALIGN                               0
+#define mc2_glb_gcfg_reserved0_BITS                                4
+#define mc2_glb_gcfg_reserved0_SHIFT                               27
+
+
+#define mc2_glb_gcfg_sref_slow_clk_en_MASK                         0x04000000
+#define mc2_glb_gcfg_sref_slow_clk_en_ALIGN                        0
+#define mc2_glb_gcfg_sref_slow_clk_en_BITS                         1
+#define mc2_glb_gcfg_sref_slow_clk_en_SHIFT                        26
+#define mc2_glb_gcfg_sref_slow_clk_en_DEFAULT                      0x00000000
+
+
+#define mc2_glb_gcfg_phy_dfi_mode_MASK                             0x03000000
+#define mc2_glb_gcfg_phy_dfi_mode_ALIGN                            0
+#define mc2_glb_gcfg_phy_dfi_mode_BITS                             2
+#define mc2_glb_gcfg_phy_dfi_mode_SHIFT                            24
+#define mc2_glb_gcfg_phy_dfi_mode_DEFAULT                          0x00000001
+
+
+#define mc2_glb_gcfg_reserved1_MASK                                0x00f00000
+#define mc2_glb_gcfg_reserved1_ALIGN                               0
+#define mc2_glb_gcfg_reserved1_BITS                                4
+#define mc2_glb_gcfg_reserved1_SHIFT                               20
+
+
+#define mc2_glb_gcfg_dpfe_block_dmem_read_MASK                     0x00080000
+#define mc2_glb_gcfg_dpfe_block_dmem_read_ALIGN                    0
+#define mc2_glb_gcfg_dpfe_block_dmem_read_BITS                     1
+#define mc2_glb_gcfg_dpfe_block_dmem_read_SHIFT                    19
+#define mc2_glb_gcfg_dpfe_block_dmem_read_DEFAULT                  0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_block_dmem_write_MASK                    0x00040000
+#define mc2_glb_gcfg_dpfe_block_dmem_write_ALIGN                   0
+#define mc2_glb_gcfg_dpfe_block_dmem_write_BITS                    1
+#define mc2_glb_gcfg_dpfe_block_dmem_write_SHIFT                   18
+#define mc2_glb_gcfg_dpfe_block_dmem_write_DEFAULT                 0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_block_imem_read_MASK                     0x00020000
+#define mc2_glb_gcfg_dpfe_block_imem_read_ALIGN                    0
+#define mc2_glb_gcfg_dpfe_block_imem_read_BITS                     1
+#define mc2_glb_gcfg_dpfe_block_imem_read_SHIFT                    17
+#define mc2_glb_gcfg_dpfe_block_imem_read_DEFAULT                  0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_block_imem_write_MASK                    0x00010000
+#define mc2_glb_gcfg_dpfe_block_imem_write_ALIGN                   0
+#define mc2_glb_gcfg_dpfe_block_imem_write_BITS                    1
+#define mc2_glb_gcfg_dpfe_block_imem_write_SHIFT                   16
+#define mc2_glb_gcfg_dpfe_block_imem_write_DEFAULT                 0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_disable_cpu_MASK                         0x00008000
+#define mc2_glb_gcfg_dpfe_disable_cpu_ALIGN                        0
+#define mc2_glb_gcfg_dpfe_disable_cpu_BITS                         1
+#define mc2_glb_gcfg_dpfe_disable_cpu_SHIFT                        15
+#define mc2_glb_gcfg_dpfe_disable_cpu_DEFAULT                      0x00000000
+
+
+#define mc2_glb_gcfg_reserved2_MASK                                0x00004000
+#define mc2_glb_gcfg_reserved2_ALIGN                               0
+#define mc2_glb_gcfg_reserved2_BITS                                1
+#define mc2_glb_gcfg_reserved2_SHIFT                               14
+
+
+#define mc2_glb_gcfg_wr_data_mode_MASK                             0x00002000
+#define mc2_glb_gcfg_wr_data_mode_ALIGN                            0
+#define mc2_glb_gcfg_wr_data_mode_BITS                             1
+#define mc2_glb_gcfg_wr_data_mode_SHIFT                            13
+#define mc2_glb_gcfg_wr_data_mode_DEFAULT                          0x00000000
+
+
+#define mc2_glb_gcfg_exe_notify_mode_MASK                          0x00001000
+#define mc2_glb_gcfg_exe_notify_mode_ALIGN                         0
+#define mc2_glb_gcfg_exe_notify_mode_BITS                          1
+#define mc2_glb_gcfg_exe_notify_mode_SHIFT                         12
+#define mc2_glb_gcfg_exe_notify_mode_DEFAULT                       0x00000000
+
+
+#define mc2_glb_gcfg_shmoo_done_MASK                               0x00000800
+#define mc2_glb_gcfg_shmoo_done_ALIGN                              0
+#define mc2_glb_gcfg_shmoo_done_BITS                               1
+#define mc2_glb_gcfg_shmoo_done_SHIFT                              11
+#define mc2_glb_gcfg_shmoo_done_DEFAULT                            0x00000000
+
+
+#define mc2_glb_gcfg_dfi_en_MASK                                   0x00000400
+#define mc2_glb_gcfg_dfi_en_ALIGN                                  0
+#define mc2_glb_gcfg_dfi_en_BITS                                   1
+#define mc2_glb_gcfg_dfi_en_SHIFT                                  10
+#define mc2_glb_gcfg_dfi_en_DEFAULT                                0x00000000
+
+
+#define mc2_glb_gcfg_mclksrc_MASK                                  0x00000200
+#define mc2_glb_gcfg_mclksrc_ALIGN                                 0
+#define mc2_glb_gcfg_mclksrc_BITS                                  1
+#define mc2_glb_gcfg_mclksrc_SHIFT                                 9
+#define mc2_glb_gcfg_mclksrc_DEFAULT                               0x00000000
+
+
+#define mc2_glb_gcfg_meminitdone_MASK                              0x00000100
+#define mc2_glb_gcfg_meminitdone_ALIGN                             0
+#define mc2_glb_gcfg_meminitdone_BITS                              1
+#define mc2_glb_gcfg_meminitdone_SHIFT                             8
+#define mc2_glb_gcfg_meminitdone_DEFAULT                           0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_uart_tx_share_en_MASK                    0x00000080
+#define mc2_glb_gcfg_dpfe_uart_tx_share_en_ALIGN                   0
+#define mc2_glb_gcfg_dpfe_uart_tx_share_en_BITS                    1
+#define mc2_glb_gcfg_dpfe_uart_tx_share_en_SHIFT                   7
+#define mc2_glb_gcfg_dpfe_uart_tx_share_en_DEFAULT                 0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_uart_tx_en_MASK                          0x00000040
+#define mc2_glb_gcfg_dpfe_uart_tx_en_ALIGN                         0
+#define mc2_glb_gcfg_dpfe_uart_tx_en_BITS                          1
+#define mc2_glb_gcfg_dpfe_uart_tx_en_SHIFT                         6
+#define mc2_glb_gcfg_dpfe_uart_tx_en_DEFAULT                       0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_uart_rx_mode_MASK                        0x00000030
+#define mc2_glb_gcfg_dpfe_uart_rx_mode_ALIGN                       0
+#define mc2_glb_gcfg_dpfe_uart_rx_mode_BITS                        2
+#define mc2_glb_gcfg_dpfe_uart_rx_mode_SHIFT                       4
+#define mc2_glb_gcfg_dpfe_uart_rx_mode_DEFAULT                     0x00000000
+
+
+#define mc2_glb_gcfg_sec_intr_mask_lock_MASK                       0x00000008
+#define mc2_glb_gcfg_sec_intr_mask_lock_ALIGN                      0
+#define mc2_glb_gcfg_sec_intr_mask_lock_BITS                       1
+#define mc2_glb_gcfg_sec_intr_mask_lock_SHIFT                      3
+#define mc2_glb_gcfg_sec_intr_mask_lock_DEFAULT                    0x00000000
+
+
+#define mc2_glb_gcfg_reserved3_MASK                                0x00000006
+#define mc2_glb_gcfg_reserved3_ALIGN                               0
+#define mc2_glb_gcfg_reserved3_BITS                                2
+#define mc2_glb_gcfg_reserved3_SHIFT                               1
+
+
+#define mc2_glb_gcfg_dpath_mode_MASK                               0x00000001
+#define mc2_glb_gcfg_dpath_mode_ALIGN                              0
+#define mc2_glb_gcfg_dpath_mode_BITS                               1
+#define mc2_glb_gcfg_dpath_mode_SHIFT                              0
+#define mc2_glb_gcfg_dpath_mode_DEFAULT                            0x00000000
+
+
+
+
+#define mc2_glb_auto_self_refresh_enable_MASK                      0x80000000
+#define mc2_glb_auto_self_refresh_enable_ALIGN                     0
+#define mc2_glb_auto_self_refresh_enable_BITS                      1
+#define mc2_glb_auto_self_refresh_enable_SHIFT                     31
+#define mc2_glb_auto_self_refresh_enable_DEFAULT                   0x00000000
+
+
+#define mc2_glb_auto_self_refresh_immediate_MASK                   0x40000000
+#define mc2_glb_auto_self_refresh_immediate_ALIGN                  0
+#define mc2_glb_auto_self_refresh_immediate_BITS                   1
+#define mc2_glb_auto_self_refresh_immediate_SHIFT                  30
+#define mc2_glb_auto_self_refresh_immediate_DEFAULT                0x00000000
+
+
+#define mc2_glb_auto_self_refresh_idle_count_MASK                  0x3fffffff
+#define mc2_glb_auto_self_refresh_idle_count_ALIGN                 0
+#define mc2_glb_auto_self_refresh_idle_count_BITS                  30
+#define mc2_glb_auto_self_refresh_idle_count_SHIFT                 0
+#define mc2_glb_auto_self_refresh_idle_count_DEFAULT               0x00000000
+
+
+
+
+#define mc2_glb_pwr_mgr_reserved0_MASK                             0xffff0000
+#define mc2_glb_pwr_mgr_reserved0_ALIGN                            0
+#define mc2_glb_pwr_mgr_reserved0_BITS                             16
+#define mc2_glb_pwr_mgr_reserved0_SHIFT                            16
+
+
+#define mc2_glb_pwr_mgr_idle_mask_MASK                             0x0000ffff
+#define mc2_glb_pwr_mgr_idle_mask_ALIGN                            0
+#define mc2_glb_pwr_mgr_idle_mask_BITS                             16
+#define mc2_glb_pwr_mgr_idle_mask_SHIFT                            0
+#define mc2_glb_pwr_mgr_idle_mask_DEFAULT                          0x00000000
+
+
+
+
+#define mc2_axi_acc_acc_eack_MASK                                  0x80000000
+#define mc2_axi_acc_acc_eack_ALIGN                                 0
+#define mc2_axi_acc_acc_eack_BITS                                  1
+#define mc2_axi_acc_acc_eack_SHIFT                                 31
+#define mc2_axi_acc_acc_eack_DEFAULT                               0x00000000
+
+
+#define mc2_axi_acc_reserved0_MASK                                 0x7fffff00
+#define mc2_axi_acc_reserved0_ALIGN                                0
+#define mc2_axi_acc_reserved0_BITS                                 23
+#define mc2_axi_acc_reserved0_SHIFT                                8
+
+
+#define mc2_axi_acc_acc_sw_MASK                                    0x00000080
+#define mc2_axi_acc_acc_sw_ALIGN                                   0
+#define mc2_axi_acc_acc_sw_BITS                                    1
+#define mc2_axi_acc_acc_sw_SHIFT                                   7
+#define mc2_axi_acc_acc_sw_DEFAULT                                 0x00000001
+
+
+#define mc2_axi_acc_acc_sr_MASK                                    0x00000040
+#define mc2_axi_acc_acc_sr_ALIGN                                   0
+#define mc2_axi_acc_acc_sr_BITS                                    1
+#define mc2_axi_acc_acc_sr_SHIFT                                   6
+#define mc2_axi_acc_acc_sr_DEFAULT                                 0x00000001
+
+
+#define mc2_axi_acc_acc_nsw_MASK                                   0x00000020
+#define mc2_axi_acc_acc_nsw_ALIGN                                  0
+#define mc2_axi_acc_acc_nsw_BITS                                   1
+#define mc2_axi_acc_acc_nsw_SHIFT                                  5
+#define mc2_axi_acc_acc_nsw_DEFAULT                                0x00000001
+
+
+#define mc2_axi_acc_acc_nsr_MASK                                   0x00000010
+#define mc2_axi_acc_acc_nsr_ALIGN                                  0
+#define mc2_axi_acc_acc_nsr_BITS                                   1
+#define mc2_axi_acc_acc_nsr_SHIFT                                  4
+#define mc2_axi_acc_acc_nsr_DEFAULT                                0x00000001
+
+
+#define mc2_axi_acc_perm_sw_MASK                                   0x00000008
+#define mc2_axi_acc_perm_sw_ALIGN                                  0
+#define mc2_axi_acc_perm_sw_BITS                                   1
+#define mc2_axi_acc_perm_sw_SHIFT                                  3
+#define mc2_axi_acc_perm_sw_DEFAULT                                0x00000001
+
+
+#define mc2_axi_acc_perm_sr_MASK                                   0x00000004
+#define mc2_axi_acc_perm_sr_ALIGN                                  0
+#define mc2_axi_acc_perm_sr_BITS                                   1
+#define mc2_axi_acc_perm_sr_SHIFT                                  2
+#define mc2_axi_acc_perm_sr_DEFAULT                                0x00000001
+
+
+#define mc2_axi_acc_perm_nsw_MASK                                  0x00000002
+#define mc2_axi_acc_perm_nsw_ALIGN                                 0
+#define mc2_axi_acc_perm_nsw_BITS                                  1
+#define mc2_axi_acc_perm_nsw_SHIFT                                 1
+#define mc2_axi_acc_perm_nsw_DEFAULT                               0x00000001
+
+
+#define mc2_axi_acc_perm_nsr_MASK                                  0x00000001
+#define mc2_axi_acc_perm_nsr_ALIGN                                 0
+#define mc2_axi_acc_perm_nsr_BITS                                  1
+#define mc2_axi_acc_perm_nsr_SHIFT                                 0
+#define mc2_axi_acc_perm_nsr_DEFAULT                               0x00000001
+
+
+
+
+#define mc2_axi_ver_reserved0_MASK                                 0xffffff00
+#define mc2_axi_ver_reserved0_ALIGN                                0
+#define mc2_axi_ver_reserved0_BITS                                 24
+#define mc2_axi_ver_reserved0_SHIFT                                8
+
+
+#define mc2_axi_ver_version_MASK                                   0x000000ff
+#define mc2_axi_ver_version_ALIGN                                  0
+#define mc2_axi_ver_version_BITS                                   8
+#define mc2_axi_ver_version_SHIFT                                  0
+#define mc2_axi_ver_version_DEFAULT                                0x00000000
+
+
+
+
+#define mc2_axi_CFG_reserved0_MASK                                 0xe0000000
+#define mc2_axi_CFG_reserved0_ALIGN                                0
+#define mc2_axi_CFG_reserved0_BITS                                 3
+#define mc2_axi_CFG_reserved0_SHIFT                                29
+
+
+#define mc2_axi_CFG_CPQ_WRITE_IN_TRANSIT_MASK                      0x1f800000
+#define mc2_axi_CFG_CPQ_WRITE_IN_TRANSIT_ALIGN                     0
+#define mc2_axi_CFG_CPQ_WRITE_IN_TRANSIT_BITS                      6
+#define mc2_axi_CFG_CPQ_WRITE_IN_TRANSIT_SHIFT                     23
+#define mc2_axi_CFG_CPQ_WRITE_IN_TRANSIT_DEFAULT                   0x00000008
+
+
+#define mc2_axi_CFG_CPU_WRITE_IN_TRANSIT_MASK                      0x007e0000
+#define mc2_axi_CFG_CPU_WRITE_IN_TRANSIT_ALIGN                     0
+#define mc2_axi_CFG_CPU_WRITE_IN_TRANSIT_BITS                      6
+#define mc2_axi_CFG_CPU_WRITE_IN_TRANSIT_SHIFT                     17
+#define mc2_axi_CFG_CPU_WRITE_IN_TRANSIT_DEFAULT                   0x00000008
+
+
+#define mc2_axi_CFG_WRITE_ACK_MODE_MASK                            0x00010000
+#define mc2_axi_CFG_WRITE_ACK_MODE_ALIGN                           0
+#define mc2_axi_CFG_WRITE_ACK_MODE_BITS                            1
+#define mc2_axi_CFG_WRITE_ACK_MODE_SHIFT                           16
+#define mc2_axi_CFG_WRITE_ACK_MODE_DEFAULT                         0x00000000
+
+
+#define mc2_axi_CFG_reserved1_MASK                                 0x0000f000
+#define mc2_axi_CFG_reserved1_ALIGN                                0
+#define mc2_axi_CFG_reserved1_BITS                                 4
+#define mc2_axi_CFG_reserved1_SHIFT                                12
+
+
+#define mc2_axi_CFG_MC_CAP_MUX_SEL_MASK                            0x00000f00
+#define mc2_axi_CFG_MC_CAP_MUX_SEL_ALIGN                           0
+#define mc2_axi_CFG_MC_CAP_MUX_SEL_BITS                            4
+#define mc2_axi_CFG_MC_CAP_MUX_SEL_SHIFT                           8
+#define mc2_axi_CFG_MC_CAP_MUX_SEL_DEFAULT                         0x00000000
+
+
+#define mc2_axi_CFG_MC_CAP_MUX_VLD_SEL_MASK                        0x000000c0
+#define mc2_axi_CFG_MC_CAP_MUX_VLD_SEL_ALIGN                       0
+#define mc2_axi_CFG_MC_CAP_MUX_VLD_SEL_BITS                        2
+#define mc2_axi_CFG_MC_CAP_MUX_VLD_SEL_SHIFT                       6
+#define mc2_axi_CFG_MC_CAP_MUX_VLD_SEL_DEFAULT                     0x00000000
+
+
+#define mc2_axi_CFG_MC_CAP_MUX_TRIG_SEL_MASK                       0x00000030
+#define mc2_axi_CFG_MC_CAP_MUX_TRIG_SEL_ALIGN                      0
+#define mc2_axi_CFG_MC_CAP_MUX_TRIG_SEL_BITS                       2
+#define mc2_axi_CFG_MC_CAP_MUX_TRIG_SEL_SHIFT                      4
+#define mc2_axi_CFG_MC_CAP_MUX_TRIG_SEL_DEFAULT                    0x00000000
+
+
+#define mc2_axi_CFG_RPT_NON_SECURE_ERR_MASK                        0x00000008
+#define mc2_axi_CFG_RPT_NON_SECURE_ERR_ALIGN                       0
+#define mc2_axi_CFG_RPT_NON_SECURE_ERR_BITS                        1
+#define mc2_axi_CFG_RPT_NON_SECURE_ERR_SHIFT                       3
+#define mc2_axi_CFG_RPT_NON_SECURE_ERR_DEFAULT                     0x00000000
+
+
+#define mc2_axi_CFG_RPT_SECURE_ERR_MASK                            0x00000004
+#define mc2_axi_CFG_RPT_SECURE_ERR_ALIGN                           0
+#define mc2_axi_CFG_RPT_SECURE_ERR_BITS                            1
+#define mc2_axi_CFG_RPT_SECURE_ERR_SHIFT                           2
+#define mc2_axi_CFG_RPT_SECURE_ERR_DEFAULT                         0x00000000
+
+
+#define mc2_axi_CFG_CMD_WAIT_WDATA_MASK                            0x00000002
+#define mc2_axi_CFG_CMD_WAIT_WDATA_ALIGN                           0
+#define mc2_axi_CFG_CMD_WAIT_WDATA_BITS                            1
+#define mc2_axi_CFG_CMD_WAIT_WDATA_SHIFT                           1
+#define mc2_axi_CFG_CMD_WAIT_WDATA_DEFAULT                         0x00000001
+
+
+#define mc2_axi_CFG_DIS_RBUS_MSTR_MASK                             0x00000001
+#define mc2_axi_CFG_DIS_RBUS_MSTR_ALIGN                            0
+#define mc2_axi_CFG_DIS_RBUS_MSTR_BITS                             1
+#define mc2_axi_CFG_DIS_RBUS_MSTR_SHIFT                            0
+#define mc2_axi_CFG_DIS_RBUS_MSTR_DEFAULT                          0x00000000
+
+
+
+
+#define mc2_axi_REP_ARB_MODE_reserved0_MASK                        0xfffff000
+#define mc2_axi_REP_ARB_MODE_reserved0_ALIGN                       0
+#define mc2_axi_REP_ARB_MODE_reserved0_BITS                        20
+#define mc2_axi_REP_ARB_MODE_reserved0_SHIFT                       12
+
+
+#define mc2_axi_REP_ARB_MODE_RD_BUFFER_SIZE_MASK                   0x00000800
+#define mc2_axi_REP_ARB_MODE_RD_BUFFER_SIZE_ALIGN                  0
+#define mc2_axi_REP_ARB_MODE_RD_BUFFER_SIZE_BITS                   1
+#define mc2_axi_REP_ARB_MODE_RD_BUFFER_SIZE_SHIFT                  11
+#define mc2_axi_REP_ARB_MODE_RD_BUFFER_SIZE_DEFAULT                0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_LEN_MASK               0x00000780
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_LEN_ALIGN              0
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_LEN_BITS               4
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_LEN_SHIFT              7
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_LEN_DEFAULT            0x00000007
+
+
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_EN_MASK                0x00000040
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_EN_ALIGN               0
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_EN_BITS                1
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_EN_SHIFT               6
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_EN_DEFAULT             0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_DIS_RRESP_ERR_MODE_MASK               0x00000020
+#define mc2_axi_REP_ARB_MODE_DIS_RRESP_ERR_MODE_ALIGN              0
+#define mc2_axi_REP_ARB_MODE_DIS_RRESP_ERR_MODE_BITS               1
+#define mc2_axi_REP_ARB_MODE_DIS_RRESP_ERR_MODE_SHIFT              5
+#define mc2_axi_REP_ARB_MODE_DIS_RRESP_ERR_MODE_DEFAULT            0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_RD_FIFO_MODE_MASK                     0x00000010
+#define mc2_axi_REP_ARB_MODE_RD_FIFO_MODE_ALIGN                    0
+#define mc2_axi_REP_ARB_MODE_RD_FIFO_MODE_BITS                     1
+#define mc2_axi_REP_ARB_MODE_RD_FIFO_MODE_SHIFT                    4
+#define mc2_axi_REP_ARB_MODE_RD_FIFO_MODE_DEFAULT                  0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_RD_PACKET_MODE_MASK                   0x00000008
+#define mc2_axi_REP_ARB_MODE_RD_PACKET_MODE_ALIGN                  0
+#define mc2_axi_REP_ARB_MODE_RD_PACKET_MODE_BITS                   1
+#define mc2_axi_REP_ARB_MODE_RD_PACKET_MODE_SHIFT                  3
+#define mc2_axi_REP_ARB_MODE_RD_PACKET_MODE_DEFAULT                0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_DIS_BRESP_ERR_MODE_MASK               0x00000004
+#define mc2_axi_REP_ARB_MODE_DIS_BRESP_ERR_MODE_ALIGN              0
+#define mc2_axi_REP_ARB_MODE_DIS_BRESP_ERR_MODE_BITS               1
+#define mc2_axi_REP_ARB_MODE_DIS_BRESP_ERR_MODE_SHIFT              2
+#define mc2_axi_REP_ARB_MODE_DIS_BRESP_ERR_MODE_DEFAULT            0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_WR_FIFO_MODE_MASK                     0x00000002
+#define mc2_axi_REP_ARB_MODE_WR_FIFO_MODE_ALIGN                    0
+#define mc2_axi_REP_ARB_MODE_WR_FIFO_MODE_BITS                     1
+#define mc2_axi_REP_ARB_MODE_WR_FIFO_MODE_SHIFT                    1
+#define mc2_axi_REP_ARB_MODE_WR_FIFO_MODE_DEFAULT                  0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_WR_REPLY_MODE_MASK                    0x00000001
+#define mc2_axi_REP_ARB_MODE_WR_REPLY_MODE_ALIGN                   0
+#define mc2_axi_REP_ARB_MODE_WR_REPLY_MODE_BITS                    1
+#define mc2_axi_REP_ARB_MODE_WR_REPLY_MODE_SHIFT                   0
+#define mc2_axi_REP_ARB_MODE_WR_REPLY_MODE_DEFAULT                 0x00000000
+
+
+
+
+#define mc2_axi_queue_cfg_reserved0_MASK                           0xfffffc00
+#define mc2_axi_queue_cfg_reserved0_ALIGN                          0
+#define mc2_axi_queue_cfg_reserved0_BITS                           22
+#define mc2_axi_queue_cfg_reserved0_SHIFT                          10
+
+
+#define mc2_axi_queue_cfg_disable_backpressure_MASK                0x00000200
+#define mc2_axi_queue_cfg_disable_backpressure_ALIGN               0
+#define mc2_axi_queue_cfg_disable_backpressure_BITS                1
+#define mc2_axi_queue_cfg_disable_backpressure_SHIFT               9
+#define mc2_axi_queue_cfg_disable_backpressure_DEFAULT             0x00000000
+
+
+#define mc2_axi_queue_cfg_overflow_drop_MASK                       0x00000100
+#define mc2_axi_queue_cfg_overflow_drop_ALIGN                      0
+#define mc2_axi_queue_cfg_overflow_drop_BITS                       1
+#define mc2_axi_queue_cfg_overflow_drop_SHIFT                      8
+#define mc2_axi_queue_cfg_overflow_drop_DEFAULT                    0x00000000
+
+
+#define mc2_axi_queue_cfg_reserved1_MASK                           0x000000f0
+#define mc2_axi_queue_cfg_reserved1_ALIGN                          0
+#define mc2_axi_queue_cfg_reserved1_BITS                           4
+#define mc2_axi_queue_cfg_reserved1_SHIFT                          4
+
+
+#define mc2_axi_queue_cfg_queue_start_MASK                         0x0000000f
+#define mc2_axi_queue_cfg_queue_start_ALIGN                        0
+#define mc2_axi_queue_cfg_queue_start_BITS                         4
+#define mc2_axi_queue_cfg_queue_start_SHIFT                        0
+#define mc2_axi_queue_cfg_queue_start_DEFAULT                      0x00000000
+
+
+
+
+#define mc2_axi_queue_size0_reserved0_MASK                         0x80000000
+#define mc2_axi_queue_size0_reserved0_ALIGN                        0
+#define mc2_axi_queue_size0_reserved0_BITS                         1
+#define mc2_axi_queue_size0_reserved0_SHIFT                        31
+
+
+#define mc2_axi_queue_size0_size3_MASK                             0x7f000000
+#define mc2_axi_queue_size0_size3_ALIGN                            0
+#define mc2_axi_queue_size0_size3_BITS                             7
+#define mc2_axi_queue_size0_size3_SHIFT                            24
+#define mc2_axi_queue_size0_size3_DEFAULT                          0x00000008
+
+
+#define mc2_axi_queue_size0_reserved1_MASK                         0x00800000
+#define mc2_axi_queue_size0_reserved1_ALIGN                        0
+#define mc2_axi_queue_size0_reserved1_BITS                         1
+#define mc2_axi_queue_size0_reserved1_SHIFT                        23
+
+
+#define mc2_axi_queue_size0_size2_MASK                             0x007f0000
+#define mc2_axi_queue_size0_size2_ALIGN                            0
+#define mc2_axi_queue_size0_size2_BITS                             7
+#define mc2_axi_queue_size0_size2_SHIFT                            16
+#define mc2_axi_queue_size0_size2_DEFAULT                          0x00000008
+
+
+#define mc2_axi_queue_size0_reserved2_MASK                         0x00008000
+#define mc2_axi_queue_size0_reserved2_ALIGN                        0
+#define mc2_axi_queue_size0_reserved2_BITS                         1
+#define mc2_axi_queue_size0_reserved2_SHIFT                        15
+
+
+#define mc2_axi_queue_size0_size1_MASK                             0x00007f00
+#define mc2_axi_queue_size0_size1_ALIGN                            0
+#define mc2_axi_queue_size0_size1_BITS                             7
+#define mc2_axi_queue_size0_size1_SHIFT                            8
+#define mc2_axi_queue_size0_size1_DEFAULT                          0x00000008
+
+
+#define mc2_axi_queue_size0_reserved3_MASK                         0x00000080
+#define mc2_axi_queue_size0_reserved3_ALIGN                        0
+#define mc2_axi_queue_size0_reserved3_BITS                         1
+#define mc2_axi_queue_size0_reserved3_SHIFT                        7
+
+
+#define mc2_axi_queue_size0_size0_MASK                             0x0000007f
+#define mc2_axi_queue_size0_size0_ALIGN                            0
+#define mc2_axi_queue_size0_size0_BITS                             7
+#define mc2_axi_queue_size0_size0_SHIFT                            0
+#define mc2_axi_queue_size0_size0_DEFAULT                          0x00000008
+
+
+
+
+#define mc2_axi_queue_map0_reserved0_MASK                          0xffffff00
+#define mc2_axi_queue_map0_reserved0_ALIGN                         0
+#define mc2_axi_queue_map0_reserved0_BITS                          24
+#define mc2_axi_queue_map0_reserved0_SHIFT                         8
+
+
+#define mc2_axi_queue_map0_cpq_rd_MASK                             0x000000c0
+#define mc2_axi_queue_map0_cpq_rd_ALIGN                            0
+#define mc2_axi_queue_map0_cpq_rd_BITS                             2
+#define mc2_axi_queue_map0_cpq_rd_SHIFT                            6
+#define mc2_axi_queue_map0_cpq_rd_DEFAULT                          0x00000003
+
+
+#define mc2_axi_queue_map0_cpq_wr_MASK                             0x00000030
+#define mc2_axi_queue_map0_cpq_wr_ALIGN                            0
+#define mc2_axi_queue_map0_cpq_wr_BITS                             2
+#define mc2_axi_queue_map0_cpq_wr_SHIFT                            4
+#define mc2_axi_queue_map0_cpq_wr_DEFAULT                          0x00000002
+
+
+#define mc2_axi_queue_map0_cpu_rd_MASK                             0x0000000c
+#define mc2_axi_queue_map0_cpu_rd_ALIGN                            0
+#define mc2_axi_queue_map0_cpu_rd_BITS                             2
+#define mc2_axi_queue_map0_cpu_rd_SHIFT                            2
+#define mc2_axi_queue_map0_cpu_rd_DEFAULT                          0x00000001
+
+
+#define mc2_axi_queue_map0_cpu_wr_MASK                             0x00000003
+#define mc2_axi_queue_map0_cpu_wr_ALIGN                            0
+#define mc2_axi_queue_map0_cpu_wr_BITS                             2
+#define mc2_axi_queue_map0_cpu_wr_SHIFT                            0
+#define mc2_axi_queue_map0_cpu_wr_DEFAULT                          0x00000000
+
+
+#define mc2_axi_SCRATCH_scratch_MASK                               0xffffffff
+#define mc2_axi_SCRATCH_scratch_ALIGN                              0
+#define mc2_axi_SCRATCH_scratch_BITS                               32
+#define mc2_axi_SCRATCH_scratch_SHIFT                              0
+#define mc2_axi_SCRATCH_scratch_DEFAULT                            0x00000000
+
+
+#define mc2_chn_ddr_acc_acc_eack_MASK                              0x80000000
+#define mc2_chn_ddr_acc_acc_eack_ALIGN                             0
+#define mc2_chn_ddr_acc_acc_eack_BITS                              1
+#define mc2_chn_ddr_acc_acc_eack_SHIFT                             31
+#define mc2_chn_ddr_acc_acc_eack_DEFAULT                           0x00000000
+
+
+#define mc2_chn_ddr_acc_reserved0_MASK                             0x7fffff00
+#define mc2_chn_ddr_acc_reserved0_ALIGN                            0
+#define mc2_chn_ddr_acc_reserved0_BITS                             23
+#define mc2_chn_ddr_acc_reserved0_SHIFT                            8
+
+
+#define mc2_chn_ddr_acc_acc_sw_MASK                                0x00000080
+#define mc2_chn_ddr_acc_acc_sw_ALIGN                               0
+#define mc2_chn_ddr_acc_acc_sw_BITS                                1
+#define mc2_chn_ddr_acc_acc_sw_SHIFT                               7
+#define mc2_chn_ddr_acc_acc_sw_DEFAULT                             0x00000001
+
+
+#define mc2_chn_ddr_acc_acc_sr_MASK                                0x00000040
+#define mc2_chn_ddr_acc_acc_sr_ALIGN                               0
+#define mc2_chn_ddr_acc_acc_sr_BITS                                1
+#define mc2_chn_ddr_acc_acc_sr_SHIFT                               6
+#define mc2_chn_ddr_acc_acc_sr_DEFAULT                             0x00000001
+
+
+#define mc2_chn_ddr_acc_acc_nsw_MASK                               0x00000020
+#define mc2_chn_ddr_acc_acc_nsw_ALIGN                              0
+#define mc2_chn_ddr_acc_acc_nsw_BITS                               1
+#define mc2_chn_ddr_acc_acc_nsw_SHIFT                              5
+#define mc2_chn_ddr_acc_acc_nsw_DEFAULT                            0x00000001
+
+
+#define mc2_chn_ddr_acc_acc_nsr_MASK                               0x00000010
+#define mc2_chn_ddr_acc_acc_nsr_ALIGN                              0
+#define mc2_chn_ddr_acc_acc_nsr_BITS                               1
+#define mc2_chn_ddr_acc_acc_nsr_SHIFT                              4
+#define mc2_chn_ddr_acc_acc_nsr_DEFAULT                            0x00000001
+
+
+#define mc2_chn_ddr_acc_perm_sw_MASK                               0x00000008
+#define mc2_chn_ddr_acc_perm_sw_ALIGN                              0
+#define mc2_chn_ddr_acc_perm_sw_BITS                               1
+#define mc2_chn_ddr_acc_perm_sw_SHIFT                              3
+#define mc2_chn_ddr_acc_perm_sw_DEFAULT                            0x00000001
+
+
+#define mc2_chn_ddr_acc_perm_sr_MASK                               0x00000004
+#define mc2_chn_ddr_acc_perm_sr_ALIGN                              0
+#define mc2_chn_ddr_acc_perm_sr_BITS                               1
+#define mc2_chn_ddr_acc_perm_sr_SHIFT                              2
+#define mc2_chn_ddr_acc_perm_sr_DEFAULT                            0x00000001
+
+
+#define mc2_chn_ddr_acc_perm_nsw_MASK                              0x00000002
+#define mc2_chn_ddr_acc_perm_nsw_ALIGN                             0
+#define mc2_chn_ddr_acc_perm_nsw_BITS                              1
+#define mc2_chn_ddr_acc_perm_nsw_SHIFT                             1
+#define mc2_chn_ddr_acc_perm_nsw_DEFAULT                           0x00000001
+
+
+#define mc2_chn_ddr_acc_perm_nsr_MASK                              0x00000001
+#define mc2_chn_ddr_acc_perm_nsr_ALIGN                             0
+#define mc2_chn_ddr_acc_perm_nsr_BITS                              1
+#define mc2_chn_ddr_acc_perm_nsr_SHIFT                             0
+#define mc2_chn_ddr_acc_perm_nsr_DEFAULT                           0x00000001
+
+
+
+
+#define mc2_chn_ddr_ver_reserved0_MASK                             0xffffff00
+#define mc2_chn_ddr_ver_reserved0_ALIGN                            0
+#define mc2_chn_ddr_ver_reserved0_BITS                             24
+#define mc2_chn_ddr_ver_reserved0_SHIFT                            8
+
+
+#define mc2_chn_ddr_ver_version_MASK                               0x000000ff
+#define mc2_chn_ddr_ver_version_ALIGN                              0
+#define mc2_chn_ddr_ver_version_BITS                               8
+#define mc2_chn_ddr_ver_version_SHIFT                              0
+#define mc2_chn_ddr_ver_version_DEFAULT                            0x00000000
+
+
+
+
+#define mc2_chn_ddr_chn_arb_cfg_fifo_mode_MASK                     0x80000000
+#define mc2_chn_ddr_chn_arb_cfg_fifo_mode_ALIGN                    0
+#define mc2_chn_ddr_chn_arb_cfg_fifo_mode_BITS                     1
+#define mc2_chn_ddr_chn_arb_cfg_fifo_mode_SHIFT                    31
+#define mc2_chn_ddr_chn_arb_cfg_fifo_mode_DEFAULT                  0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_addr_chk_disable_MASK              0x40000000
+#define mc2_chn_ddr_chn_arb_cfg_addr_chk_disable_ALIGN             0
+#define mc2_chn_ddr_chn_arb_cfg_addr_chk_disable_BITS              1
+#define mc2_chn_ddr_chn_arb_cfg_addr_chk_disable_SHIFT             30
+#define mc2_chn_ddr_chn_arb_cfg_addr_chk_disable_DEFAULT           0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_reserved0_MASK                     0x3c000000
+#define mc2_chn_ddr_chn_arb_cfg_reserved0_ALIGN                    0
+#define mc2_chn_ddr_chn_arb_cfg_reserved0_BITS                     4
+#define mc2_chn_ddr_chn_arb_cfg_reserved0_SHIFT                    26
+
+
+#define mc2_chn_ddr_chn_arb_cfg_always_auto_precharge_MASK         0x02000000
+#define mc2_chn_ddr_chn_arb_cfg_always_auto_precharge_ALIGN        0
+#define mc2_chn_ddr_chn_arb_cfg_always_auto_precharge_BITS         1
+#define mc2_chn_ddr_chn_arb_cfg_always_auto_precharge_SHIFT        25
+#define mc2_chn_ddr_chn_arb_cfg_always_auto_precharge_DEFAULT      0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_auto_precharge_MASK                0x01000000
+#define mc2_chn_ddr_chn_arb_cfg_auto_precharge_ALIGN               0
+#define mc2_chn_ddr_chn_arb_cfg_auto_precharge_BITS                1
+#define mc2_chn_ddr_chn_arb_cfg_auto_precharge_SHIFT               24
+#define mc2_chn_ddr_chn_arb_cfg_auto_precharge_DEFAULT             0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_reserved1_MASK                     0x00ffffe0
+#define mc2_chn_ddr_chn_arb_cfg_reserved1_ALIGN                    0
+#define mc2_chn_ddr_chn_arb_cfg_reserved1_BITS                     19
+#define mc2_chn_ddr_chn_arb_cfg_reserved1_SHIFT                    5
+
+
+#define mc2_chn_ddr_chn_arb_cfg_extra_slot_en_MASK                 0x00000010
+#define mc2_chn_ddr_chn_arb_cfg_extra_slot_en_ALIGN                0
+#define mc2_chn_ddr_chn_arb_cfg_extra_slot_en_BITS                 1
+#define mc2_chn_ddr_chn_arb_cfg_extra_slot_en_SHIFT                4
+#define mc2_chn_ddr_chn_arb_cfg_extra_slot_en_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpq_MASK               0x00000008
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpq_ALIGN              0
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpq_BITS               1
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpq_SHIFT              3
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpq_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpu_MASK               0x00000004
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpu_ALIGN              0
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpu_BITS               1
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpu_SHIFT              2
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpu_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_pri_elevate_dis_MASK               0x00000002
+#define mc2_chn_ddr_chn_arb_cfg_pri_elevate_dis_ALIGN              0
+#define mc2_chn_ddr_chn_arb_cfg_pri_elevate_dis_BITS               1
+#define mc2_chn_ddr_chn_arb_cfg_pri_elevate_dis_SHIFT              1
+#define mc2_chn_ddr_chn_arb_cfg_pri_elevate_dis_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_arb_mode_MASK                      0x00000001
+#define mc2_chn_ddr_chn_arb_cfg_arb_mode_ALIGN                     0
+#define mc2_chn_ddr_chn_arb_cfg_arb_mode_BITS                      1
+#define mc2_chn_ddr_chn_arb_cfg_arb_mode_SHIFT                     0
+#define mc2_chn_ddr_chn_arb_cfg_arb_mode_DEFAULT                   0x00000000
+
+
+
+
+#define mc2_chn_ddr_chn_arb_param_reserved0_MASK                   0x80000000
+#define mc2_chn_ddr_chn_arb_param_reserved0_ALIGN                  0
+#define mc2_chn_ddr_chn_arb_param_reserved0_BITS                   1
+#define mc2_chn_ddr_chn_arb_param_reserved0_SHIFT                  31
+
+
+#define mc2_chn_ddr_chn_arb_param_vq2_timeout_MASK                 0x7f000000
+#define mc2_chn_ddr_chn_arb_param_vq2_timeout_ALIGN                0
+#define mc2_chn_ddr_chn_arb_param_vq2_timeout_BITS                 7
+#define mc2_chn_ddr_chn_arb_param_vq2_timeout_SHIFT                24
+#define mc2_chn_ddr_chn_arb_param_vq2_timeout_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_param_reserved1_MASK                   0x00800000
+#define mc2_chn_ddr_chn_arb_param_reserved1_ALIGN                  0
+#define mc2_chn_ddr_chn_arb_param_reserved1_BITS                   1
+#define mc2_chn_ddr_chn_arb_param_reserved1_SHIFT                  23
+
+
+#define mc2_chn_ddr_chn_arb_param_vq0_timeout_MASK                 0x007f0000
+#define mc2_chn_ddr_chn_arb_param_vq0_timeout_ALIGN                0
+#define mc2_chn_ddr_chn_arb_param_vq0_timeout_BITS                 7
+#define mc2_chn_ddr_chn_arb_param_vq0_timeout_SHIFT                16
+#define mc2_chn_ddr_chn_arb_param_vq0_timeout_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_param_reserved2_MASK                   0x0000c000
+#define mc2_chn_ddr_chn_arb_param_reserved2_ALIGN                  0
+#define mc2_chn_ddr_chn_arb_param_reserved2_BITS                   2
+#define mc2_chn_ddr_chn_arb_param_reserved2_SHIFT                  14
+
+
+#define mc2_chn_ddr_chn_arb_param_wrr6_weight_MASK                 0x00003000
+#define mc2_chn_ddr_chn_arb_param_wrr6_weight_ALIGN                0
+#define mc2_chn_ddr_chn_arb_param_wrr6_weight_BITS                 2
+#define mc2_chn_ddr_chn_arb_param_wrr6_weight_SHIFT                12
+#define mc2_chn_ddr_chn_arb_param_wrr6_weight_DEFAULT              0x00000001
+
+
+#define mc2_chn_ddr_chn_arb_param_wrr5_weight_MASK                 0x00000c00
+#define mc2_chn_ddr_chn_arb_param_wrr5_weight_ALIGN                0
+#define mc2_chn_ddr_chn_arb_param_wrr5_weight_BITS                 2
+#define mc2_chn_ddr_chn_arb_param_wrr5_weight_SHIFT                10
+#define mc2_chn_ddr_chn_arb_param_wrr5_weight_DEFAULT              0x00000001
+
+
+#define mc2_chn_ddr_chn_arb_param_wrr0_weight_MASK                 0x00000300
+#define mc2_chn_ddr_chn_arb_param_wrr0_weight_ALIGN                0
+#define mc2_chn_ddr_chn_arb_param_wrr0_weight_BITS                 2
+#define mc2_chn_ddr_chn_arb_param_wrr0_weight_SHIFT                8
+#define mc2_chn_ddr_chn_arb_param_wrr0_weight_DEFAULT              0x00000001
+
+
+#define mc2_chn_ddr_chn_arb_param_reserved3_MASK                   0x000000e0
+#define mc2_chn_ddr_chn_arb_param_reserved3_ALIGN                  0
+#define mc2_chn_ddr_chn_arb_param_reserved3_BITS                   3
+#define mc2_chn_ddr_chn_arb_param_reserved3_SHIFT                  5
+
+
+#define mc2_chn_ddr_chn_arb_param_rdwr_wrr_weight_MASK             0x0000001f
+#define mc2_chn_ddr_chn_arb_param_rdwr_wrr_weight_ALIGN            0
+#define mc2_chn_ddr_chn_arb_param_rdwr_wrr_weight_BITS             5
+#define mc2_chn_ddr_chn_arb_param_rdwr_wrr_weight_SHIFT            0
+#define mc2_chn_ddr_chn_arb_param_rdwr_wrr_weight_DEFAULT          0x00000010
+
+
+
+
+#define mc2_chn_ddr_chn_sch_cfg_opt_chn_hshk_dis_MASK              0x80000000
+#define mc2_chn_ddr_chn_sch_cfg_opt_chn_hshk_dis_ALIGN             0
+#define mc2_chn_ddr_chn_sch_cfg_opt_chn_hshk_dis_BITS              1
+#define mc2_chn_ddr_chn_sch_cfg_opt_chn_hshk_dis_SHIFT             31
+#define mc2_chn_ddr_chn_sch_cfg_opt_chn_hshk_dis_DEFAULT           0x00000000
+
+
+#define mc2_chn_ddr_chn_sch_cfg_reserved0_MASK                     0x7ffffff8
+#define mc2_chn_ddr_chn_sch_cfg_reserved0_ALIGN                    0
+#define mc2_chn_ddr_chn_sch_cfg_reserved0_BITS                     28
+#define mc2_chn_ddr_chn_sch_cfg_reserved0_SHIFT                    3
+
+
+#define mc2_chn_ddr_chn_sch_cfg_num_cmdr_MASK                      0x00000007
+#define mc2_chn_ddr_chn_sch_cfg_num_cmdr_ALIGN                     0
+#define mc2_chn_ddr_chn_sch_cfg_num_cmdr_BITS                      3
+#define mc2_chn_ddr_chn_sch_cfg_num_cmdr_SHIFT                     0
+#define mc2_chn_ddr_chn_sch_cfg_num_cmdr_DEFAULT                   0x00000007
+
+
+
+
+#define mc2_chn_ddr_phy_st_reserved0_MASK                          0xffffffe0
+#define mc2_chn_ddr_phy_st_reserved0_ALIGN                         0
+#define mc2_chn_ddr_phy_st_reserved0_BITS                          27
+#define mc2_chn_ddr_phy_st_reserved0_SHIFT                         5
+
+
+#define mc2_chn_ddr_phy_st_phy_st_phy_ready_MASK                   0x00000010
+#define mc2_chn_ddr_phy_st_phy_st_phy_ready_ALIGN                  0
+#define mc2_chn_ddr_phy_st_phy_st_phy_ready_BITS                   1
+#define mc2_chn_ddr_phy_st_phy_st_phy_ready_SHIFT                  4
+#define mc2_chn_ddr_phy_st_phy_st_phy_ready_DEFAULT                0x00000000
+
+
+#define mc2_chn_ddr_phy_st_reserved1_MASK                          0x00000008
+#define mc2_chn_ddr_phy_st_reserved1_ALIGN                         0
+#define mc2_chn_ddr_phy_st_reserved1_BITS                          1
+#define mc2_chn_ddr_phy_st_reserved1_SHIFT                         3
+
+
+#define mc2_chn_ddr_phy_st_phy_st_sw_reset_MASK                    0x00000004
+#define mc2_chn_ddr_phy_st_phy_st_sw_reset_ALIGN                   0
+#define mc2_chn_ddr_phy_st_phy_st_sw_reset_BITS                    1
+#define mc2_chn_ddr_phy_st_phy_st_sw_reset_SHIFT                   2
+#define mc2_chn_ddr_phy_st_phy_st_sw_reset_DEFAULT                 0x00000000
+
+
+#define mc2_chn_ddr_phy_st_phy_st_hw_reset_MASK                    0x00000002
+#define mc2_chn_ddr_phy_st_phy_st_hw_reset_ALIGN                   0
+#define mc2_chn_ddr_phy_st_phy_st_hw_reset_BITS                    1
+#define mc2_chn_ddr_phy_st_phy_st_hw_reset_SHIFT                   1
+#define mc2_chn_ddr_phy_st_phy_st_hw_reset_DEFAULT                 0x00000000
+
+
+#define mc2_chn_ddr_phy_st_phy_st_phy_power_up_MASK                0x00000001
+#define mc2_chn_ddr_phy_st_phy_st_phy_power_up_ALIGN               0
+#define mc2_chn_ddr_phy_st_phy_st_phy_power_up_BITS                1
+#define mc2_chn_ddr_phy_st_phy_st_phy_power_up_SHIFT               0
+#define mc2_chn_ddr_phy_st_phy_st_phy_power_up_DEFAULT             0x00000000
+
+
+
+
+#define mc2_chn_ddr_dram_cfg_reserved0_MASK                        0xfffe0000
+#define mc2_chn_ddr_dram_cfg_reserved0_ALIGN                       0
+#define mc2_chn_ddr_dram_cfg_reserved0_BITS                        15
+#define mc2_chn_ddr_dram_cfg_reserved0_SHIFT                       17
+
+
+#define mc2_chn_ddr_dram_cfg_dram_srx_cmd_MASK                     0x00010000
+#define mc2_chn_ddr_dram_cfg_dram_srx_cmd_ALIGN                    0
+#define mc2_chn_ddr_dram_cfg_dram_srx_cmd_BITS                     1
+#define mc2_chn_ddr_dram_cfg_dram_srx_cmd_SHIFT                    16
+#define mc2_chn_ddr_dram_cfg_dram_srx_cmd_DEFAULT                  0x00000000
+
+
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs_mode_MASK                 0x0000c000
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs_mode_ALIGN                0
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs_mode_BITS                 2
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs_mode_SHIFT                14
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs_mode_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs1_enable_MASK              0x00002000
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs1_enable_ALIGN             0
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs1_enable_BITS              1
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs1_enable_SHIFT             13
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs1_enable_DEFAULT           0x00000000
+
+
+#define mc2_chn_ddr_dram_cfg_reserved1_MASK                        0x00001800
+#define mc2_chn_ddr_dram_cfg_reserved1_ALIGN                       0
+#define mc2_chn_ddr_dram_cfg_reserved1_BITS                        2
+#define mc2_chn_ddr_dram_cfg_reserved1_SHIFT                       11
+
+
+#define mc2_chn_ddr_dram_cfg_dram_cfg_2taddrcmd_MASK               0x00000400
+#define mc2_chn_ddr_dram_cfg_dram_cfg_2taddrcmd_ALIGN              0
+#define mc2_chn_ddr_dram_cfg_dram_cfg_2taddrcmd_BITS               1
+#define mc2_chn_ddr_dram_cfg_dram_cfg_2taddrcmd_SHIFT              10
+#define mc2_chn_ddr_dram_cfg_dram_cfg_2taddrcmd_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_dram_cfg_cmd_timeout_MASK                      0x000003f0
+#define mc2_chn_ddr_dram_cfg_cmd_timeout_ALIGN                     0
+#define mc2_chn_ddr_dram_cfg_cmd_timeout_BITS                      6
+#define mc2_chn_ddr_dram_cfg_cmd_timeout_SHIFT                     4
+#define mc2_chn_ddr_dram_cfg_cmd_timeout_DEFAULT                   0x0000003f
+
+
+#define mc2_chn_ddr_dram_cfg_dram_cfg_dramtype_MASK                0x0000000f
+#define mc2_chn_ddr_dram_cfg_dram_cfg_dramtype_ALIGN               0
+#define mc2_chn_ddr_dram_cfg_dram_cfg_dramtype_BITS                4
+#define mc2_chn_ddr_dram_cfg_dram_cfg_dramtype_SHIFT               0
+#define mc2_chn_ddr_dram_cfg_dram_cfg_dramtype_DEFAULT             0x00000004
+
+
+
+
+#define mc2_chn_ddr_dcmd_sch_sel_MASK                              0x80000000
+#define mc2_chn_ddr_dcmd_sch_sel_ALIGN                             0
+#define mc2_chn_ddr_dcmd_sch_sel_BITS                              1
+#define mc2_chn_ddr_dcmd_sch_sel_SHIFT                             31
+#define mc2_chn_ddr_dcmd_sch_sel_DEFAULT                           0x00000000
+
+
+#define mc2_chn_ddr_dcmd_reserved0_MASK                            0x7ffe0000
+#define mc2_chn_ddr_dcmd_reserved0_ALIGN                           0
+#define mc2_chn_ddr_dcmd_reserved0_BITS                            14
+#define mc2_chn_ddr_dcmd_reserved0_SHIFT                           17
+
+
+#define mc2_chn_ddr_dcmd_dramcmdreq_MASK                           0x00010000
+#define mc2_chn_ddr_dcmd_dramcmdreq_ALIGN                          0
+#define mc2_chn_ddr_dcmd_dramcmdreq_BITS                           1
+#define mc2_chn_ddr_dcmd_dramcmdreq_SHIFT                          16
+#define mc2_chn_ddr_dcmd_dramcmdreq_DEFAULT                        0x00000000
+
+
+#define mc2_chn_ddr_dcmd_reserved1_MASK                            0x0000fc00
+#define mc2_chn_ddr_dcmd_reserved1_ALIGN                           0
+#define mc2_chn_ddr_dcmd_reserved1_BITS                            6
+#define mc2_chn_ddr_dcmd_reserved1_SHIFT                           10
+
+
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs1_MASK                       0x00000200
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs1_ALIGN                      0
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs1_BITS                       1
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs1_SHIFT                      9
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs1_DEFAULT                    0x00000000
+
+
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs0_MASK                       0x00000100
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs0_ALIGN                      0
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs0_BITS                       1
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs0_SHIFT                      8
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs0_DEFAULT                    0x00000000
+
+
+#define mc2_chn_ddr_dcmd_reserved2_MASK                            0x000000e0
+#define mc2_chn_ddr_dcmd_reserved2_ALIGN                           0
+#define mc2_chn_ddr_dcmd_reserved2_BITS                            3
+#define mc2_chn_ddr_dcmd_reserved2_SHIFT                           5
+
+
+#define mc2_chn_ddr_dcmd_dcmd_memcmd_MASK                          0x0000001f
+#define mc2_chn_ddr_dcmd_dcmd_memcmd_ALIGN                         0
+#define mc2_chn_ddr_dcmd_dcmd_memcmd_BITS                          5
+#define mc2_chn_ddr_dcmd_dcmd_memcmd_SHIFT                         0
+#define mc2_chn_ddr_dcmd_dcmd_memcmd_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_chn_ddr_dmode_0_reserved0_MASK                         0x80000000
+#define mc2_chn_ddr_dmode_0_reserved0_ALIGN                        0
+#define mc2_chn_ddr_dmode_0_reserved0_BITS                         1
+#define mc2_chn_ddr_dmode_0_reserved0_SHIFT                        31
+
+
+#define mc2_chn_ddr_dmode_0_dmode_modedata_MASK                    0x7fff0000
+#define mc2_chn_ddr_dmode_0_dmode_modedata_ALIGN                   0
+#define mc2_chn_ddr_dmode_0_dmode_modedata_BITS                    15
+#define mc2_chn_ddr_dmode_0_dmode_modedata_SHIFT                   16
+#define mc2_chn_ddr_dmode_0_dmode_modedata_DEFAULT                 0x00000000
+
+
+#define mc2_chn_ddr_dmode_0_reserved1_MASK                         0x00008000
+#define mc2_chn_ddr_dmode_0_reserved1_ALIGN                        0
+#define mc2_chn_ddr_dmode_0_reserved1_BITS                         1
+#define mc2_chn_ddr_dmode_0_reserved1_SHIFT                        15
+
+
+#define mc2_chn_ddr_dmode_0_dmode_emodedata_MASK                   0x00007fff
+#define mc2_chn_ddr_dmode_0_dmode_emodedata_ALIGN                  0
+#define mc2_chn_ddr_dmode_0_dmode_emodedata_BITS                   15
+#define mc2_chn_ddr_dmode_0_dmode_emodedata_SHIFT                  0
+#define mc2_chn_ddr_dmode_0_dmode_emodedata_DEFAULT                0x00000000
+
+
+
+
+#define mc2_chn_ddr_dmode_2_reserved0_MASK                         0x80000000
+#define mc2_chn_ddr_dmode_2_reserved0_ALIGN                        0
+#define mc2_chn_ddr_dmode_2_reserved0_BITS                         1
+#define mc2_chn_ddr_dmode_2_reserved0_SHIFT                        31
+
+
+#define mc2_chn_ddr_dmode_2_dmode_emode3data_MASK                  0x7fff0000
+#define mc2_chn_ddr_dmode_2_dmode_emode3data_ALIGN                 0
+#define mc2_chn_ddr_dmode_2_dmode_emode3data_BITS                  15
+#define mc2_chn_ddr_dmode_2_dmode_emode3data_SHIFT                 16
+#define mc2_chn_ddr_dmode_2_dmode_emode3data_DEFAULT               0x00000000
+
+
+#define mc2_chn_ddr_dmode_2_reserved1_MASK                         0x00008000
+#define mc2_chn_ddr_dmode_2_reserved1_ALIGN                        0
+#define mc2_chn_ddr_dmode_2_reserved1_BITS                         1
+#define mc2_chn_ddr_dmode_2_reserved1_SHIFT                        15
+
+
+#define mc2_chn_ddr_dmode_2_dmode_emode2data_MASK                  0x00007fff
+#define mc2_chn_ddr_dmode_2_dmode_emode2data_ALIGN                 0
+#define mc2_chn_ddr_dmode_2_dmode_emode2data_BITS                  15
+#define mc2_chn_ddr_dmode_2_dmode_emode2data_SHIFT                 0
+#define mc2_chn_ddr_dmode_2_dmode_emode2data_DEFAULT               0x00000000
+
+
+
+
+#define mc2_chn_ddr_odt_reserved0_MASK                             0xfffffc00
+#define mc2_chn_ddr_odt_reserved0_ALIGN                            0
+#define mc2_chn_ddr_odt_reserved0_BITS                             22
+#define mc2_chn_ddr_odt_reserved0_SHIFT                            10
+
+
+#define mc2_chn_ddr_odt_odt_dynodten_MASK                          0x00000200
+#define mc2_chn_ddr_odt_odt_dynodten_ALIGN                         0
+#define mc2_chn_ddr_odt_odt_dynodten_BITS                          1
+#define mc2_chn_ddr_odt_odt_dynodten_SHIFT                         9
+#define mc2_chn_ddr_odt_odt_dynodten_DEFAULT                       0x00000001
+
+
+#define mc2_chn_ddr_odt_odt_csoddodten_MASK                        0x00000100
+#define mc2_chn_ddr_odt_odt_csoddodten_ALIGN                       0
+#define mc2_chn_ddr_odt_odt_csoddodten_BITS                        1
+#define mc2_chn_ddr_odt_odt_csoddodten_SHIFT                       8
+#define mc2_chn_ddr_odt_odt_csoddodten_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs1_MASK                        0x00000080
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs1_ALIGN                       0
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs1_BITS                        1
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs1_SHIFT                       7
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs1_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs0_MASK                        0x00000040
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs0_ALIGN                       0
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs0_BITS                        1
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs0_SHIFT                       6
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs0_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs1_MASK                        0x00000020
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs1_ALIGN                       0
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs1_BITS                        1
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs1_SHIFT                       5
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs1_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs0_MASK                        0x00000010
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs0_ALIGN                       0
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs0_BITS                        1
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs0_SHIFT                       4
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs0_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs1_MASK                        0x00000008
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs1_ALIGN                       0
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs1_BITS                        1
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs1_SHIFT                       3
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs1_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs0_MASK                        0x00000004
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs0_ALIGN                       0
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs0_BITS                        1
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs0_SHIFT                       2
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs0_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs1_MASK                        0x00000002
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs1_ALIGN                       0
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs1_BITS                        1
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs1_SHIFT                       1
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs1_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs0_MASK                        0x00000001
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs0_ALIGN                       0
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs0_BITS                        1
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs0_SHIFT                       0
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs0_DEFAULT                     0x00000000
+
+
+
+
+#define mc2_chn_ddr_ddr_param_cmd0_tAL_MASK                        0xff000000
+#define mc2_chn_ddr_ddr_param_cmd0_tAL_ALIGN                       0
+#define mc2_chn_ddr_ddr_param_cmd0_tAL_BITS                        8
+#define mc2_chn_ddr_ddr_param_cmd0_tAL_SHIFT                       24
+#define mc2_chn_ddr_ddr_param_cmd0_tAL_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_cmd0_tRCD_MASK                       0x00ff0000
+#define mc2_chn_ddr_ddr_param_cmd0_tRCD_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_cmd0_tRCD_BITS                       8
+#define mc2_chn_ddr_ddr_param_cmd0_tRCD_SHIFT                      16
+#define mc2_chn_ddr_ddr_param_cmd0_tRCD_DEFAULT                    0x00000006
+
+
+#define mc2_chn_ddr_ddr_param_cmd0_tCWL_MASK                       0x0000ff00
+#define mc2_chn_ddr_ddr_param_cmd0_tCWL_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_cmd0_tCWL_BITS                       8
+#define mc2_chn_ddr_ddr_param_cmd0_tCWL_SHIFT                      8
+#define mc2_chn_ddr_ddr_param_cmd0_tCWL_DEFAULT                    0x00000004
+
+
+#define mc2_chn_ddr_ddr_param_cmd0_tCL_MASK                        0x000000ff
+#define mc2_chn_ddr_ddr_param_cmd0_tCL_ALIGN                       0
+#define mc2_chn_ddr_ddr_param_cmd0_tCL_BITS                        8
+#define mc2_chn_ddr_ddr_param_cmd0_tCL_SHIFT                       0
+#define mc2_chn_ddr_ddr_param_cmd0_tCL_DEFAULT                     0x00000005
+
+
+
+
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_L_MASK                     0xff000000
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_L_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_L_BITS                     8
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_L_SHIFT                    24
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_L_DEFAULT                  0x00000008
+
+
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_S_MASK                     0x00ff0000
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_S_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_S_BITS                     8
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_S_SHIFT                    16
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_S_DEFAULT                  0x00000008
+
+
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_L_MASK                     0x0000ff00
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_L_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_L_BITS                     8
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_L_SHIFT                    8
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_L_DEFAULT                  0x00000004
+
+
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_S_MASK                     0x000000ff
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_S_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_S_BITS                     8
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_S_SHIFT                    0
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_S_DEFAULT                  0x00000004
+
+
+
+
+#define mc2_chn_ddr_ddr_param_cmd2_reserved0_MASK                  0xffffff00
+#define mc2_chn_ddr_ddr_param_cmd2_reserved0_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_cmd2_reserved0_BITS                  24
+#define mc2_chn_ddr_ddr_param_cmd2_reserved0_SHIFT                 8
+
+
+#define mc2_chn_ddr_ddr_param_cmd2_tCCDMW_MASK                     0x000000ff
+#define mc2_chn_ddr_ddr_param_cmd2_tCCDMW_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_cmd2_tCCDMW_BITS                     8
+#define mc2_chn_ddr_ddr_param_cmd2_tCCDMW_SHIFT                    0
+#define mc2_chn_ddr_ddr_param_cmd2_tCCDMW_DEFAULT                  0x00000020
+
+
+
+
+#define mc2_chn_ddr_ddr_param_cmd3_tFAW_MASK                       0xff000000
+#define mc2_chn_ddr_ddr_param_cmd3_tFAW_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_cmd3_tFAW_BITS                       8
+#define mc2_chn_ddr_ddr_param_cmd3_tFAW_SHIFT                      24
+#define mc2_chn_ddr_ddr_param_cmd3_tFAW_DEFAULT                    0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_cmd3_tRPpb_MASK                      0x00ff0000
+#define mc2_chn_ddr_ddr_param_cmd3_tRPpb_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_cmd3_tRPpb_BITS                      8
+#define mc2_chn_ddr_ddr_param_cmd3_tRPpb_SHIFT                     16
+#define mc2_chn_ddr_ddr_param_cmd3_tRPpb_DEFAULT                   0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_cmd3_tRPab_MASK                      0x0000ff00
+#define mc2_chn_ddr_ddr_param_cmd3_tRPab_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_cmd3_tRPab_BITS                      8
+#define mc2_chn_ddr_ddr_param_cmd3_tRPab_SHIFT                     8
+#define mc2_chn_ddr_ddr_param_cmd3_tRPab_DEFAULT                   0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_cmd3_tRAS_MASK                       0x000000ff
+#define mc2_chn_ddr_ddr_param_cmd3_tRAS_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_cmd3_tRAS_BITS                       8
+#define mc2_chn_ddr_ddr_param_cmd3_tRAS_SHIFT                      0
+#define mc2_chn_ddr_ddr_param_cmd3_tRAS_DEFAULT                    0x00000011
+
+
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_L_MASK                     0xff000000
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_L_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_L_BITS                     8
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_L_SHIFT                    24
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_L_DEFAULT                  0x00000002
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_S_MASK                     0x00ff0000
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_S_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_S_BITS                     8
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_S_SHIFT                    16
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_S_DEFAULT                  0x00000002
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tWR_MASK                        0x0000ff00
+#define mc2_chn_ddr_ddr_param_dat0_tWR_ALIGN                       0
+#define mc2_chn_ddr_ddr_param_dat0_tWR_BITS                        8
+#define mc2_chn_ddr_ddr_param_dat0_tWR_SHIFT                       8
+#define mc2_chn_ddr_ddr_param_dat0_tWR_DEFAULT                     0x00000020
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tDQSCK_MASK                     0x000000f0
+#define mc2_chn_ddr_ddr_param_dat0_tDQSCK_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_dat0_tDQSCK_BITS                     4
+#define mc2_chn_ddr_ddr_param_dat0_tDQSCK_SHIFT                    4
+#define mc2_chn_ddr_ddr_param_dat0_tDQSCK_DEFAULT                  0x00000007
+
+
+#define mc2_chn_ddr_ddr_param_dat0_reserved0_MASK                  0x0000000c
+#define mc2_chn_ddr_ddr_param_dat0_reserved0_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_dat0_reserved0_BITS                  2
+#define mc2_chn_ddr_ddr_param_dat0_reserved0_SHIFT                 2
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tWPST_MASK                      0x00000002
+#define mc2_chn_ddr_ddr_param_dat0_tWPST_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_dat0_tWPST_BITS                      1
+#define mc2_chn_ddr_ddr_param_dat0_tWPST_SHIFT                     1
+#define mc2_chn_ddr_ddr_param_dat0_tWPST_DEFAULT                   0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tWPRE_MASK                      0x00000001
+#define mc2_chn_ddr_ddr_param_dat0_tWPRE_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_dat0_tWPRE_BITS                      1
+#define mc2_chn_ddr_ddr_param_dat0_tWPRE_SHIFT                     0
+#define mc2_chn_ddr_ddr_param_dat0_tWPRE_DEFAULT                   0x00000000
+
+
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tRPST_MASK                      0x80000000
+#define mc2_chn_ddr_ddr_param_dat1_tRPST_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_dat1_tRPST_BITS                      1
+#define mc2_chn_ddr_ddr_param_dat1_tRPST_SHIFT                     31
+#define mc2_chn_ddr_ddr_param_dat1_tRPST_DEFAULT                   0x00000001
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tRPRE_MASK                      0x40000000
+#define mc2_chn_ddr_ddr_param_dat1_tRPRE_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_dat1_tRPRE_BITS                      1
+#define mc2_chn_ddr_ddr_param_dat1_tRPRE_SHIFT                     30
+#define mc2_chn_ddr_ddr_param_dat1_tRPRE_DEFAULT                   0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_dat1_reserved0_MASK                  0x3f000000
+#define mc2_chn_ddr_ddr_param_dat1_reserved0_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_dat1_reserved0_BITS                  6
+#define mc2_chn_ddr_ddr_param_dat1_reserved0_SHIFT                 24
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tW2R_MASK                       0x00ff0000
+#define mc2_chn_ddr_ddr_param_dat1_tW2R_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_dat1_tW2R_BITS                       8
+#define mc2_chn_ddr_ddr_param_dat1_tW2R_SHIFT                      16
+#define mc2_chn_ddr_ddr_param_dat1_tW2R_DEFAULT                    0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tR2R_MASK                       0x0000f000
+#define mc2_chn_ddr_ddr_param_dat1_tR2R_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_dat1_tR2R_BITS                       4
+#define mc2_chn_ddr_ddr_param_dat1_tR2R_SHIFT                      12
+#define mc2_chn_ddr_ddr_param_dat1_tR2R_DEFAULT                    0x00000003
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tW2W_MASK                       0x00000f00
+#define mc2_chn_ddr_ddr_param_dat1_tW2W_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_dat1_tW2W_BITS                       4
+#define mc2_chn_ddr_ddr_param_dat1_tW2W_SHIFT                      8
+#define mc2_chn_ddr_ddr_param_dat1_tW2W_DEFAULT                    0x00000008
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tR2W_MASK                       0x000000f0
+#define mc2_chn_ddr_ddr_param_dat1_tR2W_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_dat1_tR2W_BITS                       4
+#define mc2_chn_ddr_ddr_param_dat1_tR2W_SHIFT                      4
+#define mc2_chn_ddr_ddr_param_dat1_tR2W_DEFAULT                    0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_dat1_reserved1_MASK                  0x0000000f
+#define mc2_chn_ddr_ddr_param_dat1_reserved1_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_dat1_reserved1_BITS                  4
+#define mc2_chn_ddr_ddr_param_dat1_reserved1_SHIFT                 0
+
+
+
+
+#define mc2_chn_ddr_ddr_param_pre0_autoprecharge_MASK              0x80000000
+#define mc2_chn_ddr_ddr_param_pre0_autoprecharge_ALIGN             0
+#define mc2_chn_ddr_ddr_param_pre0_autoprecharge_BITS              1
+#define mc2_chn_ddr_ddr_param_pre0_autoprecharge_SHIFT             31
+#define mc2_chn_ddr_ddr_param_pre0_autoprecharge_DEFAULT           0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_pre0_reserved0_MASK                  0x7fff0000
+#define mc2_chn_ddr_ddr_param_pre0_reserved0_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_pre0_reserved0_BITS                  15
+#define mc2_chn_ddr_ddr_param_pre0_reserved0_SHIFT                 16
+
+
+#define mc2_chn_ddr_ddr_param_pre0_tPPD_MASK                       0x0000ff00
+#define mc2_chn_ddr_ddr_param_pre0_tPPD_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_pre0_tPPD_BITS                       8
+#define mc2_chn_ddr_ddr_param_pre0_tPPD_SHIFT                      8
+#define mc2_chn_ddr_ddr_param_pre0_tPPD_DEFAULT                    0x00000002
+
+
+#define mc2_chn_ddr_ddr_param_pre0_tRTP_MASK                       0x000000ff
+#define mc2_chn_ddr_ddr_param_pre0_tRTP_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_pre0_tRTP_BITS                       8
+#define mc2_chn_ddr_ddr_param_pre0_tRTP_SHIFT                      0
+#define mc2_chn_ddr_ddr_param_pre0_tRTP_DEFAULT                    0x00000002
+
+
+
+
+#define mc2_chn_ddr_ddr_param_pwr0_tXP_MASK                        0xfff00000
+#define mc2_chn_ddr_ddr_param_pwr0_tXP_ALIGN                       0
+#define mc2_chn_ddr_ddr_param_pwr0_tXP_BITS                        12
+#define mc2_chn_ddr_ddr_param_pwr0_tXP_SHIFT                       20
+#define mc2_chn_ddr_ddr_param_pwr0_tXP_DEFAULT                     0x00000003
+
+
+#define mc2_chn_ddr_ddr_param_pwr0_tXSR_MASK                       0x000fff00
+#define mc2_chn_ddr_ddr_param_pwr0_tXSR_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_pwr0_tXSR_BITS                       12
+#define mc2_chn_ddr_ddr_param_pwr0_tXSR_SHIFT                      8
+#define mc2_chn_ddr_ddr_param_pwr0_tXSR_DEFAULT                    0x00000002
+
+
+#define mc2_chn_ddr_ddr_param_pwr0_tSR_MASK                        0x000000ff
+#define mc2_chn_ddr_ddr_param_pwr0_tSR_ALIGN                       0
+#define mc2_chn_ddr_ddr_param_pwr0_tSR_BITS                        8
+#define mc2_chn_ddr_ddr_param_pwr0_tSR_SHIFT                       0
+#define mc2_chn_ddr_ddr_param_pwr0_tSR_DEFAULT                     0x00000003
+
+
+
+
+#define mc2_chn_ddr_ddr_param_zqc0_reserved0_MASK                  0xf0000000
+#define mc2_chn_ddr_ddr_param_zqc0_reserved0_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_zqc0_reserved0_BITS                  4
+#define mc2_chn_ddr_ddr_param_zqc0_reserved0_SHIFT                 28
+
+
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCL_MASK                      0x0fff0000
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCL_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCL_BITS                      12
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCL_SHIFT                     16
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCL_DEFAULT                   0x00000100
+
+
+#define mc2_chn_ddr_ddr_param_zqc0_reserved1_MASK                  0x0000fe00
+#define mc2_chn_ddr_ddr_param_zqc0_reserved1_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_zqc0_reserved1_BITS                  7
+#define mc2_chn_ddr_ddr_param_zqc0_reserved1_SHIFT                 9
+
+
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCS_MASK                      0x000001ff
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCS_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCS_BITS                      9
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCS_SHIFT                     0
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCS_DEFAULT                   0x00000040
+
+
+
+
+#define mc2_chn_ddr_refresh_aref0_refmaxdelay_MASK                 0xf0000000
+#define mc2_chn_ddr_refresh_aref0_refmaxdelay_ALIGN                0
+#define mc2_chn_ddr_refresh_aref0_refmaxdelay_BITS                 4
+#define mc2_chn_ddr_refresh_aref0_refmaxdelay_SHIFT                28
+#define mc2_chn_ddr_refresh_aref0_refmaxdelay_DEFAULT              0x00000004
+
+
+#define mc2_chn_ddr_refresh_aref0_reserved0_MASK                   0x0e000000
+#define mc2_chn_ddr_refresh_aref0_reserved0_ALIGN                  0
+#define mc2_chn_ddr_refresh_aref0_reserved0_BITS                   3
+#define mc2_chn_ddr_refresh_aref0_reserved0_SHIFT                  25
+
+
+#define mc2_chn_ddr_refresh_aref0_pbref_ordered_MASK               0x01000000
+#define mc2_chn_ddr_refresh_aref0_pbref_ordered_ALIGN              0
+#define mc2_chn_ddr_refresh_aref0_pbref_ordered_BITS               1
+#define mc2_chn_ddr_refresh_aref0_pbref_ordered_SHIFT              24
+#define mc2_chn_ddr_refresh_aref0_pbref_ordered_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_refresh_aref0_pbref_intlv_MASK                 0x00ff0000
+#define mc2_chn_ddr_refresh_aref0_pbref_intlv_ALIGN                0
+#define mc2_chn_ddr_refresh_aref0_pbref_intlv_BITS                 8
+#define mc2_chn_ddr_refresh_aref0_pbref_intlv_SHIFT                16
+#define mc2_chn_ddr_refresh_aref0_pbref_intlv_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_refresh_aref0_abref_num_MASK                   0x0000f000
+#define mc2_chn_ddr_refresh_aref0_abref_num_ALIGN                  0
+#define mc2_chn_ddr_refresh_aref0_abref_num_BITS                   4
+#define mc2_chn_ddr_refresh_aref0_abref_num_SHIFT                  12
+#define mc2_chn_ddr_refresh_aref0_abref_num_DEFAULT                0x00000001
+
+
+#define mc2_chn_ddr_refresh_aref0_reserved1_MASK                   0x00000c00
+#define mc2_chn_ddr_refresh_aref0_reserved1_ALIGN                  0
+#define mc2_chn_ddr_refresh_aref0_reserved1_BITS                   2
+#define mc2_chn_ddr_refresh_aref0_reserved1_SHIFT                  10
+
+
+#define mc2_chn_ddr_refresh_aref0_tREFI_MASK                       0x000003ff
+#define mc2_chn_ddr_refresh_aref0_tREFI_ALIGN                      0
+#define mc2_chn_ddr_refresh_aref0_tREFI_BITS                       10
+#define mc2_chn_ddr_refresh_aref0_tREFI_SHIFT                      0
+#define mc2_chn_ddr_refresh_aref0_tREFI_DEFAULT                    0x00000103
+
+
+
+
+#define mc2_chn_ddr_refresh_aref1_refdisable_MASK                  0x80000000
+#define mc2_chn_ddr_refresh_aref1_refdisable_ALIGN                 0
+#define mc2_chn_ddr_refresh_aref1_refdisable_BITS                  1
+#define mc2_chn_ddr_refresh_aref1_refdisable_SHIFT                 31
+#define mc2_chn_ddr_refresh_aref1_refdisable_DEFAULT               0x00000000
+
+
+#define mc2_chn_ddr_refresh_aref1_reserved0_MASK                   0x70000000
+#define mc2_chn_ddr_refresh_aref1_reserved0_ALIGN                  0
+#define mc2_chn_ddr_refresh_aref1_reserved0_BITS                   3
+#define mc2_chn_ddr_refresh_aref1_reserved0_SHIFT                  28
+
+
+#define mc2_chn_ddr_refresh_aref1_tRFCpb_MASK                      0x0fff0000
+#define mc2_chn_ddr_refresh_aref1_tRFCpb_ALIGN                     0
+#define mc2_chn_ddr_refresh_aref1_tRFCpb_BITS                      12
+#define mc2_chn_ddr_refresh_aref1_tRFCpb_SHIFT                     16
+#define mc2_chn_ddr_refresh_aref1_tRFCpb_DEFAULT                   0x0000008d
+
+
+#define mc2_chn_ddr_refresh_aref1_reserved1_MASK                   0x0000f000
+#define mc2_chn_ddr_refresh_aref1_reserved1_ALIGN                  0
+#define mc2_chn_ddr_refresh_aref1_reserved1_BITS                   4
+#define mc2_chn_ddr_refresh_aref1_reserved1_SHIFT                  12
+
+
+#define mc2_chn_ddr_refresh_aref1_tRFCab_MASK                      0x00000fff
+#define mc2_chn_ddr_refresh_aref1_tRFCab_ALIGN                     0
+#define mc2_chn_ddr_refresh_aref1_tRFCab_BITS                      12
+#define mc2_chn_ddr_refresh_aref1_tRFCab_SHIFT                     0
+#define mc2_chn_ddr_refresh_aref1_tRFCab_DEFAULT                   0x0000011a
+
+
+
+
+#define mc2_chn_ddr_auto_self_refresh_enable_MASK                  0x80000000
+#define mc2_chn_ddr_auto_self_refresh_enable_ALIGN                 0
+#define mc2_chn_ddr_auto_self_refresh_enable_BITS                  1
+#define mc2_chn_ddr_auto_self_refresh_enable_SHIFT                 31
+#define mc2_chn_ddr_auto_self_refresh_enable_DEFAULT               0x00000000
+
+
+#define mc2_chn_ddr_auto_self_refresh_immediate_MASK               0x40000000
+#define mc2_chn_ddr_auto_self_refresh_immediate_ALIGN              0
+#define mc2_chn_ddr_auto_self_refresh_immediate_BITS               1
+#define mc2_chn_ddr_auto_self_refresh_immediate_SHIFT              30
+#define mc2_chn_ddr_auto_self_refresh_immediate_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_auto_self_refresh_idle_count_MASK              0x3fffffff
+#define mc2_chn_ddr_auto_self_refresh_idle_count_ALIGN             0
+#define mc2_chn_ddr_auto_self_refresh_idle_count_BITS              30
+#define mc2_chn_ddr_auto_self_refresh_idle_count_SHIFT             0
+#define mc2_chn_ddr_auto_self_refresh_idle_count_DEFAULT           0x00000000
+
+
+
+
+#define mc2_chn_ddr_auto_zqcs_enable_MASK                          0x80000000
+#define mc2_chn_ddr_auto_zqcs_enable_ALIGN                         0
+#define mc2_chn_ddr_auto_zqcs_enable_BITS                          1
+#define mc2_chn_ddr_auto_zqcs_enable_SHIFT                         31
+#define mc2_chn_ddr_auto_zqcs_enable_DEFAULT                       0x00000000
+
+
+#define mc2_chn_ddr_auto_zqcs_timer_count_MASK                     0x7fffffe0
+#define mc2_chn_ddr_auto_zqcs_timer_count_ALIGN                    0
+#define mc2_chn_ddr_auto_zqcs_timer_count_BITS                     26
+#define mc2_chn_ddr_auto_zqcs_timer_count_SHIFT                    5
+#define mc2_chn_ddr_auto_zqcs_timer_count_DEFAULT                  0x00000000
+
+
+#define mc2_chn_ddr_auto_zqcs_reserved0_MASK                       0x0000001f
+#define mc2_chn_ddr_auto_zqcs_reserved0_ALIGN                      0
+#define mc2_chn_ddr_auto_zqcs_reserved0_BITS                       5
+#define mc2_chn_ddr_auto_zqcs_reserved0_SHIFT                      0
+
+
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_b_vld_MASK                 0x80000000
+#define mc2_chn_ddr_dfi_error_dfi_error_b_vld_ALIGN                0
+#define mc2_chn_ddr_dfi_error_dfi_error_b_vld_BITS                 1
+#define mc2_chn_ddr_dfi_error_dfi_error_b_vld_SHIFT                31
+#define mc2_chn_ddr_dfi_error_dfi_error_b_vld_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_b_clr_MASK                 0x40000000
+#define mc2_chn_ddr_dfi_error_dfi_error_b_clr_ALIGN                0
+#define mc2_chn_ddr_dfi_error_dfi_error_b_clr_BITS                 1
+#define mc2_chn_ddr_dfi_error_dfi_error_b_clr_SHIFT                30
+#define mc2_chn_ddr_dfi_error_dfi_error_b_clr_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_dfi_error_reserved0_MASK                       0x3f000000
+#define mc2_chn_ddr_dfi_error_reserved0_ALIGN                      0
+#define mc2_chn_ddr_dfi_error_reserved0_BITS                       6
+#define mc2_chn_ddr_dfi_error_reserved0_SHIFT                      24
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_b_info_MASK                0x00ff0000
+#define mc2_chn_ddr_dfi_error_dfi_error_b_info_ALIGN               0
+#define mc2_chn_ddr_dfi_error_dfi_error_b_info_BITS                8
+#define mc2_chn_ddr_dfi_error_dfi_error_b_info_SHIFT               16
+#define mc2_chn_ddr_dfi_error_dfi_error_b_info_DEFAULT             0x00000000
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_a_vld_MASK                 0x00008000
+#define mc2_chn_ddr_dfi_error_dfi_error_a_vld_ALIGN                0
+#define mc2_chn_ddr_dfi_error_dfi_error_a_vld_BITS                 1
+#define mc2_chn_ddr_dfi_error_dfi_error_a_vld_SHIFT                15
+#define mc2_chn_ddr_dfi_error_dfi_error_a_vld_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_a_clr_MASK                 0x00004000
+#define mc2_chn_ddr_dfi_error_dfi_error_a_clr_ALIGN                0
+#define mc2_chn_ddr_dfi_error_dfi_error_a_clr_BITS                 1
+#define mc2_chn_ddr_dfi_error_dfi_error_a_clr_SHIFT                14
+#define mc2_chn_ddr_dfi_error_dfi_error_a_clr_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_dfi_error_reserved1_MASK                       0x00003f00
+#define mc2_chn_ddr_dfi_error_reserved1_ALIGN                      0
+#define mc2_chn_ddr_dfi_error_reserved1_BITS                       6
+#define mc2_chn_ddr_dfi_error_reserved1_SHIFT                      8
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_a_info_MASK                0x000000ff
+#define mc2_chn_ddr_dfi_error_dfi_error_a_info_ALIGN               0
+#define mc2_chn_ddr_dfi_error_dfi_error_a_info_BITS                8
+#define mc2_chn_ddr_dfi_error_dfi_error_a_info_SHIFT               0
+#define mc2_chn_ddr_dfi_error_dfi_error_a_info_DEFAULT             0x00000000
+
+
+#define mc2_afx_acc_acc_eack_MASK                                  0x80000000
+#define mc2_afx_acc_acc_eack_ALIGN                                 0
+#define mc2_afx_acc_acc_eack_BITS                                  1
+#define mc2_afx_acc_acc_eack_SHIFT                                 31
+#define mc2_afx_acc_acc_eack_DEFAULT                               0x00000000
+
+
+#define mc2_afx_acc_reserved0_MASK                                 0x7fffff00
+#define mc2_afx_acc_reserved0_ALIGN                                0
+#define mc2_afx_acc_reserved0_BITS                                 23
+#define mc2_afx_acc_reserved0_SHIFT                                8
+
+
+#define mc2_afx_acc_acc_sw_MASK                                    0x00000080
+#define mc2_afx_acc_acc_sw_ALIGN                                   0
+#define mc2_afx_acc_acc_sw_BITS                                    1
+#define mc2_afx_acc_acc_sw_SHIFT                                   7
+#define mc2_afx_acc_acc_sw_DEFAULT                                 0x00000001
+
+
+#define mc2_afx_acc_acc_sr_MASK                                    0x00000040
+#define mc2_afx_acc_acc_sr_ALIGN                                   0
+#define mc2_afx_acc_acc_sr_BITS                                    1
+#define mc2_afx_acc_acc_sr_SHIFT                                   6
+#define mc2_afx_acc_acc_sr_DEFAULT                                 0x00000001
+
+
+#define mc2_afx_acc_acc_nsw_MASK                                   0x00000020
+#define mc2_afx_acc_acc_nsw_ALIGN                                  0
+#define mc2_afx_acc_acc_nsw_BITS                                   1
+#define mc2_afx_acc_acc_nsw_SHIFT                                  5
+#define mc2_afx_acc_acc_nsw_DEFAULT                                0x00000001
+
+
+#define mc2_afx_acc_acc_nsr_MASK                                   0x00000010
+#define mc2_afx_acc_acc_nsr_ALIGN                                  0
+#define mc2_afx_acc_acc_nsr_BITS                                   1
+#define mc2_afx_acc_acc_nsr_SHIFT                                  4
+#define mc2_afx_acc_acc_nsr_DEFAULT                                0x00000001
+
+
+#define mc2_afx_acc_perm_sw_MASK                                   0x00000008
+#define mc2_afx_acc_perm_sw_ALIGN                                  0
+#define mc2_afx_acc_perm_sw_BITS                                   1
+#define mc2_afx_acc_perm_sw_SHIFT                                  3
+#define mc2_afx_acc_perm_sw_DEFAULT                                0x00000001
+
+
+#define mc2_afx_acc_perm_sr_MASK                                   0x00000004
+#define mc2_afx_acc_perm_sr_ALIGN                                  0
+#define mc2_afx_acc_perm_sr_BITS                                   1
+#define mc2_afx_acc_perm_sr_SHIFT                                  2
+#define mc2_afx_acc_perm_sr_DEFAULT                                0x00000001
+
+
+#define mc2_afx_acc_perm_nsw_MASK                                  0x00000002
+#define mc2_afx_acc_perm_nsw_ALIGN                                 0
+#define mc2_afx_acc_perm_nsw_BITS                                  1
+#define mc2_afx_acc_perm_nsw_SHIFT                                 1
+#define mc2_afx_acc_perm_nsw_DEFAULT                               0x00000001
+
+
+#define mc2_afx_acc_perm_nsr_MASK                                  0x00000001
+#define mc2_afx_acc_perm_nsr_ALIGN                                 0
+#define mc2_afx_acc_perm_nsr_BITS                                  1
+#define mc2_afx_acc_perm_nsr_SHIFT                                 0
+#define mc2_afx_acc_perm_nsr_DEFAULT                               0x00000001
+
+
+
+
+#define mc2_afx_ver_reserved0_MASK                                 0xffffff00
+#define mc2_afx_ver_reserved0_ALIGN                                0
+#define mc2_afx_ver_reserved0_BITS                                 24
+#define mc2_afx_ver_reserved0_SHIFT                                8
+
+
+#define mc2_afx_ver_version_MASK                                   0x000000ff
+#define mc2_afx_ver_version_ALIGN                                  0
+#define mc2_afx_ver_version_BITS                                   8
+#define mc2_afx_ver_version_SHIFT                                  0
+#define mc2_afx_ver_version_DEFAULT                                0x00000000
+
+
+
+
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_enable_MASK      0x80000000
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_enable_ALIGN     0
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_enable_BITS      1
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_enable_SHIFT     31
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_enable_DEFAULT   0x00000001
+
+
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_reserved0_MASK   0x7fffff00
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_reserved0_ALIGN  0
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_reserved0_BITS   23
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_reserved0_SHIFT  8
+
+
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_addr_hi_MASK     0x000000ff
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_addr_hi_ALIGN    0
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_addr_hi_BITS     8
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_addr_hi_SHIFT    0
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_addr_hi_DEFAULT  0x00000001
+
+
+
+
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo_addr_lo_MASK     0xffffffff
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo_addr_lo_ALIGN    0
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo_addr_lo_BITS     32
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo_addr_lo_SHIFT    0
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo_addr_lo_DEFAULT  0x7fff0000
+
+
+
+
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_reserved0_MASK     0xffffff00
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_reserved0_ALIGN    0
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_reserved0_BITS     24
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_reserved0_SHIFT    8
+
+
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_addr_hi_MASK       0x000000ff
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_addr_hi_ALIGN      0
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_addr_hi_BITS       8
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_addr_hi_SHIFT      0
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_addr_hi_DEFAULT    0x00000001
+
+
+
+
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo_addr_lo_MASK       0xffffffff
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo_addr_lo_ALIGN      0
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo_addr_lo_BITS       32
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo_addr_lo_SHIFT      0
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo_addr_lo_DEFAULT    0x7fffffff
+
+
+
+
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_enable_MASK           0x80000000
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_enable_ALIGN          0
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_enable_BITS           1
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_enable_SHIFT          31
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_enable_DEFAULT        0x00000000
+
+
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_reserved0_MASK        0x7fffff00
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_reserved0_ALIGN       0
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_reserved0_BITS        23
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_reserved0_SHIFT       8
+
+
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_addr_hi_MASK          0x000000ff
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_addr_hi_ALIGN         0
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_addr_hi_BITS          8
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_addr_hi_SHIFT         0
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_addr_hi_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo_addr_lo_MASK          0xffffffff
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo_addr_lo_ALIGN         0
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo_addr_lo_BITS          32
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo_addr_lo_SHIFT         0
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo_addr_lo_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_reserved0_MASK          0xffffff00
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_reserved0_ALIGN         0
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_reserved0_BITS          24
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_reserved0_SHIFT         8
+
+
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_addr_hi_MASK            0x000000ff
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_addr_hi_ALIGN           0
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_addr_hi_BITS            8
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_addr_hi_SHIFT           0
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_addr_hi_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo_addr_lo_MASK            0xffffffff
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo_addr_lo_ALIGN           0
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo_addr_lo_BITS            32
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo_addr_lo_SHIFT           0
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo_addr_lo_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_enable_MASK           0x80000000
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_enable_ALIGN          0
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_enable_BITS           1
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_enable_SHIFT          31
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_enable_DEFAULT        0x00000000
+
+
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_reserved0_MASK        0x7fffff00
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_reserved0_ALIGN       0
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_reserved0_BITS        23
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_reserved0_SHIFT       8
+
+
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_addr_hi_MASK          0x000000ff
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_addr_hi_ALIGN         0
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_addr_hi_BITS          8
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_addr_hi_SHIFT         0
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_addr_hi_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo_addr_lo_MASK          0xffffffff
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo_addr_lo_ALIGN         0
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo_addr_lo_BITS          32
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo_addr_lo_SHIFT         0
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo_addr_lo_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_reserved0_MASK          0xffffff00
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_reserved0_ALIGN         0
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_reserved0_BITS          24
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_reserved0_SHIFT         8
+
+
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_addr_hi_MASK            0x000000ff
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_addr_hi_ALIGN           0
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_addr_hi_BITS            8
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_addr_hi_SHIFT           0
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_addr_hi_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo_addr_lo_MASK            0xffffffff
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo_addr_lo_ALIGN           0
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo_addr_lo_BITS            32
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo_addr_lo_SHIFT           0
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo_addr_lo_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_enable_MASK           0x80000000
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_enable_ALIGN          0
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_enable_BITS           1
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_enable_SHIFT          31
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_enable_DEFAULT        0x00000000
+
+
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_reserved0_MASK        0x7fffff00
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_reserved0_ALIGN       0
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_reserved0_BITS        23
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_reserved0_SHIFT       8
+
+
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_addr_hi_MASK          0x000000ff
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_addr_hi_ALIGN         0
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_addr_hi_BITS          8
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_addr_hi_SHIFT         0
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_addr_hi_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo_addr_lo_MASK          0xffffffff
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo_addr_lo_ALIGN         0
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo_addr_lo_BITS          32
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo_addr_lo_SHIFT         0
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo_addr_lo_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_reserved0_MASK          0xffffff00
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_reserved0_ALIGN         0
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_reserved0_BITS          24
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_reserved0_SHIFT         8
+
+
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_addr_hi_MASK            0x000000ff
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_addr_hi_ALIGN           0
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_addr_hi_BITS            8
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_addr_hi_SHIFT           0
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_addr_hi_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo_addr_lo_MASK            0xffffffff
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo_addr_lo_ALIGN           0
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo_addr_lo_BITS            32
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo_addr_lo_SHIFT           0
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo_addr_lo_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_enable_MASK           0x80000000
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_enable_ALIGN          0
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_enable_BITS           1
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_enable_SHIFT          31
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_enable_DEFAULT        0x00000000
+
+
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_reserved0_MASK        0x7fffff00
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_reserved0_ALIGN       0
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_reserved0_BITS        23
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_reserved0_SHIFT       8
+
+
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_addr_hi_MASK          0x000000ff
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_addr_hi_ALIGN         0
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_addr_hi_BITS          8
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_addr_hi_SHIFT         0
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_addr_hi_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo_addr_lo_MASK          0xffffffff
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo_addr_lo_ALIGN         0
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo_addr_lo_BITS          32
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo_addr_lo_SHIFT         0
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo_addr_lo_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_reserved0_MASK          0xffffff00
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_reserved0_ALIGN         0
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_reserved0_BITS          24
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_reserved0_SHIFT         8
+
+
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_addr_hi_MASK            0x000000ff
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_addr_hi_ALIGN           0
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_addr_hi_BITS            8
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_addr_hi_SHIFT           0
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_addr_hi_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo_addr_lo_MASK            0xffffffff
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo_addr_lo_ALIGN           0
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo_addr_lo_BITS            32
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo_addr_lo_SHIFT           0
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo_addr_lo_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_srcid_fltr_cfg0_srcid_enable_MASK                  0x80000000
+#define mc2_afx_srcid_fltr_cfg0_srcid_enable_ALIGN                 0
+#define mc2_afx_srcid_fltr_cfg0_srcid_enable_BITS                  1
+#define mc2_afx_srcid_fltr_cfg0_srcid_enable_SHIFT                 31
+#define mc2_afx_srcid_fltr_cfg0_srcid_enable_DEFAULT               0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved0_MASK               0x70000000
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved0_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved0_BITS               3
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved0_SHIFT              28
+
+
+#define mc2_afx_srcid_fltr_cfg0_srcid_start_srcid_MASK             0x0fff0000
+#define mc2_afx_srcid_fltr_cfg0_srcid_start_srcid_ALIGN            0
+#define mc2_afx_srcid_fltr_cfg0_srcid_start_srcid_BITS             12
+#define mc2_afx_srcid_fltr_cfg0_srcid_start_srcid_SHIFT            16
+#define mc2_afx_srcid_fltr_cfg0_srcid_start_srcid_DEFAULT          0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved1_MASK               0x0000f000
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved1_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved1_BITS               4
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved1_SHIFT              12
+
+
+#define mc2_afx_srcid_fltr_cfg0_srcid_end_srcid_MASK               0x00000fff
+#define mc2_afx_srcid_fltr_cfg0_srcid_end_srcid_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg0_srcid_end_srcid_BITS               12
+#define mc2_afx_srcid_fltr_cfg0_srcid_end_srcid_SHIFT              0
+#define mc2_afx_srcid_fltr_cfg0_srcid_end_srcid_DEFAULT            0x00000000
+
+
+
+
+#define mc2_afx_srcid_fltr_cfg1_srcid_enable_MASK                  0x80000000
+#define mc2_afx_srcid_fltr_cfg1_srcid_enable_ALIGN                 0
+#define mc2_afx_srcid_fltr_cfg1_srcid_enable_BITS                  1
+#define mc2_afx_srcid_fltr_cfg1_srcid_enable_SHIFT                 31
+#define mc2_afx_srcid_fltr_cfg1_srcid_enable_DEFAULT               0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved0_MASK               0x70000000
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved0_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved0_BITS               3
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved0_SHIFT              28
+
+
+#define mc2_afx_srcid_fltr_cfg1_srcid_start_srcid_MASK             0x0fff0000
+#define mc2_afx_srcid_fltr_cfg1_srcid_start_srcid_ALIGN            0
+#define mc2_afx_srcid_fltr_cfg1_srcid_start_srcid_BITS             12
+#define mc2_afx_srcid_fltr_cfg1_srcid_start_srcid_SHIFT            16
+#define mc2_afx_srcid_fltr_cfg1_srcid_start_srcid_DEFAULT          0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved1_MASK               0x0000f000
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved1_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved1_BITS               4
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved1_SHIFT              12
+
+
+#define mc2_afx_srcid_fltr_cfg1_srcid_end_srcid_MASK               0x00000fff
+#define mc2_afx_srcid_fltr_cfg1_srcid_end_srcid_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg1_srcid_end_srcid_BITS               12
+#define mc2_afx_srcid_fltr_cfg1_srcid_end_srcid_SHIFT              0
+#define mc2_afx_srcid_fltr_cfg1_srcid_end_srcid_DEFAULT            0x00000000
+
+
+
+
+#define mc2_afx_srcid_fltr_cfg2_srcid_enable_MASK                  0x80000000
+#define mc2_afx_srcid_fltr_cfg2_srcid_enable_ALIGN                 0
+#define mc2_afx_srcid_fltr_cfg2_srcid_enable_BITS                  1
+#define mc2_afx_srcid_fltr_cfg2_srcid_enable_SHIFT                 31
+#define mc2_afx_srcid_fltr_cfg2_srcid_enable_DEFAULT               0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved0_MASK               0x70000000
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved0_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved0_BITS               3
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved0_SHIFT              28
+
+
+#define mc2_afx_srcid_fltr_cfg2_srcid_start_srcid_MASK             0x0fff0000
+#define mc2_afx_srcid_fltr_cfg2_srcid_start_srcid_ALIGN            0
+#define mc2_afx_srcid_fltr_cfg2_srcid_start_srcid_BITS             12
+#define mc2_afx_srcid_fltr_cfg2_srcid_start_srcid_SHIFT            16
+#define mc2_afx_srcid_fltr_cfg2_srcid_start_srcid_DEFAULT          0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved1_MASK               0x0000f000
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved1_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved1_BITS               4
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved1_SHIFT              12
+
+
+#define mc2_afx_srcid_fltr_cfg2_srcid_end_srcid_MASK               0x00000fff
+#define mc2_afx_srcid_fltr_cfg2_srcid_end_srcid_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg2_srcid_end_srcid_BITS               12
+#define mc2_afx_srcid_fltr_cfg2_srcid_end_srcid_SHIFT              0
+#define mc2_afx_srcid_fltr_cfg2_srcid_end_srcid_DEFAULT            0x00000000
+
+
+
+
+#define mc2_afx_srcid_fltr_cfg3_srcid_enable_MASK                  0x80000000
+#define mc2_afx_srcid_fltr_cfg3_srcid_enable_ALIGN                 0
+#define mc2_afx_srcid_fltr_cfg3_srcid_enable_BITS                  1
+#define mc2_afx_srcid_fltr_cfg3_srcid_enable_SHIFT                 31
+#define mc2_afx_srcid_fltr_cfg3_srcid_enable_DEFAULT               0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved0_MASK               0x70000000
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved0_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved0_BITS               3
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved0_SHIFT              28
+
+
+#define mc2_afx_srcid_fltr_cfg3_srcid_start_srcid_MASK             0x0fff0000
+#define mc2_afx_srcid_fltr_cfg3_srcid_start_srcid_ALIGN            0
+#define mc2_afx_srcid_fltr_cfg3_srcid_start_srcid_BITS             12
+#define mc2_afx_srcid_fltr_cfg3_srcid_start_srcid_SHIFT            16
+#define mc2_afx_srcid_fltr_cfg3_srcid_start_srcid_DEFAULT          0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved1_MASK               0x0000f000
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved1_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved1_BITS               4
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved1_SHIFT              12
+
+
+#define mc2_afx_srcid_fltr_cfg3_srcid_end_srcid_MASK               0x00000fff
+#define mc2_afx_srcid_fltr_cfg3_srcid_end_srcid_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg3_srcid_end_srcid_BITS               12
+#define mc2_afx_srcid_fltr_cfg3_srcid_end_srcid_SHIFT              0
+#define mc2_afx_srcid_fltr_cfg3_srcid_end_srcid_DEFAULT            0x00000000
+
+
+
+
+#define mc2_afx_row_xtr_cfg_row_19_16_reserved0_MASK               0xffffffc0
+#define mc2_afx_row_xtr_cfg_row_19_16_reserved0_ALIGN              0
+#define mc2_afx_row_xtr_cfg_row_19_16_reserved0_BITS               26
+#define mc2_afx_row_xtr_cfg_row_19_16_reserved0_SHIFT              6
+
+
+#define mc2_afx_row_xtr_cfg_row_19_16_bit_16_MASK                  0x0000003f
+#define mc2_afx_row_xtr_cfg_row_19_16_bit_16_ALIGN                 0
+#define mc2_afx_row_xtr_cfg_row_19_16_bit_16_BITS                  6
+#define mc2_afx_row_xtr_cfg_row_19_16_bit_16_SHIFT                 0
+#define mc2_afx_row_xtr_cfg_row_19_16_bit_16_DEFAULT               0x0000001e
+
+
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved0_MASK               0xc0000000
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved0_ALIGN              0
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved0_BITS               2
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved0_SHIFT              30
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_15_MASK                  0x3f000000
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_15_ALIGN                 0
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_15_BITS                  6
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_15_SHIFT                 24
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_15_DEFAULT               0x0000001d
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved1_MASK               0x00c00000
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved1_ALIGN              0
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved1_BITS               2
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved1_SHIFT              22
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_14_MASK                  0x003f0000
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_14_ALIGN                 0
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_14_BITS                  6
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_14_SHIFT                 16
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_14_DEFAULT               0x0000001c
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved2_MASK               0x0000c000
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved2_ALIGN              0
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved2_BITS               2
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved2_SHIFT              14
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_13_MASK                  0x00003f00
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_13_ALIGN                 0
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_13_BITS                  6
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_13_SHIFT                 8
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_13_DEFAULT               0x0000001b
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved3_MASK               0x000000c0
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved3_ALIGN              0
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved3_BITS               2
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved3_SHIFT              6
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_12_MASK                  0x0000003f
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_12_ALIGN                 0
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_12_BITS                  6
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_12_SHIFT                 0
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_12_DEFAULT               0x0000001a
+
+
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved0_MASK                0xc0000000
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved0_ALIGN               0
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved0_BITS                2
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved0_SHIFT               30
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_11_MASK                   0x3f000000
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_11_ALIGN                  0
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_11_BITS                   6
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_11_SHIFT                  24
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_11_DEFAULT                0x00000019
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved1_MASK                0x00c00000
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved1_ALIGN               0
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved1_BITS                2
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved1_SHIFT               22
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_10_MASK                   0x003f0000
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_10_ALIGN                  0
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_10_BITS                   6
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_10_SHIFT                  16
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_10_DEFAULT                0x00000018
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved2_MASK                0x0000c000
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved2_ALIGN               0
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved2_BITS                2
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved2_SHIFT               14
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_9_MASK                    0x00003f00
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_9_ALIGN                   0
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_9_BITS                    6
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_9_SHIFT                   8
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_9_DEFAULT                 0x00000017
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved3_MASK                0x000000c0
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved3_ALIGN               0
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved3_BITS                2
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved3_SHIFT               6
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_8_MASK                    0x0000003f
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_8_ALIGN                   0
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_8_BITS                    6
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_8_SHIFT                   0
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_8_DEFAULT                 0x00000016
+
+
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved0_MASK                 0xc0000000
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved0_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved0_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved0_SHIFT                30
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_7_MASK                     0x3f000000
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_7_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_7_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_7_SHIFT                    24
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_7_DEFAULT                  0x00000015
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved1_MASK                 0x00c00000
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved1_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved1_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved1_SHIFT                22
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_6_MASK                     0x003f0000
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_6_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_6_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_6_SHIFT                    16
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_6_DEFAULT                  0x00000014
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved2_MASK                 0x0000c000
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved2_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved2_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved2_SHIFT                14
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_5_MASK                     0x00003f00
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_5_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_5_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_5_SHIFT                    8
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_5_DEFAULT                  0x00000013
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved3_MASK                 0x000000c0
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved3_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved3_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved3_SHIFT                6
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_4_MASK                     0x0000003f
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_4_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_4_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_4_SHIFT                    0
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_4_DEFAULT                  0x00000012
+
+
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved0_MASK                 0xc0000000
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved0_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved0_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved0_SHIFT                30
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_3_MASK                     0x3f000000
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_3_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_3_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_3_SHIFT                    24
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_3_DEFAULT                  0x00000011
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved1_MASK                 0x00c00000
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved1_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved1_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved1_SHIFT                22
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_2_MASK                     0x003f0000
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_2_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_2_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_2_SHIFT                    16
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_2_DEFAULT                  0x00000010
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved2_MASK                 0x0000c000
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved2_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved2_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved2_SHIFT                14
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_1_MASK                     0x00003f00
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_1_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_1_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_1_SHIFT                    8
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_1_DEFAULT                  0x0000000f
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved3_MASK                 0x000000c0
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved3_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved3_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved3_SHIFT                6
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_0_MASK                     0x0000003f
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_0_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_0_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_0_SHIFT                    0
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_0_DEFAULT                  0x0000000e
+
+
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved0_MASK                   0xc0000000
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved0_ALIGN                  0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved0_BITS                   2
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved0_SHIFT                  30
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_3_MASK                       0x3f000000
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_3_ALIGN                      0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_3_BITS                       6
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_3_SHIFT                      24
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_3_DEFAULT                    0x00000000
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved1_MASK                   0x00c00000
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved1_ALIGN                  0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved1_BITS                   2
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved1_SHIFT                  22
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_2_MASK                       0x003f0000
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_2_ALIGN                      0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_2_BITS                       6
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_2_SHIFT                      16
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_2_DEFAULT                    0x00000000
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved2_MASK                   0x0000c000
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved2_ALIGN                  0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved2_BITS                   2
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved2_SHIFT                  14
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_1_MASK                       0x00003f00
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_1_ALIGN                      0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_1_BITS                       6
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_1_SHIFT                      8
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_1_DEFAULT                    0x00000000
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved3_MASK                   0x000000c0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved3_ALIGN                  0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved3_BITS                   2
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved3_SHIFT                  6
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_0_MASK                       0x0000003f
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_0_ALIGN                      0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_0_BITS                       6
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_0_SHIFT                      0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_0_DEFAULT                    0x00000000
+
+
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved0_MASK                   0xc0000000
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved0_ALIGN                  0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved0_BITS                   2
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved0_SHIFT                  30
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_3_MASK                       0x3f000000
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_3_ALIGN                      0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_3_BITS                       6
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_3_SHIFT                      24
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_3_DEFAULT                    0x00000000
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved1_MASK                   0x00c00000
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved1_ALIGN                  0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved1_BITS                   2
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved1_SHIFT                  22
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_2_MASK                       0x003f0000
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_2_ALIGN                      0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_2_BITS                       6
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_2_SHIFT                      16
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_2_DEFAULT                    0x0000000d
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved2_MASK                   0x0000c000
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved2_ALIGN                  0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved2_BITS                   2
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved2_SHIFT                  14
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_1_MASK                       0x00003f00
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_1_ALIGN                      0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_1_BITS                       6
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_1_SHIFT                      8
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_1_DEFAULT                    0x0000000c
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved3_MASK                   0x000000c0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved3_ALIGN                  0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved3_BITS                   2
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved3_SHIFT                  6
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_0_MASK                       0x0000003f
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_0_ALIGN                      0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_0_BITS                       6
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_0_SHIFT                      0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_0_DEFAULT                    0x0000000b
+
+
+
+
+#define mc2_afx_col_xtr_cfg_col_cfg_reserved0_MASK                 0xffffffc0
+#define mc2_afx_col_xtr_cfg_col_cfg_reserved0_ALIGN                0
+#define mc2_afx_col_xtr_cfg_col_cfg_reserved0_BITS                 26
+#define mc2_afx_col_xtr_cfg_col_cfg_reserved0_SHIFT                6
+
+
+#define mc2_afx_col_xtr_cfg_col_cfg_col_bit_start_MASK             0x00000030
+#define mc2_afx_col_xtr_cfg_col_cfg_col_bit_start_ALIGN            0
+#define mc2_afx_col_xtr_cfg_col_cfg_col_bit_start_BITS             2
+#define mc2_afx_col_xtr_cfg_col_cfg_col_bit_start_SHIFT            4
+#define mc2_afx_col_xtr_cfg_col_cfg_col_bit_start_DEFAULT          0x00000001
+
+
+#define mc2_afx_col_xtr_cfg_col_cfg_col_mode_MASK                  0x0000000c
+#define mc2_afx_col_xtr_cfg_col_cfg_col_mode_ALIGN                 0
+#define mc2_afx_col_xtr_cfg_col_cfg_col_mode_BITS                  2
+#define mc2_afx_col_xtr_cfg_col_cfg_col_mode_SHIFT                 2
+#define mc2_afx_col_xtr_cfg_col_cfg_col_mode_DEFAULT               0x00000000
+
+
+#define mc2_afx_col_xtr_cfg_col_cfg_num_col_bits_MASK              0x00000003
+#define mc2_afx_col_xtr_cfg_col_cfg_num_col_bits_ALIGN             0
+#define mc2_afx_col_xtr_cfg_col_cfg_num_col_bits_BITS              2
+#define mc2_afx_col_xtr_cfg_col_cfg_num_col_bits_SHIFT             0
+#define mc2_afx_col_xtr_cfg_col_cfg_num_col_bits_DEFAULT           0x00000001
+
+
+
+
+#define mc2_afx_cs_xtr_cfg_cs_3_0_enable_MASK                      0x80000000
+#define mc2_afx_cs_xtr_cfg_cs_3_0_enable_ALIGN                     0
+#define mc2_afx_cs_xtr_cfg_cs_3_0_enable_BITS                      1
+#define mc2_afx_cs_xtr_cfg_cs_3_0_enable_SHIFT                     31
+#define mc2_afx_cs_xtr_cfg_cs_3_0_enable_DEFAULT                   0x00000000
+
+
+#define mc2_afx_cs_xtr_cfg_cs_3_0_reserved0_MASK                   0x7fffffc0
+#define mc2_afx_cs_xtr_cfg_cs_3_0_reserved0_ALIGN                  0
+#define mc2_afx_cs_xtr_cfg_cs_3_0_reserved0_BITS                   25
+#define mc2_afx_cs_xtr_cfg_cs_3_0_reserved0_SHIFT                  6
+
+
+#define mc2_afx_cs_xtr_cfg_cs_3_0_bit_0_MASK                       0x0000003f
+#define mc2_afx_cs_xtr_cfg_cs_3_0_bit_0_ALIGN                      0
+#define mc2_afx_cs_xtr_cfg_cs_3_0_bit_0_BITS                       6
+#define mc2_afx_cs_xtr_cfg_cs_3_0_bit_0_SHIFT                      0
+#define mc2_afx_cs_xtr_cfg_cs_3_0_bit_0_DEFAULT                    0x0000000b
+
+
+
+
+#define mc2_afx_chn_xtr_cfg_chn_bit_enable_MASK                    0x80000000
+#define mc2_afx_chn_xtr_cfg_chn_bit_enable_ALIGN                   0
+#define mc2_afx_chn_xtr_cfg_chn_bit_enable_BITS                    1
+#define mc2_afx_chn_xtr_cfg_chn_bit_enable_SHIFT                   31
+#define mc2_afx_chn_xtr_cfg_chn_bit_enable_DEFAULT                 0x00000001
+
+
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved0_MASK                 0x7ffffc00
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved0_ALIGN                0
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved0_BITS                 21
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved0_SHIFT                10
+
+
+#define mc2_afx_chn_xtr_cfg_chn_bit_chn_mode_MASK                  0x00000300
+#define mc2_afx_chn_xtr_cfg_chn_bit_chn_mode_ALIGN                 0
+#define mc2_afx_chn_xtr_cfg_chn_bit_chn_mode_BITS                  2
+#define mc2_afx_chn_xtr_cfg_chn_bit_chn_mode_SHIFT                 8
+#define mc2_afx_chn_xtr_cfg_chn_bit_chn_mode_DEFAULT               0x00000000
+
+
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved1_MASK                 0x000000c0
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved1_ALIGN                0
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved1_BITS                 2
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved1_SHIFT                6
+
+
+#define mc2_afx_chn_xtr_cfg_chn_bit_bit_0_MASK                     0x0000003f
+#define mc2_afx_chn_xtr_cfg_chn_bit_bit_0_ALIGN                    0
+#define mc2_afx_chn_xtr_cfg_chn_bit_bit_0_BITS                     6
+#define mc2_afx_chn_xtr_cfg_chn_bit_bit_0_SHIFT                    0
+#define mc2_afx_chn_xtr_cfg_chn_bit_bit_0_DEFAULT                  0x0000000a
+
+
+
+
+#define mc2_afx_ddr_sz_chk_reserved0_MASK                          0xffffff00
+#define mc2_afx_ddr_sz_chk_reserved0_ALIGN                         0
+#define mc2_afx_ddr_sz_chk_reserved0_BITS                          24
+#define mc2_afx_ddr_sz_chk_reserved0_SHIFT                         8
+
+
+#define mc2_afx_ddr_sz_chk_dram_size_limit_MASK                    0x000000f0
+#define mc2_afx_ddr_sz_chk_dram_size_limit_ALIGN                   0
+#define mc2_afx_ddr_sz_chk_dram_size_limit_BITS                    4
+#define mc2_afx_ddr_sz_chk_dram_size_limit_SHIFT                   4
+#define mc2_afx_ddr_sz_chk_dram_size_limit_DEFAULT                 0x0000000c
+
+
+#define mc2_afx_ddr_sz_chk_reserved1_MASK                          0x0000000f
+#define mc2_afx_ddr_sz_chk_reserved1_ALIGN                         0
+#define mc2_afx_ddr_sz_chk_reserved1_BITS                          4
+#define mc2_afx_ddr_sz_chk_reserved1_SHIFT                         0
+
+
+#define mc2_wbf_acc_acc_eack_MASK                                  0x80000000
+#define mc2_wbf_acc_acc_eack_ALIGN                                 0
+#define mc2_wbf_acc_acc_eack_BITS                                  1
+#define mc2_wbf_acc_acc_eack_SHIFT                                 31
+#define mc2_wbf_acc_acc_eack_DEFAULT                               0x00000000
+
+
+#define mc2_wbf_acc_reserved0_MASK                                 0x7fffff00
+#define mc2_wbf_acc_reserved0_ALIGN                                0
+#define mc2_wbf_acc_reserved0_BITS                                 23
+#define mc2_wbf_acc_reserved0_SHIFT                                8
+
+
+#define mc2_wbf_acc_acc_sw_MASK                                    0x00000080
+#define mc2_wbf_acc_acc_sw_ALIGN                                   0
+#define mc2_wbf_acc_acc_sw_BITS                                    1
+#define mc2_wbf_acc_acc_sw_SHIFT                                   7
+#define mc2_wbf_acc_acc_sw_DEFAULT                                 0x00000001
+
+
+#define mc2_wbf_acc_acc_sr_MASK                                    0x00000040
+#define mc2_wbf_acc_acc_sr_ALIGN                                   0
+#define mc2_wbf_acc_acc_sr_BITS                                    1
+#define mc2_wbf_acc_acc_sr_SHIFT                                   6
+#define mc2_wbf_acc_acc_sr_DEFAULT                                 0x00000001
+
+
+#define mc2_wbf_acc_acc_nsw_MASK                                   0x00000020
+#define mc2_wbf_acc_acc_nsw_ALIGN                                  0
+#define mc2_wbf_acc_acc_nsw_BITS                                   1
+#define mc2_wbf_acc_acc_nsw_SHIFT                                  5
+#define mc2_wbf_acc_acc_nsw_DEFAULT                                0x00000001
+
+
+#define mc2_wbf_acc_acc_nsr_MASK                                   0x00000010
+#define mc2_wbf_acc_acc_nsr_ALIGN                                  0
+#define mc2_wbf_acc_acc_nsr_BITS                                   1
+#define mc2_wbf_acc_acc_nsr_SHIFT                                  4
+#define mc2_wbf_acc_acc_nsr_DEFAULT                                0x00000001
+
+
+#define mc2_wbf_acc_perm_sw_MASK                                   0x00000008
+#define mc2_wbf_acc_perm_sw_ALIGN                                  0
+#define mc2_wbf_acc_perm_sw_BITS                                   1
+#define mc2_wbf_acc_perm_sw_SHIFT                                  3
+#define mc2_wbf_acc_perm_sw_DEFAULT                                0x00000001
+
+
+#define mc2_wbf_acc_perm_sr_MASK                                   0x00000004
+#define mc2_wbf_acc_perm_sr_ALIGN                                  0
+#define mc2_wbf_acc_perm_sr_BITS                                   1
+#define mc2_wbf_acc_perm_sr_SHIFT                                  2
+#define mc2_wbf_acc_perm_sr_DEFAULT                                0x00000001
+
+
+#define mc2_wbf_acc_perm_nsw_MASK                                  0x00000002
+#define mc2_wbf_acc_perm_nsw_ALIGN                                 0
+#define mc2_wbf_acc_perm_nsw_BITS                                  1
+#define mc2_wbf_acc_perm_nsw_SHIFT                                 1
+#define mc2_wbf_acc_perm_nsw_DEFAULT                               0x00000001
+
+
+#define mc2_wbf_acc_perm_nsr_MASK                                  0x00000001
+#define mc2_wbf_acc_perm_nsr_ALIGN                                 0
+#define mc2_wbf_acc_perm_nsr_BITS                                  1
+#define mc2_wbf_acc_perm_nsr_SHIFT                                 0
+#define mc2_wbf_acc_perm_nsr_DEFAULT                               0x00000001
+
+
+
+
+#define mc2_wbf_ver_reserved0_MASK                                 0xffffff00
+#define mc2_wbf_ver_reserved0_ALIGN                                0
+#define mc2_wbf_ver_reserved0_BITS                                 24
+#define mc2_wbf_ver_reserved0_SHIFT                                8
+
+
+#define mc2_wbf_ver_version_MASK                                   0x000000ff
+#define mc2_wbf_ver_version_ALIGN                                  0
+#define mc2_wbf_ver_version_BITS                                   8
+#define mc2_wbf_ver_version_SHIFT                                  0
+#define mc2_wbf_ver_version_DEFAULT                                0x00000000
+
+
+
+
+#define mc2_wbf_pri_cfg_wbf_en_MASK                                0x80000000
+#define mc2_wbf_pri_cfg_wbf_en_ALIGN                               0
+#define mc2_wbf_pri_cfg_wbf_en_BITS                                1
+#define mc2_wbf_pri_cfg_wbf_en_SHIFT                               31
+#define mc2_wbf_pri_cfg_wbf_en_DEFAULT                             0x00000000
+
+
+#define mc2_wbf_pri_cfg_reserved0_MASK                             0x70000000
+#define mc2_wbf_pri_cfg_reserved0_ALIGN                            0
+#define mc2_wbf_pri_cfg_reserved0_BITS                             3
+#define mc2_wbf_pri_cfg_reserved0_SHIFT                            28
+
+
+#define mc2_wbf_pri_cfg_prefetch_en_MASK                           0x0f000000
+#define mc2_wbf_pri_cfg_prefetch_en_ALIGN                          0
+#define mc2_wbf_pri_cfg_prefetch_en_BITS                           4
+#define mc2_wbf_pri_cfg_prefetch_en_SHIFT                          24
+#define mc2_wbf_pri_cfg_prefetch_en_DEFAULT                        0x00000000
+
+
+#define mc2_wbf_pri_cfg_reserved1_MASK                             0x00e00000
+#define mc2_wbf_pri_cfg_reserved1_ALIGN                            0
+#define mc2_wbf_pri_cfg_reserved1_BITS                             3
+#define mc2_wbf_pri_cfg_reserved1_SHIFT                            21
+
+
+#define mc2_wbf_pri_cfg_wbf_pslc_buf_mode_MASK                     0x00100000
+#define mc2_wbf_pri_cfg_wbf_pslc_buf_mode_ALIGN                    0
+#define mc2_wbf_pri_cfg_wbf_pslc_buf_mode_BITS                     1
+#define mc2_wbf_pri_cfg_wbf_pslc_buf_mode_SHIFT                    20
+#define mc2_wbf_pri_cfg_wbf_pslc_buf_mode_DEFAULT                  0x00000000
+
+
+#define mc2_wbf_pri_cfg_high_pri_chn_MASK                          0x000f0000
+#define mc2_wbf_pri_cfg_high_pri_chn_ALIGN                         0
+#define mc2_wbf_pri_cfg_high_pri_chn_BITS                          4
+#define mc2_wbf_pri_cfg_high_pri_chn_SHIFT                         16
+#define mc2_wbf_pri_cfg_high_pri_chn_DEFAULT                       0x00000003
+
+
+#define mc2_wbf_pri_cfg_reserved2_MASK                             0x0000fff0
+#define mc2_wbf_pri_cfg_reserved2_ALIGN                            0
+#define mc2_wbf_pri_cfg_reserved2_BITS                             12
+#define mc2_wbf_pri_cfg_reserved2_SHIFT                            4
+
+
+#define mc2_wbf_pri_cfg_high_pri_ifm_MASK                          0x0000000f
+#define mc2_wbf_pri_cfg_high_pri_ifm_ALIGN                         0
+#define mc2_wbf_pri_cfg_high_pri_ifm_BITS                          4
+#define mc2_wbf_pri_cfg_high_pri_ifm_SHIFT                         0
+#define mc2_wbf_pri_cfg_high_pri_ifm_DEFAULT                       0x00000003
+
+
+
+
+#define mc2_wbf_sta_bq_full_MASK                                   0x80000000
+#define mc2_wbf_sta_bq_full_ALIGN                                  0
+#define mc2_wbf_sta_bq_full_BITS                                   1
+#define mc2_wbf_sta_bq_full_SHIFT                                  31
+
+
+#define mc2_wbf_sta_bq_empty_MASK                                  0x40000000
+#define mc2_wbf_sta_bq_empty_ALIGN                                 0
+#define mc2_wbf_sta_bq_empty_BITS                                  1
+#define mc2_wbf_sta_bq_empty_SHIFT                                 30
+
+
+#define mc2_wbf_sta_reserved0_MASK                                 0x3ffc0000
+#define mc2_wbf_sta_reserved0_ALIGN                                0
+#define mc2_wbf_sta_reserved0_BITS                                 12
+#define mc2_wbf_sta_reserved0_SHIFT                                18
+
+
+#define mc2_wbf_sta_wbf_buf_level_MASK                             0x0003ff00
+#define mc2_wbf_sta_wbf_buf_level_ALIGN                            0
+#define mc2_wbf_sta_wbf_buf_level_BITS                             10
+#define mc2_wbf_sta_wbf_buf_level_SHIFT                            8
+
+
+#define mc2_wbf_sta_bq_count_MASK                                  0x000000ff
+#define mc2_wbf_sta_bq_count_ALIGN                                 0
+#define mc2_wbf_sta_bq_count_BITS                                  8
+#define mc2_wbf_sta_bq_count_SHIFT                                 0
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_go_MASK                         0x80000000
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_go_ALIGN                        0
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_go_BITS                         1
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_go_SHIFT                        31
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_go_DEFAULT                      0x00000000
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wr_MASK                         0x40000000
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wr_ALIGN                        0
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wr_BITS                         1
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wr_SHIFT                        30
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wr_DEFAULT                      0x00000000
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_reserved0_MASK                       0x3ff80000
+#define mc2_wbf_bkdr_bkdr_cmd_reserved0_ALIGN                      0
+#define mc2_wbf_bkdr_bkdr_cmd_reserved0_BITS                       11
+#define mc2_wbf_bkdr_bkdr_cmd_reserved0_SHIFT                      19
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_slice_MASK                      0x00070000
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_slice_ALIGN                     0
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_slice_BITS                      3
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_slice_SHIFT                     16
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_pslc_wbf_buf_sel_MASK                0x0000ff00
+#define mc2_wbf_bkdr_bkdr_cmd_pslc_wbf_buf_sel_ALIGN               0
+#define mc2_wbf_bkdr_bkdr_cmd_pslc_wbf_buf_sel_BITS                8
+#define mc2_wbf_bkdr_bkdr_cmd_pslc_wbf_buf_sel_SHIFT               8
+#define mc2_wbf_bkdr_bkdr_cmd_pslc_wbf_buf_sel_DEFAULT             0x00000000
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wbf_id_MASK                     0x000000ff
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wbf_id_ALIGN                    0
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wbf_id_BITS                     8
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wbf_id_SHIFT                    0
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wbf_id_DEFAULT                  0x00000000
+
+
+
+#define mc2_wbf_bkdr_bkdr_datai_ARRAY_BASE                         0x00000e94
+#define mc2_wbf_bkdr_bkdr_datai_ARRAY_START                        0
+#define mc2_wbf_bkdr_bkdr_datai_ARRAY_END                          7
+#define mc2_wbf_bkdr_bkdr_datai_ARRAY_ELEMENT_SIZE                 32
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_datai_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_datai_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_datai_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_datai_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_datai_data_DEFAULT                       0x00000000
+
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data0_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data0_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data0_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data0_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data0_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data1_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data1_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data1_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data1_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data1_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data2_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data2_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data2_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data2_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data2_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data3_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data3_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data3_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data3_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data3_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data4_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data4_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data4_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data4_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data4_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data5_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data5_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data5_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data5_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data5_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data6_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data6_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data6_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data6_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data6_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data7_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data7_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data7_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data7_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data7_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_id_bkdr_id_cmd_id_freeze_MASK                      0x80000000
+#define mc2_wbf_id_bkdr_id_cmd_id_freeze_ALIGN                     0
+#define mc2_wbf_id_bkdr_id_cmd_id_freeze_BITS                      1
+#define mc2_wbf_id_bkdr_id_cmd_id_freeze_SHIFT                     31
+#define mc2_wbf_id_bkdr_id_cmd_id_freeze_DEFAULT                   0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_cmd_reserved0_MASK                      0x70000000
+#define mc2_wbf_id_bkdr_id_cmd_reserved0_ALIGN                     0
+#define mc2_wbf_id_bkdr_id_cmd_reserved0_BITS                      3
+#define mc2_wbf_id_bkdr_id_cmd_reserved0_SHIFT                     28
+
+
+#define mc2_wbf_id_bkdr_id_cmd_id_go_MASK                          0x0f000000
+#define mc2_wbf_id_bkdr_id_cmd_id_go_ALIGN                         0
+#define mc2_wbf_id_bkdr_id_cmd_id_go_BITS                          4
+#define mc2_wbf_id_bkdr_id_cmd_id_go_SHIFT                         24
+#define mc2_wbf_id_bkdr_id_cmd_id_go_DEFAULT                       0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_cmd_reserved1_MASK                      0x00fe0000
+#define mc2_wbf_id_bkdr_id_cmd_reserved1_ALIGN                     0
+#define mc2_wbf_id_bkdr_id_cmd_reserved1_BITS                      7
+#define mc2_wbf_id_bkdr_id_cmd_reserved1_SHIFT                     17
+
+
+#define mc2_wbf_id_bkdr_id_cmd_id_wr_MASK                          0x00010000
+#define mc2_wbf_id_bkdr_id_cmd_id_wr_ALIGN                         0
+#define mc2_wbf_id_bkdr_id_cmd_id_wr_BITS                          1
+#define mc2_wbf_id_bkdr_id_cmd_id_wr_SHIFT                         16
+#define mc2_wbf_id_bkdr_id_cmd_id_wr_DEFAULT                       0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_cmd_reserved2_MASK                      0x0000ff00
+#define mc2_wbf_id_bkdr_id_cmd_reserved2_ALIGN                     0
+#define mc2_wbf_id_bkdr_id_cmd_reserved2_BITS                      8
+#define mc2_wbf_id_bkdr_id_cmd_reserved2_SHIFT                     8
+
+
+#define mc2_wbf_id_bkdr_id_cmd_id_addr_MASK                        0x000000ff
+#define mc2_wbf_id_bkdr_id_cmd_id_addr_ALIGN                       0
+#define mc2_wbf_id_bkdr_id_cmd_id_addr_BITS                        8
+#define mc2_wbf_id_bkdr_id_cmd_id_addr_SHIFT                       0
+#define mc2_wbf_id_bkdr_id_cmd_id_addr_DEFAULT                     0x00000000
+
+
+
+
+#define mc2_wbf_id_bkdr_id_data_wbf_id_wr_ptr_MASK                 0xff000000
+#define mc2_wbf_id_bkdr_id_data_wbf_id_wr_ptr_ALIGN                0
+#define mc2_wbf_id_bkdr_id_data_wbf_id_wr_ptr_BITS                 8
+#define mc2_wbf_id_bkdr_id_data_wbf_id_wr_ptr_SHIFT                24
+#define mc2_wbf_id_bkdr_id_data_wbf_id_wr_ptr_DEFAULT              0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_data_wbf_id_rd_ptr_MASK                 0x00ff0000
+#define mc2_wbf_id_bkdr_id_data_wbf_id_rd_ptr_ALIGN                0
+#define mc2_wbf_id_bkdr_id_data_wbf_id_rd_ptr_BITS                 8
+#define mc2_wbf_id_bkdr_id_data_wbf_id_rd_ptr_SHIFT                16
+#define mc2_wbf_id_bkdr_id_data_wbf_id_rd_ptr_DEFAULT              0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_data_bq_count_wr_MASK                   0x0000ff00
+#define mc2_wbf_id_bkdr_id_data_bq_count_wr_ALIGN                  0
+#define mc2_wbf_id_bkdr_id_data_bq_count_wr_BITS                   8
+#define mc2_wbf_id_bkdr_id_data_bq_count_wr_SHIFT                  8
+#define mc2_wbf_id_bkdr_id_data_bq_count_wr_DEFAULT                0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_data_wbf_id_MASK                        0x000000ff
+#define mc2_wbf_id_bkdr_id_data_wbf_id_ALIGN                       0
+#define mc2_wbf_id_bkdr_id_data_wbf_id_BITS                        8
+#define mc2_wbf_id_bkdr_id_data_wbf_id_SHIFT                       0
+#define mc2_wbf_id_bkdr_id_data_wbf_id_DEFAULT                     0x00000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4912/misc.h b/arch/arm/include/asm/arch-bcm4912/misc.h
new file mode 100644
index 0000000000..c493dbf409
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/misc.h
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4912_MISC_H
+#define _4912_MISC_H
+
+#define MISC_BASE          0xff802600
+
+/*
+ * Misc Register Set Definitions.
+ */
+typedef struct Misc {
+   uint32_t miscStrapBus; /* 0x00 */
+
+    /* boot select bits 3-5 */
+#define BOOT_SEL_STRAP_NAND_2K_PAGE             0x00
+#define BOOT_SEL_STRAP_NAND_4K_PAGE             0x08
+#define BOOT_SEL_STRAP_NAND_8K_PAGE             0x10
+#define BOOT_SEL_STRAP_NAND_512B_PAGE           0x18
+#define BOOT_SEL_STRAP_SPI_NOR                  0x38
+#define BOOT_SEL_STRAP_EMMC                     0x30
+#define BOOT_SEL_STRAP_SPI_NAND                 0x28
+
+#define BOOT_SEL_STRAP_BOOT_SEL_MASK            (0x38)
+#define BOOT_SEL_STRAP_PAGE_SIZE_MASK           (0x7)
+
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           0
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_PCIE3_RC_MODE            (0x1 << 6)
+#define MISC_STRAP_BUS_LS_SPI_SLAVE_DISABLE     (0x1 << 7)
+#define MISC_STRAP_BUS_B53_BOOT_N               (0x1 << 8)
+#define MISC_STRAP_BUS_RESET_OUT_DELAY          (0x1 << 9)
+/* When ROM BOOT OTP bits are 2b'11, always boot rom secure boot, this strap bit is don't care.
+   When ROM BOOT OTP bits are are not 2b'11, this trap bit determine the following:
+   1: boot rom non-secure boot
+   0: XIP boot
+*/
+#define MISC_STRAP_BUS_BOOTROM_BOOT             (0x1 << 12)
+#define MISC_STRAP_BUS_SW_RESERVE_MASK          (0x3 << 13)
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT      16
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ            (0x1 << MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT)
+   uint32_t miscStrapOverride;     /* 0x04 */
+   uint32_t miscMaskUBUSErr;       /* 0x08 */
+   uint32_t miscPeriphCtrl;        /* 0x0c */
+   uint32_t miscSpiMasterCtrl;     /* 0x10 */
+   uint32_t reserved0;             /* 0x14 */
+   uint32_t miscPeriphMiscCtrl;    /* 0x18 */
+   uint32_t miscPeriphMiscStat;    /* 0x1c */
+   uint32_t miscSoftResetB;        /* 0x20 */
+   uint32_t miscSpare0;            /* 0x24 */
+   uint32_t miscSWdebugNW[2];      /* 0x28 */
+   uint32_t miscWDResetCtrl;       /* 0x30 */
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+
+/*
+ * Gpio Controller
+ */
+typedef struct GpioControl {
+        uint32_t GPIODir[8];             /* 0x00-0x1f */
+        uint32_t GPIOio[8];              /* 0x20-0x3f */
+        uint32_t PadCtrl;                 /* 0x40 */
+        uint32_t SpiSlaveCfg;             /* 0x44 */
+        uint32_t TestControl;             /* 0x48 */
+        uint32_t TestPortBlockEnMSB;      /* 0x4c */
+        uint32_t TestPortBlockEnLSB;      /* 0x50 */
+        uint32_t TestPortBlockDataMSB;    /* 0x54 */
+        uint32_t TestPortBlockDataLSB;    /* 0x58 */
+        uint32_t TestPortCmd;             /* 0x5c */
+        uint32_t DiagReadBack;            /* 0x60 */
+        uint32_t DiagReadBackHi;          /* 0x64 */
+        uint32_t GeneralPurpose;          /* 0x68 */
+        uint32_t spare[3];
+} GpioControl;
+
+#define GPIO_BASE              0xff800500
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+#define PINCTRL_BASE           (GPIO_BASE + 0x54)
+
+/*
+ * Peripheral Controller
+ */
+typedef struct DMAIrqCfg {
+   uint32_t DMAIrqStatus;       /* 0x00 */
+   uint32_t DMAIrqSet;          /* 0x04 */
+   uint32_t DMAIrqClear;        /* 0x08 */
+   uint32_t DMAIrqMaskStatus;   /* 0x0c */
+   uint32_t DMAIrqMaskSet;      /* 0x10 */
+   uint32_t DMAIrqMaskClear;    /* 0x14 */
+}DMAIrqCfg;
+
+typedef struct PerfControl {
+   uint32_t RevID;        /* 0x00 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xfff
+   uint32_t reserved0[7]; /* 0x04 - 0x1f */
+   uint32_t ExtIrqCtrl;   /* 0x20 */
+#define EI_LVLSTICKY_SHFT   0
+#define EI_SENSE_SHFT   8
+#define EI_INSENS_SHFT  16
+#define EI_LEVEL_SHFT   24
+   uint32_t ExtIrqStatus;  /* 0x24 */
+#define EI_STATUS_SHFT  0
+#define EI_STATUS_MASK  0xff
+   uint32_t ExtIrqSet;     /* 0x28 */
+   uint32_t ExtIrqClear;   /* 0x2c */
+   uint32_t ExtIrqMaskStatus;/* 0x30 */
+   uint32_t ExtIrqMaskSet; /* 0x34 */
+   uint32_t ExtIrqMaskClear; /* 0x38 */
+   uint32_t reserved1[2]; /* 0x3c - 0x43 */
+   uint32_t ExtIrqMuxSel0; /* 0x44 */
+#define EXT_IRQ_SLOT_SIZE             16
+#define EXT_IRQ_MUX_SEL0_SHIFT        4
+#define EXT_IRQ_MUX_SEL0_MASK         0xf
+   uint32_t ExtIrqMuxSel1;   /* 0x48 */
+#define EXT_IRQ_MUX_SEL1_SHIFT        4
+#define EXT_IRQ_MUX_SEL1_MASK         0xf
+   uint32_t IrqPeriphStatus; /* 0x4c */
+   uint32_t IrqPeriphMask;   /* 0x50 */
+   uint32_t reserved2[8];    /* 0x54 - 0x73 */  
+   DMAIrqCfg dmaIrqCfg[3]; /* 0x74 - 0xbb */
+} PerfControl;
+
+#define PERF_BASE	0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4912/otp.h b/arch/arm/include/asm/arch-bcm4912/otp.h
new file mode 100644
index 0000000000..d7006a965a
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/otp.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _4912_OTP_H
+#define _4912_OTP_H
+
+#define JTAG_OTP_BASE    0xff802800
+
+/* row 9 */
+#define OTP_CPU_CLOCK_FREQ_ROW                  9
+#define OTP_CPU_CLOCK_FREQ_SHIFT                0
+#define OTP_CPU_CLOCK_FREQ_MASK                 0x7
+
+/* row 8 */
+#define OTP_CPU_CORE_CFG_ROW                    8
+#define OTP_CPU_CORE_CFG_SHIFT                  28
+#define OTP_CPU_CORE_CFG_MASK                   0x1 // 0=dual cores, 1=single core
+
+/* row 14 */
+#define OTP_JTAG_CUST_LOCK_ROW			0xff	
+#define OTP_JTAG_CUST_LOCK_MASK			0x1
+#define OTP_JTAG_CUST_LOCK_REG_SHIFT		25
+
+/* row 13 */
+#define OTP_BRCM_PRODUCTION_MODE_ROW       	13
+#define OTP_BRCM_PRODUCTION_MODE_SHIFT     	0
+#define OTP_BRCM_PRODUCTION_MODE_MASK      	0x1
+
+/* row 13 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           13
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         2
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+/* row 14 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           14
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         28
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          0x1 
+
+/* row 14 */
+#define OTP_CUST_BTRM_UART_DISABLE_ROW          14
+#define OTP_CUST_BTRM_UART_DISABLE_SHIFT        0
+#define OTP_CUST_BTRM_UART_DISABLE_MASK         1
+
+/* row 14 */
+#define OTP_CUST_BTRM_MSG_DISABLE_ROW           14
+#define OTP_CUST_BTRM_MSG_DISABLE_SHIFT         27
+#define OTP_CUST_BTRM_MSG_DISABLE_MASK          1
+
+/* row 29 */
+#define OTP_CUST_MFG_MRKTID_ROW                 29
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_BRCM_PRODUCTION_MODE, OTP_BRCM_PRODUCTION_MODE_ROW, OTP_BRCM_PRODUCTION_MODE_MASK, OTP_BRCM_PRODUCTION_MODE_SHIFT, 1},				\
+	}
+#endif
+
diff --git a/arch/arm/include/asm/arch-bcm4912/pmc.h b/arch/arm/include/asm/arch-bcm4912/pmc.h
new file mode 100644
index 0000000000..5343066fc2
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/pmc.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4912_PMC_H
+#define _4912_PMC_H 
+
+#define PMC_BASE         0xFFB00000
+#define PMC ((volatile Pmc * const)PMC_BASE)
+
+#define PMB_BASE         0xFFB20100
+#define PMB ((volatile PMBMaster * const)PMB_BASE)
+
+#define PROC_MON_BASE   0xFFB00000
+#define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
+
+typedef struct PmcCtrlReg {
+    uint32_t gpTmr0Ctl;           /* 0x018 */
+    uint32_t gpTmr0Cnt;           /* 0x01c */
+    uint32_t gpTmr1Ctl;           /* 0x020 */
+    uint32_t gpTmr1Cnt;           /* 0x024 */
+    uint32_t hostMboxIn;          /* 0x028 */
+    uint32_t hostMboxOut;         /* 0x02c */
+    uint32_t reserved[4];         /* 0x030 */
+    uint32_t dmaCtrl;             /* 0x040 */
+    uint32_t dmaStatus;           /* 0x044 */
+    uint32_t dma0_3FifoStatus;    /* 0x048 */
+    uint32_t reserved1[4];	    /* 0x04c */
+    uint32_t diagControl;         /* 0x05c */
+    uint32_t diagHigh;            /* 0x060 */
+    uint32_t diagLow;             /* 0x064 */
+    uint32_t reserved8;           /* 0x068 */
+    uint32_t addr1WndwMask;       /* 0x06c */
+    uint32_t addr1WndwBaseIn;     /* 0x070 */
+    uint32_t addr1WndwBaseOut;    /* 0x074 */
+    uint32_t addr2WndwMask;       /* 0x078 */
+    uint32_t addr2WndwBaseIn;     /* 0x07c */
+    uint32_t addr2WndwBaseOut;    /* 0x080 */
+    uint32_t scratch;             /* 0x084 */
+    uint32_t reserved9;           /* 0x088 */
+    uint32_t softResets;          /* 0x08c */
+    uint32_t reserved2;           /* 0x090 */
+    uint32_t m4keCoreStatus;      /* 0x094 */
+    uint32_t reserved3;           /* 0x098 */
+    uint32_t ubSlaveTimeout;      /* 0x09c */
+    uint32_t diagEn;              /* 0x0a0 */
+    uint32_t devTimeout;          /* 0x0a4 */
+    uint32_t ubusErrorOutMask;    /* 0x0a8 */
+    uint32_t diagCaptStopMask;    /* 0x0ac */
+    uint32_t revId;               /* 0x0b0 */
+    uint32_t reserved4[4];        /* 0x0b4 */
+    uint32_t diagCtrl;            /* 0x0c4 */
+    uint32_t diagStat;            /* 0x0c8 */
+    uint32_t diagMask;            /* 0x0cc */
+    uint32_t diagRslt;            /* 0x0d0 */
+    uint32_t diagCmp;             /* 0x0d4 */
+    uint32_t diagCapt;            /* 0x0d8 */    
+    uint32_t diagCnt;             /* 0x0dc */
+    uint32_t diagEdgeCnt;         /* 0x0e0 */
+    uint32_t reserved5[4];	    /* 0x0e4 */
+    uint32_t smisc_bus_config;    /* 0x0f4 */
+    uint32_t lfsr;                /* 0x0f8 */
+    uint32_t dqm_pac_lock;        /* 0x0fc */
+    uint32_t l1_irq_4ke_mask;     /* 0x100 */
+    uint32_t l1_irq_4ke_status;   /* 0x104 */
+    uint32_t l1_irq_mips_mask;    /* 0x108 */
+    uint32_t l1_irq_mips_status;  /* 0x10c */
+    uint32_t l1_irq_mips1_mask;   /* 0x110 */
+    uint32_t reserved6[3];        /* 0x114 */
+    uint32_t l2_irq_gp_mask;      /* 0x120 */
+    uint32_t l2_irq_gp_status;    /* 0x124 */
+    uint32_t l2_irq_gp_set;       /* 0x128 */
+    uint32_t reserved7;           /* 0x12c */
+    uint32_t gp_in_irq_mask;      /* 0x130 */
+    uint32_t gp_in_irq_status;    /* 0x134 */
+    uint32_t gp_in_irq_set;       /* 0x138 */
+    uint32_t gp_in_irq_sense;     /* 0x13c */
+    uint32_t gp_in;               /* 0x140 */
+    uint32_t gp_out;              /* 0x144 */
+} PmcCtrlReg;
+
+typedef struct PmcDmaReg {
+	/* 0x00 */
+	uint32_t src;
+	uint32_t dest;
+	uint32_t cmdList;
+	uint32_t lenCtl;
+	/* 0x10 */
+	uint32_t rsltSrc;
+	uint32_t rsltDest;
+	uint32_t rsltHcs;
+	uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+	/* 0x00 */
+	uint32_t bufSize;
+	uint32_t bufBase;
+	uint32_t idx2ptrIdx;
+	uint32_t idx2ptrPtr;
+	/* 0x10 */
+	uint32_t unused[2];
+	uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+	uint32_t freqScalarCtrl; /* 0x3c */
+	uint32_t freqScalarMask; /* 0x40 */
+} PmcPerfPowReg;
+
+typedef struct PmcDQMPac {
+    uint32_t dqmPac[32];
+} PmcDQMPac;
+
+typedef struct PmcDQMReg {
+	uint32_t cfg;                     /* 0x1c00 */
+	uint32_t _4keLowWtmkIrqMask;      /* 0x1c04 */
+	uint32_t mipsLowWtmkIrqMask;      /* 0x1c08 */
+	uint32_t lowWtmkIrqMask;          /* 0x1c0c */
+	uint32_t _4keNotEmptyIrqMask;     /* 0x1c10 */
+	uint32_t mipsNotEmptyIrqMask;     /* 0x1c14 */
+	uint32_t notEmptyIrqSts;          /* 0x1c18 */
+	uint32_t queueRst;                /* 0x1c1c */
+	uint32_t notEmptySts;             /* 0x1c20 */
+	uint32_t nextAvailMask;           /* 0x1c24 */
+	uint32_t nextAvailQueue;          /* 0x1c28 */
+	uint32_t mips1LowWtmkIrqMask;     /* 0x1c2c */
+	uint32_t mips1NotEmptyIrqMask;    /* 0x1c30 */
+	uint32_t autoSrcPidInsert;        /* 0x1c34 */
+    uint32_t timerIrqStatus;          /* 0x1c38 */
+    uint32_t timerStatus;             /* 0x1c3c */
+    uint32_t _4keTimerIrqMask;        /* 0x1c40 */
+    uint32_t mipsTimerIrqMask;        /* 0x1c44 */
+    uint32_t mips1TimerIrqMask;       /* 0x1c48 */
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+	uint32_t cntr[10];
+	uint32_t unused[6];	/* 0x28-0x3f */
+	uint32_t cntrIrqMask;
+	uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+	uint32_t size;
+	uint32_t cfga;
+	uint32_t cfgb;
+	uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+	uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+	uint32_t qNumFull[32];
+	uint32_t qNumEmpty[32];
+	uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+typedef struct SSBMaster {
+    uint32_t ssbmControl;     /* 0x0060 */
+    uint32_t ssbmWrData;      /* 0x0064 */
+    uint32_t ssbmRdData;      /* 0x0068 */
+    uint32_t ssbmStatus;      /* 0x006c */
+} SSBMaster;
+
+typedef struct PmmReg {
+    uint32_t memPowerCtrl;            /* 0x0000 */
+    uint32_t regSecurityConfig;       /* 0x0004 */
+} PmmReg;
+
+typedef struct keyholeReg {
+    uint32_t ctrlSts;
+    uint32_t wrData;
+    uint32_t mutex;
+    uint32_t rdData;
+} keyholeReg;
+
+typedef struct PmbBus {
+    uint32_t config;          /* 0x0100 */
+    uint32_t arbiter;         /* 0x0104 */
+    uint32_t timeout;         /* 0x0108 */
+    uint32_t unused1;         /* 0x010c */
+    keyholeReg keyhole[4];  /* 0x0110-0x014f */
+    uint32_t unused2[44];     /* 0x0150-0x01ff */
+    uint32_t map[64];         /* 0x0200-0x02ff */ 
+}PmbBus;
+
+typedef struct  CoreCtrl {
+    uint32_t  coreEnable;         /* 0x0400 */
+    uint32_t  autoresetControl;   /* 0x0404 */
+    uint32_t  coreIdle;           /* 0x0408 */
+    uint32_t  coreResetCause;     /* 0x040c */
+    uint32_t  memPwrDownCtrl0;    /* 0x0410 */
+    uint32_t  memPwrDownSts0;     /* 0x0414 */
+    uint32_t  memPwrDownCtrl1;    /* 0x0418 */
+    uint32_t  memPwrDownSts1;     /* 0x041c */
+    uint32_t  sysFlg0Status;      /* 0x0420 */
+    uint32_t  sysFlg0Set;         /* 0x0424 */
+    uint32_t  sysFlg0Clear;       /* 0x0428 */
+    uint32_t  unused1;            /* 0x042c */
+    uint32_t  usrFlg0Status;      /* 0x0430 */
+    uint32_t  usrFlg0Set;         /* 0x0434 */
+    uint32_t  usrFlg0Clear;       /* 0x0438 */
+    uint32_t  unused2;            /* 0x043c */
+    uint32_t  subsystemRev;       /* 0x0440 */
+    uint32_t  resetVector;        /* 0x0444 */
+} CoreCtrl;
+
+typedef struct  CoreState {
+    uint32_t  sysMbx[8];          /* 0x0480 */
+    uint32_t  usrMbx[8];          /* 0x04a0 */
+    uint32_t  sysMtx[4];          /* 0x04c0 */
+    uint32_t  usrMtx[8];          /* 0x04d0 */
+} CoreState;
+
+typedef struct  CoreIntr {
+    uint32_t  irqStatus;          /* 0x0500 */
+    uint32_t  irqSet;             /* 0x0504 */
+    uint32_t  irqClear;           /* 0x0508 */
+    uint32_t  unused1;            /* 0x050c */
+    uint32_t  srqStatus;          /* 0x0510 */
+    uint32_t  srqSet;             /* 0x0514 */
+    uint32_t  srqClear;           /* 0x0518 */
+    uint32_t  unused2;            /* 0x051c */
+    uint32_t  drqStatus;          /* 0x0520 */
+    uint32_t  drqSet;             /* 0x0524 */
+    uint32_t  drqClear;           /* 0x0528 */
+    uint32_t  unused3;            /* 0x052c */
+    uint32_t  frqStatus;          /* 0x0530 */
+    uint32_t  frqSet;             /* 0x0534 */
+    uint32_t  frqClear;           /* 0x0538 */
+    uint32_t  unused4;            /* 0x053c */
+    uint32_t  hostIrqLatched;     /* 0x0540 */
+    uint32_t  hostIrqSet;         /* 0x0544 */
+    uint32_t  hostIrqClear;       /* 0x0548 */
+    uint32_t  hostIrqEnable;      /* 0x054c */
+    uint32_t  obusFaultStatus;    /* 0x0550 */
+    uint32_t  obusFaultClear;     /* 0x0554 */
+    uint32_t  obusFaultAddr;      /* 0x0558 */
+} CoreIntr;
+
+typedef struct CoreProfile {
+    uint32_t  mutex;              /* 0x0580 */
+    uint32_t  lastConfPcLo;       /* 0x0584 */
+    uint32_t  lastConfPcHi;       /* 0x0588 */
+    uint32_t  lastPcLo;           /* 0x058c */
+    uint32_t  lastPcHi;           /* 0x0590 */
+    uint32_t  braTargetPc0Lo;     /* 0x0594 */
+    uint32_t  braTargetPc0Hi;     /* 0x0598 */
+    uint32_t  braTargetPc1Lo;     /* 0x059c */
+    uint32_t  braTargetPc1Hi;     /* 0x05a0 */
+    uint32_t  braTargetPc2Lo;     /* 0x05a4 */
+    uint32_t  braTargetPc2Hi;     /* 0x05a8 */
+    uint32_t  braTargetPc3Lo;     /* 0x05ac */
+    uint32_t  braTargetPc3Hi;     /* 0x05b0 */
+    uint32_t  unused[3];          /* 0x05b4-0x05bf */
+    uint32_t  profSampleW[4];     /* 0x05c0 */
+} CoreProfile;
+
+typedef struct MaestroMisc {
+    CoreCtrl coreCtrl;          /* 0x0400 */
+    uint32_t   unused1[14];       /* 0x0448-0x047f */
+    CoreState coreState;        /* 0x0480 */
+    uint32_t   unused2[4];        /* 0x04f0-0x04ff */
+    CoreIntr interrupt;         /* 0x0500 */
+    uint32_t   unused3[9];        /* 0x055c-0x057f */
+    CoreProfile profile;        /* 0x0580 */
+} MaestroMisc;
+
+typedef struct Pmc {
+    uint32_t unused0[1030];
+    PmcCtrlReg ctrl;		            /* 0x1018 */
+    uint32_t unused1[622];	            /* 0x1148-0x1cff */
+    PmcDQMPac dqmPac;                   /* 0x1b00 */
+    uint32_t unused5[32];                 /* 0x1b80-0x1bff */
+    PmcDQMReg dqm;			            /* 0x1c00 */
+    uint32_t unused6[749];		        /* 0x1c4c-0x27ff */
+    uint32_t qStatus[32];		            /* 0x2800 */
+    uint32_t unused7[480];	            /* 0x2880-0x2fff */
+    PmcDqmQMibReg qMib;		            /* 0x3000 */
+    uint32_t unused8[928];	            /* 0x3180-0x3fff */
+    PmcDqmQCtrlReg dqmQCtrl[8]; 	    /* 0x4000 */
+    uint32_t unused9[992];                /* 0x4080-0x4fff */
+    PmcDqmQDataReg dqmQData[8]; 	    /* 0x5000 */
+} Pmc;
+
+typedef struct Procmon {
+    uint32_t unused00[256];
+    MaestroMisc maestroReg;             /* 0x00400 */
+    uint32_t unused10[32396];             /* 0x005d0-0x1ffff */
+    PmmReg  pmm;                        /* 0x20000 */
+    uint32_t unused11[22];                /* 0x20008-0x2005f */
+    SSBMaster ssbMasterCtrl;            /* 0x20060 */
+    uint32_t unused12[36];                /* 0x20070-0x200ff */
+    PmbBus pmb;                         /* 0x20100 */
+    uint32_t unused13[32576];             /* 0x20300-0x3ffff */
+    uint32_t qsm[128];                    /* 0x40000-0x401ff */
+    uint32_t unused14[65408];             /* 0x40200-0x7ffff */
+    uint32_t dtcm[1024];                  /* 0x80000-0x80fff */
+    uint32_t unused15[64512];             /* 0x81000-0xbffff */
+    uint32_t itcm[4096];                  /* 0xc0000-0xc3fff */
+} Procmon;
+
+
+typedef struct PMSSBMasterControl {
+	uint32_t control;
+	uint32_t wr_data;
+	uint32_t rd_data;
+} PMSSBMasterControl;
+
+typedef struct
+{
+    uint32_t  control;
+#define PMC_PMBM_START		            (1 << 31)
+#define PMC_PMBM_TIMEOUT	            (1 << 30)
+#define PMC_PMBM_SLAVE_ERR	            (1 << 29)
+#define PMC_PMBM_BUSY		            (1 << 28)
+#define PMC_PMBM_BUS_SHIFT              (20)
+#define PMC_PMBM_Read		            (0 << 24)
+#define PMC_PMBM_Write		            (1 << 24)
+    uint32_t  wr_data;
+    uint32_t  mutex;
+    uint32_t  rd_data;
+} PMB_keyhole_reg;
+
+typedef struct PMBMaster {
+    uint32_t config;
+#define PMB_NUM_REGS_SHIFT (20)
+#define PMB_NUM_REGS_MASK  (0x3ff)
+    uint32_t arbitger;
+    uint32_t timeout;
+    uint32_t reserved;
+    PMB_keyhole_reg keyhole[4];
+    uint32_t reserved1[44];
+    uint32_t map[64];
+} PMBMaster;
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4912/pmc_addr.h b/arch/arm/include/asm/arch-bcm4912/pmc_addr.h
new file mode 100644
index 0000000000..f666fc2968
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/pmc_addr.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+#ifndef _4912_PMC_ADDR_H
+#define _4912_PMC_ADDR_H
+
+#define PMB_BUS_MAX		2
+#define PMB_BUS_ID_SHIFT	12
+
+#define PMB_BUS_PERIPH		0
+#define PMB_ADDR_PERIPH		(0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH	4
+
+#define PMB_BUS_CHIP_CLKRST	0
+#define PMB_ADDR_CHIP_CLKRST	(1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST	0
+
+#define PMB_BUS_PVTMON		1
+#define PMB_ADDR_PVTMON		(3 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON	0
+
+#define PMB_BUS_CRYPTO		1
+#define PMB_ADDR_CRYPTO		(4 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CRYPTO	0
+
+#define PMB_BUS_USB30_2X	0
+#define PMB_ADDR_USB30_2X	(5 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB30_2X	4
+
+#define PMB_BUS_PCIE1		1
+#define PMB_ADDR_PCIE1		(6 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1		4
+
+// referring to PCIEG3
+#define PMB_BUS_PCIE3		1
+#define PMB_ADDR_PCIE3		(7 | PMB_BUS_PCIE3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE3		1
+
+#define PMB_BUS_MEMC		1
+#define PMB_ADDR_MEMC		(8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC		1
+
+#define PMB_BUS_XRDP		1
+#define PMB_ADDR_XRDP		(9 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP		1
+
+#define PMB_BUS_PCIE2		1
+#define PMB_ADDR_PCIE2		(11 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE2		1
+
+#define PMB_BUS_PCIE0		0
+#define PMB_ADDR_PCIE0		(12 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0		1
+
+#define PMB_BUS_ETH		1
+#define PMB_ADDR_ETH		(13 | PMB_BUS_ETH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ETH		1
+
+#define PMB_BUS_MPM		1
+#define PMB_ADDR_MPM		(14 | PMB_BUS_MPM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MPM		1
+
+#define PMB_BUS_XRDPPLL		0
+#define PMB_ADDR_XRDPPLL	(15 | PMB_BUS_XRDPPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDPPLL	0
+
+#define PMB_BUS_PERIPH_ARS	0
+#define PMB_ADDR_PERIPH_ARS	(16 | PMB_BUS_PERIPH_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH_ARS	0
+
+#define PMB_BUS_PCIE0_UBUS_ARS	0
+#define PMB_ADDR_PCIE0_UBUS_ARS	(17 | PMB_BUS_PCIE0_UBUS_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0_UBUS_ARS 0
+
+#define PMB_BUS_USB30_2X_ARS	0
+#define PMB_ADDR_USB30_2X_ARS	(18 | PMB_BUS_USB30_2X_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB30_2X_ARS	0
+
+#define PMB_BUS_SYS_ARS		0
+#define PMB_ADDR_SYS_ARS	(19 | PMB_BUS_SYS_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYS_ARS	0
+
+#define PMB_BUS_CRYPTO2_ARS	1
+#define PMB_ADDR_CRYPTO2_ARS	(20 | PMB_BUS_CRYPTO2_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CRYPTO2_ARS	0
+
+#define PMB_BUS_XRDP_ARS	1
+#define PMB_ADDR_XRDP_ARS	(21 | PMB_BUS_XRDP_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_ARS	0
+
+#define PMB_BUS_MPM_ARS		1
+#define PMB_ADDR_MPM_ARS	(22 | PMB_BUS_MPM_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MPM_ARS	0
+
+#define PMB_BUS_MEMC_ARS	1
+#define PMB_ADDR_MEMC_ARS	(23 | PMB_BUS_MEMC_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC_ARS	0
+
+#define PMB_BUS_ETH_ARS		1
+#define PMB_ADDR_ETH_ARS	(24 | PMB_BUS_ETH_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ETH_ARS	0
+
+#define PMB_BUS_PCIE1_UBUS_ARS	1
+#define PMB_ADDR_PCIE1_UBUS_ARS	(25 | PMB_BUS_PCIE1_UBUS_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1_UBUS_ARS	0
+
+#define PMB_BUS_PCIE3_ARS	1
+#define PMB_ADDR_PCIE3_ARS	(26 | PMB_BUS_PCIE3_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE3_ARS	0
+
+#define PMB_BUS_MERLIN0_UBUS_ARS	1
+#define PMB_ADDR_MERLIN0_UBUS_ARS	(27 | PMB_BUS_MERLIN0_UBUS_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MERLIN0_UBUS_ARS	0
+
+#define PMB_BUS_MERLIN1_UBUS_ARS	1
+#define PMB_ADDR_MERLIN1_UBUS_ARS	(28 | PMB_BUS_MERLIN1_UBUS_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MERLIN1_UBUS_ARS	0
+
+#define PMB_BUS_MERLIN2_UBUS_ARS	1
+#define PMB_ADDR_MERLIN2_UBUS_ARS	(29 | PMB_BUS_MERLIN2_UBUS_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MERLIN2_UBUS_ARS	0
+
+#define PMB_BUS_ORION_PLL	1
+#define PMB_ADDR_ORION_PLL	(32 | PMB_BUS_ORION_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_PLL	0
+#define PMB_BUS_BIU_PLL		PMB_BUS_ORION_PLL
+#define PMB_ADDR_BIU_PLL	PMB_ADDR_ORION_PLL
+#define PMB_ZONES_BIU_PLL	PMB_ZONES_ORION_PLL
+
+
+#define PMB_BUS_ORION_BPCM	1
+#define PMB_ADDR_ORION_BPCM	(33 | PMB_BUS_ORION_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_BPCM	1
+#define PMB_BUS_BIU_BPCM	PMB_BUS_ORION_BPCM
+#define PMB_ADDR_BIU_BPCM	PMB_ADDR_ORION_BPCM
+#define PMB_ZONES_BIU_BPCM	PMB_ZONES_ORION_BPCM
+
+#define PMB_BUS_ORION_CPU0	1
+#define PMB_ADDR_ORION_CPU0	(34 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0	1
+
+#define PMB_BUS_ORION_CPU1	1
+#define PMB_ADDR_ORION_CPU1	(35 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1	1
+
+#define PMB_BUS_ORION_CPU2	1
+#define PMB_ADDR_ORION_CPU2	(36 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU2	1
+
+#define PMB_BUS_ORION_CPU3	1
+#define PMB_ADDR_ORION_CPU3	(37 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU3	1
+
+#define PMB_BUS_ORION_NONCPU	1
+#define PMB_ADDR_ORION_NONCPU	(38 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU	1
+
+#define PMB_BUS_ORION_ARS	1
+#define PMB_ADDR_ORION_ARS	(39 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_ARS	0
+
+#define PMB_BUS_ORION_ACEBIU_ARS	1
+#define PMB_ADDR_ORION_ACEBIU_ARS	(40 | PMB_BUS_ORION_ACEBIU_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_ACEBIU_ARS	0
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4912/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm4912/pmc_drv_cfg.h
new file mode 100644
index 0000000000..c38e5eb307
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/pmc_drv_cfg.h
@@ -0,0 +1,40 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_3_X
+#define PMC_IMPL_3_2
+
+#define PMC_LOG_IN_DTCM         1
+#define PMC_FW_IN_ITCM          1
+#define PMC_CPUTEMP_SUPPORT     1
+#define PMC_RAM_BOOT 1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm4912/rng.h b/arch/arm/include/asm/arch-bcm4912/rng.h
new file mode 100644
index 0000000000..2e5ada10c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4912_RNG_H
+#define _4912_RNG_H
+
+#define RNG_BASE	0xff800b80
+
+typedef struct Rng {
+	uint32_t ctrl0;			/* 0x00 */
+	uint32_t rngSoftReset;		/* 0x04 */
+	uint32_t rbgSoftReset;		/* 0x08 */
+	uint32_t totalBitCnt;		/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;			/* 0x14 */
+	uint32_t intStatus;		/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL	(0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL	(0x1<<2)
+	uint32_t intEn;			/* 0x1c */
+	uint32_t rngFifoData;		/* 0x20 */
+	uint32_t fifoCnt;		/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS	0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS	0x33
+	uint32_t perm;			/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4912/ubus4.h b/arch/arm/include/asm/arch-bcm4912/ubus4.h
new file mode 100644
index 0000000000..d2b1ba8143
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/ubus4.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4912_UBUS4_H
+#define _4912_UBUS4_H
+
+#define MST_PORT_NODE_PER_PHYS_BASE         0x83010000
+#define MST_PORT_NODE_USB_PHYS_BASE         0x83018000
+#define MST_PORT_NODE_B53_PHYS_BASE         0x83020000
+#define MST_PORT_NODE_SPU_PHYS_BASE         0x83028000
+#define MST_PORT_NODE_PCIE0_PHYS_BASE       0x83030000
+#define MST_PORT_NODE_PCIE1_PHYS_BASE       0x83038000
+#define MST_PORT_NODE_PCIE2_PHYS_BASE       0x83040000
+#define MST_PORT_NODE_PCIE3_PHYS_BASE       0x83048000
+#define MST_PORT_NODE_QM_PHYS_BASE          0x83050000
+#define MST_PORT_NODE_DMA0_PHYS_BASE        0x83058000
+#define MST_PORT_NODE_DMA1_PHYS_BASE        0x83060000
+#define MST_PORT_NODE_DMA2_PHYS_BASE        0x83070000
+#define MST_PORT_NODE_RQ0_PHYS_BASE         0x83078000
+#define MST_PORT_NODE_RQ1_PHYS_BASE         0x83080000
+#define MST_PORT_NODE_MPM_PHYS_BASE         0x83088000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm4912/xrdp.h b/arch/arm/include/asm/arch-bcm4912/xrdp.h
new file mode 100644
index 0000000000..8bb79b306c
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm4912/xrdp.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _4912_XRDP_H
+#define _4912_XRDP_H
+
+#define XRDP_BASE            0x82000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/BPCM.h b/arch/arm/include/asm/arch-bcm63138/BPCM.h
new file mode 100644
index 0000000000..c2e7b30f8b
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/BPCM.h
@@ -0,0 +1,736 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t sw_strap:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+// types of PMB devices
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t z2_p_wan_phy_sel:3;	/* 0-2 */
+		uint32_t reserved0:1;	/* 3 */
+		uint32_t z2_switch_p3_phy_sel:3;	/* 4-6 */
+		uint32_t reserved1:1;	/* 7 */
+		uint32_t z2_switch_p4_phy_sel:3;	/* 8-10 */
+		uint32_t reserved2:1;	/* 11 */
+		uint32_t z0_mux_sel:1;	/* 12 */
+		uint32_t z1_gphy_mux_sel:1;	/* 13 */
+		uint32_t z2_gphy_mux_sel:1;	/* 14 */
+		uint32_t z2_crossbar_mux_sel:1;	/* 15 */
+		uint32_t reserved3:1;	/* 16 */
+		uint32_t z1_pda_en:1;	/* 17 */
+		uint32_t z1_ck250_clk_en:1;	/* 18 */
+		uint32_t z1_ck25_clk_dis:1;	/* 19 */
+		uint32_t reserved4:2;	/* 20-21 */
+		uint32_t z2_ck250_clk_en:1;	/* 22 */
+		uint32_t z2_ck25_clk_dis:1;	/* 23 */
+		uint32_t z2_serdes_clk_en:1;	/* 24 */
+		uint32_t z2_serdes_reset_mdioregs:1;	/* 25 */
+		uint32_t z2_sedes_reset_pll:1;	/* 26 */
+		uint32_t z2_serdes_reset:1;	/* 27 */
+		uint32_t z2_serdes_mux_sel:1;	/* 28 */
+		uint32_t reserved5:1;	/* 29 */
+		uint32_t z1_gphy_reset:1;	/* 30 */
+		uint32_t z2_gphy_reset:1;	/* 31 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t core_pwr_ctrl:2;	// 01:00    R/W
+		uint32_t reserved2:6;	// 07:02    R/W
+		uint32_t pll_pwr_on:1;	// 08:08    R/W
+		uint32_t pll_ldo_pwr_on:1;	// 09:09    R/W
+		uint32_t pll_clamp_on:1;	// 10:10    R/W
+		uint32_t reserved1:2;	// 12:11    R/O
+		uint32_t cpu0_reset_n:1;	// 13:13    R/W
+		uint32_t cpu1_reset_n:1;	// 14:14    R/W
+		uint32_t neon_reset_n:1;	// 15:15    R/W
+		uint32_t reserved0:12;	// 27:16    R/O
+		uint32_t pwr_ctrl_sts:2;	// 29:28    R/O
+		uint32_t power_down:2;	// 31:30    R/O
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	BPCM_ZONE_N_FREQ_SCALAR_CONTROL freq_scalar_control;
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	BPCM_SGPHY_CNTL sgphy_cntl;	// offset = 0x38, actual offset = 14
+	BPCM_SGPHY_STATUS sgphy_status;	// offset = 0x3c, actual offset = 15
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	uint32_t rvrsd[2];
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_VDSL_REGS;		// total offset space = 4096
+
+#define BPCMVDSLOffset(reg)	offsetof(BPCM_VDSL_REGS,reg)
+#define BPCMVDSLRegOffset(reg)	(BPCMVDSLOffset(reg) >> 2)
+
+// ARM BPCM addresses as used by 63138 and possibly others (28nm)
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved;	// offset = 0x2c, actual offset = 11
+	ARM_CONTROL_REG arm_control;	// offset = 0x30, actual offset = 12
+	ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl_0;	// offset = 0x34, actual offset = 13
+	ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl_1;	// offset = 0x38, actual offset = 14
+	ARM_CPUx_PWR_CTRL_REG arm_neon_l2;	// offset = 0x3c, actua; offset = 15
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} ARM_BPCM_REGS;
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	uint32_t decndiv;	// offset = 0x44, actual offset = 0x11
+	uint32_t decpdiv;	// offset = 0x48, actual offset = 0x12
+	uint32_t decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved1;	// offset = 0x2c, actual offset = 11
+	uint32_t clkrst_cfg;	// offset = 0x30, actual offset = 12
+	uint32_t clkrst_control;	// offset = 0x34, actual offset = 13
+	uint32_t xtal_control;	// offset = 0x38, actual offset = 14
+	uint32_t clkrst_stat;	// offset = 0x3c, actual offset = 15
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/avs_fixup.h b/arch/arm/include/asm/arch-bcm63138/avs_fixup.h
new file mode 100644
index 0000000000..fca75efcdd
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/avs_fixup.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include <asm/arch/timer.h>
+#include <asm/arch/misc.h>
+
+/*
+The algorithm to disable AVS in PMC ROM if enabled in STRAP:
+
+   if (POR) {
+      clear_marker();
+   }
+
+   if (AVS_ENABLED) {
+     override (AVS_DISABLE);
+     set_marker();
+     do_soft_reset();
+   }
+
+   if (is_marker_set()) {
+     override (AVS_ENABLE);
+   }
+
+   clear_marker();
+*/
+ ///////////////////////////////////////////
+	// Check if this is POR
+	ldr	r0, =TIMR_BASE
+	ldr	r1, [r0, #TIMER_RESET_STATUS]
+	tst	r1, #(TIMER_RESET_STATUS_POR)
+	beq	do_avs_disabled
+	// for POR, always clear marker
+	ldr	r0, =MISC_BASE
+	ldr	r1, [r0, #MISC_STRAP_BUS]
+	bic	r1, r1, #(MISC_STRAP_BUS_PMC_AVS_OVERRIDE_MARKER)
+	str	r1, [r0, #MISC_STRAP_BUS]
+
+do_avs_disabled:
+	ldr	r0, =MISC_BASE
+	ldr	r1, [r0, #MISC_STRAP_BUS]
+	// Check if AVS "was" intentionally disabled earlier
+	tst	r1, #(MISC_STRAP_BUS_PMC_BOOT_AVS)
+	beq	do_marker_check
+	// Since AVS is enabled,
+	// disable AVS and do soft reset
+	bic	r1, r1, #(MISC_STRAP_BUS_PMC_BOOT_AVS)
+	// Set marker to indicate AVS was disabled
+	orr	r1, r1, #(MISC_STRAP_BUS_PMC_AVS_OVERRIDE_MARKER)
+	str	r1, [r0, #MISC_STRAP_BUS]
+	// Save changes (toggle override)
+	mov	r1, #1
+	str	r1, [r0, #MISC_STRAP_BUS_OVERRIDE]
+	mov	r1, #0
+	str	r1, [r0, #MISC_STRAP_BUS_OVERRIDE]
+	//soft reset the chip
+	ldr	r0, =TIMR_BASE
+	mov	r1, #1
+	str	r1, [r0, #TIMER_WD_RESET]
+	// See you in next life
+rstc:	
+	b	rstc
+
+do_marker_check:
+	// re-enable AVS only if it "was" intentionally disabled earlier
+	tst r1, #(MISC_STRAP_BUS_PMC_AVS_OVERRIDE_MARKER)
+	beq do_clear_marker
+	// Enable AVS
+	orr	r1, r1, #(MISC_STRAP_BUS_PMC_BOOT_AVS)
+        
+do_clear_marker:
+	// Clear marker
+	bic	r1, r1, #(MISC_STRAP_BUS_PMC_AVS_OVERRIDE_MARKER)
+	str	r1, [r0, #MISC_STRAP_BUS]
+	// Save changes (toggle override)
+	mov	r1, #1
+	str	r1, [r0, #MISC_STRAP_BUS_OVERRIDE]
+	mov	r1, #0
+	str	r1, [r0, #MISC_STRAP_BUS_OVERRIDE]
diff --git a/arch/arm/include/asm/arch-bcm63138/boot0.h b/arch/arm/include/asm/arch-bcm63138/boot0.h
new file mode 100644
index 0000000000..51439af122
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/boot0.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63138_BOOT0_H
+#define _63138_BOOT0_H
+
+#include <asm-offsets.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+_bcm_boot:
+	mov	r0,#0
+	mcr	p15,0,r0,c8,c7,0		/* Invalidate TLB */
+	mcr	p15,0,r0,c7,c5,0		/* Invalidate icache */
+	
+	/* Initialize system control register enable i-cache */
+	mrc	p15,0,r0,c1,c0,0
+	bic	r0,r0,#(CR_C|CR_A|CR_M)		/* Clear C, A, M bits */
+	orr	r0,r0,#CR_I			/* Set I bit: enable instruction cache */
+	mcr	p15,0,r0,c1,c0,0
+
+	isb
+
+#include <asm/arch/avs_fixup.h>	
+#include <asm/arch/pmc_ll_init.h>
+
+	/* relocate the code, init'ed data from flash to lmem  */	
+relo_image:
+	adr     r1, _bcm_boot		/* r1 source address in flash */
+	ldr	r0, =__image_copy_start	/* r0 dest address in sram */
+	subs	r4, r1, r0		/* r4 relocation offset */
+	beq	relo_dtb		/* skip relocation */
+	ldr	r2, =__image_copy_end	/* r2 dest ending address in flash */
+
+relo_loop:
+	ldmia	r1!, {r10-r11}
+	stmia	r0!, {r10-r11}
+	cmp	r0, r2
+	blo	relo_loop
+
+	/* if we attached dtb after bss, need to relocate dtb as well */	
+relo_dtb:
+#if defined(CONFIG_SPL_OF_CONTROL) && defined(CONFIG_OF_SEPARATE)
+
+#ifdef CONFIG_OF_SPL_SEPARATE_BSS
+	ldr	r3, =__image_binary_end
+#else
+	ldr	r3, =__bss_end
+#endif
+	add	r1, r3, r4       /* r1 source address in flash */
+	/* check ftd size ... */
+	/* struct fdt_header {
+	fdt32_t magic;
+	fdt32_t totalsize; */
+	ldr	r0, [r1, #4]	/* r0 total size */
+	rev	r0, r0          /* byte order from fdt to little endian */
+	lsr	r0, r0, #2      /* in the order of 4 bytes aligned */
+	add	r0, r0, #1
+	lsl	r0, r0, #2 
+	add	r2, r1, r0       /* r2 dest ending address in flash */
+	mov	r0, r3           /* r0 dest address in sram */
+
+dtb_loop:
+	ldmia	r1!, {r10-r11}
+	stmia	r0!, {r10-r11}
+	cmp	r1, r2
+	blo	dtb_loop
+#endif
+	ldr	r0, =reset
+	bx	r0
+
+#endif
+	.align(5), 0x0
+_start:
+	ARM_VECTORS
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/brom.h b/arch/arm/include/asm/arch-bcm63138/brom.h
new file mode 100644
index 0000000000..2fa9eed572
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/brom.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63138_BROM_H
+#define _63138_BROM_H
+#define BROM_SEC_BASE 0xfffeb614	   	 
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromSec_ {
+#define	BROM_GEN_JTAG_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_JTAG_SPI_SLV_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+} BromSec;
+
+#define BROM_GEN ((volatile BromSec * const) BROM_SEC_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= (BROM_GEN_JTAGE_SPI_SLV_UNLOCK_MASK<<BROM_GEN_JTAG_SPI_SLV_UNLOCK_SHIFT) ; }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/cpu.h b/arch/arm/include/asm/arch-bcm63138/cpu.h
new file mode 100644
index 0000000000..c62bbfa1ff
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/cpu.h
@@ -0,0 +1,267 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63138_CPU_H
+#define _63138_CPU_H
+
+#define ARMGTIM_BASE        0x8001e200
+#define AIP_BASE            0x80018000
+#define ARMCFG_BASE         0x80020000
+
+typedef struct ArmGTimer {
+	uint32_t gtim_glob_low;	/* 0x00 */
+	uint32_t gtim_glob_hi;	/* 0x04 */
+	uint32_t gtim_glob_ctrl;	/* 0x08 */
+#define ARM_GTIM_GLOB_CTRL_PRESCALE_SHIFT            8
+#define ARM_GTIM_GLOB_CTRL_PRESCALE_MASK             (0xff<<ARM_GTIM_GLOB_CTRL_PRESCALE_SHIFT)
+#define ARM_GTIM_GLOB_CTRL_AUTOINCR_EN               0x8
+#define ARM_GTIM_GLOB_CTRL_IRQ_EN                    0x4
+#define ARM_GTIM_GLOB_CTRL_COMP_EN                   0x2
+#define ARM_GTIM_GLOB_CTRL_TIMER_EN                  0x1
+	uint32_t gtim_glob_status;	/* 0x0c */
+	uint32_t gtim_glob_comp_low;	/* 0x10 */
+	uint32_t gtim_glob_comp_hi;	/* 0x14 */
+	uint32_t gtim_glob_incr;	/* 0x18 */
+} ArmGTimer;
+
+#define ARMGTIM ((volatile ArmGTimer * const) ARMGTIM_BASE)
+
+typedef struct ArmAipCtrl {
+	uint32_t cfg;		/* 0x00 */
+#define AIP_CTRL_CFG_WR_FAST_ACK_MASK 0x2
+	uint32_t l2c_ctrl;	/* 0x04 */
+	uint32_t arm_ctrl;	/* 0x08 */
+	uint32_t unused0;
+	uint32_t acp_ctrl[32];	/* 0x10-0xc */
+#define AIPACP_WCACHE_SHIFT         0
+#define AIPACP_WCACHE_MASK          0xf
+#define AIPACP_WCACHE_GET(reg_val) ((reg_val >> AIPACP_WCACHE_SHIFT) & AIPACP_WCACHE_MASK)
+#define AIPACP_WCACHE_SET(reg_val,new_val)   ((reg_val & ~(AIPACP_WCACHE_MASK << AIPACP_WCACHE_SHIFT)) | (new_val << AIPACP_WCACHE_SHIFT))
+#define AIPACP_RCACHE_SHIFT         4
+#define AIPACP_RCACHE_MASK          0xf
+#define AIPACP_RCACHE_GET(reg_val)  ((reg_val >> AIPACP_RCACHE_SHIFT) & AIPACP_RCACHE_MASK)
+#define AIPACP_RCACHE_SET(reg_val,new_val)   ((reg_val & ~(AIPACP_RCACHE_MASK << AIPACP_RCACHE_SHIFT)) | (new_val << AIPACP_RCACHE_SHIFT))
+#define AIPACP_WUSER_SHIFT          8
+#define AIPACP_WUSER_MASK           0x1f
+#define AIPACP_WUSER_GET(reg_val)      ((reg_val >> AIPACP_WUSER_SHIFT) & AIPACP_WUSER_MASK)
+#define AIPACP_WUSER_SET(reg_val,new_val) ((reg_val & ~(AIPACP_WUSER_MASK << AIPACP_WUSER_SHIFT)) | (new_val << AIPACP_WUSER_SHIFT))
+#define AIPACP_RUSER_SHIFT          13
+#define AIPACP_RUSER_MASK           0x1f
+#define AIPACP_RUSER_GET(reg_val)   ((reg_val >> AIPACP_RUSER_SHIFT) & AIPACP_RUSER_MASK)
+#define AIPACP_RUSER_SET(reg_val,new_val) ((reg_val & ~(AIPACP_RUSER_MASK << AIPACP_RUSER_SHIFT)) | (new_val << AIPACP_RUSER_SHIFT))
+
+	uint32_t unused1[12];
+	uint32_t debug_permission;	/* 0xc0 */
+	uint32_t debug_en;	/* 0xc4 */
+} ArmAipCtrl;
+#define ARMAIPCTRL ((volatile ArmAipCtrl * const) AIP_BASE)
+
+/*
+ * ARM CFG
+ */
+typedef struct ArmProcClkMgr {
+	uint32_t wr_access;	/* 0x00 */
+#define ARM_PROC_CLK_WR_ACCESS_PASSWORD_SHIFT         8
+#define ARM_PROC_CLK_WR_ACCESS_PASSWORD_MASK          (0xffff<<ARM_PROC_CLK_WR_ACCESS_PASSWORD_SHIFT)
+#define ARM_PROC_CLK_WR_ACCESS_PASSWORD               0xA5A5
+#define ARM_PROC_CLK_WR_ACCESS_CLKMGR_ACC_SHIFT       0
+#define ARM_PROC_CLK_WR_ACCESS_CLKMGR_ACC_MASK        (0x1<<ARM_PROC_CLK_WR_ACCESS_CLKMGR_ACC_SHIFT)
+#define ARM_PROC_CLK_WR_ACCESS_CLKMGR_ACC             0x1
+	uint32_t unused0;
+	uint32_t policy_freq;
+#define ARM_PROC_CLK_POLICY3_FREQ_SHIFT               24
+#define ARM_PROC_CLK_POLICY3_FREQ_MASK                (0x7<<ARM_PROC_CLK_POLICY3_FREQ_SHIFT)
+#define ARM_PROC_CLK_POLICY2_FREQ_SHIFT               16
+#define ARM_PROC_CLK_POLICY2_FREQ_MASK                (0x7<<ARM_PROC_CLK_POLICY2_FREQ_SHIFT)
+#define ARM_PROC_CLK_POLICY1_FREQ_SHIFT               8
+#define ARM_PROC_CLK_POLICY1_FREQ_MASK                (0x7<<ARM_PROC_CLK_POLICY1_FREQ_SHIFT)
+#define ARM_PROC_CLK_POLICY0_FREQ_SHIFT               0
+#define ARM_PROC_CLK_POLICY0_FREQ_MASK                (0x7<<ARM_PROC_CLK_POLICY0_FREQ_SHIFT)
+#define ARM_PROC_CLK_POLICY_FREQ_MASK                 (ARM_PROC_CLK_POLICY0_FREQ_MASK|ARM_PROC_CLK_POLICY1_FREQ_MASK|ARM_PROC_CLK_POLICY2_FREQ_MASK|ARM_PROC_CLK_POLICY3_FREQ_MASK)
+#define ARM_PROC_CLK_POLICY_FREQ_ALL(x)	              ((x << ARM_PROC_CLK_POLICY3_FREQ_SHIFT) | (x << ARM_PROC_CLK_POLICY2_FREQ_SHIFT) | \
+                                                       (x << ARM_PROC_CLK_POLICY1_FREQ_SHIFT) | (x << ARM_PROC_CLK_POLICY0_FREQ_SHIFT))
+#define ARM_PROC_CLK_POLICY_FREQ_CRYSTAL              0
+#define ARM_PROC_CLK_POLICY_FREQ_SYSCLK               2
+#define ARM_PROC_CLK_POLICY_FREQ_ARMPLL_SLOW          6
+#define ARM_PROC_CLK_POLICY_FREQ_ARMPLL_FAST          7
+	uint32_t policy_ctl;
+#define ARM_PROC_CLK_POLICY_CTL_GO_ATL                0x4
+#define ARM_PROC_CLK_POLICY_CTL_GO_AC                 0x2
+#define ARM_PROC_CLK_POLICY_CTL_GO                    0x1
+	uint32_t policy0_mask;	/* 0x10 */
+	uint32_t policy1_mask;
+	uint32_t policy2_mask;
+	uint32_t policy3_mask;
+	uint32_t int_en;	/* 0x20 */
+	uint32_t int_stat;
+	uint32_t unused1[3];
+	uint32_t lvm_en;	/* 0x34 */
+	uint32_t lvm0_3;
+	uint32_t lvm4_7;
+	uint32_t vlt0_3;	/* 0x40 */
+	uint32_t vlt4_7;
+	uint32_t unused2[46];
+	uint32_t bus_quiesc;	/* 0x100 */
+	uint32_t unused3[63];
+	uint32_t core0_clkgate;	/* 0x200 */
+#define ARM_PROC_CLK_CORE0_CLKGATE_HYST_EN_SHIFT     9
+#define ARM_PROC_CLK_CORE0_CLKGATE_HYST_EN_MASK      (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_HYST_EN_SHIFT)
+#define ARM_PROC_CLK_CORE0_CLKGATE_HYST_EN           1
+#define ARM_PROC_CLK_CORE0_CLKGATE_HYST_DIS          0
+#define ARM_PROC_CLK_CORE0_CLKGATE_HYST_VAL_SHIFT    8
+#define ARM_PROC_CLK_CORE0_CLKGATE_HYST_VAL_MASK     (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_HYST_VAL_SHIFT)
+#define ARM_PROC_CLK_CORE0_CLKGATE_HYST_VAL_LOW      0x0
+#define ARM_PROC_CLK_CORE0_CLKGATE_HYST_VAL_HIGH     0x1
+#define ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_SHIFT  1
+#define ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_MASK   (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_SHIFT)
+#define ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_HW     0x0
+#define ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_SW     0x1
+#define ARM_PROC_CLK_CORE0_CLKGATE_CLK_EN_SHIFT      0
+#define ARM_PROC_CLK_CORE0_CLKGATE_CLK_EN_MASK       (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_CLK_EN_SHIFT)
+#define ARM_PROC_CLK_CORE0_CLKGATE_CLK_EN            1
+#define ARM_PROC_CLK_CORE0_CLKGATE_CLK_DIS           0
+	uint32_t core1_clkgate;
+#define ARM_PROC_CLK_CORE1_CLKGATE_HYST_EN_SHIFT     9
+#define ARM_PROC_CLK_CORE1_CLKGATE_HYST_EN_MASK      (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_HYST_EN_SHIFT)
+#define ARM_PROC_CLK_CORE1_CLKGATE_HYST_EN           1
+#define ARM_PROC_CLK_CORE1_CLKGATE_HYST_DIS          0
+#define ARM_PROC_CLK_CORE1_CLKGATE_HYST_VAL_SHIFT    8
+#define ARM_PROC_CLK_CORE1_CLKGATE_HYST_VAL_MASK     (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_HYST_VAL_SHIFT)
+#define ARM_PROC_CLK_CORE1_CLKGATE_HYST_VAL_LOW      0x0
+#define ARM_PROC_CLK_CORE1_CLKGATE_HYST_VAL_HIGH     0x1
+#define ARM_PROC_CLK_CORE1_CLKGATE_GATING_SEL_SHIFT  1
+#define ARM_PROC_CLK_CORE1_CLKGATE_GATING_SEL_MASK   (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_SHIFT)
+#define ARM_PROC_CLK_CORE1_CLKGATE_GATING_SEL_HW     0x0
+#define ARM_PROC_CLK_CORE1_CLKGATE_GATING_SEL_SW     0x1
+#define ARM_PROC_CLK_CORE1_CLKGATE_CLK_EN_SHIFT      0
+#define ARM_PROC_CLK_CORE1_CLKGATE_CLK_EN_MASK       (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_CLK_EN_SHIFT)
+#define ARM_PROC_CLK_CORE1_CLKGATE_CLK_EN            1
+#define ARM_PROC_CLK_CORE1_CLKGATE_CLK_DIS           0
+	uint32_t unused4[2];
+	uint32_t arm_switch_clkgate;	/* 0x210 */
+#define ARM_PROC_CLK_SWITCH_CLKGATE_HYST_EN_SHIFT    9
+#define ARM_PROC_CLK_SWITCH_CLKGATE_HYST_EN_MASK     (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_HYST_EN_SHIFT)
+#define ARM_PROC_CLK_SWITCH_CLKGATE_HYST_EN          1
+#define ARM_PROC_CLK_SWITCH_CLKGATE_HYST_DIS         0
+#define ARM_PROC_CLK_SWITCH_CLKGATE_HYST_VAL_SHIFT   8
+#define ARM_PROC_CLK_SWITCH_CLKGATE_HYST_VAL_MASK    (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_HYST_VAL_SHIFT)
+#define ARM_PROC_CLK_SWITCH_CLKGATE_HYST_VAL_LOW     0x0
+#define ARM_PROC_CLK_SWITCH_CLKGATE_HYST_VAL_HIGH    0x1
+#define ARM_PROC_CLK_SWITCH_CLKGATE_GATING_SEL_SHIFT 1
+#define ARM_PROC_CLK_SWITCH_CLKGATE_GATING_SEL_MASK  (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_SHIFT)
+#define ARM_PROC_CLK_SWITCH_CLKGATE_GATING_SEL_HW    0x0
+#define ARM_PROC_CLK_SWITCH_CLKGATE_GATING_SEL_SW    0x1
+#define ARM_PROC_CLK_SWITCH_CLKGATE_CLK_EN_SHIFT     0
+#define ARM_PROC_CLK_SWITCH_CLKGATE_CLK_EN_MASK      (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_CLK_EN_SHIFT)
+#define ARM_PROC_CLK_SWITCH_CLKGATE_CLK_EN           1
+#define ARM_PROC_CLK_SWITCH_CLKGATE_CLK_DIS          0
+	uint32_t unused5[59];
+	uint32_t arm_periph_clkgate;	/* 0x300 */
+#define ARM_PROC_CLK_PERIPH_CLKGATE_HYST_EN_SHIFT    9
+#define ARM_PROC_CLK_PERIPH_CLKGATE_HYST_EN_MASK     (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_HYST_EN_SHIFT)
+#define ARM_PROC_CLK_PERIPH_CLKGATE_HYST_EN          1
+#define ARM_PROC_CLK_PERIPH_CLKGATE_HYST_DIS         0
+#define ARM_PROC_CLK_PERIPH_CLKGATE_HYST_VAL_SHIFT   8
+#define ARM_PROC_CLK_PERIPH_CLKGATE_HYST_VAL_MASK    (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_HYST_VAL_SHIFT)
+#define ARM_PROC_CLK_PERIPH_CLKGATE_HYST_VAL_LOW     0x0
+#define ARM_PROC_CLK_PERIPH_CLKGATE_HYST_VAL_HIGH    0x1
+#define ARM_PROC_CLK_PERIPH_CLKGATE_GATING_SEL_SHIFT 1
+#define ARM_PROC_CLK_PERIPH_CLKGATE_GATING_SEL_MASK  (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_SHIFT)
+#define ARM_PROC_CLK_PERIPH_CLKGATE_GATING_SEL_HW    0x0
+#define ARM_PROC_CLK_PERIPH_CLKGATE_GATING_SEL_SW    0x1
+#define ARM_PROC_CLK_PERIPH_CLKGATE_CLK_EN_SHIFT     0
+#define ARM_PROC_CLK_PERIPH_CLKGATE_CLK_EN_MASK      (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_CLK_EN_SHIFT)
+#define ARM_PROC_CLK_PERIPH_CLKGATE_CLK_EN           1
+#define ARM_PROC_CLK_PERIPH_CLKGATE_CLK_DIS          0
+	uint32_t unused6[63];
+	uint32_t apb0_clkgate;	/* 0x400 */
+#define ARM_PROC_CLK_APB0_CLKGATE_HYST_EN_SHIFT      9
+#define ARM_PROC_CLK_APB0_CLKGATE_HYST_EN_MASK       (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_HYST_EN_SHIFT)
+#define ARM_PROC_CLK_APB0_CLKGATE_HYST_EN            1
+#define ARM_PROC_CLK_APB0_CLKGATE_HYST_DIS           0
+#define ARM_PROC_CLK_APB0_CLKGATE_HYST_VAL_SHIFT     8
+#define ARM_PROC_CLK_APB0_CLKGATE_HYST_VAL_MASK      (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_HYST_VAL_SHIFT)
+#define ARM_PROC_CLK_APB0_CLKGATE_HYST_VAL_LOW       0x0
+#define ARM_PROC_CLK_APB0_CLKGATE_HYST_VAL_HIGH      0x1
+#define ARM_PROC_CLK_APB0_CLKGATE_GATING_SEL_SHIFT   1
+#define ARM_PROC_CLK_APB0_CLKGATE_GATING_SEL_MASK    (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_SHIFT)
+#define ARM_PROC_CLK_APB0_CLKGATE_GATING_SEL_HW      0x0
+#define ARM_PROC_CLK_APB0_CLKGATE_GATING_SEL_SW      0x1
+#define ARM_PROC_CLK_APB0_CLKGATE_CLK_EN_SHIFT       0
+#define ARM_PROC_CLK_APB0_CLKGATE_CLK_EN_MASK        (0x1<<ARM_PROC_CLK_CORE0_CLKGATE_CLK_EN_SHIFT)
+#define ARM_PROC_CLK_APB0_CLKGATE_CLK_EN             1
+#define ARM_PROC_CLK_APB0_CLKGATE_CLK_DIS            0
+	uint32_t unused7[383];
+	uint32_t pl310_div;	/* 0xa00 */
+	uint32_t pl310_trigger;
+	uint32_t arm_switch_div;
+	uint32_t arm_switch_trigger;
+	uint32_t apb_div;	/* 0xa10 */
+	uint32_t apb_trigger;
+	uint32_t unused8[122];
+	uint32_t pllarma;	/* 0xc00 */
+#define ARM_PROC_CLK_PLLARMA_PLL_LOCK                (0x1<<28)
+#define ARM_PROC_CLK_PLLARMA_PDIV_SHIFT              24
+#define ARM_PROC_CLK_PLLARMA_PDIV_MASK               (0x7<<ARM_PROC_CLK_PLLARMA_PDIV_SHIFT)
+#define ARM_PROC_CLK_PLLARMA_NDIV_SHIFT              8
+#define ARM_PROC_CLK_PLLARMA_NDIV_MASK               (0x3ff<<ARM_PROC_CLK_PLLARMA_NDIV_SHIFT)
+#define ARM_PROC_CLK_PLLARMA_PLL_LOCK_RAW            (0x1<<7)
+#define ARM_PROC_CLK_PLLARMA_PWRDWN_SWOVRRIDE_SHIFT  4
+#define ARM_PROC_CLK_PLLARMA_PWRDWN_SWOVRRIDE_MASK   (0x1<<ARM_PROC_CLK_PLLARMA_PWRDWN_SWOVRRIDE_SHIFT)
+#define ARM_PROC_CLK_PLLARMA_SOFT_POST_RESETB_N      0x2
+#define ARM_PROC_CLK_PLLARMA_SOFT_RESETB_N           0x1
+	uint32_t pllarmb;
+#define ARM_PROC_CLK_PLLARMB_NDIV_FRAC_SHIFT         0
+#define ARM_PROC_CLK_PLLARMB_NDIV_FRAC_MASK         (0xfffff<<ARM_PROC_CLK_PLLARMB_NDIV_FRAC_SHIFT)
+	uint32_t pllarmc;
+#define ARM_PROC_CLK_PLLARMC_MDIV_SHIFT              0
+#define ARM_PROC_CLK_PLLARMC_MDIV_MASK               (0xff<<ARM_PROC_CLK_PLLARMC_MDIV_SHIFT)
+	uint32_t pllarmctrl0;
+	uint32_t pllarmctrl1;	/* 0xc10 */
+	uint32_t pllarmctrl2;
+	uint32_t pllarmctrl3;
+	uint32_t pllarmctrl4;
+	uint32_t pllarmctrl5;	/* 0xc20 */
+	uint32_t pllarm_offset;
+	uint32_t unused9[118];
+	uint32_t arm_div;	/* 0xe00 */
+	uint32_t arm_seg_trg;
+	uint32_t arm_seg_trg_override;
+	uint32_t unused10;
+	uint32_t pll_debug;	/* 0xe10 */
+	uint32_t unused11[3];
+	uint32_t activity_mon1;	/* 0xe20 */
+	uint32_t activity_mon2;
+	uint32_t unused12[6];
+	uint32_t clkgate_dbg;	/* 0xe40 */
+	uint32_t unused13;
+	uint32_t apb_clkgate_dbg1;
+	uint32_t unused14[6];
+	uint32_t clkmon;	/* 0xe64 */
+	uint32_t unused15[10];
+	uint32_t kproc_ccu_prof_ctl;	/* 0xe90 */
+	uint32_t kproc_cpu_proc_sel;
+	uint32_t kproc_cpu_proc_cnt;
+	uint32_t kproc_cpu_proc_dbg;
+	uint32_t unused16[8];
+	uint32_t policy_dbg;	/* 0xec0 */
+	uint32_t tgtmask_dbg1;
+} ArmProcClkMgr;
+
+typedef struct ArmProcResetMgr {
+	uint32_t wr_access;	/* 0x00 */
+	uint32_t soft_rstn;
+	uint32_t a9_core_soft_rstn;
+} ArmProcResetMgr;
+
+typedef struct ArmCfg {
+	ArmProcClkMgr proc_clk;	/* 0x00 */
+	uint32_t unused0[14];	/* 0xec8 - 0xeff */
+	ArmProcResetMgr proc_reset;	/* 0xf00 */
+	//uint32_t unused0[61];      /* 0xf0c - 0xfff */
+} ArmCfg;
+#define ARMCFG ((volatile ArmCfg * const) ARMCFG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/ddr.h b/arch/arm/include/asm/arch-bcm63138/ddr.h
new file mode 100644
index 0000000000..37039fbd5c
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/ddr.h
@@ -0,0 +1,417 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63138_DDR_H
+#define _63138_DDR_H
+
+#define DDRPHY_BASE    0x80003000
+#define MEMC_BASE      0x80002000
+
+typedef struct UBUSInterface {
+	uint32_t CFG;		/* 0x00 */
+#define UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT   0x0
+#define UBUSIF_CFG_WRITE_REPLY_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT)
+#define UBUSIF_CFG_WRITE_BURST_MODE_SHIFT   0x1
+#define UBUSIF_CFG_WRITE_BURST_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_BURST_MODE_SHIFT)
+#define UBUSIF_CFG_INBAND_ERR_MASK_SHIFT    0x2
+#define UBUSIF_CFG_INBAND_ERR_MASK_MASK     (0x1<< UBUSIF_CFG_INBAND_ERR_MASK_SHIFT)
+#define UBUSIF_CFG_OOB_ERR_MASK_SHIFT       0x3
+#define UBUSIF_CFG_OOB_ERR_MASK_MASK        (0x1<< UBUSIF_CFG_OOB_ERR_MASK_SHIFT)
+	uint32_t SRC_QUEUE_CTRL_0;	/* 0x04 */
+	uint32_t SRC_QUEUE_CTRL_1;	/* 0x08 */
+	uint32_t SRC_QUEUE_CTRL_2;	/* 0x0c */
+	uint32_t SRC_QUEUE_CTRL_3;	/* 0x10 */
+	uint32_t REP_ARB_MODE;	/* 0x14 */
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT 0x0
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_MASK  (0x1<<UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT)
+	uint32_t SCRATCH;	/* 0x18 */
+	uint32_t DEBUG_R0;	/* 0x1c */
+	uint32_t unused[8];	/* 0x20-0x3f */
+} UBUSInterface;
+
+typedef struct EDISEngine {
+	uint32_t REV_ID;	/* 0x00 */
+	uint32_t CTRL_TRIG;	/* 0x04 */
+	uint32_t CTRL_MODE;	/* 0x08 */
+	uint32_t CTRL_SIZE;	/* 0x0c */
+	uint32_t CTRL_ADDR_START;	/* 0x10 */
+	uint32_t CTRL_ADDR_START_EXT;	/* 0x14 */
+	uint32_t CTRL_ADDR_END;	/* 0x18 */
+	uint32_t CTRL_ADDR_END_EXT;	/* 0x1c */
+	uint32_t CTRL_WRITE_MASKS;	/* 0x20 */
+	uint32_t unused0[7];	/* 0x24-0x3f */
+	uint32_t STAT_MAIN;	/* 0x40 */
+	uint32_t STAT_WORDS_WRITTEN;	/* 0x44 */
+	uint32_t STAT_WORDS_READ;	/* 0x48 */
+	uint32_t STAT_ERROR_COUNT;	/* 0x4c */
+	uint32_t STAT_ERROR_BITS;	/* 0x50 */
+	uint32_t STAT_ADDR_LAST;	/* 0x54 */
+	uint32_t STAT_ADDR_LAST_EXT;	/* 0x58 */
+	uint32_t unused1[8];	/* 0x5c-0x7b */
+	uint32_t STAT_DEBUG;	/* 0x7c */
+	uint32_t STAT_DATA_PORT[8];	/* 0x80-0x9c */
+	uint32_t GEN_LFSR_STATE[4];	/* 0xa0-0xac */
+	uint32_t GEN_CLOCK;	/* 0xb0 */
+	uint32_t GEN_PATTERN;	/* 0xb4 */
+	uint32_t unused2[2];	/* 0xb8-0xbf */
+	uint32_t BYTELANE_0_CTRL_LO;	/* 0xc0 */
+	uint32_t BYTELANE_0_CTRL_HI;	/* 0xc4 */
+	uint32_t BYTELANE_1_CTRL_LO;	/* 0xc8 */
+	uint32_t BYTELANE_1_CTRL_HI;	/* 0xcc */
+	uint32_t BYTELANE_2_CTRL_LO;	/* 0xd0 */
+	uint32_t BYTELANE_2_CTRL_HI;	/* 0xd4 */
+	uint32_t BYTELANE_3_CTRL_LO;	/* 0xd8 */
+	uint32_t BYTELANE_3_CTRL_HI;	/* 0xdc */
+	uint32_t BYTELANE_0_STAT_LO;	/* 0xe0 */
+	uint32_t BYTELANE_0_STAT_HI;	/* 0xe4 */
+	uint32_t BYTELANE_1_STAT_LO;	/* 0xe8 */
+	uint32_t BYTELANE_1_STAT_HI;	/* 0xec */
+	uint32_t BYTELANE_2_STAT_LO;	/* 0xf0 */
+	uint32_t BYTELANE_2_STAT_HI;	/* 0xf4 */
+	uint32_t BYTELANE_3_STAT_LO;	/* 0xf8 */
+	uint32_t BYTELANE_3_STAT_HI;	/* 0xfc */
+} EDISEngine;
+
+typedef struct SecureRangeCheckers {
+	uint32_t LOCK;		/* 0x00 */
+	uint32_t LOG_INFO_0;	/* 0x04 */
+	uint32_t LOG_INFO_1;	/* 0x08 */
+	uint32_t CTRL_0;	/* 0x0c */
+	uint32_t UBUS0_PORT_0;	/* 0x10 */
+	uint32_t BASE_0;	/* 0x14 */
+	uint32_t CTRL_1;	/* 0x18 */
+	uint32_t UBUS0_PORT_1;	/* 0x1c */
+	uint32_t BASE_1;	/* 0x20 */
+	uint32_t CTRL_2;	/* 0x24 */
+	uint32_t UBUS0_PORT_2;	/* 0x28 */
+	uint32_t BASE_2;	/* 0x2c */
+	uint32_t CTRL_3;	/* 0x30 */
+	uint32_t UBUS0_PORT_3;	/* 0x34 */
+	uint32_t BASE_3;	/* 0x38 */
+	uint32_t CTRL_4;	/* 0x3c */
+	uint32_t UBUS0_PORT_4;	/* 0x40 */
+	uint32_t BASE_4;	/* 0x44 */
+	uint32_t CTRL_5;	/* 0x48 */
+	uint32_t UBUS0_PORT_5;	/* 0x4c */
+	uint32_t BASE_5;	/* 0x50 */
+	uint32_t CTRL_6;	/* 0x54 */
+	uint32_t UBUS0_PORT_6;	/* 0x58 */
+	uint32_t BASE_6;	/* 0x5c */
+	uint32_t CTRL_7;	/* 0x60 */
+	uint32_t UBUS0_PORT_7;	/* 0x64 */
+	uint32_t BASE_7;	/* 0x68 */
+	uint32_t unused[37];	/* 0x6c-0xff */
+} SecureRangeCheckers;
+
+typedef struct DDRPhyControl {
+	uint32_t REVISION;	/* 0x00 */
+	uint32_t PLL_STATUS;	/* 0x04 */
+	uint32_t PLL_CONFIG;	/* 0x08 */
+	uint32_t PLL_CONTROL1;	/* 0x0c */
+	uint32_t PLL_CONTROL2;	/* 0x10 */
+	uint32_t PLL_CONTROL3;	/* 0x14 */
+	uint32_t PLL_DIVIDER;	/* 0x18 */
+	uint32_t PLL_PRE_DIVIDER;	/* 0x1c */
+	uint32_t PLL_SS_EN;	/* 0x20 */
+	uint32_t PLL_SS_CFG;	/* 0x24 */
+	uint32_t AUX_CONTROL;	/* 0x28 */
+	uint32_t IDLE_PAD_CONTROL;	/* 0x2c */
+	uint32_t IDLE_PAD_EN0;	/* 0x30 */
+	uint32_t IDLE_PAD_EN1;	/* 0x34 */
+	uint32_t DRIVE_PAD_CTL;	/* 0x38 */
+	uint32_t STATIC_PAD_CTL;	/* 0x3c */
+	uint32_t DRAM_CFG;	/* 0x40 */
+	uint32_t DRAM_TIMING1;	/* 0x44 */
+	uint32_t DRAM_TIMING2;	/* 0x48 */
+	uint32_t DRAM_TIMING3;	/* 0x4c */
+	uint32_t DRAM_TIMING4;	/* 0x50 */
+	uint32_t unused0[3];	/* 0x54-0x5f */
+
+	uint32_t VDL_REGS[47];	/* 0x60-0x118 */
+	uint32_t AC_SPARE;	/* 0x11c */
+	uint32_t unused1[4];	/* 0x120-0x12f */
+
+	uint32_t REFRESH;	/* 0x130 */
+	uint32_t UPDATE_VDL;	/* 0x134 */
+	uint32_t UPDATE_VDL_SNOOP1;	/* 0x138 */
+	uint32_t UPDATE_VDL_SNOOP2;	/* 0x13c */
+	uint32_t CMND_REG1;	/* 0x140 */
+	uint32_t CMND_AUX_REG1;	/* 0x144 */
+	uint32_t CMND_REG2;	/* 0x148 */
+	uint32_t CMND_AUX_REG2;	/* 0x14c */
+	uint32_t CMND_REG3;	/* 0x150 */
+	uint32_t CMND_AUX_REG3;	/* 0x154 */
+	uint32_t CMND_REG4;	/* 0x158 */
+	uint32_t CMND_AUX_REG4;	/* 0x15c */
+	uint32_t CMND_REG_TIMER;	/* 0x160 */
+	uint32_t MODE_REG[9];	/* 0x164-184 */
+#define PHY_CONTROL_MODE_REG_VALID_SHIFT       16
+#define PHY_CONTROL_MODE_REG_VALID_MASK        (0x1<<PHY_CONTROL_MODE_REG_VALID_SHIFT)
+	uint32_t MODE_REG15;	/* 0x188 */
+	uint32_t MODE_REG63;	/* 0x18c */
+	uint32_t ALERT_CLEAR;	/* 0x190 */
+	uint32_t ALERT_STATUS;	/* 0x194 */
+	uint32_t CA_PARITY;	/* 0x198 */
+	uint32_t CA_PLAYBACK_CTRL;	/* 0x19c */
+	uint32_t CA_PLAYBACK_STATUS0;	/* 0x1a0 */
+	uint32_t CA_PLAYBACK_STATUS1;	/* 0x1a4 */
+	uint32_t unused2;	/* 0x1a8 */
+	uint32_t WRITE_LEVEL_CTRL;	/* 0x1ac */
+	uint32_t WRITE_LEVEL_STATUS;	/* 0x1b0 */
+	uint32_t READ_EN_CTRL;	/* 0x1b4 */
+	uint32_t READ_EN_STATUS;	/* 0x1b8 */
+	uint32_t unused3;	/* 0x1bc */
+	uint32_t TRAFFIC_GEN[12];	/* 0x1c0-0x1ec */
+	uint32_t VIRT_VTT_CTRL;	/* 0x1f0 */
+	uint32_t VIRT_VTT_STATUS;	/* 0x1f4 */
+	uint32_t VIRT_VTT_CONNECTION;	/* 0x1f8 */
+	uint32_t VIRT_VTT_OVERRIDE;	/* 0x1fc */
+	uint32_t VREF_DAC_CTRL;	/* 0x200 */
+	uint32_t PHYBIST[9];	/* 0x204-0x224 */
+	uint32_t unused4[2];	/* 0x228-0x22f */
+	uint32_t STANDBY_CTRL;	/* 0x230 */
+	uint32_t DEBUG_FREEZE_EN;	/* 0x234 */
+	uint32_t DEBUG_MUX_CTRL;	/* 0x238 */
+	uint32_t DFI_CTRL;	/* 0x23c */
+#define PHY_CONTROL_DFI_CNTRL_DFI_CS1_SHIFT    7
+#define PHY_CONTROL_DFI_CNTRL_DFI_CS1_MASK     (0x1<<PHY_CONTROL_DFI_CNTRL_DFI_CS1_SHIFT)
+#define PHY_CONTROL_DFI_CNTRL_DFI_CS0_SHIFT    6
+#define PHY_CONTROL_DFI_CNTRL_DFI_CS0_MASK     (0x1<<PHY_CONTROL_DFI_CNTRL_DFI_CS0_SHIFT)
+#define PHY_CONTROL_DFI_CNTRL_DFI_RSTN_SHIFT   5
+#define PHY_CONTROL_DFI_CNTRL_DFI_RSTN_MASK    (0x1<<PHY_CONTROL_DFI_CNTRL_DFI_RSTN_SHIFT)
+#define PHY_CONTROL_DFI_CNTRL_DFI_CKE1_SHIFT   4
+#define PHY_CONTROL_DFI_CNTRL_DFI_CKE1_MASK    (0x1<<PHY_CONTROL_DFI_CNTRL_DFI_CKE1_SHIFT)
+#define PHY_CONTROL_DFI_CNTRL_DFI_CKE0_SHIFT   3
+#define PHY_CONTROL_DFI_CNTRL_DFI_CKE0_MASK    (0x1<<PHY_CONTROL_DFI_CNTRL_DFI_CKE0_SHIFT)
+#define PHY_CONTROL_DFI_CNTRL_ASSERT_REQ_SHIFT 0
+#define PHY_CONTROL_DFI_CNTRL_ASSERT_REQ_MASK  (0x1<<PHY_CONTROL_DFI_CNTRL_ASSERT_REQ_SHIFT)
+	uint32_t WRITE_ODT_CTRL;	/* 0x240 */
+	uint32_t ABI_PAR_CTRL;	/* 0x244 */
+	uint32_t ZQ_CAL;	/* 0x248 */
+	uint32_t unused5[109];	/* 0x24c-0x3ff */
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+	uint32_t VDL_CTRL_WR[12];	/* 0x00 - 0x2c */
+	uint32_t VDL_CTRL_RD[24];	/* 0x30 - 0x8c */
+	uint32_t VDL_CLK_CTRL;	/* 0x90 */
+	uint32_t VDL_LDE_CTRL;	/* 0x94 */
+	uint32_t unused0[2];	/* 0x98-0x9f */
+	uint32_t RD_EN_DLY_CYC;	/* 0xa0 */
+	uint32_t WR_CHAN_DLY_CYC;	/* 0xa4 */
+	uint32_t unused1[2];	/* 0xa8-0xaf */
+	uint32_t RD_CTRL;	/* 0xb0 */
+	uint32_t RD_FIFO_ADDR;	/* 0xb4 */
+	uint32_t RD_FIFO_DATA;	/* 0xb8 */
+	uint32_t RD_FIFO_DM_DBI;	/* 0xbc */
+	uint32_t RD_FIFO_STATUS;	/* 0xc0 */
+	uint32_t RD_FIFO_CLR;	/* 0xc4 */
+	uint32_t IDLE_PAD_CTRL;	/* 0xc8 */
+	uint32_t DRIVE_PAD_CTRL;	/* 0xcc */
+	uint32_t RD_EN_DRIVE_PAD_CTRL;	/* 0xd0 */
+	uint32_t STATIC_PAD_CTRL;	/* 0xd4 */
+	uint32_t WR_PREAMBLE_MODE;	/* 0xd8 */
+	uint32_t unused2;	/* 0xdc */
+	uint32_t ODT_CTRL;	/* 0xe0 */
+	uint32_t unused3[3];	/* 0xe4-0xef */
+	uint32_t EDC_DPD_CTRL;	/* 0xf0 */
+	uint32_t EDC_DPD_STATUS;	/* 0xf4 */
+	uint32_t EDC_DPD_OUT_CTRL;	/* 0xf8 */
+	uint32_t EDC_DPD_OUT_STATUS;	/* 0xfc */
+	uint32_t EDC_DPD_OUT_STATUS_CLEAR;	/* 0x100 */
+	uint32_t EDC_CRC_CTRL;	/* 0x104 */
+	uint32_t EDC_CRC_STATUS;	/* 0x108 */
+	uint32_t EDC_CRC_COUNT;	/* 0x10c */
+	uint32_t EDC_CRC_STATUS_CLEAR;	/* 0x110 */
+	uint32_t BL_SPARE_REG;	/* 0x114 */
+	uint32_t unused4[58];
+} DDRPhyByteLaneControl;
+
+typedef struct MEMCControl {
+	uint32_t GLB_VERS;	/* 0x000 */
+	uint32_t GLB_GCFG;	/* 0x004 */
+#define MEMC_GLB_GCFG_DRAM_EN_SHIFT        31
+#define MEMC_GLB_GCFG_DRAM_EN_MASK         (0x1<<MEMC_GLB_GCFG_DRAM_EN_SHIFT)
+#define MEMC_GLB_GCFG_PHY_4X_SHIFT         24
+#define MEMC_GLB_GCFG_PHY_4X_MASK          (0x1<<MEMC_GLB_GCFG_PHY_4X_SHIFT)
+#define MEMC_GLB_GCFG_MCLKSRC_SHIFT        9
+#define MEMC_GLB_GCFG_MCLKSRC_MASK         (0x1<<MEMC_GLB_GCFG_MCLKSRC_SHIFT)
+#define MEMC_GLB_GCFG_MEMINITDONE_SHIFT    8
+#define MEMC_GLB_GCFG_MEMINITDONE_MASK     (0x1<<MEMC_GLB_GCFG_MEMINITDONE_SHIFT)
+#define MEMC_GLB_GCFG_SIZE1_SHIFT          0
+#define MEMC_GLB_GCFG_SIZE1_MASK           (0xf<<MEMC_GLB_GCFG_SIZE1_SHIFT)
+
+	uint32_t unused0[2];	/* 0x008-0x00f */
+	uint32_t GLB_CFG;	/* 0x010 */
+#define MEMC_GLB_CFG_RR_MODE_SHIFT      0x0
+#define MEMC_GLB_CFG_RR_MODE_MASK       (0x1<<MEMC_GLB_CFG_RR_MODE_SHIFT)
+#define MEMC_GLB_CFG_BURST_MODE_SHIFT   0x1
+#define MEMC_GLB_CFG_BURST_MODE_MASK    (0x1<<MEMC_GLB_CFG_BURST_MODE_SHIFT)
+	uint32_t GLB_QUE_DIS;	/* 0x014 */
+	uint32_t GLB_SP_SEL;	/* 0x018 */
+#define MEMC_GLB_SP_SEL_SELECT_MASK     0x001fffff
+	uint32_t GLB_SP_PRI_0;	/* 0x01c */
+	uint32_t GLB_SP_PRI_1;	/* 0x020 */
+	uint32_t GLB_SP_PRI_2;	/* 0x024 */
+	uint32_t GLB_SP_PRI_3;	/* 0x028 */
+	uint32_t GLB_SP_PRI_4;	/* 0x02c */
+	uint32_t GLB_SP_PRI_5;	/* 0x030 */
+	uint32_t unused1[3];	/* 0x034-0x3f */
+	uint32_t GLB_RR_QUANTUM[12];	/* 0x040-0x06c */
+	uint32_t unused2[4];	/* 0x070-0x07f */
+
+	uint32_t INTR2_CPU_STATUS;	/* 0x080 */
+	uint32_t INTR2_CPU_SET;	/* 0x084 */
+	uint32_t INTR2_CPU_CLEAR;	/* 0x088 */
+	uint32_t INTR2_CPU_MASK_STATUS;	/* 0x08c */
+	uint32_t INTR2_CPU_MASK_SET;	/* 0x090 */
+	uint32_t INTR2_CPU_MASK_CLEAR;	/* 0x094 */
+	uint32_t unused3[10];	/* 0x098-0x0bf */
+
+	uint32_t SRAM_REMAP_CTRL;	/* 0x0c0 */
+	uint32_t SRAM_REMAP_INIT;	/* 0x0c4 */
+	uint32_t SRAM_REMAP_LOG_INFO_0;	/* 0x0c8 */
+	uint32_t SRAM_REMAP_LOG_INFO_1;	/* 0x0cc */
+	uint32_t unused4[12];	/* 0x0d0-0x0ff */
+
+	uint32_t CHN_CFG_CNFG;	/* 0x100 */
+	uint32_t CHN_CFG_CSST;	/* 0x104 */
+	uint32_t CHN_CFG_CSEND;	/* 0x108 */
+	uint32_t unused5;	/* 0x10c */
+	uint32_t CHN_CFG_ROW00_0;	/* 0x110 */
+	uint32_t CHN_CFG_ROW00_1;	/* 0x114 */
+	uint32_t CHN_CFG_ROW01_0;	/* 0x118 */
+	uint32_t CHN_CFG_ROW01_1;	/* 0x11c */
+	uint32_t unused6[4];	/* 0x120-0x12f */
+	uint32_t CHN_CFG_ROW20_0;	/* 0x130 */
+	uint32_t CHN_CFG_ROW20_1;	/* 0x134 */
+	uint32_t CHN_CFG_ROW21_0;	/* 0x138 */
+	uint32_t CHN_CFG_ROW21_1;	/* 0x13c */
+	uint32_t unused7[4];	/* 0x140-0x14f */
+	uint32_t CHN_CFG_COL00_0;	/* 0x150 */
+	uint32_t CHN_CFG_COL00_1;	/* 0x154 */
+	uint32_t CHN_CFG_COL01_0;	/* 0x158 */
+	uint32_t CHN_CFG_COL01_1;	/* 0x15c */
+	uint32_t unused8[4];	/* 0x160-0x16f */
+	uint32_t CHN_CFG_COL20_0;	/* 0x170 */
+	uint32_t CHN_CFG_COL20_1;	/* 0x174 */
+	uint32_t CHN_CFG_COL21_0;	/* 0x178 */
+	uint32_t CHN_CFG_COL21_1;	/* 0x17c */
+	uint32_t unused9[4];	/* 0x180-0x18f */
+	uint32_t CHN_CFG_BNK10;	/* 0x190 */
+	uint32_t CHN_CFG_BNK32;	/* 0x194 */
+	uint32_t unused10[26];	/* 0x198-0x1ff */
+
+	uint32_t CHN_TIM_DCMD;	/* 0x200 */
+	uint32_t CHN_TIM_DMODE_0;	/* 0x204 */
+	uint32_t CHN_TIM_DMODE_2;	/* 0x208 */
+	uint32_t CHN_TIM_CLKS;	/* 0x20c */
+	uint32_t CHN_TIM_ODT;	/* 0x210 */
+	uint32_t CHN_TIM_TIM1_0;	/* 0x214 */
+	uint32_t CHN_TIM_TIM1_1;	/* 0x218 */
+	uint32_t CHN_TIM_TIM2;	/* 0x21c */
+	uint32_t CHN_TIM_CTL_CRC;	/* 0x220 */
+	uint32_t CHN_TIM_DOUT_CRC;	/* 0x224 */
+	uint32_t CHN_TIM_DIN_CRC;	/* 0x228 */
+	uint32_t CHN_TIM_CRC_CTRL;	/* 0x22c */
+	uint32_t CHN_TIM_PHY_ST;	/* 0x230 */
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP       0x1
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_HW_RESET       0x2
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_SW_RESET       0x4
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_READY          0x10
+	uint32_t CHN_TIM_DRAM_CFG;	/* 0x234 */
+#define DRAM_CFG_DRAMSLEEP          (1<<11)
+#define MEMC_CHN_TIM_DRAM_CFG_DRAM_CFG_DRAMTYPE_SHIFT 0x0
+#define MEMC_CHN_TIM_DRAM_CFG_DRAM_CFG_DRAMTYPE_MASK  (0xf<<MEMC_CHN_TIM_DRAM_CFG_DRAM_CFG_DRAMTYPE_SHIFT)
+	uint32_t CHN_TIM_STAT;	/* 0x238 */
+	uint32_t unused11[49];	/* 0x23c-0x2ff */
+
+	UBUSInterface UBUSIF0;	/* 0x300-0x33f */
+	UBUSInterface UBUSIF1;	/* 0x340-0x37f */
+
+	uint32_t AXIRIF_0_CFG;	/* 0x380 */
+	uint32_t AXIRIF_0_REP_ARB_MODE;	/* 0x384 */
+#define MEMC_AXIRIF_0_REP_ARB_MODE_FIFO_MODE_SHIFT    0x0
+#define MEMC_AXIRIF_0_REP_ARB_MODE_FIFO_MODE_MASK     (0x3<<MEMC_AXIRIF_0_REP_ARB_MODE_FIFO_MODE_SHIFT)
+	uint32_t AXIRIF_0_SCRATCH;	/* 0x388 */
+	uint32_t unused12[29];	/* 0x38c-0x3ff */
+
+	uint32_t AXIWIF_0_CFG;	/* 0x400 */
+#define MEMC_AXIWIF_0_CFG_WRITE_REPLY_MODE_SHIFT      0x0
+#define MEMC_AXIWIF_0_CFG_WRITE_REPLY_MODE_MASK       (0x1<<MEMC_AXIWIF_0_CFG_WRITE_REPLY_MODE_SHIFT)
+#define MEMC_AXIWIF_0_CFG_WRITE_BURST_MODE_SHIFT      0x1
+#define MEMC_AXIWIF_0_CFG_WRITE_BURST_MODE_MASK       (0x1<<MEMC_AXIWIF_0_CFG_WRITE_BURST_MODE_SHIFT)
+	uint32_t AXIWIF_0_REP_ARB_MODE;	/* 0x404 */
+#define MEMC_AXIWIF_0_REP_ARB_MODE_FIFO_MODE_SHIFT    0x0
+#define MEMC_AXIWIF_0_REP_ARB_MODE_FIFO_MODE_MASK     (0x1<<MEMC_AXIRIF_0_REP_ARB_MODE_FIFO_MODE_SHIFT)
+
+	uint32_t AXIWIF_0_SCRATCH;	/* 0x408 */
+	uint32_t unused13[61];	/* 0x40c-0x4ff */
+
+	EDISEngine EDIS_0;	/* 0x500 */
+	EDISEngine EDIS_1;	/* 0x600 */
+
+	uint32_t STATS_CTRL;	/* 0x700 */
+	uint32_t STATS_TIMER_CFG;	/* 0x704 */
+	uint32_t STATS_TIMER_COUNT;	/* 0x708 */
+	uint32_t STATS_TOTAL_SLICE;	/* 0x70c */
+	uint32_t STATS_TOTAL_PACKET;	/* 0x710 */
+	uint32_t STATS_SLICE_REORDER;	/* 0x714 */
+	uint32_t STATS_IDLE_DDR_CYCLE;	/* 0x718 */
+	uint32_t STATS_ARB_GRANT;	/* 0x71c */
+	uint32_t STATS_PROG_0;	/* 0x720 */
+	uint32_t STATS_PROG_1;	/* 0x724 */
+	uint32_t STATS_ARB_GRANT_MATCH;	/* 0x728 */
+	uint32_t STATS_CFG_0;	/* 0x72c */
+	uint32_t STATS_CFG_1;	/* 0x730 */
+	uint32_t unused14[19];	/* 0x734-0x77f */
+
+	uint32_t CAP_CAPTURE_CFG;	/* 0x780 */
+	uint32_t CAP_TRIGGER_ADDR;	/* 0x784 */
+	uint32_t CAP_READ_CTRL;	/* 0x788 */
+	uint32_t unused15;	/* 0x78c */
+	uint32_t CAP_CAPTURE_MATCH0;	/* 0x790 */
+	uint32_t CAP_CAPTURE_MATCH1;	/* 0x794 */
+	uint32_t CAP_CAPTURE_MATCH2;	/* 0x798 */
+	uint32_t unused16;	/* 0x79c */
+	uint32_t CAP_CAPTURE_MASK0;	/* 0x7a0 */
+	uint32_t CAP_CAPTURE_MASK1;	/* 0x7a4 */
+	uint32_t CAP_CAPTURE_MASK2;	/* 0x7a8 */
+	uint32_t unused17;	/* 0x7ac */
+	uint32_t CAP_TRIGGER_MATCH0;	/* 0x7b0 */
+	uint32_t CAP_TRIGGER_MATCH1;	/* 0x7b4 */
+	uint32_t CAP_TRIGGER_MATCH2;	/* 0x7b8 */
+	uint32_t unused18;	/* 0x7bc */
+	uint32_t CAP_TRIGGER_MASK0;	/* 0x7c0 */
+	uint32_t CAP_TRIGGER_MASK1;	/* 0x7c4 */
+	uint32_t CAP_TRIGGER_MASK2;	/* 0x7c8 */
+	uint32_t unused19;	/* 0x7cc */
+	uint32_t CAP_READ_DATA[4];	/* 0x7d0-0x7dc */
+	uint32_t unused20[8];	/* 0x7e0-0x7ff */
+
+	SecureRangeCheckers SEC_RANGE_CHK;	/* 0x800 */
+
+	uint32_t SEC_INTR2_CPU_STATUS;	/* 0x900 */
+	uint32_t SEC_INTR2_CPU_SET;	/* 0x904 */
+	uint32_t SEC_INTR2_CPU_CLEAR;	/* 0x908 */
+	uint32_t SEC_INTR2_CPU_MASK_STATUS;	/* 0x90c */
+	uint32_t SEC_INTR2_CPU_MASK_SET;	/* 0x910 */
+	uint32_t SEC_INTR2_CPU_MASK_CLEAR;	/* 0x914 */
+	uint32_t unused21[10];	/* 0x918-0x93f */
+
+	uint32_t SEC_SRAM_REMAP_CTRL;	/* 0x940 */
+	uint32_t SEC_SRAM_REMAP_INIT;	/* 0x944 */
+	uint32_t SEC_SRAM_REMAP_LOG_0;	/* 0x948 */
+	uint32_t SEC_SRAM_REMAP_LOG_1;	/* 0x94c */
+	uint32_t unused22[428];	/* 0x950-0xfff */
+
+	DDRPhyControl PhyControl;	/* 0x1000 */
+	DDRPhyByteLaneControl PhyByteLane0Control;	/* 0x1400 */
+	DDRPhyByteLaneControl PhyByteLane1Control;	/* 0x1600 */
+} MEMCControl;
+
+#define MEMC ((volatile MEMCControl * const) MEMC_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/ethsw.h b/arch/arm/include/asm/arch-bcm63138/ethsw.h
new file mode 100644
index 0000000000..d39e72da91
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/ethsw.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63138_ETHSW_H
+#define _63138_ETHSW_H
+
+#define SWITCH_BASE              0x80080000
+
+typedef struct {
+    uint32_t led_f;
+    uint32_t reserved;
+} LED_F;
+
+typedef struct EthernetSwitchCore
+{
+    uint32_t port_traffic_ctrl[9];            /* 0x00 - 0x08 */
+    uint32_t reserved1[2];                    /* 0x09 - 0x0a */
+    uint32_t switch_mode;                     /* 0x0b */
+#define ETHSW_SM_RETRY_LIMIT_DIS                  0x04
+#define ETHSW_SM_FORWARDING_EN                    0x02
+#define ETHSW_SM_MANAGED_MODE                     0x01
+    uint32_t pause_quanta;                    /* 0x0c */
+    uint32_t reserved33; 
+    uint32_t imp_port_state;                  /*0x0e */
+#define ETHSW_IPS_USE_MII_HW_STS                  0x00
+#define ETHSW_IPS_USE_REG_CONTENTS                0x80
+#define ETHSW_IPS_GMII_SPEED_UP_NORMAL            0x00
+#define ETHSW_IPS_GMII_SPEED_UP_2G                0x40
+#define ETHSW_IPS_TXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_TXFLOW_PAUSE_CAPABLE            0x20
+#define ETHSW_IPS_RXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_RXFLOW_PAUSE_CAPABLE            0x10
+#define ETHSW_IPS_SW_PORT_SPEED_1000M_2000M       0x08
+#define ETHSW_IPS_DUPLEX_MODE                     0x02
+#define ETHSW_IPS_LINK_FAIL                       0x00
+#define ETHSW_IPS_LINK_PASS                       0x01
+    uint32_t led_refresh;                     /* 0x0f */
+    LED_F        led_function[2];                 /* 0x10 */
+    uint32_t led_function_map;                /* 0x14 */
+    uint32_t reserved14; 
+    uint32_t led_enable_map;                  /* 0x16 */
+    uint32_t reserved15; 
+    uint32_t led_mode_map0;                   /* 0x18 */
+    uint32_t reserved16; 
+    uint32_t led_function_map1;               /* 0x1a */
+    uint32_t reserved17; 
+    uint32_t reserved2[5];                    /* 0x1c - 0x20 */
+    uint32_t port_forward_ctrl;               /* 0x21 */
+    uint32_t switch_ctrl;                     /* 0x22 */
+#define ETHSW_SC_MII_DUMP_FORWARDING_EN           0x40
+#define ETHSW_SC_MII2_VOL_SEL                     0x02
+    uint32_t reserved3;                       /* 0x23 */
+    uint32_t protected_port_selection;        /* 0x24 */
+    uint32_t reserved18; 
+    uint32_t wan_port_select;                 /* 0x26 */
+    uint32_t reserved19; 
+    uint32_t pause_capability;                /* 0x28 */
+    uint32_t reserved20[3]; 
+    uint32_t reserved4[3];                    /* 0x2c - 0x2e */
+    uint32_t reserved_multicast_control;      /* 0x2f */
+    uint32_t reserved5;                       /* 0x30 */
+    uint32_t txq_flush_mode_control;          /* 0x31 */
+    uint32_t ulf_forward_map;                 /* 0x32 */
+    uint32_t reserved21; 
+    uint32_t mlf_forward_map;                 /* 0x34 */
+    uint32_t reserved22; 
+    uint32_t mlf_impc_forward_map;            /* 0x36 */
+    uint32_t reserved23; 
+    uint32_t pause_pass_through_for_rx;       /* 0x38 */
+    uint32_t reserved24; 
+    uint32_t pause_pass_through_for_tx;       /* 0x3a */
+    uint32_t reserved25; 
+    uint32_t disable_learning;                /* 0x3c */
+    uint32_t reserved26; 
+    uint32_t reserved6[26];                   /* 0x3e - 0x57 */
+    uint32_t port_state_override[8];          /* 0x58 - 0x5f */
+#define ETHSW_PS_SW_OVERRIDE                      0x40
+#define ETHSW_PS_SW_TX_FLOW_CTRL_EN               0x20
+#define ETHSW_PS_SW_RX_FLOW_CTRL_EN               0x10
+#define ETHSW_PS_SW_PORT_SPEED_1000M              0x80
+#define ETHSW_PS_SW_PORT_SPEED_100M               0x40
+#define ETHSW_PS_SW_PORT_SPEED_10M                0x00
+#define ETHSW_PS_DUPLEX_MODE                      0x02
+#define ETHSW_PS_LINK_DOWN                        0x00
+#define ETHSW_PS_LINK_UP                          0x01
+    uint32_t reserved7[4];                    /* 0x60 - 0x63 */
+    uint32_t imp_rgmii_ctrl_p4;               /* 0x64 */
+    uint32_t imp_rgmii_ctrl_p5;               /* 0x65 */
+    uint32_t reserved8[6];                    /* 0x66 - 0x6b */
+    uint32_t rgmii_timing_delay_p4;           /* 0x6c */
+    uint32_t gmii_timing_delay_p5;            /* 0x6d */
+    uint32_t reserved9[11];                   /* 0x6e - 0x78 */
+    uint32_t software_reset;                  /* 0x79 */
+    uint32_t reserved13[6];                   /* 0x7a - 0x7f */
+    uint32_t pause_frame_detection;           /* 0x80 */
+    uint32_t reserved10[7];                   /* 0x81 - 0x87 */
+    uint32_t fast_aging_ctrl;                 /* 0x88 */
+    uint32_t fast_aging_port;                 /* 0x89 */
+    uint32_t fast_aging_vid;                  /* 0x8a */
+    uint32_t anonymous1[376];                 /* 0x8b */
+    uint32_t brcm_hdr_ctrl;                   /* 0x203 */
+    uint32_t anonymous2[0x2efc];              /* 0x204 */
+    uint32_t port_vlan_ctrl[9*2];               /* 0x3100 */
+} EthernetSwitchCore;
+
+#define PBMAP_MIPS 0x100
+
+typedef struct EthernetSwitchReg
+{
+    uint32_t switch_ctrl;                      /* 0x0000 */
+    uint32_t switch_status;                    /* 0x0004 */
+    uint32_t dir_data_write_reg;               /* 0x0008 */
+    uint32_t dir_data_read_reg;                /* 0x000c */
+    uint32_t led_serial_refresh_time_unit;     /* 0x0010 */
+    uint32_t reserved1;                        /* 0x0014 */
+    uint32_t switch_rev;                       /* 0x0018 */
+    uint32_t phy_rev;                          /* 0x001c */
+    uint32_t phy_test_ctrl;                    /* 0x0020 */
+    uint32_t qphy_ctrl;                        /* 0x0024 */
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT     12
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_MASK      (0x1f<<ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT)
+#define ETHSW_QPHY_CTRL_RESET_SHIFT          8
+#define ETHSW_QPHY_CTRL_RESET_MASK           (0x1<<ETHSW_QPHY_CTRL_RESET_SHIFT )
+#define ETHSW_QPHY_CTRL_CK25_DIS_SHIFT       7
+#define ETHSW_QPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_QPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_MASK    (0xf<<ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT)
+    uint32_t qphy_status;                      /* 0x0028 */
+    uint32_t sphy_ctrl;                        /* 0x002c */
+#define ETHSW_SPHY_CTRL_PHYAD_SHIFT          8
+#define ETHSW_SPHY_CTRL_PHYAD_MASK           (0x1f<<ETHSW_SPHY_CTRL_PHYAD_SHIFT)
+#define ETHSW_SPHY_CTRL_RESET_SHIFT          5
+#define ETHSW_SPHY_CTRL_RESET_MASK           (0x1<<ETHSW_SPHY_CTRL_RESET_SHIFT )
+#define ETHSW_SPHY_CTRL_CK25_DIS_SHIFT       4
+#define ETHSW_SPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_SPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_MASK    (0x1<<ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT)
+    uint32_t sphy_status;                      /* 0x0030 */
+    uint32_t reserved2[15];                    /* 0x0034 */
+    uint32_t rgmii_5_ctrl;                     /* 0x0070 */
+    uint32_t rgmii_5_ib_status;                /* 0x0074 */
+    uint32_t rgmii_5_rx_clk_delay_ctrl;        /* 0x0078 */
+    uint32_t rgmii_7_ctrl;                     /* 0x007c */
+    uint32_t rgmii_7_ib_status;                /* 0x0080 */
+    uint32_t rgmii_7_rx_clk_delay_ctrl;        /* 0x0084 */
+    uint32_t led_blink_rate_ctrl;              /* 0x0088 */
+    uint32_t led_serial_ctrl;                  /* 0x008c */
+    uint32_t led_ctrl[5];                      /* 0x0090 */
+#define ETHSW_LED_CTRL_SPD0_ON               0x0
+#define ETHSW_LED_CTRL_SPD0_OFF              0x1
+#define ETHSW_LED_CTRL_SPD1_ON               0x0
+#define ETHSW_LED_CTRL_SPD1_OFF              0x2
+#define ETHSW_LED_CTRL_1000M_SHIFT           6
+#define ETHSW_LED_CTRL_100M_SHIFT            4
+#define ETHSW_LED_CTRL_10M_SHIFT             2
+#define ETHSW_LED_CTRL_NOLINK_SHIFT          0
+#define ETHSW_LED_CTRL_ALL_SPEED_MASK        0xff
+#define ETHSW_LED_CTRL_SPEED_MASK            0x3
+    uint32_t reserved3[2];                     /* 0x00a4 */
+    uint32_t crossbar_switch_ctrl;             /* 0x00ac */
+    uint32_t reserved4[6];                     /* 0x00b0 */
+    uint32_t rgmii_11_ctrl;                    /* 0x00c8 */
+    uint32_t rgmii_11_ib_status;               /* 0x00cc */
+    uint32_t rgmii_11_rx_clk_delay_ctrl;       /* 0x00d0 */
+    uint32_t rgmii_12_ctrl;                    /* 0x00d4 */
+#define ETHSW_RC_MII_MODE_MASK               0x1c
+#define ETHSW_RC_EXT_RVMII                   0x10
+#define ETHSW_RC_EXT_GPHY                    0x0c
+#define ETHSW_RC_EXT_EPHY                    0x08
+#define ETHSW_RC_INT_GPHY                    0x04
+#define ETHSW_RC_INT_EPHY                    0x00
+#define ETHSW_RC_ID_MODE_DIS                 0x02
+#define ETHSW_RC_RGMII_EN                    0x01
+    uint32_t rgmii_12_ib_status;               /* 0x00d8 */
+    uint32_t rgmii_12_rx_clk_delay_ctrl;       /* 0x00dc */
+#define ETHSW_RXCLK_IDDQ                     (1<<4)
+#define ETHSW_RXCLK_BYPASS                   (1<<5)
+    uint32_t anonymous1[44];                   /* 0x00e0 */
+    uint32_t single_serdes_rev;                /* 0x0190 */ /* From here for B0 and late chip only */
+    uint32_t single_serdes_ctrl;               /* 0x0194 */
+    uint32_t single_serdes_stat;               /* 0x0198 */
+    uint32_t led_wan_ctrl;                     /* 0x019c */
+} EthernetSwitchReg;
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/misc.h b/arch/arm/include/asm/arch-bcm63138/misc.h
new file mode 100644
index 0000000000..e3445221b0
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/misc.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63138_MISC_H
+#define _63138_MISC_H
+
+#define MISC_BASE                               0xfffe8180
+
+#define MISC_STRAP_BUS                          0x04
+#define MISC_STRAP_BUS_OVERRIDE                 0x08
+
+#define MISC_STRAP_BUS_PMC_AVS_OVERRIDE_MARKER  (1 << 30)
+#define MISC_STRAP_BUS_SW_RESERVE_1             (0x3 << 24)
+#define MISC_STRAP_BUS_SW_BOOT_SPI_SPINAND_EMMC_MASK (0x2 << 24)	/* Bit 25 = 0 => NAND BOOT */
+#define MISC_STRAP_BUS_SW_BOOT_NORMAL_MASK      (0x1 << 24)	/* Bit 24 = 0 => Bootrom boot */
+#define MISC_STRAP_BUS_BISR_MEM_REPAIR          (1 << 23)
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT    22
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_MASK     (1 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT)
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_100MS    (1 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT)
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_50MS     (0x0 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT)
+#define MISC_STRAP_BUS_SYS_BUS_FREQ             (0x3 << 20)
+#define MISC_STRAP_BUS_A9_CORE0_BOOT            (1 << 19)
+#define MISC_STRAP_BUS_PMC_BOOT_FLASH_N         (1 << 18)
+#define MISC_STRAP_BUS_PMC_BOOT_AVS             (1 << 17)
+#define MISC_STRAP_BUS_HS_SPIM_24B_N_32B_ADDR   (1 << 16)
+#define MISC_STRAP_BUS_HS_SPIM_CLK_SLOW_N_FAST  (1 << 15)
+#define MISC_STRAP_BUS_SW_RESERVE_0             (0x7 << 12)
+#define MISC_STRAP_BUS_DISABLE_NAND_ECC         (1 << 11)
+#define MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT       10
+#define MISC_STRAP_BUS_PMC_ROM_BOOT             (1<<MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT)	/* pmc rom boot enable */
+#define MISC_STRAP_BUS_PICO_ROM_BOOT            (1 << 9)
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           4
+#define MISC_STRAP_BUS_BOOT_OPT_MASK            (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x1f << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR_1_24MHZ     (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR_2_54MHZ     (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR_2_81MHZ     (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR_4_81MHZ     (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC                (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE	(0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_LS_SPI_SLAVE_DISABLE     (1 << 3)
+#define MISC_STRAP_BUS_PCIE1_RC_MODE            (1 << 2)
+#define MISC_STRAP_BUS_PCIE0_RC_MODE            (1 << 1)
+#define MISC_STRAP_BUS_TBUS_DISABLE             (1 << 0)
+
+#ifndef __ASSEMBLER__
+/*
+ * Misc Register Set Definitions.
+ */
+typedef struct Misc {
+#define MISC_PCIE_CTRL_CORE_SOFT_RESET_MASK     (0x3)
+	uint32_t miscPCIECtrl;	/* 0x00 */
+	uint32_t miscStrapBus;	/* 0x04 */
+	uint32_t miscStrapOverride;	/* 0x08 */
+	uint32_t miscAdsl_clock_sample;	/* 0x0c */
+	uint32_t miscRngCtrl;	/* 0x10 */
+	uint32_t miscMbox0_data;	/* 0x14 */
+	uint32_t miscMbox1_data;	/* 0x18 */
+	uint32_t miscMbox2_data;	/* 0x1c */
+	uint32_t miscMbox3_data;	/* 0x20 */
+	uint32_t miscMbox_ctrl;	/* 0x24 */
+	uint32_t miscxMIIPadCtrl[4];	/* 0x28 */
+#define MISC_XMII_PAD_MODEHV                    (1 << 6)
+#define MISC_XMII_PAD_SEL_GMII                  (1 << 4)
+#define MISC_XMII_PAD_AMP_EN                    (1 << 3)
+	uint32_t miscxMIIPullCtrl[4];	/* 0x38 */
+	uint32_t miscRBUSBridgeCtrl;	/* 0x48 */
+	uint32_t miscSGMIIFiberDetect;	/* 0x4c */
+#define MISC_SGMII_FIBER_GPIO36     (1<<0)
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xfffe8000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/otp.h b/arch/arm/include/asm/arch-bcm63138/otp.h
new file mode 100644
index 0000000000..f5d92bb3dc
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/otp.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _63138_OTP_H
+#define _63138_OTP_H
+
+
+#define JTAG_OTP_BASE    0xfffebb00
+
+struct Jtag_Otp {
+    uint32_t ctrl0;       /* 0x00 */
+#define JTAG_OTP_CTRL_BYPASS_OTP_CLK        (1 << 31)
+#define JTAG_OTP_CTRL_READ_FOUT         (1 << 30)
+#define JTAG_OTP_CTRL_TESTCOL           (1 << 29)
+#define JTAG_OTP_CTRL_CPU_DEBUG_SEL     (0xf << 25)
+#define JTAG_OTP_CTRL_BURST_UART_SEL        (1 << 24)
+#define JTAG_OTP_CTRL_ACCESS_MODE       (0x2 << 22)
+#define JTAG_OTP_CTRL_PROG_EN           (1 << 21)
+#define JTAG_OTP_CTRL_DEBUG_MDE         (1 << 20)
+#define JTAG_OTP_CTRL_WRP_CONTINUE_ON_FAIL  (1 << 19)
+#define JTAG_OTP_CTRL_WRP_PROGRAM_VERIFY_FLAG   (1 << 18)
+#define JTAG_OTP_CTRL_WRP_DOUBLE_WORD       (1 << 17)
+#define JTAG_OTP_CTRL_WRP_REGC_SEL      (0x7 << 14)
+#define JTAG_OTP_CTRL_WRP_QUADFUSE      (1 << 13)
+#define JTAG_OTP_CTRL_WRP_DOUBLEFUSE        (1 << 12)
+#define JTAG_OTP_CTRL_WRP_READ4X        (1 << 11)
+#define JTAG_OTP_CTRL_WRP_READ2X        (1 << 10)
+#define JTAG_OTP_CTRL_WRP_IN_DEBUG      (1 << 9)
+#define JTAG_OTP_CTRL_COMMAND           (0x1f << 1)
+#define JTAG_OTP_CTRL_CMD_READ      (0x00 << 1)
+#define JTAG_OTP_CTRL_CMD_READBURST (0x01 << 1)
+#define JTAG_OTP_CTRL_CMD_OTP_PROG_EN   (0x02 << 1)
+#define JTAG_OTP_CTRL_CMD_OTP_PROG_DIS  (0x03 << 1)
+#define JTAG_OTP_CTRL_CMD_PRESCREEN (0x04 << 1)
+#define JTAG_OTP_CTRL_CMD_PRESCREEN_RP  (0x05 << 1)
+#define JTAG_OTP_CTRL_CMD_FLUSH     (0x06 << 1)
+#define JTAG_OTP_CTRL_CMD_NOP       (0x07 << 1)
+#define JTAG_OTP_CTRL_CMD_PROG      (0x0a << 1)
+#define JTAG_OTP_CTRL_CMD_PROG_RP   (0x0b << 1)
+#define JTAG_OTP_CTRL_CMD_PROG_OVST (0x0c << 1)
+#define JTAG_OTP_CTRL_CMD_RELOAD    (0x0d << 1)
+#define JTAG_OTP_CTRL_CMD_ERASE     (0x0e << 1)
+#define JTAG_OTP_CTRL_CMD_LOAD_RF   (0x0f << 1)
+#define JTAG_OTP_CTRL_CMD_CTRL_WR   (0x10 << 1)
+#define JTAG_OTP_CTRL_CMD_CTRL_RD   (0x11 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_HP   (0x12 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_OVST (0x13 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_VERIFY0  (0x14 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_VERIFY1  (0x15 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_FORCE0   (0x16 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_FORCE1   (0x17 << 1)
+#define JTAG_OTP_CTRL_CMD_BURNING   (0x18 << 1)
+#define JTAG_OTP_CTRL_CMD_PROG_LOCK (0x19 << 1)
+#define JTAG_OTP_CTRL_CMD_PROG_TESTCOL  (0x1a << 1)
+#define JTAG_OTP_CTRL_CMD_READ_TESTCOL  (0x1b << 1)
+#define JTAG_OTP_CTRL_CMD_READ_FOUT (0x1e << 1)
+#define JTAG_OTP_CTRL_CMD_SFT_RESET (0x1f << 1)
+
+#define JTAG_OTP_CTRL_START         (1 << 0)
+    uint32_t ctrl1;       /* 0x04 */
+#define JTAG_OTP_CTRL_CPU_MODE          (1 << 0)
+    uint32_t ctrl2;       /* 0x08 */
+    uint32_t ctrl3;       /* 0x0c */
+    uint32_t ctrl4;       /* 0x10 */
+    uint32_t status0;     /* 0x14 */
+    uint32_t status1;     /* 0x18 */
+#define JTAG_OTP_STATUS_1_PROG_OK       (1 << 2)
+#define JTAG_OTP_STATUS_1_CMD_DONE      (1 << 1)
+    uint32_t status2;     /* 0x1c */
+    uint32_t status3;     /* 0x20 */
+#define OTP_SAR_DISABLE       0
+#define OTP_VDSL_DSLDISABLE   1
+#define OTP_DIS2LINE          2
+#define OTP_VDSL_DISVDSL      3
+#define OTP_VDSL_DIS6BND      4
+#define OTP_VDSL_DISRNC       5
+    uint32_t status4;     /* 0x24 */
+#define OTP_SF2_DISABLE       32
+#define OTP_PCIE_RCAL_VALID 33
+    uint32_t status5;     /* 0x28 */
+#define OTP_SPHY_DISABLE      64
+#define OTP_RNR_DISIPSEC      75
+#define OTP_RNR_DISSHA1       76
+#define OTP_RNR_DISSHA2       77
+#define OTP_PRNR_DISAES256    78
+#define OTP_PRNR_DISAES192    79
+#define OTP_PRNR_DISAES128    80
+#define OTP_USBH_DISEHCI      81
+#define OTP_USBH_XHCIDIS      82
+#define OTP_USBD_DISABLE      83
+#define OTP_PCIE_DISABLE0     84
+#define OTP_PCIE_DISABLE1     85
+#define OTP_A9_DISC1          86
+#define OTP_A9_DISNEON        87
+#define OTP_SATA_DISABLE      88
+#define OTP_DECT_DISABLE      89
+    uint32_t status6;     /* 0x2c */
+#define OTP_TBUS_DISABLE      120
+#define OTP_PMC_BOOT          121
+    uint32_t status7;     /* 0x30 */
+#define OTP_PMC_BOOTROM       132
+#define OTP_PMC_SECUREREG     133
+#define OTP_PBMU_DISABLE      134
+    uint32_t status8;     /* 0x34 */
+    uint32_t status9;     /* 0x38 */
+#define OTP_DDR_SECUREACC     211
+#define OTP_DDR_SECIRELCK     212
+#define OTP_ECC_MREPAIR_EN    217
+};
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW       17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1 
+
+#define OTP_BRCM_MEK_MIV_ROW                17
+#define OTP_BRCM_MEK_MIV_SHIFT              7
+#define OTP_BRCM_MEK_MIV_MASK               7
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW       18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          7
+
+/* row 24 */
+#define OTP_CUST_MFG_MRKTID_ROW         24
+#define OTP_CUST_MFG_MRKTID_SHIFT       0
+#define OTP_CUST_MFG_MRKTID_MASK        0xffff
+
+#define OTP_CUST_OP_INUSE_ROW               24
+#define OTP_CUST_OP_INUSE_SHIFT             16
+#define OTP_CUST_OP_INUSE_MASK              1
+
+/* row 25 */
+#define OTP_CUST_OP_MRKTID_ROW          25
+#define OTP_CUST_OP_MRKTID_SHIFT        0
+#define OTP_CUST_OP_MRKTID_MASK         0xffff
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_CUST_OP_INUSE, OTP_CUST_OP_INUSE_ROW, OTP_CUST_OP_INUSE_MASK, OTP_CUST_OP_INUSE_SHIFT, 1},				\
+}
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/pmc.h b/arch/arm/include/asm/arch-bcm63138/pmc.h
new file mode 100644
index 0000000000..6b46ab9cbb
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/pmc.h
@@ -0,0 +1,400 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63138_PMC_H
+#define _63138_PMC_H
+
+#define PMC_BASE                               0x80400000
+#define PROC_MON_BASE                          0x80480000
+#define PMBM0_BASE                             0x804800c0
+#define PMBM1_BASE                             0x804800e0
+
+/*
+#####################################################################
+# PMC registers
+#####################################################################
+*/
+
+#define PMC_CONTROL_HOST_MBOX_IN               0x1028
+#define PMC_CONTROL_HOST_MBOX_OUT              0x102c
+
+#define PMC_DQM_BASE                           (PMC_BASE+0x1800)
+#define PMC_DQM_NOT_EMPTY_IRQ_STS              0x18
+#define PMC_DQM_QUEUE_RST                      0x1c
+#define PMC_DQM_NOT_EMPTY_STS                  0x20
+
+#define PMC_DQM_QUEUE_CNTRL_BASE               (PMC_BASE+0x1a00)
+#define PMC_DQM_QUEUE_DATA_BASE                (PMC_BASE+0x1c00)
+
+#define PMC_DQM_QUEUE_DATA_HOST_TO_PMC         0x0
+#define PMC_DQM_QUEUE_DATA_PMC_TO_HOST         0x10
+
+/*
+#####################################################################
+# PMB registers
+#####################################################################
+*/
+#define PMB_CNTRL                             0x0
+#define PMB_CNTRL_START_SHIFT                 31
+#define PMB_CNTRL_START_MASK                  (1<<PMB_CNTRL_START_SHIFT)
+#define PMB_CNTRL_TIMEOUT_ERR_SHIFT           30
+#define PMB_CNTRL_TIMEOUT_ERR_MASK            (1<<PMB_CNTRL_TIMEOUT_ERR_SHIFT)
+#define PMB_CNTRL_SLAVE_ERR_SHIFT             29
+#define PMB_CNTRL_SLAVE_ERR_MASK              (1<<PMB_CNTRL_SLAVE_ERR_SHIFT)
+#define PMB_CNTRL_BUSY_SHIFT                  28
+#define PMB_CNTRL_BUSY_MASK                   (1<<PMB_CNTRL_BUSY_SHIFT)
+#define PMB_CNTRL_CMD_SHIFT                   20
+#define PMB_CNTRL_CMD_MASK                    (0xf<<PMB_CNTRL_CMD_SHIFT)
+#define PMB_CNTRL_ADDR_SHIFT                  0
+#define PMB_CNTRL_ADDR_MASK                   (0xfffff<<PMB_CNTRL_ADDR_SHIFT)
+
+#define PMB_WR_DATA                           0x4
+#define PMB_TIMEOUT                           0x8
+#define PMB_RD_DATA                           0xc
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Power Management Control
+ */
+typedef struct PmcCtrlReg {
+	/* 0x00 */
+	uint32_t l1Irq4keMask;
+	uint32_t l1Irq4keStatus;
+	uint32_t l1IrqMipsMask;
+	uint32_t l1IrqMipsStatus;
+	/* 0x10 */
+	uint32_t l2IrqGpMask;
+	uint32_t l2IrqGpStatus;
+	uint32_t gpTmr0Ctl;
+	uint32_t gpTmr0Cnt;
+	/* 0x20 */
+	uint32_t gpTmr1Ctl;
+	uint32_t gpTmr1Cnt;
+	uint32_t hostMboxIn;
+	uint32_t hostMboxOut;
+	/* 0x30 */
+#define PMC_CTRL_GP_FLASH_BOOT_STALL                  0x00000080
+	uint32_t gpOut;
+	uint32_t gpIn;
+	uint32_t gpInIrqMask;
+	uint32_t gpInIrqStatus;
+	/* 0x40 */
+	uint32_t dmaCtrl;
+	uint32_t dmaStatus;
+	uint32_t dma0_3FifoStatus;
+	uint32_t unused0[3];	/* 0x4c-0x57 */
+	/* 0x58 */
+	uint32_t l1IrqMips1Mask;
+	uint32_t diagControl;
+	/* 0x60 */
+	uint32_t diagHigh;
+	uint32_t diagLow;
+	uint32_t badAddr;
+	uint32_t addr1WndwMask;
+	/* 0x70 */
+	uint32_t addr1WndwBaseIn;
+	uint32_t addr1WndwBaseOut;
+	uint32_t addr2WndwMask;
+	uint32_t addr2WndwBaseIn;
+	/* 0x80 */
+	uint32_t addr2WndwBaseOut;
+	uint32_t scratch;
+	uint32_t tm;
+	uint32_t softResets;
+	/* 0x90 */
+	uint32_t eb2ubusTimeout;
+	uint32_t m4keCoreStatus;
+	uint32_t gpInIrqSense;
+	uint32_t ubSlaveTimeout;
+	/* 0xa0 */
+	uint32_t diagEn;
+	uint32_t devTimeout;
+	uint32_t ubusErrorOutMask;
+	uint32_t diagCaptStopMask;
+	/* 0xb0 */
+	uint32_t revId;
+	uint32_t gpTmr2Ctl;
+	uint32_t gpTmr2Cnt;
+	uint32_t legacyMode;
+	/* 0xc0 */
+	uint32_t smisbMonitor;
+	uint32_t diagCtrl;
+	uint32_t diagStat;
+	uint32_t diagMask;
+	/* 0xd0 */
+	uint32_t diagRslt;
+	uint32_t diagCmp;
+	uint32_t diagCapt;
+	uint32_t diagCnt;
+	/* 0xe0 */
+	uint32_t diagEdgeCnt;
+	uint32_t unused1[4];	/* 0xe4-0xf3 */
+	/* 0xf4 */
+	uint32_t iopPeriphBaseAddr;
+	uint32_t lfsr;
+	uint32_t unused2;	/* 0xfc-0xff */
+} PmcCtrlReg;
+
+typedef struct PmcOutFifoReg {
+	uint32_t msgCtrl;	/* 0x00 */
+	uint32_t msgSts;	/* 0x04 */
+	uint32_t unused[14];	/* 0x08-0x3f */
+	uint32_t msgData[16];	/* 0x40-0x7c */
+} PmcOutFifoReg;
+
+typedef struct PmcInFifoReg {
+	uint32_t msgCtrl;	/* 0x00 */
+	uint32_t msgSts;	/* 0x04 */
+	uint32_t unused[13];	/* 0x08-0x3b */
+	uint32_t msgLast;	/* 0x3c */
+	uint32_t msgData[16];	/* 0x40-0x7c */
+} PmcInFifoReg;
+
+typedef struct PmcDmaReg {
+	/* 0x00 */
+	uint32_t src;
+	uint32_t dest;
+	uint32_t cmdList;
+	uint32_t lenCtl;
+	/* 0x10 */
+	uint32_t rsltSrc;
+	uint32_t rsltDest;
+	uint32_t rsltHcs;
+	uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+	/* 0x00 */
+	uint32_t bufSize;
+	uint32_t bufBase;
+	uint32_t idx2ptrIdx;
+	uint32_t idx2ptrPtr;
+	/* 0x10 */
+	uint32_t unused[2];
+	uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+	/* 0x00 */
+	uint32_t dcacheHit;
+	uint32_t dcacheMiss;
+	uint32_t icacheHit;
+	uint32_t icacheMiss;
+	/* 0x10 */
+	uint32_t instnComplete;
+	uint32_t wtbMerge;
+	uint32_t wtbNoMerge;
+	uint32_t itlbHit;
+	/* 0x20 */
+	uint32_t itlbMiss;
+	uint32_t dtlbHit;
+	uint32_t dtlbMiss;
+	uint32_t jtlbHit;
+	/* 0x30 */
+	uint32_t jtlbMiss;
+	uint32_t powerSubZone;
+	uint32_t powerMemPda;
+	uint32_t freqScalarCtrl;
+	/* 0x40 */
+	uint32_t freqScalarMask;
+} PmcPerfPowReg;
+
+typedef struct PmcDQMReg {
+	/* 0x00 */
+	uint32_t cfg;
+	uint32_t _4keLowWtmkIrqMask;
+	uint32_t mipsLowWtmkIrqMask;
+	uint32_t lowWtmkIrqMask;
+	/* 0x10 */
+	uint32_t _4keNotEmptyIrqMask;
+	uint32_t mipsNotEmptyIrqMask;
+	uint32_t notEmptyIrqSts;
+	uint32_t queueRst;
+	/* 0x20 */
+	uint32_t notEmptySts;
+	uint32_t nextAvailMask;
+	uint32_t nextAvailQueue;
+	uint32_t mips1LowWtmkIrqMask;
+	/* 0x30 */
+	uint32_t mips1NotEmptyIrqMask;
+	uint32_t autoSrcPidInsert;
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+	uint32_t cntr[10];
+	uint32_t unused[6];	/* 0x28-0x3f */
+	uint32_t cntrIrqMask;
+	uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+	uint32_t size;
+	uint32_t cfga;
+	uint32_t cfgb;
+	uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+	uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+	uint32_t qNumFull[32];
+	uint32_t qNumEmpty[32];
+	uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+typedef struct Pmc {
+	uint32_t baseReserved;	/* 0x0000 */
+	uint32_t unused0[1023];
+	PmcCtrlReg ctrl;	/* 0x1000 */
+
+	PmcOutFifoReg outFifo;	/* 0x1100 */
+	uint32_t unused1[32];	/* 0x1180-0x11ff */
+	PmcInFifoReg inFifo;	/* 0x1200 */
+	uint32_t unused2[32];	/* 0x1280-0x12ff */
+
+	PmcDmaReg dma[2];	/* 0x1300 */
+	uint32_t unused3[48];	/* 0x1340-0x13ff */
+
+	PmcTokenReg token;	/* 0x1400 */
+	uint32_t unused4[121];	/* 0x141c-0x15ff */
+
+	PmcPerfPowReg perfPower;	/* 0x1600 */
+	uint32_t unused5[47];	/* 0x1644-0x16ff */
+
+	uint32_t msgId[32];	/* 0x1700 */
+	uint32_t unused6[32];	/* 0x1780-0x17ff */
+
+	PmcDQMReg dqm;		/* 0x1800 */
+	uint32_t unused7[50];	/* 0x1838-0x18ff */
+
+	PmcCntReg hwCounter;	/* 0x1900 */
+	uint32_t unused8[46];	/* 0x1948-0x19ff */
+
+	PmcDqmQCtrlReg dqmQCtrl[32];	/* 0x1a00 */
+	PmcDqmQDataReg dqmQData[32];	/* 0x1c00 */
+	uint32_t unused9[64];	/* 0x1e00-0x1eff */
+
+	uint32_t qStatus[32];	/* 0x1f00 */
+	uint32_t unused10[32];	/* 0x1f80-0x1fff */
+
+	PmcDqmQMibReg qMib;	/* 0x2000 */
+	uint32_t unused11[1952];	/* 0x2180-0x3ffff */
+
+	uint32_t sharedMem[8192];	/* 0x4000-0xbffc */
+} Pmc;
+
+#define PMC ((volatile Pmc * const) PMC_BASE)
+
+/*
+ * Process Monitor Module
+ */
+typedef struct PMRingOscillatorControl {
+	uint32_t control;
+	uint32_t en_lo;
+	uint32_t en_mid;
+	uint32_t en_hi;
+	uint32_t idle_lo;
+	uint32_t idle_mid;
+	uint32_t idle_hi;
+} PMRingOscillatorControl;
+
+#define RCAL_0P25UM_HORZ          0
+#define RCAL_0P25UM_VERT          1
+#define RCAL_0P5UM_HORZ           2
+#define RCAL_0P5UM_VERT           3
+#define RCAL_1UM_HORZ             4
+#define RCAL_1UM_VERT             5
+#define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
+#define PMMISC_RMON_VALID_MASK    (0x1<<16)
+typedef struct PMMiscControl {
+	uint32_t gp_out;
+	uint32_t clock_select;
+	uint32_t unused[2];
+	uint32_t misc[4];
+} PMMiscControl;
+
+typedef struct PMSSBMasterControl {
+	uint32_t control;
+#define PMC_SSBM_CONTROL_SSB_START  (1<<15)
+#define PMC_SSBM_CONTROL_SSB_ADPRE  (1<<13)
+#define PMC_SSBM_CONTROL_SSB_EN     (1<<12)
+#define PMC_SSBM_CONTROL_SSB_CMD_SHIFT (10)
+#define PMC_SSBM_CONTROL_SSB_CMD_MASK  (0x3 << PMC_SSBM_CONTROL_SSB_CMD_SHIFT)
+#define PMC_SSBM_CONTROL_SSB_CMD_READ  (2)
+#define PMC_SSBM_CONTROL_SSB_CMD_WRITE (1)
+#define PMC_SSBM_CONTROL_SSB_ADDR_SHIFT   (0)
+#define PMC_SSBM_CONTROL_SSB_ADDR_MASK (0x3ff << PMC_SSBM_CONTROL_SSB_ADDR_SHIFT)
+	uint32_t wr_data;
+	uint32_t rd_data;
+} PMSSBMasterControl;
+
+typedef struct PMEctrControl {
+	uint32_t control;
+	uint32_t interval;
+	uint32_t thresh_lo;
+	uint32_t thresh_hi;
+	uint32_t count;
+} PMEctrControl;
+
+typedef struct PMBMaster {
+	uint32_t ctrl;
+#define PMC_PMBM_START     (1 << 31)
+#define PMC_PMBM_TIMEOUT   (1 << 30)
+#define PMC_PMBM_SLAVE_ERR (1 << 29)
+#define PMC_PMBM_BUSY      (1 << 28)
+#define PMC_PMBM_Read      (0 << 20)
+#define PMC_PMBM_Write     (1 << 20)
+	uint32_t wr_data;
+	uint32_t timeout;
+	uint32_t rd_data;
+	uint32_t unused[4];
+} PMBMaster;
+
+typedef struct PMAPVTMONControl {
+	uint32_t control;
+	uint32_t reserved;
+	uint32_t cfg_lo;
+	uint32_t cfg_hi;
+	uint32_t data;
+	uint32_t vref_data;
+	uint32_t unused[2];
+	uint32_t ascan_cfg;
+	uint32_t warn_temp;
+	uint32_t reset_temp;
+	uint32_t temp_value;
+	uint32_t data1_value;
+	uint32_t data2_value;
+	uint32_t data3_value;
+} PMAPVTMONControl;
+
+typedef struct PMUBUSCfg {
+	uint32_t window[8];
+	uint32_t control;
+} PMUBUSCfg;
+
+typedef struct ProcessMonitorRegs {
+	uint32_t MonitorCtrl;	/* 0x00 */
+	uint32_t unused0[7];
+	PMRingOscillatorControl ROSC;	/* 0x20 */
+	uint32_t unused1;
+	PMMiscControl Misc;	/* 0x40 */
+	PMSSBMasterControl SSBMaster;	/* 0x60 */
+	uint32_t unused2[5];
+	PMEctrControl Ectr;	/* 0x80 */
+	uint32_t unused3[11];
+	PMBMaster PMBM[2];	/* 0xc0 */
+	PMAPVTMONControl APvtmonCtrl;	/* 0x100 */
+	uint32_t unused4[9];
+	PMUBUSCfg UBUSCfg;	/* 0x160 */
+} ProcessMonitorRegs;
+
+#define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE)
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/pmc_addr.h b/arch/arm/include/asm/arch-bcm63138/pmc_addr.h
new file mode 100644
index 0000000000..eaee85b978
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/pmc_addr.h
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef PMC_ADDR_63138_H__
+#define PMC_ADDR_63138_H__
+
+#define PMB_BUS_MAX			2
+#define PMB_BUS_ID_SHIFT		8
+
+#define PMB_BUS_APM			1
+#define PMB_ADDR_APM			(0 | PMB_BUS_APM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_APM			5
+
+//--------- SOFT Reset bits for APM ------------------------
+#define   BPCM_APM_SRESET_HARDRST_N   0x00000040
+#define   BPCM_APM_SRESET_AUDIO_N     0x00000020
+#define   BPCM_APM_SRESET_PCM_N       0x00000010
+#define   BPCM_APM_SRESET_HVGA_N      0x00000008
+#define   BPCM_APM_SRESET_HVGB_N      0x00000004
+#define   BPCM_APM_SRESET_BMU_N       0x00000002
+#define   BPCM_APM_SRESET_200_N       0x00000001
+
+#define PMB_BUS_SWITCH			1
+#define PMB_ADDR_SWITCH			(1 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SWITCH		3
+
+#define PMB_BUS_CHIP_CLKRST		1
+#define PMB_ADDR_CHIP_CLKRST		(2 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST		0
+
+#define PMB_BUS_SATA			0
+#define PMB_ADDR_SATA			(3 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SATA			1
+
+#define PMB_BUS_AIP			0
+#define PMB_ADDR_AIP			(4 | PMB_BUS_AIP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_AIP			1
+
+#define PMB_BUS_DECT_UBUS		0
+#define PMB_ADDR_DECT_UBUS		(5 | PMB_BUS_DECT_UBUS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_DECT_UBUS		1
+
+#define PMB_BUS_SAR			1
+#define PMB_ADDR_SAR			(6 | PMB_BUS_SAR << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SAR			1
+
+#define PMB_BUS_RDP			1
+#define PMB_ADDR_RDP			(7 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_RDP			2
+
+#define PMB_BUS_MEMC			0
+#define PMB_ADDR_MEMC			(8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC			1
+
+#define PMB_BUS_PERIPH			0
+#define PMB_ADDR_PERIPH			(9 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH		3
+
+#define PMB_BUS_SYSPLL			1
+#define PMB_ADDR_SYSPLL			(10 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL		0
+
+#define PMB_BUS_RDPPLL			1
+#define PMB_ADDR_RDPPLL			(11 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_RDPPLL		0
+
+#define PMB_BUS_SYSPLL2			0
+#define PMB_ADDR_SYSPLL2		(12 | PMB_BUS_SYSPLL2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL2		0
+
+#define PMB_BUS_SYSPLL3			0
+#define PMB_ADDR_SYSPLL3		(13 | PMB_BUS_SYSPLL3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL3		0
+
+#define PMB_BUS_SYSPLL4			0
+#define PMB_ADDR_SYSPLL4		(14 | PMB_BUS_SYSPLL4 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL4		0
+
+#define PMB_BUS_PCIE0			0
+#define PMB_ADDR_PCIE0			(15 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0			1
+
+#define PMB_BUS_PCIE1			0
+#define PMB_ADDR_PCIE1			(16 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1			1
+
+#define PMB_BUS_USB30_2X		1
+#define PMB_ADDR_USB30_2X		(17 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB30_2X		4
+
+#define PMB_BUS_PSAB			0
+#define PMB_ADDR_PSAB			(18 | PMB_BUS_PSAB << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PSAB			1	// not shown in spreadsheet
+
+#define PMB_BUS_PSBC			0
+#define PMB_ADDR_PSBC			(19 | PMB_BUS_PSBC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PSBC			1	// not shown in spreadsheet
+
+#define PMB_BUS_EGPHY			0
+#define PMB_ADDR_EGPHY			(20 | PMB_BUS_EGPHY << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_EGPHY			1	// not shown in spreadsheet
+
+#define PMB_BUS_VDSL3_MIPS		0
+#define PMB_ADDR_VDSL3_MIPS		(21 | PMB_BUS_VDSL3_MIPS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_VDSL3_MIPS		1
+
+#define PMB_BUS_VDSL3_CORE		0
+#define PMB_ADDR_VDSL3_CORE		(22 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_VDSL3_CORE		3
+
+#define AFEPLL_PMB_BUS_VDSL3_CORE	0
+#define AFEPLL_PMB_ADDR_VDSL3_CORE	(23 | AFEPLL_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
+#define AFEPLL_PMB_ZONES_VDSL3_CORE	0
+
+#define UBUS_PMB_BUS_VDSL3_CORE		PMB_BUS_VDSL3_CORE
+#define UBUS_PMB_ADDR_VDSL3_CORE	(24 | UBUS_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
+#define UBUS_PMB_ZONES_VDSL3_CORE	0
+
+#define UBUS_PMB_BUS_VDSL3_MIPS		PMB_BUS_VDSL3_MIPS
+#define UBUS_PMB_ADDR_VDSL3_MIPS	(25 | UBUS_PMB_BUS_VDSL3_MIPS << PMB_BUS_ID_SHIFT)
+#define UBUS_PMB_ZONES_VDSL3_MIPS	0
+
+#define UBUS_PMB_BUS_DECT		PMB_BUS_DECT_UBUS
+#define UBUS_PMB_ADDR_DECT		(26 | UBUS_PMB_BUS_DECT << PMB_BUS_ID_SHIFT)
+#define UBUS_PMB_ZONES_DECT		0
+
+#define UBUS_PMB_BUS_ARM		PMB_BUS_AIP
+#define UBUS_PMB_ADDR_ARM		(27 | UBUS_PMB_BUS_ARM << PMB_BUS_ID_SHIFT)
+#define UBUS_PMB_ZONES_ARM		0
+
+#define UBUS_PMB_BUS_DAP		PMB_BUS_AIP
+#define UBUS_PMB_ADDR_DAP		(28 | UBUS_PMB_BUS_DAP << PMB_BUS_ID_SHIFT)
+#define UBUS_PMB_ZONES_DAP		0
+
+#define UBUS_CFG0_PMB_BUS_SAR		PMB_BUS_SAR
+#define UBUS_CFG0_PMB_ADDR_SAR		(29 | UBUS_CFG0_PMB_BUS_SAR << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG0_PMB_ZONES_SAR		0
+
+#define UBUS_CFG1_PMB_BUS_SAR		PMB_BUS_SAR
+#define UBUS_CFG1_PMB_ADDR_SAR		(30 | UBUS_CFG1_PMB_BUS_SAR << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG1_PMB_ZONES_SAR		0
+
+#define UBUS_CFG_PMB_BUS_DBR		PMB_BUS_RDP
+#define UBUS_CFG_PMB_ADDR_DBR		(31 | UBUS_CFG_PMB_BUS_DBR << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_DBR		0
+
+#define UBUS_CFG_PMB_BUS_RABR		PMB_BUS_RDP
+#define UBUS_CFG_PMB_ADDR_RABR		(32 | UBUS_CFG_PMB_BUS_RABR << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_RABR		0
+
+#define UBUS_CFG_PMB_BUS_RBBR		PMB_BUS_RDP
+#define UBUS_CFG_PMB_ADDR_RBBR		(33 | UBUS_CFG_PMB_BUS_RBBR << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_RBBR		0
+
+#define UBUS_CFG_PMB_BUS_APM 		PMB_BUS_APM
+#define UBUS_CFG_PMB_ADDR_APM 		(34 | UBUS_CFG_PMB_BUS_APM << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_APM 		0
+
+#define UBUS_CFG_PMB_BUS_PCIE0 		PMB_BUS_PCIE0
+#define UBUS_CFG_PMB_ADDR_PCIE0 	(35 | UBUS_CFG_PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_PCIE0 	0
+
+#define UBUS_CFG_PMB_BUS_PCIE1 		PMB_BUS_PCIE1
+#define UBUS_CFG_PMB_ADDR_PCIE1 	(36 | UBUS_CFG_PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_PCIE1 	0
+
+#define UBUS_CFG_PMB_BUS_USBH 		PMB_BUS_USB30_2X
+#define UBUS_CFG_PMB_ADDR_USBH 		(37 | UBUS_CFG_PMB_BUS_USBH << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_USBH 	0
+
+#define UBUS_CFG_PMB_BUS_USBD 		PMB_BUS_USB30_2X
+#define UBUS_CFG_PMB_ADDR_USBD 		(38 | UBUS_CFG_PMB_BUS_USBD << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_USBD 	0
+
+#define UBUS_CFG_PMB_BUS_SWITCH		PMB_BUS_SWITCH
+#define UBUS_CFG_PMB_ADDR_SWITCH	(39 | UBUS_CFG_PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_SWITCH	0
+
+#define UBUS_CFG_PMB_BUS_PERIPH		PMB_BUS_PERIPH
+#define UBUS_CFG_PMB_ADDR_PERIPH	(40 | UBUS_CFG_PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_PERIPH	0
+
+#define UBUS_CFG_PMB_BUS_SATA  		PMB_BUS_SATA
+#define UBUS_CFG_PMB_ADDR_SATA  	(41 | UBUS_CFG_PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_SATA  	0
+
+/* define Zone enum for each block here */
+#ifndef __ASSEMBLER__
+enum {
+	APM_Zone_Main,
+	APM_Zone_Audio,
+	APM_Zone_PCM,
+	APM_Zone_HVG,
+	APM_Zone_BMU,
+};
+#endif // #ifndef __ASSEMBLER__
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm63138/pmc_drv_cfg.h
new file mode 100644
index 0000000000..718a4f2204
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/pmc_drv_cfg.h
@@ -0,0 +1,38 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_1_X
+
+#define PMC_CPU_BIG_ENDIAN   1
+#define PMC_GETRCAL_SUPPORT  1
+#define PMC_STALL_SUPPORT    1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm63138/pmc_ll_init.h b/arch/arm/include/asm/arch-bcm63138/pmc_ll_init.h
new file mode 100644
index 0000000000..131392e718
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/pmc_ll_init.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include <asm/arch/pmc.h>
+#include <asm/arch/pmc_addr.h>
+#include <asm/arch/misc.h>
+
+#define SETLEDS(a,b,c,d)
+
+/*  *********************************************************************
+    *  This function power up any necessary modules that are controlled by
+    *  PMC for board to boot such as vdsl.
+    *  This is called when still executing in place on flash
+    ********************************************************************* */
+pmc_ll_init:
+
+	ldr	r0, =MISC_BASE	/* check if PMC ROM is enabled or not */
+	ldr	r0, [r0, #MISC_STRAP_BUS]
+	lsr	r0, #MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT
+	ands	r0, #0x1
+	beq	pmbd
+
+	SETLEDS('P','M','C','S')
+	b	pmcs
+pmbd:
+	SETLEDS('P','M','B','S')
+pmcs:
+
+	/* workaround for the high temp lock issue. no need for 148 because
+	   these setting are already in the chip */
+#if defined(CONFIG_BCM63138)
+	/* config AFE PLL */
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x5		/*  cfg[0] reg offset in PLL_BPCM_REGS */ 
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	mov	r0, #1
+	lsl	r0, #27
+	orr	r2, r1, r0
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x5		/* cfg[0] reg offset in PLL_BPCM_REGS */
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* overwrite ndiv and pdiv */
+	ldr	r2, =0x80000001
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x12		/* pdiv reg offset in PLL_BPCM_REGS */
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	ldr	r2, =0x80000030
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x11		/* ndiv reg offset in PLL_BPCM_REGS */
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+#endif
+
+	/* start AFE PLL */
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x4		 /* resets reg offset in PLL_BPCM_REGS */ 
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	orr	r2, r1, #0x3
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x4		 /* resets reg offset in PLL_BPCM_REGS */
+	bl	 pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* wait AFE PLL to lock */
+afel:
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xa
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Wait for AFE PLL lock: repeat read until bit 31 (AFE PLL lock bit) is set */
+	ldr	r0, =0x80000000
+	and	r1, r0
+	cmp	r1, #0		 /* if bit 31 is not one, repeat read of reg 0x1700a */
+	beq	afel
+
+	/* AFE is locked, commence LMEM init */
+	/* Enable VDSL step 0. Power on zone 0, 1 and 2 */
+	mov	r5, #0x10
+pwr_zone_vdsl:
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, r5
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	ldr	r0, =0x1d00
+	orr	r2, r0, r1
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, r5
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	add	r5, #4
+	/* zone 0 starts from 0x10 offset */
+	cmp	r5, #(0x10+4*PMB_ZONES_VDSL3_CORE)
+	bne	pwr_zone_vdsl
+
+	/* Enable VDSL step 1: initiate a read of register 0x1600a via the PMC message handler */
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xa
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable VDSL step 1: or data with 0xffffff01 and write back into 0x1600a */ 
+	ldr	r0, =0xffffff01
+	orr	r2, r0, r1
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xa
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable VDSL step 2   : initiate a read of register 0x1600c via the PMC message handler */
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xc
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable VDSL step 2   : set the bottom two bits high and rewrite back into 0x1600c */
+	mov	r0, #0x3
+	orr	r2, r0, r1
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xc
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable VDSL step 3: initiate a read of register 0x1600a via the PMC message handler */
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xa
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable VDSL step 3   : write to reg 0x1600a */
+	ldr	r0, =0xffffff03
+	orr	r2, r0, r1
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xa
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable PCM_BMU zones */
+	mov	r5, #0x10
+pwr_zone_apm:
+	mov	r0, #PMB_ADDR_APM
+	mov	r1, r5
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	ldr	r0, =0x1d00
+	orr	r2, r0, r1
+	mov	r0, #PMB_ADDR_APM
+	mov	r1, r5
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	add	r5, #4
+	/* zone 0 starts from 0x10 offset */
+	cmp	r5, #(0x10+4*PMB_ZONES_APM)
+	bne	pwr_zone_apm
+
+	/* Move LDO reference to make it settle to the right voltage */
+	ldr	r0, =0x80100130
+	ldr	r1, [r0]
+	//set bit[15] high
+	ldr	r2, =0x8000
+	orr	r1, r2
+	str	r1, [r0]
+
+#if defined(CONFIG_BCM63138)
+	/* 63148 does not need to deassert */
+	//Wait 550usec de-assert bit[15].
+	ldr	r2, =110000
+w2:
+	sub	r2, #1
+	cmp	r2, #0
+	bne	w2
+	ldr	r1, [r0]
+	bic	r1, #0x8000
+	str	r1, [r0]
+#endif
+
+	b	pmc_done
+
+pmc_error:
+	SETLEDS('P','M','C','E')
+	mov	r0, #1
+	/* failed to power lmem? dead and stuck here */
+	b	pmc_error
+
+pmc_done:
+	SETLEDS('P','M','C','D')
+	mov	r0, #0
diff --git a/arch/arm/include/asm/arch-bcm63138/rdp.h b/arch/arm/include/asm/arch-bcm63138/rdp.h
new file mode 100644
index 0000000000..7b691ef1be
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/rdp.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63138_RDP_H
+#define _63138_RDP_H
+
+#define RDP_BASE            0x80200000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/rng.h b/arch/arm/include/asm/arch-bcm63138/rng.h
new file mode 100644
index 0000000000..4bb26eca98
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63138_RNG_H
+#define _63138_RNG_H
+
+#define RNG_BASE	0xfffe8300
+
+typedef struct Rng {
+	uint32_t ctrl0;			/* 0x00 */
+	uint32_t rngSoftReset;		/* 0x04 */
+	uint32_t rbgSoftReset;		/* 0x08 */
+	uint32_t totalBitCnt;		/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;			/* 0x14 */
+	uint32_t intStatus;		/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL	(0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL	(0x1<<2)
+	uint32_t intEn;			/* 0x1c */
+	uint32_t rngFifoData;		/* 0x20 */
+	uint32_t fifoCnt;		/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS	0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS	0x33
+	uint32_t perm;			/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/timer.h b/arch/arm/include/asm/arch-bcm63138/timer.h
new file mode 100644
index 0000000000..ae751bf315
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/timer.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63138_TIMER_H
+#define _63138_TIMER_H
+
+#define TIMR_BASE                               0xfffe8080
+
+#define TIMER_CLKRSTCTL                         0x2c
+#define TIMER_CLKRSTCTL_FAP1_PLL_CLKEN          (1<<11)
+#define TIMER_CLKRSTCTL_FAP2_PLL_CLKEN          (1<<15)
+#define TIMER_WD_RESET                          0x34
+#define TIMER_RESET_STATUS                      0x38
+#define TIMER_RESET_STATUS_POR                  (1 << 31)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63138/unimac.h b/arch/arm/include/asm/arch-bcm63138/unimac.h
new file mode 100644
index 0000000000..2f389301ef
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63138/unimac.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63138_UNIMAC_H
+#define _63138_UNIMAC_H
+
+#define UNIMAC_BASE         0x802d4000
+#define UNIMAC_CFG_BASE     UNIMAC_BASE + 0x00000000
+#define UNIMAC_MIB_BASE     UNIMAC_BASE + 0x00006000
+#define UNIMAC_TOP_BASE     UNIMAC_BASE + 0x00007800
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63146/BPCM.h b/arch/arm/include/asm/arch-bcm63146/BPCM.h
new file mode 100644
index 0000000000..10d297466a
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/BPCM.h
@@ -0,0 +1,826 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmbAddr:12;	// [11:00]
+		uint32_t map_rev:4;	// [15:12] always non-zero for AVS3 devices (see CLASSIC_BPCM_ID_REG below)
+		uint32_t island:4;	// [19:16]
+		uint32_t devType:4;	// [23:20] see enum above
+		uint32_t hw_rev:8;	// [31:24]
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+// types of PMB devices
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:6;
+		uint32_t reserved0:2;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu_reset_n:8;	// 07:00    R/W
+		uint32_t c0l2_reset:1;	// 08:08    R/W
+		uint32_t c1l2_reset:1;	// 09:09    R/W
+		uint32_t reserved0:6;	// 15:10    R/O
+		uint32_t cpu_bpcm_init_on:8;	// 23:16    R/W
+		uint32_t c0l2_bpcm_init_on:1;	// 24:24    R/W
+		uint32_t c1l2_bpcm_init_on:1;	// 25:25    R/W
+		uint32_t ubus_sr:1;	// 26:26    R/W
+		uint32_t cci_sr:1;	// 27:27    R/W
+		uint32_t webcores_sr:1;	// 28:28    R/W
+		uint32_t hw_done:1;	// 29:29    R/O
+		uint32_t sw_done:1;	// 30:30    R/W
+		uint32_t start:1;	// 31:31    R/W
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;		// 09:00
+		uint32_t reserved0:2;		// 11:10
+		uint32_t fref_eff_info:8;	// 19:12
+		uint32_t auto_cnfg_dsbl:8;	// 27:20
+		uint32_t reserved1:3;		// 30:28
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t ndiv_frac:24;	// 27:04
+		uint32_t reserved0:3;	// 30:28
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:9;	// 08:00  
+		uint32_t enableb_ch0:1;	// 09:09
+		uint32_t hold_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:9;	// 24:16
+		uint32_t enableb_ch1:1;	// 25:25
+		uint32_t hold_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:8;	// 07:00
+		uint32_t stat_select:3;	// 10:08
+		uint32_t pq_mode:1;	// 11:11
+		uint32_t stat_mode:2;	// 13:12
+		uint32_t stat_reset:1;	// 14:14  
+		uint32_t stat_update:1;	// 15:15  
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 9:0	  
+		uint32_t ndiv_frac:22;	// 31:10
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECNDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t mdiv5:9;	// 12:04
+		uint32_t mdiv0:9;	// 21:13
+		uint32_t mdiv1:9;	// 30:22
+		uint32_t reserved0:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECPDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv2:9;	// 08:00
+		uint32_t mdiv3:9;	// 17:09
+		uint32_t mdiv4:9;	// 26:18
+		uint32_t reserved0:5;	// 31:27
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECCH25_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	uint32_t reserved0;
+	uint32_t timer_control;
+	uint32_t timer_status;
+	uint32_t reserved1[2];
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+typedef union {
+	struct {
+		uint32_t ubus_soft_reset:1;
+		uint32_t alt_ubus_clk_sel:1;
+		uint32_t observe_clk_sw_init:1;
+		uint32_t alt_emmc_clk_sel:1;
+		uint32_t reserved:5;
+		uint32_t enable:1;
+		uint32_t counter:8;
+		uint32_t reserved2:14;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CLKRST_VREG_CONTROL;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	// BPCM
+	uint32_t control;	// offset 0x10, PMB reg index 4
+	BPCM_SR_CONTROL sr_control;	// offset 0x14, PMB reg index 5
+	uint32_t reserved1[2];	// offset 0x18, PMB reg index 6/7
+	// Client-specific registers
+	uint32_t client_specific[24];	// offset 0x20, PMB reg index 8..31
+	// Zones
+	BPCM_ZONE zones[];	// offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1))
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCM_OFFSET(reg) (offsetof(BPCM_REGS,reg)>>2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08, actual offset = 2
+	uint32_t cfg_control;	// offset = 0x10, actual offset = 4
+	BPCM_SR_CONTROL sr_control;	// offset = 0x14, actual offset = 5
+	uint32_t reserved1[2];	// offset = 0x18, actual offset = 6
+	uint32_t vdsl_arm_sr;	// offset = 0x20, actual offset = 8
+	BPCM_VDSL_ARM_RST_CTL vdsl_arm_rst_control;	// offset = 0x24, actual offset = 9
+	uint32_t reserved2[2];	// offset = 0x28, actual offset = 10
+	uint32_t vdsl_afe_config0;	// offset = 0x30, actual offset = 12
+	uint32_t vdsl_afe_config1;	// offset = 0x34, actual offset = 13
+	uint32_t reserved3[18];	// offset = 0x38, actual offset = 14
+	BPCM_ZONE zones;	// offset = 0x80, actual offset = 32
+} BPCM_VDSL_REGS;		// total offset space = 4096
+
+#define BPCMVDSLOffset(reg)	offsetof(BPCM_VDSL_REGS,reg)
+#define BPCMVDSLRegOffset(reg)	(BPCMVDSLOffset(reg) >> 2)
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08, actual offset = 2
+	uint32_t cfg_control;	// offset = 0x10, actual offset = 4
+	BPCM_SR_CONTROL sr_control;	// offset = 0x14, actual offset = 5
+	uint32_t reserved1[2];	// offset = 0x18, actual offset = 6
+	BPCM_ZONE zones;	// offset = 0x20, actual offset = 8
+	ARM_CONTROL_REG arm_control;	// offset = 0x40, actual offset = 16
+} ARM_BPCM_REGS;
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	/* BIU PLL BCPM definition */  
+	BPCM_ID_REG id_reg;	// offset = 0x00 
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04
+	uint32_t reserved0[2];	// offset = 0x08..0x0c
+	PLL_CTRL_REG resets;	// offset = 0x10
+	uint32_t reserved1[2];	// offset = 0x14
+	PLL_NDIV_REG ndiv;	// offset = 0x1c
+	PLL_PDIV_REG pdiv;	// offset = 0x20
+	PLL_LOOP0_REG loop0;	// offset = 0x24
+	PLL_LOOP1_REG loop1;	// offset = 0x28
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34
+	uint32_t reserved2;	// offset = 0x38
+	PLL_STAT_REG stat;	// offset = 0x3c
+	uint32_t strap;		// offset = 0x40
+	PLL_DECNDIV_REG decndiv;// offset = 0x44
+	PLL_DECPDIV_REG decpdiv;// offset = 0x48
+	PLL_DECCH25_REG decch25;// offset = 0x4c
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	uint32_t reserved1[5];	// offset = 0x14, actual offset = 5
+	PLL_NDIV_REG ndiv;	// offset = 0x28, actual offset = a
+	PLL_PDIV_REG pdiv;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x34, actual offset = d
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x38, actual offset = e
+	PLL_LOOP0_REG loop0;	// offset = 0x3c, actual offset = f
+	PLL_LOOP1_REG loop1;	// offset = 0x40, actual offset = 0x10
+	PLL_STAT_REG stat;	// offset = 0x44, actual offset = 0x11
+	uint32_t strap;		// offset = 0x48, actual offset = 0x12
+	PLL_DECNDIV_REG decndiv;// offset = 0x4c, actual offset = 0x13
+	PLL_DECPDIV_REG decpdiv;// offset = 0x50, actual offset = 0x14
+	PLL_DECCH25_REG decch25;// offset = 0x54, actual offset = 0x15
+} AFEPLL_BPCM_REGS;
+
+#define AFEPLLBPCMOffset(reg)		offsetof(AFEPLL_BPCM_REGS,reg)
+#define AFEPLLBPCMRegOffset(reg)	(AFEPLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04
+	uint32_t reserved0[2];	// offset = 0x08..0x0c
+	PLL_CTRL_REG resets;	// offset = 0x10
+	uint32_t reserved1[5];	// offset = 0x14
+	PLL_NDIV_REG ndiv;	// offset = 0x28
+	PLL_PDIV_REG pdiv;	// offset = 0x2c
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x30
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x34
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x38
+	PLL_STAT_REG stat;	// offset = 0x3c
+	uint32_t strap;		// offset = 0x40
+	PLL_DECNDIV_REG decndiv;// offset = 0x44
+	PLL_DECPDIV_REG decpdiv;// offset = 0x48
+	PLL_DECCH25_REG decch25;// offset = 0x4c
+} RDPPLL_BPCM_REGS;
+
+#define RDPPLLBPCMOffset(reg)		offsetof(RDPPLL_BPCM_REGS,reg)
+#define RDPPLLBPCMRegOffset(reg)	(RDPPLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved1;	// offset = 0x2c, actual offset = 11
+	uint32_t clkrst_cfg;	// offset = 0x30, actual offset = 12
+	BPCM_CLKRST_VREG_CONTROL vreg_control;	// offset 0x50, PMB reg index 19
+	uint32_t xtal_control;	// offset = 0x38, actual offset = 14
+	uint32_t clkrst_stat;	// offset = 0x3c, actual offset = 15
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+typedef struct {
+    // ETH_PMB
+	BPCM_ID_REG id_reg;	    // offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved8[2];	// offset 0x08, PMB reg index 2/3
+	// ETH_CFG
+	uint32_t dpg_zones;	    // offset 0x10, PMB reg index 4
+	uint32_t soft_rst;;	    // offset 0x14, PMB reg index 5
+	uint32_t reserved18[2];	// offset 0x18, PMB reg index 6/7
+    // ETH_CORE
+	uint32_t qphy_cntrl;	// offset 0x20
+	uint32_t qphy_status;	// offset 0x24
+	uint32_t sphy_cntrl;	// offset 0x28
+	uint32_t sphy_status;	// offset 0x2c
+	uint32_t serdes0_cntrl;	// offset 0x30
+	uint32_t serdes0_status;// offset 0x34
+	uint32_t serdes0_an_st; // offset 0x38
+	uint32_t serdes1_cntrl;	// offset 0x3c
+	uint32_t serdes1_status;// offset 0x40
+	uint32_t serdes1_an_st; // offset 0x44
+	uint32_t reserved48[3];
+	uint32_t rgmii_cntrl;   // offset 0x54
+	uint32_t reserved58[2];
+	uint32_t serdes0_st1;   // offset 0x60
+	uint32_t serdes1_st1;   // offset 0x64
+	uint32_t reserved68;
+	uint32_t serdes0_pwr_cntrl;// offset 0x6c
+	uint32_t serdes1_pwr_cntrl;// offset 0x70
+} BPCM_ETH_REGS;
+
+#define BPCMETHOffset(reg)		offsetof(BPCM_ETH_REGS,reg)
+#define BPCMETHRegOffset(reg)	(BPCMETHOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+#endif
+
+
diff --git a/arch/arm/include/asm/arch-bcm63146/boot0.h b/arch/arm/include/asm/arch-bcm63146/boot0.h
new file mode 100644
index 0000000000..776f923b54
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/boot0.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63146_BOOT0_H
+#define _63146_BOOT0_H
+
+#include <asm-offsets.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+_bcm_boot:
+	tlbi	alle3			/* Invalidate TLB */
+	dsb	sy
+	isb
+
+	ic	ialluis			/* Invalidate icache */
+	isb
+
+	/* Initialize system control register enable i-cache */
+	mrs	x0, sctlr_el3
+	movn	x1, #(CR_M | CR_C)
+	and	x0, x1, x0
+	orr	x0, x0, #CR_I
+	msr	sctlr_el3, x0
+	isb
+
+	/* relocate the code, init'ed data from flash to lmem  */	
+relo_image:
+	adr     x1, _bcm_boot		/* x1 source address in flash */
+	ldr	x0, =__image_copy_start	/* x0 dest address in sram */
+	subs	x4, x1, x0		/* x4 relocation offset */
+	beq	relo_dtb		/* skip relocation */
+	ldr	x2, =__image_copy_end	/* x2 dest ending address in flash */
+
+relo_loop:
+	ldp	x5, x6, [x1], #16
+	stp	x5, x6, [x0], #16
+	cmp	x0, x2
+	blo	relo_loop
+
+	/* if we attached dtb after bss, need to relocate dtb as well */	
+relo_dtb:
+#if defined(CONFIG_SPL_OF_CONTROL) && defined(CONFIG_OF_SEPARATE)
+
+#ifdef CONFIG_OF_SPL_SEPARATE_BSS
+	ldr	x3, =__image_binary_end
+#else
+	ldr	x3, =_end
+#endif
+	add	x1, x3, x4       /* r1 source address in flash */
+	mov	x0, xzr
+	mov	x2, xzr
+	/* check ftd size ... */
+	/* struct fdt_header {
+	fdt32_t magic;
+	fdt32_t totalsize; */
+	ldr	w0, [x1, #4]	/* r0 total size */
+	rev	w0, w0          /* byte order from fdt to little endian */
+	lsr	w0, w0, #2      /* in the order of 4 bytes aligned */
+	add	w0, w0, #1
+	lsl	w0, w0, #2 
+	add	x2, x1, x0       /* r2 dest ending address in flash */
+	mov	x0, x3           /* r0 dest address in sram */
+
+dtb_loop:
+	ldp	x5, x6, [x1], #16
+	stp	x5, x6, [x0], #16
+	cmp	x1, x2
+	blo	dtb_loop
+#endif
+	ldr	x0, =reset
+	br	x0
+
+#else
+	b	reset
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63146/brom.h b/arch/arm/include/asm/arch-bcm63146/brom.h
new file mode 100644
index 0000000000..b89f52dc65
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63146_BROM_H
+#define _63146_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63146/cpu.h b/arch/arm/include/asm/arch-bcm63146/cpu.h
new file mode 100644
index 0000000000..efb9d88553
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/cpu.h
@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63146_CPU_H
+#define _63146_CPU_H
+
+#include <common.h>
+
+
+typedef struct CCI500_SlaveIntf {
+	#define SNOOP_CTRL_ENABLE_SNOOP            0x1
+	uint32_t snoop_ctrl;	/* 0x0 */
+	#define SHARE_OVR_SHAREABLE_OVR_SHIFT      0x0
+	#define SHARE_OVR_SHAREABLE_OVR_MASK       0x3
+	#define SHARE_OVR_SHAREABLE_OVR_NONSHR     0x2
+	#define SHARE_OVR_SHAREABLE_OVR_SHR        0x3
+	uint32_t share_ovr;	/* 0x4 */
+	uint32_t rsvd1[62];	/* 0x8 - 0xff */
+	uint32_t arqos_ovr;	/* 0x100 */
+	uint32_t awqos_ovr;	/* 0x104 */
+	uint32_t rsvd2[2];	/* 0x108 - 0x10f */
+	uint32_t qos_max_ot;	/* 0x110 */
+	uint32_t rsvd3[955];	/* 0x114 - 0xfff */
+}CCI500_SlaveIntf;
+
+typedef struct CCI500_EventCounter {
+	uint32_t sel;	/* 0x0 */
+	uint32_t data;	/* 0x4 */
+	uint32_t ctrl;	/* 0x8 */
+	uint32_t clr_ovfl;	/* 0xC */
+	uint32_t rsvd[16380];	/* 0x10 - 0xffff */
+}CCI500_EventCounter;
+
+typedef struct CCI500 {
+	#define CONTROL_OVERRIDE_SNOOP_DISABLE     0x1
+	#define CONTROL_OVERRIDE_SNOOP_FLT_DISABLE 0x4
+	uint32_t ctrl_ovr;	/* 0x0 */
+	uint32_t rsvd1;	/* 0x4 */
+	#define SECURE_ACCESS_UNSECURE_ENABLE      0x1
+	uint32_t secr_acc;	/* 0x8 */
+	uint32_t status;	/* 0xc */
+	#define STATUS_CHANGE_PENDING              0x1
+	uint32_t impr_err;	/* 0x10 */
+	uint32_t qos_threshold;	/* 0x14 */
+	uint32_t rsvd2[58];	/* 0x18 - 0xff */
+	uint32_t pmu_ctrl;	/* 0x100 */
+	#define DBG_CTRL_EN_INTF_MON               0x1
+	uint32_t debug_ctrl;	/* 0x104 */
+	uint32_t rsvd3[958];	/* 0x108 - 0xfff */
+	#define SLAVEINTF_COHERENCY_PORT           0x0
+	#define SLAVEINTF_CPU_CLUSTER              0x1
+	CCI500_SlaveIntf si[7];	/* 0x1000 - 0x7fff */
+	uint32_t rsvd4[8192];	/* 0x8000 - 0xffff */
+	CCI500_EventCounter evt_cntr[8];	/* 0x10000 - 0x8ffff */
+}CCI500;
+
+#define CCI500_BASE	0x81100000
+#define CCI500 ((volatile CCI500 * const) CCI500_BASE)
+
+typedef struct UBUS4_RANGE_CHK_CFG {
+	uint32_t control;	/* 0x0 */
+	uint32_t srcpid[8];	/* 0x4 - 0x23 */
+	uint32_t seclev;	/* 0x24 */
+	uint32_t base;		/* 0x28 */
+	uint32_t base_up;  	/* 0x2c */
+}UBUS4_RANGE_CHK_CFG;
+
+typedef struct UBUS4_RANGE_CHK_SETUP {
+	uint32_t lock;			/* 0x0 */
+	uint32_t log_inf[3];  		/* 0x4 - 0xf */
+	UBUS4_RANGE_CHK_CFG cfg[16];	/* 0x10 - 0x30f */
+}UBUS4_RANGE_CHK_SETUP;
+
+#define UBUS4_COHERENCY_PORT_BASE	0x810A0000
+#define UBUS4_RANGE_CHK_SETUP_OFFSET    0x0
+#define UBUS4_RANGE_CHK_SETUP_BASE	(UBUS4_COHERENCY_PORT_BASE+UBUS4_RANGE_CHK_SETUP_OFFSET)
+#define UBUS4_RANGE_CHK_SETUP 		((volatile UBUS4_RANGE_CHK_SETUP * const) UBUS4_RANGE_CHK_SETUP_BASE)
+
+typedef struct BIUCFG_Access {
+	uint32_t permission;	/* 0x0 */
+	uint32_t sbox;	/* 0x4 */
+	uint32_t cpu_defeature;	/* 0x8 */
+	uint32_t dbg_security;	/* 0xc */
+	uint32_t rsvd1[32];	/* 0x10 - 0x8f */
+	uint64_t violation[2];	/* 0x90 - 0x9f */
+	uint32_t ts_access[2];	/* 0xa0 - 0xa7 */
+	uint32_t rsvd2[22];	/* 0xa8 - 0xff */
+}BIUCFG_Access;
+
+typedef struct BIUCFG_Cluster {
+	uint32_t permission;	/* 0x0 */
+	uint32_t config;	/* 0x4 */
+	uint32_t status;	/* 0x8 */
+	uint32_t control;	/* 0xc */
+	uint32_t cpucfg;	/* 0x10 */
+	uint32_t dbgrom;	/* 0x14 */
+	uint32_t rsvd1[2];	/* 0x18 - 0x1f */
+	uint64_t rvbar_addr[4];	/* 0x20 - 0x3f */
+	uint32_t rsvd2[48];	/* 0x40 - 0xff */
+}BIUCFG_Cluster;
+
+typedef struct BIUCFG_Bac {
+	uint32_t bac_permission;	/* 0x00 */
+	uint32_t bac_periphbase;	/* 0x04 */
+	uint32_t rsvd[2];	/* 0x08 - 0x0f */
+	uint32_t bac_event;	/* 0x10 */
+	uint32_t rsvd_1[3];	/* 0x14 - 0x1f */
+	uint32_t bac_ccicfg;	/* 0x20 */
+	uint32_t bac_cciaddr;	/* 0x24 */
+	uint32_t rsvd_2[4];	/* 0x28 - 0x37 */
+	uint32_t bac_ccievs2;	/* 0x38 */
+	uint32_t bac_ccievs3;	/* 0x3c */
+	uint32_t bac_ccievs4;	/* 0x40 */
+	uint32_t rsvd_3[3];	/* 0x44 - 0x4f */
+	uint32_t bac_ccievm0;	/* 0x50 */
+	uint32_t bac_ccievm1;	/* 0x54 */
+	uint32_t rsvd_4[2];	/* 0x58 - 0x5f */
+	uint32_t bac_dapapbcfg;	/* 0x60 */
+	uint32_t bac_status;	/* 0x64 */
+	uint32_t rsvd_5[2];	/* 0x68 - 0x6f */
+	uint32_t cpu_therm_irq_cfg;	/* 0x70 */
+	uint32_t cpu_therm_threshold_cfg;	/* 0x74 */
+	uint32_t rsvd_6;	/* 0x78 */
+	uint32_t cpu_therm_temp;	/* 0x7c */
+	uint32_t rsvd_7[32];	/* 0x80 - 0xff */
+} BIUCFG_Bac;
+
+typedef struct BIUCFG_Aux {
+	uint32_t aux_permission;	/* 0x00 */
+	uint32_t rsvd[3];	/* 0x04 - 0x0f */
+	uint32_t c0_clk_control;	/* 0x10 */
+	uint32_t c0_clk_ramp;	/* 0x14 */
+	uint32_t c0_clk_pattern;	/* 0x18 */
+	uint32_t rsvd_1;	/* 0x1c */
+	uint32_t c1_clk_control;	/* 0x20 */
+	uint32_t c1_clk_ramp;	/* 0x24 */
+	uint32_t c1_clk_pattern;	/* 0x28 */
+	uint32_t rsvd_2[53];	/* 0x2c - 0xff */
+} BIUCFG_Aux;
+
+typedef struct BIUCFG_TS0_CTRL {
+	uint32_t CNTCR;		/* 0x00 */
+	uint32_t CNTSR;		/* 0x04 */
+	uint32_t CNTCVL;	/* 0x08 */
+	uint32_t CNTCVU;	/* 0x0c */
+	uint32_t rsvd_0[4];	/* 0x10 - 0x1f */
+	uint32_t CNTFID0;	/* 0x20 */
+	uint32_t rsvd_1[1015];	/* 0x24 - 0xfff */
+} BIUCFG_TS0_CTRL;
+
+typedef struct BIUCFG {
+	BIUCFG_Access access;	/* 0x0 - 0xff*/
+	BIUCFG_Cluster cluster[2];	/* 0x100 - 0x2ff*/
+	BIUCFG_Bac bac;	/* 0x300 - 0x3ff */
+	uint32_t anonymous[192];	/* 0x400 - 0x6ff */
+	BIUCFG_Aux aux;	/* 0x700 - 0x7ff */
+	uint32_t anonymous_1[512];	/* 0x800 - 0xfff */
+	BIUCFG_TS0_CTRL ts0_ctrl;	/* 0x1000 - 0x1fff */
+}BIUCFG;
+
+#define BIUCFG_BASE 0x81060000
+#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63146/ddr.h b/arch/arm/include/asm/arch-bcm63146/ddr.h
new file mode 100644
index 0000000000..746b51af1b
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/ddr.h
@@ -0,0 +1,3242 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63146_DDR_H
+#define _63146_DDR_H
+
+#define MEMC_BASE        0x80040000      /* DDR IO Buf Control */
+#define PHY_BASE         0x80060000      /* DDR PHY base */
+
+#define mc2_glb_acc                              0x00000000 
+#define mc2_glb_vers                             0x00000004 
+#define mc2_glb_gcfg                             0x00000008 
+#define mc2_glb_auto_self_refresh                0x0000000c 
+#define mc2_glb_pwr_mgr                          0x00000010 
+
+
+
+#define mc2_axi_acc                              0x00000040 
+#define mc2_axi_ver                              0x00000044 
+#define mc2_axi_CFG                              0x00000048 
+#define mc2_axi_REP_ARB_MODE                     0x0000004c 
+#define mc2_axi_queue_cfg                        0x00000050 
+#define mc2_axi_queue_size0                      0x00000054 
+#define mc2_axi_queue_map0                       0x00000058 
+#define mc2_axi_SCRATCH                          0x00000060 
+#define mc2_axi_AXI_DEBUG_0_0                    0x00000064 
+#define mc2_axi_AXI_DEBUG_1_0                    0x00000068 
+#define mc2_axi_AXI_DEBUG_MISC                   0x0000006c 
+
+
+
+#define mc2_ubus_acc                             0x00000080 
+#define mc2_ubus_CFG                             0x00000084 
+#define mc2_ubus_ESRCID_CFG                      0x00000088 
+#define mc2_ubus_queue_cfg_queue_cfg             0x0000008c 
+#define mc2_ubus_queue_cfg_queue_map0            0x00000090 
+#define mc2_ubus_queue_cfg_queue_map1            0x00000094 
+#define mc2_ubus_queue_cfg_queue_map2            0x00000098 
+#define mc2_ubus_queue_cfg_queue_map3            0x0000009c 
+#define mc2_ubus_queue_cfg_queue_size0           0x000000a0 
+#define mc2_ubus_queue_cfg_queue_size1           0x000000a4 
+#define mc2_ubus_queue_cfg_queue_size2           0x000000a8 
+#define mc2_ubus_queue_cfg_queue_size3           0x000000ac 
+#define mc2_ubus_diag_ctrl                       0x000000b0 
+#define mc2_ubus_scratch                         0x000000b8 
+#define mc2_ubus_debug_ro                        0x000000bc 
+
+
+
+#define mc2_misc_acc                             0x00000200 
+#define mc2_misc_ver                             0x00000204 
+#define mc2_misc_cfg                             0x00000208 
+#define mc2_misc_vq_cfg                          0x0000020c 
+#define mc2_misc_edis_addr_rand                  0x00000210 
+#define mc2_misc_misc_dbg                        0x00000214 
+
+
+
+#define mc2_afx_acc                              0x00000300 
+#define mc2_afx_ver                              0x00000304 
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi 0x00000310 
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo 0x00000314 
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi  0x00000318 
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo  0x0000031c 
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi     0x00000320 
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo     0x00000324 
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi       0x00000328 
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo       0x0000032c 
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi     0x00000330 
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo     0x00000334 
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi       0x00000338 
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo       0x0000033c 
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi     0x00000340 
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo     0x00000344 
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi       0x00000348 
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo       0x0000034c 
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi     0x00000350 
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo     0x00000354 
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi       0x00000358 
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo       0x0000035c 
+#define mc2_afx_srcid_fltr_cfg0_srcid            0x00000360 
+#define mc2_afx_srcid_fltr_cfg1_srcid            0x00000364 
+#define mc2_afx_srcid_fltr_cfg2_srcid            0x00000368 
+#define mc2_afx_srcid_fltr_cfg3_srcid            0x0000036c 
+#define mc2_afx_row_xtr_cfg_row_19_16            0x00000380 
+#define mc2_afx_row_xtr_cfg_row_15_12            0x00000384 
+#define mc2_afx_row_xtr_cfg_row_11_8             0x00000388 
+#define mc2_afx_row_xtr_cfg_row_7_4              0x0000038c 
+#define mc2_afx_row_xtr_cfg_row_3_0              0x00000390 
+#define mc2_afx_bg_xtr_cfg_bg_3_0                0x000003a0 
+#define mc2_afx_bk_xtr_cfg_bk_3_0                0x000003a4 
+#define mc2_afx_col_xtr_cfg_col_cfg              0x000003a8 
+#define mc2_afx_cs_xtr_cfg_cs_3_0                0x000003b4 
+#define mc2_afx_chn_xtr_cfg_chn_bit              0x000003b8 
+#define mc2_afx_ddr_sz_chk                       0x000003bc 
+
+
+
+#define mc2_rchk_acc                             0x00000400 
+#define mc2_rchk_ver                             0x00000404 
+#define mc2_rchk_range_lock                      0x00000410 
+#define mc2_rchk_range_0_control                 0x00000420 
+#define mc2_rchk_range_0_persrcid_port           0x00000424 
+#define mc2_rchk_range_0_persrcid_port_upper     0x00000428 
+#define mc2_rchk_range_0_base                    0x0000042c 
+#define mc2_rchk_range_0_base_upper              0x00000430 
+#define mc2_rchk_range_0_seclev_en               0x00000434 
+#define mc2_rchk_range_1_control                 0x00000440 
+#define mc2_rchk_range_1_persrcid_port           0x00000444 
+#define mc2_rchk_range_1_persrcid_port_upper     0x00000448 
+#define mc2_rchk_range_1_base                    0x0000044c 
+#define mc2_rchk_range_1_base_upper              0x00000450 
+#define mc2_rchk_range_1_seclev_en               0x00000454 
+#define mc2_rchk_range_2_control                 0x00000460 
+#define mc2_rchk_range_2_persrcid_port           0x00000464 
+#define mc2_rchk_range_2_persrcid_port_upper     0x00000468 
+#define mc2_rchk_range_2_base                    0x0000046c 
+#define mc2_rchk_range_2_base_upper              0x00000470 
+#define mc2_rchk_range_2_seclev_en               0x00000474 
+#define mc2_rchk_range_3_control                 0x00000480 
+#define mc2_rchk_range_3_persrcid_port           0x00000484 
+#define mc2_rchk_range_3_persrcid_port_upper     0x00000488 
+#define mc2_rchk_range_3_base                    0x0000048c 
+#define mc2_rchk_range_3_base_upper              0x00000490 
+#define mc2_rchk_range_3_seclev_en               0x00000494 
+#define mc2_rchk_range_4_control                 0x000004a0 
+#define mc2_rchk_range_4_persrcid_port           0x000004a4 
+#define mc2_rchk_range_4_persrcid_port_upper     0x000004a8 
+#define mc2_rchk_range_4_base                    0x000004ac 
+#define mc2_rchk_range_4_base_upper              0x000004b0 
+#define mc2_rchk_range_4_seclev_en               0x000004b4 
+#define mc2_rchk_range_5_control                 0x000004c0 
+#define mc2_rchk_range_5_persrcid_port           0x000004c4 
+#define mc2_rchk_range_5_persrcid_port_upper     0x000004c8 
+#define mc2_rchk_range_5_base                    0x000004cc 
+#define mc2_rchk_range_5_base_upper              0x000004d0 
+#define mc2_rchk_range_5_seclev_en               0x000004d4 
+#define mc2_rchk_range_6_control                 0x000004e0 
+#define mc2_rchk_range_6_persrcid_port           0x000004e4 
+#define mc2_rchk_range_6_persrcid_port_upper     0x000004e8 
+#define mc2_rchk_range_6_base                    0x000004ec 
+#define mc2_rchk_range_6_base_upper              0x000004f0 
+#define mc2_rchk_range_6_seclev_en               0x000004f4 
+#define mc2_rchk_range_7_control                 0x00000500 
+#define mc2_rchk_range_7_persrcid_port           0x00000504 
+#define mc2_rchk_range_7_persrcid_port_upper     0x00000508 
+#define mc2_rchk_range_7_base                    0x0000050c 
+#define mc2_rchk_range_7_base_upper              0x00000510 
+#define mc2_rchk_range_7_seclev_en               0x00000514 
+#define mc2_rchk_log_info_0                      0x00000520 
+#define mc2_rchk_log_info_1                      0x00000524 
+#define mc2_rchk_log_info_2                      0x00000528 
+#define mc2_rlt_acc                              0x00000600 
+#define mc2_rlt_vers                             0x00000604 
+#define mc2_rlt_rate_limiter0_cfg_0              0x00000610 
+#define mc2_rlt_rate_limiter0_cfg_1              0x00000614 
+#define mc2_rlt_rate_limiter1_cfg_0              0x00000618 
+#define mc2_rlt_rate_limiter1_cfg_1              0x0000061c 
+#define mc2_rlt_rate_limiter2_cfg_0              0x00000620 
+#define mc2_rlt_rate_limiter2_cfg_1              0x00000624 
+#define mc2_rlt_rate_limiter3_cfg_0              0x00000628 
+#define mc2_rlt_rate_limiter3_cfg_1              0x0000062c 
+#define mc2_rlt_rate_limiter4_cfg_0              0x00000630 
+#define mc2_rlt_rate_limiter4_cfg_1              0x00000634 
+#define mc2_rlt_rate_limiter5_cfg_0              0x00000638 
+#define mc2_rlt_rate_limiter5_cfg_1              0x0000063c 
+#define mc2_rlt_monitor0_mon_0                   0x00000690 
+#define mc2_rlt_monitor0_mon_1                   0x00000694 
+#define mc2_rlt_monitor1_mon_0                   0x00000698 
+#define mc2_rlt_monitor1_mon_1                   0x0000069c 
+#define mc2_rlt_monitor2_mon_0                   0x000006a0 
+#define mc2_rlt_monitor2_mon_1                   0x000006a4 
+#define mc2_rlt_monitor3_mon_0                   0x000006a8 
+#define mc2_rlt_monitor3_mon_1                   0x000006ac 
+#define mc2_rlt_monitor4_mon_0                   0x000006b0 
+#define mc2_rlt_monitor4_mon_1                   0x000006b4 
+#define mc2_rlt_monitor5_mon_0                   0x000006b8 
+#define mc2_rlt_monitor5_mon_1                   0x000006bc 
+
+#define mc2_chn_ddr_acc                          0x00000900 
+#define mc2_chn_ddr_ver                          0x00000904 
+#define mc2_chn_ddr_chn_arb_cfg                  0x00000908 
+#define mc2_chn_ddr_chn_arb_param                0x0000090c 
+#define mc2_chn_ddr_chn_sch_cfg                  0x00000910 
+#define mc2_chn_ddr_phy_st                       0x00000914 
+#define mc2_chn_ddr_dram_cfg                     0x00000918 
+#define mc2_chn_ddr_dcmd                         0x0000091c 
+#define mc2_chn_ddr_dmode_0                      0x00000920 
+#define mc2_chn_ddr_dmode_2                      0x00000924 
+#define mc2_chn_ddr_odt                          0x00000928 
+#define mc2_chn_ddr_ddr_param_cmd0               0x0000092c 
+#define mc2_chn_ddr_ddr_param_cmd1               0x00000930 
+#define mc2_chn_ddr_ddr_param_cmd2               0x00000934 
+#define mc2_chn_ddr_ddr_param_cmd3               0x00000938 
+#define mc2_chn_ddr_ddr_param_dat0               0x0000093c 
+#define mc2_chn_ddr_ddr_param_dat1               0x00000940 
+#define mc2_chn_ddr_ddr_param_pre0               0x00000944 
+#define mc2_chn_ddr_ddr_param_pwr0               0x00000948 
+#define mc2_chn_ddr_ddr_param_zqc0               0x0000094c 
+#define mc2_chn_ddr_refresh_aref0                0x00000954 
+#define mc2_chn_ddr_refresh_aref1                0x00000958 
+#define mc2_chn_ddr_auto_self_refresh            0x0000095c 
+#define mc2_chn_ddr_auto_zqcs                    0x00000968 
+#define mc2_chn_ddr_dfi_error                    0x0000096c 
+
+
+#define mc2_chn_sram_acc                         0x00000a20 
+#define mc2_chn_sram_ver                         0x00000a24 
+#define mc2_chn_sram_ind_ctrl                    0x00000a28 
+#define mc2_chn_sram_init                        0x00000a2c 
+#define mc2_chn_sram_ind_data0                   0x00000a30 
+#define mc2_chn_sram_ind_data1                   0x00000a34 
+#define mc2_chn_sram_ind_data2                   0x00000a38 
+#define mc2_chn_sram_ind_data3                   0x00000a3c 
+
+
+#define mc2_wbf_acc                              0x00000e80 
+#define mc2_wbf_ver                              0x00000e84 
+#define mc2_wbf_pri_cfg                          0x00000e88 
+#define mc2_wbf_sta                              0x00000e8c 
+#define mc2_wbf_bkdr_bkdr_cmd                    0x00000e90 
+#define mc2_wbf_bkdr_bkdr_data0                  0x00000e94 
+#define mc2_wbf_bkdr_bkdr_data1                  0x00000e98 
+#define mc2_wbf_bkdr_bkdr_data2                  0x00000e9c 
+#define mc2_wbf_bkdr_bkdr_data3                  0x00000ea0 
+#define mc2_wbf_bkdr_bkdr_data4                  0x00000ea4 
+#define mc2_wbf_bkdr_bkdr_data5                  0x00000ea8 
+#define mc2_wbf_bkdr_bkdr_data6                  0x00000eac 
+#define mc2_wbf_bkdr_bkdr_data7                  0x00000eb0 
+#define mc2_wbf_id_bkdr_id_cmd                   0x00000ec0 
+#define mc2_wbf_id_bkdr_id_data                  0x00000ec4 
+
+
+
+#define mc2_rmx_acc                              0x00000ed0 
+#define mc2_rmx_ver                              0x00000ed4 
+#define mc2_rmx_pri_cfg                          0x00000ed8 
+
+
+#define mc2_glb_acc_acc_eack_MASK                                  0x80000000
+#define mc2_glb_acc_acc_eack_ALIGN                                 0
+#define mc2_glb_acc_acc_eack_BITS                                  1
+#define mc2_glb_acc_acc_eack_SHIFT                                 31
+#define mc2_glb_acc_acc_eack_DEFAULT                               0x00000000
+
+
+#define mc2_glb_acc_reserved0_MASK                                 0x7fffff00
+#define mc2_glb_acc_reserved0_ALIGN                                0
+#define mc2_glb_acc_reserved0_BITS                                 23
+#define mc2_glb_acc_reserved0_SHIFT                                8
+
+
+#define mc2_glb_acc_acc_sw_MASK                                    0x00000080
+#define mc2_glb_acc_acc_sw_ALIGN                                   0
+#define mc2_glb_acc_acc_sw_BITS                                    1
+#define mc2_glb_acc_acc_sw_SHIFT                                   7
+#define mc2_glb_acc_acc_sw_DEFAULT                                 0x00000001
+
+
+#define mc2_glb_acc_acc_sr_MASK                                    0x00000040
+#define mc2_glb_acc_acc_sr_ALIGN                                   0
+#define mc2_glb_acc_acc_sr_BITS                                    1
+#define mc2_glb_acc_acc_sr_SHIFT                                   6
+#define mc2_glb_acc_acc_sr_DEFAULT                                 0x00000001
+
+
+#define mc2_glb_acc_acc_nsw_MASK                                   0x00000020
+#define mc2_glb_acc_acc_nsw_ALIGN                                  0
+#define mc2_glb_acc_acc_nsw_BITS                                   1
+#define mc2_glb_acc_acc_nsw_SHIFT                                  5
+#define mc2_glb_acc_acc_nsw_DEFAULT                                0x00000001
+
+
+#define mc2_glb_acc_acc_nsr_MASK                                   0x00000010
+#define mc2_glb_acc_acc_nsr_ALIGN                                  0
+#define mc2_glb_acc_acc_nsr_BITS                                   1
+#define mc2_glb_acc_acc_nsr_SHIFT                                  4
+#define mc2_glb_acc_acc_nsr_DEFAULT                                0x00000001
+
+
+#define mc2_glb_acc_perm_sw_MASK                                   0x00000008
+#define mc2_glb_acc_perm_sw_ALIGN                                  0
+#define mc2_glb_acc_perm_sw_BITS                                   1
+#define mc2_glb_acc_perm_sw_SHIFT                                  3
+#define mc2_glb_acc_perm_sw_DEFAULT                                0x00000001
+
+
+#define mc2_glb_acc_perm_sr_MASK                                   0x00000004
+#define mc2_glb_acc_perm_sr_ALIGN                                  0
+#define mc2_glb_acc_perm_sr_BITS                                   1
+#define mc2_glb_acc_perm_sr_SHIFT                                  2
+#define mc2_glb_acc_perm_sr_DEFAULT                                0x00000001
+
+
+#define mc2_glb_acc_perm_nsw_MASK                                  0x00000002
+#define mc2_glb_acc_perm_nsw_ALIGN                                 0
+#define mc2_glb_acc_perm_nsw_BITS                                  1
+#define mc2_glb_acc_perm_nsw_SHIFT                                 1
+#define mc2_glb_acc_perm_nsw_DEFAULT                               0x00000001
+
+
+#define mc2_glb_acc_perm_nsr_MASK                                  0x00000001
+#define mc2_glb_acc_perm_nsr_ALIGN                                 0
+#define mc2_glb_acc_perm_nsr_BITS                                  1
+#define mc2_glb_acc_perm_nsr_SHIFT                                 0
+#define mc2_glb_acc_perm_nsr_DEFAULT                               0x00000001
+
+
+
+
+#define mc2_glb_vers_reserved0_MASK                                0xffff0000
+#define mc2_glb_vers_reserved0_ALIGN                               0
+#define mc2_glb_vers_reserved0_BITS                                16
+#define mc2_glb_vers_reserved0_SHIFT                               16
+
+
+#define mc2_glb_vers_VERSION_MAJOR_MASK                            0x0000ff00
+#define mc2_glb_vers_VERSION_MAJOR_ALIGN                           0
+#define mc2_glb_vers_VERSION_MAJOR_BITS                            8
+#define mc2_glb_vers_VERSION_MAJOR_SHIFT                           8
+#define mc2_glb_vers_VERSION_MAJOR_DEFAULT                         0x00000005
+
+
+#define mc2_glb_vers_VERSION_MINOR_MASK                            0x000000ff
+#define mc2_glb_vers_VERSION_MINOR_ALIGN                           0
+#define mc2_glb_vers_VERSION_MINOR_BITS                            8
+#define mc2_glb_vers_VERSION_MINOR_SHIFT                           0
+#define mc2_glb_vers_VERSION_MINOR_DEFAULT                         0x00000001
+
+
+
+
+#define mc2_glb_gcfg_dram_en_MASK                                  0x80000000
+#define mc2_glb_gcfg_dram_en_ALIGN                                 0
+#define mc2_glb_gcfg_dram_en_BITS                                  1
+#define mc2_glb_gcfg_dram_en_SHIFT                                 31
+#define mc2_glb_gcfg_dram_en_DEFAULT                               0x00000000
+
+
+#define mc2_glb_gcfg_reserved0_MASK                                0x78000000
+#define mc2_glb_gcfg_reserved0_ALIGN                               0
+#define mc2_glb_gcfg_reserved0_BITS                                4
+#define mc2_glb_gcfg_reserved0_SHIFT                               27
+
+
+#define mc2_glb_gcfg_sref_slow_clk_en_MASK                         0x04000000
+#define mc2_glb_gcfg_sref_slow_clk_en_ALIGN                        0
+#define mc2_glb_gcfg_sref_slow_clk_en_BITS                         1
+#define mc2_glb_gcfg_sref_slow_clk_en_SHIFT                        26
+#define mc2_glb_gcfg_sref_slow_clk_en_DEFAULT                      0x00000000
+
+
+#define mc2_glb_gcfg_phy_dfi_mode_MASK                             0x03000000
+#define mc2_glb_gcfg_phy_dfi_mode_ALIGN                            0
+#define mc2_glb_gcfg_phy_dfi_mode_BITS                             2
+#define mc2_glb_gcfg_phy_dfi_mode_SHIFT                            24
+#define mc2_glb_gcfg_phy_dfi_mode_DEFAULT                          0x00000001
+
+
+#define mc2_glb_gcfg_reserved1_MASK                                0x00f00000
+#define mc2_glb_gcfg_reserved1_ALIGN                               0
+#define mc2_glb_gcfg_reserved1_BITS                                4
+#define mc2_glb_gcfg_reserved1_SHIFT                               20
+
+
+#define mc2_glb_gcfg_dpfe_block_dmem_read_MASK                     0x00080000
+#define mc2_glb_gcfg_dpfe_block_dmem_read_ALIGN                    0
+#define mc2_glb_gcfg_dpfe_block_dmem_read_BITS                     1
+#define mc2_glb_gcfg_dpfe_block_dmem_read_SHIFT                    19
+#define mc2_glb_gcfg_dpfe_block_dmem_read_DEFAULT                  0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_block_dmem_write_MASK                    0x00040000
+#define mc2_glb_gcfg_dpfe_block_dmem_write_ALIGN                   0
+#define mc2_glb_gcfg_dpfe_block_dmem_write_BITS                    1
+#define mc2_glb_gcfg_dpfe_block_dmem_write_SHIFT                   18
+#define mc2_glb_gcfg_dpfe_block_dmem_write_DEFAULT                 0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_block_imem_read_MASK                     0x00020000
+#define mc2_glb_gcfg_dpfe_block_imem_read_ALIGN                    0
+#define mc2_glb_gcfg_dpfe_block_imem_read_BITS                     1
+#define mc2_glb_gcfg_dpfe_block_imem_read_SHIFT                    17
+#define mc2_glb_gcfg_dpfe_block_imem_read_DEFAULT                  0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_block_imem_write_MASK                    0x00010000
+#define mc2_glb_gcfg_dpfe_block_imem_write_ALIGN                   0
+#define mc2_glb_gcfg_dpfe_block_imem_write_BITS                    1
+#define mc2_glb_gcfg_dpfe_block_imem_write_SHIFT                   16
+#define mc2_glb_gcfg_dpfe_block_imem_write_DEFAULT                 0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_disable_cpu_MASK                         0x00008000
+#define mc2_glb_gcfg_dpfe_disable_cpu_ALIGN                        0
+#define mc2_glb_gcfg_dpfe_disable_cpu_BITS                         1
+#define mc2_glb_gcfg_dpfe_disable_cpu_SHIFT                        15
+#define mc2_glb_gcfg_dpfe_disable_cpu_DEFAULT                      0x00000000
+
+
+#define mc2_glb_gcfg_reserved2_MASK                                0x00004000
+#define mc2_glb_gcfg_reserved2_ALIGN                               0
+#define mc2_glb_gcfg_reserved2_BITS                                1
+#define mc2_glb_gcfg_reserved2_SHIFT                               14
+
+
+#define mc2_glb_gcfg_wr_data_mode_MASK                             0x00002000
+#define mc2_glb_gcfg_wr_data_mode_ALIGN                            0
+#define mc2_glb_gcfg_wr_data_mode_BITS                             1
+#define mc2_glb_gcfg_wr_data_mode_SHIFT                            13
+#define mc2_glb_gcfg_wr_data_mode_DEFAULT                          0x00000000
+
+
+#define mc2_glb_gcfg_exe_notify_mode_MASK                          0x00001000
+#define mc2_glb_gcfg_exe_notify_mode_ALIGN                         0
+#define mc2_glb_gcfg_exe_notify_mode_BITS                          1
+#define mc2_glb_gcfg_exe_notify_mode_SHIFT                         12
+#define mc2_glb_gcfg_exe_notify_mode_DEFAULT                       0x00000000
+
+
+#define mc2_glb_gcfg_shmoo_done_MASK                               0x00000800
+#define mc2_glb_gcfg_shmoo_done_ALIGN                              0
+#define mc2_glb_gcfg_shmoo_done_BITS                               1
+#define mc2_glb_gcfg_shmoo_done_SHIFT                              11
+#define mc2_glb_gcfg_shmoo_done_DEFAULT                            0x00000000
+
+
+#define mc2_glb_gcfg_dfi_en_MASK                                   0x00000400
+#define mc2_glb_gcfg_dfi_en_ALIGN                                  0
+#define mc2_glb_gcfg_dfi_en_BITS                                   1
+#define mc2_glb_gcfg_dfi_en_SHIFT                                  10
+#define mc2_glb_gcfg_dfi_en_DEFAULT                                0x00000000
+
+
+#define mc2_glb_gcfg_mclksrc_MASK                                  0x00000200
+#define mc2_glb_gcfg_mclksrc_ALIGN                                 0
+#define mc2_glb_gcfg_mclksrc_BITS                                  1
+#define mc2_glb_gcfg_mclksrc_SHIFT                                 9
+#define mc2_glb_gcfg_mclksrc_DEFAULT                               0x00000000
+
+
+#define mc2_glb_gcfg_meminitdone_MASK                              0x00000100
+#define mc2_glb_gcfg_meminitdone_ALIGN                             0
+#define mc2_glb_gcfg_meminitdone_BITS                              1
+#define mc2_glb_gcfg_meminitdone_SHIFT                             8
+#define mc2_glb_gcfg_meminitdone_DEFAULT                           0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_uart_tx_share_en_MASK                    0x00000080
+#define mc2_glb_gcfg_dpfe_uart_tx_share_en_ALIGN                   0
+#define mc2_glb_gcfg_dpfe_uart_tx_share_en_BITS                    1
+#define mc2_glb_gcfg_dpfe_uart_tx_share_en_SHIFT                   7
+#define mc2_glb_gcfg_dpfe_uart_tx_share_en_DEFAULT                 0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_uart_tx_en_MASK                          0x00000040
+#define mc2_glb_gcfg_dpfe_uart_tx_en_ALIGN                         0
+#define mc2_glb_gcfg_dpfe_uart_tx_en_BITS                          1
+#define mc2_glb_gcfg_dpfe_uart_tx_en_SHIFT                         6
+#define mc2_glb_gcfg_dpfe_uart_tx_en_DEFAULT                       0x00000000
+
+
+#define mc2_glb_gcfg_dpfe_uart_rx_mode_MASK                        0x00000030
+#define mc2_glb_gcfg_dpfe_uart_rx_mode_ALIGN                       0
+#define mc2_glb_gcfg_dpfe_uart_rx_mode_BITS                        2
+#define mc2_glb_gcfg_dpfe_uart_rx_mode_SHIFT                       4
+#define mc2_glb_gcfg_dpfe_uart_rx_mode_DEFAULT                     0x00000000
+
+
+#define mc2_glb_gcfg_sec_intr_mask_lock_MASK                       0x00000008
+#define mc2_glb_gcfg_sec_intr_mask_lock_ALIGN                      0
+#define mc2_glb_gcfg_sec_intr_mask_lock_BITS                       1
+#define mc2_glb_gcfg_sec_intr_mask_lock_SHIFT                      3
+#define mc2_glb_gcfg_sec_intr_mask_lock_DEFAULT                    0x00000000
+
+
+#define mc2_glb_gcfg_reserved3_MASK                                0x00000006
+#define mc2_glb_gcfg_reserved3_ALIGN                               0
+#define mc2_glb_gcfg_reserved3_BITS                                2
+#define mc2_glb_gcfg_reserved3_SHIFT                               1
+
+
+#define mc2_glb_gcfg_dpath_mode_MASK                               0x00000001
+#define mc2_glb_gcfg_dpath_mode_ALIGN                              0
+#define mc2_glb_gcfg_dpath_mode_BITS                               1
+#define mc2_glb_gcfg_dpath_mode_SHIFT                              0
+#define mc2_glb_gcfg_dpath_mode_DEFAULT                            0x00000000
+
+
+
+
+#define mc2_glb_auto_self_refresh_enable_MASK                      0x80000000
+#define mc2_glb_auto_self_refresh_enable_ALIGN                     0
+#define mc2_glb_auto_self_refresh_enable_BITS                      1
+#define mc2_glb_auto_self_refresh_enable_SHIFT                     31
+#define mc2_glb_auto_self_refresh_enable_DEFAULT                   0x00000000
+
+
+#define mc2_glb_auto_self_refresh_immediate_MASK                   0x40000000
+#define mc2_glb_auto_self_refresh_immediate_ALIGN                  0
+#define mc2_glb_auto_self_refresh_immediate_BITS                   1
+#define mc2_glb_auto_self_refresh_immediate_SHIFT                  30
+#define mc2_glb_auto_self_refresh_immediate_DEFAULT                0x00000000
+
+
+#define mc2_glb_auto_self_refresh_idle_count_MASK                  0x3fffffff
+#define mc2_glb_auto_self_refresh_idle_count_ALIGN                 0
+#define mc2_glb_auto_self_refresh_idle_count_BITS                  30
+#define mc2_glb_auto_self_refresh_idle_count_SHIFT                 0
+#define mc2_glb_auto_self_refresh_idle_count_DEFAULT               0x00000000
+
+
+
+
+#define mc2_glb_pwr_mgr_reserved0_MASK                             0xffff0000
+#define mc2_glb_pwr_mgr_reserved0_ALIGN                            0
+#define mc2_glb_pwr_mgr_reserved0_BITS                             16
+#define mc2_glb_pwr_mgr_reserved0_SHIFT                            16
+
+
+#define mc2_glb_pwr_mgr_idle_mask_MASK                             0x0000ffff
+#define mc2_glb_pwr_mgr_idle_mask_ALIGN                            0
+#define mc2_glb_pwr_mgr_idle_mask_BITS                             16
+#define mc2_glb_pwr_mgr_idle_mask_SHIFT                            0
+#define mc2_glb_pwr_mgr_idle_mask_DEFAULT                          0x00000000
+
+
+
+
+#define mc2_axi_acc_acc_eack_MASK                                  0x80000000
+#define mc2_axi_acc_acc_eack_ALIGN                                 0
+#define mc2_axi_acc_acc_eack_BITS                                  1
+#define mc2_axi_acc_acc_eack_SHIFT                                 31
+#define mc2_axi_acc_acc_eack_DEFAULT                               0x00000000
+
+
+#define mc2_axi_acc_reserved0_MASK                                 0x7fffff00
+#define mc2_axi_acc_reserved0_ALIGN                                0
+#define mc2_axi_acc_reserved0_BITS                                 23
+#define mc2_axi_acc_reserved0_SHIFT                                8
+
+
+#define mc2_axi_acc_acc_sw_MASK                                    0x00000080
+#define mc2_axi_acc_acc_sw_ALIGN                                   0
+#define mc2_axi_acc_acc_sw_BITS                                    1
+#define mc2_axi_acc_acc_sw_SHIFT                                   7
+#define mc2_axi_acc_acc_sw_DEFAULT                                 0x00000001
+
+
+#define mc2_axi_acc_acc_sr_MASK                                    0x00000040
+#define mc2_axi_acc_acc_sr_ALIGN                                   0
+#define mc2_axi_acc_acc_sr_BITS                                    1
+#define mc2_axi_acc_acc_sr_SHIFT                                   6
+#define mc2_axi_acc_acc_sr_DEFAULT                                 0x00000001
+
+
+#define mc2_axi_acc_acc_nsw_MASK                                   0x00000020
+#define mc2_axi_acc_acc_nsw_ALIGN                                  0
+#define mc2_axi_acc_acc_nsw_BITS                                   1
+#define mc2_axi_acc_acc_nsw_SHIFT                                  5
+#define mc2_axi_acc_acc_nsw_DEFAULT                                0x00000001
+
+
+#define mc2_axi_acc_acc_nsr_MASK                                   0x00000010
+#define mc2_axi_acc_acc_nsr_ALIGN                                  0
+#define mc2_axi_acc_acc_nsr_BITS                                   1
+#define mc2_axi_acc_acc_nsr_SHIFT                                  4
+#define mc2_axi_acc_acc_nsr_DEFAULT                                0x00000001
+
+
+#define mc2_axi_acc_perm_sw_MASK                                   0x00000008
+#define mc2_axi_acc_perm_sw_ALIGN                                  0
+#define mc2_axi_acc_perm_sw_BITS                                   1
+#define mc2_axi_acc_perm_sw_SHIFT                                  3
+#define mc2_axi_acc_perm_sw_DEFAULT                                0x00000001
+
+
+#define mc2_axi_acc_perm_sr_MASK                                   0x00000004
+#define mc2_axi_acc_perm_sr_ALIGN                                  0
+#define mc2_axi_acc_perm_sr_BITS                                   1
+#define mc2_axi_acc_perm_sr_SHIFT                                  2
+#define mc2_axi_acc_perm_sr_DEFAULT                                0x00000001
+
+
+#define mc2_axi_acc_perm_nsw_MASK                                  0x00000002
+#define mc2_axi_acc_perm_nsw_ALIGN                                 0
+#define mc2_axi_acc_perm_nsw_BITS                                  1
+#define mc2_axi_acc_perm_nsw_SHIFT                                 1
+#define mc2_axi_acc_perm_nsw_DEFAULT                               0x00000001
+
+
+#define mc2_axi_acc_perm_nsr_MASK                                  0x00000001
+#define mc2_axi_acc_perm_nsr_ALIGN                                 0
+#define mc2_axi_acc_perm_nsr_BITS                                  1
+#define mc2_axi_acc_perm_nsr_SHIFT                                 0
+#define mc2_axi_acc_perm_nsr_DEFAULT                               0x00000001
+
+
+
+
+#define mc2_axi_ver_reserved0_MASK                                 0xffffff00
+#define mc2_axi_ver_reserved0_ALIGN                                0
+#define mc2_axi_ver_reserved0_BITS                                 24
+#define mc2_axi_ver_reserved0_SHIFT                                8
+
+
+#define mc2_axi_ver_version_MASK                                   0x000000ff
+#define mc2_axi_ver_version_ALIGN                                  0
+#define mc2_axi_ver_version_BITS                                   8
+#define mc2_axi_ver_version_SHIFT                                  0
+#define mc2_axi_ver_version_DEFAULT                                0x00000000
+
+
+
+
+#define mc2_axi_CFG_reserved0_MASK                                 0xe0000000
+#define mc2_axi_CFG_reserved0_ALIGN                                0
+#define mc2_axi_CFG_reserved0_BITS                                 3
+#define mc2_axi_CFG_reserved0_SHIFT                                29
+
+
+#define mc2_axi_CFG_CPQ_WRITE_IN_TRANSIT_MASK                      0x1f800000
+#define mc2_axi_CFG_CPQ_WRITE_IN_TRANSIT_ALIGN                     0
+#define mc2_axi_CFG_CPQ_WRITE_IN_TRANSIT_BITS                      6
+#define mc2_axi_CFG_CPQ_WRITE_IN_TRANSIT_SHIFT                     23
+#define mc2_axi_CFG_CPQ_WRITE_IN_TRANSIT_DEFAULT                   0x00000008
+
+
+#define mc2_axi_CFG_CPU_WRITE_IN_TRANSIT_MASK                      0x007e0000
+#define mc2_axi_CFG_CPU_WRITE_IN_TRANSIT_ALIGN                     0
+#define mc2_axi_CFG_CPU_WRITE_IN_TRANSIT_BITS                      6
+#define mc2_axi_CFG_CPU_WRITE_IN_TRANSIT_SHIFT                     17
+#define mc2_axi_CFG_CPU_WRITE_IN_TRANSIT_DEFAULT                   0x00000008
+
+
+#define mc2_axi_CFG_WRITE_ACK_MODE_MASK                            0x00010000
+#define mc2_axi_CFG_WRITE_ACK_MODE_ALIGN                           0
+#define mc2_axi_CFG_WRITE_ACK_MODE_BITS                            1
+#define mc2_axi_CFG_WRITE_ACK_MODE_SHIFT                           16
+#define mc2_axi_CFG_WRITE_ACK_MODE_DEFAULT                         0x00000000
+
+
+#define mc2_axi_CFG_reserved1_MASK                                 0x0000f000
+#define mc2_axi_CFG_reserved1_ALIGN                                0
+#define mc2_axi_CFG_reserved1_BITS                                 4
+#define mc2_axi_CFG_reserved1_SHIFT                                12
+
+
+#define mc2_axi_CFG_MC_CAP_MUX_SEL_MASK                            0x00000f00
+#define mc2_axi_CFG_MC_CAP_MUX_SEL_ALIGN                           0
+#define mc2_axi_CFG_MC_CAP_MUX_SEL_BITS                            4
+#define mc2_axi_CFG_MC_CAP_MUX_SEL_SHIFT                           8
+#define mc2_axi_CFG_MC_CAP_MUX_SEL_DEFAULT                         0x00000000
+
+
+#define mc2_axi_CFG_MC_CAP_MUX_VLD_SEL_MASK                        0x000000c0
+#define mc2_axi_CFG_MC_CAP_MUX_VLD_SEL_ALIGN                       0
+#define mc2_axi_CFG_MC_CAP_MUX_VLD_SEL_BITS                        2
+#define mc2_axi_CFG_MC_CAP_MUX_VLD_SEL_SHIFT                       6
+#define mc2_axi_CFG_MC_CAP_MUX_VLD_SEL_DEFAULT                     0x00000000
+
+
+#define mc2_axi_CFG_MC_CAP_MUX_TRIG_SEL_MASK                       0x00000030
+#define mc2_axi_CFG_MC_CAP_MUX_TRIG_SEL_ALIGN                      0
+#define mc2_axi_CFG_MC_CAP_MUX_TRIG_SEL_BITS                       2
+#define mc2_axi_CFG_MC_CAP_MUX_TRIG_SEL_SHIFT                      4
+#define mc2_axi_CFG_MC_CAP_MUX_TRIG_SEL_DEFAULT                    0x00000000
+
+
+#define mc2_axi_CFG_RPT_NON_SECURE_ERR_MASK                        0x00000008
+#define mc2_axi_CFG_RPT_NON_SECURE_ERR_ALIGN                       0
+#define mc2_axi_CFG_RPT_NON_SECURE_ERR_BITS                        1
+#define mc2_axi_CFG_RPT_NON_SECURE_ERR_SHIFT                       3
+#define mc2_axi_CFG_RPT_NON_SECURE_ERR_DEFAULT                     0x00000000
+
+
+#define mc2_axi_CFG_RPT_SECURE_ERR_MASK                            0x00000004
+#define mc2_axi_CFG_RPT_SECURE_ERR_ALIGN                           0
+#define mc2_axi_CFG_RPT_SECURE_ERR_BITS                            1
+#define mc2_axi_CFG_RPT_SECURE_ERR_SHIFT                           2
+#define mc2_axi_CFG_RPT_SECURE_ERR_DEFAULT                         0x00000000
+
+
+#define mc2_axi_CFG_CMD_WAIT_WDATA_MASK                            0x00000002
+#define mc2_axi_CFG_CMD_WAIT_WDATA_ALIGN                           0
+#define mc2_axi_CFG_CMD_WAIT_WDATA_BITS                            1
+#define mc2_axi_CFG_CMD_WAIT_WDATA_SHIFT                           1
+#define mc2_axi_CFG_CMD_WAIT_WDATA_DEFAULT                         0x00000001
+
+
+#define mc2_axi_CFG_DIS_RBUS_MSTR_MASK                             0x00000001
+#define mc2_axi_CFG_DIS_RBUS_MSTR_ALIGN                            0
+#define mc2_axi_CFG_DIS_RBUS_MSTR_BITS                             1
+#define mc2_axi_CFG_DIS_RBUS_MSTR_SHIFT                            0
+#define mc2_axi_CFG_DIS_RBUS_MSTR_DEFAULT                          0x00000000
+
+
+
+
+#define mc2_axi_REP_ARB_MODE_reserved0_MASK                        0xfffff000
+#define mc2_axi_REP_ARB_MODE_reserved0_ALIGN                       0
+#define mc2_axi_REP_ARB_MODE_reserved0_BITS                        20
+#define mc2_axi_REP_ARB_MODE_reserved0_SHIFT                       12
+
+
+#define mc2_axi_REP_ARB_MODE_RD_BUFFER_SIZE_MASK                   0x00000800
+#define mc2_axi_REP_ARB_MODE_RD_BUFFER_SIZE_ALIGN                  0
+#define mc2_axi_REP_ARB_MODE_RD_BUFFER_SIZE_BITS                   1
+#define mc2_axi_REP_ARB_MODE_RD_BUFFER_SIZE_SHIFT                  11
+#define mc2_axi_REP_ARB_MODE_RD_BUFFER_SIZE_DEFAULT                0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_LEN_MASK               0x00000780
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_LEN_ALIGN              0
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_LEN_BITS               4
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_LEN_SHIFT              7
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_LEN_DEFAULT            0x00000007
+
+
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_EN_MASK                0x00000040
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_EN_ALIGN               0
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_EN_BITS                1
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_EN_SHIFT               6
+#define mc2_axi_REP_ARB_MODE_BRESP_PIPELINE_EN_DEFAULT             0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_DIS_RRESP_ERR_MODE_MASK               0x00000020
+#define mc2_axi_REP_ARB_MODE_DIS_RRESP_ERR_MODE_ALIGN              0
+#define mc2_axi_REP_ARB_MODE_DIS_RRESP_ERR_MODE_BITS               1
+#define mc2_axi_REP_ARB_MODE_DIS_RRESP_ERR_MODE_SHIFT              5
+#define mc2_axi_REP_ARB_MODE_DIS_RRESP_ERR_MODE_DEFAULT            0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_RD_FIFO_MODE_MASK                     0x00000010
+#define mc2_axi_REP_ARB_MODE_RD_FIFO_MODE_ALIGN                    0
+#define mc2_axi_REP_ARB_MODE_RD_FIFO_MODE_BITS                     1
+#define mc2_axi_REP_ARB_MODE_RD_FIFO_MODE_SHIFT                    4
+#define mc2_axi_REP_ARB_MODE_RD_FIFO_MODE_DEFAULT                  0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_RD_PACKET_MODE_MASK                   0x00000008
+#define mc2_axi_REP_ARB_MODE_RD_PACKET_MODE_ALIGN                  0
+#define mc2_axi_REP_ARB_MODE_RD_PACKET_MODE_BITS                   1
+#define mc2_axi_REP_ARB_MODE_RD_PACKET_MODE_SHIFT                  3
+#define mc2_axi_REP_ARB_MODE_RD_PACKET_MODE_DEFAULT                0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_DIS_BRESP_ERR_MODE_MASK               0x00000004
+#define mc2_axi_REP_ARB_MODE_DIS_BRESP_ERR_MODE_ALIGN              0
+#define mc2_axi_REP_ARB_MODE_DIS_BRESP_ERR_MODE_BITS               1
+#define mc2_axi_REP_ARB_MODE_DIS_BRESP_ERR_MODE_SHIFT              2
+#define mc2_axi_REP_ARB_MODE_DIS_BRESP_ERR_MODE_DEFAULT            0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_WR_FIFO_MODE_MASK                     0x00000002
+#define mc2_axi_REP_ARB_MODE_WR_FIFO_MODE_ALIGN                    0
+#define mc2_axi_REP_ARB_MODE_WR_FIFO_MODE_BITS                     1
+#define mc2_axi_REP_ARB_MODE_WR_FIFO_MODE_SHIFT                    1
+#define mc2_axi_REP_ARB_MODE_WR_FIFO_MODE_DEFAULT                  0x00000000
+
+
+#define mc2_axi_REP_ARB_MODE_WR_REPLY_MODE_MASK                    0x00000001
+#define mc2_axi_REP_ARB_MODE_WR_REPLY_MODE_ALIGN                   0
+#define mc2_axi_REP_ARB_MODE_WR_REPLY_MODE_BITS                    1
+#define mc2_axi_REP_ARB_MODE_WR_REPLY_MODE_SHIFT                   0
+#define mc2_axi_REP_ARB_MODE_WR_REPLY_MODE_DEFAULT                 0x00000000
+
+
+
+
+#define mc2_axi_queue_cfg_reserved0_MASK                           0xfffffc00
+#define mc2_axi_queue_cfg_reserved0_ALIGN                          0
+#define mc2_axi_queue_cfg_reserved0_BITS                           22
+#define mc2_axi_queue_cfg_reserved0_SHIFT                          10
+
+
+#define mc2_axi_queue_cfg_disable_backpressure_MASK                0x00000200
+#define mc2_axi_queue_cfg_disable_backpressure_ALIGN               0
+#define mc2_axi_queue_cfg_disable_backpressure_BITS                1
+#define mc2_axi_queue_cfg_disable_backpressure_SHIFT               9
+#define mc2_axi_queue_cfg_disable_backpressure_DEFAULT             0x00000000
+
+
+#define mc2_axi_queue_cfg_overflow_drop_MASK                       0x00000100
+#define mc2_axi_queue_cfg_overflow_drop_ALIGN                      0
+#define mc2_axi_queue_cfg_overflow_drop_BITS                       1
+#define mc2_axi_queue_cfg_overflow_drop_SHIFT                      8
+#define mc2_axi_queue_cfg_overflow_drop_DEFAULT                    0x00000000
+
+
+#define mc2_axi_queue_cfg_reserved1_MASK                           0x000000f0
+#define mc2_axi_queue_cfg_reserved1_ALIGN                          0
+#define mc2_axi_queue_cfg_reserved1_BITS                           4
+#define mc2_axi_queue_cfg_reserved1_SHIFT                          4
+
+
+#define mc2_axi_queue_cfg_queue_start_MASK                         0x0000000f
+#define mc2_axi_queue_cfg_queue_start_ALIGN                        0
+#define mc2_axi_queue_cfg_queue_start_BITS                         4
+#define mc2_axi_queue_cfg_queue_start_SHIFT                        0
+#define mc2_axi_queue_cfg_queue_start_DEFAULT                      0x00000000
+
+
+
+
+#define mc2_axi_queue_size0_reserved0_MASK                         0x80000000
+#define mc2_axi_queue_size0_reserved0_ALIGN                        0
+#define mc2_axi_queue_size0_reserved0_BITS                         1
+#define mc2_axi_queue_size0_reserved0_SHIFT                        31
+
+
+#define mc2_axi_queue_size0_size3_MASK                             0x7f000000
+#define mc2_axi_queue_size0_size3_ALIGN                            0
+#define mc2_axi_queue_size0_size3_BITS                             7
+#define mc2_axi_queue_size0_size3_SHIFT                            24
+#define mc2_axi_queue_size0_size3_DEFAULT                          0x00000008
+
+
+#define mc2_axi_queue_size0_reserved1_MASK                         0x00800000
+#define mc2_axi_queue_size0_reserved1_ALIGN                        0
+#define mc2_axi_queue_size0_reserved1_BITS                         1
+#define mc2_axi_queue_size0_reserved1_SHIFT                        23
+
+
+#define mc2_axi_queue_size0_size2_MASK                             0x007f0000
+#define mc2_axi_queue_size0_size2_ALIGN                            0
+#define mc2_axi_queue_size0_size2_BITS                             7
+#define mc2_axi_queue_size0_size2_SHIFT                            16
+#define mc2_axi_queue_size0_size2_DEFAULT                          0x00000008
+
+
+#define mc2_axi_queue_size0_reserved2_MASK                         0x00008000
+#define mc2_axi_queue_size0_reserved2_ALIGN                        0
+#define mc2_axi_queue_size0_reserved2_BITS                         1
+#define mc2_axi_queue_size0_reserved2_SHIFT                        15
+
+
+#define mc2_axi_queue_size0_size1_MASK                             0x00007f00
+#define mc2_axi_queue_size0_size1_ALIGN                            0
+#define mc2_axi_queue_size0_size1_BITS                             7
+#define mc2_axi_queue_size0_size1_SHIFT                            8
+#define mc2_axi_queue_size0_size1_DEFAULT                          0x00000008
+
+
+#define mc2_axi_queue_size0_reserved3_MASK                         0x00000080
+#define mc2_axi_queue_size0_reserved3_ALIGN                        0
+#define mc2_axi_queue_size0_reserved3_BITS                         1
+#define mc2_axi_queue_size0_reserved3_SHIFT                        7
+
+
+#define mc2_axi_queue_size0_size0_MASK                             0x0000007f
+#define mc2_axi_queue_size0_size0_ALIGN                            0
+#define mc2_axi_queue_size0_size0_BITS                             7
+#define mc2_axi_queue_size0_size0_SHIFT                            0
+#define mc2_axi_queue_size0_size0_DEFAULT                          0x00000008
+
+
+
+
+#define mc2_axi_queue_map0_reserved0_MASK                          0xffffff00
+#define mc2_axi_queue_map0_reserved0_ALIGN                         0
+#define mc2_axi_queue_map0_reserved0_BITS                          24
+#define mc2_axi_queue_map0_reserved0_SHIFT                         8
+
+
+#define mc2_axi_queue_map0_cpq_rd_MASK                             0x000000c0
+#define mc2_axi_queue_map0_cpq_rd_ALIGN                            0
+#define mc2_axi_queue_map0_cpq_rd_BITS                             2
+#define mc2_axi_queue_map0_cpq_rd_SHIFT                            6
+#define mc2_axi_queue_map0_cpq_rd_DEFAULT                          0x00000003
+
+
+#define mc2_axi_queue_map0_cpq_wr_MASK                             0x00000030
+#define mc2_axi_queue_map0_cpq_wr_ALIGN                            0
+#define mc2_axi_queue_map0_cpq_wr_BITS                             2
+#define mc2_axi_queue_map0_cpq_wr_SHIFT                            4
+#define mc2_axi_queue_map0_cpq_wr_DEFAULT                          0x00000002
+
+
+#define mc2_axi_queue_map0_cpu_rd_MASK                             0x0000000c
+#define mc2_axi_queue_map0_cpu_rd_ALIGN                            0
+#define mc2_axi_queue_map0_cpu_rd_BITS                             2
+#define mc2_axi_queue_map0_cpu_rd_SHIFT                            2
+#define mc2_axi_queue_map0_cpu_rd_DEFAULT                          0x00000001
+
+
+#define mc2_axi_queue_map0_cpu_wr_MASK                             0x00000003
+#define mc2_axi_queue_map0_cpu_wr_ALIGN                            0
+#define mc2_axi_queue_map0_cpu_wr_BITS                             2
+#define mc2_axi_queue_map0_cpu_wr_SHIFT                            0
+#define mc2_axi_queue_map0_cpu_wr_DEFAULT                          0x00000000
+
+
+#define mc2_axi_SCRATCH_scratch_MASK                               0xffffffff
+#define mc2_axi_SCRATCH_scratch_ALIGN                              0
+#define mc2_axi_SCRATCH_scratch_BITS                               32
+#define mc2_axi_SCRATCH_scratch_SHIFT                              0
+#define mc2_axi_SCRATCH_scratch_DEFAULT                            0x00000000
+
+
+#define mc2_chn_ddr_acc_acc_eack_MASK                              0x80000000
+#define mc2_chn_ddr_acc_acc_eack_ALIGN                             0
+#define mc2_chn_ddr_acc_acc_eack_BITS                              1
+#define mc2_chn_ddr_acc_acc_eack_SHIFT                             31
+#define mc2_chn_ddr_acc_acc_eack_DEFAULT                           0x00000000
+
+
+#define mc2_chn_ddr_acc_reserved0_MASK                             0x7fffff00
+#define mc2_chn_ddr_acc_reserved0_ALIGN                            0
+#define mc2_chn_ddr_acc_reserved0_BITS                             23
+#define mc2_chn_ddr_acc_reserved0_SHIFT                            8
+
+
+#define mc2_chn_ddr_acc_acc_sw_MASK                                0x00000080
+#define mc2_chn_ddr_acc_acc_sw_ALIGN                               0
+#define mc2_chn_ddr_acc_acc_sw_BITS                                1
+#define mc2_chn_ddr_acc_acc_sw_SHIFT                               7
+#define mc2_chn_ddr_acc_acc_sw_DEFAULT                             0x00000001
+
+
+#define mc2_chn_ddr_acc_acc_sr_MASK                                0x00000040
+#define mc2_chn_ddr_acc_acc_sr_ALIGN                               0
+#define mc2_chn_ddr_acc_acc_sr_BITS                                1
+#define mc2_chn_ddr_acc_acc_sr_SHIFT                               6
+#define mc2_chn_ddr_acc_acc_sr_DEFAULT                             0x00000001
+
+
+#define mc2_chn_ddr_acc_acc_nsw_MASK                               0x00000020
+#define mc2_chn_ddr_acc_acc_nsw_ALIGN                              0
+#define mc2_chn_ddr_acc_acc_nsw_BITS                               1
+#define mc2_chn_ddr_acc_acc_nsw_SHIFT                              5
+#define mc2_chn_ddr_acc_acc_nsw_DEFAULT                            0x00000001
+
+
+#define mc2_chn_ddr_acc_acc_nsr_MASK                               0x00000010
+#define mc2_chn_ddr_acc_acc_nsr_ALIGN                              0
+#define mc2_chn_ddr_acc_acc_nsr_BITS                               1
+#define mc2_chn_ddr_acc_acc_nsr_SHIFT                              4
+#define mc2_chn_ddr_acc_acc_nsr_DEFAULT                            0x00000001
+
+
+#define mc2_chn_ddr_acc_perm_sw_MASK                               0x00000008
+#define mc2_chn_ddr_acc_perm_sw_ALIGN                              0
+#define mc2_chn_ddr_acc_perm_sw_BITS                               1
+#define mc2_chn_ddr_acc_perm_sw_SHIFT                              3
+#define mc2_chn_ddr_acc_perm_sw_DEFAULT                            0x00000001
+
+
+#define mc2_chn_ddr_acc_perm_sr_MASK                               0x00000004
+#define mc2_chn_ddr_acc_perm_sr_ALIGN                              0
+#define mc2_chn_ddr_acc_perm_sr_BITS                               1
+#define mc2_chn_ddr_acc_perm_sr_SHIFT                              2
+#define mc2_chn_ddr_acc_perm_sr_DEFAULT                            0x00000001
+
+
+#define mc2_chn_ddr_acc_perm_nsw_MASK                              0x00000002
+#define mc2_chn_ddr_acc_perm_nsw_ALIGN                             0
+#define mc2_chn_ddr_acc_perm_nsw_BITS                              1
+#define mc2_chn_ddr_acc_perm_nsw_SHIFT                             1
+#define mc2_chn_ddr_acc_perm_nsw_DEFAULT                           0x00000001
+
+
+#define mc2_chn_ddr_acc_perm_nsr_MASK                              0x00000001
+#define mc2_chn_ddr_acc_perm_nsr_ALIGN                             0
+#define mc2_chn_ddr_acc_perm_nsr_BITS                              1
+#define mc2_chn_ddr_acc_perm_nsr_SHIFT                             0
+#define mc2_chn_ddr_acc_perm_nsr_DEFAULT                           0x00000001
+
+
+
+
+#define mc2_chn_ddr_ver_reserved0_MASK                             0xffffff00
+#define mc2_chn_ddr_ver_reserved0_ALIGN                            0
+#define mc2_chn_ddr_ver_reserved0_BITS                             24
+#define mc2_chn_ddr_ver_reserved0_SHIFT                            8
+
+
+#define mc2_chn_ddr_ver_version_MASK                               0x000000ff
+#define mc2_chn_ddr_ver_version_ALIGN                              0
+#define mc2_chn_ddr_ver_version_BITS                               8
+#define mc2_chn_ddr_ver_version_SHIFT                              0
+#define mc2_chn_ddr_ver_version_DEFAULT                            0x00000000
+
+
+
+
+#define mc2_chn_ddr_chn_arb_cfg_fifo_mode_MASK                     0x80000000
+#define mc2_chn_ddr_chn_arb_cfg_fifo_mode_ALIGN                    0
+#define mc2_chn_ddr_chn_arb_cfg_fifo_mode_BITS                     1
+#define mc2_chn_ddr_chn_arb_cfg_fifo_mode_SHIFT                    31
+#define mc2_chn_ddr_chn_arb_cfg_fifo_mode_DEFAULT                  0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_addr_chk_disable_MASK              0x40000000
+#define mc2_chn_ddr_chn_arb_cfg_addr_chk_disable_ALIGN             0
+#define mc2_chn_ddr_chn_arb_cfg_addr_chk_disable_BITS              1
+#define mc2_chn_ddr_chn_arb_cfg_addr_chk_disable_SHIFT             30
+#define mc2_chn_ddr_chn_arb_cfg_addr_chk_disable_DEFAULT           0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_reserved0_MASK                     0x3c000000
+#define mc2_chn_ddr_chn_arb_cfg_reserved0_ALIGN                    0
+#define mc2_chn_ddr_chn_arb_cfg_reserved0_BITS                     4
+#define mc2_chn_ddr_chn_arb_cfg_reserved0_SHIFT                    26
+
+
+#define mc2_chn_ddr_chn_arb_cfg_always_auto_precharge_MASK         0x02000000
+#define mc2_chn_ddr_chn_arb_cfg_always_auto_precharge_ALIGN        0
+#define mc2_chn_ddr_chn_arb_cfg_always_auto_precharge_BITS         1
+#define mc2_chn_ddr_chn_arb_cfg_always_auto_precharge_SHIFT        25
+#define mc2_chn_ddr_chn_arb_cfg_always_auto_precharge_DEFAULT      0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_auto_precharge_MASK                0x01000000
+#define mc2_chn_ddr_chn_arb_cfg_auto_precharge_ALIGN               0
+#define mc2_chn_ddr_chn_arb_cfg_auto_precharge_BITS                1
+#define mc2_chn_ddr_chn_arb_cfg_auto_precharge_SHIFT               24
+#define mc2_chn_ddr_chn_arb_cfg_auto_precharge_DEFAULT             0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_reserved1_MASK                     0x00ffffe0
+#define mc2_chn_ddr_chn_arb_cfg_reserved1_ALIGN                    0
+#define mc2_chn_ddr_chn_arb_cfg_reserved1_BITS                     19
+#define mc2_chn_ddr_chn_arb_cfg_reserved1_SHIFT                    5
+
+
+#define mc2_chn_ddr_chn_arb_cfg_extra_slot_en_MASK                 0x00000010
+#define mc2_chn_ddr_chn_arb_cfg_extra_slot_en_ALIGN                0
+#define mc2_chn_ddr_chn_arb_cfg_extra_slot_en_BITS                 1
+#define mc2_chn_ddr_chn_arb_cfg_extra_slot_en_SHIFT                4
+#define mc2_chn_ddr_chn_arb_cfg_extra_slot_en_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpq_MASK               0x00000008
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpq_ALIGN              0
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpq_BITS               1
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpq_SHIFT              3
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpq_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpu_MASK               0x00000004
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpu_ALIGN              0
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpu_BITS               1
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpu_SHIFT              2
+#define mc2_chn_ddr_chn_arb_cfg_per_intf_rl_cpu_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_pri_elevate_dis_MASK               0x00000002
+#define mc2_chn_ddr_chn_arb_cfg_pri_elevate_dis_ALIGN              0
+#define mc2_chn_ddr_chn_arb_cfg_pri_elevate_dis_BITS               1
+#define mc2_chn_ddr_chn_arb_cfg_pri_elevate_dis_SHIFT              1
+#define mc2_chn_ddr_chn_arb_cfg_pri_elevate_dis_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_cfg_arb_mode_MASK                      0x00000001
+#define mc2_chn_ddr_chn_arb_cfg_arb_mode_ALIGN                     0
+#define mc2_chn_ddr_chn_arb_cfg_arb_mode_BITS                      1
+#define mc2_chn_ddr_chn_arb_cfg_arb_mode_SHIFT                     0
+#define mc2_chn_ddr_chn_arb_cfg_arb_mode_DEFAULT                   0x00000000
+
+
+
+
+#define mc2_chn_ddr_chn_arb_param_reserved0_MASK                   0x80000000
+#define mc2_chn_ddr_chn_arb_param_reserved0_ALIGN                  0
+#define mc2_chn_ddr_chn_arb_param_reserved0_BITS                   1
+#define mc2_chn_ddr_chn_arb_param_reserved0_SHIFT                  31
+
+
+#define mc2_chn_ddr_chn_arb_param_vq2_timeout_MASK                 0x7f000000
+#define mc2_chn_ddr_chn_arb_param_vq2_timeout_ALIGN                0
+#define mc2_chn_ddr_chn_arb_param_vq2_timeout_BITS                 7
+#define mc2_chn_ddr_chn_arb_param_vq2_timeout_SHIFT                24
+#define mc2_chn_ddr_chn_arb_param_vq2_timeout_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_param_reserved1_MASK                   0x00800000
+#define mc2_chn_ddr_chn_arb_param_reserved1_ALIGN                  0
+#define mc2_chn_ddr_chn_arb_param_reserved1_BITS                   1
+#define mc2_chn_ddr_chn_arb_param_reserved1_SHIFT                  23
+
+
+#define mc2_chn_ddr_chn_arb_param_vq0_timeout_MASK                 0x007f0000
+#define mc2_chn_ddr_chn_arb_param_vq0_timeout_ALIGN                0
+#define mc2_chn_ddr_chn_arb_param_vq0_timeout_BITS                 7
+#define mc2_chn_ddr_chn_arb_param_vq0_timeout_SHIFT                16
+#define mc2_chn_ddr_chn_arb_param_vq0_timeout_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_chn_arb_param_reserved2_MASK                   0x0000c000
+#define mc2_chn_ddr_chn_arb_param_reserved2_ALIGN                  0
+#define mc2_chn_ddr_chn_arb_param_reserved2_BITS                   2
+#define mc2_chn_ddr_chn_arb_param_reserved2_SHIFT                  14
+
+
+#define mc2_chn_ddr_chn_arb_param_wrr6_weight_MASK                 0x00003000
+#define mc2_chn_ddr_chn_arb_param_wrr6_weight_ALIGN                0
+#define mc2_chn_ddr_chn_arb_param_wrr6_weight_BITS                 2
+#define mc2_chn_ddr_chn_arb_param_wrr6_weight_SHIFT                12
+#define mc2_chn_ddr_chn_arb_param_wrr6_weight_DEFAULT              0x00000001
+
+
+#define mc2_chn_ddr_chn_arb_param_wrr5_weight_MASK                 0x00000c00
+#define mc2_chn_ddr_chn_arb_param_wrr5_weight_ALIGN                0
+#define mc2_chn_ddr_chn_arb_param_wrr5_weight_BITS                 2
+#define mc2_chn_ddr_chn_arb_param_wrr5_weight_SHIFT                10
+#define mc2_chn_ddr_chn_arb_param_wrr5_weight_DEFAULT              0x00000001
+
+
+#define mc2_chn_ddr_chn_arb_param_wrr0_weight_MASK                 0x00000300
+#define mc2_chn_ddr_chn_arb_param_wrr0_weight_ALIGN                0
+#define mc2_chn_ddr_chn_arb_param_wrr0_weight_BITS                 2
+#define mc2_chn_ddr_chn_arb_param_wrr0_weight_SHIFT                8
+#define mc2_chn_ddr_chn_arb_param_wrr0_weight_DEFAULT              0x00000001
+
+
+#define mc2_chn_ddr_chn_arb_param_reserved3_MASK                   0x000000e0
+#define mc2_chn_ddr_chn_arb_param_reserved3_ALIGN                  0
+#define mc2_chn_ddr_chn_arb_param_reserved3_BITS                   3
+#define mc2_chn_ddr_chn_arb_param_reserved3_SHIFT                  5
+
+
+#define mc2_chn_ddr_chn_arb_param_rdwr_wrr_weight_MASK             0x0000001f
+#define mc2_chn_ddr_chn_arb_param_rdwr_wrr_weight_ALIGN            0
+#define mc2_chn_ddr_chn_arb_param_rdwr_wrr_weight_BITS             5
+#define mc2_chn_ddr_chn_arb_param_rdwr_wrr_weight_SHIFT            0
+#define mc2_chn_ddr_chn_arb_param_rdwr_wrr_weight_DEFAULT          0x00000010
+
+
+
+
+#define mc2_chn_ddr_chn_sch_cfg_opt_chn_hshk_dis_MASK              0x80000000
+#define mc2_chn_ddr_chn_sch_cfg_opt_chn_hshk_dis_ALIGN             0
+#define mc2_chn_ddr_chn_sch_cfg_opt_chn_hshk_dis_BITS              1
+#define mc2_chn_ddr_chn_sch_cfg_opt_chn_hshk_dis_SHIFT             31
+#define mc2_chn_ddr_chn_sch_cfg_opt_chn_hshk_dis_DEFAULT           0x00000000
+
+
+#define mc2_chn_ddr_chn_sch_cfg_reserved0_MASK                     0x7ffffff8
+#define mc2_chn_ddr_chn_sch_cfg_reserved0_ALIGN                    0
+#define mc2_chn_ddr_chn_sch_cfg_reserved0_BITS                     28
+#define mc2_chn_ddr_chn_sch_cfg_reserved0_SHIFT                    3
+
+
+#define mc2_chn_ddr_chn_sch_cfg_num_cmdr_MASK                      0x00000007
+#define mc2_chn_ddr_chn_sch_cfg_num_cmdr_ALIGN                     0
+#define mc2_chn_ddr_chn_sch_cfg_num_cmdr_BITS                      3
+#define mc2_chn_ddr_chn_sch_cfg_num_cmdr_SHIFT                     0
+#define mc2_chn_ddr_chn_sch_cfg_num_cmdr_DEFAULT                   0x00000007
+
+
+
+
+#define mc2_chn_ddr_phy_st_reserved0_MASK                          0xffffffe0
+#define mc2_chn_ddr_phy_st_reserved0_ALIGN                         0
+#define mc2_chn_ddr_phy_st_reserved0_BITS                          27
+#define mc2_chn_ddr_phy_st_reserved0_SHIFT                         5
+
+
+#define mc2_chn_ddr_phy_st_phy_st_phy_ready_MASK                   0x00000010
+#define mc2_chn_ddr_phy_st_phy_st_phy_ready_ALIGN                  0
+#define mc2_chn_ddr_phy_st_phy_st_phy_ready_BITS                   1
+#define mc2_chn_ddr_phy_st_phy_st_phy_ready_SHIFT                  4
+#define mc2_chn_ddr_phy_st_phy_st_phy_ready_DEFAULT                0x00000000
+
+
+#define mc2_chn_ddr_phy_st_reserved1_MASK                          0x00000008
+#define mc2_chn_ddr_phy_st_reserved1_ALIGN                         0
+#define mc2_chn_ddr_phy_st_reserved1_BITS                          1
+#define mc2_chn_ddr_phy_st_reserved1_SHIFT                         3
+
+
+#define mc2_chn_ddr_phy_st_phy_st_sw_reset_MASK                    0x00000004
+#define mc2_chn_ddr_phy_st_phy_st_sw_reset_ALIGN                   0
+#define mc2_chn_ddr_phy_st_phy_st_sw_reset_BITS                    1
+#define mc2_chn_ddr_phy_st_phy_st_sw_reset_SHIFT                   2
+#define mc2_chn_ddr_phy_st_phy_st_sw_reset_DEFAULT                 0x00000000
+
+
+#define mc2_chn_ddr_phy_st_phy_st_hw_reset_MASK                    0x00000002
+#define mc2_chn_ddr_phy_st_phy_st_hw_reset_ALIGN                   0
+#define mc2_chn_ddr_phy_st_phy_st_hw_reset_BITS                    1
+#define mc2_chn_ddr_phy_st_phy_st_hw_reset_SHIFT                   1
+#define mc2_chn_ddr_phy_st_phy_st_hw_reset_DEFAULT                 0x00000000
+
+
+#define mc2_chn_ddr_phy_st_phy_st_phy_power_up_MASK                0x00000001
+#define mc2_chn_ddr_phy_st_phy_st_phy_power_up_ALIGN               0
+#define mc2_chn_ddr_phy_st_phy_st_phy_power_up_BITS                1
+#define mc2_chn_ddr_phy_st_phy_st_phy_power_up_SHIFT               0
+#define mc2_chn_ddr_phy_st_phy_st_phy_power_up_DEFAULT             0x00000000
+
+
+
+
+#define mc2_chn_ddr_dram_cfg_reserved0_MASK                        0xfffe0000
+#define mc2_chn_ddr_dram_cfg_reserved0_ALIGN                       0
+#define mc2_chn_ddr_dram_cfg_reserved0_BITS                        15
+#define mc2_chn_ddr_dram_cfg_reserved0_SHIFT                       17
+
+
+#define mc2_chn_ddr_dram_cfg_dram_srx_cmd_MASK                     0x00010000
+#define mc2_chn_ddr_dram_cfg_dram_srx_cmd_ALIGN                    0
+#define mc2_chn_ddr_dram_cfg_dram_srx_cmd_BITS                     1
+#define mc2_chn_ddr_dram_cfg_dram_srx_cmd_SHIFT                    16
+#define mc2_chn_ddr_dram_cfg_dram_srx_cmd_DEFAULT                  0x00000000
+
+
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs_mode_MASK                 0x0000c000
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs_mode_ALIGN                0
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs_mode_BITS                 2
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs_mode_SHIFT                14
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs_mode_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs1_enable_MASK              0x00002000
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs1_enable_ALIGN             0
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs1_enable_BITS              1
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs1_enable_SHIFT             13
+#define mc2_chn_ddr_dram_cfg_dram_cfg_cs1_enable_DEFAULT           0x00000000
+
+
+#define mc2_chn_ddr_dram_cfg_reserved1_MASK                        0x00001800
+#define mc2_chn_ddr_dram_cfg_reserved1_ALIGN                       0
+#define mc2_chn_ddr_dram_cfg_reserved1_BITS                        2
+#define mc2_chn_ddr_dram_cfg_reserved1_SHIFT                       11
+
+
+#define mc2_chn_ddr_dram_cfg_dram_cfg_2taddrcmd_MASK               0x00000400
+#define mc2_chn_ddr_dram_cfg_dram_cfg_2taddrcmd_ALIGN              0
+#define mc2_chn_ddr_dram_cfg_dram_cfg_2taddrcmd_BITS               1
+#define mc2_chn_ddr_dram_cfg_dram_cfg_2taddrcmd_SHIFT              10
+#define mc2_chn_ddr_dram_cfg_dram_cfg_2taddrcmd_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_dram_cfg_cmd_timeout_MASK                      0x000003f0
+#define mc2_chn_ddr_dram_cfg_cmd_timeout_ALIGN                     0
+#define mc2_chn_ddr_dram_cfg_cmd_timeout_BITS                      6
+#define mc2_chn_ddr_dram_cfg_cmd_timeout_SHIFT                     4
+#define mc2_chn_ddr_dram_cfg_cmd_timeout_DEFAULT                   0x0000003f
+
+
+#define mc2_chn_ddr_dram_cfg_dram_cfg_dramtype_MASK                0x0000000f
+#define mc2_chn_ddr_dram_cfg_dram_cfg_dramtype_ALIGN               0
+#define mc2_chn_ddr_dram_cfg_dram_cfg_dramtype_BITS                4
+#define mc2_chn_ddr_dram_cfg_dram_cfg_dramtype_SHIFT               0
+#define mc2_chn_ddr_dram_cfg_dram_cfg_dramtype_DEFAULT             0x00000004
+
+
+
+
+#define mc2_chn_ddr_dcmd_sch_sel_MASK                              0x80000000
+#define mc2_chn_ddr_dcmd_sch_sel_ALIGN                             0
+#define mc2_chn_ddr_dcmd_sch_sel_BITS                              1
+#define mc2_chn_ddr_dcmd_sch_sel_SHIFT                             31
+#define mc2_chn_ddr_dcmd_sch_sel_DEFAULT                           0x00000000
+
+
+#define mc2_chn_ddr_dcmd_reserved0_MASK                            0x7ffe0000
+#define mc2_chn_ddr_dcmd_reserved0_ALIGN                           0
+#define mc2_chn_ddr_dcmd_reserved0_BITS                            14
+#define mc2_chn_ddr_dcmd_reserved0_SHIFT                           17
+
+
+#define mc2_chn_ddr_dcmd_dramcmdreq_MASK                           0x00010000
+#define mc2_chn_ddr_dcmd_dramcmdreq_ALIGN                          0
+#define mc2_chn_ddr_dcmd_dramcmdreq_BITS                           1
+#define mc2_chn_ddr_dcmd_dramcmdreq_SHIFT                          16
+#define mc2_chn_ddr_dcmd_dramcmdreq_DEFAULT                        0x00000000
+
+
+#define mc2_chn_ddr_dcmd_reserved1_MASK                            0x0000fc00
+#define mc2_chn_ddr_dcmd_reserved1_ALIGN                           0
+#define mc2_chn_ddr_dcmd_reserved1_BITS                            6
+#define mc2_chn_ddr_dcmd_reserved1_SHIFT                           10
+
+
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs1_MASK                       0x00000200
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs1_ALIGN                      0
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs1_BITS                       1
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs1_SHIFT                      9
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs1_DEFAULT                    0x00000000
+
+
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs0_MASK                       0x00000100
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs0_ALIGN                      0
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs0_BITS                       1
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs0_SHIFT                      8
+#define mc2_chn_ddr_dcmd_dcmd_memcmdcs0_DEFAULT                    0x00000000
+
+
+#define mc2_chn_ddr_dcmd_reserved2_MASK                            0x000000e0
+#define mc2_chn_ddr_dcmd_reserved2_ALIGN                           0
+#define mc2_chn_ddr_dcmd_reserved2_BITS                            3
+#define mc2_chn_ddr_dcmd_reserved2_SHIFT                           5
+
+
+#define mc2_chn_ddr_dcmd_dcmd_memcmd_MASK                          0x0000001f
+#define mc2_chn_ddr_dcmd_dcmd_memcmd_ALIGN                         0
+#define mc2_chn_ddr_dcmd_dcmd_memcmd_BITS                          5
+#define mc2_chn_ddr_dcmd_dcmd_memcmd_SHIFT                         0
+#define mc2_chn_ddr_dcmd_dcmd_memcmd_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_chn_ddr_dmode_0_reserved0_MASK                         0x80000000
+#define mc2_chn_ddr_dmode_0_reserved0_ALIGN                        0
+#define mc2_chn_ddr_dmode_0_reserved0_BITS                         1
+#define mc2_chn_ddr_dmode_0_reserved0_SHIFT                        31
+
+
+#define mc2_chn_ddr_dmode_0_dmode_modedata_MASK                    0x7fff0000
+#define mc2_chn_ddr_dmode_0_dmode_modedata_ALIGN                   0
+#define mc2_chn_ddr_dmode_0_dmode_modedata_BITS                    15
+#define mc2_chn_ddr_dmode_0_dmode_modedata_SHIFT                   16
+#define mc2_chn_ddr_dmode_0_dmode_modedata_DEFAULT                 0x00000000
+
+
+#define mc2_chn_ddr_dmode_0_reserved1_MASK                         0x00008000
+#define mc2_chn_ddr_dmode_0_reserved1_ALIGN                        0
+#define mc2_chn_ddr_dmode_0_reserved1_BITS                         1
+#define mc2_chn_ddr_dmode_0_reserved1_SHIFT                        15
+
+
+#define mc2_chn_ddr_dmode_0_dmode_emodedata_MASK                   0x00007fff
+#define mc2_chn_ddr_dmode_0_dmode_emodedata_ALIGN                  0
+#define mc2_chn_ddr_dmode_0_dmode_emodedata_BITS                   15
+#define mc2_chn_ddr_dmode_0_dmode_emodedata_SHIFT                  0
+#define mc2_chn_ddr_dmode_0_dmode_emodedata_DEFAULT                0x00000000
+
+
+
+
+#define mc2_chn_ddr_dmode_2_reserved0_MASK                         0x80000000
+#define mc2_chn_ddr_dmode_2_reserved0_ALIGN                        0
+#define mc2_chn_ddr_dmode_2_reserved0_BITS                         1
+#define mc2_chn_ddr_dmode_2_reserved0_SHIFT                        31
+
+
+#define mc2_chn_ddr_dmode_2_dmode_emode3data_MASK                  0x7fff0000
+#define mc2_chn_ddr_dmode_2_dmode_emode3data_ALIGN                 0
+#define mc2_chn_ddr_dmode_2_dmode_emode3data_BITS                  15
+#define mc2_chn_ddr_dmode_2_dmode_emode3data_SHIFT                 16
+#define mc2_chn_ddr_dmode_2_dmode_emode3data_DEFAULT               0x00000000
+
+
+#define mc2_chn_ddr_dmode_2_reserved1_MASK                         0x00008000
+#define mc2_chn_ddr_dmode_2_reserved1_ALIGN                        0
+#define mc2_chn_ddr_dmode_2_reserved1_BITS                         1
+#define mc2_chn_ddr_dmode_2_reserved1_SHIFT                        15
+
+
+#define mc2_chn_ddr_dmode_2_dmode_emode2data_MASK                  0x00007fff
+#define mc2_chn_ddr_dmode_2_dmode_emode2data_ALIGN                 0
+#define mc2_chn_ddr_dmode_2_dmode_emode2data_BITS                  15
+#define mc2_chn_ddr_dmode_2_dmode_emode2data_SHIFT                 0
+#define mc2_chn_ddr_dmode_2_dmode_emode2data_DEFAULT               0x00000000
+
+
+
+
+#define mc2_chn_ddr_odt_reserved0_MASK                             0xfffffc00
+#define mc2_chn_ddr_odt_reserved0_ALIGN                            0
+#define mc2_chn_ddr_odt_reserved0_BITS                             22
+#define mc2_chn_ddr_odt_reserved0_SHIFT                            10
+
+
+#define mc2_chn_ddr_odt_odt_dynodten_MASK                          0x00000200
+#define mc2_chn_ddr_odt_odt_dynodten_ALIGN                         0
+#define mc2_chn_ddr_odt_odt_dynodten_BITS                          1
+#define mc2_chn_ddr_odt_odt_dynodten_SHIFT                         9
+#define mc2_chn_ddr_odt_odt_dynodten_DEFAULT                       0x00000001
+
+
+#define mc2_chn_ddr_odt_odt_csoddodten_MASK                        0x00000100
+#define mc2_chn_ddr_odt_odt_csoddodten_ALIGN                       0
+#define mc2_chn_ddr_odt_odt_csoddodten_BITS                        1
+#define mc2_chn_ddr_odt_odt_csoddodten_SHIFT                       8
+#define mc2_chn_ddr_odt_odt_csoddodten_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs1_MASK                        0x00000080
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs1_ALIGN                       0
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs1_BITS                        1
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs1_SHIFT                       7
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs1_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs0_MASK                        0x00000040
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs0_ALIGN                       0
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs0_BITS                        1
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs0_SHIFT                       6
+#define mc2_chn_ddr_odt_cs1_odt_wr_cs0_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs1_MASK                        0x00000020
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs1_ALIGN                       0
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs1_BITS                        1
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs1_SHIFT                       5
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs1_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs0_MASK                        0x00000010
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs0_ALIGN                       0
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs0_BITS                        1
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs0_SHIFT                       4
+#define mc2_chn_ddr_odt_cs1_odt_rd_cs0_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs1_MASK                        0x00000008
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs1_ALIGN                       0
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs1_BITS                        1
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs1_SHIFT                       3
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs1_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs0_MASK                        0x00000004
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs0_ALIGN                       0
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs0_BITS                        1
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs0_SHIFT                       2
+#define mc2_chn_ddr_odt_cs0_odt_wr_cs0_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs1_MASK                        0x00000002
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs1_ALIGN                       0
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs1_BITS                        1
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs1_SHIFT                       1
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs1_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs0_MASK                        0x00000001
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs0_ALIGN                       0
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs0_BITS                        1
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs0_SHIFT                       0
+#define mc2_chn_ddr_odt_cs0_odt_rd_cs0_DEFAULT                     0x00000000
+
+
+
+
+#define mc2_chn_ddr_ddr_param_cmd0_tAL_MASK                        0xff000000
+#define mc2_chn_ddr_ddr_param_cmd0_tAL_ALIGN                       0
+#define mc2_chn_ddr_ddr_param_cmd0_tAL_BITS                        8
+#define mc2_chn_ddr_ddr_param_cmd0_tAL_SHIFT                       24
+#define mc2_chn_ddr_ddr_param_cmd0_tAL_DEFAULT                     0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_cmd0_tRCD_MASK                       0x00ff0000
+#define mc2_chn_ddr_ddr_param_cmd0_tRCD_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_cmd0_tRCD_BITS                       8
+#define mc2_chn_ddr_ddr_param_cmd0_tRCD_SHIFT                      16
+#define mc2_chn_ddr_ddr_param_cmd0_tRCD_DEFAULT                    0x00000006
+
+
+#define mc2_chn_ddr_ddr_param_cmd0_tCWL_MASK                       0x0000ff00
+#define mc2_chn_ddr_ddr_param_cmd0_tCWL_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_cmd0_tCWL_BITS                       8
+#define mc2_chn_ddr_ddr_param_cmd0_tCWL_SHIFT                      8
+#define mc2_chn_ddr_ddr_param_cmd0_tCWL_DEFAULT                    0x00000004
+
+
+#define mc2_chn_ddr_ddr_param_cmd0_tCL_MASK                        0x000000ff
+#define mc2_chn_ddr_ddr_param_cmd0_tCL_ALIGN                       0
+#define mc2_chn_ddr_ddr_param_cmd0_tCL_BITS                        8
+#define mc2_chn_ddr_ddr_param_cmd0_tCL_SHIFT                       0
+#define mc2_chn_ddr_ddr_param_cmd0_tCL_DEFAULT                     0x00000005
+
+
+
+
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_L_MASK                     0xff000000
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_L_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_L_BITS                     8
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_L_SHIFT                    24
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_L_DEFAULT                  0x00000008
+
+
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_S_MASK                     0x00ff0000
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_S_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_S_BITS                     8
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_S_SHIFT                    16
+#define mc2_chn_ddr_ddr_param_cmd1_tCCD_S_DEFAULT                  0x00000008
+
+
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_L_MASK                     0x0000ff00
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_L_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_L_BITS                     8
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_L_SHIFT                    8
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_L_DEFAULT                  0x00000004
+
+
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_S_MASK                     0x000000ff
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_S_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_S_BITS                     8
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_S_SHIFT                    0
+#define mc2_chn_ddr_ddr_param_cmd1_tRRD_S_DEFAULT                  0x00000004
+
+
+
+
+#define mc2_chn_ddr_ddr_param_cmd2_reserved0_MASK                  0xffffff00
+#define mc2_chn_ddr_ddr_param_cmd2_reserved0_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_cmd2_reserved0_BITS                  24
+#define mc2_chn_ddr_ddr_param_cmd2_reserved0_SHIFT                 8
+
+
+#define mc2_chn_ddr_ddr_param_cmd2_tCCDMW_MASK                     0x000000ff
+#define mc2_chn_ddr_ddr_param_cmd2_tCCDMW_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_cmd2_tCCDMW_BITS                     8
+#define mc2_chn_ddr_ddr_param_cmd2_tCCDMW_SHIFT                    0
+#define mc2_chn_ddr_ddr_param_cmd2_tCCDMW_DEFAULT                  0x00000020
+
+
+
+
+#define mc2_chn_ddr_ddr_param_cmd3_tFAW_MASK                       0xff000000
+#define mc2_chn_ddr_ddr_param_cmd3_tFAW_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_cmd3_tFAW_BITS                       8
+#define mc2_chn_ddr_ddr_param_cmd3_tFAW_SHIFT                      24
+#define mc2_chn_ddr_ddr_param_cmd3_tFAW_DEFAULT                    0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_cmd3_tRPpb_MASK                      0x00ff0000
+#define mc2_chn_ddr_ddr_param_cmd3_tRPpb_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_cmd3_tRPpb_BITS                      8
+#define mc2_chn_ddr_ddr_param_cmd3_tRPpb_SHIFT                     16
+#define mc2_chn_ddr_ddr_param_cmd3_tRPpb_DEFAULT                   0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_cmd3_tRPab_MASK                      0x0000ff00
+#define mc2_chn_ddr_ddr_param_cmd3_tRPab_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_cmd3_tRPab_BITS                      8
+#define mc2_chn_ddr_ddr_param_cmd3_tRPab_SHIFT                     8
+#define mc2_chn_ddr_ddr_param_cmd3_tRPab_DEFAULT                   0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_cmd3_tRAS_MASK                       0x000000ff
+#define mc2_chn_ddr_ddr_param_cmd3_tRAS_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_cmd3_tRAS_BITS                       8
+#define mc2_chn_ddr_ddr_param_cmd3_tRAS_SHIFT                      0
+#define mc2_chn_ddr_ddr_param_cmd3_tRAS_DEFAULT                    0x00000011
+
+
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_L_MASK                     0xff000000
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_L_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_L_BITS                     8
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_L_SHIFT                    24
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_L_DEFAULT                  0x00000002
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_S_MASK                     0x00ff0000
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_S_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_S_BITS                     8
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_S_SHIFT                    16
+#define mc2_chn_ddr_ddr_param_dat0_tWTR_S_DEFAULT                  0x00000002
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tWR_MASK                        0x0000ff00
+#define mc2_chn_ddr_ddr_param_dat0_tWR_ALIGN                       0
+#define mc2_chn_ddr_ddr_param_dat0_tWR_BITS                        8
+#define mc2_chn_ddr_ddr_param_dat0_tWR_SHIFT                       8
+#define mc2_chn_ddr_ddr_param_dat0_tWR_DEFAULT                     0x00000020
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tDQSCK_MASK                     0x000000f0
+#define mc2_chn_ddr_ddr_param_dat0_tDQSCK_ALIGN                    0
+#define mc2_chn_ddr_ddr_param_dat0_tDQSCK_BITS                     4
+#define mc2_chn_ddr_ddr_param_dat0_tDQSCK_SHIFT                    4
+#define mc2_chn_ddr_ddr_param_dat0_tDQSCK_DEFAULT                  0x00000007
+
+
+#define mc2_chn_ddr_ddr_param_dat0_reserved0_MASK                  0x0000000c
+#define mc2_chn_ddr_ddr_param_dat0_reserved0_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_dat0_reserved0_BITS                  2
+#define mc2_chn_ddr_ddr_param_dat0_reserved0_SHIFT                 2
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tWPST_MASK                      0x00000002
+#define mc2_chn_ddr_ddr_param_dat0_tWPST_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_dat0_tWPST_BITS                      1
+#define mc2_chn_ddr_ddr_param_dat0_tWPST_SHIFT                     1
+#define mc2_chn_ddr_ddr_param_dat0_tWPST_DEFAULT                   0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_dat0_tWPRE_MASK                      0x00000001
+#define mc2_chn_ddr_ddr_param_dat0_tWPRE_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_dat0_tWPRE_BITS                      1
+#define mc2_chn_ddr_ddr_param_dat0_tWPRE_SHIFT                     0
+#define mc2_chn_ddr_ddr_param_dat0_tWPRE_DEFAULT                   0x00000000
+
+
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tRPST_MASK                      0x80000000
+#define mc2_chn_ddr_ddr_param_dat1_tRPST_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_dat1_tRPST_BITS                      1
+#define mc2_chn_ddr_ddr_param_dat1_tRPST_SHIFT                     31
+#define mc2_chn_ddr_ddr_param_dat1_tRPST_DEFAULT                   0x00000001
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tRPRE_MASK                      0x40000000
+#define mc2_chn_ddr_ddr_param_dat1_tRPRE_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_dat1_tRPRE_BITS                      1
+#define mc2_chn_ddr_ddr_param_dat1_tRPRE_SHIFT                     30
+#define mc2_chn_ddr_ddr_param_dat1_tRPRE_DEFAULT                   0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_dat1_reserved0_MASK                  0x3f000000
+#define mc2_chn_ddr_ddr_param_dat1_reserved0_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_dat1_reserved0_BITS                  6
+#define mc2_chn_ddr_ddr_param_dat1_reserved0_SHIFT                 24
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tW2R_MASK                       0x00ff0000
+#define mc2_chn_ddr_ddr_param_dat1_tW2R_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_dat1_tW2R_BITS                       8
+#define mc2_chn_ddr_ddr_param_dat1_tW2R_SHIFT                      16
+#define mc2_chn_ddr_ddr_param_dat1_tW2R_DEFAULT                    0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tR2R_MASK                       0x0000f000
+#define mc2_chn_ddr_ddr_param_dat1_tR2R_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_dat1_tR2R_BITS                       4
+#define mc2_chn_ddr_ddr_param_dat1_tR2R_SHIFT                      12
+#define mc2_chn_ddr_ddr_param_dat1_tR2R_DEFAULT                    0x00000003
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tW2W_MASK                       0x00000f00
+#define mc2_chn_ddr_ddr_param_dat1_tW2W_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_dat1_tW2W_BITS                       4
+#define mc2_chn_ddr_ddr_param_dat1_tW2W_SHIFT                      8
+#define mc2_chn_ddr_ddr_param_dat1_tW2W_DEFAULT                    0x00000008
+
+
+#define mc2_chn_ddr_ddr_param_dat1_tR2W_MASK                       0x000000f0
+#define mc2_chn_ddr_ddr_param_dat1_tR2W_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_dat1_tR2W_BITS                       4
+#define mc2_chn_ddr_ddr_param_dat1_tR2W_SHIFT                      4
+#define mc2_chn_ddr_ddr_param_dat1_tR2W_DEFAULT                    0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_dat1_reserved1_MASK                  0x0000000f
+#define mc2_chn_ddr_ddr_param_dat1_reserved1_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_dat1_reserved1_BITS                  4
+#define mc2_chn_ddr_ddr_param_dat1_reserved1_SHIFT                 0
+
+
+
+
+#define mc2_chn_ddr_ddr_param_pre0_autoprecharge_MASK              0x80000000
+#define mc2_chn_ddr_ddr_param_pre0_autoprecharge_ALIGN             0
+#define mc2_chn_ddr_ddr_param_pre0_autoprecharge_BITS              1
+#define mc2_chn_ddr_ddr_param_pre0_autoprecharge_SHIFT             31
+#define mc2_chn_ddr_ddr_param_pre0_autoprecharge_DEFAULT           0x00000000
+
+
+#define mc2_chn_ddr_ddr_param_pre0_reserved0_MASK                  0x7fff0000
+#define mc2_chn_ddr_ddr_param_pre0_reserved0_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_pre0_reserved0_BITS                  15
+#define mc2_chn_ddr_ddr_param_pre0_reserved0_SHIFT                 16
+
+
+#define mc2_chn_ddr_ddr_param_pre0_tPPD_MASK                       0x0000ff00
+#define mc2_chn_ddr_ddr_param_pre0_tPPD_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_pre0_tPPD_BITS                       8
+#define mc2_chn_ddr_ddr_param_pre0_tPPD_SHIFT                      8
+#define mc2_chn_ddr_ddr_param_pre0_tPPD_DEFAULT                    0x00000002
+
+
+#define mc2_chn_ddr_ddr_param_pre0_tRTP_MASK                       0x000000ff
+#define mc2_chn_ddr_ddr_param_pre0_tRTP_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_pre0_tRTP_BITS                       8
+#define mc2_chn_ddr_ddr_param_pre0_tRTP_SHIFT                      0
+#define mc2_chn_ddr_ddr_param_pre0_tRTP_DEFAULT                    0x00000002
+
+
+
+
+#define mc2_chn_ddr_ddr_param_pwr0_tXP_MASK                        0xfff00000
+#define mc2_chn_ddr_ddr_param_pwr0_tXP_ALIGN                       0
+#define mc2_chn_ddr_ddr_param_pwr0_tXP_BITS                        12
+#define mc2_chn_ddr_ddr_param_pwr0_tXP_SHIFT                       20
+#define mc2_chn_ddr_ddr_param_pwr0_tXP_DEFAULT                     0x00000003
+
+
+#define mc2_chn_ddr_ddr_param_pwr0_tXSR_MASK                       0x000fff00
+#define mc2_chn_ddr_ddr_param_pwr0_tXSR_ALIGN                      0
+#define mc2_chn_ddr_ddr_param_pwr0_tXSR_BITS                       12
+#define mc2_chn_ddr_ddr_param_pwr0_tXSR_SHIFT                      8
+#define mc2_chn_ddr_ddr_param_pwr0_tXSR_DEFAULT                    0x00000002
+
+
+#define mc2_chn_ddr_ddr_param_pwr0_tSR_MASK                        0x000000ff
+#define mc2_chn_ddr_ddr_param_pwr0_tSR_ALIGN                       0
+#define mc2_chn_ddr_ddr_param_pwr0_tSR_BITS                        8
+#define mc2_chn_ddr_ddr_param_pwr0_tSR_SHIFT                       0
+#define mc2_chn_ddr_ddr_param_pwr0_tSR_DEFAULT                     0x00000003
+
+
+
+
+#define mc2_chn_ddr_ddr_param_zqc0_reserved0_MASK                  0xf0000000
+#define mc2_chn_ddr_ddr_param_zqc0_reserved0_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_zqc0_reserved0_BITS                  4
+#define mc2_chn_ddr_ddr_param_zqc0_reserved0_SHIFT                 28
+
+
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCL_MASK                      0x0fff0000
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCL_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCL_BITS                      12
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCL_SHIFT                     16
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCL_DEFAULT                   0x00000100
+
+
+#define mc2_chn_ddr_ddr_param_zqc0_reserved1_MASK                  0x0000fe00
+#define mc2_chn_ddr_ddr_param_zqc0_reserved1_ALIGN                 0
+#define mc2_chn_ddr_ddr_param_zqc0_reserved1_BITS                  7
+#define mc2_chn_ddr_ddr_param_zqc0_reserved1_SHIFT                 9
+
+
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCS_MASK                      0x000001ff
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCS_ALIGN                     0
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCS_BITS                      9
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCS_SHIFT                     0
+#define mc2_chn_ddr_ddr_param_zqc0_tZQCS_DEFAULT                   0x00000040
+
+
+
+
+#define mc2_chn_ddr_refresh_aref0_refmaxdelay_MASK                 0xf0000000
+#define mc2_chn_ddr_refresh_aref0_refmaxdelay_ALIGN                0
+#define mc2_chn_ddr_refresh_aref0_refmaxdelay_BITS                 4
+#define mc2_chn_ddr_refresh_aref0_refmaxdelay_SHIFT                28
+#define mc2_chn_ddr_refresh_aref0_refmaxdelay_DEFAULT              0x00000004
+
+
+#define mc2_chn_ddr_refresh_aref0_reserved0_MASK                   0x0e000000
+#define mc2_chn_ddr_refresh_aref0_reserved0_ALIGN                  0
+#define mc2_chn_ddr_refresh_aref0_reserved0_BITS                   3
+#define mc2_chn_ddr_refresh_aref0_reserved0_SHIFT                  25
+
+
+#define mc2_chn_ddr_refresh_aref0_pbref_ordered_MASK               0x01000000
+#define mc2_chn_ddr_refresh_aref0_pbref_ordered_ALIGN              0
+#define mc2_chn_ddr_refresh_aref0_pbref_ordered_BITS               1
+#define mc2_chn_ddr_refresh_aref0_pbref_ordered_SHIFT              24
+#define mc2_chn_ddr_refresh_aref0_pbref_ordered_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_refresh_aref0_pbref_intlv_MASK                 0x00ff0000
+#define mc2_chn_ddr_refresh_aref0_pbref_intlv_ALIGN                0
+#define mc2_chn_ddr_refresh_aref0_pbref_intlv_BITS                 8
+#define mc2_chn_ddr_refresh_aref0_pbref_intlv_SHIFT                16
+#define mc2_chn_ddr_refresh_aref0_pbref_intlv_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_refresh_aref0_abref_num_MASK                   0x0000f000
+#define mc2_chn_ddr_refresh_aref0_abref_num_ALIGN                  0
+#define mc2_chn_ddr_refresh_aref0_abref_num_BITS                   4
+#define mc2_chn_ddr_refresh_aref0_abref_num_SHIFT                  12
+#define mc2_chn_ddr_refresh_aref0_abref_num_DEFAULT                0x00000001
+
+
+#define mc2_chn_ddr_refresh_aref0_reserved1_MASK                   0x00000c00
+#define mc2_chn_ddr_refresh_aref0_reserved1_ALIGN                  0
+#define mc2_chn_ddr_refresh_aref0_reserved1_BITS                   2
+#define mc2_chn_ddr_refresh_aref0_reserved1_SHIFT                  10
+
+
+#define mc2_chn_ddr_refresh_aref0_tREFI_MASK                       0x000003ff
+#define mc2_chn_ddr_refresh_aref0_tREFI_ALIGN                      0
+#define mc2_chn_ddr_refresh_aref0_tREFI_BITS                       10
+#define mc2_chn_ddr_refresh_aref0_tREFI_SHIFT                      0
+#define mc2_chn_ddr_refresh_aref0_tREFI_DEFAULT                    0x00000103
+
+
+
+
+#define mc2_chn_ddr_refresh_aref1_refdisable_MASK                  0x80000000
+#define mc2_chn_ddr_refresh_aref1_refdisable_ALIGN                 0
+#define mc2_chn_ddr_refresh_aref1_refdisable_BITS                  1
+#define mc2_chn_ddr_refresh_aref1_refdisable_SHIFT                 31
+#define mc2_chn_ddr_refresh_aref1_refdisable_DEFAULT               0x00000000
+
+
+#define mc2_chn_ddr_refresh_aref1_reserved0_MASK                   0x70000000
+#define mc2_chn_ddr_refresh_aref1_reserved0_ALIGN                  0
+#define mc2_chn_ddr_refresh_aref1_reserved0_BITS                   3
+#define mc2_chn_ddr_refresh_aref1_reserved0_SHIFT                  28
+
+
+#define mc2_chn_ddr_refresh_aref1_tRFCpb_MASK                      0x0fff0000
+#define mc2_chn_ddr_refresh_aref1_tRFCpb_ALIGN                     0
+#define mc2_chn_ddr_refresh_aref1_tRFCpb_BITS                      12
+#define mc2_chn_ddr_refresh_aref1_tRFCpb_SHIFT                     16
+#define mc2_chn_ddr_refresh_aref1_tRFCpb_DEFAULT                   0x0000008d
+
+
+#define mc2_chn_ddr_refresh_aref1_reserved1_MASK                   0x0000f000
+#define mc2_chn_ddr_refresh_aref1_reserved1_ALIGN                  0
+#define mc2_chn_ddr_refresh_aref1_reserved1_BITS                   4
+#define mc2_chn_ddr_refresh_aref1_reserved1_SHIFT                  12
+
+
+#define mc2_chn_ddr_refresh_aref1_tRFCab_MASK                      0x00000fff
+#define mc2_chn_ddr_refresh_aref1_tRFCab_ALIGN                     0
+#define mc2_chn_ddr_refresh_aref1_tRFCab_BITS                      12
+#define mc2_chn_ddr_refresh_aref1_tRFCab_SHIFT                     0
+#define mc2_chn_ddr_refresh_aref1_tRFCab_DEFAULT                   0x0000011a
+
+
+
+
+#define mc2_chn_ddr_auto_self_refresh_enable_MASK                  0x80000000
+#define mc2_chn_ddr_auto_self_refresh_enable_ALIGN                 0
+#define mc2_chn_ddr_auto_self_refresh_enable_BITS                  1
+#define mc2_chn_ddr_auto_self_refresh_enable_SHIFT                 31
+#define mc2_chn_ddr_auto_self_refresh_enable_DEFAULT               0x00000000
+
+
+#define mc2_chn_ddr_auto_self_refresh_immediate_MASK               0x40000000
+#define mc2_chn_ddr_auto_self_refresh_immediate_ALIGN              0
+#define mc2_chn_ddr_auto_self_refresh_immediate_BITS               1
+#define mc2_chn_ddr_auto_self_refresh_immediate_SHIFT              30
+#define mc2_chn_ddr_auto_self_refresh_immediate_DEFAULT            0x00000000
+
+
+#define mc2_chn_ddr_auto_self_refresh_idle_count_MASK              0x3fffffff
+#define mc2_chn_ddr_auto_self_refresh_idle_count_ALIGN             0
+#define mc2_chn_ddr_auto_self_refresh_idle_count_BITS              30
+#define mc2_chn_ddr_auto_self_refresh_idle_count_SHIFT             0
+#define mc2_chn_ddr_auto_self_refresh_idle_count_DEFAULT           0x00000000
+
+
+
+
+#define mc2_chn_ddr_auto_zqcs_enable_MASK                          0x80000000
+#define mc2_chn_ddr_auto_zqcs_enable_ALIGN                         0
+#define mc2_chn_ddr_auto_zqcs_enable_BITS                          1
+#define mc2_chn_ddr_auto_zqcs_enable_SHIFT                         31
+#define mc2_chn_ddr_auto_zqcs_enable_DEFAULT                       0x00000000
+
+
+#define mc2_chn_ddr_auto_zqcs_timer_count_MASK                     0x7fffffe0
+#define mc2_chn_ddr_auto_zqcs_timer_count_ALIGN                    0
+#define mc2_chn_ddr_auto_zqcs_timer_count_BITS                     26
+#define mc2_chn_ddr_auto_zqcs_timer_count_SHIFT                    5
+#define mc2_chn_ddr_auto_zqcs_timer_count_DEFAULT                  0x00000000
+
+
+#define mc2_chn_ddr_auto_zqcs_reserved0_MASK                       0x0000001f
+#define mc2_chn_ddr_auto_zqcs_reserved0_ALIGN                      0
+#define mc2_chn_ddr_auto_zqcs_reserved0_BITS                       5
+#define mc2_chn_ddr_auto_zqcs_reserved0_SHIFT                      0
+
+
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_b_vld_MASK                 0x80000000
+#define mc2_chn_ddr_dfi_error_dfi_error_b_vld_ALIGN                0
+#define mc2_chn_ddr_dfi_error_dfi_error_b_vld_BITS                 1
+#define mc2_chn_ddr_dfi_error_dfi_error_b_vld_SHIFT                31
+#define mc2_chn_ddr_dfi_error_dfi_error_b_vld_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_b_clr_MASK                 0x40000000
+#define mc2_chn_ddr_dfi_error_dfi_error_b_clr_ALIGN                0
+#define mc2_chn_ddr_dfi_error_dfi_error_b_clr_BITS                 1
+#define mc2_chn_ddr_dfi_error_dfi_error_b_clr_SHIFT                30
+#define mc2_chn_ddr_dfi_error_dfi_error_b_clr_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_dfi_error_reserved0_MASK                       0x3f000000
+#define mc2_chn_ddr_dfi_error_reserved0_ALIGN                      0
+#define mc2_chn_ddr_dfi_error_reserved0_BITS                       6
+#define mc2_chn_ddr_dfi_error_reserved0_SHIFT                      24
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_b_info_MASK                0x00ff0000
+#define mc2_chn_ddr_dfi_error_dfi_error_b_info_ALIGN               0
+#define mc2_chn_ddr_dfi_error_dfi_error_b_info_BITS                8
+#define mc2_chn_ddr_dfi_error_dfi_error_b_info_SHIFT               16
+#define mc2_chn_ddr_dfi_error_dfi_error_b_info_DEFAULT             0x00000000
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_a_vld_MASK                 0x00008000
+#define mc2_chn_ddr_dfi_error_dfi_error_a_vld_ALIGN                0
+#define mc2_chn_ddr_dfi_error_dfi_error_a_vld_BITS                 1
+#define mc2_chn_ddr_dfi_error_dfi_error_a_vld_SHIFT                15
+#define mc2_chn_ddr_dfi_error_dfi_error_a_vld_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_a_clr_MASK                 0x00004000
+#define mc2_chn_ddr_dfi_error_dfi_error_a_clr_ALIGN                0
+#define mc2_chn_ddr_dfi_error_dfi_error_a_clr_BITS                 1
+#define mc2_chn_ddr_dfi_error_dfi_error_a_clr_SHIFT                14
+#define mc2_chn_ddr_dfi_error_dfi_error_a_clr_DEFAULT              0x00000000
+
+
+#define mc2_chn_ddr_dfi_error_reserved1_MASK                       0x00003f00
+#define mc2_chn_ddr_dfi_error_reserved1_ALIGN                      0
+#define mc2_chn_ddr_dfi_error_reserved1_BITS                       6
+#define mc2_chn_ddr_dfi_error_reserved1_SHIFT                      8
+
+
+#define mc2_chn_ddr_dfi_error_dfi_error_a_info_MASK                0x000000ff
+#define mc2_chn_ddr_dfi_error_dfi_error_a_info_ALIGN               0
+#define mc2_chn_ddr_dfi_error_dfi_error_a_info_BITS                8
+#define mc2_chn_ddr_dfi_error_dfi_error_a_info_SHIFT               0
+#define mc2_chn_ddr_dfi_error_dfi_error_a_info_DEFAULT             0x00000000
+
+
+#define mc2_afx_acc_acc_eack_MASK                                  0x80000000
+#define mc2_afx_acc_acc_eack_ALIGN                                 0
+#define mc2_afx_acc_acc_eack_BITS                                  1
+#define mc2_afx_acc_acc_eack_SHIFT                                 31
+#define mc2_afx_acc_acc_eack_DEFAULT                               0x00000000
+
+
+#define mc2_afx_acc_reserved0_MASK                                 0x7fffff00
+#define mc2_afx_acc_reserved0_ALIGN                                0
+#define mc2_afx_acc_reserved0_BITS                                 23
+#define mc2_afx_acc_reserved0_SHIFT                                8
+
+
+#define mc2_afx_acc_acc_sw_MASK                                    0x00000080
+#define mc2_afx_acc_acc_sw_ALIGN                                   0
+#define mc2_afx_acc_acc_sw_BITS                                    1
+#define mc2_afx_acc_acc_sw_SHIFT                                   7
+#define mc2_afx_acc_acc_sw_DEFAULT                                 0x00000001
+
+
+#define mc2_afx_acc_acc_sr_MASK                                    0x00000040
+#define mc2_afx_acc_acc_sr_ALIGN                                   0
+#define mc2_afx_acc_acc_sr_BITS                                    1
+#define mc2_afx_acc_acc_sr_SHIFT                                   6
+#define mc2_afx_acc_acc_sr_DEFAULT                                 0x00000001
+
+
+#define mc2_afx_acc_acc_nsw_MASK                                   0x00000020
+#define mc2_afx_acc_acc_nsw_ALIGN                                  0
+#define mc2_afx_acc_acc_nsw_BITS                                   1
+#define mc2_afx_acc_acc_nsw_SHIFT                                  5
+#define mc2_afx_acc_acc_nsw_DEFAULT                                0x00000001
+
+
+#define mc2_afx_acc_acc_nsr_MASK                                   0x00000010
+#define mc2_afx_acc_acc_nsr_ALIGN                                  0
+#define mc2_afx_acc_acc_nsr_BITS                                   1
+#define mc2_afx_acc_acc_nsr_SHIFT                                  4
+#define mc2_afx_acc_acc_nsr_DEFAULT                                0x00000001
+
+
+#define mc2_afx_acc_perm_sw_MASK                                   0x00000008
+#define mc2_afx_acc_perm_sw_ALIGN                                  0
+#define mc2_afx_acc_perm_sw_BITS                                   1
+#define mc2_afx_acc_perm_sw_SHIFT                                  3
+#define mc2_afx_acc_perm_sw_DEFAULT                                0x00000001
+
+
+#define mc2_afx_acc_perm_sr_MASK                                   0x00000004
+#define mc2_afx_acc_perm_sr_ALIGN                                  0
+#define mc2_afx_acc_perm_sr_BITS                                   1
+#define mc2_afx_acc_perm_sr_SHIFT                                  2
+#define mc2_afx_acc_perm_sr_DEFAULT                                0x00000001
+
+
+#define mc2_afx_acc_perm_nsw_MASK                                  0x00000002
+#define mc2_afx_acc_perm_nsw_ALIGN                                 0
+#define mc2_afx_acc_perm_nsw_BITS                                  1
+#define mc2_afx_acc_perm_nsw_SHIFT                                 1
+#define mc2_afx_acc_perm_nsw_DEFAULT                               0x00000001
+
+
+#define mc2_afx_acc_perm_nsr_MASK                                  0x00000001
+#define mc2_afx_acc_perm_nsr_ALIGN                                 0
+#define mc2_afx_acc_perm_nsr_BITS                                  1
+#define mc2_afx_acc_perm_nsr_SHIFT                                 0
+#define mc2_afx_acc_perm_nsr_DEFAULT                               0x00000001
+
+
+
+
+#define mc2_afx_ver_reserved0_MASK                                 0xffffff00
+#define mc2_afx_ver_reserved0_ALIGN                                0
+#define mc2_afx_ver_reserved0_BITS                                 24
+#define mc2_afx_ver_reserved0_SHIFT                                8
+
+
+#define mc2_afx_ver_version_MASK                                   0x000000ff
+#define mc2_afx_ver_version_ALIGN                                  0
+#define mc2_afx_ver_version_BITS                                   8
+#define mc2_afx_ver_version_SHIFT                                  0
+#define mc2_afx_ver_version_DEFAULT                                0x00000000
+
+
+
+
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_enable_MASK      0x80000000
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_enable_ALIGN     0
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_enable_BITS      1
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_enable_SHIFT     31
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_enable_DEFAULT   0x00000001
+
+
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_reserved0_MASK   0x7fffff00
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_reserved0_ALIGN  0
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_reserved0_BITS   23
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_reserved0_SHIFT  8
+
+
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_addr_hi_MASK     0x000000ff
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_addr_hi_ALIGN    0
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_addr_hi_BITS     8
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_addr_hi_SHIFT    0
+#define mc2_afx_sram_match_cfg_sram_start_addr_hi_addr_hi_DEFAULT  0x00000001
+
+
+
+
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo_addr_lo_MASK     0xffffffff
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo_addr_lo_ALIGN    0
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo_addr_lo_BITS     32
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo_addr_lo_SHIFT    0
+#define mc2_afx_sram_match_cfg_sram_start_addr_lo_addr_lo_DEFAULT  0x7fff0000
+
+
+
+
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_reserved0_MASK     0xffffff00
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_reserved0_ALIGN    0
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_reserved0_BITS     24
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_reserved0_SHIFT    8
+
+
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_addr_hi_MASK       0x000000ff
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_addr_hi_ALIGN      0
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_addr_hi_BITS       8
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_addr_hi_SHIFT      0
+#define mc2_afx_sram_match_cfg_sram_end_addr_hi_addr_hi_DEFAULT    0x00000001
+
+
+
+
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo_addr_lo_MASK       0xffffffff
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo_addr_lo_ALIGN      0
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo_addr_lo_BITS       32
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo_addr_lo_SHIFT      0
+#define mc2_afx_sram_match_cfg_sram_end_addr_lo_addr_lo_DEFAULT    0x7fffffff
+
+
+
+
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_enable_MASK           0x80000000
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_enable_ALIGN          0
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_enable_BITS           1
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_enable_SHIFT          31
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_enable_DEFAULT        0x00000000
+
+
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_reserved0_MASK        0x7fffff00
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_reserved0_ALIGN       0
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_reserved0_BITS        23
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_reserved0_SHIFT       8
+
+
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_addr_hi_MASK          0x000000ff
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_addr_hi_ALIGN         0
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_addr_hi_BITS          8
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_addr_hi_SHIFT         0
+#define mc2_afx_addr_fltr_cfg0_start_addr_hi_addr_hi_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo_addr_lo_MASK          0xffffffff
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo_addr_lo_ALIGN         0
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo_addr_lo_BITS          32
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo_addr_lo_SHIFT         0
+#define mc2_afx_addr_fltr_cfg0_start_addr_lo_addr_lo_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_reserved0_MASK          0xffffff00
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_reserved0_ALIGN         0
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_reserved0_BITS          24
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_reserved0_SHIFT         8
+
+
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_addr_hi_MASK            0x000000ff
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_addr_hi_ALIGN           0
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_addr_hi_BITS            8
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_addr_hi_SHIFT           0
+#define mc2_afx_addr_fltr_cfg0_end_addr_hi_addr_hi_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo_addr_lo_MASK            0xffffffff
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo_addr_lo_ALIGN           0
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo_addr_lo_BITS            32
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo_addr_lo_SHIFT           0
+#define mc2_afx_addr_fltr_cfg0_end_addr_lo_addr_lo_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_enable_MASK           0x80000000
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_enable_ALIGN          0
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_enable_BITS           1
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_enable_SHIFT          31
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_enable_DEFAULT        0x00000000
+
+
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_reserved0_MASK        0x7fffff00
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_reserved0_ALIGN       0
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_reserved0_BITS        23
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_reserved0_SHIFT       8
+
+
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_addr_hi_MASK          0x000000ff
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_addr_hi_ALIGN         0
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_addr_hi_BITS          8
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_addr_hi_SHIFT         0
+#define mc2_afx_addr_fltr_cfg1_start_addr_hi_addr_hi_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo_addr_lo_MASK          0xffffffff
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo_addr_lo_ALIGN         0
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo_addr_lo_BITS          32
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo_addr_lo_SHIFT         0
+#define mc2_afx_addr_fltr_cfg1_start_addr_lo_addr_lo_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_reserved0_MASK          0xffffff00
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_reserved0_ALIGN         0
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_reserved0_BITS          24
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_reserved0_SHIFT         8
+
+
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_addr_hi_MASK            0x000000ff
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_addr_hi_ALIGN           0
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_addr_hi_BITS            8
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_addr_hi_SHIFT           0
+#define mc2_afx_addr_fltr_cfg1_end_addr_hi_addr_hi_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo_addr_lo_MASK            0xffffffff
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo_addr_lo_ALIGN           0
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo_addr_lo_BITS            32
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo_addr_lo_SHIFT           0
+#define mc2_afx_addr_fltr_cfg1_end_addr_lo_addr_lo_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_enable_MASK           0x80000000
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_enable_ALIGN          0
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_enable_BITS           1
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_enable_SHIFT          31
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_enable_DEFAULT        0x00000000
+
+
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_reserved0_MASK        0x7fffff00
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_reserved0_ALIGN       0
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_reserved0_BITS        23
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_reserved0_SHIFT       8
+
+
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_addr_hi_MASK          0x000000ff
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_addr_hi_ALIGN         0
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_addr_hi_BITS          8
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_addr_hi_SHIFT         0
+#define mc2_afx_addr_fltr_cfg2_start_addr_hi_addr_hi_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo_addr_lo_MASK          0xffffffff
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo_addr_lo_ALIGN         0
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo_addr_lo_BITS          32
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo_addr_lo_SHIFT         0
+#define mc2_afx_addr_fltr_cfg2_start_addr_lo_addr_lo_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_reserved0_MASK          0xffffff00
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_reserved0_ALIGN         0
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_reserved0_BITS          24
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_reserved0_SHIFT         8
+
+
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_addr_hi_MASK            0x000000ff
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_addr_hi_ALIGN           0
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_addr_hi_BITS            8
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_addr_hi_SHIFT           0
+#define mc2_afx_addr_fltr_cfg2_end_addr_hi_addr_hi_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo_addr_lo_MASK            0xffffffff
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo_addr_lo_ALIGN           0
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo_addr_lo_BITS            32
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo_addr_lo_SHIFT           0
+#define mc2_afx_addr_fltr_cfg2_end_addr_lo_addr_lo_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_enable_MASK           0x80000000
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_enable_ALIGN          0
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_enable_BITS           1
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_enable_SHIFT          31
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_enable_DEFAULT        0x00000000
+
+
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_reserved0_MASK        0x7fffff00
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_reserved0_ALIGN       0
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_reserved0_BITS        23
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_reserved0_SHIFT       8
+
+
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_addr_hi_MASK          0x000000ff
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_addr_hi_ALIGN         0
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_addr_hi_BITS          8
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_addr_hi_SHIFT         0
+#define mc2_afx_addr_fltr_cfg3_start_addr_hi_addr_hi_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo_addr_lo_MASK          0xffffffff
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo_addr_lo_ALIGN         0
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo_addr_lo_BITS          32
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo_addr_lo_SHIFT         0
+#define mc2_afx_addr_fltr_cfg3_start_addr_lo_addr_lo_DEFAULT       0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_reserved0_MASK          0xffffff00
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_reserved0_ALIGN         0
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_reserved0_BITS          24
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_reserved0_SHIFT         8
+
+
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_addr_hi_MASK            0x000000ff
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_addr_hi_ALIGN           0
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_addr_hi_BITS            8
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_addr_hi_SHIFT           0
+#define mc2_afx_addr_fltr_cfg3_end_addr_hi_addr_hi_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo_addr_lo_MASK            0xffffffff
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo_addr_lo_ALIGN           0
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo_addr_lo_BITS            32
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo_addr_lo_SHIFT           0
+#define mc2_afx_addr_fltr_cfg3_end_addr_lo_addr_lo_DEFAULT         0x00000000
+
+
+
+
+#define mc2_afx_srcid_fltr_cfg0_srcid_enable_MASK                  0x80000000
+#define mc2_afx_srcid_fltr_cfg0_srcid_enable_ALIGN                 0
+#define mc2_afx_srcid_fltr_cfg0_srcid_enable_BITS                  1
+#define mc2_afx_srcid_fltr_cfg0_srcid_enable_SHIFT                 31
+#define mc2_afx_srcid_fltr_cfg0_srcid_enable_DEFAULT               0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved0_MASK               0x70000000
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved0_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved0_BITS               3
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved0_SHIFT              28
+
+
+#define mc2_afx_srcid_fltr_cfg0_srcid_start_srcid_MASK             0x0fff0000
+#define mc2_afx_srcid_fltr_cfg0_srcid_start_srcid_ALIGN            0
+#define mc2_afx_srcid_fltr_cfg0_srcid_start_srcid_BITS             12
+#define mc2_afx_srcid_fltr_cfg0_srcid_start_srcid_SHIFT            16
+#define mc2_afx_srcid_fltr_cfg0_srcid_start_srcid_DEFAULT          0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved1_MASK               0x0000f000
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved1_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved1_BITS               4
+#define mc2_afx_srcid_fltr_cfg0_srcid_reserved1_SHIFT              12
+
+
+#define mc2_afx_srcid_fltr_cfg0_srcid_end_srcid_MASK               0x00000fff
+#define mc2_afx_srcid_fltr_cfg0_srcid_end_srcid_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg0_srcid_end_srcid_BITS               12
+#define mc2_afx_srcid_fltr_cfg0_srcid_end_srcid_SHIFT              0
+#define mc2_afx_srcid_fltr_cfg0_srcid_end_srcid_DEFAULT            0x00000000
+
+
+
+
+#define mc2_afx_srcid_fltr_cfg1_srcid_enable_MASK                  0x80000000
+#define mc2_afx_srcid_fltr_cfg1_srcid_enable_ALIGN                 0
+#define mc2_afx_srcid_fltr_cfg1_srcid_enable_BITS                  1
+#define mc2_afx_srcid_fltr_cfg1_srcid_enable_SHIFT                 31
+#define mc2_afx_srcid_fltr_cfg1_srcid_enable_DEFAULT               0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved0_MASK               0x70000000
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved0_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved0_BITS               3
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved0_SHIFT              28
+
+
+#define mc2_afx_srcid_fltr_cfg1_srcid_start_srcid_MASK             0x0fff0000
+#define mc2_afx_srcid_fltr_cfg1_srcid_start_srcid_ALIGN            0
+#define mc2_afx_srcid_fltr_cfg1_srcid_start_srcid_BITS             12
+#define mc2_afx_srcid_fltr_cfg1_srcid_start_srcid_SHIFT            16
+#define mc2_afx_srcid_fltr_cfg1_srcid_start_srcid_DEFAULT          0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved1_MASK               0x0000f000
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved1_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved1_BITS               4
+#define mc2_afx_srcid_fltr_cfg1_srcid_reserved1_SHIFT              12
+
+
+#define mc2_afx_srcid_fltr_cfg1_srcid_end_srcid_MASK               0x00000fff
+#define mc2_afx_srcid_fltr_cfg1_srcid_end_srcid_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg1_srcid_end_srcid_BITS               12
+#define mc2_afx_srcid_fltr_cfg1_srcid_end_srcid_SHIFT              0
+#define mc2_afx_srcid_fltr_cfg1_srcid_end_srcid_DEFAULT            0x00000000
+
+
+
+
+#define mc2_afx_srcid_fltr_cfg2_srcid_enable_MASK                  0x80000000
+#define mc2_afx_srcid_fltr_cfg2_srcid_enable_ALIGN                 0
+#define mc2_afx_srcid_fltr_cfg2_srcid_enable_BITS                  1
+#define mc2_afx_srcid_fltr_cfg2_srcid_enable_SHIFT                 31
+#define mc2_afx_srcid_fltr_cfg2_srcid_enable_DEFAULT               0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved0_MASK               0x70000000
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved0_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved0_BITS               3
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved0_SHIFT              28
+
+
+#define mc2_afx_srcid_fltr_cfg2_srcid_start_srcid_MASK             0x0fff0000
+#define mc2_afx_srcid_fltr_cfg2_srcid_start_srcid_ALIGN            0
+#define mc2_afx_srcid_fltr_cfg2_srcid_start_srcid_BITS             12
+#define mc2_afx_srcid_fltr_cfg2_srcid_start_srcid_SHIFT            16
+#define mc2_afx_srcid_fltr_cfg2_srcid_start_srcid_DEFAULT          0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved1_MASK               0x0000f000
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved1_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved1_BITS               4
+#define mc2_afx_srcid_fltr_cfg2_srcid_reserved1_SHIFT              12
+
+
+#define mc2_afx_srcid_fltr_cfg2_srcid_end_srcid_MASK               0x00000fff
+#define mc2_afx_srcid_fltr_cfg2_srcid_end_srcid_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg2_srcid_end_srcid_BITS               12
+#define mc2_afx_srcid_fltr_cfg2_srcid_end_srcid_SHIFT              0
+#define mc2_afx_srcid_fltr_cfg2_srcid_end_srcid_DEFAULT            0x00000000
+
+
+
+
+#define mc2_afx_srcid_fltr_cfg3_srcid_enable_MASK                  0x80000000
+#define mc2_afx_srcid_fltr_cfg3_srcid_enable_ALIGN                 0
+#define mc2_afx_srcid_fltr_cfg3_srcid_enable_BITS                  1
+#define mc2_afx_srcid_fltr_cfg3_srcid_enable_SHIFT                 31
+#define mc2_afx_srcid_fltr_cfg3_srcid_enable_DEFAULT               0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved0_MASK               0x70000000
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved0_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved0_BITS               3
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved0_SHIFT              28
+
+
+#define mc2_afx_srcid_fltr_cfg3_srcid_start_srcid_MASK             0x0fff0000
+#define mc2_afx_srcid_fltr_cfg3_srcid_start_srcid_ALIGN            0
+#define mc2_afx_srcid_fltr_cfg3_srcid_start_srcid_BITS             12
+#define mc2_afx_srcid_fltr_cfg3_srcid_start_srcid_SHIFT            16
+#define mc2_afx_srcid_fltr_cfg3_srcid_start_srcid_DEFAULT          0x00000000
+
+
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved1_MASK               0x0000f000
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved1_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved1_BITS               4
+#define mc2_afx_srcid_fltr_cfg3_srcid_reserved1_SHIFT              12
+
+
+#define mc2_afx_srcid_fltr_cfg3_srcid_end_srcid_MASK               0x00000fff
+#define mc2_afx_srcid_fltr_cfg3_srcid_end_srcid_ALIGN              0
+#define mc2_afx_srcid_fltr_cfg3_srcid_end_srcid_BITS               12
+#define mc2_afx_srcid_fltr_cfg3_srcid_end_srcid_SHIFT              0
+#define mc2_afx_srcid_fltr_cfg3_srcid_end_srcid_DEFAULT            0x00000000
+
+
+
+
+#define mc2_afx_row_xtr_cfg_row_19_16_reserved0_MASK               0xffffffc0
+#define mc2_afx_row_xtr_cfg_row_19_16_reserved0_ALIGN              0
+#define mc2_afx_row_xtr_cfg_row_19_16_reserved0_BITS               26
+#define mc2_afx_row_xtr_cfg_row_19_16_reserved0_SHIFT              6
+
+
+#define mc2_afx_row_xtr_cfg_row_19_16_bit_16_MASK                  0x0000003f
+#define mc2_afx_row_xtr_cfg_row_19_16_bit_16_ALIGN                 0
+#define mc2_afx_row_xtr_cfg_row_19_16_bit_16_BITS                  6
+#define mc2_afx_row_xtr_cfg_row_19_16_bit_16_SHIFT                 0
+#define mc2_afx_row_xtr_cfg_row_19_16_bit_16_DEFAULT               0x0000001e
+
+
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved0_MASK               0xc0000000
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved0_ALIGN              0
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved0_BITS               2
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved0_SHIFT              30
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_15_MASK                  0x3f000000
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_15_ALIGN                 0
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_15_BITS                  6
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_15_SHIFT                 24
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_15_DEFAULT               0x0000001d
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved1_MASK               0x00c00000
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved1_ALIGN              0
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved1_BITS               2
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved1_SHIFT              22
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_14_MASK                  0x003f0000
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_14_ALIGN                 0
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_14_BITS                  6
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_14_SHIFT                 16
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_14_DEFAULT               0x0000001c
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved2_MASK               0x0000c000
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved2_ALIGN              0
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved2_BITS               2
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved2_SHIFT              14
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_13_MASK                  0x00003f00
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_13_ALIGN                 0
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_13_BITS                  6
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_13_SHIFT                 8
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_13_DEFAULT               0x0000001b
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved3_MASK               0x000000c0
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved3_ALIGN              0
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved3_BITS               2
+#define mc2_afx_row_xtr_cfg_row_15_12_reserved3_SHIFT              6
+
+
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_12_MASK                  0x0000003f
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_12_ALIGN                 0
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_12_BITS                  6
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_12_SHIFT                 0
+#define mc2_afx_row_xtr_cfg_row_15_12_bit_12_DEFAULT               0x0000001a
+
+
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved0_MASK                0xc0000000
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved0_ALIGN               0
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved0_BITS                2
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved0_SHIFT               30
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_11_MASK                   0x3f000000
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_11_ALIGN                  0
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_11_BITS                   6
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_11_SHIFT                  24
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_11_DEFAULT                0x00000019
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved1_MASK                0x00c00000
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved1_ALIGN               0
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved1_BITS                2
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved1_SHIFT               22
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_10_MASK                   0x003f0000
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_10_ALIGN                  0
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_10_BITS                   6
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_10_SHIFT                  16
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_10_DEFAULT                0x00000018
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved2_MASK                0x0000c000
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved2_ALIGN               0
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved2_BITS                2
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved2_SHIFT               14
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_9_MASK                    0x00003f00
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_9_ALIGN                   0
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_9_BITS                    6
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_9_SHIFT                   8
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_9_DEFAULT                 0x00000017
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved3_MASK                0x000000c0
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved3_ALIGN               0
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved3_BITS                2
+#define mc2_afx_row_xtr_cfg_row_11_8_reserved3_SHIFT               6
+
+
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_8_MASK                    0x0000003f
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_8_ALIGN                   0
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_8_BITS                    6
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_8_SHIFT                   0
+#define mc2_afx_row_xtr_cfg_row_11_8_bit_8_DEFAULT                 0x00000016
+
+
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved0_MASK                 0xc0000000
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved0_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved0_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved0_SHIFT                30
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_7_MASK                     0x3f000000
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_7_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_7_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_7_SHIFT                    24
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_7_DEFAULT                  0x00000015
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved1_MASK                 0x00c00000
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved1_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved1_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved1_SHIFT                22
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_6_MASK                     0x003f0000
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_6_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_6_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_6_SHIFT                    16
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_6_DEFAULT                  0x00000014
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved2_MASK                 0x0000c000
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved2_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved2_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved2_SHIFT                14
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_5_MASK                     0x00003f00
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_5_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_5_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_5_SHIFT                    8
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_5_DEFAULT                  0x00000013
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved3_MASK                 0x000000c0
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved3_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved3_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_7_4_reserved3_SHIFT                6
+
+
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_4_MASK                     0x0000003f
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_4_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_4_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_4_SHIFT                    0
+#define mc2_afx_row_xtr_cfg_row_7_4_bit_4_DEFAULT                  0x00000012
+
+
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved0_MASK                 0xc0000000
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved0_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved0_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved0_SHIFT                30
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_3_MASK                     0x3f000000
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_3_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_3_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_3_SHIFT                    24
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_3_DEFAULT                  0x00000011
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved1_MASK                 0x00c00000
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved1_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved1_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved1_SHIFT                22
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_2_MASK                     0x003f0000
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_2_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_2_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_2_SHIFT                    16
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_2_DEFAULT                  0x00000010
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved2_MASK                 0x0000c000
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved2_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved2_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved2_SHIFT                14
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_1_MASK                     0x00003f00
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_1_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_1_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_1_SHIFT                    8
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_1_DEFAULT                  0x0000000f
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved3_MASK                 0x000000c0
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved3_ALIGN                0
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved3_BITS                 2
+#define mc2_afx_row_xtr_cfg_row_3_0_reserved3_SHIFT                6
+
+
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_0_MASK                     0x0000003f
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_0_ALIGN                    0
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_0_BITS                     6
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_0_SHIFT                    0
+#define mc2_afx_row_xtr_cfg_row_3_0_bit_0_DEFAULT                  0x0000000e
+
+
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved0_MASK                   0xc0000000
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved0_ALIGN                  0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved0_BITS                   2
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved0_SHIFT                  30
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_3_MASK                       0x3f000000
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_3_ALIGN                      0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_3_BITS                       6
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_3_SHIFT                      24
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_3_DEFAULT                    0x00000000
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved1_MASK                   0x00c00000
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved1_ALIGN                  0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved1_BITS                   2
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved1_SHIFT                  22
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_2_MASK                       0x003f0000
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_2_ALIGN                      0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_2_BITS                       6
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_2_SHIFT                      16
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_2_DEFAULT                    0x00000000
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved2_MASK                   0x0000c000
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved2_ALIGN                  0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved2_BITS                   2
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved2_SHIFT                  14
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_1_MASK                       0x00003f00
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_1_ALIGN                      0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_1_BITS                       6
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_1_SHIFT                      8
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_1_DEFAULT                    0x00000000
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved3_MASK                   0x000000c0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved3_ALIGN                  0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved3_BITS                   2
+#define mc2_afx_bg_xtr_cfg_bg_3_0_reserved3_SHIFT                  6
+
+
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_0_MASK                       0x0000003f
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_0_ALIGN                      0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_0_BITS                       6
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_0_SHIFT                      0
+#define mc2_afx_bg_xtr_cfg_bg_3_0_bit_0_DEFAULT                    0x00000000
+
+
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved0_MASK                   0xc0000000
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved0_ALIGN                  0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved0_BITS                   2
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved0_SHIFT                  30
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_3_MASK                       0x3f000000
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_3_ALIGN                      0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_3_BITS                       6
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_3_SHIFT                      24
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_3_DEFAULT                    0x00000000
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved1_MASK                   0x00c00000
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved1_ALIGN                  0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved1_BITS                   2
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved1_SHIFT                  22
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_2_MASK                       0x003f0000
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_2_ALIGN                      0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_2_BITS                       6
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_2_SHIFT                      16
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_2_DEFAULT                    0x0000000d
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved2_MASK                   0x0000c000
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved2_ALIGN                  0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved2_BITS                   2
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved2_SHIFT                  14
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_1_MASK                       0x00003f00
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_1_ALIGN                      0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_1_BITS                       6
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_1_SHIFT                      8
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_1_DEFAULT                    0x0000000c
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved3_MASK                   0x000000c0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved3_ALIGN                  0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved3_BITS                   2
+#define mc2_afx_bk_xtr_cfg_bk_3_0_reserved3_SHIFT                  6
+
+
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_0_MASK                       0x0000003f
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_0_ALIGN                      0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_0_BITS                       6
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_0_SHIFT                      0
+#define mc2_afx_bk_xtr_cfg_bk_3_0_bit_0_DEFAULT                    0x0000000b
+
+
+
+
+#define mc2_afx_col_xtr_cfg_col_cfg_reserved0_MASK                 0xffffffc0
+#define mc2_afx_col_xtr_cfg_col_cfg_reserved0_ALIGN                0
+#define mc2_afx_col_xtr_cfg_col_cfg_reserved0_BITS                 26
+#define mc2_afx_col_xtr_cfg_col_cfg_reserved0_SHIFT                6
+
+
+#define mc2_afx_col_xtr_cfg_col_cfg_col_bit_start_MASK             0x00000030
+#define mc2_afx_col_xtr_cfg_col_cfg_col_bit_start_ALIGN            0
+#define mc2_afx_col_xtr_cfg_col_cfg_col_bit_start_BITS             2
+#define mc2_afx_col_xtr_cfg_col_cfg_col_bit_start_SHIFT            4
+#define mc2_afx_col_xtr_cfg_col_cfg_col_bit_start_DEFAULT          0x00000001
+
+
+#define mc2_afx_col_xtr_cfg_col_cfg_col_mode_MASK                  0x0000000c
+#define mc2_afx_col_xtr_cfg_col_cfg_col_mode_ALIGN                 0
+#define mc2_afx_col_xtr_cfg_col_cfg_col_mode_BITS                  2
+#define mc2_afx_col_xtr_cfg_col_cfg_col_mode_SHIFT                 2
+#define mc2_afx_col_xtr_cfg_col_cfg_col_mode_DEFAULT               0x00000000
+
+
+#define mc2_afx_col_xtr_cfg_col_cfg_num_col_bits_MASK              0x00000003
+#define mc2_afx_col_xtr_cfg_col_cfg_num_col_bits_ALIGN             0
+#define mc2_afx_col_xtr_cfg_col_cfg_num_col_bits_BITS              2
+#define mc2_afx_col_xtr_cfg_col_cfg_num_col_bits_SHIFT             0
+#define mc2_afx_col_xtr_cfg_col_cfg_num_col_bits_DEFAULT           0x00000001
+
+
+
+
+#define mc2_afx_cs_xtr_cfg_cs_3_0_enable_MASK                      0x80000000
+#define mc2_afx_cs_xtr_cfg_cs_3_0_enable_ALIGN                     0
+#define mc2_afx_cs_xtr_cfg_cs_3_0_enable_BITS                      1
+#define mc2_afx_cs_xtr_cfg_cs_3_0_enable_SHIFT                     31
+#define mc2_afx_cs_xtr_cfg_cs_3_0_enable_DEFAULT                   0x00000000
+
+
+#define mc2_afx_cs_xtr_cfg_cs_3_0_reserved0_MASK                   0x7fffffc0
+#define mc2_afx_cs_xtr_cfg_cs_3_0_reserved0_ALIGN                  0
+#define mc2_afx_cs_xtr_cfg_cs_3_0_reserved0_BITS                   25
+#define mc2_afx_cs_xtr_cfg_cs_3_0_reserved0_SHIFT                  6
+
+
+#define mc2_afx_cs_xtr_cfg_cs_3_0_bit_0_MASK                       0x0000003f
+#define mc2_afx_cs_xtr_cfg_cs_3_0_bit_0_ALIGN                      0
+#define mc2_afx_cs_xtr_cfg_cs_3_0_bit_0_BITS                       6
+#define mc2_afx_cs_xtr_cfg_cs_3_0_bit_0_SHIFT                      0
+#define mc2_afx_cs_xtr_cfg_cs_3_0_bit_0_DEFAULT                    0x0000000b
+
+
+
+
+#define mc2_afx_chn_xtr_cfg_chn_bit_enable_MASK                    0x80000000
+#define mc2_afx_chn_xtr_cfg_chn_bit_enable_ALIGN                   0
+#define mc2_afx_chn_xtr_cfg_chn_bit_enable_BITS                    1
+#define mc2_afx_chn_xtr_cfg_chn_bit_enable_SHIFT                   31
+#define mc2_afx_chn_xtr_cfg_chn_bit_enable_DEFAULT                 0x00000001
+
+
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved0_MASK                 0x7ffffc00
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved0_ALIGN                0
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved0_BITS                 21
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved0_SHIFT                10
+
+
+#define mc2_afx_chn_xtr_cfg_chn_bit_chn_mode_MASK                  0x00000300
+#define mc2_afx_chn_xtr_cfg_chn_bit_chn_mode_ALIGN                 0
+#define mc2_afx_chn_xtr_cfg_chn_bit_chn_mode_BITS                  2
+#define mc2_afx_chn_xtr_cfg_chn_bit_chn_mode_SHIFT                 8
+#define mc2_afx_chn_xtr_cfg_chn_bit_chn_mode_DEFAULT               0x00000000
+
+
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved1_MASK                 0x000000c0
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved1_ALIGN                0
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved1_BITS                 2
+#define mc2_afx_chn_xtr_cfg_chn_bit_reserved1_SHIFT                6
+
+
+#define mc2_afx_chn_xtr_cfg_chn_bit_bit_0_MASK                     0x0000003f
+#define mc2_afx_chn_xtr_cfg_chn_bit_bit_0_ALIGN                    0
+#define mc2_afx_chn_xtr_cfg_chn_bit_bit_0_BITS                     6
+#define mc2_afx_chn_xtr_cfg_chn_bit_bit_0_SHIFT                    0
+#define mc2_afx_chn_xtr_cfg_chn_bit_bit_0_DEFAULT                  0x0000000a
+
+
+
+
+#define mc2_afx_ddr_sz_chk_reserved0_MASK                          0xffffff00
+#define mc2_afx_ddr_sz_chk_reserved0_ALIGN                         0
+#define mc2_afx_ddr_sz_chk_reserved0_BITS                          24
+#define mc2_afx_ddr_sz_chk_reserved0_SHIFT                         8
+
+
+#define mc2_afx_ddr_sz_chk_dram_size_limit_MASK                    0x000000f0
+#define mc2_afx_ddr_sz_chk_dram_size_limit_ALIGN                   0
+#define mc2_afx_ddr_sz_chk_dram_size_limit_BITS                    4
+#define mc2_afx_ddr_sz_chk_dram_size_limit_SHIFT                   4
+#define mc2_afx_ddr_sz_chk_dram_size_limit_DEFAULT                 0x0000000c
+
+
+#define mc2_afx_ddr_sz_chk_reserved1_MASK                          0x0000000f
+#define mc2_afx_ddr_sz_chk_reserved1_ALIGN                         0
+#define mc2_afx_ddr_sz_chk_reserved1_BITS                          4
+#define mc2_afx_ddr_sz_chk_reserved1_SHIFT                         0
+
+
+#define mc2_wbf_acc_acc_eack_MASK                                  0x80000000
+#define mc2_wbf_acc_acc_eack_ALIGN                                 0
+#define mc2_wbf_acc_acc_eack_BITS                                  1
+#define mc2_wbf_acc_acc_eack_SHIFT                                 31
+#define mc2_wbf_acc_acc_eack_DEFAULT                               0x00000000
+
+
+#define mc2_wbf_acc_reserved0_MASK                                 0x7fffff00
+#define mc2_wbf_acc_reserved0_ALIGN                                0
+#define mc2_wbf_acc_reserved0_BITS                                 23
+#define mc2_wbf_acc_reserved0_SHIFT                                8
+
+
+#define mc2_wbf_acc_acc_sw_MASK                                    0x00000080
+#define mc2_wbf_acc_acc_sw_ALIGN                                   0
+#define mc2_wbf_acc_acc_sw_BITS                                    1
+#define mc2_wbf_acc_acc_sw_SHIFT                                   7
+#define mc2_wbf_acc_acc_sw_DEFAULT                                 0x00000001
+
+
+#define mc2_wbf_acc_acc_sr_MASK                                    0x00000040
+#define mc2_wbf_acc_acc_sr_ALIGN                                   0
+#define mc2_wbf_acc_acc_sr_BITS                                    1
+#define mc2_wbf_acc_acc_sr_SHIFT                                   6
+#define mc2_wbf_acc_acc_sr_DEFAULT                                 0x00000001
+
+
+#define mc2_wbf_acc_acc_nsw_MASK                                   0x00000020
+#define mc2_wbf_acc_acc_nsw_ALIGN                                  0
+#define mc2_wbf_acc_acc_nsw_BITS                                   1
+#define mc2_wbf_acc_acc_nsw_SHIFT                                  5
+#define mc2_wbf_acc_acc_nsw_DEFAULT                                0x00000001
+
+
+#define mc2_wbf_acc_acc_nsr_MASK                                   0x00000010
+#define mc2_wbf_acc_acc_nsr_ALIGN                                  0
+#define mc2_wbf_acc_acc_nsr_BITS                                   1
+#define mc2_wbf_acc_acc_nsr_SHIFT                                  4
+#define mc2_wbf_acc_acc_nsr_DEFAULT                                0x00000001
+
+
+#define mc2_wbf_acc_perm_sw_MASK                                   0x00000008
+#define mc2_wbf_acc_perm_sw_ALIGN                                  0
+#define mc2_wbf_acc_perm_sw_BITS                                   1
+#define mc2_wbf_acc_perm_sw_SHIFT                                  3
+#define mc2_wbf_acc_perm_sw_DEFAULT                                0x00000001
+
+
+#define mc2_wbf_acc_perm_sr_MASK                                   0x00000004
+#define mc2_wbf_acc_perm_sr_ALIGN                                  0
+#define mc2_wbf_acc_perm_sr_BITS                                   1
+#define mc2_wbf_acc_perm_sr_SHIFT                                  2
+#define mc2_wbf_acc_perm_sr_DEFAULT                                0x00000001
+
+
+#define mc2_wbf_acc_perm_nsw_MASK                                  0x00000002
+#define mc2_wbf_acc_perm_nsw_ALIGN                                 0
+#define mc2_wbf_acc_perm_nsw_BITS                                  1
+#define mc2_wbf_acc_perm_nsw_SHIFT                                 1
+#define mc2_wbf_acc_perm_nsw_DEFAULT                               0x00000001
+
+
+#define mc2_wbf_acc_perm_nsr_MASK                                  0x00000001
+#define mc2_wbf_acc_perm_nsr_ALIGN                                 0
+#define mc2_wbf_acc_perm_nsr_BITS                                  1
+#define mc2_wbf_acc_perm_nsr_SHIFT                                 0
+#define mc2_wbf_acc_perm_nsr_DEFAULT                               0x00000001
+
+
+
+
+#define mc2_wbf_ver_reserved0_MASK                                 0xffffff00
+#define mc2_wbf_ver_reserved0_ALIGN                                0
+#define mc2_wbf_ver_reserved0_BITS                                 24
+#define mc2_wbf_ver_reserved0_SHIFT                                8
+
+
+#define mc2_wbf_ver_version_MASK                                   0x000000ff
+#define mc2_wbf_ver_version_ALIGN                                  0
+#define mc2_wbf_ver_version_BITS                                   8
+#define mc2_wbf_ver_version_SHIFT                                  0
+#define mc2_wbf_ver_version_DEFAULT                                0x00000000
+
+
+
+
+#define mc2_wbf_pri_cfg_wbf_en_MASK                                0x80000000
+#define mc2_wbf_pri_cfg_wbf_en_ALIGN                               0
+#define mc2_wbf_pri_cfg_wbf_en_BITS                                1
+#define mc2_wbf_pri_cfg_wbf_en_SHIFT                               31
+#define mc2_wbf_pri_cfg_wbf_en_DEFAULT                             0x00000000
+
+
+#define mc2_wbf_pri_cfg_reserved0_MASK                             0x70000000
+#define mc2_wbf_pri_cfg_reserved0_ALIGN                            0
+#define mc2_wbf_pri_cfg_reserved0_BITS                             3
+#define mc2_wbf_pri_cfg_reserved0_SHIFT                            28
+
+
+#define mc2_wbf_pri_cfg_prefetch_en_MASK                           0x0f000000
+#define mc2_wbf_pri_cfg_prefetch_en_ALIGN                          0
+#define mc2_wbf_pri_cfg_prefetch_en_BITS                           4
+#define mc2_wbf_pri_cfg_prefetch_en_SHIFT                          24
+#define mc2_wbf_pri_cfg_prefetch_en_DEFAULT                        0x00000000
+
+
+#define mc2_wbf_pri_cfg_reserved1_MASK                             0x00e00000
+#define mc2_wbf_pri_cfg_reserved1_ALIGN                            0
+#define mc2_wbf_pri_cfg_reserved1_BITS                             3
+#define mc2_wbf_pri_cfg_reserved1_SHIFT                            21
+
+
+#define mc2_wbf_pri_cfg_wbf_pslc_buf_mode_MASK                     0x00100000
+#define mc2_wbf_pri_cfg_wbf_pslc_buf_mode_ALIGN                    0
+#define mc2_wbf_pri_cfg_wbf_pslc_buf_mode_BITS                     1
+#define mc2_wbf_pri_cfg_wbf_pslc_buf_mode_SHIFT                    20
+#define mc2_wbf_pri_cfg_wbf_pslc_buf_mode_DEFAULT                  0x00000000
+
+
+#define mc2_wbf_pri_cfg_high_pri_chn_MASK                          0x000f0000
+#define mc2_wbf_pri_cfg_high_pri_chn_ALIGN                         0
+#define mc2_wbf_pri_cfg_high_pri_chn_BITS                          4
+#define mc2_wbf_pri_cfg_high_pri_chn_SHIFT                         16
+#define mc2_wbf_pri_cfg_high_pri_chn_DEFAULT                       0x00000003
+
+
+#define mc2_wbf_pri_cfg_reserved2_MASK                             0x0000fff0
+#define mc2_wbf_pri_cfg_reserved2_ALIGN                            0
+#define mc2_wbf_pri_cfg_reserved2_BITS                             12
+#define mc2_wbf_pri_cfg_reserved2_SHIFT                            4
+
+
+#define mc2_wbf_pri_cfg_high_pri_ifm_MASK                          0x0000000f
+#define mc2_wbf_pri_cfg_high_pri_ifm_ALIGN                         0
+#define mc2_wbf_pri_cfg_high_pri_ifm_BITS                          4
+#define mc2_wbf_pri_cfg_high_pri_ifm_SHIFT                         0
+#define mc2_wbf_pri_cfg_high_pri_ifm_DEFAULT                       0x00000003
+
+
+
+
+#define mc2_wbf_sta_bq_full_MASK                                   0x80000000
+#define mc2_wbf_sta_bq_full_ALIGN                                  0
+#define mc2_wbf_sta_bq_full_BITS                                   1
+#define mc2_wbf_sta_bq_full_SHIFT                                  31
+
+
+#define mc2_wbf_sta_bq_empty_MASK                                  0x40000000
+#define mc2_wbf_sta_bq_empty_ALIGN                                 0
+#define mc2_wbf_sta_bq_empty_BITS                                  1
+#define mc2_wbf_sta_bq_empty_SHIFT                                 30
+
+
+#define mc2_wbf_sta_reserved0_MASK                                 0x3ffc0000
+#define mc2_wbf_sta_reserved0_ALIGN                                0
+#define mc2_wbf_sta_reserved0_BITS                                 12
+#define mc2_wbf_sta_reserved0_SHIFT                                18
+
+
+#define mc2_wbf_sta_wbf_buf_level_MASK                             0x0003ff00
+#define mc2_wbf_sta_wbf_buf_level_ALIGN                            0
+#define mc2_wbf_sta_wbf_buf_level_BITS                             10
+#define mc2_wbf_sta_wbf_buf_level_SHIFT                            8
+
+
+#define mc2_wbf_sta_bq_count_MASK                                  0x000000ff
+#define mc2_wbf_sta_bq_count_ALIGN                                 0
+#define mc2_wbf_sta_bq_count_BITS                                  8
+#define mc2_wbf_sta_bq_count_SHIFT                                 0
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_go_MASK                         0x80000000
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_go_ALIGN                        0
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_go_BITS                         1
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_go_SHIFT                        31
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_go_DEFAULT                      0x00000000
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wr_MASK                         0x40000000
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wr_ALIGN                        0
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wr_BITS                         1
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wr_SHIFT                        30
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wr_DEFAULT                      0x00000000
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_reserved0_MASK                       0x3ff80000
+#define mc2_wbf_bkdr_bkdr_cmd_reserved0_ALIGN                      0
+#define mc2_wbf_bkdr_bkdr_cmd_reserved0_BITS                       11
+#define mc2_wbf_bkdr_bkdr_cmd_reserved0_SHIFT                      19
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_slice_MASK                      0x00070000
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_slice_ALIGN                     0
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_slice_BITS                      3
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_slice_SHIFT                     16
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_pslc_wbf_buf_sel_MASK                0x0000ff00
+#define mc2_wbf_bkdr_bkdr_cmd_pslc_wbf_buf_sel_ALIGN               0
+#define mc2_wbf_bkdr_bkdr_cmd_pslc_wbf_buf_sel_BITS                8
+#define mc2_wbf_bkdr_bkdr_cmd_pslc_wbf_buf_sel_SHIFT               8
+#define mc2_wbf_bkdr_bkdr_cmd_pslc_wbf_buf_sel_DEFAULT             0x00000000
+
+
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wbf_id_MASK                     0x000000ff
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wbf_id_ALIGN                    0
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wbf_id_BITS                     8
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wbf_id_SHIFT                    0
+#define mc2_wbf_bkdr_bkdr_cmd_bkdr_wbf_id_DEFAULT                  0x00000000
+
+
+
+#define mc2_wbf_bkdr_bkdr_datai_ARRAY_BASE                         0x00000e94
+#define mc2_wbf_bkdr_bkdr_datai_ARRAY_START                        0
+#define mc2_wbf_bkdr_bkdr_datai_ARRAY_END                          7
+#define mc2_wbf_bkdr_bkdr_datai_ARRAY_ELEMENT_SIZE                 32
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_datai_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_datai_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_datai_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_datai_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_datai_data_DEFAULT                       0x00000000
+
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data0_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data0_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data0_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data0_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data0_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data1_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data1_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data1_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data1_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data1_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data2_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data2_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data2_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data2_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data2_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data3_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data3_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data3_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data3_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data3_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data4_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data4_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data4_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data4_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data4_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data5_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data5_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data5_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data5_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data5_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data6_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data6_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data6_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data6_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data6_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_bkdr_bkdr_data7_data_MASK                          0xffffffff
+#define mc2_wbf_bkdr_bkdr_data7_data_ALIGN                         0
+#define mc2_wbf_bkdr_bkdr_data7_data_BITS                          32
+#define mc2_wbf_bkdr_bkdr_data7_data_SHIFT                         0
+#define mc2_wbf_bkdr_bkdr_data7_data_DEFAULT                       0x00000000
+
+
+
+
+#define mc2_wbf_id_bkdr_id_cmd_id_freeze_MASK                      0x80000000
+#define mc2_wbf_id_bkdr_id_cmd_id_freeze_ALIGN                     0
+#define mc2_wbf_id_bkdr_id_cmd_id_freeze_BITS                      1
+#define mc2_wbf_id_bkdr_id_cmd_id_freeze_SHIFT                     31
+#define mc2_wbf_id_bkdr_id_cmd_id_freeze_DEFAULT                   0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_cmd_reserved0_MASK                      0x70000000
+#define mc2_wbf_id_bkdr_id_cmd_reserved0_ALIGN                     0
+#define mc2_wbf_id_bkdr_id_cmd_reserved0_BITS                      3
+#define mc2_wbf_id_bkdr_id_cmd_reserved0_SHIFT                     28
+
+
+#define mc2_wbf_id_bkdr_id_cmd_id_go_MASK                          0x0f000000
+#define mc2_wbf_id_bkdr_id_cmd_id_go_ALIGN                         0
+#define mc2_wbf_id_bkdr_id_cmd_id_go_BITS                          4
+#define mc2_wbf_id_bkdr_id_cmd_id_go_SHIFT                         24
+#define mc2_wbf_id_bkdr_id_cmd_id_go_DEFAULT                       0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_cmd_reserved1_MASK                      0x00fe0000
+#define mc2_wbf_id_bkdr_id_cmd_reserved1_ALIGN                     0
+#define mc2_wbf_id_bkdr_id_cmd_reserved1_BITS                      7
+#define mc2_wbf_id_bkdr_id_cmd_reserved1_SHIFT                     17
+
+
+#define mc2_wbf_id_bkdr_id_cmd_id_wr_MASK                          0x00010000
+#define mc2_wbf_id_bkdr_id_cmd_id_wr_ALIGN                         0
+#define mc2_wbf_id_bkdr_id_cmd_id_wr_BITS                          1
+#define mc2_wbf_id_bkdr_id_cmd_id_wr_SHIFT                         16
+#define mc2_wbf_id_bkdr_id_cmd_id_wr_DEFAULT                       0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_cmd_reserved2_MASK                      0x0000ff00
+#define mc2_wbf_id_bkdr_id_cmd_reserved2_ALIGN                     0
+#define mc2_wbf_id_bkdr_id_cmd_reserved2_BITS                      8
+#define mc2_wbf_id_bkdr_id_cmd_reserved2_SHIFT                     8
+
+
+#define mc2_wbf_id_bkdr_id_cmd_id_addr_MASK                        0x000000ff
+#define mc2_wbf_id_bkdr_id_cmd_id_addr_ALIGN                       0
+#define mc2_wbf_id_bkdr_id_cmd_id_addr_BITS                        8
+#define mc2_wbf_id_bkdr_id_cmd_id_addr_SHIFT                       0
+#define mc2_wbf_id_bkdr_id_cmd_id_addr_DEFAULT                     0x00000000
+
+
+
+
+#define mc2_wbf_id_bkdr_id_data_wbf_id_wr_ptr_MASK                 0xff000000
+#define mc2_wbf_id_bkdr_id_data_wbf_id_wr_ptr_ALIGN                0
+#define mc2_wbf_id_bkdr_id_data_wbf_id_wr_ptr_BITS                 8
+#define mc2_wbf_id_bkdr_id_data_wbf_id_wr_ptr_SHIFT                24
+#define mc2_wbf_id_bkdr_id_data_wbf_id_wr_ptr_DEFAULT              0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_data_wbf_id_rd_ptr_MASK                 0x00ff0000
+#define mc2_wbf_id_bkdr_id_data_wbf_id_rd_ptr_ALIGN                0
+#define mc2_wbf_id_bkdr_id_data_wbf_id_rd_ptr_BITS                 8
+#define mc2_wbf_id_bkdr_id_data_wbf_id_rd_ptr_SHIFT                16
+#define mc2_wbf_id_bkdr_id_data_wbf_id_rd_ptr_DEFAULT              0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_data_bq_count_wr_MASK                   0x0000ff00
+#define mc2_wbf_id_bkdr_id_data_bq_count_wr_ALIGN                  0
+#define mc2_wbf_id_bkdr_id_data_bq_count_wr_BITS                   8
+#define mc2_wbf_id_bkdr_id_data_bq_count_wr_SHIFT                  8
+#define mc2_wbf_id_bkdr_id_data_bq_count_wr_DEFAULT                0x00000000
+
+
+#define mc2_wbf_id_bkdr_id_data_wbf_id_MASK                        0x000000ff
+#define mc2_wbf_id_bkdr_id_data_wbf_id_ALIGN                       0
+#define mc2_wbf_id_bkdr_id_data_wbf_id_BITS                        8
+#define mc2_wbf_id_bkdr_id_data_wbf_id_SHIFT                       0
+#define mc2_wbf_id_bkdr_id_data_wbf_id_DEFAULT                     0x00000000
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63146/misc.h b/arch/arm/include/asm/arch-bcm63146/misc.h
new file mode 100644
index 0000000000..1d101c732e
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/misc.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63146_MISC_H
+#define _63146_MISC_H
+
+#define MISC_BASE          0xff802600
+
+/*
+ * Misc Register Set Definitions.
+ */
+typedef struct Misc {
+   uint32_t miscStrapBus; /* 0x00 */
+
+    /* boot select bits 3-5 */
+#define BOOT_SEL_STRAP_NAND_2K_PAGE             0x00
+#define BOOT_SEL_STRAP_NAND_4K_PAGE             0x08
+#define BOOT_SEL_STRAP_NAND_8K_PAGE             0x10
+#define BOOT_SEL_STRAP_NAND_512B_PAGE           0x18
+#define BOOT_SEL_STRAP_SPI_NOR                  0x38
+#define BOOT_SEL_STRAP_EMMC                     0x30
+#define BOOT_SEL_STRAP_SPI_NAND                 0x28
+
+#define BOOT_SEL_STRAP_BOOT_SEL_MASK            (0x38)
+#define BOOT_SEL_STRAP_PAGE_SIZE_MASK           (0x7)
+
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           0
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_PCIE0_RC_MODE            (0x1 << 6)
+#define MISC_STRAP_BUS_LS_SPI_SLAVE_DISABLE     (0x1 << 7)
+#define MISC_STRAP_BUS_B53_BOOT_N               (0x1 << 8)
+/* When ROM BOOT OTP bits are 2b'11, always boot rom secure boot, this strap bit is don't care.
+   When ROM BOOT OTP bits are are not 2b'11, this trap bit determine the following:
+   1: boot rom non-secure boot
+   0: XIP boot
+*/
+#define MISC_STRAP_BUS_BOOTROM_BOOT             (0x1 << 12)
+#define MISC_STRAP_BUS_SW_RESERVE_MASK          (0x3 << 14)
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT      16
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ            (0x1 << MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT)
+   uint32_t miscStrapOverride;     /* 0x04 */
+   uint32_t miscMaskUBUSErr;       /* 0x08 */
+   uint32_t miscPeriphCtrl;        /* 0x0c */
+   uint32_t miscSpiMasterCtrl;     /* 0x10 */
+   uint32_t reserved0;             /* 0x14 */
+   uint32_t miscPeriphMiscCtrl;    /* 0x18 */
+   uint32_t miscPeriphMiscStat;    /* 0x1c */
+   uint32_t miscSoftResetB;        /* 0x20 */
+   uint32_t miscSpare0;            /* 0x24 */
+   uint32_t miscSWdebugNW[2];      /* 0x28 */
+   uint32_t miscWDResetCtrl;       /* 0x30 */
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+
+/*
+ * Gpio Controller
+ */
+typedef struct GpioControl {
+        uint32_t GPIODir[8];             /* 0x00-0x1f */
+        uint32_t GPIOio[8];              /* 0x20-0x3f */
+        uint32_t PadCtrl;                 /* 0x40 */
+        uint32_t SpiSlaveCfg;             /* 0x44 */
+        uint32_t TestControl;             /* 0x48 */
+        uint32_t TestPortBlockEnMSB;      /* 0x4c */
+        uint32_t TestPortBlockEnLSB;      /* 0x50 */
+        uint32_t TestPortBlockDataMSB;    /* 0x54 */
+        uint32_t TestPortBlockDataLSB;    /* 0x58 */
+        uint32_t TestPortCmd;             /* 0x5c */
+        uint32_t DiagReadBack;            /* 0x60 */
+        uint32_t DiagReadBackHi;          /* 0x64 */
+        uint32_t GeneralPurpose;          /* 0x68 */
+        uint32_t spare[3];
+} GpioControl;
+
+#define GPIO_BASE              0xff800500
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+#define PINCTRL_BASE           (GPIO_BASE + 0x54)
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xfff
+} PerfControl;
+
+#define PERF_BASE              0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+#define BCM_WDT_SOFT_RESET (PERF_BASE+0x48c)
+#define BCM_LOWLEVEL_RESET() { *((volatile uint32_t *)BCM_WDT_SOFT_RESET) = 1; }
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63146/otp.h b/arch/arm/include/asm/arch-bcm63146/otp.h
new file mode 100644
index 0000000000..7365c388e2
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/otp.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _63146_OTP_H
+#define _63146_OTP_H
+
+
+#define JTAG_OTP_BASE    0xff802800
+
+/* row 9 */
+#define OTP_CPU_CLOCK_FREQ_ROW                  9
+#define OTP_CPU_CLOCK_FREQ_SHIFT                0
+#define OTP_CPU_CLOCK_FREQ_MASK                 0x7
+
+/* row 8 */
+#define OTP_CPU_CORE_CFG_ROW                    8
+#define OTP_CPU_CORE_CFG_SHIFT                  28
+#define OTP_CPU_CORE_CFG_MASK                   0x1 // 0=dual cores, 1=single core
+
+/* row 14 */
+#define OTP_JTAG_CUST_LOCK_ROW			0xff	
+#define OTP_JTAG_CUST_LOCK_MASK			0x1
+#define OTP_JTAG_CUST_LOCK_REG_SHIFT		25
+
+/* row 13 */
+#define OTP_BRCM_PRODUCTION_MODE_ROW       	13
+#define OTP_BRCM_PRODUCTION_MODE_SHIFT     	0
+#define OTP_BRCM_PRODUCTION_MODE_MASK      	0x1
+
+/* row 13 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           13
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         2
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+/* row 14 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           14
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         28
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          0x1 
+
+/* row 14 */
+#define OTP_CUST_BTRM_UART_DISABLE_ROW          14
+#define OTP_CUST_BTRM_UART_DISABLE_SHIFT        0
+#define OTP_CUST_BTRM_UART_DISABLE_MASK         1
+
+/* row 14 */
+#define OTP_CUST_BTRM_MSG_DISABLE_ROW           14
+#define OTP_CUST_BTRM_MSG_DISABLE_SHIFT         27
+#define OTP_CUST_BTRM_MSG_DISABLE_MASK          1
+/* row 29 */
+#define OTP_CUST_MFG_MRKTID_ROW                 29
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_BRCM_PRODUCTION_MODE, OTP_BRCM_PRODUCTION_MODE_ROW, OTP_BRCM_PRODUCTION_MODE_MASK, OTP_BRCM_PRODUCTION_MODE_SHIFT, 1},				\
+	}
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63146/pmc.h b/arch/arm/include/asm/arch-bcm63146/pmc.h
new file mode 100644
index 0000000000..46eeedc124
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/pmc.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63146_PMC_H
+#define _63146_PMC_H 
+
+#define PMC_BASE         0xFFB00000
+#define PMC ((volatile Pmc * const)PMC_BASE)
+
+#define PMB_BASE         0xFFB20100
+#define PMB ((volatile PMBMaster * const)PMB_BASE)
+
+#define PROC_MON_BASE   0xFFB00000
+#define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
+
+typedef struct PmcCtrlReg {
+    uint32_t gpTmr0Ctl;           /* 0x018 */
+    uint32_t gpTmr0Cnt;           /* 0x01c */
+    uint32_t gpTmr1Ctl;           /* 0x020 */
+    uint32_t gpTmr1Cnt;           /* 0x024 */
+    uint32_t hostMboxIn;          /* 0x028 */
+    uint32_t hostMboxOut;         /* 0x02c */
+    uint32_t reserved[4];         /* 0x030 */
+    uint32_t dmaCtrl;             /* 0x040 */
+    uint32_t dmaStatus;           /* 0x044 */
+    uint32_t dma0_3FifoStatus;    /* 0x048 */
+    uint32_t reserved1[4];	    /* 0x04c */
+    uint32_t diagControl;         /* 0x05c */
+    uint32_t diagHigh;            /* 0x060 */
+    uint32_t diagLow;             /* 0x064 */
+    uint32_t reserved8;           /* 0x068 */
+    uint32_t addr1WndwMask;       /* 0x06c */
+    uint32_t addr1WndwBaseIn;     /* 0x070 */
+    uint32_t addr1WndwBaseOut;    /* 0x074 */
+    uint32_t addr2WndwMask;       /* 0x078 */
+    uint32_t addr2WndwBaseIn;     /* 0x07c */
+    uint32_t addr2WndwBaseOut;    /* 0x080 */
+    uint32_t scratch;             /* 0x084 */
+    uint32_t reserved9;           /* 0x088 */
+    uint32_t softResets;          /* 0x08c */
+    uint32_t reserved2;           /* 0x090 */
+    uint32_t m4keCoreStatus;      /* 0x094 */
+    uint32_t reserved3;           /* 0x098 */
+    uint32_t ubSlaveTimeout;      /* 0x09c */
+    uint32_t diagEn;              /* 0x0a0 */
+    uint32_t devTimeout;          /* 0x0a4 */
+    uint32_t ubusErrorOutMask;    /* 0x0a8 */
+    uint32_t diagCaptStopMask;    /* 0x0ac */
+    uint32_t revId;               /* 0x0b0 */
+    uint32_t reserved4[4];        /* 0x0b4 */
+    uint32_t diagCtrl;            /* 0x0c4 */
+    uint32_t diagStat;            /* 0x0c8 */
+    uint32_t diagMask;            /* 0x0cc */
+    uint32_t diagRslt;            /* 0x0d0 */
+    uint32_t diagCmp;             /* 0x0d4 */
+    uint32_t diagCapt;            /* 0x0d8 */    
+    uint32_t diagCnt;             /* 0x0dc */
+    uint32_t diagEdgeCnt;         /* 0x0e0 */
+    uint32_t reserved5[4];	    /* 0x0e4 */
+    uint32_t smisc_bus_config;    /* 0x0f4 */
+    uint32_t lfsr;                /* 0x0f8 */
+    uint32_t dqm_pac_lock;        /* 0x0fc */
+    uint32_t l1_irq_4ke_mask;     /* 0x100 */
+    uint32_t l1_irq_4ke_status;   /* 0x104 */
+    uint32_t l1_irq_mips_mask;    /* 0x108 */
+    uint32_t l1_irq_mips_status;  /* 0x10c */
+    uint32_t l1_irq_mips1_mask;   /* 0x110 */
+    uint32_t reserved6[3];        /* 0x114 */
+    uint32_t l2_irq_gp_mask;      /* 0x120 */
+    uint32_t l2_irq_gp_status;    /* 0x124 */
+    uint32_t l2_irq_gp_set;       /* 0x128 */
+    uint32_t reserved7;           /* 0x12c */
+    uint32_t gp_in_irq_mask;      /* 0x130 */
+    uint32_t gp_in_irq_status;    /* 0x134 */
+    uint32_t gp_in_irq_set;       /* 0x138 */
+    uint32_t gp_in_irq_sense;     /* 0x13c */
+    uint32_t gp_in;               /* 0x140 */
+    uint32_t gp_out;              /* 0x144 */
+} PmcCtrlReg;
+
+typedef struct PmcDmaReg {
+	/* 0x00 */
+	uint32_t src;
+	uint32_t dest;
+	uint32_t cmdList;
+	uint32_t lenCtl;
+	/* 0x10 */
+	uint32_t rsltSrc;
+	uint32_t rsltDest;
+	uint32_t rsltHcs;
+	uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+	/* 0x00 */
+	uint32_t bufSize;
+	uint32_t bufBase;
+	uint32_t idx2ptrIdx;
+	uint32_t idx2ptrPtr;
+	/* 0x10 */
+	uint32_t unused[2];
+	uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+	uint32_t freqScalarCtrl; /* 0x3c */
+	uint32_t freqScalarMask; /* 0x40 */
+} PmcPerfPowReg;
+
+typedef struct PmcDQMPac {
+    uint32_t dqmPac[32];
+} PmcDQMPac;
+
+typedef struct PmcDQMReg {
+	uint32_t cfg;                     /* 0x1c00 */
+	uint32_t _4keLowWtmkIrqMask;      /* 0x1c04 */
+	uint32_t mipsLowWtmkIrqMask;      /* 0x1c08 */
+	uint32_t lowWtmkIrqMask;          /* 0x1c0c */
+	uint32_t _4keNotEmptyIrqMask;     /* 0x1c10 */
+	uint32_t mipsNotEmptyIrqMask;     /* 0x1c14 */
+	uint32_t notEmptyIrqSts;          /* 0x1c18 */
+	uint32_t queueRst;                /* 0x1c1c */
+	uint32_t notEmptySts;             /* 0x1c20 */
+	uint32_t nextAvailMask;           /* 0x1c24 */
+	uint32_t nextAvailQueue;          /* 0x1c28 */
+	uint32_t mips1LowWtmkIrqMask;     /* 0x1c2c */
+	uint32_t mips1NotEmptyIrqMask;    /* 0x1c30 */
+	uint32_t autoSrcPidInsert;        /* 0x1c34 */
+    uint32_t timerIrqStatus;          /* 0x1c38 */
+    uint32_t timerStatus;             /* 0x1c3c */
+    uint32_t _4keTimerIrqMask;        /* 0x1c40 */
+    uint32_t mipsTimerIrqMask;        /* 0x1c44 */
+    uint32_t mips1TimerIrqMask;       /* 0x1c48 */
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+	uint32_t cntr[10];
+	uint32_t unused[6];	/* 0x28-0x3f */
+	uint32_t cntrIrqMask;
+	uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+	uint32_t size;
+	uint32_t cfga;
+	uint32_t cfgb;
+	uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+	uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+	uint32_t qNumFull[32];
+	uint32_t qNumEmpty[32];
+	uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+typedef struct SSBMaster {
+    uint32_t ssbmControl;     /* 0x0060 */
+    uint32_t ssbmWrData;      /* 0x0064 */
+    uint32_t ssbmRdData;      /* 0x0068 */
+    uint32_t ssbmStatus;      /* 0x006c */
+} SSBMaster;
+
+typedef struct PmmReg {
+    uint32_t memPowerCtrl;            /* 0x0000 */
+    uint32_t regSecurityConfig;       /* 0x0004 */
+} PmmReg;
+
+typedef struct keyholeReg {
+    uint32_t ctrlSts;
+    uint32_t wrData;
+    uint32_t mutex;
+    uint32_t rdData;
+} keyholeReg;
+
+typedef struct PmbBus {
+    uint32_t config;          /* 0x0100 */
+    uint32_t arbiter;         /* 0x0104 */
+    uint32_t timeout;         /* 0x0108 */
+    uint32_t unused1;         /* 0x010c */
+    keyholeReg keyhole[4];  /* 0x0110-0x014f */
+    uint32_t unused2[44];     /* 0x0150-0x01ff */
+    uint32_t map[64];         /* 0x0200-0x02ff */ 
+}PmbBus;
+
+typedef struct  CoreCtrl {
+    uint32_t  coreEnable;         /* 0x0400 */
+    uint32_t  autoresetControl;   /* 0x0404 */
+    uint32_t  coreIdle;           /* 0x0408 */
+    uint32_t  coreResetCause;     /* 0x040c */
+    uint32_t  memPwrDownCtrl0;    /* 0x0410 */
+    uint32_t  memPwrDownSts0;     /* 0x0414 */
+    uint32_t  memPwrDownCtrl1;    /* 0x0418 */
+    uint32_t  memPwrDownSts1;     /* 0x041c */
+    uint32_t  sysFlg0Status;      /* 0x0420 */
+    uint32_t  sysFlg0Set;         /* 0x0424 */
+    uint32_t  sysFlg0Clear;       /* 0x0428 */
+    uint32_t  unused1;            /* 0x042c */
+    uint32_t  usrFlg0Status;      /* 0x0430 */
+    uint32_t  usrFlg0Set;         /* 0x0434 */
+    uint32_t  usrFlg0Clear;       /* 0x0438 */
+    uint32_t  unused2;            /* 0x043c */
+    uint32_t  subsystemRev;       /* 0x0440 */
+    uint32_t  resetVector;        /* 0x0444 */
+} CoreCtrl;
+
+typedef struct  CoreState {
+    uint32_t  sysMbx[8];          /* 0x0480 */
+    uint32_t  usrMbx[8];          /* 0x04a0 */
+    uint32_t  sysMtx[4];          /* 0x04c0 */
+    uint32_t  usrMtx[8];          /* 0x04d0 */
+} CoreState;
+
+typedef struct  CoreIntr {
+    uint32_t  irqStatus;          /* 0x0500 */
+    uint32_t  irqSet;             /* 0x0504 */
+    uint32_t  irqClear;           /* 0x0508 */
+    uint32_t  unused1;            /* 0x050c */
+    uint32_t  srqStatus;          /* 0x0510 */
+    uint32_t  srqSet;             /* 0x0514 */
+    uint32_t  srqClear;           /* 0x0518 */
+    uint32_t  unused2;            /* 0x051c */
+    uint32_t  drqStatus;          /* 0x0520 */
+    uint32_t  drqSet;             /* 0x0524 */
+    uint32_t  drqClear;           /* 0x0528 */
+    uint32_t  unused3;            /* 0x052c */
+    uint32_t  frqStatus;          /* 0x0530 */
+    uint32_t  frqSet;             /* 0x0534 */
+    uint32_t  frqClear;           /* 0x0538 */
+    uint32_t  unused4;            /* 0x053c */
+    uint32_t  hostIrqLatched;     /* 0x0540 */
+    uint32_t  hostIrqSet;         /* 0x0544 */
+    uint32_t  hostIrqClear;       /* 0x0548 */
+    uint32_t  hostIrqEnable;      /* 0x054c */
+    uint32_t  obusFaultStatus;    /* 0x0550 */
+    uint32_t  obusFaultClear;     /* 0x0554 */
+    uint32_t  obusFaultAddr;      /* 0x0558 */
+} CoreIntr;
+
+typedef struct CoreProfile {
+    uint32_t  mutex;              /* 0x0580 */
+    uint32_t  lastConfPcLo;       /* 0x0584 */
+    uint32_t  lastConfPcHi;       /* 0x0588 */
+    uint32_t  lastPcLo;           /* 0x058c */
+    uint32_t  lastPcHi;           /* 0x0590 */
+    uint32_t  braTargetPc0Lo;     /* 0x0594 */
+    uint32_t  braTargetPc0Hi;     /* 0x0598 */
+    uint32_t  braTargetPc1Lo;     /* 0x059c */
+    uint32_t  braTargetPc1Hi;     /* 0x05a0 */
+    uint32_t  braTargetPc2Lo;     /* 0x05a4 */
+    uint32_t  braTargetPc2Hi;     /* 0x05a8 */
+    uint32_t  braTargetPc3Lo;     /* 0x05ac */
+    uint32_t  braTargetPc3Hi;     /* 0x05b0 */
+    uint32_t  unused[3];          /* 0x05b4-0x05bf */
+    uint32_t  profSampleW[4];     /* 0x05c0 */
+} CoreProfile;
+
+typedef struct MaestroMisc {
+    CoreCtrl coreCtrl;          /* 0x0400 */
+    uint32_t   unused1[14];       /* 0x0448-0x047f */
+    CoreState coreState;        /* 0x0480 */
+    uint32_t   unused2[4];        /* 0x04f0-0x04ff */
+    CoreIntr interrupt;         /* 0x0500 */
+    uint32_t   unused3[9];        /* 0x055c-0x057f */
+    CoreProfile profile;        /* 0x0580 */
+} MaestroMisc;
+
+typedef struct Pmc {
+    uint32_t unused0[1030];
+    PmcCtrlReg ctrl;		            /* 0x1018 */
+    uint32_t unused1[622];	            /* 0x1148-0x1cff */
+    PmcDQMPac dqmPac;                   /* 0x1b00 */
+    uint32_t unused5[32];                 /* 0x1b80-0x1bff */
+    PmcDQMReg dqm;			            /* 0x1c00 */
+    uint32_t unused6[749];		        /* 0x1c4c-0x27ff */
+    uint32_t qStatus[32];		            /* 0x2800 */
+    uint32_t unused7[480];	            /* 0x2880-0x2fff */
+    PmcDqmQMibReg qMib;		            /* 0x3000 */
+    uint32_t unused8[928];	            /* 0x3180-0x3fff */
+    PmcDqmQCtrlReg dqmQCtrl[8]; 	    /* 0x4000 */
+    uint32_t unused9[992];                /* 0x4080-0x4fff */
+    PmcDqmQDataReg dqmQData[8]; 	    /* 0x5000 */
+} Pmc;
+
+typedef struct Procmon {
+    uint32_t unused00[256];
+    MaestroMisc maestroReg;             /* 0x00400 */
+    uint32_t unused10[32396];             /* 0x005d0-0x1ffff */
+    PmmReg  pmm;                        /* 0x20000 */
+    uint32_t unused11[22];                /* 0x20008-0x2005f */
+    SSBMaster ssbMasterCtrl;            /* 0x20060 */
+    uint32_t unused12[36];                /* 0x20070-0x200ff */
+    PmbBus pmb;                         /* 0x20100 */
+    uint32_t unused13[32576];             /* 0x20300-0x3ffff */
+    uint32_t qsm[128];                    /* 0x40000-0x401ff */
+    uint32_t unused14[65408];             /* 0x40200-0x7ffff */
+    uint32_t dtcm[1024];                  /* 0x80000-0x80fff */
+    uint32_t unused15[64512];             /* 0x81000-0xbffff */
+    uint32_t itcm[4096];                  /* 0xc0000-0xc3fff */
+} Procmon;
+
+
+typedef struct PMSSBMasterControl {
+	uint32_t control;
+	uint32_t wr_data;
+	uint32_t rd_data;
+} PMSSBMasterControl;
+
+typedef struct
+{
+    uint32_t  control;
+#define PMC_PMBM_START		            (1 << 31)
+#define PMC_PMBM_TIMEOUT	            (1 << 30)
+#define PMC_PMBM_SLAVE_ERR	            (1 << 29)
+#define PMC_PMBM_BUSY		            (1 << 28)
+#define PMC_PMBM_BUS_SHIFT              (20)
+#define PMC_PMBM_Read		            (0 << 24)
+#define PMC_PMBM_Write		            (1 << 24)
+    uint32_t  wr_data;
+    uint32_t  mutex;
+    uint32_t  rd_data;
+} PMB_keyhole_reg;
+
+typedef struct PMBMaster {
+    uint32_t config;
+#define PMB_NUM_REGS_SHIFT (20)
+#define PMB_NUM_REGS_MASK  (0x3ff)
+    uint32_t arbitger;
+    uint32_t timeout;
+    uint32_t reserved;
+    PMB_keyhole_reg keyhole[4];
+    uint32_t reserved1[44];
+    uint32_t map[64];
+} PMBMaster;
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63146/pmc_addr.h b/arch/arm/include/asm/arch-bcm63146/pmc_addr.h
new file mode 100644
index 0000000000..7b32c731ea
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/pmc_addr.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63146_PMC_ADDR_H
+#define _63146_PMC_ADDR_H
+
+/* FIXME! only fill those that I found from RTL */
+#define PMB_BUS_MAX		2
+#define PMB_BUS_ID_SHIFT	12
+
+#define PMB_BUS_PCIE0		0
+#define PMB_ADDR_PCIE0		(0 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0		1
+
+#define PMB_BUS_VDSL3_CORE	0
+#define PMB_ADDR_VDSL3_CORE	(1 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_VDSL3_CORE	1
+
+#define PMB_BUS_EGPHY		0
+#define PMB_ADDR_EGPHY		(2 | PMB_BUS_EGPHY << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_EGPHY		1	// not shown in spreadsheet
+
+#define PMB_BUS_XRDP		0
+#define PMB_ADDR_XRDP		(3 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP		3
+
+#define PMB_BUS_USB30_2X	0
+#define PMB_ADDR_USB30_2X	(4 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB30_2X	4
+
+#define PMB_BUS_MEMC		0
+#define PMB_ADDR_MEMC		(5 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC		1
+
+#define PMB_BUS_PVTMON		0
+#define PMB_ADDR_PVTMON		(6 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON	0
+
+#define PMB_BUS_PCIE1		0
+#define PMB_ADDR_PCIE1		(7 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1		1
+
+#define PMB_BUS_PCIE2		0
+#define PMB_ADDR_PCIE2		(8 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE2		1
+
+#define PMB_BUS_PERIPH		1
+#define PMB_ADDR_PERIPH		(9 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH	4
+
+#define PMB_BUS_VDSL3_PMD	1
+#define PMB_ADDR_VDSL3_PMD	(10 | PMB_BUS_VDSL3_PMD << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_VDSL3_PMD	1
+
+//--------- DGASP related bits/Offsets ------------------------
+#define BPCM_PHY_CNTL_OVERRIDE		0x00000002	
+#define BPCM_PHY_CNTL_AFE_PWRDWN	0x00000001
+#define PMB_ADDR_VDSL_DGASP_PMD		PMB_ADDR_VDSL3_PMD
+#define BPCM_VDSL_PHY_CTL_REG		vdsl_afe_config1	// Alias for register containing DGASP override inside the VDSL PMD
+#define BPCM_VDSL_AFE_CTL_REG		vdsl_afe_config0	// Alias for register containing DGASP configuration inside the VDSL PMD
+
+#define PMB_BUS_AFEPLL		1
+#define PMB_ADDR_AFEPLL		(11 | PMB_BUS_AFEPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_AFEPLL	1
+
+#define AFEPLL_PMB_BUS_VDSL3_CORE	PMB_BUS_AFEPLL
+#define AFEPLL_PMB_ADDR_VDSL3_CORE	PMB_ADDR_AFEPLL
+#define AFEPLL_PMB_ZONES_VDSL3_CORE	PMB_ZONES_AFEPLL
+
+#define PMB_BUS_CHIP_CLKRST	1
+#define PMB_ADDR_CHIP_CLKRST	(12 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST	0
+
+#define PMB_BUS_RDPPLL		1
+#define PMB_ADDR_RDPPLL		(13 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_RDPPLL	0
+
+#define PMB_BUS_BIU_PLL		1
+#define PMB_ADDR_BIU_PLL	(32 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL	0
+
+#define PMB_BUS_BIU_BPCM	1
+#define PMB_ADDR_BIU_BPCM	(33 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM	1
+
+#define PMB_BUS_ORION_CPU0	1
+#define PMB_ADDR_ORION_CPU0	(34 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0	1
+
+#define PMB_BUS_ORION_CPU1	1
+#define PMB_ADDR_ORION_CPU1	(35 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1	1
+
+#define PMB_BUS_ORION_NONCPU	1
+#define PMB_ADDR_ORION_NONCPU	(38 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU	1
+
+#define PMB_BUS_ORION_ARS	1
+#define PMB_ADDR_ORION_ARS	(39 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_ARS	0
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63146/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm63146/pmc_drv_cfg.h
new file mode 100644
index 0000000000..c38e5eb307
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/pmc_drv_cfg.h
@@ -0,0 +1,40 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_3_X
+#define PMC_IMPL_3_2
+
+#define PMC_LOG_IN_DTCM         1
+#define PMC_FW_IN_ITCM          1
+#define PMC_CPUTEMP_SUPPORT     1
+#define PMC_RAM_BOOT 1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm63146/rng.h b/arch/arm/include/asm/arch-bcm63146/rng.h
new file mode 100644
index 0000000000..d17142f69f
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63146_RNG_H
+#define _63146_RNG_H
+
+#define RNG_BASE	0xff800b80
+
+typedef struct Rng {
+	uint32_t ctrl0;			/* 0x00 */
+	uint32_t rngSoftReset;		/* 0x04 */
+	uint32_t rbgSoftReset;		/* 0x08 */
+	uint32_t totalBitCnt;		/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;			/* 0x14 */
+	uint32_t intStatus;		/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL	(0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL	(0x1<<2)
+	uint32_t intEn;			/* 0x1c */
+	uint32_t rngFifoData;		/* 0x20 */
+	uint32_t fifoCnt;		/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS	0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS	0x33
+	uint32_t perm;			/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63146/ubus4.h b/arch/arm/include/asm/arch-bcm63146/ubus4.h
new file mode 100644
index 0000000000..841e9c2b07
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/ubus4.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63146_UBUS4_H
+#define _63146_UBUS4_H
+
+#define MST_PORT_NODE_PER_PHYS_BASE         0x83010000
+#define MST_PORT_NODE_USB_PHYS_BASE         0x83018000
+#define MST_PORT_NODE_B53_PHYS_BASE         0x83020000
+#define MST_PORT_NODE_PCIE0_PHYS_BASE       0x83028000
+#define MST_PORT_NODE_PCIE1_PHYS_BASE       0x83030000
+#define MST_PORT_NODE_PCIE2_PHYS_BASE       0x83038000
+#define MST_PORT_NODE_DSL_PHYS_BASE         0x83048000
+#define MST_PORT_NODE_DSLCPU_PHYS_BASE      0x83050000
+#define MST_PORT_NODE_RQ0_PHYS_BASE         0x83058000
+#define MST_PORT_NODE_DMA0_PHYS_BASE        0x83060000
+#define MST_PORT_NODE_DMA1_PHYS_BASE        0x83068000
+#define MST_PORT_NODE_QM_PHYS_BASE          0x83070000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63146/xrdp.h b/arch/arm/include/asm/arch-bcm63146/xrdp.h
new file mode 100644
index 0000000000..ea77da7e86
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63146/xrdp.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63146_XRDP_H
+#define _63146_XRDP_H
+
+#define XRDP_BASE            0x82000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/BPCM.h b/arch/arm/include/asm/arch-bcm63148/BPCM.h
new file mode 100644
index 0000000000..9d5227934d
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/BPCM.h
@@ -0,0 +1,725 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t sw_strap:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+// types of PMB devices
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t z0_mux_sel:1;	/* 0 */
+		uint32_t reserved0:4;	/* 1-4 */
+		uint32_t z1_gphy_reset:1;	/* 5 */
+		uint32_t reserved1:3;	/* 6-8 */
+		uint32_t z1_ck25_clk_dis:1;	/* 9 */
+		uint32_t z1_ck250_clk_en:1;	/* 10 */
+		uint32_t reserved2:1;	/* 11 */
+		uint32_t z1_gphy_mux_sel:1;	/* 12 */
+		uint32_t z1_pda_en:1;	/* 13 */
+		uint32_t reserved3:3;	/* 14-16 */
+		uint32_t z2_gphy_reset:1;	/* 17 */
+		uint32_t z2_serdes_reset:1;	/* 18 */
+		uint32_t z2_serdes_reset_mdioregs:1;	/* 19 */
+		uint32_t z2_sedes_reset_pll:1;	/* 20 */
+		uint32_t z2_ck250_clk_en:1;	/* 21 */
+		uint32_t z2_ck25_clk_dis:1;	/* 22 */
+		uint32_t z2_serdes_clk_en:1;	/* 23 */
+		uint32_t reserved4:1;	/* 24 */
+		uint32_t z2_serdes_mux_sel:1;	/* 25 */
+		uint32_t z2_gphy_mux_sel:1;	/* 26 */
+		uint32_t z2_crossbar_mux_sel:1;	/* 27 */
+		uint32_t z2_p_wan_phy_sel:2;	/* 28-29 */
+		uint32_t z2_switch_phy_sel:2;	/* 30-31 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu0_reset_n:1;	// 00:00    R/W
+		uint32_t power_down:1;	// 01:01    R/W
+		uint32_t reserved:30;	// 31:02    R/O
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	BPCM_ZONE_N_FREQ_SCALAR_CONTROL freq_scalar_control;
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	BPCM_SGPHY_CNTL sgphy_cntl;	// offset = 0x38, actual offset = 14
+	BPCM_SGPHY_STATUS sgphy_status;	// offset = 0x3c, actual offset = 15
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	uint32_t rvrsd[2];
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_VDSL_REGS;		// total offset space = 4096
+
+#define BPCMVDSLOffset(reg)	offsetof(BPCM_VDSL_REGS,reg)
+#define BPCMVDSLRegOffset(reg)	(BPCMVDSLOffset(reg) >> 2)
+
+// ARM BPCM addresses as used by 63148 and possibly others (28nm)
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved;	// offset = 0x2c, actual offset = 11
+	ARM_CONTROL_REG arm_control;	// offset = 0x30, actual offset = 12
+	uint32_t reserved1[3];	// offset = 0x34, actual offset = 13..15
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} ARM_BPCM_REGS;
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	uint32_t decndiv;	// offset = 0x44, actual offset = 0x11
+	uint32_t decpdiv;	// offset = 0x48, actual offset = 0x12
+	uint32_t decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved1;	// offset = 0x2c, actual offset = 11
+	uint32_t clkrst_cfg;	// offset = 0x30, actual offset = 12
+	uint32_t clkrst_control;	// offset = 0x34, actual offset = 13
+	uint32_t xtal_control;	// offset = 0x38, actual offset = 14
+	uint32_t clkrst_stat;	// offset = 0x3c, actual offset = 15
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/boot0.h b/arch/arm/include/asm/arch-bcm63148/boot0.h
new file mode 100644
index 0000000000..8ce5f5a0f2
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/boot0.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63148_BOOT0_H
+#define _63148_BOOT0_H
+
+#include <asm-offsets.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+_bcm_boot:
+	mov	r0,#0
+	mcr	p15,0,r0,c8,c7,0		/* Invalidate TLB */
+	mcr	p15,0,r0,c7,c5,0		/* Invalidate icache */
+	
+	/* Initialize system control register enable i-cache */
+	mrc	p15,0,r0,c1,c0,0
+	bic	r0,r0,#(CR_C|CR_A|CR_M)		/* Clear C, A, M bits */
+	orr	r0,r0,#CR_I			/* Set I bit: enable instruction cache */
+	mcr	p15,0,r0,c1,c0,0
+
+	isb
+
+#include <asm/arch/pmc_ll_init.h>
+
+	/* relocate the code, init'ed data from flash to lmem  */	
+relo_image:
+	adr     r1, _bcm_boot		/* r1 source address in flash */
+	ldr	r0, =__image_copy_start	/* r0 dest address in sram */
+	subs	r4, r1, r0		/* r4 relocation offset */
+	beq	relo_dtb		/* skip relocation */
+	ldr	r2, =__image_copy_end	/* r2 dest ending address in flash */
+
+relo_loop:
+	ldmia	r1!, {r10-r11}
+	stmia	r0!, {r10-r11}
+	cmp	r0, r2
+	blo	relo_loop
+
+	/* if we attached dtb after bss, need to relocate dtb as well */	
+relo_dtb:
+#if defined(CONFIG_SPL_OF_CONTROL) && defined(CONFIG_OF_SEPARATE)
+
+#ifdef CONFIG_OF_SPL_SEPARATE_BSS
+	ldr	r3, =__image_binary_end
+#else
+	ldr	r3, =__bss_end
+#endif
+	add	r1, r3, r4       /* r1 source address in flash */
+	/* check ftd size ... */
+	/* struct fdt_header {
+	fdt32_t magic;
+	fdt32_t totalsize; */
+	ldr	r0, [r1, #4]	/* r0 total size */
+	rev	r0, r0          /* byte order from fdt to little endian */
+	lsr	r0, r0, #2      /* in the order of 4 bytes aligned */
+	add	r0, r0, #1
+	lsl	r0, r0, #2 
+	add	r2, r1, r0       /* r2 dest ending address in flash */
+	mov	r0, r3           /* r0 dest address in sram */
+
+dtb_loop:
+	ldmia	r1!, {r10-r11}
+	stmia	r0!, {r10-r11}
+	cmp	r1, r2
+	blo	dtb_loop
+#endif
+	ldr	r0, =reset
+	bx	r0
+
+#endif
+	.align(5), 0x0
+_start:
+	ARM_VECTORS
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/brom.h b/arch/arm/include/asm/arch-bcm63148/brom.h
new file mode 100644
index 0000000000..63c8c2d896
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/brom.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63148_BROM_H
+#define _63148_BROM_H
+#define BROM_SEC_BASE 0xfffeb614	   	 
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromSec_ {
+#define	BROM_GEN_JTAG_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_JTAG_SPI_SLV_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+} BromSec;
+
+#define BROM_GEN ((volatile BromSec * const) BROM_SEC_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= (BROM_GEN_JTAGE_SPI_SLV_UNLOCK_MASK<<BROM_GEN_JTAG_SPI_SLV_UNLOCK_SHIFT) ; }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/cpu.h b/arch/arm/include/asm/arch-bcm63148/cpu.h
new file mode 100644
index 0000000000..79267786dd
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/cpu.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63148_CPU_H
+#define _63148_CPU_H
+
+#define B15_CTRL_BASE		0x80020000
+#define BOOTLUT_BASE		0xffff0000
+
+/*
+ * B15 CFG
+ */
+typedef struct B15ArchRegion {
+	uint32_t addr_ulimit;
+	uint32_t addr_llimit;
+	uint32_t permission;
+	uint32_t access_right_ctrl;
+} B15ArchRegion;
+
+typedef struct B15Arch {
+	B15ArchRegion region[8];
+	uint32_t unused[95];
+	uint32_t scratch;
+} B15Arch;
+
+typedef struct B15CpuBusRange {
+#define ULIMIT_SHIFT 4
+#define BUSNUM_MASK 0x0000000FU
+
+#define BUSNUM_UBUS 1
+#define BUSNUM_RBUS 2
+#define BUSNUM_RSVD 3
+#define BUSNUM_MCP0 4
+#define BUSNUM_MCP1 5
+#define BUSNUM_MCP2 6
+
+	uint32_t ulimit;
+	uint32_t llimit;
+} B15CpuBusRange;
+
+typedef struct B15CpuAccessRightViol {
+	uint32_t addr;
+	uint32_t upper_addr;
+	uint32_t detail_addr;
+} B15CpuAccessRightViol;
+
+typedef struct B15CpuBPCMAVS {
+	uint32_t bpcm_id;
+	uint32_t bpcm_capability;
+	uint32_t bpcm_ctrl;
+	uint32_t bpcm_status;
+	uint32_t avs_rosc_ctrl;
+	uint32_t avs_rosc_threshold;
+	uint32_t avs_rosc_cnt;
+	uint32_t avs_pwd_ctrl;
+} B15CpuBPCMAVS;
+
+typedef struct B15CpuCtrl {
+	B15CpuBusRange bus_range[11];	/* 0x0 */
+	uint32_t secure_reset_hndshake;
+	uint32_t secure_soft_reset;
+	B15CpuAccessRightViol access_right_viol[2];	/* 0x60 */
+	uint32_t rac_cfg0;
+	uint32_t rac_cfg1;
+	uint32_t rac_flush;		/* 0x80 */
+	uint32_t cpu_power_cfg;
+	uint32_t cpu0_pwr_zone_ctrl;
+	uint32_t cpu1_pwr_zone_ctrl;
+	uint32_t cpu2_pwr_zone_ctrl;	/* 0x90 */
+	uint32_t cpu3_pwr_zone_ctrl;
+	uint32_t l2biu_pwr_zone_ctrl;
+	uint32_t cpu0_pwr_zone_cfg1;
+	uint32_t cpu0_pwr_zone_cfg2;	/* 0xa0 */
+	uint32_t cpu1_pwr_zone_cfg1;
+	uint32_t cpu1_pwr_zone_cfg2;
+	uint32_t cpu2_pwr_zone_cfg1;
+	uint32_t cpu2_pwr_zone_cfg2;	/* 0xb0 */
+	uint32_t cpu3_pwr_zone_cfg1;
+	uint32_t cpu3_pwr_zone_cfg2;
+	uint32_t l2biu_pwr_zone_cfg1;
+	uint32_t l2biu_pwr_zone_cfg2;	/* 0xc0 */
+	uint32_t cpu0_pwr_freq_scalar_ctrl;
+	uint32_t cpu1_pwr_freq_scalar_ctrl;
+	uint32_t cpu2_pwr_freq_scalar_ctrl;
+	uint32_t cpu3_pwr_freq_scalar_ctrl;	/* 0xd0 */
+	uint32_t l2biu_pwr_freq_scalar_ctrl;
+	B15CpuBPCMAVS cpu_bpcm_avs[4];	/* 0xd8 */
+	B15CpuBPCMAVS l2biu_bpcm_avs;	/* 0x158 */
+	uint32_t reset_cfg;		/* 0x178 */
+	uint32_t clock_cfg;
+	uint32_t misc_cfg;		/* 0x180 */
+	uint32_t credit;
+	uint32_t therm_throttle_temp;
+	uint32_t term_throttle_irq_cfg;
+	uint32_t therm_irq_high;		/* 0x190 */
+	uint32_t therm_irq_low;
+	uint32_t therm_misc_threshold;
+	uint32_t therm_irq_misc;
+	uint32_t defeature;		/* 0x1a0 */
+	uint32_t defeature_key;
+	uint32_t debug_rom_addr;
+	uint32_t debug_self_addr;
+	uint32_t debug_tracectrl;		/* 0x1b0 */
+	uint32_t axi_cfg;
+	uint32_t revision;
+	uint32_t ubus_cfg_window[8];	/* 0x1bc */
+	uint32_t ubus_cfg;		/* 0x1dc */
+	uint32_t unused[135];
+	uint32_t scratch;			/* 0x3fc */
+} B15CpuCtrl;
+
+typedef struct B15Ctrl {
+	uint32_t unused0[1024];
+	B15Arch arch;			/* 0x1000 */
+	uint32_t unused1[896];
+	B15CpuCtrl cpu_ctrl;		/* 0x2000 */
+} B15Ctrl;
+
+#define B15CTRL ((volatile B15Ctrl *const) B15_CTRL_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/ddr.h b/arch/arm/include/asm/arch-bcm63148/ddr.h
new file mode 100644
index 0000000000..811663e0c1
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/ddr.h
@@ -0,0 +1,417 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63148_DDR_H
+#define _63148_DDR_H
+
+#define DDRPHY_BASE    0x80003000
+#define MEMC_BASE      0x80002000
+
+typedef struct UBUSInterface {
+	uint32_t CFG;		/* 0x00 */
+#define UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT   0x0
+#define UBUSIF_CFG_WRITE_REPLY_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT)
+#define UBUSIF_CFG_WRITE_BURST_MODE_SHIFT   0x1
+#define UBUSIF_CFG_WRITE_BURST_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_BURST_MODE_SHIFT)
+#define UBUSIF_CFG_INBAND_ERR_MASK_SHIFT    0x2
+#define UBUSIF_CFG_INBAND_ERR_MASK_MASK     (0x1<< UBUSIF_CFG_INBAND_ERR_MASK_SHIFT)
+#define UBUSIF_CFG_OOB_ERR_MASK_SHIFT       0x3
+#define UBUSIF_CFG_OOB_ERR_MASK_MASK        (0x1<< UBUSIF_CFG_OOB_ERR_MASK_SHIFT)
+	uint32_t SRC_QUEUE_CTRL_0;	/* 0x04 */
+	uint32_t SRC_QUEUE_CTRL_1;	/* 0x08 */
+	uint32_t SRC_QUEUE_CTRL_2;	/* 0x0c */
+	uint32_t SRC_QUEUE_CTRL_3;	/* 0x10 */
+	uint32_t REP_ARB_MODE;	/* 0x14 */
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT 0x0
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_MASK  (0x1<<UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT)
+	uint32_t SCRATCH;	/* 0x18 */
+	uint32_t DEBUG_R0;	/* 0x1c */
+	uint32_t unused[8];	/* 0x20-0x3f */
+} UBUSInterface;
+
+typedef struct EDISEngine {
+	uint32_t REV_ID;	/* 0x00 */
+	uint32_t CTRL_TRIG;	/* 0x04 */
+	uint32_t CTRL_MODE;	/* 0x08 */
+	uint32_t CTRL_SIZE;	/* 0x0c */
+	uint32_t CTRL_ADDR_START;	/* 0x10 */
+	uint32_t CTRL_ADDR_START_EXT;	/* 0x14 */
+	uint32_t CTRL_ADDR_END;	/* 0x18 */
+	uint32_t CTRL_ADDR_END_EXT;	/* 0x1c */
+	uint32_t CTRL_WRITE_MASKS;	/* 0x20 */
+	uint32_t unused0[7];	/* 0x24-0x3f */
+	uint32_t STAT_MAIN;	/* 0x40 */
+	uint32_t STAT_WORDS_WRITTEN;	/* 0x44 */
+	uint32_t STAT_WORDS_READ;	/* 0x48 */
+	uint32_t STAT_ERROR_COUNT;	/* 0x4c */
+	uint32_t STAT_ERROR_BITS;	/* 0x50 */
+	uint32_t STAT_ADDR_LAST;	/* 0x54 */
+	uint32_t STAT_ADDR_LAST_EXT;	/* 0x58 */
+	uint32_t unused1[8];	/* 0x5c-0x7b */
+	uint32_t STAT_DEBUG;	/* 0x7c */
+	uint32_t STAT_DATA_PORT[8];	/* 0x80-0x9c */
+	uint32_t GEN_LFSR_STATE[4];	/* 0xa0-0xac */
+	uint32_t GEN_CLOCK;	/* 0xb0 */
+	uint32_t GEN_PATTERN;	/* 0xb4 */
+	uint32_t unused2[2];	/* 0xb8-0xbf */
+	uint32_t BYTELANE_0_CTRL_LO;	/* 0xc0 */
+	uint32_t BYTELANE_0_CTRL_HI;	/* 0xc4 */
+	uint32_t BYTELANE_1_CTRL_LO;	/* 0xc8 */
+	uint32_t BYTELANE_1_CTRL_HI;	/* 0xcc */
+	uint32_t BYTELANE_2_CTRL_LO;	/* 0xd0 */
+	uint32_t BYTELANE_2_CTRL_HI;	/* 0xd4 */
+	uint32_t BYTELANE_3_CTRL_LO;	/* 0xd8 */
+	uint32_t BYTELANE_3_CTRL_HI;	/* 0xdc */
+	uint32_t BYTELANE_0_STAT_LO;	/* 0xe0 */
+	uint32_t BYTELANE_0_STAT_HI;	/* 0xe4 */
+	uint32_t BYTELANE_1_STAT_LO;	/* 0xe8 */
+	uint32_t BYTELANE_1_STAT_HI;	/* 0xec */
+	uint32_t BYTELANE_2_STAT_LO;	/* 0xf0 */
+	uint32_t BYTELANE_2_STAT_HI;	/* 0xf4 */
+	uint32_t BYTELANE_3_STAT_LO;	/* 0xf8 */
+	uint32_t BYTELANE_3_STAT_HI;	/* 0xfc */
+} EDISEngine;
+
+typedef struct SecureRangeCheckers {
+	uint32_t LOCK;		/* 0x00 */
+	uint32_t LOG_INFO_0;	/* 0x04 */
+	uint32_t LOG_INFO_1;	/* 0x08 */
+	uint32_t CTRL_0;	/* 0x0c */
+	uint32_t UBUS0_PORT_0;	/* 0x10 */
+	uint32_t BASE_0;	/* 0x14 */
+	uint32_t CTRL_1;	/* 0x18 */
+	uint32_t UBUS0_PORT_1;	/* 0x1c */
+	uint32_t BASE_1;	/* 0x20 */
+	uint32_t CTRL_2;	/* 0x24 */
+	uint32_t UBUS0_PORT_2;	/* 0x28 */
+	uint32_t BASE_2;	/* 0x2c */
+	uint32_t CTRL_3;	/* 0x30 */
+	uint32_t UBUS0_PORT_3;	/* 0x34 */
+	uint32_t BASE_3;	/* 0x38 */
+	uint32_t CTRL_4;	/* 0x3c */
+	uint32_t UBUS0_PORT_4;	/* 0x40 */
+	uint32_t BASE_4;	/* 0x44 */
+	uint32_t CTRL_5;	/* 0x48 */
+	uint32_t UBUS0_PORT_5;	/* 0x4c */
+	uint32_t BASE_5;	/* 0x50 */
+	uint32_t CTRL_6;	/* 0x54 */
+	uint32_t UBUS0_PORT_6;	/* 0x58 */
+	uint32_t BASE_6;	/* 0x5c */
+	uint32_t CTRL_7;	/* 0x60 */
+	uint32_t UBUS0_PORT_7;	/* 0x64 */
+	uint32_t BASE_7;	/* 0x68 */
+	uint32_t unused[37];	/* 0x6c-0xff */
+} SecureRangeCheckers;
+
+typedef struct DDRPhyControl {
+	uint32_t REVISION;	/* 0x00 */
+	uint32_t PLL_STATUS;	/* 0x04 */
+	uint32_t PLL_CONFIG;	/* 0x08 */
+	uint32_t PLL_CONTROL1;	/* 0x0c */
+	uint32_t PLL_CONTROL2;	/* 0x10 */
+	uint32_t PLL_CONTROL3;	/* 0x14 */
+	uint32_t PLL_DIVIDER;	/* 0x18 */
+	uint32_t PLL_PRE_DIVIDER;	/* 0x1c */
+	uint32_t PLL_SS_EN;	/* 0x20 */
+	uint32_t PLL_SS_CFG;	/* 0x24 */
+	uint32_t AUX_CONTROL;	/* 0x28 */
+	uint32_t IDLE_PAD_CONTROL;	/* 0x2c */
+	uint32_t IDLE_PAD_EN0;	/* 0x30 */
+	uint32_t IDLE_PAD_EN1;	/* 0x34 */
+	uint32_t DRIVE_PAD_CTL;	/* 0x38 */
+	uint32_t STATIC_PAD_CTL;	/* 0x3c */
+	uint32_t DRAM_CFG;	/* 0x40 */
+	uint32_t DRAM_TIMING1;	/* 0x44 */
+	uint32_t DRAM_TIMING2;	/* 0x48 */
+	uint32_t DRAM_TIMING3;	/* 0x4c */
+	uint32_t DRAM_TIMING4;	/* 0x50 */
+	uint32_t unused0[3];	/* 0x54-0x5f */
+
+	uint32_t VDL_REGS[47];	/* 0x60-0x118 */
+	uint32_t AC_SPARE;	/* 0x11c */
+	uint32_t unused1[4];	/* 0x120-0x12f */
+
+	uint32_t REFRESH;	/* 0x130 */
+	uint32_t UPDATE_VDL;	/* 0x134 */
+	uint32_t UPDATE_VDL_SNOOP1;	/* 0x138 */
+	uint32_t UPDATE_VDL_SNOOP2;	/* 0x13c */
+	uint32_t CMND_REG1;	/* 0x140 */
+	uint32_t CMND_AUX_REG1;	/* 0x144 */
+	uint32_t CMND_REG2;	/* 0x148 */
+	uint32_t CMND_AUX_REG2;	/* 0x14c */
+	uint32_t CMND_REG3;	/* 0x150 */
+	uint32_t CMND_AUX_REG3;	/* 0x154 */
+	uint32_t CMND_REG4;	/* 0x158 */
+	uint32_t CMND_AUX_REG4;	/* 0x15c */
+	uint32_t CMND_REG_TIMER;	/* 0x160 */
+	uint32_t MODE_REG[9];	/* 0x164-184 */
+#define PHY_CONTROL_MODE_REG_VALID_SHIFT       16
+#define PHY_CONTROL_MODE_REG_VALID_MASK        (0x1<<PHY_CONTROL_MODE_REG_VALID_SHIFT)
+	uint32_t MODE_REG15;	/* 0x188 */
+	uint32_t MODE_REG63;	/* 0x18c */
+	uint32_t ALERT_CLEAR;	/* 0x190 */
+	uint32_t ALERT_STATUS;	/* 0x194 */
+	uint32_t CA_PARITY;	/* 0x198 */
+	uint32_t CA_PLAYBACK_CTRL;	/* 0x19c */
+	uint32_t CA_PLAYBACK_STATUS0;	/* 0x1a0 */
+	uint32_t CA_PLAYBACK_STATUS1;	/* 0x1a4 */
+	uint32_t unused2;	/* 0x1a8 */
+	uint32_t WRITE_LEVEL_CTRL;	/* 0x1ac */
+	uint32_t WRITE_LEVEL_STATUS;	/* 0x1b0 */
+	uint32_t READ_EN_CTRL;	/* 0x1b4 */
+	uint32_t READ_EN_STATUS;	/* 0x1b8 */
+	uint32_t unused3;	/* 0x1bc */
+	uint32_t TRAFFIC_GEN[12];	/* 0x1c0-0x1ec */
+	uint32_t VIRT_VTT_CTRL;	/* 0x1f0 */
+	uint32_t VIRT_VTT_STATUS;	/* 0x1f4 */
+	uint32_t VIRT_VTT_CONNECTION;	/* 0x1f8 */
+	uint32_t VIRT_VTT_OVERRIDE;	/* 0x1fc */
+	uint32_t VREF_DAC_CTRL;	/* 0x200 */
+	uint32_t PHYBIST[9];	/* 0x204-0x224 */
+	uint32_t unused4[2];	/* 0x228-0x22f */
+	uint32_t STANDBY_CTRL;	/* 0x230 */
+	uint32_t DEBUG_FREEZE_EN;	/* 0x234 */
+	uint32_t DEBUG_MUX_CTRL;	/* 0x238 */
+	uint32_t DFI_CTRL;	/* 0x23c */
+#define PHY_CONTROL_DFI_CNTRL_DFI_CS1_SHIFT    7
+#define PHY_CONTROL_DFI_CNTRL_DFI_CS1_MASK     (0x1<<PHY_CONTROL_DFI_CNTRL_DFI_CS1_SHIFT)
+#define PHY_CONTROL_DFI_CNTRL_DFI_CS0_SHIFT    6
+#define PHY_CONTROL_DFI_CNTRL_DFI_CS0_MASK     (0x1<<PHY_CONTROL_DFI_CNTRL_DFI_CS0_SHIFT)
+#define PHY_CONTROL_DFI_CNTRL_DFI_RSTN_SHIFT   5
+#define PHY_CONTROL_DFI_CNTRL_DFI_RSTN_MASK    (0x1<<PHY_CONTROL_DFI_CNTRL_DFI_RSTN_SHIFT)
+#define PHY_CONTROL_DFI_CNTRL_DFI_CKE1_SHIFT   4
+#define PHY_CONTROL_DFI_CNTRL_DFI_CKE1_MASK    (0x1<<PHY_CONTROL_DFI_CNTRL_DFI_CKE1_SHIFT)
+#define PHY_CONTROL_DFI_CNTRL_DFI_CKE0_SHIFT   3
+#define PHY_CONTROL_DFI_CNTRL_DFI_CKE0_MASK    (0x1<<PHY_CONTROL_DFI_CNTRL_DFI_CKE0_SHIFT)
+#define PHY_CONTROL_DFI_CNTRL_ASSERT_REQ_SHIFT 0
+#define PHY_CONTROL_DFI_CNTRL_ASSERT_REQ_MASK  (0x1<<PHY_CONTROL_DFI_CNTRL_ASSERT_REQ_SHIFT)
+	uint32_t WRITE_ODT_CTRL;	/* 0x240 */
+	uint32_t ABI_PAR_CTRL;	/* 0x244 */
+	uint32_t ZQ_CAL;	/* 0x248 */
+	uint32_t unused5[109];	/* 0x24c-0x3ff */
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+	uint32_t VDL_CTRL_WR[12];	/* 0x00 - 0x2c */
+	uint32_t VDL_CTRL_RD[24];	/* 0x30 - 0x8c */
+	uint32_t VDL_CLK_CTRL;	/* 0x90 */
+	uint32_t VDL_LDE_CTRL;	/* 0x94 */
+	uint32_t unused0[2];	/* 0x98-0x9f */
+	uint32_t RD_EN_DLY_CYC;	/* 0xa0 */
+	uint32_t WR_CHAN_DLY_CYC;	/* 0xa4 */
+	uint32_t unused1[2];	/* 0xa8-0xaf */
+	uint32_t RD_CTRL;	/* 0xb0 */
+	uint32_t RD_FIFO_ADDR;	/* 0xb4 */
+	uint32_t RD_FIFO_DATA;	/* 0xb8 */
+	uint32_t RD_FIFO_DM_DBI;	/* 0xbc */
+	uint32_t RD_FIFO_STATUS;	/* 0xc0 */
+	uint32_t RD_FIFO_CLR;	/* 0xc4 */
+	uint32_t IDLE_PAD_CTRL;	/* 0xc8 */
+	uint32_t DRIVE_PAD_CTRL;	/* 0xcc */
+	uint32_t RD_EN_DRIVE_PAD_CTRL;	/* 0xd0 */
+	uint32_t STATIC_PAD_CTRL;	/* 0xd4 */
+	uint32_t WR_PREAMBLE_MODE;	/* 0xd8 */
+	uint32_t unused2;	/* 0xdc */
+	uint32_t ODT_CTRL;	/* 0xe0 */
+	uint32_t unused3[3];	/* 0xe4-0xef */
+	uint32_t EDC_DPD_CTRL;	/* 0xf0 */
+	uint32_t EDC_DPD_STATUS;	/* 0xf4 */
+	uint32_t EDC_DPD_OUT_CTRL;	/* 0xf8 */
+	uint32_t EDC_DPD_OUT_STATUS;	/* 0xfc */
+	uint32_t EDC_DPD_OUT_STATUS_CLEAR;	/* 0x100 */
+	uint32_t EDC_CRC_CTRL;	/* 0x104 */
+	uint32_t EDC_CRC_STATUS;	/* 0x108 */
+	uint32_t EDC_CRC_COUNT;	/* 0x10c */
+	uint32_t EDC_CRC_STATUS_CLEAR;	/* 0x110 */
+	uint32_t BL_SPARE_REG;	/* 0x114 */
+	uint32_t unused4[58];
+} DDRPhyByteLaneControl;
+
+typedef struct MEMCControl {
+	uint32_t GLB_VERS;	/* 0x000 */
+	uint32_t GLB_GCFG;	/* 0x004 */
+#define MEMC_GLB_GCFG_DRAM_EN_SHIFT        31
+#define MEMC_GLB_GCFG_DRAM_EN_MASK         (0x1<<MEMC_GLB_GCFG_DRAM_EN_SHIFT)
+#define MEMC_GLB_GCFG_PHY_4X_SHIFT         24
+#define MEMC_GLB_GCFG_PHY_4X_MASK          (0x1<<MEMC_GLB_GCFG_PHY_4X_SHIFT)
+#define MEMC_GLB_GCFG_MCLKSRC_SHIFT        9
+#define MEMC_GLB_GCFG_MCLKSRC_MASK         (0x1<<MEMC_GLB_GCFG_MCLKSRC_SHIFT)
+#define MEMC_GLB_GCFG_MEMINITDONE_SHIFT    8
+#define MEMC_GLB_GCFG_MEMINITDONE_MASK     (0x1<<MEMC_GLB_GCFG_MEMINITDONE_SHIFT)
+#define MEMC_GLB_GCFG_SIZE1_SHIFT          0
+#define MEMC_GLB_GCFG_SIZE1_MASK           (0xf<<MEMC_GLB_GCFG_SIZE1_SHIFT)
+
+	uint32_t unused0[2];	/* 0x008-0x00f */
+	uint32_t GLB_CFG;	/* 0x010 */
+#define MEMC_GLB_CFG_RR_MODE_SHIFT      0x0
+#define MEMC_GLB_CFG_RR_MODE_MASK       (0x1<<MEMC_GLB_CFG_RR_MODE_SHIFT)
+#define MEMC_GLB_CFG_BURST_MODE_SHIFT   0x1
+#define MEMC_GLB_CFG_BURST_MODE_MASK    (0x1<<MEMC_GLB_CFG_BURST_MODE_SHIFT)
+	uint32_t GLB_QUE_DIS;	/* 0x014 */
+	uint32_t GLB_SP_SEL;	/* 0x018 */
+#define MEMC_GLB_SP_SEL_SELECT_MASK     0x001fffff
+	uint32_t GLB_SP_PRI_0;	/* 0x01c */
+	uint32_t GLB_SP_PRI_1;	/* 0x020 */
+	uint32_t GLB_SP_PRI_2;	/* 0x024 */
+	uint32_t GLB_SP_PRI_3;	/* 0x028 */
+	uint32_t GLB_SP_PRI_4;	/* 0x02c */
+	uint32_t GLB_SP_PRI_5;	/* 0x030 */
+	uint32_t unused1[3];	/* 0x034-0x3f */
+	uint32_t GLB_RR_QUANTUM[12];	/* 0x040-0x06c */
+	uint32_t unused2[4];	/* 0x070-0x07f */
+
+	uint32_t INTR2_CPU_STATUS;	/* 0x080 */
+	uint32_t INTR2_CPU_SET;	/* 0x084 */
+	uint32_t INTR2_CPU_CLEAR;	/* 0x088 */
+	uint32_t INTR2_CPU_MASK_STATUS;	/* 0x08c */
+	uint32_t INTR2_CPU_MASK_SET;	/* 0x090 */
+	uint32_t INTR2_CPU_MASK_CLEAR;	/* 0x094 */
+	uint32_t unused3[10];	/* 0x098-0x0bf */
+
+	uint32_t SRAM_REMAP_CTRL;	/* 0x0c0 */
+	uint32_t SRAM_REMAP_INIT;	/* 0x0c4 */
+	uint32_t SRAM_REMAP_LOG_INFO_0;	/* 0x0c8 */
+	uint32_t SRAM_REMAP_LOG_INFO_1;	/* 0x0cc */
+	uint32_t unused4[12];	/* 0x0d0-0x0ff */
+
+	uint32_t CHN_CFG_CNFG;	/* 0x100 */
+	uint32_t CHN_CFG_CSST;	/* 0x104 */
+	uint32_t CHN_CFG_CSEND;	/* 0x108 */
+	uint32_t unused5;	/* 0x10c */
+	uint32_t CHN_CFG_ROW00_0;	/* 0x110 */
+	uint32_t CHN_CFG_ROW00_1;	/* 0x114 */
+	uint32_t CHN_CFG_ROW01_0;	/* 0x118 */
+	uint32_t CHN_CFG_ROW01_1;	/* 0x11c */
+	uint32_t unused6[4];	/* 0x120-0x12f */
+	uint32_t CHN_CFG_ROW20_0;	/* 0x130 */
+	uint32_t CHN_CFG_ROW20_1;	/* 0x134 */
+	uint32_t CHN_CFG_ROW21_0;	/* 0x138 */
+	uint32_t CHN_CFG_ROW21_1;	/* 0x13c */
+	uint32_t unused7[4];	/* 0x140-0x14f */
+	uint32_t CHN_CFG_COL00_0;	/* 0x150 */
+	uint32_t CHN_CFG_COL00_1;	/* 0x154 */
+	uint32_t CHN_CFG_COL01_0;	/* 0x158 */
+	uint32_t CHN_CFG_COL01_1;	/* 0x15c */
+	uint32_t unused8[4];	/* 0x160-0x16f */
+	uint32_t CHN_CFG_COL20_0;	/* 0x170 */
+	uint32_t CHN_CFG_COL20_1;	/* 0x174 */
+	uint32_t CHN_CFG_COL21_0;	/* 0x178 */
+	uint32_t CHN_CFG_COL21_1;	/* 0x17c */
+	uint32_t unused9[4];	/* 0x180-0x18f */
+	uint32_t CHN_CFG_BNK10;	/* 0x190 */
+	uint32_t CHN_CFG_BNK32;	/* 0x194 */
+	uint32_t unused10[26];	/* 0x198-0x1ff */
+
+	uint32_t CHN_TIM_DCMD;	/* 0x200 */
+	uint32_t CHN_TIM_DMODE_0;	/* 0x204 */
+	uint32_t CHN_TIM_DMODE_2;	/* 0x208 */
+	uint32_t CHN_TIM_CLKS;	/* 0x20c */
+	uint32_t CHN_TIM_ODT;	/* 0x210 */
+	uint32_t CHN_TIM_TIM1_0;	/* 0x214 */
+	uint32_t CHN_TIM_TIM1_1;	/* 0x218 */
+	uint32_t CHN_TIM_TIM2;	/* 0x21c */
+	uint32_t CHN_TIM_CTL_CRC;	/* 0x220 */
+	uint32_t CHN_TIM_DOUT_CRC;	/* 0x224 */
+	uint32_t CHN_TIM_DIN_CRC;	/* 0x228 */
+	uint32_t CHN_TIM_CRC_CTRL;	/* 0x22c */
+	uint32_t CHN_TIM_PHY_ST;	/* 0x230 */
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP       0x1
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_HW_RESET       0x2
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_SW_RESET       0x4
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_READY          0x10
+	uint32_t CHN_TIM_DRAM_CFG;	/* 0x234 */
+#define DRAM_CFG_DRAMSLEEP          (1<<11)
+#define MEMC_CHN_TIM_DRAM_CFG_DRAM_CFG_DRAMTYPE_SHIFT 0x0
+#define MEMC_CHN_TIM_DRAM_CFG_DRAM_CFG_DRAMTYPE_MASK  (0xf<<MEMC_CHN_TIM_DRAM_CFG_DRAM_CFG_DRAMTYPE_SHIFT)
+	uint32_t CHN_TIM_STAT;	/* 0x238 */
+	uint32_t unused11[49];	/* 0x23c-0x2ff */
+
+	UBUSInterface UBUSIF0;	/* 0x300-0x33f */
+	UBUSInterface UBUSIF1;	/* 0x340-0x37f */
+
+	uint32_t AXIRIF_0_CFG;	/* 0x380 */
+	uint32_t AXIRIF_0_REP_ARB_MODE;	/* 0x384 */
+#define MEMC_AXIRIF_0_REP_ARB_MODE_FIFO_MODE_SHIFT    0x0
+#define MEMC_AXIRIF_0_REP_ARB_MODE_FIFO_MODE_MASK     (0x3<<MEMC_AXIRIF_0_REP_ARB_MODE_FIFO_MODE_SHIFT)
+	uint32_t AXIRIF_0_SCRATCH;	/* 0x388 */
+	uint32_t unused12[29];	/* 0x38c-0x3ff */
+
+	uint32_t AXIWIF_0_CFG;	/* 0x400 */
+#define MEMC_AXIWIF_0_CFG_WRITE_REPLY_MODE_SHIFT      0x0
+#define MEMC_AXIWIF_0_CFG_WRITE_REPLY_MODE_MASK       (0x1<<MEMC_AXIWIF_0_CFG_WRITE_REPLY_MODE_SHIFT)
+#define MEMC_AXIWIF_0_CFG_WRITE_BURST_MODE_SHIFT      0x1
+#define MEMC_AXIWIF_0_CFG_WRITE_BURST_MODE_MASK       (0x1<<MEMC_AXIWIF_0_CFG_WRITE_BURST_MODE_SHIFT)
+	uint32_t AXIWIF_0_REP_ARB_MODE;	/* 0x404 */
+#define MEMC_AXIWIF_0_REP_ARB_MODE_FIFO_MODE_SHIFT    0x0
+#define MEMC_AXIWIF_0_REP_ARB_MODE_FIFO_MODE_MASK     (0x1<<MEMC_AXIRIF_0_REP_ARB_MODE_FIFO_MODE_SHIFT)
+
+	uint32_t AXIWIF_0_SCRATCH;	/* 0x408 */
+	uint32_t unused13[61];	/* 0x40c-0x4ff */
+
+	EDISEngine EDIS_0;	/* 0x500 */
+	EDISEngine EDIS_1;	/* 0x600 */
+
+	uint32_t STATS_CTRL;	/* 0x700 */
+	uint32_t STATS_TIMER_CFG;	/* 0x704 */
+	uint32_t STATS_TIMER_COUNT;	/* 0x708 */
+	uint32_t STATS_TOTAL_SLICE;	/* 0x70c */
+	uint32_t STATS_TOTAL_PACKET;	/* 0x710 */
+	uint32_t STATS_SLICE_REORDER;	/* 0x714 */
+	uint32_t STATS_IDLE_DDR_CYCLE;	/* 0x718 */
+	uint32_t STATS_ARB_GRANT;	/* 0x71c */
+	uint32_t STATS_PROG_0;	/* 0x720 */
+	uint32_t STATS_PROG_1;	/* 0x724 */
+	uint32_t STATS_ARB_GRANT_MATCH;	/* 0x728 */
+	uint32_t STATS_CFG_0;	/* 0x72c */
+	uint32_t STATS_CFG_1;	/* 0x730 */
+	uint32_t unused14[19];	/* 0x734-0x77f */
+
+	uint32_t CAP_CAPTURE_CFG;	/* 0x780 */
+	uint32_t CAP_TRIGGER_ADDR;	/* 0x784 */
+	uint32_t CAP_READ_CTRL;	/* 0x788 */
+	uint32_t unused15;	/* 0x78c */
+	uint32_t CAP_CAPTURE_MATCH0;	/* 0x790 */
+	uint32_t CAP_CAPTURE_MATCH1;	/* 0x794 */
+	uint32_t CAP_CAPTURE_MATCH2;	/* 0x798 */
+	uint32_t unused16;	/* 0x79c */
+	uint32_t CAP_CAPTURE_MASK0;	/* 0x7a0 */
+	uint32_t CAP_CAPTURE_MASK1;	/* 0x7a4 */
+	uint32_t CAP_CAPTURE_MASK2;	/* 0x7a8 */
+	uint32_t unused17;	/* 0x7ac */
+	uint32_t CAP_TRIGGER_MATCH0;	/* 0x7b0 */
+	uint32_t CAP_TRIGGER_MATCH1;	/* 0x7b4 */
+	uint32_t CAP_TRIGGER_MATCH2;	/* 0x7b8 */
+	uint32_t unused18;	/* 0x7bc */
+	uint32_t CAP_TRIGGER_MASK0;	/* 0x7c0 */
+	uint32_t CAP_TRIGGER_MASK1;	/* 0x7c4 */
+	uint32_t CAP_TRIGGER_MASK2;	/* 0x7c8 */
+	uint32_t unused19;	/* 0x7cc */
+	uint32_t CAP_READ_DATA[4];	/* 0x7d0-0x7dc */
+	uint32_t unused20[8];	/* 0x7e0-0x7ff */
+
+	SecureRangeCheckers SEC_RANGE_CHK;	/* 0x800 */
+
+	uint32_t SEC_INTR2_CPU_STATUS;	/* 0x900 */
+	uint32_t SEC_INTR2_CPU_SET;	/* 0x904 */
+	uint32_t SEC_INTR2_CPU_CLEAR;	/* 0x908 */
+	uint32_t SEC_INTR2_CPU_MASK_STATUS;	/* 0x90c */
+	uint32_t SEC_INTR2_CPU_MASK_SET;	/* 0x910 */
+	uint32_t SEC_INTR2_CPU_MASK_CLEAR;	/* 0x914 */
+	uint32_t unused21[10];	/* 0x918-0x93f */
+
+	uint32_t SEC_SRAM_REMAP_CTRL;	/* 0x940 */
+	uint32_t SEC_SRAM_REMAP_INIT;	/* 0x944 */
+	uint32_t SEC_SRAM_REMAP_LOG_0;	/* 0x948 */
+	uint32_t SEC_SRAM_REMAP_LOG_1;	/* 0x94c */
+	uint32_t unused22[428];	/* 0x950-0xfff */
+
+	DDRPhyControl PhyControl;	/* 0x1000 */
+	DDRPhyByteLaneControl PhyByteLane0Control;	/* 0x1400 */
+	DDRPhyByteLaneControl PhyByteLane1Control;	/* 0x1600 */
+} MEMCControl;
+
+#define MEMC ((volatile MEMCControl * const) MEMC_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/ethsw.h b/arch/arm/include/asm/arch-bcm63148/ethsw.h
new file mode 100644
index 0000000000..e6c2dc15a4
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/ethsw.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63148_ETHSW_H
+#define _63148_ETHSW_H
+
+#define SWITCH_BASE              0x80080000
+
+typedef struct {
+    uint32_t led_f;
+    uint32_t reserved;
+} LED_F;
+
+typedef struct EthernetSwitchCore
+{
+    uint32_t port_traffic_ctrl[9];            /* 0x00 - 0x08 */
+    uint32_t reserved1[2];                    /* 0x09 - 0x0a */
+    uint32_t switch_mode;                     /* 0x0b */
+#define ETHSW_SM_RETRY_LIMIT_DIS                  0x04
+#define ETHSW_SM_FORWARDING_EN                    0x02
+#define ETHSW_SM_MANAGED_MODE                     0x01
+    uint32_t pause_quanta;                    /* 0x0c */
+    uint32_t reserved33; 
+    uint32_t imp_port_state;                  /*0x0e */
+#define ETHSW_IPS_USE_MII_HW_STS                  0x00
+#define ETHSW_IPS_USE_REG_CONTENTS                0x80
+#define ETHSW_IPS_GMII_SPEED_UP_NORMAL            0x00
+#define ETHSW_IPS_GMII_SPEED_UP_2G                0x40
+#define ETHSW_IPS_TXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_TXFLOW_PAUSE_CAPABLE            0x20
+#define ETHSW_IPS_RXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_RXFLOW_PAUSE_CAPABLE            0x10
+#define ETHSW_IPS_SW_PORT_SPEED_1000M_2000M       0x08
+#define ETHSW_IPS_DUPLEX_MODE                     0x02
+#define ETHSW_IPS_LINK_FAIL                       0x00
+#define ETHSW_IPS_LINK_PASS                       0x01
+    uint32_t led_refresh;                     /* 0x0f */
+    LED_F        led_function[2];                 /* 0x10 */
+    uint32_t led_function_map;                /* 0x14 */
+    uint32_t reserved14; 
+    uint32_t led_enable_map;                  /* 0x16 */
+    uint32_t reserved15; 
+    uint32_t led_mode_map0;                   /* 0x18 */
+    uint32_t reserved16; 
+    uint32_t led_function_map1;               /* 0x1a */
+    uint32_t reserved17; 
+    uint32_t reserved2[5];                    /* 0x1c - 0x20 */
+    uint32_t port_forward_ctrl;               /* 0x21 */
+    uint32_t switch_ctrl;                     /* 0x22 */
+#define ETHSW_SC_MII_DUMP_FORWARDING_EN           0x40
+#define ETHSW_SC_MII2_VOL_SEL                     0x02
+    uint32_t reserved3;                       /* 0x23 */
+    uint32_t protected_port_selection;        /* 0x24 */
+    uint32_t reserved18; 
+    uint32_t wan_port_select;                 /* 0x26 */
+    uint32_t reserved19; 
+    uint32_t pause_capability;                /* 0x28 */
+    uint32_t reserved20[3]; 
+    uint32_t reserved4[3];                    /* 0x2c - 0x2e */
+    uint32_t reserved_multicast_control;      /* 0x2f */
+    uint32_t reserved5;                       /* 0x30 */
+    uint32_t txq_flush_mode_control;          /* 0x31 */
+    uint32_t ulf_forward_map;                 /* 0x32 */
+    uint32_t reserved21; 
+    uint32_t mlf_forward_map;                 /* 0x34 */
+    uint32_t reserved22; 
+    uint32_t mlf_impc_forward_map;            /* 0x36 */
+    uint32_t reserved23; 
+    uint32_t pause_pass_through_for_rx;       /* 0x38 */
+    uint32_t reserved24; 
+    uint32_t pause_pass_through_for_tx;       /* 0x3a */
+    uint32_t reserved25; 
+    uint32_t disable_learning;                /* 0x3c */
+    uint32_t reserved26; 
+    uint32_t reserved6[26];                   /* 0x3e - 0x57 */
+    uint32_t port_state_override[8];          /* 0x58 - 0x5f */
+#define ETHSW_PS_SW_OVERRIDE                      0x40
+#define ETHSW_PS_SW_TX_FLOW_CTRL_EN               0x20
+#define ETHSW_PS_SW_RX_FLOW_CTRL_EN               0x10
+#define ETHSW_PS_SW_PORT_SPEED_1000M              0x80
+#define ETHSW_PS_SW_PORT_SPEED_100M               0x40
+#define ETHSW_PS_SW_PORT_SPEED_10M                0x00
+#define ETHSW_PS_DUPLEX_MODE                      0x02
+#define ETHSW_PS_LINK_DOWN                        0x00
+#define ETHSW_PS_LINK_UP                          0x01
+    uint32_t reserved7[4];                    /* 0x60 - 0x63 */
+    uint32_t imp_rgmii_ctrl_p4;               /* 0x64 */
+    uint32_t imp_rgmii_ctrl_p5;               /* 0x65 */
+    uint32_t reserved8[6];                    /* 0x66 - 0x6b */
+    uint32_t rgmii_timing_delay_p4;           /* 0x6c */
+    uint32_t gmii_timing_delay_p5;            /* 0x6d */
+    uint32_t reserved9[11];                   /* 0x6e - 0x78 */
+    uint32_t software_reset;                  /* 0x79 */
+    uint32_t reserved13[6];                   /* 0x7a - 0x7f */
+    uint32_t pause_frame_detection;           /* 0x80 */
+    uint32_t reserved10[7];                   /* 0x81 - 0x87 */
+    uint32_t fast_aging_ctrl;                 /* 0x88 */
+    uint32_t fast_aging_port;                 /* 0x89 */
+    uint32_t fast_aging_vid;                  /* 0x8a */
+    uint32_t anonymous1[376];                 /* 0x8b */
+    uint32_t brcm_hdr_ctrl;                   /* 0x203 */
+    uint32_t anonymous2[0x2efc];              /* 0x204 */
+    uint32_t port_vlan_ctrl[9*2];               /* 0x3100 */
+} EthernetSwitchCore;
+
+#define PBMAP_MIPS 0x100
+
+typedef struct EthernetSwitchReg
+{
+    uint32_t switch_ctrl;                      /* 0x0000 */
+    uint32_t switch_status;                    /* 0x0004 */
+    uint32_t dir_data_write_reg;               /* 0x0008 */
+    uint32_t dir_data_read_reg;                /* 0x000c */
+    uint32_t led_serial_refresh_time_unit;     /* 0x0010 */
+    uint32_t reserved1;                        /* 0x0014 */
+    uint32_t switch_rev;                       /* 0x0018 */
+    uint32_t phy_rev;                          /* 0x001c */
+    uint32_t phy_test_ctrl;                    /* 0x0020 */
+    uint32_t qphy_ctrl;                        /* 0x0024 */
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT     12
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_MASK      (0x1f<<ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT)
+#define ETHSW_QPHY_CTRL_RESET_SHIFT          8
+#define ETHSW_QPHY_CTRL_RESET_MASK           (0x1<<ETHSW_QPHY_CTRL_RESET_SHIFT )
+#define ETHSW_QPHY_CTRL_CK25_DIS_SHIFT       7
+#define ETHSW_QPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_QPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_MASK    (0xf<<ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT)
+    uint32_t qphy_status;                      /* 0x0028 */
+    uint32_t sphy_ctrl;                        /* 0x002c */
+#define ETHSW_SPHY_CTRL_PHYAD_SHIFT          8
+#define ETHSW_SPHY_CTRL_PHYAD_MASK           (0x1f<<ETHSW_SPHY_CTRL_PHYAD_SHIFT)
+#define ETHSW_SPHY_CTRL_RESET_SHIFT          5
+#define ETHSW_SPHY_CTRL_RESET_MASK           (0x1<<ETHSW_SPHY_CTRL_RESET_SHIFT )
+#define ETHSW_SPHY_CTRL_CK25_DIS_SHIFT       4
+#define ETHSW_SPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_SPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_MASK    (0x1<<ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT)
+    uint32_t sphy_status;                      /* 0x0030 */
+    uint32_t reserved2[15];                    /* 0x0034 */
+    uint32_t rgmii_5_ctrl;                     /* 0x0070 */
+    uint32_t rgmii_5_ib_status;                /* 0x0074 */
+    uint32_t rgmii_5_rx_clk_delay_ctrl;        /* 0x0078 */
+    uint32_t rgmii_7_ctrl;                     /* 0x007c */
+    uint32_t rgmii_7_ib_status;                /* 0x0080 */
+    uint32_t rgmii_7_rx_clk_delay_ctrl;        /* 0x0084 */
+    uint32_t led_blink_rate_ctrl;              /* 0x0088 */
+    uint32_t led_serial_ctrl;                  /* 0x008c */
+    uint32_t led_ctrl[5];                      /* 0x0090 */
+#define ETHSW_LED_CTRL_SPD0_ON               0x0
+#define ETHSW_LED_CTRL_SPD0_OFF              0x1
+#define ETHSW_LED_CTRL_SPD1_ON               0x0
+#define ETHSW_LED_CTRL_SPD1_OFF              0x2
+#define ETHSW_LED_CTRL_1000M_SHIFT           6
+#define ETHSW_LED_CTRL_100M_SHIFT            4
+#define ETHSW_LED_CTRL_10M_SHIFT             2
+#define ETHSW_LED_CTRL_NOLINK_SHIFT          0
+#define ETHSW_LED_CTRL_ALL_SPEED_MASK        0xff
+#define ETHSW_LED_CTRL_SPEED_MASK            0x3
+    uint32_t reserved3[2];                     /* 0x00a4 */
+    uint32_t crossbar_switch_ctrl;             /* 0x00ac */
+    uint32_t reserved4[6];                     /* 0x00b0 */
+    uint32_t rgmii_11_ctrl;                    /* 0x00c8 */
+    uint32_t rgmii_11_ib_status;               /* 0x00cc */
+    uint32_t rgmii_11_rx_clk_delay_ctrl;       /* 0x00d0 */
+    uint32_t rgmii_12_ctrl;                    /* 0x00d4 */
+#define ETHSW_RC_MII_MODE_MASK               0x1c
+#define ETHSW_RC_EXT_RVMII                   0x10
+#define ETHSW_RC_EXT_GPHY                    0x0c
+#define ETHSW_RC_EXT_EPHY                    0x08
+#define ETHSW_RC_INT_GPHY                    0x04
+#define ETHSW_RC_INT_EPHY                    0x00
+#define ETHSW_RC_ID_MODE_DIS                 0x02
+#define ETHSW_RC_RGMII_EN                    0x01
+    uint32_t rgmii_12_ib_status;               /* 0x00d8 */
+    uint32_t rgmii_12_rx_clk_delay_ctrl;       /* 0x00dc */
+#define ETHSW_RXCLK_IDDQ                     (1<<4)
+#define ETHSW_RXCLK_BYPASS                   (1<<5)
+    uint32_t anonymous1[44];                   /* 0x00e0 */
+    uint32_t single_serdes_rev;                /* 0x0190 */ /* From here for B0 and late chip only */
+    uint32_t single_serdes_ctrl;               /* 0x0194 */
+    uint32_t single_serdes_stat;               /* 0x0198 */
+    uint32_t led_wan_ctrl;                     /* 0x019c */
+} EthernetSwitchReg;
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/misc.h b/arch/arm/include/asm/arch-bcm63148/misc.h
new file mode 100644
index 0000000000..76080c051b
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/misc.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63148_MISC_H
+#define _63148_MISC_H
+
+#define MISC_BASE                               0xfffe8180
+#define GPIO_BASE                               0xfffe8100
+
+#define MISC_STRAP_BUS                          0x04
+#define MISC_STRAP_BUS_OVERRIDE                 0x08
+
+#define MISC_STRAP_BUS_SW_RESERVE_1		(0x3 << 24)
+#define MISC_STRAP_BUS_BISR_MEM_REPAIR		(1 << 23)
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT	22
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_MASK	(1 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT)
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_100MS	(1 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT)
+#define MISC_STRAP_BUS_RESET_OUT_DELAY_50MS	(0x0 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT)
+#define MISC_STRAP_BUS_SYS_BUS_FREQ		(0x3 << 20)
+#define MISC_STRAP_BUS_A9_CORE0_BOOT		(1 << 19)
+#define MISC_STRAP_BUS_PMC_BOOT_FLASH_N		(1 << 18)
+#define MISC_STRAP_BUS_PMC_BOOT_AVS		(1 << 17)
+#define MISC_STRAP_BUS_HS_SPIM_24B_N_32B_ADDR   (1 << 16)
+#define MISC_STRAP_BUS_HS_SPIM_CLK_SLOW_N_FAST  (1 << 15)
+#define MISC_STRAP_BUS_SW_RESERVE_0		(0x7 << 12)
+#define MISC_STRAP_BUS_B15_START_SLOW_FREQ	(1 << 11)
+#define MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT       10
+#define MISC_STRAP_BUS_PMC_ROM_BOOT             (1<<MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT) /* pmc rom boot enable */
+#define MISC_STRAP_BUS_PICO_ROM_BOOT		(1 << 9)
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT		4
+#define MISC_STRAP_BUS_BOOT_SEL_MASK		(0x1f << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_OPT_MASK            (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR		(0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR_1_24MHZ	(0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR_2_54MHZ	(0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR_2_81MHZ	(0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR_4_81MHZ	(0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC		(0x1e << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE	(0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE	(0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE	(0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK	(0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE	(0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT	(0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT	(0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT	(0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT	(0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT	(0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT	(0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT	(0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_LS_SPI_SLAVE_DISABLE	(1 << 3)
+#define MISC_STRAP_BUS_PCIE1_RC_MODE		(1 << 2)
+#define MISC_STRAP_BUS_PCIE0_RC_MODE		(1 << 1)
+#define MISC_STRAP_BUS_TBUS_DISABLE		(1 << 0)
+
+#ifndef __ASSEMBLER__
+/*
+ * Misc Register Set Definitions.
+ */
+typedef struct Misc {
+#define MISC_PCIE_CTRL_CORE_SOFT_RESET_MASK     (0x3)
+	uint32_t miscPCIECtrl;	/* 0x00 */
+	uint32_t miscStrapBus;	/* 0x04 */
+	uint32_t miscStrapOverride;	/* 0x08 */
+	uint32_t miscAdsl_clock_sample;	/* 0x0c */
+	uint32_t miscRngCtrl;	/* 0x10 */
+	uint32_t miscMbox0_data;	/* 0x14 */
+	uint32_t miscMbox1_data;	/* 0x18 */
+	uint32_t miscMbox2_data;	/* 0x1c */
+	uint32_t miscMbox3_data;	/* 0x20 */
+	uint32_t miscMbox_ctrl;	/* 0x24 */
+	uint32_t miscxMIIPadCtrl[4];	/* 0x28 */
+#define MISC_XMII_PAD_MODEHV                    (1 << 6)
+#define MISC_XMII_PAD_SEL_GMII                  (1 << 4)
+#define MISC_XMII_PAD_AMP_EN                    (1 << 3)
+	uint32_t miscxMIIPullCtrl[4];	/* 0x38 */
+	uint32_t miscRBUSBridgeCtrl;	/* 0x48 */
+	uint32_t miscSGMIIFiberDetect;	/* 0x4c */
+#define MISC_SGMII_FIBER_GPIO36     (1<<0)
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+/*
+ * Gpio Controller
+ */
+typedef struct GpioControl {
+	uint32_t GPIODir[5];	/* 0x00-0x10 */
+	uint32_t GPIOio[5];	/* 0x14-0x24 */
+	uint32_t SpiSlaveCfg;	/* 0x28 */
+	uint32_t unused;		/* 0x2c */
+	uint32_t TestControl;		/* 0x30 */
+	uint32_t TestPortBlockEnMSB;	/* 0x34 */
+	uint32_t TestPortBlockEnLSB;	/* 0x38 */
+	uint32_t TestPortBlockDataMSB;	/* 0x3c */
+	uint32_t TestPortBlockDataLSB;	/* 0x40 */
+#define PINMUX_DATA_SHIFT       12
+#define PINMUX_0                0
+#define PINMUX_1                1
+#define PINMUX_2                2
+#define PINMUX_3                3
+#define PINMUX_4                4
+#define PINMUX_5                5
+#define PINMUX_6                6
+#define PINMUX_MSPI             PINMUX_0
+#define PINMUX_MSPI_SS          PINMUX_1
+#define PINMUX_PCM              PINMUX_1
+#define PINMUX_GPIO             PINMUX_5
+	uint32_t TestPortCmd;		/* 0x44 */
+#define LOAD_MUX_REG_CMD        0x21
+	uint32_t GPIOBaseMode;		/* 0x48 */
+#define GPIO_BASE_USB_LED_OVERRIDE	(1<<11)
+#define GPIO_BASE_VDSL_LED_OVERRIDE	(1<<10)
+	uint32_t DiagReadBack;		/* 0x4c */
+	uint32_t DiagReadBackHi;		/* 0x50 */
+	uint32_t GeneralPurpose;		/* 0x54 */
+} GpioControl;
+
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+// PERF
+typedef struct PerfControl {
+    uint32_t        RevID;
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xfffe8000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/otp.h b/arch/arm/include/asm/arch-bcm63148/otp.h
new file mode 100644
index 0000000000..de23d542cc
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/otp.h
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _63148_OTP_H
+#define _63148_OTP_H
+
+
+#define JTAG_OTP_BASE    0xfffebb00
+
+struct Jtag_Otp {
+    uint32_t ctrl0;       /* 0x00 */
+#define JTAG_OTP_CTRL_BYPASS_OTP_CLK        (1 << 31)
+#define JTAG_OTP_CTRL_READ_FOUT         (1 << 30)
+#define JTAG_OTP_CTRL_TESTCOL           (1 << 29)
+#define JTAG_OTP_CTRL_CPU_DEBUG_SEL     (0xf << 25)
+#define JTAG_OTP_CTRL_BURST_UART_SEL        (1 << 24)
+#define JTAG_OTP_CTRL_ACCESS_MODE       (0x2 << 22)
+#define JTAG_OTP_CTRL_PROG_EN           (1 << 21)
+#define JTAG_OTP_CTRL_DEBUG_MDE         (1 << 20)
+#define JTAG_OTP_CTRL_WRP_CONTINUE_ON_FAIL  (1 << 19)
+#define JTAG_OTP_CTRL_WRP_PROGRAM_VERIFY_FLAG   (1 << 18)
+#define JTAG_OTP_CTRL_WRP_DOUBLE_WORD       (1 << 17)
+#define JTAG_OTP_CTRL_WRP_REGC_SEL      (0x7 << 14)
+#define JTAG_OTP_CTRL_WRP_QUADFUSE      (1 << 13)
+#define JTAG_OTP_CTRL_WRP_DOUBLEFUSE        (1 << 12)
+#define JTAG_OTP_CTRL_WRP_READ4X        (1 << 11)
+#define JTAG_OTP_CTRL_WRP_READ2X        (1 << 10)
+#define JTAG_OTP_CTRL_WRP_IN_DEBUG      (1 << 9)
+#define JTAG_OTP_CTRL_COMMAND           (0x1f << 1)
+#define JTAG_OTP_CTRL_CMD_READ      (0x00 << 1)
+#define JTAG_OTP_CTRL_CMD_READBURST (0x01 << 1)
+#define JTAG_OTP_CTRL_CMD_OTP_PROG_EN   (0x02 << 1)
+#define JTAG_OTP_CTRL_CMD_OTP_PROG_DIS  (0x03 << 1)
+#define JTAG_OTP_CTRL_CMD_PRESCREEN (0x04 << 1)
+#define JTAG_OTP_CTRL_CMD_PRESCREEN_RP  (0x05 << 1)
+#define JTAG_OTP_CTRL_CMD_FLUSH     (0x06 << 1)
+#define JTAG_OTP_CTRL_CMD_NOP       (0x07 << 1)
+#define JTAG_OTP_CTRL_CMD_PROG      (0x0a << 1)
+#define JTAG_OTP_CTRL_CMD_PROG_RP   (0x0b << 1)
+#define JTAG_OTP_CTRL_CMD_PROG_OVST (0x0c << 1)
+#define JTAG_OTP_CTRL_CMD_RELOAD    (0x0d << 1)
+#define JTAG_OTP_CTRL_CMD_ERASE     (0x0e << 1)
+#define JTAG_OTP_CTRL_CMD_LOAD_RF   (0x0f << 1)
+#define JTAG_OTP_CTRL_CMD_CTRL_WR   (0x10 << 1)
+#define JTAG_OTP_CTRL_CMD_CTRL_RD   (0x11 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_HP   (0x12 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_OVST (0x13 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_VERIFY0  (0x14 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_VERIFY1  (0x15 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_FORCE0   (0x16 << 1)
+#define JTAG_OTP_CTRL_CMD_READ_FORCE1   (0x17 << 1)
+#define JTAG_OTP_CTRL_CMD_BURNING   (0x18 << 1)
+#define JTAG_OTP_CTRL_CMD_PROG_LOCK (0x19 << 1)
+#define JTAG_OTP_CTRL_CMD_PROG_TESTCOL  (0x1a << 1)
+#define JTAG_OTP_CTRL_CMD_READ_TESTCOL  (0x1b << 1)
+#define JTAG_OTP_CTRL_CMD_READ_FOUT (0x1e << 1)
+#define JTAG_OTP_CTRL_CMD_SFT_RESET (0x1f << 1)
+
+#define JTAG_OTP_CTRL_START         (1 << 0)
+    uint32_t ctrl1;       /* 0x04 */
+#define JTAG_OTP_CTRL_CPU_MODE          (1 << 0)
+    uint32_t ctrl2;       /* 0x08 */
+    uint32_t ctrl3;       /* 0x0c */
+    uint32_t ctrl4;       /* 0x10 */
+    uint32_t status0;     /* 0x14 */
+    uint32_t status1;     /* 0x18 */
+#define JTAG_OTP_STATUS_1_PROG_OK       (1 << 2)
+#define JTAG_OTP_STATUS_1_CMD_DONE      (1 << 1)
+    uint32_t status2;     /* 0x1c */
+    uint32_t status3;     /* 0x20 */
+#define OTP_SAR_DISABLE       0
+#define OTP_VDSL_DSLDISABLE   1
+#define OTP_DIS2LINE          2
+#define OTP_VDSL_DISVDSL      3
+#define OTP_VDSL_DIS6BND      4
+#define OTP_VDSL_DISRNC       5
+    uint32_t status4;     /* 0x24 */
+#define OTP_SF2_DISABLE       32
+#define OTP_PCIE_RCAL_VALID 33
+    uint32_t status5;     /* 0x28 */
+#define OTP_SPHY_DISABLE      64
+#define OTP_RNR_DISIPSEC      75
+#define OTP_RNR_DISSHA1       76
+#define OTP_RNR_DISSHA2       77
+#define OTP_PRNR_DISAES256    78
+#define OTP_PRNR_DISAES192    79
+#define OTP_PRNR_DISAES128    80
+#define OTP_USBH_DISEHCI      81
+#define OTP_USBH_XHCIDIS      82
+#define OTP_USBD_DISABLE      83
+#define OTP_PCIE_DISABLE0     84
+#define OTP_PCIE_DISABLE1     85
+#define OTP_A9_DISC1          86
+#define OTP_A9_DISNEON        87
+#define OTP_SATA_DISABLE      88
+#define OTP_DECT_DISABLE      89
+    uint32_t status6;     /* 0x2c */
+#define OTP_TBUS_DISABLE      120
+#define OTP_PMC_BOOT          121
+    uint32_t status7;     /* 0x30 */
+#define OTP_PMC_BOOTROM       132
+#define OTP_PMC_SECUREREG     133
+#define OTP_PBMU_DISABLE      134
+    uint32_t status8;     /* 0x34 */
+    uint32_t status9;     /* 0x38 */
+#define OTP_DDR_SECUREACC     211
+#define OTP_DDR_SECIRELCK     212
+#define OTP_ECC_MREPAIR_EN    217
+};
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+#define OTP_BRCM_MEK_MIV_ROW                    17
+#define OTP_BRCM_MEK_MIV_SHIFT                  7
+#define OTP_BRCM_MEK_MIV_MASK                   7
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          7
+
+/* row 24 */
+#define OTP_CUST_MFG_MRKTID_ROW                 24
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+#define OTP_CUST_OP_INUSE_ROW                   24
+#define OTP_CUST_OP_INUSE_SHIFT                 16
+#define OTP_CUST_OP_INUSE_MASK                  1
+
+/* row 25 */
+#define OTP_CUST_OP_MRKTID_ROW                  25
+#define OTP_CUST_OP_MRKTID_SHIFT                0
+#define OTP_CUST_OP_MRKTID_MASK                 0xffff
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_CUST_OP_INUSE, OTP_CUST_OP_INUSE_ROW, OTP_CUST_OP_INUSE_MASK, OTP_CUST_OP_INUSE_SHIFT, 1},				\
+}
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/pmc.h b/arch/arm/include/asm/arch-bcm63148/pmc.h
new file mode 100644
index 0000000000..ee429f441a
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/pmc.h
@@ -0,0 +1,400 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63148_PMC_H
+#define _63148_PMC_H
+
+#define PMC_BASE                               0x80400000
+#define PROC_MON_BASE                          0x80480000
+#define PMBM0_BASE                             0x804800c0
+#define PMBM1_BASE                             0x804800e0
+
+/*
+#####################################################################
+# PMC registers
+#####################################################################
+*/
+
+#define PMC_CONTROL_HOST_MBOX_IN               0x1028
+#define PMC_CONTROL_HOST_MBOX_OUT              0x102c
+
+#define PMC_DQM_BASE                           (PMC_BASE+0x1800)
+#define PMC_DQM_NOT_EMPTY_IRQ_STS              0x18
+#define PMC_DQM_QUEUE_RST                      0x1c
+#define PMC_DQM_NOT_EMPTY_STS                  0x20
+
+#define PMC_DQM_QUEUE_CNTRL_BASE               (PMC_BASE+0x1a00)
+#define PMC_DQM_QUEUE_DATA_BASE                (PMC_BASE+0x1c00)
+
+#define PMC_DQM_QUEUE_DATA_HOST_TO_PMC         0x0
+#define PMC_DQM_QUEUE_DATA_PMC_TO_HOST         0x10
+
+/*
+#####################################################################
+# PMB registers
+#####################################################################
+*/
+#define PMB_CNTRL                             0x0
+#define PMB_CNTRL_START_SHIFT                 31
+#define PMB_CNTRL_START_MASK                  (1<<PMB_CNTRL_START_SHIFT)
+#define PMB_CNTRL_TIMEOUT_ERR_SHIFT           30
+#define PMB_CNTRL_TIMEOUT_ERR_MASK            (1<<PMB_CNTRL_TIMEOUT_ERR_SHIFT)
+#define PMB_CNTRL_SLAVE_ERR_SHIFT             29
+#define PMB_CNTRL_SLAVE_ERR_MASK              (1<<PMB_CNTRL_SLAVE_ERR_SHIFT)
+#define PMB_CNTRL_BUSY_SHIFT                  28
+#define PMB_CNTRL_BUSY_MASK                   (1<<PMB_CNTRL_BUSY_SHIFT)
+#define PMB_CNTRL_CMD_SHIFT                   20
+#define PMB_CNTRL_CMD_MASK                    (0xf<<PMB_CNTRL_CMD_SHIFT)
+#define PMB_CNTRL_ADDR_SHIFT                  0
+#define PMB_CNTRL_ADDR_MASK                   (0xfffff<<PMB_CNTRL_ADDR_SHIFT)
+
+#define PMB_WR_DATA                           0x4
+#define PMB_TIMEOUT                           0x8
+#define PMB_RD_DATA                           0xc
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Power Management Control
+ */
+typedef struct PmcCtrlReg {
+	/* 0x00 */
+	uint32_t l1Irq4keMask;
+	uint32_t l1Irq4keStatus;
+	uint32_t l1IrqMipsMask;
+	uint32_t l1IrqMipsStatus;
+	/* 0x10 */
+	uint32_t l2IrqGpMask;
+	uint32_t l2IrqGpStatus;
+	uint32_t gpTmr0Ctl;
+	uint32_t gpTmr0Cnt;
+	/* 0x20 */
+	uint32_t gpTmr1Ctl;
+	uint32_t gpTmr1Cnt;
+	uint32_t hostMboxIn;
+	uint32_t hostMboxOut;
+	/* 0x30 */
+#define PMC_CTRL_GP_FLASH_BOOT_STALL                  0x00000080
+	uint32_t gpOut;
+	uint32_t gpIn;
+	uint32_t gpInIrqMask;
+	uint32_t gpInIrqStatus;
+	/* 0x40 */
+	uint32_t dmaCtrl;
+	uint32_t dmaStatus;
+	uint32_t dma0_3FifoStatus;
+	uint32_t unused0[3];	/* 0x4c-0x57 */
+	/* 0x58 */
+	uint32_t l1IrqMips1Mask;
+	uint32_t diagControl;
+	/* 0x60 */
+	uint32_t diagHigh;
+	uint32_t diagLow;
+	uint32_t badAddr;
+	uint32_t addr1WndwMask;
+	/* 0x70 */
+	uint32_t addr1WndwBaseIn;
+	uint32_t addr1WndwBaseOut;
+	uint32_t addr2WndwMask;
+	uint32_t addr2WndwBaseIn;
+	/* 0x80 */
+	uint32_t addr2WndwBaseOut;
+	uint32_t scratch;
+	uint32_t tm;
+	uint32_t softResets;
+	/* 0x90 */
+	uint32_t eb2ubusTimeout;
+	uint32_t m4keCoreStatus;
+	uint32_t gpInIrqSense;
+	uint32_t ubSlaveTimeout;
+	/* 0xa0 */
+	uint32_t diagEn;
+	uint32_t devTimeout;
+	uint32_t ubusErrorOutMask;
+	uint32_t diagCaptStopMask;
+	/* 0xb0 */
+	uint32_t revId;
+	uint32_t gpTmr2Ctl;
+	uint32_t gpTmr2Cnt;
+	uint32_t legacyMode;
+	/* 0xc0 */
+	uint32_t smisbMonitor;
+	uint32_t diagCtrl;
+	uint32_t diagStat;
+	uint32_t diagMask;
+	/* 0xd0 */
+	uint32_t diagRslt;
+	uint32_t diagCmp;
+	uint32_t diagCapt;
+	uint32_t diagCnt;
+	/* 0xe0 */
+	uint32_t diagEdgeCnt;
+	uint32_t unused1[4];	/* 0xe4-0xf3 */
+	/* 0xf4 */
+	uint32_t iopPeriphBaseAddr;
+	uint32_t lfsr;
+	uint32_t unused2;	/* 0xfc-0xff */
+} PmcCtrlReg;
+
+typedef struct PmcOutFifoReg {
+	uint32_t msgCtrl;	/* 0x00 */
+	uint32_t msgSts;	/* 0x04 */
+	uint32_t unused[14];	/* 0x08-0x3f */
+	uint32_t msgData[16];	/* 0x40-0x7c */
+} PmcOutFifoReg;
+
+typedef struct PmcInFifoReg {
+	uint32_t msgCtrl;	/* 0x00 */
+	uint32_t msgSts;	/* 0x04 */
+	uint32_t unused[13];	/* 0x08-0x3b */
+	uint32_t msgLast;	/* 0x3c */
+	uint32_t msgData[16];	/* 0x40-0x7c */
+} PmcInFifoReg;
+
+typedef struct PmcDmaReg {
+	/* 0x00 */
+	uint32_t src;
+	uint32_t dest;
+	uint32_t cmdList;
+	uint32_t lenCtl;
+	/* 0x10 */
+	uint32_t rsltSrc;
+	uint32_t rsltDest;
+	uint32_t rsltHcs;
+	uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+	/* 0x00 */
+	uint32_t bufSize;
+	uint32_t bufBase;
+	uint32_t idx2ptrIdx;
+	uint32_t idx2ptrPtr;
+	/* 0x10 */
+	uint32_t unused[2];
+	uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+	/* 0x00 */
+	uint32_t dcacheHit;
+	uint32_t dcacheMiss;
+	uint32_t icacheHit;
+	uint32_t icacheMiss;
+	/* 0x10 */
+	uint32_t instnComplete;
+	uint32_t wtbMerge;
+	uint32_t wtbNoMerge;
+	uint32_t itlbHit;
+	/* 0x20 */
+	uint32_t itlbMiss;
+	uint32_t dtlbHit;
+	uint32_t dtlbMiss;
+	uint32_t jtlbHit;
+	/* 0x30 */
+	uint32_t jtlbMiss;
+	uint32_t powerSubZone;
+	uint32_t powerMemPda;
+	uint32_t freqScalarCtrl;
+	/* 0x40 */
+	uint32_t freqScalarMask;
+} PmcPerfPowReg;
+
+typedef struct PmcDQMReg {
+	/* 0x00 */
+	uint32_t cfg;
+	uint32_t _4keLowWtmkIrqMask;
+	uint32_t mipsLowWtmkIrqMask;
+	uint32_t lowWtmkIrqMask;
+	/* 0x10 */
+	uint32_t _4keNotEmptyIrqMask;
+	uint32_t mipsNotEmptyIrqMask;
+	uint32_t notEmptyIrqSts;
+	uint32_t queueRst;
+	/* 0x20 */
+	uint32_t notEmptySts;
+	uint32_t nextAvailMask;
+	uint32_t nextAvailQueue;
+	uint32_t mips1LowWtmkIrqMask;
+	/* 0x30 */
+	uint32_t mips1NotEmptyIrqMask;
+	uint32_t autoSrcPidInsert;
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+	uint32_t cntr[10];
+	uint32_t unused[6];	/* 0x28-0x3f */
+	uint32_t cntrIrqMask;
+	uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+	uint32_t size;
+	uint32_t cfga;
+	uint32_t cfgb;
+	uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+	uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+	uint32_t qNumFull[32];
+	uint32_t qNumEmpty[32];
+	uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+typedef struct Pmc {
+	uint32_t baseReserved;	/* 0x0000 */
+	uint32_t unused0[1023];
+	PmcCtrlReg ctrl;	/* 0x1000 */
+
+	PmcOutFifoReg outFifo;	/* 0x1100 */
+	uint32_t unused1[32];	/* 0x1180-0x11ff */
+	PmcInFifoReg inFifo;	/* 0x1200 */
+	uint32_t unused2[32];	/* 0x1280-0x12ff */
+
+	PmcDmaReg dma[2];	/* 0x1300 */
+	uint32_t unused3[48];	/* 0x1340-0x13ff */
+
+	PmcTokenReg token;	/* 0x1400 */
+	uint32_t unused4[121];	/* 0x141c-0x15ff */
+
+	PmcPerfPowReg perfPower;	/* 0x1600 */
+	uint32_t unused5[47];	/* 0x1644-0x16ff */
+
+	uint32_t msgId[32];	/* 0x1700 */
+	uint32_t unused6[32];	/* 0x1780-0x17ff */
+
+	PmcDQMReg dqm;		/* 0x1800 */
+	uint32_t unused7[50];	/* 0x1838-0x18ff */
+
+	PmcCntReg hwCounter;	/* 0x1900 */
+	uint32_t unused8[46];	/* 0x1948-0x19ff */
+
+	PmcDqmQCtrlReg dqmQCtrl[32];	/* 0x1a00 */
+	PmcDqmQDataReg dqmQData[32];	/* 0x1c00 */
+	uint32_t unused9[64];	/* 0x1e00-0x1eff */
+
+	uint32_t qStatus[32];	/* 0x1f00 */
+	uint32_t unused10[32];	/* 0x1f80-0x1fff */
+
+	PmcDqmQMibReg qMib;	/* 0x2000 */
+	uint32_t unused11[1952];	/* 0x2180-0x3ffff */
+
+	uint32_t sharedMem[8192];	/* 0x4000-0xbffc */
+} Pmc;
+
+#define PMC ((volatile Pmc * const) PMC_BASE)
+
+/*
+ * Process Monitor Module
+ */
+typedef struct PMRingOscillatorControl {
+	uint32_t control;
+	uint32_t en_lo;
+	uint32_t en_mid;
+	uint32_t en_hi;
+	uint32_t idle_lo;
+	uint32_t idle_mid;
+	uint32_t idle_hi;
+} PMRingOscillatorControl;
+
+#define RCAL_0P25UM_HORZ          0
+#define RCAL_0P25UM_VERT          1
+#define RCAL_0P5UM_HORZ           2
+#define RCAL_0P5UM_VERT           3
+#define RCAL_1UM_HORZ             4
+#define RCAL_1UM_VERT             5
+#define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
+#define PMMISC_RMON_VALID_MASK    (0x1<<16)
+typedef struct PMMiscControl {
+	uint32_t gp_out;
+	uint32_t clock_select;
+	uint32_t unused[2];
+	uint32_t misc[4];
+} PMMiscControl;
+
+typedef struct PMSSBMasterControl {
+	uint32_t control;
+#define PMC_SSBM_CONTROL_SSB_START  (1<<15)
+#define PMC_SSBM_CONTROL_SSB_ADPRE  (1<<13)
+#define PMC_SSBM_CONTROL_SSB_EN     (1<<12)
+#define PMC_SSBM_CONTROL_SSB_CMD_SHIFT (10)
+#define PMC_SSBM_CONTROL_SSB_CMD_MASK  (0x3 << PMC_SSBM_CONTROL_SSB_CMD_SHIFT)
+#define PMC_SSBM_CONTROL_SSB_CMD_READ  (2)
+#define PMC_SSBM_CONTROL_SSB_CMD_WRITE (1)
+#define PMC_SSBM_CONTROL_SSB_ADDR_SHIFT   (0)
+#define PMC_SSBM_CONTROL_SSB_ADDR_MASK (0x3ff << PMC_SSBM_CONTROL_SSB_ADDR_SHIFT)
+	uint32_t wr_data;
+	uint32_t rd_data;
+} PMSSBMasterControl;
+
+typedef struct PMEctrControl {
+	uint32_t control;
+	uint32_t interval;
+	uint32_t thresh_lo;
+	uint32_t thresh_hi;
+	uint32_t count;
+} PMEctrControl;
+
+typedef struct PMBMaster {
+	uint32_t ctrl;
+#define PMC_PMBM_START     (1 << 31)
+#define PMC_PMBM_TIMEOUT   (1 << 30)
+#define PMC_PMBM_SLAVE_ERR (1 << 29)
+#define PMC_PMBM_BUSY      (1 << 28)
+#define PMC_PMBM_Read      (0 << 20)
+#define PMC_PMBM_Write     (1 << 20)
+	uint32_t wr_data;
+	uint32_t timeout;
+	uint32_t rd_data;
+	uint32_t unused[4];
+} PMBMaster;
+
+typedef struct PMAPVTMONControl {
+	uint32_t control;
+	uint32_t reserved;
+	uint32_t cfg_lo;
+	uint32_t cfg_hi;
+	uint32_t data;
+	uint32_t vref_data;
+	uint32_t unused[2];
+	uint32_t ascan_cfg;
+	uint32_t warn_temp;
+	uint32_t reset_temp;
+	uint32_t temp_value;
+	uint32_t data1_value;
+	uint32_t data2_value;
+	uint32_t data3_value;
+} PMAPVTMONControl;
+
+typedef struct PMUBUSCfg {
+	uint32_t window[8];
+	uint32_t control;
+} PMUBUSCfg;
+
+typedef struct ProcessMonitorRegs {
+	uint32_t MonitorCtrl;	/* 0x00 */
+	uint32_t unused0[7];
+	PMRingOscillatorControl ROSC;	/* 0x20 */
+	uint32_t unused1;
+	PMMiscControl Misc;	/* 0x40 */
+	PMSSBMasterControl SSBMaster;	/* 0x60 */
+	uint32_t unused2[5];
+	PMEctrControl Ectr;	/* 0x80 */
+	uint32_t unused3[11];
+	PMBMaster PMBM[2];	/* 0xc0 */
+	PMAPVTMONControl APvtmonCtrl;	/* 0x100 */
+	uint32_t unused4[9];
+	PMUBUSCfg UBUSCfg;	/* 0x160 */
+} ProcessMonitorRegs;
+
+#define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE)
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/pmc_addr.h b/arch/arm/include/asm/arch-bcm63148/pmc_addr.h
new file mode 100644
index 0000000000..7bb50b08de
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/pmc_addr.h
@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef PMC_ADDR_63148_H__
+#define PMC_ADDR_63148_H__
+
+#define PMB_BUS_MAX			2
+#define PMB_BUS_ID_SHIFT		8
+
+#define PMB_BUS_APM			1
+#define PMB_ADDR_APM			(0 | PMB_BUS_APM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_APM			5
+
+//--------- SOFT Reset bits for APM ------------------------
+#define   BPCM_APM_SRESET_HARDRST_N   0x00000040
+#define   BPCM_APM_SRESET_AUDIO_N     0x00000020
+#define   BPCM_APM_SRESET_PCM_N       0x00000010
+#define   BPCM_APM_SRESET_HVGA_N      0x00000008
+#define   BPCM_APM_SRESET_HVGB_N      0x00000004
+#define   BPCM_APM_SRESET_BMU_N       0x00000002
+#define   BPCM_APM_SRESET_200_N       0x00000001
+
+#define PMB_BUS_SWITCH			1
+#define PMB_ADDR_SWITCH			(1 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SWITCH		3
+
+#define PMB_BUS_CHIP_CLKRST		1
+#define PMB_ADDR_CHIP_CLKRST		(2 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST		0
+
+#define PMB_BUS_SATA			0
+#define PMB_ADDR_SATA			(3 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SATA			1
+
+#define PMB_BUS_URB			0
+#define PMB_ADDR_URB			(4 | PMB_BUS_URB << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_URB			1
+
+#define PMB_BUS_DECT_UBUS		0
+#define PMB_ADDR_DECT_UBUS		(5 | PMB_BUS_DECT_UBUS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_DECT_UBUS		1
+
+#define PMB_BUS_SAR			1
+#define PMB_ADDR_SAR			(6 | PMB_BUS_SAR << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SAR			1
+
+#define PMB_BUS_RDP			1
+#define PMB_ADDR_RDP			(7 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_RDP			2
+
+#define PMB_BUS_MEMC			0
+#define PMB_ADDR_MEMC			(8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC			1
+
+#define PMB_BUS_PERIPH			0
+#define PMB_ADDR_PERIPH			(9 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH		1
+
+#define PMB_BUS_SYSPLL			1
+#define PMB_ADDR_SYSPLL			(10 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL		0
+
+#define PMB_BUS_RDPPLL			1
+#define PMB_ADDR_RDPPLL			(11 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_RDPPLL		0
+
+#define PMB_BUS_B15_PLL			1
+#define PMB_ADDR_B15_PLL		(12 | PMB_BUS_B15_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_B15_PLL		0
+
+#define PMB_BUS_SYSPLL3			0
+#define PMB_ADDR_SYSPLL3		(13 | PMB_BUS_SYSPLL3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL3		0
+
+#define PMB_BUS_SYSPLL4			0
+#define PMB_ADDR_SYSPLL4		(14 | PMB_BUS_SYSPLL4 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL4		0
+
+#define PMB_BUS_PCIE0			0
+#define PMB_ADDR_PCIE0			(15 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0			1
+
+#define PMB_BUS_PCIE1			0
+#define PMB_ADDR_PCIE1			(16 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1			1
+
+#define PMB_BUS_USB30_2X		1
+#define PMB_ADDR_USB30_2X		(17 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB30_2X		4
+
+#define PMB_BUS_PSAB			0
+#define PMB_ADDR_PSAB			(18 | PMB_BUS_PSAB << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PSAB			1	// not shown in spreadsheet
+
+#define PMB_BUS_PSBC			0
+#define PMB_ADDR_PSBC			(19 | PMB_BUS_PSBC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PSBC			1	// not shown in spreadsheet
+
+#define PMB_BUS_EGPHY			0
+#define PMB_ADDR_EGPHY			(20 | PMB_BUS_EGPHY << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_EGPHY			1	// not shown in spreadsheet
+
+#define PMB_BUS_VDSL3_MIPS		0
+#define PMB_ADDR_VDSL3_MIPS		(21 | PMB_BUS_VDSL3_MIPS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_VDSL3_MIPS		1
+
+#define PMB_BUS_VDSL3_CORE		0
+#define PMB_ADDR_VDSL3_CORE		(22 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_VDSL3_CORE		3
+
+#define AFEPLL_PMB_BUS_VDSL3_CORE	0
+#define AFEPLL_PMB_ADDR_VDSL3_CORE	(23 | AFEPLL_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
+#define AFEPLL_PMB_ZONES_VDSL3_CORE	0
+
+#define UBUS_PMB_BUS_VDSL3_CORE		PMB_BUS_VDSL3_CORE
+#define UBUS_PMB_ADDR_VDSL3_CORE	(24 | UBUS_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
+#define UBUS_PMB_ZONES_VDSL3_CORE	0
+
+#define UBUS_PMB_BUS_VDSL3_MIPS		PMB_BUS_VDSL3_MIPS
+#define UBUS_PMB_ADDR_VDSL3_MIPS	(25 | UBUS_PMB_BUS_VDSL3_MIPS << PMB_BUS_ID_SHIFT)
+#define UBUS_PMB_ZONES_VDSL3_MIPS	0
+
+#define UBUS_PMB_BUS_DECT		PMB_BUS_DECT_UBUS
+#define UBUS_PMB_ADDR_DECT		(26 | UBUS_PMB_BUS_DECT << PMB_BUS_ID_SHIFT)
+#define UBUS_PMB_ZONES_DECT		0
+
+#define UBUS_PMB_BUS_ARM		PMB_BUS_URB
+#define UBUS_PMB_ADDR_ARM		(27 | UBUS_PMB_BUS_ARM << PMB_BUS_ID_SHIFT)
+#define UBUS_PMB_ZONES_ARM		0
+
+#define UBUS_PMB_BUS_DAP		PMB_BUS_URB
+#define UBUS_PMB_ADDR_DAP		(28 | UBUS_PMB_BUS_DAP << PMB_BUS_ID_SHIFT)
+#define UBUS_PMB_ZONES_DAP		0
+
+#define UBUS_CFG0_PMB_BUS_SAR		PMB_BUS_SAR
+#define UBUS_CFG0_PMB_ADDR_SAR		(29 | UBUS_CFG0_PMB_BUS_SAR << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG0_PMB_ZONES_SAR		0
+
+#define UBUS_CFG1_PMB_BUS_SAR		PMB_BUS_SAR
+#define UBUS_CFG1_PMB_ADDR_SAR		(30 | UBUS_CFG1_PMB_BUS_SAR << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG1_PMB_ZONES_SAR		0
+
+#define UBUS_CFG_PMB_BUS_DBR		PMB_BUS_RDP
+#define UBUS_CFG_PMB_ADDR_DBR		(31 | UBUS_CFG_PMB_BUS_DBR << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_DBR		0
+
+#define UBUS_CFG_PMB_BUS_RABR		PMB_BUS_RDP
+#define UBUS_CFG_PMB_ADDR_RABR		(32 | UBUS_CFG_PMB_BUS_RABR << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_RABR		0
+
+#define UBUS_CFG_PMB_BUS_RBBR		PMB_BUS_RDP
+#define UBUS_CFG_PMB_ADDR_RBBR		(33 | UBUS_CFG_PMB_BUS_RBBR << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_RBBR		0
+
+#define UBUS_CFG_PMB_BUS_APM 		PMB_BUS_APM
+#define UBUS_CFG_PMB_ADDR_APM 		(34 | UBUS_CFG_PMB_BUS_APM << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_APM 		0
+
+#define UBUS_CFG_PMB_BUS_PCIE0 		PMB_BUS_PCIE0
+#define UBUS_CFG_PMB_ADDR_PCIE0 	(35 | UBUS_CFG_PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_PCIE0 	0
+
+#define UBUS_CFG_PMB_BUS_PCIE1 		PMB_BUS_PCIE1
+#define UBUS_CFG_PMB_ADDR_PCIE1 	(36 | UBUS_CFG_PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_PCIE1 	0
+
+#define UBUS_CFG_PMB_BUS_USBH 		PMB_BUS_USB30_2X
+#define UBUS_CFG_PMB_ADDR_USBH 		(37 | UBUS_CFG_PMB_BUS_USBH << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_USBH 	0
+
+#define UBUS_CFG_PMB_BUS_USBD 		PMB_BUS_USB30_2X
+#define UBUS_CFG_PMB_ADDR_USBD 		(38 | UBUS_CFG_PMB_BUS_USBD << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_USBD 	0
+
+#define UBUS_CFG_PMB_BUS_SWITCH		PMB_BUS_SWITCH
+#define UBUS_CFG_PMB_ADDR_SWITCH	(39 | UBUS_CFG_PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_SWITCH	0
+
+#define UBUS_CFG_PMB_BUS_PERIPH		PMB_BUS_PERIPH
+#define UBUS_CFG_PMB_ADDR_PERIPH	(40 | UBUS_CFG_PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_PERIPH	0
+
+#define UBUS_CFG_PMB_BUS_SATA  		PMB_BUS_SATA
+#define UBUS_CFG_PMB_ADDR_SATA  	(41 | UBUS_CFG_PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
+#define UBUS_CFG_PMB_ZONES_SATA  	0
+
+#define PMB_BUS_B15_CPU0		0	// can't find it yet
+#define PMB_ADDR_B15_CPU0  		(42 | PMB_BUS_B15_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_B15_CPU0		1
+
+#define PMB_BUS_B15_CPU1		0	// can't find it yet
+#define PMB_ADDR_B15_CPU1  		(43 | PMB_BUS_B15_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_B15_CPU1		1
+
+#define PMB_BUS_B15_L2			0	// can't find it yet
+#define PMB_ADDR_B15_L2  		(44 | PMB_BUS_B15_L2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_B15_L2		1
+
+/* define Zone enum for each block here */
+#ifndef __ASSEMBLER__
+enum {
+	APM_Zone_Main,
+	APM_Zone_Audio,
+	APM_Zone_PCM,
+	APM_Zone_HVG,
+	APM_Zone_BMU,
+};
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm63148/pmc_drv_cfg.h
new file mode 100644
index 0000000000..bb35615e86
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/pmc_drv_cfg.h
@@ -0,0 +1,37 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_1_X
+
+#define PMC_CPU_BIG_ENDIAN   1
+#define PMC_STALL_SUPPORT    1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm63148/pmc_ll_init.h b/arch/arm/include/asm/arch-bcm63148/pmc_ll_init.h
new file mode 100644
index 0000000000..131392e718
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/pmc_ll_init.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include <asm/arch/pmc.h>
+#include <asm/arch/pmc_addr.h>
+#include <asm/arch/misc.h>
+
+#define SETLEDS(a,b,c,d)
+
+/*  *********************************************************************
+    *  This function power up any necessary modules that are controlled by
+    *  PMC for board to boot such as vdsl.
+    *  This is called when still executing in place on flash
+    ********************************************************************* */
+pmc_ll_init:
+
+	ldr	r0, =MISC_BASE	/* check if PMC ROM is enabled or not */
+	ldr	r0, [r0, #MISC_STRAP_BUS]
+	lsr	r0, #MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT
+	ands	r0, #0x1
+	beq	pmbd
+
+	SETLEDS('P','M','C','S')
+	b	pmcs
+pmbd:
+	SETLEDS('P','M','B','S')
+pmcs:
+
+	/* workaround for the high temp lock issue. no need for 148 because
+	   these setting are already in the chip */
+#if defined(CONFIG_BCM63138)
+	/* config AFE PLL */
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x5		/*  cfg[0] reg offset in PLL_BPCM_REGS */ 
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	mov	r0, #1
+	lsl	r0, #27
+	orr	r2, r1, r0
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x5		/* cfg[0] reg offset in PLL_BPCM_REGS */
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* overwrite ndiv and pdiv */
+	ldr	r2, =0x80000001
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x12		/* pdiv reg offset in PLL_BPCM_REGS */
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	ldr	r2, =0x80000030
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x11		/* ndiv reg offset in PLL_BPCM_REGS */
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+#endif
+
+	/* start AFE PLL */
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x4		 /* resets reg offset in PLL_BPCM_REGS */ 
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	orr	r2, r1, #0x3
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0x4		 /* resets reg offset in PLL_BPCM_REGS */
+	bl	 pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* wait AFE PLL to lock */
+afel:
+	mov	r0, #AFEPLL_PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xa
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Wait for AFE PLL lock: repeat read until bit 31 (AFE PLL lock bit) is set */
+	ldr	r0, =0x80000000
+	and	r1, r0
+	cmp	r1, #0		 /* if bit 31 is not one, repeat read of reg 0x1700a */
+	beq	afel
+
+	/* AFE is locked, commence LMEM init */
+	/* Enable VDSL step 0. Power on zone 0, 1 and 2 */
+	mov	r5, #0x10
+pwr_zone_vdsl:
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, r5
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	ldr	r0, =0x1d00
+	orr	r2, r0, r1
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, r5
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	add	r5, #4
+	/* zone 0 starts from 0x10 offset */
+	cmp	r5, #(0x10+4*PMB_ZONES_VDSL3_CORE)
+	bne	pwr_zone_vdsl
+
+	/* Enable VDSL step 1: initiate a read of register 0x1600a via the PMC message handler */
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xa
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable VDSL step 1: or data with 0xffffff01 and write back into 0x1600a */ 
+	ldr	r0, =0xffffff01
+	orr	r2, r0, r1
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xa
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable VDSL step 2   : initiate a read of register 0x1600c via the PMC message handler */
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xc
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable VDSL step 2   : set the bottom two bits high and rewrite back into 0x1600c */
+	mov	r0, #0x3
+	orr	r2, r0, r1
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xc
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable VDSL step 3: initiate a read of register 0x1600a via the PMC message handler */
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xa
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable VDSL step 3   : write to reg 0x1600a */
+	ldr	r0, =0xffffff03
+	orr	r2, r0, r1
+	mov	r0, #PMB_ADDR_VDSL3_CORE
+	mov	r1, #0xa
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	/* Enable PCM_BMU zones */
+	mov	r5, #0x10
+pwr_zone_apm:
+	mov	r0, #PMB_ADDR_APM
+	mov	r1, r5
+	bl	pmc_read_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	ldr	r0, =0x1d00
+	orr	r2, r0, r1
+	mov	r0, #PMB_ADDR_APM
+	mov	r1, r5
+	bl	pmc_write_bpcm_reg
+	cmp	r0, #0
+	bne	pmc_error
+
+	add	r5, #4
+	/* zone 0 starts from 0x10 offset */
+	cmp	r5, #(0x10+4*PMB_ZONES_APM)
+	bne	pwr_zone_apm
+
+	/* Move LDO reference to make it settle to the right voltage */
+	ldr	r0, =0x80100130
+	ldr	r1, [r0]
+	//set bit[15] high
+	ldr	r2, =0x8000
+	orr	r1, r2
+	str	r1, [r0]
+
+#if defined(CONFIG_BCM63138)
+	/* 63148 does not need to deassert */
+	//Wait 550usec de-assert bit[15].
+	ldr	r2, =110000
+w2:
+	sub	r2, #1
+	cmp	r2, #0
+	bne	w2
+	ldr	r1, [r0]
+	bic	r1, #0x8000
+	str	r1, [r0]
+#endif
+
+	b	pmc_done
+
+pmc_error:
+	SETLEDS('P','M','C','E')
+	mov	r0, #1
+	/* failed to power lmem? dead and stuck here */
+	b	pmc_error
+
+pmc_done:
+	SETLEDS('P','M','C','D')
+	mov	r0, #0
diff --git a/arch/arm/include/asm/arch-bcm63148/rdp.h b/arch/arm/include/asm/arch-bcm63148/rdp.h
new file mode 100644
index 0000000000..72d5302acd
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/rdp.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63148_RDP_H
+#define _63148_RDP_H
+
+#define RDP_BASE            0x80200000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/rng.h b/arch/arm/include/asm/arch-bcm63148/rng.h
new file mode 100644
index 0000000000..4a88c68a63
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63148_RNG_H
+#define _63148_RNG_H
+
+#define RNG_BASE	0xfffe8300
+
+typedef struct Rng {
+	uint32_t ctrl0;			/* 0x00 */
+	uint32_t rngSoftReset;		/* 0x04 */
+	uint32_t rbgSoftReset;		/* 0x08 */
+	uint32_t totalBitCnt;		/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;			/* 0x14 */
+	uint32_t intStatus;		/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL	(0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL	(0x1<<2)
+	uint32_t intEn;			/* 0x1c */
+	uint32_t rngFifoData;		/* 0x20 */
+	uint32_t fifoCnt;		/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS	0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS	0x33
+	uint32_t perm;			/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/timer.h b/arch/arm/include/asm/arch-bcm63148/timer.h
new file mode 100644
index 0000000000..97a503026c
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/timer.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63148_TIMER_H
+#define _63148_TIMER_H
+
+#define TIMR_BASE                               0xfffe8080
+
+#define TIMER_CLKRSTCTL                         0x2c
+#define TIMER_CLKRSTCTL_FAP1_PLL_CLKEN          (1<<11)
+#define TIMER_CLKRSTCTL_FAP2_PLL_CLKEN          (1<<15)
+#define TIMER_WD_RESET                          0x34
+#define TIMER_RESET_STATUS                      0x38
+#define TIMER_RESET_STATUS_POR                  (1 << 31)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63148/unimac.h b/arch/arm/include/asm/arch-bcm63148/unimac.h
new file mode 100644
index 0000000000..1f64d1ee88
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63148/unimac.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63148_UNIMAC_H
+#define _63148_UNIMAC_H
+
+#define UNIMAC_BASE         0x802d4000
+#define UNIMAC_CFG_BASE     UNIMAC_BASE + 0x00000000
+#define UNIMAC_MIB_BASE     UNIMAC_BASE + 0x00006000
+#define UNIMAC_TOP_BASE     UNIMAC_BASE + 0x00007800
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63158/BPCM.h b/arch/arm/include/asm/arch-bcm63158/BPCM.h
new file mode 100644
index 0000000000..069714c8a0
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63158/BPCM.h
@@ -0,0 +1,874 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t sw_strap:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+// types of PMB devices
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	struct {
+		uint32_t wan_main_rst_n:1;
+		uint32_t wan_top_bb_rst_n:1;
+		uint32_t rbus_rst_n:1;
+		uint32_t reserved1:2;
+		uint32_t core_soft_rst_n:1;
+		uint32_t i_zn_sw_init:1;
+		uint32_t reserved2:1;
+		uint32_t epon_main_rst_n:1;
+		uint32_t epon_rx_rst_n:1;
+		uint32_t epon_tx_rst_n:1;
+		uint32_t epon_core_rst_n:1;
+		uint32_t ae_rx_rclk16_sw_reset_n:1;
+		uint32_t ae_rx_rbc125_sw_reset_n:1;	/* for B0 */
+		uint32_t ae_tx_tclk16_sw_reset_n:1;	/* for B0 */
+		uint32_t ae_tx_clk125_sw_reset_n:1;
+		uint32_t gpon_main_rst_n:1;
+		uint32_t gpon_rx_rst_n:1;
+		uint32_t gpon_tx_rst_n:1;
+		uint32_t gpon_8khz_rst_n:1;
+		uint32_t ngpon_main_rst_n:1;
+		uint32_t ngpon_rx_rst_n:1;
+		uint32_t ngpon_tx_rst_n:1;
+		uint32_t ngpon_8khz_rst_n:1;
+		uint32_t reserved3:2;
+		uint32_t gpon_nco_rst_n:1;
+		uint32_t epon_rx_rclk16_sw_reset_n:1;	/* for B0 */
+		uint32_t epon_rx_rbc125_sw_reset_n:1;	/* for B0 */
+		uint32_t epon_tx_tclk16_sw_reset_n:1;	/* for B0 */
+		uint32_t epon_tx_clk125_sw_reset_n:1;	/* for B0 */
+		uint32_t reserved4:1;
+	} Bits_Wantop;
+	struct {
+		uint32_t vdsl_bpcm_early_reset:1;
+		uint32_t vdsl_bpcm_reset:1;
+		uint32_t mips_ubus_soft_reset_bpcm_reset:1;
+		uint32_t qproc_1_bpcm_reset:1;
+		uint32_t qproc_2_bpcm_reset:1;
+		uint32_t sar_bpcm_soft_reset:1;
+		uint32_t vdsl_ubus_soft_bpcm_reset:1;
+		uint32_t reserved1:1;
+		uint32_t gp:24;
+	} Bits_vdsl;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t z2_p_wan_phy_sel:3;	/* 0-2 */
+		uint32_t reserved0:1;	/* 3 */
+		uint32_t z2_switch_p3_phy_sel:3;	/* 4-6 */
+		uint32_t reserved1:1;	/* 7 */
+		uint32_t z2_switch_p4_phy_sel:3;	/* 8-10 */
+		uint32_t reserved2:1;	/* 11 */
+		uint32_t z0_mux_sel:1;	/* 12 */
+		uint32_t z1_gphy_mux_sel:1;	/* 13 */
+		uint32_t z2_gphy_mux_sel:1;	/* 14 */
+		uint32_t z2_crossbar_mux_sel:1;	/* 15 */
+		uint32_t reserved3:1;	/* 16 */
+		uint32_t z1_pda_en:1;	/* 17 */
+		uint32_t z1_ck250_clk_en:1;	/* 18 */
+		uint32_t z1_ck25_clk_dis:1;	/* 19 */
+		uint32_t reserved4:2;	/* 20-21 */
+		uint32_t z2_ck250_clk_en:1;	/* 22 */
+		uint32_t z2_ck25_clk_dis:1;	/* 23 */
+		uint32_t z2_serdes_clk_en:1;	/* 24 */
+		uint32_t z2_serdes_reset_mdioregs:1;	/* 25 */
+		uint32_t z2_sedes_reset_pll:1;	/* 26 */
+		uint32_t z2_serdes_reset:1;	/* 27 */
+		uint32_t z2_serdes_mux_sel:1;	/* 28 */
+		uint32_t reserved5:1;	/* 29 */
+		uint32_t z1_gphy_reset:1;	/* 30 */
+		uint32_t z2_gphy_reset:1;	/* 31 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t z0_mux_sel:1;	//        = r_Z0_GLOBAL_CNTL[0];
+		uint32_t reserverd_1:1;	//        unused
+		uint32_t z3_pda_en:1;	//        = r_Z0_GLOBAL_CNTL[2];
+		uint32_t rx_sys_clk_en:1;	//        = r_Z0_GLOBAL_CNTL[3];
+		uint32_t tx_sys_clk_en:1;	//         = r_Z0_GLOBAL_CNTL[4];
+		uint32_t gmii_rx_clk_en:1;	//        = r_Z0_GLOBAL_CNTL[5];
+		uint32_t gmii_tx_clk_en:1;	//        = r_Z0_GLOBAL_CNTL[6];
+		uint32_t rsrvd:25;
+	} Bits;
+	uint32_t Reg32;
+
+} BPCM_GLOBAL_CNTL_0;
+
+typedef union {
+	struct {
+		uint32_t z1_pda_en:1;	//= r_Z1_GLOBAL_CNTL[0];
+		uint32_t reserved:2;
+		uint32_t z1_ck250_clk_en:1;	//= r_Z1_GLOBAL_CNTL[3];
+		uint32_t z1_ref_clk_dis:1;	//= r_Z1_GLOBAL_CNTL[4];
+		uint32_t z1_mux_sel:1;	//= r_Z1_GLOBAL_CNTL[5];
+		uint32_t z1_gphy_reset:1;	//= r_Z1_GLOBAL_CNTL[6];
+		uint32_t z1_gphy_iddq_global_pwr:1;	//= r_Z1_GLOBAL_CNTL[7];
+		uint32_t z1_gphy_force_dll_en:1;	//= r_Z1_GLOBAL_CNTL[8];
+		uint32_t z1_gphy_ext_pwr_down:4;	//= r_Z1_GLOBAL_CNTL[12:9];
+		uint32_t z1_gphy_iddq_bias:1;	//= r_Z1_GLOBAL_CNTL[13];
+		uint32_t z1_switch_p3_phy_sel:1;	//= r_Z1_GLOBAL_CNTL[14];
+		uint32_t z1_switch_p8_sel:1;	//= r_Z1_GLOBAL_CNTL[15];
+		uint32_t rsrvd:16;
+	} Bits;
+	uint32_t Reg32;
+
+} BPCM_GLOBAL_CNTL_1;
+
+typedef union {
+	struct {
+		uint32_t z2_pda_en:1;	//= r_Z2_GLOBAL_CNTL[0];
+		uint32_t reserved:1;
+		uint32_t z2_ck250_clk_en:1;	//= r_Z2_GLOBAL_CNTL[2];
+		uint32_t z2_ref_clk_dis:1;	//= r_Z2_GLOBAL_CNTL[3];
+		uint32_t z2_serdes_clk_en:1;	//= r_Z2_GLOBAL_CNTL[4];
+		uint32_t z2_gphy_mux_sel:1;	//= r_Z2_GLOBAL_CNTL[5];
+		uint32_t z2_gphy_reset:1;	//= r_Z2_GLOBAL_CNTL[6];
+		uint32_t z2_gphy_iddq_global_pwr:1;	//= r_Z2_GLOBAL_CNTL[7];
+		uint32_t z2_gphy_force_dll_en:1;	//= r_Z2_GLOBAL_CNTL[8];
+		uint32_t z2_gphy_ext_pwr_down:1;	//= r_Z2_GLOBAL_CNTL[9];
+		uint32_t z2_gphy_iddq_bias:1;	//= r_Z2_GLOBAL_CNTL[10];
+		uint32_t z2_crossbar_mux_sel:1;	//= r_Z2_GLOBAL_CNTL[11];
+		uint32_t z2_p_wan_phy_sel:2;	//= r_Z2_GLOBAL_CNTL[13:12];
+		uint32_t z2_switch_p4_phy_sel:2;	//= r_Z2_GLOBAL_CNTL[15:14];
+		uint32_t z2_switch_p6_phy_sel:2;	//= r_Z2_GLOBAL_CNTL[17:16];
+		uint32_t z2_serdes_mux_sel:1;	//= r_Z2_GLOBAL_CNTL[18];
+		uint32_t z2_serdes_iddq:1;	//= r_Z2_GLOBAL_CNTL[19];
+		uint32_t z2_serdes_pwrdwn:1;	//= r_Z2_GLOBAL_CNTL[20];
+		uint32_t z2_serdes_reset:1;	//= r_Z2_GLOBAL_CNTL[21];
+		uint32_t z2_serdes_reset_mdioregs:1;	//= r_Z2_GLOBAL_CNTL[22];
+		uint32_t z2_serdes_reset_pll:1;	//= r_Z2_GLOBAL_CNTL[23];
+		uint32_t z2_serdes_refclk_sel:3;	//= r_Z2_GLOBAL_CNTL[26:24];
+		uint32_t z2_pll_clk125_250_sel:1;	//= r_Z2_GLOBAL_CNTL[27];
+		uint32_t z2_pll_mux_clk250_sel:1;	//= r_Z2_GLOBAL_CNTL[28];
+		uint32_t rsrvd:3;
+	} Bits;
+	uint32_t Reg32;
+
+} BPCM_GLOBAL_CNTL_2;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu_reset_n:8;	// 07:00    R/W
+		uint32_t c0l2_reset:1;	// 08:08    R/W
+		uint32_t c1l2_reset:1;	// 09:09    R/W
+		uint32_t reserved0:6;	// 15:10    R/O
+		uint32_t cpu_bpcm_init_on:8;	// 23:16    R/W
+		uint32_t c0l2_bpcm_init_on:1;	// 24:24    R/W
+		uint32_t c1l2_bpcm_init_on:1;	// 25:25    R/W
+		uint32_t ubus_sr:1;	// 26:26    R/W
+		uint32_t cci_sr:1;	// 27:27    R/W
+		uint32_t webcores_sr:1;	// 28:28    R/W
+		uint32_t hw_done:1;	// 29:29    R/O
+		uint32_t sw_done:1;	// 30:30    R/W
+		uint32_t start:1;	// 31:31    R/W
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t reserved0:2;	// 11:10
+		uint32_t ndiv_frac:20;	// 31:12    
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECNDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t reserved0:12;	// 15:04
+		uint32_t mdiv0:8;	// 23:16
+		uint32_t mdiv1:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECPDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv2:8;	// 07:00
+		uint32_t mdiv3:8;	// 15:08
+		uint32_t mdiv4:8;	// 23:16
+		uint32_t mdiv5:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECCH25_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	BPCM_ZONE_N_FREQ_SCALAR_CONTROL freq_scalar_control;
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved;	// offset = 0x2c, actual offset = 11
+	BPCM_GLOBAL_CNTL_0 global_control;	// offset = 0x30, actual offset = 12
+	BPCM_GLOBAL_CNTL_1 global_control_1;	// offset = 0x34, actual offset = 13
+	BPCM_GLOBAL_CNTL_2 global_control_2;	// offset = 0x38, actual offset = 14
+	uint32_t global_status;	// offset = 0x3c, actual offset = 15
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	uint32_t rvrsd[2];
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_VDSL_REGS;		// total offset space = 4096
+
+#define BPCMVDSLOffset(reg)	offsetof(BPCM_VDSL_REGS,reg)
+#define BPCMVDSLRegOffset(reg)	(BPCMVDSLOffset(reg) >> 2)
+
+// ARM BPCM addresses as used by 63138/63148 and possibly others (28nm)
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved;	// offset = 0x2c, actual offset = 11
+	ARM_CONTROL_REG arm_control;	// offset = 0x30, actual offset = 12
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} ARM_BPCM_REGS;
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	uint32_t decndiv;	// offset = 0x44, actual offset = 0x11
+	uint32_t decpdiv;	// offset = 0x48, actual offset = 0x12
+	uint32_t decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved1;	// offset = 0x2c, actual offset = 11
+	uint32_t clkrst_cfg;	// offset = 0x30, actual offset = 12
+	uint32_t clkrst_control;	// offset = 0x34, actual offset = 13
+	uint32_t xtal_control;	// offset = 0x38, actual offset = 14
+	uint32_t clkrst_stat;	// offset = 0x3c, actual offset = 15
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63158/brom.h b/arch/arm/include/asm/arch-bcm63158/brom.h
new file mode 100644
index 0000000000..c2e0b636fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63158/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63158_BROM_H
+#define _63158_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63158/cpu.h b/arch/arm/include/asm/arch-bcm63158/cpu.h
new file mode 100644
index 0000000000..0195036373
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63158/cpu.h
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+
+
+typedef struct CCI500_SlaveIntf {
+	#define SNOOP_CTRL_ENABLE_SNOOP            0x1
+	uint32_t snoop_ctrl;	/* 0x0 */
+	#define SHARE_OVR_SHAREABLE_OVR_SHIFT      0x0
+	#define SHARE_OVR_SHAREABLE_OVR_MASK       0x3
+	#define SHARE_OVR_SHAREABLE_OVR_NONSHR     0x2
+	#define SHARE_OVR_SHAREABLE_OVR_SHR        0x3
+	uint32_t share_ovr;	/* 0x4 */
+	uint32_t rsvd1[62];	/* 0x8 - 0xff */
+	uint32_t arqos_ovr;	/* 0x100 */
+	uint32_t awqos_ovr;	/* 0x104 */
+	uint32_t rsvd2[2];	/* 0x108 - 0x10f */
+	uint32_t qos_max_ot;	/* 0x110 */
+	uint32_t rsvd3[955];	/* 0x114 - 0xfff */
+}CCI500_SlaveIntf;
+
+typedef struct CCI500_EventCounter {
+	uint32_t sel;	/* 0x0 */
+	uint32_t data;	/* 0x4 */
+	uint32_t ctrl;	/* 0x8 */
+	uint32_t clr_ovfl;	/* 0xC */
+	uint32_t rsvd[16380];	/* 0x10 - 0xffff */
+}CCI500_EventCounter;
+
+typedef struct CCI500 {
+	#define CONTROL_OVERRIDE_SNOOP_DISABLE     0x1
+	#define CONTROL_OVERRIDE_SNOOP_FLT_DISABLE 0x4
+	uint32_t ctrl_ovr;	/* 0x0 */
+	uint32_t rsvd1;	/* 0x4 */
+	#define SECURE_ACCESS_UNSECURE_ENABLE      0x1
+	uint32_t secr_acc;	/* 0x8 */
+	uint32_t status;	/* 0xc */
+	#define STATUS_CHANGE_PENDING              0x1
+	uint32_t impr_err;	/* 0x10 */
+	uint32_t qos_threshold;	/* 0x14 */
+	uint32_t rsvd2[58];	/* 0x18 - 0xff */
+	uint32_t pmu_ctrl;	/* 0x100 */
+	#define DBG_CTRL_EN_INTF_MON               0x1
+	uint32_t debug_ctrl;	/* 0x104 */
+	uint32_t rsvd3[958];	/* 0x108 - 0xfff */
+	#define SLAVEINTF_COHERENCY_PORT           0x0
+	#define SLAVEINTF_CPU_CLUSTER              0x1
+	CCI500_SlaveIntf si[7];	/* 0x1000 - 0x7fff */
+	uint32_t rsvd4[8192];	/* 0x8000 - 0xffff */
+	CCI500_EventCounter evt_cntr[8];	/* 0x10000 - 0x8ffff */
+}CCI500;
+
+#define CCI500_BASE	0x81100000
+#define CCI500 ((volatile CCI500 * const) CCI500_BASE)
+
+typedef struct UBUS4_RANGE_CHK_CFG {
+	uint32_t control;	/* 0x0 */
+	uint32_t srcpid[8];	/* 0x4 - 0x23 */
+	uint32_t seclev;	/* 0x24 */
+	uint32_t base;		/* 0x28 */
+	uint32_t base_up;  	/* 0x2c */
+}UBUS4_RANGE_CHK_CFG;
+
+typedef struct UBUS4_RANGE_CHK_SETUP {
+	uint32_t lock;			/* 0x0 */
+	uint32_t log_inf[3];  		/* 0x4 - 0xf */
+	UBUS4_RANGE_CHK_CFG cfg[16];	/* 0x10 - 0x30f */
+}UBUS4_RANGE_CHK_SETUP;
+
+#define UBUS4_COHERENCY_PORT_BASE	0x810A0000
+#define UBUS4_RANGE_CHK_SETUP_OFFSET    0x0
+#define UBUS4_RANGE_CHK_SETUP_BASE	(UBUS4_COHERENCY_PORT_BASE+UBUS4_RANGE_CHK_SETUP_OFFSET)
+#define UBUS4_RANGE_CHK_SETUP 		((volatile UBUS4_RANGE_CHK_SETUP * const) UBUS4_RANGE_CHK_SETUP_BASE)
+
+typedef struct BIUCFG_Access {
+	uint32_t permission;	/* 0x0 */
+	uint32_t sbox;	/* 0x4 */
+	uint32_t cpu_defeature;	/* 0x8 */
+	uint32_t dbg_security;	/* 0xc */
+	uint32_t rsvd1[32];	/* 0x10 - 0x8f */
+	uint64_t violation[2];	/* 0x90 - 0x9f */
+	uint32_t ts_access[2];	/* 0xa0 - 0xa7 */
+	uint32_t rsvd2[22];	/* 0xa8 - 0xff */
+}BIUCFG_Access;
+
+typedef struct BIUCFG_Cluster {
+	uint32_t permission;	/* 0x0 */
+	uint32_t config;	/* 0x4 */
+	uint32_t status;	/* 0x8 */
+	uint32_t control;	/* 0xc */
+	uint32_t cpucfg;	/* 0x10 */
+	uint32_t dbgrom;	/* 0x14 */
+	uint32_t rsvd1[2];	/* 0x18 - 0x1f */
+	uint64_t rvbar_addr[4];	/* 0x20 - 0x3f */
+	uint32_t rsvd2[48];	/* 0x40 - 0xff */
+}BIUCFG_Cluster;
+
+typedef struct BIUCFG_Bac {
+	uint32_t bac_permission;	/* 0x00 */
+	uint32_t bac_periphbase;	/* 0x04 */
+	uint32_t rsvd[2];	/* 0x08 - 0x0f */
+	uint32_t bac_event;	/* 0x10 */
+	uint32_t rsvd_1[3];	/* 0x14 - 0x1f */
+	uint32_t bac_ccicfg;	/* 0x20 */
+	uint32_t bac_cciaddr;	/* 0x24 */
+	uint32_t rsvd_2[4];	/* 0x28 - 0x37 */
+	uint32_t bac_ccievs2;	/* 0x38 */
+	uint32_t bac_ccievs3;	/* 0x3c */
+	uint32_t bac_ccievs4;	/* 0x40 */
+	uint32_t rsvd_3[3];	/* 0x44 - 0x4f */
+	uint32_t bac_ccievm0;	/* 0x50 */
+	uint32_t bac_ccievm1;	/* 0x54 */
+	uint32_t rsvd_4[2];	/* 0x58 - 0x5f */
+	uint32_t bac_dapapbcfg;	/* 0x60 */
+	uint32_t bac_status;	/* 0x64 */
+	uint32_t rsvd_5[2];	/* 0x68 - 0x6f */
+	uint32_t cpu_therm_irq_cfg;	/* 0x70 */
+	uint32_t cpu_therm_threshold_cfg;	/* 0x74 */
+	uint32_t rsvd_6;	/* 0x78 */
+	uint32_t cpu_therm_temp;	/* 0x7c */
+	uint32_t rsvd_7[32];	/* 0x80 - 0xff */
+} BIUCFG_Bac;
+
+typedef struct BIUCFG_Aux {
+	uint32_t aux_permission;	/* 0x00 */
+	uint32_t rsvd[3];	/* 0x04 - 0x0f */
+	uint32_t c0_clk_control;	/* 0x10 */
+	uint32_t c0_clk_ramp;	/* 0x14 */
+	uint32_t c0_clk_pattern;	/* 0x18 */
+	uint32_t rsvd_1;	/* 0x1c */
+	uint32_t c1_clk_control;	/* 0x20 */
+	uint32_t c1_clk_ramp;	/* 0x24 */
+	uint32_t c1_clk_pattern;	/* 0x28 */
+	uint32_t rsvd_2[53];	/* 0x2c - 0xff */
+} BIUCFG_Aux;
+
+typedef struct BIUCFG {
+	BIUCFG_Access access;	/* 0x0 - 0xff*/
+	BIUCFG_Cluster cluster[2];	/* 0x100 - 0x2ff*/
+	BIUCFG_Bac bac;	/* 0x300 - 0x3ff */
+	uint32_t anonymous[192];	/* 0x400 - 0x6ff */
+	BIUCFG_Aux aux;	/* 0x700 - 0x7ff */
+	uint32_t anonymous_1[512];	/* 0x800 - 0xfff */
+	uint32_t TSO_CNTCR;	/* 0x1000 */
+	uint32_t anonymous_2[2047];	/* 0x1004 - 0x2fff */
+}BIUCFG;
+
+#define BIUCFG_BASE 0x81060000
+#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
+
diff --git a/arch/arm/include/asm/arch-bcm63158/ddr.h b/arch/arm/include/asm/arch-bcm63158/ddr.h
new file mode 100644
index 0000000000..c10e3987c5
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63158/ddr.h
@@ -0,0 +1,601 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63158_DDR_H
+#define _63158_DDR_H
+
+#define MEMC_BASE        0x80180000  /* DDR IO Buf Control */
+
+typedef struct UBUSInterface {
+   uint32_t CFG;                /* 0x00 */
+#define UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT   0x0
+#define UBUSIF_CFG_WRITE_REPLY_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT)
+#define UBUSIF_CFG_WRITE_BURST_MODE_SHIFT   0x1
+#define UBUSIF_CFG_WRITE_BURST_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_BURST_MODE_SHIFT)
+#define UBUSIF_CFG_INBAND_ERR_MASK_SHIFT    0x2
+#define UBUSIF_CFG_INBAND_ERR_MASK_MASK     (0x1<< UBUSIF_CFG_INBAND_ERR_MASK_SHIFT)
+#define UBUSIF_CFG_OOB_ERR_MASK_SHIFT       0x3
+#define UBUSIF_CFG_OOB_ERR_MASK_MASK        (0x1<< UBUSIF_CFG_OOB_ERR_MASK_SHIFT)
+   uint32_t ESRCID_CFG;         /* 0x04 */
+   uint32_t SRC_QUEUE_CTRL[4];  /* 0x08 - 0x17 */
+   uint32_t REP_ARB_MODE;       /* 0x18 */
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT 0x0
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_MASK  (0x1<<UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT)
+   uint32_t HPQ_CFG;            /* 0x1c */
+   uint32_t SCRATCH;            /* 0x20 */
+   uint32_t DEBUG_R0;           /* 0x24 */
+   uint32_t unused[38];         /* 0x28-0xbf */
+} UBUSInterface;
+
+typedef struct AXIInterface {
+   uint32_t CFG;              /* 0x00 */
+   uint32_t REP_ARB_MODE;     /* 0x04 */
+   uint32_t QUEUE_CFG;        /* 0x08 */
+   uint32_t ESRCID_CFG;       /* 0x0c */
+   uint32_t SRC_QUEUE_CTL[8]; /* 0x10 */
+   uint32_t SRCID4_QUEUE_CFG; /* 0x30 */
+   uint32_t SCRATCH;          /* 0x34 */
+   uint32_t AXI_DEBUG[2];         /* 0x38-0x3f */
+} AXIInterface;
+
+typedef struct EDISEngine {
+   uint32_t REV_ID;             /* 0x00 */
+   uint32_t CTRL_TRIG;          /* 0x04 */
+   uint32_t CTRL_MODE;          /* 0x08 */
+   uint32_t CTRL_SIZE;          /* 0x0c */
+   uint32_t CTRL_ADDR_START;    /* 0x10 */
+   uint32_t CTRL_ADDR_START_EXT;/* 0x14 */
+   uint32_t CTRL_ADDR_END;      /* 0x18 */
+   uint32_t CTRL_ADDR_END_EXT;  /* 0x1c */
+   uint32_t CTRL_WRITE_MASKS;   /* 0x20 */
+   uint32_t CTRL_INT_ENABLES;   /* 0x24 */
+   uint32_t unused0[6];         /* 0x28-0x3f */
+   uint32_t STAT_MAIN;          /* 0x40 */
+   uint32_t STAT_WORDS_WRITTEN; /* 0x44 */
+   uint32_t STAT_WORDS_READ;    /* 0x48 */
+   uint32_t STAT_ERROR_COUNT;   /* 0x4c */
+   uint32_t STAT_ERROR_BITS;    /* 0x50 */
+   uint32_t STAT_ADDR_LAST;     /* 0x54 */
+   uint32_t STAT_ADDR_LAST_EXT; /* 0x58 */
+   uint32_t STAT_CLOCK_CYCLES;  /* 0x5c */
+   uint32_t unused1[7];         /* 0x60-0x7b */
+   uint32_t STAT_DEBUG;         /* 0x7c */
+   uint32_t STAT_DATA_PORT[8];  /* 0x80-0x9c */
+   uint32_t GEN_LFSR_STATE[4];  /* 0xa0-0xac */
+   uint32_t GEN_CLOCK;          /* 0xb0 */
+   uint32_t GEN_PATTERN;        /* 0xb4 */
+   uint32_t unused2[2];         /* 0xb8-0xbf */
+   uint32_t BYTELANE_0_CTRL_LO; /* 0xc0 */
+   uint32_t BYTELANE_0_CTRL_HI; /* 0xc4 */
+   uint32_t BYTELANE_1_CTRL_LO; /* 0xc8 */
+   uint32_t BYTELANE_1_CTRL_HI; /* 0xcc */
+   uint32_t BYTELANE_2_CTRL_LO; /* 0xd0 */
+   uint32_t BYTELANE_2_CTRL_HI; /* 0xd4 */
+   uint32_t BYTELANE_3_CTRL_LO; /* 0xd8 */
+   uint32_t BYTELANE_3_CTRL_HI; /* 0xdc */
+   uint32_t BYTELANE_0_STAT_LO; /* 0xe0 */
+   uint32_t BYTELANE_0_STAT_HI; /* 0xe4 */
+   uint32_t BYTELANE_1_STAT_LO; /* 0xe8 */
+   uint32_t BYTELANE_1_STAT_HI; /* 0xec */
+   uint32_t BYTELANE_2_STAT_LO; /* 0xf0 */
+   uint32_t BYTELANE_2_STAT_HI; /* 0xf4 */
+   uint32_t BYTELANE_3_STAT_LO; /* 0xf8 */
+   uint32_t BYTELANE_3_STAT_HI; /* 0xfc */
+} EDISEngine;
+
+typedef struct DDRPhyControl {
+   uint32_t PRIMARY_REVISION;    /* 0x00 */
+   uint32_t SECONDARY_REVISION;  /* 0x04 */
+   uint32_t FEATURE;             /* 0x08 */
+   uint32_t PLL_STATUS;          /* 0x0c */
+   uint32_t PLL_CONFIG;          /* 0x10 */
+   uint32_t PLL_CONTROL1;        /* 0x14 */
+   uint32_t PLL_CONTROL2;        /* 0x18 */
+   uint32_t PLL_CONTROL3;        /* 0x1c */
+   uint32_t PLL_DIVIDER;         /* 0x20 */
+   uint32_t PLL_PRE_DIVIDER;     /* 0x24 */
+   uint32_t PLL_SS_EN;           /* 0x28 */
+   uint32_t PLL_SS_CFG;          /* 0x2c */
+   uint32_t AUX_CONTROL;         /* 0x30 */
+   uint32_t IDLE_PAD_CONTROL;    /* 0x34 */
+   uint32_t IDLE_PAD_EN0;        /* 0x38 */
+   uint32_t IDLE_PAD_EN1;        /* 0x3c */
+   uint32_t DRIVE_PAD_CTL;       /* 0x40 */
+   uint32_t DRIVE_PAD_CTL_2T;    /* 0x44 */
+   uint32_t DRIVE_PAD_CTL_2T_A;  /* 0x48 */
+   uint32_t STATIC_PAD_CTL;      /* 0x4c */
+   uint32_t STATIC_PAD_CTL_2T;   /* 0x50 */
+   uint32_t STATIC_PAD_CTL_2T_A; /* 0x54 */
+   uint32_t RX_TRIM;             /* 0x58 */
+   uint32_t DRAM_CFG;            /* 0x5c */
+   uint32_t DRAM_TIMING2;        /* 0x60 */
+   uint32_t DRAM_TIMING3;        /* 0x64 */
+   uint32_t VDL_REGS[45];        /* 0x68-0x11b */
+   uint32_t UPDATE_VDL;          /* 0x11c */
+   uint32_t UPDATE_VDL_SNOOP1;   /* 0x120 */
+   uint32_t UPDATE_VDL_SNOOP2;   /* 0x124 */
+   uint32_t CMND_REG1;           /* 0x128 */
+   uint32_t CMND_AUX_REG1;       /* 0x12c */
+   uint32_t CMND_REG2;           /* 0x130 */
+   uint32_t CMND_AUX_REG2;       /* 0x134 */
+   uint32_t CMND_REG3;           /* 0x138 */
+   uint32_t CMND_AUX_REG3;       /* 0x13c */
+   uint32_t CMND_REG4;           /* 0x140 */
+   uint32_t CMND_AUX_REG4;       /* 0x144 */
+   uint32_t MODE_REG[8];         /* 0x148-167 */
+   uint32_t ALERT_CLEAR;         /* 0x168 */
+   uint32_t ALERT_STATUS;        /* 0x16c */
+   uint32_t ALERT_DF1;           /* 0x170 */
+   uint32_t WRITE_LEVEL_CTRL;    /* 0x174 */
+   uint32_t WRITE_LEVEL_STATUS;  /* 0x178 */
+   uint32_t READ_EN_CTRL;        /* 0x17c */
+   uint32_t READ_EN_STATUS ;     /* 0x180 */
+   uint32_t VIRT_VTT_CTRL;       /* 0x184 */
+   uint32_t VIRT_VTT_STATUS;     /* 0x188 */
+   uint32_t VIRT_VTT_CONNECTION; /* 0x18c */
+   uint32_t VIRT_VTT_OVERRIDE;   /* 0x190 */
+   uint32_t VREF_DAC_CTRL;       /* 0x194 */
+#define DDRPHY_VREF_DAC_CTRL_PDN_SHIFT             12
+#define DDRPHY_VREF_DAC_CTRL_PDN_MASK              (0xf << DDRPHY_VREF_DAC_CTRL_PDN_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT            6
+#define DDRPHY_VREF_DAC_CTRL_DAC1_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT            0
+#define DDRPHY_VREF_DAC_CTRL_DAC0_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT)
+   uint32_t STANDBY_CTRL;        /* 0x198 */
+   uint32_t DEBUG_FREEZE_EN;     /* 0x19c */
+   uint32_t DEBUG_MUX_CTRL;      /* 0x1a0 */
+   uint32_t DFI_CTRL;            /* 0x1a4 */
+   uint32_t WRITE_ODT_CTRL;      /* 0x1a8 */
+   uint32_t ABI_PAR_CTRL;        /* 0x1ac */
+   uint32_t ZQ_CAL;              /* 0x1b0 */
+   uint32_t unused6[147];        /* 0x1b4-0x3ff */
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+   uint32_t VDL_CTRL_WR[10];     /* 0x00 - 0x27 */
+   uint32_t VDL_CTRL_RD[22];     /* 0x28 - 0x7f */
+   uint32_t VDL_CLK_CTRL;        /* 0x80 */
+   uint32_t VDL_LDE_CTRL;        /* 0x84 */
+   uint32_t RD_EN_DLY_CYC;       /* 0x88 */
+#define RD_EN_DLY_CYC_CS0_CYCLES_SHIFT      0x0
+#define RD_EN_DLY_CYC_CS0_CYCLES_MASK       (0xf<<RD_EN_DLY_CYC_CS0_CYCLES_SHIFT)
+   uint32_t WR_CHAN_DLY_CYC;     /* 0x8c */
+   uint32_t RD_CTRL;             /* 0x90 */
+   uint32_t RD_FIFO_ADDR;        /* 0x94 */
+   uint32_t RD_FIFO_DATA;        /* 0x98 */
+   uint32_t RD_FIFO_DM_DBI;      /* 0x9c */
+   uint32_t RD_FIFO_STATUS;      /* 0xa0 */
+   uint32_t RD_FIFO_CLR;         /* 0xa4 */
+   uint32_t DYNAMIC_CLK_CTRL;    /* 0xa8 */
+   uint32_t IDLE_PAD_CTRL;       /* 0xac */
+   uint32_t DRIVE_PAD_CTRL;      /* 0xb0 */
+   uint32_t DQSP_DRIVE_PAD_CTRL; /* 0xb4 */
+   uint32_t DQSN_DRIVE_PAD_CTRL; /* 0xb8 */
+   uint32_t RD_EN_DRIVE_PAD_CTRL;/* 0xbc */
+   uint32_t STATIC_PAD_CTRL;     /* 0xc0 */
+   uint32_t DQ_RX_TRIM;          /* 0xc4 */
+   uint32_t MISC_RX_TRIM;        /* 0xc8 */
+   uint32_t DQS_RX_TRIM;         /* 0xcc */
+   uint32_t WR_PREAMBLE_MODE;    /* 0xd0 */
+   uint32_t ODT_CTRL;            /* 0xd4 */
+   uint32_t LDO_CONFIG;          /* 0xd8 */
+   uint32_t CLOCK_ENABLE;        /* 0xdc */
+   uint32_t CLOCK_IDLE;          /* 0xe0 */
+   uint32_t RD_CHAN_FIFO_CLR;    /* 0xe4 */
+   uint32_t BL_SPARE_REG;        /* 0xe8 */
+   uint32_t unused[69];          /* 0xec-0x1ff */
+} DDRPhyByteLaneControl;
+
+typedef struct MEMCControl {
+   uint32_t GLB_VERS;               /* 0x000 */
+   uint32_t GLB_GCFG;               /* 0x004 */
+#define MEMC_GLB_GCFG_DRAM_EN_SHIFT        31
+#define MEMC_GLB_GCFG_DRAM_EN_MASK         (0x1<<MEMC_GLB_GCFG_DRAM_EN_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ_SHIFT      30
+#define MEMC_GLB_GCFG_FORCE_SEQ_MASK       (0x1<<MEMC_GLB_GCFG_FORCE_SEQ_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT     29
+#define MEMC_GLB_GCFG_FORCE_SEQ2_MASK      (1<<MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT)
+#define MEMC_GLB_GCFG_RBF_REORDER_SHIFT    28
+#define MEMC_GLB_GCFG_RBF_REORDER_MASK     (1<<MEMC_GLB_GCFG_RBF_REORDER_SHIFT)
+#define MEMC_GLB_GCFG_SREF_SLOW_CLK_SHIFT  26
+#define MEMC_GLB_GCFG_SREF_SLOW_CLK_MASK   (1<<MEMC_GLB_GCFG_SREF_SLOW_CLK_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT   24
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_MASK    (0x3<<MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_2X           0x0
+#define MEMC_GLB_GCFG_PHY_DFI_4X           0x1
+#define MEMC_GLB_GCFG_PHY_DFI_8X           0x2
+#define MEMC_GLB_GCFG_ALT_CHN_ARB_SHIFT    21
+#define MEMC_GLB_GCFG_ALT_CHN_ARB_MASK     (0x1<<MEMC_GLB_GCFG_ALT_CHN_ARB_SHIFT)
+#define MEMC_GLB_GCFG_DFI_EN_SHIFT         10
+#define MEMC_GLB_GCFG_DFI_EN_MASK          (0x1<<MEMC_GLB_GCFG_DFI_EN_SHIFT)
+#define MEMC_GLB_GCFG_MCLKSRC_SHIFT        9
+#define MEMC_GLB_GCFG_MCLKSRC_MASK         (0x1<<MEMC_GLB_GCFG_MCLKSRC_SHIFT)
+#define MEMC_GLB_GCFG_MEMINITDONE_SHIFT    8
+#define MEMC_GLB_GCFG_MEMINITDONE_MASK     (0x1<<MEMC_GLB_GCFG_MEMINITDONE_SHIFT)
+#define MEMC_GLB_GCFG_MRQSIZE_SHIFT        0
+#define MEMC_GLB_GCFG_MRQSIZE_MASK         (0x1f<<MEMC_GLB_GCFG_MRQSIZE_SHIFT)
+   uint32_t GLB_MRQ_CFG;            /* 0x008 */
+   uint32_t unused0;                /* 0x00c */
+   uint32_t GLB_FSBL_STATE;         /* 0x010 */
+#define MEMC_GLB_FSBL_DRAM_SIZE_SHIFT      0
+#define MEMC_GLB_FSBL_DRAM_SIZE_MASK       (0xf << MEMC_GLB_FSBL_DRAM_SIZE_SHIFT)
+   uint32_t unused1[3];             /* 0x014 - 0x01f */
+
+   uint32_t SRAM_REMAP_CTRL;        /* 0x020 */
+   uint32_t SRAM_REMAP_CTRL_UPPER;  /* 0x024 */
+   uint32_t SRAM_REMAP_INIT;        /* 0x028 */
+   uint32_t SRAM_REMAP_LOG_INFO_0;  /* 0x02c */
+   uint32_t SRAM_REMAP_LOG_INFO_1;  /* 0x030 */
+   uint32_t SRAM_REMAP_LOG_INFO_2;  /* 0x034 */
+   uint32_t unused2[2];             /* 0x038-0x03f */
+
+   uint32_t RBF_REORDER_0_CFG[16];  /* 0x040 - 0x07f */
+
+   uint32_t INTR2_CPU_STATUS;       /* 0x080 */
+   uint32_t INTR2_CPU_SET;          /* 0x084 */
+   uint32_t INTR2_CPU_CLEAR;        /* 0x088 */
+   uint32_t INTR2_CPU_MASK_STATUS;  /* 0x08c */
+   uint32_t INTR2_CPU_MASK_SET;     /* 0x090 */
+   uint32_t INTR2_CPU_MASK_CLEAR;   /* 0x094 */
+   uint32_t unused3[26];            /* 0x098-0x0ff */
+
+   uint32_t CHN_CFG_CNFG;           /* 0x100 */
+#define MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT            16
+#define MEMC_CHN_CFG_CNFG_CS_MODE_MASK             (0x3 << MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT)
+   uint32_t CHN_CFG_CSST;           /* 0x104 */
+   uint32_t unused4[2];             /* 0x108-0x10f */
+   uint32_t CHN_CFG_ROW00_0;        /* 0x110 */
+   uint32_t CHN_CFG_ROW00_1;        /* 0x114 */
+   uint32_t CHN_CFG_ROW01_0;        /* 0x118 */
+   uint32_t CHN_CFG_ROW01_1;        /* 0x11c */
+   uint32_t CHN_CFG_ROW02_0;        /* 0x120 */
+   uint32_t CHN_CFG_COL00_0;        /* 0x124 */
+   uint32_t CHN_CFG_COL00_1;        /* 0x128 */
+   uint32_t CHN_CFG_COL01_0;        /* 0x12c */
+   uint32_t CHN_CFG_COL01_1;        /* 0x130 */
+   uint32_t CHN_CFG_BNK10;          /* 0x134 */
+   uint32_t CHN_CFG_BG0;            /* 0x138 */
+   uint32_t unused5;                /* 0x13c */
+   uint32_t CHN_CFG_DRAM_SZ_CHK;    /* 0x140 */
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT  4
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_MASK   (0xf<<MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT)
+   uint32_t CHN_CFG_DIAG_SEL;       /* 0x144 */
+   uint32_t unused6[46];            /* 0x148-0x1ff */
+
+   uint32_t CHN_TIM_DCMD;           /* 0x200 */
+   uint32_t CHN_TIM_DMODE_0;        /* 0x204 */
+   uint32_t CHN_TIM_DMODE_2;        /* 0x208 */
+   uint32_t CHN_TIM_CLKS;           /* 0x20c */
+#define MEMC_CHN_TIM_CLKS_REF_RATE_SHIFT          8
+#define MEMC_CHN_TIM_CLKS_REF_DISABLE_SHIFT       31
+   uint32_t CHN_TIM_ODT;            /* 0x210 */
+   uint32_t CHN_TIM_TIM1_0;         /* 0x214 */
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tWL [31:24] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_MASK                            0xff000000
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_SHIFT                           24
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_DEFAULT                         0x00000004
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRP [23:16] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_MASK                            0x00ff0000
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_SHIFT                           16
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_DEFAULT                         0x00000006
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tCL [15:08] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_MASK                            0x0000ff00
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_SHIFT                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_DEFAULT                         0x00000005
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRCD [07:00] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_MASK                           0x000000ff
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_ALIGN                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_BITS                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_SHIFT                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_DEFAULT                        0x00000006
+
+   uint32_t CHN_TIM_TIM1_1;         /* 0x218 */
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_L [31:24] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_S [23:16] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_L [15:08] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_MASK                         0x0000ff00
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_SHIFT                        8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_S [07:00] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_MASK                         0x000000ff
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_SHIFT                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_DEFAULT                      0x00000002
+
+   uint32_t CHN_TIM_TIM1_2;         /* 0x21c */
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tFAW [31:24] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_MASK                           0xff000000
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_SHIFT                          24
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_DEFAULT                        0x00000000
+/* MC_CHN_TIM :: TIM1_2 :: reserved0 [23:16] */
+#define MC_CHN_TIM_TIM1_2_reserved0_MASK                           0x00ff0000
+#define MC_CHN_TIM_TIM1_2_reserved0_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_reserved0_BITS                           8
+#define MC_CHN_TIM_TIM1_2_reserved0_SHIFT                          16
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRTP [15:08] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_MASK                           0x0000ff00
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_SHIFT                          8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_DEFAULT                        0x00000002
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRC [07:00] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_ALIGN                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_BITS                            8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_SHIFT                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_DEFAULT                         0x00000011
+
+   uint32_t CHN_TIM_TIM1_3;         /* 0x220 */
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_L [31:24] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_S [23:16] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: reserved_for_padding0 [15:12] */
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_MASK               0x0000f000
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_ALIGN              0
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_BITS               4
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_SHIFT              12
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_L [11:08] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_MASK                          0x00000f00
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_BITS                          4
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_SHIFT                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_DEFAULT                       0x00000004
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_S [07:00] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_MASK                          0x000000ff
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_BITS                          8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_SHIFT                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_DEFAULT                       0x00000004
+
+   uint32_t CHN_TIM_TIM2;          /* 0x224 */
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2R [31:30] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_MASK                             0xc0000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_BITS                             2
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_SHIFT                            30
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2W [29:27] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_MASK                             0x38000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_SHIFT                            27
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2R [26:24] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_MASK                             0x07000000
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_SHIFT                            24
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: reserved_for_padding0 [23:22] */
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_MASK                 0x00c00000
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_ALIGN                0
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_BITS                 2
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_SHIFT                22
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2W [21:18] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_MASK                             0x003c0000
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_BITS                             4
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_SHIFT                            18
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: reserved1 [17:16] */
+#define MC_CHN_TIM_TIM2_reserved1_MASK                             0x00030000
+#define MC_CHN_TIM_TIM2_reserved1_ALIGN                            0
+#define MC_CHN_TIM_TIM2_reserved1_BITS                             2
+#define MC_CHN_TIM_TIM2_reserved1_SHIFT                            16
+/* MC_CHN_TIM :: TIM2 :: TIM2_tAL [15:12] */
+#define MC_CHN_TIM_TIM2_TIM2_tAL_MASK                              0x0000f000
+#define MC_CHN_TIM_TIM2_TIM2_tAL_ALIGN                             0
+#define MC_CHN_TIM_TIM2_TIM2_tAL_BITS                              4
+#define MC_CHN_TIM_TIM2_TIM2_tAL_SHIFT                             12
+#define MC_CHN_TIM_TIM2_TIM2_tAL_DEFAULT                           0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tRFC [11:00] */
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_MASK                             0x00000fff
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_BITS                             12
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_SHIFT                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_DEFAULT                          0x00000014
+   uint32_t unused7[2];            /* 0x228 - 0x22f */
+   uint32_t CHN_TIM_PHY_ST;         /* 0x230 */
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP       0x1
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_HW_RESET       0x2
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_SW_RESET       0x4
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_READY          0x10
+   uint32_t CHN_TIM_DRAM_CFG;       /* 0x234 */
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT           12
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_MASK            (0x1<<MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT)
+#define DRAM_CFG_DRAMSLEEP                        (1<<11)
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT     10
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_MASK      (0x1<<MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT      0
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_MASK       (0xf<<MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT)
+#define MC_DRAM_CFG_DDR3                          0x1
+#define MC_DRAM_CFG_DDR4                          0x2
+   uint32_t CHN_TIM_STAT;          /* 0x238 */
+   uint32_t CHN_TIM_PERF;          /* 0x23c */
+
+   uint32_t unused8a[7];           /* 0x240 - 0x25b */
+#define MEMC_DDR_AUTO_SELFREFRESH_EN              (1 << 31)
+#define MEMC_DDR_AUTO_SR_IDLE_CNT_MASK            (0x7FFFFFFF)
+   uint32_t CHN_TIM_AUTO_SELF_REFRESH;    /* 0x25c */
+   uint32_t CHN_TIM_AUTO_ZQCS;            /* 0x260 */
+   uint32_t CHN_TIM_TIM3;                 /* 0x264 */
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_MASK                            0x0fff0000
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_ALIGN                           0
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_BITS                            12
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_SHIFT                           16
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_DEFAULT                         0x00000100
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_ALIGN                           0
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_BITS                            8
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_SHIFT                           0
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_DEFAULT                         0x00000040
+
+   uint32_t unused8[38];                  /* 0x268-0x2ff */
+
+   uint32_t ARB_CFG;                /* 0x300 */
+   uint32_t ARB_QUE_DIS[2];         /* 0x304-0x30b */
+   uint32_t unused9;                /* 0x30c */
+   uint32_t ARB_BUCKET_CFG_CPU_WR[4]; /* 0x310-0x31f */
+   uint32_t ARB_BUCKET_CFG_CPU_RD[4]; /* 0x320-0x32f */
+   uint32_t ARB_BUCKET_CFG_CPQ_RD[4]; /* 0x330-0x33f */
+   uint32_t ARB_BUCKET_CFG_CPQ_WR[4]; /* 0x340-0x34f */
+   uint32_t ARB_BUCKET_CFG_EDIS[4]; /* 0x350-0x35f */
+   uint32_t ARB_BUCKET_CFG_UBUS[32];/* 0x360-0x3df */
+   uint32_t ARB_QUEUE_PRI[3];       /* 0x3e0-0x3eb */
+   uint32_t ARB_WRR_QUEUE_PRI;      /* 0x3ec */
+   uint32_t ARB_RATE_OK_WEIGHT[2];  /* 0x3f0-0x3f7 */
+   uint32_t ARB_RATE_FAILED_WEIGHT[2];/* 0x3f8-0x3ff */
+
+   UBUSInterface UBUSIF0;         /* 0x400-0x4bf */
+   AXIInterface AXIRIF;           /* 0x4c0-0x4ff */
+   uint32_t unused10[192];          /* 0x500-0x7ff */
+
+   EDISEngine EDIS_0;             /* 0x800 */
+   uint32_t unused11[64];           /* 0x900-0x9ff */
+
+   uint32_t STATS_CTRL;             /* 0xa00 */
+   uint32_t STATS_TIMER_CFG;        /* 0xa04 */
+   uint32_t STATS_TIMER_COUNT;      /* 0xa08 */
+   uint32_t STATS_TOTAL_SLICE;      /* 0xa0c */
+   uint32_t STATS_TOTAL_PACKET;     /* 0xa10 */
+   uint32_t STATS_TOTAL_READ_SLICE; /* 0xa14 */
+   uint32_t STATS_TOTAL_READ_PACKET;/* 0xa18 */
+   uint32_t STATS_TOTAL_LATENCY;    /* 0xa1c */
+   uint32_t STATS_MAX_LATENCY;      /* 0xa20 */
+   uint32_t STATS_SLICE_REORDER;    /* 0xa24 */
+   uint32_t STATS_TOTAL_DDR_CMD;    /* 0xa28 */
+   uint32_t STATS_TOTAL_DDR_ACT;    /* 0xa2c */
+   uint32_t STATS_TOTAL_DDR_RDWR;   /* 0xa30 */
+   uint32_t STATS_TOTAL_DDR_WRRD;   /* 0xa34 */
+   uint32_t STATS_TOTAL_MRQ_CHN_FULL;/* 0xa38 */
+   uint32_t STATS_TOTAL_SELF_REF;   /* 0xa3c */
+   uint32_t STATS_ARB_GRANT_MATCH0; /* 0xa40 */
+   uint32_t STATS_TOTAL_QUEUE_FULL; /* 0xa44 */
+   uint32_t STATS_TOTAL_ARB_GRANT;  /* 0xa48 */
+   uint32_t STATS_TOTAL_RATE_OK_GRANT;/* 0xa4c */
+   uint32_t STATS_FILTER_CFG_0;     /* 0xa50 */
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT  25
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_MASK   (0x1<<MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_EN     0x02000000
+#define MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT     16
+#define MEMC_STATS_FILTER_CFG_SRC_ID_MASK      (0x1FF<<MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_SHIFT 0
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_MASK  0x0000FFFF
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS        0x00000001
+#define MEMC_STATS_FILTER_CFG_INTF_AXI         0x00000002
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS0       0x00000004
+#define MEMC_STATS_FILTER_CFG_INTF_UNUSED      0x00000008
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS0       MEMC_STATS_FILTER_CFG_INTF_UBUS
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS1       0 // MEMC_STATS_FILTER_CFG_INTF_AXI
+#define MEMC_STATS_FILTER_CFG_INTF_MCP         MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+   uint32_t STATS_PROG0_SLICE;      /* 0xa54 */
+   uint32_t STATS_PROG0_PACKET;     /* 0xa58 */
+   uint32_t STATS_PROG0_READ_SLICE; /* 0xa5c */
+   uint32_t STATS_PROG0_READ_PACKET;/* 0xa60 */
+   uint32_t STATS_PROG0_LATENCY;    /* 0xa64 */
+   uint32_t STATS_PROG0_MAX_LATENCY;/* 0xa68 */
+   uint32_t unused12;               /* 0xa6c */
+   uint32_t STATS_FILTER_CFG_1;     /* 0xa70 */
+   uint32_t STATS_PROG1_SLICE;      /* 0xa74 */
+   uint32_t STATS_PROG1_PACKET;     /* 0xa78 */ 
+   uint32_t STATS_PROG1_READ_SLICE; /* 0xa7c */  
+   uint32_t STATS_PROG1_READ_PACKET;/* 0xa80 */
+   uint32_t STATS_PROG1_LATENCY;    /* 0xa84 */ 
+   uint32_t unused13[2];            /* 0xa88 - 0xa8c */   
+   uint32_t STATS_FILTER_CFG_2;     /* 0xa90 */
+   uint32_t STATS_PROG2_SLICE;      /* 0xa94 */
+   uint32_t STATS_PROG2_PACKET;     /* 0xa98 */ 
+   uint32_t STATS_PROG2_READ_SLICE; /* 0xa9c */  
+   uint32_t STATS_PROG2_READ_PACKET;/* 0xaa0 */
+   uint32_t STATS_PROG2_LATENCY;    /* 0xaa4 */ 
+   uint32_t unused14[2];            /* 0xaa8 - 0xaac */
+   uint32_t STATS_FILTER_CFG_3;     /* 0xab0 */
+   uint32_t STATS_PROG3_SLICE;      /* 0xab4 */
+   uint32_t STATS_PROG3_PACKET;     /* 0xab8 */ 
+   uint32_t STATS_PROG3_READ_SLICE; /* 0xabc */  
+   uint32_t STATS_PROG3_READ_PACKET;/* 0xac0 */
+   uint32_t STATS_PROG3_LATENCY;    /* 0xac4 */
+   uint32_t unused15[2];            /* 0xac8 - 0xacc */
+   uint32_t STATS_AXI_BLOCK_CPU_RD; /* 0xad0 */    
+   uint32_t STATS_AXI_BLOCK_CPQ_RD; /* 0xad4 */    
+   uint32_t unused16[10];           /* 0xad8 - 0xaff */
+
+   uint32_t CAP_CAPTURE_CFG;        /* 0xb00 */
+   uint32_t CAP_TRIGGER_ADDR;       /* 0xb04 */
+   uint32_t CAP_READ_CTRL;          /* 0xb08 */
+   uint32_t unused20;               /* 0xb0c */
+   uint32_t CAP_CAPTURE_MATCH0;     /* 0xb10 */
+   uint32_t CAP_CAPTURE_MATCH1;     /* 0xb14 */
+   uint32_t CAP_CAPTURE_MATCH2;     /* 0xb18 */
+   uint32_t unused21;               /* 0xb1c */
+   uint32_t CAP_CAPTURE_MASK0;      /* 0xb20 */
+   uint32_t CAP_CAPTURE_MASK1;      /* 0xb24 */
+   uint32_t CAP_CAPTURE_MASK2;      /* 0xb28 */
+   uint32_t unused22;               /* 0xb2c */
+   uint32_t CAP_TRIGGER_START_MATCH0;     /* 0xb30 */
+   uint32_t CAP_TRIGGER_START_MATCH1;     /* 0xb34 */
+   uint32_t CAP_TRIGGER_START_MATCH2;     /* 0xb38 */
+   uint32_t unused23;               /* 0xb3c */
+   uint32_t CAP_TRIGGER_START_MASK0;      /* 0xb40 */
+   uint32_t CAP_TRIGGER_START_MASK1;      /* 0xb44 */
+   uint32_t CAP_TRIGGER_START_MASK2;      /* 0xb48 */
+   uint32_t unused24;               /* 0xb4c */
+   uint32_t CAP_READ_DATA[8];       /* 0xb50-0xb6f */
+   uint32_t CAP_TRIGGER_STOP_MATCH0;     /* 0xb70 */
+   uint32_t CAP_TRIGGER_STOP_MATCH1;     /* 0xb74 */
+   uint32_t CAP_TRIGGER_STOP_MATCH2;     /* 0xb78 */
+   uint32_t unused25_0;                  /* 0xb7c */
+   uint32_t CAP_TRIGGER_STOP_MASK0;      /* 0xb80 */
+   uint32_t CAP_TRIGGER_STOP_MASK1;      /* 0xb84 */
+   uint32_t CAP_TRIGGER_STOP_MASK2;      /* 0xb88 */
+   uint32_t unused25_1[157];             /* 0xb8c-0xdff */
+
+   uint32_t SEC_INTR2_CPU_STATUS;   /* 0xe00 */
+   uint32_t SEC_INTR2_CPU_SET;      /* 0xe04 */
+   uint32_t SEC_INTR2_CPU_CLEAR;    /* 0xe08 */
+   uint32_t SEC_INTR2_CPU_MASK_STATUS;  /* 0xe0c */
+   uint32_t SEC_INTR2_CPU_MASK_SET;  /* 0xe10 */
+   uint32_t SEC_INTR2_CPU_MASK_CLEAR;/* 0xe14 */
+   uint32_t unused26[31866];         /* 0xe18-0x1ffff */
+
+   DDRPhyControl PhyControl;                    /* 0x20000 */
+   DDRPhyByteLaneControl PhyByteLaneControl[4]; /* 0x20400 - 0x20bff */
+} MEMCControl;
+
+#define MEMC ((volatile MEMCControl * const) MEMC_BASE)
+
+
+#endif /* _63158_DDR_H */
diff --git a/arch/arm/include/asm/arch-bcm63158/ethsw.h b/arch/arm/include/asm/arch-bcm63158/ethsw.h
new file mode 100644
index 0000000000..2a40f2dc1c
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63158/ethsw.h
@@ -0,0 +1,4849 @@
+#include <config.h>
+#include <common.h>
+#include <stdlib.h>
+
+typedef struct {
+	uint32_t led_ctrl;
+#define SPDLNK_LED1_ACT_POL_SEL_SHIFT 7
+#define SPDLNK_LED1_ACT_POL_SEL_MASK (0x1 << SPDLNK_LED1_ACT_POL_SEL_SHIFT)
+#define ACT_LED_ACT_SEL_SHIFT 5
+#define ACT_LED_ACT_SEL_MASK (0x1 << ACT_LED_ACT_SEL_SHIFT)
+#define SPDLNK_LED0_ACT_SEL_SHIFT 2
+#define SPDLNK_LED0_ACT_SEL_MASK (0x1 << SPDLNK_LED0_ACT_SEL_SHIFT)
+#define RESERVED0_SHIFT 16
+#define RESERVED0_MASK (0xffff << RESERVED0_SHIFT)
+#define SPDLNK_LED0_ACT_POL_SEL_SHIFT 6
+#define SPDLNK_LED0_ACT_POL_SEL_MASK (0x1 << SPDLNK_LED0_ACT_POL_SEL_SHIFT)
+#define AGGREGATE_LED_CNTRL_RESERVED0_SHIFT 19
+#define AGGREGATE_LED_CNTRL_RESERVED0_MASK (0x1fff << AGGREGATE_LED_CNTRL_RESERVED0_SHIFT)
+#define AGGREGATE_LED_CNTRL_ACT_POL_SEL_SHIFT 17
+#define AGGREGATE_LED_CNTRL_ACT_POL_SEL_MASK (0x1 << AGGREGATE_LED_CNTRL_ACT_POL_SEL_SHIFT)
+#define SPDLNK_LED2_ACT_SEL_SHIFT 4
+#define SPDLNK_LED2_ACT_SEL_MASK (0x1 << SPDLNK_LED2_ACT_SEL_SHIFT)
+#define LED_SPD_OVRD_SHIFT 10
+#define LED_SPD_OVRD_MASK (0x7 << LED_SPD_OVRD_SHIFT)
+#define SPDLNK_LED2_ACT_POL_SEL_SHIFT 8
+#define SPDLNK_LED2_ACT_POL_SEL_MASK (0x1 << SPDLNK_LED2_ACT_POL_SEL_SHIFT)
+#define SPD_OVRD_EN_SHIFT 14
+#define SPD_OVRD_EN_MASK (0x1 << SPD_OVRD_EN_SHIFT)
+#define TX_ACT_EN_SHIFT 1
+#define TX_ACT_EN_MASK (0x1 << TX_ACT_EN_SHIFT)
+#define AGGREGATE_LED_CNTRL_ACT_SEL_SHIFT 16
+#define AGGREGATE_LED_CNTRL_ACT_SEL_MASK (0x1 << AGGREGATE_LED_CNTRL_ACT_SEL_SHIFT)
+#define LNK_STATUS_OVRD_SHIFT 13
+#define LNK_STATUS_OVRD_MASK (0x1 << LNK_STATUS_OVRD_SHIFT)
+#define RX_ACT_EN_SHIFT 0
+#define RX_ACT_EN_MASK (0x1 << RX_ACT_EN_SHIFT)
+#define AGGREGATE_LED_CNTRL_LNK_POL_SEL_SHIFT 18
+#define AGGREGATE_LED_CNTRL_LNK_POL_SEL_MASK (0x1 << AGGREGATE_LED_CNTRL_LNK_POL_SEL_SHIFT)
+#define SPDLNK_LED1_ACT_SEL_SHIFT 3
+#define SPDLNK_LED1_ACT_SEL_MASK (0x1 << SPDLNK_LED1_ACT_SEL_SHIFT)
+#define ACT_LED_POL_SEL_SHIFT 9
+#define ACT_LED_POL_SEL_MASK (0x1 << ACT_LED_POL_SEL_SHIFT)
+#define LNK_OVRD_EN_SHIFT 15
+#define LNK_OVRD_EN_MASK (0x1 << LNK_OVRD_EN_SHIFT)
+#define AGGREGATE_LED_CNTRL_PORT_EN_SHIFT 0
+#define AGGREGATE_LED_CNTRL_PORT_EN_MASK (0xffff << AGGREGATE_LED_CNTRL_PORT_EN_SHIFT)
+	uint32_t led_encoding_sel;
+	uint32_t led_encoding;
+#define LINK_AND_SPEED_ENCODING_M10G_ENCODE_SHIFT 15
+#define LINK_AND_SPEED_ENCODING_M10G_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M10G_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_SHIFT 3
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_SHIFT 6
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_SHIFT 15
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M10_ENCODE_SHIFT 3
+#define LINK_AND_SPEED_ENCODING_M10_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M10_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M1000_ENCODE_SHIFT 9
+#define LINK_AND_SPEED_ENCODING_M1000_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M1000_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_SHIFT 12
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M100_ENCODE_SHIFT 6
+#define LINK_AND_SPEED_ENCODING_M100_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M100_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_SHIFT 9
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M2500_ENCODE_SHIFT 12
+#define LINK_AND_SPEED_ENCODING_M2500_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M2500_ENCODE_SHIFT)
+
+}LED_CFG;
+
+typedef struct EthernetSwitchReg
+{
+	uint32_t switch_ctrl;                      /* 0x0000 */
+	uint32_t switch_status;                    /* 0x0004 */
+	uint32_t dir_data_write_reg;               /* 0x0008 */
+	uint32_t dir_data_read_reg;                /* 0x000c */
+	uint32_t switch_rev;                       /* 0x0010 */
+	uint32_t phy_rev;                          /* 0x0014 */
+	uint32_t phy_test_ctrl;                    /* 0x0018 */
+	uint32_t qphy_ctrl;                        /* 0x001c */
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT     12
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_MASK      (0x1f<<ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT)
+#define ETHSW_QPHY_CTRL_RESET_SHIFT          8
+#define ETHSW_QPHY_CTRL_RESET_MASK           (0x1<<ETHSW_QPHY_CTRL_RESET_SHIFT )
+#define ETHSW_QPHY_CTRL_CK25_DIS_SHIFT       7
+#define ETHSW_QPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_QPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_MASK    (0xf<<ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      6
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+
+
+	uint32_t qphy_status;                      /* 0x0020 */
+	uint32_t sphy_ctrl;                        /* 0x0024 */
+#define ETHSW_SPHY_CTRL_PHYAD_SHIFT          8
+#define ETHSW_SPHY_CTRL_PHYAD_MASK           (0x1f<<ETHSW_SPHY_CTRL_PHYAD_SHIFT)
+#define ETHSW_SPHY_CTRL_RESET_SHIFT          5
+#define ETHSW_SPHY_CTRL_RESET_MASK           (0x1<<ETHSW_SPHY_CTRL_RESET_SHIFT )
+#define ETHSW_SPHY_CTRL_CK25_DIS_SHIFT       4
+#define ETHSW_SPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_SPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_MASK    (0x1<<ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      3
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+	uint32_t sphy_status;                      /* 0x0028 */
+	uint32_t switch_phy_intr_ctrl;             /* 0x002c */
+	uint32_t reserved2[4];                     /* 0x0030 - 0x003f */
+LED_CFG led_ctrl[9];                     /* 0x0040 - 0x00ab */
+LED_CFG led_wan_ctrl;                    /* 0x00ac - 0x00b7 */
+#define ETHSW_LED_CTRL_SPD0_ON               0x0
+#define ETHSW_LED_CTRL_SPD0_OFF              0x1
+#define ETHSW_LED_CTRL_SPD1_ON               0x0
+#define ETHSW_LED_CTRL_SPD1_OFF              0x2
+#define ETHSW_LED_CTRL_1000M_SHIFT           9
+#define ETHSW_LED_CTRL_100M_SHIFT            6
+#define ETHSW_LED_CTRL_10M_SHIFT             3
+#define ETHSW_LED_CTRL_NOLINK_SHIFT          0
+#define ETHSW_LED_CTRL_ALL_SPEED_MASK        0x3ffff
+#define ETHSW_LED_CTRL_SPEED_MASK            0x7
+	uint32_t led_blink_rate_ctrl;              /* 0x00b8 */
+	uint32_t led_serial_ctrl;                  /* 0x00bc */
+	uint32_t led_refresh_period_ctrl;          /* 0x00c0 */
+	uint32_t aggregate_led_ctrl;               /* 0x00c4 */
+#define ETHSW_AGGREGATE_LED_CTRL_PORT_EN_MASK            0xffff
+#define ETHSW_AGGREGATE_LED_CTRL_ACT_SEL_MASK            0x10000
+#define ETHSW_AGGREGATE_LED_CTRL_ACT_POL_SEL_MASK        0x20000
+#define ETHSW_AGGREGATE_LED_CTRL_LNK_POL_SEL_MASK        0x40000
+	uint32_t aggregate_blink_rate_ctrl;        /* 0x00c8 */
+#define ETHSW_QGPHY3_LED_OVRD_SHIFT           29 /*0x1c*/
+#define ETHSW_QGPHY3_LED_OVRD_MASK            (1 << ETHSW_QGPHY3_LED_OVRD_SHIFT)
+	uint32_t crossbar_switch_ctrl;             /* 0x00cc */
+	uint32_t reserved4[34];                    /* 0x00d0 - 0x0157 */
+	uint32_t rgmii_11_ctrl;                    /* 0x0158 */
+	uint32_t rgmii_11_ib_status;               /* 0x015c */
+	uint32_t rgmii_11_rx_clk_delay_ctrl;       /* 0x0160 */
+
+	uint32_t rgmii_12_ctrl;                    /* 0x0164 */
+	uint32_t rgmii_12_ib_status;               /* 0x0168 */
+	uint32_t rgmii_12_rx_clk_delay_ctrl;       /* 0x016c */
+
+	uint32_t rgmii_13_ctrl;                    /* 0x0170 */
+#define ETHSW_RC_MII_MODE_MASK               0x1c
+#define ETHSW_RC_EXT_RVMII                   0x10
+#define ETHSW_RC_EXT_GPHY                    0x0c
+#define ETHSW_RC_EXT_EPHY                    0x08
+#define ETHSW_RC_INT_GPHY                    0x04
+#define ETHSW_RC_INT_EPHY                    0x00
+#define ETHSW_RC_ID_MODE_DIS                 0x02
+#define ETHSW_RC_RGMII_EN                    0x01
+	uint32_t rgmii_13_ib_status;               /* 0x0174 */
+	uint32_t rgmii_13_rx_clk_delay_ctrl;       /* 0x0178 */
+#define ETHSW_RXCLK_IDDQ                     (1<<4)
+#define ETHSW_RXCLK_BYPASS                   (1<<5)
+	uint32_t anonymous1[169];                  /* 0x017c - 0x041f*/
+	uint32_t single_serdes_rev;                /* 0x0420 */
+	uint32_t single_serdes_ctrl;               /* 0x0424 */
+	uint32_t single_serdes_stat;               /* 0x0428 */
+	uint32_t single_serdes_apd_ctrl;           /* 0x042c */
+	uint32_t single_serdes_apd_fsm_ctrl;       /* 0x0430 */
+	uint32_t spare_ctrl;                       /* 0x0434 */
+	uint32_t moca_bp_p_wan;                    /* 0x0438 */
+	uint32_t moca_bp_p[8];                     /* 0x043c - 0x0458 only p3, p4, p6 are valid */
+} EthernetSwitchReg;
+
+typedef struct EthernetSwitchCore
+{
+	uint64_t port_traffic_ctrl[9];
+	uint8_t dummy1[8];
+	uint64_t SWITCH_CORE_RX_GLOBAL_CTL;
+#define ETHSW_SM_RETRY_LIMIT_DIS                  0x04
+#define ETHSW_SM_FORWARDING_EN                    0x02
+#define ETHSW_SM_MANAGED_MODE                     0x01
+	uint32_t switch_mode;
+	uint8_t dummy2[148];
+	uint32_t SWITCH_CORE_DEBUG_REG;
+	uint8_t dummy3[20];
+	uint64_t SWITCH_CORE_NEW_CTRL;
+	uint32_t switch_ctrl;
+#define ETHSW_SC_MII_DUMP_FORWARDING_EN           0x40
+#define ETHSW_SC_MII2_VOL_SEL                     0x02
+#if 1
+	uint8_t dummy4[12];
+	uint32_t SWITCH_CORE_PROTECTED_SEL;
+	uint8_t dummy5[12];
+	uint32_t SWITCH_CORE_WAN_PORT_SEL;
+	uint8_t dummy6[68];
+	uint32_t SWITCH_CORE_RSV_MCAST_CTRL;
+	uint8_t dummy7[12];
+	uint64_t SWITCH_CORE_TXQ_FLUSH_MODE;
+	uint32_t SWITCH_CORE_ULF_DROP_MAP;
+	uint8_t dummy8[12];
+	uint32_t SWITCH_CORE_MLF_DROP_MAP;
+	uint8_t dummy9[12];
+	uint32_t SWITCH_CORE_MLF_IPMC_FWD_MAP;
+	uint8_t dummy10[12];
+	uint32_t SWITCH_CORE_RX_PAUSE_PASS;
+	uint8_t dummy11[12];
+	uint32_t SWITCH_CORE_TX_PAUSE_PASS;
+	uint8_t dummy12[12];
+	uint32_t SWITCH_CORE_DIS_LEARN;
+	uint8_t dummy13[12];
+	uint32_t SWITCH_CORE_SFT_LRN_CTL;
+	uint8_t dummy14[12];
+	uint32_t SWITCH_CORE_LOW_POWER_EXP1;
+	uint8_t dummy15[156];
+	uint32_t SWITCH_CORE_CTLREG_REG_SPARE;
+	uint8_t dummy16[292];
+	uint64_t software_reset;
+	uint32_t SWITCH_CORE_WATCH_DOG_RPT1;
+	uint8_t dummy17[12];
+	uint32_t SWITCH_CORE_WATCH_DOG_RPT2;
+	uint8_t dummy18[12];
+	uint32_t SWITCH_CORE_WATCH_DOG_RPT3;
+	uint8_t dummy19[12];
+	uint64_t SWITCH_CORE_PAUSE_FRM_CTRL;
+	uint32_t SWITCH_CORE_PAUSE_ST_ADDR;
+	uint8_t dummy20[52];
+	uint64_t SWITCH_CORE_FAST_AGE_CTRL;
+	uint64_t SWITCH_CORE_FAST_AGE_PORT;
+	uint32_t SWITCH_CORE_FAST_AGE_VID;
+	uint8_t dummy21[668];
+	uint32_t SWITCH_CORE_LOW_POWER_CTRL;
+	uint8_t dummy22[76];
+	uint32_t SWITCH_CORE_TCAM_CTRL;
+	uint8_t dummy23[12];
+	uint32_t SWITCH_CORE_TCAM_CHKSUM_STS;
+	uint8_t dummy24[12];
+	uint32_t SWITCH_CORE_LIGHTSTACK_CTRL;
+	uint8_t dummy25[156];
+	uint32_t SWITCH_CORE_LNKSTS;
+	uint8_t dummy26[12];
+	uint32_t SWITCH_CORE_LNKSTSCHG;
+	uint8_t dummy27[12];
+	uint32_t SWITCH_CORE_SPDSTS;
+	uint8_t dummy28[28];
+	uint32_t SWITCH_CORE_DUPSTS;
+	uint8_t dummy29[12];
+	uint32_t SWITCH_CORE_PAUSESTS;
+	uint8_t dummy30[28];
+	uint32_t SWITCH_CORE_SRCADRCHG;
+	uint8_t dummy31[12];
+	uint32_t SWITCH_CORE_LSA_PORT_P0;
+	uint8_t dummy32[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P1;
+	uint8_t dummy33[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P2;
+	uint8_t dummy34[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P3;
+	uint8_t dummy35[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P4;
+	uint8_t dummy36[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P5;
+	uint8_t dummy37[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P6;
+	uint8_t dummy38[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P7;
+	uint8_t dummy39[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P8;
+	uint8_t dummy40[44];
+	uint32_t SWITCH_CORE_BIST_STS0;
+	uint8_t dummy41[44];
+	uint32_t SWITCH_CORE_BIST_STS1;
+	uint8_t dummy42[28];
+	uint32_t SWITCH_CORE_PBPTRFIFO_0;
+	uint8_t dummy43[44];
+	uint32_t SWITCH_CORE_PBPTRFIFO_1;
+	uint8_t dummy44[460];
+	uint32_t SWITCH_CORE_RESET_STATUS;
+	uint8_t dummy45[124];
+	uint32_t SWITCH_CORE_STREG_REG_SPARE0;
+	uint8_t dummy46[28];
+	uint32_t SWITCH_CORE_STREG_REG_SPARE1;
+	uint8_t dummy47[732];
+	uint64_t SWITCH_CORE_GMNGCFG;
+	uint64_t SWITCH_CORE_IMP0_PRT_ID;
+	uint64_t SWITCH_CORE_IMP1_PRT_ID;
+#endif
+	uint32_t brcm_hdr_ctrl; //0x1118
+#if 1
+	uint8_t dummy48[20];
+	uint32_t SWITCH_CORE_SPTAGT;
+	uint8_t dummy49[28];
+	uint32_t SWITCH_CORE_BRCM_HDR_CTRL2;
+	uint8_t dummy50[12];
+	uint32_t SWITCH_CORE_IPG_SHRNK_CTRL;
+	uint8_t dummy51[28];
+	uint32_t SWITCH_CORE_MIRCAPCTL;
+	uint8_t dummy52[12];
+	uint32_t SWITCH_CORE_IGMIRCTL;
+	uint8_t dummy53[12];
+	uint32_t SWITCH_CORE_IGMIRDIV;
+	uint8_t dummy54[12];
+	uint32_t SWITCH_CORE_IGMIRMAC;
+	uint8_t dummy55[44];
+	uint32_t SWITCH_CORE_EGMIRCTL;
+	uint8_t dummy56[12];
+	uint32_t SWITCH_CORE_EGMIRDIV;
+	uint8_t dummy57[12];
+	uint32_t SWITCH_CORE_EGMIRMAC;
+	uint8_t dummy58[44];
+	uint32_t SWITCH_CORE_SPANCTL;
+	uint8_t dummy59[28];
+	uint32_t SWITCH_CORE_RSPANVLAN;
+	uint8_t dummy60[300];
+	uint32_t SWITCH_CORE_HL_PRTC_CTRL;
+	uint8_t dummy61[28];
+	uint32_t SWITCH_CORE_RST_MIB_CNT_EN;
+	uint8_t dummy62[28];
+	uint32_t SWITCH_CORE_IPG_SHRINK_2G_WA;
+	uint8_t dummy63[60];
+	uint32_t SWITCH_CORE_BRCM_HDR_RX_DIS;
+	uint8_t dummy64[12];
+	uint32_t SWITCH_CORE_BRCM_HDR_TX_DIS;
+	uint8_t dummy65[108];
+	uint32_t SWITCH_CORE_MNGMODE_REG_SPARE0;
+	uint8_t dummy66[28];
+	uint32_t SWITCH_CORE_MNGMODE_REG_SPARE1;
+	uint8_t dummy67[1116];
+	uint32_t SWITCH_CORE_INT_STS;
+	uint8_t dummy68[60];
+	uint32_t SWITCH_CORE_INT_EN;
+	uint8_t dummy69[60];
+	uint32_t SWITCH_CORE_SLEEP_TIMER_IMP;
+	uint8_t dummy70[12];
+	uint32_t SWITCH_CORE_PORT7_SLEEP_TIMER;
+	uint8_t dummy71[12];
+	uint32_t SWITCH_CORE_WAN_SLEEP_TIMER;
+	uint8_t dummy72[28];
+	uint32_t SWITCH_CORE_PORT_SLEEP_STS;
+	uint8_t dummy73[92];
+	uint32_t SWITCH_CORE_LINK_STS_INT_EN;
+	uint8_t dummy74[28];
+	uint32_t SWITCH_CORE_ENG_DET_INT_EN;
+	uint8_t dummy75[12];
+	uint32_t SWITCH_CORE_LPI_STS_CHG_INT_EN;
+	uint8_t dummy76[428];
+	uint32_t SWITCH_CORE_MEM_ECC_ERR_INT_STS;
+	uint8_t dummy77[12];
+	uint32_t SWITCH_CORE_MEM_ECC_ERR_INT_EN;
+	uint8_t dummy78[12];
+	uint32_t SWITCH_CORE_PORT_EVT_ECC_ERR_STS;
+	uint8_t dummy79[12];
+	uint32_t SWITCH_CORE_PORT_MIB_ECC_ERR_STS;
+	uint8_t dummy80[12];
+	uint32_t SWITCH_CORE_PORT_TXQ_ECC_ERR_STS;
+	uint8_t dummy81[60];
+	uint32_t SWITCH_CORE_PROBE_BUS_CTL;
+	uint8_t dummy82[28];
+	uint32_t SWITCH_CORE_MDC_EXTEND_CTRL;
+	uint8_t dummy83[92];
+	uint32_t SWITCH_CORE_PPPOE_SESSION_PARSE_EN;
+	uint8_t dummy84[124];
+	uint32_t SWITCH_CORE_CTLREG_1_REG_SPARE0;
+	uint8_t dummy85[28];
+	uint32_t SWITCH_CORE_CTLREG_1_REG_SPARE1;
+	uint8_t dummy86[860];
+	uint32_t SWITCH_CORE_GARLCFG;
+	uint8_t dummy87[28];
+	uint32_t SWITCH_CORE_BPDU_MCADDR;
+	uint8_t dummy88[76];
+	uint32_t SWITCH_CORE_MULTI_PORT_CTL;
+	uint8_t dummy89[12];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR0;
+	uint8_t dummy90[60];
+	uint32_t SWITCH_CORE_MPORTVEC0;
+	uint8_t dummy91[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR1;
+	uint8_t dummy92[60];
+	uint32_t SWITCH_CORE_MPORTVEC1;
+	uint8_t dummy93[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR2;
+	uint8_t dummy94[60];
+	uint32_t SWITCH_CORE_MPORTVEC2;
+	uint8_t dummy95[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR3;
+	uint8_t dummy96[60];
+	uint32_t SWITCH_CORE_MPORTVEC3;
+	uint8_t dummy97[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR4;
+	uint8_t dummy98[60];
+	uint32_t SWITCH_CORE_MPORTVEC4;
+	uint8_t dummy99[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR5;
+	uint8_t dummy100[60];
+	uint32_t SWITCH_CORE_MPORTVEC5;
+	uint8_t dummy101[60];
+	uint32_t SWITCH_CORE_ARL_BIN_FULL_CNTR;
+	uint8_t dummy102[28];
+	uint32_t SWITCH_CORE_ARL_BIN_FULL_FWD;
+	uint8_t dummy103[12];
+	uint32_t SWITCH_CORE_ARL_SEED;
+	uint8_t dummy104[76];
+	uint32_t SWITCH_CORE_ARLCTL_REG_SPARE0;
+	uint8_t dummy105[28];
+	uint32_t SWITCH_CORE_ARLCTL_REG_SPARE1;
+	uint8_t dummy106[92];
+	uint32_t SWITCH_CORE_ARL_TCAM_CTRL;
+	uint8_t dummy107[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_STS;
+	uint8_t dummy108[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_FULL_CNTR;
+	uint8_t dummy109[28];
+	uint32_t SWITCH_CORE_ARL_CPU_PORTMAP;
+	uint8_t dummy110[796];
+	uint32_t SWITCH_CORE_ARLA_RWCTL;
+	uint8_t dummy111[12];
+	uint32_t SWITCH_CORE_ARLA_MAC;
+	uint8_t dummy112[44];
+	uint32_t SWITCH_CORE_ARLA_VID;
+	uint8_t dummy113[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY0;
+	uint8_t dummy114[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY0;
+	uint8_t dummy115[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY1;
+	uint8_t dummy116[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY1;
+	uint8_t dummy117[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY2;
+	uint8_t dummy118[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY2;
+	uint8_t dummy119[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY3;
+	uint8_t dummy120[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY3;
+	uint8_t dummy121[60];
+	uint64_t SWITCH_CORE_ARLA_SRCH_CTL;
+	uint32_t SWITCH_CORE_ARLA_SRCH_ADR;
+	uint8_t dummy122[116];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID;
+	uint8_t dummy123[60];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_0;
+	uint8_t dummy124[60];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID;
+	uint8_t dummy125[60];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_1;
+	uint8_t dummy126[60];
+	uint64_t SWITCH_CORE_ARLA_VTBL_RWCTRL;
+	uint32_t SWITCH_CORE_ARLA_VTBL_ADDR;
+	uint8_t dummy127[12];
+	uint32_t SWITCH_CORE_ARLA_VTBL_ENTRY;
+	uint8_t dummy128[100];
+	uint32_t SWITCH_CORE_ARLACCS_REG_SPARE0;
+	uint8_t dummy129[28];
+	uint32_t SWITCH_CORE_ARLACCS_REG_SPARE1;
+	uint8_t dummy130[4956];
+	uint64_t SWITCH_CORE_MEM_CTRL;
+	uint32_t SWITCH_CORE_MEM_ADDR;
+	uint8_t dummy131[52];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_0_0;
+	uint8_t dummy132[60];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_0_1;
+	uint8_t dummy133[12];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_1_0;
+	uint8_t dummy134[60];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_1_1;
+	uint8_t dummy135[44];
+	uint32_t SWITCH_CORE_MEM_FRM_ADDR;
+	uint8_t dummy136[124];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA0;
+	uint8_t dummy137[60];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA1;
+	uint8_t dummy138[60];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA2;
+	uint8_t dummy139[60];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA3;
+	uint8_t dummy140[60];
+	uint32_t SWITCH_CORE_MEM_BTM_DATA0;
+	uint8_t dummy141[60];
+	uint32_t SWITCH_CORE_MEM_BTM_DATA1;
+	uint8_t dummy142[60];
+	uint32_t SWITCH_CORE_MEM_BFC_ADDR;
+	uint8_t dummy143[12];
+	uint32_t SWITCH_CORE_MEM_BFC_DATA;
+	uint8_t dummy144[108];
+	uint64_t SWITCH_CORE_PRS_FIFO_DEBUG_CTRL;
+	uint32_t SWITCH_CORE_PRS_FIFO_DEBUG_DATA;
+	uint8_t dummy145[116];
+	uint32_t SWITCH_CORE_MIBKILLOVR;
+	uint8_t dummy146[316];
+	uint32_t SWITCH_CORE_MEM_REG_SPARE0;
+	uint8_t dummy147[28];
+	uint32_t SWITCH_CORE_MEM_REG_SPARE1;
+	uint8_t dummy148[28];
+	uint32_t SWITCH_CORE_MEM_MISC_CTRL;
+	uint8_t dummy149[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL0;
+	uint8_t dummy150[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL1;
+	uint8_t dummy151[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL2;
+	uint8_t dummy152[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL3;
+	uint8_t dummy153[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL4;
+	uint8_t dummy154[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL5;
+	uint8_t dummy155[188];
+	uint32_t SWITCH_CORE_MEM_PSM_VDD_CTRL;
+	uint8_t dummy156[252];
+	uint32_t SWITCH_CORE_PORT0_DEBUG;
+	uint8_t dummy157[124];
+	uint32_t SWITCH_CORE_PORT1_DEBUG;
+	uint8_t dummy158[124];
+	uint32_t SWITCH_CORE_PORT2_DEBUG;
+	uint8_t dummy159[124];
+	uint32_t SWITCH_CORE_PORT3_DEBUG;
+	uint8_t dummy160[124];
+	uint32_t SWITCH_CORE_PORT4_DEBUG;
+	uint8_t dummy161[124];
+	uint32_t SWITCH_CORE_PORT5_DEBUG;
+	uint8_t dummy162[124];
+	uint32_t SWITCH_CORE_PORT6_DEBUG;
+	uint8_t dummy163[124];
+	uint32_t SWITCH_CORE_PORT7_DEBUG;
+	uint8_t dummy164[124];
+	uint32_t SWITCH_CORE_PORT8_DEBUG;
+	uint8_t dummy165[1020];
+	uint32_t SWITCH_CORE_FC_DIAG_CTRL;
+	uint8_t dummy166[12];
+	uint64_t SWITCH_CORE_FC_CTRL_MODE;
+	uint64_t SWITCH_CORE_FC_CTRL_PORT;
+	uint32_t SWITCH_CORE_FC_OOB_PAUSE_EN;
+	uint8_t dummy167[92];
+	uint32_t SWITCH_CORE_PAUSE_TIME_MAX;
+	uint8_t dummy168[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_MIN;
+	uint8_t dummy169[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_RESET_THD;
+	uint8_t dummy170[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD;
+	uint8_t dummy171[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_DEFAULT;
+	uint8_t dummy172[12];
+	uint32_t SWITCH_CORE_FC_MCAST_DROP_CTRL;
+	uint8_t dummy173[12];
+	uint32_t SWITCH_CORE_FC_PAUSE_DROP_CTRL;
+	uint8_t dummy174[12];
+	uint32_t SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF;
+	uint8_t dummy175[12];
+	uint32_t SWITCH_CORE_FC_RX_RUNOFF;
+	uint8_t dummy176[12];
+	uint32_t SWITCH_CORE_FC_RX_RSV_THD;
+	uint8_t dummy177[12];
+	uint32_t SWITCH_CORE_FC_RX_HYST_THD;
+	uint8_t dummy178[12];
+	uint32_t SWITCH_CORE_FC_RX_MAX_PTR;
+	uint8_t dummy179[12];
+	uint32_t SWITCH_CORE_FC_SPARE_ZERO_REG;
+	uint8_t dummy180[12];
+	uint32_t SWITCH_CORE_FC_SPARE_ONE_REG;
+	uint8_t dummy181[44];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q0;
+	uint8_t dummy182[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q1;
+	uint8_t dummy183[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q2;
+	uint8_t dummy184[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q3;
+	uint8_t dummy185[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q4;
+	uint8_t dummy186[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q5;
+	uint8_t dummy187[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q6;
+	uint8_t dummy188[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q7;
+	uint8_t dummy189[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q0;
+	uint8_t dummy190[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q1;
+	uint8_t dummy191[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q2;
+	uint8_t dummy192[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q3;
+	uint8_t dummy193[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q4;
+	uint8_t dummy194[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q5;
+	uint8_t dummy195[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q6;
+	uint8_t dummy196[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q7;
+	uint8_t dummy197[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TOTAL_USED;
+	uint8_t dummy198[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_USED;
+	uint8_t dummy199[12];
+	uint32_t SWITCH_CORE_FC_PEAK_RX_CNT;
+	uint8_t dummy200[12];
+	uint32_t SWITCH_CORE_FC_LINK_PORTMAP;
+	uint8_t dummy201[12];
+	uint32_t SWITCH_CORE_FC_GIGA_PORTMAP;
+	uint8_t dummy202[60];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P0;
+	uint8_t dummy203[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P1;
+	uint8_t dummy204[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P2;
+	uint8_t dummy205[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P3;
+	uint8_t dummy206[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P4;
+	uint8_t dummy207[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P5;
+	uint8_t dummy208[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P6;
+	uint8_t dummy209[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P7;
+	uint8_t dummy210[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P8;
+	uint8_t dummy211[60];
+	uint32_t SWITCH_CORE_FC_PAUSE_HIS;
+	uint8_t dummy212[12];
+	uint32_t SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS;
+	uint8_t dummy213[12];
+	uint32_t SWITCH_CORE_FC_RX_PAUSE_HIS;
+	uint8_t dummy214[12];
+	uint32_t SWITCH_CORE_FC_RXBUF_ERR_HIS;
+	uint8_t dummy215[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0;
+	uint8_t dummy216[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1;
+	uint8_t dummy217[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2;
+	uint8_t dummy218[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3;
+	uint8_t dummy219[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4;
+	uint8_t dummy220[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5;
+	uint8_t dummy221[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P6;
+	uint8_t dummy222[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7;
+	uint8_t dummy223[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8;
+	uint8_t dummy224[76];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0;
+	uint8_t dummy225[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1;
+	uint8_t dummy226[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2;
+	uint8_t dummy227[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3;
+	uint8_t dummy228[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4;
+	uint8_t dummy229[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5;
+	uint8_t dummy230[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P6;
+	uint8_t dummy231[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7;
+	uint8_t dummy232[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8;
+	uint8_t dummy233[684];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0;
+	uint8_t dummy234[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1;
+	uint8_t dummy235[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2;
+	uint8_t dummy236[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3;
+	uint8_t dummy237[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4;
+	uint8_t dummy238[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5;
+	uint8_t dummy239[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6;
+	uint8_t dummy240[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7;
+	uint8_t dummy241[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0;
+	uint8_t dummy242[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1;
+	uint8_t dummy243[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2;
+	uint8_t dummy244[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3;
+	uint8_t dummy245[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4;
+	uint8_t dummy246[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5;
+	uint8_t dummy247[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6;
+	uint8_t dummy248[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7;
+	uint8_t dummy249[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0;
+	uint8_t dummy250[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1;
+	uint8_t dummy251[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2;
+	uint8_t dummy252[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3;
+	uint8_t dummy253[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4;
+	uint8_t dummy254[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5;
+	uint8_t dummy255[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6;
+	uint8_t dummy256[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7;
+	uint8_t dummy257[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0;
+	uint8_t dummy258[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1;
+	uint8_t dummy259[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2;
+	uint8_t dummy260[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3;
+	uint8_t dummy261[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4;
+	uint8_t dummy262[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5;
+	uint8_t dummy263[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6;
+	uint8_t dummy264[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7;
+	uint8_t dummy265[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0;
+	uint8_t dummy266[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1;
+	uint8_t dummy267[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2;
+	uint8_t dummy268[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3;
+	uint8_t dummy269[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4;
+	uint8_t dummy270[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5;
+	uint8_t dummy271[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6;
+	uint8_t dummy272[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7;
+	uint8_t dummy273[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0;
+	uint8_t dummy274[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1;
+	uint8_t dummy275[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2;
+	uint8_t dummy276[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3;
+	uint8_t dummy277[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4;
+	uint8_t dummy278[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5;
+	uint8_t dummy279[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6;
+	uint8_t dummy280[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7;
+	uint8_t dummy281[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0;
+	uint8_t dummy282[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1;
+	uint8_t dummy283[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2;
+	uint8_t dummy284[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3;
+	uint8_t dummy285[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4;
+	uint8_t dummy286[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5;
+	uint8_t dummy287[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6;
+	uint8_t dummy288[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7;
+	uint8_t dummy289[1164];
+	uint32_t SWITCH_CORE_P0_DEBUG_MUX;
+	uint8_t dummy290[28];
+	uint32_t SWITCH_CORE_P1_DEBUG_MUX;
+	uint8_t dummy291[28];
+	uint32_t SWITCH_CORE_P2_DEBUG_MUX;
+	uint8_t dummy292[28];
+	uint32_t SWITCH_CORE_P3_DEBUG_MUX;
+	uint8_t dummy293[28];
+	uint32_t SWITCH_CORE_P4_DEBUG_MUX;
+	uint8_t dummy294[28];
+	uint32_t SWITCH_CORE_P5_DEBUG_MUX;
+	uint8_t dummy295[28];
+	uint32_t SWITCH_CORE_P6_DEBUG_MUX;
+	uint8_t dummy296[28];
+	uint32_t SWITCH_CORE_DEBUG_MUX_P7;
+	uint8_t dummy297[28];
+	uint32_t SWITCH_CORE_DEBUG_MUX_IMP;
+	uint8_t dummy298[28];
+	uint32_t SWITCH_CORE_CFP_DEBUG_BUS_0;
+	uint8_t dummy299[28];
+	uint32_t SWITCH_CORE_CFP_DEBUG_BUS_1;
+	uint8_t dummy300[28];
+	uint32_t SWITCH_CORE_WRED_DEBUG_0;
+	uint8_t dummy301[28];
+	uint32_t SWITCH_CORE_WRED_DEBUG_1;
+	uint8_t dummy302[28];
+	uint32_t SWITCH_CORE_TOP_MISC_DEBUG_0;
+	uint8_t dummy303[28];
+	uint32_t SWITCH_CORE_TOP_MISC_DEBUG_1;
+	uint8_t dummy304[28];
+	uint32_t SWITCH_CORE_DIAGREG_BUFCON;
+	uint8_t dummy305[28];
+	uint32_t SWITCH_CORE_TESTBUS_P1588;
+	uint8_t dummy306[28];
+	uint32_t SWITCH_CORE_FLOWCON_DEBUG_BUS;
+	uint8_t dummy307[1500];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0;
+	uint8_t dummy308[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1;
+	uint8_t dummy309[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2;
+	uint8_t dummy310[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3;
+	uint8_t dummy311[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4;
+	uint8_t dummy312[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5;
+	uint8_t dummy313[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6;
+	uint8_t dummy314[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7;
+	uint8_t dummy315[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0;
+	uint8_t dummy316[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1;
+	uint8_t dummy317[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2;
+	uint8_t dummy318[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3;
+	uint8_t dummy319[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4;
+	uint8_t dummy320[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5;
+	uint8_t dummy321[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6;
+	uint8_t dummy322[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7;
+	uint8_t dummy323[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0;
+	uint8_t dummy324[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1;
+	uint8_t dummy325[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2;
+	uint8_t dummy326[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3;
+	uint8_t dummy327[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4;
+	uint8_t dummy328[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5;
+	uint8_t dummy329[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6;
+	uint8_t dummy330[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7;
+	uint8_t dummy331[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0;
+	uint8_t dummy332[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1;
+	uint8_t dummy333[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2;
+	uint8_t dummy334[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3;
+	uint8_t dummy335[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4;
+	uint8_t dummy336[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5;
+	uint8_t dummy337[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6;
+	uint8_t dummy338[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7;
+	uint8_t dummy339[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0;
+	uint8_t dummy340[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1;
+	uint8_t dummy341[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2;
+	uint8_t dummy342[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3;
+	uint8_t dummy343[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4;
+	uint8_t dummy344[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5;
+	uint8_t dummy345[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6;
+	uint8_t dummy346[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7;
+	uint8_t dummy347[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0;
+	uint8_t dummy348[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1;
+	uint8_t dummy349[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2;
+	uint8_t dummy350[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3;
+	uint8_t dummy351[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4;
+	uint8_t dummy352[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5;
+	uint8_t dummy353[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6;
+	uint8_t dummy354[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7;
+	uint8_t dummy355[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0;
+	uint8_t dummy356[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1;
+	uint8_t dummy357[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2;
+	uint8_t dummy358[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3;
+	uint8_t dummy359[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4;
+	uint8_t dummy360[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5;
+	uint8_t dummy361[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6;
+	uint8_t dummy362[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7;
+	uint8_t dummy363[12];
+	uint32_t SWITCH_CORE_FC_IMP0_REG_SPARE0;
+	uint8_t dummy364[12];
+	uint32_t SWITCH_CORE_FC_IMP0_REG_SPARE1;
+	uint8_t dummy365[1132];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0;
+	uint8_t dummy366[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1;
+	uint8_t dummy367[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2;
+	uint8_t dummy368[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3;
+	uint8_t dummy369[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4;
+	uint8_t dummy370[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5;
+	uint8_t dummy371[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6;
+	uint8_t dummy372[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7;
+	uint8_t dummy373[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0;
+	uint8_t dummy374[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1;
+	uint8_t dummy375[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2;
+	uint8_t dummy376[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3;
+	uint8_t dummy377[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4;
+	uint8_t dummy378[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5;
+	uint8_t dummy379[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6;
+	uint8_t dummy380[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7;
+	uint8_t dummy381[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0;
+	uint8_t dummy382[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1;
+	uint8_t dummy383[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2;
+	uint8_t dummy384[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3;
+	uint8_t dummy385[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4;
+	uint8_t dummy386[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5;
+	uint8_t dummy387[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6;
+	uint8_t dummy388[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7;
+	uint8_t dummy389[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0;
+	uint8_t dummy390[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1;
+	uint8_t dummy391[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2;
+	uint8_t dummy392[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3;
+	uint8_t dummy393[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4;
+	uint8_t dummy394[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5;
+	uint8_t dummy395[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6;
+	uint8_t dummy396[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7;
+	uint8_t dummy397[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0;
+	uint8_t dummy398[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1;
+	uint8_t dummy399[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2;
+	uint8_t dummy400[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3;
+	uint8_t dummy401[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4;
+	uint8_t dummy402[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5;
+	uint8_t dummy403[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6;
+	uint8_t dummy404[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7;
+	uint8_t dummy405[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0;
+	uint8_t dummy406[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1;
+	uint8_t dummy407[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2;
+	uint8_t dummy408[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3;
+	uint8_t dummy409[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4;
+	uint8_t dummy410[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5;
+	uint8_t dummy411[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6;
+	uint8_t dummy412[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7;
+	uint8_t dummy413[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0;
+	uint8_t dummy414[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1;
+	uint8_t dummy415[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2;
+	uint8_t dummy416[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3;
+	uint8_t dummy417[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4;
+	uint8_t dummy418[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5;
+	uint8_t dummy419[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6;
+	uint8_t dummy420[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7;
+	uint8_t dummy421[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0;
+	uint8_t dummy422[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1;
+	uint8_t dummy423[35948];
+	uint32_t SWITCH_CORE_TxOctets_P0;
+	uint8_t dummy424[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P0;
+	uint8_t dummy425[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P0;
+	uint8_t dummy426[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P0;
+	uint8_t dummy427[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P0;
+	uint8_t dummy428[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P0;
+	uint8_t dummy429[28];
+	uint32_t SWITCH_CORE_TxCollisions_P0;
+	uint8_t dummy430[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P0;
+	uint8_t dummy431[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P0;
+	uint8_t dummy432[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P0;
+	uint8_t dummy433[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P0;
+	uint8_t dummy434[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P0;
+	uint8_t dummy435[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P0;
+	uint8_t dummy436[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P0;
+	uint8_t dummy437[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P0;
+	uint8_t dummy438[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P0;
+	uint8_t dummy439[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P0;
+	uint8_t dummy440[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P0;
+	uint8_t dummy441[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P0;
+	uint8_t dummy442[28];
+	uint32_t SWITCH_CORE_RxOctets_P0;
+	uint8_t dummy443[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P0;
+	uint8_t dummy444[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P0;
+	uint8_t dummy445[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P0;
+	uint8_t dummy446[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P0;
+	uint8_t dummy447[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P0;
+	uint8_t dummy448[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P0;
+	uint8_t dummy449[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P0;
+	uint8_t dummy450[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P0;
+	uint8_t dummy451[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P0;
+	uint8_t dummy452[28];
+	uint32_t SWITCH_CORE_RxJabbers_P0;
+	uint8_t dummy453[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P0;
+	uint8_t dummy454[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P0;
+	uint8_t dummy455[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P0;
+	uint8_t dummy456[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P0;
+	uint8_t dummy457[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P0;
+	uint8_t dummy458[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P0;
+	uint8_t dummy459[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P0;
+	uint8_t dummy460[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P0;
+	uint8_t dummy461[28];
+	uint32_t SWITCH_CORE_RxFragments_P0;
+	uint8_t dummy462[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P0;
+	uint8_t dummy463[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P0;
+	uint8_t dummy464[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P0;
+	uint8_t dummy465[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P0;
+	uint8_t dummy466[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P0;
+	uint8_t dummy467[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P0;
+	uint8_t dummy468[28];
+	uint32_t SWITCH_CORE_RxDiscard_P0;
+	uint8_t dummy469[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P0;
+	uint8_t dummy470[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P0;
+	uint8_t dummy471[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P0;
+	uint8_t dummy472[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P0;
+	uint8_t dummy473[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P0;
+	uint8_t dummy474[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P0;
+	uint8_t dummy475[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P0;
+	uint8_t dummy476[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P0;
+	uint8_t dummy477[220];
+	uint32_t SWITCH_CORE_TxOctets_P1;
+	uint8_t dummy478[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P1;
+	uint8_t dummy479[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P1;
+	uint8_t dummy480[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P1;
+	uint8_t dummy481[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P1;
+	uint8_t dummy482[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P1;
+	uint8_t dummy483[28];
+	uint32_t SWITCH_CORE_TxCollisions_P1;
+	uint8_t dummy484[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P1;
+	uint8_t dummy485[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P1;
+	uint8_t dummy486[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P1;
+	uint8_t dummy487[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P1;
+	uint8_t dummy488[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P1;
+	uint8_t dummy489[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P1;
+	uint8_t dummy490[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P1;
+	uint8_t dummy491[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P1;
+	uint8_t dummy492[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P1;
+	uint8_t dummy493[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P1;
+	uint8_t dummy494[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P1;
+	uint8_t dummy495[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P1;
+	uint8_t dummy496[28];
+	uint32_t SWITCH_CORE_RxOctets_P1;
+	uint8_t dummy497[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P1;
+	uint8_t dummy498[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P1;
+	uint8_t dummy499[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P1;
+	uint8_t dummy500[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P1;
+	uint8_t dummy501[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P1;
+	uint8_t dummy502[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P1;
+	uint8_t dummy503[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P1;
+	uint8_t dummy504[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P1;
+	uint8_t dummy505[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P1;
+	uint8_t dummy506[28];
+	uint32_t SWITCH_CORE_RxJabbers_P1;
+	uint8_t dummy507[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P1;
+	uint8_t dummy508[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P1;
+	uint8_t dummy509[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P1;
+	uint8_t dummy510[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P1;
+	uint8_t dummy511[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P1;
+	uint8_t dummy512[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P1;
+	uint8_t dummy513[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P1;
+	uint8_t dummy514[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P1;
+	uint8_t dummy515[28];
+	uint32_t SWITCH_CORE_RxFragments_P1;
+	uint8_t dummy516[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P1;
+	uint8_t dummy517[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P1;
+	uint8_t dummy518[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P1;
+	uint8_t dummy519[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P1;
+	uint8_t dummy520[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P1;
+	uint8_t dummy521[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P1;
+	uint8_t dummy522[28];
+	uint32_t SWITCH_CORE_RxDiscard_P1;
+	uint8_t dummy523[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P1;
+	uint8_t dummy524[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P1;
+	uint8_t dummy525[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P1;
+	uint8_t dummy526[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P1;
+	uint8_t dummy527[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P1;
+	uint8_t dummy528[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P1;
+	uint8_t dummy529[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P1;
+	uint8_t dummy530[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P1;
+	uint8_t dummy531[220];
+	uint32_t SWITCH_CORE_TxOctets_P2;
+	uint8_t dummy532[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P2;
+	uint8_t dummy533[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P2;
+	uint8_t dummy534[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P2;
+	uint8_t dummy535[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P2;
+	uint8_t dummy536[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P2;
+	uint8_t dummy537[28];
+	uint32_t SWITCH_CORE_TxCollisions_P2;
+	uint8_t dummy538[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P2;
+	uint8_t dummy539[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P2;
+	uint8_t dummy540[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P2;
+	uint8_t dummy541[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P2;
+	uint8_t dummy542[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P2;
+	uint8_t dummy543[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P2;
+	uint8_t dummy544[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P2;
+	uint8_t dummy545[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P2;
+	uint8_t dummy546[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P2;
+	uint8_t dummy547[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P2;
+	uint8_t dummy548[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P2;
+	uint8_t dummy549[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P2;
+	uint8_t dummy550[28];
+	uint32_t SWITCH_CORE_RxOctets_P2;
+	uint8_t dummy551[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P2;
+	uint8_t dummy552[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P2;
+	uint8_t dummy553[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P2;
+	uint8_t dummy554[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P2;
+	uint8_t dummy555[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P2;
+	uint8_t dummy556[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P2;
+	uint8_t dummy557[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P2;
+	uint8_t dummy558[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P2;
+	uint8_t dummy559[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P2;
+	uint8_t dummy560[28];
+	uint32_t SWITCH_CORE_RxJabbers_P2;
+	uint8_t dummy561[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P2;
+	uint8_t dummy562[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P2;
+	uint8_t dummy563[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P2;
+	uint8_t dummy564[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P2;
+	uint8_t dummy565[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P2;
+	uint8_t dummy566[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P2;
+	uint8_t dummy567[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P2;
+	uint8_t dummy568[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P2;
+	uint8_t dummy569[28];
+	uint32_t SWITCH_CORE_RxFragments_P2;
+	uint8_t dummy570[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P2;
+	uint8_t dummy571[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P2;
+	uint8_t dummy572[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P2;
+	uint8_t dummy573[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P2;
+	uint8_t dummy574[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P2;
+	uint8_t dummy575[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P2;
+	uint8_t dummy576[28];
+	uint32_t SWITCH_CORE_RxDiscard_P2;
+	uint8_t dummy577[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P2;
+	uint8_t dummy578[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P2;
+	uint8_t dummy579[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P2;
+	uint8_t dummy580[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P2;
+	uint8_t dummy581[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P2;
+	uint8_t dummy582[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P2;
+	uint8_t dummy583[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P2;
+	uint8_t dummy584[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P2;
+	uint8_t dummy585[220];
+	uint32_t SWITCH_CORE_TxOctets_P3;
+	uint8_t dummy586[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P3;
+	uint8_t dummy587[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P3;
+	uint8_t dummy588[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P3;
+	uint8_t dummy589[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P3;
+	uint8_t dummy590[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P3;
+	uint8_t dummy591[28];
+	uint32_t SWITCH_CORE_TxCollisions_P3;
+	uint8_t dummy592[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P3;
+	uint8_t dummy593[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P3;
+	uint8_t dummy594[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P3;
+	uint8_t dummy595[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P3;
+	uint8_t dummy596[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P3;
+	uint8_t dummy597[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P3;
+	uint8_t dummy598[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P3;
+	uint8_t dummy599[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P3;
+	uint8_t dummy600[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P3;
+	uint8_t dummy601[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P3;
+	uint8_t dummy602[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P3;
+	uint8_t dummy603[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P3;
+	uint8_t dummy604[28];
+	uint32_t SWITCH_CORE_RxOctets_P3;
+	uint8_t dummy605[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P3;
+	uint8_t dummy606[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P3;
+	uint8_t dummy607[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P3;
+	uint8_t dummy608[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P3;
+	uint8_t dummy609[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P3;
+	uint8_t dummy610[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P3;
+	uint8_t dummy611[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P3;
+	uint8_t dummy612[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P3;
+	uint8_t dummy613[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P3;
+	uint8_t dummy614[28];
+	uint32_t SWITCH_CORE_RxJabbers_P3;
+	uint8_t dummy615[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P3;
+	uint8_t dummy616[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P3;
+	uint8_t dummy617[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P3;
+	uint8_t dummy618[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P3;
+	uint8_t dummy619[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P3;
+	uint8_t dummy620[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P3;
+	uint8_t dummy621[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P3;
+	uint8_t dummy622[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P3;
+	uint8_t dummy623[28];
+	uint32_t SWITCH_CORE_RxFragments_P3;
+	uint8_t dummy624[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P3;
+	uint8_t dummy625[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P3;
+	uint8_t dummy626[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P3;
+	uint8_t dummy627[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P3;
+	uint8_t dummy628[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P3;
+	uint8_t dummy629[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P3;
+	uint8_t dummy630[28];
+	uint32_t SWITCH_CORE_RxDiscard_P3;
+	uint8_t dummy631[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P3;
+	uint8_t dummy632[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P3;
+	uint8_t dummy633[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P3;
+	uint8_t dummy634[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P3;
+	uint8_t dummy635[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P3;
+	uint8_t dummy636[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P3;
+	uint8_t dummy637[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P3;
+	uint8_t dummy638[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P3;
+	uint8_t dummy639[220];
+	uint32_t SWITCH_CORE_TxOctets_P4;
+	uint8_t dummy640[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P4;
+	uint8_t dummy641[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P4;
+	uint8_t dummy642[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P4;
+	uint8_t dummy643[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P4;
+	uint8_t dummy644[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P4;
+	uint8_t dummy645[28];
+	uint32_t SWITCH_CORE_TxCollisions_P4;
+	uint8_t dummy646[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P4;
+	uint8_t dummy647[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P4;
+	uint8_t dummy648[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P4;
+	uint8_t dummy649[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P4;
+	uint8_t dummy650[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P4;
+	uint8_t dummy651[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P4;
+	uint8_t dummy652[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P4;
+	uint8_t dummy653[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P4;
+	uint8_t dummy654[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P4;
+	uint8_t dummy655[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P4;
+	uint8_t dummy656[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P4;
+	uint8_t dummy657[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P4;
+	uint8_t dummy658[28];
+	uint32_t SWITCH_CORE_RxOctets_P4;
+	uint8_t dummy659[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P4;
+	uint8_t dummy660[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P4;
+	uint8_t dummy661[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P4;
+	uint8_t dummy662[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P4;
+	uint8_t dummy663[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P4;
+	uint8_t dummy664[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P4;
+	uint8_t dummy665[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P4;
+	uint8_t dummy666[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P4;
+	uint8_t dummy667[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P4;
+	uint8_t dummy668[28];
+	uint32_t SWITCH_CORE_RxJabbers_P4;
+	uint8_t dummy669[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P4;
+	uint8_t dummy670[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P4;
+	uint8_t dummy671[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P4;
+	uint8_t dummy672[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P4;
+	uint8_t dummy673[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P4;
+	uint8_t dummy674[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P4;
+	uint8_t dummy675[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P4;
+	uint8_t dummy676[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P4;
+	uint8_t dummy677[28];
+	uint32_t SWITCH_CORE_RxFragments_P4;
+	uint8_t dummy678[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P4;
+	uint8_t dummy679[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P4;
+	uint8_t dummy680[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P4;
+	uint8_t dummy681[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P4;
+	uint8_t dummy682[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P4;
+	uint8_t dummy683[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P4;
+	uint8_t dummy684[28];
+	uint32_t SWITCH_CORE_RxDiscard_P4;
+	uint8_t dummy685[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P4;
+	uint8_t dummy686[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P4;
+	uint8_t dummy687[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P4;
+	uint8_t dummy688[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P4;
+	uint8_t dummy689[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P4;
+	uint8_t dummy690[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P4;
+	uint8_t dummy691[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P4;
+	uint8_t dummy692[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P4;
+	uint8_t dummy693[220];
+	uint32_t SWITCH_CORE_TxOctets_P5;
+	uint8_t dummy694[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P5;
+	uint8_t dummy695[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P5;
+	uint8_t dummy696[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P5;
+	uint8_t dummy697[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P5;
+	uint8_t dummy698[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P5;
+	uint8_t dummy699[28];
+	uint32_t SWITCH_CORE_TxCollisions_P5;
+	uint8_t dummy700[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P5;
+	uint8_t dummy701[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P5;
+	uint8_t dummy702[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P5;
+	uint8_t dummy703[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P5;
+	uint8_t dummy704[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P5;
+	uint8_t dummy705[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P5;
+	uint8_t dummy706[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P5;
+	uint8_t dummy707[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P5;
+	uint8_t dummy708[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P5;
+	uint8_t dummy709[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P5;
+	uint8_t dummy710[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P5;
+	uint8_t dummy711[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P5;
+	uint8_t dummy712[28];
+	uint32_t SWITCH_CORE_RxOctets_P5;
+	uint8_t dummy713[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P5;
+	uint8_t dummy714[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P5;
+	uint8_t dummy715[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P5;
+	uint8_t dummy716[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P5;
+	uint8_t dummy717[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P5;
+	uint8_t dummy718[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P5;
+	uint8_t dummy719[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P5;
+	uint8_t dummy720[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P5;
+	uint8_t dummy721[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P5;
+	uint8_t dummy722[28];
+	uint32_t SWITCH_CORE_RxJabbers_P5;
+	uint8_t dummy723[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P5;
+	uint8_t dummy724[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P5;
+	uint8_t dummy725[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P5;
+	uint8_t dummy726[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P5;
+	uint8_t dummy727[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P5;
+	uint8_t dummy728[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P5;
+	uint8_t dummy729[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P5;
+	uint8_t dummy730[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P5;
+	uint8_t dummy731[28];
+	uint32_t SWITCH_CORE_RxFragments_P5;
+	uint8_t dummy732[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P5;
+	uint8_t dummy733[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P5;
+	uint8_t dummy734[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P5;
+	uint8_t dummy735[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P5;
+	uint8_t dummy736[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P5;
+	uint8_t dummy737[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P5;
+	uint8_t dummy738[28];
+	uint32_t SWITCH_CORE_RxDiscard_P5;
+	uint8_t dummy739[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P5;
+	uint8_t dummy740[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P5;
+	uint8_t dummy741[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P5;
+	uint8_t dummy742[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P5;
+	uint8_t dummy743[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P5;
+	uint8_t dummy744[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P5;
+	uint8_t dummy745[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P5;
+	uint8_t dummy746[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P5;
+	uint8_t dummy747[220];
+	uint32_t SWITCH_CORE_TxOctets_P6;
+	uint8_t dummy748[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P6;
+	uint8_t dummy749[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P6;
+	uint8_t dummy750[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P6;
+	uint8_t dummy751[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P6;
+	uint8_t dummy752[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P6;
+	uint8_t dummy753[28];
+	uint32_t SWITCH_CORE_TxCollisions_P6;
+	uint8_t dummy754[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P6;
+	uint8_t dummy755[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P6;
+	uint8_t dummy756[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P6;
+	uint8_t dummy757[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P6;
+	uint8_t dummy758[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P6;
+	uint8_t dummy759[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P6;
+	uint8_t dummy760[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P6;
+	uint8_t dummy761[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P6;
+	uint8_t dummy762[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P6;
+	uint8_t dummy763[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P6;
+	uint8_t dummy764[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P6;
+	uint8_t dummy765[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P6;
+	uint8_t dummy766[28];
+	uint32_t SWITCH_CORE_RxOctets_P6;
+	uint8_t dummy767[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P6;
+	uint8_t dummy768[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P6;
+	uint8_t dummy769[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P6;
+	uint8_t dummy770[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P6;
+	uint8_t dummy771[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P6;
+	uint8_t dummy772[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P6;
+	uint8_t dummy773[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P6;
+	uint8_t dummy774[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P6;
+	uint8_t dummy775[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P6;
+	uint8_t dummy776[28];
+	uint32_t SWITCH_CORE_RxJabbers_P6;
+	uint8_t dummy777[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P6;
+	uint8_t dummy778[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P6;
+	uint8_t dummy779[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P6;
+	uint8_t dummy780[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P6;
+	uint8_t dummy781[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P6;
+	uint8_t dummy782[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P6;
+	uint8_t dummy783[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P6;
+	uint8_t dummy784[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P6;
+	uint8_t dummy785[28];
+	uint32_t SWITCH_CORE_RxFragments_P6;
+	uint8_t dummy786[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P6;
+	uint8_t dummy787[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P6;
+	uint8_t dummy788[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P6;
+	uint8_t dummy789[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P6;
+	uint8_t dummy790[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P6;
+	uint8_t dummy791[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P6;
+	uint8_t dummy792[28];
+	uint32_t SWITCH_CORE_RxDiscard_P6;
+	uint8_t dummy793[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P6;
+	uint8_t dummy794[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P6;
+	uint8_t dummy795[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P6;
+	uint8_t dummy796[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P6;
+	uint8_t dummy797[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P6;
+	uint8_t dummy798[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P6;
+	uint8_t dummy799[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P6;
+	uint8_t dummy800[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P6;
+	uint8_t dummy801[220];
+	uint32_t SWITCH_CORE_TxOctets_P7;
+	uint8_t dummy802[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P7;
+	uint8_t dummy803[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P7;
+	uint8_t dummy804[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P7;
+	uint8_t dummy805[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P7;
+	uint8_t dummy806[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P7;
+	uint8_t dummy807[28];
+	uint32_t SWITCH_CORE_TxCollisions_P7;
+	uint8_t dummy808[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P7;
+	uint8_t dummy809[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P7;
+	uint8_t dummy810[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P7;
+	uint8_t dummy811[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P7;
+	uint8_t dummy812[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P7;
+	uint8_t dummy813[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P7;
+	uint8_t dummy814[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P7;
+	uint8_t dummy815[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P7;
+	uint8_t dummy816[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P7;
+	uint8_t dummy817[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P7;
+	uint8_t dummy818[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P7;
+	uint8_t dummy819[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P7;
+	uint8_t dummy820[28];
+	uint32_t SWITCH_CORE_RxOctets_P7;
+	uint8_t dummy821[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P7;
+	uint8_t dummy822[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P7;
+	uint8_t dummy823[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P7;
+	uint8_t dummy824[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P7;
+	uint8_t dummy825[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P7;
+	uint8_t dummy826[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P7;
+	uint8_t dummy827[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P7;
+	uint8_t dummy828[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P7;
+	uint8_t dummy829[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P7;
+	uint8_t dummy830[28];
+	uint32_t SWITCH_CORE_RxJabbers_P7;
+	uint8_t dummy831[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P7;
+	uint8_t dummy832[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P7;
+	uint8_t dummy833[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P7;
+	uint8_t dummy834[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P7;
+	uint8_t dummy835[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P7;
+	uint8_t dummy836[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P7;
+	uint8_t dummy837[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P7;
+	uint8_t dummy838[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P7;
+	uint8_t dummy839[28];
+	uint32_t SWITCH_CORE_RxFragments_P7;
+	uint8_t dummy840[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P7;
+	uint8_t dummy841[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P7;
+	uint8_t dummy842[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P7;
+	uint8_t dummy843[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P7;
+	uint8_t dummy844[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P7;
+	uint8_t dummy845[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P7;
+	uint8_t dummy846[28];
+	uint32_t SWITCH_CORE_RxDiscard_P7;
+	uint8_t dummy847[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P7;
+	uint8_t dummy848[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P7;
+	uint8_t dummy849[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P7;
+	uint8_t dummy850[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P7;
+	uint8_t dummy851[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P7;
+	uint8_t dummy852[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P7;
+	uint8_t dummy853[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P7;
+	uint8_t dummy854[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P7;
+	uint8_t dummy855[220];
+	uint32_t SWITCH_CORE_TxOctets_IMP;
+	uint8_t dummy856[60];
+	uint32_t SWITCH_CORE_TxDropPkts_IMP;
+	uint8_t dummy857[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_IMP;
+	uint8_t dummy858[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_IMP;
+	uint8_t dummy859[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_IMP;
+	uint8_t dummy860[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_IMP;
+	uint8_t dummy861[28];
+	uint32_t SWITCH_CORE_TxCollisions_IMP;
+	uint8_t dummy862[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_IMP;
+	uint8_t dummy863[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_IMP;
+	uint8_t dummy864[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_IMP;
+	uint8_t dummy865[28];
+	uint32_t SWITCH_CORE_TxLateCollision_IMP;
+	uint8_t dummy866[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_IMP;
+	uint8_t dummy867[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_IMP;
+	uint8_t dummy868[28];
+	uint32_t SWITCH_CORE_TxPausePkts_IMP;
+	uint8_t dummy869[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_IMP;
+	uint8_t dummy870[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_IMP;
+	uint8_t dummy871[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_IMP;
+	uint8_t dummy872[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_IMP;
+	uint8_t dummy873[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_IMP;
+	uint8_t dummy874[28];
+	uint32_t SWITCH_CORE_RxOctets_IMP;
+	uint8_t dummy875[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_IMP;
+	uint8_t dummy876[28];
+	uint32_t SWITCH_CORE_RxPausePkts_IMP;
+	uint8_t dummy877[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_IMP;
+	uint8_t dummy878[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_IMP;
+	uint8_t dummy879[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_IMP;
+	uint8_t dummy880[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_IMP;
+	uint8_t dummy881[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_IMP;
+	uint8_t dummy882[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP;
+	uint8_t dummy883[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_IMP;
+	uint8_t dummy884[28];
+	uint32_t SWITCH_CORE_RxJabbers_IMP;
+	uint8_t dummy885[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_IMP;
+	uint8_t dummy886[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_IMP;
+	uint8_t dummy887[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_IMP;
+	uint8_t dummy888[60];
+	uint32_t SWITCH_CORE_RxDropPkts_IMP;
+	uint8_t dummy889[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_IMP;
+	uint8_t dummy890[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_IMP;
+	uint8_t dummy891[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_IMP;
+	uint8_t dummy892[28];
+	uint32_t SWITCH_CORE_RxSAChanges_IMP;
+	uint8_t dummy893[28];
+	uint32_t SWITCH_CORE_RxFragments_IMP;
+	uint8_t dummy894[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_IMP;
+	uint8_t dummy895[28];
+	uint32_t SWITCH_CORE_RxSymblErr_IMP;
+	uint8_t dummy896[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_IMP;
+	uint8_t dummy897[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_IMP;
+	uint8_t dummy898[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_IMP;
+	uint8_t dummy899[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_IMP;
+	uint8_t dummy900[28];
+	uint32_t SWITCH_CORE_RxDiscard_IMP;
+	uint8_t dummy901[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_IMP;
+	uint8_t dummy902[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_IMP;
+	uint8_t dummy903[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_IMP;
+	uint8_t dummy904[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_IMP;
+	uint8_t dummy905[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_IMP;
+	uint8_t dummy906[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_IMP;
+	uint8_t dummy907[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_IMP;
+	uint8_t dummy908[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP;
+	uint8_t dummy909[14556];
+	uint32_t SWITCH_CORE_QOS_GLOBAL_CTRL;
+	uint8_t dummy910[28];
+	uint32_t SWITCH_CORE_QOS_1P_EN;
+	uint8_t dummy911[12];
+	uint32_t SWITCH_CORE_QOS_EN_DIFFSERV;
+	uint8_t dummy912[76];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P0;
+	uint8_t dummy913[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P1;
+	uint8_t dummy914[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P2;
+	uint8_t dummy915[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P3;
+	uint8_t dummy916[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P4;
+	uint8_t dummy917[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P5;
+	uint8_t dummy918[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P6;
+	uint8_t dummy919[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P7;
+	uint8_t dummy920[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_IMP;
+	uint8_t dummy921[28];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP0;
+	uint8_t dummy922[44];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP1;
+	uint8_t dummy923[44];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP2;
+	uint8_t dummy924[44];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP3;
+	uint8_t dummy925[44];
+	uint32_t SWITCH_CORE_PID2TC;
+	uint8_t dummy926[60];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P0;
+	uint8_t dummy927[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P1;
+	uint8_t dummy928[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P2;
+	uint8_t dummy929[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P3;
+	uint8_t dummy930[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P4;
+	uint8_t dummy931[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P5;
+	uint8_t dummy932[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P6;
+	uint8_t dummy933[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P7;
+	uint8_t dummy934[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_IMP;
+	uint8_t dummy935[28];
+	uint32_t SWITCH_CORE_CPU2COS_MAP;
+	uint8_t dummy936[60];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P0;
+	uint8_t dummy937[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P1;
+	uint8_t dummy938[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P2;
+	uint8_t dummy939[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P3;
+	uint8_t dummy940[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P4;
+	uint8_t dummy941[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P5;
+	uint8_t dummy942[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P6;
+	uint8_t dummy943[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P7;
+	uint8_t dummy944[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_IMP;
+	uint8_t dummy945[188];
+	uint32_t SWITCH_CORE_QOS_REG_SPARE0;
+	uint8_t dummy946[28];
+	uint32_t SWITCH_CORE_QOS_REG_SPARE1;
+	uint8_t dummy947[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P0;
+	uint8_t dummy948[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P1;
+	uint8_t dummy949[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P2;
+	uint8_t dummy950[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P3;
+	uint8_t dummy951[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P4;
+	uint8_t dummy952[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P5;
+	uint8_t dummy953[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P6;
+	uint8_t dummy954[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P7;
+	uint8_t dummy955[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_IMP;
+	uint8_t dummy956[380];
+	uint32_t port_vlan_ctrl[4*9];
+	uint8_t dummy965[112];
+	uint32_t SWITCH_CORE_VLAN_REG_SPARE0;
+	uint8_t dummy966[28];
+	uint32_t SWITCH_CORE_VLAN_REG_SPARE1;
+	uint8_t dummy967[1756];
+	uint32_t SWITCH_CORE_MAC_TRUNK_CTL;
+	uint8_t dummy968[12];
+	uint32_t SWITCH_CORE_IMP0_GRP_CTL;
+	uint8_t dummy969[108];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL0;
+	uint8_t dummy970[12];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL1;
+	uint8_t dummy971[12];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL2;
+	uint8_t dummy972[12];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL3;
+	uint8_t dummy973[76];
+	uint32_t SWITCH_CORE_TRUNK_HASH_OVRRD;
+	uint8_t dummy974[252];
+	uint32_t SWITCH_CORE_TRUNK_REG_SPARE0;
+	uint8_t dummy975[28];
+	uint32_t SWITCH_CORE_TRUNK_REG_SPARE1;
+	uint8_t dummy976[3548];
+	uint64_t SWITCH_CORE_VLAN_CTRL0;
+	uint64_t SWITCH_CORE_VLAN_CTRL1;
+	uint64_t SWITCH_CORE_VLAN_CTRL2;
+	uint32_t SWITCH_CORE_VLAN_CTRL3;
+	uint8_t dummy977[12];
+	uint64_t SWITCH_CORE_VLAN_CTRL4;
+	uint64_t SWITCH_CORE_VLAN_CTRL5;
+	uint32_t SWITCH_CORE_VLAN_CTRL6;
+	uint8_t dummy978[20];
+	uint32_t SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL;
+	uint8_t dummy979[44];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P0;
+	uint8_t dummy980[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P1;
+	uint8_t dummy981[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P2;
+	uint8_t dummy982[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P3;
+	uint8_t dummy983[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P4;
+	uint8_t dummy984[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P5;
+	uint8_t dummy985[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P6;
+	uint8_t dummy986[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P7;
+	uint8_t dummy987[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_IMP;
+	uint8_t dummy988[124];
+	uint32_t SWITCH_CORE_DTAG_TPID;
+	uint8_t dummy989[12];
+	uint32_t SWITCH_CORE_ISP_SEL_PORTMAP;
+	uint8_t dummy990[108];
+	uint32_t SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS;
+	uint8_t dummy991[28];
+	uint32_t SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA;
+	uint8_t dummy992[92];
+	uint32_t SWITCH_CORE_JOIN_ALL_VLAN_EN;
+	uint8_t dummy993[12];
+	uint32_t SWITCH_CORE_PORT_IVL_SVL_CTRL;
+	uint8_t dummy994[108];
+	uint32_t SWITCH_CORE_BCM8021Q_REG_SPARE0;
+	uint8_t dummy995[28];
+	uint32_t SWITCH_CORE_BCM8021Q_REG_SPARE1;
+	uint8_t dummy996[3292];
+	uint32_t SWITCH_CORE_DOS_CTRL;
+	uint8_t dummy997[28];
+	uint32_t SWITCH_CORE_MINIMUM_TCP_HDR_SZ;
+	uint8_t dummy998[28];
+	uint32_t SWITCH_CORE_MAX_ICMPV4_SIZE_REG;
+	uint8_t dummy999[28];
+	uint32_t SWITCH_CORE_MAX_ICMPV6_SIZE_REG;
+	uint8_t dummy1000[28];
+	uint32_t SWITCH_CORE_DOS_DIS_LRN_REG;
+	uint8_t dummy1001[124];
+	uint32_t SWITCH_CORE_DOS_REG_SPARE0;
+	uint8_t dummy1002[28];
+	uint32_t SWITCH_CORE_DOS_REG_SPARE1;
+	uint8_t dummy1003[20196];
+	uint32_t SWITCH_CORE_JUMBO_PORT_MASK;
+	uint8_t dummy1004[28];
+	uint32_t SWITCH_CORE_MIB_GD_FM_MAX_SIZE;
+	uint8_t dummy1005[84];
+	uint32_t SWITCH_CORE_JUMBO_CTRL_REG_SPARE0;
+	uint8_t dummy1006[28];
+	uint32_t SWITCH_CORE_JUMBO_CTRL_REG_SPARE1;
+	uint8_t dummy1007[1884];
+	uint32_t SWITCH_CORE_COMM_IRC_CON;
+	uint8_t dummy1008[28];
+	uint32_t SWITCH_CORE_IRC_VIRTUAL_ZERO_THD;
+	uint8_t dummy1009[12];
+	uint32_t SWITCH_CORE_IRC_ALARM_THD;
+	uint8_t dummy1010[76];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P0;
+	uint8_t dummy1011[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P1;
+	uint8_t dummy1012[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P2;
+	uint8_t dummy1013[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P3;
+	uint8_t dummy1014[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P4;
+	uint8_t dummy1015[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P5;
+	uint8_t dummy1016[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P6;
+	uint8_t dummy1017[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P7;
+	uint8_t dummy1018[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_IMP;
+	uint8_t dummy1019[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P0;
+	uint8_t dummy1020[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P1;
+	uint8_t dummy1021[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P2;
+	uint8_t dummy1022[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P3;
+	uint8_t dummy1023[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P4;
+	uint8_t dummy1024[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P5;
+	uint8_t dummy1025[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P6;
+	uint8_t dummy1026[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P7;
+	uint8_t dummy1027[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_IMP;
+	uint8_t dummy1028[92];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P0;
+	uint8_t dummy1029[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P1;
+	uint8_t dummy1030[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P2;
+	uint8_t dummy1031[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P3;
+	uint8_t dummy1032[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P4;
+	uint8_t dummy1033[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P5;
+	uint8_t dummy1034[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P6;
+	uint8_t dummy1035[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7;
+	uint8_t dummy1036[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP;
+	uint8_t dummy1037[764];
+	uint32_t SWITCH_CORE_BC_SUPPRESS_REG_SPARE0;
+	uint8_t dummy1038[28];
+	uint32_t SWITCH_CORE_BC_SUPPRESS_REG_SPARE1;
+	uint8_t dummy1039[348];
+	uint64_t SWITCH_CORE_EAP_GLO_CON;
+	uint64_t SWITCH_CORE_EAP_MULTI_ADDR_CTRL;
+	uint32_t SWITCH_CORE_EAP_DIP0;
+	uint8_t dummy1040[60];
+	uint32_t SWITCH_CORE_EAP_DIP1;
+	uint8_t dummy1041[172];
+	uint32_t SWITCH_CORE_EAP_CON_P0;
+	uint8_t dummy1042[60];
+	uint32_t SWITCH_CORE_EAP_CON_P1;
+	uint8_t dummy1043[60];
+	uint32_t SWITCH_CORE_EAP_CON_P2;
+	uint8_t dummy1044[60];
+	uint32_t SWITCH_CORE_EAP_CON_P3;
+	uint8_t dummy1045[60];
+	uint32_t SWITCH_CORE_EAP_CON_P4;
+	uint8_t dummy1046[60];
+	uint32_t SWITCH_CORE_EAP_CON_P5;
+	uint8_t dummy1047[60];
+	uint32_t SWITCH_CORE_EAP_CON_P6;
+	uint8_t dummy1048[60];
+	uint32_t SWITCH_CORE_EAP_CON_P7;
+	uint8_t dummy1049[60];
+	uint32_t SWITCH_CORE_EAP_CON_IMP;
+	uint8_t dummy1050[124];
+	uint32_t SWITCH_CORE_IEEE8021X_REG_SPARE0;
+	uint8_t dummy1051[28];
+	uint32_t SWITCH_CORE_IEEE8021X_REG_SPARE1;
+	uint8_t dummy1052[1116];
+	uint32_t SWITCH_CORE_MST_CON;
+	uint8_t dummy1053[12];
+	uint32_t SWITCH_CORE_MST_AGE;
+	uint8_t dummy1054[108];
+	uint32_t SWITCH_CORE_MST_TAB0;
+	uint8_t dummy1055[28];
+	uint32_t SWITCH_CORE_MST_TAB1;
+	uint8_t dummy1056[28];
+	uint32_t SWITCH_CORE_MST_TAB2;
+	uint8_t dummy1057[28];
+	uint32_t SWITCH_CORE_MST_TAB3;
+	uint8_t dummy1058[28];
+	uint32_t SWITCH_CORE_MST_TAB4;
+	uint8_t dummy1059[28];
+	uint32_t SWITCH_CORE_MST_TAB5;
+	uint8_t dummy1060[28];
+	uint32_t SWITCH_CORE_MST_TAB6;
+	uint8_t dummy1061[28];
+	uint32_t SWITCH_CORE_MST_TAB7;
+	uint8_t dummy1062[284];
+	uint32_t SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL;
+	uint8_t dummy1063[124];
+	uint32_t SWITCH_CORE_IEEE8021S_REG_SPARE0;
+	uint8_t dummy1064[28];
+	uint32_t SWITCH_CORE_IEEE8021S_REG_SPARE1;
+	uint8_t dummy1065[3292];
+	uint32_t SWITCH_CORE_SA_LIMIT_ENABLE;
+	uint8_t dummy1066[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_RST;
+	uint8_t dummy1067[12];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_RST;
+	uint8_t dummy1068[92];
+	uint32_t SWITCH_CORE_TOTAL_SA_LIMIT_CTL;
+	uint8_t dummy1069[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P0;
+	uint8_t dummy1070[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P1;
+	uint8_t dummy1071[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P2;
+	uint8_t dummy1072[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P3;
+	uint8_t dummy1073[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P4;
+	uint8_t dummy1074[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P5;
+	uint8_t dummy1075[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P6;
+	uint8_t dummy1076[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P7;
+	uint8_t dummy1077[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P8;
+	uint8_t dummy1078[108];
+	uint32_t SWITCH_CORE_TOTAL_SA_LRN_CNTR;
+	uint8_t dummy1079[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P0;
+	uint8_t dummy1080[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P1;
+	uint8_t dummy1081[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P2;
+	uint8_t dummy1082[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P3;
+	uint8_t dummy1083[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P4;
+	uint8_t dummy1084[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P5;
+	uint8_t dummy1085[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P6;
+	uint8_t dummy1086[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P7;
+	uint8_t dummy1087[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P8;
+	uint8_t dummy1088[108];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P0;
+	uint8_t dummy1089[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P1;
+	uint8_t dummy1090[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P2;
+	uint8_t dummy1091[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P3;
+	uint8_t dummy1092[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P4;
+	uint8_t dummy1093[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P5;
+	uint8_t dummy1094[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P6;
+	uint8_t dummy1095[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P7;
+	uint8_t dummy1096[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P8;
+	uint8_t dummy1097[28];
+	uint32_t SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT;
+	uint8_t dummy1098[92];
+	uint32_t SWITCH_CORE_MAC_LIMIT_REG_SPARE0;
+	uint8_t dummy1099[28];
+	uint32_t SWITCH_CORE_MAC_LIMIT_REG_SPARE1;
+	uint8_t dummy1100[988];
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P0;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P1;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P2;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P3;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P4;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P5;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P6;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P7;
+	uint32_t SWITCH_CORE_QOS_PRI_CTL_IMP;
+	uint8_t dummy1101[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P0;
+	uint8_t dummy1102[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P1;
+	uint8_t dummy1103[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P2;
+	uint8_t dummy1104[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P3;
+	uint8_t dummy1105[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P4;
+	uint8_t dummy1106[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P5;
+	uint8_t dummy1107[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P6;
+	uint8_t dummy1108[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P7;
+	uint8_t dummy1109[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_IMP;
+	uint8_t dummy1110[124];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P0;
+	uint8_t dummy1111[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P1;
+	uint8_t dummy1112[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P2;
+	uint8_t dummy1113[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P3;
+	uint8_t dummy1114[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P4;
+	uint8_t dummy1115[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P5;
+	uint8_t dummy1116[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P6;
+	uint8_t dummy1117[28];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P7;
+	uint8_t dummy1118[12];
+	uint32_t SWITCH_CORE_P8_WDRR_PENALTY;
+	uint8_t dummy1119[108];
+	uint32_t SWITCH_CORE_SCHEDULER_REG_SPARE0;
+	uint8_t dummy1120[28];
+	uint32_t SWITCH_CORE_SCHEDULER_REG_SPARE1;
+	uint8_t dummy1121[988];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0;
+	uint8_t dummy1122[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1;
+	uint8_t dummy1123[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2;
+	uint8_t dummy1124[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3;
+	uint8_t dummy1125[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4;
+	uint8_t dummy1126[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5;
+	uint8_t dummy1127[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P6;
+	uint8_t dummy1128[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7;
+	uint8_t dummy1129[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP;
+	uint8_t dummy1130[124];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0;
+	uint8_t dummy1131[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1;
+	uint8_t dummy1132[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2;
+	uint8_t dummy1133[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3;
+	uint8_t dummy1134[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4;
+	uint8_t dummy1135[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5;
+	uint8_t dummy1136[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P6;
+	uint8_t dummy1137[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7;
+	uint8_t dummy1138[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP;
+	uint8_t dummy1139[124];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P0;
+	uint8_t dummy1140[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P1;
+	uint8_t dummy1141[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P2;
+	uint8_t dummy1142[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P3;
+	uint8_t dummy1143[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P4;
+	uint8_t dummy1144[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P5;
+	uint8_t dummy1145[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P6;
+	uint8_t dummy1146[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P7;
+	uint8_t dummy1147[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_IMP;
+	uint8_t dummy1148[124];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0;
+	uint8_t dummy1149[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1;
+	uint8_t dummy1150[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2;
+	uint8_t dummy1151[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3;
+	uint8_t dummy1152[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4;
+	uint8_t dummy1153[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5;
+	uint8_t dummy1154[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P6;
+	uint8_t dummy1155[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7;
+	uint8_t dummy1156[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP;
+	uint8_t dummy1157[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0;
+	uint8_t dummy1158[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1;
+	uint8_t dummy1159[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0;
+	uint8_t dummy1160[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1;
+	uint8_t dummy1161[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2;
+	uint8_t dummy1162[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3;
+	uint8_t dummy1163[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4;
+	uint8_t dummy1164[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5;
+	uint8_t dummy1165[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P6;
+	uint8_t dummy1166[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7;
+	uint8_t dummy1167[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP;
+	uint8_t dummy1168[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE;
+	uint8_t dummy1169[12];
+	uint32_t SWITCH_CORE_PORT_SHAPER_ENABLE;
+	uint8_t dummy1170[12];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1171[12];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BLOCKING;
+	uint8_t dummy1172[28];
+	uint32_t SWITCH_CORE_IFG_BYTES;
+	uint8_t dummy1173[140];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P0;
+	uint8_t dummy1174[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P1;
+	uint8_t dummy1175[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P2;
+	uint8_t dummy1176[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P3;
+	uint8_t dummy1177[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P4;
+	uint8_t dummy1178[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P5;
+	uint8_t dummy1179[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P6;
+	uint8_t dummy1180[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P7;
+	uint8_t dummy1181[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP;
+	uint8_t dummy1182[124];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0;
+	uint8_t dummy1183[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1;
+	uint8_t dummy1184[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2;
+	uint8_t dummy1185[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3;
+	uint8_t dummy1186[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4;
+	uint8_t dummy1187[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5;
+	uint8_t dummy1188[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P6;
+	uint8_t dummy1189[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7;
+	uint8_t dummy1190[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP;
+	uint8_t dummy1191[124];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P0;
+	uint8_t dummy1192[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P1;
+	uint8_t dummy1193[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P2;
+	uint8_t dummy1194[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P3;
+	uint8_t dummy1195[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P4;
+	uint8_t dummy1196[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P5;
+	uint8_t dummy1197[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P6;
+	uint8_t dummy1198[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P7;
+	uint8_t dummy1199[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_IMP;
+	uint8_t dummy1200[124];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1201[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1202[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1203[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1204[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1205[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1206[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1207[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1208[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1209[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0;
+	uint8_t dummy1210[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1;
+	uint8_t dummy1211[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1212[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1213[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1214[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1215[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1216[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1217[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1218[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1219[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1220[28];
+	uint32_t SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE;
+	uint8_t dummy1221[12];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_ENABLE;
+	uint8_t dummy1222[12];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1223[12];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_BLOCKING;
+	uint8_t dummy1224[172];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P0;
+	uint8_t dummy1225[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P1;
+	uint8_t dummy1226[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P2;
+	uint8_t dummy1227[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P3;
+	uint8_t dummy1228[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P4;
+	uint8_t dummy1229[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P5;
+	uint8_t dummy1230[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P6;
+	uint8_t dummy1231[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P7;
+	uint8_t dummy1232[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP;
+	uint8_t dummy1233[124];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0;
+	uint8_t dummy1234[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1;
+	uint8_t dummy1235[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2;
+	uint8_t dummy1236[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3;
+	uint8_t dummy1237[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4;
+	uint8_t dummy1238[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5;
+	uint8_t dummy1239[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P6;
+	uint8_t dummy1240[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7;
+	uint8_t dummy1241[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP;
+	uint8_t dummy1242[124];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P0;
+	uint8_t dummy1243[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P1;
+	uint8_t dummy1244[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P2;
+	uint8_t dummy1245[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P3;
+	uint8_t dummy1246[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P4;
+	uint8_t dummy1247[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P5;
+	uint8_t dummy1248[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P6;
+	uint8_t dummy1249[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P7;
+	uint8_t dummy1250[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_IMP;
+	uint8_t dummy1251[124];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1252[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1253[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1254[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1255[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1256[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1257[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1258[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1259[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1260[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0;
+	uint8_t dummy1261[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1;
+	uint8_t dummy1262[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1263[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1264[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1265[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1266[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1267[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1268[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1269[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1270[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1271[28];
+	uint32_t SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE;
+	uint8_t dummy1272[12];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_ENABLE;
+	uint8_t dummy1273[12];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1274[12];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_BLOCKING;
+	uint8_t dummy1275[172];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P0;
+	uint8_t dummy1276[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P1;
+	uint8_t dummy1277[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P2;
+	uint8_t dummy1278[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P3;
+	uint8_t dummy1279[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P4;
+	uint8_t dummy1280[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P5;
+	uint8_t dummy1281[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P6;
+	uint8_t dummy1282[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P7;
+	uint8_t dummy1283[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP;
+	uint8_t dummy1284[124];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0;
+	uint8_t dummy1285[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1;
+	uint8_t dummy1286[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2;
+	uint8_t dummy1287[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3;
+	uint8_t dummy1288[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4;
+	uint8_t dummy1289[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5;
+	uint8_t dummy1290[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P6;
+	uint8_t dummy1291[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7;
+	uint8_t dummy1292[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP;
+	uint8_t dummy1293[124];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P0;
+	uint8_t dummy1294[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P1;
+	uint8_t dummy1295[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P2;
+	uint8_t dummy1296[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P3;
+	uint8_t dummy1297[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P4;
+	uint8_t dummy1298[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P5;
+	uint8_t dummy1299[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P6;
+	uint8_t dummy1300[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P7;
+	uint8_t dummy1301[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_IMP;
+	uint8_t dummy1302[124];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1303[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1304[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1305[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1306[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1307[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1308[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1309[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1310[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1311[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0;
+	uint8_t dummy1312[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1;
+	uint8_t dummy1313[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1314[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1315[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1316[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1317[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1318[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1319[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1320[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1321[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1322[28];
+	uint32_t SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE;
+	uint8_t dummy1323[12];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_ENABLE;
+	uint8_t dummy1324[12];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1325[12];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_BLOCKING;
+	uint8_t dummy1326[172];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P0;
+	uint8_t dummy1327[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P1;
+	uint8_t dummy1328[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P2;
+	uint8_t dummy1329[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P3;
+	uint8_t dummy1330[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P4;
+	uint8_t dummy1331[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P5;
+	uint8_t dummy1332[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P6;
+	uint8_t dummy1333[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P7;
+	uint8_t dummy1334[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP;
+	uint8_t dummy1335[124];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0;
+	uint8_t dummy1336[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1;
+	uint8_t dummy1337[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2;
+	uint8_t dummy1338[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3;
+	uint8_t dummy1339[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4;
+	uint8_t dummy1340[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5;
+	uint8_t dummy1341[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P6;
+	uint8_t dummy1342[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7;
+	uint8_t dummy1343[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP;
+	uint8_t dummy1344[124];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P0;
+	uint8_t dummy1345[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P1;
+	uint8_t dummy1346[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P2;
+	uint8_t dummy1347[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P3;
+	uint8_t dummy1348[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P4;
+	uint8_t dummy1349[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P5;
+	uint8_t dummy1350[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P6;
+	uint8_t dummy1351[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P7;
+	uint8_t dummy1352[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_IMP;
+	uint8_t dummy1353[124];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1354[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1355[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1356[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1357[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1358[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1359[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1360[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1361[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1362[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0;
+	uint8_t dummy1363[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1;
+	uint8_t dummy1364[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1365[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1366[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1367[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1368[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1369[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1370[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1371[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1372[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1373[28];
+	uint32_t SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE;
+	uint8_t dummy1374[12];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_ENABLE;
+	uint8_t dummy1375[12];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1376[12];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_BLOCKING;
+	uint8_t dummy1377[172];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P0;
+	uint8_t dummy1378[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P1;
+	uint8_t dummy1379[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P2;
+	uint8_t dummy1380[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P3;
+	uint8_t dummy1381[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P4;
+	uint8_t dummy1382[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P5;
+	uint8_t dummy1383[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P6;
+	uint8_t dummy1384[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P7;
+	uint8_t dummy1385[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP;
+	uint8_t dummy1386[124];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0;
+	uint8_t dummy1387[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1;
+	uint8_t dummy1388[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2;
+	uint8_t dummy1389[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3;
+	uint8_t dummy1390[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4;
+	uint8_t dummy1391[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5;
+	uint8_t dummy1392[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P6;
+	uint8_t dummy1393[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7;
+	uint8_t dummy1394[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP;
+	uint8_t dummy1395[124];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P0;
+	uint8_t dummy1396[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P1;
+	uint8_t dummy1397[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P2;
+	uint8_t dummy1398[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P3;
+	uint8_t dummy1399[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P4;
+	uint8_t dummy1400[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P5;
+	uint8_t dummy1401[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P6;
+	uint8_t dummy1402[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P7;
+	uint8_t dummy1403[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_IMP;
+	uint8_t dummy1404[124];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1405[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1406[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1407[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1408[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1409[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1410[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1411[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1412[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1413[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0;
+	uint8_t dummy1414[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1;
+	uint8_t dummy1415[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1416[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1417[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1418[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1419[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1420[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1421[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1422[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1423[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1424[28];
+	uint32_t SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE;
+	uint8_t dummy1425[12];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_ENABLE;
+	uint8_t dummy1426[12];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1427[12];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_BLOCKING;
+	uint8_t dummy1428[172];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P0;
+	uint8_t dummy1429[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P1;
+	uint8_t dummy1430[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P2;
+	uint8_t dummy1431[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P3;
+	uint8_t dummy1432[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P4;
+	uint8_t dummy1433[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P5;
+	uint8_t dummy1434[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P6;
+	uint8_t dummy1435[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P7;
+	uint8_t dummy1436[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP;
+	uint8_t dummy1437[124];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0;
+	uint8_t dummy1438[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1;
+	uint8_t dummy1439[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2;
+	uint8_t dummy1440[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3;
+	uint8_t dummy1441[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4;
+	uint8_t dummy1442[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5;
+	uint8_t dummy1443[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P6;
+	uint8_t dummy1444[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7;
+	uint8_t dummy1445[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP;
+	uint8_t dummy1446[124];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P0;
+	uint8_t dummy1447[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P1;
+	uint8_t dummy1448[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P2;
+	uint8_t dummy1449[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P3;
+	uint8_t dummy1450[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P4;
+	uint8_t dummy1451[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P5;
+	uint8_t dummy1452[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P6;
+	uint8_t dummy1453[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P7;
+	uint8_t dummy1454[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_IMP;
+	uint8_t dummy1455[124];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1456[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1457[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1458[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1459[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1460[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1461[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1462[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1463[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1464[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0;
+	uint8_t dummy1465[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1;
+	uint8_t dummy1466[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1467[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1468[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1469[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1470[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1471[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1472[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1473[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1474[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1475[28];
+	uint32_t SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE;
+	uint8_t dummy1476[12];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_ENABLE;
+	uint8_t dummy1477[12];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1478[12];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_BLOCKING;
+	uint8_t dummy1479[172];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P0;
+	uint8_t dummy1480[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P1;
+	uint8_t dummy1481[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P2;
+	uint8_t dummy1482[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P3;
+	uint8_t dummy1483[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P4;
+	uint8_t dummy1484[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P5;
+	uint8_t dummy1485[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P6;
+	uint8_t dummy1486[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P7;
+	uint8_t dummy1487[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP;
+	uint8_t dummy1488[124];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0;
+	uint8_t dummy1489[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1;
+	uint8_t dummy1490[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2;
+	uint8_t dummy1491[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3;
+	uint8_t dummy1492[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4;
+	uint8_t dummy1493[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5;
+	uint8_t dummy1494[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P6;
+	uint8_t dummy1495[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7;
+	uint8_t dummy1496[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP;
+	uint8_t dummy1497[124];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P0;
+	uint8_t dummy1498[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P1;
+	uint8_t dummy1499[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P2;
+	uint8_t dummy1500[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P3;
+	uint8_t dummy1501[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P4;
+	uint8_t dummy1502[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P5;
+	uint8_t dummy1503[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P6;
+	uint8_t dummy1504[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P7;
+	uint8_t dummy1505[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_IMP;
+	uint8_t dummy1506[124];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1507[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1508[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1509[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1510[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1511[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1512[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1513[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1514[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1515[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0;
+	uint8_t dummy1516[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1;
+	uint8_t dummy1517[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1518[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1519[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1520[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1521[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1522[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1523[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1524[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1525[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1526[28];
+	uint32_t SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE;
+	uint8_t dummy1527[12];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_ENABLE;
+	uint8_t dummy1528[12];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1529[12];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_BLOCKING;
+	uint8_t dummy1530[172];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P0;
+	uint8_t dummy1531[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P1;
+	uint8_t dummy1532[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P2;
+	uint8_t dummy1533[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P3;
+	uint8_t dummy1534[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P4;
+	uint8_t dummy1535[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P5;
+	uint8_t dummy1536[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P6;
+	uint8_t dummy1537[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P7;
+	uint8_t dummy1538[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP;
+	uint8_t dummy1539[124];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0;
+	uint8_t dummy1540[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1;
+	uint8_t dummy1541[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2;
+	uint8_t dummy1542[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3;
+	uint8_t dummy1543[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4;
+	uint8_t dummy1544[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5;
+	uint8_t dummy1545[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P6;
+	uint8_t dummy1546[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7;
+	uint8_t dummy1547[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP;
+	uint8_t dummy1548[124];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P0;
+	uint8_t dummy1549[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P1;
+	uint8_t dummy1550[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P2;
+	uint8_t dummy1551[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P3;
+	uint8_t dummy1552[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P4;
+	uint8_t dummy1553[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P5;
+	uint8_t dummy1554[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P6;
+	uint8_t dummy1555[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P7;
+	uint8_t dummy1556[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_IMP;
+	uint8_t dummy1557[124];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1558[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1559[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1560[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1561[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1562[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1563[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1564[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1565[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1566[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0;
+	uint8_t dummy1567[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1;
+	uint8_t dummy1568[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1569[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1570[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1571[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1572[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1573[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1574[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1575[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1576[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1577[28];
+	uint32_t SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE;
+	uint8_t dummy1578[12];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_ENABLE;
+	uint8_t dummy1579[12];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1580[12];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_BLOCKING;
+	uint8_t dummy1581[65708];
+	uint32_t SWITCH_CORE_MIB_SNAPSHOT_CTL;
+	uint8_t dummy1582[2044];
+	uint32_t SWITCH_CORE_S_TxOctets;
+	uint8_t dummy1583[60];
+	uint32_t SWITCH_CORE_S_TxDropPkts;
+	uint8_t dummy1584[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ0;
+	uint8_t dummy1585[28];
+	uint32_t SWITCH_CORE_S_TxBroadcastPkts;
+	uint8_t dummy1586[28];
+	uint32_t SWITCH_CORE_S_TxMulticastPkts;
+	uint8_t dummy1587[28];
+	uint32_t SWITCH_CORE_S_TxUnicastPkts;
+	uint8_t dummy1588[28];
+	uint32_t SWITCH_CORE_S_TxCollisions;
+	uint8_t dummy1589[28];
+	uint32_t SWITCH_CORE_S_TxSingleCollision;
+	uint8_t dummy1590[28];
+	uint32_t SWITCH_CORE_S_TxMultipleCollision;
+	uint8_t dummy1591[28];
+	uint32_t SWITCH_CORE_S_TxDeferredTransmit;
+	uint8_t dummy1592[28];
+	uint32_t SWITCH_CORE_S_TxLateCollision;
+	uint8_t dummy1593[28];
+	uint32_t SWITCH_CORE_S_TxExcessiveCollision;
+	uint8_t dummy1594[28];
+	uint32_t SWITCH_CORE_S_TxFrameInDisc;
+	uint8_t dummy1595[28];
+	uint32_t SWITCH_CORE_S_TxPausePkts;
+	uint8_t dummy1596[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ1;
+	uint8_t dummy1597[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ2;
+	uint8_t dummy1598[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ3;
+	uint8_t dummy1599[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ4;
+	uint8_t dummy1600[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ5;
+	uint8_t dummy1601[28];
+	uint32_t SWITCH_CORE_S_RxOctets;
+	uint8_t dummy1602[60];
+	uint32_t SWITCH_CORE_S_RxUndersizePkts;
+	uint8_t dummy1603[28];
+	uint32_t SWITCH_CORE_S_RxPausePkts;
+	uint8_t dummy1604[28];
+	uint32_t SWITCH_CORE_S_RxPkts64Octets;
+	uint8_t dummy1605[28];
+	uint32_t SWITCH_CORE_S_RxPkts65to127Octets;
+	uint8_t dummy1606[28];
+	uint32_t SWITCH_CORE_S_RxPkts128to255Octets;
+	uint8_t dummy1607[28];
+	uint32_t SWITCH_CORE_S_RxPkts256to511Octets;
+	uint8_t dummy1608[28];
+	uint32_t SWITCH_CORE_S_RxPkts512to1023Octets;
+	uint8_t dummy1609[28];
+	uint32_t SWITCH_CORE_S_RxPkts1024toMaxPktOctets;
+	uint8_t dummy1610[28];
+	uint32_t SWITCH_CORE_S_RxOversizePkts;
+	uint8_t dummy1611[28];
+	uint32_t SWITCH_CORE_S_RxJabbers;
+	uint8_t dummy1612[28];
+	uint32_t SWITCH_CORE_S_RxAlignmentErrors;
+	uint8_t dummy1613[28];
+	uint32_t SWITCH_CORE_S_RxFCSErrors;
+	uint8_t dummy1614[28];
+	uint32_t SWITCH_CORE_S_RxGoodOctets;
+	uint8_t dummy1615[60];
+	uint32_t SWITCH_CORE_S_RxDropPkts;
+	uint8_t dummy1616[28];
+	uint32_t SWITCH_CORE_S_RxUnicastPkts;
+	uint8_t dummy1617[28];
+	uint32_t SWITCH_CORE_S_RxMulticastPkts;
+	uint8_t dummy1618[28];
+	uint32_t SWITCH_CORE_S_RxBroadcastPkts;
+	uint8_t dummy1619[28];
+	uint32_t SWITCH_CORE_S_RxSAChanges;
+	uint8_t dummy1620[28];
+	uint32_t SWITCH_CORE_S_RxFragments;
+	uint8_t dummy1621[28];
+	uint32_t SWITCH_CORE_S_RxJumboPkt;
+	uint8_t dummy1622[28];
+	uint32_t SWITCH_CORE_S_RxSymblErr;
+	uint8_t dummy1623[28];
+	uint32_t SWITCH_CORE_S_InRangeErrCount;
+	uint8_t dummy1624[28];
+	uint32_t SWITCH_CORE_S_OutRangeErrCount;
+	uint8_t dummy1625[28];
+	uint32_t SWITCH_CORE_S_EEE_LPI_EVENT;
+	uint8_t dummy1626[28];
+	uint32_t SWITCH_CORE_S_EEE_LPI_DURATION;
+	uint8_t dummy1627[28];
+	uint32_t SWITCH_CORE_S_RxDiscard;
+	uint8_t dummy1628[60];
+	uint32_t SWITCH_CORE_S_TxQPKTQ6;
+	uint8_t dummy1629[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ7;
+	uint8_t dummy1630[28];
+	uint32_t SWITCH_CORE_S_TxPkts64Octets;
+	uint8_t dummy1631[28];
+	uint32_t SWITCH_CORE_S_TxPkts65to127Octets;
+	uint8_t dummy1632[28];
+	uint32_t SWITCH_CORE_S_TxPkts128to255Octets;
+	uint8_t dummy1633[28];
+	uint32_t SWITCH_CORE_S_TxPkts256to511Octets;
+	uint8_t dummy1634[28];
+	uint32_t SWITCH_CORE_S_TxPkts512to1023Octets;
+	uint8_t dummy1635[28];
+	uint32_t SWITCH_CORE_S_TxPkts1024toMaxPktOctets;
+	uint8_t dummy1636[220];
+	uint32_t SWITCH_CORE_LPDET_CFG;
+	uint8_t dummy1637[12];
+	uint64_t SWITCH_CORE_DF_TIMER;
+	uint32_t SWITCH_CORE_LED_PORTMAP;
+	uint8_t dummy1638[12];
+	uint32_t SWITCH_CORE_MODULE_ID0;
+	uint8_t dummy1639[44];
+	uint32_t SWITCH_CORE_MODULE_ID1;
+	uint8_t dummy1640[44];
+	uint32_t SWITCH_CORE_LPDET_SA;
+	uint8_t dummy1641[116];
+	uint32_t SWITCH_CORE_LPDET_REG_SPARE0;
+	uint8_t dummy1642[28];
+	uint32_t SWITCH_CORE_LPDET_REG_SPARE1;
+	uint8_t dummy1643[1756];
+	uint64_t SWITCH_CORE_BPM_CTRL;
+	uint64_t SWITCH_CORE_BPM_PSM_OVR_CTRL;
+	uint32_t SWITCH_CORE_BPM_PSM_TIME_CFG;
+	uint8_t dummy1644[12];
+	uint32_t SWITCH_CORE_BPM_PSM_THD_CFG;
+	uint8_t dummy1645[28];
+	uint32_t SWITCH_CORE_ROW_VMASK_OVR_CTRL;
+	uint8_t dummy1646[28];
+	uint32_t SWITCH_CORE_BPM_STS;
+	uint8_t dummy1647[28];
+	uint32_t SWITCH_CORE_BPM_PDA_OVR_CTRL;
+	uint8_t dummy1648[12];
+	uint32_t SWITCH_CORE_PDA_TIMEOUT_CFG;
+	uint8_t dummy1649[12];
+	uint32_t SWITCH_CORE_PDA_SETUP_TIME_CFG;
+	uint8_t dummy1650[12];
+	uint32_t SWITCH_CORE_PDA_HOLD_TIME_CFG;
+	uint8_t dummy1651[12];
+	uint32_t SWITCH_CORE_PBB_VBUFCNT_P0;
+	uint8_t dummy1652[12];
+	uint32_t SWITCH_CORE_PBB_VBUFCNT_P1;
+	uint8_t dummy1653[12];
+	uint32_t SWITCH_CORE_PBB_VBUFCNT_P2;
+	uint8_t dummy1654[12];
+	uint32_t SWITCH_CORE_RCY_TIME_CFG;
+	uint8_t dummy1655[12];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON_CTRL;
+	uint8_t dummy1656[60];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON0;
+	uint8_t dummy1657[60];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON1;
+	uint8_t dummy1658[60];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON2;
+	uint8_t dummy1659[316];
+	uint32_t SWITCH_CORE_BPM_REG_SPARE0;
+	uint8_t dummy1660[28];
+	uint32_t SWITCH_CORE_BPM_REG_SPARE1;
+	uint8_t dummy1661[60636];
+	uint32_t SWITCH_CORE_TRREG_CTRL0;
+	uint8_t dummy1662[28];
+	uint32_t SWITCH_CORE_TRREG_CTRL1;
+	uint8_t dummy1663[28];
+	uint32_t SWITCH_CORE_TRREG_CTRL2;
+	uint8_t dummy1664[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0;
+	uint8_t dummy1665[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1;
+	uint8_t dummy1666[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2;
+	uint8_t dummy1667[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3;
+	uint8_t dummy1668[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4;
+	uint8_t dummy1669[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5;
+	uint8_t dummy1670[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P6;
+	uint8_t dummy1671[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7;
+	uint8_t dummy1672[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP;
+	uint8_t dummy1673[124];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0;
+	uint8_t dummy1674[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1;
+	uint8_t dummy1675[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2;
+	uint8_t dummy1676[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3;
+	uint8_t dummy1677[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4;
+	uint8_t dummy1678[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5;
+	uint8_t dummy1679[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P6;
+	uint8_t dummy1680[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7;
+	uint8_t dummy1681[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP;
+	uint8_t dummy1682[124];
+	uint32_t SWITCH_CORE_TRREG_REG_SPARE0;
+	uint8_t dummy1683[28];
+	uint32_t SWITCH_CORE_TRREG_REG_SPARE1;
+	uint8_t dummy1684[604];
+	uint32_t SWITCH_CORE_EEE_EN_CTRL;
+	uint8_t dummy1685[12];
+	uint32_t SWITCH_CORE_EEE_LPI_ASSERT;
+	uint8_t dummy1686[12];
+	uint32_t SWITCH_CORE_EEE_LPI_INDICATE;
+	uint8_t dummy1687[12];
+	uint32_t SWITCH_CORE_EEE_RX_IDLE_SYMBOL;
+	uint8_t dummy1688[12];
+	uint32_t SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE;
+	uint8_t dummy1689[28];
+	uint32_t SWITCH_CORE_EEE_PIPELINE_TIMER;
+	uint8_t dummy1690[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P0;
+	uint8_t dummy1691[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P1;
+	uint8_t dummy1692[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P2;
+	uint8_t dummy1693[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P3;
+	uint8_t dummy1694[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P4;
+	uint8_t dummy1695[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P5;
+	uint8_t dummy1696[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P6;
+	uint8_t dummy1697[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P7;
+	uint8_t dummy1698[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP;
+	uint8_t dummy1699[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P0;
+	uint8_t dummy1700[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P1;
+	uint8_t dummy1701[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P2;
+	uint8_t dummy1702[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P3;
+	uint8_t dummy1703[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P4;
+	uint8_t dummy1704[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P5;
+	uint8_t dummy1705[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P6;
+	uint8_t dummy1706[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P7;
+	uint8_t dummy1707[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP;
+	uint8_t dummy1708[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P0;
+	uint8_t dummy1709[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P1;
+	uint8_t dummy1710[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P2;
+	uint8_t dummy1711[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P3;
+	uint8_t dummy1712[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P4;
+	uint8_t dummy1713[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P5;
+	uint8_t dummy1714[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P6;
+	uint8_t dummy1715[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7;
+	uint8_t dummy1716[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP;
+	uint8_t dummy1717[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P0;
+	uint8_t dummy1718[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P1;
+	uint8_t dummy1719[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P2;
+	uint8_t dummy1720[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P3;
+	uint8_t dummy1721[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P4;
+	uint8_t dummy1722[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P5;
+	uint8_t dummy1723[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P6;
+	uint8_t dummy1724[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7;
+	uint8_t dummy1725[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP;
+	uint8_t dummy1726[28];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P0;
+	uint8_t dummy1727[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P1;
+	uint8_t dummy1728[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P2;
+	uint8_t dummy1729[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P3;
+	uint8_t dummy1730[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P4;
+	uint8_t dummy1731[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P5;
+	uint8_t dummy1732[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P6;
+	uint8_t dummy1733[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P7;
+	uint8_t dummy1734[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P8;
+	uint8_t dummy1735[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P0;
+	uint8_t dummy1736[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P1;
+	uint8_t dummy1737[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P2;
+	uint8_t dummy1738[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P3;
+	uint8_t dummy1739[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P4;
+	uint8_t dummy1740[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P5;
+	uint8_t dummy1741[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P6;
+	uint8_t dummy1742[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P7;
+	uint8_t dummy1743[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_IMP;
+	uint8_t dummy1744[12];
+	uint32_t SWITCH_CORE_EEE_GLB_CONG_TH;
+	uint8_t dummy1745[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q0;
+	uint8_t dummy1746[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q1;
+	uint8_t dummy1747[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q2;
+	uint8_t dummy1748[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q3;
+	uint8_t dummy1749[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q4;
+	uint8_t dummy1750[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q5;
+	uint8_t dummy1751[20];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q6;
+	uint8_t dummy1752[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q7;
+	uint8_t dummy1753[44];
+	uint32_t SWITCH_CORE_EEE_CTL_REG_SPARE0;
+	uint8_t dummy1754[36];
+	uint32_t SWITCH_CORE_EEE_CTL_REG_SPARE1;
+	uint8_t dummy1755[52];
+	uint64_t SWITCH_CORE_EEE_DEBUG;
+	uint32_t SWITCH_CORE_EEE_LINK_DLY_TIMER;
+	uint8_t dummy1756[28];
+	uint32_t SWITCH_CORE_EEE_STATE;
+	uint8_t dummy1757[156];
+	uint32_t SWITCH_CORE_PORT_ENABLE;
+	uint8_t dummy1758[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P0;
+	uint8_t dummy1759[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P1;
+	uint8_t dummy1760[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P2;
+	uint8_t dummy1761[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P3;
+	uint8_t dummy1762[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P4;
+	uint8_t dummy1763[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P5;
+	uint8_t dummy1764[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P7;
+	uint8_t dummy1765[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_IMP;
+	uint8_t dummy1766[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P0;
+	uint8_t dummy1767[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P1;
+	uint8_t dummy1768[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P2;
+	uint8_t dummy1769[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P3;
+	uint8_t dummy1770[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P4;
+	uint8_t dummy1771[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P5;
+	uint8_t dummy1772[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P7;
+	uint8_t dummy1773[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_IMP;
+	uint8_t dummy1774[12];
+	uint32_t SWITCH_CORE_TX_TS_CAP;
+	uint8_t dummy1775[12];
+	uint32_t SWITCH_CORE_RX_TS_CAP;
+	uint8_t dummy1776[12];
+	uint32_t SWITCH_CORE_RX_TX_OPTION;
+	uint8_t dummy1777[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_LINK_DELAY_LSB;
+	uint8_t dummy1778[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_LINK_DELAY_MSB;
+	uint8_t dummy1779[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_LINK_DELAY_LSB;
+	uint8_t dummy1780[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_LINK_DELAY_MSB;
+	uint8_t dummy1781[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_LINK_DELAY_LSB;
+	uint8_t dummy1782[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_LINK_DELAY_MSB;
+	uint8_t dummy1783[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_LINK_DELAY_LSB;
+	uint8_t dummy1784[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_LINK_DELAY_MSB;
+	uint8_t dummy1785[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_LINK_DELAY_LSB;
+	uint8_t dummy1786[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_LINK_DELAY_MSB;
+	uint8_t dummy1787[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_LINK_DELAY_LSB;
+	uint8_t dummy1788[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_LINK_DELAY_MSB;
+	uint8_t dummy1789[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_LINK_DELAY_LSB;
+	uint8_t dummy1790[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_LINK_DELAY_MSB;
+	uint8_t dummy1791[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_LINK_DELAY_LSB;
+	uint8_t dummy1792[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_LINK_DELAY_MSB;
+	uint8_t dummy1793[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_TS_OFFSET_LSB;
+	uint8_t dummy1794[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_TS_OFFSET_MSB;
+	uint8_t dummy1795[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_TS_OFFSET_LSB;
+	uint8_t dummy1796[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_TS_OFFSET_MSB;
+	uint8_t dummy1797[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_TS_OFFSET_LSB;
+	uint8_t dummy1798[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_TS_OFFSET_MSB;
+	uint8_t dummy1799[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_TS_OFFSET_LSB;
+	uint8_t dummy1800[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_TS_OFFSET_MSB;
+	uint8_t dummy1801[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_TS_OFFSET_LSB;
+	uint8_t dummy1802[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_TS_OFFSET_MSB;
+	uint8_t dummy1803[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_TS_OFFSET_LSB;
+	uint8_t dummy1804[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_TS_OFFSET_MSB;
+	uint8_t dummy1805[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_TS_OFFSET_LSB;
+	uint8_t dummy1806[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_TS_OFFSET_MSB;
+	uint8_t dummy1807[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_TS_OFFSET_LSB;
+	uint8_t dummy1808[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_TS_OFFSET_MSB;
+	uint8_t dummy1809[12];
+	uint32_t SWITCH_CORE_TX_PORT_0_TS_OFFSET_LSB;
+	uint8_t dummy1810[12];
+	uint32_t SWITCH_CORE_TX_PORT_0_TS_OFFSET_MSB;
+	uint8_t dummy1811[12];
+	uint32_t SWITCH_CORE_TX_PORT_1_TS_OFFSET_LSB;
+	uint8_t dummy1812[12];
+	uint32_t SWITCH_CORE_TX_PORT_1_TS_OFFSET_MSB;
+	uint8_t dummy1813[12];
+	uint32_t SWITCH_CORE_TX_PORT_2_TS_OFFSET_LSB;
+	uint8_t dummy1814[12];
+	uint32_t SWITCH_CORE_TX_PORT_2_TS_OFFSET_MSB;
+	uint8_t dummy1815[12];
+	uint32_t SWITCH_CORE_TX_PORT_3_TS_OFFSET_LSB;
+	uint8_t dummy1816[12];
+	uint32_t SWITCH_CORE_TX_PORT_3_TS_OFFSET_MSB;
+	uint8_t dummy1817[12];
+	uint32_t SWITCH_CORE_TX_PORT_4_TS_OFFSET_LSB;
+	uint8_t dummy1818[12];
+	uint32_t SWITCH_CORE_TX_PORT_4_TS_OFFSET_MSB;
+	uint8_t dummy1819[12];
+	uint32_t SWITCH_CORE_TX_PORT_5_TS_OFFSET_LSB;
+	uint8_t dummy1820[12];
+	uint32_t SWITCH_CORE_TX_PORT_5_TS_OFFSET_MSB;
+	uint8_t dummy1821[12];
+	uint32_t SWITCH_CORE_TX_PORT_7_TS_OFFSET_LSB;
+	uint8_t dummy1822[12];
+	uint32_t SWITCH_CORE_TX_PORT_7_TS_OFFSET_MSB;
+	uint8_t dummy1823[12];
+	uint32_t SWITCH_CORE_TX_PORT_8_TS_OFFSET_LSB;
+	uint8_t dummy1824[12];
+	uint32_t SWITCH_CORE_TX_PORT_8_TS_OFFSET_MSB;
+	uint8_t dummy1825[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P0;
+	uint8_t dummy1826[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P1;
+	uint8_t dummy1827[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P2;
+	uint8_t dummy1828[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P3;
+	uint8_t dummy1829[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P4;
+	uint8_t dummy1830[12];
+	uint32_t SWITCH_CORE_DPLL_DB_LSB;
+	uint8_t dummy1831[12];
+	uint32_t SWITCH_CORE_DPLL_DB_MSB;
+	uint8_t dummy1832[12];
+	uint32_t SWITCH_CORE_DPLL_DB_SEL;
+	uint8_t dummy1833[12];
+	uint32_t SWITCH_CORE_SHD_CTL;
+	uint8_t dummy1834[12];
+	uint32_t SWITCH_CORE_SHD_LD;
+	uint8_t dummy1835[12];
+	uint32_t SWITCH_CORE_INT_MASK;
+	uint8_t dummy1836[12];
+	uint32_t SWITCH_CORE_INT_STAT;
+	uint8_t dummy1837[12];
+	uint32_t SWITCH_CORE_TX_CTL;
+	uint8_t dummy1838[12];
+	uint32_t SWITCH_CORE_RX_CTL;
+	uint8_t dummy1839[12];
+	uint32_t SWITCH_CORE_RX_TX_CTL;
+	uint8_t dummy1840[12];
+	uint32_t SWITCH_CORE_VLAN_ITPID;
+	uint8_t dummy1841[12];
+	uint32_t SWITCH_CORE_VLAN_OTPID;
+	uint8_t dummy1842[12];
+	uint32_t SWITCH_CORE_OTHER_OTPID;
+	uint8_t dummy1843[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_1;
+	uint8_t dummy1844[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_2_N_P0;
+	uint8_t dummy1845[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_2_N_P1;
+	uint8_t dummy1846[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_2_N_P2;
+	uint8_t dummy1847[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_3_N_P0;
+	uint8_t dummy1848[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_3_N_P1;
+	uint8_t dummy1849[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_4;
+	uint8_t dummy1850[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_5;
+	uint8_t dummy1851[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_6;
+	uint8_t dummy1852[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P0;
+	uint8_t dummy1853[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P1;
+	uint8_t dummy1854[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P2;
+	uint8_t dummy1855[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P3;
+	uint8_t dummy1856[12];
+	uint32_t SWITCH_CORE_NSE_NCO_1_N_P0;
+	uint8_t dummy1857[12];
+	uint32_t SWITCH_CORE_NSE_NCO_1_N_P1;
+	uint8_t dummy1858[12];
+	uint32_t SWITCH_CORE_NSE_NCO_2_N_P0;
+	uint8_t dummy1859[12];
+	uint32_t SWITCH_CORE_NSE_NCO_2_N_P1;
+	uint8_t dummy1860[12];
+	uint32_t SWITCH_CORE_NSE_NCO_2_N_P2;
+	uint8_t dummy1861[12];
+	uint32_t SWITCH_CORE_NSE_NCO_3_0;
+	uint8_t dummy1862[12];
+	uint32_t SWITCH_CORE_NSE_NCO_3_1;
+	uint8_t dummy1863[12];
+	uint32_t SWITCH_CORE_NSE_NCO_3_2;
+	uint8_t dummy1864[12];
+	uint32_t SWITCH_CORE_NSE_NCO_4;
+	uint8_t dummy1865[12];
+	uint32_t SWITCH_CORE_NSE_NCO_5_0;
+	uint8_t dummy1866[12];
+	uint32_t SWITCH_CORE_NSE_NCO_5_1;
+	uint8_t dummy1867[12];
+	uint32_t SWITCH_CORE_NSE_NCO_5_2;
+	uint8_t dummy1868[12];
+	uint32_t SWITCH_CORE_NSE_NCO_6;
+	uint8_t dummy1869[12];
+	uint32_t SWITCH_CORE_NSE_NCO_7_0;
+	uint8_t dummy1870[12];
+	uint32_t SWITCH_CORE_NSE_NCO_7_1;
+	uint8_t dummy1871[12];
+	uint32_t SWITCH_CORE_TX_COUNTER;
+	uint8_t dummy1872[12];
+	uint32_t SWITCH_CORE_RX_COUNTER;
+	uint8_t dummy1873[12];
+	uint32_t SWITCH_CORE_RX_TX_1588_COUNTER;
+	uint8_t dummy1874[12];
+	uint32_t SWITCH_CORE_TS_READ_START_END;
+	uint8_t dummy1875[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_0;
+	uint8_t dummy1876[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_1;
+	uint8_t dummy1877[140];
+	uint32_t SWITCH_CORE_HEARTBEAT_2;
+	uint8_t dummy1878[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_N_P0;
+	uint8_t dummy1879[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_N_P1;
+	uint8_t dummy1880[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_N_P2;
+	uint8_t dummy1881[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_N_P0;
+	uint8_t dummy1882[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_N_P1;
+	uint8_t dummy1883[12];
+	uint32_t SWITCH_CORE_CNTR_DBG;
+	uint8_t dummy1884[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE1;
+	uint8_t dummy1885[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE2;
+	uint8_t dummy1886[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE3;
+	uint8_t dummy1887[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE4;
+	uint8_t dummy1888[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE5;
+	uint8_t dummy1889[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE6;
+	uint8_t dummy1890[12];
+	uint32_t SWITCH_CORE_MPLS_TX_CNTL;
+	uint8_t dummy1891[12];
+	uint32_t SWITCH_CORE_MPLS_RX_CNTL;
+	uint8_t dummy1892[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_MASK_LSB;
+	uint8_t dummy1893[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_MASK_MSB;
+	uint8_t dummy1894[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_VALUE_LSB;
+	uint8_t dummy1895[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_VALUE_MSB;
+	uint8_t dummy1896[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_MASK_LSB;
+	uint8_t dummy1897[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_MASK_MSB;
+	uint8_t dummy1898[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_VALUE_LSB;
+	uint8_t dummy1899[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_VALUE_MSB;
+	uint8_t dummy1900[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_MASK_LSB;
+	uint8_t dummy1901[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_MASK_MSB;
+	uint8_t dummy1902[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_VALUE_LSB;
+	uint8_t dummy1903[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_VALUE_MSB;
+	uint8_t dummy1904[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_MASK_LSB;
+	uint8_t dummy1905[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_MASK_MSB;
+	uint8_t dummy1906[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_VALUE_LSB;
+	uint8_t dummy1907[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_VALUE_MSB;
+	uint8_t dummy1908[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_MASK_LSB;
+	uint8_t dummy1909[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_MASK_MSB;
+	uint8_t dummy1910[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_VALUE_LSB;
+	uint8_t dummy1911[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_VALUE_MSB;
+	uint8_t dummy1912[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_MASK_LSB;
+	uint8_t dummy1913[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_MASK_MSB;
+	uint8_t dummy1914[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_VALUE_LSB;
+	uint8_t dummy1915[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_VALUE_MSB;
+	uint8_t dummy1916[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_MASK_LSB;
+	uint8_t dummy1917[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_MASK_MSB;
+	uint8_t dummy1918[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_VALUE_LSB;
+	uint8_t dummy1919[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_VALUE_MSB;
+	uint8_t dummy1920[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_MASK_LSB;
+	uint8_t dummy1921[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_MASK_MSB;
+	uint8_t dummy1922[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_VALUE_LSB;
+	uint8_t dummy1923[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_VALUE_MSB;
+	uint8_t dummy1924[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_MASK_LSB;
+	uint8_t dummy1925[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_MASK_MSB;
+	uint8_t dummy1926[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_VALUE_LSB;
+	uint8_t dummy1927[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_VALUE_MSB;
+	uint8_t dummy1928[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_MASK_LSB;
+	uint8_t dummy1929[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_MASK_MSB;
+	uint8_t dummy1930[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_VALUE_LSB;
+	uint8_t dummy1931[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_VALUE_MSB;
+	uint8_t dummy1932[12];
+	uint32_t SWITCH_CORE_RX_TX_1588_COUNTER1;
+	uint8_t dummy1933[12];
+	uint32_t SWITCH_CORE_RX_CF_SPEC;
+	uint8_t dummy1934[12];
+	uint32_t SWITCH_CORE_TX_CF_SPEC;
+	uint8_t dummy1935[12];
+	uint32_t SWITCH_CORE_MPLS_PACKET_ENABLE;
+	uint8_t dummy1936[12];
+	uint32_t SWITCH_CORE_TIMECODE_SEL;
+	uint8_t dummy1937[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_3;
+	uint8_t dummy1938[12];
+	uint32_t SWITCH_CORE_TIME_STAMP;
+	uint8_t dummy1939[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_TX_CONTROL;
+	uint8_t dummy1940[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_RX_CONTROL;
+	uint8_t dummy1941[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE1;
+	uint8_t dummy1942[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE2;
+	uint8_t dummy1943[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE3;
+	uint8_t dummy1944[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE4;
+	uint8_t dummy1945[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE5;
+	uint8_t dummy1946[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE6;
+	uint8_t dummy1947[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE7;
+	uint8_t dummy1948[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE8;
+	uint8_t dummy1949[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE9;
+	uint8_t dummy1950[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE10;
+	uint8_t dummy1951[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE11;
+	uint8_t dummy1952[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE12;
+	uint8_t dummy1953[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE13;
+	uint8_t dummy1954[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_IETF_OFFSET;
+	uint8_t dummy1955[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P0;
+	uint8_t dummy1956[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P1;
+	uint8_t dummy1957[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P2;
+	uint8_t dummy1958[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P3;
+	uint8_t dummy1959[12];
+	uint32_t SWITCH_CORE_NTP_NCO_FREQ_0;
+	uint8_t dummy1960[12];
+	uint32_t SWITCH_CORE_NTP_NCO_FREQ_1;
+	uint8_t dummy1961[12];
+	uint32_t SWITCH_CORE_NTP_DOWN_CNTER_0;
+	uint8_t dummy1962[12];
+	uint32_t SWITCH_CORE_NTP_DOWN_CNTER_1;
+	uint8_t dummy1963[12];
+	uint32_t SWITCH_CORE_NTP_ERR_LSB;
+	uint8_t dummy1964[12];
+	uint32_t SWITCH_CORE_NTP_ERR_MSB;
+	uint8_t dummy1965[12];
+	uint32_t SWITCH_CORE_DM_MAC_L1_0;
+	uint8_t dummy1966[12];
+	uint32_t SWITCH_CORE_DM_MAC_L1_1;
+	uint8_t dummy1967[12];
+	uint32_t SWITCH_CORE_DM_MAC_L1_2;
+	uint8_t dummy1968[12];
+	uint32_t SWITCH_CORE_DM_MAC_L2_0;
+	uint8_t dummy1969[12];
+	uint32_t SWITCH_CORE_DM_MAC_L2_1;
+	uint8_t dummy1970[12];
+	uint32_t SWITCH_CORE_DM_MAC_L2_2;
+	uint8_t dummy1971[12];
+	uint32_t SWITCH_CORE_DM_MAC_L3_0;
+	uint8_t dummy1972[12];
+	uint32_t SWITCH_CORE_DM_MAC_L3_1;
+	uint8_t dummy1973[12];
+	uint32_t SWITCH_CORE_DM_MAC_L3_2;
+	uint8_t dummy1974[12];
+	uint32_t SWITCH_CORE_DM_MAC_CTL_0;
+	uint8_t dummy1975[12];
+	uint32_t SWITCH_CORE_DM_MAC_CTL_1;
+	uint8_t dummy1976[12];
+	uint32_t SWITCH_CORE_DM_MAC_CTL_2;
+	uint8_t dummy1977[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_3;
+	uint8_t dummy1978[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_4;
+	uint8_t dummy1979[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P0;
+	uint8_t dummy1980[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P1;
+	uint8_t dummy1981[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P2;
+	uint8_t dummy1982[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P3;
+	uint8_t dummy1983[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P4;
+	uint8_t dummy1984[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P5;
+	uint8_t dummy1985[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P6;
+	uint8_t dummy1986[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P7;
+	uint8_t dummy1987[12];
+	uint32_t SWITCH_CORE_MEM_COUNTER;
+	uint8_t dummy1988[12];
+	uint32_t SWITCH_CORE_TIMESTAMP_DELTA;
+	uint8_t dummy1989[12];
+	uint32_t SWITCH_CORE_SOP_SEL;
+	uint8_t dummy1990[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_3;
+	uint8_t dummy1991[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_4;
+	uint8_t dummy1992[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_5;
+	uint8_t dummy1993[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_6;
+	uint8_t dummy1994[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_7;
+	uint8_t dummy1995[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_8;
+	uint8_t dummy1996[12];
+	uint32_t SWITCH_CORE_INBAND_SPARE1;
+	uint8_t dummy1997[140];
+	uint32_t SWITCH_CORE_RED_CONTROL;
+	uint8_t dummy1998[12];
+	uint32_t SWITCH_CORE_TC2RED_PROFILE_TABLE;
+	uint8_t dummy1999[12];
+	uint32_t SWITCH_CORE_RED_EGRESS_BYPASS;
+	uint8_t dummy2000[12];
+	uint32_t SWITCH_CORE_RED_AQD_CONTROL;
+	uint8_t dummy2001[12];
+	uint32_t SWITCH_CORE_RED_EXPONENT;
+	uint8_t dummy2002[12];
+	uint32_t SWITCH_CORE_RED_DROP_ADD_TO_MIB;
+	uint8_t dummy2003[44];
+	uint32_t SWITCH_CORE_RED_PROFILE_DEFAULT;
+	uint8_t dummy2004[28];
+	uint32_t SWITCH_CORE_WRED_REG_SPARE0;
+	uint8_t dummy2005[28];
+	uint32_t SWITCH_CORE_WRED_REG_SPARE1;
+	uint8_t dummy2006[60];
+	uint32_t SWITCH_CORE_RED_PROFILE0;
+	uint8_t dummy2007[28];
+	uint32_t SWITCH_CORE_RED_PROFILE1;
+	uint8_t dummy2008[28];
+	uint32_t SWITCH_CORE_RED_PROFILE2;
+	uint8_t dummy2009[28];
+	uint32_t SWITCH_CORE_RED_PROFILE3;
+	uint8_t dummy2010[28];
+	uint32_t SWITCH_CORE_RED_PROFILE4;
+	uint8_t dummy2011[28];
+	uint32_t SWITCH_CORE_RED_PROFILE5;
+	uint8_t dummy2012[28];
+	uint32_t SWITCH_CORE_RED_PROFILE6;
+	uint8_t dummy2013[28];
+	uint32_t SWITCH_CORE_RED_PROFILE7;
+	uint8_t dummy2014[28];
+	uint32_t SWITCH_CORE_RED_PROFILE8;
+	uint8_t dummy2015[28];
+	uint32_t SWITCH_CORE_RED_PROFILE9;
+	uint8_t dummy2016[28];
+	uint32_t SWITCH_CORE_RED_PROFILE10;
+	uint8_t dummy2017[28];
+	uint32_t SWITCH_CORE_RED_PROFILE11;
+	uint8_t dummy2018[28];
+	uint32_t SWITCH_CORE_RED_PROFILE12;
+	uint8_t dummy2019[28];
+	uint32_t SWITCH_CORE_RED_PROFILE13;
+	uint8_t dummy2020[28];
+	uint32_t SWITCH_CORE_RED_PROFILE14;
+	uint8_t dummy2021[28];
+	uint32_t SWITCH_CORE_RED_PROFILE15;
+	uint8_t dummy2022[124];
+	uint32_t SWITCH_CORE_RED_DROP_CNTR_RST;
+	uint8_t dummy2023[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P0;
+	uint8_t dummy2024[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P1;
+	uint8_t dummy2025[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P2;
+	uint8_t dummy2026[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P3;
+	uint8_t dummy2027[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P4;
+	uint8_t dummy2028[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P5;
+	uint8_t dummy2029[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P6;
+	uint8_t dummy2030[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P7;
+	uint8_t dummy2031[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_IMP;
+	uint8_t dummy2032[124];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P0;
+	uint8_t dummy2033[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P1;
+	uint8_t dummy2034[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P2;
+	uint8_t dummy2035[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P3;
+	uint8_t dummy2036[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P4;
+	uint8_t dummy2037[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P5;
+	uint8_t dummy2038[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P6;
+	uint8_t dummy2039[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P7;
+	uint8_t dummy2040[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_IMP;
+	uint8_t dummy2041[20732];
+	uint32_t SWITCH_CORE_CFP_ACC;
+	uint8_t dummy2042[28];
+	uint32_t SWITCH_CORE_RATE_METER_GLOBAL_CTL;
+	uint8_t dummy2043[92];
+	uint32_t SWITCH_CORE_CFP_DATA0;
+	uint8_t dummy2044[28];
+	uint32_t SWITCH_CORE_CFP_DATA1;
+	uint8_t dummy2045[28];
+	uint32_t SWITCH_CORE_CFP_DATA2;
+	uint8_t dummy2046[28];
+	uint32_t SWITCH_CORE_CFP_DATA3;
+	uint8_t dummy2047[28];
+	uint32_t SWITCH_CORE_CFP_DATA4;
+	uint8_t dummy2048[28];
+	uint32_t SWITCH_CORE_CFP_DATA5;
+	uint8_t dummy2049[28];
+	uint32_t SWITCH_CORE_CFP_DATA6;
+	uint8_t dummy2050[28];
+	uint32_t SWITCH_CORE_CFP_DATA7;
+	uint8_t dummy2051[28];
+	uint32_t SWITCH_CORE_CFP_MASK0;
+	uint8_t dummy2052[28];
+	uint32_t SWITCH_CORE_CFP_MASK1;
+	uint8_t dummy2053[28];
+	uint32_t SWITCH_CORE_CFP_MASK2;
+	uint8_t dummy2054[28];
+	uint32_t SWITCH_CORE_CFP_MASK3;
+	uint8_t dummy2055[28];
+	uint32_t SWITCH_CORE_CFP_MASK4;
+	uint8_t dummy2056[28];
+	uint32_t SWITCH_CORE_CFP_MASK5;
+	uint8_t dummy2057[28];
+	uint32_t SWITCH_CORE_CFP_MASK6;
+	uint8_t dummy2058[28];
+	uint32_t SWITCH_CORE_CFP_MASK7;
+	uint8_t dummy2059[28];
+	uint32_t SWITCH_CORE_ACT_POL_DATA0;
+	uint8_t dummy2060[28];
+	uint32_t SWITCH_CORE_ACT_POL_DATA1;
+	uint8_t dummy2061[28];
+	uint32_t SWITCH_CORE_ACT_POL_DATA2;
+	uint8_t dummy2062[60];
+	uint32_t SWITCH_CORE_RATE_METER0;
+	uint8_t dummy2063[28];
+	uint32_t SWITCH_CORE_RATE_METER1;
+	uint8_t dummy2064[28];
+	uint32_t SWITCH_CORE_RATE_METER2;
+	uint8_t dummy2065[28];
+	uint32_t SWITCH_CORE_RATE_METER3;
+	uint8_t dummy2066[28];
+	uint32_t SWITCH_CORE_RATE_METER4;
+	uint8_t dummy2067[28];
+	uint32_t SWITCH_CORE_RATE_METER5;
+	uint8_t dummy2068[28];
+	uint32_t SWITCH_CORE_RATE_METER6;
+	uint8_t dummy2069[28];
+	uint32_t SWITCH_CORE_TC2COLOR;
+	uint8_t dummy2070[28];
+	uint32_t SWITCH_CORE_STAT_GREEN_CNTR;
+	uint8_t dummy2071[28];
+	uint32_t SWITCH_CORE_STAT_YELLOW_CNTR;
+	uint8_t dummy2072[28];
+	uint32_t SWITCH_CORE_STAT_RED_CNTR;
+	uint8_t dummy2073[188];
+	uint32_t SWITCH_CORE_TCAM_BIST_CONTROL;
+	uint8_t dummy2074[28];
+	uint32_t SWITCH_CORE_TCAM_BIST_STATUS;
+	uint8_t dummy2075[28];
+	uint32_t SWITCH_CORE_TCAM_TEST_COMPARE_STATUS;
+	uint8_t dummy2076[60];
+	uint32_t SWITCH_CORE_CFP_REG_SPARE0;
+	uint8_t dummy2077[28];
+	uint32_t SWITCH_CORE_CFP_REG_SPARE1;
+	uint8_t dummy2078[604];
+	uint32_t SWITCH_CORE_CFP_CTL_REG;
+	uint8_t dummy2079[124];
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_0;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_1;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_2;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_3;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_4;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_5;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_6;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_7;
+	uint32_t SWITCH_CORE_UDF_0_A_0_8_8;
+	uint8_t dummy2080[60];
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_0;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_1;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_2;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_3;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_4;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_5;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_6;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_7;
+	uint32_t SWITCH_CORE_UDF_1_A_0_8_8;
+	uint8_t dummy2081[60];
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_0;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_1;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_2;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_3;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_4;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_5;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_6;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_7;
+	uint32_t SWITCH_CORE_UDF_2_A_0_8_8;
+	uint8_t dummy2082[60];
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_0;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_1;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_2;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_3;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_4;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_5;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_6;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_7;
+	uint32_t SWITCH_CORE_UDF_0_B_0_8_8;
+	uint8_t dummy2083[60];
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_0;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_1;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_2;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_3;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_4;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_5;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_6;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_7;
+	uint32_t SWITCH_CORE_UDF_1_B_0_8_8;
+	uint8_t dummy2084[60];
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_0;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_1;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_2;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_3;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_4;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_5;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_6;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_7;
+	uint32_t SWITCH_CORE_UDF_2_B_0_8_8;
+	uint8_t dummy2085[60];
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_0;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_1;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_2;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_3;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_4;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_5;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_6;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_7;
+	uint32_t SWITCH_CORE_UDF_0_C_0_8_8;
+	uint8_t dummy2086[60];
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_0;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_1;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_2;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_3;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_4;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_5;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_6;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_7;
+	uint32_t SWITCH_CORE_UDF_1_C_0_8_8;
+	uint8_t dummy2087[60];
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_0;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_1;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_2;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_3;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_4;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_5;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_6;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_7;
+	uint32_t SWITCH_CORE_UDF_2_C_0_8_8;
+	uint8_t dummy2088[60];
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_0;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_1;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_2;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_3;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_4;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_5;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_6;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_7;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_8;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_9;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_10;
+	uint32_t SWITCH_CORE_UDF_0_D_0_11_11;
+	uint8_t dummy2089[29348];
+	uint32_t SWITCH_CORE_ARL_TCAM_ACC;
+	uint8_t dummy2090[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_DATA_P0;
+	uint8_t dummy2091[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_DATA_P1;
+	uint8_t dummy2092[92];
+	uint32_t SWITCH_CORE_ARL_SMEM_DATA;
+	uint8_t dummy2093[92];
+	uint32_t SWITCH_CORE_ARL_TCAM_BIST_CTRL;
+	uint8_t dummy2094[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_BIST_STS;
+	uint8_t dummy2095[100060];
+	uint32_t SWITCH_CORE_PLL_NDIV_INT;
+	uint8_t dummy2096[12];
+	uint32_t SWITCH_CORE_PLL_NDIV_FRAC;
+	uint8_t dummy2097[28];
+	uint32_t SWITCH_CORE_PLL_SDMOD_CTRL;
+	uint8_t dummy2098[12];
+	uint32_t SWITCH_CORE_PLL_MOD_CTRL_0;
+	uint8_t dummy2099[28];
+	uint32_t SWITCH_CORE_PLL_MOD_CTRL_1;
+	uint8_t dummy2100[28];
+	uint32_t SWITCH_CORE_PLL_MOD_CTRL_2;
+	uint8_t dummy2101[28];
+	uint32_t SWITCH_CORE_PLL_MISC_CTRL;
+	uint8_t dummy2102[12];
+	uint32_t SWITCH_CORE_PLL_DELOCK_MIB;
+	uint8_t dummy2103[28];
+	uint32_t SWITCH_CORE_PLL_SS_CTL;
+	uint8_t dummy2104[44];
+	uint32_t SWITCH_CORE_PLL_CTRL;
+	uint8_t dummy2105[12];
+	uint32_t SWITCH_CORE_PLL_STS;
+	uint8_t dummy2106[60];
+	uint32_t SWITCH_CORE_PLL_FREQ_SEL;
+	uint8_t dummy2107[44];
+	uint32_t SWITCH_CORE_PLL_TEST_CTRL_I;
+	uint8_t dummy2108[12];
+	uint32_t SWITCH_CORE_PLL_TEST_CTRL_II;
+	uint8_t dummy2109[108];
+	uint32_t SWITCH_CORE_GREEN_MODE_DATA;
+	uint8_t dummy2110[60];
+	uint32_t SWITCH_CORE_GREEN_MODE_SELECT;
+	uint8_t dummy2111[444];
+	uint32_t SWITCH_CORE_TOP_LOW_POWER_CTRL;
+	uint8_t dummy2112[12];
+	uint32_t SWITCH_CORE_TOP_IDDQ_CTL;
+	uint8_t dummy2113[108];
+	uint32_t SWITCH_CORE_IP_PLL_BYPASS;
+	uint8_t dummy2114[636];
+	uint32_t SWITCH_CORE_TOP_MODULE_CTL_SPARE0;
+	uint8_t dummy2115[28];
+	uint32_t SWITCH_CORE_TOP_MODULE_CTL_SPARE1;
+	uint8_t dummy2116[220];
+	uint32_t SWITCH_CORE_EGPHY_CTRL;
+	uint8_t dummy2117[12];
+	uint32_t SWITCH_CORE_EGPHY_PWRMGNT;
+	uint8_t dummy2118[12];
+	uint32_t SWITCH_CORE_EGPHY_PWR_DOWN;
+	uint8_t dummy2119[44];
+	uint32_t SWITCH_CORE_EGPHY_STRAP;
+	uint8_t dummy2120[12];
+	uint32_t SWITCH_CORE_EGPHY_STS;
+	uint8_t dummy2121[12];
+	uint32_t SWITCH_CORE_EGPHY_INT_STS;
+	uint8_t dummy2122[12];
+	uint32_t SWITCH_CORE_EGPHY_MODE_STS;
+	uint8_t dummy2123[12];
+	uint32_t SWITCH_CORE_EGPHY_LPI_STS;
+	uint8_t dummy2124[12];
+	uint32_t SWITCH_CORE_EGPHY_ENG_DET_STS;
+	uint8_t dummy2125[12];
+	uint32_t SWITCH_CORE_EGPHY_ENG_DET_STS_CHG;
+	uint8_t dummy2126[12];
+	uint32_t SWITCH_CORE_EGPHY_RESET_STATUS;
+	uint8_t dummy2127[1596];
+	uint32_t SWITCH_CORE_EGPHY_CTL_SPARE0;
+	uint8_t dummy2128[28];
+	uint32_t SWITCH_CORE_EGPHY_CTL_SPARE1;
+	uint8_t dummy2129[220];
+	uint32_t SWITCH_CORE_BRPHY_CTRL;
+	uint8_t dummy2130[12];
+	uint32_t SWITCH_CORE_BRPHY_PWRMGNT;
+	uint8_t dummy2131[12];
+	uint32_t SWITCH_CORE_BRPHY_PWR_DOWN;
+	uint8_t dummy2132[28];
+	uint32_t SWITCH_CORE_BRPHY_PLL_CTRL;
+	uint8_t dummy2133[28];
+	uint32_t SWITCH_CORE_BRPHY_STS;
+	uint8_t dummy2134[12];
+	uint32_t SWITCH_CORE_BRPHY_INT_STS;
+	uint8_t dummy2135[44];
+	uint32_t SWITCH_CORE_BRPHY_ENG_DET_STS;
+	uint8_t dummy2136[12];
+	uint32_t SWITCH_CORE_BRPHY_ENG_DET_STS_CHG;
+	uint8_t dummy2137[12];
+	uint32_t SWITCH_CORE_BRPHY_RESET_STATUS;
+	uint8_t dummy2138[1596];
+	uint32_t SWITCH_CORE_BRPHY_CTL_SPARE0;
+	uint8_t dummy2139[28];
+	uint32_t SWITCH_CORE_BRPHY_CTL_SPARE1;
+	uint8_t dummy2140[220];
+#endif
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P0;
+	uint8_t dummy2141[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P1;
+	uint8_t dummy2142[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P2;
+	uint8_t dummy2143[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P3;
+	uint8_t dummy2144[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P4;
+	uint8_t dummy2145[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P5;
+	uint8_t dummy2146[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_P6;
+	uint8_t dummy2147[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P7;
+	uint8_t dummy2148[12];
+	uint32_t imp_port_state;
+#define ETHSW_IPS_USE_MII_HW_STS                  0x00
+#define ETHSW_IPS_USE_REG_CONTENTS                0x80
+#define ETHSW_IPS_GMII_SPEED_UP_NORMAL            0x00
+#define ETHSW_IPS_GMII_SPEED_UP_2G                0x40
+#define ETHSW_IPS_TXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_TXFLOW_PAUSE_CAPABLE            0x20
+#define ETHSW_IPS_RXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_RXFLOW_PAUSE_CAPABLE            0x10
+#define ETHSW_IPS_SW_PORT_SPEED_1000M_2000M       0x08
+#define ETHSW_IPS_DUPLEX_MODE                     0x02
+#define ETHSW_IPS_LINK_FAIL                       0x00
+#define ETHSW_IPS_LINK_PASS                       0x01
+#if 1
+	uint8_t dummy2149[60];
+	uint32_t SWITCH_CORE_PAUSE_CAP;
+	uint8_t dummy2150[124];
+	uint32_t SWITCH_CORE_PORT4_RGMII_CTL_GP;
+	uint8_t dummy2151[12];
+	uint32_t SWITCH_CORE_PORT5_RGMII_CTL_GP;
+	uint8_t dummy2152[12];
+	uint32_t SWITCH_CORE_PORT6_RGMII_CTL_GP;
+	uint8_t dummy2153[28];
+	uint32_t SWITCH_CORE_RGMII_CTL_GP_IMP;
+	uint8_t dummy2154[188];
+	uint32_t SWITCH_CORE_P4_RGMII_TIME_DLY_GP;
+	uint8_t dummy2155[12];
+	uint32_t SWITCH_CORE_P5_RGMII_TIME_DLY_GP;
+	uint8_t dummy2156[12];
+	uint32_t SWITCH_CORE_P6_RGMII_TIME_DLY_GP;
+	uint8_t dummy2157[28];
+	uint32_t SWITCH_CORE_RGMII_TIME_DLY_GP_IMP;
+	uint8_t dummy2158[124];
+	uint32_t SWITCH_CORE_RM_PINS_DEBUG;
+	uint8_t dummy2159[12];
+	uint32_t SWITCH_CORE_MII_IDDQ_CTRL;
+	uint8_t dummy2160[12];
+	uint32_t SWITCH_CORE_MII_LOW_POWER_CTRL;
+	uint8_t dummy2161[12];
+	uint32_t SWITCH_CORE_LED_OPTIONS;
+	uint8_t dummy2162[972];
+	uint32_t SWITCH_CORE_PORT_INFO_SPARE0;
+	uint8_t dummy2163[28];
+	uint32_t SWITCH_CORE_PORT_INFO_SPARE1;
+	uint8_t dummy2164[220];
+	uint32_t SWITCH_CORE_IO_SR_CTL;
+	uint8_t dummy2165[28];
+	uint32_t SWITCH_CORE_IO_DS_SEL0;
+	uint8_t dummy2166[60];
+	uint32_t SWITCH_CORE_IO_DS_SEL2;
+	uint8_t dummy2167[28];
+	uint32_t SWITCH_CORE_GMII_IO_SR_CTL;
+	uint8_t dummy2168[28];
+	uint32_t SWITCH_CORE_GMII_IO_DS_SEL0;
+	uint8_t dummy2169[28];
+	uint32_t SWITCH_CORE_GMII_IO_DS_SEL1;
+	uint8_t dummy2170[28];
+	uint32_t SWITCH_CORE_GMII_VOL_SEL;
+	uint8_t dummy2171[12];
+	uint32_t SWITCH_CORE_PINS_DEBUG_IMP;
+	uint8_t dummy2172[28];
+	uint32_t SWITCH_CORE_BONDING_PAD_STATUS;
+	uint8_t dummy2173[12];
+	uint32_t SWITCH_CORE_STRAP_PIN_STATUS;
+	uint8_t dummy2174[28];
+	uint32_t SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE;
+	uint8_t dummy2175[60];
+	uint32_t SWITCH_CORE_EMB_CPU_STATUS;
+	uint8_t dummy2176[1404];
+	uint32_t SWITCH_CORE_CHIP_CTL_SPARE0;
+	uint8_t dummy2177[28];
+	uint32_t SWITCH_CORE_CHIP_CTL_SPARE1;
+#endif
+
+} EthernetSwitchCore;
+
+
+/*
+* Gpio Controller
+*/
+typedef struct GpioControl {
+	uint32_t GPIODir[8];   /* 0x00-0x1f */
+	uint32_t GPIOio[8];    /* 0x20-0x3f */
+	uint32_t PadControl;    /* 0x40 */
+	uint32_t SpiSlaveCfg;   /* 0x44 */
+	uint32_t TestControl;   /* 0x48 */
+	uint32_t TestPortBlockEnMSB; /* 0x4c */
+	uint32_t TestPortBlockEnLSB; /* 0x50 */
+	uint32_t TestPortBlockDataMSB;  /* 0x54 */
+	uint32_t TestPortBlockDataLSB;  /* 0x58 */
+#define PINMUX_ADDR_SHIFT       0
+#define PINMUX_ADDR_MASK        (0xfff<<PINMUX_ADDR_SHIFT)
+#define PINMUX_DATA_SHIFT       12
+#define PINMUX_DATA_MASK        (0x3f<<PINMUX_DATA_SHIFT)
+#define PINMUX_0                0
+#define PINMUX_1                1
+#define PINMUX_2                2
+#define PINMUX_3                3
+#define PINMUX_4                4
+#define PINMUX_5                5
+#define PINMUX_6                6
+#define PINMUX_MSPI             PINMUX_0
+#define PINMUX_MSPI_SS          PINMUX_1
+#define PINMUX_PCM              PINMUX_1
+/*  GPIO pad control are done indirectly using TP cmd */
+#define PAD_CTRL_SHIFT          12
+#define PAD_CTRL_MASK           (0x3f<<PAD_CTRL_SHIFT)
+#define PAD_DRIVE_STRENGTH_SHIFT   12
+#define PAD_DRIVE_STRENGTH_MASK    (0x7<<TP_XMII_PAD_DRV_STRENGTH_SHIFT)
+#define PAD_SLEW_RATE_CTRL      0x8000    /* RGMII pad amp en */
+#define PAD_INPUT_DISABLE       0x10000
+#define PAD_HYST_ENABLE         0x20000   /* RGMII pad sel gmii */
+	uint32_t TestPortCmd;        /* 0x5c */
+#define LOAD_MUX_REG_CMD        0x21
+#define LOAD_PAD_CTRL_CMD       0x22
+	uint32_t DiagReadBack;       /* 0x60 */
+	uint32_t DiagReadBackHi;     /* 0x64 */
+	uint32_t GeneralPurpose;     /* 0x68 */
+	uint32_t spare[3];           /* 0x6c-0x77 */
+} GpioControl;
+
+#define GPIO_BASE  0xff800000+0x0500
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+
+/* PHY mode as determined by straps */
+enum phy_mode {
+	PHY_MODE_NOPHY,
+	PHY_MODE_AUTO,
+	PHY_MODE_100,
+	PHY_MODE_1000,
+};
+
+/* PHY type as determined by straps */
+enum phy_type {
+	PHY_TYPE_EXT_RGMII,
+	PHY_TYPE_EXT_MII,
+	PHY_TYPE_NOPHY_RGMII
+};
+
+/* PHY speed */
+enum phy_speed {
+	PHY_SPEED_10,
+	PHY_SPEED_100,
+	PHY_SPEED_1000,
+};
+
+/* Drive strength as determined by straps */
+enum drive_strength {
+	RGMII_DRIVE_STRENGTH_LOW,
+	RGMII_DRIVE_STRENGTH_HIGH,
+};
+
+/* Bits in switch CORE_STS_OVERRIDE_GMII_Px registers */
+#define	OVRRD_EN_MASK			0x00000040
+#define	OVRRD_TX_PAUSE_MASK		0x00000020
+#define	OVRRD_RX_PAUSE_MASK		0x00000010
+#define	OVRRD_10BT_MASK			0x00000000
+#define	OVRRD_100BT_MASK		0x00000004
+#define	OVRRD_1000BT_MASK		0x00000008
+#define	OVRRD_FDX_MASK			0x00000002
+#define	OVRRD_LINK_MASK			0x00000001
+
+/* Generic MII registers */
+#define MII_BMCR            	0x00
+#define MII_BMSR            	0x01
+#define MII_PHYSID1         	0x02
+#define MII_PHYSID2         	0x03
+#define MII_ADVERTISE       	0x04
+#define MII_LPA             	0x05
+#define MII_EXPANSION       	0x06
+#define MII_CTRL1000        	0x09
+#define MII_STAT1000        	0x0a
+#define MII_ESTATUS         	0x0f
+
+/* Basic mode control register. */
+#define BMCR_RESV               0x003f
+#define BMCR_SPEED1000          0x0040
+#define BMCR_CTST               0x0080
+#define BMCR_FULLDPLX           0x0100
+#define BMCR_ANRESTART          0x0200
+#define BMCR_ISOLATE            0x0400
+#define BMCR_PDOWN              0x0800
+#define BMCR_ANENABLE           0x1000
+#define BMCR_SPEED100           0x2000
+#define BMCR_LOOPBACK           0x4000
+#define BMCR_RESET              0x8000
+
+/* Basic mode status register. */
+#define BMSR_ERCAP              0x0001
+#define BMSR_JCD                0x0002
+#define BMSR_LSTATUS            0x0004
+#define BMSR_ANEGCAPABLE        0x0008
+#define BMSR_RFAULT             0x0010
+#define BMSR_ANEGCOMPLETE       0x0020
+#define BMSR_RESV               0x00c0
+#define BMSR_ESTATEN            0x0100
+#define BMSR_100HALF2           0x0200
+#define BMSR_100FULL2           0x0400
+#define BMSR_10HALF             0x0800
+#define BMSR_10FULL             0x1000
+#define BMSR_100HALF            0x2000
+#define BMSR_100FULL            0x4000
+#define BMSR_100BASE4           0x8000
+
+/* Link partner ability register. */
+#define LPA_SLCT                0x001f
+#define LPA_10HALF              0x0020
+#define LPA_1000XFULL           0x0020
+#define LPA_10FULL              0x0040
+#define LPA_1000XHALF           0x0040
+#define LPA_100HALF             0x0080
+#define LPA_1000XPAUSE          0x0080
+#define LPA_100FULL             0x0100
+#define LPA_1000XPAUSE_ASYM     0x0100
+#define LPA_100BASE4            0x0200
+#define LPA_PAUSE_CAP           0x0400
+#define LPA_PAUSE_ASYM          0x0800
+#define LPA_RESV                0x1000
+#define LPA_RFAULT              0x2000
+#define LPA_LPACK               0x4000
+#define LPA_NPAGE               0x8000
+
+/* Extended status register */
+#define ESTATUS_1000_XFULL      0x8000
+#define ESTATUS_1000_XHALF      0x4000
+#define ESTATUS_1000_TFULL      0x2000
+#define ESTATUS_1000_THALF      0x1000
+
+/* MII_CTRL1000 register */
+#define PHY_1000BTCR_1000FD	0x0200
+#define PHY_1000BTCR_1000HD	0x0100
+
+/* MII_STAT1000 register */
+#define PHY_1000BTSR_MSCF		0x8000
+#define PHY_1000BTSR_MSCR		0x4000
+#define PHY_1000BTSR_LRS		0x2000
+#define PHY_1000BTSR_RRS		0x1000
+#define PHY_1000BTSR_1000FD	0x0800
+#define PHY_1000BTSR_1000HD	0x0400
+
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT     12
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_MASK      (0x1f<<ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT)
+#define ETHSW_QPHY_CTRL_RESET_SHIFT          8
+#define ETHSW_QPHY_CTRL_RESET_MASK           (0x1<<ETHSW_QPHY_CTRL_RESET_SHIFT )
+#define ETHSW_QPHY_CTRL_CK25_DIS_SHIFT       7
+#define ETHSW_QPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_QPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_MASK    (0xf<<ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      6
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+
+
+#define ETHSW_SPHY_CTRL_PHYAD_BASE_SHIFT     8
+#define ETHSW_SPHY_CTRL_PHYAD_BASE_MASK      (0x1f<<ETHSW_SPHY_CTRL_PHYAD_BASE_SHIFT)
+#define ETHSW_SPHY_CTRL_RESET_SHIFT          5
+#define ETHSW_SPHY_CTRL_RESET_MASK           (0x1<<ETHSW_SPHY_CTRL_RESET_SHIFT )
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_MASK    (0x1<<ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      3
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+
+#define BCM_PHY_ID_M             0x1F
+
+#define PBMAP_MIPS 0x100
+
+
diff --git a/arch/arm/include/asm/arch-bcm63158/misc.h b/arch/arm/include/asm/arch-bcm63158/misc.h
new file mode 100644
index 0000000000..c63cbfd004
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63158/misc.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63158_MISC_H
+#define _63158_MISC_H
+
+#define MISC_BASE          0xff802600
+
+/*
+ * Misc Register Set Definitions.
+ */
+typedef struct Misc {
+   uint32_t miscStrapBus; /* 0x00 */
+
+    /* boot select bits 3-5 */
+#define BOOT_SEL_STRAP_NAND_2K_PAGE             0x00
+#define BOOT_SEL_STRAP_NAND_4K_PAGE             0x08
+#define BOOT_SEL_STRAP_NAND_8K_PAGE             0x10
+#define BOOT_SEL_STRAP_NAND_512B_PAGE           0x18
+#define BOOT_SEL_STRAP_SPI_NOR                  0x38
+#define BOOT_SEL_STRAP_EMMC                     0x30
+#define BOOT_SEL_STRAP_SPI_NAND                 0x28
+
+#define BOOT_SEL_STRAP_BOOT_SEL_MASK            (0x38)
+#define BOOT_SEL_STRAP_PAGE_SIZE_MASK           (0x7)
+
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           0
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_B53_BOOT_N               (0x1 << 6)
+#define MISC_STRAP_BUS_BOOTROM_BOOT_N           (0x1 << 7)
+#define MISC_STRAP_BUS_BOOROM_BOOT_N            MISC_STRAP_BUS_BOOTROM_BOOT_N
+#define MISC_STRAP_BUS_LS_SPI_SLAVE_DISABLE     (0x1 << 8)
+#define MISC_STRAP_BUS_PCIE_SATA_MASK           (0x1 << 11)  /* 1-PCIe2 0-SATAB */
+#define MISC_STRAP_BUS_PCIE0_RC_MODE            (0x1 << 12)
+#define MISC_STRAP_BUS_RESET_OUT_DELAY          (0x1 << 13)
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT      15
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ            (0x1 << MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT)
+#define MISC_STRAP_BUS_SW_RESERVE_MASK          (0x1f << 16)
+   uint32_t miscStrapOverride;     /* 0x04 */
+   uint32_t miscMaskUBUSErr;       /* 0x08 */
+   uint32_t miscPeriphCtrl;        /* 0x0c */
+   uint32_t miscSpiMasterCtrl;     /* 0x10 */
+   uint32_t reserved0;             /* 0x14 */
+   uint32_t miscPeriphMiscCtrl;    /* 0x18 */
+   uint32_t miscPeriphMiscStat;    /* 0x1c */
+   uint32_t miscSoftResetB;        /* 0x20 */
+   uint32_t miscSpare0;            /* 0x24 */
+   uint32_t miscSWdebugNW[2];      /* 0x28 */
+   uint32_t miscWDResetCtrl;       /* 0x30 */
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+#define DUAL_CORE_63152 0x63152
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63158/otp.h b/arch/arm/include/asm/arch-bcm63158/otp.h
new file mode 100644
index 0000000000..b8634e89e2
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63158/otp.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _63158_OTP_H
+#define _63158_OTP_H
+
+#define JTAG_OTP_BASE    0xff802800
+
+/* row 8 */
+#define OTP_CPU_CORE_CFG_ROW                    8
+#define OTP_CPU_CORE_CFG_SHIFT                  28
+#define OTP_CPU_CORE_CFG_MASK                   0x3
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          7
+
+/* row 23 */
+#define OTP_CUST_MFG_MRKTID_ROW                 23
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_CPU_CORE_CFG, OTP_CPU_CORE_CFG_ROW, OTP_CPU_CORE_CFG_MASK, OTP_CPU_CORE_CFG_SHIFT, 1},				\
+	}
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63158/pmc.h b/arch/arm/include/asm/arch-bcm63158/pmc.h
new file mode 100644
index 0000000000..35f395b426
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63158/pmc.h
@@ -0,0 +1,364 @@
+#ifndef PMC_H
+#define PMC_H 
+
+/*
+ * Process Monitor Module
+ */
+typedef struct PMRingOscillatorControl {
+   uint32_t control;
+   uint32_t en_lo;
+   uint32_t en_mid;
+   uint32_t en_hi;
+   uint32_t idle_lo;
+   uint32_t idle_mid;
+   uint32_t idle_hi;
+} PMRingOscillatorControl;
+
+#define RCAL_0P25UM_HORZ          0
+#define RCAL_0P25UM_VERT          1
+#define RCAL_0P5UM_HORZ           2
+#define RCAL_0P5UM_VERT           3
+#define RCAL_1UM_HORZ             4
+#define RCAL_1UM_VERT             5
+#define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
+#define PMMISC_RMON_VALID_MASK    (0x1<<16)
+typedef struct PMMiscControl {
+   uint32_t gp_out;
+   uint32_t clock_select;
+   uint32_t unused[2];
+   uint32_t misc[4];
+} PMMiscControl;
+
+typedef struct PMSSBMasterControl {
+   uint32_t control;
+#define PMC_SSBM_CONTROL_SSB_START  (1<<15)
+#define PMC_SSBM_CONTROL_SSB_ADPRE  (1<<13)
+#define PMC_SSBM_CONTROL_SSB_EN     (1<<12)
+#define PMC_SSBM_CONTROL_SSB_CMD_SHIFT (10)
+#define PMC_SSBM_CONTROL_SSB_CMD_MASK  (0x3 << PMC_SSBM_CONTROL_SSB_CMD_SHIFT)
+#define PMC_SSBM_CONTROL_SSB_CMD_READ  (2)
+#define PMC_SSBM_CONTROL_SSB_CMD_WRITE (1)
+#define PMC_SSBM_CONTROL_SSB_ADDR_SHIFT   (0)
+#define PMC_SSBM_CONTROL_SSB_ADDR_MASK (0x3ff << PMC_SSBM_CONTROL_SSB_ADDR_SHIFT)
+   uint32_t wr_data;
+   uint32_t rd_data;
+} PMSSBMasterControl;
+
+typedef struct PMEctrControl {
+   uint32_t control;
+   uint32_t interval;
+   uint32_t thresh_lo;
+   uint32_t thresh_hi;
+   uint32_t count;
+} PMEctrControl;
+
+typedef struct PMBMaster {
+   uint32_t ctrl;
+#define PMC_PMBM_START     (1 << 31)
+#define PMC_PMBM_TIMEOUT   (1 << 30)
+#define PMC_PMBM_SLAVE_ERR (1 << 29)
+#define PMC_PMBM_BUSY      (1 << 28)
+#define PMC_PMBM_Read      (0 << 20)
+#define PMC_PMBM_Write     (1 << 20)
+   uint32_t wr_data;
+   uint32_t timeout;
+   uint32_t rd_data;
+   uint32_t unused[4];
+} PMBMaster;
+
+typedef struct PMAPVTMONControl {
+   uint32_t control;
+   uint32_t reserved;
+   uint32_t cfg_lo;
+   uint32_t cfg_hi;
+   uint32_t data;
+   uint32_t vref_data;
+   uint32_t unused[2];
+   uint32_t ascan_cfg;
+   uint32_t warn_temp;
+   uint32_t reset_temp;
+   uint32_t temp_value;
+   uint32_t data1_value;
+   uint32_t data2_value;
+   uint32_t data3_value;
+} PMAPVTMONControl;
+
+typedef struct PMUBUSCfg {
+   uint32_t window[8];
+   uint32_t control;
+} PMUBUSCfg;
+
+typedef struct ProcessMonitorRegs {
+   uint32_t MonitorCtrl;     /* 0x00 */
+   uint32_t unused0[7];
+   PMRingOscillatorControl ROSC; /* 0x20 */
+   uint32_t unused1;
+   PMMiscControl Misc;     /* 0x40 */
+   PMSSBMasterControl SSBMaster; /* 0x60 */
+   uint32_t unused2[5];
+   PMEctrControl Ectr;     /* 0x80 */
+   uint32_t unused3[11];
+   PMBMaster PMBM[2];      /* 0xc0 */
+   PMAPVTMONControl APvtmonCtrl; /* 0x100 - 0x13b */
+   uint32_t unused4[41];
+   PMUBUSCfg UBUSCfg;      /* 0x1e0 */
+} ProcessMonitorRegs;
+
+#define PROCMON ((volatile ProcessMonitorRegs * const)0x80280000)
+
+/*
+ * Power Management Control
+ */
+typedef struct PmcCtrlReg {
+   /* 0x00 */
+   uint32_t l1Irq4keMask;
+   uint32_t l1Irq4keStatus;
+   uint32_t l1IrqMipsMask;
+   uint32_t l1IrqMipsStatus;
+   /* 0x10 */
+   uint32_t l2IrqGpMask;
+   uint32_t l2IrqGpStatus;
+   uint32_t gpTmr0Ctl;
+   uint32_t gpTmr0Cnt;
+   /* 0x20 */
+   uint32_t gpTmr1Ctl;
+   uint32_t gpTmr1Cnt;
+   uint32_t hostMboxIn;
+   uint32_t hostMboxOut;
+   /* 0x30 */
+#define PMC_CTRL_GP_FLASH_BOOT_STALL                  0x00000080
+   uint32_t gpOut;
+   uint32_t gpIn;
+   uint32_t gpInIrqMask;
+   uint32_t gpInIrqStatus;
+   /* 0x40 */
+   uint32_t dmaCtrl;
+   uint32_t dmaStatus;
+   uint32_t dma0_3FifoStatus;
+   uint32_t unused0[3];   /* 0x4c-0x57 */
+   /* 0x58 */
+   uint32_t l1IrqMips1Mask;
+   uint32_t diagControl;
+   /* 0x60 */
+   uint32_t diagHigh;
+   uint32_t diagLow;
+   uint32_t badAddr;
+   uint32_t addr1WndwMask;
+   /* 0x70 */
+   uint32_t addr1WndwBaseIn;
+   uint32_t addr1WndwBaseOut;
+   uint32_t addr2WndwMask;
+   uint32_t addr2WndwBaseIn;
+   /* 0x80 */
+   uint32_t addr2WndwBaseOut;
+   uint32_t scratch;
+   uint32_t tm;
+   uint32_t softResets;
+   /* 0x90 */
+   uint32_t eb2ubusTimeout;
+   uint32_t m4keCoreStatus;
+   uint32_t gpInIrqSense;
+   uint32_t ubSlaveTimeout;
+   /* 0xa0 */
+   uint32_t diagEn;
+   uint32_t devTimeout;
+   uint32_t ubusErrorOutMask;
+   uint32_t diagCaptStopMask;
+   /* 0xb0 */
+   uint32_t revId;
+   uint32_t gpTmr2Ctl;
+   uint32_t gpTmr2Cnt;
+   uint32_t legacyMode;
+   /* 0xc0 */
+   uint32_t smisbMonitor;
+   uint32_t diagCtrl;
+   uint32_t diagStat;
+   uint32_t diagMask;
+   /* 0xd0 */
+   uint32_t diagRslt;
+   uint32_t diagCmp;
+   uint32_t diagCapt;
+   uint32_t diagCnt;
+   /* 0xe0 */
+   uint32_t diagEdgeCnt;
+   uint32_t unused1[4];   /* 0xe4-0xf3 */
+   /* 0xf4 */
+   uint32_t iopPeriphBaseAddr;
+   uint32_t lfsr;
+   uint32_t unused2;      /* 0xfc-0xff */
+} PmcCtrlReg;
+
+typedef struct PmcOutFifoReg {
+   uint32_t msgCtrl;      /* 0x00 */
+   uint32_t msgSts;       /* 0x04 */
+   uint32_t unused[14];   /* 0x08-0x3f */
+   uint32_t msgData[16];  /* 0x40-0x7c */
+} PmcOutFifoReg;
+
+typedef struct PmcInFifoReg {
+   uint32_t msgCtrl;      /* 0x00 */
+   uint32_t msgSts;       /* 0x04 */
+   uint32_t unused[13];   /* 0x08-0x3b */
+   uint32_t msgLast;      /* 0x3c */
+   uint32_t msgData[16];  /* 0x40-0x7c */
+} PmcInFifoReg;
+
+typedef struct PmcDmaReg {
+   /* 0x00 */
+   uint32_t src;
+   uint32_t dest;
+   uint32_t cmdList;
+   uint32_t lenCtl;
+   /* 0x10 */
+   uint32_t rsltSrc;
+   uint32_t rsltDest;
+   uint32_t rsltHcs;
+   uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+   /* 0x00 */
+   uint32_t bufSize;
+   uint32_t bufBase;
+   uint32_t idx2ptrIdx;
+   uint32_t idx2ptrPtr;
+   /* 0x10 */
+   uint32_t unused[2];
+   uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+   /* 0x00 */
+   uint32_t dcacheHit;
+   uint32_t dcacheMiss;
+   uint32_t icacheHit;
+   uint32_t icacheMiss;
+   /* 0x10 */
+   uint32_t instnComplete;
+   uint32_t wtbMerge;
+   uint32_t wtbNoMerge;
+   uint32_t itlbHit;
+   /* 0x20 */
+   uint32_t itlbMiss;
+   uint32_t dtlbHit;
+   uint32_t dtlbMiss;
+   uint32_t jtlbHit;
+   /* 0x30 */
+   uint32_t jtlbMiss;
+   uint32_t powerSubZone;
+   uint32_t powerMemPda;
+   uint32_t freqScalarCtrl;
+   /* 0x40 */
+   uint32_t freqScalarMask;
+} PmcPerfPowReg;
+
+typedef struct PmcDQMReg {
+   /* 0x00 */
+   uint32_t cfg;
+   uint32_t _4keLowWtmkIrqMask;
+   uint32_t mipsLowWtmkIrqMask;
+   uint32_t lowWtmkIrqMask;
+   /* 0x10 */
+   uint32_t _4keNotEmptyIrqMask;
+   uint32_t mipsNotEmptyIrqMask;
+   uint32_t notEmptyIrqSts;
+   uint32_t queueRst;
+   /* 0x20 */
+   uint32_t notEmptySts;
+   uint32_t nextAvailMask;
+   uint32_t nextAvailQueue;
+   uint32_t mips1LowWtmkIrqMask;
+   /* 0x30 */
+   uint32_t mips1NotEmptyIrqMask;
+   uint32_t autoSrcPidInsert;
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+   uint32_t cntr[10];
+   uint32_t unused[6]; /* 0x28-0x3f */
+   uint32_t cntrIrqMask;
+   uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+   uint32_t size;
+   uint32_t cfga;
+   uint32_t cfgb;
+   uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+   uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+   uint32_t qNumFull[32];
+   uint32_t qNumEmpty[32];
+   uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+#define PVTMON_REG
+typedef struct {
+   uint32_t control;      // 0x100
+   uint32_t reserved;     // 0x104
+   uint32_t cfg_lo;       // 0x108
+   uint32_t reserved1;    // 0x10c
+   uint32_t adc_data;     // 0x110
+   uint32_t vref_data;    // 0x114
+   uint32_t reserved2[2]; // 0x118
+   uint32_t ascan_config; // 0x120
+   uint32_t reserved3[119];
+} pvtmon_regs;
+
+typedef struct Pmc {
+   uint32_t baseReserved;    /* 0x0000 */
+   uint32_t unused0[1023];
+   PmcCtrlReg ctrl;     /* 0x1000 */
+
+   PmcOutFifoReg outFifo;     /* 0x1100 */
+   uint32_t unused1[32];     /* 0x1180-0x11ff */
+   PmcInFifoReg inFifo;    /* 0x1200 */
+   uint32_t unused2[32];     /* 0x1280-0x12ff */
+
+   PmcDmaReg dma[2];    /* 0x1300 */
+   uint32_t unused3[48];     /* 0x1340-0x13ff */
+
+   PmcTokenReg token;      /* 0x1400 */
+   uint32_t unused4[121];    /* 0x141c-0x15ff */
+
+   PmcPerfPowReg perfPower;   /* 0x1600 */
+   uint32_t unused5[47];     /* 0x1644-0x16ff */
+
+   uint32_t msgId[32];    /* 0x1700 */
+   uint32_t unused6[32];     /* 0x1780-0x17ff */
+
+   PmcDQMReg dqm;       /* 0x1800 */
+   uint32_t unused7[50];     /* 0x1838-0x18ff */
+
+   PmcCntReg hwCounter;    /* 0x1900 */
+   uint32_t unused8[46];     /* 0x1948-0x19ff */
+
+   PmcDqmQCtrlReg dqmQCtrl[32];  /* 0x1a00 */
+   PmcDqmQDataReg dqmQData[32];  /* 0x1c00 */
+   uint32_t unused9[64];     /* 0x1e00-0x1eff */
+
+   uint32_t qStatus[32];     /* 0x1f00 */
+   uint32_t unused10[32];    /* 0x1f80-0x1fff */
+
+   PmcDqmQMibReg qMib;     /* 0x2000 */
+   uint32_t unused11[1952];     /* 0x2180-0x3ffff */
+
+   uint32_t sharedMem[512];    /* 0x4000-0x47ff */
+   uint32_t unused12[126528];  /* 0x4800-0x80100 */
+
+   pvtmon_regs pvtmon[2];
+} Pmc;
+
+
+#define PMC_BASE         0x80200000
+#define PMC ((volatile Pmc * const)PMC_BASE)
+
+#define PERF_PHYS_BASE        0xff800000
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63158/pmc_addr.h b/arch/arm/include/asm/arch-bcm63158/pmc_addr.h
new file mode 100644
index 0000000000..890ad0ef63
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63158/pmc_addr.h
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef PMC_ADDR_63158_H__
+#define PMC_ADDR_63158_H__
+
+#define PMB_BUS_MAX              2
+#define PMB_BUS_ID_SHIFT         8
+
+#define PMB_BUS_PERIPH           1
+#define PMB_ADDR_PERIPH          (3 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH         4
+
+#define PMB_BUS_CHIP_CLKRST      0
+#define PMB_ADDR_CHIP_CLKRST     (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST    0
+
+#define BPCM_CLKRST_AFE_PWRDWN   0x80000000
+
+#define PMB_BUS_SYSPLL           0
+#define PMB_ADDR_SYSPLL          (4 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL         0
+
+#define PMB_BUS_RDPPLL           0
+#define PMB_ADDR_RDPPLL          (6 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_RDPPLL         0
+
+#define PMB_BUS_UBUSPLL          0
+#define PMB_ADDR_UBUSPLL         (5 | PMB_BUS_UBUSPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_UBUSPLL        0
+
+#define PMB_BUS_MEMC             0
+#define PMB_ADDR_MEMC            (2 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC           1
+
+#define PMB_BUS_SYNC_PLL         1
+#define PMB_ADDR_SYNC_PLL        (7 | PMB_BUS_SYNC_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYNC_PLL       1
+
+#define PMB_BUS_USB30_2X         1
+#define PMB_ADDR_USB30_2X        (13 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB30_2X       4
+
+#define PMB_BUS_WAN              1
+#define PMB_ADDR_WAN             (15 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WAN            7
+
+#define PMB_BUS_XRDP             1
+#define PMB_ADDR_XRDP            (16 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP           3
+
+#define PMB_BUS_PCIE0            0
+#define PMB_ADDR_PCIE0           (8 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0          1
+
+#define PMB_BUS_PCIE1            0
+#define PMB_ADDR_PCIE1           (9 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1          1
+
+#define PMB_BUS_PCIE2            0
+#define PMB_ADDR_PCIE2           (10 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE2          1
+
+#define PMB_BUS_PCIE3            1
+#define PMB_ADDR_PCIE3           (12 | PMB_BUS_PCIE3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE3          1
+
+#define PMB_BUS_SATA             0
+#define PMB_ADDR_SATA            (11 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SATA           1
+
+#define PMB_BUS_SGMII            1
+#define PMB_ADDR_SGMII           (14 | PMB_BUS_SGMII << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SGMII          0
+
+#define PMB_BUS_SWITCH           1
+#define PMB_ADDR_SWITCH          (0 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SWITCH         4
+
+#define PMB_BUS_XRDP_RC0         1
+#define PMB_ADDR_XRDP_RC0        (17 | PMB_BUS_XRDP_RC0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC0       1
+
+#define PMB_BUS_XRDP_RC1         1
+#define PMB_ADDR_XRDP_RC1        (18 | PMB_BUS_XRDP_RC1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC1       1
+
+#define PMB_BUS_XRDP_RC2         1
+#define PMB_ADDR_XRDP_RC2        (19 | PMB_BUS_XRDP_RC2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC2       1
+
+#define PMB_BUS_XRDP_RC3         1
+#define PMB_ADDR_XRDP_RC3        (20 | PMB_BUS_XRDP_RC3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC3       1
+
+#define PMB_BUS_XRDP_RC4         1
+#define PMB_ADDR_XRDP_RC4        (21 | PMB_BUS_XRDP_RC4 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC4       1
+
+#define PMB_BUS_XRDP_RC5         1
+#define PMB_ADDR_XRDP_RC5        (22 | PMB_BUS_XRDP_RC5 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC5       1
+
+#define PMB_BUS_VDSL3_CORE       0
+#define PMB_ADDR_VDSL3_CORE      (23 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_VDSL3_CORE     1
+
+#define PMB_BUS_VDSL3_MIPS       PMB_BUS_VDSL3_CORE
+#define PMB_ADDR_VDSL3_MIPS      PMB_ADDR_VDSL3_CORE
+#define PMB_ZONES_VDSL3_MIPS     PMB_ZONES_VDSL3_CORE
+
+#define PMB_BUS_VDSL3_PMD        0
+#define PMB_ADDR_VDSL3_PMD       (24 | PMB_BUS_VDSL3_PMD << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_VDSL3_PMD      1
+
+//--------- DGASP related bits/Offsets ------------------------
+#define BPCM_PHY_CNTL_OVERRIDE         0x08000000
+#define PMB_ADDR_VDSL_DGASP_PMD        PMB_ADDR_VDSL3_PMD
+#define BPCM_VDSL_PHY_CTL_REG	       global_control  // Alias for register containing DGASP override inside the VDSL PMD
+#define BPCM_VDSL_AFE_CTL_REG	       misc_control    // Alias for register containing DGASP configuration inside the VDSL PMD
+
+#define PMB_BUS_CRYPTO           0
+#define PMB_ADDR_CRYPTO          (25 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CRYPTO         1
+
+#define AFEPLL_PMB_BUS_VDSL3_CORE       0
+#define AFEPLL_PMB_ADDR_VDSL3_CORE      (26 | AFEPLL_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
+#define AFEPLL_PMB_ZONES_VDSL3_CORE     0
+
+#define PMB_BUS_ORION_CPU0       0
+#define PMB_ADDR_ORION_CPU0      (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0     1
+
+#define PMB_BUS_ORION_CPU1       0
+#define PMB_ADDR_ORION_CPU1      (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1     1
+
+#define PMB_BUS_ORION_CPU2       0
+#define PMB_ADDR_ORION_CPU2      (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU2     1
+
+#define PMB_BUS_ORION_CPU3       0
+#define PMB_ADDR_ORION_CPU3      (35 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU3     1
+
+#define PMB_BUS_ORION_NONCPU     0
+#define PMB_ADDR_ORION_NONCPU    (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU   1
+
+#define PMB_BUS_ORION_ARS        0
+#define PMB_ADDR_ORION_ARS       (37 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_ARS      0
+
+#define PMB_BUS_BIU_PLL          0
+#define PMB_ADDR_BIU_PLL         (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL        0
+
+#define PMB_BUS_BIU_BPCM         0
+#define PMB_ADDR_BIU_BPCM        (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM       1
+
+#define PMB_BUS_ORION_C0_ARS     0
+#define PMB_ADDR_ORION_C0_ARS    (45 | PMB_BUS_ORION_C0_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_C0_ARS   0
+
+#define PMB_BUS_PCM              1
+#define PMB_ADDR_PCM             (3 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCM            4
+
+enum {
+	PCM_Zone_Main,
+	PCM_Zone_PCM=3
+};
+//--------- SOFT Reset bits for PCM ------------------------
+#define   BPCM_PCM_SRESET_PCM_N       0x00000040
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63158/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm63158/pmc_drv_cfg.h
new file mode 100644
index 0000000000..c101a3deec
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63158/pmc_drv_cfg.h
@@ -0,0 +1,42 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_1_X
+
+#define PMC_CPU_BIG_ENDIAN   1
+#define PMC_GETRCAL_SUPPORT  1 
+#define PMC_CPUTEMP_SUPPORT 1
+#define PMC_CLOCK_SET_SUPPORT 1
+#define PMC_RAM_BOOT 1
+#define PMC_IN_MAIN_LOOP	kPMCRunStateRunning
+#define PMC_SHARED_MEMORY   0x80204000
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm63158/rng.h b/arch/arm/include/asm/arch-bcm63158/rng.h
new file mode 100644
index 0000000000..407576c7f0
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63158/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63158_RNG_H
+#define _63158_RNG_H
+
+#define RNG_BASE	0xff800b80
+
+typedef struct Rng {
+	uint32_t ctrl0;			/* 0x00 */
+	uint32_t rngSoftReset;		/* 0x04 */
+	uint32_t rbgSoftReset;		/* 0x08 */
+	uint32_t totalBitCnt;		/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;			/* 0x14 */
+	uint32_t intStatus;		/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL	(0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL	(0x1<<2)
+	uint32_t intEn;			/* 0x1c */
+	uint32_t rngFifoData;		/* 0x20 */
+	uint32_t fifoCnt;		/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS	0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS	0x33
+	uint32_t perm;			/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63178/BPCM.h b/arch/arm/include/asm/arch-bcm63178/BPCM.h
new file mode 100644
index 0000000000..fbe0bb87ea
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/BPCM.h
@@ -0,0 +1,741 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmbAddr:12;	// [11:00]
+		uint32_t map_rev:4;	// [15:12] always non-zero for AVS3 devices (see CLASSIC_BPCM_ID_REG below)
+		uint32_t island:4;	// [19:16]
+		uint32_t devType:4;	// [23:20] see enum above
+		uint32_t hw_rev:8;	// [31:24]
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+// types of PMB devices
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	struct {
+		uint32_t vdsl_bpcm_early_reset:1;
+		uint32_t vdsl_bpcm_reset:1;
+		uint32_t mips_ubus_soft_reset_bpcm_reset:1;
+		uint32_t qproc_1_bpcm_reset:1;
+		uint32_t qproc_2_bpcm_reset:1;
+		uint32_t sar_bpcm_soft_reset:1;
+		uint32_t vdsl_ubus_soft_bpcm_reset:1;
+		uint32_t reserved1:1;
+		uint32_t gp:24;
+	} Bits_vdsl;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu_reset_n:8;	// 07:00    R/W
+		uint32_t c0l2_reset:1;	// 08:08    R/W
+		uint32_t c1l2_reset:1;	// 09:09    R/W
+		uint32_t reserved0:6;	// 15:10    R/O
+		uint32_t cpu_bpcm_init_on:8;	// 23:16    R/W
+		uint32_t c0l2_bpcm_init_on:1;	// 24:24    R/W
+		uint32_t c1l2_bpcm_init_on:1;	// 25:25    R/W
+		uint32_t ubus_sr:1;	// 26:26    R/W
+		uint32_t cci_sr:1;	// 27:27    R/W
+		uint32_t webcores_sr:1;	// 28:28    R/W
+		uint32_t hw_done:1;	// 29:29    R/O
+		uint32_t sw_done:1;	// 30:30    R/W
+		uint32_t start:1;	// 31:31    R/W
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t reserved0:2;	// 11:10
+		uint32_t ndiv_frac:20;	// 31:12    
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECNDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t reserved0:12;	// 15:04
+		uint32_t mdiv0:8;	// 23:16
+		uint32_t mdiv1:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECPDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv2:8;	// 07:00
+		uint32_t mdiv3:8;	// 15:08
+		uint32_t mdiv4:8;	// 23:16
+		uint32_t mdiv5:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECCH25_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	uint32_t reserved0;
+	uint32_t timer_control;
+	uint32_t timer_status;
+	uint32_t reserved1[2];
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+typedef union {
+	struct {
+		uint32_t counter:8;
+		uint32_t reserved2:7;
+		uint32_t enable:1;
+		uint32_t reserved1:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CLKRST_VREG_CONTROL;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	// BPCM
+	uint32_t control;	// offset 0x10, PMB reg index 4
+	BPCM_SR_CONTROL sr_control;	// offset 0x14, PMB reg index 5
+	uint32_t reserved1[2];	// offset 0x18, PMB reg index 6/7
+	// Client-specific registers
+	uint32_t client_specific[24];	// offset 0x20, PMB reg index 8..31
+	// Zones
+	BPCM_ZONE zones[];	// offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1))
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08, actual offset = 2
+	uint32_t cfg_control;	// offset = 0x10, actual offset = 4
+	BPCM_SR_CONTROL sr_control;	// offset = 0x14, actual offset = 5
+	uint32_t reserved1[10];	// offset = 0x18, actual offset = 6
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x40, actual offset = 16
+	uint32_t vdsl_phy_ctl;	// offset = 0x44, actual offset = 17
+	uint32_t vdsl_afe_ctl;	// offset = 0x48, actual offset = 18
+	uint32_t reserved2[13];	// offset = 0x4c, actual offset = 19
+	BPCM_ZONE zones;	// offset = 0x80, actual offset = 32
+} BPCM_VDSL_REGS;		// total offset space = 4096
+
+#define BPCMVDSLOffset(reg)	offsetof(BPCM_VDSL_REGS,reg)
+#define BPCMVDSLRegOffset(reg)	(BPCMVDSLOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08, actual offset = 2
+	uint32_t cfg_control;	// offset = 0x10, actual offset = 4
+	BPCM_SR_CONTROL sr_control;	// offset = 0x14, actual offset = 5
+	uint32_t reserved1[6];	// offset = 0x18, actual offset = 6
+	ARM_CONTROL_REG arm_control;	// offset = 0x30, actual offset = 12
+	uint32_t biu_clk_control0;	// offset = 0x34, actual offset = 13
+	uint32_t tbd[18];	// offset = 0x38, actual offset = 14
+	BPCM_ZONE zones;	// offset = 0x80, actual offset = 32
+} ARM_BPCM_REGS;
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	PLL_DECNDIV_REG decndiv;	// offset = 0x44, actual offset = 0x11
+	PLL_DECPDIV_REG decpdiv;	// offset = 0x48, actual offset = 0x12
+	PLL_DECCH25_REG decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[7];	// offset 0x08-0x20, PMB reg index 2-8
+	uint32_t control;	// offset 0x24, PMB reg index 9
+	uint32_t unused[10];	// offset 0x28, PMB reg index 10
+	BPCM_CLKRST_VREG_CONTROL vreg_control;	// offset 0x50, PMB reg index 19
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63178/brom.h b/arch/arm/include/asm/arch-bcm63178/brom.h
new file mode 100644
index 0000000000..0575e395c9
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63178_BROM_H
+#define _63178_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63178/cpu.h b/arch/arm/include/asm/arch-bcm63178/cpu.h
new file mode 100644
index 0000000000..be2727b803
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/cpu.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63178_CPU_H
+#define _63178_CPU_H
+
+#define BIUCFG_BASE		0x81060000
+#define CCI500_BASE	        0x81100000
+
+typedef struct BIUCFG_Access {
+	uint32_t permission;	/* 0x0 */
+	uint32_t sbox;		/* 0x4 */
+	uint32_t cpu_defeature;	/* 0x8 */
+	uint32_t dbg_security;	/* 0xc */
+	uint32_t rsvd1[32];	/* 0x10 - 0x8f */
+	uint64_t violation[2];	/* 0x90 - 0x9f */
+	uint32_t ts_access[2];	/* 0xa0 - 0xa7 */
+	uint32_t rsvd2[22];	/* 0xa8 - 0xff */
+} BIUCFG_Access;
+
+typedef struct BIUCFG_Cluster {
+	uint32_t permission;	/* 0x0 */
+	uint32_t config;	/* 0x4 */
+	uint32_t status;	/* 0x8 */
+	uint32_t control;	/* 0xc */
+	uint32_t cpucfg;	/* 0x10 */
+	uint32_t dbgrom;	/* 0x14 */
+	uint32_t rsvd1[2];	/* 0x18 - 0x1f */
+	uint32_t rvbar_addr[4];	/* 0x20 - 0x2f */
+	uint32_t rsvd2[52];	/* 0x30 - 0xff */
+} BIUCFG_Cluster;
+
+typedef struct BIUCFG_AuxClkCtrl {
+	uint32_t clk_control;	/* 0x0 */
+	uint32_t clk_ramp;	/* 0x4 */
+	uint32_t clk_pattern;	/* 0x8 */
+	uint32_t rsvd;		/* 0xC */
+} BIUCFG_AuxClkCtrl;
+
+typedef struct BIUCFGux {
+	uint32_t permission;	/* 0 */
+	uint32_t rsvd1[3];	/* 0x04 - 0x0c */
+	BIUCFG_AuxClkCtrl cluster_clkctrl[2];	/* 0x10 - 0x2c */
+	uint32_t rsvd2[52];	/* 0x30 - 0xFF */
+} BIUCFG_Aux;
+
+typedef struct BIUCFG_Bac {
+	uint32_t bac_permission;	/* 0x00 */
+	uint32_t bac_periphbase;	/* 0x04 */
+	uint32_t rsvd[2];		/* 0x08 - 0x0f */
+	uint32_t bac_event;		/* 0x10 */
+	uint32_t rsvd_1[3];		/* 0x14 - 0x1f */
+	uint32_t bac_ccicfg;		/* 0x20 */
+	uint32_t bac_cciaddr;		/* 0x24 */
+	uint32_t rsvd_2[4];		/* 0x28 - 0x37 */
+	uint32_t bac_ccievs2;		/* 0x38 */
+	uint32_t bac_ccievs3;		/* 0x3c */
+	uint32_t bac_ccievs4;		/* 0x40 */
+	uint32_t rsvd_3[3];		/* 0x44 - 0x4f */
+	uint32_t bac_ccievm0;		/* 0x50 */
+	uint32_t bac_ccievm1;		/* 0x54 */
+	uint32_t rsvd_4[2];		/* 0x58 - 0x5f */
+	uint32_t bac_dapapbcfg;		/* 0x60 */
+	uint32_t bac_status;		/* 0x64 */
+	uint32_t rsvd_5[2];		/* 0x68 - 0x6f */
+	uint32_t cpu_therm_irq_cfg; /* 0x70 */
+	uint32_t cpu_therm_threshold_cfg; /* 0x74 */
+	uint32_t rsvd_6;		/* 0x78 */
+	uint32_t cpu_therm_temp;	/* 0x7c */
+	uint32_t rsvd_7[32];		/* 0x80 - 0xff */
+} BIUCFG_Bac;
+
+
+typedef struct BIUCFG {
+	BIUCFG_Access access;	/* 0x0 - 0xff */
+	BIUCFG_Cluster cluster[2];	/* 0x100 - 0x2ff */
+	BIUCFG_Bac bac;		/* 0x300 - 0x3ff */
+	uint32_t rsvd1[192];	/* 0x400 - 0x6ff */
+	BIUCFG_Aux aux;		/* 0x700 - 0x7ff */
+	uint32_t rsrvd2[512];	/* 0x800 - 0xfff */
+	uint32_t TSO_CNTCR;	/* 0x1000 */
+	uint32_t rsvd2[2047];	/* 0x1004 - 0x2fff */
+} BIUCFG;
+
+#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
+
+typedef struct CCI500_SlaveIntf {
+#define SNOOP_CTRL_ENABLE_SNOOP		0x1
+	uint32_t snoop_ctrl;		/* 0x0 */
+#define SHARE_OVR_SHAREABLE_OVR_SHIFT	0x0
+#define SHARE_OVR_SHAREABLE_OVR_MASK	0x3
+#define SHARE_OVR_SHAREABLE_OVR_NONSHR	0x2
+#define SHARE_OVR_SHAREABLE_OVR_SHR	0x3
+	uint32_t share_ovr;		/* 0x4 */
+	uint32_t rsvd1[62];		/* 0x8 - 0xff */
+	uint32_t arqos_ovr;		/* 0x100 */
+	uint32_t awqos_ovr;		/* 0x104 */
+	uint32_t rsvd2[2];		 /* 0x108 - 0x10f */
+	uint32_t qos_max_ot;		/* 0x110 */
+	uint32_t rsvd3[955];		/* 0x114 - 0xfff */
+}CCI500_SlaveIntf;
+
+typedef struct CCI500_EventCounter {
+	uint32_t sel;	/* 0x0 */
+	uint32_t data;	/* 0x4 */
+	uint32_t ctrl;	/* 0x8 */
+	uint32_t clr_ovfl;/* 0xC */
+	uint32_t rsvd[16380];/* 0x10 - 0xffff */
+}CCI500_EventCounter;
+typedef struct CCI500 {
+#define CONTROL_OVERRIDE_SNOOP_DISABLE     0x1
+#define CONTROL_OVERRIDE_SNOOP_FLT_DISABLE 0x4
+	uint32_t ctrl_ovr;        /* 0x0 */
+	uint32_t rsvd1;           /* 0x4 */
+#define SECURE_ACCESS_UNSECURE_ENABLE      0x1
+	uint32_t secr_acc;        /* 0x8 */
+	uint32_t status;          /* 0xc */
+#define STATUS_CHANGE_PENDING              0x1
+	uint32_t impr_err;        /* 0x10 */
+	uint32_t qos_threshold;   /* 0x14 */
+	uint32_t rsvd2[58];       /* 0x18 - 0xff */
+	uint32_t pmu_ctrl;        /* 0x100 */
+#define DBG_CTRL_EN_INTF_MON               0x1
+	uint32_t debug_ctrl;      /* 0x104 */
+	uint32_t rsvd3[958];      /* 0x108 - 0xfff */
+#define SLAVEINTF_COHERENCY_PORT           0x0
+#define SLAVEINTF_CPU_CLUSTER              0x1
+	CCI500_SlaveIntf si[7]; /* 0x1000 - 0x7fff */
+	uint32_t rsvd4[8192];     /* 0x8000 - 0xffff */
+	CCI500_EventCounter evt_cntr[8]; /* 0x10000 - 0x8ffff */
+}CCI500;
+#define CCI500 ((volatile CCI500 * const) CCI500_BASE)
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63178/ddr.h b/arch/arm/include/asm/arch-bcm63178/ddr.h
new file mode 100644
index 0000000000..51bde152fe
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/ddr.h
@@ -0,0 +1,586 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63178_DDR_H
+#define _63178_DDR_H
+
+#define MEMC_BASE	0x80180000	/* DDR IO Buf Control */
+
+typedef struct AXIInterface {
+	uint32_t CFG;			/* 0x00 */
+	uint32_t REP_ARB_MODE;		/* 0x04 */
+	uint32_t QUEUE_CFG;		/* 0x08 */
+	uint32_t ESRCID_CFG;		/* 0x0c */
+	uint32_t SRC_QUEUE_CTRL[8];	/* 0x10 */
+	uint32_t SRC_ID_4_QUEUE_CTRL;	/* 0x30 */
+	uint32_t SCRATCH;		/* 0x34 */
+	uint32_t AXI_DEBUG[2];		/* 0x38 */
+} AXIInterface;
+
+typedef struct EDISEngine {
+	uint32_t REV_ID;		/* 0x00 */
+	uint32_t CTRL_TRIG;		/* 0x04 */
+	uint32_t CTRL_MODE;		/* 0x08 */
+	uint32_t CTRL_SIZE;		/* 0x0c */
+	uint32_t CTRL_ADDR_START;	/* 0x10 */
+	uint32_t CTRL_ADDR_START_EXT;	/* 0x14 */
+	uint32_t CTRL_ADDR_END;		/* 0x18 */
+	uint32_t CTRL_ADDR_END_EXT;	/* 0x1c */
+	uint32_t CTRL_WRITE_MASKS;	/* 0x20 */
+	uint32_t CTRL_INT_ENABLES;	/* 0x24 */
+	uint32_t unused0[6];		/* 0x28-0x3f */
+	uint32_t STAT_MAIN;		/* 0x40 */
+	uint32_t STAT_WORDS_WRITTEN;	/* 0x44 */
+	uint32_t STAT_WORDS_READ;	/* 0x48 */
+	uint32_t STAT_ERROR_COUNT;	/* 0x4c */
+	uint32_t STAT_ERROR_BITS;	/* 0x50 */
+	uint32_t STAT_ADDR_LAST;	/* 0x54 */
+	uint32_t STAT_ADDR_LAST_EXT;	/* 0x58 */
+	uint32_t STAT_CLOCK_CYCLES;	/* 0x5c */
+	uint32_t unused1[7];		/* 0x60-0x7b */
+	uint32_t STAT_DEBUG;		/* 0x7c */
+	uint32_t STAT_DATA_PORT[8];	/* 0x80-0x9c */
+	uint32_t GEN_LFSR_STATE[4];	/* 0xa0-0xac */
+	uint32_t GEN_CLOCK;		/* 0xb0 */
+	uint32_t GEN_PATTERN;		/* 0xb4 */
+	uint32_t unused2[2];		/* 0xb8-0xbf */
+	uint32_t BYTELANE_0_CTRL_LO;	/* 0xc0 */
+	uint32_t BYTELANE_0_CTRL_HI;	/* 0xc4 */
+	uint32_t BYTELANE_1_CTRL_LO;	/* 0xc8 */
+	uint32_t BYTELANE_1_CTRL_HI;	/* 0xcc */
+	uint32_t BYTELANE_2_CTRL_LO;	/* 0xd0 */
+	uint32_t BYTELANE_2_CTRL_HI;	/* 0xd4 */
+	uint32_t BYTELANE_3_CTRL_LO;	/* 0xd8 */
+	uint32_t BYTELANE_3_CTRL_HI;	/* 0xdc */
+	uint32_t BYTELANE_0_STAT_LO;	/* 0xe0 */
+	uint32_t BYTELANE_0_STAT_HI;	/* 0xe4 */
+	uint32_t BYTELANE_1_STAT_LO;	/* 0xe8 */
+	uint32_t BYTELANE_1_STAT_HI;	/* 0xec */
+	uint32_t BYTELANE_2_STAT_LO;	/* 0xf0 */
+	uint32_t BYTELANE_2_STAT_HI;	/* 0xf4 */
+	uint32_t BYTELANE_3_STAT_LO;	/* 0xf8 */
+	uint32_t BYTELANE_3_STAT_HI;	/* 0xfc */
+} EDISEngine;
+
+typedef struct RangeCtrl {
+	uint32_t CTRL;			/* 0x00 */
+	uint32_t UBUS0_PORT;		/* 0x04 */
+	uint32_t UBUS0_PORT_UPPER;	/* 0x08 */
+	uint32_t BASE;			/* 0x0c */
+	uint32_t BASE_UPPER;		/* 0x10 */
+	uint32_t SECLEC_EN;		/* 0x14 */
+} RangeCtrl;
+
+typedef struct SecureRangeCheckers {
+	uint32_t LOCK;			/* 0x00 */
+	uint32_t LOG_INFO[3];		/* 0x04 - 0x0c */
+	RangeCtrl RANGE_CTRL[8];	/* 0x10 - 0xcf */
+	uint32_t unused[12];		/* 0xd0 - 0xff */
+} SecureRangeCheckers;
+
+typedef struct DDRPhyControl {
+	uint32_t REVISION;		/* 0x00 */
+	uint32_t PLL_STATUS;		/* 0x04 */
+	uint32_t PLL_CONFIG;		/* 0x08 */
+	uint32_t PLL_CONTROL1;		/* 0x0c */
+	uint32_t PLL_CONTROL2;		/* 0x10 */
+	uint32_t PLL_CONTROL3;		/* 0x14 */
+	uint32_t PLL_DIVIDER;		/* 0x18 */
+	uint32_t PLL_PRE_DIVIDER;	/* 0x1c */
+	uint32_t PLL_SS_EN;		/* 0x20 */
+	uint32_t PLL_SS_CFG;		/* 0x24 */
+	uint32_t unused00;		/* 0x28 */
+	uint32_t IDLE_PAD_CONTROL;	/* 0x2c */
+	uint32_t IDLE_PAD_EN0;		/* 0x30 */
+	uint32_t IDLE_PAD_EN1;		/* 0x34 */
+	uint32_t DRIVE_PAD_CTL;		/* 0x38 */
+	uint32_t DRIVE_PAD_CTL_2T;	/* 0x3c */
+	uint32_t STATIC_PAD_CTL;	/* 0x40 */
+	uint32_t DRAM_CFG;		/* 0x44 */
+	uint32_t unused01;		/* 0x48 */
+	uint32_t DRAM_TIMING2;		/* 0x4c */
+	uint32_t DRAM_TIMING3;		/* 0x50 */
+	uint32_t unused02;		/* 0x54 */
+	uint32_t VDL_REGS[45];		/* 0x58-0x108 */
+	uint32_t UPDATE_VDL;		/* 0x10C */
+	uint32_t UPDATE_VDL_SNOOP1;	/* 0x110 */
+	uint32_t UPDATE_VDL_SNOOP2;	/* 0x114 */
+	uint32_t CMND_REG1;		/* 0x118 */
+	uint32_t CMND_AUX_REG1;		/* 0x11C */
+	uint32_t CMND_REG2;		/* 0x120 */
+	uint32_t CMND_AUX_REG2;		/* 0x124 */
+	uint32_t CMND_REG3;		/* 0x128 */
+	uint32_t CMND_AUX_REG3;		/* 0x12C */
+	uint32_t CMND_REG4;		/* 0x130 */
+	uint32_t CMND_AUX_REG4;		/* 0x134 */
+	uint32_t MODE_REG[4];		/* 0x138-144 */
+	uint32_t unused2[13];		/* 0x148-178 */
+	uint32_t WRITE_LEVEL_CTRL;	/* 0x17c */
+	uint32_t WRITE_LEVEL_STATUS;	/* 0x180 */
+	uint32_t READ_EN_CTRL;		/* 0x184 */
+	uint32_t READ_EN_STATUS;	/* 0x188 */
+	uint32_t VIRT_VTT_CTRL;		/* 0x18C */
+	uint32_t VIRT_VTT_STATUS;	/* 0x190 */
+	uint32_t VIRT_VTT_CONNECTION;	/* 0x194 */
+	uint32_t VIRT_VTT_OVERRIDE;	/* 0x198 */
+	uint32_t VREF_DAC_CTRL;		/* 0x19C */
+#define DDRPHY_VREF_DAC_CTRL_PDN_SHIFT             12
+#define DDRPHY_VREF_DAC_CTRL_PDN_MASK              (0xf << DDRPHY_VREF_DAC_CTRL_PDN_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT            6
+#define DDRPHY_VREF_DAC_CTRL_DAC1_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT            0
+#define DDRPHY_VREF_DAC_CTRL_DAC0_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT)
+	uint32_t PHYBIST[12];		/* 0x1A0-0x1CC */
+	uint32_t STANDBY_CTRL;		/* 0x1D0 */
+	uint32_t DEBUG_FREEZE_EN;	/* 0x1D4 */
+	uint32_t DEBUG_MUX_CTRL;	/* 0x1D8 */
+	uint32_t DFI_CTRL;		/* 0x1DC */
+	uint32_t unused3[8];		/* 0x1E0-1FC */
+	uint32_t CLOCK_IDLE;		/* 0x200 */
+	uint32_t unused5[127];		/* 0x204-0x3ff */
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+	uint32_t VDL_CTRL_WR[11];	/* 0x00-0x28 */
+	uint32_t VDL_CTRL_RD[22];	/* 0x2c-0x80 */
+	uint32_t VDL_CLK_CTRL;		/* 0x84 */
+	uint32_t VDL_LDE_CTRL;		/* 0x88 */
+	uint32_t RD_EN_DLY_CYC;		/* 0x8c */
+	uint32_t WR_CHAN_DLY_CYC;	/* 0x90 */
+	uint32_t RD_CTRL;		/* 0x94 */
+	uint32_t RD_FIFO_ADDR;		/* 0x98 */
+	uint32_t RD_FIFO_DATA;		/* 0x9C */
+	uint32_t RD_FIFO_DM_DBI;	/* 0xA0 */
+	uint32_t RD_FIFO_STATUS;	/* 0xA4 */
+	uint32_t RD_FIFO_CLR;		/* 0xA8 */
+	uint32_t IDLE_PAD_CTRL;		/* 0xAC */
+	uint32_t DRIVE_PAD_CTRL;	/* 0xB0 */
+	uint32_t DQSP_DRIVE_PAD_CTRL;	/* 0xB4 */
+	uint32_t DQSN_DRIVE_PAD_CTRL;	/* 0xB8 */
+	uint32_t unused1;		/* 0xBC */
+	uint32_t RD_EN_DRIVE_PAD_CTRL;	/* 0xC0 */
+	uint32_t STATIC_PAD_CTRL;	/* 0xC4 */
+	uint32_t WR_PREAMBLE_MODE;	/* 0xC8 */
+	uint32_t ODT_CTRL;		/* 0xCC */
+	uint32_t CLOCK_ENABLE;		/* 0xD0 */
+	uint32_t CLOCK_IDLE;		/* 0xD4 */
+	uint32_t BL_SPARE_REG;		/* 0xD8 */
+	uint32_t unused4[73];		/* 0xDC */
+} DDRPhyByteLaneControl;
+
+typedef struct MEMCControl {
+	uint32_t GLB_VERS;		/* 0x000 */
+	uint32_t GLB_GCFG;		/* 0x004 */
+#define MEMC_GLB_GCFG_DRAM_EN_SHIFT        31
+#define MEMC_GLB_GCFG_DRAM_EN_MASK         (0x1<<MEMC_GLB_GCFG_DRAM_EN_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ_SHIFT      30
+#define MEMC_GLB_GCFG_FORCE_SEQ_MASK       (0x1<<MEMC_GLB_GCFG_FORCE_SEQ_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT     29
+#define MEMC_GLB_GCFG_FORCE_SEQ2_MASK      (1<<MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT)
+#define MEMC_GLB_GCFG_RBF_REORDER_SHIFT    28
+#define MEMC_GLB_GCFG_RBF_REORDER_MASK     (1<<MEMC_GLB_GCFG_RBF_REORDER_SHIFT)
+#define MEMC_GLB_GCFG_SREF_SLOW_CLK_SHIFT  26
+#define MEMC_GLB_GCFG_SREF_SLOW_CLK_MASK   (1<<MEMC_GLB_GCFG_SREF_SLOW_CLK_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT   24
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_MASK    (0x3<<MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_2X           0x0
+#define MEMC_GLB_GCFG_PHY_DFI_4X           0x1
+#define MEMC_GLB_GCFG_PHY_DFI_8X           0x2
+#define MEMC_GLB_GCFG_DFI_EN_SHIFT         10
+#define MEMC_GLB_GCFG_DFI_EN_MASK          (0x1<<MEMC_GLB_GCFG_DFI_EN_SHIFT)
+#define MEMC_GLB_GCFG_MCLKSRC_SHIFT        9
+#define MEMC_GLB_GCFG_MCLKSRC_MASK         (0x1<<MEMC_GLB_GCFG_MCLKSRC_SHIFT)
+#define MEMC_GLB_GCFG_MEMINITDONE_SHIFT    8
+#define MEMC_GLB_GCFG_MEMINITDONE_MASK     (0x1<<MEMC_GLB_GCFG_MEMINITDONE_SHIFT)
+#define MEMC_GLB_GCFG_MRQSIZE_SHIFT        0
+#define MEMC_GLB_GCFG_MRQSIZE_MASK         (0x1f<<MEMC_GLB_GCFG_MRQSIZE_SHIFT)
+	uint32_t GLB_MRQ_CFG;		/* 0x008 */
+	uint32_t unused0;		/* 0x00c */
+	uint32_t GLB_FSBL_STATE;	/* 0x010 */
+#define MEMC_GLB_FSBL_DRAM_SIZE_SHIFT      0
+#define MEMC_GLB_FSBL_DRAM_SIZE_MASK       (0xf << MEMC_GLB_FSBL_DRAM_SIZE_SHIFT)
+	uint32_t unused1[3];		/* 0x014 - 0x01f */
+
+	uint32_t SRAM_REMAP_CTRL;	/* 0x020 */
+	uint32_t SRAM_REMAP_CTRL_UPPER;	/* 0x024 */
+	uint32_t SRAM_REMAP_INIT;	/* 0x028 */
+	uint32_t SRAM_REMAP_LOG_INFO_0;	/* 0x02c */
+	uint32_t SRAM_REMAP_LOG_INFO_1;	/* 0x030 */
+	uint32_t SRAM_REMAP_LOG_INFO_2;	/* 0x034 */
+	uint32_t unused2[2];		/* 0x038-0x03f */
+
+	uint32_t RBF_REORDER_0_CFG[16];	/* 0x040 - 0x07f */
+
+	uint32_t INTR2_CPU_STATUS;	/* 0x080 */
+	uint32_t INTR2_CPU_SET;		/* 0x084 */
+	uint32_t INTR2_CPU_CLEAR;	/* 0x088 */
+	uint32_t INTR2_CPU_MASK_STATUS;	/* 0x08c */
+	uint32_t INTR2_CPU_MASK_SET;	/* 0x090 */
+	uint32_t INTR2_CPU_MASK_CLEAR;	/* 0x094 */
+	uint32_t unused3[26];		/* 0x098-0x0ff */
+
+	uint32_t CHN_CFG_CNFG;		/* 0x100 */
+#define MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT            16
+#define MEMC_CHN_CFG_CNFG_CS_MODE_MASK             (0x3 << MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT)
+	uint32_t CHN_CFG_CSST;		/* 0x104 */
+	uint32_t unused4[2];		/* 0x108-0x10f */
+	uint32_t CHN_CFG_ROW00_0;	/* 0x110 */
+	uint32_t CHN_CFG_ROW00_1;	/* 0x114 */
+	uint32_t CHN_CFG_ROW01_0;	/* 0x118 */
+	uint32_t CHN_CFG_ROW01_1;	/* 0x11c */
+	uint32_t CHN_CFG_ROW02_0;	/* 0x120 */
+	uint32_t CHN_CFG_COL00_0;	/* 0x124 */
+	uint32_t CHN_CFG_COL00_1;	/* 0x128 */
+	uint32_t CHN_CFG_COL01_0;	/* 0x12c */
+	uint32_t CHN_CFG_COL01_1;	/* 0x130 */
+	uint32_t CHN_CFG_BNK10;		/* 0x134 */
+	uint32_t CHN_CFG_BG0;		/* 0x138 */
+	uint32_t unused5;		/* 0x13c */
+	uint32_t CHN_CFG_DRAM_SZ_CHK;	/* 0x140 */
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT  4
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_MASK   (0xf<<MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT)
+	uint32_t CHN_CFG_DIAG_SEL;	/* 0x144 */
+	uint32_t unused6[46];		/* 0x148-0x1ff */
+
+	uint32_t CHN_TIM_DCMD;		/* 0x200 */
+	uint32_t CHN_TIM_DMODE_0;	/* 0x204 */
+	uint32_t CHN_TIM_DMODE_2;	/* 0x208 */
+	uint32_t CHN_TIM_CLKS;		/* 0x20c */
+#define MEMC_CHN_TIM_CLKS_REF_RATE_SHIFT          8
+#define MEMC_CHN_TIM_CLKS_REF_DISABLE_SHIFT       31
+	uint32_t CHN_TIM_ODT;		/* 0x210 */
+	uint32_t CHN_TIM_TIM1_0;	/* 0x214 */
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tWL [31:24] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_MASK                            0xff000000
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_SHIFT                           24
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_DEFAULT                         0x00000004
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRP [23:16] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_MASK                            0x00ff0000
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_SHIFT                           16
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_DEFAULT                         0x00000006
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tCL [15:08] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_MASK                            0x0000ff00
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_SHIFT                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_DEFAULT                         0x00000005
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRCD [07:00] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_MASK                           0x000000ff
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_ALIGN                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_BITS                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_SHIFT                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_DEFAULT                        0x00000006
+
+	uint32_t CHN_TIM_TIM1_1;	/* 0x218 */
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_L [31:24] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_S [23:16] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_L [15:08] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_MASK                         0x0000ff00
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_SHIFT                        8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_S [07:00] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_MASK                         0x000000ff
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_SHIFT                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_DEFAULT                      0x00000002
+
+	uint32_t CHN_TIM_TIM1_2;	/* 0x21c */
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tFAW [31:24] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_MASK                           0xff000000
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_SHIFT                          24
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_DEFAULT                        0x00000000
+/* MC_CHN_TIM :: TIM1_2 :: reserved0 [23:16] */
+#define MC_CHN_TIM_TIM1_2_reserved0_MASK                           0x00ff0000
+#define MC_CHN_TIM_TIM1_2_reserved0_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_reserved0_BITS                           8
+#define MC_CHN_TIM_TIM1_2_reserved0_SHIFT                          16
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRTP [15:08] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_MASK                           0x0000ff00
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_SHIFT                          8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_DEFAULT                        0x00000002
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRC [07:00] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_ALIGN                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_BITS                            8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_SHIFT                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_DEFAULT                         0x00000011
+
+	uint32_t CHN_TIM_TIM1_3;	/* 0x220 */
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_L [31:24] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_S [23:16] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: reserved_for_padding0 [15:12] */
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_MASK               0x0000f000
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_ALIGN              0
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_BITS               4
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_SHIFT              12
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_L [11:08] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_MASK                          0x00000f00
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_BITS                          4
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_SHIFT                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_DEFAULT                       0x00000004
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_S [07:00] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_MASK                          0x000000ff
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_BITS                          8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_SHIFT                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_DEFAULT                       0x00000004
+
+	uint32_t CHN_TIM_TIM2;		/* 0x224 */
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2R [31:30] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_MASK                             0xc0000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_BITS                             2
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_SHIFT                            30
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2W [29:27] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_MASK                             0x38000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_SHIFT                            27
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2R [26:24] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_MASK                             0x07000000
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_SHIFT                            24
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: reserved_for_padding0 [23:22] */
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_MASK                 0x00c00000
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_ALIGN                0
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_BITS                 2
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_SHIFT                22
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2W [21:18] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_MASK                             0x003c0000
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_BITS                             4
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_SHIFT                            18
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: reserved1 [17:16] */
+#define MC_CHN_TIM_TIM2_reserved1_MASK                             0x00030000
+#define MC_CHN_TIM_TIM2_reserved1_ALIGN                            0
+#define MC_CHN_TIM_TIM2_reserved1_BITS                             2
+#define MC_CHN_TIM_TIM2_reserved1_SHIFT                            16
+/* MC_CHN_TIM :: TIM2 :: TIM2_tAL [15:12] */
+#define MC_CHN_TIM_TIM2_TIM2_tAL_MASK                              0x0000f000
+#define MC_CHN_TIM_TIM2_TIM2_tAL_ALIGN                             0
+#define MC_CHN_TIM_TIM2_TIM2_tAL_BITS                              4
+#define MC_CHN_TIM_TIM2_TIM2_tAL_SHIFT                             12
+#define MC_CHN_TIM_TIM2_TIM2_tAL_DEFAULT                           0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tRFC [11:00] */
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_MASK                             0x00000fff
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_BITS                             12
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_SHIFT                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_DEFAULT                          0x00000014
+
+	uint32_t unused7[2];		/* 0x228 - 0x22f */
+	uint32_t CHN_TIM_PHY_ST;	/* 0x230 */
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP       0x1
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_HW_RESET       0x2
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_SW_RESET       0x4
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_READY          0x10
+	uint32_t CHN_TIM_DRAM_CFG;	/* 0x234 */
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT           12
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_MASK            (0x1<<MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT     10
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_MASK      (0x1<<MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT      0
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_MASK       (0xf<<MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT)
+#define MC_DRAM_CFG_DDR3                          0x1
+	uint32_t CHN_TIM_STAT;		/* 0x238 */
+	uint32_t CHN_TIM_PERF;		/* 0x23c */
+
+	uint32_t CHN_TIM_PKM_CFG;	/* 0x240 */
+	uint32_t CHN_TIM_AB4_CFG;	/* 0x244 */
+	uint32_t unused8[2];		/* 0x248 */
+	uint32_t CHN_TIM_AB4_ACT_PRI;	/* 0x250 */
+	uint32_t CHN_TIM_AB4_PRI_OPEN;	/* 0x254 */
+	uint32_t CHN_TIM_AB4_PRI_CLOSED;/* 0x258 */
+	uint32_t CHN_TIM_AUTO_SELF_REFRESH;/* 0x25c */
+#define MEMC_DDR_AUTO_SELFREFRESH_EN              (1 << 31)
+#define MEMC_DDR_AUTO_SR_IDLE_CNT_MASK            (0x7FFFFFFF)
+	uint32_t CHN_TIM_AUTO_ZQCS;	/* 0x260 */
+	uint32_t CHN_TIM_TIM3;		/* 0x264 */
+	uint32_t unused9[38];		/* 0x268-0x2ff */
+
+	uint32_t ARB_CFG;		/* 0x300 */
+	uint32_t ARB_QUE_DIS[2];	/* 0x304 */
+	uint32_t unused10;		/* 0x30c */
+	uint32_t ARB_BKT_CFG_CPU_WR[4];	/* 0x310 */
+	uint32_t ARB_BKT_CFG_CPU_RD[4];	/* 0x320 */
+	uint32_t ARB_BKT_CFG_CPQ_RD[4];	/* 0x330 */
+	uint32_t ARB_BKT_CFG_CPQ_WR[4];	/* 0x340 */
+	uint32_t ARB_BKT_CFG_EDIS[4];	/* 0x350 */
+	uint32_t unused11[32];		/* 0x360 */
+	uint32_t ARB_QUEUE_PRI[3];	/* 0x3e0 */
+	uint32_t ARB_WRR_QUEUE_PRI;	/* 0x3ec */
+	uint32_t ARB_RATE_OK_WEIGHT[2];	/* 0x3f0 */
+	uint32_t ARB_RATE_FAIL_WEIGHT[2];/* 0x3f8 */
+
+	uint32_t unused12[48];		/* 0x400 */
+	AXIInterface AXIWIF;		/* 0x4c0 */
+
+	uint32_t unused13[192];		/* 0x500-0x7ff */
+
+	EDISEngine EDIS_0;		/* 0x800 */
+	uint32_t unused14[64];		/* 0x900 */
+
+	uint32_t STATS_CTRL;		/* 0xa00 */
+	uint32_t STATS_TIMER_CFG;	/* 0xa04 */
+	uint32_t STATS_TIMER_COUNT;	/* 0xa08 */
+	uint32_t STATS_TOTAL_SLICE;	/* 0xa0c */
+	uint32_t STATS_TOTAL_PACKET;	/* 0xa10 */
+	uint32_t STATS_TOTAL_READ_SLICE;/* 0xa14 */
+	uint32_t STATS_TOTAL_READ_PACKET;/* 0xa18 */
+	uint32_t STATS_TOTAL_LATENCY;	/* 0xa1c */
+	uint32_t STAT_MAX_LATENCY;	/* 0xa20 */
+	uint32_t STATS_SLICE_REORDER;	/* 0xa24 */
+	uint32_t STATS_TOTAL_DDR_CMD;	/* 0xa28 */
+	uint32_t STATS_TOTAL_DDR_ACT;	/* 0xa2c */
+	uint32_t STATS_TOTAL_DDR_RDWR;	/* 0xa30 */
+	uint32_t STATS_TOTAL_DDR_WRRD;	/* 0xa34 */
+	uint32_t STATS_TOTAL_MRQ_CHN_FULL;/* 0xa38 */
+	uint32_t STATS_TOTAL_SELF_REF;	/* 0xa3c */
+	uint32_t STATS_ARB_GRANT_MATCH0;/* 0xa40 */
+	uint32_t STATS_TOTAL_QUEUE_FULL;/* 0xa44 */
+	uint32_t STATS_TOTAL_ARB_GRANT;	/* 0xa48 */
+	uint32_t STATS_TOTAL_RATE_OK_GRANT;/* 0xa4c*/
+	uint32_t STATS_FILTER_CFG_0;	/* 0xa50 */
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT  25
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_MASK   (0x1<<MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_EN     0x02000000
+#define MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT     16
+#define MEMC_STATS_FILTER_CFG_SRC_ID_MASK      (0x1FF<<MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_SHIFT 0
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_MASK  0x0000FFFF
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS        0x00000001
+#define MEMC_STATS_FILTER_CFG_INTF_AXI         0x00000002
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS0       0x00000004
+#define MEMC_STATS_FILTER_CFG_INTF_UNUSED      0x00000008
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS0       MEMC_STATS_FILTER_CFG_INTF_UBUS
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_MCP         MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+	uint32_t STATS_PROG0_SLICE;	/* 0xa54 */
+	uint32_t STATS_PROG0_PACKET;	/* 0xa58 */
+	uint32_t STATS_PROG0_READ_SLICE;/* 0xa5c */
+	uint32_t STATS_PROG0_READ_PACKET;/* 0xa60 */
+	uint32_t STATS_PROG0_LATENCY;	/* 0xa64 */ 
+	uint32_t STATS_PROG0_MAX_LETANCY;/* 0xa68 */
+
+	// uint32_t unused15[37];	/* 0xa6c */
+	uint32_t unused15_0;		/* 0xa6c */
+	uint32_t STATS_FILTER_CFG_1;	/* 0xa70 */
+	uint32_t STATS_PROG1_SLICE;	/* 0xa74 */
+	uint32_t STATS_PROG1_PACKET;	/* 0xa78 */ 
+	uint32_t STATS_PROG1_READ_SLICE;/* 0xa7c */  
+	uint32_t STATS_PROG1_READ_PACKET;/* 0xa80 */
+	uint32_t STATS_PROG1_LATENCY;	/* 0xa84 */ 
+	uint32_t unused15_1[2];		/* 0xa88 - 0xa8c */   
+	uint32_t STATS_FILTER_CFG_2;	/* 0xa90 */
+	uint32_t STATS_PROG2_SLICE;	/* 0xa94 */
+	uint32_t STATS_PROG2_PACKET;	/* 0xa98 */ 
+	uint32_t STATS_PROG2_READ_SLICE;/* 0xa9c */  
+	uint32_t STATS_PROG2_READ_PACKET;/* 0xaa0 */
+	uint32_t STATS_PROG2_LATENCY;	/* 0xaa4 */ 
+	uint32_t unused15_2[2];		/* 0xaa8 - 0xaac */
+	uint32_t STATS_FILTER_CFG_3;	/* 0xab0 */
+	uint32_t STATS_PROG3_SLICE;	/* 0xab4 */
+	uint32_t STATS_PROG3_PACKET;	/* 0xab8 */ 
+	uint32_t STATS_PROG3_READ_SLICE;/* 0xabc */  
+	uint32_t STATS_PROG3_READ_PACKET;/* 0xac0 */
+	uint32_t STATS_PROG3_LATENCY;	/* 0xac4 */
+	uint32_t unused15_3[2];		/* 0xac8 - 0xacc */
+	uint32_t STATS_AXI_BLOCK_CPU_RD;/* 0xad0 */    
+	uint32_t STATS_AXI_BLOCK_CPQ_RD;/* 0xad4 */    
+	uint32_t unused15_4[10];	/* 0xad8 - 0xaff */
+   
+	uint32_t CAP_CAPTURE_CFG;	/* 0xb00 */
+	uint32_t CAP_TRIGGER_ADDR;	/* 0xb04 */
+	uint32_t CAP_READ_CTRL;		/* 0xb08 */
+	uint32_t unused16;		/* 0xb0c */
+	uint32_t CAP_CAPTURE_MATCH0;	/* 0xb10 */
+	uint32_t CAP_CAPTURE_MATCH1;	/* 0xb14 */
+	uint32_t CAP_CAPTURE_MATCH2;	/* 0xb18 */
+	uint32_t unused17;		/* 0xb1c */
+	uint32_t CAP_CAPTURE_MASK0;	/* 0xb20 */
+	uint32_t CAP_CAPTURE_MASK1;	/* 0xb24 */
+	uint32_t CAP_CAPTURE_MASK2;	/* 0xb28 */
+	uint32_t unused18;		/* 0xb2c */
+	uint32_t CAP_TRIGGER_MATCH0;	/* 0xb30 */
+	uint32_t CAP_TRIGGER_MATCH1;	/* 0xb34 */
+	uint32_t CAP_TRIGGER_MATCH2;	/* 0xb38 */
+	uint32_t unused19;		/* 0xb3c */
+	uint32_t CAP_TRIGGER_MASK0;	/* 0xb40 */
+	uint32_t CAP_TRIGGER_MASK1;	/* 0xb44 */
+	uint32_t CAP_TRIGGER_MASK2;	/* 0xb48 */
+	uint32_t unused20;		/* 0xb4c */
+	uint32_t CAP_READ_DATA[8];	/* 0xb50-0xb6f */
+	uint32_t unused21[164];		/* 0xb70-0xdff */
+
+	uint32_t SEC_INTR2_CPU_STATUS;	/* 0xe00 */
+	uint32_t SEC_INTR2_CPU_SET;	/* 0xe04 */
+	uint32_t SEC_INTR2_CPU_CLEAR;	/* 0xe08 */
+	uint32_t SEC_INTR2_CPU_MASK_STATUS;/* 0xe0c */
+	uint32_t SEC_INTR2_CPU_MASK_SET;/* 0xe10 */
+	uint32_t SEC_INTR2_CPU_MASK_CLEAR;/* 0xe14 */
+	uint32_t unused22[58];		/* 0xe18-0xeff */
+
+	uint32_t UBUSIF0_PERMCTL;	/* 0xf00 */
+	uint32_t UBUSIF1_PERMCTL;	/* 0xf04 */
+	uint32_t SRAM_REMAP_PERMCTL;	/* 0xf08 */
+	uint32_t AXIWIF_PERMCTL;	/* 0xf0c */
+	uint32_t CHNCFG_PERMCTL;	/* 0xf10 */
+	uint32_t MCCAP_PERMCTL;		/* 0xf14 */
+	uint32_t SCRAM_PERMCTL;		/* 0xf18 */
+	uint32_t RNG_PERMCTL;		/* 0xf1c */
+	uint32_t RNGCHK_PERMCTL;	/* 0xf20 */
+	uint32_t unused23[567];		/* 0xf24-0x17ff */
+
+	SecureRangeCheckers SEC_RANGE_CHK;/* 0x1800-0x18ff */
+	uint32_t unused24[31168];	/* 0x1900-0x1ffff */
+
+	DDRPhyControl PhyControl;	/* 0x20000 */
+	DDRPhyByteLaneControl PhyByteLane0Control;/* 0x20400 - 0x205ff */
+	DDRPhyByteLaneControl PhyByteLane1Control;/* 0x20600 - 0x207ff */
+} MEMCControl;
+
+
+#define MEMC ((volatile MEMCControl * const) MEMC_BASE)
+
+
+#endif /* _63178_DDR_H */
diff --git a/arch/arm/include/asm/arch-bcm63178/ethsw.h b/arch/arm/include/asm/arch-bcm63178/ethsw.h
new file mode 100644
index 0000000000..ec1da6ff51
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/ethsw.h
@@ -0,0 +1,4650 @@
+#include <config.h>
+#include <common.h>
+#include <stdlib.h>
+
+typedef struct {
+    uint32_t led_ctrl;
+#define SPDLNK_LED1_ACT_POL_SEL_SHIFT 7
+#define SPDLNK_LED1_ACT_POL_SEL_MASK (0x1 << SPDLNK_LED1_ACT_POL_SEL_SHIFT)
+#define ACT_LED_ACT_SEL_SHIFT 5
+#define ACT_LED_ACT_SEL_MASK (0x1 << ACT_LED_ACT_SEL_SHIFT)
+#define SPDLNK_LED0_ACT_SEL_SHIFT 2
+#define SPDLNK_LED0_ACT_SEL_MASK (0x1 << SPDLNK_LED0_ACT_SEL_SHIFT)
+#define RESERVED0_SHIFT 16
+#define RESERVED0_MASK (0xffff << RESERVED0_SHIFT)
+#define SPDLNK_LED0_ACT_POL_SEL_SHIFT 6
+#define SPDLNK_LED0_ACT_POL_SEL_MASK (0x1 << SPDLNK_LED0_ACT_POL_SEL_SHIFT)
+#define AGGREGATE_LED_CNTRL_RESERVED0_SHIFT 19
+#define AGGREGATE_LED_CNTRL_RESERVED0_MASK (0x1fff << AGGREGATE_LED_CNTRL_RESERVED0_SHIFT)
+#define AGGREGATE_LED_CNTRL_ACT_POL_SEL_SHIFT 17
+#define AGGREGATE_LED_CNTRL_ACT_POL_SEL_MASK (0x1 << AGGREGATE_LED_CNTRL_ACT_POL_SEL_SHIFT)
+#define SPDLNK_LED2_ACT_SEL_SHIFT 4
+#define SPDLNK_LED2_ACT_SEL_MASK (0x1 << SPDLNK_LED2_ACT_SEL_SHIFT)
+#define LED_SPD_OVRD_SHIFT 10
+#define LED_SPD_OVRD_MASK (0x7 << LED_SPD_OVRD_SHIFT)
+#define SPDLNK_LED2_ACT_POL_SEL_SHIFT 8
+#define SPDLNK_LED2_ACT_POL_SEL_MASK (0x1 << SPDLNK_LED2_ACT_POL_SEL_SHIFT)
+#define SPD_OVRD_EN_SHIFT 14
+#define SPD_OVRD_EN_MASK (0x1 << SPD_OVRD_EN_SHIFT)
+#define TX_ACT_EN_SHIFT 1
+#define TX_ACT_EN_MASK (0x1 << TX_ACT_EN_SHIFT)
+#define AGGREGATE_LED_CNTRL_ACT_SEL_SHIFT 16
+#define AGGREGATE_LED_CNTRL_ACT_SEL_MASK (0x1 << AGGREGATE_LED_CNTRL_ACT_SEL_SHIFT)
+#define LNK_STATUS_OVRD_SHIFT 13
+#define LNK_STATUS_OVRD_MASK (0x1 << LNK_STATUS_OVRD_SHIFT)
+#define RX_ACT_EN_SHIFT 0
+#define RX_ACT_EN_MASK (0x1 << RX_ACT_EN_SHIFT)
+#define AGGREGATE_LED_CNTRL_LNK_POL_SEL_SHIFT 18
+#define AGGREGATE_LED_CNTRL_LNK_POL_SEL_MASK (0x1 << AGGREGATE_LED_CNTRL_LNK_POL_SEL_SHIFT)
+#define SPDLNK_LED1_ACT_SEL_SHIFT 3
+#define SPDLNK_LED1_ACT_SEL_MASK (0x1 << SPDLNK_LED1_ACT_SEL_SHIFT)
+#define ACT_LED_POL_SEL_SHIFT 9
+#define ACT_LED_POL_SEL_MASK (0x1 << ACT_LED_POL_SEL_SHIFT)
+#define LNK_OVRD_EN_SHIFT 15
+#define LNK_OVRD_EN_MASK (0x1 << LNK_OVRD_EN_SHIFT)
+#define AGGREGATE_LED_CNTRL_PORT_EN_SHIFT 0
+#define AGGREGATE_LED_CNTRL_PORT_EN_MASK (0xffff << AGGREGATE_LED_CNTRL_PORT_EN_SHIFT)
+    uint32_t led_encoding_sel;
+    uint32_t led_encoding;
+#define LINK_AND_SPEED_ENCODING_M10G_ENCODE_SHIFT 15
+#define LINK_AND_SPEED_ENCODING_M10G_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M10G_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_SHIFT 3
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_SHIFT 6
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_SHIFT 15
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M10_ENCODE_SHIFT 3
+#define LINK_AND_SPEED_ENCODING_M10_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M10_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M1000_ENCODE_SHIFT 9
+#define LINK_AND_SPEED_ENCODING_M1000_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M1000_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_SHIFT 12
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M100_ENCODE_SHIFT 6
+#define LINK_AND_SPEED_ENCODING_M100_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M100_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_SHIFT 9
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M2500_ENCODE_SHIFT 12
+#define LINK_AND_SPEED_ENCODING_M2500_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M2500_ENCODE_SHIFT)
+
+}LED_CFG;
+
+typedef struct EthernetSwitchReg
+{
+    uint32_t switch_ctrl;                      /* 0x0000 */
+#define ETHSW_SWITCH_CTRL_SWITCH_CLK_SEL_SHIFT  27
+#define ETHSW_SWITCH_CTRL_SWITCH_CLK_SEL_MASK   (0x3<<ETHSW_SWITCH_CTRL_SWITCH_CLK_SEL_SHIFT)
+#define ETHSW_SWITCH_CTRL_SYSPORT_CLK_SEL_SHIFT 24
+#define ETHSW_SWITCH_CTRL_SYSPORT_CLK_SEL_MASK  (0x3<<ETHSW_SWITCH_CTRL_SYSPORT_CLK_SEL_SHIFT)
+#define ETHSW_SWITCH_CTRL_P8_CLK_SEL_SHIFT      3
+#define ETHSW_SWITCH_CTRL_P8_CLK_SEL_MASK       (0x3<<ETHSW_SWITCH_CTRL_P8_CLK_SEL_SHIFT)
+    uint32_t switch_status;                    /* 0x0004 */
+    uint32_t dir_data_write_reg;               /* 0x0008 */
+    uint32_t dir_data_read_reg;                /* 0x000c */
+    uint32_t switch_rev;                       /* 0x0010 */
+    uint32_t phy_rev;                          /* 0x0014 */
+    uint32_t phy_test_ctrl;                    /* 0x0018 */
+    uint32_t qphy_ctrl;                        /* 0x001c */
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT     12
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_MASK      (0x1f<<ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT)
+#define ETHSW_QPHY_CTRL_RESET_SHIFT          8
+#define ETHSW_QPHY_CTRL_RESET_MASK           (0x1<<ETHSW_QPHY_CTRL_RESET_SHIFT )
+#define ETHSW_QPHY_CTRL_CK25_DIS_SHIFT       7
+#define ETHSW_QPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_QPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_MASK    (0xf<<ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      6
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+
+
+    uint32_t qphy_status;                      /* 0x0020 */
+    uint32_t sphy_ctrl;                        /* 0x0024 */
+#define ETHSW_SPHY_CTRL_PHYAD_SHIFT          8
+#define ETHSW_SPHY_CTRL_PHYAD_MASK           (0x1f<<ETHSW_SPHY_CTRL_PHYAD_SHIFT)
+#define ETHSW_SPHY_CTRL_RESET_SHIFT          5
+#define ETHSW_SPHY_CTRL_RESET_MASK           (0x1<<ETHSW_SPHY_CTRL_RESET_SHIFT )
+#define ETHSW_SPHY_CTRL_CK25_DIS_SHIFT       4
+#define ETHSW_SPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_SPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_MASK    (0x1<<ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      3
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+    uint32_t sphy_status;                      /* 0x0028 */
+    uint32_t switch_phy_intr_ctrl;             /* 0x002c */
+    uint32_t reserved2[4];                     /* 0x0030 - 0x003f */
+    LED_CFG led_ctrl[9];                     /* 0x0040 - 0x00ab */  //63178: port6,7 not populated
+    LED_CFG reserved_ac;                     /* 0x00ac - 0x00b7 */  //63178: led_wan_ctrl not populated
+#define ETHSW_LED_CTRL_SPD0_ON               0x0
+#define ETHSW_LED_CTRL_SPD0_OFF              0x1
+#define ETHSW_LED_CTRL_SPD1_ON               0x0
+#define ETHSW_LED_CTRL_SPD1_OFF              0x2
+#define ETHSW_LED_CTRL_1000M_SHIFT           9
+#define ETHSW_LED_CTRL_100M_SHIFT            6
+#define ETHSW_LED_CTRL_10M_SHIFT             3
+#define ETHSW_LED_CTRL_NOLINK_SHIFT          0
+#define ETHSW_LED_CTRL_ALL_SPEED_MASK        0x3ffff
+#define ETHSW_LED_CTRL_SPEED_MASK            0x7
+    uint32_t led_blink_rate_ctrl;              /* 0x00b8 */
+    uint32_t reserved_bc;                      /* 0x00bc */           //63178: led_serial_ctrl not populated
+    uint32_t led_refresh_period_ctrl;          /* 0x00c0 */
+    uint32_t aggregate_led_ctrl;               /* 0x00c4 */
+#define ETHSW_AGGREGATE_LED_CTRL_PORT_EN_MASK            0xffff
+#define ETHSW_AGGREGATE_LED_CTRL_ACT_SEL_MASK            0x10000
+#define ETHSW_AGGREGATE_LED_CTRL_ACT_POL_SEL_MASK        0x20000
+#define ETHSW_AGGREGATE_LED_CTRL_LNK_POL_SEL_MASK        0x40000
+    uint32_t aggregate_blink_rate_ctrl;        /* 0x00c8 */
+#define ETHSW_QGPHY3_LED_OVRD_SHIFT           29 /*0x1c*/
+#define ETHSW_QGPHY3_LED_OVRD_MASK            (1 << ETHSW_QGPHY3_LED_OVRD_SHIFT)
+    uint32_t reserved_cc;                      /* 0x00cc */           //63178: crossbar_switch_ctrl not populated
+    uint32_t reserved_d0[19];                  /* 0x00d0 - 0x011b */
+    uint32_t rgmii_5_ctrl;                     /* 0x011c */           //63178: add rgmii_5, remove rgmii_11,12,13
+#define ETHSW_RC_MII_MODE_MASK               0x1c
+#define ETHSW_RC_EXT_RVMII                   0x10
+#define ETHSW_RC_EXT_GPHY                    0x0c
+#define ETHSW_RC_EXT_EPHY                    0x08
+#define ETHSW_RC_INT_GPHY                    0x04
+#define ETHSW_RC_INT_EPHY                    0x00
+#define ETHSW_RC_ID_MODE_DIS                 0x02
+#define ETHSW_RC_RGMII_EN                    0x01
+    uint32_t rgmii_5_ib_status;                /* 0x0120 */
+    uint32_t rgmii_5_rx_clk_delay_ctrl;        /* 0x0124 */
+#define ETHSW_RXCLK_IDDQ                     (1<<4)
+#define ETHSW_RXCLK_BYPASS                   (1<<5)
+    uint32_t reserved_128[202];                 /* 0x0128 - 0x044f */
+    uint32_t moca_bp_mapping_port5;            /* 0x0450*/
+} EthernetSwitchReg;
+
+
+/*
+** Eth Switch Registers
+*/
+typedef struct {
+    unsigned int led_f;
+    unsigned int reserved;
+} LED_F;
+
+typedef struct EthernetSwitchCore
+{
+	uint64_t port_traffic_ctrl[9];
+	uint8_t dummy1[8];
+	uint64_t SWITCH_CORE_RX_GLOBAL_CTL;
+#define ETHSW_SM_RETRY_LIMIT_DIS                  0x04
+#define ETHSW_SM_FORWARDING_EN                    0x02
+#define ETHSW_SM_MANAGED_MODE                     0x01
+	uint32_t switch_mode;
+	uint8_t dummy2[148];
+	uint32_t SWITCH_CORE_DEBUG_REG;
+	uint8_t dummy3[20];
+	uint64_t SWITCH_CORE_NEW_CTRL;
+	uint32_t switch_ctrl;
+#define ETHSW_SC_MII_DUMP_FORWARDING_EN           0x40
+#define ETHSW_SC_MII2_VOL_SEL                     0x02
+	uint8_t dummy4[12];
+	uint32_t SWITCH_CORE_PROTECTED_SEL;
+	uint8_t dummy5[12];
+	uint32_t SWITCH_CORE_WAN_PORT_SEL;
+	uint8_t dummy6[68];
+	uint32_t SWITCH_CORE_RSV_MCAST_CTRL;
+	uint8_t dummy7[12];
+	uint64_t SWITCH_CORE_TXQ_FLUSH_MODE;
+	uint32_t SWITCH_CORE_ULF_DROP_MAP;
+	uint8_t dummy8[12];
+	uint32_t SWITCH_CORE_MLF_DROP_MAP;
+	uint8_t dummy9[12];
+	uint32_t SWITCH_CORE_MLF_IPMC_FWD_MAP;
+	uint8_t dummy10[12];
+	uint32_t SWITCH_CORE_RX_PAUSE_PASS;
+	uint8_t dummy11[12];
+	uint32_t SWITCH_CORE_TX_PAUSE_PASS;
+	uint8_t dummy12[12];
+	uint32_t SWITCH_CORE_DIS_LEARN;
+	uint8_t dummy13[12];
+	uint32_t SWITCH_CORE_SFT_LRN_CTL;
+	uint8_t dummy14[12];
+	uint32_t SWITCH_CORE_LOW_POWER_EXP1;
+	uint8_t dummy15[156];
+	uint32_t SWITCH_CORE_CTLREG_REG_SPARE;
+	uint8_t dummy16[292];
+	uint64_t software_reset;
+	uint32_t SWITCH_CORE_WATCH_DOG_RPT1;
+	uint8_t dummy17[12];
+	uint32_t SWITCH_CORE_WATCH_DOG_RPT2;
+	uint8_t dummy18[12];
+	uint32_t SWITCH_CORE_WATCH_DOG_RPT3;
+	uint8_t dummy19[12];
+	uint64_t SWITCH_CORE_PAUSE_FRM_CTRL;
+	uint32_t SWITCH_CORE_PAUSE_ST_ADDR;
+	uint8_t dummy20[52];
+	uint64_t SWITCH_CORE_FAST_AGE_CTRL;
+	uint64_t SWITCH_CORE_FAST_AGE_PORT;
+	uint32_t SWITCH_CORE_FAST_AGE_VID;
+	uint8_t dummy21[668];
+	uint32_t SWITCH_CORE_LOW_POWER_CTRL;
+	uint8_t dummy22[76];
+	uint32_t SWITCH_CORE_TCAM_CTRL;
+	uint8_t dummy23[12];
+	uint32_t SWITCH_CORE_TCAM_CHKSUM_STS;
+	uint8_t dummy24[12];
+	uint32_t SWITCH_CORE_LIGHTSTACK_CTRL;
+	uint8_t dummy25[156];
+	uint32_t SWITCH_CORE_LNKSTS;
+	uint8_t dummy26[12];
+	uint32_t SWITCH_CORE_LNKSTSCHG;
+	uint8_t dummy27[12];
+	uint32_t SWITCH_CORE_SPDSTS;
+	uint8_t dummy28[28];
+	uint32_t SWITCH_CORE_DUPSTS;
+	uint8_t dummy29[12];
+	uint32_t SWITCH_CORE_PAUSESTS;
+	uint8_t dummy30[28];
+	uint32_t SWITCH_CORE_SRCADRCHG;
+	uint8_t dummy31[12];
+	uint32_t SWITCH_CORE_LSA_PORT_P0;
+	uint8_t dummy32[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P1;
+	uint8_t dummy33[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P2;
+	uint8_t dummy34[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P3;
+	uint8_t dummy35[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P4;
+	uint8_t dummy36[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P5;
+	uint8_t dummy37[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P6;
+	uint8_t dummy38[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P7;
+	uint8_t dummy39[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P8;
+	uint8_t dummy40[44];
+	uint32_t SWITCH_CORE_BIST_STS0;
+	uint8_t dummy41[44];
+	uint32_t SWITCH_CORE_BIST_STS1;
+	uint8_t dummy42[28];
+	uint32_t SWITCH_CORE_PBPTRFIFO_0;
+	uint8_t dummy43[44];
+	uint32_t SWITCH_CORE_PBPTRFIFO_1;
+	uint8_t dummy44[460];
+	uint32_t SWITCH_CORE_RESET_STATUS;
+	uint8_t dummy45[124];
+	uint32_t SWITCH_CORE_STREG_REG_SPARE0;
+	uint8_t dummy46[28];
+	uint32_t SWITCH_CORE_STREG_REG_SPARE1;
+	uint8_t dummy47[732];
+	uint64_t SWITCH_CORE_GMNGCFG;
+	uint64_t SWITCH_CORE_IMP0_PRT_ID;
+	uint64_t SWITCH_CORE_IMP1_PRT_ID;
+	uint32_t brcm_hdr_ctrl;
+	uint8_t dummy48[20];
+	uint32_t SWITCH_CORE_SPTAGT;
+	uint8_t dummy49[28];
+	uint32_t SWITCH_CORE_BRCM_HDR_CTRL2;
+	uint8_t dummy50[12];
+	uint32_t SWITCH_CORE_IPG_SHRNK_CTRL;
+	uint8_t dummy51[28];
+	uint32_t SWITCH_CORE_MIRCAPCTL;
+	uint8_t dummy52[12];
+	uint32_t SWITCH_CORE_IGMIRCTL;
+	uint8_t dummy53[12];
+	uint32_t SWITCH_CORE_IGMIRDIV;
+	uint8_t dummy54[12];
+	uint32_t SWITCH_CORE_IGMIRMAC;
+	uint8_t dummy55[44];
+	uint32_t SWITCH_CORE_EGMIRCTL;
+	uint8_t dummy56[12];
+	uint32_t SWITCH_CORE_EGMIRDIV;
+	uint8_t dummy57[12];
+	uint32_t SWITCH_CORE_EGMIRMAC;
+	uint8_t dummy58[44];
+	uint32_t SWITCH_CORE_SPANCTL;
+	uint8_t dummy59[28];
+	uint32_t SWITCH_CORE_RSPANVLAN;
+	uint8_t dummy60[300];
+	uint32_t SWITCH_CORE_HL_PRTC_CTRL;
+	uint8_t dummy61[28];
+	uint32_t SWITCH_CORE_RST_MIB_CNT_EN;
+	uint8_t dummy62[28];
+	uint32_t SWITCH_CORE_IPG_SHRINK_2G_WA;
+	uint8_t dummy63[60];
+	uint32_t SWITCH_CORE_BRCM_HDR_RX_DIS;
+	uint8_t dummy64[12];
+	uint32_t SWITCH_CORE_BRCM_HDR_TX_DIS;
+	uint8_t dummy65[108];
+	uint32_t SWITCH_CORE_MNGMODE_REG_SPARE0;
+	uint8_t dummy66[28];
+	uint32_t SWITCH_CORE_MNGMODE_REG_SPARE1;
+	uint8_t dummy67[1116];
+	uint32_t SWITCH_CORE_INT_STS;
+	uint8_t dummy68[60];
+	uint32_t SWITCH_CORE_INT_EN;
+	uint8_t dummy69[60];
+	uint32_t SWITCH_CORE_SLEEP_TIMER_IMP;
+	uint8_t dummy70[12];
+	uint32_t SWITCH_CORE_PORT7_SLEEP_TIMER;
+	uint8_t dummy71[12];
+	uint32_t SWITCH_CORE_WAN_SLEEP_TIMER;
+	uint8_t dummy72[28];
+	uint32_t SWITCH_CORE_PORT_SLEEP_STS;
+	uint8_t dummy73[92];
+	uint32_t SWITCH_CORE_LINK_STS_INT_EN;
+	uint8_t dummy74[28];
+	uint32_t SWITCH_CORE_ENG_DET_INT_EN;
+	uint8_t dummy75[12];
+	uint32_t SWITCH_CORE_LPI_STS_CHG_INT_EN;
+	uint8_t dummy76[428];
+	uint32_t SWITCH_CORE_MEM_ECC_ERR_INT_STS;
+	uint8_t dummy77[12];
+	uint32_t SWITCH_CORE_MEM_ECC_ERR_INT_EN;
+	uint8_t dummy78[12];
+	uint32_t SWITCH_CORE_PORT_EVT_ECC_ERR_STS;
+	uint8_t dummy79[12];
+	uint32_t SWITCH_CORE_PORT_MIB_ECC_ERR_STS;
+	uint8_t dummy80[12];
+	uint32_t SWITCH_CORE_PORT_TXQ_ECC_ERR_STS;
+	uint8_t dummy81[60];
+	uint32_t SWITCH_CORE_PROBE_BUS_CTL;
+	uint8_t dummy82[28];
+	uint32_t SWITCH_CORE_MDC_EXTEND_CTRL;
+	uint8_t dummy83[92];
+	uint32_t SWITCH_CORE_PPPOE_SESSION_PARSE_EN;
+	uint8_t dummy84[124];
+	uint32_t SWITCH_CORE_CTLREG_1_REG_SPARE0;
+	uint8_t dummy85[28];
+	uint32_t SWITCH_CORE_CTLREG_1_REG_SPARE1;
+	uint8_t dummy86[860];
+	uint32_t SWITCH_CORE_GARLCFG;
+	uint8_t dummy87[28];
+	uint32_t SWITCH_CORE_BPDU_MCADDR;
+	uint8_t dummy88[76];
+	uint32_t SWITCH_CORE_MULTI_PORT_CTL;
+	uint8_t dummy89[12];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR0;
+	uint8_t dummy90[60];
+	uint32_t SWITCH_CORE_MPORTVEC0;
+	uint8_t dummy91[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR1;
+	uint8_t dummy92[60];
+	uint32_t SWITCH_CORE_MPORTVEC1;
+	uint8_t dummy93[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR2;
+	uint8_t dummy94[60];
+	uint32_t SWITCH_CORE_MPORTVEC2;
+	uint8_t dummy95[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR3;
+	uint8_t dummy96[60];
+	uint32_t SWITCH_CORE_MPORTVEC3;
+	uint8_t dummy97[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR4;
+	uint8_t dummy98[60];
+	uint32_t SWITCH_CORE_MPORTVEC4;
+	uint8_t dummy99[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR5;
+	uint8_t dummy100[60];
+	uint32_t SWITCH_CORE_MPORTVEC5;
+	uint8_t dummy101[60];
+	uint32_t SWITCH_CORE_ARL_BIN_FULL_CNTR;
+	uint8_t dummy102[28];
+	uint32_t SWITCH_CORE_ARL_BIN_FULL_FWD;
+	uint8_t dummy103[12];
+	uint32_t SWITCH_CORE_ARL_SEED;
+	uint8_t dummy104[76];
+	uint32_t SWITCH_CORE_ARLCTL_REG_SPARE0;
+	uint8_t dummy105[28];
+	uint32_t SWITCH_CORE_ARLCTL_REG_SPARE1;
+	uint8_t dummy106[92];
+	uint32_t SWITCH_CORE_ARL_TCAM_CTRL;
+	uint8_t dummy107[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_STS;
+	uint8_t dummy108[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_FULL_CNTR;
+	uint8_t dummy109[28];
+	uint32_t SWITCH_CORE_ARL_CPU_PORTMAP;
+	uint8_t dummy110[796];
+	uint32_t SWITCH_CORE_ARLA_RWCTL;
+	uint8_t dummy111[12];
+	uint32_t SWITCH_CORE_ARLA_MAC;
+	uint8_t dummy112[44];
+	uint32_t SWITCH_CORE_ARLA_VID;
+	uint8_t dummy113[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY0;
+	uint8_t dummy114[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY0;
+	uint8_t dummy115[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY1;
+	uint8_t dummy116[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY1;
+	uint8_t dummy117[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY2;
+	uint8_t dummy118[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY2;
+	uint8_t dummy119[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY3;
+	uint8_t dummy120[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY3;
+	uint8_t dummy121[60];
+	uint64_t SWITCH_CORE_ARLA_SRCH_CTL;
+	uint32_t SWITCH_CORE_ARLA_SRCH_ADR;
+	uint8_t dummy122[116];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID;
+	uint8_t dummy123[60];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_0;
+	uint8_t dummy124[60];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID;
+	uint8_t dummy125[60];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_1;
+	uint8_t dummy126[60];
+	uint64_t SWITCH_CORE_ARLA_VTBL_RWCTRL;
+	uint32_t SWITCH_CORE_ARLA_VTBL_ADDR;
+	uint8_t dummy127[12];
+	uint32_t SWITCH_CORE_ARLA_VTBL_ENTRY;
+	uint8_t dummy128[100];
+	uint32_t SWITCH_CORE_ARLACCS_REG_SPARE0;
+	uint8_t dummy129[28];
+	uint32_t SWITCH_CORE_ARLACCS_REG_SPARE1;
+	uint8_t dummy130[4956];
+	uint64_t SWITCH_CORE_MEM_CTRL;
+	uint32_t SWITCH_CORE_MEM_ADDR;
+	uint8_t dummy131[52];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_0_0;
+	uint8_t dummy132[60];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_0_1;
+	uint8_t dummy133[12];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_1_0;
+	uint8_t dummy134[60];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_1_1;
+	uint8_t dummy135[44];
+	uint32_t SWITCH_CORE_MEM_FRM_ADDR;
+	uint8_t dummy136[124];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA0;
+	uint8_t dummy137[60];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA1;
+	uint8_t dummy138[60];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA2;
+	uint8_t dummy139[60];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA3;
+	uint8_t dummy140[60];
+	uint32_t SWITCH_CORE_MEM_BTM_DATA0;
+	uint8_t dummy141[60];
+	uint32_t SWITCH_CORE_MEM_BTM_DATA1;
+	uint8_t dummy142[60];
+	uint32_t SWITCH_CORE_MEM_BFC_ADDR;
+	uint8_t dummy143[12];
+	uint32_t SWITCH_CORE_MEM_BFC_DATA;
+	uint8_t dummy144[108];
+	uint64_t SWITCH_CORE_PRS_FIFO_DEBUG_CTRL;
+	uint32_t SWITCH_CORE_PRS_FIFO_DEBUG_DATA;
+	uint8_t dummy145[116];
+	uint32_t SWITCH_CORE_MIBKILLOVR;
+	uint8_t dummy146[316];
+	uint32_t SWITCH_CORE_MEM_REG_SPARE0;
+	uint8_t dummy147[28];
+	uint32_t SWITCH_CORE_MEM_REG_SPARE1;
+	uint8_t dummy148[28];
+	uint32_t SWITCH_CORE_MEM_MISC_CTRL;
+	uint8_t dummy149[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL0;
+	uint8_t dummy150[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL1;
+	uint8_t dummy151[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL2;
+	uint8_t dummy152[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL3;
+	uint8_t dummy153[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL4;
+	uint8_t dummy154[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL5;
+	uint8_t dummy155[188];
+	uint32_t SWITCH_CORE_MEM_PSM_VDD_CTRL;
+	uint8_t dummy156[252];
+	uint32_t SWITCH_CORE_PORT0_DEBUG;
+	uint8_t dummy157[124];
+	uint32_t SWITCH_CORE_PORT1_DEBUG;
+	uint8_t dummy158[124];
+	uint32_t SWITCH_CORE_PORT2_DEBUG;
+	uint8_t dummy159[124];
+	uint32_t SWITCH_CORE_PORT3_DEBUG;
+	uint8_t dummy160[124];
+	uint32_t SWITCH_CORE_PORT4_DEBUG;
+	uint8_t dummy161[124];
+	uint32_t SWITCH_CORE_PORT5_DEBUG;
+	uint8_t dummy162[124];
+	uint32_t SWITCH_CORE_PORT6_DEBUG;
+	uint8_t dummy163[124];
+	uint32_t SWITCH_CORE_PORT7_DEBUG;
+	uint8_t dummy164[124];
+	uint32_t SWITCH_CORE_PORT8_DEBUG;
+	uint8_t dummy165[1020];
+	uint32_t SWITCH_CORE_FC_DIAG_CTRL;
+	uint8_t dummy166[12];
+	uint64_t SWITCH_CORE_FC_CTRL_MODE;
+	uint64_t SWITCH_CORE_FC_CTRL_PORT;
+	uint32_t SWITCH_CORE_FC_OOB_PAUSE_EN;
+	uint8_t dummy167[92];
+	uint32_t SWITCH_CORE_PAUSE_TIME_MAX;
+	uint8_t dummy168[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_MIN;
+	uint8_t dummy169[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_RESET_THD;
+	uint8_t dummy170[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD;
+	uint8_t dummy171[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_DEFAULT;
+	uint8_t dummy172[12];
+	uint32_t SWITCH_CORE_FC_MCAST_DROP_CTRL;
+	uint8_t dummy173[12];
+	uint32_t SWITCH_CORE_FC_PAUSE_DROP_CTRL;
+	uint8_t dummy174[12];
+	uint32_t SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF;
+	uint8_t dummy175[12];
+	uint32_t SWITCH_CORE_FC_RX_RUNOFF;
+	uint8_t dummy176[12];
+	uint32_t SWITCH_CORE_FC_RX_RSV_THD;
+	uint8_t dummy177[12];
+	uint32_t SWITCH_CORE_FC_RX_HYST_THD;
+	uint8_t dummy178[12];
+	uint32_t SWITCH_CORE_FC_RX_MAX_PTR;
+	uint8_t dummy179[12];
+	uint32_t SWITCH_CORE_FC_SPARE_ZERO_REG;
+	uint8_t dummy180[12];
+	uint32_t SWITCH_CORE_FC_SPARE_ONE_REG;
+	uint8_t dummy181[44];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q0;
+	uint8_t dummy182[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q1;
+	uint8_t dummy183[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q2;
+	uint8_t dummy184[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q3;
+	uint8_t dummy185[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q4;
+	uint8_t dummy186[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q5;
+	uint8_t dummy187[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q6;
+	uint8_t dummy188[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q7;
+	uint8_t dummy189[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q0;
+	uint8_t dummy190[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q1;
+	uint8_t dummy191[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q2;
+	uint8_t dummy192[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q3;
+	uint8_t dummy193[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q4;
+	uint8_t dummy194[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q5;
+	uint8_t dummy195[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q6;
+	uint8_t dummy196[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q7;
+	uint8_t dummy197[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TOTAL_USED;
+	uint8_t dummy198[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_USED;
+	uint8_t dummy199[12];
+	uint32_t SWITCH_CORE_FC_PEAK_RX_CNT;
+	uint8_t dummy200[12];
+	uint32_t SWITCH_CORE_FC_LINK_PORTMAP;
+	uint8_t dummy201[12];
+	uint32_t SWITCH_CORE_FC_GIGA_PORTMAP;
+	uint8_t dummy202[60];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P0;
+	uint8_t dummy203[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P1;
+	uint8_t dummy204[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P2;
+	uint8_t dummy205[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P3;
+	uint8_t dummy206[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P4;
+	uint8_t dummy207[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P5;
+	uint8_t dummy208[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P6;
+	uint8_t dummy209[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P7;
+	uint8_t dummy210[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P8;
+	uint8_t dummy211[60];
+	uint32_t SWITCH_CORE_FC_PAUSE_HIS;
+	uint8_t dummy212[12];
+	uint32_t SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS;
+	uint8_t dummy213[12];
+	uint32_t SWITCH_CORE_FC_RX_PAUSE_HIS;
+	uint8_t dummy214[12];
+	uint32_t SWITCH_CORE_FC_RXBUF_ERR_HIS;
+	uint8_t dummy215[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0;
+	uint8_t dummy216[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1;
+	uint8_t dummy217[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2;
+	uint8_t dummy218[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3;
+	uint8_t dummy219[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4;
+	uint8_t dummy220[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5;
+	uint8_t dummy221[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P6;
+	uint8_t dummy222[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7;
+	uint8_t dummy223[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8;
+	uint8_t dummy224[76];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0;
+	uint8_t dummy225[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1;
+	uint8_t dummy226[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2;
+	uint8_t dummy227[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3;
+	uint8_t dummy228[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4;
+	uint8_t dummy229[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5;
+	uint8_t dummy230[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P6;
+	uint8_t dummy231[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7;
+	uint8_t dummy232[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8;
+	uint8_t dummy233[684];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0;
+	uint8_t dummy234[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1;
+	uint8_t dummy235[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2;
+	uint8_t dummy236[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3;
+	uint8_t dummy237[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4;
+	uint8_t dummy238[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5;
+	uint8_t dummy239[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6;
+	uint8_t dummy240[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7;
+	uint8_t dummy241[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0;
+	uint8_t dummy242[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1;
+	uint8_t dummy243[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2;
+	uint8_t dummy244[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3;
+	uint8_t dummy245[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4;
+	uint8_t dummy246[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5;
+	uint8_t dummy247[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6;
+	uint8_t dummy248[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7;
+	uint8_t dummy249[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0;
+	uint8_t dummy250[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1;
+	uint8_t dummy251[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2;
+	uint8_t dummy252[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3;
+	uint8_t dummy253[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4;
+	uint8_t dummy254[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5;
+	uint8_t dummy255[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6;
+	uint8_t dummy256[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7;
+	uint8_t dummy257[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0;
+	uint8_t dummy258[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1;
+	uint8_t dummy259[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2;
+	uint8_t dummy260[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3;
+	uint8_t dummy261[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4;
+	uint8_t dummy262[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5;
+	uint8_t dummy263[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6;
+	uint8_t dummy264[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7;
+	uint8_t dummy265[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0;
+	uint8_t dummy266[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1;
+	uint8_t dummy267[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2;
+	uint8_t dummy268[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3;
+	uint8_t dummy269[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4;
+	uint8_t dummy270[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5;
+	uint8_t dummy271[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6;
+	uint8_t dummy272[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7;
+	uint8_t dummy273[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0;
+	uint8_t dummy274[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1;
+	uint8_t dummy275[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2;
+	uint8_t dummy276[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3;
+	uint8_t dummy277[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4;
+	uint8_t dummy278[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5;
+	uint8_t dummy279[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6;
+	uint8_t dummy280[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7;
+	uint8_t dummy281[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0;
+	uint8_t dummy282[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1;
+	uint8_t dummy283[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2;
+	uint8_t dummy284[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3;
+	uint8_t dummy285[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4;
+	uint8_t dummy286[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5;
+	uint8_t dummy287[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6;
+	uint8_t dummy288[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7;
+	uint8_t dummy289[1164];
+	uint32_t SWITCH_CORE_P0_DEBUG_MUX;
+	uint8_t dummy290[28];
+	uint32_t SWITCH_CORE_P1_DEBUG_MUX;
+	uint8_t dummy291[28];
+	uint32_t SWITCH_CORE_P2_DEBUG_MUX;
+	uint8_t dummy292[28];
+	uint32_t SWITCH_CORE_P3_DEBUG_MUX;
+	uint8_t dummy293[28];
+	uint32_t SWITCH_CORE_P4_DEBUG_MUX;
+	uint8_t dummy294[28];
+	uint32_t SWITCH_CORE_P5_DEBUG_MUX;
+	uint8_t dummy295[28];
+	uint32_t SWITCH_CORE_P6_DEBUG_MUX;
+	uint8_t dummy296[28];
+	uint32_t SWITCH_CORE_DEBUG_MUX_P7;
+	uint8_t dummy297[28];
+	uint32_t SWITCH_CORE_DEBUG_MUX_IMP;
+	uint8_t dummy298[28];
+	uint32_t SWITCH_CORE_CFP_DEBUG_BUS_0;
+	uint8_t dummy299[28];
+	uint32_t SWITCH_CORE_CFP_DEBUG_BUS_1;
+	uint8_t dummy300[28];
+	uint32_t SWITCH_CORE_WRED_DEBUG_0;
+	uint8_t dummy301[28];
+	uint32_t SWITCH_CORE_WRED_DEBUG_1;
+	uint8_t dummy302[28];
+	uint32_t SWITCH_CORE_TOP_MISC_DEBUG_0;
+	uint8_t dummy303[28];
+	uint32_t SWITCH_CORE_TOP_MISC_DEBUG_1;
+	uint8_t dummy304[28];
+	uint32_t SWITCH_CORE_DIAGREG_BUFCON;
+	uint8_t dummy305[28];
+	uint32_t SWITCH_CORE_TESTBUS_P1588;
+	uint8_t dummy306[28];
+	uint32_t SWITCH_CORE_FLOWCON_DEBUG_BUS;
+	uint8_t dummy307[1500];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0;
+	uint8_t dummy308[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1;
+	uint8_t dummy309[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2;
+	uint8_t dummy310[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3;
+	uint8_t dummy311[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4;
+	uint8_t dummy312[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5;
+	uint8_t dummy313[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6;
+	uint8_t dummy314[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7;
+	uint8_t dummy315[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0;
+	uint8_t dummy316[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1;
+	uint8_t dummy317[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2;
+	uint8_t dummy318[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3;
+	uint8_t dummy319[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4;
+	uint8_t dummy320[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5;
+	uint8_t dummy321[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6;
+	uint8_t dummy322[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7;
+	uint8_t dummy323[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0;
+	uint8_t dummy324[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1;
+	uint8_t dummy325[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2;
+	uint8_t dummy326[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3;
+	uint8_t dummy327[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4;
+	uint8_t dummy328[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5;
+	uint8_t dummy329[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6;
+	uint8_t dummy330[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7;
+	uint8_t dummy331[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0;
+	uint8_t dummy332[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1;
+	uint8_t dummy333[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2;
+	uint8_t dummy334[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3;
+	uint8_t dummy335[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4;
+	uint8_t dummy336[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5;
+	uint8_t dummy337[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6;
+	uint8_t dummy338[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7;
+	uint8_t dummy339[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0;
+	uint8_t dummy340[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1;
+	uint8_t dummy341[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2;
+	uint8_t dummy342[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3;
+	uint8_t dummy343[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4;
+	uint8_t dummy344[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5;
+	uint8_t dummy345[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6;
+	uint8_t dummy346[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7;
+	uint8_t dummy347[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0;
+	uint8_t dummy348[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1;
+	uint8_t dummy349[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2;
+	uint8_t dummy350[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3;
+	uint8_t dummy351[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4;
+	uint8_t dummy352[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5;
+	uint8_t dummy353[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6;
+	uint8_t dummy354[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7;
+	uint8_t dummy355[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0;
+	uint8_t dummy356[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1;
+	uint8_t dummy357[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2;
+	uint8_t dummy358[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3;
+	uint8_t dummy359[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4;
+	uint8_t dummy360[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5;
+	uint8_t dummy361[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6;
+	uint8_t dummy362[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7;
+	uint8_t dummy363[12];
+	uint32_t SWITCH_CORE_FC_IMP0_REG_SPARE0;
+	uint8_t dummy364[12];
+	uint32_t SWITCH_CORE_FC_IMP0_REG_SPARE1;
+	uint8_t dummy365[1132];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0;
+	uint8_t dummy366[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1;
+	uint8_t dummy367[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2;
+	uint8_t dummy368[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3;
+	uint8_t dummy369[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4;
+	uint8_t dummy370[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5;
+	uint8_t dummy371[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6;
+	uint8_t dummy372[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7;
+	uint8_t dummy373[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0;
+	uint8_t dummy374[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1;
+	uint8_t dummy375[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2;
+	uint8_t dummy376[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3;
+	uint8_t dummy377[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4;
+	uint8_t dummy378[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5;
+	uint8_t dummy379[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6;
+	uint8_t dummy380[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7;
+	uint8_t dummy381[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0;
+	uint8_t dummy382[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1;
+	uint8_t dummy383[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2;
+	uint8_t dummy384[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3;
+	uint8_t dummy385[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4;
+	uint8_t dummy386[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5;
+	uint8_t dummy387[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6;
+	uint8_t dummy388[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7;
+	uint8_t dummy389[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0;
+	uint8_t dummy390[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1;
+	uint8_t dummy391[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2;
+	uint8_t dummy392[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3;
+	uint8_t dummy393[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4;
+	uint8_t dummy394[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5;
+	uint8_t dummy395[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6;
+	uint8_t dummy396[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7;
+	uint8_t dummy397[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0;
+	uint8_t dummy398[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1;
+	uint8_t dummy399[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2;
+	uint8_t dummy400[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3;
+	uint8_t dummy401[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4;
+	uint8_t dummy402[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5;
+	uint8_t dummy403[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6;
+	uint8_t dummy404[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7;
+	uint8_t dummy405[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0;
+	uint8_t dummy406[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1;
+	uint8_t dummy407[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2;
+	uint8_t dummy408[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3;
+	uint8_t dummy409[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4;
+	uint8_t dummy410[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5;
+	uint8_t dummy411[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6;
+	uint8_t dummy412[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7;
+	uint8_t dummy413[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0;
+	uint8_t dummy414[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1;
+	uint8_t dummy415[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2;
+	uint8_t dummy416[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3;
+	uint8_t dummy417[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4;
+	uint8_t dummy418[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5;
+	uint8_t dummy419[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6;
+	uint8_t dummy420[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7;
+	uint8_t dummy421[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0;
+	uint8_t dummy422[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1;
+	uint8_t dummy423[35948];
+	uint32_t SWITCH_CORE_TxOctets_P0;
+	uint8_t dummy424[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P0;
+	uint8_t dummy425[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P0;
+	uint8_t dummy426[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P0;
+	uint8_t dummy427[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P0;
+	uint8_t dummy428[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P0;
+	uint8_t dummy429[28];
+	uint32_t SWITCH_CORE_TxCollisions_P0;
+	uint8_t dummy430[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P0;
+	uint8_t dummy431[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P0;
+	uint8_t dummy432[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P0;
+	uint8_t dummy433[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P0;
+	uint8_t dummy434[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P0;
+	uint8_t dummy435[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P0;
+	uint8_t dummy436[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P0;
+	uint8_t dummy437[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P0;
+	uint8_t dummy438[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P0;
+	uint8_t dummy439[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P0;
+	uint8_t dummy440[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P0;
+	uint8_t dummy441[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P0;
+	uint8_t dummy442[28];
+	uint32_t SWITCH_CORE_RxOctets_P0;
+	uint8_t dummy443[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P0;
+	uint8_t dummy444[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P0;
+	uint8_t dummy445[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P0;
+	uint8_t dummy446[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P0;
+	uint8_t dummy447[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P0;
+	uint8_t dummy448[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P0;
+	uint8_t dummy449[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P0;
+	uint8_t dummy450[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P0;
+	uint8_t dummy451[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P0;
+	uint8_t dummy452[28];
+	uint32_t SWITCH_CORE_RxJabbers_P0;
+	uint8_t dummy453[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P0;
+	uint8_t dummy454[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P0;
+	uint8_t dummy455[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P0;
+	uint8_t dummy456[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P0;
+	uint8_t dummy457[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P0;
+	uint8_t dummy458[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P0;
+	uint8_t dummy459[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P0;
+	uint8_t dummy460[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P0;
+	uint8_t dummy461[28];
+	uint32_t SWITCH_CORE_RxFragments_P0;
+	uint8_t dummy462[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P0;
+	uint8_t dummy463[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P0;
+	uint8_t dummy464[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P0;
+	uint8_t dummy465[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P0;
+	uint8_t dummy466[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P0;
+	uint8_t dummy467[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P0;
+	uint8_t dummy468[28];
+	uint32_t SWITCH_CORE_RxDiscard_P0;
+	uint8_t dummy469[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P0;
+	uint8_t dummy470[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P0;
+	uint8_t dummy471[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P0;
+	uint8_t dummy472[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P0;
+	uint8_t dummy473[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P0;
+	uint8_t dummy474[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P0;
+	uint8_t dummy475[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P0;
+	uint8_t dummy476[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P0;
+	uint8_t dummy477[220];
+	uint32_t SWITCH_CORE_TxOctets_P1;
+	uint8_t dummy478[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P1;
+	uint8_t dummy479[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P1;
+	uint8_t dummy480[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P1;
+	uint8_t dummy481[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P1;
+	uint8_t dummy482[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P1;
+	uint8_t dummy483[28];
+	uint32_t SWITCH_CORE_TxCollisions_P1;
+	uint8_t dummy484[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P1;
+	uint8_t dummy485[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P1;
+	uint8_t dummy486[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P1;
+	uint8_t dummy487[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P1;
+	uint8_t dummy488[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P1;
+	uint8_t dummy489[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P1;
+	uint8_t dummy490[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P1;
+	uint8_t dummy491[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P1;
+	uint8_t dummy492[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P1;
+	uint8_t dummy493[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P1;
+	uint8_t dummy494[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P1;
+	uint8_t dummy495[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P1;
+	uint8_t dummy496[28];
+	uint32_t SWITCH_CORE_RxOctets_P1;
+	uint8_t dummy497[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P1;
+	uint8_t dummy498[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P1;
+	uint8_t dummy499[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P1;
+	uint8_t dummy500[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P1;
+	uint8_t dummy501[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P1;
+	uint8_t dummy502[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P1;
+	uint8_t dummy503[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P1;
+	uint8_t dummy504[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P1;
+	uint8_t dummy505[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P1;
+	uint8_t dummy506[28];
+	uint32_t SWITCH_CORE_RxJabbers_P1;
+	uint8_t dummy507[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P1;
+	uint8_t dummy508[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P1;
+	uint8_t dummy509[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P1;
+	uint8_t dummy510[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P1;
+	uint8_t dummy511[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P1;
+	uint8_t dummy512[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P1;
+	uint8_t dummy513[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P1;
+	uint8_t dummy514[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P1;
+	uint8_t dummy515[28];
+	uint32_t SWITCH_CORE_RxFragments_P1;
+	uint8_t dummy516[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P1;
+	uint8_t dummy517[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P1;
+	uint8_t dummy518[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P1;
+	uint8_t dummy519[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P1;
+	uint8_t dummy520[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P1;
+	uint8_t dummy521[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P1;
+	uint8_t dummy522[28];
+	uint32_t SWITCH_CORE_RxDiscard_P1;
+	uint8_t dummy523[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P1;
+	uint8_t dummy524[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P1;
+	uint8_t dummy525[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P1;
+	uint8_t dummy526[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P1;
+	uint8_t dummy527[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P1;
+	uint8_t dummy528[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P1;
+	uint8_t dummy529[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P1;
+	uint8_t dummy530[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P1;
+	uint8_t dummy531[220];
+	uint32_t SWITCH_CORE_TxOctets_P2;
+	uint8_t dummy532[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P2;
+	uint8_t dummy533[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P2;
+	uint8_t dummy534[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P2;
+	uint8_t dummy535[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P2;
+	uint8_t dummy536[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P2;
+	uint8_t dummy537[28];
+	uint32_t SWITCH_CORE_TxCollisions_P2;
+	uint8_t dummy538[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P2;
+	uint8_t dummy539[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P2;
+	uint8_t dummy540[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P2;
+	uint8_t dummy541[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P2;
+	uint8_t dummy542[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P2;
+	uint8_t dummy543[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P2;
+	uint8_t dummy544[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P2;
+	uint8_t dummy545[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P2;
+	uint8_t dummy546[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P2;
+	uint8_t dummy547[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P2;
+	uint8_t dummy548[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P2;
+	uint8_t dummy549[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P2;
+	uint8_t dummy550[28];
+	uint32_t SWITCH_CORE_RxOctets_P2;
+	uint8_t dummy551[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P2;
+	uint8_t dummy552[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P2;
+	uint8_t dummy553[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P2;
+	uint8_t dummy554[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P2;
+	uint8_t dummy555[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P2;
+	uint8_t dummy556[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P2;
+	uint8_t dummy557[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P2;
+	uint8_t dummy558[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P2;
+	uint8_t dummy559[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P2;
+	uint8_t dummy560[28];
+	uint32_t SWITCH_CORE_RxJabbers_P2;
+	uint8_t dummy561[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P2;
+	uint8_t dummy562[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P2;
+	uint8_t dummy563[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P2;
+	uint8_t dummy564[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P2;
+	uint8_t dummy565[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P2;
+	uint8_t dummy566[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P2;
+	uint8_t dummy567[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P2;
+	uint8_t dummy568[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P2;
+	uint8_t dummy569[28];
+	uint32_t SWITCH_CORE_RxFragments_P2;
+	uint8_t dummy570[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P2;
+	uint8_t dummy571[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P2;
+	uint8_t dummy572[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P2;
+	uint8_t dummy573[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P2;
+	uint8_t dummy574[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P2;
+	uint8_t dummy575[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P2;
+	uint8_t dummy576[28];
+	uint32_t SWITCH_CORE_RxDiscard_P2;
+	uint8_t dummy577[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P2;
+	uint8_t dummy578[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P2;
+	uint8_t dummy579[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P2;
+	uint8_t dummy580[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P2;
+	uint8_t dummy581[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P2;
+	uint8_t dummy582[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P2;
+	uint8_t dummy583[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P2;
+	uint8_t dummy584[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P2;
+	uint8_t dummy585[220];
+	uint32_t SWITCH_CORE_TxOctets_P3;
+	uint8_t dummy586[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P3;
+	uint8_t dummy587[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P3;
+	uint8_t dummy588[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P3;
+	uint8_t dummy589[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P3;
+	uint8_t dummy590[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P3;
+	uint8_t dummy591[28];
+	uint32_t SWITCH_CORE_TxCollisions_P3;
+	uint8_t dummy592[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P3;
+	uint8_t dummy593[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P3;
+	uint8_t dummy594[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P3;
+	uint8_t dummy595[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P3;
+	uint8_t dummy596[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P3;
+	uint8_t dummy597[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P3;
+	uint8_t dummy598[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P3;
+	uint8_t dummy599[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P3;
+	uint8_t dummy600[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P3;
+	uint8_t dummy601[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P3;
+	uint8_t dummy602[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P3;
+	uint8_t dummy603[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P3;
+	uint8_t dummy604[28];
+	uint32_t SWITCH_CORE_RxOctets_P3;
+	uint8_t dummy605[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P3;
+	uint8_t dummy606[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P3;
+	uint8_t dummy607[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P3;
+	uint8_t dummy608[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P3;
+	uint8_t dummy609[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P3;
+	uint8_t dummy610[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P3;
+	uint8_t dummy611[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P3;
+	uint8_t dummy612[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P3;
+	uint8_t dummy613[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P3;
+	uint8_t dummy614[28];
+	uint32_t SWITCH_CORE_RxJabbers_P3;
+	uint8_t dummy615[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P3;
+	uint8_t dummy616[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P3;
+	uint8_t dummy617[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P3;
+	uint8_t dummy618[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P3;
+	uint8_t dummy619[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P3;
+	uint8_t dummy620[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P3;
+	uint8_t dummy621[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P3;
+	uint8_t dummy622[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P3;
+	uint8_t dummy623[28];
+	uint32_t SWITCH_CORE_RxFragments_P3;
+	uint8_t dummy624[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P3;
+	uint8_t dummy625[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P3;
+	uint8_t dummy626[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P3;
+	uint8_t dummy627[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P3;
+	uint8_t dummy628[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P3;
+	uint8_t dummy629[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P3;
+	uint8_t dummy630[28];
+	uint32_t SWITCH_CORE_RxDiscard_P3;
+	uint8_t dummy631[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P3;
+	uint8_t dummy632[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P3;
+	uint8_t dummy633[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P3;
+	uint8_t dummy634[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P3;
+	uint8_t dummy635[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P3;
+	uint8_t dummy636[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P3;
+	uint8_t dummy637[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P3;
+	uint8_t dummy638[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P3;
+	uint8_t dummy639[220];
+	uint32_t SWITCH_CORE_TxOctets_P4;
+	uint8_t dummy640[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P4;
+	uint8_t dummy641[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P4;
+	uint8_t dummy642[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P4;
+	uint8_t dummy643[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P4;
+	uint8_t dummy644[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P4;
+	uint8_t dummy645[28];
+	uint32_t SWITCH_CORE_TxCollisions_P4;
+	uint8_t dummy646[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P4;
+	uint8_t dummy647[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P4;
+	uint8_t dummy648[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P4;
+	uint8_t dummy649[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P4;
+	uint8_t dummy650[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P4;
+	uint8_t dummy651[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P4;
+	uint8_t dummy652[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P4;
+	uint8_t dummy653[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P4;
+	uint8_t dummy654[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P4;
+	uint8_t dummy655[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P4;
+	uint8_t dummy656[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P4;
+	uint8_t dummy657[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P4;
+	uint8_t dummy658[28];
+	uint32_t SWITCH_CORE_RxOctets_P4;
+	uint8_t dummy659[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P4;
+	uint8_t dummy660[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P4;
+	uint8_t dummy661[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P4;
+	uint8_t dummy662[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P4;
+	uint8_t dummy663[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P4;
+	uint8_t dummy664[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P4;
+	uint8_t dummy665[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P4;
+	uint8_t dummy666[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P4;
+	uint8_t dummy667[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P4;
+	uint8_t dummy668[28];
+	uint32_t SWITCH_CORE_RxJabbers_P4;
+	uint8_t dummy669[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P4;
+	uint8_t dummy670[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P4;
+	uint8_t dummy671[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P4;
+	uint8_t dummy672[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P4;
+	uint8_t dummy673[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P4;
+	uint8_t dummy674[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P4;
+	uint8_t dummy675[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P4;
+	uint8_t dummy676[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P4;
+	uint8_t dummy677[28];
+	uint32_t SWITCH_CORE_RxFragments_P4;
+	uint8_t dummy678[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P4;
+	uint8_t dummy679[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P4;
+	uint8_t dummy680[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P4;
+	uint8_t dummy681[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P4;
+	uint8_t dummy682[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P4;
+	uint8_t dummy683[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P4;
+	uint8_t dummy684[28];
+	uint32_t SWITCH_CORE_RxDiscard_P4;
+	uint8_t dummy685[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P4;
+	uint8_t dummy686[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P4;
+	uint8_t dummy687[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P4;
+	uint8_t dummy688[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P4;
+	uint8_t dummy689[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P4;
+	uint8_t dummy690[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P4;
+	uint8_t dummy691[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P4;
+	uint8_t dummy692[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P4;
+	uint8_t dummy693[220];
+	uint32_t SWITCH_CORE_TxOctets_P5;
+	uint8_t dummy694[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P5;
+	uint8_t dummy695[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P5;
+	uint8_t dummy696[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P5;
+	uint8_t dummy697[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P5;
+	uint8_t dummy698[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P5;
+	uint8_t dummy699[28];
+	uint32_t SWITCH_CORE_TxCollisions_P5;
+	uint8_t dummy700[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P5;
+	uint8_t dummy701[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P5;
+	uint8_t dummy702[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P5;
+	uint8_t dummy703[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P5;
+	uint8_t dummy704[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P5;
+	uint8_t dummy705[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P5;
+	uint8_t dummy706[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P5;
+	uint8_t dummy707[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P5;
+	uint8_t dummy708[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P5;
+	uint8_t dummy709[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P5;
+	uint8_t dummy710[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P5;
+	uint8_t dummy711[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P5;
+	uint8_t dummy712[28];
+	uint32_t SWITCH_CORE_RxOctets_P5;
+	uint8_t dummy713[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P5;
+	uint8_t dummy714[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P5;
+	uint8_t dummy715[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P5;
+	uint8_t dummy716[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P5;
+	uint8_t dummy717[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P5;
+	uint8_t dummy718[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P5;
+	uint8_t dummy719[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P5;
+	uint8_t dummy720[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P5;
+	uint8_t dummy721[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P5;
+	uint8_t dummy722[28];
+	uint32_t SWITCH_CORE_RxJabbers_P5;
+	uint8_t dummy723[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P5;
+	uint8_t dummy724[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P5;
+	uint8_t dummy725[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P5;
+	uint8_t dummy726[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P5;
+	uint8_t dummy727[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P5;
+	uint8_t dummy728[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P5;
+	uint8_t dummy729[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P5;
+	uint8_t dummy730[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P5;
+	uint8_t dummy731[28];
+	uint32_t SWITCH_CORE_RxFragments_P5;
+	uint8_t dummy732[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P5;
+	uint8_t dummy733[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P5;
+	uint8_t dummy734[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P5;
+	uint8_t dummy735[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P5;
+	uint8_t dummy736[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P5;
+	uint8_t dummy737[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P5;
+	uint8_t dummy738[28];
+	uint32_t SWITCH_CORE_RxDiscard_P5;
+	uint8_t dummy739[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P5;
+	uint8_t dummy740[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P5;
+	uint8_t dummy741[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P5;
+	uint8_t dummy742[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P5;
+	uint8_t dummy743[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P5;
+	uint8_t dummy744[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P5;
+	uint8_t dummy745[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P5;
+	uint8_t dummy746[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P5;
+	uint8_t dummy747[220];
+	uint32_t SWITCH_CORE_TxOctets_P6;
+	uint8_t dummy748[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P6;
+	uint8_t dummy749[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P6;
+	uint8_t dummy750[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P6;
+	uint8_t dummy751[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P6;
+	uint8_t dummy752[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P6;
+	uint8_t dummy753[28];
+	uint32_t SWITCH_CORE_TxCollisions_P6;
+	uint8_t dummy754[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P6;
+	uint8_t dummy755[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P6;
+	uint8_t dummy756[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P6;
+	uint8_t dummy757[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P6;
+	uint8_t dummy758[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P6;
+	uint8_t dummy759[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P6;
+	uint8_t dummy760[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P6;
+	uint8_t dummy761[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P6;
+	uint8_t dummy762[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P6;
+	uint8_t dummy763[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P6;
+	uint8_t dummy764[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P6;
+	uint8_t dummy765[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P6;
+	uint8_t dummy766[28];
+	uint32_t SWITCH_CORE_RxOctets_P6;
+	uint8_t dummy767[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P6;
+	uint8_t dummy768[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P6;
+	uint8_t dummy769[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P6;
+	uint8_t dummy770[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P6;
+	uint8_t dummy771[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P6;
+	uint8_t dummy772[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P6;
+	uint8_t dummy773[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P6;
+	uint8_t dummy774[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P6;
+	uint8_t dummy775[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P6;
+	uint8_t dummy776[28];
+	uint32_t SWITCH_CORE_RxJabbers_P6;
+	uint8_t dummy777[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P6;
+	uint8_t dummy778[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P6;
+	uint8_t dummy779[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P6;
+	uint8_t dummy780[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P6;
+	uint8_t dummy781[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P6;
+	uint8_t dummy782[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P6;
+	uint8_t dummy783[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P6;
+	uint8_t dummy784[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P6;
+	uint8_t dummy785[28];
+	uint32_t SWITCH_CORE_RxFragments_P6;
+	uint8_t dummy786[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P6;
+	uint8_t dummy787[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P6;
+	uint8_t dummy788[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P6;
+	uint8_t dummy789[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P6;
+	uint8_t dummy790[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P6;
+	uint8_t dummy791[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P6;
+	uint8_t dummy792[28];
+	uint32_t SWITCH_CORE_RxDiscard_P6;
+	uint8_t dummy793[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P6;
+	uint8_t dummy794[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P6;
+	uint8_t dummy795[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P6;
+	uint8_t dummy796[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P6;
+	uint8_t dummy797[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P6;
+	uint8_t dummy798[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P6;
+	uint8_t dummy799[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P6;
+	uint8_t dummy800[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P6;
+	uint8_t dummy801[220];
+	uint32_t SWITCH_CORE_TxOctets_P7;
+	uint8_t dummy802[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P7;
+	uint8_t dummy803[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P7;
+	uint8_t dummy804[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P7;
+	uint8_t dummy805[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P7;
+	uint8_t dummy806[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P7;
+	uint8_t dummy807[28];
+	uint32_t SWITCH_CORE_TxCollisions_P7;
+	uint8_t dummy808[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P7;
+	uint8_t dummy809[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P7;
+	uint8_t dummy810[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P7;
+	uint8_t dummy811[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P7;
+	uint8_t dummy812[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P7;
+	uint8_t dummy813[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P7;
+	uint8_t dummy814[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P7;
+	uint8_t dummy815[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P7;
+	uint8_t dummy816[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P7;
+	uint8_t dummy817[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P7;
+	uint8_t dummy818[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P7;
+	uint8_t dummy819[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P7;
+	uint8_t dummy820[28];
+	uint32_t SWITCH_CORE_RxOctets_P7;
+	uint8_t dummy821[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P7;
+	uint8_t dummy822[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P7;
+	uint8_t dummy823[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P7;
+	uint8_t dummy824[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P7;
+	uint8_t dummy825[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P7;
+	uint8_t dummy826[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P7;
+	uint8_t dummy827[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P7;
+	uint8_t dummy828[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P7;
+	uint8_t dummy829[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P7;
+	uint8_t dummy830[28];
+	uint32_t SWITCH_CORE_RxJabbers_P7;
+	uint8_t dummy831[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P7;
+	uint8_t dummy832[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P7;
+	uint8_t dummy833[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P7;
+	uint8_t dummy834[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P7;
+	uint8_t dummy835[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P7;
+	uint8_t dummy836[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P7;
+	uint8_t dummy837[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P7;
+	uint8_t dummy838[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P7;
+	uint8_t dummy839[28];
+	uint32_t SWITCH_CORE_RxFragments_P7;
+	uint8_t dummy840[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P7;
+	uint8_t dummy841[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P7;
+	uint8_t dummy842[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P7;
+	uint8_t dummy843[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P7;
+	uint8_t dummy844[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P7;
+	uint8_t dummy845[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P7;
+	uint8_t dummy846[28];
+	uint32_t SWITCH_CORE_RxDiscard_P7;
+	uint8_t dummy847[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P7;
+	uint8_t dummy848[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P7;
+	uint8_t dummy849[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P7;
+	uint8_t dummy850[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P7;
+	uint8_t dummy851[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P7;
+	uint8_t dummy852[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P7;
+	uint8_t dummy853[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P7;
+	uint8_t dummy854[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P7;
+	uint8_t dummy855[220];
+	uint32_t SWITCH_CORE_TxOctets_IMP;
+	uint8_t dummy856[60];
+	uint32_t SWITCH_CORE_TxDropPkts_IMP;
+	uint8_t dummy857[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_IMP;
+	uint8_t dummy858[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_IMP;
+	uint8_t dummy859[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_IMP;
+	uint8_t dummy860[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_IMP;
+	uint8_t dummy861[28];
+	uint32_t SWITCH_CORE_TxCollisions_IMP;
+	uint8_t dummy862[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_IMP;
+	uint8_t dummy863[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_IMP;
+	uint8_t dummy864[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_IMP;
+	uint8_t dummy865[28];
+	uint32_t SWITCH_CORE_TxLateCollision_IMP;
+	uint8_t dummy866[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_IMP;
+	uint8_t dummy867[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_IMP;
+	uint8_t dummy868[28];
+	uint32_t SWITCH_CORE_TxPausePkts_IMP;
+	uint8_t dummy869[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_IMP;
+	uint8_t dummy870[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_IMP;
+	uint8_t dummy871[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_IMP;
+	uint8_t dummy872[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_IMP;
+	uint8_t dummy873[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_IMP;
+	uint8_t dummy874[28];
+	uint32_t SWITCH_CORE_RxOctets_IMP;
+	uint8_t dummy875[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_IMP;
+	uint8_t dummy876[28];
+	uint32_t SWITCH_CORE_RxPausePkts_IMP;
+	uint8_t dummy877[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_IMP;
+	uint8_t dummy878[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_IMP;
+	uint8_t dummy879[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_IMP;
+	uint8_t dummy880[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_IMP;
+	uint8_t dummy881[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_IMP;
+	uint8_t dummy882[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP;
+	uint8_t dummy883[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_IMP;
+	uint8_t dummy884[28];
+	uint32_t SWITCH_CORE_RxJabbers_IMP;
+	uint8_t dummy885[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_IMP;
+	uint8_t dummy886[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_IMP;
+	uint8_t dummy887[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_IMP;
+	uint8_t dummy888[60];
+	uint32_t SWITCH_CORE_RxDropPkts_IMP;
+	uint8_t dummy889[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_IMP;
+	uint8_t dummy890[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_IMP;
+	uint8_t dummy891[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_IMP;
+	uint8_t dummy892[28];
+	uint32_t SWITCH_CORE_RxSAChanges_IMP;
+	uint8_t dummy893[28];
+	uint32_t SWITCH_CORE_RxFragments_IMP;
+	uint8_t dummy894[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_IMP;
+	uint8_t dummy895[28];
+	uint32_t SWITCH_CORE_RxSymblErr_IMP;
+	uint8_t dummy896[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_IMP;
+	uint8_t dummy897[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_IMP;
+	uint8_t dummy898[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_IMP;
+	uint8_t dummy899[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_IMP;
+	uint8_t dummy900[28];
+	uint32_t SWITCH_CORE_RxDiscard_IMP;
+	uint8_t dummy901[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_IMP;
+	uint8_t dummy902[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_IMP;
+	uint8_t dummy903[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_IMP;
+	uint8_t dummy904[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_IMP;
+	uint8_t dummy905[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_IMP;
+	uint8_t dummy906[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_IMP;
+	uint8_t dummy907[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_IMP;
+	uint8_t dummy908[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP;
+	uint8_t dummy909[14556];
+	uint32_t SWITCH_CORE_QOS_GLOBAL_CTRL;
+	uint8_t dummy910[28];
+	uint32_t SWITCH_CORE_QOS_1P_EN;
+	uint8_t dummy911[12];
+	uint32_t SWITCH_CORE_QOS_EN_DIFFSERV;
+	uint8_t dummy912[76];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P0;
+	uint8_t dummy913[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P1;
+	uint8_t dummy914[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P2;
+	uint8_t dummy915[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P3;
+	uint8_t dummy916[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P4;
+	uint8_t dummy917[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P5;
+	uint8_t dummy918[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P6;
+	uint8_t dummy919[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P7;
+	uint8_t dummy920[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_IMP;
+	uint8_t dummy921[28];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP0;
+	uint8_t dummy922[44];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP1;
+	uint8_t dummy923[44];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP2;
+	uint8_t dummy924[44];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP3;
+	uint8_t dummy925[44];
+	uint32_t SWITCH_CORE_PID2TC;
+	uint8_t dummy926[60];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P0;
+	uint8_t dummy927[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P1;
+	uint8_t dummy928[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P2;
+	uint8_t dummy929[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P3;
+	uint8_t dummy930[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P4;
+	uint8_t dummy931[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P5;
+	uint8_t dummy932[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P6;
+	uint8_t dummy933[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P7;
+	uint8_t dummy934[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_IMP;
+	uint8_t dummy935[28];
+	uint32_t SWITCH_CORE_CPU2COS_MAP;
+	uint8_t dummy936[60];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P0;
+	uint8_t dummy937[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P1;
+	uint8_t dummy938[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P2;
+	uint8_t dummy939[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P3;
+	uint8_t dummy940[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P4;
+	uint8_t dummy941[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P5;
+	uint8_t dummy942[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P6;
+	uint8_t dummy943[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P7;
+	uint8_t dummy944[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_IMP;
+	uint8_t dummy945[188];
+	uint32_t SWITCH_CORE_QOS_REG_SPARE0;
+	uint8_t dummy946[28];
+	uint32_t SWITCH_CORE_QOS_REG_SPARE1;
+	uint8_t dummy947[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P0;
+	uint8_t dummy948[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P1;
+	uint8_t dummy949[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P2;
+	uint8_t dummy950[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P3;
+	uint8_t dummy951[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P4;
+	uint8_t dummy952[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P5;
+	uint8_t dummy953[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P6;
+	uint8_t dummy954[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P7;
+	uint8_t dummy955[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_IMP;
+	uint8_t dummy956[380];
+	uint32_t port_vlan_ctrl[4*9];
+	uint8_t dummy965[112];
+	uint32_t SWITCH_CORE_VLAN_REG_SPARE0;
+	uint8_t dummy966[28];
+	uint32_t SWITCH_CORE_VLAN_REG_SPARE1;
+	uint8_t dummy967[1756];
+	uint32_t SWITCH_CORE_MAC_TRUNK_CTL;
+	uint8_t dummy968[12];
+	uint32_t SWITCH_CORE_IMP0_GRP_CTL;
+	uint8_t dummy969[108];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL0;
+	uint8_t dummy970[12];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL1;
+	uint8_t dummy971[12];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL2;
+	uint8_t dummy972[12];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL3;
+	uint8_t dummy973[76];
+	uint32_t SWITCH_CORE_TRUNK_HASH_OVRRD;
+	uint8_t dummy974[252];
+	uint32_t SWITCH_CORE_TRUNK_REG_SPARE0;
+	uint8_t dummy975[28];
+	uint32_t SWITCH_CORE_TRUNK_REG_SPARE1;
+	uint8_t dummy976[3548];
+	uint64_t SWITCH_CORE_VLAN_CTRL0;
+	uint64_t SWITCH_CORE_VLAN_CTRL1;
+	uint64_t SWITCH_CORE_VLAN_CTRL2;
+	uint32_t SWITCH_CORE_VLAN_CTRL3;
+	uint8_t dummy977[12];
+	uint64_t SWITCH_CORE_VLAN_CTRL4;
+	uint64_t SWITCH_CORE_VLAN_CTRL5;
+	uint32_t SWITCH_CORE_VLAN_CTRL6;
+	uint8_t dummy978[20];
+	uint32_t SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL;
+	uint8_t dummy979[44];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P0;
+	uint8_t dummy980[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P1;
+	uint8_t dummy981[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P2;
+	uint8_t dummy982[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P3;
+	uint8_t dummy983[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P4;
+	uint8_t dummy984[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P5;
+	uint8_t dummy985[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P6;
+	uint8_t dummy986[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P7;
+	uint8_t dummy987[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_IMP;
+	uint8_t dummy988[124];
+	uint32_t SWITCH_CORE_DTAG_TPID;
+	uint8_t dummy989[12];
+	uint32_t SWITCH_CORE_ISP_SEL_PORTMAP;
+	uint8_t dummy990[108];
+	uint32_t SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS;
+	uint8_t dummy991[28];
+	uint32_t SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA;
+	uint8_t dummy992[92];
+	uint32_t SWITCH_CORE_JOIN_ALL_VLAN_EN;
+	uint8_t dummy993[12];
+	uint32_t SWITCH_CORE_PORT_IVL_SVL_CTRL;
+	uint8_t dummy994[108];
+	uint32_t SWITCH_CORE_BCM8021Q_REG_SPARE0;
+	uint8_t dummy995[28];
+	uint32_t SWITCH_CORE_BCM8021Q_REG_SPARE1;
+	uint8_t dummy996[3292];
+	uint32_t SWITCH_CORE_DOS_CTRL;
+	uint8_t dummy997[28];
+	uint32_t SWITCH_CORE_MINIMUM_TCP_HDR_SZ;
+	uint8_t dummy998[28];
+	uint32_t SWITCH_CORE_MAX_ICMPV4_SIZE_REG;
+	uint8_t dummy999[28];
+	uint32_t SWITCH_CORE_MAX_ICMPV6_SIZE_REG;
+	uint8_t dummy1000[28];
+	uint32_t SWITCH_CORE_DOS_DIS_LRN_REG;
+	uint8_t dummy1001[124];
+	uint32_t SWITCH_CORE_DOS_REG_SPARE0;
+	uint8_t dummy1002[28];
+	uint32_t SWITCH_CORE_DOS_REG_SPARE1;
+	uint8_t dummy1003[20196];
+	uint32_t SWITCH_CORE_JUMBO_PORT_MASK;
+	uint8_t dummy1004[28];
+	uint32_t SWITCH_CORE_MIB_GD_FM_MAX_SIZE;
+	uint8_t dummy1005[84];
+	uint32_t SWITCH_CORE_JUMBO_CTRL_REG_SPARE0;
+	uint8_t dummy1006[28];
+	uint32_t SWITCH_CORE_JUMBO_CTRL_REG_SPARE1;
+	uint8_t dummy1007[1884];
+	uint32_t SWITCH_CORE_COMM_IRC_CON;
+	uint8_t dummy1008[28];
+	uint32_t SWITCH_CORE_IRC_VIRTUAL_ZERO_THD;
+	uint8_t dummy1009[12];
+	uint32_t SWITCH_CORE_IRC_ALARM_THD;
+	uint8_t dummy1010[76];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P0;
+	uint8_t dummy1011[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P1;
+	uint8_t dummy1012[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P2;
+	uint8_t dummy1013[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P3;
+	uint8_t dummy1014[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P4;
+	uint8_t dummy1015[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P5;
+	uint8_t dummy1016[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P6;
+	uint8_t dummy1017[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P7;
+	uint8_t dummy1018[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_IMP;
+	uint8_t dummy1019[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P0;
+	uint8_t dummy1020[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P1;
+	uint8_t dummy1021[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P2;
+	uint8_t dummy1022[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P3;
+	uint8_t dummy1023[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P4;
+	uint8_t dummy1024[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P5;
+	uint8_t dummy1025[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P6;
+	uint8_t dummy1026[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P7;
+	uint8_t dummy1027[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_IMP;
+	uint8_t dummy1028[92];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P0;
+	uint8_t dummy1029[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P1;
+	uint8_t dummy1030[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P2;
+	uint8_t dummy1031[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P3;
+	uint8_t dummy1032[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P4;
+	uint8_t dummy1033[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P5;
+	uint8_t dummy1034[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P6;
+	uint8_t dummy1035[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7;
+	uint8_t dummy1036[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP;
+	uint8_t dummy1037[764];
+	uint32_t SWITCH_CORE_BC_SUPPRESS_REG_SPARE0;
+	uint8_t dummy1038[28];
+	uint32_t SWITCH_CORE_BC_SUPPRESS_REG_SPARE1;
+	uint8_t dummy1039[348];
+	uint64_t SWITCH_CORE_EAP_GLO_CON;
+	uint64_t SWITCH_CORE_EAP_MULTI_ADDR_CTRL;
+	uint32_t SWITCH_CORE_EAP_DIP0;
+	uint8_t dummy1040[60];
+	uint32_t SWITCH_CORE_EAP_DIP1;
+	uint8_t dummy1041[172];
+	uint32_t SWITCH_CORE_EAP_CON_P0;
+	uint8_t dummy1042[60];
+	uint32_t SWITCH_CORE_EAP_CON_P1;
+	uint8_t dummy1043[60];
+	uint32_t SWITCH_CORE_EAP_CON_P2;
+	uint8_t dummy1044[60];
+	uint32_t SWITCH_CORE_EAP_CON_P3;
+	uint8_t dummy1045[60];
+	uint32_t SWITCH_CORE_EAP_CON_P4;
+	uint8_t dummy1046[60];
+	uint32_t SWITCH_CORE_EAP_CON_P5;
+	uint8_t dummy1047[60];
+	uint32_t SWITCH_CORE_EAP_CON_P6;
+	uint8_t dummy1048[60];
+	uint32_t SWITCH_CORE_EAP_CON_P7;
+	uint8_t dummy1049[60];
+	uint32_t SWITCH_CORE_EAP_CON_IMP;
+	uint8_t dummy1050[124];
+	uint32_t SWITCH_CORE_IEEE8021X_REG_SPARE0;
+	uint8_t dummy1051[28];
+	uint32_t SWITCH_CORE_IEEE8021X_REG_SPARE1;
+	uint8_t dummy1052[1116];
+	uint32_t SWITCH_CORE_MST_CON;
+	uint8_t dummy1053[12];
+	uint32_t SWITCH_CORE_MST_AGE;
+	uint8_t dummy1054[108];
+	uint32_t SWITCH_CORE_MST_TAB0;
+	uint8_t dummy1055[28];
+	uint32_t SWITCH_CORE_MST_TAB1;
+	uint8_t dummy1056[28];
+	uint32_t SWITCH_CORE_MST_TAB2;
+	uint8_t dummy1057[28];
+	uint32_t SWITCH_CORE_MST_TAB3;
+	uint8_t dummy1058[28];
+	uint32_t SWITCH_CORE_MST_TAB4;
+	uint8_t dummy1059[28];
+	uint32_t SWITCH_CORE_MST_TAB5;
+	uint8_t dummy1060[28];
+	uint32_t SWITCH_CORE_MST_TAB6;
+	uint8_t dummy1061[28];
+	uint32_t SWITCH_CORE_MST_TAB7;
+	uint8_t dummy1062[284];
+	uint32_t SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL;
+	uint8_t dummy1063[124];
+	uint32_t SWITCH_CORE_IEEE8021S_REG_SPARE0;
+	uint8_t dummy1064[28];
+	uint32_t SWITCH_CORE_IEEE8021S_REG_SPARE1;
+	uint8_t dummy1065[3292];
+	uint32_t SWITCH_CORE_SA_LIMIT_ENABLE;
+	uint8_t dummy1066[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_RST;
+	uint8_t dummy1067[12];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_RST;
+	uint8_t dummy1068[92];
+	uint32_t SWITCH_CORE_TOTAL_SA_LIMIT_CTL;
+	uint8_t dummy1069[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P0;
+	uint8_t dummy1070[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P1;
+	uint8_t dummy1071[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P2;
+	uint8_t dummy1072[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P3;
+	uint8_t dummy1073[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P4;
+	uint8_t dummy1074[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P5;
+	uint8_t dummy1075[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P6;
+	uint8_t dummy1076[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P7;
+	uint8_t dummy1077[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P8;
+	uint8_t dummy1078[108];
+	uint32_t SWITCH_CORE_TOTAL_SA_LRN_CNTR;
+	uint8_t dummy1079[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P0;
+	uint8_t dummy1080[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P1;
+	uint8_t dummy1081[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P2;
+	uint8_t dummy1082[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P3;
+	uint8_t dummy1083[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P4;
+	uint8_t dummy1084[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P5;
+	uint8_t dummy1085[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P6;
+	uint8_t dummy1086[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P7;
+	uint8_t dummy1087[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P8;
+	uint8_t dummy1088[108];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P0;
+	uint8_t dummy1089[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P1;
+	uint8_t dummy1090[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P2;
+	uint8_t dummy1091[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P3;
+	uint8_t dummy1092[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P4;
+	uint8_t dummy1093[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P5;
+	uint8_t dummy1094[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P6;
+	uint8_t dummy1095[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P7;
+	uint8_t dummy1096[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P8;
+	uint8_t dummy1097[28];
+	uint32_t SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT;
+	uint8_t dummy1098[92];
+	uint32_t SWITCH_CORE_MAC_LIMIT_REG_SPARE0;
+	uint8_t dummy1099[28];
+	uint32_t SWITCH_CORE_MAC_LIMIT_REG_SPARE1;
+	uint8_t dummy1100[988];
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P0;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P1;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P2;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P3;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P4;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P5;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P6;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P7;
+	uint32_t SWITCH_CORE_QOS_PRI_CTL_IMP;
+	uint8_t dummy1101[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P0;
+	uint8_t dummy1102[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P1;
+	uint8_t dummy1103[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P2;
+	uint8_t dummy1104[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P3;
+	uint8_t dummy1105[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P4;
+	uint8_t dummy1106[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P5;
+	uint8_t dummy1107[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P6;
+	uint8_t dummy1108[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P7;
+	uint8_t dummy1109[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_IMP;
+	uint8_t dummy1110[124];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P0;
+	uint8_t dummy1111[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P1;
+	uint8_t dummy1112[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P2;
+	uint8_t dummy1113[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P3;
+	uint8_t dummy1114[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P4;
+	uint8_t dummy1115[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P5;
+	uint8_t dummy1116[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P6;
+	uint8_t dummy1117[28];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P7;
+	uint8_t dummy1118[12];
+	uint32_t SWITCH_CORE_P8_WDRR_PENALTY;
+	uint8_t dummy1119[108];
+	uint32_t SWITCH_CORE_SCHEDULER_REG_SPARE0;
+	uint8_t dummy1120[28];
+	uint32_t SWITCH_CORE_SCHEDULER_REG_SPARE1;
+	uint8_t dummy1121[988];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0;
+	uint8_t dummy1122[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1;
+	uint8_t dummy1123[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2;
+	uint8_t dummy1124[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3;
+	uint8_t dummy1125[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4;
+	uint8_t dummy1126[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5;
+	uint8_t dummy1127[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P6;
+	uint8_t dummy1128[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7;
+	uint8_t dummy1129[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP;
+	uint8_t dummy1130[124];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0;
+	uint8_t dummy1131[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1;
+	uint8_t dummy1132[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2;
+	uint8_t dummy1133[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3;
+	uint8_t dummy1134[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4;
+	uint8_t dummy1135[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5;
+	uint8_t dummy1136[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P6;
+	uint8_t dummy1137[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7;
+	uint8_t dummy1138[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP;
+	uint8_t dummy1139[124];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P0;
+	uint8_t dummy1140[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P1;
+	uint8_t dummy1141[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P2;
+	uint8_t dummy1142[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P3;
+	uint8_t dummy1143[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P4;
+	uint8_t dummy1144[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P5;
+	uint8_t dummy1145[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P6;
+	uint8_t dummy1146[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P7;
+	uint8_t dummy1147[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_IMP;
+	uint8_t dummy1148[124];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0;
+	uint8_t dummy1149[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1;
+	uint8_t dummy1150[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2;
+	uint8_t dummy1151[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3;
+	uint8_t dummy1152[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4;
+	uint8_t dummy1153[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5;
+	uint8_t dummy1154[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P6;
+	uint8_t dummy1155[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7;
+	uint8_t dummy1156[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP;
+	uint8_t dummy1157[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0;
+	uint8_t dummy1158[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1;
+	uint8_t dummy1159[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0;
+	uint8_t dummy1160[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1;
+	uint8_t dummy1161[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2;
+	uint8_t dummy1162[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3;
+	uint8_t dummy1163[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4;
+	uint8_t dummy1164[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5;
+	uint8_t dummy1165[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P6;
+	uint8_t dummy1166[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7;
+	uint8_t dummy1167[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP;
+	uint8_t dummy1168[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE;
+	uint8_t dummy1169[12];
+	uint32_t SWITCH_CORE_PORT_SHAPER_ENABLE;
+	uint8_t dummy1170[12];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1171[12];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BLOCKING;
+	uint8_t dummy1172[28];
+	uint32_t SWITCH_CORE_IFG_BYTES;
+	uint8_t dummy1173[140];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P0;
+	uint8_t dummy1174[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P1;
+	uint8_t dummy1175[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P2;
+	uint8_t dummy1176[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P3;
+	uint8_t dummy1177[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P4;
+	uint8_t dummy1178[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P5;
+	uint8_t dummy1179[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P6;
+	uint8_t dummy1180[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P7;
+	uint8_t dummy1181[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP;
+	uint8_t dummy1182[124];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0;
+	uint8_t dummy1183[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1;
+	uint8_t dummy1184[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2;
+	uint8_t dummy1185[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3;
+	uint8_t dummy1186[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4;
+	uint8_t dummy1187[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5;
+	uint8_t dummy1188[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P6;
+	uint8_t dummy1189[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7;
+	uint8_t dummy1190[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP;
+	uint8_t dummy1191[124];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P0;
+	uint8_t dummy1192[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P1;
+	uint8_t dummy1193[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P2;
+	uint8_t dummy1194[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P3;
+	uint8_t dummy1195[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P4;
+	uint8_t dummy1196[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P5;
+	uint8_t dummy1197[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P6;
+	uint8_t dummy1198[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P7;
+	uint8_t dummy1199[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_IMP;
+	uint8_t dummy1200[124];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1201[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1202[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1203[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1204[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1205[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1206[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1207[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1208[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1209[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0;
+	uint8_t dummy1210[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1;
+	uint8_t dummy1211[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1212[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1213[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1214[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1215[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1216[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1217[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1218[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1219[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1220[28];
+	uint32_t SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE;
+	uint8_t dummy1221[12];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_ENABLE;
+	uint8_t dummy1222[12];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1223[12];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_BLOCKING;
+	uint8_t dummy1224[172];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P0;
+	uint8_t dummy1225[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P1;
+	uint8_t dummy1226[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P2;
+	uint8_t dummy1227[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P3;
+	uint8_t dummy1228[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P4;
+	uint8_t dummy1229[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P5;
+	uint8_t dummy1230[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P6;
+	uint8_t dummy1231[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P7;
+	uint8_t dummy1232[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP;
+	uint8_t dummy1233[124];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0;
+	uint8_t dummy1234[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1;
+	uint8_t dummy1235[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2;
+	uint8_t dummy1236[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3;
+	uint8_t dummy1237[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4;
+	uint8_t dummy1238[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5;
+	uint8_t dummy1239[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P6;
+	uint8_t dummy1240[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7;
+	uint8_t dummy1241[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP;
+	uint8_t dummy1242[124];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P0;
+	uint8_t dummy1243[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P1;
+	uint8_t dummy1244[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P2;
+	uint8_t dummy1245[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P3;
+	uint8_t dummy1246[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P4;
+	uint8_t dummy1247[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P5;
+	uint8_t dummy1248[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P6;
+	uint8_t dummy1249[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P7;
+	uint8_t dummy1250[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_IMP;
+	uint8_t dummy1251[124];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1252[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1253[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1254[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1255[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1256[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1257[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1258[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1259[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1260[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0;
+	uint8_t dummy1261[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1;
+	uint8_t dummy1262[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1263[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1264[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1265[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1266[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1267[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1268[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1269[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1270[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1271[28];
+	uint32_t SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE;
+	uint8_t dummy1272[12];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_ENABLE;
+	uint8_t dummy1273[12];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1274[12];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_BLOCKING;
+	uint8_t dummy1275[172];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P0;
+	uint8_t dummy1276[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P1;
+	uint8_t dummy1277[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P2;
+	uint8_t dummy1278[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P3;
+	uint8_t dummy1279[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P4;
+	uint8_t dummy1280[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P5;
+	uint8_t dummy1281[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P6;
+	uint8_t dummy1282[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P7;
+	uint8_t dummy1283[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP;
+	uint8_t dummy1284[124];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0;
+	uint8_t dummy1285[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1;
+	uint8_t dummy1286[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2;
+	uint8_t dummy1287[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3;
+	uint8_t dummy1288[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4;
+	uint8_t dummy1289[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5;
+	uint8_t dummy1290[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P6;
+	uint8_t dummy1291[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7;
+	uint8_t dummy1292[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP;
+	uint8_t dummy1293[124];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P0;
+	uint8_t dummy1294[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P1;
+	uint8_t dummy1295[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P2;
+	uint8_t dummy1296[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P3;
+	uint8_t dummy1297[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P4;
+	uint8_t dummy1298[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P5;
+	uint8_t dummy1299[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P6;
+	uint8_t dummy1300[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P7;
+	uint8_t dummy1301[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_IMP;
+	uint8_t dummy1302[124];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1303[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1304[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1305[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1306[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1307[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1308[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1309[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1310[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1311[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0;
+	uint8_t dummy1312[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1;
+	uint8_t dummy1313[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1314[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1315[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1316[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1317[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1318[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1319[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1320[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1321[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1322[28];
+	uint32_t SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE;
+	uint8_t dummy1323[12];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_ENABLE;
+	uint8_t dummy1324[12];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1325[12];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_BLOCKING;
+	uint8_t dummy1326[172];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P0;
+	uint8_t dummy1327[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P1;
+	uint8_t dummy1328[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P2;
+	uint8_t dummy1329[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P3;
+	uint8_t dummy1330[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P4;
+	uint8_t dummy1331[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P5;
+	uint8_t dummy1332[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P6;
+	uint8_t dummy1333[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P7;
+	uint8_t dummy1334[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP;
+	uint8_t dummy1335[124];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0;
+	uint8_t dummy1336[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1;
+	uint8_t dummy1337[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2;
+	uint8_t dummy1338[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3;
+	uint8_t dummy1339[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4;
+	uint8_t dummy1340[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5;
+	uint8_t dummy1341[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P6;
+	uint8_t dummy1342[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7;
+	uint8_t dummy1343[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP;
+	uint8_t dummy1344[124];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P0;
+	uint8_t dummy1345[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P1;
+	uint8_t dummy1346[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P2;
+	uint8_t dummy1347[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P3;
+	uint8_t dummy1348[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P4;
+	uint8_t dummy1349[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P5;
+	uint8_t dummy1350[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P6;
+	uint8_t dummy1351[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P7;
+	uint8_t dummy1352[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_IMP;
+	uint8_t dummy1353[124];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1354[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1355[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1356[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1357[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1358[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1359[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1360[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1361[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1362[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0;
+	uint8_t dummy1363[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1;
+	uint8_t dummy1364[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1365[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1366[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1367[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1368[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1369[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1370[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1371[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1372[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1373[28];
+	uint32_t SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE;
+	uint8_t dummy1374[12];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_ENABLE;
+	uint8_t dummy1375[12];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1376[12];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_BLOCKING;
+	uint8_t dummy1377[172];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P0;
+	uint8_t dummy1378[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P1;
+	uint8_t dummy1379[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P2;
+	uint8_t dummy1380[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P3;
+	uint8_t dummy1381[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P4;
+	uint8_t dummy1382[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P5;
+	uint8_t dummy1383[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P6;
+	uint8_t dummy1384[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P7;
+	uint8_t dummy1385[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP;
+	uint8_t dummy1386[124];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0;
+	uint8_t dummy1387[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1;
+	uint8_t dummy1388[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2;
+	uint8_t dummy1389[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3;
+	uint8_t dummy1390[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4;
+	uint8_t dummy1391[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5;
+	uint8_t dummy1392[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P6;
+	uint8_t dummy1393[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7;
+	uint8_t dummy1394[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP;
+	uint8_t dummy1395[124];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P0;
+	uint8_t dummy1396[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P1;
+	uint8_t dummy1397[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P2;
+	uint8_t dummy1398[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P3;
+	uint8_t dummy1399[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P4;
+	uint8_t dummy1400[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P5;
+	uint8_t dummy1401[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P6;
+	uint8_t dummy1402[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P7;
+	uint8_t dummy1403[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_IMP;
+	uint8_t dummy1404[124];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1405[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1406[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1407[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1408[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1409[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1410[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1411[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1412[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1413[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0;
+	uint8_t dummy1414[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1;
+	uint8_t dummy1415[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1416[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1417[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1418[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1419[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1420[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1421[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1422[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1423[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1424[28];
+	uint32_t SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE;
+	uint8_t dummy1425[12];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_ENABLE;
+	uint8_t dummy1426[12];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1427[12];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_BLOCKING;
+	uint8_t dummy1428[172];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P0;
+	uint8_t dummy1429[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P1;
+	uint8_t dummy1430[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P2;
+	uint8_t dummy1431[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P3;
+	uint8_t dummy1432[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P4;
+	uint8_t dummy1433[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P5;
+	uint8_t dummy1434[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P6;
+	uint8_t dummy1435[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P7;
+	uint8_t dummy1436[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP;
+	uint8_t dummy1437[124];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0;
+	uint8_t dummy1438[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1;
+	uint8_t dummy1439[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2;
+	uint8_t dummy1440[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3;
+	uint8_t dummy1441[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4;
+	uint8_t dummy1442[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5;
+	uint8_t dummy1443[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P6;
+	uint8_t dummy1444[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7;
+	uint8_t dummy1445[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP;
+	uint8_t dummy1446[124];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P0;
+	uint8_t dummy1447[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P1;
+	uint8_t dummy1448[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P2;
+	uint8_t dummy1449[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P3;
+	uint8_t dummy1450[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P4;
+	uint8_t dummy1451[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P5;
+	uint8_t dummy1452[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P6;
+	uint8_t dummy1453[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P7;
+	uint8_t dummy1454[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_IMP;
+	uint8_t dummy1455[124];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1456[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1457[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1458[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1459[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1460[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1461[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1462[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1463[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1464[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0;
+	uint8_t dummy1465[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1;
+	uint8_t dummy1466[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1467[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1468[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1469[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1470[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1471[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1472[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1473[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1474[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1475[28];
+	uint32_t SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE;
+	uint8_t dummy1476[12];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_ENABLE;
+	uint8_t dummy1477[12];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1478[12];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_BLOCKING;
+	uint8_t dummy1479[172];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P0;
+	uint8_t dummy1480[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P1;
+	uint8_t dummy1481[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P2;
+	uint8_t dummy1482[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P3;
+	uint8_t dummy1483[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P4;
+	uint8_t dummy1484[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P5;
+	uint8_t dummy1485[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P6;
+	uint8_t dummy1486[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P7;
+	uint8_t dummy1487[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP;
+	uint8_t dummy1488[124];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0;
+	uint8_t dummy1489[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1;
+	uint8_t dummy1490[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2;
+	uint8_t dummy1491[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3;
+	uint8_t dummy1492[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4;
+	uint8_t dummy1493[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5;
+	uint8_t dummy1494[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P6;
+	uint8_t dummy1495[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7;
+	uint8_t dummy1496[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP;
+	uint8_t dummy1497[124];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P0;
+	uint8_t dummy1498[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P1;
+	uint8_t dummy1499[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P2;
+	uint8_t dummy1500[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P3;
+	uint8_t dummy1501[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P4;
+	uint8_t dummy1502[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P5;
+	uint8_t dummy1503[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P6;
+	uint8_t dummy1504[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P7;
+	uint8_t dummy1505[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_IMP;
+	uint8_t dummy1506[124];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1507[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1508[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1509[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1510[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1511[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1512[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1513[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1514[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1515[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0;
+	uint8_t dummy1516[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1;
+	uint8_t dummy1517[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1518[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1519[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1520[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1521[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1522[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1523[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1524[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1525[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1526[28];
+	uint32_t SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE;
+	uint8_t dummy1527[12];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_ENABLE;
+	uint8_t dummy1528[12];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1529[12];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_BLOCKING;
+	uint8_t dummy1530[172];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P0;
+	uint8_t dummy1531[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P1;
+	uint8_t dummy1532[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P2;
+	uint8_t dummy1533[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P3;
+	uint8_t dummy1534[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P4;
+	uint8_t dummy1535[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P5;
+	uint8_t dummy1536[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P6;
+	uint8_t dummy1537[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P7;
+	uint8_t dummy1538[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP;
+	uint8_t dummy1539[124];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0;
+	uint8_t dummy1540[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1;
+	uint8_t dummy1541[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2;
+	uint8_t dummy1542[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3;
+	uint8_t dummy1543[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4;
+	uint8_t dummy1544[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5;
+	uint8_t dummy1545[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P6;
+	uint8_t dummy1546[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7;
+	uint8_t dummy1547[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP;
+	uint8_t dummy1548[124];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P0;
+	uint8_t dummy1549[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P1;
+	uint8_t dummy1550[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P2;
+	uint8_t dummy1551[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P3;
+	uint8_t dummy1552[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P4;
+	uint8_t dummy1553[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P5;
+	uint8_t dummy1554[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P6;
+	uint8_t dummy1555[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P7;
+	uint8_t dummy1556[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_IMP;
+	uint8_t dummy1557[124];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1558[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1559[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1560[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1561[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1562[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1563[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1564[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1565[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1566[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0;
+	uint8_t dummy1567[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1;
+	uint8_t dummy1568[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1569[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1570[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1571[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1572[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1573[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1574[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1575[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1576[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1577[28];
+	uint32_t SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE;
+	uint8_t dummy1578[12];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_ENABLE;
+	uint8_t dummy1579[12];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1580[12];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_BLOCKING;
+	uint8_t dummy1581[65708];
+	uint32_t SWITCH_CORE_MIB_SNAPSHOT_CTL;
+	uint8_t dummy1582[2044];
+	uint32_t SWITCH_CORE_S_TxOctets;
+	uint8_t dummy1583[60];
+	uint32_t SWITCH_CORE_S_TxDropPkts;
+	uint8_t dummy1584[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ0;
+	uint8_t dummy1585[28];
+	uint32_t SWITCH_CORE_S_TxBroadcastPkts;
+	uint8_t dummy1586[28];
+	uint32_t SWITCH_CORE_S_TxMulticastPkts;
+	uint8_t dummy1587[28];
+	uint32_t SWITCH_CORE_S_TxUnicastPkts;
+	uint8_t dummy1588[28];
+	uint32_t SWITCH_CORE_S_TxCollisions;
+	uint8_t dummy1589[28];
+	uint32_t SWITCH_CORE_S_TxSingleCollision;
+	uint8_t dummy1590[28];
+	uint32_t SWITCH_CORE_S_TxMultipleCollision;
+	uint8_t dummy1591[28];
+	uint32_t SWITCH_CORE_S_TxDeferredTransmit;
+	uint8_t dummy1592[28];
+	uint32_t SWITCH_CORE_S_TxLateCollision;
+	uint8_t dummy1593[28];
+	uint32_t SWITCH_CORE_S_TxExcessiveCollision;
+	uint8_t dummy1594[28];
+	uint32_t SWITCH_CORE_S_TxFrameInDisc;
+	uint8_t dummy1595[28];
+	uint32_t SWITCH_CORE_S_TxPausePkts;
+	uint8_t dummy1596[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ1;
+	uint8_t dummy1597[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ2;
+	uint8_t dummy1598[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ3;
+	uint8_t dummy1599[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ4;
+	uint8_t dummy1600[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ5;
+	uint8_t dummy1601[28];
+	uint32_t SWITCH_CORE_S_RxOctets;
+	uint8_t dummy1602[60];
+	uint32_t SWITCH_CORE_S_RxUndersizePkts;
+	uint8_t dummy1603[28];
+	uint32_t SWITCH_CORE_S_RxPausePkts;
+	uint8_t dummy1604[28];
+	uint32_t SWITCH_CORE_S_RxPkts64Octets;
+	uint8_t dummy1605[28];
+	uint32_t SWITCH_CORE_S_RxPkts65to127Octets;
+	uint8_t dummy1606[28];
+	uint32_t SWITCH_CORE_S_RxPkts128to255Octets;
+	uint8_t dummy1607[28];
+	uint32_t SWITCH_CORE_S_RxPkts256to511Octets;
+	uint8_t dummy1608[28];
+	uint32_t SWITCH_CORE_S_RxPkts512to1023Octets;
+	uint8_t dummy1609[28];
+	uint32_t SWITCH_CORE_S_RxPkts1024toMaxPktOctets;
+	uint8_t dummy1610[28];
+	uint32_t SWITCH_CORE_S_RxOversizePkts;
+	uint8_t dummy1611[28];
+	uint32_t SWITCH_CORE_S_RxJabbers;
+	uint8_t dummy1612[28];
+	uint32_t SWITCH_CORE_S_RxAlignmentErrors;
+	uint8_t dummy1613[28];
+	uint32_t SWITCH_CORE_S_RxFCSErrors;
+	uint8_t dummy1614[28];
+	uint32_t SWITCH_CORE_S_RxGoodOctets;
+	uint8_t dummy1615[60];
+	uint32_t SWITCH_CORE_S_RxDropPkts;
+	uint8_t dummy1616[28];
+	uint32_t SWITCH_CORE_S_RxUnicastPkts;
+	uint8_t dummy1617[28];
+	uint32_t SWITCH_CORE_S_RxMulticastPkts;
+	uint8_t dummy1618[28];
+	uint32_t SWITCH_CORE_S_RxBroadcastPkts;
+	uint8_t dummy1619[28];
+	uint32_t SWITCH_CORE_S_RxSAChanges;
+	uint8_t dummy1620[28];
+	uint32_t SWITCH_CORE_S_RxFragments;
+	uint8_t dummy1621[28];
+	uint32_t SWITCH_CORE_S_RxJumboPkt;
+	uint8_t dummy1622[28];
+	uint32_t SWITCH_CORE_S_RxSymblErr;
+	uint8_t dummy1623[28];
+	uint32_t SWITCH_CORE_S_InRangeErrCount;
+	uint8_t dummy1624[28];
+	uint32_t SWITCH_CORE_S_OutRangeErrCount;
+	uint8_t dummy1625[28];
+	uint32_t SWITCH_CORE_S_EEE_LPI_EVENT;
+	uint8_t dummy1626[28];
+	uint32_t SWITCH_CORE_S_EEE_LPI_DURATION;
+	uint8_t dummy1627[28];
+	uint32_t SWITCH_CORE_S_RxDiscard;
+	uint8_t dummy1628[60];
+	uint32_t SWITCH_CORE_S_TxQPKTQ6;
+	uint8_t dummy1629[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ7;
+	uint8_t dummy1630[28];
+	uint32_t SWITCH_CORE_S_TxPkts64Octets;
+	uint8_t dummy1631[28];
+	uint32_t SWITCH_CORE_S_TxPkts65to127Octets;
+	uint8_t dummy1632[28];
+	uint32_t SWITCH_CORE_S_TxPkts128to255Octets;
+	uint8_t dummy1633[28];
+	uint32_t SWITCH_CORE_S_TxPkts256to511Octets;
+	uint8_t dummy1634[28];
+	uint32_t SWITCH_CORE_S_TxPkts512to1023Octets;
+	uint8_t dummy1635[28];
+	uint32_t SWITCH_CORE_S_TxPkts1024toMaxPktOctets;
+	uint8_t dummy1636[220];
+	uint32_t SWITCH_CORE_LPDET_CFG;
+	uint8_t dummy1637[12];
+	uint64_t SWITCH_CORE_DF_TIMER;
+	uint32_t SWITCH_CORE_LED_PORTMAP;
+	uint8_t dummy1638[12];
+	uint32_t SWITCH_CORE_MODULE_ID0;
+	uint8_t dummy1639[44];
+	uint32_t SWITCH_CORE_MODULE_ID1;
+	uint8_t dummy1640[44];
+	uint32_t SWITCH_CORE_LPDET_SA;
+	uint8_t dummy1641[116];
+	uint32_t SWITCH_CORE_LPDET_REG_SPARE0;
+	uint8_t dummy1642[28];
+	uint32_t SWITCH_CORE_LPDET_REG_SPARE1;
+	uint8_t dummy1643[1756];
+	uint64_t SWITCH_CORE_BPM_CTRL;
+	uint64_t SWITCH_CORE_BPM_PSM_OVR_CTRL;
+	uint32_t SWITCH_CORE_BPM_PSM_TIME_CFG;
+	uint8_t dummy1644[12];
+	uint32_t SWITCH_CORE_BPM_PSM_THD_CFG;
+	uint8_t dummy1645[28];
+	uint32_t SWITCH_CORE_ROW_VMASK_OVR_CTRL;
+	uint8_t dummy1646[28];
+	uint32_t SWITCH_CORE_BPM_STS;
+	uint8_t dummy1647[28];
+	uint32_t SWITCH_CORE_BPM_PDA_OVR_CTRL;
+	uint8_t dummy1648[12];
+	uint32_t SWITCH_CORE_PDA_TIMEOUT_CFG;
+	uint8_t dummy1649[12];
+	uint32_t SWITCH_CORE_PDA_SETUP_TIME_CFG;
+	uint8_t dummy1650[12];
+	uint32_t SWITCH_CORE_PDA_HOLD_TIME_CFG;
+	uint8_t dummy1651[12];
+	uint32_t SWITCH_CORE_PBB_VBUFCNT_P0;
+	uint8_t dummy1652[12];
+	uint32_t SWITCH_CORE_PBB_VBUFCNT_P1;
+	uint8_t dummy1653[12];
+	uint32_t SWITCH_CORE_PBB_VBUFCNT_P2;
+	uint8_t dummy1654[12];
+	uint32_t SWITCH_CORE_RCY_TIME_CFG;
+	uint8_t dummy1655[12];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON_CTRL;
+	uint8_t dummy1656[60];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON0;
+	uint8_t dummy1657[60];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON1;
+	uint8_t dummy1658[60];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON2;
+	uint8_t dummy1659[316];
+	uint32_t SWITCH_CORE_BPM_REG_SPARE0;
+	uint8_t dummy1660[28];
+	uint32_t SWITCH_CORE_BPM_REG_SPARE1;
+	uint8_t dummy1661[60636];
+	uint32_t SWITCH_CORE_TRREG_CTRL0;
+	uint8_t dummy1662[28];
+	uint32_t SWITCH_CORE_TRREG_CTRL1;
+	uint8_t dummy1663[28];
+	uint32_t SWITCH_CORE_TRREG_CTRL2;
+	uint8_t dummy1664[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0;
+	uint8_t dummy1665[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1;
+	uint8_t dummy1666[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2;
+	uint8_t dummy1667[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3;
+	uint8_t dummy1668[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4;
+	uint8_t dummy1669[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5;
+	uint8_t dummy1670[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P6;
+	uint8_t dummy1671[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7;
+	uint8_t dummy1672[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP;
+	uint8_t dummy1673[124];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0;
+	uint8_t dummy1674[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1;
+	uint8_t dummy1675[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2;
+	uint8_t dummy1676[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3;
+	uint8_t dummy1677[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4;
+	uint8_t dummy1678[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5;
+	uint8_t dummy1679[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P6;
+	uint8_t dummy1680[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7;
+	uint8_t dummy1681[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP;
+	uint8_t dummy1682[124];
+	uint32_t SWITCH_CORE_TRREG_REG_SPARE0;
+	uint8_t dummy1683[28];
+	uint32_t SWITCH_CORE_TRREG_REG_SPARE1;
+	uint8_t dummy1684[604];
+	uint32_t SWITCH_CORE_EEE_EN_CTRL;
+	uint8_t dummy1685[12];
+	uint32_t SWITCH_CORE_EEE_LPI_ASSERT;
+	uint8_t dummy1686[12];
+	uint32_t SWITCH_CORE_EEE_LPI_INDICATE;
+	uint8_t dummy1687[12];
+	uint32_t SWITCH_CORE_EEE_RX_IDLE_SYMBOL;
+	uint8_t dummy1688[12];
+	uint32_t SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE;
+	uint8_t dummy1689[28];
+	uint32_t SWITCH_CORE_EEE_PIPELINE_TIMER;
+	uint8_t dummy1690[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P0;
+	uint8_t dummy1691[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P1;
+	uint8_t dummy1692[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P2;
+	uint8_t dummy1693[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P3;
+	uint8_t dummy1694[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P4;
+	uint8_t dummy1695[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P5;
+	uint8_t dummy1696[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P6;
+	uint8_t dummy1697[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P7;
+	uint8_t dummy1698[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP;
+	uint8_t dummy1699[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P0;
+	uint8_t dummy1700[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P1;
+	uint8_t dummy1701[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P2;
+	uint8_t dummy1702[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P3;
+	uint8_t dummy1703[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P4;
+	uint8_t dummy1704[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P5;
+	uint8_t dummy1705[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P6;
+	uint8_t dummy1706[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P7;
+	uint8_t dummy1707[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP;
+	uint8_t dummy1708[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P0;
+	uint8_t dummy1709[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P1;
+	uint8_t dummy1710[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P2;
+	uint8_t dummy1711[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P3;
+	uint8_t dummy1712[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P4;
+	uint8_t dummy1713[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P5;
+	uint8_t dummy1714[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P6;
+	uint8_t dummy1715[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7;
+	uint8_t dummy1716[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP;
+	uint8_t dummy1717[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P0;
+	uint8_t dummy1718[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P1;
+	uint8_t dummy1719[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P2;
+	uint8_t dummy1720[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P3;
+	uint8_t dummy1721[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P4;
+	uint8_t dummy1722[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P5;
+	uint8_t dummy1723[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P6;
+	uint8_t dummy1724[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7;
+	uint8_t dummy1725[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP;
+	uint8_t dummy1726[28];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P0;
+	uint8_t dummy1727[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P1;
+	uint8_t dummy1728[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P2;
+	uint8_t dummy1729[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P3;
+	uint8_t dummy1730[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P4;
+	uint8_t dummy1731[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P5;
+	uint8_t dummy1732[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P6;
+	uint8_t dummy1733[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P7;
+	uint8_t dummy1734[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P8;
+	uint8_t dummy1735[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P0;
+	uint8_t dummy1736[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P1;
+	uint8_t dummy1737[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P2;
+	uint8_t dummy1738[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P3;
+	uint8_t dummy1739[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P4;
+	uint8_t dummy1740[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P5;
+	uint8_t dummy1741[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P6;
+	uint8_t dummy1742[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P7;
+	uint8_t dummy1743[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_IMP;
+	uint8_t dummy1744[12];
+	uint32_t SWITCH_CORE_EEE_GLB_CONG_TH;
+	uint8_t dummy1745[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q0;
+	uint8_t dummy1746[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q1;
+	uint8_t dummy1747[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q2;
+	uint8_t dummy1748[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q3;
+	uint8_t dummy1749[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q4;
+	uint8_t dummy1750[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q5;
+	uint8_t dummy1751[20];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q6;
+	uint8_t dummy1752[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q7;
+	uint8_t dummy1753[44];
+	uint32_t SWITCH_CORE_EEE_CTL_REG_SPARE0;
+	uint8_t dummy1754[36];
+	uint32_t SWITCH_CORE_EEE_CTL_REG_SPARE1;
+	uint8_t dummy1755[52];
+	uint64_t SWITCH_CORE_EEE_DEBUG;
+	uint32_t SWITCH_CORE_EEE_LINK_DLY_TIMER;
+	uint8_t dummy1756[28];
+	uint32_t SWITCH_CORE_EEE_STATE;
+	uint8_t dummy1757[156];
+	uint32_t SWITCH_CORE_PORT_ENABLE;
+	uint8_t dummy1758[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P0;
+	uint8_t dummy1759[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P1;
+	uint8_t dummy1760[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P2;
+	uint8_t dummy1761[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P3;
+	uint8_t dummy1762[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P4;
+	uint8_t dummy1763[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P5;
+	uint8_t dummy1764[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P7;
+	uint8_t dummy1765[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_IMP;
+	uint8_t dummy1766[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P0;
+	uint8_t dummy1767[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P1;
+	uint8_t dummy1768[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P2;
+	uint8_t dummy1769[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P3;
+	uint8_t dummy1770[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P4;
+	uint8_t dummy1771[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P5;
+	uint8_t dummy1772[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P7;
+	uint8_t dummy1773[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_IMP;
+	uint8_t dummy1774[12];
+	uint32_t SWITCH_CORE_TX_TS_CAP;
+	uint8_t dummy1775[12];
+	uint32_t SWITCH_CORE_RX_TS_CAP;
+	uint8_t dummy1776[12];
+	uint32_t SWITCH_CORE_RX_TX_OPTION;
+	uint8_t dummy1777[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_LINK_DELAY_LSB;
+	uint8_t dummy1778[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_LINK_DELAY_MSB;
+	uint8_t dummy1779[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_LINK_DELAY_LSB;
+	uint8_t dummy1780[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_LINK_DELAY_MSB;
+	uint8_t dummy1781[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_LINK_DELAY_LSB;
+	uint8_t dummy1782[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_LINK_DELAY_MSB;
+	uint8_t dummy1783[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_LINK_DELAY_LSB;
+	uint8_t dummy1784[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_LINK_DELAY_MSB;
+	uint8_t dummy1785[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_LINK_DELAY_LSB;
+	uint8_t dummy1786[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_LINK_DELAY_MSB;
+	uint8_t dummy1787[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_LINK_DELAY_LSB;
+	uint8_t dummy1788[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_LINK_DELAY_MSB;
+	uint8_t dummy1789[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_LINK_DELAY_LSB;
+	uint8_t dummy1790[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_LINK_DELAY_MSB;
+	uint8_t dummy1791[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_LINK_DELAY_LSB;
+	uint8_t dummy1792[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_LINK_DELAY_MSB;
+	uint8_t dummy1793[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_TS_OFFSET_LSB;
+	uint8_t dummy1794[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_TS_OFFSET_MSB;
+	uint8_t dummy1795[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_TS_OFFSET_LSB;
+	uint8_t dummy1796[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_TS_OFFSET_MSB;
+	uint8_t dummy1797[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_TS_OFFSET_LSB;
+	uint8_t dummy1798[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_TS_OFFSET_MSB;
+	uint8_t dummy1799[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_TS_OFFSET_LSB;
+	uint8_t dummy1800[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_TS_OFFSET_MSB;
+	uint8_t dummy1801[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_TS_OFFSET_LSB;
+	uint8_t dummy1802[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_TS_OFFSET_MSB;
+	uint8_t dummy1803[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_TS_OFFSET_LSB;
+	uint8_t dummy1804[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_TS_OFFSET_MSB;
+	uint8_t dummy1805[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_TS_OFFSET_LSB;
+	uint8_t dummy1806[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_TS_OFFSET_MSB;
+	uint8_t dummy1807[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_TS_OFFSET_LSB;
+	uint8_t dummy1808[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_TS_OFFSET_MSB;
+	uint8_t dummy1809[12];
+	uint32_t SWITCH_CORE_TX_PORT_0_TS_OFFSET_LSB;
+	uint8_t dummy1810[12];
+	uint32_t SWITCH_CORE_TX_PORT_0_TS_OFFSET_MSB;
+	uint8_t dummy1811[12];
+	uint32_t SWITCH_CORE_TX_PORT_1_TS_OFFSET_LSB;
+	uint8_t dummy1812[12];
+	uint32_t SWITCH_CORE_TX_PORT_1_TS_OFFSET_MSB;
+	uint8_t dummy1813[12];
+	uint32_t SWITCH_CORE_TX_PORT_2_TS_OFFSET_LSB;
+	uint8_t dummy1814[12];
+	uint32_t SWITCH_CORE_TX_PORT_2_TS_OFFSET_MSB;
+	uint8_t dummy1815[12];
+	uint32_t SWITCH_CORE_TX_PORT_3_TS_OFFSET_LSB;
+	uint8_t dummy1816[12];
+	uint32_t SWITCH_CORE_TX_PORT_3_TS_OFFSET_MSB;
+	uint8_t dummy1817[12];
+	uint32_t SWITCH_CORE_TX_PORT_4_TS_OFFSET_LSB;
+	uint8_t dummy1818[12];
+	uint32_t SWITCH_CORE_TX_PORT_4_TS_OFFSET_MSB;
+	uint8_t dummy1819[12];
+	uint32_t SWITCH_CORE_TX_PORT_5_TS_OFFSET_LSB;
+	uint8_t dummy1820[12];
+	uint32_t SWITCH_CORE_TX_PORT_5_TS_OFFSET_MSB;
+	uint8_t dummy1821[12];
+	uint32_t SWITCH_CORE_TX_PORT_7_TS_OFFSET_LSB;
+	uint8_t dummy1822[12];
+	uint32_t SWITCH_CORE_TX_PORT_7_TS_OFFSET_MSB;
+	uint8_t dummy1823[12];
+	uint32_t SWITCH_CORE_TX_PORT_8_TS_OFFSET_LSB;
+	uint8_t dummy1824[12];
+	uint32_t SWITCH_CORE_TX_PORT_8_TS_OFFSET_MSB;
+	uint8_t dummy1825[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P0;
+	uint8_t dummy1826[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P1;
+	uint8_t dummy1827[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P2;
+	uint8_t dummy1828[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P3;
+	uint8_t dummy1829[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P4;
+	uint8_t dummy1830[12];
+	uint32_t SWITCH_CORE_DPLL_DB_LSB;
+	uint8_t dummy1831[12];
+	uint32_t SWITCH_CORE_DPLL_DB_MSB;
+	uint8_t dummy1832[12];
+	uint32_t SWITCH_CORE_DPLL_DB_SEL;
+	uint8_t dummy1833[12];
+	uint32_t SWITCH_CORE_SHD_CTL;
+	uint8_t dummy1834[12];
+	uint32_t SWITCH_CORE_SHD_LD;
+	uint8_t dummy1835[12];
+	uint32_t SWITCH_CORE_INT_MASK;
+	uint8_t dummy1836[12];
+	uint32_t SWITCH_CORE_INT_STAT;
+	uint8_t dummy1837[12];
+	uint32_t SWITCH_CORE_TX_CTL;
+	uint8_t dummy1838[12];
+	uint32_t SWITCH_CORE_RX_CTL;
+	uint8_t dummy1839[12];
+	uint32_t SWITCH_CORE_RX_TX_CTL;
+	uint8_t dummy1840[12];
+	uint32_t SWITCH_CORE_VLAN_ITPID;
+	uint8_t dummy1841[12];
+	uint32_t SWITCH_CORE_VLAN_OTPID;
+	uint8_t dummy1842[12];
+	uint32_t SWITCH_CORE_OTHER_OTPID;
+	uint8_t dummy1843[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_1;
+	uint8_t dummy1844[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_2_N_P0;
+	uint8_t dummy1845[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_2_N_P1;
+	uint8_t dummy1846[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_2_N_P2;
+	uint8_t dummy1847[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_3_N_P0;
+	uint8_t dummy1848[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_3_N_P1;
+	uint8_t dummy1849[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_4;
+	uint8_t dummy1850[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_5;
+	uint8_t dummy1851[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_6;
+	uint8_t dummy1852[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P0;
+	uint8_t dummy1853[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P1;
+	uint8_t dummy1854[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P2;
+	uint8_t dummy1855[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P3;
+	uint8_t dummy1856[12];
+	uint32_t SWITCH_CORE_NSE_NCO_1_N_P0;
+	uint8_t dummy1857[12];
+	uint32_t SWITCH_CORE_NSE_NCO_1_N_P1;
+	uint8_t dummy1858[12];
+	uint32_t SWITCH_CORE_NSE_NCO_2_N_P0;
+	uint8_t dummy1859[12];
+	uint32_t SWITCH_CORE_NSE_NCO_2_N_P1;
+	uint8_t dummy1860[12];
+	uint32_t SWITCH_CORE_NSE_NCO_2_N_P2;
+	uint8_t dummy1861[12];
+	uint32_t SWITCH_CORE_NSE_NCO_3_0;
+	uint8_t dummy1862[12];
+	uint32_t SWITCH_CORE_NSE_NCO_3_1;
+	uint8_t dummy1863[12];
+	uint32_t SWITCH_CORE_NSE_NCO_3_2;
+	uint8_t dummy1864[12];
+	uint32_t SWITCH_CORE_NSE_NCO_4;
+	uint8_t dummy1865[12];
+	uint32_t SWITCH_CORE_NSE_NCO_5_0;
+	uint8_t dummy1866[12];
+	uint32_t SWITCH_CORE_NSE_NCO_5_1;
+	uint8_t dummy1867[12];
+	uint32_t SWITCH_CORE_NSE_NCO_5_2;
+	uint8_t dummy1868[12];
+	uint32_t SWITCH_CORE_NSE_NCO_6;
+	uint8_t dummy1869[12];
+	uint32_t SWITCH_CORE_NSE_NCO_7_0;
+	uint8_t dummy1870[12];
+	uint32_t SWITCH_CORE_NSE_NCO_7_1;
+	uint8_t dummy1871[12];
+	uint32_t SWITCH_CORE_TX_COUNTER;
+	uint8_t dummy1872[12];
+	uint32_t SWITCH_CORE_RX_COUNTER;
+	uint8_t dummy1873[12];
+	uint32_t SWITCH_CORE_RX_TX_1588_COUNTER;
+	uint8_t dummy1874[12];
+	uint32_t SWITCH_CORE_TS_READ_START_END;
+	uint8_t dummy1875[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_0;
+	uint8_t dummy1876[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_1;
+	uint8_t dummy1877[140];
+	uint32_t SWITCH_CORE_HEARTBEAT_2;
+	uint8_t dummy1878[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_N_P0;
+	uint8_t dummy1879[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_N_P1;
+	uint8_t dummy1880[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_N_P2;
+	uint8_t dummy1881[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_N_P0;
+	uint8_t dummy1882[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_N_P1;
+	uint8_t dummy1883[12];
+	uint32_t SWITCH_CORE_CNTR_DBG;
+	uint8_t dummy1884[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE1;
+	uint8_t dummy1885[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE2;
+	uint8_t dummy1886[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE3;
+	uint8_t dummy1887[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE4;
+	uint8_t dummy1888[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE5;
+	uint8_t dummy1889[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE6;
+	uint8_t dummy1890[12];
+	uint32_t SWITCH_CORE_MPLS_TX_CNTL;
+	uint8_t dummy1891[12];
+	uint32_t SWITCH_CORE_MPLS_RX_CNTL;
+	uint8_t dummy1892[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_MASK_LSB;
+	uint8_t dummy1893[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_MASK_MSB;
+	uint8_t dummy1894[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_VALUE_LSB;
+	uint8_t dummy1895[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_VALUE_MSB;
+	uint8_t dummy1896[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_MASK_LSB;
+	uint8_t dummy1897[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_MASK_MSB;
+	uint8_t dummy1898[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_VALUE_LSB;
+	uint8_t dummy1899[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_VALUE_MSB;
+	uint8_t dummy1900[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_MASK_LSB;
+	uint8_t dummy1901[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_MASK_MSB;
+	uint8_t dummy1902[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_VALUE_LSB;
+	uint8_t dummy1903[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_VALUE_MSB;
+	uint8_t dummy1904[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_MASK_LSB;
+	uint8_t dummy1905[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_MASK_MSB;
+	uint8_t dummy1906[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_VALUE_LSB;
+	uint8_t dummy1907[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_VALUE_MSB;
+	uint8_t dummy1908[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_MASK_LSB;
+	uint8_t dummy1909[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_MASK_MSB;
+	uint8_t dummy1910[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_VALUE_LSB;
+	uint8_t dummy1911[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_VALUE_MSB;
+	uint8_t dummy1912[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_MASK_LSB;
+	uint8_t dummy1913[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_MASK_MSB;
+	uint8_t dummy1914[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_VALUE_LSB;
+	uint8_t dummy1915[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_VALUE_MSB;
+	uint8_t dummy1916[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_MASK_LSB;
+	uint8_t dummy1917[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_MASK_MSB;
+	uint8_t dummy1918[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_VALUE_LSB;
+	uint8_t dummy1919[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_VALUE_MSB;
+	uint8_t dummy1920[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_MASK_LSB;
+	uint8_t dummy1921[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_MASK_MSB;
+	uint8_t dummy1922[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_VALUE_LSB;
+	uint8_t dummy1923[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_VALUE_MSB;
+	uint8_t dummy1924[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_MASK_LSB;
+	uint8_t dummy1925[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_MASK_MSB;
+	uint8_t dummy1926[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_VALUE_LSB;
+	uint8_t dummy1927[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_VALUE_MSB;
+	uint8_t dummy1928[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_MASK_LSB;
+	uint8_t dummy1929[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_MASK_MSB;
+	uint8_t dummy1930[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_VALUE_LSB;
+	uint8_t dummy1931[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_VALUE_MSB;
+	uint8_t dummy1932[12];
+	uint32_t SWITCH_CORE_RX_TX_1588_COUNTER1;
+	uint8_t dummy1933[12];
+	uint32_t SWITCH_CORE_RX_CF_SPEC;
+	uint8_t dummy1934[12];
+	uint32_t SWITCH_CORE_TX_CF_SPEC;
+	uint8_t dummy1935[12];
+	uint32_t SWITCH_CORE_MPLS_PACKET_ENABLE;
+	uint8_t dummy1936[12];
+	uint32_t SWITCH_CORE_TIMECODE_SEL;
+	uint8_t dummy1937[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_3;
+	uint8_t dummy1938[12];
+	uint32_t SWITCH_CORE_TIME_STAMP;
+	uint8_t dummy1939[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_TX_CONTROL;
+	uint8_t dummy1940[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_RX_CONTROL;
+	uint8_t dummy1941[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE1;
+	uint8_t dummy1942[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE2;
+	uint8_t dummy1943[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE3;
+	uint8_t dummy1944[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE4;
+	uint8_t dummy1945[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE5;
+	uint8_t dummy1946[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE6;
+	uint8_t dummy1947[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE7;
+	uint8_t dummy1948[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE8;
+	uint8_t dummy1949[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE9;
+	uint8_t dummy1950[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE10;
+	uint8_t dummy1951[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE11;
+	uint8_t dummy1952[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE12;
+	uint8_t dummy1953[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE13;
+	uint8_t dummy1954[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_IETF_OFFSET;
+	uint8_t dummy1955[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P0;
+	uint8_t dummy1956[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P1;
+	uint8_t dummy1957[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P2;
+	uint8_t dummy1958[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P3;
+	uint8_t dummy1959[12];
+	uint32_t SWITCH_CORE_NTP_NCO_FREQ_0;
+	uint8_t dummy1960[12];
+	uint32_t SWITCH_CORE_NTP_NCO_FREQ_1;
+	uint8_t dummy1961[12];
+	uint32_t SWITCH_CORE_NTP_DOWN_CNTER_0;
+	uint8_t dummy1962[12];
+	uint32_t SWITCH_CORE_NTP_DOWN_CNTER_1;
+	uint8_t dummy1963[12];
+	uint32_t SWITCH_CORE_NTP_ERR_LSB;
+	uint8_t dummy1964[12];
+	uint32_t SWITCH_CORE_NTP_ERR_MSB;
+	uint8_t dummy1965[12];
+	uint32_t SWITCH_CORE_DM_MAC_L1_0;
+	uint8_t dummy1966[12];
+	uint32_t SWITCH_CORE_DM_MAC_L1_1;
+	uint8_t dummy1967[12];
+	uint32_t SWITCH_CORE_DM_MAC_L1_2;
+	uint8_t dummy1968[12];
+	uint32_t SWITCH_CORE_DM_MAC_L2_0;
+	uint8_t dummy1969[12];
+	uint32_t SWITCH_CORE_DM_MAC_L2_1;
+	uint8_t dummy1970[12];
+	uint32_t SWITCH_CORE_DM_MAC_L2_2;
+	uint8_t dummy1971[12];
+	uint32_t SWITCH_CORE_DM_MAC_L3_0;
+	uint8_t dummy1972[12];
+	uint32_t SWITCH_CORE_DM_MAC_L3_1;
+	uint8_t dummy1973[12];
+	uint32_t SWITCH_CORE_DM_MAC_L3_2;
+	uint8_t dummy1974[12];
+	uint32_t SWITCH_CORE_DM_MAC_CTL_0;
+	uint8_t dummy1975[12];
+	uint32_t SWITCH_CORE_DM_MAC_CTL_1;
+	uint8_t dummy1976[12];
+	uint32_t SWITCH_CORE_DM_MAC_CTL_2;
+	uint8_t dummy1977[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_3;
+	uint8_t dummy1978[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_4;
+	uint8_t dummy1979[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P0;
+	uint8_t dummy1980[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P1;
+	uint8_t dummy1981[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P2;
+	uint8_t dummy1982[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P3;
+	uint8_t dummy1983[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P4;
+	uint8_t dummy1984[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P5;
+	uint8_t dummy1985[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P6;
+	uint8_t dummy1986[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P7;
+	uint8_t dummy1987[12];
+	uint32_t SWITCH_CORE_MEM_COUNTER;
+	uint8_t dummy1988[12];
+	uint32_t SWITCH_CORE_TIMESTAMP_DELTA;
+	uint8_t dummy1989[12];
+	uint32_t SWITCH_CORE_SOP_SEL;
+	uint8_t dummy1990[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_3;
+	uint8_t dummy1991[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_4;
+	uint8_t dummy1992[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_5;
+	uint8_t dummy1993[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_6;
+	uint8_t dummy1994[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_7;
+	uint8_t dummy1995[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_8;
+	uint8_t dummy1996[12];
+	uint32_t SWITCH_CORE_INBAND_SPARE1;
+	uint8_t dummy1997[140];
+	uint32_t SWITCH_CORE_RED_CONTROL;
+	uint8_t dummy1998[12];
+	uint32_t SWITCH_CORE_TC2RED_PROFILE_TABLE;
+	uint8_t dummy1999[12];
+	uint32_t SWITCH_CORE_RED_EGRESS_BYPASS;
+	uint8_t dummy2000[12];
+	uint32_t SWITCH_CORE_RED_AQD_CONTROL;
+	uint8_t dummy2001[12];
+	uint32_t SWITCH_CORE_RED_EXPONENT;
+	uint8_t dummy2002[12];
+	uint32_t SWITCH_CORE_RED_DROP_ADD_TO_MIB;
+	uint8_t dummy2003[44];
+	uint32_t SWITCH_CORE_RED_PROFILE_DEFAULT;
+	uint8_t dummy2004[28];
+	uint32_t SWITCH_CORE_WRED_REG_SPARE0;
+	uint8_t dummy2005[28];
+	uint32_t SWITCH_CORE_WRED_REG_SPARE1;
+	uint8_t dummy2006[60];
+	uint32_t SWITCH_CORE_RED_PROFILE0;
+	uint8_t dummy2007[28];
+	uint32_t SWITCH_CORE_RED_PROFILE1;
+	uint8_t dummy2008[28];
+	uint32_t SWITCH_CORE_RED_PROFILE2;
+	uint8_t dummy2009[28];
+	uint32_t SWITCH_CORE_RED_PROFILE3;
+	uint8_t dummy2010[28];
+	uint32_t SWITCH_CORE_RED_PROFILE4;
+	uint8_t dummy2011[28];
+	uint32_t SWITCH_CORE_RED_PROFILE5;
+	uint8_t dummy2012[28];
+	uint32_t SWITCH_CORE_RED_PROFILE6;
+	uint8_t dummy2013[28];
+	uint32_t SWITCH_CORE_RED_PROFILE7;
+	uint8_t dummy2014[28];
+	uint32_t SWITCH_CORE_RED_PROFILE8;
+	uint8_t dummy2015[28];
+	uint32_t SWITCH_CORE_RED_PROFILE9;
+	uint8_t dummy2016[28];
+	uint32_t SWITCH_CORE_RED_PROFILE10;
+	uint8_t dummy2017[28];
+	uint32_t SWITCH_CORE_RED_PROFILE11;
+	uint8_t dummy2018[28];
+	uint32_t SWITCH_CORE_RED_PROFILE12;
+	uint8_t dummy2019[28];
+	uint32_t SWITCH_CORE_RED_PROFILE13;
+	uint8_t dummy2020[28];
+	uint32_t SWITCH_CORE_RED_PROFILE14;
+	uint8_t dummy2021[28];
+	uint32_t SWITCH_CORE_RED_PROFILE15;
+	uint8_t dummy2022[124];
+	uint32_t SWITCH_CORE_RED_DROP_CNTR_RST;
+	uint8_t dummy2023[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P0;
+	uint8_t dummy2024[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P1;
+	uint8_t dummy2025[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P2;
+	uint8_t dummy2026[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P3;
+	uint8_t dummy2027[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P4;
+	uint8_t dummy2028[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P5;
+	uint8_t dummy2029[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P6;
+	uint8_t dummy2030[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P7;
+	uint8_t dummy2031[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_IMP;
+	uint8_t dummy2032[124];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P0;
+	uint8_t dummy2033[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P1;
+	uint8_t dummy2034[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P2;
+	uint8_t dummy2035[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P3;
+	uint8_t dummy2036[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P4;
+	uint8_t dummy2037[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P5;
+	uint8_t dummy2038[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P6;
+	uint8_t dummy2039[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P7;
+	uint8_t dummy2040[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_IMP;
+	uint8_t dummy2041[20732];
+	uint32_t SWITCH_CORE_CFP_ACC;
+	uint8_t dummy2042[28];
+	uint32_t SWITCH_CORE_RATE_METER_GLOBAL_CTL;
+	uint8_t dummy2043[92];
+	uint32_t SWITCH_CORE_CFP_DATA0;
+	uint8_t dummy2044[28];
+	uint32_t SWITCH_CORE_CFP_DATA1;
+	uint8_t dummy2045[28];
+	uint32_t SWITCH_CORE_CFP_DATA2;
+	uint8_t dummy2046[28];
+	uint32_t SWITCH_CORE_CFP_DATA3;
+	uint8_t dummy2047[28];
+	uint32_t SWITCH_CORE_CFP_DATA4;
+	uint8_t dummy2048[28];
+	uint32_t SWITCH_CORE_CFP_DATA5;
+	uint8_t dummy2049[28];
+	uint32_t SWITCH_CORE_CFP_DATA6;
+	uint8_t dummy2050[28];
+	uint32_t SWITCH_CORE_CFP_DATA7;
+	uint8_t dummy2051[28];
+	uint32_t SWITCH_CORE_CFP_MASK0;
+	uint8_t dummy2052[28];
+	uint32_t SWITCH_CORE_CFP_MASK1;
+	uint8_t dummy2053[28];
+	uint32_t SWITCH_CORE_CFP_MASK2;
+	uint8_t dummy2054[28];
+	uint32_t SWITCH_CORE_CFP_MASK3;
+	uint8_t dummy2055[28];
+	uint32_t SWITCH_CORE_CFP_MASK4;
+	uint8_t dummy2056[28];
+	uint32_t SWITCH_CORE_CFP_MASK5;
+	uint8_t dummy2057[28];
+	uint32_t SWITCH_CORE_CFP_MASK6;
+	uint8_t dummy2058[28];
+	uint32_t SWITCH_CORE_CFP_MASK7;
+	uint8_t dummy2059[28];
+	uint32_t SWITCH_CORE_ACT_POL_DATA0;
+	uint8_t dummy2060[28];
+	uint32_t SWITCH_CORE_ACT_POL_DATA1;
+	uint8_t dummy2061[28];
+	uint32_t SWITCH_CORE_ACT_POL_DATA2;
+	uint8_t dummy2062[60];
+	uint32_t SWITCH_CORE_RATE_METER0;
+	uint8_t dummy2063[28];
+	uint32_t SWITCH_CORE_RATE_METER1;
+	uint8_t dummy2064[28];
+	uint32_t SWITCH_CORE_RATE_METER2;
+	uint8_t dummy2065[28];
+	uint32_t SWITCH_CORE_RATE_METER3;
+	uint8_t dummy2066[28];
+	uint32_t SWITCH_CORE_RATE_METER4;
+	uint8_t dummy2067[28];
+	uint32_t SWITCH_CORE_RATE_METER5;
+	uint8_t dummy2068[28];
+	uint32_t SWITCH_CORE_RATE_METER6;
+	uint8_t dummy2069[28];
+	uint32_t SWITCH_CORE_TC2COLOR;
+	uint8_t dummy2070[28];
+	uint32_t SWITCH_CORE_STAT_GREEN_CNTR;
+	uint8_t dummy2071[28];
+	uint32_t SWITCH_CORE_STAT_YELLOW_CNTR;
+	uint8_t dummy2072[28];
+	uint32_t SWITCH_CORE_STAT_RED_CNTR;
+	uint8_t dummy2073[188];
+	uint32_t SWITCH_CORE_TCAM_BIST_CONTROL;
+	uint8_t dummy2074[28];
+	uint32_t SWITCH_CORE_TCAM_BIST_STATUS;
+	uint8_t dummy2075[28];
+	uint32_t SWITCH_CORE_TCAM_TEST_COMPARE_STATUS;
+	uint8_t dummy2076[60];
+	uint32_t SWITCH_CORE_CFP_REG_SPARE0;
+	uint8_t dummy2077[28];
+	uint32_t SWITCH_CORE_CFP_REG_SPARE1;
+	uint8_t dummy2078[604];
+	uint32_t SWITCH_CORE_CFP_CTL_REG;
+	uint8_t dummy2079[124];
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_0;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_1;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_2;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_3;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_4;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_5;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_6;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_7;
+	uint32_t SWITCH_CORE_UDF_0_A_0_8_8;
+	uint8_t dummy2080[60];
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_0;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_1;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_2;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_3;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_4;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_5;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_6;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_7;
+	uint32_t SWITCH_CORE_UDF_1_A_0_8_8;
+	uint8_t dummy2081[60];
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_0;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_1;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_2;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_3;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_4;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_5;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_6;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_7;
+	uint32_t SWITCH_CORE_UDF_2_A_0_8_8;
+	uint8_t dummy2082[60];
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_0;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_1;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_2;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_3;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_4;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_5;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_6;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_7;
+	uint32_t SWITCH_CORE_UDF_0_B_0_8_8;
+	uint8_t dummy2083[60];
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_0;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_1;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_2;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_3;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_4;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_5;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_6;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_7;
+	uint32_t SWITCH_CORE_UDF_1_B_0_8_8;
+	uint8_t dummy2084[60];
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_0;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_1;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_2;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_3;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_4;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_5;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_6;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_7;
+	uint32_t SWITCH_CORE_UDF_2_B_0_8_8;
+	uint8_t dummy2085[60];
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_0;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_1;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_2;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_3;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_4;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_5;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_6;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_7;
+	uint32_t SWITCH_CORE_UDF_0_C_0_8_8;
+	uint8_t dummy2086[60];
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_0;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_1;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_2;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_3;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_4;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_5;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_6;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_7;
+	uint32_t SWITCH_CORE_UDF_1_C_0_8_8;
+	uint8_t dummy2087[60];
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_0;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_1;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_2;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_3;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_4;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_5;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_6;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_7;
+	uint32_t SWITCH_CORE_UDF_2_C_0_8_8;
+	uint8_t dummy2088[60];
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_0;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_1;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_2;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_3;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_4;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_5;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_6;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_7;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_8;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_9;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_10;
+	uint32_t SWITCH_CORE_UDF_0_D_0_11_11;
+	uint8_t dummy2089[29348];
+	uint32_t SWITCH_CORE_ARL_TCAM_ACC;
+	uint8_t dummy2090[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_DATA_P0;
+	uint8_t dummy2091[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_DATA_P1;
+	uint8_t dummy2092[92];
+	uint32_t SWITCH_CORE_ARL_SMEM_DATA;
+	uint8_t dummy2093[92];
+	uint32_t SWITCH_CORE_ARL_TCAM_BIST_CTRL;
+	uint8_t dummy2094[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_BIST_STS;
+	uint8_t dummy2095[100060];
+	uint32_t SWITCH_CORE_PLL_NDIV_INT;
+	uint8_t dummy2096[12];
+	uint32_t SWITCH_CORE_PLL_NDIV_FRAC;
+	uint8_t dummy2097[28];
+	uint32_t SWITCH_CORE_PLL_SDMOD_CTRL;
+	uint8_t dummy2098[12];
+	uint32_t SWITCH_CORE_PLL_MOD_CTRL_0;
+	uint8_t dummy2099[28];
+	uint32_t SWITCH_CORE_PLL_MOD_CTRL_1;
+	uint8_t dummy2100[28];
+	uint32_t SWITCH_CORE_PLL_MOD_CTRL_2;
+	uint8_t dummy2101[28];
+	uint32_t SWITCH_CORE_PLL_MISC_CTRL;
+	uint8_t dummy2102[12];
+	uint32_t SWITCH_CORE_PLL_DELOCK_MIB;
+	uint8_t dummy2103[28];
+	uint32_t SWITCH_CORE_PLL_SS_CTL;
+	uint8_t dummy2104[44];
+	uint32_t SWITCH_CORE_PLL_CTRL;
+	uint8_t dummy2105[12];
+	uint32_t SWITCH_CORE_PLL_STS;
+	uint8_t dummy2106[60];
+	uint32_t SWITCH_CORE_PLL_FREQ_SEL;
+	uint8_t dummy2107[44];
+	uint32_t SWITCH_CORE_PLL_TEST_CTRL_I;
+	uint8_t dummy2108[12];
+	uint32_t SWITCH_CORE_PLL_TEST_CTRL_II;
+	uint8_t dummy2109[108];
+	uint32_t SWITCH_CORE_GREEN_MODE_DATA;
+	uint8_t dummy2110[60];
+	uint32_t SWITCH_CORE_GREEN_MODE_SELECT;
+	uint8_t dummy2111[444];
+	uint32_t SWITCH_CORE_TOP_LOW_POWER_CTRL;
+	uint8_t dummy2112[12];
+	uint32_t SWITCH_CORE_TOP_IDDQ_CTL;
+	uint8_t dummy2113[108];
+	uint32_t SWITCH_CORE_IP_PLL_BYPASS;
+	uint8_t dummy2114[636];
+	uint32_t SWITCH_CORE_TOP_MODULE_CTL_SPARE0;
+	uint8_t dummy2115[28];
+	uint32_t SWITCH_CORE_TOP_MODULE_CTL_SPARE1;
+	uint8_t dummy2116[220];
+	uint32_t SWITCH_CORE_EGPHY_CTRL;
+	uint8_t dummy2117[12];
+	uint32_t SWITCH_CORE_EGPHY_PWRMGNT;
+	uint8_t dummy2118[12];
+	uint32_t SWITCH_CORE_EGPHY_PWR_DOWN;
+	uint8_t dummy2119[44];
+	uint32_t SWITCH_CORE_EGPHY_STRAP;
+	uint8_t dummy2120[12];
+	uint32_t SWITCH_CORE_EGPHY_STS;
+	uint8_t dummy2121[12];
+	uint32_t SWITCH_CORE_EGPHY_INT_STS;
+	uint8_t dummy2122[12];
+	uint32_t SWITCH_CORE_EGPHY_MODE_STS;
+	uint8_t dummy2123[12];
+	uint32_t SWITCH_CORE_EGPHY_LPI_STS;
+	uint8_t dummy2124[12];
+	uint32_t SWITCH_CORE_EGPHY_ENG_DET_STS;
+	uint8_t dummy2125[12];
+	uint32_t SWITCH_CORE_EGPHY_ENG_DET_STS_CHG;
+	uint8_t dummy2126[12];
+	uint32_t SWITCH_CORE_EGPHY_RESET_STATUS;
+	uint8_t dummy2127[1596];
+	uint32_t SWITCH_CORE_EGPHY_CTL_SPARE0;
+	uint8_t dummy2128[28];
+	uint32_t SWITCH_CORE_EGPHY_CTL_SPARE1;
+	uint8_t dummy2129[220];
+	uint32_t SWITCH_CORE_BRPHY_CTRL;
+	uint8_t dummy2130[12];
+	uint32_t SWITCH_CORE_BRPHY_PWRMGNT;
+	uint8_t dummy2131[12];
+	uint32_t SWITCH_CORE_BRPHY_PWR_DOWN;
+	uint8_t dummy2132[28];
+	uint32_t SWITCH_CORE_BRPHY_PLL_CTRL;
+	uint8_t dummy2133[28];
+	uint32_t SWITCH_CORE_BRPHY_STS;
+	uint8_t dummy2134[12];
+	uint32_t SWITCH_CORE_BRPHY_INT_STS;
+	uint8_t dummy2135[44];
+	uint32_t SWITCH_CORE_BRPHY_ENG_DET_STS;
+	uint8_t dummy2136[12];
+	uint32_t SWITCH_CORE_BRPHY_ENG_DET_STS_CHG;
+	uint8_t dummy2137[12];
+	uint32_t SWITCH_CORE_BRPHY_RESET_STATUS;
+	uint8_t dummy2138[1596];
+	uint32_t SWITCH_CORE_BRPHY_CTL_SPARE0;
+	uint8_t dummy2139[28];
+	uint32_t SWITCH_CORE_BRPHY_CTL_SPARE1;
+	uint8_t dummy2140[220];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P0;
+	uint8_t dummy2141[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P1;
+	uint8_t dummy2142[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P2;
+	uint8_t dummy2143[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P3;
+	uint8_t dummy2144[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P4;
+	uint8_t dummy2145[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P5;
+	uint8_t dummy2146[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_P6;
+	uint8_t dummy2147[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P7;
+	uint8_t dummy2148[12];
+	uint32_t imp_port_state;
+#define ETHSW_IPS_USE_MII_HW_STS                  0x00
+#define ETHSW_IPS_USE_REG_CONTENTS                0x80
+#define ETHSW_IPS_GMII_SPEED_UP_NORMAL            0x00
+#define ETHSW_IPS_GMII_SPEED_UP_2G                0x40
+#define ETHSW_IPS_TXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_TXFLOW_PAUSE_CAPABLE            0x20
+#define ETHSW_IPS_RXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_RXFLOW_PAUSE_CAPABLE            0x10
+#define ETHSW_IPS_SW_PORT_SPEED_1000M_2000M       0x08
+#define ETHSW_IPS_DUPLEX_MODE                     0x02
+#define ETHSW_IPS_LINK_FAIL                       0x00
+#define ETHSW_IPS_LINK_PASS                       0x01
+	uint8_t dummy2149[60];
+	uint32_t SWITCH_CORE_PAUSE_CAP;
+	uint8_t dummy2150[124];
+	uint32_t SWITCH_CORE_PORT4_RGMII_CTL_GP;
+	uint8_t dummy2151[12];
+	uint32_t SWITCH_CORE_PORT5_RGMII_CTL_GP;
+	uint8_t dummy2152[12];
+	uint32_t SWITCH_CORE_PORT6_RGMII_CTL_GP;
+	uint8_t dummy2153[28];
+	uint32_t SWITCH_CORE_RGMII_CTL_GP_IMP;
+	uint8_t dummy2154[188];
+	uint32_t SWITCH_CORE_P4_RGMII_TIME_DLY_GP;
+	uint8_t dummy2155[12];
+	uint32_t SWITCH_CORE_P5_RGMII_TIME_DLY_GP;
+	uint8_t dummy2156[12];
+	uint32_t SWITCH_CORE_P6_RGMII_TIME_DLY_GP;
+	uint8_t dummy2157[28];
+	uint32_t SWITCH_CORE_RGMII_TIME_DLY_GP_IMP;
+	uint8_t dummy2158[124];
+	uint32_t SWITCH_CORE_RM_PINS_DEBUG;
+	uint8_t dummy2159[12];
+	uint32_t SWITCH_CORE_MII_IDDQ_CTRL;
+	uint8_t dummy2160[12];
+	uint32_t SWITCH_CORE_MII_LOW_POWER_CTRL;
+	uint8_t dummy2161[12];
+	uint32_t SWITCH_CORE_LED_OPTIONS;
+	uint8_t dummy2162[972];
+	uint32_t SWITCH_CORE_PORT_INFO_SPARE0;
+	uint8_t dummy2163[28];
+	uint32_t SWITCH_CORE_PORT_INFO_SPARE1;
+	uint8_t dummy2164[220];
+	uint32_t SWITCH_CORE_IO_SR_CTL;
+	uint8_t dummy2165[28];
+	uint32_t SWITCH_CORE_IO_DS_SEL0;
+	uint8_t dummy2166[60];
+	uint32_t SWITCH_CORE_IO_DS_SEL2;
+	uint8_t dummy2167[28];
+	uint32_t SWITCH_CORE_GMII_IO_SR_CTL;
+	uint8_t dummy2168[28];
+	uint32_t SWITCH_CORE_GMII_IO_DS_SEL0;
+	uint8_t dummy2169[28];
+	uint32_t SWITCH_CORE_GMII_IO_DS_SEL1;
+	uint8_t dummy2170[28];
+	uint32_t SWITCH_CORE_GMII_VOL_SEL;
+	uint8_t dummy2171[12];
+	uint32_t SWITCH_CORE_PINS_DEBUG_IMP;
+	uint8_t dummy2172[28];
+	uint32_t SWITCH_CORE_BONDING_PAD_STATUS;
+	uint8_t dummy2173[12];
+	uint32_t SWITCH_CORE_STRAP_PIN_STATUS;
+	uint8_t dummy2174[28];
+	uint32_t SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE;
+	uint8_t dummy2175[60];
+	uint32_t SWITCH_CORE_EMB_CPU_STATUS;
+	uint8_t dummy2176[1404];
+	uint32_t SWITCH_CORE_CHIP_CTL_SPARE0;
+	uint8_t dummy2177[28];
+	uint32_t SWITCH_CORE_CHIP_CTL_SPARE1;
+
+} EthernetSwitchCore;
+
+#define PBMAP_MIPS 0x100
+
diff --git a/arch/arm/include/asm/arch-bcm63178/misc.h b/arch/arm/include/asm/arch-bcm63178/misc.h
new file mode 100644
index 0000000000..5140af1e06
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/misc.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63178_MISC_H
+#define _63178_MISC_H
+
+#define MISC_BASE          0xff802600
+
+/*
+ * Misc Register Set Definitions.
+ */
+typedef struct Misc {
+    uint32_t  miscStrapBus;                       /* 0x00 */
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           0
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_PCIE0_RC_MODE            (0x1 << 6)
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT      9
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ            (0x1 << MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT)
+#define MISC_STRAP_BUS_BOOTROM_BOOT             (0x1 << 11)
+#define MISC_STRAP_BUS_B53_NO_BOOT              (0x1 << 12) /* 1-PMC boot A53, 0-A53 boots at POR */
+
+    uint32_t  miscStrapOverride;                  /* 0x04 */
+    uint32_t  miscMaskUBUSErr;                    /* 0x08 */
+    uint32_t  miscPeriphCtrl;                     /* 0x0c */
+    uint32_t  miscSPImasterCtrl;                  /* 0x10 */
+    uint32_t  miscDierevid;                       /* 0x14 */
+    uint32_t  miscPeriphMiscCtrl;                 /* 0x18 */
+    uint32_t  miscPeriphMiscStat;                 /* 0x1c */
+    uint32_t  miscSoftResetB;                     /* 0x20 */
+    uint32_t  reserved0;                          /* 0x24 */
+    uint32_t  miscSWdebugNW[2];                   /* 0x28 */
+    uint32_t  miscWDresetCtrl;                    /* 0x30 */
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+
+typedef struct TopControl {
+   uint32_t      reserved_00;        // 0x0
+   uint32_t      Rgmii1PadCtl;       // 0x4
+#define MISC_XMII_PAD_MODEHV                    (1 << 6)
+#define MISC_XMII_PAD_IND                       (1 << 5) 
+#define MISC_XMII_PAD_SEL_GMII                  (1 << 4)
+#define MISC_XMII_PAD_AMP_EN                    (1 << 3)
+#define MISC_XMII_PAD_DRIVE_STRENGTH_SHIFT      0
+#define MISC_XMII_PAD_DRIVE_STRENGTH_MASK       (0x7<<MISC_XMII_PAD_DRIVE_STRENGTH_SHIFT)
+   uint32_t      reserved_08;        // 0x8
+   uint32_t      reserved_0c;        // 0xc
+   uint32_t      MiiPullCtl;         // 0x10
+   uint32_t      Rgmii1PullCtl;      // 0x14
+   uint32_t      Rgmii2PullCtl;      // 0x18
+   uint32_t      Rgmii3PullCtl;      // 0x1c
+   uint32_t      SgmiiFiberDetect;   // 0x20
+   uint32_t      DgSensePadCtl;      // 0x24
+#define DG_CTRL_SHIFT   4
+#define DG_EN_SHIFT     3
+#define DG_TRIM_SHIFT   0
+   uint32_t      TpDirOverride0;     // 0x28
+   uint32_t      TpDirOverride1;     // 0x2c
+   uint32_t      RescalReadData0;    // 0x30
+   uint32_t      RescalReadData1;    // 0x34
+   uint32_t      reserved0;          // 0x38 
+   uint32_t      ResetStatus;        // 0x3c 
+#define PCIE_RESET_STATUS       0x10000000
+#define SW_RESET_STATUS         0x20000000
+#define HW_RESET_STATUS         0x40000000
+#define POR_RESET_STATUS        0x80000000
+#define RESET_STATUS_MASK       0xF0000000
+   uint32_t      TodSync;            // 0x40
+   uint32_t      Pm0Pm1RescalSts;    // 0x44
+   uint32_t      Pm2Pm3RescalSts;    // 0x48
+   uint32_t      SgbRescalSts;       // 0x4c
+   uint32_t      Pm0Pm1RescalCfg;    // 0x50
+   uint32_t      Pm2Pm3RescalCfg;    // 0x54
+   uint32_t      SgbRescalCfg;       // 0x58
+   uint32_t      Pm0Pm1TmonCfg;      // 0x5c
+   uint32_t      Pm2Pm3TmonCfg;      // 0x60
+   uint32_t      SgbTmonCfg;         // 0x64
+   uint32_t      MdioMasterSelect;   // 0x68
+   uint32_t      SwControlReg;       // 0x6c
+   uint32_t      Reg2P5VDectCtrl;    // 0x70
+   uint32_t      OrionIntPending;    // 0x74
+   uint32_t      DslClockSample;     // 0x78
+   uint32_t      LdoCtl;             // 0x7c
+#define LDO_VREG_CTRL_EN           0x400000
+#define LDO_VREG_CTRL_SHIFT        1
+#define LDO_VREG_CTRL_MASK         (0x1fffff << LDO_VREG_CTRL_SHIFT)
+#define LDO_VREG_CTRL_TRIM_SHIFT   2
+#define LDO_VREG_CTRL_TRIM_MASK    (0xf << LDO_VREG_CTRL_TRIM_SHIFT)
+#define LDO_VREG_CTRL_SELECT_SHIFT 6
+#define LDO_VREG_CTRL_SELECT_MASK  (0xf << LDO_VREG_CTRL_SELECT_SHIFT)
+#define LDO_VREG_CTRL_PWRDN        0x1
+} TopControl;
+
+#define TOP_CONTROL_BASE           0xff85a000
+#define TOPCTRL ((volatile TopControl * const) TOP_CONTROL_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63178/otp.h b/arch/arm/include/asm/arch-bcm63178/otp.h
new file mode 100644
index 0000000000..a79b9fe4f9
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/otp.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _63178_OTP_H
+#define _63178_OTP_H
+
+#define JTAG_OTP_BASE   0xff802800
+
+/* row 8 */
+#define OTP_CPU_CORE_CFG_ROW            8
+#define OTP_CPU_CORE_CFG_SHIFT          28
+#define OTP_CPU_CORE_CFG_MASK           0x1
+
+/* row 9 */
+#define OTP_LDO_TRIM_ROW                9
+#define OTP_LDO_TRIM_SHIFT              28
+#define OTP_LDO_TRIM_MASK               0xf
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          7
+
+/* row 23 */
+#define OTP_CUST_MFG_MRKTID_ROW                 23
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+/* row 9 */
+#define OTP_LDO_TRIM_ROW                9
+#define OTP_LDO_TRIM_SHIFT              28
+#define OTP_LDO_TRIM_MASK               0xf
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_CPU_CORE_CFG, OTP_CPU_CORE_CFG_ROW, OTP_CPU_CORE_CFG_MASK, OTP_CPU_CORE_CFG_SHIFT, 1},				\
+	{OTP_MAP_LDO_TRIM, OTP_LDO_TRIM_ROW, OTP_LDO_TRIM_MASK, OTP_LDO_TRIM_SHIFT, 1},				\
+	}
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63178/pmc.h b/arch/arm/include/asm/arch-bcm63178/pmc.h
new file mode 100644
index 0000000000..b7402bd156
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/pmc.h
@@ -0,0 +1,336 @@
+#ifndef PMC_H
+#define PMC_H 
+/*
+ * Power Management Control
+ */
+typedef struct PmcCtrlReg {
+    uint32_t gpTmr0Ctl;           /* 0x018 */
+    uint32_t gpTmr0Cnt;           /* 0x01c */
+    uint32_t gpTmr1Ctl;           /* 0x020 */
+    uint32_t gpTmr1Cnt;           /* 0x024 */
+    uint32_t hostMboxIn;          /* 0x028 */
+    uint32_t hostMboxOut;         /* 0x02c */
+    uint32_t reserved[4];         /* 0x030 */
+    uint32_t dmaCtrl;             /* 0x040 */
+    uint32_t dmaStatus;           /* 0x044 */
+    uint32_t dma0_3FifoStatus;    /* 0x048 */
+    uint32_t reserved1[4];	    /* 0x04c */
+    uint32_t diagControl;         /* 0x05c */
+    uint32_t diagHigh;            /* 0x060 */
+    uint32_t diagLow;             /* 0x064 */
+    uint32_t reserved8;           /* 0x068 */
+    uint32_t addr1WndwMask;       /* 0x06c */
+    uint32_t addr1WndwBaseIn;     /* 0x070 */
+    uint32_t addr1WndwBaseOut;    /* 0x074 */
+    uint32_t addr2WndwMask;       /* 0x078 */
+    uint32_t addr2WndwBaseIn;     /* 0x07c */
+    uint32_t addr2WndwBaseOut;    /* 0x080 */
+    uint32_t scratch;             /* 0x084 */
+    uint32_t reserved9;           /* 0x088 */
+    uint32_t softResets;          /* 0x08c */
+    uint32_t reserved2;           /* 0x090 */
+    uint32_t m4keCoreStatus;      /* 0x094 */
+    uint32_t reserved3;           /* 0x098 */
+    uint32_t ubSlaveTimeout;      /* 0x09c */
+    uint32_t diagEn;              /* 0x0a0 */
+    uint32_t devTimeout;          /* 0x0a4 */
+    uint32_t ubusErrorOutMask;    /* 0x0a8 */
+    uint32_t diagCaptStopMask;    /* 0x0ac */
+    uint32_t revId;               /* 0x0b0 */
+    uint32_t reserved4[4];        /* 0x0b4 */
+    uint32_t diagCtrl;            /* 0x0c4 */
+    uint32_t diagStat;            /* 0x0c8 */
+    uint32_t diagMask;            /* 0x0cc */
+    uint32_t diagRslt;            /* 0x0d0 */
+    uint32_t diagCmp;             /* 0x0d4 */
+    uint32_t diagCapt;            /* 0x0d8 */    
+    uint32_t diagCnt;             /* 0x0dc */
+    uint32_t diagEdgeCnt;         /* 0x0e0 */
+    uint32_t reserved5[4];	    /* 0x0e4 */
+    uint32_t smisc_bus_config;    /* 0x0f4 */
+    uint32_t lfsr;                /* 0x0f8 */
+    uint32_t dqm_pac_lock;        /* 0x0fc */
+    uint32_t l1_irq_4ke_mask;     /* 0x100 */
+    uint32_t l1_irq_4ke_status;   /* 0x104 */
+    uint32_t l1_irq_mips_mask;    /* 0x108 */
+    uint32_t l1_irq_mips_status;  /* 0x10c */
+    uint32_t l1_irq_mips1_mask;   /* 0x110 */
+    uint32_t reserved6[3];        /* 0x114 */
+    uint32_t l2_irq_gp_mask;      /* 0x120 */
+    uint32_t l2_irq_gp_status;    /* 0x124 */
+    uint32_t l2_irq_gp_set;       /* 0x128 */
+    uint32_t reserved7;           /* 0x12c */
+    uint32_t gp_in_irq_mask;      /* 0x130 */
+    uint32_t gp_in_irq_status;    /* 0x134 */
+    uint32_t gp_in_irq_set;       /* 0x138 */
+    uint32_t gp_in_irq_sense;     /* 0x13c */
+    uint32_t gp_in;               /* 0x140 */
+    uint32_t gp_out;              /* 0x144 */
+} PmcCtrlReg;
+
+typedef struct PmcDmaReg {
+	/* 0x00 */
+	uint32_t src;
+	uint32_t dest;
+	uint32_t cmdList;
+	uint32_t lenCtl;
+	/* 0x10 */
+	uint32_t rsltSrc;
+	uint32_t rsltDest;
+	uint32_t rsltHcs;
+	uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+	/* 0x00 */
+	uint32_t bufSize;
+	uint32_t bufBase;
+	uint32_t idx2ptrIdx;
+	uint32_t idx2ptrPtr;
+	/* 0x10 */
+	uint32_t unused[2];
+	uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+	uint32_t freqScalarCtrl; /* 0x3c */
+	uint32_t freqScalarMask; /* 0x40 */
+} PmcPerfPowReg;
+
+typedef struct PmcDQMPac {
+    uint32_t dqmPac[32];
+} PmcDQMPac;
+
+typedef struct PmcDQMReg {
+	uint32_t cfg;                     /* 0x1c00 */
+	uint32_t _4keLowWtmkIrqMask;      /* 0x1c04 */
+	uint32_t mipsLowWtmkIrqMask;      /* 0x1c08 */
+	uint32_t lowWtmkIrqMask;          /* 0x1c0c */
+	uint32_t _4keNotEmptyIrqMask;     /* 0x1c10 */
+	uint32_t mipsNotEmptyIrqMask;     /* 0x1c14 */
+	uint32_t notEmptyIrqSts;          /* 0x1c18 */
+	uint32_t queueRst;                /* 0x1c1c */
+	uint32_t notEmptySts;             /* 0x1c20 */
+	uint32_t nextAvailMask;           /* 0x1c24 */
+	uint32_t nextAvailQueue;          /* 0x1c28 */
+	uint32_t mips1LowWtmkIrqMask;     /* 0x1c2c */
+	uint32_t mips1NotEmptyIrqMask;    /* 0x1c30 */
+	uint32_t autoSrcPidInsert;        /* 0x1c34 */
+    uint32_t timerIrqStatus;          /* 0x1c38 */
+    uint32_t timerStatus;             /* 0x1c3c */
+    uint32_t _4keTimerIrqMask;        /* 0x1c40 */
+    uint32_t mipsTimerIrqMask;        /* 0x1c44 */
+    uint32_t mips1TimerIrqMask;       /* 0x1c48 */
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+	uint32_t cntr[10];
+	uint32_t unused[6];	/* 0x28-0x3f */
+	uint32_t cntrIrqMask;
+	uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+	uint32_t size;
+	uint32_t cfga;
+	uint32_t cfgb;
+	uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+	uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+	uint32_t qNumFull[32];
+	uint32_t qNumEmpty[32];
+	uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+typedef struct SSBMaster {
+    uint32_t ssbmControl;     /* 0x0060 */
+    uint32_t ssbmWrData;      /* 0x0064 */
+    uint32_t ssbmRdData;      /* 0x0068 */
+    uint32_t ssbmStatus;      /* 0x006c */
+} SSBMaster;
+
+typedef struct PmmReg {
+    uint32_t memPowerCtrl;            /* 0x0000 */
+    uint32_t regSecurityConfig;       /* 0x0004 */
+} PmmReg;
+
+typedef struct keyholeReg {
+    uint32_t ctrlSts;
+    uint32_t wrData;
+    uint32_t mutex;
+    uint32_t rdData;
+} keyholeReg;
+
+typedef struct PmbBus {
+    uint32_t config;          /* 0x0100 */
+    uint32_t arbiter;         /* 0x0104 */
+    uint32_t timeout;         /* 0x0108 */
+    uint32_t unused1;         /* 0x010c */
+    keyholeReg keyhole[4];  /* 0x0110-0x014f */
+    uint32_t unused2[44];     /* 0x0150-0x01ff */
+    uint32_t map[64];         /* 0x0200-0x02ff */ 
+}PmbBus;
+
+typedef struct  CoreCtrl {
+    uint32_t  coreEnable;         /* 0x0400 */
+    uint32_t  autoresetControl;   /* 0x0404 */
+    uint32_t  coreIdle;           /* 0x0408 */
+    uint32_t  coreResetCause;     /* 0x040c */
+    uint32_t  memPwrDownCtrl0;    /* 0x0410 */
+    uint32_t  memPwrDownSts0;     /* 0x0414 */
+    uint32_t  memPwrDownCtrl1;    /* 0x0418 */
+    uint32_t  memPwrDownSts1;     /* 0x041c */
+    uint32_t  sysFlg0Status;      /* 0x0420 */
+    uint32_t  sysFlg0Set;         /* 0x0424 */
+    uint32_t  sysFlg0Clear;       /* 0x0428 */
+    uint32_t  unused1;            /* 0x042c */
+    uint32_t  usrFlg0Status;      /* 0x0430 */
+    uint32_t  usrFlg0Set;         /* 0x0434 */
+    uint32_t  usrFlg0Clear;       /* 0x0438 */
+    uint32_t  unused2;            /* 0x043c */
+    uint32_t  subsystemRev;       /* 0x0440 */
+    uint32_t  resetVector;        /* 0x0444 */
+} CoreCtrl;
+
+typedef struct  CoreState {
+    uint32_t  sysMbx[8];          /* 0x0480 */
+    uint32_t  usrMbx[8];          /* 0x04a0 */
+    uint32_t  sysMtx[4];          /* 0x04c0 */
+    uint32_t  usrMtx[8];          /* 0x04d0 */
+} CoreState;
+
+typedef struct  CoreIntr {
+    uint32_t  irqStatus;          /* 0x0500 */
+    uint32_t  irqSet;             /* 0x0504 */
+    uint32_t  irqClear;           /* 0x0508 */
+    uint32_t  unused1;            /* 0x050c */
+    uint32_t  srqStatus;          /* 0x0510 */
+    uint32_t  srqSet;             /* 0x0514 */
+    uint32_t  srqClear;           /* 0x0518 */
+    uint32_t  unused2;            /* 0x051c */
+    uint32_t  drqStatus;          /* 0x0520 */
+    uint32_t  drqSet;             /* 0x0524 */
+    uint32_t  drqClear;           /* 0x0528 */
+    uint32_t  unused3;            /* 0x052c */
+    uint32_t  frqStatus;          /* 0x0530 */
+    uint32_t  frqSet;             /* 0x0534 */
+    uint32_t  frqClear;           /* 0x0538 */
+    uint32_t  unused4;            /* 0x053c */
+    uint32_t  hostIrqLatched;     /* 0x0540 */
+    uint32_t  hostIrqSet;         /* 0x0544 */
+    uint32_t  hostIrqClear;       /* 0x0548 */
+    uint32_t  hostIrqEnable;      /* 0x054c */
+    uint32_t  obusFaultStatus;    /* 0x0550 */
+    uint32_t  obusFaultClear;     /* 0x0554 */
+    uint32_t  obusFaultAddr;      /* 0x0558 */
+} CoreIntr;
+
+typedef struct CoreProfile {
+    uint32_t  mutex;              /* 0x0580 */
+    uint32_t  lastConfPcLo;       /* 0x0584 */
+    uint32_t  lastConfPcHi;       /* 0x0588 */
+    uint32_t  lastPcLo;           /* 0x058c */
+    uint32_t  lastPcHi;           /* 0x0590 */
+    uint32_t  braTargetPc0Lo;     /* 0x0594 */
+    uint32_t  braTargetPc0Hi;     /* 0x0598 */
+    uint32_t  braTargetPc1Lo;     /* 0x059c */
+    uint32_t  braTargetPc1Hi;     /* 0x05a0 */
+    uint32_t  braTargetPc2Lo;     /* 0x05a4 */
+    uint32_t  braTargetPc2Hi;     /* 0x05a8 */
+    uint32_t  braTargetPc3Lo;     /* 0x05ac */
+    uint32_t  braTargetPc3Hi;     /* 0x05b0 */
+    uint32_t  unused[3];          /* 0x05b4-0x05bf */
+    uint32_t  profSampleW[4];     /* 0x05c0 */
+} CoreProfile;
+
+typedef struct MaestroMisc {
+    CoreCtrl coreCtrl;          /* 0x0400 */
+    uint32_t   unused1[14];       /* 0x0448-0x047f */
+    CoreState coreState;        /* 0x0480 */
+    uint32_t   unused2[4];        /* 0x04f0-0x04ff */
+    CoreIntr interrupt;         /* 0x0500 */
+    uint32_t   unused3[9];        /* 0x055c-0x057f */
+    CoreProfile profile;        /* 0x0580 */
+} MaestroMisc;
+
+typedef struct Pmc {
+    uint32_t unused0[1030];
+    PmcCtrlReg ctrl;		            /* 0x1018 */
+    uint32_t unused1[622];	            /* 0x1148-0x1cff */
+    PmcDQMPac dqmPac;                   /* 0x1b00 */
+    uint32_t unused5[32];                 /* 0x1b80-0x1bff */
+    PmcDQMReg dqm;			            /* 0x1c00 */
+    uint32_t unused6[749];		        /* 0x1c4c-0x27ff */
+    uint32_t qStatus[32];		            /* 0x2800 */
+    uint32_t unused7[480];	            /* 0x2880-0x2fff */
+    PmcDqmQMibReg qMib;		            /* 0x3000 */
+    uint32_t unused8[928];	            /* 0x3180-0x3fff */
+    PmcDqmQCtrlReg dqmQCtrl[8]; 	    /* 0x4000 */
+    uint32_t unused9[992];                /* 0x4080-0x4fff */
+    PmcDqmQDataReg dqmQData[8]; 	    /* 0x5000 */
+} Pmc;
+
+#define PMC_BASE 0x80300000
+#define PMC ((volatile Pmc * const) PMC_BASE)
+
+typedef struct Procmon {
+    uint32_t unused00[256];
+    MaestroMisc maestroReg;             /* 0x00400 */
+    uint32_t unused10[32396];             /* 0x005d0-0x1ffff */
+    PmmReg  pmm;                        /* 0x20000 */
+    uint32_t unused11[22];                /* 0x20008-0x2005f */
+    SSBMaster ssbMasterCtrl;            /* 0x20060 */
+    uint32_t unused12[36];                /* 0x20070-0x200ff */
+    PmbBus pmb;                         /* 0x20100 */
+    uint32_t unused13[32576];             /* 0x20300-0x3ffff */
+    uint32_t qsm[128];                    /* 0x40000-0x401ff */
+    uint32_t unused14[65408];             /* 0x40200-0x7ffff */
+    uint32_t dtcm[1024];                  /* 0x80000-0x80fff */
+} Procmon;
+#define PROC_MON_BASE 0x80300000
+#define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
+
+typedef struct PMSSBMasterControl {
+        uint32_t control;
+        uint32_t wr_data;
+        uint32_t rd_data;
+} PMSSBMasterControl;
+
+typedef struct
+{
+    uint32_t  control;
+#define PMC_PMBM_START                      (1 << 31)
+#define PMC_PMBM_TIMEOUT                    (1 << 30)
+#define PMC_PMBM_SLAVE_ERR                  (1 << 29)
+#define PMC_PMBM_BUSY                       (1 << 28)
+#define PMC_PMBM_BUS_SHIFT              (20)
+#define PMC_PMBM_Read                       (0 << 24)
+#define PMC_PMBM_Write                      (1 << 24)
+    uint32_t  wr_data;
+    uint32_t  mutex;
+    uint32_t  rd_data;
+} PMB_keyhole_reg;
+
+typedef struct PMBMaster {
+    uint32_t config;
+#define PMB_NUM_REGS_SHIFT (20)
+#define PMB_NUM_REGS_MASK  (0x3ff)
+    uint32_t arbitger;
+    uint32_t timeout;
+    uint32_t reserved;
+    PMB_keyhole_reg keyhole[4];
+    uint32_t reserved1[44];
+    uint32_t map[64];
+} PMBMaster;
+#define PMB_BASE (0x80200000+0x00120100)
+#define PMB ((volatile PMBMaster * const) PMB_BASE)
+
+
+#define PERF_PHYS_BASE              0xff800000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63178/pmc_addr.h b/arch/arm/include/asm/arch-bcm63178/pmc_addr.h
new file mode 100644
index 0000000000..57f443b38d
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/pmc_addr.h
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ 
+*/
+
+#ifndef PMC_ADDR_63178_H__
+#define PMC_ADDR_63178_H__
+
+#define PMB_BUS_ID_SHIFT         12
+
+#define PMB_BUS_PERIPH           0
+#define PMB_ADDR_PERIPH          (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH         4
+
+#define PMB_BUS_CHIP_CLKRST      0
+#define PMB_ADDR_CHIP_CLKRST     (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST    0
+
+#define BPCM_CLKRST_AFE_PWRDWN   0x20000000
+
+#define PMB_BUS_AFEPLL           0
+#define PMB_ADDR_AFEPLL          (2 | PMB_BUS_AFEPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_AFEPLL         0
+
+#define AFEPLL_PMB_BUS_VDSL3_CORE       PMB_BUS_AFEPLL
+#define AFEPLL_PMB_ADDR_VDSL3_CORE      PMB_ADDR_AFEPLL
+#define AFEPLL_PMB_ZONES_VDSL3_CORE     PMB_ZONES_AFEPLL
+
+#define PMB_BUS_PVTMON           0
+#define PMB_ADDR_PVTMON          (3 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON         0
+
+#define PMB_BUS_SWITCH           0
+#define PMB_ADDR_SWITCH          (4 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SWITCH         4
+
+#define PMB_BUS_USB30_2X         0
+#define PMB_ADDR_USB30_2X        (5 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB30_2X       4
+
+#define PMB_BUS_PCIE0            1
+#define PMB_ADDR_PCIE0           (6 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0          1
+
+#define PMB_BUS_VDSL3_CORE       1
+#define PMB_ADDR_VDSL3_CORE      (7 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_VDSL3_CORE     2
+
+#define PMB_BUS_VDSL3_MIPS       PMB_BUS_VDSL3_CORE
+#define PMB_ADDR_VDSL3_MIPS      PMB_ADDR_VDSL3_CORE
+#define PMB_ZONES_VDSL3_MIPS     PMB_ZONES_VDSL3_CORE
+
+//--------- DGASP related bits/Offsets ------------------------
+#define BPCM_PHY_CNTL_OVERRIDE         0x08000000
+#define PMB_ADDR_VDSL_DGASP_PMD        PMB_ADDR_VDSL3_CORE
+#define BPCM_VDSL_PHY_CTL_REG	       vdsl_phy_ctl	// Alias for register containing DGASP override inside the VDSL PMD
+#define BPCM_VDSL_AFE_CTL_REG	       vdsl_afe_ctl	// Alias for register containing DGASP configuration inside the VDSL PMD
+
+#define PMB_BUS_MEMC             1
+#define PMB_ADDR_MEMC            (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC           1
+
+#define PMB_BUS_WLAN0_PHY1       0
+#define PMB_ADDR_WLAN0_PHY1      (9 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY1     1
+
+#define PMB_BUS_WLAN0_PHY2       0
+#define PMB_ADDR_WLAN0_PHY2      (10 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY2     1
+
+#define PMB_BUS_WLAN0            0
+#define PMB_ADDR_WLAN0           (11 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0          1
+
+#define PMB_BUS_ORION_CPU0       1
+#define PMB_ADDR_ORION_CPU0      (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0     1
+
+#define PMB_BUS_ORION_CPU1       1
+#define PMB_ADDR_ORION_CPU1      (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1     1
+
+#define PMB_BUS_ORION_CPU2       1
+#define PMB_ADDR_ORION_CPU2      (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU2     1
+
+#define PMB_BUS_ORION_NONCPU     1
+#define PMB_ADDR_ORION_NONCPU    (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU   1
+
+#define PMB_BUS_BIU_PLL          1
+#define PMB_ADDR_BIU_PLL         (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL        0
+
+#define PMB_BUS_BIU_BPCM         1
+#define PMB_ADDR_BIU_BPCM        (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM       1
+
+#define PMB_BUS_PCM              PMB_BUS_PERIPH
+#define PMB_ADDR_PCM             (0 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCM            4
+
+enum {
+	PCM_Zone_Main,
+	PCM_Zone_PCM = 3
+};
+//--------- SOFT Reset bits for PCM ------------------------
+#define   BPCM_PCM_SRESET_PCM_N       0x00000040
+
+#define RCAL_0P25UM_HORZ          0
+#define RCAL_0P25UM_VERT          1
+#define RCAL_0P5UM_HORZ           2
+#define RCAL_0P5UM_VERT           3
+#define RCAL_1UM_HORZ             4
+#define RCAL_1UM_VERT             5
+#define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
+#define PMMISC_RMON_VALID_MASK    (0x1<<16)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63178/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm63178/pmc_drv_cfg.h
new file mode 100644
index 0000000000..ed376309ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/pmc_drv_cfg.h
@@ -0,0 +1,40 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_3_X
+#define PMC_IMPL_3_2
+
+#define PMC_LOG_IN_DTCM         1
+#define PMC_GETRCAL_SUPPORT     1
+#define PMC_CPUTEMP_SUPPORT     1
+#define PMC_RAM_BOOT 1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm63178/rng.h b/arch/arm/include/asm/arch-bcm63178/rng.h
new file mode 100644
index 0000000000..6f4ca0c53c
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63178_RNG_H
+#define _63178_RNG_H
+
+#define RNG_BASE	0xff800b80
+
+typedef struct Rng {
+	uint32_t ctrl0;			/* 0x00 */
+	uint32_t rngSoftReset;		/* 0x04 */
+	uint32_t rbgSoftReset;		/* 0x08 */
+	uint32_t totalBitCnt;		/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;			/* 0x14 */
+	uint32_t intStatus;		/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL	(0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL	(0x1<<2)
+	uint32_t intEn;			/* 0x1c */
+	uint32_t rngFifoData;		/* 0x20 */
+	uint32_t fifoCnt;		/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS	0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS	0x33
+	uint32_t perm;			/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm63178/ubus4.h b/arch/arm/include/asm/arch-bcm63178/ubus4.h
new file mode 100644
index 0000000000..dc0f3e2179
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm63178/ubus4.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _63178_UBUS4_H
+#define _63718_UBUS4_H
+
+#define MST_PORT_NODE_PER_PHYS_BASE         0x83010000
+#define MST_PORT_NODE_USB_PHYS_BASE         0x83018000
+#define MST_PORT_NODE_CPU_PHYS_BASE         0x83020000
+#define MST_PORT_NODE_PMC_PHYS_BASE         0x83028000 
+#define MST_PORT_NODE_PCIE0_PHYS_BASE       0x83030000
+#define MST_PORT_NODE_SWH_PHYS_BASE         0x83038000
+#define MST_PORT_NODE_WIFI_PHYS_BASE        0x83050000
+#define MST_PORT_NODE_DSL_PHYS_BASE         0x83060000
+#define MST_PORT_NODE_DSLCPU_PHYS_BASE      0x83068000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6756/BPCM.h b/arch/arm/include/asm/arch-bcm6756/BPCM.h
new file mode 100644
index 0000000000..9507387edd
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/BPCM.h
@@ -0,0 +1,761 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t sw_strap:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+// types of PMB devices
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu_reset_n:8;	// 07:00    R/W
+		uint32_t c0l2_reset:1;	// 08:08    R/W
+		uint32_t c1l2_reset:1;	// 09:09    R/W
+		uint32_t reserved0:6;	// 15:10    R/O
+		uint32_t cpu_bpcm_init_on:8;	// 23:16    R/W
+		uint32_t c0l2_bpcm_init_on:1;	// 24:24    R/W
+		uint32_t c1l2_bpcm_init_on:1;	// 25:25    R/W
+		uint32_t ubus_sr:1;	// 26:26    R/W
+		uint32_t cci_sr:1;	// 27:27    R/W
+		uint32_t webcores_sr:1;	// 28:28    R/W
+		uint32_t hw_done:1;	// 29:29    R/O
+		uint32_t sw_done:1;	// 30:30    R/W
+		uint32_t start:1;	// 31:31    R/W
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t reserved0:2;	// 11:10
+		uint32_t ndiv_frac:20;	// 31:12    
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECNDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t reserved0:12;	// 15:04
+		uint32_t mdiv0:8;	// 23:16
+		uint32_t mdiv1:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECPDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv2:8;	// 07:00
+		uint32_t mdiv3:8;	// 15:08
+		uint32_t mdiv4:8;	// 23:16
+		uint32_t mdiv5:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECCH25_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	uint32_t reserved0;
+	uint32_t timer_control;
+	uint32_t timer_status;
+	uint32_t reserved1[2];
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+typedef union {
+	struct {
+		uint32_t ubus_soft_rst:1;
+		uint32_t alt_ubus_clk_sel:1;
+		uint32_t obsv_clk_swinit:1;
+		uint32_t reserved0:17;
+		uint32_t wl0_rf_enable:1;
+		uint32_t wl1_rf_enable:1;
+		uint32_t reserved1:10;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CLKRST_CONTROL;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	// BPCM
+	uint32_t control;	// offset 0x10, PMB reg index 4
+	BPCM_SR_CONTROL sr_control;	// offset 0x14, PMB reg index 5
+	uint32_t reserved1[2];	// offset 0x18, PMB reg index 6/7
+	// Client-specific registers
+	uint32_t client_specific[24];	// offset 0x20, PMB reg index 8..31
+	// Zones
+	BPCM_ZONE zones[];	// offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1))
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCM_OFFSET(reg) (offsetof(BPCM_REGS,reg)>>2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	uint32_t rvrsd[2];
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_VDSL_REGS;		// total offset space = 4096
+
+#define BPCMVDSLOffset(reg)	offsetof(BPCM_VDSL_REGS,reg)
+#define BPCMVDSLRegOffset(reg)	(BPCMVDSLOffset(reg) >> 2)
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08, actual offset = 2
+	uint32_t cfg_control;	// offset = 0x10, actual offset = 4
+	BPCM_SR_CONTROL sr_control;	// offset = 0x14, actual offset = 5
+	uint32_t reserved1[6];	// offset = 0x18, actual offset = 6
+	ARM_CONTROL_REG arm_control;	// offset = 0x30, actual offset = 12
+	uint32_t biu_clk_control0;	// offset = 0x34, actual offset = 13
+	uint32_t tbd[18];	// offset = 0x38, actual offset = 14
+	BPCM_ZONE zones;	// offset = 0x80, actual offset = 32
+} ARM_BPCM_REGS;
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	PLL_DECNDIV_REG decndiv;	// offset = 0x44, actual offset = 0x11
+	PLL_DECPDIV_REG decpdiv;	// offset = 0x48, actual offset = 0x12
+	PLL_DECCH25_REG decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[7];	// offset 0x08-0x20, PMB reg index 2-8
+	uint32_t control;	// offset 0x24, PMB reg index 9
+	uint32_t observe_cntrl;	// offset 0x28, PMB reg index 10
+	uint32_t observe_div;	// offset 0x2c, PMB reg index 11
+	uint32_t observe_enable;	// offset 0x30, PMB reg index 12
+	BPCM_CLKRST_CONTROL clkrst_control;	// offset 0x34, PMB reg index 13
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	// BPCM
+	uint32_t control;	// offset 0x10, PMB reg index 4
+	BPCM_SR_CONTROL sr_control;	// offset 0x14, PMB reg index 5
+
+	uint32_t z0_pm_cntl;	// offset 0x18
+	uint32_t z0_pm_status;	// offset 0x1c
+	uint32_t z1_pm_cntl;	// offset 0x20
+	uint32_t z2_pm_cntl;	// offset 0x24
+	uint32_t reserved1[22];	// reserved from 0x28 to 0x7F
+	BPCM_ZONE zones[];
+
+} BPCM_SYSPORT_REGS;
+
+#define SYSPOffset(reg)		offsetof(BPCM_SYSPORT_REGS,reg)
+#define SYSPRegOffset(reg)	(SYSPOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6756/brom.h b/arch/arm/include/asm/arch-bcm6756/brom.h
new file mode 100644
index 0000000000..206301816b
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6756_BROM_H
+#define _6756_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6756/cpu.h b/arch/arm/include/asm/arch-bcm6756/cpu.h
new file mode 100644
index 0000000000..14dafa6f61
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/cpu.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6756_CPU_H
+#define _6756_CPU_H
+
+#define BOOTLUT_BASE	0xffff0000
+
+#define BIUCFG_BASE	0x81060000
+#define CCI500_BASE	0x81100000
+
+typedef struct BIUCFG_Access {
+	uint32_t permission;	/* 0x0 */
+	uint32_t sbox;		/* 0x4 */
+	uint32_t cpu_defeature;	/* 0x8 */
+	uint32_t dbg_security;	/* 0xc */
+	uint32_t rsvd1[32];	/* 0x10 - 0x8f */
+	uint64_t violation[2];	/* 0x90 - 0x9f */
+	uint32_t ts_access[2];	/* 0xa0 - 0xa7 */
+	uint32_t rsvd2[22];	/* 0xa8 - 0xff */
+} BIUCFG_Access;
+
+typedef struct BIUCFG_Cluster {
+	uint32_t permission;	/* 0x0 */
+	uint32_t config;	/* 0x4 */
+	uint32_t status;	/* 0x8 */
+	uint32_t control;	/* 0xc */
+	uint32_t cpucfg;	/* 0x10 */
+	uint32_t dbgrom;	/* 0x14 */
+	uint32_t rsvd1[2];	/* 0x18 - 0x1f */
+	uint32_t rvbar_addr[4];	/* 0x20 - 0x2f */
+	uint32_t rsvd2[52];	/* 0x30 - 0xff */
+} BIUCFG_Cluster;
+
+typedef struct BIUCFG_AuxClkCtrl {
+	uint32_t clk_control;	/* 0x0 */
+	uint32_t clk_ramp;	/* 0x4 */
+	uint32_t clk_pattern;	/* 0x8 */
+	uint32_t rsvd;		/* 0xC */
+} BIUCFG_AuxClkCtrl;
+
+typedef struct BIUCFGux {
+	uint32_t permission;	/* 0 */
+	uint32_t rsvd1[3];	/* 0x04 - 0x0c */
+	BIUCFG_AuxClkCtrl cluster_clkctrl[2];	/* 0x10 - 0x2c */
+	uint32_t rsvd2[52];	/* 0x30 - 0xFF */
+} BIUCFG_Aux;
+
+typedef struct BIUCFG_Bac {
+	uint32_t bac_permission;	/* 0x00 */
+	uint32_t bac_periphbase;	/* 0x04 */
+	uint32_t rsvd[2];		/* 0x08 - 0x0f */
+	uint32_t bac_event;		/* 0x10 */
+	uint32_t rsvd_1[3];		/* 0x14 - 0x1f */
+	uint32_t bac_ccicfg;		/* 0x20 */
+	uint32_t bac_cciaddr;		/* 0x24 */
+	uint32_t rsvd_2[4];		/* 0x28 - 0x37 */
+	uint32_t bac_ccievs2;		/* 0x38 */
+	uint32_t bac_ccievs3;		/* 0x3c */
+	uint32_t bac_ccievs4;		/* 0x40 */
+	uint32_t rsvd_3[3];		/* 0x44 - 0x4f */
+	uint32_t bac_ccievm0;		/* 0x50 */
+	uint32_t bac_ccievm1;		/* 0x54 */
+	uint32_t rsvd_4[2];		/* 0x58 - 0x5f */
+	uint32_t bac_dapapbcfg;		/* 0x60 */
+	uint32_t bac_status;		/* 0x64 */
+	uint32_t rsvd_5[2];		/* 0x68 - 0x6f */
+	uint32_t cpu_therm_irq_cfg; 	/* 0x70 */
+	uint32_t cpu_therm_threshold_cfg; /* 0x74 */
+	uint32_t rsvd_6;		/* 0x78 */
+	uint32_t cpu_therm_temp;	/* 0x7c */
+	uint32_t rsvd_7[32];		/* 0x80 - 0xff */
+} BIUCFG_Bac;
+
+typedef struct BIUCFG {
+	BIUCFG_Access access;	/* 0x0 - 0xff */
+	BIUCFG_Cluster cluster[2];	/* 0x100 - 0x2ff */
+	BIUCFG_Bac bac;		/* 0x300 - 0x3ff */
+	uint32_t rsvd1[192];	/* 0x400 - 0x6ff */
+	BIUCFG_Aux aux;		/* 0x700 - 0x7ff */
+	uint32_t rsrvd2[512];	/* 0x800 - 0xfff */
+	uint32_t TSO_CNTCR;	/* 0x1000 */
+	uint32_t rsvd2[2047];	/* 0x1004 - 0x2fff */
+} BIUCFG;
+
+#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
+
+typedef struct CCI500_SlaveIntf {
+#define SNOOP_CTRL_ENABLE_SNOOP		0x1
+	uint32_t snoop_ctrl;		/* 0x0 */
+#define SHARE_OVR_SHAREABLE_OVR_SHIFT	0x0
+#define SHARE_OVR_SHAREABLE_OVR_MASK	0x3
+#define SHARE_OVR_SHAREABLE_OVR_NONSHR	0x2
+#define SHARE_OVR_SHAREABLE_OVR_SHR	0x3
+	uint32_t share_ovr;		/* 0x4 */
+	uint32_t rsvd1[62];		/* 0x8 - 0xff */
+	uint32_t arqos_ovr;		/* 0x100 */
+	uint32_t awqos_ovr;		/* 0x104 */
+	uint32_t rsvd2[2];		 /* 0x108 - 0x10f */
+	uint32_t qos_max_ot;		/* 0x110 */
+	uint32_t rsvd3[955];		/* 0x114 - 0xfff */
+}CCI500_SlaveIntf;
+
+typedef struct CCI500_EventCounter {
+	uint32_t sel;	/* 0x0 */
+	uint32_t data;	/* 0x4 */
+	uint32_t ctrl;	/* 0x8 */
+	uint32_t clr_ovfl;/* 0xC */
+	uint32_t rsvd[16380];/* 0x10 - 0xffff */
+}CCI500_EventCounter;
+
+typedef struct CCI500 {
+#define CONTROL_OVERRIDE_SNOOP_DISABLE	0x1
+#define CONTROL_OVERRIDE_SNOOP_FLT_DISABLE 0x4
+	uint32_t ctrl_ovr;	/* 0x0 */
+	uint32_t rsvd1;		/* 0x4 */
+#define SECURE_ACCESS_UNSECURE_ENABLE	0x1
+	uint32_t secr_acc;	/* 0x8 */
+	uint32_t status;	 /* 0xc */
+#define STATUS_CHANGE_PENDING		0x1
+	uint32_t impr_err;	/* 0x10 */
+	uint32_t qos_threshold;	/* 0x14 */
+	uint32_t rsvd2[58];	/* 0x18 - 0xff */
+	uint32_t pmu_ctrl;	/* 0x100 */
+#define DBG_CTRL_EN_INTF_MON		0x1
+	uint32_t debug_ctrl;	/* 0x104 */
+	uint32_t rsvd3[958];	/* 0x108 - 0xfff */
+#define SLAVEINTF_COHERENCY_PORT	0x0
+#define SLAVEINTF_CPU_CLUSTER		0x1
+	CCI500_SlaveIntf si[7];	/* 0x1000 - 0x7fff */
+	uint32_t rsvd4[8192];	/* 0x8000 - 0xffff */
+	CCI500_EventCounter evt_cntr[8]; /* 0x10000 - 0x8ffff */
+}CCI500;
+#define CCI500 ((volatile CCI500 * const) CCI500_BASE)
+
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6756/ddr.h b/arch/arm/include/asm/arch-bcm6756/ddr.h
new file mode 100644
index 0000000000..450215968b
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/ddr.h
@@ -0,0 +1,616 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6756_DDR_H
+#define _6756_DDR_H
+
+#define MEMC_BASE	0x80180000	/* DDR IO Buf Control */
+
+typedef struct AXIInterface {
+	uint32_t CFG;			/* 0x00 */
+	uint32_t REP_ARB_MODE;		/* 0x04 */
+	uint32_t QUEUE_CFG;		/* 0x08 */
+	uint32_t ESRCID_CFG;		/* 0x0c */
+	uint32_t SRC_QUEUE_CTRL[8];	/* 0x10 */
+	uint32_t SRC_ID_4_QUEUE_CTRL;	/* 0x30 */
+	uint32_t SCRATCH;		/* 0x34 */
+	uint32_t AXI_DEBUG[2];		/* 0x38 */
+} AXIInterface;
+
+typedef struct EDISEngine {
+	uint32_t REV_ID;		/* 0x00 */
+	uint32_t CTRL_TRIG;		/* 0x04 */
+	uint32_t CTRL_MODE;		/* 0x08 */
+	uint32_t CTRL_SIZE;		/* 0x0c */
+	uint32_t CTRL_ADDR_START;	/* 0x10 */
+	uint32_t CTRL_ADDR_START_EXT;	/* 0x14 */
+	uint32_t CTRL_ADDR_END;		/* 0x18 */
+	uint32_t CTRL_ADDR_END_EXT;	/* 0x1c */
+	uint32_t CTRL_WRITE_MASKS;	/* 0x20 */
+	uint32_t CTRL_INT_ENABLES;	/* 0x24 */
+	uint32_t unused0[6];		/* 0x28-0x3f */
+	uint32_t STAT_MAIN;		/* 0x40 */
+	uint32_t STAT_WORDS_WRITTEN;	/* 0x44 */
+	uint32_t STAT_WORDS_READ;	/* 0x48 */
+	uint32_t STAT_ERROR_COUNT;	/* 0x4c */
+	uint32_t STAT_ERROR_BITS;	/* 0x50 */
+	uint32_t STAT_ADDR_LAST;	/* 0x54 */
+	uint32_t STAT_ADDR_LAST_EXT;	/* 0x58 */
+	uint32_t STAT_CLOCK_CYCLES;	/* 0x5c */
+	uint32_t unused1[7];		/* 0x60-0x7b */
+	uint32_t STAT_DEBUG;		/* 0x7c */
+	uint32_t STAT_DATA_PORT[8];	/* 0x80-0x9c */
+	uint32_t GEN_LFSR_STATE[4];	/* 0xa0-0xac */
+	uint32_t GEN_CLOCK;		/* 0xb0 */
+	uint32_t GEN_PATTERN;		/* 0xb4 */
+	uint32_t unused2[2];		/* 0xb8-0xbf */
+	uint32_t BYTELANE_0_CTRL_LO;	/* 0xc0 */
+	uint32_t BYTELANE_0_CTRL_HI;	/* 0xc4 */
+	uint32_t BYTELANE_1_CTRL_LO;	/* 0xc8 */
+	uint32_t BYTELANE_1_CTRL_HI;	/* 0xcc */
+	uint32_t BYTELANE_2_CTRL_LO;	/* 0xd0 */
+	uint32_t BYTELANE_2_CTRL_HI;	/* 0xd4 */
+	uint32_t BYTELANE_3_CTRL_LO;	/* 0xd8 */
+	uint32_t BYTELANE_3_CTRL_HI;	/* 0xdc */
+	uint32_t BYTELANE_0_STAT_LO;	/* 0xe0 */
+	uint32_t BYTELANE_0_STAT_HI;	/* 0xe4 */
+	uint32_t BYTELANE_1_STAT_LO;	/* 0xe8 */
+	uint32_t BYTELANE_1_STAT_HI;	/* 0xec */
+	uint32_t BYTELANE_2_STAT_LO;	/* 0xf0 */
+	uint32_t BYTELANE_2_STAT_HI;	/* 0xf4 */
+	uint32_t BYTELANE_3_STAT_LO;	/* 0xf8 */
+	uint32_t BYTELANE_3_STAT_HI;	/* 0xfc */
+} EDISEngine;
+
+typedef struct RangeCtrl {
+	uint32_t CTRL;			/* 0x00 */
+	uint32_t UBUS0_PORT;		/* 0x04 */
+	uint32_t UBUS0_PORT_UPPER;	/* 0x08 */
+	uint32_t BASE;			/* 0x0c */
+	uint32_t BASE_UPPER;		/* 0x10 */
+	uint32_t SECLEC_EN;		/* 0x14 */
+} RangeCtrl;
+
+typedef struct SecureRangeCheckers {
+	uint32_t LOCK;			/* 0x00 */
+	uint32_t LOG_INFO[3];		/* 0x04 - 0x0c */
+	RangeCtrl RANGE_CTRL[8];	/* 0x10 - 0xcf */
+	uint32_t unused[12];		/* 0xd0 - 0xff */
+} SecureRangeCheckers;
+
+typedef struct DDRPhyControl {
+	uint32_t PRIMARY_REVISION;	/* 0x00 */
+	uint32_t SECONDARY_REVISION;	/* 0x04 */
+	uint32_t FEATURE;		/* 0x08 */
+	uint32_t PLL_STATUS;		/* 0x0c */
+	uint32_t PLL_CONFIG;		/* 0x10 */
+	uint32_t PLL_CONTROL1;		/* 0x14 */
+	uint32_t PLL_CONTROL2;		/* 0x18 */
+	uint32_t PLL_CONTROL3;		/* 0x1c */
+	uint32_t PLL_DIVIDER;		/* 0x20 */
+	uint32_t PLL_PRE_DIVIDER;	/* 0x24 */
+	uint32_t PLL_SS_EN;		/* 0x28 */
+	uint32_t PLL_SS_CFG;		/* 0x2c */
+	uint32_t AUX_CONTROL;		/* 0x30 */
+	uint32_t IDLE_PAD_CONTROL;	/* 0x34 */
+	uint32_t IDLE_PAD_EN0;		/* 0x38 */
+	uint32_t IDLE_PAD_EN1;		/* 0x3c */
+	uint32_t DRIVE_PAD_CTL;		/* 0x40 */
+	uint32_t DRIVE_PAD_CTL_2T;	/* 0x44 */
+	uint32_t DRIVE_PAD_CTL_2T_A;	/* 0x48 */
+	uint32_t STATIC_PAD_CTL;	/* 0x4c */
+	uint32_t STATIC_PAD_CTL_2T;	/* 0x50 */
+	uint32_t STATIC_PAD_CTL_2T_A;	/* 0x54 */
+	uint32_t RX_TRIM;		/* 0x58 */
+	uint32_t DRAM_CFG;		/* 0x5c */
+	uint32_t DRAM_TIMING2;		/* 0x60 */
+	uint32_t DRAM_TIMING3;		/* 0x64 */
+	uint32_t VDL_REGS[45];		/* 0x68-0x11b */
+	uint32_t UPDATE_VDL;		/* 0x11c */
+	uint32_t UPDATE_VDL_SNOOP1;	/* 0x120 */
+	uint32_t UPDATE_VDL_SNOOP2;	/* 0x124 */
+	uint32_t CMND_REG1;		/* 0x128 */
+	uint32_t CMND_AUX_REG1;		/* 0x12c */
+	uint32_t CMND_REG2;		/* 0x130 */
+	uint32_t CMND_AUX_REG2;		/* 0x134 */
+	uint32_t CMND_REG3;		/* 0x138 */
+	uint32_t CMND_AUX_REG3;		/* 0x13c */
+	uint32_t CMND_REG4;		/* 0x140 */
+	uint32_t CMND_AUX_REG4;		/* 0x144 */
+	uint32_t MODE_REG[8];		/* 0x148-167 */
+	uint32_t ALERT_CLEAR;		/* 0x168 */
+	uint32_t ALERT_STATUS;		/* 0x16c */
+	uint32_t ALERT_DF1;		/* 0x170 */
+	uint32_t WRITE_LEVEL_CTRL;	/* 0x174 */
+	uint32_t WRITE_LEVEL_STATUS;	/* 0x178 */
+	uint32_t READ_EN_CTRL;		/* 0x17c */
+	uint32_t READ_EN_STATUS;	/* 0x180 */
+	uint32_t VIRT_VTT_CTRL;		/* 0x184 */
+	uint32_t VIRT_VTT_STATUS;	/* 0x188 */
+	uint32_t VIRT_VTT_CONNECTION;	/* 0x18c */
+	uint32_t VIRT_VTT_OVERRIDE;	/* 0x190 */
+	uint32_t VREF_DAC_CTRL;		/* 0x194 */
+#define DDRPHY_VREF_DAC_CTRL_PDN_SHIFT             12
+#define DDRPHY_VREF_DAC_CTRL_PDN_MASK              (0xf << DDRPHY_VREF_DAC_CTRL_PDN_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT            6
+#define DDRPHY_VREF_DAC_CTRL_DAC1_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT            0
+#define DDRPHY_VREF_DAC_CTRL_DAC0_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT)
+	uint32_t STANDBY_CTRL;		/* 0x198 */
+	uint32_t DEBUG_FREEZE_EN;	/* 0x19c */
+	uint32_t DEBUG_MUX_CTRL;	/* 0x1a0 */
+	uint32_t DFI_CTRL;		/* 0x1a4 */
+	uint32_t WRITE_ODT_CTRL;	/* 0x1a8 */
+	uint32_t ABI_PAR_CTRL;		/* 0x1ac */
+	uint32_t ZQ_CAL;		/* 0x1b0 */
+	uint32_t ZQ_CAL2;		/* 0x1b4 */
+	uint32_t unused6[14];		/* 0x1b8-0x1ef */
+	uint32_t CLOCK_IDLE;		/* 0x1f0 */
+	uint32_t unused7[131];		/* 0x1f4-0x3ff */
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+	uint32_t VDL_CTRL_WR[10];	/* 0x00 - 0x27 */
+	uint32_t VDL_CTRL_RD[22];	/* 0x28 - 0x7f */
+	uint32_t VDL_CLK_CTRL;		/* 0x80 */
+	uint32_t VDL_LDE_CTRL;		/* 0x84 */
+	uint32_t RD_EN_DLY_CYC;		/* 0x88 */
+#define RD_EN_DLY_CYC_CS0_CYCLES_SHIFT      0x0
+#define RD_EN_DLY_CYC_CS0_CYCLES_MASK       (0xf<<RD_EN_DLY_CYC_CS0_CYCLES_SHIFT)
+	uint32_t WR_CHAN_DLY_CYC;	/* 0x8c */
+	uint32_t RD_CTRL;		/* 0x90 */
+	uint32_t RD_FIFO_ADDR;		/* 0x94 */
+	uint32_t RD_FIFO_DATA;		/* 0x98 */
+	uint32_t RD_FIFO_DM_DBI;	/* 0x9c */
+	uint32_t RD_FIFO_STATUS;	/* 0xa0 */
+	uint32_t RD_FIFO_CLR;		/* 0xa4 */
+	uint32_t DYNAMIC_CLK_CTRL;	/* 0xa8 */
+	uint32_t IDLE_PAD_CTRL;		/* 0xac */
+	uint32_t DRIVE_PAD_CTRL;	/* 0xb0 */
+	uint32_t DQSP_DRIVE_PAD_CTRL;	/* 0xb4 */
+	uint32_t DQSN_DRIVE_PAD_CTRL;	/* 0xb8 */
+	uint32_t RD_EN_DRIVE_PAD_CTRL;	/* 0xbc */
+	uint32_t STATIC_PAD_CTRL;	/* 0xc0 */
+	uint32_t DQ_RX_TRIM;		/* 0xc4 */
+	uint32_t MISC_RX_TRIM;		/* 0xc8 */
+	uint32_t DQS_RX_TRIM;		/* 0xcc */
+	uint32_t WR_PREAMBLE_MODE;	/* 0xd0 */
+	uint32_t ODT_CTRL;		/* 0xd4 */
+	uint32_t LDO_CONFIG;		/* 0xd8 */
+	uint32_t CLOCK_ENABLE;		/* 0xdc */
+	uint32_t CLOCK_IDLE;		/* 0xe0 */
+	uint32_t RD_CHAN_FIFO_CLR;	/* 0xe4 */
+	uint32_t BL_SPARE_REG;		/* 0xe8 */
+	uint32_t unused[69];		/* 0xec-0x1ff */
+} DDRPhyByteLaneControl;
+
+
+typedef struct MEMCControl {
+	uint32_t GLB_VERS;		/* 0x000 */
+	uint32_t GLB_GCFG;		/* 0x004 */
+#define MEMC_GLB_GCFG_DRAM_EN_SHIFT        31
+#define MEMC_GLB_GCFG_DRAM_EN_MASK         (0x1<<MEMC_GLB_GCFG_DRAM_EN_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ_SHIFT      30
+#define MEMC_GLB_GCFG_FORCE_SEQ_MASK       (0x1<<MEMC_GLB_GCFG_FORCE_SEQ_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT     29
+#define MEMC_GLB_GCFG_FORCE_SEQ2_MASK      (1<<MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT)
+#define MEMC_GLB_GCFG_RBF_REORDER_SHIFT    28
+#define MEMC_GLB_GCFG_RBF_REORDER_MASK     (1<<MEMC_GLB_GCFG_RBF_REORDER_SHIFT)
+#define MEMC_GLB_GCFG_SREF_SLOW_CLK_SHIFT  26
+#define MEMC_GLB_GCFG_SREF_SLOW_CLK_MASK   (1<<MEMC_GLB_GCFG_SREF_SLOW_CLK_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT   24
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_MASK    (0x3<<MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_2X           0x0
+#define MEMC_GLB_GCFG_PHY_DFI_4X           0x1
+#define MEMC_GLB_GCFG_PHY_DFI_8X           0x2
+#define MEMC_GLB_GCFG_ALT_CHN_ARB_SHIFT    21
+#define MEMC_GLB_GCFG_ALT_CHN_ARB_MASK     (0x1<<MEMC_GLB_GCFG_ALT_CHN_ARB_SHIFT)
+#define MEMC_GLB_GCFG_DFI_EN_SHIFT         10
+#define MEMC_GLB_GCFG_DFI_EN_MASK          (0x1<<MEMC_GLB_GCFG_DFI_EN_SHIFT)
+#define MEMC_GLB_GCFG_MCLKSRC_SHIFT        9
+#define MEMC_GLB_GCFG_MCLKSRC_MASK         (0x1<<MEMC_GLB_GCFG_MCLKSRC_SHIFT)
+#define MEMC_GLB_GCFG_MEMINITDONE_SHIFT    8
+#define MEMC_GLB_GCFG_MEMINITDONE_MASK     (0x1<<MEMC_GLB_GCFG_MEMINITDONE_SHIFT)
+#define MEMC_GLB_GCFG_MRQSIZE_SHIFT        0
+#define MEMC_GLB_GCFG_MRQSIZE_MASK         (0x1f<<MEMC_GLB_GCFG_MRQSIZE_SHIFT)
+	uint32_t GLB_MRQ_CFG;		/* 0x008 */
+	uint32_t unused0;		/* 0x00c */
+	uint32_t GLB_FSBL_STATE;	/* 0x010 */
+#define MEMC_GLB_FSBL_DRAM_SIZE_SHIFT      0
+#define MEMC_GLB_FSBL_DRAM_SIZE_MASK       (0xf << MEMC_GLB_FSBL_DRAM_SIZE_SHIFT)
+	uint32_t unused1[3];		/* 0x014 - 0x01f */
+
+	uint32_t SRAM_REMAP_CTRL;	/* 0x020 */
+	uint32_t SRAM_REMAP_CTRL_UPPER;	/* 0x024 */
+	uint32_t SRAM_REMAP_INIT;	/* 0x028 */
+	uint32_t SRAM_REMAP_LOG_INFO_0;	/* 0x02c */
+	uint32_t SRAM_REMAP_LOG_INFO_1;	/* 0x030 */
+	uint32_t SRAM_REMAP_LOG_INFO_2;	/* 0x034 */
+	uint32_t unused2[2];		/* 0x038-0x03f */
+
+	uint32_t RBF_REORDER_0_CFG[16];	/* 0x040 - 0x07f */
+
+	uint32_t INTR2_CPU_STATUS;	/* 0x080 */
+	uint32_t INTR2_CPU_SET;		/* 0x084 */
+	uint32_t INTR2_CPU_CLEAR;	/* 0x088 */
+	uint32_t INTR2_CPU_MASK_STATUS;	/* 0x08c */
+	uint32_t INTR2_CPU_MASK_SET;	/* 0x090 */
+	uint32_t INTR2_CPU_MASK_CLEAR;	/* 0x094 */
+	uint32_t unused3[26];		/* 0x098-0x0ff */
+
+	uint32_t CHN_CFG_CNFG;		/* 0x100 */
+#define MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT            16
+#define MEMC_CHN_CFG_CNFG_CS_MODE_MASK             (0x3 << MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT)
+	uint32_t CHN_CFG_CSST;		/* 0x104 */
+	uint32_t unused4[2];		/* 0x108-0x10f */
+	uint32_t CHN_CFG_ROW00_0;	/* 0x110 */
+	uint32_t CHN_CFG_ROW00_1;	/* 0x114 */
+	uint32_t CHN_CFG_ROW01_0;	/* 0x118 */
+	uint32_t CHN_CFG_ROW01_1;	/* 0x11c */
+	uint32_t CHN_CFG_ROW02_0;	/* 0x120 */
+	uint32_t CHN_CFG_COL00_0;	/* 0x124 */
+	uint32_t CHN_CFG_COL00_1;	/* 0x128 */
+	uint32_t CHN_CFG_COL01_0;	/* 0x12c */
+	uint32_t CHN_CFG_COL01_1;	/* 0x130 */
+	uint32_t CHN_CFG_BNK10;		/* 0x134 */
+	uint32_t CHN_CFG_BG0;		/* 0x138 */
+	uint32_t unused5;		/* 0x13c */
+	uint32_t CHN_CFG_DRAM_SZ_CHK;	/* 0x140 */
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT  4
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_MASK   (0xf<<MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT)
+	uint32_t CHN_CFG_DIAG_SEL;	/* 0x144 */
+	uint32_t unused6[46];		/* 0x148-0x1ff */
+
+	uint32_t CHN_TIM_DCMD;		/* 0x200 */
+	uint32_t CHN_TIM_DMODE_0;	/* 0x204 */
+	uint32_t CHN_TIM_DMODE_2;	/* 0x208 */
+	uint32_t CHN_TIM_CLKS;		/* 0x20c */
+#define MEMC_CHN_TIM_CLKS_REF_RATE_SHIFT          8
+#define MEMC_CHN_TIM_CLKS_REF_DISABLE_SHIFT       31
+	uint32_t CHN_TIM_ODT;		/* 0x210 */
+	uint32_t CHN_TIM_TIM1_0;	/* 0x214 */
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tWL [31:24] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_MASK                            0xff000000
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_SHIFT                           24
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_DEFAULT                         0x00000004
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRP [23:16] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_MASK                            0x00ff0000
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_SHIFT                           16
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_DEFAULT                         0x00000006
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tCL [15:08] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_MASK                            0x0000ff00
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_SHIFT                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_DEFAULT                         0x00000005
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRCD [07:00] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_MASK                           0x000000ff
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_ALIGN                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_BITS                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_SHIFT                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_DEFAULT                        0x00000006
+
+	uint32_t CHN_TIM_TIM1_1;	/* 0x218 */
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_L [31:24] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_S [23:16] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_L [15:08] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_MASK                         0x0000ff00
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_SHIFT                        8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_S [07:00] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_MASK                         0x000000ff
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_SHIFT                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_DEFAULT                      0x00000002
+
+	uint32_t CHN_TIM_TIM1_2;	/* 0x21c */
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tFAW [31:24] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_MASK                           0xff000000
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_SHIFT                          24
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_DEFAULT                        0x00000000
+/* MC_CHN_TIM :: TIM1_2 :: reserved0 [23:16] */
+#define MC_CHN_TIM_TIM1_2_reserved0_MASK                           0x00ff0000
+#define MC_CHN_TIM_TIM1_2_reserved0_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_reserved0_BITS                           8
+#define MC_CHN_TIM_TIM1_2_reserved0_SHIFT                          16
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRTP [15:08] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_MASK                           0x0000ff00
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_SHIFT                          8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_DEFAULT                        0x00000002
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRC [07:00] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_ALIGN                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_BITS                            8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_SHIFT                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_DEFAULT                         0x00000011
+
+	uint32_t CHN_TIM_TIM1_3;	/* 0x220 */
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_L [31:24] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_S [23:16] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: reserved_for_padding0 [15:12] */
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_MASK               0x0000f000
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_ALIGN              0
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_BITS               4
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_SHIFT              12
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_L [11:08] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_MASK                          0x00000f00
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_BITS                          4
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_SHIFT                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_DEFAULT                       0x00000004
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_S [07:00] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_MASK                          0x000000ff
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_BITS                          8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_SHIFT                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_DEFAULT                       0x00000004
+
+	uint32_t CHN_TIM_TIM2;		/* 0x224 */
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2R [31:30] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_MASK                             0xc0000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_BITS                             2
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_SHIFT                            30
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2W [29:27] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_MASK                             0x38000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_SHIFT                            27
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2R [26:24] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_MASK                             0x07000000
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_SHIFT                            24
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: reserved_for_padding0 [23:22] */
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_MASK                 0x00c00000
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_ALIGN                0
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_BITS                 2
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_SHIFT                22
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2W [21:18] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_MASK                             0x003c0000
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_BITS                             4
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_SHIFT                            18
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: reserved1 [17:16] */
+#define MC_CHN_TIM_TIM2_reserved1_MASK                             0x00030000
+#define MC_CHN_TIM_TIM2_reserved1_ALIGN                            0
+#define MC_CHN_TIM_TIM2_reserved1_BITS                             2
+#define MC_CHN_TIM_TIM2_reserved1_SHIFT                            16
+/* MC_CHN_TIM :: TIM2 :: TIM2_tAL [15:12] */
+#define MC_CHN_TIM_TIM2_TIM2_tAL_MASK                              0x0000f000
+#define MC_CHN_TIM_TIM2_TIM2_tAL_ALIGN                             0
+#define MC_CHN_TIM_TIM2_TIM2_tAL_BITS                              4
+#define MC_CHN_TIM_TIM2_TIM2_tAL_SHIFT                             12
+#define MC_CHN_TIM_TIM2_TIM2_tAL_DEFAULT                           0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tRFC [11:00] */
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_MASK                             0x00000fff
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_BITS                             12
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_SHIFT                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_DEFAULT                          0x00000014
+
+	uint32_t unused7[2];		/* 0x228 - 0x22f */
+	uint32_t CHN_TIM_PHY_ST;	/* 0x230 */
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP       0x1
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_HW_RESET       0x2
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_SW_RESET       0x4
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_READY          0x10
+	uint32_t CHN_TIM_DRAM_CFG;	/* 0x234 */
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT           12
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_MASK            (0x1<<MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT     10
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_MASK      (0x1<<MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT      0
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_MASK       (0xf<<MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT)
+#define MC_DRAM_CFG_DDR3                          0x1
+#define MC_DRAM_CFG_DDR4                          0x2
+	uint32_t CHN_TIM_STAT;		/* 0x238 */
+	uint32_t CHN_TIM_PERF;		/* 0x23c */
+
+	uint32_t CHN_TIM_PKM_CFG;	/* 0x240 */
+	uint32_t CHN_TIM_AB4_CFG;	/* 0x244 */
+	uint32_t unused8[2];		/* 0x248 */
+	uint32_t CHN_TIM_AB4_ACT_PRI;	/* 0x250 */
+	uint32_t CHN_TIM_AB4_PRI_OPEN;	/* 0x254 */
+	uint32_t CHN_TIM_AB4_PRI_CLOSED;/* 0x258 */
+	uint32_t CHN_TIM_AUTO_SELF_REFRESH;/* 0x25c */
+#define MEMC_DDR_AUTO_SELFREFRESH_EN              (1 << 31)
+#define MEMC_DDR_AUTO_SR_IDLE_CNT_MASK            (0x7FFFFFFF)
+	uint32_t CHN_TIM_AUTO_ZQCS;	/* 0x260 */
+	uint32_t CHN_TIM_TIM3;		/* 0x264 */
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_MASK                            0x0fff0000
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_ALIGN                           0
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_BITS                            12
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_SHIFT                           16
+#define MC_CHN_TIM_TIM3_TIM3_TZQCL_DEFAULT                         0x00000100
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_ALIGN                           0
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_BITS                            8
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_SHIFT                           0
+#define MC_CHN_TIM_TIM3_TIM3_TZQCS_DEFAULT                         0x00000040
+
+	uint32_t unused9[38];		/* 0x268-0x2ff */
+
+	uint32_t ARB_CFG;		/* 0x300 */
+	uint32_t ARB_QUE_DIS[2];	/* 0x304 */
+	uint32_t unused10;		/* 0x30c */
+	uint32_t ARB_BKT_CFG_CPU_WR[4];	/* 0x310 */
+	uint32_t ARB_BKT_CFG_CPU_RD[4];	/* 0x320 */
+	uint32_t ARB_BKT_CFG_CPQ_RD[4];	/* 0x330 */
+	uint32_t ARB_BKT_CFG_CPQ_WR[4];	/* 0x340 */
+	uint32_t ARB_BKT_CFG_EDIS[4];	/* 0x350 */
+	uint32_t unused11[32];		/* 0x360 */
+	uint32_t ARB_QUEUE_PRI[3];	/* 0x3e0 */
+	uint32_t ARB_WRR_QUEUE_PRI;	/* 0x3ec */
+	uint32_t ARB_RATE_OK_WEIGHT[2];	/* 0x3f0 */
+	uint32_t ARB_RATE_FAIL_WEIGHT[2];/* 0x3f8 */
+
+	uint32_t unused12[48];		/* 0x400 */
+	AXIInterface AXIWIF;		/* 0x4c0 */
+
+	uint32_t unused13[192];		/* 0x500-0x7ff */
+
+	EDISEngine EDIS_0;		/* 0x800 */
+	uint32_t unused14[64];		/* 0x900 */
+
+	uint32_t STATS_CTRL;		/* 0xa00 */
+	uint32_t STATS_TIMER_CFG;	/* 0xa04 */
+	uint32_t STATS_TIMER_COUNT;	/* 0xa08 */
+	uint32_t STATS_TOTAL_SLICE;	/* 0xa0c */
+	uint32_t STATS_TOTAL_PACKET;	/* 0xa10 */
+	uint32_t STATS_TOTAL_READ_SLICE;/* 0xa14 */
+	uint32_t STATS_TOTAL_READ_PACKET;/* 0xa18 */
+	uint32_t STATS_TOTAL_LATENCY;	/* 0xa1c */
+	uint32_t STAT_MAX_LATENCY;	/* 0xa20 */
+	uint32_t STATS_SLICE_REORDER;	/* 0xa24 */
+	uint32_t STATS_TOTAL_DDR_CMD;	/* 0xa28 */
+	uint32_t STATS_TOTAL_DDR_ACT;	/* 0xa2c */
+	uint32_t STATS_TOTAL_DDR_RDWR;	/* 0xa30 */
+	uint32_t STATS_TOTAL_DDR_WRRD;	/* 0xa34 */
+	uint32_t STATS_TOTAL_MRQ_CHN_FULL;/* 0xa38 */
+	uint32_t STATS_TOTAL_SELF_REF;	/* 0xa3c */
+	uint32_t STATS_ARB_GRANT_MATCH0;/* 0xa40 */
+	uint32_t STATS_TOTAL_QUEUE_FULL;/* 0xa44 */
+	uint32_t STATS_TOTAL_ARB_GRANT;	/* 0xa48 */
+	uint32_t STATS_TOTAL_RATE_OK_GRANT;/* 0xa4c*/
+	uint32_t STATS_FILTER_CFG_0;	/* 0xa50 */
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT  25
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_MASK   (0x1<<MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_EN     0x02000000
+#define MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT     16
+#define MEMC_STATS_FILTER_CFG_SRC_ID_MASK      (0x1FF<<MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_SHIFT 0
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_MASK  0x0000FFFF
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS        0x00000001
+#define MEMC_STATS_FILTER_CFG_INTF_AXI         0x00000002
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS0       0x00000004
+#define MEMC_STATS_FILTER_CFG_INTF_UNUSED      0x00000008
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS0       MEMC_STATS_FILTER_CFG_INTF_UBUS
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_MCP         MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+	uint32_t STATS_PROG0_SLICE;	/* 0xa54 */
+	uint32_t STATS_PROG0_PACKET;	/* 0xa58 */
+	uint32_t STATS_PROG0_READ_SLICE;/* 0xa5c */
+	uint32_t STATS_PROG0_READ_PACKET;/* 0xa60 */
+	uint32_t STATS_PROG0_LATENCY;	/* 0xa64 */ 
+	uint32_t STATS_PROG0_MAX_LETANCY;/* 0xa68 */
+
+	// uint32_t unused15[37];	/* 0xa6c */
+	uint32_t unused15_0;		/* 0xa6c */
+	uint32_t STATS_FILTER_CFG_1;	/* 0xa70 */
+	uint32_t STATS_PROG1_SLICE;	/* 0xa74 */
+	uint32_t STATS_PROG1_PACKET;	/* 0xa78 */ 
+	uint32_t STATS_PROG1_READ_SLICE;/* 0xa7c */  
+	uint32_t STATS_PROG1_READ_PACKET;/* 0xa80 */
+	uint32_t STATS_PROG1_LATENCY;	/* 0xa84 */ 
+	uint32_t unused15_1[2];		/* 0xa88 - 0xa8c */   
+	uint32_t STATS_FILTER_CFG_2;	/* 0xa90 */
+	uint32_t STATS_PROG2_SLICE;	/* 0xa94 */
+	uint32_t STATS_PROG2_PACKET;	/* 0xa98 */ 
+	uint32_t STATS_PROG2_READ_SLICE;/* 0xa9c */  
+	uint32_t STATS_PROG2_READ_PACKET;/* 0xaa0 */
+	uint32_t STATS_PROG2_LATENCY;	/* 0xaa4 */ 
+	uint32_t unused15_2[2];		/* 0xaa8 - 0xaac */
+	uint32_t STATS_FILTER_CFG_3;	/* 0xab0 */
+	uint32_t STATS_PROG3_SLICE;	/* 0xab4 */
+	uint32_t STATS_PROG3_PACKET;	/* 0xab8 */ 
+	uint32_t STATS_PROG3_READ_SLICE;/* 0xabc */  
+	uint32_t STATS_PROG3_READ_PACKET;/* 0xac0 */
+	uint32_t STATS_PROG3_LATENCY;	/* 0xac4 */
+	uint32_t unused15_3[2];		/* 0xac8 - 0xacc */
+	uint32_t STATS_AXI_BLOCK_CPU_RD;/* 0xad0 */    
+	uint32_t STATS_AXI_BLOCK_CPQ_RD;/* 0xad4 */    
+	uint32_t unused15_4[10];	/* 0xad8 - 0xaff */
+   
+	uint32_t CAP_CAPTURE_CFG;	/* 0xb00 */
+	uint32_t CAP_TRIGGER_ADDR;	/* 0xb04 */
+	uint32_t CAP_READ_CTRL;		/* 0xb08 */
+	uint32_t unused16;		/* 0xb0c */
+	uint32_t CAP_CAPTURE_MATCH0;	/* 0xb10 */
+	uint32_t CAP_CAPTURE_MATCH1;	/* 0xb14 */
+	uint32_t CAP_CAPTURE_MATCH2;	/* 0xb18 */
+	uint32_t unused17;		/* 0xb1c */
+	uint32_t CAP_CAPTURE_MASK0;	/* 0xb20 */
+	uint32_t CAP_CAPTURE_MASK1;	/* 0xb24 */
+	uint32_t CAP_CAPTURE_MASK2;	/* 0xb28 */
+	uint32_t unused18;		/* 0xb2c */
+	uint32_t CAP_TRIGGER_MATCH0;	/* 0xb30 */
+	uint32_t CAP_TRIGGER_MATCH1;	/* 0xb34 */
+	uint32_t CAP_TRIGGER_MATCH2;	/* 0xb38 */
+	uint32_t unused19;		/* 0xb3c */
+	uint32_t CAP_TRIGGER_MASK0;	/* 0xb40 */
+	uint32_t CAP_TRIGGER_MASK1;	/* 0xb44 */
+	uint32_t CAP_TRIGGER_MASK2;	/* 0xb48 */
+	uint32_t unused20;		/* 0xb4c */
+	uint32_t CAP_READ_DATA[8];	/* 0xb50-0xb6f */
+	uint32_t unused21[164];		/* 0xb70-0xdff */
+
+	uint32_t SEC_INTR2_CPU_STATUS;	/* 0xe00 */
+	uint32_t SEC_INTR2_CPU_SET;	/* 0xe04 */
+	uint32_t SEC_INTR2_CPU_CLEAR;	/* 0xe08 */
+	uint32_t SEC_INTR2_CPU_MASK_STATUS;/* 0xe0c */
+	uint32_t SEC_INTR2_CPU_MASK_SET;/* 0xe10 */
+	uint32_t SEC_INTR2_CPU_MASK_CLEAR;/* 0xe14 */
+	uint32_t unused22[58];		/* 0xe18-0xeff */
+
+	uint32_t UBUSIF0_PERMCTL;	/* 0xf00 */
+	uint32_t UBUSIF1_PERMCTL;	/* 0xf04 */
+	uint32_t SRAM_REMAP_PERMCTL;	/* 0xf08 */
+	uint32_t AXIWIF_PERMCTL;	/* 0xf0c */
+	uint32_t CHNCFG_PERMCTL;	/* 0xf10 */
+	uint32_t MCCAP_PERMCTL;		/* 0xf14 */
+	uint32_t SCRAM_PERMCTL;		/* 0xf18 */
+	uint32_t RNG_PERMCTL;		/* 0xf1c */
+	uint32_t RNGCHK_PERMCTL;	/* 0xf20 */
+	uint32_t unused23[567];		/* 0xf24-0x17ff */
+
+	SecureRangeCheckers SEC_RANGE_CHK;/* 0x1800-0x18ff */
+	uint32_t unused24[31168];	/* 0x1900-0x1ffff */
+
+	DDRPhyControl PhyControl;	/* 0x20000 */
+	DDRPhyByteLaneControl PhyByteLane0Control;/* 0x20400 - 0x205ff */
+	DDRPhyByteLaneControl PhyByteLane1Control;/* 0x20600 - 0x207ff */
+} MEMCControl;
+
+
+#define MEMC ((volatile MEMCControl * const) MEMC_BASE)
+
+#endif /* _6756_DDR_H */
diff --git a/arch/arm/include/asm/arch-bcm6756/ethsw.h b/arch/arm/include/asm/arch-bcm6756/ethsw.h
new file mode 100644
index 0000000000..4f60647662
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/ethsw.h
@@ -0,0 +1,4656 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _6756_ETHSW_H
+#define _6756_ETHSW_H
+
+#include <config.h>
+#include <common.h>
+#include <stdlib.h>
+
+typedef struct {
+    uint32_t led_ctrl;
+#define SPDLNK_LED1_ACT_POL_SEL_SHIFT 7
+#define SPDLNK_LED1_ACT_POL_SEL_MASK (0x1 << SPDLNK_LED1_ACT_POL_SEL_SHIFT)
+#define ACT_LED_ACT_SEL_SHIFT 5
+#define ACT_LED_ACT_SEL_MASK (0x1 << ACT_LED_ACT_SEL_SHIFT)
+#define SPDLNK_LED0_ACT_SEL_SHIFT 2
+#define SPDLNK_LED0_ACT_SEL_MASK (0x1 << SPDLNK_LED0_ACT_SEL_SHIFT)
+#define RESERVED0_SHIFT 16
+#define RESERVED0_MASK (0xffff << RESERVED0_SHIFT)
+#define SPDLNK_LED0_ACT_POL_SEL_SHIFT 6
+#define SPDLNK_LED0_ACT_POL_SEL_MASK (0x1 << SPDLNK_LED0_ACT_POL_SEL_SHIFT)
+#define AGGREGATE_LED_CNTRL_RESERVED0_SHIFT 19
+#define AGGREGATE_LED_CNTRL_RESERVED0_MASK (0x1fff << AGGREGATE_LED_CNTRL_RESERVED0_SHIFT)
+#define AGGREGATE_LED_CNTRL_ACT_POL_SEL_SHIFT 17
+#define AGGREGATE_LED_CNTRL_ACT_POL_SEL_MASK (0x1 << AGGREGATE_LED_CNTRL_ACT_POL_SEL_SHIFT)
+#define SPDLNK_LED2_ACT_SEL_SHIFT 4
+#define SPDLNK_LED2_ACT_SEL_MASK (0x1 << SPDLNK_LED2_ACT_SEL_SHIFT)
+#define LED_SPD_OVRD_SHIFT 10
+#define LED_SPD_OVRD_MASK (0x7 << LED_SPD_OVRD_SHIFT)
+#define SPDLNK_LED2_ACT_POL_SEL_SHIFT 8
+#define SPDLNK_LED2_ACT_POL_SEL_MASK (0x1 << SPDLNK_LED2_ACT_POL_SEL_SHIFT)
+#define SPD_OVRD_EN_SHIFT 14
+#define SPD_OVRD_EN_MASK (0x1 << SPD_OVRD_EN_SHIFT)
+#define TX_ACT_EN_SHIFT 1
+#define TX_ACT_EN_MASK (0x1 << TX_ACT_EN_SHIFT)
+#define AGGREGATE_LED_CNTRL_ACT_SEL_SHIFT 16
+#define AGGREGATE_LED_CNTRL_ACT_SEL_MASK (0x1 << AGGREGATE_LED_CNTRL_ACT_SEL_SHIFT)
+#define LNK_STATUS_OVRD_SHIFT 13
+#define LNK_STATUS_OVRD_MASK (0x1 << LNK_STATUS_OVRD_SHIFT)
+#define RX_ACT_EN_SHIFT 0
+#define RX_ACT_EN_MASK (0x1 << RX_ACT_EN_SHIFT)
+#define AGGREGATE_LED_CNTRL_LNK_POL_SEL_SHIFT 18
+#define AGGREGATE_LED_CNTRL_LNK_POL_SEL_MASK (0x1 << AGGREGATE_LED_CNTRL_LNK_POL_SEL_SHIFT)
+#define SPDLNK_LED1_ACT_SEL_SHIFT 3
+#define SPDLNK_LED1_ACT_SEL_MASK (0x1 << SPDLNK_LED1_ACT_SEL_SHIFT)
+#define ACT_LED_POL_SEL_SHIFT 9
+#define ACT_LED_POL_SEL_MASK (0x1 << ACT_LED_POL_SEL_SHIFT)
+#define LNK_OVRD_EN_SHIFT 15
+#define LNK_OVRD_EN_MASK (0x1 << LNK_OVRD_EN_SHIFT)
+#define AGGREGATE_LED_CNTRL_PORT_EN_SHIFT 0
+#define AGGREGATE_LED_CNTRL_PORT_EN_MASK (0xffff << AGGREGATE_LED_CNTRL_PORT_EN_SHIFT)
+    uint32_t led_encoding_sel;
+    uint32_t led_encoding;
+#define LINK_AND_SPEED_ENCODING_M10G_ENCODE_SHIFT 15
+#define LINK_AND_SPEED_ENCODING_M10G_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M10G_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_SHIFT 3
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_SHIFT 6
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_SHIFT 15
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M10_ENCODE_SHIFT 3
+#define LINK_AND_SPEED_ENCODING_M10_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M10_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M1000_ENCODE_SHIFT 9
+#define LINK_AND_SPEED_ENCODING_M1000_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M1000_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_SHIFT 12
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M100_ENCODE_SHIFT 6
+#define LINK_AND_SPEED_ENCODING_M100_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M100_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_SHIFT 9
+#define LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_SHIFT)
+#define LINK_AND_SPEED_ENCODING_M2500_ENCODE_SHIFT 12
+#define LINK_AND_SPEED_ENCODING_M2500_ENCODE_MASK (0x7 << LINK_AND_SPEED_ENCODING_M2500_ENCODE_SHIFT)
+
+}LED_CFG;
+
+/* leaving the definition of the QPHY register for compilation only */
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT     12
+#define ETHSW_QPHY_CTRL_PHYAD_BASE_MASK      (0x1f<<ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT)
+#define ETHSW_QPHY_CTRL_RESET_SHIFT          8
+#define ETHSW_QPHY_CTRL_RESET_MASK           (0x1<<ETHSW_QPHY_CTRL_RESET_SHIFT )
+#define ETHSW_QPHY_CTRL_CK25_DIS_SHIFT       7
+#define ETHSW_QPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_QPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_QPHY_CTRL_EXT_PWR_DOWN_MASK    (0xf<<ETHSW_QPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      6
+#define ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+
+typedef struct EthernetSwitchReg
+{
+    uint32_t switch_ctrl;                      /* 0x0000 */
+#define ETHSW_SWITCH_CTRL_SWITCH_CLK_SEL_SHIFT  27
+#define ETHSW_SWITCH_CTRL_SWITCH_CLK_SEL_MASK   (0x3<<ETHSW_SWITCH_CTRL_SWITCH_CLK_SEL_SHIFT)
+#define ETHSW_SWITCH_CTRL_SYSPORT_CLK_SEL_SHIFT 24
+#define ETHSW_SWITCH_CTRL_SYSPORT_CLK_SEL_MASK  (0x3<<ETHSW_SWITCH_CTRL_SYSPORT_CLK_SEL_SHIFT)
+#define ETHSW_SWITCH_CTRL_P8_CLK_SEL_SHIFT      3
+#define ETHSW_SWITCH_CTRL_P8_CLK_SEL_MASK       (0x3<<ETHSW_SWITCH_CTRL_P8_CLK_SEL_SHIFT)
+    uint32_t switch_status;                    /* 0x0004 */
+    uint32_t dir_data_write_reg;               /* 0x0008 */
+    uint32_t dir_data_read_reg;                /* 0x000c */
+    uint32_t switch_rev;                       /* 0x0010 */
+    uint32_t phy_rev;                          /* 0x0014 */
+    uint32_t phy_test_ctrl;                    /* 0x0018 */
+    uint32_t reserved1[2];                     /* 0x001c */
+    uint32_t sphy_ctrl;                        /* 0x0024 */
+#define ETHSW_SPHY_CTRL_PHYAD_SHIFT          8
+#define ETHSW_SPHY_CTRL_PHYAD_MASK           (0x1f<<ETHSW_SPHY_CTRL_PHYAD_SHIFT)
+#define ETHSW_SPHY_CTRL_RESET_SHIFT          5
+#define ETHSW_SPHY_CTRL_RESET_MASK           (0x1<<ETHSW_SPHY_CTRL_RESET_SHIFT )
+#define ETHSW_SPHY_CTRL_CK25_DIS_SHIFT       4
+#define ETHSW_SPHY_CTRL_CK25_DIS_MASK        (0x1<<ETHSW_SPHY_CTRL_CK25_DIS_SHIFT)
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT   1
+#define ETHSW_SPHY_CTRL_EXT_PWR_DOWN_MASK    (0x1<<ETHSW_SPHY_CTRL_EXT_PWR_DOWN_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT      0
+#define ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_BIAS_SHIFT)
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT      3
+#define ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK       (0x1<<ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_SHIFT)
+    uint32_t sphy_status;                      /* 0x0028 */
+    uint32_t switch_phy_intr_ctrl;             /* 0x002c */
+    uint32_t reserved30[2];                    /* 0x0030 - 0x0037 */
+    uint32_t led_pwm_ctrl;                     /* 0x0038 */
+    uint32_t led_intensity_ctrl;               /* 0x003c */
+    LED_CFG led_ctrl[10];                    /* 0x0040 - 0x00b7 */  //6756: port 0,1,5,6 are populated
+#define ETHSW_LED_CTRL_SPD0_ON               0x0
+#define ETHSW_LED_CTRL_SPD0_OFF              0x1
+#define ETHSW_LED_CTRL_SPD1_ON               0x0
+#define ETHSW_LED_CTRL_SPD1_OFF              0x2
+#define ETHSW_LED_CTRL_1000M_SHIFT           9
+#define ETHSW_LED_CTRL_100M_SHIFT            6
+#define ETHSW_LED_CTRL_10M_SHIFT             3
+#define ETHSW_LED_CTRL_NOLINK_SHIFT          0
+#define ETHSW_LED_CTRL_ALL_SPEED_MASK        0x3ffff
+#define ETHSW_LED_CTRL_SPEED_MASK            0x7
+    uint32_t led_blink_rate_ctrl;              /* 0x00b8 */
+    uint32_t reserved_bc;                      /* 0x00bc */           //63178: led_serial_ctrl not populated
+    uint32_t led_refresh_period_ctrl;          /* 0x00c0 */
+    uint32_t aggregate_led_ctrl;               /* 0x00c4 */
+#define ETHSW_AGGREGATE_LED_CTRL_PORT_EN_MASK            0xffff
+#define ETHSW_AGGREGATE_LED_CTRL_ACT_SEL_MASK            0x10000
+#define ETHSW_AGGREGATE_LED_CTRL_ACT_POL_SEL_MASK        0x20000
+#define ETHSW_AGGREGATE_LED_CTRL_LNK_POL_SEL_MASK        0x40000
+    uint32_t aggregate_blink_rate_ctrl;        /* 0x00c8 */
+    uint32_t aggregate_led_pwm_ctrl;           /* 0x00cc */
+    uint32_t aggregate_led_intensity_ctrl;     /* 0x00d0 */
+    uint32_t resereved_d4[6];                  /* 0x00d4 - 0x00eb */
+    uint32_t rgmii_1_ctrl;                     /* 0x00ec */
+#define ETHSW_RC_MII_MODE_MASK               0x1c
+#define ETHSW_RC_EXT_RVMII                   0x10
+#define ETHSW_RC_EXT_GPHY                    0x0c
+#define ETHSW_RC_EXT_EPHY                    0x08
+#define ETHSW_RC_INT_GPHY                    0x04
+#define ETHSW_RC_INT_EPHY                    0x00
+#define ETHSW_RC_ID_MODE_DIS                 0x02
+#define ETHSW_RC_RGMII_EN                    0x01
+    uint32_t rgmii_1_ib_status;                /* 0x00f0 */
+    uint32_t rgmii_1_rx_clk_delay_ctrl;        /* 0x00f4 */
+#define ETHSW_RXCLK_IDDQ                     (1<<4)
+#define ETHSW_RXCLK_BYPASS                   (1<<5)
+
+    uint32_t reserved_f8[210];                 /* 0x00f8 - 0x043f */
+    uint32_t moca_bp_mapping_port1;            /* 0x0440*/
+} EthernetSwitchReg;
+
+
+typedef struct {
+    unsigned int led_f;
+    unsigned int reserved;
+} LED_F;
+
+typedef struct EthernetSwitchCore
+{
+	uint64_t port_traffic_ctrl[9];                // 0x00000 - 00047      only p0, p1, p5, p6, p8 are valid
+	uint8_t dummy1[8];
+	uint64_t SWITCH_CORE_RX_GLOBAL_CTL;           // 0x00050
+#define ETHSW_SM_RETRY_LIMIT_DIS                  0x04
+#define ETHSW_SM_FORWARDING_EN                    0x02
+#define ETHSW_SM_MANAGED_MODE                     0x01
+	uint32_t switch_mode;
+	uint8_t dummy2[148];
+	uint32_t SWITCH_CORE_DEBUG_REG;
+	uint8_t dummy3[20];
+	uint64_t SWITCH_CORE_NEW_CTRL;
+	uint32_t switch_ctrl;
+#define ETHSW_SC_MII_DUMP_FORWARDING_EN           0x40
+#define ETHSW_SC_MII2_VOL_SEL                     0x02
+	uint8_t dummy4[12];
+	uint32_t SWITCH_CORE_PROTECTED_SEL;
+	uint8_t dummy5[12];
+	uint32_t SWITCH_CORE_WAN_PORT_SEL;
+	uint8_t dummy6[68];
+	uint32_t SWITCH_CORE_RSV_MCAST_CTRL;
+	uint8_t dummy7[12];
+	uint64_t SWITCH_CORE_TXQ_FLUSH_MODE;
+	uint32_t SWITCH_CORE_ULF_DROP_MAP;
+	uint8_t dummy8[12];
+	uint32_t SWITCH_CORE_MLF_DROP_MAP;
+	uint8_t dummy9[12];
+	uint32_t SWITCH_CORE_MLF_IPMC_FWD_MAP;
+	uint8_t dummy10[12];
+	uint32_t SWITCH_CORE_RX_PAUSE_PASS;
+	uint8_t dummy11[12];
+	uint32_t SWITCH_CORE_TX_PAUSE_PASS;
+	uint8_t dummy12[12];
+	uint32_t SWITCH_CORE_DIS_LEARN;
+	uint8_t dummy13[12];
+	uint32_t SWITCH_CORE_SFT_LRN_CTL;
+	uint8_t dummy14[12];
+	uint32_t SWITCH_CORE_LOW_POWER_EXP1;
+	uint8_t dummy15[156];
+	uint32_t SWITCH_CORE_CTLREG_REG_SPARE;
+	uint8_t dummy16[292];
+	uint64_t software_reset;
+	uint32_t SWITCH_CORE_WATCH_DOG_RPT1;
+	uint8_t dummy17[12];
+	uint32_t SWITCH_CORE_WATCH_DOG_RPT2;
+	uint8_t dummy18[12];
+	uint32_t SWITCH_CORE_WATCH_DOG_RPT3;
+	uint8_t dummy19[12];
+	uint64_t SWITCH_CORE_PAUSE_FRM_CTRL;
+	uint32_t SWITCH_CORE_PAUSE_ST_ADDR;
+	uint8_t dummy20[52];
+	uint64_t SWITCH_CORE_FAST_AGE_CTRL;
+	uint64_t SWITCH_CORE_FAST_AGE_PORT;
+	uint32_t SWITCH_CORE_FAST_AGE_VID;
+	uint8_t dummy21[668];
+	uint32_t SWITCH_CORE_LOW_POWER_CTRL;
+	uint8_t dummy22[76];
+	uint32_t SWITCH_CORE_TCAM_CTRL;
+	uint8_t dummy23[12];
+	uint32_t SWITCH_CORE_TCAM_CHKSUM_STS;
+	uint8_t dummy24[12];
+	uint32_t SWITCH_CORE_LIGHTSTACK_CTRL;
+	uint8_t dummy25[156];
+	uint32_t SWITCH_CORE_LNKSTS;
+	uint8_t dummy26[12];
+	uint32_t SWITCH_CORE_LNKSTSCHG;
+	uint8_t dummy27[12];
+	uint32_t SWITCH_CORE_SPDSTS;
+	uint8_t dummy28[28];
+	uint32_t SWITCH_CORE_DUPSTS;
+	uint8_t dummy29[12];
+	uint32_t SWITCH_CORE_PAUSESTS;
+	uint8_t dummy30[28];
+	uint32_t SWITCH_CORE_SRCADRCHG;
+	uint8_t dummy31[12];
+	uint32_t SWITCH_CORE_LSA_PORT_P0;
+	uint8_t dummy32[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P1;
+	uint8_t dummy33[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P2;
+	uint8_t dummy34[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P3;
+	uint8_t dummy35[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P4;
+	uint8_t dummy36[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P5;
+	uint8_t dummy37[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P6;
+	uint8_t dummy38[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P7;
+	uint8_t dummy39[44];
+	uint32_t SWITCH_CORE_LSA_PORT_P8;
+	uint8_t dummy40[44];
+	uint32_t SWITCH_CORE_BIST_STS0;
+	uint8_t dummy41[44];
+	uint32_t SWITCH_CORE_BIST_STS1;
+	uint8_t dummy42[28];
+	uint32_t SWITCH_CORE_PBPTRFIFO_0;
+	uint8_t dummy43[44];
+	uint32_t SWITCH_CORE_PBPTRFIFO_1;
+	uint8_t dummy44[460];
+	uint32_t SWITCH_CORE_RESET_STATUS;
+	uint8_t dummy45[124];
+	uint32_t SWITCH_CORE_STREG_REG_SPARE0;
+	uint8_t dummy46[28];
+	uint32_t SWITCH_CORE_STREG_REG_SPARE1;
+	uint8_t dummy47[732];
+	uint64_t SWITCH_CORE_GMNGCFG;
+	uint64_t SWITCH_CORE_IMP0_PRT_ID;
+	uint64_t SWITCH_CORE_IMP1_PRT_ID;
+	uint32_t brcm_hdr_ctrl;
+	uint8_t dummy48[20];
+	uint32_t SWITCH_CORE_SPTAGT;
+	uint8_t dummy49[28];
+	uint32_t SWITCH_CORE_BRCM_HDR_CTRL2;
+	uint8_t dummy50[12];
+	uint32_t SWITCH_CORE_IPG_SHRNK_CTRL;
+	uint8_t dummy51[28];
+	uint32_t SWITCH_CORE_MIRCAPCTL;
+	uint8_t dummy52[12];
+	uint32_t SWITCH_CORE_IGMIRCTL;
+	uint8_t dummy53[12];
+	uint32_t SWITCH_CORE_IGMIRDIV;
+	uint8_t dummy54[12];
+	uint32_t SWITCH_CORE_IGMIRMAC;
+	uint8_t dummy55[44];
+	uint32_t SWITCH_CORE_EGMIRCTL;
+	uint8_t dummy56[12];
+	uint32_t SWITCH_CORE_EGMIRDIV;
+	uint8_t dummy57[12];
+	uint32_t SWITCH_CORE_EGMIRMAC;
+	uint8_t dummy58[44];
+	uint32_t SWITCH_CORE_SPANCTL;
+	uint8_t dummy59[28];
+	uint32_t SWITCH_CORE_RSPANVLAN;
+	uint8_t dummy60[300];
+	uint32_t SWITCH_CORE_HL_PRTC_CTRL;
+	uint8_t dummy61[28];
+	uint32_t SWITCH_CORE_RST_MIB_CNT_EN;
+	uint8_t dummy62[28];
+	uint32_t SWITCH_CORE_IPG_SHRINK_2G_WA;
+	uint8_t dummy63[60];
+	uint32_t SWITCH_CORE_BRCM_HDR_RX_DIS;
+	uint8_t dummy64[12];
+	uint32_t SWITCH_CORE_BRCM_HDR_TX_DIS;
+	uint8_t dummy65[108];
+	uint32_t SWITCH_CORE_MNGMODE_REG_SPARE0;
+	uint8_t dummy66[28];
+	uint32_t SWITCH_CORE_MNGMODE_REG_SPARE1;
+	uint8_t dummy67[1116];
+	uint32_t SWITCH_CORE_INT_STS;
+	uint8_t dummy68[60];
+	uint32_t SWITCH_CORE_INT_EN;
+	uint8_t dummy69[60];
+	uint32_t SWITCH_CORE_SLEEP_TIMER_IMP;
+	uint8_t dummy70[12];
+	uint32_t SWITCH_CORE_PORT7_SLEEP_TIMER;
+	uint8_t dummy71[12];
+	uint32_t SWITCH_CORE_WAN_SLEEP_TIMER;
+	uint8_t dummy72[28];
+	uint32_t SWITCH_CORE_PORT_SLEEP_STS;
+	uint8_t dummy73[92];
+	uint32_t SWITCH_CORE_LINK_STS_INT_EN;
+	uint8_t dummy74[28];
+	uint32_t SWITCH_CORE_ENG_DET_INT_EN;
+	uint8_t dummy75[12];
+	uint32_t SWITCH_CORE_LPI_STS_CHG_INT_EN;
+	uint8_t dummy76[428];
+	uint32_t SWITCH_CORE_MEM_ECC_ERR_INT_STS;
+	uint8_t dummy77[12];
+	uint32_t SWITCH_CORE_MEM_ECC_ERR_INT_EN;
+	uint8_t dummy78[12];
+	uint32_t SWITCH_CORE_PORT_EVT_ECC_ERR_STS;
+	uint8_t dummy79[12];
+	uint32_t SWITCH_CORE_PORT_MIB_ECC_ERR_STS;
+	uint8_t dummy80[12];
+	uint32_t SWITCH_CORE_PORT_TXQ_ECC_ERR_STS;
+	uint8_t dummy81[60];
+	uint32_t SWITCH_CORE_PROBE_BUS_CTL;
+	uint8_t dummy82[28];
+	uint32_t SWITCH_CORE_MDC_EXTEND_CTRL;
+	uint8_t dummy83[92];
+	uint32_t SWITCH_CORE_PPPOE_SESSION_PARSE_EN;
+	uint8_t dummy84[124];
+	uint32_t SWITCH_CORE_CTLREG_1_REG_SPARE0;
+	uint8_t dummy85[28];
+	uint32_t SWITCH_CORE_CTLREG_1_REG_SPARE1;
+	uint8_t dummy86[860];
+	uint32_t SWITCH_CORE_GARLCFG;
+	uint8_t dummy87[28];
+	uint32_t SWITCH_CORE_BPDU_MCADDR;
+	uint8_t dummy88[76];
+	uint32_t SWITCH_CORE_MULTI_PORT_CTL;
+	uint8_t dummy89[12];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR0;
+	uint8_t dummy90[60];
+	uint32_t SWITCH_CORE_MPORTVEC0;
+	uint8_t dummy91[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR1;
+	uint8_t dummy92[60];
+	uint32_t SWITCH_CORE_MPORTVEC1;
+	uint8_t dummy93[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR2;
+	uint8_t dummy94[60];
+	uint32_t SWITCH_CORE_MPORTVEC2;
+	uint8_t dummy95[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR3;
+	uint8_t dummy96[60];
+	uint32_t SWITCH_CORE_MPORTVEC3;
+	uint8_t dummy97[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR4;
+	uint8_t dummy98[60];
+	uint32_t SWITCH_CORE_MPORTVEC4;
+	uint8_t dummy99[60];
+	uint32_t SWITCH_CORE_MULTIPORT_ADDR5;
+	uint8_t dummy100[60];
+	uint32_t SWITCH_CORE_MPORTVEC5;
+	uint8_t dummy101[60];
+	uint32_t SWITCH_CORE_ARL_BIN_FULL_CNTR;
+	uint8_t dummy102[28];
+	uint32_t SWITCH_CORE_ARL_BIN_FULL_FWD;
+	uint8_t dummy103[12];
+	uint32_t SWITCH_CORE_ARL_SEED;
+	uint8_t dummy104[76];
+	uint32_t SWITCH_CORE_ARLCTL_REG_SPARE0;
+	uint8_t dummy105[28];
+	uint32_t SWITCH_CORE_ARLCTL_REG_SPARE1;
+	uint8_t dummy106[92];
+	uint32_t SWITCH_CORE_ARL_TCAM_CTRL;
+	uint8_t dummy107[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_STS;
+	uint8_t dummy108[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_FULL_CNTR;
+	uint8_t dummy109[28];
+	uint32_t SWITCH_CORE_ARL_CPU_PORTMAP;
+	uint8_t dummy110[796];
+	uint32_t SWITCH_CORE_ARLA_RWCTL;
+	uint8_t dummy111[12];
+	uint32_t SWITCH_CORE_ARLA_MAC;
+	uint8_t dummy112[44];
+	uint32_t SWITCH_CORE_ARLA_VID;
+	uint8_t dummy113[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY0;
+	uint8_t dummy114[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY0;
+	uint8_t dummy115[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY1;
+	uint8_t dummy116[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY1;
+	uint8_t dummy117[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY2;
+	uint8_t dummy118[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY2;
+	uint8_t dummy119[60];
+	uint32_t SWITCH_CORE_ARLA_MACVID_ENTRY3;
+	uint8_t dummy120[60];
+	uint32_t SWITCH_CORE_ARLA_FWD_ENTRY3;
+	uint8_t dummy121[60];
+	uint64_t SWITCH_CORE_ARLA_SRCH_CTL;
+	uint32_t SWITCH_CORE_ARLA_SRCH_ADR;
+	uint8_t dummy122[116];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_0_MACVID;
+	uint8_t dummy123[60];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_0;
+	uint8_t dummy124[60];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_1_MACVID;
+	uint8_t dummy125[60];
+	uint32_t SWITCH_CORE_ARLA_SRCH_RSLT_1;
+	uint8_t dummy126[60];
+	uint64_t SWITCH_CORE_ARLA_VTBL_RWCTRL;
+	uint32_t SWITCH_CORE_ARLA_VTBL_ADDR;
+	uint8_t dummy127[12];
+	uint32_t SWITCH_CORE_ARLA_VTBL_ENTRY;
+	uint8_t dummy128[100];
+	uint32_t SWITCH_CORE_ARLACCS_REG_SPARE0;
+	uint8_t dummy129[28];
+	uint32_t SWITCH_CORE_ARLACCS_REG_SPARE1;
+	uint8_t dummy130[4956];
+	uint64_t SWITCH_CORE_MEM_CTRL;
+	uint32_t SWITCH_CORE_MEM_ADDR;
+	uint8_t dummy131[52];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_0_0;
+	uint8_t dummy132[60];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_0_1;
+	uint8_t dummy133[12];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_1_0;
+	uint8_t dummy134[60];
+	uint32_t SWITCH_CORE_MEM_DEBUG_DATA_1_1;
+	uint8_t dummy135[44];
+	uint32_t SWITCH_CORE_MEM_FRM_ADDR;
+	uint8_t dummy136[124];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA0;
+	uint8_t dummy137[60];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA1;
+	uint8_t dummy138[60];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA2;
+	uint8_t dummy139[60];
+	uint32_t SWITCH_CORE_MEM_FRM_DATA3;
+	uint8_t dummy140[60];
+	uint32_t SWITCH_CORE_MEM_BTM_DATA0;
+	uint8_t dummy141[60];
+	uint32_t SWITCH_CORE_MEM_BTM_DATA1;
+	uint8_t dummy142[60];
+	uint32_t SWITCH_CORE_MEM_BFC_ADDR;
+	uint8_t dummy143[12];
+	uint32_t SWITCH_CORE_MEM_BFC_DATA;
+	uint8_t dummy144[108];
+	uint64_t SWITCH_CORE_PRS_FIFO_DEBUG_CTRL;
+	uint32_t SWITCH_CORE_PRS_FIFO_DEBUG_DATA;
+	uint8_t dummy145[116];
+	uint32_t SWITCH_CORE_MIBKILLOVR;
+	uint8_t dummy146[316];
+	uint32_t SWITCH_CORE_MEM_REG_SPARE0;
+	uint8_t dummy147[28];
+	uint32_t SWITCH_CORE_MEM_REG_SPARE1;
+	uint8_t dummy148[28];
+	uint32_t SWITCH_CORE_MEM_MISC_CTRL;
+	uint8_t dummy149[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL0;
+	uint8_t dummy150[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL1;
+	uint8_t dummy151[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL2;
+	uint8_t dummy152[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL3;
+	uint8_t dummy153[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL4;
+	uint8_t dummy154[28];
+	uint32_t SWITCH_CORE_MEM_TEST_CTRL5;
+	uint8_t dummy155[188];
+	uint32_t SWITCH_CORE_MEM_PSM_VDD_CTRL;
+	uint8_t dummy156[252];
+	uint32_t SWITCH_CORE_PORT0_DEBUG;
+	uint8_t dummy157[124];
+	uint32_t SWITCH_CORE_PORT1_DEBUG;
+	uint8_t dummy158[124];
+	uint32_t SWITCH_CORE_PORT2_DEBUG;
+	uint8_t dummy159[124];
+	uint32_t SWITCH_CORE_PORT3_DEBUG;
+	uint8_t dummy160[124];
+	uint32_t SWITCH_CORE_PORT4_DEBUG;
+	uint8_t dummy161[124];
+	uint32_t SWITCH_CORE_PORT5_DEBUG;
+	uint8_t dummy162[124];
+	uint32_t SWITCH_CORE_PORT6_DEBUG;
+	uint8_t dummy163[124];
+	uint32_t SWITCH_CORE_PORT7_DEBUG;
+	uint8_t dummy164[124];
+	uint32_t SWITCH_CORE_PORT8_DEBUG;
+	uint8_t dummy165[1020];
+	uint32_t SWITCH_CORE_FC_DIAG_CTRL;
+	uint8_t dummy166[12];
+	uint64_t SWITCH_CORE_FC_CTRL_MODE;
+	uint64_t SWITCH_CORE_FC_CTRL_PORT;
+	uint32_t SWITCH_CORE_FC_OOB_PAUSE_EN;
+	uint8_t dummy167[92];
+	uint32_t SWITCH_CORE_PAUSE_TIME_MAX;
+	uint8_t dummy168[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_MIN;
+	uint8_t dummy169[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_RESET_THD;
+	uint8_t dummy170[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_UPDATE_PERIOD;
+	uint8_t dummy171[12];
+	uint32_t SWITCH_CORE_PAUSE_TIME_DEFAULT;
+	uint8_t dummy172[12];
+	uint32_t SWITCH_CORE_FC_MCAST_DROP_CTRL;
+	uint8_t dummy173[12];
+	uint32_t SWITCH_CORE_FC_PAUSE_DROP_CTRL;
+	uint8_t dummy174[12];
+	uint32_t SWITCH_CORE_FC_TXQ_THD_PAUSE_OFF;
+	uint8_t dummy175[12];
+	uint32_t SWITCH_CORE_FC_RX_RUNOFF;
+	uint8_t dummy176[12];
+	uint32_t SWITCH_CORE_FC_RX_RSV_THD;
+	uint8_t dummy177[12];
+	uint32_t SWITCH_CORE_FC_RX_HYST_THD;
+	uint8_t dummy178[12];
+	uint32_t SWITCH_CORE_FC_RX_MAX_PTR;
+	uint8_t dummy179[12];
+	uint32_t SWITCH_CORE_FC_SPARE_ZERO_REG;
+	uint8_t dummy180[12];
+	uint32_t SWITCH_CORE_FC_SPARE_ONE_REG;
+	uint8_t dummy181[44];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q0;
+	uint8_t dummy182[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q1;
+	uint8_t dummy183[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q2;
+	uint8_t dummy184[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q3;
+	uint8_t dummy185[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q4;
+	uint8_t dummy186[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q5;
+	uint8_t dummy187[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q6;
+	uint8_t dummy188[12];
+	uint32_t SWITCH_CORE_FC_MON_TX_Q7;
+	uint8_t dummy189[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q0;
+	uint8_t dummy190[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q1;
+	uint8_t dummy191[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q2;
+	uint8_t dummy192[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q3;
+	uint8_t dummy193[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q4;
+	uint8_t dummy194[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q5;
+	uint8_t dummy195[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q6;
+	uint8_t dummy196[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TX_Q7;
+	uint8_t dummy197[12];
+	uint32_t SWITCH_CORE_FC_PEAK_TOTAL_USED;
+	uint8_t dummy198[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_USED;
+	uint8_t dummy199[12];
+	uint32_t SWITCH_CORE_FC_PEAK_RX_CNT;
+	uint8_t dummy200[12];
+	uint32_t SWITCH_CORE_FC_LINK_PORTMAP;
+	uint8_t dummy201[12];
+	uint32_t SWITCH_CORE_FC_GIGA_PORTMAP;
+	uint8_t dummy202[60];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P0;
+	uint8_t dummy203[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P1;
+	uint8_t dummy204[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P2;
+	uint8_t dummy205[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P3;
+	uint8_t dummy206[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P4;
+	uint8_t dummy207[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P5;
+	uint8_t dummy208[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P6;
+	uint8_t dummy209[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P7;
+	uint8_t dummy210[12];
+	uint32_t SWITCH_CORE_FC_CONG_PORTMAP_P8;
+	uint8_t dummy211[60];
+	uint32_t SWITCH_CORE_FC_PAUSE_HIS;
+	uint8_t dummy212[12];
+	uint32_t SWITCH_CORE_FC_TX_QUANTUM_PAUSE_HIS;
+	uint8_t dummy213[12];
+	uint32_t SWITCH_CORE_FC_RX_PAUSE_HIS;
+	uint8_t dummy214[12];
+	uint32_t SWITCH_CORE_FC_RXBUF_ERR_HIS;
+	uint8_t dummy215[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P0;
+	uint8_t dummy216[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P1;
+	uint8_t dummy217[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P2;
+	uint8_t dummy218[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P3;
+	uint8_t dummy219[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P4;
+	uint8_t dummy220[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P5;
+	uint8_t dummy221[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P6;
+	uint8_t dummy222[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P7;
+	uint8_t dummy223[12];
+	uint32_t SWITCH_CORE_FC_TXQ_CONG_PORTMAP_P8;
+	uint8_t dummy224[76];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P0;
+	uint8_t dummy225[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P1;
+	uint8_t dummy226[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P2;
+	uint8_t dummy227[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P3;
+	uint8_t dummy228[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P4;
+	uint8_t dummy229[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P5;
+	uint8_t dummy230[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P6;
+	uint8_t dummy231[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P7;
+	uint8_t dummy232[12];
+	uint32_t SWITCH_CORE_FC_TOTAL_CONG_PORTMAP_P8;
+	uint8_t dummy233[684];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q0;
+	uint8_t dummy234[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q1;
+	uint8_t dummy235[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q2;
+	uint8_t dummy236[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q3;
+	uint8_t dummy237[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q4;
+	uint8_t dummy238[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q5;
+	uint8_t dummy239[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q6;
+	uint8_t dummy240[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_RSV_Q7;
+	uint8_t dummy241[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q0;
+	uint8_t dummy242[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q1;
+	uint8_t dummy243[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q2;
+	uint8_t dummy244[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q3;
+	uint8_t dummy245[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q4;
+	uint8_t dummy246[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q5;
+	uint8_t dummy247[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q6;
+	uint8_t dummy248[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_HYST_Q7;
+	uint8_t dummy249[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q0;
+	uint8_t dummy250[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q1;
+	uint8_t dummy251[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q2;
+	uint8_t dummy252[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q3;
+	uint8_t dummy253[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q4;
+	uint8_t dummy254[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q5;
+	uint8_t dummy255[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q6;
+	uint8_t dummy256[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_PAUSE_Q7;
+	uint8_t dummy257[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q0;
+	uint8_t dummy258[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q1;
+	uint8_t dummy259[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q2;
+	uint8_t dummy260[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q3;
+	uint8_t dummy261[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q4;
+	uint8_t dummy262[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q5;
+	uint8_t dummy263[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q6;
+	uint8_t dummy264[12];
+	uint32_t SWITCH_CORE_FC_LAN_TXQ_THD_DROP_Q7;
+	uint8_t dummy265[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q0;
+	uint8_t dummy266[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q1;
+	uint8_t dummy267[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q2;
+	uint8_t dummy268[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q3;
+	uint8_t dummy269[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q4;
+	uint8_t dummy270[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q5;
+	uint8_t dummy271[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q6;
+	uint8_t dummy272[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_HYST_Q7;
+	uint8_t dummy273[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q0;
+	uint8_t dummy274[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q1;
+	uint8_t dummy275[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q2;
+	uint8_t dummy276[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q3;
+	uint8_t dummy277[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q4;
+	uint8_t dummy278[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q5;
+	uint8_t dummy279[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q6;
+	uint8_t dummy280[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_PAUSE_Q7;
+	uint8_t dummy281[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q0;
+	uint8_t dummy282[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q1;
+	uint8_t dummy283[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q2;
+	uint8_t dummy284[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q3;
+	uint8_t dummy285[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q4;
+	uint8_t dummy286[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q5;
+	uint8_t dummy287[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q6;
+	uint8_t dummy288[12];
+	uint32_t SWITCH_CORE_FC_LAN_TOTAL_THD_DROP_Q7;
+	uint8_t dummy289[1164];
+	uint32_t SWITCH_CORE_P0_DEBUG_MUX;
+	uint8_t dummy290[28];
+	uint32_t SWITCH_CORE_P1_DEBUG_MUX;
+	uint8_t dummy291[28];
+	uint32_t SWITCH_CORE_P2_DEBUG_MUX;
+	uint8_t dummy292[28];
+	uint32_t SWITCH_CORE_P3_DEBUG_MUX;
+	uint8_t dummy293[28];
+	uint32_t SWITCH_CORE_P4_DEBUG_MUX;
+	uint8_t dummy294[28];
+	uint32_t SWITCH_CORE_P5_DEBUG_MUX;
+	uint8_t dummy295[28];
+	uint32_t SWITCH_CORE_P6_DEBUG_MUX;
+	uint8_t dummy296[28];
+	uint32_t SWITCH_CORE_DEBUG_MUX_P7;
+	uint8_t dummy297[28];
+	uint32_t SWITCH_CORE_DEBUG_MUX_IMP;
+	uint8_t dummy298[28];
+	uint32_t SWITCH_CORE_CFP_DEBUG_BUS_0;
+	uint8_t dummy299[28];
+	uint32_t SWITCH_CORE_CFP_DEBUG_BUS_1;
+	uint8_t dummy300[28];
+	uint32_t SWITCH_CORE_WRED_DEBUG_0;
+	uint8_t dummy301[28];
+	uint32_t SWITCH_CORE_WRED_DEBUG_1;
+	uint8_t dummy302[28];
+	uint32_t SWITCH_CORE_TOP_MISC_DEBUG_0;
+	uint8_t dummy303[28];
+	uint32_t SWITCH_CORE_TOP_MISC_DEBUG_1;
+	uint8_t dummy304[28];
+	uint32_t SWITCH_CORE_DIAGREG_BUFCON;
+	uint8_t dummy305[28];
+	uint32_t SWITCH_CORE_TESTBUS_P1588;
+	uint8_t dummy306[28];
+	uint32_t SWITCH_CORE_FLOWCON_DEBUG_BUS;
+	uint8_t dummy307[1500];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q0;
+	uint8_t dummy308[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q1;
+	uint8_t dummy309[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q2;
+	uint8_t dummy310[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q3;
+	uint8_t dummy311[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q4;
+	uint8_t dummy312[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q5;
+	uint8_t dummy313[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q6;
+	uint8_t dummy314[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_RSV_Q7;
+	uint8_t dummy315[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q0;
+	uint8_t dummy316[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q1;
+	uint8_t dummy317[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q2;
+	uint8_t dummy318[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q3;
+	uint8_t dummy319[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q4;
+	uint8_t dummy320[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q5;
+	uint8_t dummy321[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q6;
+	uint8_t dummy322[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_HYST_Q7;
+	uint8_t dummy323[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q0;
+	uint8_t dummy324[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q1;
+	uint8_t dummy325[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q2;
+	uint8_t dummy326[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q3;
+	uint8_t dummy327[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q4;
+	uint8_t dummy328[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q5;
+	uint8_t dummy329[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q6;
+	uint8_t dummy330[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_PAUSE_Q7;
+	uint8_t dummy331[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q0;
+	uint8_t dummy332[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q1;
+	uint8_t dummy333[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q2;
+	uint8_t dummy334[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q3;
+	uint8_t dummy335[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q4;
+	uint8_t dummy336[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q5;
+	uint8_t dummy337[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q6;
+	uint8_t dummy338[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TXQ_THD_DROP_Q7;
+	uint8_t dummy339[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q0;
+	uint8_t dummy340[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q1;
+	uint8_t dummy341[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q2;
+	uint8_t dummy342[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q3;
+	uint8_t dummy343[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q4;
+	uint8_t dummy344[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q5;
+	uint8_t dummy345[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q6;
+	uint8_t dummy346[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_HYST_Q7;
+	uint8_t dummy347[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q0;
+	uint8_t dummy348[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q1;
+	uint8_t dummy349[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q2;
+	uint8_t dummy350[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q3;
+	uint8_t dummy351[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q4;
+	uint8_t dummy352[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q5;
+	uint8_t dummy353[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q6;
+	uint8_t dummy354[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_PAUSE_Q7;
+	uint8_t dummy355[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q0;
+	uint8_t dummy356[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q1;
+	uint8_t dummy357[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q2;
+	uint8_t dummy358[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q3;
+	uint8_t dummy359[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q4;
+	uint8_t dummy360[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q5;
+	uint8_t dummy361[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q6;
+	uint8_t dummy362[12];
+	uint32_t SWITCH_CORE_FC_IMP0_TOTAL_THD_DROP_Q7;
+	uint8_t dummy363[12];
+	uint32_t SWITCH_CORE_FC_IMP0_REG_SPARE0;
+	uint8_t dummy364[12];
+	uint32_t SWITCH_CORE_FC_IMP0_REG_SPARE1;
+	uint8_t dummy365[1132];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q0;
+	uint8_t dummy366[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q1;
+	uint8_t dummy367[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q2;
+	uint8_t dummy368[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q3;
+	uint8_t dummy369[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q4;
+	uint8_t dummy370[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q5;
+	uint8_t dummy371[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q6;
+	uint8_t dummy372[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_RSV_Q7;
+	uint8_t dummy373[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q0;
+	uint8_t dummy374[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q1;
+	uint8_t dummy375[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q2;
+	uint8_t dummy376[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q3;
+	uint8_t dummy377[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q4;
+	uint8_t dummy378[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q5;
+	uint8_t dummy379[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q6;
+	uint8_t dummy380[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_HYST_Q7;
+	uint8_t dummy381[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0;
+	uint8_t dummy382[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1;
+	uint8_t dummy383[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2;
+	uint8_t dummy384[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3;
+	uint8_t dummy385[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4;
+	uint8_t dummy386[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5;
+	uint8_t dummy387[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6;
+	uint8_t dummy388[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7;
+	uint8_t dummy389[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q0;
+	uint8_t dummy390[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q1;
+	uint8_t dummy391[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q2;
+	uint8_t dummy392[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q3;
+	uint8_t dummy393[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q4;
+	uint8_t dummy394[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q5;
+	uint8_t dummy395[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q6;
+	uint8_t dummy396[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TXQ_THD_DROP_Q7;
+	uint8_t dummy397[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q0;
+	uint8_t dummy398[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q1;
+	uint8_t dummy399[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q2;
+	uint8_t dummy400[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q3;
+	uint8_t dummy401[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q4;
+	uint8_t dummy402[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q5;
+	uint8_t dummy403[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q6;
+	uint8_t dummy404[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_HYST_Q7;
+	uint8_t dummy405[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0;
+	uint8_t dummy406[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1;
+	uint8_t dummy407[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2;
+	uint8_t dummy408[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3;
+	uint8_t dummy409[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4;
+	uint8_t dummy410[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5;
+	uint8_t dummy411[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6;
+	uint8_t dummy412[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7;
+	uint8_t dummy413[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q0;
+	uint8_t dummy414[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q1;
+	uint8_t dummy415[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q2;
+	uint8_t dummy416[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q3;
+	uint8_t dummy417[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q4;
+	uint8_t dummy418[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q5;
+	uint8_t dummy419[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q6;
+	uint8_t dummy420[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_TOTAL_THD_DROP_Q7;
+	uint8_t dummy421[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_REG_SPARE0;
+	uint8_t dummy422[12];
+	uint32_t SWITCH_CORE_FC_WAN_IMP1_REG_SPARE1;
+	uint8_t dummy423[35948];
+	uint32_t SWITCH_CORE_TxOctets_P0;
+	uint8_t dummy424[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P0;
+	uint8_t dummy425[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P0;
+	uint8_t dummy426[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P0;
+	uint8_t dummy427[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P0;
+	uint8_t dummy428[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P0;
+	uint8_t dummy429[28];
+	uint32_t SWITCH_CORE_TxCollisions_P0;
+	uint8_t dummy430[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P0;
+	uint8_t dummy431[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P0;
+	uint8_t dummy432[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P0;
+	uint8_t dummy433[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P0;
+	uint8_t dummy434[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P0;
+	uint8_t dummy435[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P0;
+	uint8_t dummy436[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P0;
+	uint8_t dummy437[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P0;
+	uint8_t dummy438[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P0;
+	uint8_t dummy439[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P0;
+	uint8_t dummy440[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P0;
+	uint8_t dummy441[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P0;
+	uint8_t dummy442[28];
+	uint32_t SWITCH_CORE_RxOctets_P0;
+	uint8_t dummy443[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P0;
+	uint8_t dummy444[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P0;
+	uint8_t dummy445[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P0;
+	uint8_t dummy446[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P0;
+	uint8_t dummy447[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P0;
+	uint8_t dummy448[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P0;
+	uint8_t dummy449[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P0;
+	uint8_t dummy450[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P0;
+	uint8_t dummy451[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P0;
+	uint8_t dummy452[28];
+	uint32_t SWITCH_CORE_RxJabbers_P0;
+	uint8_t dummy453[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P0;
+	uint8_t dummy454[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P0;
+	uint8_t dummy455[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P0;
+	uint8_t dummy456[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P0;
+	uint8_t dummy457[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P0;
+	uint8_t dummy458[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P0;
+	uint8_t dummy459[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P0;
+	uint8_t dummy460[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P0;
+	uint8_t dummy461[28];
+	uint32_t SWITCH_CORE_RxFragments_P0;
+	uint8_t dummy462[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P0;
+	uint8_t dummy463[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P0;
+	uint8_t dummy464[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P0;
+	uint8_t dummy465[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P0;
+	uint8_t dummy466[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P0;
+	uint8_t dummy467[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P0;
+	uint8_t dummy468[28];
+	uint32_t SWITCH_CORE_RxDiscard_P0;
+	uint8_t dummy469[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P0;
+	uint8_t dummy470[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P0;
+	uint8_t dummy471[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P0;
+	uint8_t dummy472[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P0;
+	uint8_t dummy473[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P0;
+	uint8_t dummy474[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P0;
+	uint8_t dummy475[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P0;
+	uint8_t dummy476[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P0;
+	uint8_t dummy477[220];
+	uint32_t SWITCH_CORE_TxOctets_P1;
+	uint8_t dummy478[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P1;
+	uint8_t dummy479[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P1;
+	uint8_t dummy480[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P1;
+	uint8_t dummy481[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P1;
+	uint8_t dummy482[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P1;
+	uint8_t dummy483[28];
+	uint32_t SWITCH_CORE_TxCollisions_P1;
+	uint8_t dummy484[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P1;
+	uint8_t dummy485[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P1;
+	uint8_t dummy486[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P1;
+	uint8_t dummy487[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P1;
+	uint8_t dummy488[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P1;
+	uint8_t dummy489[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P1;
+	uint8_t dummy490[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P1;
+	uint8_t dummy491[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P1;
+	uint8_t dummy492[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P1;
+	uint8_t dummy493[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P1;
+	uint8_t dummy494[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P1;
+	uint8_t dummy495[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P1;
+	uint8_t dummy496[28];
+	uint32_t SWITCH_CORE_RxOctets_P1;
+	uint8_t dummy497[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P1;
+	uint8_t dummy498[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P1;
+	uint8_t dummy499[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P1;
+	uint8_t dummy500[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P1;
+	uint8_t dummy501[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P1;
+	uint8_t dummy502[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P1;
+	uint8_t dummy503[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P1;
+	uint8_t dummy504[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P1;
+	uint8_t dummy505[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P1;
+	uint8_t dummy506[28];
+	uint32_t SWITCH_CORE_RxJabbers_P1;
+	uint8_t dummy507[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P1;
+	uint8_t dummy508[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P1;
+	uint8_t dummy509[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P1;
+	uint8_t dummy510[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P1;
+	uint8_t dummy511[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P1;
+	uint8_t dummy512[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P1;
+	uint8_t dummy513[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P1;
+	uint8_t dummy514[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P1;
+	uint8_t dummy515[28];
+	uint32_t SWITCH_CORE_RxFragments_P1;
+	uint8_t dummy516[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P1;
+	uint8_t dummy517[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P1;
+	uint8_t dummy518[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P1;
+	uint8_t dummy519[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P1;
+	uint8_t dummy520[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P1;
+	uint8_t dummy521[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P1;
+	uint8_t dummy522[28];
+	uint32_t SWITCH_CORE_RxDiscard_P1;
+	uint8_t dummy523[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P1;
+	uint8_t dummy524[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P1;
+	uint8_t dummy525[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P1;
+	uint8_t dummy526[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P1;
+	uint8_t dummy527[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P1;
+	uint8_t dummy528[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P1;
+	uint8_t dummy529[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P1;
+	uint8_t dummy530[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P1;
+	uint8_t dummy531[220];
+	uint32_t SWITCH_CORE_TxOctets_P2;
+	uint8_t dummy532[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P2;
+	uint8_t dummy533[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P2;
+	uint8_t dummy534[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P2;
+	uint8_t dummy535[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P2;
+	uint8_t dummy536[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P2;
+	uint8_t dummy537[28];
+	uint32_t SWITCH_CORE_TxCollisions_P2;
+	uint8_t dummy538[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P2;
+	uint8_t dummy539[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P2;
+	uint8_t dummy540[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P2;
+	uint8_t dummy541[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P2;
+	uint8_t dummy542[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P2;
+	uint8_t dummy543[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P2;
+	uint8_t dummy544[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P2;
+	uint8_t dummy545[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P2;
+	uint8_t dummy546[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P2;
+	uint8_t dummy547[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P2;
+	uint8_t dummy548[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P2;
+	uint8_t dummy549[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P2;
+	uint8_t dummy550[28];
+	uint32_t SWITCH_CORE_RxOctets_P2;
+	uint8_t dummy551[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P2;
+	uint8_t dummy552[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P2;
+	uint8_t dummy553[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P2;
+	uint8_t dummy554[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P2;
+	uint8_t dummy555[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P2;
+	uint8_t dummy556[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P2;
+	uint8_t dummy557[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P2;
+	uint8_t dummy558[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P2;
+	uint8_t dummy559[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P2;
+	uint8_t dummy560[28];
+	uint32_t SWITCH_CORE_RxJabbers_P2;
+	uint8_t dummy561[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P2;
+	uint8_t dummy562[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P2;
+	uint8_t dummy563[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P2;
+	uint8_t dummy564[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P2;
+	uint8_t dummy565[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P2;
+	uint8_t dummy566[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P2;
+	uint8_t dummy567[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P2;
+	uint8_t dummy568[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P2;
+	uint8_t dummy569[28];
+	uint32_t SWITCH_CORE_RxFragments_P2;
+	uint8_t dummy570[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P2;
+	uint8_t dummy571[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P2;
+	uint8_t dummy572[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P2;
+	uint8_t dummy573[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P2;
+	uint8_t dummy574[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P2;
+	uint8_t dummy575[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P2;
+	uint8_t dummy576[28];
+	uint32_t SWITCH_CORE_RxDiscard_P2;
+	uint8_t dummy577[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P2;
+	uint8_t dummy578[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P2;
+	uint8_t dummy579[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P2;
+	uint8_t dummy580[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P2;
+	uint8_t dummy581[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P2;
+	uint8_t dummy582[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P2;
+	uint8_t dummy583[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P2;
+	uint8_t dummy584[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P2;
+	uint8_t dummy585[220];
+	uint32_t SWITCH_CORE_TxOctets_P3;
+	uint8_t dummy586[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P3;
+	uint8_t dummy587[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P3;
+	uint8_t dummy588[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P3;
+	uint8_t dummy589[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P3;
+	uint8_t dummy590[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P3;
+	uint8_t dummy591[28];
+	uint32_t SWITCH_CORE_TxCollisions_P3;
+	uint8_t dummy592[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P3;
+	uint8_t dummy593[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P3;
+	uint8_t dummy594[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P3;
+	uint8_t dummy595[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P3;
+	uint8_t dummy596[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P3;
+	uint8_t dummy597[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P3;
+	uint8_t dummy598[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P3;
+	uint8_t dummy599[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P3;
+	uint8_t dummy600[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P3;
+	uint8_t dummy601[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P3;
+	uint8_t dummy602[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P3;
+	uint8_t dummy603[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P3;
+	uint8_t dummy604[28];
+	uint32_t SWITCH_CORE_RxOctets_P3;
+	uint8_t dummy605[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P3;
+	uint8_t dummy606[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P3;
+	uint8_t dummy607[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P3;
+	uint8_t dummy608[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P3;
+	uint8_t dummy609[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P3;
+	uint8_t dummy610[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P3;
+	uint8_t dummy611[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P3;
+	uint8_t dummy612[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P3;
+	uint8_t dummy613[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P3;
+	uint8_t dummy614[28];
+	uint32_t SWITCH_CORE_RxJabbers_P3;
+	uint8_t dummy615[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P3;
+	uint8_t dummy616[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P3;
+	uint8_t dummy617[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P3;
+	uint8_t dummy618[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P3;
+	uint8_t dummy619[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P3;
+	uint8_t dummy620[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P3;
+	uint8_t dummy621[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P3;
+	uint8_t dummy622[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P3;
+	uint8_t dummy623[28];
+	uint32_t SWITCH_CORE_RxFragments_P3;
+	uint8_t dummy624[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P3;
+	uint8_t dummy625[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P3;
+	uint8_t dummy626[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P3;
+	uint8_t dummy627[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P3;
+	uint8_t dummy628[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P3;
+	uint8_t dummy629[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P3;
+	uint8_t dummy630[28];
+	uint32_t SWITCH_CORE_RxDiscard_P3;
+	uint8_t dummy631[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P3;
+	uint8_t dummy632[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P3;
+	uint8_t dummy633[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P3;
+	uint8_t dummy634[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P3;
+	uint8_t dummy635[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P3;
+	uint8_t dummy636[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P3;
+	uint8_t dummy637[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P3;
+	uint8_t dummy638[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P3;
+	uint8_t dummy639[220];
+	uint32_t SWITCH_CORE_TxOctets_P4;
+	uint8_t dummy640[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P4;
+	uint8_t dummy641[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P4;
+	uint8_t dummy642[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P4;
+	uint8_t dummy643[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P4;
+	uint8_t dummy644[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P4;
+	uint8_t dummy645[28];
+	uint32_t SWITCH_CORE_TxCollisions_P4;
+	uint8_t dummy646[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P4;
+	uint8_t dummy647[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P4;
+	uint8_t dummy648[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P4;
+	uint8_t dummy649[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P4;
+	uint8_t dummy650[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P4;
+	uint8_t dummy651[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P4;
+	uint8_t dummy652[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P4;
+	uint8_t dummy653[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P4;
+	uint8_t dummy654[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P4;
+	uint8_t dummy655[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P4;
+	uint8_t dummy656[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P4;
+	uint8_t dummy657[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P4;
+	uint8_t dummy658[28];
+	uint32_t SWITCH_CORE_RxOctets_P4;
+	uint8_t dummy659[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P4;
+	uint8_t dummy660[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P4;
+	uint8_t dummy661[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P4;
+	uint8_t dummy662[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P4;
+	uint8_t dummy663[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P4;
+	uint8_t dummy664[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P4;
+	uint8_t dummy665[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P4;
+	uint8_t dummy666[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P4;
+	uint8_t dummy667[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P4;
+	uint8_t dummy668[28];
+	uint32_t SWITCH_CORE_RxJabbers_P4;
+	uint8_t dummy669[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P4;
+	uint8_t dummy670[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P4;
+	uint8_t dummy671[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P4;
+	uint8_t dummy672[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P4;
+	uint8_t dummy673[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P4;
+	uint8_t dummy674[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P4;
+	uint8_t dummy675[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P4;
+	uint8_t dummy676[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P4;
+	uint8_t dummy677[28];
+	uint32_t SWITCH_CORE_RxFragments_P4;
+	uint8_t dummy678[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P4;
+	uint8_t dummy679[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P4;
+	uint8_t dummy680[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P4;
+	uint8_t dummy681[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P4;
+	uint8_t dummy682[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P4;
+	uint8_t dummy683[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P4;
+	uint8_t dummy684[28];
+	uint32_t SWITCH_CORE_RxDiscard_P4;
+	uint8_t dummy685[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P4;
+	uint8_t dummy686[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P4;
+	uint8_t dummy687[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P4;
+	uint8_t dummy688[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P4;
+	uint8_t dummy689[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P4;
+	uint8_t dummy690[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P4;
+	uint8_t dummy691[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P4;
+	uint8_t dummy692[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P4;
+	uint8_t dummy693[220];
+	uint32_t SWITCH_CORE_TxOctets_P5;
+	uint8_t dummy694[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P5;
+	uint8_t dummy695[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P5;
+	uint8_t dummy696[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P5;
+	uint8_t dummy697[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P5;
+	uint8_t dummy698[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P5;
+	uint8_t dummy699[28];
+	uint32_t SWITCH_CORE_TxCollisions_P5;
+	uint8_t dummy700[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P5;
+	uint8_t dummy701[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P5;
+	uint8_t dummy702[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P5;
+	uint8_t dummy703[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P5;
+	uint8_t dummy704[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P5;
+	uint8_t dummy705[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P5;
+	uint8_t dummy706[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P5;
+	uint8_t dummy707[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P5;
+	uint8_t dummy708[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P5;
+	uint8_t dummy709[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P5;
+	uint8_t dummy710[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P5;
+	uint8_t dummy711[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P5;
+	uint8_t dummy712[28];
+	uint32_t SWITCH_CORE_RxOctets_P5;
+	uint8_t dummy713[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P5;
+	uint8_t dummy714[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P5;
+	uint8_t dummy715[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P5;
+	uint8_t dummy716[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P5;
+	uint8_t dummy717[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P5;
+	uint8_t dummy718[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P5;
+	uint8_t dummy719[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P5;
+	uint8_t dummy720[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P5;
+	uint8_t dummy721[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P5;
+	uint8_t dummy722[28];
+	uint32_t SWITCH_CORE_RxJabbers_P5;
+	uint8_t dummy723[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P5;
+	uint8_t dummy724[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P5;
+	uint8_t dummy725[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P5;
+	uint8_t dummy726[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P5;
+	uint8_t dummy727[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P5;
+	uint8_t dummy728[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P5;
+	uint8_t dummy729[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P5;
+	uint8_t dummy730[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P5;
+	uint8_t dummy731[28];
+	uint32_t SWITCH_CORE_RxFragments_P5;
+	uint8_t dummy732[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P5;
+	uint8_t dummy733[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P5;
+	uint8_t dummy734[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P5;
+	uint8_t dummy735[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P5;
+	uint8_t dummy736[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P5;
+	uint8_t dummy737[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P5;
+	uint8_t dummy738[28];
+	uint32_t SWITCH_CORE_RxDiscard_P5;
+	uint8_t dummy739[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P5;
+	uint8_t dummy740[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P5;
+	uint8_t dummy741[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P5;
+	uint8_t dummy742[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P5;
+	uint8_t dummy743[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P5;
+	uint8_t dummy744[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P5;
+	uint8_t dummy745[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P5;
+	uint8_t dummy746[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P5;
+	uint8_t dummy747[220];
+	uint32_t SWITCH_CORE_TxOctets_P6;
+	uint8_t dummy748[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P6;
+	uint8_t dummy749[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P6;
+	uint8_t dummy750[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P6;
+	uint8_t dummy751[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P6;
+	uint8_t dummy752[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P6;
+	uint8_t dummy753[28];
+	uint32_t SWITCH_CORE_TxCollisions_P6;
+	uint8_t dummy754[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P6;
+	uint8_t dummy755[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P6;
+	uint8_t dummy756[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P6;
+	uint8_t dummy757[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P6;
+	uint8_t dummy758[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P6;
+	uint8_t dummy759[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P6;
+	uint8_t dummy760[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P6;
+	uint8_t dummy761[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P6;
+	uint8_t dummy762[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P6;
+	uint8_t dummy763[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P6;
+	uint8_t dummy764[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P6;
+	uint8_t dummy765[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P6;
+	uint8_t dummy766[28];
+	uint32_t SWITCH_CORE_RxOctets_P6;
+	uint8_t dummy767[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P6;
+	uint8_t dummy768[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P6;
+	uint8_t dummy769[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P6;
+	uint8_t dummy770[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P6;
+	uint8_t dummy771[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P6;
+	uint8_t dummy772[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P6;
+	uint8_t dummy773[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P6;
+	uint8_t dummy774[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P6;
+	uint8_t dummy775[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P6;
+	uint8_t dummy776[28];
+	uint32_t SWITCH_CORE_RxJabbers_P6;
+	uint8_t dummy777[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P6;
+	uint8_t dummy778[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P6;
+	uint8_t dummy779[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P6;
+	uint8_t dummy780[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P6;
+	uint8_t dummy781[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P6;
+	uint8_t dummy782[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P6;
+	uint8_t dummy783[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P6;
+	uint8_t dummy784[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P6;
+	uint8_t dummy785[28];
+	uint32_t SWITCH_CORE_RxFragments_P6;
+	uint8_t dummy786[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P6;
+	uint8_t dummy787[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P6;
+	uint8_t dummy788[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P6;
+	uint8_t dummy789[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P6;
+	uint8_t dummy790[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P6;
+	uint8_t dummy791[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P6;
+	uint8_t dummy792[28];
+	uint32_t SWITCH_CORE_RxDiscard_P6;
+	uint8_t dummy793[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P6;
+	uint8_t dummy794[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P6;
+	uint8_t dummy795[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P6;
+	uint8_t dummy796[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P6;
+	uint8_t dummy797[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P6;
+	uint8_t dummy798[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P6;
+	uint8_t dummy799[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P6;
+	uint8_t dummy800[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P6;
+	uint8_t dummy801[220];
+	uint32_t SWITCH_CORE_TxOctets_P7;
+	uint8_t dummy802[60];
+	uint32_t SWITCH_CORE_TxDropPkts_P7;
+	uint8_t dummy803[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_P7;
+	uint8_t dummy804[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_P7;
+	uint8_t dummy805[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_P7;
+	uint8_t dummy806[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_P7;
+	uint8_t dummy807[28];
+	uint32_t SWITCH_CORE_TxCollisions_P7;
+	uint8_t dummy808[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_P7;
+	uint8_t dummy809[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_P7;
+	uint8_t dummy810[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_P7;
+	uint8_t dummy811[28];
+	uint32_t SWITCH_CORE_TxLateCollision_P7;
+	uint8_t dummy812[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_P7;
+	uint8_t dummy813[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_P7;
+	uint8_t dummy814[28];
+	uint32_t SWITCH_CORE_TxPausePkts_P7;
+	uint8_t dummy815[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_P7;
+	uint8_t dummy816[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_P7;
+	uint8_t dummy817[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_P7;
+	uint8_t dummy818[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_P7;
+	uint8_t dummy819[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_P7;
+	uint8_t dummy820[28];
+	uint32_t SWITCH_CORE_RxOctets_P7;
+	uint8_t dummy821[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_P7;
+	uint8_t dummy822[28];
+	uint32_t SWITCH_CORE_RxPausePkts_P7;
+	uint8_t dummy823[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_P7;
+	uint8_t dummy824[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_P7;
+	uint8_t dummy825[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_P7;
+	uint8_t dummy826[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_P7;
+	uint8_t dummy827[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_P7;
+	uint8_t dummy828[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_P7;
+	uint8_t dummy829[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_P7;
+	uint8_t dummy830[28];
+	uint32_t SWITCH_CORE_RxJabbers_P7;
+	uint8_t dummy831[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_P7;
+	uint8_t dummy832[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_P7;
+	uint8_t dummy833[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_P7;
+	uint8_t dummy834[60];
+	uint32_t SWITCH_CORE_RxDropPkts_P7;
+	uint8_t dummy835[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_P7;
+	uint8_t dummy836[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_P7;
+	uint8_t dummy837[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_P7;
+	uint8_t dummy838[28];
+	uint32_t SWITCH_CORE_RxSAChanges_P7;
+	uint8_t dummy839[28];
+	uint32_t SWITCH_CORE_RxFragments_P7;
+	uint8_t dummy840[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_P7;
+	uint8_t dummy841[28];
+	uint32_t SWITCH_CORE_RxSymblErr_P7;
+	uint8_t dummy842[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_P7;
+	uint8_t dummy843[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_P7;
+	uint8_t dummy844[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_P7;
+	uint8_t dummy845[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_P7;
+	uint8_t dummy846[28];
+	uint32_t SWITCH_CORE_RxDiscard_P7;
+	uint8_t dummy847[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_P7;
+	uint8_t dummy848[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_P7;
+	uint8_t dummy849[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_P7;
+	uint8_t dummy850[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_P7;
+	uint8_t dummy851[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_P7;
+	uint8_t dummy852[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_P7;
+	uint8_t dummy853[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_P7;
+	uint8_t dummy854[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_P7;
+	uint8_t dummy855[220];
+	uint32_t SWITCH_CORE_TxOctets_IMP;
+	uint8_t dummy856[60];
+	uint32_t SWITCH_CORE_TxDropPkts_IMP;
+	uint8_t dummy857[28];
+	uint32_t SWITCH_CORE_TxQPKTQ0_IMP;
+	uint8_t dummy858[28];
+	uint32_t SWITCH_CORE_TxBroadcastPkts_IMP;
+	uint8_t dummy859[28];
+	uint32_t SWITCH_CORE_TxMulticastPkts_IMP;
+	uint8_t dummy860[28];
+	uint32_t SWITCH_CORE_TxUnicastPkts_IMP;
+	uint8_t dummy861[28];
+	uint32_t SWITCH_CORE_TxCollisions_IMP;
+	uint8_t dummy862[28];
+	uint32_t SWITCH_CORE_TxSingleCollision_IMP;
+	uint8_t dummy863[28];
+	uint32_t SWITCH_CORE_TxMultipleCollision_IMP;
+	uint8_t dummy864[28];
+	uint32_t SWITCH_CORE_TxDeferredTransmit_IMP;
+	uint8_t dummy865[28];
+	uint32_t SWITCH_CORE_TxLateCollision_IMP;
+	uint8_t dummy866[28];
+	uint32_t SWITCH_CORE_TxExcessiveCollision_IMP;
+	uint8_t dummy867[28];
+	uint32_t SWITCH_CORE_TxFrameInDisc_IMP;
+	uint8_t dummy868[28];
+	uint32_t SWITCH_CORE_TxPausePkts_IMP;
+	uint8_t dummy869[28];
+	uint32_t SWITCH_CORE_TxQPKTQ1_IMP;
+	uint8_t dummy870[28];
+	uint32_t SWITCH_CORE_TxQPKTQ2_IMP;
+	uint8_t dummy871[28];
+	uint32_t SWITCH_CORE_TxQPKTQ3_IMP;
+	uint8_t dummy872[28];
+	uint32_t SWITCH_CORE_TxQPKTQ4_IMP;
+	uint8_t dummy873[28];
+	uint32_t SWITCH_CORE_TxQPKTQ5_IMP;
+	uint8_t dummy874[28];
+	uint32_t SWITCH_CORE_RxOctets_IMP;
+	uint8_t dummy875[60];
+	uint32_t SWITCH_CORE_RxUndersizePkts_IMP;
+	uint8_t dummy876[28];
+	uint32_t SWITCH_CORE_RxPausePkts_IMP;
+	uint8_t dummy877[28];
+	uint32_t SWITCH_CORE_RxPkts64Octets_IMP;
+	uint8_t dummy878[28];
+	uint32_t SWITCH_CORE_RxPkts65to127Octets_IMP;
+	uint8_t dummy879[28];
+	uint32_t SWITCH_CORE_RxPkts128to255Octets_IMP;
+	uint8_t dummy880[28];
+	uint32_t SWITCH_CORE_RxPkts256to511Octets_IMP;
+	uint8_t dummy881[28];
+	uint32_t SWITCH_CORE_RxPkts512to1023Octets_IMP;
+	uint8_t dummy882[28];
+	uint32_t SWITCH_CORE_RxPkts1024toMaxPktOctets_IMP;
+	uint8_t dummy883[28];
+	uint32_t SWITCH_CORE_RxOversizePkts_IMP;
+	uint8_t dummy884[28];
+	uint32_t SWITCH_CORE_RxJabbers_IMP;
+	uint8_t dummy885[28];
+	uint32_t SWITCH_CORE_RxAlignmentErrors_IMP;
+	uint8_t dummy886[28];
+	uint32_t SWITCH_CORE_RxFCSErrors_IMP;
+	uint8_t dummy887[28];
+	uint32_t SWITCH_CORE_RxGoodOctets_IMP;
+	uint8_t dummy888[60];
+	uint32_t SWITCH_CORE_RxDropPkts_IMP;
+	uint8_t dummy889[28];
+	uint32_t SWITCH_CORE_RxUnicastPkts_IMP;
+	uint8_t dummy890[28];
+	uint32_t SWITCH_CORE_RxMulticastPkts_IMP;
+	uint8_t dummy891[28];
+	uint32_t SWITCH_CORE_RxBroadcastPkts_IMP;
+	uint8_t dummy892[28];
+	uint32_t SWITCH_CORE_RxSAChanges_IMP;
+	uint8_t dummy893[28];
+	uint32_t SWITCH_CORE_RxFragments_IMP;
+	uint8_t dummy894[28];
+	uint32_t SWITCH_CORE_RxJumboPkt_IMP;
+	uint8_t dummy895[28];
+	uint32_t SWITCH_CORE_RxSymblErr_IMP;
+	uint8_t dummy896[28];
+	uint32_t SWITCH_CORE_InRangeErrCount_IMP;
+	uint8_t dummy897[28];
+	uint32_t SWITCH_CORE_OutRangeErrCount_IMP;
+	uint8_t dummy898[28];
+	uint32_t SWITCH_CORE_EEE_LPI_EVENT_IMP;
+	uint8_t dummy899[28];
+	uint32_t SWITCH_CORE_EEE_LPI_DURATION_IMP;
+	uint8_t dummy900[28];
+	uint32_t SWITCH_CORE_RxDiscard_IMP;
+	uint8_t dummy901[60];
+	uint32_t SWITCH_CORE_TxQPKTQ6_IMP;
+	uint8_t dummy902[28];
+	uint32_t SWITCH_CORE_TxQPKTQ7_IMP;
+	uint8_t dummy903[28];
+	uint32_t SWITCH_CORE_TxPkts64Octets_IMP;
+	uint8_t dummy904[28];
+	uint32_t SWITCH_CORE_TxPkts65to127Octets_IMP;
+	uint8_t dummy905[28];
+	uint32_t SWITCH_CORE_TxPkts128to255Octets_IMP;
+	uint8_t dummy906[28];
+	uint32_t SWITCH_CORE_TxPkts256to511Octets_IMP;
+	uint8_t dummy907[28];
+	uint32_t SWITCH_CORE_TxPkts512to1023Octets_IMP;
+	uint8_t dummy908[28];
+	uint32_t SWITCH_CORE_TxPkts1024toMaxPktOctets_IMP;
+	uint8_t dummy909[14556];
+	uint32_t SWITCH_CORE_QOS_GLOBAL_CTRL;
+	uint8_t dummy910[28];
+	uint32_t SWITCH_CORE_QOS_1P_EN;
+	uint8_t dummy911[12];
+	uint32_t SWITCH_CORE_QOS_EN_DIFFSERV;
+	uint8_t dummy912[76];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P0;
+	uint8_t dummy913[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P1;
+	uint8_t dummy914[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P2;
+	uint8_t dummy915[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P3;
+	uint8_t dummy916[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P4;
+	uint8_t dummy917[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P5;
+	uint8_t dummy918[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P6;
+	uint8_t dummy919[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_P7;
+	uint8_t dummy920[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI0_IMP;
+	uint8_t dummy921[28];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP0;
+	uint8_t dummy922[44];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP1;
+	uint8_t dummy923[44];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP2;
+	uint8_t dummy924[44];
+	uint32_t SWITCH_CORE_QOS_DIFF_DSCP3;
+	uint8_t dummy925[44];
+	uint32_t SWITCH_CORE_PID2TC;
+	uint8_t dummy926[60];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P0;
+	uint8_t dummy927[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P1;
+	uint8_t dummy928[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P2;
+	uint8_t dummy929[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P3;
+	uint8_t dummy930[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P4;
+	uint8_t dummy931[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P5;
+	uint8_t dummy932[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P6;
+	uint8_t dummy933[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_P7;
+	uint8_t dummy934[12];
+	uint32_t SWITCH_CORE_TC_SEL_TABLE_IMP;
+	uint8_t dummy935[28];
+	uint32_t SWITCH_CORE_CPU2COS_MAP;
+	uint8_t dummy936[60];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P0;
+	uint8_t dummy937[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P1;
+	uint8_t dummy938[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P2;
+	uint8_t dummy939[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P3;
+	uint8_t dummy940[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P4;
+	uint8_t dummy941[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P5;
+	uint8_t dummy942[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P6;
+	uint8_t dummy943[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_P7;
+	uint8_t dummy944[28];
+	uint32_t SWITCH_CORE_TC2COS_MAP_IMP;
+	uint8_t dummy945[188];
+	uint32_t SWITCH_CORE_QOS_REG_SPARE0;
+	uint8_t dummy946[28];
+	uint32_t SWITCH_CORE_QOS_REG_SPARE1;
+	uint8_t dummy947[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P0;
+	uint8_t dummy948[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P1;
+	uint8_t dummy949[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P2;
+	uint8_t dummy950[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P3;
+	uint8_t dummy951[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P4;
+	uint8_t dummy952[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P5;
+	uint8_t dummy953[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P6;
+	uint8_t dummy954[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_P7;
+	uint8_t dummy955[28];
+	uint32_t SWITCH_CORE_PCP2TC_DEI1_IMP;
+	uint8_t dummy956[380];
+	uint32_t port_vlan_ctrl[4*9];
+	uint8_t dummy965[112];
+	uint32_t SWITCH_CORE_VLAN_REG_SPARE0;
+	uint8_t dummy966[28];
+	uint32_t SWITCH_CORE_VLAN_REG_SPARE1;
+	uint8_t dummy967[1756];
+	uint32_t SWITCH_CORE_MAC_TRUNK_CTL;
+	uint8_t dummy968[12];
+	uint32_t SWITCH_CORE_IMP0_GRP_CTL;
+	uint8_t dummy969[108];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL0;
+	uint8_t dummy970[12];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL1;
+	uint8_t dummy971[12];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL2;
+	uint8_t dummy972[12];
+	uint32_t SWITCH_CORE_TRUNK_GRP_CTL3;
+	uint8_t dummy973[76];
+	uint32_t SWITCH_CORE_TRUNK_HASH_OVRRD;
+	uint8_t dummy974[252];
+	uint32_t SWITCH_CORE_TRUNK_REG_SPARE0;
+	uint8_t dummy975[28];
+	uint32_t SWITCH_CORE_TRUNK_REG_SPARE1;
+	uint8_t dummy976[3548];
+	uint64_t SWITCH_CORE_VLAN_CTRL0;
+	uint64_t SWITCH_CORE_VLAN_CTRL1;
+	uint64_t SWITCH_CORE_VLAN_CTRL2;
+	uint32_t SWITCH_CORE_VLAN_CTRL3;
+	uint8_t dummy977[12];
+	uint64_t SWITCH_CORE_VLAN_CTRL4;
+	uint64_t SWITCH_CORE_VLAN_CTRL5;
+	uint32_t SWITCH_CORE_VLAN_CTRL6;
+	uint8_t dummy978[20];
+	uint32_t SWITCH_CORE_VLAN_MULTI_PORT_ADDR_CTL;
+	uint8_t dummy979[44];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P0;
+	uint8_t dummy980[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P1;
+	uint8_t dummy981[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P2;
+	uint8_t dummy982[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P3;
+	uint8_t dummy983[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P4;
+	uint8_t dummy984[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P5;
+	uint8_t dummy985[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P6;
+	uint8_t dummy986[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_P7;
+	uint8_t dummy987[12];
+	uint32_t SWITCH_CORE_DEFAULT_1Q_TAG_IMP;
+	uint8_t dummy988[124];
+	uint32_t SWITCH_CORE_DTAG_TPID;
+	uint8_t dummy989[12];
+	uint32_t SWITCH_CORE_ISP_SEL_PORTMAP;
+	uint8_t dummy990[108];
+	uint32_t SWITCH_CORE_EGRESS_VID_RMK_TBL_ACS;
+	uint8_t dummy991[28];
+	uint32_t SWITCH_CORE_EGRESS_VID_RMK_TBL_DATA;
+	uint8_t dummy992[92];
+	uint32_t SWITCH_CORE_JOIN_ALL_VLAN_EN;
+	uint8_t dummy993[12];
+	uint32_t SWITCH_CORE_PORT_IVL_SVL_CTRL;
+	uint8_t dummy994[108];
+	uint32_t SWITCH_CORE_BCM8021Q_REG_SPARE0;
+	uint8_t dummy995[28];
+	uint32_t SWITCH_CORE_BCM8021Q_REG_SPARE1;
+	uint8_t dummy996[3292];
+	uint32_t SWITCH_CORE_DOS_CTRL;
+	uint8_t dummy997[28];
+	uint32_t SWITCH_CORE_MINIMUM_TCP_HDR_SZ;
+	uint8_t dummy998[28];
+	uint32_t SWITCH_CORE_MAX_ICMPV4_SIZE_REG;
+	uint8_t dummy999[28];
+	uint32_t SWITCH_CORE_MAX_ICMPV6_SIZE_REG;
+	uint8_t dummy1000[28];
+	uint32_t SWITCH_CORE_DOS_DIS_LRN_REG;
+	uint8_t dummy1001[124];
+	uint32_t SWITCH_CORE_DOS_REG_SPARE0;
+	uint8_t dummy1002[28];
+	uint32_t SWITCH_CORE_DOS_REG_SPARE1;
+	uint8_t dummy1003[20196];
+	uint32_t SWITCH_CORE_JUMBO_PORT_MASK;
+	uint8_t dummy1004[28];
+	uint32_t SWITCH_CORE_MIB_GD_FM_MAX_SIZE;
+	uint8_t dummy1005[84];
+	uint32_t SWITCH_CORE_JUMBO_CTRL_REG_SPARE0;
+	uint8_t dummy1006[28];
+	uint32_t SWITCH_CORE_JUMBO_CTRL_REG_SPARE1;
+	uint8_t dummy1007[1884];
+	uint32_t SWITCH_CORE_COMM_IRC_CON;
+	uint8_t dummy1008[28];
+	uint32_t SWITCH_CORE_IRC_VIRTUAL_ZERO_THD;
+	uint8_t dummy1009[12];
+	uint32_t SWITCH_CORE_IRC_ALARM_THD;
+	uint8_t dummy1010[76];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P0;
+	uint8_t dummy1011[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P1;
+	uint8_t dummy1012[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P2;
+	uint8_t dummy1013[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P3;
+	uint8_t dummy1014[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P4;
+	uint8_t dummy1015[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P5;
+	uint8_t dummy1016[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P6;
+	uint8_t dummy1017[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_P7;
+	uint8_t dummy1018[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_IMP;
+	uint8_t dummy1019[28];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P0;
+	uint8_t dummy1020[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P1;
+	uint8_t dummy1021[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P2;
+	uint8_t dummy1022[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P3;
+	uint8_t dummy1023[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P4;
+	uint8_t dummy1024[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P5;
+	uint8_t dummy1025[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P6;
+	uint8_t dummy1026[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_P7;
+	uint8_t dummy1027[12];
+	uint32_t SWITCH_CORE_BC_SUP_RATECTRL_1_IMP;
+	uint8_t dummy1028[92];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P0;
+	uint8_t dummy1029[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P1;
+	uint8_t dummy1030[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P2;
+	uint8_t dummy1031[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P3;
+	uint8_t dummy1032[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P4;
+	uint8_t dummy1033[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P5;
+	uint8_t dummy1034[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P6;
+	uint8_t dummy1035[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_P7;
+	uint8_t dummy1036[28];
+	uint32_t SWITCH_CORE_BC_SUP_PKTDROP_CNT_IMP;
+	uint8_t dummy1037[764];
+	uint32_t SWITCH_CORE_BC_SUPPRESS_REG_SPARE0;
+	uint8_t dummy1038[28];
+	uint32_t SWITCH_CORE_BC_SUPPRESS_REG_SPARE1;
+	uint8_t dummy1039[348];
+	uint64_t SWITCH_CORE_EAP_GLO_CON;
+	uint64_t SWITCH_CORE_EAP_MULTI_ADDR_CTRL;
+	uint32_t SWITCH_CORE_EAP_DIP0;
+	uint8_t dummy1040[60];
+	uint32_t SWITCH_CORE_EAP_DIP1;
+	uint8_t dummy1041[172];
+	uint32_t SWITCH_CORE_EAP_CON_P0;
+	uint8_t dummy1042[60];
+	uint32_t SWITCH_CORE_EAP_CON_P1;
+	uint8_t dummy1043[60];
+	uint32_t SWITCH_CORE_EAP_CON_P2;
+	uint8_t dummy1044[60];
+	uint32_t SWITCH_CORE_EAP_CON_P3;
+	uint8_t dummy1045[60];
+	uint32_t SWITCH_CORE_EAP_CON_P4;
+	uint8_t dummy1046[60];
+	uint32_t SWITCH_CORE_EAP_CON_P5;
+	uint8_t dummy1047[60];
+	uint32_t SWITCH_CORE_EAP_CON_P6;
+	uint8_t dummy1048[60];
+	uint32_t SWITCH_CORE_EAP_CON_P7;
+	uint8_t dummy1049[60];
+	uint32_t SWITCH_CORE_EAP_CON_IMP;
+	uint8_t dummy1050[124];
+	uint32_t SWITCH_CORE_IEEE8021X_REG_SPARE0;
+	uint8_t dummy1051[28];
+	uint32_t SWITCH_CORE_IEEE8021X_REG_SPARE1;
+	uint8_t dummy1052[1116];
+	uint32_t SWITCH_CORE_MST_CON;
+	uint8_t dummy1053[12];
+	uint32_t SWITCH_CORE_MST_AGE;
+	uint8_t dummy1054[108];
+	uint32_t SWITCH_CORE_MST_TAB0;
+	uint8_t dummy1055[28];
+	uint32_t SWITCH_CORE_MST_TAB1;
+	uint8_t dummy1056[28];
+	uint32_t SWITCH_CORE_MST_TAB2;
+	uint8_t dummy1057[28];
+	uint32_t SWITCH_CORE_MST_TAB3;
+	uint8_t dummy1058[28];
+	uint32_t SWITCH_CORE_MST_TAB4;
+	uint8_t dummy1059[28];
+	uint32_t SWITCH_CORE_MST_TAB5;
+	uint8_t dummy1060[28];
+	uint32_t SWITCH_CORE_MST_TAB6;
+	uint8_t dummy1061[28];
+	uint32_t SWITCH_CORE_MST_TAB7;
+	uint8_t dummy1062[284];
+	uint32_t SWITCH_CORE_SPT_MULTI_ADDR_BPS_CTRL;
+	uint8_t dummy1063[124];
+	uint32_t SWITCH_CORE_IEEE8021S_REG_SPARE0;
+	uint8_t dummy1064[28];
+	uint32_t SWITCH_CORE_IEEE8021S_REG_SPARE1;
+	uint8_t dummy1065[3292];
+	uint32_t SWITCH_CORE_SA_LIMIT_ENABLE;
+	uint8_t dummy1066[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_RST;
+	uint8_t dummy1067[12];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_RST;
+	uint8_t dummy1068[92];
+	uint32_t SWITCH_CORE_TOTAL_SA_LIMIT_CTL;
+	uint8_t dummy1069[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P0;
+	uint8_t dummy1070[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P1;
+	uint8_t dummy1071[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P2;
+	uint8_t dummy1072[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P3;
+	uint8_t dummy1073[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P4;
+	uint8_t dummy1074[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P5;
+	uint8_t dummy1075[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P6;
+	uint8_t dummy1076[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P7;
+	uint8_t dummy1077[12];
+	uint32_t SWITCH_CORE_SA_LIMIT_CTL_P8;
+	uint8_t dummy1078[108];
+	uint32_t SWITCH_CORE_TOTAL_SA_LRN_CNTR;
+	uint8_t dummy1079[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P0;
+	uint8_t dummy1080[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P1;
+	uint8_t dummy1081[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P2;
+	uint8_t dummy1082[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P3;
+	uint8_t dummy1083[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P4;
+	uint8_t dummy1084[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P5;
+	uint8_t dummy1085[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P6;
+	uint8_t dummy1086[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P7;
+	uint8_t dummy1087[12];
+	uint32_t SWITCH_CORE_SA_LRN_CNTR_P8;
+	uint8_t dummy1088[108];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P0;
+	uint8_t dummy1089[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P1;
+	uint8_t dummy1090[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P2;
+	uint8_t dummy1091[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P3;
+	uint8_t dummy1092[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P4;
+	uint8_t dummy1093[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P5;
+	uint8_t dummy1094[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P6;
+	uint8_t dummy1095[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P7;
+	uint8_t dummy1096[28];
+	uint32_t SWITCH_CORE_SA_OVERLIMIT_CNTR_P8;
+	uint8_t dummy1097[28];
+	uint32_t SWITCH_CORE_SA_OVER_LIMIT_COPY_REDIRECT;
+	uint8_t dummy1098[92];
+	uint32_t SWITCH_CORE_MAC_LIMIT_REG_SPARE0;
+	uint8_t dummy1099[28];
+	uint32_t SWITCH_CORE_MAC_LIMIT_REG_SPARE1;
+	uint8_t dummy1100[988];
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P0;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P1;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P2;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P3;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P4;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P5;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P6;
+	uint64_t SWITCH_CORE_QOS_PRI_CTL_P7;
+	uint32_t SWITCH_CORE_QOS_PRI_CTL_IMP;
+	uint8_t dummy1101[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P0;
+	uint8_t dummy1102[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P1;
+	uint8_t dummy1103[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P2;
+	uint8_t dummy1104[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P3;
+	uint8_t dummy1105[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P4;
+	uint8_t dummy1106[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P5;
+	uint8_t dummy1107[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P6;
+	uint8_t dummy1108[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_P7;
+	uint8_t dummy1109[60];
+	uint32_t SWITCH_CORE_QOS_WEIGHT_IMP;
+	uint8_t dummy1110[124];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P0;
+	uint8_t dummy1111[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P1;
+	uint8_t dummy1112[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P2;
+	uint8_t dummy1113[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P3;
+	uint8_t dummy1114[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P4;
+	uint8_t dummy1115[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P5;
+	uint8_t dummy1116[12];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P6;
+	uint8_t dummy1117[28];
+	uint32_t SWITCH_CORE_WDRR_PENALTY_P7;
+	uint8_t dummy1118[12];
+	uint32_t SWITCH_CORE_P8_WDRR_PENALTY;
+	uint8_t dummy1119[108];
+	uint32_t SWITCH_CORE_SCHEDULER_REG_SPARE0;
+	uint8_t dummy1120[28];
+	uint32_t SWITCH_CORE_SCHEDULER_REG_SPARE1;
+	uint8_t dummy1121[988];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P0;
+	uint8_t dummy1122[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P1;
+	uint8_t dummy1123[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P2;
+	uint8_t dummy1124[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P3;
+	uint8_t dummy1125[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P4;
+	uint8_t dummy1126[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P5;
+	uint8_t dummy1127[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P6;
+	uint8_t dummy1128[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_P7;
+	uint8_t dummy1129[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_IMP;
+	uint8_t dummy1130[124];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P0;
+	uint8_t dummy1131[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P1;
+	uint8_t dummy1132[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P2;
+	uint8_t dummy1133[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P3;
+	uint8_t dummy1134[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P4;
+	uint8_t dummy1135[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P5;
+	uint8_t dummy1136[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P6;
+	uint8_t dummy1137[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_P7;
+	uint8_t dummy1138[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_IMP;
+	uint8_t dummy1139[124];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P0;
+	uint8_t dummy1140[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P1;
+	uint8_t dummy1141[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P2;
+	uint8_t dummy1142[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P3;
+	uint8_t dummy1143[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P4;
+	uint8_t dummy1144[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P5;
+	uint8_t dummy1145[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P6;
+	uint8_t dummy1146[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_P7;
+	uint8_t dummy1147[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_STS_IMP;
+	uint8_t dummy1148[124];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P0;
+	uint8_t dummy1149[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P1;
+	uint8_t dummy1150[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P2;
+	uint8_t dummy1151[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P3;
+	uint8_t dummy1152[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P4;
+	uint8_t dummy1153[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P5;
+	uint8_t dummy1154[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P6;
+	uint8_t dummy1155[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_P7;
+	uint8_t dummy1156[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_IMP;
+	uint8_t dummy1157[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE0;
+	uint8_t dummy1158[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_CTLREG_REG_SPARE1;
+	uint8_t dummy1159[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P0;
+	uint8_t dummy1160[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P1;
+	uint8_t dummy1161[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P2;
+	uint8_t dummy1162[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P3;
+	uint8_t dummy1163[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P4;
+	uint8_t dummy1164[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P5;
+	uint8_t dummy1165[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P6;
+	uint8_t dummy1166[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_P7;
+	uint8_t dummy1167[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_IMP;
+	uint8_t dummy1168[28];
+	uint32_t SWITCH_CORE_PORT_SHAPER_AVB_SHAPING_MODE;
+	uint8_t dummy1169[12];
+	uint32_t SWITCH_CORE_PORT_SHAPER_ENABLE;
+	uint8_t dummy1170[12];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1171[12];
+	uint32_t SWITCH_CORE_PORT_SHAPER_BLOCKING;
+	uint8_t dummy1172[28];
+	uint32_t SWITCH_CORE_IFG_BYTES;
+	uint8_t dummy1173[140];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P0;
+	uint8_t dummy1174[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P1;
+	uint8_t dummy1175[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P2;
+	uint8_t dummy1176[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P3;
+	uint8_t dummy1177[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P4;
+	uint8_t dummy1178[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P5;
+	uint8_t dummy1179[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P6;
+	uint8_t dummy1180[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_P7;
+	uint8_t dummy1181[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_REFRESH_IMP;
+	uint8_t dummy1182[124];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P0;
+	uint8_t dummy1183[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P1;
+	uint8_t dummy1184[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P2;
+	uint8_t dummy1185[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P3;
+	uint8_t dummy1186[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P4;
+	uint8_t dummy1187[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P5;
+	uint8_t dummy1188[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P6;
+	uint8_t dummy1189[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_P7;
+	uint8_t dummy1190[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_THD_SEL_IMP;
+	uint8_t dummy1191[124];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P0;
+	uint8_t dummy1192[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P1;
+	uint8_t dummy1193[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P2;
+	uint8_t dummy1194[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P3;
+	uint8_t dummy1195[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P4;
+	uint8_t dummy1196[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P5;
+	uint8_t dummy1197[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P6;
+	uint8_t dummy1198[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_P7;
+	uint8_t dummy1199[28];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_STS_IMP;
+	uint8_t dummy1200[124];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1201[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1202[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1203[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1204[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1205[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1206[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1207[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1208[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1209[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0;
+	uint8_t dummy1210[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1;
+	uint8_t dummy1211[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1212[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1213[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1214[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1215[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1216[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1217[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1218[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1219[28];
+	uint32_t SWITCH_CORE_QUEUE0_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1220[28];
+	uint32_t SWITCH_CORE_QUEUE0_AVB_SHAPING_MODE;
+	uint8_t dummy1221[12];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_ENABLE;
+	uint8_t dummy1222[12];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1223[12];
+	uint32_t SWITCH_CORE_QUEUE0_SHAPER_BLOCKING;
+	uint8_t dummy1224[172];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P0;
+	uint8_t dummy1225[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P1;
+	uint8_t dummy1226[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P2;
+	uint8_t dummy1227[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P3;
+	uint8_t dummy1228[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P4;
+	uint8_t dummy1229[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P5;
+	uint8_t dummy1230[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P6;
+	uint8_t dummy1231[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_P7;
+	uint8_t dummy1232[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_REFRESH_IMP;
+	uint8_t dummy1233[124];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P0;
+	uint8_t dummy1234[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P1;
+	uint8_t dummy1235[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P2;
+	uint8_t dummy1236[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P3;
+	uint8_t dummy1237[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P4;
+	uint8_t dummy1238[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P5;
+	uint8_t dummy1239[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P6;
+	uint8_t dummy1240[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_P7;
+	uint8_t dummy1241[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_THD_SEL_IMP;
+	uint8_t dummy1242[124];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P0;
+	uint8_t dummy1243[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P1;
+	uint8_t dummy1244[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P2;
+	uint8_t dummy1245[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P3;
+	uint8_t dummy1246[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P4;
+	uint8_t dummy1247[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P5;
+	uint8_t dummy1248[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P6;
+	uint8_t dummy1249[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_P7;
+	uint8_t dummy1250[28];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_STS_IMP;
+	uint8_t dummy1251[124];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1252[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1253[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1254[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1255[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1256[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1257[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1258[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1259[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1260[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0;
+	uint8_t dummy1261[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1;
+	uint8_t dummy1262[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1263[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1264[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1265[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1266[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1267[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1268[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1269[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1270[28];
+	uint32_t SWITCH_CORE_QUEUE1_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1271[28];
+	uint32_t SWITCH_CORE_QUEUE1_AVB_SHAPING_MODE;
+	uint8_t dummy1272[12];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_ENABLE;
+	uint8_t dummy1273[12];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1274[12];
+	uint32_t SWITCH_CORE_QUEUE1_SHAPER_BLOCKING;
+	uint8_t dummy1275[172];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P0;
+	uint8_t dummy1276[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P1;
+	uint8_t dummy1277[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P2;
+	uint8_t dummy1278[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P3;
+	uint8_t dummy1279[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P4;
+	uint8_t dummy1280[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P5;
+	uint8_t dummy1281[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P6;
+	uint8_t dummy1282[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_P7;
+	uint8_t dummy1283[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_REFRESH_IMP;
+	uint8_t dummy1284[124];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P0;
+	uint8_t dummy1285[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P1;
+	uint8_t dummy1286[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P2;
+	uint8_t dummy1287[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P3;
+	uint8_t dummy1288[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P4;
+	uint8_t dummy1289[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P5;
+	uint8_t dummy1290[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P6;
+	uint8_t dummy1291[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_P7;
+	uint8_t dummy1292[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_THD_SEL_IMP;
+	uint8_t dummy1293[124];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P0;
+	uint8_t dummy1294[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P1;
+	uint8_t dummy1295[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P2;
+	uint8_t dummy1296[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P3;
+	uint8_t dummy1297[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P4;
+	uint8_t dummy1298[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P5;
+	uint8_t dummy1299[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P6;
+	uint8_t dummy1300[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_P7;
+	uint8_t dummy1301[28];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_STS_IMP;
+	uint8_t dummy1302[124];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1303[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1304[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1305[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1306[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1307[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1308[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1309[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1310[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1311[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0;
+	uint8_t dummy1312[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1;
+	uint8_t dummy1313[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1314[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1315[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1316[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1317[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1318[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1319[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1320[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1321[28];
+	uint32_t SWITCH_CORE_QUEUE2_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1322[28];
+	uint32_t SWITCH_CORE_QUEUE2_AVB_SHAPING_MODE;
+	uint8_t dummy1323[12];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_ENABLE;
+	uint8_t dummy1324[12];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1325[12];
+	uint32_t SWITCH_CORE_QUEUE2_SHAPER_BLOCKING;
+	uint8_t dummy1326[172];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P0;
+	uint8_t dummy1327[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P1;
+	uint8_t dummy1328[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P2;
+	uint8_t dummy1329[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P3;
+	uint8_t dummy1330[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P4;
+	uint8_t dummy1331[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P5;
+	uint8_t dummy1332[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P6;
+	uint8_t dummy1333[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_P7;
+	uint8_t dummy1334[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_REFRESH_IMP;
+	uint8_t dummy1335[124];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P0;
+	uint8_t dummy1336[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P1;
+	uint8_t dummy1337[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P2;
+	uint8_t dummy1338[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P3;
+	uint8_t dummy1339[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P4;
+	uint8_t dummy1340[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P5;
+	uint8_t dummy1341[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P6;
+	uint8_t dummy1342[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_P7;
+	uint8_t dummy1343[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_THD_SEL_IMP;
+	uint8_t dummy1344[124];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P0;
+	uint8_t dummy1345[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P1;
+	uint8_t dummy1346[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P2;
+	uint8_t dummy1347[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P3;
+	uint8_t dummy1348[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P4;
+	uint8_t dummy1349[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P5;
+	uint8_t dummy1350[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P6;
+	uint8_t dummy1351[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_P7;
+	uint8_t dummy1352[28];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_STS_IMP;
+	uint8_t dummy1353[124];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1354[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1355[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1356[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1357[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1358[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1359[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1360[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1361[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1362[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0;
+	uint8_t dummy1363[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1;
+	uint8_t dummy1364[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1365[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1366[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1367[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1368[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1369[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1370[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1371[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1372[28];
+	uint32_t SWITCH_CORE_QUEUE3_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1373[28];
+	uint32_t SWITCH_CORE_QUEUE3_AVB_SHAPING_MODE;
+	uint8_t dummy1374[12];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_ENABLE;
+	uint8_t dummy1375[12];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1376[12];
+	uint32_t SWITCH_CORE_QUEUE3_SHAPER_BLOCKING;
+	uint8_t dummy1377[172];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P0;
+	uint8_t dummy1378[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P1;
+	uint8_t dummy1379[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P2;
+	uint8_t dummy1380[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P3;
+	uint8_t dummy1381[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P4;
+	uint8_t dummy1382[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P5;
+	uint8_t dummy1383[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P6;
+	uint8_t dummy1384[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_P7;
+	uint8_t dummy1385[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_REFRESH_IMP;
+	uint8_t dummy1386[124];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P0;
+	uint8_t dummy1387[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P1;
+	uint8_t dummy1388[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P2;
+	uint8_t dummy1389[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P3;
+	uint8_t dummy1390[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P4;
+	uint8_t dummy1391[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P5;
+	uint8_t dummy1392[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P6;
+	uint8_t dummy1393[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_P7;
+	uint8_t dummy1394[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_THD_SEL_IMP;
+	uint8_t dummy1395[124];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P0;
+	uint8_t dummy1396[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P1;
+	uint8_t dummy1397[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P2;
+	uint8_t dummy1398[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P3;
+	uint8_t dummy1399[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P4;
+	uint8_t dummy1400[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P5;
+	uint8_t dummy1401[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P6;
+	uint8_t dummy1402[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_P7;
+	uint8_t dummy1403[28];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_STS_IMP;
+	uint8_t dummy1404[124];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1405[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1406[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1407[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1408[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1409[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1410[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1411[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1412[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1413[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0;
+	uint8_t dummy1414[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1;
+	uint8_t dummy1415[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1416[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1417[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1418[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1419[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1420[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1421[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1422[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1423[28];
+	uint32_t SWITCH_CORE_QUEUE4_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1424[28];
+	uint32_t SWITCH_CORE_QUEUE4_AVB_SHAPING_MODE;
+	uint8_t dummy1425[12];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_ENABLE;
+	uint8_t dummy1426[12];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1427[12];
+	uint32_t SWITCH_CORE_QUEUE4_SHAPER_BLOCKING;
+	uint8_t dummy1428[172];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P0;
+	uint8_t dummy1429[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P1;
+	uint8_t dummy1430[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P2;
+	uint8_t dummy1431[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P3;
+	uint8_t dummy1432[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P4;
+	uint8_t dummy1433[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P5;
+	uint8_t dummy1434[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P6;
+	uint8_t dummy1435[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_P7;
+	uint8_t dummy1436[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_REFRESH_IMP;
+	uint8_t dummy1437[124];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P0;
+	uint8_t dummy1438[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P1;
+	uint8_t dummy1439[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P2;
+	uint8_t dummy1440[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P3;
+	uint8_t dummy1441[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P4;
+	uint8_t dummy1442[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P5;
+	uint8_t dummy1443[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P6;
+	uint8_t dummy1444[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_P7;
+	uint8_t dummy1445[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_THD_SEL_IMP;
+	uint8_t dummy1446[124];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P0;
+	uint8_t dummy1447[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P1;
+	uint8_t dummy1448[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P2;
+	uint8_t dummy1449[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P3;
+	uint8_t dummy1450[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P4;
+	uint8_t dummy1451[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P5;
+	uint8_t dummy1452[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P6;
+	uint8_t dummy1453[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_P7;
+	uint8_t dummy1454[28];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_STS_IMP;
+	uint8_t dummy1455[124];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1456[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1457[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1458[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1459[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1460[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1461[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1462[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1463[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1464[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0;
+	uint8_t dummy1465[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1;
+	uint8_t dummy1466[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1467[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1468[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1469[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1470[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1471[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1472[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1473[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1474[28];
+	uint32_t SWITCH_CORE_QUEUE5_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1475[28];
+	uint32_t SWITCH_CORE_QUEUE5_AVB_SHAPING_MODE;
+	uint8_t dummy1476[12];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_ENABLE;
+	uint8_t dummy1477[12];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1478[12];
+	uint32_t SWITCH_CORE_QUEUE5_SHAPER_BLOCKING;
+	uint8_t dummy1479[172];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P0;
+	uint8_t dummy1480[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P1;
+	uint8_t dummy1481[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P2;
+	uint8_t dummy1482[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P3;
+	uint8_t dummy1483[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P4;
+	uint8_t dummy1484[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P5;
+	uint8_t dummy1485[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P6;
+	uint8_t dummy1486[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_P7;
+	uint8_t dummy1487[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_REFRESH_IMP;
+	uint8_t dummy1488[124];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P0;
+	uint8_t dummy1489[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P1;
+	uint8_t dummy1490[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P2;
+	uint8_t dummy1491[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P3;
+	uint8_t dummy1492[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P4;
+	uint8_t dummy1493[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P5;
+	uint8_t dummy1494[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P6;
+	uint8_t dummy1495[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_P7;
+	uint8_t dummy1496[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_THD_SEL_IMP;
+	uint8_t dummy1497[124];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P0;
+	uint8_t dummy1498[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P1;
+	uint8_t dummy1499[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P2;
+	uint8_t dummy1500[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P3;
+	uint8_t dummy1501[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P4;
+	uint8_t dummy1502[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P5;
+	uint8_t dummy1503[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P6;
+	uint8_t dummy1504[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_P7;
+	uint8_t dummy1505[28];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_STS_IMP;
+	uint8_t dummy1506[124];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1507[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1508[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1509[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1510[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1511[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1512[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1513[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1514[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1515[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0;
+	uint8_t dummy1516[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1;
+	uint8_t dummy1517[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1518[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1519[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1520[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1521[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1522[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1523[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1524[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1525[28];
+	uint32_t SWITCH_CORE_QUEUE6_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1526[28];
+	uint32_t SWITCH_CORE_QUEUE6_AVB_SHAPING_MODE;
+	uint8_t dummy1527[12];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_ENABLE;
+	uint8_t dummy1528[12];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1529[12];
+	uint32_t SWITCH_CORE_QUEUE6_SHAPER_BLOCKING;
+	uint8_t dummy1530[172];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P0;
+	uint8_t dummy1531[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P1;
+	uint8_t dummy1532[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P2;
+	uint8_t dummy1533[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P3;
+	uint8_t dummy1534[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P4;
+	uint8_t dummy1535[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P5;
+	uint8_t dummy1536[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P6;
+	uint8_t dummy1537[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_P7;
+	uint8_t dummy1538[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_REFRESH_IMP;
+	uint8_t dummy1539[124];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P0;
+	uint8_t dummy1540[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P1;
+	uint8_t dummy1541[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P2;
+	uint8_t dummy1542[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P3;
+	uint8_t dummy1543[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P4;
+	uint8_t dummy1544[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P5;
+	uint8_t dummy1545[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P6;
+	uint8_t dummy1546[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_P7;
+	uint8_t dummy1547[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_THD_SEL_IMP;
+	uint8_t dummy1548[124];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P0;
+	uint8_t dummy1549[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P1;
+	uint8_t dummy1550[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P2;
+	uint8_t dummy1551[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P3;
+	uint8_t dummy1552[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P4;
+	uint8_t dummy1553[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P5;
+	uint8_t dummy1554[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P6;
+	uint8_t dummy1555[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_P7;
+	uint8_t dummy1556[28];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_STS_IMP;
+	uint8_t dummy1557[124];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P0;
+	uint8_t dummy1558[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P1;
+	uint8_t dummy1559[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P2;
+	uint8_t dummy1560[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P3;
+	uint8_t dummy1561[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P4;
+	uint8_t dummy1562[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P5;
+	uint8_t dummy1563[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P6;
+	uint8_t dummy1564[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_P7;
+	uint8_t dummy1565[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_REFRESH_IMP;
+	uint8_t dummy1566[60];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0;
+	uint8_t dummy1567[28];
+	uint32_t SWITCH_CORE_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1;
+	uint8_t dummy1568[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P0;
+	uint8_t dummy1569[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P1;
+	uint8_t dummy1570[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P2;
+	uint8_t dummy1571[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P3;
+	uint8_t dummy1572[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P4;
+	uint8_t dummy1573[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P5;
+	uint8_t dummy1574[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P6;
+	uint8_t dummy1575[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_P7;
+	uint8_t dummy1576[28];
+	uint32_t SWITCH_CORE_QUEUE7_MAX_PACKET_THD_SEL_IMP;
+	uint8_t dummy1577[28];
+	uint32_t SWITCH_CORE_QUEUE7_AVB_SHAPING_MODE;
+	uint8_t dummy1578[12];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_ENABLE;
+	uint8_t dummy1579[12];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_BUCKET_COUNT_SELECT;
+	uint8_t dummy1580[12];
+	uint32_t SWITCH_CORE_QUEUE7_SHAPER_BLOCKING;
+	uint8_t dummy1581[65708];
+	uint32_t SWITCH_CORE_MIB_SNAPSHOT_CTL;
+	uint8_t dummy1582[2044];
+	uint32_t SWITCH_CORE_S_TxOctets;
+	uint8_t dummy1583[60];
+	uint32_t SWITCH_CORE_S_TxDropPkts;
+	uint8_t dummy1584[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ0;
+	uint8_t dummy1585[28];
+	uint32_t SWITCH_CORE_S_TxBroadcastPkts;
+	uint8_t dummy1586[28];
+	uint32_t SWITCH_CORE_S_TxMulticastPkts;
+	uint8_t dummy1587[28];
+	uint32_t SWITCH_CORE_S_TxUnicastPkts;
+	uint8_t dummy1588[28];
+	uint32_t SWITCH_CORE_S_TxCollisions;
+	uint8_t dummy1589[28];
+	uint32_t SWITCH_CORE_S_TxSingleCollision;
+	uint8_t dummy1590[28];
+	uint32_t SWITCH_CORE_S_TxMultipleCollision;
+	uint8_t dummy1591[28];
+	uint32_t SWITCH_CORE_S_TxDeferredTransmit;
+	uint8_t dummy1592[28];
+	uint32_t SWITCH_CORE_S_TxLateCollision;
+	uint8_t dummy1593[28];
+	uint32_t SWITCH_CORE_S_TxExcessiveCollision;
+	uint8_t dummy1594[28];
+	uint32_t SWITCH_CORE_S_TxFrameInDisc;
+	uint8_t dummy1595[28];
+	uint32_t SWITCH_CORE_S_TxPausePkts;
+	uint8_t dummy1596[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ1;
+	uint8_t dummy1597[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ2;
+	uint8_t dummy1598[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ3;
+	uint8_t dummy1599[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ4;
+	uint8_t dummy1600[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ5;
+	uint8_t dummy1601[28];
+	uint32_t SWITCH_CORE_S_RxOctets;
+	uint8_t dummy1602[60];
+	uint32_t SWITCH_CORE_S_RxUndersizePkts;
+	uint8_t dummy1603[28];
+	uint32_t SWITCH_CORE_S_RxPausePkts;
+	uint8_t dummy1604[28];
+	uint32_t SWITCH_CORE_S_RxPkts64Octets;
+	uint8_t dummy1605[28];
+	uint32_t SWITCH_CORE_S_RxPkts65to127Octets;
+	uint8_t dummy1606[28];
+	uint32_t SWITCH_CORE_S_RxPkts128to255Octets;
+	uint8_t dummy1607[28];
+	uint32_t SWITCH_CORE_S_RxPkts256to511Octets;
+	uint8_t dummy1608[28];
+	uint32_t SWITCH_CORE_S_RxPkts512to1023Octets;
+	uint8_t dummy1609[28];
+	uint32_t SWITCH_CORE_S_RxPkts1024toMaxPktOctets;
+	uint8_t dummy1610[28];
+	uint32_t SWITCH_CORE_S_RxOversizePkts;
+	uint8_t dummy1611[28];
+	uint32_t SWITCH_CORE_S_RxJabbers;
+	uint8_t dummy1612[28];
+	uint32_t SWITCH_CORE_S_RxAlignmentErrors;
+	uint8_t dummy1613[28];
+	uint32_t SWITCH_CORE_S_RxFCSErrors;
+	uint8_t dummy1614[28];
+	uint32_t SWITCH_CORE_S_RxGoodOctets;
+	uint8_t dummy1615[60];
+	uint32_t SWITCH_CORE_S_RxDropPkts;
+	uint8_t dummy1616[28];
+	uint32_t SWITCH_CORE_S_RxUnicastPkts;
+	uint8_t dummy1617[28];
+	uint32_t SWITCH_CORE_S_RxMulticastPkts;
+	uint8_t dummy1618[28];
+	uint32_t SWITCH_CORE_S_RxBroadcastPkts;
+	uint8_t dummy1619[28];
+	uint32_t SWITCH_CORE_S_RxSAChanges;
+	uint8_t dummy1620[28];
+	uint32_t SWITCH_CORE_S_RxFragments;
+	uint8_t dummy1621[28];
+	uint32_t SWITCH_CORE_S_RxJumboPkt;
+	uint8_t dummy1622[28];
+	uint32_t SWITCH_CORE_S_RxSymblErr;
+	uint8_t dummy1623[28];
+	uint32_t SWITCH_CORE_S_InRangeErrCount;
+	uint8_t dummy1624[28];
+	uint32_t SWITCH_CORE_S_OutRangeErrCount;
+	uint8_t dummy1625[28];
+	uint32_t SWITCH_CORE_S_EEE_LPI_EVENT;
+	uint8_t dummy1626[28];
+	uint32_t SWITCH_CORE_S_EEE_LPI_DURATION;
+	uint8_t dummy1627[28];
+	uint32_t SWITCH_CORE_S_RxDiscard;
+	uint8_t dummy1628[60];
+	uint32_t SWITCH_CORE_S_TxQPKTQ6;
+	uint8_t dummy1629[28];
+	uint32_t SWITCH_CORE_S_TxQPKTQ7;
+	uint8_t dummy1630[28];
+	uint32_t SWITCH_CORE_S_TxPkts64Octets;
+	uint8_t dummy1631[28];
+	uint32_t SWITCH_CORE_S_TxPkts65to127Octets;
+	uint8_t dummy1632[28];
+	uint32_t SWITCH_CORE_S_TxPkts128to255Octets;
+	uint8_t dummy1633[28];
+	uint32_t SWITCH_CORE_S_TxPkts256to511Octets;
+	uint8_t dummy1634[28];
+	uint32_t SWITCH_CORE_S_TxPkts512to1023Octets;
+	uint8_t dummy1635[28];
+	uint32_t SWITCH_CORE_S_TxPkts1024toMaxPktOctets;
+	uint8_t dummy1636[220];
+	uint32_t SWITCH_CORE_LPDET_CFG;
+	uint8_t dummy1637[12];
+	uint64_t SWITCH_CORE_DF_TIMER;
+	uint32_t SWITCH_CORE_LED_PORTMAP;
+	uint8_t dummy1638[12];
+	uint32_t SWITCH_CORE_MODULE_ID0;
+	uint8_t dummy1639[44];
+	uint32_t SWITCH_CORE_MODULE_ID1;
+	uint8_t dummy1640[44];
+	uint32_t SWITCH_CORE_LPDET_SA;
+	uint8_t dummy1641[116];
+	uint32_t SWITCH_CORE_LPDET_REG_SPARE0;
+	uint8_t dummy1642[28];
+	uint32_t SWITCH_CORE_LPDET_REG_SPARE1;
+	uint8_t dummy1643[1756];
+	uint64_t SWITCH_CORE_BPM_CTRL;
+	uint64_t SWITCH_CORE_BPM_PSM_OVR_CTRL;
+	uint32_t SWITCH_CORE_BPM_PSM_TIME_CFG;
+	uint8_t dummy1644[12];
+	uint32_t SWITCH_CORE_BPM_PSM_THD_CFG;
+	uint8_t dummy1645[28];
+	uint32_t SWITCH_CORE_ROW_VMASK_OVR_CTRL;
+	uint8_t dummy1646[28];
+	uint32_t SWITCH_CORE_BPM_STS;
+	uint8_t dummy1647[28];
+	uint32_t SWITCH_CORE_BPM_PDA_OVR_CTRL;
+	uint8_t dummy1648[12];
+	uint32_t SWITCH_CORE_PDA_TIMEOUT_CFG;
+	uint8_t dummy1649[12];
+	uint32_t SWITCH_CORE_PDA_SETUP_TIME_CFG;
+	uint8_t dummy1650[12];
+	uint32_t SWITCH_CORE_PDA_HOLD_TIME_CFG;
+	uint8_t dummy1651[12];
+	uint32_t SWITCH_CORE_PBB_VBUFCNT_P0;
+	uint8_t dummy1652[12];
+	uint32_t SWITCH_CORE_PBB_VBUFCNT_P1;
+	uint8_t dummy1653[12];
+	uint32_t SWITCH_CORE_PBB_VBUFCNT_P2;
+	uint8_t dummy1654[12];
+	uint32_t SWITCH_CORE_RCY_TIME_CFG;
+	uint8_t dummy1655[12];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON_CTRL;
+	uint8_t dummy1656[60];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON0;
+	uint8_t dummy1657[60];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON1;
+	uint8_t dummy1658[60];
+	uint32_t SWITCH_CORE_PBB_PWRDWN_MON2;
+	uint8_t dummy1659[316];
+	uint32_t SWITCH_CORE_BPM_REG_SPARE0;
+	uint8_t dummy1660[28];
+	uint32_t SWITCH_CORE_BPM_REG_SPARE1;
+	uint8_t dummy1661[60636];
+	uint32_t SWITCH_CORE_TRREG_CTRL0;
+	uint8_t dummy1662[28];
+	uint32_t SWITCH_CORE_TRREG_CTRL1;
+	uint8_t dummy1663[28];
+	uint32_t SWITCH_CORE_TRREG_CTRL2;
+	uint8_t dummy1664[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P0;
+	uint8_t dummy1665[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P1;
+	uint8_t dummy1666[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P2;
+	uint8_t dummy1667[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P3;
+	uint8_t dummy1668[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P4;
+	uint8_t dummy1669[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P5;
+	uint8_t dummy1670[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P6;
+	uint8_t dummy1671[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_P7;
+	uint8_t dummy1672[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2PCP_MAP_IMP;
+	uint8_t dummy1673[124];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P0;
+	uint8_t dummy1674[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P1;
+	uint8_t dummy1675[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P2;
+	uint8_t dummy1676[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P3;
+	uint8_t dummy1677[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P4;
+	uint8_t dummy1678[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P5;
+	uint8_t dummy1679[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P6;
+	uint8_t dummy1680[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_P7;
+	uint8_t dummy1681[60];
+	uint32_t SWITCH_CORE_EGRESS_PKT_TC2CPCP_MAP_IMP;
+	uint8_t dummy1682[124];
+	uint32_t SWITCH_CORE_TRREG_REG_SPARE0;
+	uint8_t dummy1683[28];
+	uint32_t SWITCH_CORE_TRREG_REG_SPARE1;
+	uint8_t dummy1684[604];
+	uint32_t SWITCH_CORE_EEE_EN_CTRL;
+	uint8_t dummy1685[12];
+	uint32_t SWITCH_CORE_EEE_LPI_ASSERT;
+	uint8_t dummy1686[12];
+	uint32_t SWITCH_CORE_EEE_LPI_INDICATE;
+	uint8_t dummy1687[12];
+	uint32_t SWITCH_CORE_EEE_RX_IDLE_SYMBOL;
+	uint8_t dummy1688[12];
+	uint32_t SWITCH_CORE_EEE_LPI_SYMBOL_TX_DISABLE;
+	uint8_t dummy1689[28];
+	uint32_t SWITCH_CORE_EEE_PIPELINE_TIMER;
+	uint8_t dummy1690[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P0;
+	uint8_t dummy1691[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P1;
+	uint8_t dummy1692[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P2;
+	uint8_t dummy1693[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P3;
+	uint8_t dummy1694[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P4;
+	uint8_t dummy1695[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P5;
+	uint8_t dummy1696[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P6;
+	uint8_t dummy1697[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_P7;
+	uint8_t dummy1698[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_G_IMP;
+	uint8_t dummy1699[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P0;
+	uint8_t dummy1700[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P1;
+	uint8_t dummy1701[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P2;
+	uint8_t dummy1702[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P3;
+	uint8_t dummy1703[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P4;
+	uint8_t dummy1704[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P5;
+	uint8_t dummy1705[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P6;
+	uint8_t dummy1706[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_P7;
+	uint8_t dummy1707[28];
+	uint32_t SWITCH_CORE_EEE_SLEEP_TIMER_H_IMP;
+	uint8_t dummy1708[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P0;
+	uint8_t dummy1709[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P1;
+	uint8_t dummy1710[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P2;
+	uint8_t dummy1711[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P3;
+	uint8_t dummy1712[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P4;
+	uint8_t dummy1713[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P5;
+	uint8_t dummy1714[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P6;
+	uint8_t dummy1715[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_P7;
+	uint8_t dummy1716[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_G_IMP;
+	uint8_t dummy1717[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P0;
+	uint8_t dummy1718[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P1;
+	uint8_t dummy1719[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P2;
+	uint8_t dummy1720[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P3;
+	uint8_t dummy1721[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P4;
+	uint8_t dummy1722[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P5;
+	uint8_t dummy1723[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P6;
+	uint8_t dummy1724[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_P7;
+	uint8_t dummy1725[28];
+	uint32_t SWITCH_CORE_EEE_MIN_LP_TIMER_H_IMP;
+	uint8_t dummy1726[28];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P0;
+	uint8_t dummy1727[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P1;
+	uint8_t dummy1728[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P2;
+	uint8_t dummy1729[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P3;
+	uint8_t dummy1730[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P4;
+	uint8_t dummy1731[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P5;
+	uint8_t dummy1732[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P6;
+	uint8_t dummy1733[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P7;
+	uint8_t dummy1734[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_G_P8;
+	uint8_t dummy1735[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P0;
+	uint8_t dummy1736[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P1;
+	uint8_t dummy1737[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P2;
+	uint8_t dummy1738[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P3;
+	uint8_t dummy1739[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P4;
+	uint8_t dummy1740[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P5;
+	uint8_t dummy1741[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P6;
+	uint8_t dummy1742[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_P7;
+	uint8_t dummy1743[12];
+	uint32_t SWITCH_CORE_EEE_WAKE_TIMER_H_IMP;
+	uint8_t dummy1744[12];
+	uint32_t SWITCH_CORE_EEE_GLB_CONG_TH;
+	uint8_t dummy1745[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q0;
+	uint8_t dummy1746[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q1;
+	uint8_t dummy1747[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q2;
+	uint8_t dummy1748[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q3;
+	uint8_t dummy1749[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q4;
+	uint8_t dummy1750[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q5;
+	uint8_t dummy1751[20];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q6;
+	uint8_t dummy1752[12];
+	uint32_t SWITCH_CORE_EEE_TX_CONG_TH_Q7;
+	uint8_t dummy1753[44];
+	uint32_t SWITCH_CORE_EEE_CTL_REG_SPARE0;
+	uint8_t dummy1754[36];
+	uint32_t SWITCH_CORE_EEE_CTL_REG_SPARE1;
+	uint8_t dummy1755[52];
+	uint64_t SWITCH_CORE_EEE_DEBUG;
+	uint32_t SWITCH_CORE_EEE_LINK_DLY_TIMER;
+	uint8_t dummy1756[28];
+	uint32_t SWITCH_CORE_EEE_STATE;
+	uint8_t dummy1757[156];
+	uint32_t SWITCH_CORE_PORT_ENABLE;
+	uint8_t dummy1758[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P0;
+	uint8_t dummy1759[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P1;
+	uint8_t dummy1760[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P2;
+	uint8_t dummy1761[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P3;
+	uint8_t dummy1762[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P4;
+	uint8_t dummy1763[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P5;
+	uint8_t dummy1764[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_P7;
+	uint8_t dummy1765[12];
+	uint32_t SWITCH_CORE_TX_MODE_PORT_IMP;
+	uint8_t dummy1766[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P0;
+	uint8_t dummy1767[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P1;
+	uint8_t dummy1768[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P2;
+	uint8_t dummy1769[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P3;
+	uint8_t dummy1770[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P4;
+	uint8_t dummy1771[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P5;
+	uint8_t dummy1772[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_P7;
+	uint8_t dummy1773[12];
+	uint32_t SWITCH_CORE_RX_MODE_PORT_IMP;
+	uint8_t dummy1774[12];
+	uint32_t SWITCH_CORE_TX_TS_CAP;
+	uint8_t dummy1775[12];
+	uint32_t SWITCH_CORE_RX_TS_CAP;
+	uint8_t dummy1776[12];
+	uint32_t SWITCH_CORE_RX_TX_OPTION;
+	uint8_t dummy1777[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_LINK_DELAY_LSB;
+	uint8_t dummy1778[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_LINK_DELAY_MSB;
+	uint8_t dummy1779[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_LINK_DELAY_LSB;
+	uint8_t dummy1780[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_LINK_DELAY_MSB;
+	uint8_t dummy1781[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_LINK_DELAY_LSB;
+	uint8_t dummy1782[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_LINK_DELAY_MSB;
+	uint8_t dummy1783[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_LINK_DELAY_LSB;
+	uint8_t dummy1784[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_LINK_DELAY_MSB;
+	uint8_t dummy1785[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_LINK_DELAY_LSB;
+	uint8_t dummy1786[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_LINK_DELAY_MSB;
+	uint8_t dummy1787[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_LINK_DELAY_LSB;
+	uint8_t dummy1788[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_LINK_DELAY_MSB;
+	uint8_t dummy1789[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_LINK_DELAY_LSB;
+	uint8_t dummy1790[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_LINK_DELAY_MSB;
+	uint8_t dummy1791[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_LINK_DELAY_LSB;
+	uint8_t dummy1792[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_LINK_DELAY_MSB;
+	uint8_t dummy1793[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_TS_OFFSET_LSB;
+	uint8_t dummy1794[12];
+	uint32_t SWITCH_CORE_RX_PORT_0_TS_OFFSET_MSB;
+	uint8_t dummy1795[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_TS_OFFSET_LSB;
+	uint8_t dummy1796[12];
+	uint32_t SWITCH_CORE_RX_PORT_1_TS_OFFSET_MSB;
+	uint8_t dummy1797[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_TS_OFFSET_LSB;
+	uint8_t dummy1798[12];
+	uint32_t SWITCH_CORE_RX_PORT_2_TS_OFFSET_MSB;
+	uint8_t dummy1799[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_TS_OFFSET_LSB;
+	uint8_t dummy1800[12];
+	uint32_t SWITCH_CORE_RX_PORT_3_TS_OFFSET_MSB;
+	uint8_t dummy1801[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_TS_OFFSET_LSB;
+	uint8_t dummy1802[12];
+	uint32_t SWITCH_CORE_RX_PORT_4_TS_OFFSET_MSB;
+	uint8_t dummy1803[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_TS_OFFSET_LSB;
+	uint8_t dummy1804[12];
+	uint32_t SWITCH_CORE_RX_PORT_5_TS_OFFSET_MSB;
+	uint8_t dummy1805[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_TS_OFFSET_LSB;
+	uint8_t dummy1806[12];
+	uint32_t SWITCH_CORE_RX_PORT_7_TS_OFFSET_MSB;
+	uint8_t dummy1807[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_TS_OFFSET_LSB;
+	uint8_t dummy1808[12];
+	uint32_t SWITCH_CORE_RX_PORT_8_TS_OFFSET_MSB;
+	uint8_t dummy1809[12];
+	uint32_t SWITCH_CORE_TX_PORT_0_TS_OFFSET_LSB;
+	uint8_t dummy1810[12];
+	uint32_t SWITCH_CORE_TX_PORT_0_TS_OFFSET_MSB;
+	uint8_t dummy1811[12];
+	uint32_t SWITCH_CORE_TX_PORT_1_TS_OFFSET_LSB;
+	uint8_t dummy1812[12];
+	uint32_t SWITCH_CORE_TX_PORT_1_TS_OFFSET_MSB;
+	uint8_t dummy1813[12];
+	uint32_t SWITCH_CORE_TX_PORT_2_TS_OFFSET_LSB;
+	uint8_t dummy1814[12];
+	uint32_t SWITCH_CORE_TX_PORT_2_TS_OFFSET_MSB;
+	uint8_t dummy1815[12];
+	uint32_t SWITCH_CORE_TX_PORT_3_TS_OFFSET_LSB;
+	uint8_t dummy1816[12];
+	uint32_t SWITCH_CORE_TX_PORT_3_TS_OFFSET_MSB;
+	uint8_t dummy1817[12];
+	uint32_t SWITCH_CORE_TX_PORT_4_TS_OFFSET_LSB;
+	uint8_t dummy1818[12];
+	uint32_t SWITCH_CORE_TX_PORT_4_TS_OFFSET_MSB;
+	uint8_t dummy1819[12];
+	uint32_t SWITCH_CORE_TX_PORT_5_TS_OFFSET_LSB;
+	uint8_t dummy1820[12];
+	uint32_t SWITCH_CORE_TX_PORT_5_TS_OFFSET_MSB;
+	uint8_t dummy1821[12];
+	uint32_t SWITCH_CORE_TX_PORT_7_TS_OFFSET_LSB;
+	uint8_t dummy1822[12];
+	uint32_t SWITCH_CORE_TX_PORT_7_TS_OFFSET_MSB;
+	uint8_t dummy1823[12];
+	uint32_t SWITCH_CORE_TX_PORT_8_TS_OFFSET_LSB;
+	uint8_t dummy1824[12];
+	uint32_t SWITCH_CORE_TX_PORT_8_TS_OFFSET_MSB;
+	uint8_t dummy1825[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P0;
+	uint8_t dummy1826[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P1;
+	uint8_t dummy1827[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P2;
+	uint8_t dummy1828[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P3;
+	uint8_t dummy1829[12];
+	uint32_t SWITCH_CORE_TIME_CODE_N_P4;
+	uint8_t dummy1830[12];
+	uint32_t SWITCH_CORE_DPLL_DB_LSB;
+	uint8_t dummy1831[12];
+	uint32_t SWITCH_CORE_DPLL_DB_MSB;
+	uint8_t dummy1832[12];
+	uint32_t SWITCH_CORE_DPLL_DB_SEL;
+	uint8_t dummy1833[12];
+	uint32_t SWITCH_CORE_SHD_CTL;
+	uint8_t dummy1834[12];
+	uint32_t SWITCH_CORE_SHD_LD;
+	uint8_t dummy1835[12];
+	uint32_t SWITCH_CORE_INT_MASK;
+	uint8_t dummy1836[12];
+	uint32_t SWITCH_CORE_INT_STAT;
+	uint8_t dummy1837[12];
+	uint32_t SWITCH_CORE_TX_CTL;
+	uint8_t dummy1838[12];
+	uint32_t SWITCH_CORE_RX_CTL;
+	uint8_t dummy1839[12];
+	uint32_t SWITCH_CORE_RX_TX_CTL;
+	uint8_t dummy1840[12];
+	uint32_t SWITCH_CORE_VLAN_ITPID;
+	uint8_t dummy1841[12];
+	uint32_t SWITCH_CORE_VLAN_OTPID;
+	uint8_t dummy1842[12];
+	uint32_t SWITCH_CORE_OTHER_OTPID;
+	uint8_t dummy1843[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_1;
+	uint8_t dummy1844[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_2_N_P0;
+	uint8_t dummy1845[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_2_N_P1;
+	uint8_t dummy1846[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_2_N_P2;
+	uint8_t dummy1847[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_3_N_P0;
+	uint8_t dummy1848[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_3_N_P1;
+	uint8_t dummy1849[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_4;
+	uint8_t dummy1850[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_5;
+	uint8_t dummy1851[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_6;
+	uint8_t dummy1852[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P0;
+	uint8_t dummy1853[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P1;
+	uint8_t dummy1854[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P2;
+	uint8_t dummy1855[12];
+	uint32_t SWITCH_CORE_NSE_DPLL_7_N_P3;
+	uint8_t dummy1856[12];
+	uint32_t SWITCH_CORE_NSE_NCO_1_N_P0;
+	uint8_t dummy1857[12];
+	uint32_t SWITCH_CORE_NSE_NCO_1_N_P1;
+	uint8_t dummy1858[12];
+	uint32_t SWITCH_CORE_NSE_NCO_2_N_P0;
+	uint8_t dummy1859[12];
+	uint32_t SWITCH_CORE_NSE_NCO_2_N_P1;
+	uint8_t dummy1860[12];
+	uint32_t SWITCH_CORE_NSE_NCO_2_N_P2;
+	uint8_t dummy1861[12];
+	uint32_t SWITCH_CORE_NSE_NCO_3_0;
+	uint8_t dummy1862[12];
+	uint32_t SWITCH_CORE_NSE_NCO_3_1;
+	uint8_t dummy1863[12];
+	uint32_t SWITCH_CORE_NSE_NCO_3_2;
+	uint8_t dummy1864[12];
+	uint32_t SWITCH_CORE_NSE_NCO_4;
+	uint8_t dummy1865[12];
+	uint32_t SWITCH_CORE_NSE_NCO_5_0;
+	uint8_t dummy1866[12];
+	uint32_t SWITCH_CORE_NSE_NCO_5_1;
+	uint8_t dummy1867[12];
+	uint32_t SWITCH_CORE_NSE_NCO_5_2;
+	uint8_t dummy1868[12];
+	uint32_t SWITCH_CORE_NSE_NCO_6;
+	uint8_t dummy1869[12];
+	uint32_t SWITCH_CORE_NSE_NCO_7_0;
+	uint8_t dummy1870[12];
+	uint32_t SWITCH_CORE_NSE_NCO_7_1;
+	uint8_t dummy1871[12];
+	uint32_t SWITCH_CORE_TX_COUNTER;
+	uint8_t dummy1872[12];
+	uint32_t SWITCH_CORE_RX_COUNTER;
+	uint8_t dummy1873[12];
+	uint32_t SWITCH_CORE_RX_TX_1588_COUNTER;
+	uint8_t dummy1874[12];
+	uint32_t SWITCH_CORE_TS_READ_START_END;
+	uint8_t dummy1875[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_0;
+	uint8_t dummy1876[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_1;
+	uint8_t dummy1877[140];
+	uint32_t SWITCH_CORE_HEARTBEAT_2;
+	uint8_t dummy1878[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_N_P0;
+	uint8_t dummy1879[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_N_P1;
+	uint8_t dummy1880[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_N_P2;
+	uint8_t dummy1881[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_N_P0;
+	uint8_t dummy1882[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_N_P1;
+	uint8_t dummy1883[12];
+	uint32_t SWITCH_CORE_CNTR_DBG;
+	uint8_t dummy1884[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE1;
+	uint8_t dummy1885[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE2;
+	uint8_t dummy1886[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE3;
+	uint8_t dummy1887[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE4;
+	uint8_t dummy1888[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE5;
+	uint8_t dummy1889[12];
+	uint32_t SWITCH_CORE_MPLS_SPARE6;
+	uint8_t dummy1890[12];
+	uint32_t SWITCH_CORE_MPLS_TX_CNTL;
+	uint8_t dummy1891[12];
+	uint32_t SWITCH_CORE_MPLS_RX_CNTL;
+	uint8_t dummy1892[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_MASK_LSB;
+	uint8_t dummy1893[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_MASK_MSB;
+	uint8_t dummy1894[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_VALUE_LSB;
+	uint8_t dummy1895[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL1_VALUE_MSB;
+	uint8_t dummy1896[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_MASK_LSB;
+	uint8_t dummy1897[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_MASK_MSB;
+	uint8_t dummy1898[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_VALUE_LSB;
+	uint8_t dummy1899[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL2_VALUE_MSB;
+	uint8_t dummy1900[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_MASK_LSB;
+	uint8_t dummy1901[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_MASK_MSB;
+	uint8_t dummy1902[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_VALUE_LSB;
+	uint8_t dummy1903[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL3_VALUE_MSB;
+	uint8_t dummy1904[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_MASK_LSB;
+	uint8_t dummy1905[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_MASK_MSB;
+	uint8_t dummy1906[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_VALUE_LSB;
+	uint8_t dummy1907[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL4_VALUE_MSB;
+	uint8_t dummy1908[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_MASK_LSB;
+	uint8_t dummy1909[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_MASK_MSB;
+	uint8_t dummy1910[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_VALUE_LSB;
+	uint8_t dummy1911[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL5_VALUE_MSB;
+	uint8_t dummy1912[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_MASK_LSB;
+	uint8_t dummy1913[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_MASK_MSB;
+	uint8_t dummy1914[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_VALUE_LSB;
+	uint8_t dummy1915[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL6_VALUE_MSB;
+	uint8_t dummy1916[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_MASK_LSB;
+	uint8_t dummy1917[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_MASK_MSB;
+	uint8_t dummy1918[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_VALUE_LSB;
+	uint8_t dummy1919[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL7_VALUE_MSB;
+	uint8_t dummy1920[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_MASK_LSB;
+	uint8_t dummy1921[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_MASK_MSB;
+	uint8_t dummy1922[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_VALUE_LSB;
+	uint8_t dummy1923[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL8_VALUE_MSB;
+	uint8_t dummy1924[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_MASK_LSB;
+	uint8_t dummy1925[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_MASK_MSB;
+	uint8_t dummy1926[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_VALUE_LSB;
+	uint8_t dummy1927[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL9_VALUE_MSB;
+	uint8_t dummy1928[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_MASK_LSB;
+	uint8_t dummy1929[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_MASK_MSB;
+	uint8_t dummy1930[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_VALUE_LSB;
+	uint8_t dummy1931[12];
+	uint32_t SWITCH_CORE_MPLS_LABEL10_VALUE_MSB;
+	uint8_t dummy1932[12];
+	uint32_t SWITCH_CORE_RX_TX_1588_COUNTER1;
+	uint8_t dummy1933[12];
+	uint32_t SWITCH_CORE_RX_CF_SPEC;
+	uint8_t dummy1934[12];
+	uint32_t SWITCH_CORE_TX_CF_SPEC;
+	uint8_t dummy1935[12];
+	uint32_t SWITCH_CORE_MPLS_PACKET_ENABLE;
+	uint8_t dummy1936[12];
+	uint32_t SWITCH_CORE_TIMECODE_SEL;
+	uint8_t dummy1937[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_3;
+	uint8_t dummy1938[12];
+	uint32_t SWITCH_CORE_TIME_STAMP;
+	uint8_t dummy1939[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_TX_CONTROL;
+	uint8_t dummy1940[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_RX_CONTROL;
+	uint8_t dummy1941[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE1;
+	uint8_t dummy1942[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE2;
+	uint8_t dummy1943[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE3;
+	uint8_t dummy1944[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE4;
+	uint8_t dummy1945[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE5;
+	uint8_t dummy1946[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE6;
+	uint8_t dummy1947[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE7;
+	uint8_t dummy1948[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE8;
+	uint8_t dummy1949[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE9;
+	uint8_t dummy1950[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE10;
+	uint8_t dummy1951[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE11;
+	uint8_t dummy1952[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE12;
+	uint8_t dummy1953[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_ETYPE13;
+	uint8_t dummy1954[12];
+	uint32_t SWITCH_CORE_DELAY_MEASUREMENT_IETF_OFFSET;
+	uint8_t dummy1955[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P0;
+	uint8_t dummy1956[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P1;
+	uint8_t dummy1957[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P2;
+	uint8_t dummy1958[12];
+	uint32_t SWITCH_CORE_NTP_TIME_STAMP_N_P3;
+	uint8_t dummy1959[12];
+	uint32_t SWITCH_CORE_NTP_NCO_FREQ_0;
+	uint8_t dummy1960[12];
+	uint32_t SWITCH_CORE_NTP_NCO_FREQ_1;
+	uint8_t dummy1961[12];
+	uint32_t SWITCH_CORE_NTP_DOWN_CNTER_0;
+	uint8_t dummy1962[12];
+	uint32_t SWITCH_CORE_NTP_DOWN_CNTER_1;
+	uint8_t dummy1963[12];
+	uint32_t SWITCH_CORE_NTP_ERR_LSB;
+	uint8_t dummy1964[12];
+	uint32_t SWITCH_CORE_NTP_ERR_MSB;
+	uint8_t dummy1965[12];
+	uint32_t SWITCH_CORE_DM_MAC_L1_0;
+	uint8_t dummy1966[12];
+	uint32_t SWITCH_CORE_DM_MAC_L1_1;
+	uint8_t dummy1967[12];
+	uint32_t SWITCH_CORE_DM_MAC_L1_2;
+	uint8_t dummy1968[12];
+	uint32_t SWITCH_CORE_DM_MAC_L2_0;
+	uint8_t dummy1969[12];
+	uint32_t SWITCH_CORE_DM_MAC_L2_1;
+	uint8_t dummy1970[12];
+	uint32_t SWITCH_CORE_DM_MAC_L2_2;
+	uint8_t dummy1971[12];
+	uint32_t SWITCH_CORE_DM_MAC_L3_0;
+	uint8_t dummy1972[12];
+	uint32_t SWITCH_CORE_DM_MAC_L3_1;
+	uint8_t dummy1973[12];
+	uint32_t SWITCH_CORE_DM_MAC_L3_2;
+	uint8_t dummy1974[12];
+	uint32_t SWITCH_CORE_DM_MAC_CTL_0;
+	uint8_t dummy1975[12];
+	uint32_t SWITCH_CORE_DM_MAC_CTL_1;
+	uint8_t dummy1976[12];
+	uint32_t SWITCH_CORE_DM_MAC_CTL_2;
+	uint8_t dummy1977[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_3;
+	uint8_t dummy1978[12];
+	uint32_t SWITCH_CORE_HEARTBEAT_4;
+	uint8_t dummy1979[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P0;
+	uint8_t dummy1980[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P1;
+	uint8_t dummy1981[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P2;
+	uint8_t dummy1982[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P3;
+	uint8_t dummy1983[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P4;
+	uint8_t dummy1984[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P5;
+	uint8_t dummy1985[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P6;
+	uint8_t dummy1986[12];
+	uint32_t SWITCH_CORE_INBAND_CNTL_N_P7;
+	uint8_t dummy1987[12];
+	uint32_t SWITCH_CORE_MEM_COUNTER;
+	uint8_t dummy1988[12];
+	uint32_t SWITCH_CORE_TIMESTAMP_DELTA;
+	uint8_t dummy1989[12];
+	uint32_t SWITCH_CORE_SOP_SEL;
+	uint8_t dummy1990[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_3;
+	uint8_t dummy1991[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_4;
+	uint8_t dummy1992[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_5;
+	uint8_t dummy1993[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_6;
+	uint8_t dummy1994[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_7;
+	uint8_t dummy1995[12];
+	uint32_t SWITCH_CORE_TIME_STAMP_INFO_8;
+	uint8_t dummy1996[12];
+	uint32_t SWITCH_CORE_INBAND_SPARE1;
+	uint8_t dummy1997[140];
+	uint32_t SWITCH_CORE_RED_CONTROL;
+	uint8_t dummy1998[12];
+	uint32_t SWITCH_CORE_TC2RED_PROFILE_TABLE;
+	uint8_t dummy1999[12];
+	uint32_t SWITCH_CORE_RED_EGRESS_BYPASS;
+	uint8_t dummy2000[12];
+	uint32_t SWITCH_CORE_RED_AQD_CONTROL;
+	uint8_t dummy2001[12];
+	uint32_t SWITCH_CORE_RED_EXPONENT;
+	uint8_t dummy2002[12];
+	uint32_t SWITCH_CORE_RED_DROP_ADD_TO_MIB;
+	uint8_t dummy2003[44];
+	uint32_t SWITCH_CORE_RED_PROFILE_DEFAULT;
+	uint8_t dummy2004[28];
+	uint32_t SWITCH_CORE_WRED_REG_SPARE0;
+	uint8_t dummy2005[28];
+	uint32_t SWITCH_CORE_WRED_REG_SPARE1;
+	uint8_t dummy2006[60];
+	uint32_t SWITCH_CORE_RED_PROFILE0;
+	uint8_t dummy2007[28];
+	uint32_t SWITCH_CORE_RED_PROFILE1;
+	uint8_t dummy2008[28];
+	uint32_t SWITCH_CORE_RED_PROFILE2;
+	uint8_t dummy2009[28];
+	uint32_t SWITCH_CORE_RED_PROFILE3;
+	uint8_t dummy2010[28];
+	uint32_t SWITCH_CORE_RED_PROFILE4;
+	uint8_t dummy2011[28];
+	uint32_t SWITCH_CORE_RED_PROFILE5;
+	uint8_t dummy2012[28];
+	uint32_t SWITCH_CORE_RED_PROFILE6;
+	uint8_t dummy2013[28];
+	uint32_t SWITCH_CORE_RED_PROFILE7;
+	uint8_t dummy2014[28];
+	uint32_t SWITCH_CORE_RED_PROFILE8;
+	uint8_t dummy2015[28];
+	uint32_t SWITCH_CORE_RED_PROFILE9;
+	uint8_t dummy2016[28];
+	uint32_t SWITCH_CORE_RED_PROFILE10;
+	uint8_t dummy2017[28];
+	uint32_t SWITCH_CORE_RED_PROFILE11;
+	uint8_t dummy2018[28];
+	uint32_t SWITCH_CORE_RED_PROFILE12;
+	uint8_t dummy2019[28];
+	uint32_t SWITCH_CORE_RED_PROFILE13;
+	uint8_t dummy2020[28];
+	uint32_t SWITCH_CORE_RED_PROFILE14;
+	uint8_t dummy2021[28];
+	uint32_t SWITCH_CORE_RED_PROFILE15;
+	uint8_t dummy2022[124];
+	uint32_t SWITCH_CORE_RED_DROP_CNTR_RST;
+	uint8_t dummy2023[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P0;
+	uint8_t dummy2024[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P1;
+	uint8_t dummy2025[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P2;
+	uint8_t dummy2026[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P3;
+	uint8_t dummy2027[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P4;
+	uint8_t dummy2028[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P5;
+	uint8_t dummy2029[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P6;
+	uint8_t dummy2030[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_P7;
+	uint8_t dummy2031[28];
+	uint32_t SWITCH_CORE_RED_PKT_DROP_CNTR_IMP;
+	uint8_t dummy2032[124];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P0;
+	uint8_t dummy2033[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P1;
+	uint8_t dummy2034[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P2;
+	uint8_t dummy2035[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P3;
+	uint8_t dummy2036[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P4;
+	uint8_t dummy2037[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P5;
+	uint8_t dummy2038[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P6;
+	uint8_t dummy2039[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_P7;
+	uint8_t dummy2040[60];
+	uint32_t SWITCH_CORE_RED_BYTE_DROP_CNTR_IMP;
+	uint8_t dummy2041[20732];
+	uint32_t SWITCH_CORE_CFP_ACC;
+	uint8_t dummy2042[28];
+	uint32_t SWITCH_CORE_RATE_METER_GLOBAL_CTL;
+	uint8_t dummy2043[92];
+	uint32_t SWITCH_CORE_CFP_DATA0;
+	uint8_t dummy2044[28];
+	uint32_t SWITCH_CORE_CFP_DATA1;
+	uint8_t dummy2045[28];
+	uint32_t SWITCH_CORE_CFP_DATA2;
+	uint8_t dummy2046[28];
+	uint32_t SWITCH_CORE_CFP_DATA3;
+	uint8_t dummy2047[28];
+	uint32_t SWITCH_CORE_CFP_DATA4;
+	uint8_t dummy2048[28];
+	uint32_t SWITCH_CORE_CFP_DATA5;
+	uint8_t dummy2049[28];
+	uint32_t SWITCH_CORE_CFP_DATA6;
+	uint8_t dummy2050[28];
+	uint32_t SWITCH_CORE_CFP_DATA7;
+	uint8_t dummy2051[28];
+	uint32_t SWITCH_CORE_CFP_MASK0;
+	uint8_t dummy2052[28];
+	uint32_t SWITCH_CORE_CFP_MASK1;
+	uint8_t dummy2053[28];
+	uint32_t SWITCH_CORE_CFP_MASK2;
+	uint8_t dummy2054[28];
+	uint32_t SWITCH_CORE_CFP_MASK3;
+	uint8_t dummy2055[28];
+	uint32_t SWITCH_CORE_CFP_MASK4;
+	uint8_t dummy2056[28];
+	uint32_t SWITCH_CORE_CFP_MASK5;
+	uint8_t dummy2057[28];
+	uint32_t SWITCH_CORE_CFP_MASK6;
+	uint8_t dummy2058[28];
+	uint32_t SWITCH_CORE_CFP_MASK7;
+	uint8_t dummy2059[28];
+	uint32_t SWITCH_CORE_ACT_POL_DATA0;
+	uint8_t dummy2060[28];
+	uint32_t SWITCH_CORE_ACT_POL_DATA1;
+	uint8_t dummy2061[28];
+	uint32_t SWITCH_CORE_ACT_POL_DATA2;
+	uint8_t dummy2062[60];
+	uint32_t SWITCH_CORE_RATE_METER0;
+	uint8_t dummy2063[28];
+	uint32_t SWITCH_CORE_RATE_METER1;
+	uint8_t dummy2064[28];
+	uint32_t SWITCH_CORE_RATE_METER2;
+	uint8_t dummy2065[28];
+	uint32_t SWITCH_CORE_RATE_METER3;
+	uint8_t dummy2066[28];
+	uint32_t SWITCH_CORE_RATE_METER4;
+	uint8_t dummy2067[28];
+	uint32_t SWITCH_CORE_RATE_METER5;
+	uint8_t dummy2068[28];
+	uint32_t SWITCH_CORE_RATE_METER6;
+	uint8_t dummy2069[28];
+	uint32_t SWITCH_CORE_TC2COLOR;
+	uint8_t dummy2070[28];
+	uint32_t SWITCH_CORE_STAT_GREEN_CNTR;
+	uint8_t dummy2071[28];
+	uint32_t SWITCH_CORE_STAT_YELLOW_CNTR;
+	uint8_t dummy2072[28];
+	uint32_t SWITCH_CORE_STAT_RED_CNTR;
+	uint8_t dummy2073[188];
+	uint32_t SWITCH_CORE_TCAM_BIST_CONTROL;
+	uint8_t dummy2074[28];
+	uint32_t SWITCH_CORE_TCAM_BIST_STATUS;
+	uint8_t dummy2075[28];
+	uint32_t SWITCH_CORE_TCAM_TEST_COMPARE_STATUS;
+	uint8_t dummy2076[60];
+	uint32_t SWITCH_CORE_CFP_REG_SPARE0;
+	uint8_t dummy2077[28];
+	uint32_t SWITCH_CORE_CFP_REG_SPARE1;
+	uint8_t dummy2078[604];
+	uint32_t SWITCH_CORE_CFP_CTL_REG;
+	uint8_t dummy2079[124];
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_0;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_1;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_2;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_3;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_4;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_5;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_6;
+	uint64_t SWITCH_CORE_UDF_0_A_0_8_7;
+	uint32_t SWITCH_CORE_UDF_0_A_0_8_8;
+	uint8_t dummy2080[60];
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_0;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_1;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_2;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_3;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_4;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_5;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_6;
+	uint64_t SWITCH_CORE_UDF_1_A_0_8_7;
+	uint32_t SWITCH_CORE_UDF_1_A_0_8_8;
+	uint8_t dummy2081[60];
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_0;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_1;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_2;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_3;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_4;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_5;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_6;
+	uint64_t SWITCH_CORE_UDF_2_A_0_8_7;
+	uint32_t SWITCH_CORE_UDF_2_A_0_8_8;
+	uint8_t dummy2082[60];
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_0;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_1;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_2;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_3;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_4;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_5;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_6;
+	uint64_t SWITCH_CORE_UDF_0_B_0_8_7;
+	uint32_t SWITCH_CORE_UDF_0_B_0_8_8;
+	uint8_t dummy2083[60];
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_0;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_1;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_2;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_3;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_4;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_5;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_6;
+	uint64_t SWITCH_CORE_UDF_1_B_0_8_7;
+	uint32_t SWITCH_CORE_UDF_1_B_0_8_8;
+	uint8_t dummy2084[60];
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_0;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_1;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_2;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_3;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_4;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_5;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_6;
+	uint64_t SWITCH_CORE_UDF_2_B_0_8_7;
+	uint32_t SWITCH_CORE_UDF_2_B_0_8_8;
+	uint8_t dummy2085[60];
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_0;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_1;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_2;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_3;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_4;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_5;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_6;
+	uint64_t SWITCH_CORE_UDF_0_C_0_8_7;
+	uint32_t SWITCH_CORE_UDF_0_C_0_8_8;
+	uint8_t dummy2086[60];
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_0;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_1;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_2;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_3;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_4;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_5;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_6;
+	uint64_t SWITCH_CORE_UDF_1_C_0_8_7;
+	uint32_t SWITCH_CORE_UDF_1_C_0_8_8;
+	uint8_t dummy2087[60];
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_0;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_1;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_2;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_3;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_4;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_5;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_6;
+	uint64_t SWITCH_CORE_UDF_2_C_0_8_7;
+	uint32_t SWITCH_CORE_UDF_2_C_0_8_8;
+	uint8_t dummy2088[60];
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_0;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_1;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_2;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_3;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_4;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_5;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_6;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_7;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_8;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_9;
+	uint64_t SWITCH_CORE_UDF_0_D_0_11_10;
+	uint32_t SWITCH_CORE_UDF_0_D_0_11_11;
+	uint8_t dummy2089[29348];
+	uint32_t SWITCH_CORE_ARL_TCAM_ACC;
+	uint8_t dummy2090[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_DATA_P0;
+	uint8_t dummy2091[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_DATA_P1;
+	uint8_t dummy2092[92];
+	uint32_t SWITCH_CORE_ARL_SMEM_DATA;
+	uint8_t dummy2093[92];
+	uint32_t SWITCH_CORE_ARL_TCAM_BIST_CTRL;
+	uint8_t dummy2094[28];
+	uint32_t SWITCH_CORE_ARL_TCAM_BIST_STS;
+	uint8_t dummy2095[100060];
+	uint32_t SWITCH_CORE_PLL_NDIV_INT;
+	uint8_t dummy2096[12];
+	uint32_t SWITCH_CORE_PLL_NDIV_FRAC;
+	uint8_t dummy2097[28];
+	uint32_t SWITCH_CORE_PLL_SDMOD_CTRL;
+	uint8_t dummy2098[12];
+	uint32_t SWITCH_CORE_PLL_MOD_CTRL_0;
+	uint8_t dummy2099[28];
+	uint32_t SWITCH_CORE_PLL_MOD_CTRL_1;
+	uint8_t dummy2100[28];
+	uint32_t SWITCH_CORE_PLL_MOD_CTRL_2;
+	uint8_t dummy2101[28];
+	uint32_t SWITCH_CORE_PLL_MISC_CTRL;
+	uint8_t dummy2102[12];
+	uint32_t SWITCH_CORE_PLL_DELOCK_MIB;
+	uint8_t dummy2103[28];
+	uint32_t SWITCH_CORE_PLL_SS_CTL;
+	uint8_t dummy2104[44];
+	uint32_t SWITCH_CORE_PLL_CTRL;
+	uint8_t dummy2105[12];
+	uint32_t SWITCH_CORE_PLL_STS;
+	uint8_t dummy2106[60];
+	uint32_t SWITCH_CORE_PLL_FREQ_SEL;
+	uint8_t dummy2107[44];
+	uint32_t SWITCH_CORE_PLL_TEST_CTRL_I;
+	uint8_t dummy2108[12];
+	uint32_t SWITCH_CORE_PLL_TEST_CTRL_II;
+	uint8_t dummy2109[108];
+	uint32_t SWITCH_CORE_GREEN_MODE_DATA;
+	uint8_t dummy2110[60];
+	uint32_t SWITCH_CORE_GREEN_MODE_SELECT;
+	uint8_t dummy2111[444];
+	uint32_t SWITCH_CORE_TOP_LOW_POWER_CTRL;
+	uint8_t dummy2112[12];
+	uint32_t SWITCH_CORE_TOP_IDDQ_CTL;
+	uint8_t dummy2113[108];
+	uint32_t SWITCH_CORE_IP_PLL_BYPASS;
+	uint8_t dummy2114[636];
+	uint32_t SWITCH_CORE_TOP_MODULE_CTL_SPARE0;
+	uint8_t dummy2115[28];
+	uint32_t SWITCH_CORE_TOP_MODULE_CTL_SPARE1;
+	uint8_t dummy2116[220];
+	uint32_t SWITCH_CORE_EGPHY_CTRL;
+	uint8_t dummy2117[12];
+	uint32_t SWITCH_CORE_EGPHY_PWRMGNT;
+	uint8_t dummy2118[12];
+	uint32_t SWITCH_CORE_EGPHY_PWR_DOWN;
+	uint8_t dummy2119[44];
+	uint32_t SWITCH_CORE_EGPHY_STRAP;
+	uint8_t dummy2120[12];
+	uint32_t SWITCH_CORE_EGPHY_STS;
+	uint8_t dummy2121[12];
+	uint32_t SWITCH_CORE_EGPHY_INT_STS;
+	uint8_t dummy2122[12];
+	uint32_t SWITCH_CORE_EGPHY_MODE_STS;
+	uint8_t dummy2123[12];
+	uint32_t SWITCH_CORE_EGPHY_LPI_STS;
+	uint8_t dummy2124[12];
+	uint32_t SWITCH_CORE_EGPHY_ENG_DET_STS;
+	uint8_t dummy2125[12];
+	uint32_t SWITCH_CORE_EGPHY_ENG_DET_STS_CHG;
+	uint8_t dummy2126[12];
+	uint32_t SWITCH_CORE_EGPHY_RESET_STATUS;
+	uint8_t dummy2127[1596];
+	uint32_t SWITCH_CORE_EGPHY_CTL_SPARE0;
+	uint8_t dummy2128[28];
+	uint32_t SWITCH_CORE_EGPHY_CTL_SPARE1;
+	uint8_t dummy2129[220];
+	uint32_t SWITCH_CORE_BRPHY_CTRL;
+	uint8_t dummy2130[12];
+	uint32_t SWITCH_CORE_BRPHY_PWRMGNT;
+	uint8_t dummy2131[12];
+	uint32_t SWITCH_CORE_BRPHY_PWR_DOWN;
+	uint8_t dummy2132[28];
+	uint32_t SWITCH_CORE_BRPHY_PLL_CTRL;
+	uint8_t dummy2133[28];
+	uint32_t SWITCH_CORE_BRPHY_STS;
+	uint8_t dummy2134[12];
+	uint32_t SWITCH_CORE_BRPHY_INT_STS;
+	uint8_t dummy2135[44];
+	uint32_t SWITCH_CORE_BRPHY_ENG_DET_STS;
+	uint8_t dummy2136[12];
+	uint32_t SWITCH_CORE_BRPHY_ENG_DET_STS_CHG;
+	uint8_t dummy2137[12];
+	uint32_t SWITCH_CORE_BRPHY_RESET_STATUS;
+	uint8_t dummy2138[1596];
+	uint32_t SWITCH_CORE_BRPHY_CTL_SPARE0;
+	uint8_t dummy2139[28];
+	uint32_t SWITCH_CORE_BRPHY_CTL_SPARE1;
+	uint8_t dummy2140[220];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P0;
+	uint8_t dummy2141[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P1;
+	uint8_t dummy2142[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P2;
+	uint8_t dummy2143[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P3;
+	uint8_t dummy2144[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P4;
+	uint8_t dummy2145[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P5;
+	uint8_t dummy2146[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_P6;
+	uint8_t dummy2147[12];
+	uint32_t SWITCH_CORE_STS_OVERRIDE_GMII_P7;
+	uint8_t dummy2148[12];
+	uint32_t imp_port_state;
+#define ETHSW_IPS_USE_MII_HW_STS                  0x00
+#define ETHSW_IPS_USE_REG_CONTENTS                0x80
+#define ETHSW_IPS_GMII_SPEED_UP_NORMAL            0x00
+#define ETHSW_IPS_GMII_SPEED_UP_2G                0x40
+#define ETHSW_IPS_TXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_TXFLOW_PAUSE_CAPABLE            0x20
+#define ETHSW_IPS_RXFLOW_NOT_PAUSE_CAPABLE        0x00
+#define ETHSW_IPS_RXFLOW_PAUSE_CAPABLE            0x10
+#define ETHSW_IPS_SW_PORT_SPEED_1000M_2000M       0x08
+#define ETHSW_IPS_DUPLEX_MODE                     0x02
+#define ETHSW_IPS_LINK_FAIL                       0x00
+#define ETHSW_IPS_LINK_PASS                       0x01
+	uint8_t dummy2149[60];
+	uint32_t SWITCH_CORE_PAUSE_CAP;
+	uint8_t dummy2150[124];
+	uint32_t SWITCH_CORE_PORT4_RGMII_CTL_GP;
+	uint8_t dummy2151[12];
+	uint32_t SWITCH_CORE_PORT5_RGMII_CTL_GP;
+	uint8_t dummy2152[12];
+	uint32_t SWITCH_CORE_PORT6_RGMII_CTL_GP;
+	uint8_t dummy2153[28];
+	uint32_t SWITCH_CORE_RGMII_CTL_GP_IMP;
+	uint8_t dummy2154[188];
+	uint32_t SWITCH_CORE_P4_RGMII_TIME_DLY_GP;
+	uint8_t dummy2155[12];
+	uint32_t SWITCH_CORE_P5_RGMII_TIME_DLY_GP;
+	uint8_t dummy2156[12];
+	uint32_t SWITCH_CORE_P6_RGMII_TIME_DLY_GP;
+	uint8_t dummy2157[28];
+	uint32_t SWITCH_CORE_RGMII_TIME_DLY_GP_IMP;
+	uint8_t dummy2158[124];
+	uint32_t SWITCH_CORE_RM_PINS_DEBUG;
+	uint8_t dummy2159[12];
+	uint32_t SWITCH_CORE_MII_IDDQ_CTRL;
+	uint8_t dummy2160[12];
+	uint32_t SWITCH_CORE_MII_LOW_POWER_CTRL;
+	uint8_t dummy2161[12];
+	uint32_t SWITCH_CORE_LED_OPTIONS;
+	uint8_t dummy2162[972];
+	uint32_t SWITCH_CORE_PORT_INFO_SPARE0;
+	uint8_t dummy2163[28];
+	uint32_t SWITCH_CORE_PORT_INFO_SPARE1;
+	uint8_t dummy2164[220];
+	uint32_t SWITCH_CORE_IO_SR_CTL;
+	uint8_t dummy2165[28];
+	uint32_t SWITCH_CORE_IO_DS_SEL0;
+	uint8_t dummy2166[60];
+	uint32_t SWITCH_CORE_IO_DS_SEL2;
+	uint8_t dummy2167[28];
+	uint32_t SWITCH_CORE_GMII_IO_SR_CTL;
+	uint8_t dummy2168[28];
+	uint32_t SWITCH_CORE_GMII_IO_DS_SEL0;
+	uint8_t dummy2169[28];
+	uint32_t SWITCH_CORE_GMII_IO_DS_SEL1;
+	uint8_t dummy2170[28];
+	uint32_t SWITCH_CORE_GMII_VOL_SEL;
+	uint8_t dummy2171[12];
+	uint32_t SWITCH_CORE_PINS_DEBUG_IMP;
+	uint8_t dummy2172[28];
+	uint32_t SWITCH_CORE_BONDING_PAD_STATUS;
+	uint8_t dummy2173[12];
+	uint32_t SWITCH_CORE_STRAP_PIN_STATUS;
+	uint8_t dummy2174[28];
+	uint32_t SWITCH_CORE_DIRECT_INPUT_CTRL_VALUE;
+	uint8_t dummy2175[60];
+	uint32_t SWITCH_CORE_EMB_CPU_STATUS;
+	uint8_t dummy2176[1404];
+	uint32_t SWITCH_CORE_CHIP_CTL_SPARE0;
+	uint8_t dummy2177[28];
+	uint32_t SWITCH_CORE_CHIP_CTL_SPARE1;
+
+} EthernetSwitchCore;
+
+#define PBMAP_MIPS 0x100
+
+#endif /* _6756_ETHSW_H */
diff --git a/arch/arm/include/asm/arch-bcm6756/misc.h b/arch/arm/include/asm/arch-bcm6756/misc.h
new file mode 100644
index 0000000000..c9bc0dbf40
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/misc.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6756_MISC_H
+#define _6756_MISC_H
+
+/*
+ * Gpio Controller
+ */
+typedef struct GpioControl {
+        uint32_t GPIODir[8];             /* 0x00-0x1c */
+        uint32_t GPIOio[8];              /* 0x20-0x3c */
+        uint32_t PadCtrl;                 /* 0x40 */
+        uint32_t SpiSlaveCfg;             /* 0x44 */
+        uint32_t TestControl;             /* 0x48 */
+        uint32_t TestPortBlockEnMSB;      /* 0x4c */
+        uint32_t TestPortBlockEnLSB;      /* 0x50 */
+        uint32_t TestPortBlockDataMSB;    /* 0x54 */
+        uint32_t TestPortBlockDataLSB;    /* 0x58 */
+#define PINMUX_DATA_SHIFT       12
+#define PINMUX_0                0
+#define PINMUX_1                1
+#define PINMUX_2                2
+#define PINMUX_3                3
+#define PINMUX_4                4
+#define PINMUX_5                5
+#define PINMUX_6                6
+#define PINMUX_7                7
+#define PAD_CTRL_SHIFT          12
+#define PAD_CTRL_MASK           (0x3f<<PAD_CTRL_SHIFT)
+#define PAD_SEL_SHIFT           12
+#define PAD_AMP_SHIFT           15
+#define PAD_IND_SHIFT           16
+#define PAD_GMII_SHIFT          17
+       uint32_t TestPortCmd;             /* 0x5c */
+#define LOAD_MUX_REG_CMD        0x21
+#define LOAD_PAD_CTRL_CMD       0x22
+        uint32_t DiagReadBack;            /* 0x60 */
+        uint32_t DiagReadBackHi;          /* 0x64 */
+        uint32_t GeneralPurpose;          /* 0x68 */
+        uint32_t spare[3];
+} GpioControl;
+
+#define GPIO_BASE          0xff800500
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+
+#define MISC_BASE          0xff802600
+
+/*
+ * Misc Register Set Definitions.
+ */
+typedef struct Misc {
+    uint32_t  miscStrapBus;                       /* 0x00 */
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           0
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_PCIE0_RC_MODE            (0x1 << 6)
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT      9
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ            (0x1 << MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT)
+#define MISC_STRAP_BUS_BOOTROM_BOOT             (0x1 << 12)
+    uint32_t  miscStrapOverride;                  /* 0x04 */
+    uint32_t  miscMaskUBUSErr;                    /* 0x08 */
+    uint32_t  miscPeriphCtrl;                     /* 0x0c */
+    uint32_t  miscSPImasterCtrl;                  /* 0x10 */
+    uint32_t  miscDierevid;                       /* 0x14 */
+    uint32_t  miscPeriphMiscCtrl;                 /* 0x18 */
+    uint32_t  miscPeriphMiscStat;                 /* 0x1c */
+    uint32_t  miscSoftResetB;                     /* 0x20 */
+    uint32_t  reserved0;                          /* 0x24 */
+    uint32_t  miscSWdebugNW[2];                   /* 0x28 */
+    uint32_t  miscWDresetCtrl;                    /* 0x30 */
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+typedef struct TopControl {
+   uint32_t      MiiPadCtl;          // 0x0
+   uint32_t      Rgmii1PadCtl;       // 0x4
+   uint32_t      Rgmii2PadCtl;       // 0x8
+   uint32_t      Rgmii3PadCtl;       // 0xc
+   uint32_t      MiiPullCtl;         // 0x10
+   uint32_t      Rgmii1PullCtl;      // 0x14
+   uint32_t      Rgmii2PullCtl;      // 0x18
+   uint32_t      Rgmii3PullCtl;      // 0x1c
+   uint32_t      SgmiiFiberDetect;   // 0x20
+   uint32_t      DgSensePadCtl;      // 0x24
+#define DG_CTRL_SHIFT   4
+#define DG_CTRL_MASK    0x00000030   
+#define DG_EN_SHIFT     3
+#define DG_TRIM_SHIFT   0
+#define DG_TRIM_MASK    0x00000007   
+   uint32_t      TpDirOverride0;     // 0x28
+   uint32_t      TpDirOverride1;     // 0x2c
+   uint32_t      RescalReadData0;    // 0x30
+   uint32_t      RescalReadData1;    // 0x34
+   uint32_t      reserved0;          // 0x38 
+   uint32_t      ResetStatus;        // 0x3c 
+#define PCIE_RESET_STATUS       0x10000000
+#define SW_RESET_STATUS         0x20000000
+#define HW_RESET_STATUS         0x40000000
+#define POR_RESET_STATUS        0x80000000
+#define RESET_STATUS_MASK       0xF0000000
+   uint32_t      TodSync;            // 0x40
+   uint32_t      Pm0Pm1RescalSts;    // 0x44
+   uint32_t      Pm2Pm3RescalSts;    // 0x48
+   uint32_t      SgbRescalSts;       // 0x4c
+   uint32_t      Pm0Pm1RescalCfg;    // 0x50
+   uint32_t      Pm2Pm3RescalCfg;    // 0x54
+   uint32_t      SgbRescalCfg;       // 0x58
+   uint32_t      Pm0Pm1TmonCfg;      // 0x5c
+   uint32_t      Pm2Pm3TmonCfg;      // 0x60
+   uint32_t      SgbTmonCfg;         // 0x64
+   uint32_t      MdioMasterSelect;   // 0x68
+   uint32_t      SwControlReg;       // 0x6c
+   uint32_t      Reg2P5VDectCtrl;    // 0x70
+   uint32_t      OrionIntPending;    // 0x74
+   uint32_t      DslClockSample;     // 0x78
+   uint32_t      LdoCtl;             // 0x7c
+#define LDO_VREG_CTRL_EN           0x400000
+#define LDO_VREG_CTRL_SHIFT        1
+#define LDO_VREG_CTRL_MASK         (0x1fffff << LDO_VREG_CTRL_SHIFT)
+#define LDO_VREG_CTRL_TRIM_SHIFT   2
+#define LDO_VREG_CTRL_TRIM_MASK    (0xf << LDO_VREG_CTRL_TRIM_SHIFT)
+#define LDO_VREG_CTRL_SELECT_SHIFT 6
+#define LDO_VREG_CTRL_SELECT_MASK  (0xf << LDO_VREG_CTRL_SELECT_SHIFT)
+#define LDO_VREG_CTRL_PWRDN        0x1
+} TopControl;
+
+#define TOP_CONTROL_BASE           0xff85a000
+#define TOPCTRL ((volatile TopControl * const) TOP_CONTROL_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6756/otp.h b/arch/arm/include/asm/arch-bcm6756/otp.h
new file mode 100644
index 0000000000..8defa3f9e2
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/otp.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _6756_OTP_H
+#define _6756_OTP_H
+
+
+#define JTAG_OTP_BASE   0xff802800
+
+/* row 8 */
+#define OTP_CPU_CORE_CFG_ROW            8
+#define OTP_CPU_CORE_CFG_SHIFT          28
+#define OTP_CPU_CORE_CFG_MASK           0x7
+
+/* row 9 */
+#define OTP_CPU_CLOCK_FREQ_ROW          9
+#define OTP_CPU_CLOCK_FREQ_SHIFT        0
+#define OTP_CPU_CLOCK_FREQ_MASK         0x7
+
+#define OTP_LDO_TRIM_ROW                9
+#define OTP_LDO_TRIM_SHIFT              28
+#define OTP_LDO_TRIM_MASK               0xf
+
+/* row 14 */
+#define OTP_SGMII_DISABLE_ROW           14
+#define OTP_SGMII_DISABLE_SHIFT         5
+#define OTP_SGMII_DISABLE_MASK          0x1
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          7
+
+/* row 23 */
+#define OTP_CUST_MFG_MRKTID_ROW                 23
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+/* row 9 */
+#define OTP_LDO_TRIM_ROW                9
+#define OTP_LDO_TRIM_SHIFT              28
+#define OTP_LDO_TRIM_MASK               0xf
+
+/* row 14 */
+#define OTP_SGMII_DISABLE_ROW           14
+#define OTP_SGMII_DISABLE_SHIFT         5
+#define OTP_SGMII_DISABLE_MASK          0x1
+
+
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_CPU_CORE_CFG, OTP_CPU_CORE_CFG_ROW, OTP_CPU_CORE_CFG_MASK, OTP_CPU_CORE_CFG_SHIFT, 1},				\
+	{OTP_MAP_LDO_TRIM, OTP_LDO_TRIM_ROW, OTP_LDO_TRIM_MASK, OTP_LDO_TRIM_SHIFT, 1},				\
+	}
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6756/pmc.h b/arch/arm/include/asm/arch-bcm6756/pmc.h
new file mode 100644
index 0000000000..b7402bd156
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/pmc.h
@@ -0,0 +1,336 @@
+#ifndef PMC_H
+#define PMC_H 
+/*
+ * Power Management Control
+ */
+typedef struct PmcCtrlReg {
+    uint32_t gpTmr0Ctl;           /* 0x018 */
+    uint32_t gpTmr0Cnt;           /* 0x01c */
+    uint32_t gpTmr1Ctl;           /* 0x020 */
+    uint32_t gpTmr1Cnt;           /* 0x024 */
+    uint32_t hostMboxIn;          /* 0x028 */
+    uint32_t hostMboxOut;         /* 0x02c */
+    uint32_t reserved[4];         /* 0x030 */
+    uint32_t dmaCtrl;             /* 0x040 */
+    uint32_t dmaStatus;           /* 0x044 */
+    uint32_t dma0_3FifoStatus;    /* 0x048 */
+    uint32_t reserved1[4];	    /* 0x04c */
+    uint32_t diagControl;         /* 0x05c */
+    uint32_t diagHigh;            /* 0x060 */
+    uint32_t diagLow;             /* 0x064 */
+    uint32_t reserved8;           /* 0x068 */
+    uint32_t addr1WndwMask;       /* 0x06c */
+    uint32_t addr1WndwBaseIn;     /* 0x070 */
+    uint32_t addr1WndwBaseOut;    /* 0x074 */
+    uint32_t addr2WndwMask;       /* 0x078 */
+    uint32_t addr2WndwBaseIn;     /* 0x07c */
+    uint32_t addr2WndwBaseOut;    /* 0x080 */
+    uint32_t scratch;             /* 0x084 */
+    uint32_t reserved9;           /* 0x088 */
+    uint32_t softResets;          /* 0x08c */
+    uint32_t reserved2;           /* 0x090 */
+    uint32_t m4keCoreStatus;      /* 0x094 */
+    uint32_t reserved3;           /* 0x098 */
+    uint32_t ubSlaveTimeout;      /* 0x09c */
+    uint32_t diagEn;              /* 0x0a0 */
+    uint32_t devTimeout;          /* 0x0a4 */
+    uint32_t ubusErrorOutMask;    /* 0x0a8 */
+    uint32_t diagCaptStopMask;    /* 0x0ac */
+    uint32_t revId;               /* 0x0b0 */
+    uint32_t reserved4[4];        /* 0x0b4 */
+    uint32_t diagCtrl;            /* 0x0c4 */
+    uint32_t diagStat;            /* 0x0c8 */
+    uint32_t diagMask;            /* 0x0cc */
+    uint32_t diagRslt;            /* 0x0d0 */
+    uint32_t diagCmp;             /* 0x0d4 */
+    uint32_t diagCapt;            /* 0x0d8 */    
+    uint32_t diagCnt;             /* 0x0dc */
+    uint32_t diagEdgeCnt;         /* 0x0e0 */
+    uint32_t reserved5[4];	    /* 0x0e4 */
+    uint32_t smisc_bus_config;    /* 0x0f4 */
+    uint32_t lfsr;                /* 0x0f8 */
+    uint32_t dqm_pac_lock;        /* 0x0fc */
+    uint32_t l1_irq_4ke_mask;     /* 0x100 */
+    uint32_t l1_irq_4ke_status;   /* 0x104 */
+    uint32_t l1_irq_mips_mask;    /* 0x108 */
+    uint32_t l1_irq_mips_status;  /* 0x10c */
+    uint32_t l1_irq_mips1_mask;   /* 0x110 */
+    uint32_t reserved6[3];        /* 0x114 */
+    uint32_t l2_irq_gp_mask;      /* 0x120 */
+    uint32_t l2_irq_gp_status;    /* 0x124 */
+    uint32_t l2_irq_gp_set;       /* 0x128 */
+    uint32_t reserved7;           /* 0x12c */
+    uint32_t gp_in_irq_mask;      /* 0x130 */
+    uint32_t gp_in_irq_status;    /* 0x134 */
+    uint32_t gp_in_irq_set;       /* 0x138 */
+    uint32_t gp_in_irq_sense;     /* 0x13c */
+    uint32_t gp_in;               /* 0x140 */
+    uint32_t gp_out;              /* 0x144 */
+} PmcCtrlReg;
+
+typedef struct PmcDmaReg {
+	/* 0x00 */
+	uint32_t src;
+	uint32_t dest;
+	uint32_t cmdList;
+	uint32_t lenCtl;
+	/* 0x10 */
+	uint32_t rsltSrc;
+	uint32_t rsltDest;
+	uint32_t rsltHcs;
+	uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+	/* 0x00 */
+	uint32_t bufSize;
+	uint32_t bufBase;
+	uint32_t idx2ptrIdx;
+	uint32_t idx2ptrPtr;
+	/* 0x10 */
+	uint32_t unused[2];
+	uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+	uint32_t freqScalarCtrl; /* 0x3c */
+	uint32_t freqScalarMask; /* 0x40 */
+} PmcPerfPowReg;
+
+typedef struct PmcDQMPac {
+    uint32_t dqmPac[32];
+} PmcDQMPac;
+
+typedef struct PmcDQMReg {
+	uint32_t cfg;                     /* 0x1c00 */
+	uint32_t _4keLowWtmkIrqMask;      /* 0x1c04 */
+	uint32_t mipsLowWtmkIrqMask;      /* 0x1c08 */
+	uint32_t lowWtmkIrqMask;          /* 0x1c0c */
+	uint32_t _4keNotEmptyIrqMask;     /* 0x1c10 */
+	uint32_t mipsNotEmptyIrqMask;     /* 0x1c14 */
+	uint32_t notEmptyIrqSts;          /* 0x1c18 */
+	uint32_t queueRst;                /* 0x1c1c */
+	uint32_t notEmptySts;             /* 0x1c20 */
+	uint32_t nextAvailMask;           /* 0x1c24 */
+	uint32_t nextAvailQueue;          /* 0x1c28 */
+	uint32_t mips1LowWtmkIrqMask;     /* 0x1c2c */
+	uint32_t mips1NotEmptyIrqMask;    /* 0x1c30 */
+	uint32_t autoSrcPidInsert;        /* 0x1c34 */
+    uint32_t timerIrqStatus;          /* 0x1c38 */
+    uint32_t timerStatus;             /* 0x1c3c */
+    uint32_t _4keTimerIrqMask;        /* 0x1c40 */
+    uint32_t mipsTimerIrqMask;        /* 0x1c44 */
+    uint32_t mips1TimerIrqMask;       /* 0x1c48 */
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+	uint32_t cntr[10];
+	uint32_t unused[6];	/* 0x28-0x3f */
+	uint32_t cntrIrqMask;
+	uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+	uint32_t size;
+	uint32_t cfga;
+	uint32_t cfgb;
+	uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+	uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+	uint32_t qNumFull[32];
+	uint32_t qNumEmpty[32];
+	uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+typedef struct SSBMaster {
+    uint32_t ssbmControl;     /* 0x0060 */
+    uint32_t ssbmWrData;      /* 0x0064 */
+    uint32_t ssbmRdData;      /* 0x0068 */
+    uint32_t ssbmStatus;      /* 0x006c */
+} SSBMaster;
+
+typedef struct PmmReg {
+    uint32_t memPowerCtrl;            /* 0x0000 */
+    uint32_t regSecurityConfig;       /* 0x0004 */
+} PmmReg;
+
+typedef struct keyholeReg {
+    uint32_t ctrlSts;
+    uint32_t wrData;
+    uint32_t mutex;
+    uint32_t rdData;
+} keyholeReg;
+
+typedef struct PmbBus {
+    uint32_t config;          /* 0x0100 */
+    uint32_t arbiter;         /* 0x0104 */
+    uint32_t timeout;         /* 0x0108 */
+    uint32_t unused1;         /* 0x010c */
+    keyholeReg keyhole[4];  /* 0x0110-0x014f */
+    uint32_t unused2[44];     /* 0x0150-0x01ff */
+    uint32_t map[64];         /* 0x0200-0x02ff */ 
+}PmbBus;
+
+typedef struct  CoreCtrl {
+    uint32_t  coreEnable;         /* 0x0400 */
+    uint32_t  autoresetControl;   /* 0x0404 */
+    uint32_t  coreIdle;           /* 0x0408 */
+    uint32_t  coreResetCause;     /* 0x040c */
+    uint32_t  memPwrDownCtrl0;    /* 0x0410 */
+    uint32_t  memPwrDownSts0;     /* 0x0414 */
+    uint32_t  memPwrDownCtrl1;    /* 0x0418 */
+    uint32_t  memPwrDownSts1;     /* 0x041c */
+    uint32_t  sysFlg0Status;      /* 0x0420 */
+    uint32_t  sysFlg0Set;         /* 0x0424 */
+    uint32_t  sysFlg0Clear;       /* 0x0428 */
+    uint32_t  unused1;            /* 0x042c */
+    uint32_t  usrFlg0Status;      /* 0x0430 */
+    uint32_t  usrFlg0Set;         /* 0x0434 */
+    uint32_t  usrFlg0Clear;       /* 0x0438 */
+    uint32_t  unused2;            /* 0x043c */
+    uint32_t  subsystemRev;       /* 0x0440 */
+    uint32_t  resetVector;        /* 0x0444 */
+} CoreCtrl;
+
+typedef struct  CoreState {
+    uint32_t  sysMbx[8];          /* 0x0480 */
+    uint32_t  usrMbx[8];          /* 0x04a0 */
+    uint32_t  sysMtx[4];          /* 0x04c0 */
+    uint32_t  usrMtx[8];          /* 0x04d0 */
+} CoreState;
+
+typedef struct  CoreIntr {
+    uint32_t  irqStatus;          /* 0x0500 */
+    uint32_t  irqSet;             /* 0x0504 */
+    uint32_t  irqClear;           /* 0x0508 */
+    uint32_t  unused1;            /* 0x050c */
+    uint32_t  srqStatus;          /* 0x0510 */
+    uint32_t  srqSet;             /* 0x0514 */
+    uint32_t  srqClear;           /* 0x0518 */
+    uint32_t  unused2;            /* 0x051c */
+    uint32_t  drqStatus;          /* 0x0520 */
+    uint32_t  drqSet;             /* 0x0524 */
+    uint32_t  drqClear;           /* 0x0528 */
+    uint32_t  unused3;            /* 0x052c */
+    uint32_t  frqStatus;          /* 0x0530 */
+    uint32_t  frqSet;             /* 0x0534 */
+    uint32_t  frqClear;           /* 0x0538 */
+    uint32_t  unused4;            /* 0x053c */
+    uint32_t  hostIrqLatched;     /* 0x0540 */
+    uint32_t  hostIrqSet;         /* 0x0544 */
+    uint32_t  hostIrqClear;       /* 0x0548 */
+    uint32_t  hostIrqEnable;      /* 0x054c */
+    uint32_t  obusFaultStatus;    /* 0x0550 */
+    uint32_t  obusFaultClear;     /* 0x0554 */
+    uint32_t  obusFaultAddr;      /* 0x0558 */
+} CoreIntr;
+
+typedef struct CoreProfile {
+    uint32_t  mutex;              /* 0x0580 */
+    uint32_t  lastConfPcLo;       /* 0x0584 */
+    uint32_t  lastConfPcHi;       /* 0x0588 */
+    uint32_t  lastPcLo;           /* 0x058c */
+    uint32_t  lastPcHi;           /* 0x0590 */
+    uint32_t  braTargetPc0Lo;     /* 0x0594 */
+    uint32_t  braTargetPc0Hi;     /* 0x0598 */
+    uint32_t  braTargetPc1Lo;     /* 0x059c */
+    uint32_t  braTargetPc1Hi;     /* 0x05a0 */
+    uint32_t  braTargetPc2Lo;     /* 0x05a4 */
+    uint32_t  braTargetPc2Hi;     /* 0x05a8 */
+    uint32_t  braTargetPc3Lo;     /* 0x05ac */
+    uint32_t  braTargetPc3Hi;     /* 0x05b0 */
+    uint32_t  unused[3];          /* 0x05b4-0x05bf */
+    uint32_t  profSampleW[4];     /* 0x05c0 */
+} CoreProfile;
+
+typedef struct MaestroMisc {
+    CoreCtrl coreCtrl;          /* 0x0400 */
+    uint32_t   unused1[14];       /* 0x0448-0x047f */
+    CoreState coreState;        /* 0x0480 */
+    uint32_t   unused2[4];        /* 0x04f0-0x04ff */
+    CoreIntr interrupt;         /* 0x0500 */
+    uint32_t   unused3[9];        /* 0x055c-0x057f */
+    CoreProfile profile;        /* 0x0580 */
+} MaestroMisc;
+
+typedef struct Pmc {
+    uint32_t unused0[1030];
+    PmcCtrlReg ctrl;		            /* 0x1018 */
+    uint32_t unused1[622];	            /* 0x1148-0x1cff */
+    PmcDQMPac dqmPac;                   /* 0x1b00 */
+    uint32_t unused5[32];                 /* 0x1b80-0x1bff */
+    PmcDQMReg dqm;			            /* 0x1c00 */
+    uint32_t unused6[749];		        /* 0x1c4c-0x27ff */
+    uint32_t qStatus[32];		            /* 0x2800 */
+    uint32_t unused7[480];	            /* 0x2880-0x2fff */
+    PmcDqmQMibReg qMib;		            /* 0x3000 */
+    uint32_t unused8[928];	            /* 0x3180-0x3fff */
+    PmcDqmQCtrlReg dqmQCtrl[8]; 	    /* 0x4000 */
+    uint32_t unused9[992];                /* 0x4080-0x4fff */
+    PmcDqmQDataReg dqmQData[8]; 	    /* 0x5000 */
+} Pmc;
+
+#define PMC_BASE 0x80300000
+#define PMC ((volatile Pmc * const) PMC_BASE)
+
+typedef struct Procmon {
+    uint32_t unused00[256];
+    MaestroMisc maestroReg;             /* 0x00400 */
+    uint32_t unused10[32396];             /* 0x005d0-0x1ffff */
+    PmmReg  pmm;                        /* 0x20000 */
+    uint32_t unused11[22];                /* 0x20008-0x2005f */
+    SSBMaster ssbMasterCtrl;            /* 0x20060 */
+    uint32_t unused12[36];                /* 0x20070-0x200ff */
+    PmbBus pmb;                         /* 0x20100 */
+    uint32_t unused13[32576];             /* 0x20300-0x3ffff */
+    uint32_t qsm[128];                    /* 0x40000-0x401ff */
+    uint32_t unused14[65408];             /* 0x40200-0x7ffff */
+    uint32_t dtcm[1024];                  /* 0x80000-0x80fff */
+} Procmon;
+#define PROC_MON_BASE 0x80300000
+#define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
+
+typedef struct PMSSBMasterControl {
+        uint32_t control;
+        uint32_t wr_data;
+        uint32_t rd_data;
+} PMSSBMasterControl;
+
+typedef struct
+{
+    uint32_t  control;
+#define PMC_PMBM_START                      (1 << 31)
+#define PMC_PMBM_TIMEOUT                    (1 << 30)
+#define PMC_PMBM_SLAVE_ERR                  (1 << 29)
+#define PMC_PMBM_BUSY                       (1 << 28)
+#define PMC_PMBM_BUS_SHIFT              (20)
+#define PMC_PMBM_Read                       (0 << 24)
+#define PMC_PMBM_Write                      (1 << 24)
+    uint32_t  wr_data;
+    uint32_t  mutex;
+    uint32_t  rd_data;
+} PMB_keyhole_reg;
+
+typedef struct PMBMaster {
+    uint32_t config;
+#define PMB_NUM_REGS_SHIFT (20)
+#define PMB_NUM_REGS_MASK  (0x3ff)
+    uint32_t arbitger;
+    uint32_t timeout;
+    uint32_t reserved;
+    PMB_keyhole_reg keyhole[4];
+    uint32_t reserved1[44];
+    uint32_t map[64];
+} PMBMaster;
+#define PMB_BASE (0x80200000+0x00120100)
+#define PMB ((volatile PMBMaster * const) PMB_BASE)
+
+
+#define PERF_PHYS_BASE              0xff800000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6756/pmc_addr.h b/arch/arm/include/asm/arch-bcm6756/pmc_addr.h
new file mode 100644
index 0000000000..5d940c83fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/pmc_addr.h
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ 
+*/
+
+#ifndef PMC_ADDR_6756_H__
+#define PMC_ADDR_6756_H__
+
+#define PMB_BUS_ID_SHIFT         12
+
+#define PMB_BUS_PERIPH           1
+#define PMB_ADDR_PERIPH          (16 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH         4
+
+#define PMB_BUS_CRYPTO           0
+#define PMB_ADDR_CRYPTO          (1 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CRYPTO         1
+
+#define PMB_BUS_PVTMON           0
+#define PMB_ADDR_PVTMON          (2 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON         0
+
+#define PMB_BUS_CHIP_CLKRST      0
+#define PMB_ADDR_CHIP_CLKRST     (3 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST    0
+
+#define PMB_BUS_USB31_20         0
+#define PMB_ADDR_USB31_20        (4 | PMB_BUS_USB31_20 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB31_20       4
+
+#define PMB_BUS_WLAN0            0
+#define PMB_ADDR_WLAN0           (5 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0          1
+
+#define PMB_BUS_WLAN0_PHY1       0
+#define PMB_ADDR_WLAN0_PHY1      (6 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY1     1
+
+#define PMB_BUS_WLAN0_PHY2       0
+#define PMB_ADDR_WLAN0_PHY2      (7 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY2     1
+
+#define PMB_BUS_WLAN1            0
+#define PMB_ADDR_WLAN1           (8 | PMB_BUS_WLAN1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1          1
+
+#define PMB_BUS_WLAN1_PHY1       0
+#define PMB_ADDR_WLAN1_PHY1      (9 | PMB_BUS_WLAN1_PHY1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1_PHY1     1
+
+#define PMB_BUS_WLAN1_PHY2       0
+#define PMB_ADDR_WLAN1_PHY2      (10 | PMB_BUS_WLAN1_PHY2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN1_PHY2     1
+
+#define PMB_BUS_MEMC             0
+#define PMB_ADDR_MEMC            (11 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC           1
+
+#define PMB_BUS_SWITCH           0
+#define PMB_ADDR_SWITCH          (12 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SWITCH         5
+
+#define PMB_BUS_PCIE0            1
+#define PMB_ADDR_PCIE0           (17 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0          1
+
+#define PMB_BUS_ORION_CPU0       0
+#define PMB_ADDR_ORION_CPU0      (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0     1
+
+#define PMB_BUS_ORION_CPU1       0
+#define PMB_ADDR_ORION_CPU1      (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1     1
+
+#define PMB_BUS_ORION_CPU2       0
+#define PMB_ADDR_ORION_CPU2      (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU2     1
+
+#define PMB_BUS_ORION_CPU3       0
+#define PMB_ADDR_ORION_CPU3      (35 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU3     1
+
+#define PMB_BUS_ORION_NONCPU     0
+#define PMB_ADDR_ORION_NONCPU    (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU   1
+
+#define PMB_BUS_BIU_PLL          0
+#define PMB_ADDR_BIU_PLL         (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL        0
+
+#define PMB_BUS_BIU_BPCM         0
+#define PMB_ADDR_BIU_BPCM        (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM       1
+
+#define RCAL_0P25UM_HORZ          0
+#define RCAL_0P25UM_VERT          1
+#define RCAL_0P5UM_HORZ           2
+#define RCAL_0P5UM_VERT           3
+#define RCAL_1UM_HORZ             4
+#define RCAL_1UM_VERT             5
+#define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
+#define PMMISC_RMON_VALID_MASK    (0x1<<16)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6756/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm6756/pmc_drv_cfg.h
new file mode 100644
index 0000000000..ac92fbd4c0
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/pmc_drv_cfg.h
@@ -0,0 +1,40 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_3_X
+#define PMC_IMPL_3_2
+
+#define PMC_LOG_IN_DTCM		1
+#define PMC_GETRCAL_SUPPORT 1
+#define PMC_CPUTEMP_SUPPORT 1
+#define PMC_RAM_BOOT 1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm6756/rng.h b/arch/arm/include/asm/arch-bcm6756/rng.h
new file mode 100644
index 0000000000..10420dba20
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6756_RNG_H
+#define _6756_RNG_H
+
+#define RNG_BASE	0xff800b80
+
+typedef struct Rng {
+	uint32_t ctrl0;			/* 0x00 */
+	uint32_t rngSoftReset;		/* 0x04 */
+	uint32_t rbgSoftReset;		/* 0x08 */
+	uint32_t totalBitCnt;		/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;			/* 0x14 */
+	uint32_t intStatus;		/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL	(0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL	(0x1<<2)
+	uint32_t intEn;			/* 0x1c */
+	uint32_t rngFifoData;		/* 0x20 */
+	uint32_t fifoCnt;		/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS	0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS	0x33
+	uint32_t perm;			/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6756/ubus4.h b/arch/arm/include/asm/arch-bcm6756/ubus4.h
new file mode 100644
index 0000000000..2474f39d99
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6756/ubus4.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6756_UBUS4_H
+#define _6756_UBUS4_H
+
+#define MST_PORT_NODE_PER_PHYS_BASE         0x83010000
+#define MST_PORT_NODE_USB_PHYS_BASE         0x83018000
+#define MST_PORT_NODE_CPU_PHYS_BASE         0x83020000
+#define MST_PORT_NODE_PMC_PHYS_BASE         0x83028000 
+#define MST_PORT_NODE_PCIE0_PHYS_BASE       0x83030000
+#define MST_PORT_NODE_SWH_PHYS_BASE         0x83038000
+#define MST_PORT_NODE_MPM_PHYS_BASE         0x83040000
+#define MST_PORT_NODE_SPU_PHYS_BASE         0x83048000
+#define MST_PORT_NODE_WIFI_PHYS_BASE        0x83050000
+#define MST_PORT_NODE_WIFI1_PHYS_BASE       0x83058000
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6846/BPCM.h b/arch/arm/include/asm/arch-bcm6846/BPCM.h
new file mode 100644
index 0000000000..724e999bab
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6846/BPCM.h
@@ -0,0 +1,750 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmbAddr:12;	// [11:00]
+		uint32_t map_rev:4;	// [15:12] always non-zero for AVS3 devices (see CLASSIC_BPCM_ID_REG below)
+		uint32_t island:4;	// [19:16]
+		uint32_t devType:4;	// [23:20] see enum above
+		uint32_t hw_rev:8;	// [31:24]
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;	// [07:00]
+		uint32_t hw_rev:4;	// [11:08]
+		uint32_t map_rev:4;	// [15:12] always zero for classic devices (technically upper 4-bits of hw_rev)
+		uint32_t sw_strap:16;	// [31:16]
+	} Bits;
+	uint32_t Reg32;
+} CLASSIC_BPCM_ID_REG;
+
+// types of PMB devices
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu_reset_n:8;	// 07:00    R/W
+		uint32_t c0l2_reset:1;	// 08:08    R/W
+		uint32_t c1l2_reset:1;	// 09:09    R/W
+		uint32_t reserved0:6;	// 15:10    R/O
+		uint32_t cpu_bpcm_init_on:8;	// 23:16    R/W
+		uint32_t c0l2_bpcm_init_on:1;	// 24:24    R/W
+		uint32_t c1l2_bpcm_init_on:1;	// 25:25    R/W
+		uint32_t ubus_sr:1;	// 26:26    R/W
+		uint32_t cci_sr:1;	// 27:27    R/W
+		uint32_t webcores_sr:1;	// 28:28    R/W
+		uint32_t hw_done:1;	// 29:29    R/O
+		uint32_t sw_done:1;	// 30:30    R/W
+		uint32_t start:1;	// 31:31    R/W
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t reserved0:2;	// 11:10
+		uint32_t ndiv_frac:20;	// 31:12    
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECNDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t reserved0:12;	// 15:04
+		uint32_t mdiv0:8;	// 23:16
+		uint32_t mdiv1:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECPDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv2:8;	// 07:00
+		uint32_t mdiv3:8;	// 15:08
+		uint32_t mdiv4:8;	// 23:16
+		uint32_t mdiv5:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECCH25_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	BPCM_ZONE_N_FREQ_SCALAR_CONTROL freq_scalar_control;
+	uint32_t reserved[4];
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	// BPCM
+	uint32_t control;	// offset 0x10, PMB reg index 4
+	BPCM_SR_CONTROL sr_control;	// offset 0x14, PMB reg index 5
+	uint32_t reserved1[2];	// offset 0x18, PMB reg index 6/7
+	// Client-specific registers
+	uint32_t client_specific[24];	// offset 0x20, PMB reg index 8..31
+	// Zones
+	BPCM_ZONE zones[];	// offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1))
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	CLASSIC_BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x1c, actual offset = 7
+	BPCM_SR_CONTROL sr_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0[3];	// offset = 0x24, actual offset = 9
+	ARM_CONTROL_REG arm_control;	// offset = 0x30, actual offset = 12
+	uint32_t biu_clk_control0;	// offset = 0x34, actual offset = 13
+	uint32_t reserved1[2];	// offset = 0x38, actual offset = 14
+	BPCM_ZONE zones;	// offset = 0x40, actual offset = 16
+} ARM_BPCM_REGS;
+
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	PLL_DECNDIV_REG decndiv;	// offset = 0x44, actual offset = 0x11
+	PLL_DECPDIV_REG decpdiv;	// offset = 0x48, actual offset = 0x12
+	PLL_DECCH25_REG decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_CLASSIC_BPCM_REGS;
+
+#define PLLCLASSICBPCMOffset(reg)  offsetof(PLL_CLASSIC_BPCM_REGS,reg)
+#define PLLCLASSICBPCMRegOffset(reg)   (PLLCLASSICBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04
+	uint32_t reserved0[6];	// offset = 0x08
+	PLL_CTRL_REG resets;	// offset = 0x20
+	PLL_CFG0_REG cfg0;	// offset = 0x24
+	PLL_CFG1_REG cfg1;	// offset = 0x28
+	PLL_NDIV_REG ndiv;	// offset = 0x2c
+	PLL_PDIV_REG pdiv;	// offset = 0x30
+	PLL_LOOP0_REG loop0;	// offset = 0x34
+	uint32_t reserved1;	// offset = 0x38
+	PLL_LOOP1_REG loop1;	// offset = 0x3c
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x40
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x44
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x48
+	PLL_STAT_REG stat;	// offset = 0x4c
+	uint32_t strap;		// offset = 0x50
+	PLL_DECNDIV_REG decndiv;	// offset = 0x54
+	PLL_DECPDIV_REG decpdiv;	// offset = 0x58
+	PLL_DECCH25_REG decch25;	// offset = 0x5c
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved1;	// offset = 0x2c, actual offset = 11
+	uint32_t clkrst_cfg;	// offset = 0x30, actual offset = 12
+	uint32_t clkrst_control;	// offset = 0x34, actual offset = 13
+	uint32_t xtal_control;	// offset = 0x38, actual offset = 14
+	uint32_t clkrst_stat;	// offset = 0x3c, actual offset = 15
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6846/brom.h b/arch/arm/include/asm/arch-bcm6846/brom.h
new file mode 100644
index 0000000000..75a938572d
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6846/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6846_BROM_H
+#define _6846_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6846/cpu.h b/arch/arm/include/asm/arch-bcm6846/cpu.h
new file mode 100644
index 0000000000..cc2fa6efaa
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6846/cpu.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6846_CPU_H
+#define _6846_CPU_H
+
+#define BIUCFG_BASE		0x81060000
+#define CCI400_BASE       0x81090000
+#define BOOTLUT_BASE		0xffff0000
+
+typedef struct CCI400_SlaveIntf {
+#define SNOOP_CTRL_ENABLE_SNOOP            0x1
+    uint32_t snoop_ctrl;        /* 0x0 */
+    uint32_t share_ovr;         /* 0x4 */
+    uint32_t rsvd1[62];         /* 0x8 - 0xff */
+    uint32_t arqos_ovr;         /* 0x100 */
+    uint32_t awqos_ovr;         /* 0x104 */
+    uint32_t rsvd2[2];          /* 0x108 - 0x10f */
+    uint32_t qos_max_ot;        /* 0x110 */
+    uint32_t rsvd3[955];        /* 0x114 - 0xfff */
+}CCI400_SlaveIntf;
+
+
+typedef struct CCI400 {
+    uint32_t ctrl_ovr;        /* 0x0 */
+    uint32_t spec_ctrl;       /* 0x4 */
+#define SECURE_ACCESS_UNSECURE_ENABLE      0x1
+    uint32_t secr_acc;        /* 0x8 */
+    uint32_t status;          /* 0xc */
+    uint32_t impr_err;        /* 0x10 */
+    uint32_t rdvd[59];        /* 0x14 */
+    uint32_t pmu_ctrl;        /* 0x100 */
+    uint32_t rsvd1[959];      /* 0x104 - 0xfff */
+    CCI400_SlaveIntf si[5]; /* 0x1000 - 0x5fff */
+}CCI400;
+
+#define CCI400 ((volatile CCI400 * const) CCI400_BASE)
+
+typedef struct BIUCFG_Access {
+	uint32_t permission;	/* 0x0 */
+	uint32_t sbox;		/* 0x4 */
+	uint32_t cpu_defeature;	/* 0x8 */
+	uint32_t dbg_security;	/* 0xc */
+	uint32_t rsvd1[32];	/* 0x10 - 0x8f */
+	uint64_t violation[2];	/* 0x90 - 0x9f */
+	uint32_t ts_access[2];	/* 0xa0 - 0xa7 */
+	uint32_t rsvd2[22];	/* 0xa8 - 0xff */
+} BIUCFG_Access;
+
+typedef struct BIUCFG_Cluster {
+	uint32_t permission;	/* 0x0 */
+	uint32_t config;	/* 0x4 */
+	uint32_t status;	/* 0x8 */
+	uint32_t control;	/* 0xc */
+	uint32_t cpucfg;	/* 0x10 */
+	uint32_t dbgrom;	/* 0x14 */
+	uint32_t rsvd1[2];	/* 0x18 - 0x1f */
+	uint32_t rvbar_addr[4];	/* 0x20 - 0x2f */
+	uint32_t rsvd2[52];	/* 0x30 - 0xff */
+} BIUCFG_Cluster;
+
+typedef struct BIUCFG_AuxClkCtrl {
+	uint32_t clk_control;	/* 0x0 */
+	uint32_t clk_ramp;	/* 0x4 */
+	uint32_t clk_pattern;	/* 0x8 */
+	uint32_t rsvd;		/* 0xC */
+} BIUCFG_AuxClkCtrl;
+
+typedef struct BIUCFGux {
+	uint32_t permission;	/* 0 */
+	uint32_t rsvd1[3];	/* 0x04 - 0x0c */
+	BIUCFG_AuxClkCtrl cluster_clkctrl[2];	/* 0x10 - 0x2c */
+	uint32_t rsvd2[52];	/* 0x30 - 0xFF */
+} BIUCFG_Aux;
+
+typedef struct BIUCFG {
+	BIUCFG_Access access;	/* 0x0 - 0xff */
+	BIUCFG_Cluster cluster[1];	/* 0x100 - 0x1ff */
+	uint32_t rsvd1[320];	/* 0x200 - 0x6ff */
+	BIUCFG_Aux aux;		/* 0x700 - 0x7ff */
+	uint32_t rsrvd2[512];	/* 0x800 - 0xfff */
+	uint32_t TSO_CNTCR;	/* 0x1000 */
+	uint32_t rsvd2[2047];	/* 0x1004 - 0x2fff */
+} BIUCFG;
+
+#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6846/ddr.h b/arch/arm/include/asm/arch-bcm6846/ddr.h
new file mode 100644
index 0000000000..1feee107ed
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6846/ddr.h
@@ -0,0 +1,493 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6846_DDR_H
+#define _6846_DDR_H
+
+#define MEMC_BASE   0x80180000  /* DDR IO Buf Control */
+
+typedef struct AXIInterface {
+   uint32_t CFG;                  /* 0x00 */
+   uint32_t REP_ARB_MODE;         /* 0x04 */
+   uint32_t QUEUE_CFG;            /* 0x08 */
+   uint32_t ESRCID_CFG;           /* 0x0c */
+   uint32_t SRC_QUEUE_CTRL[8];    /* 0x10 */
+   uint32_t SRC_ID_4_QUEUE_CTRL;  /* 0x30 */
+   uint32_t SCRATCH;              /* 0x34 */
+   uint32_t AXI_DEBUG[2];         /* 0x38 */
+} AXIInterface;
+
+typedef struct EDISEngine {
+   uint32_t REV_ID;             /* 0x00 */
+   uint32_t CTRL_TRIG;          /* 0x04 */
+   uint32_t CTRL_MODE;          /* 0x08 */
+   uint32_t CTRL_SIZE;          /* 0x0c */
+   uint32_t CTRL_ADDR_START;    /* 0x10 */
+   uint32_t CTRL_ADDR_START_EXT;/* 0x14 */
+   uint32_t CTRL_ADDR_END;      /* 0x18 */
+   uint32_t CTRL_ADDR_END_EXT;  /* 0x1c */
+   uint32_t CTRL_WRITE_MASKS;   /* 0x20 */
+   uint32_t CTRL_INT_ENABLES;   /* 0x24 */
+   uint32_t unused0[6];         /* 0x28-0x3f */
+   uint32_t STAT_MAIN;          /* 0x40 */
+   uint32_t STAT_WORDS_WRITTEN; /* 0x44 */
+   uint32_t STAT_WORDS_READ;    /* 0x48 */
+   uint32_t STAT_ERROR_COUNT;   /* 0x4c */
+   uint32_t STAT_ERROR_BITS;    /* 0x50 */
+   uint32_t STAT_ADDR_LAST;     /* 0x54 */
+   uint32_t STAT_ADDR_LAST_EXT; /* 0x58 */
+   uint32_t STAT_CLOCK_CYCLES;  /* 0x5c */
+   uint32_t unused1[7];         /* 0x60-0x7b */
+   uint32_t STAT_DEBUG;         /* 0x7c */
+   uint32_t STAT_DATA_PORT[8];  /* 0x80-0x9c */
+   uint32_t GEN_LFSR_STATE[4];  /* 0xa0-0xac */
+   uint32_t GEN_CLOCK;          /* 0xb0 */
+   uint32_t GEN_PATTERN;        /* 0xb4 */
+   uint32_t unused2[2];         /* 0xb8-0xbf */
+   uint32_t BYTELANE_0_CTRL_LO; /* 0xc0 */
+   uint32_t BYTELANE_0_CTRL_HI; /* 0xc4 */
+   uint32_t BYTELANE_1_CTRL_LO; /* 0xc8 */
+   uint32_t BYTELANE_1_CTRL_HI; /* 0xcc */
+   uint32_t BYTELANE_2_CTRL_LO; /* 0xd0 */
+   uint32_t BYTELANE_2_CTRL_HI; /* 0xd4 */
+   uint32_t BYTELANE_3_CTRL_LO; /* 0xd8 */
+   uint32_t BYTELANE_3_CTRL_HI; /* 0xdc */
+   uint32_t BYTELANE_0_STAT_LO; /* 0xe0 */
+   uint32_t BYTELANE_0_STAT_HI; /* 0xe4 */
+   uint32_t BYTELANE_1_STAT_LO; /* 0xe8 */
+   uint32_t BYTELANE_1_STAT_HI; /* 0xec */
+   uint32_t BYTELANE_2_STAT_LO; /* 0xf0 */
+   uint32_t BYTELANE_2_STAT_HI; /* 0xf4 */
+   uint32_t BYTELANE_3_STAT_LO; /* 0xf8 */
+   uint32_t BYTELANE_3_STAT_HI; /* 0xfc */
+} EDISEngine;
+
+typedef struct RangeCtrl {
+   uint32_t CTRL;                /* 0x00 */
+   uint32_t UBUS0_PORT;          /* 0x04 */
+   uint32_t UBUS0_PORT_UPPER;    /* 0x08 */
+   uint32_t BASE;                /* 0x0c */
+   uint32_t BASE_UPPER;          /* 0x10 */
+   uint32_t SECLEC_EN;           /* 0x14 */
+} RangeCtrl;
+
+typedef struct SecureRangeCheckers {
+   uint32_t LOCK;            /* 0x00 */
+   uint32_t LOG_INFO[3];     /* 0x04 - 0x0c */
+   RangeCtrl RANGE_CTRL[8];/* 0x10 - 0xcf */
+   uint32_t unused[12];      /* 0xd0 - 0xff */
+} SecureRangeCheckers;
+
+typedef struct MEMCControl {
+   uint32_t GLB_VERS;               /* 0x000 */
+   uint32_t GLB_GCFG;               /* 0x004 */
+#define MEMC_GLB_GCFG_DRAM_EN_SHIFT        31
+#define MEMC_GLB_GCFG_DRAM_EN_MASK         (0x1<<MEMC_GLB_GCFG_DRAM_EN_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ_SHIFT      30
+#define MEMC_GLB_GCFG_FORCE_SEQ_MASK       (0x1<<MEMC_GLB_GCFG_FORCE_SEQ_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT     29
+#define MEMC_GLB_GCFG_FORCE_SEQ2_MASK      (1<<MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT)
+#define MEMC_GLB_GCFG_RBF_REORDER_SHIFT    28
+#define MEMC_GLB_GCFG_RBF_REORDER_MASK     (1<<MEMC_GLB_GCFG_RBF_REORDER_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT   24
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_MASK    (0x3<<MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_2X           0x0
+#define MEMC_GLB_GCFG_PHY_DFI_4X           0x1
+#define MEMC_GLB_GCFG_PHY_DFI_8X           0x2
+#define MEMC_GLB_GCFG_DFI_EN_SHIFT         10
+#define MEMC_GLB_GCFG_DFI_EN_MASK          (0x1<<MEMC_GLB_GCFG_DFI_EN_SHIFT)
+#define MEMC_GLB_GCFG_MCLKSRC_SHIFT        9
+#define MEMC_GLB_GCFG_MCLKSRC_MASK         (0x1<<MEMC_GLB_GCFG_MCLKSRC_SHIFT)
+#define MEMC_GLB_GCFG_MEMINITDONE_SHIFT    8
+#define MEMC_GLB_GCFG_MEMINITDONE_MASK     (0x1<<MEMC_GLB_GCFG_MEMINITDONE_SHIFT)
+   uint32_t GLB_MRQ_CFG;            /* 0x008 */
+   uint32_t unused0;                /* 0x00c */
+   uint32_t GLB_FSBL_STATE;         /* 0x010 */
+#define MEMC_GLB_FSBL_DRAM_SIZE_SHIFT      0
+#define MEMC_GLB_FSBL_DRAM_SIZE_MASK       (0xf << MEMC_GLB_FSBL_DRAM_SIZE_SHIFT)
+   uint32_t unused1[3];             /* 0x014 - 0x01f */
+
+   uint32_t SRAM_REMAP_CTRL;        /* 0x020 */
+   uint32_t SRAM_REMAP_CTRL_UPPER;  /* 0x024 */
+   uint32_t SRAM_REMAP_INIT;        /* 0x028 */
+   uint32_t SRAM_REMAP_LOG_INFO_0;  /* 0x02c */
+   uint32_t SRAM_REMAP_LOG_INFO_1;  /* 0x030 */
+   uint32_t SRAM_REMAP_LOG_INFO_2;  /* 0x034 */
+   uint32_t unused2[2];             /* 0x038-0x03f */
+
+   uint32_t RBF_REORDER_0_CFG[16];  /* 0x040 - 0x07f */
+
+   uint32_t INTR2_CPU_STATUS;       /* 0x080 */
+   uint32_t INTR2_CPU_SET;          /* 0x084 */
+   uint32_t INTR2_CPU_CLEAR;        /* 0x088 */
+   uint32_t INTR2_CPU_MASK_STATUS;  /* 0x08c */
+   uint32_t INTR2_CPU_MASK_SET;     /* 0x090 */
+   uint32_t INTR2_CPU_MASK_CLEAR;   /* 0x094 */
+   uint32_t unused3[26];            /* 0x098-0x0ff */
+
+   uint32_t CHN_CFG_CNFG;           /* 0x100 */
+#define MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT            16
+#define MEMC_CHN_CFG_CNFG_CS_MODE_MASK             (0x3 << MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT)
+   uint32_t CHN_CFG_CSST;           /* 0x104 */
+   uint32_t unused4[2];             /* 0x108-0x10f */
+   uint32_t CHN_CFG_ROW00_0;        /* 0x110 */
+   uint32_t CHN_CFG_ROW00_1;        /* 0x114 */
+   uint32_t CHN_CFG_ROW01_0;        /* 0x118 */
+   uint32_t CHN_CFG_ROW01_1;        /* 0x11c */
+   uint32_t CHN_CFG_ROW02_0;        /* 0x120 */
+   uint32_t CHN_CFG_COL00_0;        /* 0x124 */
+   uint32_t CHN_CFG_COL00_1;        /* 0x128 */
+   uint32_t CHN_CFG_COL01_0;        /* 0x12c */
+   uint32_t CHN_CFG_COL01_1;        /* 0x130 */
+   uint32_t CHN_CFG_BNK10;          /* 0x134 */
+   uint32_t CHN_CFG_BG0;            /* 0x138 */
+   uint32_t unused5;                /* 0x13c */
+   uint32_t CHN_CFG_DRAM_SZ_CHK;    /* 0x140 */
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT                          4
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_MASK                           (0xf<<MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT)
+   uint32_t CHN_CFG_DIAG_SEL;       /* 0x144 */
+   uint32_t unused6[46];            /* 0x148-0x1ff */
+
+   uint32_t CHN_TIM_DCMD;           /* 0x200 */
+   uint32_t CHN_TIM_DMODE_0;        /* 0x204 */
+   uint32_t CHN_TIM_DMODE_2;        /* 0x208 */
+   uint32_t CHN_TIM_CLKS;           /* 0x20c */
+#define MEMC_CHN_TIM_CLKS_REF_RATE_SHIFT          8
+#define MEMC_CHN_TIM_CLKS_REF_DISABLE_SHIFT       31
+   uint32_t CHN_TIM_ODT;            /* 0x210 */
+   uint32_t CHN_TIM_TIM1_0;         /* 0x214 */
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tWL [31:24] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_MASK                            0xff000000
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_SHIFT                           24
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_DEFAULT                         0x00000004
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRP [23:16] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_MASK                            0x00ff0000
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_SHIFT                           16
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_DEFAULT                         0x00000006
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tCL [15:08] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_MASK                            0x0000ff00
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_SHIFT                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_DEFAULT                         0x00000005
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRCD [07:00] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_MASK                           0x000000ff
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_ALIGN                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_BITS                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_SHIFT                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_DEFAULT                        0x00000006
+
+   uint32_t CHN_TIM_TIM1_1;         /* 0x218 */
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_L [31:24] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_S [23:16] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_L [15:08] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_MASK                         0x0000ff00
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_SHIFT                        8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_S [07:00] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_MASK                         0x000000ff
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_SHIFT                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_DEFAULT                      0x00000002
+
+   uint32_t CHN_TIM_TIM1_2;         /* 0x21c */
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tFAW [31:24] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_MASK                           0xff000000
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_SHIFT                          24
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_DEFAULT                        0x00000000
+/* MC_CHN_TIM :: TIM1_2 :: reserved0 [23:16] */
+#define MC_CHN_TIM_TIM1_2_reserved0_MASK                           0x00ff0000
+#define MC_CHN_TIM_TIM1_2_reserved0_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_reserved0_BITS                           8
+#define MC_CHN_TIM_TIM1_2_reserved0_SHIFT                          16
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRTP [15:08] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_MASK                           0x0000ff00
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_SHIFT                          8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_DEFAULT                        0x00000002
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRC [07:00] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_ALIGN                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_BITS                            8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_SHIFT                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_DEFAULT                         0x00000011
+
+   uint32_t CHN_TIM_TIM1_3;         /* 0x220 */
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_L [31:24] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_S [23:16] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: reserved_for_padding0 [15:12] */
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_MASK               0x0000f000
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_ALIGN              0
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_BITS               4
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_SHIFT              12
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_L [11:08] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_MASK                          0x00000f00
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_BITS                          4
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_SHIFT                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_DEFAULT                       0x00000004
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_S [07:00] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_MASK                          0x000000ff
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_BITS                          8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_SHIFT                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_DEFAULT                       0x00000004
+
+   uint32_t CHN_TIM_TIM2;          /* 0x224 */
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2R [31:30] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_MASK                             0xc0000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_BITS                             2
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_SHIFT                            30
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2W [29:27] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_MASK                             0x38000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_SHIFT                            27
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2R [26:24] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_MASK                             0x07000000
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_SHIFT                            24
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: reserved_for_padding0 [23:22] */
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_MASK                 0x00c00000
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_ALIGN                0
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_BITS                 2
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_SHIFT                22
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2W [21:18] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_MASK                             0x003c0000
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_BITS                             4
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_SHIFT                            18
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: reserved1 [17:16] */
+#define MC_CHN_TIM_TIM2_reserved1_MASK                             0x00030000
+#define MC_CHN_TIM_TIM2_reserved1_ALIGN                            0
+#define MC_CHN_TIM_TIM2_reserved1_BITS                             2
+#define MC_CHN_TIM_TIM2_reserved1_SHIFT                            16
+/* MC_CHN_TIM :: TIM2 :: TIM2_tAL [15:12] */
+#define MC_CHN_TIM_TIM2_TIM2_tAL_MASK                              0x0000f000
+#define MC_CHN_TIM_TIM2_TIM2_tAL_ALIGN                             0
+#define MC_CHN_TIM_TIM2_TIM2_tAL_BITS                              4
+#define MC_CHN_TIM_TIM2_TIM2_tAL_SHIFT                             12
+#define MC_CHN_TIM_TIM2_TIM2_tAL_DEFAULT                           0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tRFC [11:00] */
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_MASK                             0x00000fff
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_BITS                             12
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_SHIFT                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_DEFAULT                          0x00000014
+
+   uint32_t unused7[2];            /* 0x228 - 0x22f */
+   uint32_t CHN_TIM_PHY_ST;         /* 0x230 */
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP       0x1
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_HW_RESET       0x2
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_SW_RESET       0x4
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_READY          0x10
+   uint32_t CHN_TIM_DRAM_CFG;       /* 0x234 */
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT           12
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_MASK            (0x1<<MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT     10
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_MASK      (0x1<<MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT      0
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_MASK       (0xf<<MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT)
+#define MC_DRAM_CFG_DDR3                          0x1
+   uint32_t CHN_TIM_STAT;           /* 0x238 */
+   uint32_t CHN_TIM_PERF;           /* 0x23c */
+
+   uint32_t CHN_TIM_PKM_CFG;        /* 0x240 */
+   uint32_t CHN_TIM_AB4_CFG;        /* 0x244 */
+   uint32_t unused8[2];             /* 0x248 */
+   uint32_t CHN_TIM_AB4_ACT_PRI;    /* 0x250 */
+   uint32_t CHN_TIM_AB4_PRI_OPEN;   /* 0x254 */
+   uint32_t CHN_TIM_AB4_PRI_CLOSED; /* 0x258 */
+   uint32_t CHN_TIM_AUTO_SELF_REF;  /* 0x25c */
+   uint32_t CHN_TIM_AUTO_ZQCS;      /* 0x260 */
+   uint32_t CHN_TIM_TIM3;           /* 0x264 */
+   uint32_t unused9[38];            /* 0x268-0x2ff */
+
+   uint32_t ARB_CFG;                /* 0x300 */
+   uint32_t ARB_QUE_DIS[2];         /* 0x304 */
+   uint32_t unused10;               /* 0x30c */
+   uint32_t ARB_BKT_CFG_CPU_WR[4];  /* 0x310 */
+   uint32_t ARB_BKT_CFG_CPU_RD[4];  /* 0x320 */
+   uint32_t ARB_BKT_CFG_CPQ_RD[4];  /* 0x330 */
+   uint32_t ARB_BKT_CFG_CPQ_WR[4];  /* 0x340 */
+   uint32_t ARB_BKT_CFG_EDIS[4];    /* 0x350 */
+   uint32_t unused11[32];           /* 0x360 */
+   uint32_t ARB_QUEUE_PRI[3];       /* 0x3e0 */
+   uint32_t ARB_WRR_QUEUE_PRI;      /* 0x3ec */
+   uint32_t ARB_RATE_OK_WEIGHT[2];  /* 0x3f0 */
+   uint32_t ARB_RATE_FAIL_WEIGHT[2]; /* 0x3f4 */
+
+   uint32_t unused12[48];           /* 0x400 */
+   AXIInterface AXIWIF;           /* 0x4c0 */
+
+   uint32_t unused13[192];          /* 0x500-0x7ff */
+
+   EDISEngine EDIS_0;             /* 0x800 */
+   uint32_t unused14[64];           /* 0x900 */
+
+   uint32_t STATS_CTRL;             /* 0xa00 */
+   uint32_t STATS_TIMER_CFG;        /* 0xa04 */
+   uint32_t STATS_TIMER_COUNT;      /* 0xa08 */
+   uint32_t STATS_TOTAL_SLICE;      /* 0xa0c */
+   uint32_t STATS_TOTAL_PACKET;     /* 0xa10 */
+   uint32_t STATS_TOTAL_READ_SLICE; /* 0xa14 */
+   uint32_t STATS_TOTAL_READ_PACKET;/* 0xa18 */
+   uint32_t STATS_TOTAL_LATENCY;    /* 0xa1c */
+   uint32_t STAT_MAX_LATENCY;       /* 0xa20 */
+   uint32_t STATS_SLICE_REORDER;    /* 0xa24 */
+   uint32_t STATS_TOTAL_DDR_CMD;    /* 0xa28 */
+   uint32_t STATS_TOTAL_DDR_ACT;    /* 0xa2c */
+   uint32_t STATS_TOTAL_DDR_RDWR;   /* 0xa30 */
+   uint32_t STATS_TOTAL_DDR_WRRD;   /* 0xa34 */
+   uint32_t STATS_TOTAL_MRQ_CHN_FULL; /* 0xa38 */
+   uint32_t STATS_TOTAL_SELF_REF;   /* 0xa3c */
+   uint32_t STATS_ARB_GRANT_MATCH0; /* 0xa40 */
+   uint32_t STATS_TOTAL_QUEUE_FULL; /* 0xa44 */
+   uint32_t STATS_TOTAL_ARB_GRANT;  /* 0xa48 */
+   uint32_t STATS_TOTAL_RATE_OK_GRANT; /* 0xa4c*/
+   uint32_t STATS_FILTER_CFG_0;     /* 0xa50 */
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT  25
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_MASK   (0x1<<MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_EN     0x02000000
+#define MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT     16
+#define MEMC_STATS_FILTER_CFG_SRC_ID_MASK      (0x1FF<<MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_SHIFT 0
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_MASK  0x0000FFFF
+#define MEMC_STATS_FILTER_CFG_INTF_AXI         0x00000001
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS0       0x00000002
+#define MEMC_STATS_FILTER_CFG_INTF_UNUSED      0x00000008
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS        MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS0       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_MCP         MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+   uint32_t STATS_PROG0_SLICE;      /* 0xa54 */
+   uint32_t STATS_PROG0_PACKET;     /* 0xa58 */
+   uint32_t STATS_PROG0_READ_SLICE; /* 0xa5c */
+   uint32_t STATS_PROG0_READ_PACKET; /* 0xa60 */
+   uint32_t STATS_PROG0_LATENCY;    /* 0xa64 */
+   uint32_t STATS_PROG0_MAX_LETANCY; /* 0xa68 */
+
+   // uint32_t unused15[37];            /* 0xa6c */
+   uint32_t unused15_0;              /* 0xa6c */
+   uint32_t STATS_FILTER_CFG_1;     /* 0xa70 */
+   uint32_t STATS_PROG1_SLICE;      /* 0xa74 */
+   uint32_t STATS_PROG1_PACKET;     /* 0xa78 */
+   uint32_t STATS_PROG1_READ_SLICE; /* 0xa7c */
+   uint32_t STATS_PROG1_READ_PACKET;/* 0xa80 */
+   uint32_t STATS_PROG1_LATENCY;    /* 0xa84 */
+   uint32_t unused15_1[2];          /* 0xa88 - 0xa8c */
+   uint32_t STATS_FILTER_CFG_2;     /* 0xa90 */
+   uint32_t STATS_PROG2_SLICE;      /* 0xa94 */
+   uint32_t STATS_PROG2_PACKET;     /* 0xa98 */
+   uint32_t STATS_PROG2_READ_SLICE; /* 0xa9c */
+   uint32_t STATS_PROG2_READ_PACKET;/* 0xaa0 */
+   uint32_t STATS_PROG2_LATENCY;    /* 0xaa4 */
+   uint32_t unused15_2[2];          /* 0xaa8 - 0xaac */
+   uint32_t STATS_FILTER_CFG_3;     /* 0xab0 */
+   uint32_t STATS_PROG3_SLICE;      /* 0xab4 */
+   uint32_t STATS_PROG3_PACKET;     /* 0xab8 */
+   uint32_t STATS_PROG3_READ_SLICE; /* 0xabc */
+   uint32_t STATS_PROG3_READ_PACKET;/* 0xac0 */
+   uint32_t STATS_PROG3_LATENCY;    /* 0xac4 */
+   uint32_t unused15_3[2];            /* 0xac8 - 0xacc */
+   uint32_t STATS_AXI_BLOCK_CPU_RD; /* 0xad0 */
+   uint32_t STATS_AXI_BLOCK_CPQ_RD; /* 0xad4 */
+   uint32_t unused15_4[10];           /* 0xad8 - 0xaff */
+
+   uint32_t CAP_CAPTURE_CFG;        /* 0xb00 */
+   uint32_t CAP_TRIGGER_ADDR;       /* 0xb04 */
+   uint32_t CAP_READ_CTRL;          /* 0xb08 */
+   uint32_t unused16;               /* 0xb0c */
+   uint32_t CAP_CAPTURE_MATCH0;     /* 0xb10 */
+   uint32_t CAP_CAPTURE_MATCH1;     /* 0xb14 */
+   uint32_t CAP_CAPTURE_MATCH2;     /* 0xb18 */
+   uint32_t unused17;               /* 0xb1c */
+   uint32_t CAP_CAPTURE_MASK0;      /* 0xb20 */
+   uint32_t CAP_CAPTURE_MASK1;      /* 0xb24 */
+   uint32_t CAP_CAPTURE_MASK2;      /* 0xb28 */
+   uint32_t unused18;               /* 0xb2c */
+   uint32_t CAP_TRIGGER_MATCH0;     /* 0xb30 */
+   uint32_t CAP_TRIGGER_MATCH1;     /* 0xb34 */
+   uint32_t CAP_TRIGGER_MATCH2;     /* 0xb38 */
+   uint32_t unused19;               /* 0xb3c */
+   uint32_t CAP_TRIGGER_MASK0;      /* 0xb40 */
+   uint32_t CAP_TRIGGER_MASK1;      /* 0xb44 */
+   uint32_t CAP_TRIGGER_MASK2;      /* 0xb48 */
+   uint32_t unused20;               /* 0xb4c */
+   uint32_t CAP_READ_DATA[8];       /* 0xb50-0xb6f */
+   uint32_t unused21[164];          /* 0xb70-0xdff */
+
+   uint32_t SEC_INTR2_CPU_STATUS;   /* 0xe00 */
+   uint32_t SEC_INTR2_CPU_SET;      /* 0xe04 */
+   uint32_t SEC_INTR2_CPU_CLEAR;    /* 0xe08 */
+   uint32_t SEC_INTR2_CPU_MASK_STATUS;  /* 0xe0c */
+   uint32_t SEC_INTR2_CPU_MASK_SET;  /* 0xe10 */
+   uint32_t SEC_INTR2_CPU_MASK_CLEAR;   /* 0xe14 */
+   uint32_t unused22[58];              /* 0xe18-0xeff */
+
+   uint32_t UBUSIF0_PERMCTL;          /* 0xf00 */
+   uint32_t UBUSIF1_PERMCTL;          /* 0xf04 */
+   uint32_t SRAM_REMAP_PERMCTL;       /* 0xf08 */
+   uint32_t AXIWIF_PERMCTL;           /* 0xf0c */
+   uint32_t CHNCFG_PERMCTL;           /* 0xf10 */
+   uint32_t MCCAP_PERMCTL;            /* 0xf14 */
+   uint32_t SCRAM_PERMCTL;            /* 0xf18 */
+   uint32_t RNG_PERMCTL;              /* 0xf1c */
+   uint32_t RNGCHK_PERMCTL;           /* 0xf20 */
+   uint32_t unused23[567];            /* 0xf24-0x17ff */
+
+   SecureRangeCheckers SEC_RANGE_CHK; /* 0x1800-0x18ff */
+   uint32_t unused24[31168];            /* 0x1900-0x200000 */
+
+   uint32_t PhyControl[256];           /* 0x2000 */
+   uint32_t PhyByteLane0Control[128];  /* 0x2400 */
+   uint32_t PhyByteLane1Control[128];  /* 0x2600 */
+   uint32_t PhyByteLane2Control[128];  /* 0x2800 */
+   uint32_t PhyByteLane3Control[128];  /* 0x2a00 */
+} MEMCControl;
+
+
+#define MEMC ((volatile MEMCControl * const) MEMC_BASE)
+
+
+#endif /* _6846_DDR_H */
+
diff --git a/arch/arm/include/asm/arch-bcm6846/misc.h b/arch/arm/include/asm/arch-bcm6846/misc.h
new file mode 100644
index 0000000000..dd3b79b69e
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6846/misc.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6846_MISC_H
+#define _6846_MISC_H
+
+/*
+ * Gpio Controller
+ */
+typedef struct GpioControl {
+        uint32_t GPIODir[8];             /* 0x00-0x1c */
+        uint32_t GPIOio[8];              /* 0x20-0x3c */
+        uint32_t PadCtrl;                 /* 0x40 */
+        uint32_t SpiSlaveCfg;             /* 0x44 */
+        uint32_t TestControl;             /* 0x48 */
+        uint32_t TestPortBlockEnMSB;      /* 0x4c */
+        uint32_t TestPortBlockEnLSB;      /* 0x50 */
+        uint32_t TestPortBlockDataMSB;    /* 0x54 */
+        uint32_t TestPortBlockDataLSB;    /* 0x58 */
+#define PINMUX_DATA_SHIFT       12
+#define PINMUX_0                0
+#define PINMUX_1                1
+#define PINMUX_2                2
+#define PINMUX_3                3
+#define PINMUX_4                4
+#define PINMUX_5                5
+#define PINMUX_6                6
+#define PINMUX_7                7
+#define PAD_CTRL_SHIFT          12
+#define PAD_CTRL_MASK           (0x3f<<PAD_CTRL_SHIFT)
+#define PAD_SEL_SHIFT           12
+#define PAD_AMP_SHIFT           15
+#define PAD_IND_SHIFT           16
+#define PAD_GMII_SHIFT          17
+       uint32_t TestPortCmd;             /* 0x5c */
+#define LOAD_MUX_REG_CMD        0x21
+#define LOAD_PAD_CTRL_CMD       0x22
+        uint32_t DiagReadBack;            /* 0x60 */
+        uint32_t DiagReadBackHi;          /* 0x64 */
+        uint32_t GeneralPurpose;          /* 0x68 */
+        uint32_t spare[3];
+} GpioControl;
+
+#define GPIO_BASE          0xff800500
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+/*
+ ** Misc Register Set Definitions.
+ */
+
+typedef struct Misc {
+    uint32_t  miscStrapBus;                       /* 0x00 */
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           5
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOTROM_BOOT_N           (0x1 << 11)
+
+#define MISC_STRAP_BUS_PCIE_SATA_MASK		    (1 << 3)  /* 1-PCI  0-SATA */
+#define MISC_STRAP_BUS_B53_NO_BOOT              (1 << 12) /* 1-PMC boot A53, 0-A53 boots at POR */
+#define MISC_STRAP_DDR_DENSITY_SHIFT            18
+#define MISC_STRAP_DDR_DENSITY_MASK             (3 << MISC_STRAP_DDR_DENSITY_SHIFT) /* 0=1Gb, 1=2Gb, 2=8Gb, 3=4Gb */
+#define MISC_STRAP_BUS_PMC_BOOT_AVS             (1 << 20) /* 1 = PMC run AVS */
+#define MISC_STRAP_BUS_PMC_BOOT_FLASH_N         (1 << 21) /* 1 = PMC boot from rom */
+#define MISC_STRAP_DDR_FREQ_SHIFT               27
+#define MISC_STRAP_DDR_FREQ_MASK                (1 << MISC_STRAP_DDR_FREQ_SHIFT) /* 1-800MHz, 0-533MHz */
+#define MISC_STRAP_BUS_PCIE_SINGLE_LANES_SHIFT  29
+#define MISC_STRAP_BUS_PCIE_SINGLE_LANES        (1 << MISC_STRAP_BUS_PCIE_SINGLE_LANES_SHIFT) /* 1-Single Lanes  0-Dual Lanes */
+#define MISC_STRAP_ENABLE_INT_1p8V              (1 << 1)
+
+    uint32_t  miscStrapOverride;                  /* 0x04 */
+    uint32_t  miscMaskUBUSErr;                    /* 0x08 */
+    uint32_t  miscPeriphCtrl;                     /* 0x0c */
+    uint32_t  miscSPImasterCtrl;                  /* 0x10 */
+    uint32_t  miscDierevid;                       /* 0x14 */
+    uint32_t  miscPeriphMiscCtrl;                 /* 0x18 */
+    uint32_t  miscPeriphMiscStat;                 /* 0x1c */
+    uint32_t  miscMbox0_data;                     /* 0x20 */
+    uint32_t  miscMbox1_data;                     /* 0x24 */
+    uint32_t  miscMbox2_data;                     /* 0x28 */
+    uint32_t  miscMbox3_data;                     /* 0x2c */
+    uint32_t  miscMbox_ctrl;                      /* 0x30 */
+    uint32_t  miscSoftResetB;                     /* 0x34 */
+    uint32_t  reserved0;                          /* 0x38 */
+    uint32_t  miscSWdebugNW[2];                   /* 0x3c */
+    uint32_t  miscWDresetCtrl;                    /* 0x44 */
+} Misc;
+
+#define MISC_BASE          0xff802600
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6846/otp.h b/arch/arm/include/asm/arch-bcm6846/otp.h
new file mode 100644
index 0000000000..d7eeb90236
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6846/otp.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _6846_OTP_H
+#define _6846_OTP_H
+
+#define JTAG_OTP_BASE    0xff802800
+
+/* row 8 */
+#define OTP_CPU_CORE_CFG_ROW            	8
+#define OTP_CPU_CORE_CFG_SHIFT          	28
+#define OTP_CPU_CORE_CFG_MASK           	0x1
+
+/* row 9 */
+#define OTP_CPU_CLOCK_FREQ_ROW          	9
+#define OTP_CPU_CLOCK_FREQ_SHIFT        	0
+#define OTP_CPU_CLOCK_FREQ_MASK         	0x7
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          7
+
+/* row 23 */
+#define OTP_CUST_MFG_MRKTID_ROW                 23
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_CPU_CLOCK_FREQ, OTP_CPU_CLOCK_FREQ_ROW, OTP_CPU_CLOCK_FREQ_MASK, OTP_CPU_CLOCK_FREQ_SHIFT, 1},				\
+	{OTP_MAP_CPU_CORE_CFG, OTP_CPU_CORE_CFG_ROW, OTP_CPU_CORE_CFG_MASK, OTP_CPU_CORE_CFG_SHIFT, 1},				\
+	}
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6846/pmc.h b/arch/arm/include/asm/arch-bcm6846/pmc.h
new file mode 100644
index 0000000000..51db3a880f
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6846/pmc.h
@@ -0,0 +1,350 @@
+#ifndef PMC_H
+#define PMC_H 
+
+/*
+ * Power Management Control
+ */
+typedef struct PmcCtrlReg {
+    uint32_t gpTmr0Ctl;           /* 0x018 */
+    uint32_t gpTmr0Cnt;           /* 0x01c */
+    uint32_t gpTmr1Ctl;           /* 0x020 */
+    uint32_t gpTmr1Cnt;           /* 0x024 */
+    uint32_t hostMboxIn;          /* 0x028 */
+    uint32_t hostMboxOut;         /* 0x02c */
+    uint32_t reserved[4];         /* 0x030 */
+    uint32_t dmaCtrl;             /* 0x040 */
+    uint32_t dmaStatus;           /* 0x044 */
+    uint32_t dma0_3FifoStatus;    /* 0x048 */
+    uint32_t reserved1[4];	    /* 0x04c */
+    uint32_t diagControl;         /* 0x05c */
+    uint32_t diagHigh;            /* 0x060 */
+    uint32_t diagLow;             /* 0x064 */
+    uint32_t reserved8;           /* 0x068 */
+    uint32_t addr1WndwMask;       /* 0x06c */
+    uint32_t addr1WndwBaseIn;     /* 0x070 */
+    uint32_t addr1WndwBaseOut;    /* 0x074 */
+    uint32_t addr2WndwMask;       /* 0x078 */
+    uint32_t addr2WndwBaseIn;     /* 0x07c */
+    uint32_t addr2WndwBaseOut;    /* 0x080 */
+    uint32_t scratch;             /* 0x084 */
+    uint32_t reserved9;           /* 0x088 */
+    uint32_t softResets;          /* 0x08c */
+    uint32_t reserved2;           /* 0x090 */
+    uint32_t m4keCoreStatus;      /* 0x094 */
+    uint32_t reserved3;           /* 0x098 */
+    uint32_t ubSlaveTimeout;      /* 0x09c */
+    uint32_t diagEn;              /* 0x0a0 */
+    uint32_t devTimeout;          /* 0x0a4 */
+    uint32_t ubusErrorOutMask;    /* 0x0a8 */
+    uint32_t diagCaptStopMask;    /* 0x0ac */
+    uint32_t revId;               /* 0x0b0 */
+    uint32_t gpTmr2Ctl;           /* 0x0b4 */
+    uint32_t gpTmr2Cnt;           /* 0x0b8 */
+    uint32_t reserved4[2];        /* 0x0bc */
+    uint32_t diagCtrl;            /* 0x0c4 */
+    uint32_t diagStat;            /* 0x0c8 */
+    uint32_t diagMask;            /* 0x0cc */
+    uint32_t diagRslt;            /* 0x0d0 */
+    uint32_t diagCmp;             /* 0x0d4 */
+    uint32_t diagCapt;            /* 0x0d8 */    
+    uint32_t diagCnt;             /* 0x0dc */
+    uint32_t diagEdgeCnt;         /* 0x0e0 */
+    uint32_t reserved5[4];	    /* 0x0e4 */
+    uint32_t smisc_bus_config;    /* 0x0f4 */
+    uint32_t lfsr;                /* 0x0f8 */
+    uint32_t dqm_pac_lock;        /* 0x0fc */
+    uint32_t l1_irq_4ke_mask;     /* 0x100 */
+    uint32_t l1_irq_4ke_status;   /* 0x104 */
+    uint32_t l1_irq_mips_mask;    /* 0x108 */
+    uint32_t l1_irq_mips_status;  /* 0x10c */
+    uint32_t l1_irq_mips1_mask;   /* 0x110 */
+    uint32_t reserved6[3];        /* 0x114 */
+    uint32_t l2_irq_gp_mask;      /* 0x120 */
+    uint32_t l2_irq_gp_status;    /* 0x124 */
+    uint32_t l2_irq_gp_set;       /* 0x128 */
+    uint32_t reserved7;           /* 0x12c */
+    uint32_t gp_in_irq_mask;      /* 0x130 */
+    uint32_t gp_in_irq_status;    /* 0x134 */
+    uint32_t gp_in_irq_set;       /* 0x138 */
+    uint32_t gp_in_irq_sense;     /* 0x13c */
+    uint32_t gp_in;               /* 0x140 */
+    uint32_t gp_out;              /* 0x144 */
+} PmcCtrlReg;
+
+typedef struct PmcDmaReg {
+	/* 0x00 */
+	uint32_t src;
+	uint32_t dest;
+	uint32_t cmdList;
+	uint32_t lenCtl;
+	/* 0x10 */
+	uint32_t rsltSrc;
+	uint32_t rsltDest;
+	uint32_t rsltHcs;
+	uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+	/* 0x00 */
+	uint32_t bufSize;
+	uint32_t bufBase;
+	uint32_t idx2ptrIdx;
+	uint32_t idx2ptrPtr;
+	/* 0x10 */
+	uint32_t unused[2];
+	uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+	uint32_t freqScalarCtrl; /* 0x3c */
+	uint32_t freqScalarMask; /* 0x40 */
+} PmcPerfPowReg;
+
+typedef struct PmcDQMPac {
+    uint32_t dqmPac[32];
+} PmcDQMPac;
+
+typedef struct PmcDQMReg {
+	uint32_t cfg;                     /* 0x1c00 */
+	uint32_t _4keLowWtmkIrqMask;      /* 0x1c04 */
+	uint32_t mipsLowWtmkIrqMask;      /* 0x1c08 */
+	uint32_t lowWtmkIrqMask;          /* 0x1c0c */
+	uint32_t _4keNotEmptyIrqMask;     /* 0x1c10 */
+	uint32_t mipsNotEmptyIrqMask;     /* 0x1c14 */
+	uint32_t notEmptyIrqSts;          /* 0x1c18 */
+	uint32_t queueRst;                /* 0x1c1c */
+	uint32_t notEmptySts;             /* 0x1c20 */
+	uint32_t nextAvailMask;           /* 0x1c24 */
+	uint32_t nextAvailQueue;          /* 0x1c28 */
+	uint32_t mips1LowWtmkIrqMask;     /* 0x1c2c */
+	uint32_t mips1NotEmptyIrqMask;    /* 0x1c30 */
+	uint32_t autoSrcPidInsert;        /* 0x1c34 */
+    uint32_t timerIrqStatus;          /* 0x1c38 */
+    uint32_t timerStatus;             /* 0x1c3c */
+    uint32_t _4keTimerIrqMask;        /* 0x1c40 */
+    uint32_t mipsTimerIrqMask;        /* 0x1c44 */
+    uint32_t mips1TimerIrqMask;       /* 0x1c48 */
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+	uint32_t cntr[10];
+	uint32_t unused[6];	/* 0x28-0x3f */
+	uint32_t cntrIrqMask;
+	uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+	uint32_t size;
+	uint32_t cfga;
+	uint32_t cfgb;
+	uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+	uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+	uint32_t qNumFull[32];
+	uint32_t qNumEmpty[32];
+	uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+typedef struct PMSSBMasterControl {
+    uint32_t control;     /* 0x0060 */
+    uint32_t wr_data;      /* 0x0064 */
+    uint32_t rd_data;      /* 0x0068 */
+    uint32_t status;      /* 0x006c */
+} PMSSBMasterControl;
+
+#define SWR_FIRST 0
+#define SWR_LAST 4
+#define SWR_READ_CMD_P 0xB800
+#define SWR_WR_CMD_P   0xB400
+#define SWR_EN         0x1000
+#define SET_ADDR(ps, reg)  (((ps) << 5 | ((reg) & 0x1f)) & 0x2ff)
+
+#define SR_TEST(x)  {\
+                     int num;\
+                     for(num=1000;(((PROCMON->SSBMaster.control) & 0x8000) && (num > 0)) ; num--) ;\
+                         if(!num) \
+                         {\
+                             printf("Error num %d timeout num = %d!!!", (x),  num);\
+                         }\
+}
+
+typedef struct PmmReg {
+    uint32_t memPowerCtrl;            /* 0x0000 */
+    uint32_t regSecurityConfig;       /* 0x0004 */
+} PmmReg;
+
+typedef struct keyholeReg {
+    uint32_t ctrlSts;
+    uint32_t wrData;
+    uint32_t mutex;
+    uint32_t rdData;
+} keyholeReg;
+
+typedef struct PmbBus {
+    uint32_t config;          /* 0x0100 */
+    uint32_t arbiter;         /* 0x0104 */
+    uint32_t timeout;         /* 0x0108 */
+    uint32_t unused1;         /* 0x010c */
+    keyholeReg keyhole[4];  /* 0x0110-0x014f */
+    uint32_t unused2[44];     /* 0x0150-0x01ff */
+    uint32_t map[64];         /* 0x0200-0x02ff */ 
+}PmbBus;
+
+typedef struct  CoreCtrl {
+    uint32_t  coreEnable;         /* 0x0400 */
+    uint32_t  autoresetControl;   /* 0x0404 */
+    uint32_t  coreIdle;           /* 0x0408 */
+    uint32_t  coreResetCause;     /* 0x040c */
+    uint32_t  memPwrDownCtrl0;    /* 0x0410 */
+    uint32_t  memPwrDownSts0;     /* 0x0414 */
+    uint32_t  memPwrDownCtrl1;    /* 0x0418 */
+    uint32_t  memPwrDownSts1;     /* 0x041c */
+    uint32_t  sysFlg0Status;      /* 0x0420 */
+    uint32_t  sysFlg0Set;         /* 0x0424 */
+    uint32_t  sysFlg0Clear;       /* 0x0428 */
+    uint32_t  unused1;            /* 0x042c */
+    uint32_t  usrFlg0Status;      /* 0x0430 */
+    uint32_t  usrFlg0Set;         /* 0x0434 */
+    uint32_t  usrFlg0Clear;       /* 0x0438 */
+    uint32_t  unused2;            /* 0x043c */
+    uint32_t  subsystemRev;       /* 0x0440 */
+    uint32_t  resetVector;        /* 0x0444 */
+} CoreCtrl;
+
+typedef struct  CoreState {
+    uint32_t  sysMbx[8];          /* 0x0480 */
+    uint32_t  usrMbx[8];          /* 0x04a0 */
+    uint32_t  sysMtx[4];          /* 0x04c0 */
+    uint32_t  usrMtx[8];          /* 0x04d0 */
+} CoreState;
+
+typedef struct  CoreIntr {
+    uint32_t  irqStatus;          /* 0x0500 */
+    uint32_t  irqSet;             /* 0x0504 */
+    uint32_t  irqClear;           /* 0x0508 */
+    uint32_t  unused1;            /* 0x050c */
+    uint32_t  srqStatus;          /* 0x0510 */
+    uint32_t  srqSet;             /* 0x0514 */
+    uint32_t  srqClear;           /* 0x0518 */
+    uint32_t  unused2;            /* 0x051c */
+    uint32_t  drqStatus;          /* 0x0520 */
+    uint32_t  drqSet;             /* 0x0524 */
+    uint32_t  drqClear;           /* 0x0528 */
+    uint32_t  unused3;            /* 0x052c */
+    uint32_t  frqStatus;          /* 0x0530 */
+    uint32_t  frqSet;             /* 0x0534 */
+    uint32_t  frqClear;           /* 0x0538 */
+    uint32_t  unused4;            /* 0x053c */
+    uint32_t  hostIrqLatched;     /* 0x0540 */
+    uint32_t  hostIrqSet;         /* 0x0544 */
+    uint32_t  hostIrqClear;       /* 0x0548 */
+    uint32_t  hostIrqEnable;      /* 0x054c */
+    uint32_t  obusFaultStatus;    /* 0x0550 */
+    uint32_t  obusFaultClear;     /* 0x0554 */
+    uint32_t  obusFaultAddr;      /* 0x0558 */
+} CoreIntr;
+
+typedef struct CoreProfile {
+    uint32_t  mutex;              /* 0x0580 */
+    uint32_t  lastConfPcLo;       /* 0x0584 */
+    uint32_t  lastConfPcHi;       /* 0x0588 */
+    uint32_t  lastPcLo;           /* 0x058c */
+    uint32_t  lastPcHi;           /* 0x0590 */
+    uint32_t  braTargetPc0Lo;     /* 0x0594 */
+    uint32_t  braTargetPc0Hi;     /* 0x0598 */
+    uint32_t  braTargetPc1Lo;     /* 0x059c */
+    uint32_t  braTargetPc1Hi;     /* 0x05a0 */
+    uint32_t  braTargetPc2Lo;     /* 0x05a4 */
+    uint32_t  braTargetPc2Hi;     /* 0x05a8 */
+    uint32_t  braTargetPc3Lo;     /* 0x05ac */
+    uint32_t  braTargetPc3Hi;     /* 0x05b0 */
+    uint32_t  unused[3];          /* 0x05b4-0x05bf */
+    uint32_t  profSampleW[4];     /* 0x05c0 */
+} CoreProfile;
+
+typedef struct MaestroMisc {
+    CoreCtrl coreCtrl;          /* 0x0400 */
+    uint32_t   unused1[14];       /* 0x0448-0x047f */
+    CoreState coreState;        /* 0x0480 */
+    uint32_t   unused2[4];        /* 0x04f0-0x04ff */
+    CoreIntr interrupt;         /* 0x0500 */
+    uint32_t   unused3[9];        /* 0x055c-0x057f */
+    CoreProfile profile;        /* 0x0580 */
+} MaestroMisc;
+
+typedef struct Pmc {
+    uint32_t baseReserved;		        /* 0x0000 */
+    uint32_t unused0[1029];
+    PmcCtrlReg ctrl;		            /* 0x1018 */
+    uint32_t unused1[174];	            /* 0x1148-0x13ff */
+    PmcTokenReg token;		            /* 0x1400 */
+    uint32_t unused2[136];		        /* 0x141c-0x163b */
+    PmcPerfPowReg perfPower;	        /* 0x163c */
+    uint32_t unused3[175];		        /* 0x1644-0x18ff */
+    PmcCntReg hwCounter;		        /* 0x1900 */
+    uint32_t unused4[110];		        /* 0x1948-0x1aff */
+    PmcDQMPac dqmPac;                   /* 0x1b00 */
+    uint32_t unused5[32];                 /* 0x1b80-0x1bff */
+    PmcDQMReg dqm;			            /* 0x1c00 */
+    uint32_t unused6[749];		        /* 0x1c4c-0x27ff */
+    uint32_t qStatus[32];		            /* 0x2800 */
+    uint32_t unused7[480];	            /* 0x2880-0x2fff */
+    PmcDqmQMibReg qMib;		            /* 0x3000 */
+    uint32_t unused8[928];	            /* 0x3180-0x3fff */
+    PmcDqmQCtrlReg dqmQCtrl[8]; 	    /* 0x4000 */
+    uint32_t unused9[992];                /* 0x4080-0x4fff */
+    PmcDqmQDataReg dqmQData[8]; 	    /* 0x5000 */
+} Pmc;
+#define PMC_BASE         0xffb00000
+#define PMC ((volatile Pmc * const) PMC_BASE)
+
+/*
+ * Process Monitor Module
+ */
+typedef struct Procmon {
+    PmmReg  pmm;                        /* 0x20000 */
+    uint32_t unused11[22];                /* 0x20008-0x2005f */
+    PMSSBMasterControl SSBMaster;            /* 0x20060 */
+    uint32_t unused12[36];                /* 0x20070-0x200ff */
+    PmbBus pmb;                         /* 0x20100 */
+    uint32_t unused13[64];                /* 0x20300-0x203ff */
+    MaestroMisc maestroReg;             /* 0x20400 */
+} Procmon;
+#define PROC_MON_BASE        0xffb20000
+#define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
+
+typedef struct
+{
+    uint32_t  control;
+#define PMC_PMBM_START		            (1 << 31)
+#define PMC_PMBM_TIMEOUT	            (1 << 30)
+#define PMC_PMBM_SLAVE_ERR	            (1 << 29)
+#define PMC_PMBM_BUSY		            (1 << 28)
+#define PMC_PMBM_BUS_SHIFT              (20)
+#define PMC_PMBM_Read		            (0 << 24)
+#define PMC_PMBM_Write		            (1 << 24)
+    uint32_t  wr_data;
+    uint32_t  mutex;
+    uint32_t  rd_data;
+} PMB_keyhole_reg;
+
+typedef struct PMBMaster {
+    uint32_t config;
+#define PMB_NUM_REGS_SHIFT (20)
+#define PMB_NUM_REGS_MASK  (0x3ff)
+    uint32_t arbitger;
+    uint32_t timeout;
+    uint32_t reserved;
+    PMB_keyhole_reg keyhole[4];
+    uint32_t reserved1[44];
+	uint32_t map[64];
+} PMBMaster;
+#define PMB_BASE             0xffb20100
+#define PMB ((volatile PMBMaster * const) PMB_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6846/pmc_addr.h b/arch/arm/include/asm/arch-bcm6846/pmc_addr.h
new file mode 100644
index 0000000000..1ddf1c67fe
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6846/pmc_addr.h
@@ -0,0 +1,62 @@
+#define PMB_BUS_MAX              2
+#define PMB_BUS_ID_SHIFT         12 
+
+#define PMB_BUS_PERIPH           0
+#define PMB_ADDR_PERIPH          (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH         4
+
+#define PMB_BUS_CHIP_CLKRST      1
+#define PMB_ADDR_CHIP_CLKRST     (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST    0
+
+#define PMB_BUS_RDPPLL           1
+#define PMB_ADDR_RDPPLL          (3 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_RDPPLL         0
+
+#define PMB_BUS_PVTMON           1
+#define PMB_ADDR_PVTMON          (6 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON         0
+
+#define PMB_BUS_MEMC             1
+#define PMB_ADDR_MEMC            (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC           1
+
+#define PMB_BUS_USB20_2X         1
+#define PMB_ADDR_USB20_2X        (10 | PMB_BUS_USB20_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB20_2X       4
+
+#define PMB_BUS_WAN              1
+#define PMB_ADDR_WAN             (11 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WAN            3
+
+#define PMB_BUS_XRDP              1
+#define PMB_ADDR_XRDP             (12 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP            3
+
+#define PMB_BUS_XRDP_RC0          1
+#define PMB_ADDR_XRDP_RC0         (14 | PMB_BUS_XRDP_RC0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC0        1
+
+#define PMB_BUS_XRDP_RC1          1
+#define PMB_ADDR_XRDP_RC1         (15 | PMB_BUS_XRDP_RC1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC1        1
+
+#define PMB_BUS_XRDP_RC2          1
+#define PMB_ADDR_XRDP_RC2         (16 | PMB_BUS_XRDP_RC2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC2        1
+
+#define PMB_BUS_PCIE0             0
+#define PMB_ADDR_PCIE0            (18 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0           1
+
+#define PMB_BUS_PCIE1             0
+#define PMB_ADDR_PCIE1            (19 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1           1
+
+#define PMB_BUS_BIU_PLL           1
+#define PMB_ADDR_BIU_PLL          (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL         1
+
+#define PMB_BUS_BIU_BPCM          1
+#define PMB_ADDR_BIU_BPCM         (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM        1
diff --git a/arch/arm/include/asm/arch-bcm6846/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm6846/pmc_drv_cfg.h
new file mode 100644
index 0000000000..2fcca35220
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6846/pmc_drv_cfg.h
@@ -0,0 +1,38 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_3_X
+#define PMC_IMPL_3_1
+
+#define PMC_UCBID 1
+#define PMC_RAM_BOOT 1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm6846/rng.h b/arch/arm/include/asm/arch-bcm6846/rng.h
new file mode 100644
index 0000000000..401ec12120
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6846/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6846_RNG_H
+#define _6846_RNG_H
+
+#define RNG_BASE	0xff800b80
+
+typedef struct Rng {
+	uint32_t ctrl0;			/* 0x00 */
+	uint32_t rngSoftReset;		/* 0x04 */
+	uint32_t rbgSoftReset;		/* 0x08 */
+	uint32_t totalBitCnt;		/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;			/* 0x14 */
+	uint32_t intStatus;		/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL	(0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL	(0x1<<2)
+	uint32_t intEn;			/* 0x1c */
+	uint32_t rngFifoData;		/* 0x20 */
+	uint32_t fifoCnt;		/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS	0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS	0x33
+	uint32_t perm;			/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6846/ubus4.h b/arch/arm/include/asm/arch-bcm6846/ubus4.h
new file mode 100644
index 0000000000..6cbbcae1ed
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6846/ubus4.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _6846_UBUS4_H
+#define _6846_UBUS4_H
+
+#define UBUS_MAPPED_BASE    0x83000080
+
+typedef struct Ubus4ClkCtrlCfgRegs {
+    uint32_t ClockCtrl;
+#define UBUS4_CLK_CTRL_EN_SHIFT    (0)
+#define UBUS4_CLK_CTRL_EN_MASK     (0x1 << UBUS4_CLK_CTRL_EN_SHIFT)
+#define UBUS4_CLK_BYPASS_SHIFT     (2)
+#define UBUS4_CLK_BYPASS_MASK      (0x1 << UBUS4_CLK_BYPASS_SHIFT)
+#define UBUS4_MIN_CLK_SEL_SHIFT    (4)
+#define UBUS4_MIN_CLK_SEL_MASK     (0x7 << UBUS4_MIN_CLK_SEL_SHIFT)
+#define UBUS4_MID_CLK_SEL_SHIFT    (8)
+#define UBUS4_MID_CLK_SEL_MASK     (0x7 << UBUS4_MID_CLK_SEL_SHIFT)
+    uint32_t reserved0[3];
+    uint32_t Min2Mid_threshhold;
+    uint32_t Mid2Max_threshhold;
+    uint32_t Mid2Min_threshhold;
+    uint32_t Max2Mid_threshhold;
+    uint32_t ClkIntoMin;
+    uint32_t ClkIntoMid;
+    uint32_t ClkIntoMax;
+    uint32_t reserved1;
+    uint32_t ClkMinTime;
+    uint32_t ClkMidTime;
+    uint32_t ClkMaxTime;
+} Ubus4ClkCtrlCfgRegs;
+
+#define UBUS4CLK ((volatile Ubus4ClkCtrlCfgRegs * const) UBUS_MAPPED_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6855/BPCM.h b/arch/arm/include/asm/arch-bcm6855/BPCM.h
new file mode 100644
index 0000000000..58f9a8452d
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/BPCM.h
@@ -0,0 +1,904 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmbAddr:12;	// [11:00]
+		uint32_t map_rev:4;	// [15:12] always non-zero for AVS3 devices (see CLASSIC_BPCM_ID_REG below)
+		uint32_t island:4;	// [19:16]
+		uint32_t devType:4;	// [23:20] see enum above
+		uint32_t hw_rev:8;	// [31:24]
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+enum {
+	kPMB_NO_DEVICE = 0,
+	kPMB_BPCM = 1,		// in AVS3, this structure does not contain ARS registers (except for "classic" BPCM devices) 
+	kPMB_MIPS_PLL = 2,
+	kPMB_GEN_PLL = 3,
+	kPMB_LC_PLL = 4,
+	kPMB_CLKRST = 5,
+	kPMB_PVTMON = 6,	// used in in AVS3 when PVT is wrapped in a BPCM structure
+	kPMB_TMON_INTERNAL = 7,	// ditto - used when TMON thermistor is on-die
+	kPMB_TMON_EXTERNAL = 8,	// ditto - used when thermistor is off-die
+	kPMB_ARS = 9,		// AVS Remote Sensors - remote oscillators and Power-Watchdog
+	// 10..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu_reset_n:8;	// 07:00    R/W
+		uint32_t c0l2_reset:1;	// 08:08    R/W
+		uint32_t c1l2_reset:1;	// 09:09    R/W
+		uint32_t reserved0:6;	// 15:10    R/O
+		uint32_t cpu_bpcm_init_on:8;	// 23:16    R/W
+		uint32_t c0l2_bpcm_init_on:1;	// 24:24    R/W
+		uint32_t c1l2_bpcm_init_on:1;	// 25:25    R/W
+		uint32_t ubus_sr:1;	// 26:26    R/W
+		uint32_t cci_sr:1;	// 27:27    R/W
+		uint32_t webcores_sr:1;	// 28:28    R/W
+		uint32_t hw_done:1;	// 29:29    R/O
+		uint32_t sw_done:1;	// 30:30    R/W
+		uint32_t start:1;	// 31:31    R/W
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t reserved0:2;	// 11:10
+		uint32_t ndiv_frac:20;	// 31:12    
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECNDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t reserved0:12;	// 15:04
+		uint32_t mdiv0:8;	// 23:16
+		uint32_t mdiv1:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECPDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv2:8;	// 07:00
+		uint32_t mdiv3:8;	// 15:08
+		uint32_t mdiv4:8;	// 23:16
+		uint32_t mdiv5:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECCH25_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	uint32_t reserved0;
+	uint32_t timer_control;
+	uint32_t timer_status;
+	uint32_t reserved1[2];
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	// BPCM
+	uint32_t control;	// offset 0x10, PMB reg index 4
+	BPCM_SR_CONTROL sr_control;	// offset 0x14, PMB reg index 5
+	uint32_t reserved1[2];	// offset 0x18, PMB reg index 6/7
+	// Client-specific registers
+	uint32_t client_specific[24];	// offset 0x20, PMB reg index 8..31
+	// Zones
+	BPCM_ZONE zones[];	// offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1))
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08, actual offset = 2
+	uint32_t cfg_control;	// offset = 0x10, actual offset = 4
+	BPCM_SR_CONTROL sr_control;	// offset = 0x14, actual offset = 5
+	uint32_t reserved1[6];	// offset = 0x18, actual offset = 6
+	ARM_CONTROL_REG arm_control;	// offset = 0x30, actual offset = 12
+	uint32_t biu_clk_control0;	// offset = 0x34, actual offset = 13
+	uint32_t tbd[18];	// offset = 0x38, actual offset = 14
+	BPCM_ZONE zones;	// offset = 0x80, actual offset = 32
+} ARM_BPCM_REGS;
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	PLL_DECNDIV_REG decndiv;	// offset = 0x44, actual offset = 0x11
+	PLL_DECPDIV_REG decpdiv;	// offset = 0x48, actual offset = 0x12
+	PLL_DECCH25_REG decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t dac_data:10;	// [09:00]
+		uint32_t vavs_minb0:1;	// [10:10] - R/O iVDDC <= Vmin0
+		uint32_t vavs_minb1:1;	// [11:11] - R/O iVDDC <= Vmin1
+		uint32_t vavs_warnb0:1;	// [12:12] - R/O iVDDC <= Vwarn0
+		uint32_t vavs_warnb1:1;	// [13:13] - R/O iVDDC <= Vwarn1
+		uint32_t vavs_maxb0:1;	// [14:14] - R/O iVDDC <= Vmax0
+		uint32_t vavs_maxb1:1;	// [15:15] - R/O iVDDC <= Vmax1
+		uint32_t adc_data:10;	// [25:16] - R/O ADC output data in offset binary format
+		uint32_t adc_data_valid:1;	// [26:26] - R/O
+		uint32_t reserved:5;	// [31:27] - R/O 
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_DATA_REG;
+
+typedef union {
+	// little endian - from page 5 of "ANA_VTMON_TS16FF_S0 & ANA_VTMON_PAD_TS16FF_Sx Module Specification"
+	// defaut value = 0x00000001
+	struct {
+		uint32_t bg_adj:3;	// [02:00] - default = 1
+		uint32_t vtest_sel:4;	// [06:03] - VTest = i_VDCC * (<value>+1)/20, default = 0
+		uint32_t rmon_sel:3;	// [09:07]
+		uint32_t mode:3;	// [12:10]
+		uint32_t adc_insel:2;	// [14:13] - only used in expert mode (mode = 0b111)
+		uint32_t dac_en:1;	// [15:15] - only used in expert mode (mode = 0b111)
+		uint32_t con_pad:1;	// [16:16] - only used in expert mode (mode = 0b111)
+		uint32_t burnin_en:1;	// [17:17] - only used in expert mode (mode = 0b111)
+		uint32_t reserved:1;	// [18:18]
+		uint32_t vdccmon_refadj_max1:1;	// [19:19]
+		uint32_t vdccmon_refadj_min0:4;	// [23:20]
+		uint32_t vdccmon_refadj_min1:3;	// [26:24]
+		uint32_t dac_reset:1;	// [27:27]
+		uint32_t dac_set:1;	// [28:28]
+		uint32_t vdccmon_refadj_max0:3;	// [31:29]
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t rstb:1;	// [00:00] - low active.  default = 0 (i.e. in reset)
+		uint32_t pwr_dn:1;	// [01:01] - high-active.  default = 1 (i.e. powered down)
+		uint32_t clk_en:1;	// [02:02]
+		uint32_t reserved0:1;	// [03:03]
+		uint32_t sel:3;	// [06:04] - see enum below - reset value = 0
+		uint32_t reserved1:1;	// [07:07]
+		uint32_t clk_div:5;	// [12:08] - value needed to divide pm_clk by (2*clk_div) to generate a 5MHz clock
+		uint32_t reserved2:19;	// [31:13]
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_CONFIG_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t accum_en:1;	// [00:00]
+		uint32_t round_en:1;	// [01:01] defaults to 1 (rounding enabled)
+		uint32_t reserved1:6;	// [07:02]
+		uint32_t skip_len:4;	// [11:08] how many samples to skip prior to starting averaging, default = 3
+		uint32_t reserved0:20;	// [31:12]
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_ACQ_CONFIG_REG;
+
+typedef union {
+	struct {
+		uint32_t warn_threshold:10;	// [09:00] - in ADC counts
+		uint32_t warn_en:1;	// [10:10]
+		uint32_t reserved0:3;	// [13:11]
+		uint32_t clear_warn:1;	// [14:14] - Write only
+		uint32_t warn:1;	// [15:15] - Read only
+		uint32_t reset_threshold:10;	// [25:16] - in ADC counts
+		uint32_t reset_en:1;	// [26:26]
+		uint32_t reserved1:3;	// [29:27]
+		uint32_t clear_reset:1;	// [30:30] - Write only
+		uint32_t reset:1;	// [31:31] - Read only
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_TEMP_WARN_RESET_REG;
+
+typedef union {
+	struct {
+		uint32_t reset_value:10;	// [09:00]
+		uint32_t reserved:22;	// [31:10]
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_RESET_TEMP_REG;
+
+typedef union {
+	struct {
+		uint32_t value:10;	// [09:00] - there are <meas_len> fractional bits
+		uint32_t reserved0:8;	// [17:10]
+		uint32_t valid:1;	// [18:18]
+		uint32_t busy:1;	// [19:19]
+		uint32_t reserved1:4;	// [23:20]
+		uint32_t meas_len:3;	// [26:24]  #samples = 2^<value>
+		uint32_t reserved2:4;	// [30:27]
+		uint32_t enable:1;	// [31:31]
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_ACCUM_REG;
+
+typedef union {
+	struct {
+		uint32_t sel:6;	// [05:00] - ring oscillator select (0..35)
+		uint32_t reserved2:2;	// [07:06]
+		uint32_t srm_ind_en:1;	// [08:08]
+		uint32_t srm_ind_od:1;	// [09:09]
+		uint32_t srm_ind_sel:2;	// [11:10]
+		uint32_t reserved1:4;	// [15:12]
+		uint32_t out:1;	// [16:16]
+		uint32_t all_idl_low_oscs:1;	// [17:17]
+		uint32_t all_idl_hi_oscs:1;	// [18:18]
+		uint32_t reserved0:13;	// [31:19]
+	} Bits;
+	uint32_t Reg32;
+} ROSC_CTRL_STS_REG;
+
+typedef union {
+	struct {
+		uint32_t count:16;	// [15:00]
+		uint32_t valid:1;	// [16:16]
+		uint32_t too_lo:1;	// [17:17] - count <= thresh_lo (only when THRESH_EN == 1)
+		uint32_t too_hi:1;	// [18:18] - count <= thresh_hi (only when THRESH_EN == 1)
+		uint32_t reserved0:5;	// [23:19]
+		uint32_t continuous:1;	// [24:24]
+		uint32_t thresh_en:1;	// [25:25] - enable threshold detection
+		uint32_t ectr_en:1;	// [26:26] - enable counter
+		uint32_t src_en:1;	// [27:27] - enable event source (may not do anything???)
+		uint32_t meas_len:4;	// [31:28] - interval = 2^(<meas_len>+1)
+	} Bits;
+	uint32_t Reg32;
+} ECTR_CTRL_STS_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;	// [15:00]
+		uint32_t thresh_hi:16;	// [31:16]
+	} Bits;
+	uint32_t Reg32;
+} ECTR_THRESH_REG;
+
+typedef struct {
+	ECTR_CTRL_STS_REG count_reg;
+	ECTR_THRESH_REG thresh_reg;
+} ROSC_REGS;
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	uint32_t reserved1[12];	// offset 0x10, PMB reg index 4-15 (future proofing )
+	APVTMON_CONTROL_REG control;	// offset 0x40, PMB reg index 16
+	APVTMON_CONFIG_STATUS_REG config;	// offset 0x44, PMB reg index 17
+	APVTMON_DATA_REG adc_data;	// offset 0x48, PMB reg index 18
+	uint32_t reserved2;	// offset 0x4c, PMB reg index 19
+	APVTMON_ACQ_CONFIG_REG accum_config;	// offset 0x50, PMB reg index 20
+	APVTMON_TEMP_WARN_RESET_REG warn_rst;	// offset 0x54, PMB reg index 21
+	uint32_t reserved3[2];	// offset 0x58, PMB reg index 23
+	APVTMON_ACCUM_REG acq_accum_regs[8];	// offset 0x60, PMB reg index 24-31
+	ROSC_CTRL_STS_REG rosc_ctrl_sts;	// offset 0x80, PMB reg index 32
+	uint32_t rosc_en_lo;	// offset 0x84, PMB reg index 33
+	uint32_t rosc_en_hi;	// offset 0x88, PMB reg index 34
+	uint32_t rosc_idle_lo;	// offset 0x8c, PMB reg index 35
+	uint32_t rosc_idle_hi;	// offset 0x90, PMB reg index 36
+	uint32_t reserved4[3];	// offset 0x94, PMB reg index 37-39
+	ROSC_REGS ectr_regs;	// offset 0xa0, PMB reg index 40/41
+} PVTMON_REGS;
+// retrieves the BYTE offset of a PVTMON register:
+#define PVTMON_OFFSET(reg) (offsetof(PVTMON_REGS,reg)>>2)
+
+typedef struct {
+// PMB-slave
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[6];	// offset 0x08, PMB reg index 2-7
+	// ROSC registers
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset 0x20, PMB reg index 8
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset 0x24, PMB reg index 9
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset 0x28, PMB reg index 10
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset 0x2c, PMB reg index 11
+	BPCM_AVS_PWD_CONTROL pwd_ctrl;	// offset 0x30, PMB reg index 12
+	BPCM_PWD_ACCUM_CONTROL pwd_accum;	// offset 0x34, PMB reg index 13
+} ARS_REGS;
+// retrieves the BYTE offset of an ARS register:
+#define ARS_OFFSET(reg) (offsetof(ARS_REGS, reg)>>2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved1;	// offset = 0x2c, actual offset = 11
+	uint32_t clkrst_cfg;	// offset = 0x30, actual offset = 12
+	uint32_t clkrst_control;	// offset = 0x34, actual offset = 13
+	uint32_t xtal_control;	// offset = 0x38, actual offset = 14
+	uint32_t clkrst_stat;	// offset = 0x3c, actual offset = 15
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6855/boot0.h b/arch/arm/include/asm/arch-bcm6855/boot0.h
new file mode 100644
index 0000000000..af69028c9e
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/boot0.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6855_BOOT0_H
+#define _6855_BOOT0_H
+
+#include <asm-offsets.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+_bcm_boot:
+	mov	r0,#0
+
+	b skip_emu
+    .org    0x10
+    .word   1
+    .org    0x40
+
+skip_emu:
+	mcr	p15,0,r0,c8,c7,0		/* Invalidate TLB */
+	mcr	p15,0,r0,c7,c5,0		/* Invalidate icache */
+	
+	/* Initialize system control register enable i-cache */
+	mrc	p15,0,r0,c1,c0,0
+	bic	r0,r0,#(CR_C|CR_A|CR_M)		/* Clear C, A, M bits */
+	orr	r0,r0,#CR_I			/* Set I bit: enable instruction cache */
+	mcr	p15,0,r0,c1,c0,0
+
+	isb
+
+	/* relocate the code, init'ed data from flash to lmem  */	
+relo_image:
+	adr     r1, _bcm_boot		/* r1 source address in flash */
+	ldr	r0, =__image_copy_start	/* r0 dest address in sram */
+	subs	r4, r1, r0		/* r4 relocation offset */
+	beq	relo_dtb		/* skip relocation */
+	ldr	r2, =__image_copy_end	/* r2 dest ending address in flash */
+
+relo_loop:
+	ldmia	r1!, {r10-r11}
+	stmia	r0!, {r10-r11}
+	cmp	r0, r2
+	blo	relo_loop
+
+	/* if we attached dtb after bss, need to relocate dtb as well */	
+relo_dtb:
+#if defined(CONFIG_SPL_OF_CONTROL) && defined(CONFIG_OF_SEPARATE)
+
+#ifdef CONFIG_OF_SPL_SEPARATE_BSS
+	ldr	r3, =__image_binary_end
+#else
+	ldr	r3, =__bss_end
+#endif
+	add	r1, r3, r4       /* r1 source address in flash */
+	/* check ftd size ... */
+	/* struct fdt_header {
+	fdt32_t magic;
+	fdt32_t totalsize; */
+	ldr	r0, [r1, #4]	/* r0 total size */
+	rev	r0, r0          /* byte order from fdt to little endian */
+	lsr	r0, r0, #2      /* in the order of 4 bytes aligned */
+	add	r0, r0, #1
+	lsl	r0, r0, #2 
+	add	r2, r1, r0       /* r2 dest ending address in flash */
+	mov	r0, r3           /* r0 dest address in sram */
+
+dtb_loop:
+	ldmia	r1!, {r10-r11}
+	stmia	r0!, {r10-r11}
+	cmp	r1, r2
+	blo	dtb_loop
+#endif
+	ldr	r0, =reset
+	bx	r0
+
+#endif
+	.align(5), 0x0
+_start:
+	ARM_VECTORS
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6855/brom.h b/arch/arm/include/asm/arch-bcm6855/brom.h
new file mode 100644
index 0000000000..9cdcb5c791
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6855_BROM_H
+#define _6855_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6855/cpu.h b/arch/arm/include/asm/arch-bcm6855/cpu.h
new file mode 100644
index 0000000000..8d7df2d9de
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/cpu.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6855_CPU_H
+#define _6855_CPU_H
+
+#define BOOTLUT_BASE      0xffff0000
+#define BIUCFG_BASE       0x81060000
+
+#define MAX_NUM_OF_CPU	3
+
+typedef struct BIUCFG_Access {
+	uint32_t permission;	/* 0x0 */
+	uint32_t reserved0;		/* 0x4 */
+	uint32_t cpu_defeature;	/* 0x8 */
+	uint32_t dbg_security;	/* 0xc */
+	uint32_t rsvd1[36];	/* 0x10 - 0x9f */
+	uint32_t ts_access;	/* 0xa0 - 0xa3 */
+	uint32_t rsvd2[23];	/* 0xa4 - 0xff */
+} BIUCFG_Access;
+
+typedef struct BIUCFG_Cluster {
+	uint32_t permission;	/* 0x0 */
+	uint32_t config;	/* 0x4 */
+	uint32_t status;	/* 0x8 */
+	uint32_t control;	/* 0xc */
+	uint32_t cpucfg;	/* 0x10 */
+	uint32_t dbgrom;	/* 0x14 */
+	uint32_t rsvd1[2];	/* 0x18 - 0x1f */
+	uint64_t rvbar_addr[4];	/* 0x20 - 0x3f */
+	uint32_t rsvd2[48];	/* 0x40 - 0xff */
+} BIUCFG_Cluster;
+
+typedef struct BIUCFG_AuxClkCtrl {
+	uint32_t clk_control;	/* 0x0 */
+	uint32_t clk_ramp;	/* 0x4 */
+	uint32_t clk_pattern;	/* 0x8 */
+	uint32_t rsvd;		/* 0xC */
+} BIUCFG_AuxClkCtrl;
+
+typedef struct BIUCFGux {
+	uint32_t permission;	/* 0 */
+	uint32_t rsvd1[3];	/* 0x04 - 0x0c */
+	BIUCFG_AuxClkCtrl cluster_clkctrl[2];	/* 0x10 - 0x2c */
+	uint32_t rsvd2[52];	/* 0x30 - 0xFF */
+} BIUCFG_Aux;
+
+typedef struct BIUCFG {
+	BIUCFG_Access access;	/* 0x0 - 0xff */
+	BIUCFG_Cluster cluster[1];	/* 0x100 - 0x1ff */
+	uint32_t rsvd1[320];	/* 0x200 - 0x6ff */
+	BIUCFG_Aux aux;		/* 0x700 - 0x7ff */
+	uint32_t rsrvd2[512];	/* 0x800 - 0xfff */
+	uint32_t TSO_CNTCR;	/* 0x1000 */
+	uint32_t rsvd2[2047];	/* 0x1004 - 0x2fff */
+} BIUCFG;
+
+#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6855/ddr.h b/arch/arm/include/asm/arch-bcm6855/ddr.h
new file mode 100644
index 0000000000..877c7abebd
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/ddr.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6855_DDR_H
+#define _6855_DDR_H
+
+#define MEMC_BASE   0x80180000  /* DDR IO Buf Control */
+
+// FIXMET
+
+#endif /* _6855_DDR_H */
+
diff --git a/arch/arm/include/asm/arch-bcm6855/misc.h b/arch/arm/include/asm/arch-bcm6855/misc.h
new file mode 100644
index 0000000000..b32039e7be
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/misc.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6855_MISC_H
+#define _6855_MISC_H
+
+/*
+ * Gpio Controller
+ */
+typedef struct GpioControl {
+        uint32_t GPIODir[8];             /* 0x00-0x1c */
+        uint32_t GPIOio[8];              /* 0x20-0x3c */
+        uint32_t PadCtrl;                 /* 0x40 */
+        uint32_t SpiSlaveCfg;             /* 0x44 */
+        uint32_t TestControl;             /* 0x48 */
+        uint32_t TestPortBlockEnMSB;      /* 0x4c */
+        uint32_t TestPortBlockEnLSB;      /* 0x50 */
+        uint32_t TestPortBlockDataMSB;    /* 0x54 */
+        uint32_t TestPortBlockDataLSB;    /* 0x58 */
+#define PINMUX_DATA_SHIFT       12
+#define PINMUX_0                0
+#define PINMUX_1                1
+#define PINMUX_2                2
+#define PINMUX_3                3
+#define PINMUX_4                4
+#define PINMUX_5                5
+#define PINMUX_6                6
+#define PINMUX_7                7
+#define PAD_CTRL_SHIFT          12
+#define PAD_CTRL_MASK           (0x3f<<PAD_CTRL_SHIFT)
+#define PAD_SEL_SHIFT           12
+#define PAD_AMP_SHIFT           15
+#define PAD_IND_SHIFT           16
+#define PAD_GMII_SHIFT          17
+       uint32_t TestPortCmd;             /* 0x5c */
+#define LOAD_MUX_REG_CMD        0x21
+#define LOAD_PAD_CTRL_CMD       0x22
+        uint32_t DiagReadBack;            /* 0x60 */
+        uint32_t DiagReadBackHi;          /* 0x64 */
+        uint32_t GeneralPurpose;          /* 0x68 */
+        uint32_t spare[3];
+} GpioControl;
+
+#define GPIO_BASE          0xff800500
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+/*
+ ** Misc Register Set Definitions.
+ */
+typedef struct Misc {
+    uint32_t  miscStrapBus;                       /* 0x00 */
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           5
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOTROM_BOOT_N           (0x1 << 11)
+
+#define MISC_STRAP_BUS_PCIE_RC_MODE_SHIFT       0
+#define MISC_STRAP_BUS_PCIE_RC_MODE MASK        (1 << MISC_STRAP_BUS_PCIE_SINGLE_LANES_SHIFT) /* 1-root complex  0-end point */
+#define MISC_STRAP_GPON_TX_EN_SHIFT             1         
+#define MISC_STRAP_GPON_TX_EN_MASK              (1 << MISC_STRAP_GPON_TX_EN_SHIFT)  // 1-Single ended, 0-differential
+#define MISC_STRAP_USB_PMU_POLARITY_SHIFT       30
+#define MISC_STRAP_USB_PMU_POLARITY_MASK        (1 << MISC_STRAP_USB_PMU_POLARITY_SHIFT)  // 1-active low, 0-active high
+
+    uint32_t  miscStrapOverride;                  /* 0x04 */
+    uint32_t  miscMaskUBUSErr;                    /* 0x08 */
+    uint32_t  miscPeriphCtrl;                     /* 0x0c */
+    uint32_t  miscSPImasterCtrl;                  /* 0x10 */
+    uint32_t  miscDierevid;                       /* 0x14 */
+    uint32_t  miscPeriphMiscCtrl;                 /* 0x18 */
+    uint32_t  miscPeriphMiscStat;                 /* 0x1c */
+    uint32_t  miscSoftResetB;                     /* 0x20 */
+    uint32_t  reserved0;                          /* 0x24 */
+    uint32_t  miscSWdebugNW[2];                   /* 0x3c */
+    uint32_t  miscWDresetCtrl;                    /* 0x30 */
+} Misc;
+
+#define MISC_BASE          0xff802600
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+typedef struct TopControl {
+   uint32_t      MiiPadCtl;          // 0x0
+   uint32_t      DgSensePadCtl;      // 0x4
+#define DG_CTRL_SHIFT   4
+#define DG_EN_SHIFT     3
+#define DG_TRIM_SHIFT   0
+   uint32_t      TpDirOverride0;     // 0x8
+   uint32_t      TpDirOverride1;     // 0xc
+   uint32_t      AnaDetectModeHv;    // 0x10
+   uint32_t      Twop5vDetectCtrl;   // 0x14
+   uint32_t      ResetStatus;        // 0x18
+#define PCIE_RESET_STATUS       0x10000000
+#define SW_RESET_STATUS         0x20000000
+#define HW_RESET_STATUS         0x40000000
+#define POR_RESET_STATUS        0x80000000
+#define RESET_STATUS_MASK       0xF0000000
+   uint32_t      MdioMasterSelect;   // 0x1c
+   uint32_t      OrionIntPending;    // 0x20
+   uint32_t      Pm2Pm3RescalSts;    // 0x24
+   uint32_t      AdslClkSample;      // 0x28
+   uint32_t      ChipTracking0;      // 0x2c
+   uint32_t      ChipTracking1;      // 0x30
+   uint32_t      OtpChipidLC;        // 0x34
+#define CHIP_ID_LC_SIZE         4
+#define CHIP_ID_LC_MASK         0x0000000f
+   uint32_t      SwControlReg;       // 0x6c
+} TopControl;
+
+#define TOP_CONTROL_BASE 0xff85a000
+#define TOPCTRL ((volatile TopControl * const) TOP_CONTROL_BASE)
+#define TOP ((volatile TopControl * const) TOP_CONTROL_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6855/otp.h b/arch/arm/include/asm/arch-bcm6855/otp.h
new file mode 100644
index 0000000000..2c659fd4a7
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/otp.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _6855_OTP_H
+#define _6855_OTP_H
+
+#define JTAG_OTP_BASE   0xff802800
+
+/* row 8 */
+#define OTP_CPU_CORE_CFG_ROW            	8
+#define OTP_CPU_CORE_CFG_SHIFT          	28
+#define OTP_CPU_CORE_CFG_MASK           	0x7
+
+#define OTP_SEC_CHIPVAR_ROW             	8
+#define OTP_SEC_CHIPVAR_SHIFT           	24
+#define OTP_SEC_CHIPVAR_MASK            	0xf
+
+/* row 14 */
+#define OTP_PCM_DISABLE_ROW             	14
+#define OTP_PCM_DISABLE_SHIFT           	13
+#define OTP_PCM_DISABLE_MASK            	0x1
+
+/* row 9 */
+#define OTP_CPU_CLOCK_FREQ_ROW          	9
+#define OTP_CPU_CLOCK_FREQ_SHIFT        	0
+#define OTP_CPU_CLOCK_FREQ_MASK         	0x7
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          7
+
+/* row 20 */
+#define OTP_CHIPID_ROW                  	20
+#define OTP_CHIPID_SHIFT                	0
+#define OTP_CHIP_ID_MASK                	0xffffffff
+
+/* row 23 */
+#define OTP_CUST_MFG_MRKTID_ROW                 23
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+/* row 17 */
+#define OTP_BRCM_ENFORCE_BINIT_ROW 		17
+#define OTP_BRCM_ENFORCE_BINIT_SHIFT		13
+#define OTP_BRCM_ENFORCE_BINIT_MASK		1
+
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)												\
+	static otp_hw_cmn_row_t __VV__[ ] = {										\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1, {.addr_type = OTP_HW_CMN_ROW_ADDR_ROW} },	\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT,1, {.addr_type = OTP_HW_CMN_ROW_ADDR_ROW}},	\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT,1, {.addr_type = OTP_HW_CMN_ROW_ADDR_ROW} },				\
+	{OTP_MAP_SEC_CHIPVAR, OTP_SEC_CHIPVAR_ROW, OTP_SEC_CHIPVAR_MASK, OTP_SEC_CHIPVAR_SHIFT, 1, {.addr_type = OTP_HW_CMN_ROW_ADDR_ROW}},\
+	{OTP_MAP_CPU_CORE_CFG, OTP_CPU_CORE_CFG_ROW, OTP_CPU_CORE_CFG_MASK, OTP_CPU_CORE_CFG_SHIFT, 1, {.addr_type = OTP_HW_CMN_ROW_ADDR_ROW}},				\
+	{OTP_MAP_CPU_CLOCK_FREQ, OTP_CPU_CLOCK_FREQ_ROW, OTP_CPU_CLOCK_FREQ_MASK,OTP_CPU_CLOCK_FREQ_SHIFT, 1, {.addr_type = OTP_HW_CMN_ROW_ADDR_ROW} }		\
+	}
+#endif
+
diff --git a/arch/arm/include/asm/arch-bcm6855/pmc.h b/arch/arm/include/asm/arch-bcm6855/pmc.h
new file mode 100644
index 0000000000..924fcbe4a0
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/pmc.h
@@ -0,0 +1,169 @@
+#ifndef PMC_H
+#define PMC_H 
+
+/*
+ * Power Management Control
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t propagate_to_err  :  1; // [00:00] -+
+        uint32_t propagate_slv_err :  1; // [01:01]  | - these are potentially dangerous and MAY cause a system crash
+        uint32_t pmbus_reset_n     :  1; // [02:02] -+
+        uint32_t reserved0         :  1; // [03:03]
+        uint32_t maxPmbIdx         :  3; // [06:04] 0-based (0-7)
+        uint32_t reserved1         :  1; // [07:07]
+        uint32_t maxClientId       : 12; // [19:08] 0-based (theoreticaly 0-4095, but code limits this to 256 devices - 0-255)
+        uint32_t numRegsPerClient  : 10; // [29:20] some power of 2 - number of 32-bit registers in each client (max = 512)
+        uint32_t startDiscovery    :  1; // [30:30] kicks off H/W discovery of clients and fills in the map (see PMB_REGS below)
+        uint32_t discoveryBusy     :  1; // [31:31] whether or not H/W discovery is still busy creating the map
+    } Bits;
+    uint32_t Reg32;
+} PMB_CONFIG_REG;
+
+typedef union
+{
+    struct {
+        uint32_t data      : 16; // [15:00]
+        uint32_t reserved1 : 16; // [31:16]
+    } Bits;
+    uint32_t Reg32;
+} SSBM_data_reg;
+
+typedef union
+{
+    struct {
+        uint32_t  ssb_addr    : 10; // [09:00]
+        uint32_t  ssb_cmd     :  2; // [11:10]
+        uint32_t  ssb_en      :  1; // [12:12]
+        uint32_t  ssb_add_pre :  1; // [13:13]
+        uint32_t  reserved2   :  1; // [14:14]
+        uint32_t  ssb_start   :  1; // [15:15]
+        uint32_t  reserved1   : 16; // [31:16]
+    } Bits;
+    uint32_t Reg32;
+} SSBM_control_reg;
+
+typedef union
+{
+    struct {
+        uint32_t busy      :  1; // [00:00]
+        uint32_t reserved1 : 31; // [31:01]
+    } Bits;
+    uint32_t Reg32;
+} SSBM_status_reg;
+
+typedef union
+{
+    struct {
+        uint32_t swreg_th_lo : 8; // [07:00]
+        uint32_t swreg_th_hi : 8; // [15:08]
+        uint32_t reserved    :16; // [31:16]
+    } Bits;
+    uint32_t Reg32;
+} SSBM_SWREG_th_hilo_reg;
+
+typedef union
+{
+    struct {
+        uint32_t ssb_lock_addr : 10; // [09:00]
+        uint32_t lock_bit      :  1; // [10:10]
+        uint32_t lock_mode     :  1; // [11:11]
+        uint32_t reserved      : 20; // [31:12]
+    } Bits;
+    uint32_t Reg32;
+} SSBM_SWREG_lock_reg;
+
+#define kSSBWrite   0x01
+#define kSSBRead    0x02
+#define kSSBEn      (1 << 12)
+#define kSSBStart   (1 << 15)
+
+typedef struct PMSSBMasterControl {
+    uint32_t control;     /* 0x0060 */
+    uint32_t wr_data;      /* 0x0064 */
+    uint32_t rd_data;      /* 0x0068 */
+    uint32_t status;      /* 0x006c */
+    SSBM_SWREG_th_hilo_reg  ssbmThHiLo;     /* 0x0070 */
+    SSBM_SWREG_lock_reg     ssbmSwLock;     /* 0x0074 */
+} PMSSBMasterControl;
+
+#define SWR_FIRST 0
+#define SWR_LAST 4
+#define SWR_READ_CMD_P 0xB800
+#define SWR_WR_CMD_P   0xB400
+#define SWR_EN         0x1000
+#define SET_ADDR(ps, reg)  (((ps) << 5 | ((reg) & 0x1f)) & 0x2ff)
+
+#define SR_TEST(x)  {\
+                     int num;\
+                     for(num=1000;(((PROCMON->SSBMaster.control) & 0x8000) && (num > 0)) ; num--) ;\
+                         if(!num) \
+                         {\
+                             printf("Error num %d timeout num = %d!!!", (x),  num);\
+                         }\
+}
+
+typedef struct PmmReg {
+    uint32_t memPowerCtrl;            /* 0x0000 */
+    uint32_t regSecurityConfig;       /* 0x0004 */
+} PmmReg;
+
+typedef struct keyholeReg {
+    uint32_t ctrlSts;
+    uint32_t wrData;
+    uint32_t mutex;
+    uint32_t rdData;
+} keyholeReg;
+
+typedef struct PmbBus {
+    PMB_CONFIG_REG config;          /* 0x0100 */
+    uint32_t arbiter;         /* 0x0104 */
+    uint32_t timeout;         /* 0x0108 */
+    uint32_t unused1;         /* 0x010c */
+    keyholeReg keyhole[4];  /* 0x0110-0x014f */
+    uint32_t unused2[44];     /* 0x0150-0x01ff */
+    uint32_t map[64];         /* 0x0200-0x02ff */ 
+}PmbBus;
+
+typedef struct Procmon {
+    PmmReg  pmm;                        /* 0x20000 */
+    uint32_t unused11[22];                /* 0x20008-0x2005f */
+    PMSSBMasterControl SSBMaster;            /* 0x20060-0x20077 */
+    uint32_t unused12[34];                /* 0x20078-0x200ff */
+    PmbBus pmb;                         /* 0x20100 */
+} Procmon;
+#define PROC_MON_BASE        0xffb20000
+#define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
+
+typedef struct
+{
+    uint32_t  control;
+#define PMC_PMBM_START                  (1 << 31)
+#define PMC_PMBM_TIMEOUT                (1 << 30)
+#define PMC_PMBM_SLAVE_ERR              (1 << 29)
+#define PMC_PMBM_BUSY                   (1 << 28)
+#define PMC_PMBM_BUS_SHIFT              (20)
+#define PMC_PMBM_Read                   (0 << 24)
+#define PMC_PMBM_Write                  (1 << 24)
+    uint32_t  wr_data;
+    uint32_t  mutex;
+    uint32_t  rd_data;
+} PMB_keyhole_reg;
+
+typedef struct PMBMaster {
+    uint32_t config;
+#define PMB_NUM_REGS_SHIFT (20)
+#define PMB_NUM_REGS_MASK  (0x3ff)
+    uint32_t arbitger;
+    uint32_t timeout;
+    uint32_t reserved;
+    PMB_keyhole_reg keyhole[4];
+    uint32_t reserved1[44];
+    uint32_t map[64];
+} PMBMaster;
+#define PMB_BASE        0xffb20100
+#define PMB ((volatile PMBMaster * const) PMB_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6855/pmc_addr.h b/arch/arm/include/asm/arch-bcm6855/pmc_addr.h
new file mode 100644
index 0000000000..1349221e17
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/pmc_addr.h
@@ -0,0 +1,79 @@
+#define PMB_BUS_MAX				2
+#define PMB_BUS_ID_SHIFT		12
+
+#define PMB_BUS_PERIPH			0
+#define PMB_ADDR_PERIPH			(0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH		4
+
+#define PMB_BUS_CHIP_CLKRST		0
+#define PMB_ADDR_CHIP_CLKRST	(1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST	0
+
+#define PMB_BUS_SYSPLL			0
+#define PMB_ADDR_SYSPLL			(3 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL		0
+
+#define PMB_BUS_PVTMON			0
+#define PMB_ADDR_PVTMON			(6 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON		0
+
+#define PMB_BUS_MEMC			0
+#define PMB_ADDR_MEMC			(8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC			1
+
+#define PMB_BUS_USB20_2X		1
+#define PMB_ADDR_USB20_2X		(10 | PMB_BUS_USB20_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB20_2X		4
+
+#define PMB_BUS_WAN				1
+#define PMB_ADDR_WAN			(11 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WAN			3
+
+#define PMB_BUS_XRDP			1
+#define PMB_ADDR_XRDP			(12 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP			3
+
+#define PMB_BUS_PCIE0			1
+#define PMB_ADDR_PCIE0			(17 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0			1
+
+#define PMB_BUS_PCIE1			1
+#define PMB_ADDR_PCIE1			(18 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1			1
+
+#define PMB_BUS_WLAN0			1
+#define PMB_ADDR_WLAN0			(19 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0			1
+
+#define PMB_BUS_WLAN0_PHY1		1
+#define PMB_ADDR_WLAN0_PHY1		(20 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY1	1
+
+#define PMB_BUS_WLAN0_PHY2		1
+#define PMB_ADDR_WLAN0_PHY2		(21 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0_PHY2	1
+
+#define PMB_BUS_ORION_CPU0		0
+#define PMB_ADDR_ORION_CPU0		(32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0	1
+
+#define PMB_BUS_ORION_CPU1		0
+#define PMB_ADDR_ORION_CPU1		(33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1	1
+
+#define PMB_BUS_ORION_CPU2		0
+#define PMB_ADDR_ORION_CPU2		(33 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU2	1
+
+#define PMB_BUS_ORION_NONCPU	0
+#define PMB_ADDR_ORION_NONCPU	(36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU	1
+
+#define PMB_BUS_BIU_PLL			0
+#define PMB_ADDR_BIU_PLL		(38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL		0
+
+#define PMB_BUS_BIU_BPCM		0
+#define PMB_ADDR_BIU_BPCM		(39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM		1
+
diff --git a/arch/arm/include/asm/arch-bcm6855/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm6855/pmc_drv_cfg.h
new file mode 100644
index 0000000000..83aa0127c1
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/pmc_drv_cfg.h
@@ -0,0 +1,34 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_ON_HOSTCPU      1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm6855/rng.h b/arch/arm/include/asm/arch-bcm6855/rng.h
new file mode 100644
index 0000000000..e30018116a
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6855_RNG_H
+#define _6855_RNG_H
+
+#define RNG_BASE	0xff800b80
+
+typedef struct Rng {
+	uint32_t ctrl0;			/* 0x00 */
+	uint32_t rngSoftReset;		/* 0x04 */
+	uint32_t rbgSoftReset;		/* 0x08 */
+	uint32_t totalBitCnt;		/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;			/* 0x14 */
+	uint32_t intStatus;		/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL	(0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL	(0x1<<2)
+	uint32_t intEn;			/* 0x1c */
+	uint32_t rngFifoData;		/* 0x20 */
+	uint32_t fifoCnt;		/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS	0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS	0x33
+	uint32_t perm;			/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6855/ubus4.h b/arch/arm/include/asm/arch-bcm6855/ubus4.h
new file mode 100644
index 0000000000..006d4b3b9d
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6855/ubus4.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _6855_UBUS4_H
+#define _6855_UBUS4_H
+
+#define UBUS_MAPPED_BASE    0x83000080
+
+typedef struct Ubus4ClkCtrlCfgRegs {
+    uint32_t ClockCtrl;
+#define UBUS4_CLK_CTRL_EN_SHIFT    (0)
+#define UBUS4_CLK_CTRL_EN_MASK     (0x1 << UBUS4_CLK_CTRL_EN_SHIFT)
+#define UBUS4_CLK_BYPASS_SHIFT     (2)
+#define UBUS4_CLK_BYPASS_MASK      (0x1 << UBUS4_CLK_BYPASS_SHIFT)
+#define UBUS4_MIN_CLK_SEL_SHIFT    (4)
+#define UBUS4_MIN_CLK_SEL_MASK     (0x7 << UBUS4_MIN_CLK_SEL_SHIFT)
+#define UBUS4_MID_CLK_SEL_SHIFT    (8)
+#define UBUS4_MID_CLK_SEL_MASK     (0x7 << UBUS4_MID_CLK_SEL_SHIFT)
+    uint32_t reserved0[3];
+    uint32_t Min2Mid_threshhold;
+    uint32_t Mid2Max_threshhold;
+    uint32_t Mid2Min_threshhold;
+    uint32_t Max2Mid_threshhold;
+    uint32_t ClkIntoMin;
+    uint32_t ClkIntoMid;
+    uint32_t ClkIntoMax;
+    uint32_t reserved1;
+    uint32_t ClkMinTime;
+    uint32_t ClkMidTime;
+    uint32_t ClkMaxTime;
+} Ubus4ClkCtrlCfgRegs;
+#define UBUS4CLK ((volatile Ubus4ClkCtrlCfgRegs * const) UBUS_MAPPED_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6856/BPCM.h b/arch/arm/include/asm/arch-bcm6856/BPCM.h
new file mode 100644
index 0000000000..724e999bab
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6856/BPCM.h
@@ -0,0 +1,750 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmbAddr:12;	// [11:00]
+		uint32_t map_rev:4;	// [15:12] always non-zero for AVS3 devices (see CLASSIC_BPCM_ID_REG below)
+		uint32_t island:4;	// [19:16]
+		uint32_t devType:4;	// [23:20] see enum above
+		uint32_t hw_rev:8;	// [31:24]
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;	// [07:00]
+		uint32_t hw_rev:4;	// [11:08]
+		uint32_t map_rev:4;	// [15:12] always zero for classic devices (technically upper 4-bits of hw_rev)
+		uint32_t sw_strap:16;	// [31:16]
+	} Bits;
+	uint32_t Reg32;
+} CLASSIC_BPCM_ID_REG;
+
+// types of PMB devices
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu_reset_n:8;	// 07:00    R/W
+		uint32_t c0l2_reset:1;	// 08:08    R/W
+		uint32_t c1l2_reset:1;	// 09:09    R/W
+		uint32_t reserved0:6;	// 15:10    R/O
+		uint32_t cpu_bpcm_init_on:8;	// 23:16    R/W
+		uint32_t c0l2_bpcm_init_on:1;	// 24:24    R/W
+		uint32_t c1l2_bpcm_init_on:1;	// 25:25    R/W
+		uint32_t ubus_sr:1;	// 26:26    R/W
+		uint32_t cci_sr:1;	// 27:27    R/W
+		uint32_t webcores_sr:1;	// 28:28    R/W
+		uint32_t hw_done:1;	// 29:29    R/O
+		uint32_t sw_done:1;	// 30:30    R/W
+		uint32_t start:1;	// 31:31    R/W
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t reserved0:2;	// 11:10
+		uint32_t ndiv_frac:20;	// 31:12    
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECNDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t reserved0:12;	// 15:04
+		uint32_t mdiv0:8;	// 23:16
+		uint32_t mdiv1:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECPDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv2:8;	// 07:00
+		uint32_t mdiv3:8;	// 15:08
+		uint32_t mdiv4:8;	// 23:16
+		uint32_t mdiv5:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECCH25_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	BPCM_ZONE_N_FREQ_SCALAR_CONTROL freq_scalar_control;
+	uint32_t reserved[4];
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	// BPCM
+	uint32_t control;	// offset 0x10, PMB reg index 4
+	BPCM_SR_CONTROL sr_control;	// offset 0x14, PMB reg index 5
+	uint32_t reserved1[2];	// offset 0x18, PMB reg index 6/7
+	// Client-specific registers
+	uint32_t client_specific[24];	// offset 0x20, PMB reg index 8..31
+	// Zones
+	BPCM_ZONE zones[];	// offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1))
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	CLASSIC_BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x1c, actual offset = 7
+	BPCM_SR_CONTROL sr_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0[3];	// offset = 0x24, actual offset = 9
+	ARM_CONTROL_REG arm_control;	// offset = 0x30, actual offset = 12
+	uint32_t biu_clk_control0;	// offset = 0x34, actual offset = 13
+	uint32_t reserved1[2];	// offset = 0x38, actual offset = 14
+	BPCM_ZONE zones;	// offset = 0x40, actual offset = 16
+} ARM_BPCM_REGS;
+
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	PLL_DECNDIV_REG decndiv;	// offset = 0x44, actual offset = 0x11
+	PLL_DECPDIV_REG decpdiv;	// offset = 0x48, actual offset = 0x12
+	PLL_DECCH25_REG decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_CLASSIC_BPCM_REGS;
+
+#define PLLCLASSICBPCMOffset(reg)  offsetof(PLL_CLASSIC_BPCM_REGS,reg)
+#define PLLCLASSICBPCMRegOffset(reg)   (PLLCLASSICBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04
+	uint32_t reserved0[6];	// offset = 0x08
+	PLL_CTRL_REG resets;	// offset = 0x20
+	PLL_CFG0_REG cfg0;	// offset = 0x24
+	PLL_CFG1_REG cfg1;	// offset = 0x28
+	PLL_NDIV_REG ndiv;	// offset = 0x2c
+	PLL_PDIV_REG pdiv;	// offset = 0x30
+	PLL_LOOP0_REG loop0;	// offset = 0x34
+	uint32_t reserved1;	// offset = 0x38
+	PLL_LOOP1_REG loop1;	// offset = 0x3c
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x40
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x44
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x48
+	PLL_STAT_REG stat;	// offset = 0x4c
+	uint32_t strap;		// offset = 0x50
+	PLL_DECNDIV_REG decndiv;	// offset = 0x54
+	PLL_DECPDIV_REG decpdiv;	// offset = 0x58
+	PLL_DECCH25_REG decch25;	// offset = 0x5c
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved1;	// offset = 0x2c, actual offset = 11
+	uint32_t clkrst_cfg;	// offset = 0x30, actual offset = 12
+	uint32_t clkrst_control;	// offset = 0x34, actual offset = 13
+	uint32_t xtal_control;	// offset = 0x38, actual offset = 14
+	uint32_t clkrst_stat;	// offset = 0x3c, actual offset = 15
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6856/brom.h b/arch/arm/include/asm/arch-bcm6856/brom.h
new file mode 100644
index 0000000000..2c4c19944f
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6856/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6856_BROM_H
+#define _6856_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6856/cpu.h b/arch/arm/include/asm/arch-bcm6856/cpu.h
new file mode 100644
index 0000000000..de8fce0025
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6856/cpu.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6856_CPU_H
+#define _6856_CPU_H
+
+#define BIUCFG_BASE       0x81060000
+#define CCI400_BASE       0x81090000
+
+typedef struct BIUCFG_Access {
+    uint32_t permission;        /* 0x0 */
+    uint32_t sbox;              /* 0x4 */
+    uint32_t cpu_defeature;     /* 0x8 */
+    uint32_t dbg_security;      /* 0xc */
+    uint32_t rsvd1[32];         /* 0x10 - 0x8f */
+    uint64_t violation[2];      /* 0x90 - 0x9f */
+    uint32_t ts_access[2];      /* 0xa0 - 0xa7 */
+    uint32_t rsvd2[22];         /* 0xa8 - 0xff */
+}BIUCFG_Access;
+
+typedef struct BIUCFG_Cluster {
+    uint32_t permission;        /* 0x0 */
+    uint32_t config;            /* 0x4 */
+    uint32_t status;            /* 0x8 */
+    uint32_t control;           /* 0xc */
+    uint32_t cpucfg;            /* 0x10 */
+    uint32_t dbgrom;            /* 0x14 */
+    uint32_t rsvd1[2];          /* 0x18 - 0x1f */
+    uint64_t rvbar_addr[4];     /* 0x20 - 0x3f */
+    uint32_t rsvd2[48];         /* 0x40 - 0xff */
+}BIUCFG_Cluster;
+
+typedef struct BIUCFG_AuxClkCtrl {
+    uint32_t clk_control;       /* 0x0 */
+    uint32_t clk_ramp;          /* 0x4 */
+    uint32_t clk_pattern;       /* 0x8 */
+    uint32_t rsvd;              /* 0xC */
+} BIUCFG_AuxClkCtrl;
+
+typedef struct BIUCFG_Aux {
+    uint32_t            permission;         /* 0 */
+    uint32_t            rsvd1[3];           /* 0x04 - 0x0c */
+    BIUCFG_AuxClkCtrl cluster_clkctrl[2]; /* 0x10 - 0x2c */
+    uint32_t            rsvd2[52];          /* 0x30 - 0xFF */
+} BIUCFG_Aux;
+
+
+typedef struct BIUCFG {
+    BIUCFG_Access  access;        /* 0x0 - 0xff*/
+    BIUCFG_Cluster cluster[1];    /* 0x100 - 0x1ff*/
+    uint32_t         rsvd1[320];    /* 0x200 - 0x6ff */
+    BIUCFG_Aux     aux;           /* 0x700 - 0x7ff */
+    uint32_t         rsvd2[2560];   /* 0x800 - 0x2fff */
+
+}BIUCFG;
+
+#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
+
+typedef struct CCI400_SlaveIntf {
+#define SNOOP_CTRL_ENABLE_SNOOP            0x1
+    uint32_t snoop_ctrl;        /* 0x0 */
+    uint32_t share_ovr;         /* 0x4 */
+    uint32_t rsvd1[62];         /* 0x8 - 0xff */
+    uint32_t arqos_ovr;         /* 0x100 */
+    uint32_t awqos_ovr;         /* 0x104 */
+    uint32_t rsvd2[2];          /* 0x108 - 0x10f */
+    uint32_t qos_max_ot;        /* 0x110 */
+    uint32_t rsvd3[955];        /* 0x114 - 0xfff */
+}CCI400_SlaveIntf;
+
+
+typedef struct CCI400 {
+    uint32_t ctrl_ovr;        /* 0x0 */
+    uint32_t spec_ctrl;       /* 0x4 */
+#define SECURE_ACCESS_UNSECURE_ENABLE      0x1
+    uint32_t secr_acc;        /* 0x8 */
+    uint32_t status;          /* 0xc */
+    uint32_t impr_err;        /* 0x10 */
+    uint32_t rdvd[59];        /* 0x14 */
+    uint32_t pmu_ctrl;        /* 0x100 */
+    uint32_t rsvd1[959];      /* 0x104 - 0xfff */
+    CCI400_SlaveIntf si[5]; /* 0x1000 - 0x5fff */
+}CCI400;
+
+#define CCI400 ((volatile CCI400 * const) CCI400_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6856/ddr.h b/arch/arm/include/asm/arch-bcm6856/ddr.h
new file mode 100644
index 0000000000..883328d6ae
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6856/ddr.h
@@ -0,0 +1,573 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6856_DDR_H
+#define _6856_DDR_H
+
+#define MEMC_BASE        0x80180000
+
+typedef struct AXIInterface {
+   uint32_t CFG;				/* 0x00 */
+#define MEMC_AXI_WRITE_ACK_MODE_SHIFT		9
+#define MEMC_AXI_FAST_ACK_MODE_MASK			(1 << MEMC_AXI_WRITE_ACK_MODE_SHIFT)
+   uint32_t REP_ARB_MODE;		/* 0x04 */
+   uint32_t SCRATCH;			/* 0x08 */
+   uint32_t ESRCID_CFG;		/* 0x0c */
+   uint32_t SRC_QUEUE_CTL[8];	/* 0x10 */
+   uint32_t AXI_DEBUG;          /* 0x30 */
+   uint32_t unused[3];		/* 0x34-0x3f */
+} AXIInterface;
+
+typedef struct EDISEngine {
+   uint32_t REV_ID;             /* 0x00 */
+   uint32_t CTRL_TRIG;          /* 0x04 */
+   uint32_t CTRL_MODE;          /* 0x08 */
+   uint32_t CTRL_SIZE;          /* 0x0c */
+   uint32_t CTRL_ADDR_START;    /* 0x10 */
+   uint32_t CTRL_ADDR_START_EXT;/* 0x14 */
+   uint32_t CTRL_ADDR_END;      /* 0x18 */
+   uint32_t CTRL_ADDR_END_EXT;  /* 0x1c */
+   uint32_t CTRL_WRITE_MASKS;   /* 0x20 */
+   uint32_t CTRL_INT_ENABLES;   /* 0x24 */
+   uint32_t unused0[6];         /* 0x28-0x3f */
+   uint32_t STAT_MAIN;          /* 0x40 */
+   uint32_t STAT_WORDS_WRITTEN; /* 0x44 */
+   uint32_t STAT_WORDS_READ;    /* 0x48 */
+   uint32_t STAT_ERROR_COUNT;   /* 0x4c */
+   uint32_t STAT_ERROR_BITS;    /* 0x50 */
+   uint32_t STAT_ADDR_LAST;     /* 0x54 */
+   uint32_t STAT_ADDR_LAST_EXT; /* 0x58 */
+   uint32_t STAT_CLOCK_CYCLES;  /* 0x5c */
+   uint32_t unused1[7];         /* 0x60-0x7b */
+   uint32_t STAT_DEBUG;         /* 0x7c */
+   uint32_t STAT_DATA_PORT[8];  /* 0x80-0x9c */
+   uint32_t GEN_LFSR_STATE[4];  /* 0xa0-0xac */
+   uint32_t GEN_CLOCK;          /* 0xb0 */
+   uint32_t GEN_PATTERN;        /* 0xb4 */
+   uint32_t unused2[2];         /* 0xb8-0xbf */
+   uint32_t BYTELANE_0_CTRL_LO; /* 0xc0 */
+   uint32_t BYTELANE_0_CTRL_HI; /* 0xc4 */
+   uint32_t BYTELANE_1_CTRL_LO; /* 0xc8 */
+   uint32_t BYTELANE_1_CTRL_HI; /* 0xcc */
+   uint32_t BYTELANE_2_CTRL_LO; /* 0xd0 */
+   uint32_t BYTELANE_2_CTRL_HI; /* 0xd4 */
+   uint32_t BYTELANE_3_CTRL_LO; /* 0xd8 */
+   uint32_t BYTELANE_3_CTRL_HI; /* 0xdc */
+   uint32_t BYTELANE_0_STAT_LO; /* 0xe0 */
+   uint32_t BYTELANE_0_STAT_HI; /* 0xe4 */
+   uint32_t BYTELANE_1_STAT_LO; /* 0xe8 */
+   uint32_t BYTELANE_1_STAT_HI; /* 0xec */
+   uint32_t BYTELANE_2_STAT_LO; /* 0xf0 */
+   uint32_t BYTELANE_2_STAT_HI; /* 0xf4 */
+   uint32_t BYTELANE_3_STAT_LO; /* 0xf8 */
+   uint32_t BYTELANE_3_STAT_HI; /* 0xfc */
+} EDISEngine;
+
+typedef struct RangeCtrl {
+   uint32_t CTRL;                /* 0x00 */
+   uint32_t UBUS0_PORT;          /* 0x04 */
+   uint32_t UBUS0_PORT_UPPER;    /* 0x08 */
+   uint32_t BASE;                /* 0x0c */
+   uint32_t BASE_UPPER;          /* 0x10 */
+   uint32_t SECLEV_EN;           /* 0x14 */
+} RangeCtrl;
+
+typedef struct SecureRangeCheckers {
+   uint32_t LOCK;            /* 0x00 */
+   uint32_t LOG_INFO[3];     /* 0x04 - 0x0c */
+   RangeCtrl RANGE_CTRL[8];/* 0x10 - 0xcc */
+   uint32_t unused[12];      /* 0xd0 - 0xff */
+} SecureRangeCheckers;
+
+typedef struct DDRPhyControl {
+   uint32_t PRIMARY_REVISION;    /* 0x00 */
+   uint32_t SECONDARY_REVISION;  /* 0x04 */
+   uint32_t FEATURE;             /* 0x08 */
+   uint32_t PLL_STATUS;          /* 0x0c */
+   uint32_t PLL_CONFIG;          /* 0x10 */
+   uint32_t PLL_CONTROL1;        /* 0x14 */
+   uint32_t PLL_CONTROL2;        /* 0x18 */
+   uint32_t PLL_CONTROL3;        /* 0x1c */
+   uint32_t PLL_DIVIDER;         /* 0x20 */
+   uint32_t PLL_PRE_DIVIDER;     /* 0x24 */
+   uint32_t PLL_SS_EN;           /* 0x28 */
+   uint32_t PLL_SS_CFG;          /* 0x2c */
+   uint32_t AUX_CONTROL;         /* 0x30 */
+   uint32_t IDLE_PAD_CONTROL;    /* 0x34 */
+   uint32_t IDLE_PAD_EN0;        /* 0x38 */
+   uint32_t IDLE_PAD_EN1;        /* 0x3c */
+   uint32_t DRIVE_PAD_CTL;       /* 0x40 */
+   uint32_t DRIVE_PAD_CTL_2T;    /* 0x44 */
+   uint32_t DRIVE_PAD_CTL_2T_A;  /* 0x48 */
+   uint32_t STATIC_PAD_CTL;      /* 0x4c */
+   uint32_t STATIC_PAD_CTL_2T;   /* 0x50 */
+   uint32_t STATIC_PAD_CTL_2T_A; /* 0x54 */
+   uint32_t RX_TRIM;             /* 0x58 */
+   uint32_t DRAM_CFG;            /* 0x5c */
+   uint32_t DRAM_TIMING2;        /* 0x60 */
+   uint32_t DRAM_TIMING3;        /* 0x64 */
+   uint32_t VDL_REGS[45];        /* 0x68-0x11b */
+   uint32_t UPDATE_VDL;          /* 0x11c */
+   uint32_t UPDATE_VDL_SNOOP1;   /* 0x120 */
+   uint32_t UPDATE_VDL_SNOOP2;   /* 0x124 */
+   uint32_t CMND_REG1;           /* 0x128 */
+   uint32_t CMND_AUX_REG1;       /* 0x12c */
+   uint32_t CMND_REG2;           /* 0x130 */
+   uint32_t CMND_AUX_REG2;       /* 0x134 */
+   uint32_t CMND_REG3;           /* 0x138 */
+   uint32_t CMND_AUX_REG3;       /* 0x13c */
+   uint32_t CMND_REG4;           /* 0x140 */
+   uint32_t CMND_AUX_REG4;       /* 0x144 */
+   uint32_t MODE_REG[8];         /* 0x148-167 */
+   uint32_t ALERT_CLEAR;         /* 0x168 */
+   uint32_t ALERT_STATUS;        /* 0x16c */
+   uint32_t ALERT_DF1;           /* 0x170 */
+   uint32_t WRITE_LEVEL_CTRL;    /* 0x174 */
+   uint32_t WRITE_LEVEL_STATUS;  /* 0x178 */
+   uint32_t READ_EN_CTRL;        /* 0x17c */
+   uint32_t READ_EN_STATUS ;     /* 0x180 */
+   uint32_t VIRT_VTT_CTRL;       /* 0x184 */
+   uint32_t VIRT_VTT_STATUS;     /* 0x188 */
+   uint32_t VIRT_VTT_CONNECTION; /* 0x18c */
+   uint32_t VIRT_VTT_OVERRIDE;   /* 0x190 */
+   uint32_t VREF_DAC_CTRL;       /* 0x194 */
+#define DDRPHY_VREF_DAC_CTRL_PDN_SHIFT             12
+#define DDRPHY_VREF_DAC_CTRL_PDN_MASK              (0xf << DDRPHY_VREF_DAC_CTRL_PDN_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT            6
+#define DDRPHY_VREF_DAC_CTRL_DAC1_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT            0
+#define DDRPHY_VREF_DAC_CTRL_DAC0_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT)
+   uint32_t STANDBY_CTRL;        /* 0x198 */
+   uint32_t DEBUG_FREEZE_EN;     /* 0x19c */
+   uint32_t DEBUG_MUX_CTRL;      /* 0x1a0 */
+   uint32_t DFI_CTRL;            /* 0x1a4 */
+   uint32_t WRITE_ODT_CTRL;      /* 0x1a8 */
+   uint32_t ABI_PAR_CTRL;        /* 0x1ac */
+   uint32_t ZQ_CAL;              /* 0x1b0 */
+   uint32_t unused6[147];        /* 0x1b4-0x3ff */
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+   uint32_t VDL_CTRL_WR[10];     /* 0x00 - 0x27 */
+   uint32_t VDL_CTRL_RD[22];     /* 0x28 - 0x7f */
+   uint32_t VDL_CLK_CTRL;        /* 0x80 */
+   uint32_t VDL_LDE_CTRL;        /* 0x84 */
+   uint32_t RD_EN_DLY_CYC;       /* 0x88 */
+#define RD_EN_DLY_CYC_CS0_CYCLES_SHIFT      0x0
+#define RD_EN_DLY_CYC_CS0_CYCLES_MASK       (0xf<<RD_EN_DLY_CYC_CS0_CYCLES_SHIFT)
+   uint32_t WR_CHAN_DLY_CYC;     /* 0x8c */
+   uint32_t RD_CTRL;             /* 0x90 */
+   uint32_t RD_FIFO_ADDR;        /* 0x94 */
+   uint32_t RD_FIFO_DATA;        /* 0x98 */
+   uint32_t RD_FIFO_DM_DBI;      /* 0x9c */
+   uint32_t RD_FIFO_STATUS;      /* 0xa0 */
+   uint32_t RD_FIFO_CLR;         /* 0xa4 */
+   uint32_t DYNAMIC_CLK_CTRL;    /* 0xa8 */
+   uint32_t IDLE_PAD_CTRL;       /* 0xac */
+   uint32_t DRIVE_PAD_CTRL;      /* 0xb0 */
+   uint32_t DQSP_DRIVE_PAD_CTRL; /* 0xb4 */
+   uint32_t DQSN_DRIVE_PAD_CTRL; /* 0xb8 */
+   uint32_t RD_EN_DRIVE_PAD_CTRL;/* 0xbc */
+   uint32_t STATIC_PAD_CTRL;     /* 0xc0 */
+   uint32_t DQ_RX_TRIM;          /* 0xc4 */
+   uint32_t MISC_RX_TRIM;        /* 0xc8 */
+   uint32_t DQS_RX_TRIM;         /* 0xcc */
+   uint32_t WR_PREAMBLE_MODE;    /* 0xd0 */
+   uint32_t ODT_CTRL;            /* 0xd4 */
+   uint32_t LDO_CONFIG;          /* 0xd8 */
+   uint32_t CLOCK_ENABLE;        /* 0xdc */
+   uint32_t CLOCK_IDLE;          /* 0xe0 */
+   uint32_t RD_CHAN_FIFO_CLR;    /* 0xe4 */
+   uint32_t BL_SPARE_REG;        /* 0xe8 */
+   uint32_t unused[69];          /* 0xec-0x1ff */
+} DDRPhyByteLaneControl;
+
+typedef struct MEMCControl {
+   uint32_t GLB_VERS;               /* 0x000 */
+   uint32_t GLB_GCFG;               /* 0x004 */
+#define MEMC_GLB_GCFG_DRAM_EN_SHIFT        31
+#define MEMC_GLB_GCFG_DRAM_EN_MASK         (0x1<<MEMC_GLB_GCFG_DRAM_EN_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ_SHIFT      30
+#define MEMC_GLB_GCFG_FORCE_SEQ_MASK       (0x1<<MEMC_GLB_GCFG_FORCE_SEQ_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT     29
+#define MEMC_GLB_GCFG_FORCE_SEQ2_MASK      (1<<MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT)
+#define MEMC_GLB_GCFG_RBF_REORDER_SHIFT    28
+#define MEMC_GLB_GCFG_RBF_REORDER_MASK     (1<<MEMC_GLB_GCFG_RBF_REORDER_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT   24
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_MASK    (0x3<<MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_2X           0x0
+#define MEMC_GLB_GCFG_PHY_DFI_4X           0x1
+#define MEMC_GLB_GCFG_PHY_DFI_8X           0x2
+#define MEMC_GLB_GCFG_DFI_EN_SHIFT         10
+#define MEMC_GLB_GCFG_DFI_EN_MASK          (0x1<<MEMC_GLB_GCFG_DFI_EN_SHIFT)
+#define MEMC_GLB_GCFG_MCLKSRC_SHIFT        9
+#define MEMC_GLB_GCFG_MCLKSRC_MASK         (0x1<<MEMC_GLB_GCFG_MCLKSRC_SHIFT)
+#define MEMC_GLB_GCFG_MEMINITDONE_SHIFT    8
+#define MEMC_GLB_GCFG_MEMINITDONE_MASK     (0x1<<MEMC_GLB_GCFG_MEMINITDONE_SHIFT)
+   uint32_t GLB_MRQ_CFG;            /* 0x008 */
+   uint32_t unused0;                /* 0x00c */
+   uint32_t GLB_FSBL_STATE;         /* 0x010 */
+#define MEMC_GLB_FSBL_DRAM_SIZE_SHIFT      0
+#define MEMC_GLB_FSBL_DRAM_SIZE_MASK       (0xf << MEMC_GLB_FSBL_DRAM_SIZE_SHIFT)
+   uint32_t unused1[3];             /* 0x014 - 0x01f */
+
+   uint32_t SRAM_REMAP_CTRL;        /* 0x020 */
+   uint32_t SRAM_REMAP_CTRL_UPPER;  /* 0x024 */
+   uint32_t SRAM_REMAP_INIT;        /* 0x028 */
+   uint32_t SRAM_REMAP_LOG_INFO_0;  /* 0x02c */
+   uint32_t SRAM_REMAP_LOG_INFO_1;  /* 0x030 */
+   uint32_t SRAM_REMAP_LOG_INFO_2;  /* 0x034 */
+   uint32_t unused2[2];             /* 0x038-0x03f */
+
+   uint32_t RBF_REORDER_0_CFG[16];  /* 0x040 - 0x07f */
+
+   uint32_t INTR2_CPU_STATUS;       /* 0x080 */
+   uint32_t INTR2_CPU_SET;          /* 0x084 */
+   uint32_t INTR2_CPU_CLEAR;        /* 0x088 */
+   uint32_t INTR2_CPU_MASK_STATUS;  /* 0x08c */
+   uint32_t INTR2_CPU_MASK_SET;     /* 0x090 */
+   uint32_t INTR2_CPU_MASK_CLEAR;   /* 0x094 */
+   uint32_t unused3[26];            /* 0x098-0x0ff */
+
+   uint32_t CHN_CFG_CNFG;           /* 0x100 */
+#define MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT            16
+#define MEMC_CHN_CFG_CNFG_CS_MODE_MASK             (0x3 << MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT)
+   uint32_t CHN_CFG_CSST;           /* 0x104 */
+   uint32_t unused4[2];             /* 0x108-0x10f */
+   uint32_t CHN_CFG_ROW00_0;        /* 0x110 */
+   uint32_t CHN_CFG_ROW00_1;        /* 0x114 */
+   uint32_t CHN_CFG_ROW01_0;        /* 0x118 */
+   uint32_t CHN_CFG_ROW01_1;        /* 0x11c */
+   uint32_t CHN_CFG_ROW02_0;        /* 0x120 */
+   uint32_t CHN_CFG_COL00_0;        /* 0x124 */
+   uint32_t CHN_CFG_COL00_1;        /* 0x128 */
+   uint32_t CHN_CFG_COL01_0;        /* 0x12c */
+   uint32_t CHN_CFG_COL01_1;        /* 0x130 */
+   uint32_t CHN_CFG_BNK10;          /* 0x134 */
+   uint32_t CHN_CFG_BG0;            /* 0x138 */
+   uint32_t unused5;                /* 0x13c */
+   uint32_t CHN_CFG_DRAM_SZ_CHK;    /* 0x140 */
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT                          4
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_MASK                           (0xf<<MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT)
+   uint32_t CHN_CFG_DIAG_SEL;       /* 0x144 */
+   uint32_t unused6[46];            /* 0x148-0x1ff */
+
+   uint32_t CHN_TIM_DCMD;           /* 0x200 */
+   uint32_t CHN_TIM_DMODE_0;        /* 0x204 */
+   uint32_t CHN_TIM_DMODE_2;        /* 0x208 */
+   uint32_t CHN_TIM_CLKS;           /* 0x20c */
+#define MEMC_CHN_TIM_CLKS_REF_RATE_SHIFT          8
+#define MEMC_CHN_TIM_CLKS_REF_MAX_DELAY_SHIFT     24
+#define MEMC_CHN_TIM_CLKS_REF_DISABLE_SHIFT       31
+   uint32_t CHN_TIM_ODT;            /* 0x210 */
+   uint32_t CHN_TIM_TIM1_0;         /* 0x214 */
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tWL [31:24] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_MASK                            0xff000000
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_SHIFT                           24
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_DEFAULT                         0x00000004
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRP [23:16] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_MASK                            0x00ff0000
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_SHIFT                           16
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_DEFAULT                         0x00000006
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tCL [15:08] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_MASK                            0x0000ff00
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_SHIFT                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_DEFAULT                         0x00000005
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRCD [07:00] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_MASK                           0x000000ff
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_ALIGN                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_BITS                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_SHIFT                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_DEFAULT                        0x00000006
+
+   uint32_t CHN_TIM_TIM1_1;         /* 0x218 */
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_L [31:24] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_S [23:16] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_L [15:08] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_MASK                         0x0000ff00
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_SHIFT                        8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_S [07:00] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_MASK                         0x000000ff
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_SHIFT                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_DEFAULT                      0x00000002
+
+   uint32_t CHN_TIM_TIM1_2;         /* 0x21c */
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tFAW [31:24] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_MASK                           0xff000000
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_SHIFT                          24
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_DEFAULT                        0x00000000
+/* MC_CHN_TIM :: TIM1_2 :: reserved0 [23:16] */
+#define MC_CHN_TIM_TIM1_2_reserved0_MASK                           0x00ff0000
+#define MC_CHN_TIM_TIM1_2_reserved0_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_reserved0_BITS                           8
+#define MC_CHN_TIM_TIM1_2_reserved0_SHIFT                          16
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRTP [15:08] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_MASK                           0x0000ff00
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_SHIFT                          8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_DEFAULT                        0x00000002
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRC [07:00] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_ALIGN                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_BITS                            8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_SHIFT                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_DEFAULT                         0x00000011
+
+   uint32_t CHN_TIM_TIM1_3;         /* 0x220 */
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_L [31:24] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_S [23:16] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: reserved_for_padding0 [15:12] */
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_MASK               0x0000f000
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_ALIGN              0
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_BITS               4
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_SHIFT              12
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_L [11:08] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_MASK                          0x00000f00
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_BITS                          4
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_SHIFT                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_DEFAULT                       0x00000004
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_S [07:00] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_MASK                          0x000000ff
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_BITS                          8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_SHIFT                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_DEFAULT                       0x00000004
+
+   uint32_t CHN_TIM_TIM2;          /* 0x224 */
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2R [31:30] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_MASK                             0xc0000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_BITS                             2
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_SHIFT                            30
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2W [29:27] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_MASK                             0x38000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_SHIFT                            27
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2R [26:24] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_MASK                             0x07000000
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_SHIFT                            24
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: reserved_for_padding0 [23:22] */
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_MASK                 0x00c00000
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_ALIGN                0
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_BITS                 2
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_SHIFT                22
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2W [21:18] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_MASK                             0x003c0000
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_BITS                             4
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_SHIFT                            18
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: reserved1 [17:16] */
+#define MC_CHN_TIM_TIM2_reserved1_MASK                             0x00030000
+#define MC_CHN_TIM_TIM2_reserved1_ALIGN                            0
+#define MC_CHN_TIM_TIM2_reserved1_BITS                             2
+#define MC_CHN_TIM_TIM2_reserved1_SHIFT                            16
+/* MC_CHN_TIM :: TIM2 :: TIM2_tAL [15:12] */
+#define MC_CHN_TIM_TIM2_TIM2_tAL_MASK                              0x0000f000
+#define MC_CHN_TIM_TIM2_TIM2_tAL_ALIGN                             0
+#define MC_CHN_TIM_TIM2_TIM2_tAL_BITS                              4
+#define MC_CHN_TIM_TIM2_TIM2_tAL_SHIFT                             12
+#define MC_CHN_TIM_TIM2_TIM2_tAL_DEFAULT                           0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tRFC [11:00] */
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_MASK                             0x00000fff
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_BITS                             12
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_SHIFT                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_DEFAULT                          0x00000014
+
+   uint32_t unused7[2];                /* 0x228 - 0x22f */
+   uint32_t CHN_TIM_PHY_ST;            /* 0x230 */
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP       0x1
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_HW_RESET       0x2
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_SW_RESET       0x4
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_READY          0x10
+   uint32_t CHN_TIM_DRAM_CFG;       /* 0x234 */
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT           12
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_MASK            (0x1<<MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT     10
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_MASK      (0x1<<MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT      0
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_MASK       (0xf<<MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT)
+#define MC_DRAM_CFG_DDR3                          0x1
+   uint32_t CHN_TIM_STAT;              /* 0x238 */
+   uint32_t CHN_TIM_PERF;              /* 0x23c */
+   uint32_t unused8[48];               /* 0x240-0x2ff */
+
+   uint32_t ARB_CFG;                   /* 0x300 */
+#define MEMC_ARB_CFG_RR_MODE_SHIFT      0x0
+#define MEMC_ARB_CFG_RR_MODE_MASK       (0x1<<MEMC_ARB_CFG_RR_MODE_SHIFT)
+#define MEMC_ARB_CFG_BURST_MODE_SHIFT   0x1
+#define MEMC_ARB_CFG_BURST_MODE_MASK    (0x1<<MEMC_ARB_CFG_BURST_MODE_SHIFT)
+   uint32_t ARB_QUE_DIS[2];            /* 0x304 */
+   uint32_t ARB_SP_SEL[2];             /* 0x30c */
+   uint32_t ARB_RDWR_QUANTUM;          /* 0x314 */
+   uint32_t unused9[2];                /* 0x318 - 0x31f */
+   uint32_t ARB_SP_PRI[9];             /* 0x320 */
+   uint32_t unused10[3];               /* 0x344-0x34f */
+   uint32_t ARB_RR_QUANTUM[18];        /* 0x350 */
+   uint32_t unused11[26];              /* 0x398 - 0x3ff */
+
+   uint32_t unused12[48];              /* 0x400-0x4bf */
+
+   AXIInterface AXIWIF;			     /* 0x4c0-0x4ff */
+
+   uint32_t unused13[192];		     /* 0x500-0x7ff */
+
+   EDISEngine EDIS_0;                /* 0x800 */
+   uint32_t unused14[64];              /* 0x900 */
+
+   uint32_t STATS_CTRL;                /* 0xa00 */
+   uint32_t STATS_TIMER_CFG;           /* 0xa04 */
+   uint32_t STATS_TIMER_COUNT;         /* 0xa08 */
+   uint32_t STATS_TOTAL_SLICE;         /* 0xa0c */
+   uint32_t STATS_TOTAL_PACKET;        /* 0xa10 */
+   uint32_t STATS_TOTAL_READ_SLICE;    /* 0xa14 */
+   uint32_t STATS_TOTAL_READ_PACKET;   /* 0xa18 */
+   uint32_t STATS_TOTAL_LATENCY;       /* 0xa1c */
+   uint32_t STATS_MAX_LATENCY;         /* 0xa20 */
+   uint32_t STATS_SLICE_REORDER;       /* 0xa24 */
+   uint32_t STATS_TOTAL_DDR_CMD;       /* 0xa28 */
+   uint32_t STATS_TOTAL_DDR_ACT;       /* 0xa2c */
+   uint32_t STATS_TOTAL_DDR_RDWR;      /* 0xa30 */
+   uint32_t STATS_TOTAL_DDR_WRRD;      /* 0xa34 */
+   uint32_t STATS_TOTAL_MRQ_CHN_FULL;  /* 0xa38 */
+   uint32_t STATS_TOTAL_SELF_REF;      /* 0xa3c */
+   uint32_t STATS_ARB_GRANT_MATCH0;    /* 0xa40 */
+   uint32_t STATS_TOTAL_QUEUE_FULL;    /* 0xa44 */
+   uint32_t STATS_TOTAL_ARB_GRANT;     /* 0xa48 */
+   uint32_t STATS_TOTAL_RATE_OK_GRANT; /* 0xa4c */
+   uint32_t STATS_FILTER_CFG_0;        /* 0xa50 */
+   uint32_t STATS_PROG0_SLICE;         /* 0xa54 */
+   uint32_t STATS_PROG0_PACKET;        /* 0xa58 */
+   uint32_t STATS_PROG0_READ_SLICE;    /* 0xa5c */
+   uint32_t STATS_PROG0_READ_PACKET;   /* 0xa60 */
+   uint32_t STATS_PROG0_LATENCY;       /* 0xa64 */
+   uint32_t STATS_PROG0_MAX_LATENCY;   /* 0xa68 */
+   uint32_t unused15;                  /* 0xa6c */
+   uint32_t STATS_FILTER_CFG_1;        /* 0xa70 */
+   uint32_t STATS_PROG1_SLICE;         /* 0xa74 */
+   uint32_t STATS_PROG1_PACKET;        /* 0xa78 */
+   uint32_t STATS_PROG1_READ_SLICE;    /* 0xa7c */
+   uint32_t STATS_PROG1_READ_PACKET;   /* 0xa80 */
+   uint32_t STATS_PROG1_LATENCY;       /* 0xa84 */
+   uint32_t unused16[2];               /* 0xa88 - 0xa8f */
+   uint32_t STATS_FILTER_CFG_2;        /* 0xa90 */
+   uint32_t STATS_PROG2_SLICE;         /* 0xa94 */
+   uint32_t STATS_PROG2_PACKET;        /* 0xa98 */
+   uint32_t STATS_PROG2_READ_SLICE;    /* 0xa9c */
+   uint32_t STATS_PROG2_READ_PACKET;   /* 0xaa0 */
+   uint32_t STATS_PROG2_LATENCY;       /* 0xaa4 */
+   uint32_t unused17[2];               /* 0xaa8 - 0xaaf */
+   uint32_t STATS_FILTER_CFG_3;        /* 0xab0 */
+   uint32_t STATS_PROG3_SLICE;         /* 0xab4 */
+   uint32_t STATS_PROG3_PACKET;        /* 0xab8 */
+   uint32_t STATS_PROG3_READ_SLICE;    /* 0xabc */
+   uint32_t STATS_PROG3_READ_PACKET;   /* 0xac0 */
+   uint32_t STATS_PROG3_LATENCY;       /* 0xac4 */
+   uint32_t unused18[2];               /* 0xac8 - 0xacf */
+   uint32_t STATS_AXI_BLOCK_CPU_RD;    /* 0xad0 */
+   uint32_t STATS_AXI_BLOCK_CPQ_RD;    /* 0xad4 */
+   uint32_t unused19[10];              /* 0xad8-0xaff */
+
+   uint32_t CAP_CAPTURE_CFG;           /* 0xb00 */
+   uint32_t CAP_TRIGGER_ADDR;          /* 0xb04 */
+   uint32_t CAP_READ_CTRL;             /* 0xb08 */
+   uint32_t unused20;                  /* 0xb0c */
+   uint32_t CAP_CAPTURE_MATCH0;        /* 0xb10 */
+   uint32_t CAP_CAPTURE_MATCH1;        /* 0xb14 */
+   uint32_t CAP_CAPTURE_MATCH2;        /* 0xb18 */
+   uint32_t unused21;                  /* 0xb1c */
+   uint32_t CAP_CAPTURE_MASK0;         /* 0xb20 */
+   uint32_t CAP_CAPTURE_MASK1;         /* 0xb24 */
+   uint32_t CAP_CAPTURE_MASK2;         /* 0xb28 */
+   uint32_t unused22;                  /* 0xb2c */
+   uint32_t CAP_TRIGGER_MATCH0;        /* 0xb30 */
+   uint32_t CAP_TRIGGER_MATCH1;        /* 0xb34 */
+   uint32_t CAP_TRIGGER_MATCH2;        /* 0xb38 */
+   uint32_t unused23;                  /* 0xb3c */
+   uint32_t CAP_TRIGGER_MASK0;         /* 0xb40 */
+   uint32_t CAP_TRIGGER_MASK1;         /* 0xb44 */
+   uint32_t CAP_TRIGGER_MASK2;         /* 0xb48 */
+   uint32_t unused24;                  /* 0xb4c */
+   uint32_t CAP_READ_DATA[8];          /* 0xb50-0xb6f */
+   uint32_t CAP_TRIGGER_STOP_MATCH0;   /* 0xb70 */
+   uint32_t CAP_TRIGGER_STOP_MATCH1;   /* 0xb74 */
+   uint32_t CAP_TRIGGER_STOP_MATCH2;   /* 0xb78 */
+   uint32_t unused25;                  /* 0xb7c */
+   uint32_t CAP_TRIGGER_STOP_MASK0;    /* 0xb80 */
+   uint32_t CAP_TRIGGER_STOP_MASK1;    /* 0xb84 */
+   uint32_t CAP_TRIGGER_STOP_MASK2;    /* 0xb88 */
+   uint32_t unused26[157];             /* 0xb8c-0xdff */
+
+   uint32_t SEC_INTR2_CPU_STATUS;      /* 0xe00 */
+   uint32_t SEC_INTR2_CPU_SET;         /* 0xe04 */
+   uint32_t SEC_INTR2_CPU_CLEAR;       /* 0xe08 */
+   uint32_t SEC_INTR2_CPU_MASK_STATUS; /* 0xe0c */
+   uint32_t SEC_INTR2_CPU_MASK_SET;    /* 0xe10 */
+   uint32_t SEC_INTR2_CPU_MASK_CLEAR;  /* 0xe14 */
+   uint32_t unused27[58];              /* 0xe18-0xeff */
+
+   uint32_t UBUSIF0_PERMCTL;			/* 0xf00 */
+   uint32_t UBUSIF1_PERMCTL;          /* 0xf04 */
+   uint32_t SRAM_REMAP_PERMCTL;       /* 0xf08 */
+   uint32_t AXIWIF_PERMCTL;           /* 0xf0c */
+   uint32_t CHNCFG_PERMCTL;           /* 0xf10 */
+   uint32_t MCCAP_PERMCTL;            /* 0xf14 */
+   uint32_t SCRAM_PERMCTL;            /* 0xf18 */
+   uint32_t RNG_PERMCTL;              /* 0xf1c */
+   uint32_t RNGCHK_PERMCTL;           /* 0xf20 */
+   uint32_t unused28[567];            /* 0xf24-0x17ff */
+
+   SecureRangeCheckers SEC_RANGE_CHK; /* 0x1800-0x18ff */
+   uint32_t unused29[31168];            /* 0x1900-0x200000 */
+
+   DDRPhyControl PhyControl;                    /* 0x20000 */
+   DDRPhyByteLaneControl PhyByteLaneControl[4]; /* 0x20400 - 0x20bff */
+} MEMCControl;
+
+#define MEMC ((volatile MEMCControl * const) MEMC_BASE)
+
+#endif /* _6856_DDR_H */
diff --git a/arch/arm/include/asm/arch-bcm6856/misc.h b/arch/arm/include/asm/arch-bcm6856/misc.h
new file mode 100644
index 0000000000..16475512ae
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6856/misc.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6856_MISC_H
+#define _6856_MISC_H
+/*
+ * Gpio Controller
+ */
+typedef struct GpioControl {
+        uint32_t GPIODir[8];             /* 0x00-0x1f */
+        uint32_t GPIOio[8];              /* 0x20-0x3f */
+        uint32_t PadCtrl;                 /* 0x40 */
+        uint32_t SpiSlaveCfg;             /* 0x44 */
+        uint32_t TestControl;             /* 0x48 */
+        uint32_t TestPortBlockEnMSB;      /* 0x4c */
+        uint32_t TestPortBlockEnLSB;      /* 0x50 */
+        uint32_t TestPortBlockDataMSB;    /* 0x54 */
+        uint32_t TestPortBlockDataLSB;    /* 0x58 */
+#define PINMUX_DATA_SHIFT       12
+#define PINMUX_0                0
+#define PINMUX_1                1
+#define PINMUX_2                2
+#define PINMUX_3                3
+#define PINMUX_4                4
+#define PINMUX_5                5
+#define PINMUX_6                6
+#define PINMUX_7                7
+        uint32_t TestPortCmd;             /* 0x5c */
+#define LOAD_MUX_REG_CMD        0x21
+#define LOAD_PAD_CTRL_CMD       0x22
+        uint32_t DiagReadBack;            /* 0x60 */
+        uint32_t DiagReadBackHi;          /* 0x64 */
+        uint32_t GeneralPurpose;          /* 0x68 */
+        uint32_t spare[3];
+} GpioControl;
+
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+/* Number to mask conversion macro used for GPIODir and GPIOio */
+#define GPIO_NUM_MAX                84 /* accoring to pinmuxing table */
+#define GPIO_NUM_TO_ARRAY_IDX(X)	(((X & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? (((X & BP_GPIO_NUM_MASK) >> 5) & 0x0f) : (0))
+#define GPIO_NUM_TO_MASK(X)         (((X & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? (1 << ((X & BP_GPIO_NUM_MASK) & 0x1f)) : (0))
+#define GPIO_NUM_TO_ARRAY_SHIFT(X)  (((X) & BP_GPIO_NUM_MASK) & 0x1f)
+
+/*
+** Misc Register Set Definitions.
+*/
+
+typedef struct Misc {
+    uint32_t  miscStrapBus;                       /* 0x00 */
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           5
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOTROM_BOOT_N           (0x1 << 11)
+
+    uint32_t  miscStrapOverride;                  /* 0x04 */
+    uint32_t  miscMaskUBUSErr;                    /* 0x08 */
+    uint32_t  miscPeriphCtrl;                     /* 0x0c */
+    uint32_t  miscSPImasterCtrl;                  /* 0x10 */
+    uint32_t  miscDierevid;                       /* 0x14 */
+    uint32_t  miscPeriphMiscCtrl;                 /* 0x18 */
+    uint32_t  miscPeriphMiscStat;                 /* 0x1c */
+    uint32_t  miscMbox0_data;                     /* 0x20 */
+    uint32_t  miscMbox1_data;                     /* 0x24 */
+    uint32_t  miscMbox2_data;                     /* 0x28 */
+    uint32_t  miscMbox3_data;                     /* 0x2c */
+    uint32_t  miscMbox_ctrl;                      /* 0x30 */
+    uint32_t  miscSoftResetB;                     /* 0x34 */
+    uint32_t  miscSpare0;                         /* 0x38 */
+    uint32_t  miscSWdebugNW[2];                   /* 0x3c-0x40 */
+    uint32_t  miscWDenReset;                      /* 0x44 */
+} Misc;
+
+#define MISC_BASE          0xff802600
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6856/otp.h b/arch/arm/include/asm/arch-bcm6856/otp.h
new file mode 100644
index 0000000000..82a45b6d52
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6856/otp.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+#ifndef _6856_OTP_H
+#define _6856_OTP_H
+
+
+#define JTAG_OTP_BASE    0xff802800
+
+/* row 8 */
+#define OTP_CPU_CORE_CFG_ROW            8
+#define OTP_CPU_CORE_CFG_SHIFT          28
+#define OTP_CPU_CORE_CFG_MASK           0x7
+
+/* row 9 */
+#define OTP_CPU_CLOCK_FREQ_ROW          9
+#define OTP_CPU_CLOCK_FREQ_SHIFT        0
+#define OTP_CPU_CLOCK_FREQ_MASK         0x7
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          7
+
+/* row 23 */
+#define OTP_CUST_MFG_MRKTID_ROW                 23
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_CPU_CLOCK_FREQ, OTP_CPU_CLOCK_FREQ_ROW, OTP_CPU_CLOCK_FREQ_MASK, OTP_CPU_CLOCK_FREQ_SHIFT, 1},				\
+	{OTP_MAP_CPU_CORE_CFG, OTP_CPU_CORE_CFG_ROW, OTP_CPU_CORE_CFG_MASK, OTP_CPU_CORE_CFG_SHIFT, 1},				\
+	}
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6856/pmc.h b/arch/arm/include/asm/arch-bcm6856/pmc.h
new file mode 100644
index 0000000000..eb112bb424
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6856/pmc.h
@@ -0,0 +1,361 @@
+#ifndef PMC_H
+#define PMC_H 
+
+/*
+ * Power Management Control
+ */
+typedef struct PmcCtrlReg {
+	uint32_t gpTmr0Ctl;           /* 0x018 */
+	uint32_t gpTmr0Cnt;           /* 0x01c */
+	uint32_t gpTmr1Ctl;           /* 0x020 */
+	uint32_t gpTmr1Cnt;           /* 0x024 */
+	uint32_t hostMboxIn;          /* 0x028 */
+	uint32_t hostMboxOut;         /* 0x02c */
+	uint32_t reserved[4];         /* 0x030 */
+	uint32_t dmaCtrl;             /* 0x040 */
+	uint32_t dmaStatus;           /* 0x044 */
+	uint32_t dma0_3FifoStatus;    /* 0x048 */
+	uint32_t reserved1[4];	    /* 0x04c */
+	uint32_t diagControl;         /* 0x05c */
+	uint32_t diagHigh;            /* 0x060 */
+	uint32_t diagLow;             /* 0x064 */
+	uint32_t reserved8;           /* 0x068 */
+	uint32_t addr1WndwMask;       /* 0x06c */
+	uint32_t addr1WndwBaseIn;     /* 0x070 */
+	uint32_t addr1WndwBaseOut;    /* 0x074 */
+	uint32_t addr2WndwMask;       /* 0x078 */
+	uint32_t addr2WndwBaseIn;     /* 0x07c */
+	uint32_t addr2WndwBaseOut;    /* 0x080 */
+	uint32_t scratch;             /* 0x084 */
+	uint32_t reserved9;           /* 0x088 */
+	uint32_t softResets;          /* 0x08c */
+	uint32_t reserved2;           /* 0x090 */
+	uint32_t m4keCoreStatus;      /* 0x094 */
+	uint32_t reserved3;           /* 0x098 */
+	uint32_t ubSlaveTimeout;      /* 0x09c */
+	uint32_t diagEn;              /* 0x0a0 */
+	uint32_t devTimeout;          /* 0x0a4 */
+	uint32_t ubusErrorOutMask;    /* 0x0a8 */
+	uint32_t diagCaptStopMask;    /* 0x0ac */
+	uint32_t revId;               /* 0x0b0 */
+	uint32_t gpTmr2Ctl;           /* 0x0b4 */
+	uint32_t gpTmr2Cnt;           /* 0x0b8 */
+	uint32_t reserved4[2];        /* 0x0bc */
+	uint32_t diagCtrl;            /* 0x0c4 */
+	uint32_t diagStat;            /* 0x0c8 */
+	uint32_t diagMask;            /* 0x0cc */
+	uint32_t diagRslt;            /* 0x0d0 */
+	uint32_t diagCmp;             /* 0x0d4 */
+	uint32_t diagCapt;            /* 0x0d8 */    
+	uint32_t diagCnt;             /* 0x0dc */
+	uint32_t diagEdgeCnt;         /* 0x0e0 */
+	uint32_t reserved5[4];	    /* 0x0e4 */
+	uint32_t smisc_bus_config;    /* 0x0f4 */
+	uint32_t lfsr;                /* 0x0f8 */
+    uint32_t dqm_pac_lock;        /* 0x0fc */
+    uint32_t l1_irq_4ke_mask;     /* 0x100 */
+    uint32_t l1_irq_4ke_status;   /* 0x104 */
+    uint32_t l1_irq_mips_mask;    /* 0x108 */
+    uint32_t l1_irq_mips_status;  /* 0x10c */
+    uint32_t l1_irq_mips1_mask;   /* 0x110 */
+    uint32_t reserved6[3];        /* 0x114 */
+    uint32_t l2_irq_gp_mask;      /* 0x120 */
+    uint32_t l2_irq_gp_status;    /* 0x124 */
+    uint32_t l2_irq_gp_set;       /* 0x128 */
+    uint32_t reserved7;           /* 0x12c */
+    uint32_t gp_in_irq_mask;      /* 0x130 */
+    uint32_t gp_in_irq_status;    /* 0x134 */
+    uint32_t gp_in_irq_set;       /* 0x138 */
+    uint32_t gp_in_irq_sense;     /* 0x13c */
+    uint32_t gp_in;               /* 0x140 */
+    uint32_t gp_out;              /* 0x144 */
+} PmcCtrlReg;
+
+typedef struct PmcDmaReg {
+	/* 0x00 */
+	uint32_t src;
+	uint32_t dest;
+	uint32_t cmdList;
+	uint32_t lenCtl;
+	/* 0x10 */
+	uint32_t rsltSrc;
+	uint32_t rsltDest;
+	uint32_t rsltHcs;
+	uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+	/* 0x00 */
+	uint32_t bufSize;
+	uint32_t bufBase;
+	uint32_t idx2ptrIdx;
+	uint32_t idx2ptrPtr;
+	/* 0x10 */
+	uint32_t unused[2];
+	uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+	uint32_t freqScalarCtrl; /* 0x3c */
+	uint32_t freqScalarMask; /* 0x40 */
+} PmcPerfPowReg;
+
+typedef struct PmcDQMPac {
+    uint32_t dqmPac[32];
+} PmcDQMPac;
+
+typedef struct PmcDQMReg {
+	uint32_t cfg;                     /* 0x1c00 */
+	uint32_t _4keLowWtmkIrqMask;      /* 0x1c04 */
+	uint32_t mipsLowWtmkIrqMask;      /* 0x1c08 */
+	uint32_t lowWtmkIrqMask;          /* 0x1c0c */
+	uint32_t _4keNotEmptyIrqMask;     /* 0x1c10 */
+	uint32_t mipsNotEmptyIrqMask;     /* 0x1c14 */
+	uint32_t notEmptyIrqSts;          /* 0x1c18 */
+	uint32_t queueRst;                /* 0x1c1c */
+	uint32_t notEmptySts;             /* 0x1c20 */
+	uint32_t nextAvailMask;           /* 0x1c24 */
+	uint32_t nextAvailQueue;          /* 0x1c28 */
+	uint32_t mips1LowWtmkIrqMask;     /* 0x1c2c */
+	uint32_t mips1NotEmptyIrqMask;    /* 0x1c30 */
+	uint32_t autoSrcPidInsert;        /* 0x1c34 */
+    uint32_t timerIrqStatus;          /* 0x1c38 */
+    uint32_t timerStatus;             /* 0x1c3c */
+    uint32_t _4keTimerIrqMask;        /* 0x1c40 */
+    uint32_t mipsTimerIrqMask;        /* 0x1c44 */
+    uint32_t mips1TimerIrqMask;       /* 0x1c48 */
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+	uint32_t cntr[10];
+	uint32_t unused[6];	/* 0x28-0x3f */
+	uint32_t cntrIrqMask;
+	uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+	uint32_t size;
+	uint32_t cfga;
+	uint32_t cfgb;
+	uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+	uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+	uint32_t qNumFull[32];
+	uint32_t qNumEmpty[32];
+	uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+typedef struct PMSSBMasterControl {
+    uint32_t control;     /* 0x0060 */
+    uint32_t wr_data;      /* 0x0064 */
+    uint32_t rd_data;      /* 0x0068 */
+    uint32_t status;      /* 0x006c */
+} PMSSBMasterControl;
+
+#define SWR_FIRST 0
+#define SWR_LAST 4
+#define SWR_READ_CMD_P 0xB800
+#define SWR_WR_CMD_P   0xB400
+#define SWR_EN         0x1000
+#define SET_ADDR(ps, reg)  (((ps) << 5 | ((reg) & 0x1f)) & 0x2ff)
+
+#define SR_TEST(x)  {\
+                     int num;\
+                     for(num=1000;(((PROCMON->SSBMaster.control) & 0x8000) && (num > 0)) ; num--) ;\
+                         if(!num) \
+                         {\
+                             printf("Error num %d timeout num = %d!!!", (x),  num);\
+                         }\
+}
+
+
+typedef struct PmmReg {
+    uint32_t memPowerCtrl;            /* 0x0000 */
+    uint32_t regSecurityConfig;       /* 0x0004 */
+} PmmReg;
+
+typedef struct keyholeReg {
+    uint32_t ctrlSts;
+    uint32_t wrData;
+    uint32_t mutex;
+    uint32_t rdData;
+} keyholeReg;
+
+typedef struct PmbBus {
+    uint32_t config;          /* 0x0100 */
+    uint32_t arbiter;         /* 0x0104 */
+    uint32_t timeout;         /* 0x0108 */
+    uint32_t unused1;         /* 0x010c */
+    keyholeReg keyhole[4];  /* 0x0110-0x014f */
+    uint32_t unused2[44];     /* 0x0150-0x01ff */
+    uint32_t map[64];         /* 0x0200-0x02ff */ 
+}PmbBus;
+
+typedef struct  CoreCtrl {
+    uint32_t  coreEnable;         /* 0x0400 */
+    uint32_t  autoresetControl;   /* 0x0404 */
+    uint32_t  coreIdle;           /* 0x0408 */
+    uint32_t  coreResetCause;     /* 0x040c */
+    uint32_t  memPwrDownCtrl0;    /* 0x0410 */
+    uint32_t  memPwrDownSts0;     /* 0x0414 */
+    uint32_t  memPwrDownCtrl1;    /* 0x0418 */
+    uint32_t  memPwrDownSts1;     /* 0x041c */
+    uint32_t  sysFlg0Status;      /* 0x0420 */
+    uint32_t  sysFlg0Set;         /* 0x0424 */
+    uint32_t  sysFlg0Clear;       /* 0x0428 */
+    uint32_t  unused1;            /* 0x042c */
+    uint32_t  usrFlg0Status;      /* 0x0430 */
+    uint32_t  usrFlg0Set;         /* 0x0434 */
+    uint32_t  usrFlg0Clear;       /* 0x0438 */
+    uint32_t  unused2;            /* 0x043c */
+    uint32_t  subsystemRev;       /* 0x0440 */
+    uint32_t  resetVector;        /* 0x0444 */
+} CoreCtrl;
+
+typedef struct  CoreState {
+    uint32_t  sysMbx[8];          /* 0x0480 */
+    uint32_t  usrMbx[8];          /* 0x04a0 */
+    uint32_t  sysMtx[4];          /* 0x04c0 */
+    uint32_t  usrMtx[8];          /* 0x04d0 */
+} CoreState;
+
+typedef struct  CoreIntr {
+    uint32_t  irqStatus;          /* 0x0500 */
+    uint32_t  irqSet;             /* 0x0504 */
+    uint32_t  irqClear;           /* 0x0508 */
+    uint32_t  unused1;            /* 0x050c */
+    uint32_t  srqStatus;          /* 0x0510 */
+    uint32_t  srqSet;             /* 0x0514 */
+    uint32_t  srqClear;           /* 0x0518 */
+    uint32_t  unused2;            /* 0x051c */
+    uint32_t  drqStatus;          /* 0x0520 */
+    uint32_t  drqSet;             /* 0x0524 */
+    uint32_t  drqClear;           /* 0x0528 */
+    uint32_t  unused3;            /* 0x052c */
+    uint32_t  frqStatus;          /* 0x0530 */
+    uint32_t  frqSet;             /* 0x0534 */
+    uint32_t  frqClear;           /* 0x0538 */
+    uint32_t  unused4;            /* 0x053c */
+    uint32_t  hostIrqLatched;     /* 0x0540 */
+    uint32_t  hostIrqSet;         /* 0x0544 */
+    uint32_t  hostIrqClear;       /* 0x0548 */
+    uint32_t  hostIrqEnable;      /* 0x054c */
+    uint32_t  obusFaultStatus;    /* 0x0550 */
+    uint32_t  obusFaultClear;     /* 0x0554 */
+    uint32_t  obusFaultAddr;      /* 0x0558 */
+} CoreIntr;
+
+typedef struct CoreProfile {
+    uint32_t  mutex;              /* 0x0580 */
+    uint32_t  lastConfPcLo;       /* 0x0584 */
+    uint32_t  lastConfPcHi;       /* 0x0588 */
+    uint32_t  lastPcLo;           /* 0x058c */
+    uint32_t  lastPcHi;           /* 0x0590 */
+    uint32_t  braTargetPc0Lo;     /* 0x0594 */
+    uint32_t  braTargetPc0Hi;     /* 0x0598 */
+    uint32_t  braTargetPc1Lo;     /* 0x059c */
+    uint32_t  braTargetPc1Hi;     /* 0x05a0 */
+    uint32_t  braTargetPc2Lo;     /* 0x05a4 */
+    uint32_t  braTargetPc2Hi;     /* 0x05a8 */
+    uint32_t  braTargetPc3Lo;     /* 0x05ac */
+    uint32_t  braTargetPc3Hi;     /* 0x05b0 */
+    uint32_t  unused[3];          /* 0x05b4-0x05bf */
+    uint32_t  profSampleW[4];     /* 0x05c0 */
+} CoreProfile;
+
+typedef struct MaestroMisc {
+    CoreCtrl coreCtrl;          /* 0x0400 */
+    uint32_t   unused1[14];       /* 0x0448-0x047f */
+    CoreState coreState;        /* 0x0480 */
+    uint32_t   unused2[4];        /* 0x04f0-0x04ff */
+    CoreIntr interrupt;         /* 0x0500 */
+    uint32_t   unused3[9];        /* 0x055c-0x057f */
+    CoreProfile profile;        /* 0x0580 */
+} MaestroMisc;
+
+typedef struct Pmc {
+	uint32_t baseReserved;		        /* 0x0000 */
+	uint32_t unused0[1029];
+	PmcCtrlReg ctrl;		            /* 0x1018 */
+
+	uint32_t unused1[174];	            /* 0x1148-0x13ff */
+
+	PmcTokenReg token;		            /* 0x1400 */
+	uint32_t unused2[136];		        /* 0x141c-0x163b */
+
+	PmcPerfPowReg perfPower;	        /* 0x163c */
+	uint32_t unused3[175];		        /* 0x1644-0x18ff */
+
+	PmcCntReg hwCounter;		        /* 0x1900 */
+	uint32_t unused4[110];		        /* 0x1948-0x1aff */
+
+    PmcDQMPac dqmPac;                   /* 0x1b00 */
+    uint32_t unused5[32];                 /* 0x1b80-0x1bff */
+
+	PmcDQMReg dqm;			            /* 0x1c00 */
+	uint32_t unused6[749];		        /* 0x1c4c-0x27ff */
+	
+    uint32_t qStatus[32];		            /* 0x2800 */
+	uint32_t unused7[480];	            /* 0x2880-0x2fff */
+	
+    PmcDqmQMibReg qMib;		            /* 0x3000 */
+	uint32_t unused8[928];	            /* 0x3180-0x3fff */
+
+	PmcDqmQCtrlReg dqmQCtrl[8]; 	    /* 0x4000 */
+	uint32_t unused9[992];                /* 0x4080-0x4fff */
+
+	PmcDqmQDataReg dqmQData[8]; 	    /* 0x5000 */
+} Pmc;
+#define PMC_BASE         0xffb00000
+#define PMC ((volatile Pmc * const) PMC_BASE)
+    
+typedef struct Procmon {
+    PmmReg  pmm;                        /* 0x20000 */
+    uint32_t unused11[22];                /* 0x20008-0x2005f */
+
+    PMSSBMasterControl SSBMaster;            /* 0x20060 */
+    uint32_t unused12[36];                /* 0x20070-0x200ff */
+
+    PmbBus pmb;                         /* 0x20100 */
+    uint32_t unused13[64];                /* 0x20300-0x203ff */
+
+    MaestroMisc maestroReg;             /* 0x20400 */
+} Procmon;
+#define PROC_MON_BASE        0xffb20000
+#define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
+
+typedef struct
+{
+    uint32_t  control;
+#define PMC_PMBM_START		            (1 << 31)
+#define PMC_PMBM_TIMEOUT	            (1 << 30)
+#define PMC_PMBM_SLAVE_ERR	            (1 << 29)
+#define PMC_PMBM_BUSY		            (1 << 28)
+#define PMC_PMBM_BUS_SHIFT              (20)
+#define PMC_PMBM_Read		            (0 << 24)
+#define PMC_PMBM_Write		            (1 << 24)
+    uint32_t  wr_data;
+    uint32_t  mutex;
+    uint32_t  rd_data;
+} PMB_keyhole_reg;
+
+typedef struct PMBMaster {
+    uint32_t config;
+#define PMB_NUM_REGS_SHIFT (20)
+#define PMB_NUM_REGS_MASK  (0x3ff)
+    uint32_t arbitger;
+    uint32_t timeout;
+    uint32_t reserved;
+    PMB_keyhole_reg keyhole[4];
+    uint32_t reserved1[44];
+	uint32_t map[64];
+} PMBMaster;
+#define PMB_BASE             0xffb20100
+#define PMB ((volatile PMBMaster * const) PMB_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6856/pmc_addr.h b/arch/arm/include/asm/arch-bcm6856/pmc_addr.h
new file mode 100644
index 0000000000..50a31dae80
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6856/pmc_addr.h
@@ -0,0 +1,102 @@
+#define PMB_BUS_MAX              2
+#define PMB_BUS_ID_SHIFT         12
+
+#define PMB_BUS_PERIPH           0
+#define PMB_ADDR_PERIPH          (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH         4
+
+#define PMB_BUS_MEMC             0
+#define PMB_ADDR_MEMC            (1 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC           1
+
+#define PMB_BUS_PVTMON           0
+#define PMB_ADDR_PVTMON          (2 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON         0
+
+#define PMB_BUS_CHIP_CLKRST      0
+#define PMB_ADDR_CHIP_CLKRST     (3 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST    0
+
+#define PMB_BUS_USB30_2X         0
+#define PMB_ADDR_USB30_2X        (4 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB30_2X       4
+
+#define PMB_BUS_SYSPLL           0
+#define PMB_ADDR_SYSPLL          (5 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL         0
+
+#define PMB_BUS_RDPPLL           0
+#define PMB_ADDR_RDPPLL          (6 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_RDPPLL         0
+
+#define PMB_BUS_PCIE0            1
+#define PMB_ADDR_PCIE0           (7 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0          1
+
+#define PMB_BUS_PCIE1            1
+#define PMB_ADDR_PCIE1           (8 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1          1
+
+#define PMB_BUS_PCIE2            1
+#define PMB_ADDR_PCIE2           (9 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE2          1
+
+#define PMB_BUS_XRDP             1
+#define PMB_ADDR_XRDP            (10 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP           3
+
+#define PMB_BUS_XRDP_RC0         1
+#define PMB_ADDR_XRDP_RC0        (11 | PMB_BUS_XRDP_RC0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC0       1
+
+#define PMB_BUS_XRDP_RC1         1
+#define PMB_ADDR_XRDP_RC1        (12 | PMB_BUS_XRDP_RC1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC1       1
+
+#define PMB_BUS_XRDP_RC2         1
+#define PMB_ADDR_XRDP_RC2        (13 | PMB_BUS_XRDP_RC2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC2       1
+
+#define PMB_BUS_XRDP_RC3         1
+#define PMB_ADDR_XRDP_RC3        (14 | PMB_BUS_XRDP_RC3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC3       1
+
+#define PMB_BUS_XRDP_RC4         1
+#define PMB_ADDR_XRDP_RC4        (15 | PMB_BUS_XRDP_RC4 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC4       1
+
+#define PMB_BUS_XRDP_RC5         1
+#define PMB_ADDR_XRDP_RC5        (16 | PMB_BUS_XRDP_RC5 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC5       1
+
+#define PMB_BUS_XRDP_RC6         1
+#define PMB_ADDR_XRDP_RC6        (17 | PMB_BUS_XRDP_RC6 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC6       1
+
+#define PMB_BUS_XRDP_RC7         1
+#define PMB_ADDR_XRDP_RC7        (18 | PMB_BUS_XRDP_RC7 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC7       1
+
+#define PMB_BUS_WAN              1
+#define PMB_ADDR_WAN             (19 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WAN            6
+
+#define PMB_BUS_ORION_CPU0         0
+#define PMB_ADDR_ORION_CPU0        (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0       1
+
+#define PMB_BUS_ORION_CPU1         0
+#define PMB_ADDR_ORION_CPU1        (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1       1
+
+#define PMB_BUS_ORION_NONCPU       0
+#define PMB_ADDR_ORION_NONCPU      (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU     1
+
+#define PMB_BUS_BIU_PLL            0
+#define PMB_ADDR_BIU_PLL           (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL          1
+
+#define PMB_BUS_BIU_BPCM           0
+#define PMB_ADDR_BIU_BPCM          (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM         1
diff --git a/arch/arm/include/asm/arch-bcm6856/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm6856/pmc_drv_cfg.h
new file mode 100644
index 0000000000..2fcca35220
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6856/pmc_drv_cfg.h
@@ -0,0 +1,38 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_3_X
+#define PMC_IMPL_3_1
+
+#define PMC_UCBID 1
+#define PMC_RAM_BOOT 1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm6856/rng.h b/arch/arm/include/asm/arch-bcm6856/rng.h
new file mode 100644
index 0000000000..415958d135
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6856/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6858_RNG_H
+#define _6858_RNG_H
+
+#define RNG_BASE    0xff800b80
+
+typedef struct Rng {
+	uint32_t ctrl0;		/* 0x00 */
+	uint32_t rngSoftReset;	/* 0x04 */
+	uint32_t rbgSoftReset;	/* 0x08 */
+	uint32_t totalBitCnt;	/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;		/* 0x14 */
+	uint32_t intStatus;	/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL       (0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL       (0x1<<2)
+	uint32_t intEn;		/* 0x1c */
+	uint32_t rngFifoData;	/* 0x20 */
+	uint32_t fifoCnt;	/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS           0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS           0x33
+	uint32_t perm;		/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6856/ubus4.h b/arch/arm/include/asm/arch-bcm6856/ubus4.h
new file mode 100644
index 0000000000..f36f41b84d
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6856/ubus4.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _6856_UBUS4_H
+#define _6856_UBUS4_H
+
+#define UBUS_MAPPED_BASE    0x83000080
+
+typedef struct Ubus4ClkCtrlCfgRegs {
+    uint32_t ClockCtrl;
+#define UBUS4_CLK_CTRL_EN_SHIFT    (0)
+#define UBUS4_CLK_CTRL_EN_MASK     (0x1 << UBUS4_CLK_CTRL_EN_SHIFT)
+#define UBUS4_CLK_BYPASS_SHIFT     (2)
+#define UBUS4_CLK_BYPASS_MASK      (0x1 << UBUS4_CLK_BYPASS_SHIFT)
+#define UBUS4_MIN_CLK_SEL_SHIFT    (4)
+#define UBUS4_MIN_CLK_SEL_MASK     (0x7 << UBUS4_MIN_CLK_SEL_SHIFT)
+#define UBUS4_MID_CLK_SEL_SHIFT    (8)
+#define UBUS4_MID_CLK_SEL_MASK     (0x7 << UBUS4_MID_CLK_SEL_SHIFT)
+    uint32_t reserved0[3];
+    uint32_t Min2Mid_threshhold;
+    uint32_t Mid2Max_threshhold;
+    uint32_t Mid2Min_threshhold;
+    uint32_t Max2Mid_threshhold;
+    uint32_t ClkIntoMin;
+    uint32_t ClkIntoMid;
+    uint32_t ClkIntoMax;
+    uint32_t reserved1;
+    uint32_t ClkMinTime;
+    uint32_t ClkMidTime;
+    uint32_t ClkMaxTime;
+} Ubus4ClkCtrlCfgRegs;
+
+#define UBUS4CLK ((volatile Ubus4ClkCtrlCfgRegs * const) UBUS_MAPPED_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6858/BPCM.h b/arch/arm/include/asm/arch-bcm6858/BPCM.h
new file mode 100644
index 0000000000..d18c44c9fb
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6858/BPCM.h
@@ -0,0 +1,762 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t sw_strap:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+// types of PMB devices
+enum {
+	kPMB_BPCM = 0,
+	kPMB_MIPS_PLL = 1,
+	kPMB_GEN_PLL = 2,
+	kPMB_LC_PLL = 3,
+	// 4..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	struct {
+		uint32_t wan_main_rst_n:1;
+		uint32_t wan_top_bb_rst_n:1;
+		uint32_t epon_core_rst_n:1;
+		uint32_t epon_rx_rclk16_sw_reset_n:1;
+		uint32_t epon_rx_rbc125_sw_reset_n:1;
+		uint32_t epon_tx_tclk16_sw_reset_n:1;
+		uint32_t epon_tx_clk125_sw_reset_n:1;
+		uint32_t gpon_main_rst_n:1;
+		uint32_t gpon_rx_rst_n:1;
+		uint32_t gpon_tx_rst_n:1;
+		uint32_t gpon_8khz_rst_n:1;
+		uint32_t ngpon_main_rst_n:1;
+		uint32_t ngpon_rx_rst_n:1;
+		uint32_t ngpon_tx_rst_n:1;
+		uint32_t ngpon_8khz_rst_n:1;
+		uint32_t gpon_nco_rst_n:1;
+		uint32_t apm_rst_n:1;
+		uint32_t reserved:15;
+	} Bits_Wantop;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu_reset_n:8;	// 07:00    R/W
+		uint32_t c0l2_reset:1;	// 08:08    R/W
+		uint32_t c1l2_reset:1;	// 09:09    R/W
+		uint32_t reserved0:6;	// 15:10    R/O
+		uint32_t cpu_bpcm_init_on:8;	// 23:16    R/W
+		uint32_t c0l2_bpcm_init_on:1;	// 24:24    R/W
+		uint32_t c1l2_bpcm_init_on:1;	// 25:25    R/W
+		uint32_t ubus_sr:1;	// 26:26    R/W
+		uint32_t cci_sr:1;	// 27:27    R/W
+		uint32_t webcores_sr:1;	// 28:28    R/W
+		uint32_t hw_done:1;	// 29:29    R/O
+		uint32_t sw_done:1;	// 30:30    R/W
+		uint32_t start:1;	// 31:31    R/W
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t reserved0:2;	// 11:10
+		uint32_t ndiv_frac:20;	// 31:12    
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECNDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t reserved0:12;	// 15:04
+		uint32_t mdiv0:8;	// 23:16
+		uint32_t mdiv1:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECPDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv2:8;	// 07:00
+		uint32_t mdiv3:8;	// 15:08
+		uint32_t mdiv4:8;	// 23:16
+		uint32_t mdiv5:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECCH25_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	BPCM_ZONE_N_FREQ_SCALAR_CONTROL freq_scalar_control;
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	BPCM_SGPHY_CNTL sgphy_cntl;	// offset = 0x38, actual offset = 14
+	BPCM_SGPHY_STATUS sgphy_status;	// offset = 0x3c, actual offset = 15
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	BPCM_GLOBAL_CNTL global_control;	// offset = 0x2c, actual offset = 11
+	BPCM_MISC_CONTROL misc_control;	// offset = 0x30, actual offset = 12
+	BPCM_MISC_CONTROL2 misc_control2;	// offset = 0x34, actual offset = 13
+	uint32_t rvrsd[2];
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} BPCM_VDSL_REGS;		// total offset space = 4096
+
+#define BPCMVDSLOffset(reg)	offsetof(BPCM_VDSL_REGS,reg)
+#define BPCMVDSLRegOffset(reg)	(BPCMVDSLOffset(reg) >> 2)
+
+// ARM BPCM addresses as used by 63138/63148 and possibly others (28nm)
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	BPCM_PWD_ACCUM_CONTROL pwd_accum_control;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved;	// offset = 0x2c, actual offset = 11
+	ARM_CONTROL_REG arm_control;	// offset = 0x30, actual offset = 12
+	uint32_t biu_clk_control0;	// offset = 0x34, actual offset = 13
+	uint32_t reserved1[2];	// offset = 0x38, actual offset = 13..14
+	BPCM_ZONE zones[1020];	// offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
+} ARM_BPCM_REGS;
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	PLL_DECNDIV_REG decndiv;	// offset = 0x44, actual offset = 0x11
+	PLL_DECPDIV_REG decpdiv;	// offset = 0x48, actual offset = 0x12
+	PLL_DECCH25_REG decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	uint32_t reserved0;	// offset = 0x24, actual offset = 9
+	BPCM_SR_CONTROL sr_control;	// offset = 0x28, actual offset = 10
+	uint32_t reserved1;	// offset = 0x2c, actual offset = 11
+	uint32_t clkrst_cfg;	// offset = 0x30, actual offset = 12
+	uint32_t clkrst_control;	// offset = 0x34, actual offset = 13
+	uint32_t xtal_control;	// offset = 0x38, actual offset = 14
+	uint32_t clkrst_stat;	// offset = 0x3c, actual offset = 15
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6858/brom.h b/arch/arm/include/asm/arch-bcm6858/brom.h
new file mode 100644
index 0000000000..c3bf26c1e9
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6858/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6858_BROM_H
+#define _6858_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6858/cpu.h b/arch/arm/include/asm/arch-bcm6858/cpu.h
new file mode 100644
index 0000000000..208aeb7500
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6858/cpu.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6858_CPU_H
+#define _6858_CPU_H
+
+#define BIUCFG_BASE       0x81060000
+#define CCI400_BASE       0x81090000
+
+typedef struct CCI400_SlaveIntf {
+#define SNOOP_CTRL_ENABLE_SNOOP            0x1
+    uint32_t snoop_ctrl;        /* 0x0 */
+    uint32_t share_ovr;         /* 0x4 */
+    uint32_t rsvd1[62];         /* 0x8 - 0xff */
+    uint32_t arqos_ovr;         /* 0x100 */
+    uint32_t awqos_ovr;         /* 0x104 */
+    uint32_t rsvd2[2];          /* 0x108 - 0x10f */
+    uint32_t qos_max_ot;        /* 0x110 */
+    uint32_t rsvd3[955];        /* 0x114 - 0xfff */
+}CCI400_SlaveIntf;
+
+
+typedef struct CCI400 {
+    uint32_t ctrl_ovr;        /* 0x0 */
+    uint32_t spec_ctrl;       /* 0x4 */
+#define SECURE_ACCESS_UNSECURE_ENABLE      0x1
+    uint32_t secr_acc;        /* 0x8 */
+    uint32_t status;          /* 0xc */
+    uint32_t impr_err;        /* 0x10 */
+    uint32_t rdvd[59];        /* 0x14 */
+    uint32_t pmu_ctrl;        /* 0x100 */
+    uint32_t rsvd1[959];      /* 0x104 - 0xfff */
+    CCI400_SlaveIntf si[5]; /* 0x1000 - 0x5fff */
+}CCI400;
+
+#define CCI400 ((volatile CCI400 * const) CCI400_BASE)
+
+typedef struct BIUCFG_Access {
+	uint32_t permission;	/* 0x0 */
+	uint32_t sbox;		/* 0x4 */
+	uint32_t cpu_defeature;	/* 0x8 */
+	uint32_t dbg_security;	/* 0xc */
+	uint32_t rsvd1[32];	/* 0x10 - 0x8f */
+	uint64_t violation[2];	/* 0x90 - 0x9f */
+	uint32_t ts_access[2];	/* 0xa0 - 0xa7 */
+	uint32_t rsvd2[22];	/* 0xa8 - 0xff */
+} BIUCFG_Access;
+
+typedef struct BIUCFG_Cluster {
+	uint32_t permission;	/* 0x0 */
+	uint32_t config;	/* 0x4 */
+	uint32_t status;	/* 0x8 */
+	uint32_t control;	/* 0xc */
+	uint32_t cpucfg;	/* 0x10 */
+	uint32_t dbgrom;	/* 0x14 */
+	uint32_t rsvd1[2];	/* 0x18 - 0x1f */
+	uint32_t rvbar_addr[4];	/* 0x20 - 0x2f */
+	uint32_t rsvd2[52];	/* 0x30 - 0xff */
+} BIUCFG_Cluster;
+
+typedef struct BIUCFG_AuxClkCtrl {
+	uint32_t clk_control;	/* 0x0 */
+	uint32_t clk_ramp;	/* 0x4 */
+	uint32_t clk_pattern;	/* 0x8 */
+	uint32_t rsvd;		/* 0xC */
+} BIUCFG_AuxClkCtrl;
+
+typedef struct BIUCFGux {
+	uint32_t permission;	/* 0 */
+	uint32_t rsvd1[3];	/* 0x04 - 0x0c */
+	BIUCFG_AuxClkCtrl cluster_clkctrl[2];	/* 0x10 - 0x2c */
+	uint32_t rsvd2[52];	/* 0x30 - 0xFF */
+} BIUCFG_Aux;
+
+typedef struct BIUCFG {
+	BIUCFG_Access access;	/* 0x0 - 0xff */
+	BIUCFG_Cluster cluster[1];	/* 0x100 - 0x1ff */
+	uint32_t rsvd1[320];	/* 0x200 - 0x6ff */
+	BIUCFG_Aux aux;		/* 0x700 - 0x7ff */
+	uint32_t rsrvd2[512];	/* 0x800 - 0xfff */
+	uint32_t TSO_CNTCR;	/* 0x1000 */
+	uint32_t rsvd2[2047];	/* 0x1004 - 0x2fff */
+} BIUCFG;
+
+#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6858/ddr.h b/arch/arm/include/asm/arch-bcm6858/ddr.h
new file mode 100644
index 0000000000..ef3a29fa78
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6858/ddr.h
@@ -0,0 +1,606 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6858_DDR_H
+#define _6858_DDR_H
+
+#define MEMC_BASE        0x80180000
+
+typedef struct UBUSInterface {
+	uint32_t CFG;		/* 0x00 */
+	uint32_t ESRCID_CFG;	/* 0x04 */
+#define UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT   0x0
+#define UBUSIF_CFG_WRITE_REPLY_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT)
+#define UBUSIF_CFG_WRITE_BURST_MODE_SHIFT   0x1
+#define UBUSIF_CFG_WRITE_BURST_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_BURST_MODE_SHIFT)
+#define UBUSIF_CFG_INBAND_ERR_MASK_SHIFT    0x2
+#define UBUSIF_CFG_INBAND_ERR_MASK_MASK     (0x1<< UBUSIF_CFG_INBAND_ERR_MASK_SHIFT)
+#define UBUSIF_CFG_OOB_ERR_MASK_SHIFT       0x3
+#define UBUSIF_CFG_OOB_ERR_MASK_MASK        (0x1<< UBUSIF_CFG_OOB_ERR_MASK_SHIFT)
+	uint32_t SRC_QUEUE_CTRL[4];	/* 0x08 - 0x14 */
+	uint32_t REP_ARB_MODE;	/* 0x18 */
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT 0x0
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_MASK  (0x1<<UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT)
+	uint32_t SCRATCH;	/* 0x1c */
+	uint32_t DEBUG_R0;	/* 0x20 */
+	uint32_t unused[7];	/* 0x24-0x3f */
+} UBUSInterface;
+
+typedef struct AXIInterface {
+	uint32_t CFG;		/* 0x00 */
+	uint32_t REP_ARB_MODE;	/* 0x04 */
+	uint32_t SCRATCH;	/* 0x08 */
+	uint32_t ESRCID_CFG;	/* 0x0c */
+	uint32_t SRC_QUEUE_CTL[8];	/* 0x10 */
+	uint32_t debug;		/* 0x30 */
+	uint32_t unused[3];	/* 0x34-0x3f */
+} AXIInterface;
+
+typedef struct EDISEngine {
+	uint32_t REV_ID;	/* 0x00 */
+	uint32_t CTRL_TRIG;	/* 0x04 */
+	uint32_t CTRL_MODE;	/* 0x08 */
+	uint32_t CTRL_SIZE;	/* 0x0c */
+	uint32_t CTRL_ADDR_START;	/* 0x10 */
+	uint32_t CTRL_ADDR_START_EXT;	/* 0x14 */
+	uint32_t CTRL_ADDR_END;	/* 0x18 */
+	uint32_t CTRL_ADDR_END_EXT;	/* 0x1c */
+	uint32_t CTRL_WRITE_MASKS;	/* 0x20 */
+	uint32_t CTRL_INT_ENABLES;	/* 0x24 */
+	uint32_t unused0[6];	/* 0x28-0x3f */
+	uint32_t STAT_MAIN;	/* 0x40 */
+	uint32_t STAT_WORDS_WRITTEN;	/* 0x44 */
+	uint32_t STAT_WORDS_READ;	/* 0x48 */
+	uint32_t STAT_ERROR_COUNT;	/* 0x4c */
+	uint32_t STAT_ERROR_BITS;	/* 0x50 */
+	uint32_t STAT_ADDR_LAST;	/* 0x54 */
+	uint32_t STAT_ADDR_LAST_EXT;	/* 0x58 */
+	uint32_t STAT_CLOCK_CYCLES;	/* 0x5c */
+	uint32_t unused1[7];	/* 0x60-0x7b */
+	uint32_t STAT_DEBUG;	/* 0x7c */
+	uint32_t STAT_DATA_PORT[8];	/* 0x80-0x9c */
+	uint32_t GEN_LFSR_STATE[4];	/* 0xa0-0xac */
+	uint32_t GEN_CLOCK;	/* 0xb0 */
+	uint32_t GEN_PATTERN;	/* 0xb4 */
+	uint32_t unused2[2];	/* 0xb8-0xbf */
+	uint32_t BYTELANE_0_CTRL_LO;	/* 0xc0 */
+	uint32_t BYTELANE_0_CTRL_HI;	/* 0xc4 */
+	uint32_t BYTELANE_1_CTRL_LO;	/* 0xc8 */
+	uint32_t BYTELANE_1_CTRL_HI;	/* 0xcc */
+	uint32_t BYTELANE_2_CTRL_LO;	/* 0xd0 */
+	uint32_t BYTELANE_2_CTRL_HI;	/* 0xd4 */
+	uint32_t BYTELANE_3_CTRL_LO;	/* 0xd8 */
+	uint32_t BYTELANE_3_CTRL_HI;	/* 0xdc */
+	uint32_t BYTELANE_0_STAT_LO;	/* 0xe0 */
+	uint32_t BYTELANE_0_STAT_HI;	/* 0xe4 */
+	uint32_t BYTELANE_1_STAT_LO;	/* 0xe8 */
+	uint32_t BYTELANE_1_STAT_HI;	/* 0xec */
+	uint32_t BYTELANE_2_STAT_LO;	/* 0xf0 */
+	uint32_t BYTELANE_2_STAT_HI;	/* 0xf4 */
+	uint32_t BYTELANE_3_STAT_LO;	/* 0xf8 */
+	uint32_t BYTELANE_3_STAT_HI;	/* 0xfc */
+} EDISEngine;
+
+typedef struct RangeCtrl {
+	uint32_t CTRL;		/* 0x00 */
+	uint32_t UBUS0_PORT;	/* 0x04 */
+	uint32_t UBUS0_PORT_UPPER;	/* 0x08 */
+	uint32_t BASE;		/* 0x0c */
+	uint32_t BASE_UPPER;	/* 0x10 */
+} RangeCtrl;
+
+typedef struct SecureRangeCheckers {
+	uint32_t LOCK;		/* 0x00 */
+	uint32_t LOG_INFO[3];	/* 0x04 - 0x0c */
+	RangeCtrl RANGE_CTRL[8];	/* 0x10 - 0xac */
+	uint32_t unused[20];	/* 0xb0 - 0xff */
+} SecureRangeCheckers;
+
+typedef struct DDRPhyControl {
+	uint32_t PRIMARY_REVISION;	/* 0x00 */
+	uint32_t SECONDARY_REVISION;	/* 0x04 */
+	uint32_t FEATURE;	/* 0x08 */
+	uint32_t PLL_STATUS;	/* 0x0c */
+	uint32_t PLL_CONFIG;	/* 0x10 */
+	uint32_t PLL_CONTROL1;	/* 0x14 */
+	uint32_t PLL_CONTROL2;	/* 0x18 */
+	uint32_t PLL_CONTROL3;	/* 0x1c */
+	uint32_t PLL_DIVIDER;	/* 0x20 */
+	uint32_t PLL_PRE_DIVIDER;	/* 0x24 */
+	uint32_t PLL_SS_EN;	/* 0x28 */
+	uint32_t PLL_SS_CFG;	/* 0x2c */
+	uint32_t AUX_CONTROL;	/* 0x30 */
+	uint32_t IDLE_PAD_CONTROL;	/* 0x34 */
+	uint32_t IDLE_PAD_EN0;	/* 0x38 */
+	uint32_t IDLE_PAD_EN1;	/* 0x3c */
+	uint32_t DRIVE_PAD_CTL;	/* 0x40 */
+	uint32_t DRIVE_PAD_CTL_2T;	/* 0x44 */
+	uint32_t DRIVE_PAD_CTL_2T_A;	/* 0x48 */
+	uint32_t STATIC_PAD_CTL;	/* 0x4c */
+	uint32_t STATIC_PAD_CTL_2T;	/* 0x50 */
+	uint32_t STATIC_PAD_CTL_2T_A;	/* 0x54 */
+	uint32_t RX_TRIM;	/* 0x58 */
+	uint32_t DRAM_CFG;	/* 0x5c */
+	uint32_t DRAM_TIMING2;	/* 0x60 */
+	uint32_t DRAM_TIMING3;	/* 0x64 */
+	uint32_t VDL_REGS[45];	/* 0x68-0x11b */
+	uint32_t UPDATE_VDL;	/* 0x11c */
+	uint32_t UPDATE_VDL_SNOOP1;	/* 0x120 */
+	uint32_t UPDATE_VDL_SNOOP2;	/* 0x124 */
+	uint32_t CMND_REG1;	/* 0x128 */
+	uint32_t CMND_AUX_REG1;	/* 0x12c */
+	uint32_t CMND_REG2;	/* 0x130 */
+	uint32_t CMND_AUX_REG2;	/* 0x134 */
+	uint32_t CMND_REG3;	/* 0x138 */
+	uint32_t CMND_AUX_REG3;	/* 0x13c */
+	uint32_t CMND_REG4;	/* 0x140 */
+	uint32_t CMND_AUX_REG4;	/* 0x144 */
+	uint32_t MODE_REG[8];	/* 0x148-167 */
+	uint32_t ALERT_CLEAR;	/* 0x168 */
+	uint32_t ALERT_STATUS;	/* 0x16c */
+	uint32_t ALERT_DF1;	/* 0x170 */
+	uint32_t WRITE_LEVEL_CTRL;	/* 0x174 */
+	uint32_t WRITE_LEVEL_STATUS;	/* 0x178 */
+	uint32_t READ_EN_CTRL;	/* 0x17c */
+	uint32_t READ_EN_STATUS;	/* 0x180 */
+	uint32_t VIRT_VTT_CTRL;	/* 0x184 */
+	uint32_t VIRT_VTT_STATUS;	/* 0x188 */
+	uint32_t VIRT_VTT_CONNECTION;	/* 0x18c */
+	uint32_t VIRT_VTT_OVERRIDE;	/* 0x190 */
+	uint32_t VREF_DAC_CTRL;	/* 0x194 */
+#define DDRPHY_VREF_DAC_CTRL_PDN_SHIFT             12
+#define DDRPHY_VREF_DAC_CTRL_PDN_MASK              (0xf << DDRPHY_VREF_DAC_CTRL_PDN_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT            6
+#define DDRPHY_VREF_DAC_CTRL_DAC1_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT)
+#define DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT            0
+#define DDRPHY_VREF_DAC_CTRL_DAC0_MASK             (0x3f << DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT)
+	uint32_t STANDBY_CTRL;	/* 0x198 */
+	uint32_t DEBUG_FREEZE_EN;	/* 0x19c */
+	uint32_t DEBUG_MUX_CTRL;	/* 0x1a0 */
+	uint32_t DFI_CTRL;	/* 0x1a4 */
+	uint32_t WRITE_ODT_CTRL;	/* 0x1a8 */
+	uint32_t ABI_PAR_CTRL;	/* 0x1ac */
+	uint32_t ZQ_CAL;	/* 0x1b0 */
+	uint32_t unused6[147];	/* 0x1b4-0x3ff */
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+	uint32_t VDL_CTRL_WR[10];	/* 0x00 - 0x27 */
+	uint32_t VDL_CTRL_RD[22];	/* 0x28 - 0x7f */
+	uint32_t VDL_CLK_CTRL;	/* 0x80 */
+	uint32_t VDL_LDE_CTRL;	/* 0x84 */
+	uint32_t RD_EN_DLY_CYC;	/* 0x88 */
+#define RD_EN_DLY_CYC_CS0_CYCLES_SHIFT      0x0
+#define RD_EN_DLY_CYC_CS0_CYCLES_MASK       (0xf<<RD_EN_DLY_CYC_CS0_CYCLES_SHIFT)
+	uint32_t WR_CHAN_DLY_CYC;	/* 0x8c */
+	uint32_t RD_CTRL;	/* 0x90 */
+	uint32_t RD_FIFO_ADDR;	/* 0x94 */
+	uint32_t RD_FIFO_DATA;	/* 0x98 */
+	uint32_t RD_FIFO_DM_DBI;	/* 0x9c */
+	uint32_t RD_FIFO_STATUS;	/* 0xa0 */
+	uint32_t RD_FIFO_CLR;	/* 0xa4 */
+	uint32_t DYNAMIC_CLK_CTRL;	/* 0xa8 */
+	uint32_t IDLE_PAD_CTRL;	/* 0xac */
+	uint32_t DRIVE_PAD_CTRL;	/* 0xb0 */
+	uint32_t DQSP_DRIVE_PAD_CTRL;	/* 0xb4 */
+	uint32_t DQSN_DRIVE_PAD_CTRL;	/* 0xb8 */
+	uint32_t RD_EN_DRIVE_PAD_CTRL;	/* 0xbc */
+	uint32_t STATIC_PAD_CTRL;	/* 0xc0 */
+	uint32_t DQ_RX_TRIM;	/* 0xc4 */
+	uint32_t MISC_RX_TRIM;	/* 0xc8 */
+	uint32_t DQS_RX_TRIM;	/* 0xcc */
+	uint32_t WR_PREAMBLE_MODE;	/* 0xd0 */
+	uint32_t ODT_CTRL;	/* 0xd4 */
+	uint32_t LDO_CONFIG;	/* 0xd8 */
+	uint32_t CLOCK_ENABLE;	/* 0xdc */
+	uint32_t CLOCK_IDLE;	/* 0xe0 */
+	uint32_t RD_CHAN_FIFO_CLR;	/* 0xe4 */
+	uint32_t BL_SPARE_REG;	/* 0xe8 */
+	uint32_t unused[69];	/* 0xec-0x1ff */
+} DDRPhyByteLaneControl;
+
+typedef struct MEMCControl {
+	uint32_t GLB_VERS;	/* 0x000 */
+	uint32_t GLB_GCFG;	/* 0x004 */
+#define MEMC_GLB_GCFG_DRAM_EN_SHIFT        31
+#define MEMC_GLB_GCFG_DRAM_EN_MASK         (0x1<<MEMC_GLB_GCFG_DRAM_EN_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ_SHIFT      30
+#define MEMC_GLB_GCFG_FORCE_SEQ_MASK       (0x1<<MEMC_GLB_GCFG_FORCE_SEQ_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT     29
+#define MEMC_GLB_GCFG_FORCE_SEQ2_MASK      (1<<MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT)
+#define MEMC_GLB_GCFG_RBF_REORDER_SHIFT    28
+#define MEMC_GLB_GCFG_RBF_REORDER_MASK     (1<<MEMC_GLB_GCFG_RBF_REORDER_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT   24
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_MASK    (0x3<<MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_2X           0x0
+#define MEMC_GLB_GCFG_PHY_DFI_4X           0x1
+#define MEMC_GLB_GCFG_PHY_DFI_8X           0x2
+#define MEMC_GLB_GCFG_DFI_EN_SHIFT         10
+#define MEMC_GLB_GCFG_DFI_EN_MASK          (0x1<<MEMC_GLB_GCFG_DFI_EN_SHIFT)
+#define MEMC_GLB_GCFG_MCLKSRC_SHIFT        9
+#define MEMC_GLB_GCFG_MCLKSRC_MASK         (0x1<<MEMC_GLB_GCFG_MCLKSRC_SHIFT)
+#define MEMC_GLB_GCFG_MEMINITDONE_SHIFT    8
+#define MEMC_GLB_GCFG_MEMINITDONE_MASK     (0x1<<MEMC_GLB_GCFG_MEMINITDONE_SHIFT)
+#define MEMC_GLB_GCFG_SIZE1_SHIFT          0
+#define MEMC_GLB_GCFG_SIZE1_MASK           (0xf<<MEMC_GLB_GCFG_SIZE1_SHIFT)
+	uint32_t GLB_MRQ_CFG;	/* 0x008 */
+	uint32_t unused0;	/* 0x00c */
+	uint32_t GLB_FSBL_STATE;	/* 0x010 */
+	uint32_t unused1[3];	/* 0x014 - 0x01f */
+
+	uint32_t SRAM_REMAP_CTRL;	/* 0x020 */
+	uint32_t SRAM_REMAP_CTRL_UPPER;	/* 0x024 */
+	uint32_t SRAM_REMAP_INIT;	/* 0x028 */
+	uint32_t SRAM_REMAP_LOG_INFO_0;	/* 0x02c */
+	uint32_t SRAM_REMAP_LOG_INFO_1;	/* 0x030 */
+	uint32_t SRAM_REMAP_LOG_INFO_2;	/* 0x034 */
+	uint32_t unused2[2];	/* 0x038-0x03f */
+
+	uint32_t RBF_REORDER_0_CFG[16];	/* 0x040 - 0x07f */
+
+	uint32_t INTR2_CPU_STATUS;	/* 0x080 */
+	uint32_t INTR2_CPU_SET;	/* 0x084 */
+	uint32_t INTR2_CPU_CLEAR;	/* 0x088 */
+	uint32_t INTR2_CPU_MASK_STATUS;	/* 0x08c */
+	uint32_t INTR2_CPU_MASK_SET;	/* 0x090 */
+	uint32_t INTR2_CPU_MASK_CLEAR;	/* 0x094 */
+	uint32_t unused3[26];	/* 0x098-0x0ff */
+
+	uint32_t CHN_CFG_CNFG;	/* 0x100 */
+#define MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT            16
+#define MEMC_CHN_CFG_CNFG_CS_MODE_MASK             (0x3 << MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT)
+	uint32_t CHN_CFG_CSST;	/* 0x104 */
+	uint32_t unused4[2];	/* 0x108-0x10f */
+	uint32_t CHN_CFG_ROW00_0;	/* 0x110 */
+	uint32_t CHN_CFG_ROW00_1;	/* 0x114 */
+	uint32_t CHN_CFG_ROW01_0;	/* 0x118 */
+	uint32_t CHN_CFG_ROW01_1;	/* 0x11c */
+	uint32_t CHN_CFG_ROW02_0;	/* 0x120 */
+	uint32_t CHN_CFG_COL00_0;	/* 0x124 */
+	uint32_t CHN_CFG_COL00_1;	/* 0x128 */
+	uint32_t CHN_CFG_COL01_0;	/* 0x12c */
+	uint32_t CHN_CFG_COL01_1;	/* 0x130 */
+	uint32_t CHN_CFG_BNK10;	/* 0x134 */
+	uint32_t CHN_CFG_BG0;	/* 0x138 */
+	uint32_t unused5;	/* 0x13c */
+	uint32_t CHN_CFG_DRAM_SZ_CHK;	/* 0x140 */
+	uint32_t CHN_CFG_DIAG_SEL;	/* 0x144 */
+	uint32_t unused6[46];	/* 0x148-0x1ff */
+
+	uint32_t CHN_TIM_DCMD;	/* 0x200 */
+	uint32_t CHN_TIM_DMODE_0;	/* 0x204 */
+	uint32_t CHN_TIM_DMODE_2;	/* 0x208 */
+	uint32_t CHN_TIM_CLKS;	/* 0x20c */
+#define MEMC_CHN_TIM_CLKS_REF_RATE_SHIFT          8
+#define MEMC_CHN_TIM_CLKS_REF_DISABLE_SHIFT       31
+	uint32_t CHN_TIM_ODT;	/* 0x210 */
+	uint32_t CHN_TIM_TIM1_0;	/* 0x214 */
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tWL [31:24] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_MASK                            0xff000000
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_SHIFT                           24
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_DEFAULT                         0x00000004
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRP [23:16] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_MASK                            0x00ff0000
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_SHIFT                           16
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_DEFAULT                         0x00000006
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tCL [15:08] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_MASK                            0x0000ff00
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_SHIFT                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_DEFAULT                         0x00000005
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRCD [07:00] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_MASK                           0x000000ff
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_ALIGN                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_BITS                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_SHIFT                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_DEFAULT                        0x00000006
+
+	uint32_t CHN_TIM_TIM1_1;	/* 0x218 */
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_L [31:24] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_S [23:16] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_L [15:08] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_MASK                         0x0000ff00
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_SHIFT                        8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_S [07:00] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_MASK                         0x000000ff
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_SHIFT                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_DEFAULT                      0x00000002
+
+	uint32_t CHN_TIM_TIM1_2;	/* 0x21c */
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tFAW [31:24] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_MASK                           0xff000000
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_SHIFT                          24
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_DEFAULT                        0x00000000
+/* MC_CHN_TIM :: TIM1_2 :: reserved0 [23:16] */
+#define MC_CHN_TIM_TIM1_2_reserved0_MASK                           0x00ff0000
+#define MC_CHN_TIM_TIM1_2_reserved0_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_reserved0_BITS                           8
+#define MC_CHN_TIM_TIM1_2_reserved0_SHIFT                          16
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRTP [15:08] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_MASK                           0x0000ff00
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_SHIFT                          8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_DEFAULT                        0x00000002
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRC [07:00] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_ALIGN                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_BITS                            8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_SHIFT                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_DEFAULT                         0x00000011
+
+	uint32_t CHN_TIM_TIM1_3;	/* 0x220 */
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_L [31:24] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_S [23:16] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: reserved_for_padding0 [15:12] */
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_MASK               0x0000f000
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_ALIGN              0
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_BITS               4
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_SHIFT              12
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_L [11:08] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_MASK                          0x00000f00
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_BITS                          4
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_SHIFT                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_DEFAULT                       0x00000004
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_S [07:00] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_MASK                          0x000000ff
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_BITS                          8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_SHIFT                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_DEFAULT                       0x00000004
+
+	uint32_t CHN_TIM_TIM2;	/* 0x224 */
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2R [31:30] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_MASK                             0xc0000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_BITS                             2
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_SHIFT                            30
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2W [29:27] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_MASK                             0x38000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_SHIFT                            27
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2R [26:24] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_MASK                             0x07000000
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_SHIFT                            24
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: reserved_for_padding0 [23:22] */
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_MASK                 0x00c00000
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_ALIGN                0
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_BITS                 2
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_SHIFT                22
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2W [21:18] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_MASK                             0x003c0000
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_BITS                             4
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_SHIFT                            18
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_DEFAULT                          0x00000000
+#define MC_CHN_TIM_TIM2_reserved1_MASK                             0x00030000
+#define MC_CHN_TIM_TIM2_reserved1_ALIGN                            0
+#define MC_CHN_TIM_TIM2_reserved1_BITS                             2
+#define MC_CHN_TIM_TIM2_reserved1_SHIFT                            16
+/* MC_CHN_TIM :: TIM2 :: TIM2_tAL [15:12] */
+#define MC_CHN_TIM_TIM2_TIM2_tAL_MASK                              0x0000f000
+#define MC_CHN_TIM_TIM2_TIM2_tAL_ALIGN                             0
+#define MC_CHN_TIM_TIM2_TIM2_tAL_BITS                              4
+#define MC_CHN_TIM_TIM2_TIM2_tAL_SHIFT                             12
+#define MC_CHN_TIM_TIM2_TIM2_tAL_DEFAULT                           0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tRFC [11:00] */
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_MASK                             0x00000fff
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_BITS                             12
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_SHIFT                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_DEFAULT                          0x00000014
+
+	uint32_t unused7[2];	/* 0x228 - 0x22f */
+	uint32_t CHN_TIM_PHY_ST;	/* 0x230 */
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP       0x1
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_HW_RESET       0x2
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_SW_RESET       0x4
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_READY          0x10
+	uint32_t CHN_TIM_DRAM_CFG;	/* 0x234 */
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT           12
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_MASK            (0x1<<MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT)
+#define DRAM_CFG_DRAMSLEEP                        (1<<11)
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT     10
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_MASK      (0x1<<MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT      0
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_MASK       (0xf<<MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT)
+#define MC_DRAM_CFG_DDR3                          0x1
+	uint32_t CHN_TIM_STAT;	/* 0x238 */
+	uint32_t CHN_TIM_PERF;	/* 0x23c */
+	uint32_t unused8[48];	/* 0x240-0x2ff */
+
+	uint32_t ARB_CFG;	/* 0x300 */
+#define MEMC_ARB_CFG_RR_MODE_SHIFT      0x0
+#define MEMC_ARB_CFG_RR_MODE_MASK       (0x1<<MEMC_ARB_CFG_RR_MODE_SHIFT)
+#define MEMC_ARB_CFG_BURST_MODE_SHIFT   0x1
+#define MEMC_ARB_CFG_BURST_MODE_MASK    (0x1<<MEMC_ARB_CFG_BURST_MODE_SHIFT)
+	uint32_t ARB_QUE_DIS[2];	/* 0x304 */
+	uint32_t ARB_SP_SEL[2];	/* 0x30c */
+	uint32_t ARB_RDWR_QUANTUM;	/* 0x314 */
+	uint32_t unused9[2];	/* 0x318 - 0x31f */
+	uint32_t ARB_SP_PRI[9];	/* 0x320 */
+	uint32_t unused10[3];	/* 0x344-0x34f */
+	uint32_t ARB_RR_QUANTUM[18];	/* 0x350 */
+	uint32_t unused11[26];	/* 0x398 - 0x3ff */
+
+	UBUSInterface UBUSIF0;	/* 0x400-0x43f */
+	uint32_t unused12[16];	/* 0x440-0x47f */
+
+	uint32_t unused12a[16];	/* 0x480-0x4bf */
+	AXIInterface AXIWIF;	/* 0x4c0-0x4ff */
+
+	uint32_t unused13[192];	/* 0x500-0x7ff */
+
+	EDISEngine EDIS_0;	/* 0x800 */
+	uint32_t unused13a[64];	/* 0x900 */
+
+	uint32_t STATS_CTRL;	/* 0xa00 */
+	uint32_t STATS_TIMER_CFG;	/* 0xa04 */
+	uint32_t STATS_TIMER_COUNT;	/* 0xa08 */
+	uint32_t STATS_TOTAL_SLICE;	/* 0xa0c */
+	uint32_t STATS_TOTAL_PACKET;	/* 0xa10 */
+	uint32_t STATS_TOTAL_READ_SLICE;	/* 0xa14 */
+	uint32_t STATS_TOTAL_READ_PACKET;	/* 0xa18 */
+	uint32_t STATS_TOTAL_LATENCY;	/* 0xa1c */
+	uint32_t STATS_MAX_LATENCY;	/* 0xa20 */
+	uint32_t STATS_SLICE_REORDER;	/* 0xa24 */
+	uint32_t STATS_TOTAL_DDR_CMD;	/* 0xa28 */
+	uint32_t STATS_TOTAL_DDR_ACT;	/* 0xa2c */
+	uint32_t STATS_TOTAL_DDR_RDWR;	/* 0xa30 */
+	uint32_t STATS_TOTAL_DDR_WRRD;	/* 0xa34 */
+	uint32_t STATS_TOTAL_MRQ_CHN_FULL;	/* 0xa38 */
+	uint32_t STATS_TOTAL_SELF_REF;	/* 0xa3c */
+	uint32_t STATS_ARB_GRANT_MATCH0;	/* 0xa40 */
+	uint32_t STATS_TOTAL_QUEUE_FULL;	/* 0xa44 */
+	uint32_t STATS_TOTAL_ARB_GRANT;	/* 0xa48 */
+	uint32_t STATS_TOTAL_RATE_OK_GRANT;	/* 0xa4c */
+	uint32_t STATS_FILTER_CFG_0;	/* 0xa50 */
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT  25
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_MASK   (0x1<<MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_EN     0x02000000
+#define MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT     16
+#define MEMC_STATS_FILTER_CFG_SRC_ID_MASK      (0x1FF<<MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_SHIFT 0
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_MASK  0x0000FFFF
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS        0x00000001
+#define MEMC_STATS_FILTER_CFG_INTF_AXI         0x00000002
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS0       0x00000004
+#define MEMC_STATS_FILTER_CFG_INTF_UNUSED      0x00000008
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS0       MEMC_STATS_FILTER_CFG_INTF_UBUS
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS1       MEMC_STATS_FILTER_CFG_INTF_AXI
+#define MEMC_STATS_FILTER_CFG_INTF_MCP         MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+	uint32_t STATS_PROG0_SLICE;	/* 0xa54 */
+	uint32_t STATS_PROG0_PACKET;	/* 0xa58 */
+	uint32_t STATS_PROG0_READ_SLICE;	/* 0xa5c */
+	uint32_t STATS_PROG0_READ_PACKET;	/* 0xa60 */
+	uint32_t STATS_PROG0_LATENCY;	/* 0xa64 */
+	uint32_t STATS_PROG0_MAX_LATENCY;	/* 0xa68 */
+	uint32_t unused14[1];	/* 0xa6c */
+	uint32_t STATS_FILTER_CFG_1;	/* 0xa70 */
+	uint32_t STATS_PROG1_SLICE;	/* 0xa74 */
+	uint32_t STATS_PROG1_PACKET;	/* 0xa78 */
+	uint32_t STATS_PROG1_READ_SLICE;	/* 0xa7c */
+	uint32_t STATS_PROG1_READ_PACKET;	/* 0xa80 */
+	uint32_t STATS_PROG1_LATENCY;	/* 0xa84 */
+	uint32_t unused15[2];	/* 0xa88 - 0xa8f */
+	uint32_t STATS_FILTER_CFG_2;	/* 0xa90 */
+	uint32_t STATS_PROG2_SLICE;	/* 0xa94 */
+	uint32_t STATS_PROG2_PACKET;	/* 0xa98 */
+	uint32_t STATS_PROG2_READ_SLICE;	/* 0xa9c */
+	uint32_t STATS_PROG2_READ_PACKET;	/* 0xaa0 */
+	uint32_t STATS_PROG2_LATENCY;	/* 0xaa4 */
+	uint32_t unused16[2];	/* 0xaa8 - 0xaaf */
+	uint32_t STATS_FILTER_CFG_3;	/* 0xab0 */
+	uint32_t STATS_PROG3_SLICE;	/* 0xab4 */
+	uint32_t STATS_PROG3_PACKET;	/* 0xab8 */
+	uint32_t STATS_PROG3_READ_SLICE;	/* 0xabc */
+	uint32_t STATS_PROG3_READ_PACKET;	/* 0xac0 */
+	uint32_t STATS_PROG3_LATENCY;	/* 0xac4 */
+	uint32_t unused17[2];	/* 0xac8 - 0xacf */
+	uint32_t STATS_AXI_BLOCK_CPU_RD;	/* 0xad0 */
+	uint32_t STATS_AXI_BLOCK_CPQ_RD;	/* 0xad4 */
+	uint32_t unused17_1[10];	/* 0xad8 - 0xaff */
+
+	uint32_t CAP_CAPTURE_CFG;	/* 0xb00 */
+	uint32_t CAP_TRIGGER_ADDR;	/* 0xb04 */
+	uint32_t CAP_READ_CTRL;	/* 0xb08 */
+	uint32_t unused18;	/* 0xb0c */
+	uint32_t CAP_CAPTURE_MATCH0;	/* 0xb10 */
+	uint32_t CAP_CAPTURE_MATCH1;	/* 0xb14 */
+	uint32_t CAP_CAPTURE_MATCH2;	/* 0xb18 */
+	uint32_t unused19;	/* 0xb1c */
+	uint32_t CAP_CAPTURE_MASK0;	/* 0xb20 */
+	uint32_t CAP_CAPTURE_MASK1;	/* 0xb24 */
+	uint32_t CAP_CAPTURE_MASK2;	/* 0xb28 */
+	uint32_t unused20;	/* 0xb2c */
+	uint32_t CAP_TRIGGER_MATCH0;	/* 0xb30 */
+	uint32_t CAP_TRIGGER_MATCH1;	/* 0xb34 */
+	uint32_t CAP_TRIGGER_MATCH2;	/* 0xb38 */
+	uint32_t unused21;	/* 0xb3c */
+	uint32_t CAP_TRIGGER_MASK0;	/* 0xb40 */
+	uint32_t CAP_TRIGGER_MASK1;	/* 0xb44 */
+	uint32_t CAP_TRIGGER_MASK2;	/* 0xb48 */
+	uint32_t unused22;	/* 0xb4c */
+	uint32_t CAP_READ_DATA[8];	/* 0xb50-0xb6f */
+	uint32_t unused23[164];	/* 0xb70-0xdff */
+
+	uint32_t SEC_INTR2_CPU_STATUS;	/* 0xe00 */
+	uint32_t SEC_INTR2_CPU_SET;	/* 0xe04 */
+	uint32_t SEC_INTR2_CPU_CLEAR;	/* 0xe08 */
+	uint32_t SEC_INTR2_CPU_MASK_STATUS;	/* 0xe0c */
+	uint32_t SEC_INTR2_CPU_MASK_SET;	/* 0xe10 */
+	uint32_t SEC_INTR2_CPU_MASK_CLEAR;	/* 0xe14 */
+	uint32_t unused24[58];	/* 0xe18-0xeff */
+
+	uint32_t UBUSIF0_PERMCTL;	/* 0xf00 */
+	uint32_t UBUSIF0_ACCCTL;	/* 0xf04 */
+	uint32_t UBUSIF1_PERMCTL;	/* 0xf08 */
+	uint32_t UBUSIF1_ACCCTL;	/* 0xf0c */
+	uint32_t AXIRIF_PERMCTL;	/* 0xf10 */
+	uint32_t AXIRIF_ACCCTL;	/* 0xf14 */
+	uint32_t AXIWIF_PERMCTL;	/* 0xf18 */
+	uint32_t AXIWIF_ACCCTL;	/* 0xf1c */
+	uint32_t CHNCFG_PERMCTL;	/* 0xf20 */
+	uint32_t CHNCFG_ACCCTL;	/* 0xf24 */
+	uint32_t MCCAP_PERMCTL;	/* 0xf28 */
+	uint32_t MCCAP_ACCCTL;	/* 0xf2c */
+	uint32_t SCRAM_PERMCTL;	/* 0xf30 */
+	uint32_t SCRAM_ACCCTL;	/* 0xf34 */
+	uint32_t RNG_PERMCTL;	/* 0xf38 */
+	uint32_t RNG_ACCCTL;	/* 0xf3c */
+	uint32_t RNGCHK_PERMCTL;	/* 0xf40 */
+	uint32_t RNGCHK_ACCCTL;	/* 0xf44 */
+	uint32_t unused25[558];	/* 0xf48-0x17ff */
+
+	SecureRangeCheckers SEC_RANGE_CHK;	/* 0x1800-0x18ff */
+	uint32_t unused26[31168];	/* 0x1900-0x1ffff */
+
+	DDRPhyControl PhyControl;	/* 0x20000 */
+	DDRPhyByteLaneControl PhyByteLaneControl[4];	/* 0x20400 - 0x20bff */
+} MEMCControl;
+
+#define MEMC ((volatile MEMCControl * const) MEMC_BASE)
+
+#endif /* _6858_DDR_H */
diff --git a/arch/arm/include/asm/arch-bcm6858/misc.h b/arch/arm/include/asm/arch-bcm6858/misc.h
new file mode 100644
index 0000000000..77fb8ee13b
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6858/misc.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6858_MISC_H
+#define _6858_MISC_H
+
+/*
+ ** Misc Register Set Definitions.
+ */
+
+typedef struct Misc {
+    uint32_t  miscStrapBus;                       /* 0x00 */
+#define MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT        5
+#define MISC_STRAP_BUS_BOOT_SEL0_4_MASK         (0x18 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL5_SHIFT          11
+#define MISC_STRAP_BUS_BOOT_SEL5_MASK           (0x1 << MISC_STRAP_BUS_BOOT_SEL5_SHIFT)
+#define BOOT_SEL5_STRAP_ADJ_SHIFT               (MISC_STRAP_BUS_BOOT_SEL5_SHIFT-MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+
+    /* boot select bits 0-2 */
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+
+    /* boot select bits 3-5 */
+#define BOOT_SEL_STRAP_BOOT_SEL_NAND_MASK		0x20
+#define BOOT_SEL_STRAP_NAND_2K_PAGE             0x00
+#define BOOT_SEL_STRAP_NAND_4K_PAGE             0x08
+#define BOOT_SEL_STRAP_NAND_8K_PAGE             0x10
+#define BOOT_SEL_STRAP_NAND_512B_PAGE           0x18
+#define BOOT_SEL_STRAP_SPI_NOR                  0x38
+#define BOOT_SEL_STRAP_EMMC                     0x30
+#define BOOT_SEL_STRAP_SPI_NAND                 0x28
+#define BOOT_SEL_STRAP_NAND						0x00
+
+#define BOOT_SEL_STRAP_BOOT_SEL_MASK            (0x38)
+#define BOOT_SEL_STRAP_PAGE_SIZE_MASK           (0x7)
+
+#define MISC_STRAP_BUS_PCIE_SATA_MASK           (1 << 3)
+#define MISC_STRAP_BUS_BOOROM_BOOT_N            (1 << 10 )
+#define MISC_STRAP_BUS_B53_NO_BOOT              (1 << 12) /* 1 = PMC boots before B53 */
+#define MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT       13
+#define MISC_STRAP_BUS_PMC_ROM_BOOT             (0x1 << MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT) /* 1 = PMC boot */
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ            (1 << 14) /* 1 = Slow 400MHz cpu freq */
+#define MISC_STRAP_BUS_PMC_BOOT_AVS             (1 << 20) /* 1 = PMC run AVS */
+#define MISC_STRAP_BUS_PMC_BOOT_FLASH           (1 << 21) /* 1 = PMC boot from flash */ 
+#define MISC_STRAP_BUS_UBUS_FREQ_SHIFT          22
+#define MISC_STRAP_BUS_UBUS_FREQ_MASK           (1 << MISC_STRAP_BUS_UBUS_FREQ_SHIFT) /* 1 = 2GHz, 0 = 1GHz */  
+#define MISC_STRAP_DDR_16B_EN_SHIFT             26
+#define MISC_STRAP_DDR_16B_EN_MASK              (1 << MISC_STRAP_DDR_16B_EN_SHIFT)
+#define MISC_STRAP_DDR_DENSITY_SHIFT            15
+#define MISC_STRAP_DDR_DENSITY_MASK             (3 << MISC_STRAP_DDR_DENSITY_SHIFT) /* 1=8Gb, 2=4Gb, 3=2Gb */
+#define MISC_STRAP_DDR_OVERRIDE_N_SHIFT         17
+#define MISC_STRAP_DDR_OVERRIDE_N_MASK          (1 << MISC_STRAP_DDR_OVERRIDE_N_SHIFT)
+#define MISC_STRAP_OEC_SHIFT                    24
+#define MISC_STRAP_OEC_MASK                     (0x3 << MISC_STRAP_OEC_SHIFT)
+#define MISC_STRAP_OEC_156MHZ                   0x1
+#define MISC_STRAP_OEC_155MHZ                   0x2
+#define MISC_STRAP_OEC_50MHZ                    0x3
+
+    uint32_t  miscStrapOverride;                  /* 0x04 */
+    uint32_t  miscSWdebug[6];                     /* 0x08-0x1c */
+    uint32_t  miscWDresetCtrl;                    /* 0x20 */
+    uint32_t  miscSWdebugNW[2];                   /* 0x24-0x28 */
+    uint32_t  miscSoftResetB;                     /* 0x2c */
+    uint32_t  miscPLLstatus;                      /* 0x30 */
+    uint32_t  miscDierevid;                       /* 0x34 */
+    uint32_t  miscSPImasterCtrl;                  /* 0x38 */
+    uint32_t  miscAltBoot;                        /* 0x3c */
+    uint32_t  miscPeriphCtrl;                     /* 0x40 */
+#define MISC_PCIE_CTRL_CORE_SOFT_RESET_MASK     (0x7)
+    uint32_t  miscPCIECtrl;                       /* 0x44 */
+    uint32_t  miscAdslClockSample;                /* 0x48 */
+    uint32_t  miscRNGCtrl;                        /* 0x4c */
+    uint32_t  miscMbox0_data;                     /* 0x50 */
+    uint32_t  miscMbox1_data;                     /* 0x54 */
+    uint32_t  miscMbox2_data;                     /* 0x58 */
+    uint32_t  miscMbox3_data;                     /* 0x5c */
+    uint32_t  miscMbox_ctrl;                      /* 0x60 */
+    uint32_t  miscMIIPadCtrl;                     /* 0x64 */
+    uint32_t  miscRGMII1PadCtrl;                  /* 0x68 */
+    uint32_t  miscRGMII2PadCtrl;                  /* 0x6c */
+    uint32_t  miscRGMII3PadCtrl;                  /* 0x70 */
+    uint32_t  miscMIIPullCtrl;                    /* 0x74 */
+    uint32_t  miscRGMII1PullCtrl;                 /* 0x78 */
+    uint32_t  miscRGMII2PullCtrl;                 /* 0x7c */
+    uint32_t  miscRGMII3PullCtrl;                 /* 0x80 */
+    uint32_t  miscWDenReset;                      /* 0x84 */
+    uint32_t  miscBootOverlayEn;                  /* 0x88 */
+    uint32_t  miscSGMIIfiber;                     /* 0x8c */
+    uint32_t  miscUNIMACCtrl;                     /* 0x90 */
+    uint32_t  miscMaskUBUSErr;                    /* 0x94 */
+    uint32_t  miscTOSsync;                        /* 0x98 */
+    uint32_t  miscPM0_1_status;                   /* 0x9c */
+    uint32_t  miscPM2_3_status;                   /* 0xa0 */
+    uint32_t  miscSGB_status;                     /* 0xa4 */
+    uint32_t  miscPM0_1_config;                   /* 0xa8 */
+    uint32_t  miscPM2_3_config;                   /* 0xac */
+    uint32_t  miscSGB_config;                     /* 0xb0 */
+    uint32_t  miscPM0_1_tmon_config;              /* 0xb4 */
+    uint32_t  miscPM2_3_tmon_config;              /* 0xb8 */
+    uint32_t  miscSGB_tmon_config;                /* 0xbc */
+    uint32_t  miscMDIOmasterSelect;               /* 0xc0 */
+    uint32_t  miscUSIMCtrl;                       /* 0xc4 */
+    uint32_t  miscUSIMPadCtrl;                    /* 0xc8 */
+    uint32_t  miscPerSpareReg[3];                 /* 0xcc - 0xd4 */
+    uint32_t  miscDgSensePadCtrl;                 /* 0xd8 */
+#define DG_CTRL_SHIFT   4
+#define DG_EN_SHIFT     3
+#define DG_TRIM_SHIFT   0
+    uint32_t  miscPeriphMiscCtrl;                 /* 0xdc */
+    uint32_t  miscPeriphMiscStat;                 /* 0xe0 */
+} Misc;
+
+#define MISC_BASE          0xff802600
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   16
+#define CHIP_ID_MASK    (0xffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6858/otp.h b/arch/arm/include/asm/arch-bcm6858/otp.h
new file mode 100644
index 0000000000..8d5a221dc1
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6858/otp.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _6858_OTP_H
+#define _6858_OTP_H
+
+
+#define JTAG_OTP_BASE    0xff800e00
+
+/* row 12 */
+#define OTP_SEC_CHIPVAR_ROW			12
+#define OTP_SEC_CHIPVAR_MASK			0xf
+#define OTP_SEC_CHIPVAR_SHIFT			0x0
+
+/* row 14 */
+#define OTP_CPU_CORE_CFG_ROW			14
+#define OTP_CPU_CORE_CFG_SHIFT			14
+#define OTP_CPU_CORE_CFG_MASK			0x3
+
+#define OTP_CPU_CLOCK_FREQ_ROW          	14
+#define OTP_CPU_CLOCK_FREQ_SHIFT        	9
+#define OTP_CPU_CLOCK_FREQ_MASK         	0x7
+/* row 14 */
+#define OTP_CPU_CORE_CFG_ROW			14
+#define OTP_CPU_CORE_CFG_SHIFT			14
+#define OTP_CPU_CORE_CFG_MASK			0x3
+
+/* row 14 */
+#define OTP_CPU_CORE_CFG_ROW			14
+#define OTP_CPU_CORE_CFG_SHIFT			14
+#define OTP_CPU_CORE_CFG_MASK			0x3
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          7
+
+/* row 24 */
+#define OTP_CUST_MFG_MRKTID_ROW                 24
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)									\
+	static otp_hw_cmn_row_t __VV__[ ] = {									\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT, 1},\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT, 1},				\
+	{OTP_MAP_SEC_CHIPVAR, OTP_SEC_CHIPVAR_ROW, OTP_SEC_CHIPVAR_MASK, OTP_SEC_CHIPVAR_SHIFT, 1},				\
+	{OTP_MAP_CPU_CORE_CFG, OTP_CPU_CORE_CFG_ROW, OTP_CPU_CORE_CFG_MASK, OTP_CPU_CORE_CFG_SHIFT, 1},				\
+	{OTP_MAP_CPU_CLOCK_FREQ, OTP_CPU_CLOCK_FREQ_ROW, OTP_CPU_CLOCK_FREQ_MASK, OTP_CPU_CLOCK_FREQ_SHIFT, 1},				\
+	}
+
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6858/pmc.h b/arch/arm/include/asm/arch-bcm6858/pmc.h
new file mode 100644
index 0000000000..ba7a6c164a
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6858/pmc.h
@@ -0,0 +1,353 @@
+#ifndef PMC_H
+#define PMC_H 
+
+/*
+ * Power Management Control
+ */
+typedef struct PmcCtrlReg {
+    /* 0x00 */
+    uint32_t l1Irq4keMask;
+    uint32_t l1Irq4keStatus;
+    uint32_t l1IrqMipsMask;
+    uint32_t l1IrqMipsStatus;
+    /* 0x10 */
+    uint32_t l2IrqGpMask;
+    uint32_t l2IrqGpStatus;
+    uint32_t gpTmr0Ctl;
+    uint32_t gpTmr0Cnt;
+    /* 0x20 */
+    uint32_t gpTmr1Ctl;
+    uint32_t gpTmr1Cnt;
+    uint32_t hostMboxIn;
+    uint32_t hostMboxOut;
+    /* 0x30 */
+#define PMC_CTRL_GP_FLASH_BOOT_STALL    0x00000080
+    uint32_t gpOut;
+    uint32_t gpIn;
+    uint32_t gpInIrqMask;
+    uint32_t gpInIrqStatus;
+    /* 0x40 */
+    uint32_t dmaCtrl;
+    uint32_t dmaStatus;
+    uint32_t dma0_3FifoStatus;
+    uint32_t unused0[3];                  /* 0x4c-0x57 */
+    /* 0x58 */
+    uint32_t l1IrqMips1Mask;
+    uint32_t diagControl;
+    /* 0x60 */
+    uint32_t diagHigh;
+    uint32_t diagLow;
+    uint32_t badAddr;
+    uint32_t addr1WndwMask;
+    /* 0x70 */
+    uint32_t addr1WndwBaseIn;
+    uint32_t addr1WndwBaseOut;
+    uint32_t addr2WndwMask;
+    uint32_t addr2WndwBaseIn;
+    /* 0x80 */
+    uint32_t addr2WndwBaseOut;
+    uint32_t scratch;
+    uint32_t tm;
+    uint32_t softResets;
+    /* 0x90 */
+    uint32_t eb2ubusTimeout;
+    uint32_t m4keCoreStatus;
+    uint32_t gpInIrqSense;
+    uint32_t ubSlaveTimeout;
+    /* 0xa0 */
+    uint32_t diagEn;
+    uint32_t devTimeout;
+    uint32_t ubusErrorOutMask;
+    uint32_t diagCaptStopMask;
+    /* 0xb0 */
+    uint32_t revId;
+    uint32_t gpTmr2Ctl;
+    uint32_t gpTmr2Cnt;
+    uint32_t legacyMode;
+    /* 0xc0 */
+    uint32_t smisbMonitor;
+    uint32_t diagCtrl;
+    uint32_t diagStat;
+    uint32_t diagMask;
+    /* 0xd0 */
+    uint32_t diagRslt;
+    uint32_t diagCmp;
+    uint32_t diagCapt;
+    uint32_t diagCnt;
+    /* 0xe0 */
+    uint32_t diagEdgeCnt;
+    uint32_t unused1[4];                  /* 0xe4-0xf3 */
+    /* 0xf4 */
+    uint32_t iopPeriphBaseAddr;
+    uint32_t lfsr;
+    uint32_t unused2;                     /* 0xfc-0xff */
+} PmcCtrlReg;
+
+typedef struct PmcOutFifoReg {
+    uint32_t msgCtrl;                     /* 0x00 */
+    uint32_t msgSts;                      /* 0x04 */
+    uint32_t unused[14];                  /* 0x08-0x3f */
+    uint32_t msgData[16];                 /* 0x40-0x7c */
+} PmcOutFifoReg;
+
+typedef struct PmcInFifoReg {
+    uint32_t msgCtrl;                     /* 0x00 */
+    uint32_t msgSts;                      /* 0x04 */
+    uint32_t unused[13];                  /* 0x08-0x3b */
+    uint32_t msgLast;                     /* 0x3c */
+    uint32_t msgData[16];                 /* 0x40-0x7c */
+} PmcInFifoReg;
+
+typedef struct PmcDmaReg {
+    /* 0x00 */
+    uint32_t src;
+    uint32_t dest;
+    uint32_t cmdList;
+    uint32_t lenCtl;
+    /* 0x10 */
+    uint32_t rsltSrc;
+    uint32_t rsltDest;
+    uint32_t rsltHcs;
+    uint32_t rsltLenStat;
+} PmcDmaReg;
+
+typedef struct PmcTokenReg {
+    /* 0x00 */
+    uint32_t bufSize;
+    uint32_t bufBase;
+    uint32_t idx2ptrIdx;
+    uint32_t idx2ptrPtr;
+    /* 0x10 */
+    uint32_t unused[2];
+    uint32_t bufSize2;
+} PmcTokenReg;
+
+typedef struct PmcPerfPowReg {
+    /* 0x00 */
+    uint32_t dcacheHit;
+    uint32_t dcacheMiss;
+    uint32_t icacheHit;
+    uint32_t icacheMiss;
+    /* 0x10 */
+    uint32_t instnComplete;
+    uint32_t wtbMerge;
+    uint32_t wtbNoMerge;
+    uint32_t itlbHit;
+    /* 0x20 */
+    uint32_t itlbMiss;
+    uint32_t dtlbHit;
+    uint32_t dtlbMiss;
+    uint32_t jtlbHit;
+    /* 0x30 */
+    uint32_t jtlbMiss;
+    uint32_t powerSubZone;
+    uint32_t powerMemPda;
+    uint32_t freqScalarCtrl;
+    /* 0x40 */
+    uint32_t freqScalarMask;
+} PmcPerfPowReg;
+
+typedef struct PmcDQMReg {
+    /* 0x00 */
+    uint32_t cfg;
+    uint32_t _4keLowWtmkIrqMask;
+    uint32_t mipsLowWtmkIrqMask;
+    uint32_t lowWtmkIrqMask;
+    /* 0x10 */
+    uint32_t _4keNotEmptyIrqMask;
+    uint32_t mipsNotEmptyIrqMask;
+    uint32_t notEmptyIrqSts;
+    uint32_t queueRst;
+    /* 0x20 */
+    uint32_t notEmptySts;
+    uint32_t nextAvailMask;
+    uint32_t nextAvailQueue;
+    uint32_t mips1LowWtmkIrqMask;
+    /* 0x30 */
+    uint32_t mips1NotEmptyIrqMask;
+    uint32_t autoSrcPidInsert;
+} PmcDQMReg;
+
+typedef struct PmcCntReg {
+    uint32_t cntr[10];
+    uint32_t unused[6];   /* 0x28-0x3f */
+    uint32_t cntrIrqMask;
+    uint32_t cntrIrqSts;
+} PmcCntReg;
+
+typedef struct PmcDqmQCtrlReg {
+    uint32_t size;
+    uint32_t cfga;
+    uint32_t cfgb;
+    uint32_t cfgc;
+} PmcDqmQCtrlReg;
+
+typedef struct PmcDqmQDataReg {
+    uint32_t word[4];
+} PmcDqmQDataReg;
+
+typedef struct PmcDqmQMibReg {
+    uint32_t qNumFull[32];
+    uint32_t qNumEmpty[32];
+    uint32_t qNumPushed[32];
+} PmcDqmQMibReg;
+
+typedef struct Pmc {
+    uint32_t baseReserved;                /* 0x0000 */
+    uint32_t unused0[1023];
+    PmcCtrlReg ctrl;                    /* 0x1000 */
+
+    PmcOutFifoReg outFifo;              /* 0x1100 */
+    uint32_t unused1[32];                 /* 0x1180-0x11ff */
+    PmcInFifoReg inFifo;                /* 0x1200 */
+    uint32_t unused2[32];                 /* 0x1280-0x12ff */
+
+    PmcDmaReg dma[2];                   /* 0x1300 */
+    uint32_t unused3[48];                 /* 0x1340-0x13ff */
+
+    PmcTokenReg token;                  /* 0x1400 */
+    uint32_t unused4[121];                /* 0x141c-0x15ff */
+
+    PmcPerfPowReg perfPower;            /* 0x1600 */
+    uint32_t unused5[47];                 /* 0x1644-0x16ff */
+
+    uint32_t msgId[32];                   /* 0x1700 */
+    uint32_t unused6[32];                 /* 0x1780-0x17ff */
+
+    PmcDQMReg dqm;                      /* 0x1800 */
+    uint32_t unused7[50];                 /* 0x1838-0x18ff */
+
+    PmcCntReg hwCounter;                /* 0x1900 */
+    uint32_t unused8[46];                 /* 0x1948-0x19ff */
+
+    PmcDqmQCtrlReg dqmQCtrl[32];        /* 0x1a00 */
+    PmcDqmQDataReg dqmQData[32];        /* 0x1c00 */
+    uint32_t unused9[64];                 /* 0x1e00-0x1eff */
+
+    uint32_t qStatus[32];                 /* 0x1f00 */
+    uint32_t unused10[32];                /* 0x1f80-0x1fff */
+
+    PmcDqmQMibReg qMib;                 /* 0x2000 */
+    uint32_t unused11[1952];              /* 0x2180-0x3ffff */
+
+    uint32_t sharedMem[8192];             /* 0x4000-0xbffc */
+} Pmc;
+
+#define PMC_BASE         0x80200000
+#define PMC ((volatile Pmc * const) PMC_BASE)
+
+/*
+ * Process Monitor Module
+ */
+typedef struct PMRingOscillatorControl {
+    uint32_t control;
+    uint32_t en_lo;
+    uint32_t en_mid;
+    uint32_t en_hi;
+    uint32_t idle_lo;
+    uint32_t idle_mid;
+    uint32_t idle_hi;
+} PMRingOscillatorControl;
+
+#define RCAL_0P25UM_HORZ                0
+#define RCAL_0P25UM_VERT                1
+#define RCAL_0P5UM_HORZ                 2
+#define RCAL_0P5UM_VERT                 3
+#define RCAL_1UM_HORZ                   4
+#define RCAL_1UM_VERT                   5
+#define PMMISC_RMON_EXT_REG             ((RCAL_1UM_VERT + 1)/2)
+#define PMMISC_RMON_VALID_MASK          (0x1<<16)
+typedef struct PMMiscControl {
+    uint32_t gp_out;
+    uint32_t clock_select;
+    uint32_t unused[2];
+    uint32_t misc[4];
+} PMMiscControl;
+
+typedef struct PMSSBMasterControl {
+    uint32_t control;
+    uint32_t wr_data;
+    uint32_t rd_data;
+} PMSSBMasterControl;
+
+#define SWR_FIRST 1
+#define SWR_LAST 3
+
+#define SWR_READ_CMD_P 0xB800
+#define SWR_WR_CMD_P   0xB400
+#define SWR_EN         0x1000
+#define SET_ADDR(ps, reg)  (((ps) << 5 | ((reg) & 0x1f)) & 0x2ff)
+
+#define SR_TEST(x)  {\
+                     int num;\
+                     for(num=1000;(((PROCMON->SSBMaster.control) & 0x8000) && (num > 0)) ; num--) ;\
+                         if(!num) \
+                         {\
+                             printf("Error num %d timeout num = %d!!!", (x),  num);\
+                         }\
+}
+
+typedef struct PMEctrControl {
+    uint32_t control;
+    uint32_t interval;
+    uint32_t thresh_lo;
+    uint32_t thresh_hi;
+    uint32_t count;
+} PMEctrControl;
+
+typedef struct PMBMaster {
+    uint32_t ctrl;
+#define PMC_PMBM_START                  (1 << 31)
+#define PMC_PMBM_TIMEOUT                (1 << 30)
+#define PMC_PMBM_SLAVE_ERR              (1 << 29)
+#define PMC_PMBM_BUSY                   (1 << 28)
+#define PMC_PMBM_Read                   (0 << 20)
+#define PMC_PMBM_Write                  (1 << 20)
+    uint32_t wr_data;
+    uint32_t timeout;
+    uint32_t rd_data;
+    uint32_t unused[4];
+} PMBMaster;
+
+typedef struct PMAPVTMONControl {
+    uint32_t control;
+    uint32_t reserved;
+    uint32_t cfg_lo;
+    uint32_t cfg_hi;
+    uint32_t data;
+    uint32_t vref_data;
+    uint32_t unused[2];
+    uint32_t ascan_cfg;
+    uint32_t warn_temp;
+    uint32_t reset_temp;
+    uint32_t temp_value;
+    uint32_t data1_value;
+    uint32_t data2_value;
+    uint32_t data3_value;
+} PMAPVTMONControl;
+
+typedef struct PMUBUSCfg {
+    uint32_t window[8];
+    uint32_t control;
+} PMUBUSCfg;
+
+typedef struct ProcessMonitorRegs {
+    uint32_t MonitorCtrl;               /* 0x00 */
+    uint32_t unused0[7];
+    PMRingOscillatorControl ROSC;       /* 0x20 */
+    uint32_t unused1;
+    PMMiscControl Misc;                 /* 0x40 */
+    PMSSBMasterControl SSBMaster;       /* 0x60 */
+    uint32_t unused2[5];
+    PMEctrControl Ectr;                 /* 0x80 */
+    uint32_t unused3[11];
+    PMBMaster PMBM[2];                  /* 0xc0 */
+    PMAPVTMONControl APvtmonCtrl;       /* 0x100 */
+    uint32_t unused4[9];
+    PMUBUSCfg UBUSCfg;                  /* 0x160 */
+} ProcessMonitorRegs;
+
+#define PROC_MON_BASE        0x80280000
+#define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6858/pmc_addr.h b/arch/arm/include/asm/arch-bcm6858/pmc_addr.h
new file mode 100644
index 0000000000..05c31db7e6
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6858/pmc_addr.h
@@ -0,0 +1,134 @@
+#define PMB_BUS_MAX              2
+#define PMB_BUS_ID_SHIFT         8
+
+#define PMB_BUS_PERIPH           0
+#define PMB_ADDR_PERIPH          (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH         3
+
+#define PMB_BUS_CHIP_CLKRST      0
+#define PMB_ADDR_CHIP_CLKRST     (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST    0
+
+#define PMB_BUS_SYSPLL           0
+#define PMB_ADDR_SYSPLL          (2 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL         0
+
+#define PMB_BUS_RDPPLL           0
+#define PMB_ADDR_RDPPLL          (3 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_RDPPLL         0
+
+#define PMB_BUS_UNIPLL           0
+#define PMB_ADDR_UNIPLL          (5 | PMB_BUS_UNIPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_UNIPLL         0
+
+#define PMB_BUS_CRYPTO           1
+#define PMB_ADDR_CRYPTO          (6 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CRYPTO         0
+
+#define PMB_BUS_APM              0
+#define PMB_ADDR_APM             (7 | PMB_BUS_APM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_APM            2
+
+#define PMB_BUS_MEMC             0
+#define PMB_ADDR_MEMC            (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC           1
+
+#define PMB_BUS_LPORT            1
+#define PMB_ADDR_LPORT           (9 | PMB_BUS_LPORT << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_LPORT          3
+
+#define PMB_BUS_USB30_2X         1
+#define PMB_ADDR_USB30_2X        (10 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB30_2X       4
+
+#define PMB_BUS_WAN              1
+#define PMB_ADDR_WAN             (11 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WAN            7
+
+#define PMB_BUS_XRDP              1
+#define PMB_ADDR_XRDP             (12 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP            3
+
+#define PMB_BUS_XRDP_QM           1
+#define PMB_ADDR_XRDP_QM          (13 | PMB_BUS_XRDP_QM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_QM         1
+
+#define PMB_BUS_XRDP_RC_QUAD0     1
+#define PMB_ADDR_XRDP_RC_QUAD0    (14 | PMB_BUS_XRDP_RC_QUAD0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC_QUAD0   1
+
+#define PMB_BUS_XRDP_RC_QUAD1     1
+#define PMB_ADDR_XRDP_RC_QUAD1    (15 | PMB_BUS_XRDP_RC_QUAD1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC_QUAD1   1
+
+#define PMB_BUS_XRDP_RC_QUAD2     1
+#define PMB_ADDR_XRDP_RC_QUAD2    (16 | PMB_BUS_XRDP_RC_QUAD2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC_QUAD2   1
+
+#define PMB_BUS_XRDP_RC_QUAD3     1
+#define PMB_ADDR_XRDP_RC_QUAD3    (17 | PMB_BUS_XRDP_RC_QUAD3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP_RC_QUAD3   1
+
+#define PMB_BUS_PCIE0              1
+#define PMB_ADDR_PCIE0             (18 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0            1
+
+#define PMB_BUS_PCIE1              1
+#define PMB_ADDR_PCIE1             (19 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE1            1
+
+#define PMB_BUS_SATA               1
+#define PMB_ADDR_SATA             (20 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SATA             1
+
+#define PMB_BUS_PCIE_UBUS          1
+#define PMB_ADDR_PCIE_UBUS         (21 | PMB_BUS_PCIE_UBUS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE_UBUS        1
+
+#define PMB_BUS_ORION_CPU0         0
+#define PMB_ADDR_ORION_CPU0        (24 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0       1
+
+#define PMB_BUS_ORION_CPU1         0
+#define PMB_ADDR_ORION_CPU1        (25 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1       1
+
+#define PMB_BUS_ORION_CPU2         0
+#define PMB_ADDR_ORION_CPU2        (26 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU2       1
+
+#define PMB_BUS_ORION_CPU3         0
+#define PMB_ADDR_ORION_CPU3        (27 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU3       1
+
+#define PMB_BUS_ORION_NONCPU       0
+#define PMB_ADDR_ORION_NONCPU      (28 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU     1
+
+#define PMB_BUS_ORION_ARS          0
+#define PMB_ADDR_ORION_ARS         (29 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_ARS        1
+
+#define PMB_BUS_BIU_PLL            0
+#define PMB_ADDR_BIU_PLL           (30 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL          1   // FIXMET
+
+#define PMB_BUS_BIU_BPCM           0
+#define PMB_ADDR_BIU_BPCM          (31 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM         1
+
+#define PMB_BUS_PCM                0
+
+#define PMB_ADDR_PCM               (0 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT)
+
+#define PMB_ZONES_PCM              2
+
+enum {
+    PCM_Zone_Main,
+    PCM_Zone_PCM=3,
+};
+
+//--------- SOFT Reset bits for PCM ------------------------
+#define   BPCM_PCM_SRESET_HARDRST_N   0x00000004
+#define   BPCM_PCM_SRESET_PCM_N       0x00000040
+#define   BPCM_PCM_SRESET_BUS_N       0x00000001
diff --git a/arch/arm/include/asm/arch-bcm6858/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm6858/pmc_drv_cfg.h
new file mode 100644
index 0000000000..dd15d87a03
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6858/pmc_drv_cfg.h
@@ -0,0 +1,39 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_IMPL_1_X
+
+#define PMC_CPU_BIG_ENDIAN   1
+#define PMC_GETRCAL_SUPPORT  1
+#define PMC_STALL_SUPPORT    1
+#define PMC_UCBID 1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm6858/rng.h b/arch/arm/include/asm/arch-bcm6858/rng.h
new file mode 100644
index 0000000000..415958d135
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6858/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6858_RNG_H
+#define _6858_RNG_H
+
+#define RNG_BASE    0xff800b80
+
+typedef struct Rng {
+	uint32_t ctrl0;		/* 0x00 */
+	uint32_t rngSoftReset;	/* 0x04 */
+	uint32_t rbgSoftReset;	/* 0x08 */
+	uint32_t totalBitCnt;	/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;		/* 0x14 */
+	uint32_t intStatus;	/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL       (0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL       (0x1<<2)
+	uint32_t intEn;		/* 0x1c */
+	uint32_t rngFifoData;	/* 0x20 */
+	uint32_t fifoCnt;	/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS           0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS           0x33
+	uint32_t perm;		/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6858/ubus4.h b/arch/arm/include/asm/arch-bcm6858/ubus4.h
new file mode 100644
index 0000000000..fbac846acb
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6858/ubus4.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6858_UBUS4_H
+#define _6858_UBUS4_H
+
+#define UBUS_SYS_MODULE_BASE                0x83000000
+
+#define MST_PORT_NODE_PCIE0_PHYS_BASE       0x8300C000
+#define MST_PORT_NODE_PCIE2_PHYS_BASE       0x83014000
+#define MST_PORT_NODE_B53_PHYS_BASE         0x83020000
+#define MST_PORT_NODE_SPU_PHYS_BASE         0x83030000
+#define MST_PORT_NODE_USB_PHYS_BASE         0x83038000
+#define MST_PORT_NODE_PMC_PHYS_BASE         0x83044000
+#define MST_PORT_NODE_APM_PHYS_BASE         0x8304C000
+#define MST_PORT_NODE_PER_PHYS_BASE         0x83058000
+#define MST_PORT_NODE_PER_DMA_PHYS_BASE     0x83060000
+#define MST_PORT_NODE_DMA0_PHYS_BASE        0x83464000
+#define MST_PORT_NODE_DMA1_PHYS_BASE        0x83468000
+#define MST_PORT_NODE_RQ0_PHYS_BASE         0x83480000
+#define MST_PORT_NODE_RQ1_PHYS_BASE         0x83488000
+#define MST_PORT_NODE_RQ2_PHYS_BASE         0x83490000
+#define MST_PORT_NODE_RQ3_PHYS_BASE         0x83498000
+#define MST_PORT_NODE_NATC_PHYS_BASE        0x834A0000
+#define MST_PORT_NODE_DQM_PHYS_BASE         0x834A4000
+#define MST_PORT_NODE_QM_PHYS_BASE          0x834AC000
+#define MST_PORT_NODE_TOP_BUFF_PHYS_BASE    0x830e0000
+#define MST_PORT_NODE_XRDP_BUFF_PHYS_BASE   0x834e4000
+
+typedef struct Ubus4SysModuleTop {
+	uint32_t unused0[16];      /* 0x0 */
+	uint32_t UcbData;          /* 0x40 */
+	uint32_t UcbHdr;           /* 0x44 */
+	uint32_t UcbCntl;          /* 0x48 */
+	uint32_t unused1;          /* 0x4c */
+	uint32_t ReadUcbHdr;       /* 0x50 */
+	uint32_t ReadUcbData;      /* 0x54 */
+	uint32_t ReadUcbStatus;    /* 0x58 */
+	uint32_t ReacUcbFifoStatus; /* 0x5c */
+} Ubus4SysModuleTop;
+
+#define UBUSSYSTOP ((volatile Ubus4SysModuleTop * const) UBUS_SYS_MODULE_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6878/BPCM.h b/arch/arm/include/asm/arch-bcm6878/BPCM.h
new file mode 100644
index 0000000000..e1c8a978da
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6878/BPCM.h
@@ -0,0 +1,946 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#ifndef BPCM_H
+#define BPCM_H
+
+typedef union {
+	struct {
+		uint32_t pmbAddr:12;	// [11:00]
+		uint32_t map_rev:4;	// [15:12] always non-zero for AVS3 devices (see CLASSIC_BPCM_ID_REG below)
+		uint32_t island:4;	// [19:16]
+		uint32_t devType:4;	// [23:20] see enum above
+		uint32_t hw_rev:8;	// [31:24]
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ID_REG;
+
+enum {
+	kPMB_NO_DEVICE = 0,
+	kPMB_BPCM = 1,		// in AVS3, this structure does not contain ARS registers (except for "classic" BPCM devices) 
+	kPMB_MIPS_PLL = 2,
+	kPMB_GEN_PLL = 3,
+	kPMB_LC_PLL = 4,
+	kPMB_CLKRST = 5,
+	kPMB_PVTMON = 6,	// used in in AVS3 when PVT is wrapped in a BPCM structure
+	kPMB_TMON_INTERNAL = 7,	// ditto - used when TMON thermistor is on-die
+	kPMB_TMON_EXTERNAL = 8,	// ditto - used when thermistor is off-die
+	kPMB_ARS = 9,		// AVS Remote Sensors - remote oscillators and Power-Watchdog
+	// 10..15 reserved
+};
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t num_sr_bits:8;
+		uint32_t devType:4;	// see enum above
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t pwd_alert:1;
+		uint32_t reserved:31;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t ro_en_s:1;
+		uint32_t ro_en_h:1;
+		uint32_t ectr_en_s:1;
+		uint32_t ectr_en_h:1;
+		uint32_t thresh_en_s:1;
+		uint32_t thresh_en_h:1;
+		uint32_t continuous_s:1;
+		uint32_t continuous_h:1;
+		uint32_t reserved:4;
+		uint32_t valid_s:1;
+		uint32_t alert_s:1;
+		uint32_t valid_h:1;
+		uint32_t alert_h:1;
+		uint32_t interval:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;
+		uint32_t thresh_hi:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_THRESHOLD;
+
+typedef union {
+	struct {
+		uint32_t count_s:16;
+		uint32_t count_h:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_ROSC_COUNT;
+
+typedef union {
+	struct {
+		uint32_t pwd_en:1;
+		uint32_t pwd_alert_sel:1;
+		uint32_t start:6;
+		uint32_t pwd_tm_en:1;
+		uint32_t reserved2:6;
+		uint32_t alert:1;
+		uint32_t ccfg:8;
+		uint32_t rsel:3;
+		uint32_t clr_cfg:3;
+		uint32_t reserved1:2;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_AVS_PWD_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWD_ACCUM_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t sr:8;
+		uint32_t gp:24;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SR_CONTROL;
+
+typedef union{
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+	struct {
+		uint32_t vdsl_arm_por_reset_n:1;
+		uint32_t vdsl_arm_reset_n:1;
+		uint32_t vdsl_arm_debug_reset_n:1;
+		uint32_t vdsl_arm_l2_reset_n:1;
+		uint32_t vdsl_arm_cdbgrstreq_en:1;
+		uint32_t vdsl_arm_niden_a7_b0:1;
+		uint32_t vdsl_arm_spniden_a7_b0:1;
+		uint32_t vdsl_arm_nsocdbgreset_a7:1;
+		uint32_t axi4_ubus4_pass_through_disable:1;
+		uint32_t vdsl_arm_dbgen_a7_b0:1;
+		uint32_t vdsl_arm_spiden_a7_b0:1;
+		uint32_t vdsl_arm_scratch_reg:21;
+	} Bits_vdsl;
+} BPCM_VDSL_ARM_RST_CTL;
+
+typedef union {
+	struct {
+		uint32_t tbd:32;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_GLOBAL_CNTL;
+
+typedef union {
+	struct {
+		uint32_t ctl;
+	} Bits_sata_gp;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved:25;
+	} Bits_switch_z1_qgphy;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:1;	/* 1 */
+		uint32_t force_dll_en:1;	/* 2 */
+		uint32_t iddq_global_pwd:1;	/* 3 */
+		uint32_t ck25_dis:1;	/* 4 */
+		uint32_t phy_reset:1;	/* 5 */
+		uint32_t reserved0:2;
+		uint32_t phy_ad:5;	/* 8-12 */
+		uint32_t reserved1:18;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_1port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwd:1;	/* 6 */
+		uint32_t ck25_dis:1;	/* 7 */
+		uint32_t phy_reset:1;	/* 8 */
+		uint32_t reserved0:3;
+		uint32_t phy_ad:5;	/* 12-16 */
+		uint32_t reserved1:14;
+		uint32_t ctrl_en:1;	/* 31 */
+	} Bits_egphy_4port;
+	struct {
+		uint32_t iddq_bias:1;	/* 0 */
+		uint32_t ext_pwr_down:4;	/* 1-4 */
+		uint32_t force_dll_en:1;	/* 5 */
+		uint32_t iddq_global_pwr:1;	/* 6 */
+		uint32_t reserved0:25;	/* 7-31 */
+	} Bits_qgphy_cntl;
+	struct {
+		uint32_t ctl;
+	} Bits_vdsl_phy;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits_qgphy_status;
+	struct {
+		uint32_t alt_bfc_vector:12;	/* 00-11 */
+		uint32_t reserved0:3;
+		uint32_t alt_bfc_en:1;	/* 15 */
+		uint32_t reset_dly_cfg:2;	/* 16-17 */
+		uint32_t reserved1:8;
+		uint32_t ext_mclk_en_reset:1;	/* 26 */
+		uint32_t ext_mclk_en:1;	/* 27 */
+		uint32_t por_reset_n_ctl:1;	/* 28 */
+		uint32_t reset_n_ctl:1;	/* 29 */
+		uint32_t reserved2:1;
+		uint32_t clken:1;	/* 31 */
+	} Bits_vdsl_mips;	/* second PHY MIPS core */
+	uint32_t Reg32;
+} BPCM_MISC_CONTROL2;
+
+typedef union {
+	struct {
+		uint32_t gphy_iddq_bias:1;	/* 00 */
+		uint32_t gphy_ext_pwr_down:1;	/* 01 */
+		uint32_t gphy_force_dll_en:1;	/* 02 */
+		uint32_t gphy_iddq_global_pwr:1;	/* 03 */
+		uint32_t serdes_iddq:1;	/* 04 */
+		uint32_t serdes_pwrdwn:1;	/* 05 */
+		uint32_t reserved0:2;	/* 07:06 */
+		uint32_t serdes_refclk_sel:3;	/* 10:08 */
+		uint32_t reserved1:5;	/* 15:11 */
+		uint32_t pll_clk125_250_sel:1;	/* 16 */
+		uint32_t pll_mux_clk_250_sel:1;	/* 17 */
+		uint32_t reserved2:14;	/* 31:18 */
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_CNTL;
+
+typedef union {
+	struct {
+		uint32_t field;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_SGPHY_STATUS;
+
+typedef union {
+	struct {
+		uint32_t cpu_reset_n:8;	// 07:00    R/W
+		uint32_t c0l2_reset:1;	// 08:08    R/W
+		uint32_t c1l2_reset:1;	// 09:09    R/W
+		uint32_t reserved0:6;	// 15:10    R/O
+		uint32_t cpu_bpcm_init_on:8;	// 23:16    R/W
+		uint32_t c0l2_bpcm_init_on:1;	// 24:24    R/W
+		uint32_t c1l2_bpcm_init_on:1;	// 25:25    R/W
+		uint32_t ubus_sr:1;	// 26:26    R/W
+		uint32_t cci_sr:1;	// 27:27    R/W
+		uint32_t webcores_sr:1;	// 28:28    R/W
+		uint32_t hw_done:1;	// 29:29    R/O
+		uint32_t sw_done:1;	// 30:30    R/W
+		uint32_t start:1;	// 31:31    R/W
+	} Bits;
+	uint32_t Reg32;
+} ARM_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t mem_pwr_ok:1;	// 00:00    R/W
+		uint32_t mem_pwr_on:1;	// 01:01    R/W
+		uint32_t mem_clamp_on:1;	// 02:02    R/W
+		uint32_t reserved2:1;	// 03:03    R/W
+		uint32_t mem_pwr_ok_status:1;	// 04:04    R/O
+		uint32_t mem_pwr_on_status:1;	// 05:05    R/O
+		uint32_t reserved1:2;	// 07:06    R/W
+		uint32_t mem_pda:4;	// 11:08    R/W only LS bit for CPU0/1, all four bits for neon_l2
+		uint32_t reserved0:3;	// 14:12    R/W
+		uint32_t clamp_on:1;	// 15:15    R/W
+		uint32_t pwr_ok:4;	// 19:16    R/W ditto
+		uint32_t pwr_on:4;	// 23:20    R/W ditto
+		uint32_t pwr_ok_status:4;	// 27:24    R/O ditto
+		uint32_t pwr_on_status:4;	// 31:28    R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
+	} Bits;
+	uint32_t Reg32;
+} ARM_CPUx_PWR_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t resetb:1;	// 00:00
+		uint32_t post_resetb:1;	// 01:01
+		uint32_t pwrdwn:1;	// 02:02
+		uint32_t master_reset:1;	// 03:03
+		uint32_t pwrdwn_ldo:1;	// 04:04
+		uint32_t iso:1;	// 05:05 // only used in afepll
+		uint32_t reserved0:2;	// 07:06
+		uint32_t ldo_ctrl:6;	// 13:08
+		uint32_t reserved1:1;	// 14:14
+		uint32_t hold_ch_all:1;	// 15:15
+		uint32_t reserved2:4;	// 16:19
+		uint32_t byp_wait:1;	// 20:20 // only used in b15pll
+		uint32_t reserved3:11;	// 21:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t fb_offset:12;	// 11:00
+		uint32_t fb_phase_en:1;	// 12:12
+		uint32_t _8phase_en:1;	// 13:13
+		uint32_t sr:18;	// 31:14
+	} Bits;
+	uint32_t Reg32;
+} PLL_PHASE_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t ndiv_frac:20;	// 29:10
+		uint32_t reserved0:1;	// 30
+		uint32_t ndiv_override:1;	// 31
+	} Bits;
+	uint32_t Reg32;
+} PLL_NDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:3;	// 02:00
+		uint32_t reserved0:28;	// 30:03
+		uint32_t ndiv_pdiv_override:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_PDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv0:8;	// 07:00
+		uint32_t enableb_ch0:1;	// 08:08
+		uint32_t hold_ch0:1;	// 09:09
+		uint32_t load_en_ch0:1;	// 10:10
+		uint32_t mdel0:1;	// 11:11
+		uint32_t reserved0:3;	// 14:12
+		uint32_t mdiv_override0:1;	// 15:15
+		uint32_t mdiv1:8;	// 23:16
+		uint32_t enableb_ch1:1;	// 24:24
+		uint32_t hold_ch1:1;	// 25:25
+		uint32_t load_en_ch1:1;	// 26:26
+		uint32_t mdel1:1;	// 27:27
+		uint32_t reserved1:3;	// 30:28
+		uint32_t mdiv_override1:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_CHCFG_REG;
+
+typedef union {
+	struct {
+		uint32_t reserved0:4;	// 03:00
+		uint32_t ka:3;	// 06:04
+		uint32_t reserved1:1;	// 07:07
+		uint32_t ki:3;	// 10:08
+		uint32_t reserved2:1;	// 11:11
+		uint32_t kp:4;	// 15:12
+		uint32_t ssc_step:16;	// 31:16
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP0_REG;
+
+typedef union {
+	struct {
+		uint32_t ssc_limit:22;	// 21:00
+		uint32_t reserved0:2;	// 23:22
+		uint32_t ssc_clkdiv:4;	// 27:24
+		uint32_t ssc_status:1;	// 28:28
+		uint32_t reserved1:2;	// 30:29
+		uint32_t ssc_mode:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_LOOP1_REG;
+
+typedef union {
+	struct {
+		uint32_t fdco_ctrl_bypass:16;	// 15:00
+		uint32_t fdco_bypass_en:1;	// 16:16
+		uint32_t fdco_dac_sel:1;	// 17:17
+		uint32_t state_reset:1;	// 18:18
+		uint32_t state_mode:2;	// 20:19
+		uint32_t state_sel:3;	// 23:21
+		uint32_t state_update:1;	// 24:24
+		uint32_t dco_en:1;	// 25:25
+		uint32_t dco_div2_div4:1;	// 26:26
+		uint32_t dco_bias_boost:1;	// 27:27
+		uint32_t bb_en:1;	// 28:28
+		uint32_t t2d_offset:3;	// 31:29
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG0_REG;
+
+typedef union {
+	struct {
+		uint32_t t2d_offset_msb:1;	// 00:00
+		uint32_t t2d_clk_enable:1;	// 01:01
+		uint32_t t2d_clk_sel:1;	// 02:02
+		uint32_t kpp:4;	// 06:03
+		uint32_t pwm_ctrl:2;	// 08:07
+		uint32_t port_reset_mode:2;	// 10:09
+		uint32_t byp2_en:1;	// 11:11
+		uint32_t byp1_en:1;	// 12:12
+		uint32_t ref_diff_sel:1;	// 13:13
+		uint32_t ki_startlow:1;	// 14:14
+		uint32_t en_500ohm:1;	// 15:15
+		uint32_t refd2c_bias:3;	// 18:16
+		uint32_t post_div2_div3:1;	// 19:19
+		uint32_t ki_boost:1;	// 20:20
+		uint32_t reserved0:11;	// 31:21
+	} Bits;
+	uint32_t Reg32;
+} PLL_CFG1_REG;
+
+typedef union {
+	struct {
+		uint32_t en_cml:3;	// 02:00
+		uint32_t tri_en:1;	// 03:03
+		uint32_t test_sel:3;	// 06:04
+		uint32_t test_en:1;	// 07:07
+		uint32_t reserved0:24;
+	} Bits;
+	uint32_t Reg32;
+} PLL_OCTRL_REG;
+
+typedef union {
+	struct {
+		uint32_t out:12;	// 11:00
+		uint32_t reserved:19;	// 30:12
+		uint32_t lock:1;	// 31:31
+	} Bits;
+	uint32_t Reg32;
+} PLL_STAT_REG;
+
+typedef union {
+	struct {
+		uint32_t ndiv_int:10;	// 09:00
+		uint32_t reserved0:2;	// 11:10
+		uint32_t ndiv_frac:20;	// 31:12    
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECNDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t pdiv:4;	// 03:00
+		uint32_t reserved0:12;	// 15:04
+		uint32_t mdiv0:8;	// 23:16
+		uint32_t mdiv1:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECPDIV_REG;
+
+typedef union {
+	struct {
+		uint32_t mdiv2:8;	// 07:00
+		uint32_t mdiv3:8;	// 15:08
+		uint32_t mdiv4:8;	// 23:16
+		uint32_t mdiv5:8;	// 31:24
+	} Bits;
+	uint32_t Reg32;
+} PLL_DECCH25_REG;
+
+typedef union {
+	struct {
+		uint32_t manual_clk_en:1;
+		uint32_t manual_reset_ctl:1;
+		uint32_t freq_scale_used:1;	// R/O
+		uint32_t dpg_capable:1;	// R/O
+		uint32_t manual_mem_pwr:2;
+		uint32_t manual_iso_ctl:1;
+		uint32_t manual_ctl:1;
+		uint32_t dpg_ctl_en:1;
+		uint32_t pwr_dn_req:1;
+		uint32_t pwr_up_req:1;
+		uint32_t mem_pwr_ctl_en:1;
+		uint32_t blk_reset_assert:1;
+		uint32_t mem_stby:1;
+		uint32_t reserved:5;
+		uint32_t pwr_cntl_state:5;
+		uint32_t freq_scalar_dyn_sel:1;	// R/O
+		uint32_t pwr_off_state:1;	// R/O
+		uint32_t pwr_on_state:1;	// R/O
+		uint32_t pwr_good:1;	// R/O
+		uint32_t dpg_pwr_state:1;	// R/O
+		uint32_t mem_pwr_state:1;	// R/O
+		uint32_t iso_state:1;	// R/O
+		uint32_t reset_state:1;	// R/O
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONTROL;
+
+typedef union {
+	struct {
+		uint32_t pwr_ok_delay_sel:3;
+		uint32_t pwk_ok_thresh:2;
+		uint32_t reserved:3;
+		uint32_t iso_on_delay:4;
+		uint32_t iso_off_delay:4;
+		uint32_t clock_on_delay:4;
+		uint32_t clock_off_delay:4;
+		uint32_t reset_on_delay:4;
+		uint32_t reset_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG1;
+
+typedef union {
+	struct {
+		uint32_t delay_prescale_sel:3;
+		uint32_t slew_prescale_sel:3;
+		uint32_t reserved:6;
+		uint32_t dpgn_on_delay:4;
+		uint32_t dpg1_on_delay:4;
+		uint32_t dpg_off_delay:4;
+		uint32_t mem_on_delay:4;
+		uint32_t mem_off_delay:4;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_PWR_ZONE_N_CONFIG2;
+
+typedef union {
+	struct {
+		uint32_t fs_bypass_en:1;
+		uint32_t gear_sel:1;
+		uint32_t use_dyn_gear_sel:1;
+		uint32_t reserved2:1;
+		uint32_t low_gear_div:3;
+		uint32_t high_gear_div:3;
+		uint32_t reserved:22;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
+
+typedef struct {
+	BPCM_PWR_ZONE_N_CONTROL control;
+	BPCM_PWR_ZONE_N_CONFIG1 config1;
+	BPCM_PWR_ZONE_N_CONFIG2 config2;
+	uint32_t reserved0;
+	uint32_t timer_control;
+	uint32_t timer_status;
+	uint32_t reserved1[2];
+} BPCM_ZONE;
+
+#define BPCMZoneOffset(reg)	offsetof(BPCM_ZONE,reg)
+#define BPCMZoneRegOffset(reg)	(BPCMZoneOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t pmb_Addr:8;
+		uint32_t hw_rev:8;
+		uint32_t module_id:16;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_ID_REG;
+
+typedef union {
+	struct {
+		uint32_t num_zones:8;
+		uint32_t sr_reg_bits:8;
+		uint32_t pllType:2;
+		uint32_t reserved0:1;
+		uint32_t ubus:1;
+		uint32_t reserved1:12;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CAPABILITES_REG;
+
+typedef union {
+	struct {
+		uint32_t ctrl_eswap:4;
+		uint32_t reserved0:4;
+		uint32_t ctrl_cd:4;
+		uint32_t reserved1:4;
+		uint32_t ctrl_seclev:8;
+		uint32_t reqout_seclev:8;
+	} Bits;
+	uint32_t Reg32;
+} BPCM_UBUS_CTRL_REG;
+
+typedef union {
+	struct {
+		uint64_t addr_in:24;
+		uint64_t addr_out:24;
+		uint64_t pid:8;
+		uint64_t size:5;
+		uint64_t cmddta:1;
+		uint64_t en:2;
+	} Bits;
+	struct {
+		uint32_t word0;
+		uint32_t word1;
+	} Regs32;
+	uint64_t Reg64;
+} BPCM_UBUS_CFG_REG;
+
+// There is a 20-bit address used to access any given BPCM register.  The upper 8-bits
+// is the device address and the lower 12-bits is used to represent the BPCM register
+// set for that device.  32-bit registers are allocated on 4-byte boundaries
+// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
+// Thus, to get the actual address of any given register within the device's address
+// space, I'll use the "C" offsetof macro and divide the result by 4
+// e.g.:
+// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL);    // yields the byte offset of the target register
+// int regAddress = regOffset/4;                                // yields the 32-bit word offset of the target register
+// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
+// (address of the BPCM device) and register offset (like regOffset above).  The offset
+// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
+// device address will serve as the upper 8-bits of the actual address.
+typedef struct {
+	// PMB-slave:
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	// BPCM
+	uint32_t control;	// offset 0x10, PMB reg index 4
+	BPCM_SR_CONTROL sr_control;	// offset 0x14, PMB reg index 5
+	uint32_t reserved1[2];	// offset 0x18, PMB reg index 6/7
+	// Client-specific registers
+	uint32_t client_specific[24];	// offset 0x20, PMB reg index 8..31
+	// Zones
+	BPCM_ZONE zones[];	// offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1))
+} BPCM_REGS;			// total offset space = 4096
+
+#define BPCMOffset(reg)		offsetof(BPCM_REGS,reg)
+#define BPCMRegOffset(reg)	(BPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08, actual offset = 2
+	uint32_t cfg_control;	// offset = 0x10, actual offset = 4
+	BPCM_SR_CONTROL sr_control;	// offset = 0x14, actual offset = 5
+	uint32_t reserved1[6];	// offset = 0x18, actual offset = 6
+	ARM_CONTROL_REG arm_control;	// offset = 0x30, actual offset = 12
+	uint32_t biu_clk_control0;	// offset = 0x34, actual offset = 13
+	uint32_t tbd[18];	// offset = 0x38, actual offset = 14
+	BPCM_ZONE zones;	// offset = 0x80, actual offset = 32
+} ARM_BPCM_REGS;
+#define ARMBPCMOffset(reg)  offsetof(ARM_BPCM_REGS,reg)
+#define ARMBPCMRegOffset(reg)   (ARMBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04
+	uint32_t reserved0[6];	// offset = 0x08
+	PLL_CTRL_REG resets;	// offset = 0x20
+	PLL_CFG0_REG cfg0;	// offset = 0x24
+	PLL_CFG1_REG cfg1;	// offset = 0x28
+	PLL_NDIV_REG ndiv;	// offset = 0x2c
+	PLL_PDIV_REG pdiv;	// offset = 0x30
+	PLL_LOOP0_REG loop0;	// offset = 0x34
+	uint32_t reserved1;	// offset = 0x38
+	PLL_LOOP1_REG loop1;	// offset = 0x3c
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x40
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x44
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x48
+	PLL_STAT_REG stat;	// offset = 0x4c
+	uint32_t strap;		// offset = 0x50
+	PLL_DECNDIV_REG decndiv;	// offset = 0x54
+	PLL_DECPDIV_REG decpdiv;	// offset = 0x58
+	PLL_DECCH25_REG decch25;	// offset = 0x5c
+} PLL_CLASSIC_BPCM_REGS;
+
+#define PLLCLASSICBPCMOffset(reg)  offsetof(PLL_CLASSIC_BPCM_REGS,reg)
+#define PLLCLASSICBPCMRegOffset(reg)   (PLLCLASSICBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t reserved0[2];	// offset = 0x08..0x0c, actual offset 2..3
+	PLL_CTRL_REG resets;	// offset = 0x10, actual offset = 4
+	PLL_CFG0_REG cfg0;	// offset = 0x14, actual offset = 5
+	PLL_CFG1_REG cfg1;	// offset = 0x18, actual offset = 6
+	PLL_NDIV_REG ndiv;	// offset = 0x1c, actual offset = 7
+	PLL_PDIV_REG pdiv;	// offset = 0x20, actual offset = 8
+	PLL_LOOP0_REG loop0;	// offset = 0x24, actual offset = 9
+	PLL_LOOP1_REG loop1;	// offset = 0x28, actual offset = a
+	PLL_CHCFG_REG ch01_cfg;	// offset = 0x2c, actual offset = b
+	PLL_CHCFG_REG ch23_cfg;	// offset = 0x30, actual offset = c
+	PLL_CHCFG_REG ch45_cfg;	// offset = 0x34, actual offset = d
+	PLL_OCTRL_REG octrl;	// offset = 0x38, actual offset = e
+	PLL_STAT_REG stat;	// offset = 0x3c, actual offset = f
+	uint32_t strap;		// offset = 0x40, actual offset = 0x10
+	PLL_DECNDIV_REG decndiv;	// offset = 0x44, actual offset = 0x11
+	PLL_DECPDIV_REG decpdiv;	// offset = 0x48, actual offset = 0x12
+	PLL_DECCH25_REG decch25;	// offset = 0x4c, actual offset = 0x13
+} PLL_BPCM_REGS;
+
+#define PLLBPCMOffset(reg)	offsetof(PLL_BPCM_REGS,reg)
+#define PLLBPCMRegOffset(reg)	(PLLBPCMOffset(reg) >> 2)
+
+typedef union {
+	struct {
+		uint32_t dac_data:10;	// [09:00]
+		uint32_t vavs_minb0:1;	// [10:10] - R/O iVDDC <= Vmin0
+		uint32_t vavs_minb1:1;	// [11:11] - R/O iVDDC <= Vmin1
+		uint32_t vavs_warnb0:1;	// [12:12] - R/O iVDDC <= Vwarn0
+		uint32_t vavs_warnb1:1;	// [13:13] - R/O iVDDC <= Vwarn1
+		uint32_t vavs_maxb0:1;	// [14:14] - R/O iVDDC <= Vmax0
+		uint32_t vavs_maxb1:1;	// [15:15] - R/O iVDDC <= Vmax1
+		uint32_t adc_data:10;	// [25:16] - R/O ADC output data in offset binary format
+		uint32_t adc_data_valid:1;	// [26:26] - R/O
+		uint32_t reserved:5;	// [31:27] - R/O 
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_DATA_REG;
+
+typedef union {
+	// little endian - from page 5 of "ANA_VTMON_TS16FF_S0 & ANA_VTMON_PAD_TS16FF_Sx Module Specification"
+	// defaut value = 0x00000001
+	struct {
+		uint32_t bg_adj:3;	// [02:00] - default = 1
+		uint32_t vtest_sel:4;	// [06:03] - VTest = i_VDCC * (<value>+1)/20, default = 0
+		uint32_t rmon_sel:3;	// [09:07]
+		uint32_t mode:3;	// [12:10]
+		uint32_t adc_insel:2;	// [14:13] - only used in expert mode (mode = 0b111)
+		uint32_t dac_en:1;	// [15:15] - only used in expert mode (mode = 0b111)
+		uint32_t con_pad:1;	// [16:16] - only used in expert mode (mode = 0b111)
+		uint32_t burnin_en:1;	// [17:17] - only used in expert mode (mode = 0b111)
+		uint32_t reserved:1;	// [18:18]
+		uint32_t vdccmon_refadj_max1:1;	// [19:19]
+		uint32_t vdccmon_refadj_min0:4;	// [23:20]
+		uint32_t vdccmon_refadj_min1:3;	// [26:24]
+		uint32_t dac_reset:1;	// [27:27]
+		uint32_t dac_set:1;	// [28:28]
+		uint32_t vdccmon_refadj_max0:3;	// [31:29]
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_CONTROL_REG;
+
+typedef union {
+	struct {
+		uint32_t rstb:1;	// [00:00] - low active.  default = 0 (i.e. in reset)
+		uint32_t pwr_dn:1;	// [01:01] - high-active.  default = 1 (i.e. powered down)
+		uint32_t clk_en:1;	// [02:02]
+		uint32_t reserved0:1;	// [03:03]
+		uint32_t sel:3;	// [06:04] - see enum below - reset value = 0
+		uint32_t reserved1:1;	// [07:07]
+		uint32_t clk_div:5;	// [12:08] - value needed to divide pm_clk by (2*clk_div) to generate a 5MHz clock
+		uint32_t reserved2:19;	// [31:13]
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_CONFIG_STATUS_REG;
+
+typedef union {
+	struct {
+		uint32_t accum_en:1;	// [00:00]
+		uint32_t round_en:1;	// [01:01] defaults to 1 (rounding enabled)
+		uint32_t reserved1:6;	// [07:02]
+		uint32_t skip_len:4;	// [11:08] how many samples to skip prior to starting averaging, default = 3
+		uint32_t reserved0:20;	// [31:12]
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_ACQ_CONFIG_REG;
+
+typedef union {
+	struct {
+		uint32_t warn_threshold:10;	// [09:00] - in ADC counts
+		uint32_t warn_en:1;	// [10:10]
+		uint32_t reserved0:3;	// [13:11]
+		uint32_t clear_warn:1;	// [14:14] - Write only
+		uint32_t warn:1;	// [15:15] - Read only
+		uint32_t reset_threshold:10;	// [25:16] - in ADC counts
+		uint32_t reset_en:1;	// [26:26]
+		uint32_t reserved1:3;	// [29:27]
+		uint32_t clear_reset:1;	// [30:30] - Write only
+		uint32_t reset:1;	// [31:31] - Read only
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_TEMP_WARN_RESET_REG;
+
+typedef union {
+	struct {
+		uint32_t reset_value:10;	// [09:00]
+		uint32_t reserved:22;	// [31:10]
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_RESET_TEMP_REG;
+
+typedef union {
+	struct {
+		uint32_t value:10;	// [09:00] - there are <meas_len> fractional bits
+		uint32_t reserved0:8;	// [17:10]
+		uint32_t valid:1;	// [18:18]
+		uint32_t busy:1;	// [19:19]
+		uint32_t reserved1:4;	// [23:20]
+		uint32_t meas_len:3;	// [26:24]  #samples = 2^<value>
+		uint32_t reserved2:4;	// [30:27]
+		uint32_t enable:1;	// [31:31]
+	} Bits;
+	uint32_t Reg32;
+} APVTMON_ACCUM_REG;
+
+typedef union {
+	struct {
+		uint32_t sel:6;	// [05:00] - ring oscillator select (0..35)
+		uint32_t reserved2:2;	// [07:06]
+		uint32_t srm_ind_en:1;	// [08:08]
+		uint32_t srm_ind_od:1;	// [09:09]
+		uint32_t srm_ind_sel:2;	// [11:10]
+		uint32_t reserved1:4;	// [15:12]
+		uint32_t out:1;	// [16:16]
+		uint32_t all_idl_low_oscs:1;	// [17:17]
+		uint32_t all_idl_hi_oscs:1;	// [18:18]
+		uint32_t reserved0:13;	// [31:19]
+	} Bits;
+	uint32_t Reg32;
+} ROSC_CTRL_STS_REG;
+
+typedef union {
+	struct {
+		uint32_t count:16;	// [15:00]
+		uint32_t valid:1;	// [16:16]
+		uint32_t too_lo:1;	// [17:17] - count <= thresh_lo (only when THRESH_EN == 1)
+		uint32_t too_hi:1;	// [18:18] - count <= thresh_hi (only when THRESH_EN == 1)
+		uint32_t reserved0:5;	// [23:19]
+		uint32_t continuous:1;	// [24:24]
+		uint32_t thresh_en:1;	// [25:25] - enable threshold detection
+		uint32_t ectr_en:1;	// [26:26] - enable counter
+		uint32_t src_en:1;	// [27:27] - enable event source (may not do anything???)
+		uint32_t meas_len:4;	// [31:28] - interval = 2^(<meas_len>+1)
+	} Bits;
+	uint32_t Reg32;
+} ECTR_CTRL_STS_REG;
+
+typedef union {
+	struct {
+		uint32_t thresh_lo:16;	// [15:00]
+		uint32_t thresh_hi:16;	// [31:16]
+	} Bits;
+	uint32_t Reg32;
+} ECTR_THRESH_REG;
+
+typedef struct {
+	ECTR_CTRL_STS_REG count_reg;
+	ECTR_THRESH_REG thresh_reg;
+} ROSC_REGS;
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[2];	// offset 0x08, PMB reg index 2/3
+	uint32_t reserved1[12];	// offset 0x10, PMB reg index 4-15 (future proofing )
+	APVTMON_CONTROL_REG control;	// offset 0x40, PMB reg index 16
+	APVTMON_CONFIG_STATUS_REG config;	// offset 0x44, PMB reg index 17
+	APVTMON_DATA_REG adc_data;	// offset 0x48, PMB reg index 18
+	uint32_t reserved2;	// offset 0x4c, PMB reg index 19
+	APVTMON_ACQ_CONFIG_REG accum_config;	// offset 0x50, PMB reg index 20
+	APVTMON_TEMP_WARN_RESET_REG warn_rst;	// offset 0x54, PMB reg index 21
+	uint32_t reserved3[2];	// offset 0x58, PMB reg index 23
+	APVTMON_ACCUM_REG acq_accum_regs[8];	// offset 0x60, PMB reg index 24-31
+	ROSC_CTRL_STS_REG rosc_ctrl_sts;	// offset 0x80, PMB reg index 32
+	uint32_t rosc_en_lo;	// offset 0x84, PMB reg index 33
+	uint32_t rosc_en_hi;	// offset 0x88, PMB reg index 34
+	uint32_t rosc_idle_lo;	// offset 0x8c, PMB reg index 35
+	uint32_t rosc_idle_hi;	// offset 0x90, PMB reg index 36
+	uint32_t reserved4[3];	// offset 0x94, PMB reg index 37-39
+	ROSC_REGS ectr_regs;	// offset 0xa0, PMB reg index 40/41
+} PVTMON_REGS;
+// retrieves the BYTE offset of a PVTMON register:
+#define PVTMON_OFFSET(reg) (offsetof(PVTMON_REGS,reg)>>2)
+
+typedef struct {
+// PMB-slave
+	BPCM_ID_REG id_reg;	// offset 0x00, PMB reg index 0
+	BPCM_CAPABILITES_REG capabilities;	// offset 0x04, PMB reg index 1
+	uint32_t reserved0[6];	// offset 0x08, PMB reg index 2-7
+	// ROSC registers
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset 0x20, PMB reg index 8
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset 0x24, PMB reg index 9
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset 0x28, PMB reg index 10
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset 0x2c, PMB reg index 11
+	BPCM_AVS_PWD_CONTROL pwd_ctrl;	// offset 0x30, PMB reg index 12
+	BPCM_PWD_ACCUM_CONTROL pwd_accum;	// offset 0x34, PMB reg index 13
+} ARS_REGS;
+// retrieves the BYTE offset of an ARS register:
+#define ARS_OFFSET(reg) (offsetof(ARS_REGS, reg)>>2)
+
+typedef struct {
+	BPCM_UBUS_ID_REG id_reg;	/* offset = 0x00, actual offset = 0 */
+	BPCM_UBUS_CAPABILITES_REG capabilities;	/* offset = 0x04, actual offset = 1 */
+	uint32_t reserved0;	/* offset = 0x08, actual offset = 2 */
+	BPCM_UBUS_CTRL_REG ctrl;	/* offset = 0x0c, actual offset = 3 */
+	BPCM_UBUS_CFG_REG cfg[4];	/* offset = 0x10..0x2c, actual offset = 4..11 */
+} BPCM_UBUS_REG;
+
+#define UBUSBPCMOffset(reg)	offsetof(BPCM_UBUS_REG,reg)
+#define UBUSBPCMRegOffset(reg)	(UBUSBPCMOffset(reg) >> 2)
+
+typedef struct {
+	BPCM_ID_REG id_reg;	// offset = 0x00, actual offset = 0
+	BPCM_CAPABILITES_REG capabilities;	// offset = 0x04, actual offset = 1
+	uint32_t control;	// offset = 0x08, actual offset = 2
+	BPCM_STATUS_REG status;	// offset = 0x0c, actual offset = 3
+	BPCM_AVS_ROSC_CONTROL_REG rosc_control;	// offset = 0x10, actual offset = 4
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h;	// offset = 0x14, actual offset = 5
+	BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s;	// offset = 0x18, actual offset = 6
+	BPCM_AVS_ROSC_COUNT rosc_count;	// offset = 0x1c, actual offset = 7
+	BPCM_AVS_PWD_CONTROL pwd_control;	// offset = 0x20, actual offset = 8
+	uint32_t bpcm_ctrl;	// offset = 0x24, actual offset = 9
+	uint32_t clkrst_control;	// offset = 0x28, actual offset = 10
+	uint32_t ext_observe_ctrl;	// offset = 0x2c, actual offset = 11
+	uint32_t reserved0[2];	// offset = 0x30-0x34, actual offset 12-13
+	uint32_t xtal_control;	// offset = 0x38, actual offset = 14
+	uint32_t clkrst_stat;	// offset = 0x3c, actual offset = 15
+	uint32_t reserved1;	// offset = 0x40, actual offset = 16
+	uint32_t clkrst_ena_clk_31_0;	// offset = 0x44, actual offset = 17
+	uint32_t clkrst_ena_clk_63_32;	// offset = 0x48, actual offset = 18
+	uint32_t clkrst_ena_clk_95_64;	// offset = 0x4c, actual offset = 19
+	uint32_t reserved2[11];	// offset = 0x50-0x78, actual offset = 20-30
+	uint32_t clkrst_ena_reset_31_0;	// offset = 0x7c, actual offset = 31
+	uint32_t clkrst_ena_reset_63_32;	// offset = 0x80, actual offset = 32
+	uint32_t clkrst_pll_observe_clk;	// offset = 0x84, actual offset = 33
+	uint32_t clkrst_ref_cnt_thresh;	// offset = 0x88, actual offset = 34
+	uint32_t clkrst_pll_clk_low_th;	// offset = 0x8c, actual offset = 35
+	uint32_t clkrst_pll_clk_hi_th;	// offset = 0x90, actual offset = 36
+	uint32_t clkrst_pll_clk_stat;	// offset = 0x94, actual offset = 37
+	uint32_t clkrst_sticky_bit_stat;	// offset = 0x98, actual offset = 38
+	uint32_t clkrst_clk250_src_sel;	// offset = 0x9c, actual offset = 39
+	uint32_t clkrst_ena_force;	// offset = 0xa0, actual offset = 40
+	uint32_t reserved3;	// offset = 0xa4, actual offset = 41
+	uint32_t pmd_xtal_cntl;	// offset = 0xa8, actual offset = 42
+	uint32_t pmd_xtal_cntl2;	// offset = 0xac, actual offset = 43
+} BPCM_CLKRST_REGS;
+
+#define CLKRSTBPCMOffset(reg)  offsetof(BPCM_CLKRST_REGS, reg)
+#define CLKRSTBPCMRegOffset(reg)   (CLKRSTBPCMOffset(reg) >> 2)
+
+// *************************** macros ******************************
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6878/brom.h b/arch/arm/include/asm/arch-bcm6878/brom.h
new file mode 100644
index 0000000000..147b197334
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6878/brom.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6878_BROM_H
+#define _6878_BROM_H
+
+#define BROM_GEN_BASE          0xff800600
+
+/*
+ * BROM_GEN Register Definition .
+ */
+typedef struct BromGen_ {
+#define	BROM_GEN_SPI_SLV_UNLOCK_MASK	0x1
+#define	BROM_GEN_SPI_SLV_UNLOCK_SHIFT	0x2
+#define BROM_GEN_TAG_UNLOCK_MASK	0x1
+#define BROM_GEN_TAG_UNLOCK_SHIFT	0x1
+		uint32_t secBootCfg;
+		uint32_t bromCrcRevIdLow;
+		uint32_t bromCrcRevIdHigh;
+} BromGen;
+
+#define BROM_GEN ((volatile BromGen * const) BROM_GEN_BASE)
+#define BROM_GEN_JTAG_UNLOCK do {BROM_GEN->secBootCfg |= ((BROM_GEN_SPI_SLV_UNLOCK_MASK<<BROM_GEN_SPI_SLV_UNLOCK_SHIFT) | \
+						(BROM_GEN_TAG_UNLOCK_MASK<<BROM_GEN_TAG_UNLOCK_SHIFT)); }while(0) 
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6878/cpu.h b/arch/arm/include/asm/arch-bcm6878/cpu.h
new file mode 100644
index 0000000000..01e88f7d9f
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6878/cpu.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6878_CPU_H
+#define _6878_CPU_H
+
+#define BOOTLUT_BASE      0xffff0000
+#define BIUCFG_BASE       0x81060000
+
+typedef struct BIUCFG_Access {
+	uint32_t permission;	/* 0x0 */
+	uint32_t reserved0;		/* 0x4 */
+	uint32_t cpu_defeature;	/* 0x8 */
+	uint32_t dbg_security;	/* 0xc */
+	uint32_t rsvd1[36];	/* 0x10 - 0x9f */
+	uint32_t ts_access;	/* 0xa0 - 0xa3 */
+	uint32_t rsvd2[23];	/* 0xa4 - 0xff */
+} BIUCFG_Access;
+
+typedef struct BIUCFG_Cluster {
+	uint32_t permission;	/* 0x0 */
+	uint32_t config;	/* 0x4 */
+	uint32_t status;	/* 0x8 */
+	uint32_t control;	/* 0xc */
+	uint32_t cpucfg;	/* 0x10 */
+	uint32_t dbgrom;	/* 0x14 */
+	uint32_t rsvd1[2];	/* 0x18 - 0x1f */
+	uint32_t rvbar_addr[8];	/* 0x20 - 0x3f */
+	uint32_t rsvd2[48];	/* 0x40 - 0xff */
+} BIUCFG_Cluster;
+
+typedef struct BIUCFG_AuxClkCtrl {
+	uint32_t clk_control;	/* 0x0 */
+	uint32_t clk_ramp;	/* 0x4 */
+	uint32_t clk_pattern;	/* 0x8 */
+	uint32_t rsvd;		/* 0xC */
+} BIUCFG_AuxClkCtrl;
+
+typedef struct BIUCFGux {
+	uint32_t permission;	/* 0 */
+	uint32_t rsvd1[3];	/* 0x04 - 0x0c */
+	BIUCFG_AuxClkCtrl cluster_clkctrl[2];	/* 0x10 - 0x2c */
+	uint32_t rsvd2[52];	/* 0x30 - 0xFF */
+} BIUCFG_Aux;
+
+typedef struct BIUCFG {
+	BIUCFG_Access access;	/* 0x0 - 0xff */
+	BIUCFG_Cluster cluster[1];	/* 0x100 - 0x1ff */
+	uint32_t rsvd1[320];	/* 0x200 - 0x6ff */
+	BIUCFG_Aux aux;		/* 0x700 - 0x7ff */
+	uint32_t rsrvd2[512];	/* 0x800 - 0xfff */
+	uint32_t TSO_CNTCR;	/* 0x1000 */
+	uint32_t rsvd2[2047];	/* 0x1004 - 0x2fff */
+} BIUCFG;
+
+#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6878/ddr.h b/arch/arm/include/asm/arch-bcm6878/ddr.h
new file mode 100644
index 0000000000..308710030f
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6878/ddr.h
@@ -0,0 +1,510 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6878_DDR_H
+#define _6878_DDR_H
+
+#define MEMC_BASE   0x80180000  /* DDR IO Buf Control */
+
+typedef struct AXIInterface {
+   uint32_t CFG;                  /* 0x00 */
+   uint32_t REP_ARB_MODE;         /* 0x04 */
+   uint32_t QUEUE_CFG;            /* 0x08 */
+   uint32_t ESRCID_CFG;           /* 0x0c */
+   uint32_t SRC_QUEUE_CTRL[8];    /* 0x10 */
+   uint32_t SRC_ID_4_QUEUE_CTRL;  /* 0x30 */
+   uint32_t SCRATCH;              /* 0x34 */
+   uint32_t AXI_DEBUG[2];         /* 0x38 */
+} AXIInterface;
+
+typedef struct EDISEngine {
+   uint32_t REV_ID;             /* 0x00 */
+   uint32_t CTRL_TRIG;          /* 0x04 */
+   uint32_t CTRL_MODE;          /* 0x08 */
+   uint32_t CTRL_SIZE;          /* 0x0c */
+   uint32_t CTRL_ADDR_START;    /* 0x10 */
+   uint32_t CTRL_ADDR_START_EXT;/* 0x14 */
+   uint32_t CTRL_ADDR_END;      /* 0x18 */
+   uint32_t CTRL_ADDR_END_EXT;  /* 0x1c */
+   uint32_t CTRL_WRITE_MASKS;   /* 0x20 */
+   uint32_t CTRL_INT_ENABLES;   /* 0x24 */
+   uint32_t unused0[6];         /* 0x28-0x3f */
+   uint32_t STAT_MAIN;          /* 0x40 */
+   uint32_t STAT_WORDS_WRITTEN; /* 0x44 */
+   uint32_t STAT_WORDS_READ;    /* 0x48 */
+   uint32_t STAT_ERROR_COUNT;   /* 0x4c */
+   uint32_t STAT_ERROR_BITS;    /* 0x50 */
+   uint32_t STAT_ADDR_LAST;     /* 0x54 */
+   uint32_t STAT_ADDR_LAST_EXT; /* 0x58 */
+   uint32_t STAT_CLOCK_CYCLES;  /* 0x5c */
+   uint32_t unused1[7];         /* 0x60-0x7b */
+   uint32_t STAT_DEBUG;         /* 0x7c */
+   uint32_t STAT_DATA_PORT[8];  /* 0x80-0x9c */
+   uint32_t GEN_LFSR_STATE[4];  /* 0xa0-0xac */
+   uint32_t GEN_CLOCK;          /* 0xb0 */
+   uint32_t GEN_PATTERN;        /* 0xb4 */
+   uint32_t unused2[2];         /* 0xb8-0xbf */
+   uint32_t BYTELANE_0_CTRL_LO; /* 0xc0 */
+   uint32_t BYTELANE_0_CTRL_HI; /* 0xc4 */
+   uint32_t BYTELANE_1_CTRL_LO; /* 0xc8 */
+   uint32_t BYTELANE_1_CTRL_HI; /* 0xcc */
+   uint32_t BYTELANE_2_CTRL_LO; /* 0xd0 */
+   uint32_t BYTELANE_2_CTRL_HI; /* 0xd4 */
+   uint32_t BYTELANE_3_CTRL_LO; /* 0xd8 */
+   uint32_t BYTELANE_3_CTRL_HI; /* 0xdc */
+   uint32_t BYTELANE_0_STAT_LO; /* 0xe0 */
+   uint32_t BYTELANE_0_STAT_HI; /* 0xe4 */
+   uint32_t BYTELANE_1_STAT_LO; /* 0xe8 */
+   uint32_t BYTELANE_1_STAT_HI; /* 0xec */
+   uint32_t BYTELANE_2_STAT_LO; /* 0xf0 */
+   uint32_t BYTELANE_2_STAT_HI; /* 0xf4 */
+   uint32_t BYTELANE_3_STAT_LO; /* 0xf8 */
+   uint32_t BYTELANE_3_STAT_HI; /* 0xfc */
+} EDISEngine;
+
+typedef struct RangeCtrl {
+   uint32_t CTRL;                /* 0x00 */
+   uint32_t UBUS0_PORT;          /* 0x04 */
+   uint32_t UBUS0_PORT_UPPER;    /* 0x08 */
+   uint32_t BASE;                /* 0x0c */
+   uint32_t BASE_UPPER;          /* 0x10 */
+   uint32_t SECLEC_EN;           /* 0x14 */
+} RangeCtrl;
+
+typedef struct SecureRangeCheckers {
+   uint32_t LOCK;            /* 0x00 */
+   uint32_t LOG_INFO[3];     /* 0x04 - 0x0c */
+   RangeCtrl RANGE_CTRL[8];/* 0x10 - 0xcf */
+   uint32_t unused[12];      /* 0xd0 - 0xff */
+} SecureRangeCheckers;
+
+typedef struct UBUSInterface {
+   uint32_t CFG;                /* 0x00 */
+   uint32_t ESRCID_CFG;         /* 0x04 */
+#define UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT   0x0
+#define UBUSIF_CFG_WRITE_REPLY_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT)
+#define UBUSIF_CFG_WRITE_BURST_MODE_SHIFT   0x1
+#define UBUSIF_CFG_WRITE_BURST_MODE_MASK    (0x1<< UBUSIF_CFG_WRITE_BURST_MODE_SHIFT)
+#define UBUSIF_CFG_INBAND_ERR_MASK_SHIFT    0x2
+#define UBUSIF_CFG_INBAND_ERR_MASK_MASK     (0x1<< UBUSIF_CFG_INBAND_ERR_MASK_SHIFT)
+#define UBUSIF_CFG_OOB_ERR_MASK_SHIFT       0x3
+#define UBUSIF_CFG_OOB_ERR_MASK_MASK        (0x1<< UBUSIF_CFG_OOB_ERR_MASK_SHIFT)
+   uint32_t SRC_QUEUE_CTRL[4];  /* 0x08 - 0x14 */
+   uint32_t REP_ARB_MODE;       /* 0x18 */
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT 0x0
+#define UBUSIF_REP_ARB_MODE_FIFO_MODE_MASK  (0x1<<UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT)
+   uint32_t HPQ_CFG;            /* 0x1c */
+   uint32_t SCRATCH;            /* 0x20 */
+   uint32_t DEBUG_R0;           /* 0x24 */
+   uint32_t unused[6];          /* 0x28-0x3f */
+} UBUSInterface;
+
+typedef struct MEMCControl {
+   uint32_t GLB_VERS;               /* 0x000 */
+   uint32_t GLB_GCFG;               /* 0x004 */
+#define MEMC_GLB_GCFG_DRAM_EN_SHIFT        31
+#define MEMC_GLB_GCFG_DRAM_EN_MASK         (0x1<<MEMC_GLB_GCFG_DRAM_EN_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ_SHIFT      30
+#define MEMC_GLB_GCFG_FORCE_SEQ_MASK       (0x1<<MEMC_GLB_GCFG_FORCE_SEQ_SHIFT)
+#define MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT     29
+#define MEMC_GLB_GCFG_FORCE_SEQ2_MASK      (1<<MEMC_GLB_GCFG_FORCE_SEQ2_SHIFT)
+#define MEMC_GLB_GCFG_RBF_REORDER_SHIFT    28
+#define MEMC_GLB_GCFG_RBF_REORDER_MASK     (1<<MEMC_GLB_GCFG_RBF_REORDER_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT   24
+#define MEMC_GLB_GCFG_PHY_DFI_MODE_MASK    (0x3<<MEMC_GLB_GCFG_PHY_DFI_MODE_SHIFT)
+#define MEMC_GLB_GCFG_PHY_DFI_2X           0x0
+#define MEMC_GLB_GCFG_PHY_DFI_4X           0x1
+#define MEMC_GLB_GCFG_PHY_DFI_8X           0x2
+#define MEMC_GLB_GCFG_DFI_EN_SHIFT         10
+#define MEMC_GLB_GCFG_DFI_EN_MASK          (0x1<<MEMC_GLB_GCFG_DFI_EN_SHIFT)
+#define MEMC_GLB_GCFG_MCLKSRC_SHIFT        9
+#define MEMC_GLB_GCFG_MCLKSRC_MASK         (0x1<<MEMC_GLB_GCFG_MCLKSRC_SHIFT)
+#define MEMC_GLB_GCFG_MEMINITDONE_SHIFT    8
+#define MEMC_GLB_GCFG_MEMINITDONE_MASK     (0x1<<MEMC_GLB_GCFG_MEMINITDONE_SHIFT)
+   uint32_t GLB_MRQ_CFG;            /* 0x008 */
+   uint32_t unused0;                /* 0x00c */
+   uint32_t GLB_FSBL_STATE;         /* 0x010 */
+#define MEMC_GLB_FSBL_DRAM_SIZE_SHIFT      0
+#define MEMC_GLB_FSBL_DRAM_SIZE_MASK       (0xf << MEMC_GLB_FSBL_DRAM_SIZE_SHIFT)
+   uint32_t unused1[3];             /* 0x014 - 0x01f */
+
+   uint32_t SRAM_REMAP_CTRL;        /* 0x020 */
+   uint32_t SRAM_REMAP_CTRL_UPPER;  /* 0x024 */
+   uint32_t SRAM_REMAP_INIT;        /* 0x028 */
+   uint32_t SRAM_REMAP_LOG_INFO_0;  /* 0x02c */
+   uint32_t SRAM_REMAP_LOG_INFO_1;  /* 0x030 */
+   uint32_t SRAM_REMAP_LOG_INFO_2;  /* 0x034 */
+   uint32_t unused2[2];             /* 0x038-0x03f */
+
+   uint32_t RBF_REORDER_0_CFG[16];  /* 0x040 - 0x07f */
+
+   uint32_t INTR2_CPU_STATUS;       /* 0x080 */
+   uint32_t INTR2_CPU_SET;          /* 0x084 */
+   uint32_t INTR2_CPU_CLEAR;        /* 0x088 */
+   uint32_t INTR2_CPU_MASK_STATUS;  /* 0x08c */
+   uint32_t INTR2_CPU_MASK_SET;     /* 0x090 */
+   uint32_t INTR2_CPU_MASK_CLEAR;   /* 0x094 */
+   uint32_t unused3[26];            /* 0x098-0x0ff */
+
+   uint32_t CHN_CFG_CNFG;           /* 0x100 */
+#define MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT            16
+#define MEMC_CHN_CFG_CNFG_CS_MODE_MASK             (0x3 << MEMC_CHN_CFG_CNFG_CS_MODE_SHIFT)
+   uint32_t CHN_CFG_CSST;           /* 0x104 */
+   uint32_t unused4[2];             /* 0x108-0x10f */
+   uint32_t CHN_CFG_ROW00_0;        /* 0x110 */
+   uint32_t CHN_CFG_ROW00_1;        /* 0x114 */
+   uint32_t CHN_CFG_ROW01_0;        /* 0x118 */
+   uint32_t CHN_CFG_ROW01_1;        /* 0x11c */
+   uint32_t CHN_CFG_ROW02_0;        /* 0x120 */
+   uint32_t CHN_CFG_COL00_0;        /* 0x124 */
+   uint32_t CHN_CFG_COL00_1;        /* 0x128 */
+   uint32_t CHN_CFG_COL01_0;        /* 0x12c */
+   uint32_t CHN_CFG_COL01_1;        /* 0x130 */
+   uint32_t CHN_CFG_BNK10;          /* 0x134 */
+   uint32_t CHN_CFG_BG0;            /* 0x138 */
+   uint32_t unused5;                /* 0x13c */
+   uint32_t CHN_CFG_DRAM_SZ_CHK;    /* 0x140 */
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT                          4
+#define MEMC_CHN_CFG_DRAM_SZ_CHK_MASK                           (0xf<<MEMC_CHN_CFG_DRAM_SZ_CHK_SHIFT)
+   uint32_t CHN_CFG_DIAG_SEL;       /* 0x144 */
+   uint32_t unused6[46];            /* 0x148-0x1ff */
+
+   uint32_t CHN_TIM_DCMD;           /* 0x200 */
+   uint32_t CHN_TIM_DMODE_0;        /* 0x204 */
+   uint32_t CHN_TIM_DMODE_2;        /* 0x208 */
+   uint32_t CHN_TIM_CLKS;           /* 0x20c */
+#define MEMC_CHN_TIM_CLKS_REF_RATE_SHIFT          8
+#define MEMC_CHN_TIM_CLKS_REF_DISABLE_SHIFT       31
+   uint32_t CHN_TIM_ODT;            /* 0x210 */
+   uint32_t CHN_TIM_TIM1_0;         /* 0x214 */
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tWL [31:24] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_MASK                            0xff000000
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_SHIFT                           24
+#define MC_CHN_TIM_TIM1_0_TIM1_tWL_DEFAULT                         0x00000004
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRP [23:16] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_MASK                            0x00ff0000
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_SHIFT                           16
+#define MC_CHN_TIM_TIM1_0_TIM1_tRP_DEFAULT                         0x00000006
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tCL [15:08] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_MASK                            0x0000ff00
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_ALIGN                           0
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_BITS                            8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_SHIFT                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tCL_DEFAULT                         0x00000005
+/* MC_CHN_TIM :: TIM1_0 :: TIM1_tRCD [07:00] */
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_MASK                           0x000000ff
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_ALIGN                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_BITS                           8
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_SHIFT                          0
+#define MC_CHN_TIM_TIM1_0_TIM1_tRCD_DEFAULT                        0x00000006
+
+   uint32_t CHN_TIM_TIM1_1;         /* 0x218 */
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_L [31:24] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tCCD_S [23:16] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_1_TIM1_tCCD_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_L [15:08] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_MASK                         0x0000ff00
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_SHIFT                        8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_1 :: TIM1_tRRD_S [07:00] */
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_MASK                         0x000000ff
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_BITS                         8
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_SHIFT                        0
+#define MC_CHN_TIM_TIM1_1_TIM1_tRRD_S_DEFAULT                      0x00000002
+
+   uint32_t CHN_TIM_TIM1_2;         /* 0x21c */
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tFAW [31:24] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_MASK                           0xff000000
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_SHIFT                          24
+#define MC_CHN_TIM_TIM1_2_TIM1_tFAW_DEFAULT                        0x00000000
+/* MC_CHN_TIM :: TIM1_2 :: reserved0 [23:16] */
+#define MC_CHN_TIM_TIM1_2_reserved0_MASK                           0x00ff0000
+#define MC_CHN_TIM_TIM1_2_reserved0_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_reserved0_BITS                           8
+#define MC_CHN_TIM_TIM1_2_reserved0_SHIFT                          16
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRTP [15:08] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_MASK                           0x0000ff00
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_ALIGN                          0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_BITS                           8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_SHIFT                          8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRTP_DEFAULT                        0x00000002
+/* MC_CHN_TIM :: TIM1_2 :: TIM1_tRC [07:00] */
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_MASK                            0x000000ff
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_ALIGN                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_BITS                            8
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_SHIFT                           0
+#define MC_CHN_TIM_TIM1_2_TIM1_tRC_DEFAULT                         0x00000011
+
+   uint32_t CHN_TIM_TIM1_3;         /* 0x220 */
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_L [31:24] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_MASK                         0xff000000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_SHIFT                        24
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_L_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWTR_S [23:16] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_MASK                         0x00ff0000
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_ALIGN                        0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_BITS                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_SHIFT                        16
+#define MC_CHN_TIM_TIM1_3_TIM1_tWTR_S_DEFAULT                      0x00000002
+/* MC_CHN_TIM :: TIM1_3 :: reserved_for_padding0 [15:12] */
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_MASK               0x0000f000
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_ALIGN              0
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_BITS               4
+#define MC_CHN_TIM_TIM1_3_reserved_for_padding0_SHIFT              12
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_L [11:08] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_MASK                          0x00000f00
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_BITS                          4
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_SHIFT                         8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_L_DEFAULT                       0x00000004
+/* MC_CHN_TIM :: TIM1_3 :: TIM1_tWR_S [07:00] */
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_MASK                          0x000000ff
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_ALIGN                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_BITS                          8
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_SHIFT                         0
+#define MC_CHN_TIM_TIM1_3_TIM1_tWR_S_DEFAULT                       0x00000004
+
+   uint32_t CHN_TIM_TIM2;          /* 0x224 */
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2R [31:30] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_MASK                             0xc0000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_BITS                             2
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_SHIFT                            30
+#define MC_CHN_TIM_TIM2_TIM2_tR2R_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: TIM2_tR2W [29:27] */
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_MASK                             0x38000000
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_SHIFT                            27
+#define MC_CHN_TIM_TIM2_TIM2_tR2W_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2R [26:24] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_MASK                             0x07000000
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_BITS                             3
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_SHIFT                            24
+#define MC_CHN_TIM_TIM2_TIM2_tW2R_DEFAULT                          0x00000001
+/* MC_CHN_TIM :: TIM2 :: reserved_for_padding0 [23:22] */
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_MASK                 0x00c00000
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_ALIGN                0
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_BITS                 2
+#define MC_CHN_TIM_TIM2_reserved_for_padding0_SHIFT                22
+/* MC_CHN_TIM :: TIM2 :: TIM2_tW2W [21:18] */
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_MASK                             0x003c0000
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_BITS                             4
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_SHIFT                            18
+#define MC_CHN_TIM_TIM2_TIM2_tW2W_DEFAULT                          0x00000000
+/* MC_CHN_TIM :: TIM2 :: reserved1 [17:16] */
+#define MC_CHN_TIM_TIM2_reserved1_MASK                             0x00030000
+#define MC_CHN_TIM_TIM2_reserved1_ALIGN                            0
+#define MC_CHN_TIM_TIM2_reserved1_BITS                             2
+#define MC_CHN_TIM_TIM2_reserved1_SHIFT                            16
+/* MC_CHN_TIM :: TIM2 :: TIM2_tAL [15:12] */
+#define MC_CHN_TIM_TIM2_TIM2_tAL_MASK                              0x0000f000
+#define MC_CHN_TIM_TIM2_TIM2_tAL_ALIGN                             0
+#define MC_CHN_TIM_TIM2_TIM2_tAL_BITS                              4
+#define MC_CHN_TIM_TIM2_TIM2_tAL_SHIFT                             12
+#define MC_CHN_TIM_TIM2_TIM2_tAL_DEFAULT                           0x00000000
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_MASK                             0x00000fff
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_ALIGN                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_BITS                             12
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_SHIFT                            0
+#define MC_CHN_TIM_TIM2_TIM2_tRFC_DEFAULT                          0x00000014
+
+   uint32_t unused7[2];            /* 0x228 - 0x22f */
+   uint32_t CHN_TIM_PHY_ST;         /* 0x230 */
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP       0x1
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_HW_RESET       0x2
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_SW_RESET       0x4
+#define MEMC_CHN_TIM_PHY_ST_PHY_ST_READY          0x10
+   uint32_t CHN_TIM_DRAM_CFG;       /* 0x234 */
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT           12
+#define MEMC_CHN_TIM_DRAM_CFG_HDP_MASK            (0x1<<MEMC_CHN_TIM_DRAM_CFG_HDP_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT     10
+#define MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_MASK      (0x1<<MEMC_CHN_TIM_DRAM_CFG_2TADDRCMD_SHIFT)
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT      0
+#define MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_MASK       (0xf<<MEMC_CHN_TIM_DRAM_CFG_DRAMTYPE_SHIFT)
+#define MC_DRAM_CFG_DDR3                          0x1
+   uint32_t CHN_TIM_STAT;           /* 0x238 */
+   uint32_t CHN_TIM_PERF;           /* 0x23c */
+
+   uint32_t CHN_TIM_PKM_CFG;        /* 0x240 */
+   uint32_t CHN_TIM_AB4_CFG;        /* 0x244 */
+   uint32_t unused8[2];             /* 0x248 */
+   uint32_t CHN_TIM_AB4_ACT_PRI;    /* 0x250 */
+   uint32_t CHN_TIM_AB4_PRI_OPEN;   /* 0x254 */
+   uint32_t CHN_TIM_AB4_PRI_CLOSED; /* 0x258 */
+   uint32_t CHN_TIM_AUTO_SELF_REF;  /* 0x25c */
+   uint32_t CHN_TIM_AUTO_ZQCS;      /* 0x260 */
+   uint32_t CHN_TIM_TIM3;           /* 0x264 */
+   uint32_t unused9[38];            /* 0x268-0x2ff */
+
+   uint32_t ARB_CFG;                /* 0x300 */
+   uint32_t unused10;               /* 0x304 */
+   uint32_t ARB_SP_PR[2];           /* 0x308 */
+   uint32_t ARB_BKT_CFG_CPU_WR[4];  /* 0x310 */
+   uint32_t ARB_BKT_CFG_CPU_RD[4];  /* 0x320 */
+   uint32_t unused11[8];            /* 0x330 */
+   uint32_t ARB_BKT_CFG_EDIS[4];    /* 0x350 */
+   uint32_t ARB_BKT_CFG_UBUS[32];   /* 0x360 */
+   uint32_t unused11a[4];           /* 0x3e0 */
+   uint32_t ARB_RATE_OK_WEIGHT[2];  /* 0x3f0 */
+   uint32_t ARB_RATE_FAIL_WEIGHT[2]; /* 0x3f4 */
+
+   UBUSInterface UBUSIF0;         /* 0x400-0x43f */
+   uint32_t unused12[32];           /* 0x440 */
+   AXIInterface AXIWIF;           /* 0x4c0 */
+
+   uint32_t unused13[192];          /* 0x500-0x7ff */
+
+   EDISEngine EDIS_0;             /* 0x800 */
+   uint32_t unused14[64];           /* 0x900 */
+
+   uint32_t STATS_CTRL;             /* 0xa00 */
+   uint32_t STATS_TIMER_CFG;        /* 0xa04 */
+   uint32_t STATS_TIMER_COUNT;      /* 0xa08 */
+   uint32_t STATS_TOTAL_SLICE;      /* 0xa0c */
+   uint32_t STATS_TOTAL_PACKET;     /* 0xa10 */
+   uint32_t STATS_TOTAL_READ_SLICE; /* 0xa14 */
+   uint32_t STATS_TOTAL_READ_PACKET;/* 0xa18 */
+   uint32_t STATS_TOTAL_LATENCY;    /* 0xa1c */
+   uint32_t STAT_MAX_LATENCY;       /* 0xa20 */
+   uint32_t STATS_SLICE_REORDER;    /* 0xa24 */
+   uint32_t STATS_TOTAL_DDR_CMD;    /* 0xa28 */
+   uint32_t STATS_TOTAL_DDR_ACT;    /* 0xa2c */
+   uint32_t STATS_TOTAL_DDR_RDWR;   /* 0xa30 */
+   uint32_t STATS_TOTAL_DDR_WRRD;   /* 0xa34 */
+   uint32_t STATS_TOTAL_MRQ_CHN_FULL; /* 0xa38 */
+   uint32_t STATS_TOTAL_SELF_REF;   /* 0xa3c */
+   uint32_t STATS_ARB_GRANT_MATCH0; /* 0xa40 */
+   uint32_t STATS_TOTAL_QUEUE_FULL; /* 0xa44 */
+   uint32_t STATS_TOTAL_ARB_GRANT;  /* 0xa48 */
+   uint32_t STATS_TOTAL_RATE_OK_GRANT; /* 0xa4c*/
+   uint32_t STATS_FILTER_CFG_0;     /* 0xa50 */
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT  25
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_MASK   (0x1<<MEMC_STATS_FILTER_CFG_MATCH_SRC_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_SRC_EN     0x02000000
+#define MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT     16
+#define MEMC_STATS_FILTER_CFG_SRC_ID_MASK      (0x1FF<<MEMC_STATS_FILTER_CFG_SRC_ID_SHIFT)
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_SHIFT 0
+#define MEMC_STATS_FILTER_CFG_MATCH_INTF_MASK  0x0000FFFF
+#define MEMC_STATS_FILTER_CFG_INTF_AXI         0x00000001
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS0       0x00000002
+#define MEMC_STATS_FILTER_CFG_INTF_UNUSED      0x00000008
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS        MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS0       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_UBUS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_MCP         MEMC_STATS_FILTER_CFG_INTF_UNUSED
+#define MEMC_STATS_FILTER_CFG_INTF_EDIS1       MEMC_STATS_FILTER_CFG_INTF_UNUSED
+   uint32_t STATS_PROG0_SLICE;      /* 0xa54 */
+   uint32_t STATS_PROG0_PACKET;     /* 0xa58 */
+   uint32_t STATS_PROG0_READ_SLICE; /* 0xa5c */
+   uint32_t STATS_PROG0_READ_PACKET; /* 0xa60 */
+   uint32_t STATS_PROG0_LATENCY;    /* 0xa64 */
+   uint32_t STATS_PROG0_MAX_LETANCY; /* 0xa68 */
+
+   // uint32_t unused15[37];            /* 0xa6c */
+   uint32_t unused15_0;              /* 0xa6c */
+   uint32_t STATS_FILTER_CFG_1;     /* 0xa70 */
+   uint32_t STATS_PROG1_SLICE;      /* 0xa74 */
+   uint32_t STATS_PROG1_PACKET;     /* 0xa78 */
+   uint32_t STATS_PROG1_READ_SLICE; /* 0xa7c */
+   uint32_t STATS_PROG1_READ_PACKET;/* 0xa80 */
+   uint32_t STATS_PROG1_LATENCY;    /* 0xa84 */
+   uint32_t unused15_1[2];          /* 0xa88 - 0xa8c */
+   uint32_t STATS_FILTER_CFG_2;     /* 0xa90 */
+   uint32_t STATS_PROG2_SLICE;      /* 0xa94 */
+   uint32_t STATS_PROG2_PACKET;     /* 0xa98 */
+   uint32_t STATS_PROG2_READ_SLICE; /* 0xa9c */
+   uint32_t STATS_PROG2_READ_PACKET;/* 0xaa0 */
+   uint32_t STATS_PROG2_LATENCY;    /* 0xaa4 */
+   uint32_t unused15_2[2];          /* 0xaa8 - 0xaac */
+   uint32_t STATS_FILTER_CFG_3;     /* 0xab0 */
+   uint32_t STATS_PROG3_SLICE;      /* 0xab4 */
+   uint32_t STATS_PROG3_PACKET;     /* 0xab8 */
+   uint32_t STATS_PROG3_READ_SLICE; /* 0xabc */
+   uint32_t STATS_PROG3_READ_PACKET;/* 0xac0 */
+   uint32_t STATS_PROG3_LATENCY;    /* 0xac4 */
+   uint32_t unused15_3[2];            /* 0xac8 - 0xacc */
+   uint32_t STATS_AXI_BLOCK_CPU_RD; /* 0xad0 */
+   uint32_t STATS_AXI_BLOCK_CPQ_RD; /* 0xad4 */
+   uint32_t unused15_4[10];           /* 0xad8 - 0xaff */
+
+   uint32_t CAP_CAPTURE_CFG;        /* 0xb00 */
+   uint32_t CAP_TRIGGER_ADDR;       /* 0xb04 */
+   uint32_t CAP_READ_CTRL;          /* 0xb08 */
+   uint32_t unused16;               /* 0xb0c */
+   uint32_t CAP_CAPTURE_MATCH0;     /* 0xb10 */
+   uint32_t CAP_CAPTURE_MATCH1;     /* 0xb14 */
+   uint32_t CAP_CAPTURE_MATCH2;     /* 0xb18 */
+   uint32_t unused17;               /* 0xb1c */
+   uint32_t CAP_CAPTURE_MASK0;      /* 0xb20 */
+   uint32_t CAP_CAPTURE_MASK1;      /* 0xb24 */
+   uint32_t CAP_CAPTURE_MASK2;      /* 0xb28 */
+   uint32_t unused18;               /* 0xb2c */
+   uint32_t CAP_TRIGGER_MATCH0;     /* 0xb30 */
+   uint32_t CAP_TRIGGER_MATCH1;     /* 0xb34 */
+   uint32_t CAP_TRIGGER_MATCH2;     /* 0xb38 */
+   uint32_t unused19;               /* 0xb3c */
+   uint32_t CAP_TRIGGER_MASK0;      /* 0xb40 */
+   uint32_t CAP_TRIGGER_MASK1;      /* 0xb44 */
+   uint32_t CAP_TRIGGER_MASK2;      /* 0xb48 */
+   uint32_t unused20;               /* 0xb4c */
+   uint32_t CAP_READ_DATA[8];       /* 0xb50-0xb6f */
+   uint32_t unused21[164];          /* 0xb70-0xdff */
+
+   uint32_t SEC_INTR2_CPU_STATUS;   /* 0xe00 */
+   uint32_t SEC_INTR2_CPU_SET;      /* 0xe04 */
+   uint32_t SEC_INTR2_CPU_CLEAR;    /* 0xe08 */
+   uint32_t SEC_INTR2_CPU_MASK_STATUS;  /* 0xe0c */
+   uint32_t SEC_INTR2_CPU_MASK_SET;  /* 0xe10 */
+   uint32_t SEC_INTR2_CPU_MASK_CLEAR;   /* 0xe14 */
+   uint32_t unused22[58];              /* 0xe18-0xeff */
+
+   uint32_t UBUSIF0_PERMCTL;          /* 0xf00 */
+   uint32_t UBUSIF1_PERMCTL;          /* 0xf04 */
+   uint32_t SRAM_REMAP_PERMCTL;       /* 0xf08 */
+   uint32_t AXIWIF_PERMCTL;           /* 0xf0c */
+   uint32_t CHNCFG_PERMCTL;           /* 0xf10 */
+   uint32_t MCCAP_PERMCTL;            /* 0xf14 */
+   uint32_t SCRAM_PERMCTL;            /* 0xf18 */
+   uint32_t RNG_PERMCTL;              /* 0xf1c */
+   uint32_t RNGCHK_PERMCTL;           /* 0xf20 */
+   uint32_t unused23[567];            /* 0xf24-0x17ff */
+
+   SecureRangeCheckers SEC_RANGE_CHK; /* 0x1800-0x18ff */
+   uint32_t unused24[31168];            /* 0x1900-0x200000 */
+
+   uint32_t PhyControl[256];           /* 0x20000 */
+   uint32_t PhyByteLane0Control[128];  /* 0x20400 */
+   uint32_t PhyByteLane1Control[128];  /* 0x20600 */
+} MEMCControl;
+
+
+#define MEMC ((volatile MEMCControl * const) MEMC_BASE)
+
+
+#endif /* _6878_DDR_H */
+
diff --git a/arch/arm/include/asm/arch-bcm6878/misc.h b/arch/arm/include/asm/arch-bcm6878/misc.h
new file mode 100644
index 0000000000..d5d71dfe79
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6878/misc.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6878_MISC_H
+#define _6878_MISC_H
+
+/*
+ * Gpio Controller
+ */
+typedef struct GpioControl {
+        uint32_t GPIODir[8];             /* 0x00-0x1c */
+        uint32_t GPIOio[8];              /* 0x20-0x3c */
+        uint32_t PadCtrl;                 /* 0x40 */
+        uint32_t SpiSlaveCfg;             /* 0x44 */
+        uint32_t TestControl;             /* 0x48 */
+        uint32_t TestPortBlockEnMSB;      /* 0x4c */
+        uint32_t TestPortBlockEnLSB;      /* 0x50 */
+        uint32_t TestPortBlockDataMSB;    /* 0x54 */
+        uint32_t TestPortBlockDataLSB;    /* 0x58 */
+#define PINMUX_DATA_SHIFT       12
+#define PINMUX_0                0
+#define PINMUX_1                1
+#define PINMUX_2                2
+#define PINMUX_3                3
+#define PINMUX_4                4
+#define PINMUX_5                5
+#define PINMUX_6                6
+#define PINMUX_7                7
+#define PAD_CTRL_SHIFT          12
+#define PAD_CTRL_MASK           (0x3f<<PAD_CTRL_SHIFT)
+#define PAD_SEL_SHIFT           12
+#define PAD_AMP_SHIFT           15
+#define PAD_IND_SHIFT           16
+#define PAD_GMII_SHIFT          17
+       uint32_t TestPortCmd;             /* 0x5c */
+#define LOAD_MUX_REG_CMD        0x21
+#define LOAD_PAD_CTRL_CMD       0x22
+        uint32_t DiagReadBack;            /* 0x60 */
+        uint32_t DiagReadBackHi;          /* 0x64 */
+        uint32_t GeneralPurpose;          /* 0x68 */
+        uint32_t spare[3];
+} GpioControl;
+
+#define GPIO_BASE          0xff800500
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+/*
+ ** Misc Register Set Definitions.
+ */
+typedef struct Misc {
+    uint32_t  miscStrapBus;                       /* 0x00 */
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           5
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOTROM_BOOT_N           (0x1 << 11)
+
+#define MISC_STRAP_BUS_PCIE_RC_MODE_SHIFT       0
+#define MISC_STRAP_BUS_PCIE_RC_MODE MASK        (1 << MISC_STRAP_BUS_PCIE_SINGLE_LANES_SHIFT) /* 1-root complex  0-end point */
+#define MISC_STRAP_GPON_TX_EN_SHIFT             1         
+#define MISC_STRAP_GPON_TX_EN_MASK              (1 << MISC_STRAP_GPON_TX_EN_SHIFT)  // 1-Single ended, 0-differential
+#define MISC_STRAP_USB_PMU_POLARITY_SHIFT       30
+#define MISC_STRAP_USB_PMU_POLARITY_MASK        (1 << MISC_STRAP_USB_PMU_POLARITY_SHIFT)  // 1-active low, 0-active high
+
+    uint32_t  miscStrapOverride;                  /* 0x04 */
+    uint32_t  miscMaskUBUSErr;                    /* 0x08 */
+    uint32_t  miscPeriphCtrl;                     /* 0x0c */
+    uint32_t  miscSPImasterCtrl;                  /* 0x10 */
+    uint32_t  miscDierevid;                       /* 0x14 */
+    uint32_t  miscPeriphMiscCtrl;                 /* 0x18 */
+    uint32_t  miscPeriphMiscStat;                 /* 0x1c */
+    uint32_t  miscSoftResetB;                     /* 0x20 */
+    uint32_t  reserved0;                          /* 0x24 */
+    uint32_t  miscSWdebugNW[2];                   /* 0x3c */
+    uint32_t  miscWDresetCtrl;                    /* 0x30 */
+} Misc;
+
+#define MISC_BASE          0xff802600
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+// PERF
+typedef struct PerfControl { /* GenInt */
+     uint32_t        RevID;             /* (00) word 0 */
+#define CHIP_ID_SHIFT   12
+#define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
+#define REV_ID_MASK     0xff
+} PerfControl;
+
+#define PERF_BASE              0xff800000
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6878/otp.h b/arch/arm/include/asm/arch-bcm6878/otp.h
new file mode 100644
index 0000000000..cbc4eae953
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6878/otp.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _6878_OTP_H
+#define _6878_OTP_H
+
+#define JTAG_OTP_BASE   0xff802800
+
+/* row 8 */
+#define OTP_CPU_CORE_CFG_ROW            	8
+#define OTP_CPU_CORE_CFG_SHIFT          	28
+#define OTP_CPU_CORE_CFG_MASK           	0x3
+
+/* row 9 */
+#define OTP_CPU_CLOCK_FREQ_ROW          	9
+#define OTP_CPU_CLOCK_FREQ_SHIFT        	0
+#define OTP_CPU_CLOCK_FREQ_MASK         	0x7
+
+/* row 17 */
+#define OTP_BRCM_BTRM_BOOT_ENABLE_ROW           17
+#define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT         3
+#define OTP_BRCM_BTRM_BOOT_ENABLE_MASK          1
+
+/* row 18 */
+#define OTP_CUST_BTRM_BOOT_ENABLE_ROW           18
+#define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT         15
+#define OTP_CUST_BTRM_BOOT_ENABLE_MASK          7
+
+/* row 23 */
+#define OTP_CUST_MFG_MRKTID_ROW                 23
+#define OTP_CUST_MFG_MRKTID_SHIFT               0
+#define OTP_CUST_MFG_MRKTID_MASK                0xffff
+
+/* row 17 */
+#define OTP_BRCM_ENFORCE_BINIT_ROW 		17
+#define OTP_BRCM_ENFORCE_BINIT_SHIFT		13
+#define OTP_BRCM_ENFORCE_BINIT_MASK		1
+
+/* A row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure boot handling frequency, chipid and so on 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_OTP_MAP_ROW_INITLR(__VV__)												\
+	static otp_hw_cmn_row_t __VV__[ ] = {										\
+	{OTP_MAP_BRCM_BTRM_BOOT_ENABLE, OTP_BRCM_BTRM_BOOT_ENABLE_ROW, OTP_BRCM_BTRM_BOOT_ENABLE_MASK, OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT, 1, {.addr_type = OTP_HW_CMN_ROW_ADDR_ROW} },	\
+	{OTP_MAP_CUST_BTRM_BOOT_ENABLE, OTP_CUST_BTRM_BOOT_ENABLE_ROW, OTP_CUST_BTRM_BOOT_ENABLE_MASK, OTP_CUST_BTRM_BOOT_ENABLE_SHIFT,1, {.addr_type = OTP_HW_CMN_ROW_ADDR_ROW}},	\
+	{OTP_MAP_CUST_MFG_MRKTID, OTP_CUST_MFG_MRKTID_ROW, OTP_CUST_MFG_MRKTID_MASK, OTP_CUST_MFG_MRKTID_SHIFT,1, {.addr_type = OTP_HW_CMN_ROW_ADDR_ROW} },				\
+	{OTP_MAP_CPU_CORE_CFG, OTP_CPU_CORE_CFG_ROW, OTP_CPU_CORE_CFG_MASK, OTP_CPU_CORE_CFG_SHIFT, 1},				\
+	{OTP_MAP_CPU_CLOCK_FREQ, OTP_CPU_CLOCK_FREQ_ROW, OTP_CPU_CLOCK_FREQ_MASK,OTP_CPU_CLOCK_FREQ_SHIFT, 1, {.addr_type = OTP_HW_CMN_ROW_ADDR_ROW} }		\
+	}
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6878/pmc.h b/arch/arm/include/asm/arch-bcm6878/pmc.h
new file mode 100644
index 0000000000..924fcbe4a0
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6878/pmc.h
@@ -0,0 +1,169 @@
+#ifndef PMC_H
+#define PMC_H 
+
+/*
+ * Power Management Control
+ */
+typedef union
+{
+    struct
+    {
+        uint32_t propagate_to_err  :  1; // [00:00] -+
+        uint32_t propagate_slv_err :  1; // [01:01]  | - these are potentially dangerous and MAY cause a system crash
+        uint32_t pmbus_reset_n     :  1; // [02:02] -+
+        uint32_t reserved0         :  1; // [03:03]
+        uint32_t maxPmbIdx         :  3; // [06:04] 0-based (0-7)
+        uint32_t reserved1         :  1; // [07:07]
+        uint32_t maxClientId       : 12; // [19:08] 0-based (theoreticaly 0-4095, but code limits this to 256 devices - 0-255)
+        uint32_t numRegsPerClient  : 10; // [29:20] some power of 2 - number of 32-bit registers in each client (max = 512)
+        uint32_t startDiscovery    :  1; // [30:30] kicks off H/W discovery of clients and fills in the map (see PMB_REGS below)
+        uint32_t discoveryBusy     :  1; // [31:31] whether or not H/W discovery is still busy creating the map
+    } Bits;
+    uint32_t Reg32;
+} PMB_CONFIG_REG;
+
+typedef union
+{
+    struct {
+        uint32_t data      : 16; // [15:00]
+        uint32_t reserved1 : 16; // [31:16]
+    } Bits;
+    uint32_t Reg32;
+} SSBM_data_reg;
+
+typedef union
+{
+    struct {
+        uint32_t  ssb_addr    : 10; // [09:00]
+        uint32_t  ssb_cmd     :  2; // [11:10]
+        uint32_t  ssb_en      :  1; // [12:12]
+        uint32_t  ssb_add_pre :  1; // [13:13]
+        uint32_t  reserved2   :  1; // [14:14]
+        uint32_t  ssb_start   :  1; // [15:15]
+        uint32_t  reserved1   : 16; // [31:16]
+    } Bits;
+    uint32_t Reg32;
+} SSBM_control_reg;
+
+typedef union
+{
+    struct {
+        uint32_t busy      :  1; // [00:00]
+        uint32_t reserved1 : 31; // [31:01]
+    } Bits;
+    uint32_t Reg32;
+} SSBM_status_reg;
+
+typedef union
+{
+    struct {
+        uint32_t swreg_th_lo : 8; // [07:00]
+        uint32_t swreg_th_hi : 8; // [15:08]
+        uint32_t reserved    :16; // [31:16]
+    } Bits;
+    uint32_t Reg32;
+} SSBM_SWREG_th_hilo_reg;
+
+typedef union
+{
+    struct {
+        uint32_t ssb_lock_addr : 10; // [09:00]
+        uint32_t lock_bit      :  1; // [10:10]
+        uint32_t lock_mode     :  1; // [11:11]
+        uint32_t reserved      : 20; // [31:12]
+    } Bits;
+    uint32_t Reg32;
+} SSBM_SWREG_lock_reg;
+
+#define kSSBWrite   0x01
+#define kSSBRead    0x02
+#define kSSBEn      (1 << 12)
+#define kSSBStart   (1 << 15)
+
+typedef struct PMSSBMasterControl {
+    uint32_t control;     /* 0x0060 */
+    uint32_t wr_data;      /* 0x0064 */
+    uint32_t rd_data;      /* 0x0068 */
+    uint32_t status;      /* 0x006c */
+    SSBM_SWREG_th_hilo_reg  ssbmThHiLo;     /* 0x0070 */
+    SSBM_SWREG_lock_reg     ssbmSwLock;     /* 0x0074 */
+} PMSSBMasterControl;
+
+#define SWR_FIRST 0
+#define SWR_LAST 4
+#define SWR_READ_CMD_P 0xB800
+#define SWR_WR_CMD_P   0xB400
+#define SWR_EN         0x1000
+#define SET_ADDR(ps, reg)  (((ps) << 5 | ((reg) & 0x1f)) & 0x2ff)
+
+#define SR_TEST(x)  {\
+                     int num;\
+                     for(num=1000;(((PROCMON->SSBMaster.control) & 0x8000) && (num > 0)) ; num--) ;\
+                         if(!num) \
+                         {\
+                             printf("Error num %d timeout num = %d!!!", (x),  num);\
+                         }\
+}
+
+typedef struct PmmReg {
+    uint32_t memPowerCtrl;            /* 0x0000 */
+    uint32_t regSecurityConfig;       /* 0x0004 */
+} PmmReg;
+
+typedef struct keyholeReg {
+    uint32_t ctrlSts;
+    uint32_t wrData;
+    uint32_t mutex;
+    uint32_t rdData;
+} keyholeReg;
+
+typedef struct PmbBus {
+    PMB_CONFIG_REG config;          /* 0x0100 */
+    uint32_t arbiter;         /* 0x0104 */
+    uint32_t timeout;         /* 0x0108 */
+    uint32_t unused1;         /* 0x010c */
+    keyholeReg keyhole[4];  /* 0x0110-0x014f */
+    uint32_t unused2[44];     /* 0x0150-0x01ff */
+    uint32_t map[64];         /* 0x0200-0x02ff */ 
+}PmbBus;
+
+typedef struct Procmon {
+    PmmReg  pmm;                        /* 0x20000 */
+    uint32_t unused11[22];                /* 0x20008-0x2005f */
+    PMSSBMasterControl SSBMaster;            /* 0x20060-0x20077 */
+    uint32_t unused12[34];                /* 0x20078-0x200ff */
+    PmbBus pmb;                         /* 0x20100 */
+} Procmon;
+#define PROC_MON_BASE        0xffb20000
+#define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
+
+typedef struct
+{
+    uint32_t  control;
+#define PMC_PMBM_START                  (1 << 31)
+#define PMC_PMBM_TIMEOUT                (1 << 30)
+#define PMC_PMBM_SLAVE_ERR              (1 << 29)
+#define PMC_PMBM_BUSY                   (1 << 28)
+#define PMC_PMBM_BUS_SHIFT              (20)
+#define PMC_PMBM_Read                   (0 << 24)
+#define PMC_PMBM_Write                  (1 << 24)
+    uint32_t  wr_data;
+    uint32_t  mutex;
+    uint32_t  rd_data;
+} PMB_keyhole_reg;
+
+typedef struct PMBMaster {
+    uint32_t config;
+#define PMB_NUM_REGS_SHIFT (20)
+#define PMB_NUM_REGS_MASK  (0x3ff)
+    uint32_t arbitger;
+    uint32_t timeout;
+    uint32_t reserved;
+    PMB_keyhole_reg keyhole[4];
+    uint32_t reserved1[44];
+    uint32_t map[64];
+} PMBMaster;
+#define PMB_BASE        0xffb20100
+#define PMB ((volatile PMBMaster * const) PMB_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm6878/pmc_addr.h b/arch/arm/include/asm/arch-bcm6878/pmc_addr.h
new file mode 100644
index 0000000000..5763406df0
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6878/pmc_addr.h
@@ -0,0 +1,62 @@
+#define PMB_BUS_MAX              2
+#define PMB_BUS_ID_SHIFT         12
+
+#define PMB_BUS_PERIPH           0
+#define PMB_ADDR_PERIPH          (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PERIPH         3
+
+#define PMB_BUS_CHIP_CLKRST      1
+#define PMB_ADDR_CHIP_CLKRST     (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_CHIP_CLKRST    0
+
+#define PMB_BUS_SYSPLL          1
+#define PMB_ADDR_SYSPLL         (3 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_SYSPLL        0
+
+#define PMB_BUS_PVTMON           1
+#define PMB_ADDR_PVTMON          (6 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PVTMON         0
+
+#define PMB_BUS_MEMC             1
+#define PMB_ADDR_MEMC            (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_MEMC           1
+
+#define PMB_BUS_USB20_2X         1
+#define PMB_ADDR_USB20_2X        (10 | PMB_BUS_USB20_2X << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_USB20_2X       4
+
+#define PMB_BUS_WAN              1
+#define PMB_ADDR_WAN             (11 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WAN            3
+
+#define PMB_BUS_XRDP              1
+#define PMB_ADDR_XRDP             (12 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_XRDP            3
+
+#define PMB_BUS_PCIE0             1
+#define PMB_ADDR_PCIE0            (18 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_PCIE0           1
+
+#define PMB_BUS_WLAN0             0
+#define PMB_ADDR_WLAN0            (19 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_WLAN0           1
+
+#define PMB_BUS_ORION_CPU0       1
+#define PMB_ADDR_ORION_CPU0      (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU0     1
+
+#define PMB_BUS_ORION_CPU1       1
+#define PMB_ADDR_ORION_CPU1      (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_CPU1     1
+
+#define PMB_BUS_ORION_NONCPU     1
+#define PMB_ADDR_ORION_NONCPU    (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_ORION_NONCPU   1
+
+#define PMB_BUS_BIU_PLL          1
+#define PMB_ADDR_BIU_PLL         (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_PLL        0
+
+#define PMB_BUS_BIU_BPCM         1
+#define PMB_ADDR_BIU_BPCM        (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
+#define PMB_ZONES_BIU_BPCM       1
diff --git a/arch/arm/include/asm/arch-bcm6878/pmc_drv_cfg.h b/arch/arm/include/asm/arch-bcm6878/pmc_drv_cfg.h
new file mode 100644
index 0000000000..83aa0127c1
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6878/pmc_drv_cfg.h
@@ -0,0 +1,34 @@
+/*
+<:copyright-BRCM:2019:DUAL/GPL:standard 
+
+   Copyright (c) 2019 Broadcom 
+   All Rights Reserved
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License, version 2, as published by
+the Free Software Foundation (the "GPL").
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+
+A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.
+
+:> 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains special header for different flavors of PMC drivers.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_CFG_H
+#define PMC_DRV_CFG_H
+
+#define PMC_ON_HOSTCPU      1
+
+#endif // #ifndef PMC_DRV_CFG_H
diff --git a/arch/arm/include/asm/arch-bcm6878/rng.h b/arch/arm/include/asm/arch-bcm6878/rng.h
new file mode 100644
index 0000000000..83367fec05
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm6878/rng.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _6878_RNG_H
+#define _6878_RNG_H
+
+#define RNG_BASE	0xff800b80
+
+typedef struct Rng {
+	uint32_t ctrl0;			/* 0x00 */
+	uint32_t rngSoftReset;		/* 0x04 */
+	uint32_t rbgSoftReset;		/* 0x08 */
+	uint32_t totalBitCnt;		/* 0x0c */
+	uint32_t totalBitCntThreshold;	/* 0x10 */
+	uint32_t revId;			/* 0x14 */
+	uint32_t intStatus;		/* 0x18 */
+#define RNG_INT_STATUS_NIST_FAIL	(0x1<<5)
+#define RNG_INT_STATUS_FIFO_FULL	(0x1<<2)
+	uint32_t intEn;			/* 0x1c */
+	uint32_t rngFifoData;		/* 0x20 */
+	uint32_t fifoCnt;		/* 0x24 */
+#define RNG_PERM_ALLOW_SECURE_ACCESS	0xCC
+#define RNG_PERM_ALLOW_NONSEC_ACCESS	0x33
+	uint32_t perm;			/* 0x28 */
+} Rng;
+
+#define RNG_PERM_SHIFT 		0x0
+#define RNG_PERM_BLK_SHIFT	0x4
+
+#define RNG_PERM_SEC_W 		0x8
+#define RNG_PERM_SEC_R 		0x4
+#define RNG_PERM_NSEC_W 	0x2
+#define RNG_PERM_NSEC_R 	0x1
+
+#define RNG_PERM_BLK_SEC_W 	0x8
+#define RNG_PERM_BLK_SEC_R 	0x4
+#define RNG_PERM_BLK_NSEC_W 	0x2
+#define RNG_PERM_BLK_NSEC_R 	0x1
+
+#define RNG_PERM_NSEC_ENABLE   (((RNG_PERM_BLK_NSEC_R|RNG_PERM_BLK_NSEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_SEC_ENABLE   (((RNG_PERM_BLK_SEC_R|RNG_PERM_BLK_SEC_W)<<RNG_PERM_BLK_SHIFT)|  (RNG_PERM_SEC_W|RNG_PERM_SEC_R)<<RNG_PERM_SHIFT)
+#define RNG_PERM_DISABLE_ALL	0x0   
+
+#define RNG ((volatile Rng * const) RNG_BASE)
+
+#endif
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 950ec1e793..883991ba72 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -33,6 +33,11 @@ int check_cache_range(unsigned long start, unsigned long stop);
 void l2_cache_enable(void);
 void l2_cache_disable(void);
 void set_section_dcache(int section, enum dcache_option option);
+#ifdef CONFIG_ARMV7_LPAE
+void set_section_attr(int section, u64 virt, u64 attr);
+#else
+void set_section_attr(int section, u32 virt, u32 attr);
+#endif
 
 void arm_init_before_mmu(void);
 void arm_init_domains(void);
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 370031f2ac..8beff505a3 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,6 +1,7 @@
 #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
 	!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \
-	!defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP)
+	!defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \
+	!defined(CONFIG_ARCH_BCMBCA)
 #include <asm/arch/gpio.h>
 #endif
 #include <asm-generic/gpio.h>
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index aed2e3c51e..841e4515f5 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -345,6 +345,14 @@ void switch_to_hypervisor_ret(void);
 #define wfi()
 #endif
 
+static inline unsigned long read_mpidr(void)
+{
+	unsigned long val;
+
+	asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+	return val;
+}
+
 static inline unsigned long get_cpsr(void)
 {
 	unsigned long cpsr;
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index b2913e8165..d14fd7e84e 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -23,6 +23,26 @@ __weak void arm_init_domains(void)
 {
 }
 
+#ifdef CONFIG_ARMV7_LPAE
+void set_section_attr(int section, u64 virt, u64 attr)
+#else
+void set_section_attr(int section, u32 virt, u32 attr)
+#endif
+{
+#ifdef CONFIG_ARMV7_LPAE
+	u64 *page_table = (u64 *)gd->arch.tlb_addr;
+	u64 value = virt;
+#else
+	u32 *page_table = (u32 *)gd->arch.tlb_addr;
+	u32 value = virt;
+#endif
+	/* Add page attribute bits */
+	value |= attr;
+
+	/* Set PTE */
+	page_table[section] = value;
+}
+
 void set_section_dcache(int section, enum dcache_option option)
 {
 #ifdef CONFIG_ARMV7_LPAE
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 449544d11c..463d283cb7 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -77,6 +77,7 @@ void noncached_init(void)
 	phys_addr_t start, end;
 	size_t size;
 
+	/* If this calculation changes, update board_f.c:reserve_noncached() */
 	end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
 	size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
 	start = end - size;
diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig
new file mode 100644
index 0000000000..1d6a842331
--- /dev/null
+++ b/arch/arm/mach-bcmbca/Kconfig
@@ -0,0 +1,368 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if ARCH_BCMBCA
+
+config BCM63158
+	bool "Broadcom BCM63158 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select ARM64
+
+config BCM4908
+	bool "Broadcom BCM4908 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select ARM64
+
+config BCM4912
+	bool "Broadcom BCM4912 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select ARM64
+
+config BCM6858
+	bool "Broadcom BCM6858 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select ARM64
+
+config BCM6856
+	bool "Broadcom BCM6856 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select ARM64
+
+config BCM63178
+	bool "Broadcom BCM63178 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select SYS_ARCH_TIMER
+	select CPU_V7A
+
+config BCM47622
+	bool "Broadcom BCM47622 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select SYS_ARCH_TIMER
+	select CPU_V7A
+
+config BCM6756
+	bool "Broadcom BCM6756 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select SYS_ARCH_TIMER
+	select CPU_V7A
+
+config BCM63138
+	bool "Broadcom BCM63138 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select CPU_V7A
+	select ENABLE_ARM_SOC_BOOT0_HOOK if SPL
+	select TIMER
+	select BCM6XXX_TIMER
+	imply SPL_TIMER
+	imply TPL_TIMER
+
+config BCM63148
+	bool "Broadcom BCM63148 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select CPU_V7A
+	select ENABLE_ARM_SOC_BOOT0_HOOK if SPL
+	select TIMER
+	select BCM6XXX_TIMER
+	select ARM_CORTEX_A15_CVE_2017_5715
+	imply SPL_TIMER
+	imply TPL_TIMER
+
+config BCM63146
+	bool "Broadcom BCM63146 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select ARM64
+
+config BCM6846
+	bool "Broadcom BCM6846 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select SYS_ARCH_TIMER
+	select CPU_V7A
+
+config BCM6878
+	bool "Broadcom BCM6878 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select SYS_ARCH_TIMER
+	select CPU_V7A
+
+config BCM6855
+	bool "Broadcom BCM6855 family"
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select SYS_ARCH_TIMER
+	select CPU_V7A
+
+config BCMBCA_OTP
+	bool "Broadcom BCA OTP controller"
+	default y
+
+config OTP_V1
+	bool "OTP Version 1 controller (40nm SoC)"
+	depends on BCMBCA_OTP 
+	default y if BCM63138
+	default y if BCM63148
+	default y if BCM6858
+	default y if BCM4908
+	default n
+
+config OTP_V2
+	bool "OTP Version 2 controller(28nm SoC)"
+	depends on BCMBCA_OTP 
+	default y if BCM63158
+	default y if BCM63178
+	default y if BCM47622
+	default y if BCM6756
+	default y if BCM6846
+	default y if BCM6878
+	default y if BCM6855
+	default y if BCM6856
+	default n
+
+config OTP_V3
+	bool "OTP Version 2 controller(16nm SoC)"
+	depends on BCMBCA_OTP 
+	default y if BCM4912
+	default y if BCM63146
+	default n
+
+config OTP_LOCK 
+	bool "OTP HW CPU locking"
+	depends on BCMBCA_OTP 
+	default y if BCM63178
+	default y if BCM4912
+	default y if BCM47622
+	default y if BCM6756
+	default y if BCM63146
+	default y if BCM6878
+	default y if BCM6855
+	default n
+
+config OTP_SOTP 
+	bool "Secure OTP support"
+	depends on BCMBCA_OTP 
+	default y if BCM63158
+	default y if BCM63178
+	default y if BCM47622
+	default y if BCM6756	
+	default y if BCM6846
+	default y if BCM6856
+	default y if BCM6858
+	default y if BCM4908
+	default n
+
+config OTP_SKP 
+	bool "Secure OTP via Secure Key Portal (SKP) support"
+	depends on BCMBCA_OTP 
+	default y if BCM4912
+	default y if BCM63146
+	default n
+
+config OTP_SKO 
+	bool "Secure OTP via Secure Key Object (SKO) support"
+	depends on BCMBCA_OTP 
+	default y if BCM6878
+	default y if BCM6855
+	default n
+
+config BCMBCA_RDP
+	bool "Broadcom BCA RDP Support"
+	default n
+
+config BCMBCA_UBUS
+	bool "Broadcom BCA UBUS Support"
+	default y if BCM6858
+	default y if BCM47622
+	default y if BCM6756	
+	default y if BCM63178
+	default n
+
+config BCMBCA_PMC
+	bool "Broadcom BCA PMC Support"
+	default y if BCM63138
+	default y if BCM63148
+	default y if BCM63158
+	default y if BCM63178
+	default y if BCM4908
+	default y if BCM4912
+	default y if BCM47622
+	default y if BCM6756	
+	default y if BCM63146
+	default y if BCM6846
+	default y if BCM6856
+	default y if BCM6858
+	default y if BCM6878
+	default y if BCM6855
+	default n
+
+config BCMBCA_PMC_SWITCH
+	bool "Broadcom BCA PMC SWITCH Support"
+	default y if BCM63138 || BCM63148 || BCM63158 || BCM4908 || BCM63178 || BCM6756
+	default n
+
+config BCMBCA_PMC_RDP
+	bool "Broadcom BCA PMC RDP Support"
+	default y if BCM63138
+	default y if BCM63148
+	default n
+
+config BCMBCA_PMC_XRDP
+	bool "Broadcom BCA PMC XRDP Support"
+	default y if BCM63146
+	default y if BCM6846
+	default y if BCM6856
+	default y if BCM6858
+	default y if BCM6878
+	default n
+
+config BCMBCA_PMC_LPORT
+	bool "Broadcom BCA PMC LPORT Support"
+	default y if BCM6858
+	default n
+
+config BCMBCA_PMC_SYSPORT
+	bool "Broadcom BCA PMC SystemPort Support"
+	default y if BCM47622
+	default n
+
+config BCMBCA_DDRC
+	bool "Broadcom BCA DDR Support"
+	depends on SPL
+	default n
+
+config BCMBCA_DPFE
+	bool "Broadcom BCA DPFE Engine based DDR init"
+	depends on SPL
+	default n
+
+config BCMBCA_DDR_REGINIT
+	bool "Broadcom BCA registers based DDR init"
+	depends on SPL
+	default n
+
+config BRCM_SPL_MEMC_SRAM
+	bool "Set SPL pagetables in MEMC SRAM"
+	depends on SPL
+	default y if BCM6858
+	default y if BCM4908
+	default y if BCM6856
+	default y if BCM6846
+	default y if BCM63178
+	default y if BCM47622
+	default y if BCM6756	
+	default n
+
+config BCMBCA_RNG
+    bool "Broadcom BCA RNG driver"
+    default y if BCM63138
+    default y if BCM63148
+    default y if BCM63158
+    default y if BCM63178
+    default y if BCM4908
+    default y if BCM4912
+    default y if BCM47622
+    default y if BCM6756
+    default y if BCM63146
+    default y if BCM6846
+    default y if BCM6856
+    default y if BCM6858
+    default y if BCM6878
+    default y if BCM6855
+    default n
+
+if BCMBCA_DDRC
+
+config BCMBCA_DDR_LOADADDR
+	hex "DDR binary load address"
+
+config BCMBCA_DDR4
+	bool "DDR4 Chip Support"
+	default n
+
+config BCMBCA_DDRC_SCRAMBLER
+	bool "DDR Scrambler support"
+	select SPL_HASH_SUPPORT
+	default y if BCM63158
+	default y if BCM63146
+	default y if BCM4912
+	default y if BCM6858
+	default y if BCM4908
+	default n
+
+config BCMBCA_DDRC_EARLY_VREF_DQ
+	bool "Early VREF_DQ support"
+	default y if BCM63158
+	default y if BCM4908
+	default y if BCM63178
+	default y if BCM47622
+	default y if BCM6756
+	default y if BCM6858
+	default y if BCM6856
+	default n
+	help
+	  Enable or disable early VREF_DQ voltage turn on
+
+config BCMBCA_DDRC_DBGPRINT
+	bool "DDR Debug Print"
+	default y if BCM6858
+	default y if BCM6846
+	default y if BCM6878
+	default y if BCM6856
+	default y if BCM47622
+	default y if BCM6756	
+	default y if BCM63146
+	default y if BCM4912	
+	default y if BCM6855
+	default n
+
+config BCMBCA_DDR_MCBSEL_OVERRIDE
+	bool "MCB selector override"
+	default n
+	help
+	  Enable or disable mcb seletor override from environment variable
+
+config BCMBCA_DDR_MCBSEL_OVERRIDE_VALUE
+	hex "MCB selector override value"
+	depends on BCMBCA_DDR_MCBSEL_OVERRIDE
+	default 0x0
+	help
+	  mcb seletor override value
+
+config BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE
+	hex "Max size of DDR binary for JTAG"
+
+endif
+
+if BCMBCA_DPFE
+source "arch/arm/mach-bcmbca/bcmbca_dpfe/Kconfig"
+endif
+source "arch/arm/mach-bcmbca/bcm63158/Kconfig"
+source "arch/arm/mach-bcmbca/bcm4908/Kconfig"
+source "arch/arm/mach-bcmbca/bcm4912/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6858/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6856/Kconfig"
+source "arch/arm/mach-bcmbca/bcm63178/Kconfig"
+source "arch/arm/mach-bcmbca/bcm47622/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6756/Kconfig"
+source "arch/arm/mach-bcmbca/bcm63138/Kconfig"
+source "arch/arm/mach-bcmbca/bcm63148/Kconfig"
+source "arch/arm/mach-bcmbca/bcm63146/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6846/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6878/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6855/Kconfig"
+
+endif
+
diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile
new file mode 100644
index 0000000000..64591648b3
--- /dev/null
+++ b/arch/arm/mach-bcmbca/Makefile
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+obj-y += mmu_setup.o pinmux.o lowlevel_init.o
+obj-$(CONFIG_OF_SYSTEM_SETUP) += bcmbca-dtsetup.o dt_helper.o
+
+obj-$(CONFIG_BCM63158) += bcm63158/
+obj-$(CONFIG_BCM63146) += bcm63146/
+obj-$(CONFIG_BCM6858) += bcm6858/
+obj-$(CONFIG_BCM6856) += bcm6856/
+obj-$(CONFIG_BCM63178) += bcm63178/
+obj-$(CONFIG_BCM47622) += bcm47622/
+obj-$(CONFIG_BCM6756) += bcm6756/
+obj-$(CONFIG_BCM4908) += bcm4908/
+obj-$(CONFIG_BCM4912) += bcm4912/
+obj-$(CONFIG_BCM63138) += bcm63138/
+obj-$(CONFIG_BCM63148) += bcm63148/
+obj-$(CONFIG_BCM6846) += bcm6846/
+obj-$(CONFIG_BCM6878) += bcm6878/
+obj-$(CONFIG_BCM6855) += bcm6855/
+
+obj-$(CONFIG_BCMBCA_PMC) += pmc/
+obj-$(CONFIG_BCMBCA_UBUS) += ubus/
+obj-$(CONFIG_BCMBCA_OTP) += otp/
+obj-$(CONFIG_BCMBCA_RNG) += rng/
+
+ifndef CONFIG_SPL_BUILD
+# u-boot proper
+obj-$(CONFIG_BCMBCA_RDP) += rdp/
+obj-$(CONFIG_BCMBCA_XRDP_146) += xrdp/
+
+else # SPL_BUILD
+
+# TPL and SPL
+obj-$(CONFIG_SPL_BUILD) += bcm_fdtdec.o
+obj-$(CONFIG_NAND) += bcmbca_nand_spl.o
+obj-$(CONFIG_BCMBCA_BOARD_TK_PROG) += otp_tk/
+
+ifndef CONFIG_TPL_BUILD
+# SPL ONLY
+ifdef CONFIG_BCMBCA_DDRC
+obj-$(CONFIG_SPL_BUILD)	+= spl_ddrinit.o
+ifdef CONFIG_BCMBCA_DDR_REGINIT
+obj-$(CONFIG_SPL_BUILD) += ddrinit_reg.o
+else # BCMBCA_DDR_REGINIT
+ifdef CONFIG_BCMBCA_DPFE
+obj-$(CONFIG_SPL_BUILD)	+= ddrinit_dpfe.o
+subdir-$(CONFIG_SPL_BUILD) += bcmbca_dpfe
+else # BCMBCA_DPFE
+subdir-$(CONFIG_SPL_BUILD) += bcmbca_ddr
+endif # BCMBCA_DPFE
+endif # BCMBCA_DDR_REGINIT
+endif # BCMBCA_DDRC
+
+endif # TPL_BUILD
+
+endif # SPL_BUILD
diff --git a/arch/arm/mach-bcmbca/bcm47622/Kconfig b/arch/arm/mach-bcmbca/bcm47622/Kconfig
new file mode 100644
index 0000000000..2b29d73ea2
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm47622/Kconfig
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM47622
+
+config TARGET_BCM947622
+	bool "Broadcom 47622 Reference Board"
+	depends on ARCH_BCMBCA
+
+config SYS_SOC
+	default "bcm47622"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+	hex "default DDR3 mcb selector value"
+	default 0x00001607
+
+config BCMBCA_DDR4_DEF_MCBSEL
+	hex "default DDR4 mcb selector value"
+	default 0x101607
+endif
+
+config TPL_MAX_SIZE
+	default 1048576
+
+config RSVD_USE_MAX_FROM_ENV_AND_DT 
+	bool "RSVD will use max value from env and DT"
+	default y
+
+config BCMBCA_LDO_TRIM
+	bool "Support LDO Trim"
+	default y
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm47622/Makefile b/arch/arm/mach-bcmbca/bcm47622/Makefile
new file mode 100644
index 0000000000..29dad125c5
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm47622/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+obj-y += cpu.o
+obj-y += mmu_table.o
\ No newline at end of file
diff --git a/arch/arm/mach-bcmbca/bcm47622/cpu.c b/arch/arm/mach-bcmbca/bcm47622/cpu.c
new file mode 100644
index 0000000000..95426bff02
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm47622/cpu.c
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/ubus4.h>
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+static void enable_ns_access(void)
+{
+	BIUCFG->bac.bac_permission |= 0x33;     // Linux access to BAC_CPU_THERM_TEMP
+}
+
+/*this function is used to turn on CCI from secure mode 
+*  *   it also turns snooping enable for S5 CPU interface*/
+static void cci500_enable(void)
+{
+	/*Enable access from E2 and below */
+	CCI500->secr_acc |= SECURE_ACCESS_UNSECURE_ENABLE;
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+	printf("Chip ID: BCM%X_%X\n",chipId,revId);
+}
+#endif
+
+#if defined(CONFIG_BCMBCA_PMC)
+
+void boost_cpu_clock(void)
+{
+	printf("set cpu freq to 1500MHz\n");
+	set_cpu_freq(1500);
+	pll_ch_freq_set(PMB_ADDR_BIU_PLL, 1, 3000/600); // raise ACEBIU clock rate to 600 MHz
+}
+
+int set_cpu_freq(int freqMHz)
+{
+	int mdiv;
+
+	if( freqMHz > 1500 || freqMHz < 300 )
+	{
+		printf("%dMHz is not supported\n", freqMHz);
+		return -1;
+	}
+
+	/* VCO at 3GHz, mdiv = Fvco/target frequency */
+	mdiv = 3000/freqMHz;
+
+	pll_ch_freq_set(PMB_ADDR_BIU_PLL, 0, mdiv);
+
+	return 3000/mdiv;	
+}
+#endif
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_EMMC)
+		return BOOT_DEVICE_MMC1;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+
+	u32 frq = COUNTER_FREQUENCY;
+
+	spl_ddrinit_prepare();
+
+	/* set arch timer frequency */
+	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
+	/* enable system timer */
+	BIUCFG->TSO_CNTCR |= 1;
+
+	/* force axi write reply to workaround wifi memory write ordering issue */
+	ubus_master_cpu_enable_axi_write_cache(0);
+	/* enable unalgined access */
+	set_cr(get_cr() & ~CR_A);	
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+	enable_ns_access();
+	cci500_enable();
+#endif
+
+
+    return 0;
+}
+
+void arch_cpu_deinit()
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	/* restore axi write cache when we spl does not need to use wifi memory */
+	ubus_master_cpu_enable_axi_write_cache(1);
+#endif
+}
+
+int get_nr_cpus()
+{
+	uint32_t nr_cpus;
+
+	if (bcm_otp_get_nr_cpus(&nr_cpus)) {
+		printf("Error: failed to read cpu core from OTP\n");
+		nr_cpus = 4;
+	} else {
+		if (nr_cpus >= 0 && nr_cpus <= 4)
+			nr_cpus = 4;
+		else
+			nr_cpus = 8 - nr_cpus;
+	}
+
+	return nr_cpus;
+}
diff --git a/arch/arm/mach-bcmbca/bcm47622/mmu_table.c b/arch/arm/mach-bcmbca/bcm47622/mmu_table.c
new file mode 100644
index 0000000000..5193cbde42
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm47622/mmu_table.c
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include "mmu_map_v7.h"
+
+static struct mm_region broadcom_bcm947622_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) 
+#if !defined(CONFIG_TPL_BUILD)
+	/* SPL table */
+	/* DDR memory. Enable the maximum 2GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000,
+		.phys = 0x00000000,
+		.size = SZ_2G,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+	/* PSRAM for SPL runtime  */
+
+	{
+		.virt = 0x85200000,
+		.phys = 0x85200000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_CACHED_MEM,
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+#else
+	/* TPL table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+#endif
+#else
+	/* u-boot table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	{
+		/* CCI 500 */
+		.virt = 0x81100000,
+		.phys = 0x81100000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* SYSPORT 0 and 1 */
+		.virt = 0x80400000,
+		.phys = 0x80400000,
+		.size = SZ_2M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* BIU */
+		.virt = 0x81000000,
+		.phys = 0x81000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* UBUS */
+		.virt = 0x83000000,
+		.phys = 0x83000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* USB (includes other blocks in the 1M window) */
+		.virt = 0x8000c000,
+		.phys = 0x8000c000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+#endif
+	{
+		/* PMC */
+		.virt = 0x80200000,
+		.phys = 0x80200000,
+		.size = SZ_2M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* MEMC PHY register */
+		.virt = 0x80100000,
+		.phys = 0x80100000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000,
+		.phys = 0xff800000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* BLUT */
+		.virt = 0xfff00000,
+		.phys = 0xfff00000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	}, 
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm947622_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm4908/Kconfig b/arch/arm/mach-bcmbca/bcm4908/Kconfig
new file mode 100644
index 0000000000..fe70b01d54
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4908/Kconfig
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM4908
+
+config TARGET_BCM94908
+	bool "Broadcom 4908 Reference Board"
+	depends on ARCH_BCMBCA
+
+config SYS_SOC
+	default "bcm4908"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+	hex "default DDR3 mcb selector value"
+	default 0x523
+endif
+
+config RSVD_USE_MAX_FROM_ENV_AND_DT 
+	bool "RSVD will use max value from env and DT"
+	default y
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm4908/Makefile b/arch/arm/mach-bcmbca/bcm4908/Makefile
new file mode 100644
index 0000000000..8cb9592c8f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4908/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+obj-y += mmu_table.o
+obj-y += cpu.o
\ No newline at end of file
diff --git a/arch/arm/mach-bcmbca/bcm4908/cpu.c b/arch/arm/mach-bcmbca/bcm4908/cpu.c
new file mode 100644
index 0000000000..0572deaa5f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4908/cpu.c
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/sections.h>
+#include <asm/arch/cpu.h>
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#endif
+#if defined(CONFIG_BCMBCA_DDRC)
+#include "spl_ddrinit.h"
+#endif
+#include "bcmbca-dtsetup.h"
+
+uint32_t cpu_speed = 0;
+#define DUAL_CORE_4906 0x4906
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+
+static void enable_ubus_fast_write_ack(void)
+{
+	BIUCTRL->ubus_cfg |= 0x70;
+}
+
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+	printf("Chip ID: BCM%X_%X\n",chipId,revId);
+}
+#endif
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_EMMC)
+		return BOOT_DEVICE_MMC1;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NOR)
+		return BOOT_DEVICE_NOR;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+#if defined(CONFIG_BCMBCA_PMC)
+
+void boost_cpu_clock(void)
+{
+	cpu_speed = (MISC->miscStrapBus&MISC_STRAP_BUS_CPU_SLOW_FREQ) ? 400: 1800;
+	printf("set cpu freq to 1800MHz from %dMHz\n", cpu_speed);
+	set_cpu_freq(1800);
+}
+
+int set_cpu_freq(int freqMHz)
+{
+	PLL_CTRL_REG ctrl_reg;
+	uint32_t clkcfg;
+
+	/* only support 1800MHz and 400MHz for now */
+	if( freqMHz != 1800 && freqMHz != 400)
+	{
+		printf("%dMHz is not supported, stay with %dMHz\n", freqMHz, cpu_speed);
+		return -1;
+	}
+
+	/* this code is used to switch from default slow cpu 400MHz to 1.8GHz */
+	if( freqMHz == 1800 )
+	{
+		if( cpu_speed == 400 )
+		{
+			ReadBPCMRegister(PMB_ADDR_B53PLL, PLLBPCMRegOffset(resets), &ctrl_reg.Reg32);
+			ctrl_reg.Bits.byp_wait = 0;
+			WriteBPCMRegister(PMB_ADDR_B53PLL, PLLBPCMRegOffset(resets), ctrl_reg.Reg32);
+		}
+		/* adjust clock divider and safe mode setting for better perfomance */
+		clkcfg = BIUCTRL->clock_cfg;
+		clkcfg &= ~(BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_MASK|BIU_CPU_CTRL_CLK_CFG_SAFE_CLOCK_MODE_MASK|BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_MASK);
+		clkcfg |= (BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_DIV2|BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_DIV1);
+		BIUCTRL->clock_cfg = clkcfg;
+	}
+
+	if( freqMHz == 400 )
+	{
+		/* turn on safe mode setting */
+		clkcfg = BIUCTRL->clock_cfg;
+		clkcfg &= ~(BIU_CPU_CTRL_CLK_CFG_SAFE_CLOCK_MODE_MASK);
+		clkcfg |= (BIU_CPU_CTRL_CLK_CFG_SAFE_CLOCK_MODE_MASK);
+		BIUCTRL->clock_cfg = clkcfg;
+
+		if( cpu_speed == 1800)
+		{
+			ReadBPCMRegister(PMB_ADDR_B53PLL, PLLBPCMRegOffset(resets), &ctrl_reg.Reg32);
+			ctrl_reg.Bits.byp_wait = 1;
+			WriteBPCMRegister(PMB_ADDR_B53PLL, PLLBPCMRegOffset(resets), ctrl_reg.Reg32);
+		}
+	}
+
+	cpu_speed = freqMHz;
+	return freqMHz;
+}
+#endif
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	enable_ubus_fast_write_ack();
+#if defined(CONFIG_BCMBCA_DDRC)
+	spl_ddrinit_prepare();
+#endif
+	/* enable unalgined access */
+	set_sctlr(get_sctlr() & ~CR_A);
+#endif
+	return 0;
+}
+int get_nr_cpus()
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	int nr_cpus=QUAD_CPUS;
+
+	if(chipId == DUAL_CORE_4906)
+		nr_cpus=DUAL_CPUS;
+
+	return nr_cpus;
+}
+
+#if !defined(CONFIG_TPL_ATF)
+void boot_secondary_cpu(unsigned long vector)
+{
+	uint32_t cpu, nr_cpus = QUAD_CPUS;
+
+	printf("boot secondary cpu from 0x%lx\n", vector);
+
+	nr_cpus = get_nr_cpus();
+	cpu = 1;
+	while (cpu < nr_cpus) {
+		BOOT_LUT->bootLutRst = (uint32_t)vector;
+		BIUCTRL->power_cfg |= (0x1 << (cpu+BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON_SHIFT));
+		BIUCTRL->reset_cfg &= ~(0x1 << cpu);
+		cpu++;
+	}
+
+	return;
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm4908/mmu_table.c b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c
new file mode 100644
index 0000000000..8a9a6d1f08
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region broadcom_bcm94908_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	/* DDR memory. Enable the maximum 4GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 2UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* MEMC and DDRY PHY control registers */
+	{
+		.virt = 0x80018000UL,
+		.phys = 0x80018000UL,
+		.size = 0x40000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* RDP MEM for bootrom runtime  */
+	{
+		.virt = CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_128K_OFFSET,
+		.phys = CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_128K_OFFSET,
+		.size = SZ_128K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+	/* RDP MEM 32Kfor bootrom runtime  */
+	{
+		.virt = CONFIG_SYS_INIT_RAM_ADDR_VIRT,
+		.phys = CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_32K_OFFSET,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+	/* RDP MEM 48K part 0 bootrom runtime  */
+	{
+		.virt = CONFIG_SYS_INIT_RAM_ADDR_VIRT + SZ_32K,
+		.phys = CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_48K_0_OFFSET,
+		.size = SZ_32K + SZ_16K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+	/* RDP MEM 48K part 1 bootrom runtime  */
+	{
+		.virt = CONFIG_SYS_INIT_RAM_ADDR_VIRT + SZ_32K + SZ_32K + SZ_16K,
+		.phys = CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_48K_1_OFFSET,
+		.size = SZ_32K + SZ_16K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#else
+	/* DDR entries for cached memory, total size is a placehold
+	   and will be filled in at run time. MUST be first entry */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 1UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+		/* PMC */
+	{
+		.virt = 0x80200000,
+		.phys = 0x80200000,
+		.size = 0x81000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* USB */
+	{
+		.virt = 0x8000C000UL,
+		.phys = 0x8000C000UL,
+		.size = 0x3000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+		/* BIUCFG */
+	{
+		.virt = 0x81062000UL,
+		.phys = 0x81062000UL,
+		.size = 0x1000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+		/* BOOTLUT */
+	{
+		.virt = 0xffff0000UL,
+		.phys = 0xffff0000UL,
+		.size = 0x1000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+		/* UNIMAC */
+	{
+		.virt = 0x80002000UL,
+		.phys = 0x80002000UL,
+		.size = 0x1000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+		/* SF2 */
+	{
+		.virt = 0x80080000UL,
+		.phys = 0x80080000UL,
+		.size = 0x42000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#endif
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000UL,
+		.phys = 0xff800000UL,
+		.size = 0x100000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, 
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm94908_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm4912/Kconfig b/arch/arm/mach-bcmbca/bcm4912/Kconfig
new file mode 100644
index 0000000000..5c34bc769e
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4912/Kconfig
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM4912
+
+config TARGET_BCM94912
+	bool "Broadcom 4912 Reference Board"
+	depends on ARCH_BCMBCA
+
+config SYS_SOC
+	default "bcm4912"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+	hex "default DDR3 mcb selector value"
+	default 0x41607
+
+config BCMBCA_DDR4_DEF_MCBSEL
+	hex "default DDR4 mcb selector value"
+	default 0x141733
+endif
+
+config RSVD_USE_MAX_FROM_ENV_AND_DT 
+	bool "RSVD will use max value from env and DT"
+	default y
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm4912/Makefile b/arch/arm/mach-bcmbca/bcm4912/Makefile
new file mode 100644
index 0000000000..e7f9f65ffb
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4912/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+obj-y += mmu_table.o
+obj-y += cpu.o
diff --git a/arch/arm/mach-bcmbca/bcm4912/cpu.c b/arch/arm/mach-bcmbca/bcm4912/cpu.c
new file mode 100644
index 0000000000..919ac8bd47
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4912/cpu.c
@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_DDRC)
+#include <asm/arch/ddr.h>
+#endif
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#endif
+#include "tpl_params.h"
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+
+static void enable_ts0_couner(void)
+{
+	BIUCFG->ts0_ctrl.CNTCR |= 0x1;
+}
+
+static void enable_upper_memory_access(void)
+{
+	/* enable the 8G to 16G address range for memc */ 	
+	BIUCFG->bac.bac_cciaddr = 0x55550055;
+	CCI500->ctrl_ovr |= (1 << 29);
+}
+
+#elif defined(CONFIG_TPL_BUILD)
+static void cci500_enable(void)
+{
+	/*Enable access from E2 and below */
+	CCI500->secr_acc |= SECURE_ACCESS_UNSECURE_ENABLE;
+}
+
+static void enable_ns_access(void)
+{
+	BIUCFG->bac.bac_permission |= 0x33; // Linux access to BAC_CPU_THERM_TEMP
+}
+
+static void disable_memc_sram(void)
+{
+	uint32_t addr = MEMC_BASE + mc2_afx_sram_match_cfg_sram_start_addr_hi;
+	
+	writel(readl(addr)&~0x80000000, addr);
+}
+
+static void setup_ubus_rangechk(void)
+{
+	/* Size in MB. First 2GB is set up by default */  
+	int size_left = tplparams->ddr_size - 2048;
+	int size, size_bit, i = 1;
+#ifdef PHYS_SDRAM_2
+	uint64_t addr = PHYS_SDRAM_2;
+#else
+	uint64_t addr = 0x100000000UL;
+#endif
+	
+	/* Fix the default of RC0 to only enable lower 2G memory for ubus master */
+	UBUS4_RANGE_CHK_SETUP->cfg[0].base = 0x13;
+	
+	/* setup the second range check for the top DDR region */
+	while (size_left > 0 && i < 16) {
+		/* each range checker can support up to 4GB size */  
+		if (size_left > 4096 )
+			size = 4096;
+		else
+			size = size_left;
+		size_left -= size;
+		size_bit = 0;
+		size = (size << 8);  /* MB to # of 4KB */
+		while (size) {
+			size = (size >> 1);
+			if (size)
+				size_bit++;
+		}
+
+	        UBUS4_RANGE_CHK_SETUP->cfg[i].control = 0x1f0;
+		UBUS4_RANGE_CHK_SETUP->cfg[i].srcpid[0] = 0xffffffff;
+		UBUS4_RANGE_CHK_SETUP->cfg[i].seclev = 0xffffffff;
+		UBUS4_RANGE_CHK_SETUP->cfg[i].base = (addr&0xffffffe0) | size_bit;
+		UBUS4_RANGE_CHK_SETUP->cfg[i].base_up = addr >> 32;
+
+		addr += 4096UL << size_bit;
+		i++;
+	}
+}
+
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+	printf("Chip ID: BCM%X_%X\n",chipId,revId);
+}
+#endif
+
+#if defined(CONFIG_BCMBCA_PMC)
+void boost_cpu_clock(void)
+{
+	printf("set cpu freq to 2000MHz\n");
+	set_cpu_freq(2000);
+	pll_ch_freq_set(PMB_ADDR_BIU_PLL, 1, 4000/800); // raise ACEBIU clock rate to 800 MHz
+}
+
+int set_cpu_freq(int freqMHz)
+{
+	int mdiv;
+
+	if( freqMHz > 2000 || freqMHz < 400 )
+	{
+		printf("%dMHz is not supported\n", freqMHz);
+		return -1;
+	}
+
+	/* VCO at 4GHz, mdiv = Fvco/target frequency */
+	mdiv = 4000/freqMHz;
+
+	pll_ch_freq_set(PMB_ADDR_BIU_PLL, 0, mdiv);
+
+	return 4000/mdiv;
+}
+#endif
+
+static int reset_plls(void)
+{
+	/* Software workaround for non-resetting eMMC PLL */
+	pll_ch_reset(PMB_ADDR_BIU_PLL, 5, PLLBPCMRegOffset(ch45_cfg));
+	return 0;
+}
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	enable_ts0_couner();
+#if defined(CONFIG_BCMBCA_DDRC)
+	spl_ddrinit_prepare();
+#endif
+	enable_upper_memory_access();
+	/* enable unalgined access */
+	set_sctlr(get_sctlr() & ~CR_A);
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+	enable_ns_access();
+	disable_memc_sram();
+	setup_ubus_rangechk();
+	cci500_enable();
+#endif
+
+    reset_plls();
+    return 0;
+}
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_EMMC)
+		return BOOT_DEVICE_MMC1;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+#if !defined(CONFIG_TPL_ATF)
+void boot_secondary_cpu(unsigned long vector)
+{
+	uint32_t cpu, nr_cpus = 4;
+	ARM_CONTROL_REG ctrl_reg;
+	uint64_t rvbar = vector;
+
+	printf("boot secondary cpu from 0x%lx\n", vector);
+
+	cpu = 1;
+	while (cpu < nr_cpus) {
+		int stat;
+
+		BIUCFG->cluster[0].rvbar_addr[cpu] = rvbar;
+		stat = PowerOnDevice(PMB_ADDR_ORION_CPU0 + cpu);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to power on secondary cpu %d - sts %d\n", cpu, stat);
+
+		stat = ReadBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), &ctrl_reg.Reg32);
+		ctrl_reg.Bits.cpu_reset_n &= ~(0x1 << cpu);
+		stat |= WriteBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), ctrl_reg.Reg32);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to boot secondary cpu %d - sts %d\n", cpu, stat);
+		cpu++;
+	}
+
+	return;
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm4912/mmu_table.c b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c
new file mode 100644
index 0000000000..f38d54a48a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#ifdef CONFIG_SPL_XIP_SUPPORT
+#include <boot_flash.h>
+#endif
+
+static struct mm_region broadcom_bcm94912_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	/* DDR memory. Enable the maximum 8GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 2UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	{
+		.virt = 0x100000000UL,
+		.phys = 0x100000000UL,
+		.size = 6UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* MEMC control registers */
+	{
+		.virt = 0x80040000UL,
+		.phys = 0x80040000UL,
+		.size = 0x2000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+	/* DDR PHY control registers */
+	{
+		.virt = 0x80060000UL,
+		.phys = 0x80060000UL,
+		.size = 0x6000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* DPFE control registers */
+	{
+		.virt = 0x80070000UL,
+		.phys = 0x80070000UL,
+		.size = 0xc000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+	/* LMEM for bootrom runtime  */
+	{
+		.virt = CONFIG_SYS_INIT_RAM_ADDR,
+		.phys = CONFIG_SYS_INIT_RAM_ADDR,
+		.size = CONFIG_SYS_INIT_RAM_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+#ifdef CONFIG_SPL_XIP_SUPPORT
+	/* NOR FLASH XIP Window */
+	{
+		.virt = NOR_XIP_BASE_ADDR,
+		.phys = NOR_XIP_BASE_ADDR,
+		.size = 0x100000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#endif
+#else
+	/* DDR entries for cached memory, total size is a placehold
+	   and will be filled in at run time. MUST be first entry */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 1UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+		/* GIC */
+	{
+		.virt = 0x81001000UL,
+		.phys = 0x81001000UL,
+		.size = 0x7000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+
+	{
+		/* XRDP PSRAM */
+		.virt = 0x82000000UL,
+		.phys = 0x82000000UL,
+		.size = 0x30000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	},
+
+	{
+		/* XRDP Rest of block */
+		.virt = 0x82700000UL,
+		.phys = 0x82700000UL,
+		.size = 0x600000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+	{
+		/* ETH_PHY_TOP */
+		.virt = 0x837ff000UL,
+		.phys = 0x837ff000UL,
+		.size = 0x1000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+	{
+		/* PMC */
+		.virt = 0xffa00000UL,
+		.phys = 0xffa00000UL,
+		.size = 0x200000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#endif
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000UL,
+		.phys = 0xff800000UL,
+                .size = 0x100000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* CCI-500 */
+	{
+		.virt = 0x81100000,
+		.phys = 0x81100000,
+		.size = 0x91000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},	
+		/* BIUCFG */
+	{
+		.virt = 0x81060000,
+		.phys = 0x81060000,
+		.size = 0x3000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+		/* UBUS4 Coherency Port */
+	{
+		.virt = 0x810A0000,
+		.phys = 0x810A0000,
+		.size = 0x1000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm94912_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm63138/Kconfig b/arch/arm/mach-bcmbca/bcm63138/Kconfig
new file mode 100644
index 0000000000..eb14e61d74
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/Kconfig
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM63138
+
+config TARGET_BCM963138
+	bool "Broadcom 63138 Reference Board"
+	depends on ARCH_BCMBCA
+
+config SYS_SOC
+	default "bcm63138"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+	hex "default DDR3 mcb selector value"
+	default 0x421
+endif
+
+config TPL_MAX_SIZE
+	default 1048576
+
+config RSVD_USE_MAX_FROM_ENV_AND_DT 
+	bool "RSVD will use max value from env and DT"
+	default y
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm63138/Makefile b/arch/arm/mach-bcmbca/bcm63138/Makefile
new file mode 100644
index 0000000000..6ac5fdfe02
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+obj-y += cpu.o
+obj-y += mmu_table.o
+ifndef CONFIG_TPL_BUILD
+# SPL
+obj-$(CONFIG_SPL_BUILD)	+= pmc.o
+endif
+
+ifndef CONFIG_SPL_BUILD
+# u-boot proper
+obj-$(CONFIG_BCMBCA_RDP) += rdp_fw/
+endif
\ No newline at end of file
diff --git a/arch/arm/mach-bcmbca/bcm63138/cpu.c b/arch/arm/mach-bcmbca/bcm63138/cpu.c
new file mode 100644
index 0000000000..62d851c339
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/cpu.c
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/misc.h>
+#include <spl.h>
+#include "bcmbca-dtsetup.h"
+
+#define SINGLE_CORE_63132 0x63132
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+static void set_vr_gain(void)
+{
+	/* set the internal voltage regulator gain to 8. This reduces the response time and keeps
+	   voltage supply to ddr stable. */
+	PROCMON->SSBMaster.wr_data = 0x800;
+	PROCMON->SSBMaster.control = 0x3440;
+	PROCMON->SSBMaster.control = 0xb440;
+	while (PROCMON->SSBMaster.control & 0x8000) ;
+
+	PROCMON->SSBMaster.wr_data = 0x802;
+	PROCMON->SSBMaster.control = 0x3440;
+	PROCMON->SSBMaster.control = 0xb440;
+	while (PROCMON->SSBMaster.control & 0x8000) ;
+
+	PROCMON->SSBMaster.wr_data = 0x800;
+	PROCMON->SSBMaster.control = 0x3440;
+	PROCMON->SSBMaster.control = 0xb440;
+	while (PROCMON->SSBMaster.control & 0x8000) ;
+}
+
+static void enable_ubus_fast_ack(void)
+{
+	ARMAIPCTRL->cfg |= AIP_CTRL_CFG_WR_FAST_ACK_MASK;
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+	printf("Chip ID: BCM%X_%X\n",chipId,revId);
+}
+#endif
+
+int bcmbca_get_boot_device(void)
+{
+	if ( (MISC->miscStrapBus & MISC_STRAP_BUS_SW_BOOT_SPI_SPINAND_EMMC_MASK) &&
+		((MISC->miscStrapBus & MISC_STRAP_BUS_BOOT_OPT_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND) )
+		return BOOT_DEVICE_SPI;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SPI_NOR) != MISC_STRAP_BUS_BOOT_SPI_NOR)
+		return BOOT_DEVICE_NAND;
+
+	if ( (MISC->miscStrapBus & MISC_STRAP_BUS_SW_BOOT_SPI_SPINAND_EMMC_MASK) &&
+		((MISC->miscStrapBus & MISC_STRAP_BUS_BOOT_OPT_MASK) == MISC_STRAP_BUS_BOOT_EMMC) )
+		return BOOT_DEVICE_MMC1;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+void boost_cpu_clock(void)
+{
+	printf("set cpu freq to 1000MHz\n");
+	set_cpu_freq(1000);
+}
+
+int set_cpu_freq(int freqMHz)
+{
+	int mdiv = 0;
+	int policy = 0;
+
+	if (freqMHz < 200 || freqMHz > 1000) {
+		printf("invalid cpu frequency %d\n", freqMHz);
+		return -1;
+	}
+
+	/* enable write access the arm clk mananger */
+	ARMCFG->proc_clk.wr_access |=
+	    (ARM_PROC_CLK_WR_ACCESS_PASSWORD <<
+	     ARM_PROC_CLK_WR_ACCESS_PASSWORD_SHIFT) |
+	    ARM_PROC_CLK_WR_ACCESS_CLKMGR_ACC;
+	mdiv = 2000 / freqMHz;
+
+	if (mdiv < 10) {	/* setting frequency between 200 MHz and 1 GHz */
+		/* set clk divider and enable pll */
+		int ndiv = 2 * 1000 / 25;	// ndiv based on 1GHz
+
+		ARMCFG->proc_clk.pllarma =
+		    (ARMCFG->proc_clk.
+		     pllarma & ~(ARM_PROC_CLK_PLLARMA_PDIV_MASK |
+				 ARM_PROC_CLK_PLLARMA_NDIV_MASK |
+				 ARM_PROC_CLK_PLLARMA_PWRDWN_SWOVRRIDE_MASK)) |
+		    (2 << ARM_PROC_CLK_PLLARMA_PDIV_SHIFT) | (ndiv <<
+							      ARM_PROC_CLK_PLLARMA_NDIV_SHIFT)
+		    | ARM_PROC_CLK_PLLARMA_SOFT_RESETB_N;
+
+		/* wait for pll to lock */
+		while ((ARMCFG->proc_clk.
+			pllarma & ARM_PROC_CLK_PLLARMA_PLL_LOCK_RAW) == 0) ;
+
+		/* enable post diveder */
+		ARMCFG->proc_clk.pllarma |=
+		    ARM_PROC_CLK_PLLARMA_SOFT_POST_RESETB_N;
+	}
+
+	/* set the freq policy */
+	policy =
+	    (freqMHz ==
+	     200) ? ARM_PROC_CLK_POLICY_FREQ_SYSCLK :
+	    ARM_PROC_CLK_POLICY_FREQ_ARMPLL_SLOW;
+	ARMCFG->proc_clk.policy_freq =
+	    (ARMCFG->proc_clk.
+	     policy_freq & ~ARM_PROC_CLK_POLICY_FREQ_MASK) | (policy <<
+							      ARM_PROC_CLK_POLICY3_FREQ_SHIFT)
+	    | (policy << ARM_PROC_CLK_POLICY2_FREQ_SHIFT) | (policy <<
+							     ARM_PROC_CLK_POLICY1_FREQ_SHIFT)
+	    | (policy << ARM_PROC_CLK_POLICY0_FREQ_SHIFT);
+
+	/* setting the mdiv */
+	ARMCFG->proc_clk.pllarmc &= 0xffffff00;
+	ARMCFG->proc_clk.pllarmc |= mdiv;
+	ARMCFG->proc_clk.pllarmc |= 0x800;
+
+	/* enabled hardware clock gating */
+	ARMCFG->proc_clk.core0_clkgate =
+	    (ARMCFG->proc_clk.
+	     core0_clkgate & ~ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_MASK) |
+	    (ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_HW <<
+	     ARM_PROC_CLK_CORE0_CLKGATE_GATING_SEL_SHIFT);
+	ARMCFG->proc_clk.core1_clkgate =
+	    (ARMCFG->proc_clk.
+	     core1_clkgate & ~ARM_PROC_CLK_CORE1_CLKGATE_GATING_SEL_MASK) |
+	    (ARM_PROC_CLK_CORE1_CLKGATE_GATING_SEL_HW <<
+	     ARM_PROC_CLK_CORE1_CLKGATE_GATING_SEL_SHIFT);
+	ARMCFG->proc_clk.arm_switch_clkgate =
+	    (ARMCFG->proc_clk.
+	     arm_switch_clkgate & ~ARM_PROC_CLK_SWITCH_CLKGATE_GATING_SEL_MASK)
+	    | (ARM_PROC_CLK_SWITCH_CLKGATE_GATING_SEL_HW <<
+	       ARM_PROC_CLK_SWITCH_CLKGATE_GATING_SEL_SHIFT);
+	ARMCFG->proc_clk.arm_periph_clkgate =
+	    (ARMCFG->proc_clk.
+	     arm_periph_clkgate & ~ARM_PROC_CLK_PERIPH_CLKGATE_GATING_SEL_MASK)
+	    | (ARM_PROC_CLK_PERIPH_CLKGATE_GATING_SEL_HW <<
+	       ARM_PROC_CLK_PERIPH_CLKGATE_GATING_SEL_SHIFT);
+	ARMCFG->proc_clk.apb0_clkgate =
+	    (ARMCFG->proc_clk.
+	     apb0_clkgate & ~ARM_PROC_CLK_APB0_CLKGATE_GATING_SEL_MASK) |
+	    (ARM_PROC_CLK_APB0_CLKGATE_GATING_SEL_HW <<
+	     ARM_PROC_CLK_APB0_CLKGATE_GATING_SEL_SHIFT);
+
+	/* enable the new freq policy */
+	ARMCFG->proc_clk.policy_ctl |=
+	    (ARM_PROC_CLK_POLICY_CTL_GO_AC | ARM_PROC_CLK_POLICY_CTL_GO);
+
+	/* wait for policy to be activated */
+	while (ARMCFG->proc_clk.policy_ctl & ARM_PROC_CLK_POLICY_CTL_GO) ;
+
+	return 2000/mdiv;
+}
+
+int get_nr_cpus()
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	int nr_cpus=DUAL_CPUS;
+
+	if(chipId == SINGLE_CORE_63132)
+		nr_cpus=ONE_CPU;
+
+	return nr_cpus;
+}
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	enable_ubus_fast_ack();
+	set_vr_gain();
+	/* enable unalgined access */
+	set_cr(get_cr() & ~CR_A);	
+#endif
+	return 0;
+}
diff --git a/arch/arm/mach-bcmbca/bcm63138/mmu_table.c b/arch/arm/mach-bcmbca/bcm63138/mmu_table.c
new file mode 100644
index 0000000000..98948624a0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/mmu_table.c
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include "mmu_map_v7.h"
+
+static struct mm_region broadcom_bcm963138_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_TPL_BUILD)
+	/* SPL table */
+
+	/* DDR memory. Enable the maximum 1GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000,
+		.phys = 0x00000000,
+		.size = SZ_1G,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+	/* LMEM for SPL runtime  */
+	{
+		.virt = 0x80700000,
+		.phys = 0x80700000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_CACHED_MEM,
+	},
+#else
+	/* TPL table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	/* LMEM for SPL runtime  */
+	{
+		.virt = 0x80700000,
+		.phys = 0x80700000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_CACHED_MEM,
+	},
+#endif
+#else
+	/* u-boot table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	{
+		/* APM */
+		.virt = 0x80100000,
+		.phys = 0x80100000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* RDP */
+		.virt = 0x80200000,
+		.phys = 0x80200000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+#endif
+	{
+		/* Register space (covers MEMC, USB, etc) */
+		.virt = 0x80000000,
+		.phys = 0x80000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* PMC */
+		.virt = 0x80400000,
+		.phys = 0x80400000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* SoC peripheral */
+		.virt = 0xfff00000,
+		.phys = 0xfff00000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	}, 
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm963138_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm63138/pmc.S b/arch/arm/mach-bcmbca/bcm63138/pmc.S
new file mode 100644
index 0000000000..70bfff18f5
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/pmc.S
@@ -0,0 +1,237 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include <linux/linkage.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/misc.h>
+
+/*  *********************************************************************
+    *  pmc_send_cmd()
+    *
+    *   send pmc cmd to DQM queue and wait for response
+    *   
+    *	 
+    *  Inputs:
+    *   r0 - DQM input word0 
+    *   r1 - DQM input word1
+    *   r2 - DQM input word2
+    *   r3 - DQM input word3
+    *	
+    *  Outputs:
+    *   r0 - DQM output word0 
+    *   r1 - DQM output word1
+    *   r2 - DQM output word2
+    *   r3 - DQM output word3
+    *	
+    *  Register used:
+    *   r0, r1, r2, r3, r4
+    ********************************************************************* */
+ENTRY(pmc_send_cmd)
+
+	ldr     r4, =PMC_DQM_QUEUE_DATA_BASE
+	add     r4, #PMC_DQM_QUEUE_DATA_HOST_TO_PMC 
+	str     r0, [r4, #0x0]
+        str     r1, [r4, #0x4]       
+        str     r2, [r4, #0x8]       
+        str     r3, [r4, #0xc]     /* Write register value (the 4th word) intiates the write  */ 
+
+        ldr     r4, =PMC_DQM_BASE
+        mov     r1, #2             /* Only need the status for DQM message queue 1 PMC to Host */
+pmcw:   ldr     r2, [r4, #PMC_DQM_NOT_EMPTY_STS]
+        and     r2, r2, r1          /* get rid of everything except 2nd bit  */
+	cmp     r2, #0 
+        beq     pmcw             /* Repeat until DQM1 is ready with data  */
+	
+        ldr     r4, =PMC_DQM_QUEUE_DATA_BASE
+	add     r4, #PMC_DQM_QUEUE_DATA_PMC_TO_HOST
+        ldr     r0, [r4, #0x0]
+        ldr     r1, [r4, #0x4]
+        ldr     r2, [r4, #0x8]
+        ldr     r3, [r4, #0xc]     /* read word 3 ( read is complete ... DQM1 has been flushed) */
+
+	mov  pc, lr
+ENDPROC(pmc_send_cmd)
+
+/*  *********************************************************************
+    *  pmb_send_cmd()
+    *
+    *   register access using power mamagement bus directly
+    *   
+    *	 
+    *  Inputs:
+    *   r0 - dev address 
+    *   r1 - register offset 
+    *   r2 - register value for write, ignore for read
+    *	r3 - 0 for read, 1 for write
+    *  Outputs:
+    *   r0 - return value
+    * 	     zero - success, 1 - time out, 2 - slave error
+    *   r1 - read value 
+    *	
+    *  Register used:
+    *   r0, r1, r2, r3, r4
+    ********************************************************************* */
+ENTRY(pmb_send_cmd)
+	
+	mov     r4, #3             /* check which power management bus */
+        ands    r4, r0, LSR #8
+	ldreq   r4, =PMBM0_BASE
+        ldrne   r4, =PMBM1_BASE
+
+	and     r0, #0xff
+	orr     r1, r0, LSL #12
+	orr     r1, r3, LSL #PMB_CNTRL_CMD_SHIFT
+
+	/* make sure PMBM is not busy */
+pmbw1:
+	mov     r3, #1
+	ldr     r0, [r4, #PMB_CNTRL]
+	ands    r3, r0, LSR #PMB_CNTRL_BUSY_SHIFT
+	bne     pmbw1
+
+	/* store the data if for write */
+	mov     r3, r1, LSR #PMB_CNTRL_CMD_SHIFT
+	ands    r3, #0x1
+	beq     scmd
+        str     r2, [r4, #PMB_WR_DATA]
+scmd:	
+	/* send the cmd */
+        str     r1, [r4, #PMB_CNTRL]
+	mov     r3, #1
+	orr     r1, r3, LSL #PMB_CNTRL_START_SHIFT
+        str     r1, [r4, #PMB_CNTRL]
+
+	/* make sure the cmd is done */
+pmbw2:
+	mov     r3, #1
+	ldr     r0, [r4, #PMB_CNTRL]
+	ands    r3, r0, LSR #PMB_CNTRL_START_SHIFT
+	bne     pmbw2
+
+	/* check if any error */
+	mov     r3, #1
+	ands    r3, r0, LSR #PMB_CNTRL_TIMEOUT_ERR_SHIFT
+	movne   r0, #1
+	bne     pmb_done
+	
+	mov     r3, #1
+	ands    r3, r0, LSR #PMB_CNTRL_SLAVE_ERR_SHIFT
+	movne   r0, #2
+	bne     pmb_done
+
+	mov     r0, #0
+	mov     r3, r1, LSR #PMB_CNTRL_CMD_SHIFT
+	ands    r3, #0x1
+	bne     pmb_done
+        ldr     r1, [r4, #PMB_RD_DATA]	
+	
+pmb_done:	
+	mov  pc, lr
+	
+ENDPROC(pmb_send_cmd)
+	
+/*  *********************************************************************
+    *  pmc_write_bpcm_reg()
+    *
+    *   perform a write to a BPCM register via the PMC message handler
+    *   
+    *	 
+    *  Inputs:
+    *   r0 - dev address 
+    *   r1 - register offset 
+    *   r2 - register value to write
+    *	
+    *  Outputs:
+    *   r0 - return value, pmc error code.
+    * 	     zero - success, non zero - error
+    *	
+    *  Register used:
+    *   r0, r1, r2, r3, r4, r10
+    ********************************************************************* */
+ENTRY(pmc_write_bpcm_reg)
+	mov	r10, lr		   /* persevere link reg across call */
+
+	ldr     r4, =MISC_BASE     /* check if PMC ROM is enabled or not */
+	ldr     r4, [r4, #MISC_STRAP_BUS]   
+	lsr     r4, #MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT
+	ands    r4, #0x1
+	beq     nopmc1
+	
+        mov     r3, r2
+        and     r2, r1, #0xff      /* register addr offset within pmbs device  */
+	ldr     r4, =0x3ff
+        and     r1, r0, r4
+	lsl     r1, #10            /* DQM message word1 pmb bus index[19:18]=0, dev addr within bus[17:10] */
+	mov     r0, #0xd           /* DQM message word0 cmdId[7:0]=cmdWriteBpcmReg=0x0d */
+
+	bl      pmc_send_cmd
+	
+	lsr     r0, #8
+	and     r0, #0xff         /* return the PMC error code */
+	b       write_reg_done
+	
+nopmc1:                           /* use PMB direct access */
+        mov     r3, #1            /* 1 for write */
+	bl      pmb_send_cmd
+	
+write_reg_done:	
+	mov	lr, r10		/* restore link */
+	mov	pc, lr
+ENDPROC(pmc_write_bpcm_reg)
+
+
+/*  *********************************************************************
+    *  pmc_read_bpcm_reg()
+    *
+    *   perform a read to a BPCM register via the PMC message handler
+    *   
+    *	 
+    *  Inputs:
+    *   r0 - dev address 
+    *   r1 - register offset 
+    *	
+    *  Outputs:
+    *   r0 - return value, pmc error code.
+    * 	     zero - success, non zero - error
+    *	r1 - register value if return success
+    *	
+    *  Register used:
+    *   r0, r1, r2, r3, r4, r10
+    ********************************************************************* */
+ENTRY(pmc_read_bpcm_reg)
+
+	mov	r10, lr		   /* persevere link reg across call */
+
+	ldr     r4, =MISC_BASE     /* check if PMC ROM is enabled or not */
+	ldr     r4, [r4, #MISC_STRAP_BUS]   
+	lsr     r4, #MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT
+	ands    r4, #0x1
+	beq     nopmc2
+
+        mov     r3, #0
+        and     r2, r1, #0xff      /* register addr offset within pmbs device  */
+	ldr     r4, =0x3ff
+        and     r1, r0, r4
+	lsl     r1, #10            /* DQM message word1 pmb bus index[19:18]=0, dev addr within bus[17:10] */
+	mov     r0, #0xb           /* DQM message word0 cmdId[7:0]=cmdReadBpcmReg=0x0b */
+
+        bl      pmc_send_cmd
+	
+	lsr     r0, #8
+	and     r0, #0xff      /* return the PMC error code */
+        mov     r1, r2
+	b       read_reg_done
+	
+nopmc2:                           /* use PMB direct access */
+        mov     r3, #0            /* 0 for write */
+	bl      pmb_send_cmd
+	
+read_reg_done:	
+	mov	lr, r10		/* restore link */
+	mov	pc, lr
+
+ENDPROC(pmc_read_bpcm_reg)
+
+	
diff --git a/arch/arm/mach-bcmbca/bcm63138/rdp_fw/Makefile b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/Makefile
new file mode 100644
index 0000000000..2d63fbb27b
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+KBUILD_CPPFLAGS += --include linux/types.h
+
+obj-y +=				\
+	runner_fw_b.o			\
+	runner_fw_c.o			\
+	runner_fw_d.o			\
+	predict_runner_fw_b.o		\
+	predict_runner_fw_c.o		\
+	predict_runner_fw_d.o
+
diff --git a/arch/arm/mach-bcmbca/bcm63138/rdp_fw/predict_runner_fw_b.c b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/predict_runner_fw_b.c
new file mode 100755
index 0000000000..ec2bba582f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/predict_runner_fw_b.c
@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint16_t firmware_predict_B[] = {
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0008,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x8000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0010,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x2020,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0040,
+    0x0000,
+    0x0082,
+    0x0000,
+    0x0020,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0001,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0100,
+    0x0000,
+    0x0080,
+    0x0000,
+    0x0020,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0100,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0080,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0001,
+    0x0002,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0100,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0004,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0400,
+    0x1000,
+    0x0010,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0200,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x4000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0002,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0200,
+    0x0000,
+    0x0000,
+    0x0200,
+    0x1000,
+    0x0000,
+    0x0000,
+    0x4000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x1000,
+    0x0040,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0080,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+};
diff --git a/arch/arm/mach-bcmbca/bcm63138/rdp_fw/predict_runner_fw_c.c b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/predict_runner_fw_c.c
new file mode 100755
index 0000000000..8d09bc7c9b
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/predict_runner_fw_c.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint16_t firmware_predict_C[] = {
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0008,
+    0x0000,
+    0x0000,
+    0x1004,
+    0x8009,
+    0x0000,
+    0x0000,
+    0x0002,
+    0x0200,
+    0x0000,
+    0x0008,
+    0x0400,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0010,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0080,
+    0x0000,
+    0x0000,
+    0x0010,
+    0x0001,
+    0x0001,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0002,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x4000,
+    0x0040,
+    0x0000,
+    0x2002,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0040,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x4000,
+    0x0000,
+    0x0040,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0001,
+    0x0000,
+    0x0200,
+    0x0000,
+    0x0000,
+    0x4000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0400,
+    0x0000,
+    0x0080,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0010,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0000,
+    0x0008,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x2000,
+    0x0200,
+    0x0010,
+    0x0000,
+    0x0000,
+    0x0400,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+};
diff --git a/arch/arm/mach-bcmbca/bcm63138/rdp_fw/predict_runner_fw_d.c b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/predict_runner_fw_d.c
new file mode 100755
index 0000000000..9f72dd814e
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/predict_runner_fw_d.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint16_t firmware_predict_D[] = {
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0200,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0101,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0004,
+    0x8000,
+    0x0010,
+    0x0000,
+    0x0000,
+    0x0200,
+    0x0000,
+    0x2000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x8000,
+    0x2000,
+    0x0000,
+    0x0009,
+    0x0004,
+    0x1000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x2000,
+    0x0000,
+    0x0000,
+    0x0200,
+    0x2000,
+    0x1000,
+    0x0800,
+    0x0000,
+    0x0804,
+    0x0100,
+    0x0002,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0040,
+    0x0001,
+    0x0001,
+    0x0000,
+    0x0002,
+    0x0004,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0100,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x0000,
+    0x0100,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0001,
+    0x0200,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+};
diff --git a/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_a_labels.h b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_a_labels.h
new file mode 100755
index 0000000000..97e3260d37
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_a_labels.h
@@ -0,0 +1,91 @@
+#ifndef RUNNER_A_CODE_ADDRESSES
+#define RUNNER_A_CODE_ADDRESSES
+
+#define runner_a_start_task_initialization_task		(0x14)
+#define runner_a_initialization_task		(0x14)
+#define runner_a_start_task_timer_scheduler_set		(0x38AC)
+#define runner_a_timer_scheduler_set		(0x38AC)
+#define runner_a_start_task_cpu_rx_wakeup_request		(0x2670)
+#define runner_a_cpu_rx_wakeup_request		(0x2670)
+#define runner_a_start_task_flow_cache_wakeup_request		(0xE78)
+#define runner_a_flow_cache_wakeup_request		(0xE78)
+#define runner_a_start_task_cpu_tx_wakeup_request		(0x2E1C)
+#define runner_a_cpu_tx_wakeup_request		(0x2E1C)
+#define runner_a_start_task_policer_budget_allocator_1st_wakeup_request		(0x39E0)
+#define runner_a_policer_budget_allocator_1st_wakeup_request		(0x39E0)
+#define runner_a_start_task_wan_direct_wakeup_request		(0x18D4)
+#define runner_a_wan_direct_wakeup_request		(0x18D4)
+#define runner_a_start_task_wan_cpu_wakeup_request		(0x204)
+#define runner_a_wan_cpu_wakeup_request		(0x204)
+#define runner_a_start_task_wan_normal_wakeup_request		(0x3C8)
+#define runner_a_wan_normal_wakeup_request		(0x3C8)
+#define runner_a_start_task_downstream_multicast_wakeup_request		(0x335C)
+#define runner_a_downstream_multicast_wakeup_request		(0x335C)
+#define runner_a_start_task_debug_routine		(0x11C)
+#define runner_a_debug_routine		(0x11C)
+#define runner_a_start_task_free_skb_index_wakeup_request		(0x39AC)
+#define runner_a_free_skb_index_wakeup_request		(0x39AC)
+#define runner_a_free_skb_index_tx_abs_done		(0x39AC)
+#define runner_a_start_task_dhd_tx_post		(0x4428)
+#define runner_a_dhd_tx_post		(0x4428)
+#define runner_a_start_task_dhd_tx_complete_wakeup_request		(0x484C)
+#define runner_a_dhd_tx_complete_wakeup_request		(0x484C)
+#define runner_a_dhd_tx_complete_check_next		(0x484C)
+#define runner_a_start_task_ipsec_ds_wakeup_request		(0x3CE8)
+#define runner_a_ipsec_ds_wakeup_request		(0x3CE8)
+#define runner_a_start_task_ethwan2_normal_wakeup_request		(0x260)
+#define runner_a_ethwan2_normal_wakeup_request		(0x260)
+#define runner_a_gpe_sop_push_replace_ddr_sram_32		(0x1A90)
+#define runner_a_gpe_sop_push_replace_sram_32_64		(0x1B04)
+#define runner_a_gpe_sop_push_replace_sram_64		(0x1B18)
+#define runner_a_gpe_sop_push_replace_sram_64_32		(0x1B2C)
+#define runner_a_gpe_sop_pull_replace_ddr_sram_32		(0x1B40)
+#define runner_a_gpe_sop_pull_replace_sram_32_64		(0x1BB4)
+#define runner_a_gpe_sop_pull_replace_sram_64		(0x1C04)
+#define runner_a_gpe_sop_pull_replace_sram_64_32		(0x1C40)
+#define runner_a_gpe_replace_pointer_32_ddr		(0x1C90)
+#define runner_a_gpe_replace_pointer_32_sram		(0x1CB4)
+#define runner_a_gpe_replace_pointer_64_sram		(0x1CD8)
+#define runner_a_gpe_replace_16		(0x1CFC)
+#define runner_a_gpe_replace_32		(0x1D30)
+#define runner_a_gpe_replace_bits_16		(0x1D54)
+#define runner_a_gpe_copy_add_16_cl		(0x1D80)
+#define runner_a_gpe_copy_add_16_sram		(0x1D8C)
+#define runner_a_gpe_copy_bits_16_cl		(0x1DD4)
+#define runner_a_gpe_copy_bits_16_sram		(0x1DE0)
+#define runner_a_gpe_insert_16		(0x1E28)
+#define runner_a_gpe_delete_16		(0x1E90)
+#define runner_a_gpe_decrement_8		(0x1ED0)
+#define runner_a_gpe_apply_icsum_16		(0x1EF4)
+#define runner_a_gpe_apply_icsum_nz_16		(0x1F18)
+#define runner_a_gpe_compute_csum_16_cl		(0x1F54)
+#define runner_a_gpe_compute_csum_16_sram		(0x1F60)
+#define runner_a_gpe_buffer_copy_16_sram		(0x1FA0)
+#define runner_a_gpe_buffer_copy_16_ddr		(0x1FC8)
+#define runner_a_ingress_classification_key_src_ip		(0x21D0)
+#define runner_a_ingress_classification_key_dst_ip		(0x2214)
+#define runner_a_ingress_classification_key_ipv6_flow_label		(0x2258)
+#define runner_a_ingress_classification_key_generic_rule_1		(0x227C)
+#define runner_a_ingress_classification_key_generic_rule_2		(0x2284)
+#define runner_a_ingress_classification_key_outer_tpid		(0x22F0)
+#define runner_a_ingress_classification_key_inner_tpid		(0x22FC)
+#define runner_a_ingress_classification_key_src_port		(0x2318)
+#define runner_a_ingress_classification_key_dst_port		(0x2338)
+#define runner_a_ingress_classification_key_outer_vlan		(0x2358)
+#define runner_a_ingress_classification_key_inner_vlan		(0x2370)
+#define runner_a_ingress_classification_key_dst_mac		(0x238C)
+#define runner_a_ingress_classification_key_src_mac		(0x2394)
+#define runner_a_ingress_classification_key_ether_type		(0x23BC)
+#define runner_a_ingress_classification_key_ip_protocol		(0x23D0)
+#define runner_a_ingress_classification_key_dscp		(0x23F4)
+#define runner_a_ingress_classification_key_ssid		(0x2410)
+#define runner_a_ingress_classification_key_ingress_port		(0x2414)
+#define runner_a_ingress_classification_key_outer_pbits		(0x2424)
+#define runner_a_ingress_classification_key_inner_pbits		(0x243C)
+#define runner_a_ingress_classification_key_number_of_vlans		(0x2458)
+#define runner_a_ingress_classification_key_layer3_protocol		(0x2468)
+#define runner_a_cpu_rx_meter_budget_allocate		(0x392C)
+#define runner_a_dhd_tx_post_close_aggregation		(0x3978)
+#define runner_a_schedule_free_skb_index		(0x3990)
+
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_b_labels.h b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_b_labels.h
new file mode 100755
index 0000000000..4c663c2fa3
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_b_labels.h
@@ -0,0 +1,56 @@
+#ifndef RUNNER_B_CODE_ADDRESSES
+#define RUNNER_B_CODE_ADDRESSES
+
+#define runner_b_start_task_initialization_task		(0x14)
+#define runner_b_initialization_task		(0x14)
+#define runner_b_start_task_timer_scheduler_set		(0x2E8C)
+#define runner_b_timer_scheduler_set		(0x2E8C)
+#define runner_b_start_task_cpu_rx_wakeup_request		(0x1574)
+#define runner_b_cpu_rx_wakeup_request		(0x1574)
+#define runner_b_start_task_cpu_tx_wakeup_request		(0x26A8)
+#define runner_b_cpu_tx_wakeup_request		(0x26A8)
+#define runner_b_start_task_policer_budget_allocator_1st_wakeup_request		(0x3338)
+#define runner_b_policer_budget_allocator_1st_wakeup_request		(0x3338)
+#define runner_b_start_task_rate_control_budget_allocator_1st_wakeup_request		(0x2588)
+#define runner_b_rate_control_budget_allocator_1st_wakeup_request		(0x2588)
+#define runner_b_start_task_wan_interworking_enqueue_wakeup_request		(0x208)
+#define runner_b_wan_interworking_enqueue_wakeup_request		(0x208)
+#define runner_b_start_task_wan_tx_wakeup_request		(0x6EC)
+#define runner_b_wan_tx_wakeup_request		(0x6EC)
+#define runner_b_start_task_debug_routine		(0x120)
+#define runner_b_debug_routine		(0x120)
+#define runner_b_start_task_timer_7_1st_wakeup_request		(0x30DC)
+#define runner_b_timer_7_1st_wakeup_request		(0x30DC)
+#define runner_b_start_task_free_skb_index_wakeup_request		(0x3020)
+#define runner_b_free_skb_index_wakeup_request		(0x3020)
+#define runner_b_start_task_dhd_tx_post		(0x3494)
+#define runner_b_dhd_tx_post		(0x3494)
+#define runner_b_ingress_classification_key_src_ip		(0x10AC)
+#define runner_b_ingress_classification_key_dst_ip		(0x10F0)
+#define runner_b_ingress_classification_key_ipv6_flow_label		(0x1134)
+#define runner_b_ingress_classification_key_generic_rule_1		(0x1158)
+#define runner_b_ingress_classification_key_generic_rule_2		(0x1160)
+#define runner_b_ingress_classification_key_outer_tpid		(0x11CC)
+#define runner_b_ingress_classification_key_inner_tpid		(0x11D8)
+#define runner_b_ingress_classification_key_src_port		(0x11F4)
+#define runner_b_ingress_classification_key_dst_port		(0x1214)
+#define runner_b_ingress_classification_key_outer_vlan		(0x1234)
+#define runner_b_ingress_classification_key_inner_vlan		(0x124C)
+#define runner_b_ingress_classification_key_dst_mac		(0x1268)
+#define runner_b_ingress_classification_key_src_mac		(0x1270)
+#define runner_b_ingress_classification_key_ether_type		(0x1298)
+#define runner_b_ingress_classification_key_ip_protocol		(0x12AC)
+#define runner_b_ingress_classification_key_dscp		(0x12D0)
+#define runner_b_ingress_classification_key_ssid		(0x12EC)
+#define runner_b_ingress_classification_key_ingress_port		(0x1304)
+#define runner_b_ingress_classification_key_outer_pbits		(0x1314)
+#define runner_b_ingress_classification_key_inner_pbits		(0x132C)
+#define runner_b_ingress_classification_key_number_of_vlans		(0x1348)
+#define runner_b_ingress_classification_key_layer3_protocol		(0x1358)
+#define runner_b_spdsvc_timer_wakeup_request		(0x2DF8)
+#define runner_b_cpu_rx_meter_budget_allocate		(0x2F0C)
+#define runner_b_upstream_rate_limiter_budget_allocate		(0x2F58)
+#define runner_b_schedule_free_skb_index		(0x3004)
+#define runner_b_pps_rate_limiter_timer_wakeup_request		(0x3140)
+
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_c_labels.h b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_c_labels.h
new file mode 100755
index 0000000000..9f4658f8f0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_c_labels.h
@@ -0,0 +1,40 @@
+#ifndef RUNNER_C_CODE_ADDRESSES
+#define RUNNER_C_CODE_ADDRESSES
+
+#define runner_c_start_task_initialization_task		(0x14)
+#define runner_c_initialization_task		(0x14)
+#define runner_c_start_task_timer_scheduler_set		(0x80C)
+#define runner_c_timer_scheduler_set		(0x80C)
+#define runner_c_start_task_lan_tx_wakeup_request		(0x454)
+#define runner_c_lan_tx_wakeup_request		(0x454)
+#define runner_c_start_task_cpu_tx_wakeup_request		(0xB2C)
+#define runner_c_cpu_tx_wakeup_request		(0xB2C)
+#define runner_c_start_task_lan_enqueue_ih_wakeup_request		(0x1C4)
+#define runner_c_lan_enqueue_ih_wakeup_request		(0x1C4)
+#define runner_c_start_task_lan_enqueue_pd_wakeup_request		(0x208)
+#define runner_c_lan_enqueue_pd_wakeup_request		(0x208)
+#define runner_c_start_task_multicast_lan_enqueue_wakeup_request		(0x258)
+#define runner_c_multicast_lan_enqueue_wakeup_request		(0x258)
+#define runner_c_start_task_wlan_mcast_wakeup_request		(0x2E7C)
+#define runner_c_wlan_mcast_wakeup_request		(0x2E7C)
+#define runner_c_start_task_cpu_rx_int_coalesce_timer_1st_wakeup_request		(0xA74)
+#define runner_c_cpu_rx_int_coalesce_timer_1st_wakeup_request		(0xA74)
+#define runner_c_start_task_debug_routine		(0xDC)
+#define runner_c_debug_routine		(0xDC)
+#define runner_c_start_task_gso_wakeup_request		(0x1D5C)
+#define runner_c_gso_wakeup_request		(0x1D5C)
+#define runner_c_start_task_timer_7_1st_wakeup_request		(0x9E0)
+#define runner_c_timer_7_1st_wakeup_request		(0x9E0)
+#define runner_c_start_task_free_skb_index_wakeup_request		(0x97C)
+#define runner_c_free_skb_index_wakeup_request		(0x97C)
+#define runner_c_start_task_service_queue_dequeue_wakeup_request		(0x37B4)
+#define runner_c_service_queue_dequeue_wakeup_request		(0x37B4)
+#define runner_c_start_task_service_queue_enqueue_wakeup_request		(0x3884)
+#define runner_c_service_queue_enqueue_wakeup_request		(0x3884)
+#define runner_c_ds_rate_limiter_budget_allocate		(0x88C)
+#define runner_c_ds_service_queue_rate_limiter_budget_allocate		(0x948)
+#define runner_c_schedule_free_skb_index		(0x960)
+#define runner_c_pps_rate_limiter_timer_wakeup_request		(0xA44)
+#define runner_c_spdsvc_timer_wakeup_request		(0x1044)
+
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_d_labels.h b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_d_labels.h
new file mode 100755
index 0000000000..7c3d5e5f2d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/rdd_runner_d_labels.h
@@ -0,0 +1,54 @@
+#ifndef RUNNER_D_CODE_ADDRESSES
+#define RUNNER_D_CODE_ADDRESSES
+
+#define runner_d_start_task_initialization_task		(0x14)
+#define runner_d_initialization_task		(0x14)
+#define runner_d_start_task_timer_scheduler_set		(0x1C44)
+#define runner_d_timer_scheduler_set		(0x1C44)
+#define runner_d_start_task_flow_cache_wakeup_request		(0xD94)
+#define runner_d_flow_cache_wakeup_request		(0xD94)
+#define runner_d_start_task_lan_dispatch_wakeup_request		(0x1A24)
+#define runner_d_lan_dispatch_wakeup_request		(0x1A24)
+#define runner_d_start_task_lan_cpu_wakeup_request		(0x154)
+#define runner_d_lan_cpu_wakeup_request		(0x154)
+#define runner_d_start_task_lan_normal_wakeup_request		(0x19C)
+#define runner_d_lan_normal_wakeup_request		(0x19C)
+#define runner_d_start_task_debug_routine		(0x6C)
+#define runner_d_debug_routine		(0x6C)
+#define runner_d_start_task_free_skb_index_wakeup_request		(0x1DC0)
+#define runner_d_free_skb_index_wakeup_request		(0x1DC0)
+#define runner_d_free_skb_index_tx_abs_done		(0x1DC0)
+#define runner_d_start_task_dhd_rx_complete_wakeup_request		(0x1F28)
+#define runner_d_dhd_rx_complete_wakeup_request		(0x1F28)
+#define runner_d_gpe_sop_push_replace_ddr_sram_32		(0x13D8)
+#define runner_d_gpe_sop_push_replace_sram_32_64		(0x144C)
+#define runner_d_gpe_sop_push_replace_sram_64		(0x1460)
+#define runner_d_gpe_sop_push_replace_sram_64_32		(0x1474)
+#define runner_d_gpe_sop_pull_replace_ddr_sram_32		(0x1488)
+#define runner_d_gpe_sop_pull_replace_sram_32_64		(0x14FC)
+#define runner_d_gpe_sop_pull_replace_sram_64		(0x154C)
+#define runner_d_gpe_sop_pull_replace_sram_64_32		(0x1588)
+#define runner_d_gpe_replace_pointer_32_ddr		(0x15D8)
+#define runner_d_gpe_replace_pointer_32_sram		(0x15FC)
+#define runner_d_gpe_replace_pointer_64_sram		(0x1620)
+#define runner_d_gpe_replace_16		(0x1644)
+#define runner_d_gpe_replace_32		(0x1678)
+#define runner_d_gpe_replace_bits_16		(0x169C)
+#define runner_d_gpe_copy_add_16_cl		(0x16C8)
+#define runner_d_gpe_copy_add_16_sram		(0x16D4)
+#define runner_d_gpe_copy_bits_16_cl		(0x171C)
+#define runner_d_gpe_copy_bits_16_sram		(0x1728)
+#define runner_d_gpe_insert_16		(0x1770)
+#define runner_d_gpe_delete_16		(0x17D8)
+#define runner_d_gpe_decrement_8		(0x1818)
+#define runner_d_gpe_apply_icsum_16		(0x183C)
+#define runner_d_gpe_apply_icsum_nz_16		(0x1860)
+#define runner_d_gpe_compute_csum_16_cl		(0x189C)
+#define runner_d_gpe_compute_csum_16_sram		(0x18A8)
+#define runner_d_gpe_buffer_copy_16_sram		(0x18E8)
+#define runner_d_gpe_buffer_copy_16_ddr		(0x1910)
+#define runner_d_upstream_ingress_rate_limiter_budget_allocate		(0x1CC4)
+#define runner_d_upstream_quasi_budget_allocate		(0x1D44)
+#define runner_d_schedule_free_skb_index		(0x1DA4)
+
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm63138/rdp_fw/runner_fw_b.c b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/runner_fw_b.c
new file mode 100755
index 0000000000..8defe496cf
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/runner_fw_b.c
@@ -0,0 +1,7180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint32_t firmware_binary_B[] = {
+    0x0A300005,
+    0xFC000000,
+    0x10000048,
+    0xFC000000,
+    0xFC000000,
+    0x221A7E42,
+    0x222A7E83,
+    0x224A7F03,
+    0x226A7F83,
+    0xC2001202,
+    0xC2001302,
+    0xBC801000,
+    0xBC800018,
+    0xC2021202,
+    0xC2021302,
+    0xBC8000F4,
+    0x969200F0,
+    0xBC800034,
+    0xD0020092,
+    0x228AECA1,
+    0xC2021502,
+    0xBC9A9F84,
+    0xBC800064,
+    0xBC8003C8,
+    0x2A124026,
+    0xCE920080,
+    0xBC992C04,
+    0xBC810AC8,
+    0xBC810F00,
+    0x2A824006,
+    0xBC811348,
+    0xBC811580,
+    0x2A824026,
+    0xBC811608,
+    0xBC800000,
+    0x2A824046,
+    0xBC800000,
+    0xBC811CC0,
+    0x2A824066,
+    0xBC811D88,
+    0xBC811F40,
+    0x2A824086,
+    0xBC812148,
+    0xBC812340,
+    0x2A8240A6,
+    0xBC8124C8,
+    0xBC812680,
+    0x2A8240C6,
+    0xBC812708,
+    0xBC812980,
+    0x2A8240E6,
+    0xBC812AC8,
+    0xBC812D00,
+    0x2A824106,
+    0xBC812EC8,
+    0xBC813040,
+    0x2A824126,
+    0xBC813148,
+    0xBC8132C0,
+    0x2A824146,
+    0xBC813488,
+    0xBC813580,
+    0x2A824166,
+    0xBC991904,
+    0xBC82F0CC,
+    0xBC82F580,
+    0x2A824006,
+    0xBC830044,
+    0x2A824055,
+    0x18000000,
+    0xFC000000,
+    0xFC000000,
+    0x2A0AA402,
+    0x2A1AA442,
+    0x2A2AA483,
+    0x2A4AA503,
+    0x2A6AA583,
+    0x2A8AA603,
+    0x2AAAA683,
+    0x2ACAA703,
+    0x2AEAA783,
+    0x2B0AA803,
+    0x2B2AA883,
+    0x2B4AA903,
+    0x2B6AA983,
+    0x2B8AAA03,
+    0x2BAAAA83,
+    0x2BCAAB03,
+    0x2BEAAB83,
+    0xC6800042,
+    0x2A8AF202,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xC2000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x220AA402,
+    0x221AA442,
+    0x222AA483,
+    0x224AA503,
+    0x226AA583,
+    0x228AA603,
+    0x22AAA683,
+    0x22CAA703,
+    0x22EAA783,
+    0x230AA803,
+    0x232AA883,
+    0x234AA903,
+    0x236AA983,
+    0x238AAA03,
+    0x23AAAA83,
+    0x23CAAB03,
+    0x23EAAB83,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x16000001,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x248A4000,
+    0xA4A20A80,
+    0x06720886,
+    0x2C0A4000,
+    0x22828784,
+    0x23A2876C,
+    0xBCB8C004,
+    0xA4B69020,
+    0x82924012,
+    0x8A92440A,
+    0x22C2875C,
+    0xA0E30650,
+    0xA4C00650,
+    0x2122C002,
+    0xA0D48D00,
+    0x86036080,
+    0x02008805,
+    0xBCFA0004,
+    0x02002008,
+    0xAAB36580,
+    0x80B3E0B0,
+    0xBCB83004,
+    0x96D34050,
+    0x80B2E0D0,
+    0x86032030,
+    0x0200C0E4,
+    0x96C30010,
+    0x82C32180,
+    0xFC000000,
+    0xA0F38650,
+    0x2182C0C5,
+    0xA5262100,
+    0x8312AEC0,
+    0x22C28407,
+    0xA5200700,
+    0xA5800600,
+    0x20B44000,
+    0x22EAE421,
+    0x0A32E057,
+    0x96B3C010,
+    0x82F2E1C0,
+    0x22B287FC,
+    0xA0B2CA00,
+    0x256600F5,
+    0x26F600A5,
+    0xA1431C00,
+    0x0A33AC5D,
+    0x2735803C,
+    0xBD100004,
+    0x8AE6A0F0,
+    0xFC000000,
+    0x0EFB8C05,
+    0xBCE07C04,
+    0x840520E0,
+    0x0200D0D2,
+    0x23428754,
+    0x0634E4ED,
+    0x27258025,
+    0x27458045,
+    0x84052120,
+    0x0200C8A5,
+    0x2A028784,
+    0x228AE1C1,
+    0xFC000000,
+    0x0F22100A,
+    0xA1331C00,
+    0xA0828A80,
+    0x22EAE1A1,
+    0xFC000000,
+    0x0A1390C3,
+    0x23428754,
+    0x02002009,
+    0x86E3A010,
+    0x2AEAE1A1,
+    0x22EAE181,
+    0xFC000000,
+    0x0A1390BC,
+    0x23428754,
+    0x86E3A010,
+    0x2AEAE181,
+    0xCB45E01E,
+    0xFC000000,
+    0xC945F13E,
+    0x0659E042,
+    0xBCE00064,
+    0xD0038082,
+    0xA140A000,
+    0x22208035,
+    0x8284A010,
+    0x2E858025,
+    0x26E58006,
+    0x2283C0A6,
+    0x80822130,
+    0x2A83C0A6,
+    0xC9A3813E,
+    0xA4C2C8E0,
+    0xA4D003B0,
+    0xA4D69170,
+    0x0A23A008,
+    0x28C50003,
+    0xCBA2801E,
+    0x20838002,
+    0x80822142,
+    0x02002005,
+    0x28838002,
+    0xA4E52000,
+    0xA4E52000,
+    0xA4E52100,
+    0x0A345CC2,
+    0x2EE58006,
+    0x26858075,
+    0x26B600B5,
+    0x26C60086,
+    0x8C82E080,
+    0x2E8600B5,
+    0x2283C026,
+    0x22B3C09C,
+    0x8C8220C0,
+    0x2A83C026,
+    0x0402C809,
+    0x8A82E018,
+    0x2A83C09C,
+    0x00002009,
+    0x2283C015,
+    0xD0020006,
+    0xBCB00024,
+    0xC202D702,
+    0x18004147,
+    0xFC000000,
+    0xFC000000,
+    0x20B44000,
+    0xFC000000,
+    0x0A32C3F9,
+    0x020023A4,
+    0xFC000000,
+    0xFC000000,
+    0x18002087,
+    0xFC000000,
+    0xFC000000,
+    0x06C49FA6,
+    0x23228446,
+    0xA1248440,
+    0x0A3487A3,
+    0x840520E0,
+    0x02008FA1,
+    0x82E52030,
+    0x0200239F,
+    0x8B43A038,
+    0xA4C51C00,
+    0x07F3501F,
+    0x237AF341,
+    0x80E32000,
+    0x81536000,
+    0x2545C002,
+    0xFC000000,
+    0x0A350816,
+    0xBD400014,
+    0xA1935E00,
+    0xA59506F0,
+    0x06F35803,
+    0xBD400034,
+    0xBD400074,
+    0xD0050194,
+    0xA4E2CAE0,
+    0x234AE5C0,
+    0xA4E50930,
+    0xA4E01370,
+    0x8F43A803,
+    0xA5501170,
+    0x2D45C003,
+    0x82E5C080,
+    0x8AE38019,
+    0x2AEAF341,
+    0xBD400294,
+    0x14000000,
+    0xBCE00024,
+    0xD0038140,
+    0x14000000,
+    0xFC000000,
+    0xFC000000,
+    0x10000C8C,
+    0xBD004E80,
+    0xFC000000,
+    0x10000C70,
+    0xBD004F40,
+    0xFC000000,
+    0x0A3643F7,
+    0xBC8A3004,
+    0xA0E28E60,
+    0x96B2C0F1,
+    0xA4D69170,
+    0x20E200E6,
+    0xBD0051C0,
+    0x10000CA8,
+    0xA1431C00,
+    0xBDA88004,
+    0xBC8FFFFC,
+    0x42EA0017,
+    0xFC000000,
+    0xFC000000,
+    0x237AF341,
+    0xA1A35170,
+    0xFC000000,
+    0x2485C002,
+    0xFC000000,
+    0x0A32080F,
+    0x80E32000,
+    0x81536000,
+    0x228AECA1,
+    0x82822120,
+    0x96820011,
+    0xA5520F00,
+    0x10080126,
+    0xFC000000,
+    0xFC000000,
+    0xBD005780,
+    0x10000CA2,
+    0xFC000000,
+    0xFC000000,
+    0x0200037B,
+    0x10000C86,
+    0xBD005880,
+    0xFC000000,
+    0x020013F8,
+    0xFC000000,
+    0x26E58055,
+    0xFC000000,
+    0x0A338018,
+    0x0A321806,
+    0x22838015,
+    0x8404A080,
+    0x02008814,
+    0x02001009,
+    0x22838046,
+    0x23438025,
+    0x8404A140,
+    0x02009351,
+    0x22838035,
+    0x8404A080,
+    0x0200980C,
+    0x22838066,
+    0x8534A140,
+    0xC6E020C1,
+    0x07F20005,
+    0xA8822130,
+    0x8403A080,
+    0x0200C347,
+    0x02000004,
+    0xA884E080,
+    0x8403A080,
+    0x0200C343,
+    0x0200100D,
+    0x23428754,
+    0x22C28407,
+    0x23428754,
+    0x2282C015,
+    0x8A8223F0,
+    0x86022200,
+    0x02005803,
+    0x82C52150,
+    0x82C52140,
+    0x02002011,
+    0x228287FC,
+    0xA0B20A00,
+    0x2283C015,
+    0x8A8223F0,
+    0x86022200,
+    0x02006007,
+    0x26858034,
+    0xA0C31C00,
+    0xCA80C01C,
+    0x02002007,
+    0xC88080CE,
+    0x82C52140,
+    0xCA81101C,
+    0xFC000000,
+    0xC88100CE,
+    0x82C52150,
+    0xA0828A80,
+    0xBCE00064,
+    0xD0038082,
+    0x86052010,
+    0x02009005,
+    0xCBA4801C,
+    0x02002004,
+    0xCA05201C,
+    0xFC000000,
+    0xCAC5E01C,
+    0x10080C5C,
+    0xFC000000,
+    0xFC000000,
+    0x00001009,
+    0xFC000000,
+    0x231287A4,
+    0xA0E4C600,
+    0xBD38B004,
+    0xA5338270,
+    0xAAE46020,
+    0x82E3A100,
+    0x02002310,
+    0x8115A000,
+    0x2164C0E5,
+    0x26844025,
+    0x82822010,
+    0x2E844025,
+    0x26B580A5,
+    0x26C58066,
+    0x81646000,
+    0x2282C006,
+    0x02002339,
+    0x8C8220C0,
+    0x2A82C006,
+    0x0A221004,
+    0x80C02086,
+    0x22ABCB82,
+    0x80C2A086,
+    0xBCAA0004,
+    0xFC000000,
+    0xAAB32580,
+    0x8152A0B0,
+    0x86032080,
+    0x0200A00A,
+    0x22A5400C,
+    0x236540C5,
+    0xBCB83004,
+    0x96A30050,
+    0x8152E0A0,
+    0xFC000000,
+    0xFC000000,
+    0x22A5400C,
+    0x236540C5,
+    0x0A32987B,
+    0x28020002,
+    0x22F54004,
+    0x26D580B5,
+    0x9F434000,
+    0xBD0077C0,
+    0x065501B1,
+    0x97450010,
+    0x834521C0,
+    0xFC000000,
+    0xFC000000,
+    0x24C58145,
+    0x22E540A6,
+    0xFC000000,
+    0x26A3003C,
+    0xFC000000,
+    0x06328180,
+    0xFC000000,
+    0x22AA9782,
+    0xFC000000,
+    0x0A228402,
+    0x0A1285A2,
+    0xBD007A80,
+    0x27E30006,
+    0xFC000000,
+    0x0A33E994,
+    0x20AF8003,
+    0xA1D29C00,
+    0xA172D170,
+    0xA4B01170,
+    0x84E3A1D0,
+    0x2AE540A6,
+    0x07F2D19F,
+    0xBD007C80,
+    0xA0E28320,
+    0xA4B38770,
+    0xBCE8C004,
+    0xA4E5D020,
+    0xA4A00320,
+    0x22F54015,
+    0x8AF3E3F0,
+    0x8603E200,
+    0x02005005,
+    0x26F30034,
+    0xCAF0401E,
+    0x02001005,
+    0xC8F001DE,
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+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+};
+char *rdpa_version_fw_b = "$Change: 239242 $";
diff --git a/arch/arm/mach-bcmbca/bcm63138/rdp_fw/runner_fw_c.c b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/runner_fw_c.c
new file mode 100755
index 0000000000..02013fa466
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/runner_fw_c.c
@@ -0,0 +1,4108 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint32_t firmware_binary_C[] = {
+    0x0A300005,
+    0xFC000000,
+    0x10000037,
+    0xFC000000,
+    0xFC000000,
+    0x221ABE42,
+    0x222AEC83,
+    0x224AED03,
+    0x226AED83,
+    0xC2001202,
+    0xC2001302,
+    0xBC801000,
+    0xBC800018,
+    0xC2021202,
+    0xC2021302,
+    0x228B9561,
+    0xC2021502,
+    0xC6801B82,
+    0x8A8221F9,
+    0x8E822801,
+    0xC2021B82,
+    0xC6801F42,
+    0x82802030,
+    0x8E822400,
+    0x8E822800,
+    0xC2021F42,
+    0xBC8B5000,
+    0xBC900014,
+    0x2A92024C,
+    0xBC9B6080,
+    0xFC000000,
+    0xBC8B9404,
+    0x2A824005,
+    0xBC8B9684,
+    0x2A824015,
+    0xBC8B6684,
+    0x2A824025,
+    0xBC828D44,
+    0x2A824035,
+    0xBC9B6F80,
+    0xFC000000,
+    0xBC8B9204,
+    0x2A824005,
+    0xBC8B9704,
+    0x2A824015,
+    0xBC80C244,
+    0x2A824035,
+    0xBC975D04,
+    0xBC8088C4,
+    0x2A824045,
+    0xBC809484,
+    0x2A824075,
+    0x18000000,
+    0xFC000000,
+    0xFC000000,
+    0x2A0B3202,
+    0x2A1B3242,
+    0x2A2B3283,
+    0x2A4B3303,
+    0x2A6B3383,
+    0x2A8B3403,
+    0x2AAB3483,
+    0x2ACB3503,
+    0x2AEB3583,
+    0x2B0B3603,
+    0x2B2B3683,
+    0x2B4B3703,
+    0x2B6B3783,
+    0x2B8B3803,
+    0x2BAB3883,
+    0x2BCB3903,
+    0x2BEB3983,
+    0xC6800042,
+    0x2A8B27C2,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xC2000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x220B3202,
+    0x221B3242,
+    0x222B3283,
+    0x224B3303,
+    0x226B3383,
+    0x228B3403,
+    0x22AB3483,
+    0x22CB3503,
+    0x22EB3583,
+    0x230B3603,
+    0x232B3683,
+    0x234B3703,
+    0x236B3783,
+    0x238B3803,
+    0x23AB3883,
+    0x23CB3903,
+    0x23EB3983,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x16000001,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x20BA4000,
+    0xA4A2CC80,
+    0x0672C871,
+    0x280A4000,
+    0x82924012,
+    0x8A92440A,
+    0x2312863C,
+    0x22C2875C,
+    0x228287FC,
+    0xA0F20800,
+    0x23428407,
+    0xA543CAE0,
+    0x23328784,
+    0xA5500770,
+    0x02002021,
+    0xBC800064,
+    0xD00200B2,
+    0x25424003,
+    0xFC000000,
+    0x07F5080A,
+    0x2C024002,
+    0x82924080,
+    0x8A924019,
+    0xA5500770,
+    0xA1150B30,
+    0xA0C50780,
+    0x02002015,
+    0xA0F50AE0,
+    0xA13503B0,
+    0x21428003,
+    0xBC802D14,
+    0x07F50854,
+    0xC2021702,
+    0x28028002,
+    0x020023F5,
+    0x82A28080,
+    0x8AA28029,
+    0x21424003,
+    0xFC000000,
+    0x07F5084C,
+    0x28024002,
+    0x82924080,
+    0x8A924808,
+    0xA1150B30,
+    0xA0C50780,
+    0xA0F50AE0,
+    0xA13503B0,
+    0xBC888004,
+    0xA4844650,
+    0xA4830620,
+    0x232B3181,
+    0x22BB3101,
+    0x20820002,
+    0xFC000000,
+    0xFC000000,
+    0x23620025,
+    0x22E20045,
+    0x8405A0E0,
+    0x0200883C,
+    0x0F64900C,
+    0x22EB7FD0,
+    0x232A0044,
+    0x22DB3161,
+    0x8D23A120,
+    0x0A136050,
+    0x86E36010,
+    0x22D2C035,
+    0x2B2B7FD0,
+    0x0200200B,
+    0x2ADB3101,
+    0x2AEB3161,
+    0x22DB3141,
+    0x8D23A120,
+    0x0A136047,
+    0x86D36010,
+    0x22E2C035,
+    0x2AEB3101,
+    0x2ADB3141,
+    0x2B2B7FD0,
+    0x22D20006,
+    0x82E5A010,
+    0x2AE20025,
+    0x0A236008,
+    0xA543E4E0,
+    0x2942C003,
+    0x20C34002,
+    0x80C320B2,
+    0x0200200E,
+    0x28C34002,
+    0xA4D2E000,
+    0xA4D2E000,
+    0xA4D2E100,
+    0x92E32070,
+    0x22FA00C4,
+    0xA0B51C00,
+    0x96B2C020,
+    0xA0C545C0,
+    0xA4B00400,
+    0xA4B386E0,
+    0xA4B3C710,
+    0xC202D8C2,
+    0x2AD20006,
+    0x22C20074,
+    0x22BA004C,
+    0x8CB2E0C0,
+    0x2ABA004C,
+    0x06709C04,
+    0x22B75A42,
+    0x82B2E010,
+    0x2AB75A42,
+    0x228A0034,
+    0x96820040,
+    0x00002010,
+    0x82822010,
+    0xC2021702,
+    0x18000005,
+    0xFC000000,
+    0xFC000000,
+    0x23720055,
+    0xFC000000,
+    0x0A35C018,
+    0x0A34D806,
+    0x22D5C015,
+    0x8405A0D0,
+    0x02008814,
+    0x02001009,
+    0x22D5C046,
+    0x22E5C025,
+    0x8405A0E0,
+    0x020093BA,
+    0x22D5C035,
+    0x8405A0D0,
+    0x0200980C,
+    0x22D5C066,
+    0x8535A0E0,
+    0xC6E020C1,
+    0x07F34005,
+    0xA8D36130,
+    0x8403A0D0,
+    0x0200C3B0,
+    0x02000004,
+    0xA8D4E0D0,
+    0x8403A0D0,
+    0x0200C3AC,
+    0x2282007C,
+    0xCA80C01C,
+    0x07F5680D,
+    0xA0B51C00,
+    0xC88080BE,
+    0x06709C0A,
+    0x22875A02,
+    0x82822010,
+    0x2A875A02,
+    0x228758C2,
+    0x22B75902,
+    0x86822010,
+    0x2A8758C2,
+    0x8002E080,
+    0x02004804,
+    0x100806E1,
+    0xFC000000,
+    0xCB15201C,
+    0x00001010,
+    0xFC000000,
+    0x23FB7FD0,
+    0xBD400064,
+    0x0A37C07E,
+    0x0A35007B,
+    0xFC000000,
+    0x22977982,
+    0xFC000000,
+    0x0A224402,
+    0x0A124476,
+    0x9C87C080,
+    0xBC9AB804,
+    0xA4920630,
+    0x82822010,
+    0xA0820600,
+    0x21E24002,
+    0x22B24026,
+    0xFC000000,
+    0x233F804C,
+    0x9E94C000,
+    0xA4B24720,
+    0x0652506F,
+    0x22DF8055,
+    0x93226070,
+    0x20CAC002,
+    0x94A04120,
+    0xC4D000D0,
+    0x23130005,
+    0x880360A0,
+    0x02006806,
+    0x22DF802C,
+    0x20E44003,
+    0x94904090,
+    0x020013F2,
+    0x8934E098,
+    0xA093C5C0,
+    0x96A24020,
+    0x82A2A0C0,
+    0x82B2A030,
+    0xFC000000,
+    0x213F80A5,
+    0x21DF80B4,
+    0xFC000000,
+    0x22A4C007,
+    0xA0A29180,
+    0xA0B2D180,
+    0x84A2E0A0,
+    0xA0A28C00,
+    0x86A2A080,
+    0x02008853,
+    0x82B2E010,
+    0xA0A39C00,
+    0x8602A440,
+    0x02008803,
+    0xBCA00444,
+    0xA4E29C00,
+    0x0E7B584E,
+    0xA0B2CC00,
+    0x2AB4C024,
+    0x22DF80C4,
+    0xA0A39C00,
+    0x96A28020,
+    0xA4A00400,
+    0xA4A486E0,
+    0xA4A34710,
+    0xA4A04340,
+    0xC20298C2,
+    0xA0A39B30,
+    0x97428030,
+    0xA4E01B30,
+    0xA4F007C0,
+    0x22A3007C,
+    0xCAA0401E,
+    0xA0B39C00,
+    0xC8A000BE,
+    0x96A28031,
+    0x82A2A080,
+    0xCAA5201E,
+    0x23330025,
+    0x0A35200F,
+    0x22AAEE03,
+    0x2AA44007,
+    0x2B430005,
+    0x20A50002,
+    0xA0A29C00,
+    0x96A28020,
+    0xA4A00400,
+    0xA4A486E0,
+    0xA4A34710,
+    0xC20298C2,
+    0x22A30025,
+    0x02002009,
+    0x8732A010,
+    0x2B330025,
+    0x22A30074,
+    0x2A030006,
+    0x2A030025,
+    0x22BF804C,
+    0x88A2E0A8,
+    0x2AAF804C,
+    0x22AB3181,
+    0x22BB3121,
+    0x0F329007,
+    0x2B12C035,
+    0x2B1B3121,
+    0x22AB3161,
+    0x02002006,
+    0x82A2A010,
+    0x2AAB3161,
+    0x22AB3141,
+    0x82A2A010,
+    0x2AAB3141,
+    0x07F3E028,
+    0x86A3A040,
+    0x8EB3E403,
+    0x229779A1,
+    0x86926010,
+    0x2A9779A1,
+    0x229F804C,
+    0xFC000000,
+    0x0A326B8B,
+    0xD00740A3,
+    0xBD400064,
+    0x229F8044,
+    0x02002387,
+    0x89F7E098,
+    0x2BFB7FD0,
+    0xBC900024,
+    0xC2025702,
+    0x18004547,
+    0xFC000000,
+    0xFC000000,
+    0x0200137F,
+    0x87452010,
+    0xBCB93004,
+    0xA4B34630,
+    0xA0A39C00,
+    0xFC000000,
+    0x22D2C006,
+    0x84036000,
+    0x0200C804,
+    0x020023AE,
+    0x84A360A0,
+    0x2AA2C006,
+    0x229F8066,
+    0x22AF8044,
+    0xFC000000,
+    0x22BA4024,
+    0x86B2E010,
+    0x020023EF,
+    0xA0B2CC00,
+    0x2ABA4024,
+    0x82C26010,
+    0xBCDB2C04,
+    0xA4D30630,
+    0x87932010,
+    0xBD7B7F84,
+    0xA5764600,
+    0x02002024,
+    0xBD406D44,
+    0x21A5C000,
+    0x0A368806,
+    0xBCC00024,
+    0xC2031702,
+    0x18006B07,
+    0xFC000000,
+    0xFC000000,
+    0x26976742,
+    0xA0E2DC00,
+    0x96C38020,
+    0x809260C0,
+    0xBCFB2404,
+    0xA4F64620,
+    0xBD1B7F84,
+    0xA5164600,
+    0xBCDABD04,
+    0xA4D64610,
+    0x42F24047,
+    0xFC000000,
+    0xFC000000,
+    0x20C3C002,
+    0xFC000000,
+    0x0A3303FB,
+    0xA5042100,
+    0x20944000,
+    0x20F34001,
+    0x86926010,
+    0x28944000,
+    0xA4B33C00,
+    0x28E3C001,
+    0x8293E020,
+    0x020023B4,
+    0xA4F24A00,
+    0x28F34001,
+    0xBCCB2C04,
+    0xFC000000,
+    0x20D34000,
+    0x20E30194,
+    0x84E360E0,
+    0x8B83A3F0,
+    0x02006025,
+    0x28D30194,
+    0x29A5C000,
+    0xBD6B3B04,
+    0xA5664610,
+    0xBCDB3E04,
+    0x22CB9910,
+    0x21558001,
+    0xFC000000,
+    0x87862010,
+    0x20E54001,
+    0x83A6A010,
+    0x22F758C2,
+    0x231758A1,
+    0x0A33C40B,
+    0x840460E0,
+    0x02004809,
+    0x86F3E010,
+    0x2AF758C2,
+    0x23175A82,
+    0x83146010,
+    0x2B175A82,
+    0x23175902,
+    0x800460F0,
+    0x02004804,
+    0x8EE3A801,
+    0x28E340C5,
+    0x82C32020,
+    0x82E56020,
+    0xA5538A00,
+    0x06430804,
+    0x100006B9,
+    0xBCE07F84,
+    0x2723F342,
+    0x0A362BE7,
+    0x2ACB9910,
+    0x29558001,
+    0x00001014,
+    0x29A5C000,
+    0x228B64E1,
+    0xC2021381,
+    0xBC800224,
+    0x96820020,
+    0x8E822030,
+    0xC2021340,
+    0xBC8B31A4,
+    0xBC976E04,
+    0xFC000000,
+    0x20820001,
+    0xFC000000,
+    0x0A320012,
+    0xBCC75D04,
+    0x22A24015,
+    0x96A28010,
+    0x22B24004,
+    0xFC000000,
+    0x20A300A5,
+    0x86B2E010,
+    0x0200C006,
+    0xFC000000,
+    0x0008200A,
+    0xFC000000,
+    0xFC000000,
+    0x22B2400C,
+    0x2AB24004,
+    0x0E1A0BF2,
+    0x86822010,
+    0x82926080,
+    0x18008247,
+    0xFC000000,
+    0xFC000000,
+    0x22A50035,
+    0x22C50006,
+    0x22E50025,
+    0x0A329022,
+    0x20B54001,
+    0xA0D2D080,
+    0x80D2E0D0,
+    0xFC000000,
+    0x06234803,
+    0x82C32010,
+    0x86D36040,
+    0x06F29C03,
+    0xA0A29E00,
+    0x96A28030,
+    0x06F39C03,
+    0xA0B39E00,
+    0x96B2C030,
+    0x80A320A0,
+    0x8402E0A0,
+    0x0200D003,
+    0x2AA50006,
+    0x2AB50006,
+    0x8604E050,
+    0x02009003,
+    0x28D54001,
+    0x02000012,
+    0xBCA88004,
+    0xA4A4C650,
+    0xFC000000,
+    0xFC000000,
+    0x20A28002,
+    0xFC000000,
+    0xFC000000,
+    0x22AA8034,
+    0x96A28040,
+    0x82A2A010,
+    0xC2029702,
+    0x8334E010,
+    0x83452080,
+    0x83556020,
+    0x0E5CDBD8,
+    0xFC000000,
+    0xFC000000,
+    0xBD577C00,
+    0x14000000,
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+    0xC2021702,
+    0x18037B47,
+    0xFC000000,
+    0xFC000000,
+    0xA0820AE0,
+    0xA0820A00,
+    0x968200F0,
+    0xA4825E00,
+    0x020023F9,
+    0xBC900034,
+    0xD0024086,
+    0x20828000,
+    0xA4920A80,
+    0x06720830,
+    0x28028000,
+    0x82A28010,
+    0x8AA28408,
+    0x23224407,
+    0x22F247FC,
+    0x22B24784,
+    0xA5300770,
+    0x22E246D4,
+    0x22D2477C,
+    0xBD700004,
+    0xA5739180,
+    0x0E1B8016,
+    0xA522C330,
+    0x23124786,
+    0x0E0B8008,
+    0x22B2463C,
+    0x2342475C,
+    0xA0C2C230,
+    0x94C500C1,
+    0x0E0B880E,
+    0xA522C8E0,
+    0xA5230740,
+    0x22C24754,
+    0x22B24774,
+    0xA15449A0,
+    0xA1445400,
+    0xA0E444E0,
+    0xA1144500,
+    0x8163A0B2,
+    0xA5654820,
+    0xA5651460,
+    0xA5644550,
+    0xA5731100,
+    0xBCB00064,
+    0xD002C082,
+    0x10000CC7,
+    0xBCB39284,
+    0xFC000000,
+    0x0A356BD7,
+    0xBC802D14,
+    0xC2021702,
+    0xA083CA00,
+    0x96B200F0,
+    0xA4B4DE00,
+    0x020023D1,
+    0xBC800034,
+    0xD00200B6,
+    0x18038847,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+};
+char *rdpa_version_fw_c = "$Change: 239242 $";
diff --git a/arch/arm/mach-bcmbca/bcm63138/rdp_fw/runner_fw_d.c b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/runner_fw_d.c
new file mode 100755
index 0000000000..79476861eb
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/rdp_fw/runner_fw_d.c
@@ -0,0 +1,4108 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint32_t firmware_binary_D[] = {
+    0x0A300005,
+    0xFC000000,
+    0x1000001B,
+    0xFC000000,
+    0xFC000000,
+    0x221A7E42,
+    0x222A8683,
+    0x224A8703,
+    0x226A8783,
+    0x228AECA1,
+    0xC2021502,
+    0xC2001202,
+    0xC2001302,
+    0xBC801000,
+    0xBC800018,
+    0xC2021202,
+    0xC2021302,
+    0x1000064F,
+    0xBD000500,
+    0xFC000000,
+    0xBC991904,
+    0xBC81CC4C,
+    0xBC81D440,
+    0x2A824026,
+    0x18000000,
+    0xFC000000,
+    0xFC000000,
+    0x2A0AA402,
+    0x2A1AA442,
+    0x2A2AA483,
+    0x2A4AA503,
+    0x2A6AA583,
+    0x2A8AA603,
+    0x2AAAA683,
+    0x2ACAA703,
+    0x2AEAA783,
+    0x2B0AA803,
+    0x2B2AA883,
+    0x2B4AA903,
+    0x2B6AA983,
+    0x2B8AAA03,
+    0x2BAAAA83,
+    0x2BCAAB03,
+    0x2BEAAB83,
+    0xC6800042,
+    0x2A8AF202,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xC2000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x220AA402,
+    0x221AA442,
+    0x222AA483,
+    0x224AA503,
+    0x226AA583,
+    0x228AA603,
+    0x22AAA683,
+    0x22CAA703,
+    0x22EAA783,
+    0x230AA803,
+    0x232AA883,
+    0x234AA903,
+    0x236AA983,
+    0x238AAA03,
+    0x23AAAA83,
+    0x23CAAB03,
+    0x23EAAB83,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x16000001,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x229AF580,
+    0x9E924000,
+    0xFC000000,
+    0x0652400A,
+    0xBD100004,
+    0xBCBAE1E4,
+    0x21220003,
+    0xA094CD00,
+    0xA4A24A80,
+    0x28020002,
+    0x0A3481BC,
+    0x0200101A,
+    0x2A0287B4,
+    0xBC900024,
+    0xC2025702,
+    0x18001547,
+    0xFC000000,
+    0xFC000000,
+    0x21220003,
+    0xBD100004,
+    0xBCBAE1E4,
+    0xA0E32100,
+    0x07F4E15E,
+    0xA094CD00,
+    0xA4A24A80,
+    0x229AF580,
+    0x9E924000,
+    0xFC000000,
+    0x06524004,
+    0x02002008,
+    0xD0038004,
+    0xFC000000,
+    0xBC900024,
+    0xC2025702,
+    0x180019C7,
+    0xFC000000,
+    0xFC000000,
+    0x22928446,
+    0x2A02879C,
+    0xA0949C00,
+    0x2A9286E5,
+    0xBD5A9604,
+    0x22E287FC,
+    0x86E3A020,
+    0xA5538620,
+    0x23428446,
+    0xFC000000,
+    0x20E54002,
+    0xFC000000,
+    0x0A338457,
+    0x06039C13,
+    0x2352855C,
+    0x86056110,
+    0x02004810,
+    0xA1550440,
+    0x86056010,
+    0x02005807,
+    0x23628575,
+    0x8755A430,
+    0x8B556018,
+    0x02004809,
+    0x02001157,
+    0xBD7000B4,
+    0xBD502224,
+    0x8B65A018,
+    0x8405A150,
+    0x02004803,
+    0x02001151,
+    0xBD7000B4,
+    0x06139C0E,
+    0x2352855C,
+    0xA15508C0,
+    0x86056050,
+    0x0200580A,
+    0x23528544,
+    0x815560A0,
+    0xFC000000,
+    0xFC000000,
+    0x21554000,
+    0x86056820,
+    0x02004803,
+    0x02005143,
+    0xBD700054,
+    0x06650002,
+    0x07950018,
+    0x06F38C17,
+    0xBD682004,
+    0x235287FC,
+    0x87556020,
+    0xA5654660,
+    0xD745A851,
+    0xFC000000,
+    0xFC000000,
+    0xC7600742,
+    0xFC000000,
+    0x0685880D,
+    0xBC9A6004,
+    0xA4954640,
+    0xA0E59000,
+    0xFC000000,
+    0xFC000000,
+    0x209240E4,
+    0x8A026800,
+    0x0200592D,
+    0xA1724C00,
+    0x100001C7,
+    0x8293A000,
+    0xFC000000,
+    0x07138814,
+    0x06B5000E,
+    0x07450812,
+    0xFC000000,
+    0x235285CC,
+    0x8B556028,
+    0xBD8FFFF4,
+    0x237285D5,
+    0x236285E5,
+    0x0A354806,
+    0x8405E180,
+    0x02004804,
+    0x0A358803,
+    0x02001007,
+    0xA5400340,
+    0x072398F7,
+    0xBC9002E4,
+    0x100001E9,
+    0xBD7000E4,
+    0xFC000000,
+    0x07338808,
+    0x07D50002,
+    0x07E50806,
+    0x074398EF,
+    0xBC9002F4,
+    0x100001E9,
+    0xBD700124,
+    0xFC000000,
+    0x23828525,
+    0x2A02879C,
+    0x06B50109,
+    0x07050011,
+    0x06650010,
+    0xFC000000,
+    0x235AF4E0,
+    0x22EAF5B0,
+    0x06054C0C,
+    0x0A339515,
+    0x2A12879C,
+    0xBCEAAC04,
+    0x23628095,
+    0x237280A6,
+    0xD763A854,
+    0xFC000000,
+    0xFC000000,
+    0xC6E00742,
+    0xFC000000,
+    0x06838D0B,
+    0x2A02879C,
+    0x074500E9,
+    0x07E500F5,
+    0x07D500F4,
+    0xFC000000,
+    0x2352854C,
+    0x86E560E0,
+    0xA1950440,
+    0x86066010,
+    0x02006841,
+    0x236285A4,
+    0x97758041,
+    0x815620E0,
+    0x22E2855C,
+    0x84056090,
+    0x0200C0E8,
+    0x86056400,
+    0x0200C802,
+    0xA5255C00,
+    0x2B828785,
+    0x22928544,
+    0x8603A290,
+    0x02005009,
+    0xBD500024,
+    0x8603A2F0,
+    0x02005006,
+    0xBD500034,
+    0x0EEDC8ED,
+    0xFC000000,
+    0xFC000000,
+    0x020000E9,
+    0xBCCAE900,
+    0x234287FC,
+    0xA1450800,
+    0x97554040,
+    0x2A028566,
+    0x21430144,
+    0xA5550800,
+    0x8342AAC0,
+    0xD75500C2,
+    0x2B52855C,
+    0x1000021E,
+    0xBCC04740,
+    0xBD700004,
+    0x0A3528DE,
+    0x2AE2855C,
+    0x2A0A9810,
+    0xFC000000,
+    0x22E2855C,
+    0x8603A2F0,
+    0x02005123,
+    0xFC000000,
+    0x83426070,
+    0x83526060,
+    0x80E26000,
+    0x83726280,
+    0x8363A040,
+    0x20928144,
+    0x2A928534,
+    0x23428446,
+    0xBC900020,
+    0xA5424440,
+    0x21628165,
+    0x8293A000,
+    0x8365A280,
+    0x2B628785,
+    0x20928095,
+    0xA0925040,
+    0x2A92853C,
+    0x20928154,
+    0x2A92855C,
+    0x0200206D,
+    0x21528176,
+    0x2B528566,
+    0x86066020,
+    0x020058AD,
+    0xBD700294,
+    0x83862280,
+    0x80E620E0,
+    0x8403A090,
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+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
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+    0xFC000000,
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+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
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+    0xFC000000,
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+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+};
+char *rdpa_version_fw_d = "$Change: 239581 $";
diff --git a/arch/arm/mach-bcmbca/bcm63146/Kconfig b/arch/arm/mach-bcmbca/bcm63146/Kconfig
new file mode 100644
index 0000000000..09f581338d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63146/Kconfig
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM63146
+
+config TARGET_BCM963146
+	bool "Broadcom 63146 Reference Board"
+	depends on ARCH_BCMBCA
+
+config SYS_SOC
+	default "bcm63146"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+	hex "default DDR3 mcb selector value"
+	default 0x1607
+
+config BCMBCA_DDR4_DEF_MCBSEL
+	hex "default DDR4 mcb selector value"
+	default 0x101633
+endif
+
+config RSVD_USE_MAX_FROM_ENV_AND_DT 
+	bool "RSVD will use max value from env and DT"
+	default y
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm63146/Makefile b/arch/arm/mach-bcmbca/bcm63146/Makefile
new file mode 100644
index 0000000000..e7f9f65ffb
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63146/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+obj-y += mmu_table.o
+obj-y += cpu.o
diff --git a/arch/arm/mach-bcmbca/bcm63146/cpu.c b/arch/arm/mach-bcmbca/bcm63146/cpu.c
new file mode 100644
index 0000000000..10a23c3eee
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63146/cpu.c
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_DDRC)
+#include <asm/arch/ddr.h>
+#endif
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#endif
+#include "tpl_params.h"
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+
+static void enable_ts0_couner(void)
+{
+	BIUCFG->ts0_ctrl.CNTCR |= 0x1;
+}
+#elif defined(CONFIG_TPL_BUILD)
+static void cci500_enable(void)
+{
+	/*Enable access from E2 and below */
+	CCI500->secr_acc |= SECURE_ACCESS_UNSECURE_ENABLE;
+}
+
+static void enable_ns_access(void)
+{
+	BIUCFG->bac.bac_permission |= 0x33; // Linux access to BAC_CPU_THERM_TEMP
+}
+
+static void disable_memc_sram(void)
+{
+	uint32_t addr = MEMC_BASE + mc2_afx_sram_match_cfg_sram_start_addr_hi;
+	
+	writel(readl(addr)&~0x80000000, addr);
+}
+
+static void setup_ubus_rangechk(void)
+{
+	/* Fix the default of RC0 to only enable lower 2G memory for ubus master */		
+	UBUS4_RANGE_CHK_SETUP->cfg[0].base = 0x13;
+	/* setup the second range check for the top DDR region */
+	if (tplparams->ddr_size > 2048) {
+		UBUS4_RANGE_CHK_SETUP->cfg[1].control = 0x1f0;
+		UBUS4_RANGE_CHK_SETUP->cfg[1].srcpid[0] = 0xffffffff;
+		UBUS4_RANGE_CHK_SETUP->cfg[1].seclev = 0xffffffff;
+		/* enable ubus maser to access the upper 2GB */	
+		UBUS4_RANGE_CHK_SETUP->cfg[1].base = 0x13;
+		UBUS4_RANGE_CHK_SETUP->cfg[1].base_up = 0x1;
+	}
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+	printf("Chip ID: BCM%X_%X\n",chipId,revId);
+}
+#endif
+
+#if defined(CONFIG_BCMBCA_PMC)
+void boost_cpu_clock(void)
+{
+	printf("set cpu freq to 2000MHz\n");
+	set_cpu_freq(2000);
+	pll_ch_freq_set(PMB_ADDR_BIU_PLL, 1, 4000/800); // raise ACEBIU clock rate to 800 MHz
+}
+
+int set_cpu_freq(int freqMHz)
+{
+	int mdiv;
+
+	if( freqMHz > 2000 || freqMHz < 400 )
+	{
+		printf("%dMHz is not supported\n", freqMHz);
+		return -1;
+	}
+
+	/* VCO at 4GHz, mdiv = Fvco/target frequency */
+	mdiv = 4000/freqMHz;
+
+	pll_ch_freq_set(PMB_ADDR_BIU_PLL, 0, mdiv);
+
+	return 4000/mdiv;
+}
+#endif
+
+static int reset_plls(void)
+{
+	/* Force Reset eMMC PLL */
+	pll_ch_reset(PMB_ADDR_RDPPLL, 1, PLLBPCMRegOffset(ch01_cfg));
+	return 0;
+}
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	enable_ts0_couner();
+#if defined(CONFIG_BCMBCA_DDRC)
+	spl_ddrinit_prepare();
+#endif
+	/* enable unalgined access */
+	set_sctlr(get_sctlr() & ~CR_A);
+#endif
+#if defined(CONFIG_TPL_BUILD)
+	enable_ns_access();
+	disable_memc_sram();
+	setup_ubus_rangechk();	
+	cci500_enable();
+#endif
+
+    reset_plls();
+    return 0;
+}
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_EMMC)
+		return BOOT_DEVICE_MMC1;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+#if !defined(CONFIG_TPL_ATF)
+void boot_secondary_cpu(unsigned long vector)
+{
+	uint32_t cpu, nr_cpus = 2;
+	ARM_CONTROL_REG ctrl_reg;
+	uint64_t rvbar = vector;
+
+	printf("boot secondary cpu from 0x%lx\n", vector);
+
+	cpu = 1;
+	while (cpu < nr_cpus) {
+		int stat;
+
+		BIUCFG->cluster[0].rvbar_addr[cpu] = rvbar;
+		stat = PowerOnDevice(PMB_ADDR_ORION_CPU0 + cpu);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to power on secondary cpu %d - sts %d\n", cpu, stat);
+
+		stat = ReadBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), &ctrl_reg.Reg32);
+		ctrl_reg.Bits.cpu_reset_n &= ~(0x1 << cpu);
+		stat |= WriteBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), ctrl_reg.Reg32);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to boot secondary cpu %d - sts %d\n", cpu, stat);
+		cpu++;
+	}
+
+	return;
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm63146/mmu_table.c b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c
new file mode 100644
index 0000000000..81762ff9cc
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#ifdef CONFIG_SPL_XIP_SUPPORT
+#include <boot_flash.h>
+#endif
+
+static struct mm_region broadcom_bcm963146_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	/* DDR memory. Enable the maximum 4GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 2UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	{
+		.virt = 0x100000000UL,
+		.phys = 0x100000000UL,
+		.size = 2UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* MEMC control registers */
+	{
+		.virt = 0x80040000UL,
+		.phys = 0x80040000UL,
+		.size = 0x2000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+	/* DDR PHY control registers */
+	{
+		.virt = 0x80060000UL,
+		.phys = 0x80060000UL,
+		.size = 0x6000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* DPFE control registers */
+	{
+		.virt = 0x80070000UL,
+		.phys = 0x80070000UL,
+		.size = 0xc000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+	/* LMEM for bootrom runtime  */
+	{
+		.virt = CONFIG_SYS_INIT_RAM_ADDR,
+		.phys = CONFIG_SYS_INIT_RAM_ADDR,
+		.size = CONFIG_SYS_INIT_RAM_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+
+#ifdef CONFIG_SPL_XIP_SUPPORT
+	/* NOR FLASH XIP Window */
+	{
+		.virt = NOR_XIP_BASE_ADDR,
+		.phys = NOR_XIP_BASE_ADDR,
+		.size = 0x100000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#endif
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#else
+	/* DDR entries for cached memory, total size is a placehold
+	   and will be filled in at run time. MUST be first entry */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 1UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+		/* GIC */
+	{
+		.virt = 0x81001000UL,
+		.phys = 0x81001000UL,
+		.size = 0x7000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* CCI-500 */
+	{
+		.virt = 0x81100000,
+		.phys = 0x81100000,
+		.size = 0x91000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+	{
+		/* XRDP PSRAM */
+		.virt = 0x82000000UL,
+		.phys = 0x82000000UL,
+		.size = 0x30000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	},
+
+	{
+		/* XRDP Rest of block */
+		.virt = 0x82700000UL,
+		.phys = 0x82700000UL,
+		.size = 0x600000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+	{
+		/* ETH_PHY_TOP */
+		.virt = 0x837ff000UL,
+		.phys = 0x837ff000UL,
+		.size = 0x1000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+	{
+		/* PMC */
+		.virt = 0xffa00000UL,
+		.phys = 0xffa00000UL,
+		.size = 0x200000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#endif
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000UL,
+		.phys = 0xff800000UL,
+                .size = 0x100000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, 
+		/* BIUCFG */
+	{
+		.virt = 0x81060000,
+		.phys = 0x81060000,
+		.size = 0x3000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+		/* UBUS4 Coherency Port */
+	{
+		.virt = 0x810A0000,
+		.phys = 0x810A0000,
+		.size = 0x1000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm963146_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm63148/Kconfig b/arch/arm/mach-bcmbca/bcm63148/Kconfig
new file mode 100644
index 0000000000..9df47ae0e0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/Kconfig
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM63148
+
+config TARGET_BCM963148
+	bool "Broadcom 63148 Reference Board"
+	depends on ARCH_BCMBCA
+
+config SYS_SOC
+	default "bcm63148"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+	hex "default DDR3 mcb selector value"
+	default 0x421
+endif
+
+config TPL_MAX_SIZE
+	default 1048576
+
+config RSVD_USE_MAX_FROM_ENV_AND_DT 
+	bool "RSVD will use max value from env and DT"
+	default y
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm63148/Makefile b/arch/arm/mach-bcmbca/bcm63148/Makefile
new file mode 100644
index 0000000000..3d667300f4
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+obj-y += cpu.o
+obj-y += mmu_table.o
+ifndef CONFIG_TPL_BUILD
+# SPL
+obj-$(CONFIG_SPL_BUILD)	+= pmc.o
+endif
+
+ifndef CONFIG_SPL_BUILD
+# u-boot proper
+obj-$(CONFIG_BCMBCA_RDP) += rdp_fw/
+endif
diff --git a/arch/arm/mach-bcmbca/bcm63148/cpu.c b/arch/arm/mach-bcmbca/bcm63148/cpu.c
new file mode 100644
index 0000000000..e3565a31a3
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/cpu.c
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/cpu.h>
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+static void set_b15_config(void)
+{
+	uint32_t reg = 0x0;
+
+	/* set mcp0 read/write credits to 8 */
+	/* And workaround for HW63148-100: Disabling write pairing by clearing bits 28-31.*/
+	reg = B15CTRL->cpu_ctrl.credit;
+	reg &= 0x0fffff00;
+	reg |= 0x88;
+	B15CTRL->cpu_ctrl.credit = reg;
+
+	/* set RAC_config0 to 0x0 to disable it */
+	B15CTRL->cpu_ctrl.rac_cfg0 = 0x0;
+
+	return;
+}
+
+static void set_vr_gain(void)
+{
+	/* set the internal voltage regulator gain to 8. This reduces the response time and keeps
+	   voltage supply to ddr stable. */
+	PROCMON->SSBMaster.wr_data = 0x800;
+	PROCMON->SSBMaster.control = 0x3440;
+	PROCMON->SSBMaster.control = 0xb440;
+	while (PROCMON->SSBMaster.control & 0x8000) ;
+
+	PROCMON->SSBMaster.wr_data = 0x802;
+	PROCMON->SSBMaster.control = 0x3440;
+	PROCMON->SSBMaster.control = 0xb440;
+	while (PROCMON->SSBMaster.control & 0x8000) ;
+
+	PROCMON->SSBMaster.wr_data = 0x800;
+	PROCMON->SSBMaster.control = 0x3440;
+	PROCMON->SSBMaster.control = 0xb440;
+	while (PROCMON->SSBMaster.control & 0x8000) ;
+}
+
+static void set_ubus_config(void)
+{
+	/* enable UBUS multiple read/write transaction to improve performance */
+	B15CTRL->cpu_ctrl.ubus_cfg |= 0x70;
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+	printf("Chip ID: BCM%X_%X\n",chipId,revId);
+}
+#endif
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SPI_NOR) != MISC_STRAP_BUS_BOOT_SPI_NOR)
+		return BOOT_DEVICE_NAND;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+#if defined(CONFIG_BCMBCA_PMC)
+#define PLL_GET_CHANNEL_OFFSET(channel)  (PLLBPCMRegOffset(ch01_cfg) + ((channel/2)*sizeof(PLL_CHCFG_REG)>>2))
+static void set_biu_pll_post_divider(int bpcmaddr, int channel, int mdiv)
+{
+	PLL_CHCFG_REG pll_ch_cfg;
+	int offset, mdiv_rb;
+
+	if( channel < 0 || channel > 5 )
+	   return;
+
+	offset = PLL_GET_CHANNEL_OFFSET(channel);
+
+	ReadBPCMRegister(bpcmaddr, offset, &pll_ch_cfg.Reg32);
+	mdiv_rb = channel&1 ? pll_ch_cfg.Bits.mdiv1 : pll_ch_cfg.Bits.mdiv0;
+	if (mdiv_rb != mdiv) {
+		if( channel&1 )
+			pll_ch_cfg.Bits.mdiv1 = mdiv;
+		else
+			pll_ch_cfg.Bits.mdiv0 = mdiv;
+		WriteBPCMRegister(bpcmaddr, offset, pll_ch_cfg.Reg32);
+		udelay(1000);
+		if( channel&1 )
+			pll_ch_cfg.Bits.mdiv_override1 = 1;
+		else
+			pll_ch_cfg.Bits.mdiv_override0 = 1;
+		WriteBPCMRegister(bpcmaddr, offset, pll_ch_cfg.Reg32);
+		udelay(10000);
+	}
+
+	return;
+}
+
+void boost_cpu_clock(void)
+{
+	printf("set cpu freq to 1500MHz\n");
+	set_cpu_freq(1500);
+}
+
+int set_cpu_freq(int freqMHz)
+{
+	uint32_t val;
+	int mdiv0 = 2;
+
+	/* we only support the following frequency:
+	 * 1) 375, 750, and 1500
+	 * 2) 125, 250, 500, and 1000 */
+	val = B15CTRL->cpu_ctrl.clock_cfg;
+	if ((freqMHz == 375) || (freqMHz == 750) || (freqMHz == 1500)) {
+		mdiv0 = 2;
+		val &= ~0xf;
+		val |= (1500 / freqMHz) - 1;
+		if (freqMHz == 1500)
+			val &= ~0x10;
+	} else if ((freqMHz == 125) || (freqMHz == 250) || (freqMHz == 500)  || (freqMHz == 1000)) {
+		mdiv0 = 3;
+		val &= ~0xf;
+		val |= (1000 / freqMHz) - 1;
+		if (freqMHz == 1000)
+			val &= ~0x10;
+	} else if (freqMHz == 7501) {
+		/* this is a special setting of 750 MHz for hw team to try */
+		mdiv0 = 4;
+		val &= ~0xf;
+		freqMHz = 750;
+	} else {
+		printf("cpufreq %dMHz is not supported\n", freqMHz);
+		return -1;
+	}
+
+	set_biu_pll_post_divider(PMB_ADDR_B15_PLL, 0, mdiv0);
+
+	B15CTRL->cpu_ctrl.clock_cfg = val;
+
+	return freqMHz;
+}
+#endif
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	set_ubus_config();
+	set_b15_config();
+	set_vr_gain();
+#endif
+	/* enable unalgined access */
+	set_cr(get_cr() & ~CR_A);	
+	
+	return 0;
+}
+
+#if !defined(CONFIG_TPL_ATF)
+void boot_secondary_cpu(unsigned long vector)
+{
+	printf("boot secondary cpu from 0x%lx\n", vector);
+
+	*(volatile uint32_t*)(BOOTLUT_BASE+0x20) = vector;
+
+	B15CTRL->cpu_ctrl.cpu1_pwr_zone_ctrl |= 0x400;
+	B15CTRL->cpu_ctrl.reset_cfg &= 0xfffffffd;
+
+	return;
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm63148/mmu_table.c b/arch/arm/mach-bcmbca/bcm63148/mmu_table.c
new file mode 100644
index 0000000000..14b97757e5
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/mmu_table.c
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include "mmu_map_v7.h"
+
+static struct mm_region broadcom_bcm963148_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_TPL_BUILD)
+	/* SPL table */
+
+	/* DDR memory. Enable the maximum 1GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000,
+		.phys = 0x00000000,
+		.size = SZ_1G,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+	/* LMEM for SPL runtime  */
+	{
+		.virt = 0x80700000,
+		.phys = 0x80700000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_CACHED_MEM,
+	},
+#else
+	/* TPL table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	/* LMEM for SPL runtime  */
+	{
+		.virt = 0x80700000,
+		.phys = 0x80700000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_CACHED_MEM,
+	},
+#endif
+#else
+	/* u-boot table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	{
+		/* APM */
+		.virt = 0x80100000,
+		.phys = 0x80100000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* RDP */
+		.virt = 0x80200000,
+		.phys = 0x80200000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+#endif
+	{
+		/* Register space (covers MEMC, USB, etc) */
+		.virt = 0x80000000,
+		.phys = 0x80000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* PMC */
+		.virt = 0x80400000,
+		.phys = 0x80400000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* SoC peripheral */
+		.virt = 0xfff00000,
+		.phys = 0xfff00000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	}, 
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm963148_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm63148/pmc.S b/arch/arm/mach-bcmbca/bcm63148/pmc.S
new file mode 100644
index 0000000000..70bfff18f5
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/pmc.S
@@ -0,0 +1,237 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include <linux/linkage.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/misc.h>
+
+/*  *********************************************************************
+    *  pmc_send_cmd()
+    *
+    *   send pmc cmd to DQM queue and wait for response
+    *   
+    *	 
+    *  Inputs:
+    *   r0 - DQM input word0 
+    *   r1 - DQM input word1
+    *   r2 - DQM input word2
+    *   r3 - DQM input word3
+    *	
+    *  Outputs:
+    *   r0 - DQM output word0 
+    *   r1 - DQM output word1
+    *   r2 - DQM output word2
+    *   r3 - DQM output word3
+    *	
+    *  Register used:
+    *   r0, r1, r2, r3, r4
+    ********************************************************************* */
+ENTRY(pmc_send_cmd)
+
+	ldr     r4, =PMC_DQM_QUEUE_DATA_BASE
+	add     r4, #PMC_DQM_QUEUE_DATA_HOST_TO_PMC 
+	str     r0, [r4, #0x0]
+        str     r1, [r4, #0x4]       
+        str     r2, [r4, #0x8]       
+        str     r3, [r4, #0xc]     /* Write register value (the 4th word) intiates the write  */ 
+
+        ldr     r4, =PMC_DQM_BASE
+        mov     r1, #2             /* Only need the status for DQM message queue 1 PMC to Host */
+pmcw:   ldr     r2, [r4, #PMC_DQM_NOT_EMPTY_STS]
+        and     r2, r2, r1          /* get rid of everything except 2nd bit  */
+	cmp     r2, #0 
+        beq     pmcw             /* Repeat until DQM1 is ready with data  */
+	
+        ldr     r4, =PMC_DQM_QUEUE_DATA_BASE
+	add     r4, #PMC_DQM_QUEUE_DATA_PMC_TO_HOST
+        ldr     r0, [r4, #0x0]
+        ldr     r1, [r4, #0x4]
+        ldr     r2, [r4, #0x8]
+        ldr     r3, [r4, #0xc]     /* read word 3 ( read is complete ... DQM1 has been flushed) */
+
+	mov  pc, lr
+ENDPROC(pmc_send_cmd)
+
+/*  *********************************************************************
+    *  pmb_send_cmd()
+    *
+    *   register access using power mamagement bus directly
+    *   
+    *	 
+    *  Inputs:
+    *   r0 - dev address 
+    *   r1 - register offset 
+    *   r2 - register value for write, ignore for read
+    *	r3 - 0 for read, 1 for write
+    *  Outputs:
+    *   r0 - return value
+    * 	     zero - success, 1 - time out, 2 - slave error
+    *   r1 - read value 
+    *	
+    *  Register used:
+    *   r0, r1, r2, r3, r4
+    ********************************************************************* */
+ENTRY(pmb_send_cmd)
+	
+	mov     r4, #3             /* check which power management bus */
+        ands    r4, r0, LSR #8
+	ldreq   r4, =PMBM0_BASE
+        ldrne   r4, =PMBM1_BASE
+
+	and     r0, #0xff
+	orr     r1, r0, LSL #12
+	orr     r1, r3, LSL #PMB_CNTRL_CMD_SHIFT
+
+	/* make sure PMBM is not busy */
+pmbw1:
+	mov     r3, #1
+	ldr     r0, [r4, #PMB_CNTRL]
+	ands    r3, r0, LSR #PMB_CNTRL_BUSY_SHIFT
+	bne     pmbw1
+
+	/* store the data if for write */
+	mov     r3, r1, LSR #PMB_CNTRL_CMD_SHIFT
+	ands    r3, #0x1
+	beq     scmd
+        str     r2, [r4, #PMB_WR_DATA]
+scmd:	
+	/* send the cmd */
+        str     r1, [r4, #PMB_CNTRL]
+	mov     r3, #1
+	orr     r1, r3, LSL #PMB_CNTRL_START_SHIFT
+        str     r1, [r4, #PMB_CNTRL]
+
+	/* make sure the cmd is done */
+pmbw2:
+	mov     r3, #1
+	ldr     r0, [r4, #PMB_CNTRL]
+	ands    r3, r0, LSR #PMB_CNTRL_START_SHIFT
+	bne     pmbw2
+
+	/* check if any error */
+	mov     r3, #1
+	ands    r3, r0, LSR #PMB_CNTRL_TIMEOUT_ERR_SHIFT
+	movne   r0, #1
+	bne     pmb_done
+	
+	mov     r3, #1
+	ands    r3, r0, LSR #PMB_CNTRL_SLAVE_ERR_SHIFT
+	movne   r0, #2
+	bne     pmb_done
+
+	mov     r0, #0
+	mov     r3, r1, LSR #PMB_CNTRL_CMD_SHIFT
+	ands    r3, #0x1
+	bne     pmb_done
+        ldr     r1, [r4, #PMB_RD_DATA]	
+	
+pmb_done:	
+	mov  pc, lr
+	
+ENDPROC(pmb_send_cmd)
+	
+/*  *********************************************************************
+    *  pmc_write_bpcm_reg()
+    *
+    *   perform a write to a BPCM register via the PMC message handler
+    *   
+    *	 
+    *  Inputs:
+    *   r0 - dev address 
+    *   r1 - register offset 
+    *   r2 - register value to write
+    *	
+    *  Outputs:
+    *   r0 - return value, pmc error code.
+    * 	     zero - success, non zero - error
+    *	
+    *  Register used:
+    *   r0, r1, r2, r3, r4, r10
+    ********************************************************************* */
+ENTRY(pmc_write_bpcm_reg)
+	mov	r10, lr		   /* persevere link reg across call */
+
+	ldr     r4, =MISC_BASE     /* check if PMC ROM is enabled or not */
+	ldr     r4, [r4, #MISC_STRAP_BUS]   
+	lsr     r4, #MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT
+	ands    r4, #0x1
+	beq     nopmc1
+	
+        mov     r3, r2
+        and     r2, r1, #0xff      /* register addr offset within pmbs device  */
+	ldr     r4, =0x3ff
+        and     r1, r0, r4
+	lsl     r1, #10            /* DQM message word1 pmb bus index[19:18]=0, dev addr within bus[17:10] */
+	mov     r0, #0xd           /* DQM message word0 cmdId[7:0]=cmdWriteBpcmReg=0x0d */
+
+	bl      pmc_send_cmd
+	
+	lsr     r0, #8
+	and     r0, #0xff         /* return the PMC error code */
+	b       write_reg_done
+	
+nopmc1:                           /* use PMB direct access */
+        mov     r3, #1            /* 1 for write */
+	bl      pmb_send_cmd
+	
+write_reg_done:	
+	mov	lr, r10		/* restore link */
+	mov	pc, lr
+ENDPROC(pmc_write_bpcm_reg)
+
+
+/*  *********************************************************************
+    *  pmc_read_bpcm_reg()
+    *
+    *   perform a read to a BPCM register via the PMC message handler
+    *   
+    *	 
+    *  Inputs:
+    *   r0 - dev address 
+    *   r1 - register offset 
+    *	
+    *  Outputs:
+    *   r0 - return value, pmc error code.
+    * 	     zero - success, non zero - error
+    *	r1 - register value if return success
+    *	
+    *  Register used:
+    *   r0, r1, r2, r3, r4, r10
+    ********************************************************************* */
+ENTRY(pmc_read_bpcm_reg)
+
+	mov	r10, lr		   /* persevere link reg across call */
+
+	ldr     r4, =MISC_BASE     /* check if PMC ROM is enabled or not */
+	ldr     r4, [r4, #MISC_STRAP_BUS]   
+	lsr     r4, #MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT
+	ands    r4, #0x1
+	beq     nopmc2
+
+        mov     r3, #0
+        and     r2, r1, #0xff      /* register addr offset within pmbs device  */
+	ldr     r4, =0x3ff
+        and     r1, r0, r4
+	lsl     r1, #10            /* DQM message word1 pmb bus index[19:18]=0, dev addr within bus[17:10] */
+	mov     r0, #0xb           /* DQM message word0 cmdId[7:0]=cmdReadBpcmReg=0x0b */
+
+        bl      pmc_send_cmd
+	
+	lsr     r0, #8
+	and     r0, #0xff      /* return the PMC error code */
+        mov     r1, r2
+	b       read_reg_done
+	
+nopmc2:                           /* use PMB direct access */
+        mov     r3, #0            /* 0 for write */
+	bl      pmb_send_cmd
+	
+read_reg_done:	
+	mov	lr, r10		/* restore link */
+	mov	pc, lr
+
+ENDPROC(pmc_read_bpcm_reg)
+
+	
diff --git a/arch/arm/mach-bcmbca/bcm63148/rdp_fw/Makefile b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/Makefile
new file mode 100644
index 0000000000..2d63fbb27b
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+KBUILD_CPPFLAGS += --include linux/types.h
+
+obj-y +=				\
+	runner_fw_b.o			\
+	runner_fw_c.o			\
+	runner_fw_d.o			\
+	predict_runner_fw_b.o		\
+	predict_runner_fw_c.o		\
+	predict_runner_fw_d.o
+
diff --git a/arch/arm/mach-bcmbca/bcm63148/rdp_fw/predict_runner_fw_b.c b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/predict_runner_fw_b.c
new file mode 100644
index 0000000000..755acf4f39
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/predict_runner_fw_b.c
@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint16_t firmware_predict_B[] = {
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0008,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x8000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0010,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0800,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0400,
+    0x0004,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0800,
+    0x0000,
+    0x1040,
+    0x0000,
+    0x0400,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x2000,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0400,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x2000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x0040,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x2000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0080,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x8000,
+    0x0000,
+    0x0202,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x4000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0400,
+    0x0000,
+    0x0008,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0040,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x4000,
+    0x0000,
+    0x0000,
+    0x4000,
+    0x0000,
+    0x0002,
+    0x0000,
+    0x0000,
+    0x0008,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0802,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+};
diff --git a/arch/arm/mach-bcmbca/bcm63148/rdp_fw/predict_runner_fw_c.c b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/predict_runner_fw_c.c
new file mode 100644
index 0000000000..475908727c
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/predict_runner_fw_c.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint16_t firmware_predict_C[] = {
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0008,
+    0x0000,
+    0x0200,
+    0x0488,
+    0x0040,
+    0x0000,
+    0x0010,
+    0x1000,
+    0x4000,
+    0x4000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0040,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0100,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x0002,
+    0x0002,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0004,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x8000,
+    0x0080,
+    0x0000,
+    0x4004,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0080,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x8000,
+    0x0000,
+    0x0080,
+    0x0000,
+    0x0000,
+    0x0040,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0002,
+    0x0000,
+    0x0400,
+    0x0000,
+    0x0000,
+    0x8000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0800,
+    0x0000,
+    0x0100,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x0000,
+    0x2000,
+    0x0000,
+    0x0000,
+    0x0010,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0040,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x4000,
+    0x0400,
+    0x0020,
+    0x0000,
+    0x0000,
+    0x0800,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+};
diff --git a/arch/arm/mach-bcmbca/bcm63148/rdp_fw/predict_runner_fw_d.c b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/predict_runner_fw_d.c
new file mode 100644
index 0000000000..632715e686
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/predict_runner_fw_d.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint16_t firmware_predict_D[] = {
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0200,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0101,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x4000,
+    0x0000,
+    0x0800,
+    0x0001,
+    0x0000,
+    0x0000,
+    0x0020,
+    0x0000,
+    0x0200,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0800,
+    0x0200,
+    0x0400,
+    0x0000,
+    0x0004,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0010,
+    0x0000,
+    0x0000,
+    0x0001,
+    0x0010,
+    0x0008,
+    0x0004,
+    0x0200,
+    0x8004,
+    0x0100,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x2000,
+    0x0080,
+    0x0080,
+    0x0000,
+    0x0100,
+    0x0200,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x8000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x1000,
+    0x0000,
+    0x8000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0080,
+    0x0000,
+    0x0001,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+    0x0000,
+};
diff --git a/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_a_labels.h b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_a_labels.h
new file mode 100644
index 0000000000..f70dccb825
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_a_labels.h
@@ -0,0 +1,91 @@
+#ifndef RUNNER_A_CODE_ADDRESSES
+#define RUNNER_A_CODE_ADDRESSES
+
+#define runner_a_start_task_initialization_task		(0x14)
+#define runner_a_initialization_task		(0x14)
+#define runner_a_start_task_timer_scheduler_set		(0x3844)
+#define runner_a_timer_scheduler_set		(0x3844)
+#define runner_a_start_task_cpu_rx_wakeup_request		(0x2608)
+#define runner_a_cpu_rx_wakeup_request		(0x2608)
+#define runner_a_start_task_flow_cache_wakeup_request		(0xE78)
+#define runner_a_flow_cache_wakeup_request		(0xE78)
+#define runner_a_start_task_cpu_tx_wakeup_request		(0x2DB4)
+#define runner_a_cpu_tx_wakeup_request		(0x2DB4)
+#define runner_a_start_task_policer_budget_allocator_1st_wakeup_request		(0x3978)
+#define runner_a_policer_budget_allocator_1st_wakeup_request		(0x3978)
+#define runner_a_start_task_wan_direct_wakeup_request		(0x186C)
+#define runner_a_wan_direct_wakeup_request		(0x186C)
+#define runner_a_start_task_wan_cpu_wakeup_request		(0x204)
+#define runner_a_wan_cpu_wakeup_request		(0x204)
+#define runner_a_start_task_wan_normal_wakeup_request		(0x3C8)
+#define runner_a_wan_normal_wakeup_request		(0x3C8)
+#define runner_a_start_task_downstream_multicast_wakeup_request		(0x32F4)
+#define runner_a_downstream_multicast_wakeup_request		(0x32F4)
+#define runner_a_start_task_debug_routine		(0x11C)
+#define runner_a_debug_routine		(0x11C)
+#define runner_a_start_task_free_skb_index_wakeup_request		(0x3944)
+#define runner_a_free_skb_index_wakeup_request		(0x3944)
+#define runner_a_free_skb_index_tx_abs_done		(0x3944)
+#define runner_a_start_task_dhd_tx_post		(0x43C0)
+#define runner_a_dhd_tx_post		(0x43C0)
+#define runner_a_start_task_dhd_tx_complete_wakeup_request		(0x47E4)
+#define runner_a_dhd_tx_complete_wakeup_request		(0x47E4)
+#define runner_a_dhd_tx_complete_check_next		(0x47E4)
+#define runner_a_start_task_ipsec_ds_wakeup_request		(0x3C80)
+#define runner_a_ipsec_ds_wakeup_request		(0x3C80)
+#define runner_a_start_task_ethwan2_normal_wakeup_request		(0x260)
+#define runner_a_ethwan2_normal_wakeup_request		(0x260)
+#define runner_a_gpe_sop_push_replace_ddr_sram_32		(0x1A28)
+#define runner_a_gpe_sop_push_replace_sram_32_64		(0x1A9C)
+#define runner_a_gpe_sop_push_replace_sram_64		(0x1AB0)
+#define runner_a_gpe_sop_push_replace_sram_64_32		(0x1AC4)
+#define runner_a_gpe_sop_pull_replace_ddr_sram_32		(0x1AD8)
+#define runner_a_gpe_sop_pull_replace_sram_32_64		(0x1B4C)
+#define runner_a_gpe_sop_pull_replace_sram_64		(0x1B9C)
+#define runner_a_gpe_sop_pull_replace_sram_64_32		(0x1BD8)
+#define runner_a_gpe_replace_pointer_32_ddr		(0x1C28)
+#define runner_a_gpe_replace_pointer_32_sram		(0x1C4C)
+#define runner_a_gpe_replace_pointer_64_sram		(0x1C70)
+#define runner_a_gpe_replace_16		(0x1C94)
+#define runner_a_gpe_replace_32		(0x1CC8)
+#define runner_a_gpe_replace_bits_16		(0x1CEC)
+#define runner_a_gpe_copy_add_16_cl		(0x1D18)
+#define runner_a_gpe_copy_add_16_sram		(0x1D24)
+#define runner_a_gpe_copy_bits_16_cl		(0x1D6C)
+#define runner_a_gpe_copy_bits_16_sram		(0x1D78)
+#define runner_a_gpe_insert_16		(0x1DC0)
+#define runner_a_gpe_delete_16		(0x1E28)
+#define runner_a_gpe_decrement_8		(0x1E68)
+#define runner_a_gpe_apply_icsum_16		(0x1E8C)
+#define runner_a_gpe_apply_icsum_nz_16		(0x1EB0)
+#define runner_a_gpe_compute_csum_16_cl		(0x1EEC)
+#define runner_a_gpe_compute_csum_16_sram		(0x1EF8)
+#define runner_a_gpe_buffer_copy_16_sram		(0x1F38)
+#define runner_a_gpe_buffer_copy_16_ddr		(0x1F60)
+#define runner_a_ingress_classification_key_src_ip		(0x2168)
+#define runner_a_ingress_classification_key_dst_ip		(0x21AC)
+#define runner_a_ingress_classification_key_ipv6_flow_label		(0x21F0)
+#define runner_a_ingress_classification_key_generic_rule_1		(0x2214)
+#define runner_a_ingress_classification_key_generic_rule_2		(0x221C)
+#define runner_a_ingress_classification_key_outer_tpid		(0x2288)
+#define runner_a_ingress_classification_key_inner_tpid		(0x2294)
+#define runner_a_ingress_classification_key_src_port		(0x22B0)
+#define runner_a_ingress_classification_key_dst_port		(0x22D0)
+#define runner_a_ingress_classification_key_outer_vlan		(0x22F0)
+#define runner_a_ingress_classification_key_inner_vlan		(0x2308)
+#define runner_a_ingress_classification_key_dst_mac		(0x2324)
+#define runner_a_ingress_classification_key_src_mac		(0x232C)
+#define runner_a_ingress_classification_key_ether_type		(0x2354)
+#define runner_a_ingress_classification_key_ip_protocol		(0x2368)
+#define runner_a_ingress_classification_key_dscp		(0x238C)
+#define runner_a_ingress_classification_key_ssid		(0x23A8)
+#define runner_a_ingress_classification_key_ingress_port		(0x23AC)
+#define runner_a_ingress_classification_key_outer_pbits		(0x23BC)
+#define runner_a_ingress_classification_key_inner_pbits		(0x23D4)
+#define runner_a_ingress_classification_key_number_of_vlans		(0x23F0)
+#define runner_a_ingress_classification_key_layer3_protocol		(0x2400)
+#define runner_a_cpu_rx_meter_budget_allocate		(0x38C4)
+#define runner_a_dhd_tx_post_close_aggregation		(0x3910)
+#define runner_a_schedule_free_skb_index		(0x3928)
+
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_b_labels.h b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_b_labels.h
new file mode 100644
index 0000000000..e94578f36a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_b_labels.h
@@ -0,0 +1,56 @@
+#ifndef RUNNER_B_CODE_ADDRESSES
+#define RUNNER_B_CODE_ADDRESSES
+
+#define runner_b_start_task_initialization_task		(0x14)
+#define runner_b_initialization_task		(0x14)
+#define runner_b_start_task_timer_scheduler_set		(0x2E60)
+#define runner_b_timer_scheduler_set		(0x2E60)
+#define runner_b_start_task_cpu_rx_wakeup_request		(0x1548)
+#define runner_b_cpu_rx_wakeup_request		(0x1548)
+#define runner_b_start_task_cpu_tx_wakeup_request		(0x267C)
+#define runner_b_cpu_tx_wakeup_request		(0x267C)
+#define runner_b_start_task_policer_budget_allocator_1st_wakeup_request		(0x330C)
+#define runner_b_policer_budget_allocator_1st_wakeup_request		(0x330C)
+#define runner_b_start_task_rate_control_budget_allocator_1st_wakeup_request		(0x255C)
+#define runner_b_rate_control_budget_allocator_1st_wakeup_request		(0x255C)
+#define runner_b_start_task_wan_interworking_enqueue_wakeup_request		(0x208)
+#define runner_b_wan_interworking_enqueue_wakeup_request		(0x208)
+#define runner_b_start_task_wan_tx_wakeup_request		(0x6EC)
+#define runner_b_wan_tx_wakeup_request		(0x6EC)
+#define runner_b_start_task_debug_routine		(0x120)
+#define runner_b_debug_routine		(0x120)
+#define runner_b_start_task_timer_7_1st_wakeup_request		(0x30B0)
+#define runner_b_timer_7_1st_wakeup_request		(0x30B0)
+#define runner_b_start_task_free_skb_index_wakeup_request		(0x2FF4)
+#define runner_b_free_skb_index_wakeup_request		(0x2FF4)
+#define runner_b_start_task_dhd_tx_post		(0x3468)
+#define runner_b_dhd_tx_post		(0x3468)
+#define runner_b_ingress_classification_key_src_ip		(0x1080)
+#define runner_b_ingress_classification_key_dst_ip		(0x10C4)
+#define runner_b_ingress_classification_key_ipv6_flow_label		(0x1108)
+#define runner_b_ingress_classification_key_generic_rule_1		(0x112C)
+#define runner_b_ingress_classification_key_generic_rule_2		(0x1134)
+#define runner_b_ingress_classification_key_outer_tpid		(0x11A0)
+#define runner_b_ingress_classification_key_inner_tpid		(0x11AC)
+#define runner_b_ingress_classification_key_src_port		(0x11C8)
+#define runner_b_ingress_classification_key_dst_port		(0x11E8)
+#define runner_b_ingress_classification_key_outer_vlan		(0x1208)
+#define runner_b_ingress_classification_key_inner_vlan		(0x1220)
+#define runner_b_ingress_classification_key_dst_mac		(0x123C)
+#define runner_b_ingress_classification_key_src_mac		(0x1244)
+#define runner_b_ingress_classification_key_ether_type		(0x126C)
+#define runner_b_ingress_classification_key_ip_protocol		(0x1280)
+#define runner_b_ingress_classification_key_dscp		(0x12A4)
+#define runner_b_ingress_classification_key_ssid		(0x12C0)
+#define runner_b_ingress_classification_key_ingress_port		(0x12D8)
+#define runner_b_ingress_classification_key_outer_pbits		(0x12E8)
+#define runner_b_ingress_classification_key_inner_pbits		(0x1300)
+#define runner_b_ingress_classification_key_number_of_vlans		(0x131C)
+#define runner_b_ingress_classification_key_layer3_protocol		(0x132C)
+#define runner_b_spdsvc_timer_wakeup_request		(0x2DCC)
+#define runner_b_cpu_rx_meter_budget_allocate		(0x2EE0)
+#define runner_b_upstream_rate_limiter_budget_allocate		(0x2F2C)
+#define runner_b_schedule_free_skb_index		(0x2FD8)
+#define runner_b_pps_rate_limiter_timer_wakeup_request		(0x3114)
+
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_c_labels.h b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_c_labels.h
new file mode 100644
index 0000000000..ceaf03ddbd
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_c_labels.h
@@ -0,0 +1,40 @@
+#ifndef RUNNER_C_CODE_ADDRESSES
+#define RUNNER_C_CODE_ADDRESSES
+
+#define runner_c_start_task_initialization_task		(0x14)
+#define runner_c_initialization_task		(0x14)
+#define runner_c_start_task_timer_scheduler_set		(0x790)
+#define runner_c_timer_scheduler_set		(0x790)
+#define runner_c_start_task_lan_tx_wakeup_request		(0x430)
+#define runner_c_lan_tx_wakeup_request		(0x430)
+#define runner_c_start_task_cpu_tx_wakeup_request		(0xAB0)
+#define runner_c_cpu_tx_wakeup_request		(0xAB0)
+#define runner_c_start_task_lan_enqueue_ih_wakeup_request		(0x1C4)
+#define runner_c_lan_enqueue_ih_wakeup_request		(0x1C4)
+#define runner_c_start_task_lan_enqueue_pd_wakeup_request		(0x208)
+#define runner_c_lan_enqueue_pd_wakeup_request		(0x208)
+#define runner_c_start_task_multicast_lan_enqueue_wakeup_request		(0x258)
+#define runner_c_multicast_lan_enqueue_wakeup_request		(0x258)
+#define runner_c_start_task_wlan_mcast_wakeup_request		(0x2DC0)
+#define runner_c_wlan_mcast_wakeup_request		(0x2DC0)
+#define runner_c_start_task_cpu_rx_int_coalesce_timer_1st_wakeup_request		(0x9F8)
+#define runner_c_cpu_rx_int_coalesce_timer_1st_wakeup_request		(0x9F8)
+#define runner_c_start_task_debug_routine		(0xDC)
+#define runner_c_debug_routine		(0xDC)
+#define runner_c_start_task_gso_wakeup_request		(0x1CA0)
+#define runner_c_gso_wakeup_request		(0x1CA0)
+#define runner_c_start_task_timer_7_1st_wakeup_request		(0x964)
+#define runner_c_timer_7_1st_wakeup_request		(0x964)
+#define runner_c_start_task_free_skb_index_wakeup_request		(0x900)
+#define runner_c_free_skb_index_wakeup_request		(0x900)
+#define runner_c_start_task_service_queue_dequeue_wakeup_request		(0x36F8)
+#define runner_c_service_queue_dequeue_wakeup_request		(0x36F8)
+#define runner_c_start_task_service_queue_enqueue_wakeup_request		(0x37C8)
+#define runner_c_service_queue_enqueue_wakeup_request		(0x37C8)
+#define runner_c_ds_rate_limiter_budget_allocate		(0x810)
+#define runner_c_ds_service_queue_rate_limiter_budget_allocate		(0x8CC)
+#define runner_c_schedule_free_skb_index		(0x8E4)
+#define runner_c_pps_rate_limiter_timer_wakeup_request		(0x9C8)
+#define runner_c_spdsvc_timer_wakeup_request		(0xF88)
+
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_d_labels.h b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_d_labels.h
new file mode 100644
index 0000000000..b3f65f26ef
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/rdd_runner_d_labels.h
@@ -0,0 +1,54 @@
+#ifndef RUNNER_D_CODE_ADDRESSES
+#define RUNNER_D_CODE_ADDRESSES
+
+#define runner_d_start_task_initialization_task		(0x14)
+#define runner_d_initialization_task		(0x14)
+#define runner_d_start_task_timer_scheduler_set		(0x1BE0)
+#define runner_d_timer_scheduler_set		(0x1BE0)
+#define runner_d_start_task_flow_cache_wakeup_request		(0xD84)
+#define runner_d_flow_cache_wakeup_request		(0xD84)
+#define runner_d_start_task_lan_dispatch_wakeup_request		(0x19C0)
+#define runner_d_lan_dispatch_wakeup_request		(0x19C0)
+#define runner_d_start_task_lan_cpu_wakeup_request		(0x154)
+#define runner_d_lan_cpu_wakeup_request		(0x154)
+#define runner_d_start_task_lan_normal_wakeup_request		(0x19C)
+#define runner_d_lan_normal_wakeup_request		(0x19C)
+#define runner_d_start_task_debug_routine		(0x6C)
+#define runner_d_debug_routine		(0x6C)
+#define runner_d_start_task_free_skb_index_wakeup_request		(0x1D5C)
+#define runner_d_free_skb_index_wakeup_request		(0x1D5C)
+#define runner_d_free_skb_index_tx_abs_done		(0x1D5C)
+#define runner_d_start_task_dhd_rx_complete_wakeup_request		(0x1EC4)
+#define runner_d_dhd_rx_complete_wakeup_request		(0x1EC4)
+#define runner_d_gpe_sop_push_replace_ddr_sram_32		(0x1374)
+#define runner_d_gpe_sop_push_replace_sram_32_64		(0x13E8)
+#define runner_d_gpe_sop_push_replace_sram_64		(0x13FC)
+#define runner_d_gpe_sop_push_replace_sram_64_32		(0x1410)
+#define runner_d_gpe_sop_pull_replace_ddr_sram_32		(0x1424)
+#define runner_d_gpe_sop_pull_replace_sram_32_64		(0x1498)
+#define runner_d_gpe_sop_pull_replace_sram_64		(0x14E8)
+#define runner_d_gpe_sop_pull_replace_sram_64_32		(0x1524)
+#define runner_d_gpe_replace_pointer_32_ddr		(0x1574)
+#define runner_d_gpe_replace_pointer_32_sram		(0x1598)
+#define runner_d_gpe_replace_pointer_64_sram		(0x15BC)
+#define runner_d_gpe_replace_16		(0x15E0)
+#define runner_d_gpe_replace_32		(0x1614)
+#define runner_d_gpe_replace_bits_16		(0x1638)
+#define runner_d_gpe_copy_add_16_cl		(0x1664)
+#define runner_d_gpe_copy_add_16_sram		(0x1670)
+#define runner_d_gpe_copy_bits_16_cl		(0x16B8)
+#define runner_d_gpe_copy_bits_16_sram		(0x16C4)
+#define runner_d_gpe_insert_16		(0x170C)
+#define runner_d_gpe_delete_16		(0x1774)
+#define runner_d_gpe_decrement_8		(0x17B4)
+#define runner_d_gpe_apply_icsum_16		(0x17D8)
+#define runner_d_gpe_apply_icsum_nz_16		(0x17FC)
+#define runner_d_gpe_compute_csum_16_cl		(0x1838)
+#define runner_d_gpe_compute_csum_16_sram		(0x1844)
+#define runner_d_gpe_buffer_copy_16_sram		(0x1884)
+#define runner_d_gpe_buffer_copy_16_ddr		(0x18AC)
+#define runner_d_upstream_ingress_rate_limiter_budget_allocate		(0x1C60)
+#define runner_d_upstream_quasi_budget_allocate		(0x1CE0)
+#define runner_d_schedule_free_skb_index		(0x1D40)
+
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm63148/rdp_fw/runner_fw_b.c b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/runner_fw_b.c
new file mode 100644
index 0000000000..a47cdb898f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/runner_fw_b.c
@@ -0,0 +1,7180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint32_t firmware_binary_B[] = {
+    0x0A300005,
+    0xFC000000,
+    0x10000048,
+    0xFC000000,
+    0xFC000000,
+    0x221A7E42,
+    0x222A7E83,
+    0x224A7F03,
+    0x226A7F83,
+    0xC2001202,
+    0xC2001302,
+    0xBC801000,
+    0xBC800018,
+    0xC2021202,
+    0xC2021302,
+    0xBC8000F4,
+    0x969200E0,
+    0xBC800034,
+    0xD0020092,
+    0x228AECA1,
+    0xC2021502,
+    0xBC9A9F84,
+    0xBC800064,
+    0xBC8003C8,
+    0x2A124026,
+    0xCE920080,
+    0xBC992C04,
+    0xBC810808,
+    0xBC810C40,
+    0x2A824006,
+    0xBC811088,
+    0xBC8112C0,
+    0x2A824026,
+    0xBC811348,
+    0xBC800000,
+    0x2A824046,
+    0xBC800000,
+    0xBC811A00,
+    0x2A824066,
+    0xBC811AC8,
+    0xBC811C80,
+    0x2A824086,
+    0xBC811E88,
+    0xBC812080,
+    0x2A8240A6,
+    0xBC812208,
+    0xBC8123C0,
+    0x2A8240C6,
+    0xBC812448,
+    0xBC8126C0,
+    0x2A8240E6,
+    0xBC812808,
+    0xBC812A40,
+    0x2A824106,
+    0xBC812C08,
+    0xBC812D80,
+    0x2A824126,
+    0xBC812E88,
+    0xBC813000,
+    0x2A824146,
+    0xBC8131C8,
+    0xBC8132C0,
+    0x2A824166,
+    0xBC991904,
+    0xBC82EE0C,
+    0xBC82F2C0,
+    0x2A824006,
+    0xBC82FD84,
+    0x2A824055,
+    0x18000000,
+    0xFC000000,
+    0xFC000000,
+    0x2A0AA402,
+    0x2A1AA442,
+    0x2A2AA483,
+    0x2A4AA503,
+    0x2A6AA583,
+    0x2A8AA603,
+    0x2AAAA683,
+    0x2ACAA703,
+    0x2AEAA783,
+    0x2B0AA803,
+    0x2B2AA883,
+    0x2B4AA903,
+    0x2B6AA983,
+    0x2B8AAA03,
+    0x2BAAAA83,
+    0x2BCAAB03,
+    0x2BEAAB83,
+    0xC6800042,
+    0x2A8AF202,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xC2000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x220AA402,
+    0x221AA442,
+    0x222AA483,
+    0x224AA503,
+    0x226AA583,
+    0x228AA603,
+    0x22AAA683,
+    0x22CAA703,
+    0x22EAA783,
+    0x230AA803,
+    0x232AA883,
+    0x234AA903,
+    0x236AA983,
+    0x238AAA03,
+    0x23AAAA83,
+    0x23CAAB03,
+    0x23EAAB83,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x16000001,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x248A4000,
+    0xA4A20A80,
+    0x06720886,
+    0x2C0A4000,
+    0x22828784,
+    0x23A2876C,
+    0xBCB8C004,
+    0xA4B69020,
+    0x82924012,
+    0x8A92440A,
+    0x22C2875C,
+    0xA0E30650,
+    0xA4C00650,
+    0x2122C002,
+    0xA0D48D00,
+    0x86036080,
+    0x02008805,
+    0xBCFA0004,
+    0x02002008,
+    0xAAB36580,
+    0x80B3E0B0,
+    0xBCB83004,
+    0x96D34050,
+    0x80B2E0D0,
+    0x86032030,
+    0x0200C0E4,
+    0x96C30010,
+    0x82C32180,
+    0xFC000000,
+    0xA0F38650,
+    0x2182C0C5,
+    0xA5262100,
+    0x8312AEC0,
+    0x22C28407,
+    0xA5200700,
+    0xA5800600,
+    0x20B44000,
+    0x22EAE421,
+    0x0A32E057,
+    0x96B3C010,
+    0x82F2E1C0,
+    0x22B287FC,
+    0xA0B2CA00,
+    0x256600F5,
+    0x26F600A5,
+    0xA1431C00,
+    0x0A33AC5D,
+    0x2735803C,
+    0xBD100004,
+    0x8AE6A0F0,
+    0xFC000000,
+    0x0EFB8C05,
+    0xBCE07C04,
+    0x840520E0,
+    0x0200D0D2,
+    0x23428754,
+    0x0634E4ED,
+    0x27258025,
+    0x27458045,
+    0x84052120,
+    0x0200C8A5,
+    0x2A028784,
+    0x228AE1C1,
+    0xFC000000,
+    0x0F22100A,
+    0xA1331C00,
+    0xA0828A80,
+    0x22EAE1A1,
+    0xFC000000,
+    0x0A1390C3,
+    0x23428754,
+    0x02002009,
+    0x86E3A010,
+    0x2AEAE1A1,
+    0x22EAE181,
+    0xFC000000,
+    0x0A1390BC,
+    0x23428754,
+    0x86E3A010,
+    0x2AEAE181,
+    0xCB45E01E,
+    0xFC000000,
+    0xC945F13E,
+    0x0659E042,
+    0xBCE00064,
+    0xD0038082,
+    0xA140A000,
+    0x22208035,
+    0x8284A010,
+    0x2E858025,
+    0x26E58006,
+    0x2283C0A6,
+    0x80822130,
+    0x2A83C0A6,
+    0xC9A3813E,
+    0xA4C2C8E0,
+    0xA4D003B0,
+    0xA4D69170,
+    0x0A23A008,
+    0x28C50003,
+    0xCBA2801E,
+    0x20838002,
+    0x80822142,
+    0x02002005,
+    0x28838002,
+    0xA4E52000,
+    0xA4E52000,
+    0xA4E52100,
+    0x0A345CC2,
+    0x2EE58006,
+    0x26858075,
+    0x26B600B5,
+    0x26C60086,
+    0x8C82E080,
+    0x2E8600B5,
+    0x2283C026,
+    0x22B3C09C,
+    0x8C8220C0,
+    0x2A83C026,
+    0x0402C809,
+    0x8A82E018,
+    0x2A83C09C,
+    0x00002009,
+    0x2283C015,
+    0xD0020006,
+    0xBCB00024,
+    0xC202D702,
+    0x18004147,
+    0xFC000000,
+    0xFC000000,
+    0x20B44000,
+    0xFC000000,
+    0x0A32C3F9,
+    0x020023A4,
+    0xFC000000,
+    0xFC000000,
+    0x18002087,
+    0xFC000000,
+    0xFC000000,
+    0x06C49FA6,
+    0x23228446,
+    0xA1248440,
+    0x0A3487A3,
+    0x840520E0,
+    0x02008FA1,
+    0x82E52030,
+    0x0200239F,
+    0x8B43A038,
+    0xA4C51C00,
+    0x07F3501F,
+    0x237AF341,
+    0x80E32000,
+    0x81536000,
+    0x2545C002,
+    0xFC000000,
+    0x0A350816,
+    0xBD400014,
+    0xA1935C00,
+    0xA59506E0,
+    0x06F35803,
+    0xBD400034,
+    0xBD400074,
+    0xD0050194,
+    0xA4E2CAE0,
+    0x234AE5C0,
+    0xA4E50930,
+    0xA4E01370,
+    0x8F43A803,
+    0xA5501170,
+    0x2D45C003,
+    0x82E5C080,
+    0x8AE38019,
+    0x2AEAF341,
+    0xBD400294,
+    0x14000000,
+    0xBCE00024,
+    0xD0038140,
+    0x14000000,
+    0xFC000000,
+    0xFC000000,
+    0x10000C81,
+    0xBD004E80,
+    0xFC000000,
+    0x10000C65,
+    0xBD004F40,
+    0xFC000000,
+    0x0A3643F7,
+    0xBC8A3004,
+    0xA0E28E60,
+    0x96B2C0E1,
+    0xA4D69170,
+    0x20E200E6,
+    0xBD0051C0,
+    0x10000C9D,
+    0xA1431C00,
+    0xBDA88004,
+    0xBC8FFFFC,
+    0x42EA0017,
+    0xFC000000,
+    0xFC000000,
+    0x237AF341,
+    0xA1A35170,
+    0xFC000000,
+    0x2485C002,
+    0xFC000000,
+    0x0A32080F,
+    0x80E32000,
+    0x81536000,
+    0x228AECA1,
+    0x82822120,
+    0x96820011,
+    0xA5520F00,
+    0x10080126,
+    0xFC000000,
+    0xFC000000,
+    0xBD005780,
+    0x10000C97,
+    0xFC000000,
+    0xFC000000,
+    0x0200037B,
+    0x10000C7B,
+    0xBD005880,
+    0xFC000000,
+    0x020013F8,
+    0xFC000000,
+    0x26E58055,
+    0xFC000000,
+    0x0A338018,
+    0x0A321806,
+    0x22838015,
+    0x8404A080,
+    0x02008814,
+    0x02001009,
+    0x22838046,
+    0x23438025,
+    0x8404A140,
+    0x02009351,
+    0x22838035,
+    0x8404A080,
+    0x0200980C,
+    0x22838066,
+    0x8534A140,
+    0xC6E020C1,
+    0x07F20005,
+    0xA8822130,
+    0x8403A080,
+    0x0200C347,
+    0x02000004,
+    0xA884E080,
+    0x8403A080,
+    0x0200C343,
+    0x0200100D,
+    0x23428754,
+    0x22C28407,
+    0x23428754,
+    0x2282C015,
+    0x8A8223F0,
+    0x86022200,
+    0x02005803,
+    0x82C52150,
+    0x82C52140,
+    0x02002011,
+    0x228287FC,
+    0xA0B20A00,
+    0x2283C015,
+    0x8A8223F0,
+    0x86022200,
+    0x02006007,
+    0x26858034,
+    0xA0C31C00,
+    0xCA80C01C,
+    0x02002007,
+    0xC88080CE,
+    0x82C52140,
+    0xCA81101C,
+    0xFC000000,
+    0xC88100CE,
+    0x82C52150,
+    0xA0828A80,
+    0xBCE00064,
+    0xD0038082,
+    0x86052010,
+    0x02009005,
+    0xCBA4801C,
+    0x02002004,
+    0xCA05201C,
+    0xFC000000,
+    0xCAC5E01C,
+    0x10080C51,
+    0xFC000000,
+    0xFC000000,
+    0x00001009,
+    0xFC000000,
+    0x231287A4,
+    0xA0E4C600,
+    0xBD38B004,
+    0xA5338270,
+    0xAAE46020,
+    0x82E3A100,
+    0x02002310,
+    0x8115A000,
+    0x2164C0E5,
+    0x26844025,
+    0x82822010,
+    0x2E844025,
+    0x26B580A5,
+    0x26C58066,
+    0x81646000,
+    0x2282C006,
+    0x02002339,
+    0x8C8220C0,
+    0x2A82C006,
+    0x0A221004,
+    0x80C02086,
+    0x22ABCB82,
+    0x80C2A086,
+    0xBCAA0004,
+    0xFC000000,
+    0xAAB32580,
+    0x8152A0B0,
+    0x86032080,
+    0x0200A00A,
+    0x22A5400C,
+    0x236540C5,
+    0xBCB83004,
+    0x96A30050,
+    0x8152E0A0,
+    0xFC000000,
+    0xFC000000,
+    0x22A5400C,
+    0x236540C5,
+    0x0A32987A,
+    0x28020002,
+    0x22F54004,
+    0x26D580B5,
+    0x9F434000,
+    0xBD0077C0,
+    0x065501A6,
+    0x97450010,
+    0x834521C0,
+    0xFC000000,
+    0xFC000000,
+    0x24C58145,
+    0x22E540A6,
+    0xFC000000,
+    0x26A3003C,
+    0xFC000000,
+    0x06328175,
+    0xBD007940,
+    0x27E30006,
+    0xFC000000,
+    0x0A33E98E,
+    0x20AF8003,
+    0xA1D29C00,
+    0xA172D170,
+    0xA4B01170,
+    0x84E3A1D0,
+    0x2AE540A6,
+    0x07F2D199,
+    0xBD007B40,
+    0xA0E28320,
+    0xA4B38770,
+    0xBCE8C004,
+    0xA4E5D020,
+    0xA4A00320,
+    0x22F54015,
+    0x8AF3E3F0,
+    0x8603E200,
+    0x02005005,
+    0x26F30034,
+    0xCAF0401E,
+    0x02001005,
+    0xC8F001DE,
+    0xCAF0F01E,
+    0xFC000000,
+    0xC8F0E1DE,
+    0x26F30025,
+    0x0A232406,
+    0x8723E010,
+    0x2F230025,
+    0x26FB0025,
+    0x8723E010,
+    0x2F2B0025,
+    0xA0F29B30,
+    0x96F3C030,
+    0x0A33E006,
+    0x20E38002,
+    0xA4A39B30,
+    0x0200200F,
+    0x2EF30005,
+    0xFC000000,
+    0xBD008580,
+    0xBD4083C0,
+    0x0A232D59,
+    0x27330075,
+    0x2E030006,
+    0x88C36138,
+    0x2EC580B5,
+    0x0A331805,
+    0x22C5409C,
+    0xA4C04200,
+    0x2AC5409C,
+    0x8EB2E403,
+    0x07F2800D,
+    0x8AD5E070,
+    0xA0C387A0,
+    0x0E7B4811,
+    0x96C30002,
+    0x8AC32070,
+    0x86032070,
+    0x02004006,
+    0x86032010,
+    0x02004004,
+    0x86032040,
+    0x02005809,
+    0xFC000000,
+    0x22E54015,
+    0x86A2A040,
+    0x86076400,
+    0x02009012,
+    0xFC000000,
+    0x02001004,
+    0xFC000000,
+    0x22E54015,
+    0x86A2A040,
+    0x22CA9842,
+    0xBCDAB584,
+    0xCED30080,
+    0x1000023B,
+    0x22CAE1C1,
+    0xBD008C80,
+    0x22BA9842,
+    0xBCAA9F84,
+    0xCEA2C080,
+    0x18006EC7,
+    0x802001E6,
+    0xFC000000,
+    0x020023F4,
+    0xBCC003C4,
+    0xA4A31C00,
+    0x0F231007,
+    0xD00380A3,
+    0x280F8002,
+    0x22AAE1A1,
+    0x02002006,
+    0x82A28010,
+    0x2AAAE1A1,
+    0x22AAE181,
+    0x82A28010,
+    0x2AAAE181,
+    0x00002010,
+    0x2A2F8026,
+    0xFC000000,
+    0x22E54026,
+    0x23754046,
+    0x88A3A170,
+    0x0A32806B,
+    0xFC000000,
+    0x9EA28002,
+    0x96A28010,
+    0x82A2A180,
+    0xFC000000,
+    0xFC000000,
+    0x216540A5,
+    0x22F54004,
+    0xBD009840,
+    0x26D580B5,
+    0x9F434000,
+    0x97450010,
+    0x834521C0,
+    0xFC000000,
+    0xFC000000,
+    0x24C58145,
+    0x231540A6,
+    0xFC000000,
+    0x26A3003C,
+    0xFC000000,
+    0x063280F3,
+    0xBD0099C0,
+    0x27E30006,
+    0xFC000000,
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+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+};
+char *rdpa_version_fw_b = "$Change: 255249 $";
diff --git a/arch/arm/mach-bcmbca/bcm63148/rdp_fw/runner_fw_c.c b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/runner_fw_c.c
new file mode 100644
index 0000000000..574f938d6e
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/runner_fw_c.c
@@ -0,0 +1,4108 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint32_t firmware_binary_C[] = {
+    0x0A300005,
+    0xFC000000,
+    0x10000037,
+    0xFC000000,
+    0xFC000000,
+    0x221ABE42,
+    0x222AEC83,
+    0x224AED03,
+    0x226AED83,
+    0xC2001202,
+    0xC2001302,
+    0xBC801000,
+    0xBC800018,
+    0xC2021202,
+    0xC2021302,
+    0x228B9561,
+    0xC2021502,
+    0xC6801B82,
+    0x8A8221F9,
+    0x8E822801,
+    0xC2021B82,
+    0xC6801F42,
+    0x82802030,
+    0x8E822400,
+    0x8E822800,
+    0xC2021F42,
+    0xBC8B5000,
+    0xBC900014,
+    0x2A92024C,
+    0xBC9B6080,
+    0xFC000000,
+    0xBC8B9404,
+    0x2A824005,
+    0xBC8B9684,
+    0x2A824015,
+    0xBC8B6684,
+    0x2A824025,
+    0xBC828184,
+    0x2A824035,
+    0xBC9B6F80,
+    0xFC000000,
+    0xBC8B9204,
+    0x2A824005,
+    0xBC8B9704,
+    0x2A824015,
+    0xBC80BA84,
+    0x2A824035,
+    0xBC975D04,
+    0xBC808104,
+    0x2A824045,
+    0xBC808CC4,
+    0x2A824075,
+    0x18000000,
+    0xFC000000,
+    0xFC000000,
+    0x2A0B3202,
+    0x2A1B3242,
+    0x2A2B3283,
+    0x2A4B3303,
+    0x2A6B3383,
+    0x2A8B3403,
+    0x2AAB3483,
+    0x2ACB3503,
+    0x2AEB3583,
+    0x2B0B3603,
+    0x2B2B3683,
+    0x2B4B3703,
+    0x2B6B3783,
+    0x2B8B3803,
+    0x2BAB3883,
+    0x2BCB3903,
+    0x2BEB3983,
+    0xC6800042,
+    0x2A8B27C2,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xC2000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x220B3202,
+    0x221B3242,
+    0x222B3283,
+    0x224B3303,
+    0x226B3383,
+    0x228B3403,
+    0x22AB3483,
+    0x22CB3503,
+    0x22EB3583,
+    0x230B3603,
+    0x232B3683,
+    0x234B3703,
+    0x236B3783,
+    0x238B3803,
+    0x23AB3883,
+    0x23CB3903,
+    0x23EB3983,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x16000001,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x20BA4000,
+    0xA4A2CC80,
+    0x0672C868,
+    0x280A4000,
+    0x82924012,
+    0x8A92440A,
+    0x2312863C,
+    0x22C2875C,
+    0x228287FC,
+    0xA0F20800,
+    0x23428407,
+    0xA543CAE0,
+    0x23228784,
+    0xA5500770,
+    0x02002021,
+    0xBC800064,
+    0xD00200B2,
+    0x25424003,
+    0xFC000000,
+    0x07F5080A,
+    0x2C024002,
+    0x82924080,
+    0x8A924019,
+    0xA5500770,
+    0xA1150B30,
+    0xA0C50780,
+    0x02002015,
+    0xA0F50AE0,
+    0xA12503B0,
+    0x21428003,
+    0xBC802D14,
+    0x07F5084B,
+    0xC2021702,
+    0x28028002,
+    0x020023F5,
+    0x82A28080,
+    0x8AA28029,
+    0x21424003,
+    0xFC000000,
+    0x07F50843,
+    0x28024002,
+    0x82924080,
+    0x8A924808,
+    0xA1150B30,
+    0xA0C50780,
+    0xA0F50AE0,
+    0xA12503B0,
+    0xBC888004,
+    0xA4844650,
+    0xA4830620,
+    0x22EB3181,
+    0x22BB3101,
+    0x20820002,
+    0xFC000000,
+    0xFC000000,
+    0x23320025,
+    0x22D20045,
+    0x8404E0D0,
+    0x02008833,
+    0x0F33900C,
+    0x22DB7FD0,
+    0x22EA0044,
+    0x22CB3161,
+    0x8CE360E0,
+    0x0A132047,
+    0x86D32010,
+    0x22C2C035,
+    0x2AEB7FD0,
+    0x0200200B,
+    0x2ACB3101,
+    0x2ADB3161,
+    0x22CB3141,
+    0x8CE360E0,
+    0x0A13203E,
+    0x86C32010,
+    0x22D2C035,
+    0x2ADB3101,
+    0x2ACB3141,
+    0x2AEB7FD0,
+    0x22C20006,
+    0x82D4E010,
+    0x2AD20025,
+    0x0A232008,
+    0xA543E4E0,
+    0x2942C003,
+    0x20E30002,
+    0x80E3A0B2,
+    0x02002005,
+    0x28E30002,
+    0xA4C2E000,
+    0xA4C2E000,
+    0xA4C2E100,
+    0x2AC20006,
+    0x22C20074,
+    0x22BA004C,
+    0x8CB2E0C0,
+    0x2ABA004C,
+    0x06709C04,
+    0x22B75A42,
+    0x82B2E010,
+    0x2AB75A42,
+    0x228A0034,
+    0x96820040,
+    0x00002010,
+    0x82822010,
+    0xC2021702,
+    0x18000005,
+    0xFC000000,
+    0xFC000000,
+    0x23620055,
+    0xFC000000,
+    0x0A358018,
+    0x0A349806,
+    0x22C58015,
+    0x8404E0C0,
+    0x02008814,
+    0x02001009,
+    0x22C58046,
+    0x22D58025,
+    0x8404E0D0,
+    0x020093C3,
+    0x22C58035,
+    0x8404E0C0,
+    0x0200980C,
+    0x22C58066,
+    0x8524E0D0,
+    0xC6D020C1,
+    0x07F30005,
+    0xA8C32120,
+    0x840360C0,
+    0x0200C3B9,
+    0x02000004,
+    0xA8C4A0C0,
+    0x840360C0,
+    0x0200C3B5,
+    0x2282007C,
+    0xCA80C01C,
+    0x07F5680D,
+    0xA0B51C00,
+    0xC88080BE,
+    0x06709C0A,
+    0x22875A02,
+    0x82822010,
+    0x2A875A02,
+    0x228758C2,
+    0x22B75902,
+    0x86822010,
+    0x2A8758C2,
+    0x8002E080,
+    0x02004804,
+    0x100806B2,
+    0xFC000000,
+    0xCB15201C,
+    0x00001010,
+    0xFC000000,
+    0x23FB7FD0,
+    0xBD300064,
+    0x0A37C068,
+    0x0A34C065,
+    0xFC000000,
+    0x9C87C080,
+    0xBC9AB804,
+    0xA4920630,
+    0x82822010,
+    0xA0820600,
+    0x21E24002,
+    0x22B24026,
+    0xFC000000,
+    0x232F804C,
+    0x9E948000,
+    0xA4B24720,
+    0x0652505D,
+    0x22DF8055,
+    0x92A26070,
+    0x20CAC002,
+    0x94A040A0,
+    0xC4D000D0,
+    0x23130005,
+    0x880360A0,
+    0x02006806,
+    0x22DF802C,
+    0x20E44003,
+    0x94904090,
+    0x020013F2,
+    0x8924A098,
+    0xA1D3C5C0,
+    0x96974020,
+    0x829260C0,
+    0x82A26030,
+    0xFC000000,
+    0x212F8095,
+    0x209F80A4,
+    0xFC000000,
+    0x22A48007,
+    0xA0A29180,
+    0xA0B2D180,
+    0x84A2E0A0,
+    0xA0A28C00,
+    0x86A2A080,
+    0x02008841,
+    0x82B2E010,
+    0xA0A39C00,
+    0x8602A440,
+    0x02008803,
+    0xBCA00444,
+    0xA4E29C00,
+    0x0E7B583C,
+    0xA0B2CC00,
+    0x2AB48024,
+    0xA0A39B30,
+    0x96D28030,
+    0xA4E01B30,
+    0xA4F007C0,
+    0x22A3007C,
+    0xCAA0401E,
+    0xA0B39C00,
+    0xC8A000BE,
+    0x96A28031,
+    0x82A2A080,
+    0xCAA5201E,
+    0x22B30025,
+    0x0A336008,
+    0x232AEE03,
+    0x2B244007,
+    0x2AD30005,
+    0x22A30025,
+    0x02002009,
+    0x86B2A010,
+    0x2AB30025,
+    0x22A30074,
+    0x2A030006,
+    0x2A030025,
+    0x22CF804C,
+    0x88A320A8,
+    0x2AAF804C,
+    0x22AB3181,
+    0x22CB3121,
+    0x0EB29007,
+    0x2B130035,
+    0x2B1B3121,
+    0x22AB3161,
+    0x02002006,
+    0x82A2A010,
+    0x2AAB3161,
+    0x22AB3141,
+    0x82A2A010,
+    0x2AAB3141,
+    0x07F3E025,
+    0x86A3A040,
+    0x8EB3E403,
+    0x22CF804C,
+    0xFC000000,
+    0x0A332BA1,
+    0xD00240A3,
+    0xBD300064,
+    0x229F8044,
+    0x0200239D,
+    0x89F7E098,
+    0x2BFB7FD0,
+    0xBC900024,
+    0xC2025702,
+    0x18004307,
+    0xFC000000,
+    0xFC000000,
+    0x02001395,
+    0x8734E010,
+    0xBCB93004,
+    0xA4B34630,
+    0xA0A39C00,
+    0xFC000000,
+    0x22D2C006,
+    0x84036000,
+    0x0200C804,
+    0x020023C0,
+    0x84A360A0,
+    0x2AA2C006,
+    0x229F8066,
+    0x22AF8044,
+    0xFC000000,
+    0x22BA4024,
+    0x86B2E010,
+    0x020023EF,
+    0xA0B2CC00,
+    0x2ABA4024,
+    0x82C76010,
+    0xBCDB2C04,
+    0xA4D30630,
+    0x87932010,
+    0xBD7B7F84,
+    0xA5764600,
+    0x02002024,
+    0xBD406584,
+    0x21A5C000,
+    0x0A368806,
+    0xBCC00024,
+    0xC2031702,
+    0x18006347,
+    0xFC000000,
+    0xFC000000,
+    0x26C76742,
+    0xA0F2DC00,
+    0x96D3C020,
+    0x80C320D0,
+    0xBD1B2404,
+    0xA5164620,
+    0xBD2B7F84,
+    0xA5264600,
+    0xBCEABD04,
+    0xA4E64610,
+    0x43130047,
+    0xFC000000,
+    0xFC000000,
+    0x20D44002,
+    0xFC000000,
+    0x0A3343FB,
+    0xA5042100,
+    0x20C48000,
+    0x21138001,
+    0x86C32010,
+    0x28C48000,
+    0xA4B37C00,
+    0x28F44001,
+    0x82C46020,
+    0x020023B7,
+    0xA5130A00,
+    0x29138001,
+    0xBCCB2C04,
+    0xFC000000,
+    0x20D34000,
+    0x20E30194,
+    0x84E360E0,
+    0x8B83A3F0,
+    0x02006025,
+    0x28D30194,
+    0x29A5C000,
+    0xBD6B3B04,
+    0xA5664610,
+    0xBCDB3E04,
+    0x22CB9910,
+    0x21558001,
+    0xFC000000,
+    0x87862010,
+    0x20E54001,
+    0x83A6A010,
+    0x22F758C2,
+    0x231758A1,
+    0x0A33C40B,
+    0x840460E0,
+    0x02004809,
+    0x86F3E010,
+    0x2AF758C2,
+    0x23175A82,
+    0x83146010,
+    0x2B175A82,
+    0x23175902,
+    0x800460F0,
+    0x02004804,
+    0x8EE3A801,
+    0x28E340C5,
+    0x82C32020,
+    0x82E56020,
+    0xA5538A00,
+    0x06430804,
+    0x1000068A,
+    0xBCE077C4,
+    0x2723F342,
+    0x0A362BE7,
+    0x2ACB9910,
+    0x29558001,
+    0x00001014,
+    0x29A5C000,
+    0x228B64E1,
+    0xC2021381,
+    0xBC800224,
+    0x96820020,
+    0x8E822030,
+    0xC2021340,
+    0xBC8B31A4,
+    0xBC976E04,
+    0xFC000000,
+    0x20820001,
+    0xFC000000,
+    0x0A320012,
+    0xBCC75D04,
+    0x22A24015,
+    0x96A28010,
+    0x22B24004,
+    0xFC000000,
+    0x20A300A5,
+    0x86B2E010,
+    0x0200C006,
+    0xFC000000,
+    0x0008200A,
+    0xFC000000,
+    0xFC000000,
+    0x22B2400C,
+    0x2AB24004,
+    0x0E1A0BF2,
+    0x86822010,
+    0x82926080,
+    0x18007A87,
+    0xFC000000,
+    0xFC000000,
+    0x22A50035,
+    0x22C50006,
+    0x22E50025,
+    0x0A329022,
+    0x20B54001,
+    0xA0D2D080,
+    0x80D2E0D0,
+    0xFC000000,
+    0x06234803,
+    0x82C32010,
+    0x86D36040,
+    0x06F29C03,
+    0xA0A29E00,
+    0x96A28030,
+    0x06F39C03,
+    0xA0B39E00,
+    0x96B2C030,
+    0x80A320A0,
+    0x8402E0A0,
+    0x0200D003,
+    0x2AA50006,
+    0x2AB50006,
+    0x8604E050,
+    0x02009003,
+    0x28D54001,
+    0x02000012,
+    0xBCA88004,
+    0xA4A4C650,
+    0xFC000000,
+    0xFC000000,
+    0x20A28002,
+    0xFC000000,
+    0xFC000000,
+    0x22AA8034,
+    0x96A28040,
+    0x82A2A010,
+    0xC2029702,
+    0x8334E010,
+    0x83452080,
+    0x83556020,
+    0x0E5CDBD8,
+    0xFC000000,
+    0xFC000000,
+    0xBD577C00,
+    0x14000000,
+    0xBD300004,
+    0xBD493000,
+    0x10000D88,
+    0xBCF08D84,
+    0xFC000000,
+    0x14000000,
+    0xFC000000,
+    0xFC000000,
+    0xBCA01D14,
+    0xC2029702,
+    0xBCA02814,
+    0xC2029702,
+    0x14000000,
+    0xFC000000,
+    0xFC000000,
+    0x82826010,
+    0xBCDB2C04,
+    0xA4D20630,
+    0x87922010,
+    0xBD7B7F84,
+    0xA5764600,
+    0xFC000000,
+    0xFC000000,
+    0x21A5C000,
+    0x100001B7,
+    0xBD409304,
+    0xFC000000,
+    0xBCDB3E04,
+    0xBC8B9914,
+    0x22CB9910,
+    0xFC000000,
+    0x0A330006,
+    0xFC000000,
+    0x1000068A,
+    0xBCE09544,
+    0x2723F342,
+    0x28C20000,
+    0x18009007,
+    0xFC000000,
+    0xFC000000,
+    0x2A075802,
+    0x26876F41,
+    0xC20213E1,
+    0xBC800264,
+    0x96820020,
+    0x8E822030,
+    0xC2021370,
+    0xBC864A84,
+    0x2A8B9741,
+    0x2A0B98E0,
+    0xFC000000,
+    0xFC000000,
+    0x228B9741,
+    0xFC000000,
+    0xFC000000,
+    0x20A20001,
+    0x82822020,
+    0x0A329005,
+    0x2A8B9741,
+    0x0000200A,
+    0xFC000000,
+    0xFC000000,
+    0x18009807,
+    0xFC000000,
+    0xFC000000,
+    0x228779A1,
+    0x22B77981,
+    0x22A779E1,
+    0x0A32C406,
+    0x808220B0,
+    0x840220A0,
+    0x0200C802,
+    0x808020A0,
+    0x2A8779A1,
+    0x10000265,
+    0xFC000000,
+    0xFC000000,
+    0x26976F61,
+    0xC20253C1,
+    0xBC800274,
+    0x96820020,
+    0x8E822030,
+    0xC2021350,
+    0xBC800054,
+    0xC2021110,
+    0xC6801110,
+    0xFC000000,
+    0x06020006,
+    0xFC000000,
+    0xFC000000,
+    0x1800A386,
+    0xFC000000,
+    0xFC000000,
+    0x26C76FE1,
+    0xBCF70C04,
+    0x0A331018,
+    0x80D020C0,
+    0x9EE34001,
+    0xFC000000,
+    0x0653A014,
+    0x94A040E0,
+    0xA4F38820,
+    0xFC000000,
+    0x88D360A8,
+    0x2483C002,
+    0xA1121460,
+    0xA0B21560,
+    0x80B2E090,
+    0xA482D560,
+    0x2C83C002,
+    0x8402E110,
+    0x0200A3F2,
+    0x96838020,
+    0x82822020,
+    0x88C320A8,
+    0xCA86001E,
+    0x020023ED,
+    0xC2029601,
+    0x2EC76FE1,
+    0xBC800024,
+    0x1800A107,
+    0xC2021110,
+    0xFC000000,
+    0x21424003,
+    0x8A052803,
+    0x0200404A,
+    0xFC000000,
+    0xFC000000,
+    0x228B9920,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x0A320007,
+    0xFC000000,
+    0xBC800024,
+    0xC2021702,
+    0x1800AC47,
+    0xFC000000,
+    0xFC000000,
+    0x2A1B9920,
+    0xA13507C0,
+    0x8604E070,
+    0x02004082,
+    0x8604E040,
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+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+};
+char *rdpa_version_fw_c = "$Change: 241757 $";
diff --git a/arch/arm/mach-bcmbca/bcm63148/rdp_fw/runner_fw_d.c b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/runner_fw_d.c
new file mode 100644
index 0000000000..ee34e766ae
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/rdp_fw/runner_fw_d.c
@@ -0,0 +1,4108 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+
+uint32_t firmware_binary_D[] = {
+    0x0A300005,
+    0xFC000000,
+    0x1000001B,
+    0xFC000000,
+    0xFC000000,
+    0x221A7E42,
+    0x222A8683,
+    0x224A8703,
+    0x226A8783,
+    0x228AECA1,
+    0xC2021502,
+    0xC2001202,
+    0xC2001302,
+    0xBC801000,
+    0xBC800018,
+    0xC2021202,
+    0xC2021302,
+    0x10000636,
+    0xBD000500,
+    0xFC000000,
+    0xBC991904,
+    0xBC81C60C,
+    0xBC81CE00,
+    0x2A824026,
+    0x18000000,
+    0xFC000000,
+    0xFC000000,
+    0x2A0AA402,
+    0x2A1AA442,
+    0x2A2AA483,
+    0x2A4AA503,
+    0x2A6AA583,
+    0x2A8AA603,
+    0x2AAAA683,
+    0x2ACAA703,
+    0x2AEAA783,
+    0x2B0AA803,
+    0x2B2AA883,
+    0x2B4AA903,
+    0x2B6AA983,
+    0x2B8AAA03,
+    0x2BAAAA83,
+    0x2BCAAB03,
+    0x2BEAAB83,
+    0xC6800042,
+    0x2A8AF202,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xC2000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x220AA402,
+    0x221AA442,
+    0x222AA483,
+    0x224AA503,
+    0x226AA583,
+    0x228AA603,
+    0x22AAA683,
+    0x22CAA703,
+    0x22EAA783,
+    0x230AA803,
+    0x232AA883,
+    0x234AA903,
+    0x236AA983,
+    0x238AAA03,
+    0x23AAAA83,
+    0x23CAAB03,
+    0x23EAAB83,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x16000001,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0x229AF580,
+    0x9E924000,
+    0xFC000000,
+    0x0652400A,
+    0xBD100004,
+    0xBCBAE1E4,
+    0x21220003,
+    0xA094CD00,
+    0xA4A24A80,
+    0x28020002,
+    0x0A3481BC,
+    0x0200101A,
+    0x2A0287B4,
+    0xBC900024,
+    0xC2025702,
+    0x18001547,
+    0xFC000000,
+    0xFC000000,
+    0x21220003,
+    0xBD100004,
+    0xBCBAE1E4,
+    0xA0E32100,
+    0x07F4E15E,
+    0xA094CD00,
+    0xA4A24A80,
+    0x229AF580,
+    0x9E924000,
+    0xFC000000,
+    0x06524004,
+    0x02002008,
+    0xD0038004,
+    0xFC000000,
+    0xBC900024,
+    0xC2025702,
+    0x180019C7,
+    0xFC000000,
+    0xFC000000,
+    0x22928446,
+    0x2A02879C,
+    0xA0949C00,
+    0x2A9286E5,
+    0xBD5A9604,
+    0x22E287FC,
+    0x86E3A020,
+    0xA5538620,
+    0x23428446,
+    0xFC000000,
+    0x20E54002,
+    0xFC000000,
+    0x0A338457,
+    0x06039C13,
+    0x2352855C,
+    0x86056110,
+    0x02004810,
+    0xA1550440,
+    0x86056010,
+    0x02005807,
+    0x23628575,
+    0x8755A430,
+    0x8B556018,
+    0x02004809,
+    0x02001157,
+    0xBD7000B4,
+    0xBD502224,
+    0x8B65A018,
+    0x8405A150,
+    0x02004803,
+    0x02001151,
+    0xBD7000B4,
+    0x06139C0E,
+    0x2352855C,
+    0xA15508C0,
+    0x86056050,
+    0x0200580A,
+    0x23528544,
+    0x815560A0,
+    0xFC000000,
+    0xFC000000,
+    0x21554000,
+    0x86056820,
+    0x02004803,
+    0x02005143,
+    0xBD700054,
+    0x06650002,
+    0x07950018,
+    0x06F38C17,
+    0xBD682004,
+    0x235287FC,
+    0x87556020,
+    0xA5654660,
+    0xD745A851,
+    0xFC000000,
+    0xFC000000,
+    0xC7600742,
+    0xFC000000,
+    0x0685880D,
+    0xBC9A6004,
+    0xA4954640,
+    0xA0E59000,
+    0xFC000000,
+    0xFC000000,
+    0x209240E4,
+    0x8A026800,
+    0x0200592D,
+    0xA1724C00,
+    0x100001C7,
+    0x8293A000,
+    0xFC000000,
+    0x07138814,
+    0x06B5000E,
+    0x07450812,
+    0xFC000000,
+    0x235285CC,
+    0x8B556028,
+    0xBD8FFFF4,
+    0x237285D5,
+    0x236285E5,
+    0x0A354806,
+    0x8405E180,
+    0x02004804,
+    0x0A358803,
+    0x02001007,
+    0xA5400340,
+    0x072398F7,
+    0xBC9002E4,
+    0x100001E9,
+    0xBD7000E4,
+    0xFC000000,
+    0x07338808,
+    0x07D50002,
+    0x07E50806,
+    0x074398EF,
+    0xBC9002F4,
+    0x100001E9,
+    0xBD700124,
+    0xFC000000,
+    0x23828525,
+    0x2A02879C,
+    0x06B50109,
+    0x07050011,
+    0x06650010,
+    0xFC000000,
+    0x235AF4E0,
+    0x22EAF5B0,
+    0x06054C0C,
+    0x0A339515,
+    0x2A12879C,
+    0xBCEAAC04,
+    0x23628095,
+    0x237280A6,
+    0xD763A854,
+    0xFC000000,
+    0xFC000000,
+    0xC6E00742,
+    0xFC000000,
+    0x06838D0B,
+    0x2A02879C,
+    0x074500E9,
+    0x07E500F5,
+    0x07D500F4,
+    0xFC000000,
+    0x2352854C,
+    0x86E560E0,
+    0xA1950440,
+    0x86066010,
+    0x02006841,
+    0x236285A4,
+    0x97758041,
+    0x815620E0,
+    0x22E2855C,
+    0x84056090,
+    0x0200C0E8,
+    0x86056400,
+    0x0200C802,
+    0xA5255C00,
+    0x2B828785,
+    0x22928544,
+    0x8603A290,
+    0x02005009,
+    0xBD500024,
+    0x8603A2F0,
+    0x02005006,
+    0xBD500034,
+    0x0EEDC8ED,
+    0xFC000000,
+    0xFC000000,
+    0x020000E9,
+    0xBCCAE900,
+    0x234287FC,
+    0xA1450800,
+    0x97554040,
+    0x2A028566,
+    0x21430144,
+    0xA5550800,
+    0x8342AAC0,
+    0xD75500C2,
+    0x2B52855C,
+    0x1000021E,
+    0xBCC04740,
+    0xBD700004,
+    0x0A3528DE,
+    0x2AE2855C,
+    0x2A0A9810,
+    0xFC000000,
+    0x22E2855C,
+    0x8603A2F0,
+    0x02005123,
+    0xFC000000,
+    0x83426070,
+    0x83526060,
+    0x80E26000,
+    0x83726280,
+    0x8363A040,
+    0x20928144,
+    0x2A928534,
+    0x23428446,
+    0xBC900020,
+    0xA5424440,
+    0x21628165,
+    0x8293A000,
+    0x8365A280,
+    0x2B628785,
+    0x20928095,
+    0xA0925040,
+    0x2A92853C,
+    0x20928154,
+    0x2A92855C,
+    0x0200206D,
+    0x21528176,
+    0x2B528566,
+    0x86066020,
+    0x020058AD,
+    0xBD700294,
+    0x83862280,
+    0x80E620E0,
+    0x8403A090,
+    0x0200C0A7,
+    0x8603A400,
+    0x0200C802,
+    0xA5239C00,
+    0x22E2855C,
+    0x22928544,
+    0x8603A040,
+    0x0200500A,
+    0xBD700044,
+    0x8603A2F0,
+    0x02005007,
+    0xBD700034,
+    0x2B828785,
+    0x8605AFF0,
+    0x020048AA,
+    0xFC000000,
+    0x020000A7,
+    0x814560A0,
+    0x83452080,
+    0x81502008,
+    0xD7550102,
+    0x2A028566,
+    0xFC000000,
+    0xC7600642,
+    0x2B628586,
+    0x83450100,
+    0xD7550102,
+    0x23428554,
+    0x8F452010,
+    0x2B428554,
+    0xC7500642,
+    0x234287FC,
+    0xA1450800,
+    0xBCCAE900,
+    0x9765C040,
+    0x2B5285A6,
+    0x21430144,
+    0xA5650800,
+    0x8342AAC0,
+    0xD76500C2,
+    0x2B62855C,
+    0x1000021E,
+    0xBCC05B40,
+    0xBD700004,
+    0x0A35288E,
+    0x2AE2855C,
+    0x2A0A9810,
+    0x22E2855C,
+    0x8603A2F0,
+    0x020050D4,
+    0xFC000000,
+    0x83426080,
+    0x22E28554,
+    0x8AE3A018,
+    0x2AE28554,
+    0x20E28144,
+    0x2AE28534,
+    0x83526090,
+    0x80E26000,
+    0x83726140,
+    0x8383A020,
+    0x8293A010,
+    0x23428446,
+    0xBCC00010,
+    0xA5430440,
+    0x20928094,
+    0x2A92853C,
+    0x8363A0C0,
+    0x20928154,
+    0x2A92855C,
+    0x21528185,
+    0x2B528785,
+    0x8355A020,
+    0x21828165,
+    0x8365A040,
+    0x2B828585,
+    0x21528155,
+    0x2B528595,
+    0x8385A020,
+    0x21928165,
+    0x8355A040,
+    0x2B9285A5,
+    0x21628185,
+    0x2B6285B5,
+    0x83656020,
+    0x21828155,
+    0x83556040,
+    0x2B828565,
+    0x21528165,
+    0x2B528575,
+    0x8363A060,
+    0x215280E4,
+    0x86056450,
+    0x0200584A,
+    0xFC000000,
+    0x21628165,
+    0xBD53FFF4,
+    0x8805A150,
+    0x02005845,
+    0xFC000000,
+    0x2B428446,
+    0x2AE2854C,
+    0x82E5E0D0,
+    0x86026060,
+    0x02006806,
+    0xFC000000,
+    0x20E280E4,
+    0x8A03A070,
+    0x0200404E,
+    0x0200003A,
+    0x86026110,
+    0x0200404B,
+    0x86026720,
+    0x02005049,
+    0x860263D0,
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+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+    0xFC000000,
+};
+char *rdpa_version_fw_d = "$Change: 255901 $";
diff --git a/arch/arm/mach-bcmbca/bcm63158/Kconfig b/arch/arm/mach-bcmbca/bcm63158/Kconfig
new file mode 100644
index 0000000000..1829394420
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63158/Kconfig
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM63158
+
+config TARGET_BCM963158
+	bool "Broadcom 63158 Reference Board"
+	depends on ARCH_BCMBCA
+
+config SYS_SOC
+	default "bcm63158"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+	hex "default DDR3 mcb selector value"
+	default 0x523
+
+config BCMBCA_DDR4_DEF_MCBSEL
+	hex "default DDR4 mcb selector value"
+	default 0x141727
+endif
+
+config RSVD_USE_MAX_FROM_ENV_AND_DT 
+	bool "RSVD will use max value from env and DT"
+	default y
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm63158/Makefile b/arch/arm/mach-bcmbca/bcm63158/Makefile
new file mode 100644
index 0000000000..e7f9f65ffb
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63158/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+obj-y += mmu_table.o
+obj-y += cpu.o
diff --git a/arch/arm/mach-bcmbca/bcm63158/cpu.c b/arch/arm/mach-bcmbca/bcm63158/cpu.c
new file mode 100644
index 0000000000..2d7c8e429a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63158/cpu.c
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/sections.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/cpu.h>
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#endif
+#if defined(CONFIG_BCMBCA_DDRC)
+#include "spl_ddrinit.h"
+#endif
+#include "bcmbca-dtsetup.h"
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+
+static void enable_ts0_counter(void)
+{
+	BIUCFG->TSO_CNTCR |= 1;
+}
+
+#elif defined(CONFIG_TPL_BUILD)
+static void cci500_enable(void)
+{
+	/*Enable access from E2 and below */
+	CCI500->secr_acc |= SECURE_ACCESS_UNSECURE_ENABLE;
+}
+
+static void enable_ns_access(void)
+{
+	BIUCFG->bac.bac_permission |= 0x33;	// Linux access to BAC_CPU_THERM_TEMP
+}
+
+static void setup_ubus_rangechk(void)
+{
+	/* Fix the default of RC0 to only enable lower 2G memory for ubus master */		
+	UBUS4_RANGE_CHK_SETUP->cfg[0].base = 0x13;
+	/* setup the second range check for the top DDR region */
+	if (tplparams->ddr_size > 2048) {
+		UBUS4_RANGE_CHK_SETUP->cfg[1].control = 0x1f0;
+		UBUS4_RANGE_CHK_SETUP->cfg[1].srcpid[0] = 0xffffffff;
+		UBUS4_RANGE_CHK_SETUP->cfg[1].seclev = 0xffffffff;
+		/* enable ubus maser to access the upper 2GB */	
+		UBUS4_RANGE_CHK_SETUP->cfg[1].base = 0x13;
+		UBUS4_RANGE_CHK_SETUP->cfg[1].base_up = 0x1;
+	}
+}
+
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+	printf("Chip ID: BCM%X_%X\n",chipId,revId);
+}
+#endif
+
+#if defined(CONFIG_BCMBCA_PMC)
+static void wait_biu_pll_lock(int bpcmaddr)
+{
+	PLL_STAT_REG stat_reg;
+
+	do {
+		ReadBPCMRegister(bpcmaddr, PLLBPCMRegOffset(stat),
+				 &stat_reg.Reg32);
+	} while (stat_reg.Bits.lock == 0);
+
+	return;
+}
+
+#define PLL_GET_CHANNEL_OFFSET(channel)  (PLLBPCMRegOffset(ch01_cfg) + ((channel/2)*sizeof(PLL_CHCFG_REG)>>2))
+void set_biu_pll_post_divider(int bpcmaddr, int channel, int mdiv)
+{
+	PLL_CHCFG_REG pll_ch_cfg;
+	int offset, mdiv_rb;
+
+	if (channel < 0 || channel > 5)
+		return;
+
+	offset = PLL_GET_CHANNEL_OFFSET(channel);
+
+	ReadBPCMRegister(bpcmaddr, offset, &pll_ch_cfg.Reg32);
+	mdiv_rb = channel & 1 ? pll_ch_cfg.Bits.mdiv1 : pll_ch_cfg.Bits.mdiv0;
+	if (mdiv_rb != mdiv) {
+		if (channel & 1)
+			pll_ch_cfg.Bits.mdiv1 = mdiv;
+		else
+			pll_ch_cfg.Bits.mdiv0 = mdiv;
+		WriteBPCMRegister(bpcmaddr, offset, pll_ch_cfg.Reg32);
+		udelay(1000);
+		if (channel & 1)
+			pll_ch_cfg.Bits.mdiv_override1 = 1;
+		else
+			pll_ch_cfg.Bits.mdiv_override0 = 1;
+		WriteBPCMRegister(bpcmaddr, offset, pll_ch_cfg.Reg32);
+		udelay(10000);
+	}
+
+	return;
+}
+
+#if defined(CONFIG_TPL_BUILD)
+#define CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV (17)
+static void disable_xtal_clk(void)
+{
+	uint32_t data;
+	int ret;
+
+	ret = ReadBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+		CLKRSTBPCMRegOffset(xtal_control), &data);
+
+	data |= (0x1 << CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV);
+
+	ret |= WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+		CLKRSTBPCMRegOffset(xtal_control), data);
+
+	if (ret)
+		printf("Failed to disable xtal clk\n");
+}
+#endif
+
+void boost_cpu_clock(void)
+{
+	printf("set cpu freq to 1675MHz\n");
+	set_cpu_freq(1675);
+
+	disable_xtal_clk();
+}
+
+int set_cpu_freq(int freqMHz)
+{
+	PLL_CTRL_REG ctrl_reg;
+	PLL_NDIV_REG ndiv_reg;
+	PLL_PDIV_REG pdiv_reg;
+	int mdiv = 2;
+	int ndiv;
+
+	/* cpufreq = Fvco/mdiv = ndiv*50MHz/mdiv */
+	/* For clock below the nominal frequency, we use post divider mdiv = 2  
+	   cpufreq = ndiv*50MHz/2 where ndiv = 22..67 for 550MHz, 425MHz.. 1675
+	   For overclock, we use post divider mdiv=1 in order to keep vco frequency low
+	   cpufreq = ndiv*50MHz/1 where ndiv = 34 .. 44  for 1700MHz, 1750MHz.. 2200MHz */
+
+	if (freqMHz < 550 || freqMHz > 1675) {
+		printf("%dMHz is not supported\n", freqMHz);
+		return -1;
+	}
+
+	if (freqMHz > 1675)
+		mdiv = 1;
+	ndiv = (mdiv * freqMHz) / 50;
+
+	/* round freqMHz to the factor of 50/25MHz */
+	freqMHz = (50 * ndiv) / mdiv;
+
+	/* switch to bypass clock for cpu clock change first */
+	ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets),
+			 &ctrl_reg.Reg32);
+	ctrl_reg.Bits.byp_wait = 1;
+	WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets),
+			  ctrl_reg.Reg32);
+
+	/* assert pll reset */
+	ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets),
+			 &ctrl_reg.Reg32);
+	ctrl_reg.Bits.master_reset = 1;
+	WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets),
+			  ctrl_reg.Reg32);
+
+	/* change vco pll frequency */
+	ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(pdiv),
+			 &pdiv_reg.Reg32);
+	pdiv_reg.Bits.ndiv_pdiv_override = 1;
+	WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(pdiv),
+			  pdiv_reg.Reg32);
+
+	ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(ndiv),
+			 &ndiv_reg.Reg32);
+	ndiv_reg.Bits.ndiv_int = ndiv;
+	WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(ndiv),
+			  ndiv_reg.Reg32);
+
+	/* de-assert pll reset */
+	ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets),
+			 &ctrl_reg.Reg32);
+	ctrl_reg.Bits.master_reset = 0;
+	WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets),
+			  ctrl_reg.Reg32);
+
+	/* wait for pll to lock */
+	wait_biu_pll_lock(PMB_ADDR_BIU_PLL);
+
+	/* set the post divider */
+	set_biu_pll_post_divider(PMB_ADDR_BIU_PLL, 0, mdiv);
+
+	/* switch back to VCO PLL clock */
+	ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets),
+			 &ctrl_reg.Reg32);
+	ctrl_reg.Bits.byp_wait = 0;
+	WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets),
+			  ctrl_reg.Reg32);
+
+	return freqMHz;
+}
+#endif
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	enable_ts0_counter();
+#if defined(CONFIG_BCMBCA_DDRC)
+	spl_ddrinit_prepare();
+	/* enable unalgined access */
+	set_sctlr(get_sctlr() & ~CR_A);
+#endif
+#endif
+#if defined(CONFIG_TPL_BUILD)
+	enable_ns_access();
+	setup_ubus_rangechk();	
+	cci500_enable();
+#endif
+	return 0;
+}
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_EMMC)
+		return BOOT_DEVICE_MMC1;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+int get_nr_cpus()
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	int nr_cpus=QUAD_CPUS;
+
+	if(chipId == DUAL_CORE_63152)
+		nr_cpus=DUAL_CPUS;
+
+	return nr_cpus;
+}
+
+#if !defined(CONFIG_TPL_ATF)
+void boot_secondary_cpu(unsigned long vector)
+{
+	uint32_t cpu, nr_cpus = QUAD_CPUS;
+	ARM_CONTROL_REG ctrl_reg;
+	uint64_t rvbar = vector;
+
+	nr_cpus = get_nr_cpus();
+
+	printf("boot secondary cpu from 0x%lx\n", vector);
+
+	cpu = 1;
+	while (cpu < nr_cpus) {
+		int stat;
+
+		BIUCFG->cluster[0].rvbar_addr[cpu] = rvbar;
+		stat = PowerOnDevice(PMB_ADDR_ORION_CPU0 + cpu);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to power on secondary cpu %d - sts %d\n", cpu, stat);
+
+		stat = ReadBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), &ctrl_reg.Reg32);
+		ctrl_reg.Bits.cpu_reset_n &= ~(0x1 << cpu);
+		stat |= WriteBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), ctrl_reg.Reg32);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to boot secondary cpu %d - sts %d\n", cpu, stat);
+		cpu++;
+	}
+
+	return;
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm63158/mmu_table.c b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c
new file mode 100644
index 0000000000..aa54718de2
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region broadcom_bcm963158_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	/* DDR memory. Enable the maximum 4GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 2UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	{
+		.virt = 0x100000000UL,
+		.phys = 0x100000000UL,
+		.size = 2UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* MEMC and DDRY PHY control registers */
+	{
+		.virt = 0x80180000UL,
+		.phys = 0x80180000UL,
+		.size = 0x40000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* LMEM for bootrom runtime  */
+	{
+		.virt = CONFIG_SYS_INIT_RAM_ADDR,
+		.phys = CONFIG_SYS_INIT_RAM_ADDR,
+		.size = CONFIG_SYS_INIT_RAM_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#else
+	/* DDR entries for cached memory, total size is a placehold
+	   and will be filled in at run time. MUST be first entry */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 1UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+		/* CCI-500 */
+	{
+		.virt = 0x81100000,
+		.phys = 0x81100000,
+		.size = 0x91000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* BIUCFG */
+	{
+		.virt = 0x81060000,
+		.phys = 0x81060000,
+		.size = 0x3000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* PMC */
+	{
+		.virt = 0x80200000,
+		.phys = 0x80200000,
+		.size = 0x81000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* USB */
+	{
+		.virt = 0x8000C000UL,
+		.phys = 0x8000C000UL,
+		.size = 0x3000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#endif
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000UL,
+		.phys = 0xff800000UL,
+                .size = 0x100000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, 
+		/* System port and Switch Core */
+	{
+		.virt = 0x80400000UL,
+		.phys = 0x80400000UL,
+		.size = 0x100000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* GIC */
+	{
+		.virt = 0x81001000UL,
+		.phys = 0x81001000UL,
+		.size = 0x7000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* UBUS4 Coherency Port */
+	{
+		.virt = 0x810A0000,
+		.phys = 0x810A0000,
+		.size = 0x1000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},	
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm963158_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm63178/Kconfig b/arch/arm/mach-bcmbca/bcm63178/Kconfig
new file mode 100644
index 0000000000..b36c07b3ed
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63178/Kconfig
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM63178
+
+config TARGET_BCM963178
+	bool "Broadcom 63178 Reference Board"
+	depends on ARCH_BCMBCA
+
+config SYS_SOC
+	default "bcm63178"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+	hex "default DDR3 mcb selector value"
+	default 0x20001603
+endif
+
+config TPL_MAX_SIZE
+	default 1048576
+
+config RSVD_USE_MAX_FROM_ENV_AND_DT 
+	bool "RSVD will use max value from env and DT"
+	default y
+
+config BCMBCA_LDO_TRIM
+	bool "Support LDO Trim"
+	default y
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm63178/Makefile b/arch/arm/mach-bcmbca/bcm63178/Makefile
new file mode 100644
index 0000000000..e80bcb13a3
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63178/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+obj-y += cpu.o
+obj-y += mmu_table.o
diff --git a/arch/arm/mach-bcmbca/bcm63178/cpu.c b/arch/arm/mach-bcmbca/bcm63178/cpu.c
new file mode 100644
index 0000000000..61b3bf11d6
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63178/cpu.c
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/ubus4.h>
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+static void enable_ns_access(void)
+{
+	BIUCFG->bac.bac_permission |= 0x33;     // Linux access to BAC_CPU_THERM_TEMP
+}
+/*this function is used to turn on CCI from secure mode
+ *   it also turns snooping enable for S5 CPU interface*/
+static void cci500_enable(void)
+{
+	/*Enable access from E2 and below */
+	CCI500->secr_acc |= SECURE_ACCESS_UNSECURE_ENABLE;
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+	printf("Chip ID: BCM%X_%X\n",chipId,revId);
+}
+#endif
+
+#if defined(CONFIG_BCMBCA_PMC)
+
+void boost_cpu_clock(void)
+{
+	printf("set cpu freq to 1500MHz\n");
+	set_cpu_freq(1500);
+	pll_ch_freq_set(PMB_ADDR_BIU_PLL, 1, 3000/600); // raise ACEBIU clock rate to 600 MHz
+}
+
+int set_cpu_freq(int freqMHz)
+{
+	int mdiv;
+
+	if( freqMHz > 1500 || freqMHz < 300 )
+	{
+		printf("%dMHz is not supported\n", freqMHz);
+		return -1;
+	}
+
+	/* VCO at 3GHz, mdiv = Fvco/target frequency */
+	mdiv = 3000/freqMHz;
+
+	pll_ch_freq_set(PMB_ADDR_BIU_PLL, 0, mdiv);
+
+	return 3000/mdiv;	
+}
+#endif
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NOR)
+		return BOOT_DEVICE_NOR;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	u32 frq = COUNTER_FREQUENCY;
+
+	spl_ddrinit_prepare();
+
+	// set arch timer frequency
+	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
+	// enable system timer
+	BIUCFG->TSO_CNTCR |= 1;
+
+	/* force axi write reply to workaround wifi memory write ordering issue */
+	ubus_master_cpu_enable_axi_write_cache(0);
+	/* enable unalgined access */
+	set_cr(get_cr() & ~CR_A);
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+	cci500_enable();
+	enable_ns_access();
+#endif
+
+    return 0;
+}
+
+void arch_cpu_deinit()
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	/* restore axi write cache when we spl does not need to use wifi memory */
+	ubus_master_cpu_enable_axi_write_cache(1);
+#endif
+}
diff --git a/arch/arm/mach-bcmbca/bcm63178/mmu_table.c b/arch/arm/mach-bcmbca/bcm63178/mmu_table.c
new file mode 100644
index 0000000000..76dfcb1f86
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63178/mmu_table.c
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include "mmu_map_v7.h"
+
+static struct mm_region broadcom_bcm963178_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) 
+#if !defined(CONFIG_TPL_BUILD)
+	/* SPL table */
+	/* DDR memory. Enable the maximum 2GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000,
+		.phys = 0x00000000,
+		.size = SZ_2G,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+	/* PSRAM for SPL runtime  */
+
+	{
+		.virt = 0x84200000,
+		.phys = 0x84200000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_CACHED_MEM,
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+#else
+	/* TPL table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+#endif
+#else
+	/* u-boot table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	{
+		/* CCI 500 */
+		.virt = 0x81100000,
+		.phys = 0x81100000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* SWITCH SYSPORT */
+		.virt = 0x80400000,
+		.phys = 0x80400000,
+		.size = SZ_2M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* BIU */
+		.virt = 0x81000000,
+		.phys = 0x81000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* UBUS */
+		.virt = 0x83000000,
+		.phys = 0x83000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* USB (includes other blocks in the 1M window) */
+		.virt = 0x8000c000,
+		.phys = 0x8000c000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+#endif
+	{
+		/* PMC */
+		.virt = 0x80200000,
+		.phys = 0x80200000,
+		.size = SZ_2M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* MEMC PHY register */
+		.virt = 0x80100000,
+		.phys = 0x80100000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000,
+		.phys = 0xff800000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* BLUT */
+		.virt = 0xfff00000,
+		.phys = 0xfff00000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	}, 
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm963178_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm6756/Kconfig b/arch/arm/mach-bcmbca/bcm6756/Kconfig
new file mode 100644
index 0000000000..2215eed4e5
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6756/Kconfig
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM6756
+
+config TARGET_BCM96756
+	bool "Broadcom 47622 Reference Board"
+	depends on ARCH_BCMBCA
+
+config SYS_SOC
+	default "bcm6756"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+	hex "default DDR3 mcb selector value"
+	default 0x00001607
+
+config BCMBCA_DDR4_DEF_MCBSEL
+	hex "default DDR4 mcb selector value"
+	default 0x101607
+endif
+
+config TPL_MAX_SIZE
+	default 1048576
+
+config RSVD_USE_MAX_FROM_ENV_AND_DT 
+	bool "RSVD will use max value from env and DT"
+	default y
+
+config BCMBCA_LDO_TRIM
+	bool "Support LDO Trim"
+	default y
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm6756/Makefile b/arch/arm/mach-bcmbca/bcm6756/Makefile
new file mode 100644
index 0000000000..29dad125c5
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6756/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+obj-y += cpu.o
+obj-y += mmu_table.o
\ No newline at end of file
diff --git a/arch/arm/mach-bcmbca/bcm6756/cpu.c b/arch/arm/mach-bcmbca/bcm6756/cpu.c
new file mode 100644
index 0000000000..b60aac79f2
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6756/cpu.c
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/ubus4.h>
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+static void enable_ns_access(void)
+{
+	BIUCFG->bac.bac_permission |= 0x33;     // Linux access to BAC_CPU_THERM_TEMP
+}
+
+/*this function is used to turn on CCI from secure mode 
+*  *   it also turns snooping enable for S5 CPU interface*/
+static void cci500_enable(void)
+{
+	/*Enable access from E2 and below */
+	CCI500->secr_acc |= SECURE_ACCESS_UNSECURE_ENABLE;
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+	printf("Chip ID: BCM%X_%X\n",chipId,revId);
+}
+#endif
+
+#if defined(CONFIG_BCMBCA_PMC)
+
+void boost_cpu_clock(void)
+{
+	printf("set cpu freq to 1700MHz\n");
+	set_cpu_freq(1700);
+	pll_ch_freq_set(PMB_ADDR_BIU_PLL, 1, 3000/600); // raise ACEBIU clock rate to 600 MHz
+}
+
+int set_cpu_freq(int freqMHz)
+{
+	int mdiv;
+
+	if( freqMHz > 1700 || freqMHz < 485 )
+	{
+		printf("%dMHz is not supported\n", freqMHz);
+		return -1;
+	}
+
+	/* VCO at 3.4GHz, mdiv = Fvco/target frequency */
+	mdiv = 3400/freqMHz;
+
+	pll_ch_freq_set(PMB_ADDR_BIU_PLL, 0, mdiv);
+
+	return 3400/mdiv;	
+}
+#endif
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_EMMC)
+		return BOOT_DEVICE_MMC1;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+
+	u32 frq = COUNTER_FREQUENCY;
+
+	spl_ddrinit_prepare();
+
+	/* set arch timer frequency */
+	asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
+	/* enable system timer */
+	BIUCFG->TSO_CNTCR |= 1;
+
+	/* enable unalgined access */
+	set_cr(get_cr() & ~CR_A);	
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+	enable_ns_access();
+	cci500_enable();
+#endif
+
+
+    return 0;
+}
+
+void arch_cpu_deinit()
+{
+}
+
+int get_nr_cpus()
+{
+	uint32_t nr_cpus;
+
+	if (bcm_otp_get_nr_cpus(&nr_cpus)) {
+		printf("Error: failed to read cpu core from OTP\n");
+		nr_cpus = 4;
+	} else {
+		if (nr_cpus >= 0 && nr_cpus <= 4)
+			nr_cpus = 4;
+		else
+			nr_cpus = 8 - nr_cpus;
+	}
+
+	return nr_cpus;
+}
+
+#if !defined(CONFIG_TPL_ATF)
+void boot_secondary_cpu(unsigned long vector)
+{
+	uint32_t cpu = 1; 
+	uint32_t nr_cpus = get_nr_cpus();
+	ARM_CONTROL_REG ctrl_reg;
+
+	printf("boot secondary cpu from 0x%lx\n", vector);
+
+	*(volatile uint32_t*)(BOOTLUT_BASE+0x20) = vector;
+	
+	while (cpu < nr_cpus) {
+		int stat;
+
+		stat = PowerOnDevice(PMB_ADDR_ORION_CPU0 + cpu);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to power on secondary cpu %d - sts %d\n", cpu, stat);
+		
+		stat = ReadBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), &ctrl_reg.Reg32);
+		ctrl_reg.Bits.cpu_reset_n &= ~(0x1 << cpu);
+		stat |= WriteBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), ctrl_reg.Reg32);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to boot secondary cpu %d - sts %d\n", cpu, stat);
+		
+		cpu++;
+	}
+
+	return;
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm6756/mmu_table.c b/arch/arm/mach-bcmbca/bcm6756/mmu_table.c
new file mode 100644
index 0000000000..fd1a21d841
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6756/mmu_table.c
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include "mmu_map_v7.h"
+
+static struct mm_region broadcom_bcm96756_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) 
+#if !defined(CONFIG_TPL_BUILD)
+	/* SPL table */
+	/* DDR memory. Enable the maximum 2GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000,
+		.phys = 0x00000000,
+		.size = SZ_2G,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+	/* PSRAM for SPL runtime  */
+
+	{
+		.virt = 0x85200000,
+		.phys = 0x85200000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_CACHED_MEM,
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+#else
+	/* TPL table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+#endif
+#else
+	/* u-boot table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	{
+		/* CCI 500 */
+		.virt = 0x81100000,
+		.phys = 0x81100000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* SYSPORT 0 and 1 */
+		.virt = 0x80400000,
+		.phys = 0x80400000,
+		.size = SZ_2M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* BIU */
+		.virt = 0x81000000,
+		.phys = 0x81000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* UBUS */
+		.virt = 0x83000000,
+		.phys = 0x83000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* USB (includes other blocks in the 1M window) */
+		.virt = 0x8000c000,
+		.phys = 0x8000c000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+#endif
+	{
+		/* PMC */
+		.virt = 0x80200000,
+		.phys = 0x80200000,
+		.size = SZ_2M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* MEMC PHY register */
+		.virt = 0x80100000,
+		.phys = 0x80100000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000,
+		.phys = 0xff800000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* BLUT */
+		.virt = 0xfff00000,
+		.phys = 0xfff00000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	}, 
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm96756_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm6846/Kconfig b/arch/arm/mach-bcmbca/bcm6846/Kconfig
new file mode 100644
index 0000000000..b22c710545
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6846/Kconfig
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM6846
+
+config TARGET_BCM96846
+    bool "Broadcom 6846 Reference Board"
+    depends on ARCH_BCMBCA
+
+config SYS_SOC
+    default "bcm6846"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+    hex "default mcb selector value"
+    default 0x527
+endif
+
+config TPL_MAX_SIZE
+    default 1048576
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
+
diff --git a/arch/arm/mach-bcmbca/bcm6846/Makefile b/arch/arm/mach-bcmbca/bcm6846/Makefile
new file mode 100644
index 0000000000..5567c2c89e
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6846/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/pmc
+
+obj-y += cpu.o
+obj-y += mmu_table.o
+
diff --git a/arch/arm/mach-bcmbca/bcm6846/cpu.c b/arch/arm/mach-bcmbca/bcm6846/cpu.c
new file mode 100644
index 0000000000..ee0671efdb
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6846/cpu.c
@@ -0,0 +1,249 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/ubus4.h>
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#include "clk_rst.h"
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+static void cci400_enable(void)
+{
+    CCI400->secr_acc |= SECURE_ACCESS_UNSECURE_ENABLE;
+}
+
+static void enable_ns_access(void)
+{
+    BIUCFG->aux.permission |= 0xff;
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+static void swrw(unsigned int ps, unsigned int reg, unsigned int val)
+{
+    unsigned int cmd = 0;
+    unsigned int cmd1 = 0;
+    unsigned int reg0 = 0;
+
+    PROCMON->SSBMaster.control = SWR_EN;
+
+    if (reg == 0) {
+        /* no need read reg0 in case that we write to it , we know wal :) */
+        reg0 = val;
+    } else {
+        /* read reg0 */
+        cmd1 = SWR_READ_CMD_P | SET_ADDR(ps, 0);
+        PROCMON->SSBMaster.control = cmd1;
+        SR_TEST(1)
+            reg0 = PROCMON->SSBMaster.rd_data;
+    }
+    /* write reg */
+    PROCMON->SSBMaster.wr_data = val;
+    cmd = SWR_WR_CMD_P | SET_ADDR(ps, reg);
+    PROCMON->SSBMaster.control = cmd;
+    SR_TEST(2);
+    /*toggele bit 1 reg0 this load the new regs value */
+    cmd1 = SWR_WR_CMD_P | SET_ADDR(ps, 0);
+    PROCMON->SSBMaster.wr_data = reg0 & ~0x2;
+    PROCMON->SSBMaster.control = cmd1;
+    SR_TEST(3);
+    PROCMON->SSBMaster.wr_data = reg0 | 0x2;
+    PROCMON->SSBMaster.control = cmd1;
+    SR_TEST(4);
+    PROCMON->SSBMaster.wr_data = reg0 & ~0x2;
+    PROCMON->SSBMaster.control = cmd1;
+    SR_TEST(5);
+}
+
+static void bcm_setsw(void)
+{
+    swrw(0,3,0x5171);
+    swrw(0,6,0xb000);
+    swrw(0,7,0x0029);
+    /* 1.8 SWREG  set bit reg3[8] & reg3[4]  pll_en and pll_phase_en */
+    swrw(1,3,0x5170);
+    swrw(1,7,0x0029);
+    /* 1.5 SWREG  set bit reg3[8] & reg3[4]  pll_en and pll_phase_en */
+    swrw(2,3,0x5170);
+    swrw(2,7,0x0029);
+    /* 1.0 Analog SWREG  set bit reg3[8] & reg3[4]  pll_en and pll_phase_en */
+    swrw(3,3,0x5170);
+    swrw(3,7,0x0029);
+
+    if (!(MISC->miscStrapBus & MISC_STRAP_ENABLE_INT_1p8V))
+        swrw(1,0,0xc691);
+}
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+#define CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV (17)
+static void disable_xtal_clk(void)
+{
+    uint32_t data;
+    int ret;
+
+    ret = ReadBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+                   CLKRSTBPCMRegOffset(xtal_control), &data);
+
+    data |= (0x1 << CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV);
+
+    ret |= WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+                CLKRSTBPCMRegOffset(xtal_control), data);
+
+    if (ret)
+        printf("Failed to disable xtal clk\n");
+}
+#endif
+
+void boost_cpu_clock(void)
+{
+    unsigned int clk_index, cpu_clock;
+    int stat;
+    PLL_CTRL_REG ctrl_reg;
+
+    //configure ubus clock
+    UBUS4CLK->ClockCtrl = 0x04;
+
+    if (!bcm_otp_get_cpu_clk(&clk_index))
+    {
+        switch (clk_index) {
+        case 0:
+        case 1:
+            cpu_clock = 1000;
+            break;
+        case 2:
+            cpu_clock = 750;
+            break;
+        default:
+            cpu_clock = 0;
+        }
+    }
+    else
+        printf("Error: failed to read cpu clock\n");
+   
+    stat = ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLCLASSICBPCMRegOffset(resets), &ctrl_reg.Reg32);
+    ctrl_reg.Bits.byp_wait = 0;
+    stat |= WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLCLASSICBPCMRegOffset(resets), ctrl_reg.Reg32);
+
+    if (stat)
+        printf("Error: failed to set cpu fast mode\n");
+    else
+        printf("CPU Clock: %dMHz\n", cpu_clock);
+
+    disable_xtal_clk();
+}
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+    u32 frq = COUNTER_FREQUENCY;
+
+    spl_ddrinit_prepare();
+
+    // set arch timer frequency
+    asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
+
+    // enable spi slave
+    *((volatile unsigned int*)CONFIG_BROM_REG_ADDR) |= 0x4;
+
+    // enable system timer
+    BIUCFG->TSO_CNTCR |= 1;
+
+    bcm_setsw();
+    
+    /* enable unalgined access */    
+    set_cr(get_cr() & ~CR_A);
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+    enable_ns_access();
+    cci400_enable();
+#endif
+
+	return 0;
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+const uint32_t cpu_speed_table[4] = {
+	1000, 1000, 750, 0
+};
+
+void print_chipinfo(void)
+{
+	char *mktname = NULL;
+	unsigned int cpu_speed, rdp_speed, clk_index;
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+	switch (chipId) {
+	case(0x68463):
+		mktname = "68460U";
+		break;
+	case(0x68464):
+		mktname = "68461S";
+	default:
+		mktname = NULL;
+	}
+
+	if (mktname == NULL)
+		printf("Chip ID: BCM%X_%X\n",chipId,revId);
+	else
+		printf("Chip ID: BCM%s_%X\n",mktname,revId);
+
+	get_rdp_freq(&rdp_speed);
+	if ( !bcm_otp_get_cpu_clk(&clk_index) )
+		cpu_speed = cpu_speed_table[clk_index];
+	else
+		cpu_speed = 0;
+
+	printf("ARM Cortex A7 Dual Core: %dMHz\n",cpu_speed);
+	printf("RDP: %dMHz\n",rdp_speed);
+}
+#endif
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+#if !defined(CONFIG_TPL_ATF)
+void boot_secondary_cpu(unsigned long vector)
+{
+	uint32_t cpu = 1; 
+	uint32_t nr_cpus = 2;
+	ARM_CONTROL_REG ctrl_reg;
+
+	printf("boot secondary cpu from 0x%lx\n", vector);
+
+	*(volatile uint32_t*)(BOOTLUT_BASE+0x20) = vector;
+	
+	while (cpu < nr_cpus) {
+		int stat;
+
+		stat = ReadBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), &ctrl_reg.Reg32);
+		ctrl_reg.Bits.cpu_reset_n &= ~(0x1 << cpu);
+		stat |= WriteBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), ctrl_reg.Reg32);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to boot secondary cpu %d - sts %d\n", cpu, stat);
+		cpu++;
+	}
+
+	return;
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm6846/mmu_table.c b/arch/arm/mach-bcmbca/bcm6846/mmu_table.c
new file mode 100644
index 0000000000..9f420a0fdd
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6846/mmu_table.c
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include "mmu_map_v7.h"
+
+static struct mm_region broadcom_bcm96846_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) 
+#if !defined(CONFIG_TPL_BUILD)
+	/* SPL table */
+	/* DDR memory. Enable the maximum 2GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000,
+		.phys = 0x00000000,
+		.size = SZ_1G,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+	/* PSRAM for SPL runtime  */
+
+	{
+		.virt = 0x82600000,
+		.phys = 0x82600000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+
+    /* page table area */
+    {
+        .virt = 0x7ff00000,
+        .phys = 0x7ff00000,
+        .size = SZ_1M,
+        .attrs = SECTION_ATTR_DEVICE,
+    },
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+#else
+	/* TPL table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+    {
+        /* UBUS */
+        .virt = 0x83000000,
+        .phys = 0x83000000,
+        .size = SZ_1M,
+        .attrs = SECTION_ATTR_DEVICE,
+    },
+
+#endif
+#else
+	/* u-boot table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	{
+		/* BIU & CCI400 */
+		.virt = 0x81000000,
+		.phys = 0x81000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+		/* USB */
+	{
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+#endif
+	{
+		/* PMC */
+		.virt = 0xffb00000,
+		.phys = 0xffb00000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* MEMC PHY register */
+		.virt = 0x80100000,
+		.phys = 0x80100000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000,
+		.phys = 0xff800000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* BLUT */
+		.virt = 0xfff00000,
+		.phys = 0xfff00000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	}, 
+		/* XRDP */
+	{
+		.virt = 0x82000000UL,
+		.phys = 0x82000000UL,
+		.size = 16 * SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm96846_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm6855/Kconfig b/arch/arm/mach-bcmbca/bcm6855/Kconfig
new file mode 100644
index 0000000000..bc2f5c47ed
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6855/Kconfig
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM6855
+
+config TARGET_BCM96855
+    bool "Broadcom 6855 Reference Board"
+    depends on ARCH_BCMBCA
+
+config SYS_SOC
+    default "bcm6855"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+    hex "default mcb selector value"
+    default 0x80407
+endif
+
+config TPL_MAX_SIZE
+    default 1048576
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
+
diff --git a/arch/arm/mach-bcmbca/bcm6855/Makefile b/arch/arm/mach-bcmbca/bcm6855/Makefile
new file mode 100644
index 0000000000..5567c2c89e
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6855/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/pmc
+
+obj-y += cpu.o
+obj-y += mmu_table.o
+
diff --git a/arch/arm/mach-bcmbca/bcm6855/cpu.c b/arch/arm/mach-bcmbca/bcm6855/cpu.c
new file mode 100644
index 0000000000..5c58815481
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6855/cpu.c
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/ubus4.h>
+#include <spl.h>
+#include "bcm_otp.h"
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#include "clk_rst.h"
+#endif
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+    u32 frq = COUNTER_FREQUENCY;
+
+    // set arch timer frequency
+    asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
+
+    // enable system timer
+    BIUCFG->TSO_CNTCR |= 1;
+
+    /* enable unalgined access */    
+    set_cr(get_cr() & ~CR_A);
+#endif
+
+    return 0;
+}
+
+void boost_cpu_clock(void)
+{
+    int stat = 0;
+    uint32_t chipid;
+    PLL_CTRL_REG ctrl_reg;
+
+    chipid =  (((PERF->RevID & CHIP_ID_MASK) >> (CHIP_ID_SHIFT-CHIP_ID_LC_SIZE)) | (TOP->OtpChipidLC && CHIP_ID_LC_MASK));
+    if ((chipid==0x68552c) || (chipid==0x682520) || (chipid==0x685500))
+    {
+        stat = ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), &ctrl_reg.Reg32);
+        ctrl_reg.Bits.byp_wait = 1;
+        stat |= WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), ctrl_reg.Reg32);
+
+        stat |= pll_vco_config(PMB_ADDR_BIU_PLL ,60, 1);
+        stat |= pll_ch_freq_set(PMB_ADDR_BIU_PLL, 0, 2);
+
+        stat = ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), &ctrl_reg.Reg32);
+        ctrl_reg.Bits.byp_wait = 0;
+        stat |= WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), ctrl_reg.Reg32);
+    }
+    else if (chipid==685520)
+        stat = pll_ch_freq_set(PMB_ADDR_BIU_PLL, 0, 2);
+
+    if (stat)
+        printf("Error: failed to set cpu clock\n");
+
+    UBUS4CLK->ClockCtrl = UBUS4_CLK_BYPASS_MASK;
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	unsigned int cpu_speed, rdp_speed, nr_cores;
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+    unsigned int chipIdLC = (TOP->OtpChipidLC && CHIP_ID_LC_MASK);
+    if (chipIdLC)
+        chipId = (chipId << CHIP_ID_LC_SIZE) | chipIdLC;
+
+    printf("Chip ID: BCM%X_%X\n",chipId,revId);
+
+    pll_ch_freq_get(PMB_ADDR_BIU_PLL, 0, &cpu_speed);
+    if (bcm_otp_get_nr_cpus(&nr_cores))
+        printf("Error: failed to read cores from OTP\n");
+    else
+    {
+        if (nr_cores)
+            printf("ARM Cortex A7 Dual Core: %dMHz", cpu_speed);
+        else
+            printf("ARM Cortex A7 Triple Core: %dMHz", cpu_speed);
+    }
+
+    get_rdp_freq(& rdp_speed);
+    printf("RDP Freq: %dMHz\n", rdp_speed);
+}
+#endif
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+#if !defined(CONFIG_TPL_ATF)
+void boot_secondary_cpu(unsigned long vector)
+{
+    uint32_t cpu = 1;
+    uint32_t nr_cpus;
+    ARM_CONTROL_REG ctrl_reg;
+    uint64_t rvbar = vector;
+    int stat;
+
+    printf("boot secondary cpu from 0x%lx\n", vector);
+
+    *(volatile uint32_t*)(BOOTLUT_BASE+0x20) = vector;
+
+    if ( bcm_otp_get_nr_cpus(&nr_cpus) )
+        return;
+
+    nr_cpus = MAX_NUM_OF_CPU-nr_cpus;
+
+    while (cpu < nr_cpus)
+    {
+        BIUCFG->cluster[0].rvbar_addr[cpu] = rvbar;
+
+        stat = PowerOnDevice(PMB_ADDR_ORION_CPU0 + cpu);
+        if (stat != kPMC_NO_ERROR)
+            printf("failed to power on secondary cpu %d - sts %d\n", cpu, stat);	
+
+        stat = ReadBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), &ctrl_reg.Reg32);
+        ctrl_reg.Bits.cpu_reset_n &= ~(0x1 << cpu);
+        stat |= WriteBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), ctrl_reg.Reg32);
+        if (stat != kPMC_NO_ERROR)
+            printf("failed to boot secondary cpu %d - sts %d\n", cpu, stat);
+        cpu++;
+    }
+
+    return;
+}
+#endif
+
diff --git a/arch/arm/mach-bcmbca/bcm6855/mmu_table.c b/arch/arm/mach-bcmbca/bcm6855/mmu_table.c
new file mode 100644
index 0000000000..4d9b62d133
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6855/mmu_table.c
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include "mmu_map_v7.h"
+
+static struct mm_region broadcom_bcm96855_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) 
+#if !defined(CONFIG_TPL_BUILD)
+	/* SPL table */
+	/* DDR memory. Enable the maximum 2GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000,
+		.phys = 0x00000000,
+		.size = SZ_2G,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+
+	/* PSRAM for SPL runtime  */
+	{
+		.virt = 0x82000000,
+		.phys = 0x82000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+
+    /* page table area */
+    {
+        .virt = 0x82700000,
+        .phys = 0x82700000,
+        .size = SZ_1M,
+        .attrs = SECTION_ATTR_DEVICE,
+    },
+#else
+	/* TPL table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	{
+		.virt = 0x82000000,
+		.phys = 0x82000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+#endif
+#else
+	/* u-boot table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	{
+		/* BIU */
+		.virt = 0x81000000,
+		.phys = 0x81000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* UBUS */
+		.virt = 0x83000000,
+		.phys = 0x83000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+		/* USB */
+	{
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+		/* XRDP */
+	{
+		.virt = 0x82000000UL,
+		.phys = 0x82000000UL,
+		.size = 16 * SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+#endif
+	{
+		/* PMC */
+		.virt = 0xffb00000,
+		.phys = 0xffb00000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* MEMC PHY register */
+		.virt = 0x80100000,
+		.phys = 0x80100000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000,
+		.phys = 0xff800000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* BLUT */
+		.virt = 0xfff00000,
+		.phys = 0xfff00000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	}, 
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm96855_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm6856/Kconfig b/arch/arm/mach-bcmbca/bcm6856/Kconfig
new file mode 100644
index 0000000000..937db38456
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6856/Kconfig
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM6856
+
+config TARGET_BCM96856
+	bool "Broadcom 6856 Reference Board"
+	depends on ARCH_BCMBCA
+
+config SYS_SOC
+	default "bcm6856"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+	hex "default DDR3 mcb selector value"
+	default 0x1527
+endif
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm6856/Makefile b/arch/arm/mach-bcmbca/bcm6856/Makefile
new file mode 100644
index 0000000000..c7efc2be51
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6856/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/pmc
+
+obj-y += mmu_table.o
+obj-y += cpu.o
+
diff --git a/arch/arm/mach-bcmbca/bcm6856/cpu.c b/arch/arm/mach-bcmbca/bcm6856/cpu.c
new file mode 100644
index 0000000000..9f9fa84839
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6856/cpu.c
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ubus4.h>
+#include "bcm_otp.h"
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#include "clk_rst.h"
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+static void cci400_enable(void)
+{
+	CCI400->secr_acc |= SECURE_ACCESS_UNSECURE_ENABLE;
+}
+
+static void enable_ns_access(void)
+{
+	BIUCFG->aux.permission |= 0xff;
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+static void swrw(unsigned int ps, unsigned int reg, unsigned int val)
+{
+    unsigned int cmd = 0;
+    unsigned int cmd1 = 0;
+    unsigned int reg0 = 0;
+
+    PROCMON->SSBMaster.control = SWR_EN;
+
+    if (reg == 0) {
+        /* no need read reg0 in case that we write to it , we know wal :) */
+        reg0 = val;
+    } else {
+        /* read reg0 */
+        cmd1 = SWR_READ_CMD_P | SET_ADDR(ps, 0);
+        PROCMON->SSBMaster.control = cmd1;
+        SR_TEST(1)
+            reg0 = PROCMON->SSBMaster.rd_data;
+    }
+    /* write reg */
+    PROCMON->SSBMaster.wr_data = val;
+    cmd = SWR_WR_CMD_P | SET_ADDR(ps, reg);
+    PROCMON->SSBMaster.control = cmd;
+    SR_TEST(2);
+    /*toggele bit 1 reg0 this load the new regs value */
+    cmd1 = SWR_WR_CMD_P | SET_ADDR(ps, 0);
+    PROCMON->SSBMaster.wr_data = reg0 & ~0x2;
+    PROCMON->SSBMaster.control = cmd1;
+    SR_TEST(3);
+    PROCMON->SSBMaster.wr_data = reg0 | 0x2;
+    PROCMON->SSBMaster.control = cmd1;
+    SR_TEST(4);
+    PROCMON->SSBMaster.wr_data = reg0 & ~0x2;
+    PROCMON->SSBMaster.control = cmd1;
+    SR_TEST(5);
+}
+
+static void bcm_setsw(void)
+{
+    swrw(0,3,0x5372);
+    swrw(0,6,0xb000);
+    swrw(0,7,0x0029);
+    swrw(1,3,0x5370);
+    swrw(1,7,0x0029);
+    swrw(2,3,0x5370);
+    swrw(2,7,0x0029);
+    swrw(3,3,0x5370);
+    swrw(3,7,0x0029);
+}
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+#define CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV (17)
+static void disable_xtal_clk(void)
+{
+    uint32_t data;
+    int ret;
+
+    ret = ReadBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+                   CLKRSTBPCMRegOffset(xtal_control), &data);
+
+    data |= (0x1 << CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV);
+
+    ret |= WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+                CLKRSTBPCMRegOffset(xtal_control), data);
+
+    if (ret)
+        printf("Failed to disable xtal clk\n");
+}
+#endif
+
+void boost_cpu_clock(void)
+{
+    unsigned int clk_index, cpu_clock;
+    int stat;
+    PLL_CTRL_REG ctrl_reg;
+
+    //configure ubus clock
+    UBUS4CLK->ClockCtrl = 0x04;
+
+    if ( !bcm_otp_get_cpu_clk(&clk_index) )
+        cpu_clock = 500 + 500*(2-clk_index);
+        else
+        cpu_clock = 0;
+
+    stat = ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLCLASSICBPCMRegOffset(resets), &ctrl_reg.Reg32);
+        ctrl_reg.Bits.byp_wait = 0;
+        stat |= WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLCLASSICBPCMRegOffset(resets), ctrl_reg.Reg32);
+
+    if (stat)
+        printf("Error: failed to set cpu fast mode\n");
+
+    printf("CPU Clock: %dMHz\n", cpu_clock);
+
+    disable_xtal_clk();
+}
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	spl_ddrinit_prepare();
+	bcm_setsw();
+	/* enable unalgined access */	
+	set_sctlr(get_sctlr() & ~CR_A);	
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+	enable_ns_access();
+	cci400_enable();
+#endif
+
+    return 0;
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	char *mktname = NULL;
+	char *nr_cores = NULL;
+	unsigned int cpu_speed, rdp_speed, otp_cores;
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+	printf("Chip ID: BCM%X_%X\n",chipId,revId);
+
+	if ( !bcm_otp_get_nr_cpus(&otp_cores) )
+	{
+		if (otp_cores == 0)
+			nr_cores = "Dual";
+		else if (otp_cores == 1)
+			nr_cores = "Single";
+	}
+
+	pll_ch_freq_get(PMB_ADDR_BIU_PLL, 0, &cpu_speed);
+	get_rdp_freq(&rdp_speed);
+
+	printf("Broadcom B53 %s Core: %dMHz\n", nr_cores, cpu_speed);
+	printf("RDP: %dMHz\n",rdp_speed);
+}
+#endif
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_EMMC)
+		return BOOT_DEVICE_MMC1;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+#if !defined(CONFIG_TPL_ATF)
+void boot_secondary_cpu(unsigned long vector)
+{
+	uint32_t cpu = 1; 
+	uint32_t nr_cpus = 2;
+	ARM_CONTROL_REG ctrl_reg;
+
+	printf("boot secondary cpu from 0x%lx\n", vector);
+
+	while (cpu < nr_cpus) {
+		int stat;
+
+		BIUCFG->cluster[0].rvbar_addr[cpu] = vector;
+		stat = PowerOnDevice(PMB_ADDR_ORION_CPU0 + cpu);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to power on secondary cpu %d - sts %d\n", cpu, stat);
+
+		stat = ReadBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), &ctrl_reg.Reg32);
+		ctrl_reg.Bits.cpu_reset_n &= ~(0x1 << cpu);
+		stat |= WriteBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), ctrl_reg.Reg32);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to boot secondary cpu %d - sts %d\n", cpu, stat);
+		cpu++;
+	}
+
+	return;
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm6856/mmu_table.c b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c
new file mode 100644
index 0000000000..a29f4fd510
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region broadcom_bcm96856_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	/* DDR memory. Enable the maximum 4GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 2UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	{
+		.virt = 0x100000000UL,
+		.phys = 0x100000000UL,
+		.size = 2UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* MEMC and DDRY PHY control registers */
+	{
+		.virt = 0x80180000UL,
+		.phys = 0x80180000UL,
+		.size = 0x40000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* LMEM for bootrom runtime  */
+	{
+		.virt = CONFIG_SYS_INIT_RAM_ADDR,
+		.phys = CONFIG_SYS_INIT_RAM_ADDR,
+		.size = CONFIG_SYS_INIT_RAM_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#else
+	/* DDR entries for cached memory, total size is a placehold
+	   and will be filled in at run time. MUST be first entry */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 1UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+		/* PMC */
+	{
+		.virt = 0xffb00000UL,
+		.phys = 0xffb00000UL,
+		.size = 0x6000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* PROC_MON */
+	{
+		.virt = 0xffb20000UL,
+		.phys = 0xffb20000UL,
+		.size = 0x1000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+        /* BIUCFG */
+	{
+		.virt = 0x81060000UL,
+		.phys = 0x81060000UL,
+		.size = 0x3000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* CCI400 */
+	{
+		.virt = 0x81090000,
+		.phys = 0x81090000,
+		.size = 0x10000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+        /* UBUS */
+    {
+        .virt = 0x83000000UL,
+        .phys = 0x83000000UL,
+        .size = 0x600000,
+        .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+             PTE_BLOCK_NON_SHARE |
+             PTE_BLOCK_PXN | PTE_BLOCK_UXN
+    },
+#if !defined(CONFIG_TPL_BUILD)
+		/* USB */
+	{
+		.virt = 0x8000C000UL,
+		.phys = 0x8000C000UL,
+		.size = 0x3000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* XRDP */
+	{
+		.virt = 0x82000000UL,
+		.phys = 0x82000000UL,
+		.size = 0x1000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#endif
+#endif
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000UL,
+		.phys = 0xff800000UL,
+		.size = SZ_1M,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, 
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm96856_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm6858/Kconfig b/arch/arm/mach-bcmbca/bcm6858/Kconfig
new file mode 100644
index 0000000000..374e2a032f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6858/Kconfig
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM6858
+
+config TARGET_BCM96858
+	bool "Broadcom 6858 Reference Board"
+	depends on ARCH_BCMBCA
+
+config SYS_SOC
+	default "bcm6858"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+	hex "default DDR3 mcb selector value"
+	default 0x527
+endif
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm6858/Makefile b/arch/arm/mach-bcmbca/bcm6858/Makefile
new file mode 100644
index 0000000000..c7efc2be51
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6858/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/pmc
+
+obj-y += mmu_table.o
+obj-y += cpu.o
+
diff --git a/arch/arm/mach-bcmbca/bcm6858/cpu.c b/arch/arm/mach-bcmbca/bcm6858/cpu.c
new file mode 100644
index 0000000000..1782cd601c
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6858/cpu.c
@@ -0,0 +1,281 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <spl_ddrinit.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/misc.h>
+#include "bcm_otp.h"
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "clk_rst.h"
+#include "asm/arch/BPCM.h"
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+static void cci400_enable(void)
+{
+    CCI400->secr_acc |= SECURE_ACCESS_UNSECURE_ENABLE;
+}
+
+static void enable_ns_access(void)
+{
+    BIUCFG->aux.permission |= 0xff;
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+static void swrw(unsigned int ps, unsigned int reg, unsigned int val)
+{
+    unsigned int cmd = 0;
+    unsigned int cmd1 = 0;
+    unsigned int reg0 = 0;
+
+    PROCMON->SSBMaster.control = SWR_EN;
+
+    if (reg == 0) {
+        /* no need read reg0 in case that we write to it , we know wal :) */
+        reg0 = val;
+    } else {
+        /* read reg0 */
+        cmd1 = SWR_READ_CMD_P | SET_ADDR(ps, 0);
+        PROCMON->SSBMaster.control = cmd1;
+        SR_TEST(1)
+            reg0 = PROCMON->SSBMaster.rd_data;
+    }
+    /* write reg */
+    PROCMON->SSBMaster.wr_data = val;
+    cmd = SWR_WR_CMD_P | SET_ADDR(ps, reg);
+    PROCMON->SSBMaster.control = cmd;
+    SR_TEST(2);
+    /*toggele bit 1 reg0 this load the new regs value */
+    cmd1 = SWR_WR_CMD_P | SET_ADDR(ps, 0);
+    PROCMON->SSBMaster.wr_data = reg0 & ~0x2;
+    PROCMON->SSBMaster.control = cmd1;
+    SR_TEST(3);
+    PROCMON->SSBMaster.wr_data = reg0 | 0x2;
+    PROCMON->SSBMaster.control = cmd1;
+    SR_TEST(4);
+    PROCMON->SSBMaster.wr_data = reg0 & ~0x2;
+    PROCMON->SSBMaster.control = cmd1;
+    SR_TEST(5);
+}
+
+static void bcm_setsw(void)
+{
+    swrw(1,3,0x5170);
+    swrw(1,7,0x4829);
+    swrw(2,3,0x5172);
+    swrw(2,7,0x4829);
+}
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+#define CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV (17)
+static void disable_xtal_clk(void)
+{
+    uint32_t data;
+    int ret;
+
+    ret = ReadBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+                   CLKRSTBPCMRegOffset(xtal_control), &data);
+
+    data |= (0x1 << CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV);
+
+    ret |= WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+                CLKRSTBPCMRegOffset(xtal_control), data);
+
+    if (ret)
+        printf("Failed to disable xtal clk\n");
+}
+#endif
+
+void boost_cpu_clock(void)
+{
+    unsigned int clk_index, cpu_clock;
+    unsigned int chipId = 0;
+    int stat;
+    bcm_otp_get_chipid(&chipId);
+
+    if (chipId == 0x5 || chipId == 0x2)
+    {
+        cpu_clock = 1000;
+        if (pll_ch_freq_set(PMB_ADDR_BIU_PLL, 0, 3))
+            printf("Error: failed to set CPU clock\n");
+    }
+    else if ( !bcm_otp_get_cpu_clk(&clk_index) )
+            cpu_clock = 500 + 500*(2-clk_index);
+    else
+        cpu_clock = 0;
+    
+    /* configure AXI clock */
+    if (pll_ch_freq_set(PMB_ADDR_BIU_PLL, 2, 4))
+        printf("Error: failed to set AXI clock\n");
+
+    /* Change cpu to fast clock */
+    if ((MISC->miscStrapBus)&MISC_STRAP_BUS_CPU_SLOW_FREQ)
+    {
+        int stat;
+        PLL_CTRL_REG ctrl_reg;
+        stat = ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), &ctrl_reg.Reg32);
+        ctrl_reg.Bits.byp_wait = 0;
+        stat |= WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), ctrl_reg.Reg32);
+        if (stat)
+            printf("Error: failed to set cpu fast mode\n");
+    }
+
+    printf("CPU Clock: %dMHz\n", cpu_clock);
+
+    stat = PowerOnDevice(PMB_ADDR_RDPPLL);
+
+    stat = pll_ch_freq_set(PMB_ADDR_RDPPLL, 0, 2);
+    stat |= pll_ch_freq_set(PMB_ADDR_RDPPLL, 1, 1);
+
+    if (stat)
+        printf("Error: Failed to set RDPPLL\n");
+
+    disable_xtal_clk();
+}
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	spl_ddrinit_prepare();
+	// enable system timer
+	BIUCFG->TSO_CNTCR |= 1;
+
+	bcm_setsw();
+	/* enable unalgined access */	
+	set_sctlr(get_sctlr() & ~CR_A);	
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+    enable_ns_access();
+    cci400_enable();
+#endif
+
+	return 0;
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	char *mktname = NULL;
+	char *nr_cores = NULL;
+	unsigned int cpu_speed, rdp_speed, chipId;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+	
+	if (bcm_otp_get_chipid(&chipId)) {
+		chipId = 0;
+	}
+
+ 
+	switch (chipId) {
+	case(0x0):
+		nr_cores = "Quad";
+	case(0x1):
+		mktname = "68580X";
+		break;
+	case(0x2):
+		nr_cores = "Dual";
+		mktname = "55040";
+		break;
+	case(0x3):
+		mktname = "68580H";
+		break;
+	case(0x4):
+		mktname = "55040P";
+		break;
+	case(0x5):
+		nr_cores = "Dual";
+		mktname = "55045";
+		break;
+	case(0x6):
+		mktname = "68580XV";
+		break;
+	case(0x7):
+		mktname = "49508";
+		break;
+	case(0x8):
+		mktname = "62119";
+		break;
+	case(0x9):
+		mktname = "68580XP";
+		break;
+	case(0xA):
+		mktname = "62119P";
+		break;
+	case(0xB):
+		nr_cores = "Dual";
+		mktname = "55040B";
+		break;
+	case(0xC):
+		mktname = "55040M";
+		break;
+	case(0xD):
+		mktname = "68580XF";
+		break;
+	default:
+		mktname = NULL;
+	}
+
+	printf("Chip ID: BCM%s_%X\n",mktname,revId);
+
+	pll_ch_freq_get(PMB_ADDR_BIU_PLL, 0, &cpu_speed);
+	printf("Broadcom B53 %s Core: %dMHz\n", nr_cores, cpu_speed);
+
+	get_rdp_freq(&rdp_speed);
+	printf("RDP: %dMHz\n",rdp_speed);
+}
+#endif
+
+int bcmbca_get_boot_device(void)
+{
+	unsigned int bootsel = ((MISC->miscStrapBus & MISC_STRAP_BUS_BOOT_SEL0_4_MASK) >> MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT) |
+							((MISC->miscStrapBus & MISC_STRAP_BUS_BOOT_SEL5_MASK) >> BOOT_SEL5_STRAP_ADJ_SHIFT);
+
+	if ((bootsel & BOOT_SEL_STRAP_BOOT_SEL_NAND_MASK) == BOOT_SEL_STRAP_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((bootsel & BOOT_SEL_STRAP_BOOT_SEL_MASK) == BOOT_SEL_STRAP_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	if ((bootsel & BOOT_SEL_STRAP_BOOT_SEL_MASK) == BOOT_SEL_STRAP_EMMC)
+		return BOOT_DEVICE_MMC1;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+#if !defined(CONFIG_TPL_ATF)
+void boot_secondary_cpu(unsigned long vector)
+{
+	uint32_t cpu = 1; 
+	uint32_t nr_cpus = 4;
+	ARM_CONTROL_REG ctrl_reg;
+
+	printf("boot secondary cpu from 0x%lx\n", vector);
+
+	while (cpu < nr_cpus) {
+		int stat;
+
+		BIUCFG->cluster[0].rvbar_addr[cpu] = vector >> 8;
+		stat = PowerOnDevice(PMB_ADDR_ORION_CPU0 + cpu);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to power on secondary cpu %d - sts %d\n", cpu, stat);
+
+		stat = ReadBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), &ctrl_reg.Reg32);
+		ctrl_reg.Bits.cpu_reset_n &= ~(0x1 << cpu);
+		stat |= WriteBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), ctrl_reg.Reg32);
+		if (stat != kPMC_NO_ERROR)
+			printf("failed to boot secondary cpu %d - sts %d\n", cpu, stat);
+		cpu++;
+	}
+
+	return;
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/bcm6858/mmu_table.c b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c
new file mode 100644
index 0000000000..b0c50e3f7d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c
@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region broadcom_bcm96858_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+	/* DDR memory. Enable the maximum 4GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 2UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	{
+		.virt = 0x100000000UL,
+		.phys = 0x100000000UL,
+		.size = 2UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* MEMC and DDRY PHY control registers */
+	{
+		.virt = 0x80180000UL,
+		.phys = 0x80180000UL,
+		.size = 0x40000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+	/* LMEM for bootrom runtime  */
+	{
+		.virt = CONFIG_SYS_INIT_RAM_ADDR,
+		.phys = CONFIG_SYS_INIT_RAM_ADDR,
+		.size = CONFIG_SYS_INIT_RAM_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#else
+	/* DDR entries for cached memory, total size is a placehold
+	   and will be filled in at run time. MUST be first entry */
+	{
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 1UL * SZ_1G,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			PTE_BLOCK_INNER_SHARE
+	},
+		/* PMC */
+	{
+		.virt = 0x80200000UL,
+		.phys = 0x80200000UL,
+		.size = 0x5000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* PROC_MON */
+	{
+		.virt = 0x80280000UL,
+		.phys = 0x80280000UL,
+		.size = 0x1000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+        /* BIUCFG */
+    {
+        .virt = 0x81060000,
+        .phys = 0x81060000,
+        .size = 0x3000,
+        .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+             PTE_BLOCK_NON_SHARE |
+             PTE_BLOCK_PXN | PTE_BLOCK_UXN
+    },
+
+       /* CCI400 */
+    {
+        .virt = 0x81090000,
+        .phys = 0x81090000,
+        .size = 0x10000,
+        .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+             PTE_BLOCK_NON_SHARE |
+             PTE_BLOCK_PXN | PTE_BLOCK_UXN
+    },
+	/* STD Mem  */
+	{
+		.virt = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.phys = CONFIG_SYS_INIT_STD_32K_ADDR,
+		.size = SZ_32K,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			PTE_BLOCK_NON_SHARE |
+			PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+
+#if !defined(CONFIG_TPL_BUILD)
+		/* USB */
+	{
+		.virt = 0x8000C000UL,
+		.phys = 0x8000C000UL,
+		.size = 0x3000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* LPORT */
+	{
+		.virt = 0x80138000UL,
+		.phys = 0x80138000UL,
+		.size = 0x6000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* UBUS */
+	{
+		.virt = 0x83000000UL,
+		.phys = 0x83000000UL,
+		.size = 0x600000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+		/* XRDP */
+	{
+		.virt = 0x82000000UL,
+		.phys = 0x82000000UL,
+		.size = 0x1000000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	},
+#endif
+#endif
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000UL,
+		.phys = 0xff800000UL,
+		.size = 0x100000,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, 
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm96858_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm6878/Kconfig b/arch/arm/mach-bcmbca/bcm6878/Kconfig
new file mode 100644
index 0000000000..b86344ebf6
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6878/Kconfig
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+if BCM6878
+
+config TARGET_BCM96878
+    bool "Broadcom 6878 Reference Board"
+    depends on ARCH_BCMBCA
+
+config SYS_SOC
+    default "bcm6878"
+
+if BCMBCA_DDRC
+config BCMBCA_DDR_DEF_MCBSEL
+    hex "default mcb selector value"
+    default 0x80407
+endif
+
+config TPL_MAX_SIZE
+    default 1048576
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
+
diff --git a/arch/arm/mach-bcmbca/bcm6878/Makefile b/arch/arm/mach-bcmbca/bcm6878/Makefile
new file mode 100644
index 0000000000..5567c2c89e
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6878/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/pmc
+
+obj-y += cpu.o
+obj-y += mmu_table.o
+
diff --git a/arch/arm/mach-bcmbca/bcm6878/cpu.c b/arch/arm/mach-bcmbca/bcm6878/cpu.c
new file mode 100644
index 0000000000..521335e0bf
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6878/cpu.c
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr.h>
+#include <spl.h>
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#include "clk_rst.h"
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+#define CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV (2)
+#define CLOCK_RESET_XTAL_CONTROL_BIT_PWRON  (27)
+#define CLOCK_RESET_XTAL_CONTROL2_BIT_PD    (0)
+
+static void disable_xtal_clk(void)
+{
+    uint32_t data;
+    int ret;
+
+    ret = ReadBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+                   CLKRSTBPCMRegOffset(pmd_xtal_cntl), &data);
+
+    data |= (0x1 << CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV);
+    data &= ~(0x1 << CLOCK_RESET_XTAL_CONTROL_BIT_PWRON);
+
+    ret |= WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+                CLKRSTBPCMRegOffset(pmd_xtal_cntl), data);
+
+    ret |= ReadBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+                 CLKRSTBPCMRegOffset(pmd_xtal_cntl2), &data);
+
+    data |= (0x1 << CLOCK_RESET_XTAL_CONTROL2_BIT_PD);
+
+    ret |= WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+                CLKRSTBPCMRegOffset(pmd_xtal_cntl2), data);
+
+    if (ret)
+        printf("Failed to disable xtal clk\n");
+}
+#endif
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+    u32 frq = COUNTER_FREQUENCY;
+
+    // set arch timer frequency
+    asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
+
+    // enable system timer
+    BIUCFG->TSO_CNTCR |= 1;
+
+    /* enable unalgined access */    
+    set_cr(get_cr() & ~CR_A);
+#endif
+
+    return 0;
+}
+
+void boost_cpu_clock(void)
+{
+    unsigned int clk_index, cpu_clock;
+    int stat;
+    PLL_CTRL_REG ctrl_reg;
+
+    if ( !bcm_otp_get_cpu_clk(&clk_index) )
+    {
+        switch (clk_index) {
+            case 0:
+            case 1:
+                cpu_clock = 1200;
+                break;
+            case 2:
+                cpu_clock = 800;
+                break;
+            default:
+                cpu_clock = 0;
+            }
+    }
+    else
+        printf("ERROR: failed to read cpu clock\n");
+
+    stat = ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), &ctrl_reg.Reg32);
+    ctrl_reg.Bits.byp_wait = 0;
+    stat |= WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), ctrl_reg.Reg32);
+
+    if (stat)
+        printf("ERROR: failed to set cpu fast clock\n");
+    else
+        printf("CPU Clock: %dMHz\n", cpu_clock);
+
+    disable_xtal_clk();
+}
+
+#if !defined(CONFIG_SPL_BUILD)
+void print_chipinfo(void)
+{
+	char *mktname = NULL;
+	unsigned int cpu_speed, rdp_speed;
+	unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
+	unsigned int revId = PERF->RevID & REV_ID_MASK;
+
+	switch (chipId) {
+	case(0x6878A):
+		mktname = "68782G";
+		break;
+	case(0x68789):
+		mktname = "68781H";
+		break;
+	case(0x6878C):
+		mktname = "68789";
+		break;
+	case(0x6878E):
+		mktname = "68782N";
+		break;
+	case(0x6878D):
+		mktname = "68781G";
+		break;
+	default:
+		mktname = NULL;
+	}
+
+	if (mktname == NULL)
+		printf("Chip ID: BCM%X_%X\n",chipId,revId);
+	else
+		printf("Chip ID: BCM%s_%X\n",mktname,revId);
+
+	pll_ch_freq_get(PMB_ADDR_BIU_PLL, 0, &cpu_speed);
+	get_rdp_freq(&rdp_speed);
+
+	printf("ARM Cortex A7 Dual Core: %dMHz\n",cpu_speed);
+	printf("RDP: %dMHz\n",rdp_speed);
+}
+#endif
+
+int bcmbca_get_boot_device(void)
+{
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
+		return BOOT_DEVICE_NAND;
+
+	if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
+		return BOOT_DEVICE_SPI;
+
+	printf("Error: boot_sel straps are not set correctly\n");
+
+	return BOOT_DEVICE_NONE;
+}
+
+#if !defined(CONFIG_TPL_ATF)
+void boot_secondary_cpu(unsigned long vector)
+{
+    uint32_t cpu = 1;
+    uint32_t nr_cpus = 2;
+    ARM_CONTROL_REG ctrl_reg;
+    uint64_t rvbar = vector;
+    int stat;
+
+    printf("boot secondary cpu from 0x%lx\n", vector);
+
+    *(volatile uint32_t*)(BOOTLUT_BASE+0x20) = vector;
+
+    BIUCFG->cluster[0].rvbar_addr[cpu] = rvbar;
+
+    stat = PowerOnDevice(PMB_ADDR_ORION_CPU0 + cpu);
+        if (stat != kPMC_NO_ERROR)
+            printf("failed to power on secondary cpu %d - sts %d\n", cpu, stat);
+
+    while (cpu < nr_cpus) 
+    {
+        stat = ReadBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), &ctrl_reg.Reg32);
+        ctrl_reg.Bits.cpu_reset_n &= ~(0x1 << cpu);
+        stat |= WriteBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), ctrl_reg.Reg32);
+        if (stat != kPMC_NO_ERROR)
+            printf("failed to boot secondary cpu %d - sts %d\n", cpu, stat);
+        cpu++;
+    }
+
+    return;
+}
+#endif
+
diff --git a/arch/arm/mach-bcmbca/bcm6878/mmu_table.c b/arch/arm/mach-bcmbca/bcm6878/mmu_table.c
new file mode 100644
index 0000000000..6c55bbe8c2
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6878/mmu_table.c
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include "mmu_map_v7.h"
+
+static struct mm_region broadcom_bcm96878_mem_map[] = {
+#if defined(CONFIG_SPL_BUILD) 
+#if !defined(CONFIG_TPL_BUILD)
+	/* SPL table */
+	/* DDR memory. Enable the maximum 2GB DDR for alias test. Use Device Attr
+	  to avoid CPU speculative fetch */
+	{
+		.virt = 0x00000000,
+		.phys = 0x00000000,
+		.size = SZ_2G,
+		.attrs = SECTION_ATTR_DEVICE, 
+	},
+	/* PSRAM for SPL runtime  */
+
+	{
+		.virt = 0x82600000,
+		.phys = 0x82600000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+
+    /* page table area */
+    {
+        .virt = 0x82c00000,
+        .phys = 0x82c00000,
+        .size = SZ_1M,
+        .attrs = SECTION_ATTR_DEVICE,
+    },
+#else
+	/* TPL table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	{
+		.virt = 0x82600000,
+		.phys = 0x82600000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+#endif
+#else
+	/* u-boot table */
+	/* 
+	 * uboot ddr entries for cached memory will be set in ram_bank_mmu_setup 
+	 * based on actual size 
+         */
+	{
+		/* BIU */
+		.virt = 0x81000000,
+		.phys = 0x81000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* UBUS */
+		.virt = 0x83000000,
+		.phys = 0x83000000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+		/* USB */
+	{
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+		/* XRDP */
+	{
+		.virt = 0x82000000UL,
+		.phys = 0x82000000UL,
+		.size = 16 * SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+#endif
+	{
+		/* PMC */
+		.virt = 0xffb00000,
+		.phys = 0xffb00000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* MEMC PHY register */
+		.virt = 0x80100000,
+		.phys = 0x80100000,
+		.size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* SoC peripheral */
+		.virt = 0xff800000,
+		.phys = 0xff800000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	},
+	{
+		/* BLUT */
+		.virt = 0xfff00000,
+		.phys = 0xfff00000,
+                .size = SZ_1M,
+		.attrs = SECTION_ATTR_DEVICE,
+	}, 
+	{
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = broadcom_bcm96878_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm_fdtdec.c b/arch/arm/mach-bcmbca/bcm_fdtdec.c
new file mode 100644
index 0000000000..1bcfd4e099
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm_fdtdec.c
@@ -0,0 +1,22 @@
+#include <common.h>
+#include <fdt.h>
+#include <malloc.h>
+#include <image.h>
+#include <asm/sections.h>
+
+#if defined(CONFIG_ARM64)
+void  __attribute__((section(".data"))) * g_fdt_ptr = NULL;
+void *board_fdt_blob_setup(void)
+{
+	struct fdt_header * fdt_blob = (ulong *)&_end;
+	if(  uimage_to_cpu(fdt_blob->magic) == FDT_MAGIC )
+	{
+		g_fdt_ptr = malloc(  uimage_to_cpu(fdt_blob->totalsize) );
+		if( g_fdt_ptr )
+			memcpy( (char*)g_fdt_ptr, (char*)fdt_blob, uimage_to_cpu(fdt_blob->totalsize) );
+	}
+
+	return g_fdt_ptr;
+}
+#endif
+
diff --git a/arch/arm/mach-bcmbca/bcmbca-dtsetup.c b/arch/arm/mach-bcmbca/bcmbca-dtsetup.c
new file mode 100644
index 0000000000..e1b4ee532d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcmbca-dtsetup.c
@@ -0,0 +1,512 @@
+#include <common.h>
+#include <malloc.h>
+#include <spl.h>
+
+#include "bcmbca-dtsetup.h"
+#include "dt_helper.h"
+#include "boot_flash.h"
+#include "spl_env.h"
+
+#define FDT_PAD_BYTES 0x1000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int set_sec_exports(void *blob)
+{
+	int off_linux, ret=0;
+	int  len = 0;	
+	u8 * value;
+	int trust_offset,exp_item_offset;
+	char * exp_flag;
+	char * node_name;
+	int ndepth;
+
+	off_linux=fdt_path_offset (blob, "/");
+	if (off_linux < 0) {
+		return ret;
+	}
+
+	trust_offset = fdt_path_offset(gd->fdt_blob, "/trust");
+	if (trust_offset < 0) {
+		debug("INFO: Didnt find /trust node in boot DTB\n");
+		return ret;
+	}
+
+	for (ndepth = 0, exp_item_offset = fdt_next_node(gd->fdt_blob, trust_offset, &ndepth);
+		(exp_item_offset >= 0) && (ndepth > 0);
+		exp_item_offset = fdt_next_node(gd->fdt_blob, exp_item_offset, &ndepth)) {
+		if (ndepth == 1) {
+				/*
+				 * Direct child node of the trust parent node,
+				 * i.e. item node.
+				 */
+			node_name = (char*)fdt_get_name(gd->fdt_blob, exp_item_offset, &len);
+			exp_flag = (char*)(fdt_getprop(gd->fdt_blob, exp_item_offset, "export", &len));
+			value = (char*)(fdt_getprop(gd->fdt_blob, exp_item_offset, "value", &len));
+		
+			if( exp_flag && len && value && node_name && (strcasecmp(exp_flag, "yes") == 0) ) {
+				ret = fdt_setprop(blob, off_linux, node_name, value, len);
+				if(ret != 0 ) {
+					printf("fdt_setprop failed for %s [%d]\n", node_name, ret);
+					return ret;
+				}
+			}
+		}
+	}
+	return ret;
+}
+
+static int set_uboot_version(void *blob)
+{
+	char version[64];
+	int offset, ret=-1;
+
+	display_options_get_banner(false, version, sizeof(version));
+	offset=fdt_path_offset (blob, "/");
+	if(offset >= 0 )
+	{
+		ret = fdt_setprop(blob, offset, "uboot-version", version, strlen(version));
+		if(ret != 0 )
+			printf("fdt_setprop failed [%d]\n", ret);
+	}
+	return ret;
+}
+
+static int set_uboot_env(void *blob)
+{
+	env_t *ep;
+	char *envbuf = NULL;
+	int ret = -2;
+	int elen;
+	char *config;
+	uint32_t new;
+	int i;
+	char *found = NULL;
+	int offset;
+
+	config = env_get("env_boot_magic");
+	if (NULL == config)
+	{
+		printf("env_boot_magic missing in the env\n");
+		return -1;
+	}
+	elen = simple_strtoul(config, NULL, 0);
+	found = malloc(strlen(config) + 1);
+	if (!found)
+	{
+		printf("memory allocation failed\n");
+		return -2;
+	}
+	strcpy(found, config);
+	envbuf = malloc(max(elen + 12, CONFIG_ENV_SIZE + 12));
+	if (!envbuf)
+	{
+		printf("memory allocation failed\n");
+		return -2;
+	}
+	ep = (env_t *) (envbuf + 8);
+	ret = env_export(ep);
+	for (i = CONFIG_ENV_SIZE; i < elen; i++) {
+		envbuf[12 + i] = 0xff;
+	}
+	new = crc32(0, ep->data, elen - 4);
+	memcpy(&ep->crc, &new, sizeof(new));
+
+	offset=fdt_path_offset (blob, "/");
+	if(offset >= 0 )
+	{
+		//add 0x1000 (4096) padding bytes, 12 bytes for env header
+		ret=fdt_increase_size(blob, max(elen + 12, CONFIG_ENV_SIZE + 12)+FDT_PAD_BYTES);
+		ret = fdt_setprop(blob, offset, "uboot_env", envbuf, max(elen + 12, CONFIG_ENV_SIZE + 12));
+		if(ret != 0 )
+			printf("fdt_setprop failed [%d]\n", ret);
+	}
+	else
+	{
+		printf("can't append uboot env to dtb, / node not found\n");
+		ret=-4;
+	}
+
+	return ret;
+}
+
+/* Todo: port the remaining code from cfe dtb_set_bootcmd(void) */
+static int set_bootargs(void *blob)
+{
+	char* boot_args;
+	char* extra_args, *mtd_parts, *rootfs;
+	int len = 0;
+
+	boot_args = env_get("bootargs");
+	if (boot_args) {
+		/* fdt_chosen function already override the bootargs.. just print the msg */
+		printf("linux boot command line overriden from bootargs env variable:\n");
+		printf("   %s\n", boot_args);
+	} else
+	{
+		boot_args = malloc(1024);
+		if (boot_args == NULL) {
+			printf("Failed to allocate memory for bootargs!\n");
+			return -1;
+		}
+
+		memset(boot_args, 0x0, 1024);
+
+		/* append the required bootargs saved in the env variables */
+		mtd_parts = env_get("mtdparts");
+		if (mtd_parts)
+			len = snprintf(boot_args, 1024, "mtdparts=%s ", mtd_parts);
+
+		rootfs = env_get("rootfs_opts");
+		if (rootfs)
+			strncat(boot_args, rootfs, 1024-len);
+
+		/* any other argment to append? */
+		extra_args = env_get("+bootargs");
+		if (extra_args) {
+			strncat(boot_args, " ", 1024-strlen(boot_args));
+			strncat(boot_args, extra_args, 1024-strlen(boot_args));
+		}
+		
+		strncat(boot_args, " cma=0M", 1024-strlen(boot_args));
+
+		printf("appending extra boot args to linux boot command line:\n");
+		printf("   %s\n", boot_args);
+		dtb_set_bootargs(blob, boot_args, 1);
+
+		free(boot_args);
+	}
+
+	return 0;
+}
+
+static int is_cma_rsvmem_enabled(void *fdt_ptr)
+{
+	char dt_node_name[64];
+	int len;
+	int ret = 0;
+
+	sprintf(dt_node_name, "/%s/%s%s", DT_RSVD_NODE_STR, DT_RSVD_PREFIX_STR, CMA_BASE_ADDR_STR);
+	if (dtb_get_prop(fdt_ptr, dt_node_name, "reg", &len)) {
+		ret = 1;
+	}
+	return ret;
+}
+
+static void del_all_cma_nodes(void *dtb_ptr)
+{
+	char dt_node_name[64];
+
+	sprintf(dt_node_name, "%s%s", DT_RSVD_PREFIX_STR, CMA_BASE_ADDR_STR);
+	dtb_del_reserved_memory(dtb_ptr, dt_node_name);
+	dtb_del_cma_rsvmem_device(dtb_ptr);
+
+	return;
+}
+
+static int get_dsl_excl_range(void *dtb_ptr, char *name, uint64_t* low, uint64_t* high)
+{
+    int ret = -1;
+
+    ret = dtb_getprop_cma_rsv_param(dtb_ptr, name, "excl-addr-low", low);
+    if (ret != 0)
+        return ret;
+    ret = dtb_getprop_cma_rsv_param(dtb_ptr, name, "excl-addr-high", high);
+
+    return ret;
+}
+
+static void set_reserved_memory(void *dtb_ptr, bd_t *bd)
+{
+	uint64_t mem_end = bd->bi_dram[0].size + bd->bi_dram[0].start;
+	uint64_t rsrv_mem_required = 0;
+	char dt_node_name[64];
+	int use_max_from_env_and_dt = 0;
+	uint64_t size;
+	
+#ifdef CONFIG_RSVD_USE_MAX_FROM_ENV_AND_DT
+	use_max_from_env_and_dt = 1;
+#endif
+	
+	struct mem_reserv_prm {
+		uint64_t size;
+		int      size_in_mb;
+		char *   of_str;
+		char *   env_str;
+		int      from_dt;
+	} params[] = {
+				  /* DSL memory must be reserved first toward end of 256MB */
+				 {0, 0, ADSL_BASE_ADDR_STR, NULL, 0},
+				 {0, 1, PARAM1_BASE_ADDR_STR, ENV_RDP1, 0}, {0, 1, PARAM2_BASE_ADDR_STR, ENV_RDP2, 0}, 
+				 {0, 1, BUFMEM_BASE_ADDR_STR, ENV_BUFMEM, 0}, {0, 1, RNRMEM_BASE_ADDR_STR, ENV_RNRMEM, 0},
+				 {0, 1, DHD_BASE_ADDR_STR, ENV_DHD1, 0}, {0, 1, DHD_BASE_ADDR_STR_1, ENV_DHD2, 0},
+				 {0, 1, DHD_BASE_ADDR_STR_2, ENV_DHD3, 0}, {0, 1, NULL, NULL, 0}}, *params_ptr = params;
+
+	if(!dtb_ptr){
+		printf("RSVD: ERROT  NULL dtb pointer!");
+		return;
+	}
+
+#if defined(CONFIG_BCM63138) || defined(CONFIG_BCM63148)
+	if (mem_end > 256 * SZ_1M)
+		mem_end = 256 * SZ_1M;
+#endif	
+
+	/* We support only alocation using CMA */
+	/* Some device like 63178, 47622 don't use CMA, just exit here */
+	if (!is_cma_rsvmem_enabled(dtb_ptr)){
+		return;
+	}	
+
+	/*compute alocation memory*/
+	while (params_ptr->of_str){
+		size = 0;
+		/* get size from environment */
+		if (params_ptr->env_str){
+			params_ptr->size = env_get_ulong(params_ptr->env_str, 0, 0);
+			if (params_ptr->size_in_mb)
+				params_ptr->size *= SZ_1M;
+		}
+		/* if no environment for the parameter or CONFIG_ENV_NOT_OVERRIDE defined,
+		  	get size from DT */
+		if (!params_ptr->size || use_max_from_env_and_dt){
+			if (dtb_getprop_cma_rsvmem_size(dtb_ptr, params_ptr->of_str, &size) != 0){ 
+				params_ptr->size = 0;
+				printf("RSVD: not found enrty for %s\n", params_ptr->of_str);
+			}
+			else if (strcmp(params_ptr->of_str, ADSL_BASE_ADDR_STR) == 0) {
+				uint64_t adsl_excl_low = 0, adsl_excl_high;
+				if ((get_dsl_excl_range(dtb_ptr, params_ptr->of_str, &adsl_excl_low, &adsl_excl_high) == 0) && (adsl_excl_low != 0)) {
+					printf("adsl_excl_memory_range: low=0x%X high=0x%X rsv_size=0x%X mem_end=0x%X\n", adsl_excl_low, adsl_excl_high, size, mem_end);
+					if ((mem_end > adsl_excl_low) && ((mem_end - size) < adsl_excl_high))
+						mem_end = adsl_excl_low;
+				}
+				else {
+					if( mem_end > 256*SZ_1M )
+						mem_end = 256*SZ_1M;
+				}
+			}
+		}
+	
+		if(size && (!use_max_from_env_and_dt || params_ptr->size < size)){
+				params_ptr->from_dt = 1;
+				params_ptr->size = size;
+		}
+		
+		if (!params_ptr->size){
+			params_ptr++;
+			continue;
+		}		
+			
+		params_ptr->size = ALIGN(params_ptr->size, SZ_1M);
+
+		/* make sure we don't reserve too much memory in total that can cause
+		 * conflict with linux. Print big warining */
+		if ((rsrv_mem_required + params_ptr->size) > (mem_end - (32 * SZ_1M))) {
+			/* out of the range, worning and skip it */
+			printf("RSVD: Not enough memory %s skipped!\n", params_ptr->of_str);
+			printf("Requested 0x%llx already alocated 0x%llx, mem_end 0x%llx\n",
+			       params_ptr->size, rsrv_mem_required, mem_end);
+			dtb_del_cma_rsvmem(dtb_ptr, params_ptr->of_str);
+			params_ptr->size = 0;
+		}
+		else
+			rsrv_mem_required += params_ptr->size;
+		
+		params_ptr++;
+	}
+	
+	if (rsrv_mem_required == 0 ) {
+		/* remove the cma nodes if no rsvmem is needed */
+		del_all_cma_nodes(dtb_ptr);
+		printf("RSVD: No CMA memory reserved\n");
+		return;
+	}
+		
+	/* update DTB and environmet */
+	params_ptr = params;
+	
+	while (params_ptr->of_str){	
+		if (!params_ptr->size){
+			params_ptr++;
+			continue;
+		}
+		if(!params_ptr->from_dt){
+			/* update DT */
+			dtb_setprop_cma_rsvmem_size(dtb_ptr, params_ptr->of_str, params_ptr->size);
+		}
+		else if (params_ptr->env_str){
+			/* propogate in env, make it visible in linux proc */
+			env_set_ulong(params_ptr->env_str, params_ptr->size_in_mb?params_ptr->size/SZ_1M:params_ptr->size);
+		}
+		printf("RSVD: Allocated for %s    %uMB\n", params_ptr->of_str, (uint32_t)(params_ptr->size/SZ_1M));
+		params_ptr++;
+	}
+	
+	/* kernel want 4MB aligned in both start address and size
+	   mem_end already aligned so need care only of rsrv_mem_required*/
+	rsrv_mem_required = ALIGN(rsrv_mem_required, SZ_4M);
+	
+	sprintf(dt_node_name, "%s%s", DT_RSVD_PREFIX_STR, CMA_BASE_ADDR_STR);
+	if (!dtb_set_reserved_memory(dtb_ptr, dt_node_name, mem_end - rsrv_mem_required, rsrv_mem_required))
+		printf("RSVD: Total 0x%08x bytes CMA reserved memory @ 0x%08x\n",
+		   (uint32_t)rsrv_mem_required, (uint32_t)(mem_end - rsrv_mem_required));
+	else
+		printf("RSVD: ERROR set CMA reserved memory!\n");
+}
+
+static void set_flash_node(void* fdt_addr)
+{
+	if (bcmbca_get_boot_device() != BOOT_DEVICE_SPI)
+		fdt_status_disabled_by_alias(fdt_addr, "spinand0");
+
+	if (bcmbca_get_boot_device() != BOOT_DEVICE_NAND)
+		fdt_status_disabled_by_alias(fdt_addr, "nand0")	;  
+
+	if (bcmbca_get_boot_device() != BOOT_DEVICE_NOR)
+		fdt_status_disabled_by_alias(fdt_addr, "spinor0")	;  
+}
+
+int ft_system_setup(void *blob, bd_t *bd)
+{
+	int ret;
+
+	set_flash_node(blob);
+	ft_update_cpu_nodes(blob, bd);
+	set_reserved_memory(blob, bd);
+	ret = set_bootargs(blob);
+	ret |= set_uboot_env(blob);
+	ret |= set_uboot_version(blob);
+	ret |= set_sec_exports(blob);
+
+	return ret;
+}
+
+static inline char * dev_to_string(int bdevice)
+{
+	char *device_str=NULL;
+	switch(bdevice)
+	{
+		case BOOT_DEVICE_NAND:
+		case BOOT_DEVICE_SPI:	/* SPI NAND */	  
+			device_str=FLASH_DEV_STR_NAND;
+			break;
+
+		case BOOT_DEVICE_NOR:
+			device_str=FLASH_DEV_STR_SPINOR;
+			break;
+		case BOOT_DEVICE_MMC1:
+		case BOOT_DEVICE_MMC2:
+		case BOOT_DEVICE_MMC2_2:
+			device_str=FLASH_DEV_STR_EMMC;
+			break;
+		
+	}
+	return device_str;
+}
+
+void update_uboot_fdt(void *fdt_addr, tpl_params *tplp)
+{
+	int offset, regsize;
+	uint64_t total_size;
+#if defined(CONFIG_ARM64)
+	uint64_t reg[4];
+	uint64_t split_size = PHYS_SDRAM_1_SIZE;
+#if defined(PHYS_SDRAM_2)	
+	uint64_t second_base = PHYS_SDRAM_2;
+#else
+	uint64_t second_base = PHYS_SDRAM_1_SIZE;	
+#endif
+#else
+	uint32_t reg[2];
+#endif
+
+	total_size = ((uint64_t)tplp->ddr_size)*SZ_1M;
+	
+	/* Fixup memory offsets */
+	offset=fdt_path_offset (fdt_addr, "/memory");
+	if(offset >= 0)
+	{
+#if defined(CONFIG_ARM64)
+		reg[0] = cpu_to_fdt64(0);
+		if (total_size <= split_size) {
+			reg[1] = cpu_to_fdt64(total_size);
+			regsize = 16;
+		} else {
+		  	reg[1] = cpu_to_fdt64(split_size);
+			reg[2] = cpu_to_fdt64(second_base);
+			reg[3] = cpu_to_fdt64(total_size-split_size);
+			regsize = 32;
+		}
+#else
+		reg[0] = cpu_to_fdt32(0);
+		reg[1] = cpu_to_fdt32(total_size);
+		regsize = sizeof(reg);
+#endif
+		if(fdt_setprop(fdt_addr, offset, "reg", reg, regsize))
+		{
+			printf("Could not set memory node in the fdt, device may not boot properly\n");
+		}
+	}
+
+	/*get boot device from tplparams */
+	offset=fdt_path_offset (fdt_addr, "/chosen");
+	if(offset >= 0)
+	{
+		char *dev_string=dev_to_string(tplp->boot_device);
+		if(dev_string != NULL)
+		{
+			if(fdt_setprop_string(fdt_addr, offset, "boot_device", dev_string))
+			{
+				printf("Could not set boot device node in the fdt, device may not boot properly\n");
+			}
+		}
+
+#if defined(CONFIG_BCMBCA_PMC)
+		char *avs_disable =
+			find_spl_env_val(tplp->environment, ENV_AVS_DISABLE);
+		if (avs_disable && *avs_disable == '1' &&
+			fdt_setprop(fdt_addr, offset, ENV_AVS_DISABLE,
+				avs_disable, sizeof(*avs_disable)))
+		{
+			printf("Could not set avs_disable=1 in the fdt, "
+					"device may not boot properly\n");
+		}
+#endif
+	}
+
+  	//other parameters???
+	set_flash_node(fdt_addr);
+}
+
+__attribute__ ((weak))
+int get_nr_cpus()
+{
+	return -1;
+}
+
+#define CPU_STR "/cpus/cpu@"
+
+void ft_update_cpu_nodes(void *blob, bd_t * bd)
+{
+	int nr_cpus=get_nr_cpus(), cpu=0;
+	int offset;
+	char cpu_node_str[30];
+
+	if(nr_cpus >= 1)
+	{
+		for( cpu = QUAD_CPUS-1; cpu >= nr_cpus; cpu--)
+		{
+			if(snprintf(cpu_node_str, sizeof(cpu_node_str), "%s%d", CPU_STR, cpu) != -1)
+			{
+				offset = fdt_path_offset(blob, cpu_node_str);
+				if (offset >= 0)
+				{
+					fdt_del_node(blob, offset);
+				}
+			}
+		}
+	}
+
+	return;
+}
diff --git a/arch/arm/mach-bcmbca/bcmbca_ddr/Makefile b/arch/arm/mach-bcmbca/bcmbca_ddr/Makefile
new file mode 100644
index 0000000000..c80812f6e0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcmbca_ddr/Makefile
@@ -0,0 +1 @@
+# This file is intentionally blank
diff --git a/arch/arm/mach-bcmbca/bcmbca_dpfe/Kconfig b/arch/arm/mach-bcmbca/bcmbca_dpfe/Kconfig
new file mode 100644
index 0000000000..472d861d89
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcmbca_dpfe/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+config MHS_VER
+	string "MHS version"
+	default "2p2" if BCM47622
+	default "4p3" if BCM63146
+	default "5p3" if BCM4912
+
+config DPFE_SEGSIZE
+	hex "dpfe segment size"
+	default 0x500c
+
+config MEMC_VER
+	string "MEMC version"
+	default "4p50" if BCM47622
+	default "5p1" if BCM63146 || BCM4912
diff --git a/arch/arm/mach-bcmbca/bcmbca_dpfe/Makefile b/arch/arm/mach-bcmbca/bcmbca_dpfe/Makefile
new file mode 100644
index 0000000000..c80812f6e0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcmbca_dpfe/Makefile
@@ -0,0 +1 @@
+# This file is intentionally blank
diff --git a/arch/arm/mach-bcmbca/bcmbca_nand_spl.c b/arch/arm/mach-bcmbca/bcmbca_nand_spl.c
new file mode 100644
index 0000000000..9f3cd6c204
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcmbca_nand_spl.c
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <spl.h>
+
+#include <asm/arch/misc.h>
+
+#include "bca_common.h"
+#include "bcmbca_nand_spl.h"
+#include "brcmnand_spl.h"
+#include <linux/mtd/spinand_mini.h>
+
+
+u32 (*get_block_size)(void);
+u32 (*get_page_size)(void);
+u64 (*get_total_size)(void);
+int (*read_block)(int block, int offset, u8 *dst, u32 len);
+int (*is_bad_block)(int block);
+
+
+int type = BOOT_DEVICE_NAND;
+
+
+void nand_init(void)
+{
+	static int nand_init = 0;
+
+	/* return if already initalized */
+	if (nand_init)
+		return;
+
+	type = bcmbca_get_boot_device();
+
+	switch (type)
+	{
+#if defined(CONFIG_MTD_SPI_NAND)
+		case BOOT_DEVICE_SPI:
+			spinandmini_init();
+			get_page_size = spinandmini_get_page_size;
+			get_block_size = spinandmini_get_block_size;
+			get_total_size = spinandmini_get_total_size;
+			read_block = spinandmini_read_buf;
+			is_bad_block = spinandmini_is_bad_block;
+			break;
+#endif
+
+#if defined(CONFIG_NAND_BRCMNAND)
+		case BOOT_DEVICE_NAND:			
+		default:
+			brcmnand_init();
+			get_page_size = brcmnand_get_page_size;
+			get_block_size = brcmnand_get_block_size;
+			get_total_size = brcmnand_get_total_size;
+			read_block = brcmnand_read_buf;
+			is_bad_block = brcmnand_is_bad_block;
+			break;
+#endif
+	}
+
+	nand_init = 1;
+
+	return;
+}
+
+void nand_deselect(void)
+{
+}
+
+u32 nand_spl_get_page_size(void)
+{
+	return (*get_page_size)();
+}
+
+u32 nand_spl_get_blk_size(void)
+{
+	return (*get_block_size)();
+}
+
+u64 nand_spl_get_total_size(void)
+{
+	return (*get_total_size)();
+}
+
+__weak int nand_is_bad_block(unsigned int blk)
+{
+	return (*is_bad_block)(blk);
+}
+
+int nand_spl_read_block(int block, int offset, int len, void *dst)
+{
+	int ret;
+  
+	ret = (*read_block)(block, offset, dst, len);
+	return (ret > 0) ? 0 : ret;
+}
+
+int nand_spl_load_image(u32 offs, u32 size, void *dst)
+{
+	u32 block, lastblock, block_size;
+	u32 block_offset, read_size;
+	int ret = 0;
+
+	block_size = nand_spl_get_blk_size();
+	/* offs has to be aligned to a page address! */
+	block = offs / block_size;
+	lastblock = (offs + size - 1) / block_size;
+	block_offset = offs % block_size;
+	read_size = block_size - block_offset;
+	if (read_size > size)
+		read_size = size;
+
+	if (nand_is_bad_block(block))
+		return -EIO;
+
+	while (block <= lastblock) {
+		/* Skip bad blocks */
+		if (!nand_is_bad_block(block)) {
+			ret = nand_spl_read_block(block, block_offset, read_size, dst);
+			if (ret < 0) {
+				printf("read block %d offset 0x%x size 0x%x dst %p failed ret %d\n",
+				       block, block_offset, read_size, dst, ret);
+				return -EIO;
+			}
+		} else {
+			printf("nand_spl_load_image skip bad block %d\n", block);
+			lastblock++;
+			block++;
+			continue;
+		}
+
+		size -= read_size;
+		if (size == 0)
+			break;
+
+		dst += read_size;
+		read_size = block_size;
+		if (read_size > size)
+			read_size = size;
+		block_offset = 0;
+		block++;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-bcmbca/ddrinit_dpfe.c b/arch/arm/mach-bcmbca/ddrinit_dpfe.c
new file mode 100644
index 0000000000..c6a1263c16
--- /dev/null
+++ b/arch/arm/mach-bcmbca/ddrinit_dpfe.c
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/ddr.h>
+
+#include "spl_ddrinit.h"
+#include "ddrinit_dpfe.h"
+#include "boot_blob.h"
+#include "tpl_params.h"
+
+typedef int (*load_dpfe_seg_fun)(dpfe_seg_param* param);
+
+/*
+This is a stub function for jtag load.
+cmm script will have a breakpoint, stop here and load the next stage of the dpfe
+*/
+static int load_dpfe_segment_stub(dpfe_seg_param* param)
+{
+static int last_seg=0;
+
+	/* cmm script sets this to 1 when it reaches the last stage of dpfe */
+	return last_seg;
+}
+static int load_dpfe_segment(dpfe_seg_param* param)
+{
+	int last_seg = -1, rc;
+	int size = param->buf_size;
+	uint32_t magic = BP_DDR_IS_DDR4(param->mcb_sel) ? DPFE_DDR4_TABLE_MAGIC|param->seg_id : DPFE_DDR3_TABLE_MAGIC|param->seg_id;
+
+	if (param->seg_buf && param->buf_size) {
+		rc = load_boot_blob(magic, param->seg_id, param->seg_buf, &size);
+		if (rc == BOOT_BLOB_NOT_IN_HASTTBL) { /* seg id not in has table. try with last seg id flag */
+			size = param->buf_size;
+			rc = load_boot_blob(magic|0x80, param->seg_id|0x80, param->seg_buf, &size);
+			if (rc == BOOT_BLOB_SUCCESS)
+				last_seg = 1;
+			else
+				last_seg = rc;
+		} else
+			last_seg = rc;
+	}
+	debug("load_dpfe_segment %d return %d\n", param->seg_id, last_seg);
+	return last_seg;
+}
+
+
+/* return 1 if there is alias, 0 no alias.  memsize in MB */
+static int memc_alias_test(uint32_t memsize)
+{
+	volatile uint32_t *base_addr;
+	volatile uint32_t *test_addr;
+	uint64_t test_size, total_size;
+#ifdef CONFIG_BCMBCA_IKOS
+	uint32_t data;
+#endif
+	int ret = 0;
+
+	total_size = ((uint64_t) (memsize)) << 20;
+	base_addr = (volatile uint32_t *)((uintptr_t) CONFIG_SYS_SDRAM_BASE);
+
+	for (test_size = 256; test_size < total_size;
+	     test_size = test_size << 1) {
+		test_addr =
+		    (volatile uint32_t *)((uintptr_t) base_addr +
+					  (uintptr_t) test_size);
+#if defined(PHYS_SDRAM_2)
+		/* if we are over the lower memory region from 0 to 2GB, we shift to the upper memory region */
+		if (test_size >= PHYS_SDRAM_1_SIZE)
+			test_addr =
+			    (volatile uint32_t *)((uintptr_t) test_addr +
+						  PHYS_SDRAM_1_SIZE);
+#endif
+#ifdef CONFIG_BCMBCA_IKOS
+		data = *test_addr;
+#endif
+		*base_addr = 0;
+		*test_addr = 0xaa55beef;
+		if (*base_addr == *test_addr) {
+			printf("alias detected at 0x%p\n", test_addr);
+			ret = 1;
+			break;
+		}
+		/* check base addr and make sure it does not get overriden */
+		if (*base_addr != 0x0) {
+			printf("alias test at 0x%p corrupted base 0x%x 0x%x\n",
+			       test_addr, *base_addr, *test_addr);
+			ret = 1;
+			break;
+		}
+#ifdef CONFIG_BCMBCA_IKOS
+		*test_addr = data;
+#endif
+	}
+
+	return ret;
+}
+
+static int memory_test_range(uint32_t *addr, uint32_t size)
+{
+	uint32_t *temp;
+	int i, ret = 0;
+ 	uint32_t data;
+
+  	for (temp = addr, i = 0; i < size/sizeof(uint32_t); i++)
+		*temp++ = i;
+
+	for (temp = addr, i = 0; i < size/sizeof(uint32_t); i++) {
+		data = *temp++;
+		if (data != i)
+			break;
+	}
+
+	if (i != size/sizeof(uint32_t)) {
+		printf("DDR test failed at 0x%p\n\r", addr+i);	  
+		ret = -1;
+	}
+
+	return ret;
+}
+
+/* return 1 if there is error, 0 no error.  memsize in MB */
+static int memc_memory_test(uint32_t memsize)
+{
+	uint32_t *addr;
+	int ret = 0;
+	uint64_t total_size;
+
+	total_size = ((uint64_t) (memsize)) << 20;
+
+	addr = (uint32_t *)CONFIG_SYS_SDRAM_BASE;
+	ret = memory_test_range(addr, SZ_4K);
+#if defined(PHYS_SDRAM_2)
+	if (total_size > PHYS_SDRAM_1_SIZE) {
+		addr = (uint32_t *)PHYS_SDRAM_2;
+		total_size -= PHYS_SDRAM_1_SIZE;
+		while ((int64_t)total_size) {
+			ret |= memory_test_range(addr, SZ_4K);
+			total_size -= SZ_1G;
+			addr = (uint32_t*)((uint64_t)addr + SZ_1G);
+		}
+	}
+#endif
+	if (!ret)
+		printf("DDR test done successfully\n\r");
+	else {
+		ret = -2;
+	}
+
+	return ret;
+}
+
+
+int ddr_init_dpfe(ddr_init_param * ddrinit_params)
+{
+	uint32_t ret, memcfg, ddr_size;
+	int is_safemode;
+	uint8_t *seg_buf = NULL;
+	int seg_id, last_seg;
+	dpfe_seg_param seg_params;
+	dpfe_param dpfe_params;
+	dpfe_func run_dpfe;
+	load_dpfe_seg_fun load_dpfe_segment_p=load_dpfe_segment;
+
+
+	if (IS_JTAG_LOADED(boot_params))
+	{
+		load_dpfe_segment_p=load_dpfe_segment_stub;
+	}
+
+	is_safemode = ddrinit_params->safe_mode;
+	memcfg = ddrinit_params->mcb_sel;
+
+	seg_buf = (void *)ddrinit_params->dpfe_segbuf;
+	run_dpfe = (dpfe_func)ddrinit_params->dpfe_stdalone;
+
+	dpfe_params.mcb = (uint32_t *) ddrinit_params->mcb;
+#ifdef CONFIG_BCMBCA_DDRC_SCRAMBLER
+	dpfe_params.seed = ddrinit_params->seed;
+#endif
+	dpfe_params.ddr_size = &ddr_size;
+	dpfe_params.seg_param = &seg_params;
+	dpfe_params.dpfe_option = 0;
+
+	if (is_safemode)
+		dpfe_params.dpfe_option |= DPFE_OPTION_SAFEMODE;
+
+	seg_id = last_seg = 0;
+	dpfe_params.dpfe_option |= DPFE_OPTION_SEG_FIRST;
+
+	seg_params.seg_buf = seg_buf;
+	seg_params.mcb_sel = memcfg;
+	seg_params.buf_size = CONFIG_DPFE_SEGSIZE;;
+  
+	while (!last_seg) {
+		seg_params.seg_id = seg_id;
+		last_seg = load_dpfe_segment_p(&seg_params);
+		if (last_seg < 0) {
+			printf("failed to load dpfe segment %d!\n\r", seg_id);
+			return -1;
+		}
+		if (last_seg)
+			dpfe_params.dpfe_option |= DPFE_OPTION_SEG_LAST;
+
+		ret = run_dpfe(&dpfe_params);
+		if (ret < 0) {
+			return -1;
+		}
+
+		if (ret > 0) {
+			printf("shmoo finish early at segment %d!\n\r", seg_id);
+			break;
+		}
+
+		dpfe_params.dpfe_option &= ~DPFE_OPTION_SEG_MASK;
+		seg_id++;
+	}
+
+	/* make sure configure register write are really carried over to target block */
+	__asm__ __volatile__("dsb	sy");
+	__asm__ __volatile__("isb");
+
+	/* get the ddr size in mega bytes */
+	if (ddrinit_params->ddr_size != NULL)
+		*ddrinit_params->ddr_size = ddr_size;
+
+
+	/* Make sure it is configured size is not larger the actual size */
+	if (is_safemode == 0) {
+		if (memc_alias_test(ddr_size)) {
+			printf
+			    ("\nMemory alias detected. Probably wrong memory size is specified or memory subsystem not working\n");
+			return -3;
+		}
+	}
+
+	if ((ret = memc_memory_test(ddr_size)))
+		return ret;
+
+	return ret;
+}
diff --git a/arch/arm/mach-bcmbca/ddrinit_reg.c b/arch/arm/mach-bcmbca/ddrinit_reg.c
new file mode 100644
index 0000000000..32bddcee13
--- /dev/null
+++ b/arch/arm/mach-bcmbca/ddrinit_reg.c
@@ -0,0 +1,491 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/arch/ddr.h>
+
+#include "spl_ddrinit.h"
+
+/*
+	op - operation type
+		0 - read, 32 bit read operation
+		1 - write, 32 bit write operation
+		2 - poll read, read until the value read mactches read_value&mask
+*/
+#define REG_OP_READ	0x0
+#define REG_OP_WRITE	0x1
+#define REG_OP_POLL	0x2
+
+typedef struct _reg_entry {
+	uint32_t op;
+	uint32_t addr;
+	uint32_t mask;
+	uint32_t value;
+} reg_entry;
+
+reg_entry reg_table[] = {
+#ifdef CONFIG_BCM63146
+        {1, 0x800400b8, 0, 0x12345678},
+        {0, 0x800400b8, 0, 0x12345678},
+        {0, 0x80040e88, 0, 0x00030003},
+        {1, 0x80040e88, 0, 0x80030003},
+        {0, 0x80040914, 0, 0x00000011},
+        {0, 0x80040008, 0, 0x01000000},
+        {1, 0x80040008, 0, 0x01000000},
+        {1, 0x8004091c, 0, 0x00000307},
+        {1, 0x80060364, 0, 0x00000001},
+        {1, 0x80060228, 0, 0x02000000},
+        {1, 0x8006022c, 0, 0x00000a0e},
+        {1, 0x80060230, 0, 0x00000000},
+        {1, 0x80060030, 0, 0x00000000},
+        {1, 0x8006002c, 0, 0x00000000},
+        {1, 0x80060014, 0, 0x00000003},
+        {1, 0x80060018, 0, 0x00000000},
+        {1, 0x80060020, 0, 0x00000032},
+        {1, 0x80060024, 0, 0x02a99999},
+        {0, 0x80060034, 0, 0x00000001},
+        {1, 0x80060034, 0, 0x00000003},
+        {1, 0x80060044, 0, 0x00000101},
+        {1, 0x80060018, 0, 0x00000001},
+        {0, 0x8006000c, 0, 0x00004001},
+        {1, 0x80060018, 0, 0x00000001},
+        {0, 0x80040008, 0, 0x01000000},
+        {1, 0x80040008, 0, 0x01000000},
+        {1, 0x80040008, 0, 0x01000200},
+        {1, 0x8006002c, 0, 0x00000000},
+        {0, 0x8006035c, 0, 0x00000011},
+        {1, 0x8006035c, 0, 0x00000010},
+        {1, 0x80060064, 0, 0x00072020},
+        {0, 0x80060388, 0, 0x07f8f0f0},
+        {1, 0x80060388, 0, 0x27f8f0f0},
+        {0, 0x8006035c, 0, 0x00000010},
+        {1, 0x8006035c, 0, 0x00000000},
+        {1, 0x8006035c, 0, 0x00000008},
+        {1, 0x8006034c, 0, 0x00000000},
+        {1, 0x80060354, 0, 0x00000000},
+        {1, 0x80060344, 0, 0x00000000},
+        {1, 0x8006020c, 0, 0x00031bff},
+        {1, 0x80060210, 0, 0x00031bff},
+        {1, 0x80060078, 0, 0x00031bff},
+        {1, 0x8006007c, 0, 0x00031bff},
+        {1, 0x80060720, 0, 0x00031bff},
+        {1, 0x80060724, 0, 0x00031bff},
+        {1, 0x80060728, 0, 0x00031bff},
+        {1, 0x80060920, 0, 0x00031bff},
+        {1, 0x80060924, 0, 0x00031bff},
+        {1, 0x80060928, 0, 0x00031bff},
+        {0, 0x80060220, 0, 0x40000002},
+        {1, 0x80060220, 0, 0x40000002},
+        {0, 0x80060050, 0, 0x0000000c},
+        {1, 0x80060050, 0, 0x0000000c},
+        {0, 0x80060068, 0, 0x00180000},
+        {1, 0x80060068, 0, 0x00180000},
+        {1, 0x80060368, 0, 0x00001000},
+        {0, 0x800606d0, 0, 0x00000000},
+        {1, 0x80060734, 0, 0x0000083c},
+        {0, 0x800608d0, 0, 0x00000000},
+        {1, 0x80060934, 0, 0x0000083c},
+        {1, 0x80060380, 0, 0x00000000},
+        {1, 0x80060718, 0, 0x00000000},
+        {1, 0x80060918, 0, 0x00000000},
+        {0, 0x8006072c, 0, 0x00020000},
+        {1, 0x8006072c, 0, 0x00020000},
+        {1, 0x8006092c, 0, 0x00020000},
+        {1, 0x80060730, 0, 0x001241c3},
+        {1, 0x80060930, 0, 0x001241c3},
+        {0, 0x8006071c, 0, 0x00c0000a},
+        {1, 0x8006071c, 0, 0x0000000a},
+        {1, 0x8006091c, 0, 0x0000000a},
+        {0, 0x80060388, 0, 0x27f8f0f0},
+        {1, 0x80060388, 0, 0x07f8f0f0},
+        {1, 0x80060364, 0, 0x00000001},
+        {0, 0x80060364, 0, 0x00000003},
+        {0, 0x80060388, 0, 0x07f8f0f0},
+        {1, 0x80060388, 0, 0x27f8f0f0},
+        {0, 0x80060388, 0, 0x27f8f0f0},
+        {1, 0x80060388, 0, 0x2ff8f0f0},
+        {0, 0x8006038c, 0, 0x00000000},
+        {1, 0x8006038c, 0, 0x00000040},
+        {0, 0x80060304, 0, 0x00000000},
+        {0, 0x80060304, 0, 0x00000000},
+        {1, 0x800602d4, 0, 0xe0820228},
+        {1, 0x800602e0, 0, 0x80820228},
+        {1, 0x800602ec, 0, 0x60820228},
+        {0, 0x80060304, 0, 0x00000002},
+        {0, 0x80060304, 0, 0x00000002},
+        {1, 0x80060304, 0, 0x00000002},
+        {1, 0x800602d4, 0, 0xe0830000},
+        {1, 0x800602e0, 0, 0x80830000},
+        {1, 0x800602ec, 0, 0x60830000},
+        {0, 0x80060304, 0, 0x00000002},
+        {0, 0x80060304, 0, 0x00000002},
+        {1, 0x80060304, 0, 0x00000002},
+        {1, 0x800602d4, 0, 0xe0810006},
+        {1, 0x800602e0, 0, 0x80810006},
+        {1, 0x800602ec, 0, 0x60810006},
+        {0, 0x80060304, 0, 0x00000002},
+        {0, 0x80060304, 0, 0x00000002},
+        {1, 0x80060304, 0, 0x00000002},
+        {1, 0x800602d4, 0, 0xe0801124},
+        {1, 0x800602e0, 0, 0x80801124},
+        {1, 0x800602ec, 0, 0x60801124},
+        {0, 0x80060304, 0, 0x00000002},
+        {0, 0x80060304, 0, 0x00000002},
+        {1, 0x80060304, 0, 0x00000002},
+        {1, 0x800602d4, 0, 0xe0300400},
+        {1, 0x800602e0, 0, 0x80300400},
+        {1, 0x800602ec, 0, 0x60300400},
+        {1, 0x80060364, 0, 0x00000000},
+        {0, 0x80060364, 0, 0x00000000},
+        {0, 0x80060308, 0, 0x00011124},
+        {0, 0x8006030c, 0, 0x00010006},
+        {0, 0x80060310, 0, 0x00010228},
+        {0, 0x80060314, 0, 0x00010000},
+        {1, 0x80040918, 0, 0x000003f1},
+        {0, 0x80040008, 0, 0x01000200},
+        {1, 0x80040008, 0, 0x01000600},
+        {1, 0x800403a8, 0, 0x00000011},
+        {1, 0x800403b8, 0, 0x0000000a},
+        {1, 0x80040390, 0, 0x100f0e0d},
+        {1, 0x8004038c, 0, 0x14131211},
+        {1, 0x80040388, 0, 0x18171615},
+        {1, 0x80040384, 0, 0x001b1a19},
+        {1, 0x80040380, 0, 0x00000000},
+        {1, 0x800403a4, 0, 0x000c0b0a},
+	/* SKIP MEMC SRAM disable. Used by MMU table */
+#if 0
+        {0, 0x80040310, 0, 0x80000001},
+        {1, 0x80040310, 0, 0x00000001},
+#endif
+        {1, 0x8004092c, 0, 0x000e0a0e},
+        {1, 0x80040930, 0, 0x00040007},
+        {1, 0x80040934, 0, 0x00000000},
+        {1, 0x80040938, 0, 0x26000e24},
+        {1, 0x8004093c, 0, 0x00081000},
+        {1, 0x80040940, 0, 0x00000000},
+        {1, 0x80040944, 0, 0x00000408},
+        {1, 0x80040948, 0, 0x0002000b},
+        {1, 0x8004094c, 0, 0x01560056},
+        {1, 0x80040954, 0, 0x40001100},
+        {1, 0x80040958, 0, 0x008d0118},
+        {0, 0x80040048, 0, 0x04100002},
+        {1, 0x80040048, 0, 0x04100002},
+        {1, 0x8004004c, 0, 0x00000380},
+        {1, 0x80040050, 0, 0x00000000},
+        {1, 0x80040054, 0, 0x08080808},
+        {1, 0x80040058, 0, 0x000000e4},
+        {0, 0x80040908, 0, 0x00000000},
+        {1, 0x80040908, 0, 0x00000001},
+        {0, 0x80040910, 0, 0x00000000},
+        {1, 0x80040910, 0, 0x00000005},
+        {0, 0x80040008, 0, 0x01000600},
+        {1, 0x80040008, 0, 0x81000700},
+        {0, 0x80040008, 0, 0x81000700},
+	{0, 0, 0, 0x9},   /* hijack last entry value for total ddr size */
+#endif
+
+#ifdef CONFIG_BCM4912
+	/* 2x4096Mbit DDR3 1067Mz */
+        {1, 0x800400b8, 0, 0x12345678},
+        {0, 0x800400b8, 0, 0x12345678},
+        {0, 0x80040e88, 0, 0x00030003},
+        {1, 0x80040e88, 0, 0x80030003},
+        {0, 0x80040914, 0, 0x00000011},
+        {0, 0x80040008, 0, 0x01000000},
+        {1, 0x80040008, 0, 0x01000000},
+        {1, 0x8004091c, 0, 0x00000307},
+        {1, 0x80060364, 0, 0x00000001},
+        {1, 0x80060228, 0, 0x00000000},
+        {1, 0x8006022c, 0, 0x00000a0e},
+        {1, 0x80060230, 0, 0x00000000},
+        {1, 0x80060030, 0, 0x00000000},
+        {1, 0x8006002c, 0, 0x00000000},
+        {1, 0x80060014, 0, 0x00000003},
+        {1, 0x80060018, 0, 0x00000000},
+        {1, 0x80060020, 0, 0x00000032},
+        {1, 0x80060024, 0, 0x02a99999},
+        {1, 0x80060044, 0, 0x00000101},
+        {1, 0x80060018, 0, 0x00000001},
+        {0, 0x8006000c, 0, 0x00004001},
+        {1, 0x80060018, 0, 0x00000003},
+        {0, 0x80040008, 0, 0x01000000},
+        {1, 0x80040008, 0, 0x01000000},
+        {1, 0x80040008, 0, 0x01000200},
+        {1, 0x8006002c, 0, 0x00000000},
+        {0, 0x8006035c, 0, 0x00000011},
+        {1, 0x8006035c, 0, 0x00000010},
+        {1, 0x80060064, 0, 0x00072020},
+        {0, 0x80060388, 0, 0x07f8f0f0},
+        {1, 0x80060388, 0, 0x27f8f0f0},
+        {0, 0x8006035c, 0, 0x00000010},
+        {1, 0x8006035c, 0, 0x00000000},
+        {1, 0x8006035c, 0, 0x00000008},
+        {1, 0x8006034c, 0, 0x00000000},
+        {1, 0x80060354, 0, 0x00000000},
+        {1, 0x80060344, 0, 0x00000000},
+        {1, 0x8006020c, 0, 0x00031bff},
+        {1, 0x80060210, 0, 0x00031bff},
+        {1, 0x80060078, 0, 0x00031bff},
+        {1, 0x8006007c, 0, 0x00031bff},
+        {1, 0x80060720, 0, 0x00031bff},
+        {1, 0x80060724, 0, 0x00031bff},
+        {1, 0x80060728, 0, 0x00031bff},
+        {1, 0x80060920, 0, 0x00031bff},
+        {1, 0x80060924, 0, 0x00031bff},
+        {1, 0x80060928, 0, 0x00031bff},
+        {1, 0x80060b20, 0, 0x00031bff},
+        {1, 0x80060b24, 0, 0x00031bff},
+        {1, 0x80060b28, 0, 0x00031bff},
+        {1, 0x80060d20, 0, 0x00031bff},
+        {1, 0x80060d24, 0, 0x00031bff},
+        {1, 0x80060d28, 0, 0x00031bff},
+        {0, 0x80060220, 0, 0x40000002},
+        {1, 0x80060220, 0, 0x40000002},
+        {0, 0x80060050, 0, 0x0000000c},
+        {1, 0x80060050, 0, 0x0000000c},
+        {0, 0x80060068, 0, 0x00180000},
+        {1, 0x80060068, 0, 0x00180000},
+        {1, 0x80060368, 0, 0x00001000},
+        {0, 0x800606d0, 0, 0x00000000},
+        {1, 0x80060734, 0, 0x0000083c},
+        {0, 0x800608d0, 0, 0x00000000},
+        {1, 0x80060934, 0, 0x0000083c},
+        {0, 0x80060ad0, 0, 0x00000000},
+        {1, 0x80060b34, 0, 0x0000083c},
+        {0, 0x80060cd0, 0, 0x00000000},
+        {1, 0x80060d34, 0, 0x0000083c},
+        {1, 0x80060380, 0, 0x00000000},
+        {1, 0x80060718, 0, 0x00000000},
+        {1, 0x80060918, 0, 0x00000000},
+        {1, 0x80060b18, 0, 0x00000000},
+        {1, 0x80060d18, 0, 0x00000000},
+        {0, 0x8006072c, 0, 0x00020000},
+        {1, 0x8006072c, 0, 0x00020000},
+        {1, 0x8006092c, 0, 0x00020000},
+        {1, 0x80060b2c, 0, 0x00020000},
+        {1, 0x80060d2c, 0, 0x00020000},
+        {1, 0x80060730, 0, 0x001241c3},
+        {1, 0x80060930, 0, 0x001241c3},
+        {1, 0x80060b30, 0, 0x001241c3},
+        {1, 0x80060d30, 0, 0x001241c3},
+        {0, 0x8006071c, 0, 0x00c0000a},
+        {1, 0x8006071c, 0, 0x0000000a},
+        {1, 0x8006091c, 0, 0x0000000a},
+        {1, 0x80060b1c, 0, 0x0000000a},
+        {1, 0x80060d1c, 0, 0x0000000a},
+        {0, 0x80060388, 0, 0x27f8f0f0},
+        {1, 0x80060388, 0, 0x07f8f0f0},
+        {1, 0x80060364, 0, 0x00000001},
+        {0, 0x80060364, 0, 0x00000003},
+        {0, 0x80060388, 0, 0x07f8f0f0},
+        {1, 0x80060388, 0, 0x27f8f0f0},
+        {0, 0x80060388, 0, 0x27f8f0f0},
+        {1, 0x80060388, 0, 0x2ff8f0f0},
+        {0, 0x8006038c, 0, 0x00000000},
+        {1, 0x8006038c, 0, 0x00000040},
+        {0, 0x80060304, 0, 0x00000000},
+        {0, 0x80060304, 0, 0x00000000},
+        {1, 0x800602d4, 0, 0xe0820228},
+        {1, 0x800602e0, 0, 0x80820228},
+        {1, 0x800602ec, 0, 0x60820228},
+        {0, 0x80060304, 0, 0x00000002},
+        {0, 0x80060304, 0, 0x00000002},
+        {1, 0x80060304, 0, 0x00000002},
+        {1, 0x800602d4, 0, 0xe0830000},
+        {1, 0x800602e0, 0, 0x80830000},
+        {1, 0x800602ec, 0, 0x60830000},
+        {0, 0x80060304, 0, 0x00000002},
+        {0, 0x80060304, 0, 0x00000002},
+        {1, 0x80060304, 0, 0x00000002},
+        {1, 0x800602d4, 0, 0xe0810006},
+        {1, 0x800602e0, 0, 0x80810006},
+        {1, 0x800602ec, 0, 0x60810006},
+        {0, 0x80060304, 0, 0x00000002},
+        {0, 0x80060304, 0, 0x00000002},
+        {1, 0x80060304, 0, 0x00000002},
+        {1, 0x800602d4, 0, 0xe0801124},
+        {1, 0x800602e0, 0, 0x80801124},
+        {1, 0x800602ec, 0, 0x60801124},
+        {0, 0x80060304, 0, 0x00000002},
+        {0, 0x80060304, 0, 0x00000002},
+        {1, 0x80060304, 0, 0x00000002},
+        {1, 0x800602d4, 0, 0xe0300400},
+        {1, 0x800602e0, 0, 0x80300400},
+        {1, 0x800602ec, 0, 0x60300400},
+        {1, 0x80060364, 0, 0x00000000},
+        {0, 0x80060364, 0, 0x00000000},
+        {0, 0x80060308, 0, 0x00011124},
+        {0, 0x8006030c, 0, 0x00010006},
+        {0, 0x80060310, 0, 0x00010228},
+        {0, 0x80060314, 0, 0x00010000},
+        {1, 0x80040918, 0, 0x000000a1},
+        {0, 0x80040008, 0, 0x01000200},
+        {1, 0x80040008, 0, 0x01000600},
+        {1, 0x800403a8, 0, 0x00000021},
+        {1, 0x800403b8, 0, 0x0000000a},
+        {1, 0x80040390, 0, 0x100f0e0d},
+        {1, 0x8004038c, 0, 0x14131211},
+        {1, 0x80040388, 0, 0x18171615},
+        {1, 0x80040384, 0, 0x001b1a19},
+        {1, 0x80040380, 0, 0x00000000},
+        {1, 0x800403a4, 0, 0x000c0b0a},
+	/* SKIP MEMC SRAM disable. Used by MMU table */
+#if 0
+        {0, 0x80040310, 0, 0x80000001},
+        {1, 0x80040310, 0, 0x00000001},
+#endif
+        {1, 0x8004092c, 0, 0x000e0a0e},
+        {1, 0x80040930, 0, 0x00040007},
+        {1, 0x80040934, 0, 0x00000000},
+        {1, 0x80040938, 0, 0x26000e24},
+        {1, 0x8004093c, 0, 0x00081000},
+        {1, 0x80040940, 0, 0x00000000},
+        {1, 0x80040944, 0, 0x00000408},
+        {1, 0x80040948, 0, 0x0002000b},
+        {1, 0x8004094c, 0, 0x01560056},
+        {1, 0x80040954, 0, 0x40001100},
+        {1, 0x80040958, 0, 0x008d0118},
+        {0, 0x80040048, 0, 0x04100002},
+        {1, 0x80040048, 0, 0x04100002},
+        {1, 0x8004004c, 0, 0x00000380},
+        {1, 0x80040050, 0, 0x00000000},
+        {1, 0x80040054, 0, 0x08080808},
+        {1, 0x80040058, 0, 0x000000e4},
+        {0, 0x80040908, 0, 0x00000000},
+        {1, 0x80040908, 0, 0x00000001},
+        {0, 0x80040910, 0, 0x00000007},
+        {1, 0x80040910, 0, 0x00000005},
+        {0, 0x80040008, 0, 0x01000600},
+        {1, 0x80040008, 0, 0x81000700},
+        {0, 0x80040008, 0, 0x81000700},
+	{0, 0, 0, 0xa},   /* 1GB hijack last entry value for total ddr size */
+#endif
+};
+
+static uint32_t run_reg_init(void)
+{
+	reg_entry* entry = &reg_table[0];
+	uint32_t value;
+
+	while (entry->addr) {
+		switch(entry->op) {
+			case REG_OP_READ:
+				value = *((volatile uint32_t*)(uintptr_t)entry->addr);
+				/* printf("ddr_regs         read32   : addr=0x00%08x, data=0x%08x\n", entry->addr, value); */
+			break;
+
+			case REG_OP_WRITE:
+				*((volatile uint32_t*)(uintptr_t)entry->addr) = entry->value;
+				/* printf("ddr_regs         write32  : addr=0x00%08x, data=0x%08x\n", entry->addr, entry->value); */
+			break;
+
+			case REG_OP_POLL:
+				while ((value = *((volatile uint32_t*)(uintptr_t)entry->addr))
+					!= (entry->value&entry->mask));
+			break;
+		}
+		entry++;
+	}
+
+	return 1<<(entry->value);
+}
+
+/* return 1 if there is alias, 0 no alias.  memsize in MB */
+static int memc_alias_test(uint32_t memsize)
+{
+	int ret = 0;
+	volatile uint32_t *base_addr;
+	volatile uint32_t *test_addr;
+	uint64_t test_size, total_size;
+#ifdef CONFIG_BCMBCA_IKOS
+	uint32_t data;
+#endif
+
+
+	total_size = ((uint64_t) (memsize)) << 20;
+	base_addr = (volatile uint32_t *)((uintptr_t) CONFIG_SYS_SDRAM_BASE);
+
+	for (test_size = 256; test_size < total_size;
+	     test_size = test_size << 1) {
+		test_addr =
+		    (volatile uint32_t *)((uintptr_t) base_addr +
+					  (uintptr_t) test_size);
+#if defined(PHYS_SDRAM_2)
+		/* if we are over the lower memory region from 0 to 2GB, we shift to the upper memory region */
+		if (test_size >= PHYS_SDRAM_1_SIZE)
+			test_addr =
+			    (volatile uint32_t *)((uintptr_t) test_addr +
+						  PHYS_SDRAM_1_SIZE);
+#endif
+#ifdef CONFIG_BCMBCA_IKOS
+		data = *test_addr;
+#endif
+		*base_addr = 0;
+		*test_addr = 0xaa55beef;
+		if (*base_addr == *test_addr) {
+			ret = 1;
+			break;
+		}
+#ifdef CONFIG_BCMBCA_IKOS
+		*test_addr = data;
+#endif
+	}
+
+	return ret;
+}
+
+/* return 1 if there is error, 0 no error.  memsize in MB */
+static int memc_memory_test(uint32_t memsize)
+{
+	volatile uint32_t *temp;
+	volatile uint32_t *addr;
+	int i, ret = 0;
+	uint32_t data;
+
+	addr = (volatile uint32_t *)CONFIG_SYS_SDRAM_BASE;
+	for (temp = addr, i = 0; i < 1024; i++)
+		*temp++ = i;
+
+	for (temp = addr, i = 0; i < 1024; i++) {
+		data = *temp++;
+		if (data != i)
+			break;
+	}
+
+	if (i == 1024)
+		printf("DDR test done successfully\n\r");
+	else {
+		printf("DDR test failed i=%d\n\r", i);
+		ret = -2;
+	}
+
+	return ret;
+}
+
+int ddr_init_reg(ddr_init_param * ddrinit_params)
+{
+	int ret;
+	uint32_t ddr_size_MB;
+
+	ddr_size_MB = run_reg_init();
+	printf("ddr init done total size %dMB\n", ddr_size_MB);
+
+	/* make sure configure register write are really carried over to target block */
+	__asm__ __volatile__("dsb	sy");
+	__asm__ __volatile__("isb");
+
+	if (memc_alias_test(ddr_size_MB)) {
+		printf("\nMemory alias detected. Probably wrong memory size is specified or memory subsystem not working\n");
+		return -3;
+	}
+
+	if (ret = memc_memory_test(ddr_size_MB))
+		return ret;
+
+	if (ddrinit_params && ddrinit_params->ddr_size != NULL)
+		*ddrinit_params->ddr_size = ddr_size_MB;
+
+	return ret;
+}
diff --git a/arch/arm/mach-bcmbca/dt_helper.c b/arch/arm/mach-bcmbca/dt_helper.c
new file mode 100644
index 0000000000..e36e4c10e0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/dt_helper.c
@@ -0,0 +1,358 @@
+#include <stdio.h>
+#include <malloc.h>
+#include <linux/libfdt.h>
+
+#include "dt_helper.h"
+
+static int dtb_setprop(void *fdt, const char *node_path, const char *property,
+		uint32_t *val_array, int size)
+{
+	int offset = fdt_path_offset(fdt, node_path);
+
+	if (offset == -FDT_ERR_NOTFOUND)
+		return -1;
+
+	return fdt_setprop(fdt, offset, property, val_array, size);
+}
+
+static const void *dtb_getprop(const void *fdt, const char *node_path,
+                   const char *property, int *len)
+{
+	int offset = fdt_path_offset(fdt, node_path);
+
+	if (offset == -FDT_ERR_NOTFOUND)
+		return NULL;
+
+	return fdt_getprop(fdt, offset, property, len);
+}
+
+static const int dtb_delnode(void *fdt, const char *node_path)
+{
+	int offset = fdt_path_offset(fdt, node_path);
+
+	if (offset == -FDT_ERR_NOTFOUND)
+		return -1;
+
+	return fdt_del_node(fdt, offset);
+}
+static void dtb_get_addr_size_cells(const char* dtb,
+					const char* node_path,
+					uint32_t* addr_cell_sz,
+					uint32_t* size_cell_sz)
+{
+	uint32_t* prop;
+	int len;
+	prop = (uint32_t*)dtb_getprop(dtb, node_path, "#address-cells", &len);
+	*addr_cell_sz = prop? cpu_to_fdt32(*prop):OF_NODE_ADDR_CELLS_DEFAULT;
+	prop = (uint32_t*)dtb_getprop(dtb, node_path, "#size-cells", &len);
+	*size_cell_sz = prop? cpu_to_fdt32(*prop):OF_NODE_SIZE_CELLS_DEFAULT;
+}
+
+int dtb_set_reserved_memory(void *dtb_ptr, char* name, uint64_t addr, uint64_t size)
+{
+	const void* prop;
+	char node_name[96];
+	uint32_t propval[4];
+	int len;
+	uint32_t addr_cell_sz, size_cell_sz;
+	uint64_t temp;
+
+	if (!dtb_ptr) {
+		return -1;
+	}
+
+	dtb_get_addr_size_cells(dtb_ptr,"/reserved-memory", &addr_cell_sz, &size_cell_sz);
+	if (addr_cell_sz > 2 || size_cell_sz > 2) {
+		printf("%s  Cells sizes are not supported %d %d \n", __func__, addr_cell_sz, size_cell_sz);
+		return -1;
+	}
+
+	sprintf(node_name, "/reserved-memory/%s", name);
+
+	/* assume address and size are 64 bit for 4908. need to read #address-cells and #size_cells
+	determine the actual size */
+	prop = dtb_getprop(dtb_ptr, node_name, "reg", &len);
+	/* sanity check */
+	if (prop &&  len == (size_cell_sz+addr_cell_sz)*sizeof(uint32_t) ) {
+		if (addr_cell_sz == 1) {
+			*propval = cpu_to_fdt32(addr);
+		} else {
+			temp = cpu_to_fdt64(addr);
+			memcpy((unsigned char*)propval, (unsigned char*)&temp, sizeof(uint64_t));
+		}
+
+		if (size_cell_sz == 1) {
+			*(propval+addr_cell_sz) = cpu_to_fdt32(size);
+		} else {
+			temp = cpu_to_fdt64(size);
+		memcpy((unsigned char*)(propval+addr_cell_sz), (unsigned char*)&temp, sizeof(uint64_t));
+		}
+		/* setting only size of the memory e.g. size_cell of the 'reg' */
+		memcpy((void*)prop, (char*)propval, len);
+		dtb_setprop(dtb_ptr, node_name, "reg", (uint32_t*)prop, len);
+		return 0;
+	}
+	printf("WARNING: Node's property %s is not defined\n",node_name);
+
+	return -1;
+}
+
+int dtb_del_cma_rsvmem_device(void *dtb_ptr)
+{
+	char dt_node_name[64];
+	int ret;
+
+	if (!dtb_ptr) {
+		return -1;
+	}
+
+	/* del the cache device node first */
+	sprintf(dt_node_name, "/%s", DT_CMA_CACHED_NODE_STR);
+	ret = dtb_delnode(dtb_ptr, dt_node_name);
+
+	/* del the uncached device node */
+	sprintf(dt_node_name, "/%s", DT_CMA_UNCACHED_NODE_STR);
+	ret |= dtb_delnode(dtb_ptr, dt_node_name);
+
+	return ret;
+}
+
+
+const void *dtb_get_prop(void *dtb_ptr, const char *node_path,
+	const char *property, int *len)
+{
+
+	return dtb_getprop(dtb_ptr, node_path, property, len);
+}
+
+
+int dtb_getprop_reg(void *dtb_ptr,
+			const char* node_name_par,
+			const char *node_name,
+			uint64_t* addr,
+			uint64_t* size)
+{
+	uint32_t addr_cell_sz, size_cell_sz;
+	const uint32_t* prop;
+	int len;
+	char node_path[96];
+	uint64_t temp;
+
+	if (!dtb_ptr) {
+		return -1;
+	}
+	sprintf(node_path, "/%s", node_name_par);
+	dtb_get_addr_size_cells(dtb_ptr, node_path, &addr_cell_sz, &size_cell_sz);
+	if (addr_cell_sz > 2 || size_cell_sz > 2) {
+		printf("%s  Cells sizes are not supported %d %d \n", __func__, addr_cell_sz, size_cell_sz);
+		return -1;
+	}
+	sprintf(node_path, "/%s/%s", node_name_par, node_name);
+	prop = (const uint32_t*)dtb_getprop(dtb_ptr, node_path, "reg", &len);
+	if (prop && len == (size_cell_sz+addr_cell_sz)*sizeof(uint32_t) ) {
+		if (size_cell_sz == 1) {
+			*size = (uint64_t)fdt32_to_cpu(*(prop+addr_cell_sz));
+		} else {
+			memcpy((unsigned char*)&temp, (unsigned char*)(prop+addr_cell_sz), sizeof(uint64_t));
+			*size = fdt64_to_cpu(temp);
+		}
+
+		if (addr_cell_sz == 1) {
+			*addr = (uint64_t)fdt32_to_cpu(*prop);
+		} else {
+			memcpy((unsigned char*)&temp, (unsigned char*)prop, sizeof(uint64_t));
+			*addr = fdt64_to_cpu(temp);
+		}
+		return 0;
+	}
+	return -1;
+}
+
+static int _dtb_getprop_cma_rsv_param(const void* dtb_ptr, char *node_name, const char *name, uint64_t* param)
+{
+    const uint32_t* prop;
+    int len;
+
+    prop = (const uint32_t*)dtb_getprop(dtb_ptr, node_name, name, &len);
+    if (prop && len == sizeof(uint32_t) ) {
+        *param = (uint64_t)fdt32_to_cpu(*prop); 
+        return 0;
+    }
+
+    return -1;
+}
+
+static int _dtb_getprop_cma_rsvmem_size(const void* dtb_ptr, char *node_name, uint64_t* size)
+{
+	const uint32_t* prop;
+	int len;
+
+	prop = (const uint32_t*)dtb_getprop(dtb_ptr, node_name, DT_CMA_RSVSIZE_PROP_STR, &len);
+	if (prop && len == sizeof(uint32_t) ) {
+		*size = (uint64_t)fdt32_to_cpu(*prop);
+		return 0;
+	}
+
+	return -1;
+}
+
+static int _dtb_setprop_cma_rsvmem_size(void* dtb_ptr, char *node_name, uint64_t size)
+{
+	const uint32_t* prop;
+	int len;
+	uint32_t propval;
+
+	prop = (const uint32_t*)dtb_getprop(dtb_ptr, node_name, DT_CMA_RSVSIZE_PROP_STR, &len);
+	if (prop && len == sizeof(uint32_t) ) {
+		propval = cpu_to_fdt32(size);
+
+		memcpy((void*)prop, (char*)&propval, len);
+		dtb_setprop(dtb_ptr, node_name, DT_CMA_RSVSIZE_PROP_STR, (uint32_t*)prop, len);
+
+		return 0;
+	}
+
+	return -1;
+}
+
+static int  _dtb_del_cma_rsvmem(void* dtb_ptr, char *node_name)
+{
+	return dtb_delnode(dtb_ptr, node_name);
+}
+
+int dtb_getprop_cma_rsv_param(void *dtb_ptr, const char *node_suffix, const char *name, uint64_t* param)
+{
+	char dt_node_name[64];
+	int ret;
+
+	if (!dtb_ptr) {
+		return -1;
+	}
+
+	/* try the cache node first */
+	sprintf(dt_node_name, "/%s/%s%s", DT_CMA_CACHED_NODE_STR, DT_RSVD_PREFIX_STR, node_suffix);
+	ret = _dtb_getprop_cma_rsv_param(dtb_ptr, dt_node_name, name, param);
+	if (ret != 0) {
+		/* try the uncached node */
+		sprintf(dt_node_name, "/%s/%s%s", DT_CMA_UNCACHED_NODE_STR, DT_RSVD_PREFIX_STR, node_suffix);
+		ret = _dtb_getprop_cma_rsv_param(dtb_ptr, dt_node_name, name, param);
+	}
+
+	return ret;
+}
+
+int dtb_getprop_cma_rsvmem_size(void *dtb_ptr, const char *name, uint64_t* size)
+{
+	return dtb_getprop_cma_rsv_param(dtb_ptr, name, DT_CMA_RSVSIZE_PROP_STR, size);
+}
+
+
+int dtb_setprop_cma_rsvmem_size(char* dtb_ptr, const char *name, uint64_t size)
+{
+	char dt_node_name[64];
+	int ret;
+
+	if (!dtb_ptr) {
+		return -1;
+	}
+
+	/* try the cache node first */
+	sprintf(dt_node_name, "/%s/%s%s", DT_CMA_CACHED_NODE_STR, DT_RSVD_PREFIX_STR, name);
+	ret = _dtb_setprop_cma_rsvmem_size(dtb_ptr, dt_node_name, size);
+	if (ret != 0) {
+		/* try the uncached node */
+		sprintf(dt_node_name, "/%s/%s%s", DT_CMA_UNCACHED_NODE_STR, DT_RSVD_PREFIX_STR, name);
+		ret = _dtb_setprop_cma_rsvmem_size(dtb_ptr, dt_node_name, size);
+	}
+
+	return ret;
+}
+
+int dtb_del_cma_rsvmem(void* dtb_ptr, const char *name)
+{
+	char dt_node_name[64];
+	int ret;
+
+	if (!dtb_ptr) {
+		return -1;
+	}
+
+	/* try the cache node first */
+	sprintf(dt_node_name, "/%s/%s%s", DT_CMA_CACHED_NODE_STR, DT_RSVD_PREFIX_STR, name);
+	ret = _dtb_del_cma_rsvmem(dtb_ptr, dt_node_name);
+	if (ret != 0) {
+		/* try the uncached node */
+		sprintf(dt_node_name, "/%s/%s%s", DT_CMA_UNCACHED_NODE_STR, DT_RSVD_PREFIX_STR, name);
+		ret = _dtb_del_cma_rsvmem(dtb_ptr, dt_node_name);
+	}
+
+	return ret;
+}
+
+int dtb_del_reserved_memory(void* dtb_ptr, char* name)
+{
+	char node_name[96];
+	sprintf(node_name, "/reserved-memory/%s", name);
+	return dtb_delnode(dtb_ptr, node_name);
+}
+
+
+int dtb_set_bootargs(void *fdt, char* bootargs, int append )
+{
+	const void *propdata =NULL;
+	int nodeoffset, res = -1,proplen = 0;
+
+	char *node = NULL,*prop=NULL,**err_msg = &prop, *new_bootargs = NULL;
+	if (!fdt) {
+		return res;
+	}
+	node = malloc(sizeof(DT_CHOSEN_NODE)+sizeof(DT_ROOT_NODE));
+	if (!node) {
+		goto err_out;
+	}
+	sprintf(node,"%s%s",DT_ROOT_NODE,DT_CHOSEN_NODE);
+	nodeoffset = fdt_path_offset(fdt, node);
+	if (nodeoffset == -FDT_ERR_NOTFOUND) {
+		*err_msg = node;
+		goto err_out;
+	}
+	prop = DT_BOOTARGS_PROP;
+	propdata = fdt_getprop(fdt, nodeoffset, prop, &proplen);
+
+	/* edit this to include mmc device root node in DT_BOOTARGS */
+	new_bootargs = malloc(DT_BOOTARGS_MAX_SIZE);
+	if (!new_bootargs) {
+		goto err_out;
+	}
+	memset(new_bootargs, 0x0, DT_BOOTARGS_MAX_SIZE);
+	if (append) {
+		if (proplen+strlen(bootargs)+1 > DT_BOOTARGS_MAX_SIZE) {
+			printf("Not enough space to append boot arg %s\n", bootargs);
+			goto err_out;
+		}
+
+		strncpy(new_bootargs, bootargs, DT_BOOTARGS_MAX_SIZE);
+		strncat(new_bootargs, " ", DT_BOOTARGS_MAX_SIZE);
+		if (propdata) {
+			strncat(new_bootargs, propdata, DT_BOOTARGS_MAX_SIZE);
+		}
+	} else {
+		strncpy(new_bootargs, bootargs, DT_BOOTARGS_MAX_SIZE);
+	}
+
+	res = fdt_setprop_string(fdt, nodeoffset, prop, new_bootargs);
+	if (res) {
+		goto err_out;
+	}
+
+	res = 0;
+err_out:
+	free(node);
+	if (new_bootargs) {
+		free(new_bootargs);
+	}
+	if (res && *err_msg) {
+		printf("Error accessing %s\n",*err_msg);
+	}
+	return res;
+}
diff --git a/arch/arm/mach-bcmbca/include/bca_common.h b/arch/arm/mach-bcmbca/include/bca_common.h
new file mode 100644
index 0000000000..cd4f807798
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/bca_common.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _BCMBCA_COMMON_H
+#define _BCMBCA_COMMON_H
+
+int suffix2shift(char suffix);
+
+int parse_env_string_plus_nums(const char *buffer, char **name, const int maxargs, unsigned long  *args, char *suffixes);
+int parse_env_nums(const char *buffer, const int maxargs, unsigned long  *args, char *suffixes);
+int bcmbca_get_boot_device(void);
+
+void print_chipinfo(void);
+void boost_cpu_clock(void);
+int set_cpu_freq(int freqMHz);
+
+int bcm_board_boot_fit_fdt_fixup(void* fdt);
+int bcm_board_boot_fdt_fixup(void* fdt);
+void init_cli_cb_arr(void);
+void register_cli_job_cb(unsigned long time_period, void (*job_cb)(void));
+void unregister_cli_job_cb(void (*job_cb)(void));
+void run_cli_jobs(void);
+
+#define BRCM_ROOTFS_SHA256_PROP      "brcm_rootfs_sha256"
+#define BRCM_ROOTFS_IMGLEN_PROP      "brcm_rootfs_imglen"
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/bca_sdk.h b/arch/arm/mach-bcmbca/include/bca_sdk.h
new file mode 100644
index 0000000000..38198aa723
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/bca_sdk.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _BCMBCA_SDK_H
+#define _BCMBCA_SDK_H
+
+#include <mmc.h>
+#include "boot_flash.h"
+
+/* volume ID assignments for UBI volumes
+ * 1 - metadata_copy1
+ * 2 - metadata_copy2 
+ * 3 - bootfs_1
+ * 4 - rootfs_1
+ * 5 - bootfs_2
+ * 6 - rootfs_2
+ * 7-9 RESERVED  
+ * 10 - data
+ * 11 - defaults (it is possible that uboot will need to access data and defaults during provisioning)
+ * Volume numbers > 11 would not need to be accessed by number and can be assigned at will
+ */
+
+#define METADATA_SIZE 256
+#define MAX_METADATA_SIZE 2048
+
+#define ACTIVE_IMGIDX_BOOTSTRAP	0
+#define ACTIVE_IMGIDX_1	1
+#define ACTIVE_IMGIDX_2	2
+#define ACTIVE_IMGIDX_MAX	ACTIVE_IMGIDX_2
+
+/* UBI volumes defines */
+#define IMAGE_VOL_ID_1 3
+#define IMAGE_VOL_ID_2 5
+#define METADATA_VOL_ID_1 1
+#define METADATA_VOL_ID_2 2
+
+/* GPT Partitions defines */
+#define IMAGE_PART_ID_1 IMAGE_VOL_ID_1
+#define IMAGE_PART_ID_2 IMAGE_VOL_ID_2
+#define METADATA_PART_ID_1 METADATA_VOL_ID_1 
+#define METADATA_PART_ID_2 METADATA_VOL_ID_2
+
+#define BOOT_MAGIC_MAGIC 0x75456e76
+
+enum boot_device {
+	BCA_DEV_NAND,
+	BCA_DEV_SPINAND,
+	BCA_DEV_MMC,
+	BCA_DEV_NOR,
+	BCA_DEV_NETBOOT,
+	BCA_DEV_UNKNOWN = 0
+};
+
+struct bcasdk_ctx {
+	enum boot_device boot_device;
+	enum boot_device image_device;
+	struct ubispl_info *ubispl;
+	struct mmc *mmc;
+	struct blk_desc *mmcboot_blk;
+	int active_image;
+	int last_reset_reason;
+	/* FIXME -- What is the "handle" for the GPT table where we find the image partitions? */
+};
+
+/*Define the partition name for spi nor flash*/
+#define LOADER_PART "loader"
+/*partition name for fitimage*/
+#define BOOTFS_PART "bootfs"
+#define ROOTFS_PART "rootfs"
+#define DATA_PART "data"
+
+int get_img_index_for_upgrade(int flag);
+int flash_upgrade_img_bundle( ulong bundle_addr , int img_index, const char * conf_name);
+int commit_image ( int img_index );
+
+int env_override_import(void *ep);
+
+#endif
+
+
diff --git a/arch/arm/mach-bcmbca/include/bcm_otp.h b/arch/arm/mach-bcmbca/include/bcm_otp.h
new file mode 100644
index 0000000000..ec9a132365
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/bcm_otp.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2020 Broadcom Ltd.
+ */
+/*
+ * 
+ */
+
+#ifndef __BCM_OTP_H__
+#define __BCM_OTP_H__
+
+#include "otp_map.h"
+#include "otp_map_cmn.h"
+
+typedef enum {
+	BCM_OTP_MAP,
+	BCM_SOTP_MAP,
+	BCM_MAP_MAX,
+} otp_map_t;
+
+typedef struct bcm_otp {
+	otp_map_cmn_t* map[BCM_MAP_MAX]; 
+} bcm_otp_t;
+
+
+otp_map_cmn_t*  bcm_otp(otp_map_t);
+
+otp_map_cmn_err_t bcm_otp_read(otp_map_feat_t, u32**, u32*);
+otp_map_cmn_err_t bcm_otp_write(otp_map_feat_t, const u32*, u32);
+otp_map_cmn_err_t bcm_otp_ctl(otp_map_t id, otp_hw_cmn_ctl_cmd_t *cmd, u32 *res);
+int bcm_otp_init(void);
+
+/* helper functions */
+otp_map_cmn_err_t bcm_sotp_ctl_perm( otp_hw_cmn_ctl_t ctl, u32 data, u32* res);
+
+/* short hand for reading/writing just a u32 val*/
+otp_map_cmn_err_t bcm_otp_get(otp_map_feat_t, u32*);
+
+#define bcm_otp_set(_feat, data) bcm_otp_write(_feat, data, sizeof(u32)
+
+int bcm_otp_get_cpu_clk(unsigned int* val);
+int bcm_otp_get_chipid(unsigned int* val);
+int bcm_otp_get_nr_cpus(u32* val);
+#endif
diff --git a/arch/arm/mach-bcmbca/include/bcm_rng.h b/arch/arm/mach-bcmbca/include/bcm_rng.h
new file mode 100644
index 0000000000..18505a1e29
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/bcm_rng.h
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Broadcom
+ */
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2019 Broadcom Ltd.
+ */
+/*
+ * 
+ */
+
+#ifndef __BCM_RNG_H__
+#define __BCM_RNG_H__
+
+#include <asm/arch/rng.h>
+int rng_pac_lock(uint32_t mode);
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/bcm_secure.h b/arch/arm/mach-bcmbca/include/bcm_secure.h
new file mode 100644
index 0000000000..135ac06059
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/bcm_secure.h
@@ -0,0 +1,238 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _BCM_SECURE_H
+#define _BCM_SECURE_H
+#include <asm/arch/brom.h>
+#define	BCM_RSA				"rsa2048"
+#define	BCM_PADDING			"emsa_pss"
+#define	BCM_CHECKSUM			"sha256"
+/*Sizes in bytes*/
+#define BCM_SECBT_RSA_PUBEXP		65537
+#define BCM_SECBT_RSA2048_MOD_LEN	256	
+#define BCM_SECBT_AES_CBC128_EK_LEN	16	
+#define BCM_SECBT_AES_CBC128_IV_LEN	16	
+#define BCM_SEC_BOOTROM_CRED_ADDR	
+#define	BCM_SECBT_CRED		(bcm_secbt_args())
+#define	BCM_SECBT_CRED_MOD	BCM_SECBT_CRED->auth.manu 
+#define	BCM_SECBT_CRED_AES	BCM_SECBT_CRED->encr.bek 
+#define	BCM_SECBT_CRED_AES_IV	BCM_SECBT_CRED->encr.biv
+
+#ifdef CONFIG_BCMBCA_EARLY_ABORT_JTAG_UNLOCK 
+#define BCM_SEC_UNLOCK_JTAG BROM_GEN_JTAG_UNLOCK 
+#else
+#define BCM_SEC_UNLOCK_JTAG
+#endif
+
+#include "image.h"
+
+#define FIT_AES1 "fit-aes1"
+#define FIT_AES2 "fit-aes2"
+
+struct bcm_secbt_auth_args {
+	uint8_t	manu[BCM_SECBT_RSA2048_MOD_LEN] __attribute__ ((aligned (4)));
+	uint8_t	oper[BCM_SECBT_RSA2048_MOD_LEN] __attribute__ ((aligned (4)));
+};
+
+struct bcm_secbt_encr_args {
+	uint8_t	bek[BCM_SECBT_AES_CBC128_EK_LEN];
+	uint8_t	iek[BCM_SECBT_AES_CBC128_EK_LEN];
+	uint8_t	biv[BCM_SECBT_AES_CBC128_IV_LEN];
+	uint8_t	iiv[BCM_SECBT_AES_CBC128_IV_LEN];
+};
+
+typedef struct __bcm_secbt_args{
+	struct bcm_secbt_auth_args	auth __attribute__ ((aligned (4)));
+	struct bcm_secbt_encr_args	encr;
+} bcm_secbt_args_t;
+
+typedef struct _bcm_sec_key_aes_arg {
+	u8	key[BCM_SECBT_AES_CBC128_EK_LEN*2];
+	char	id[64];
+} bcm_sec_key_aes_arg_t;
+
+typedef struct _bcm_sec_enc_key_arg {
+	char * name;
+	char * perm;
+	char * algo;
+	u8 * data;
+	u32 size;
+	u32 size_enc;
+	u64 load_addr;
+} bcm_sec_enc_key_arg_t;
+
+typedef struct _bcm_sec_export_item_arg {
+	char * id;
+	char * name;
+	u32 salt;
+	char * algo;
+	u8 * value;
+	u8 exp_flag;
+	u32 len;
+} bcm_sec_export_item_t;
+
+typedef	struct _bcm_sek_key_arg {
+	int len; 
+	void*	arg;
+	union {
+		bcm_sec_enc_key_arg_t * enc_key; 
+		bcm_sec_export_item_t * item;
+		bcm_sec_key_aes_arg_t * aes;
+	};
+} bcm_sec_key_arg_t;
+
+typedef struct _bcm_sec_key_ {
+	uint8_t rsa_pub[BCM_SECBT_RSA2048_MOD_LEN];
+	uint8_t aes_ek[BCM_SECBT_AES_CBC128_EK_LEN*2];
+	u8*	pub;
+	union {
+		u8*	ek;
+		void*	ch_ek;
+	};
+} bcm_sec_key_t;
+
+
+static inline volatile bcm_secbt_args_t * bcm_secbt_args(void) {
+	return (volatile bcm_secbt_args_t*)(CONFIG_SYS_SEC_CRED_ADDR);
+}
+
+typedef enum _bcm_sec_states { 
+	SEC_STATE_UNSEC = 0,
+	SEC_STATE_GEN3_MFG = 0x1,
+	SEC_STATE_GEN3_FLD = 0x2 
+} bcm_sec_state_t;
+
+#define SEC_STATE_SECURE (SEC_STATE_GEN3_MFG|SEC_STATE_GEN3_FLD)
+
+/* Security runtime context */
+typedef enum _bcm_sec_ctx { 
+	SEC_NONE = 0x0,
+	SEC_INIT = 0x1, /* various initializations if any */
+	SEC_SET = 0x2, /* commits various parameters for keys and sotp permissions*/
+	SEC_SET_SCHED = 0x100, /* Schedules multiple parameters to be set(run)  
+						later by invoking SEC_SET*/ 
+	SEC_SCHED_CLR = 0x200, /*  clears the schedule mask; */
+} bcm_sec_ctx_t;
+
+typedef enum _bcm_sec_ctrl {
+	SEC_CTRL_NONE = 0,
+	SEC_CTRL_FIT_AUTH, 		/* verify signature */
+	SEC_CTRL_FIT_SEC, 		/* FIT secure header process  */
+	SEC_CTRL_DT_CHAIN_SHA, 	/* verify signature */
+	SEC_CTRL_SOTP_LOCK_ALL, /*default - everything is open  */
+	SEC_CTRL_SOTP_UNLOCK_SOTP , /*    */
+	SEC_CTRL_SOTP_UNLOCK_SOTP_UNSEC, /*    */
+	SEC_CTRL_SOTP_UNLOCK_SOTP_UNSEC_PROV, /*    */
+	SEC_CTRL_SOTP_UNLOCK_SOTP_SEC, /*   */
+	SEC_CTRL_SOTP_JTAG_UNLOCK, /*   */
+	SEC_CTRL_KEY_GET,
+	SEC_CTRL_KEY_CHAIN_RSA,
+	SEC_CTRL_KEY_CHAIN_AES,
+	SEC_CTRL_KEY_CHAIN_ENCKEY,
+	SEC_CTRL_KEY_EXPORT_ITEM,
+	SEC_CTRL_KEY_CLEAN_SEC_MEM,
+	SEC_CTRL_KEY_CLEAN_ALL,
+	SEC_CTRL_RNG_LOCK_ALL, /*default - everything is open  */
+	SEC_CTRL_RNG_UNLOCK_RNG , /*    */
+	SEC_CTRL_RNG_UNLOCK_RNG_UNSEC, /*    */
+	SEC_CTRL_RNG_UNLOCK_RNG_SEC, /*   */
+	SEC_CTRL_MAX
+} bcm_sec_ctrl_t;
+
+typedef struct _sec_ctrl_arg {
+	/* an array with SEC_CTRL_RUN_ORDER_MAX 
+ 	*	represents order in which each corresponding
+ 	*	value is processed  
+ 	* 	*/
+	bcm_sec_ctrl_t ctrl;
+	void* ctrl_arg;
+} bcm_sec_ctrl_arg_t;
+
+typedef struct _bcm_sec_ bcm_sec_t;
+
+#define SEC_CTRL_RUN_ORDER_MAX 10 
+typedef struct _bcm_sec_cb_arg {
+	bcm_sec_ctrl_arg_t arg[SEC_CTRL_RUN_ORDER_MAX];
+} bcm_sec_cb_arg_t;
+
+/*Handlers xxxx_cb*/
+typedef struct _bcm_sec_ctrl_cb_ {
+	int (*cb)(bcm_sec_t*, bcm_sec_ctrl_t, void *);
+	bcm_sec_ctrl_arg_t arg[SEC_CTRL_RUN_ORDER_MAX];
+} bcm_sec_ctrl_cb_t;
+
+typedef enum _ctrl_args {
+	SEC_CTRL_ARG_MAIN = 0,
+	SEC_CTRL_ARG_KEY,
+	SEC_CTRL_ARG_SOTP,
+	SEC_CTRL_ARG_RNG,
+	SEC_CTRL_ARG_MAX,
+} bcm_sec_ctrl_arg_num_t;
+
+
+typedef struct {
+	u32 delg_id;
+	u32 max_antirollback;
+	u8* sec_policy_fit;
+	u8 rsa_pub[BCM_SECBT_RSA2048_MOD_LEN];
+	u8 aes_ek[BCM_SECBT_AES_CBC128_EK_LEN*2];
+} bcm_sec_delg_cfg;
+
+struct _bcm_sec_ {
+        bcm_sec_key_t key;
+	bcm_sec_delg_cfg  * delg_cfg_obj;
+        bcm_sec_state_t state;
+        bcm_sec_ctx_t curr_ctx;
+        bcm_sec_ctx_t sched_ctx;
+	bcm_sec_ctrl_cb_t cb[SEC_CTRL_ARG_MAX]; 
+	bcm_sec_ctrl_arg_num_t ord[SEC_CTRL_ARG_MAX]; 
+}; 
+
+int bcm_sec_set_sec_ser_num( char * ser_num, u32 ser_num_size);
+int bcm_sec_get_sec_ser_num( char * ser_num, u32 ser_num_size);
+int bcm_sec_set_dev_spec_key( char * dev_spec_key, u32 dev_spec_key_size);
+int bcm_sec_get_dev_spec_key( char * dev_spec_key, u32 dev_spec_key_size);
+int bcm_sec_get_antirollback_lvl( u32 * lvl);
+int bcm_sec_set_antirollback_lvl( u32 lvl);
+void bcm_sec_abort(void);
+bcm_sec_t* bcm_sec(void);
+bcm_sec_state_t bcm_sec_state(void);
+
+/* returns ek + iv in the 'aes' pointer  */
+void bcm_sec_get_active_aes_key(u8** key);
+/* pass pointer to ek+iv*/
+void bcm_sec_set_active_aes_key(u8* key);
+
+u8* bcm_sec_get_active_pub_key(void);
+u8* bcm_sec_set_active_pub_key(u8 * key);
+
+u8* bcm_sec_get_root_pub_key(void);
+void bcm_sec_get_root_aes_key(u8** key);
+int bcm_sec_delg_process_sdr( u8 * psdr, u8 * hdr_end, u32 * sdr_plus_sig_size);
+int bcm_sec_delg_process_sec_node(u8 * fit);
+bcm_sec_delg_cfg * bcm_sec_get_delg_cfg(void);
+
+int bcm_sec_update_ctrl_arg(bcm_sec_ctrl_arg_t* k,
+			bcm_sec_ctrl_arg_num_t ctrl);
+void bcm_sec_clean_keys(bcm_sec_t* sec);
+void bcm_sec_init(void);
+int bcm_sec_do(bcm_sec_ctx_t, bcm_sec_cb_arg_t args[SEC_CTRL_ARG_MAX]); 
+ulong bcm_sec_get_reqd_load_size( void * fit );
+int bcm_sec_validate_fit(void*, uint32_t);
+void bcm_sec_digest(const u8 *data, u32 len, u8* digest, char* algo);
+int bcm_sec_rsa_verify(const u8 *obj,
+                u32 obj_len, const u8* sig,
+                u32 sig_len, const u8 *pub,
+                struct image_sign_info *im );
+void bcm_sec_deinit(void);
+int bcm_sec_sec_fit(void* fit);
+int bcm_sec_btrm_key_info(bcm_sec_t* sec);
+void bcm_sec_aes_cbc128(u8 *key, u8 *iv, u8* txt, u32 length, u32 flag);
+
+/* TODO:must be moved or replaced by common primitives*/
+u8* bcm_util_env_var2bin(const char* id, u32 data_len );
+u8* bcm_util_get_fdt_prop_data(void* fdt, char* path, char *prop, int* len);
+int bcm_util_hex2u32(const char* s, u8*  d);
+#endif
diff --git a/arch/arm/mach-bcmbca/include/bcm_ubus4.h b/arch/arm/mach-bcmbca/include/bcm_ubus4.h
new file mode 100644
index 0000000000..c4518e8a81
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/bcm_ubus4.h
@@ -0,0 +1,418 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Broadcom
+ */
+/*
+ * 
+ */
+
+#ifndef __BCM_UBUS4_H__
+#define __BCM_UBUS4_H__
+
+#ifndef IS_BCMCHIP
+#define IS_BCMCHIP(num) (defined(_BCM9##num##_)||defined(CONFIG_BCM9##num)|| defined(CONFIG_BCM##num))
+#endif
+
+typedef struct ub_mst_addr_map_t {
+    int           port_id;
+    unsigned long base;
+} ub_mst_addr_map_t;
+
+#if IS_BCMCHIP(6858)
+#define UCB_NODE_ID_SLV_SYS     0
+#define UCB_NODE_ID_MST_PCIE0   3
+#define UCB_NODE_ID_SLV_PCIE0   4
+#define UCB_NODE_ID_MST_PCIE2   5
+#define UCB_NODE_ID_SLV_PCIE2   6
+#define UCB_NODE_ID_MST_SATA    UCB_NODE_ID_MST_PCIE2
+#define UCB_NODE_ID_SLV_SATA    UCB_NODE_ID_SLV_PCIE2
+#define UCB_NODE_ID_MST_USB     14
+#define UCB_NODE_ID_SLV_USB     15
+#define UCB_NODE_ID_SLV_LPORT   19
+#define UCB_NODE_ID_SLV_WAN     21
+
+int ubus_master_set_rte_addr(int master_port_id, int port, int val);
+#endif
+
+
+#if IS_BCMCHIP(6856)
+#define UCB_NODE_ID_SLV_SYS     0
+#define UCB_NODE_ID_MST_PCIE0   3
+#define UCB_NODE_ID_SLV_PCIE0   4
+#define UCB_NODE_ID_MST_USB     14
+#define UCB_NODE_ID_SLV_USB     15
+#define UCB_NODE_ID_SLV_MEMC    16
+#elif IS_BCMCHIP(6846)
+#define UCB_NODE_ID_MST_PCIE0   3
+#define UCB_NODE_ID_SLV_PCIE0   4
+#define UCB_NODE_ID_MST_USB     14
+#define UCB_NODE_ID_SLV_USB     15
+#define UCB_NODE_ID_SLV_MEMC    16
+#endif
+
+
+#if IS_BCMCHIP(6846) || IS_BCMCHIP(6856)
+extern unsigned int g_board_size_power_of_2;
+#endif
+
+#if IS_BCMCHIP(63158)
+
+#define UBUS_MAX_PORT_NUM        32
+#define UBUS_NUM_OF_MST_PORTS    17
+#define UBUS_PORT_ID_LAST_SYSTOP 13
+
+#define UBUS_PORT_ID_BIU         2
+#define UBUS_PORT_ID_DMA0        24
+#define UBUS_PORT_ID_DQM         23
+#define UBUS_PORT_ID_DSLCPU      11
+#define UBUS_PORT_ID_DSL         6
+#define UBUS_PORT_ID_FPM         21
+#define UBUS_PORT_ID_MEMC        1
+#define UBUS_PORT_ID_NATC        26
+#define UBUS_PORT_ID_PCIE0       8
+#define UBUS_PORT_ID_PCIE2       9
+#define UBUS_PORT_ID_PCIE3       10
+#define UBUS_PORT_ID_PERDMA      7
+#define UBUS_PORT_ID_PER         3
+#define UBUS_PORT_ID_PMC         13
+#define UBUS_PORT_ID_PSRAM       16
+#define UBUS_PORT_ID_QM          22
+#define UBUS_PORT_ID_RQ0         32
+#define UBUS_PORT_ID_SPU         5
+#define UBUS_PORT_ID_SWH         14
+#define UBUS_PORT_ID_SYS         31
+#define UBUS_PORT_ID_SYSXRDP     27
+#define UBUS_PORT_ID_USB         4
+#define UBUS_PORT_ID_VPB         20
+#define UBUS_PORT_ID_WAN         12
+
+#elif IS_BCMCHIP(63146)
+#define UBUS_MAX_PORT_NUM        17
+#define UBUS_NUM_OF_MST_PORTS    12
+#define UBUS_PORT_ID_LAST_SYSTOP 0
+
+#define UBUS_PORT_ID_MEMC        1
+#define UBUS_PORT_ID_BIU         2
+#define UBUS_PORT_ID_PER         3
+#define UBUS_PORT_ID_USB         4
+#define UBUS_PORT_ID_DSL         5
+#define UBUS_PORT_ID_DSLCPU      6
+#define UBUS_PORT_ID_ETHPHY      7
+#define UBUS_PORT_ID_PCIE0       8
+#define UBUS_PORT_ID_PCIE1       9
+#define UBUS_PORT_ID_PCIE2       10
+#define UBUS_PORT_ID_PSRAM       11
+#define UBUS_PORT_ID_DMA0        12
+#define UBUS_PORT_ID_DMA1        13
+#define UBUS_PORT_ID_RQ0         14
+#define UBUS_PORT_ID_QM          15
+#define UBUS_PORT_ID_VPB         16
+
+#elif IS_BCMCHIP(4912)
+#define UBUS_MAX_PORT_NUM        24
+#define UBUS_NUM_OF_MST_PORTS    16
+#define UBUS_PORT_ID_LAST_SYSTOP 0
+
+#define UBUS_PORT_ID_MEMC        1
+#define UBUS_PORT_ID_BIU         2
+#define UBUS_PORT_ID_PER         3
+#define UBUS_PORT_ID_USB         4
+#define UBUS_PORT_ID_ETHPHY      5
+#define UBUS_PORT_ID_PCIE0       8
+#define UBUS_PORT_ID_PCIE1       9
+#define UBUS_PORT_ID_PCIE2       10
+#define UBUS_PORT_ID_PCIE3       11
+#define UBUS_PORT_ID_SPU         12
+#define UBUS_PORT_ID_VPB         14
+#define UBUS_PORT_ID_MPM         15
+#define UBUS_PORT_ID_DMA0        16
+#define UBUS_PORT_ID_DMA1        17
+#define UBUS_PORT_ID_DMA2        18
+#define UBUS_PORT_ID_QM          19
+#define UBUS_PORT_ID_RQ0         20
+#define UBUS_PORT_ID_RQ1         21
+#define UBUS_PORT_ID_PSRAM       22
+#define UBUS_PORT_ID_PSRAM1      23
+
+#elif IS_BCMCHIP(6858)
+#define UBUS_MAX_PORT_NUM        35
+#define UBUS_NUM_OF_MST_PORTS    19
+#define UBUS_PORT_ID_LAST_SYSTOP 15
+
+#define UBUS_PORT_ID_MEMC        1
+#define UBUS_PORT_ID_BIU         2
+#define UBUS_PORT_ID_PER         3
+#define UBUS_PORT_ID_USB         4
+#define UBUS_PORT_ID_PERDMA      5
+#define UBUS_PORT_ID_SPU         6
+#define UBUS_PORT_ID_PCIE0       8
+#define UBUS_PORT_ID_PCIE2       9
+#define UBUS_PORT_ID_PMC         15
+#define UBUS_PORT_ID_XRDP_VPB    20
+#define UBUS_PORT_ID_QM          22
+#define UBUS_PORT_ID_DQM         23
+#define UBUS_PORT_ID_DMA0        24
+#define UBUS_PORT_ID_DMA1        25
+#define UBUS_PORT_ID_NATC        26
+#define UBUS_PORT_ID_TOP_BUFF    28
+#define UBUS_PORT_ID_XRDP_BUFF   29
+#define UBUS_PORT_ID_RQ0         32
+#define UBUS_PORT_ID_RQ1         33
+#define UBUS_PORT_ID_RQ2         34
+#define UBUS_PORT_ID_RQ3         35
+
+#elif IS_BCMCHIP(6846)
+#define UBUS_MAX_PORT_NUM        15
+#define UBUS_NUM_OF_MST_PORTS    9
+#define UBUS_PORT_ID_LAST_SYSTOP 7
+
+#define UBUS_PORT_ID_MEMC        1
+#define UBUS_PORT_ID_BIU         2
+#define UBUS_PORT_ID_PER         3
+#define UBUS_PORT_ID_USB         4
+#define UBUS_PORT_ID_PCIE0       7
+#define UBUS_PORT_ID_QM          11
+#define UBUS_PORT_ID_DQM         12
+#define UBUS_PORT_ID_DMA0        13
+#define UBUS_PORT_ID_NATC        14
+#define UBUS_PORT_ID_RQ0         15
+
+#elif IS_BCMCHIP(6878)
+#define UBUS_PORT_ID_MEMC        1
+#define UBUS_MAX_PORT_NUM        14
+#define UBUS_NUM_OF_MST_PORTS    8
+#define UBUS_PORT_ID_LAST_SYSTOP 7
+
+#define UBUS_PORT_ID_BIU         2
+#define UBUS_PORT_ID_PER         3
+#define UBUS_PORT_ID_USB         4
+#define UBUS_PORT_ID_WIFI        6
+#define UBUS_PORT_ID_PCIE0       7
+#define UBUS_PORT_ID_QM          11
+#define UBUS_PORT_ID_DMA0        13
+#define UBUS_PORT_ID_RQ0         14
+
+#define UBUS_PORT_ID_VPB         9
+
+#elif IS_BCMCHIP(6855)
+#define UBUS_MAX_PORT_NUM        21
+#define UBUS_NUM_OF_MST_PORTS    11
+#define UBUS_PORT_ID_LAST_SYSTOP 12
+
+#define UBUS_PORT_ID_BIU         2
+#define UBUS_PORT_ID_PER         3
+#define UBUS_PORT_ID_USB         4
+#define UBUS_PORT_ID_PCIE0       10
+#define UBUS_PORT_ID_WIFI        12
+#define UBUS_PORT_ID_DMA0        16
+#define UBUS_PORT_ID_DMA1        17
+#define UBUS_PORT_ID_DMA2        18
+#define UBUS_PORT_ID_QM          19
+#define UBUS_PORT_ID_RQ0         20
+#define UBUS_PORT_ID_RQ1         21
+
+#elif IS_BCMCHIP(63178)
+#define UBUS_MAX_PORT_NUM        11
+#define UBUS_NUM_OF_MST_PORTS    9
+#define UBUS_PORT_ID_LAST_SYSTOP 0
+
+#define UBUS_PORT_ID_SYS         0
+#define UBUS_PORT_ID_MEMC        1
+#define UBUS_PORT_ID_BIU         2
+#define UBUS_PORT_ID_PER         3
+#define UBUS_PORT_ID_USB         4
+#define UBUS_PORT_ID_DSL         5
+#define UBUS_PORT_ID_DSLCPU      6
+#define UBUS_PORT_ID_PMC         7
+#define UBUS_PORT_ID_SWH         8
+#define UBUS_PORT_ID_PCIE0       10
+#define UBUS_PORT_ID_WIFI        12
+
+#elif IS_BCMCHIP(47622)
+#define UBUS_MAX_PORT_NUM        12
+#define UBUS_NUM_OF_MST_PORTS    10
+#define UBUS_PORT_ID_LAST_SYSTOP 0
+
+#define UBUS_PORT_ID_SYS         0
+#define UBUS_PORT_ID_MEMC        1
+#define UBUS_PORT_ID_BIU         2
+#define UBUS_PORT_ID_PER         3
+#define UBUS_PORT_ID_USB         4
+#define UBUS_PORT_ID_PMC         7
+#define UBUS_PORT_ID_SYSPORT     8
+#define UBUS_PORT_ID_SYSPORT1    9
+#define UBUS_PORT_ID_PCIE0       10
+#define UBUS_PORT_ID_SPU         11
+#define UBUS_PORT_ID_WIFI        13
+#define UBUS_PORT_ID_WIFI1       14
+
+#elif IS_BCMCHIP(6856)
+#define UBUS_MAX_PORT_NUM        19
+#define UBUS_NUM_OF_MST_PORTS    12
+#define UBUS_PORT_ID_LAST_SYSTOP 7
+
+#define UBUS_PORT_ID_MEMC        1
+#define UBUS_PORT_ID_BIU         2
+#define UBUS_PORT_ID_PER         3
+#define UBUS_PORT_ID_USB         4
+#define UBUS_PORT_ID_PCIE2       6
+#define UBUS_PORT_ID_PCIE0       7
+#define UBUS_PORT_ID_QM          11
+#define UBUS_PORT_ID_DQM         12
+#define UBUS_PORT_ID_DMA0        13
+#define UBUS_PORT_ID_NATC        14
+#define UBUS_PORT_ID_DMA1        17
+#define UBUS_PORT_ID_RQ0         18
+#define UBUS_PORT_ID_RQ1         19
+
+#elif IS_BCMCHIP(6756)
+#define UBUS_MAX_PORT_NUM        12
+#define UBUS_NUM_OF_MST_PORTS    10
+#define UBUS_PORT_ID_LAST_SYSTOP 0
+
+#define UBUS_PORT_ID_SYS         0
+#define UBUS_PORT_ID_MEMC        1
+#define UBUS_PORT_ID_BIU         2
+#define UBUS_PORT_ID_PER         3
+#define UBUS_PORT_ID_USB         4
+#define UBUS_PORT_ID_PMC         7
+#define UBUS_PORT_ID_SWH         8
+#define UBUS_PORT_ID_MPM         9
+#define UBUS_PORT_ID_PCIE0       10
+#define UBUS_PORT_ID_SPU         11
+#define UBUS_PORT_ID_WIFI        13
+#define UBUS_PORT_ID_WIFI1       14
+#endif
+
+#ifdef CONFIG_BCM_GLB_COHERENCY
+#define IS_DDR_COHERENT 1
+#else
+#define IS_DDR_COHERENT 0
+#endif
+
+#define DECODE_CFG_SIZE_MASK        0xff00
+#define DECODE_CFG_SIZE_SHIFT       8
+#define DECODE_CFG_ENABLE_MASK      0x60000
+#define DECODE_CFG_ENABLE_SHIFT     17
+#define DECODE_CFG_CACHE_BITS_MASK  0x380000
+#define DECODE_CFG_CACHE_BITS_SHIFT 19
+#define DECODE_CFG_CMD_DTA_MASK     0x10000
+#define DECODE_CFG_CMD_DTA_SHIFT    16
+#define DECODE_CFG_STRICT_MASK      0x400000
+#define DECODE_CFG_STRICT_SHIFT     22
+#define DECODE_CFG_PORT_ID_MASK     0xff
+#define DECODE_CFG_PORT_ID_SHIFT    0
+#define DECODE_CFG_CTRL_CACHE_SEL_SHIFT 4
+#define DECODE_CFG_CTRL_CACHE_SEL_MASK  (0x3<<DECODE_CFG_CTRL_CACHE_SEL_SHIFT)
+
+#define DECODE_CFG_ENABLE_OFF       (0 << DECODE_CFG_ENABLE_SHIFT)
+
+#define DECODE_CFG_ENABLE_ADDR_ONLY (1 << DECODE_CFG_ENABLE_SHIFT)
+#define DECODE_CFG_ENABLE_CDSM_0    (2 << DECODE_CFG_ENABLE_SHIFT)
+#define DECODE_CFG_ENABLE_CDSM_1    (3 << DECODE_CFG_ENABLE_SHIFT)
+#define DECODE_CFG_CACHE_BITS       (1 << DECODE_CFG_CACHE_BITS_SHIFT)
+
+#define DECODE_CFG_CTRL_CACHE_SEL_DEF     (0x0<<DECODE_CFG_CTRL_CACHE_SEL_SHIFT)
+#define DECODE_CFG_CTRL_CACHE_SEL_INPUT   (0x1<<DECODE_CFG_CTRL_CACHE_SEL_SHIFT)
+#define DECODE_CFG_CTRL_CACHE_SEL_CFG_REG (0x2<<DECODE_CFG_CTRL_CACHE_SEL_SHIFT)
+
+/**
+ * m = memory, f = field
+ */
+#define GET_FIELD(m,f) \
+    (((m) & f##_MASK) >> f##_SHIFT)
+
+typedef struct
+{
+    uint32_t base_addr;
+    uint32_t remap_addr;
+    uint32_t attributes;
+}DecodeCfgMstWndRegs;
+
+/* BIU Registers */
+
+typedef struct
+{
+    uint32_t ctrl;
+    uint32_t cache_cfg;
+    uint32_t reserved[2];
+    DecodeCfgMstWndRegs window[20];
+} DecodeCfgRegs;
+
+typedef struct
+{
+#define AXI_CFG_AWCACHE_BYPASS     (0x1<<5)
+    uint32_t cfg;
+    uint32_t bufsize;
+} AXICfgRegs;
+
+#if IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
+
+#define ROUTE_ADDR_SIZE        0x400
+#define TOKEN_SIZE             0x400
+typedef struct
+{
+    uint32_t port_cfg[12];                  /* 0x0 */
+#define DCM_UBUS_CONGESTION_THRESHOLD 3  
+    uint32_t reserved1[52];                 /* 0x30 */
+    uint32_t loopback[20];                  /* 0x100 */
+    uint32_t reserved2[556];                /* 0x150 */  
+    DecodeCfgRegs decode_cfg;               /* 0xA00 */
+    uint32_t reserved3[128];                /* 0xB00 */
+    AXICfgRegs axi_cfg;                     /* 0xD00 */
+    uint32_t reserved4[190];                /* 0xD08 */  
+    uint32_t routing_addr[ROUTE_ADDR_SIZE]; /* 0x1000 */
+    uint32_t token[TOKEN_SIZE];             /* 0x2000 */
+} MstPortNode;
+
+#else
+
+#if IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(6878) || IS_BCMCHIP(6756)
+#define ROUTE_ADDR_SIZE        0x100
+#define TOKEN_SIZE             0x100
+#else
+#define ROUTE_ADDR_SIZE        0x80
+#define TOKEN_SIZE             0x80
+#endif
+
+typedef struct
+{
+    uint32_t port_cfg[8];
+#define DCM_UBUS_CONGESTION_THRESHOLD 3
+    uint32_t reserved1[56];
+    uint32_t loopback[20];
+    uint32_t reserved2[44];
+    uint32_t routing_addr[ROUTE_ADDR_SIZE];
+    uint32_t token[TOKEN_SIZE];
+    DecodeCfgRegs decode_cfg;
+    uint8_t rsvd1[512];
+    AXICfgRegs axi_cfg;
+} MstPortNode;
+
+#endif
+
+typedef struct ubus_credit_cfg {
+    int port_id;
+    int credit;
+}ubus_credit_cfg_t;
+
+void ubus_master_port_init(void);
+void bcm_ubus_config(void);
+void ubus_cong_threshold_wr(int port_id, unsigned int val);
+int ubus_master_remap_port(int master_port_id);
+int log2_32 (unsigned int value);
+int ubus_master_set_token_credits(int master_port_id, int token, int credits);
+void ubus_deregister_port(int ucbid);
+void ubus_register_port(int ucbid);
+#if IS_BCMCHIP(63158) || IS_BCMCHIP(6858)
+void apply_ubus_credit_each_master(int master);
+#endif
+#if IS_BCMCHIP(6858)
+void ubus_master_rte_cfg(void);
+#endif
+#if IS_BCMCHIP(63178)
+void configure_ubus_sar_reg_decode(void);
+#endif
+void ubus_master_cpu_enable_axi_write_cache(int enable);
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/bcmbca-dtsetup.h b/arch/arm/mach-bcmbca/include/bcmbca-dtsetup.h
new file mode 100644
index 0000000000..9ac1f3bbf0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/bcmbca-dtsetup.h
@@ -0,0 +1,21 @@
+#include <common.h>
+#include <fdt_support.h>
+#include <environment.h>
+#include <stdlib.h>
+#include "tpl_params.h"
+
+void update_uboot_fdt(void *fdt_addr, tpl_params *tplp);
+void ft_update_cpu_nodes(void* dtb_ptr, bd_t *bd);
+
+#define ENV_RDP1			PARAM1_BASE_ADDR_STR
+#define ENV_RDP2 			PARAM2_BASE_ADDR_STR
+#define ENV_DHD1			DHD_BASE_ADDR_STR	
+#define ENV_DHD2			DHD_BASE_ADDR_STR_1
+#define ENV_DHD3			DHD_BASE_ADDR_STR_2
+#define ENV_BUFMEM			BUFMEM_BASE_ADDR_STR
+#define ENV_RNRMEM			RNRMEM_BASE_ADDR_STR
+
+#define QUAD_CPUS 4
+#define DUAL_CPUS 2
+#define ONE_CPU   1
+
diff --git a/arch/arm/mach-bcmbca/include/bcmbca_button.h b/arch/arm/mach-bcmbca/include/bcmbca_button.h
new file mode 100644
index 0000000000..20f73161c2
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/bcmbca_button.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _BCMBCA_BUTTON_H
+#define _BCMBCA_BUTTON_H
+
+typedef void (*buttonNotifyHook_t)(unsigned long timeInMs, void *param);
+int register_button_action(const char *button_name, const char *action_name,
+	buttonNotifyHook_t hook);
+int register_button_action_for_event(const char *button_name, const char* event_name,
+	const char *action_name, buttonNotifyHook_t hook);
+void bcmbca_button_init(void);
+void btn_poll_block(void);
+int btn_poll(void);
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/bcmbca_nand_spl.h b/arch/arm/mach-bcmbca/include/bcmbca_nand_spl.h
new file mode 100644
index 0000000000..32d3e20528
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/bcmbca_nand_spl.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _BCMBCA_NAND_SPL_H
+#define _BCMBCA_NAND_SPL_H
+
+u32 nand_spl_get_blk_size(void);
+u32 nand_spl_get_page_size(void);
+u64 nand_spl_get_total_size(void);
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/boot_blob.h b/arch/arm/mach-bcmbca/include/boot_blob.h
new file mode 100644
index 0000000000..50f07724c5
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/boot_blob.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _BOOT_BLOB_H
+#define _BOOT_BLOB_H
+
+#define BOOT_BLOB_SUCCESS		0
+#define BOOT_BLOB_NOT_IN_HASTTBL	-1
+#define BOOT_BLOB_INVALID_PARAM		-2
+#define BOOT_BLOB_MAGIC_NOT_FOUND	-3
+#define BOOT_BLOB_VERIFICATION_FAIL	-4
+
+#define DPFE_MAGIC_MASK		0xffffff00
+#define MCB_TABLE_MAGIC		0x00CB00CB
+#define DDR3_TABLE_MAGIC	0x64447233
+#define DDR4_TABLE_MAGIC	0x64447234
+#define DPFE_DDR3_TABLE_MAGIC	0x64503300
+#define DPFE_DDR4_TABLE_MAGIC	0x64503400
+#define UBOOT_ENV_MAGIC		0x75456e76
+#define TPL_TABLE_MAGIC		0x74506c21
+
+#define IS_DPFE_DDR3_MAGIC(magic)	\
+	(((magic)&DPFE_MAGIC_MASK) == DPFE_DDR3_TABLE_MAGIC)
+#define IS_DPFE_DDR4_MAGIC(magic)	\
+	(((magic)&DPFE_MAGIC_MASK) == DPFE_DDR4_TABLE_MAGIC)
+#define IS_DPFE_MAGIC(magic)		\
+	(IS_DPFE_DDR3_MAGIC(magic) || IS_DPFE_DDR4_MAGIC(magic))
+
+#define BOOT_BLOB_MAX_MAGIC_SEARCH	6
+#define BOOT_BLOB_MAX_MAGIC_NUMS	6
+#define BOOT_BLOB_SEARCH_START_ADDR	0x0
+#define BOOT_BLOB_SEARCH_END_ADDR	0x200000
+#define BOOT_BLOB_SEARCH_BOUNDARY	0x1000
+#define BOOT_BLOB_MAX_ENV_SIZE		0x10000
+
+#if defined(CONFIG_BCM6846) || defined(CONFIG_BCM6878)
+#define BOOT_BLOB_MAX_DDR_SIZE		0x8000
+#else
+#define BOOT_BLOB_MAX_DDR_SIZE		0x10000
+#endif
+
+struct overlays {
+	uint32_t ovltype;
+	uint32_t selector;
+	uint32_t offset;
+	uint32_t size;
+	uint8_t sha[32];
+};
+
+typedef struct _boot_blob_hdr {
+	uint32_t magic;
+	uint32_t length;
+	uint32_t crc;
+}boot_blob_hdr;
+
+int load_boot_blob(uint32_t magic, uint32_t sel, void *data, int* len);
+void *load_spl_env(void *buffer);
+struct overlays* get_boot_blob_hash_entry(int i);
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/boot_flash.h b/arch/arm/mach-bcmbca/include/boot_flash.h
new file mode 100644
index 0000000000..9a31eaf45f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/boot_flash.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _BOOT_FLASH_H
+#define _BOOT_FLASH_H
+
+#define NOR_XIP_BASE_ADDR 0xffd00000
+
+#define FLASH_DEV_STR_NAND	 "NAND"
+#define FLASH_DEV_STR_SPINOR "SPINOR"
+#define FLASH_DEV_STR_EMMC	 "EMMC"
+
+#define SPIFLASH_MTDNAME "nor0"
+
+int boot_flash_init(void);
+int read_boot_device(uint32_t address, void *data, int len);
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/brcmnand_spl.h b/arch/arm/mach-bcmbca/include/brcmnand_spl.h
new file mode 100644
index 0000000000..fce102848a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/brcmnand_spl.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _BRCM_NAND_SPL_H
+#define _BRCM_NAND_SPL_H
+
+void brcmnand_init(void);
+uint32_t brcmnand_get_block_size(void);
+uint32_t brcmnand_get_page_size(void);
+uint64_t brcmnand_get_total_size(void);
+int brcmnand_read_buf(int block, int offset, u8 *dst, u32 len);
+int brcmnand_is_bad_block(int block);
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/ddrinit_dpfe.h b/arch/arm/mach-bcmbca/include/ddrinit_dpfe.h
new file mode 100644
index 0000000000..ddeb3cab19
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/ddrinit_dpfe.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _DDRINIT_DPFE_H
+#define _DDRINIT_DPFE_H
+
+#define DPFE_OPTION_SAFEMODE			0x1
+#define DPFE_OPTION_SEG_FIRST			0x2
+#define DPFE_OPTION_SEG_LAST			0x4
+#define DPFE_OPTION_SEG_MASK			(DPFE_OPTION_SEG_FIRST|DPFE_OPTION_SEG_LAST)
+
+typedef struct _dpfe_seg_param {
+	uint8_t* seg_buf;
+	uint32_t buf_size;
+	int seg_id;
+	uint32_t mcb_sel;
+}dpfe_seg_param;
+
+typedef struct _dpfe_param {
+	dpfe_seg_param* seg_param;
+	uint32_t* mcb;
+#ifdef CONFIG_BCMBCA_DDRC_SCRAMBLER
+	uint32_t *seed;
+#endif
+	uint32_t* ddr_size;
+	uint32_t dpfe_option;
+}dpfe_param;
+
+typedef int (*dpfe_func) (dpfe_param* params);
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/dt_helper.h b/arch/arm/mach-bcmbca/include/dt_helper.h
new file mode 100644
index 0000000000..1c6808e673
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/dt_helper.h
@@ -0,0 +1,46 @@
+#define ADSL_BASE_ADDR_STR		"adsl"
+#define PARAM1_BASE_ADDR_STR		"rdp1"
+#define PARAM2_BASE_ADDR_STR		"rdp2"
+#define DHD_BASE_ADDR_STR		"dhd0"
+#define DHD_BASE_ADDR_STR_1		"dhd1"
+#define DHD_BASE_ADDR_STR_2		"dhd2"
+#define PLC_BASE_ADDR_STR		"plc"
+#define OPTEE_BASE_ADDR_STR		"optee"
+#define TZIOC_BASE_ADDR_STR		"tzioc"
+#define CMA_BASE_ADDR_STR		"cma"
+#define CMA_PAD_BASE_ADDR_STR		"pad0"
+#define BUFMEM_BASE_ADDR_STR		"bufmem"
+#define RNRMEM_BASE_ADDR_STR		"rnrmem"
+#define B15_MEGA_BARRIER		"b15_mega_br"
+#define DT_RSVD_PREFIX_STR		"dt_reserved_"
+#define DT_RSVD_NODE_STR		"reserved-memory"
+#define DT_CMA_CACHED_NODE_STR		"plat_rsvmem_cached_device"
+#define DT_CMA_UNCACHED_NODE_STR		"plat_rsvmem_uncached_device"
+#define DT_CMA_RSVSIZE_PROP_STR		"rsvd-size"
+#define DT_ROOT_NODE			"/"
+#define DT_MEMORY_NODE			"memory"
+#define OF_NODE_ADDR_CELLS_DEFAULT	0x2
+#define OF_NODE_SIZE_CELLS_DEFAULT	0x1
+
+#define DT_CHOSEN_NODE			"chosen"
+
+#define DT_BOOTARGS_PROP		"bootargs"
+#define DT_BOOTARGS_MAX_SIZE		1024
+
+
+
+int dtb_set_reserved_memory(void *dtb_ptr, char* name, uint64_t addr, uint64_t size);
+int dtb_del_cma_rsvmem_device(void *dtb_ptr);
+const void *dtb_get_prop(void *dtb_ptr, const char *node_path,
+	const char *property, int *len);
+int dtb_getprop_reg(void *dtb_ptr,
+			const char* node_name_par,
+			const char *node_name,
+			uint64_t* addr,
+			uint64_t* size);
+int dtb_getprop_cma_rsv_param(void *dtb_ptr, const char *node_suffix, const char *name, uint64_t* param);
+int dtb_getprop_cma_rsvmem_size(void *dtb_ptr, const char *name, uint64_t* size);
+int dtb_setprop_cma_rsvmem_size(char* dtb_ptr, const char *name, uint64_t size);
+int dtb_del_cma_rsvmem(void* dtb_ptr, const char *name);
+int dtb_del_reserved_memory(void* dtb_ptr, char* name);
+int dtb_set_bootargs(void *fdt, char* bootargs, int append);
diff --git a/arch/arm/mach-bcmbca/include/early_abort.h b/arch/arm/mach-bcmbca/include/early_abort.h
new file mode 100644
index 0000000000..e578bd6eda
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/early_abort.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _EARLY_ABORT_H
+#define _EARLY_ABORT_H
+typedef enum _spl_ea_status_e {
+	SPL_EA_NONE = 0x0,
+	SPL_EA_DDR3_SAFE_MODE = 0x1,
+	SPL_EA_DDR4_SAFE_MODE = 0x2,
+	SPL_EA_DDR_MCB_SEL = 0x4,
+	SPL_EA_IMAGE_RECOV = 0x8,
+	SPL_EA_IMAGE_FB = 0x10,
+	SPL_EA_IGNORE_BOARDID = 0x20,
+	SPL_EA_JTAG_UNLOCK = 0x40,
+} spl_ea_status_t;
+
+
+typedef struct e_abort_s {
+	spl_ea_status_t status;
+	uint32_t data;
+} early_abort_t;
+
+void early_abort(void);
+early_abort_t* early_abort_info(void);
+#define SPL_EA_TM_MS 60000
+#define SPL_EA_CATCH_TM_MS 200
+#endif
diff --git a/arch/arm/mach-bcmbca/include/mmu_map_v7.h b/arch/arm/mach-bcmbca/include/mmu_map_v7.h
new file mode 100644
index 0000000000..bc72d67ee0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/mmu_map_v7.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef MMU_MAP_V7_H
+#define MMU_MAP_V7_H
+
+
+/*  MMU and TT (Translation Tables) definitions 
+
+   WBWA == Write-Back, Write-Allocate
+   WBNWA == Write-Back, No Write-Allocate
+   WTNWA == Write-Through, No Write-Allocate
+   NC == Non-Cacheable
+   SO == Strongly-Ordered
+   SD == Sharable-Device
+   NSD == Non-Sharable-Device
+*/
+  
+#define DESC_DOMAIN(x)          ((x << 5) & 0x000001E0)
+
+// section descriptor definitions
+#define SECTION_AP              0xc00
+#define SECTION_XN              0x10
+#define SECTION_PXN             0x1
+#if defined(CONFIG_BCM63138)
+/* A9 does not support PXN */
+#define SECTION_XN_ALL          (SECTION_XN)
+#else
+#define SECTION_XN_ALL          (SECTION_XN|SECTION_PXN)
+#endif
+#define SECTION_SHAREABLE       (1 << 16)
+#define SECTION_SUPER_DESC      (1 << 18)
+#define SECTION_DESC_NS         (1 << 19) 
+// TEX[2] = 1
+#define SECTION_OUTER_NC_INNER_WBWA         0x00004006
+#define SECTION_OUTER_WBNWA_INNER_WBWA      0x00007006
+#define SECTION_OUTER_WTNWA_INNER_WBWA      0x00006006
+#define SECTION_OUTER_WBWA_INNER_NC         0x00005002
+// TEX[2] = 0, OUTER & INNER are same all the time
+#define SECTION_OUTER_WBWA_INNER_WBWA       0x0000100E
+#define SECTION_OUTER_NSD_INNER_NSD         0x00002002
+#define SECTION_OUTER_NC_INNER_NC           0x00001002
+#define SECTION_OUTER_WTNWA_INNER_WTNWA     0x0000000A
+#define SECTION_OUTER_WBNWA_INNER_WBNWA     0x0000000E
+#define SECTION_OUTER_SO_INNER_SO           0x00000002
+#define SECTION_OUTER_SD_INNER_SD           0x00000006
+
+// definition for common section attribute 
+#define SECTION_ATTR_INVALID       0x0  
+#define SECTION_ATTR_CACHED_MEM    \
+	(SECTION_OUTER_WBWA_INNER_WBWA|SECTION_AP|DESC_DOMAIN(0))
+#define SECTION_ATTR_NONCACHED_MEM \
+	(SECTION_OUTER_NC_INNER_NC|SECTION_AP|DESC_DOMAIN(0))
+#define SECTION_ATTR_DEVICE        \
+	(SECTION_OUTER_NSD_INNER_NSD|SECTION_AP|SECTION_XN_ALL|DESC_DOMAIN(0))
+#define SECTION_ATTR_DEVICE_EXEC   \
+	(SECTION_OUTER_NSD_INNER_NSD|SECTION_AP|DESC_DOMAIN(0))
+#define SECTION_SET(__PA__,__ATTR__) ((__PA__&0xfff00000)|(__ATTR__&0xfffff))
+
+struct mm_region {
+	phys_addr_t phys;
+#ifdef CONFIG_ARMV7_LPAE
+	uint64_t virt;
+	uint64_t attrs;
+#else
+	uint32_t virt;
+	uint32_t attrs;
+#endif
+	uint32_t size;
+};
+
+extern struct mm_region *mem_map;
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/otp_hw.h b/arch/arm/mach-bcmbca/include/otp_hw.h
new file mode 100644
index 0000000000..8964c745d0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/otp_hw.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _OTP_HW_H
+#define _OTP_HW_H
+
+#include "otp_hw_map.h"
+
+/*
+ * includes common OTP controller offsets
+ * */
+
+#define OTP_STATUS_CMD_DONE_TMO_CNT 		65536
+#define OTP_CPU_LOCK_TMO_CNT 			65536
+
+
+#if defined (CONFIG_OTP_V1)
+/* 40nm SoC */
+
+#define OTP_CTRL0_ACCESS_MODE			(0x2 << 22)
+#define OTP_CTRL0_PROG_EN			(0x1 << 21)
+#define OTP_CTRL0_START				(0x1 << 0)
+#define OTP_CTRL0_CMD_OTP_PROG_EN		(0x2 << 1)
+#define OTP_CTRL0_CMD_PROG			(0xA << 1)
+#define OTP_CTRL0_CMD_PROG_LOCK			(0x19 << 1)
+
+#define OTP_CTRL0_PROG_MODE_ENABLE		(OTP_CTRL0_START|OTP_CTRL0_PROG_EN|OTP_CTRL0_CMD_OTP_PROG_EN)
+#define OTP_CTRL0_PROG_CMD_START		(OTP_CTRL0_START|OTP_CTRL0_CMD_PROG|OTP_CTRL0_ACCESS_MODE|OTP_CTRL0_PROG_EN)
+
+#define OTP_CTRL0_OFFSET			0x0
+
+#define OTP_CTRL1_CPU_MODE			(1 << 0)
+#define OTP_CTRL1_OFFSET			0x4
+#define OTP_CTRL2_OFFSET			0x8
+#define OTP_CTRL3_OFFSET			0xC
+
+#define OTP_STATUS0_OFFSET			0x14
+
+#define OTP_STATUS1_PROG_OK			(1 << 2)
+#define OTP_STATUS1_CMD_DONE			(1 << 1)
+#define OTP_STATUS1_OFFSET			0x18
+
+#elif defined(CONFIG_OTP_V2) || defined(CONFIG_OTP_V3)
+
+/*  28-16nm SoC */
+#define OTP_CTRL0_START				(0x1 << 0)
+#define OTP_CTRL0_CMD_OTP_PROG_EN		(0x2 << 1)
+#define OTP_CTRL0_CMD_PROG			(0xA << 1)
+#define OTP_CTRL0_CMD_PROG_LOCK			(0x19 << 1)
+#define OTP_CTRL0_PROG_MODE_ENABLE		(OTP_CTRL0_START|OTP_CTRL0_CMD_OTP_PROG_EN)
+#define OTP_CTRL0_PROG_CMD_START		(OTP_CTRL0_START|OTP_CTRL0_CMD_PROG) 
+#define OTP_CTRL0_OFFSET			0x0
+
+#define OTP_CTRL1_CPU_MODE			(1 << 0)
+#define OTP_CTRL1_OFFSET			0x4
+#define OTP_CTRL2_OFFSET			0x8
+#define OTP_CTRL2_HI_OFFSET			0xC
+#define OTP_CTRL3_OFFSET			0x10
+
+#define OTP_STATUS0_OFFSET			0x18
+#define OTP_STATUS0_HI_OFFSET			0x1C
+
+#define OTP_STATUS1_PROG_OK			(1 << 2)
+#define OTP_STATUS1_CMD_DONE			(1 << 1)
+#define OTP_STATUS1_OFFSET			0x20
+
+
+#define OTP_CPU_LOCK_SHIFT			0x0
+#define OTP_CPU_LOCK_MASK			0x1
+
+
+#if defined(CONFIG_OTP_LOCK)
+
+#if defined(CONFIG_OTP_V3)
+/* 16nm SoC*/
+#define OTP_CPU_LOCK_OFFSET			0x54
+#else
+#define OTP_CPU_LOCK_OFFSET			0x70
+#endif
+
+#endif
+#else
+
+#error OTP controller is not defined  
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/otp_hw_cmn.h b/arch/arm/mach-bcmbca/include/otp_hw_cmn.h
new file mode 100644
index 0000000000..e7f0287275
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/otp_hw_cmn.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+#ifndef _OTP_HW_CMN_H_
+#define _OTP_HW_CMN_H_
+
+
+/* Generic OTP controller Interface */
+
+typedef struct otp_hw_cmn_s otp_hw_cmn_t;
+
+typedef enum otp_hw_cmn_err_e{
+   OTP_HW_CMN_OK = 0,
+   OTP_HW_CMN_ERR_FAIL = -1,
+   OTP_HW_CMN_ERR_UNSP = -2,
+   OTP_HW_CMN_ERR_KEY_EMPTY = -3,
+   OTP_HW_CMN_ERR_DESC_ECC = -4,
+   OTP_HW_CMN_ERR_DATA_ECC = -5, 
+   OTP_HW_CMN_ERR_TMO = -6,
+   OTP_HW_CMN_ERR_INVAL = -7,
+   OTP_HW_CMN_ERR_BAD_PARAM = -8,
+   OTP_HW_CMN_ERR_WRITE_FAIL= -9,
+} otp_hw_cmn_err_t;
+
+
+
+
+/*status command to use in control function*/
+/*  
+ * (N)SRD - (Non)Secure Master Read 
+ * (N)SW - (Non)Secure Master Write 
+ * S - Secure  
+ * PAC - peripheral access control either block or registers  
+ *  - Secure Master Write 
+ * */
+typedef enum otp_hw_cmn_status_e{
+   OTP_HW_CMN_STATUS_UNLOCKED		= 0x0,
+   OTP_HW_CMN_STATUS_SRD_LOCKED		= 0x1,
+   OTP_HW_CMN_STATUS_SW_LOCKED		= 0x2,
+   OTP_HW_CMN_STATUS_NSRD_LOCKED	= 0x4,
+   OTP_HW_CMN_STATUS_NSW_LOCKED		= 0x8,
+   OTP_HW_CMN_STATUS_SW_PAC_LOCKED	= 0x10,
+   OTP_HW_CMN_STATUS_NSW_PAC_LOCKED	= 0x20,
+   OTP_HW_CMN_STATUS_SRD_PAC_LOCKED	= 0x40,
+   OTP_HW_CMN_STATUS_NSRD_PAC_LOCKED	= 0x80,
+   OTP_HW_CMN_STATUS_NS_LOCKED 		= 0x100,
+   OTP_HW_CMN_STATUS_S_LOCKED 		= 0x200,
+   OTP_HW_CMN_STATUS_ROW_W_LOCKED 	= 0x400,
+   OTP_HW_CMN_STATUS_ROW_RD_LOCKED 	= 0x800,
+   OTP_HW_CMN_STATUS_ROW_DATA_VALID	= 0x1000
+} otp_hw_cmn_status_t;
+
+/*generic lock command to use in control function*/
+/*  
+ * (N)SRD - (Non)Secure Master Read 
+ * (N)SW - (Non)Secure Master Write 
+ * S - Secure  
+ * PAC - peripheral access control either block or registers  
+ *  - Secure Master Write 
+ * */
+typedef enum otp_hw_cmn_perm_e{
+   OTP_HW_CMN_CTL_LOCK_NONE 		= 0x0,
+   OTP_HW_CMN_CTL_LOCK_PAC_SW 		= 0x1,
+   OTP_HW_CMN_CTL_LOCK_PAC_NSW 		= 0x2,
+   OTP_HW_CMN_CTL_LOCK_PAC_NSRD 	= 0x4,
+   OTP_HW_CMN_CTL_LOCK_PAC_SRD 		= 0x8,
+   OTP_HW_CMN_CTL_LOCK_SRD 		= 0x10,
+   OTP_HW_CMN_CTL_LOCK_NSRD 		= 0x20,
+   OTP_HW_CMN_CTL_LOCK_SW 		= 0x40,
+   OTP_HW_CMN_CTL_LOCK_NSW 		= 0x80,
+   OTP_HW_CMN_CTL_LOCK_ALL 		= 0x100,
+   OTP_HW_CMN_CTL_LOCK_NS 		= 0x200,
+   OTP_HW_CMN_CTL_LOCK_NS_PROV 		= 0x400,
+   OTP_HW_CMN_CTL_LOCK_S 		= 0x800,
+   OTP_HW_CMN_CTL_LOCK_ROW_RD 		= 0x1000,
+   OTP_HW_CMN_CTL_LOCK_ROW_W 		= 0x2000,
+} otp_hw_cmn_perm_t;
+/* container for the control call*/
+typedef struct _otp_hw_ctl_data_s {
+	u32 addr;
+	union {
+		otp_hw_cmn_perm_t perm;
+		otp_hw_cmn_status_t status;
+	};
+} otp_hw_ctl_data_t;
+
+/* generic OTP command options*/
+typedef enum otp_hw_cmn_ctl_e {
+   OTP_HW_CMN_CTL_NONE			= 0x0,
+   OTP_HW_CMN_CTL_STATUS 		= 0x1,
+   OTP_HW_CMN_CTL_LOCK 			= 0x2,
+   OTP_HW_CMN_CTL_UNLOCK 		= 0x4,
+   OTP_HW_CMN_CTL_OTPCMD_AUTH_PROG	= 0x8,
+   OTP_HW_CMN_CTL_OTPCMD_AUTH_PROG_DONE	= 0x10,
+   OTP_HW_CMN_CTL_OTPCMD_ECC 		= 0x20,
+   OTP_HW_CMN_CTL_OTPCMD_ECC_WREAD 	= 0x40,
+   OTP_HW_CMN_CTL_OTPCMD_PROG_LOCK 	= 0x80,
+   OTP_HW_CMN_CTL_CONF			= 0x100
+} otp_hw_cmn_ctl_t;
+
+/* generic row id*/
+typedef enum otp_hw_cmn_row_addr_type_e{
+   OTP_HW_CMN_ROW_ADDR_NONE = 0x0,
+   OTP_HW_CMN_ROW_ADDR_ROW,
+} otp_hw_cmn_row_addr_type_t;
+
+
+/* a control functions argument */
+typedef struct _otp_hw_ctl_data_ {
+	otp_hw_cmn_ctl_t ctl;
+	uintptr_t data;
+	u32 size;
+} otp_hw_cmn_ctl_cmd_t;
+
+/* a row configuration container */
+typedef struct otp_hw_row_conf_s {
+	otp_hw_cmn_ctl_t	op_type;
+	otp_hw_cmn_row_addr_type_t addr_type;
+	ulong perm;
+	uintptr_t arg;
+} otp_hw_cmn_row_conf_t;
+
+/* a row data container with map to feature name*/
+typedef struct otp_hw_cmn_row_s {
+	otp_map_feat_t feat;
+	u32 addr;
+	u32 mask;
+	u32 shift;
+	u32 range;
+	otp_hw_cmn_row_conf_t conf;
+	union {
+		u8* pdata;
+		u32 data;
+	};
+	u32 valid;	
+} otp_hw_cmn_row_t;
+
+/* otp hw object */
+struct otp_hw_cmn_s {
+	//Driver which is implemented elsewhere
+	otp_hw_cmn_t *drv_ext;	
+	uintptr_t mm;
+	otp_hw_cmn_row_t *rows;
+	u32 row_max;
+	otp_hw_cmn_row_conf_t row_conf;
+	otp_hw_cmn_ctl_cmd_t ctl_cmd;
+	/* reads one or more rows from the device*/
+	otp_hw_cmn_err_t (*read)(otp_hw_cmn_t *dev,
+			u32 addr,
+			u32 *,
+			u32);
+
+	/* writes one or more rows to the device*/
+	otp_hw_cmn_err_t (*write)(otp_hw_cmn_t *,
+			u32 addr,
+			const u32 *,
+			u32 );
+	/* reads  one or more rows from the device based on otp_hw_cmn_row_conf_t - does not require
+ 	*  feature map
+ 	* */
+	otp_hw_cmn_err_t (*read_ex)(otp_hw_cmn_t *dev,
+			u32 addr,
+			otp_hw_cmn_row_conf_t *,
+			u32 *,
+			u32);
+	/* writes  one or more rows to the device based on otp_hw_cmn_row_conf_t 
+ 	* 	- does not require
+ 	*  feature map
+ 	* */
+	otp_hw_cmn_err_t (*write_ex)(otp_hw_cmn_t *,
+			u32 addr,
+			otp_hw_cmn_row_conf_t *,
+			const u32 *,
+			u32 );
+ 
+	/* control various device functions such as:
+	*	-lock
+	*	-status
+ 	*   based on otp_hw_cmdn_ctl_cmd_t content 
+ 	* */
+	otp_hw_cmn_err_t (*ctl)(otp_hw_cmn_t *dev, 
+			const otp_hw_cmn_ctl_cmd_t *cmd,
+			u32* res);
+};
+/* on init pointer */
+typedef otp_hw_cmn_err_t  (*otp_hw_cmn_init_t)(otp_hw_cmn_t* );
+
+#endif
+
+
diff --git a/arch/arm/mach-bcmbca/include/otp_hw_map.h b/arch/arm/mach-bcmbca/include/otp_hw_map.h
new file mode 100644
index 0000000000..370f42aab4
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/otp_hw_map.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _OTP_HW_MAP_H
+#define _OTP_HW_MAP_H
+
+/*
+ * includes common OTP map rows for JTAG password
+ * */
+#if defined (CONFIG_OTP_V1)
+
+#define OTP_JTAG_SER_NUM_ROW_1          	19          // Row19[25:20] = CSEC_CHIPID[5:0]
+#define OTP_JTAG_SER_NUM_MASK_1         	0x0000003F
+#define OTP_JTAG_SER_NUM_REG_SHIFT_1    	20
+#define OTP_JTAG_SER_NUM_ROW_2          	20          // Row20[25:0]  = CSEC_CHIPID[31:6]
+#define OTP_JTAG_SER_NUM_MASK_2         	0x03FFFFFF
+#define OTP_JTAG_SER_NUM_SHIFT_2        	6
+#define OTP_JTAG_PWD_ROW_1              	21          // Row21[25:0]  = CSEC_PWD[25:0]
+#define OTP_JTAG_PWD_ROW_2              	22          // Row22[25:0]  = CSEC_PWD[51:26]
+#define OTP_JTAG_PWD_ROW_3              	23          // Row23[11:0]  = CSEC_PWD[63:52]
+#define OTP_JTAG_PWD_MASK_1             	0x03FFFFFF
+#define OTP_JTAG_PWD_MASK_2             	0x03FFFFFF
+#define OTP_JTAG_PWD_MASK_3             	0x00000FFF
+#define OTP_JTAG_PWD_SHIFT_1            	0
+#define OTP_JTAG_PWD_SHIFT_2            	26
+#define OTP_JTAG_PWD_SHIFT_3            	52
+#define OTP_JTAG_PWD_RDLOCK_ROW         	23
+#define OTP_JTAG_PWD_RDLOCK_REG_SHIFT   	25          // Row23[25]
+
+#define OTP_JTAG_MODE_ROW               	18
+#define OTP_JTAG_MODE_REG_SHIFT         	9
+#define OTP_JTAG_MODE_LOCK              	0x38
+#define OTP_JTAG_MODE_PERMALOCK         	0x3F
+#define OTP_JTAG_MODE_MASK			0x3F
+
+#define OTP_JTAG_CUST_LOCK_ROW          	6
+#define OTP_JTAG_CUST_LOCK_VAL          	0x1F
+#define OTP_JTAG_CUST_LOCK_REG_SHIFT    	25
+
+
+
+#elif defined (CONFIG_OTP_V2)
+
+
+#define OTP_JTAG_MODE_ROW               18
+#define OTP_JTAG_MODE_REG_SHIFT         9
+#define OTP_JTAG_MODE_LOCK              0x38
+#define OTP_JTAG_MODE_PERMALOCK         0x3F
+#define OTP_JTAG_MODE_MASK              0x3F
+
+#define OTP_JTAG_SER_NUM_ROW            20          // Row20 = CSEC_CHIPID
+#define OTP_JTAG_SER_NUM_SHIFT		0x0
+#define OTP_JTAG_SER_NUM_MASK		0xFFFFFFFF
+
+#define OTP_JTAG_PWD_ROW_1              21          // Row21 = CSEC_JTAGPWD[31:0]
+#define OTP_JTAG_PWD_SHIFT_1            0
+#define OTP_JTAG_PWD_MASK_1             0xFFFFFFFF
+
+#define OTP_JTAG_PWD_ROW_2              22          // ROW22 = CSEC_JTAGPWD[63:32]
+#define OTP_JTAG_PWD_MASK_2             0xFFFFFFFF
+#define OTP_JTAG_PWD_SHIFT_2		0x0  //was 31 why?
+
+/* row 19 */
+#define OTP_JTAG_PWD_RDLOCK_ROW		19          // ROW19[31]
+#define OTP_JTAG_PWD_RDLOCK_SHIFT	31
+#define OTP_JTAG_PWD_RDLOCK_MASK	0x1	
+
+/* row 6 */
+/* This is a section LOCKING row - whole section getting locked
+ * either CUSTomer( USER2)
+ * rows 18-25 are locked 
+ *
+ * */
+#define OTP_JTAG_CUST_LOCK_ROW          6
+#define OTP_JTAG_CUST_LOCK_SHIFT	25
+#define OTP_JTAG_CUST_LOCK_MASK		0x1F
+#define OTP_JTAG_CUST_LOCK_VAL          0x1F
+
+
+#elif defined (CONFIG_OTP_V3)
+
+
+/* row 14 */
+#define OTP_JTAG_MODE_ROW               	14 /* 0 -fully open; 2 - pwd protected; 3 fully closed*/
+#define OTP_JTAG_MODE_SHIFT         		16
+#define OTP_JTAG_MODE_MASK         		0x3
+#define OTP_JTAG_MODE_LOCK              	0x2
+#define OTP_JTAG_MODE_PERMALOCK         	0x3
+
+/* row 26 */
+#define OTP_JTAG_SER_NUM_ROW          		26          // Row26 = CSEC_JTAGID[31:0] (formerly CSEC_CHIPID) 
+#define OTP_JTAG_SER_NUM_SHIFT			0x0
+#define OTP_JTAG_SER_NUM_MASK			0xFFFFFFFF
+
+/* row 27 */
+#define OTP_JTAG_PWD_ROW_1              	27          // Row27 = CSEC_JTAGPWD[31:0]
+#define OTP_JTAG_PWD_SHIFT_1            	0
+#define OTP_JTAG_PWD_MASK_1             	0xFFFFFFFF
+
+/* row 28 */
+#define OTP_JTAG_PWD_ROW_2              	28          // ROW28 = CSEC_JTAGPWD[63:32]
+#define OTP_JTAG_PWD_SHIFT_1            	0
+#define OTP_JTAG_PWD_MASK_2             	0xFFFFFFFF
+
+/* row 14 */
+#define OTP_JTAG_PWD_RDLOCK_ROW         	14          // ROW14[25] (formerly CSEC_READLOCK) 
+#define OTP_JTAG_PWD_RDLOCK_SHIFT       	25	
+#define OTP_JTAG_PWD_RDLOCK_MASK         	0x1 
+
+
+#else
+
+#error OTP MAP is not defined  
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/otp_map.h b/arch/arm/mach-bcmbca/include/otp_map.h
new file mode 100644
index 0000000000..891d3abace
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/otp_map.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#ifndef _OTP_MAP_H
+#define _OTP_MAP_H
+/*  
+ * 	OTP feature map.
+ * 	An OTP field named in the corresponding SoC e.g 63138-63146 or 6858-6855 is being assigned a feature name
+ * 	OTP map feature name closely resembles a specific OTP map row name. Other entries server as delimiters. 
+ * 	This allows to unify access to OTP map across all SoCs  	
+ * 	Whenever new otp field is needed to be read or fused it neets to be declared here and subsequently mapped in
+ * 	the driver initilizer function to the feature name
+ * 	Example:
+ * 	OTP_MAP_LDO_TRIM -feature name 
+ * 	OTP_MAP_LDO_TRIM_ROW - as defined in otp specific arch 
+ *
+ *  */
+typedef enum otp_map_feat {
+	OTP_MAP_INVALID = 0,
+	OTP_MAP_SEC_CHIPVAR,
+	OTP_MAP_LDO_TRIM,
+	OTP_MAP_CPU_CLOCK_FREQ,
+	OTP_MAP_PMC_BOOT,
+	OTP_MAP_PCM_DISABLE,
+	OTP_MAP_CPU_CORE_CFG,
+	OTP_MAP_SGMII_DISABLE,
+	OTP_MAP_SATA_DISABLE,
+	OTP_MAP_BRCM_BTRM_BOOT_ENABLE,
+	OTP_MAP_CUST_BTRM_BOOT_ENABLE,
+	OTP_MAP_BRCM_ENFORCE_BINIT,
+	OTP_MAP_CUST_MFG_MRKTID,
+	OTP_MAP_BRCM_PRODUCTION_MODE,
+	OTP_MAP_CUST_OP_INUSE,
+	SOTP_MAP_INVALID,
+	SOTP_MAP_FLD_ROE,
+	SOTP_MAP_FLD_HMID,
+	SOTP_MAP_KEY_DEV_SPECIFIC,
+	SOTP_MAP_SER_NUM,
+	SOTP_MAP_KEY_SECT_1,
+	SOTP_MAP_KEY_SECT_2,
+	SOTP_MAP_KEY_SECT_3,
+	SOTP_MAP_KEY_SECT_4,
+	SOTP_MAP_KEY_SECT_5,
+	SOTP_MAP_ANTI_ROLLBACK,
+	SOTP_MAP_UNUSED_1,
+	SOTP_MAP_UNUSED_2,
+	SOTP_MAP_UNUSED_3,
+	SOTP_MAP_UNUSED_4,
+	SOTP_MAP_UNUSED_5,
+	SOTP_MAP_UNUSED_6,
+	SOTP_MAP_UNUSED_7,
+	OTP_MAP_MAX
+} otp_map_feat_t;
+
+
+
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/otp_map_cmn.h b/arch/arm/mach-bcmbca/include/otp_map_cmn.h
new file mode 100644
index 0000000000..bff6c8da15
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/otp_map_cmn.h
@@ -0,0 +1,45 @@
+#ifndef __OTP_MAP_CMN_H
+#define __OTP_MAP_CMN_H
+
+#include "otp_map.h"
+#include "otp_hw_cmn.h"
+
+/* Generic OTP MAP Interface */
+typedef struct _otp_map_cmn otp_map_cmn_t;
+
+typedef enum _otp_map_cmn_err_ {
+   OTP_MAP_CMN_OK = 0,
+   OTP_MAP_CMN_ERR_FAIL = -1,
+   OTP_MAP_CMN_ERR_UNSP = -2,
+   OTP_MAP_CMN_ERR_INVAL= -3,
+} otp_map_cmn_err_t;
+
+
+struct _otp_map_cmn {
+	otp_hw_cmn_t dev;
+	otp_hw_cmn_init_t dev_init;
+	/* 
+ 	* fuse/write feature.   Feed  with data aray of u32 and size 
+ 	* */
+	otp_map_cmn_err_t (*write)(otp_map_cmn_t*, u32, const u32*, u32);
+	/* 
+ 	* reads  feature content. Return data pointer and its size 
+ 	* */
+	otp_map_cmn_err_t (*read)(otp_map_cmn_t*, u32, u32**, u32*);
+	/* control various functions such as:
+	*	-lock
+	*	-status
+ 	*   based on otp_hw_cmd_ctl_cmd_t content 
+ 	* */
+	otp_map_cmn_err_t (*ctl)(otp_map_cmn_t*, otp_hw_cmn_ctl_cmd_t*, u32*);
+};
+/* An initializer for otp_map_cmnt_t obj. 
+ * Accept external driver object with an initializer function  */
+otp_map_cmn_err_t otp_map_cmn_init(otp_map_cmn_t* map,
+			otp_hw_cmn_init_t hw_init,  
+			otp_hw_cmn_t* ext_drv);
+
+otp_hw_cmn_err_t otp_hw_cmn_init(otp_hw_cmn_t* dev);
+otp_hw_cmn_err_t sotp_hw_cmn_init(otp_hw_cmn_t* dev);
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/pinctrl.h b/arch/arm/mach-bcmbca/include/pinctrl.h
new file mode 100644
index 0000000000..122ea4462c
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/pinctrl.h
@@ -0,0 +1,25 @@
+#include <common.h>
+
+
+#define PINMUX_ADDR_SHIFT       0
+#define PINMUX_ADDR_MASK        (0xfff<<PINMUX_ADDR_SHIFT)
+#define PINMUX_DATA_SHIFT       12
+#define PINMUX_DATA_MASK        (0x3f<<PINMUX_DATA_SHIFT)
+
+#define LOAD_MUX_REG_CMD        0x21
+#define LOAD_PAD_CTRL_CMD       0x22
+#define LOAD_SELECT_CMD         0x23
+
+/*===================================================*/
+
+typedef struct pinctrl_reg {
+	uint32_t TestPortBlockDataMSB;
+	uint32_t TestPortBlockDataLSB;
+	uint32_t TestPortCmd;
+	uint32_t DiagReadBack;
+	uint32_t DiagReadBackHi;
+}pinctrl_reg;
+
+/* pinmux function */
+int bcmbca_pinmux_set (volatile struct pinctrl_reg *regp, int pin, int func);
+
diff --git a/arch/arm/mach-bcmbca/include/pmc_drv.h b/arch/arm/mach-bcmbca/include/pmc_drv.h
new file mode 100755
index 0000000000..d9061e4ffd
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/pmc_drv.h
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+/*
+ 
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      This contains header for PMC driver.
+ *****************************************************************************/
+
+#ifndef PMC_DRV_H
+#define PMC_DRV_H
+
+#include "asm/arch/pmc_drv_cfg.h"
+
+#ifndef CONFIG_SPL_BUILD
+#define CFG_RAMAPP
+#endif
+
+#include <common.h>
+
+#if defined(CONFIG_BCMBCA_IKOS) && !defined(CONFIG_BRCM_IKOS)
+#define CONFIG_BRCM_IKOS
+#endif
+
+#ifndef EXPORT_SYMBOL
+#define EXPORT_SYMBOL(a)
+#endif
+
+#ifndef IS_BCMCHIP
+#define IS_BCMCHIP(num) (defined(_BCM9##num##_) || \
+		defined(CONFIG_BCM9##num) || defined(CONFIG_BCM##num))
+#endif
+
+#if defined(__ASSEMBLER__) && !defined(_LANGUAGE_ASSEMBLY)
+#define _LANGUAGE_ASSEMBLY 
+#endif
+
+#include <asm/arch/pmc_addr.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/misc.h>
+
+#define MAX_PMC_ROM_SIZE    0x8000
+#define MAX_PMC_LOG_SIZE    0x8000
+
+/* PMC reserved area.
+   **NOTE**: Please make sure it matches with
+   shared/opensource/include/bcm963xx/bcm_mem_reserve.h
+*/
+#define PMC_RESERVED_MEM_START  0x000C0000
+#define PMC_RESERVED_MEM_SIZE   0x00040000	// Total PMC reserved memory size 256KB
+#define CFG_BOOT_PMC_LOG_SIZE   0x00010000	// Leave 64K reserved memory for PMC log
+
+
+#define CFG_BOOT_PMC_ADDR       (PMC_RESERVED_MEM_START)
+#define CFG_BOOT_PMC_SIZE       (PMC_RESERVED_MEM_SIZE  - CFG_BOOT_PMC_LOG_SIZE) // Memory reserved for PMC firmware
+#define CFG_BOOT_PMC_LOG_ADDR   (PMC_RESERVED_MEM_START + CFG_BOOT_PMC_SIZE)
+
+#if MAX_PMC_ROM_SIZE + MAX_PMC_LOG_SIZE > CFG_BOOT_PMC_SIZE
+#error ROM and LOG buffer size needs to be re-adjusted
+#endif
+
+#ifndef _LANGUAGE_ASSEMBLY 
+#define pmc_spin_lock(...) do { } while (0)
+#define pmc_spin_unlock(...) do { } while (0)
+
+extern int getAVSConfig(void);
+extern int is_pmcfw_code_loaded(void);
+extern int is_pmcfw_data_loaded(void);
+
+#define cache_to_uncache(va) (va)
+
+#define console_status serial_tstc
+
+#ifndef phys_to_virt
+#define phys_to_virt(a) (a)
+#endif
+
+#endif // #ifndef _LANGUAGE_ASSEMBLY 
+
+#ifndef PMC_IN_MAIN_LOOP 
+    #define PMC_IN_MAIN_LOOP	6
+#endif
+
+#ifndef PMC_BOOT_TMO_SECONDS
+    #define PMC_BOOT_TMO_SECONDS	0
+#endif
+
+/* there are 32 DQM, since REPLY DQM will always be one after the REQUEST
+ * DQM, we should use use 0 to 30 for REQ DQM, so RPL DQM will be 1 to 31 */
+/* 63138 has pair of DQM#0+DQM#1, #2+#3, #4+#5, and #6+#7.  We will use
+ * DQM#0+DQM#1 pair */
+#define PMC_DQM_REQ_NUM		0
+
+#define PMC_DQM_RPL_NUM		(PMC_DQM_REQ_NUM + 1)
+#define PMC_DQM_RPL_STS		(1 << PMC_DQM_RPL_NUM)
+
+#define PMC_MODE_DQM		0
+#define PMC_MODE_PMB_DIRECT	1
+#ifdef PMC_IMPL_3_X
+#define PMC_ACCESS_BPCM_DIRECT	1
+#else
+#define PMC_ACCESS_BPCM_DIRECT	0
+#endif
+
+#ifndef _LANGUAGE_ASSEMBLY
+// ---------------------------- Returned error codes --------------------------
+enum {
+	// 0..15 may come from either the interface or from the PMC command handler
+	// 256 or greater only come from the interface
+	kPMC_NO_ERROR,
+	kPMC_INVALID_ISLAND,
+	kPMC_INVALID_DEVICE,
+	kPMC_INVALID_ZONE,
+	kPMC_INVALID_STATE,
+	kPMC_INVALID_COMMAND,
+	kPMC_LOG_EMPTY,
+	kPMC_INVALID_PARAM,
+	kPMC_BPCM_READ_TIMEOUT,
+	kPMC_INVALID_BUS,
+	kPMC_INVALID_QUEUE_NUMBER,
+	kPMC_QUEUE_NOT_AVAILABLE,
+	kPMC_INVALID_TOKEN_SIZE,
+	kPMC_INVALID_WATERMARKS,
+	kPMC_INSUFFICIENT_QSM_MEMORY,
+	kPMC_INVALID_BOOT_COMMAND,
+	kPMC_BOOT_FAILED,
+	kPMC_COMMAND_TIMEOUT = 256,
+	kPMC_MESSAGE_ID_MISMATCH,
+};
+
+// ---------------------------- Returned log entry structure --------------------------
+typedef struct {
+	uint8_t reserved;
+	uint8_t logMsgID;
+	uint8_t errorCode;
+	uint8_t logCmdID;
+	uint8_t srcPort;
+	uint8_t e_msgID;
+	uint8_t e_errorCode;
+	uint8_t e_cmdID;
+	struct {
+		uint32_t logReplyNum:8;
+		uint32_t e_Island:4;
+		uint32_t e_Bus:2;
+		uint32_t e_DevAddr:8;
+		uint32_t e_Zone:10;
+	} s;
+	uint32_t e_Data0;
+} TErrorLogEntry;
+
+// ---------------------------- Power states --------------------------
+enum {
+	kPMCPowerState_Unknown,
+	kPMCPowerState_NoPower,
+	kPMCPowerState_LowPower,
+	kPMCPowerState_FullPower,
+};
+
+// PMC run-state:
+enum {
+	kPMCRunStateExecutingBootROM = 0,
+	kPMCRunStateWaitingBMUComplete,
+	kPMCRunStateAVSCompleteWaitingForImage,
+	kPMCRunStateAuthenticatingImage,
+	kPMCRunStateAuthenticationFailed,
+	kPMCRunStateReserved,
+	kPMCRunStateStalled,
+	kPMCRunStateRunning
+};
+
+// the only valid "gear" values for "SetClockGear" function
+enum {
+	kClockGearLow,
+	kClockGearHigh,
+	kClockGearDynamic,
+	kClockGearBypass
+};
+
+// PMC Boot options ( parameter for pmc_boot function )
+enum {
+	kPMCBootDefault = 0,
+	kPMCBootAVSDisable,
+	kPMCBootAVSTrackDisable,
+	kPMCBootLogBuffer,
+	kPMCBootLogSize
+};
+
+// int TuneRunner(void);
+// int GetSelect0(void);
+// int GetSelect3(void);
+int pmc_init(void);
+void pmc_reset(void);
+void pmc_initmode(void);
+// int get_pmc_boot_param(unsigned boot_option, unsigned *boot_param);
+void pmc_log(int log_type);
+void pmc_save_log_item(void);
+void pmc_show_log_item(void);
+int read_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t * value);
+int write_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t value);
+int GetRevision(unsigned int *change, unsigned int *revision);
+int GetPVT(int sel, int island, int *value);
+int GetRCalSetting(int resistor, int *rcal);
+int GetDevPresence(int devAddr, int *value);
+int GetSWStrap(int devAddr, int *value);
+int GetHWRev(int devAddr, int *value);
+int GetNumZones(int devAddr, int *value);
+int GetAvsDisableState(int island, int *state);
+int Ping(void);
+int GetErrorLogEntry(TErrorLogEntry * logEntry);
+int SetClockHighGear(int devAddr, int zone, int clkN);
+int SetClockLowGear(int devAddr, int zone, int clkN);
+int SetClockGear(int devAddr, int zone, int gear);
+int SetRunState(int island, int state);
+int SetPowerState(int island, int state);
+#if !defined(PMC_ON_HOSTCPU)
+void BootPmcNoRom(unsigned long physAddr);
+#endif
+int ReadBPCMRegister(int devAddr, int wordOffset, uint32_t * value);
+int WriteBPCMRegister(int devAddr, int wordOffset, uint32_t value);
+int ReadZoneRegister(int devAddr, int zone, int wordOffset, uint32_t * value);
+int WriteZoneRegister(int devAddr, int zone, int wordOffset, uint32_t value);
+int PowerOnDevice(int devAddr);
+int PowerOffDevice(int devAddr, int repower);
+int PowerOnZone(int devAddr, int zone);
+int PowerOffZone(int devAddr, int zone);
+int ResetDevice(int devAddr);
+int ResetZone(int devAddr, int zone);
+int CloseAVS(int island, unsigned short margin_mv_slow,
+	     unsigned short margin_mv_fast, unsigned short maximum_mv,
+	     unsigned short minimum_mv);
+int RecloseAVS(int iscold);
+void WaitPmc(int runState, void* pmc_log);
+int StallPmc(void);
+int UnstallPmc(void);
+int GetAllROs(void *shmem);
+
+enum pvtctl_sel {
+	kTEMPERATURE = 0,
+	kV_0p85_0 = 1,
+	kV_0p85_1 = 2,
+	kV_VIN = 3,
+	kV_1p00_1 = 4,
+	kV_1p80 = 5,
+	kV_3p30 = 6,
+	kTEST = 7,
+};
+int pmc_convert_pvtmon(int sel, int value);
+int pmc_get_tracktemp(int *status);
+int pmc_set_tracktemp(int enable);
+#endif //_LANGUAGE_ASSEMBLY
+
+#endif // PMC_DRV_H
diff --git a/arch/arm/mach-bcmbca/include/sko.h b/arch/arm/mach-bcmbca/include/sko.h
new file mode 100755
index 0000000000..d64ae045d1
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/sko.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+#ifndef _SKO_H
+#define _SKO_H
+
+/* SECURE KEY OBJECT - SKO */
+
+
+#define SKO_BASE 0xff804000
+
+
+#define SKO_KEYN_PAC_CNTRL_SHIFT        	0x0
+#define SKO_KEYN_PAC_CNTRL_MASK         	0xffffffff
+#define SKO_KEYN_PAC_CTRL_OFFSET		0x00 
+      
+#define SKO_KEYN_STATUS_SHIFT           	31
+#define SKO_KEYN_STATUS_MASK            	1
+#define SKO_KEYN_STATUS_OFFSET			0x04
+       
+#define SKO_KEYN_CONTROL_SHIFT           	31
+#define SKO_KEYN_CONTROL_MASK            	1
+#define SKO_KEYN_CTRL_OFFSET                    0x0C
+      
+#define SKO_KEYN_DATA_SHIFT             	0x0
+#define SKO_KEYN_DATA_MASK              	0xffffffff 
+#define SKO_KEYN_DATA_OFFSET                    0x10 
+
+#define SKO_SIZE				0x40
+ 
+#define SKO_KEY_DATA_GOOD(_R_)			((_R_ >> SKO_KEYN_STATUS_SHIFT)&SKO_KEYN_STATUS_MASK) 
+
+#define SKO_ROW_SHIFT				0
+#define SKO_ROW_MASK				0xffffffff
+
+#define SKO_0_DESC_CONF				0x9b009000
+#define SKO_0_CTL_CONF				0x80000000
+#define SKO_0_DESC_ROW				42
+#define SKO_0_CTL_ROW				46
+#define SKO_0_DATA_ROW				47
+#define SKO_0_CRC_ROW				55
+
+#define SKO_1_DESC_CONF				0x9b01300a
+#define SKO_1_CTL_CONF				0x80000000
+#define SKO_1_DESC_ROW				43
+#define SKO_1_CTL_ROW				56
+#define SKO_1_DATA_ROW				57
+#define SKO_1_CRC_ROW				65
+
+/*Block bits are sticky until reset */
+#define SKO_PAC_MASK				0xff
+#define SKO_PERM_PAC_KEY_SHIFT			0x4
+#define SKO_PERM_PAC_SHIFT			0x0
+#define SKO_PAC_PERM_MASK			0xf
+
+#define SKO_PAC_LOCK_MASK			0x1
+
+#define SKO_PAC_KEY_SW_LOCK_SHIFT		7
+#define SKO_PAC_KEY_SR_LOCK_SHIFT		6
+#define SKO_PAC_KEY_NSW_LOCK_SHIFT		5
+#define SKO_PAC_KEY_NSR_LOCK_SHIFT		4
+#define SKO_PAC_PERM_SW_LOCK_SHIFT		3	
+#define SKO_PAC_PERM_SR_LOCK_SHIFT		2
+#define SKO_PAC_PERM_NSW_LOCK_SHIFT		1
+#define SKO_PAC_PERM_NSR_LOCK_SHIFT		0
+
+#define SKO_PERM_LOCK_ALL			0xf0
+
+#define SKO_PERM_KEY_SR_LOCK			(0x1<<SKO_PAC_KEY_SR_LOCK_SHIFT)
+#define SKO_PERM_KEY_NSR_LOCK			(0x1<<SKO_PAC_KEY_NSR_LOCK_SHIFT)
+
+#define SKO_PERM_KEY_SW_LOCK			(0x1<<SKO_PAC_KEY_SW_LOCK_SHIFT)
+#define SKO_PERM_KEY_NSW_LOCK			(0x1<<SKO_PAC_KEY_NSW_LOCK_SHIFT)
+
+#define SKO_PERM_PAC_SR_LOCK			(0x1<<SKO_PAC_PERM_SR_LOCK_SHIFT)
+#define SKO_PERM_PAC_NSR_LOCK			(0x1<<SKO_PAC_PERM_NSR_LOCK_SHIFT)
+
+#define SKO_PERM_PAC_SW_LOCK			(0x1<<SKO_PAC_PERM_SW_LOCK_SHIFT)
+#define SKO_PERM_PAC_NSW_LOCK			(0x1<<SKO_PAC_PERM_NSW_LOCK_SHIFT)
+
+
+/* Lock enable bit for PERM_PAC is 0; for PERM_KEY 1  */
+#define SKO_PERM_PAC_LOCK_SET(_R_, _V_)		(_R_ &= (~(_V_)) ) 	
+#define SKO_PERM_KEY_LOCK_SET(_R_, _V_)		(_R_ |= (_V_))
+
+#define SKO_SECT_MAX				2 
+#define SKO_NON_SECT				3 
+
+/* special case for 6878 only - belongs to otp.h */
+#define OTP_BOOT_SW_0_ROW              		26
+#define OTP_BOOT_SW_0_SHIFT                     0
+#define OTP_BOOT_SW_0_MASK                	0xffffffff
+#define SKO_ADDR2SECT(__A)\
+	( __A != SKO_0_DATA_ROW? (__A != SKO_1_DATA_ROW? (__A < OTP_BOOT_SW_0_ROW? __A : SKO_NON_SECT) : 1 ) : 0) 
+
+
+/* An SOTP row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure keys reading and fusing 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_SOTP_MAP_ROW_INITLR(__VV__)					\
+	static otp_hw_cmn_row_t __VV__[ ] = {					\
+	{SOTP_MAP_FLD_ROE, SKO_0_DATA_ROW, SKO_ROW_MASK, SKO_ROW_SHIFT, 8, .conf = {.arg = SKO_0_CTL_ROW, .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC} },		\
+	{SOTP_MAP_KEY_DEV_SPECIFIC, SKO_1_DATA_ROW, SKO_ROW_MASK, SKO_ROW_SHIFT, 8, .conf = {.arg = SKO_1_CTL_ROW, .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC}},	\
+	{OTP_MAP_INVALID, SKO_0_CTL_ROW, SKO_ROW_MASK, SKO_ROW_SHIFT, 1, .conf = {.arg = SKO_0_CTL_CONF, .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC} },	\
+	{OTP_MAP_INVALID, SKO_0_DESC_ROW, SKO_ROW_MASK, SKO_ROW_SHIFT, 1, .conf = {.arg = SKO_0_DESC_CONF, .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC} },	\
+	{OTP_MAP_INVALID, SKO_1_CTL_ROW, SKO_ROW_MASK, SKO_ROW_SHIFT, 1,  .conf = {.arg = SKO_1_CTL_CONF, .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC} },  	\
+	{OTP_MAP_INVALID, SKO_1_DESC_ROW, SKO_ROW_MASK, SKO_ROW_SHIFT, 1, .conf = {.arg = SKO_1_DESC_CONF, .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC} },	\
+	{SOTP_MAP_FLD_HMID, OTP_BOOT_SW_0_ROW,	OTP_BOOT_SW_0_MASK, OTP_BOOT_SW_0_SHIFT, 8}	};
+
+
+
+#endif
+
diff --git a/arch/arm/mach-bcmbca/include/skp.h b/arch/arm/mach-bcmbca/include/skp.h
new file mode 100755
index 0000000000..65dbfd1093
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/skp.h
@@ -0,0 +1,303 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+#ifndef _SKP_H
+#define _SKP_H
+
+/* KSR defs */
+#define KSR_BASE 0xff805000
+
+#define KSR_STATUS_KEY_LOADED_SHIFT	24
+#define KSR_STATUS_KEY_LOADED_MASK	0x1
+#define KSR_STATUS_READY_SHIFT		21
+#define KSR_STATUS_READY_MASK		0x1
+#define KSR_STATUS_DESC_VALID_SHIFT	20
+#define KSR_STATUS_DESC_VALID_MASK	0x1
+#define KSR_RD_DESC_DGOOD_MASK          0x1
+#define KSR_RD_DESC_DGOOD_SHIFT         29
+#define KSR_RD_DGOOD(_V_)      ((_V_>>KSR_RD_DESC_DGOOD_SHIFT)&KSR_RD_DESC_DGOOD_MASK) 
+
+#define	KSR_PORTAL_VALID(_V_)	(	((_V_>>KSR_STATUS_KEY_LOADED_SHIFT)&KSR_STATUS_KEY_LOADED_MASK) &\
+					((_V_>>KSR_STATUS_READY_SHIFT)&KSR_STATUS_READY_MASK)		&\
+ 					((_V_>>KSR_STATUS_DESC_VALID_SHIFT)&KSR_STATUS_DESC_VALID_MASK) )
+
+#define KSR_STATUS_ECC_DATA_SHIFT	23
+#define KSR_STATUS_ECC_DATA_MASK	0x1
+#define KSR_STATUS_ECC_DESC_SHIFT	22
+#define KSR_STATUS_ECC_DESC_MASK	0x1
+#define KSR_PORTAL_ECC_DATA_ERR(_V_)	((_V_>>KSR_STATUS_ECC_DATA_SHIFT)&KSR_STATUS_ECC_DATA_MASK)
+#define KSR_PORTAL_ECC_DESC_ERR(_V_)	((_V_>>KSR_STATUS_ECC_DESC_SHIFT)&KSR_STATUS_ECC_DESC_MASK)
+#define	KSR_PORTAL_KEY_LOADED(_V_) 	((_V_>>KSR_STATUS_KEY_LOADED_SHIFT)&KSR_STATUS_KEY_LOADED_MASK)
+
+
+#define KSR_PORTAL_OTP_PGM_DESC_VALID_SHIFT	31
+#define KSR_PORTAL_OTP_PGM_DESC_VALID_MASK	0x1
+
+#define KSR_PORTAL_PGM_DESC_PERM_SHIFT		0
+#define KSR_PORTAL_PGM_DESC_PERM_MASK		0xf
+
+#define KSR_PORTAL_PGM_DESC_LOCK_MASK		0x1	
+
+#define KSR_PORTAL_PGM_DESC_BLK_SW_LOCK_SHIFT	7
+#define KSR_PORTAL_PGM_DESC_BLK_SR_LOCK_SHIFT	6
+#define KSR_PORTAL_PGM_DESC_BLK_NSW_LOCK_SHIFT	5
+#define KSR_PORTAL_PGM_DESC_BLK_NSR_LOCK_SHIFT	4
+#define KSR_PORTAL_PGM_DESC_PERM_SW_LOCK_SHIFT	3	
+#define KSR_PORTAL_PGM_DESC_PERM_SR_LOCK_SHIFT	2
+#define KSR_PORTAL_PGM_DESC_PERM_NSW_LOCK_SHIFT	1
+#define KSR_PORTAL_PGM_DESC_PERM_NSR_LOCK_SHIFT	0
+
+#define KSR_PERM_BLK_SR_LOCK	(0x1<<KSR_PORTAL_PGM_DESC_BLK_SR_LOCK_SHIFT)
+#define KSR_PERM_BLK_NSR_LOCK	(0x1<<KSR_PORTAL_PGM_DESC_BLK_NSR_LOCK_SHIFT)
+
+#define KSR_PERM_BLK_SW_LOCK	(0x1<<KSR_PORTAL_PGM_DESC_BLK_SW_LOCK_SHIFT)
+#define KSR_PERM_BLK_NSW_LOCK	(0x1<<KSR_PORTAL_PGM_DESC_BLK_NSW_LOCK_SHIFT)
+
+#define KSR_PERM_PAC_SR_LOCK	(0x1<<KSR_PORTAL_PGM_DESC_PERM_SR_LOCK_SHIFT)
+#define KSR_PERM_PAC_NSR_LOCK	(0x1<<KSR_PORTAL_PGM_DESC_PERM_NSR_LOCK_SHIFT)
+
+#define KSR_PERM_PAC_SW_LOCK	(0x1<<KSR_PORTAL_PGM_DESC_PERM_SW_LOCK_SHIFT)
+#define KSR_PERM_PAC_NSW_LOCK	(0x1<<KSR_PORTAL_PGM_DESC_PERM_NSW_LOCK_SHIFT)
+
+#define KSR_PERM_LOCK_ALL	0xff
+/* Allways keep access to PERM fields locked for NSEC */
+#define KSR_PERM_UNLOCK_ALL	(KSR_PERM_PAC_NSR_LOCK | KSR_PERM_PAC_NSW_LOCK)
+#define KSR_PERM_LOCK_NS					\
+				(KSR_PERM_BLK_NSR_LOCK 	| 	\
+				KSR_PERM_BLK_NSW_LOCK 	| 	\
+				KSR_PERM_PAC_NSR_LOCK 	| 	\
+				KSR_PERM_PAC_NSW_LOCK)
+/* Unlocking NONSEC BLK access should unlock SEC BLK access as well */
+#define KSR_PERM_UNLOCK_NS	(KSR_PERM_UNLOCK_ALL)
+/* Locking SEC BLK access should also lock NONSEC BLK acces as well */
+#define KSR_PERM_LOCK_S		(KSR_PERM_LOCK_ALL)
+/* Unlocking SEC BLK access should lock NONSEC BLK access as well */
+#define KSR_PERM_UNLOCK_S	(KSR_PERM_LOCK_NS)
+
+
+#define KSR_PORTAL_PGM_DESC_NRW_PERM					\
+		(0x1<<KSR_PORTAL_OTP_PGM_DESC_VALID_SHIFT)
+
+#define KSR_PORTAL_PGM_DESC_SRW_PERM					\
+		((0x1<<KSR_PORTAL_OTP_PGM_DESC_VALID_SHIFT)    |	\
+		(0x1<<KSR_PORTAL_PGM_DESC_BLK_NSW_LOCK_SHIFT)  |	\
+		(0x1<<KSR_PORTAL_PGM_DESC_BLK_NSR_LOCK_SHIFT)  |	\
+		(0x1<<KSR_PORTAL_PGM_DESC_PERM_NSW_LOCK_SHIFT) |	\
+		(0x1<<KSR_PORTAL_PGM_DESC_PERM_NSR_LOCK_SHIFT))
+
+#define KSR_PORTAL_OTP_CMD_MASK			0xf
+#define KSR_PORTAL_OTP_CMD_SHIFT		0x0
+
+#define KSR_PORTAL_OTP_CMD_PGM_DESC_WORD	0x8
+#define KSR_PORTAL_OTP_CMD_PGM_DESC_ECC		0x9
+#define KSR_PORTAL_OTP_CMD_PGM_KEY		0x2
+
+#define KSR_OTP_CMD_PGM_DESC_WORD		((KSR_PORTAL_OTP_CMD_MASK&KSR_PORTAL_OTP_CMD_PGM_DESC_WORD)<<KSR_PORTAL_OTP_CMD_SHIFT)
+#define KSR_OTP_CMD_PGM_DESC_ECC		((KSR_PORTAL_OTP_CMD_MASK&KSR_PORTAL_OTP_CMD_PGM_DESC_ECC)<<KSR_PORTAL_OTP_CMD_SHIFT)
+#define KSR_OTP_CMD_PGM_KEY			((KSR_PORTAL_OTP_CMD_MASK&KSR_PORTAL_OTP_CMD_PGM_KEY)<<KSR_PORTAL_OTP_CMD_SHIFT)
+
+
+#define KSR_OTP_STATUS_CMD_ACTIVE_SHIFT	31
+#define KSR_OTP_STATUS_CMD_ACTIVE_MASK	0x1
+#define KSR_OTP_STATUS_ACTIVE(_V_)		\
+		((_V_>>KSR_OTP_STATUS_CMD_ACTIVE_SHIFT)&KSR_OTP_STATUS_CMD_ACTIVE_MASK)
+#define KSR_OTP_STATUS_OPCODE_SHIFT	16
+#define KSR_OTP_STATUS_OPCODE_MASK	0xf
+#define KSR_OTP_STATUS_CMD_ERR_SHIFT	0x0
+#define KSR_OTP_STATUS_CMD_ERR_MASK	0xff
+
+#define KSR_OTP_STATUS_CMD_ERROR(_V_)		\
+		((_V_>>KSR_OTP_STATUS_CMD_ERR_SHIFT)&KSR_OTP_STATUS_CMD_ERR_MASK)
+
+
+#define KSR_PAC_OFFSET                 	 	0x00       
+#define KSR_OTP_CMD_OFFSET                  	0x04       
+#define KSR_OTP_STATUS_OFFSET               	0x08       
+#define KSR_RD_DESC_OFFSET                  	0x0c       
+#define KSR_PGM_DESC_OFFSET                 	0x10       
+#define KSR_PORTAL_STATUS_OFFSET            	0x14       
+#define KSR_DATA_OFFSET		    		0x20
+
+#define KSR_SIZE  0x80 
+#define KSR_OFFSET 0x0 
+#define KSR_START_ROW_ADDR			0
+#define KSR_MAX_ROW_ADDR			(KSR_START_ROW_ADDR+6)
+
+
+/* FSR defs */
+#define FSR_BASE 0xff805300 
+
+#define FSR_PORTAL_OTP_CMD_READ_DATA		0x2		
+#define FSR_PORTAL_OTP_CMD_READ_DESC		0x3
+#define FSR_PORTAL_OTP_CMD_WRITE_DATA		0x4
+#define FSR_PORTAL_OTP_CMD_WRITE_DATA_ECC	0x5
+#define FSR_PORTAL_OTP_CMD_WRITE_DESC		0x8
+#define FSR_PORTAL_OTP_CMD_WRITE_DESC_ECC	0x9
+#define FSR_PORTAL_OTP_CMD_RELOAD_DATA		0xc
+#define FSR_PORTAL_OTP_CMD_RELOAD_DESC		0xd	
+
+#define FSR_PORTAL_OTP_CMD_WORD_SEL_MASK	0xfff
+#define FSR_PORTAL_OTP_CMD_WORD_SEL_SHIFT	0x4
+
+#define FSR_PORTAL_OTP_CMD_MASK			0xf
+#define FSR_PORTAL_OTP_CMD_SHIFT		0x0
+
+
+#define FSR_OTP_CMD_READ_DATA		((FSR_PORTAL_OTP_CMD_MASK&FSR_PORTAL_OTP_CMD_READ_DATA)<<FSR_PORTAL_OTP_CMD_SHIFT)
+#define FSR_OTP_CMD_READ_DESC		((FSR_PORTAL_OTP_CMD_MASK&FSR_PORTAL_OTP_CMD_READ_DESC)<<FSR_PORTAL_OTP_CMD_SHIFT)
+#define FSR_OTP_CMD_PGM_DATA		((FSR_PORTAL_OTP_CMD_MASK&FSR_PORTAL_OTP_CMD_WRITE_DATA)<<FSR_PORTAL_OTP_CMD_SHIFT)
+#define FSR_OTP_CMD_PGM_DATA_ECC	((FSR_PORTAL_OTP_CMD_MASK&FSR_PORTAL_OTP_CMD_WRITE_DATA_ECC)<<FSR_PORTAL_OTP_CMD_SHIFT)
+#define FSR_OTP_CMD_PGM_DESC		((FSR_PORTAL_OTP_CMD_MASK&FSR_PORTAL_OTP_CMD_WRITE_DESC)<<FSR_PORTAL_OTP_CMD_SHIFT)
+#define FSR_OTP_CMD_PGM_DESC_ECC	((FSR_PORTAL_OTP_CMD_MASK&FSR_PORTAL_OTP_CMD_WRITE_DESC_ECC)<<FSR_PORTAL_OTP_CMD_SHIFT)
+#define FSR_OTP_CMD_RELOAD_DATA		((FSR_PORTAL_OTP_CMD_MASK&FSR_PORTAL_OTP_CMD_RELOAD_DATA)<<FSR_PORTAL_OTP_CMD_SHIFT)
+#define FSR_OTP_CMD_RELOAD_DESC		((FSR_PORTAL_OTP_CMD_MASK&FSR_PORTAL_OTP_CMD_RELOAD_DESC)<<FSR_PORTAL_OTP_CMD_SHIFT)
+
+#define FSR_PORTAL_STATUS_ECC_PGM_DIS_SHIFT	23
+#define FSR_PORTAL_STATUS_ECC_PGM_DIS_MASK	0x1
+#define FSR_PORTAL_STATUS_RLOCK_SHIFT	22
+#define FSR_PORTAL_STATUS_RLOCK_MASK	0x1
+#define FSR_PORTAL_STATUS_READY_SHIFT		21
+#define FSR_PORTAL_STATUS_READY_MASK		0x1
+#define FSR_PORTAL_STATUS_DESC_VALID_SHIFT	20
+#define FSR_PORTAL_STATUS_DESC_VALID_MASK	0x1
+
+#define	FSR_PORTAL_RLOCK(_V_)	(	((_V_>>	FSR_PORTAL_STATUS_RLOCK_SHIFT)&\
+						FSR_PORTAL_STATUS_RLOCK_MASK)	 	)
+
+#define	FSR_PORTAL_ECC_DIS(_V_)	(	((_V_>>	FSR_PORTAL_STATUS_ECC_PGM_DIS_SHIFT)&\
+						FSR_PORTAL_STATUS_ECC_PGM_DIS_MASK)	)
+
+#define	FSR_PORTAL_VALID(_V_)	(	((_V_>>	FSR_PORTAL_STATUS_READY_SHIFT)&\
+						FSR_PORTAL_STATUS_READY_MASK)		&\
+ 					((_V_>>	FSR_PORTAL_STATUS_DESC_VALID_SHIFT)&\
+						FSR_PORTAL_STATUS_DESC_VALID_MASK)	)
+
+#define FSR_RD_DESC_VALID_SHIFT         31
+#define FSR_RD_DESC_VALID_MASK          0x1
+#define FSR_RD_DESC_ECC_PGM_DIS_SHIFT	29
+#define FSR_RD_DESC_ECC_PGM_DIS_MASK	0x1
+#define FSR_RD_DESC_RLOCK_SHIFT		28
+#define FSR_RD_DESC_RLOCK_MASK		0x1
+#define FSR_RD_DESC_SIZE_SHIFT		12
+#define FSR_RD_DESC_SIZE_MASK		0xfff
+
+#define FSR_RD_DDATA_SIZE(_V_)	((_V_>>FSR_RD_DESC_SIZE_SHIFT)&FSR_RD_DESC_SIZE_MASK)
+#define FSR_RD_DGOOD(_V_)      	((_V_>>FSR_RD_DESC_VALID_SHIFT)&FSR_RD_DESC_VALID_MASK) 
+
+#define FSR_OTP_STATUS_CMD_ACTIVE_SHIFT	31
+#define FSR_OTP_STATUS_CMD_ACTIVE_MASK	0x1
+#define FSR_OTP_STATUS_OPCODE_SHIFT	16
+#define FSR_OTP_STATUS_OPCODE_MASK	0xf
+#define FSR_OTP_STATUS_CMD_ERR_SHIFT	0x0
+#define FSR_OTP_STATUS_CMD_ERR_MASK	0xff
+
+#define FSR_OTP_STATUS_ACTIVE(_V_)		\
+		((_V_>>FSR_OTP_STATUS_CMD_ACTIVE_SHIFT)&FSR_OTP_STATUS_CMD_ACTIVE_MASK)
+#define FSR_OTP_STATUS_CMD_ERROR(_V_)		\
+		((_V_>>FSR_OTP_STATUS_CMD_ERR_SHIFT)&FSR_OTP_STATUS_CMD_ERR_MASK)
+
+#define FSR_PORTAL_RD_ECC_MASK			0x3ff
+
+#define FSR_PORTAL_PGM_BLK_SW_LOCK_SHIFT	7
+#define FSR_PORTAL_PGM_BLK_SR_LOCK_SHIFT	6
+#define FSR_PORTAL_PGM_BLK_NSW_LOCK_SHIFT	5
+#define FSR_PORTAL_PGM_BLK_NSR_LOCK_SHIFT	4
+#define FSR_PORTAL_PGM_PERM_SW_LOCK_SHIFT	3	
+#define FSR_PORTAL_PGM_PERM_SR_LOCK_SHIFT	2
+#define FSR_PORTAL_PGM_PERM_NSW_LOCK_SHIFT	1
+#define FSR_PORTAL_PGM_PERM_NSR_LOCK_SHIFT	0
+
+#define FSR_PERM_BLK_SR_LOCK	(0x1<<FSR_PORTAL_PGM_BLK_SR_LOCK_SHIFT)
+#define FSR_PERM_BLK_NSR_LOCK	(0x1<<FSR_PORTAL_PGM_BLK_NSR_LOCK_SHIFT)
+
+#define FSR_PERM_BLK_SW_LOCK	(0x1<<FSR_PORTAL_PGM_BLK_SW_LOCK_SHIFT)
+#define FSR_PERM_BLK_NSW_LOCK	(0x1<<FSR_PORTAL_PGM_BLK_NSW_LOCK_SHIFT)
+
+#define FSR_PERM_PAC_SR_LOCK	(0x1<<FSR_PORTAL_PGM_PERM_SR_LOCK_SHIFT)
+#define FSR_PERM_PAC_NSR_LOCK	(0x1<<FSR_PORTAL_PGM_PERM_NSR_LOCK_SHIFT)
+
+#define FSR_PERM_PAC_SW_LOCK	(0x1<<FSR_PORTAL_PGM_PERM_SW_LOCK_SHIFT)
+#define FSR_PERM_PAC_NSW_LOCK	(0x1<<FSR_PORTAL_PGM_PERM_NSW_LOCK_SHIFT)
+
+#define FSR_PERM_LOCK_ALL	0xff
+/* Allways keep access to PERM fields locked for NSEC */
+#define FSR_PERM_UNLOCK_ALL	(FSR_PERM_PAC_NSR_LOCK | FSR_PERM_PAC_NSW_LOCK)
+#define FSR_PERM_LOCK_NS					\
+				(FSR_PERM_BLK_NSR_LOCK 	| 	\
+				FSR_PERM_BLK_NSW_LOCK 	| 	\
+				FSR_PERM_PAC_NSR_LOCK 	| 	\
+				FSR_PERM_PAC_NSW_LOCK)
+/* Unlocking NONSEC BLK access should UNLOCK SEC BLK access as well */
+#define FSR_PERM_UNLOCK_NS	(FSR_PERM_UNLOCK_ALL)
+/* Locking SEC BLK access should also LOCK NONSEC BLK acces as well */
+#define FSR_PERM_LOCK_S		(FSR_PERM_LOCK_ALL)
+/* Unlocking SEC BLK access should LOCK NONSEC BLK access as well */
+#define FSR_PERM_UNLOCK_S	(FSR_PERM_LOCK_NS)
+
+
+#define FSR_OTP_CMD_OFFSET                  	0x00       
+#define FSR_OTP_STATUS_OFFSET               	0x04       
+#define FSR_DATA_OFFSET		    		0x08
+#define FSR_RD_ECC_OFFSET                  	0x0c       
+#define FSR_PORTAL_STATUS_OFFSET            	0x10       
+#define FSR_PAC_OFFSET                 	 	0x18       
+
+#define FSR_SIZE  0x20 
+#define FSR_OFFSET 0x300 
+#define FSR_START_ROW_ADDR			6
+#define FSR_MAX_ROW_ADDR			(FSR_START_ROW_ADDR+8)
+	
+/* An SOTP row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure keys reading and fusing 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+#define	DEFINE_SOTP_MAP_ROW_INITLR(__VV__)														\
+static otp_hw_cmn_row_t __VV__[ ] = {															\
+		{.feat = SOTP_MAP_FLD_ROE,          .addr = (KSR_START_ROW_ADDR+0), .range = 8, .conf = {.perm = KSR_PORTAL_PGM_DESC_SRW_PERM, .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC}},	\
+		{.feat = SOTP_MAP_FLD_HMID,         .addr = (KSR_START_ROW_ADDR+1), .range = 8, .conf = {.perm = KSR_PORTAL_PGM_DESC_SRW_PERM, .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC}},	\
+		{.feat = SOTP_MAP_KEY_DEV_SPECIFIC, .addr = (KSR_START_ROW_ADDR+2), .range = 8, .conf = {.perm = (KSR_PORTAL_PGM_DESC_NRW_PERM), .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC}},\
+		{.feat = SOTP_MAP_SER_NUM,          .addr = (KSR_START_ROW_ADDR+3), .range = 8, .conf = {.perm = (KSR_PORTAL_PGM_DESC_NRW_PERM), .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC}},\
+		{.feat = SOTP_MAP_KEY_SECT_1,       .addr = (KSR_START_ROW_ADDR+4), .range = 8, .conf = {.perm = (KSR_PORTAL_PGM_DESC_NRW_PERM), .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC}},\
+		{.feat = SOTP_MAP_KEY_SECT_2,       .addr = (KSR_START_ROW_ADDR+5), .range = 8, .conf = {.perm = (KSR_PORTAL_PGM_DESC_NRW_PERM), .op_type = OTP_HW_CMN_CTL_OTPCMD_ECC}},\
+		{.feat = SOTP_MAP_ANTI_ROLLBACK,    .addr = (FSR_START_ROW_ADDR+0), .range = 4, .conf = {.op_type = OTP_HW_CMN_CTL_CONF}},	\
+		{.feat = SOTP_MAP_UNUSED_1,         .addr = (FSR_START_ROW_ADDR+1), .range = 4, .conf = {.op_type = OTP_HW_CMN_CTL_CONF}},	\
+		{.feat = SOTP_MAP_UNUSED_2,         .addr = (FSR_START_ROW_ADDR+2), .range = 8, .conf = {.op_type = OTP_HW_CMN_CTL_CONF}},	\
+		{.feat = SOTP_MAP_UNUSED_3,         .addr = (FSR_START_ROW_ADDR+3), .range = 8, .conf = {.op_type = OTP_HW_CMN_CTL_CONF}},	\
+		{.feat = SOTP_MAP_UNUSED_4,         .addr = (FSR_START_ROW_ADDR+4), .range = 2, .conf = {.op_type = OTP_HW_CMN_CTL_CONF}},	\
+		{.feat = SOTP_MAP_UNUSED_5,         .addr = (FSR_START_ROW_ADDR+5), .range = 4, .conf = {.op_type = OTP_HW_CMN_CTL_CONF}},	\
+		{.feat = SOTP_MAP_UNUSED_6,         .addr = (FSR_START_ROW_ADDR+6), .range = 4, .conf = {.op_type = OTP_HW_CMN_CTL_CONF}},	\
+		{.feat = SOTP_MAP_UNUSED_7,         .addr = (FSR_START_ROW_ADDR+7), .range = 2, .conf = {.op_type = OTP_HW_CMN_CTL_CONF}},	\
+	};
+	
+/* Not implemented yet*/
+typedef struct FsrPortal {
+#define FSR_FP_OTP_CMD_READ_DATA		0x2
+#define FSR_FP_OTP_CMD_READ_OPCODE_MASK		0xf
+#define FSR_FP_OTP_CMD_READ_OPCODE_SHIFT	0
+#define FSR_FP_OTP_CMD_WORD_SEL_MASK		0xfff
+#define FSR_FP_OTP_CMD_WORD_SEL_SHIFT		4
+	u32 fp_otp_cmd;                 	/* 0x0       */
+#define FSR_FP_OTP_STATUS_ACTIVE_MASK		0x1	
+#define FSR_FP_OTP_STATUS_ACTIVE_SHIFT		31	
+#define FSR_FP_OTP_STATUS_ERR_MASK		0xff
+#define FSR_FP_OTP_STATUS_ERR_SHIFT		0	
+	u32 fp_otp_status;              	/* 0x04       */
+	u32 fp_data;                 	/* 0x08      */
+	u32 fp_rd_ecc;                	/* 0x0c       */
+#define FSR_FP_PORTAL_STATUS_READY_MASK		0x1
+#define FSR_FP_PORTAL_STATUS_READY_SHIFT	21
+#define FSR_FP_PORTAL_STATUS_DESC_VALID_MASK	0x1
+#define FSR_FP_PORTAL_STATUS_DESC_VALID_SHIFT	20
+	u32 fp_portal_status;           /* 0x10       */
+	u32 fp_rsvd[3];
+} fsr_portal_t;
+
+#define FSR_PORTAL_0 ((volatile fsr_portal_t * const) FSR_BASE)
+
+
+
+
+#endif
+
diff --git a/arch/arm/mach-bcmbca/include/sotp.h b/arch/arm/mach-bcmbca/include/sotp.h
new file mode 100644
index 0000000000..b7bb1d6f19
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/sotp.h
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+#ifndef _SOTP_H
+#define _SOTP_H
+
+#define SOTP_BASE			0xff800c00
+#define SOTP_OTP_REGION_RD_LOCK		0x3c
+
+
+#define  SOTP_OTP_PROG_CTRL_OFFSET             0x00   
+#define  SOTP_OTP_WDATA_0_OFFSET               0x04 
+#define  SOTP_OTP_WDATA_1_OFFSET               0x08 
+#define  SOTP_OTP_ADDR_OFFSET                  0x0C 
+#define  SOTP_OTP_CTRL_0_OFFSET                0x10 
+#define  DUMMY1_OFFSET                         0x14   
+#define  SOTP_OTP_STATUS_0_OFFSET              0x18 
+#define  SOTP_OTP_STATUS_1_OFFSET              0x1C 
+#define  SOTP_OTP_RDATA_0_OFFSET               0x20 
+#define  SOTP_OTP_RDATA_1_OFFSET               0x24 
+#define  SOTP_CHIP_STATES_OFFSET               0x28 
+#define  DUMMY2_OFFSET                         0x2C   
+#define  SOTP_OTP_ECCCNT_OFFSET                0x30 
+#define  SOTP_OTP_BAD_ADDR_OFFSET              0x34 
+#define  SOTP_OTP_WR_LOCK_OFFSET               0x38 
+#define  SOTP_OTP_RD_LOCK_OFFSET               0x3C 
+#define  SOTP_ROM_BLOCK_START_OFFSET           0x40 
+#define  SOTP_ROM_BLOCK_END_OFFSET             0x44 
+#define  SOTP_SAMU_CNTRL_OFFSET                0x48 
+#define  SOTP_CHIP_CNTRL_OFFSET                0x4C 
+#define  SOTP_SR_STATE_0_OFFSET                0x50 
+#define  SOTP_SR_STATE_1_OFFSET                0x54 
+#define  SOTP_SR_STATE_2_OFFSET                0x58 
+#define  SOTP_SR_STATE_3_OFFSET                0x5C 
+#define  SOTP_SR_STATE_4_OFFSET                0x60 
+#define  SOTP_SR_STATE_5_OFFSET                0x64 
+#define  SOTP_SR_STATE_6_OFFSET                0x68 
+#define  SOTP_SR_STATE_7_OFFSET                0x6C 
+#define  SOTP_PERM_OFFSET                      0x70 
+#define  SOTP_SOTP_OUT_0_OFFSET                0x74 
+#define  SOTP_SOTP_OUT_1_OFFSET                0x78 
+#define  SOTP_SOTP_OUT_2_OFFSET                0x7C 
+#define  SOTP_SOTP_INOUT_OFFSET                0x80
+/*
+#####################################################################
+# SOTP Registers
+#####################################################################
+*/
+
+#define SOTP_OTP_PROG_CTRL			0x00
+
+#define SOTP_OTP_PROG_CTRL_OTP_ECC_WREN_SHIFT   8
+#define SOTP_OTP_PROG_CTRL_OTP_ECC_WREN 	(1 << SOTP_OTP_PROG_CTRL_OTP_ECC_WREN_SHIFT)
+
+#define SOTP_OTP_PROG_CTRL_OTP_DISABLE_ECC_SHIFT 9
+#define SOTP_OTP_PROG_CTRL_OTP_DISABLE_ECC 	(1 << SOTP_OTP_PROG_CTRL_OTP_DISABLE_ECC_SHIFT)
+
+#define SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN_SHIFT 15
+#define SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN	(1 << SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN_SHIFT)
+
+#define SOTP_OTP_PROG_CTRL_REGS_ECC_EN_SHIFT     17
+#define SOTP_OTP_PROG_CTRL_REGS_ECC_EN_MASK      (0xf << SOTP_OTP_PROG_CTRL_REGS_ECC_EN_SHIFT) /* bits 20:17 */
+#define SOTP_OTP_PROG_CTRL_REGS_ECC_EN           (0xa << SOTP_OTP_PROG_CTRL_REGS_ECC_EN_SHIFT)
+#define SOTP_OTP_PROG_CTRL_REGS_ECC_DIS          (0x5 << SOTP_OTP_PROG_CTRL_REGS_ECC_EN_SHIFT)
+
+/* --- */
+
+#define SOTP_OTP_WDATA_0			0x04
+
+/* --- */
+
+#define SOTP_OTP_WDATA_1			0x08
+#define SOTP_OTP_WDATA_1_FAIL_SHIFT		7
+#define SOTP_OTP_WDATA_1_FAIL_MASK		(0x3 << SOTP_OTP_WDATA_1_FAIL_SHIFT)
+
+/* --- */
+
+#define SOTP_OTP_ADDR				0x0c
+#define SOTP_OTP_ADDR_OTP_ADDR_SHIFT		6
+
+/* --- */
+
+#define SOTP_OTP_CTRL_0				0x10
+
+#define SOTP_OTP_CTRL_0_OTP_CMD_SHIFT		1
+#define SOTP_OTP_CTRL_0_OTP_CMD_MASK		(0x1f << SOTP_OTP_CTRL_0_OTP_CMD_SHIFT) /* bits [05:01] */
+#define SOTP_OTP_CTRL_0_OTP_CMD_OTP_READ	(0x0 << SOTP_OTP_CTRL_0_OTP_CMD_SHIFT) 
+#define SOTP_OTP_CTRL_0_OTP_CMD_OTP_PROG_ENABLE	(0x2 << SOTP_OTP_CTRL_0_OTP_CMD_SHIFT) 
+#define SOTP_OTP_CTRL_0_OTP_CMD_PROG		(0xa << SOTP_OTP_CTRL_0_OTP_CMD_SHIFT) 
+
+#define SOTP_OTP_CTRL_0_START_SHIFT		0
+#define SOTP_OTP_CTRL_0_START            	(0x1 << SOTP_OTP_CTRL_0_START_SHIFT)   
+
+/* --- */
+
+#define SOTP_OTP_STATUS_1			0x1c
+
+#define SOTP_OTP_STATUS_1_CMD_DONE_SHIFT	1
+#define SOTP_OTP_STATUS_1_CMD_DONE	        (0x1 << SOTP_OTP_STATUS_1_CMD_DONE_SHIFT) 
+
+#define SOTP_OTP_STATUS_1_ECC_COR_SHIFT		16
+#define SOTP_OTP_STATUS_1_ECC_COR	        (0x1 << SOTP_OTP_STATUS_1_ECC_COR_SHIFT) 
+
+#define SOTP_OTP_STATUS_1_ECC_DET_SHIFT		17
+#define SOTP_OTP_STATUS_1_ECC_DET	        (0x1 << SOTP_OTP_STATUS_1_ECC_DET_SHIFT) 
+
+/* --- */
+
+#define SOTP_OTP_RDATA_0			0x20
+
+/* --- */
+
+#define SOTP_OTP_RDATA_1			0x24
+#define SOTP_OTP_RDATA_1_FAIL_SHIFT		7
+#define SOTP_OTP_RDATA_1_FAIL_MASK		(0x3 << SOTP_OTP_RDATA_1_FAIL_SHIFT)
+
+/* --- */
+
+#define SOTP_OTP_REGION_RD_LOCK			0x3c
+
+/* --- */
+
+#define SOTP_CHIP_CTRL                          0x4c
+
+#define SOTP_CHIP_CNTRL_SW_OVERRIDE_CHIP_STATES_SHIFT   4
+#define SOTP_CHIP_CNTRL_SW_OVERRIDE_CHIP_STATES (0x1 << SOTP_CHIP_CNTRL_SW_OVERRIDE_CHIP_STATES_SHIFT)
+
+#define SOTP_CHIP_CTRL_SW_MANU_PROG_SHIFT       5
+#define SOTP_CHIP_CTRL_SW_MANU_PROG             (0x1 << SOTP_CHIP_CTRL_SW_MANU_PROG_SHIFT)
+
+#define SOTP_CHIP_CTRL_SW_NON_AB_DEVICE_SHIFT   7
+#define SOTP_CHIP_CTRL_SW_NON_AB_DEVICE         (0x1 << SOTP_CHIP_CTRL_SW_NON_AB_DEVICE_SHIFT)
+
+/* --- */
+
+#define SOTP_SOTP_OUT_0                         0x74
+#define SOTP_SOTP_OUT_0_SOTP_OTP_READY_SHIFT    26
+#define SOTP_SOTP_OUT_0_SOTP_OTP_READY          (1 << SOTP_SOTP_OUT_0_SOTP_OTP_READY_SHIFT)
+
+#define SOTP ((volatile sotp_t * const) SOTP_BASE)
+
+#define SOTP_PERM		0x70
+#define SOTP_PERM_SHIFT 	0x0
+#define SOTP_PERM_BLK_SHIFT	0x4
+
+#define SOTP_PERM_SEC_W 	0x8
+#define SOTP_PERM_SEC_R 	0x4
+#define SOTP_PERM_NSEC_W 	0x2
+#define SOTP_PERM_NSEC_R 	0x1
+
+#define SOTP_PERM_BLK_SEC_W 	0x8
+#define SOTP_PERM_BLK_SEC_R 	0x4
+#define SOTP_PERM_BLK_NSEC_W 	0x2
+#define SOTP_PERM_BLK_NSEC_R 	0x1
+
+#define SOTP_PERM_NSEC_ENABLE   (((SOTP_PERM_BLK_NSEC_R|SOTP_PERM_BLK_NSEC_W)<<SOTP_PERM_BLK_SHIFT)| (SOTP_PERM_SEC_W|SOTP_PERM_SEC_R)<<SOTP_PERM_SHIFT)
+#define SOTP_PERM_SEC_ENABLE    (((SOTP_PERM_BLK_SEC_R|SOTP_PERM_BLK_SEC_W)<<SOTP_PERM_BLK_SHIFT)|  (SOTP_PERM_SEC_W|SOTP_PERM_SEC_R)<<SOTP_PERM_SHIFT)
+#define SOTP_PERM_DISABLE_ALL	0x0
+/* When enabling all access, keep the NONSEC access locked for permissions register */
+#define SOTP_PERM_ENABLE_ALL	(((SOTP_PERM_BLK_SEC_W|SOTP_PERM_BLK_SEC_R|SOTP_PERM_BLK_NSEC_W|SOTP_PERM_BLK_NSEC_R)<<SOTP_PERM_BLK_SHIFT)| ((SOTP_PERM_SEC_W|SOTP_PERM_SEC_R)<<SOTP_PERM_SHIFT))
+
+#define SOTP_PERM_ALLOW_SECURE_ACCESS_ONLY	0xCC
+#define SOTP_PERM_ALLOW_NONSEC_ACCESS_ONLY	0x33
+/* When enabling NONSEC, enable SEC as well */
+#define SOTP_PERM_ALLOW_NONSEC_BLK_ACCESS	(SOTP_PERM_ENABLE_ALL)
+/* When disabling SEC, disable NONSEC as well */
+#define SOTP_PERM_DISABLE_SECURE_ACCESS		(SOTP_PERM_DISABLE_ALL)
+
+#define ROWS_PER_RGN 4
+#define SOTP_RGN_CNT 28 
+#define SOTP_ROW_CNT  (ROWS_PER_RGN*SOTP_ROW_CNT)
+
+
+typedef enum _sotp_row_status_ {
+   SOTP_S_ROW_SUCCESS,	   // The function has completed successfully
+   SOTP_S_ROW_ECC_COR, 	   // The function corrected 1 bad bit within the row (row is still usable)
+   SOTP_E_ROW_ECC_DET,	   // The function detected 2 or more uncorrectable bits within the row (row is bad)
+   SOTP_E_ROW_FAIL_SET,	   // The function detected that 1 or both of the fail bits are set (row is bad)
+   SOTP_E_ROW_READ_LOCK,   // The function detected that the row is locked from reading
+   SOTP_E_ROW_FUSE_LOCK,   // The function detected that the row is locked from further fusing
+   SOTP_E_ROW_TIMEOUT,	   // The function experienced unexpected FSM timeout from the SOTP block 
+   SOTP_E_ROW_ERROR	   // The function experienced unexpected register return value from the SOTP block 
+} SotpRowStatus;
+
+
+typedef enum _sotp_keys_status{
+   SOTP_S_KEY_SUCCESS,	   // The function has completed successfully, and a credential exists
+   SOTP_S_KEY_EMPTY,	   // The function has completed successfully, but the section is empty
+   SOTP_E_KEY_BADPARAM,	   // The function received a bad input parameter 
+   SOTP_E_KEY_OVERRUN,	   // The function ran out of rows within the section before the entire key and crc was fused
+   SOTP_E_KEY_UNDERRUN,	   // The function ran out of valid section rows before reading the entire key and crc
+   SOTP_E_KEY_CRC_MIS,	   // The function detected a CRC mismatch during the key read (key is bad or empty)
+   SOTP_E_KEY_ERROR	   // The function experienced an unexpected return value  
+} SotpKeyStatus;
+
+
+/* SOTP base defines */
+#define    SOTP_MAX_CNTR     		1000
+#define    SOTP_NUM_ROWS		112     /* Maximum rows accessable in SOTP */
+#define    SOTP_BITS_PER_ROW		41	/* Bits in each SOTP row, only some rows allow direct programming of all 41 bits */
+
+#define    SOTP_BYTES_PER_ROW  		4       /* User Data bytes in one keyslot row */
+#define    SOTP_ROWS_IN_REGION          4
+
+/* LOCK sections */
+#define    SOTP_WRAPPER_LOCK_SECTION    1       /* Section # containing write lock bits */
+#define    SOTP_PROG_LOCK_SECTION       2       /* Section # containing read lock bits */
+#define    SOTP_REGIONS_IN_LOCK		1       /* Number of regions in combined lock sections */
+#define    SOTP_FIRST_FUSELOCK_ROW 	8	/* First row containing fuse-lock ctrl bits */	
+#define    SOTP_NUM_REG_IN_FUSELOCK_ROW	21      /* Num regions represented in each fuse-lock row */
+
+/* Keyslot sections */
+#define    SOTP_MIN_KEYSLOT		7	/* First keyslot section # */
+#define    SOTP_MAX_KEYSLOT		13	/* Last  keyslot section # */
+#define    SOTP_REGIONS_IN_KEYSLOT      3       /* Number of regions in each keyslot section */
+#define    SOTP_ROWS_IN_KEYSLOT 	12      /* Number of rows in each keyslot section */
+#define    SOTP_FIRST_KEYSLOT_ROW 	28      /* First row containing 32-bit credential data */
+#define    SOTP_FIRST_KEYSLOT_REGION    7       /* First region containing credential data */
+#define    SOTP_FIRST_KEYSLOT_SECTION   7       /* First keyslot section # */
+#define    SOTP_REGIONS_MASK_IN_KEYSLOT 7
+#define    SOTP_MAX_KEYLEN 		8       /* Maximum key length in 32-bit words */ 
+
+/* Device CFG section */
+#define    SOTP_DEVICE_CFG_SECTION      3       /* Section # containing SOTP device cfg */
+#define    SOTP_REGIONS_IN_DEVCFG	1       /* Number of regions in device cfg */
+
+
+/* General CFG sections */
+#define    SOTP_FIRST_CFG_SECTION       4       /* First general CFG section # */
+#define    SOTP_FIRST_ECC_CONFIG_ROW    16      /* First row containing ECC protected 32-bit config data */
+#define    SOTP_REGIONS_IN_CFG          1       /* Number of regions in the General CFG sections */
+
+
+
+/* An SOTP row initializer that maps actual row number with mask and shift to a feature name;
+ * this allows to use features vs. rows for common functionality, 
+ * such as secure keys reading and fusing 
+ * prevent ifdef dependencies when used outside of arch directories for common among SoCs logic
+ * */
+	
+#define	DEFINE_SOTP_MAP_ROW_INITLR(__VV__)					\
+	static otp_hw_cmn_row_t __VV__[ ] = {					\
+		{.addr = 16, .range = 4, .feat = SOTP_MAP_ANTI_ROLLBACK, .conf = {.addr_type = OTP_HW_CMN_ROW_ADDR_ROW, .op_type = OTP_HW_CMN_CTL_CONF} },	\
+		{.addr = 28, .range = 8, .feat = SOTP_MAP_KEY_DEV_SPECIFIC },	\
+		{.addr = 40, .range = 8, .feat = SOTP_MAP_FLD_ROE },		\
+		{.addr = 52, .range = 8, .feat = SOTP_MAP_FLD_HMID },		\
+		{.addr = 64, .range = 8, .feat = SOTP_MAP_SER_NUM },	\
+		{.addr = 76, .range = 8, .feat = SOTP_MAP_KEY_SECT_1},		\
+		{.addr = 88, .range = 8, .feat = SOTP_MAP_KEY_SECT_2},		\
+		{.addr = 100, .range = 8, .feat = SOTP_MAP_KEY_SECT_3},		\
+	};
+#endif
diff --git a/arch/arm/mach-bcmbca/include/spl_ddrinit.h b/arch/arm/mach-bcmbca/include/spl_ddrinit.h
new file mode 100644
index 0000000000..ac272a16bb
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/spl_ddrinit.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _SPL_DDRINIT_H
+#define _SPL_DDRINIT_H
+
+#ifdef CONFIG_BCMBCA_DPFE
+#include "ddrinit_dpfe.h"
+#endif
+
+/* Information about DDR memory configuration */
+#if defined(CONFIG_BCM6846) || defined(CONFIG_BCM6878)
+#define BP_DDR_SUPPORT_2L_PCB		1
+#endif
+
+#if defined(CONFIG_BCM63178) || defined(CONFIG_BCM4912)
+#define BP_DDR_SUPPORT_VTT		1
+/* 63178 board does not support this optoin */
+#define BP_DDR_SUPPORT_VTT_DIS_PASVTERM 0
+#endif
+
+#define BP_DDR_SPEED_MASK		0x1f
+#define BP_DDR_SPEED_SHIFT		0
+#define BP_DDR_SPEED_SAFE		0
+#define BP_DDR_SPEED_400_6_6_6		1	/* DDR3-800E  */
+#define BP_DDR_SPEED_533_7_7_7		2	/* DDR3-1066F */
+#define BP_DDR_SPEED_533_8_8_8		3	/* DDR3-1066G */
+#define BP_DDR_SPEED_667_9_9_9		4	/* DDR3-1333H */
+#define BP_DDR_SPEED_667_10_10_10	5	/* DDR3-1333J */
+#define BP_DDR_SPEED_800_10_10_10	6	/* DDR3-1600J */
+#define BP_DDR_SPEED_800_11_11_11	7	/* DDR3-1600K */
+#define BP_DDR_SPEED_1067_11_11_11	8	/* DDR3-2133K */
+#define BP_DDR_SPEED_1067_12_12_12	9	/* DDR3-2133L */
+#define BP_DDR_SPEED_1067_13_13_13	10	/* DDR3-2133M */
+#define BP_DDR_SPEED_1067_14_14_14	11	/* DDR3-2133N */ 
+#define BP_DDR_SPEED_933_10_10_10	12	/* DDR3-1866J */
+#define BP_DDR_SPEED_933_11_11_11	13	/* DDR3-1866K */ 
+#define BP_DDR_SPEED_933_12_12_12	14	/* DDR3-1866L */
+#define BP_DDR_SPEED_933_13_13_13	15	/* DDR3-1866M */
+#define BP_DDR_SPEED_1067_15_15_15	16	/* DDR4-2133P */
+#define BP_DDR_SPEED_1067_16_16_16	17	/* DDR4-2133R */
+#define BP_DDR_SPEED_1200_17_17_17	18	/* DDR4-2400T */
+#define BP_DDR_SPEED_1200_18_18_18	19	/* DDR4-2400U */
+#define BP_DDR_SPEED_1333_19_19_19	20	/* DDR4-2666V */
+#define BP_DDR_SPEED_1600_22_22_22	21	/* DDR4-3200AA */
+#define BP_DDR_SPEED_1600_24_24_24	22	/* DDR4-3200AC */
+#define BP_DDR_SPEED_CUSTOM_1		27
+#define BP_DDR_SPEED_CUSTOM_2		28
+#define BP_DDR_SPEED_CUSTOM_3		29
+#define BP_DDR_SPEED_CUSTOM_4		30
+
+#define BP_DDR_SPEED_IS_1067(spd)	((spd) == BP_DDR_SPEED_1067_11_11_11 ||\
+					 (spd) == BP_DDR_SPEED_1067_12_12_12 ||\
+					 (spd) == BP_DDR_SPEED_1067_13_13_13 ||\
+					 (spd) == BP_DDR_SPEED_1067_14_14_14 ||\
+					 (spd) == BP_DDR_SPEED_1067_15_15_15 ||\
+					 (spd) == BP_DDR_SPEED_1067_16_16_16)
+
+#define BP_DDR_SPEED_IS_800(spd)	((spd) == BP_DDR_SPEED_800_10_10_10 ||\
+					 (spd) == BP_DDR_SPEED_800_11_11_11)
+
+#define BP_DDR_DEVICE_WIDTH_MASK	0xe0
+#define BP_DDR_DEVICE_WIDTH_SHIFT	5
+#define BP_DDR_DEVICE_WIDTH_8		(0 << BP_DDR_DEVICE_WIDTH_SHIFT)
+#define BP_DDR_DEVICE_WIDTH_16		(1 << BP_DDR_DEVICE_WIDTH_SHIFT)
+#define BP_DDR_DEVICE_WIDTH_32		(2 << BP_DDR_DEVICE_WIDTH_SHIFT)
+
+#define BP_DDR_TOTAL_SIZE_MASK		0xf00
+#define BP_DDR_TOTAL_SIZE_SHIFT		8
+#define BP_DDR_TOTAL_SIZE_64MB		(1 << BP_DDR_TOTAL_SIZE_SHIFT)
+#define BP_DDR_TOTAL_SIZE_128MB	(2 << BP_DDR_TOTAL_SIZE_SHIFT)
+#define BP_DDR_TOTAL_SIZE_256MB	(3 << BP_DDR_TOTAL_SIZE_SHIFT)
+#define BP_DDR_TOTAL_SIZE_512MB	(4 << BP_DDR_TOTAL_SIZE_SHIFT)
+#define BP_DDR_TOTAL_SIZE_1024MB	(5 << BP_DDR_TOTAL_SIZE_SHIFT)
+#define BP_DDR_TOTAL_SIZE_2048MB	(6 << BP_DDR_TOTAL_SIZE_SHIFT)
+#define BP_DDR_TOTAL_SIZE_4096MB	(7 << BP_DDR_TOTAL_SIZE_SHIFT)
+
+#define BP_DDR_SSC_CONFIG_MASK		0xf000
+#define BP_DDR_SSC_CONFIG_SHIFT		12
+#define BP_DDR_SSC_CONFIG_NONE		(0 << BP_DDR_SSC_CONFIG_SHIFT)
+#define BP_DDR_SSC_CONFIG_1		(1 << BP_DDR_SSC_CONFIG_SHIFT)
+#define BP_DDR_SSC_CONFIG_2		(2 << BP_DDR_SSC_CONFIG_SHIFT)
+#define BP_DDR_SSC_CONFIG_CUSTOM	(3 << BP_DDR_SSC_CONFIG_SHIFT)
+
+#define BP_DDR_TEMP_MASK		0x30000
+#define BP_DDR_TEMP_SHIFT		16
+#define BP_DDR_TEMP_NORMAL		(0 << BP_DDR_TEMP_SHIFT)	/* Self-Refresh for Normal Temperature */
+#define BP_DDR_TEMP_EXTENDED_SRT	(1 << BP_DDR_TEMP_SHIFT)	/* Self-Refresh for Extended Temperature */
+#define BP_DDR_TEMP_EXTENDED_ASR	(2 << BP_DDR_TEMP_SHIFT)	/* Auto Self-Refresh Enabled for Normal and Extended Temperature */
+
+#define BP_DDR_TOTAL_WIDTH_MASK		0xc0000
+#define BP_DDR_TOTAL_WIDTH_SHIFT	18
+#define BP_DDR_TOTAL_WIDTH_16BIT	(0 << BP_DDR_TOTAL_WIDTH_SHIFT)
+#define BP_DDR_TOTAL_WIDTH_32BIT	(1 << BP_DDR_TOTAL_WIDTH_SHIFT)
+#define BP_DDR_TOTAL_WIDTH_8BIT		(2 << BP_DDR_TOTAL_WIDTH_SHIFT)
+
+#if defined(CONFIG_BCM47189)
+/*only meaningful for 47189*/
+/*ddr enable half TREF */
+#define BP_DDR_HALF_TREF_MASK		0x100000
+#define BP_DDR_HALF_TREF_SHIFT		20
+#define BP_DDR_HALF_TREF		(1 << BP_DDR_HALF_TREF_SHIFT)
+
+/*ddr rRFC */
+#define BP_DDR_TRFC_MASK		0xe00000
+#define BP_DDR_TRFC_SHIFT		21
+#define BP_DDR_TRFC_90NS		(1 << BP_DDR_TRFC_SHIFT)
+#define BP_DDR_TRFC_110NS		(2 << BP_DDR_TRFC_SHIFT)
+#define BP_DDR_TRFC_160NS		(3 << BP_DDR_TRFC_SHIFT)
+#define BP_DDR_TRFC_260NS		(4 << BP_DDR_TRFC_SHIFT)
+#define BP_DDR_TRFC_350NS		(5 << BP_DDR_TRFC_SHIFT)
+#else
+#define BP_DDR_TYPE_MASK		0x300000
+#define BP_DDR_TYPE_SHIFT		20
+#define BP_DDR_TYPE_DDR3		(0 << BP_DDR_TYPE_SHIFT)
+#define BP_DDR_TYPE_DDR4		(1 << BP_DDR_TYPE_SHIFT)
+#define BP_DDR_IS_DDR4(mcb_sel)		(((mcb_sel)&BP_DDR_TYPE_MASK) == BP_DDR_TYPE_DDR4)
+#endif
+
+/* Vtt termination settings. Vtt termination is required in the board design for 
+   Address and Control line to improve the signal integrity when it need to support
+   DDR at high clock. For slow DDR, Vtt termination is not used. It can be no termination 
+   at all with direct connection through serial resistor from DDR chip to the PHY or 
+   with passive terminatin of a pull-up and pull-down resistors.
+
+   In low-end 2 layer board design, Vtt usually is not used as DDR runs slow so PCB_2LAYER
+   option is essetnially Vtt dsiabled. But Vtt option is not determined by the layer of PCB. 
+   Keep this PCB definition only for compatiblity reason and new design should use VTT setting.
+ */
+#if defined(BP_DDR_SUPPORT_2L_PCB)
+#define BP_DDR_PCB_MASK			0x20000000
+#define BP_DDR_PCB_SHIFT		29
+#define BP_DDR_PCB_MULTI_LAYER		(0 << BP_DDR_PCB_SHIFT)
+#define BP_DDR_PCB_2LAYER		(1 << BP_DDR_PCB_SHIFT)
+#endif
+
+#if defined(BP_DDR_SUPPORT_VTT)
+#define BP_DDR_VTT_MASK			0x30000000
+#define BP_DDR_VTT_SHIFT		28
+#define BP_DDR_VTT_EN			(0 << BP_DDR_VTT_SHIFT)	/* Vtt enabled */
+#define BP_DDR_VTT_EN_DR		(3 << BP_DDR_VTT_SHIFT) /* Vtt enabled with dual rank ddr support */
+#define BP_DDR_VTT_DIS_NOTERM		(2 << BP_DDR_VTT_SHIFT)	/* Vtt disabled with no AC termination */
+#if defined(BP_DDR_SUPPORT_VTT_DIS_PASVTERM)
+#define BP_DDR_VTT_DIS_PASVTERM		(1 << BP_DDR_VTT_SHIFT)	/* Vtt disabled with passive AC termination */
+#endif
+#endif
+
+#define BP_DDR_CONFIG_MASK		(~(BP_DDR_CONFIG_DEBUG|BP_DDR_CONFIG_OVERRIDE))
+#define BP_DDR_CONFIG_DEBUG		(1 << 30)
+#define BP_DDR_CONFIG_OVERRIDE		(1 << 31)
+
+#define BP_DDR_SEL_VALUE(mcb_sel)	((mcb_sel)&BP_DDR_CONFIG_MASK)
+
+#define MCB_SIZE			608
+
+typedef struct _ddr_init_param {
+	uint32_t mcb_sel;
+	uint32_t *mcb;
+	uint32_t *seed;
+	int      safe_mode;
+	uint32_t *ddr_size;
+#if defined(CONFIG_BCMBCA_DPFE)
+	void* dpfe_stdalone;
+	uint8_t* dpfe_segbuf;
+#endif
+} ddr_init_param;
+
+typedef int (*ddr_init_func) (ddr_init_param* param);
+
+#if defined(CONFIG_BCMBCA_DPFE)
+extern int ddr_init_dpfe(ddr_init_param* ddrinit_params);
+#endif
+
+#if defined(CONFIG_BCMBCA_DDR_REGINIT)
+extern int ddr_init_reg(ddr_init_param* ddrinit_params);
+#endif
+
+#define JTAG_LOAD_MCB_BIN_OFFSET	8
+#define SPL_DDR_INIT_MCB_OVRD		0x1
+#define SPL_DDR_INIT_MCB_SEL		0x2
+#define SPL_DDR_INIT_DDR3_SAFE_MODE		0x4
+#define SPL_DDR_INIT_DDR4_SAFE_MODE		0x8
+int spl_ddrinit(uint32_t sel_mode, uint32_t sel);
+void spl_ddrinit_prepare(void);
+uint32_t get_ddr_size(void);
+void spl_list_mcb_sel(void);
+#endif
diff --git a/arch/arm/mach-bcmbca/include/spl_env.h b/arch/arm/mach-bcmbca/include/spl_env.h
new file mode 100644
index 0000000000..facc456c0c
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/spl_env.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _TPL_ENV_H
+#define _TPL_ENV_H
+
+#define TPL_ENV_ADDR ((CONFIG_TPL_TEXT_BASE - BOOT_BLOB_MAX_ENV_SIZE)&~0xff)
+
+char *find_spl_env_val(const char *buffer, const char *name);
+
+int get_spl_env_val(const char *buffer, const char *name, char *out, int maxlen);
+
+int validate_metadata(char *cp,int *valid,int *comitted,int *seq) ;
+
+/* UBOOT has multiple conflicting CRC32 functions... so we'll wrap the right one */
+uint32_t the_env_crc32(int a, void *b, int len) ;
+
+#define ENV_AVS_DISABLE "avs_disable"
+
+#endif
diff --git a/arch/arm/mach-bcmbca/include/tpl_params.h b/arch/arm/mach-bcmbca/include/tpl_params.h
new file mode 100644
index 0000000000..f59437378f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/include/tpl_params.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _TPL_PARAMS_H
+#define _TPL_PARAMS_H
+
+#include "boot_blob.h"
+
+#define EF_JTAG_LOAD 0x1
+
+typedef struct tpl_params_s {
+	void *environment;
+	uint32_t early_flags;
+	uint32_t ddr_size;  /* in MB */
+	uint8_t boot_device; 
+} tpl_params;
+
+extern uint32_t boot_params;
+#if defined(CONFIG_TPL_BUILD)
+extern tpl_params* tplparams;
+#endif
+
+#define TPL_PARAMS_ADDR ((CONFIG_TPL_TEXT_BASE - BOOT_BLOB_MAX_ENV_SIZE - sizeof(tpl_params) \
+	- 0x100)&~0xff)
+
+#define IS_JTAG_LOADED(params) ((params) & EF_JTAG_LOAD)
+
+#endif
diff --git a/arch/arm/mach-bcmbca/lowlevel_init.S b/arch/arm/mach-bcmbca/lowlevel_init.S
new file mode 100644
index 0000000000..e209058ad6
--- /dev/null
+++ b/arch/arm/mach-bcmbca/lowlevel_init.S
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ *
+ */
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+#ifndef CONFIG_TPL_BUILD	
+.align 8
+.global boot_params
+boot_params:
+	.word 0x0
+
+.global save_boot_params
+save_boot_params:
+
+#ifdef CONFIG_ARM64
+	ldr	x10, =0xd0deed
+	cmp	x9, x10
+	bne	1f
+	adr	x8, boot_params
+	ldr	w9, [x8]
+	orr	w9, w9, #0x1
+	str	w9, [x8]
+#else
+	ldr	r10,=0xd0deed
+	cmp	r9, r10
+	bne	1f
+	ldr	r9, boot_params
+	orr	r9, r9, #0x1
+	str	r9, boot_params
+#endif
+
+1:
+	/* Returns */
+	b	save_boot_params_ret
+#endif
+	
+#if defined(CONFIG_TPL_ATF) && defined(CONFIG_ARM64)
+/*
+ * Called by armv8_switch_to_el2 to switch from el2 to el1
+ * aarch32. When ATF support this switch, we can remove
+ * this function
+ */
+ENTRY(armv8_el2_to_aarch32)
+	armv8_switch_to_el1_m x4, x5, x6	
+ENDPROC(armv8_el2_to_aarch32)	
+#endif	
diff --git a/arch/arm/mach-bcmbca/mmu_setup.c b/arch/arm/mach-bcmbca/mmu_setup.c
new file mode 100644
index 0000000000..71ef0f9336
--- /dev/null
+++ b/arch/arm/mach-bcmbca/mmu_setup.c
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#ifdef CONFIG_CPU_V7A
+#include "mmu_map_v7.h"
+#else
+#include <asm/armv8/mmu.h>
+#endif
+
+#if !(CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CPU_V7A
+int __attribute__((section(".data"))) reg_mmu_init = 0;
+
+void arm_init_domains(void)
+{
+	/* Set the access control to client so AP is checked with tlb entry */
+	asm volatile("mcr p15, 0, %0, c3, c0, 0"
+		     : : "r" (0x55555555));
+}
+
+/* 
+ * Override the weak dram_bank_mmu_setup to setup not only dram but
+ * entire mmu based on the mem_map list. This function is called by mmu_setup
+ */
+void dram_bank_mmu_setup(int bank)
+{
+
+	bd_t *bd = gd->bd;
+	int i, j, section, num_sec;
+	uint32_t *page_table = (u32 *)gd->arch.tlb_addr;
+	uint32_t pgt_size = gd->arch.tlb_size;
+	uint32_t virt;
+
+	/* zereod out the entire table so undefined region is not accessible */
+	if (reg_mmu_init == 0)
+		memset((void*)page_table, 0x0, pgt_size);
+
+	if (bd && bd->bi_dram[bank].size) {
+		for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+		     i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
+			 (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
+		     i++) {
+			set_section_attr(i, i<<MMU_SECTION_SHIFT, SECTION_ATTR_CACHED_MEM);
+		}
+	}
+
+	if (reg_mmu_init)
+		return;
+
+	for (i = 0; mem_map[i].size; i++) {
+		section = mem_map[i].phys >> MMU_SECTION_SHIFT;
+		num_sec = mem_map[i].size >> MMU_SECTION_SHIFT;
+		virt = mem_map[i].virt >> MMU_SECTION_SHIFT;
+		for( j = 0; j < num_sec; j++)
+			set_section_attr(section+j, (virt+j)<<MMU_SECTION_SHIFT, mem_map[i].attrs);
+	}
+	reg_mmu_init = 1;
+
+}
+
+#else
+
+static void bcm_setup_pgtables(void)
+{
+	u64 tlb_addr = gd->arch.tlb_addr;
+	u64 tlb_size = gd->arch.tlb_size;
+
+	/* Reset the fill ptr */
+	gd->arch.tlb_fillptr = tlb_addr;
+
+	/* Create normal system page tables */
+	setup_pgtables();
+
+#if !defined(CONFIG_SPL_BUILD)
+	/* Create emergency page tables */
+	gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr -
+			     (uintptr_t)gd->arch.tlb_addr;
+	gd->arch.tlb_addr = gd->arch.tlb_fillptr;
+	setup_pgtables();
+	gd->arch.tlb_emerg = gd->arch.tlb_addr;
+#endif
+
+	gd->arch.tlb_addr = tlb_addr;
+	gd->arch.tlb_size = tlb_size;
+}
+
+void mmu_setup(void)
+{
+	int el;
+
+	/* Set up page tables only once */
+	if (!gd->arch.tlb_fillptr)
+		bcm_setup_pgtables();
+
+	el = current_el();
+	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
+			  MEMORY_ATTRIBUTES);
+
+	/* enable the mmu */
+	set_sctlr(get_sctlr() | CR_M);
+}
+#endif
+#endif
+
+void enable_caches(void)
+{
+	icache_enable();
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+	dcache_enable();
+#endif
+}
+
diff --git a/arch/arm/mach-bcmbca/otp/Makefile b/arch/arm/mach-bcmbca/otp/Makefile
new file mode 100644
index 0000000000..10f2b93f53
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp/Makefile
@@ -0,0 +1,8 @@
+obj-$(CONFIG_BCMBCA_OTP) += bcm_otp.o
+obj-$(CONFIG_BCMBCA_OTP) += otp_map_cmn.o
+obj-$(CONFIG_BCMBCA_OTP) += otp_hw.o
+obj-$(CONFIG_OTP_SOTP) += sotp_hw.o
+obj-$(CONFIG_OTP_LOCK) += otp_hw_cpu_lock.o
+obj-$(CONFIG_OTP_V2) += otp_hw_ecc.o
+obj-$(CONFIG_OTP_SKP) += skp_hw.o
+obj-$(CONFIG_OTP_SKO) += sko_hw.o
diff --git a/arch/arm/mach-bcmbca/otp/bcm_otp.c b/arch/arm/mach-bcmbca/otp/bcm_otp.c
new file mode 100644
index 0000000000..611f4f3ed0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp/bcm_otp.c
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2020 Broadcom Ltd.
+ */
+#include <common.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include "linux/printk.h"
+#include <asm/arch/otp.h>
+#include <asm/arch/misc.h>
+#include <malloc.h>
+#include "bcm_secure.h"
+#include "bcm_otp.h"
+
+/* global and static reserved in data section will not be nuked by bss clean loop*/
+static bcm_otp_t *s_bcm_otp __attribute__((section(".data"))) = NULL;
+
+__weak otp_hw_cmn_err_t otp_hw_cmn_init(otp_hw_cmn_t* dev)
+{
+	return OTP_HW_CMN_ERR_UNSP;
+}
+__weak otp_hw_cmn_err_t sotp_hw_cmn_init(otp_hw_cmn_t* dev)
+{
+	return OTP_HW_CMN_ERR_UNSP;
+}
+
+static otp_map_cmn_t* _get_map(otp_map_feat_t feat)
+{
+	if ((int)feat  <= OTP_MAP_INVALID || 
+		(int) feat == SOTP_MAP_INVALID ||
+		(int) feat >= OTP_MAP_MAX) {
+		return NULL;
+	}
+	return  bcm_otp( feat < SOTP_MAP_INVALID? BCM_OTP_MAP : BCM_SOTP_MAP); 
+}
+
+int bcm_otp_init()
+{
+	otp_map_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL;
+	static otp_map_cmn_t s_map_obj[BCM_MAP_MAX] __attribute__((section(".data")));
+	static bcm_otp_t s_otp_obj __attribute__((section(".data")));
+	if (s_bcm_otp) {
+		printf ("%s ERROR: BCM_OTP - not reentrant\n", __FUNCTION__);
+		goto err;
+	}
+/*
+ * malloc if desired here
+ * */
+	memset(s_map_obj, 0, sizeof(s_map_obj));
+	memset(&s_otp_obj, 0, sizeof(s_otp_obj));
+
+	rc = otp_map_cmn_init(&s_map_obj[BCM_OTP_MAP], otp_hw_cmn_init, NULL);
+	if (rc) {
+		printf ("%s ERROR: BCM_OTP unable to initialize OTP\n", __FUNCTION__);
+		goto err;
+	}
+
+	s_otp_obj.map[BCM_OTP_MAP] = &s_map_obj[BCM_OTP_MAP];
+
+	rc = otp_map_cmn_init(&s_map_obj[BCM_SOTP_MAP], 
+				sotp_hw_cmn_init, &s_otp_obj.map[BCM_OTP_MAP]->dev);
+	if (rc) {
+		if (rc != OTP_MAP_CMN_ERR_UNSP) {
+			printf ("%s ERROR: BCM_OTP unable to initialize SOTP\n", __FUNCTION__);
+			goto err;
+		}
+		s_otp_obj.map[BCM_SOTP_MAP] = NULL;
+	} else {
+		s_otp_obj.map[BCM_SOTP_MAP] = &s_map_obj[BCM_SOTP_MAP];
+	}
+
+	s_bcm_otp = &s_otp_obj;
+	rc = OTP_MAP_CMN_OK;
+err:
+	return rc;
+}
+
+otp_map_cmn_t* bcm_otp(otp_map_t id)
+{
+	return (id < BCM_OTP_MAP || id >= BCM_MAP_MAX || !s_bcm_otp)?  NULL : s_bcm_otp->map[id];
+}
+
+otp_map_cmn_err_t bcm_otp_read(otp_map_feat_t otp_feat, u32** data, u32* size)
+{
+	otp_map_cmn_t* obj = _get_map(otp_feat);
+	if (!obj ) {
+		return OTP_MAP_CMN_ERR_FAIL;
+	}
+	return obj->read(obj, otp_feat, data, size);
+}
+
+otp_map_cmn_err_t bcm_otp_get(otp_map_feat_t otp_feat, u32* data)
+{
+	otp_map_cmn_err_t  rc = OTP_MAP_CMN_ERR_FAIL;
+	u32 size = 0;
+	u32* p = NULL;
+	rc = bcm_otp_read(otp_feat, &p, &size);
+	if (rc) {
+		goto err;
+	}
+	if (size > sizeof(u32)) {
+		rc =  OTP_MAP_CMN_ERR_INVAL;
+		goto err;
+	}
+	memcpy(data, p ,sizeof(u32));
+	rc = OTP_MAP_CMN_OK;
+err:
+	return rc;
+}
+
+
+otp_map_cmn_err_t bcm_otp_write(otp_map_feat_t otp_feat, const u32* data, u32 size)
+{
+	otp_map_cmn_t* obj = _get_map(otp_feat);
+	if (!obj ) {
+		return OTP_MAP_CMN_ERR_FAIL;
+	}
+	return obj->write(obj, otp_feat, data, size);
+}
+
+otp_map_cmn_err_t bcm_otp_ctl(otp_map_t id, 	
+		otp_hw_cmn_ctl_cmd_t *cmd, u32 *res)
+{
+	otp_map_cmn_t* obj = bcm_otp(id);
+	if (!obj) {
+		return OTP_MAP_CMN_ERR_FAIL;
+	}
+	return obj->ctl(obj, cmd, res);
+}
+
+/* an SOTP helper*/
+otp_map_cmn_err_t bcm_sotp_ctl_perm( otp_hw_cmn_ctl_t ctl, 
+			u32 data, u32* res)
+{
+	otp_map_cmn_err_t rc = OTP_MAP_CMN_ERR_INVAL;
+	u32 stat = 0;
+	otp_hw_ctl_data_t ctl_data = {0} ;
+	otp_hw_cmn_ctl_cmd_t cmd = {
+		.ctl = ctl,
+		.data = (uintptr_t)&ctl_data, 
+		.size = sizeof(ctl_data)
+	};
+	otp_map_cmn_t* obj = bcm_otp(BCM_SOTP_MAP);
+	if (!obj) {
+		return rc;
+	}
+	switch(cmd.ctl) {
+   		case OTP_HW_CMN_CTL_STATUS: {
+			if (!res) {
+				goto err; 
+			}
+			ctl_data.status = (otp_hw_cmn_status_t) data; 
+			break;
+		}
+   		case OTP_HW_CMN_CTL_LOCK:
+   		case OTP_HW_CMN_CTL_UNLOCK:
+			ctl_data.perm = (otp_hw_cmn_perm_t) data; 
+			break;
+		default:
+			rc = OTP_MAP_CMN_ERR_UNSP;
+			goto err;		
+	}
+	rc = obj->ctl(obj, &cmd, &stat);
+	if (rc) {
+		goto err;	
+	}	
+	if (res) {
+		*res = stat;
+	}
+	
+err:
+	return rc;	
+}
+
+int bcm_otp_get_ldo_trim(unsigned int* val)
+{
+    return bcm_otp_get(OTP_MAP_LDO_TRIM, val);
+}
+
+int bcm_otp_get_cpu_clk(unsigned int* val)
+{
+    return bcm_otp_get(OTP_MAP_CPU_CLOCK_FREQ, val);
+}
+
+int bcm_otp_get_chipid(unsigned int* val)
+{
+    return bcm_otp_get(OTP_MAP_SEC_CHIPVAR, val);
+}
+
+int bcm_otp_get_nr_cpus(u32* val)
+{
+	return bcm_otp_get(OTP_MAP_CPU_CORE_CFG, val);
+}
+
+
+
+
diff --git a/arch/arm/mach-bcmbca/otp/otp_hw.c b/arch/arm/mach-bcmbca/otp/otp_hw.c
new file mode 100644
index 0000000000..3d5ebda01a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp/otp_hw.c
@@ -0,0 +1,357 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+/**********************************************************************
+ *	
+ * OTP controller driver 
+ *	
+ *********************************************************************	
+ */
+#include <common.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include "linux/printk.h"
+#include <asm/arch/misc.h>
+#include <asm/arch/otp.h>
+#include "otp_hw.h" 
+#include "otp_map_cmn.h"
+
+//#define OTP_DRY_RUN
+//#define DBG_OTP
+#ifdef DBG_OTP
+#define _ETR(__p__)  printf("%s ERROR: \n\t\t\t\t -> %s:%d code %d\n",__FILE__,__FUNCTION__,__LINE__,__p__)
+#define _TR(__p__)  printf("%s \n\t\t\t\t -> %s:%d %d (0x%x)\n",__FILE__,__FUNCTION__,__LINE__,__p__,__p__)
+#define _DPRT(...)  printf(__VA_ARGS__) 
+#else
+#define _ETR(__p__)
+#define _TR(__p__)
+#define _DPRT(...)
+#endif
+
+__weak void otp_hw_writel(void* dev, u32 offset, u32 data)
+{
+	otp_hw_cmn_t* otp_hw = (otp_hw_cmn_t*)dev; 
+	writel(data, otp_hw->mm + offset);
+}
+
+__weak u32 otp_hw_readl(void* dev, u32 offset)
+{
+	otp_hw_cmn_t* otp_hw = (otp_hw_cmn_t*)dev;
+	return readl(otp_hw->mm+offset);	
+}
+
+__weak otp_hw_cmn_err_t otp_hw_cpu_lock(otp_hw_cmn_t* dev)
+{
+	return OTP_HW_CMN_OK;
+}
+
+__weak void otp_hw_cpu_unlock(otp_hw_cmn_t* dev)
+{
+	/* Release hardware spinlock for OTP */
+}
+
+__weak otp_hw_cmn_err_t otp_hw_set_ecc(otp_hw_cmn_t* dev, u32 ecc)
+{
+	return OTP_HW_CMN_ERR_UNSP;
+}
+
+__weak u32 otp_hw_get_ecc(otp_hw_cmn_t* dev, u32* ecc)
+{
+	return OTP_HW_CMN_ERR_UNSP;
+}
+
+static int otp_wait_cmd_done(otp_hw_cmn_t *dev)
+{
+	long to = OTP_STATUS_CMD_DONE_TMO_CNT;
+	while (to && !(otp_hw_readl(dev, OTP_STATUS1_OFFSET)&OTP_STATUS1_CMD_DONE)) {
+		udelay(1);
+		to--;
+	}
+	return (!to);
+}
+
+static int otp_wait_cmd_ready(otp_hw_cmn_t *dev)
+{
+	int to = OTP_STATUS_CMD_DONE_TMO_CNT;
+	do {
+		if (((otp_hw_readl(dev, OTP_STATUS1_OFFSET))&OTP_STATUS1_CMD_DONE) != 0) {
+			break;
+		}
+		udelay(1);
+		to--;
+	} while (to);
+	return (!to);	
+}
+
+/*Enables OTP programming mode*/
+static otp_hw_cmn_err_t  otp_auth_prog_mode(otp_hw_cmn_t *dev)
+{
+	int i = 0;
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_TMO;
+	u32 authVal[ ] = {0xf, 0x4, 0x8, 0xd};
+	if(otp_hw_cpu_lock(dev)) {
+		_ETR(rc);	
+      		goto err;
+	}
+
+	otp_hw_writel(dev, OTP_CTRL0_OFFSET, 0x0);
+	/* Enable CPU side programming of OTP */
+	otp_hw_writel(dev, OTP_CTRL1_OFFSET, 
+			(otp_hw_readl(dev, OTP_CTRL1_OFFSET)|OTP_CTRL1_CPU_MODE));
+	/* Clear row register. A non-empty row register results in a failed prog-enable sequence on some SoCs */
+	otp_hw_writel(dev, OTP_CTRL3_OFFSET, 0x0);
+	/* Put OTP in program mode --> prog-enable sequence */
+	for (i = 0; i < sizeof(authVal)/sizeof(u32); i++) {
+		otp_hw_writel(dev, OTP_CTRL2_OFFSET, authVal[i]);
+		otp_hw_writel(dev, OTP_CTRL0_OFFSET, OTP_CTRL0_PROG_MODE_ENABLE);
+		if ( otp_wait_cmd_done(dev)) {
+			_ETR(rc);	
+         		printf("%s: ERROR! Timed out waiting for  Program Mode; status:0x%08x\n", 
+				__FUNCTION__, otp_hw_readl(dev, OTP_STATUS1_OFFSET));
+         		goto err;
+      		}
+		otp_hw_writel(dev, OTP_CTRL0_OFFSET, 0x0);
+   	}
+	udelay(300);
+	if ((otp_hw_readl(dev, OTP_STATUS1_OFFSET) & OTP_STATUS1_PROG_OK) != OTP_STATUS1_PROG_OK) {
+		_ETR(rc);
+		printf("%s: ERROR: Unable to set OTP program mode OTP\n",__FUNCTION__);
+		goto err;
+	}
+	rc = OTP_HW_CMN_OK;
+err:
+	if (rc) {
+		otp_hw_cpu_unlock(dev);
+	}
+	return rc;
+}
+
+static otp_hw_cmn_err_t otp_auth_prog_mode_done(otp_hw_cmn_t *dev)
+{
+	otp_hw_writel(dev, OTP_CTRL0_OFFSET, 0x0);
+	otp_hw_writel(dev, OTP_CTRL1_OFFSET, 
+			(otp_hw_readl(dev, OTP_CTRL1_OFFSET)&(~OTP_CTRL1_CPU_MODE)));
+	otp_hw_cpu_unlock(dev);
+	return OTP_HW_CMN_OK;
+}
+
+__weak otp_hw_cmn_err_t otp_hw_cmn_ctl(otp_hw_cmn_t *dev, 
+			const otp_hw_cmn_ctl_cmd_t *cmd,
+			u32* res)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_UNSP;
+	switch ((u32)cmd->ctl) {
+   		case OTP_HW_CMN_CTL_OTPCMD_AUTH_PROG:
+ 			rc = otp_auth_prog_mode(dev);
+			break;
+  		case OTP_HW_CMN_CTL_OTPCMD_AUTH_PROG_DONE:
+ 			rc =otp_auth_prog_mode_done(dev);
+			break;
+   		case OTP_HW_CMN_CTL_CONF:
+			memcpy(&dev->row_conf, 
+				(otp_hw_cmn_row_conf_t*)cmd->data, 
+				cmd->size);
+
+			dev->ctl_cmd.ctl |= cmd->ctl;
+			rc = OTP_HW_CMN_OK;
+			break;
+   		case (~((u32)OTP_HW_CMN_CTL_CONF)):
+			dev->ctl_cmd.ctl &= ~cmd->ctl;
+			rc = OTP_HW_CMN_OK;
+			break;
+		default :
+			break;	
+	}
+	return rc;
+	
+}
+
+/************************************************************
+ *  int bcm_otp_hw_write 
+ *  Input parameters: 
+ *     addr   - Row address
+ *  Return value:
+ ***********************************************************/
+__weak otp_hw_cmn_err_t  otp_hw_write(otp_hw_cmn_t *dev, 
+				u32 addr,
+				otp_hw_cmn_row_conf_t* row_conf,
+				const u32* data,
+				u32 size)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_TMO;
+	if (size < sizeof(u32)) {
+		rc = OTP_HW_CMN_ERR_INVAL;
+		_ETR(rc);
+		goto err;
+	}
+	if (row_conf && (row_conf->op_type & OTP_HW_CMN_CTL_OTPCMD_ECC)) {
+		if (size < sizeof(u32)*2) {
+			rc = OTP_HW_CMN_ERR_INVAL;
+			_ETR(rc);
+			goto err;
+		}
+	}
+	_DPRT("%s:%d DEBUG: fusing data 0x%x at 0x%x\n",__FUNCTION__,__LINE__, *data, addr);
+	rc = otp_auth_prog_mode(dev);
+	if (rc) {
+		_ETR(rc);
+		goto err;
+	}
+
+#ifndef OTP_DRY_RUN
+	otp_hw_writel(dev, OTP_CTRL2_OFFSET, *data);
+#endif
+	if ( row_conf && (row_conf->op_type&OTP_HW_CMN_CTL_OTPCMD_ECC) ) {
+		otp_hw_set_ecc(dev, *(data + 1));
+	}
+#ifndef OTP_DRY_RUN
+	otp_hw_writel(dev, OTP_CTRL3_OFFSET, addr);
+#endif
+	if (row_conf && (row_conf->op_type & OTP_HW_CMN_CTL_OTPCMD_PROG_LOCK)) {
+		otp_hw_writel(dev, OTP_CTRL0_OFFSET, (OTP_CTRL0_PROG_CMD_START|OTP_CTRL0_CMD_PROG_LOCK));
+	} else {
+		otp_hw_writel(dev, OTP_CTRL0_OFFSET, OTP_CTRL0_PROG_CMD_START);
+	}
+
+#ifndef OTP_DRY_RUN
+	if (otp_wait_cmd_done(dev)) {
+		printf("%s: ERROR! Timed out waiting for OTP command completion (WRITE)! status: 0x%08x\n", 
+		__FUNCTION__, otp_hw_readl(dev, OTP_STATUS1_OFFSET));
+		goto err;
+	}
+#endif
+	_DPRT("%s:%d Fused: 0x%x  \n", __FUNCTION__,__LINE__,*data);
+	rc = OTP_HW_CMN_OK;
+err:
+	otp_auth_prog_mode_done(dev);
+	return rc;
+}
+
+/***********************************************************
+ *  otp_hw_cmn_err_t otp_hw_read
+ *  Input parameters: 
+ *     addr    - Row address
+ *  Return value:
+ *      returns 0 if successful, value in *value
+ ***********************************************************/
+__weak otp_hw_cmn_err_t  otp_hw_read(otp_hw_cmn_t *dev, 
+				u32 addr,
+				otp_hw_cmn_row_conf_t* row_conf,
+				u32* data,
+				u32 size)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_TMO;
+	if (size < sizeof(u32)) {
+		rc = OTP_HW_CMN_ERR_FAIL;
+		_ETR(rc);
+		goto err;
+	}
+	if (row_conf && (row_conf->op_type & OTP_HW_CMN_CTL_OTPCMD_ECC)) {
+		if (size < sizeof(u32)*2) {
+			rc = OTP_HW_CMN_ERR_INVAL;
+			_ETR(rc);
+			goto err;
+		}
+	}
+
+	rc = otp_hw_cpu_lock(dev);
+	if (rc) {
+		_ETR(rc);
+		goto err;
+	}
+
+	if ((otp_hw_readl(dev, OTP_STATUS1_OFFSET)&OTP_STATUS1_CMD_DONE) == 0){
+		_DPRT("%s 1 CMD done was not set\n", __FUNCTION__);
+	}	
+	/* turn on cpu mode, set up row addr, activate read word */
+	otp_hw_writel(dev, OTP_CTRL1_OFFSET, 
+			(otp_hw_readl(dev, OTP_CTRL1_OFFSET)|OTP_CTRL1_CPU_MODE));
+	otp_hw_writel(dev, OTP_CTRL3_OFFSET, addr);
+	otp_hw_writel(dev, OTP_CTRL0_OFFSET, OTP_CTRL0_START);
+
+	/* Wait for low CMD_DONE (current operation has begun), reset countdown, wait for retrieval to complete 
+ 	*	Redundant; can't be always caught 
+ 	*	 	*/
+	otp_wait_cmd_ready(dev);
+	/* Wait for high CMD_DONE */
+	if (otp_wait_cmd_done(dev)) {
+		_ETR(rc);
+		printf("%s: ERROR! Timed out waiting for OTP command completion (READ)! status: 0x%08x\n", 
+		__FUNCTION__, otp_hw_readl(dev, OTP_STATUS1_OFFSET));
+		goto err;
+   	}
+
+	/* If read was successful, retrieve data */
+   
+	*data = otp_hw_readl(dev, OTP_STATUS0_OFFSET);
+	_DPRT("DEBUG: got 0x%x from otp\n", *data);
+	if (row_conf && (row_conf->op_type & OTP_HW_CMN_CTL_OTPCMD_ECC)) {
+		otp_hw_get_ecc(dev, data + 1);
+	}
+
+	rc = OTP_HW_CMN_OK;
+	/* zero out the ctrl_0 reg, turn off cpu mode, return results */
+err:
+	otp_hw_writel(dev, OTP_CTRL0_OFFSET, 0x0);
+	otp_hw_writel(dev, OTP_CTRL1_OFFSET,
+			(otp_hw_readl(dev, OTP_CTRL1_OFFSET)&(~OTP_CTRL1_CPU_MODE)));
+	otp_hw_cpu_unlock(dev);
+	return rc;
+}
+
+static  otp_hw_cmn_err_t write(otp_hw_cmn_t* dev, 
+		u32 addr,
+		const u32* data,
+		u32 size)
+{
+	otp_hw_cmn_row_conf_t *cfg =  
+				(dev->ctl_cmd.ctl&OTP_HW_CMN_CTL_CONF)? &dev->row_conf : NULL;
+	return dev->write_ex? 
+		dev->write_ex(dev, addr, cfg, data, size) : OTP_HW_CMN_ERR_UNSP;
+}
+
+static otp_hw_cmn_err_t read(otp_hw_cmn_t *dev,
+			u32 addr,
+			u32 *data,
+			u32 size)
+{
+	otp_hw_cmn_row_conf_t *cfg =  
+		(dev->ctl_cmd.ctl&OTP_HW_CMN_CTL_CONF)? 
+			&dev->row_conf : NULL;
+	return dev->read_ex?
+		dev->read_ex(dev, addr, cfg, data, size):OTP_HW_CMN_ERR_UNSP;
+
+}
+__weak otp_hw_cmn_err_t otp_hw_dev_mmap(otp_hw_cmn_t* dev)
+{
+	dev->mm = JTAG_OTP_BASE;
+	return OTP_HW_CMN_OK;
+}
+
+__weak otp_hw_cmn_err_t otp_hw_init(otp_hw_cmn_t* dev)
+{
+	DEFINE_OTP_MAP_ROW_INITLR(rows);
+	if (otp_hw_dev_mmap(dev)) {
+		return OTP_HW_CMN_ERR_FAIL;
+	}
+	dev->rows = rows;
+	dev->row_max = sizeof(rows)/sizeof(otp_hw_cmn_row_t);
+	return OTP_HW_CMN_OK;
+}
+
+
+otp_hw_cmn_err_t otp_hw_cmn_init(otp_hw_cmn_t* dev)
+{
+	if (otp_hw_init(dev)) {
+		return OTP_HW_CMN_ERR_FAIL;
+	}
+	dev->read = read;
+	dev->write = write;
+	dev->read_ex = otp_hw_read;
+	dev->write_ex = otp_hw_write;
+	dev->ctl = otp_hw_cmn_ctl;
+	return OTP_HW_CMN_OK;
+}
+
diff --git a/arch/arm/mach-bcmbca/otp/otp_hw_cpu_lock.c b/arch/arm/mach-bcmbca/otp/otp_hw_cpu_lock.c
new file mode 100644
index 0000000000..a3762c258e
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp/otp_hw_cpu_lock.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+
+/**********************************************************************
+ *	
+ * OTP HW CPU lock semaphore  
+ *	
+ *********************************************************************	
+ */
+#include <common.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include "linux/printk.h"
+#include <asm/arch/misc.h>
+#include <asm/arch/otp.h>
+#include "otp_hw.h" 
+#include "otp_map_cmn.h" 
+
+
+otp_hw_cmn_err_t otp_hw_cpu_lock(otp_hw_cmn_t* dev)
+{
+	/*  HW Lock the OTP controller
+	*   Until lock is obtained the HW will NOT PERMIT the CPU to access 
+	*   OTP control registers
+ 	**/
+	int to = OTP_CPU_LOCK_TMO_CNT;
+	writel(0x1, dev->mm + OTP_CPU_LOCK_OFFSET);
+	while( to && 
+		!((readl(dev->mm + OTP_CPU_LOCK_OFFSET)>>OTP_CPU_LOCK_SHIFT) & OTP_CPU_LOCK_MASK))  {
+		udelay(1);
+		to--;
+	}
+	if ( to < 1) {
+		printf("%s: Error! Timed out waiting for OTP_CPU_LOCK!\n", __FUNCTION__);
+		return OTP_HW_CMN_ERR_TMO;
+	}
+	return OTP_HW_CMN_OK;
+}
+
+void otp_hw_cpu_unlock(otp_hw_cmn_t* dev)
+{
+	/* Release hardware spinlock for OTP */
+	writel(0x0, dev->mm + OTP_CPU_LOCK_OFFSET);
+}
+
diff --git a/arch/arm/mach-bcmbca/otp/otp_hw_ecc.c b/arch/arm/mach-bcmbca/otp/otp_hw_ecc.c
new file mode 100644
index 0000000000..0fed7987e6
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp/otp_hw_ecc.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+/**********************************************************************
+ *	
+ * OTP hw ecc function  
+ *
+ *	
+ ********************************************************************	
+ */
+#include <common.h>
+#include <linux/types.h>
+#include "linux/io.h"
+#include "linux/printk.h"
+#include <asm/arch/misc.h>
+#include <asm/arch/otp.h>
+#include "otp_hw.h"
+#include "otp_map_cmn.h"
+
+//#define OTP_DRY_RUN
+
+otp_hw_cmn_err_t otp_hw_set_ecc(otp_hw_cmn_t* dev, u32 ecc)
+{
+	//printf("%s FUSE ECC 0x%x \n", __FUNCTION__,ecc);
+#ifndef OTP_DRY_RUN
+	writel(ecc, dev->mm + OTP_CTRL2_HI_OFFSET);
+#endif
+	return OTP_HW_CMN_OK;
+}
+
+otp_hw_cmn_err_t otp_hw_get_ecc(otp_hw_cmn_t* dev, u32* ecc)
+{
+	*ecc = readl(dev->mm + OTP_STATUS0_HI_OFFSET);
+	return OTP_HW_CMN_OK;
+}
diff --git a/arch/arm/mach-bcmbca/otp/otp_map_cmn.c b/arch/arm/mach-bcmbca/otp/otp_map_cmn.c
new file mode 100644
index 0000000000..52c7737b5d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp/otp_map_cmn.c
@@ -0,0 +1,282 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+#include <common.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include "linux/printk.h"
+#include <asm/arch/otp.h>
+#include <asm/arch/misc.h>
+#include <malloc.h>
+#include "bcm_secure.h"
+#include "otp_map_cmn.h"
+
+//#define DBG_OTP
+
+#ifdef DBG_OTP
+#define _ETR(__p__)  printf("%s \n\t\t\t\t -> %s:%d code %d\n",__FILE__, __FUNCTION__,__LINE__,__p__)
+#define _DPRT(...)  printf(__VA_ARGS__) 
+#else
+#define _ETR(__p__)
+#define _DPRT(...)
+#endif
+/* address finder  */
+static otp_map_cmn_err_t __get_addr(otp_map_cmn_t *obj, 
+				otp_map_feat_t ft,
+				u32* idx)
+{
+	int i ;
+	otp_hw_cmn_t* dev = &obj->dev;
+	otp_hw_cmn_row_t* rows = dev->rows;	
+	for (i = 0; i < dev->row_max; i++ ) {
+		if (ft > OTP_MAP_INVALID && ft < OTP_MAP_MAX) {
+			if (ft ==  rows[i].feat) {
+				*idx = i;
+				_DPRT("%s:%d id %d \n",__FUNCTION__,__LINE__, i);
+				return OTP_MAP_CMN_OK;	
+			} 
+		}
+	}
+	_DPRT("%s:%d feat %d \n",__FUNCTION__,__LINE__, ft);
+	return OTP_MAP_CMN_ERR_UNSP;	
+}
+ 
+/* redirects to device base control function.  */
+static otp_map_cmn_err_t otp_map_cmn_ctl(otp_map_cmn_t *obj,
+			otp_hw_cmn_ctl_cmd_t* cmd,  u32* res)
+{
+	otp_map_cmn_err_t rc = OTP_MAP_CMN_ERR_FAIL;
+	otp_hw_cmn_t* dev = &obj->dev;
+	otp_hw_cmn_row_t* rows = dev->rows;	
+	u32 id = 0;
+	_DPRT("control 0x%x \n",cmd->ctl);
+	if (cmd->ctl == OTP_HW_CMN_CTL_LOCK || 
+		cmd->ctl == OTP_HW_CMN_CTL_STATUS)  {
+		otp_hw_ctl_data_t* ctl_data = (otp_hw_ctl_data_t*)cmd->data;
+		/*convert: from feature to row*/
+		rc = __get_addr(obj, ctl_data->addr, &id); 
+		if (rc) {
+			_ETR(rc);
+			goto err;
+		}
+		ctl_data->addr = rows[id].addr;
+	}
+
+	rc = dev->ctl(dev, cmd, res);
+	if (rc) {
+		_ETR(rc);
+		goto err;
+	} 
+	rc = OTP_MAP_CMN_OK;
+err:
+	return rc;
+}
+
+/* fuse/write either one a feature mapped row or set of rows depending on 
+ * underlying ROW intializer   (otp_hw_cmn_row_t)  
+ * otp row mask and shift are also applied here
+ * */
+static otp_map_cmn_err_t otp_map_cmn_write(otp_map_cmn_t *obj, 
+			u32 feat, const u32* data,  u32 size)
+{
+	int i;
+	u32 range = 1, write_sz;
+	otp_hw_cmn_t* dev = &obj->dev;
+	otp_map_cmn_err_t rc = OTP_MAP_CMN_ERR_FAIL;
+	otp_hw_cmn_row_t* rows = dev->rows;
+	u32 id = 0;
+	u32 *row_data;
+	if (__get_addr(obj, feat, &id)) {
+		_ETR(rc);
+		goto err;
+	}
+	if (id >= dev->row_max || 
+			size > rows[id].range*sizeof(u32)) {
+		_ETR(OTP_MAP_CMN_ERR_INVAL);
+		return OTP_MAP_CMN_ERR_INVAL;
+	}
+	row_data = malloc(size);
+	if (!row_data) {
+		_ETR(rc);
+		goto err;
+	}
+	memcpy(row_data, data, size); 
+	if (rows[id].mask) {
+		for (i = 0; i < rows[id].range ;i++ ) {
+			row_data[i] = ((data[i]&rows[id].mask)<<rows[id].shift);
+		}
+	}
+	if (rows[id].conf.addr_type == OTP_HW_CMN_ROW_ADDR_ROW) {
+		range = rows[id].range;
+		write_sz = sizeof(u32);
+	} else {
+		range = 1;
+		write_sz = sizeof(u32)*rows[id].range;
+	}  
+	for (i = 0; i < range; i++)  {
+		_DPRT("%s:%d attempt to write: 0x%x at row 0x%x\n",__FUNCTION__,__LINE__,
+			row_data[i],(rows[id].addr+i));
+		if (dev->write(dev, rows[id].addr + i, &row_data[i], write_sz)) {
+				_ETR(rc);
+				/* Commit failed, invalidate cached data */
+				rows[id].valid = 0;
+				goto err;	
+		}
+	}
+	rc = OTP_MAP_CMN_OK;
+err:
+	free(row_data);
+	return rc;
+}
+
+/* read either a feature mapped row or set of rows depending on 
+ * underlying ROW intializer   (otp_hw_cmn_row_t)  
+ * otp row mask and shift are also applied here
+ * An objec is returned with size. Second read on the same feature will return
+ * it's  cached copy
+ * */
+static otp_map_cmn_err_t otp_map_cmn_read(otp_map_cmn_t *obj,
+			u32 feat, 
+			u32** data, u32* size)
+{
+	int i;
+	otp_map_cmn_err_t rc = OTP_MAP_CMN_ERR_FAIL;
+	otp_hw_cmn_t* dev = &obj->dev;
+	otp_hw_cmn_row_t* rows = dev->rows;	
+	u32* p;
+	u32 id = 0;
+	if (!data) {
+		rc = OTP_MAP_CMN_ERR_INVAL;
+		_ETR(rc);
+		goto err;
+	}
+	rc = __get_addr(obj, feat, &id); 
+	if (rc) {
+		_ETR(rc);
+		goto err;
+	}
+	_DPRT("%s: id:%d, range:%d, addr_type:%d, op_type:%d\n", __FUNCTION__, id, rows[id].range, rows[id].conf.addr_type, rows[id].conf.op_type);
+	p = rows[id].range > 1?
+			(u32*)(rows[id].pdata) : &rows[id].data;
+	if (!rows[id].valid) {
+		u32 range;
+		u32 read_sz;
+		if (rows[id].conf.addr_type == OTP_HW_CMN_ROW_ADDR_ROW) {
+			range = rows[id].range;
+			read_sz = sizeof(u32);
+		} else {
+			range = 1;
+			read_sz = sizeof(u32)*rows[id].range;
+		}  
+		
+		for (i = 0; i < range; i++) { 
+			rc = dev->read(dev, rows[id].addr+i, 
+				 &p[i], read_sz);
+			if (rc) {
+				_ETR(rc);
+				goto err;
+			}
+		}
+		if (rows[id].mask) {
+			for (i = 0; i < rows[id].range ;i++ ) {
+				p[i] = ((p[i] >> rows[id].shift)&rows[id].mask);
+			}
+		}
+		rows[id].valid = 1;
+	}
+
+	*data = p;
+	if (size) {
+		*size = rows[id].range*sizeof(u32);
+	}
+	rc = OTP_MAP_CMN_OK;
+err:
+	return rc;	
+}
+#if defined BCM_OTP_READ_MAP 
+static inline otp_map_cmn_err_t otp_map_cmn_read_map(otp_map_cmn_t* map)
+{
+	u32 i, size = 0, *val;
+	otp_hw_cmn_t* dev = &map->dev;
+	otp_hw_cmn_row_t* rows = dev->rows;	
+	otp_map_cmn_err_t rc = OTP_MAP_CMN_ERR_FAIL;
+	for( i = 0; i < dev->row_max; i++ ) {
+		if (!rows[i].feat) {
+			continue;
+		}
+		rc = map->read(map, rows[i].feat, 
+			&val, &size);
+		if (rc) {
+			_ETR(rc);
+		} else { 
+			_DPRT("%s:%d Got feat %d val 0x%x size 0x%x \n", __FUNCTION__,__LINE__,rows[i].feat, *val, size);
+		}
+	}
+	rc = OTP_MAP_CMN_OK;
+	return rc;
+}
+#endif
+__weak void* otp_map_cmn_malloc(size_t sz)
+{
+	return malloc(sz);
+}
+
+static inline otp_map_cmn_err_t  initialize(otp_map_cmn_t* obj)
+{
+	u32 i;
+	otp_hw_cmn_row_t* rows = obj->dev.rows;
+	otp_map_cmn_err_t rc = OTP_MAP_CMN_ERR_FAIL;
+	for (i = 0; i < obj->dev.row_max; i++ ) {
+		if (rows[i].range > 1) {
+			u8* p = otp_map_cmn_malloc(rows[i].range*sizeof(u32));
+			if (!p) {
+				_ETR(rc);
+				goto err;
+			}
+			rows[i].pdata = p;
+		}
+	}
+	rc = OTP_MAP_CMN_OK;
+err:
+	return rc;
+}
+
+ 
+otp_map_cmn_err_t otp_map_cmn_init(otp_map_cmn_t *map, 
+			otp_hw_cmn_init_t hw_init,
+			otp_hw_cmn_t* ext_drv)
+{
+	otp_map_cmn_err_t rc = OTP_MAP_CMN_ERR_FAIL;
+	if (!hw_init ) {
+		goto err;
+	} 
+	rc = hw_init(&map->dev); 
+	if (rc) {
+		if (rc == OTP_HW_CMN_ERR_UNSP) {
+			rc = OTP_MAP_CMN_ERR_UNSP;
+		}
+		_ETR(rc);
+		goto err;
+	}
+	if (ext_drv) {
+		map->dev.drv_ext = ext_drv;
+	}
+	if (initialize(map)) {
+		_ETR(rc);
+		goto err;
+	}
+	map->ctl = otp_map_cmn_ctl;
+	map->write = otp_map_cmn_write;
+	map->read = otp_map_cmn_read;
+
+#if defined BCM_OTP_READ_MAP 
+	if(otp_map_cmn_read_map(map)) {
+		_ETR(rc);
+		/*goto err;*/
+	}
+#endif
+	rc = OTP_MAP_CMN_OK;
+err:
+	return rc;
+}
diff --git a/arch/arm/mach-bcmbca/otp/sko_hw.c b/arch/arm/mach-bcmbca/otp/sko_hw.c
new file mode 100644
index 0000000000..bc3c3c6e92
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp/sko_hw.c
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2020 Broadcom Ltd.
+ */
+
+/**********************************************************************
+ *	
+ * sko_hw.c			 
+ * Includes both secure and non-secure otp operations 
+ *
+ *	
+ *********************************************************************	
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include "linux/printk.h"
+#include <asm/arch/misc.h>
+#include "otp_map_cmn.h"
+#include "sko.h"
+
+
+//#define DBG_OTP
+
+#ifdef DBG_OTP
+#define _ETR(__p__)  printf("%s \n\t\t\t\t -> %s:%d error code %d\n",__FILE__,__FUNCTION__,__LINE__,__p__)
+#define _TR(__p__)  printf("%s \n\t\t\t\t -> %s:%d  %d / 0x%x\n",__FILE__,__FUNCTION__,__LINE__,__p__,__p__)
+#define _DPRT(...)  printf(__VA_ARGS__) 
+#else
+#define _ETR(__p__)
+#define _TR(__p__)
+#define _DPRT(...)
+#endif
+/* Descriptor fields for  SKO objects 
+Row:42 SKO_0 
+		desc=0x9B009000 :(ecc which calculated at run-time) 
+			7-bit_ECC=0x46, VALID=1, Rsvd=2'b0, WLOCK=1, 
+			RLOCK=1, SEND_ECC=0, ECC_EN=1, FOUT=1, 
+			12-bit_LAST_PTR=0x9, 12-bit_FIRST_PTR=0x0
+Row 46 CRC
+*/
+/*
+ * This a debug SKO_1 if needed for the test
+Row:43 SKO_1 
+*	desc=0x9B01300A : 7-bit_ECC=0x4E, VALID=1, Rsvd=2'b0, 
+*			WLOCK=1, RLOCK=1, 
+*			SEND_ECC=0, ECC_EN=1, FOUT=1, 
+*			12-bit_LAST_PTR=0x13,12-bit_FIRST_PTR=0xA
+*
+*
+*    	{{43, 0x0, 0xffffffff, 0, 1, 0, (void*)0x8101300A}, 
+*        {56, 0x0, 0xffffffff, 0, 1, 0, (void*)0x80000000}}
+*/
+__weak u32 sko_hw_readl(void* dev, u32 offs)
+{
+	otp_hw_cmn_t* hw_dev = (otp_hw_cmn_t*)dev;
+	return readl(hw_dev->mm+offs);
+}
+
+__weak void sko_hw_writel(void* dev, u32 offs, u32 data)
+{
+	otp_hw_cmn_t* hw_dev = (otp_hw_cmn_t*)dev; 
+	_DPRT("0x%x < 0x%x\n",hw_dev->mm+offs, data);
+	writel(data, hw_dev->mm + offs);
+}
+/*
+ * locates row id
+ * */
+static otp_hw_cmn_err_t  lookup_row(otp_hw_cmn_t* dev, 
+	u32 addr,
+	otp_hw_cmn_row_t** row)
+{
+	u32 i;
+	otp_hw_cmn_row_t* rows = dev->rows;
+	for (i = 0; i < dev->row_max; i++) {
+		if (rows[i].addr == addr) {
+			*row = &rows[i];
+			return OTP_HW_CMN_OK;	
+		}
+	}
+	return OTP_HW_CMN_ERR_UNSP;
+}
+#if !defined(CONFIG_SPL_BUILD) || defined (CONFIG_BCMBCA_BOARD_TK_PROG)
+static inline u32 _bit(u32 v, u32 no) {
+		return ((v >> no)&0x1);
+}
+static inline u8 ecc7(u32 v) 
+{
+		return (u8) ((_bit(v,0)  ^ _bit(v,1)  ^ _bit(v,2)  ^ _bit(v,3)  ^ _bit(v,4)  ^ _bit(v,5)  ^ _bit(v,6)  ^ _bit(v,7)  ^ _bit(v,14) ^ _bit(v,19) ^ _bit(v,22) ^ _bit(v,24) ^ _bit(v,30) ^ _bit(v,31) ) |
+          ((_bit(v,4)  ^ _bit(v,7)  ^ _bit(v,8)  ^ _bit(v,9)  ^ _bit(v,10) ^ _bit(v,11) ^ _bit(v,12) ^ _bit(v,13) ^ _bit(v,14) ^ _bit(v,15) ^ _bit(v,18) ^ _bit(v,21) ^ _bit(v,24) ^ _bit(v,29))<<0x1) |
+          ((_bit(v,3)  ^ _bit(v,11) ^ _bit(v,16) ^ _bit(v,17) ^ _bit(v,18) ^ _bit(v,19) ^ _bit(v,20) ^ _bit(v,21) ^ _bit(v,22) ^ _bit(v,23) ^ _bit(v,26) ^ _bit(v,27) ^ _bit(v,29) ^ _bit(v,30))<<0x2) |
+          ((_bit(v,2)  ^ _bit(v,6)  ^ _bit(v,10) ^ _bit(v,13) ^ _bit(v,15) ^ _bit(v,16) ^ _bit(v,24) ^ _bit(v,25) ^ _bit(v,26) ^ _bit(v,27) ^ _bit(v,28) ^ _bit(v,29) ^ _bit(v,30) ^ _bit(v,31))<<0x3) |
+          ((_bit(v,1)  ^ _bit(v,2)  ^ _bit(v,5)  ^ _bit(v,7)  ^ _bit(v,9)  ^ _bit(v,12) ^ _bit(v,15) ^ _bit(v,20) ^ _bit(v,21) ^ _bit(v,22) ^ _bit(v,23) ^ _bit(v,25) ^ _bit(v,26) ^ _bit(v,28))<<0x4) |
+          ((_bit(v,0)  ^ _bit(v,5)  ^ _bit(v,6)  ^ _bit(v,8)  ^ _bit(v,12) ^ _bit(v,13) ^ _bit(v,14) ^ _bit(v,16) ^ _bit(v,17) ^ _bit(v,18) ^ _bit(v,19) ^ _bit(v,20) ^ _bit(v,28))<<0x5) |
+          ((_bit(v,0)  ^ _bit(v,1)  ^ _bit(v,3)  ^ _bit(v,4)  ^ _bit(v,8)  ^ _bit(v,9)  ^ _bit(v,10) ^ _bit(v,11) ^ _bit(v,17) ^ _bit(v,23) ^ _bit(v,25) ^ _bit(v,27) ^ _bit(v,31))<<0x6));
+};
+
+
+/* writes row with ecc. Calls for an external driver
+ * to do the job
+ * */
+static inline int write_row(otp_hw_cmn_t* dev, 
+		u32 addr, 
+		otp_hw_cmn_row_conf_t* row_conf,
+		u32 data)
+{
+	u32	d[2] = {data, 0};
+	u32	size = sizeof(u32);
+	if (row_conf->op_type == OTP_HW_CMN_CTL_OTPCMD_ECC) {
+		d[1] = ecc7(d[0]);
+		size *= 2;
+	}
+        _DPRT("row: %d data: 0x%x ecc: 0x%x\n", addr, d[0], d[1]);
+        return dev->drv_ext->write_ex(dev->drv_ext, 
+			addr, row_conf, (const u32*)d, size);
+}
+
+static inline u32 get_crc32(u32 v, u32 crc)
+{
+        v = ntohl(v);
+	/* uboot crc32 negates results this however implemented assuming otherwise*/
+     	if (crc == 0) {
+		crc = 0xffffffff;
+     	}
+	/* for this implementation chosen no complement crc32 as exepcted by crc calc for 
+ 	* sko object
+ 	* */
+	return  crc32_no_comp(crc, (u8*)&v, sizeof(u32));
+}
+
+/* Writes full or partial key object at once*/  
+
+static  otp_hw_cmn_err_t sko_hw_write(otp_hw_cmn_t* dev, 
+		u32 addr,
+		const u32* data,
+		u32 size)
+{
+        int i;
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	u32 *d = (u32*)data;
+	u32 crc = 0;
+        otp_hw_cmn_row_t *row, *row_ctl, *row_desc;
+	rc = lookup_row(dev, addr, &row);
+	if (rc) {
+		goto err;
+	}
+
+	u32 sko_sect = SKO_ADDR2SECT(row->addr);
+	if (sko_sect == SKO_NON_SECT) {
+		int i; 
+		if (size > (row->range*sizeof(u32)) || 
+			!dev->drv_ext->write_ex)	{
+			rc = OTP_HW_CMN_ERR_UNSP;
+			goto err;
+		}
+		for (i = 0; i < size/sizeof(u32); i++) {	
+        		rc = dev->drv_ext->write_ex(dev->drv_ext, 
+				addr+i, &row->conf, (const u32*)&d[i], sizeof(u32));
+			if (rc) {
+				goto err;
+			}
+		}
+		return rc;
+	}
+
+	rc = lookup_row(dev, row->conf.arg, &row_ctl);
+	if (rc) {
+		goto err;
+	}
+	row_desc = row_ctl + 1;
+
+        /* order is important; */
+        /* 1. Fuse a control data for the SKO */
+        rc = write_row(dev, row_ctl->addr, 
+			&row_ctl->conf, row_ctl->conf.arg); 
+	if (rc){
+            goto err;
+        }
+	
+	crc = get_crc32((u32)row_ctl->conf.arg, 0);
+        /* otp data*/
+	for (i = 0; i < row->range; i++) {
+		rc = write_row(dev, row->addr + i, 
+			&row->conf, d[i]);
+		if (rc){
+               		goto err;
+            	}
+		crc = get_crc32(d[i], crc);
+        }
+        crc = (~crc);
+	/* crc over ctl and data - fuse */
+        rc = write_row(dev, row->addr + i,
+			 &row->conf, crc);
+	if (rc) {
+		goto err;
+	}
+	_DPRT ("final crc 0x%x\n",crc);
+        /* descriptor;  must be written at last; 
+ 	*it can have config with  enabled data ecc and WR LOCK  */
+        rc = write_row(dev, row_desc->addr, 
+			&row_desc->conf, row_desc->conf.arg); 
+	if (rc) {
+		goto err; 
+	}
+	rc = OTP_HW_CMN_OK; 
+err:
+	return rc;
+}
+#else
+static  otp_hw_cmn_err_t sko_hw_write(otp_hw_cmn_t* dev, 
+		u32 addr,
+		const u32* data,
+		u32 size)
+{
+	return OTP_HW_CMN_OK; 
+}
+#endif
+
+static otp_hw_cmn_err_t sko_hw_read(otp_hw_cmn_t *dev,
+			u32 addr,
+			u32 *data,
+			u32 size)
+{
+        otp_hw_cmn_row_t *row;
+	otp_hw_cmn_err_t  rc = OTP_HW_CMN_ERR_FAIL;
+	u32 sko_sect, sko_offs; 
+	int i;
+	rc = lookup_row(dev, addr, &row);
+	if (rc) {
+		_ETR(addr);
+		goto err;
+	}
+	
+	sko_sect = SKO_ADDR2SECT(row->addr);
+	_TR(sko_sect);
+	_TR(row->addr);
+	if ( sko_sect >= SKO_SECT_MAX ) {
+		int i;	
+		if (size > row->range*sizeof(u32)) {
+			rc = OTP_HW_CMN_ERR_INVAL;
+			goto err;
+		}
+		if (sko_sect != SKO_NON_SECT ||
+			!dev->drv_ext->read ) {
+			rc = OTP_HW_CMN_ERR_UNSP;
+			_ETR(addr); 
+			goto err; 
+		}
+		for (i = 0; i <  size/sizeof(u32); i++) {	
+			rc = dev->drv_ext->read(dev->drv_ext, 
+					row->addr+i, &data[i], size);
+			if (rc) {
+				goto err;
+			}
+		}
+		return rc;
+	}
+	sko_offs = sko_sect*SKO_SIZE;
+	_DPRT("0x%x status 0x%x\n",sko, sko_hw_readl(dev, sko_hw_readl(dev, SKO_KEYN_STATUS_OFFSET + sko_offs)));
+	if ( !SKO_KEY_DATA_GOOD(sko_hw_readl(dev, SKO_KEYN_STATUS_OFFSET + sko_offs))) {
+		goto err;
+	}
+	for (i = 0; i <  size/sizeof(u32); i ++) {
+		data[i] = sko_hw_readl(dev, sko_offs + SKO_KEYN_DATA_OFFSET + i*sizeof(u32));
+		_DPRT(" 0x%x\n",  data[i]);
+	}
+	rc = OTP_HW_CMN_OK;
+err:
+	return rc;	
+}
+
+/* return status of the key object - valid or not
+ *
+ * Various PAC lock modes if selected
+ * */
+static otp_hw_cmn_err_t status(otp_hw_cmn_t *dev,
+			u32 addr,
+			otp_hw_cmn_status_t status,
+			u32* res)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_UNSP; 
+	u32 sko_sect,sko_offs; 
+        otp_hw_cmn_row_t  *row = NULL;
+	u32 perm_mask = 0;
+	if ( lookup_row(dev, addr, &row)) {
+		_ETR(addr); 
+		goto err;
+	}
+
+	sko_sect = SKO_ADDR2SECT(row->addr);
+	_DPRT("%s sect %d row %d \n",__FUNCTION__,sko_sect,row->addr); 
+	if ( sko_sect >= SKO_SECT_MAX) {
+		if (sko_sect == SKO_NON_SECT) {
+			u32 data = 0;
+			if (!(status & OTP_HW_CMN_STATUS_ROW_DATA_VALID) || 
+				!dev->drv_ext->read) {
+				_ETR(addr); 
+				goto err; 
+			}
+			rc = dev->drv_ext->read(dev->drv_ext, 
+					row->addr, &data, sizeof(u32));
+			if (rc) {
+				_ETR(addr); 
+				goto err;	
+			}
+			_TR(data);
+			if (!data) {
+				status &= ~OTP_HW_CMN_STATUS_ROW_DATA_VALID;
+			}
+			*res = status;
+			return 	OTP_HW_CMN_OK;
+		} else {
+			rc = OTP_HW_CMN_ERR_INVAL;
+			_ETR(sko_sect); 
+			goto err; 
+		}
+	}
+
+	sko_offs = sko_sect*SKO_SIZE;	
+	perm_mask = (sko_hw_readl(dev, SKO_KEYN_PAC_CTRL_OFFSET+sko_offs)&SKO_PAC_MASK);
+	
+	/*for an SKO PERM_PAC bit if set means unlocked(enabled) */
+	/* clearing bit OTP_HW_CMN_STATUS_NSRD_PAC_LOCKED if was requested*/
+	if (perm_mask & SKO_PERM_PAC_NSR_LOCK) {
+   		status &= ~OTP_HW_CMN_STATUS_NSRD_PAC_LOCKED;
+	}
+	if (perm_mask & SKO_PERM_PAC_SR_LOCK) {
+   		status &= ~OTP_HW_CMN_STATUS_SRD_PAC_LOCKED;
+	}
+	if (perm_mask & SKO_PERM_PAC_NSW_LOCK) {
+		status &= ~OTP_HW_CMN_STATUS_NSW_PAC_LOCKED;
+	}
+	if (perm_mask & SKO_PERM_PAC_SW_LOCK) {
+		status &= ~OTP_HW_CMN_STATUS_SW_PAC_LOCKED;
+	}
+	/*for an SKO PERM_KEY bit if set means locked(disabled) */
+	if (!(perm_mask & SKO_PERM_KEY_SR_LOCK)) {
+		status &= ~OTP_HW_CMN_STATUS_SRD_LOCKED;
+	}
+	if (!(perm_mask & SKO_PERM_KEY_NSR_LOCK)) {
+   		status &=  ~OTP_HW_CMN_STATUS_NSRD_LOCKED;
+	}
+	if (!(perm_mask & SKO_PERM_KEY_SW_LOCK)) {
+   		status &= ~OTP_HW_CMN_STATUS_SW_LOCKED;
+	}
+	if (!(perm_mask & SKO_PERM_KEY_NSW_LOCK)) {
+		status &= ~OTP_HW_CMN_STATUS_NSW_LOCKED;
+	}
+	if ( !SKO_KEY_DATA_GOOD(sko_hw_readl(dev, SKO_KEYN_STATUS_OFFSET+sko_offs))) {
+		status &= ~OTP_HW_CMN_STATUS_ROW_DATA_VALID;
+	}
+	*res = status;
+	rc = OTP_HW_CMN_OK;
+err:
+	return rc;
+}
+
+static otp_hw_cmn_err_t lock_all(otp_hw_cmn_t *dev)
+{
+	int i;
+	for (i = 1; i < SKO_SECT_MAX; i++) { 
+		sko_hw_writel(dev, 
+			SKO_KEYN_PAC_CTRL_OFFSET+i*SKO_SIZE, SKO_PERM_LOCK_ALL);
+	}
+	return OTP_HW_CMN_OK;
+
+}
+
+static otp_hw_cmn_err_t lock(otp_hw_cmn_t *dev,
+			u32 addr, 
+			otp_hw_cmn_perm_t perm)
+{
+
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	u32	sko_sect;
+        otp_hw_cmn_row_t  *row;
+	u32 perm_mask = 0;
+	if (perm & OTP_HW_CMN_CTL_LOCK_ALL) {
+  		return lock_all(dev);
+	}
+
+	if ( lookup_row(dev, addr, &row)) {
+		rc = OTP_HW_CMN_ERR_UNSP;
+		_ETR(rc); 
+		goto err;
+	}
+	sko_sect = SKO_ADDR2SECT(row->addr);
+	if ( sko_sect >= SKO_SECT_MAX) {
+		rc = OTP_HW_CMN_ERR_INVAL;
+		goto err;
+	}
+   	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_NSRD) {
+		SKO_PERM_PAC_LOCK_SET(perm_mask, SKO_PERM_PAC_NSR_LOCK);
+	}
+   	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_SRD) {
+		SKO_PERM_PAC_LOCK_SET(perm_mask, SKO_PERM_PAC_SR_LOCK);
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_NSW) {
+		SKO_PERM_PAC_LOCK_SET(perm_mask, SKO_PERM_PAC_NSW_LOCK);
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_SW) {
+		SKO_PERM_PAC_LOCK_SET(perm_mask, SKO_PERM_PAC_SW_LOCK);
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_SRD) {
+		SKO_PERM_KEY_LOCK_SET(perm_mask, SKO_PERM_KEY_SR_LOCK);
+	}
+   	if (perm & OTP_HW_CMN_CTL_LOCK_NSRD) {
+		SKO_PERM_KEY_LOCK_SET(perm_mask, SKO_PERM_KEY_NSR_LOCK);
+	}
+   	if (perm & OTP_HW_CMN_CTL_LOCK_SW) {
+		SKO_PERM_KEY_LOCK_SET(perm_mask, SKO_PERM_KEY_SW_LOCK);
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_NSW) {
+		SKO_PERM_KEY_LOCK_SET(perm_mask, SKO_PERM_KEY_NSW_LOCK);
+	}
+	sko_hw_writel(dev, SKO_KEYN_PAC_CTRL_OFFSET+sko_sect*SKO_SIZE, perm_mask);
+	rc = OTP_HW_CMN_OK;
+err:
+	return rc;
+
+}
+
+__weak otp_hw_cmn_err_t sotp_hw_cmn_ctl(otp_hw_cmn_t *dev, 
+			const otp_hw_cmn_ctl_cmd_t *cmd,
+			u32* res)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_UNSP;
+	switch ((u32)(cmd->ctl)) {
+   		case OTP_HW_CMN_CTL_CONF:
+			memcpy(&dev->row_conf, 
+				(otp_hw_cmn_row_conf_t*)cmd->data, 
+				cmd->size);
+
+			dev->ctl_cmd.ctl |= cmd->ctl;
+			rc = OTP_HW_CMN_OK;
+			break;
+   		case (~((u32)OTP_HW_CMN_CTL_CONF)):
+			dev->ctl_cmd.ctl &= ~cmd->ctl;
+			rc = OTP_HW_CMN_OK;
+			break;
+   		case OTP_HW_CMN_CTL_LOCK: {
+				otp_hw_ctl_data_t* ctl_data = (otp_hw_ctl_data_t*)cmd->data;	
+				rc = lock(dev, ctl_data->addr, ctl_data->perm);
+			}
+			break;
+   		case OTP_HW_CMN_CTL_STATUS: {
+				otp_hw_ctl_data_t* ctl_data = (otp_hw_ctl_data_t*)cmd->data;	
+				rc = status(dev, ctl_data->addr, ctl_data->status, res);
+			}
+			break;
+		default :
+			break;
+	}
+	return rc;
+}
+
+__weak otp_hw_cmn_err_t sotp_hw_dev_mmap(otp_hw_cmn_t* dev)
+{
+	dev->mm = SKO_BASE;
+	return OTP_HW_CMN_OK;
+}
+
+__weak otp_hw_cmn_err_t sotp_hw_init(otp_hw_cmn_t* dev)
+{
+	DEFINE_SOTP_MAP_ROW_INITLR(rows);
+	if (sotp_hw_dev_mmap(dev)) {
+		return OTP_HW_CMN_ERR_FAIL;
+	}
+	dev->rows = rows;
+	dev->row_max = sizeof(rows)/sizeof(otp_hw_cmn_row_t);
+	return OTP_HW_CMN_OK;
+}
+
+
+otp_hw_cmn_err_t sotp_hw_cmn_init(otp_hw_cmn_t* dev)
+{
+	if (sotp_hw_init(dev)) {
+		return OTP_HW_CMN_ERR_FAIL;
+	}
+	dev->read = sko_hw_read;
+	dev->write = sko_hw_write;
+	dev->ctl = sotp_hw_cmn_ctl;
+	return OTP_HW_CMN_OK;
+}
diff --git a/arch/arm/mach-bcmbca/otp/skp_hw.c b/arch/arm/mach-bcmbca/otp/skp_hw.c
new file mode 100644
index 0000000000..9e1ea044e1
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp/skp_hw.c
@@ -0,0 +1,955 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2020 Broadcom Ltd.
+ */
+/**********************************************************************
+ *	
+ * sko_hw.c			 
+ * Includes both secure and non-secure otp operations 
+ *
+ *	
+ *********************************************************************	
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include "linux/printk.h"
+#include <asm/arch/misc.h>
+#include "otp_map_cmn.h"
+#include "skp.h"
+
+//#define DBG_OTP
+
+#ifdef DBG_OTP
+#define _ETR(__p__)  printf("%s \n\t\t\t\t -> :%s :%d  code %d / 0x%x\n",__FILE__,__FUNCTION__,__LINE__,__p__,__p__)
+#define _DPRT(...)  printf(__VA_ARGS__) 
+#else
+#define _ETR(__p__)
+#define _DPRT(...)
+#endif
+
+static otp_hw_cmn_err_t  lookup_row(otp_hw_cmn_t* dev, 
+	u32 addr,
+	otp_hw_cmn_row_t** row)
+{
+	u32 i;
+	otp_hw_cmn_row_t* rows = dev->rows;
+	for (i = 0; i < dev->row_max; i++) {
+		if (rows[i].addr == addr) {
+			*row = &rows[i];
+			return OTP_HW_CMN_OK;	
+		}
+	}
+	_ETR(OTP_HW_CMN_ERR_UNSP);
+	return OTP_HW_CMN_ERR_UNSP;
+}
+
+/******************** FSR ACCESS FUNCTIONS ********************/
+__weak u32 fsr_hw_readl(void* dev, u32 offs)
+{
+	u32 val;
+	otp_hw_cmn_t* hw_dev = (otp_hw_cmn_t*)dev; 
+	val = readl(hw_dev->mm+FSR_OFFSET+offs);
+	_DPRT("0x%p > 0x%x\n",(void*)(hw_dev->mm+offs+FSR_OFFSET), val);
+	return val;
+}
+
+__weak void fsr_hw_writel(void* dev, u32 offs, u32 data)
+{
+	otp_hw_cmn_t* hw_dev = (otp_hw_cmn_t*)dev; 
+	_DPRT("0x%p < 0x%x\n",(void*)(hw_dev->mm+offs+FSR_OFFSET), data);
+	writel(data, hw_dev->mm+FSR_OFFSET+offs);
+}
+
+static  otp_hw_cmn_err_t fsr_poll_otp_status(otp_hw_cmn_t* dev, 
+						u32 fsr_offs)
+{
+	int to = 10000, errc = 0; 
+
+	do {
+		u32 st = fsr_hw_readl(dev, FSR_OTP_STATUS_OFFSET+fsr_offs);
+		_DPRT("Fsr status 0x%x\n",st);
+		if (!FSR_OTP_STATUS_ACTIVE(fsr_hw_readl(dev, FSR_OTP_STATUS_OFFSET+fsr_offs) )) {
+			break;
+		}
+		udelay(1);
+		to--;
+	} while(to);
+
+	errc = FSR_OTP_STATUS_CMD_ERROR(fsr_hw_readl(dev,FSR_OTP_STATUS_OFFSET+fsr_offs));
+	if (errc) {
+		_DPRT("%s: ERROR: otp status err 0x%x\n",
+			__FUNCTION__, fsr_hw_readl(dev, FSR_OTP_STATUS_OFFSET+fsr_offs));
+	}
+	return (!to || errc);
+}
+
+static otp_hw_cmn_err_t fsr_read(otp_hw_cmn_t* dev,
+			otp_hw_cmn_row_t  *row,
+			otp_hw_cmn_row_conf_t* row_conf,
+			u32 *data,
+			u32 size)
+{
+        int i;
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	u32 fsr_offs;
+	u32 raw_read = 0;
+	u32 desc = 0;
+
+	fsr_offs = FSR_SIZE*(row->addr-FSR_START_ROW_ADDR);
+	if (row_conf && row_conf->op_type != OTP_HW_CMN_CTL_OTPCMD_ECC) {
+		_DPRT("%s %d \n\t\t\t\t Raw read!\n",
+			__FUNCTION__,__LINE__);
+		raw_read = 1;
+	}
+
+	/* 1 - Check portal status */
+	/* Issue RELOAD_DESC command to FSR_PORTAL_FP0_OTP_COMMAND */
+	fsr_hw_writel(dev, FSR_OTP_CMD_OFFSET+fsr_offs,FSR_OTP_CMD_RELOAD_DESC);
+	/* Check cmd complete,FSR_PORTAL_FP0_OTP_STATUS active(31)=0 cmd_err(7:0)=0 */
+	if (fsr_poll_otp_status(dev, fsr_offs)) {
+		rc = OTP_HW_CMN_ERR_TMO; 
+		_ETR(rc);
+		goto err;
+	}
+
+	/* Check valid(20)==1, ready(21)==1 */
+	if (!FSR_PORTAL_VALID(fsr_hw_readl(dev, FSR_PORTAL_STATUS_OFFSET+fsr_offs))) {
+		/* Portal is empty --> return zeroed data */
+		_DPRT("%s %d \n\t\t\t\t Empty Portal! portal_status 0x%x\n",
+			__FUNCTION__,__LINE__,
+			fsr_hw_readl(dev, FSR_PORTAL_STATUS_OFFSET+fsr_offs));
+		memset(data, 0x0, size);
+		rc = OTP_HW_CMN_OK; 
+		goto err;
+	}
+
+	/* DESC status is in FSR_PORTAL_FP0_PORTAL_STATUS */
+	/* RLOCK = 1 --> Cant read */
+	if( FSR_PORTAL_RLOCK(fsr_hw_readl(dev, FSR_PORTAL_STATUS_OFFSET+fsr_offs)) ) {
+		rc = OTP_HW_CMN_ERR_FAIL; 
+		_DPRT("%s %d \n\t\t\t\t Cant Read! RLOCK is set!\n",
+			__FUNCTION__,__LINE__);
+		_ETR(rc);
+		goto err;
+	}
+
+	/* RAW and ECC_PGM_DIS = 0 --> Cant raw read */
+	if( raw_read && !FSR_PORTAL_ECC_DIS(fsr_hw_readl(dev, FSR_PORTAL_STATUS_OFFSET+fsr_offs))){
+		rc = OTP_HW_CMN_ERR_FAIL; 
+		_DPRT("%s %d \n\t\t\t\t Cant Read RAW! ECC_DIS is NOT set!\n",
+			__FUNCTION__,__LINE__);
+		_ETR(rc);
+		goto err;
+	}
+
+	/* 2 - Read Decriptor to determine portal size */
+	/* Issue READ_DESC command to FSR_PORTAL_FP0_OTP_COMMAND */
+	fsr_hw_writel(dev, FSR_OTP_CMD_OFFSET+fsr_offs,FSR_OTP_CMD_READ_DESC);
+	/* Check command complete */
+	if (fsr_poll_otp_status(dev, fsr_offs)) {
+		rc = OTP_HW_CMN_ERR_TMO; 
+		_ETR(rc);
+		goto err;
+	}
+	/* DESC is in FSR_PORTAL_FP0_DATA */
+	/* Check valid(31)==1 , this should succeed as PORTAL status is good*/
+	desc = fsr_hw_readl(dev, FSR_DATA_OFFSET+fsr_offs);
+	if(!FSR_RD_DGOOD(desc)) {
+		_ETR(rc);
+		_DPRT("%s %d \n\t\t\t\t desc 0x%x\n",
+			__FUNCTION__,__LINE__,
+			fsr_hw_readl(dev, FSR_DATA_OFFSET+fsr_offs));
+		rc = OTP_HW_CMN_ERR_FAIL; 
+		goto err;
+	}
+	/* Check if requested data fits inside this FSR, check SIZE(23:12) */
+	if(size/sizeof(u32) > FSR_RD_DDATA_SIZE(desc)) {
+		_ETR(rc);
+		_DPRT("%s %d \n\t\t\t\t size 0x%x > 0x%0x\n",
+			__FUNCTION__,__LINE__, size/sizeof(u32), FSR_RD_DDATA_SIZE(desc));
+		rc =  OTP_HW_CMN_ERR_BAD_PARAM; 
+		goto err;
+	}
+
+	/* 3 - Read data */
+	for (i = 0; i < size/sizeof(u32); i++ ) {
+		/* Issue READ_DATA command - Set WORD SEL(15:4) to pick word# */
+		fsr_hw_writel(dev, FSR_OTP_CMD_OFFSET+fsr_offs,
+			(i<<FSR_PORTAL_OTP_CMD_WORD_SEL_SHIFT)|FSR_OTP_CMD_READ_DATA);
+		/* Check command complete */
+		if (fsr_poll_otp_status(dev, fsr_offs)) {
+			rc = OTP_HW_CMN_ERR_TMO; 
+			_ETR(rc);
+			goto err;
+		}
+
+		/* Read data from FSR_PORTAL_FP0_DATA */
+		data[i] = fsr_hw_readl(dev, FSR_DATA_OFFSET+fsr_offs);
+		_DPRT("%s %d \n\t\t\t\t read data[%d] 0x%x \n",
+			__FUNCTION__,__LINE__, i, data[i]);
+
+		/* Optional - Read ECC from FSR_PORTAL_FP0_RD_ECC */
+	}
+	rc = OTP_HW_CMN_OK;
+err:
+	return rc;
+}
+
+static otp_hw_cmn_err_t fsr_write(otp_hw_cmn_t* dev,
+			otp_hw_cmn_row_t  *row,
+			otp_hw_cmn_row_conf_t* row_conf,
+			u32 *data,
+			u32 size)
+{
+        int i;
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	u32 fsr_offs; 
+	otp_hw_cmn_ctl_cmd_t ctl = {.ctl = OTP_HW_CMN_CTL_OTPCMD_AUTH_PROG};
+	u32 res = 0;
+	u32 raw_write = 0;
+	u32 desc = 0;
+	otp_hw_cmn_t *ext_drv = dev->drv_ext;
+
+	fsr_offs = FSR_SIZE*(row->addr-FSR_START_ROW_ADDR);
+	if (row_conf && row_conf->op_type != OTP_HW_CMN_CTL_OTPCMD_ECC) {
+		_DPRT("%s %d \n\t\t\t\t Raw write!\n",
+			__FUNCTION__,__LINE__);
+		raw_write = 1;
+	}
+
+	/* 1 - Place OTP in program mode */
+	rc = ext_drv->ctl(ext_drv, &ctl, &res);
+	if (rc) {
+		_ETR(rc);
+		goto err;
+	}
+	ctl.ctl = OTP_HW_CMN_CTL_OTPCMD_AUTH_PROG_DONE;
+	rc = ext_drv->ctl(ext_drv, &ctl, &res);
+	if (rc) {
+		_ETR(rc);
+		goto err;
+	}
+
+	/* 2 - Check portal status */
+	/* Issue RELOAD_DESC command to FSR_PORTAL_FP0_OTP_COMMAND */
+	fsr_hw_writel(dev, FSR_OTP_CMD_OFFSET+fsr_offs,FSR_OTP_CMD_RELOAD_DESC);
+	/* Check cmd complete,FSR_PORTAL_FP0_OTP_STATUS active(31)=0 cmd_err(7:0)=0 */
+	if (fsr_poll_otp_status(dev, fsr_offs)) {
+		rc = OTP_HW_CMN_ERR_TMO; 
+		_ETR(rc);
+		goto err;
+	}
+
+	/* Check valid(20)==1, ready(21)==1*/
+	if (!FSR_PORTAL_VALID(fsr_hw_readl(dev, FSR_PORTAL_STATUS_OFFSET+fsr_offs))) {
+		/* If Portal DESC is not valid ---> empty!, program it */
+		/* Set VALID = 1 and RLOCK = 0 */
+		desc = FSR_RD_DESC_VALID_MASK<<FSR_RD_DESC_VALID_SHIFT;
+
+		/* If RAW, set ECC_PGM_DIS */
+		if( raw_write )
+			desc |= FSR_RD_DESC_ECC_PGM_DIS_MASK<<FSR_RD_DESC_ECC_PGM_DIS_SHIFT;
+
+		/* A - Write descriptor to FSR_PORTAL_FP0_DATA */
+		fsr_hw_writel(dev, FSR_DATA_OFFSET+fsr_offs,desc);
+
+		/* B - Issue PGM_DESC command to FSR_PORTAL_FP0_OTP_COMMAND */
+		fsr_hw_writel(dev, FSR_OTP_CMD_OFFSET+fsr_offs,FSR_OTP_CMD_PGM_DESC);
+		/* Check cmd complete,FSR_PORTAL_FP0_OTP_STATUS active(31)=0 cmd_err(7:0)=0 */
+		if (fsr_poll_otp_status(dev, fsr_offs)) {
+			rc = OTP_HW_CMN_ERR_TMO; 
+			_ETR(rc);
+			goto err;
+		}
+
+		/* C - Issue PGM_DESC_ECC command to FSR_PORTAL_FP0_OTP_COMMAND */
+		fsr_hw_writel(dev, FSR_OTP_CMD_OFFSET+fsr_offs,FSR_OTP_CMD_PGM_DESC_ECC);
+		/* Check cmd complete,FSR_PORTAL_FP0_OTP_STATUS active(31)=0 cmd_err(7:0)=0 */
+		if (fsr_poll_otp_status(dev, fsr_offs)) {
+			rc = OTP_HW_CMN_ERR_TMO; 
+			_ETR(rc);
+			goto err;
+		}
+
+		/* D - Issue RELOAD_DESC command to FSR_PORTAL_FP0_OTP_COMMAND */
+		fsr_hw_writel(dev, FSR_OTP_CMD_OFFSET+fsr_offs,FSR_OTP_CMD_RELOAD_DESC);
+		/* Check cmd complete,FSR_PORTAL_FP0_OTP_STATUS active(31)=0 cmd_err(7:0)=0 */
+		if (fsr_poll_otp_status(dev, fsr_offs)) {
+			rc = OTP_HW_CMN_ERR_TMO; 
+			_ETR(rc);
+			goto err;
+		}
+	} else {
+		/* Valid PORTAL and DESC */
+		/* DESC status is in FSR_PORTAL_FP0_PORTAL_STATUS */
+		/* RLOCK = 1 --> Cant write */
+		if( FSR_PORTAL_RLOCK(fsr_hw_readl(dev, FSR_PORTAL_STATUS_OFFSET+fsr_offs)) ) {
+			rc = OTP_HW_CMN_ERR_WRITE_FAIL; 
+			_DPRT("%s %d \n\t\t\t\t Cant Write! RLOCK is set!\n",
+				__FUNCTION__,__LINE__);
+			_ETR(rc);
+			goto err;
+		}
+
+		/* RAW and ECC_PGM_DIS = 0 --> Cant raw write */
+		if( raw_write && !FSR_PORTAL_ECC_DIS(fsr_hw_readl(dev, 
+				FSR_PORTAL_STATUS_OFFSET+fsr_offs))) {
+			rc = OTP_HW_CMN_ERR_WRITE_FAIL; 
+			_DPRT("%s %d \n\t\t\t\t Cant Write RAW! ECC_DIS is NOT set!\n",
+				__FUNCTION__,__LINE__);
+			_ETR(rc);
+			goto err;
+		}
+
+		/* NOT RAW and ECC_PGM_DIS = 1 --> Cant non-raw write without ECC */
+		if( !raw_write && FSR_PORTAL_ECC_DIS(fsr_hw_readl(dev, 
+				FSR_PORTAL_STATUS_OFFSET+fsr_offs))) {
+			rc = OTP_HW_CMN_ERR_WRITE_FAIL; 
+			_DPRT("%s %d \n\t\t\t\t Cant Write Non-raw! ECC_DIS is set!\n",
+				__FUNCTION__,__LINE__);
+			_ETR(rc);
+			goto err;
+		}
+	}
+
+
+	/* 3 - Read Decriptor to determine portal size */
+	/* Issue READ_DESC command to FSR_PORTAL_FP0_OTP_COMMAND */
+	fsr_hw_writel(dev, FSR_OTP_CMD_OFFSET+fsr_offs,FSR_OTP_CMD_READ_DESC);
+	/* Check command complete */
+	if (fsr_poll_otp_status(dev, fsr_offs)) {
+		rc = OTP_HW_CMN_ERR_TMO; 
+		_ETR(rc);
+		goto err;
+	}
+	/* Read and check if descriptor is valid(31) */
+	desc = fsr_hw_readl(dev, FSR_DATA_OFFSET+fsr_offs);
+	if(!FSR_RD_DGOOD(desc)) {
+		_ETR(rc);
+		_DPRT("%s %d \n\t\t\t\t desc 0x%x\n",
+			__FUNCTION__,__LINE__,
+			fsr_hw_readl(dev, FSR_DATA_OFFSET+fsr_offs));
+		rc = OTP_HW_CMN_ERR_FAIL; 
+		goto err;
+	}
+	/* Check if requested data fits inside this FSR, check SIZE(23:12) */
+	if(size/sizeof(u32) > FSR_RD_DDATA_SIZE(desc)) {
+		_ETR(rc);
+		_DPRT("%s %d \n\t\t\t\t size 0x%x > 0x%0x\n",
+			__FUNCTION__,__LINE__, size/sizeof(u32), FSR_RD_DDATA_SIZE(desc));
+		rc =  OTP_HW_CMN_ERR_BAD_PARAM; 
+		goto err;
+	}
+	/* If not a raw_write, check if portal has been written to */
+	if( !raw_write ) {
+		for (i = 0; i < size/sizeof(u32); i++ ) {
+			/* Issue READ_DATA command - Set WORD SEL(15:4) to pick word# */
+			fsr_hw_writel(dev, FSR_OTP_CMD_OFFSET+fsr_offs,
+				(i<<FSR_PORTAL_OTP_CMD_WORD_SEL_SHIFT)|FSR_OTP_CMD_READ_DATA);
+			/* Check command complete */
+			if (fsr_poll_otp_status(dev, fsr_offs)) {
+				rc = OTP_HW_CMN_ERR_TMO; 
+				_ETR(rc);
+				goto err;
+			}
+
+			/* Read ECC from FSR_PORTAL_FP0_RD_ECC */
+			if(fsr_hw_readl(dev,FSR_RD_ECC_OFFSET+fsr_offs) & FSR_PORTAL_RD_ECC_MASK) {
+				rc = OTP_HW_CMN_ERR_WRITE_FAIL; 
+				_DPRT("%s %d \n\t\t\t\t Cannot overwrite portal! ECC is set!\n",
+					__FUNCTION__,__LINE__);
+				_ETR(rc);
+				goto err;
+			}
+		}
+	}
+
+	/* 4 - Write data and ECC ( if reqd ) */
+	for (i = 0; i < size/sizeof(u32); i++ ) {
+		/* Read data from FSR_PORTAL_FP0_DATA */
+		_DPRT("%s %d \n\t\t\t\t write data[%d] 0x%x \n",
+			__FUNCTION__,__LINE__, i, data[i]);
+
+		fsr_hw_writel(dev, FSR_DATA_OFFSET+fsr_offs, data[i]);
+
+		/* Issue WRITE_DATA command - Set WORD SEL(15:4) to pick word# */
+		fsr_hw_writel(dev, FSR_OTP_CMD_OFFSET+fsr_offs,
+			(i<<FSR_PORTAL_OTP_CMD_WORD_SEL_SHIFT)|FSR_OTP_CMD_PGM_DATA);
+		/* Check command complete */
+		if (fsr_poll_otp_status(dev, fsr_offs)) {
+			rc = OTP_HW_CMN_ERR_TMO; 
+			_ETR(rc);
+			goto err;
+		}
+
+		if( !raw_write ) {		
+			/* Issue WRITE_ECC command - Set WORD SEL(15:4) to pick word# */
+			fsr_hw_writel(dev, FSR_OTP_CMD_OFFSET+fsr_offs,
+				(i<<FSR_PORTAL_OTP_CMD_WORD_SEL_SHIFT)|FSR_OTP_CMD_PGM_DATA_ECC);
+			/* Check command complete */
+			if (fsr_poll_otp_status(dev, fsr_offs)) {
+				rc = OTP_HW_CMN_ERR_TMO; 
+				_ETR(rc);
+				goto err;
+			}
+		}
+	}
+	
+	_DPRT("Fused FSR rows as expected \n");
+       	rc = OTP_HW_CMN_OK; 
+err:
+        return rc;
+}
+
+/******************** KSR ACCESS FUNCTIONS ********************/
+__weak u32 ksr_hw_readl(void* dev, u32 offs)
+{
+	otp_hw_cmn_t* hw_dev = (otp_hw_cmn_t*)dev; 
+	return readl(hw_dev->mm+KSR_OFFSET+offs);
+}
+
+__weak void ksr_hw_writel(void* dev, u32 offs, u32 data)
+{
+	otp_hw_cmn_t* hw_dev = (otp_hw_cmn_t*)dev; 
+	_DPRT("0x%x < 0x%x\n",hw_dev->mm+offs, data);
+	writel(data, hw_dev->mm+KSR_OFFSET+offs);
+}
+
+static  otp_hw_cmn_err_t ksr_poll_otp_status(otp_hw_cmn_t* dev, 
+						u32 ksr_offs)
+{
+	int to = 10000, errc = 0; 
+
+	do {
+		u32 st = ksr_hw_readl(dev, KSR_OTP_STATUS_OFFSET+ksr_offs);
+		_DPRT("Ksr status 0x%x\n",st);
+		if (!KSR_OTP_STATUS_ACTIVE(ksr_hw_readl(dev, KSR_OTP_STATUS_OFFSET+ksr_offs) )) {
+			break;
+		}
+		udelay(1);
+		to--;
+	} while(to);
+
+	errc = KSR_OTP_STATUS_CMD_ERROR(ksr_hw_readl(dev,KSR_OTP_STATUS_OFFSET+ksr_offs));
+	if (errc) {
+		printf("%s: ERROR: otp status err 0x%x\n",
+			__FUNCTION__, ksr_hw_readl(dev, KSR_OTP_STATUS_OFFSET+ksr_offs));
+	}
+	return (!to || errc);
+}
+
+static otp_hw_cmn_err_t ksr_read(otp_hw_cmn_t* dev,
+			otp_hw_cmn_row_t  *row,
+			otp_hw_cmn_row_conf_t* row_conf,
+			u32 *data,
+			u32 size)
+{
+        int i;
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	u32 ksr_offs;
+	ksr_offs = KSR_SIZE*(row->addr-KSR_START_ROW_ADDR);
+	if ( !KSR_PORTAL_VALID(ksr_hw_readl(dev, KSR_PORTAL_STATUS_OFFSET+ksr_offs)) ||
+		!KSR_RD_DGOOD(ksr_hw_readl(dev, KSR_RD_DESC_OFFSET+ksr_offs))) {
+		_ETR(rc);
+		_DPRT("%s %d \n\t\t\t\t portal_status 0x%x rd_desc 0x%x\n",
+			__FUNCTION__,__LINE__,ksr_hw_readl(dev, KSR_PORTAL_STATUS_OFFSET+ksr_offs), ksr_hw_readl(dev, KSR_RD_DESC_OFFSET+ksr_offs));
+		rc = OTP_HW_CMN_ERR_KEY_EMPTY; 
+		goto err;
+	}
+	for (i = 0; i <  size/sizeof(u32); i++ ) {
+		data[i] = ksr_hw_readl(dev, KSR_DATA_OFFSET+i*sizeof(u32)+ksr_offs);
+		_DPRT("%s %d \n\t\t\t\t data[%d] 0x%x \n",
+			__FUNCTION__,__LINE__, i, data[i]);
+	}
+	rc = OTP_HW_CMN_OK;
+err:
+	return rc;
+
+}
+
+static otp_hw_cmn_err_t ksr_write(otp_hw_cmn_t* dev,
+			otp_hw_cmn_row_t  *row,
+			otp_hw_cmn_row_conf_t* row_conf,
+			u32 *data,
+			u32 size)
+{
+        int i;
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	u32 ksr_offs; 
+	otp_hw_cmn_ctl_cmd_t ctl = {.ctl = OTP_HW_CMN_CTL_OTPCMD_AUTH_PROG};
+	u32 res = 0;
+	otp_hw_cmn_t *ext_drv = dev->drv_ext;
+	ksr_offs = KSR_SIZE*(row->addr-KSR_START_ROW_ADDR);
+	
+/*
+	1) Set OTP in program mode using classic CPU access as mentioned in Sec3.
+	2) Write bit[31] (valid) to “1” and bit[7:0] PAC fields as required (refer RDB for definition) into KEY_PORTAL_KP0_PGM_DESCRIPTOR
+	3) Issue PGM_DESCRIPTOR_WORD command, write bit[3:0] CMD field to “0x8”  in KEY_PORTAL_KP0_OTP_COMMAND, 
+		this command programs into the OTP Macro one 32-bit Descriptor word. The data to be written comes from the KP_PGM_DESCRIPTOR register.
+	4) Wait/Check for command_active to be low which indicates that the command issued is completed. 
+		Poll for the register bit “command_active(bit [31])” in KEY_PORTAL_KP0_OTP_STATUS. 
+		Once command is completed. Check for the bits[7:0] CMD_ERR (refer RDB for definition of the bits).
+	5) Issue PGM_DESCRIPTOR_ECC command, write bit[3:0] CMD field to “0x9”  in KEY_PORTAL_KP0_OTP_COMMAND, 
+		this command programs into the OTP Macro just the 10 ECC bits for the Descriptor row, 
+		which the OTP Controller automatically calculates based on the OTP data already programmed in this row.
+	6) Wait/Check for command_active to be low which indicates that the command issued is completed. 
+		Poll for the register bit “command_active(bit [31])” in KEY_PORTAL_KP0_OTP_STATUS.
+		Once command is completed. Check for the bits[7:0] CMD_ERR (refer RDB for definition of the bits).
+	7) Write all the 8 Keys into KEY_PORTAL_KP0_DATA_0, KEY_PORTAL_KP0_DATA_1, KEY_PORTAL_KP0_DATA_2, KEY_PORTAL_KP0_DATA_3, 
+		KEY_PORTAL_KP0_DATA_4, KEY_PORTAL_KP0_DATA_5, KEY_PORTAL_KP0_DATA_6, KEY_PORTAL_KP0_DATA_7 respectively.
+	8) Issue PGM_KEY command, write bit[3:0] CMD field to “0x2”  in KEY_PORTAL_KP0_OTP_COMMAND, 
+		this command programs (in the OTP Array) the entire key (including the CRC value) for this Key Portal. 
+		The hardware internally calculates the CRC value for the key and programs it into the CRC OTP field for this key.
+	9) Wait/Check for command_active to be low which indicates that the command issued is completed. 
+		Poll for the register bit “command_active(bit [31])” in KEY_PORTAL_KP0_OTP_STATUS. 
+		Once command is completed. Check for the bits[7:0] CMD_ERR (refer RDB for definition of the bits).
+	10) Issue chip reset.
+ 
+4.3 KSR PORTAL CPU READ ACCESS:
+
+KSR sectioned region thru portal can be accessed only in secure-boot mode, i.e. bit 2 in Row13 and bit 28 in Row 14 should be “1”.
+
+All 6 Key portals can be accessed in any order. Below sequence is explained by considering Key portal0 as an example same applies for other 5 Key portals as well.
+
+	1) Upon chip reboot, design loads the KSR descriptor, checks for its validity, 
+		and loads the keys into the registers once they are good.
+	2) Read KEY_PORTAL_KP0_RD_DESCRIPTOR, check for bit[29] DGOOD, this should be “1” which indicates descriptor 
+			validity checks passed and the also all 8 Keys are good with no CRC/ECC errors. 
+		a. If DGOOD is “0”, all 8 keys read in Step(3) will be zeroes, KEY_PORTAL_KP0_PORTAL_STATUS 
+			register will have more status info bits like Descriptor validity, Desc ECC error, Data ECC error, Keys loaded (Refer RDB).
+	3) Read KEY_PORTAL_KP0_PAC register, this register initially gets loaded with the PAC values 
+			from OTP but later can also be programmed, based on the PAC permissions Key portal registers can be accessed. Please refer RDB for more information. 
+	4) Read all the 8 Keys which are loaded in KEY_PORTAL_KP0_DATA_0, KEY_PORTAL_KP0_DATA_1, KEY_PORTAL_KP0_DATA_2, KEY_PORTAL_KP0_DATA_3, KEY_PORTAL_KP0_DATA_4, KEY_PORTAL_KP0_DATA_5, KEY_PORTAL_KP0_DATA_6, KEY_PORTAL_KP0_DATA_7 respectively.
+
+*/
+	rc = ext_drv->ctl(ext_drv, &ctl, &res);
+	if (rc) {
+		_ETR(rc);
+		goto err;
+	}
+
+	ctl.ctl = OTP_HW_CMN_CTL_OTPCMD_AUTH_PROG_DONE;
+	rc = ext_drv->ctl(ext_drv, &ctl, &res);
+	if (rc) {
+		_ETR(rc);
+		goto err;
+	}
+
+	_ETR((u32)row_conf->perm);
+	_ETR(KSR_PORTAL_PGM_DESC_SRW_PERM);
+	if (ksr_poll_otp_status(dev, ksr_offs)) {
+		rc = OTP_HW_CMN_ERR_TMO; 
+		_ETR(rc);
+		goto err;
+	}
+	ksr_hw_writel(dev, KSR_PGM_DESC_OFFSET + ksr_offs, (u32)row_conf->perm);
+	_ETR(ksr_hw_readl(dev, KSR_PGM_DESC_OFFSET+ksr_offs));
+	ksr_hw_writel(dev, KSR_OTP_CMD_OFFSET + ksr_offs, KSR_PORTAL_OTP_CMD_PGM_DESC_WORD);
+	if (ksr_poll_otp_status(dev, ksr_offs)) {
+		rc = OTP_HW_CMN_ERR_TMO; 
+		_ETR(rc);
+		goto err;
+	}
+	_ETR(KSR_PORTAL_OTP_CMD_PGM_DESC_WORD);
+	if ((row_conf->op_type&OTP_HW_CMN_CTL_OTPCMD_ECC)) {
+		ksr_hw_writel(dev, KSR_OTP_CMD_OFFSET+ksr_offs,KSR_PORTAL_OTP_CMD_PGM_DESC_ECC);
+		if (ksr_poll_otp_status(dev,ksr_offs)) {
+			rc = OTP_HW_CMN_ERR_TMO; 
+			_ETR(rc);
+			goto err;
+		}
+		_ETR(KSR_PORTAL_OTP_CMD_PGM_DESC_ECC);
+	}
+	for (i = 0 ; i <  size/sizeof(u32); i++) {
+		ksr_hw_writel(dev, KSR_DATA_OFFSET+ksr_offs+i*sizeof(u32), data[i]);
+	}
+	ksr_hw_writel(dev, KSR_OTP_CMD_OFFSET + ksr_offs, KSR_PORTAL_OTP_CMD_PGM_KEY);
+	_ETR(ksr_hw_readl(dev, KSR_OTP_CMD_OFFSET+ksr_offs));
+	if (ksr_poll_otp_status(dev, ksr_offs)) {
+		rc = OTP_HW_CMN_ERR_TMO;
+		_ETR(rc);
+		goto err;
+	}
+	
+	_DPRT("Fused KSR rows as expected \n");
+       	rc = OTP_HW_CMN_OK; 
+err:
+        return rc;
+}
+
+static otp_hw_cmn_err_t ksr_set_populated_pacs(otp_hw_cmn_t *dev, u32 pac_val)
+{
+	int i;
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	/* First 2 KSR Portals have their PACS fused via their descriptors -- ignore */
+	for (i = 2; i < KSR_MAX_ROW_ADDR; i++) { 
+		/* If portal is valid and descriptor is good, we have valid data so lock NS */
+		if ( KSR_PORTAL_VALID(ksr_hw_readl(dev, KSR_PORTAL_STATUS_OFFSET+i*KSR_SIZE)) &&
+			KSR_RD_DGOOD(ksr_hw_readl(dev, KSR_RD_DESC_OFFSET+i*KSR_SIZE))) {
+				ksr_hw_writel(dev, KSR_PAC_OFFSET+i*KSR_SIZE, pac_val);
+		}
+	}
+	rc = OTP_HW_CMN_OK;
+	return rc;
+}
+
+static otp_hw_cmn_err_t ksr_set_all_pacs(otp_hw_cmn_t *dev, u32 pac_val)
+{
+	int i;
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	/* First 2 KSR Portals have their PACS fused via their descriptors -- ignore */
+	for (i = 2; i < KSR_MAX_ROW_ADDR; i++) { 
+		ksr_hw_writel(dev, KSR_PAC_OFFSET+i*KSR_SIZE, pac_val);
+	}
+	rc = OTP_HW_CMN_OK;
+	return rc;
+
+}
+
+static otp_hw_cmn_err_t ksr_portal_lock(otp_hw_cmn_t *dev,
+			u32 addr, 
+			otp_hw_cmn_perm_t perm,
+			u8 lock)
+{
+	otp_hw_cmn_row_t  *row;
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	u32 curr_perm_mask = 0;
+	u32 perm_mask = 0;
+	if ( lookup_row(dev, addr, &row)) {
+		rc = OTP_HW_CMN_ERR_UNSP;
+		_ETR(rc); 
+		goto err;
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_NSRD) {
+		perm_mask |= KSR_PERM_PAC_NSR_LOCK;
+	}
+   	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_SRD) {
+		perm_mask |= KSR_PERM_PAC_SR_LOCK;
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_NSW) {
+		perm_mask |= KSR_PERM_PAC_NSW_LOCK;
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_SW) {
+		perm_mask |= KSR_PERM_PAC_SW_LOCK;
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_SRD) {
+		perm_mask |= KSR_PERM_BLK_SR_LOCK;
+	}
+   	if (perm & OTP_HW_CMN_CTL_LOCK_NSRD) {
+		perm_mask |= KSR_PERM_BLK_NSR_LOCK;
+	}
+   	if (perm & OTP_HW_CMN_CTL_LOCK_SW) {
+		perm_mask |= KSR_PERM_BLK_SW_LOCK;
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_NSW) {
+		perm_mask |= KSR_PERM_BLK_NSW_LOCK;
+	}
+	if (perm_mask) {
+		curr_perm_mask = ksr_hw_readl(dev, KSR_PAC_OFFSET + row->addr*KSR_SIZE);
+		if( lock ) {
+			ksr_hw_writel(dev, KSR_PAC_OFFSET + row->addr*KSR_SIZE, 
+				curr_perm_mask|perm_mask);
+		} else {
+			ksr_hw_writel(dev, KSR_PAC_OFFSET + row->addr*KSR_SIZE, 
+				curr_perm_mask&(~perm_mask));
+		}
+
+		rc = OTP_HW_CMN_OK;
+	}
+err:
+	return rc;
+}
+
+static otp_hw_cmn_err_t ksr_multi_portal_lock(otp_hw_cmn_t *dev,
+			otp_hw_cmn_perm_t perm,
+			u8 lock)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	if( lock ) {
+		if (perm & OTP_HW_CMN_CTL_LOCK_NS) {
+	  		rc = ksr_set_all_pacs(dev, KSR_PERM_LOCK_NS);
+		} else if (perm & OTP_HW_CMN_CTL_LOCK_ALL) {
+	  		rc = ksr_set_all_pacs(dev, KSR_PERM_LOCK_ALL);
+		} else if (perm & OTP_HW_CMN_CTL_LOCK_S) {
+	  		rc = ksr_set_all_pacs(dev, KSR_PERM_LOCK_S);
+		} 
+	} else {
+		if (perm & OTP_HW_CMN_CTL_LOCK_NS || perm & OTP_HW_CMN_CTL_LOCK_NS_PROV ) {
+	  		rc = ksr_set_all_pacs(dev, KSR_PERM_UNLOCK_NS);
+			if( perm & OTP_HW_CMN_CTL_LOCK_NS_PROV) {
+				/* LOCK NS access for keys that are populated */
+				rc = ksr_set_populated_pacs(dev, KSR_PERM_LOCK_NS);
+			}
+		} else if (perm & OTP_HW_CMN_CTL_LOCK_S) {
+	  		rc = ksr_set_all_pacs(dev, KSR_PERM_UNLOCK_S);
+		} else if (perm & OTP_HW_CMN_CTL_LOCK_ALL) {
+	  		rc = ksr_set_all_pacs(dev, KSR_PERM_UNLOCK_ALL);
+		} 
+	}
+	return rc;
+}
+
+static otp_hw_cmn_err_t ksr_portal_status(otp_hw_cmn_t *dev,
+			u32 addr,
+			otp_hw_cmn_status_t status,
+			u32* res)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	u32 perm_mask = 0,ksr_offs;
+        otp_hw_cmn_row_t  *row = NULL;
+
+	if ( lookup_row(dev, addr, &row)) {
+		rc = OTP_HW_CMN_ERR_UNSP;
+		_ETR(rc); 
+		goto err;
+	} 
+
+	ksr_offs = KSR_SIZE*(row->addr-KSR_START_ROW_ADDR);
+	perm_mask = ksr_hw_readl(dev, KSR_PAC_OFFSET+ksr_offs);
+	
+	if (!(perm_mask & KSR_PERM_PAC_NSR_LOCK)) {
+   		status &= ~OTP_HW_CMN_STATUS_NSRD_PAC_LOCKED;
+	}
+	if (!(perm_mask & KSR_PERM_PAC_SR_LOCK)) {
+   		status &= ~OTP_HW_CMN_STATUS_SRD_PAC_LOCKED;
+	}
+	if (!(perm_mask & KSR_PERM_PAC_NSW_LOCK)) {
+		status &= ~OTP_HW_CMN_STATUS_NSW_PAC_LOCKED;
+	}
+	if (!(perm_mask & KSR_PERM_PAC_SW_LOCK)) {
+		status &= ~OTP_HW_CMN_STATUS_SW_PAC_LOCKED;
+	}
+	if (!(perm_mask & KSR_PERM_BLK_SR_LOCK)) {
+		status &= ~OTP_HW_CMN_STATUS_SRD_LOCKED;
+	}
+	if (!(perm_mask & KSR_PERM_BLK_NSR_LOCK)) {
+   		status &=  ~OTP_HW_CMN_STATUS_NSRD_LOCKED;
+	}
+	if (!(perm_mask & KSR_PERM_BLK_SW_LOCK)) {
+   		status &= ~OTP_HW_CMN_STATUS_SW_LOCKED;
+	}
+	if (!(perm_mask & KSR_PERM_BLK_NSW_LOCK)) {
+		status &= ~OTP_HW_CMN_STATUS_NSW_LOCKED;
+	}
+	if ( !KSR_PORTAL_VALID(ksr_hw_readl(dev, KSR_PORTAL_STATUS_OFFSET+ksr_offs)) ||
+		!KSR_RD_DGOOD(ksr_hw_readl(dev, KSR_RD_DESC_OFFSET+ksr_offs))) {
+		status &= ~OTP_HW_CMN_STATUS_ROW_DATA_VALID;
+	}
+	*res = status;
+	rc = OTP_HW_CMN_OK;
+err:
+	return rc;
+}
+
+
+/******************** SKP ACCESS FUNCTIONS ********************/
+static  otp_hw_cmn_err_t skp_write(otp_hw_cmn_t* dev, 
+		u32 addr,
+		otp_hw_cmn_row_conf_t* conf,
+		const u32* data,
+		u32 size)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+        otp_hw_cmn_row_t *row;
+	otp_hw_cmn_row_conf_t* row_conf;
+	if (!dev->drv_ext) {
+		rc = OTP_HW_CMN_ERR_INVAL;
+		_ETR(rc);
+		goto err;
+	}
+	if (lookup_row(dev, addr, &row)) {
+		rc = OTP_HW_CMN_ERR_UNSP;
+		_ETR(rc);
+		goto err;
+	}
+
+	if ((int)size <= 0 || (int)size > row->range*sizeof(u32) || (int)row->addr < 0) {
+		rc = OTP_HW_CMN_ERR_INVAL; 
+		_ETR(rc);
+		goto err;
+	}
+
+	row_conf = conf?conf:&row->conf;
+	if( (int)row->addr < KSR_MAX_ROW_ADDR ) {
+		rc = ksr_write( dev, row, row_conf, (u32*)data, size );
+	} else if(((int)row->addr >=FSR_START_ROW_ADDR) && ((int)row->addr < FSR_MAX_ROW_ADDR)) {
+		rc = fsr_write( dev, row, row_conf, (u32*)data, size );
+	} else {
+		rc = OTP_HW_CMN_ERR_INVAL; 
+		_ETR(rc);
+	}
+err:
+	_DPRT("%s: rc %d\n", __FUNCTION__, rc);
+	return rc;
+
+}
+
+static otp_hw_cmn_err_t skp_read(otp_hw_cmn_t *dev,
+			u32 addr,
+			otp_hw_cmn_row_conf_t* conf,
+			u32 *data,
+			u32 size)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+        otp_hw_cmn_row_t  *row;
+	otp_hw_cmn_row_conf_t* row_conf;
+	if (!dev->drv_ext) {
+		rc = OTP_HW_CMN_ERR_INVAL; 
+		_ETR(rc);
+		goto err;
+	}
+	if( lookup_row(dev, addr, &row)) {
+		rc = OTP_HW_CMN_ERR_UNSP;
+		_ETR(rc); 
+		goto err;
+	}
+	if ((int)size <= 0 || (int)size > row->range*sizeof(u32) || (int)row->addr < 0) {
+		rc = OTP_HW_CMN_ERR_INVAL; 
+		_ETR(rc);
+		goto err;
+	}
+
+	row_conf = conf? conf : &row->conf;
+	if( (int)row->addr < KSR_MAX_ROW_ADDR ) {
+		rc = ksr_read( dev, row, row_conf, (u32*)data, size );
+	} else if(((int)row->addr >=FSR_START_ROW_ADDR) && ((int)row->addr < FSR_MAX_ROW_ADDR)) {
+		rc = fsr_read( dev, row, row_conf, (u32*)data, size );
+	} else {
+		rc = OTP_HW_CMN_ERR_INVAL; 
+		_ETR(rc);
+	}
+err:
+	_DPRT("%s: rc %d\n", __FUNCTION__, rc);
+	return rc;
+}
+
+static  otp_hw_cmn_err_t skp_hw_write(otp_hw_cmn_t* dev, 
+		u32 addr,
+		const u32* data,
+		u32 size)
+{
+	otp_hw_cmn_row_conf_t *cfg =  
+				!(dev->ctl_cmd.ctl&OTP_HW_CMN_CTL_CONF)? NULL: &dev->row_conf;
+	_ETR(dev->ctl_cmd.ctl);	
+	return skp_write(dev, addr, cfg, data, size);
+}
+
+static otp_hw_cmn_err_t skp_hw_read(otp_hw_cmn_t *dev,
+			u32 addr,
+			u32 *data,
+			u32 size)
+{
+
+	otp_hw_cmn_row_conf_t *cfg =  
+			  !(dev->ctl_cmd.ctl&OTP_HW_CMN_CTL_CONF)? NULL : &dev->row_conf;
+	_ETR(dev->ctl_cmd.ctl);	
+	return skp_read(dev, addr, cfg, data, size);
+
+}
+
+static otp_hw_cmn_err_t skp_hw_lock(otp_hw_cmn_t *dev,
+			u32 addr, 
+			otp_hw_cmn_perm_t perm,
+			u8 lock)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	switch ( perm ) {
+		case OTP_HW_CMN_CTL_LOCK_NS:
+		case OTP_HW_CMN_CTL_LOCK_NS_PROV:
+		case OTP_HW_CMN_CTL_LOCK_ALL:
+		case OTP_HW_CMN_CTL_LOCK_S:
+			/* TODO: Add FSR support */
+			rc = ksr_multi_portal_lock(dev, perm, lock);
+		break;
+		default:
+			/* TODO: Add FSR support */
+			rc = ksr_portal_lock(dev, addr, perm, lock);
+	}
+	return rc;
+}
+
+
+static otp_hw_cmn_err_t skp_hw_status(otp_hw_cmn_t *dev,
+			u32 addr,
+			otp_hw_cmn_status_t status,
+			u32* res)
+{
+
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL; 
+	/* TODO: Add FSR support */
+	rc = ksr_portal_status(dev, addr, status, res);
+	return rc;
+}
+
+__weak otp_hw_cmn_err_t sotp_hw_cmn_ctl(otp_hw_cmn_t *dev, 
+			const otp_hw_cmn_ctl_cmd_t *cmd,
+			u32* res)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_UNSP;
+	switch ((u32)(cmd->ctl)) {
+   		case OTP_HW_CMN_CTL_CONF:
+			memcpy(&dev->row_conf, 
+				(otp_hw_cmn_row_conf_t*)cmd->data, 
+				cmd->size);
+
+			dev->ctl_cmd.ctl |= cmd->ctl;
+			rc = OTP_HW_CMN_OK;
+			break;
+   		case (~((u32)OTP_HW_CMN_CTL_CONF)):
+			dev->ctl_cmd.ctl &= ~cmd->ctl;
+			rc = OTP_HW_CMN_OK;
+			break;
+   		case OTP_HW_CMN_CTL_UNLOCK: {
+				otp_hw_ctl_data_t* ctl_data = (otp_hw_ctl_data_t*)cmd->data;
+				rc = skp_hw_lock(dev, ctl_data->addr, ctl_data->perm, 0);
+			}
+			break;
+		case OTP_HW_CMN_CTL_LOCK: {
+				otp_hw_ctl_data_t* ctl_data = (otp_hw_ctl_data_t*)cmd->data;
+				rc = skp_hw_lock(dev, ctl_data->addr, ctl_data->perm, 1);
+			}
+			break;
+   		case OTP_HW_CMN_CTL_STATUS: {
+				otp_hw_ctl_data_t* ctl_data = (otp_hw_ctl_data_t*)cmd->data;	
+				rc = skp_hw_status(dev, ctl_data->addr, ctl_data->status, res);
+			}
+			break;
+		default :
+			break;	
+	}
+	return rc;
+	
+}
+
+
+__weak otp_hw_cmn_err_t sotp_hw_dev_mmap(otp_hw_cmn_t* dev)
+{
+	dev->mm = KSR_BASE;
+	return OTP_HW_CMN_OK;
+}
+
+__weak otp_hw_cmn_err_t sotp_hw_init(otp_hw_cmn_t* dev)
+{
+	DEFINE_SOTP_MAP_ROW_INITLR(rows);
+	if (sotp_hw_dev_mmap(dev)) {
+		return OTP_HW_CMN_ERR_FAIL;
+	}
+	dev->rows = rows;
+	dev->row_max = sizeof(rows)/sizeof(otp_hw_cmn_row_t);
+	return OTP_HW_CMN_OK;
+}
+
+
+otp_hw_cmn_err_t sotp_hw_cmn_init(otp_hw_cmn_t* dev)
+{
+	if (sotp_hw_init(dev)) {
+		_ETR(OTP_HW_CMN_ERR_FAIL);
+		return OTP_HW_CMN_ERR_FAIL;
+	}
+	dev->read = skp_hw_read;
+	dev->write = skp_hw_write;
+	dev->ctl = sotp_hw_cmn_ctl;
+	return OTP_HW_CMN_OK;
+}
diff --git a/arch/arm/mach-bcmbca/otp/sotp_hw.c b/arch/arm/mach-bcmbca/otp/sotp_hw.c
new file mode 100644
index 0000000000..3d14f7834f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp/sotp_hw.c
@@ -0,0 +1,1679 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2020 Broadcom Ltd.
+ */
+
+/***************************************************************************
+*
+* Description: Secure OTP  accessor for SoCs: 
+* 	6856,6858,6846,63158,4908,47622,63178,6756
+
+
+* write(fuse)/read key and rows for the SEC KEY section , read/write(fuse) status per region 
+*
+*
+***************************************************************************/
+
+/* Includes. */
+
+#include <common.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include "linux/printk.h"
+#include <asm/arch/misc.h>
+
+#include "otp_map_cmn.h"
+#include "sotp.h"
+
+//#define OTP_DRY_RUN
+//#define DEBUG_SOTP
+
+#ifdef DEBUG_SOTP
+#define   SOTP_DBG(...) printf(__VA_ARGS__)
+#define _ETR(__p__)  printf("%s \n\t\t\t\t -> %s:%d ERROR code %d\n",__FILE__, __FUNCTION__,__LINE__,__p__)
+#define _TR(__p__)  printf("%s \n\t\t\t\t -> %s:%d code %d / 0x%x\n",__FILE__, __FUNCTION__,__LINE__,__p__,__p__)
+#else
+#define   SOTP_DBG(...)
+#define _ETR(__p__)
+#define _TR(__p__)
+#endif
+
+#define SOTP_ERR_PRINT printf
+
+
+typedef enum __section_id {
+	SOTP_SECT_ID_RSVD = 0,
+	SOTP_SECT_ID_BLOCK_LOCK,
+	SOTP_SECT_ID_PROGLOCK,
+	SOTP_SECT_ID_DEVICE_CFG,
+	SOTP_SECT_ID_GENERAL_CFG_BCM,
+	SOTP_SECT_ID_GENERAL_CUST_ID,
+	SOTP_SECT_ID_GENERAL_VEND_ID,
+	SOTP_SECT_ID_SEC_KEY_1,
+	SOTP_SECT_ID_SEC_KEY_2,
+	SOTP_SECT_ID_SEC_KEY_3,
+	SOTP_SECT_ID_SEC_KEY_4,
+	SOTP_SECT_ID_SEC_KEY_5,
+	SOTP_SECT_ID_SEC_KEY_6,
+	SOTP_SECT_ID_SEC_KEY_7,
+	SOTP_SECT_ID_MAX,
+} sotp_section_id_t;
+
+static  int sectn_map[SOTP_SECT_ID_MAX] = 
+			{8, 2, 2, 4, 4, 4, 4, 12, 12, 12, 12, 12, 12, 12 };
+
+
+/*
+ * locates row id
+ * */
+static otp_hw_cmn_err_t  lookup_row(otp_hw_cmn_t* dev, 
+	u32 addr,
+	otp_hw_cmn_row_t** row)
+{
+	u32 i;
+	otp_hw_cmn_row_t* rows = dev->rows;
+	for (i = 0; i < dev->row_max; i++) {
+		if ( (addr >= rows[i].addr) && (addr < (rows[i].addr + rows[i].range)) ) {
+			*row = &rows[i];
+			return OTP_HW_CMN_OK;	
+		}
+	}
+	_ETR(OTP_HW_CMN_ERR_UNSP);
+	return OTP_HW_CMN_ERR_UNSP;
+}
+
+static u32 row2regn(u32 r)
+{
+	return (r/ROWS_PER_RGN);
+}
+
+static int row2sect(int row, u32* sect)
+{
+	int i; 
+	if (row < 0 || row > sect[SOTP_SECT_ID_MAX-1] - 1) {
+		return -1;
+	}
+
+	for (i = 0; i < SOTP_SECT_ID_MAX; i++) {
+		if (row <= (int)sectn_map[i] - 1) {
+			*sect = i;
+			break;	
+		}
+	}
+	SOTP_DBG("row %u --> sect %u\n",row, *sect); 
+	return 0;
+}
+
+/*
+static inline int sect2row(otp_hw_cmn_section_id_t s, u32 row_range[2])
+{
+	if (s >= SOTP_SECT_ID_RSVD  && s < SOTP_SECT_ID_MAX) {
+		row_range[0] = !s ? 0 : sectn_map[s-1];
+		row_range[1] = sectn_map[s] - row_range[0];
+		return 0;
+	}
+	return -1;
+}
+*/
+static inline u32 sect2regn(u32 s, u32 regn_range[2])
+{
+	if (s >= SOTP_SECT_ID_RSVD  && s < SOTP_SECT_ID_MAX) {
+		regn_range[0] = !s ? 0 : sectn_map[s-1]/ROWS_PER_RGN ;
+		regn_range[1] = sectn_map[s]/ROWS_PER_RGN - regn_range[0];
+		return 0;
+	}
+	return -1;
+}
+
+#define sotp_hw_writel_or(__DEV__,__OFST__,__data)		\
+	sotp_hw_writel(__DEV__,__OFST__,(sotp_hw_readl(__DEV__,__OFST__)|__data))
+
+
+#define sotp_hw_writel_and(__DEV__,__OFST__,__data)		\
+	sotp_hw_writel(__DEV__,__OFST__,(sotp_hw_readl(__DEV__,__OFST__)&__data))
+
+__weak u32 sotp_hw_readl(void* dev, u32 offs)
+{
+	otp_hw_cmn_t* hw_dev = (otp_hw_cmn_t*)dev; 
+	return readl(hw_dev->mm+offs);
+}
+
+__weak void sotp_hw_writel(void* dev, u32 offs, u32 data)
+{
+	otp_hw_cmn_t* hw_dev = (otp_hw_cmn_t*)dev; 
+	writel(data, hw_dev->mm + offs);
+}
+
+/***************************************************************************
+* Prototypes / Globals
+***************************************************************************/
+
+/***************************************************************************
+* SOTP functions
+***************************************************************************/
+
+/***************************************************************************
+// Function Name: getCrc32
+// Description  : caculate the CRC 32 of the given data.
+// Parameters   : pdata - array of data.
+//                size - number of input data bytes.
+//                crc -  either 0 or previous return value.
+// Returns      : crc.
+****************************************************************************/
+static u32 getCrc32(u8 *pdata, u32 size, u32 crc)
+{
+     	if (crc == 0) {
+		crc = 0xffffffff;
+     	}
+	/* 
+ 	*  no complement crc32 is used for an SOTP controller   
+ 	* 
+ 	* */
+	return  crc32_no_comp(crc, pdata, size);
+}
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpPollForFDone(void)
+    *  
+    *  Input parameters: 
+    *      none 
+    *      
+    *  Return value:
+    *      SOTP_S_ROW_SUCCESS - The function has completed successfully
+    *      SOTP_E_ROW_TIMEOUT - The function experienced unexpected FSM timeout 
+    *                           from the SOTP block 
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpPollForFDone(otp_hw_cmn_t *dev)
+{
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+
+   u32 reg_rd_data;
+   u32 cntr = 0;
+   
+   reg_rd_data = sotp_hw_readl(dev,SOTP_SOTP_OUT_0_OFFSET);
+   while (( ! (reg_rd_data & SOTP_SOTP_OUT_0_SOTP_OTP_READY)) && (cntr < SOTP_MAX_CNTR))
+   {
+      cntr++;
+      mdelay(1);
+      reg_rd_data = sotp_hw_readl(dev,SOTP_SOTP_OUT_0_OFFSET);
+   }
+
+   if (cntr == SOTP_MAX_CNTR)
+   {
+      rval = SOTP_E_ROW_TIMEOUT;
+      SOTP_ERR_PRINT("\nTimeout waiting for FDONE. \n");
+   }
+
+   return rval;
+}
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpSetStartAndPollForCmdDone(void)
+    *  
+    *  Input parameters: 
+    *      none 
+    *      
+    *  Return value:
+    *      SOTP_S_ROW_SUCCESS - The function has completed successfully
+    *      SOTP_E_ROW_TIMEOUT - The function experienced unexpected FSM timeout 
+    *                           from the SOTP block 
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpSetStartAndPollForCmdDone(otp_hw_cmn_t *dev)
+{
+   
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+
+   u32 reg_rd_data;
+   u32 cntr = 0;
+   /* Set the start bit */
+   sotp_hw_writel_or(dev, SOTP_OTP_CTRL_0_OFFSET, SOTP_OTP_CTRL_0_START);
+
+   mdelay(1);
+
+   /* Wait for the FSM to say it is done */
+   reg_rd_data = sotp_hw_readl(dev, SOTP_OTP_STATUS_1_OFFSET);
+   while (( ! (reg_rd_data & SOTP_OTP_STATUS_1_CMD_DONE)) && (cntr < SOTP_MAX_CNTR)) {
+      cntr++;
+      mdelay(1);
+      reg_rd_data = sotp_hw_readl(dev, SOTP_OTP_STATUS_1_OFFSET);
+   }
+   if (cntr != SOTP_MAX_CNTR)
+   {
+      /* Clear the start bit */
+      sotp_hw_writel_and(dev, SOTP_OTP_CTRL_0_OFFSET, (~SOTP_OTP_CTRL_0_START));
+   }
+   else
+   {
+      rval = SOTP_E_ROW_TIMEOUT;
+      SOTP_ERR_PRINT("\nTimeout waiting for CMD_DONE. 0x%x timeout after %d ms\n",reg_rd_data, cntr);
+   }
+
+   return rval;
+}
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpPrepForFusing(void)
+    *  
+    *  Input parameters: 
+    *      none            
+    *
+    *  Return value:
+    *      SOTP_S_ROW_SUCCESS - The function has completed successfully
+    *      SOTP_E_ROW_TIMEOUT - The function experienced unexpected FSM timeout 
+    *                           from the SOTP block 
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpPrepForFusing(otp_hw_cmn_t *dev)
+{
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+   int i;
+   u32 authVal[4] = {0xf,0x4,0x8,0xd};
+
+   /* Poll for FDONE bit before doing any access */
+   if ((rval = sotpPollForFDone(dev)) == SOTP_E_ROW_TIMEOUT) {
+	_ETR(rval);
+      return rval;
+    }
+   /* turn on the cpu mode */
+   sotp_hw_writel_or(dev, SOTP_OTP_PROG_CTRL_OFFSET , SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN);
+
+   /* set up the OTP_CMD for OTP_ProgEnable */
+   sotp_hw_writel(dev, SOTP_OTP_CTRL_0_OFFSET , SOTP_OTP_CTRL_0_OTP_CMD_OTP_PROG_ENABLE);
+
+   /* Write F, 4, 8, D in sequence to BITSEL */
+   for (i = 0; i < sizeof(authVal)/sizeof(u32); i++) {
+      sotp_hw_writel(dev, SOTP_OTP_WDATA_0_OFFSET , authVal[i]);
+      /* Start the state machine */
+      rval = sotpSetStartAndPollForCmdDone(dev);
+	if (rval != SOTP_S_ROW_SUCCESS) {
+	        _ETR(rval);
+		goto err;
+	}
+         /* Clear the CMD_DONE bit */
+	sotp_hw_writel(dev, SOTP_OTP_STATUS_1_OFFSET , SOTP_OTP_STATUS_1_CMD_DONE);
+
+   }
+
+   /* By default, SOTP block state is "unprogrammed" which prevents writing to      */
+   /* rows 16-111. Set the state to ManuProg and SwNonAbDevice to allow programming */
+   sotp_hw_writel_or(dev, SOTP_CHIP_CNTRL_OFFSET, (SOTP_CHIP_CTRL_SW_MANU_PROG | SOTP_CHIP_CTRL_SW_NON_AB_DEVICE | \
+                    SOTP_CHIP_CNTRL_SW_OVERRIDE_CHIP_STATES));
+
+   /* Poll for FDONE bit before doing any further access */
+   rval = sotpPollForFDone(dev);
+err:
+   /* return if prep is ok or not */
+   return rval;
+}
+
+
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpFinishFusing(void)
+    *  
+    *  Input parameters: 
+    *      none     
+    *
+    *  Return value:
+    *     SOTP_S_ROW_SUCCESS - The function has completed successfully
+    *     SOTP_E_ROW_TIMEOUT - The function experienced unexpected FSM timeout 
+    *                          from the SOTP block 
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpFinishFusing(otp_hw_cmn_t *dev)
+{
+   
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+
+
+   /* set up the OTP_CMD for PROG  */
+#ifndef OTP_DRY_RUN
+   sotp_hw_writel(dev, SOTP_OTP_CTRL_0_OFFSET , SOTP_OTP_CTRL_0_OTP_CMD_PROG);
+   /* Start the state machine */
+   if ((rval = sotpSetStartAndPollForCmdDone(dev)) == SOTP_S_ROW_SUCCESS)
+   {
+      /* Clear the CMD_DONE bit */
+      sotp_hw_writel(dev, SOTP_OTP_STATUS_1_OFFSET , SOTP_OTP_STATUS_1_CMD_DONE);
+
+      /* turn off cpu mode */
+      sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN));
+   }
+#else
+      /* Clear the CMD_DONE bit */
+      sotp_hw_writel(dev, SOTP_OTP_STATUS_1_OFFSET , SOTP_OTP_STATUS_1_CMD_DONE);
+
+      /* turn off cpu mode */
+      sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN));
+#endif
+   return rval;
+}
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpReadNonEccRow(u32 row, u64 *pData)
+    *  
+    *  Input parameters: 
+    *      row   - row in question
+    *      pDst  - pointer to where the data will be returned to
+    *      
+    *  Return value:
+    *      SOTP_S_ROW_SUCCESS     - The function has completed successfully
+    *      SOTP_E_ROW_TIMEOUT     - The function experienced unexpected FSM 
+    *                               timeout from the SOTP block (pDst is invalid)
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpReadNonEccRow(otp_hw_cmn_t *dev,u32 row, u64 *pDst)
+{
+   
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+
+
+   /* Poll for FDONE bit before doing any access */
+   if ((rval = sotpPollForFDone(dev)) == SOTP_E_ROW_TIMEOUT)
+      return rval;
+
+   /* Clear ECC detect, ecc correct as well as command done bits */
+   sotp_hw_writel(dev, SOTP_OTP_STATUS_1_OFFSET , (SOTP_OTP_STATUS_1_CMD_DONE | SOTP_OTP_STATUS_1_ECC_COR | SOTP_OTP_STATUS_1_ECC_DET));
+
+   /* zero out the regs_ecc_en bits, then turn on cpu mode, and set regs_ecc_en to disabled */
+   sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_REGS_ECC_EN_MASK));
+   sotp_hw_writel_or(dev, SOTP_OTP_PROG_CTRL_OFFSET,  ( SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN | SOTP_OTP_PROG_CTRL_OTP_DISABLE_ECC | \
+                              SOTP_OTP_PROG_CTRL_REGS_ECC_DIS ));
+
+   /* Set OTP addr with the row to be read */
+   sotp_hw_writel(dev, SOTP_OTP_ADDR_OFFSET , (row << SOTP_OTP_ADDR_OTP_ADDR_SHIFT));
+
+   /* set up the OTP_CMD for OTP_READ */
+   sotp_hw_writel(dev, SOTP_OTP_CTRL_0_OFFSET , SOTP_OTP_CTRL_0_OTP_CMD_OTP_READ);
+
+   /* Start the state machine */
+   if ((rval = sotpSetStartAndPollForCmdDone(dev)) == SOTP_S_ROW_SUCCESS)
+   {
+      /* Data in row is valid. Pass it to return buffer */
+      *pDst = (((u64)sotp_hw_readl(dev, SOTP_OTP_RDATA_1_OFFSET) << 32) | (sotp_hw_readl(dev,SOTP_OTP_RDATA_0_OFFSET)));
+
+      /* Clear the CMD_DONE bit */
+      sotp_hw_writel(dev, SOTP_OTP_STATUS_1_OFFSET , SOTP_OTP_STATUS_1_CMD_DONE);
+
+      /* turn off cpu mode */
+      sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN));
+   }
+
+   return rval;
+}
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpFuseNonEccRow(u32 row, u64 src)
+    *  
+    *  Input parameters: 
+    *      row   - row in question
+    *      src   - data bits to fuse (only the bottom 41 bits are relevant)
+    *     
+    *  Return value:
+    *     SOTP_S_ROW_SUCCESS     - The function has completed successfully
+    *     SOTP_E_ROW_TIMEOUT     - The function experienced unexpected FSM 
+    *                              timeout from the SOTP block 
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpFuseNonEccRow(otp_hw_cmn_t *dev, u32 row, u64 src)
+{
+   
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+
+
+   /* Prepare the SOTP FSM for fusing a row of data */
+   if ((rval = sotpPrepForFusing(dev)) != SOTP_S_ROW_SUCCESS)
+      return rval;
+
+   /* Disable ECC to be generated and fused by hardware */
+   sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_OTP_ECC_WREN));
+
+   /* Set OTP addr with the row to be fused */
+   sotp_hw_writel(dev, SOTP_OTP_ADDR_OFFSET , (row << SOTP_OTP_ADDR_OTP_ADDR_SHIFT));
+#ifndef OTP_DRY_RUN  
+   /* Set up the registers with the data to be written */
+   sotp_hw_writel(dev, SOTP_OTP_WDATA_0_OFFSET , (u32)(src & 0xffffffff)); /* lower 32 bit data word */
+   sotp_hw_writel(dev, SOTP_OTP_WDATA_1_OFFSET , (u32)(src >> 32)); /* upper 32 bit data word */
+#endif
+   /* ... and fuse */
+   rval = sotpFinishFusing(dev);
+
+   return rval;
+}
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpIsRegionFuseLocked(u32 region)
+    *  
+    *  Input parameters: 
+    *      row   - rows 28 thru 111 reside in different regions that may be fuse-locked
+    *      
+    *  Return value:
+    *      SOTP_S_ROW_SUCCESS     - The function has completed successfully
+    *      SOTP_E_ROW_FUSE_LOCK   - The row in question is within a region that 
+    *                               is permanently fuse-locked 
+    *      SOTP_E_ROW_TIMEOUT     - The function experienced unexpected FSM 
+    *                               timeout from the SOTP block 
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpIsRegionFuseLocked(otp_hw_cmn_t *dev,u32 region)
+{
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+   u64 rowData;
+
+   /* The locking of all the regions require two rows of OTP. Each row has 41 */
+   /* bits. There are no ecc nor fail bits in these two rows. Hence, regions  */
+   /* 0 thru 19 lock bits are in SOTP row 8. Region 20 has a lock bit in each */
+   /* row. Regions 21 thru 27 are all in row 9. Retrieve row 8 if required. If*/
+   /* If either one of the two approp. bits are set, the region is fuse locked*/
+   if (region < SOTP_NUM_REG_IN_FUSELOCK_ROW)
+   {
+      if ((rval = sotpReadNonEccRow(dev, SOTP_FIRST_FUSELOCK_ROW, &rowData)) != SOTP_S_ROW_SUCCESS)
+         return rval;
+      else
+      {
+         if (rowData & ( (u64)0x3 << (region * 2) )) 
+            return SOTP_E_ROW_FUSE_LOCK;
+      }
+   }
+
+   if (region >= (SOTP_NUM_REG_IN_FUSELOCK_ROW - 1))
+   {
+      if ((rval = sotpReadNonEccRow(dev, (SOTP_FIRST_FUSELOCK_ROW + 1), &rowData)) != SOTP_S_ROW_SUCCESS)
+         return rval;
+      else
+      {
+         if ((region == (SOTP_NUM_REG_IN_FUSELOCK_ROW - 1)) && (rowData & 0x1))
+            return SOTP_E_ROW_FUSE_LOCK;
+         else 
+         { 
+            if (rowData & ( (u64)0x3 << (((region-SOTP_NUM_REG_IN_FUSELOCK_ROW)*2)+1) )) 
+               return SOTP_E_ROW_FUSE_LOCK;
+         } 
+      }
+   }
+
+   return rval;
+}
+
+
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpFuseLockRegion(u32 region)
+    *  
+    *  Description: PERMANENTLY WRITE LOCK regions
+    *
+    *  Input parameters: 
+    *     row   - rows 28 thru 111 reside in different regions that may be fuse-locked
+    *     
+    *  Return value:
+    *     SOTP_S_ROW_SUCCESS     - The function has completed successfully
+    *     SOTP_E_ROW_TIMEOUT     - The function experienced unexpected FSM 
+    *                              timeout from the SOTP block 
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpFuseLockRegion(otp_hw_cmn_t *dev,u32 region)
+{
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+   u64 bitsToFuse;
+
+   /* The locking of all the regions require two rows of OTP. Each row has 41 */
+   /* bits. There are no ecc nor fail bits in these two rows. Hence, regions  */
+   /* 0 thru 19 lock bits are in SOTP row 8. Region 20 has a lock bit in each */
+   /* row. Regions 21 thru 27 are all in row 9. Retrieve row 8 if required. If*/
+   /* If either one of the two approp. bits are set, the region is fuse locked*/
+   if (region < SOTP_NUM_REG_IN_FUSELOCK_ROW)
+   {
+      // Figure out the bits to fuse (truncate to 41 bits)
+      bitsToFuse = ((u64)0x3 << (region * 2)) & 0x1ffffffffff;
+
+      if ((rval = sotpFuseNonEccRow(dev, SOTP_FIRST_FUSELOCK_ROW, bitsToFuse)) != SOTP_S_ROW_SUCCESS)
+         return rval;
+   }
+
+   if (region >= (SOTP_NUM_REG_IN_FUSELOCK_ROW - 1))
+   {
+      // Figure out the bits to fuse (truncate to 41 bits)
+      if (region == (SOTP_NUM_REG_IN_FUSELOCK_ROW - 1)) 
+         bitsToFuse = 0x1;
+      else
+         bitsToFuse =  (u64)0x3 << (((region-SOTP_NUM_REG_IN_FUSELOCK_ROW)*2)+1);
+
+      rval = sotpFuseNonEccRow(dev, (SOTP_FIRST_FUSELOCK_ROW + 1), bitsToFuse);
+   }
+
+   return rval;
+}
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpWriteEccRow(u32 row, u32 src)
+    *  
+    *  Input parameters: 
+    *     row  - SOTP has 112 rows total. This func is allowed to write to
+    *            rows 28 thru 111 (first row is row 0)
+    *     src  - Each row has 41 bits. Rows 16 thru 111 have 2 fail bits,
+    *            7 ecc bits, and 32 data bits. This input parameter is
+    *            the 32 data bits to be fused. 
+    *     raw_write - If set then ECC checks are skipped
+    *     
+    *  Return value:
+    *     SOTP_S_ROW_SUCCESS  - The function has completed successfully
+    *     SOTP_E_ROW_FUSE_LOCK- The row is permanently locked from being changed
+    *     SOTP_E_ROW_TIMEOUT  - The function experienced unexpected FSM timeout 
+    *                           from the SOTP block 
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpWriteEccRow(otp_hw_cmn_t *dev, u32 row, u32 src, u32 raw_write)
+{
+   
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+
+   SOTP_DBG("%s: row:%d data:0x%08x\n", __FUNCTION__, row, src);
+
+   if( row < SOTP_FIRST_ECC_CONFIG_ROW || row > SOTP_NUM_ROWS-1 )
+   {
+      SOTP_ERR_PRINT("%s: ECC Row %d out of bound! Min:%d Max:%d\n", __FUNCTION__, row, SOTP_FIRST_ECC_CONFIG_ROW, SOTP_NUM_ROWS-1);
+      return SOTP_E_ROW_ERROR;
+   }
+
+   /* Check to see that the row in question is not fuse locked */
+   if ((rval = sotpIsRegionFuseLocked(dev, row/SOTP_ROWS_IN_REGION)) == SOTP_E_ROW_FUSE_LOCK)
+   {
+      SOTP_ERR_PRINT("%s: Row %d is fuse locked. Cannot write row data.\n", __FUNCTION__, row);
+      return rval;
+   }
+
+   /* Prepare the SOTP FSM for fusing a row of data */
+   if ((rval = sotpPrepForFusing(dev)) != SOTP_S_ROW_SUCCESS) {
+	_ETR(rval);
+      return rval;
+   }
+   if( raw_write )
+   {
+      /* Disable ECC computation and fusing by hardware */
+      sotp_hw_writel_or(dev, SOTP_OTP_PROG_CTRL_OFFSET , SOTP_OTP_PROG_CTRL_OTP_DISABLE_ECC);
+      sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_OTP_ECC_WREN));
+   }
+   else
+   {
+      /* Enable ECC to be generated and fused by hardware */
+      sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_OTP_DISABLE_ECC));
+      sotp_hw_writel_or(dev, SOTP_OTP_PROG_CTRL_OFFSET , SOTP_OTP_PROG_CTRL_OTP_ECC_WREN);
+   }
+#ifndef  OTP_DRY_RUN
+   /* Set OTP addr with the row to be fused */
+   sotp_hw_writel(dev, SOTP_OTP_ADDR_OFFSET , (row << SOTP_OTP_ADDR_OTP_ADDR_SHIFT));
+
+   /* Set up the registers with the data to be written */
+   sotp_hw_writel(dev, SOTP_OTP_WDATA_0_OFFSET , src); /* 32 bit data word */
+   sotp_hw_writel(dev, SOTP_OTP_WDATA_1_OFFSET , 0);   /* ensure the two fail bits are not fused */
+#endif
+   /* ... and fuse */
+   rval = sotpFinishFusing(dev);
+
+   return rval;
+}
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpFuseSecKeyRowFailBits(u32 row)
+    *  
+    *  Input parameters: 
+    *      row   - This func is allowed to fuse fail bits in rows 28 thru 111
+    *      
+    *  Return value:
+    *      SOTP_S_ROW_SUCCESS     - The function has completed successfully
+    *      SOTP_E_ROW_TIMEOUT     - The function experienced unexpected FSM 
+    *                               timeout from the SOTP block 
+    *      SOTP_E_ROW_ERROR       - The function experienced unexpected register 
+    *                               ret value from SOTP block 
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpFuseSecKeyRowFailBits(otp_hw_cmn_t *dev, u32 row)
+{
+   
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+
+
+   /* Prepare the SOTP FSM for fusing a row of data */
+   if ((rval = sotpPrepForFusing(dev)) != SOTP_S_ROW_SUCCESS)
+      return rval;
+
+   /* Enable ECC to be generated and fused by hardware */
+   sotp_hw_writel_or(dev, SOTP_OTP_PROG_CTRL_OFFSET , SOTP_OTP_PROG_CTRL_OTP_ECC_WREN);
+#ifndef OTP_DRY_RUN
+   /* Set OTP addr with the row to be fused */
+   sotp_hw_writel(dev, SOTP_OTP_ADDR_OFFSET , (row << SOTP_OTP_ADDR_OTP_ADDR_SHIFT));
+
+   /* Set up the registers with the data to be written */
+   sotp_hw_writel(dev, SOTP_OTP_WDATA_0_OFFSET , 0);                          /* 32 bit data word  ... no change    */
+   sotp_hw_writel(dev, SOTP_OTP_WDATA_1_OFFSET , SOTP_OTP_WDATA_1_FAIL_MASK); /* ensure the two fail bits are fused */
+#endif
+   /* ... and fuse */
+   rval = sotpFinishFusing(dev);
+
+   return rval;
+}
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpRegionReadLockStatus(u32 region)
+    *  
+    *  Input parameters: 
+    *     row   - regions 0 - 28
+    *     
+    *  Return value:
+    *     SOTP_S_ROW_SUCCESS     - The function has completed successfully
+    *     SOTP_E_ROW_READ_LOCK   - The row in question is within a region that 
+    *                               is read-locked until the next POR
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpRegionReadLockStatus(otp_hw_cmn_t *dev, u32 region)
+{
+   
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+
+   /* Check to see if that region is locked */
+   if ((sotp_hw_readl(dev, SOTP_OTP_RD_LOCK_OFFSET) & ( 0x1 << region )) )
+      rval = SOTP_E_ROW_READ_LOCK;
+
+   return rval;
+}
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpReadEccRow(u32 row, u32 *pDst)
+    *  
+    *  Input parameters: 
+    *     row   - This func is allowed to read from rows 28 thru 111
+    *     pDst  - A pointer to the location that the retrieved 32 data
+    *             bits will be written to.
+    *     raw_read - If set then ECC checks are skipped
+    *     
+    *  Return value:
+    *     SOTP_S_ROW_SUCCESS     - The function has completed successfully
+    *     SOTP_S_ROW_ECC_COR     - The function ecc corrected 1 bad bit when 
+    *                              returning row data (pDst points to valid data)
+    *     SOTP_E_ROW_ECC_DET     - The function detected 2 or more uncorrectable 
+    *                              bits within the row (pDst is invalid)
+    *     SOTP_E_ROW_FAIL_SET    - The function detected that 1 or both of 
+    *                              the fail bits are set (pDst is invalid)
+    *     SOTP_E_ROW_READ_LOCK   - The row in question is within a region that 
+    *                              is read-locked until the next POR
+    *     SOTP_E_ROW_TIMEOUT     - The function experienced unexpected FSM 
+    *                              timeout from the SOTP block (pDst is invalid)
+    *     SOTP_E_ROW_ERROR       - The function experienced unexpected register 
+    *                              ret value from SOTP block (pDst is invalid)
+    *
+    ********************************************************************* */
+static SotpRowStatus sotpReadEccRow(otp_hw_cmn_t *dev, u32 row, u32 *pDst, u32 raw_read)
+{
+   
+   SotpRowStatus rval;
+
+
+   SOTP_DBG("%s: row:%d bufp:%px\n", __FUNCTION__, row, pDst);
+
+   if( row < SOTP_FIRST_ECC_CONFIG_ROW || row > SOTP_NUM_ROWS-1 )
+   {
+      SOTP_DBG("%s: ECC Row %d out of bound! Min:%d Max:%d\n", __FUNCTION__, row, SOTP_FIRST_ECC_CONFIG_ROW, SOTP_NUM_ROWS-1);
+      return SOTP_E_ROW_ERROR;
+   }
+
+   /* Check to see that the row in question is not readlocked until the next POR */
+   if ((rval = sotpRegionReadLockStatus(dev, row/SOTP_ROWS_IN_REGION)) == SOTP_E_ROW_READ_LOCK)
+   {
+      SOTP_DBG("%s: Row %d is locked from reading. Returned key data is invalid\n", __FUNCTION__, row);
+      return SOTP_E_ROW_READ_LOCK;
+   }
+
+   /* Poll for FDONE bit before doing any access */
+   if ((rval = sotpPollForFDone(dev)) == SOTP_E_ROW_TIMEOUT)
+   {
+      SOTP_ERR_PRINT("%s: Row %d read timed out. \n", __FUNCTION__, row);
+      return SOTP_E_ROW_TIMEOUT;
+   }
+
+   /* Clear ECC detect, ecc correct as well as command done bits */
+   sotp_hw_writel(dev, SOTP_OTP_STATUS_1_OFFSET , 
+		(SOTP_OTP_STATUS_1_CMD_DONE | SOTP_OTP_STATUS_1_ECC_COR | SOTP_OTP_STATUS_1_ECC_DET));
+
+   /* enable ecc checks (low), zero out the regs_ecc_en bits  ... then turn on cpu mode, and set regs_ecc_en to enabled */
+   /* expect Bug?  When ecc=0 then programs 0x0, Reg says that it should be set to 4'b0101 : ECC check DISABLED */
+   sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~( SOTP_OTP_PROG_CTRL_OTP_DISABLE_ECC | SOTP_OTP_PROG_CTRL_REGS_ECC_EN_MASK )));
+
+   /* Disable ECC checks for raw reads */
+   if( raw_read )
+      sotp_hw_writel_or(dev, SOTP_OTP_PROG_CTRL_OFFSET , ( SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN | SOTP_OTP_PROG_CTRL_OTP_DISABLE_ECC | SOTP_OTP_PROG_CTRL_REGS_ECC_DIS ));
+   else
+      sotp_hw_writel_or(dev, SOTP_OTP_PROG_CTRL_OFFSET , ( SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN | SOTP_OTP_PROG_CTRL_REGS_ECC_EN ));
+
+   /* Set OTP addr with the row to be read */
+   sotp_hw_writel(dev, SOTP_OTP_ADDR_OFFSET , (row << SOTP_OTP_ADDR_OTP_ADDR_SHIFT));
+
+   /* set up the OTP_CMD for OTP_READ */
+   sotp_hw_writel(dev, SOTP_OTP_CTRL_0_OFFSET , SOTP_OTP_CTRL_0_OTP_CMD_OTP_READ);
+
+   /* Start the state machine */
+   if ((rval = sotpSetStartAndPollForCmdDone(dev)) == SOTP_S_ROW_SUCCESS)
+   {
+      if( !raw_read ) 
+      {
+         /* If the row is marked as failed, abort */
+         if (sotp_hw_readl(dev, SOTP_OTP_RDATA_1_OFFSET) & SOTP_OTP_RDATA_1_FAIL_MASK )
+         {
+            SOTP_ERR_PRINT("Row %d is marked as failed . \n", row);
+            return ( SOTP_E_ROW_FAIL_SET );
+         }
+    
+         /* See if the data is bad and ecc correction was not possible */
+         if (sotp_hw_readl(dev, SOTP_OTP_STATUS_1_OFFSET) & SOTP_OTP_STATUS_1_ECC_DET )
+         {
+            SOTP_ERR_PRINT("Row data failed ecc with 2 or more bits . \n");
+               return ( SOTP_E_ROW_ECC_DET );
+         }
+
+         /* See if the data is good but an ecc correction took place */
+         if (sotp_hw_readl(dev, SOTP_OTP_STATUS_1_OFFSET) & SOTP_OTP_STATUS_1_ECC_COR )
+         {
+            SOTP_ERR_PRINT("Row data valid, but ecc corrected 1 bit. \n");
+            rval = SOTP_S_ROW_ECC_COR;
+         }
+      }
+
+      /* Data in row is valid. Pass it to return buffer */
+      *pDst = sotp_hw_readl(dev,SOTP_OTP_RDATA_0_OFFSET);
+
+      /* Clear the CMD_DONE bit */
+      sotp_hw_writel(dev, SOTP_OTP_STATUS_1_OFFSET , SOTP_OTP_STATUS_1_CMD_DONE);
+
+      /* turn off cpu mode */
+      sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN));
+   }
+
+   return rval;
+}
+
+/*  *********************************************************************
+    *  extern SotpKeyStatus sotpReadKeyslotData(u32 section, u32 *pDst, u32 len)
+    *  
+    *  Description - Used by the bootrom or bootloader to read a key from SOTP
+    *
+    *  Input parameters: 
+    *     section - Section that the key info should be read from
+    *               (7 =< section =< 13)
+    *     pDst    - pointer to the buffer containing the key (chopped 
+    *               up into 32 bit words)
+    *     len     - The number of 32 bit words in the key to read in (len =< 8)
+    *     
+    *  Return value:
+    *     SOTP_S_KEY_SUCCESS - The function has completed successfully, and
+    *                          pDst holds valid data
+    *     SOTP_S_KEY_EMPTY   - The function has completed successfully, but 
+    *                          no credential is currently stored in this section
+    *     SOTP_E_KEY_CRC_MIS - The function detected a CRC mismatch during the key read 
+    *     SOTP_E_KEY_UNDERRUN- The function ran out of rows within a section
+    *                          before reading the entire key and crc
+    *     SOTP_E_KEY_ERROR   - The function experienced an error in one of the
+    *                          rows of the section
+    *
+    ********************************************************************* */
+static SotpKeyStatus sotpReadKeyslotData(otp_hw_cmn_t *dev, u32 section, u32 *pDst, u32 len)
+{
+   u32 startRow, row, printRow, readCrc;
+   u32 calcCrc = 0;
+
+   u32 i = 0;
+   SotpKeyStatus rval    = SOTP_E_KEY_BADPARAM;
+   SotpRowStatus rowRval = SOTP_S_ROW_SUCCESS;
+
+   SOTP_DBG("%s: section:%d bufp:%px len:%d\n", __FUNCTION__, section, pDst, len);
+
+   /* perform checks of input params */
+   if ((pDst == NULL) || (len == 0) || (len > SOTP_MAX_KEYLEN))
+      return rval;
+
+   if ((section < SOTP_MIN_KEYSLOT) || (section > SOTP_MAX_KEYSLOT))
+   {
+      SOTP_ERR_PRINT("%s: keyslot section:%d out of bound! Min:%d Max:%d\n", __FUNCTION__, section, SOTP_MIN_KEYSLOT, SOTP_MAX_KEYSLOT);
+      return rval;
+   }
+
+   /* Determine the starting row */
+   startRow = ((section - SOTP_MIN_KEYSLOT) * SOTP_ROWS_IN_KEYSLOT) + SOTP_FIRST_KEYSLOT_ROW;
+
+   /* Start reading the key and CRC */
+   for ( row = startRow ; row < (startRow + SOTP_ROWS_IN_KEYSLOT); row++)
+   {
+      /* Determine the current row in a printable format for if something fails */
+      printRow = row - startRow;
+      if (printRow >= 0xa)
+         printRow += (0x100 - 0xa);
+
+      if (i < len) {
+         rowRval = sotpReadEccRow(dev, row, &pDst[i], 0); /* currently reading the key */
+		_TR(pDst[i]);
+}
+
+      if (i == len)
+         rowRval = sotpReadEccRow(dev, row, &readCrc, 0); /* currently reading the crc */
+
+      switch(rowRval)
+      {
+         /* If success, just keep going */
+         case SOTP_S_ROW_SUCCESS: 
+         case SOTP_S_ROW_ECC_COR:
+            i++;
+            if (i > len)
+            {
+               /* done reading sotp. Perform crc validation */
+               calcCrc = getCrc32((u8 *)pDst, (len*4), calcCrc);
+_TR(calcCrc);	
+_TR(readCrc);	
+               if (readCrc == calcCrc) 
+                  return SOTP_S_KEY_SUCCESS; /* Done. pDst buffer holds the key and is good */
+               else
+               {
+                  /* Either the section is empty, or a valid crc mismatch condition exists */
+                  for (i = 0; i < len; i++)
+                  {
+                     if (pDst[i] != 0)
+                     {
+                        SOTP_ERR_PRINT("\nCalculated crc did not match crc stored in row %d. Returned key data is invalid\n", row);
+                        return SOTP_E_KEY_CRC_MIS;
+                     }
+                  }
+                  return SOTP_S_KEY_EMPTY;
+               }
+            }      
+            break;
+
+         /* If fail bit(s) set, row has been marked bad during fusing ... ignore this row */
+         case SOTP_E_ROW_FAIL_SET:
+            break;
+
+         /* Read had 2 or more uncorrectable bits, AND the fail bits were NOT set */
+         /* Row has failed over time in the field */
+         case SOTP_E_ROW_ECC_DET:
+            SOTP_ERR_PRINT("\n2 or more Uncorrectable bits within row %d. Returned key data is invalid \n", row);
+            return SOTP_E_KEY_ERROR;
+            break;
+
+         case SOTP_E_ROW_READ_LOCK:
+            SOTP_DBG("\nRow %d is locked from reading. Returned key data is invalid\n", row);
+            return SOTP_E_KEY_ERROR;
+            break;
+
+         case SOTP_E_ROW_TIMEOUT:
+            SOTP_ERR_PRINT("\nUnexpected SOTP block timeout while reading row %d. Returned key data is invalid\n", row);
+            return SOTP_E_KEY_ERROR;
+            break;
+
+         case SOTP_E_ROW_ERROR:
+         default:
+            SOTP_ERR_PRINT("\nUnknown condition in reading row %d. Returned key data is invalid\n", row);
+            return SOTP_E_KEY_ERROR;
+            break;
+      }
+   }
+
+   /* If we make it here, we ran out of rows in the key slot ... returned data is not valid */
+   SOTP_ERR_PRINT("\nRan out of rows in section %d before reading entire key and crc. Returned key data is invalid\n", section);
+   return SOTP_E_KEY_UNDERRUN;
+}
+
+/*  *********************************************************************
+    *  static SotpKeyStatus sotpLockSecKeyFuse(u32 section)
+    *  
+    *  Input parameters: 
+    *      section - There are 7 locations called sections that can hold 
+    *                up to 256 bits of key information. (7 =< section =< 13).
+    *                This is the location that is to be PERMANENTLY locked down from
+    *                future fusing. This is a permanent lockout even after POR.
+    *      
+    *  Return value:
+    *      SOTP_S_KEY_SUCCESS     - The function has completed successfully
+    *      SOTP_E_KEY_BADPARAM    - The function recieved a bad input parameter
+    *      SOTP_E_KEY_ERROR       - The function experienced unexpected register 
+    *                               ret value from SOTP block 
+    *
+    ********************************************************************* */
+static SotpKeyStatus sotpLockSecKeyFuse(otp_hw_cmn_t *dev, u32 section)
+{
+   SotpKeyStatus rval = SOTP_S_KEY_SUCCESS;
+   u32 region, startRegion;
+
+   /* perform checks of input params */
+   if ((section < SOTP_MIN_KEYSLOT) || (section > SOTP_MAX_KEYSLOT))
+      return SOTP_E_KEY_BADPARAM;
+
+   /* Figure out the start region, and then for each of the three regions */
+   /* in the section, do the for loop */
+   startRegion = SOTP_FIRST_KEYSLOT_REGION + ((section - SOTP_MIN_KEYSLOT) * SOTP_REGIONS_IN_KEYSLOT);
+   for (region = startRegion; region < (startRegion+3); region++)
+   {
+      if (sotpFuseLockRegion(dev, region) != SOTP_S_ROW_SUCCESS)
+         return SOTP_E_KEY_ERROR;
+   }
+   
+   return rval;
+}
+
+/*  *********************************************************************
+    *  static SotpRowStatus sotpLockRegion(u32 region)
+    *  
+    *  Description: TEMPORARILY READ/WRITE LOCK regions. Lock gets reset on POR
+    *
+    *  Input parameters: 
+    *     row   - rows 28 thru 111 reside in different regions that may be fuse-locked
+    *     
+    *  Return value:
+    *     SOTP_S_ROW_SUCCESS     - The function has completed successfully
+    *     SOTP_E_ROW_TIMEOUT     - The function experienced unexpected FSM 
+    *                              timeout from the SOTP block 
+    *
+    ********************************************************************* */
+static SotpKeyStatus sotpLockRegion(otp_hw_cmn_t *dev, u32 region_mask) 
+{
+   if( region_mask ) 
+   {
+      /* enable ecc checks (low), zero out the regs_ecc_en bits  ... then turn on cpu mode, and set regs_ecc_en to enabled */
+      /* expect Bug?  When ecc=0 then programs 0x0, Reg says that it should be set to 4'b0101 : ECC check DISABLED */
+      sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_REGS_ECC_EN_MASK));
+      sotp_hw_writel_or(dev, SOTP_OTP_PROG_CTRL_OFFSET , ( SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN | SOTP_OTP_PROG_CTRL_REGS_ECC_DIS ));
+
+      /* wait a little */
+      mdelay(1);
+
+      /* The read/write lock register is a write-once register on a bit-for-bit bassis     */
+      /* so you don't have to worry about preserving bits that are already set to 1. */
+      sotp_hw_writel_or(dev, SOTP_OTP_RD_LOCK_OFFSET , region_mask);
+      sotp_hw_writel_or(dev, SOTP_OTP_WR_LOCK_OFFSET , region_mask);
+
+      /* wait a little */
+      mdelay(1);
+
+      /* turn off cpu mode */
+      sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN));
+   }
+
+   return SOTP_S_KEY_SUCCESS;
+}
+
+static SotpKeyStatus sotpReadLockRegion(otp_hw_cmn_t *dev, u32 region)
+{
+   return sotpLockRegion(dev, (1 << region));
+}
+
+
+/*  *********************************************************************
+    *  extern SotpKeyStatus readLockKeyslot(u32 section)
+    *  
+    *  Description - After the bootrom or bootloader has read a key from
+    *                SOTP, this function can be called so that no 
+    *                other sw can read this key at a later time.
+    *
+    *  Input parameters: 
+    *      section - There are 7 locations called sections that can hold 
+    *                up to 256 bits of key information. (7 =< section =< 13)
+    *                This is the location that is to be locked down from
+    *                reading until the next power-on-reset.
+    *      
+    *  Return value:
+    *      SOTP_S_KEY_SUCCESS     - The function has completed successfully
+    *      SOTP_E_KEY_BADPARAM    - The function recieved a bad input parameter
+    *
+    ********************************************************************* */
+static SotpKeyStatus readLockKeyslot(otp_hw_cmn_t *dev, u32 section)
+{
+   u32 startRegion;
+
+   /* perform checks of input params */
+   if ((section < SOTP_MIN_KEYSLOT) || (section > SOTP_MAX_KEYSLOT))
+      return SOTP_E_KEY_BADPARAM;
+
+   /* Determine the starting region to lock */
+   startRegion = SOTP_FIRST_KEYSLOT_REGION + 
+      ((section - SOTP_MIN_KEYSLOT) * SOTP_REGIONS_IN_KEYSLOT);
+
+   return (sotpLockRegion(dev, (SOTP_REGIONS_MASK_IN_KEYSLOT << startRegion))); 
+}
+
+static SotpKeyStatus sotpReadLockNonEmptyRegions(otp_hw_cmn_t *dev)
+{
+   int i,j;
+   u32 value;
+   u32 startRegion = SOTP_FIRST_FUSELOCK_ROW/SOTP_ROWS_IN_REGION + SOTP_REGIONS_IN_LOCK;
+   u32 regionMask = 0;
+   SotpRowStatus rval = SOTP_S_ROW_SUCCESS;
+
+   /* readlock all regions before start region */
+   if( startRegion ) 
+	   regionMask = ((1<<startRegion) - 1);
+
+   for( i=startRegion; i<SOTP_NUM_ROWS/SOTP_ROWS_IN_REGION; i++) 
+   {
+      for( j=0; j<SOTP_ROWS_IN_REGION; j++) 
+      {
+         /* Do a raw read */
+         value = 0;
+         if( j+(i*SOTP_ROWS_IN_REGION) < SOTP_FIRST_ECC_CONFIG_ROW )
+            rval = sotpReadNonEccRow( dev, j+(i*SOTP_ROWS_IN_REGION), &value);
+         else
+            rval = sotpReadEccRow(dev, j+(i*SOTP_ROWS_IN_REGION), &value, 1);
+
+         if( value )
+         {
+            regionMask |= 1 << i;
+            break;
+         }
+      }
+   }
+   return (sotpLockRegion(dev, regionMask));
+}
+
+static SotpKeyStatus sotpKeySlotReadLockStatus(otp_hw_cmn_t *dev, u32 section)
+{
+   u32 startRegion;
+   int i;
+
+   /* perform checks of input params */
+   if ((section < SOTP_MIN_KEYSLOT) || (section > SOTP_MAX_KEYSLOT))
+      return SOTP_E_KEY_BADPARAM;
+
+   /* enable ecc checks (low), zero out the regs_ecc_en bits  ... then turn on cpu mode, and set regs_ecc_en to enabled */
+   /* expect Bug?  When ecc=0 then programs 0x0, Reg says that it should be set to 4'b0101 : ECC check DISABLED */
+   sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_REGS_ECC_EN_MASK));
+   sotp_hw_writel_or(dev, SOTP_OTP_PROG_CTRL_OFFSET , ( SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN | SOTP_OTP_PROG_CTRL_REGS_ECC_DIS ));
+
+   /* Determine the starting region to lock */
+   startRegion = SOTP_FIRST_KEYSLOT_REGION + ((section - SOTP_MIN_KEYSLOT) * SOTP_REGIONS_IN_KEYSLOT);
+
+   for( i=0; i<SOTP_REGIONS_IN_KEYSLOT; i++ )
+   {
+
+       /* Check to see if that region is locked */
+       if (sotp_hw_readl(dev, SOTP_OTP_RD_LOCK_OFFSET) & ( 0x1 << startRegion ) )
+          return SOTP_E_ROW_READ_LOCK;
+
+       /* Go to next region in keyslot */
+       startRegion++;
+   }
+
+   /* turn off cpu mode */
+   sotp_hw_writel_and(dev, SOTP_OTP_PROG_CTRL_OFFSET , (~SOTP_OTP_PROG_CTRL_OTP_CPU_MODE_EN));
+
+   return 0;
+}
+
+/*  *********************************************************************
+    *  extern SotpKeyStatus sotpWriteKeyslotData(u32 section, u32 *pSrc, u32 len)
+    *  
+    *  Description - Used during manufacturing to fuse a security credential
+    *                into SOTP
+    *
+    *  Input parameters: 
+    *     section - There are 7 locations called sections that can hold 
+    *               up to 256 bits of key information. (7 =< section =< 13)
+    *     pSrc    - pointer to the buffer containing the key (chopped 
+    *               up into 32 bit words)
+    *     len     - The number of 32 bit words in the key (len =< 8)
+    *     
+    *  Return value:
+    *     SOTP_S_KEY_SUCCESS - The function has completed successfully
+    *     SOTP_E_KEY_BADPARAM- The function recieved a bad input parameter
+    *     SOTP_E_KEY_OVERRUN - The function ran out of rows within a section
+    *                          before the entire key and crc was fused
+    *     SOTP_E_KEY_TIMEOUT - The function experienced unexpected FSM 
+    *                          timeout from the SOTP block 
+    *     SOTP_E_KEY_ERROR   - The function experienced unexpected register 
+    *                          ret value from SOTP block 
+    *
+    ********************************************************************* */
+static SotpKeyStatus sotpWriteKeyslotData(otp_hw_cmn_t *dev,
+ 					u32 section, 
+					u32 *pSrc, 
+					u32 len)
+{
+   u32 startRow, row, calcCrc, startRegion, fuse_lock, read_lock;
+   u32 rowData = 0;
+   u32 i = 0;
+   SotpKeyStatus rval    = SOTP_E_KEY_BADPARAM;
+   SotpRowStatus rowRval = SOTP_S_ROW_SUCCESS;
+
+   SOTP_DBG("%s: section:%d bufp:%px len:%d\n", __FUNCTION__, section, pSrc, len);
+
+   /* perform checks of input params */
+   if ((pSrc == NULL) || (len == 0) || (len > SOTP_MAX_KEYLEN))
+      return rval;
+
+   if ((section < SOTP_MIN_KEYSLOT) || (section > SOTP_MAX_KEYSLOT))
+   {
+      SOTP_ERR_PRINT("%s: keyslot section:%d out of bound! Min:%d Max:%d\n", __FUNCTION__, section, SOTP_MIN_KEYSLOT, SOTP_MAX_KEYSLOT);
+      return rval;
+   }
+
+   /* Calculate the crc that is to be stored into the key slot */
+   calcCrc = getCrc32((u8 *)pSrc, (len*4), 0 );
+
+   /* Determine the starting row to fuse */
+   startRow = ((section - SOTP_MIN_KEYSLOT) * SOTP_ROWS_IN_KEYSLOT) + SOTP_FIRST_KEYSLOT_ROW;
+
+   /* Determine starting region */
+   startRegion = startRow / SOTP_ROWS_IN_REGION;
+
+   /* Make sure that the regions we are writing to are not read-locked or fuse-locked */
+   for( i = startRegion; i < startRegion + SOTP_REGIONS_IN_KEYSLOT; i++ )
+   {
+      fuse_lock = sotpIsRegionFuseLocked(dev, i);
+      read_lock = sotpRegionReadLockStatus(dev, i);
+      if( fuse_lock || read_lock )
+      {
+         SOTP_ERR_PRINT("%s: section:%d region:%d %s_locked! Abort keyslot programming!\n", __FUNCTION__, section, i, (fuse_lock?"fuse":"read"));
+         return rval;
+      }
+   }
+
+   /* Make sure that entire keyslot is empty before attempting to program */
+   for ( row = startRow ; row < (startRow + SOTP_ROWS_IN_KEYSLOT); row++) {
+      /* TODO: Add counter to allow certain amount of failiures ( 3 redundant ) */
+      rowRval = sotpReadEccRow(dev, row, &rowData, 0);
+      if( rowRval != SOTP_S_ROW_SUCCESS )
+      {
+         SOTP_ERR_PRINT("%s: Cant read keyslot section:%d row:%d! Abort keyslot programming!\n", __FUNCTION__, section, row);
+         return rval;
+      }
+
+      if(rowData)
+      {
+         SOTP_ERR_PRINT("%s: keyslot section:%d row:%d not empty! Abort keyslot programming!\n", __FUNCTION__, section, row);
+         return rval;
+      }
+   }
+
+   /* Start fusing the key and CRC */
+   for ( row = startRow, i = 0 ; row < (startRow + SOTP_ROWS_IN_KEYSLOT); row++)
+   {
+	_TR(pSrc[i]);
+      if (i < len)
+         rowRval = sotpWriteEccRow(dev, row, pSrc[i], 0); /* currently writing the key */
+
+      if (i == len) {
+	 _TR(calcCrc);
+         rowRval = sotpWriteEccRow(dev, row, calcCrc, 0); /* write the crc */
+      }
+	_TR(pSrc[i]);
+      /* See if it was successful */
+      switch(rowRval)
+      {
+
+         case SOTP_S_ROW_SUCCESS:
+         {
+            /* Check the integrity of the row just fused */
+            rowRval = sotpReadEccRow(dev, row, &rowData, 0);
+
+            switch(rowRval)
+            {
+               case SOTP_S_ROW_SUCCESS: 
+               case SOTP_S_ROW_ECC_COR:
+               {
+                  if (i < len)
+                  {
+                     if (pSrc[i] == rowData)
+                        i++;
+                     else
+                     {
+                        SOTP_ERR_PRINT("\nWritten and read data didn't match within row %d. Section %d is unusable\n", row, section);
+                        return SOTP_E_KEY_ERROR;
+                     }
+                  }
+                  else
+                  {
+                     if (calcCrc == rowData) {
+#ifdef DEBUG_SOTP
+			return SOTP_S_ROW_SUCCESS;
+#else
+                        return(sotpLockSecKeyFuse(dev, section)); /* key and crc fused. Lock section from further writes */
+#endif 
+                     }
+                     else
+                     {
+                        SOTP_ERR_PRINT("\nCalculated and read crc didn't match within row %d. Section %d is unusable\n", row, section);
+                        return SOTP_E_KEY_ERROR;
+                     }
+                  }
+
+                  break;
+               }
+
+               case SOTP_E_ROW_ECC_DET:
+               {
+                  /* row has 2 or more uncorrectable bits. Mark the row as failed */
+                  if ((rowRval = sotpFuseSecKeyRowFailBits(dev, row)) != SOTP_S_ROW_SUCCESS)
+                  {
+                     SOTP_ERR_PRINT("\nFailed to fuse fail bits within row %d. Section %d is unusable\n", row, section);
+                     return SOTP_E_KEY_ERROR;
+                  }
+                  break;
+               }
+
+               case SOTP_E_ROW_FAIL_SET:
+               {
+                  SOTP_ERR_PRINT("\nFail bits have previously been fused within row %d. Section %d is unusable\n", row, section);
+                  return SOTP_E_KEY_ERROR;
+                  break;
+               }
+
+               case SOTP_E_ROW_READ_LOCK:
+               {
+                  SOTP_DBG("\nRow %d is locked from reading. Cannot verify. Section %d may be unusable\n", row, section);
+                  return SOTP_E_KEY_ERROR;
+                  break;
+               }
+
+               default:
+               {
+                  SOTP_ERR_PRINT("\nUnknown condition in reading row %d. Section %d may be unusable\n", row, section);
+                  return SOTP_E_KEY_ERROR;
+                  break;
+               }
+            }
+
+            break;
+         }
+
+         case SOTP_E_ROW_FUSE_LOCK:
+         {
+            SOTP_ERR_PRINT("\nRow %d is locked from fusing. Section %d may be unusable\n", row, section);
+            return SOTP_E_KEY_ERROR;
+            break;
+         }
+
+         case SOTP_E_ROW_TIMEOUT:
+         {
+            SOTP_ERR_PRINT("\nUnexpected SOTP block timeout while fusing row %d. Section %d may be unusable\n", row, section);
+            return SOTP_E_KEY_ERROR;
+            break;
+         }
+
+         case SOTP_E_ROW_ERROR:
+         default:
+         {
+            SOTP_ERR_PRINT("\nUnknown condition while fusing row %d. Section %d may be unusable\n", row, section);
+            return SOTP_E_KEY_ERROR;
+            break;
+         }
+
+      }
+   }
+
+   SOTP_ERR_PRINT("\nRan out of rows before fusing entire key and crc. Section %d is unusable \n", section);
+   return SOTP_E_KEY_OVERRUN;
+}
+
+__weak otp_hw_cmn_err_t sotp_hw_read(otp_hw_cmn_t *dev, 
+				u32 addr,
+				otp_hw_cmn_row_conf_t *conf, 
+				u32* data,
+				u32 size)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL;
+	int res = 0;
+
+	if (conf && conf->addr_type == OTP_HW_CMN_ROW_ADDR_ROW) {
+    		res = sotpReadEccRow(dev, addr, (u32*)data, 
+			conf->op_type == OTP_HW_CMN_CTL_OTPCMD_ECC? 0:1);
+    		if (res != SOTP_S_KEY_SUCCESS && res != SOTP_S_ROW_ECC_COR ) {
+			goto err;
+		}
+	} else {
+		u32 sect = 0;
+		if (row2sect(addr, &sect)) {
+			rc = OTP_HW_CMN_ERR_UNSP;
+			goto err;
+		}	
+    		res = sotpReadKeyslotData(dev, sect, (u32*)data, size/sizeof(u32));
+    		if (res != SOTP_S_KEY_SUCCESS && res != SOTP_S_ROW_ECC_COR ) {
+			goto err;
+		}
+	}
+	rc = OTP_HW_CMN_OK;
+err:
+	return rc;
+}
+
+static otp_hw_cmn_err_t dev_status(otp_hw_cmn_t *dev,
+			u32 sect,
+			otp_hw_cmn_status_t status,
+			u32* res)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL;
+        u32 perm_mask  = sotp_hw_readl(dev, SOTP_PERM_OFFSET); 
+	if ( status & OTP_HW_CMN_STATUS_ROW_DATA_VALID )  {
+		u32 tmp[8];
+		if (sotpReadKeyslotData(dev, sect, tmp, 8) != SOTP_S_KEY_SUCCESS || 
+			sotpKeySlotReadLockStatus(dev, sect) == SOTP_E_ROW_READ_LOCK) {
+			status &= ~OTP_HW_CMN_STATUS_ROW_DATA_VALID;
+		_TR(status);	
+		}
+	}
+	if (status & OTP_HW_CMN_STATUS_ROW_W_LOCKED) {
+		u32 regn_range[2];
+		if ( sect2regn(sect, regn_range) ) {
+			rc = OTP_HW_CMN_ERR_UNSP;
+			goto err;
+		}
+    		if(sotpIsRegionFuseLocked(dev, sect) != SOTP_E_ROW_FUSE_LOCK) {
+			status &= ~OTP_HW_CMN_STATUS_ROW_W_LOCKED;
+		}
+	}
+	if ( status & OTP_HW_CMN_STATUS_ROW_RD_LOCKED )  {
+    		if (sotpKeySlotReadLockStatus(dev, sect) != SOTP_E_ROW_READ_LOCK) { 
+			status &= ~OTP_HW_CMN_STATUS_ROW_RD_LOCKED;
+		}
+	}
+	/* permission register access status*/
+	if ( !(perm_mask & SOTP_PERM_NSEC_R) ) {
+   		status &= ~OTP_HW_CMN_STATUS_NSRD_PAC_LOCKED;
+	}
+	if ( !(perm_mask & SOTP_PERM_SEC_R) ) {
+   		status &= ~OTP_HW_CMN_STATUS_SRD_PAC_LOCKED;
+	}
+	if ( !(perm_mask & SOTP_PERM_NSEC_W) ) {
+		status &= ~OTP_HW_CMN_STATUS_NSW_PAC_LOCKED;
+	}
+	if ( !( perm_mask & SOTP_PERM_SEC_W) ) {
+		status &= ~OTP_HW_CMN_STATUS_SW_PAC_LOCKED;
+	}
+	if ( !(perm_mask & (SOTP_PERM_BLK_SEC_R<<SOTP_PERM_BLK_SHIFT) )) {
+		status &= ~OTP_HW_CMN_STATUS_SRD_LOCKED;
+	}
+	if ( !(perm_mask & (SOTP_PERM_BLK_NSEC_R<<SOTP_PERM_BLK_SHIFT)	)) {
+   		status &=  ~OTP_HW_CMN_STATUS_NSRD_LOCKED;
+	}
+	if ( !(perm_mask & (SOTP_PERM_BLK_SEC_W<<SOTP_PERM_BLK_SHIFT) )) {
+   		status &= ~OTP_HW_CMN_STATUS_SW_LOCKED;
+	}
+
+	if ( !(perm_mask & (SOTP_PERM_BLK_NSEC_W<<SOTP_PERM_BLK_SHIFT) )) {
+		status &= ~OTP_HW_CMN_STATUS_NSW_LOCKED;
+	}
+	*res = status;
+	rc = OTP_HW_CMN_OK;
+	
+err:
+	return rc;
+}
+
+static otp_hw_cmn_err_t  sotp_hw_lock(otp_hw_cmn_t *dev, 
+				u32 sect,
+				otp_hw_cmn_perm_t perm, 
+				u32 clear_lock) 
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_UNSP;
+	u32 perm_mask = 0;
+	if (perm & OTP_HW_CMN_CTL_LOCK_ALL) {
+		if (clear_lock) {
+                        SOTP_DBG("%s:UNLOCKING ALL!\n", __FUNCTION__);
+			sotp_hw_writel(dev, SOTP_PERM_OFFSET, SOTP_PERM_ENABLE_ALL);
+		} else {
+                        SOTP_DBG("%s:LOCKING ALL!\n", __FUNCTION__);
+			int i;
+			for (i = 0; i <= SOTP_MIN_KEYSLOT; i++) {
+    				if (readLockKeyslot(dev, i) != SOTP_S_KEY_SUCCESS) { 
+					rc = OTP_HW_CMN_ERR_FAIL;
+					goto err;
+				}
+			}
+			sotp_hw_writel(dev, SOTP_PERM_OFFSET, SOTP_PERM_DISABLE_ALL);
+		}
+		return OTP_HW_CMN_OK;
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_S) {
+		if (clear_lock) {
+                        SOTP_DBG("%s:UNLOCKING SEC!\n", __FUNCTION__);
+			sotp_hw_writel(dev, SOTP_PERM_OFFSET, SOTP_PERM_ALLOW_SECURE_ACCESS_ONLY);
+		} else {
+                        SOTP_DBG("%s:LOCKING SEC!\n", __FUNCTION__);
+			sotp_hw_writel(dev, SOTP_PERM_OFFSET, SOTP_PERM_DISABLE_SECURE_ACCESS);
+		}
+		return OTP_HW_CMN_OK;
+	}
+
+	if (perm & OTP_HW_CMN_CTL_LOCK_NS || perm & OTP_HW_CMN_CTL_LOCK_NS_PROV) {
+		if (clear_lock) {
+                        SOTP_DBG("%s:UNLOCKING NONSEC BLK!\n", __FUNCTION__);
+			sotp_hw_writel(dev, SOTP_PERM_OFFSET, SOTP_PERM_ALLOW_NONSEC_BLK_ACCESS);
+		} else {
+                        SOTP_DBG("%s:LOCKING NONSEC!\n", __FUNCTION__);
+			sotp_hw_writel_and(dev, SOTP_PERM_OFFSET, 
+                           ((~SOTP_PERM_ALLOW_NONSEC_ACCESS_ONLY)&0xff));
+		}
+		if( perm & OTP_HW_CMN_CTL_LOCK_NS_PROV ) {
+			sotpReadLockNonEmptyRegions(dev);
+		}
+		return OTP_HW_CMN_OK;
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_ROW_RD) {
+                if (!clear_lock) {
+    			if (readLockKeyslot(dev, sect) != SOTP_S_KEY_SUCCESS) { 
+				rc = OTP_HW_CMN_ERR_FAIL;
+				goto err;
+			}
+		}
+	} 
+	/* permission register access status*/
+  	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_NSRD) {
+		perm_mask |= SOTP_PERM_NSEC_R;
+	}
+   	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_SRD) {
+		perm_mask |= SOTP_PERM_SEC_R;  
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_NSW) {
+		perm_mask |= SOTP_PERM_NSEC_W;
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_PAC_SW) {
+		perm_mask |= SOTP_PERM_SEC_W;
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_SRD) {
+		perm_mask |= (SOTP_PERM_BLK_SEC_R<<SOTP_PERM_BLK_SHIFT);
+	}
+   	if (perm & OTP_HW_CMN_CTL_LOCK_NSRD) {
+		perm_mask |= (SOTP_PERM_BLK_NSEC_R<<SOTP_PERM_BLK_SHIFT);
+	}
+	if (perm & OTP_HW_CMN_CTL_LOCK_SW) {
+		perm_mask |= (SOTP_PERM_BLK_SEC_W<<SOTP_PERM_BLK_SHIFT);
+	}
+
+	if (perm & OTP_HW_CMN_CTL_LOCK_NSW) {
+		perm_mask |= (SOTP_PERM_BLK_NSEC_W<<SOTP_PERM_BLK_SHIFT);
+	}
+	if (perm_mask) {
+               if (clear_lock) {
+                       sotp_hw_writel_and(dev, SOTP_PERM_OFFSET, (~perm_mask));
+               } 
+               sotp_hw_writel(dev, SOTP_PERM_OFFSET, perm_mask);
+               rc = OTP_HW_CMN_OK;
+	}
+err:
+	return rc;
+}
+
+__weak otp_hw_cmn_err_t  sotp_hw_write(otp_hw_cmn_t *dev, 
+				u32 addr,
+				otp_hw_cmn_row_conf_t *conf, 
+				const u32* data,
+				u32 size)
+{
+	otp_hw_cmn_err_t rc = OTP_HW_CMN_ERR_FAIL;
+	if (conf && conf->addr_type == OTP_HW_CMN_ROW_ADDR_ROW) {
+		u32 raw_write = 1;
+		if (conf->op_type == OTP_HW_CMN_CTL_OTPCMD_ECC) {
+			u32 ecc = 0;
+			if (sotpReadEccRow(dev, addr, &ecc, 0) != SOTP_S_ROW_SUCCESS) {
+				goto err;
+			}
+			if (ecc) {
+				rc  = OTP_HW_CMN_ERR_DATA_ECC;
+				SOTP_ERR_PRINT("%s: Row already has valid data! Not writing SOTP row\n", 
+					__FUNCTION__);
+				goto err;
+			}
+			raw_write = 0;
+		}
+    		if ( sotpWriteEccRow(dev, addr, *(u32*)data, raw_write) != SOTP_S_ROW_SUCCESS) {
+			goto err; 		
+		}
+	} else {
+		u32 sect = 0;
+		if (row2sect(addr, &sect)) {
+			goto err;
+		}	
+    		if (sotpWriteKeyslotData(dev, sect, (u32*)data, 
+			size/sizeof(u32)) != SOTP_S_KEY_SUCCESS) {
+			goto err;
+		}
+	}
+	/* Non ecc raw row write
+ 	*	case OTP_HW_CMN_ADDR_TYPE_ROW: {
+    		if ( sotpWriteEccRow(dev, addr, *(u32*)data, 1) != SOTP_S_ROW_SUCCESS) {
+			goto err; 		
+		}
+		break;
+	}*/
+	rc = OTP_HW_CMN_OK;
+err:
+	return rc;
+}
+
+__weak otp_hw_cmn_err_t sotp_hw_ctl(otp_hw_cmn_t *dev, 
+			const otp_hw_cmn_ctl_cmd_t *cmd,
+			u32* res)
+{
+	otp_hw_cmn_err_t  rc = OTP_HW_CMN_ERR_FAIL;
+	u32 clear_lock = 0;
+	switch((u32)cmd->ctl) {
+   		case OTP_HW_CMN_CTL_CONF:
+			memcpy(&dev->row_conf, 
+				(otp_hw_cmn_row_conf_t*)cmd->data, 
+				cmd->size);
+
+			dev->ctl_cmd.ctl |= cmd->ctl;
+			rc = OTP_HW_CMN_OK;
+			break;
+   		case (~((u32)OTP_HW_CMN_CTL_CONF)):
+			dev->ctl_cmd.ctl &= ~cmd->ctl;
+			rc = OTP_HW_CMN_OK;
+			break;
+		case	OTP_HW_CMN_CTL_STATUS: {
+			u32 sect;
+			otp_hw_ctl_data_t* ctl_data = (otp_hw_ctl_data_t*)cmd->data;
+			_TR(ctl_data->addr);
+			if (row2sect(ctl_data->addr, &sect)) {
+				rc = OTP_HW_CMN_ERR_UNSP;
+				return rc;
+			}
+  			rc = dev_status(dev, sect, 
+				ctl_data->perm, res);
+			break;
+		}
+		case	OTP_HW_CMN_CTL_UNLOCK: 
+			clear_lock = 1;
+		case	OTP_HW_CMN_CTL_LOCK: {
+			u32 sect;
+			otp_hw_ctl_data_t* ctl_data = (otp_hw_ctl_data_t*)cmd->data;	
+			if (row2sect(ctl_data->addr, &sect)) {
+				rc = OTP_HW_CMN_ERR_UNSP;
+				return rc;
+			}
+  			rc = sotp_hw_lock(dev, sect, ctl_data->perm, clear_lock);
+			break;
+		}
+		default:
+			rc = OTP_HW_CMN_ERR_UNSP;
+			break;
+	}
+	return  rc;
+}
+
+static  otp_hw_cmn_err_t sotp_hw_write_dev(otp_hw_cmn_t* dev, 
+		u32 addr,
+		const u32* data,
+		u32 size)
+{
+        otp_hw_cmn_row_t *row;
+	otp_hw_cmn_row_conf_t *cfg;  
+	otp_hw_cmn_err_t  rc = OTP_HW_CMN_ERR_FAIL;
+	rc = lookup_row(dev, addr, &row);
+
+	if( dev->ctl_cmd.ctl&OTP_HW_CMN_CTL_CONF )
+		cfg = &dev->row_conf;
+	else if (rc == 0)
+		cfg = &row->conf;
+	else
+		cfg = NULL;
+
+	SOTP_DBG("%s: ctl_cmd.ctl:%d rc:%d\n", __FUNCTION__, dev->ctl_cmd.ctl, rc);
+
+	return dev->write_ex? 
+		dev->write_ex(dev, addr, cfg, data, size) : OTP_HW_CMN_ERR_UNSP;
+}
+
+static otp_hw_cmn_err_t sotp_hw_read_dev(otp_hw_cmn_t *dev,
+			u32 addr,
+			u32 *data,
+			u32 size)
+{
+        otp_hw_cmn_row_t *row;
+	otp_hw_cmn_row_conf_t *cfg;  
+	otp_hw_cmn_err_t  rc = OTP_HW_CMN_ERR_FAIL;
+	rc = lookup_row(dev, addr, &row);
+
+	if( dev->ctl_cmd.ctl&OTP_HW_CMN_CTL_CONF )
+		cfg = &dev->row_conf;
+	else if (rc == 0)
+		cfg = &row->conf;
+	else
+		cfg = NULL;
+
+	SOTP_DBG("%s: ctl_cmd.ctl:%d rc:%d\n", __FUNCTION__, dev->ctl_cmd.ctl, rc);
+
+	return dev->read_ex?
+		dev->read_ex(dev, addr, cfg, data, size):OTP_HW_CMN_ERR_UNSP;
+
+}
+
+__weak otp_hw_cmn_err_t sotp_hw_dev_mmap(otp_hw_cmn_t* dev)
+{
+	dev->mm = SOTP_BASE;
+	return OTP_HW_CMN_OK;
+}
+
+__weak otp_hw_cmn_err_t sotp_hw_init (otp_hw_cmn_t *dev)
+{
+	int i = 0;
+	int *m = sectn_map;
+	DEFINE_SOTP_MAP_ROW_INITLR(rows);
+	if (sotp_hw_dev_mmap(dev)) {
+		return OTP_HW_CMN_ERR_FAIL;
+	}
+	dev->rows = rows;
+	dev->row_max = sizeof(rows)/sizeof(otp_hw_cmn_row_t);
+	/* map for a section to a row count */	
+	for (i = 1 ; i < SOTP_SECT_ID_MAX; i++) {
+		 m[i] += m[i-1];
+	}
+	return OTP_HW_CMN_OK;
+}
+
+otp_hw_cmn_err_t sotp_hw_cmn_init (otp_hw_cmn_t *dev)
+{
+	if (sotp_hw_init(dev)) {
+		return OTP_HW_CMN_ERR_FAIL;
+	}
+	dev->write_ex = sotp_hw_write;
+	dev->write = sotp_hw_write_dev;
+	dev->read_ex = sotp_hw_read;
+	dev->read = sotp_hw_read_dev;
+	dev->ctl  = sotp_hw_ctl;
+	return OTP_HW_CMN_OK;
+}
+
+
diff --git a/arch/arm/mach-bcmbca/otp_tk/Makefile b/arch/arm/mach-bcmbca/otp_tk/Makefile
new file mode 100644
index 0000000000..fd9425ced2
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp_tk/Makefile
@@ -0,0 +1 @@
+obj-y += sec_tk.o tk_ks.o
diff --git a/arch/arm/mach-bcmbca/otp_tk/sec_tk.c b/arch/arm/mach-bcmbca/otp_tk/sec_tk.c
new file mode 100644
index 0000000000..13bf807d8c
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp_tk/sec_tk.c
@@ -0,0 +1,265 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2020 Broadcom Ltd.
+ */
+#include <common.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include "linux/printk.h"
+#include <asm/arch/misc.h>
+#include "bcm_otp.h"
+#include <u-boot/rsa.h>
+#include <u-boot/sha256.h>
+#include <uboot_aes.h>
+#include "bcm_secure.h"
+#include "tk_ks.h"
+
+//#define DRY_RUN
+
+#define	TM_SAMPLE_RATE 10
+
+static char _get_char(void)
+{
+	return tstc() ? getc():'\0';
+}
+
+static inline int sec_tk_check_abort(int sec)
+{
+    char str[8],ch;
+    sec *= TM_SAMPLE_RATE;
+    while (sec > 0) {
+	ch = _get_char();
+        if (ch == 'c' || ch == 'C') {
+            break;
+        }
+	if (!(sec%TM_SAMPLE_RATE)) {
+        	sprintf(str,"%3d",sec/TM_SAMPLE_RATE);
+	}
+       	puts(str);
+        putc('\r');
+        memset(str, 0, 8);
+        mdelay(1000/TM_SAMPLE_RATE);
+        sec--;
+    }
+    return sec;
+}
+
+
+static inline void ntohl_array(u32* a, u32 length) 
+{
+    int i;
+    for (i = 0;i < length; i++)  {
+         a[i] = ntohl(a[i]);
+    }
+}
+
+
+static int sec_tk_fuse_verify(otp_map_feat_t id, 
+			const u8* data, 
+			u32 size)
+{
+	u32	*data_verify = NULL,
+		size_verify = 0;
+	otp_map_cmn_err_t rc = OTP_MAP_CMN_OK; 
+	rc = bcm_otp_read(id, &data_verify, &size_verify);
+	if (rc) {
+		if (rc != OTP_HW_CMN_ERR_KEY_EMPTY) {
+			goto err;
+		}
+		rc = OTP_MAP_CMN_OK;
+	}
+#ifndef  DRY_RUN 
+	if (!data || !(*data)) {
+		printf("EINV\n");
+		goto err;
+	}
+	rc = bcm_otp_write(id, data, size);
+	if (rc) {
+		printf("EFSD\n");
+		goto err;
+	}
+#else 
+	do{
+		int i;
+		printf("Fusing with size %d data: \n\t",size);
+		for (i = 0; i < size; i++) {
+			printf(" 0x%x ",data[i]);
+		}
+		printf("\n");
+	}while(0);
+#endif
+err:
+	return rc;
+}
+
+static inline int sec_tk_commit_req(ks_req_state_t req_state, 
+                                bcm_sec_state_t cur_state)
+{
+        int res, rc = 0;
+	
+        switch(cur_state) {
+                case SEC_STATE_UNSEC:
+                        if (req_state == KS_REQ_TRANSIT_FLD || 
+                                req_state == KS_REQ_TRANSIT_MFG){
+                                printf("MFG\n");
+				u32 val = 0x1, size = 4;
+				if (sec_tk_fuse_verify(OTP_MAP_BRCM_BTRM_BOOT_ENABLE, &val, size )) {
+					goto err;
+				}
+				val = 0x7;
+				if (sec_tk_fuse_verify(OTP_MAP_CUST_BTRM_BOOT_ENABLE, &val, size )) {
+					goto err;
+				}
+                        }
+                        break;
+                case SEC_STATE_GEN3_MFG:
+                        if (req_state == KS_REQ_TRANSIT_FLD) {
+                                int res;
+                        	/*program otp bits accordingly */
+                                u8 ek_iv[KS_AES_128_CBC_SZ+KS_AES_128_CBC_SZ],
+                                                hash[KS_HASH_SZ]; 
+                                u32 mid;
+
+                                if (ks_get_data_info(KS_DATA_TYPE_KEY_AES_CBC_128_EK, 
+                                        KS_DATA_STATE_FLD_ENCR, ek_iv) != KS_ERR_SUCC) {
+                                        goto err;
+                                }
+                                if (ks_get_data_info(KS_DATA_TYPE_KEY_AES_CBC_128_IV, 
+                                        KS_DATA_STATE_FLD_ENCR, ek_iv+KS_AES_128_CBC_SZ) != KS_ERR_SUCC) {
+                                        goto err;
+                                }
+                                if (ks_get_data_info(KS_DATA_TYPE_HASH, 
+                                                KS_DATA_STATE_RAW, hash) != KS_ERR_SUCC) {
+                                        goto err;
+                                }
+                                if (ks_get_data_info(KS_DATA_TYPE_MID, 
+                                        KS_DATA_STATE_RAW, &mid) != KS_ERR_SUCC) {
+                                        goto err;
+                                }
+                                printf("FLD\n");
+				/*
+                                 since sotp interface dealing with 32 bit integers - assumption is
+                                 that raw byte data from keystore are always honoring big endian 
+                                */
+				mid = ntohl(mid);
+                                ntohl_array((u32*)ek_iv,(KS_AES_128_CBC_SZ*2)/sizeof(u32)); 
+                                ntohl_array((u32*)hash,(KS_HASH_SZ)/sizeof(u32)); 
+				rc = sec_tk_fuse_verify(OTP_MAP_CUST_MFG_MRKTID, &mid, sizeof(u32));
+				if (rc) {
+                                        goto err;
+				}
+				rc = sec_tk_fuse_verify(SOTP_MAP_FLD_HMID, hash, KS_HASH_SZ);
+				if (rc) {
+                                        goto err;
+				}
+				rc = sec_tk_fuse_verify(SOTP_MAP_FLD_ROE, ek_iv, KS_AES_128_CBC_SZ*2);
+				if (rc) {
+                                        goto err;
+				}
+                        }
+                        break;
+                default:
+                        goto err;
+        }
+        return 0;
+err:    
+        return -1;
+}
+
+
+static inline int sec_tk_do_req(u32 sec_arch,
+				bcm_sec_state_t sec_state,
+                                ks_req_info_t *req_info)
+{
+	/*
+        if (ks_get_req_info(&req_info) != KS_ERR_SUCC) {
+                goto err;
+        }*/
+        
+        switch(sec_arch) {
+                case SEC_ARCH_GEN3:
+                        sec_tk_commit_req(req_info->state, sec_state);
+                        break;
+                case SEC_ARCH_GEN2:
+                case SEC_ARCH_NONE:
+                case SEC_ARCH_GEN1:
+                default:
+                        goto err;
+        }
+        return 0;
+err:
+        printf("EREQ\n");
+        return -1;
+}
+
+static int sec_tk_allow_req(bcm_sec_state_t sec_state, 
+                        ks_req_state_t req_state)
+{
+        switch (sec_state) {
+                case SEC_STATE_UNSEC:
+                        if (req_state == KS_REQ_TRANSIT_MFG ||
+                                req_state == KS_REQ_TRANSIT_FLD) {
+                                return 1;       
+                        }
+                        break;
+                case SEC_STATE_GEN3_MFG:
+                        if (req_state == KS_REQ_TRANSIT_FLD) {
+                                return 1;       
+                        }
+                        break;
+                default:
+                        break;
+        }
+        return 0; 
+}
+
+int sec_tk()
+{	
+	char* msg = NULL;
+	u8* aes_key;
+        ks_req_info_t req_info;
+	bcm_sec_state_t state = bcm_sec()->state;
+        printf("SECE\n");
+        printf("GEN3\n");
+	bcm_sec_get_active_aes_key(&aes_key);
+        if (ks_init(state,
+		SEC_ARCH_GEN3, 
+		bcm_sec_get_active_pub_key(),
+		aes_key) != KS_ERR_SUCC) {
+                goto err;
+        }
+        if (ks_get_req_info(&req_info) != KS_ERR_SUCC) {
+                goto err;
+        }
+
+        if (!sec_tk_allow_req(state, req_info.state)) {
+                printf("FUSD\n");
+                goto done;
+        }
+        switch (state) {
+                case SEC_STATE_UNSEC:
+                        msg = "NSEC\n";
+                        break;
+                case SEC_STATE_GEN3_MFG:
+                        msg = "MFG\n";
+                        break;
+                default:
+                        goto err;
+        }
+       	printf(msg);
+        printf("ABT?\n");
+        if (sec_tk_check_abort(req_info.abort_delay)) {
+                
+                printf("CNCL\n");
+                goto done;
+        }
+        if (sec_tk_do_req(SEC_ARCH_GEN3, state ,&req_info) == 0) {
+                printf("POR!\n");
+        }
+done:
+        return 0;
+err:
+        printf("SERR\n"); 
+        return -1;
+}
+
diff --git a/arch/arm/mach-bcmbca/otp_tk/tk_ks.c b/arch/arm/mach-bcmbca/otp_tk/tk_ks.c
new file mode 100644
index 0000000000..27b475f8cd
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp_tk/tk_ks.c
@@ -0,0 +1,331 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2020 Broadcom Ltd.
+ */
+#include <common.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include "linux/printk.h"
+#include <asm/arch/misc.h>
+#include <asm/byteorder.h>
+#include <asm/sections.h>
+#include <linux/errno.h>
+#include <asm/unaligned.h>
+#include <malloc.h>
+#include <u-boot/rsa.h>
+#include "u-boot/rsa-mod-exp.h"
+#include <u-boot/sha256.h>
+#include <uboot_aes.h>
+#include <fdtdec.h>
+#include "bcm_secure.h"
+#include "tk_ks.h"
+
+enum ks_obj_state {
+        KS_OBJ_INACTIVE = 0,
+        KS_OBJ_INVALID = -1,
+        KS_OBJ_OK = 1
+};
+
+static struct ksobj {
+        ks_t *ks;
+        u32 ks_sz;
+        u32 sec_state;
+        enum ks_obj_state state;
+        /* data buffer allocated/set in gen_info call*/
+        void* mem;
+	u8 *ek;
+	u8 *pub;
+} ks_obj;
+
+static u8 keystore[KS_MAX_SZ] __attribute__((section(".data"))) ;
+
+
+static inline int authenticate(const u8* sig,
+			u32 size, 
+			const u8* pub_key)
+{
+	struct image_sign_info im;
+	im.checksum = image_get_checksum_algo("sha256,");
+	if (bcm_sec_rsa_verify(sig + KS_SIG_SIZE, size , sig, KS_SIG_SIZE, pub_key, &im )) {
+		return -1;
+	}
+	return 0;
+}
+
+/*in-place decrypt */
+static inline void  aes_cbc128_decrypt(u32 *txt,
+                        u32 size, u8 *key, u8 *iv) 
+{
+	bcm_sec_aes_cbc128((u8*)key, (u8*)iv, (u8*)txt, size, 0);
+}
+
+/*
+ *
+ *	KS - short for key_store 
+ *
+ * */
+static inline u32 get_crc32(u8 *v, u32 size, u32 crc)
+{
+     	if (crc == 0) {
+		crc = 0xffffffff;
+     	}
+	/* for this implementation chosen no complement crc32 as exepcted by crc calc for 
+ 	* sko object
+ 	* */
+	return  crc32_no_comp(crc, v, size);
+}
+
+
+
+
+
+static inline ks_err_t ks_type2size(ks_data_type_t data_type, u32 *size)
+{
+        u32 sz;
+        switch(data_type) {
+                case KS_DATA_TYPE_KEY_AES_CBC_128_IV:
+                case KS_DATA_TYPE_KEY_AES_CBC_128_EK:
+                        sz = KS_AES_128_CBC_SZ;
+                        break;  
+                case KS_DATA_TYPE_KEY_AES_CBC_256_EK:
+                case KS_DATA_TYPE_KEY_AES_CBC_256_IV:
+                        sz = KS_AES_256_CBC_SZ;
+                        break;  
+                case KS_DATA_TYPE_RSA_PUB:
+                case KS_DATA_TYPE_HASH:
+                        sz = KS_HASH_SZ;
+                        break;  
+                case KS_DATA_TYPE_MID:
+                case KS_DATA_TYPE_OID:
+                        sz = KS_MID_SZ;
+                        break;  
+                default:
+                        return  KS_ERR_INVALID;
+        }
+        *size = sz;
+        return  KS_ERR_SUCC;
+}
+
+static ks_err_t ks_verify(ks_t* ks,
+			u32 curr_sec_state,
+			const u8* pub_key
+                        /*Sizeof of the object without signature*/
+                       )
+{
+        ks_req_state_t sec_state_req = ks->hdr.req_info.state;
+        switch(sec_state_req) {
+                case KS_REQ_TRANSIT_FLD: 
+                        if (curr_sec_state == SEC_STATE_GEN3_MFG) {
+                                if (authenticate(ks->key.sig, 
+					ks->hdr.info_size - (sizeof(ks->key.crc) + KS_SIG_SIZE), 
+					pub_key)) {
+					goto err_fatal;
+				}
+                                printf("KATH\n");
+                        } else if (curr_sec_state == SEC_STATE_UNSEC) {
+                                if (ks->hdr.info_size < sizeof(u32) || 
+                                ks->key.crc != get_crc32(((u8*)&ks->key.crc)+sizeof(ks->key.crc), 
+                                        ks->hdr.info_size - sizeof(ks->key.crc), 0)) {
+                                                                        goto err;
+                                }
+                        }
+                        break;  
+                case KS_REQ_TRANSIT_MFG:
+                        if (ks->hdr.info_size != 0 || curr_sec_state != SEC_STATE_UNSEC) {
+                                goto err;
+                        }
+                        break;
+                default:
+                        goto err;
+        }
+        return  KS_ERR_SUCC;
+err:
+        printf("EVER\n");
+        return  KS_ERR_INVALID;
+err_fatal:
+	ks_reset();
+	/* destroy hang, watchdog reset*/	
+	hang();	
+}
+/* copy keystore to an internal data array; 
+ * on v7 if not copied it can be erased by
+ * BSS clean loop before int_r is called */
+void sec_tk_find_keystore()
+{
+        u8 *bdata = KS_OFFSET;
+	if (KS_IS_FDT(bdata)) {
+		bdata +=  KS_FDT_SIZE(bdata);
+	}
+	memcpy(keystore, bdata, KS_MAX_SZ);
+}
+
+/*
+        Reads and verifies key store
+*/
+ks_err_t ks_init(bcm_sec_state_t sec_state, 
+                u32 sec_arch,
+		const u8* pub_key,
+		const u8* aes_key)
+{
+        /*
+          Read flash block at offset 724*1024  
+          Verify if valid header is valid 
+        */
+        ks_hdr_t *hdr = NULL;
+        u8 *mem = NULL, *bdata = NULL;
+	printf("KINI\n");
+        /*BRKPT;*/ 
+        if (ks_obj.state  == KS_OBJ_OK) {
+                return KS_ERR_SUCC; 
+        }
+        if (ks_obj.state == KS_OBJ_INVALID) {      
+                return KS_ERR_INVALID; 
+        }
+        
+	hdr = (ks_hdr_t*)keystore;
+        if (memcmp(hdr->magic, KS_MAGIC, 
+			KS_MAGIC_SIZE)) {
+                printf("EMGC\n");
+                goto err;
+        }
+        if (hdr->crc != get_crc32(keystore, 
+                        sizeof(ks_hdr_t) - sizeof((*hdr).crc),
+                        0)) {
+                printf("EHCR\n");
+                goto err;
+        }
+
+        if (hdr->info_size + sizeof(ks_hdr_t) > KS_MAX_SZ) {
+                printf("ESIZ\n");
+                goto err;
+        }
+
+
+
+        /* we've compiled in with predefined sec arch support
+        - GEN3
+        */
+        if (sec_arch != hdr->sec_arch) {
+                printf("EARC\n");
+                goto err;
+        }
+        /* if booted in non-sec mode - verify data crc */
+        if (ks_verify((ks_t*)keystore, sec_state, 
+			bcm_sec_get_active_pub_key())) {
+                goto err;
+        }
+        ks_obj.mem = keystore;
+        ks_obj.ks = (ks_t*)keystore;
+        ks_obj.sec_state = sec_state;
+	ks_obj.pub = pub_key;
+	ks_obj.ek = aes_key;
+        ks_obj.state = KS_OBJ_OK;
+        return KS_ERR_SUCC; 
+err:
+        ks_obj.state = KS_OBJ_INVALID;
+        return KS_ERR_INVALID;
+}
+
+static ks_err_t ks_get_data(ks_key_info_t* key_info,
+			u8* cbc128_ek,
+			void* data)
+{
+        /*Copy data to the destination*/
+        ks_err_t rc =  KS_ERR_INVALID;
+        u32 data_sz; 
+        if (ks_type2size(KS_DATA_GET_TYPE(key_info->type_state), &data_sz)) {
+                printf("EKTP\n");
+                goto err;
+        }
+        switch(KS_DATA_GET_STATE(key_info->type_state)) {
+                case KS_DATA_STATE_FLD_ENCR:
+                        /*Decrypting 
+ 			* key_info->size must be padded to u32 
+ 			* */
+			if (!IS_ALIGNED(key_info->size, sizeof(u32))) {
+                		printf("EKEY\n");
+				goto err;
+			}
+			/*in place decryption encrypted - */
+                        aes_cbc128_decrypt( (u32*)&key_info->data[0],/*src*/
+                                        key_info->size, /*data len*/
+                                        cbc128_ek, /* key */
+                                        cbc128_ek + BCM_SECBT_AES_CBC128_EK_LEN); /*iv*/ 
+                        /*key_sz is expected size of the key per type*/
+                        memcpy(data, (u32*)&key_info->data[0], data_sz);
+                        break;
+                case KS_DATA_STATE_RAW:
+                        memcpy(data, &key_info->data[0], data_sz);
+                        break;
+                default:
+                        goto err;
+        }
+        rc = KS_ERR_SUCC; 
+err:
+        return rc;
+}
+/* returned pointer must be released in non CFE_ROM mode and 
+        keystore_data_release needs to be called when no more keys are not needed
+*/
+ks_err_t ks_get_data_info(ks_data_type_t type, 
+			ks_data_state_t state,
+			void* data)
+{
+        /*Copy data to the destination*/
+        ks_err_t  rc = KS_ERR_INVALID;
+        ks_hdr_t *hdr;
+        ks_key_info_t *key_info;
+        u8 *key_info_max;
+        if (ks_obj.state != KS_OBJ_OK) {
+                return KS_ERR_INVALID; 
+        }
+        hdr = &ks_obj.ks->hdr;
+        key_info = &((ks_t*)ks_obj.mem)->key.info;
+        key_info_max = (u8*)key_info + hdr->info_size - (sizeof(u32) + KS_SIG_SIZE);
+        while ((u8*)key_info < key_info_max) {
+                if ( KS_DATA_GET_TYPE(key_info->type_state) == type &&
+                        KS_DATA_GET_STATE(key_info->type_state) == state) {
+                        break;
+                }
+                key_info = (ks_key_info_t*)((uintptr_t)key_info+sizeof(ks_key_info_t)+key_info->size);
+        }
+        if ((u8*)key_info == key_info_max) {
+                goto err;
+        }
+        if (ks_get_data(key_info, 
+               ks_obj.ek,data) != KS_ERR_SUCC) {
+               goto err;
+        }
+        rc =  KS_ERR_SUCC; 
+err:
+        if (rc) {
+            printf("ERNF\n");
+        }
+        return rc;
+}
+
+ks_err_t ks_get_req_info(ks_req_info_t* req_info)
+{
+        if (ks_obj.state != KS_OBJ_OK) {
+                goto err;
+        }
+        memcpy(req_info, 
+		&ks_obj.ks->hdr.req_info, 
+		sizeof(ks_req_info_t));
+        return KS_ERR_SUCC; 
+err:
+        return KS_ERR_INVALID; 
+}
+
+static  void ks_data_release(void)
+{
+
+}
+ks_err_t ks_reset()
+{
+        if (ks_obj.state == KS_OBJ_OK) {
+                ks_data_release();
+        }
+        memset(&ks_obj, 0, sizeof(ks_obj));
+        return KS_ERR_SUCC; 
+}
diff --git a/arch/arm/mach-bcmbca/otp_tk/tk_ks.h b/arch/arm/mach-bcmbca/otp_tk/tk_ks.h
new file mode 100644
index 0000000000..942ca5f85f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/otp_tk/tk_ks.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2020 Broadcom Ltd.
+ */
+#ifndef __KS_H_
+#define __KS_H_
+ 
+/*
+ *
+ *	KS - Key Store 
+ *
+ * */
+
+#define KS_AES_256_CBC_SZ	AES256_KEY_LENGTH
+#define KS_AES_128_CBC_SZ	AES128_KEY_LENGTH
+#define KS_HASH_SZ		SHA256_SUM_LEN 
+#define KS_MID_SZ		4 
+
+#define KS_MAGIC		"BRCMKEYSTORE"
+/*Adjusting for \0*/
+#define KS_MAGIC_SIZE 		(sizeof(KS_MAGIC)-sizeof(char)) 
+#define KS_MAGIC_LEN		ALIGN(KS_MAGIC_SIZE, 4)
+
+#define KS_SIG_SIZE		RSA2048_BYTES
+#define KS_DEF_ABORT_DELAY	1
+
+#define	SEC_ARCH_NONE 0
+#define	SEC_ARCH_GEN1 1
+#define	SEC_ARCH_GEN2 2
+#define	SEC_ARCH_GEN3 3
+
+#define KS_MAX_KEYS 1 
+#define KS_MAX_SZ ALIGN((sizeof(ks_t)+KS_MAX_KEYS*(sizeof(ks_key_info_t)+KS_AES_128_CBC_SZ*4+KS_HASH_SZ*2+KS_MID_SZ*2)),4)
+
+
+#if defined (CONFIG_ARM64)
+#define KS_OFFSET   _image_binary_end
+#else
+#define KS_OFFSET   __bss_end
+#endif
+#define KS_IS_FDT(_FDT_)  (fdt_magic(_FDT_) == FDT_MAGIC)
+#define KS_FDT_SIZE(_FDT_)  (fdt_totalsize(_FDT_)) 
+
+typedef enum _ks_err {
+        KS_ERR_SUCC,
+        KS_ERR_INVALID,
+        KS_ERR_KEY_NOT_FOUND
+} ks_err_t;
+
+typedef enum _ks_req_state {
+        KS_REQ_NONE=0x0,
+        KS_REQ_TRANSIT_GEN2_BTRM,
+        KS_REQ_TRANSIT_GEN2_MFG,
+        KS_REQ_TRANSIT_GEN2_OP,
+        KS_REQ_TRANSIT_MFG,
+        KS_REQ_TRANSIT_FLD,
+} ks_req_state_t;
+
+typedef enum _ks_data_type {
+        KS_DATA_TYPE_KEY_AES_CBC_128_EK=0x0,
+        KS_DATA_TYPE_KEY_AES_CBC_128_IV=0x1,
+        KS_DATA_TYPE_KEY_AES_CBC_256_EK=0x2,
+        KS_DATA_TYPE_KEY_AES_CBC_256_IV=0x3,
+        KS_DATA_TYPE_RSA_PUB=0x4,
+        KS_DATA_TYPE_RSA_PRIV=0x5,
+        KS_DATA_TYPE_HASH=0x6,
+        KS_DATA_TYPE_MID=0x7,
+        KS_DATA_TYPE_OID=0x8,
+        KS_DATA_TYPE_BROM_MODE=0x9,
+        KS_DATA_TYPE_CUST_BROM_MODE=0xa,
+        KS_DATA_TYPE_MAX=0xb
+} ks_data_type_t;
+
+typedef enum _ks_data_state {
+        KS_DATA_STATE_RAW=0x0,
+        KS_DATA_STATE_MFG_ENCR=0x1,
+        KS_DATA_STATE_MFG_OEM_ENCR=0x2,
+        KS_DATA_STATE_FLD_ENCR=0x3,
+        KS_DATA_STATE_FLD_OEM_ENCR=0x4,
+        KS_DATA_STATE_MAX=0x5
+} ks_data_state_t;
+
+#define KS_STAT_MSK 0xff
+#define KS_DATA_GET_TYPE(d) (d&KS_STAT_MSK)
+#define KS_DATA_GET_STATE(d) ((d>>8)&KS_STAT_MSK)
+
+struct __attribute__((packed)) ks_req_info {
+        /*This what was requested by build*/
+        /*ks_req_state_t*/
+        u32 state;
+        u32 abort_delay;
+        /*sec_arch_info_t */
+};
+
+typedef struct  ks_req_info ks_req_info_t;
+
+struct __attribute__((packed)) ks_key_info {
+        u32 size;
+        u32 type_state;
+	/* must be multiple of u32*/
+        u8 data[0];
+};
+
+typedef struct ks_key_info ks_key_info_t;
+
+typedef struct __attribute__((packed)) ks_key {
+        /*crc of the data, sig and the key_info*/
+        u32 crc;
+        u8 sig[KS_SIG_SIZE];
+        ks_key_info_t info;
+} ks_key_t;
+
+/* Dual purpose:
+1. In non-secure mode (verifying via otp) if not-requested to enter to SEC mode
+   proceed to default cfe_rom path
+   -if requiested an MFG_FLD proceed to MFG enter
+   -if requiested an FLD proceed to FLD via MFG
+2. If in secure MFG but requested MFG_FLD proceed to FLD
+3. If in FLD mode proceed to secure boot  
+*/
+struct __attribute__((packed)) ks_hdr {
+        u8 magic[KS_MAGIC_SIZE];
+        u32 sec_arch;
+        ks_req_info_t req_info;
+        u32 info_size; 
+        /*header crc */
+        u32 crc; 
+};
+
+typedef struct ks_hdr ks_hdr_t; 
+
+typedef struct __attribute__((packed)) ks {
+        ks_hdr_t hdr;
+        ks_key_t key;
+} ks_t;
+
+/*
+        initializes and  verifies a key store
+*/
+ks_err_t ks_init(bcm_sec_state_t sec_state, 
+                u32 sec_arch,
+		const u8* pub,
+		const u8* aes_cbc128);
+ks_err_t ks_get_data_info(ks_data_type_t type, 
+			ks_data_state_t state,
+			void* data);
+ks_err_t ks_get_req_info(ks_req_info_t* req_info);
+ks_err_t ks_reset(void);
+
+
+#define BRKPT	do {						\
+			*((volatile u32*)0xff800600)=0x6;	\
+			asm("1: b 1b"); }while(0)
+#endif
diff --git a/arch/arm/mach-bcmbca/pinmux.c b/arch/arm/mach-bcmbca/pinmux.c
new file mode 100644
index 0000000000..07af8383fc
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pinmux.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include "pinctrl.h"
+
+/* this function is intended to be shared in SPL / TPL / UBOOT */
+int bcmbca_pinmux_set (volatile struct pinctrl_reg *regp, int pin, int func)
+{
+	uint32_t data = 0;
+
+	data |= pin;
+	data |= (func << PINMUX_DATA_SHIFT);
+
+	debug("pinmux %d func %d\n", pin, func);
+
+	regp->TestPortBlockDataMSB = 0;
+	regp->TestPortBlockDataLSB = data;
+	regp->TestPortCmd = LOAD_MUX_REG_CMD;
+
+	return 0;
+}
+
diff --git a/arch/arm/mach-bcmbca/pmc/Makefile b/arch/arm/mach-bcmbca/pmc/Makefile
new file mode 100644
index 0000000000..fea337da65
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/Makefile
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+# Temperarily put the pmc impl in arch folder. Need to 
+# move to driver and could try to use the power-domain 
+# uclass but it is very simple form now and need to add
+# the interface we need
+
+EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/ubus
+
+obj-y +=			\
+	pmc_drv.o		\
+	pmc_drv_bootloader.o	\
+	clk_rst.o		\
+
+obj-$(CONFIG_BCMBCA_PMC_SWITCH) += pmc_switch.o
+obj-$(CONFIG_BCMBCA_PMC_RDP) += pmc_rdp.o
+obj-$(CONFIG_BCMBCA_PMC_XRDP) += pmc_xrdp.o
+obj-$(CONFIG_BCMBCA_PMC_LPORT) += pmc_lport.o
+obj-$(CONFIG_BCMBCA_PMC_SYSPORT) += pmc_sysport.o
diff --git a/arch/arm/mach-bcmbca/pmc/clk_rst.c b/arch/arm/mach-bcmbca/pmc/clk_rst.c
new file mode 100755
index 0000000000..16c8001a85
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/clk_rst.c
@@ -0,0 +1,715 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+
+#include "pmc_drv.h"
+#include "clk_rst.h"
+#include "asm/arch/BPCM.h"
+
+#define VCO0_FREQ	1200
+#define VCO2_FREQ	1600
+
+#if IS_BCMCHIP(6855)
+int pll_vco_config(unsigned int pll_addr, unsigned int ndivider, unsigned int pdivider)
+{
+	int ret = 0;
+	PLL_CTRL_REG pll_ctrl;
+	PLL_STAT_REG pll_stat;
+	PLL_NDIV_REG pll_ndiv;
+	PLL_PDIV_REG pll_pdiv;
+
+	//  reset pll
+	ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(resets), &pll_ctrl.Reg32);
+	pll_ctrl.Bits.master_reset = 1;
+	WriteBPCMRegister(pll_addr, PLLBPCMRegOffset(resets), pll_ctrl.Reg32);
+
+	// change ndiv and pdiv
+	ret = ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(pdiv), &pll_pdiv.Reg32);
+	pll_pdiv.Bits.pdiv = pdivider;
+	pll_pdiv.Bits.ndiv_pdiv_override = 1;
+	ret |= WriteBPCMRegister(pll_addr, PLLBPCMRegOffset(pdiv), pll_pdiv.Reg32);
+
+	ret = ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ndiv), &pll_ndiv.Reg32);
+	pll_ndiv.Bits.ndiv_int = ndivider;
+	pll_ndiv.Bits.ndiv_override = 1;
+	ret |= WriteBPCMRegister(pll_addr, PLLBPCMRegOffset(ndiv), pll_ndiv.Reg32);
+
+	// take pll out of reset
+	ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(resets), &pll_ctrl.Reg32);
+	pll_ctrl.Bits.master_reset = 0;
+	WriteBPCMRegister(pll_addr, PLLBPCMRegOffset(resets), pll_ctrl.Reg32);
+
+	// wait untill pll is locked
+	do {
+		ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(stat), &pll_stat.Reg32);
+	} while (pll_stat.Bits.lock == 0);
+
+	return ret;
+}
+#endif
+
+#if IS_BCMCHIP(6858) || IS_BCMCHIP(63158) || IS_BCMCHIP(6856) || \
+	IS_BCMCHIP(6846) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || \
+	IS_BCMCHIP(6878) || IS_BCMCHIP(63146) || IS_BCMCHIP(4912) || \
+	IS_BCMCHIP(6855) || IS_BCMCHIP(6756)
+#define PLL_REFCLK  50
+int pll_vco_freq_get(unsigned int pll_addr, unsigned int *fvco)
+{
+	int ret = 0;
+	PLL_DECNDIV_REG pll_decndiv;
+	PLL_DECPDIV_REG pll_decpdiv;
+#if IS_BCMCHIP(63158) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || \
+	IS_BCMCHIP(63146) || IS_BCMCHIP(4912) || IS_BCMCHIP(6855) || \
+	IS_BCMCHIP(6756)
+	PLL_NDIV_REG ndiv_reg;
+	PLL_PDIV_REG pdiv_reg;
+#endif
+
+#if IS_BCMCHIP(6856)
+	ret =
+	    ReadBPCMRegister(pll_addr, PLLCLASSICBPCMRegOffset(decndiv),
+			     &pll_decndiv.Reg32);
+	ret |=
+	    ReadBPCMRegister(pll_addr, PLLCLASSICBPCMRegOffset(decpdiv),
+			     &pll_decpdiv.Reg32);
+#else
+	ret =
+	    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(decndiv),
+			     &pll_decndiv.Reg32);
+	ret |=
+	    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(decpdiv),
+			     &pll_decpdiv.Reg32);
+#endif
+	if (ret != 0)
+		return -1;
+
+	// Let's ignore ndiv_frac, it is set to zero anyway by HW.
+	*fvco =
+	    (PLL_REFCLK * (pll_decndiv.Bits.ndiv_int)) / pll_decpdiv.Bits.pdiv;
+
+#if IS_BCMCHIP(63158) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || \
+	IS_BCMCHIP(63146) || IS_BCMCHIP(4912) || IS_BCMCHIP(6855) || \
+	IS_BCMCHIP(6756)
+	if (!ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(pdiv), &pdiv_reg.Reg32)
+	    && pdiv_reg.Bits.ndiv_pdiv_override
+	    && !ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ndiv),
+				 &ndiv_reg.Reg32))
+		*fvco =
+		    (PLL_REFCLK * (ndiv_reg.Bits.ndiv_int)) /
+		    pdiv_reg.Bits.pdiv;
+#endif
+
+	return 0;
+}
+
+int pll_ch_freq_get(unsigned int pll_addr, unsigned int ch, unsigned int *freq)
+{
+	int ret;
+	unsigned int fvco, mdiv;
+	PLL_DECPDIV_REG pll_decpdiv;
+	PLL_DECCH25_REG pll_decch25;
+	PLL_CHCFG_REG ch_cfg;
+
+	ret = pll_vco_freq_get(pll_addr, &fvco);
+
+	if (ret != 0)
+		return -1;
+
+	// The pll may include up to 6 channels.
+	switch (ch) {
+	case 0:
+#if IS_BCMCHIP(6856)
+		ret =
+		    ReadBPCMRegister(pll_addr,
+				     PLLCLASSICBPCMRegOffset(ch01_cfg),
+				     &ch_cfg.Reg32);
+#else
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch01_cfg),
+				     &ch_cfg.Reg32);
+#endif
+		/* Check if default value is overitten */
+		if (ch_cfg.Bits.mdiv_override0)
+			mdiv = ch_cfg.Bits.mdiv0;	/* Use the new value */
+		else {		/* If not, read from the default */
+
+#if IS_BCMCHIP(6856)
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLCLASSICBPCMRegOffset(decpdiv),
+					     &pll_decpdiv.Reg32);
+#else
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLBPCMRegOffset(decpdiv),
+					     &pll_decpdiv.Reg32);
+#endif
+			mdiv = pll_decpdiv.Bits.mdiv0;
+		}
+		break;
+	case 1:
+#if IS_BCMCHIP(6856)
+		ret =
+		    ReadBPCMRegister(pll_addr,
+				     PLLCLASSICBPCMRegOffset(ch01_cfg),
+				     &ch_cfg.Reg32);
+#else
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch01_cfg),
+				     &ch_cfg.Reg32);
+#endif
+		if (ch_cfg.Bits.mdiv_override1)
+			mdiv = ch_cfg.Bits.mdiv1;
+		else {
+#if IS_BCMCHIP(6856)
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLCLASSICBPCMRegOffset(decpdiv),
+					     &pll_decpdiv.Reg32);
+#else
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLBPCMRegOffset(decpdiv),
+					     &pll_decpdiv.Reg32);
+#endif
+			mdiv = pll_decpdiv.Bits.mdiv1;
+		}
+		break;
+	case 2:
+#if IS_BCMCHIP(6856)
+		ret =
+		    ReadBPCMRegister(pll_addr,
+				     PLLCLASSICBPCMRegOffset(ch23_cfg),
+				     &ch_cfg.Reg32);
+#else
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch23_cfg),
+				     &ch_cfg.Reg32);
+#endif
+		if (ch_cfg.Bits.mdiv_override0)
+			mdiv = ch_cfg.Bits.mdiv0;
+		else {
+#if IS_BCMCHIP(6856)
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLCLASSICBPCMRegOffset(decch25),
+					     &pll_decch25.Reg32);
+#else
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLBPCMRegOffset(decch25),
+					     &pll_decch25.Reg32);
+#endif
+			mdiv = pll_decch25.Bits.mdiv2;
+		}
+		break;
+	case 3:
+#if IS_BCMCHIP(6856)
+		ret =
+		    ReadBPCMRegister(pll_addr,
+				     PLLCLASSICBPCMRegOffset(ch23_cfg),
+				     &ch_cfg.Reg32);
+#else
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch23_cfg),
+				     &ch_cfg.Reg32);
+#endif
+		if (ch_cfg.Bits.mdiv_override1)
+			mdiv = ch_cfg.Bits.mdiv1;
+		else {
+#if IS_BCMCHIP(6856)
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLCLASSICBPCMRegOffset(decch25),
+					     &pll_decch25.Reg32);
+#else
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLBPCMRegOffset(decch25),
+					     &pll_decch25.Reg32);
+#endif
+			mdiv = pll_decch25.Bits.mdiv3;
+		}
+		break;
+	case 4:
+#if IS_BCMCHIP(6856)
+		ret =
+		    ReadBPCMRegister(pll_addr,
+				     PLLCLASSICBPCMRegOffset(ch45_cfg),
+				     &ch_cfg.Reg32);
+#else
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch45_cfg),
+				     &ch_cfg.Reg32);
+#endif
+		if (ch_cfg.Bits.mdiv_override0)
+			mdiv = ch_cfg.Bits.mdiv0;
+		else {
+#if IS_BCMCHIP(6856)
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLCLASSICBPCMRegOffset(decch25),
+					     &pll_decch25.Reg32);
+#else
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLBPCMRegOffset(decch25),
+					     &pll_decch25.Reg32);
+#endif
+			mdiv = pll_decch25.Bits.mdiv4;
+		}
+		break;
+	case 5:
+#if IS_BCMCHIP(6856)
+		ret =
+		    ReadBPCMRegister(pll_addr,
+				     PLLCLASSICBPCMRegOffset(ch45_cfg),
+				     &ch_cfg.Reg32);
+#else
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch45_cfg),
+				     &ch_cfg.Reg32);
+#endif
+		if (ch_cfg.Bits.mdiv_override1)
+			mdiv = ch_cfg.Bits.mdiv1;
+		else {
+#if IS_BCMCHIP(6856)
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLCLASSICBPCMRegOffset(decch25),
+					     &pll_decch25.Reg32);
+			mdiv = pll_decch25.Bits.mdiv5;			
+#elif IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLBPCMRegOffset(decpdiv),
+					     &pll_decpdiv.Reg32);
+			mdiv = pll_decpdiv.Bits.mdiv5;			
+#else			
+			ret =
+			    ReadBPCMRegister(pll_addr,
+					     PLLBPCMRegOffset(decch25),
+					     &pll_decch25.Reg32);
+			mdiv = pll_decch25.Bits.mdiv5;			
+#endif
+		}
+		break;
+	default:
+		return -1;
+	};
+
+	if (ret != 0)
+		return -1;
+
+	*freq = fvco / mdiv;
+
+	return 0;
+}
+EXPORT_SYMBOL(pll_ch_freq_get);
+#endif
+
+unsigned long get_rdp_freq(unsigned int *rdp_freq)
+{
+	int ret = -1;
+#if IS_BCMCHIP(6878)
+	unsigned int fvco, mdiv;
+	PLL_DECNDIV_REG pll_decndiv;
+	PLL_DECPDIV_REG pll_decpdiv;
+
+	ret =
+	    ReadBPCMRegister(PMB_ADDR_SYSPLL, PLLCLASSICBPCMRegOffset(decndiv),
+			     &pll_decndiv.Reg32);
+	ret |=
+	    ReadBPCMRegister(PMB_ADDR_SYSPLL, PLLCLASSICBPCMRegOffset(decpdiv),
+			     &pll_decpdiv.Reg32);
+	// Let's ignore ndiv_frac, it is set to zero anyway by HW.
+	fvco =
+	    (PLL_REFCLK * (pll_decndiv.Bits.ndiv_int)) / pll_decpdiv.Bits.pdiv;
+
+	// read mdiv of channel 0
+	ret =
+	    ReadBPCMRegister(PMB_ADDR_SYSPLL, PLLCLASSICBPCMRegOffset(decpdiv),
+			     &pll_decpdiv.Reg32);
+	mdiv = pll_decpdiv.Bits.mdiv0;
+
+	*rdp_freq = fvco / mdiv;
+
+
+#elif IS_BCMCHIP(6858) || IS_BCMCHIP(63158) || IS_BCMCHIP(6856) || \
+	IS_BCMCHIP(6846)
+	ret =
+	    pll_ch_freq_get(PMB_ADDR_RDPPLL, XRDPPLL_RUNNER_CHANNEL, rdp_freq);
+#if IS_BCMCHIP(6856) || IS_BCMCHIP(6846)
+	*rdp_freq /= 2;
+#endif
+#elif IS_BCMCHIP(6855)
+
+	ret = pll_ch_freq_get(PMB_ADDR_SYSPLL, XRDPPLL_RUNNER_CHANNEL, rdp_freq);
+
+#elif IS_BCMCHIP(63138) || IS_BCMCHIP(63148) || IS_BCMCHIP(4908)
+/* FIXME!! when knowing the real frequency info for 4908/62118 RDP */
+
+#define RDP_PLL_REFCLK		50	/* 50 MHz for 63138 */
+
+/* the formula here is
+ * F_vco = (1 / pdiv) * (ndiv_int + ndiv_frac / (2 ^ 20)) * F_ref
+ * F_clkout,n = (F_vco / mdiv_n)
+ * ch#0 connects to runner block
+ * ch#1 connects to test block
+ * ch#2 connects to ipsec & rng block
+ *
+ * default values are:
+ * ndiv_int = 0x8c (140)
+ * ndiv_frac = 0
+ * pdiv = 2
+ * mdiv[0] = 0x5
+ * mdiv[1] = 0xa
+ * mdiv[2] = 0x23 (35).
+ *
+ * F_vco = 3500 MHz
+ * F_clkout,0 = 700 MHz -> runner
+ */
+
+	PLL_NDIV_REG pll_ndiv;
+	PLL_PDIV_REG pll_pdiv;
+	PLL_CHCFG_REG pll_ch01_cfg;
+
+	ret = ReadBPCMRegister(PMB_ADDR_RDPPLL, PLLBPCMRegOffset(ndiv),
+				&pll_ndiv.Reg32);
+	ret |= ReadBPCMRegister(PMB_ADDR_RDPPLL, PLLBPCMRegOffset(pdiv),
+				&pll_pdiv.Reg32);
+	ret |= ReadBPCMRegister(PMB_ADDR_RDPPLL, PLLBPCMRegOffset(ch01_cfg),
+				&pll_ch01_cfg.Reg32);
+	if (ret != 0)
+		return -1;
+
+	*rdp_freq = RDP_PLL_REFCLK * (pll_ndiv.Bits.ndiv_int);
+	// FIXME! for simplicity, ndiv_frac is taken out.  Otherwise, the value
+	// will be in form of double.
+	*rdp_freq = *rdp_freq / pll_pdiv.Bits.pdiv / pll_ch01_cfg.Bits.mdiv0;
+
+#elif IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
+	/* FIXME */
+	/* Use RDPPLLBPCMRegOffset macro here. Its definitio is different than 
+	   the main PLL */
+	ret = 0;
+	*rdp_freq = 1200;
+
+#endif
+
+	return ret;
+}
+EXPORT_SYMBOL(get_rdp_freq);
+
+#if IS_BCMCHIP(6858) || IS_BCMCHIP(6856) || IS_BCMCHIP(6846) || \
+	IS_BCMCHIP(63158) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || \
+	IS_BCMCHIP(6878) || IS_BCMCHIP(63146) || IS_BCMCHIP(4912) || \
+	IS_BCMCHIP(6855) || IS_BCMCHIP(6756)
+int pll_ch_reset(unsigned int pll_addr, unsigned int ch, unsigned int pll_reg_offset)
+{
+	int ret;
+	PLL_CHCFG_REG ch_cfg;
+
+	// The pll may include up to 6 channels.
+	switch (ch) {
+	case 0:
+	case 2:
+	case 4:
+		ret =
+		    ReadBPCMRegister(pll_addr, pll_reg_offset,
+				     &ch_cfg.Reg32);
+		ch_cfg.Bits.mdiv0 = 0;
+		ch_cfg.Bits.mdiv_override0 = 0;
+		ret |=
+		    WriteBPCMRegister(pll_addr, pll_reg_offset,
+				      ch_cfg.Reg32);
+		break;
+	case 1:
+	case 3:
+	case 5:
+		ret =
+		    ReadBPCMRegister(pll_addr, pll_reg_offset,
+				     &ch_cfg.Reg32);
+		ch_cfg.Bits.mdiv1 = 0;
+		ch_cfg.Bits.mdiv_override1 = 0;
+		ret |=
+		    WriteBPCMRegister(pll_addr, pll_reg_offset,
+				      ch_cfg.Reg32);
+		break;
+	default:
+		return -1;
+	};
+
+	return ret;
+}
+
+int pll_ch_freq_set_offs(unsigned int pll_addr, unsigned int ch, unsigned int mdiv, unsigned int offset)
+{
+	int ret;
+	PLL_CHCFG_REG ch_cfg;
+
+	// The pll may include up to 6 channels.
+	switch (ch) {
+	case 0:
+	case 2:
+	case 4:
+		ret = ReadBPCMRegister(pll_addr, offset, &ch_cfg.Reg32);
+		ch_cfg.Bits.mdiv0 = mdiv;
+		ch_cfg.Bits.mdiv_override0 = 1;
+		ret |= WriteBPCMRegister(pll_addr, offset, ch_cfg.Reg32);
+		break;
+	case 1:
+	case 3:
+	case 5:
+		ret = ReadBPCMRegister(pll_addr, offset, &ch_cfg.Reg32);
+		ch_cfg.Bits.mdiv1 = mdiv;
+		ch_cfg.Bits.mdiv_override1 = 1;
+		ret |= WriteBPCMRegister(pll_addr, offset, ch_cfg.Reg32);
+		break;
+	default:
+		return -1;
+	};
+	return ret;
+}
+
+int pll_ch_freq_set(unsigned int pll_addr, unsigned int ch, unsigned int mdiv)
+{
+	int ret;
+
+	// The pll may include up to 6 channels.
+	switch (ch) {
+	case 0:
+	case 1:
+		ret |= pll_ch_freq_set_offs( pll_addr, ch, mdiv, PLLBPCMRegOffset(ch01_cfg));
+		break;
+	case 2:
+	case 3:
+		ret |= pll_ch_freq_set_offs( pll_addr, ch, mdiv, PLLBPCMRegOffset(ch23_cfg));
+		break;
+	case 4:
+	case 5:
+		ret |= pll_ch_freq_set_offs( pll_addr, ch, mdiv, PLLBPCMRegOffset(ch45_cfg));
+		break;
+	default:
+		return -1;
+	};
+
+	return ret;
+}
+
+int pll_ch_freq_vco_set(unsigned int pll_addr, unsigned int ch,
+			unsigned int mdiv, unsigned int use_vco)
+{
+	int ret;
+	PLL_CHCFG_REG ch_cfg;
+
+	// The pll may include up to 6 channels.
+	switch (ch) {
+	case 0:
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch01_cfg),
+				     &ch_cfg.Reg32);
+		ch_cfg.Bits.mdiv0 = mdiv;
+		ch_cfg.Bits.mdiv_override0 = 1;
+		ch_cfg.Bits.reserved0 = use_vco ? 1 : 0;
+		ret |=
+		    WriteBPCMRegister(pll_addr, PLLBPCMRegOffset(ch01_cfg),
+				      ch_cfg.Reg32);
+		break;
+	case 1:
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch01_cfg),
+				     &ch_cfg.Reg32);
+		ch_cfg.Bits.mdiv1 = mdiv;
+		ch_cfg.Bits.mdiv_override1 = 1;
+		ch_cfg.Bits.reserved1 = use_vco ? 1 : 0;
+		ret |=
+		    WriteBPCMRegister(pll_addr, PLLBPCMRegOffset(ch01_cfg),
+				      ch_cfg.Reg32);
+		break;
+	case 2:
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch23_cfg),
+				     &ch_cfg.Reg32);
+		ch_cfg.Bits.mdiv0 = mdiv;
+		ch_cfg.Bits.mdiv_override0 = 1;
+		ch_cfg.Bits.reserved0 = use_vco ? 1 : 0;
+		ret |=
+		    WriteBPCMRegister(pll_addr, PLLBPCMRegOffset(ch23_cfg),
+				      ch_cfg.Reg32);
+		break;
+	case 3:
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch23_cfg),
+				     &ch_cfg.Reg32);
+		ch_cfg.Bits.mdiv1 = mdiv;
+		ch_cfg.Bits.mdiv_override1 = 1;
+		ch_cfg.Bits.reserved1 = use_vco ? 1 : 0;
+		ret |=
+		    WriteBPCMRegister(pll_addr, PLLBPCMRegOffset(ch23_cfg),
+				      ch_cfg.Reg32);
+		break;
+	case 4:
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch45_cfg),
+				     &ch_cfg.Reg32);
+		ch_cfg.Bits.mdiv0 = mdiv;
+		ch_cfg.Bits.mdiv_override0 = 1;
+		ch_cfg.Bits.reserved0 = use_vco ? 1 : 0;
+		ret |=
+		    WriteBPCMRegister(pll_addr, PLLBPCMRegOffset(ch45_cfg),
+				      ch_cfg.Reg32);
+		break;
+	case 5:
+		ret =
+		    ReadBPCMRegister(pll_addr, PLLBPCMRegOffset(ch45_cfg),
+				     &ch_cfg.Reg32);
+		ch_cfg.Bits.mdiv1 = mdiv;
+		ch_cfg.Bits.mdiv_override1 = 1;
+		ch_cfg.Bits.reserved1 = use_vco ? 1 : 0;
+		ret |=
+		    WriteBPCMRegister(pll_addr, PLLBPCMRegOffset(ch45_cfg),
+				      ch_cfg.Reg32);
+		break;
+	default:
+		return -1;
+	};
+
+	return ret;
+}
+#endif
+
+#if IS_BCMCHIP(6858)
+int bcm_change_cpu_clk(BCM_CPU_CLK clock)
+{
+	int ret = 0;
+	PLL_CTRL_REG ctrl_reg;
+
+	if (ReadBPCMRegister
+	    (PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), &ctrl_reg.Reg32))
+		return -1;
+
+	if (clock == BCM_CPU_CLK_HIGH)
+		ctrl_reg.Bits.byp_wait = 0;
+	else if (clock == BCM_CPU_CLK_LOW)
+		ctrl_reg.Bits.byp_wait = 1;
+	else
+		ret = -1;
+
+	ret = WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets),
+				ctrl_reg.Reg32);
+
+	return ret;
+}
+#endif
+
+#if defined(__KERNEL__) && IS_BCMCHIP(63158)
+void clk_divide_50mhz_to_25mhz(void)
+{
+	uint32_t data;
+	int ret;
+
+	ret = ReadBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+			       CLKRSTBPCMRegOffset(xtal_control), &data);
+	if (ret) {
+		printk("Failed to ReadBPCMRegister CHIP_CLKRST block "
+		       "CLKRST_XTAL_CNTL. Error=%d\n", ret);
+		return;
+	}
+
+	/* Divide clock by 2. From 50mhz to 25mhz */
+	data |= (0x1 << 24);
+
+	ret =
+	    WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+			      CLKRSTBPCMRegOffset(xtal_control), data);
+	if (ret)
+		printk("Failed to writeBPCMRegister CHIP_CLKRST block "
+		       "CLKRST_XTAL_CNTL. Error=%d\n", ret);
+}
+EXPORT_SYMBOL(clk_divide_50mhz_to_25mhz);
+#endif
+
+#if defined(__KERNEL__) && (IS_BCMCHIP(6858) || IS_BCMCHIP(6846) || \
+		IS_BCMCHIP(6856) || IS_BCMCHIP(6878))
+#if IS_BCMCHIP(6878)
+#define PMD_CLOCK_REG pmd_xtal_cntl
+#define CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV (2)
+#define CLOCK_RESET_XTAL_CONTROL_BIT_PWRON  (27)
+#define PMD_CLOCK_REG2 pmd_xtal_cntl2
+#define CLOCK_RESET_XTAL_CONTROL2_BIT_PD    (0)
+#else
+#define PMD_CLOCK_REG xtal_control
+#define CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV (17)
+#endif
+
+void disable_25mhz_clk_to_pmd(void)
+{
+	uint32_t data;
+	int ret;
+
+	ret = ReadBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+			       CLKRSTBPCMRegOffset(PMD_CLOCK_REG), &data);
+	if (ret) {
+		printk("Failed to ReadBPCMRegister CHIP_CLKRST block "
+		       "CLKRST_XTAL_CNTL. Error=%d\n", ret);
+		return;
+	}
+
+	data |= (0x1 << CLOCK_RESET_XTAL_CONTROL_BIT_PD_DRV);
+#if IS_BCMCHIP(6878)
+	data &= ~(0x1 << CLOCK_RESET_XTAL_CONTROL_BIT_PWRON);
+#endif
+
+	ret = WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+				CLKRSTBPCMRegOffset(PMD_CLOCK_REG), data);
+	if (ret)
+		printk("Failed to writeBPCMRegister CHIP_CLKRST block "
+		       "CLKRST_XTAL_CNTL. Error=%d\n", ret);
+
+#if IS_BCMCHIP(6878)
+	ret =
+	    ReadBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+			     CLKRSTBPCMRegOffset(PMD_CLOCK_REG2), &data);
+	if (ret) {
+		printk("Failed to ReadBPCMRegister CHIP_CLKRST block "
+		       "PMD_XTAL_CNTL2. Error=%d\n", ret);
+		return;
+	}
+
+	data |= (0x1 << CLOCK_RESET_XTAL_CONTROL2_BIT_PD);
+
+	ret = WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+				CLKRSTBPCMRegOffset(PMD_CLOCK_REG2), data);
+	if (ret)
+		printk("Failed to writeBPCMRegister CHIP_CLKRST block "
+		       "CLKRST_XTAL_CNTL2. Error=%d\n", ret);
+#endif
+}
+EXPORT_SYMBOL(disable_25mhz_clk_to_pmd);
+#endif
+
+void set_vreg_clk(void)
+{
+#if IS_BCMCHIP(63178) || IS_BCMCHIP(63146)
+	int ret;
+	BPCM_CLKRST_VREG_CONTROL vreg_control_reg;
+
+	vreg_control_reg.Bits.enable = 1;
+	vreg_control_reg.Bits.counter = 0x24;
+#if IS_BCMCHIP(63146)
+	vreg_control_reg.Bits.counter = 0x32;
+#endif
+	ret = WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+				CLKRSTBPCMRegOffset(vreg_control),
+				vreg_control_reg.Reg32);
+	if (ret)
+		printk("Failed to writeBPCMRegister CHIP_CLKRST block "
+		       "VREG_CONTROL. Error=%d\n", ret);
+#endif
+}
+EXPORT_SYMBOL(set_vreg_clk);
diff --git a/arch/arm/mach-bcmbca/pmc/clk_rst.h b/arch/arm/mach-bcmbca/pmc/clk_rst.h
new file mode 100755
index 0000000000..77fc1424f6
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/clk_rst.h
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+
+#ifndef CLK_RST_H
+#define CLK_RST_H
+
+#ifndef IS_BCMCHIP
+#define IS_BCMCHIP(num) (defined(_BCM9##num##_)||defined(CONFIG_BCM9##num)||\
+				defined(CONFIG_BCM##num))
+#endif
+
+// pll dividers 
+struct PLL_DIVIDERS {
+	unsigned int pdiv;
+	unsigned int ndiv_int;
+	unsigned int ndiv_frac;
+	unsigned int ka;
+	unsigned int ki;
+	unsigned int kp;
+};
+
+int pll_vco_freq_set(unsigned int pll_addr, struct PLL_DIVIDERS *divs);
+int pll_ch_reset(unsigned int pll_addr, unsigned int ch, unsigned int pll_reg_offset);
+int pll_ch_freq_set(unsigned int pll_addr, unsigned int ch, unsigned int mdiv);
+int pll_ch_freq_get(unsigned int pll_addr, unsigned int ch, unsigned int *freq);
+int ddr_freq_set(unsigned long freq);
+int viper_freq_set(unsigned long freq);
+int rdp_freq_set(unsigned long freq);
+unsigned long get_rdp_freq(unsigned int *rdp_freq);
+#if IS_BCMCHIP(6858) || IS_BCMCHIP(6856) || IS_BCMCHIP(6878) || IS_BCMCHIP(6855)
+int pll_vco_freq_get(unsigned int pll_addr, unsigned int *fvco);
+int pll_ch_freq_vco_set(unsigned int pll_addr, unsigned int ch,
+			unsigned int mdiv, unsigned int use_vco);
+#endif
+
+#if IS_BCMCHIP(6855)
+int pll_vco_config(unsigned int pll_addr, unsigned int ndivider, unsigned int pdivider);
+#endif
+
+void set_vreg_clk(void);
+
+#if IS_BCMCHIP(6858)
+
+typedef enum {
+	BCM_CPU_CLK_HIGH,
+	BCM_CPU_CLK_LOW
+} BCM_CPU_CLK;
+
+int bcm_change_cpu_clk(BCM_CPU_CLK clock);
+
+#endif
+
+#if IS_BCMCHIP(6858) || IS_BCMCHIP(6855)
+#define XRDPPLL_RUNNER_CHANNEL   0
+#endif
+#if IS_BCMCHIP(6856) || IS_BCMCHIP(6846)
+#define XRDPPLL_RUNNER_CHANNEL   1
+#endif
+#if IS_BCMCHIP(6878)
+#define SYSPLL_RUNNER_CHANNEL   0
+#endif
+#if IS_BCMCHIP(63158)
+/* TBD. Verify value. */
+#define XRDPPLL_RUNNER_CHANNEL   1
+#endif
+#endif //#ifndef CLK_RST_H
diff --git a/arch/arm/mach-bcmbca/pmc/command.h b/arch/arm/mach-bcmbca/pmc/command.h
new file mode 100755
index 0000000000..5d770d5d9d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/command.h
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+
+#ifndef PMCCOMMAND_H
+#define PMCCOMMAND_H
+
+#include "pmc_drv.h"
+
+typedef union {
+	struct {
+		uint32_t cmdID:8;
+		uint32_t error:8;
+		uint32_t msgID:8;
+		uint32_t srcPort:8;
+	} Bits;
+	uint32_t Reg32;
+} TCommandWord0;
+
+#ifdef PMC_IMPL_3_X
+typedef union {
+	struct {
+		uint32_t devAddr:16;	// [15:00] bus in upper nibble (only values of 0-7 are allowed), device address in lower 12 bits (4096 devices = 0..4095)
+		uint32_t zoneIdx:10;	// [25:16] maximum 1023 registers/zone (0..1022)
+		uint32_t island:4;	// [27:26] maximum 15 power islands (0..15) (island 15 = ALL islands!
+		uint32_t reserved:2;	// [31:28]
+	} Bits;
+	uint32_t Reg32;
+} TCommandWord1;
+#else
+typedef union {
+	struct {
+		uint32_t zoneIdx:10;
+		uint32_t devAddr:10;
+		uint32_t island:4;
+		uint32_t logNum:8;
+	} Bits;
+	uint32_t Reg32;
+} TCommandWord1;
+#endif
+
+// Ping, GetNextLogEntry, GetRMON and Sigma
+typedef struct {
+	uint32_t unused[2];
+} TCommandNoParams;
+
+typedef struct {
+	uint32_t params[2];
+} TCommandGenericParams;
+
+// PowerZoneOnOff, SetRunState, SetPowerState
+typedef struct {
+#if defined(PMC_CPU_BIG_ENDIAN)
+	uint8_t reserved[3];
+	uint8_t state;
+#else
+	uint8_t state;
+	uint8_t reserved[3];
+#endif
+	uint32_t unused;
+} TCommandStateOnly;
+
+// PowerDevOnOff
+typedef struct {
+#if defined(PMC_CPU_BIG_ENDIAN)
+	uint8_t reserved[2];
+	uint8_t restore;
+	uint8_t state;
+#else
+	uint8_t state;
+	uint8_t restore;
+	uint8_t reserved[2];
+#endif
+	uint32_t unused;
+} TCommandPowerDevice;
+
+// PowerOffIsland
+typedef struct {
+#if defined(PMC_CPU_BIG_ENDIAN)
+	uint8_t reserved[3];
+	uint8_t restore;
+#else
+	uint8_t restore;
+	uint8_t reserved[3];
+#endif
+	uint32_t unused;
+} TCommandPowerIsland;
+
+// SetClockLowGear, SetClockHighGear
+typedef struct {
+#if defined(PMC_CPU_BIG_ENDIAN)
+	uint8_t reserved[3];
+	uint8_t clkN;
+#else
+	uint8_t clkN;
+	uint8_t reserved[3];
+#endif
+	uint32_t unused;
+} TCommandSetClockN;
+
+// SetClockGear
+typedef struct {
+#if defined(PMC_CPU_BIG_ENDIAN)
+	uint8_t reserved[3];
+	uint8_t gear;
+#else
+	uint8_t gear;
+	uint8_t reserved[3];
+#endif
+	uint32_t unused;
+} TCommandSetClockGear;
+
+typedef struct {
+#if defined(PMC_CPU_BIG_ENDIAN)
+	uint8_t unused1;
+	uint8_t numTokens;
+	uint8_t tokenSize;
+	uint8_t queueNumber;
+	uint16_t unused2;
+	uint8_t high_watermark;
+	uint8_t low_watermark;
+#else
+	uint8_t queueNumber;
+	uint8_t tokenSize;
+	uint8_t numTokens;
+	uint8_t unused1;
+	uint8_t low_watermark;
+	uint8_t high_watermark;
+	uint16_t unused2;
+#endif
+} TCommandAllocDQM;
+
+typedef struct {
+	uint32_t phy_src_addr;
+	uint32_t dest_addr;	// lower 8 bits **may** be log2 window size
+} TCommandJumpApp;
+
+typedef struct {
+#if defined(PMC_IMPL_3_X) || IS_BCMCHIP(63158)
+	union {
+		uint32_t word2;
+		struct {
+			uint16_t margin_mv_slow;
+			uint16_t maximum_mv;
+		};
+	};
+	union {
+		uint32_t word3;
+		struct {
+			uint16_t margin_mv_fast;
+			uint16_t minimum_mv;
+		};
+	};
+#else
+	uint32_t margin_mv_slow;
+	uint32_t margin_mv_fast;
+#endif
+} TCommandCloseAVS;
+
+typedef struct {
+	uint32_t word2;
+	uint32_t word3;
+} TCommandResponse;
+
+typedef struct {
+	TCommandWord0 word0;
+	TCommandWord1 word1;
+	union {
+		TCommandNoParams cmdNoParams;
+		TCommandGenericParams cmdGenericParams;
+		TCommandStateOnly cmdStateOnlyParam;
+		TCommandPowerDevice cmdPowerDevice;
+		TCommandPowerIsland cmdPowerIsland;
+		TCommandSetClockN cmdSetClockN;
+		TCommandSetClockGear cmdSetClockGear;
+		TCommandAllocDQM cmdAllocDqm;
+		TCommandJumpApp cmdJumpApp;
+		TCommandCloseAVS cmdCloseAVS;
+		TCommandResponse cmdResponse;
+	} u;
+} TCommand;
+
+// special values to select all devices/zones
+#define ALL_DEVICES	0x3ff
+#define ALL_ZONES	0x3ff
+
+// used in validate caller to prevent/allow restrictions on island, device and/or zone
+#define ANY_ISLAND	998
+#define ANY_DEVICE	1024
+#define ANY_ZONE	1024
+#define NO_ISLAND	999
+#define NO_DEVICE	1025
+#define NO_ZONE		1025
+
+// error codes
+enum {
+	NO_ERROR = 0,
+	INVALID_ISLAND,
+	INVALID_DEVICE,
+	INVALID_ZONE,
+	INVALID_STATE,
+	INVALID_COMMAND,
+	LOG_EMPTY,
+	INVALID_PARAM,
+	BPCM_READ_TIMEOUT,
+	INVALID_BUS,
+	INVALID_QUEUE_NUMBER,
+	QUEUE_NOT_AVAILABLE,
+	INVALID_TOKEN_SIZE,
+	INVALID_WATERMARKS,
+	INSUFFIENT_QSM_MEMORY_AVAILABLE,
+	INVALID_BOOT_COMMAND,
+	BPCM_WRITE_TIMEOUT,
+	CMD_TABLE_FULL,
+	CMD_TABLE_LOCKED,
+};
+
+// command codes
+enum {
+	// low-level commands
+	cmdReserved = 0,
+	cmdGetDevPresence,
+	cmdGetSWStrap,
+	cmdGetHWRev,
+	cmdGetNumZones,
+	cmdPing,
+	cmdGetNextLogEntry,
+	cmdGetRMON,
+	cmdSetClockHighGear,
+	cmdSetClockLowGear,
+	cmdSetClockGear,
+	cmdReadBpcmReg,
+	cmdReadZoneReg,
+	cmdWriteBpcmReg,
+	cmdWriteZoneReg,
+	// general-purpose high-level commands
+	cmdSetRunState,
+	cmdSetPowerState,
+	cmdShutdownAllowed,
+	cmdGetSelect0,
+	cmdGetSelect3,
+	cmdGetAvsDisableState,
+	cmdGetPVT,
+	// specific-purpose high-level commands
+	cmdPowerDevOnOff,
+	cmdPowerZoneOnOff,
+	cmdResetDevice,
+	cmdResetZone,
+	cmdAllocateG2UDQM,
+	cmdQSMAvailable,
+	cmdRevision,
+	cmdRegisterCmdHandler,
+	cmdFindUnusedCommand,
+	cmdLockCmdTable,
+	cmdJumpApp,
+	cmdStall,
+	cmdCloseAVS,
+	cmdReadROs,
+	cmdGetTrackTemp,
+	cmdSetTrackTemp,
+#ifdef PMC_IMPL_3_X
+	cmdGetIslandStatus,
+	cmdGetTMON,
+	cmdSetTemperatureThresholds,
+	cmdResetTemperatureWarning,
+#endif
+};
+
+extern void ProcessCommand(TCommand * cmd, TCommand * response);
+
+#endif // PMCCOMMAND_H
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_drv.c b/arch/arm/mach-bcmbca/pmc/pmc_drv.c
new file mode 100755
index 0000000000..1c5c771206
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_drv.c
@@ -0,0 +1,1135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2019 Broadcom Ltd.
+ */
+/*
+
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      Common code for PMC Linux, U-Boot, and ATF drivers 
+ *****************************************************************************/
+
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#include "command.h"
+
+#if IS_BCMCHIP(6858) || defined(PMC_IMPL_3_X)
+// #include "bcm_otp.h" // TODO: add back this after implenting otp util
+#include "clk_rst.h"
+#endif
+
+int pmc_mode = PMC_MODE_DQM;
+
+#ifdef PMC_LOG_IN_DTCM
+void pmc_show_log_item(void)
+{
+	unsigned short i, item_sz;
+	char * dtcm = (char *) PROCMON->dtcm;  
+
+	item_sz = PMC->ctrl.hostMboxOut >> 16;
+
+	for (i = 0; i < item_sz; i++)
+		printk("%c", dtcm[i]);  
+
+	if (item_sz) // reset the item_sz to 0
+		PMC->ctrl.hostMboxOut &= 0xffff;
+}
+
+void pmc_save_log_item(void)
+{
+	char *buf = (char *) phys_to_virt(CFG_BOOT_PMC_LOG_ADDR);
+	unsigned short *plen = (unsigned short *) buf;
+	char *dst = buf + sizeof(*plen) + *plen;
+	unsigned short item_sz = PMC->ctrl.hostMboxOut >> 16;
+	char *dtcm = (char *) PROCMON->dtcm;  
+	int i = 0;
+	
+	while (i < item_sz && *plen < CFG_BOOT_PMC_LOG_SIZE - sizeof(*plen)) {
+		dst[i] = dtcm[i];
+		i++;
+		(*plen)++;
+	}
+
+	if (item_sz) // reset the item_sz to 0
+		PMC->ctrl.hostMboxOut &= 0xffff;
+}
+#endif // #ifdef PMC_LOG_IN_DTCM
+
+static int SendAndWait(TCommand * cmd, TCommand * rsp)
+{
+#if defined(PMC_ON_HOSTCPU)
+	rsp->u.cmdGenericParams.params[0] = 0;
+	rsp->u.cmdGenericParams.params[1] = 0;
+	return 0;
+#else
+#if IS_BCMCHIP(63138)
+	/* translate new cmdID into old cmdID that the pmc will understand NB:
+	 * requires cmdIDs below to be the new versions
+	 */
+
+	static const unsigned char newToOldcmdIDMap[] = {
+		[cmdSetRunState] = 64,	// cmdSetRunState,
+		[cmdSetPowerState] = 65,	// cmdSetPowerState,
+		[cmdShutdownAllowed] = 66,	// cmdShutdownAllowed,
+		[cmdGetSelect0] = 67,	// cmdGetSelect0,
+		[cmdGetSelect3] = 68,	// cmdGetSelect3,
+		[cmdGetAvsDisableState] = 69,	// cmdGetAvsDisableState,
+		[cmdGetPVT] = 70,	// cmdGetPVT,
+		[cmdPowerDevOnOff] = 129,	// cmdPowerDevOnOff,
+		[cmdPowerZoneOnOff] = 130,	// cmdPowerZoneOnOff,
+		[cmdResetDevice] = 131,	// cmdResetDevice,
+		[cmdResetZone] = 132,	// cmdResetZone,
+		[cmdAllocateG2UDQM] = 133,	// cmdAllocateG2UDQM,
+		[cmdQSMAvailable] = 134,	// cmdQSMAvailable,
+		[cmdRevision] = 135,	// cmdRevision,
+	};
+
+	static int pmc_remap = 0;
+#endif
+	static uint32_t reqdID = 1;
+	int status = kPMC_COMMAND_TIMEOUT;
+	TCommand dummy;
+
+#if defined(BOOT_MEMC_SRAM)
+	reqdID = 1;
+#endif
+	pmc_spin_lock();
+
+	/* clear previous rsp data if any */
+	while (PMC->dqm.notEmptySts & PMC_DQM_RPL_STS) {
+		if (!rsp)
+			rsp = &dummy;
+
+		rsp->word0.Reg32 = PMC->dqmQData[PMC_DQM_RPL_NUM].word[0];
+		rsp->word1.Reg32 = PMC->dqmQData[PMC_DQM_RPL_NUM].word[1];
+		rsp->u.cmdGenericParams.params[0] =
+		    PMC->dqmQData[PMC_DQM_RPL_NUM].word[2];
+		rsp->u.cmdGenericParams.params[1] =
+		    PMC->dqmQData[PMC_DQM_RPL_NUM].word[3];
+
+		printk
+		    ("PMC reqdID=%d previous rsp.word[0-3]=0x[%08x %08x %08x %08x] status=%d\n",
+		     reqdID, rsp->word0.Reg32, rsp->word1.Reg32,
+		     rsp->u.cmdGenericParams.params[0],
+		     rsp->u.cmdGenericParams.params[1], rsp->word0.Bits.error);
+	}
+
+#if IS_BCMCHIP(63138)
+	if (pmc_remap && cmd->word0.Bits.cmdID < sizeof newToOldcmdIDMap &&
+	    newToOldcmdIDMap[cmd->word0.Bits.cmdID])
+		cmd->word0.Bits.cmdID = newToOldcmdIDMap[cmd->word0.Bits.cmdID];
+#endif
+
+#ifdef PMC_LOG_IN_DTCM
+	if (cmd->word0.Bits.cmdID == cmdCloseAVS)
+		PMC->ctrl.hostMboxOut = 1; // request sync dtcm log
+#endif
+
+	cmd->word0.Bits.msgID = reqdID;
+
+	/* send the command */
+	PMC->dqmQData[PMC_DQM_REQ_NUM].word[0] = cmd->word0.Reg32;
+	PMC->dqmQData[PMC_DQM_REQ_NUM].word[1] = cmd->word1.Reg32;
+	PMC->dqmQData[PMC_DQM_REQ_NUM].word[2] =
+	    cmd->u.cmdGenericParams.params[0];
+	PMC->dqmQData[PMC_DQM_REQ_NUM].word[3] =
+	    cmd->u.cmdGenericParams.params[1];
+
+#ifdef CONFIG_BRCM_IKOS
+	/* We do not enable PMC TIMER here for IKOS, or it will wait forever */
+	while (!(PMC->dqm.notEmptySts & PMC_DQM_RPL_STS)) ;
+#elif defined(PMC_IMPL_3_X)
+#ifdef PMC_LOG_IN_DTCM
+	if (cmd->word0.Bits.cmdID == cmdCloseAVS) {
+		while (!(PMC->dqm.notEmptySts & PMC_DQM_RPL_STS))
+			pmc_show_log_item();
+
+		PMC->ctrl.hostMboxOut = 0; // ignore dtcm log
+	} 
+	else
+#endif // #ifdef PMC_LOG_IN_DTCM
+	{
+		PMC->ctrl.gpTmr0Ctl = ((1 << 31) | (1 << 29) |
+				((400000 << 1) & 0x1fffffff));	// 400ms
+
+		while (!(PMC->dqm.notEmptySts & PMC_DQM_RPL_STS) &&
+				(PMC->ctrl.gpTmr0Ctl & (1 << 31))) ;
+	}
+#else
+	PMC->ctrl.gpTmr2Ctl = ((1 << 31) | (1 << 29) | 400000);	// 400ms
+
+	while (!(PMC->dqm.notEmptySts & PMC_DQM_RPL_STS) &&
+	       (PMC->ctrl.gpTmr2Ctl & (1 << 31))) {
+#if (IS_BCMCHIP(63148) || IS_BCMCHIP(4908))
+		/* Do not tight poll the PMC registers for longer command */
+		if (cmd->word0.Bits.cmdID == cmdCloseAVS)
+			udelay(1000);
+#endif
+	}
+#endif /* CONFIG_BRCM_IKOS */
+
+	if (PMC->dqm.notEmptySts & PMC_DQM_RPL_STS) {
+		if (!rsp)
+			rsp = &dummy;
+
+		/* command didn't timeout, fill in the response */
+		rsp->word0.Reg32 = PMC->dqmQData[PMC_DQM_RPL_NUM].word[0];
+		rsp->word1.Reg32 = PMC->dqmQData[PMC_DQM_RPL_NUM].word[1];
+		rsp->u.cmdGenericParams.params[0] =
+		    PMC->dqmQData[PMC_DQM_RPL_NUM].word[2];
+		rsp->u.cmdGenericParams.params[1] =
+		    PMC->dqmQData[PMC_DQM_RPL_NUM].word[3];
+
+		if (rsp->word0.Bits.msgID == reqdID)
+			status = rsp->word0.Bits.error;
+		else
+			status = kPMC_MESSAGE_ID_MISMATCH;
+
+		if (status != kPMC_NO_ERROR)
+			printk
+			    ("PMC reqdID=%d error=%d rsp.word[0-3]=0x[%08x %08x %08x %08x]\n",
+			     reqdID, status, rsp->word0.Reg32, rsp->word1.Reg32,
+			     rsp->u.cmdGenericParams.params[0],
+			     rsp->u.cmdGenericParams.params[1]);
+	}
+
+	reqdID = (reqdID + 1) & 0xff;
+
+	pmc_spin_unlock();
+
+	return status;
+#endif
+}
+
+static int SendCmd(TCommand * cmd, int cmdID, int devAddr, int zone, int island,
+		   TCommand * rsp)
+{
+	cmd->word0.Reg32 = 0;
+	cmd->word0.Bits.cmdID = cmdID;
+	cmd->word1.Reg32 = 0;
+	cmd->word1.Bits.devAddr = devAddr;
+	cmd->word1.Bits.zoneIdx = zone;
+	cmd->word1.Bits.island = island;
+
+	return SendAndWait(cmd, rsp);
+}
+
+int SendCommand(int cmdID, int devAddr, int zone, int island, uint32_t word2,
+		uint32_t word3, TCommand * rsp)
+{
+	TCommand cmd;
+
+	cmd.u.cmdGenericParams.params[0] = word2;
+	cmd.u.cmdGenericParams.params[1] = word3;
+
+	return SendCmd(&cmd, cmdID, devAddr, zone, island, rsp);
+}
+
+int GetRevision(uint32_t * change, uint32_t * revision)
+{
+	if (pmc_mode == PMC_MODE_DQM) {
+		TCommand rsp;
+		int status = SendCommand(cmdRevision, 0, 0, 0, 0, 0, &rsp);
+
+		if (status == kPMC_NO_ERROR) {
+			*change = rsp.u.cmdResponse.word2;
+			*revision = rsp.u.cmdResponse.word3;
+		}
+
+		return status;
+	} else
+		return kPMC_INVALID_COMMAND;
+}
+EXPORT_SYMBOL(GetRevision);
+
+#if defined(PMC_IMPL_3_X) || defined(PMC_ON_HOSTCPU)
+#define KEYHOLE_IDX 0
+
+int read_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t * value)
+{
+	int status = kPMC_NO_ERROR;
+	int bus = (devAddr >> PMB_BUS_ID_SHIFT) & 0x3;
+	uint32_t address, ctlSts;
+	volatile PMB_keyhole_reg *keyhole = &PMB->keyhole[KEYHOLE_IDX];
+
+
+	address =
+	    ((devAddr & 0xff) *
+	     ((PMB->
+	       config >> PMB_NUM_REGS_SHIFT) & PMB_NUM_REGS_MASK)) |
+	    (wordOffset);
+
+	keyhole->control =
+	    PMC_PMBM_START | (bus << PMC_PMBM_BUS_SHIFT) | (PMC_PMBM_Read) |
+	    address;
+	ctlSts = keyhole->control;
+	while (ctlSts & PMC_PMBM_BUSY)
+		ctlSts = keyhole->control;	/*wait for completion */
+
+	if (ctlSts & PMC_PMBM_TIMEOUT)
+		status = kPMC_COMMAND_TIMEOUT;
+	else
+		*value = keyhole->rd_data;
+
+	return status;
+}
+
+int write_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t value)
+{
+	int status = kPMC_NO_ERROR;
+	int bus = (devAddr >> PMB_BUS_ID_SHIFT) & 0x3;
+	uint32_t address, ctlSts;
+	volatile PMB_keyhole_reg *keyhole = &PMB->keyhole[KEYHOLE_IDX];
+
+	address =
+	    ((devAddr & 0xff) *
+	     ((PMB->
+	       config >> PMB_NUM_REGS_SHIFT) & PMB_NUM_REGS_MASK)) |
+	    (wordOffset);
+	keyhole->wr_data = value;
+	keyhole->control =
+	    PMC_PMBM_START | (bus << PMC_PMBM_BUS_SHIFT) | (PMC_PMBM_Write) |
+	    address;
+
+	ctlSts = keyhole->control;
+	while (ctlSts & PMC_PMBM_BUSY)
+		ctlSts = keyhole->control;	/*wait for completion */
+
+	if (ctlSts & PMC_PMBM_TIMEOUT)
+		status = kPMC_COMMAND_TIMEOUT;
+
+	return status;
+}
+
+static int is_pvtmon_enabled = 0;
+static void pvtmon_enable(void)
+{
+	uint32_t index;
+	uint32_t target;
+#define PVTCLKDIV (5 << 8)
+
+	pmc_spin_lock();
+
+	// set up analog hardware to enable counting
+	target = PVTCLKDIV | 4;	// 4 = clk_en|!pwr_dn|rstb
+	write_bpcm_reg_direct(PMB_ADDR_PVTMON, 17, target);
+	for (index = 0; index < 100000; index++) ;
+	target = PVTCLKDIV | 5;	// 5 = clk_en|!pwr_dn|!rstb
+	write_bpcm_reg_direct(PMB_ADDR_PVTMON, 17, target);
+
+	// set sample size of ALL counters except TEST (7)
+	// set enable bit for ONLY 0 (temperature and external) and V1p0<0> - these will be the only ones we use during Match and Closure
+	for (index = 0; index < 8; index++) {
+		target = (0x5 << 24) | 0x80000000;	//pvtmon samples (32 [2^5]) + enable
+		write_bpcm_reg_direct(PMB_ADDR_PVTMON, 24 + index, target);
+		read_bpcm_reg_direct(PMB_ADDR_PVTMON, 24 + index, &target);	// read once to clear valid bit
+	}
+
+	// enable accumulation:
+	// 0x00000801 = skip_len = 8, enable accumulation
+	target = 0x00000801;
+	write_bpcm_reg_direct(PMB_ADDR_PVTMON, 20, target);
+	is_pvtmon_enabled = 1;
+
+	pmc_spin_unlock();
+}
+
+#ifndef unlikely
+#define unlikely(x)	(x)
+#endif
+static int read_pvt_direct(int index, int *val)
+{
+	int status;
+	uint32_t target;
+
+	// assuming PVTMON already enabled in DQM mode
+	if (unlikely((pmc_mode != PMC_MODE_DQM) && !is_pvtmon_enabled))
+		pvtmon_enable();
+
+	status = read_bpcm_reg_direct(PMB_ADDR_PVTMON, 24 + index, &target);
+	if (unlikely(status))
+		goto EXIT;
+
+	while (!(target & (1 << 18))) {
+		// the value SHOULD be valid immediatly, but just in case...
+		status =
+		    read_bpcm_reg_direct(PMB_ADDR_PVTMON, 24 + index, &target);
+		if (unlikely(status))
+			goto EXIT;
+	}
+
+	*val = target & 0x3ff;
+
+EXIT:
+	return status;
+}
+
+int GetPVT(int sel, int island, int *value)
+{
+	return read_pvt_direct(sel, value);
+}
+#else // #if defined(PMC_IMPL_3_X) || defined(PMC_ON_HOSTCPU)
+int read_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t * value)
+{
+	int status = kPMC_NO_ERROR;
+	int bus = (devAddr >> PMB_BUS_ID_SHIFT) & 0x3;
+	volatile PMBMaster *pmbm_ptr;
+
+	if (bus >= PMB_BUS_MAX)
+		return kPMC_INVALID_BUS;
+
+	pmbm_ptr = &(PROCMON->PMBM[bus]);
+
+	/* Make sure PMBM is not busy */
+
+	pmbm_ptr->ctrl = PMC_PMBM_START | PMC_PMBM_Read |
+	    ((devAddr & 0xff) << 12) | wordOffset;
+
+	while (pmbm_ptr->ctrl & PMC_PMBM_START) ;
+
+	if (pmbm_ptr->ctrl & PMC_PMBM_TIMEOUT)
+		status = kPMC_COMMAND_TIMEOUT;
+	else
+		*value = pmbm_ptr->rd_data;
+
+	return status;
+}
+
+int write_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t value)
+{
+	int bus = (devAddr >> PMB_BUS_ID_SHIFT) & 0x3;
+	int status = kPMC_NO_ERROR;
+	volatile PMBMaster *pmbm_ptr;
+	if (bus >= PMB_BUS_MAX)
+		return kPMC_INVALID_BUS;
+
+	pmbm_ptr = &(PROCMON->PMBM[bus]);
+
+	pmbm_ptr->wr_data = value;
+	pmbm_ptr->ctrl = PMC_PMBM_START | PMC_PMBM_Write |
+	    ((devAddr & 0xff) << 12) | wordOffset;
+
+	while (pmbm_ptr->ctrl & PMC_PMBM_START) ;
+
+	if (pmbm_ptr->ctrl & PMC_PMBM_TIMEOUT)
+		status = kPMC_COMMAND_TIMEOUT;
+
+	return status;
+}
+
+int GetPVT(int sel, int island, int *value)
+{
+	if (pmc_mode == PMC_MODE_DQM) {
+		TCommand rsp;
+		int status = SendCommand(cmdGetPVT, 0, 0, island, sel, 0, &rsp);
+
+		if (status == kPMC_NO_ERROR)
+			*value = rsp.u.cmdResponse.word2;
+		return status;
+	} else
+		return kPMC_INVALID_COMMAND;
+}
+#endif // #if defined(PMC_IMPL_3_X) || defined(PMC_ON_HOSTCPU)
+EXPORT_SYMBOL(GetPVT);
+
+/* GetRCalSetting reads resistor value and calculates the calibration setting for the SGMII, PCIe, SATA
+   and USB HW blocks that requires resistor calibration to meet specification requirement.
+   The HW driver should call this function and write the value to calibration register during initialzation
+
+   input param: resistor - the resistor type that specific HW calibration care about:
+   inout param: rcal - 4 bit RCAL value [0 -15] representing the increment or decrement to the internal resistor.   
+   return: kPMC_NO_ERROR or kPMC_INVALID_COMMAND if error condition
+*/
+int GetRCalSetting(int resistor, int *rcal)
+{
+#if defined(PMC_GETRCAL_SUPPORT) 
+	int res_int, res_ext, ratio, ratio1;
+	int rc = kPMC_NO_ERROR;
+
+	if (pmc_mode == PMC_MODE_DQM) {
+#if IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(6756)
+		TCommand rsp;
+		int status;
+
+		/* make sure the resistor selection is valid */
+		/* Not supporting the other resistors because there is no room in DQM RSP */
+		if (resistor < RCAL_1UM_HORZ || resistor > RCAL_1UM_VERT)
+			return kPMC_INVALID_COMMAND;
+
+		status = SendCommand(cmdGetRMON, 0, 0, 0, 0, 0, &rsp);
+		if (status != kPMC_NO_ERROR)
+			return kPMC_INVALID_COMMAND;
+
+		/* make sure the resistor data is collected by PMC */
+		if (!(rsp.u.cmdResponse.word3 & (1 << 16)))
+			return kPMC_INVALID_STATE;
+
+		res_int = rsp.u.cmdResponse.word2;
+		res_ext = rsp.u.cmdResponse.word3 & 0xffff;
+#else
+		/* make sure the resistor selection is valid */
+		if (resistor < RCAL_0P25UM_HORZ || resistor > RCAL_1UM_VERT)
+			return kPMC_INVALID_COMMAND;
+
+		/* make sure the resistor data is collected by PMC */
+		if ((PROCMON->Misc.
+		     misc[PMMISC_RMON_EXT_REG] & PMMISC_RMON_VALID_MASK) == 0)
+			return kPMC_INVALID_COMMAND;
+
+		res_int = PROCMON->Misc.misc[resistor >> 1];
+		res_ext = (PROCMON->Misc.misc[PMMISC_RMON_EXT_REG]) & 0xffff;
+#endif
+		if (resistor % 2)
+			res_int >>= 16;
+		res_int &= 0xffff;
+
+		/* Return error if the res_ext saturated such as
+		   the ext resistor is not available */
+		if (res_ext > 0x3a0) {
+			printk("%s:res_ext value 0x%x is saturated!\n",
+			       __func__, res_ext);
+			return kPMC_INVALID_STATE;
+		}
+
+		/* Ratio = CLAMP((INT) (128.0 * V(REXT)/V(RINT)), 0, 255) */
+		ratio = (128 * res_ext) / res_int;
+		if (ratio > 255)
+			ratio = 255;
+
+		/* Ratio1 = CLAMP(128 - (Ratio - 128) * 4, 0, 255) */
+		ratio1 = (128 - (ratio - 128) * 4);
+		if (ratio1 < 0)
+			ratio1 = 0;
+		if (ratio1 > 255)
+			ratio1 = 255;
+
+		/* convert to 4 bit rcal setting value */
+		*rcal = (ratio1 >> 4) & 0xf;
+#if 1
+		printk
+		    ("getrcal for res select %d, int %d, ext %d, ratio %d ratio1 %d, rcal %d\n",
+		     resistor, res_int, res_ext, ratio, ratio1, *rcal);
+#endif
+	} else {
+		/* not supported if PMC is not running for now. To support that, need to copy the PMC rom 
+		   code to read out resistor value manually */
+		rc = kPMC_INVALID_COMMAND;
+	}
+
+	return rc;
+#else
+    return kPMC_INVALID_COMMAND;
+#endif
+}
+
+EXPORT_SYMBOL(GetRCalSetting);
+
+/* note: all the [Read|Write][BPCM|Zone]Register functions are different from
+ * how they are defined in firmware code.  In the driver code, it takes in
+ * wordOffset as the argument, but in the firmware code, it uses byteOffset */
+int ReadBPCMRegister(int devAddr, int wordOffset, uint32_t * value)
+{
+	int status = kPMC_INVALID_STATE;
+
+	if (PMC_ACCESS_BPCM_DIRECT || pmc_mode == PMC_MODE_PMB_DIRECT) {
+		pmc_spin_lock();
+		status = read_bpcm_reg_direct(devAddr, wordOffset, value);
+		pmc_spin_unlock();
+	} else if (pmc_mode == PMC_MODE_DQM) {
+		TCommand rsp;
+		status =
+		    SendCommand(cmdReadBpcmReg, devAddr, 0, 0, wordOffset, 0,
+				&rsp);
+
+		if (status == kPMC_NO_ERROR)
+			*value = rsp.u.cmdResponse.word2;
+	}
+
+	return status;
+}
+
+EXPORT_SYMBOL(ReadBPCMRegister);
+
+int ReadZoneRegister(int devAddr, int zone, int wordOffset, uint32_t * value)
+{
+	int status = kPMC_INVALID_STATE;
+
+	if ((unsigned)wordOffset >= 4)
+		return kPMC_INVALID_PARAM;
+
+	if (PMC_ACCESS_BPCM_DIRECT || pmc_mode == PMC_MODE_PMB_DIRECT)
+		return ReadBPCMRegister(devAddr,
+					BPCMRegOffset(zones[zone].control) +
+					wordOffset, value);
+
+	if (pmc_mode == PMC_MODE_DQM) {
+		TCommand rsp;
+
+		status =
+		    SendCommand(cmdReadZoneReg, devAddr, zone, 0, wordOffset, 0,
+				&rsp);
+		if (status == kPMC_NO_ERROR)
+			*value = rsp.u.cmdResponse.word2;
+	}
+
+	return status;
+}
+
+EXPORT_SYMBOL(ReadZoneRegister);
+
+int WriteBPCMRegister(int devAddr, int wordOffset, uint32_t value)
+{
+	int status = kPMC_INVALID_STATE;
+
+	if (PMC_ACCESS_BPCM_DIRECT || pmc_mode == PMC_MODE_PMB_DIRECT) {
+		pmc_spin_lock();
+		status = write_bpcm_reg_direct(devAddr, wordOffset, value);
+		pmc_spin_unlock();
+	} else if (pmc_mode == PMC_MODE_DQM) {
+		status =
+		    SendCommand(cmdWriteBpcmReg, devAddr, 0, 0, wordOffset,
+				value, 0);
+	}
+
+	return status;
+}
+
+EXPORT_SYMBOL(WriteBPCMRegister);
+
+int WriteZoneRegister(int devAddr, int zone, int wordOffset, uint32_t value)
+{
+	if ((unsigned)wordOffset >= 4)
+		return kPMC_INVALID_PARAM;
+
+	if (PMC_ACCESS_BPCM_DIRECT || pmc_mode == PMC_MODE_PMB_DIRECT)
+		return WriteBPCMRegister(devAddr,
+					 BPCMRegOffset(zones[zone].control) +
+					 wordOffset, value);
+
+	if (pmc_mode == PMC_MODE_DQM)
+		return SendCommand(cmdWriteZoneReg, devAddr, zone, 0,
+				   wordOffset, value, 0);
+
+	return kPMC_INVALID_STATE;
+}
+
+EXPORT_SYMBOL(WriteZoneRegister);
+
+int PowerOnDevice(int devAddr)
+{
+	if (PMC_ACCESS_BPCM_DIRECT || pmc_mode == PMC_MODE_PMB_DIRECT) {
+		int ix, status;
+		BPCM_CAPABILITES_REG capabilities;
+
+		status =
+		    ReadBPCMRegister(devAddr, BPCMRegOffset(capabilities),
+				     &capabilities.Reg32);
+		for (ix = 0;
+		     (ix < capabilities.Bits.num_zones)
+		     && (status == kPMC_NO_ERROR); ix++) {
+			status = PowerOnZone(devAddr, ix);
+		}
+
+		return status;
+	}
+
+	if (pmc_mode == PMC_MODE_DQM) {
+		TCommand cmd = {0};
+		cmd.u.cmdPowerDevice.state = 1;
+		return SendCmd(&cmd, cmdPowerDevOnOff, devAddr, 0, 0, 0);
+	}
+
+	return kPMC_INVALID_STATE;
+}
+
+EXPORT_SYMBOL(PowerOnDevice);
+
+int PowerOffDevice(int devAddr, int repower)
+{
+	if (PMC_ACCESS_BPCM_DIRECT || pmc_mode == PMC_MODE_PMB_DIRECT) {
+		/* we can power off the entire device by powering off the 0th zone. */
+		BPCM_PWR_ZONE_N_CONTROL reg;
+		int status;
+
+		status =
+		    ReadBPCMRegister(devAddr, BPCMRegOffset(zones[0].control),
+				     &reg.Reg32);
+
+		if (status == kPMC_NO_ERROR && reg.Bits.pwr_off_state == 0) {
+			reg.Bits.pwr_dn_req = 1;
+			WriteBPCMRegister(devAddr,
+					  BPCMRegOffset(zones[0].control),
+					  reg.Reg32);
+		}
+
+		return status;
+	}
+
+	if (pmc_mode == PMC_MODE_DQM) {
+		TCommand cmd = {0};
+		cmd.u.cmdPowerDevice.state = 0;
+		cmd.u.cmdPowerDevice.restore = repower;
+		return SendCmd(&cmd, cmdPowerDevOnOff, devAddr, 0, 0, 0);
+	}
+
+	return kPMC_INVALID_STATE;
+}
+
+EXPORT_SYMBOL(PowerOffDevice);
+
+int PowerOnZone(int devAddr, int zone)
+{
+	BPCM_PWR_ZONE_N_CONTROL reg;
+	int status;
+
+#if IS_BCMCHIP(6858)
+	/* Do not use DQM command cmdPowerZoneOnOff for non 6858 because this command is only available if a
+	   PMC application has been uploaded to expand the PMC boot rom functionality */
+	if (pmc_mode == PMC_MODE_DQM) {
+		TCommand cmd = {0};
+		cmd.u.cmdStateOnlyParam.state = 1;
+		return SendCmd(&cmd, cmdPowerZoneOnOff, devAddr, zone, 0, 0);
+	}
+#endif
+
+	status =
+	    ReadBPCMRegister(devAddr, BPCMRegOffset(zones[zone].control),
+			     &reg.Reg32);
+	if (status == kPMC_NO_ERROR && reg.Bits.pwr_on_state == 0) {
+		reg.Bits.pwr_dn_req = 0;
+		reg.Bits.dpg_ctl_en = 1;
+		reg.Bits.pwr_up_req = 1;
+		reg.Bits.mem_pwr_ctl_en = 1;
+		reg.Bits.blk_reset_assert = 1;
+		status =
+		    WriteBPCMRegister(devAddr,
+				      BPCMRegOffset(zones[zone].control),
+				      reg.Reg32);
+	}
+	return status;
+}
+
+EXPORT_SYMBOL(PowerOnZone);
+
+int PowerOffZone(int devAddr, int zone)
+{
+	BPCM_PWR_ZONE_N_CONTROL reg;
+	int status;
+
+#if IS_BCMCHIP(6858)
+	/* Do not use DQM command cmdPowerZoneOnOff for non 6858 because this command is only available if a
+	   PMC application has been uploaded to expand the PMC boot rom functionality */
+	if (pmc_mode == PMC_MODE_DQM) {
+		TCommand cmd = {0};
+		cmd.u.cmdStateOnlyParam.state = 0;
+		return SendCmd(&cmd, cmdPowerZoneOnOff, devAddr, zone, 0, 0);
+	}
+#endif
+
+	status =
+	    ReadBPCMRegister(devAddr, BPCMRegOffset(zones[zone].control),
+			     &reg.Reg32);
+	if (status == kPMC_NO_ERROR) {
+		reg.Bits.pwr_dn_req = 1;
+		reg.Bits.pwr_up_req = 0;
+		status =
+		    WriteBPCMRegister(devAddr,
+				      BPCMRegOffset(zones[zone].control),
+				      reg.Reg32);
+	}
+	return status;
+}
+
+EXPORT_SYMBOL(PowerOffZone);
+
+int ResetDevice(int devAddr)
+{
+	/* all zones had their blk_reset_assert bits set at initial config time */
+	BPCM_PWR_ZONE_N_CONTROL reg;
+	int status;
+
+#if IS_BCMCHIP(6858)
+	/* Do not use DQM command cmdResetDevice for non 6858 because this command is only available if a
+	   PMC application has been uploaded to expand the PMC boot rom functionality */
+	if (pmc_mode == PMC_MODE_DQM)
+		return SendCommand(cmdResetDevice, devAddr, 0, 0, 0, 0, 0);
+#endif
+
+	status = PowerOffDevice(devAddr, 0);
+	do {
+		status =
+		    ReadBPCMRegister(devAddr, BPCMRegOffset(zones[0].control),
+				     &reg.Reg32);
+	} while ((reg.Bits.pwr_off_state != 1) && (status == kPMC_NO_ERROR));
+	if (status == kPMC_NO_ERROR)
+		status = PowerOnDevice(devAddr);
+	return status;
+}
+
+EXPORT_SYMBOL(ResetDevice);
+
+int ResetZone(int devAddr, int zone)
+{
+	BPCM_PWR_ZONE_N_CONTROL reg;
+	int status;
+
+#if IS_BCMCHIP(6858)
+	/* Do not use DQM command cmdResetZone for non 6858 because this command is only available if a
+	   PMC application has been uploaded to expand the PMC boot rom functionality */
+	if (pmc_mode == PMC_MODE_DQM)
+		return SendCommand(cmdResetZone, devAddr, zone, 0, 0, 0, 0);
+#endif
+
+	status = PowerOffZone(devAddr, zone);
+	do {
+		status =
+		    ReadBPCMRegister(devAddr,
+				     BPCMRegOffset(zones[zone].control),
+				     &reg.Reg32);
+	} while ((reg.Bits.pwr_off_state != 1) && (status == kPMC_NO_ERROR));
+	if (status == kPMC_NO_ERROR)
+		status = PowerOnZone(devAddr, zone);
+	return status;
+}
+
+EXPORT_SYMBOL(ResetZone);
+
+/* close AVS with margin slow, fast, max, min (mV) */
+int CloseAVS(int island, unsigned short margin_mv_slow,
+	     unsigned short margin_mv_fast, unsigned short maximum_mv,
+	     unsigned short minimum_mv)
+{
+	if (pmc_mode == PMC_MODE_DQM) {
+		TCommand rsp;
+		int status;
+
+#if defined(PMC_IMPL_3_X) || IS_BCMCHIP(63158)
+		TCommandCloseAVS ca;
+
+		if (minimum_mv && maximum_mv && (minimum_mv > maximum_mv))
+			return kPMC_INVALID_PARAM;
+
+		ca.margin_mv_slow = margin_mv_slow;
+		ca.margin_mv_fast = margin_mv_fast;
+		ca.maximum_mv = maximum_mv;
+		ca.minimum_mv = minimum_mv;
+
+		status = SendCommand(cmdCloseAVS, 0, 0, island,
+				     ca.word2, ca.word3, &rsp);
+#else
+		status = SendCommand(cmdCloseAVS, 0, 0, island,
+				     margin_mv_slow, margin_mv_fast, &rsp);
+#endif
+
+		return status;
+	} else
+		return kPMC_INVALID_COMMAND;
+}
+
+EXPORT_SYMBOL(CloseAVS);
+
+#if !defined(PMC_ON_HOSTCPU) 
+int PMCcmd(int arg[4])
+{
+	TCommand *cmd = (TCommand *) arg;
+
+	return SendAndWait(cmd, cmd);
+}
+
+#if PMC_BOOT_TMO_SECONDS
+static void pmc_dump_misc_block_regs(void) 
+{
+	static const struct {
+		uint32_t *offset;
+		uint32_t count;
+		const char *name;
+	} regs[] = {
+		{ (void*)&PROCMON->maestroReg.coreCtrl.coreEnable,
+			1, "corectrl_core_enable" },
+		{ (void*)&PROCMON->maestroReg.coreCtrl.coreResetCause,
+			1, "corectrl_core_reset_cause" },
+		{ (void*)&PROCMON->maestroReg.coreCtrl.sysFlg0Status,
+			1, "corectrl_sys_flg0_status" },
+		{ (void*)&PROCMON->maestroReg.coreCtrl.usrFlg0Status,
+			1, "corectrl_usr_flg0_status" },
+		{ (void*)&PROCMON->maestroReg.coreCtrl.resetVector,
+			1, "corectrl_reset_vector" },
+		{ (void*)&PROCMON->maestroReg.coreState.sysMbx[0],
+			8, "corestate_sys_mbx0..7" },
+		{ (void*)&PROCMON->maestroReg.coreState.usrMbx[0],
+			8, "corestate_usr_mbx0..7" },
+		{ (void*)&PROCMON->maestroReg.profile.lastConfPcLo,
+			1, "profile_last_conf_pc_lo" },
+		{ (void*)&PROCMON->maestroReg.profile.lastPcLo,
+			1, "profile_last_pc_lo" },
+		{ (void*)&PMC->ctrl.scratch,
+			1, "control_scratch" },
+	};
+
+	int i, j;
+
+	for (i = 0; i < sizeof(regs) / sizeof(regs[0]); i++) {
+		printk("\tmd.l 0x%p %x ## %s",
+				regs[i].offset, regs[i].count, regs[i].name);
+		for (j = 0; j < regs[i].count; j++) {
+			if (!(j%4)) printk("\n%p:", regs[i].offset+j);
+			printk(" %08x", *(regs[i].offset + j));
+		}
+		printk("\n");
+	}
+}
+#endif
+
+void WaitPmc(int runState, void *pmc_log)
+{
+	int cur, failed;
+#ifdef PMC_IMPL_3_X
+	char *log_buffer_start = (char *)(pmc_log)+4;
+	char *log_buffer_itter = log_buffer_start;
+#endif
+
+	if (pmc_mode != PMC_MODE_DQM)
+		return;
+
+	failed = 0;
+#if PMC_BOOT_TMO_SECONDS
+	PMC->ctrl.gpTmr0Ctl = (1 << 31) | (1 << 29) |
+			(((PMC_BOOT_TMO_SECONDS * 1000000) << 1) & 0x1fffffff);
+#endif
+
+	do {
+#ifdef PMC_LOG_IN_DTCM
+		pmc_save_log_item();
+#endif
+		cur = PMC->ctrl.hostMboxIn;
+#ifdef PMC_IMPL_3_X
+#define PMC_CHIP_NOT_VALID (0x7<<5)
+		if ((cur & PMC_CHIP_NOT_VALID) == PMC_CHIP_NOT_VALID) {
+			printk("**ERR**: PMC firmware is not compatible to this chip\n");
+			failed = 1;
+			PROCMON->maestroReg.coreCtrl.coreEnable = 0;
+			break;
+		}
+
+#if PMC_BOOT_TMO_SECONDS
+		if (!PROCMON->maestroReg.coreCtrl.coreEnable) {
+			printk("**ERR**: PMC firmware crashed\n");
+			failed = 1;
+			pmc_dump_misc_block_regs();
+			break;
+		}
+		if (!(PMC->ctrl.gpTmr0Ctl & (1 << 31))) {
+			printk("**ERR**: %u seconds passed\n", PMC_BOOT_TMO_SECONDS);
+			failed = 1;
+			PROCMON->maestroReg.coreCtrl.coreEnable = 0;
+			pmc_dump_misc_block_regs();
+			break;
+		}
+#endif
+
+		if (pmc_log)
+		{
+			if (*(unsigned int *)(log_buffer_start - 4) == 0xc0ffee55) 
+			{
+				while(*log_buffer_itter && *log_buffer_itter != 0xff)
+				{
+					printf("%c", *log_buffer_itter);
+					log_buffer_itter++;
+					if(log_buffer_itter == (log_buffer_start + CFG_BOOT_PMC_LOG_SIZE))
+						log_buffer_itter = log_buffer_start;
+				}
+			}
+		}
+
+#else /* #ifdef PMC_IMPL_3_X */
+		cur >>= 24;
+		/* Check if PMC is failing */
+		if ((cur & 7) == kPMCRunStateStalled) {
+			failed = 1;
+			/* Leave PMC in reset state */
+			PMC->ctrl.softResets = 0x1;
+			break;
+		}
+#endif /* #ifdef PMC_IMPL_3_X */
+	} while ((cur & 7) != runState);
+
+	if (!failed) return;
+
+	printk("**ERR**: PMC firmware failed to boot\n"
+		"\tPress any key to continue ...\n");
+	while (!console_status()) ;
+	/* PMC is now in direct mode */
+	pmc_mode = PMC_MODE_PMB_DIRECT;
+}
+
+void BootPmcNoRom(unsigned long physAddr)
+{
+	PMC->ctrl.addr1WndwMask = 0xffffc000;
+	PMC->ctrl.addr1WndwBaseIn = 0x1fc00000;
+	PMC->ctrl.addr1WndwBaseOut = physAddr;
+
+	PMC->ctrl.softResets &= ~1;
+}
+#endif
+
+/* new pmc firmware implements stall command */
+/* state indicated by stalled bit in run status */
+
+#define PMC_STALLED (1 << 30)
+
+/* return value doesn't appear to be used */
+int StallPmc(void)
+{
+#if defined(PMC_STALL_SUPPORT) 
+	TCommand rsp;
+
+	/* ignore if pmc not booted from flash or already stalled */
+	if (pmc_mode == PMC_MODE_PMB_DIRECT ||
+#if defined MISC_STRAP_BUS_PMC_BOOT_FLASH
+	    (MISC->miscStrapBus & MISC_STRAP_BUS_PMC_BOOT_FLASH) == 0 ||
+#else
+	    (MISC->miscStrapBus & MISC_STRAP_BUS_PMC_BOOT_FLASH_N) != 0 ||
+#endif
+	    PMC->ctrl.hostMboxIn & PMC_STALLED)
+		return 0;
+
+	/* return non-zero if stall command fails */
+	return SendCommand(cmdStall, 0, 0, 0, 0, 0, &rsp);
+#else
+    return kPMC_INVALID_COMMAND;
+#endif
+}
+
+EXPORT_SYMBOL(StallPmc);
+
+/* return value doesn't appear to be used */
+int UnstallPmc(void)
+{
+#if defined(PMC_STALL_SUPPORT) 
+	/* clear stalled bit if pmc booted from flash */
+	if ((pmc_mode != PMC_MODE_PMB_DIRECT) &&
+#if defined MISC_STRAP_BUS_PMC_BOOT_FLASH
+	    ((MISC->miscStrapBus & MISC_STRAP_BUS_PMC_BOOT_FLASH) != 0))
+#else
+	    ((MISC->miscStrapBus & MISC_STRAP_BUS_PMC_BOOT_FLASH_N) == 0))
+#endif
+	    PMC->ctrl.hostMboxIn &= ~PMC_STALLED;
+
+#endif
+	return 0;
+}
+
+EXPORT_SYMBOL(UnstallPmc);
+
+// initalize pmc_mode (possibly) before printk available
+void pmc_initmode(void)
+{
+#if defined MISC_STRAP_BUS_PMC_ROM_BOOT
+	/* read the strap pin and based on the strap pin, choose the mode */
+	if ((MISC->miscStrapBus & MISC_STRAP_BUS_PMC_ROM_BOOT) == 0)
+		pmc_mode = PMC_MODE_PMB_DIRECT;
+#else // #if defined MISC_STRAP_BUS_PMC_ROM_BOOT
+	pmc_mode = PMC_MODE_PMB_DIRECT;
+#ifdef CFG_RAMAPP
+#if IS_BCMCHIP(63158)
+	/* MIPS based PMC */
+	if (PMC->ctrl.softResets == 0)
+		pmc_mode = PMC_MODE_DQM;
+#elif defined(PMC_IMPL_3_X)
+	/* Maestro based PMC) */
+	if (PROCMON->maestroReg.coreCtrl.coreEnable == 1)
+		pmc_mode = PMC_MODE_DQM;
+#endif // #if IS_BCMCHIP(63158)
+#endif // #ifdef CFG_RAMAPP
+#endif // #if defined MISC_STRAP_BUS_PMC_ROM_BOOT
+}
+
+void pmc_reset(void)
+{
+#if IS_BCMCHIP(63158)
+	// First, make sure PMC core is held in reset
+	PMC->ctrl.softResets = 0x1;
+	// Set PVTMON in non-AVS mode
+	PMC->pvtmon[0].cfg_lo = PMC->pvtmon[0].cfg_lo & ~(0x7 << 10);
+	PMC->pvtmon[1].cfg_lo = PMC->pvtmon[1].cfg_lo & ~(0x7 << 10);
+	// PMC now in direct mode
+	pmc_mode = PMC_MODE_PMB_DIRECT;
+#endif
+}
+
+int pmc_convert_pvtmon(int sel, int value)
+{
+#if IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
+	switch (sel) {
+	case kTEMPERATURE:	// convert value to milli-degree Celsius
+		return (45000000 - 54956 * value) / 100;
+	case kV_0p85_0:		// convert value to milli-voltage
+	case kV_0p85_1:
+	case kV_VIN:
+	case kV_1p00_1:
+		return 9442 * value / (8 * 1024);
+	case kV_1p80:
+		return 9442 * value / (4 * 1024);
+	case kV_3p30:
+		return 9442 * value / (2 * 1024);
+	case kTEST:
+		return 9442 * value / 1024;
+	}
+#else // #if IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
+	switch (sel) {
+	case kTEMPERATURE:	// convert value to milli-degree Celsius
+#if IS_BCMCHIP(63148)		// pvt2
+		return (38887551 - 466415 * value / 10) / 100;
+#elif defined(PMC_IMPL_3_X) || IS_BCMCHIP(6878) || IS_BCMCHIP(6855)
+		return (41335000 - 49055 * value) / 100;
+#else
+		return (41004000 - 48705 * value) / 100;
+#endif
+	case kV_0p85_0:	// convert value to milli-voltage
+	case kV_0p85_1:
+		return 880 * value * 10 / (10 * 1024);
+	case kV_VIN:
+	case kV_1p00_1:
+		return 880 * value * 10 / (7 * 1024);
+	case kV_1p80:
+		return 880 * value * 10 / (4 * 1024);
+	case kV_3p30:
+		return 880 * value * 10 / (2 * 1024);
+	case kTEST:
+		return 880 * value / 1024;
+	}
+#endif // #if IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
+
+	return -1;
+}
+
+EXPORT_SYMBOL(pmc_convert_pvtmon);
+
+int pmc_get_tracktemp(int *status)
+{
+	TCommand rsp;
+	int ret;
+
+	if (pmc_mode != PMC_MODE_DQM)
+		return kPMC_INVALID_COMMAND;
+
+	ret = SendCommand(cmdGetTrackTemp, 0, 0, 0, 0, 0, &rsp);
+	if (ret == kPMC_NO_ERROR)
+		*status = ! !rsp.u.cmdResponse.word2;
+
+	return ret;
+}
+
+int pmc_set_tracktemp(int enable)
+{
+	if (pmc_mode != PMC_MODE_DQM)
+		return kPMC_INVALID_COMMAND;
+
+	return SendCommand(cmdSetTrackTemp, 0, 0, 0, ! !enable, 0, NULL);
+}
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_drv_bootloader.c b/arch/arm/mach-bcmbca/pmc/pmc_drv_bootloader.c
new file mode 100644
index 0000000000..a3af615f4f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_drv_bootloader.c
@@ -0,0 +1,539 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2019 Broadcom Ltd.
+ */
+/*
+
+*/
+
+/*****************************************************************************
+ *  Description:
+ *      PMC driver code for bootloaders 
+ *****************************************************************************/
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+#include "command.h"
+
+extern int pmc_mode;
+
+#if defined(PMC_RAM_BOOT)
+/* Include the platform specific PMC boot code */
+#if IS_BCMCHIP(63178)
+#include "pmc_firmware_63178.h"
+#elif IS_BCMCHIP(47622)
+#include "pmc_firmware_47622.h"
+#elif IS_BCMCHIP(6756)
+#include "pmc_firmware_6756.h"
+#elif IS_BCMCHIP(63158)
+#include "pmc_romdata_63158.h"
+#elif IS_BCMCHIP(6846)
+#include "pmc_firmware_68460.h"
+#elif IS_BCMCHIP(6856)
+#include "pmc_firmware_68560.h"
+#elif IS_BCMCHIP(63146)
+#include "pmc_firmware_63146.h"
+#elif IS_BCMCHIP(4912)
+#include "pmc_firmware_4912.h"
+#endif
+
+#if IS_BCMCHIP(63158)
+// PMC boot options and parameters
+typedef struct PMCBootOption {
+	unsigned int option;	// Boot option
+	unsigned int opt_param;	// Parameter to boot option
+} __attribute__ ((packed)) TPMCBootOption;
+
+typedef struct PMCBootParams {
+	unsigned int pmc_image_addr;	// PMC image address
+	unsigned int pmc_image_size;	// PMC image size
+	unsigned int pmc_image_max_size;	// PMC max size
+	unsigned int pmc_boot_option_cnt;	// Number of boot options
+} __attribute__ ((packed)) TPMCBootParams;
+
+#define LOCATE_BOOT_OPTIONS(a) ((long)(a) + sizeof(TPMCBootParams))
+
+typedef struct PMCBootLog {
+	int cfe_rd_idx;		// PMC read index
+	int pmc_log_type;	// PMC log type
+} __attribute__ ((packed)) TPMCBootLog;
+
+TPMCBootParams *pmcBootParams = NULL;
+
+void set_pmc_boot_param(unsigned int boot_option, unsigned int boot_param)
+{
+	void *bootParamEnd =
+	    (void *)pmcBootParams + sizeof(TPMCBootParams) +
+	    (pmcBootParams->pmc_boot_option_cnt + 1) * sizeof(TPMCBootOption);
+	TPMCBootOption *bootOptions = NULL;
+
+	// check boot parameters do not corss the boundary
+	if ((unsigned long)bootParamEnd >
+	    pmcBootParams->pmc_image_addr + pmcBootParams->pmc_image_max_size) {
+		printk
+		    ("Error: %s : Space not available for PMC boot parameter\n",
+		     __func__);
+		return;
+	}
+	// Locate boot option area
+	bootOptions = (TPMCBootOption *) LOCATE_BOOT_OPTIONS(pmcBootParams);
+	// set boot options
+	switch (boot_option) {
+	case kPMCBootDefault:
+		pmcBootParams->pmc_boot_option_cnt = 0;
+		break;
+	case kPMCBootAVSDisable:
+	case kPMCBootAVSTrackDisable:
+	case kPMCBootLogBuffer:
+	case kPMCBootLogSize:
+		bootOptions[pmcBootParams->pmc_boot_option_cnt].option =
+		    boot_option;
+		bootOptions[pmcBootParams->pmc_boot_option_cnt].opt_param =
+		    boot_param;
+		pmcBootParams->pmc_boot_option_cnt++;
+		break;
+	default:
+		printk("Error: %s : Invalid PMC boot option\n", __func__);
+	}
+}
+
+int get_pmc_boot_param(unsigned int boot_option, unsigned int *boot_param)
+{
+	TPMCBootOption *bootOptions;
+	int i;
+	// Locate boot option area
+	bootOptions = (TPMCBootOption *) LOCATE_BOOT_OPTIONS(pmcBootParams);
+
+	for (i = 0; pmcBootParams && i < pmcBootParams->pmc_boot_option_cnt;
+	     i++) {
+		if (bootOptions[i].option == boot_option) {
+			*boot_param = bootOptions[i].opt_param;
+			return 0;
+		}
+	}
+	return -1;
+}
+
+void init_pmc_boot_param(long image_addr, int image_size, int max_size)
+{
+	// loacate boot parameter location at the end of image.
+	pmcBootParams =
+	    (TPMCBootParams *) (image_addr + image_size -
+				sizeof(TPMCBootParams));
+	// Set boot param related global variables
+	pmcBootParams->pmc_image_addr = image_addr;
+	pmcBootParams->pmc_image_size = image_size;
+	pmcBootParams->pmc_image_max_size = max_size;
+	// Set default option
+	set_pmc_boot_param(kPMCBootDefault, 0);
+	printk("Boot pmc_image_addr 0x%08X\n", pmcBootParams->pmc_image_addr);
+	printk("Boot pmc_image_size 0x%08X\n", pmcBootParams->pmc_image_size);
+	printk("Boot pmc_image_max_size 0x%08X\n",
+	       pmcBootParams->pmc_image_max_size);
+}
+#endif
+
+#ifdef PMC_LOG_IN_DTCM
+static void pmc_show_boot_log(void)
+{
+	int i;
+
+	printk("\n---start of pmc firmware boot log---\n");
+
+	for (i = 0; i < *(unsigned short *) CFG_BOOT_PMC_LOG_ADDR; i++)
+		printk("%c", *(char *) (CFG_BOOT_PMC_LOG_ADDR +
+					sizeof(unsigned short) + i));
+
+	printk("\n====end of pmc firmware boot log====\n");
+}
+
+static void pmc_show_live_log(void)
+{
+	printk("start showing pmc firmware live log, "
+			"press any key to stop ...\n");
+	PMC->ctrl.hostMboxOut = 1; // request sync dtcm log
+	while (!console_status())
+		pmc_show_log_item();
+	PMC->ctrl.hostMboxOut = 0; // ignore dtcm log
+	printk("\n... key pressed, stop showing pmc firmware live log.\n");
+}
+#endif
+
+void pmc_log(int log_type)
+{
+#if defined(PMC_SHARED_MEMORY)
+	static char cache_buffer[CFG_BOOT_PMC_LOG_SIZE];
+	unsigned int log_location = 0;
+	unsigned int log_size = 0;
+
+	/* Do log, only if log buffer and log buffer size is known */
+	if ((get_pmc_boot_param(kPMCBootLogBuffer, &log_location) != -1) &&
+	    (get_pmc_boot_param(kPMCBootLogSize, &log_size) != -1)) {
+		TPMCBootLog *log_header = (TPMCBootLog *) PMC_SHARED_MEMORY;
+		char *log_buffer = (char *)cache_to_uncache(log_location);
+		char *format_str = NULL;
+		unsigned int value[10];
+
+		/* Let PMC know, CFE wants to read from the begining */
+		log_header->cfe_rd_idx = 0;
+		log_header->pmc_log_type = log_type;
+
+		/* Keep pumping out the log */
+		while (1) {
+			int i = 0, fmt_cnt = 0, avl_to_process = 0;
+			int pmc_wr, cfe_rd;
+
+			/* Wait until log is available in the buffer */
+			do {
+				pmc_wr = PMC->ctrl.scratch;
+				cfe_rd = log_header->cfe_rd_idx;
+				/* Exit if key is pressed */
+				if (console_status()) {
+					/* Let PMC know that CFE is not interested in reading log */
+					log_header->cfe_rd_idx = -1;
+					return;
+				}
+			} while (pmc_wr == cfe_rd);
+
+			avl_to_process =
+			    (pmc_wr + log_size - cfe_rd) % log_size;
+
+#ifdef __UBOOT__
+			flush_dcache_all();
+#endif
+			/* Read from the circular log buffer into the cache buffer */
+			if (cfe_rd > pmc_wr) {
+				/* step 1: Copy from cfe_rd to the end of log_buffer */
+				memcpy((void *)cache_buffer,
+				       (void *)&log_buffer[cfe_rd],
+				       log_size - cfe_rd);
+				/* step 2: Copy from the begining of the log_buffer to pmc_wr */
+				memcpy((void *)(cache_buffer + log_size -
+						cfe_rd), (void *)&log_buffer[0],
+				       pmc_wr);
+			} else
+				/* Copy everything between cfe_rd and pmc_wr */
+				memcpy((void *)cache_buffer,
+				       (void *)&log_buffer[cfe_rd],
+				       pmc_wr - cfe_rd);
+
+			/* Read is done. Let PMC know how far has been read */
+			log_header->cfe_rd_idx =
+			    (log_header->cfe_rd_idx +
+			     avl_to_process) % log_size;
+
+			/* Process all inside the cache_buffer that has been read */
+			i = 0;
+			while (i < avl_to_process) {
+				format_str = &cache_buffer[i];
+				/* Scan for format count inside the NULL terminated format string */
+				fmt_cnt = 0;
+				while (cache_buffer[i]) {
+					if (cache_buffer[i] == '%')
+						fmt_cnt++;
+					i++;
+				}
+				/* collect the values after the format string, if there is any */
+				i++;
+				if (fmt_cnt == 0)
+					continue;
+				memcpy((void *)value, (void *)&cache_buffer[i],
+				       sizeof(unsigned int) * fmt_cnt);
+				printf(format_str, value[0], value[1], value[2],
+				       value[3], value[4], value[5], value[6],
+				       value[7], value[8], value[9]);
+				/* Look for next format string, inside the cache_buffer */
+				i += fmt_cnt * sizeof(unsigned int);
+			}
+		}
+	}
+#endif /* PMC_SHARED_MEMORY */
+#ifdef PMC_LOG_IN_DTCM
+	pmc_show_boot_log();
+	pmc_show_live_log();
+#endif
+}
+
+static void pmc_boot(void)
+{
+#if !defined (PMC_IMPL_3_X)
+	volatile unsigned int dummy;
+#endif
+	unsigned long physAddrPmc;
+	unsigned int len;
+	const unsigned char *pmccode = NULL;
+	void *pmc_log_start = NULL;
+#ifdef PMC_LOG_IN_DTCM
+	unsigned int i; 
+
+	if (!is_pmcfw_data_loaded()) {
+		/* Copy PMC data into DTCM, needed to boot PMC */
+		/* Copy to correct area */
+		len = sizeof(pmcdata);
+		for (i = 0; i < len; i += 4)
+			PROCMON->dtcm[(i + PMC_DTCM_LOG_SIZE) >> 2] =
+			(pmcdata[i + 3] << 24) | (pmcdata[i + 2] << 16) |
+			(pmcdata[i + 1] << 8) | pmcdata[i];
+	}
+
+	/* set bootlog_len to 0 */
+	* (unsigned short *) CFG_BOOT_PMC_LOG_ADDR = 0;
+	
+	if (getAVSConfig()) {
+		printk
+		    ("%s: nvram opted to disable AVS, PMC firmware code not loaded\n",
+		     __func__);
+		return;
+	}
+#elif defined(CFG_BOOT_PMC3_DATA_ADDR)
+
+	if (!is_pmcfw_data_loaded()) {
+		/* Copy PMC data into DTCM, needed to boot PMC */
+		/* Copy to correct area */
+
+		len = sizeof(pmcdata);
+		memcpy((void *)CFG_BOOT_PMC3_DATA_ADDR, pmcdata, len);
+        if(env_get("print_avs_log"))
+            pmc_log_start = (void *)CFG_BOOT_PMC3_DATA_ADDR;
+    }
+#endif
+
+	// copy image to aligned address in pmc boot area
+	len = sizeof(pmcappdata);
+	pmccode = pmcappdata;
+#ifdef PMC_FW_IN_ITCM
+	physAddrPmc = (unsigned long) PROCMON->itcm;
+#elif defined(CFG_BOOT_PMC3_START_ADDR)
+	physAddrPmc = CFG_BOOT_PMC3_START_ADDR;
+#else
+	physAddrPmc = CFG_BOOT_PMC_ADDR;
+#endif
+
+	if (len > PMC_RESERVED_MEM_SIZE
+#ifdef PMC_FW_IN_ITCM
+		|| len > sizeof(PROCMON->itcm)
+#endif
+		) {
+		printk
+		    ("%s: ** ERROR ** PMC image is too big to fit in memory \n",
+		     __func__);
+		pmc_mode = PMC_MODE_PMB_DIRECT;
+		return;
+	}
+
+	if (!is_pmcfw_code_loaded())
+		memcpy((void *)physAddrPmc, pmccode, len);
+
+#if IS_BCMCHIP(63158)
+	pmc_reset();
+
+	init_pmc_boot_param(physAddrPmc, len, CFG_BOOT_PMC_SIZE);
+	/* Setup PMC log buffer */
+	set_pmc_boot_param(kPMCBootLogBuffer, CFG_BOOT_PMC_LOG_ADDR);
+	set_pmc_boot_param(kPMCBootLogSize, CFG_BOOT_PMC_LOG_SIZE);
+
+	if (getAVSConfig() != 0) {
+		printk("Info: %s PMC opted to disable AVS\n", __func__);
+		set_pmc_boot_param(kPMCBootAVSDisable, 1);
+	}
+#endif
+	/* Boot code and boot params are loaded. Time to flush the content */
+#ifdef __UBOOT__
+	flush_dcache_all();
+	invalidate_icache_all();
+#else
+	_cfe_flushcache(CFE_CACHE_FLUSH_D, 0, 0);
+#endif
+
+#if defined(PMC_IMPL_3_X)
+	printf("Take PMC out of reset\n");
+	// clear/reset fields of PVTMONRO_ACQ_TEMP_WARN_RESET
+	write_bpcm_reg_direct(PMB_ADDR_PVTMON, 0x54 >> 2,
+			      (1 << 30) | (1 << 14));
+#ifdef PMC_LOG_IN_DTCM
+	PMC->ctrl.hostMboxOut = 1; // request sync dtcm log
+#endif
+#ifdef PMC_FW_IN_ITCM
+	PROCMON->maestroReg.coreCtrl.resetVector = 0;
+#else
+	PROCMON->maestroReg.coreCtrl.resetVector = (uint32_t) physAddrPmc;
+#endif
+	PROCMON->maestroReg.coreCtrl.coreEnable = 1;
+#else /* defined(PMC_IMPL_3_X */
+#if IS_BCMCHIP(63158)
+	/* open window for the  PMC to see peripheral address space */
+	PMC->ctrl.addr2WndwMask = ~((1 << 16) - 1);
+	PMC->ctrl.addr2WndwBaseIn = 0x10000000;
+	PMC->ctrl.addr2WndwBaseOut = PERF_PHYS_BASE;
+	dummy = PMC->ctrl.addr2WndwBaseOut;	// dummy, just for sync
+#else
+	PMC->ctrl.addr2WndwMask = 0;
+	PMC->ctrl.addr2WndwBaseIn = 0;
+	PMC->ctrl.addr2WndwBaseOut = 0;
+#endif
+	/* open window for the  PMC to see DDR */
+	PMC->ctrl.addr1WndwMask = ~(PMC_RESERVED_MEM_SIZE - 1);
+	PMC->ctrl.addr1WndwBaseIn = 0x1fc00000;
+	PMC->ctrl.addr1WndwBaseOut = (uint32_t) physAddrPmc;
+
+	dummy = PMC->ctrl.addr1WndwBaseOut;	// dummy, just for sync
+	dummy = dummy;
+
+	printf("Take PMC out of reset\n");
+	PMC->ctrl.softResets = 0x0;
+#endif
+
+	pmc_mode = PMC_MODE_DQM;
+
+	printf("waiting for PMC finish booting\n");
+	WaitPmc(PMC_IN_MAIN_LOOP, pmc_log_start);
+#if defined(PMC_IMPL_3_X)
+	{
+		uint32_t change;
+		uint32_t revision;
+		if (!GetRevision(&change, &revision)) {
+			printf("PMC rev: %d.%d.%d.%d running\n",
+			       (revision >> 28) & 0xf, (revision >> 20) & 0xff,
+			       (revision & 0xfffff), change);
+		}
+#ifdef PMC_LOG_IN_DTCM
+		PMC->ctrl.hostMboxOut = 0; // ignore dtcm log
+#endif
+	}
+#endif
+}
+#endif //defined(PMC_RAM_BOOT)
+
+#if IS_BCMCHIP(4908) && !defined _ATF_
+static void pmc_patch_4908(void)
+{
+	static const
+#include "pmc_patch_4908.h"
+	    // relocate to end of pmc shared memory
+	const unsigned linkaddr = (0xb6004800 - sizeof track_bin) & ~15;
+	TCommand rsp;
+
+	memcpy((void *)&PMC->sharedMem[(linkaddr & 0x7ff) / 4],
+	       track_bin, sizeof track_bin);
+
+	// register command
+	if (SendCommand(cmdRegisterCmdHandler, 0, 0, 0, 96, linkaddr, &rsp)
+	    || rsp.word0.Bits.error)
+		printk("%s:%d %d\n", __func__,
+		       rsp.word0.Bits.cmdID, rsp.word0.Bits.error);
+	else {
+		// check sec_chipvar and send command
+		uint32_t cap = ((uint32_t *) JTAG_OTP_BASE)[12];
+		uint32_t slow, fast;	// margin
+
+		if ((cap & 15) != 0) {
+			slow = 80, fast = 55;
+		} else {
+			slow = 100, fast = 100;
+		}
+
+		if (SendCommand(96, 0, 0, 0, slow, fast, &rsp)
+		    || rsp.word0.Bits.error)
+			printk("%s:%d %d %x %x %x\n", __func__,
+			       rsp.word0.Bits.cmdID, rsp.word0.Bits.error,
+			       rsp.word1.Reg32, rsp.u.cmdResponse.word2,
+			       rsp.u.cmdResponse.word3);
+	}
+}
+#endif
+
+#if IS_BCMCHIP(6846) || IS_BCMCHIP(6856) || IS_BCMCHIP(6858) || IS_BCMCHIP(6878)
+#define SWREG_ADJUSTMENT_SUPPORT
+
+unsigned int swr_read(unsigned int ps, unsigned int reg)
+{
+    unsigned int cmd = SWR_READ_CMD_P | SET_ADDR(ps, reg);
+
+    PROCMON->SSBMaster.control = SWR_EN;
+    PROCMON->SSBMaster.control = cmd;
+    SR_TEST(22);
+    return PROCMON->SSBMaster.rd_data;
+}
+
+static void dump_swregs(void)
+{
+    int i, j;
+    printf("Dump Current setting of SWREGs\n");
+    for (i = SWR_FIRST; i < SWR_LAST; i++)
+        for (j = 0; j < 10; j++) {
+            printf("%s, reg=0x%02x, val=0x%04x\n",
+                   (i ==
+                0 ? "1.0D" : (i ==
+                          1 ? "1.8 " : (i ==
+                                2 ? "1.5 " :
+                                "1.0A"))), j,
+                   swr_read(i, j));
+        }
+}
+#endif
+
+#if IS_BCMCHIP(6856)
+static void pmc_patch_6856(void)
+{
+	// Disable force bit on CLKRST BPCM to allow correct pinmuxing
+	uint32_t target;
+
+	ReadBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+			 CLKRSTBPCMRegOffset(clkrst_control), &target);
+	target &= 0xfffbffff;
+	WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+			  CLKRSTBPCMRegOffset(clkrst_control), target);
+}
+#endif
+
+#if IS_BCMCHIP(6878)
+void swreg_clk_sync(void)
+{
+	uint32_t target;
+	/* Remove the force observe clock to allow of correct pinmuxing of GPIO_7 */
+
+	ReadBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+			 CLKRSTBPCMRegOffset(clkrst_ena_force), &target);
+	target |= 0xfffffffe;
+	WriteBPCMRegister(PMB_ADDR_CHIP_CLKRST,
+			  CLKRSTBPCMRegOffset(clkrst_ena_force), target);
+}
+#endif
+
+int pmc_init(void)
+{
+	int rc = 0;
+
+	pmc_initmode();
+
+#if defined(SWREG_ADJUSTMENT_SUPPORT)
+	dump_swregs();
+#endif
+#if IS_BCMCHIP(6856)
+	pmc_patch_6856();
+#endif
+#if IS_BCMCHIP(6878)
+    swreg_clk_sync();
+#endif
+
+#if defined(PMC_RAM_BOOT)
+	pmc_boot();
+#endif
+
+	printk("%s:PMC using %s mode\n", __func__,
+	       pmc_mode == PMC_MODE_PMB_DIRECT ? "PMB_DIRECT" : "DQM");
+	if (pmc_mode == PMC_MODE_PMB_DIRECT)
+		return 0;
+
+#if IS_BCMCHIP(4908) && !defined _ATF_
+	if (getAVSConfig() == 0) {
+		pmc_patch_4908();
+	} else
+		printk("%s:AVS disabled\n", __func__);
+#endif
+
+	return rc;
+}
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_firmware_47622.h b/arch/arm/mach-bcmbca/pmc/pmc_firmware_47622.h
new file mode 100644
index 0000000000..9cbc7bf792
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_firmware_47622.h
@@ -0,0 +1,1385 @@
+/*
+ * * <:copyright-BRCM:2017:DUAL/GPL:standard
+ * * 
+ * *    Copyright (c) 2017 Broadcom 
+ * *    All Rights Reserved
+ * * 
+ * * This program is free software; you can redistribute it and/or modify
+ * * it under the terms of the GNU General Public License, version 2, as published by
+ * * the Free Software Foundation (the "GPL").
+ * * 
+ * * This program is distributed in the hope that it will be useful,
+ * * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * * GNU General Public License for more details.
+ * * 
+ * * 
+ * * A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+ * * writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * * Boston, MA 02111-1307, USA.
+ * * 
+ * * :>
+ * */
+
+#ifndef PMC_ROMDATA_47622_H
+#define PMC_ROMDATA_47622_H
+#define PMC_VER_IMPL 3
+#define PMC_VER_MAJOR 2
+#define PMC_VER_MINOR 2
+#define PMC_VER_CHANGELIST "$Change: 284027 $"
+const unsigned char pmcappdata[] = {
+  0x01, 0x00, 0x00, 0xbf, 0x03, 0xfe, 0x67, 0xc3, 0xfe, 0x4b, 0xc3, 0xfe,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x08, 0xe6, 0x05,
+  0x00, 0x00, 0x00, 0x8c, 0x52, 0x04, 0x00, 0x66, 0x5a, 0x00, 0x60, 0x09,
+  0x00, 0x00, 0x00, 0x92, 0x55, 0x05, 0x00, 0x00, 0x58, 0x7a, 0x64, 0x4c,
+  0x00, 0x72, 0x05, 0x00, 0x00, 0x00, 0x8e, 0x55, 0x44, 0x00, 0x64, 0x09,
+  0x00, 0x00, 0x44, 0x06, 0x81, 0x86, 0x41, 0x20, 0x39, 0x00, 0x00, 0xf4,
+  0xcf, 0x62, 0x05, 0x00, 0x00, 0x00, 0x8e, 0x55, 0x86, 0x41, 0x20, 0x39,
+  0x00, 0x00, 0xf8, 0xcb, 0x62, 0x48, 0x00, 0x64, 0x05, 0x00, 0x00, 0x84,
+  0x09, 0x7f, 0x07, 0x0c, 0xe6, 0x03, 0x00, 0x80, 0x00, 0x3c, 0x23, 0x0c,
+  0x88, 0x62, 0x38, 0x40, 0x55, 0xba, 0x4f, 0x00, 0x04, 0x00, 0x64, 0x4c,
+  0x04, 0x72, 0xcd, 0xab, 0x89, 0xc8, 0x7b, 0x64, 0x45, 0x23, 0x01, 0xcc,
+  0x59, 0x64, 0x05, 0x00, 0x00, 0x00, 0x8f, 0x64, 0x86, 0x43, 0x20, 0xec,
+  0x83, 0x62, 0xbb, 0x63, 0x00, 0x80, 0x03, 0xe6, 0x04, 0x00, 0x64, 0x4c,
+  0x04, 0x48, 0xc3, 0x07, 0xf6, 0x3b, 0x00, 0xf2, 0x87, 0xc2, 0xfe, 0x46,
+  0x50, 0x07, 0x43, 0x78, 0xfe, 0x87, 0x04, 0xfe, 0x47, 0xc0, 0xf2, 0x44,
+  0x0c, 0x31, 0x10, 0x04, 0xca, 0x08, 0x08, 0xe8, 0x00, 0x3c, 0x23, 0x03,
+  0xc0, 0xf1, 0x02, 0x68, 0x00, 0x03, 0x40, 0xf2, 0x03, 0xc7, 0xf1, 0x02,
+  0xfc, 0x00, 0x73, 0x40, 0xf2, 0x00, 0x3c, 0x23, 0x08, 0x00, 0x74, 0xc4,
+  0x3f, 0x64, 0x50, 0x08, 0x1d, 0x18, 0x00, 0x64, 0x44, 0x37, 0x64, 0x84,
+  0x09, 0x1e, 0x9b, 0x05, 0x00, 0x47, 0x44, 0x00, 0xec, 0xc7, 0x73, 0x84,
+  0x03, 0x64, 0x0b, 0x07, 0xf2, 0x57, 0xc3, 0xfe, 0x9f, 0x11, 0xf2, 0xc7,
+  0x11, 0xf2, 0xef, 0x11, 0xf2, 0x17, 0x12, 0xf2, 0x3f, 0x12, 0xf2, 0x67,
+  0x12, 0xf2, 0xe7, 0x51, 0xf2, 0xff, 0x50, 0xf2, 0x87, 0x13, 0xf2, 0xcf,
+  0x51, 0xf2, 0x44, 0x00, 0x64, 0x73, 0x06, 0xf2, 0x44, 0x00, 0x64, 0xf3,
+  0x06, 0xf2, 0x8d, 0xd6, 0x92, 0x84, 0x28, 0x64, 0xc3, 0x46, 0xf2, 0xa7,
+  0x01, 0xfe, 0x35, 0x0c, 0x00, 0x04, 0xb6, 0x64, 0xb3, 0x06, 0xf2, 0x35,
+  0x0c, 0x00, 0x04, 0x9e, 0x64, 0xbb, 0x06, 0xf2, 0x35, 0x0c, 0x00, 0x84,
+  0x96, 0x64, 0xd3, 0x06, 0xf2, 0x35, 0x0c, 0x00, 0x04, 0xaa, 0x64, 0xc3,
+  0x06, 0xf2, 0x35, 0x0c, 0x00, 0x44, 0x9d, 0x64, 0xdb, 0x06, 0xf2, 0x01,
+  0x0c, 0x00, 0x04, 0xf2, 0x64, 0xcb, 0x06, 0xf2, 0x35, 0x0c, 0x00, 0x44,
+  0x7c, 0x64, 0xe3, 0x06, 0xf2, 0x67, 0xc3, 0xfe, 0xc4, 0xff, 0x64, 0x5b,
+  0x06, 0xf2, 0x67, 0xc3, 0xfe, 0x87, 0xc2, 0xfe, 0x05, 0x00, 0x00, 0x46,
+  0x40, 0x04, 0x43, 0x78, 0xfe, 0x84, 0x00, 0x64, 0x05, 0x10, 0x00, 0x44,
+  0x86, 0x80, 0x01, 0xad, 0xde, 0x44, 0x00, 0x64, 0x4b, 0x04, 0x00, 0x4f,
+  0x08, 0x00, 0x53, 0x0c, 0x00, 0x57, 0x10, 0x00, 0x5b, 0x14, 0x00, 0x5f,
+  0x18, 0x00, 0x63, 0x1c, 0x00, 0x67, 0x20, 0x00, 0x6b, 0x24, 0x00, 0x6f,
+  0x28, 0x00, 0x73, 0x2c, 0x00, 0x77, 0x30, 0x00, 0x7b, 0x34, 0x00, 0x7f,
+  0x38, 0x00, 0x40, 0x60, 0x26, 0x40, 0xe0, 0x26, 0x00, 0x00, 0x23, 0x01,
+  0x0c, 0x00, 0x88, 0x08, 0x64, 0x39, 0x0c, 0x00, 0x04, 0x78, 0x64, 0x1b,
+  0x0b, 0xf2, 0x23, 0x07, 0xf2, 0x08, 0x53, 0x64, 0x05, 0x00, 0x00, 0x04,
+  0x80, 0x64, 0x03, 0x48, 0xf2, 0x0b, 0x44, 0xf2, 0xfd, 0xff, 0xff, 0x08,
+  0xf9, 0x64, 0xfd, 0x1f, 0x00, 0x04, 0xf8, 0x64, 0x13, 0x48, 0xf2, 0x1b,
+  0x44, 0xf2, 0xfd, 0xff, 0xff, 0x08, 0xfb, 0x64, 0x05, 0x00, 0x00, 0x04,
+  0x80, 0x64, 0x23, 0x48, 0xf2, 0x2b, 0x44, 0xf2, 0x08, 0x03, 0x64, 0x04,
+  0x38, 0x64, 0x33, 0x48, 0xf2, 0x3b, 0x44, 0xf2, 0x05, 0x00, 0x00, 0x08,
+  0x8b, 0x64, 0x0d, 0x00, 0x00, 0x04, 0xb8, 0x64, 0x43, 0x48, 0xf2, 0x4b,
+  0x44, 0xf2, 0xfd, 0xff, 0xff, 0x08, 0xfb, 0x64, 0xfd, 0x1f, 0x00, 0x04,
+  0xf8, 0x64, 0x53, 0x48, 0xf2, 0x5b, 0x44, 0xf2, 0x05, 0x10, 0x00, 0x08,
+  0x03, 0x64, 0x05, 0x10, 0x00, 0x04, 0x78, 0x64, 0x63, 0x48, 0xf2, 0x6b,
+  0x44, 0xf2, 0x08, 0x41, 0x64, 0x04, 0x48, 0x64, 0x73, 0x48, 0xf2, 0x7b,
+  0x44, 0xf2, 0xe7, 0x1c, 0xfe, 0x0f, 0x20, 0xe5, 0x00, 0x41, 0x64, 0xd8,
+  0xd7, 0x63, 0x00, 0x00, 0x66, 0x8e, 0x00, 0x60, 0x14, 0x00, 0x64, 0x90,
+  0x14, 0xc8, 0x18, 0x44, 0x64, 0x82, 0x41, 0x20, 0xfc, 0xd3, 0x63, 0x22,
+  0x40, 0x20, 0x83, 0x11, 0x00, 0xf0, 0xd3, 0x63, 0xa3, 0x03, 0x90, 0x83,
+  0x21, 0x00, 0xe4, 0xd3, 0x63, 0x87, 0x23, 0x80, 0x0a, 0x40, 0x20, 0x02,
+  0x42, 0x20, 0xdf, 0x05, 0x00, 0xd8, 0x97, 0x62, 0x6c, 0x9d, 0x3a, 0x9b,
+  0x31, 0x00, 0xc6, 0xff, 0x7f, 0xd4, 0x00, 0x64, 0x70, 0x14, 0xc8, 0x18,
+  0x44, 0x74, 0x82, 0x41, 0x20, 0xf0, 0xcf, 0x63, 0x22, 0x40, 0x20, 0x83,
+  0x11, 0x00, 0xe4, 0xcf, 0x63, 0x0a, 0x40, 0x20, 0x03, 0x02, 0x50, 0xf4,
+  0x93, 0x62, 0xdf, 0x05, 0x00, 0x6c, 0x1d, 0x3a, 0x9b, 0x21, 0x00, 0xd6,
+  0xbf, 0x7f, 0x00, 0x42, 0x64, 0xc0, 0xcf, 0x63, 0x22, 0x40, 0x20, 0x00,
+  0x43, 0x64, 0xf4, 0xcb, 0x63, 0x1e, 0x40, 0x20, 0x01, 0x0c, 0x00, 0xc0,
+  0x32, 0x64, 0x05, 0x00, 0x00, 0x14, 0x88, 0x55, 0x10, 0x00, 0xc8, 0xd0,
+  0xd3, 0x63, 0xd4, 0x87, 0x62, 0x01, 0x0c, 0x00, 0x00, 0x08, 0x64, 0x20,
+  0x00, 0xc8, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0xd0, 0xc3, 0x63, 0x00,
+  0x00, 0x64, 0x18, 0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xcc, 0xbb, 0x62, 0x00,
+  0x00, 0x64, 0x28, 0x00, 0xc8, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0xfd,
+  0xf3, 0xff, 0xc4, 0xb7, 0x62, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0x31,
+  0x00, 0x00, 0xd0, 0x93, 0x63, 0x03, 0x00, 0xe0, 0x00, 0x00, 0x64, 0x18,
+  0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xd8, 0xaf, 0x62, 0x00, 0x00, 0x64, 0x98,
+  0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xe8, 0xab, 0x62, 0x00, 0x00, 0x64, 0x18,
+  0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xf8, 0xa7, 0x62, 0x0f, 0xc2, 0xf1, 0xd2,
+  0x68, 0x00, 0x23, 0x50, 0xf2, 0x00, 0x00, 0x64, 0x10, 0x00, 0xc8, 0xe3,
+  0x02, 0xf2, 0x35, 0x0c, 0x00, 0x00, 0xc2, 0x64, 0x10, 0x00, 0xc8, 0xcb,
+  0x02, 0xf2, 0x67, 0xc3, 0xfe, 0x07, 0x04, 0xe0, 0x40, 0x00, 0x65, 0x5b,
+  0x02, 0xf2, 0x01, 0x00, 0x82, 0x07, 0x00, 0x00, 0x33, 0x06, 0xf2, 0x48,
+  0x00, 0x64, 0xe3, 0x09, 0xf2, 0x67, 0xc3, 0xfe, 0xa3, 0xbf, 0x7f, 0x88,
+  0x08, 0x31, 0x18, 0x08, 0xca, 0x48, 0x10, 0x5a, 0x10, 0x08, 0x7a, 0x00,
+  0x3c, 0x23, 0x0c, 0x00, 0x64, 0x4c, 0xcc, 0x1e, 0x84, 0x08, 0x31, 0x10,
+  0x04, 0xca, 0x10, 0x0c, 0x7a, 0x00, 0x3c, 0x23, 0x05, 0x10, 0x00, 0x18,
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+  0x00, 0x3c, 0x23, 0x0b, 0x08, 0xe6, 0x05, 0x00, 0x00, 0x58, 0x7a, 0x64,
+  0x14, 0x00, 0x72, 0x9b, 0x29, 0x00, 0x04, 0x00, 0x64, 0x28, 0x04, 0xc8,
+  0xa3, 0x03, 0x90, 0xc9, 0xf3, 0xff, 0xc4, 0xbb, 0x63, 0x83, 0x23, 0x80,
+  0x05, 0x00, 0x00, 0x3c, 0x8c, 0x64, 0x88, 0x01, 0xd0, 0xd3, 0x23, 0x80,
+  0x00, 0x09, 0xd8, 0xd3, 0x03, 0x90, 0x40, 0x00, 0x64, 0xc7, 0x03, 0xb0,
+  0x8a, 0x21, 0xc0, 0x23, 0x09, 0xa0, 0x0f, 0x0c, 0xe6, 0x03, 0x10, 0xe6,
+  0x35, 0x0c, 0x00, 0x1b, 0x74, 0x53, 0xdc, 0xfb, 0x63, 0xc2, 0x41, 0x20,
+  0xe8, 0xf3, 0x63, 0x00, 0x00, 0x66, 0xf6, 0xbf, 0x7f, 0x35, 0x0c, 0x00,
+  0xc0, 0x3b, 0x64, 0xd4, 0xf3, 0x63, 0x09, 0x00, 0x00, 0x00, 0x93, 0x52,
+  0x04, 0x80, 0x66, 0x0e, 0x40, 0x60, 0x82, 0x41, 0x20, 0xc8, 0xdb, 0x62,
+  0xd4, 0x87, 0x62, 0x1b, 0x00, 0xe0, 0x0c, 0x00, 0x64, 0x38, 0x0c, 0xc8,
+  0x83, 0x4b, 0x90, 0x88, 0x03, 0xd8, 0xc9, 0xf3, 0xff, 0xc8, 0x9f, 0x63,
+  0x8b, 0x43, 0x80, 0x80, 0x0b, 0xd0, 0x8f, 0xd5, 0x7f, 0xd0, 0xfb, 0x63,
+  0x40, 0x84, 0x62, 0x80, 0x00, 0x64, 0x1b, 0x02, 0xf2, 0x67, 0xc3, 0xfe,
+  0x83, 0xa0, 0xf1, 0x02, 0x48, 0x20, 0x0b, 0x02, 0xf2, 0x67, 0xc3, 0xfe,
+  0x07, 0x00, 0xfe, 0x5c, 0x80, 0x62, 0x43, 0xe0, 0xf1, 0xfd, 0xbf, 0xff,
+  0x00, 0x00, 0x64, 0x07, 0x42, 0xf2, 0x67, 0xc3, 0xfe, 0x8f, 0x1f, 0xfe,
+  0x83, 0xc2, 0xfe, 0x02, 0x78, 0x27, 0x03, 0x78, 0xfe, 0x00, 0x04, 0x23,
+  0x0e, 0x40, 0x20, 0x10, 0x00, 0x64, 0x00, 0x10, 0x1e, 0x03, 0x04, 0x00,
+  0x00, 0x08, 0x1e, 0xc0, 0x04, 0x1e, 0x00, 0x3c, 0x23, 0x57, 0xc3, 0xfe,
+  0x05, 0x10, 0x00, 0x18, 0x28, 0x64, 0xe0, 0x18, 0xc8, 0x83, 0x41, 0x90,
+  0x93, 0x45, 0x90, 0xa3, 0x79, 0x90, 0xb3, 0x7d, 0x90, 0x1f, 0xa5, 0xf1,
+  0xdc, 0xe9, 0xa3, 0x83, 0x1d, 0x90, 0x1f, 0x8f, 0xf1, 0x93, 0x1d, 0x90,
+  0x9f, 0x8f, 0xf1, 0xa3, 0x1d, 0x90, 0x1f, 0xe0, 0xf1, 0xb3, 0x1d, 0x90,
+  0x1f, 0xa5, 0xf1, 0xd0, 0x31, 0x26, 0x2b, 0x00, 0xf3, 0x1f, 0xce, 0xf1,
+  0xa3, 0x1d, 0x90, 0x9f, 0xce, 0xf1, 0xb3, 0x1d, 0x90, 0x1f, 0xa5, 0xf1,
+  0xd4, 0x31, 0x26, 0x2b, 0x00, 0xf3, 0x1f, 0xdd, 0xf1, 0xa3, 0x1d, 0x90,
+  0x9f, 0xdd, 0xf1, 0xb3, 0x1d, 0x90, 0x18, 0x00, 0x64, 0x10, 0x18, 0xc8,
+  0xc0, 0xdb, 0x1f, 0x67, 0x1e, 0xfe, 0x73, 0x87, 0xf1, 0x76, 0x53, 0x20,
+  0x77, 0x30, 0xf2, 0xb3, 0xc2, 0xfe, 0x32, 0x43, 0x04, 0x03, 0x7b, 0xfe,
+  0x30, 0x80, 0x64, 0x6b, 0x32, 0xf2, 0x1f, 0x1e, 0xfe, 0x17, 0x1e, 0xfe,
+  0x2b, 0x28, 0xe0, 0x3f, 0x00, 0xfd, 0x03, 0x40, 0xfd, 0xa3, 0x7f, 0x90,
+  0x93, 0x43, 0x90, 0x67, 0xc3, 0xfe, 0x07, 0xa9, 0xf1, 0xa3, 0x07, 0x90,
+  0xbf, 0xa9, 0xf1, 0xb3, 0x3f, 0x90, 0x03, 0xaa, 0xf1, 0x83, 0x43, 0x90,
+  0x67, 0xc3, 0xfe, 0x19, 0x00, 0x00, 0x80, 0x40, 0x74, 0xdc, 0x8f, 0x62,
+  0x2b, 0x28, 0xe0, 0x3f, 0x00, 0xfd, 0x03, 0x40, 0xfd, 0xa3, 0x7f, 0x90,
+  0x93, 0x43, 0x90, 0x67, 0xc3, 0xfe, 0x07, 0xa9, 0xf1, 0xa3, 0x07, 0x90,
+  0xbf, 0xa9, 0xf1, 0xb3, 0x3f, 0x90, 0x03, 0xaa, 0xf1, 0x83, 0x43, 0x90,
+  0x67, 0xc3, 0xfe, 0x19, 0x00, 0x00, 0xc0, 0x40, 0x74, 0xdc, 0x8b, 0x62,
+  0x2b, 0x28, 0xe0, 0x3f, 0x00, 0xfd, 0x03, 0x40, 0xfd, 0xa3, 0x7f, 0x90,
+  0x93, 0x43, 0x90, 0x67, 0xc3, 0xfe, 0x07, 0xa9, 0xf1, 0xa3, 0x07, 0x90,
+  0xbf, 0xa9, 0xf1, 0xb3, 0x3f, 0x90, 0x03, 0xaa, 0xf1, 0x83, 0x43, 0x90,
+  0x67, 0xc3, 0xfe, 0x19, 0x00, 0x00, 0x40, 0x40, 0x74, 0xdc, 0x87, 0x62,
+  0x09, 0x00, 0x00, 0xc7, 0x50, 0xf9, 0x10, 0x00, 0x64, 0xc9, 0xf3, 0xff,
+  0x7c, 0x53, 0x72, 0x93, 0xc2, 0xfe, 0x12, 0x41, 0x24, 0x03, 0x79, 0xfe,
+  0x53, 0x87, 0xf1, 0x56, 0x41, 0x24, 0x77, 0x10, 0xf2, 0x10, 0x80, 0x64,
+  0x5b, 0x12, 0xf2, 0x6b, 0x12, 0xf2, 0x67, 0xc3, 0xfe, 0x93, 0xc2, 0xfe,
+  0x12, 0x41, 0x04, 0x03, 0x79, 0xfe, 0xff, 0x1b, 0xfe, 0x09, 0x00, 0x00,
+  0x53, 0x4c, 0xf4, 0x33, 0xc3, 0xfe, 0x1b, 0x10, 0xe6, 0x09, 0x00, 0x00,
+  0x44, 0x03, 0x81, 0x7d, 0x00, 0x00, 0x3c, 0x7c, 0xaf, 0x5e, 0x40, 0x20,
+  0x0e, 0x00, 0x60, 0x09, 0x00, 0x00, 0x64, 0x07, 0x81, 0x58, 0x00, 0x64,
+  0xb3, 0x03, 0x90, 0xa3, 0x1b, 0x90, 0x07, 0x00, 0xfd, 0x83, 0x47, 0xb0,
+  0x01, 0x00, 0xf0, 0x48, 0x04, 0x64, 0xc0, 0x00, 0x74, 0xc4, 0x87, 0x62,
+  0x82, 0x83, 0xe0, 0x00, 0xe0, 0x26, 0x1a, 0x40, 0x60, 0x88, 0x1b, 0xd8,
+  0x01, 0x00, 0xf0, 0x48, 0x01, 0x64, 0xc0, 0x00, 0x74, 0xe4, 0x83, 0x62,
+  0x48, 0x00, 0x64, 0xa3, 0x0b, 0x90, 0x00, 0x00, 0x74, 0x01, 0x00, 0xf0,
+  0x48, 0x00, 0x64, 0xcc, 0x83, 0x62, 0x40, 0x00, 0x64, 0xd0, 0xcf, 0x63,
+  0x03, 0x80, 0xe5, 0x20, 0x84, 0x1d, 0x10, 0x7a, 0x31, 0xb3, 0x23, 0x00,
+  0x4c, 0x0a, 0x2b, 0x3c, 0x02, 0xa7, 0x03, 0x33, 0x01, 0xd3, 0x50, 0xfb,
+  0x9b, 0x23, 0x40, 0x06, 0x40, 0x20, 0x22, 0x41, 0x20, 0xd6, 0x43, 0x20,
+  0x84, 0x14, 0x72, 0x87, 0x0d, 0x00, 0x4e, 0x4c, 0x00, 0xd3, 0x20, 0x00,
+  0xbb, 0xd3, 0xf2, 0xcc, 0x01, 0x64, 0xa3, 0x0f, 0xb0, 0x87, 0x23, 0x00,
+  0x47, 0x08, 0x90, 0x8f, 0x37, 0x00, 0x0c, 0x3d, 0x72, 0x03, 0xa3, 0x80,
+  0x8b, 0x4d, 0x00, 0xf8, 0x97, 0x62, 0xfa, 0x41, 0x20, 0x07, 0x84, 0xe5,
+  0x4e, 0x1d, 0x00, 0xcf, 0x44, 0x00, 0xcc, 0x00, 0xb6, 0x3a, 0x00, 0x60,
+  0x64, 0x00, 0x64, 0x4c, 0x8e, 0x40, 0xd0, 0x80, 0xba, 0x60, 0x40, 0x70,
+  0x0a, 0x40, 0x60, 0x47, 0x10, 0x00, 0x9b, 0x8d, 0xf2, 0x4c, 0x0d, 0x31,
+  0x18, 0x0c, 0xc8, 0xd0, 0x90, 0x1d, 0x4e, 0x41, 0x20, 0xd0, 0x90, 0x1d,
+  0x83, 0xbf, 0x7f, 0xd0, 0x80, 0x92, 0xe6, 0xff, 0x7f, 0x67, 0x00, 0x80,
+  0x9b, 0x05, 0x00, 0x47, 0x10, 0x00, 0x4c, 0x06, 0x5e, 0x9b, 0x05, 0x00,
+  0xc4, 0x00, 0x66, 0xf6, 0xbf, 0x7f, 0xc7, 0xbf, 0x7f, 0xca, 0x1f, 0x00,
+  0x8b, 0x44, 0x00, 0x8c, 0x00, 0xb6, 0x4e, 0x00, 0x60, 0x50, 0x00, 0x64,
+  0x08, 0x89, 0x40, 0x90, 0x80, 0xba, 0x32, 0x40, 0x60, 0x10, 0x10, 0x5a,
+  0xc3, 0x10, 0x90, 0xcf, 0x88, 0xf2, 0xc8, 0x0f, 0x31, 0x20, 0x08, 0xc8,
+  0x3e, 0x42, 0x20, 0xa2, 0x40, 0x20, 0xca, 0x43, 0x20, 0x3e, 0x42, 0x20,
+  0xa2, 0x40, 0x20, 0x37, 0xbf, 0x7f, 0x10, 0x08, 0xf0, 0xc0, 0x10, 0xd8,
+  0xd7, 0xbf, 0x7f, 0x90, 0x80, 0x92, 0xd2, 0xff, 0x7f, 0xc0, 0x00, 0xe4,
+  0x03, 0x10, 0x00, 0xcf, 0x04, 0x00, 0x13, 0xf0, 0x8f, 0x08, 0x05, 0x5e,
+  0xc4, 0x08, 0x78, 0x84, 0x00, 0x66, 0xf6, 0xbf, 0x7f, 0xaf, 0xbf, 0x7f,
+  0x00, 0x7c, 0x31, 0x00, 0xfc, 0xa1, 0x00, 0x3c, 0x23, 0x03, 0x18, 0xe5,
+  0x18, 0x84, 0x1d, 0x09, 0x00, 0x00, 0x00, 0x9c, 0x52, 0x96, 0x40, 0x20,
+  0x00, 0x00, 0x66, 0x16, 0x00, 0x60, 0x4a, 0x41, 0x20, 0x80, 0x9d, 0x1d,
+  0xd0, 0x93, 0x62, 0x07, 0x1c, 0xe5, 0x08, 0x00, 0x64, 0x00, 0x00, 0x74,
+  0xc0, 0x93, 0x62, 0xfd, 0xff, 0xff, 0x3c, 0xfc, 0x87, 0x12, 0x40, 0x60,
+  0x44, 0x00, 0x64, 0x09, 0x00, 0x00, 0x84, 0x07, 0x7f, 0x09, 0x00, 0x00,
+  0x08, 0x9c, 0x52, 0x84, 0x00, 0x66, 0xc2, 0xbf, 0x7f, 0x4a, 0x41, 0x20,
+  0x80, 0x9d, 0x1d, 0xcc, 0xfb, 0x63, 0xbf, 0xbf, 0x7f, 0x03, 0x00, 0xe0,
+  0xcc, 0xfb, 0x63, 0x03, 0x60, 0x20, 0x07, 0x04, 0xe0, 0x37, 0x00, 0xfe,
+  0x9f, 0x00, 0xfe, 0x03, 0x00, 0xe0, 0xc4, 0x87, 0x62, 0x40, 0x80, 0x1d,
+  0x07, 0x04, 0xe0, 0x03, 0x10, 0xe5, 0x14, 0x7c, 0x27, 0x58, 0x7c, 0x27,
+  0x03, 0xd4, 0xfa, 0x47, 0xd8, 0xfa, 0x03, 0xd4, 0xf2, 0x47, 0xd8, 0xf2,
+  0xdc, 0x83, 0x62, 0x47, 0xd4, 0xfa, 0x47, 0xd4, 0xf2, 0x57, 0xd9, 0xfa,
+  0x03, 0xd4, 0xfa, 0x03, 0xd4, 0xf2, 0x07, 0x14, 0xe5, 0x4b, 0x24, 0xfe,
+  0x50, 0x04, 0xc8, 0x8a, 0x4c, 0x20, 0x8b, 0x04, 0x00, 0x52, 0x40, 0x20,
+  0x04, 0x88, 0x3e, 0x8c, 0x80, 0x25, 0x00, 0x8c, 0x40, 0x10, 0x08, 0xca,
+  0x00, 0x50, 0x1e, 0x00, 0x3c, 0x23, 0x04, 0x00, 0x64, 0xb0, 0xc7, 0xc9,
+  0x47, 0x00, 0x80, 0xa0, 0xc7, 0xc9, 0x07, 0x00, 0xfe, 0x0e, 0x40, 0x20,
+  0x48, 0x04, 0x5e, 0xc4, 0x08, 0x78, 0x84, 0x00, 0x66, 0xf6, 0xbf, 0x7f,
+  0x00, 0x3c, 0x23, 0x8c, 0x00, 0x64, 0x01, 0x00, 0x00, 0xcf, 0x01, 0xfe,
+  0x01, 0x04, 0x00, 0x8c, 0x05, 0x64, 0x01, 0x00, 0x00, 0x6f, 0x01, 0xfe,
+  0x4b, 0xc3, 0xfe, 0x63, 0xc3, 0xfe, 0x67, 0xc3, 0xfe, 0x8f, 0x03, 0x80,
+  0x83, 0x13, 0x80, 0xbb, 0x23, 0x00, 0xc0, 0x00, 0x86, 0x02, 0xbc, 0x9f,
+  0x00, 0x3c, 0x23, 0xa0, 0xcf, 0x7b, 0x67, 0xc3, 0xfe, 0x63, 0xc3, 0xfe,
+  0xa7, 0x1f, 0xfe, 0x10, 0x00, 0x64, 0xc5, 0xf3, 0xff, 0x14, 0x11, 0x73,
+  0xcf, 0x1f, 0xfe
+};
+
+#define PMC_DTCM_LOG_SIZE 256
+
+const unsigned char pmcdata[] = {
+  0x3c, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x40, 0x01, 0x00, 0x00, 0x40, 0x0a, 0x00, 0x00, 0xb8, 0x04, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x44, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42,
+  0x43, 0x44, 0x45, 0x46, 0x00, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
+  0x37, 0x38, 0x39, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x00, 0x28, 0x6e,
+  0x75, 0x6c, 0x6c, 0x29, 0x00, 0x25, 0x30, 0x34, 0x75, 0x3a, 0x20, 0x00,
+  0x73, 0x63, 0x72, 0x61, 0x74, 0x63, 0x68, 0x3a, 0x20, 0x30, 0x78, 0x25,
+  0x30, 0x38, 0x78, 0x0a, 0x00, 0x50, 0x4d, 0x43, 0x5f, 0x56, 0x45, 0x52,
+  0x3a, 0x25, 0x64, 0x2e, 0x25, 0x64, 0x2e, 0x25, 0x64, 0x0a, 0x00, 0x24,
+  0x43, 0x68, 0x61, 0x6e, 0x67, 0x65, 0x3a, 0x20, 0x32, 0x38, 0x34, 0x30,
+  0x32, 0x37, 0x20, 0x24, 0x00, 0x32, 0x30, 0x30, 0x36, 0x32, 0x32, 0x5f,
+  0x31, 0x31, 0x33, 0x30, 0x00, 0x54, 0x53, 0x3a, 0x25, 0x73, 0x0a, 0x00,
+  0x43, 0x48, 0x49, 0x44, 0x3a, 0x25, 0x78, 0x0a, 0x00, 0x43, 0x52, 0x45,
+  0x56, 0x3a, 0x25, 0x78, 0x0a, 0x00, 0x50, 0x41, 0x52, 0x54, 0x49, 0x44,
+  0x3a, 0x25, 0x78, 0x20, 0x43, 0x46, 0x41, 0x4d, 0x3a, 0x25, 0x78, 0x20,
+  0x73, 0x6b, 0x69, 0x70, 0x70, 0x65, 0x64, 0x20, 0x63, 0x68, 0x69, 0x70,
+  0x20, 0x69, 0x64, 0x20, 0x76, 0x61, 0x6c, 0x69, 0x64, 0x61, 0x74, 0x69,
+  0x6f, 0x6e, 0x0a, 0x00, 0x52, 0x4f, 0x20, 0x53, 0x56, 0x54, 0x20, 0x25,
+  0x64, 0x20, 0x48, 0x56, 0x54, 0x20, 0x25, 0x64, 0x20, 0x4c, 0x56, 0x54,
+  0x20, 0x25, 0x64, 0x0a, 0x00, 0x48, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x43,
+  0x6c, 0x6f, 0x73, 0x65, 0x41, 0x56, 0x53, 0x3a, 0x20, 0x6f, 0x76, 0x65,
+  0x72, 0x77, 0x72, 0x69, 0x74, 0x69, 0x6e, 0x67, 0x20, 0x70, 0x72, 0x65,
+  0x76, 0x69, 0x6f, 0x75, 0x73, 0x20, 0x43, 0x6c, 0x6f, 0x73, 0x65, 0x41,
+  0x56, 0x53, 0x20, 0x6c, 0x6f, 0x67, 0x0a, 0x00, 0x48, 0x61, 0x6e, 0x64,
+  0x6c, 0x65, 0x43, 0x6c, 0x6f, 0x73, 0x65, 0x41, 0x56, 0x53, 0x3a, 0x20,
+  0x69, 0x73, 0x6c, 0x61, 0x6e, 0x64, 0x20, 0x25, 0x64, 0x20, 0x73, 0x6c,
+  0x6f, 0x77, 0x20, 0x25, 0x64, 0x20, 0x66, 0x61, 0x73, 0x74, 0x20, 0x25,
+  0x64, 0x20, 0x6d, 0x61, 0x78, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x69, 0x6e,
+  0x20, 0x25, 0x64, 0x0a, 0x00, 0x48, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x43,
+  0x6c, 0x6f, 0x73, 0x65, 0x41, 0x56, 0x53, 0x3a, 0x20, 0x66, 0x69, 0x6e,
+  0x69, 0x73, 0x68, 0x65, 0x64, 0x20, 0x77, 0x69, 0x74, 0x68, 0x20, 0x65,
+  0x72, 0x72, 0x6f, 0x72, 0x43, 0x6f, 0x64, 0x65, 0x20, 0x25, 0x75, 0x0a,
+  0x00, 0x41, 0x56, 0x53, 0x20, 0x44, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65,
+  0x64, 0x0a, 0x00, 0x44, 0x41, 0x43, 0x3a, 0x20, 0x25, 0x64, 0x0a, 0x00,
+  0x4c, 0x56, 0x54, 0x00, 0x48, 0x56, 0x54, 0x00, 0x64, 0x65, 0x76, 0x20,
+  0x61, 0x64, 0x64, 0x72, 0x20, 0x30, 0x78, 0x25, 0x78, 0x20, 0x52, 0x4f,
+  0x20, 0x74, 0x79, 0x70, 0x65, 0x20, 0x53, 0x56, 0x54, 0x20, 0x76, 0x61,
+  0x6c, 0x75, 0x65, 0x20, 0x25, 0x75, 0x20, 0x52, 0x4f, 0x20, 0x74, 0x79,
+  0x70, 0x65, 0x20, 0x25, 0x73, 0x20, 0x76, 0x61, 0x6c, 0x75, 0x65, 0x20,
+  0x25, 0x75, 0x0a, 0x00, 0x63, 0x75, 0x72, 0x5f, 0x64, 0x61, 0x63, 0x20,
+  0x25, 0x75, 0x20, 0x63, 0x75, 0x72, 0x56, 0x20, 0x25, 0x75, 0x20, 0x63,
+  0x75, 0x72, 0x54, 0x65, 0x6d, 0x70, 0x20, 0x25, 0x75, 0x20, 0x64, 0x65,
+  0x6c, 0x74, 0x61, 0x20, 0x25, 0x64, 0x20, 0x6e, 0x65, 0x77, 0x5f, 0x64,
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+  0x67, 0x69, 0x6e, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x63, 0x61,
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+  0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x6c, 0x6f, 0x77, 0x20, 0x25,
+  0x64, 0x0a, 0x00, 0x41, 0x56, 0x53, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65,
+  0x64, 0x20, 0x6f, 0x6e, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x63, 0x6f, 0x64,
+  0x65, 0x20, 0x25, 0x64, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x5f, 0x73, 0x77,
+  0x72, 0x65, 0x67, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x74, 0x61,
+  0x72, 0x67, 0x65, 0x74, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x63,
+  0x61, 0x6c, 0x63, 0x5f, 0x73, 0x77, 0x72, 0x65, 0x67, 0x5f, 0x64, 0x61,
+  0x63, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x41, 0x56, 0x53, 0x20, 0x69, 0x73,
+  0x6c, 0x61, 0x6e, 0x64, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x61, 0x72, 0x67,
+  0x69, 0x6e, 0x5f, 0x6d, 0x76, 0x5f, 0x73, 0x6c, 0x6f, 0x77, 0x20, 0x25,
+  0x64, 0x20, 0x6d, 0x61, 0x72, 0x67, 0x69, 0x6e, 0x5f, 0x6d, 0x76, 0x5f,
+  0x66, 0x61, 0x73, 0x74, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x61, 0x78, 0x69,
+  0x6d, 0x75, 0x6d, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x69,
+  0x6e, 0x69, 0x6d, 0x75, 0x6d, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x0a,
+  0x00, 0x53, 0x65, 0x74, 0x74, 0x69, 0x6e, 0x67, 0x20, 0x54, 0x68, 0x72,
+  0x65, 0x73, 0x68, 0x6f, 0x6c, 0x64, 0x73, 0x20, 0x66, 0x6f, 0x72, 0x20,
+  0x25, 0x64, 0x20, 0x68, 0x69, 0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f, 0x20,
+  0x25, 0x64, 0x0a, 0x00, 0x53, 0x65, 0x74, 0x74, 0x69, 0x6e, 0x67, 0x20,
+  0x52, 0x34, 0x38, 0x5f, 0x25, 0x64, 0x20, 0x54, 0x68, 0x72, 0x65, 0x73,
+  0x68, 0x6f, 0x6c, 0x64, 0x73, 0x20, 0x68, 0x69, 0x20, 0x25, 0x64, 0x20,
+  0x6c, 0x6f, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x44, 0x75, 0x6d, 0x70, 0x20,
+  0x61, 0x6c, 0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73, 0x20, 0x6f, 0x6e, 0x20,
+  0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x0a, 0x00, 0x40, 0x40, 0x40,
+  0x46, 0x41, 0x49, 0x4c, 0x45, 0x44, 0x00, 0x40, 0x40, 0x40, 0x50, 0x41,
+  0x53, 0x53, 0x45, 0x44, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x74, 0xc4, 0xec,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0xff, 0x00, 0x00, 0x00, 0x50, 0x0a, 0x00, 0x00
+};
+#endif //PMC_ROMDATA_47622_H
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_firmware_4912.h b/arch/arm/mach-bcmbca/pmc/pmc_firmware_4912.h
new file mode 100644
index 0000000000..b0ae13b42f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_firmware_4912.h
@@ -0,0 +1,1430 @@
+/*
+ * * <:copyright-BRCM:2017:DUAL/GPL:standard
+ * * 
+ * *    Copyright (c) 2017 Broadcom 
+ * *    All Rights Reserved
+ * * 
+ * * This program is free software; you can redistribute it and/or modify
+ * * it under the terms of the GNU General Public License, version 2, as published by
+ * * the Free Software Foundation (the "GPL").
+ * * 
+ * * This program is distributed in the hope that it will be useful,
+ * * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * * GNU General Public License for more details.
+ * * 
+ * * 
+ * * A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+ * * writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * * Boston, MA 02111-1307, USA.
+ * * 
+ * * :>
+ * */
+
+#ifndef PMC_ROMDATA_4912_H
+#define PMC_ROMDATA_4912_H
+#define PMC_VER_IMPL 3
+#define PMC_VER_MAJOR 3
+#define PMC_VER_MINOR 4
+#define PMC_VER_CHANGELIST "$Change: 300027 $"
+#ifndef DEVICE_TREE
+const unsigned char pmcappdata[] = {
+  0xeb, 0x42, 0xf2, 0x35, 0x00, 0x00, 0x87, 0x1a, 0xfe, 0x00, 0x00, 0x00,
+  0x11, 0x10, 0x00, 0x04, 0x0b, 0x4e, 0x40, 0x00, 0x84, 0x07, 0xbc, 0xfd,
+  0x11, 0x10, 0x00, 0x08, 0x0b, 0x64, 0x8e, 0x08, 0xc0, 0xc0, 0x80, 0x90,
+  0xfa, 0xff, 0x7f, 0x04, 0x00, 0x64, 0x10, 0x04, 0x5e, 0x00, 0x01, 0x66,
+  0x0e, 0x00, 0x60, 0x40, 0xc0, 0x92, 0x12, 0x40, 0x60, 0x11, 0x10, 0x00,
+  0x74, 0x05, 0x82, 0x00, 0x3c, 0x23, 0x44, 0x10, 0x78, 0xdf, 0xbf, 0x7f,
+  0x00, 0x80, 0xa2, 0x11, 0x10, 0x00, 0x04, 0x01, 0x80, 0x11, 0x10, 0x00,
+  0x04, 0x06, 0x64, 0x4b, 0x20, 0x80, 0xbc, 0x7c, 0xb3, 0xfa, 0xbf, 0x7f,
+  0x00, 0x3c, 0x23, 0x04, 0xfa, 0x64, 0x00, 0x44, 0x24, 0xaf, 0x1f, 0xfe,
+  0x47, 0x44, 0x00, 0xfd, 0xff, 0xff, 0x7c, 0x7c, 0x93, 0x03, 0xbc, 0xfd,
+  0x03, 0x04, 0x00, 0x3c, 0xfc, 0xe4, 0xeb, 0xbf, 0x7f, 0x0d, 0x00, 0x00,
+  0x08, 0x60, 0x55, 0x0d, 0x00, 0x00, 0x12, 0xbc, 0x1f, 0x03, 0x0c, 0x36,
+  0x87, 0x00, 0x80, 0x3d, 0x00, 0x00, 0x4e, 0x00, 0x00, 0x3d, 0x00, 0x00,
+  0xc0, 0x00, 0x92, 0x12, 0x00, 0x60, 0x08, 0x00, 0x64, 0x82, 0x40, 0x20,
+  0x00, 0x3c, 0x23, 0x4f, 0x24, 0x37, 0xec, 0x90, 0x48, 0x12, 0x40, 0x60,
+  0x47, 0x10, 0x35, 0x7c, 0x00, 0x48, 0xe6, 0xbf, 0x7f, 0x8b, 0x10, 0x00,
+  0xc3, 0xbf, 0x7f, 0x28, 0x00, 0x72, 0x00, 0x08, 0x2b, 0x0d, 0x00, 0x00,
+  0x03, 0xf0, 0x82, 0x24, 0x00, 0x72, 0x40, 0x00, 0x75, 0x0d, 0x00, 0x00,
+  0x34, 0x87, 0x82, 0x00, 0x3c, 0x23, 0x1b, 0x08, 0xe6, 0xfd, 0xff, 0xff,
+  0x7c, 0x7c, 0x93, 0x1a, 0x40, 0x20, 0x1a, 0x00, 0x60, 0x03, 0x10, 0x80,
+  0x01, 0x00, 0x3c, 0x00, 0x80, 0x8e, 0x40, 0x00, 0x64, 0x7e, 0x40, 0x60,
+  0xfd, 0xff, 0xff, 0xb8, 0x7c, 0x87, 0x2e, 0x00, 0x60, 0x82, 0x11, 0xc0,
+  0xfd, 0xff, 0xff, 0x3c, 0xfc, 0x85, 0x1e, 0x40, 0x60, 0xa3, 0x0f, 0x90,
+  0xfc, 0xf3, 0x63, 0x8f, 0x23, 0x80, 0x24, 0x00, 0x72, 0x80, 0x00, 0x64,
+  0x4b, 0x00, 0x60, 0x00, 0x00, 0x64, 0x88, 0x00, 0xc8, 0xfd, 0xff, 0xff,
+  0xf8, 0x7c, 0x87, 0x3a, 0x00, 0x60, 0x87, 0x11, 0x80, 0x01, 0xff, 0x03,
+  0x4a, 0x00, 0x00, 0x01, 0xff, 0x03, 0x80, 0x80, 0x86, 0x22, 0x40, 0x60,
+  0x13, 0x00, 0x80, 0x4f, 0x28, 0x38, 0x00, 0x00, 0x64, 0x3f, 0xa1, 0x3b,
+  0xc4, 0x3c, 0x3a, 0x02, 0x0c, 0x80, 0x1f, 0x0c, 0xe6, 0x00, 0x00, 0x64,
+  0xfb, 0xbf, 0x7f, 0x00, 0x04, 0x92, 0x1e, 0x00, 0x60, 0x11, 0x10, 0x00,
+  0x0c, 0x0a, 0x52, 0xcf, 0x04, 0xd0, 0x11, 0x10, 0x00, 0x44, 0x0d, 0x7e,
+  0x00, 0x3c, 0x23, 0x0d, 0x00, 0x00, 0x03, 0x10, 0x0b, 0x0a, 0x30, 0xe3,
+  0x93, 0x04, 0xd0, 0x33, 0x88, 0xb1, 0x00, 0x3c, 0x23, 0x00, 0x04, 0x92,
+  0x46, 0x0c, 0x00, 0x26, 0x00, 0x60, 0x11, 0x10, 0x00, 0x00, 0x0a, 0x52,
+  0x4c, 0x0c, 0x2b, 0x0a, 0xe0, 0x00, 0x93, 0x4c, 0xfb, 0x11, 0x10, 0x00,
+  0x44, 0x11, 0x7e, 0x00, 0x3c, 0x23, 0x0d, 0x00, 0x00, 0x03, 0x10, 0x0b,
+  0x0a, 0x30, 0xe3, 0x4c, 0x10, 0x2b, 0x92, 0xc0, 0x01, 0x07, 0x4d, 0xfb,
+  0x33, 0x84, 0xb1, 0x00, 0x3c, 0x23, 0x13, 0x00, 0xe0, 0x01, 0x12, 0x00,
+  0x10, 0x00, 0x64, 0x0f, 0x01, 0x84, 0xa0, 0x03, 0xe7, 0xbc, 0x7c, 0xb3,
+  0x0d, 0x00, 0x00, 0x37, 0xab, 0xf8, 0xff, 0x28, 0x3a, 0x8f, 0x0c, 0x00,
+  0xcb, 0x88, 0xf9, 0x8f, 0x23, 0x80, 0xc0, 0x43, 0x24, 0xbc, 0x08, 0x27,
+  0x03, 0xbc, 0xf2, 0xd3, 0x40, 0xd0, 0xa3, 0x0f, 0x90, 0xbf, 0x23, 0x80,
+  0xc0, 0x3f, 0xa4, 0xa3, 0x03, 0x90, 0x8f, 0x23, 0x80, 0xcf, 0x04, 0xda,
+  0xa3, 0x0f, 0x90, 0x87, 0x23, 0x80, 0x48, 0x00, 0xa2, 0xa3, 0x0b, 0x90,
+  0xbf, 0x23, 0x80, 0x03, 0xbd, 0x94, 0xa0, 0x03, 0xe7, 0x03, 0x81, 0x84,
+  0xa3, 0x03, 0x90, 0x8f, 0x23, 0x80, 0xf0, 0xb4, 0x26, 0xf2, 0xff, 0x7f,
+  0x93, 0x23, 0x80, 0xc8, 0x04, 0x64, 0x34, 0x15, 0x26, 0x16, 0x00, 0x40,
+  0x87, 0x23, 0x80, 0x78, 0x94, 0x26, 0x1a, 0x40, 0x60, 0x08, 0x02, 0x64,
+  0x0d, 0x00, 0x00, 0x34, 0x8b, 0x82, 0x00, 0x00, 0x64, 0x17, 0x04, 0xe0,
+  0x01, 0x12, 0x00, 0x00, 0x4b, 0x55, 0xf7, 0xbf, 0x7f, 0x0b, 0x08, 0xe6,
+  0x01, 0x12, 0x00, 0x18, 0x00, 0x64, 0x93, 0x01, 0x84, 0xbf, 0x0c, 0x00,
+  0x0d, 0x00, 0x00, 0x37, 0xab, 0xf8, 0xbc, 0x7c, 0xb3, 0x93, 0x8d, 0x94,
+  0xcb, 0x8b, 0xf9, 0x0f, 0x29, 0x3a, 0xc0, 0x40, 0x24, 0x90, 0x08, 0x27,
+  0x0f, 0x90, 0xf2, 0xfd, 0x0f, 0x00, 0xc2, 0xbc, 0x1f, 0x0f, 0x04, 0xda,
+  0x04, 0x04, 0xa2, 0x83, 0x85, 0x94, 0xbf, 0x81, 0x84, 0xf0, 0xb7, 0x26,
+  0xfa, 0xff, 0x7f, 0xf4, 0x17, 0x26, 0xc8, 0x04, 0x64, 0x12, 0x00, 0x40,
+  0xf8, 0x97, 0x26, 0x12, 0x40, 0x60, 0x08, 0x02, 0x64, 0x0d, 0x00, 0x00,
+  0x34, 0x8b, 0x82, 0x0f, 0x0c, 0xe6, 0x03, 0x00, 0x80, 0x4b, 0x00, 0x50,
+  0x07, 0x10, 0x35, 0x03, 0x24, 0x37, 0x67, 0x1d, 0xfe, 0x13, 0x00, 0xe0,
+  0x03, 0x00, 0x80, 0xa0, 0x03, 0xe7, 0x48, 0x88, 0x1d, 0x07, 0x10, 0x35,
+  0x03, 0x24, 0x37, 0xd8, 0xf7, 0x63, 0x17, 0x04, 0xe0, 0x13, 0x10, 0xe6,
+  0x47, 0x10, 0x00, 0x58, 0x14, 0x2b, 0x86, 0x41, 0x20, 0x1e, 0x40, 0x20,
+  0xa3, 0x0b, 0x90, 0xf4, 0xfb, 0x63, 0x8b, 0x23, 0x80, 0x00, 0x18, 0x94,
+  0x80, 0x00, 0x92, 0x13, 0x00, 0xfd, 0x80, 0x80, 0x86, 0x04, 0x29, 0x2b,
+  0x0f, 0x40, 0xfd, 0xd0, 0x24, 0x2b, 0x0b, 0x44, 0xfb, 0x8b, 0x50, 0xfb,
+  0xc0, 0x99, 0x1d, 0x13, 0x14, 0xe6, 0x2f, 0x1f, 0xfe, 0x0f, 0x28, 0xe5,
+  0x1a, 0x40, 0x20, 0x20, 0x00, 0xc8, 0x03, 0x00, 0x80, 0x00, 0x30, 0x26,
+  0x16, 0x00, 0x60, 0x88, 0x00, 0x64, 0x0d, 0x00, 0x00, 0x34, 0x8b, 0x82,
+  0x0f, 0x2c, 0xe5, 0x01, 0x12, 0x00, 0x04, 0x40, 0x55, 0x0f, 0x10, 0x35,
+  0x4b, 0x0c, 0x32, 0xc0, 0x88, 0x3a, 0x66, 0x40, 0x60, 0x48, 0x02, 0x64,
+  0xdb, 0xbf, 0x7f, 0x80, 0x9d, 0x1d, 0x08, 0x02, 0xe5, 0xec, 0xf3, 0x63,
+  0x06, 0x0a, 0xc0, 0x40, 0x80, 0x90, 0x22, 0x40, 0x60, 0x01, 0x00, 0x04,
+  0x00, 0x20, 0x8e, 0x16, 0x00, 0x60, 0x00, 0x74, 0x98, 0x08, 0x08, 0x94,
+  0x80, 0x9d, 0x1d, 0xd8, 0xf3, 0x63, 0x57, 0x05, 0x00, 0xdf, 0x01, 0x01,
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+  0x40, 0x40, 0x74, 0xd8, 0x87, 0x62, 0x09, 0x00, 0x00, 0x37, 0x53, 0xf9,
+  0x10, 0x00, 0x64, 0xc9, 0xff, 0xff, 0xec, 0x93, 0x73, 0x93, 0xc2, 0xfe,
+  0x12, 0x41, 0x24, 0x03, 0x79, 0xfe, 0x53, 0x87, 0xf1, 0x56, 0x41, 0x24,
+  0x77, 0x10, 0xf2, 0x10, 0x80, 0x64, 0x5b, 0x12, 0xf2, 0x6b, 0x12, 0xf2,
+  0x93, 0x8c, 0xf1, 0x12, 0x41, 0x04, 0xcb, 0x10, 0xf2, 0x67, 0xc3, 0xfe,
+  0x09, 0x00, 0x00, 0x53, 0x73, 0xf4, 0x33, 0xc3, 0xfe, 0x1b, 0x10, 0xe6,
+  0x09, 0x00, 0x00, 0x04, 0xc1, 0x81, 0x7d, 0x00, 0x00, 0x3c, 0x7c, 0xaf,
+  0x5e, 0x40, 0x20, 0x0e, 0x00, 0x60, 0x09, 0x00, 0x00, 0x24, 0xc5, 0x81,
+  0x58, 0x00, 0x64, 0xb3, 0x03, 0x90, 0xa3, 0x1b, 0x90, 0x07, 0x00, 0xfd,
+  0x83, 0x47, 0xb0, 0x01, 0x00, 0xf0, 0x48, 0x04, 0x64, 0xc0, 0x00, 0x74,
+  0xc4, 0x87, 0x62, 0x82, 0x83, 0xe0, 0x00, 0xe0, 0x26, 0x1a, 0x40, 0x60,
+  0x88, 0x1b, 0xd8, 0x01, 0x00, 0xf0, 0x48, 0x01, 0x64, 0xc0, 0x00, 0x74,
+  0xe4, 0x83, 0x62, 0x48, 0x00, 0x64, 0xa3, 0x0b, 0x90, 0x00, 0x00, 0x74,
+  0x01, 0x00, 0xf0, 0x48, 0x00, 0x64, 0xcc, 0x83, 0x62, 0x40, 0x00, 0x64,
+  0xf8, 0xc7, 0x63, 0x03, 0x80, 0xe5, 0x20, 0x84, 0x1d, 0x10, 0x7a, 0x31,
+  0xb3, 0x23, 0x00, 0x4c, 0x0a, 0x2b, 0x3c, 0x02, 0xa7, 0x03, 0x33, 0x01,
+  0xd3, 0x50, 0xfb, 0x9b, 0x23, 0x40, 0x06, 0x40, 0x20, 0x22, 0x41, 0x20,
+  0xd6, 0x43, 0x20, 0x84, 0x14, 0x72, 0x87, 0x0d, 0x00, 0x4e, 0x4c, 0x00,
+  0xd3, 0x20, 0x00, 0xbb, 0xd3, 0xf2, 0xcc, 0x01, 0x64, 0xa3, 0x0f, 0xb0,
+  0x87, 0x23, 0x00, 0x47, 0x08, 0x90, 0x8f, 0x37, 0x00, 0x0c, 0x3d, 0x72,
+  0x03, 0xa3, 0x80, 0x8b, 0x4d, 0x00, 0xc8, 0x9b, 0x62, 0xfa, 0x41, 0x20,
+  0x07, 0x84, 0xe5, 0x4e, 0x1d, 0x00, 0xcf, 0x44, 0x00, 0xcc, 0x00, 0xb6,
+  0x3a, 0x00, 0x60, 0x64, 0x00, 0x64, 0x4c, 0x8e, 0x40, 0xd0, 0x80, 0xba,
+  0x60, 0x40, 0x70, 0x0a, 0x40, 0x60, 0x47, 0x10, 0x00, 0x9b, 0x8d, 0xf2,
+  0x4c, 0x0d, 0x31, 0x18, 0x0c, 0xc8, 0xd0, 0x90, 0x1d, 0x4e, 0x41, 0x20,
+  0xd0, 0x90, 0x1d, 0x83, 0xbf, 0x7f, 0xd0, 0x80, 0x92, 0xe6, 0xff, 0x7f,
+  0x67, 0x00, 0x80, 0x9b, 0x05, 0x00, 0x47, 0x10, 0x00, 0x4c, 0x06, 0x5e,
+  0x9b, 0x05, 0x00, 0xc4, 0x00, 0x66, 0xf6, 0xbf, 0x7f, 0xc7, 0xbf, 0x7f,
+  0xca, 0x1f, 0x00, 0x8b, 0x44, 0x00, 0x8c, 0x00, 0xb6, 0x4e, 0x00, 0x60,
+  0x50, 0x00, 0x64, 0x08, 0x89, 0x40, 0x90, 0x80, 0xba, 0x32, 0x40, 0x60,
+  0x10, 0x10, 0x5a, 0xc3, 0x10, 0x90, 0xcf, 0x88, 0xf2, 0xc8, 0x0f, 0x31,
+  0x20, 0x08, 0xc8, 0x3e, 0x42, 0x20, 0xa2, 0x40, 0x20, 0xca, 0x43, 0x20,
+  0x3e, 0x42, 0x20, 0xa2, 0x40, 0x20, 0x37, 0xbf, 0x7f, 0x10, 0x08, 0xf0,
+  0xc0, 0x10, 0xd8, 0xd7, 0xbf, 0x7f, 0x90, 0x80, 0x92, 0xd2, 0xff, 0x7f,
+  0xc0, 0x00, 0xe4, 0x03, 0x10, 0x00, 0xcf, 0x04, 0x00, 0x13, 0xf0, 0x8f,
+  0x08, 0x05, 0x5e, 0xc4, 0x08, 0x78, 0x84, 0x00, 0x66, 0xf6, 0xbf, 0x7f,
+  0xaf, 0xbf, 0x7f, 0x18, 0x00, 0x64, 0x10, 0x18, 0xc8, 0xc0, 0xdb, 0x1f,
+  0x57, 0x17, 0xfe, 0x00, 0x7c, 0x31, 0x00, 0xfc, 0xa1, 0x00, 0x3c, 0x23,
+  0x03, 0x18, 0xe5, 0x18, 0x84, 0x1d, 0x09, 0x00, 0x00, 0x00, 0xea, 0x52,
+  0x96, 0x40, 0x20, 0x00, 0x00, 0x66, 0x16, 0x00, 0x60, 0x4a, 0x41, 0x20,
+  0x80, 0x9d, 0x1d, 0xf8, 0x93, 0x62, 0x07, 0x1c, 0xe5, 0x08, 0x00, 0x64,
+  0x00, 0x00, 0x74, 0xe8, 0x93, 0x62, 0xfd, 0xff, 0xff, 0x3c, 0xfc, 0x87,
+  0x12, 0x40, 0x60, 0x44, 0x00, 0x64, 0x09, 0x00, 0x00, 0x44, 0xc5, 0x7f,
+  0x09, 0x00, 0x00, 0x08, 0xea, 0x52, 0x84, 0x00, 0x66, 0xc2, 0xbf, 0x7f,
+  0x4a, 0x41, 0x20, 0x80, 0x9d, 0x1d, 0xcc, 0xfb, 0x63, 0xbf, 0xbf, 0x7f,
+  0x03, 0x00, 0xe0, 0xcc, 0xfb, 0x63, 0x03, 0x60, 0x20, 0x07, 0x04, 0xe0,
+  0xb7, 0x00, 0xfe, 0x1f, 0x01, 0xfe, 0x03, 0x00, 0xe0, 0xc4, 0x8b, 0x62,
+  0x40, 0x80, 0x1d, 0x07, 0x04, 0xe0, 0x03, 0x18, 0xe5, 0x10, 0x84, 0x1d,
+  0x60, 0x08, 0xc8, 0x00, 0x08, 0x64, 0x03, 0xc8, 0xf2, 0x18, 0x00, 0x74,
+  0x0c, 0x00, 0x25, 0x58, 0x8d, 0x3e, 0x2c, 0x00, 0xc8, 0x5c, 0x89, 0x3e,
+  0x44, 0x81, 0x40, 0x08, 0x89, 0x3e, 0x9b, 0x44, 0xfb, 0x90, 0x9d, 0x1d,
+  0x00, 0x95, 0x1d, 0x07, 0x1c, 0xe5, 0x03, 0x10, 0xe5, 0x14, 0x7c, 0x27,
+  0x58, 0x7c, 0x27, 0x03, 0xd4, 0xfa, 0x47, 0xd8, 0xfa, 0x03, 0xd4, 0xf2,
+  0x47, 0xd8, 0xf2, 0xdc, 0x83, 0x62, 0x47, 0xd4, 0xfa, 0x47, 0xd4, 0xf2,
+  0x57, 0xd9, 0xfa, 0x03, 0xd4, 0xfa, 0x03, 0xd4, 0xf2, 0x07, 0x14, 0xe5,
+  0x4b, 0x24, 0xfe, 0x50, 0x04, 0xc8, 0x8a, 0x4c, 0x20, 0x8b, 0x04, 0x00,
+  0x52, 0x40, 0x20, 0x04, 0x88, 0x3e, 0x8c, 0x80, 0x25, 0x00, 0x8c, 0x40,
+  0x10, 0x08, 0xca, 0x00, 0x50, 0x1e, 0x00, 0x3c, 0x23, 0x04, 0x00, 0x64,
+  0xb0, 0xc7, 0xc9, 0x47, 0x00, 0x80, 0xa0, 0xc7, 0xc9, 0x07, 0x00, 0xfe,
+  0x8c, 0x00, 0x64, 0x01, 0x00, 0x00, 0x5f, 0x1a, 0xfe, 0x01, 0x04, 0x00,
+  0x8c, 0x05, 0x64, 0x01, 0x00, 0x00, 0xff, 0x19, 0xfe, 0x03, 0x00, 0x80,
+  0x00, 0x3c, 0x23, 0x30, 0x84, 0x62, 0x38, 0x40, 0x55, 0xba, 0x4f, 0x00,
+  0x04, 0x00, 0x64, 0x4c, 0x04, 0x72, 0xcd, 0xab, 0x89, 0xc8, 0x7b, 0x64,
+  0x45, 0x23, 0x01, 0xcc, 0x59, 0x64, 0x05, 0x00, 0x00, 0x00, 0xe6, 0x64,
+  0x86, 0x43, 0x20, 0xec, 0x83, 0x62, 0xbb, 0x63, 0x00, 0x80, 0x03, 0xe6,
+  0x04, 0x00, 0x64, 0x4c, 0x04, 0x48, 0xc3, 0x07, 0xf6, 0x3b, 0x00, 0xf2,
+  0x87, 0xc2, 0xfe, 0x46, 0x50, 0x07, 0x43, 0x78, 0xfe, 0x97, 0x03, 0xfe,
+  0x47, 0xc0, 0xf2, 0x44, 0x0c, 0x31, 0x10, 0x04, 0xca, 0x08, 0x08, 0xe8,
+  0x00, 0x3c, 0x23, 0x08, 0x00, 0x74, 0xc4, 0x3f, 0x64, 0x50, 0x08, 0x1d,
+  0x18, 0x00, 0x64, 0x44, 0x37, 0x64, 0x84, 0x09, 0x1e, 0x9b, 0x05, 0x00,
+  0x47, 0x44, 0x00, 0xec, 0xc7, 0x73, 0x84, 0x03, 0x64, 0x0b, 0x07, 0xf2,
+  0x57, 0xc3, 0xfe, 0x9f, 0x11, 0xf2, 0xc7, 0x11, 0xf2, 0xef, 0x11, 0xf2,
+  0x17, 0x12, 0xf2, 0x3f, 0x12, 0xf2, 0x67, 0x12, 0xf2, 0xe7, 0x51, 0xf2,
+  0xff, 0x50, 0xf2, 0xcf, 0x51, 0xf2, 0x44, 0x00, 0x64, 0xf3, 0x06, 0xf2,
+  0x8d, 0xd6, 0x92, 0x84, 0x28, 0x64, 0xc3, 0x46, 0xf2, 0xb7, 0x01, 0xfe,
+  0x35, 0x00, 0x00, 0x84, 0x12, 0x64, 0xb3, 0x06, 0xf2, 0x35, 0x00, 0x00,
+  0x84, 0x06, 0x64, 0xbb, 0x06, 0xf2, 0x31, 0x00, 0x00, 0x04, 0xea, 0x64,
+  0xd3, 0x06, 0xf2, 0x31, 0x00, 0x00, 0x04, 0xf6, 0x64, 0xc3, 0x06, 0xf2,
+  0x31, 0x00, 0x00, 0x44, 0xf5, 0x64, 0xdb, 0x06, 0xf2, 0x39, 0x00, 0x00,
+  0x84, 0x95, 0x64, 0xcb, 0x06, 0xf2, 0x31, 0x00, 0x00, 0x04, 0xc6, 0x64,
+  0xe3, 0x06, 0xf2, 0x67, 0xc3, 0xfe, 0xc4, 0xff, 0x64, 0x5b, 0x06, 0xf2,
+  0x44, 0x00, 0x64, 0xe3, 0x05, 0xf2, 0x67, 0xc3, 0xfe, 0x87, 0xc2, 0xfe,
+  0x05, 0x00, 0x00, 0x46, 0x50, 0x04, 0x43, 0x78, 0xfe, 0x84, 0x00, 0x64,
+  0x05, 0x10, 0x00, 0x44, 0x86, 0x80, 0x01, 0xad, 0xde, 0x44, 0x00, 0x64,
+  0x4b, 0x04, 0x00, 0x4f, 0x08, 0x00, 0x53, 0x0c, 0x00, 0x57, 0x10, 0x00,
+  0x5b, 0x14, 0x00, 0x5f, 0x18, 0x00, 0x63, 0x1c, 0x00, 0x67, 0x20, 0x00,
+  0x6b, 0x24, 0x00, 0x6f, 0x28, 0x00, 0x73, 0x2c, 0x00, 0x77, 0x30, 0x00,
+  0x7b, 0x34, 0x00, 0x7f, 0x38, 0x00, 0x40, 0x60, 0x26, 0x40, 0xe0, 0x26,
+  0x00, 0x00, 0x23, 0x08, 0x41, 0x64, 0x05, 0x00, 0x00, 0x04, 0xd8, 0x64,
+  0x03, 0x48, 0xf2, 0x0b, 0x44, 0xf2, 0xfd, 0xff, 0xff, 0x08, 0xfb, 0x64,
+  0x05, 0x00, 0x00, 0x04, 0xd8, 0x64, 0x13, 0x48, 0xf2, 0x1b, 0x44, 0xf2,
+  0x08, 0x03, 0x64, 0x04, 0x38, 0x64, 0x23, 0x48, 0xf2, 0x2b, 0x44, 0xf2,
+  0x05, 0x00, 0x00, 0x08, 0xe3, 0x64, 0x0d, 0x00, 0x00, 0x04, 0xf0, 0x64,
+  0x33, 0x48, 0xf2, 0x3b, 0x44, 0xf2, 0x05, 0x10, 0x00, 0x08, 0x03, 0x64,
+  0x05, 0x10, 0x00, 0x04, 0x78, 0x64, 0x43, 0x48, 0xf2, 0x4b, 0x44, 0xf2,
+  0x87, 0x1d, 0xfe, 0x0f, 0x20, 0xe5, 0x00, 0x41, 0x64, 0xfd, 0xff, 0xff,
+  0xf0, 0x97, 0x63, 0x00, 0x00, 0x66, 0xa2, 0x00, 0x60, 0x14, 0x00, 0x64,
+  0xa8, 0x14, 0xc8, 0x18, 0x44, 0x64, 0x82, 0x41, 0x20, 0xfd, 0xff, 0xff,
+  0xd0, 0x93, 0x63, 0x22, 0x40, 0x20, 0x83, 0x11, 0x00, 0xfd, 0xff, 0xff,
+  0xe0, 0x8f, 0x63, 0xa3, 0x03, 0x90, 0x83, 0x21, 0x00, 0xfd, 0xff, 0xff,
+  0xf0, 0x8b, 0x63, 0x87, 0x23, 0x80, 0x0a, 0x40, 0x20, 0x02, 0x42, 0x20,
+  0xdf, 0x05, 0x00, 0xd8, 0x97, 0x62, 0x6c, 0x9d, 0x3a, 0x9b, 0x31, 0x00,
+  0xba, 0xff, 0x7f, 0xd4, 0x00, 0x64, 0x80, 0x14, 0xc8, 0x18, 0x44, 0x74,
+  0x82, 0x41, 0x20, 0xfd, 0xff, 0xff, 0xc8, 0x83, 0x63, 0x22, 0x40, 0x20,
+  0x83, 0x11, 0x00, 0xfd, 0xff, 0xff, 0xd8, 0xff, 0x62, 0x0a, 0x40, 0x20,
+  0x03, 0x02, 0x50, 0xec, 0x93, 0x62, 0xdf, 0x05, 0x00, 0x6c, 0x1d, 0x3a,
+  0x9b, 0x21, 0x00, 0xce, 0xbf, 0x7f, 0x00, 0x42, 0x64, 0xfd, 0xff, 0xff,
+  0xe0, 0xf7, 0x62, 0x22, 0x40, 0x20, 0x00, 0x43, 0x64, 0xfd, 0xff, 0xff,
+  0xf0, 0xf3, 0x62, 0x1e, 0x40, 0x20, 0x00, 0x00, 0x64, 0x05, 0x00, 0x00,
+  0x14, 0xe0, 0x55, 0x18, 0x00, 0xc8, 0xc5, 0xff, 0xff, 0xe8, 0x9b, 0x63,
+  0xd0, 0x87, 0x62, 0x00, 0x00, 0x64, 0x28, 0x00, 0xc8, 0x4a, 0x41, 0x20,
+  0x00, 0x9e, 0x1d, 0xc5, 0xff, 0xff, 0xd4, 0x97, 0x63, 0x00, 0x00, 0x64,
+  0x18, 0x00, 0xc8, 0xc5, 0xff, 0xff, 0xe4, 0x93, 0x63, 0x00, 0x00, 0x64,
+  0x28, 0x00, 0xc8, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0xc5, 0xff, 0xff,
+  0xdc, 0x8f, 0x63, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0x57, 0xf6, 0x7f,
+  0x03, 0x00, 0xe0, 0x00, 0x00, 0x64, 0x18, 0x00, 0xc8, 0xc5, 0xff, 0xff,
+  0xfc, 0x87, 0x63, 0x00, 0x00, 0x64, 0x90, 0x00, 0xc8, 0xc5, 0xff, 0xff,
+  0xcc, 0x87, 0x63, 0x00, 0x00, 0x64, 0x18, 0x00, 0xc8, 0xc5, 0xff, 0xff,
+  0xdc, 0x83, 0x63, 0x0b, 0xc1, 0xf1, 0x8e, 0x68, 0x00, 0x13, 0x4c, 0xf2,
+  0x31, 0x00, 0x00, 0x90, 0xf1, 0x64, 0xe3, 0x12, 0xf2, 0x35, 0x00, 0x00,
+  0xbc, 0x1e, 0x64, 0xcb, 0x3e, 0xf2, 0x67, 0xc3, 0xfe, 0x07, 0x04, 0xe0,
+  0x40, 0x00, 0x65, 0x5b, 0x02, 0xf2, 0x01, 0x00, 0x82, 0x07, 0x00, 0x00,
+  0x33, 0x06, 0xf2, 0x67, 0xc3, 0xfe, 0xaf, 0xbf, 0x7f, 0x88, 0x08, 0x31,
+  0x18, 0x08, 0xca, 0x48, 0x10, 0x5a, 0x10, 0x08, 0x7a, 0x00, 0x3c, 0x23,
+  0x0c, 0x00, 0x64, 0x4c, 0xcc, 0x1e, 0x84, 0x08, 0x31, 0x10, 0x04, 0xca,
+  0x10, 0x0c, 0x7a, 0x00, 0x3c, 0x23, 0xf9, 0xff, 0xff, 0x98, 0xc5, 0x62,
+  0xcf, 0x14, 0xfe, 0x4b, 0xc3, 0xfe, 0x63, 0xc3, 0xfe, 0x67, 0xc3, 0xfe,
+  0x8f, 0x03, 0x80, 0x83, 0x13, 0x80, 0xbb, 0x23, 0x00, 0xc0, 0x00, 0x86,
+  0x02, 0xbc, 0x9f, 0x00, 0x3c, 0x23, 0xa0, 0xcf, 0x7b, 0x67, 0xc3, 0xfe,
+  0x63, 0xc3, 0xfe, 0xa7, 0x1f, 0xfe, 0x10, 0x00, 0x64, 0xc5, 0xff, 0xff,
+  0xbc, 0x93, 0x72, 0xcf, 0x1f, 0xfe
+};
+
+#define PMC_DTCM_LOG_SIZE 256
+
+const unsigned char pmcdata[] = {
+  0x98, 0x0b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x28, 0x01, 0x00, 0x00, 0x98, 0x0b, 0x00, 0x00, 0x44, 0x04, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42,
+  0x43, 0x44, 0x45, 0x46, 0x00, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
+  0x37, 0x38, 0x39, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x00, 0x28, 0x6e,
+  0x75, 0x6c, 0x6c, 0x29, 0x00, 0x25, 0x30, 0x34, 0x75, 0x3a, 0x20, 0x00,
+  0x73, 0x63, 0x72, 0x61, 0x74, 0x63, 0x68, 0x3a, 0x20, 0x30, 0x78, 0x25,
+  0x30, 0x38, 0x78, 0x0a, 0x00, 0x50, 0x4d, 0x42, 0x5f, 0x41, 0x52, 0x53,
+  0x20, 0x61, 0x74, 0x20, 0x44, 0x65, 0x76, 0x41, 0x64, 0x64, 0x72, 0x3d,
+  0x25, 0x64, 0x20, 0x62, 0x75, 0x73, 0x20, 0x25, 0x64, 0x20, 0x69, 0x73,
+  0x6c, 0x61, 0x6e, 0x64, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x50, 0x4d, 0x42,
+  0x5f, 0x50, 0x56, 0x54, 0x4d, 0x4f, 0x4e, 0x20, 0x61, 0x74, 0x20, 0x44,
+  0x65, 0x76, 0x41, 0x64, 0x64, 0x72, 0x3d, 0x25, 0x64, 0x20, 0x62, 0x75,
+  0x73, 0x20, 0x25, 0x64, 0x20, 0x69, 0x73, 0x6c, 0x61, 0x6e, 0x64, 0x20,
+  0x25, 0x64, 0x0a, 0x00, 0x50, 0x4d, 0x43, 0x5f, 0x56, 0x45, 0x52, 0x3a,
+  0x25, 0x64, 0x2e, 0x25, 0x64, 0x2e, 0x25, 0x64, 0x0a, 0x00, 0x24, 0x43,
+  0x68, 0x61, 0x6e, 0x67, 0x65, 0x3a, 0x20, 0x33, 0x30, 0x30, 0x30, 0x32,
+  0x37, 0x20, 0x24, 0x00, 0x32, 0x30, 0x31, 0x30, 0x30, 0x32, 0x5f, 0x30,
+  0x39, 0x33, 0x34, 0x00, 0x54, 0x53, 0x3a, 0x25, 0x73, 0x0a, 0x00, 0x50,
+  0x41, 0x52, 0x54, 0x49, 0x44, 0x3a, 0x25, 0x78, 0x20, 0x73, 0x6b, 0x69,
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+  0x65, 0x64, 0x20, 0x66, 0x72, 0x6f, 0x6d, 0x20, 0x50, 0x56, 0x54, 0x20,
+  0x30, 0x78, 0x25, 0x78, 0x20, 0x3d, 0x20, 0x25, 0x64, 0x6d, 0x56, 0x0a,
+  0x00, 0x56, 0x41, 0x44, 0x43, 0x31, 0x20, 0x72, 0x65, 0x61, 0x64, 0x65,
+  0x64, 0x20, 0x66, 0x72, 0x6f, 0x6d, 0x20, 0x56, 0x49, 0x4e, 0x20, 0x30,
+  0x78, 0x25, 0x78, 0x20, 0x3d, 0x20, 0x25, 0x64, 0x6d, 0x56, 0x0a, 0x00,
+  0x56, 0x41, 0x44, 0x43, 0x32, 0x20, 0x72, 0x65, 0x61, 0x64, 0x65, 0x64,
+  0x20, 0x66, 0x72, 0x6f, 0x6d, 0x20, 0x56, 0x49, 0x4e, 0x20, 0x30, 0x78,
+  0x25, 0x78, 0x20, 0x3d, 0x20, 0x25, 0x64, 0x6d, 0x56, 0x0a, 0x00, 0x44,
+  0x75, 0x6d, 0x70, 0x20, 0x61, 0x6c, 0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73,
+  0x20, 0x6f, 0x6e, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x0a,
+  0x00, 0x44, 0x65, 0x76, 0x41, 0x64, 0x64, 0x72, 0x20, 0x3a, 0x20, 0x25,
+  0x64, 0x20, 0x00, 0x25, 0x63, 0x31, 0x36, 0x3a, 0x20, 0x25, 0x64, 0x20,
+  0x20, 0x20, 0x25, 0x63, 0x32, 0x30, 0x3a, 0x20, 0x25, 0x64, 0x20, 0x20,
+  0x20, 0x00, 0x52, 0x34, 0x38, 0x5f, 0x25, 0x64, 0x3a, 0x20, 0x25, 0x75,
+  0x0a, 0x00, 0x55, 0x31, 0x36, 0x00, 0x55, 0x32, 0x30, 0x00, 0x4c, 0x31,
+  0x36, 0x00, 0x4c, 0x32, 0x30, 0x00, 0x53, 0x31, 0x36, 0x00, 0x53, 0x32,
+  0x30, 0x00, 0x00, 0x00, 0xce, 0xb0, 0x5c, 0xfe, 0x00, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+#endif //DEVICE_TREE
+#endif //PMC_ROMDATA_4912_H
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_firmware_63146.h b/arch/arm/mach-bcmbca/pmc/pmc_firmware_63146.h
new file mode 100644
index 0000000000..8853ae32a9
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_firmware_63146.h
@@ -0,0 +1,1427 @@
+/*
+ * * <:copyright-BRCM:2017:DUAL/GPL:standard
+ * * 
+ * *    Copyright (c) 2017 Broadcom 
+ * *    All Rights Reserved
+ * * 
+ * * This program is free software; you can redistribute it and/or modify
+ * * it under the terms of the GNU General Public License, version 2, as published by
+ * * the Free Software Foundation (the "GPL").
+ * * 
+ * * This program is distributed in the hope that it will be useful,
+ * * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * * GNU General Public License for more details.
+ * * 
+ * * 
+ * * A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+ * * writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * * Boston, MA 02111-1307, USA.
+ * * 
+ * * :>
+ * */
+
+#ifndef PMC_ROMDATA_63146_H
+#define PMC_ROMDATA_63146_H
+#define PMC_VER_IMPL 3
+#define PMC_VER_MAJOR 3
+#define PMC_VER_MINOR 4
+#define PMC_VER_CHANGELIST "$Change: 300027 $"
+#ifndef DEVICE_TREE
+const unsigned char pmcappdata[] = {
+  0xeb, 0x42, 0xf2, 0x35, 0x00, 0x00, 0x4f, 0x19, 0xfe, 0x00, 0x00, 0x00,
+  0x11, 0x10, 0x00, 0x04, 0x0b, 0x4e, 0x40, 0x00, 0x84, 0x07, 0xbc, 0xfd,
+  0x11, 0x10, 0x00, 0x08, 0x0b, 0x64, 0x8e, 0x08, 0xc0, 0xc0, 0x80, 0x90,
+  0xfa, 0xff, 0x7f, 0x04, 0x00, 0x64, 0x10, 0x04, 0x5e, 0x00, 0x01, 0x66,
+  0x0e, 0x00, 0x60, 0x40, 0xc0, 0x92, 0x12, 0x40, 0x60, 0x11, 0x10, 0x00,
+  0x74, 0x05, 0x82, 0x00, 0x3c, 0x23, 0x44, 0x10, 0x78, 0xdf, 0xbf, 0x7f,
+  0x00, 0x80, 0xa2, 0x11, 0x10, 0x00, 0x04, 0x01, 0x80, 0x11, 0x10, 0x00,
+  0x04, 0x06, 0x64, 0x4b, 0x20, 0x80, 0xbc, 0x7c, 0xb3, 0xfa, 0xbf, 0x7f,
+  0x00, 0x3c, 0x23, 0x04, 0xfa, 0x64, 0x00, 0x44, 0x24, 0xaf, 0x1f, 0xfe,
+  0x47, 0x44, 0x00, 0xfd, 0xff, 0xff, 0x7c, 0x7c, 0x93, 0x03, 0xbc, 0xfd,
+  0x03, 0x04, 0x00, 0x3c, 0xfc, 0xe4, 0xeb, 0xbf, 0x7f, 0x0d, 0x00, 0x00,
+  0x08, 0x60, 0x55, 0x0d, 0x00, 0x00, 0x12, 0xbc, 0x1f, 0x03, 0x0c, 0x36,
+  0x87, 0x00, 0x80, 0x3d, 0x00, 0x00, 0x4e, 0x00, 0x00, 0x3d, 0x00, 0x00,
+  0xc0, 0x00, 0x92, 0x12, 0x00, 0x60, 0x08, 0x00, 0x64, 0x82, 0x40, 0x20,
+  0x00, 0x3c, 0x23, 0x4f, 0x24, 0x37, 0xec, 0x90, 0x48, 0x12, 0x40, 0x60,
+  0x47, 0x10, 0x35, 0x7c, 0x00, 0x48, 0xe6, 0xbf, 0x7f, 0x8b, 0x10, 0x00,
+  0xc3, 0xbf, 0x7f, 0x28, 0x00, 0x72, 0x00, 0x08, 0x2b, 0x0d, 0x00, 0x00,
+  0x03, 0xf0, 0x82, 0x24, 0x00, 0x72, 0x40, 0x00, 0x75, 0x0d, 0x00, 0x00,
+  0x34, 0x87, 0x82, 0x00, 0x3c, 0x23, 0x1b, 0x08, 0xe6, 0xfd, 0xff, 0xff,
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+  0x18, 0x44, 0x64, 0x82, 0x41, 0x20, 0xfd, 0xff, 0xff, 0xd0, 0x93, 0x63,
+  0x22, 0x40, 0x20, 0x83, 0x11, 0x00, 0xfd, 0xff, 0xff, 0xe0, 0x8f, 0x63,
+  0xa3, 0x03, 0x90, 0x83, 0x21, 0x00, 0xfd, 0xff, 0xff, 0xf0, 0x8b, 0x63,
+  0x87, 0x23, 0x80, 0x0a, 0x40, 0x20, 0x02, 0x42, 0x20, 0xdf, 0x05, 0x00,
+  0xd8, 0x97, 0x62, 0x6c, 0x9d, 0x3a, 0x9b, 0x31, 0x00, 0xba, 0xff, 0x7f,
+  0xd4, 0x00, 0x64, 0x80, 0x14, 0xc8, 0x18, 0x44, 0x74, 0x82, 0x41, 0x20,
+  0xfd, 0xff, 0xff, 0xc8, 0x83, 0x63, 0x22, 0x40, 0x20, 0x83, 0x11, 0x00,
+  0xfd, 0xff, 0xff, 0xd8, 0xff, 0x62, 0x0a, 0x40, 0x20, 0x03, 0x02, 0x50,
+  0xec, 0x93, 0x62, 0xdf, 0x05, 0x00, 0x6c, 0x1d, 0x3a, 0x9b, 0x21, 0x00,
+  0xce, 0xbf, 0x7f, 0x00, 0x42, 0x64, 0xfd, 0xff, 0xff, 0xe0, 0xf7, 0x62,
+  0x22, 0x40, 0x20, 0x00, 0x43, 0x64, 0xfd, 0xff, 0xff, 0xf0, 0xf3, 0x62,
+  0x1e, 0x40, 0x20, 0x00, 0x00, 0x64, 0x05, 0x00, 0x00, 0x14, 0xe0, 0x55,
+  0x18, 0x00, 0xc8, 0xc5, 0xff, 0xff, 0xc4, 0xa7, 0x63, 0xd0, 0x87, 0x62,
+  0x00, 0x00, 0x64, 0x28, 0x00, 0xc8, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d,
+  0xc5, 0xff, 0xff, 0xf0, 0x9f, 0x63, 0x00, 0x00, 0x64, 0x18, 0x00, 0xc8,
+  0xc5, 0xff, 0xff, 0xc0, 0x9f, 0x63, 0x00, 0x00, 0x64, 0x28, 0x00, 0xc8,
+  0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0xc5, 0xff, 0xff, 0xf8, 0x97, 0x63,
+  0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0x57, 0xf6, 0x7f, 0x03, 0x00, 0xe0,
+  0x00, 0x00, 0x64, 0x18, 0x00, 0xc8, 0xc5, 0xff, 0xff, 0xd8, 0x93, 0x63,
+  0x00, 0x00, 0x64, 0x90, 0x00, 0xc8, 0xc5, 0xff, 0xff, 0xe8, 0x8f, 0x63,
+  0x00, 0x00, 0x64, 0x18, 0x00, 0xc8, 0xc5, 0xff, 0xff, 0xf8, 0x8b, 0x63,
+  0x0b, 0xc1, 0xf1, 0x8e, 0x68, 0x00, 0x13, 0x4c, 0xf2, 0x31, 0x00, 0x00,
+  0xd0, 0xe7, 0x64, 0xe3, 0x12, 0xf2, 0x35, 0x00, 0x00, 0xfc, 0x14, 0x64,
+  0xcb, 0x3e, 0xf2, 0x67, 0xc3, 0xfe, 0x07, 0x04, 0xe0, 0x40, 0x00, 0x65,
+  0x5b, 0x02, 0xf2, 0x01, 0x00, 0x82, 0x07, 0x00, 0x00, 0x33, 0x06, 0xf2,
+  0x67, 0xc3, 0xfe, 0xaf, 0xbf, 0x7f, 0x88, 0x08, 0x31, 0x18, 0x08, 0xca,
+  0x48, 0x10, 0x5a, 0x10, 0x08, 0x7a, 0x00, 0x3c, 0x23, 0x0c, 0x00, 0x64,
+  0x4c, 0xcc, 0x1e, 0x84, 0x08, 0x31, 0x10, 0x04, 0xca, 0x10, 0x0c, 0x7a,
+  0x00, 0x3c, 0x23, 0xf9, 0xff, 0xff, 0x98, 0xc5, 0x62, 0xcf, 0x14, 0xfe,
+  0x4b, 0xc3, 0xfe, 0x63, 0xc3, 0xfe, 0x67, 0xc3, 0xfe, 0x8f, 0x03, 0x80,
+  0x83, 0x13, 0x80, 0xbb, 0x23, 0x00, 0xc0, 0x00, 0x86, 0x02, 0xbc, 0x9f,
+  0x00, 0x3c, 0x23, 0xa0, 0xcf, 0x7b, 0x67, 0xc3, 0xfe, 0x63, 0xc3, 0xfe,
+  0xa7, 0x1f, 0xfe, 0x10, 0x00, 0x64, 0xc5, 0xff, 0xff, 0xf4, 0xd0, 0x72,
+  0xcf, 0x1f, 0xfe
+};
+
+#define PMC_DTCM_LOG_SIZE 256
+
+const unsigned char pmcdata[] = {
+  0x98, 0x0b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x28, 0x01, 0x00, 0x00, 0x98, 0x0b, 0x00, 0x00, 0x44, 0x04, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42,
+  0x43, 0x44, 0x45, 0x46, 0x00, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
+  0x37, 0x38, 0x39, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x00, 0x28, 0x6e,
+  0x75, 0x6c, 0x6c, 0x29, 0x00, 0x25, 0x30, 0x34, 0x75, 0x3a, 0x20, 0x00,
+  0x73, 0x63, 0x72, 0x61, 0x74, 0x63, 0x68, 0x3a, 0x20, 0x30, 0x78, 0x25,
+  0x30, 0x38, 0x78, 0x0a, 0x00, 0x50, 0x4d, 0x42, 0x5f, 0x41, 0x52, 0x53,
+  0x20, 0x61, 0x74, 0x20, 0x44, 0x65, 0x76, 0x41, 0x64, 0x64, 0x72, 0x3d,
+  0x25, 0x64, 0x20, 0x62, 0x75, 0x73, 0x20, 0x25, 0x64, 0x20, 0x69, 0x73,
+  0x6c, 0x61, 0x6e, 0x64, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x50, 0x4d, 0x42,
+  0x5f, 0x50, 0x56, 0x54, 0x4d, 0x4f, 0x4e, 0x20, 0x61, 0x74, 0x20, 0x44,
+  0x65, 0x76, 0x41, 0x64, 0x64, 0x72, 0x3d, 0x25, 0x64, 0x20, 0x62, 0x75,
+  0x73, 0x20, 0x25, 0x64, 0x20, 0x69, 0x73, 0x6c, 0x61, 0x6e, 0x64, 0x20,
+  0x25, 0x64, 0x0a, 0x00, 0x50, 0x4d, 0x43, 0x5f, 0x56, 0x45, 0x52, 0x3a,
+  0x25, 0x64, 0x2e, 0x25, 0x64, 0x2e, 0x25, 0x64, 0x0a, 0x00, 0x24, 0x43,
+  0x68, 0x61, 0x6e, 0x67, 0x65, 0x3a, 0x20, 0x33, 0x30, 0x30, 0x30, 0x32,
+  0x37, 0x20, 0x24, 0x00, 0x32, 0x30, 0x31, 0x30, 0x30, 0x32, 0x5f, 0x30,
+  0x39, 0x33, 0x34, 0x00, 0x54, 0x53, 0x3a, 0x25, 0x73, 0x0a, 0x00, 0x50,
+  0x41, 0x52, 0x54, 0x49, 0x44, 0x3a, 0x25, 0x78, 0x20, 0x73, 0x6b, 0x69,
+  0x70, 0x70, 0x65, 0x64, 0x20, 0x63, 0x68, 0x69, 0x70, 0x20, 0x69, 0x64,
+  0x20, 0x76, 0x61, 0x6c, 0x69, 0x64, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x0a,
+  0x00, 0x53, 0x49, 0x47, 0x4e, 0x5f, 0x4f, 0x46, 0x46, 0x5f, 0x4d, 0x56,
+  0x20, 0x25, 0x75, 0x0a, 0x00, 0x52, 0x34, 0x38, 0x20, 0x49, 0x44, 0x2c,
+  0x20, 0x54, 0x61, 0x72, 0x67, 0x65, 0x74, 0x20, 0x28, 0x4b, 0x48, 0x7a,
+  0x29, 0x2c, 0x20, 0x54, 0x61, 0x72, 0x67, 0x65, 0x74, 0x20, 0x28, 0x43,
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+  0x64, 0x2c, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x30, 0x33, 0x2c, 0x20, 0x25,
+  0x64, 0x2c, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x25,
+  0x64, 0x0a, 0x00, 0x30, 0x34, 0x2c, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x25,
+  0x64, 0x2c, 0x20, 0x25, 0x64, 0x2c, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x30,
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+  0x66, 0x6f, 0x72, 0x20, 0x25, 0x64, 0x20, 0x68, 0x69, 0x20, 0x25, 0x64,
+  0x20, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x53, 0x65, 0x74, 0x74,
+  0x69, 0x6e, 0x67, 0x20, 0x52, 0x34, 0x38, 0x5f, 0x25, 0x64, 0x20, 0x54,
+  0x68, 0x72, 0x65, 0x73, 0x68, 0x6f, 0x6c, 0x64, 0x73, 0x20, 0x68, 0x69,
+  0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x52,
+  0x34, 0x38, 0x5f, 0x25, 0x64, 0x20, 0x53, 0x6b, 0x69, 0x70, 0x70, 0x65,
+  0x64, 0x0a, 0x00, 0x56, 0x41, 0x44, 0x43, 0x20, 0x72, 0x65, 0x61, 0x64,
+  0x65, 0x64, 0x20, 0x66, 0x72, 0x6f, 0x6d, 0x20, 0x50, 0x56, 0x54, 0x20,
+  0x30, 0x78, 0x25, 0x78, 0x20, 0x3d, 0x20, 0x25, 0x64, 0x6d, 0x56, 0x0a,
+  0x00, 0x56, 0x41, 0x44, 0x43, 0x31, 0x20, 0x72, 0x65, 0x61, 0x64, 0x65,
+  0x64, 0x20, 0x66, 0x72, 0x6f, 0x6d, 0x20, 0x56, 0x49, 0x4e, 0x20, 0x30,
+  0x78, 0x25, 0x78, 0x20, 0x3d, 0x20, 0x25, 0x64, 0x6d, 0x56, 0x0a, 0x00,
+  0x56, 0x41, 0x44, 0x43, 0x32, 0x20, 0x72, 0x65, 0x61, 0x64, 0x65, 0x64,
+  0x20, 0x66, 0x72, 0x6f, 0x6d, 0x20, 0x56, 0x49, 0x4e, 0x20, 0x30, 0x78,
+  0x25, 0x78, 0x20, 0x3d, 0x20, 0x25, 0x64, 0x6d, 0x56, 0x0a, 0x00, 0x44,
+  0x75, 0x6d, 0x70, 0x20, 0x61, 0x6c, 0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73,
+  0x20, 0x6f, 0x6e, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x0a,
+  0x00, 0x44, 0x65, 0x76, 0x41, 0x64, 0x64, 0x72, 0x20, 0x3a, 0x20, 0x25,
+  0x64, 0x20, 0x00, 0x25, 0x63, 0x31, 0x36, 0x3a, 0x20, 0x25, 0x64, 0x20,
+  0x20, 0x20, 0x25, 0x63, 0x32, 0x30, 0x3a, 0x20, 0x25, 0x64, 0x20, 0x20,
+  0x20, 0x00, 0x52, 0x34, 0x38, 0x5f, 0x25, 0x64, 0x3a, 0x20, 0x25, 0x75,
+  0x0a, 0x00, 0x55, 0x31, 0x36, 0x00, 0x55, 0x32, 0x30, 0x00, 0x4c, 0x31,
+  0x36, 0x00, 0x4c, 0x32, 0x30, 0x00, 0x53, 0x31, 0x36, 0x00, 0x53, 0x32,
+  0x30, 0x00, 0x00, 0x00, 0xdb, 0xea, 0x31, 0x28, 0x00, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+#endif //DEVICE_TREE
+#endif //PMC_ROMDATA_63146_H
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_firmware_63178.h b/arch/arm/mach-bcmbca/pmc/pmc_firmware_63178.h
new file mode 100644
index 0000000000..f0a5d75e5f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_firmware_63178.h
@@ -0,0 +1,1388 @@
+/*
+ * * <:copyright-BRCM:2017:DUAL/GPL:standard
+ * * 
+ * *    Copyright (c) 2017 Broadcom 
+ * *    All Rights Reserved
+ * * 
+ * * This program is free software; you can redistribute it and/or modify
+ * * it under the terms of the GNU General Public License, version 2, as published by
+ * * the Free Software Foundation (the "GPL").
+ * * 
+ * * This program is distributed in the hope that it will be useful,
+ * * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * * GNU General Public License for more details.
+ * * 
+ * * 
+ * * A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+ * * writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * * Boston, MA 02111-1307, USA.
+ * * 
+ * * :>
+ * */
+
+#ifndef PMC_ROMDATA_63178_H
+#define PMC_ROMDATA_63178_H
+#define PMC_VER_IMPL 3
+#define PMC_VER_MAJOR 2
+#define PMC_VER_MINOR 2
+#define PMC_VER_CHANGELIST "$Change: 284027 $"
+const unsigned char pmcappdata[] = {
+  0x01, 0x00, 0x00, 0xbf, 0x03, 0xfe, 0x67, 0xc3, 0xfe, 0x4b, 0xc3, 0xfe,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x08, 0xe6, 0x05,
+  0x00, 0x00, 0x00, 0x8c, 0x52, 0x04, 0x00, 0x66, 0x5a, 0x00, 0x60, 0x09,
+  0x00, 0x00, 0x00, 0x92, 0x55, 0x05, 0x00, 0x00, 0x58, 0x7a, 0x64, 0x4c,
+  0x00, 0x72, 0x05, 0x00, 0x00, 0x00, 0x8e, 0x55, 0x44, 0x00, 0x64, 0x09,
+  0x00, 0x00, 0x44, 0x06, 0x81, 0x86, 0x41, 0x20, 0x39, 0x00, 0x00, 0xc4,
+  0xdb, 0x62, 0x05, 0x00, 0x00, 0x00, 0x8e, 0x55, 0x86, 0x41, 0x20, 0x39,
+  0x00, 0x00, 0xc8, 0xd7, 0x62, 0x48, 0x00, 0x64, 0x05, 0x00, 0x00, 0x84,
+  0x09, 0x7f, 0x07, 0x0c, 0xe6, 0x03, 0x00, 0x80, 0x00, 0x3c, 0x23, 0x0c,
+  0x88, 0x62, 0x38, 0x40, 0x55, 0xba, 0x4f, 0x00, 0x04, 0x00, 0x64, 0x4c,
+  0x04, 0x72, 0xcd, 0xab, 0x89, 0xc8, 0x7b, 0x64, 0x45, 0x23, 0x01, 0xcc,
+  0x59, 0x64, 0x05, 0x00, 0x00, 0x00, 0x8f, 0x64, 0x86, 0x43, 0x20, 0xec,
+  0x83, 0x62, 0xbb, 0x63, 0x00, 0x80, 0x03, 0xe6, 0x04, 0x00, 0x64, 0x4c,
+  0x04, 0x48, 0xc3, 0x07, 0xf6, 0x3b, 0x00, 0xf2, 0x87, 0xc2, 0xfe, 0x46,
+  0x50, 0x07, 0x43, 0x78, 0xfe, 0x87, 0x04, 0xfe, 0x47, 0xc0, 0xf2, 0x44,
+  0x0c, 0x31, 0x10, 0x04, 0xca, 0x08, 0x08, 0xe8, 0x00, 0x3c, 0x23, 0x03,
+  0xc0, 0xf1, 0x02, 0x68, 0x00, 0x03, 0x40, 0xf2, 0x03, 0xc7, 0xf1, 0x02,
+  0xfc, 0x00, 0x73, 0x40, 0xf2, 0x00, 0x3c, 0x23, 0x08, 0x00, 0x74, 0xc4,
+  0x3f, 0x64, 0x50, 0x08, 0x1d, 0x18, 0x00, 0x64, 0x44, 0x37, 0x64, 0x84,
+  0x09, 0x1e, 0x9b, 0x05, 0x00, 0x47, 0x44, 0x00, 0xec, 0xc7, 0x73, 0x84,
+  0x03, 0x64, 0x0b, 0x07, 0xf2, 0x57, 0xc3, 0xfe, 0x9f, 0x11, 0xf2, 0xc7,
+  0x11, 0xf2, 0xef, 0x11, 0xf2, 0x17, 0x12, 0xf2, 0x3f, 0x12, 0xf2, 0x67,
+  0x12, 0xf2, 0xe7, 0x51, 0xf2, 0xff, 0x50, 0xf2, 0x87, 0x13, 0xf2, 0xcf,
+  0x51, 0xf2, 0x44, 0x00, 0x64, 0x73, 0x06, 0xf2, 0x44, 0x00, 0x64, 0xf3,
+  0x06, 0xf2, 0x8d, 0xd6, 0x92, 0x84, 0x28, 0x64, 0xc3, 0x46, 0xf2, 0xa7,
+  0x01, 0xfe, 0x35, 0x0c, 0x00, 0x04, 0xbf, 0x64, 0xb3, 0x06, 0xf2, 0x35,
+  0x0c, 0x00, 0x04, 0xa7, 0x64, 0xbb, 0x06, 0xf2, 0x35, 0x0c, 0x00, 0x84,
+  0x9f, 0x64, 0xd3, 0x06, 0xf2, 0x35, 0x0c, 0x00, 0x04, 0xb3, 0x64, 0xc3,
+  0x06, 0xf2, 0x35, 0x0c, 0x00, 0x44, 0xa6, 0x64, 0xdb, 0x06, 0xf2, 0x01,
+  0x0c, 0x00, 0x04, 0xf2, 0x64, 0xcb, 0x06, 0xf2, 0x35, 0x0c, 0x00, 0x44,
+  0x85, 0x64, 0xe3, 0x06, 0xf2, 0x67, 0xc3, 0xfe, 0xc4, 0xff, 0x64, 0x5b,
+  0x06, 0xf2, 0x67, 0xc3, 0xfe, 0x87, 0xc2, 0xfe, 0x05, 0x00, 0x00, 0x46,
+  0x40, 0x04, 0x43, 0x78, 0xfe, 0x84, 0x00, 0x64, 0x05, 0x10, 0x00, 0x44,
+  0x86, 0x80, 0x01, 0xad, 0xde, 0x44, 0x00, 0x64, 0x4b, 0x04, 0x00, 0x4f,
+  0x08, 0x00, 0x53, 0x0c, 0x00, 0x57, 0x10, 0x00, 0x5b, 0x14, 0x00, 0x5f,
+  0x18, 0x00, 0x63, 0x1c, 0x00, 0x67, 0x20, 0x00, 0x6b, 0x24, 0x00, 0x6f,
+  0x28, 0x00, 0x73, 0x2c, 0x00, 0x77, 0x30, 0x00, 0x7b, 0x34, 0x00, 0x7f,
+  0x38, 0x00, 0x40, 0x60, 0x26, 0x40, 0xe0, 0x26, 0x00, 0x00, 0x23, 0x01,
+  0x0c, 0x00, 0x88, 0x08, 0x64, 0x39, 0x0c, 0x00, 0x04, 0x80, 0x64, 0x1b,
+  0x0b, 0xf2, 0x23, 0x07, 0xf2, 0x08, 0x53, 0x64, 0x05, 0x00, 0x00, 0x04,
+  0x80, 0x64, 0x03, 0x48, 0xf2, 0x0b, 0x44, 0xf2, 0xfd, 0xff, 0xff, 0x08,
+  0xf9, 0x64, 0xfd, 0x1f, 0x00, 0x04, 0xf8, 0x64, 0x13, 0x48, 0xf2, 0x1b,
+  0x44, 0xf2, 0xfd, 0xff, 0xff, 0x08, 0xfb, 0x64, 0x05, 0x00, 0x00, 0x04,
+  0x80, 0x64, 0x23, 0x48, 0xf2, 0x2b, 0x44, 0xf2, 0x08, 0x03, 0x64, 0x04,
+  0x38, 0x64, 0x33, 0x48, 0xf2, 0x3b, 0x44, 0xf2, 0x05, 0x00, 0x00, 0x08,
+  0x8b, 0x64, 0x0d, 0x00, 0x00, 0x04, 0xc0, 0x64, 0x43, 0x48, 0xf2, 0x4b,
+  0x44, 0xf2, 0xfd, 0xff, 0xff, 0x08, 0xfb, 0x64, 0xfd, 0x1f, 0x00, 0x04,
+  0xf8, 0x64, 0x53, 0x48, 0xf2, 0x5b, 0x44, 0xf2, 0x05, 0x10, 0x00, 0x08,
+  0x03, 0x64, 0x05, 0x10, 0x00, 0x04, 0x78, 0x64, 0x63, 0x48, 0xf2, 0x6b,
+  0x44, 0xf2, 0x08, 0x41, 0x64, 0x04, 0x48, 0x64, 0x73, 0x48, 0xf2, 0x7b,
+  0x44, 0xf2, 0xe7, 0x1c, 0xfe, 0x0f, 0x20, 0xe5, 0x00, 0x41, 0x64, 0xd8,
+  0xd7, 0x63, 0x00, 0x00, 0x66, 0x8e, 0x00, 0x60, 0x14, 0x00, 0x64, 0x90,
+  0x14, 0xc8, 0x18, 0x44, 0x64, 0x82, 0x41, 0x20, 0xfc, 0xd3, 0x63, 0x22,
+  0x40, 0x20, 0x83, 0x11, 0x00, 0xf0, 0xd3, 0x63, 0xa3, 0x03, 0x90, 0x83,
+  0x21, 0x00, 0xe4, 0xd3, 0x63, 0x87, 0x23, 0x80, 0x0a, 0x40, 0x20, 0x02,
+  0x42, 0x20, 0xdf, 0x05, 0x00, 0xd8, 0x97, 0x62, 0x6c, 0x9d, 0x3a, 0x9b,
+  0x31, 0x00, 0xc6, 0xff, 0x7f, 0xd4, 0x00, 0x64, 0x70, 0x14, 0xc8, 0x18,
+  0x44, 0x74, 0x82, 0x41, 0x20, 0xf0, 0xcf, 0x63, 0x22, 0x40, 0x20, 0x83,
+  0x11, 0x00, 0xe4, 0xcf, 0x63, 0x0a, 0x40, 0x20, 0x03, 0x02, 0x50, 0xf4,
+  0x93, 0x62, 0xdf, 0x05, 0x00, 0x6c, 0x1d, 0x3a, 0x9b, 0x21, 0x00, 0xd6,
+  0xbf, 0x7f, 0x00, 0x42, 0x64, 0xc0, 0xcf, 0x63, 0x22, 0x40, 0x20, 0x00,
+  0x43, 0x64, 0xf4, 0xcb, 0x63, 0x1e, 0x40, 0x20, 0x01, 0x0c, 0x00, 0xc0,
+  0x32, 0x64, 0x05, 0x00, 0x00, 0x14, 0x88, 0x55, 0x10, 0x00, 0xc8, 0xd0,
+  0xd3, 0x63, 0xd4, 0x87, 0x62, 0x01, 0x0c, 0x00, 0x00, 0x08, 0x64, 0x20,
+  0x00, 0xc8, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0xd0, 0xc3, 0x63, 0x00,
+  0x00, 0x64, 0x18, 0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xcc, 0xbb, 0x62, 0x00,
+  0x00, 0x64, 0x28, 0x00, 0xc8, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0xfd,
+  0xf3, 0xff, 0xc4, 0xb7, 0x62, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0x31,
+  0x00, 0x00, 0xe0, 0x9b, 0x63, 0x03, 0x00, 0xe0, 0x00, 0x00, 0x64, 0x18,
+  0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xd8, 0xaf, 0x62, 0x00, 0x00, 0x64, 0x98,
+  0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xe8, 0xab, 0x62, 0x00, 0x00, 0x64, 0x18,
+  0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xf8, 0xa7, 0x62, 0x0f, 0xc2, 0xf1, 0xd2,
+  0x68, 0x00, 0x23, 0x50, 0xf2, 0x00, 0x00, 0x64, 0x10, 0x00, 0xc8, 0xe3,
+  0x02, 0xf2, 0x35, 0x0c, 0x00, 0x00, 0xcb, 0x64, 0x10, 0x00, 0xc8, 0xcb,
+  0x02, 0xf2, 0x67, 0xc3, 0xfe, 0x07, 0x04, 0xe0, 0x40, 0x00, 0x65, 0x5b,
+  0x02, 0xf2, 0x01, 0x00, 0x82, 0x07, 0x00, 0x00, 0x33, 0x06, 0xf2, 0x48,
+  0x00, 0x64, 0xe3, 0x09, 0xf2, 0x67, 0xc3, 0xfe, 0xa3, 0xbf, 0x7f, 0x88,
+  0x08, 0x31, 0x18, 0x08, 0xca, 0x48, 0x10, 0x5a, 0x10, 0x08, 0x7a, 0x00,
+  0x3c, 0x23, 0x0c, 0x00, 0x64, 0x4c, 0xcc, 0x1e, 0x84, 0x08, 0x31, 0x10,
+  0x04, 0xca, 0x10, 0x0c, 0x7a, 0x00, 0x3c, 0x23, 0x05, 0x10, 0x00, 0x18,
+  0x28, 0x64, 0x70, 0x18, 0xc8, 0x83, 0x41, 0x90, 0x93, 0x45, 0x90, 0xa3,
+  0x79, 0x90, 0xb3, 0x7d, 0x90, 0x9f, 0xb7, 0xf1, 0xdc, 0xed, 0xa3, 0x83,
+  0x1d, 0x90, 0x1f, 0x8c, 0xf1, 0x93, 0x1d, 0x90, 0x9f, 0x8c, 0xf1, 0xa3,
+  0x1d, 0x90, 0x1f, 0xe0, 0xf1, 0xb3, 0x1d, 0x90, 0x18, 0x00, 0x64, 0x10,
+  0x18, 0xc8, 0xc0, 0xdb, 0x1f, 0x31, 0x00, 0x00, 0xf7, 0x0e, 0xfe, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x80, 0xa2, 0x11, 0x10, 0x00, 0x04, 0x01, 0x80, 0x11, 0x10, 0x00,
+  0x04, 0x06, 0x64, 0x4b, 0x20, 0x80, 0xbc, 0x7c, 0xb3, 0xfa, 0xbf, 0x7f,
+  0x00, 0x3c, 0x23, 0x04, 0xfa, 0x64, 0x00, 0x44, 0x24, 0xaf, 0x1f, 0xfe,
+  0x13, 0x00, 0xe0, 0x01, 0x12, 0x00, 0x10, 0x00, 0x64, 0x0f, 0x01, 0x84,
+  0xa0, 0x03, 0xe7, 0xbc, 0x7c, 0xb3, 0x0d, 0x00, 0x00, 0xd7, 0xa3, 0xf8,
+  0xff, 0x28, 0x3a, 0x8f, 0x0c, 0x00, 0xcb, 0x88, 0xf9, 0x8f, 0x23, 0x80,
+  0xc0, 0x43, 0x24, 0xbc, 0x08, 0x27, 0x03, 0xbc, 0xf2, 0xd3, 0x40, 0xd0,
+  0xa3, 0x0f, 0x90, 0xbf, 0x23, 0x80, 0xc0, 0x3f, 0xa4, 0xa3, 0x03, 0x90,
+  0x8f, 0x23, 0x80, 0xcf, 0x04, 0xda, 0xa3, 0x0f, 0x90, 0x87, 0x23, 0x80,
+  0x48, 0x00, 0xa2, 0xa3, 0x0b, 0x90, 0xbf, 0x23, 0x80, 0x03, 0xbd, 0x94,
+  0xa0, 0x03, 0xe7, 0x03, 0x81, 0x84, 0xa3, 0x03, 0x90, 0x8f, 0x23, 0x80,
+  0xf0, 0xb4, 0x26, 0xf2, 0xff, 0x7f, 0x93, 0x23, 0x80, 0xc8, 0x04, 0x64,
+  0x34, 0x15, 0x26, 0x16, 0x00, 0x40, 0x87, 0x23, 0x80, 0x78, 0x94, 0x26,
+  0x1a, 0x40, 0x60, 0x08, 0x02, 0x64, 0x0d, 0x00, 0x00, 0xd4, 0x0b, 0x82,
+  0x00, 0x00, 0x64, 0x17, 0x04, 0xe0, 0x01, 0x12, 0x00, 0x00, 0x4b, 0x55,
+  0xf7, 0xbf, 0x7f, 0x0b, 0x08, 0xe6, 0x01, 0x12, 0x00, 0x18, 0x00, 0x64,
+  0x93, 0x01, 0x84, 0xbf, 0x0c, 0x00, 0x0d, 0x00, 0x00, 0xd7, 0xa3, 0xf8,
+  0xbc, 0x7c, 0xb3, 0x93, 0x8d, 0x94, 0xcb, 0x8b, 0xf9, 0x0f, 0x29, 0x3a,
+  0xc0, 0x40, 0x24, 0x90, 0x08, 0x27, 0x0f, 0x90, 0xf2, 0xfd, 0x0f, 0x00,
+  0xc2, 0xbc, 0x1f, 0x0f, 0x04, 0xda, 0x04, 0x04, 0xa2, 0x83, 0x85, 0x94,
+  0xbf, 0x81, 0x84, 0xf0, 0xb7, 0x26, 0xfa, 0xff, 0x7f, 0xf4, 0x17, 0x26,
+  0xc8, 0x04, 0x64, 0x12, 0x00, 0x40, 0xf8, 0x97, 0x26, 0x12, 0x40, 0x60,
+  0x08, 0x02, 0x64, 0x0d, 0x00, 0x00, 0xd4, 0x0b, 0x82, 0x0f, 0x0c, 0xe6,
+  0x03, 0x00, 0x80, 0x4b, 0x00, 0x50, 0x07, 0x10, 0x35, 0x03, 0x24, 0x37,
+  0x67, 0x1d, 0xfe, 0x13, 0x00, 0xe0, 0x03, 0x00, 0x80, 0xa0, 0x03, 0xe7,
+  0x48, 0x88, 0x1d, 0x07, 0x10, 0x35, 0x03, 0x24, 0x37, 0xd8, 0xf7, 0x63,
+  0x17, 0x04, 0xe0, 0x01, 0x12, 0x00, 0x08, 0x00, 0x64, 0x8f, 0x80, 0x81,
+  0x46, 0xbc, 0x00, 0x63, 0x80, 0xd2, 0xd0, 0x40, 0x98, 0x83, 0x90, 0x91,
+  0x8f, 0x80, 0x81, 0xd0, 0x30, 0x94, 0x0c, 0x21, 0x98, 0x83, 0x8c, 0x91,
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+  0x16, 0x40, 0x20, 0xb0, 0x00, 0xc8, 0x04, 0x15, 0x64, 0xe5, 0xff, 0xff,
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+  0x80, 0x81, 0x92, 0x07, 0x40, 0xfd, 0xe3, 0x05, 0x90, 0x0f, 0x1c, 0xe5,
+  0x0b, 0x08, 0xe6, 0x03, 0x10, 0x80, 0x5a, 0x40, 0x20, 0x03, 0x10, 0x3d,
+  0x77, 0xe3, 0x7f, 0x48, 0x00, 0xc8, 0x04, 0x15, 0x64, 0xe5, 0xff, 0xff,
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+  0x08, 0x00, 0x99, 0x83, 0x51, 0x51, 0x0b, 0x0c, 0xe6, 0xe5, 0xff, 0xff,
+  0x77, 0x01, 0xfe, 0x0f, 0x0c, 0xe6, 0x1b, 0x28, 0xe5, 0x17, 0x10, 0x80,
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+  0x83, 0xa0, 0x06, 0xbd, 0x00, 0x00, 0xc4, 0xe7, 0x64, 0xd3, 0x5f, 0x60,
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+  0xbf, 0xa9, 0xf1, 0xb3, 0x3f, 0x90, 0x03, 0xaa, 0xf1, 0x83, 0x43, 0x90,
+  0x67, 0xc3, 0xfe, 0x19, 0x00, 0x00, 0x80, 0x40, 0x74, 0xdc, 0x8f, 0x62,
+  0x2b, 0x28, 0xe0, 0x3f, 0x00, 0xfd, 0x03, 0x40, 0xfd, 0xa3, 0x7f, 0x90,
+  0x93, 0x43, 0x90, 0x67, 0xc3, 0xfe, 0x07, 0xa9, 0xf1, 0xa3, 0x07, 0x90,
+  0xbf, 0xa9, 0xf1, 0xb3, 0x3f, 0x90, 0x03, 0xaa, 0xf1, 0x83, 0x43, 0x90,
+  0x67, 0xc3, 0xfe, 0x19, 0x00, 0x00, 0xc0, 0x40, 0x74, 0xdc, 0x8b, 0x62,
+  0x2b, 0x28, 0xe0, 0x3f, 0x00, 0xfd, 0x03, 0x40, 0xfd, 0xa3, 0x7f, 0x90,
+  0x93, 0x43, 0x90, 0x67, 0xc3, 0xfe, 0x07, 0xa9, 0xf1, 0xa3, 0x07, 0x90,
+  0xbf, 0xa9, 0xf1, 0xb3, 0x3f, 0x90, 0x03, 0xaa, 0xf1, 0x83, 0x43, 0x90,
+  0x67, 0xc3, 0xfe, 0x19, 0x00, 0x00, 0x40, 0x40, 0x74, 0xdc, 0x87, 0x62,
+  0x09, 0x00, 0x00, 0xc7, 0x50, 0xf9, 0x10, 0x00, 0x64, 0xc9, 0xf3, 0xff,
+  0x5c, 0x52, 0x72, 0x93, 0xc2, 0xfe, 0x12, 0x41, 0x24, 0x03, 0x79, 0xfe,
+  0x53, 0x87, 0xf1, 0x56, 0x41, 0x24, 0x77, 0x10, 0xf2, 0x10, 0x80, 0x64,
+  0x5b, 0x12, 0xf2, 0x6b, 0x12, 0xf2, 0x67, 0xc3, 0xfe, 0x93, 0xc2, 0xfe,
+  0x12, 0x41, 0x04, 0x03, 0x79, 0xfe, 0xff, 0x1b, 0xfe, 0x09, 0x00, 0x00,
+  0x53, 0x4c, 0xf4, 0x33, 0xc3, 0xfe, 0x1b, 0x10, 0xe6, 0x09, 0x00, 0x00,
+  0x44, 0x03, 0x81, 0x7d, 0x00, 0x00, 0x3c, 0x7c, 0xaf, 0x5e, 0x40, 0x20,
+  0x0e, 0x00, 0x60, 0x09, 0x00, 0x00, 0x64, 0x07, 0x81, 0x58, 0x00, 0x64,
+  0xb3, 0x03, 0x90, 0xa3, 0x1b, 0x90, 0x07, 0x00, 0xfd, 0x83, 0x47, 0xb0,
+  0x01, 0x00, 0xf0, 0x48, 0x04, 0x64, 0xc0, 0x00, 0x74, 0xc4, 0x87, 0x62,
+  0x82, 0x83, 0xe0, 0x00, 0xe0, 0x26, 0x1a, 0x40, 0x60, 0x88, 0x1b, 0xd8,
+  0x01, 0x00, 0xf0, 0x48, 0x01, 0x64, 0xc0, 0x00, 0x74, 0xe4, 0x83, 0x62,
+  0x48, 0x00, 0x64, 0xa3, 0x0b, 0x90, 0x00, 0x00, 0x74, 0x01, 0x00, 0xf0,
+  0x48, 0x00, 0x64, 0xcc, 0x83, 0x62, 0x40, 0x00, 0x64, 0xd0, 0xcf, 0x63,
+  0x03, 0x80, 0xe5, 0x20, 0x84, 0x1d, 0x10, 0x7a, 0x31, 0xb3, 0x23, 0x00,
+  0x4c, 0x0a, 0x2b, 0x3c, 0x02, 0xa7, 0x03, 0x33, 0x01, 0xd3, 0x50, 0xfb,
+  0x9b, 0x23, 0x40, 0x06, 0x40, 0x20, 0x22, 0x41, 0x20, 0xd6, 0x43, 0x20,
+  0x84, 0x14, 0x72, 0x87, 0x0d, 0x00, 0x4e, 0x4c, 0x00, 0xd3, 0x20, 0x00,
+  0xbb, 0xd3, 0xf2, 0xcc, 0x01, 0x64, 0xa3, 0x0f, 0xb0, 0x87, 0x23, 0x00,
+  0x47, 0x08, 0x90, 0x8f, 0x37, 0x00, 0x0c, 0x3d, 0x72, 0x03, 0xa3, 0x80,
+  0x8b, 0x4d, 0x00, 0xf8, 0x97, 0x62, 0xfa, 0x41, 0x20, 0x07, 0x84, 0xe5,
+  0x4e, 0x1d, 0x00, 0xcf, 0x44, 0x00, 0xcc, 0x00, 0xb6, 0x3a, 0x00, 0x60,
+  0x64, 0x00, 0x64, 0x4c, 0x8e, 0x40, 0xd0, 0x80, 0xba, 0x60, 0x40, 0x70,
+  0x0a, 0x40, 0x60, 0x47, 0x10, 0x00, 0x9b, 0x8d, 0xf2, 0x4c, 0x0d, 0x31,
+  0x18, 0x0c, 0xc8, 0xd0, 0x90, 0x1d, 0x4e, 0x41, 0x20, 0xd0, 0x90, 0x1d,
+  0x83, 0xbf, 0x7f, 0xd0, 0x80, 0x92, 0xe6, 0xff, 0x7f, 0x67, 0x00, 0x80,
+  0x9b, 0x05, 0x00, 0x47, 0x10, 0x00, 0x4c, 0x06, 0x5e, 0x9b, 0x05, 0x00,
+  0xc4, 0x00, 0x66, 0xf6, 0xbf, 0x7f, 0xc7, 0xbf, 0x7f, 0xca, 0x1f, 0x00,
+  0x8b, 0x44, 0x00, 0x8c, 0x00, 0xb6, 0x4e, 0x00, 0x60, 0x50, 0x00, 0x64,
+  0x08, 0x89, 0x40, 0x90, 0x80, 0xba, 0x32, 0x40, 0x60, 0x10, 0x10, 0x5a,
+  0xc3, 0x10, 0x90, 0xcf, 0x88, 0xf2, 0xc8, 0x0f, 0x31, 0x20, 0x08, 0xc8,
+  0x3e, 0x42, 0x20, 0xa2, 0x40, 0x20, 0xca, 0x43, 0x20, 0x3e, 0x42, 0x20,
+  0xa2, 0x40, 0x20, 0x37, 0xbf, 0x7f, 0x10, 0x08, 0xf0, 0xc0, 0x10, 0xd8,
+  0xd7, 0xbf, 0x7f, 0x90, 0x80, 0x92, 0xd2, 0xff, 0x7f, 0xc0, 0x00, 0xe4,
+  0x03, 0x10, 0x00, 0xcf, 0x04, 0x00, 0x13, 0xf0, 0x8f, 0x08, 0x05, 0x5e,
+  0xc4, 0x08, 0x78, 0x84, 0x00, 0x66, 0xf6, 0xbf, 0x7f, 0xaf, 0xbf, 0x7f,
+  0x00, 0x7c, 0x31, 0x00, 0xfc, 0xa1, 0x00, 0x3c, 0x23, 0x03, 0x18, 0xe5,
+  0x18, 0x84, 0x1d, 0x09, 0x00, 0x00, 0x00, 0x9c, 0x52, 0x96, 0x40, 0x20,
+  0x00, 0x00, 0x66, 0x16, 0x00, 0x60, 0x4a, 0x41, 0x20, 0x80, 0x9d, 0x1d,
+  0xd0, 0x93, 0x62, 0x07, 0x1c, 0xe5, 0x08, 0x00, 0x64, 0x00, 0x00, 0x74,
+  0xc0, 0x93, 0x62, 0xfd, 0xff, 0xff, 0x3c, 0xfc, 0x87, 0x12, 0x40, 0x60,
+  0x44, 0x00, 0x64, 0x09, 0x00, 0x00, 0x84, 0x07, 0x7f, 0x09, 0x00, 0x00,
+  0x08, 0x9c, 0x52, 0x84, 0x00, 0x66, 0xc2, 0xbf, 0x7f, 0x4a, 0x41, 0x20,
+  0x80, 0x9d, 0x1d, 0xcc, 0xfb, 0x63, 0xbf, 0xbf, 0x7f, 0x03, 0x00, 0xe0,
+  0xcc, 0xfb, 0x63, 0x03, 0x60, 0x20, 0x07, 0x04, 0xe0, 0x37, 0x00, 0xfe,
+  0x9f, 0x00, 0xfe, 0x03, 0x00, 0xe0, 0xc4, 0x87, 0x62, 0x40, 0x80, 0x1d,
+  0x07, 0x04, 0xe0, 0x03, 0x10, 0xe5, 0x14, 0x7c, 0x27, 0x58, 0x7c, 0x27,
+  0x03, 0xd4, 0xfa, 0x47, 0xd8, 0xfa, 0x03, 0xd4, 0xf2, 0x47, 0xd8, 0xf2,
+  0xdc, 0x83, 0x62, 0x47, 0xd4, 0xfa, 0x47, 0xd4, 0xf2, 0x57, 0xd9, 0xfa,
+  0x03, 0xd4, 0xfa, 0x03, 0xd4, 0xf2, 0x07, 0x14, 0xe5, 0x4b, 0x24, 0xfe,
+  0x50, 0x04, 0xc8, 0x8a, 0x4c, 0x20, 0x8b, 0x04, 0x00, 0x52, 0x40, 0x20,
+  0x04, 0x88, 0x3e, 0x8c, 0x80, 0x25, 0x00, 0x8c, 0x40, 0x10, 0x08, 0xca,
+  0x00, 0x50, 0x1e, 0x00, 0x3c, 0x23, 0x04, 0x00, 0x64, 0xb0, 0xc7, 0xc9,
+  0x47, 0x00, 0x80, 0xa0, 0xc7, 0xc9, 0x07, 0x00, 0xfe, 0x0e, 0x40, 0x20,
+  0x48, 0x04, 0x5e, 0xc4, 0x08, 0x78, 0x84, 0x00, 0x66, 0xf6, 0xbf, 0x7f,
+  0x00, 0x3c, 0x23, 0x8c, 0x00, 0x64, 0x01, 0x00, 0x00, 0xcf, 0x01, 0xfe,
+  0x01, 0x04, 0x00, 0x8c, 0x05, 0x64, 0x01, 0x00, 0x00, 0x6f, 0x01, 0xfe,
+  0x4b, 0xc3, 0xfe, 0x63, 0xc3, 0xfe, 0x67, 0xc3, 0xfe, 0x8f, 0x03, 0x80,
+  0x83, 0x13, 0x80, 0xbb, 0x23, 0x00, 0xc0, 0x00, 0x86, 0x02, 0xbc, 0x9f,
+  0x00, 0x3c, 0x23, 0xa0, 0xcf, 0x7b, 0x67, 0xc3, 0xfe, 0x63, 0xc3, 0xfe,
+  0xa7, 0x1f, 0xfe, 0x10, 0x00, 0x64, 0xc5, 0xf3, 0xff, 0xf4, 0xd3, 0x72,
+  0xcf, 0x1f, 0xfe
+};
+
+#define PMC_DTCM_LOG_SIZE 256
+
+const unsigned char pmcdata[] = {
+  0x3c, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x40, 0x01, 0x00, 0x00, 0x40, 0x0a, 0x00, 0x00, 0xcc, 0x04, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x44, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42,
+  0x43, 0x44, 0x45, 0x46, 0x00, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
+  0x37, 0x38, 0x39, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x00, 0x28, 0x6e,
+  0x75, 0x6c, 0x6c, 0x29, 0x00, 0x25, 0x30, 0x34, 0x75, 0x3a, 0x20, 0x00,
+  0x73, 0x63, 0x72, 0x61, 0x74, 0x63, 0x68, 0x3a, 0x20, 0x30, 0x78, 0x25,
+  0x30, 0x38, 0x78, 0x0a, 0x00, 0x50, 0x4d, 0x43, 0x5f, 0x56, 0x45, 0x52,
+  0x3a, 0x25, 0x64, 0x2e, 0x25, 0x64, 0x2e, 0x25, 0x64, 0x0a, 0x00, 0x24,
+  0x43, 0x68, 0x61, 0x6e, 0x67, 0x65, 0x3a, 0x20, 0x32, 0x38, 0x34, 0x30,
+  0x32, 0x37, 0x20, 0x24, 0x00, 0x32, 0x30, 0x30, 0x36, 0x32, 0x32, 0x5f,
+  0x31, 0x31, 0x33, 0x30, 0x00, 0x54, 0x53, 0x3a, 0x25, 0x73, 0x0a, 0x00,
+  0x43, 0x48, 0x49, 0x44, 0x3a, 0x25, 0x78, 0x0a, 0x00, 0x43, 0x52, 0x45,
+  0x56, 0x3a, 0x25, 0x78, 0x0a, 0x00, 0x50, 0x41, 0x52, 0x54, 0x49, 0x44,
+  0x3a, 0x25, 0x78, 0x20, 0x43, 0x46, 0x41, 0x4d, 0x3a, 0x25, 0x78, 0x20,
+  0x73, 0x6b, 0x69, 0x70, 0x70, 0x65, 0x64, 0x20, 0x63, 0x68, 0x69, 0x70,
+  0x20, 0x69, 0x64, 0x20, 0x76, 0x61, 0x6c, 0x69, 0x64, 0x61, 0x74, 0x69,
+  0x6f, 0x6e, 0x0a, 0x00, 0x52, 0x4f, 0x20, 0x53, 0x56, 0x54, 0x20, 0x25,
+  0x64, 0x20, 0x48, 0x56, 0x54, 0x20, 0x25, 0x64, 0x20, 0x4c, 0x56, 0x54,
+  0x20, 0x25, 0x64, 0x0a, 0x00, 0x48, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x43,
+  0x6c, 0x6f, 0x73, 0x65, 0x41, 0x56, 0x53, 0x3a, 0x20, 0x6f, 0x76, 0x65,
+  0x72, 0x77, 0x72, 0x69, 0x74, 0x69, 0x6e, 0x67, 0x20, 0x70, 0x72, 0x65,
+  0x76, 0x69, 0x6f, 0x75, 0x73, 0x20, 0x43, 0x6c, 0x6f, 0x73, 0x65, 0x41,
+  0x56, 0x53, 0x20, 0x6c, 0x6f, 0x67, 0x0a, 0x00, 0x48, 0x61, 0x6e, 0x64,
+  0x6c, 0x65, 0x43, 0x6c, 0x6f, 0x73, 0x65, 0x41, 0x56, 0x53, 0x3a, 0x20,
+  0x69, 0x73, 0x6c, 0x61, 0x6e, 0x64, 0x20, 0x25, 0x64, 0x20, 0x73, 0x6c,
+  0x6f, 0x77, 0x20, 0x25, 0x64, 0x20, 0x66, 0x61, 0x73, 0x74, 0x20, 0x25,
+  0x64, 0x20, 0x6d, 0x61, 0x78, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x69, 0x6e,
+  0x20, 0x25, 0x64, 0x0a, 0x00, 0x48, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x43,
+  0x6c, 0x6f, 0x73, 0x65, 0x41, 0x56, 0x53, 0x3a, 0x20, 0x66, 0x69, 0x6e,
+  0x69, 0x73, 0x68, 0x65, 0x64, 0x20, 0x77, 0x69, 0x74, 0x68, 0x20, 0x65,
+  0x72, 0x72, 0x6f, 0x72, 0x43, 0x6f, 0x64, 0x65, 0x20, 0x25, 0x75, 0x0a,
+  0x00, 0x41, 0x56, 0x53, 0x20, 0x44, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65,
+  0x64, 0x0a, 0x00, 0x44, 0x41, 0x43, 0x3a, 0x20, 0x25, 0x64, 0x0a, 0x00,
+  0x4c, 0x56, 0x54, 0x00, 0x48, 0x56, 0x54, 0x00, 0x64, 0x65, 0x76, 0x20,
+  0x61, 0x64, 0x64, 0x72, 0x20, 0x30, 0x78, 0x25, 0x78, 0x20, 0x52, 0x4f,
+  0x20, 0x74, 0x79, 0x70, 0x65, 0x20, 0x53, 0x56, 0x54, 0x20, 0x76, 0x61,
+  0x6c, 0x75, 0x65, 0x20, 0x25, 0x75, 0x20, 0x52, 0x4f, 0x20, 0x74, 0x79,
+  0x70, 0x65, 0x20, 0x25, 0x73, 0x20, 0x76, 0x61, 0x6c, 0x75, 0x65, 0x20,
+  0x25, 0x75, 0x0a, 0x00, 0x63, 0x75, 0x72, 0x5f, 0x64, 0x61, 0x63, 0x20,
+  0x25, 0x75, 0x20, 0x63, 0x75, 0x72, 0x56, 0x20, 0x25, 0x75, 0x20, 0x63,
+  0x75, 0x72, 0x54, 0x65, 0x6d, 0x70, 0x20, 0x25, 0x75, 0x20, 0x64, 0x65,
+  0x6c, 0x74, 0x61, 0x20, 0x25, 0x64, 0x20, 0x6e, 0x65, 0x77, 0x5f, 0x64,
+  0x61, 0x63, 0x20, 0x25, 0x75, 0x0a, 0x00, 0x4d, 0x56, 0x41, 0x44, 0x43,
+  0x31, 0x20, 0x4d, 0x65, 0x61, 0x73, 0x75, 0x72, 0x65, 0x64, 0x20, 0x25,
+  0x75, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x75, 0x6c, 0x61, 0x74, 0x65, 0x64,
+  0x20, 0x25, 0x75, 0x0a, 0x00, 0x4d, 0x65, 0x61, 0x73, 0x75, 0x72, 0x65,
+  0x64, 0x20, 0x4d, 0x56, 0x41, 0x44, 0x43, 0x32, 0x20, 0x25, 0x75, 0x0a,
+  0x00, 0x4d, 0x56, 0x20, 0x44, 0x65, 0x6c, 0x74, 0x61, 0x20, 0x66, 0x6f,
+  0x72, 0x20, 0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x20, 0x64, 0x65, 0x6c,
+  0x74, 0x61, 0x20, 0x25, 0x75, 0x20, 0x4d, 0x56, 0x0a, 0x00, 0x44, 0x75,
+  0x6d, 0x70, 0x20, 0x61, 0x6c, 0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73, 0x20,
+  0x6f, 0x6e, 0x20, 0x76, 0x68, 0x69, 0x67, 0x68, 0x5f, 0x6d, 0x76, 0x20,
+  0x25, 0x64, 0x0a, 0x00, 0x44, 0x75, 0x6d, 0x70, 0x20, 0x61, 0x6c, 0x6c,
+  0x20, 0x52, 0x4f, 0x27, 0x73, 0x20, 0x6f, 0x6e, 0x20, 0x76, 0x6c, 0x6f,
+  0x77, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x52, 0x4f, 0x5b,
+  0x25, 0x64, 0x5d, 0x20, 0x74, 0x61, 0x72, 0x67, 0x65, 0x74, 0x5f, 0x72,
+  0x6f, 0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f, 0x77, 0x5f, 0x72, 0x6f, 0x20,
+  0x25, 0x64, 0x20, 0x73, 0x6c, 0x6f, 0x70, 0x65, 0x20, 0x25, 0x64, 0x20,
+  0x76, 0x6c, 0x6f, 0x77, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x64,
+  0x61, 0x63, 0x5f, 0x6c, 0x6f, 0x77, 0x20, 0x25, 0x64, 0x20, 0x76, 0x68,
+  0x69, 0x67, 0x68, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x64, 0x61,
+  0x63, 0x5f, 0x68, 0x69, 0x67, 0x68, 0x20, 0x25, 0x64, 0x20, 0x76, 0x6f,
+  0x6c, 0x74, 0x61, 0x67, 0x65, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x0a,
+  0x00, 0x52, 0x4f, 0x5b, 0x25, 0x64, 0x5d, 0x20, 0x74, 0x61, 0x72, 0x67,
+  0x65, 0x74, 0x5f, 0x72, 0x6f, 0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f, 0x77,
+  0x5f, 0x72, 0x6f, 0x20, 0x25, 0x64, 0x20, 0x76, 0x6c, 0x6f, 0x77, 0x5f,
+  0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x6c, 0x6f,
+  0x77, 0x20, 0x25, 0x64, 0x20, 0x68, 0x69, 0x67, 0x68, 0x5f, 0x72, 0x6f,
+  0x20, 0x25, 0x64, 0x20, 0x76, 0x68, 0x69, 0x67, 0x68, 0x5f, 0x6d, 0x76,
+  0x20, 0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x68, 0x69, 0x67, 0x68,
+  0x20, 0x25, 0x64, 0x0a, 0x00, 0x61, 0x76, 0x73, 0x5f, 0x64, 0x61, 0x63,
+  0x20, 0x25, 0x64, 0x20, 0x70, 0x72, 0x65, 0x64, 0x69, 0x63, 0x74, 0x5f,
+  0x6d, 0x76, 0x20, 0x25, 0x75, 0x20, 0x61, 0x76, 0x73, 0x5f, 0x6d, 0x76,
+  0x20, 0x25, 0x64, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x5f, 0x6d, 0x61, 0x72,
+  0x67, 0x69, 0x6e, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x63, 0x61,
+  0x6c, 0x63, 0x5f, 0x73, 0x77, 0x72, 0x65, 0x67, 0x5f, 0x6d, 0x76, 0x20,
+  0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x68, 0x69, 0x67, 0x68, 0x20,
+  0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x6c, 0x6f, 0x77, 0x20, 0x25,
+  0x64, 0x0a, 0x00, 0x41, 0x56, 0x53, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65,
+  0x64, 0x20, 0x6f, 0x6e, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x63, 0x6f, 0x64,
+  0x65, 0x20, 0x25, 0x64, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x5f, 0x73, 0x77,
+  0x72, 0x65, 0x67, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x74, 0x61,
+  0x72, 0x67, 0x65, 0x74, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x63,
+  0x61, 0x6c, 0x63, 0x5f, 0x73, 0x77, 0x72, 0x65, 0x67, 0x5f, 0x64, 0x61,
+  0x63, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x41, 0x56, 0x53, 0x20, 0x69, 0x73,
+  0x6c, 0x61, 0x6e, 0x64, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x61, 0x72, 0x67,
+  0x69, 0x6e, 0x5f, 0x6d, 0x76, 0x5f, 0x73, 0x6c, 0x6f, 0x77, 0x20, 0x25,
+  0x64, 0x20, 0x6d, 0x61, 0x72, 0x67, 0x69, 0x6e, 0x5f, 0x6d, 0x76, 0x5f,
+  0x66, 0x61, 0x73, 0x74, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x61, 0x78, 0x69,
+  0x6d, 0x75, 0x6d, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x69,
+  0x6e, 0x69, 0x6d, 0x75, 0x6d, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x0a,
+  0x00, 0x53, 0x65, 0x74, 0x74, 0x69, 0x6e, 0x67, 0x20, 0x54, 0x68, 0x72,
+  0x65, 0x73, 0x68, 0x6f, 0x6c, 0x64, 0x73, 0x20, 0x66, 0x6f, 0x72, 0x20,
+  0x25, 0x64, 0x20, 0x68, 0x69, 0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f, 0x20,
+  0x25, 0x64, 0x0a, 0x00, 0x53, 0x65, 0x74, 0x74, 0x69, 0x6e, 0x67, 0x20,
+  0x52, 0x34, 0x38, 0x5f, 0x25, 0x64, 0x20, 0x54, 0x68, 0x72, 0x65, 0x73,
+  0x68, 0x6f, 0x6c, 0x64, 0x73, 0x20, 0x68, 0x69, 0x20, 0x25, 0x64, 0x20,
+  0x6c, 0x6f, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x44, 0x75, 0x6d, 0x70, 0x20,
+  0x61, 0x6c, 0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73, 0x20, 0x6f, 0x6e, 0x20,
+  0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x0a, 0x00, 0x40, 0x40, 0x40,
+  0x46, 0x41, 0x49, 0x4c, 0x45, 0x44, 0x00, 0x40, 0x40, 0x40, 0x50, 0x41,
+  0x53, 0x53, 0x45, 0x44, 0x00, 0x00, 0x00, 0x00, 0xbf, 0xd0, 0xc0, 0x54,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0xff, 0x00, 0x00, 0x00, 0x50, 0x0a, 0x00, 0x00
+};
+#endif //PMC_ROMDATA_63178_H
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_firmware_6756.h b/arch/arm/mach-bcmbca/pmc/pmc_firmware_6756.h
new file mode 100644
index 0000000000..b87c14f57d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_firmware_6756.h
@@ -0,0 +1,1388 @@
+/*
+ * * <:copyright-BRCM:2017:DUAL/GPL:standard
+ * * 
+ * *    Copyright (c) 2017 Broadcom 
+ * *    All Rights Reserved
+ * * 
+ * * This program is free software; you can redistribute it and/or modify
+ * * it under the terms of the GNU General Public License, version 2, as published by
+ * * the Free Software Foundation (the "GPL").
+ * * 
+ * * This program is distributed in the hope that it will be useful,
+ * * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * * GNU General Public License for more details.
+ * * 
+ * * 
+ * * A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+ * * writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * * Boston, MA 02111-1307, USA.
+ * * 
+ * * :>
+ * */
+
+#ifndef PMC_ROMDATA_6756_H
+#define PMC_ROMDATA_6756_H
+#define PMC_VER_IMPL 3
+#define PMC_VER_MAJOR 2
+#define PMC_VER_MINOR 2
+#define PMC_VER_CHANGELIST "$Change: 284027 $"
+const unsigned char pmcappdata[] = {
+  0x01, 0x00, 0x00, 0xbf, 0x03, 0xfe, 0x67, 0xc3, 0xfe, 0x4b, 0xc3, 0xfe,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x08, 0xe6, 0x05,
+  0x00, 0x00, 0x00, 0x8c, 0x52, 0x04, 0x00, 0x66, 0x5a, 0x00, 0x60, 0x09,
+  0x00, 0x00, 0x00, 0x92, 0x55, 0x05, 0x00, 0x00, 0x58, 0x7a, 0x64, 0x4c,
+  0x00, 0x72, 0x05, 0x00, 0x00, 0x00, 0x8e, 0x55, 0x44, 0x00, 0x64, 0x09,
+  0x00, 0x00, 0x44, 0x06, 0x81, 0x86, 0x41, 0x20, 0x39, 0x00, 0x00, 0xc4,
+  0xdb, 0x62, 0x05, 0x00, 0x00, 0x00, 0x8e, 0x55, 0x86, 0x41, 0x20, 0x39,
+  0x00, 0x00, 0xc8, 0xd7, 0x62, 0x48, 0x00, 0x64, 0x05, 0x00, 0x00, 0x84,
+  0x09, 0x7f, 0x07, 0x0c, 0xe6, 0x03, 0x00, 0x80, 0x00, 0x3c, 0x23, 0x0c,
+  0x88, 0x62, 0x38, 0x40, 0x55, 0xba, 0x4f, 0x00, 0x04, 0x00, 0x64, 0x4c,
+  0x04, 0x72, 0xcd, 0xab, 0x89, 0xc8, 0x7b, 0x64, 0x45, 0x23, 0x01, 0xcc,
+  0x59, 0x64, 0x05, 0x00, 0x00, 0x00, 0x8f, 0x64, 0x86, 0x43, 0x20, 0xec,
+  0x83, 0x62, 0xbb, 0x63, 0x00, 0x80, 0x03, 0xe6, 0x04, 0x00, 0x64, 0x4c,
+  0x04, 0x48, 0xc3, 0x07, 0xf6, 0x3b, 0x00, 0xf2, 0x87, 0xc2, 0xfe, 0x46,
+  0x50, 0x07, 0x43, 0x78, 0xfe, 0x87, 0x04, 0xfe, 0x47, 0xc0, 0xf2, 0x44,
+  0x0c, 0x31, 0x10, 0x04, 0xca, 0x08, 0x08, 0xe8, 0x00, 0x3c, 0x23, 0x03,
+  0xc0, 0xf1, 0x02, 0x68, 0x00, 0x03, 0x40, 0xf2, 0x03, 0xc7, 0xf1, 0x02,
+  0xfc, 0x00, 0x73, 0x40, 0xf2, 0x00, 0x3c, 0x23, 0x08, 0x00, 0x74, 0xc4,
+  0x3f, 0x64, 0x50, 0x08, 0x1d, 0x18, 0x00, 0x64, 0x44, 0x37, 0x64, 0x84,
+  0x09, 0x1e, 0x9b, 0x05, 0x00, 0x47, 0x44, 0x00, 0xec, 0xc7, 0x73, 0x84,
+  0x03, 0x64, 0x0b, 0x07, 0xf2, 0x57, 0xc3, 0xfe, 0x9f, 0x11, 0xf2, 0xc7,
+  0x11, 0xf2, 0xef, 0x11, 0xf2, 0x17, 0x12, 0xf2, 0x3f, 0x12, 0xf2, 0x67,
+  0x12, 0xf2, 0xe7, 0x51, 0xf2, 0xff, 0x50, 0xf2, 0x87, 0x13, 0xf2, 0xcf,
+  0x51, 0xf2, 0x44, 0x00, 0x64, 0x73, 0x06, 0xf2, 0x44, 0x00, 0x64, 0xf3,
+  0x06, 0xf2, 0x8d, 0xd6, 0x92, 0x84, 0x28, 0x64, 0xc3, 0x46, 0xf2, 0xa7,
+  0x01, 0xfe, 0x35, 0x0c, 0x00, 0x04, 0xbf, 0x64, 0xb3, 0x06, 0xf2, 0x35,
+  0x0c, 0x00, 0x04, 0xa7, 0x64, 0xbb, 0x06, 0xf2, 0x35, 0x0c, 0x00, 0x84,
+  0x9f, 0x64, 0xd3, 0x06, 0xf2, 0x35, 0x0c, 0x00, 0x04, 0xb3, 0x64, 0xc3,
+  0x06, 0xf2, 0x35, 0x0c, 0x00, 0x44, 0xa6, 0x64, 0xdb, 0x06, 0xf2, 0x01,
+  0x0c, 0x00, 0x04, 0xf2, 0x64, 0xcb, 0x06, 0xf2, 0x35, 0x0c, 0x00, 0x44,
+  0x85, 0x64, 0xe3, 0x06, 0xf2, 0x67, 0xc3, 0xfe, 0xc4, 0xff, 0x64, 0x5b,
+  0x06, 0xf2, 0x67, 0xc3, 0xfe, 0x87, 0xc2, 0xfe, 0x05, 0x00, 0x00, 0x46,
+  0x40, 0x04, 0x43, 0x78, 0xfe, 0x84, 0x00, 0x64, 0x05, 0x10, 0x00, 0x44,
+  0x86, 0x80, 0x01, 0xad, 0xde, 0x44, 0x00, 0x64, 0x4b, 0x04, 0x00, 0x4f,
+  0x08, 0x00, 0x53, 0x0c, 0x00, 0x57, 0x10, 0x00, 0x5b, 0x14, 0x00, 0x5f,
+  0x18, 0x00, 0x63, 0x1c, 0x00, 0x67, 0x20, 0x00, 0x6b, 0x24, 0x00, 0x6f,
+  0x28, 0x00, 0x73, 0x2c, 0x00, 0x77, 0x30, 0x00, 0x7b, 0x34, 0x00, 0x7f,
+  0x38, 0x00, 0x40, 0x60, 0x26, 0x40, 0xe0, 0x26, 0x00, 0x00, 0x23, 0x01,
+  0x0c, 0x00, 0x88, 0x08, 0x64, 0x39, 0x0c, 0x00, 0x04, 0x80, 0x64, 0x1b,
+  0x0b, 0xf2, 0x23, 0x07, 0xf2, 0x08, 0x53, 0x64, 0x05, 0x00, 0x00, 0x04,
+  0x80, 0x64, 0x03, 0x48, 0xf2, 0x0b, 0x44, 0xf2, 0xfd, 0xff, 0xff, 0x08,
+  0xf9, 0x64, 0xfd, 0x1f, 0x00, 0x04, 0xf8, 0x64, 0x13, 0x48, 0xf2, 0x1b,
+  0x44, 0xf2, 0xfd, 0xff, 0xff, 0x08, 0xfb, 0x64, 0x05, 0x00, 0x00, 0x04,
+  0x80, 0x64, 0x23, 0x48, 0xf2, 0x2b, 0x44, 0xf2, 0x08, 0x03, 0x64, 0x04,
+  0x38, 0x64, 0x33, 0x48, 0xf2, 0x3b, 0x44, 0xf2, 0x05, 0x00, 0x00, 0x08,
+  0x8b, 0x64, 0x0d, 0x00, 0x00, 0x04, 0xc0, 0x64, 0x43, 0x48, 0xf2, 0x4b,
+  0x44, 0xf2, 0xfd, 0xff, 0xff, 0x08, 0xfb, 0x64, 0xfd, 0x1f, 0x00, 0x04,
+  0xf8, 0x64, 0x53, 0x48, 0xf2, 0x5b, 0x44, 0xf2, 0x05, 0x10, 0x00, 0x08,
+  0x03, 0x64, 0x05, 0x10, 0x00, 0x04, 0x78, 0x64, 0x63, 0x48, 0xf2, 0x6b,
+  0x44, 0xf2, 0x08, 0x41, 0x64, 0x04, 0x48, 0x64, 0x73, 0x48, 0xf2, 0x7b,
+  0x44, 0xf2, 0xe7, 0x1c, 0xfe, 0x0f, 0x20, 0xe5, 0x00, 0x41, 0x64, 0xd8,
+  0xd7, 0x63, 0x00, 0x00, 0x66, 0x8e, 0x00, 0x60, 0x14, 0x00, 0x64, 0x90,
+  0x14, 0xc8, 0x18, 0x44, 0x64, 0x82, 0x41, 0x20, 0xfc, 0xd3, 0x63, 0x22,
+  0x40, 0x20, 0x83, 0x11, 0x00, 0xf0, 0xd3, 0x63, 0xa3, 0x03, 0x90, 0x83,
+  0x21, 0x00, 0xe4, 0xd3, 0x63, 0x87, 0x23, 0x80, 0x0a, 0x40, 0x20, 0x02,
+  0x42, 0x20, 0xdf, 0x05, 0x00, 0xd8, 0x97, 0x62, 0x6c, 0x9d, 0x3a, 0x9b,
+  0x31, 0x00, 0xc6, 0xff, 0x7f, 0xd4, 0x00, 0x64, 0x70, 0x14, 0xc8, 0x18,
+  0x44, 0x74, 0x82, 0x41, 0x20, 0xf0, 0xcf, 0x63, 0x22, 0x40, 0x20, 0x83,
+  0x11, 0x00, 0xe4, 0xcf, 0x63, 0x0a, 0x40, 0x20, 0x03, 0x02, 0x50, 0xf4,
+  0x93, 0x62, 0xdf, 0x05, 0x00, 0x6c, 0x1d, 0x3a, 0x9b, 0x21, 0x00, 0xd6,
+  0xbf, 0x7f, 0x00, 0x42, 0x64, 0xc0, 0xcf, 0x63, 0x22, 0x40, 0x20, 0x00,
+  0x43, 0x64, 0xf4, 0xcb, 0x63, 0x1e, 0x40, 0x20, 0x01, 0x0c, 0x00, 0xc0,
+  0x32, 0x64, 0x05, 0x00, 0x00, 0x14, 0x88, 0x55, 0x10, 0x00, 0xc8, 0xd0,
+  0xd3, 0x63, 0xd4, 0x87, 0x62, 0x01, 0x0c, 0x00, 0x00, 0x08, 0x64, 0x20,
+  0x00, 0xc8, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0xd0, 0xc3, 0x63, 0x00,
+  0x00, 0x64, 0x18, 0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xcc, 0xbb, 0x62, 0x00,
+  0x00, 0x64, 0x28, 0x00, 0xc8, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0xfd,
+  0xf3, 0xff, 0xc4, 0xb7, 0x62, 0x4a, 0x41, 0x20, 0x00, 0x9e, 0x1d, 0x31,
+  0x00, 0x00, 0xe0, 0x9b, 0x63, 0x03, 0x00, 0xe0, 0x00, 0x00, 0x64, 0x18,
+  0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xd8, 0xaf, 0x62, 0x00, 0x00, 0x64, 0x98,
+  0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xe8, 0xab, 0x62, 0x00, 0x00, 0x64, 0x18,
+  0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xf8, 0xa7, 0x62, 0x0f, 0xc2, 0xf1, 0xd2,
+  0x68, 0x00, 0x23, 0x50, 0xf2, 0x00, 0x00, 0x64, 0x10, 0x00, 0xc8, 0xe3,
+  0x02, 0xf2, 0x35, 0x0c, 0x00, 0x00, 0xcb, 0x64, 0x10, 0x00, 0xc8, 0xcb,
+  0x02, 0xf2, 0x67, 0xc3, 0xfe, 0x07, 0x04, 0xe0, 0x40, 0x00, 0x65, 0x5b,
+  0x02, 0xf2, 0x01, 0x00, 0x82, 0x07, 0x00, 0x00, 0x33, 0x06, 0xf2, 0x48,
+  0x00, 0x64, 0xe3, 0x09, 0xf2, 0x67, 0xc3, 0xfe, 0xa3, 0xbf, 0x7f, 0x88,
+  0x08, 0x31, 0x18, 0x08, 0xca, 0x48, 0x10, 0x5a, 0x10, 0x08, 0x7a, 0x00,
+  0x3c, 0x23, 0x0c, 0x00, 0x64, 0x4c, 0xcc, 0x1e, 0x84, 0x08, 0x31, 0x10,
+  0x04, 0xca, 0x10, 0x0c, 0x7a, 0x00, 0x3c, 0x23, 0x05, 0x10, 0x00, 0x18,
+  0x28, 0x64, 0x70, 0x18, 0xc8, 0x83, 0x41, 0x90, 0x93, 0x45, 0x90, 0xa3,
+  0x79, 0x90, 0xb3, 0x7d, 0x90, 0x9f, 0xb7, 0xf1, 0xdc, 0xed, 0xa3, 0x83,
+  0x1d, 0x90, 0x1f, 0x8c, 0xf1, 0x93, 0x1d, 0x90, 0x9f, 0x8c, 0xf1, 0xa3,
+  0x1d, 0x90, 0x1f, 0xe0, 0xf1, 0xb3, 0x1d, 0x90, 0x18, 0x00, 0x64, 0x10,
+  0x18, 0xc8, 0xc0, 0xdb, 0x1f, 0x31, 0x00, 0x00, 0xf7, 0x0e, 0xfe, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x80, 0xa2, 0x11, 0x10, 0x00, 0x04, 0x01, 0x80, 0x11, 0x10, 0x00,
+  0x04, 0x06, 0x64, 0x4b, 0x20, 0x80, 0xbc, 0x7c, 0xb3, 0xfa, 0xbf, 0x7f,
+  0x00, 0x3c, 0x23, 0x04, 0xfa, 0x64, 0x00, 0x44, 0x24, 0xaf, 0x1f, 0xfe,
+  0x13, 0x00, 0xe0, 0x01, 0x12, 0x00, 0x10, 0x00, 0x64, 0x0f, 0x01, 0x84,
+  0xa0, 0x03, 0xe7, 0xbc, 0x7c, 0xb3, 0x0d, 0x00, 0x00, 0xd7, 0xa3, 0xf8,
+  0xff, 0x28, 0x3a, 0x8f, 0x0c, 0x00, 0xcb, 0x88, 0xf9, 0x8f, 0x23, 0x80,
+  0xc0, 0x43, 0x24, 0xbc, 0x08, 0x27, 0x03, 0xbc, 0xf2, 0xd3, 0x40, 0xd0,
+  0xa3, 0x0f, 0x90, 0xbf, 0x23, 0x80, 0xc0, 0x3f, 0xa4, 0xa3, 0x03, 0x90,
+  0x8f, 0x23, 0x80, 0xcf, 0x04, 0xda, 0xa3, 0x0f, 0x90, 0x87, 0x23, 0x80,
+  0x48, 0x00, 0xa2, 0xa3, 0x0b, 0x90, 0xbf, 0x23, 0x80, 0x03, 0xbd, 0x94,
+  0xa0, 0x03, 0xe7, 0x03, 0x81, 0x84, 0xa3, 0x03, 0x90, 0x8f, 0x23, 0x80,
+  0xf0, 0xb4, 0x26, 0xf2, 0xff, 0x7f, 0x93, 0x23, 0x80, 0xc8, 0x04, 0x64,
+  0x34, 0x15, 0x26, 0x16, 0x00, 0x40, 0x87, 0x23, 0x80, 0x78, 0x94, 0x26,
+  0x1a, 0x40, 0x60, 0x08, 0x02, 0x64, 0x0d, 0x00, 0x00, 0xd4, 0x0b, 0x82,
+  0x00, 0x00, 0x64, 0x17, 0x04, 0xe0, 0x01, 0x12, 0x00, 0x00, 0x4b, 0x55,
+  0xf7, 0xbf, 0x7f, 0x0b, 0x08, 0xe6, 0x01, 0x12, 0x00, 0x18, 0x00, 0x64,
+  0x93, 0x01, 0x84, 0xbf, 0x0c, 0x00, 0x0d, 0x00, 0x00, 0xd7, 0xa3, 0xf8,
+  0xbc, 0x7c, 0xb3, 0x93, 0x8d, 0x94, 0xcb, 0x8b, 0xf9, 0x0f, 0x29, 0x3a,
+  0xc0, 0x40, 0x24, 0x90, 0x08, 0x27, 0x0f, 0x90, 0xf2, 0xfd, 0x0f, 0x00,
+  0xc2, 0xbc, 0x1f, 0x0f, 0x04, 0xda, 0x04, 0x04, 0xa2, 0x83, 0x85, 0x94,
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+  0xe5, 0xff, 0xff, 0xe8, 0xff, 0x63, 0x41, 0xff, 0xff, 0x44, 0x18, 0x64,
+  0x08, 0x44, 0x24, 0xb9, 0x76, 0x02, 0x83, 0xa0, 0x06, 0x04, 0x19, 0x64,
+  0x2f, 0x61, 0x60, 0xa3, 0x01, 0x90, 0xd3, 0xbf, 0x7f, 0x0b, 0x18, 0xe5,
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+  0x16, 0x40, 0x20, 0xb0, 0x00, 0xc8, 0x04, 0x15, 0x64, 0xe5, 0xff, 0xff,
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+  0x37, 0xd2, 0x7f, 0x82, 0x41, 0x20, 0x3f, 0xec, 0x7f, 0x01, 0x05, 0x00,
+  0xc0, 0x01, 0x64, 0xaf, 0xbf, 0x7f, 0x07, 0x10, 0xe5, 0x16, 0x40, 0x20,
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+  0x0b, 0x80, 0x11, 0x8f, 0x10, 0x80, 0xc0, 0x00, 0x86, 0x03, 0x00, 0xfd,
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+  0x14, 0x00, 0x72, 0x9b, 0x29, 0x00, 0x04, 0x00, 0x64, 0x28, 0x04, 0xc8,
+  0xa3, 0x03, 0x90, 0xc9, 0xf3, 0xff, 0xf4, 0xaf, 0x63, 0x83, 0x23, 0x80,
+  0x05, 0x00, 0x00, 0x3c, 0x8c, 0x64, 0x88, 0x01, 0xd0, 0xd3, 0x23, 0x80,
+  0x00, 0x09, 0xd8, 0xd3, 0x03, 0x90, 0x40, 0x00, 0x64, 0xc7, 0x03, 0xb0,
+  0x8a, 0x21, 0xc0, 0x23, 0x09, 0xa0, 0x0f, 0x0c, 0xe6, 0x03, 0x10, 0xe6,
+  0x35, 0x0c, 0x00, 0x1b, 0x04, 0x54, 0xdc, 0xfb, 0x63, 0xc2, 0x41, 0x20,
+  0xe8, 0xf3, 0x63, 0x00, 0x00, 0x66, 0xf6, 0xbf, 0x7f, 0x35, 0x0c, 0x00,
+  0xc0, 0x44, 0x64, 0xd4, 0xf3, 0x63, 0x09, 0x00, 0x00, 0x00, 0x93, 0x52,
+  0x04, 0x80, 0x66, 0x0e, 0x40, 0x60, 0x82, 0x41, 0x20, 0xc8, 0xdb, 0x62,
+  0xd4, 0x87, 0x62, 0x1b, 0x00, 0xe0, 0x0c, 0x00, 0x64, 0x38, 0x0c, 0xc8,
+  0x83, 0x4b, 0x90, 0x88, 0x03, 0xd8, 0xc9, 0xf3, 0xff, 0xf8, 0x93, 0x63,
+  0x8b, 0x43, 0x80, 0x80, 0x0b, 0xd0, 0x5f, 0xd5, 0x7f, 0xd0, 0xfb, 0x63,
+  0x40, 0x84, 0x62, 0x80, 0x00, 0x64, 0x1b, 0x02, 0xf2, 0x67, 0xc3, 0xfe,
+  0x83, 0xa0, 0xf1, 0x02, 0x48, 0x20, 0x0b, 0x02, 0xf2, 0x67, 0xc3, 0xfe,
+  0x07, 0x00, 0xfe, 0x5c, 0x80, 0x62, 0x43, 0xe0, 0xf1, 0xfd, 0xbf, 0xff,
+  0x00, 0x00, 0x64, 0x07, 0x42, 0xf2, 0x67, 0xc3, 0xfe, 0x8f, 0x1f, 0xfe,
+  0x83, 0xc2, 0xfe, 0x02, 0x78, 0x27, 0x03, 0x78, 0xfe, 0x00, 0x04, 0x23,
+  0x0e, 0x40, 0x20, 0x10, 0x00, 0x64, 0x00, 0x10, 0x1e, 0x03, 0x04, 0x00,
+  0x00, 0x08, 0x1e, 0xc0, 0x04, 0x1e, 0x00, 0x3c, 0x23, 0x57, 0xc3, 0xfe,
+  0x05, 0x10, 0x00, 0x18, 0x28, 0x64, 0xe0, 0x18, 0xc8, 0x83, 0x41, 0x90,
+  0x93, 0x45, 0x90, 0xa3, 0x79, 0x90, 0xb3, 0x7d, 0x90, 0x1f, 0xa5, 0xf1,
+  0xdc, 0xe9, 0xa3, 0x83, 0x1d, 0x90, 0x1f, 0x8f, 0xf1, 0x93, 0x1d, 0x90,
+  0x9f, 0x8f, 0xf1, 0xa3, 0x1d, 0x90, 0x1f, 0xe0, 0xf1, 0xb3, 0x1d, 0x90,
+  0x1f, 0xa5, 0xf1, 0xd0, 0x31, 0x26, 0x2b, 0x00, 0xf3, 0x1f, 0xce, 0xf1,
+  0xa3, 0x1d, 0x90, 0x9f, 0xce, 0xf1, 0xb3, 0x1d, 0x90, 0x1f, 0xa5, 0xf1,
+  0xd4, 0x31, 0x26, 0x2b, 0x00, 0xf3, 0x1f, 0xdd, 0xf1, 0xa3, 0x1d, 0x90,
+  0x9f, 0xdd, 0xf1, 0xb3, 0x1d, 0x90, 0x18, 0x00, 0x64, 0x10, 0x18, 0xc8,
+  0xc0, 0xdb, 0x1f, 0x67, 0x1e, 0xfe, 0x73, 0x87, 0xf1, 0x76, 0x53, 0x20,
+  0x77, 0x30, 0xf2, 0xb3, 0xc2, 0xfe, 0x32, 0x43, 0x04, 0x03, 0x7b, 0xfe,
+  0x30, 0x80, 0x64, 0x6b, 0x32, 0xf2, 0x1f, 0x1e, 0xfe, 0x17, 0x1e, 0xfe,
+  0x2b, 0x28, 0xe0, 0x3f, 0x00, 0xfd, 0x03, 0x40, 0xfd, 0xa3, 0x7f, 0x90,
+  0x93, 0x43, 0x90, 0x67, 0xc3, 0xfe, 0x07, 0xa9, 0xf1, 0xa3, 0x07, 0x90,
+  0xbf, 0xa9, 0xf1, 0xb3, 0x3f, 0x90, 0x03, 0xaa, 0xf1, 0x83, 0x43, 0x90,
+  0x67, 0xc3, 0xfe, 0x19, 0x00, 0x00, 0x80, 0x40, 0x74, 0xdc, 0x8f, 0x62,
+  0x2b, 0x28, 0xe0, 0x3f, 0x00, 0xfd, 0x03, 0x40, 0xfd, 0xa3, 0x7f, 0x90,
+  0x93, 0x43, 0x90, 0x67, 0xc3, 0xfe, 0x07, 0xa9, 0xf1, 0xa3, 0x07, 0x90,
+  0xbf, 0xa9, 0xf1, 0xb3, 0x3f, 0x90, 0x03, 0xaa, 0xf1, 0x83, 0x43, 0x90,
+  0x67, 0xc3, 0xfe, 0x19, 0x00, 0x00, 0xc0, 0x40, 0x74, 0xdc, 0x8b, 0x62,
+  0x2b, 0x28, 0xe0, 0x3f, 0x00, 0xfd, 0x03, 0x40, 0xfd, 0xa3, 0x7f, 0x90,
+  0x93, 0x43, 0x90, 0x67, 0xc3, 0xfe, 0x07, 0xa9, 0xf1, 0xa3, 0x07, 0x90,
+  0xbf, 0xa9, 0xf1, 0xb3, 0x3f, 0x90, 0x03, 0xaa, 0xf1, 0x83, 0x43, 0x90,
+  0x67, 0xc3, 0xfe, 0x19, 0x00, 0x00, 0x40, 0x40, 0x74, 0xdc, 0x87, 0x62,
+  0x09, 0x00, 0x00, 0xc7, 0x50, 0xf9, 0x10, 0x00, 0x64, 0xc9, 0xf3, 0xff,
+  0x5c, 0x52, 0x72, 0x93, 0xc2, 0xfe, 0x12, 0x41, 0x24, 0x03, 0x79, 0xfe,
+  0x53, 0x87, 0xf1, 0x56, 0x41, 0x24, 0x77, 0x10, 0xf2, 0x10, 0x80, 0x64,
+  0x5b, 0x12, 0xf2, 0x6b, 0x12, 0xf2, 0x67, 0xc3, 0xfe, 0x93, 0xc2, 0xfe,
+  0x12, 0x41, 0x04, 0x03, 0x79, 0xfe, 0xff, 0x1b, 0xfe, 0x09, 0x00, 0x00,
+  0x53, 0x4c, 0xf4, 0x33, 0xc3, 0xfe, 0x1b, 0x10, 0xe6, 0x09, 0x00, 0x00,
+  0x44, 0x03, 0x81, 0x7d, 0x00, 0x00, 0x3c, 0x7c, 0xaf, 0x5e, 0x40, 0x20,
+  0x0e, 0x00, 0x60, 0x09, 0x00, 0x00, 0x64, 0x07, 0x81, 0x58, 0x00, 0x64,
+  0xb3, 0x03, 0x90, 0xa3, 0x1b, 0x90, 0x07, 0x00, 0xfd, 0x83, 0x47, 0xb0,
+  0x01, 0x00, 0xf0, 0x48, 0x04, 0x64, 0xc0, 0x00, 0x74, 0xc4, 0x87, 0x62,
+  0x82, 0x83, 0xe0, 0x00, 0xe0, 0x26, 0x1a, 0x40, 0x60, 0x88, 0x1b, 0xd8,
+  0x01, 0x00, 0xf0, 0x48, 0x01, 0x64, 0xc0, 0x00, 0x74, 0xe4, 0x83, 0x62,
+  0x48, 0x00, 0x64, 0xa3, 0x0b, 0x90, 0x00, 0x00, 0x74, 0x01, 0x00, 0xf0,
+  0x48, 0x00, 0x64, 0xcc, 0x83, 0x62, 0x40, 0x00, 0x64, 0xd0, 0xcf, 0x63,
+  0x03, 0x80, 0xe5, 0x20, 0x84, 0x1d, 0x10, 0x7a, 0x31, 0xb3, 0x23, 0x00,
+  0x4c, 0x0a, 0x2b, 0x3c, 0x02, 0xa7, 0x03, 0x33, 0x01, 0xd3, 0x50, 0xfb,
+  0x9b, 0x23, 0x40, 0x06, 0x40, 0x20, 0x22, 0x41, 0x20, 0xd6, 0x43, 0x20,
+  0x84, 0x14, 0x72, 0x87, 0x0d, 0x00, 0x4e, 0x4c, 0x00, 0xd3, 0x20, 0x00,
+  0xbb, 0xd3, 0xf2, 0xcc, 0x01, 0x64, 0xa3, 0x0f, 0xb0, 0x87, 0x23, 0x00,
+  0x47, 0x08, 0x90, 0x8f, 0x37, 0x00, 0x0c, 0x3d, 0x72, 0x03, 0xa3, 0x80,
+  0x8b, 0x4d, 0x00, 0xf8, 0x97, 0x62, 0xfa, 0x41, 0x20, 0x07, 0x84, 0xe5,
+  0x4e, 0x1d, 0x00, 0xcf, 0x44, 0x00, 0xcc, 0x00, 0xb6, 0x3a, 0x00, 0x60,
+  0x64, 0x00, 0x64, 0x4c, 0x8e, 0x40, 0xd0, 0x80, 0xba, 0x60, 0x40, 0x70,
+  0x0a, 0x40, 0x60, 0x47, 0x10, 0x00, 0x9b, 0x8d, 0xf2, 0x4c, 0x0d, 0x31,
+  0x18, 0x0c, 0xc8, 0xd0, 0x90, 0x1d, 0x4e, 0x41, 0x20, 0xd0, 0x90, 0x1d,
+  0x83, 0xbf, 0x7f, 0xd0, 0x80, 0x92, 0xe6, 0xff, 0x7f, 0x67, 0x00, 0x80,
+  0x9b, 0x05, 0x00, 0x47, 0x10, 0x00, 0x4c, 0x06, 0x5e, 0x9b, 0x05, 0x00,
+  0xc4, 0x00, 0x66, 0xf6, 0xbf, 0x7f, 0xc7, 0xbf, 0x7f, 0xca, 0x1f, 0x00,
+  0x8b, 0x44, 0x00, 0x8c, 0x00, 0xb6, 0x4e, 0x00, 0x60, 0x50, 0x00, 0x64,
+  0x08, 0x89, 0x40, 0x90, 0x80, 0xba, 0x32, 0x40, 0x60, 0x10, 0x10, 0x5a,
+  0xc3, 0x10, 0x90, 0xcf, 0x88, 0xf2, 0xc8, 0x0f, 0x31, 0x20, 0x08, 0xc8,
+  0x3e, 0x42, 0x20, 0xa2, 0x40, 0x20, 0xca, 0x43, 0x20, 0x3e, 0x42, 0x20,
+  0xa2, 0x40, 0x20, 0x37, 0xbf, 0x7f, 0x10, 0x08, 0xf0, 0xc0, 0x10, 0xd8,
+  0xd7, 0xbf, 0x7f, 0x90, 0x80, 0x92, 0xd2, 0xff, 0x7f, 0xc0, 0x00, 0xe4,
+  0x03, 0x10, 0x00, 0xcf, 0x04, 0x00, 0x13, 0xf0, 0x8f, 0x08, 0x05, 0x5e,
+  0xc4, 0x08, 0x78, 0x84, 0x00, 0x66, 0xf6, 0xbf, 0x7f, 0xaf, 0xbf, 0x7f,
+  0x00, 0x7c, 0x31, 0x00, 0xfc, 0xa1, 0x00, 0x3c, 0x23, 0x03, 0x18, 0xe5,
+  0x18, 0x84, 0x1d, 0x09, 0x00, 0x00, 0x00, 0x9c, 0x52, 0x96, 0x40, 0x20,
+  0x00, 0x00, 0x66, 0x16, 0x00, 0x60, 0x4a, 0x41, 0x20, 0x80, 0x9d, 0x1d,
+  0xd0, 0x93, 0x62, 0x07, 0x1c, 0xe5, 0x08, 0x00, 0x64, 0x00, 0x00, 0x74,
+  0xc0, 0x93, 0x62, 0xfd, 0xff, 0xff, 0x3c, 0xfc, 0x87, 0x12, 0x40, 0x60,
+  0x44, 0x00, 0x64, 0x09, 0x00, 0x00, 0x84, 0x07, 0x7f, 0x09, 0x00, 0x00,
+  0x08, 0x9c, 0x52, 0x84, 0x00, 0x66, 0xc2, 0xbf, 0x7f, 0x4a, 0x41, 0x20,
+  0x80, 0x9d, 0x1d, 0xcc, 0xfb, 0x63, 0xbf, 0xbf, 0x7f, 0x03, 0x00, 0xe0,
+  0xcc, 0xfb, 0x63, 0x03, 0x60, 0x20, 0x07, 0x04, 0xe0, 0x37, 0x00, 0xfe,
+  0x9f, 0x00, 0xfe, 0x03, 0x00, 0xe0, 0xc4, 0x87, 0x62, 0x40, 0x80, 0x1d,
+  0x07, 0x04, 0xe0, 0x03, 0x10, 0xe5, 0x14, 0x7c, 0x27, 0x58, 0x7c, 0x27,
+  0x03, 0xd4, 0xfa, 0x47, 0xd8, 0xfa, 0x03, 0xd4, 0xf2, 0x47, 0xd8, 0xf2,
+  0xdc, 0x83, 0x62, 0x47, 0xd4, 0xfa, 0x47, 0xd4, 0xf2, 0x57, 0xd9, 0xfa,
+  0x03, 0xd4, 0xfa, 0x03, 0xd4, 0xf2, 0x07, 0x14, 0xe5, 0x4b, 0x24, 0xfe,
+  0x50, 0x04, 0xc8, 0x8a, 0x4c, 0x20, 0x8b, 0x04, 0x00, 0x52, 0x40, 0x20,
+  0x04, 0x88, 0x3e, 0x8c, 0x80, 0x25, 0x00, 0x8c, 0x40, 0x10, 0x08, 0xca,
+  0x00, 0x50, 0x1e, 0x00, 0x3c, 0x23, 0x04, 0x00, 0x64, 0xb0, 0xc7, 0xc9,
+  0x47, 0x00, 0x80, 0xa0, 0xc7, 0xc9, 0x07, 0x00, 0xfe, 0x0e, 0x40, 0x20,
+  0x48, 0x04, 0x5e, 0xc4, 0x08, 0x78, 0x84, 0x00, 0x66, 0xf6, 0xbf, 0x7f,
+  0x00, 0x3c, 0x23, 0x8c, 0x00, 0x64, 0x01, 0x00, 0x00, 0xcf, 0x01, 0xfe,
+  0x01, 0x04, 0x00, 0x8c, 0x05, 0x64, 0x01, 0x00, 0x00, 0x6f, 0x01, 0xfe,
+  0x4b, 0xc3, 0xfe, 0x63, 0xc3, 0xfe, 0x67, 0xc3, 0xfe, 0x8f, 0x03, 0x80,
+  0x83, 0x13, 0x80, 0xbb, 0x23, 0x00, 0xc0, 0x00, 0x86, 0x02, 0xbc, 0x9f,
+  0x00, 0x3c, 0x23, 0xa0, 0xcf, 0x7b, 0x67, 0xc3, 0xfe, 0x63, 0xc3, 0xfe,
+  0xa7, 0x1f, 0xfe, 0x10, 0x00, 0x64, 0xc5, 0xf3, 0xff, 0xf4, 0xd3, 0x72,
+  0xcf, 0x1f, 0xfe
+};
+
+#define PMC_DTCM_LOG_SIZE 256
+
+const unsigned char pmcdata[] = {
+  0x3c, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x40, 0x01, 0x00, 0x00, 0x40, 0x0a, 0x00, 0x00, 0xcc, 0x04, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x44, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41, 0x42,
+  0x43, 0x44, 0x45, 0x46, 0x00, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
+  0x37, 0x38, 0x39, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x00, 0x28, 0x6e,
+  0x75, 0x6c, 0x6c, 0x29, 0x00, 0x25, 0x30, 0x34, 0x75, 0x3a, 0x20, 0x00,
+  0x73, 0x63, 0x72, 0x61, 0x74, 0x63, 0x68, 0x3a, 0x20, 0x30, 0x78, 0x25,
+  0x30, 0x38, 0x78, 0x0a, 0x00, 0x50, 0x4d, 0x43, 0x5f, 0x56, 0x45, 0x52,
+  0x3a, 0x25, 0x64, 0x2e, 0x25, 0x64, 0x2e, 0x25, 0x64, 0x0a, 0x00, 0x24,
+  0x43, 0x68, 0x61, 0x6e, 0x67, 0x65, 0x3a, 0x20, 0x32, 0x38, 0x34, 0x30,
+  0x32, 0x37, 0x20, 0x24, 0x00, 0x32, 0x30, 0x31, 0x31, 0x30, 0x36, 0x5f,
+  0x31, 0x32, 0x32, 0x39, 0x00, 0x54, 0x53, 0x3a, 0x25, 0x73, 0x0a, 0x00,
+  0x43, 0x48, 0x49, 0x44, 0x3a, 0x25, 0x78, 0x0a, 0x00, 0x43, 0x52, 0x45,
+  0x56, 0x3a, 0x25, 0x78, 0x0a, 0x00, 0x50, 0x41, 0x52, 0x54, 0x49, 0x44,
+  0x3a, 0x25, 0x78, 0x20, 0x43, 0x46, 0x41, 0x4d, 0x3a, 0x25, 0x78, 0x20,
+  0x73, 0x6b, 0x69, 0x70, 0x70, 0x65, 0x64, 0x20, 0x63, 0x68, 0x69, 0x70,
+  0x20, 0x69, 0x64, 0x20, 0x76, 0x61, 0x6c, 0x69, 0x64, 0x61, 0x74, 0x69,
+  0x6f, 0x6e, 0x0a, 0x00, 0x52, 0x4f, 0x20, 0x53, 0x56, 0x54, 0x20, 0x25,
+  0x64, 0x20, 0x48, 0x56, 0x54, 0x20, 0x25, 0x64, 0x20, 0x4c, 0x56, 0x54,
+  0x20, 0x25, 0x64, 0x0a, 0x00, 0x48, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x43,
+  0x6c, 0x6f, 0x73, 0x65, 0x41, 0x56, 0x53, 0x3a, 0x20, 0x6f, 0x76, 0x65,
+  0x72, 0x77, 0x72, 0x69, 0x74, 0x69, 0x6e, 0x67, 0x20, 0x70, 0x72, 0x65,
+  0x76, 0x69, 0x6f, 0x75, 0x73, 0x20, 0x43, 0x6c, 0x6f, 0x73, 0x65, 0x41,
+  0x56, 0x53, 0x20, 0x6c, 0x6f, 0x67, 0x0a, 0x00, 0x48, 0x61, 0x6e, 0x64,
+  0x6c, 0x65, 0x43, 0x6c, 0x6f, 0x73, 0x65, 0x41, 0x56, 0x53, 0x3a, 0x20,
+  0x69, 0x73, 0x6c, 0x61, 0x6e, 0x64, 0x20, 0x25, 0x64, 0x20, 0x73, 0x6c,
+  0x6f, 0x77, 0x20, 0x25, 0x64, 0x20, 0x66, 0x61, 0x73, 0x74, 0x20, 0x25,
+  0x64, 0x20, 0x6d, 0x61, 0x78, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x69, 0x6e,
+  0x20, 0x25, 0x64, 0x0a, 0x00, 0x48, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x43,
+  0x6c, 0x6f, 0x73, 0x65, 0x41, 0x56, 0x53, 0x3a, 0x20, 0x66, 0x69, 0x6e,
+  0x69, 0x73, 0x68, 0x65, 0x64, 0x20, 0x77, 0x69, 0x74, 0x68, 0x20, 0x65,
+  0x72, 0x72, 0x6f, 0x72, 0x43, 0x6f, 0x64, 0x65, 0x20, 0x25, 0x75, 0x0a,
+  0x00, 0x41, 0x56, 0x53, 0x20, 0x44, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65,
+  0x64, 0x0a, 0x00, 0x44, 0x41, 0x43, 0x3a, 0x20, 0x25, 0x64, 0x0a, 0x00,
+  0x4c, 0x56, 0x54, 0x00, 0x48, 0x56, 0x54, 0x00, 0x64, 0x65, 0x76, 0x20,
+  0x61, 0x64, 0x64, 0x72, 0x20, 0x30, 0x78, 0x25, 0x78, 0x20, 0x52, 0x4f,
+  0x20, 0x74, 0x79, 0x70, 0x65, 0x20, 0x53, 0x56, 0x54, 0x20, 0x76, 0x61,
+  0x6c, 0x75, 0x65, 0x20, 0x25, 0x75, 0x20, 0x52, 0x4f, 0x20, 0x74, 0x79,
+  0x70, 0x65, 0x20, 0x25, 0x73, 0x20, 0x76, 0x61, 0x6c, 0x75, 0x65, 0x20,
+  0x25, 0x75, 0x0a, 0x00, 0x63, 0x75, 0x72, 0x5f, 0x64, 0x61, 0x63, 0x20,
+  0x25, 0x75, 0x20, 0x63, 0x75, 0x72, 0x56, 0x20, 0x25, 0x75, 0x20, 0x63,
+  0x75, 0x72, 0x54, 0x65, 0x6d, 0x70, 0x20, 0x25, 0x75, 0x20, 0x64, 0x65,
+  0x6c, 0x74, 0x61, 0x20, 0x25, 0x64, 0x20, 0x6e, 0x65, 0x77, 0x5f, 0x64,
+  0x61, 0x63, 0x20, 0x25, 0x75, 0x0a, 0x00, 0x4d, 0x56, 0x41, 0x44, 0x43,
+  0x31, 0x20, 0x4d, 0x65, 0x61, 0x73, 0x75, 0x72, 0x65, 0x64, 0x20, 0x25,
+  0x75, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x75, 0x6c, 0x61, 0x74, 0x65, 0x64,
+  0x20, 0x25, 0x75, 0x0a, 0x00, 0x4d, 0x65, 0x61, 0x73, 0x75, 0x72, 0x65,
+  0x64, 0x20, 0x4d, 0x56, 0x41, 0x44, 0x43, 0x32, 0x20, 0x25, 0x75, 0x0a,
+  0x00, 0x4d, 0x56, 0x20, 0x44, 0x65, 0x6c, 0x74, 0x61, 0x20, 0x66, 0x6f,
+  0x72, 0x20, 0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x20, 0x64, 0x65, 0x6c,
+  0x74, 0x61, 0x20, 0x25, 0x75, 0x20, 0x4d, 0x56, 0x0a, 0x00, 0x44, 0x75,
+  0x6d, 0x70, 0x20, 0x61, 0x6c, 0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73, 0x20,
+  0x6f, 0x6e, 0x20, 0x76, 0x68, 0x69, 0x67, 0x68, 0x5f, 0x6d, 0x76, 0x20,
+  0x25, 0x64, 0x0a, 0x00, 0x44, 0x75, 0x6d, 0x70, 0x20, 0x61, 0x6c, 0x6c,
+  0x20, 0x52, 0x4f, 0x27, 0x73, 0x20, 0x6f, 0x6e, 0x20, 0x76, 0x6c, 0x6f,
+  0x77, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x52, 0x4f, 0x5b,
+  0x25, 0x64, 0x5d, 0x20, 0x74, 0x61, 0x72, 0x67, 0x65, 0x74, 0x5f, 0x72,
+  0x6f, 0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f, 0x77, 0x5f, 0x72, 0x6f, 0x20,
+  0x25, 0x64, 0x20, 0x73, 0x6c, 0x6f, 0x70, 0x65, 0x20, 0x25, 0x64, 0x20,
+  0x76, 0x6c, 0x6f, 0x77, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x64,
+  0x61, 0x63, 0x5f, 0x6c, 0x6f, 0x77, 0x20, 0x25, 0x64, 0x20, 0x76, 0x68,
+  0x69, 0x67, 0x68, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x64, 0x61,
+  0x63, 0x5f, 0x68, 0x69, 0x67, 0x68, 0x20, 0x25, 0x64, 0x20, 0x76, 0x6f,
+  0x6c, 0x74, 0x61, 0x67, 0x65, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x0a,
+  0x00, 0x52, 0x4f, 0x5b, 0x25, 0x64, 0x5d, 0x20, 0x74, 0x61, 0x72, 0x67,
+  0x65, 0x74, 0x5f, 0x72, 0x6f, 0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f, 0x77,
+  0x5f, 0x72, 0x6f, 0x20, 0x25, 0x64, 0x20, 0x76, 0x6c, 0x6f, 0x77, 0x5f,
+  0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x6c, 0x6f,
+  0x77, 0x20, 0x25, 0x64, 0x20, 0x68, 0x69, 0x67, 0x68, 0x5f, 0x72, 0x6f,
+  0x20, 0x25, 0x64, 0x20, 0x76, 0x68, 0x69, 0x67, 0x68, 0x5f, 0x6d, 0x76,
+  0x20, 0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x68, 0x69, 0x67, 0x68,
+  0x20, 0x25, 0x64, 0x0a, 0x00, 0x61, 0x76, 0x73, 0x5f, 0x64, 0x61, 0x63,
+  0x20, 0x25, 0x64, 0x20, 0x70, 0x72, 0x65, 0x64, 0x69, 0x63, 0x74, 0x5f,
+  0x6d, 0x76, 0x20, 0x25, 0x75, 0x20, 0x61, 0x76, 0x73, 0x5f, 0x6d, 0x76,
+  0x20, 0x25, 0x64, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x5f, 0x6d, 0x61, 0x72,
+  0x67, 0x69, 0x6e, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x63, 0x61,
+  0x6c, 0x63, 0x5f, 0x73, 0x77, 0x72, 0x65, 0x67, 0x5f, 0x6d, 0x76, 0x20,
+  0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x68, 0x69, 0x67, 0x68, 0x20,
+  0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x6c, 0x6f, 0x77, 0x20, 0x25,
+  0x64, 0x0a, 0x00, 0x41, 0x56, 0x53, 0x20, 0x63, 0x6c, 0x6f, 0x73, 0x65,
+  0x64, 0x20, 0x6f, 0x6e, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x63, 0x6f, 0x64,
+  0x65, 0x20, 0x25, 0x64, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x5f, 0x73, 0x77,
+  0x72, 0x65, 0x67, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x74, 0x61,
+  0x72, 0x67, 0x65, 0x74, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x63,
+  0x61, 0x6c, 0x63, 0x5f, 0x73, 0x77, 0x72, 0x65, 0x67, 0x5f, 0x64, 0x61,
+  0x63, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x41, 0x56, 0x53, 0x20, 0x69, 0x73,
+  0x6c, 0x61, 0x6e, 0x64, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x61, 0x72, 0x67,
+  0x69, 0x6e, 0x5f, 0x6d, 0x76, 0x5f, 0x73, 0x6c, 0x6f, 0x77, 0x20, 0x25,
+  0x64, 0x20, 0x6d, 0x61, 0x72, 0x67, 0x69, 0x6e, 0x5f, 0x6d, 0x76, 0x5f,
+  0x66, 0x61, 0x73, 0x74, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x61, 0x78, 0x69,
+  0x6d, 0x75, 0x6d, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x20, 0x6d, 0x69,
+  0x6e, 0x69, 0x6d, 0x75, 0x6d, 0x5f, 0x6d, 0x76, 0x20, 0x25, 0x64, 0x0a,
+  0x00, 0x53, 0x65, 0x74, 0x74, 0x69, 0x6e, 0x67, 0x20, 0x54, 0x68, 0x72,
+  0x65, 0x73, 0x68, 0x6f, 0x6c, 0x64, 0x73, 0x20, 0x66, 0x6f, 0x72, 0x20,
+  0x25, 0x64, 0x20, 0x68, 0x69, 0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f, 0x20,
+  0x25, 0x64, 0x0a, 0x00, 0x53, 0x65, 0x74, 0x74, 0x69, 0x6e, 0x67, 0x20,
+  0x52, 0x34, 0x38, 0x5f, 0x25, 0x64, 0x20, 0x54, 0x68, 0x72, 0x65, 0x73,
+  0x68, 0x6f, 0x6c, 0x64, 0x73, 0x20, 0x68, 0x69, 0x20, 0x25, 0x64, 0x20,
+  0x6c, 0x6f, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x44, 0x75, 0x6d, 0x70, 0x20,
+  0x61, 0x6c, 0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73, 0x20, 0x6f, 0x6e, 0x20,
+  0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x0a, 0x00, 0x40, 0x40, 0x40,
+  0x46, 0x41, 0x49, 0x4c, 0x45, 0x44, 0x00, 0x40, 0x40, 0x40, 0x50, 0x41,
+  0x53, 0x53, 0x45, 0x44, 0x00, 0x00, 0x00, 0x00, 0xa5, 0x0d, 0x27, 0x81,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0xff, 0x00, 0x00, 0x00, 0x50, 0x0a, 0x00, 0x00
+};
+#endif //PMC_ROMDATA_6756_H
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_firmware_68460.h b/arch/arm/mach-bcmbca/pmc/pmc_firmware_68460.h
new file mode 100644
index 0000000000..418167338f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_firmware_68460.h
@@ -0,0 +1,2468 @@
+/*
+ * * <:copyright-BRCM:2017:DUAL/GPL:standard
+ * * 
+ * *    Copyright (c) 2017 Broadcom 
+ * *    All Rights Reserved
+ * * 
+ * * This program is free software; you can redistribute it and/or modify
+ * * it under the terms of the GNU General Public License, version 2, as published by
+ * * the Free Software Foundation (the "GPL").
+ * * 
+ * * This program is distributed in the hope that it will be useful,
+ * * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * * GNU General Public License for more details.
+ * * 
+ * * 
+ * * A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+ * * writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * * Boston, MA 02111-1307, USA.
+ * * 
+ * * :>
+ * */
+
+#ifndef PMC_ROMDATA_68460_H
+#define PMC_ROMDATA_68460_H
+#define CFG_BOOT_PMC3_START_ADDR 0xc0000
+#define CFG_BOOT_PMC3_DATA_ADDR 0x4000000
+#define PMC_VER_IMPL 3
+#define PMC_VER_MAJOR 4
+#define PMC_VER_MINOR 1
+const unsigned char pmcappdata[] = {
+  0x01, 0x00, 0x00, 0x07, 0x12, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x08, 0xe5, 0x00,
+  0x00, 0x64, 0x18, 0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xdc, 0xf7, 0x63, 0x00,
+  0x00, 0x64, 0x20, 0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xec, 0xf3, 0x63, 0x1f,
+  0x00, 0x60, 0x40, 0x00, 0x65, 0x5b, 0x02, 0xf2, 0xfd, 0xff, 0x81, 0xc0,
+  0xff, 0x64, 0x33, 0x02, 0xf2, 0x67, 0xc3, 0xfe, 0x00, 0x00, 0x64, 0x18,
+  0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xe8, 0xeb, 0x63, 0xfd, 0xff, 0x00, 0xd4,
+  0xff, 0x64, 0x55, 0xd5, 0xff, 0x4b, 0x55, 0x45, 0xc8, 0xc8, 0xfc, 0x01,
+  0x00, 0x00, 0xcc, 0xeb, 0x63, 0x00, 0x00, 0x64, 0x20, 0x00, 0xc8, 0x03,
+  0x0c, 0xe5, 0xfd, 0xf3, 0xff, 0x37, 0x1c, 0xfe, 0x07, 0x0c, 0xe5, 0x03,
+  0x00, 0x80, 0x00, 0x3c, 0x23, 0x0f, 0x20, 0xe5, 0x08, 0x00, 0x64, 0x04,
+  0x04, 0x64, 0x00, 0x0c, 0x64, 0x01, 0x00, 0x00, 0xcc, 0x8b, 0x63, 0x01,
+  0x00, 0x04, 0x00, 0x01, 0x64, 0xd8, 0xff, 0x63, 0x04, 0x00, 0x66, 0x2e,
+  0x00, 0x60, 0x00, 0x0c, 0x64, 0x08, 0x00, 0x64, 0x04, 0x08, 0x64, 0x01,
+  0x00, 0x00, 0xd4, 0x83, 0x63, 0x01, 0x0c, 0x00, 0x00, 0x08, 0x64, 0x50,
+  0x01, 0xc8, 0xe8, 0xf3, 0x63, 0xa3, 0x00, 0x60, 0xd4, 0x00, 0x64, 0x01,
+  0x00, 0x04, 0x18, 0x04, 0x64, 0x34, 0x14, 0x72, 0x14, 0x01, 0x64, 0x01,
+  0x00, 0x04, 0x18, 0x0d, 0x74, 0x9c, 0x14, 0x72, 0xbb, 0xbf, 0x7f, 0x82,
+  0x41, 0x20, 0xfc, 0xf7, 0x63, 0x22, 0x40, 0x20, 0x83, 0x11, 0x00, 0xf0,
+  0xf7, 0x63, 0xa3, 0x03, 0x90, 0x83, 0x21, 0x00, 0xe4, 0xf7, 0x63, 0x87,
+  0x23, 0x80, 0x0a, 0x40, 0x20, 0x02, 0x42, 0x20, 0xdf, 0x05, 0x00, 0xfc,
+  0x8f, 0x62, 0x6c, 0x1d, 0x3a, 0x9b, 0x31, 0x00, 0xc6, 0xbf, 0x7f, 0xaf,
+  0xbf, 0x7f, 0x82, 0x41, 0x20, 0xf8, 0xf3, 0x63, 0x22, 0x40, 0x20, 0x83,
+  0x11, 0x00, 0xec, 0xf3, 0x63, 0x0a, 0x40, 0x20, 0x03, 0x02, 0x50, 0xe0,
+  0x8f, 0x62, 0xdf, 0x05, 0x00, 0x6c, 0x1d, 0x3a, 0x9b, 0x21, 0x00, 0xd6,
+  0xbf, 0x7f, 0x43, 0xbf, 0x7f, 0x01, 0x00, 0x04, 0x00, 0x02, 0x64, 0xc0,
+  0xf3, 0x63, 0x1a, 0x40, 0x20, 0x01, 0x00, 0x04, 0x00, 0x03, 0x64, 0xf0,
+  0xef, 0x63, 0x1e, 0x40, 0x20, 0x08, 0x00, 0x64, 0x00, 0x0c, 0x64, 0x04,
+  0x0c, 0x64, 0x05, 0x00, 0x00, 0x14, 0x60, 0x55, 0x01, 0x00, 0x00, 0xd0,
+  0xd7, 0x62, 0x01, 0x0c, 0x00, 0x40, 0x79, 0x64, 0x20, 0x00, 0xc8, 0x4a,
+  0x41, 0x20, 0x80, 0x9d, 0x1d, 0xd0, 0x8b, 0x62, 0x00, 0x0c, 0x64, 0x08,
+  0x00, 0x64, 0x04, 0x0e, 0x64, 0x01, 0x00, 0x00, 0xcc, 0xcf, 0x62, 0x00,
+  0x00, 0x64, 0x18, 0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xfc, 0x9b, 0x63, 0x00,
+  0x0c, 0x64, 0x8a, 0x41, 0x20, 0x04, 0x10, 0x64, 0x01, 0x00, 0x00, 0xe0,
+  0xc7, 0x62, 0x00, 0x00, 0x64, 0x28, 0x00, 0xc8, 0x4a, 0x41, 0x20, 0x80,
+  0x9d, 0x1d, 0xfd, 0xf3, 0xff, 0xf8, 0x93, 0x63, 0x4a, 0x41, 0x20, 0x80,
+  0x9d, 0x1d, 0x01, 0x00, 0x00, 0xc8, 0xc7, 0x62, 0x88, 0x08, 0x31, 0x18,
+  0x08, 0xca, 0x48, 0x10, 0x5a, 0x10, 0x08, 0x7a, 0x00, 0x3c, 0x23, 0x0c,
+  0x00, 0x64, 0x4c, 0xcc, 0x1e, 0x84, 0x08, 0x31, 0x10, 0x04, 0xca, 0x10,
+  0x0c, 0x7a, 0x00, 0x3c, 0x23, 0x03, 0x08, 0xe6, 0x05, 0x00, 0x00, 0x00,
+  0x62, 0x52, 0x04, 0x00, 0x66, 0x52, 0x00, 0x60, 0x09, 0x00, 0x00, 0x00,
+  0x70, 0x55, 0x18, 0x05, 0x64, 0x44, 0x00, 0x72, 0x83, 0x05, 0x40, 0x09,
+  0x00, 0x00, 0x04, 0xc2, 0x80, 0x05, 0x00, 0x00, 0x00, 0x64, 0x55, 0x69,
+  0x00, 0x00, 0xf4, 0xff, 0x62, 0x05, 0x00, 0x00, 0x00, 0x64, 0x55, 0x86,
+  0x41, 0x20, 0x69, 0x00, 0x00, 0xf8, 0xfb, 0x62, 0x40, 0x00, 0x64, 0x05,
+  0x00, 0x00, 0x44, 0xc0, 0x7e, 0x07, 0x0c, 0xe6, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0xdc, 0x93, 0x62, 0x00, 0x04, 0x64, 0x04, 0x04, 0x64, 0x08, 0x00, 0x64,
+  0x93, 0x40, 0x60, 0x01, 0x00, 0x04, 0x38, 0x00, 0x55, 0xba, 0x4f, 0x00,
+  0xcd, 0xab, 0x89, 0xc8, 0x7b, 0x64, 0x45, 0x23, 0x01, 0xcc, 0x59, 0x64,
+  0x05, 0x00, 0x00, 0x00, 0x6c, 0x64, 0x86, 0x43, 0x20, 0xd0, 0x87, 0x62,
+  0xbb, 0x63, 0x00, 0x80, 0x03, 0xe6, 0x00, 0x04, 0x64, 0x04, 0x06, 0x64,
+  0x08, 0x00, 0x64, 0x4f, 0x40, 0x60, 0x04, 0x00, 0x64, 0x4c, 0x04, 0x48,
+  0xc3, 0x07, 0xf6, 0x3b, 0x00, 0xf2, 0x00, 0x04, 0x64, 0x04, 0x08, 0x64,
+  0x08, 0x00, 0x64, 0x2f, 0x40, 0x60, 0x83, 0xc2, 0xfe, 0x02, 0x60, 0x07,
+  0x03, 0x78, 0xfe, 0xfd, 0xff, 0xff, 0x37, 0x0f, 0xfe, 0x47, 0xc0, 0xf2,
+  0x44, 0x0c, 0x31, 0x10, 0x04, 0xca, 0x08, 0x08, 0xe8, 0x00, 0x3c, 0x23,
+  0x00, 0x20, 0x2b, 0x03, 0x44, 0xfb, 0x83, 0x40, 0xf1, 0x09, 0x00, 0x00,
+  0x84, 0xc1, 0x80, 0x05, 0x12, 0x00, 0x84, 0x40, 0x80, 0x00, 0x3c, 0x23,
+  0x03, 0x18, 0xe5, 0x18, 0x84, 0x1d, 0x96, 0x40, 0x20, 0x00, 0x0c, 0x64,
+  0x08, 0x00, 0x64, 0x04, 0x14, 0x64, 0xc8, 0xff, 0x63, 0x00, 0x00, 0x64,
+  0x18, 0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xd4, 0xc7, 0x62, 0x8a, 0x41, 0x20,
+  0x00, 0x14, 0x74, 0xec, 0xfb, 0x63, 0x80, 0x9d, 0x1d, 0x4a, 0x41, 0x20,
+  0xa3, 0x6c, 0x60, 0x1a, 0x40, 0x20, 0x0a, 0x40, 0x20, 0x00, 0x1c, 0x74,
+  0xd0, 0xfb, 0x63, 0x82, 0x41, 0x20, 0xe4, 0xdf, 0x62, 0x08, 0x00, 0x74,
+  0xc0, 0x3f, 0x64, 0x00, 0x08, 0x1d, 0x14, 0x00, 0x64, 0x50, 0x37, 0x64,
+  0x44, 0x09, 0x1e, 0x57, 0x05, 0x00, 0x13, 0x45, 0x00, 0xec, 0xd3, 0x73,
+  0x88, 0x03, 0x64, 0x0b, 0x0b, 0xf2, 0x9f, 0x01, 0xf2, 0xc7, 0x01, 0xf2,
+  0xef, 0x01, 0xf2, 0x17, 0x02, 0xf2, 0x3f, 0x02, 0xf2, 0x67, 0x02, 0xf2,
+  0xe7, 0x41, 0xf2, 0xff, 0x40, 0xf2, 0x87, 0x03, 0xf2, 0xcf, 0x41, 0xf2,
+  0x48, 0x00, 0x64, 0x73, 0x0a, 0xf2, 0x48, 0x00, 0x64, 0xf3, 0x0a, 0xf2,
+  0x88, 0xc4, 0x64, 0xc3, 0x4a, 0xf2, 0x05, 0x0c, 0x00, 0x08, 0x29, 0x64,
+  0xb3, 0x0a, 0xf2, 0x05, 0x0c, 0x00, 0x08, 0x14, 0x64, 0xbb, 0x0a, 0xf2,
+  0x05, 0x0c, 0x00, 0x88, 0x1e, 0x64, 0xc3, 0x0a, 0xf2, 0x05, 0x0c, 0x00,
+  0x88, 0x33, 0x64, 0xcb, 0x0a, 0xf2, 0x05, 0x0c, 0x00, 0x08, 0x3e, 0x64,
+  0xd3, 0x0a, 0xf2, 0x05, 0x0c, 0x00, 0x88, 0x54, 0x64, 0xdb, 0x0a, 0xf2,
+  0x05, 0x0c, 0x00, 0x48, 0x55, 0x64, 0xe3, 0x0a, 0xf2, 0x01, 0x0c, 0x00,
+  0x8c, 0x08, 0x64, 0x6d, 0x0c, 0x00, 0x08, 0x10, 0x64, 0x1b, 0x0f, 0xf2,
+  0x23, 0x0b, 0xf2, 0xfd, 0xff, 0xff, 0xc8, 0xff, 0x64, 0xfd, 0xff, 0x00,
+  0xcc, 0xff, 0x64, 0xcf, 0x48, 0xf2, 0xdf, 0x40, 0xf2, 0x67, 0xc3, 0xfe,
+  0x83, 0xc2, 0xfe, 0x00, 0x10, 0x94, 0x03, 0x78, 0xfe, 0x01, 0xad, 0xde,
+  0x00, 0x00, 0x64, 0x07, 0x04, 0x00, 0x0b, 0x08, 0x00, 0x0f, 0x0c, 0x00,
+  0x13, 0x10, 0x00, 0x17, 0x14, 0x00, 0x1b, 0x18, 0x00, 0x1f, 0x1c, 0x00,
+  0x23, 0x20, 0x00, 0x27, 0x24, 0x00, 0x2b, 0x28, 0x00, 0x2f, 0x2c, 0x00,
+  0x33, 0x30, 0x00, 0x37, 0x34, 0x00, 0x3b, 0x38, 0x00, 0x00, 0x60, 0x26,
+  0x00, 0xe0, 0x26, 0x00, 0x3c, 0x23, 0x8b, 0xc2, 0xfe, 0x82, 0x48, 0x20,
+  0x03, 0x78, 0xfe, 0xfd, 0xff, 0xff, 0xc0, 0xff, 0x64, 0xfd, 0xff, 0x00,
+  0xc4, 0xff, 0x64, 0xc0, 0xc0, 0xfc, 0x47, 0x80, 0xf8, 0x83, 0x78, 0xfe,
+  0xcf, 0x40, 0xf2, 0x00, 0x3c, 0x23, 0x03, 0x08, 0xe0, 0x8e, 0x1c, 0x00,
+  0x90, 0x0c, 0x31, 0x10, 0x0c, 0xca, 0x04, 0x04, 0x78, 0x08, 0x00, 0x64,
+  0x48, 0x08, 0x1d, 0x10, 0x10, 0xca, 0x08, 0x08, 0xe8, 0x07, 0x0c, 0xe0,
+  0x2b, 0x28, 0xe0, 0x3f, 0x00, 0xfd, 0xa3, 0x7f, 0x90, 0x3f, 0x40, 0xfd,
+  0x93, 0x7f, 0x90, 0x3f, 0xa9, 0xf1, 0xa3, 0x3f, 0x90, 0xbf, 0xa9, 0xf1,
+  0xb3, 0x3f, 0x90, 0x3f, 0xaa, 0xf1, 0x19, 0x00, 0x00, 0x80, 0x40, 0x74,
+  0x83, 0x7f, 0x90, 0xec, 0x93, 0x62, 0x2b, 0x28, 0xe0, 0x3f, 0x00, 0xfd,
+  0xa3, 0x7f, 0x90, 0x3f, 0x40, 0xfd, 0x93, 0x7f, 0x90, 0x3f, 0xa9, 0xf1,
+  0xa3, 0x3f, 0x90, 0xbf, 0xa9, 0xf1, 0xb3, 0x3f, 0x90, 0x3f, 0xaa, 0xf1,
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+  0x05, 0x00, 0x00, 0x06, 0x1c, 0xe1, 0x47, 0x9c, 0xf2, 0x1c, 0x08, 0x64,
+  0xdf, 0xc5, 0xf2, 0x30, 0x1c, 0xc8, 0x68, 0x9e, 0x40, 0x04, 0x86, 0x3e,
+  0x98, 0x9c, 0x40, 0x6b, 0x68, 0xfb, 0x14, 0x9e, 0x40, 0xac, 0x41, 0x31,
+  0x80, 0xae, 0x1d, 0xc4, 0xab, 0x63, 0xa3, 0x03, 0x90, 0x80, 0xae, 0x1d,
+  0xf4, 0xa7, 0x63, 0x8b, 0x23, 0x80, 0xa7, 0x3d, 0xfe, 0x44, 0x41, 0x31,
+  0x40, 0x42, 0x24, 0x88, 0x40, 0x2b, 0x83, 0x44, 0xd0, 0x0c, 0x08, 0x3a,
+  0x22, 0x00, 0x60, 0x8b, 0x98, 0xf2, 0x0c, 0x88, 0x3a, 0x8f, 0x98, 0xf2,
+  0xac, 0x09, 0x3a, 0x86, 0x40, 0x20, 0x8b, 0xcc, 0xf9, 0x4b, 0x88, 0xf9,
+  0x8b, 0xc0, 0xf2, 0x80, 0xac, 0x1d, 0xa3, 0x0b, 0x90, 0xec, 0xa3, 0x63,
+  0x22, 0x40, 0x20, 0x83, 0x23, 0x80, 0xc6, 0x42, 0x20, 0xd8, 0xa3, 0x63,
+  0x46, 0x41, 0x20, 0x40, 0x42, 0x24, 0x43, 0x60, 0xd8, 0x0c, 0x04, 0x3a,
+  0xde, 0x01, 0x60, 0x47, 0x98, 0xf2, 0xac, 0x85, 0x3a, 0x5b, 0x98, 0xf2,
+  0x0c, 0x04, 0x3a, 0x4a, 0x40, 0x20, 0x47, 0xd8, 0xf9, 0x87, 0x84, 0xf9,
+  0xbf, 0x01, 0x60, 0x24, 0x08, 0x72, 0x40, 0x00, 0x74, 0xd8, 0x9f, 0x63,
+  0x1a, 0x40, 0x20, 0xfd, 0x00, 0x00, 0xbc, 0x7d, 0xb7, 0x12, 0x00, 0x60,
+  0xbc, 0x3d, 0xae, 0xde, 0x21, 0x80, 0x17, 0x00, 0x60, 0xfd, 0xff, 0x00,
+  0xbc, 0x7d, 0xaf, 0x1c, 0x04, 0x64, 0xde, 0xa1, 0x80, 0x80, 0x9d, 0x3e,
+  0x05, 0x00, 0x00, 0x2a, 0x1c, 0xe1, 0x6f, 0xda, 0xf2, 0xab, 0x9e, 0xf2,
+  0x1c, 0x08, 0x64, 0xdf, 0xe9, 0xf2, 0x88, 0x1d, 0xc8, 0x70, 0xaa, 0x3e,
+  0x98, 0x9d, 0x40, 0x44, 0x9e, 0x40, 0x28, 0xaa, 0x3e, 0xa7, 0x46, 0xfb,
+  0xa8, 0x41, 0x31, 0x00, 0xab, 0x1d, 0xf0, 0x97, 0x63, 0xa3, 0x03, 0x90,
+  0x00, 0xab, 0x1d, 0xe0, 0x97, 0x63, 0x8b, 0x23, 0x80, 0xaf, 0x3d, 0xfe,
+  0x44, 0x42, 0x31, 0xc0, 0x42, 0x24, 0x88, 0x40, 0x2b, 0x83, 0x44, 0xd0,
+  0x0c, 0x08, 0x3a, 0x14, 0x9e, 0x40, 0x22, 0x00, 0x60, 0x8b, 0x98, 0xf2,
+  0x0c, 0x88, 0x3a, 0x8f, 0x98, 0xf2, 0xac, 0x09, 0x3a, 0x86, 0x40, 0x20,
+  0x8b, 0xcc, 0xf9, 0x4b, 0x88, 0xf9, 0x8b, 0xc0, 0xf2, 0x80, 0xa8, 0x1d,
+  0xa3, 0x0b, 0x90, 0xd4, 0x93, 0x63, 0x22, 0x40, 0x20, 0x83, 0x23, 0x80,
+  0x86, 0x42, 0x20, 0xc0, 0x93, 0x63, 0x46, 0x42, 0x20, 0xec, 0x42, 0x24,
+  0x43, 0x60, 0xd8, 0xcc, 0x06, 0x3a, 0x22, 0x00, 0x60, 0x47, 0x98, 0xf2,
+  0xcc, 0x86, 0x3a, 0x43, 0x98, 0xf2, 0xac, 0x05, 0x3a, 0x4a, 0x40, 0x20,
+  0x47, 0xc0, 0xf9, 0x87, 0x84, 0xf9, 0x6f, 0xec, 0xf2, 0xa8, 0x41, 0x31,
+  0xc0, 0xaa, 0x1d, 0xc4, 0x8f, 0x63, 0xa3, 0x03, 0x90, 0xc0, 0xaa, 0x1d,
+  0xf4, 0x8b, 0x63, 0x8b, 0x23, 0x80, 0xa7, 0x3d, 0xfe, 0x44, 0x41, 0x31,
+  0x40, 0x42, 0x24, 0x88, 0x40, 0x2b, 0x83, 0x44, 0xd0, 0x0c, 0x08, 0x3a,
+  0x22, 0x00, 0x60, 0x8b, 0x98, 0xf2, 0x0c, 0x88, 0x3a, 0x8f, 0x98, 0xf2,
+  0xac, 0x09, 0x3a, 0x86, 0x40, 0x20, 0x8b, 0xcc, 0xf9, 0x4b, 0x88, 0xf9,
+  0x8b, 0xc0, 0xf2, 0x80, 0xa8, 0x1d, 0xa3, 0x0b, 0x90, 0xec, 0x87, 0x63,
+  0x22, 0x40, 0x20, 0x83, 0x23, 0x80, 0x86, 0x42, 0x20, 0xd8, 0x87, 0x63,
+  0x46, 0x41, 0x20, 0x40, 0x42, 0x24, 0x43, 0x60, 0xd8, 0x0c, 0x04, 0x3a,
+  0x1e, 0x00, 0x60, 0x47, 0x98, 0xf2, 0xac, 0x85, 0x3a, 0x5b, 0x98, 0xf2,
+  0x0c, 0x04, 0x3a, 0x5b, 0xd8, 0xf9, 0x47, 0x98, 0xf9, 0x47, 0xc0, 0xf2,
+  0x48, 0x9c, 0x3e, 0x0c, 0x00, 0x64, 0x1b, 0x02, 0x60, 0xcc, 0x24, 0x3a,
+  0x0e, 0x00, 0x60, 0x08, 0xa4, 0x1d, 0x0b, 0x02, 0x60, 0xfd, 0x00, 0x00,
+  0xfc, 0x7c, 0xb7, 0x16, 0x00, 0x60, 0xfc, 0x3c, 0xae, 0x1c, 0x00, 0x64,
+  0xde, 0x21, 0x80, 0x17, 0x00, 0x60, 0xfd, 0xff, 0x00, 0xfc, 0x7c, 0xaf,
+  0x1c, 0x04, 0x64, 0xde, 0xa1, 0x80, 0xc0, 0x9c, 0x3e, 0x05, 0x00, 0x00,
+  0x02, 0x1c, 0xe1, 0x18, 0x08, 0x64, 0x1f, 0x9c, 0xf2, 0x9b, 0xdd, 0xf2,
+  0x6c, 0x18, 0x72, 0x6c, 0x0e, 0x3a, 0x0e, 0x00, 0x60, 0xac, 0x20, 0x3a,
+  0x1e, 0x00, 0x60, 0x07, 0xca, 0xf2, 0x6c, 0x20, 0x3a, 0x6b, 0xce, 0xf2,
+  0x0b, 0x00, 0xfd, 0xab, 0xca, 0xf2, 0x56, 0x40, 0x20, 0x48, 0xa9, 0x1d,
+  0x93, 0x01, 0x60, 0xc0, 0x98, 0x40, 0x94, 0x9c, 0x3e, 0x57, 0x41, 0xfb,
+  0x6c, 0x9e, 0x3e, 0x40, 0x9a, 0x40, 0x74, 0x41, 0x31, 0x24, 0x9e, 0x3e,
+  0x73, 0x3d, 0xfe, 0x67, 0x42, 0xfb, 0xc0, 0xb6, 0x1d, 0xa8, 0x98, 0x40,
+  0x6b, 0xf7, 0x7f, 0xa3, 0x03, 0x90, 0xc0, 0xb6, 0x1d, 0x5b, 0xf7, 0x7f,
+  0x8f, 0x23, 0x80, 0x08, 0x43, 0x24, 0x2e, 0x40, 0x20, 0x44, 0x42, 0x31,
+  0xc0, 0x40, 0x2b, 0x03, 0x44, 0xd0, 0x8c, 0x00, 0x3a, 0x20, 0x9a, 0x40,
+  0x2a, 0x00, 0x60, 0x03, 0x94, 0xf2, 0x6c, 0x01, 0x3a, 0x0e, 0x00, 0x60,
+  0xac, 0x00, 0x3a, 0x0e, 0x00, 0x60, 0xef, 0x46, 0x00, 0x0f, 0x00, 0x60,
+  0xef, 0x4a, 0x00, 0x03, 0x94, 0xf2, 0x0b, 0xc8, 0xf2, 0x80, 0xb4, 0x1d,
+  0xb3, 0x0b, 0x90, 0x07, 0xf7, 0x7f, 0xa3, 0x03, 0x90, 0x83, 0x33, 0x80,
+  0x46, 0x43, 0x20, 0xf3, 0xf6, 0x7f, 0x93, 0x23, 0x80, 0x0c, 0x43, 0x24,
+  0x43, 0x52, 0xd8, 0xcc, 0x24, 0x3a, 0x2a, 0x00, 0x60, 0x67, 0x96, 0xf2,
+  0x6c, 0x25, 0x3a, 0x0e, 0x00, 0x60, 0xec, 0x24, 0x3a, 0x0e, 0x00, 0x60,
+  0x03, 0x44, 0x00, 0x0f, 0x00, 0x60, 0x03, 0x48, 0x00, 0x67, 0x96, 0xf2,
+  0xec, 0x42, 0x2b, 0xc3, 0x42, 0xfb, 0x84, 0x42, 0x31, 0x4f, 0xce, 0xf2,
+  0x8b, 0x3e, 0xfe, 0x27, 0x3c, 0xfe, 0x00, 0x40, 0x31, 0x50, 0x4a, 0x24,
+  0x08, 0x48, 0x24, 0x64, 0x46, 0x24, 0x00, 0x44, 0x24, 0x67, 0x8a, 0xf2,
+  0x04, 0x41, 0x31, 0x47, 0xa4, 0xf2, 0x8c, 0x04, 0x3a, 0x01, 0x01, 0x00,
+  0x0b, 0x00, 0x00, 0x03, 0x88, 0xf9, 0x6c, 0x40, 0x31, 0xc3, 0x82, 0xf2,
+  0x44, 0x40, 0x2b, 0x13, 0x3d, 0xfe, 0x2c, 0x0c, 0x3a, 0x47, 0x90, 0xf2,
+  0x16, 0x00, 0x60, 0xec, 0x00, 0x48, 0x26, 0x00, 0x60, 0x4c, 0x20, 0x3a,
+  0x1e, 0x00, 0x60, 0x4b, 0xe8, 0xf2, 0xac, 0x04, 0x3a, 0x17, 0xd4, 0xf2,
+  0x03, 0x00, 0xfd, 0x43, 0xc1, 0xf2, 0x86, 0x40, 0x20, 0x07, 0xc6, 0xf2,
+  0x6c, 0x20, 0x3a, 0xc3, 0xc0, 0xf2, 0x0f, 0x00, 0xfd, 0x03, 0xcc, 0xf2,
+  0x1c, 0x9c, 0x40, 0x44, 0x98, 0x3e, 0xcb, 0x45, 0xfb, 0x0c, 0x98, 0x3e,
+  0x80, 0x8c, 0x1d, 0x17, 0x8c, 0xe5, 0x03, 0x10, 0xe5, 0x14, 0x7c, 0x27,
+  0x58, 0x7c, 0x27, 0x03, 0xd4, 0xfa, 0x47, 0xd8, 0xfa, 0x03, 0xd4, 0xf2,
+  0x47, 0xd8, 0xf2, 0xdc, 0x83, 0x62, 0x47, 0xd4, 0xfa, 0x47, 0xd4, 0xf2,
+  0x57, 0xd9, 0xfa, 0x03, 0xd4, 0xfa, 0x03, 0xd4, 0xf2, 0x07, 0x14, 0xe5,
+  0x4b, 0x24, 0xfe, 0x50, 0x04, 0xc8, 0x8a, 0x4c, 0x20, 0x8b, 0x04, 0x00,
+  0x52, 0x40, 0x20, 0x04, 0x88, 0x3e, 0x8c, 0x80, 0x25, 0x00, 0x8c, 0x40,
+  0x10, 0x08, 0xca, 0x00, 0x50, 0x1e, 0x00, 0x3c, 0x23, 0x04, 0x00, 0x64,
+  0xb0, 0xc7, 0xc9, 0x47, 0x00, 0x80, 0xa0, 0xc7, 0xc9, 0x07, 0x00, 0xfe,
+  0x0f, 0x44, 0x00, 0x48, 0x04, 0x5e, 0xc4, 0x48, 0x78, 0x84, 0x00, 0x66,
+  0xf6, 0xbf, 0x7f, 0x00, 0x3c, 0x23, 0x8c, 0x00, 0x64, 0x01, 0x00, 0x00,
+  0xcf, 0x01, 0xfe, 0x01, 0x04, 0x00, 0x8c, 0x05, 0x64, 0x01, 0x00, 0x00,
+  0x6f, 0x01, 0xfe, 0x4b, 0xc3, 0xfe, 0x63, 0xc3, 0xfe, 0x67, 0xc3, 0xfe,
+  0x8f, 0x03, 0x80, 0x83, 0x13, 0x80, 0xbb, 0x23, 0x00, 0xc0, 0x00, 0x86,
+  0x02, 0xbc, 0x9f, 0x00, 0x3c, 0x23, 0xa0, 0xcf, 0x7b, 0x67, 0xc3, 0xfe,
+  0x63, 0xc3, 0xfe, 0xa7, 0x1f, 0xfe, 0xe7, 0x1f, 0xfe
+};
+const unsigned char pmcdata[] = {
+  0xb0, 0x09, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x0c, 0x00, 0x00, 0x00, 0x80, 0x05, 0x00, 0x00, 0x78, 0x05, 0x00, 0x04,
+  0x30, 0x00, 0x00, 0x00, 0x28, 0x05, 0x00, 0x00, 0x74, 0x05, 0x00, 0x04,
+  0x04, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x04,
+  0x1c, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00,
+  0xb8, 0x09, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x40, 0x40, 0x40, 0x46, 0x41, 0x49, 0x4c, 0x45, 0x44, 0x00, 0x40, 0x40,
+  0x40, 0x50, 0x41, 0x53, 0x53, 0x45, 0x44, 0x00, 0x73, 0x63, 0x72, 0x61,
+  0x74, 0x63, 0x68, 0x3a, 0x20, 0x30, 0x78, 0x25, 0x30, 0x38, 0x78, 0x0a,
+  0x00, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41,
+  0x42, 0x43, 0x44, 0x45, 0x46, 0x00, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+  0x36, 0x37, 0x38, 0x39, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x00, 0x28,
+  0x6e, 0x75, 0x6c, 0x6c, 0x29, 0x00, 0x00, 0x00, 0x5c, 0x16, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xa6, 0x1a, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xfb, 0x19, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0x63, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0x0f, 0x18, 0x0c, 0x00,
+  0x27, 0x1b, 0x0c, 0x00, 0xc6, 0x1b, 0x0c, 0x00, 0xa5, 0x18, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xa6, 0x1a, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0x4f, 0x17, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0x74, 0x19, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xeb, 0x1a, 0x0c, 0x00, 0xfb, 0x19, 0x0c, 0x00, 0x25, 0x30, 0x34, 0x75,
+  0x3a, 0x20, 0x00, 0x52, 0x4f, 0x20, 0x53, 0x56, 0x54, 0x20, 0x25, 0x64,
+  0x20, 0x48, 0x56, 0x54, 0x20, 0x25, 0x64, 0x20, 0x4c, 0x56, 0x54, 0x20,
+  0x25, 0x64, 0x0a, 0x00, 0x50, 0x4d, 0x43, 0x5f, 0x56, 0x45, 0x52, 0x3a,
+  0x25, 0x64, 0x2e, 0x25, 0x64, 0x2e, 0x25, 0x64, 0x0a, 0x00, 0x32, 0x30,
+  0x30, 0x36, 0x32, 0x38, 0x5f, 0x31, 0x34, 0x32, 0x38, 0x00, 0x54, 0x53,
+  0x3a, 0x25, 0x73, 0x0a, 0x00, 0x43, 0x48, 0x49, 0x44, 0x3a, 0x25, 0x78,
+  0x0a, 0x00, 0x43, 0x52, 0x45, 0x56, 0x3a, 0x25, 0x78, 0x0a, 0x00, 0x49,
+  0x6d, 0x61, 0x67, 0x65, 0x20, 0x69, 0x73, 0x20, 0x6e, 0x6f, 0x74, 0x20,
+  0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, 0x62, 0x6c, 0x65, 0x20, 0x77,
+  0x69, 0x74, 0x68, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x68, 0x69, 0x70,
+  0x0a, 0x00, 0x44, 0x41, 0x43, 0x3a, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x73,
+  0x6d, 0x61, 0x6c, 0x6c, 0x20, 0x73, 0x74, 0x65, 0x70, 0x20, 0x44, 0x41,
+  0x43, 0x3a, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x63, 0x75, 0x72, 0x5f, 0x64,
+  0x61, 0x63, 0x20, 0x25, 0x75, 0x20, 0x63, 0x75, 0x72, 0x56, 0x20, 0x25,
+  0x75, 0x20, 0x63, 0x75, 0x72, 0x54, 0x65, 0x6d, 0x70, 0x20, 0x25, 0x75,
+  0x20, 0x64, 0x65, 0x6c, 0x74, 0x61, 0x20, 0x25, 0x64, 0x20, 0x6e, 0x65,
+  0x77, 0x5f, 0x64, 0x61, 0x63, 0x20, 0x25, 0x75, 0x0a, 0x00, 0x41, 0x56,
+  0x53, 0x20, 0x44, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x0a, 0x00,
+  0x4d, 0x56, 0x41, 0x44, 0x43, 0x31, 0x20, 0x4d, 0x65, 0x61, 0x73, 0x75,
+  0x72, 0x65, 0x64, 0x20, 0x25, 0x75, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x75,
+  0x6c, 0x61, 0x74, 0x65, 0x64, 0x20, 0x25, 0x75, 0x0a, 0x00, 0x4d, 0x65,
+  0x61, 0x73, 0x75, 0x72, 0x65, 0x64, 0x20, 0x4d, 0x56, 0x41, 0x44, 0x43,
+  0x32, 0x20, 0x25, 0x75, 0x0a, 0x00, 0x4d, 0x56, 0x20, 0x44, 0x65, 0x6c,
+  0x74, 0x61, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x25, 0x64, 0x20, 0x64, 0x61,
+  0x63, 0x20, 0x64, 0x65, 0x6c, 0x74, 0x61, 0x20, 0x25, 0x75, 0x20, 0x4d,
+  0x56, 0x0a, 0x00, 0x4c, 0x56, 0x54, 0x00, 0x48, 0x56, 0x54, 0x00, 0x64,
+  0x65, 0x76, 0x20, 0x61, 0x64, 0x64, 0x72, 0x20, 0x30, 0x78, 0x25, 0x78,
+  0x20, 0x52, 0x4f, 0x20, 0x74, 0x79, 0x70, 0x65, 0x20, 0x53, 0x56, 0x54,
+  0x20, 0x76, 0x61, 0x6c, 0x75, 0x65, 0x20, 0x25, 0x75, 0x20, 0x52, 0x4f,
+  0x20, 0x74, 0x79, 0x70, 0x65, 0x20, 0x25, 0x73, 0x20, 0x76, 0x61, 0x6c,
+  0x75, 0x65, 0x20, 0x25, 0x75, 0x0a, 0x00, 0x55, 0x6e, 0x6b, 0x6e, 0x6f,
+  0x77, 0x6e, 0x00, 0x53, 0x56, 0x54, 0x00, 0x43, 0x61, 0x6c, 0x63, 0x75,
+  0x6c, 0x61, 0x74, 0x65, 0x64, 0x20, 0x53, 0x69, 0x67, 0x6d, 0x61, 0x20,
+  0x66, 0x6f, 0x72, 0x20, 0x25, 0x73, 0x20, 0x52, 0x4f, 0x3a, 0x20, 0x25,
+  0x64, 0x0a, 0x00, 0x53, 0x65, 0x74, 0x74, 0x69, 0x6e, 0x67, 0x20, 0x54,
+  0x68, 0x65, 0x73, 0x68, 0x6f, 0x6c, 0x64, 0x73, 0x20, 0x66, 0x6f, 0x72,
+  0x20, 0x25, 0x64, 0x20, 0x68, 0x69, 0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f,
+  0x20, 0x25, 0x64, 0x0a, 0x00, 0x44, 0x75, 0x6d, 0x70, 0x20, 0x61, 0x6c,
+  0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73, 0x20, 0x6f, 0x6e, 0x20, 0x68, 0x69,
+  0x67, 0x68, 0x20, 0x56, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x44, 0x75, 0x6d,
+  0x70, 0x20, 0x61, 0x6c, 0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73, 0x20, 0x6f,
+  0x6e, 0x20, 0x6c, 0x6f, 0x77, 0x20, 0x56, 0x20, 0x25, 0x64, 0x0a, 0x00,
+  0x52, 0x4f, 0x5b, 0x25, 0x64, 0x5d, 0x20, 0x74, 0x61, 0x72, 0x67, 0x65,
+  0x74, 0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f, 0x77, 0x5f, 0x72, 0x6f, 0x20,
+  0x25, 0x64, 0x20, 0x73, 0x6c, 0x6f, 0x70, 0x65, 0x20, 0x25, 0x64, 0x20,
+  0x76, 0x6c, 0x6f, 0x77, 0x20, 0x25, 0x64, 0x20, 0x4d, 0x56, 0x20, 0x5b,
+  0x25, 0x64, 0x5d, 0x20, 0x76, 0x68, 0x69, 0x67, 0x68, 0x20, 0x25, 0x64,
+  0x20, 0x4d, 0x56, 0x20, 0x5b, 0x25, 0x64, 0x5d, 0x20, 0x76, 0x6f, 0x6c,
+  0x74, 0x61, 0x67, 0x65, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x61, 0x76, 0x73,
+  0x5f, 0x64, 0x61, 0x63, 0x20, 0x25, 0x64, 0x20, 0x76, 0x63, 0x6f, 0x6e,
+  0x76, 0x20, 0x25, 0x64, 0x6d, 0x56, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x75,
+  0x6c, 0x61, 0x74, 0x65, 0x64, 0x5f, 0x6d, 0x61, 0x72, 0x67, 0x69, 0x6e,
+  0x20, 0x25, 0x64, 0x20, 0x6d, 0x56, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x5b,
+  0x25, 0x64, 0x5d, 0x6d, 0x56, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x68, 0x69,
+  0x67, 0x68, 0x20, 0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x6c, 0x6f,
+  0x77, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x41, 0x56, 0x53, 0x20, 0x43, 0x6c,
+  0x6f, 0x73, 0x65, 0x64, 0x20, 0x6f, 0x6e, 0x20, 0x64, 0x61, 0x63, 0x5f,
+  0x63, 0x6f, 0x64, 0x65, 0x20, 0x25, 0x64, 0x20, 0x43, 0x61, 0x6c, 0x63,
+  0x69, 0x6c, 0x61, 0x74, 0x65, 0x64, 0x20, 0x25, 0x64, 0x20, 0x4d, 0x56,
+  0x20, 0x74, 0x61, 0x72, 0x67, 0x65, 0x74, 0x20, 0x25, 0x64, 0x20, 0x4d,
+  0x56, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x75, 0x6c, 0x61, 0x74, 0x65, 0x64,
+  0x20, 0x64, 0x61, 0x63, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x44, 0x75, 0x6d,
+  0x70, 0x20, 0x61, 0x6c, 0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73, 0x20, 0x6f,
+  0x6e, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x0a, 0x00, 0x00,
+  0x01, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x04, 0x04, 0x04, 0x04, 0x04,
+  0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
+  0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x06, 0x06, 0x06, 0x06, 0x06,
+  0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06,
+  0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06,
+  0x06, 0x06, 0x06, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
+  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
+  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
+  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
+  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
+  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x00, 0x92, 0x5e, 0x84, 0x4e, 0x00, 0x00, 0x00, 0x00,
+  0x23, 0x07, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+  0xc8, 0x09, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00
+};
+#endif //PMC_ROMDATA_68460_H
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_firmware_68560.h b/arch/arm/mach-bcmbca/pmc/pmc_firmware_68560.h
new file mode 100644
index 0000000000..1b69d5f1ef
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_firmware_68560.h
@@ -0,0 +1,2471 @@
+/*
+ * * <:copyright-BRCM:2017:DUAL/GPL:standard
+ * * 
+ * *    Copyright (c) 2017 Broadcom 
+ * *    All Rights Reserved
+ * * 
+ * * This program is free software; you can redistribute it and/or modify
+ * * it under the terms of the GNU General Public License, version 2, as published by
+ * * the Free Software Foundation (the "GPL").
+ * * 
+ * * This program is distributed in the hope that it will be useful,
+ * * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * * GNU General Public License for more details.
+ * * 
+ * * 
+ * * A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+ * * writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+ * * Boston, MA 02111-1307, USA.
+ * * 
+ * * :>
+ * */
+
+#ifndef PMC_ROMDATA_68560_H
+#define PMC_ROMDATA_68560_H
+#define CFG_BOOT_PMC3_START_ADDR 0xc0000
+#define CFG_BOOT_PMC3_DATA_ADDR 0x4000000
+#define PMC_VER_IMPL 3
+#define PMC_VER_MAJOR 4
+#define PMC_VER_MINOR 1
+const unsigned char pmcappdata[] = {
+  0x01, 0x00, 0x00, 0x07, 0x12, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x08, 0xe5, 0x00,
+  0x00, 0x64, 0x18, 0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xdc, 0xf7, 0x63, 0x00,
+  0x00, 0x64, 0x20, 0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xec, 0xf3, 0x63, 0x1f,
+  0x00, 0x60, 0x40, 0x00, 0x65, 0x5b, 0x02, 0xf2, 0xfd, 0xff, 0x81, 0xc0,
+  0xff, 0x64, 0x33, 0x02, 0xf2, 0x67, 0xc3, 0xfe, 0x00, 0x00, 0x64, 0x18,
+  0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xe8, 0xeb, 0x63, 0xfd, 0xff, 0x00, 0xd4,
+  0xff, 0x64, 0x55, 0xd5, 0xff, 0x4b, 0x55, 0x45, 0xc8, 0xc8, 0xfc, 0x01,
+  0x00, 0x00, 0xcc, 0xeb, 0x63, 0x00, 0x00, 0x64, 0x20, 0x00, 0xc8, 0x03,
+  0x0c, 0xe5, 0xfd, 0xf3, 0xff, 0x37, 0x1c, 0xfe, 0x07, 0x0c, 0xe5, 0x03,
+  0x00, 0x80, 0x00, 0x3c, 0x23, 0x0f, 0x20, 0xe5, 0x08, 0x00, 0x64, 0x04,
+  0x04, 0x64, 0x00, 0x0c, 0x64, 0x01, 0x00, 0x00, 0xcc, 0x8b, 0x63, 0x01,
+  0x00, 0x04, 0x00, 0x01, 0x64, 0xd8, 0xff, 0x63, 0x04, 0x00, 0x66, 0x2e,
+  0x00, 0x60, 0x00, 0x0c, 0x64, 0x08, 0x00, 0x64, 0x04, 0x08, 0x64, 0x01,
+  0x00, 0x00, 0xd4, 0x83, 0x63, 0x01, 0x0c, 0x00, 0x00, 0x08, 0x64, 0x50,
+  0x01, 0xc8, 0xe8, 0xf3, 0x63, 0xa3, 0x00, 0x60, 0xd4, 0x00, 0x64, 0x01,
+  0x00, 0x04, 0x18, 0x04, 0x64, 0x34, 0x14, 0x72, 0x14, 0x01, 0x64, 0x01,
+  0x00, 0x04, 0x18, 0x0d, 0x74, 0x9c, 0x14, 0x72, 0xbb, 0xbf, 0x7f, 0x82,
+  0x41, 0x20, 0xfc, 0xf7, 0x63, 0x22, 0x40, 0x20, 0x83, 0x11, 0x00, 0xf0,
+  0xf7, 0x63, 0xa3, 0x03, 0x90, 0x83, 0x21, 0x00, 0xe4, 0xf7, 0x63, 0x87,
+  0x23, 0x80, 0x0a, 0x40, 0x20, 0x02, 0x42, 0x20, 0xdf, 0x05, 0x00, 0xfc,
+  0x8f, 0x62, 0x6c, 0x1d, 0x3a, 0x9b, 0x31, 0x00, 0xc6, 0xbf, 0x7f, 0xaf,
+  0xbf, 0x7f, 0x82, 0x41, 0x20, 0xf8, 0xf3, 0x63, 0x22, 0x40, 0x20, 0x83,
+  0x11, 0x00, 0xec, 0xf3, 0x63, 0x0a, 0x40, 0x20, 0x03, 0x02, 0x50, 0xe0,
+  0x8f, 0x62, 0xdf, 0x05, 0x00, 0x6c, 0x1d, 0x3a, 0x9b, 0x21, 0x00, 0xd6,
+  0xbf, 0x7f, 0x43, 0xbf, 0x7f, 0x01, 0x00, 0x04, 0x00, 0x02, 0x64, 0xc0,
+  0xf3, 0x63, 0x1a, 0x40, 0x20, 0x01, 0x00, 0x04, 0x00, 0x03, 0x64, 0xf0,
+  0xef, 0x63, 0x1e, 0x40, 0x20, 0x08, 0x00, 0x64, 0x00, 0x0c, 0x64, 0x04,
+  0x0c, 0x64, 0x05, 0x00, 0x00, 0x14, 0x60, 0x55, 0x01, 0x00, 0x00, 0xd0,
+  0xd7, 0x62, 0x01, 0x0c, 0x00, 0x40, 0x79, 0x64, 0x20, 0x00, 0xc8, 0x4a,
+  0x41, 0x20, 0x80, 0x9d, 0x1d, 0xd0, 0x8b, 0x62, 0x00, 0x0c, 0x64, 0x08,
+  0x00, 0x64, 0x04, 0x0e, 0x64, 0x01, 0x00, 0x00, 0xcc, 0xcf, 0x62, 0x00,
+  0x00, 0x64, 0x18, 0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xfc, 0x9b, 0x63, 0x00,
+  0x0c, 0x64, 0x8a, 0x41, 0x20, 0x04, 0x10, 0x64, 0x01, 0x00, 0x00, 0xe0,
+  0xc7, 0x62, 0x00, 0x00, 0x64, 0x28, 0x00, 0xc8, 0x4a, 0x41, 0x20, 0x80,
+  0x9d, 0x1d, 0xfd, 0xf3, 0xff, 0xf8, 0x93, 0x63, 0x4a, 0x41, 0x20, 0x80,
+  0x9d, 0x1d, 0x01, 0x00, 0x00, 0xc8, 0xc7, 0x62, 0x88, 0x08, 0x31, 0x18,
+  0x08, 0xca, 0x48, 0x10, 0x5a, 0x10, 0x08, 0x7a, 0x00, 0x3c, 0x23, 0x0c,
+  0x00, 0x64, 0x4c, 0xcc, 0x1e, 0x84, 0x08, 0x31, 0x10, 0x04, 0xca, 0x10,
+  0x0c, 0x7a, 0x00, 0x3c, 0x23, 0x03, 0x08, 0xe6, 0x05, 0x00, 0x00, 0x00,
+  0x62, 0x52, 0x04, 0x00, 0x66, 0x52, 0x00, 0x60, 0x09, 0x00, 0x00, 0x00,
+  0x70, 0x55, 0x18, 0x05, 0x64, 0x44, 0x00, 0x72, 0x83, 0x05, 0x40, 0x09,
+  0x00, 0x00, 0x04, 0xc2, 0x80, 0x05, 0x00, 0x00, 0x00, 0x64, 0x55, 0x69,
+  0x00, 0x00, 0xec, 0x87, 0x63, 0x05, 0x00, 0x00, 0x00, 0x64, 0x55, 0x86,
+  0x41, 0x20, 0x69, 0x00, 0x00, 0xf0, 0x83, 0x63, 0x40, 0x00, 0x64, 0x05,
+  0x00, 0x00, 0x44, 0xc0, 0x7e, 0x07, 0x0c, 0xe6, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0xdc, 0x93, 0x62, 0x00, 0x04, 0x64, 0x04, 0x04, 0x64, 0x08, 0x00, 0x64,
+  0x93, 0x40, 0x60, 0x01, 0x00, 0x04, 0x38, 0x00, 0x55, 0xba, 0x4f, 0x00,
+  0xcd, 0xab, 0x89, 0xc8, 0x7b, 0x64, 0x45, 0x23, 0x01, 0xcc, 0x59, 0x64,
+  0x05, 0x00, 0x00, 0x00, 0x6c, 0x64, 0x86, 0x43, 0x20, 0xd0, 0x87, 0x62,
+  0xbb, 0x63, 0x00, 0x80, 0x03, 0xe6, 0x00, 0x04, 0x64, 0x04, 0x06, 0x64,
+  0x08, 0x00, 0x64, 0x4f, 0x40, 0x60, 0x04, 0x00, 0x64, 0x4c, 0x04, 0x48,
+  0xc3, 0x07, 0xf6, 0x3b, 0x00, 0xf2, 0x00, 0x04, 0x64, 0x04, 0x08, 0x64,
+  0x08, 0x00, 0x64, 0x2f, 0x40, 0x60, 0x83, 0xc2, 0xfe, 0x02, 0x60, 0x07,
+  0x03, 0x78, 0xfe, 0xfd, 0xff, 0xff, 0x37, 0x0f, 0xfe, 0x47, 0xc0, 0xf2,
+  0x44, 0x0c, 0x31, 0x10, 0x04, 0xca, 0x08, 0x08, 0xe8, 0x00, 0x3c, 0x23,
+  0x00, 0x20, 0x2b, 0x03, 0x44, 0xfb, 0x83, 0x40, 0xf1, 0x09, 0x00, 0x00,
+  0x84, 0xc1, 0x80, 0x05, 0x12, 0x00, 0x84, 0x40, 0x80, 0x00, 0x3c, 0x23,
+  0x03, 0x18, 0xe5, 0x18, 0x84, 0x1d, 0x96, 0x40, 0x20, 0x00, 0x0c, 0x64,
+  0x08, 0x00, 0x64, 0x04, 0x14, 0x64, 0xc8, 0xff, 0x63, 0x00, 0x00, 0x64,
+  0x18, 0x00, 0xc8, 0xfd, 0xf3, 0xff, 0xd4, 0xc7, 0x62, 0x8a, 0x41, 0x20,
+  0x00, 0x14, 0x74, 0xec, 0xfb, 0x63, 0x80, 0x9d, 0x1d, 0x4a, 0x41, 0x20,
+  0xa3, 0x6c, 0x60, 0x1a, 0x40, 0x20, 0x0a, 0x40, 0x20, 0x00, 0x1c, 0x74,
+  0xd0, 0xfb, 0x63, 0x82, 0x41, 0x20, 0xe4, 0xdf, 0x62, 0x08, 0x00, 0x74,
+  0xc0, 0x3f, 0x64, 0x00, 0x08, 0x1d, 0x14, 0x00, 0x64, 0x50, 0x37, 0x64,
+  0x44, 0x09, 0x1e, 0x57, 0x05, 0x00, 0x13, 0x45, 0x00, 0xec, 0xd3, 0x73,
+  0x88, 0x03, 0x64, 0x0b, 0x0b, 0xf2, 0x9f, 0x01, 0xf2, 0xc7, 0x01, 0xf2,
+  0xef, 0x01, 0xf2, 0x17, 0x02, 0xf2, 0x3f, 0x02, 0xf2, 0x67, 0x02, 0xf2,
+  0xe7, 0x41, 0xf2, 0xff, 0x40, 0xf2, 0x87, 0x03, 0xf2, 0xcf, 0x41, 0xf2,
+  0x48, 0x00, 0x64, 0x73, 0x0a, 0xf2, 0x48, 0x00, 0x64, 0xf3, 0x0a, 0xf2,
+  0x88, 0xc4, 0x64, 0xc3, 0x4a, 0xf2, 0x05, 0x0c, 0x00, 0x08, 0x29, 0x64,
+  0xb3, 0x0a, 0xf2, 0x05, 0x0c, 0x00, 0x08, 0x14, 0x64, 0xbb, 0x0a, 0xf2,
+  0x05, 0x0c, 0x00, 0x88, 0x1e, 0x64, 0xc3, 0x0a, 0xf2, 0x05, 0x0c, 0x00,
+  0x88, 0x33, 0x64, 0xcb, 0x0a, 0xf2, 0x05, 0x0c, 0x00, 0x08, 0x3e, 0x64,
+  0xd3, 0x0a, 0xf2, 0x05, 0x0c, 0x00, 0x88, 0x54, 0x64, 0xdb, 0x0a, 0xf2,
+  0x05, 0x0c, 0x00, 0x48, 0x55, 0x64, 0xe3, 0x0a, 0xf2, 0x01, 0x0c, 0x00,
+  0x8c, 0x08, 0x64, 0x6d, 0x0c, 0x00, 0x08, 0x18, 0x64, 0x1b, 0x0f, 0xf2,
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+  0x2a, 0x00, 0x60, 0x03, 0x8c, 0xf2, 0x4c, 0x00, 0x3a, 0x0e, 0x00, 0x60,
+  0xcc, 0x00, 0x3a, 0x0e, 0x00, 0x60, 0x9b, 0x45, 0x00, 0x0f, 0x00, 0x60,
+  0x9b, 0x49, 0x00, 0x03, 0x8c, 0xf2, 0x83, 0x4f, 0x90, 0x37, 0xc4, 0xf2,
+  0x40, 0xb3, 0x1d, 0xdc, 0xbf, 0x63, 0xa3, 0x03, 0x90, 0x40, 0xb3, 0x1d,
+  0xcc, 0xbf, 0x63, 0x8b, 0x23, 0x80, 0xa8, 0x42, 0x24, 0xc3, 0x49, 0xd8,
+  0x8c, 0x1e, 0x3a, 0x2e, 0x00, 0x60, 0x8f, 0x43, 0x80, 0xdf, 0x8d, 0xf2,
+  0xec, 0x1c, 0x3a, 0x0e, 0x00, 0x60, 0xac, 0x1e, 0x3a, 0x0e, 0x00, 0x60,
+  0x03, 0x44, 0x00, 0x0f, 0x00, 0x60, 0x03, 0x48, 0x00, 0xdf, 0x8d, 0xf2,
+  0x98, 0x41, 0x2b, 0x93, 0x41, 0xfb, 0xc8, 0x42, 0x31, 0x03, 0x3d, 0xfe,
+  0x04, 0x41, 0x31, 0xcf, 0x3e, 0xfe, 0x18, 0x4c, 0x24, 0x4c, 0x4c, 0x24,
+  0x00, 0x48, 0x24, 0x44, 0x48, 0x24, 0x03, 0x8c, 0xf2, 0x88, 0x41, 0x31,
+  0x8b, 0x80, 0xf2, 0xcc, 0x08, 0x3a, 0x01, 0x01, 0x00, 0x4f, 0x00, 0x00,
+  0x47, 0x8c, 0xf9, 0x8c, 0x40, 0x31, 0xdf, 0xe9, 0xf2, 0xc7, 0x84, 0xf2,
+  0x6c, 0x1c, 0x3a, 0x26, 0x00, 0x60, 0x88, 0x40, 0x2b, 0x9b, 0x3d, 0xfe,
+  0x20, 0x96, 0x40, 0x8b, 0x98, 0xf2, 0x8c, 0x20, 0x3a, 0x12, 0x00, 0x60,
+  0xec, 0x05, 0x48, 0x0a, 0x00, 0x60, 0x13, 0x45, 0x00, 0x14, 0x00, 0x64,
+  0x08, 0x95, 0x1d, 0x80, 0x8c, 0x1d, 0x1f, 0x8c, 0xe5, 0x13, 0x88, 0xe5,
+  0x20, 0x84, 0x1d, 0x98, 0x8c, 0x1d, 0x16, 0x40, 0x20, 0x6a, 0x42, 0x20,
+  0xac, 0x4d, 0x72, 0x8c, 0x24, 0x3a, 0x06, 0x01, 0x60, 0xfd, 0x00, 0x00,
+  0xbc, 0x7c, 0xb7, 0x12, 0x00, 0x60, 0xbc, 0x3c, 0xae, 0xde, 0x20, 0x80,
+  0x17, 0x00, 0x60, 0xfd, 0xff, 0x00, 0xbc, 0x7c, 0xaf, 0x1c, 0x04, 0x64,
+  0xde, 0xa1, 0x80, 0x80, 0x9c, 0x3e, 0x05, 0x00, 0x00, 0x06, 0x1c, 0xe1,
+  0x47, 0x9c, 0xf2, 0x1c, 0x08, 0x64, 0xdf, 0xc5, 0xf2, 0x30, 0x1c, 0xc8,
+  0x68, 0x9e, 0x40, 0x04, 0x86, 0x3e, 0x98, 0x9c, 0x40, 0x6b, 0x68, 0xfb,
+  0x14, 0x9e, 0x40, 0xac, 0x41, 0x31, 0x80, 0xae, 0x1d, 0xc4, 0xab, 0x63,
+  0xa3, 0x03, 0x90, 0x80, 0xae, 0x1d, 0xf4, 0xa7, 0x63, 0x8b, 0x23, 0x80,
+  0xa7, 0x3d, 0xfe, 0x44, 0x41, 0x31, 0x40, 0x42, 0x24, 0x88, 0x40, 0x2b,
+  0x83, 0x44, 0xd0, 0x0c, 0x08, 0x3a, 0x22, 0x00, 0x60, 0x8b, 0x98, 0xf2,
+  0x0c, 0x88, 0x3a, 0x8f, 0x98, 0xf2, 0xac, 0x09, 0x3a, 0x86, 0x40, 0x20,
+  0x8b, 0xcc, 0xf9, 0x4b, 0x88, 0xf9, 0x8b, 0xc0, 0xf2, 0x80, 0xac, 0x1d,
+  0xa3, 0x0b, 0x90, 0xec, 0xa3, 0x63, 0x22, 0x40, 0x20, 0x83, 0x23, 0x80,
+  0xc6, 0x42, 0x20, 0xd8, 0xa3, 0x63, 0x46, 0x41, 0x20, 0x40, 0x42, 0x24,
+  0x43, 0x60, 0xd8, 0x0c, 0x04, 0x3a, 0xde, 0x01, 0x60, 0x47, 0x98, 0xf2,
+  0xac, 0x85, 0x3a, 0x5b, 0x98, 0xf2, 0x0c, 0x04, 0x3a, 0x4a, 0x40, 0x20,
+  0x47, 0xd8, 0xf9, 0x87, 0x84, 0xf9, 0xbf, 0x01, 0x60, 0x24, 0x08, 0x72,
+  0x40, 0x00, 0x74, 0xd8, 0x9f, 0x63, 0x1a, 0x40, 0x20, 0xfd, 0x00, 0x00,
+  0xbc, 0x7d, 0xb7, 0x12, 0x00, 0x60, 0xbc, 0x3d, 0xae, 0xde, 0x21, 0x80,
+  0x17, 0x00, 0x60, 0xfd, 0xff, 0x00, 0xbc, 0x7d, 0xaf, 0x1c, 0x04, 0x64,
+  0xde, 0xa1, 0x80, 0x80, 0x9d, 0x3e, 0x05, 0x00, 0x00, 0x2a, 0x1c, 0xe1,
+  0x6f, 0xda, 0xf2, 0xab, 0x9e, 0xf2, 0x1c, 0x08, 0x64, 0xdf, 0xe9, 0xf2,
+  0x88, 0x1d, 0xc8, 0x70, 0xaa, 0x3e, 0x98, 0x9d, 0x40, 0x44, 0x9e, 0x40,
+  0x28, 0xaa, 0x3e, 0xa7, 0x46, 0xfb, 0xa8, 0x41, 0x31, 0x00, 0xab, 0x1d,
+  0xf0, 0x97, 0x63, 0xa3, 0x03, 0x90, 0x00, 0xab, 0x1d, 0xe0, 0x97, 0x63,
+  0x8b, 0x23, 0x80, 0xaf, 0x3d, 0xfe, 0x44, 0x42, 0x31, 0xc0, 0x42, 0x24,
+  0x88, 0x40, 0x2b, 0x83, 0x44, 0xd0, 0x0c, 0x08, 0x3a, 0x14, 0x9e, 0x40,
+  0x22, 0x00, 0x60, 0x8b, 0x98, 0xf2, 0x0c, 0x88, 0x3a, 0x8f, 0x98, 0xf2,
+  0xac, 0x09, 0x3a, 0x86, 0x40, 0x20, 0x8b, 0xcc, 0xf9, 0x4b, 0x88, 0xf9,
+  0x8b, 0xc0, 0xf2, 0x80, 0xa8, 0x1d, 0xa3, 0x0b, 0x90, 0xd4, 0x93, 0x63,
+  0x22, 0x40, 0x20, 0x83, 0x23, 0x80, 0x86, 0x42, 0x20, 0xc0, 0x93, 0x63,
+  0x46, 0x42, 0x20, 0xec, 0x42, 0x24, 0x43, 0x60, 0xd8, 0xcc, 0x06, 0x3a,
+  0x22, 0x00, 0x60, 0x47, 0x98, 0xf2, 0xcc, 0x86, 0x3a, 0x43, 0x98, 0xf2,
+  0xac, 0x05, 0x3a, 0x4a, 0x40, 0x20, 0x47, 0xc0, 0xf9, 0x87, 0x84, 0xf9,
+  0x6f, 0xec, 0xf2, 0xa8, 0x41, 0x31, 0xc0, 0xaa, 0x1d, 0xc4, 0x8f, 0x63,
+  0xa3, 0x03, 0x90, 0xc0, 0xaa, 0x1d, 0xf4, 0x8b, 0x63, 0x8b, 0x23, 0x80,
+  0xa7, 0x3d, 0xfe, 0x44, 0x41, 0x31, 0x40, 0x42, 0x24, 0x88, 0x40, 0x2b,
+  0x83, 0x44, 0xd0, 0x0c, 0x08, 0x3a, 0x22, 0x00, 0x60, 0x8b, 0x98, 0xf2,
+  0x0c, 0x88, 0x3a, 0x8f, 0x98, 0xf2, 0xac, 0x09, 0x3a, 0x86, 0x40, 0x20,
+  0x8b, 0xcc, 0xf9, 0x4b, 0x88, 0xf9, 0x8b, 0xc0, 0xf2, 0x80, 0xa8, 0x1d,
+  0xa3, 0x0b, 0x90, 0xec, 0x87, 0x63, 0x22, 0x40, 0x20, 0x83, 0x23, 0x80,
+  0x86, 0x42, 0x20, 0xd8, 0x87, 0x63, 0x46, 0x41, 0x20, 0x40, 0x42, 0x24,
+  0x43, 0x60, 0xd8, 0x0c, 0x04, 0x3a, 0x1e, 0x00, 0x60, 0x47, 0x98, 0xf2,
+  0xac, 0x85, 0x3a, 0x5b, 0x98, 0xf2, 0x0c, 0x04, 0x3a, 0x5b, 0xd8, 0xf9,
+  0x47, 0x98, 0xf9, 0x47, 0xc0, 0xf2, 0x48, 0x9c, 0x3e, 0x0c, 0x00, 0x64,
+  0x1b, 0x02, 0x60, 0xcc, 0x24, 0x3a, 0x0e, 0x00, 0x60, 0x08, 0xa4, 0x1d,
+  0x0b, 0x02, 0x60, 0xfd, 0x00, 0x00, 0xfc, 0x7c, 0xb7, 0x16, 0x00, 0x60,
+  0xfc, 0x3c, 0xae, 0x1c, 0x00, 0x64, 0xde, 0x21, 0x80, 0x17, 0x00, 0x60,
+  0xfd, 0xff, 0x00, 0xfc, 0x7c, 0xaf, 0x1c, 0x04, 0x64, 0xde, 0xa1, 0x80,
+  0xc0, 0x9c, 0x3e, 0x05, 0x00, 0x00, 0x02, 0x1c, 0xe1, 0x18, 0x08, 0x64,
+  0x1f, 0x9c, 0xf2, 0x9b, 0xdd, 0xf2, 0x6c, 0x18, 0x72, 0x6c, 0x0e, 0x3a,
+  0x0e, 0x00, 0x60, 0xac, 0x20, 0x3a, 0x1e, 0x00, 0x60, 0x07, 0xca, 0xf2,
+  0x6c, 0x20, 0x3a, 0x6b, 0xce, 0xf2, 0x0b, 0x00, 0xfd, 0xab, 0xca, 0xf2,
+  0x56, 0x40, 0x20, 0x48, 0xa9, 0x1d, 0x93, 0x01, 0x60, 0xc0, 0x98, 0x40,
+  0x94, 0x9c, 0x3e, 0x57, 0x41, 0xfb, 0x6c, 0x9e, 0x3e, 0x40, 0x9a, 0x40,
+  0x74, 0x41, 0x31, 0x24, 0x9e, 0x3e, 0x73, 0x3d, 0xfe, 0x67, 0x42, 0xfb,
+  0xc0, 0xb6, 0x1d, 0xa8, 0x98, 0x40, 0x6b, 0xf7, 0x7f, 0xa3, 0x03, 0x90,
+  0xc0, 0xb6, 0x1d, 0x5b, 0xf7, 0x7f, 0x8f, 0x23, 0x80, 0x08, 0x43, 0x24,
+  0x2e, 0x40, 0x20, 0x44, 0x42, 0x31, 0xc0, 0x40, 0x2b, 0x03, 0x44, 0xd0,
+  0x8c, 0x00, 0x3a, 0x20, 0x9a, 0x40, 0x2a, 0x00, 0x60, 0x03, 0x94, 0xf2,
+  0x6c, 0x01, 0x3a, 0x0e, 0x00, 0x60, 0xac, 0x00, 0x3a, 0x0e, 0x00, 0x60,
+  0xef, 0x46, 0x00, 0x0f, 0x00, 0x60, 0xef, 0x4a, 0x00, 0x03, 0x94, 0xf2,
+  0x0b, 0xc8, 0xf2, 0x80, 0xb4, 0x1d, 0xb3, 0x0b, 0x90, 0x07, 0xf7, 0x7f,
+  0xa3, 0x03, 0x90, 0x83, 0x33, 0x80, 0x46, 0x43, 0x20, 0xf3, 0xf6, 0x7f,
+  0x93, 0x23, 0x80, 0x0c, 0x43, 0x24, 0x43, 0x52, 0xd8, 0xcc, 0x24, 0x3a,
+  0x2a, 0x00, 0x60, 0x67, 0x96, 0xf2, 0x6c, 0x25, 0x3a, 0x0e, 0x00, 0x60,
+  0xec, 0x24, 0x3a, 0x0e, 0x00, 0x60, 0x03, 0x44, 0x00, 0x0f, 0x00, 0x60,
+  0x03, 0x48, 0x00, 0x67, 0x96, 0xf2, 0xec, 0x42, 0x2b, 0xc3, 0x42, 0xfb,
+  0x84, 0x42, 0x31, 0x4f, 0xce, 0xf2, 0x8b, 0x3e, 0xfe, 0x27, 0x3c, 0xfe,
+  0x00, 0x40, 0x31, 0x50, 0x4a, 0x24, 0x08, 0x48, 0x24, 0x64, 0x46, 0x24,
+  0x00, 0x44, 0x24, 0x67, 0x8a, 0xf2, 0x04, 0x41, 0x31, 0x47, 0xa4, 0xf2,
+  0x8c, 0x04, 0x3a, 0x01, 0x01, 0x00, 0x0b, 0x00, 0x00, 0x03, 0x88, 0xf9,
+  0x6c, 0x40, 0x31, 0xc3, 0x82, 0xf2, 0x44, 0x40, 0x2b, 0x13, 0x3d, 0xfe,
+  0x2c, 0x0c, 0x3a, 0x47, 0x90, 0xf2, 0x16, 0x00, 0x60, 0xec, 0x00, 0x48,
+  0x26, 0x00, 0x60, 0x4c, 0x20, 0x3a, 0x1e, 0x00, 0x60, 0x4b, 0xe8, 0xf2,
+  0xac, 0x04, 0x3a, 0x17, 0xd4, 0xf2, 0x03, 0x00, 0xfd, 0x43, 0xc1, 0xf2,
+  0x86, 0x40, 0x20, 0x07, 0xc6, 0xf2, 0x6c, 0x20, 0x3a, 0xc3, 0xc0, 0xf2,
+  0x0f, 0x00, 0xfd, 0x03, 0xcc, 0xf2, 0x1c, 0x9c, 0x40, 0x44, 0x98, 0x3e,
+  0xcb, 0x45, 0xfb, 0x0c, 0x98, 0x3e, 0x80, 0x8c, 0x1d, 0x17, 0x8c, 0xe5,
+  0x03, 0x10, 0xe5, 0x14, 0x7c, 0x27, 0x58, 0x7c, 0x27, 0x03, 0xd4, 0xfa,
+  0x47, 0xd8, 0xfa, 0x03, 0xd4, 0xf2, 0x47, 0xd8, 0xf2, 0xdc, 0x83, 0x62,
+  0x47, 0xd4, 0xfa, 0x47, 0xd4, 0xf2, 0x57, 0xd9, 0xfa, 0x03, 0xd4, 0xfa,
+  0x03, 0xd4, 0xf2, 0x07, 0x14, 0xe5, 0x4b, 0x24, 0xfe, 0x50, 0x04, 0xc8,
+  0x8a, 0x4c, 0x20, 0x8b, 0x04, 0x00, 0x52, 0x40, 0x20, 0x04, 0x88, 0x3e,
+  0x8c, 0x80, 0x25, 0x00, 0x8c, 0x40, 0x10, 0x08, 0xca, 0x00, 0x50, 0x1e,
+  0x00, 0x3c, 0x23, 0x04, 0x00, 0x64, 0xb0, 0xc7, 0xc9, 0x47, 0x00, 0x80,
+  0xa0, 0xc7, 0xc9, 0x07, 0x00, 0xfe, 0x0f, 0x44, 0x00, 0x48, 0x04, 0x5e,
+  0xc4, 0x48, 0x78, 0x84, 0x00, 0x66, 0xf6, 0xbf, 0x7f, 0x00, 0x3c, 0x23,
+  0x8c, 0x00, 0x64, 0x01, 0x00, 0x00, 0xcf, 0x01, 0xfe, 0x01, 0x04, 0x00,
+  0x8c, 0x05, 0x64, 0x01, 0x00, 0x00, 0x6f, 0x01, 0xfe, 0x4b, 0xc3, 0xfe,
+  0x63, 0xc3, 0xfe, 0x67, 0xc3, 0xfe, 0x8f, 0x03, 0x80, 0x83, 0x13, 0x80,
+  0xbb, 0x23, 0x00, 0xc0, 0x00, 0x86, 0x02, 0xbc, 0x9f, 0x00, 0x3c, 0x23,
+  0xa0, 0xcf, 0x7b, 0x67, 0xc3, 0xfe, 0x63, 0xc3, 0xfe, 0xa7, 0x1f, 0xfe,
+  0xe7, 0x1f, 0xfe
+};
+const unsigned char pmcdata[] = {
+  0xb0, 0x09, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x0c, 0x00, 0x00, 0x00, 0x80, 0x05, 0x00, 0x00, 0x78, 0x05, 0x00, 0x04,
+  0x30, 0x00, 0x00, 0x00, 0x28, 0x05, 0x00, 0x00, 0x74, 0x05, 0x00, 0x04,
+  0x04, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x04,
+  0x1c, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00,
+  0xb8, 0x09, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x40, 0x40, 0x40, 0x46, 0x41, 0x49, 0x4c, 0x45, 0x44, 0x00, 0x40, 0x40,
+  0x40, 0x50, 0x41, 0x53, 0x53, 0x45, 0x44, 0x00, 0x73, 0x63, 0x72, 0x61,
+  0x74, 0x63, 0x68, 0x3a, 0x20, 0x30, 0x78, 0x25, 0x30, 0x38, 0x78, 0x0a,
+  0x00, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x41,
+  0x42, 0x43, 0x44, 0x45, 0x46, 0x00, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35,
+  0x36, 0x37, 0x38, 0x39, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x00, 0x28,
+  0x6e, 0x75, 0x6c, 0x6c, 0x29, 0x00, 0x00, 0x00, 0x5c, 0x16, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xa6, 0x1a, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xfb, 0x19, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0x63, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0x0f, 0x18, 0x0c, 0x00,
+  0x27, 0x1b, 0x0c, 0x00, 0xc6, 0x1b, 0x0c, 0x00, 0xa5, 0x18, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0xa6, 0x1a, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00, 0x4f, 0x17, 0x0c, 0x00,
+  0xe7, 0x1b, 0x0c, 0x00, 0x74, 0x19, 0x0c, 0x00, 0xe7, 0x1b, 0x0c, 0x00,
+  0xeb, 0x1a, 0x0c, 0x00, 0xfb, 0x19, 0x0c, 0x00, 0x25, 0x30, 0x34, 0x75,
+  0x3a, 0x20, 0x00, 0x52, 0x4f, 0x20, 0x53, 0x56, 0x54, 0x20, 0x25, 0x64,
+  0x20, 0x48, 0x56, 0x54, 0x20, 0x25, 0x64, 0x20, 0x4c, 0x56, 0x54, 0x20,
+  0x25, 0x64, 0x0a, 0x00, 0x50, 0x4d, 0x43, 0x5f, 0x56, 0x45, 0x52, 0x3a,
+  0x25, 0x64, 0x2e, 0x25, 0x64, 0x2e, 0x25, 0x64, 0x0a, 0x00, 0x32, 0x30,
+  0x30, 0x36, 0x32, 0x38, 0x5f, 0x31, 0x34, 0x32, 0x37, 0x00, 0x54, 0x53,
+  0x3a, 0x25, 0x73, 0x0a, 0x00, 0x43, 0x48, 0x49, 0x44, 0x3a, 0x25, 0x78,
+  0x0a, 0x00, 0x43, 0x52, 0x45, 0x56, 0x3a, 0x25, 0x78, 0x0a, 0x00, 0x49,
+  0x6d, 0x61, 0x67, 0x65, 0x20, 0x69, 0x73, 0x20, 0x6e, 0x6f, 0x74, 0x20,
+  0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, 0x62, 0x6c, 0x65, 0x20, 0x77,
+  0x69, 0x74, 0x68, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x68, 0x69, 0x70,
+  0x0a, 0x00, 0x44, 0x41, 0x43, 0x3a, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x73,
+  0x6d, 0x61, 0x6c, 0x6c, 0x20, 0x73, 0x74, 0x65, 0x70, 0x20, 0x44, 0x41,
+  0x43, 0x3a, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x63, 0x75, 0x72, 0x5f, 0x64,
+  0x61, 0x63, 0x20, 0x25, 0x75, 0x20, 0x63, 0x75, 0x72, 0x56, 0x20, 0x25,
+  0x75, 0x20, 0x63, 0x75, 0x72, 0x54, 0x65, 0x6d, 0x70, 0x20, 0x25, 0x75,
+  0x20, 0x64, 0x65, 0x6c, 0x74, 0x61, 0x20, 0x25, 0x64, 0x20, 0x6e, 0x65,
+  0x77, 0x5f, 0x64, 0x61, 0x63, 0x20, 0x25, 0x75, 0x0a, 0x00, 0x41, 0x56,
+  0x53, 0x20, 0x44, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x64, 0x0a, 0x00,
+  0x4d, 0x56, 0x41, 0x44, 0x43, 0x31, 0x20, 0x4d, 0x65, 0x61, 0x73, 0x75,
+  0x72, 0x65, 0x64, 0x20, 0x25, 0x75, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x75,
+  0x6c, 0x61, 0x74, 0x65, 0x64, 0x20, 0x25, 0x75, 0x0a, 0x00, 0x4d, 0x65,
+  0x61, 0x73, 0x75, 0x72, 0x65, 0x64, 0x20, 0x4d, 0x56, 0x41, 0x44, 0x43,
+  0x32, 0x20, 0x25, 0x75, 0x0a, 0x00, 0x4d, 0x56, 0x20, 0x44, 0x65, 0x6c,
+  0x74, 0x61, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x25, 0x64, 0x20, 0x64, 0x61,
+  0x63, 0x20, 0x64, 0x65, 0x6c, 0x74, 0x61, 0x20, 0x25, 0x75, 0x20, 0x4d,
+  0x56, 0x0a, 0x00, 0x4c, 0x56, 0x54, 0x00, 0x48, 0x56, 0x54, 0x00, 0x64,
+  0x65, 0x76, 0x20, 0x61, 0x64, 0x64, 0x72, 0x20, 0x30, 0x78, 0x25, 0x78,
+  0x20, 0x52, 0x4f, 0x20, 0x74, 0x79, 0x70, 0x65, 0x20, 0x53, 0x56, 0x54,
+  0x20, 0x76, 0x61, 0x6c, 0x75, 0x65, 0x20, 0x25, 0x75, 0x20, 0x52, 0x4f,
+  0x20, 0x74, 0x79, 0x70, 0x65, 0x20, 0x25, 0x73, 0x20, 0x76, 0x61, 0x6c,
+  0x75, 0x65, 0x20, 0x25, 0x75, 0x0a, 0x00, 0x55, 0x6e, 0x6b, 0x6e, 0x6f,
+  0x77, 0x6e, 0x00, 0x53, 0x56, 0x54, 0x00, 0x43, 0x61, 0x6c, 0x63, 0x75,
+  0x6c, 0x61, 0x74, 0x65, 0x64, 0x20, 0x53, 0x69, 0x67, 0x6d, 0x61, 0x20,
+  0x66, 0x6f, 0x72, 0x20, 0x25, 0x73, 0x20, 0x52, 0x4f, 0x3a, 0x20, 0x25,
+  0x64, 0x0a, 0x00, 0x53, 0x65, 0x74, 0x74, 0x69, 0x6e, 0x67, 0x20, 0x54,
+  0x68, 0x65, 0x73, 0x68, 0x6f, 0x6c, 0x64, 0x73, 0x20, 0x66, 0x6f, 0x72,
+  0x20, 0x25, 0x64, 0x20, 0x68, 0x69, 0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f,
+  0x20, 0x25, 0x64, 0x0a, 0x00, 0x44, 0x75, 0x6d, 0x70, 0x20, 0x61, 0x6c,
+  0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73, 0x20, 0x6f, 0x6e, 0x20, 0x68, 0x69,
+  0x67, 0x68, 0x20, 0x56, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x44, 0x75, 0x6d,
+  0x70, 0x20, 0x61, 0x6c, 0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73, 0x20, 0x6f,
+  0x6e, 0x20, 0x6c, 0x6f, 0x77, 0x20, 0x56, 0x20, 0x25, 0x64, 0x0a, 0x00,
+  0x52, 0x4f, 0x5b, 0x25, 0x64, 0x5d, 0x20, 0x74, 0x61, 0x72, 0x67, 0x65,
+  0x74, 0x20, 0x25, 0x64, 0x20, 0x6c, 0x6f, 0x77, 0x5f, 0x72, 0x6f, 0x20,
+  0x25, 0x64, 0x20, 0x73, 0x6c, 0x6f, 0x70, 0x65, 0x20, 0x25, 0x64, 0x20,
+  0x76, 0x6c, 0x6f, 0x77, 0x20, 0x25, 0x64, 0x20, 0x4d, 0x56, 0x20, 0x5b,
+  0x25, 0x64, 0x5d, 0x20, 0x76, 0x68, 0x69, 0x67, 0x68, 0x20, 0x25, 0x64,
+  0x20, 0x4d, 0x56, 0x20, 0x5b, 0x25, 0x64, 0x5d, 0x20, 0x76, 0x6f, 0x6c,
+  0x74, 0x61, 0x67, 0x65, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x61, 0x76, 0x73,
+  0x5f, 0x64, 0x61, 0x63, 0x20, 0x25, 0x64, 0x20, 0x76, 0x63, 0x6f, 0x6e,
+  0x76, 0x20, 0x25, 0x64, 0x6d, 0x56, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x75,
+  0x6c, 0x61, 0x74, 0x65, 0x64, 0x5f, 0x6d, 0x61, 0x72, 0x67, 0x69, 0x6e,
+  0x20, 0x25, 0x64, 0x20, 0x6d, 0x56, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x5b,
+  0x25, 0x64, 0x5d, 0x6d, 0x56, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x68, 0x69,
+  0x67, 0x68, 0x20, 0x25, 0x64, 0x20, 0x64, 0x61, 0x63, 0x5f, 0x6c, 0x6f,
+  0x77, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x41, 0x56, 0x53, 0x20, 0x43, 0x6c,
+  0x6f, 0x73, 0x65, 0x64, 0x20, 0x6f, 0x6e, 0x20, 0x64, 0x61, 0x63, 0x5f,
+  0x63, 0x6f, 0x64, 0x65, 0x20, 0x25, 0x64, 0x20, 0x43, 0x61, 0x6c, 0x63,
+  0x69, 0x6c, 0x61, 0x74, 0x65, 0x64, 0x20, 0x25, 0x64, 0x20, 0x4d, 0x56,
+  0x20, 0x74, 0x61, 0x72, 0x67, 0x65, 0x74, 0x20, 0x25, 0x64, 0x20, 0x4d,
+  0x56, 0x20, 0x63, 0x61, 0x6c, 0x63, 0x75, 0x6c, 0x61, 0x74, 0x65, 0x64,
+  0x20, 0x64, 0x61, 0x63, 0x20, 0x25, 0x64, 0x0a, 0x00, 0x44, 0x75, 0x6d,
+  0x70, 0x20, 0x61, 0x6c, 0x6c, 0x20, 0x52, 0x4f, 0x27, 0x73, 0x20, 0x6f,
+  0x6e, 0x20, 0x73, 0x74, 0x61, 0x72, 0x74, 0x75, 0x70, 0x0a, 0x00, 0x00,
+  0x01, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x04, 0x04, 0x04, 0x04, 0x04,
+  0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05,
+  0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x06, 0x06, 0x06, 0x06, 0x06,
+  0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06,
+  0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06,
+  0x06, 0x06, 0x06, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
+  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
+  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
+  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
+  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
+  0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+  0x08, 0x08, 0x08, 0x00, 0x4f, 0x4a, 0xf0, 0x86, 0x00, 0x00, 0x00, 0x00,
+  0x23, 0x07, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00,
+  0xc8, 0x09, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00
+};
+#endif //PMC_ROMDATA_68560_H
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_lport.c b/arch/arm/mach-bcmbca/pmc/pmc_lport.c
new file mode 100755
index 0000000000..610bfbfa8b
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_lport.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+
+*/
+
+#define PRINTK printf
+#define UDELAY udelay
+
+#include "pmc_drv.h"
+#include "pmc_lport.h"
+#include "asm/arch/BPCM.h"
+#include "clk_rst.h"
+
+/* pmc_lport.c
+ *
+ *  Created on: 21 Nov 2015
+ *      Author: yonatani
+ */
+
+#define UNIPLL_CHAN23_MDIV 5
+
+int pmc_lport_init(void)
+{
+    int status;
+    LPORT_BPCM_Z0_CONTROL_REG z0_ctl =
+    { };
+    LPORT_BPCM_Z1_CONTROL_REG z1_ctl =
+    { };
+    LPORT_BPCM_Z2_CONTROL_REG z2_ctl =
+    { };
+
+    //Configur PLL
+    status = PowerOnDevice(PMB_ADDR_UNIPLL);
+    if (status)
+    {
+        PRINTK("UNIPLL PowerOnDevice failed\n");
+        return status;
+    }
+
+    status =  pll_ch_freq_vco_set(PMB_ADDR_UNIPLL, 2, UNIPLL_CHAN23_MDIV, 0);
+    if (status)
+    {
+        PRINTK("UNIPLL Channel 2 Mdiv=5 failed\n");
+        return status;
+    }
+
+    //Configure LPORT Block BPCM
+    status = PowerOnDevice(PMB_ADDR_LPORT);
+    if (status)
+    {
+        PRINTK("LPORT PowerOnDevice failed\n");
+        return status;
+    }
+
+    z0_ctl.z0_ubus_dev_clk_en = 1;
+    z0_ctl.z0_qegphy_clk_en = 1;
+    status = WriteBPCMRegister(PMB_ADDR_LPORT, LPORT_BPCM_Z0_CONTROL, *(uint32_t *)&z0_ctl);
+    if (status)
+    {
+        PRINTK("LPORT  failed BPCM LPORT_BPCM_Z0_CONTROL\n");
+        return status;
+    }
+
+    z1_ctl.z1_cclk_clk_en = 1;
+    z1_ctl.z1_clk_250_clk_en = 1;
+    z1_ctl.z1_data_path_cclk_clk_en = 1;
+    z1_ctl.z1_tsc_clk_en = 1;
+    z1_ctl.z1_tsc_clk_gated_clk_en = 1;
+    z1_ctl.z1_tsclk_clk_en = 1;
+
+    status = WriteBPCMRegister(PMB_ADDR_LPORT, LPORT_BPCM_Z1_CONTROL, *(uint32_t *)&z1_ctl);
+    if (status)
+    {
+        PRINTK("LPORT  failed BPCM LPORT_BPCM_Z1_CONTROL\n");
+        return status;
+    }
+
+    z2_ctl.z2_cclk_clk_en = 1;
+    z2_ctl.z2_clk_250_clk_en = 1;
+    z2_ctl.z2_tsc_clk_en = 1;
+    z2_ctl.z2_data_path_cclk_clk_en = 1;
+    z2_ctl.z2_tsc_clk_gated_clk_en = 1;
+    z2_ctl.z2_tsclk_clk_en = 1;
+
+    status = WriteBPCMRegister(PMB_ADDR_LPORT, LPORT_BPCM_Z2_CONTROL, *(uint32_t *)&z2_ctl);
+    if (status)
+    {
+        PRINTK("LPORT unreset failed BPCM LPORT_BPCM_Z2_CONTROL\n");
+        return status;
+    }
+
+    status = WriteBPCMRegister(PMB_ADDR_LPORT, LPORT_BPCM_Z0_DSERDES0_CTRL, 6);
+    if (status)
+    {
+        PRINTK("LPORT unreset failed BPCM LPORT_BPCM_Z0_DSERDES0_CTRL\n");
+        return status;
+    }
+
+    status = WriteBPCMRegister(PMB_ADDR_LPORT, LPORT_BPCM_Z0_DSERDES1_CTRL, 6);
+    if (status)
+    {
+        PRINTK("LPORT unreset failed BPCM LPORT_BPCM_Z1_DSERDES0_CTRL\n");
+        return status;
+    }
+
+    UDELAY(1000);
+
+    status = WriteBPCMRegister(PMB_ADDR_LPORT, LPORT_BPCM_Z0_DSERDES0_CTRL, 0);
+    if (status)
+    {
+        PRINTK("LPORT unreset failed BPCM LPORT_BPCM_Z0_DSERDES0_CTRL\n");
+        return status;
+    }
+
+    status = WriteBPCMRegister(PMB_ADDR_LPORT, LPORT_BPCM_Z0_DSERDES1_CTRL, 0);
+    if (status)
+    {
+        PRINTK("LPORT unreset failed BPCM LPORT_BPCM_Z1_DSERDES0_CTRL\n");
+        return status;
+    }
+
+    return status;
+}
+
+int pmc_lport_shutdown(void)
+{
+    /* shut down all zones */
+    return PowerOffDevice(PMB_ADDR_LPORT, 0);
+}
+
+#if !defined(_CFE_) && !defined(__UBOOT__)
+EXPORT_SYMBOL(pmc_lport_init);
+postcore_initcall(pmc_lport_init);
+#endif
+
+
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_lport.h b/arch/arm/mach-bcmbca/pmc/pmc_lport.h
new file mode 100755
index 0000000000..fbaca997a4
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_lport.h
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+
+*/
+/*
+
+ * pmc_lport.h
+ *
+ *  Created on  Nov 21 2015
+ *      Author: yonatani
+ */
+
+#ifndef _PMC_LPORT_H_
+#define _PMC_LPORT_H_
+
+//LPORT BPCM Specific registers
+#define LPORT_BPCM_Z0_CONTROL         0x20  // offset in bytes: 0x80
+#define LPORT_BPCM_Z0_QEGPHY_CTRL     0x21  // offset in bytes: 0x84
+#define LPORT_BPCM_Z0_QEGPHY_STATUS   0x22  // offset in bytes: 0x88
+#define LPORT_BPCM_Z0_DSERDES0_CTRL   0x23  // offset in bytes: 0x8c
+#define LPORT_BPCM_Z0_DSERDES0_STATUS 0x24  // offset in bytes: 0x90
+#define LPORT_BPCM_Z0_DSERDES1_CTRL   0x25  // offset in bytes: 0x94
+#define LPORT_BPCM_Z0_DSERDES1_STATUS 0x26  // offset in bytes: 0x98
+#define LPORT_BPCM_Z1_CONTROL         0x27  // offset in bytes: 0x9c
+#define LPORT_BPCM_Z2_CONTROL         0x28  // offset in bytes: 0xa0
+
+typedef struct
+{
+    uint32_t z0_sw_init_1:1;                  // 0
+    uint32_t z0_mux_sel:1;                    // 1
+    uint32_t z0_ubus_dev_clk_en:1;            // 2
+    uint32_t z0_qegphy_clk_en:1;              // 3
+    uint32_t z0_pmx_sel:1;                    // 4
+    uint32_t z0_gport_sel:8;                  // 5:12
+    uint32_t z0_control_UNUSED:19;            // 31:13
+}LPORT_BPCM_Z0_CONTROL_REG;
+
+
+typedef struct
+{
+    uint32_t z1_sw_init_1:1;                  // 0
+    uint32_t z1_clk_250_clk_en:1;             // 1
+    uint32_t z1_tsc_clk_en:1;                 // 2
+    uint32_t z1_tsc_clk_gated_clk_en:1;       // 3
+    uint32_t z1_cclk_clk_en:1;                // 4
+    uint32_t z1_data_path_cclk_clk_en:1;      // 5
+    uint32_t z1_tsclk_clk_en:1;               // 6
+    uint32_t z1_control_UNUSED1:25;           // 31:7
+}LPORT_BPCM_Z1_CONTROL_REG;
+
+typedef struct
+{
+    uint32_t z2_sw_init_1:1;                  // 0
+    uint32_t z2_clk_250_clk_en:1;             // 1
+    uint32_t z2_tsc_clk_en:1;                 // 2
+    uint32_t z2_tsc_clk_gated_clk_en:1;       // 3
+    uint32_t z2_cclk_clk_en:1;                // 4
+    uint32_t z2_data_path_cclk_clk_en:1;      // 5
+    uint32_t z2_tsclk_clk_en:1;               // 6
+    uint32_t z2_control_UNUSED:25;            // 31:7
+}LPORT_BPCM_Z2_CONTROL_REG;
+
+int pmc_lport_init(void);
+int pmc_lport_shutdown(void);
+#endif /* _PMC_LPORT_H_ */
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_patch_4908.h b/arch/arm/mach-bcmbca/pmc/pmc_patch_4908.h
new file mode 100644
index 0000000000..aebbb97e86
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_patch_4908.h
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2016 Broadcom
+ */
+// 
+unsigned char track_bin[] = {
+  0xe0, 0xff, 0xbd, 0x27, 0x14, 0x00, 0xb1, 0xaf, 0x00, 0x00, 0x11, 0x3c,
+  0x18, 0x00, 0xb2, 0xaf, 0x10, 0x00, 0xb0, 0xaf, 0x1c, 0x00, 0xbf, 0xaf,
+  0x21, 0x90, 0x80, 0x00, 0x21, 0x80, 0xa0, 0x00, 0x00, 0x00, 0x31, 0x26,
+  0x22, 0x88, 0x51, 0x00, 0x70, 0x06, 0x82, 0x8f, 0x09, 0xf8, 0x40, 0x00,
+  0x21, 0x20, 0xa0, 0x00, 0x08, 0x00, 0x03, 0x8e, 0x08, 0x49, 0x02, 0x24,
+  0x33, 0x00, 0x62, 0x14, 0x1c, 0x00, 0xbf, 0x8f, 0x0c, 0x00, 0x03, 0x8e,
+  0x4a, 0x0a, 0x02, 0x24, 0x30, 0x00, 0x62, 0x54, 0x18, 0x00, 0xb2, 0x8f,
+  0x00, 0x06, 0x82, 0x8f, 0x21, 0x28, 0x00, 0x02, 0x09, 0xf8, 0x40, 0x00,
+  0x21, 0x20, 0x00, 0x02, 0x00, 0x00, 0x02, 0x3c, 0x08, 0x00, 0x03, 0x8e,
+  0x38, 0x01, 0x42, 0x24, 0xc0, 0x9f, 0x10, 0x3c, 0x21, 0x10, 0x51, 0x00,
+  0x2c, 0x00, 0x62, 0xac, 0xcc, 0x35, 0x02, 0x26, 0x30, 0x00, 0x62, 0xac,
+  0x00, 0x00, 0x02, 0x3c, 0x90, 0x02, 0x42, 0x24, 0x21, 0x88, 0x51, 0x00,
+  0x80, 0x01, 0x83, 0xaf, 0x00, 0xb6, 0x04, 0x3c, 0x70, 0x06, 0x91, 0xaf,
+  0x28, 0x10, 0x82, 0x90, 0x7f, 0x00, 0x42, 0x30, 0x28, 0x10, 0x82, 0xa0,
+  0x38, 0x08, 0x02, 0x26, 0x09, 0xf8, 0x40, 0x00, 0x00, 0x00, 0x60, 0xa4,
+  0x8c, 0x09, 0x02, 0x26, 0x09, 0xf8, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0xa4, 0x0a, 0x02, 0x26, 0x09, 0xf8, 0x40, 0x00, 0x64, 0x13, 0x10, 0x26,
+  0x08, 0x00, 0x44, 0x8e, 0x09, 0xf8, 0x00, 0x02, 0x0c, 0x00, 0x45, 0x8e,
+  0x80, 0x01, 0x90, 0x8f, 0x00, 0x00, 0x02, 0x96, 0x0a, 0x00, 0x40, 0x10,
+  0x1c, 0x00, 0xbf, 0x8f, 0x0d, 0x00, 0x11, 0x04, 0x09, 0x80, 0x04, 0x3c,
+  0x48, 0x00, 0x19, 0x8e, 0x1c, 0x00, 0xbf, 0x8f, 0x18, 0x00, 0xb2, 0x8f,
+  0x14, 0x00, 0xb1, 0x8f, 0x10, 0x00, 0xb0, 0x8f, 0x08, 0x00, 0x20, 0x03,
+  0x20, 0x00, 0xbd, 0x27, 0x18, 0x00, 0xb2, 0x8f, 0x14, 0x00, 0xb1, 0x8f,
+  0x10, 0x00, 0xb0, 0x8f, 0x08, 0x00, 0xe0, 0x03, 0x20, 0x00, 0xbd, 0x27,
+  0x00, 0xb6, 0x02, 0x3c, 0x84, 0x10, 0x43, 0x8c, 0x01, 0x00, 0x63, 0x04,
+  0x84, 0x10, 0x44, 0xac, 0x08, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00,
+  0x80, 0x01, 0x82, 0x8f, 0xd8, 0xff, 0xbd, 0x27, 0x00, 0x00, 0x43, 0x94,
+  0x4f, 0x00, 0x60, 0x14, 0x24, 0x00, 0xbf, 0xaf, 0x30, 0x00, 0x42, 0x8c,
+  0x18, 0x00, 0xa4, 0x27, 0x14, 0x00, 0xa5, 0x27, 0x09, 0xf8, 0x40, 0x00,
+  0x10, 0x00, 0xa6, 0x27, 0x80, 0x01, 0x82, 0x8f, 0x18, 0x00, 0xa4, 0x97,
+  0x10, 0x00, 0x43, 0x94, 0x2b, 0x18, 0x83, 0x00, 0x0f, 0x00, 0x60, 0x14,
+  0x1a, 0x00, 0xa9, 0x97, 0x12, 0x00, 0x43, 0x94, 0x2b, 0x18, 0x23, 0x01,
+  0x0c, 0x00, 0x60, 0x54, 0x0f, 0x00, 0x04, 0x3c, 0x14, 0x00, 0xa8, 0x97,
+  0x18, 0x00, 0x46, 0x94, 0x2b, 0x30, 0x06, 0x01, 0x07, 0x00, 0xc0, 0x54,
+  0x0f, 0x00, 0x04, 0x3c, 0x16, 0x00, 0xa7, 0x97, 0x1a, 0x00, 0x46, 0x94,
+  0x2b, 0x30, 0xe6, 0x00, 0x06, 0x00, 0xc0, 0x50, 0x14, 0x00, 0x45, 0x94,
+  0x0f, 0x00, 0x04, 0x3c, 0xda, 0xff, 0x11, 0x04, 0x01, 0x00, 0x84, 0x24,
+  0x14, 0x00, 0x00, 0x10, 0x04, 0x00, 0x04, 0x24, 0x2b, 0x28, 0xa4, 0x00,
+  0x16, 0x00, 0xa0, 0x50, 0x80, 0x01, 0x82, 0x8f, 0x16, 0x00, 0x44, 0x94,
+  0x2b, 0x20, 0x89, 0x00, 0x12, 0x00, 0x80, 0x50, 0x80, 0x01, 0x82, 0x8f,
+  0x1c, 0x00, 0x43, 0x94, 0x2b, 0x18, 0x68, 0x00, 0x0e, 0x00, 0x60, 0x50,
+  0x80, 0x01, 0x82, 0x8f, 0x1e, 0x00, 0x42, 0x94, 0x2b, 0x10, 0x47, 0x00,
+  0x0a, 0x00, 0x40, 0x10, 0x80, 0x01, 0x82, 0x8f, 0x0f, 0x00, 0x04, 0x3c,
+  0xc6, 0xff, 0x11, 0x04, 0x02, 0x00, 0x84, 0x24, 0xff, 0xff, 0x04, 0x24,
+  0xc0, 0x9f, 0x02, 0x3c, 0xb8, 0x37, 0x42, 0x24, 0x09, 0xf8, 0x40, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x82, 0x8f, 0x03, 0x00, 0x04, 0x24,
+  0x38, 0x00, 0x42, 0x8c, 0x09, 0xf8, 0x40, 0x00, 0x20, 0x00, 0x05, 0x24,
+  0x00, 0xb6, 0x04, 0x3c, 0x00, 0x10, 0x84, 0x24, 0xf9, 0x02, 0x45, 0x28,
+  0x30, 0x00, 0x83, 0x8c, 0x06, 0x00, 0xa0, 0x10, 0x02, 0x03, 0x42, 0x28,
+  0x02, 0x00, 0x62, 0x30, 0x09, 0x00, 0x40, 0x14, 0x02, 0x00, 0x63, 0x34,
+  0x06, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x40, 0x14,
+  0x02, 0x00, 0x62, 0x30, 0x03, 0x00, 0x40, 0x10, 0xfd, 0xff, 0x02, 0x24,
+  0x24, 0x18, 0x62, 0x00, 0x30, 0x00, 0x83, 0xac, 0x0f, 0x00, 0x04, 0x3c,
+  0xa8, 0xff, 0x11, 0x04, 0x03, 0x00, 0x84, 0x24, 0x24, 0x00, 0xbf, 0x8f,
+  0x08, 0x00, 0xe0, 0x03, 0x28, 0x00, 0xbd, 0x27, 0x08, 0x49, 0x02, 0x24,
+  0x08, 0x00, 0xa2, 0xac, 0x4a, 0x1a, 0x02, 0x24, 0x08, 0x00, 0xe0, 0x03,
+  0x0c, 0x00, 0xa2, 0xac, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00
+};
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_rdp.c b/arch/arm/mach-bcmbca/pmc/pmc_rdp.c
new file mode 100755
index 0000000000..19f9599321
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_rdp.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+
+*/
+
+#include "pmc_drv.h"
+#include "pmc_rdp.h"
+#include "asm/arch/BPCM.h"
+
+#define PRINTK	printf
+
+static int pmc_rdp_start_pll_with_clk(uint32_t clk)
+{
+	uint32_t bpcmResReg;
+	uint32_t error;
+
+	if (WriteBPCMRegister(PMB_ADDR_RDPPLL, PLLBPCMRegOffset(resets), 0))
+		PRINTK
+		    ("failed to configure PMB RDPPLL at word offset of 0x%02x\n",
+		     (unsigned int)PLLBPCMRegOffset(resets));
+
+#if 0				// FIXME! after we know how to pass the RDP clk info, also clean the hardcode value?
+	if (clk == 550 MHz) {
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0x7, 0x00000084))
+			PRINTK("failed to configure PMB RDPPLL 0x7\n");
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0x8, 0x80000002))
+			PRINTK("failed to configure PMB RDPPLL 0x8\n");
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0xb, 0x800c8006))
+			PRINTK("failed to configure PMB RDPPLL 0xb\n");
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0xc, 0x81008021))
+			PRINTK("failed to configure PMB RDPPLL 0xc\n");
+		PRINTK
+		    ("%s:setting up RDP PLL to run at reduced speed of 550/275 MHz\n",
+		     __func__);
+	} else if (clk == 400 MHz) {
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0x7, 0x00000080))
+			PRINTK("failed to configure PMB RDPPLL 0x7\n");
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0x8, 0x80000002))
+			PRINTK("failed to configure PMB RDPPLL 0x8\n");
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0xb, 0x80108008))
+			PRINTK("failed to configure PMB RDPPLL 0xb\n");
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0xc, 0x81008020))
+			PRINTK("failed to configure PMB RDPPLL 0xc\n");
+		PRINTK
+		    ("%s:setting up RDP PLL to run at reduced speed of 400/200 MHz\n",
+		     __func__);
+	} else if (clk == 200 MHz) {
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0x7, 0x00000080))
+			PRINTK("failed to configure PMB RDPPLL 0x7\n");
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0x8, 0x80000002))
+			PRINTK("failed to configure PMB RDPPLL 0x8\n");
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0xb, 0x80208010))
+			PRINTK("failed to configure PMB RDPPLL 0xb\n");
+		if (WriteBPCMRegister(PMB_ADDR_RDPPLL, 0xc, 0x81008020))
+			PRINTK("failed to configure PMB RDPPLL 0xc\n");
+		PRINTK
+		    ("%s:setting up RDP PLL to run at reduced speed of 200/100 MHz\n",
+		     __func__);
+	}
+#endif
+
+	error = ReadBPCMRegister(PMB_ADDR_RDPPLL, PLLBPCMRegOffset(resets),
+				 (uint32_t *) & bpcmResReg);
+	if (error)
+		PRINTK("Failed to ReadBPCMRegister RDPPLL block at word offset "
+		       "of 0x%02x\n", (unsigned int)PLLBPCMRegOffset(resets));
+
+	if (WriteBPCMRegister(PMB_ADDR_RDPPLL, PLLBPCMRegOffset(resets),
+			      (bpcmResReg | (1 << 0))))
+		PRINTK("failed to configure PMB RDPPLL of 0x%02x\n",
+		       (unsigned int)PLLBPCMRegOffset(resets));
+
+	do {
+		error = ReadBPCMRegister(PMB_ADDR_RDPPLL,
+					 PLLBPCMRegOffset(stat),
+					 (uint32_t *) & bpcmResReg);
+		if (error)
+			PRINTK("Failed to ReadBPCMRegister RDPPLL block "
+			       "0x%02x\n",
+			       (unsigned int)PLLBPCMRegOffset(stat));
+	} while (!(bpcmResReg & 0x80000000));
+
+	error = ReadBPCMRegister(PMB_ADDR_RDPPLL, PLLBPCMRegOffset(resets),
+				 (uint32_t *) & bpcmResReg);
+	if (error)
+		PRINTK("Failed to ReadBPCMRegister RDPPLL block at word offset "
+		       "of 0x%02x\n", (unsigned int)PLLBPCMRegOffset(resets));
+
+	if (WriteBPCMRegister(PMB_ADDR_RDPPLL, PLLBPCMRegOffset(resets),
+			      (bpcmResReg | (1 << 1))))
+		PRINTK("failed to configure PMB RDPPLL of 0x%02x\n",
+		       (unsigned int)PLLBPCMRegOffset(resets));
+	return error;
+}
+
+int pmc_rdp_power_up(void)
+{
+#if defined(PMB_ADDR_RDP)
+	return PowerOnDevice(PMB_ADDR_RDP);
+#endif
+#if 0
+	int i, ret;
+	BPCM_PWR_ZONE_N_CONTROL pwr_zone_ctrl;
+
+	for (i = 0; i < PMB_ZONES_RDP; i++) {
+		ret = ReadZoneRegister(PMB_ADDR_RDP, i, 0,
+				       &pwr_zone_ctrl.Reg32);
+		if (ret)
+			return;
+		pwr_zone_ctrl.Bits.pwr_dn_req = 0;
+		pwr_zone_ctrl.Bits.dpg_ctl_en = 1;
+		pwr_zone_ctrl.Bits.pwr_up_req = 1;
+		pwr_zone_ctrl.Bits.mem_pwr_ctl_en = 1;
+		pwr_zone_ctrl.Bits.blk_reset_assert = 1;
+
+		ret = WriteZoneRegister(PMB_ADDR_RDP, i, 0,
+					pwr_zone_ctrl.Reg32);
+		if (ret)
+			return;
+	}
+#endif
+}
+
+int pmc_rdp_power_down(void)
+{
+#if defined(PMB_ADDR_RDP)
+	return PowerOffDevice(PMB_ADDR_RDP, 0);
+#endif
+#if 0
+	int i, ret;
+	BPCM_PWR_ZONE_N_CONTROL pwr_zone_ctrl;
+
+	for (i = 0; i < PMB_ZONES_RDP; i++) {
+		ret = ReadZoneRegister(PMB_ADDR_RDP, i, 0,
+				       &pwr_zone_ctrl.Reg32);
+		if (ret)
+			return;
+		pwr_zone_ctrl.Bits.pwr_dn_req = 1;
+		pwr_zone_ctrl.Bits.dpg_ctl_en = 0;
+		pwr_zone_ctrl.Bits.pwr_up_req = 0;
+		pwr_zone_ctrl.Bits.mem_pwr_ctl_en = 0;
+		pwr_zone_ctrl.Bits.blk_reset_assert = 0;
+
+		ret = WriteZoneRegister(PMB_ADDR_RDP, i, 0,
+					pwr_zone_ctrl.Reg32);
+		if (ret)
+			return;
+	}
+#endif
+}
+
+int pmc_rdp_init(void)
+{
+	int ret;
+
+	pmc_rdp_start_pll_with_clk(0);
+
+#if defined(PMB_ADDR_RDP)
+	/* put all RDP modules in reset state */
+	ret = WriteBPCMRegister(PMB_ADDR_RDP, BPCMRegOffset(sr_control), 0);
+	if (ret)
+		PRINTK("%s:%d:failed to configure PMB RDP at word offset of "
+		       "0x%02x\n", __func__, __LINE__,
+		       (unsigned int)BPCMRegOffset(sr_control));
+#endif
+
+	ret = pmc_rdp_power_down();
+	if (ret)
+		PRINTK("%s:%d:initialization fails! ret = %d\n", __func__,
+		       __LINE__, ret);
+
+	ret = pmc_rdp_power_up();
+	if (ret)
+		PRINTK("%s:%d:initialization fails! ret = %d\n", __func__,
+		       __LINE__, ret);
+
+#if defined(PMB_ADDR_RDP)
+	/* we will just put all the modules off reset */
+	ret = WriteBPCMRegister(PMB_ADDR_RDP, BPCMRegOffset(sr_control),
+				0xffffffff);
+	if (ret)
+		PRINTK("%s:%d:failed to configure PMB RDP at word offset of "
+		       "0x%02x\n", __func__, __LINE__,
+		       (unsigned int)BPCMRegOffset(sr_control));
+#endif
+
+	return ret;
+}
+
+int pmc_rdp_shut_down(void)
+{
+#if defined(PMB_ADDR_RDP)
+	int ret;
+
+	/* put all RDP modules in reset state */
+	ret = WriteBPCMRegister(PMB_ADDR_RDP, BPCMRegOffset(sr_control), 0);
+	if (ret)
+		PRINTK("%s:%d:failed to configure PMB RDP at word offset of "
+		       "0x%02x\n", __func__, __LINE__,
+		       (unsigned int)BPCMRegOffset(sr_control));
+	return ret;
+#else
+	return -1;
+#endif
+}
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_rdp.h b/arch/arm/mach-bcmbca/pmc/pmc_rdp.h
new file mode 100755
index 0000000000..b523bec860
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_rdp.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+
+#ifndef PMC_RDP_H
+#define PMC_RDP_H
+
+int pmc_rdp_power_up(void);
+int pmc_rdp_power_down(void);
+int pmc_rdp_init(void);
+int pmc_rdp_shut_down(void);
+
+#endif /* #ifndef PMC_RDP_H */
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_romdata_63158.h b/arch/arm/mach-bcmbca/pmc/pmc_romdata_63158.h
new file mode 100644
index 0000000000..847895427f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_romdata_63158.h
@@ -0,0 +1,1671 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Broadcom
+ */
+/*
+ * * 
+ * */
+
+
+#ifndef PMC_ROMDATA_63158_H
+#define PMC_ROMDATA_63158_H
+const unsigned char pmcappdata[] = {
+  0x3c, 0x08, 0x00, 0x40, 0x40, 0x88, 0x60, 0x00, 0x40, 0x80, 0x68, 0x00,
+  0x40, 0x80, 0x48, 0x00, 0x40, 0x80, 0x58, 0x00, 0x40, 0x80, 0x70, 0x00,
+  0x40, 0x80, 0xf0, 0x00, 0x40, 0x08, 0x80, 0x00, 0x3c, 0x01, 0x00, 0x80,
+  0x01, 0x01, 0x40, 0x24, 0x11, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00,
+  0x3c, 0x0a, 0x10, 0x00, 0x40, 0x8a, 0xd0, 0x00, 0x24, 0x08, 0x00, 0x80,
+  0x40, 0x88, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x09, 0x80, 0x00,
+  0xbd, 0x29, 0x00, 0x00, 0x40, 0x80, 0xd0, 0x00, 0x40, 0x08, 0x80, 0x00,
+  0x24, 0x01, 0xff, 0xf8, 0x01, 0x01, 0x40, 0x24, 0x40, 0x88, 0x80, 0x00,
+  0x40, 0x08, 0x80, 0x01, 0x04, 0x11, 0x00, 0x2a, 0x00, 0x08, 0x24, 0x02,
+  0x00, 0x40, 0xa0, 0x21, 0x00, 0x60, 0xb0, 0x21, 0x04, 0x11, 0x00, 0x26,
+  0x00, 0x08, 0x21, 0xc2, 0x00, 0x40, 0xa8, 0x21, 0x00, 0x60, 0xb8, 0x21,
+  0x3c, 0x0c, 0x80, 0x00, 0x40, 0x80, 0xe0, 0x00, 0x01, 0x94, 0x48, 0x21,
+  0x26, 0xca, 0xff, 0xff, 0x01, 0x40, 0x50, 0x27, 0x01, 0x8a, 0x40, 0x24,
+  0x25, 0x29, 0xff, 0xff, 0x01, 0x2a, 0x48, 0x24, 0xbd, 0x08, 0x00, 0x00,
+  0x15, 0x09, 0xff, 0xfe, 0x01, 0x16, 0x40, 0x21, 0x01, 0x95, 0x48, 0x21,
+  0x26, 0xea, 0xff, 0xff, 0x01, 0x40, 0x50, 0x27, 0x01, 0x8a, 0x40, 0x24,
+  0x25, 0x29, 0xff, 0xff, 0x01, 0x2a, 0x48, 0x24, 0xbd, 0x09, 0x00, 0x00,
+  0x15, 0x09, 0xff, 0xfe, 0x01, 0x17, 0x40, 0x21, 0x3c, 0x1c, 0x80, 0x00,
+  0x27, 0x9c, 0x70, 0x00, 0x23, 0x9d, 0x10, 0x00, 0x03, 0x80, 0x40, 0x21,
+  0x21, 0x09, 0x0a, 0xc8, 0x01, 0x09, 0x50, 0x2b, 0x11, 0x40, 0x00, 0x04,
+  0x00, 0x00, 0x00, 0x00, 0xad, 0x00, 0x00, 0x00, 0x10, 0x00, 0xff, 0xfb,
+  0x25, 0x08, 0x00, 0x04, 0x04, 0x11, 0x00, 0xbb, 0x00, 0x00, 0x00, 0x00,
+  0x10, 0x00, 0xff, 0xf2, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x40,
+  0x30, 0x83, 0x01, 0xc0, 0x00, 0x03, 0x19, 0x82, 0x00, 0x62, 0x10, 0x04,
+  0x30, 0x83, 0x00, 0x38, 0x00, 0x03, 0x18, 0xc2, 0x10, 0x60, 0x00, 0x09,
+  0x00, 0x00, 0x00, 0x00, 0x3c, 0x01, 0xdf, 0xff, 0x34, 0x21, 0xff, 0xff,
+  0x03, 0xe1, 0xf8, 0x24, 0x24, 0x0a, 0x00, 0x02, 0x00, 0x6a, 0x18, 0x04,
+  0x30, 0x8a, 0x00, 0x07, 0x21, 0x4a, 0x00, 0x01, 0x71, 0x42, 0x10, 0x02,
+  0x03, 0xe0, 0x00, 0x08, 0x70, 0x43, 0x10, 0x02, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+  0x8e, 0x23, 0x00, 0x04, 0x24, 0x02, 0x00, 0x03, 0x14, 0x62, 0x00, 0x4a,
+  0x00, 0x00, 0x00, 0x00, 0x0f, 0xf0, 0x04, 0x74, 0x00, 0x00, 0x20, 0x21,
+  0x24, 0x0d, 0x03, 0xe8, 0x00, 0x4d, 0x00, 0x1a, 0x8f, 0xa2, 0x00, 0x28,
+  0x3c, 0x0e, 0x9f, 0xc0, 0x3c, 0x0f, 0x9f, 0xc0, 0x24, 0x4c, 0x70, 0x64,
+  0x25, 0xce, 0x2b, 0xd4, 0x25, 0xef, 0x2b, 0x9c, 0x3c, 0x18, 0x9f, 0xc0,
+  0x00, 0x00, 0x68, 0x12, 0x8d, 0x84, 0x00, 0x00, 0x3c, 0x0a, 0x00, 0x1c,
+  0x00, 0x8a, 0x18, 0x24, 0x3c, 0x02, 0x00, 0x14, 0x50, 0x62, 0x00, 0x38,
+  0xae, 0x20, 0x00, 0x04, 0x04, 0x83, 0xff, 0xf9, 0x25, 0x8c, 0x00, 0x1c,
+  0x7c, 0x82, 0x3a, 0x80, 0x24, 0x42, 0xff, 0xe0, 0x30, 0x42, 0x00, 0xff,
+  0x2c, 0x42, 0x00, 0x05, 0x54, 0x40, 0xff, 0xf3, 0x25, 0x8c, 0x00, 0x1c,
+  0x3c, 0x09, 0x00, 0x03, 0x35, 0x29, 0xfc, 0x00, 0x00, 0x89, 0x18, 0x24,
+  0x34, 0x02, 0x98, 0x00, 0x10, 0x62, 0x00, 0x28, 0x3c, 0x02, 0x16, 0x00,
+  0x00, 0x82, 0x10, 0x24, 0x54, 0x40, 0xff, 0xea, 0x25, 0x8c, 0x00, 0x1c,
+  0x0f, 0xf0, 0x10, 0x54, 0x7c, 0x84, 0x1d, 0x40, 0x24, 0x07, 0x22, 0x60,
+  0x70, 0x47, 0x10, 0x02, 0x24, 0x07, 0x1c, 0x00, 0x00, 0x47, 0x00, 0x1a,
+  0x8d, 0x85, 0x00, 0x00, 0x3c, 0x03, 0x00, 0x0c, 0x00, 0xaa, 0x50, 0x24,
+  0x95, 0x82, 0x00, 0x04, 0x15, 0x43, 0x00, 0x0a, 0x00, 0x00, 0x38, 0x12,
+  0xaf, 0xa2, 0x00, 0x14, 0x7c, 0xa2, 0x3a, 0x80, 0xaf, 0xa2, 0x00, 0x10,
+  0x01, 0xa0, 0x30, 0x21, 0x7c, 0xa5, 0x1d, 0x40, 0x0f, 0xf0, 0x10, 0xbe,
+  0x27, 0x04, 0x2b, 0x6c, 0x10, 0x00, 0xff, 0xd5, 0x25, 0x8c, 0x00, 0x1c,
+  0x95, 0x83, 0x00, 0x06, 0x00, 0xa9, 0x48, 0x24, 0xaf, 0xa2, 0x00, 0x14,
+  0x34, 0x04, 0x94, 0x00, 0x7c, 0xa2, 0x3a, 0x80, 0xaf, 0xa3, 0x00, 0x18,
+  0xaf, 0xa2, 0x00, 0x10, 0x01, 0xa0, 0x30, 0x21, 0x15, 0x24, 0x00, 0x03,
+  0x7c, 0xa5, 0x1d, 0x40, 0x10, 0x00, 0x00, 0x02, 0x01, 0xe0, 0x20, 0x21,
+  0x01, 0xc0, 0x20, 0x21, 0x0f, 0xf0, 0x10, 0xbe, 0x00, 0x00, 0x00, 0x00,
+  0x10, 0x00, 0xff, 0xc4, 0x25, 0x8c, 0x00, 0x1c, 0x0f, 0xf0, 0x10, 0x72,
+  0x3c, 0x10, 0xb6, 0x08, 0x0f, 0xf0, 0x11, 0x31, 0x00, 0x00, 0x00, 0x00,
+  0x8e, 0x02, 0x02, 0x80, 0x7c, 0x42, 0x03, 0x80, 0x10, 0x40, 0xff, 0xfb,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0xa2, 0x00, 0x28,
+  0x3c, 0x12, 0x00, 0x1c, 0x24, 0x56, 0x70, 0x64, 0xaf, 0xb6, 0x00, 0x30,
+  0x3c, 0x10, 0x00, 0x14, 0x27, 0x94, 0x00, 0x40, 0x8e, 0xc2, 0x00, 0x00,
+  0x02, 0x42, 0x10, 0x24, 0x10, 0x50, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00,
+  0x0f, 0xf0, 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x8e, 0xc2, 0x00, 0x00,
+  0x7c, 0x42, 0x1d, 0x40, 0x00, 0x02, 0x10, 0x40, 0x02, 0x82, 0x10, 0x21,
+  0x94, 0x42, 0x00, 0x00, 0x54, 0x40, 0xff, 0xf4, 0x26, 0xd6, 0x00, 0x1c,
+  0x00, 0x00, 0x28, 0x21, 0x0f, 0xf0, 0x10, 0x7d, 0x02, 0xc0, 0x20, 0x21,
+  0x10, 0x00, 0xff, 0xef, 0x26, 0xd6, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00,
+  0x3c, 0x02, 0x9f, 0xc0, 0x24, 0x42, 0x2c, 0x90, 0xaf, 0xa2, 0x00, 0x34,
+  0x3c, 0x02, 0x9f, 0xc0, 0x24, 0x42, 0x2c, 0x58, 0xaf, 0xa2, 0x00, 0x38,
+  0x3c, 0x02, 0x9f, 0xc0, 0x27, 0x94, 0x00, 0x40, 0x27, 0x92, 0x00, 0x2c,
+  0x00, 0x00, 0x80, 0x21, 0xaf, 0xa2, 0x00, 0x3c, 0x0f, 0xf0, 0x11, 0x31,
+  0x00, 0x00, 0x00, 0x00, 0x8f, 0x82, 0x00, 0x50, 0x54, 0x40, 0x00, 0xa7,
+  0x26, 0x10, 0x00, 0x01, 0x96, 0x82, 0x00, 0x00, 0x14, 0x40, 0x00, 0xa3,
+  0x8f, 0xa2, 0x00, 0x2c, 0x8f, 0xac, 0x00, 0x30, 0x8c, 0x42, 0x00, 0x04,
+  0x00, 0x00, 0xc0, 0x21, 0x38, 0x42, 0x00, 0x01, 0x2c, 0x55, 0x00, 0x01,
+  0x00, 0x00, 0x78, 0x21, 0x00, 0x00, 0xb8, 0x21, 0x00, 0x00, 0x70, 0x21,
+  0x00, 0x00, 0xf0, 0x21, 0x00, 0x00, 0xc8, 0x21, 0x8d, 0x82, 0x00, 0x00,
+  0x3c, 0x03, 0x00, 0x1c, 0x00, 0x62, 0x18, 0x24, 0x3c, 0x04, 0x00, 0x14,
+  0x10, 0x64, 0x00, 0x67, 0x7c, 0x42, 0x1d, 0x40, 0x54, 0x50, 0xff, 0xf9,
+  0x25, 0x8c, 0x00, 0x1c, 0x25, 0x93, 0x00, 0x08, 0x00, 0x00, 0x68, 0x21,
+  0x96, 0x63, 0xff, 0xfc, 0x2c, 0x62, 0x00, 0x0b, 0x54, 0x40, 0x00, 0x5a,
+  0x25, 0xad, 0x00, 0x01, 0x8d, 0x84, 0x00, 0x00, 0x3c, 0x02, 0x00, 0x1f,
+  0x34, 0x42, 0xfc, 0x00, 0x00, 0x82, 0x10, 0x24, 0x3c, 0x05, 0x00, 0x0c,
+  0x10, 0x45, 0x00, 0x06, 0x24, 0xa7, 0x04, 0x00, 0x10, 0x47, 0x00, 0x06,
+  0x24, 0xa5, 0x0c, 0x00, 0x00, 0x45, 0x10, 0x26, 0x10, 0x00, 0x00, 0x04,
+  0x00, 0x62, 0x70, 0x0a, 0x10, 0x00, 0x00, 0x02, 0x00, 0x60, 0xb8, 0x21,
+  0x00, 0x60, 0xf0, 0x21, 0x3c, 0x02, 0x00, 0x03, 0x34, 0x42, 0xfc, 0x00,
+  0x00, 0x82, 0x10, 0x24, 0x34, 0x05, 0x94, 0x00, 0x54, 0x45, 0x00, 0x09,
+  0x96, 0x62, 0x00, 0x04, 0x3c, 0x02, 0x00, 0x1c, 0x00, 0x82, 0x20, 0x24,
+  0x3c, 0x02, 0x00, 0x0c, 0x10, 0x82, 0x00, 0x03, 0x39, 0xa2, 0x00, 0x01,
+  0x00, 0x62, 0xc0, 0x0b, 0x00, 0x62, 0x78, 0x0a, 0x96, 0x62, 0x00, 0x04,
+  0x00, 0x62, 0x10, 0x2b, 0x50, 0x40, 0x00, 0x0f, 0x96, 0x62, 0x00, 0x00,
+  0xaf, 0xa3, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x86, 0x45, 0x00, 0x00,
+  0x02, 0x00, 0x20, 0x21, 0x0f, 0xf0, 0x11, 0x81, 0x00, 0x05, 0x28, 0x80,
+  0x3c, 0x04, 0x9f, 0xc0, 0x02, 0x00, 0x28, 0x21, 0x0f, 0xf0, 0x10, 0xbe,
+  0x24, 0x84, 0x2c, 0x0c, 0x24, 0x02, 0x00, 0x01, 0xaf, 0x82, 0x00, 0x08,
+  0x10, 0x00, 0x00, 0x04, 0x8f, 0xa3, 0x00, 0x48, 0x00, 0x43, 0x10, 0x2b,
+  0x2c, 0x42, 0x00, 0x01, 0x03, 0x22, 0xc8, 0x21, 0x8f, 0x96, 0x00, 0x08,
+  0x24, 0x02, 0x00, 0x01, 0x52, 0xc2, 0x00, 0x07, 0x96, 0x67, 0x00, 0x04,
+  0x53, 0x20, 0x00, 0x23, 0x25, 0xad, 0x00, 0x01, 0x24, 0x02, 0x00, 0x02,
+  0x56, 0xc2, 0x00, 0x21, 0x25, 0xad, 0x00, 0x01, 0x96, 0x67, 0x00, 0x00,
+  0x8d, 0x86, 0x00, 0x00, 0x24, 0x02, 0x00, 0x03, 0x7c, 0xc4, 0x14, 0x80,
+  0x14, 0x82, 0x00, 0x07, 0x24, 0x02, 0x00, 0x01, 0x8f, 0xa2, 0x00, 0x3c,
+  0xaf, 0xa3, 0x00, 0x10, 0x7c, 0xc6, 0x3a, 0x80, 0x02, 0x00, 0x28, 0x21,
+  0x10, 0x00, 0x00, 0x08, 0x24, 0x44, 0x2c, 0x20, 0xaf, 0xa3, 0x00, 0x10,
+  0x7c, 0xc6, 0x3a, 0x80, 0x11, 0xa2, 0x00, 0x03, 0x02, 0x00, 0x28, 0x21,
+  0x10, 0x00, 0x00, 0x02, 0x8f, 0xa4, 0x00, 0x38, 0x8f, 0xa4, 0x00, 0x34,
+  0x0f, 0xf0, 0x10, 0xbe, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x01,
+  0x16, 0xc2, 0x00, 0x04, 0x24, 0x02, 0x00, 0x02, 0xaf, 0x80, 0x00, 0x08,
+  0x10, 0x00, 0x00, 0x17, 0x24, 0x15, 0x00, 0x01, 0x16, 0xc2, 0x00, 0x02,
+  0x24, 0x15, 0x00, 0x01, 0xaf, 0x80, 0x00, 0x08, 0x25, 0xad, 0x00, 0x01,
+  0x24, 0x02, 0x00, 0x02, 0x15, 0xa2, 0xff, 0xa1, 0x26, 0x73, 0x00, 0x02,
+  0x10, 0x00, 0xff, 0x95, 0x25, 0x8c, 0x00, 0x1c, 0x17, 0x20, 0x00, 0x0d,
+  0x01, 0xf8, 0x10, 0x25, 0x00, 0x00, 0x00, 0x00, 0x86, 0x45, 0x00, 0x00,
+  0x02, 0x00, 0x20, 0x21, 0x0f, 0xf0, 0x11, 0x81, 0x00, 0x05, 0x28, 0x23,
+  0x3c, 0x04, 0x9f, 0xc0, 0x02, 0x00, 0x28, 0x21, 0x0f, 0xf0, 0x10, 0xbe,
+  0x24, 0x84, 0x2c, 0xc8, 0x24, 0x02, 0x00, 0x02, 0xaf, 0x82, 0x00, 0x08,
+  0x01, 0xf8, 0x10, 0x25, 0x02, 0xe2, 0x10, 0x25, 0x03, 0xc2, 0x10, 0x25,
+  0x01, 0xc2, 0x10, 0x25, 0x30, 0x42, 0xff, 0xff, 0x00, 0x02, 0x10, 0x2b,
+  0x00, 0x55, 0x10, 0x24, 0x50, 0x40, 0x00, 0x18, 0x26, 0x10, 0x00, 0x01,
+  0x0f, 0xf0, 0x04, 0x74, 0x00, 0x00, 0x20, 0x21, 0x02, 0x00, 0x20, 0x21,
+  0x0f, 0xf0, 0x10, 0x54, 0x00, 0x40, 0x48, 0x21, 0x24, 0x07, 0x22, 0x60,
+  0x70, 0x47, 0x10, 0x02, 0x24, 0x07, 0x1c, 0x00, 0x00, 0x47, 0x00, 0x1a,
+  0x24, 0x06, 0x03, 0xe8, 0x3c, 0x04, 0x9f, 0xc0, 0xaf, 0xb8, 0x00, 0x20,
+  0xaf, 0xaf, 0x00, 0x1c, 0xaf, 0xae, 0x00, 0x18, 0xaf, 0xbe, 0x00, 0x14,
+  0xaf, 0xb7, 0x00, 0x10, 0x02, 0x00, 0x28, 0x21, 0x24, 0x84, 0x2c, 0xdc,
+  0x00, 0x00, 0x38, 0x12, 0x01, 0x26, 0x00, 0x1a, 0x0f, 0xf0, 0x10, 0xbe,
+  0x00, 0x00, 0x30, 0x12, 0x26, 0x10, 0x00, 0x01, 0x24, 0x02, 0x00, 0x02,
+  0x26, 0x94, 0x00, 0x02, 0x16, 0x02, 0xff, 0x52, 0x26, 0x52, 0x00, 0x02,
+  0x8f, 0x82, 0x00, 0x44, 0x14, 0x40, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00,
+  0x0f, 0xf0, 0x04, 0x74, 0x00, 0x00, 0x20, 0x21, 0x3c, 0x03, 0x00, 0x01,
+  0x34, 0x63, 0xe8, 0x48, 0x00, 0x43, 0x10, 0x2a, 0x14, 0x40, 0x00, 0x11,
+  0x3c, 0x05, 0xb6, 0x00, 0x24, 0x02, 0xff, 0xff, 0xac, 0xa2, 0x10, 0x2c,
+  0x0f, 0xf0, 0x0a, 0x6d, 0x24, 0x04, 0x0b, 0xb8, 0x8c, 0xa3, 0x10, 0x7c,
+  0x3c, 0x06, 0xa0, 0x00, 0x00, 0x66, 0x18, 0x25, 0x88, 0x64, 0x04, 0x8c,
+  0x8c, 0xa2, 0x10, 0x7c, 0x98, 0x64, 0x04, 0x8f, 0x00, 0x46, 0x10, 0x25,
+  0x00, 0x80, 0x18, 0x21, 0x24, 0x04, 0x00, 0x01, 0x7c, 0x83, 0xc6, 0x04,
+  0xa8, 0x43, 0x04, 0x8c, 0xb8, 0x43, 0x04, 0x8f, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0xfe, 0x6c, 0x8e, 0x23, 0x00, 0x04,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00
+};
+#endif //PMC_ROMDATA_63158_H
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_switch.c b/arch/arm/mach-bcmbca/pmc/pmc_switch.c
new file mode 100755
index 0000000000..17bec47ade
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_switch.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+#include "pmc_drv.h"
+#include "pmc_switch.h"
+#include "asm/arch/BPCM.h"
+
+int pmc_switch_enable_rgmii_zone_clk(int z1_clk_enable, int z2_clk_enable)
+{
+	int ret = 0;
+#if defined(CONFIG_BCM63138) || defined(CONFIG_BCM63148) || defined(CONFIG_BCM4908) || defined(CONFIG_BCM63158)
+#if defined(CONFIG_BCM63158)
+	BPCM_GLOBAL_CNTL_1 global_cntl_1;
+	BPCM_GLOBAL_CNTL_2 global_cntl_2;
+#else
+	BPCM_GLOBAL_CNTL global_cntl;
+#endif
+
+#if defined(CONFIG_BCM63148)
+	BPCM_SGPHY_CNTL sgphy_cntl;
+
+	sgphy_cntl.Reg32 = 0x33;
+	ret = WriteBPCMRegister(PMB_ADDR_SWITCH,
+				BPCMRegOffset(sgphy_cntl), sgphy_cntl.Reg32);
+#endif
+
+#if defined(CONFIG_BCM63158)
+	ret = ReadBPCMRegister(PMB_ADDR_SWITCH,
+			       BPCMRegOffset(global_control_1),
+			       &global_cntl_1.Reg32);
+	ret =
+	    ReadBPCMRegister(PMB_ADDR_SWITCH, BPCMRegOffset(global_control_2),
+			     &global_cntl_2.Reg32);
+
+	global_cntl_1.Bits.z1_ck250_clk_en = 0;
+	global_cntl_2.Bits.z2_ck250_clk_en = 0;
+	ret = WriteBPCMRegister(PMB_ADDR_SWITCH,
+				BPCMRegOffset(global_control_1),
+				global_cntl_1.Reg32);
+	ret =
+	    WriteBPCMRegister(PMB_ADDR_SWITCH, BPCMRegOffset(global_control_2),
+			      global_cntl_2.Reg32);
+
+	ret = ReadBPCMRegister(PMB_ADDR_SWITCH,
+			       BPCMRegOffset(global_control_1),
+			       &global_cntl_1.Reg32);
+
+	ret = ReadBPCMRegister(PMB_ADDR_SWITCH,
+			       BPCMRegOffset(global_control_2),
+			       &global_cntl_2.Reg32);
+	if (z1_clk_enable)
+		global_cntl_1.Bits.z1_ck250_clk_en = 1;
+	if (z2_clk_enable)
+		global_cntl_2.Bits.z2_ck250_clk_en = 1;
+	ret = WriteBPCMRegister(PMB_ADDR_SWITCH,
+				BPCMRegOffset(global_control_1),
+				global_cntl_1.Reg32);
+	ret =
+	    WriteBPCMRegister(PMB_ADDR_SWITCH, BPCMRegOffset(global_control_2),
+			      global_cntl_2.Reg32);
+
+#else
+	ret = ReadBPCMRegister(PMB_ADDR_SWITCH,
+			       BPCMRegOffset(global_control),
+			       &global_cntl.Reg32);
+
+	global_cntl.Bits.z1_ck250_clk_en = 0;
+	global_cntl.Bits.z2_ck250_clk_en = 0;
+	ret = WriteBPCMRegister(PMB_ADDR_SWITCH,
+				BPCMRegOffset(global_control),
+				global_cntl.Reg32);
+
+	ret = ReadBPCMRegister(PMB_ADDR_SWITCH,
+			       BPCMRegOffset(global_control),
+			       &global_cntl.Reg32);
+	if (z1_clk_enable)
+		global_cntl.Bits.z1_ck250_clk_en = 1;
+	if (z2_clk_enable)
+		global_cntl.Bits.z2_ck250_clk_en = 1;
+	ret = WriteBPCMRegister(PMB_ADDR_SWITCH,
+				BPCMRegOffset(global_control),
+				global_cntl.Reg32);
+#endif
+
+	printf("%s: Rgmii Tx clock zone1 enable %d zone2 enable %d. \n",
+	       __FUNCTION__, z1_clk_enable, z2_clk_enable);
+#endif
+	
+	return ret;
+}
+
+int pmc_switch_power_up(void)
+{
+	return PowerOnDevice(PMB_ADDR_SWITCH);
+}
+
+int pmc_switch_power_down(void)
+{
+	return PowerOffDevice(PMB_ADDR_SWITCH, 0);
+}
+
+#if defined(CONFIG_BCM63158) && (CONFIG_BRCM_CHIP_REV==0x63158A0)
+#define SWITCH_PLL_NORMAL   (0xC)	/* switch PLL is from 3GMHz, divider of 12 (0xD) will bring it to 250 MHz */
+#define SWITCH_PLL_LOW_PWR  (0xF0)	/* switch PLL is from 3GMHz, divider of 240 (0xF0) will bring it to 12.5 MHz */
+#elif defined(CONFIG_BCM63158)
+/* From VLSI:
+   PLL VCO frequency increased by 1.5x from A0 to B0;
+   In normal mode we increased Switch frequency from A0 to B0 and that's why the value is less than 1.5x.
+   Low power mode can stay at 1.5x which provides the same PLL output freq between A0 and B0.
+*/
+#define SWITCH_PLL_NORMAL   (0x11)
+#define SWITCH_PLL_LOW_PWR  (0xFF)
+#elif defined(CONFIG_BCM63178)
+#define SWITCH_PLL_NORMAL   (0x06)
+#define SWITCH_PLL_LOW_PWR  (0xFF)
+#endif
+
+#if defined(CONFIG_BCM63158) || defined (CONFIG_BCM63178) || defined (CONFIG_BCM6756)
+void pmc_sysport_reset_system_port(int port)
+{
+	int status;
+	uint32_t reg;
+	(void)port;
+
+	// for both BCM63158 and BCM63178, system port is tide to Zone 3 of the Switch BPCM
+	status =
+	    ReadBPCMRegister(PMB_ADDR_SWITCH, BPCMRegOffset(sr_control), &reg);
+	if (status == kPMC_NO_ERROR) {
+		// system port is on zone 3 of the switch BPCM
+		reg |= 0x8;
+		status =
+		    WriteBPCMRegister(PMB_ADDR_SWITCH,
+				      BPCMRegOffset(sr_control), reg);
+
+		if (status == kPMC_NO_ERROR) {
+			reg &= ~0x8;
+			status =
+			    WriteBPCMRegister(PMB_ADDR_SWITCH,
+					      BPCMRegOffset(sr_control), reg);
+		}
+	}
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_switch.h b/arch/arm/mach-bcmbca/pmc/pmc_switch.h
new file mode 100755
index 0000000000..032612ff19
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_switch.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ 
+*/
+
+#ifndef PMC_SWITCH_H
+#define PMC_SWITCH_H
+
+int pmc_switch_power_up(void);
+int pmc_switch_power_down(void);
+void pmc_switch_clock_lowpower_mode(int low_power);
+int pmc_switch_enable_rgmii_zone_clk(int z1_clk_enable, int z2_clk_enable);
+
+#endif //#ifndef PMC_SWITCH_H
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_sysport.c b/arch/arm/mach-bcmbca/pmc/pmc_sysport.c
new file mode 100644
index 0000000000..d4011d6459
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_sysport.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Broadcom
+ */
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2020 Broadcom Ltd.
+ */
+/*
+ 
+*/
+#include "pmc_drv.h"
+#include "asm/arch/BPCM.h"
+
+
+int pmc_sysport_power_up(void)
+{
+    PowerOnDevice(PMB_ADDR_SYSP);
+
+    // reset system port through BPCM
+    pmc_sysport_reset_system_port(0);
+//#if defined(_BCM947622_) || defined(CONFIG_BCM947622)
+    pmc_sysport_reset_system_port(1);
+//#endif
+
+    return 0;
+}
+
+int pmc_sysport_power_down(void)
+{
+    return PowerOffDevice(PMB_ADDR_SYSP, 0);
+}
+
+void pmc_sysport_reset_system_port (int port)
+{
+    int status;
+    uint32_t reg;
+    int offset;
+
+	printf("sysport reset %d\n", port);
+
+    // only sysport 0 and 1 is expect to be used in CFE, reject non port reset request
+    if (port == 0)
+    {
+        offset=SYSPRegOffset(z1_pm_cntl);
+    }
+//#if defined(_BCM947622_) || defined(CONFIG_BCM947622)
+    else if (port == 1)
+    {
+        offset=SYSPRegOffset(z2_pm_cntl);
+    }
+//#endif
+    else
+    {
+        printf("unexpected system port %d reset\n", port);
+        return;
+    }
+
+    status = ReadBPCMRegister(PMB_ADDR_SYSP, offset, &reg);
+    if (status == kPMC_NO_ERROR)
+    {
+        // toggle sw_init field (bit 0)
+        reg |= 0x1;
+        status = WriteBPCMRegister(PMB_ADDR_SYSP, offset, reg);
+
+        if (status == kPMC_NO_ERROR)
+        {
+            reg &= ~0x1;
+            status = WriteBPCMRegister(PMB_ADDR_SYSP, offset, reg);
+        }
+    }
+}
+
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_xrdp.c b/arch/arm/mach-bcmbca/pmc/pmc_xrdp.c
new file mode 100755
index 0000000000..c050d3c921
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_xrdp.c
@@ -0,0 +1,431 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+
+*/
+
+#define PRINTK printf
+
+#include "pmc_drv.h"
+#include "pmc_xrdp.h"
+#include "asm/arch/BPCM.h"
+#include "clk_rst.h"
+#include "bcm_ubus4.h"
+
+int pmc_xrdp_init(void)
+{
+    int status = 0;
+
+#if IS_BCMCHIP(6858)
+    uint32_t reg = 0;
+
+    status =  PowerOnDevice(PMB_ADDR_XRDP);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP\n");
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_QM);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_QM\n");
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC_QUAD0);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC_QUAD0\n");
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC_QUAD1);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC_QUAD1\n");
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC_QUAD2);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC_QUAD2\n");
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC_QUAD3);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC_QUAD3\n");
+        return status;
+    }
+
+    PRINTK("Toggle reset of XRDP core...\n");
+    status = ReadBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), &reg);
+    reg &= 0xFFFFFF00;
+    status = WriteBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), reg);
+
+    status |= ReadBPCMRegister(PMB_ADDR_XRDP_QM, BPCMRegOffset(sr_control), &reg);
+    reg &= 0xFFFFFF00;
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_QM, BPCMRegOffset(sr_control), reg);
+
+    status |=  ReadBPCMRegister(PMB_ADDR_XRDP_RC_QUAD0, BPCMRegOffset(sr_control), &reg);
+    reg &= 0xFFFFFF00;
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC_QUAD0, BPCMRegOffset(sr_control), reg);
+
+    status |=  ReadBPCMRegister(PMB_ADDR_XRDP_RC_QUAD1, BPCMRegOffset(sr_control), &reg);
+    reg &= 0xFFFFFF00;
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC_QUAD1, BPCMRegOffset(sr_control), reg);
+
+    status |=  ReadBPCMRegister(PMB_ADDR_XRDP_RC_QUAD2, BPCMRegOffset(sr_control), &reg);
+    reg &= 0xFFFFFF00;
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC_QUAD2, BPCMRegOffset(sr_control), reg);
+
+    status |=  ReadBPCMRegister(PMB_ADDR_XRDP_RC_QUAD3, BPCMRegOffset(sr_control), &reg);
+    reg &= 0xFFFFFF00;
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC_QUAD3, BPCMRegOffset(sr_control), reg);
+
+    if(status)
+    {
+        PRINTK("failed Toggle reset of XRDP core to zero...\n");
+        return status;
+    }
+    status |=  ReadBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), &reg);
+    reg |= 0xff;
+    status = WriteBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), reg);
+
+    status |=  ReadBPCMRegister(PMB_ADDR_XRDP_QM, BPCMRegOffset(sr_control), &reg);
+    reg |= 0xff;
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_QM, BPCMRegOffset(sr_control), 0xff);
+
+
+    status |=  ReadBPCMRegister(PMB_ADDR_XRDP_RC_QUAD0, BPCMRegOffset(sr_control), &reg);
+    reg |= 0xff;
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC_QUAD0, BPCMRegOffset(sr_control), reg);
+
+    status |=  ReadBPCMRegister(PMB_ADDR_XRDP_RC_QUAD1, BPCMRegOffset(sr_control), &reg);
+    reg |= 0xff;
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC_QUAD1, BPCMRegOffset(sr_control), reg);
+
+    status |=  ReadBPCMRegister(PMB_ADDR_XRDP_RC_QUAD2, BPCMRegOffset(sr_control), &reg);
+    reg |= 0xff;
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC_QUAD2, BPCMRegOffset(sr_control), reg);
+
+    status |=  ReadBPCMRegister(PMB_ADDR_XRDP_RC_QUAD3, BPCMRegOffset(sr_control), &reg);
+    reg |= 0xff;
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC_QUAD3, BPCMRegOffset(sr_control), reg);
+
+    if(status)
+    {
+        PRINTK("failed Toggle reset of XRDP core to 0xff...\n");
+        return status;
+    }
+
+    apply_ubus_credit_each_master(UBUS_PORT_ID_QM);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_DQM);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_NATC);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_DMA0);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_DMA1);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_RQ0);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_RQ1);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_RQ2);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_RQ3);
+
+    ubus_master_rte_cfg();
+
+#elif IS_BCMCHIP(63158) || IS_BCMCHIP(6856)
+
+    status =  PowerOnDevice(PMB_ADDR_XRDP);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP status[%d]\n",status);
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC0);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC0\n");
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC1);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC1\n");
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC2);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC2\n");
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC3);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC3\n");
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC4);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC4\n");
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC5);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC5\n");
+        return status;
+    }
+
+#if IS_BCMCHIP(6856)
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC6);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC4\n");
+        return status;
+    }
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC7);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice XRDP_RC5\n");
+        return status;
+    }
+    PRINTK("Toggle reset of XRDP core...\n");
+    status = WriteBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), 0x7);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC0, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC1, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC2, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC3, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC4, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC5, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC6, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC7, BPCMRegOffset(sr_control), 0); 
+    if (status)
+    {
+        PRINTK("failed Toggle reset of XRDP core to zero...\n");
+        return status;
+    }
+
+    status = WriteBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC0, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC1, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC2, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC3, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC4, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC5, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC6, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC7, BPCMRegOffset(sr_control), 0xfffffff); 
+    if (status)
+    {
+        PRINTK("failed Toggle reset of XRDP core to 0xffffffff...\n");
+        return status;
+    }
+#endif
+    status = PowerOnDevice(PMB_ADDR_WAN);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice PMB_ADDR_WAN\n");
+        return status;
+    }
+
+    PRINTK("Toggle reset of XRDP core...\n");
+    status = WriteBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), 0x7);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC0, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC1, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC2, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC3, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC4, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC5, BPCMRegOffset(sr_control), 0);
+
+    if (status)
+    {
+        PRINTK("failed Toggle reset of XRDP core to zero...\n");
+        return status;
+    }
+
+    status = WriteBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC0, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC1, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC2, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC3, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC4, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC5, BPCMRegOffset(sr_control), 0xfffffff);
+
+    if (status)
+    {
+        PRINTK("failed Toggle reset of XRDP core to 0xffffffff...\n");
+        return status;
+    }
+#elif IS_BCMCHIP(6846)
+    status = PowerOnDevice(PMB_ADDR_XRDP);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice PMB_ADDR_XRDP\n");
+        return status;
+    }
+
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC0);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice PMB_ADDR_XRDP_RC0\n");
+        return status;
+    }
+
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC1);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice PMB_ADDR_XRDP_RC1\n");
+        return status;
+    }
+
+    status = PowerOnDevice(PMB_ADDR_XRDP_RC2);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice PMB_ADDR_XRDP_RC2\n");
+        return status;
+    }
+
+    status = PowerOnDevice(PMB_ADDR_WAN);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice PMB_ADDR_WAN\n");
+        return status;
+    }
+
+    PRINTK("Toggle reset of XRDP core...\n");
+    status = WriteBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), 0x7);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC0, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC1, BPCMRegOffset(sr_control), 0);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC2, BPCMRegOffset(sr_control), 0);
+
+    if (status)
+    {
+        PRINTK("failed Toggle reset of XRDP core to zero...\n");
+        return status;
+    }
+
+    status = WriteBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC0, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC1, BPCMRegOffset(sr_control), 0xfffffff);
+    status |= WriteBPCMRegister(PMB_ADDR_XRDP_RC2, BPCMRegOffset(sr_control), 0xfffffff);
+
+    if (status)
+    {
+        PRINTK("failed Toggle reset of XRDP core to 0xffffffff...\n");
+        return status;
+    }
+#elif IS_BCMCHIP(6878) || IS_BCMCHIP(63146) || IS_BCMCHIP(4912)
+    status = PowerOnDevice(PMB_ADDR_XRDP);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice PMB_ADDR_XRDP\n");
+        return status;
+    }
+
+#if IS_BCMCHIP(6878)
+    status = PowerOnDevice(PMB_ADDR_WAN);
+    if(status)
+    {
+        PRINTK("Failed to PowerOnDevice PMB_ADDR_WAN\n");
+        return status;
+    }
+#endif
+
+    PRINTK("Toggle reset of XRDP core...\n");
+    status = WriteBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), 0x7);
+    if (status)
+    {
+        PRINTK("failed Toggle reset of XRDP core to zero...\n");
+        return status;
+    }
+
+    status = WriteBPCMRegister(PMB_ADDR_XRDP, BPCMRegOffset(sr_control), 0xfffffff);
+    if (status)
+    {
+        PRINTK("failed Toggle reset of XRDP core to 0xffffffff...\n");
+        return status;
+    }
+#else
+    PRINTK("%s is not implemented in platform yet!\n", __FUNCTION__);
+#endif
+
+#if IS_BCMCHIP(63158)
+    apply_ubus_credit_each_master(UBUS_PORT_ID_QM);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_DQM);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_NATC);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_DMA0);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_RQ0);
+    apply_ubus_credit_each_master(UBUS_PORT_ID_SWH);
+#endif
+#if defined(CONFIG_BCM_UBUS4_DCM)
+    ubus_cong_threshold_wr(UBUS_PORT_ID_QM, 0);
+    ubus_cong_threshold_wr(UBUS_PORT_ID_DQM, 0);
+    ubus_cong_threshold_wr(UBUS_PORT_ID_NATC, 0);
+    ubus_cong_threshold_wr(UBUS_PORT_ID_DMA0, 0);
+    ubus_cong_threshold_wr(UBUS_PORT_ID_RQ0, 0);
+#if IS_BCMCHIP(63158)
+    ubus_cong_threshold_wr(UBUS_PORT_ID_SWH, 0);
+#elif IS_BCMCHIP(6858)
+    ubus_cong_threshold_wr(UBUS_PORT_ID_DMA1, 0);
+    ubus_cong_threshold_wr(UBUS_PORT_ID_RQ1, 0);
+    ubus_cong_threshold_wr(UBUS_PORT_ID_RQ2, 0);
+    ubus_cong_threshold_wr(UBUS_PORT_ID_RQ3, 0);
+#elif IS_BCMCHIP(6856)
+    ubus_cong_threshold_wr(UBUS_PORT_ID_DMA1, 0);
+    ubus_cong_threshold_wr(UBUS_PORT_ID_RQ1, 0);
+#endif
+#endif
+
+    return status;
+}
+
+int pmc_xrdp_shutdown(void)
+{
+    int status = 0;
+#if IS_BCMCHIP(6858)
+    status =  PowerOffDevice(PMB_ADDR_XRDP, 0);
+    if(status)
+    {
+        PRINTK("Failed to PowerOffDevice XRDP\n");
+        return status;
+    }
+    status = PowerOffDevice(PMB_ADDR_XRDP_QM, 0);
+    if(status)
+    {
+        PRINTK("Failed to PowerOffDevice XRDP_QM\n");
+        return status;
+    }
+    status = PowerOffDevice(PMB_ADDR_XRDP_RC_QUAD0, 0);
+    if(status)
+    {
+        PRINTK("Failed to PowerOffDevice XRDP_RC_QUAD0\n");
+        return status;
+    }
+    status = PowerOffDevice(PMB_ADDR_XRDP_RC_QUAD1, 0);
+    if(status)
+    {
+        PRINTK("Failed to PowerOffDevice XRDP_RC_QUAD1\n");
+        return status;
+    }
+    status = PowerOffDevice(PMB_ADDR_XRDP_RC_QUAD2, 0);
+    if(status)
+    {
+        PRINTK("Failed to PowerOffDevice XRDP_RC_QUAD2\n");
+        return status;
+    }
+    status = PowerOffDevice(PMB_ADDR_XRDP_RC_QUAD3, 0);
+    if(status)
+    {
+        PRINTK("Failed to PowerOffDevice XRDP_RC_QUAD3\n");
+        return status;
+    }
+#else
+    PRINTK("%s is not implemented in platform yet!\n", __FUNCTION__);
+#endif
+
+    return status;
+}
+
+#if !defined(_CFE_) && !defined(__UBOOT__)
+EXPORT_SYMBOL(pmc_xrdp_init);
+postcore_initcall(pmc_xrdp_init);
+#endif
diff --git a/arch/arm/mach-bcmbca/pmc/pmc_xrdp.h b/arch/arm/mach-bcmbca/pmc/pmc_xrdp.h
new file mode 100755
index 0000000000..a2a84607f8
--- /dev/null
+++ b/arch/arm/mach-bcmbca/pmc/pmc_xrdp.h
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+
+*/
+/*
+ * pmc_xrdp.h
+ *
+ *  Created on: 17 Nov 2015
+ *      Author: yonatani
+ */
+
+#ifndef _PMC_XRDP_H_
+#define _PMC_XRDP_H_
+
+int pmc_xrdp_init(void);
+int pmc_xrdp_shutdown(void);
+
+#endif /* _PMC_XRDP_H_ */
diff --git a/arch/arm/mach-bcmbca/rdp/Makefile b/arch/arm/mach-bcmbca/rdp/Makefile
new file mode 100755
index 0000000000..76be020953
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/Makefile
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+KBUILD_CPPFLAGS += -DLEGACY_RDP -DRDD_BASIC -DBCM_DSL_RDP
+
+ifdef CONFIG_BCM63138
+KBUILD_CPPFLAGS += -DDSL_63138
+endif
+
+ifdef CONFIG_BCM63148
+KBUILD_CPPFLAGS += -DDSL_63148
+endif
+
+UBOOTINCLUDE += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/$(subst \",,$(CONFIG_SYS_SOC))/rdp_fw
+
+obj-y +=				\
+	unimac_drv_impl1.o		\
+	rdp_bbh_arrays.o		\
+	rdp_dma_arrays.o		\
+	rdp_drv_ih.o			\
+	rdp_drv_bpm.o			\
+	rdp_drv_sbpm.o			\
+	rdp_drv_bbh.o			\
+	rdp_cpu_ring.o			\
+	rdp_misc.o			\
+	rdd_cpu.o			\
+	rdd_init.o			\
+	rdd_tm.o			\
+	rdd_common.o			\
+	data_path_init.o		\
diff --git a/arch/arm/mach-bcmbca/rdp/access_macros.h b/arch/arm/mach-bcmbca/rdp/access_macros.h
new file mode 100755
index 0000000000..f91a1f1761
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/access_macros.h
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef __ACCESS_MACROS_H_INCLUDED
+
+#define __ACCESS_MACROS_H_INCLUDED
+
+#define RDP_BLOCK_SIZE          0x1000000
+#define WAN_BLOCK_ADDRESS_MASK  0xFFFF
+
+#if defined(__ARMEL__) || defined(BCM_DSL_RDP)
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+#define _BYTE_ORDER_LITTLE_ENDIAN_
+#endif
+#ifndef FIRMWARE_LITTLE_ENDIAN
+#define FIRMWARE_LITTLE_ENDIAN
+#endif
+#endif
+
+#if defined(__ARMEL__) || defined(BCM_DSL_RDP)
+#define SOC_BASE_ADDRESS        0x00000000
+#else
+#define SOC_BASE_ADDRESS		0xA0000000
+#endif
+
+#if !defined(FIRMWARE_INIT) && !defined(USE_SOC_BASE_ADDR)
+#define DEVICE_ADDRESS(_a) ( (SOC_BASE_ADDRESS) | ((uintptr_t)_a))
+#else /*FIRMWARE_INIT || USE_SOC_BASE_ADDR:*/
+extern uint8_t *soc_base_address;
+#define DEVICE_ADDRESS(_a) ( (volatile uint8_t * const) (soc_base_address + ((uint32_t)(_a) & 0xFFFFF)) )
+#endif
+
+#ifndef FSSIM
+
+#if defined LINUX_KERNEL
+ #include <linux/types.h>
+ #include <asm/barrier.h>
+ #define WMB()	wmb()
+#else
+ #define WMB()	/* */
+#endif
+
+/* This is a temporary fix and must be removed once table manager is fixed */
+#define FIELD_MREAD_I_32(p, x, y, i, r)
+
+static inline uint16_t __swap2bytes(uint16_t a)
+{
+    return ( a << 8 ) | ( a >> 8 );
+}
+static inline uint32_t __swap4bytes(uint32_t a)
+{
+    return ( ( a << 24 ) |
+             ( ( a & 0xFF00 ) << 8 ) |
+             ( ( a & 0xFF0000 ) >> 8 ) |
+             ( a >> 24 ) );
+}
+
+#if defined(FIRMWARE_LITTLE_ENDIAN)
+#if defined(__ARMEL__) || defined(__AARCH64EL__)
+static inline uint16_t swap2bytes(uint16_t a)
+{
+    __asm__("rev16 %0, %1" : "=r" (a) : "r" (a));
+    return a;
+}
+
+#if defined(__ARMEL__)
+static inline uint32_t swap4bytes(uint32_t a)
+{
+    __asm__("rev %0, %1" : "=r" (a) : "r" (a));
+    return a;
+}
+
+#define READ_RX_DESC(_desc_ptr, _w0, _w1, _w2) \
+	__asm__("ldm	%0, {%1, %2, %3}" \
+		: "=r" (_desc_ptr), "=r" (_w0), "=r" (_w1), "=r" (_w2) \
+		: "0" (_desc_ptr))
+#else /* defined(__AARCH64EL__) */
+static inline uint32_t swap4bytes(uint32_t a)
+{
+    __asm__("rev32 %0, %1" : "=r" (a) : "r" (a));
+    return a;
+}
+
+/* reverses the 4 bytes in each 32-bit element of Xm*/
+static inline uint64_t swap4bytes64(uint64_t a)
+{
+    __asm__("rev32 %0, %1" : "=r" (a) : "r" (a));
+    return a;
+}
+
+#define READ_RX_DESC(_desc_ptr, _dw0, _dw1) \
+	__asm__("ldnp	%1, %2, [%0]" \
+		: "=r" (_desc_ptr), "=r" (_dw0), "=r" (_dw1) \
+		: "0" (_desc_ptr))
+#endif
+
+#else
+#define swap2bytes(a) __swap2bytes(a)
+#define swap4bytes(a) __swap4bytes(a)
+#endif /* __ARMEL__ */
+
+#else /* FIRMWARE_LITTLE_ENDIAN */
+#define swap2bytes(a)           ( a )
+#define swap4bytes(a)           ( a )
+#endif /* FIRMWARE_LITTLE_ENDIAN */
+
+/*
+ * Endian swapping macros that work on any CPU.
+ * Swap between CPU byte order and Big Endian byte order
+ */
+#if defined(_BYTE_ORDER_LITTLE_ENDIAN_) || \
+    (defined(__BYTE_ORDER) && defined(__LITTLE_ENDIAN) && __BYTE_ORDER == __LITTLE_ENDIAN) || \
+    (defined(__BYTE_ORDER__) && defined(__LITTLE_ENDIAN__) && __BYTE_ORDER__ == __LITTLE_ENDIAN__)
+
+#define cpu_be_swap_16(x)   swap2bytes(x)
+#define cpu_be_swap_32(x)   swap4bytes(x)
+
+#else
+
+#define cpu_be_swap_16(x)   (x)
+#define cpu_be_swap_32(x)   (x)
+
+#endif
+
+
+/* The following group of macros are for register access only.
+   Please don't use them to read/write memory - they are unsafe
+*/
+#if defined(FIRMWARE_LITTLE_ENDIAN)
+
+#define VAL32(_a)               ( *(volatile uint32_t*)(DEVICE_ADDRESS(_a)) )
+#define READ_8(a, r)            ( *(volatile uint8_t*) &(r) = *(volatile uint8_t* ) DEVICE_ADDRESS(a) )
+#define READ_16(a, r)           do { \
+                                       uint16_t u16 = *(volatile uint16_t*) DEVICE_ADDRESS(a); \
+                                       *(volatile uint16_t*)&(r) = swap2bytes(u16); \
+                                } while(0)
+#define READ_32(a, r)           do { \
+                                       uint32_t u32 = *(volatile uint32_t*) DEVICE_ADDRESS(a); \
+                                       *(volatile uint32_t*)&(r) = swap4bytes(u32); \
+                                } while(0)
+
+#define WRITE_8( a, r)			( *(volatile uint8_t* )DEVICE_ADDRESS(a) = *(uint8_t* )&(r) )
+#define WRITE_16(a, r)			( *(volatile uint16_t*)DEVICE_ADDRESS(a) = swap2bytes(*(uint16_t*)&(r) ))
+#define WRITE_32(a, r)			( *(volatile uint32_t*)DEVICE_ADDRESS(a) = swap4bytes(*(uint32_t*)&(r) ))
+
+#define READ_I_8(a, i, r)		( *(volatile uint8_t* )&(r) = *((volatile uint8_t* ) DEVICE_ADDRESS(a) + (i)) )
+#define READ_I_16(a, i, r)		do { \
+                                    uint16_t u16 = *((volatile uint16_t*) DEVICE_ADDRESS(a) + (i)); \
+                                    *(volatile uint16_t*)&(r) = swap2bytes(u16); \
+                                } while(0)
+#define READ_I_32(a, i, r)		do { \
+                                    uint32_t u32 = *((volatile uint32_t*) DEVICE_ADDRESS(a) + (i)); \
+                                    *(volatile uint32_t*)&(r) = swap4bytes(u32); \
+                                } while(0)
+
+#define WRITE_I_8( a, i, r )    ( *((volatile uint8_t* ) DEVICE_ADDRESS(a) + (i)) = *(uint8_t*) &(r) )
+#define WRITE_I_16( a, i, r )	( *((volatile uint16_t*) DEVICE_ADDRESS(a) + (i)) = swap2bytes(*(uint16_t*)&(r) ))
+#define WRITE_I_32( a, i, r )	( *((volatile uint32_t*) DEVICE_ADDRESS(a) + (i)) = swap4bytes(*(uint32_t*)&(r) ))
+
+#else
+
+#define VAL32(_a) 				( *(volatile uint32_t*)(DEVICE_ADDRESS(_a)) )
+#define READ_8(a, r)			( *(volatile uint8_t*) &(r) = *(volatile uint8_t* ) DEVICE_ADDRESS(a) )
+#define READ_16(a, r)			( *(volatile uint16_t*)&(r) = *(volatile uint16_t*) DEVICE_ADDRESS(a) )
+#define READ_32(a, r)			( *(volatile uint32_t*)&(r) = *(volatile uint32_t*) DEVICE_ADDRESS(a) )
+
+#define WRITE_8( a, r)			( *(volatile uint8_t* )DEVICE_ADDRESS(a) = *(uint8_t* )&(r) )
+#define WRITE_16(a, r)			( *(volatile uint16_t*)DEVICE_ADDRESS(a) = *(uint16_t*)&(r) )
+#define WRITE_32(a, r)			( *(volatile uint32_t*)DEVICE_ADDRESS(a) = *(uint32_t*)&(r) )
+
+#define READ_I_8(a, i, r)		( *(volatile uint8_t* )&(r) = *((volatile uint8_t* ) DEVICE_ADDRESS(a) + (i)) )
+#define READ_I_16(a, i, r)		( *(volatile uint16_t*)&(r) = *((volatile uint16_t*) DEVICE_ADDRESS(a) + (i)) )
+#define READ_I_32(a, i, r)		( *(volatile uint32_t*)&(r) = *((volatile uint32_t*) DEVICE_ADDRESS(a) + (i)) )
+
+#define WRITE_I_8( a, i, r )		( *((volatile uint8_t* ) DEVICE_ADDRESS(a) + (i)) = *(uint8_t*) &(r) )
+#define WRITE_I_16( a, i, r )	( *((volatile uint16_t*) DEVICE_ADDRESS(a) + (i)) = *(uint16_t*)&(r) )
+#define WRITE_I_32( a, i, r )	( *((volatile uint32_t*) DEVICE_ADDRESS(a) + (i)) = *(uint32_t*)&(r) )
+
+#endif
+
+#define BL_READ_32(a,r) READ_32(a,r)
+#define BL_WRITE_32(a,r) WRITE_32(a,r)
+#define BL_WRITE_I_32( a, i, r ) WRITE_I_32( a, i, r )
+#define BL_READ_I_32(a, i, r) READ_I_32(a, i, r)
+
+/* The following group of macros are intended for shared/io memory access
+*/
+
+#define MGET_8(a )              ( *(volatile uint8_t* )(a) )
+#define MGET_16(a)              swap2bytes( *(volatile uint16_t*)(a) )
+#define MGET_32(a)              swap4bytes( *(volatile uint32_t*)(a) )
+
+#define MREAD_8( a, r)			( (r) = MGET_8( a ) )
+#define MREAD_16(a, r)			( (r) = MGET_16( a ) )
+#define MREAD_32(a, r)			( (r) = MGET_32( a ) )
+
+#define MWRITE_8( a, r )        ( *(volatile uint8_t *)(a) = (uint8_t) (r))
+#define MWRITE_16( a, r )       ( *(volatile uint16_t*)(a) = swap2bytes((uint16_t)(r)))
+#define MWRITE_32( a, r )       ( *(volatile uint32_t*)(a) = swap4bytes((uint32_t)(r)))
+
+#define MGET_I_8( a, i)         ( *((volatile uint8_t *)(a) + (i)) )
+#define MGET_I_16(a, i)         swap2bytes( *((volatile uint16_t*)(a) + (i)) )
+#define MGET_I_32(a, i)         swap4bytes( *((volatile uint32_t*)(a) + (i)) )
+
+#define MREAD_I_8( a, i, r)		( (r) = MGET_I_8( (a),(i)) )
+#define MREAD_I_16(a, i, r)		( (r) = MGET_I_16((a),(i)) )
+#define MREAD_I_32(a, i, r)		( (r) = MGET_I_32((a),(i)) )
+
+#define MWRITE_I_8( a, i, r)    ( *((volatile uint8_t *)(a) + (i)) = (uint8_t)(r) )
+#define MWRITE_I_16(a, i, r)    ( *((volatile uint16_t*)(a) + (i)) = swap2bytes((uint16_t)(r)) )
+#define MWRITE_I_32(a, i, r)    ( *((volatile uint32_t*)(a) + (i)) = swap4bytes((uint32_t)(r)) )
+
+/* Set block of shared memory to the specified value */
+#define MEMSET(a, v, sz)				memset(a, v, sz)
+
+/* Copy memory block local memory --> shared memory */
+#define MWRITE_BLK_8(d, s, sz )      memcpy(d, s, sz)
+#define MWRITE_BLK_16(d, s, sz)      { uint32_t i, val; for ( i = 0; i < ( sz / 2 ); i++ ){ val = *((volatile uint16_t*)(s) + (i)); MWRITE_I_16( d, i, val ); } }
+#define MWRITE_BLK_32(d, s, sz)      { uint32_t i, val; for ( i = 0; i < ( sz / 4 ); i++ ){ val = *((volatile uint32_t*)(s) + (i)); MWRITE_I_32( d, i, val ); } }
+
+/* Copy memory block shared memory --> local memory */
+#define MREAD_BLK_8(d, s, sz )   	    memcpy(d, s, sz)
+#define MREAD_BLK_16(d, s, sz)  		memcpy(d, s, sz)
+#define MREAD_BLK_32(d, s, sz)  		memcpy(d, s, sz)
+
+#else
+ #define WMB() 	/* */
+ /* Simulation environment */
+ #include <access_macros_fssim.h>
+
+#endif /* #ifdef FSSIM */
+
+/* Bit-field access macros
+: v		-  value
+: lsbn	- ls_bit_number
+: fw	- field_width
+: a     - address
+: rv	- read_value
+ */
+#define FIELD_GET(v, lsbn, fw)			( ((v)>>(lsbn)) & ((unsigned)(1 << (fw)) - 1) )
+
+#define FIELD_MGET_32(a, lsbn, fw)		( FIELD_GET( MGET_32(a), (lsbn), (fw)) )
+#define FIELD_MGET_16(a, lsbn, fw)      ( FIELD_GET( MGET_16(a), (lsbn), (fw)) )
+#define FIELD_MGET_8( a, lsbn, fw)		( FIELD_GET( MGET_8(a) , (lsbn), (fw)) )
+
+#define FIELD_MREAD_8( a, lsbn, fw, rv)	( rv = FIELD_MGET_8( (a),   (lsbn), (fw)) )
+#define FIELD_MREAD_16(a, lsbn, fw, rv)	( rv = FIELD_MGET_16((a),   (lsbn), (fw)) )
+#define FIELD_MREAD_32(a, lsbn, fw, rv)	( rv = FIELD_MGET_32((a),   (lsbn), (fw)) )
+
+#define SWAPBYTES(buffer,len) do {uint8_t _i; for(_i = 0; _i < len; _i += sizeof(uint32_t)) *((uint32_t *)(&(buffer[_i]))) = swap4bytes(*((uint32_t *)(&(buffer[_i]))));} while(0)
+
+#define FIELD_SET( value, ls_bit_number, field_width, write_value )     \
+        do {                                                           \
+            uint32_t  mask;                                             \
+            mask = ( ( 1U << (field_width) ) - 1 ) << (ls_bit_number);   \
+            value &=  ~mask;                                            \
+            value |= (write_value) << (ls_bit_number);                  \
+        } while(0)
+
+#define FIELD_MWRITE_32( address, ls_bit_number, field_width, write_value )     \
+        do {                                                                    \
+            uint32_t  current_value = MGET_32(address);            			    \
+            FIELD_SET(current_value, ls_bit_number, field_width, write_value ); \
+            MWRITE_32(address, current_value);                                  \
+        } while(0)
+
+#define FIELD_MWRITE_16( address, ls_bit_number, field_width, write_value)      \
+        do{                                                                     \
+            uint16_t  current_value = MGET_16(address);                         \
+            FIELD_SET(current_value, ls_bit_number, field_width, write_value);  \
+            MWRITE_16(address, current_value);                                  \
+        } while(0)
+
+#define FIELD_MWRITE_8( address, ls_bit_number, field_width, write_value )      \
+        do{                                                                     \
+            uint8_t  current_value = MGET_8(address);                           \
+            FIELD_SET(current_value, ls_bit_number, field_width, write_value);  \
+            MWRITE_8(address, current_value);                                   \
+        } while(0)
+
+
+#define GROUP_MREAD_I_8(group, addr, i, ret) (ret = _rdd_i_read(group, (addr), i, rdd_size_8))
+#define GROUP_MREAD_I_16(group, addr, i, ret) (ret = _rdd_i_read(group, (addr), i, rdd_size_16))
+#define GROUP_MREAD_I_32(group, addr, i, ret) (ret = _rdd_i_read(group, (addr), i, rdd_size_32))
+
+#define GROUP_MREAD_8(group, addr, ret) (ret = _rdd_i_read(group, (addr), 0, rdd_size_8))
+#define GROUP_MREAD_16(group, addr, ret) (ret = _rdd_i_read(group, (addr), 0, rdd_size_16))
+#define GROUP_MREAD_32(group, addr, ret) (ret = _rdd_i_read(group, (addr), 0, rdd_size_32))
+
+#define GROUP_FIELD_MREAD_8(group, addr, lsb, width, ret) (ret = _rdd_field_read(group, (addr), lsb, rdd_size_8))
+#define GROUP_FIELD_MREAD_16(group, addr, lsb, width, ret) (ret = _rdd_field_read(group, (addr), lsb, rdd_size_16))
+#define GROUP_FIELD_MREAD_32(group, addr, lsb, width, ret) (ret = _rdd_field_read(group, (addr), lsb, rdd_size_32))
+
+#define GROUP_MWRITE_I_8(group, addr, i, val) _rdd_i_write(group, (addr), val, i, rdd_size_8)
+#define GROUP_MWRITE_I_16(group, addr, i, val) _rdd_i_write(group, (addr), val, i, rdd_size_16)
+#define GROUP_MWRITE_I_32(group, addr, i, val) _rdd_i_write(group, (addr), val, i, rdd_size_32)
+
+#define GROUP_MWRITE_8(group, addr, val) _rdd_i_write(group, (addr), val, 0, rdd_size_8)
+#define GROUP_MWRITE_16(group, addr, val) _rdd_i_write(group, (addr), val, 0, rdd_size_16)
+#define GROUP_MWRITE_32(group, addr, val) _rdd_i_write(group, (addr), val, 0, rdd_size_32)
+
+#define GROUP_FIELD_MWRITE_8(group, addr, lsb, width, val) _rdd_field_write(group, (addr), val, lsb, width, rdd_size_8)
+#define GROUP_FIELD_MWRITE_16(group, addr, lsb, width, val) _rdd_field_write(group, (addr), val, lsb, width, rdd_size_16)
+#define GROUP_FIELD_MWRITE_32(group, addr, lsb, width, val) _rdd_field_write(group, (addr), val, lsb, width, rdd_size_32)
+
+#endif /* __ACCESS_MACROS_H_INCLUDED */
diff --git a/arch/arm/mach-bcmbca/rdp/bcm_mm.h b/arch/arm/mach-bcmbca/rdp/bcm_mm.h
new file mode 100755
index 0000000000..5de1747692
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/bcm_mm.h
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2013 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the Broadcom OS/CPU independent Memory Management API   */
+/*                                                                            */
+/******************************************************************************/
+
+#ifndef _BCM_MM_H_
+#define _BCM_MM_H_
+
+#if defined(__UBOOT__)
+
+#include <common.h>
+
+#define VIRT_TO_PHYS(_addr)				((unsigned int)_addr)
+#define PHYS_TO_CACHED(_addr)				((void *)((unsigned int)_addr))
+#define PHYS_TO_UNCACHED(_addr)				((void *)((unsigned int)_addr))
+
+#define CACHED_MALLOC_ATOMIC(_size) 			malloc(_size)
+#define CACHED_MALLOC(_size) 				malloc(_size)
+#define CACHED_FREE(_ptr)				free(_ptr)
+#define NONCACHED_MALLOC_ATOMIC(_size) 			noncached_alloc(_size, 64)
+#define NONCACHED_MALLOC(_size) 			noncached_alloc(_size, 64)
+#define NONCACHED_FREE(_ptr) 				(_ptr)
+
+#define KMALLOC(_size, _align)				memalign(_align, _size)
+#define KFREE(_ptr)					free(_ptr)
+
+#if defined(CONFIG_BCM6858) || defined(CONFIG_BCM63148) || \
+    defined(CONFIG_BCM6846) || defined(CONFIG_BCM6856) || defined(CONFIG_BCM6878)
+#define DMA_CACHE_LINE					64
+#else
+#define DMA_CACHE_LINE					32
+#endif
+
+#define FLUSH_RANGE(s,l) 				({unsigned long start, end;	\
+				start = ((unsigned long)(s))&~(DMA_CACHE_LINE-1);			\
+				end = (((unsigned long)(s)+(l)) + DMA_CACHE_LINE - 1)&~(DMA_CACHE_LINE-1); \
+				flush_dcache_range(start, end);	})
+
+#define INV_RANGE(s,l) 					({unsigned long start, end;	\
+				start = ((unsigned long)(s))&~(DMA_CACHE_LINE-1); \
+				end = (((unsigned long)(s)+(l)) + DMA_CACHE_LINE - 1)&~(DMA_CACHE_LINE-1); \
+				invalidate_dcache_range(start, end);	})
+#elif defined(__KERNEL__)
+
+#if defined(CONFIG_MIPS)
+
+#define CACHE_TO_NONCACHE(x)    			KSEG1ADDR(x)
+#define NONCACHE_TO_CACHE(x)    			KSEG0ADDR(x)
+#define CACHED_MALLOC_ATOMIC(_size) 			kmalloc(_size,GFP_ATOMIC)
+#define CACHED_MALLOC(_size) 				kmalloc(_size,GFP_KERNEL)
+#define CACHED_FREE(ptr) 				kfree((void*)ptr)
+#define NONCACHED_MALLOC_ATOMIC(_size) 			CACHE_TO_NONCACHE(kmalloc(_size,GFP_ATOMIC|__GFP_DMA))
+#define NONCACHED_MALLOC(_size) 			CACHE_TO_NONCACHE(kmalloc(_size,GFP_ATOMIC|__GFP_DMA))
+#define NONCACHED_FREE(_ptr) 				kfree((void*)NONCACHE_TO_CACHE(_ptr))
+#ifdef VIRT_TO_PHYS
+#undef VIRT_TO_PHYS
+#endif
+#define VIRT_TO_PHYS(_addr)				CPHYSADDR(_addr)
+#define PHYS_TO_CACHED(_addr)				KSEG0ADDR(_addr)
+#define PHYS_TO_UNCACHED(_addr)				KSEG1ADDR(_addr)
+#define FLUSH_RANGE(_addr, _size) 			blast_dcache_range(_addr, _addr+_size)
+#define INV_RANGE(_addr, _size) 			blast_inv_dcache_range((uint32_t)_addr, (uint32_t)_addr+_size)
+
+#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+
+#define CACHE_TO_NONCACHE(x)    			(x)
+#define NONCACHE_TO_CACHE(x)    			(x)
+#define CACHED_MALLOC_ATOMIC(_size) 			kmalloc(_size,GFP_ATOMIC)
+#define CACHED_MALLOC(_size) 				kmalloc(_size,GFP_KERNEL)
+#define CACHED_FREE(ptr) 				kfree((void*)ptr)
+#ifdef CONFIG_PLAT_BCM63XX_ACP
+/* will allocate an additional 4 bytes at the end to store the original virtual pointer */
+#define NONCACHED_MALLOC(_size, _phys_addr_ptr)		({void *_acp_addr_ptr = NULL;			\
+		void *_org_addr_ptr = dma_alloc_coherent(NULL, _size + sizeof(void *), _phys_addr_ptr, GFP_KERNEL|GFP_ACP);	\
+		if (_org_addr_ptr != NULL) {								\
+			_acp_addr_ptr = (void *)ACP_ADDRESS(*_phys_addr_ptr);				\
+			*(uintptr_t *)((uintptr_t)_acp_addr_ptr + _size) = (uintptr_t)_org_addr_ptr;	\
+		}											\
+		_acp_addr_ptr;		})
+#define NONCACHED_MALLOC_ATOMIC(_size, _phys_addr_ptr)	({void *_acp_addr_ptr = NULL;			\
+		void *_org_addr_ptr = dma_alloc_coherent(NULL, _size + sizeof(void *), _phys_addr_ptr, GFP_ATOMIC|GFP_ACP);	\
+		if (_org_addr_ptr != NULL) {								\
+			_acp_addr_ptr = (void *)ACP_ADDRESS(*_phys_addr_ptr);				\
+			*(uintptr_t *)((uintptr_t)_acp_addr_ptr + _size) = (uintptr_t)_org_addr_ptr;	\
+		}											\
+		_acp_addr_ptr;		})
+#define NONCACHED_FREE(_size, _ptr, _phys_addr)		({void *_org_addr_ptr;				\
+			_org_addr_ptr = (void *)(*(uintptr_t *)((uintptr_t)_ptr + _size));	\
+		dma_free_coherent(NULL, _size + 4, _org_addr_ptr, _phys_addr);	})
+#else
+#define NONCACHED_MALLOC_ATOMIC(_size, _phys_addr_ptr)	dma_alloc_coherent(NULL, _size, _phys_addr_ptr, GFP_ATOMIC)
+#define NONCACHED_MALLOC(_size, _phys_addr_ptr)		dma_alloc_coherent(NULL, _size, _phys_addr_ptr, GFP_KERNEL)
+#define NONCACHED_FREE(size, _ptr, _phys_addr)		dma_free_coherent(NULL, size, _ptr, _phys_addr)
+#endif
+#ifndef VIRT_TO_PHYS
+#define VIRT_TO_PHYS(_addr)				virt_to_phys((const volatile void *)_addr)
+#endif
+#define PHYS_TO_CACHED(_addr)				phys_to_virt((phys_addr_t)_addr)
+#define PHYS_TO_UNCACHED(_addr)				phys_to_virt((phys_addr_t)_addr)
+#define FLUSH_RANGE(_addr, _size) 			dma_map_single(NULL, (void *)_addr, _size, DMA_TO_DEVICE)
+#define INV_RANGE(_addr, _size) 			dma_map_single(NULL, (void *)_addr, _size, DMA_FROM_DEVICE)
+
+#endif
+
+#define DMA_CACHE_LINE					dma_get_cache_alignment()
+
+#else /* __KERNEL__ */
+#define CACHE_TO_NONCACHE(x)    			KSEG1ADDR(x)
+#define NONCACHE_TO_CACHE(x)    			KSEG0ADDR(x)
+#define VIRT_TO_PHYS(_addr)				CPHYSADDR(_addr)
+#define PHYS_TO_CACHED(_addr)				KSEG0ADDR(_addr)
+#define PHYS_TO_UNCACHED(_addr)				KSEG1ADDR(_addr)
+#endif
+
+#endif /* _BCM_MM_H_ */
diff --git a/arch/arm/mach-bcmbca/rdp/bcm_pkt_lengths.h b/arch/arm/mach-bcmbca/rdp/bcm_pkt_lengths.h
new file mode 100755
index 0000000000..51350ca3c1
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/bcm_pkt_lengths.h
@@ -0,0 +1,147 @@
+#ifndef __BCM_PKT_LENGTHS_H__
+#define __BCM_PKT_LENGTHS_H__
+
+
+/*TODO: makesure this file compiles when not for linux kernel also */
+
+
+/* this file is used to define the packet length for All platforms and
+   features at a common place */
+#if defined(CONFIG_BCM63148) || defined(CONFIG_BCM4908) || defined(CONFIG_BCM6858) || defined(CONFIG_BCM63158) || \
+    defined(CONFIG_BCM6846)  || defined(CONFIG_BCM47189) || defined(CONFIG_BCM6856) || defined(CONFIG_BCM63178) || \
+    defined(CONFIG_BCM47622) || defined(CONFIG_BCM6878) || defined(CONFIG_BCM6756)
+
+#define BCM_DCACHE_LINE_LEN	64ul
+#define BCM_DCACHE_ALIGN_LEN	63ul
+
+#elif defined(CONFIG_BCM63138)
+
+#define BCM_DCACHE_LINE_LEN	32
+#define BCM_DCACHE_ALIGN_LEN	31
+
+#else
+
+#define BCM_DCACHE_LINE_LEN	16
+#define BCM_DCACHE_ALIGN_LEN	15
+
+#endif
+
+
+#define BCM_DCACHE_ALIGN(len)  ((len + BCM_DCACHE_ALIGN_LEN) & ~BCM_DCACHE_ALIGN_LEN)
+
+#define GREATER(x, y)  (x>y ? x:y)
+
+
+ /* ############ MAX Packet payload size ############ */
+
+/*Ethernet */
+#define ENET_MAX_MTU_PAYLOAD_SIZE  (1500)  /* Ethernet Max Payload Size */
+
+/* XTM */
+#define XTM_MAX_MTU_PAYLOAD_SIZE    1500
+
+/* WLAN */
+
+#define WLAN_MAX_MTU_PAYLOAD_SIZE (1500)
+
+#if defined(CONFIG_BCM_USER_DEFINED_DEFAULT_MTU)
+    #if (CONFIG_BCM_USER_DEFINED_DEFAULT_MTU_SIZE > ENET_MAX_MTU_PAYLOAD_SIZE)
+    #error "ERROR - CONFIG_BCM_USER_DEFINED_DEFAULT_MTU_SIZE > ENET_MAX_MTU_PAYLOAD_SIZE"
+    #endif
+    #if (CONFIG_BCM_USER_DEFINED_DEFAULT_MTU_SIZE > XTM_MAX_MTU_PAYLOAD_SIZE)
+    #error "ERROR - CONFIG_BCM_USER_DEFINED_DEFAULT_MTU_SIZE > XTM_MAX_MTU_PAYLOAD_SIZE"
+    #endif
+
+    #define BCM_ENET_DEFAULT_MTU_SIZE CONFIG_BCM_USER_DEFINED_DEFAULT_MTU_SIZE
+    #define BCM_XTM_DEFAULT_MTU_SIZE  CONFIG_BCM_USER_DEFINED_DEFAULT_MTU_SIZE
+
+#else /* !CONFIG_BCM_USER_DEFINED_DEFAULT_MTU */
+
+    #define BCM_ENET_DEFAULT_MTU_SIZE ENET_MAX_MTU_PAYLOAD_SIZE
+    #define BCM_XTM_DEFAULT_MTU_SIZE  XTM_MAX_MTU_PAYLOAD_SIZE
+
+#endif
+
+
+/* select greater of XTM, WLAN, ENET and use it as MAX payload in system
+ * for buffer allocation purpose
+ */
+
+/*TODO check if compiler is replacing these checks with a final value, if not
+ select the MAX payload manually */
+
+#define BCM_MAX_MTU_PAYLOAD_SIZE GREATER( \
+								GREATER(ENET_MAX_MTU_PAYLOAD_SIZE, XTM_MAX_MTU_PAYLOAD_SIZE) \
+								,WLAN_MAX_MTU_PAYLOAD_SIZE)
+
+
+/* ############ space needed for L2 header ############ */
+#ifndef ENET_MAX_MTU_EXTRA_SIZE
+#define ENET_MAX_MTU_EXTRA_SIZE  (32) /* EH_SIZE(14) + VLANTAG(4) + VLANTAG(4) + BRCMTAG(6) + FCS(4) + Extra(??) (4)*/
+#endif
+
+/*select greater value*/
+#define BCM_MAX_MTU_EXTRA_SIZE    ENET_MAX_MTU_EXTRA_SIZE
+
+
+
+/* ############ Headroom needed in the packet ############ */
+
+/* this headroom is needed for WLAN header for  ENET,XTM,XPON ==> WLAN traffic */
+#define WLAN_TX_HEADROOM    208
+#define XTM_BONDING_HEADROOM       48
+#define GRE_HDR_LEN         16
+
+/* Headroom is a multiple of cacheline */
+#define BCM_PKT_HEADROOM  BCM_DCACHE_ALIGN(WLAN_TX_HEADROOM + GRE_HDR_LEN)
+
+
+/* ############ Tailroom needed in the packet ############ */
+
+#define BCM_SKB_TAILROOM	32
+
+/* ############ XRDP DMA Offset ############ */
+#if defined(CONFIG_BCM6858)
+#define DMA_MAX_OFFSET     128
+#else
+#define DMA_MAX_OFFSET     0   
+#endif
+
+#if defined(CONFIG_BCM47189)
+#define DMA_DATA_OFFSET 4
+#endif
+
+/* ############ Toatal length used for packets ############ */
+//#define BCM_MAX_PKT_LEN              BCM_MAX_MTU_EXTRA_SIZE + BCM_MAX_MTU_PAYLOAD_SIZE
+    /*align this to 64 bytes as Iudma may overwite, some bytes if not 64 byte aligned , bug in iudma*/
+#if defined(CONFIG_BCM_ENET_SYSPORT)
+
+    #define SYSPORT_MAX_PKT_LEN (2048)
+    #define SYSPORT_PKT_LEN_LOG2 (11)
+
+    #define CALC_MAX_PKT_LEN             ((DMA_MAX_OFFSET + BCM_MAX_MTU_EXTRA_SIZE + BCM_MAX_MTU_PAYLOAD_SIZE + 63) & ~63)
+    #if CALC_MAX_PKT_LEN > SYSPORT_MAX_PKT_LEN
+        #error "Error: CALC_MAX_PKT_LEN > SYSPORT_MAX_PKT_LEN"
+    #endif
+    #define BCM_MAX_PKT_LEN              SYSPORT_MAX_PKT_LEN
+
+#else
+/* This ignores the headroom in the BPM buffer otherwise it could be reduced.
+ It could be set to 1856 so that the headroom in the BPM buffer would be used. 
+ But to keep things simple and safe, max pkt len is assigned to PKTBUFSZ from
+ linux_osl.h */
+#define BCM_MAX_PKT_LEN               GREATER(2048, ((DMA_MAX_OFFSET + BCM_MAX_MTU_EXTRA_SIZE + BCM_MAX_MTU_PAYLOAD_SIZE + 63) & ~63))
+#endif 
+
+/* ############ Toatal buf size i.e BCM_MAX_PKT_LEN + metadata(fkb,skb_sharedinfo etc..) ############ */
+/* BCM_FKB_INPLACE, BCM_PKT_HEADROOM are always to be at cache-aligned boundaries */
+
+#define BCM_PKTBUF_SIZE             (BCM_DCACHE_ALIGN(BCM_MAX_PKT_LEN))
+
+/* ############ other common defines ############ */
+
+#define ENET_MIN_MTU_SIZE       60            /* Without FCS */
+#define ENET_MIN_MTU_SIZE_EXT_SWITCH       64            /* Without FCS */
+#define ENET_MAX_MTU_SIZE       (ENET_MAX_MTU_PAYLOAD_SIZE + ENET_MAX_MTU_EXTRA_SIZE)
+
+#endif /* __BCM_PKT_LENGTHS_H__ */
diff --git a/arch/arm/mach-bcmbca/rdp/bdmf_data_types.h b/arch/arm/mach-bcmbca/rdp/bdmf_data_types.h
new file mode 100755
index 0000000000..8f866092ca
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/bdmf_data_types.h
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ * 
+ */
+
+/*******************************************************************
+ * bdmf_types.h
+ *
+ * Broadcom Device Management Framework - built-in attribute types
+ *
+ *******************************************************************/
+
+#ifndef BDMF_DATA_TYPES_H_
+#define BDMF_DATA_TYPES_H_
+
+#if defined LINUX_KERNEL || __KERNEL__
+#include <linux/types.h>
+#include <linux/compat.h>
+#endif 
+
+/** Signed integer
+ */
+typedef int64_t bdmf_number;
+
+/** Index. Signed to allow special values. Long enough to enable casting to pointer
+ */
+
+#if (defined(__KERNEL__) || defined(BDMF_SYSTEM_SIM) || defined(RDP_SIM))
+typedef long bdmf_index;
+typedef unsigned long bdmf_ptr;
+#else
+#if defined KERNEL_64
+typedef uint64_t bdmf_index;
+typedef uint64_t bdmf_ptr;
+#else
+typedef long bdmf_index;
+typedef uint32_t bdmf_ptr;
+#endif /* KERNEL_64 */
+#endif /* __KERNEL__ */
+
+
+#define BDMF_INDEX_UNASSIGNED   (-1)    /**< "Unassigned" bdmf_index value */
+#define BDMF_INDEX_ANY          (-2)    /**< "Any" bdmf_index value */
+
+/** String */
+typedef char *bdmf_string;
+
+/** Ethernet address */
+typedef struct {
+    uint8_t b[6];  /**< Address bytes */
+} bdmf_mac_t;
+
+/** Check if MAC address is zero
+  * param[in]   ip  IP address
+  */
+static inline int bdmf_mac_is_zero(const bdmf_mac_t *mac)
+{
+    return !mac->b[0] && !mac->b[1] && !mac->b[2] && !mac->b[3] && !mac->b[4] && !mac->b[5];
+}
+
+/** Enumeration value */
+typedef long bdmf_enum;
+
+/** Boolean value */
+typedef char bdmf_boolean;
+
+/** IP address family */
+typedef enum {
+    bdmf_ip_family_ipv4,
+    bdmf_ip_family_ipv6
+} bdmf_ip_family;
+
+/** IPv4 address */
+typedef uint32_t bdmf_ipv4;
+
+/** IPv6 address */
+typedef struct
+{
+    uint8_t data[16];
+} bdmf_ipv6_t;
+
+/** IPv4 or IPv6 address */
+typedef struct {
+    bdmf_ip_family family;      /**< Address family: IPv4 / IPv6 */
+    union {
+        bdmf_ipv4 ipv4;         /**< IPv4 address */
+        bdmf_ipv6_t ipv6;       /**< IPv6 address */
+    } addr;
+} bdmf_ip_t;
+
+/** Check if IPv6 address is zero
+  * param[in]   ip  IPv6 address
+  */
+static inline int bdmf_ipv6_is_zero(const bdmf_ipv6_t *ipv6)
+{
+    uint32_t *ipv6_as_int = (uint32_t *)ipv6;
+    return !ipv6_as_int[0] && !ipv6_as_int[1] && !ipv6_as_int[2] && !ipv6_as_int[3];
+}
+
+/** Check if IP address is zero
+  * param[in]   ip  IP address
+  */
+static inline int bdmf_ip_is_zero(const bdmf_ip_t *ip)
+{
+    if (ip->family == bdmf_ip_family_ipv4)
+        return !ip->addr.ipv4;
+    return bdmf_ipv6_is_zero(&ip->addr.ipv6);
+}
+
+/** Compare IP addresses
+  * param[in]   ip  IP address
+  * param[in]   ip2  IP address
+  */
+static inline int bdmf_ip_cmp(const bdmf_ip_t *ip, const bdmf_ip_t *ip2)
+{
+    uint32_t *ipv6_as_int, *ipv6_as_int2;
+
+    if (ip->family != ip2->family)
+        return -1;
+    if (ip->family == bdmf_ip_family_ipv4)
+        return ip->addr.ipv4 != ip2->addr.ipv4;
+
+    ipv6_as_int = (uint32_t *)&ip->addr.ipv6;
+    ipv6_as_int2 = (uint32_t *)&ip2->addr.ipv6;
+    return !(ipv6_as_int[0] == ipv6_as_int2[0] && ipv6_as_int[1] == ipv6_as_int2[1] && 
+        ipv6_as_int[2] == ipv6_as_int2[2] && ipv6_as_int[3] == ipv6_as_int2[3]);
+}
+
+#if (defined(PHYS_ADDR_64BIT) || defined(CONFIG_PHYS_ADDR_T_64BIT)) && !defined(WL4908)
+typedef uint64_t bdmf_phys_addr_t;
+#else
+typedef uint32_t bdmf_phys_addr_t;
+#endif
+
+#endif /* BDMF_DATA_TYPES_H_ */
diff --git a/arch/arm/mach-bcmbca/rdp/bdmf_errno.h b/arch/arm/mach-bcmbca/rdp/bdmf_errno.h
new file mode 100755
index 0000000000..f10d8e9ecd
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/bdmf_errno.h
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ * 
+ */
+
+/*******************************************************************
+ * bdmf_errno.h
+ *
+ * BDMF framework - generic error codes
+ *
+ *******************************************************************/
+
+#ifndef BDMF_ERRNO_H
+
+#define BDMF_ERRNO_H
+
+/** \defgroup bdmf_errno Broadlight Error Codes
+ *
+ * This header files includes declaration of generic error codes and also
+ * support functions for adding additional error code ranges and
+ * conversion of error code to error message.
+ * @{
+ */
+
+/** Generic error codes
+ */
+typedef enum { 
+    BDMF_ERR_OK               =  0,   /**< OK */
+    BDMF_ERR_PARM             = -1,   /**< Error in parameters */
+    BDMF_ERR_NOMEM            = -2,   /**< No memory */
+    BDMF_ERR_NORES            = -3,   /**< No resources */
+    BDMF_ERR_INTERNAL         = -4,   /**< Internal error */
+    BDMF_ERR_NOENT            = -5,   /**< Entry doesn't exist */
+    BDMF_ERR_NODEV            = -6,   /**< Device doesn't exist */
+    BDMF_ERR_ALREADY          = -7,   /**< Entry already exists */
+    BDMF_ERR_RANGE            = -8,   /**< Out of range */
+    BDMF_ERR_PERM             = -9,   /**< No permission to perform an operation */
+    BDMF_ERR_NOT_SUPPORTED    = -10,  /**< Operation is not supported */
+    BDMF_ERR_PARSE            = -11,  /**< Parsing error */
+    BDMF_ERR_INVALID_OP       = -12,  /**< Invalid operation */
+    BDMF_ERR_IO               = -13,  /**< I/O error */
+    BDMF_ERR_STATE            = -14,  /**< Object is in bad state */
+    BDMF_ERR_DELETED          = -15,  /**< Object is deleted */
+    BDMF_ERR_TOO_MANY         = -16,  /**< Too many objects */
+    BDMF_ERR_NOT_LINKED       = -17,  /**< Objects are not linked */
+    BDMF_ERR_NO_MORE          = -18,  /**< No more entries */
+    BDMF_ERR_OVERFLOW         = -19,  /**< Buffer overflow */
+    BDMF_ERR_COMM_FAIL        = -20,  /**< Communication failure */
+    BDMF_ERR_NOT_CONNECTED    = -21,  /**< No connection with the target system */
+    BDMF_ERR_SYSCALL_ERR      = -22,  /**< System call returned error */
+    BDMF_ERR_MSG_ERROR        = -23,  /**< Received message is insane */
+    BDMF_ERR_TOO_MANY_REQS    = -24,  /**< Too many outstanding requests */
+    BDMF_ERR_NO_MSG_SERVER    = -25,  /**< Remote delivery error. No message server. */
+    BDMF_ERR_NO_LOCAL_SUBS    = -26,  /**< Local subsystem is not set */
+    BDMF_ERR_NO_SUBS          = -27,  /**< Subsystem is not recognised */
+    BDMF_ERR_INTR             = -28,  /**< Operation interrupted */
+    BDMF_ERR_HIST_RES_MISMATCH= -29,  /**< History result mismatch */
+    BDMF_ERR_MORE             = -30,  /**< More work to do */
+    BDMF_ERR_IGNORE           = -31,  /**< Ignore the error */
+    BDMF_ERR_LAST         = -100,    /**< Last generic error */
+} bdmf_error_t;
+
+/** Register error code range
+ *
+ * \param[in]   from        From number. Must be negative
+ * \param[in]   to          To number. Must be negative >from
+ * \param[in]   p_strerr    Callback that returns error string
+ *
+ * \returns  BDMF_ERR_OK      - OK\n
+ *           BDMF_ERR_PARM    - error in parameters\n
+ *           BDMF_ERR_NOMEM   - no memory
+ *           BDMF_ERR_ALREADY - ( from, to ) range overlaps with existing range
+ */
+bdmf_error_t bdmf_error_range_register(int from, int to,
+                                   const char *(*p_strerr)(int err));
+
+
+/** Unregister error code range
+ *
+ * \param[in]   from        From number. Must be negative
+ * \param[in]   to          To number. Must be negative >from
+ *
+ * \returns  BDMF_ERR_OK      - OK\n
+ *           BDMF_ERR_PARM    - error in parameters\n
+ *           BDMF_ERR_NOENT   - ( from, to ) range is not registered
+ */
+bdmf_error_t bdmf_error_range_unregister(int from, int to);
+
+
+/** Convert error code to error string
+ *
+ * \param[in]   err         Error code. One of bdmf_error_t constants or additional
+ *                          codes registered using bdmf_error_register()
+ * \returns Error string
+ */
+const char *bdmf_strerror(int err);
+
+/** @} */
+
+#endif /* #ifndef BDMF_ERRNO_H */
+
diff --git a/arch/arm/mach-bcmbca/rdp/bl_os_wraper.h b/arch/arm/mach-bcmbca/rdp/bl_os_wraper.h
new file mode 100755
index 0000000000..4f06e8d516
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/bl_os_wraper.h
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2012 Broadcom
+ */
+/*
+*  
+*/
+
+/************************************************************************/
+/*									*/
+/* OS abstraction							*/
+/*									*/
+/************************************************************************/
+
+#ifndef _BL_OS_WRAPER_H_
+#define _BL_OS_WRAPER_H_
+
+
+#if defined __UBOOT__
+ #include <common.h>
+ #define bdmf_sysb	int
+ #define xprintf	printf
+#elif defined __KERNEL__
+
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/interrupt.h>
+ #include <linux/delay.h>
+ #include <linux/slab.h>
+ #include <linux/version.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)
+ #include <linux/mm_types.h>
+#endif
+ #include <linux/slab_def.h>
+ #include <linux/version.h>
+ #include <linux/types.h>
+ #include <linux/netdevice.h>
+ #include <linux/skbuff.h>
+ #include <linux/platform_device.h>
+ #include <linux/string.h>
+ #include <linux/irq.h>
+ #include <linux/uaccess.h>
+#else
+ #warning "Unspecified OS !"
+#endif
+
+
+#define BL_ZERO_REG(reg) 	do {*(unsigned int*)reg = 0;} while(0)
+
+#define ONE_SEC_IN_NANO		1000000000
+#define	BL_LILAC_IRQ_BASE	0x70
+
+#ifdef DEBUG
+#define BL_ASSERT(x)	if (!(x)) {\
+				printk("Assertion in %s at line %d failed/n", __FILE__, __LINE__); \
+				while(1); \
+			}
+#else
+#define BL_ASSERT(x)
+#endif
+
+
+#endif /* #ifndef _BL_OS_WRAPER_H_ */
+
diff --git a/arch/arm/mach-bcmbca/rdp/data_path_init.c b/arch/arm/mach-bcmbca/rdp/data_path_init.c
new file mode 100755
index 0000000000..17da11720a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/data_path_init.c
@@ -0,0 +1,1830 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the implementation for Broadcom's BCM63138 Data path    */
+/* initialization sequence                                                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+
+
+#ifdef __UBOOT__
+#include <common.h>
+#endif
+#include "data_path_init.h"
+#include "rdpa_types.h"
+#include "rdpa_config.h"
+#include "rdp_drv_bpm.h"
+#include "rdp_drv_sbpm.h"
+#include "rdp_drv_ih.h"
+#include "rdp_drv_bbh.h"
+#include "rdp_dma.h"
+#include "rdd_ih_defs.h"
+#include "rdd.h"
+#include "rdd_tm.h"
+
+static  S_DPI_CFG   DpiBasicConfig = {WAN_TYPE_NONE,1536,0,0,0,0};
+
+#if defined(BDMF_SYSTEM_SIM)
+#define __print(fmt, arg...)
+#elif defined(__UBOOT__)
+#define __print(fmt, arg...) printf(fmt, ##arg)
+#else
+#define __print(fmt, arg...) printk(fmt, ##arg)
+#endif
+
+#define BCM63138_TM_DEF_DDR_SIZE                    0x0E00000
+#define BCM63138_TM_MC_DEF_DDR_SIZE                 0x0400000
+#define CS_RDD_ETH_TX_QUEUE_PACKET_THRESHOLD    256
+#define CS_RDD_CPU_RX_QUEUE_SIZE                32
+
+
+#define SHIFTL(_a) ( 1 << _a)
+/****************************************************************************
+ *
+ * Defines
+ *
+ * *************************************************************************/
+
+#define DEFAULT_RUNNER_FREQ             800
+#define RDD_CPU_TX_ABS_FIFO_SIZE        LILAC_RDD_CPU_TX_SKB_LIMIT_MAX
+
+/* multicast header size */
+#define BBH_MULTICAST_HEADER_SIZE_FOR_LAN_PORT 32
+#define BBH_MULTICAST_HEADER_SIZE_FOR_WAN_PORT 96
+
+/* PD FIFO size of EMAC, when MDU mode is disabled */
+#define BBH_TX_EMAC_PD_FIFO_SIZE_MDU_MODE_DISABLED 8
+/* PD FIFO size of EMAC, when MDU mode is enabled */
+#define BBH_TX_EMAC_PD_FIFO_SIZE_MDU_MODE_ENABLED 4
+/* DMA */
+#define BBH_RX_DMA_FIFOS_SIZE_WAN_DMA 19
+#define BBH_RX_DMA_FIFOS_SIZE_WAN_DSL 19
+#define BBH_RX_DMA_FIFOS_SIZE_LAN_DMA 9
+#define BBH_RX_DMA_FIFOS_SIZE_LAN_BBH 11
+#define BBH_RX_DMA_EXCLUSIVE_THRESHOLD_WAN_DMA 17
+#define BBH_RX_DMA_EXCLUSIVE_THRESHOLD_WAN_BBH 18
+#define BBH_RX_DMA_EXCLUSIVE_THRESHOLD_LAN_DMA 7
+#define BBH_RX_DMA_EXCLUSIVE_THRESHOLD_LAN_BBH 11
+#define BBH_RX_SDMA_FIFOS_SIZE_WAN 7
+#define BBH_RX_SDMA_FIFOS_SIZE_LAN 5
+#define BBH_RX_SDMA_EXCLUSIVE_THRESHOLD_WAN 6
+#define BBH_RX_SDMA_EXCLUSIVE_THRESHOLD_LAN 4
+#define BBH_RX_DMA_TOTAL_NUMBER_OF_CHUNK_DESCRIPTORS 64
+#define BBH_RX_SDMA_TOTAL_NUMBER_OF_CHUNK_DESCRIPTORS 32
+
+#define ATM_MIN_DATA_SIZE    4   /* Such as PPPoA or IPoA */
+#define MIN_XTM_PKT_SIZE ATM_MIN_DATA_SIZE
+#define MIN_ETH_PKT_SIZE 64
+#define BBH_RX_FLOWS_32_255_GROUP_DIVIDER 255
+#define BBH_RX_ETH_MIN_PKT_SIZE_SELECTION_INDEX 0
+
+#define BBH_RX_MAX_PKT_SIZE_SELECTION_INDEX 0
+
+//#define IH_HEADER_LENGTH_MIN 64
+#define IH_HEADER_LENGTH_MIN ATM_MIN_DATA_SIZE
+
+#define IH_PARSER_EXCEPTION_STATUS_BITS 0x47
+#define IH_PARSER_AH_DETECTION 0x18000
+/* PPP protocol code for IPv4 is configured at index 0 */
+#define IH_PARSER_PPP_PROTOCOL_CODE_0_IPV4 0x21
+/* PPP protocol code for IPv6 is configured at index 1 */
+#define IH_PARSER_PPP_PROTOCOL_CODE_1_IPV6 0x57
+
+#define IH_ETH0_ROUTE_ADDRESS 0x1C
+#define IH_ETH1_ROUTE_ADDRESS 0xC
+#define IH_ETH2_ROUTE_ADDRESS 0x14
+#define IH_ETH3_ROUTE_ADDRESS 0x8
+#define IH_ETH4_ROUTE_ADDRESS 0x10
+#define IH_GPON_ROUTE_ADDRESS 0
+#define IH_DSL_ROUTE_ADDRESS IH_GPON_ROUTE_ADDRESS
+#define IH_RUNNER_A_ROUTE_ADDRESS 0x3
+#define IH_RUNNER_B_ROUTE_ADDRESS 0x2
+#define IH_DA_FILTER_IPTV_IPV4 0
+#define IH_DA_FILTER_IPTV_IPV6 1
+#define TCP_CTRL_FLAG_RST 0x04
+#define TCP_CTRL_FLAG_SYN 0x02
+#define TCP_CTRL_FLAG_FIN 0x01
+/* size of ingress queue of each one of the EMACs which function as LAN */
+#define IH_INGRESS_QUEUE_SIZE_LAN_EMACS 2
+/* size of ingress queue of the WAN port */
+#define IH_INGRESS_QUEUE_SIZE_WAN 4
+/* size of ingress queue of each runner */
+#define IH_INGRESS_QUEUE_SIZE_RUNNERS 1
+/* priority of ingress queue of each one of the EMACs which function as LAN */
+#define IH_INGRESS_QUEUE_PRIORITY_LAN_EMACS 1
+/* priority of ingress queue of the WAN port */
+#define IH_INGRESS_QUEUE_PRIORITY_WAN 2
+/* priority of ingress queue of each runner */
+#define IH_INGRESS_QUEUE_PRIORITY_RUNNERS 0
+/* weight of ingress queue of each one of the EMACs which function as LAN */
+#define IH_INGRESS_QUEUE_WEIGHT_LAN_EMACS 1
+/* weight of ingress queue of the WAN port */
+#define IH_INGRESS_QUEUE_WEIGHT_WAN 1
+/* weight of ingress queue of each runner */
+#define IH_INGRESS_QUEUE_WEIGHT_RUNNERS 1
+/* congestion threshold of ingress queue of each one of the EMACs which function as LAN */
+#define IH_INGRESS_QUEUE_CONGESTION_THRESHOLD_LAN_EMACS 65
+/* congestion threshold of ingress queue of the WAN port */
+#define IH_INGRESS_QUEUE_CONGESTION_THRESHOLD_WAN_ETH 65
+#define IH_INGRESS_QUEUE_CONGESTION_THRESHOLD_WAN_DSL 0x1F /* 31 */
+/* congestion threshold of ingress queue of each runner */
+#define IH_INGRESS_QUEUE_CONGESTION_THRESHOLD_RUNNERS 65
+
+#define IH_IP_L4_FILTER_USER_DEFINED_0          0
+#define IH_IP_L4_FILTER_USER_DEFINED_1          1
+#define IH_IP_L4_FILTER_USER_DEFINED_2          2
+#define IH_IP_L4_FILTER_USER_DEFINED_3          3
+
+#define IH_L4_FILTER_DEF                        0xff
+/* we use one basic class */
+#define IH_BASIC_CLASS_INDEX          0
+/* IH classifier indices for broadcast and multicast traffic iptv destination */
+#define IH_CLASSIFIER_BCAST_IPTV 0
+#define IH_CLASSIFIER_IGMP_IPTV 1
+#define IH_CLASSIFIER_ICMPV6 2
+#define IH_CLASSIFIER_IPTV  (IH_CLASSIFIER_ICMPV6 + 1)
+
+#define MASK_IH_CLASS_KEY_L4 0x3c0
+/* IPTV DA filter mask in IH */
+#define IPTV_FILTER_MASK_DA 0x3800
+#define IPTV_FILTER_MASK_BCAST  0x8000
+
+/* default value for SBPM */
+#define SBPM_DEFAULT_THRESHOLD 800
+#define SBPM_DEFAULT_HYSTERESIS 0
+#define BPM_DEFAULT_HYSTERESIS 64
+#define SBPM_BASE_ADDRESS 0
+#define SBPM_LIST_SIZE 0x3FF
+#define BPM_CPU_NUMBER_OF_BUFFERS 1536
+#if defined(DSL_63138)
+#if defined(CONFIG_BCM_JUMBO_FRAME)
+#define DRV_BBH_DDR_BUFFER_SIZE  DRV_BBH_DDR_BUFFER_SIZE_2_5_KB
+#else
+#define DRV_BBH_DDR_BUFFER_SIZE  DRV_BBH_DDR_BUFFER_SIZE_2_KB
+#endif
+#define DRV_BBH_DDR_BPM_MESSAGE_FORMAT DRV_BBH_DDR_BPM_MESSAGE_FORMAT_15_BIT_BN_WIDTH
+#define DRV_SPARE_BN_MESSAGE_FORMAT DRV_SPARE_BN_MESSAGE_FORMAT_15_bit_BN_WIDTH
+#elif defined(DSL_63148) && defined(CONFIG_BCM_JUMBO_FRAME)
+#define DRV_BBH_DDR_BUFFER_SIZE  DRV_BBH_DDR_BUFFER_SIZE_4_KB
+#define DRV_BBH_DDR_BPM_MESSAGE_FORMAT  DRV_BBH_DDR_BPM_MESSAGE_FORMAT_14_BIT_BN_WIDTH
+#define DRV_SPARE_BN_MESSAGE_FORMAT DRV_SPARE_BN_MESSAGE_FORMAT_14_bit_BN_WIDTH
+#else
+#define DRV_BBH_DDR_BUFFER_SIZE  DRV_BBH_DDR_BUFFER_SIZE_2_KB
+#define DRV_BBH_DDR_BPM_MESSAGE_FORMAT DRV_BBH_DDR_BPM_MESSAGE_FORMAT_14_BIT_BN_WIDTH
+#define DRV_SPARE_BN_MESSAGE_FORMAT DRV_SPARE_BN_MESSAGE_FORMAT_14_bit_BN_WIDTH
+#endif
+
+/*DSL DEFS*/
+/* size of each one of FIFOs 0-7 */
+#define BBH_TX_DSL_PD_FIFO_SIZE_0_7 4
+/* size of each one of FIFOs 8-15 */
+#define BBH_TX_DSL_PD_FIFO_SIZE_8_15 3
+#define BBH_TX_DSL_PD_FIFO_SIZE_16_23 3
+#define BBH_TX_DSL_PD_FIFO_SIZE_24_31 3
+#define BBH_TX_DSL_PD_FIFO_SIZE_32_39 3
+#define BBH_TX_DSL_NUMBER_OF_QUEUES_IN_PD_FIFO_GROUP 8
+#define BBH_TX_DSL_TOTAL_NUMBER_OF_PDS 128
+#define BBH_TX_DSL_PD_FIFO_BASE_0 0
+#define BBH_TX_DSL_PD_FIFO_BASE_1 (BBH_TX_DSL_PD_FIFO_BASE_0 + BBH_TX_DSL_PD_FIFO_SIZE_0_7)
+#define BBH_TX_DSL_PD_FIFO_BASE_2 (BBH_TX_DSL_PD_FIFO_BASE_1 + BBH_TX_DSL_PD_FIFO_SIZE_0_7)
+#define BBH_TX_DSL_PD_FIFO_BASE_3 (BBH_TX_DSL_PD_FIFO_BASE_2 + BBH_TX_DSL_PD_FIFO_SIZE_0_7)
+#define BBH_TX_DSL_PD_FIFO_BASE_4 (BBH_TX_DSL_PD_FIFO_BASE_3 + BBH_TX_DSL_PD_FIFO_SIZE_0_7)
+#define BBH_TX_DSL_PD_FIFO_BASE_5 (BBH_TX_DSL_PD_FIFO_BASE_4 + BBH_TX_DSL_PD_FIFO_SIZE_0_7)
+#define BBH_TX_DSL_PD_FIFO_BASE_6 (BBH_TX_DSL_PD_FIFO_BASE_5 + BBH_TX_DSL_PD_FIFO_SIZE_0_7)
+#define BBH_TX_DSL_PD_FIFO_BASE_7 (BBH_TX_DSL_PD_FIFO_BASE_6 + BBH_TX_DSL_PD_FIFO_SIZE_0_7)
+#define BBH_TX_DSL_PD_FIFO_BASE_8_15 (BBH_TX_DSL_PD_FIFO_BASE_7 + BBH_TX_DSL_PD_FIFO_SIZE_0_7)
+#define BBH_TX_DSL_PD_FIFO_BASE_16_23 \
+    (BBH_TX_DSL_PD_FIFO_BASE_8_15 + (BBH_TX_DSL_NUMBER_OF_QUEUES_IN_PD_FIFO_GROUP * BBH_TX_DSL_PD_FIFO_SIZE_8_15))
+#define BBH_TX_DSL_PD_FIFO_BASE_24_31 (BBH_TX_DSL_PD_FIFO_BASE_16_23 + \
+    (BBH_TX_DSL_NUMBER_OF_QUEUES_IN_PD_FIFO_GROUP * BBH_TX_DSL_PD_FIFO_SIZE_16_23))
+#define BBH_TX_DSL_PD_FIFO_BASE_32_39 (BBH_TX_DSL_PD_FIFO_BASE_24_31 + \
+    (BBH_TX_DSL_NUMBER_OF_QUEUES_IN_PD_FIFO_GROUP * BBH_TX_DSL_PD_FIFO_SIZE_24_31))
+
+/******************************************************************************/
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    BB_MODULE_DMA,
+    BB_MODULE_SDMA,
+
+    BB_MODULE_NUM
+}E_BB_MODULE;
+
+typedef enum
+{
+    DMA_PERIPHERAL_EMAC_0 = 0,
+    DMA_PERIPHERAL_EMAC_1 = 1,
+    DMA_PERIPHERAL_DSL = 5,
+
+    DMA_NUMBER_OF_PERIPHERALS
+}
+E_DMA_PERIPHERAL;
+/******************************************************************************/
+/*                                                                            */
+/* Macros definitions                                                         */
+/*                                                                            */
+/******************************************************************************/
+/* sets bit #i of a given number to a given value */
+#define SET_BIT_I( number , i , bit_value )   ( ( number ) &= ( ~ ( 1 << i ) )  , ( number ) |= ( bit_value << i ) )
+#define MS_BYTE_TO_8_BYTE_RESOLUTION(address)  ((address) >> 3)
+#define ARRAY_LENGTH(array) (sizeof(array)/sizeof(array[0]))
+
+#define BBH_PORT_IS_WAN(_portIndex) (_portIndex == DRV_BBH_EMAC_0 || _portIndex == DRV_BBH_DSL)
+
+/*****************************************************************************/
+/*                                                                           */
+/* Local Defines                                                             */
+/*                                                                           */
+/*****************************************************************************/
+
+static S_DPI_CFG *pDpiCfg = NULL;
+static uint32_t initDone = 0;
+
+/* route addresses (for both TX & RX) */
+static const uint8_t bbh_route_address_dma[DRV_BBH_NUMBER_OF_PORTS]=
+{
+    0xC, 0xD, 0xE, 0xD, 0xE, 0xF, 0xF
+};
+
+static const uint8_t bbh_route_address_bpm[DRV_BBH_NUMBER_OF_PORTS]=
+{
+    0x14, 0x15, 0x16, 0x15, 0x16, 0x17, 0x17
+};
+
+static const uint8_t bbh_route_address_sdma[DRV_BBH_NUMBER_OF_PORTS]=
+{
+    0x1C, 0x1D, 0x1E, 0x1D, 0x1E, 0x1F, 0x1F
+};
+
+static const uint8_t bbh_route_address_sbpm[DRV_BBH_NUMBER_OF_PORTS]=
+{
+    0x34, 0x35, 0x36, 0x35, 0x36, 0x37, 0x37
+};
+
+static const uint8_t bbh_route_address_runner_0[DRV_BBH_NUMBER_OF_PORTS]=
+{
+    0x0, 0x1, 0x2, 0x1, 0x2, 0x3, 0x3
+};
+
+static const uint8_t bbh_route_address_runner_1[DRV_BBH_NUMBER_OF_PORTS]=
+{
+    0x8, 0x9, 0xA, 0x9, 0xA, 0xB, 0xB
+};
+
+static const uint8_t bbh_route_address_ih[DRV_BBH_NUMBER_OF_PORTS]=
+{
+    0x18, 0x19, 0x1A, 0x11, 0x12, 0x13, 0x13
+};
+
+/* same values for DMA & SDMA */
+static const uint8_t bbh_dma_and_sdma_read_requests_fifo_base_address[DRV_BBH_NUMBER_OF_PORTS]=
+{
+    0x0, 0x8, 0x10, 0x18, 0x20, 0x28, 0x28
+};
+
+/* IH Classes indexes & configurations */
+typedef struct
+{
+    uint8_t class_index;
+
+    DRV_IH_CLASS_CONFIG class_config;
+}
+ih_class_cfg;
+ih_class_cfg gs_ih_classes[] =
+{
+    {
+        /* LAN bridged eth0 */
+        DRV_RDD_IH_CLASS_LAN_BRIDGED_ETH0_INDEX,
+        {
+            DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX, /* da_lookup_required */
+            DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX, /* sa_lookup_required */
+            DRV_RDD_IH_CLASS_10_CLASS_SEARCH_3,
+            DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_4,
+            DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1, /* da_lookup_required */
+            DRV_RDD_IH_CLASS_10_DROP_ON_MISS,
+            DRV_RDD_IH_CLASS_10_DSCP_TO_PBITS_TABLE_INDEX,
+            DRV_RDD_IH_CLASS_10_DIRECT_MODE_DEFAULT,
+            DRV_RDD_IH_CLASS_10_DIRECT_MODE_OVERRIDE,
+            DRV_RDD_IH_CLASS_10_TARGET_MEMORY_DEFAULT,
+            DRV_RDD_IH_CLASS_10_TARGET_MEMORY_OVERRIDE,
+            DRV_RDD_IH_CLASS_10_INGRESS_QOS_DEFAULT,
+            DRV_RDD_IH_CLASS_10_INGRESS_QOS_OVERRIDE,
+            DRV_RDD_IH_CLASS_10_TARGET_RUNNER_DEFAULT,
+            DRV_RDD_IH_CLASS_10_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE,
+            DRV_RDD_IH_CLASS_10_TARGET_RUNNER_FOR_DIRECT_MODE,
+            DRV_RDD_IH_CLASS_10_LOAD_BALANCING_ENABLE,
+            DRV_RDD_IH_CLASS_10_PREFERENCE_LOAD_BALANCING_ENABLE
+        }
+    },
+    {
+        /* LAN bridged eth1 */
+        DRV_RDD_IH_CLASS_LAN_BRIDGED_ETH1_INDEX,
+        {
+            DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX, /* da_lookup_required */
+            DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX, /* sa_lookup_required */
+            DRV_RDD_IH_CLASS_11_CLASS_SEARCH_3,
+            DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_4,
+            DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1, /* da_lookup_required */
+            DRV_RDD_IH_CLASS_11_DROP_ON_MISS,
+            DRV_RDD_IH_CLASS_11_DSCP_TO_PBITS_TABLE_INDEX,
+            DRV_RDD_IH_CLASS_11_DIRECT_MODE_DEFAULT,
+            DRV_RDD_IH_CLASS_11_DIRECT_MODE_OVERRIDE,
+            DRV_RDD_IH_CLASS_11_TARGET_MEMORY_DEFAULT,
+            DRV_RDD_IH_CLASS_11_TARGET_MEMORY_OVERRIDE,
+            DRV_RDD_IH_CLASS_11_INGRESS_QOS_DEFAULT,
+            DRV_RDD_IH_CLASS_11_INGRESS_QOS_OVERRIDE,
+            DRV_RDD_IH_CLASS_11_TARGET_RUNNER_DEFAULT,
+            DRV_RDD_IH_CLASS_11_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE,
+            DRV_RDD_IH_CLASS_11_TARGET_RUNNER_FOR_DIRECT_MODE,
+            DRV_RDD_IH_CLASS_11_LOAD_BALANCING_ENABLE,
+            DRV_RDD_IH_CLASS_11_PREFERENCE_LOAD_BALANCING_ENABLE
+        }
+    },
+};
+
+/* following arrays are initialized in run-time. */
+/* DMA related */
+static uint8_t bbh_rx_dma_data_fifo_base_address[DRV_BBH_NUMBER_OF_PORTS];
+static uint8_t bbh_rx_dma_chunk_descriptor_fifo_base_address[DRV_BBH_NUMBER_OF_PORTS];
+static uint8_t bbh_rx_dma_data_and_chunk_descriptor_fifos_size[DRV_BBH_NUMBER_OF_PORTS];
+static uint8_t bbh_rx_dma_exclusive_threshold[DRV_BBH_NUMBER_OF_PORTS];
+/* SDMA related */
+static uint8_t bbh_rx_sdma_data_fifo_base_address[DRV_BBH_NUMBER_OF_PORTS];
+static uint8_t bbh_rx_sdma_chunk_descriptor_fifo_base_address[DRV_BBH_NUMBER_OF_PORTS];
+static uint8_t bbh_rx_sdma_data_and_chunk_descriptor_fifos_size[DRV_BBH_NUMBER_OF_PORTS];
+static uint8_t bbh_rx_sdma_exclusive_threshold[DRV_BBH_NUMBER_OF_PORTS];
+static uint16_t bbh_ih_ingress_buffers_bitmask[DRV_BBH_NUMBER_OF_PORTS];
+
+static const BL_LILAC_RDD_EMAC_ID_DTE bbh_to_rdd_emac_map[] =
+{
+        BL_LILAC_RDD_EMAC_ID_0 ,
+        BL_LILAC_RDD_EMAC_ID_1 ,
+        BL_LILAC_RDD_EMAC_ID_2 ,
+        BL_LILAC_RDD_EMAC_ID_3 ,
+        BL_LILAC_RDD_EMAC_ID_4 ,
+};
+
+/******************************************************************************/
+/* There are 8 IH ingress queues. This enumeration defines, for each ingress  */
+/* queue, which physical source port it belongs to.                           */
+/******************************************************************************/
+
+typedef enum
+{
+    IH_INGRESS_QUEUE_0_ETH0 = 0 ,
+    IH_INGRESS_QUEUE_1_ETH1 = 1 ,
+    IH_INGRESS_QUEUE_5_DSL = 5 ,
+    IH_INGRESS_QUEUE_6_RUNNER_A = 6 ,
+    IH_INGRESS_QUEUE_7_RUNNER_B = 7 ,
+
+    NUMBER_OF_IH_INGRESS_QUEUES
+}
+IH_INGRESS_QUEUE_INDEX ;
+
+/* FW binaries */
+extern uint32_t firmware_binary_A[];
+extern uint32_t firmware_binary_B[];
+extern uint32_t firmware_binary_C[];
+extern uint32_t firmware_binary_D[];
+extern uint16_t firmware_predict_A[];
+extern uint16_t firmware_predict_B[];
+extern uint16_t firmware_predict_C[];
+extern uint16_t firmware_predict_D[];
+
+void f_basic_sbpm_sp_enable(void);
+void f_basic_bpm_sp_enable(void);
+
+typedef struct
+{
+    uint32_t bpm_def_thresh;    
+    uint32_t bpm_gbl_thresh;    
+} rdp_bpm_cfg_params;
+
+
+static void f_update_bbh_ih_ingress_buffers_bitmask(DRV_BBH_PORT_INDEX bbh_port_index, uint8_t base_location, uint8_t queue_size)
+{
+    uint16_t bitmask = 0;
+    uint8_t i;
+
+    /* set '1's according to queue_size  */
+    for (i= 0; i < queue_size; i++)
+    {
+        SET_BIT_I(bitmask, i, 1);
+    }
+    /* do shifting according to xi_base_location */
+    bitmask <<= base_location;
+
+    /* update in database */
+    bbh_ih_ingress_buffers_bitmask[bbh_port_index] = bitmask;
+}
+
+static void fi_dma_configure_memory_allocation ( E_BB_MODULE module_id ,
+                                                 E_DMA_PERIPHERAL peripheral_id ,
+                                                 uint32_t data_memory_offset_address ,
+                                                 uint32_t cd_memory_offset_address ,
+                                                 uint32_t number_of_buffers )
+{
+    DMA_REGS_CONFIG_MALLOC config_malloc ;
+
+    DMA_REGS_CONFIG_MALLOC_READ( module_id , peripheral_id , config_malloc ) ;
+    config_malloc.datatoffset = data_memory_offset_address ;
+    config_malloc.cdoffset = cd_memory_offset_address ;
+    config_malloc.numofbuff = number_of_buffers ;
+    DMA_REGS_CONFIG_MALLOC_WRITE( module_id , peripheral_id , config_malloc ) ;
+}
+
+static void f_initialize_dma_sdma(void)
+{
+    DMA_REGS_CONFIG_U_THRESH dma_thresh;
+
+    /* DMA */
+    fi_dma_configure_memory_allocation ( BB_MODULE_DMA ,
+                                         DMA_PERIPHERAL_EMAC_0 ,
+                                         BBH_RX_DMA_FIFOS_SIZE_LAN_BBH * DMA_PERIPHERAL_EMAC_0  ,
+                                         BBH_RX_DMA_FIFOS_SIZE_LAN_BBH * DMA_PERIPHERAL_EMAC_0  ,
+                                         BBH_RX_DMA_FIFOS_SIZE_LAN_BBH) ;
+    /* SDMA */
+    fi_dma_configure_memory_allocation ( BB_MODULE_SDMA ,
+                                         DMA_PERIPHERAL_EMAC_0 ,
+                                         bbh_rx_sdma_data_fifo_base_address [ DMA_PERIPHERAL_EMAC_0 ] ,
+                                         bbh_rx_sdma_chunk_descriptor_fifo_base_address [ DMA_PERIPHERAL_EMAC_0 ] ,
+                                         bbh_rx_sdma_data_and_chunk_descriptor_fifos_size [ DMA_PERIPHERAL_EMAC_0 ] ) ;
+
+    /* DMA */
+    fi_dma_configure_memory_allocation ( BB_MODULE_DMA ,
+                                         DMA_PERIPHERAL_EMAC_1 ,
+                                         BBH_RX_DMA_FIFOS_SIZE_LAN_BBH * DMA_PERIPHERAL_EMAC_1  ,
+                                         BBH_RX_DMA_FIFOS_SIZE_LAN_BBH * DMA_PERIPHERAL_EMAC_1  ,
+                                         BBH_RX_DMA_FIFOS_SIZE_LAN_BBH) ;
+    /* SDMA */
+    fi_dma_configure_memory_allocation ( BB_MODULE_SDMA ,
+                                         DMA_PERIPHERAL_EMAC_1 ,
+                                         bbh_rx_sdma_data_fifo_base_address [ DMA_PERIPHERAL_EMAC_1 ] ,
+                                         bbh_rx_sdma_chunk_descriptor_fifo_base_address [ DMA_PERIPHERAL_EMAC_1 ] ,
+                                         bbh_rx_sdma_data_and_chunk_descriptor_fifos_size [ DMA_PERIPHERAL_EMAC_1 ] ) ;
+
+    /* DMA*/
+    fi_dma_configure_memory_allocation ( BB_MODULE_DMA ,
+                                         DMA_PERIPHERAL_DSL ,
+                                         bbh_rx_dma_data_fifo_base_address [ DRV_BBH_DSL ] ,
+                                         bbh_rx_dma_chunk_descriptor_fifo_base_address [ DRV_BBH_DSL ] ,
+                                         bbh_rx_dma_data_and_chunk_descriptor_fifos_size [ DRV_BBH_DSL ] ) ;
+    /* SDMA */
+    fi_dma_configure_memory_allocation ( BB_MODULE_SDMA ,
+                                         DMA_PERIPHERAL_DSL ,
+                                         bbh_rx_sdma_data_fifo_base_address [ DRV_BBH_DSL ] ,
+                                         bbh_rx_sdma_chunk_descriptor_fifo_base_address [ DRV_BBH_DSL ] ,
+                                         bbh_rx_sdma_data_and_chunk_descriptor_fifos_size [ DRV_BBH_DSL ] ) ;
+
+    dma_thresh.out_of_u = 1;
+    dma_thresh.into_u = 5;
+    DMA_REGS_CONFIG_U_THRESH_WRITE(BB_MODULE_DMA,DMA_PERIPHERAL_EMAC_0,dma_thresh);
+    DMA_REGS_CONFIG_U_THRESH_WRITE(BB_MODULE_DMA,DMA_PERIPHERAL_EMAC_1,dma_thresh);
+    DMA_REGS_CONFIG_U_THRESH_WRITE(BB_MODULE_DMA,DMA_PERIPHERAL_DSL,dma_thresh);
+}
+
+static E_DPI_RC f_initialize_bbh_dma_sdma_related_arrays(void)
+{
+    uint8_t dma_base_address = 0;
+    uint8_t sdma_base_address = 0;
+
+    /* Ethernet WAN */
+    bbh_rx_dma_data_and_chunk_descriptor_fifos_size[DRV_BBH_EMAC_0] = BBH_RX_DMA_FIFOS_SIZE_WAN_DMA;
+    bbh_rx_dma_exclusive_threshold[DRV_BBH_EMAC_0] = BBH_RX_DMA_EXCLUSIVE_THRESHOLD_WAN_DMA;
+    bbh_rx_sdma_data_and_chunk_descriptor_fifos_size[DRV_BBH_EMAC_0] = BBH_RX_SDMA_FIFOS_SIZE_WAN;
+    bbh_rx_sdma_exclusive_threshold[DRV_BBH_EMAC_0] = BBH_RX_SDMA_EXCLUSIVE_THRESHOLD_WAN;
+
+    bbh_rx_dma_data_fifo_base_address[DRV_BBH_EMAC_0] = dma_base_address;
+    bbh_rx_dma_chunk_descriptor_fifo_base_address[DRV_BBH_EMAC_0] = dma_base_address;
+    bbh_rx_sdma_data_fifo_base_address[DRV_BBH_EMAC_0] = sdma_base_address;
+    bbh_rx_sdma_chunk_descriptor_fifo_base_address[DRV_BBH_EMAC_0] = sdma_base_address;
+
+    dma_base_address += bbh_rx_dma_data_and_chunk_descriptor_fifos_size[DRV_BBH_EMAC_0];
+    sdma_base_address += bbh_rx_sdma_data_and_chunk_descriptor_fifos_size[DRV_BBH_EMAC_0];
+
+    /* SF2 */
+    bbh_rx_dma_data_and_chunk_descriptor_fifos_size[DRV_BBH_EMAC_1] = BBH_RX_DMA_FIFOS_SIZE_LAN_DMA;
+    bbh_rx_dma_exclusive_threshold[DRV_BBH_EMAC_1] = BBH_RX_DMA_EXCLUSIVE_THRESHOLD_LAN_DMA;
+    bbh_rx_sdma_data_and_chunk_descriptor_fifos_size[DRV_BBH_EMAC_1] = BBH_RX_SDMA_FIFOS_SIZE_LAN;
+    bbh_rx_sdma_exclusive_threshold[DRV_BBH_EMAC_1] = BBH_RX_SDMA_EXCLUSIVE_THRESHOLD_LAN;
+
+    bbh_rx_dma_data_fifo_base_address[DRV_BBH_EMAC_1] = dma_base_address;
+    bbh_rx_dma_chunk_descriptor_fifo_base_address[DRV_BBH_EMAC_1] = dma_base_address;
+    bbh_rx_sdma_data_fifo_base_address[DRV_BBH_EMAC_1] = sdma_base_address;
+    bbh_rx_sdma_chunk_descriptor_fifo_base_address[DRV_BBH_EMAC_1] = sdma_base_address;
+
+    dma_base_address += bbh_rx_dma_data_and_chunk_descriptor_fifos_size[DRV_BBH_EMAC_1];
+    sdma_base_address += bbh_rx_sdma_data_and_chunk_descriptor_fifos_size[DRV_BBH_EMAC_1];
+
+    /* DSL */
+    bbh_rx_dma_data_and_chunk_descriptor_fifos_size[DRV_BBH_DSL] = BBH_RX_DMA_FIFOS_SIZE_WAN_DMA;
+    bbh_rx_dma_exclusive_threshold[DRV_BBH_DSL] = BBH_RX_DMA_EXCLUSIVE_THRESHOLD_WAN_DMA;
+    bbh_rx_sdma_data_and_chunk_descriptor_fifos_size[DRV_BBH_DSL] = BBH_RX_SDMA_FIFOS_SIZE_WAN;
+    bbh_rx_sdma_exclusive_threshold[DRV_BBH_DSL] = BBH_RX_SDMA_EXCLUSIVE_THRESHOLD_WAN;
+
+    bbh_rx_dma_data_fifo_base_address[DRV_BBH_DSL] = dma_base_address;
+    bbh_rx_dma_chunk_descriptor_fifo_base_address[DRV_BBH_DSL] = dma_base_address;
+    bbh_rx_sdma_data_fifo_base_address[DRV_BBH_DSL] = sdma_base_address;
+    bbh_rx_sdma_chunk_descriptor_fifo_base_address[DRV_BBH_DSL] = sdma_base_address;
+
+    dma_base_address += bbh_rx_dma_data_and_chunk_descriptor_fifos_size[DRV_BBH_DSL];
+    sdma_base_address += bbh_rx_sdma_data_and_chunk_descriptor_fifos_size[DRV_BBH_DSL];
+
+    /* check that we didn't overrun */
+    if (dma_base_address > BBH_RX_DMA_TOTAL_NUMBER_OF_CHUNK_DESCRIPTORS ||
+        sdma_base_address > BBH_RX_SDMA_TOTAL_NUMBER_OF_CHUNK_DESCRIPTORS)
+    {
+        __print("%s:(%d) error",__FUNCTION__,__LINE__);
+        return DPI_RC_ERROR;
+    }
+    return DPI_RC_OK;
+}
+
+static uint16_t f_get_bbh_rx_pd_fifo_base_address_normal_queue_in_8_byte(DRV_BBH_PORT_INDEX port_index)
+{
+    switch (port_index)
+    {
+    case DRV_BBH_EMAC_0:
+        return MS_BYTE_TO_8_BYTE_RESOLUTION(ETH0_RX_DESCRIPTORS_ADDRESS);
+
+    case DRV_BBH_EMAC_1:
+        return MS_BYTE_TO_8_BYTE_RESOLUTION(ETH1_RX_DESCRIPTORS_ADDRESS);
+
+    case DRV_BBH_DSL:
+        return MS_BYTE_TO_8_BYTE_RESOLUTION(GPON_RX_NORMAL_DESCRIPTORS_ADDRESS);
+
+    default:
+        return 0;
+    }
+}
+static uint16_t f_get_bbh_rx_pd_fifo_base_address_direct_queue_in_8_byte(DRV_BBH_PORT_INDEX port_index)
+{
+    switch (port_index)
+    {
+    case DRV_BBH_EMAC_0:
+        return MS_BYTE_TO_8_BYTE_RESOLUTION(ETH0_RX_DIRECT_DESCRIPTORS_ADDRESS);
+
+    case DRV_BBH_EMAC_1:
+        return MS_BYTE_TO_8_BYTE_RESOLUTION(ETH1_RX_DIRECT_DESCRIPTORS_ADDRESS);
+
+    case DRV_BBH_DSL:
+        return MS_BYTE_TO_8_BYTE_RESOLUTION(GPON_RX_DIRECT_DESCRIPTORS_ADDRESS);
+
+    default:
+        return 0;
+    }
+}
+static uint8_t f_bbh_rx_runner_task_normal_queue(DRV_IH_RUNNER_CLUSTER runner_cluster, DRV_BBH_PORT_INDEX port_index)
+{
+    uint8_t isWan = BBH_PORT_IS_WAN(port_index);
+
+    if (runner_cluster == DRV_IH_RUNNER_CLUSTER_A)
+    {
+        if (isWan)
+        {
+            return (port_index == DRV_BBH_DSL) ? WAN_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER
+                                               : WAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER;
+        }
+        /* the port is LAN */
+        else
+        {
+            /* runner A doesn't handle the normal queue for LAN */
+            return 0;
+        }
+    }
+    /* runner B */
+    else
+    {
+        if (isWan)
+        {
+            /* runner B doesn't handle WAN */
+            return 0;
+        }
+        /* the port is LAN */
+        else
+        {
+            switch (port_index)
+            {
+            case DRV_BBH_EMAC_0:
+                /* EMAC 0 is not supported as a LAN */
+                return 0;
+
+            case DRV_BBH_EMAC_1:
+#if defined(__UBOOT__)
+                return LAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER;
+#else
+                return LAN_DISPATCH_THREAD_NUMBER;
+#endif
+
+                /* we are not supposed to get here */
+            default:
+                return 0;
+            }
+        }
+    }
+}
+
+static uint8_t f_bbh_rx_runner_task_direct_queue(DRV_IH_RUNNER_CLUSTER runner_cluster, DRV_BBH_PORT_INDEX portIndex)
+{
+    if ( BBH_PORT_IS_WAN( portIndex ) )
+    {
+        return WAN_DIRECT_THREAD_NUMBER;
+    }
+
+    /* the port is LAN */
+    if (runner_cluster == DRV_IH_RUNNER_CLUSTER_A)
+    {
+        switch (portIndex)
+        {
+        case DRV_BBH_EMAC_0:
+             return ETH0_RX_DIRECT_RUNNER_A_TASK_NUMBER;
+
+        case DRV_BBH_EMAC_1:
+             return ETH1_RX_DIRECT_RUNNER_A_TASK_NUMBER;
+
+             /* we are not supposed to get here */
+         default:
+             return 0;
+         }
+    }/* runner B */
+    else
+    {
+        switch (portIndex)
+         {
+        case DRV_BBH_EMAC_0:
+             return ETH0_RX_DIRECT_RUNNER_B_TASK_NUMBER;
+
+        case DRV_BBH_EMAC_1:
+             return ETH1_RX_DIRECT_RUNNER_B_TASK_NUMBER;
+
+             /* we are not supposed to get here */
+         default:
+             return 0;
+         }
+    }
+}
+
+static void f_initialize_bbh_of_emac_port(DRV_BBH_PORT_INDEX port_index)
+{
+	uint16_t mdu_mode_read_pointer_address_in_byte;
+    uint32_t mdu_mode_read_pointer_address_in_byte_uint32;
+    DRV_BBH_TX_CONFIGURATION bbh_tx_configuration ;
+    DRV_BBH_RX_CONFIGURATION bbh_rx_configuration ;
+    DRV_BBH_PER_FLOW_CONFIGURATION per_flow_configuration ;
+
+    /*** BBH TX ***/
+    bbh_tx_configuration.dma_route_address = bbh_route_address_dma[port_index];
+    bbh_tx_configuration.bpm_route_address = bbh_route_address_bpm[port_index];
+    bbh_tx_configuration.sdma_route_address = bbh_route_address_sdma[port_index];
+    bbh_tx_configuration.sbpm_route_address = bbh_route_address_sbpm[port_index];
+    /* runner 0 is the one which handles TX  except for wan mode emac4*/
+    if ( port_index == DRV_BBH_EMAC_0 )
+    {
+        bbh_tx_configuration.runner_route_address = bbh_route_address_runner_1[port_index];
+    }
+    else
+    {
+        bbh_tx_configuration.runner_route_address = bbh_route_address_runner_0[port_index];
+    }
+
+    bbh_tx_configuration.ddr_buffer_size = DRV_BBH_DDR_BUFFER_SIZE;
+    bbh_tx_configuration.ddr_bpm_message_format = DRV_BBH_DDR_BPM_MESSAGE_FORMAT;
+    bbh_tx_configuration.payload_offset_resolution = DRV_BBH_PAYLOAD_OFFSET_RESOLUTION_2_B;
+    bbh_tx_configuration.multicast_headers_base_address_in_byte = (uint32_t) pDpiCfg->runner_mc_base_addr_phys;
+
+    if ( port_index == DRV_BBH_EMAC_0 )
+    {
+        bbh_tx_configuration.multicast_header_size = BBH_MULTICAST_HEADER_SIZE_FOR_LAN_PORT;
+        /* this is the task also in Gbe case */
+        bbh_tx_configuration.task_0 = WAN1_TX_THREAD_NUMBER;
+        bbh_tx_configuration.skb_address = MS_BYTE_TO_8_BYTE_RESOLUTION(ETHWAN_ABSOLUTE_TX_BBH_COUNTER_ADDRESS);
+    }
+    else
+        /*we will reach here in case the BBH port in lan ports 0 - 4*/
+    {
+        bbh_tx_configuration.multicast_header_size = BBH_MULTICAST_HEADER_SIZE_FOR_LAN_PORT;
+
+        bbh_tx_configuration.skb_address = MS_BYTE_TO_8_BYTE_RESOLUTION(EMAC_ABSOLUTE_TX_BBH_COUNTER_ADDRESS) + bbh_to_rdd_emac_map[port_index];
+
+        bbh_tx_configuration.task_0 = ETH_TX_THREAD_NUMBER;
+    }
+
+    /* other task numbers are irrelevant (relevant for DSL only) */
+    bbh_tx_configuration.task_1 = 0;
+    bbh_tx_configuration.task_2 = 0;
+    bbh_tx_configuration.task_3 = 0;
+    bbh_tx_configuration.task_4 = 0;
+    bbh_tx_configuration.task_5 = 0;
+    bbh_tx_configuration.task_6 = 0;
+    bbh_tx_configuration.task_7 = 0;
+    bbh_tx_configuration.task_8_39 = 0;
+
+
+    if ( port_index == DRV_BBH_EMAC_0 )
+    {
+        bbh_tx_configuration.mdu_mode_enable = 0;
+        /* irrelevant in this case */
+        bbh_tx_configuration.mdu_mode_read_pointer_address_in_8_byte = 0;
+    }
+    else
+    {
+        bbh_tx_configuration.mdu_mode_enable = 1;
+
+        rdd_mdu_mode_pointer_get(bbh_to_rdd_emac_map[port_index], &mdu_mode_read_pointer_address_in_byte);
+
+        mdu_mode_read_pointer_address_in_byte_uint32 = mdu_mode_read_pointer_address_in_byte;
+
+        /* after division, this will be back a 16 bit number */
+        bbh_tx_configuration.mdu_mode_read_pointer_address_in_8_byte = (uint16_t)MS_BYTE_TO_8_BYTE_RESOLUTION(mdu_mode_read_pointer_address_in_byte_uint32);
+    }
+
+    /* For Ethernet port working in MDU mode, PD FIFO size should be configured to 4 (and not 8). */
+    bbh_tx_configuration.pd_fifo_size_0 =  (bbh_tx_configuration.mdu_mode_enable == 1) ? BBH_TX_EMAC_PD_FIFO_SIZE_MDU_MODE_ENABLED : BBH_TX_EMAC_PD_FIFO_SIZE_MDU_MODE_DISABLED;
+
+    /* other FIFOs are irrelevant (relevant for DSL only) */
+    bbh_tx_configuration.pd_fifo_size_1 = DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE;
+    bbh_tx_configuration.pd_fifo_size_2 = DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE;
+    bbh_tx_configuration.pd_fifo_size_3 = DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE;
+    bbh_tx_configuration.pd_fifo_size_4 = DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE;
+    bbh_tx_configuration.pd_fifo_size_5 = DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE;
+    bbh_tx_configuration.pd_fifo_size_6 = DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE;
+    bbh_tx_configuration.pd_fifo_size_7 = DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE;
+    bbh_tx_configuration.pd_fifo_size_8_15 = DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE;
+    bbh_tx_configuration.pd_fifo_size_16_23 = DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE;
+    bbh_tx_configuration.pd_fifo_size_24_31 = DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE;
+    bbh_tx_configuration.pd_fifo_size_32_39 = DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE;
+
+    bbh_tx_configuration.pd_fifo_base_0 = 0;
+
+    /* other FIFOs are irrelevant (relevant for DSL only) */
+    bbh_tx_configuration.pd_fifo_base_1 = 0;
+    bbh_tx_configuration.pd_fifo_base_2 = 0;
+    bbh_tx_configuration.pd_fifo_base_3 = 0;
+    bbh_tx_configuration.pd_fifo_base_4 = 0;
+    bbh_tx_configuration.pd_fifo_base_5 = 0;
+    bbh_tx_configuration.pd_fifo_base_6 = 0;
+    bbh_tx_configuration.pd_fifo_base_7 = 0;
+    bbh_tx_configuration.pd_fifo_base_8_15 = 0;
+    bbh_tx_configuration.pd_fifo_base_16_23 = 0;
+    bbh_tx_configuration.pd_fifo_base_24_31 = 0;
+    bbh_tx_configuration.pd_fifo_base_32_39 = 0;
+
+    /* pd_prefetch_byte_threshold feature is irrelevant in EMAC (since there is only one FIFO) */
+    bbh_tx_configuration.pd_prefetch_byte_threshold_enable = 0;
+    bbh_tx_configuration.pd_prefetch_byte_threshold_0_in_32_byte = 0;
+    bbh_tx_configuration.pd_prefetch_byte_threshold_1_in_32_byte = 0;
+    bbh_tx_configuration.pd_prefetch_byte_threshold_2_in_32_byte = 0;
+    bbh_tx_configuration.pd_prefetch_byte_threshold_3_in_32_byte = 0;
+    bbh_tx_configuration.pd_prefetch_byte_threshold_4_in_32_byte = 0;
+    bbh_tx_configuration.pd_prefetch_byte_threshold_5_in_32_byte = 0;
+    bbh_tx_configuration.pd_prefetch_byte_threshold_6_in_32_byte = 0;
+    bbh_tx_configuration.pd_prefetch_byte_threshold_7_in_32_byte = 0;
+    bbh_tx_configuration.pd_prefetch_byte_threshold_8_39_in_32_byte = 0;
+
+    bbh_tx_configuration.dma_read_requests_fifo_base_address = bbh_dma_and_sdma_read_requests_fifo_base_address[port_index];
+    bbh_tx_configuration.dma_read_requests_maximal_number = BBH_TX_CONFIGURATIONS_DMACFG_TX_MAXREQ_MAX_VALUE_VALUE_RESET_VALUE;
+    bbh_tx_configuration.sdma_read_requests_fifo_base_address = bbh_dma_and_sdma_read_requests_fifo_base_address[port_index];
+    bbh_tx_configuration.sdma_read_requests_maximal_number = BBH_TX_CONFIGURATIONS_SDMACFG_TX_MAXREQ_MAX_VALUE_VALUE_RESET_VALUE;
+
+    /* irrelevant in EMAC case */
+    bbh_tx_configuration.tcont_address_in_8_byte = 0;
+
+    bbh_tx_configuration.ddr_tm_base_address = (uint32_t)pDpiCfg->runner_tm_base_addr_phys;
+
+    bbh_tx_configuration.emac_1588_enable = 0;
+
+    fi_bl_drv_bbh_tx_set_configuration(port_index, &bbh_tx_configuration);
+
+    /*** BBH RX ***/
+    /* bbh_rx_set_configuration */
+    bbh_rx_configuration.dma_route_address = bbh_route_address_dma[port_index];
+    bbh_rx_configuration.bpm_route_address = bbh_route_address_bpm[port_index];
+    bbh_rx_configuration.sdma_route_address = bbh_route_address_sdma[port_index];
+    bbh_rx_configuration.sbpm_route_address = bbh_route_address_sbpm[port_index];
+    bbh_rx_configuration.runner_0_route_address = bbh_route_address_runner_0[port_index];
+    bbh_rx_configuration.runner_1_route_address = bbh_route_address_runner_1[port_index];
+    bbh_rx_configuration.ih_route_address = bbh_route_address_ih[port_index];
+
+    bbh_rx_configuration.ddr_buffer_size = DRV_BBH_DDR_BUFFER_SIZE;
+    bbh_rx_configuration.ddr_bpm_message_format = DRV_BBH_DDR_BPM_MESSAGE_FORMAT;
+    bbh_rx_configuration.ddr_tm_base_address = (uint32_t)pDpiCfg->runner_tm_base_addr_phys;
+    bbh_rx_configuration.pd_fifo_base_address_normal_queue_in_8_byte = f_get_bbh_rx_pd_fifo_base_address_normal_queue_in_8_byte(port_index);
+    bbh_rx_configuration.pd_fifo_base_address_direct_queue_in_8_byte = f_get_bbh_rx_pd_fifo_base_address_direct_queue_in_8_byte(port_index);
+    bbh_rx_configuration.pd_fifo_size_normal_queue = DRV_RDD_IH_RUNNER_0_MAXIMAL_NUMBER_OF_BUFFERS;
+    bbh_rx_configuration.pd_fifo_size_direct_queue = DRV_RDD_IH_RUNNER_0_MAXIMAL_NUMBER_OF_BUFFERS;
+    bbh_rx_configuration.runner_0_task_normal_queue = f_bbh_rx_runner_task_normal_queue (DRV_IH_RUNNER_CLUSTER_A, port_index);
+    bbh_rx_configuration.runner_0_task_direct_queue = f_bbh_rx_runner_task_direct_queue (DRV_IH_RUNNER_CLUSTER_A, port_index);
+    bbh_rx_configuration.runner_1_task_normal_queue = f_bbh_rx_runner_task_normal_queue (DRV_IH_RUNNER_CLUSTER_B, port_index);
+    bbh_rx_configuration.runner_1_task_direct_queue = f_bbh_rx_runner_task_direct_queue (DRV_IH_RUNNER_CLUSTER_B, port_index);
+    bbh_rx_configuration.dma_data_fifo_base_address = BBH_RX_DMA_FIFOS_SIZE_LAN_BBH * port_index;
+    bbh_rx_configuration.dma_chunk_descriptor_fifo_base_address = BBH_RX_DMA_FIFOS_SIZE_LAN_BBH * port_index;
+    bbh_rx_configuration.sdma_data_fifo_base_address = bbh_rx_sdma_data_fifo_base_address[port_index];
+    bbh_rx_configuration.sdma_chunk_descriptor_fifo_base_address = bbh_rx_sdma_chunk_descriptor_fifo_base_address[port_index ];
+    bbh_rx_configuration.dma_data_and_chunk_descriptor_fifos_size = BBH_RX_DMA_FIFOS_SIZE_LAN_BBH;
+    bbh_rx_configuration.dma_exclusive_threshold = BBH_RX_DMA_EXCLUSIVE_THRESHOLD_LAN_BBH;
+    bbh_rx_configuration.sdma_data_and_chunk_descriptor_fifos_size = bbh_rx_sdma_data_and_chunk_descriptor_fifos_size[port_index ];
+    bbh_rx_configuration.sdma_exclusive_threshold = bbh_rx_sdma_exclusive_threshold[port_index];
+
+
+    bbh_rx_configuration.minimum_packet_size_0 = MIN_ETH_PKT_SIZE;
+
+
+    /* minimum_packet_size 1-3 are not in use */
+    bbh_rx_configuration.minimum_packet_size_1 = MIN_ETH_PKT_SIZE;
+    bbh_rx_configuration.minimum_packet_size_2 = MIN_ETH_PKT_SIZE;
+    bbh_rx_configuration.minimum_packet_size_3 = MIN_ETH_PKT_SIZE;
+
+
+    bbh_rx_configuration.maximum_packet_size_0 = pDpiCfg->mtu_size;
+
+
+    /* maximum_packet_size 1-3 are not in use */
+    bbh_rx_configuration.maximum_packet_size_1 = pDpiCfg->mtu_size;
+    bbh_rx_configuration.maximum_packet_size_2 = pDpiCfg->mtu_size;
+    bbh_rx_configuration.maximum_packet_size_3 = pDpiCfg->mtu_size;
+
+    bbh_rx_configuration.ih_ingress_buffers_bitmask = bbh_ih_ingress_buffers_bitmask[port_index];
+    bbh_rx_configuration.packet_header_offset = DRV_RDD_IH_PACKET_HEADER_OFFSET;
+    bbh_rx_configuration.reassembly_offset_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION(pDpiCfg->headroom_size);
+
+    /* By default, the triggers for FC will be disabled and the triggers for drop enabled.
+       If the user configures flow control for the port, the triggers for drop will be
+       disabled and triggers for FC (including Runner request) will be enabled */
+    bbh_rx_configuration.flow_control_triggers_bitmask = 0;
+    bbh_rx_configuration.drop_triggers_bitmask = DRV_BBH_RX_DROP_TRIGGER_BPM_IS_IN_EXCLUSIVE_STATE | DRV_BBH_RX_DROP_TRIGGER_SBPM_IS_IN_EXCLUSIVE_STATE;
+
+    /* following configuration is irrelevant in EMAC case */
+    bbh_rx_configuration.flows_32_255_group_divider = BBH_RX_FLOWS_32_255_GROUP_DIVIDER;
+    bbh_rx_configuration.ploam_default_ih_class = 0;
+    bbh_rx_configuration.ploam_ih_class_override = 0;
+
+    fi_bl_drv_bbh_rx_set_configuration(port_index, &bbh_rx_configuration);
+
+    /* bbh_rx_set_per_flow_configuration */
+    per_flow_configuration.minimum_packet_size_selection = BBH_RX_ETH_MIN_PKT_SIZE_SELECTION_INDEX;
+    per_flow_configuration.maximum_packet_size_selection = BBH_RX_MAX_PKT_SIZE_SELECTION_INDEX;
+
+    if ( port_index == DRV_BBH_EMAC_0 )
+    {
+        per_flow_configuration.default_ih_class = DRV_RDD_IH_CLASS_WAN_BRIDGED_LOW_INDEX;
+        per_flow_configuration.ih_class_override = 1;
+    }
+    else
+    {
+        per_flow_configuration.ih_class_override = 0;
+
+        switch (port_index)
+        {
+        case DRV_BBH_EMAC_0:
+            per_flow_configuration.default_ih_class = DRV_RDD_IH_CLASS_LAN_BRIDGED_ETH0_INDEX;
+            break;
+        case DRV_BBH_EMAC_1:
+            per_flow_configuration.default_ih_class = DRV_RDD_IH_CLASS_LAN_BRIDGED_ETH1_INDEX;
+            break;
+        default:
+            return;
+            break;
+        }
+    }
+
+    /* in EMAC, only flow 0 is relevant */
+    fi_bl_drv_bbh_rx_set_per_flow_configuration(port_index, 0, &per_flow_configuration);
+
+    return;
+}
+/* this function configures all 8 ingress queues in IH */
+static int fi_ih_configure_ingress_queues(void)
+{
+    int i;
+    DRV_IH_INGRESS_QUEUE_CONFIG ingress_queue_config;
+    uint8_t base_location = 0;
+
+    /* queues of EMAC 0 */
+    ingress_queue_config.base_location = base_location;
+    ingress_queue_config.size = IH_INGRESS_QUEUE_SIZE_WAN;
+    ingress_queue_config.priority = IH_INGRESS_QUEUE_PRIORITY_WAN;
+    ingress_queue_config.weight = IH_INGRESS_QUEUE_WEIGHT_WAN;
+    ingress_queue_config.congestion_threshold = IH_INGRESS_QUEUE_CONGESTION_THRESHOLD_WAN_ETH;
+
+    fi_bl_drv_ih_configure_ingress_queue(IH_INGRESS_QUEUE_0_ETH0, &ingress_queue_config);
+
+    /* update the correspoding bitmask in database, to be configured in BBH */
+    f_update_bbh_ih_ingress_buffers_bitmask(DRV_BBH_EMAC_0, ingress_queue_config.base_location, ingress_queue_config.size);
+
+    base_location += ingress_queue_config.size;
+
+    /* queues of EMAC 1 */
+    ingress_queue_config.base_location = base_location;
+    ingress_queue_config.size = IH_INGRESS_QUEUE_SIZE_LAN_EMACS;
+    ingress_queue_config.priority = IH_INGRESS_QUEUE_PRIORITY_LAN_EMACS;
+    ingress_queue_config.weight = IH_INGRESS_QUEUE_WEIGHT_LAN_EMACS;
+    ingress_queue_config.congestion_threshold = IH_INGRESS_QUEUE_CONGESTION_THRESHOLD_LAN_EMACS;
+
+    fi_bl_drv_ih_configure_ingress_queue(IH_INGRESS_QUEUE_1_ETH1, &ingress_queue_config);
+
+    /* update the correspoding bitmask in database, to be configured in BBH */
+    f_update_bbh_ih_ingress_buffers_bitmask(DRV_BBH_EMAC_1, ingress_queue_config.base_location, ingress_queue_config.size);
+
+    base_location += ingress_queue_config.size;
+
+    /* queues of DSL */
+    ingress_queue_config.base_location = base_location;
+    ingress_queue_config.size = IH_INGRESS_QUEUE_SIZE_WAN;
+    ingress_queue_config.priority = IH_INGRESS_QUEUE_PRIORITY_WAN;
+    ingress_queue_config.weight = IH_INGRESS_QUEUE_WEIGHT_WAN;
+    ingress_queue_config.congestion_threshold = IH_INGRESS_QUEUE_CONGESTION_THRESHOLD_WAN_DSL;
+
+    fi_bl_drv_ih_configure_ingress_queue(IH_INGRESS_QUEUE_5_DSL, &ingress_queue_config);
+
+    /* update the correspoding bitmask in database, to be configured in BBH */
+    f_update_bbh_ih_ingress_buffers_bitmask(DRV_BBH_DSL, ingress_queue_config.base_location, ingress_queue_config.size);
+
+    base_location += ingress_queue_config.size;
+
+    /* queues of runners */
+    for (i = IH_INGRESS_QUEUE_6_RUNNER_A; i <= IH_INGRESS_QUEUE_6_RUNNER_A; i++)
+    {
+        ingress_queue_config.base_location = base_location;
+        ingress_queue_config.size = IH_INGRESS_QUEUE_SIZE_RUNNERS;
+        ingress_queue_config.priority = IH_INGRESS_QUEUE_PRIORITY_RUNNERS;
+        ingress_queue_config.weight = IH_INGRESS_QUEUE_WEIGHT_RUNNERS;
+        ingress_queue_config.congestion_threshold = IH_INGRESS_QUEUE_CONGESTION_THRESHOLD_RUNNERS;
+
+        fi_bl_drv_ih_configure_ingress_queue (i, &ingress_queue_config);
+
+        base_location += ingress_queue_config.size;
+    }
+
+    /* check that we didn't overrun */
+    if (base_location > DRV_IH_INGRESS_QUEUES_ARRAY_SIZE)
+    {
+        /* sum of sizes exceeded the total array size */
+        return DPI_RC_ERROR;
+    }
+    return DPI_RC_OK;
+}
+
+/* this function configures the IH classes which are in use */
+static void f_ih_configure_lookup_tables(void)
+{
+    DRV_IH_LOOKUP_TABLE_60_BIT_KEY_CONFIG lookup_table_60_bit_key_config ;
+
+    /*** table 1: MAC DA ***/
+    lookup_table_60_bit_key_config.table_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_LOOKUP_TABLE_1_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.table_size = DRV_RDD_IH_LOOKUP_TABLE_1_SIZE;
+    lookup_table_60_bit_key_config.maximal_search_depth = DRV_RDD_IH_LOOKUP_TABLE_1_SEARCH_DEPTH;
+    lookup_table_60_bit_key_config.hash_type = DRV_RDD_IH_LOOKUP_TABLE_1_HASH_TYPE;
+    lookup_table_60_bit_key_config.sa_search_enable = DRV_RDD_IH_LOOKUP_TABLE_1_SA_ENABLE;
+    lookup_table_60_bit_key_config.aging_enable = DRV_RDD_IH_LOOKUP_TABLE_1_AGING_ENABLE;
+    lookup_table_60_bit_key_config.cam_enable = DRV_RDD_IH_LOOKUP_TABLE_1_CAM_ENABLE;
+    lookup_table_60_bit_key_config.cam_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_LOOKUP_TABLE_1_CAM_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.context_table_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_CONTEXT_TABLE_1_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.context_table_entry_size = DRV_RDD_IH_CONTEXT_TABLE_1_ENTRY_SIZE;
+    lookup_table_60_bit_key_config.cam_context_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_CONTEXT_TABLE_1_CAM_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.part_0_start_offset_in_4_byte = DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_0_START_OFFSET;
+    lookup_table_60_bit_key_config.part_0_shift_offset_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_0_SHIFT;
+    lookup_table_60_bit_key_config.part_1_start_offset_in_4_byte = DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_1_START_OFFSET;
+    lookup_table_60_bit_key_config.part_1_shift_offset_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_1_SHIFT;
+    lookup_table_60_bit_key_config.key_extension = DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_KEY_EXTENSION;
+    lookup_table_60_bit_key_config.part_0_mask_low = DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_0_MASK_LOW;
+    lookup_table_60_bit_key_config.part_0_mask_high = DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_0_MASK_HIGH;
+    lookup_table_60_bit_key_config.part_1_mask_low = DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_1_MASK_LOW;
+    lookup_table_60_bit_key_config.part_1_mask_high = DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_1_MASK_HIGH;
+    lookup_table_60_bit_key_config.global_mask_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_GLOBAL_MASK;
+
+    fi_bl_drv_ih_configure_lut_60_bit_key(DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX, &lookup_table_60_bit_key_config);
+
+    //TODO:move that function to RDPA_System
+    /*** table 2: IPTV ***/
+    //rdpa_ih_cfg_iptv_lookup_table(iptv_lookup_method_mac);
+
+    /*** table 3: DS ingress classification ***/
+    lookup_table_60_bit_key_config.table_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_LOOKUP_TABLE_3_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.table_size = DRV_RDD_IH_LOOKUP_TABLE_3_SIZE;
+    lookup_table_60_bit_key_config.maximal_search_depth = DRV_RDD_IH_LOOKUP_TABLE_3_SEARCH_DEPTH;
+    lookup_table_60_bit_key_config.hash_type = DRV_RDD_IH_LOOKUP_TABLE_3_HASH_TYPE;
+    lookup_table_60_bit_key_config.sa_search_enable = DRV_RDD_IH_LOOKUP_TABLE_3_SA_ENABLE;
+    lookup_table_60_bit_key_config.aging_enable = DRV_RDD_IH_LOOKUP_TABLE_3_AGING_ENABLE;
+    lookup_table_60_bit_key_config.cam_enable = DRV_RDD_IH_LOOKUP_TABLE_3_CAM_ENABLE;
+    lookup_table_60_bit_key_config.cam_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_LOOKUP_TABLE_3_CAM_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.context_table_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_CONTEXT_TABLE_3_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.context_table_entry_size = DRV_RDD_IH_CONTEXT_TABLE_3_ENTRY_SIZE;
+    lookup_table_60_bit_key_config.cam_context_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_CONTEXT_TABLE_3_CAM_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.part_0_start_offset_in_4_byte = DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_0_START_OFFSET;
+    lookup_table_60_bit_key_config.part_0_shift_offset_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_0_SHIFT;
+    lookup_table_60_bit_key_config.part_1_start_offset_in_4_byte = DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_1_START_OFFSET;
+    lookup_table_60_bit_key_config.part_1_shift_offset_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_1_SHIFT;
+    lookup_table_60_bit_key_config.key_extension = DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_KEY_EXTENSION;
+    lookup_table_60_bit_key_config.part_0_mask_low = DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_0_MASK_LOW;
+    lookup_table_60_bit_key_config.part_0_mask_high = DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_0_MASK_HIGH;
+    lookup_table_60_bit_key_config.part_1_mask_low = DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_1_MASK_LOW;
+    lookup_table_60_bit_key_config.part_1_mask_high = DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_1_MASK_HIGH;
+    lookup_table_60_bit_key_config.global_mask_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_GLOBAL_MASK;
+
+    fi_bl_drv_ih_configure_lut_60_bit_key(DRV_RDD_IH_LOOKUP_TABLE_DS_INGRESS_CLASSIFICATION_INDEX, &lookup_table_60_bit_key_config);
+
+    /*** table 4: US ingress classification 1 per LAN port ***/
+    lookup_table_60_bit_key_config.table_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_LOOKUP_TABLE_4_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.table_size = DRV_RDD_IH_LOOKUP_TABLE_4_SIZE;
+    lookup_table_60_bit_key_config.maximal_search_depth = DRV_RDD_IH_LOOKUP_TABLE_4_SEARCH_DEPTH;
+    lookup_table_60_bit_key_config.hash_type = DRV_RDD_IH_LOOKUP_TABLE_4_HASH_TYPE;
+    lookup_table_60_bit_key_config.sa_search_enable = DRV_RDD_IH_LOOKUP_TABLE_4_SA_ENABLE;
+    lookup_table_60_bit_key_config.aging_enable = DRV_RDD_IH_LOOKUP_TABLE_4_AGING_ENABLE;
+    lookup_table_60_bit_key_config.cam_enable = DRV_RDD_IH_LOOKUP_TABLE_4_CAM_ENABLE;
+    lookup_table_60_bit_key_config.cam_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_LOOKUP_TABLE_4_CAM_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.context_table_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_CONTEXT_TABLE_4_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.context_table_entry_size = DRV_RDD_IH_CONTEXT_TABLE_4_ENTRY_SIZE;
+    lookup_table_60_bit_key_config.cam_context_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_CONTEXT_TABLE_4_CAM_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.part_0_start_offset_in_4_byte = DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_0_START_OFFSET;
+    lookup_table_60_bit_key_config.part_0_shift_offset_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_0_SHIFT;
+    lookup_table_60_bit_key_config.part_1_start_offset_in_4_byte = DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_1_START_OFFSET;
+    lookup_table_60_bit_key_config.part_1_shift_offset_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_1_SHIFT;
+    lookup_table_60_bit_key_config.key_extension = DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_KEY_EXTENSION;
+    lookup_table_60_bit_key_config.part_0_mask_low = DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_0_MASK_LOW;
+    lookup_table_60_bit_key_config.part_0_mask_high = DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_0_MASK_HIGH;
+    lookup_table_60_bit_key_config.part_1_mask_low = DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_1_MASK_LOW;
+    lookup_table_60_bit_key_config.part_1_mask_high = DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_1_MASK_HIGH;
+    lookup_table_60_bit_key_config.global_mask_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_GLOBAL_MASK;
+
+    fi_bl_drv_ih_configure_lut_60_bit_key(DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX, &lookup_table_60_bit_key_config);
+
+    /*** table 6: IPTV source IP ***/
+    lookup_table_60_bit_key_config.table_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_LOOKUP_TABLE_6_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.table_size = DRV_RDD_IH_LOOKUP_TABLE_6_SIZE;
+    lookup_table_60_bit_key_config.maximal_search_depth = DRV_RDD_IH_LOOKUP_TABLE_6_SEARCH_DEPTH;
+    lookup_table_60_bit_key_config.hash_type = DRV_RDD_IH_LOOKUP_TABLE_6_HASH_TYPE;
+    lookup_table_60_bit_key_config.sa_search_enable = DRV_RDD_IH_LOOKUP_TABLE_6_SA_ENABLE;
+    lookup_table_60_bit_key_config.aging_enable = DRV_RDD_IH_LOOKUP_TABLE_6_AGING_ENABLE;
+    lookup_table_60_bit_key_config.cam_enable = DRV_RDD_IH_LOOKUP_TABLE_6_CAM_ENABLE;
+    lookup_table_60_bit_key_config.cam_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_LOOKUP_TABLE_6_CAM_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.context_table_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_CONTEXT_TABLE_6_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.context_table_entry_size = DRV_RDD_IH_CONTEXT_TABLE_6_ENTRY_SIZE;
+    lookup_table_60_bit_key_config.cam_context_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_CONTEXT_TABLE_6_CAM_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.part_0_start_offset_in_4_byte = DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_0_START_OFFSET;
+    lookup_table_60_bit_key_config.part_0_shift_offset_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_0_SHIFT;
+    lookup_table_60_bit_key_config.part_1_start_offset_in_4_byte = DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_1_START_OFFSET;
+    lookup_table_60_bit_key_config.part_1_shift_offset_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_1_SHIFT;
+    lookup_table_60_bit_key_config.key_extension = DRV_RDD_IH_LOOKUP_TABLE_6_KEY_KEY_EXTENSION;
+    lookup_table_60_bit_key_config.part_0_mask_low = DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_0_MASK_LOW;
+    lookup_table_60_bit_key_config.part_0_mask_high = DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_0_MASK_HIGH;
+    lookup_table_60_bit_key_config.part_1_mask_low = DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_1_MASK_LOW;
+    lookup_table_60_bit_key_config.part_1_mask_high = DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_1_MASK_HIGH;
+    lookup_table_60_bit_key_config.global_mask_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_6_KEY_GLOBAL_MASK;
+
+    fi_bl_drv_ih_configure_lut_60_bit_key(DRV_RDD_IH_LOOKUP_TABLE_IPTV_SRC_IP_INDEX, &lookup_table_60_bit_key_config);
+
+    /*** table 9: MAC SA ***/
+    lookup_table_60_bit_key_config.table_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_LOOKUP_TABLE_9_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.table_size = DRV_RDD_IH_LOOKUP_TABLE_9_SIZE;
+    lookup_table_60_bit_key_config.maximal_search_depth = DRV_RDD_IH_LOOKUP_TABLE_9_SEARCH_DEPTH;
+    lookup_table_60_bit_key_config.hash_type = DRV_RDD_IH_LOOKUP_TABLE_9_HASH_TYPE;
+    lookup_table_60_bit_key_config.sa_search_enable = DRV_RDD_IH_LOOKUP_TABLE_9_SA_ENABLE;
+    lookup_table_60_bit_key_config.aging_enable = DRV_RDD_IH_LOOKUP_TABLE_9_AGING_ENABLE;
+    lookup_table_60_bit_key_config.cam_enable = DRV_RDD_IH_LOOKUP_TABLE_9_CAM_ENABLE;
+    lookup_table_60_bit_key_config.cam_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_LOOKUP_TABLE_9_CAM_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.context_table_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_CONTEXT_TABLE_9_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.context_table_entry_size = DRV_RDD_IH_CONTEXT_TABLE_9_ENTRY_SIZE;
+    lookup_table_60_bit_key_config.cam_context_base_address_in_8_byte = MS_BYTE_TO_8_BYTE_RESOLUTION (DRV_RDD_IH_CONTEXT_TABLE_9_CAM_BASE_ADDRESS);
+    lookup_table_60_bit_key_config.part_0_start_offset_in_4_byte = DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_0_START_OFFSET;
+    lookup_table_60_bit_key_config.part_0_shift_offset_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_0_SHIFT;
+    lookup_table_60_bit_key_config.part_1_start_offset_in_4_byte = DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_1_START_OFFSET;
+    lookup_table_60_bit_key_config.part_1_shift_offset_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_1_SHIFT;
+    lookup_table_60_bit_key_config.key_extension = DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_KEY_EXTENSION;
+    lookup_table_60_bit_key_config.part_0_mask_low = DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_0_MASK_LOW;
+    lookup_table_60_bit_key_config.part_0_mask_high = DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_0_MASK_HIGH;
+    lookup_table_60_bit_key_config.part_1_mask_low = DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_1_MASK_LOW;
+    lookup_table_60_bit_key_config.part_1_mask_high = DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_1_MASK_HIGH;
+    lookup_table_60_bit_key_config.global_mask_in_4_bit = DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_GLOBAL_MASK;
+
+    fi_bl_drv_ih_configure_lut_60_bit_key(DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX,
+        &lookup_table_60_bit_key_config);
+}
+static uint32_t is_matrix_source_lan(DRV_IH_TARGET_MATRIX_SOURCE_PORT source_port)
+{
+
+    if ( source_port != DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH0 && source_port != DRV_IH_TARGET_MATRIX_SOURCE_PORT_GPON )
+    {
+        return 1;
+    }
+    return 0;
+}
+
+static uint32_t is_matrix_dest_lan(DRV_IH_TARGET_MATRIX_SOURCE_PORT source_port)
+{
+    if ( source_port != DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH0 && source_port != DRV_IH_TARGET_MATRIX_SOURCE_PORT_GPON )
+    {
+        return 1;
+    }
+    return 0;
+}
+
+static uint32_t is_matrix_source_wan(DRV_IH_TARGET_MATRIX_SOURCE_PORT source_port)
+{
+    if ( source_port == DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH0 || source_port == DRV_IH_TARGET_MATRIX_SOURCE_PORT_GPON )
+    {
+        return 1;
+    }
+    return 0;
+}
+/* calculates the "direct_mode" value for target matrix */
+static uint32_t f_ih_calculate_direct_mode(DRV_IH_TARGET_MATRIX_SOURCE_PORT source_port,
+									DRV_IH_TARGET_MATRIX_DESTINATION_PORT destination_port)
+{
+    /* lan -> lan/pci/multicast: direct mode should be set */
+    if (is_matrix_source_lan(source_port) &&
+        (is_matrix_dest_lan(destination_port) ||
+        destination_port == DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE0 ||
+        destination_port == DRV_IH_TARGET_MATRIX_DESTINATION_PORT_MULTICAST) &&
+        (DRV_IH_TARGET_MATRIX_DESTINATION_PORT)source_port != destination_port)
+    {
+        return 1;
+    }
+    /* pci -> lan/pci: direct mode should be set */
+    else if (source_port == DRV_IH_TARGET_MATRIX_SOURCE_PORT_PCIE0 &&
+        (is_matrix_dest_lan(destination_port) || destination_port == DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE0))
+    {
+        return 1;
+    }
+    return 0;
+}
+static uint32_t f_ih_calculate_forward(DRV_IH_TARGET_MATRIX_SOURCE_PORT source_port, DRV_IH_TARGET_MATRIX_DESTINATION_PORT destination_port)
+{
+
+    /* no self forwarding except PCI */
+    if (source_port == DRV_IH_TARGET_MATRIX_SOURCE_PORT_PCIE0 &&
+        destination_port == DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE0)
+    {
+        return 1;
+    }
+    else if ((DRV_IH_TARGET_MATRIX_DESTINATION_PORT)source_port == destination_port)
+    {
+        return 0;
+    }
+    /* no self forwarding (if emac 4 is wan, then its, sp will be emac 4 and its dest port will be gpon */
+    else if (is_matrix_source_wan(source_port) && destination_port == DRV_IH_TARGET_MATRIX_DESTINATION_PORT_GPON)
+    {
+        return 0;
+    }
+    /* enable forwarding to LANs/WAN/PCI0 (PCI1 is not supported currently). */
+    else if (destination_port <= DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE0)
+    {
+        return 1;
+    }
+    /* forward to "multicast" from WAN/LAN port */
+    else if ((is_matrix_source_wan(source_port) || is_matrix_source_lan(source_port)) &&
+        (destination_port == DRV_IH_TARGET_MATRIX_DESTINATION_PORT_MULTICAST))
+    {
+        return 1;
+    }
+    return 0;
+}
+
+static void sbpm_drv_init(void)
+{
+    DRV_SBPM_GLOBAL_CONFIGURATION sbpm_global_configuration;
+    DRV_SBPM_USER_GROUPS_THRESHOLDS sbpm_ug_configuration;
+    int i;
+
+    sbpm_global_configuration.hysteresis = SBPM_DEFAULT_HYSTERESIS;
+    sbpm_global_configuration.threshold = SBPM_DEFAULT_THRESHOLD;
+
+    for (i = 0; i < ARRAY_LENGTH(sbpm_ug_configuration.ug_arr); i++)
+    {
+        sbpm_ug_configuration.ug_arr[i].hysteresis = SBPM_DEFAULT_HYSTERESIS;
+        sbpm_ug_configuration.ug_arr[i].threshold = SBPM_DEFAULT_THRESHOLD;
+        sbpm_ug_configuration.ug_arr[i].exclusive_hysteresis = SBPM_DEFAULT_HYSTERESIS;
+        sbpm_ug_configuration.ug_arr[i].exclusive_threshold = SBPM_DEFAULT_THRESHOLD;
+    }
+    fi_bl_drv_sbpm_init(SBPM_BASE_ADDRESS, SBPM_LIST_SIZE, SBPM_REPLY_ADDRESS, &sbpm_global_configuration,
+        &sbpm_ug_configuration);
+}
+
+#define VAL_2K      (2*1024)
+#define VAL_2_5K    (2*1024+512)
+#define VAL_4K      (4*1024)
+#define VAL_5K      (5*1024)
+#define VAL_7_5K    (7*1024+512)
+#define VAL_15K     (15*1024)
+#define VAL_16K     (16*1024)
+#define VAL_30K     (30*1024)
+
+static void rdp_bpm_threshod_get(const uint32_t max_bpm_bufs, uint32_t *p_bpm_gbl_thresh, uint32_t *p_bpm_def_thresh)
+{
+    if (max_bpm_bufs < VAL_2_5K)
+    {
+        *p_bpm_gbl_thresh = 0;
+        *p_bpm_def_thresh = 0;
+    }
+    else if (max_bpm_bufs < VAL_5K)
+    {
+        *p_bpm_gbl_thresh = DRV_BPM_GLOBAL_THRESHOLD_2_5K;
+        *p_bpm_def_thresh = VAL_2_5K;
+    }
+    else if (max_bpm_bufs < VAL_7_5K)
+    {
+        *p_bpm_gbl_thresh = DRV_BPM_GLOBAL_THRESHOLD_5K;
+        *p_bpm_def_thresh = VAL_5K;
+    }
+    else if (max_bpm_bufs < VAL_15K)
+    {
+        *p_bpm_gbl_thresh = DRV_BPM_GLOBAL_THRESHOLD_7_5K;
+        *p_bpm_def_thresh = VAL_7_5K;
+    }
+    else
+    {
+#if defined(DSL_63138)
+        if (max_bpm_bufs < VAL_30K)
+        {
+            *p_bpm_gbl_thresh = DRV_BPM_GLOBAL_THRESHOLD_15K;
+            *p_bpm_def_thresh = VAL_15K;
+        }
+        else
+        {
+            *p_bpm_gbl_thresh = DRV_BPM_GLOBAL_THRESHOLD_30K;
+            *p_bpm_def_thresh = VAL_30K;
+        }
+#else
+        *p_bpm_gbl_thresh = DRV_BPM_GLOBAL_THRESHOLD_15K;
+        *p_bpm_def_thresh = VAL_15K;
+#endif
+    }
+}
+static uint32_t rdp_bpm_buf_size(void)
+{
+    if (DRV_BBH_DDR_BUFFER_SIZE == DRV_BBH_DDR_BUFFER_SIZE_2_KB)
+    {
+        return VAL_2K;
+    }
+    else if (DRV_BBH_DDR_BUFFER_SIZE == DRV_BBH_DDR_BUFFER_SIZE_2_5_KB)
+    {
+        return VAL_2_5K;
+    }
+    else if (DRV_BBH_DDR_BUFFER_SIZE == DRV_BBH_DDR_BUFFER_SIZE_4_KB)
+    {
+        return VAL_4K;
+    }
+    else if (DRV_BBH_DDR_BUFFER_SIZE == DRV_BBH_DDR_BUFFER_SIZE_16_KB)
+    {
+        return VAL_16K;
+    }
+    return 0; /* Error */
+}
+
+static int rdp_bpm_cfg_params_get(S_DPI_CFG *pCfg, rdp_bpm_cfg_params *p_bpm_cfg_params)
+{
+    int sz_for_bpm, max_bpm_bufs, max_mc_bufs, max_bufs_supported, tm_mc_can_merge = 0, wasted_size = 0;
+    uint32_t bpm_buf_size, new_runner_mc_size, new_runner_tm_size;
+
+    if (((pCfg->runner_tm_base_addr + (pCfg->runner_tm_size << 20)) == pCfg->runner_mc_base_addr) &&
+        ((pCfg->runner_tm_base_addr_phys + (pCfg->runner_tm_size << 20)) == pCfg->runner_mc_base_addr_phys))
+    {
+        tm_mc_can_merge = 1;
+    } 
+    
+    if (((pCfg->runner_mc_base_addr + (pCfg->runner_mc_size << 20)) == pCfg->runner_tm_base_addr) &&
+        ((pCfg->runner_mc_base_addr_phys + (pCfg->runner_mc_size << 20)) == pCfg->runner_tm_base_addr_phys))
+        tm_mc_can_merge = 2;
+
+    bpm_buf_size = rdp_bpm_buf_size();
+    if (tm_mc_can_merge != 0)
+    {
+        /* calculate the bpm buffer number supported based on the total of memory size reserved */
+        sz_for_bpm = ((pCfg->runner_tm_size + pCfg->runner_mc_size) << 20) - RDP_DDR_DATA_STRUCTURES_SIZE;
+
+        max_bufs_supported = sz_for_bpm / (bpm_buf_size + 512);
+        if (max_bufs_supported < VAL_2_5K)
+            goto bpm_cfg_params_error;
+
+        rdp_bpm_threshod_get(max_bufs_supported, &p_bpm_cfg_params->bpm_gbl_thresh, &p_bpm_cfg_params->bpm_def_thresh);
+        new_runner_tm_size = ROUND_UP_MB(p_bpm_cfg_params->bpm_def_thresh * bpm_buf_size);
+        new_runner_mc_size = ROUND_UP_MB(p_bpm_cfg_params->bpm_def_thresh * 512);
+
+        if ((new_runner_tm_size + new_runner_mc_size) > sz_for_bpm)
+        {
+            max_bufs_supported = p_bpm_cfg_params->bpm_def_thresh - 1;
+            rdp_bpm_threshod_get(max_bufs_supported, &p_bpm_cfg_params->bpm_gbl_thresh, &p_bpm_cfg_params->bpm_def_thresh);
+            if (p_bpm_cfg_params->bpm_def_thresh == 0)
+                goto bpm_cfg_params_error;
+
+            new_runner_tm_size = ROUND_UP_MB(p_bpm_cfg_params->bpm_def_thresh * bpm_buf_size);
+            new_runner_mc_size = ROUND_UP_MB(p_bpm_cfg_params->bpm_def_thresh * 512);
+        }
+
+        new_runner_tm_size += RDP_DDR_DATA_STRUCTURES_SIZE;
+        wasted_size = pCfg->runner_tm_size - (new_runner_tm_size >> 20) + pCfg->runner_mc_size - (new_runner_mc_size >> 20);
+        /* we only need to adjust the reserved memory only when sizes for both tables have changed */
+        if ((pCfg->runner_tm_size != (new_runner_tm_size >> 20)) && (pCfg->runner_mc_size != (new_runner_mc_size >> 20)))
+        {
+            pCfg->runner_tm_size = new_runner_tm_size >> 20;
+            pCfg->runner_mc_size = new_runner_mc_size >> 20;
+            if (tm_mc_can_merge == 1)
+            {
+                pCfg->runner_mc_base_addr = pCfg->runner_tm_base_addr + new_runner_tm_size;
+                pCfg->runner_mc_base_addr_phys = pCfg->runner_tm_base_addr_phys + new_runner_tm_size;
+            }
+            else /* if (tm_mc_can_merge == 2) */
+            {
+                pCfg->runner_tm_base_addr = pCfg->runner_mc_base_addr + new_runner_mc_size;
+                pCfg->runner_tm_base_addr_phys = pCfg->runner_mc_base_addr_phys + new_runner_mc_size;
+            }
+            __print("RDP reserved memory has been adjusted\n"
+                    "\tTM: base_addr = 0x%p, phys_addr = 0x%p, size = %uMB\n"
+                    "\tMC: base_addr = 0x%p, phys_addr = 0x%p, size = %uMB\n",
+                    (void *)pCfg->runner_tm_base_addr, (void *)pCfg->runner_tm_base_addr_phys, pCfg->runner_tm_size,
+                    (void *)pCfg->runner_mc_base_addr, (void *)pCfg->runner_mc_base_addr_phys, pCfg->runner_mc_size);
+        }
+    }
+    else /* if (tm_mc_can_merge == 0) */
+    {
+        sz_for_bpm = (pCfg->runner_tm_size << 20) - RDP_DDR_DATA_STRUCTURES_SIZE;
+    
+        max_bpm_bufs = sz_for_bpm / bpm_buf_size;
+        if (max_bpm_bufs < VAL_2_5K)
+            goto bpm_cfg_params_error;
+
+        max_mc_bufs = pCfg->runner_mc_size << 11;  /* runner_mc_size * 1MB / 512B */
+        if (max_mc_bufs < VAL_2_5K)
+            goto bpm_cfg_params_error;
+
+        /* use whichever is less as the real buffer number supported */
+        if (max_mc_bufs > max_bpm_bufs)
+            max_bufs_supported = max_bpm_bufs;
+        else
+            max_bufs_supported = max_mc_bufs;
+
+        rdp_bpm_threshod_get(max_bufs_supported, &p_bpm_cfg_params->bpm_gbl_thresh, &p_bpm_cfg_params->bpm_def_thresh);
+
+        new_runner_tm_size = ROUND_UP_MB(p_bpm_cfg_params->bpm_def_thresh * bpm_buf_size) + RDP_DDR_DATA_STRUCTURES_SIZE;
+        new_runner_mc_size = ROUND_UP_MB(p_bpm_cfg_params->bpm_def_thresh * 512);
+        wasted_size = pCfg->runner_tm_size - (new_runner_tm_size >> 20) + pCfg->runner_mc_size - (new_runner_mc_size >> 20);
+    }
+
+    __print("\n RDP TM memory = %uMB, MC memory = %uMB : Max Possible Bufs <%u> of size <%u>; Allocating <%u> bufs; RDP enum <%u>\n",
+            pCfg->runner_tm_size, pCfg->runner_mc_size, max_bufs_supported, bpm_buf_size, p_bpm_cfg_params->bpm_def_thresh, p_bpm_cfg_params->bpm_gbl_thresh );
+    /* print some warrning messages when there are some significant amounts of wasted reserved memory */
+    if (wasted_size >= 5)
+        __print("WARNING!RDP reserved memories are wasting %dMB of memory, please adjust your reserved memory size\n", wasted_size);
+
+    return 0;
+
+bpm_cfg_params_error:
+
+    __print("\nRDP memory reservation required at least %uMB TM memory (%uMB for table + %uMB for buffer) "
+            "and %uMB MC memory\n",
+            ((ROUND_UP_MB(RDP_DDR_DATA_STRUCTURES_SIZE) + ROUND_UP_MB(VAL_2_5K * bpm_buf_size)) >> 20),
+            (ROUND_UP_MB(RDP_DDR_DATA_STRUCTURES_SIZE) >> 20),
+            (ROUND_UP_MB(VAL_2_5K * bpm_buf_size) >> 20),
+            (ROUND_UP_MB(VAL_2_5K << 9) >> 20));
+    __print("\nHave only reserved RDP TM memory = %uMB, MC memory = %uMB\n",
+            pCfg->runner_tm_size, pCfg->runner_mc_size);
+
+    return -1;
+
+}
+
+static void bpm_drv_init(S_DPI_CFG  *pCfg, rdp_bpm_cfg_params *p_bpm_cfg_params)
+{
+    DRV_BPM_GLOBAL_CONFIGURATION bpm_global_configuration;
+    DRV_BPM_USER_GROUPS_THRESHOLDS bpm_ug_configuration;
+    DRV_BPM_RUNNER_MSG_CTRL_PARAMS runner_msg_ctrl_params;
+    int i;
+
+    bpm_global_configuration.hysteresis = BPM_DEFAULT_HYSTERESIS;
+    bpm_global_configuration.threshold = p_bpm_cfg_params->bpm_gbl_thresh;
+    for (i = 0; i < ARRAY_LENGTH(bpm_ug_configuration.ug_arr); i++)
+    {
+        bpm_ug_configuration.ug_arr[i].hysteresis = BPM_DEFAULT_HYSTERESIS;
+        bpm_ug_configuration.ug_arr[i].threshold = (i == DRV_BPM_USER_GROUP_7) ?
+            BPM_CPU_NUMBER_OF_BUFFERS : p_bpm_cfg_params->bpm_def_thresh;
+        bpm_ug_configuration.ug_arr[i].exclusive_hysteresis = BPM_DEFAULT_HYSTERESIS;
+        bpm_ug_configuration.ug_arr[i].exclusive_threshold = (i == DRV_BPM_USER_GROUP_7) ?
+            BPM_CPU_NUMBER_OF_BUFFERS - 32 : p_bpm_cfg_params->bpm_def_thresh;
+    }
+
+    fi_bl_drv_bpm_init(&bpm_global_configuration,&bpm_ug_configuration, BPM_REPLY_RUNNER_A_ADDRESS, DRV_SPARE_BN_MESSAGE_FORMAT);
+
+    fi_bl_drv_bpm_get_runner_msg_ctrl(&runner_msg_ctrl_params);
+
+    runner_msg_ctrl_params.runner_a_reply_target_address = (BPM_REPLY_RUNNER_A_ADDRESS + 0x10000) >> 3;
+    runner_msg_ctrl_params.runner_b_reply_target_address = (BPM_REPLY_RUNNER_B_ADDRESS + 0x10000) >> 3;
+
+    fi_bl_drv_bpm_set_runner_msg_ctrl(&runner_msg_ctrl_params);
+
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_GPON, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_EMAC0, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_EMAC1, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_EMAC2, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_EMAC3, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_EMAC4, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_MIPS_C, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_MIPS_D, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_PCI0, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_PCI1, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_USB0, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_USB1, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_SPARE_0, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_SPARE_1, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_RNR_A, DRV_BPM_USER_GROUP_4);
+    fi_bl_drv_bpm_set_user_group_mapping(DRV_BPM_SP_RNR_B, DRV_BPM_USER_GROUP_4);
+}
+
+static void f_ih_configure_target_matrix(void)
+{
+    int i, j;
+    DRV_IH_TARGET_MATRIX_PER_SP_CONFIG per_sp_config;
+
+    for (i = DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH0; i < DRV_IH_TARGET_MATRIX_NUMBER_OF_SOURCE_PORTS; i++)
+    {
+        /* the destination ports after 'multicast' are not in use currently */
+        for (j = DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH0; j < DRV_IH_TARGET_MATRIX_NUMBER_OF_DESTINATION_PORTS; j++)
+        {
+            per_sp_config.entry[j].target_memory = DRV_IH_TARGET_MEMORY_DDR;
+            per_sp_config.entry[j].direct_mode = f_ih_calculate_direct_mode(i, j);
+
+            fi_bl_drv_ih_set_forward(i, j, f_ih_calculate_forward(i, j));
+        }
+        fi_bl_drv_ih_set_target_matrix(i, &per_sp_config);
+    }
+}
+
+static void f_ih_configure_parser(void)
+{
+    DRV_IH_PARSER_CONFIG parser_config ;
+
+    /* parser configuration */
+    parser_config.tcp_flags = TCP_CTRL_FLAG_FIN | TCP_CTRL_FLAG_RST | TCP_CTRL_FLAG_SYN;
+    parser_config.exception_status_bits = IH_PARSER_EXCEPTION_STATUS_BITS;
+    parser_config.ppp_code_1_ipv6 = 1;
+    parser_config.ipv6_extension_header_bitmask = 0;
+    parser_config.snap_user_defined_organization_code = IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_RESET_VALUE_RESET_VALUE;
+    parser_config.snap_rfc1042_encapsulation_enable = IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_DISABLED_VALUE_RESET_VALUE;
+    parser_config.snap_802_1q_encapsulation_enable = IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_DISABLED_VALUE_RESET_VALUE;
+    parser_config.gre_protocol = IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_PROTOCOL_VALUE_RESET_VALUE;
+
+    /*  eng[15] = eng[16] = 1 for AH header detection (IPv4 and IPv6) */
+    parser_config.eng_cfg = IH_PARSER_AH_DETECTION;
+
+    fi_bl_drv_ih_configure_parser(&parser_config);
+}
+
+
+
+/* this function configures the IH classes which are in use */
+static void f_ih_configure_classes(void)
+{
+    uint8_t i;
+
+    for (i = 0; i < ARRAY_LENGTH(gs_ih_classes); i++)
+    {
+        fi_bl_drv_ih_configure_class(gs_ih_classes[i].class_index, &gs_ih_classes[i].class_config);
+    }
+}
+
+static void f_ih_init(void)
+{
+    DRV_IH_GENERAL_CONFIG ih_general_config ;
+    DRV_IH_PACKET_HEADER_OFFSETS packet_header_offsets ;
+    DRV_IH_RUNNER_BUFFERS_CONFIG runner_buffers_config ;
+    DRV_IH_RUNNERS_LOAD_THRESHOLDS runners_load_thresholds ;
+    DRV_IH_ROUTE_ADDRESSES xi_route_addresses ;
+    DRV_IH_LOGICAL_PORTS_CONFIG logical_ports_config ;
+    DRV_IH_SOURCE_PORT_TO_INGRESS_QUEUE_MAPPING source_port_to_ingress_queue_mapping ;
+    DRV_IH_WAN_PORTS_CONFIG wan_ports_config ;
+
+    /* general configuration */
+    ih_general_config.runner_a_ih_response_address                  = MS_BYTE_TO_8_BYTE_RESOLUTION(RUNNER_FLOW_IH_RESPONSE_ADDRESS);
+    ih_general_config.runner_b_ih_response_address                  = MS_BYTE_TO_8_BYTE_RESOLUTION(RUNNER_FLOW_IH_RESPONSE_ADDRESS);
+    ih_general_config.runner_a_ih_congestion_report_address         = MS_BYTE_TO_8_BYTE_RESOLUTION(DRV_RDD_IH_RUNNER_0_IH_CONGESTION_REPORT_ADDRESS);
+    ih_general_config.runner_b_ih_congestion_report_address         = MS_BYTE_TO_8_BYTE_RESOLUTION(DRV_RDD_IH_RUNNER_1_IH_CONGESTION_REPORT_ADDRESS);
+    ih_general_config.runner_a_ih_congestion_report_enable          = DRV_RDD_IH_RUNNER_0_IH_CONGESTION_REPORT_ENABLE;
+    ih_general_config.runner_b_ih_congestion_report_enable          = DRV_RDD_IH_RUNNER_1_IH_CONGESTION_REPORT_ENABLE;
+    ih_general_config.lut_searches_enable_in_direct_mode            = 1;
+    ih_general_config.sn_stamping_enable_in_direct_mode             = 1;
+    ih_general_config.header_length_minimum                         = IH_HEADER_LENGTH_MIN;
+    ih_general_config.congestion_discard_disable                    = 0;
+    ih_general_config.cam_search_enable_upon_invalid_lut_entry      = DRV_RDD_IH_CAM_SEARCH_ENABLE_UPON_INVALID_LUT_ENTRY;
+
+    fi_bl_drv_ih_set_general_configuration(&ih_general_config);
+
+    /* packet header offsets configuration */
+    packet_header_offsets.eth0_packet_header_offset                 = DRV_RDD_IH_PACKET_HEADER_OFFSET;
+    packet_header_offsets.eth1_packet_header_offset                 = DRV_RDD_IH_PACKET_HEADER_OFFSET;
+    packet_header_offsets.gpon_packet_header_offset                 = DRV_RDD_IH_PACKET_HEADER_OFFSET;
+    packet_header_offsets.runner_a_packet_header_offset             = DRV_RDD_IH_PACKET_HEADER_OFFSET;
+    packet_header_offsets.runner_b_packet_header_offset             = DRV_RDD_IH_PACKET_HEADER_OFFSET;
+    packet_header_offsets.eth2_packet_header_offset                 = 0;
+    packet_header_offsets.eth3_packet_header_offset                 = 0;
+    packet_header_offsets.eth4_packet_header_offset                 = 0;
+
+    fi_bl_drv_ih_set_packet_header_offsets(& packet_header_offsets);
+
+    /* Runner Buffers configuration */
+    /* same ih_managed_rb_base_address should be used for both runners */
+    runner_buffers_config.runner_a_ih_managed_rb_base_address       = MS_BYTE_TO_8_BYTE_RESOLUTION(DRV_RDD_IH_RUNNER_0_IH_MANAGED_RB_BASE_ADDRESS);
+    runner_buffers_config.runner_b_ih_managed_rb_base_address       = MS_BYTE_TO_8_BYTE_RESOLUTION(DRV_RDD_IH_RUNNER_1_IH_MANAGED_RB_BASE_ADDRESS);
+    runner_buffers_config.runner_a_runner_managed_rb_base_address   = MS_BYTE_TO_8_BYTE_RESOLUTION(DRV_RDD_IH_RUNNER_0_RUNNER_MANAGED_RB_BASE_ADDRESS);
+    runner_buffers_config.runner_b_runner_managed_rb_base_address   = MS_BYTE_TO_8_BYTE_RESOLUTION(DRV_RDD_IH_RUNNER_1_RUNNER_MANAGED_RB_BASE_ADDRESS);
+    runner_buffers_config.runner_a_maximal_number_of_buffers        = DRV_IH_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS_32;
+    runner_buffers_config.runner_b_maximal_number_of_buffers        = DRV_IH_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS_32;
+
+    fi_bl_drv_ih_set_runner_buffers_configuration(&runner_buffers_config);
+
+    /* runners load thresholds configuration */
+    runners_load_thresholds.runner_a_high_congestion_threshold      = DRV_RDD_IH_RUNNER_0_MAXIMAL_NUMBER_OF_BUFFERS;
+    runners_load_thresholds.runner_b_high_congestion_threshold      = DRV_RDD_IH_RUNNER_0_MAXIMAL_NUMBER_OF_BUFFERS;
+    runners_load_thresholds.runner_a_exclusive_congestion_threshold = DRV_RDD_IH_RUNNER_0_MAXIMAL_NUMBER_OF_BUFFERS;
+    runners_load_thresholds.runner_b_exclusive_congestion_threshold = DRV_RDD_IH_RUNNER_0_MAXIMAL_NUMBER_OF_BUFFERS;
+    runners_load_thresholds.runner_a_load_balancing_threshold       = DRV_RDD_IH_RUNNER_0_MAXIMAL_NUMBER_OF_BUFFERS;
+    runners_load_thresholds.runner_b_load_balancing_threshold       = DRV_RDD_IH_RUNNER_0_MAXIMAL_NUMBER_OF_BUFFERS;
+    runners_load_thresholds.runner_a_load_balancing_hysteresis      = DRV_RDD_IH_RUNNER_0_MAXIMAL_NUMBER_OF_BUFFERS;
+    runners_load_thresholds.runner_b_load_balancing_hysteresis      = DRV_RDD_IH_RUNNER_0_MAXIMAL_NUMBER_OF_BUFFERS;
+
+    fi_bl_drv_ih_set_runners_load_thresholds (& runners_load_thresholds);
+
+    /* route addresses configuration */
+    xi_route_addresses.eth0_route_address     = IH_ETH0_ROUTE_ADDRESS;
+    xi_route_addresses.eth1_route_address     = IH_ETH1_ROUTE_ADDRESS;
+    xi_route_addresses.gpon_route_address     = IH_DSL_ROUTE_ADDRESS;
+    xi_route_addresses.runner_a_route_address = IH_RUNNER_A_ROUTE_ADDRESS;
+    xi_route_addresses.runner_b_route_address = IH_RUNNER_B_ROUTE_ADDRESS;
+
+    fi_bl_drv_ih_set_route_addresses(&xi_route_addresses);
+
+    /* logical ports configuration */
+    logical_ports_config.eth0_config.parsing_layer_depth        = IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH0_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE;
+    logical_ports_config.eth0_config.proprietary_tag_size       = DRV_IH_PROPRIETARY_TAG_SIZE_0;
+
+    logical_ports_config.eth1_config.parsing_layer_depth        = IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH1_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE;
+#if defined(__UBOOT__)
+    logical_ports_config.eth1_config.proprietary_tag_size       = DRV_IH_PROPRIETARY_TAG_SIZE_0;
+#else
+    logical_ports_config.eth1_config.proprietary_tag_size       = DRV_IH_PROPRIETARY_TAG_SIZE_4;
+#endif
+
+    logical_ports_config.gpon_config.parsing_layer_depth        = IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_GPON_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE;
+    logical_ports_config.gpon_config.proprietary_tag_size       = DRV_IH_PROPRIETARY_TAG_SIZE_0;
+
+    logical_ports_config.eth2_config.parsing_layer_depth 		= 0;
+    logical_ports_config.eth2_config.proprietary_tag_size 		= 0;
+
+    logical_ports_config.eth3_config.parsing_layer_depth 		= 0;
+    logical_ports_config.eth3_config.proprietary_tag_size 		= 0;
+
+    logical_ports_config.eth4_config.parsing_layer_depth 		= 0;
+    logical_ports_config.eth4_config.proprietary_tag_size 		= 0;
+
+    logical_ports_config.runner_a_config.parsing_layer_depth    = IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RNRA_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE;
+    logical_ports_config.runner_a_config.proprietary_tag_size   = DRV_IH_PROPRIETARY_TAG_SIZE_0;
+
+    logical_ports_config.runner_b_config.parsing_layer_depth    = IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RNRB_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE;
+    logical_ports_config.runner_b_config.proprietary_tag_size   = DRV_IH_PROPRIETARY_TAG_SIZE_0;
+
+    logical_ports_config.pcie0_config.parsing_layer_depth 		= IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_PCIE0_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE;
+    logical_ports_config.pcie0_config.proprietary_tag_size 		= DRV_IH_PROPRIETARY_TAG_SIZE_0;
+
+    logical_ports_config.pcie1_config.parsing_layer_depth 		= IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_PCIE1_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE;
+    logical_ports_config.pcie1_config.proprietary_tag_size 		= DRV_IH_PROPRIETARY_TAG_SIZE_0;
+
+    fi_bl_drv_ih_set_logical_ports_configuration(&logical_ports_config);
+
+    /* source port to ingress queue mapping */
+    source_port_to_ingress_queue_mapping.eth0_ingress_queue     = IH_INGRESS_QUEUE_0_ETH0;
+    source_port_to_ingress_queue_mapping.eth1_ingress_queue     = IH_INGRESS_QUEUE_1_ETH1;
+    source_port_to_ingress_queue_mapping.gpon_ingress_queue     = IH_INGRESS_QUEUE_5_DSL;
+    source_port_to_ingress_queue_mapping.runner_a_ingress_queue = IH_INGRESS_QUEUE_6_RUNNER_A;
+    source_port_to_ingress_queue_mapping.runner_b_ingress_queue = IH_INGRESS_QUEUE_7_RUNNER_B;
+
+    fi_bl_drv_ih_set_source_port_to_ingress_queue_mapping(&source_port_to_ingress_queue_mapping);
+
+    /* ingress queues configuration */
+    fi_ih_configure_ingress_queues();
+
+    /* configure wan ports */
+    wan_ports_config.eth0 = 1;
+    wan_ports_config.eth1 = 0;
+    wan_ports_config.eth2 = 0;
+    wan_ports_config.eth3 = 0;
+    wan_ports_config.eth4 = 0;
+    wan_ports_config.gpon = 1; /* DSL */
+    wan_ports_config.runner_a = 0;
+    wan_ports_config.runner_b = 0;
+    wan_ports_config.pcie0 = 0;
+    wan_ports_config.pcie1 = 0;
+
+    fi_bl_drv_ih_configure_wan_ports(&wan_ports_config);
+
+    f_ih_configure_lookup_tables();
+
+    f_ih_configure_classes();
+
+    f_ih_configure_target_matrix();
+
+    f_ih_configure_parser();
+}
+
+
+static void f_initialize_basic_runner_parameters(void)
+{
+    BL_LILAC_RDD_ERROR_DTE rdd_error;
+    uint32_t    i,j;
+
+    /* Default configuration of all RDD reasons to CPU_RX_QUEUE_ID_0 */
+    for (i = 0; i < rdpa_cpu_reason__num_of; i++)
+    {
+        rdd_error = rdd_cpu_reason_to_cpu_rx_queue(i, 0, rdpa_dir_ds, 0);
+
+        rdd_error |= rdd_cpu_reason_to_cpu_rx_queue(i, 0, rdpa_dir_us, 0);
+    }
+
+    /* Initialize Ethernet priority queues */
+    for (i = 0; i < 8; i++)
+    {
+        for (j = BL_LILAC_RDD_EMAC_ID_0; j < BL_LILAC_RDD_EMAC_ID_7; j++)
+        {
+            /* Configure queue size in RDD */
+            rdd_error |= rdd_eth_tx_queue_config(j, i, CS_RDD_ETH_TX_QUEUE_PACKET_THRESHOLD,0,INVALID_COUNTER_ID);
+        }
+    }
+}
+
+static void f_configure_runner(S_DPI_CFG  *pCfg, rdp_bpm_cfg_params *p_bpm_cfg_params)
+{
+    /* Local Variables */
+    RDD_INIT_PARAMS rdd_init_params ;
+
+    /* zero Runner memories (data, program and context) */
+    rdd_init();
+
+    rdd_load_microcode((uint8_t*) NULL,
+            (uint8_t*) firmware_binary_B, (uint8_t*) firmware_binary_C,
+            (uint8_t*) firmware_binary_D);
+
+    rdd_load_prediction((uint8_t*) NULL,
+            (uint8_t*) firmware_predict_B, (uint8_t*) firmware_predict_C,
+            (uint8_t*) firmware_predict_D);
+
+    /* Add basic offset when pass the addresses to RDD */
+    rdd_init_params.ddr_pool_ptr       = (uint8_t *) pCfg->runner_tm_base_addr;
+    rdd_init_params.ddr_pool_ptr_phys  = (uint32_t) pCfg->runner_tm_base_addr_phys;
+    rdd_init_params.extra_ddr_pool_ptr = (uint8_t *) pCfg->runner_mc_base_addr;
+    rdd_init_params.extra_ddr_pool_ptr_phys = (uint32_t) pCfg->runner_mc_base_addr_phys;
+    /* ddr_runner_table only needs to be 512KB aligned, but we make 1 MB anyway */
+    rdd_init_params.ddr_runner_tables_ptr = (uint8_t *) ROUND_UP_MB(pCfg->runner_tm_base_addr +
+        (p_bpm_cfg_params->bpm_def_thresh * rdp_bpm_buf_size()));
+    rdd_init_params.ddr_runner_tables_ptr_phys = RDD_RSV_VIRT_TO_PHYS(pCfg->runner_tm_base_addr, 
+        pCfg->runner_tm_base_addr_phys, rdd_init_params.ddr_runner_tables_ptr);
+    rdd_init_params.mac_table_size     = BL_LILAC_RDD_MAC_TABLE_SIZE_64;
+    /* we don't have iptv table. the following is just a dummy */
+    rdd_init_params.iptv_table_size    = BL_LILAC_RDD_MAC_TABLE_SIZE_256;
+    rdd_init_params.ddr_headroom_size  = pCfg->headroom_size;
+    /* XXX: Temporary, take this from global_system */
+#ifdef __UBOOT__
+    rdd_init_params.broadcom_switch_mode = 0; /* unmanaged */
+#else
+    rdd_init_params.broadcom_switch_mode = 1; /* managed */
+#endif
+    rdd_init_params.broadcom_switch_physical_port = BL_LILAC_RDD_LAN1_BRIDGE_PORT;
+
+    /* ip class operational mode*/
+    rdd_init_params.bridge_flow_cache_mode = 0;
+
+    /* The chip revision A0/B0 refers to BCM6838.  The BCM63138A0 handles Runner semaphores
+     * like BCM6838A0. The BCM63148 and BCM63138B0 handle Runner semaphores like BCM6838B0.
+     */
+    rdd_init_params.chip_revision = RDD_CHIP_REVISION_B0;
+    rdd_init_params.cpu_tx_abs_packet_limit = RDD_CPU_TX_ABS_FIFO_SIZE;
+    rdd_init_params.lp_mode = pCfg->runner_lp;
+    rdd_data_structures_init(&rdd_init_params);
+
+}
+
+void f_basic_bpm_sp_enable(void)
+{
+    BPM_MODULE_REGS_BPM_SP_EN bpm_sp_enable;
+
+    BPM_MODULE_REGS_BPM_SP_EN_READ( bpm_sp_enable);
+
+    bpm_sp_enable.rnra_en = 1;
+    bpm_sp_enable.rnrb_en = 1;
+    bpm_sp_enable.gpon_en = 0;
+    bpm_sp_enable.emac0_en = 1;
+    bpm_sp_enable.emac1_en = 1;
+
+
+    BPM_MODULE_REGS_BPM_SP_EN_WRITE( bpm_sp_enable);
+
+}
+void f_basic_sbpm_sp_enable(void)
+{
+    DRV_SBPM_SP_ENABLE sbpm_sp_enable = { 0 };
+
+    sbpm_sp_enable.rnra_sp_enable = 1;
+    sbpm_sp_enable.rnrb_sp_enable = 1;
+    sbpm_sp_enable.eth0_sp_enable = 1;
+    sbpm_sp_enable.eth1_sp_enable = 1;
+    sbpm_sp_enable.eth2_sp_enable = 0;
+    sbpm_sp_enable.eth3_sp_enable = 0;
+    sbpm_sp_enable.eth4_sp_enable = 0;
+
+    fi_bl_drv_sbpm_sp_enable(&sbpm_sp_enable);
+}
+
+uint32_t data_path_init( S_DPI_CFG  *pCfg)
+{
+    uint32_t            error        = DPI_RC_OK;
+    uint32_t            rnrFreq      = DEFAULT_RUNNER_FREQ;
+
+    DRV_BBH_PORT_INDEX  macIter;
+    rdp_bpm_cfg_params   bpm_cfg_params;
+
+
+    /* Point to default configuration if none is passed to init */
+    pDpiCfg = !pCfg ? &DpiBasicConfig : pCfg;
+
+    /*init dma arrays*/
+    f_initialize_bbh_dma_sdma_related_arrays();
+
+    if (rdp_bpm_cfg_params_get(pCfg, &bpm_cfg_params)) {
+        __print("FAILED TO INITIALIZE RDP DUE TO RESERVE MEMORY NOT ENOUGH\n");
+        return DPI_RC_ERROR;
+    }
+
+    /*init runner,load microcode and structures*/
+    f_configure_runner(pCfg, &bpm_cfg_params);
+
+    /*set runner frequency*/
+    if (pDpiCfg->runner_freq == 0)
+    {
+        rnrFreq = DEFAULT_RUNNER_FREQ;
+    }
+    else
+    {
+        rnrFreq = pDpiCfg->runner_freq;
+    }
+
+    rdd_runner_frequency_set(rnrFreq);
+        
+    /*configure IH*/
+    f_ih_init();
+
+    /*init SBPM*/
+    sbpm_drv_init();
+
+    /*init BPM*/
+    bpm_drv_init(pCfg, &bpm_cfg_params);
+
+    /*init BBH of emac ports*/
+    for ( macIter =  DRV_BBH_EMAC_0; macIter <= DRV_BBH_EMAC_1; macIter++)
+    {
+        f_initialize_bbh_of_emac_port(macIter);
+    }
+    /*init DMA and SDMA*/
+    f_initialize_dma_sdma();
+
+    /*configure basic runner parameters*/
+    f_initialize_basic_runner_parameters();
+
+    if ( error == DPI_RC_OK )
+    {
+        initDone = 1;
+    }
+    return error;
+
+}
+
+uint32_t data_path_go(void)
+{
+    if ( initDone != 1 )
+    {
+        __print("Data Path init didn't finished \n");
+        return DPI_RC_ERROR;
+    }
+
+    /*enable runner*/
+    rdd_runner_enable();
+
+    /*enable the source ports in bpm/sbpm in case of basic config*/
+    f_basic_bpm_sp_enable();
+    f_basic_sbpm_sp_enable();
+
+    return DPI_RC_OK;
+}
+uint32_t data_path_shutdown(void)
+{
+    return DPI_RC_OK;
+}
diff --git a/arch/arm/mach-bcmbca/rdp/data_path_init.h b/arch/arm/mach-bcmbca/rdp/data_path_init.h
new file mode 100755
index 0000000000..36e41c2945
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/data_path_init.h
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the definitions for Broadcom's 6838 Data path           */
+/* initialization sequence                                                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+#ifndef __BCM63138_DATA_PATH_INIT_H
+#define __BCM63138_DATA_PATH_INIT_H
+
+typedef enum
+{
+    WAN_TYPE_NONE = 0,
+    WAN_TYPE_RGMII = 1,
+    WAN_TYPE_DSL = 5
+}E_WAN_TYPE;
+
+
+typedef enum
+{
+    DPI_RC_OK,
+    DPI_RC_ERROR
+}E_DPI_RC;
+
+
+typedef struct
+{
+    uint32_t mtu_size;
+    uint32_t headroom_size;
+    uint32_t runner_freq;
+    uint32_t runner_tm_base_addr;
+    uint32_t runner_tm_base_addr_phys;
+    uint32_t runner_tm_size;
+    uint32_t runner_mc_base_addr;
+    uint32_t runner_mc_base_addr_phys;
+    uint32_t runner_mc_size;
+    uint32_t runner_lp;
+} S_DPI_CFG;
+
+uint32_t data_path_init(S_DPI_CFG *pCfg);
+uint32_t data_path_go(void);
+uint32_t data_path_shutdown(void);
+void f_configure_bridge_port_sa_da(void);
+void reset_unreset_rdp_block(void);
+
+
+#endif //#define __BCM63138_DATA_PATH_INIT_H
diff --git a/arch/arm/mach-bcmbca/rdp/hwapi_mac.h b/arch/arm/mach-bcmbca/rdp/hwapi_mac.h
new file mode 100755
index 0000000000..3ef4bf7a7e
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/hwapi_mac.h
@@ -0,0 +1,1017 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2013 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This header file defines all datatypes and functions exported for the      */
+/* Ethernet MAC		                                                          */
+/*                                                                            */
+/******************************************************************************/
+
+
+#ifndef __UNIFIED_DRV_MAC_H
+#define __UNIFIED_DRV_MAC_H
+
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+#if !defined(CONFIG_BCM47622)
+#include "rdpa_types.h"
+#else //47622 - does not have runner, just include necessary definitions
+
+#define rdpa_emac   int
+
+/** EMAC rates */
+typedef enum
+{
+    rdpa_emac_rate_10m,     /**< 10 Mbps */
+    rdpa_emac_rate_100m,    /**< 100 Mbps */
+    rdpa_emac_rate_1g,      /**< 1 Gbps */
+    rdpa_emac_rate_2_5g,    /**< 2.5 Gbps */
+
+    rdpa_emac_rate__num_of, /* Number of rates */
+} rdpa_emac_rate;
+
+/** EMAC configuration */
+typedef struct
+{
+    char loopback;      /**< 1 = line loopback */
+    rdpa_emac_rate rate;       /**< EMAC rate */
+    char generate_crc;  /**< 1 = generate CRC */
+    char full_duplex;   /**< 1 = full duplex */
+    char pad_short;     /**< 1 = pad short frames */
+    char allow_too_long;/**< 1 = allow long frames */
+    char check_length;  /**< 1 = check frame length */
+    uint32_t preamble_length;   /**< Preamble length */
+    uint32_t back2back_gap;     /**< Back2Back inter-packet gap */
+    uint32_t non_back2back_gap; /**< Non Back2Back inter-packet gap */
+    uint32_t min_interframe_gap; /**< Min inter-frame gap */
+    char rx_flow_control;/**< 1 = enable RX flow control */
+    char tx_flow_control;/**< 1 = enable TX flow control */
+} rdpa_emac_cfg_t;
+
+/** RX RMON counters.
+ * Underlying type for emac_rx_stat aggregate type.
+ */
+typedef struct
+{
+    uint32_t byte;              /**< Receive Byte Counter */
+    uint32_t packet;            /**< Receive Packet Counter */
+    uint32_t frame_64;          /**< Receive 64 Byte Frame Counter */
+    uint32_t frame_65_127;      /**< Receive 65 to 127 Byte Frame Counter */
+    uint32_t frame_128_255;     /**< Receive 128 to 255 Byte Frame Counter */
+    uint32_t frame_256_511;     /**< Receive 256 to 511 Byte Frame Counter */
+    uint32_t frame_512_1023;    /**< Receive 512 to 1023 Byte Frame Counter */
+    uint32_t frame_1024_1518;   /**< Receive 1024 to 1518 Byte Frame Counter */
+    uint32_t frame_1519_mtu;    /**< Receive 1519 to MTU Frame Counter */
+    uint32_t multicast_packet;  /**< Receive Multicast Packet */
+    uint32_t broadcast_packet;  /**< Receive Broadcast Packet */
+    uint32_t unicast_packet;    /**< Receive Unicast Packet */
+    uint32_t alignment_error;   /**< Receive Alignment error */
+    uint32_t frame_length_error;/**< Receive Frame Length Error Counter */
+    uint32_t code_error;        /**< Receive Code Error Counter */
+    uint32_t carrier_sense_error;/**< Receive Carrier sense error */
+    uint32_t fcs_error;         /**< Receive FCS Error Counter */
+    uint32_t control_frame;     /**< Receive Control Frame Counter */
+    uint32_t pause_control_frame;/**< Receive Pause Control Frame */
+    uint32_t unknown_opcode;    /**< Receive Unknown opcode */
+    uint32_t undersize_packet;  /**< Receive Undersize Packet */
+    uint32_t oversize_packet;   /**< Receive Oversize Packet */
+    uint32_t fragments;         /**< Receive Fragments */
+    uint32_t jabber;            /**< Receive Jabber counter */
+    uint32_t overflow;          /**< Receive Overflow counter */
+} rdpa_emac_rx_stat_t;
+
+/** Tx RMON counters.
+ * Underlying type for emac_tx_stat aggregate type.
+ */
+typedef struct
+{
+    uint32_t byte;              /**< Transmit Byte Counter */
+    uint32_t packet;            /**< Transmit Packet Counter */
+    uint32_t frame_64;          /**< Transmit 64 Byte Frame Counter */
+    uint32_t frame_65_127;      /**< Transmit 65 to 127 Byte Frame Counter */
+    uint32_t frame_128_255;     /**< Transmit 128 to 255 Byte Frame Counter */
+    uint32_t frame_256_511;     /**< Transmit 256 to 511 Byte Frame Counter */
+    uint32_t frame_512_1023;    /**< Transmit 512 to 1023 Byte Frame Counter */
+    uint32_t frame_1024_1518;   /**< Transmit 1024 to 1518 Byte Frame Counter */
+    uint32_t frame_1519_mtu;    /**< Transmit 1519 to MTU Frame Counter */
+    uint32_t fcs_error;         /**< Transmit FCS Error */
+    uint32_t multicast_packet;  /**< Transmit Multicast Packet */
+    uint32_t broadcast_packet;  /**< Transmit Broadcast Packet */
+    uint32_t unicast_packet;    /**< Transmit Unicast Packet */
+    uint32_t excessive_collision; /**< Transmit Excessive collision counter */
+    uint32_t late_collision;    /**< Transmit Late collision counter */
+    uint32_t single_collision;  /**< Transmit Single collision frame counter */
+    uint32_t multiple_collision;/**< Transmit Multiple collision frame counter */
+    uint32_t total_collision;   /**< Transmit Total Collision Counter */
+    uint32_t pause_control_frame; /**< Transmit PAUSE Control Frame */
+    uint32_t deferral_packet;   /**< Transmit Deferral Packet */
+    uint32_t excessive_deferral_packet; /**< Transmit Excessive Deferral Packet */
+    uint32_t jabber_frame;      /**< Transmit Jabber Frame */
+    uint32_t control_frame;     /**< Transmit Control Frame */
+    uint32_t oversize_frame;    /**< Transmit Oversize Frame counter */
+    uint32_t undersize_frame;   /**< Transmit Undersize Frame */
+    uint32_t fragments_frame;   /**< Transmit Fragments Frame counter */
+    uint32_t error;             /**< Transmission errors*/
+    uint32_t underrun;          /**< Transmission underrun */
+} rdpa_emac_tx_stat_t;
+
+/** Emac statistics */
+typedef struct
+{
+    rdpa_emac_rx_stat_t rx; /**< Emac Receive Statistics */
+    rdpa_emac_tx_stat_t tx; /**< Emac Transmit Statistics */
+} rdpa_emac_stat_t;
+
+/** Ethernet address */
+typedef struct {
+    uint8_t b[6];  /**< Address bytes */
+} bdmf_mac_t;
+
+#endif //47622
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+
+typedef struct
+{
+	int32_t rxFlowEnable;
+	int32_t txFlowEnable;
+}S_MAC_HWAPI_FLOW_CTRL;
+
+typedef enum
+{
+	MAC_LPBK_NONE,
+	MAC_LPBK_LOCAL,
+	MAC_LPBK_REMOTE,
+	MAC_LPBK_BOTH
+}MAC_LPBK;
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	uint32_t    reserved:26;// Reserved bits must be written with 0.  A read returns an unknown value.
+	uint32_t    mac_link_stat:1;// Link status indication.Reset value is 0x0.
+	uint32_t    mac_tx_pause:1;// 1: MAC Tx pause enabled. 0: MAC Tx pause disabled. Reset value is 0x1.
+	uint32_t	mac_rx_pause:1;// 1: MAC Rx pause enabled. 0: MAC Rx pause disabled.	Reset value is 0x1.
+	uint32_t	mac_duplex:1;//1: Half duplex. 0: Full duplex. Reset value is 0x0.
+	uint32_t	mac_speed:2;// 00: 10Mbps, 01: 100Mbps, 10: 1Gbps, 11: 2.5Gbps	Reset value is 0x2.
+
+}S_HWAPI_MAC_STATUS;
+#else
+typedef struct
+{
+	uint32_t	mac_speed:2;// 00: 10Mbps, 01: 100Mbps, 10: 1Gbps, 11: 2.5Gbps	Reset value is 0x2.
+	uint32_t	mac_duplex:1;//1: Half duplex. 0: Full duplex. Reset value is 0x0.
+	uint32_t	mac_rx_pause:1;// 1: MAC Rx pause enabled. 0: MAC Rx pause disabled.	Reset value is 0x1.
+	uint32_t    mac_tx_pause:1;// 1: MAC Tx pause enabled. 0: MAC Tx pause disabled. Reset value is 0x1.
+	uint32_t    mac_link_stat:1;// Link status indication.Reset value is 0x0.
+	uint32_t    reserved:26;// Reserved bits must be written with 0.  A read returns an unknown value.
+
+}S_HWAPI_MAC_STATUS;
+#endif
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_configuration                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get configuration                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   get the configuratin of a mac port	,note that current status of emac	  */
+/*   might be different than configuration when working in autoneg			  */
+/*	to get the current status use mac_hwapi_get_mac_status API				  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    emac_cfg -  structure holds the current configuration of the mac  port  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_configuration(rdpa_emac emacNum,rdpa_emac_cfg_t *emac_cfg);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_configuration                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set configuration                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   set the configuratin of a mac port                                       */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   emac_cfg -  structure holds the current configuration of the mac  port   */
+/*                                                                            */
+/* Output:                                                                    */
+/*      																	  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_configuration(rdpa_emac emacNum,rdpa_emac_cfg_t *emac_cfg);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_duplex		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port duplex                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the dulplex of a port												  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    full_duples  :  1 = full dulplex,0 = half_duplex						  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_duplex(rdpa_emac emacNum,int32_t *full_duplex);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_duplex		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port duplex                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the dulplex of a port												  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    full_duples  :  1 = full dulplex,0 = half_duplex						  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_duplex(rdpa_emac emacNum,int32_t full_duplex);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_speed		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port speed rate                                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the speed of a port													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                              							                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*      rate -   enum of the speed                                            */
+/******************************************************************************/
+void mac_hwapi_get_speed(rdpa_emac emacNum,rdpa_emac_rate *rate);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_speed		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port speed rate                                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the speed of a port													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*      rate -   enum of the speed   						                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                   							              */
+/******************************************************************************/
+
+void mac_hwapi_set_speed(rdpa_emac emacNum,rdpa_emac_rate rate);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_external_conf                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - en/disable external speed configuration                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set port speed external configuration				      				  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    enable - boolean enable                                                 */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                   							              */
+/******************************************************************************/
+
+void mac_hwapi_set_external_conf(rdpa_emac emacNum, int enable);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rxtx_enable                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx and rx enable                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get tx and rx enable													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                             								  */
+/*                                                                            */
+/* Output:                                                                    */
+/*       rxtxEnable  - boolean enable   	                                  */
+/******************************************************************************/
+void mac_hwapi_get_rxtx_enable(rdpa_emac emacNum,int32_t *rxEnable,int32_t *txEnable);
+
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_rxtx_enable                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx and rx enable                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set tx and rx enable													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    rxtxEnable  - boolean enable                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_rxtx_enable(rdpa_emac emacNum,int32_t rxEnable,int32_t txEnable);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_sw_reset		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port software reset                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the sw reset bit of emac port										  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    swReset  :  1 = reset,0 = not reset									  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_sw_reset(rdpa_emac emacNum,int32_t *swReset);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_sw_reset		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port software reset                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the sw reset bit of emac port										  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   swReset  :  1 = reset,0 = not reset	                                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*    								  										  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_sw_reset(rdpa_emac emacNum,int32_t swReset);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_min_pkt_size                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get tx minimum packet size                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*  Get the unimac configuration for minimum tx packet size                   */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    min_pkt_size  :  14...125                                               */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_min_pkt_size(rdpa_emac emacNum,int32_t *min_pkt_size);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_min_pkt_size                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx minimum packet size                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*  Set the unimac configuration for minimum tx packet size                   */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*   min_pkt_size  :  14...125                                                */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_min_pkt_size(rdpa_emac emacNum,int32_t min_pkt_size);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port TX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the port maximum transmit unit size in bytes						  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                              										      */
+/*                                                                            */
+/* Output:                                                                    */
+/*    maxTxFrameLen - size of frame in bytes 								  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_max_frame_len(rdpa_emac emacNum,uint32_t *maxTxFrameLen );
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port TX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the port maximum transmit unit size in bytes						  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    maxTxFrameLen - size of frame in bytes                         	      */
+/*                                                                            */
+/* Output:                                                                    */
+/*   																		  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_max_frame_len(rdpa_emac emacNum,uint32_t maxTxFrameLen );
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port RX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the port maximum receive unit size in bytes							  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                           	     										  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   maxRxFrameLen - size of current MRU									  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_rx_max_frame_len(rdpa_emac emacNum,uint32_t *maxRxFrameLen );
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_rx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port RX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the port maximum receive unit size in bytes							  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    maxRxFrameLen - size of current MRU        							  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   									  									  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_rx_max_frame_len(rdpa_emac emacNum,uint32_t maxRxFrameLen );
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_igp_len	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port inter frame gap                                 	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the inter frame gap	size in bytes									  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   txIpgLen - length in bytes                                               */
+/*                                                                            */
+/* Output:                                                                    */
+/*    																		  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_igp_len(rdpa_emac emacNum,uint32_t txIpgLen );
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_igp_len	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port inter frame gap                                 	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the inter frame gap	size in bytes									  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                      							          */
+/*                                                                            */
+/* Output:                                                                    */
+/*    txIpgLen - length in bytes    										  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_igp_len(rdpa_emac emacNum,uint32_t *txIpgLen );
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_mac_status	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port status                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the status of mac													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    macStatus  :  														  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_mac_status(rdpa_emac emacNum,S_HWAPI_MAC_STATUS *macStatus);
+
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_flow_control                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*           																  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   flowControl - structure with parameters of tx and rx flow control		  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_flow_control                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   flowControl - structure with parameters of tx and rx flow control        */
+/*                                                                            */
+/* Output:                                                                    */
+/*   						  												  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_pause_params                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   flowControl - structure with parameters of tx and rx flow control        */
+/*                                                                            */
+/* Output:                                                                    */
+/*   						  												  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_pause_params(rdpa_emac emacNum,int32_t pauseCtrlEnable,uint32_t pauseTimer,uint32_t pauseQuanta);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rx_counters	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	get the rx counters of port                           	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the rx counters of port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    rxCounters  :  structure filled with counters							  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_rx_counters(rdpa_emac emacNum,rdpa_emac_rx_stat_t *rxCounters);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_counters	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	get the tx counters of port                           	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the tx counters of port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    txCounters  :  structure filled with counters							  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_counters(rdpa_emac emacNum,rdpa_emac_tx_stat_t *txCounters);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_init_emac	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_init_emac(rdpa_emac emacNum);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_loopback	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_loopback(rdpa_emac emacNum,MAC_LPBK *loopback);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_loopback	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_loopback(rdpa_emac emacNum,MAC_LPBK loopback);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_modify_flow_control_pause_pkt_addr                             */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - Modify the Flow Control pause pkt source address            */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function modifies the flow control pause pkt source address         */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - EMAC id (0-5)                                                 */
+/*                                                                            */
+/*   mac - Flow Control mac address                                   */
+/*                                                                            */
+/* Output:   N/A                                                              */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_modify_flow_control_pause_pkt_addr ( rdpa_emac emacNum,
+    bdmf_mac_t mac);
+void mac_hwapi_set_unimac_cfg(rdpa_emac emacNum, int32_t enabled);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_backpressure_ext                                           */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set/reset backpressure to external switch                   */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set/reset backpressure to external switch                                 */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*   enable  - boolean enable                                                 */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_backpressure_ext(rdpa_emac emacNum, int32_t enable);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_eee                                                        */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set eee configuration                                       */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set eee configuration                                                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*   enable  - boolean enable                                                 */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_eee(rdpa_emac emacNum, int32_t enable);
+
+#endif
diff --git a/arch/arm/mach-bcmbca/rdp/packing.h b/arch/arm/mach-bcmbca/rdp/packing.h
new file mode 100755
index 0000000000..deaa86e5c4
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/packing.h
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2012 Broadcom
+ */
+/*
+*  
+*/
+
+#ifndef __PACKING_H_
+#define __PACKING_H_
+
+#define __PACKING_ATTRIBUTE_STRUCT_END__  __attribute__ ((packed))
+#define __PACKING_ATTRIBUTE_FIELD_LEVEL__ 
+
+#endif
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdd.h b/arch/arm/mach-bcmbca/rdp/rdd.h
new file mode 100755
index 0000000000..7b4a94c4c9
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd.h
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef _BL_LILAC_DRV_RUNNER_H
+#define _BL_LILAC_DRV_RUNNER_H
+
+#include "bl_os_wraper.h"
+#include "access_macros.h"
+
+
+#if defined(__UBOOT__)
+#include "bcm_mm.h"
+#define RDP_CPU_RING_MAX_QUEUES         1
+#define RDP_WLAN_MAX_QUEUES             0
+
+#elif defined(__KERNEL__)
+#include "bcm_mm.h"
+#define PHYS_TO_VIRT(_addr)             PHYS_TO_CACHED(_addr)
+#define RDP_CPU_RING_MAX_QUEUES         RDPA_CPU_MAX_QUEUES
+#define RDP_WLAN_MAX_QUEUES             RDPA_WLAN_MAX_QUEUES
+
+#else
+#define VIRT_TO_PHYS(_addr)             ((uint32_t)_addr)
+#define PHYS_TO_VIRT(_addr)             (_addr)
+#endif
+
+#define RDD_VIRT_TO_PHYS(_addr) VIRT_TO_PHYS(_addr)
+#define RDD_PHYS_TO_VIRT(_addr) PHYS_TO_VIRT(_addr)
+
+#if defined(__UBOOT__)
+#define RDD_RSV_VIRT_TO_PHYS(_vbase, _pbase, _addr) RDD_VIRT_TO_PHYS(_addr)
+#define RDD_RSV_PHYS_TO_VIRT(_vbase, _pbase, _addr) RDD_PHYS_TO_VIRT(_addr)
+#elif defined(__KERNEL__)
+#include "bcm_rsvmem.h"
+#define RDD_RSV_VIRT_TO_PHYS(_vbase, _pbase, _addr) BcmMemReserveVirtToPhys(_vbase, _pbase, _addr)
+#define RDD_RSV_PHYS_TO_VIRT(_vbase, _pbase, _addr) BcmMemReservePhysToVirt(_vbase, _pbase, _addr)
+#else
+#define RDD_RSV_VIRT_TO_PHYS(_vbase, _pbase, _addr) RDD_VIRT_TO_PHYS(_addr)
+#define RDD_RSV_PHYS_TO_VIRT(_vbase, _pbase, _addr) RDD_PHYS_TO_VIRT(_addr)
+#endif
+
+
+#ifndef __PACKING_ATTRIBUTE_STRUCT_END__
+#include "packing.h"
+#endif
+
+#include "rdp_runner.h"
+#include "rdpa_types.h"
+
+#include "rdp_drv_bpm.h"
+
+/* temporary until complete stratosphere removal */
+#define bdmf_fastlock int
+#define DEFINE_BDMF_FASTLOCK(lock) int lock = 0
+#define bdmf_fastlock_lock(_lock)       (*_lock = 0)
+#define bdmf_fastlock_unlock(_lock)     (*_lock = 0)
+#define bdmf_fastlock_lock_irq(_lock, _flag)   (_flag = *_lock)
+#define bdmf_fastlock_unlock_irq(_lock, _flag) (*_lock = _flag)
+
+#if !defined(BDMF_SYSTEM_SIM)
+#define rdd_print(fmt, args...) printk(fmt, ##args)
+#else
+#define rdd_print(fmt, args...) printf(fmt, ##args)
+#endif
+
+/* task addresses labels from fw compilation */
+#include "rdd_runner_a_labels.h"
+#include "rdd_runner_b_labels.h"
+#include "rdd_runner_c_labels.h"
+#include "rdd_runner_d_labels.h"
+
+#include "rdd_defs.h"
+#include "rdd_runner_defs_auto.h"
+#include "rdd_runner_defs.h"
+#include "rdd_data_structures_auto.h"
+#include "rdd_data_structures.h"
+#include "rdd_common.h"
+#include "rdd_cpu.h"
+#include "rdd_init.h"
+#include "rdd_lookup_engine.h"
+#include "rdd_tm.h"
+#include "rdd_platform.h"
+
+/* priority range according to classification type : acl 128-191, flow 64-127, qos 0-63, ip_flow 192-255  */
+#define RDPA_QOS_PRTY_OFFSET 0
+#define RDPA_FLOW_PRTY_OFFSET 64
+#define RDPA_ACL_PRTY_OFFSET 128
+#define RDPA_IP_FLOW_PRTY_OFFSET 192
+
+#endif /* _BL_LILAC_DRV_RUNNER_H */
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_common.c b/arch/arm/mach-bcmbca/rdp/rdd_common.c
new file mode 100755
index 0000000000..b0c018867e
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_common.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#include "rdd.h"
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Global Variables                                */
+/*                                                                            */
+/******************************************************************************/
+
+int                                g_dbg_lvl;
+RDD_FC_MCAST_CONNECTION2_TABLE_DTS *g_fc_mcast_connection2_table_ptr;
+#if defined(DSL_63138) || defined(DSL_63148)
+RDD_CONNECTION_TABLE_DTS    *g_ds_connection_table_ptr;
+#endif
+
+uint8_t*  g_runner_ddr_base_addr;
+uint32_t  g_runner_ddr_base_addr_phys;
+uint8_t*  g_runner_tables_ptr;
+uint8_t*  g_runner_extra_ddr_base_addr;
+uint32_t  g_runner_extra_ddr_base_addr_phys;
+uint32_t  g_ddr_headroom_size;
+uint8_t   g_broadcom_switch_mode = 0;
+uint32_t  g_bridge_flow_cache_mode;
+uint32_t  g_cpu_tx_queue_write_ptr[ 4 ];
+uint32_t  g_cpu_tx_queue_abs_data_ptr_write_ptr[ 4 ];
+uint32_t  g_rate_controllers_pool_idx;
+uint32_t  g_chip_revision;
+uint8_t   g_lookup_port_init_mapping_table[16];
+
+RDD_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTE  g_ingress_classification_rule_cfg_table[ 2 ];
+RDD_WAN_TX_POINTERS_TABLE_DTS                  *wan_tx_pointers_table_ptr;
+BL_LILAC_RDD_BRIDGE_PORT_DTE                   g_broadcom_switch_physical_port = 0;
+uint32_t  g_cpu_tx_abs_packet_limit = 0;
+uint16_t  *g_free_skb_indexes_fifo_table = NULL;
+uint8_t **g_cpu_tx_skb_pointers_reference_array = NULL;
+uint8_t *g_dhd_tx_cpu_usage_reference_array = NULL;
+rdd_phys_addr_t *g_cpu_tx_data_pointers_reference_array = NULL;
+rdd_phys_addr_t g_free_skb_indexes_fifo_table_physical_address = 0;
+rdd_phys_addr_t g_free_skb_indexes_fifo_table_physical_address_last_idx = 0;
+
+DEFINE_BDMF_FASTLOCK( int_lock );
+DEFINE_BDMF_FASTLOCK( int_lock_irq );
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_common.h b/arch/arm/mach-bcmbca/rdp/rdd_common.h
new file mode 100755
index 0000000000..9176e30d5c
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_common.h
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+   
+*/
+
+#ifndef _BL_LILAC_DRV_RUNNER_COMMON_H
+#define _BL_LILAC_DRV_RUNNER_COMMON_H
+
+#include "rdd_data_structures.h"
+#if !defined(FIRMWARE_INIT)
+#include "rdp_drv_bpm.h"
+#endif /* !defined(FIRMWARE_INIT) */
+
+typedef struct {
+    uint32_t write;
+    uint32_t read;
+    uint32_t count;
+    uint16_t *data;
+} cpu_tx_skb_free_indexes_cache_t;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_smart_card_global_params_config                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*  Smart card                                                                */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets the global timing parameters that should apply on     */
+/*  transactions from now on                        		              */
+/*                                                                            */
+/*                                                                            */
+/* Input:                                                                     */
+/*   xi_waiting_time - The maximum delay between the leading edge of a        */
+/* 	 	character transmitted by the card and the leading edge of the */
+/* 	    previous character  					      */
+/* 	 xi_guard_time	-  The minimum delay between the leading edges of     */
+/* 		 two consecutive characters                                   */
+/*   xi_etu	-  elementary time unit , in which one bit is transffered     */
+/*                                                                            */
+/* Output:                                                                    */
+/*     BL_LILAC_RDD_ERROR_DTE - Return status                                 */
+/*     		BL_LILAC_RDD_OK - No error                                    */
+/*                                                                            */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_smart_card_global_params_config ( uint32_t  xi_waiting_time,
+                                                             uint8_t   xi_guard_time,
+                                                             uint8_t   xi_etu,
+                                                             uint8_t   xi_max_retransmit );
+
+
+/************************************************************************************/
+/*                                                                                  */
+/* Name:  rdd_smart_card_command_params_config                                      */                           
+/*                                                                       	    */
+/* Title:                                                                           */
+/*                                                                                  */
+/*  Smart card                                                                      */
+/*                                                                                  */
+/* Abstract:                                                                        */
+/* 		This function sets the parameters of the wanted transaction         */
+/*		and starts it.							    */
+/* Input:  									    */
+/*		*xi_header_arr  - array of 5 bytes containing the header            */
+/*		*xi_data_arr	- data array to send                                */
+/*		xi_send_len   	- number of bytes to be send to the smart card.     */
+/*		  		  Only for PPS and NORMAL task types .		    */
+/*		xi_receive_len   - number of bytes to be recieved to/from the       */
+/*			           smart card. Ignored for not NORMAL task type     */
+/*		xi_task_type -  TX_TASK / RX_TASK / PPS / ANSWER_TO_RESET / NORMAL  */
+/*										    */
+/*		TX_TASK:                                                            */
+/*			Sending header and data to the card .                       */
+/*                                                                                  */
+/*		RX_TASK:                                                            */
+/*			Sending header and receiving data from the card.            */
+/*                                                                                  */
+/*      PPS :                                                                       */
+/*			The pps message is contained in xi_data array.              */
+/*			xi_send_len   is the length of pps message.                 */
+/*			xi_header      will be ignored.                             */
+/*                                                                                  */
+/*		RESET:                                                              */
+/* 			receive and parse (calculating the size) of ANSWER_TO_RESET */
+/* 			PDU initiated after cold/warm reset  of smart card.         */
+/*		 	Note: xi_data_len, xi_header, xi_data are ignored           */
+/*	                                                                            */
+/*      NORMAL : sending xi_send_len bytes  and receiving xi_receive_len  bytes .   */
+/*		        (used mainly for debugging)		                    */
+/* 		Output:                                                             */
+/*     		BL_LILAC_RDD_OK                                                     */
+/*                                                                                  */
+/************************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_smart_card_command_params_config ( uint8_t   xi_task_type,
+                                                              uint16_t  xi_send_length,
+                                                              uint16_t  xi_receive_length,
+                                                              uint8_t   *xi_header_array,
+                                                              uint8_t   *xi_data_array );
+
+
+/************************************************************************************/
+/*                                                                                  */
+/* Name: 	 rdd_smart_card_command_params_read                                 */
+/*                                                                                  */
+/* Title:    Smart card                                                             */
+/*                                                                            	    */
+/* Abstract:                                                                        */
+/*		This function reads  the bytes received from smart card.            */
+/*       Use after transaction is completed.                                        */
+/*                   					                            */
+/*	Input:       	                                                            */
+/*		*xi_send_len   - ptr to number of bytes that was sent               */
+/*		*xi_recieve_len  -  ptr to number of bytes that was received	    */
+/*              *xi_data_arr  - data array  of received bytes with length           */
+/*                xi_recieve_len                                                    */
+/*      *status_byte  - status of the transaction when it was ended (success/error) */
+/*		                                                                    */
+/*	Output:                                                                     */
+/*    	BL_LILAC_RDD_OK                                                             */
+/*                                                                                  */
+/************************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_smart_card_command_params_read ( uint16_t  *xo_send_length,
+                                                            uint16_t  *xo_receive_length,
+                                                            uint8_t   *xo_data_array,
+                                                            uint8_t   *status_byte,
+                                                            uint32_t  *xo_send_error_counter,
+                                                            uint32_t  *xo_recv_error_counter );
+
+
+/************************************************************************************/
+/*                                                                                  */
+/*  Name: 	 rdd_smart_card_status_get                                          */
+/*                                                                                  */
+/* Title:    Smart card                                                             */
+/*                                                                                  */
+/* Abstract:                                                                        */
+/*		This function reads  status from smart card.                        */
+/*                   					                            */
+/*	Input:       	                                                            */
+/*		none                                                                */
+/*		                                                                    */
+/*	Output:                                                                     */
+/*    	BL_LILAC_RDD_OK                                                             */
+/*                                                                                  */
+/************************************************************************************/
+BL_LILAC_RDD_ERROR_DTE  rdd_smart_card_status_get ( uint8_t  *xo_smart_card_status );
+
+
+/************************************************************************************/
+/*                                                                                  */
+/* Name:  rdd_smart_card_task_start                                                 */                 
+/*                                                                                  */
+/* Title:    Smart card                                                             */
+/*                                                                            	    */
+/* Abstract:                                                                        */
+/* 		This function send wakeup to smart card task                        */
+/*		and starts it.						            */
+/*                                                                                  */
+/* Input:                                                                           */
+/*		none		        				     	    */
+/*                                                                                  */
+/* 	Output:                                                                     */
+/*     		BL_LILAC_RDD_OK                                                     */
+/*                                                                                  */
+/************************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_smart_card_task_start ( void );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_critical_section_config                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - RDD lock mechanism                                     */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* This function initializes pointers to critical section callback functions  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*     xi_lock_function - pointer to critical section begin function          */
+/*     xi_unlock_function - pointer to critical section exit function         */
+/*     xi_lock_irq_function - pointer to critical section within IRQ begin    */
+/*                            function                                        */
+/*     xi_unlock_irq_function - pointer to critical section exit within IRQ   */
+/*                            function                                        */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_critical_section_config ( BL_LILAC_RDD_LOCK_CRITICAL_SECTION_FP_DTE        xi_lock_function,
+                                                     BL_LILAC_RDD_UNLOCK_CRITICAL_SECTION_FP_DTE      xi_unlock_function,
+                                                     BL_LILAC_RDD_LOCK_CRITICAL_SECTION_FP_IRQ_DTE    xi_lock_irq_function,
+                                                     BL_LILAC_RDD_UNLOCK_CRITICAL_SECTION_FP_IRQ_DTE  xi_unlock_irq_function );
+
+
+
+/* INTERNAL COMMON FUNCTIONS */
+
+static inline BL_LILAC_RDD_BRIDGE_PORT_DTE rdd_bridge_port_vector_to_bridge_port ( BL_LILAC_RDD_BRIDGE_PORT_VECTOR_DTE  xi_bridge_port_vector )
+{
+    BL_LILAC_RDD_BRIDGE_PORT_DTE  bridge_port;
+
+    switch ( xi_bridge_port_vector ) 
+    {
+    case BL_LILAC_RDD_BRIDGE_PORT_VECTOR_PCI:
+        bridge_port = BL_LILAC_RDD_PCI_BRIDGE_PORT;
+        break;
+
+    case BL_LILAC_RDD_BRIDGE_PORT_VECTOR_LAN0:
+        bridge_port = BL_LILAC_RDD_LAN0_BRIDGE_PORT;
+        break;
+
+    case BL_LILAC_RDD_BRIDGE_PORT_VECTOR_LAN1:
+        bridge_port = BL_LILAC_RDD_LAN1_BRIDGE_PORT;
+        break;
+
+    case BL_LILAC_RDD_BRIDGE_PORT_VECTOR_LAN2:
+        bridge_port = BL_LILAC_RDD_LAN2_BRIDGE_PORT;
+        break;
+
+    case BL_LILAC_RDD_BRIDGE_PORT_VECTOR_LAN3:
+        bridge_port = BL_LILAC_RDD_LAN3_BRIDGE_PORT;
+        break;
+
+    case BL_LILAC_RDD_BRIDGE_PORT_VECTOR_LAN4:
+        bridge_port = BL_LILAC_RDD_LAN4_BRIDGE_PORT;
+        break;
+
+    default:
+        bridge_port = 0;
+        break;
+    }
+
+    return ( bridge_port );
+}
+
+
+static inline int32_t rdd_bridge_port_to_port_index ( BL_LILAC_RDD_BRIDGE_PORT_DTE  xi_bridge_port,
+                                                      BL_LILAC_RDD_SUBNET_ID_DTE    xi_subnet_id )
+{
+    /* upstream */
+    if ( ( xi_bridge_port >= BL_LILAC_RDD_LAN0_BRIDGE_PORT ) && ( xi_bridge_port <= BL_LILAC_RDD_LAN4_BRIDGE_PORT ) )
+    {
+        if ( xi_subnet_id == 0 )
+        {
+            return ( xi_bridge_port );
+        }
+    }
+    /*also apply for G999.1 General configuration:*/
+    else if ( xi_bridge_port == BL_LILAC_RDD_PCI_BRIDGE_PORT )
+    {
+        return ( 0 );
+    }
+
+    /* downstream */
+    else if ( BL_LILAC_RDD_IS_WAN_BRIDGE_PORT(xi_bridge_port) ) // DSL
+    {
+        if ( xi_subnet_id == 0 )
+        {
+            return ( BL_LILAC_RDD_SUBNET_BRIDGE );
+        }
+    }
+    else if ( xi_bridge_port == BL_LILAC_RDD_WAN_IPTV_BRIDGE_PORT )
+    {
+        if ( xi_subnet_id == 0 )
+        {
+            return ( BL_LILAC_RDD_SUBNET_BRIDGE_IPTV );
+        }
+    }
+    else if ( xi_bridge_port == BL_LILAC_RDD_WAN_ROUTER_PORT )
+    {
+        if ( xi_subnet_id == 0 )
+        {
+            return ( BL_LILAC_RDD_SUBNET_FLOW_CACHE );
+        }
+    }
+
+    return ( -1 );
+}
+
+
+static inline int32_t rdd_bridge_port_to_class_id ( BL_LILAC_RDD_BRIDGE_PORT_DTE  xi_bridge_port )
+{
+    switch ( xi_bridge_port )
+    {
+    case BL_LILAC_RDD_WAN0_BRIDGE_PORT: // DSL
+    case BL_LILAC_RDD_WAN1_BRIDGE_PORT: // DSL
+
+        return ( LILAC_RDD_IH_WAN_BRIDGE_LOW_CLASS );
+
+    case BL_LILAC_RDD_LAN0_BRIDGE_PORT:
+
+        return ( LILAC_RDD_IH_LAN_EMAC0_CLASS );
+
+    case BL_LILAC_RDD_LAN1_BRIDGE_PORT:
+
+        return ( LILAC_RDD_IH_LAN_EMAC1_CLASS );
+
+    case BL_LILAC_RDD_LAN2_BRIDGE_PORT:
+
+        return ( LILAC_RDD_IH_LAN_EMAC2_CLASS );
+
+    case BL_LILAC_RDD_LAN3_BRIDGE_PORT:
+
+        return ( LILAC_RDD_IH_LAN_EMAC3_CLASS );
+
+    case BL_LILAC_RDD_LAN4_BRIDGE_PORT:
+
+        return ( LILAC_RDD_IH_LAN_EMAC4_CLASS );
+
+    case BL_LILAC_RDD_PCI_BRIDGE_PORT:
+
+        return ( LILAC_RDD_IH_PCI_CLASS );
+
+    default:
+
+        return ( 0 );
+    }
+
+    return ( 0 );
+}
+
+
+#if !defined(FIRMWARE_INIT)
+static inline int32_t rdd_bridge_port_to_bpm_src_port ( BL_LILAC_RDD_BRIDGE_PORT_DTE  xi_bridge_port )
+{
+    switch ( xi_bridge_port )
+    {
+    case BL_LILAC_RDD_WAN0_BRIDGE_PORT: // DSL
+    case BL_LILAC_RDD_WAN1_BRIDGE_PORT: // DSL
+
+        return ( DRV_BPM_SP_GPON );
+
+    case BL_LILAC_RDD_LAN0_BRIDGE_PORT:
+
+        return ( DRV_BPM_SP_EMAC0 );
+
+    case BL_LILAC_RDD_LAN1_BRIDGE_PORT:
+
+        return ( DRV_BPM_SP_EMAC1 );
+
+    case BL_LILAC_RDD_LAN2_BRIDGE_PORT:
+
+        return ( DRV_BPM_SP_EMAC2 );
+
+    case BL_LILAC_RDD_LAN3_BRIDGE_PORT:
+
+        return ( DRV_BPM_SP_EMAC3 );
+
+    case BL_LILAC_RDD_LAN4_BRIDGE_PORT:
+
+        return ( DRV_BPM_SP_EMAC4 );
+
+    case BL_LILAC_RDD_PCI_BRIDGE_PORT:
+
+        return ( DRV_BPM_SP_PCI0 );
+
+    default:
+
+        return ( 0 );
+    }
+
+    return ( 0 );
+}
+#endif
+
+
+BL_LILAC_RDD_ERROR_DTE rdd_timer_task_config ( rdpa_traffic_dir  xi_direction,
+                                               uint16_t          xi_task_period_in_usec,
+                                               uint16_t          xi_firmware_routine_address_id );
+
+
+static inline uint32_t rdd_budget_to_alloc_unit ( uint32_t budget, uint32_t period, uint32_t exponent )
+{
+    return ( ( ( budget + ( ( 1000000 / period ) / 2 ) ) / ( 1000000 / period ) ) >> exponent );
+}
+
+
+static inline uint32_t rdd_get_exponent ( uint32_t  value,
+                                          uint32_t  mantissa_len,
+                                          uint32_t  exponent_list_len,
+                                          uint32_t  *exponent_list )
+{
+    uint32_t  i;
+
+    for ( i = exponent_list_len - 1; i > 0; i-- )
+    {
+        if ( value > ( ( ( 1 << mantissa_len ) - 1 ) << exponent_list[ i - 1 ] ) )
+        {
+            return ( i );
+        }
+    }
+
+    return ( 0 );
+}
+
+
+BL_LILAC_RDD_ERROR_DTE f_rdd_cpu_tx_send_message ( LILAC_RDD_CPU_TX_MESSAGE_TYPE  xi_msg_type,
+                                                   LILAC_RDD_RUNNER_INDEX_DTS     xi_runner_index,
+                                                   uint32_t                       xi_sram_base,
+                                                   uint32_t                       xi_parameter_1,
+                                                   uint32_t                       xi_parameter_2,
+                                                   uint32_t                       xi_parameter_3,
+                                                   BL_LILAC_RDD_CPU_WAIT_DTE      xi_wait );
+
+#define rdd_cpu_tx_send_message f_rdd_cpu_tx_send_message
+
+
+#endif /* _BL_LILAC_DRV_RUNNER_COMMON_H */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_cpu.c b/arch/arm/mach-bcmbca/rdp/rdd_cpu.c
new file mode 100755
index 0000000000..eb1813cac0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_cpu.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#include "rdd.h"
+
+#define _RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE  RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE2
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Global Variables                                */
+/*                                                                            */
+/******************************************************************************/
+
+#if !defined(FIRMWARE_INIT)
+static uint8_t                                 g_dummy_read;
+#endif
+extern uint8_t                                 g_broadcom_switch_mode;
+extern BL_LILAC_RDD_BRIDGE_PORT_DTE            g_broadcom_switch_physical_port;
+
+extern RDD_WAN_TX_POINTERS_TABLE_DTS           *wan_tx_pointers_table_ptr;
+extern rdpa_bpm_buffer_size_t g_bpm_buffer_size;
+
+BL_LILAC_RDD_ERROR_DTE rdd_cpu_rx_initialize ( void )
+{
+    RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS               *cpu_reason_to_cpu_rx_queue_table_ptr;
+    RDD_CPU_REASON_TO_CPU_RX_QUEUE_ENTRY_DTS               *cpu_reason_to_cpu_rx_queue_entry_ptr;
+    RDD_DS_CPU_REASON_TO_METER_TABLE_DTS                      *cpu_reason_to_meter_table_ptr;
+    RDD_CPU_REASON_TO_METER_ENTRY_DTS                      *cpu_reason_to_meter_entry_ptr;
+    uint16_t                                               *cpu_rx_ingress_queue_ptr;
+    uint8_t                                                cpu_reason;
+    uint8_t                                                cpu_queue;
+
+    cpu_rx_ingress_queue_ptr = ( uint16_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_ADDRESS );
+
+    MWRITE_16( cpu_rx_ingress_queue_ptr, DS_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS );
+
+    cpu_rx_ingress_queue_ptr = ( uint16_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_FAST_INGRESS_QUEUE_PTR_ADDRESS );
+
+    MWRITE_16( cpu_rx_ingress_queue_ptr, US_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS );
+
+
+    cpu_rx_ingress_queue_ptr = ( uint16_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_ADDRESS );
+
+    MWRITE_16( cpu_rx_ingress_queue_ptr, DS_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS );
+
+    cpu_rx_ingress_queue_ptr = ( uint16_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_PICO_INGRESS_QUEUE_PTR_ADDRESS );
+
+    MWRITE_16( cpu_rx_ingress_queue_ptr, US_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS );
+
+    cpu_reason_to_cpu_rx_queue_table_ptr = ( RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS );
+
+    /* set cpu reason_direct_flow to queue 0 for backward compatibility */
+    cpu_reason = rdpa_cpu_rx_reason_direct_flow;
+    cpu_queue = BL_LILAC_RDD_CPU_RX_QUEUE_0;
+    cpu_reason_to_cpu_rx_queue_entry_ptr = &( cpu_reason_to_cpu_rx_queue_table_ptr->entry[ 0 ] [ cpu_reason ] );
+    RDD_CPU_REASON_TO_CPU_RX_QUEUE_ENTRY_CPU_RX_QUEUE_WRITE ( cpu_queue, cpu_reason_to_cpu_rx_queue_entry_ptr );
+    cpu_reason_to_cpu_rx_queue_entry_ptr = &( cpu_reason_to_cpu_rx_queue_table_ptr->entry[ 1 ] [ cpu_reason ] );
+    RDD_CPU_REASON_TO_CPU_RX_QUEUE_ENTRY_CPU_RX_QUEUE_WRITE ( cpu_queue, cpu_reason_to_cpu_rx_queue_entry_ptr );
+
+    for ( cpu_reason = rdpa_cpu_rx_reason_oam; cpu_reason < rdpa_cpu_reason__num_of; cpu_reason++ )
+    {
+        cpu_reason_to_meter_table_ptr = ( RDD_DS_CPU_REASON_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_REASON_TO_METER_TABLE_ADDRESS );
+
+        cpu_reason_to_meter_entry_ptr = &( cpu_reason_to_meter_table_ptr->entry[ cpu_reason ] );
+
+        RDD_CPU_REASON_TO_METER_ENTRY_CPU_METER_WRITE ( BL_LILAC_RDD_CPU_METER_DISABLE, cpu_reason_to_meter_entry_ptr );
+
+        cpu_reason_to_meter_table_ptr = ( RDD_DS_CPU_REASON_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_REASON_TO_METER_TABLE_ADDRESS );
+
+        cpu_reason_to_meter_entry_ptr = &( cpu_reason_to_meter_table_ptr->entry[ cpu_reason ] );
+
+        RDD_CPU_REASON_TO_METER_ENTRY_CPU_METER_WRITE ( BL_LILAC_RDD_CPU_METER_DISABLE, cpu_reason_to_meter_entry_ptr );
+    }
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+BL_LILAC_RDD_ERROR_DTE rdd_cpu_tx_initialize ( void )
+{
+    uint32_t *ih_header_descriptor_ptr;
+    uint32_t ih_header_descriptor[2];
+    uint32_t *ih_buffer_bbh_ptr;
+    int i;
+
+    ih_header_descriptor_ptr = ( uint32_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS );
+
+    ih_header_descriptor[ 0 ] = ( LILAC_RDD_ON << 5 ) + ( CPU_TX_FAST_THREAD_NUMBER << 6 );
+
+    ih_header_descriptor[ 1 ] = WAN_SRC_PORT + ( LILAC_RDD_IH_HEADER_LENGTH << 5 ) + ( LILAC_RDD_RUNNER_A_IH_BUFFER << 20 );
+
+    MWRITE_32( ( ( uint8_t * )ih_header_descriptor_ptr + 0 ), ih_header_descriptor[ 0 ] );
+    MWRITE_32( ( ( uint8_t * )ih_header_descriptor_ptr + 4 ), ih_header_descriptor[ 1 ] );
+
+    ih_header_descriptor_ptr = ( uint32_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS );
+    for (i = 0; i < 3; i++)
+    {
+        ih_header_descriptor[ 0 ] = LILAC_RDD_ON << 5;
+
+        ih_header_descriptor[ 1 ] = ( LILAC_RDD_IH_HEADER_LENGTH << 5 ) + ( LILAC_RDD_RUNNER_B_IH_BUFFER << 20 );
+
+        MWRITE_32( ( ( uint8_t * )ih_header_descriptor_ptr + 0 ), ih_header_descriptor[ 0 ] );
+        MWRITE_32( ( ( uint8_t * )ih_header_descriptor_ptr + 4 ), ih_header_descriptor[ 1 ] );
+        ih_header_descriptor_ptr += 2;
+    }
+
+    ih_buffer_bbh_ptr = ( uint32_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + IH_BUFFER_BBH_POINTER_ADDRESS );
+
+    MWRITE_32( ih_buffer_bbh_ptr, ( ( BBH_PERIPHERAL_IH << 16 ) | ( LILAC_RDD_IH_BUFFER_BBH_ADDRESS + LILAC_RDD_RUNNER_B_IH_BUFFER_BBH_OFFSET ) ) );
+
+    g_cpu_tx_queue_write_ptr[ FAST_RUNNER_A ] = CPU_TX_FAST_QUEUE_ADDRESS;
+    g_cpu_tx_queue_write_ptr[ FAST_RUNNER_B ] = CPU_TX_FAST_QUEUE_ADDRESS;
+    g_cpu_tx_queue_write_ptr[ PICO_RUNNER_A ] = CPU_TX_PICO_QUEUE_ADDRESS;
+    g_cpu_tx_queue_write_ptr[ PICO_RUNNER_B ] = CPU_TX_PICO_QUEUE_ADDRESS;
+
+    g_cpu_tx_queue_abs_data_ptr_write_ptr[ FAST_RUNNER_A ] = DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS;
+    g_cpu_tx_queue_abs_data_ptr_write_ptr[ FAST_RUNNER_B ] = US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS;
+    g_cpu_tx_queue_abs_data_ptr_write_ptr[ PICO_RUNNER_A ] = DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS;
+    g_cpu_tx_queue_abs_data_ptr_write_ptr[ PICO_RUNNER_B ] = US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS;
+
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+BL_LILAC_RDD_ERROR_DTE _rdd_cpu_reason_to_cpu_rx_queue ( rdpa_cpu_reason  xi_cpu_reason,
+                                                        BL_LILAC_RDD_CPU_RX_QUEUE_DTE   xi_queue_id,
+                                                        rdpa_traffic_dir                xi_direction,
+                                                        uint32_t                        xi_table_index )
+{
+    RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS  *cpu_reason_to_cpu_rx_queue_table_ptr;
+    RDD_CPU_REASON_TO_CPU_RX_QUEUE_ENTRY_DTS  *cpu_reason_to_cpu_rx_queue_entry_ptr;
+    uint8_t                                   cpu_queue;
+
+    /* check the validity of the input parameters - CPU-RX reason */
+    if ( xi_cpu_reason >= _RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE )
+    {
+        return ( BL_LILAC_RDD_ERROR_CPU_RX_REASON_ILLEGAL );
+    }
+
+    if ( (xi_direction == rdpa_dir_ds && xi_table_index > CPU_REASON_WAN1_TABLE_INDEX) ||
+         (xi_direction == rdpa_dir_us && xi_table_index > CPU_REASON_LAN_TABLE_INDEX) )
+    {
+        return ( BL_LILAC_RDD_ERROR_CPU_RX_REASON_ILLEGAL );
+    }
+
+    /* check the validity of the input parameters - CPU-RX queue-id */
+    if ( xi_queue_id >= CPU_RX_NUMBER_OF_QUEUES )
+    {
+        return ( BL_LILAC_RDD_ERROR_CPU_RX_QUEUE_ILLEGAL );
+    }
+
+    if ( xi_direction == rdpa_dir_ds )
+    {
+        cpu_reason_to_cpu_rx_queue_table_ptr = ( RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS );
+    }
+    else
+    {
+        cpu_reason_to_cpu_rx_queue_table_ptr = ( RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS - sizeof ( RUNNER_COMMON ) );
+    }
+
+    cpu_reason_to_cpu_rx_queue_entry_ptr = &( cpu_reason_to_cpu_rx_queue_table_ptr->entry[xi_table_index] [ xi_cpu_reason ] );
+
+    cpu_queue = xi_queue_id;
+
+    RDD_CPU_REASON_TO_CPU_RX_QUEUE_ENTRY_CPU_RX_QUEUE_WRITE ( cpu_queue, cpu_reason_to_cpu_rx_queue_entry_ptr );
+
+    return ( BL_LILAC_RDD_OK ); 
+}
+
+BL_LILAC_RDD_ERROR_DTE rdd_cpu_reason_to_cpu_rx_queue ( rdpa_cpu_reason  xi_cpu_reason,
+                                                        BL_LILAC_RDD_CPU_RX_QUEUE_DTE   xi_queue_id,
+                                                        rdpa_traffic_dir                xi_direction,
+                                                        uint32_t                        xi_table_index )
+{
+    return _rdd_cpu_reason_to_cpu_rx_queue(xi_cpu_reason, xi_queue_id, xi_direction, xi_table_index);
+}
+
+BL_LILAC_RDD_ERROR_DTE rdd_cpu_tx_write_eth_packet ( uint8_t                    *xi_packet_ptr,
+                                                     uint32_t                   xi_packet_size,
+                                                     BL_LILAC_RDD_EMAC_ID_DTE   xi_emac_id,
+                                                     uint8_t                    xi_wifi_ssid,
+                                                     BL_LILAC_RDD_QUEUE_ID_DTE  xi_queue_id )
+{
+#if !defined(FIRMWARE_INIT)
+    RUNNER_REGS_CFG_CPU_WAKEUP  runner_cpu_wakeup_register;
+    uint8_t                    *packet_ddr_ptr;
+#endif
+    RDD_CPU_TX_DESCRIPTOR_DTS   *cpu_tx_descriptor_ptr;
+    uint32_t                    cpu_tx_descriptor;
+    uint32_t                    bpm_buffer_number;
+    uint8_t                     cpu_tx_descriptor_valid;
+    unsigned long               flags;
+
+    bdmf_fastlock_lock_irq ( &int_lock_irq, flags );
+
+    cpu_tx_descriptor_ptr = ( RDD_CPU_TX_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + g_cpu_tx_queue_write_ptr[ PICO_RUNNER_A ] );
+
+    /* if the descriptor is valid then the CPU-TX queue is full and the packet should be dropped */
+    RDD_CPU_TX_DESCRIPTOR_CORE_VALID_READ ( cpu_tx_descriptor_valid, cpu_tx_descriptor_ptr );
+
+    if ( cpu_tx_descriptor_valid )
+    {
+        bdmf_fastlock_unlock_irq ( &int_lock_irq, flags );
+        return ( BL_LILAC_RDD_ERROR_CPU_TX_QUEUE_FULL );
+    }
+
+#if !defined(FIRMWARE_INIT)
+    if ( fi_bl_drv_bpm_req_buffer ( DRV_BPM_SP_SPARE_0, ( uint32_t * )&bpm_buffer_number ) != DRV_BPM_ERROR_NO_ERROR )
+    {
+        bdmf_fastlock_unlock_irq ( &int_lock_irq, flags );
+        return ( BL_LILAC_RDD_ERROR_BPM_ALLOC_FAIL );
+    }
+
+    packet_ddr_ptr = g_runner_ddr_base_addr + bpm_buffer_number * g_bpm_buffer_size + g_ddr_headroom_size + LILAC_RDD_PACKET_DDR_OFFSET;
+
+    /* copy the packet from the supplied DDR buffer */
+    MWRITE_BLK_8 ( packet_ddr_ptr, xi_packet_ptr, xi_packet_size );
+
+    g_dummy_read = *( packet_ddr_ptr + xi_packet_size - 1 );
+#else
+    bpm_buffer_number = 0;
+#endif
+
+    /* write CPU-TX descriptor and validate it */
+    cpu_tx_descriptor = 0;
+    RDD_CPU_TX_DESCRIPTOR_CORE_PAYLOAD_OFFSET_L_WRITE(cpu_tx_descriptor, (g_ddr_headroom_size + LILAC_RDD_PACKET_DDR_OFFSET) / 2);
+    
+    RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_L_WRITE(cpu_tx_descriptor, bpm_buffer_number);
+    /* !!! assuming this function is only used by 63138/63148 CFE, we hardcode 1 to lag_port_pti */
+    RDD_CPU_TX_DESCRIPTOR_CORE_LAG_PORT_PTI_L_WRITE(cpu_tx_descriptor, 1);
+
+    MWRITE_32((uint8_t *)cpu_tx_descriptor_ptr + 4, cpu_tx_descriptor);
+
+    cpu_tx_descriptor = 0;
+    RDD_CPU_TX_DESCRIPTOR_CORE_PACKET_LENGTH_L_WRITE(cpu_tx_descriptor, xi_packet_size + 4);
+    RDD_CPU_TX_DESCRIPTOR_CORE_SRC_BRIDGE_PORT_L_WRITE(cpu_tx_descriptor, SPARE_0_SRC_PORT);
+    RDD_CPU_TX_DESCRIPTOR_CORE_TX_QUEUE_L_WRITE(cpu_tx_descriptor, xi_queue_id);
+    RDD_CPU_TX_DESCRIPTOR_CORE_EMAC_L_WRITE(cpu_tx_descriptor, xi_emac_id);
+    RDD_CPU_TX_DESCRIPTOR_CORE_COMMAND_L_WRITE(cpu_tx_descriptor, LILAC_RDD_CPU_TX_COMMAND_EGRESS_PORT_PACKET);
+    RDD_CPU_TX_DESCRIPTOR_CORE_VALID_L_WRITE(cpu_tx_descriptor, LILAC_RDD_TRUE);
+
+    MWRITE_32((uint8_t *)cpu_tx_descriptor_ptr, cpu_tx_descriptor);
+
+    /* increment and wrap around if needed the write pointer of the CPU-TX queue */
+    g_cpu_tx_queue_write_ptr[ PICO_RUNNER_A ] += sizeof(RDD_CPU_TX_DESCRIPTOR_DTS);
+    g_cpu_tx_queue_write_ptr[ PICO_RUNNER_A ] &= LILAC_RDD_CPU_TX_QUEUE_SIZE_MASK;
+
+#if !defined(FIRMWARE_INIT)
+    /* send asynchronous wakeup command to the CPU-TX thread in the Runner */
+    runner_cpu_wakeup_register.req_trgt = CPU_TX_PICO_THREAD_NUMBER >> 5;
+    runner_cpu_wakeup_register.thread_num = CPU_TX_PICO_THREAD_NUMBER & 0x1f;
+    runner_cpu_wakeup_register.urgent_req = LILAC_RDD_FALSE;
+
+    RUNNER_REGS_0_CFG_CPU_WAKEUP_WRITE ( runner_cpu_wakeup_register );
+#endif
+
+    bdmf_fastlock_unlock_irq ( &int_lock_irq, flags );
+    return ( BL_LILAC_RDD_OK );
+}
+
+BL_LILAC_RDD_ERROR_DTE rdd_ring_init ( uint32_t  xi_ring_id,
+                                       uint8_t unused0,
+                                       rdd_phys_addr_t xi_ring_address,
+                                       uint32_t  xi_number_of_entries,
+                                       uint32_t  xi_size_of_entry,
+                                       uint32_t  xi_interrupt_id,
+                                       uint32_t unused1,
+                                       bdmf_phys_addr_t unused2,
+                                       uint8_t unused3
+                                       )
+{
+    RDD_RING_DESCRIPTORS_TABLE_DTS  *ring_table_ptr;
+    RDD_RING_DESCRIPTOR_DTS         *ring_descriptor_ptr;
+
+
+    ring_table_ptr = ( RDD_RING_DESCRIPTORS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RING_DESCRIPTORS_TABLE_ADDRESS );
+
+    ring_descriptor_ptr = &( ring_table_ptr->entry[ xi_ring_id ] );
+
+    RDD_RING_DESCRIPTOR_ENTRIES_COUNTER_WRITE ( 0, ring_descriptor_ptr );
+    RDD_RING_DESCRIPTOR_SIZE_OF_ENTRY_WRITE ( xi_size_of_entry, ring_descriptor_ptr );
+    RDD_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_WRITE ( xi_number_of_entries, ring_descriptor_ptr );
+    RDD_RING_DESCRIPTOR_INTERRUPT_ID_WRITE ( 1 << xi_interrupt_id, ring_descriptor_ptr );
+    RDD_RING_DESCRIPTOR_RING_POINTER_WRITE ( xi_ring_address, ring_descriptor_ptr );
+
+    return ( BL_LILAC_RDD_OK );
+}
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_cpu.h b/arch/arm/mach-bcmbca/rdp/rdd_cpu.h
new file mode 100755
index 0000000000..e0c9a4b4bb
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_cpu.h
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+
+/*
+    
+*/
+
+#ifndef _BL_LILAC_DRV_RUNNER_CPU_H
+#define _BL_LILAC_DRV_RUNNER_CPU_H
+
+#include "rdpa_cpu.h"
+#include "bdmf_errno.h"
+
+extern uint8_t  *g_runner_ddr_base_addr;
+extern uint32_t  g_ddr_headroom_size;
+extern uint32_t  g_cpu_tx_queue_write_ptr[ 4 ];
+extern uint32_t  g_cpu_tx_queue_abs_data_ptr_write_ptr[ 4 ];
+extern uint32_t  g_cpu_tx_abs_packet_limit;
+
+
+extern uint16_t  *g_free_skb_indexes_fifo_table;
+extern uint8_t **g_cpu_tx_skb_pointers_reference_array;
+extern bdmf_fastlock int_lock_irq;
+
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_cpu_reason_to_cpu_rx_queue                                           */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - CPU interface.                                         */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   cpu trap reason to cpu rx queue conversion.                              */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_cpu_reason - the reason for sending the packet to the CPU             */
+/*   xi_queue_id - CPU-RX queue index (0-7)                                   */
+/*   xi_direction - upstream or downstream                                    */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*     BL_LILAC_RDD_ERROR_CPU_RX_QUEUE_ILLEGAL - CPU-RX queue is illegal.     */
+/*     BL_LILAC_RDD_ERROR_CPU_RX_REASON_ILLEGAL - CPU-RX reason is illegal.   */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_cpu_reason_to_cpu_rx_queue ( rdpa_cpu_reason  xi_cpu_reason,
+                                                        BL_LILAC_RDD_CPU_RX_QUEUE_DTE   xi_queue_id,
+                                                        rdpa_traffic_dir                xi_direction,
+                                                        uint32_t                        xi_table_index );
+
+/******************************************************************************/
+/*                                                                            */
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_l4_dst_port_read                                                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - CPU interface.                                         */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   read entry from l4 dst port to cpu trap reason mapping table.            */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_index - index of entry want to read                                   */
+/*   xo_is_static - static or dynamic                                         */
+/*   xo_is_tcp - tcp or udp                                                   */  
+/*   xo_l4_dst_port - dst port                                                */
+/*   xo_reason - the cpu trap reason                                          */
+/*   xo_refcnt - reference count                                              */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_l4_dst_port_read ( uint32_t xi_index, bdmf_boolean *xo_is_static, bdmf_boolean *xo_is_tcp, uint16_t *xo_l4_dst_port, rdpa_cpu_reason *xo_reason, uint8_t *xo_refcnt );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_l4_dst_port_delete                                                   */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - CPU interface.                                         */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   delete entry from l4 dst port to cpu trap reason mapping table.          */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_index - index of entry want to read                                   */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_l4_dst_port_delete ( uint32_t xi_index );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_l4_dst_port_find                                                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - CPU interface.                                         */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   find entry in l4 dst port to cpu trap reason mapping table.              */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_is_tcp - tcp or udp                                                   */  
+/*   xi_l4_dst_port - dst port                                                */
+/*   xo_index - index of the new add entry                                    */  
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_l4_dst_port_find ( bdmf_boolean xi_is_tcp, uint16_t xi_l4_dst_port, uint32_t *xo_index );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_cpu_tx_write_eth_packet                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - CPU interface.                                         */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This packet is directed to the EMAC TX queue.                            */
+/*   check if the CPU TX queue is not full, if not then a DDR buffer is       */
+/*   allocated from the BPM, then the packet data is copied to the allocated  */
+/*   buffer and a new packet descriptor is written to the CPU TX queue.       */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_packet_ptr - pointer to a DDR buffer that hold the packet data        */
+/*   xi_packet_size - packet size in bytes                                    */
+/*   xi_emac_id - EMAC port index (ETH0 - ETH4, PCI)                          */
+/*   xi_wifi_ssid - service set id for PCI with wifi multiple ssid support    */
+/*   xi_queue_id - ETH TX queue index                                         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*     BL_LILAC_RDD_ERROR_CPU_TX_NOT_ALLOWED - the runner is not enabled.     */
+/*     BL_LILAC_RDD_ERROR_CPU_TX_QUEUE_FULL - the CPU TX has no place for new */
+/*                                            packets.                        */
+/*     BL_LILAC_RDD_ERROR_BPM_ALLOC_FAIL - unable to allocate a DDR buffer to */
+/*                                         from the BPM.                      */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_cpu_tx_write_eth_packet ( uint8_t                    *xi_packet_ptr,
+                                                     uint32_t                   xi_packet_size,
+                                                     BL_LILAC_RDD_EMAC_ID_DTE   xi_emac_id,
+                                                     uint8_t                    xi_wifi_ssid,
+                                                     BL_LILAC_RDD_QUEUE_ID_DTE  xi_queue_id );
+
+/* local */
+BL_LILAC_RDD_ERROR_DTE rdd_cpu_rx_initialize ( void );
+
+BL_LILAC_RDD_ERROR_DTE rdd_cpu_tx_initialize ( void );
+
+BL_LILAC_RDD_ERROR_DTE rdd_spdsvc_initialize( void );
+
+BL_LILAC_RDD_ERROR_DTE rdd_spdsvc_get_tx_result( uint8_t *xo_running_p,
+                                                 uint32_t *xo_tx_packets_p,
+                                                 uint32_t *xo_tx_discards_p );
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_ring_init                                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - CPU interface.                                         */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   configures CPU-RX ring, set the number packets that are pending to be    */
+/*   read by the CPU for that queue, and the interrupt that will be set       */
+/*   during packet enterance to the queue, the default interrupt is the queue */
+/*   number.                                                                  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ring_id - CPU-RX ring index (0-7)                                     */
+/*   xi_number_of_entries - queue maximum size in packets.                    */
+/*   xi_ring_address - address of allocated ring                              */
+/*   xi_size_of_entry - size of cpu-rx descriptor                             */
+/*   xi_interrupt_id  - interrupt id to set                                   */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_ring_init ( uint32_t  xi_ring_id,
+                                       uint8_t unused0,
+                                       rdd_phys_addr_t xi_ring_address,
+                                       uint32_t  xi_number_of_entries,
+                                       uint32_t  xi_size_of_entry,
+                                       uint32_t  xi_interrupt_id,
+                                       uint32_t unused1,
+                                       bdmf_phys_addr_t unused2,
+                                       uint8_t unused3
+                                       );
+
+#endif /* _BL_LILAC_DRV_RUNNER_CPU_H */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_data_structures.h b/arch/arm/mach-bcmbca/rdp/rdd_data_structures.h
new file mode 100755
index 0000000000..67e3eeb5e8
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_data_structures.h
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef _BL_LILAC_DRV_RUNNER_DATA_STRUCTURES_H
+#define _BL_LILAC_DRV_RUNNER_DATA_STRUCTURES_H
+
+
+/********************************** Defines ***********************************/
+
+/* Runner Device Driver version */
+#define LILAC_RDD_RELEASE                                   ( 0x04 )
+#define LILAC_RDD_VERSION                                   ( 0x10 )
+#define LILAC_RDD_PATCH                                     ( 0x02 )
+#define LILAC_RDD_REVISION                                  ( 0x01 )
+
+#define RDP_CFG_BUF_SIZE_2K                                 0
+#define RDP_CFG_BUF_SIZE_4K                                 1
+#define RDP_CFG_BUF_SIZE_16K                                2
+#define RDP_CFG_BUF_SIZE_2_5K                               7
+
+
+#if defined(WL4908) && defined(CONFIG_BCM_JUMBO_FRAME)
+#define LILAC_RDD_RUNNER_PACKET_BUFFER_SIZE                 512 /* FPM token size */
+#elif defined(WL4908)
+#define LILAC_RDD_RUNNER_PACKET_BUFFER_SIZE                 256 /* FPM token size */
+#elif defined(DSL_63138) && defined(CONFIG_BCM_JUMBO_FRAME)
+#define LILAC_RDD_RUNNER_PACKET_BUFFER_SIZE                 2560
+#define RDP_CFG_BUF_SIZE_VALUE RDP_CFG_BUF_SIZE_2_5K
+#elif defined(DSL_63148) && defined(CONFIG_BCM_JUMBO_FRAME)
+#define LILAC_RDD_RUNNER_PACKET_BUFFER_SIZE                 4096
+#define RDP_CFG_BUF_SIZE_VALUE RDP_CFG_BUF_SIZE_4K
+#else
+#define LILAC_RDD_RUNNER_PACKET_BUFFER_SIZE                 2048
+#define RDP_CFG_BUF_SIZE_VALUE RDP_CFG_BUF_SIZE_2K
+#endif
+#define RDD_SIMULATION_PACKET_BUFFER_SIZE                   2048
+#define LILAC_RDD_RUNNER_EXTENSION_BUFFER_SIZE              512
+#define LILAC_RDD_PACKET_DDR_OFFSET                         18
+#define LILAC_RDD_RUNNER_PSRAM_BUFFER_SIZE                  128
+#define LILAC_RDD_RUNNER_EXTENSION_PACKET_BUFFER_SIZE       64
+#define LILAC_RDD_RUNNER_EXTENSION_PACKET_HEADER_SIZE       32
+
+/* RX - TX */
+#define LILAC_RDD_RATE_CONTROLLERS_BUDGET_SET_SIZE          16
+#define RDD_EMAC_NUMBER_OF_QUEUES                           8
+#define LILAC_RDD_EMAC_EGRESS_COUNTER_OFFSET                0
+#define LILAC_RDD_EMAC_RATE_SHAPER_GROUPS_STATUS_OFFSET     8
+#define RDD_RATE_CONTROL_EXPONENT0                          1
+#define RDD_RATE_CONTROL_EXPONENT1                          4
+#define RDD_RATE_CONTROL_EXPONENT2                          7
+#define RDD_RATE_CONTROL_EXPONENT_NUM                       3
+
+/* CPU-RX table & queues */
+
+/* CPU-TX table */
+#define LILAC_RDD_CPU_TX_QUEUE_SIZE                         16
+#define LILAC_RDD_CPU_TX_QUEUE_SIZE_MASK                    0xFF7F
+#define LILAC_RDD_CPU_TX_DESCRIPTOR_NUMBER_MASK             0x00F8
+#define LILAC_RDD_CPU_TX_ABS_DATA_PTR_DESCRIPTOR_SIZE       4
+#define LILAC_RDD_CPU_TX_ABS_DATA_PTR_QUEUE_SIZE            16
+#define LILAC_RDD_CPU_TX_ABS_DATA_PTR_QUEUE_SIZE_MASK       0xFFBF
+#define LILAC_RDD_CPU_TX_COMMAND_EGRESS_PORT_PACKET         0
+#define LILAC_RDD_CPU_TX_COMMAND_BRIDGE_PACKET              1
+#define LILAC_RDD_CPU_TX_COMMAND_INTERWORKING_PACKET        2
+#define LILAC_RDD_CPU_TX_COMMAND_ABSOLUTE_ADDRESS_PACKET    3
+#define LILAC_RDD_CPU_TX_COMMAND_SPDSVC_PACKET              4
+#define LILAC_RDD_CPU_TX_COMMAND_MESSAGE                    7
+
+/* Bridging */
+#define LILAC_RDD_NUMBER_OF_BRIDGE_PORTS                    15
+#define LILAC_RDD_FLOW_CLASSIFICATION_ENTRY_STOP            0xFFFF
+#define LILAC_RDD_MAX_PBITS                                 7
+#define LILAC_RDD_NUMBER_OF_ETHER_TYPE_FILTERS              12
+
+/* Ingress Classification */
+#define RDD_INGRESS_CLASSIFICATION_SEARCH_HOP               BL_LILAC_RDD_MAC_TABLE_MAX_HOP_4
+#define RDD_INGRESS_CLASSIFICATION_SEARCH_DEPTH             (1 << RDD_INGRESS_CLASSIFICATION_SEARCH_HOP)
+
+/* Ingress Handler */
+#define LILAC_RDD_IH_HEADER_LENGTH                          110
+#define LILAC_RDD_IH_BUFFER_BBH_ADDRESS                     0x8000
+#define LILAC_RDD_RUNNER_A_IH_BUFFER                        14
+#define LILAC_RDD_RUNNER_B_IH_BUFFER                        15
+#define LILAC_RDD_RUNNER_A_IH_BUFFER_BBH_OFFSET             ( ( LILAC_RDD_RUNNER_A_IH_BUFFER * 128 + LILAC_RDD_PACKET_DDR_OFFSET ) / 8 )
+#define LILAC_RDD_RUNNER_B_IH_BUFFER_BBH_OFFSET             ( ( LILAC_RDD_RUNNER_B_IH_BUFFER * 128 + LILAC_RDD_PACKET_DDR_OFFSET ) / 8 )
+#define LILAC_RDD_IH_HEADER_DESCRIPTOR_BBH_ADDRESS          0x0
+#define INVALID_BPM_BUFFER                                  0xFFFF
+
+#define LILAC_RDD_IH_PCI_CLASS                              2
+#define LILAC_RDD_IH_WAN_BRIDGE_LOW_CLASS                   9
+#define LILAC_RDD_IH_LAN_EMAC0_CLASS                        10
+#define LILAC_RDD_IH_LAN_EMAC1_CLASS                        11
+#define LILAC_RDD_IH_LAN_EMAC2_CLASS                        12
+#define LILAC_RDD_IH_LAN_EMAC3_CLASS                        13
+#define LILAC_RDD_IH_LAN_EMAC4_CLASS                        14
+
+/* MAC Table */
+#define LILAC_RDD_MAC_CONTEXT_MULTICAST                     0x1
+#define LILAC_RDD_MAC_CONTEXT_ENTRY_TYPE_MASK               ( 1 << 6 )
+
+/* Router Tables */
+#define LILAC_RDD_NUMBER_OF_SUBNETS                         3
+
+#define LILAC_RDD_NUMBER_OF_TIMER_TASKS                     8
+#define LILAC_RDD_CPU_RX_METER_TIMER_PERIOD                 10000
+
+/* VLAN & PBITs actions */
+#define LILAC_RDD_VLAN_TYPES                                4
+#define LILAC_RDD_VLAN_TYPE_UNTAGGED                        0
+#define LILAC_RDD_VLAN_TYPE_SINGLE                          1
+#define LILAC_RDD_VLAN_TYPE_DOUBLE                          2
+#define LILAC_RDD_VLAN_TYPE_PRIORITY                        3
+#define LILAC_RDD_VLAN_COMMAND_SKIP                         128
+
+/* VLAN switching */
+#define LILAC_RDD_LAN_VID_SKIP_VALUE                        0x8000
+#define LILAC_RDD_LAN_VID_STOP_VALUE                        0xFFFF
+
+/* Firewall */
+#define LILAC_RDD_FIREWALL_RULES_MASK_MAX_LENGTH            32
+
+/* PCI */
+#define LILAC_RDD_PCI_TX_NUMBER_OF_FIFOS                    4
+#define LILAC_RDD_PCI_TX_FIFO_SIZE                          8
+
+/* CRC */
+#define RDD_CRC_TYPE_16                                     0
+#define RDD_CRC_TYPE_32                                     1
+
+/* GPIO */
+#define RDD_GPIO_IO_ADDRESS                                 0x148
+
+/* -Etc- */
+#define LILAC_RDD_TRUE                                      1
+#define LILAC_RDD_FALSE                                     0
+#define LILAC_RDD_ON                                        1
+#define LILAC_RDD_OFF                                       0
+
+/* CPU TX */
+#define LILAC_RDD_CPU_TX_SKB_INDEX_OWNERSHIP_BIT_MASK       0x8000
+#define LILAC_RDD_CPU_TX_SKB_INDEX_MASK                     0x3FFF
+#define LILAC_RDD_CPU_TX_SKB_LIMIT_MIN                      256
+#define LILAC_RDD_CPU_TX_SKB_LIMIT_MAX                      16384
+#define LILAC_RDD_CPU_TX_SKB_LIMIT_MULTIPLICATION           8
+
+#define RDD_CLEAR_REGISTER( v )                             ( *( ( uint32_t *) v ) = 0 )
+
+#define ADDRESS_OF(runner, task_name)                       runner##_##task_name
+
+#define ROUND_UP_TO_BITS(_val, _bit)      (((_val) + (1 << _bit) - 1) & ~((1 << _bit) - 1))
+#define ROUND_UP_MB(_n)                   ROUND_UP_TO_BITS(_n, 20ul)
+
+#if defined(WL4908)
+#define RDP_NATC_CONTEXT_TABLE_SIZE       (sizeof(RDD_NATC_CONTEXT_TABLE_DTS))
+#define RDP_NATC_CONTEXT_TABLE_ADDR       (NATC_CONTEXT_TABLE_ADDRESS)
+
+#define RDP_CONTEXT_CONTINUATION_TABLE_SIZE  (sizeof(RDD_CONTEXT_CONTINUATION_TABLE_DTS))
+#define RDP_CONTEXT_CONTINUATION_TABLE_ADDR  (RDP_NATC_CONTEXT_TABLE_ADDR + ROUND_UP_TO_BITS(RDP_NATC_CONTEXT_TABLE_SIZE, 21))
+
+#define RDP_NATC_KEY_TABLE_SIZE           (sizeof(RDD_NAT_CACHE_TABLE_DTS) + sizeof(RDD_NAT_CACHE_EXTENSION_TABLE_DTS))
+#define RDP_NATC_KEY_TABLE_ADDR           (RDP_CONTEXT_CONTINUATION_TABLE_ADDR + ROUND_UP_MB(RDP_CONTEXT_CONTINUATION_TABLE_SIZE))
+
+#define RDP_DDR_DATA_STRUCTURES_SIZE      (RDP_NATC_KEY_TABLE_ADDR + ROUND_UP_MB(RDP_NATC_KEY_TABLE_SIZE))
+
+#ifdef CONFIG_BCM_RDPA_MCAST
+#define RDP_DDR_MC_HEADER_SIZE            0x2000000
+#else
+#define RDP_DDR_MC_HEADER_SIZE            0
+#endif
+#else // if defined(WL4908) else DSL_63138
+#define RDP_DDR_DATA_STRUCTURES_SIZE      (sizeof(RDD_CONNECTION_TABLE_DTS) * 2 + ROUND_UP_MB(sizeof(RDD_CONTEXT_TABLE_DTS)))
+#endif
+
+#if !defined(FIRMWARE_INIT)
+/* DDR offsets */
+#define DsConnectionTableBase              ( g_runner_tables_ptr + DS_CONNECTION_TABLE_ADDRESS )
+#define UsConnectionTableBase              ( g_runner_tables_ptr + US_CONNECTION_TABLE_ADDRESS )
+#endif
+
+/******************************* Data structures ******************************/
+
+#define LILAC_RDD_FIELD_SHIFT( ls_bit_number, field_width, write_value )    ( ( write_value & ( ( 1 << (field_width) ) - 1 ) ) << ( ls_bit_number ) )
+
+#define RDD_EMAC_DESCRIPTOR_EGRESS_COUNTER_OFFSET  0
+
+/* WAN TX Pointers table */
+typedef struct
+{
+    uint16_t  wan_channel_ptr;
+    uint16_t  rate_controller_ptr;
+    uint16_t  wan_tx_queue_ptr;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_POINTERS_ENTRY_DTS;
+
+
+typedef struct
+{
+    RDD_WAN_TX_POINTERS_ENTRY_DTS  entry[ RDD_WAN_CHANNELS_0_7_TABLE_SIZE + RDD_WAN_CHANNELS_8_39_TABLE_SIZE ][ RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLER_ADDR_NUMBER ]
+                                        [ RDD_US_RATE_CONTROLLER_DESCRIPTOR_TX_QUEUE_ADDR_NUMBER ];
+}
+RDD_WAN_TX_POINTERS_TABLE_DTS;
+
+
+#define RDD_CPU_RX_DESCRIPTOR_SKB_INDEX_READ( r, p )            FIELD_MREAD_32( ( (uint8_t *)p + 4),  0,  8, r )
+#define RDD_CPU_RX_DESCRIPTOR_REASON_L_READ( p )                FIELD_GET( *( (uint32_t *)p + 0), 25,  6 )
+#define RDD_CPU_RX_DESCRIPTOR_PAYLOAD_OFFSET_FLAG_L_READ( p )   FIELD_GET( *( (uint32_t *)p + 0), 22,  1 )
+#define RDD_CPU_RX_DESCRIPTOR_FLOW_ID_L_READ( p )               FIELD_GET( *( (uint32_t *)p + 0), 14,  8 )
+#define RDD_CPU_RX_DESCRIPTOR_PACKET_LENGTH_L_READ( p )         FIELD_GET( *( (uint32_t *)p + 0),  0, 14 )
+#define RDD_CPU_RX_DESCRIPTOR_SRC_PORT_L_READ( p )              FIELD_GET( *( (uint32_t *)p + 1), 28,  4 )
+#define RDD_CPU_RX_DESCRIPTOR_NEXT_PTR_L_READ( p )              FIELD_GET( *( (uint32_t *)p + 1), 15, 13 )
+#define RDD_CPU_RX_DESCRIPTOR_ABS_FLAG_L_READ( p )              FIELD_GET( *( (uint32_t *)p + 1), 14,  1 )
+#if defined(DSL_63138)
+#define RDD_CPU_RX_DESCRIPTOR_BUFFER_NUMBER_L_READ( p )         FIELD_GET( *( (uint32_t *)p + 1),  0, 15 )
+#else
+#define RDD_CPU_RX_DESCRIPTOR_BUFFER_NUMBER_L_READ( p )         FIELD_GET( *( (uint32_t *)p + 1),  0, 14 )
+#endif
+#define RDD_CPU_RX_DESCRIPTOR_SKB_INDEX_L_READ( p )             FIELD_GET( *( (uint32_t *)p + 1),  0,  8 )
+
+
+#define RDD_CPU_TX_DESCRIPTOR_CONTEXT_INDEX_WRITE( v, p )      FIELD_MWRITE_32( ( (uint8_t *)p + 0), 0, 15, v )
+#define RDD_CPU_TX_DESCRIPTOR_COUNTER_WRITE( v, p )            FIELD_MWRITE_32( ( (uint8_t *)p + 0), 0,  5, v )
+#define RDD_CPU_TX_DESCRIPTOR_IPTV_MAC_IDX_WRITE( v, p )       FIELD_MWRITE_32( ( (uint8_t *)p + 0), 0, 11, v )
+#define RDD_CPU_TX_DESCRIPTOR_COUNTER_4_BYTES_WRITE( v, p )    FIELD_MWRITE_32( ( (uint8_t *)p + 0), 5,  1, v )
+#define RDD_CPU_TX_DESCRIPTOR_SRC_BRIDGE_PORT_WRITE( v, p )    FIELD_MWRITE_32( ( (uint8_t *)p + 0), 14, 5, v )
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_WRITE( v, p )              FIELD_MWRITE_32( ( (uint8_t *)p + 0), 19, 3, v )
+#define RDD_CPU_TX_DESCRIPTOR_GROUP_WRITE( v, p )              FIELD_MWRITE_32( ( (uint8_t *)p + 0), 19, 7, v )
+#define RDD_CPU_TX_DESCRIPTOR_FLOW_WRITE( v, p )               FIELD_MWRITE_32( ( (uint8_t *)p + 0), 19, 9, v )
+#define RDD_CPU_TX_DESCRIPTOR_EMAC_WRITE( v, p )               FIELD_MWRITE_32( ( (uint8_t *)p + 0), 22, 4, v )
+#define RDD_CPU_TX_DESCRIPTOR_INTERRUPT_NUMBER_WRITE( v, p )   FIELD_MWRITE_32( ( (uint8_t *)p + 0), 22, 4, v )
+#define RDD_CPU_TX_DESCRIPTOR_TCONT_INDEX_WRITE( v, p )        FIELD_MWRITE_32( ( (uint8_t *)p + 4), 22, 6, v )
+#define RDD_CPU_TX_DESCRIPTOR_TX_QUEUE_PTR_WRITE( v, p )       FIELD_MWRITE_32( ( (uint8_t *)p + 4), 23, 9, v )
+#define RDD_CPU_TX_DESCRIPTOR_MESSAGE_PARAMETER_WRITE( v, p )  FIELD_MWRITE_32( ( (uint8_t *)p + 4), 23, 5, v )
+
+#define RDD_CPU_TX_DESCRIPTOR_VALID_L_WRITE( v )               LILAC_RDD_FIELD_SHIFT( 31,  1, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_COMMAND_L_WRITE( v )             LILAC_RDD_FIELD_SHIFT( 28,  3, (v) )
+#ifndef G9991
+#define RDD_CPU_TX_DESCRIPTOR_EMAC_L_WRITE( v )                LILAC_RDD_FIELD_SHIFT( 22,  4, (v) )
+#else
+#define RDD_CPU_TX_DESCRIPTOR_EMAC_L_WRITE( v )                LILAC_RDD_FIELD_SHIFT( 22,  5, (v) )
+#endif
+#define RDD_CPU_TX_DESCRIPTOR_US_GEM_FLOW_L_WRITE( v )         LILAC_RDD_FIELD_SHIFT( 20,  8, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_L_WRITE( v )               LILAC_RDD_FIELD_SHIFT( 19,  3, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_SUBNET_ID_L_WRITE( v )           LILAC_RDD_FIELD_SHIFT( 19,  4, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_DS_GEM_FLOW_L_WRITE( v )         LILAC_RDD_FIELD_SHIFT( 14,  8, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_SRC_BRIDGE_PORT_L_WRITE( v )     LILAC_RDD_FIELD_SHIFT( 14,  5, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_PACKET_LENGTH_L_WRITE( v )       LILAC_RDD_FIELD_SHIFT(  0, 14, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_SSID_L_WRITE( v )                LILAC_RDD_FIELD_SHIFT( 27,  4, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_TX_QUEUE_PTR_L_WRITE( v )        LILAC_RDD_FIELD_SHIFT( 23,  9, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_MESSAGE_PARAMETER_L_WRITE( v )   LILAC_RDD_FIELD_SHIFT( 23,  5, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_IH_CLASS_L_WRITE( v )            LILAC_RDD_FIELD_SHIFT( 23,  4, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_PAYLOAD_OFFSET_L_WRITE( v )      LILAC_RDD_FIELD_SHIFT( 16,  7, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_1588_INDICATION_L_WRITE( v )     LILAC_RDD_FIELD_SHIFT( 27,  1, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_TCONT_INDEX_L_WRITE( v )         LILAC_RDD_FIELD_SHIFT(  8,  6, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_ABS_FLAG_L_WRITE( v )            LILAC_RDD_FIELD_SHIFT( 31,  1, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_GSO_PKT_L_WRITE( v )             LILAC_RDD_FIELD_SHIFT( 27,  1, (v) )
+#if defined(DSL_63138)
+#define RDD_CPU_TX_DESCRIPTOR_BUFFER_NUMBER_L_WRITE( v )       LILAC_RDD_FIELD_SHIFT(  0, 15, (v) )
+#else
+#define RDD_CPU_TX_DESCRIPTOR_BUFFER_NUMBER_L_WRITE( v )       LILAC_RDD_FIELD_SHIFT(  0, 14, (v) )
+#endif
+#define RDD_CPU_TX_DESCRIPTOR_SKB_INDEX_L_WRITE( v )           LILAC_RDD_FIELD_SHIFT(  0,  8, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_FLOW_L_WRITE( v )                LILAC_RDD_FIELD_SHIFT( 19,  9, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_IPTV_MAC_IDX_L_WRITE( v )        LILAC_RDD_FIELD_SHIFT(  0, 11, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_GROUP_L_WRITE( v )               LILAC_RDD_FIELD_SHIFT( 19,  7, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_COUNTER_L_WRITE( v )             LILAC_RDD_FIELD_SHIFT(  0,  5, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_COUNTER_4_BYTES_L_WRITE( v )     LILAC_RDD_FIELD_SHIFT(  5,  1, (v) )
+#define RDD_CPU_TX_DESCRIPTOR_MSG_TYPE_L_WRITE( v )            LILAC_RDD_FIELD_SHIFT(  0,  4, (v) )
+
+
+#define LILAC_RDD_INGRESS_RATE_LIMITER_MAX_ALLOCATED_BUDGET    ( ( 1 << 17 ) - 1)
+
+
+typedef struct
+{
+    BL_LILAC_RDD_FILTER_MODE_DTE  entry[ 9 ][ LILAC_RDD_NUMBER_OF_SUBNETS ][ LILAC_RDD_NUMBER_OF_ETHER_TYPE_FILTERS ];
+}
+BL_LILAC_RDD_ETHER_TYPE_FILTER_MATRIX_DTS;
+
+
+/* software version */
+typedef struct
+{
+    /* code */
+    uint8_t   code;
+
+    /* version */
+    uint8_t   version;
+
+    /* patch */
+    uint8_t   patch;
+
+    /* revision */
+    uint8_t   revision;
+}
+BL_LILAC_RDD_VERSION_DTS;
+
+
+#if defined(WL4908)
+#define RDD_FLOW_ENTRIES_SIZE 16512
+#define RDD_FLOW_ENTRY_VALID 0x80000000
+#define RDD_RESERVED_CONTEXT_ENTRIES 128
+#define RDD_CONTEXT_TABLE_SIZE RDD_FLOW_ENTRIES_SIZE
+#endif /* WL4908 */
+
+
+/****************************** Enumeration ***********************************/
+
+typedef enum
+{
+    LILAC_RDD_CPU_TX_MESSAGE_DDR_HEADROOM_SIZE_SET                = 0,
+    LILAC_RDD_CPU_TX_MESSAGE_RX_FLOW_PM_COUNTERS_GET              = 1,
+    LILAC_RDD_CPU_TX_MESSAGE_TX_FLOW_PM_COUNTERS_GET              = 2,
+    LILAC_RDD_CPU_TX_MESSAGE_FLOW_PM_COUNTERS_GET                 = 3,
+    LILAC_RDD_CPU_TX_MESSAGE_BRIDGE_PORT_PM_COUNTERS_GET          = 4,
+    LILAC_RDD_CPU_TX_MESSAGE_FLUSH_GPON_QUEUE                     = 5,
+    LILAC_RDD_CPU_TX_MESSAGE_LAG_PORT_GET                         = 5,
+    LILAC_RDD_CPU_TX_MESSAGE_GLOBAL_REGISTERS_GET                 = 6,
+    LILAC_RDD_CPU_TX_MESSAGE_IPTV_MAC_COUNTER_GET                 = 7,
+    LILAC_RDD_CPU_TX_MESSAGE_INVALIDATE_CONTEXT_INDEX_CACHE_ENTRY = 8,
+    LILAC_RDD_CPU_TX_MESSAGE_RING_DESTROY                         = 9,
+    LILAC_RDD_CPU_TX_MESSAGE_IPV6_CRC_GET                         = 10,
+    LILAC_RDD_CPU_TX_MESSAGE_PM_COUNTER_GET                       = 11,
+    LILAC_RDD_CPU_TX_MESSAGE_FLUSH_ETH_QUEUE                      = 12,
+    LILAC_RDD_CPU_TX_MESSAGE_UPDATE_US_PD_POOL_QUOTA              = 12,
+    LILAC_RDD_CPU_TX_MESSAGE_ACTIVATE_TCONT                       = 13,
+    LILAC_RDD_CPU_TX_MESSAGE_UPDATE_PD_POOL_QUOTA                 = 13,
+    LILAC_RDD_CPU_TX_MESSAGE_MIRRORING_MODE_CONFIG                = 14,
+    LILAC_RDD_CPU_TX_MESSAGE_DHD_MESSAGE                          = 14,
+    LILAC_RDD_CPU_TX_MESSAGE_RELEASE_SKB_BUFFERS                  = 15,
+}
+LILAC_RDD_CPU_TX_MESSAGE_TYPE;
+
+#define RDD_CPU_TX_MESSAGE_DHD_MESSAGE LILAC_RDD_CPU_TX_MESSAGE_DHD_MESSAGE
+
+typedef enum
+{
+    LILAC_RDD_MAC_HASH_TYPE_INCREMENTAL = 0,
+    LILAC_RDD_MAC_HASH_TYPE_CRC16       = 1,
+}
+LILAC_RDD_MAC_TABLE_HASH_TYPE;
+
+
+typedef enum
+{
+    LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_UNKNOWN         = 0,
+    LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_PPPOE_DISCOVERY = 1,
+    LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_PPPOE_SESSION   = 2,
+    LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_IPOE            = 4,
+    LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_USER_DEFINED_0  = 8,
+    LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_USER_DEFINED_1  = 16,
+    LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_USER_DEFINED_2  = 32,
+    LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_USER_DEFINED_3  = 64,
+}
+LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_DTE;
+
+
+typedef enum
+{
+    LILAC_RDD_FARWARDING_DIRECTION_UPSTREAM =   0,
+    LILAC_RDD_FARWARDING_DIRECTION_DOWNSTREAM = 1,
+}
+LILAC_RDD_BRIDGE_FORWARDING_DIRECTION_DTS;
+
+
+
+typedef enum
+{
+    CS_R8  = 0,
+    CS_R9  = 1,
+    CS_R10 = 2,
+    CS_R11 = 4,
+    CS_R12 = 5,
+    CS_R13 = 6,
+    CS_R14 = 8,
+    CS_R15 = 9,
+    CS_R16 = 10,
+    CS_R17 = 12,
+    CS_R18 = 13,
+    CS_R19 = 14,
+    CS_R20 = 16,
+    CS_R21 = 17,
+    CS_R22 = 18,
+    CS_R23 = 20,
+    CS_R24 = 21,
+    CS_R25 = 22,
+    CS_R26 = 24,
+    CS_R27 = 25,
+    CS_R28 = 26,
+    CS_R29 = 28,
+    CS_R30 = 29,
+    CS_R31 = 30,
+}
+LILAC_RDD_LOCAL_REGISTER_INDEX_DTS;
+
+
+typedef enum
+{
+    FAST_RUNNER_A = 0,
+    FAST_RUNNER_B = 1,
+    PICO_RUNNER_A = 2,
+    PICO_RUNNER_B = 3,
+}
+LILAC_RDD_RUNNER_INDEX_DTS;
+
+
+
+/**** ingress classification ****/
+
+typedef struct
+{
+    uint32_t    valid;
+    int32_t     priority;
+    uint32_t    rule_type;
+    uint32_t    next_rule_cfg_id;
+    uint32_t    next_group_id;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_CLASSIFICATION_RULE_CFG_DTE;
+
+
+typedef struct
+{
+    uint32_t                                 first_rule_cfg_id;
+    uint32_t                                 first_gen_filter_rule_cfg_id;
+    RDD_INGRESS_CLASSIFICATION_RULE_CFG_DTE  rule_cfg[ 16 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTE;
+
+
+
+/**** Router definitions ****/
+
+#define LILAC_RDD_CONNECTION_ENTRY_SIZE                 16
+#define LILAC_RDD_CONTEXT_ENTRY_SIZE                    sizeof(RDD_CONTEXT_ENTRY_UNION_DTS)
+#define LILAC_RDD_CONNECTION_TABLE_SET_SIZE             4
+#define LILAC_RDD_RESERVED_CONTEXT_ENTRIES              128
+
+#define PARSER_LAYER4_PROTOCOL_TCP                      1
+#define PARSER_LAYER4_PROTOCOL_UDP                      2
+
+/* Offsets must correspond to current rdd_data_structures_auto.h number_of_ports and port_mask offsets. */
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_NUM_PORTS_PORT_MASK_WRITE( v, p ) FIELD_MWRITE_16((uint8_t *)p + 8, 0, 12, v )
+
+typedef struct
+{
+	uint32_t	good_csum_packets        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	no_csum_packets          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bad_ipv4_hdr_csum_packets	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bad_tcp_udp_csum_packets 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CSO_COUNTERS_ENTRY_DTS;
+
+#define rdd_phys_addr_t bdmf_phys_addr_t 
+
+#endif /*_BL_LILAC_DRV_RUNNER_DATA_STRUCTURES_H */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_data_structures_auto.h b/arch/arm/mach-bcmbca/rdp/rdd_data_structures_auto.h
new file mode 100755
index 0000000000..4d4859861a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_data_structures_auto.h
@@ -0,0 +1,20669 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+
+
+/* This is an automated file. Do not edit its contents. */
+
+
+#ifndef _RDD_DATA_STRUCTURES_AUTO_H
+#define _RDD_DATA_STRUCTURES_AUTO_H
+
+/* PRIVATE_A */
+#define RDD_IH_BUFFER_RESERVED_FW_ONLY_NUMBER	64
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_IH_BUFFER_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IH_BUFFER_DTS;
+
+#if defined DSL_63138
+
+#define RDD_INGRESS_HANDLER_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_IH_BUFFER_DTS	entry[ RDD_INGRESS_HANDLER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_HANDLER_BUFFER_DTS;
+
+#define RDD_INGRESS_HANDLER_BUFFER_PTR()	( RDD_INGRESS_HANDLER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + INGRESS_HANDLER_BUFFER_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved0                     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	next_packet_descriptor_pointer	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PACKET_DESCRIPTOR_DTS;
+
+#define RDD_PACKET_DESCRIPTOR_NEXT_PACKET_DESCRIPTOR_POINTER_READ(r, p)                 MREAD_16((uint8_t *)p + 6, r)
+#define RDD_PACKET_DESCRIPTOR_NEXT_PACKET_DESCRIPTOR_POINTER_WRITE(v, p)                MWRITE_16((uint8_t *)p + 6, v)
+#if defined DSL_63138
+
+typedef struct
+{
+	uint32_t	crc_calc          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wan_port_or_fstat 	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	source_bridge_port	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	absolute_normal   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	last_indication   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pti               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	_1588             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	add_indication    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	header_number     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_offset    	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_location   	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = packet_location, size = 15 bits
+	uint32_t	buffer_number     	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	abs_address_index 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_TX_DESCRIPTOR_DTS;
+
+#define RDD_BBH_TX_DESCRIPTOR_CRC_CALC_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_CRC_CALC_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_WAN_PORT_OR_FSTAT_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p, 3, 12, r)
+#define RDD_BBH_TX_DESCRIPTOR_WAN_PORT_OR_FSTAT_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p, 3, 12, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_BRIDGE_PORT_READ(r, p)                 FIELD_MREAD_32((uint8_t *)p + 0, 14, 5, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_BRIDGE_PORT_WRITE(v, p)                FIELD_MWRITE_32((uint8_t *)p + 0, 14, 5, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 2, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 2, 0, 14, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABSOLUTE_NORMAL_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABSOLUTE_NORMAL_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_INDICATION_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 4, 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_INDICATION_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 4, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_PTI_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 4, 4, 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_PTI_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 4, 4, 2, v)
+#define RDD_BBH_TX_DESCRIPTOR__1588_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 4, 3, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR__1588_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 4, 3, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_ADD_INDICATION_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 4, 2, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_ADD_INDICATION_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 4, 2, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_HEADER_NUMBER_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 4, 7, 3, r)
+#define RDD_BBH_TX_DESCRIPTOR_HEADER_NUMBER_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 4, 7, 3, v)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 5, 0, 7, r)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 5, 0, 7, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 6, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 6, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LOCATION_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 6, 0, 15, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LOCATION_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 6, 0, 15, v)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 6, 0, 15, r)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 6, 0, 15, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_ADDRESS_INDEX_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_ADDRESS_INDEX_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#endif
+
+typedef struct
+{
+	uint32_t	union_field1          	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = union_field1, size = 15 bits
+	uint32_t	next_packet_descriptor	:13	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0             	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1             	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	service_queue         	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	egress_port           	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length         	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	absolute_normal       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast_ssid        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wred_bit              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_queue              	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	header_number         	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_offset        	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number         	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUE_DESCRIPTOR_DTS;
+
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_UNION_FIELD1_READ(r, p)                           FIELD_MREAD_16((uint8_t *)p, 1, 15, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_UNION_FIELD1_WRITE(v, p)                          FIELD_MWRITE_16((uint8_t *)p, 1, 15, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_NEXT_PACKET_DESCRIPTOR_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p, 3, 13, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_NEXT_PACKET_DESCRIPTOR_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p, 3, 13, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_SERVICE_QUEUE_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 1, 1, 3, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_SERVICE_QUEUE_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 1, 1, 3, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_EGRESS_PORT_READ(r, p)                            FIELD_MREAD_32((uint8_t *)p + 0, 14, 3, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_EGRESS_PORT_WRITE(v, p)                           FIELD_MWRITE_32((uint8_t *)p + 0, 14, 3, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                          FIELD_MREAD_16((uint8_t *)p + 2, 0, 14, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                         FIELD_MWRITE_16((uint8_t *)p + 2, 0, 14, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_ABSOLUTE_NORMAL_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_ABSOLUTE_NORMAL_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_MULTICAST_SSID_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 4, 6, 1, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_MULTICAST_SSID_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 4, 6, 1, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_WRED_BIT_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 4, 5, 1, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_WRED_BIT_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 4, 5, 1, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_TX_QUEUE_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 4, 2, 3, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_TX_QUEUE_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 4, 2, 3, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_HEADER_NUMBER_READ(r, p)                          FIELD_MREAD_16((uint8_t *)p + 4, 7, 3, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_HEADER_NUMBER_WRITE(v, p)                         FIELD_MWRITE_16((uint8_t *)p + 4, 7, 3, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_PAYLOAD_OFFSET_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 5, 0, 7, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_PAYLOAD_OFFSET_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 5, 0, 7, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 6, 7, 1, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 6, 7, 1, v)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                          FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_SERVICE_QUEUE_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                         FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_CONNECTION_CONTEXT_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER	32
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_CONNECTION_CONTEXT_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONNECTION_CONTEXT_BUFFER_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_BUFFER_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CONTEXT_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_PTR()	( RDD_DS_CONNECTION_CONTEXT_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CONTEXT_BUFFER_ADDRESS )
+
+#endif
+#define RDD_GSO_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER	32
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_GSO_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_BUFFER_ENTRY_DTS;
+
+#define RDD_GSO_PSEUDO_HEADER_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER	10
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_GSO_PSEUDO_HEADER_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_PSEUDO_HEADER_BUFFER_ENTRY_DTS;
+
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TWO_BYTES_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	active_rate_controllers	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BUDGET_ALLOCATOR_ENTRY_DTS;
+
+#define RDD_BUDGET_ALLOCATOR_ENTRY_ACTIVE_RATE_CONTROLLERS_READ(r, p)                 MREAD_16((uint8_t *)p, r)
+#define RDD_BUDGET_ALLOCATOR_ENTRY_ACTIVE_RATE_CONTROLLERS_WRITE(v, p)                MWRITE_16((uint8_t *)p, v)
+
+#define RDD_BUDGET_ALLOCATOR_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BUDGET_ALLOCATOR_ENTRY_DTS	entry[ RDD_BUDGET_ALLOCATOR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BUDGET_ALLOCATOR_TABLE_DTS;
+
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_PTR()	( RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_ADDRESS )
+
+
+typedef struct
+{
+	uint8_t	cpu_meter 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_REASON_TO_METER_ENTRY_DTS;
+
+#define RDD_CPU_REASON_TO_METER_ENTRY_CPU_METER_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_CPU_REASON_TO_METER_ENTRY_CPU_METER_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+#if defined DSL_63138
+
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE     64
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_REASON_TO_METER_TABLE_DTS;
+
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_PTR()	( RDD_DS_CPU_REASON_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_REASON_TO_METER_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	current_budget  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	budget_limit    	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocated_budget	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_METER_ENTRY_DTS;
+
+#define RDD_CPU_RX_METER_ENTRY_CURRENT_BUDGET_READ(r, p)                   MREAD_16((uint8_t *)p, r)
+#define RDD_CPU_RX_METER_ENTRY_CURRENT_BUDGET_WRITE(v, p)                  MWRITE_16((uint8_t *)p, v)
+#define RDD_CPU_RX_METER_ENTRY_BUDGET_LIMIT_READ(r, p)                     MREAD_16((uint8_t *)p + 2, r)
+#define RDD_CPU_RX_METER_ENTRY_BUDGET_LIMIT_WRITE(v, p)                    MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_CPU_RX_METER_ENTRY_ALLOCATED_BUDGET_READ(r, p)                 MREAD_16((uint8_t *)p + 4, r)
+#define RDD_CPU_RX_METER_ENTRY_ALLOCATED_BUDGET_WRITE(v, p)                MWRITE_16((uint8_t *)p + 4, v)
+
+#define RDD_CPU_RX_METER_TABLE_SIZE     16
+typedef struct
+{
+	RDD_CPU_RX_METER_ENTRY_DTS	entry[ RDD_CPU_RX_METER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_METER_TABLE_DTS;
+
+#define RDD_DS_CPU_RX_METER_TABLE_PTR()	( RDD_DS_CPU_RX_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_METER_TABLE_ADDRESS )
+
+
+typedef struct
+{
+	uint32_t	current_budget	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	exponent      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	commited_rate 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bucket_size   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	commited_burst	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	drop_counter  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_POLICER_ENTRY_DTS;
+
+#define RDD_POLICER_ENTRY_CURRENT_BUDGET_READ(r, p)                 MREAD_32((uint8_t *)p, r)
+#define RDD_POLICER_ENTRY_CURRENT_BUDGET_WRITE(v, p)                MWRITE_32((uint8_t *)p, v)
+#define RDD_POLICER_ENTRY_EXPONENT_READ(r, p)                       MREAD_16((uint8_t *)p + 4, r)
+#define RDD_POLICER_ENTRY_EXPONENT_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_POLICER_ENTRY_COMMITED_RATE_READ(r, p)                  MREAD_16((uint8_t *)p + 6, r)
+#define RDD_POLICER_ENTRY_COMMITED_RATE_WRITE(v, p)                 MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_POLICER_ENTRY_BUCKET_SIZE_READ(r, p)                    MREAD_16((uint8_t *)p + 10, r)
+#define RDD_POLICER_ENTRY_BUCKET_SIZE_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_POLICER_ENTRY_COMMITED_BURST_READ(r, p)                 MREAD_16((uint8_t *)p + 12, r)
+#define RDD_POLICER_ENTRY_COMMITED_BURST_WRITE(v, p)                MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_POLICER_ENTRY_DROP_COUNTER_READ(r, p)                   MREAD_16((uint8_t *)p + 14, r)
+#define RDD_POLICER_ENTRY_DROP_COUNTER_WRITE(v, p)                  MWRITE_16((uint8_t *)p + 14, v)
+
+#define RDD_POLICER_TABLE_SIZE     16
+typedef struct
+{
+	RDD_POLICER_ENTRY_DTS	entry[ RDD_POLICER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_POLICER_TABLE_DTS;
+
+#define RDD_DS_POLICER_TABLE_PTR()	( RDD_DS_POLICER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_POLICER_TABLE_ADDRESS )
+
+#define RDD_IPSEC_DS_BUFFER_RESERVED_NUMBER	176
+
+typedef struct
+{
+	uint8_t	reserved[RDD_IPSEC_DS_BUFFER_RESERVED_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_BUFFER_DTS;
+
+#if defined DSL_63138
+
+#define RDD_IPSEC_DS_BUFFER_POOL_SIZE     2
+typedef struct
+{
+	RDD_IPSEC_DS_BUFFER_DTS	entry[ RDD_IPSEC_DS_BUFFER_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_BUFFER_POOL_DTS;
+
+#define RDD_IPSEC_DS_BUFFER_POOL_PTR()	( RDD_IPSEC_DS_BUFFER_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_BUFFER_POOL_ADDRESS )
+
+#endif
+#define RDD_IPSEC_SA_DESC_AUTH_KEY_NUMBER	32
+#define RDD_IPSEC_SA_DESC_CRYPT_KEY_NUMBER	32
+
+typedef struct
+{
+	uint32_t	spi                                              	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	eng_cfg                                          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                                        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	hmac_dis                                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	auth_key_fetch_dis                               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2                                        	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	auth_alg                                         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	nxt_hdr                                          	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aes_key_size                                     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	des_dec_vec                                      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	des_iters                                        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rng_clk_en                                       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3                                        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rng_seed                                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rng_sample_num                                   	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved4                                        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	crypt_key_fetch_dis                              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	write_dis                                        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mech                                             	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	decrypt                                          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	crypt_alg                                        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved5                                        	:13	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	clustr_ovrrd                                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	read_clustr_sel                                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	write_clustr_sel                                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	add                                              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	auth_key[RDD_IPSEC_SA_DESC_AUTH_KEY_NUMBER];
+	uint8_t	crypt_key[RDD_IPSEC_SA_DESC_CRYPT_KEY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_SA_DESC_DTS;
+
+#define RDD_IPSEC_SA_DESC_SPI_READ(r, p)                                 MREAD_32((uint8_t *)p, r)
+#define RDD_IPSEC_SA_DESC_SPI_WRITE(v, p)                                MWRITE_32((uint8_t *)p, v)
+#define RDD_IPSEC_SA_DESC_SPI_L_READ( wv )                               FIELD_GET( wv, 0, 32 )
+#define RDD_IPSEC_SA_DESC_SPI_L_WRITE( v, wv )                           FIELD_SET( v, 0, 32, wv )
+#define RDD_IPSEC_SA_DESC_ENG_CFG_READ(r, p)                             MREAD_16((uint8_t *)p + 4, r)
+#define RDD_IPSEC_SA_DESC_ENG_CFG_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_IPSEC_SA_DESC_ENG_CFG_L_READ( wv )                           FIELD_GET( wv, 16, 16 )
+#define RDD_IPSEC_SA_DESC_ENG_CFG_L_WRITE( v, wv )                       FIELD_SET( v, 16, 16, wv )
+#define RDD_IPSEC_SA_DESC_HMAC_DIS_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 7, 7, 1, r)
+#define RDD_IPSEC_SA_DESC_HMAC_DIS_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 7, 7, 1, v)
+#define RDD_IPSEC_SA_DESC_HMAC_DIS_L_READ( wv )                          FIELD_GET( wv, 7, 1 )
+#define RDD_IPSEC_SA_DESC_HMAC_DIS_L_WRITE( v, wv )                      FIELD_SET( v, 7, 1, wv )
+#define RDD_IPSEC_SA_DESC_AUTH_KEY_FETCH_DIS_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 7, 6, 1, r)
+#define RDD_IPSEC_SA_DESC_AUTH_KEY_FETCH_DIS_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 7, 6, 1, v)
+#define RDD_IPSEC_SA_DESC_AUTH_KEY_FETCH_DIS_L_READ( wv )                FIELD_GET( wv, 6, 1 )
+#define RDD_IPSEC_SA_DESC_AUTH_KEY_FETCH_DIS_L_WRITE( v, wv )            FIELD_SET( v, 6, 1, wv )
+#define RDD_IPSEC_SA_DESC_AUTH_ALG_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 7, 0, 2, r)
+#define RDD_IPSEC_SA_DESC_AUTH_ALG_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 7, 0, 2, v)
+#define RDD_IPSEC_SA_DESC_AUTH_ALG_L_READ( wv )                          FIELD_GET( wv, 0, 2 )
+#define RDD_IPSEC_SA_DESC_AUTH_ALG_L_WRITE( v, wv )                      FIELD_SET( v, 0, 2, wv )
+#define RDD_IPSEC_SA_DESC_NXT_HDR_READ(r, p)                             MREAD_8((uint8_t *)p + 8, r)
+#define RDD_IPSEC_SA_DESC_NXT_HDR_WRITE(v, p)                            MWRITE_8((uint8_t *)p + 8, v)
+#define RDD_IPSEC_SA_DESC_NXT_HDR_L_READ( wv )                           FIELD_GET( wv, 24, 8 )
+#define RDD_IPSEC_SA_DESC_NXT_HDR_L_WRITE( v, wv )                       FIELD_SET( v, 24, 8, wv )
+#define RDD_IPSEC_SA_DESC_AES_KEY_SIZE_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 9, 5, 3, r)
+#define RDD_IPSEC_SA_DESC_AES_KEY_SIZE_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 9, 5, 3, v)
+#define RDD_IPSEC_SA_DESC_AES_KEY_SIZE_L_READ( wv )                      FIELD_GET( wv, 21, 3 )
+#define RDD_IPSEC_SA_DESC_AES_KEY_SIZE_L_WRITE( v, wv )                  FIELD_SET( v, 21, 3, wv )
+#define RDD_IPSEC_SA_DESC_DES_DEC_VEC_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 9, 2, 3, r)
+#define RDD_IPSEC_SA_DESC_DES_DEC_VEC_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 9, 2, 3, v)
+#define RDD_IPSEC_SA_DESC_DES_DEC_VEC_L_READ( wv )                       FIELD_GET( wv, 18, 3 )
+#define RDD_IPSEC_SA_DESC_DES_DEC_VEC_L_WRITE( v, wv )                   FIELD_SET( v, 18, 3, wv )
+#define RDD_IPSEC_SA_DESC_DES_ITERS_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 9, 0, 2, r)
+#define RDD_IPSEC_SA_DESC_DES_ITERS_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 9, 0, 2, v)
+#define RDD_IPSEC_SA_DESC_DES_ITERS_L_READ( wv )                         FIELD_GET( wv, 16, 2 )
+#define RDD_IPSEC_SA_DESC_DES_ITERS_L_WRITE( v, wv )                     FIELD_SET( v, 16, 2, wv )
+#define RDD_IPSEC_SA_DESC_RNG_CLK_EN_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 10, 7, 1, r)
+#define RDD_IPSEC_SA_DESC_RNG_CLK_EN_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 10, 7, 1, v)
+#define RDD_IPSEC_SA_DESC_RNG_CLK_EN_L_READ( wv )                        FIELD_GET( wv, 15, 1 )
+#define RDD_IPSEC_SA_DESC_RNG_CLK_EN_L_WRITE( v, wv )                    FIELD_SET( v, 15, 1, wv )
+#define RDD_IPSEC_SA_DESC_RNG_SEED_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 10, 5, 1, r)
+#define RDD_IPSEC_SA_DESC_RNG_SEED_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 10, 5, 1, v)
+#define RDD_IPSEC_SA_DESC_RNG_SEED_L_READ( wv )                          FIELD_GET( wv, 13, 1 )
+#define RDD_IPSEC_SA_DESC_RNG_SEED_L_WRITE( v, wv )                      FIELD_SET( v, 13, 1, wv )
+#define RDD_IPSEC_SA_DESC_RNG_SAMPLE_NUM_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 10, 0, 5, r)
+#define RDD_IPSEC_SA_DESC_RNG_SAMPLE_NUM_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 10, 0, 5, v)
+#define RDD_IPSEC_SA_DESC_RNG_SAMPLE_NUM_L_READ( wv )                    FIELD_GET( wv, 8, 5 )
+#define RDD_IPSEC_SA_DESC_RNG_SAMPLE_NUM_L_WRITE( v, wv )                FIELD_SET( v, 8, 5, wv )
+#define RDD_IPSEC_SA_DESC_CRYPT_KEY_FETCH_DIS_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 11, 6, 1, r)
+#define RDD_IPSEC_SA_DESC_CRYPT_KEY_FETCH_DIS_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 11, 6, 1, v)
+#define RDD_IPSEC_SA_DESC_CRYPT_KEY_FETCH_DIS_L_READ( wv )               FIELD_GET( wv, 6, 1 )
+#define RDD_IPSEC_SA_DESC_CRYPT_KEY_FETCH_DIS_L_WRITE( v, wv )           FIELD_SET( v, 6, 1, wv )
+#define RDD_IPSEC_SA_DESC_WRITE_DIS_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 11, 5, 1, r)
+#define RDD_IPSEC_SA_DESC_WRITE_DIS_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 11, 5, 1, v)
+#define RDD_IPSEC_SA_DESC_WRITE_DIS_L_READ( wv )                         FIELD_GET( wv, 5, 1 )
+#define RDD_IPSEC_SA_DESC_WRITE_DIS_L_WRITE( v, wv )                     FIELD_SET( v, 5, 1, wv )
+#define RDD_IPSEC_SA_DESC_MECH_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 11, 3, 2, r)
+#define RDD_IPSEC_SA_DESC_MECH_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 11, 3, 2, v)
+#define RDD_IPSEC_SA_DESC_MECH_L_READ( wv )                              FIELD_GET( wv, 3, 2 )
+#define RDD_IPSEC_SA_DESC_MECH_L_WRITE( v, wv )                          FIELD_SET( v, 3, 2, wv )
+#define RDD_IPSEC_SA_DESC_DECRYPT_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 11, 2, 1, r)
+#define RDD_IPSEC_SA_DESC_DECRYPT_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 11, 2, 1, v)
+#define RDD_IPSEC_SA_DESC_DECRYPT_L_READ( wv )                           FIELD_GET( wv, 2, 1 )
+#define RDD_IPSEC_SA_DESC_DECRYPT_L_WRITE( v, wv )                       FIELD_SET( v, 2, 1, wv )
+#define RDD_IPSEC_SA_DESC_CRYPT_ALG_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 11, 0, 2, r)
+#define RDD_IPSEC_SA_DESC_CRYPT_ALG_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 11, 0, 2, v)
+#define RDD_IPSEC_SA_DESC_CRYPT_ALG_L_READ( wv )                         FIELD_GET( wv, 0, 2 )
+#define RDD_IPSEC_SA_DESC_CRYPT_ALG_L_WRITE( v, wv )                     FIELD_SET( v, 0, 2, wv )
+#define RDD_IPSEC_SA_DESC_CLUSTR_OVRRD_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 13, 2, 1, r)
+#define RDD_IPSEC_SA_DESC_CLUSTR_OVRRD_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 13, 2, 1, v)
+#define RDD_IPSEC_SA_DESC_CLUSTR_OVRRD_L_READ( wv )                      FIELD_GET( wv, 18, 1 )
+#define RDD_IPSEC_SA_DESC_CLUSTR_OVRRD_L_WRITE( v, wv )                  FIELD_SET( v, 18, 1, wv )
+#define RDD_IPSEC_SA_DESC_READ_CLUSTR_SEL_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 13, 1, 1, r)
+#define RDD_IPSEC_SA_DESC_READ_CLUSTR_SEL_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 13, 1, 1, v)
+#define RDD_IPSEC_SA_DESC_READ_CLUSTR_SEL_L_READ( wv )                   FIELD_GET( wv, 17, 1 )
+#define RDD_IPSEC_SA_DESC_READ_CLUSTR_SEL_L_WRITE( v, wv )               FIELD_SET( v, 17, 1, wv )
+#define RDD_IPSEC_SA_DESC_WRITE_CLUSTR_SEL_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 13, 0, 1, r)
+#define RDD_IPSEC_SA_DESC_WRITE_CLUSTR_SEL_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 13, 0, 1, v)
+#define RDD_IPSEC_SA_DESC_WRITE_CLUSTR_SEL_L_READ( wv )                  FIELD_GET( wv, 16, 1 )
+#define RDD_IPSEC_SA_DESC_WRITE_CLUSTR_SEL_L_WRITE( v, wv )              FIELD_SET( v, 16, 1, wv )
+#define RDD_IPSEC_SA_DESC_ADD_READ(r, p)                                 MREAD_16((uint8_t *)p + 14, r)
+#define RDD_IPSEC_SA_DESC_ADD_WRITE(v, p)                                MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_IPSEC_SA_DESC_ADD_L_READ( wv )                               FIELD_GET( wv, 0, 16 )
+#define RDD_IPSEC_SA_DESC_ADD_L_WRITE( v, wv )                           FIELD_SET( v, 0, 16, wv )
+#define RDD_IPSEC_SA_DESC_AUTH_KEY_READ(r, p, i)                         MREAD_I_8((uint8_t *)p + 16, i, r)
+#define RDD_IPSEC_SA_DESC_AUTH_KEY_WRITE(v, p, i)                        MWRITE_I_8((uint8_t *)p + 16, i, v)
+#define RDD_IPSEC_SA_DESC_CRYPT_KEY_READ(r, p, i)                        MREAD_I_8((uint8_t *)p + 48, i, r)
+#define RDD_IPSEC_SA_DESC_CRYPT_KEY_WRITE(v, p, i)                       MWRITE_I_8((uint8_t *)p + 48, i, v)
+#if defined DSL_63138
+
+#define RDD_IPSEC_DS_SA_DESC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_DTS	entry[ RDD_IPSEC_DS_SA_DESC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_SA_DESC_TABLE_DTS;
+
+#define RDD_IPSEC_DS_SA_DESC_TABLE_PTR()	( RDD_IPSEC_DS_SA_DESC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_SA_DESC_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_IPSEC_US_SA_DESC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_DTS	entry[ RDD_IPSEC_US_SA_DESC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_US_SA_DESC_TABLE_DTS;
+
+#define RDD_IPSEC_US_SA_DESC_TABLE_PTR()	( RDD_IPSEC_US_SA_DESC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_US_SA_DESC_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	current_peak_budget           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocated_peak_budget_exponent	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocated_peak_budget         	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_budget_limit_exponent    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_budget_limit             	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	current_sustain_budget        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocated_sustain_budget      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_limiter_mask             	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_burst_counter            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_weight                   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0                     	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_burst_flag               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_DTS;
+
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_CURRENT_PEAK_BUDGET_READ(r, p)                            MREAD_32((uint8_t *)p, r)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_CURRENT_PEAK_BUDGET_WRITE(v, p)                           MWRITE_32((uint8_t *)p, v)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_ALLOCATED_PEAK_BUDGET_EXPONENT_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 4, 6, 2, r)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_ALLOCATED_PEAK_BUDGET_EXPONENT_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 4, 6, 2, v)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_ALLOCATED_PEAK_BUDGET_READ(r, p)                          FIELD_MREAD_16((uint8_t *)p + 4, 0, 14, r)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_ALLOCATED_PEAK_BUDGET_WRITE(v, p)                         FIELD_MWRITE_16((uint8_t *)p + 4, 0, 14, v)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_PEAK_BUDGET_LIMIT_EXPONENT_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 6, 6, 2, r)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_PEAK_BUDGET_LIMIT_EXPONENT_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 6, 6, 2, v)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_PEAK_BUDGET_LIMIT_READ(r, p)                              FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_PEAK_BUDGET_LIMIT_WRITE(v, p)                             FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_CURRENT_SUSTAIN_BUDGET_READ(r, p)                         MREAD_32((uint8_t *)p + 8, r)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_CURRENT_SUSTAIN_BUDGET_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_ALLOCATED_SUSTAIN_BUDGET_READ(r, p)                       MREAD_32((uint8_t *)p + 12, r)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_ALLOCATED_SUSTAIN_BUDGET_WRITE(v, p)                      MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_RATE_LIMITER_MASK_READ(r, p)                              MREAD_32((uint8_t *)p + 16, r)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_RATE_LIMITER_MASK_WRITE(v, p)                             MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_PEAK_BURST_COUNTER_READ(r, p)                             MREAD_16((uint8_t *)p + 20, r)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_PEAK_BURST_COUNTER_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 20, v)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_PEAK_WEIGHT_READ(r, p)                                    MREAD_8((uint8_t *)p + 22, r)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_PEAK_WEIGHT_WRITE(v, p)                                   MWRITE_8((uint8_t *)p + 22, v)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_PEAK_BURST_FLAG_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 23, 0, 1, r)
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_PEAK_BURST_FLAG_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 23, 0, 1, v)
+#if defined DSL_63138
+
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_DTS	entry[ RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_PTR()	( RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + SERVICE_QUEUES_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	period        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	counter_reload	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	firmware_ptr  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TIMER_TASK_DESCRIPTOR_ENTRY_DTS;
+
+#define RDD_TIMER_TASK_DESCRIPTOR_ENTRY_PERIOD_READ(r, p)                         MREAD_8((uint8_t *)p, r)
+#define RDD_TIMER_TASK_DESCRIPTOR_ENTRY_PERIOD_WRITE(v, p)                        MWRITE_8((uint8_t *)p, v)
+#define RDD_TIMER_TASK_DESCRIPTOR_ENTRY_COUNTER_RELOAD_READ(r, p)                 MREAD_8((uint8_t *)p + 1, r)
+#define RDD_TIMER_TASK_DESCRIPTOR_ENTRY_COUNTER_RELOAD_WRITE(v, p)                MWRITE_8((uint8_t *)p + 1, v)
+#define RDD_TIMER_TASK_DESCRIPTOR_ENTRY_FIRMWARE_PTR_READ(r, p)                   MREAD_16((uint8_t *)p + 2, r)
+#define RDD_TIMER_TASK_DESCRIPTOR_ENTRY_FIRMWARE_PTR_WRITE(v, p)                  MWRITE_16((uint8_t *)p + 2, v)
+
+#define RDD_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TIMER_TASK_DESCRIPTOR_ENTRY_DTS	entry[ RDD_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_DTS;
+
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+
+typedef struct
+{
+	uint32_t	bbh_descriptor_0 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbh_descriptor_1 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	skb_free_index   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	copies_in_transit	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	total_copies     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	terminate        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1        	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	total_length     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tokens           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bucket_size      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bucket           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_queue_discards	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_queue_writes  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_queue_reads   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	start_time_usec  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	end_time_usec    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_buf_ptr     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	eth_header_0     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	eth_header_1     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	eth_header_2     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	eth_header_3     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	eth_header_4     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	eth_header_5     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SPDSVC_CONTEXT_ENTRY_DTS;
+
+#define RDD_SPDSVC_CONTEXT_ENTRY_BBH_DESCRIPTOR_0_READ(r, p)                  MREAD_32((uint8_t *)p, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_BBH_DESCRIPTOR_0_WRITE(v, p)                 MWRITE_32((uint8_t *)p, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_BBH_DESCRIPTOR_1_READ(r, p)                  MREAD_32((uint8_t *)p + 4, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_BBH_DESCRIPTOR_1_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_SKB_FREE_INDEX_READ(r, p)                    MREAD_16((uint8_t *)p + 10, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_SKB_FREE_INDEX_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_COPIES_IN_TRANSIT_READ(r, p)                 MREAD_32((uint8_t *)p + 12, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_COPIES_IN_TRANSIT_WRITE(v, p)                MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TOTAL_COPIES_READ(r, p)                      MREAD_32((uint8_t *)p + 16, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TOTAL_COPIES_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TERMINATE_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 20, 7, 1, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TERMINATE_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 20, 7, 1, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TOTAL_LENGTH_READ(r, p)                      MREAD_16((uint8_t *)p + 22, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TOTAL_LENGTH_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 22, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TOKENS_READ(r, p)                            MREAD_16((uint8_t *)p + 24, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TOKENS_WRITE(v, p)                           MWRITE_16((uint8_t *)p + 24, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_BUCKET_SIZE_READ(r, p)                       MREAD_16((uint8_t *)p + 26, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_BUCKET_SIZE_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 26, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_BUCKET_READ(r, p)                            MREAD_32((uint8_t *)p + 28, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_BUCKET_WRITE(v, p)                           MWRITE_32((uint8_t *)p + 28, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TX_QUEUE_DISCARDS_READ(r, p)                 MREAD_32((uint8_t *)p + 32, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TX_QUEUE_DISCARDS_WRITE(v, p)                MWRITE_32((uint8_t *)p + 32, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TX_QUEUE_WRITES_READ(r, p)                   MREAD_32((uint8_t *)p + 36, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TX_QUEUE_WRITES_WRITE(v, p)                  MWRITE_32((uint8_t *)p + 36, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TX_QUEUE_READS_READ(r, p)                    MREAD_32((uint8_t *)p + 40, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_TX_QUEUE_READS_WRITE(v, p)                   MWRITE_32((uint8_t *)p + 40, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_START_TIME_USEC_READ(r, p)                   MREAD_32((uint8_t *)p + 44, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_START_TIME_USEC_WRITE(v, p)                  MWRITE_32((uint8_t *)p + 44, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_END_TIME_USEC_READ(r, p)                     MREAD_32((uint8_t *)p + 48, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_END_TIME_USEC_WRITE(v, p)                    MWRITE_32((uint8_t *)p + 48, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_DATA_BUF_PTR_READ(r, p)                      MREAD_32((uint8_t *)p + 52, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_DATA_BUF_PTR_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 52, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_0_READ(r, p)                      MREAD_32((uint8_t *)p + 56, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_0_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 56, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_1_READ(r, p)                      MREAD_32((uint8_t *)p + 60, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_1_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 60, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_2_READ(r, p)                      MREAD_32((uint8_t *)p + 64, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_2_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 64, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_3_READ(r, p)                      MREAD_32((uint8_t *)p + 68, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_3_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 68, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_4_READ(r, p)                      MREAD_32((uint8_t *)p + 72, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_4_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 72, v)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_5_READ(r, p)                      MREAD_16((uint8_t *)p + 76, r)
+#define RDD_SPDSVC_CONTEXT_ENTRY_ETH_HEADER_5_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 76, v)
+
+typedef struct
+{
+	uint16_t	primitive_address	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TIMER_SCHEDULER_PRIMITIVE_ENTRY_DTS;
+
+#define RDD_TIMER_SCHEDULER_PRIMITIVE_ENTRY_PRIMITIVE_ADDRESS_READ(r, p)                 MREAD_16((uint8_t *)p, r)
+#define RDD_TIMER_SCHEDULER_PRIMITIVE_ENTRY_PRIMITIVE_ADDRESS_WRITE(v, p)                MWRITE_16((uint8_t *)p, v)
+#if defined DSL_63138
+
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_TIMER_SCHEDULER_PRIMITIVE_ENTRY_DTS	entry[ RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_EIGHT_BYTES_RESERVED_FW_ONLY_NUMBER	2
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_EIGHT_BYTES_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EIGHT_BYTES_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_DTS;
+
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_PTR()	( RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS )
+
+#endif
+
+#define RDD_PICO_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TIMER_TASK_DESCRIPTOR_ENTRY_DTS	entry[ RDD_PICO_TIMER_TASK_DESCRIPTOR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PICO_TIMER_TASK_DESCRIPTOR_TABLE_DTS;
+
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_DHD_LIST_TABLE_NUMBER	64
+
+typedef struct
+{
+	uint32_t	bbh_descriptor_0                                                      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbh_descriptor_1                                                      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_buffer_0                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_buffer_1                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_buffer_2                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_buffer_3                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_buffer_4                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_buffer_5                                                           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ingress_queue_write_ptr                                               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bpm_buffer_number_0                                                   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bpm_buffer_number_1                                                   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bpm_buffer_number_2                                                   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bpm_buffer_number_3                                                   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bpm_buffer_address_0                                                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bpm_buffer_address_1                                                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bpm_buffer_address_2                                                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bpm_buffer_address_3                                                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	request_id                                                            	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_buf_ptr                                                          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_list_base_address                                                 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ingress_queue_pd_write_ptr                                            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ingress_queue_pd_read_ptr                                             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_proxy_enabled                                                      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_list_size                                                         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_list_ptr                                                          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	dhd_list_table[RDD_WLAN_MCAST_CONTROL_ENTRY_DHD_LIST_TABLE_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_CONTROL_ENTRY_DTS;
+
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BBH_DESCRIPTOR_0_READ(r, p)                           MREAD_32((uint8_t *)p, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BBH_DESCRIPTOR_0_WRITE(v, p)                          MWRITE_32((uint8_t *)p, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BBH_DESCRIPTOR_1_READ(r, p)                           MREAD_32((uint8_t *)p + 4, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BBH_DESCRIPTOR_1_WRITE(v, p)                          MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_0_READ(r, p)                                MREAD_32((uint8_t *)p + 8, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_0_WRITE(v, p)                               MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_1_READ(r, p)                                MREAD_32((uint8_t *)p + 12, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_1_WRITE(v, p)                               MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_2_READ(r, p)                                MREAD_32((uint8_t *)p + 16, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_2_WRITE(v, p)                               MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_3_READ(r, p)                                MREAD_32((uint8_t *)p + 20, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_3_WRITE(v, p)                               MWRITE_32((uint8_t *)p + 20, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_4_READ(r, p)                                MREAD_32((uint8_t *)p + 24, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_4_WRITE(v, p)                               MWRITE_32((uint8_t *)p + 24, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_5_READ(r, p)                                MREAD_16((uint8_t *)p + 28, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_L2_BUFFER_5_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 28, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_INGRESS_QUEUE_WRITE_PTR_READ(r, p)                    MREAD_16((uint8_t *)p + 30, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_INGRESS_QUEUE_WRITE_PTR_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 30, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_NUMBER_0_READ(r, p)                        MREAD_32((uint8_t *)p + 32, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_NUMBER_0_WRITE(v, p)                       MWRITE_32((uint8_t *)p + 32, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_NUMBER_1_READ(r, p)                        MREAD_32((uint8_t *)p + 36, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_NUMBER_1_WRITE(v, p)                       MWRITE_32((uint8_t *)p + 36, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_NUMBER_2_READ(r, p)                        MREAD_32((uint8_t *)p + 40, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_NUMBER_2_WRITE(v, p)                       MWRITE_32((uint8_t *)p + 40, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_NUMBER_3_READ(r, p)                        MREAD_32((uint8_t *)p + 44, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_NUMBER_3_WRITE(v, p)                       MWRITE_32((uint8_t *)p + 44, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_ADDRESS_0_READ(r, p)                       MREAD_32((uint8_t *)p + 48, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_ADDRESS_0_WRITE(v, p)                      MWRITE_32((uint8_t *)p + 48, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_ADDRESS_1_READ(r, p)                       MREAD_32((uint8_t *)p + 52, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_ADDRESS_1_WRITE(v, p)                      MWRITE_32((uint8_t *)p + 52, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_ADDRESS_2_READ(r, p)                       MREAD_32((uint8_t *)p + 56, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_ADDRESS_2_WRITE(v, p)                      MWRITE_32((uint8_t *)p + 56, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_ADDRESS_3_READ(r, p)                       MREAD_32((uint8_t *)p + 60, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_BPM_BUFFER_ADDRESS_3_WRITE(v, p)                      MWRITE_32((uint8_t *)p + 60, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_REQUEST_ID_READ(r, p)                                 MREAD_32((uint8_t *)p + 64, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_REQUEST_ID_WRITE(v, p)                                MWRITE_32((uint8_t *)p + 64, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_DATA_BUF_PTR_READ(r, p)                               MREAD_32((uint8_t *)p + 68, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_DATA_BUF_PTR_WRITE(v, p)                              MWRITE_32((uint8_t *)p + 68, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_DHD_LIST_BASE_ADDRESS_READ(r, p)                      MREAD_32((uint8_t *)p + 72, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_DHD_LIST_BASE_ADDRESS_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 72, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_INGRESS_QUEUE_PD_WRITE_PTR_READ(r, p)                 MREAD_16((uint8_t *)p + 76, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_INGRESS_QUEUE_PD_WRITE_PTR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 76, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_INGRESS_QUEUE_PD_READ_PTR_READ(r, p)                  MREAD_16((uint8_t *)p + 78, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_INGRESS_QUEUE_PD_READ_PTR_WRITE(v, p)                 MWRITE_16((uint8_t *)p + 78, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_IS_PROXY_ENABLED_READ(r, p)                           MREAD_8((uint8_t *)p + 80, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_IS_PROXY_ENABLED_WRITE(v, p)                          MWRITE_8((uint8_t *)p + 80, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_DHD_LIST_SIZE_READ(r, p)                              MREAD_8((uint8_t *)p + 81, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_DHD_LIST_SIZE_WRITE(v, p)                             MWRITE_8((uint8_t *)p + 81, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_DHD_LIST_PTR_READ(r, p)                               MREAD_16((uint8_t *)p + 82, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_DHD_LIST_PTR_WRITE(v, p)                              MWRITE_16((uint8_t *)p + 82, v)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_DHD_LIST_TABLE_READ(r, p, i)                          MREAD_I_8((uint8_t *)p + 84, i, r)
+#define RDD_WLAN_MCAST_CONTROL_ENTRY_DHD_LIST_TABLE_WRITE(v, p, i)                         MWRITE_I_8((uint8_t *)p + 84, i, v)
+
+typedef struct
+{
+	uint32_t	valid_mask	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_WAN_UDP_FILTER_CONTROL_ENTRY_DTS;
+
+#define RDD_DS_WAN_UDP_FILTER_CONTROL_ENTRY_VALID_MASK_READ(r, p)                 MREAD_32((uint8_t *)p, r)
+#define RDD_DS_WAN_UDP_FILTER_CONTROL_ENTRY_VALID_MASK_WRITE(v, p)                MWRITE_32((uint8_t *)p, v)
+
+typedef struct
+{
+	uint32_t	tokens     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bucket     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bucket_size	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TOTAL_PPS_RATE_LIMITER_ENTRY_DTS;
+
+#define RDD_TOTAL_PPS_RATE_LIMITER_ENTRY_TOKENS_READ(r, p)                      MREAD_16((uint8_t *)p, r)
+#define RDD_TOTAL_PPS_RATE_LIMITER_ENTRY_TOKENS_WRITE(v, p)                     MWRITE_16((uint8_t *)p, v)
+#define RDD_TOTAL_PPS_RATE_LIMITER_ENTRY_BUCKET_READ(r, p)                      MREAD_16((uint8_t *)p + 2, r)
+#define RDD_TOTAL_PPS_RATE_LIMITER_ENTRY_BUCKET_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_TOTAL_PPS_RATE_LIMITER_ENTRY_BUCKET_SIZE_READ(r, p)                 MREAD_16((uint8_t *)p + 6, r)
+#define RDD_TOTAL_PPS_RATE_LIMITER_ENTRY_BUCKET_SIZE_WRITE(v, p)                MWRITE_16((uint8_t *)p + 6, v)
+
+typedef struct
+{
+	uint8_t	cpu_trap  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	drop      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	parameter 	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_FILTERS_PARAMETER_ENTRY_DTS;
+
+#define RDD_INGRESS_FILTERS_PARAMETER_ENTRY_CPU_TRAP_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_INGRESS_FILTERS_PARAMETER_ENTRY_CPU_TRAP_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_INGRESS_FILTERS_PARAMETER_ENTRY_DROP_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p, 6, 1, r)
+#define RDD_INGRESS_FILTERS_PARAMETER_ENTRY_DROP_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p, 6, 1, v)
+#define RDD_INGRESS_FILTERS_PARAMETER_ENTRY_PARAMETER_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 0, 6, r)
+#define RDD_INGRESS_FILTERS_PARAMETER_ENTRY_PARAMETER_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 0, 6, v)
+#if defined DSL_63138
+
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_PARAMETER_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE ][ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	allocated_budget	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	current_budget  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_LIMITER_REMAINDER_ENTRY_DTS;
+
+#define RDD_RATE_LIMITER_REMAINDER_ENTRY_ALLOCATED_BUDGET_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_RATE_LIMITER_REMAINDER_ENTRY_ALLOCATED_BUDGET_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+#define RDD_RATE_LIMITER_REMAINDER_ENTRY_CURRENT_BUDGET_READ(r, p)                   MREAD_8((uint8_t *)p + 1, r)
+#define RDD_RATE_LIMITER_REMAINDER_ENTRY_CURRENT_BUDGET_WRITE(v, p)                  MWRITE_8((uint8_t *)p + 1, v)
+#if defined DSL_63138
+
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_RATE_LIMITER_REMAINDER_ENTRY_DTS	entry[ RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_LIMITER_REMAINDER_TABLE_DTS;
+
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_PTR()	( RDD_RATE_LIMITER_REMAINDER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RATE_LIMITER_REMAINDER_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	vlan_index_table_ptr	:13	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	opbit_remark_mode   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipbit_remark_mode   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	qos_mapping_mode    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wifi_ssid           	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_port         	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	traffic_class       	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	forward_mode        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	service_queue_mode  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dest                	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = dest, size = 3 bits
+	uint32_t	subnet_id           	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	trap_reason         	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	drop                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cpu                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	policer_mode        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	policer_id          	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_shaping_mode   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cpu_mirroring       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	service_queue       	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dei_remark_enable   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dei_value           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ic_ip_flow          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_pbit          	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inner_pbit          	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dscp_remarking_mode 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dscp                	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ecn                 	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_VLAN_INDEX_TABLE_PTR_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p, 3, 13, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_VLAN_INDEX_TABLE_PTR_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p, 3, 13, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_OPBIT_REMARK_MODE_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 1, 2, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_OPBIT_REMARK_MODE_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 1, 2, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_IPBIT_REMARK_MODE_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 1, 1, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_IPBIT_REMARK_MODE_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 1, 1, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_QOS_MAPPING_MODE_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 1, 0, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_QOS_MAPPING_MODE_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 1, 0, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_WIFI_SSID_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 2, 4, 4, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_WIFI_SSID_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 2, 4, 4, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_EGRESS_PORT_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 2, 0, 4, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_EGRESS_PORT_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 2, 0, 4, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_TRAFFIC_CLASS_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 3, 5, 3, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_TRAFFIC_CLASS_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 3, 5, 3, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_FORWARD_MODE_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 3, 4, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_FORWARD_MODE_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 3, 4, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_SERVICE_QUEUE_MODE_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 3, 3, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_SERVICE_QUEUE_MODE_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 3, 3, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DEST_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 3, 0, 3, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DEST_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 3, 0, 3, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_SUBNET_ID_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 3, 1, 2, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_SUBNET_ID_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 3, 1, 2, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_TRAP_REASON_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 3, 0, 3, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_TRAP_REASON_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 3, 0, 3, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DROP_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DROP_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_CPU_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 4, 6, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_CPU_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 4, 6, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_POLICER_MODE_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 4, 5, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_POLICER_MODE_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 4, 5, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_POLICER_ID_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 4, 1, 4, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_POLICER_ID_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 4, 1, 4, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_RATE_SHAPING_MODE_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 4, 0, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_RATE_SHAPING_MODE_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 4, 0, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_CPU_MIRRORING_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 5, 7, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_CPU_MIRRORING_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 5, 7, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_SERVICE_QUEUE_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 5, 2, 5, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_SERVICE_QUEUE_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 5, 2, 5, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DEI_REMARK_ENABLE_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 5, 1, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DEI_REMARK_ENABLE_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 5, 1, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DEI_VALUE_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 5, 0, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DEI_VALUE_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 5, 0, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_IC_IP_FLOW_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 6, 7, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_IC_IP_FLOW_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 6, 7, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_OUTER_PBIT_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 6, 4, 3, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_OUTER_PBIT_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 6, 4, 3, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_INNER_PBIT_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 6, 1, 3, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_INNER_PBIT_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 6, 1, 3, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DSCP_REMARKING_MODE_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 6, 0, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DSCP_REMARKING_MODE_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 6, 0, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DSCP_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 7, 2, 6, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DSCP_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 7, 2, 6, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_ECN_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 7, 0, 2, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_ECN_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 7, 0, 2, v)
+#if defined DSL_63138
+
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+typedef struct
+{
+	RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved1    	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vid0         	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2    	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vid1         	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	context_index	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rx_if        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved4    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	next_entry   	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_sa        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_CONNECTION2_ENTRY_DTS;
+
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_VID0_READ(r, p)                          FIELD_MREAD_16((uint8_t *)p, 0, 12, r)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_VID0_WRITE(v, p)                         FIELD_MWRITE_16((uint8_t *)p, 0, 12, v)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_VID1_READ(r, p)                          FIELD_MREAD_16((uint8_t *)p + 2, 0, 12, r)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_VID1_WRITE(v, p)                         FIELD_MWRITE_16((uint8_t *)p + 2, 0, 12, v)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_VALID_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_VALID_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_CONTEXT_INDEX_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 4, 0, 15, r)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_CONTEXT_INDEX_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 4, 0, 15, v)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_RX_IF_READ(r, p)                         MREAD_8((uint8_t *)p + 6, r)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_RX_IF_WRITE(v, p)                        MWRITE_8((uint8_t *)p + 6, v)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_NEXT_ENTRY_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 7, 0, 7, r)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_NEXT_ENTRY_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 7, 0, 7, v)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_IP_SA_READ(r, p)                         MREAD_32((uint8_t *)p + 8, r)
+#define RDD_FC_MCAST_CONNECTION2_ENTRY_IP_SA_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 8, v)
+#if defined DSL_63138
+
+#define RDD_FC_MCAST_CONNECTION2_TABLE_SIZE     128
+typedef struct
+{
+	RDD_FC_MCAST_CONNECTION2_ENTRY_DTS	entry[ RDD_FC_MCAST_CONNECTION2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_CONNECTION2_TABLE_DTS;
+
+#define RDD_FC_MCAST_CONNECTION2_TABLE_PTR()	( RDD_FC_MCAST_CONNECTION2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + FC_MCAST_CONNECTION2_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	eth_mac_pointer 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_queue_pointer	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_QUEUE_POINTERS_ENTRY_DTS;
+
+#define RDD_ETH_TX_QUEUE_POINTERS_ENTRY_ETH_MAC_POINTER_READ(r, p)                  MREAD_16((uint8_t *)p, r)
+#define RDD_ETH_TX_QUEUE_POINTERS_ENTRY_ETH_MAC_POINTER_WRITE(v, p)                 MWRITE_16((uint8_t *)p, v)
+#define RDD_ETH_TX_QUEUE_POINTERS_ENTRY_TX_QUEUE_POINTER_READ(r, p)                 MREAD_16((uint8_t *)p + 2, r)
+#define RDD_ETH_TX_QUEUE_POINTERS_ENTRY_TX_QUEUE_POINTER_WRITE(v, p)                MWRITE_16((uint8_t *)p + 2, v)
+#if defined DSL_63138
+
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE     72
+typedef struct
+{
+	RDD_ETH_TX_QUEUE_POINTERS_ENTRY_DTS	entry[ RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_QUEUES_POINTERS_TABLE_DTS;
+
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_PTR()	( RDD_ETH_TX_QUEUES_POINTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_QUEUES_POINTERS_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved_0  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dst_mac     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dst_mac_lsw 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_1  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_2  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vtag0_tpid  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vtag0_tci   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vtag1_tpid  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vtag1_tci   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_mac     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_mac_lshw	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	eth_type    	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_L2_UCAST_TUPLE_ENTRY_DTS;
+
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_DST_MAC_READ(r, p)                      MREAD_16((uint8_t *)p + 2, r)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_DST_MAC_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_DST_MAC_LSW_READ(r, p)                  MREAD_32((uint8_t *)p + 4, r)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_DST_MAC_LSW_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_VTAG0_TPID_READ(r, p)                   MREAD_16((uint8_t *)p + 16, r)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_VTAG0_TPID_WRITE(v, p)                  MWRITE_16((uint8_t *)p + 16, v)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_VTAG0_TCI_READ(r, p)                    MREAD_16((uint8_t *)p + 18, r)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_VTAG0_TCI_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 18, v)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_VTAG1_TPID_READ(r, p)                   MREAD_16((uint8_t *)p + 20, r)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_VTAG1_TPID_WRITE(v, p)                  MWRITE_16((uint8_t *)p + 20, v)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_VTAG1_TCI_READ(r, p)                    MREAD_16((uint8_t *)p + 22, r)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_VTAG1_TCI_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 22, v)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_SRC_MAC_READ(r, p)                      MREAD_32((uint8_t *)p + 24, r)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_SRC_MAC_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 24, v)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_SRC_MAC_LSHW_READ(r, p)                 MREAD_16((uint8_t *)p + 28, r)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_SRC_MAC_LSHW_WRITE(v, p)                MWRITE_16((uint8_t *)p + 28, v)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_ETH_TYPE_READ(r, p)                     MREAD_16((uint8_t *)p + 30, r)
+#define RDD_FC_L2_UCAST_TUPLE_ENTRY_ETH_TYPE_WRITE(v, p)                    MWRITE_16((uint8_t *)p + 30, v)
+#if defined DSL_63138
+
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_SBPM_REPLY_ENTRY_RESERVED_FW_ONLY_NUMBER	32
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_SBPM_REPLY_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SBPM_REPLY_ENTRY_DTS;
+
+
+typedef struct
+{
+	uint32_t	head_ptr              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tail_ptr              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ingress_packet_counter	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_packet_counter 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_threshold      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	profile_ptr           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rs_status_offset      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rs_group_status_offset	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	queue_mask            	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	index                 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_QUEUE_DESCRIPTOR_DTS;
+
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_HEAD_PTR_READ(r, p)                               MREAD_16((uint8_t *)p, r)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_HEAD_PTR_WRITE(v, p)                              MWRITE_16((uint8_t *)p, v)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_TAIL_PTR_READ(r, p)                               MREAD_16((uint8_t *)p + 2, r)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_TAIL_PTR_WRITE(v, p)                              MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_INGRESS_PACKET_COUNTER_READ(r, p)                 MREAD_16((uint8_t *)p + 4, r)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_INGRESS_PACKET_COUNTER_WRITE(v, p)                MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_EGRESS_PACKET_COUNTER_READ(r, p)                  MREAD_16((uint8_t *)p + 6, r)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_EGRESS_PACKET_COUNTER_WRITE(v, p)                 MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_PACKET_THRESHOLD_READ(r, p)                       MREAD_16((uint8_t *)p + 8, r)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_PACKET_THRESHOLD_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_PROFILE_PTR_READ(r, p)                            MREAD_16((uint8_t *)p + 10, r)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_PROFILE_PTR_WRITE(v, p)                           MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_RS_STATUS_OFFSET_READ(r, p)                       MREAD_8((uint8_t *)p + 12, r)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_RS_STATUS_OFFSET_WRITE(v, p)                      MWRITE_8((uint8_t *)p + 12, v)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_RS_GROUP_STATUS_OFFSET_READ(r, p)                 MREAD_8((uint8_t *)p + 13, r)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_RS_GROUP_STATUS_OFFSET_WRITE(v, p)                MWRITE_8((uint8_t *)p + 13, v)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_QUEUE_MASK_READ(r, p)                             MREAD_8((uint8_t *)p + 14, r)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_QUEUE_MASK_WRITE(v, p)                            MWRITE_8((uint8_t *)p + 14, v)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_INDEX_READ(r, p)                                  MREAD_8((uint8_t *)p + 15, r)
+#define RDD_ETH_TX_QUEUE_DESCRIPTOR_INDEX_WRITE(v, p)                                 MWRITE_8((uint8_t *)p + 15, v)
+#if defined DSL_63138
+
+#define RDD_ETH_TX_QUEUES_TABLE_SIZE     72
+typedef struct
+{
+	RDD_ETH_TX_QUEUE_DESCRIPTOR_DTS	entry[ RDD_ETH_TX_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_QUEUES_TABLE_DTS;
+
+#define RDD_ETH_TX_QUEUES_TABLE_PTR()	( RDD_ETH_TX_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_QUEUES_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	l4_protocol         	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ptag                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	number_of_vlans     	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	broadcast           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l3_protocol         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_protocol         	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l4_protocol_mask    	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error_mask          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ptag_mask           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	number_of_vlans_mask	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	broadcast_mask      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast_mask      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l3_protocol_mask    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_protocol_mask    	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_FILTERS_LOOKUP_ENTRY_DTS;
+
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L4_PROTOCOL_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p, 4, 4, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L4_PROTOCOL_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p, 4, 4, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_ERROR_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p, 3, 1, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_ERROR_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p, 3, 1, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_PTAG_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p, 2, 1, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_PTAG_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p, 2, 1, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_NUMBER_OF_VLANS_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p, 0, 2, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_NUMBER_OF_VLANS_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p, 0, 2, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_BROADCAST_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 1, 7, 1, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_BROADCAST_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 1, 7, 1, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_MULTICAST_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 1, 6, 1, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_MULTICAST_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 1, 6, 1, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L3_PROTOCOL_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 1, 4, 2, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L3_PROTOCOL_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 1, 4, 2, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L2_PROTOCOL_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 1, 0, 4, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L2_PROTOCOL_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 1, 0, 4, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L4_PROTOCOL_MASK_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 2, 4, 4, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L4_PROTOCOL_MASK_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 2, 4, 4, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_ERROR_MASK_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 2, 3, 1, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_ERROR_MASK_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 2, 3, 1, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_PTAG_MASK_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 2, 2, 1, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_PTAG_MASK_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 2, 2, 1, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_NUMBER_OF_VLANS_MASK_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 2, 0, 2, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_NUMBER_OF_VLANS_MASK_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 2, 0, 2, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_BROADCAST_MASK_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 3, 7, 1, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_BROADCAST_MASK_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 3, 7, 1, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_MULTICAST_MASK_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 3, 6, 1, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_MULTICAST_MASK_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 3, 6, 1, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L3_PROTOCOL_MASK_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 3, 4, 2, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L3_PROTOCOL_MASK_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 3, 4, 2, v)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L2_PROTOCOL_MASK_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 3, 0, 4, r)
+#define RDD_INGRESS_FILTERS_LOOKUP_ENTRY_L2_PROTOCOL_MASK_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 3, 0, 4, v)
+#if defined DSL_63138
+
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_LOOKUP_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE ][ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	enable    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FORWARDING_MATRIX_ENTRY_DTS;
+
+#define RDD_FORWARDING_MATRIX_ENTRY_ENABLE_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_FORWARDING_MATRIX_ENTRY_ENABLE_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+#if defined DSL_63138
+
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_FORWARDING_MATRIX_ENTRY_DTS	entry[ RDD_DS_FORWARDING_MATRIX_TABLE_SIZE ][ RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FORWARDING_MATRIX_TABLE_DTS;
+
+#define RDD_DS_FORWARDING_MATRIX_TABLE_PTR()	( RDD_DS_FORWARDING_MATRIX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FORWARDING_MATRIX_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	valid                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	context_index          	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bucket_overflow_counter	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command_list_length_64 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_extend             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_multicast           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	protocol               	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved               	:23	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_pure_ack           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tos                    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_mac_crc            	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dst_mac_crc            	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_L2_UCAST_CONNECTION_ENTRY_DTS;
+
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_VALID_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_VALID_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_CONTEXT_INDEX_READ(r, p)                           FIELD_MREAD_16((uint8_t *)p, 0, 15, r)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_CONTEXT_INDEX_WRITE(v, p)                          FIELD_MWRITE_16((uint8_t *)p, 0, 15, v)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_BUCKET_OVERFLOW_COUNTER_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 2, 5, 3, r)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_BUCKET_OVERFLOW_COUNTER_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 2, 5, 3, v)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_COMMAND_LIST_LENGTH_64_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 2, 1, 4, r)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_COMMAND_LIST_LENGTH_64_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 2, 1, 4, v)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_KEY_EXTEND_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 2, 0, 1, r)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_KEY_EXTEND_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 2, 0, 1, v)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_IS_MULTICAST_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 3, 7, 1, r)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_IS_MULTICAST_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 3, 7, 1, v)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_PROTOCOL_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 3, 0, 7, r)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_PROTOCOL_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 3, 0, 7, v)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_TCP_PURE_ACK_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 6, 0, 1, r)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_TCP_PURE_ACK_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 6, 0, 1, v)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_TOS_READ(r, p)                                     MREAD_8((uint8_t *)p + 7, r)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_TOS_WRITE(v, p)                                    MWRITE_8((uint8_t *)p + 7, v)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_SRC_MAC_CRC_READ(r, p)                             MREAD_32((uint8_t *)p + 8, r)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_SRC_MAC_CRC_WRITE(v, p)                            MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_DST_MAC_CRC_READ(r, p)                             MREAD_32((uint8_t *)p + 12, r)
+#define RDD_FC_L2_UCAST_CONNECTION_ENTRY_DST_MAC_CRC_WRITE(v, p)                            MWRITE_32((uint8_t *)p + 12, v)
+
+typedef struct
+{
+	uint32_t	generic_rule_type  	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1          	:23	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	generic_rule_offset	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	generic_rule_mask  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_DTS;
+
+#define RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_GENERIC_RULE_TYPE_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p, 6, 2, r)
+#define RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_GENERIC_RULE_TYPE_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p, 6, 2, v)
+#define RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_GENERIC_RULE_OFFSET_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 3, 0, 7, r)
+#define RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_GENERIC_RULE_OFFSET_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 3, 0, 7, v)
+#define RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_GENERIC_RULE_MASK_READ(r, p)                   MREAD_32((uint8_t *)p + 4, r)
+#define RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_GENERIC_RULE_MASK_WRITE(v, p)                  MWRITE_32((uint8_t *)p + 4, v)
+#if defined DSL_63138
+
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_L2_UCAST_CONNECTION_BUFFER_SIZE     4
+typedef struct
+{
+	RDD_FC_L2_UCAST_CONNECTION_ENTRY_DTS	entry[ RDD_DS_L2_UCAST_CONNECTION_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_L2_UCAST_CONNECTION_BUFFER_DTS;
+
+#define RDD_DS_L2_UCAST_CONNECTION_BUFFER_PTR()	( RDD_DS_L2_UCAST_CONNECTION_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_L2_UCAST_CONNECTION_BUFFER_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	egress_counter              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0                   	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ingress_counter             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_limiter_id             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_task_number              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	emac_mask                   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_queues_status            	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	gpio_flow_control_vector_ptr	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_counters_ptr_0       	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2                   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbh_destination_0           	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_counters_ptr_1       	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3                   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbh_destination_1           	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_counters_ptr_2       	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved4                   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbh_destination_2           	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_port                 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved5                   	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved6                   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_MAC_DESCRIPTOR_DTS;
+
+#define RDD_ETH_TX_MAC_DESCRIPTOR_EGRESS_COUNTER_READ(r, p)                               MREAD_8((uint8_t *)p, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_EGRESS_COUNTER_WRITE(v, p)                              MWRITE_8((uint8_t *)p, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_INGRESS_COUNTER_READ(r, p)                              MREAD_8((uint8_t *)p + 4, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_INGRESS_COUNTER_WRITE(v, p)                             MWRITE_8((uint8_t *)p + 4, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_RATE_LIMITER_ID_READ(r, p)                              MREAD_8((uint8_t *)p + 5, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_RATE_LIMITER_ID_WRITE(v, p)                             MWRITE_8((uint8_t *)p + 5, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_TX_TASK_NUMBER_READ(r, p)                               MREAD_8((uint8_t *)p + 6, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_TX_TASK_NUMBER_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 6, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_EMAC_MASK_READ(r, p)                                    MREAD_8((uint8_t *)p + 8, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_EMAC_MASK_WRITE(v, p)                                   MWRITE_8((uint8_t *)p + 8, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_TX_QUEUES_STATUS_READ(r, p)                             MREAD_8((uint8_t *)p + 9, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_TX_QUEUES_STATUS_WRITE(v, p)                            MWRITE_8((uint8_t *)p + 9, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_GPIO_FLOW_CONTROL_VECTOR_PTR_READ(r, p)                 MREAD_16((uint8_t *)p + 10, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_GPIO_FLOW_CONTROL_VECTOR_PTR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_PACKET_COUNTERS_PTR_0_READ(r, p)                        MREAD_16((uint8_t *)p + 12, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_PACKET_COUNTERS_PTR_0_WRITE(v, p)                       MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_BBH_DESTINATION_0_READ(r, p)                            MREAD_8((uint8_t *)p + 15, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_BBH_DESTINATION_0_WRITE(v, p)                           MWRITE_8((uint8_t *)p + 15, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_PACKET_COUNTERS_PTR_1_READ(r, p)                        MREAD_16((uint8_t *)p + 16, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_PACKET_COUNTERS_PTR_1_WRITE(v, p)                       MWRITE_16((uint8_t *)p + 16, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_BBH_DESTINATION_1_READ(r, p)                            MREAD_8((uint8_t *)p + 19, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_BBH_DESTINATION_1_WRITE(v, p)                           MWRITE_8((uint8_t *)p + 19, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_PACKET_COUNTERS_PTR_2_READ(r, p)                        MREAD_16((uint8_t *)p + 20, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_PACKET_COUNTERS_PTR_2_WRITE(v, p)                       MWRITE_16((uint8_t *)p + 20, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_BBH_DESTINATION_2_READ(r, p)                            MREAD_8((uint8_t *)p + 23, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_BBH_DESTINATION_2_WRITE(v, p)                           MWRITE_8((uint8_t *)p + 23, v)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_EGRESS_PORT_READ(r, p)                                  MREAD_8((uint8_t *)p + 24, r)
+#define RDD_ETH_TX_MAC_DESCRIPTOR_EGRESS_PORT_WRITE(v, p)                                 MWRITE_8((uint8_t *)p + 24, v)
+#if defined DSL_63138
+
+#define RDD_ETH_TX_MAC_TABLE_SIZE     10
+typedef struct
+{
+	RDD_ETH_TX_MAC_DESCRIPTOR_DTS	entry[ RDD_ETH_TX_MAC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_MAC_TABLE_DTS;
+
+#define RDD_ETH_TX_MAC_TABLE_PTR()	( RDD_ETH_TX_MAC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_MAC_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	msg_type        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	if_id           	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	common_hdr_flags	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	epoch           	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	request_id      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	status          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_id    	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dma_done_mark   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_DESCRIPTOR_DTS;
+
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_MSG_TYPE_READ(r, p)                         MREAD_8((uint8_t *)p, r)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_MSG_TYPE_WRITE(v, p)                        MWRITE_8((uint8_t *)p, v)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_MSG_TYPE_L_READ( wv )                       FIELD_GET( wv, 24, 8 )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_MSG_TYPE_L_WRITE( v, wv )                   FIELD_SET( v, 24, 8, wv )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_IF_ID_READ(r, p)                            MREAD_8((uint8_t *)p + 1, r)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_IF_ID_WRITE(v, p)                           MWRITE_8((uint8_t *)p + 1, v)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_IF_ID_L_READ( wv )                          FIELD_GET( wv, 16, 8 )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_IF_ID_L_WRITE( v, wv )                      FIELD_SET( v, 16, 8, wv )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_COMMON_HDR_FLAGS_READ(r, p)                 MREAD_8((uint8_t *)p + 2, r)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_COMMON_HDR_FLAGS_WRITE(v, p)                MWRITE_8((uint8_t *)p + 2, v)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_COMMON_HDR_FLAGS_L_READ( wv )               FIELD_GET( wv, 8, 8 )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_COMMON_HDR_FLAGS_L_WRITE( v, wv )           FIELD_SET( v, 8, 8, wv )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_EPOCH_READ(r, p)                            MREAD_8((uint8_t *)p + 3, r)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_EPOCH_WRITE(v, p)                           MWRITE_8((uint8_t *)p + 3, v)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_EPOCH_L_READ( wv )                          FIELD_GET( wv, 0, 8 )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_EPOCH_L_WRITE( v, wv )                      FIELD_SET( v, 0, 8, wv )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_REQUEST_ID_READ(r, p)                       MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_REQUEST_ID_WRITE(v, p)                      MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_REQUEST_ID_L_READ( wv )                     FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_REQUEST_ID_L_WRITE( v, wv )                 FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_STATUS_READ(r, p)                           MREAD_16((uint8_t *)p + 8, r)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_STATUS_WRITE(v, p)                          MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_STATUS_L_READ( wv )                         FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_STATUS_L_WRITE( v, wv )                     FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_FLOW_RING_ID_READ(r, p)                     MREAD_16((uint8_t *)p + 10, r)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_FLOW_RING_ID_WRITE(v, p)                    MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_FLOW_RING_ID_L_READ( wv )                   FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_FLOW_RING_ID_L_WRITE( v, wv )               FIELD_SET( v, 0, 16, wv )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_DMA_DONE_MARK_READ(r, p)                    MREAD_32((uint8_t *)p + 12, r)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_DMA_DONE_MARK_WRITE(v, p)                   MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_DMA_DONE_MARK_L_READ( wv )                  FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_DMA_DONE_MARK_L_WRITE( v, wv )              FIELD_SET( v, 0, 32, wv )
+
+typedef struct
+{
+	uint32_t	request_id  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_id	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	if_id       	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_DTS;
+
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_REQUEST_ID_READ(r, p)                   MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_REQUEST_ID_WRITE(v, p)                  MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_REQUEST_ID_L_READ( wv )                 FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_REQUEST_ID_L_WRITE( v, wv )             FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_FLOW_RING_ID_READ(r, p)                 MREAD_16((uint8_t *)p + 4, r)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_FLOW_RING_ID_WRITE(v, p)                MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_FLOW_RING_ID_L_READ( wv )               FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_FLOW_RING_ID_L_WRITE( v, wv )           FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_IF_ID_READ(r, p)                        MREAD_8((uint8_t *)p + 6, r)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_IF_ID_WRITE(v, p)                       MWRITE_8((uint8_t *)p + 6, v)
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_IF_ID_L_READ( wv )                      FIELD_GET( wv, 8, 8 )
+#define RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_IF_ID_L_WRITE( v, wv )                  FIELD_SET( v, 8, 8, wv )
+#if defined DSL_63138
+
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_PTR()	( RDD_RUNNER_FWTRACE_MAINA_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RUNNER_FWTRACE_MAINA_PARAM_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved_fw_only	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FOUR_BYTES_DTS;
+
+#if defined DSL_63138
+
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_HANDLER_SKB_DATA_POINTER_DTS;
+
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_PTR()	( RDD_INGRESS_HANDLER_SKB_DATA_POINTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	reserved_fw_only	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ONE_BYTE_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	ring_ptr  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ring_size 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ring_base 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ring_end  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_COMPLETE_RING_DESCRIPTOR_DTS;
+
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_RING_PTR_READ(r, p)                  MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_RING_PTR_WRITE(v, p)                 MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_RING_SIZE_READ(r, p)                 MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_RING_SIZE_WRITE(v, p)                MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_RING_BASE_READ(r, p)                 MREAD_32((uint8_t *)p + 8, r)
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_RING_BASE_WRITE(v, p)                MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_RING_END_READ(r, p)                  MREAD_32((uint8_t *)p + 12, r)
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_RING_END_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 12, v)
+#if defined DSL_63138
+
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_COMPLETE_RING_DESCRIPTOR_DTS	entry[ RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_DTS;
+
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_PTR()	( RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOA_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_PTR()	( RDD_RUNNER_FWTRACE_PICOA_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RUNNER_FWTRACE_PICOA_PARAM_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	current_budget      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	budget_limit_exp    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	budget_limit        	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocated_budget_exp	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocated_budget    	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_LIMITER_ENTRY_DTS;
+
+#define RDD_RATE_LIMITER_ENTRY_CURRENT_BUDGET_READ(r, p)                       MREAD_32((uint8_t *)p, r)
+#define RDD_RATE_LIMITER_ENTRY_CURRENT_BUDGET_WRITE(v, p)                      MWRITE_32((uint8_t *)p, v)
+#define RDD_RATE_LIMITER_ENTRY_BUDGET_LIMIT_EXP_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_RATE_LIMITER_ENTRY_BUDGET_LIMIT_EXP_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_RATE_LIMITER_ENTRY_BUDGET_LIMIT_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p + 4, 0, 15, r)
+#define RDD_RATE_LIMITER_ENTRY_BUDGET_LIMIT_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p + 4, 0, 15, v)
+#define RDD_RATE_LIMITER_ENTRY_ALLOCATED_BUDGET_EXP_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 6, 7, 1, r)
+#define RDD_RATE_LIMITER_ENTRY_ALLOCATED_BUDGET_EXP_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 6, 7, 1, v)
+#define RDD_RATE_LIMITER_ENTRY_ALLOCATED_BUDGET_READ(r, p)                     FIELD_MREAD_16((uint8_t *)p + 6, 0, 15, r)
+#define RDD_RATE_LIMITER_ENTRY_ALLOCATED_BUDGET_WRITE(v, p)                    FIELD_MWRITE_16((uint8_t *)p + 6, 0, 15, v)
+#if defined DSL_63138
+
+#define RDD_DS_RATE_LIMITER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_RATE_LIMITER_ENTRY_DTS	entry[ RDD_DS_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_DS_RATE_LIMITER_TABLE_PTR()	( RDD_DS_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	reserved             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	cpu_reason           	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	ingress_classify_mode	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	ingress_flow         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_WAN_FLOW_ENTRY_DTS;
+
+#define RDD_DS_WAN_FLOW_ENTRY_CPU_REASON_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p, 1, 6, r)
+#define RDD_DS_WAN_FLOW_ENTRY_CPU_REASON_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p, 1, 6, v)
+#define RDD_DS_WAN_FLOW_ENTRY_INGRESS_CLASSIFY_MODE_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 0, 1, r)
+#define RDD_DS_WAN_FLOW_ENTRY_INGRESS_CLASSIFY_MODE_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 0, 1, v)
+#define RDD_DS_WAN_FLOW_ENTRY_INGRESS_FLOW_READ(r, p)                          MREAD_8((uint8_t *)p + 1, r)
+#define RDD_DS_WAN_FLOW_ENTRY_INGRESS_FLOW_WRITE(v, p)                         MWRITE_8((uint8_t *)p + 1, v)
+#if defined DSL_63138
+
+#define RDD_DS_WAN_FLOW_TABLE_SIZE     256
+typedef struct
+{
+	RDD_DS_WAN_FLOW_ENTRY_DTS	entry[ RDD_DS_WAN_FLOW_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_WAN_FLOW_TABLE_DTS;
+
+#define RDD_DS_WAN_FLOW_TABLE_PTR()	( RDD_DS_WAN_FLOW_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_WAN_FLOW_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	offset    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	value     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mask      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	hits      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_WAN_UDP_FILTER_ENTRY_DTS;
+
+#define RDD_DS_WAN_UDP_FILTER_ENTRY_OFFSET_READ(r, p)                 MREAD_32((uint8_t *)p, r)
+#define RDD_DS_WAN_UDP_FILTER_ENTRY_OFFSET_WRITE(v, p)                MWRITE_32((uint8_t *)p, v)
+#define RDD_DS_WAN_UDP_FILTER_ENTRY_VALUE_READ(r, p)                  MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DS_WAN_UDP_FILTER_ENTRY_VALUE_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DS_WAN_UDP_FILTER_ENTRY_MASK_READ(r, p)                   MREAD_32((uint8_t *)p + 8, r)
+#define RDD_DS_WAN_UDP_FILTER_ENTRY_MASK_WRITE(v, p)                  MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_DS_WAN_UDP_FILTER_ENTRY_HITS_READ(r, p)                   MREAD_32((uint8_t *)p + 12, r)
+#define RDD_DS_WAN_UDP_FILTER_ENTRY_HITS_WRITE(v, p)                  MWRITE_32((uint8_t *)p + 12, v)
+#if defined DSL_63138
+
+#define RDD_DS_WAN_UDP_FILTER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DS_WAN_UDP_FILTER_ENTRY_DTS	entry[ RDD_DS_WAN_UDP_FILTER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_WAN_UDP_FILTER_TABLE_DTS;
+
+#define RDD_DS_WAN_UDP_FILTER_TABLE_PTR()	( RDD_DS_WAN_UDP_FILTER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_WAN_UDP_FILTER_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	u8        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_PORT_HEADER_ENTRY_DTS;
+
+#define RDD_FC_MCAST_PORT_HEADER_ENTRY_U8_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_FC_MCAST_PORT_HEADER_ENTRY_U8_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+#if defined DSL_63138
+
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE     8
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2    64
+typedef struct
+{
+	RDD_FC_MCAST_PORT_HEADER_ENTRY_DTS	entry[ RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE ][ RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_PORT_HEADER_BUFFER_DTS;
+
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_PTR()	( RDD_FC_MCAST_PORT_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + FC_MCAST_PORT_HEADER_BUFFER_ADDRESS )
+
+#endif
+#define RDD_CONNECTION_CONTEXT_MULTICAST_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER	16
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_CONNECTION_CONTEXT_MULTICAST_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONNECTION_CONTEXT_MULTICAST_BUFFER_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_MULTICAST_BUFFER_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_PTR()	( RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+typedef struct
+{
+	uint32_t	last_sbn        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	fstat_cell      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_id         	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length   	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	fstat_error     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error_type      	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ih_buffer_number	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number   	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_RX_DESCRIPTOR_DTS;
+
+#define RDD_BBH_RX_DESCRIPTOR_LAST_SBN_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p, 6, 10, r)
+#define RDD_BBH_RX_DESCRIPTOR_LAST_SBN_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p, 6, 10, v)
+#define RDD_BBH_RX_DESCRIPTOR_FSTAT_CELL_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 1, 5, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_FSTAT_CELL_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 1, 5, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_FLOW_ID_READ(r, p)                          FIELD_MREAD_32((uint8_t *)p + 0, 14, 7, r)
+#define RDD_BBH_RX_DESCRIPTOR_FLOW_ID_WRITE(v, p)                         FIELD_MWRITE_32((uint8_t *)p + 0, 14, 7, v)
+#define RDD_BBH_RX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 2, 0, 14, r)
+#define RDD_BBH_RX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 2, 0, 14, v)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_FSTAT_ERROR_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 4, 5, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_FSTAT_ERROR_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 4, 5, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_TYPE_READ(r, p)                       FIELD_MREAD_16((uint8_t *)p + 4, 6, 7, r)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_TYPE_WRITE(v, p)                      FIELD_MWRITE_16((uint8_t *)p + 4, 6, 7, v)
+#define RDD_BBH_RX_DESCRIPTOR_IH_BUFFER_NUMBER_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 5, 0, 6, r)
+#define RDD_BBH_RX_DESCRIPTOR_IH_BUFFER_NUMBER_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 5, 0, 6, v)
+#define RDD_BBH_RX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 6, 7, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 6, 7, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 6, 0, 15, r)
+#define RDD_BBH_RX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 6, 0, 15, v)
+#endif
+#if defined DSL_63138
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE     64
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_DTS;
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_PTR()	( RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_LAN_ENQUEUE_SQ_PD_ADDRESS )
+
+#endif
+#define RDD_ETH_RX_DESCRIPTORS_RESERVED_FW_ONLY_NUMBER	2
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_ETH_RX_DESCRIPTORS_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_RX_DESCRIPTORS_DTS;
+
+#if defined DSL_63138
+
+#define RDD_ETH0_RX_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_ETH0_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH0_RX_DESCRIPTORS_DTS;
+
+#define RDD_ETH0_RX_DESCRIPTORS_PTR()	( RDD_ETH0_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH0_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+#define RDD_RUNNER_FLOW_HEADER_BUFFER_RESERVED_FW_ONLY_NUMBER	32
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_RUNNER_FLOW_HEADER_BUFFER_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FLOW_HEADER_BUFFER_DTS;
+
+#define RDD_GRE_RUNNER_FLOW_HEADER_BUFFER_RESERVED_FW_ONLY_NUMBER	32
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_GRE_RUNNER_FLOW_HEADER_BUFFER_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GRE_RUNNER_FLOW_HEADER_BUFFER_DTS;
+
+#if defined DSL_63138
+
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_SQ_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#define RDD_CPU_TX_BBH_DESCRIPTORS_ENTRY_RESERVED_FW_ONLY_NUMBER	2
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_CPU_TX_BBH_DESCRIPTORS_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_BBH_DESCRIPTORS_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_CPU_TX_BBH_DESCRIPTORS_ENTRY_DTS	entry[ RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_TX_BBH_DESCRIPTORS_DTS;
+
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_PTR()	( RDD_DS_CPU_TX_BBH_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_TX_BBH_DESCRIPTORS_ADDRESS )
+
+#endif
+#define RDD_PROFILING_BUFFER_PICO_RUNNER_RESERVED_FW_ONLY_NUMBER	64
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_PROFILING_BUFFER_PICO_RUNNER_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PROFILING_BUFFER_PICO_RUNNER_DTS;
+
+
+typedef struct
+{
+	uint32_t	reserved0 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_DTS;
+
+
+typedef struct
+{
+	uint32_t	valid            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command          	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_wred_high_prio	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	gso              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	emac             	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_queue         	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_bridge_port  	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	abs_flag         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	lag_port_pti     	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	message_parameter	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_offset   	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_CORE_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_CORE_VALID_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_VALID_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_VALID_L_READ( wv )                           FIELD_GET( wv, 31, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_VALID_L_WRITE( v, wv )                       FIELD_SET( v, 31, 1, wv )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_COMMAND_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p, 4, 3, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_COMMAND_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p, 4, 3, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_COMMAND_L_READ( wv )                         FIELD_GET( wv, 28, 3 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_COMMAND_L_WRITE( v, wv )                     FIELD_SET( v, 28, 3, wv )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_IS_WRED_HIGH_PRIO_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 3, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_IS_WRED_HIGH_PRIO_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 3, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_IS_WRED_HIGH_PRIO_L_READ( wv )               FIELD_GET( wv, 27, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_IS_WRED_HIGH_PRIO_L_WRITE( v, wv )           FIELD_SET( v, 27, 1, wv )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_GSO_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p, 2, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_GSO_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p, 2, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_GSO_L_READ( wv )                             FIELD_GET( wv, 26, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_GSO_L_WRITE( v, wv )                         FIELD_SET( v, 26, 1, wv )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_EMAC_READ(r, p)                              FIELD_MREAD_16((uint8_t *)p, 6, 4, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_EMAC_WRITE(v, p)                             FIELD_MWRITE_16((uint8_t *)p, 6, 4, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_EMAC_L_READ( wv )                            FIELD_GET( wv, 22, 4 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_EMAC_L_WRITE( v, wv )                        FIELD_SET( v, 22, 4, wv )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_TX_QUEUE_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 1, 3, 3, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_TX_QUEUE_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 1, 3, 3, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_TX_QUEUE_L_READ( wv )                        FIELD_GET( wv, 19, 3 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_TX_QUEUE_L_WRITE( v, wv )                    FIELD_SET( v, 19, 3, wv )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_SRC_BRIDGE_PORT_READ(r, p)                   FIELD_MREAD_32((uint8_t *)p + 0, 14, 5, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_SRC_BRIDGE_PORT_WRITE(v, p)                  FIELD_MWRITE_32((uint8_t *)p + 0, 14, 5, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_SRC_BRIDGE_PORT_L_READ( wv )                 FIELD_GET( wv, 14, 5 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_SRC_BRIDGE_PORT_L_WRITE( v, wv )             FIELD_SET( v, 14, 5, wv )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_PACKET_LENGTH_READ(r, p)                     FIELD_MREAD_16((uint8_t *)p + 2, 0, 14, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_PACKET_LENGTH_WRITE(v, p)                    FIELD_MWRITE_16((uint8_t *)p + 2, 0, 14, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_PACKET_LENGTH_L_READ( wv )                   FIELD_GET( wv, 0, 14 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_PACKET_LENGTH_L_WRITE( v, wv )               FIELD_SET( v, 0, 14, wv )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_ABS_FLAG_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_ABS_FLAG_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_ABS_FLAG_L_READ( wv )                        FIELD_GET( wv, 31, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_ABS_FLAG_L_WRITE( v, wv )                    FIELD_SET( v, 31, 1, wv )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_LAG_PORT_PTI_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 4, 4, 2, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_LAG_PORT_PTI_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 4, 4, 2, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_LAG_PORT_PTI_L_READ( wv )                    FIELD_GET( wv, 28, 2 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_LAG_PORT_PTI_L_WRITE( v, wv )                FIELD_SET( v, 28, 2, wv )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_MESSAGE_PARAMETER_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 4, 7, 5, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_MESSAGE_PARAMETER_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 4, 7, 5, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_MESSAGE_PARAMETER_L_READ( wv )               FIELD_GET( wv, 23, 5 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_MESSAGE_PARAMETER_L_WRITE( v, wv )           FIELD_SET( v, 23, 5, wv )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_PAYLOAD_OFFSET_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 5, 0, 7, r)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_PAYLOAD_OFFSET_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 5, 0, 7, v)
+#define RDD_CPU_TX_DESCRIPTOR_CORE_PAYLOAD_OFFSET_L_READ( wv )                  FIELD_GET( wv, 16, 7 )
+#define RDD_CPU_TX_DESCRIPTOR_CORE_PAYLOAD_OFFSET_L_WRITE( v, wv )              FIELD_SET( v, 16, 7, wv )
+#if defined DSL_63138
+
+typedef struct
+{
+	uint32_t	reserved0    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1    	:17	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_BPM_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 6, 0, 15, r)
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 6, 0, 15, v)
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_L_READ( wv )               FIELD_GET( wv, 0, 15 )
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_L_WRITE( v, wv )           FIELD_SET( v, 0, 15, wv )
+#endif
+
+typedef struct
+{
+	uint32_t	reserved0 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1 	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	skb_index 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_ABS_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_ABS_SKB_INDEX_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_SKB_INDEX_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_SKB_INDEX_L_READ( wv )               FIELD_GET( wv, 0, 14 )
+#define RDD_CPU_TX_DESCRIPTOR_ABS_SKB_INDEX_L_WRITE( v, wv )           FIELD_SET( v, 0, 14, wv )
+
+typedef struct
+{
+	uint32_t	reserved0          	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	downstream_wan_flow	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1          	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_DS_FAST_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_DS_FAST_DOWNSTREAM_WAN_FLOW_READ(r, p)                 FIELD_MREAD_32((uint8_t *)p + 0, 14, 8, r)
+#define RDD_CPU_TX_DESCRIPTOR_DS_FAST_DOWNSTREAM_WAN_FLOW_WRITE(v, p)                FIELD_MWRITE_32((uint8_t *)p + 0, 14, 8, v)
+#define RDD_CPU_TX_DESCRIPTOR_DS_FAST_DOWNSTREAM_WAN_FLOW_L_READ( wv )               FIELD_GET( wv, 14, 8 )
+#define RDD_CPU_TX_DESCRIPTOR_DS_FAST_DOWNSTREAM_WAN_FLOW_L_WRITE( v, wv )           FIELD_SET( v, 14, 8, wv )
+
+typedef struct
+{
+	uint32_t	reserved0        	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_wred_high_prio	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	upstream_gem_flow	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1        	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_queue         	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2        	:23	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_US_FAST_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_IS_WRED_HIGH_PRIO_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 3, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_IS_WRED_HIGH_PRIO_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 3, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_IS_WRED_HIGH_PRIO_L_READ( wv )               FIELD_GET( wv, 27, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_IS_WRED_HIGH_PRIO_L_WRITE( v, wv )           FIELD_SET( v, 27, 1, wv )
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_UPSTREAM_GEM_FLOW_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p, 3, 8, r)
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_UPSTREAM_GEM_FLOW_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p, 3, 8, v)
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_UPSTREAM_GEM_FLOW_L_READ( wv )               FIELD_GET( wv, 19, 8 )
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_UPSTREAM_GEM_FLOW_L_WRITE( v, wv )           FIELD_SET( v, 19, 8, wv )
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_TX_QUEUE_READ(r, p)                          FIELD_MREAD_16((uint8_t *)p + 4, 7, 9, r)
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_TX_QUEUE_WRITE(v, p)                         FIELD_MWRITE_16((uint8_t *)p + 4, 7, 9, v)
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_TX_QUEUE_L_READ( wv )                        FIELD_GET( wv, 23, 9 )
+#define RDD_CPU_TX_DESCRIPTOR_US_FAST_TX_QUEUE_L_WRITE( v, wv )                    FIELD_SET( v, 23, 9, wv )
+
+typedef struct
+{
+	uint32_t	reserved0 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	en_1588   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2 	:27	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_DS_PICO_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_EN_1588_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 4, 3, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_EN_1588_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 4, 3, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_EN_1588_L_READ( wv )                 FIELD_GET( wv, 27, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_EN_1588_L_WRITE( v, wv )             FIELD_SET( v, 27, 1, wv )
+
+typedef struct
+{
+	uint32_t	reserved0     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ssid_multicast	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ssid          	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2     	:26	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_SSID_MULTICAST_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 4, 6, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_SSID_MULTICAST_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 4, 6, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_SSID_MULTICAST_L_READ( wv )               FIELD_GET( wv, 30, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_SSID_MULTICAST_L_WRITE( v, wv )           FIELD_SET( v, 30, 1, wv )
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_SSID_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 4, 2, 4, r)
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_SSID_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 4, 2, 4, v)
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_SSID_L_READ( wv )                         FIELD_GET( wv, 26, 4 )
+#define RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_SSID_L_WRITE( v, wv )                     FIELD_SET( v, 26, 4, wv )
+
+typedef struct
+{
+	uint32_t	valid       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0   	:28	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1   	:28	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	message_type	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_MESSAGE_DESCRIPTOR_DTS;
+
+#define RDD_CPU_TX_MESSAGE_DESCRIPTOR_VALID_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_CPU_TX_MESSAGE_DESCRIPTOR_VALID_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_CPU_TX_MESSAGE_DESCRIPTOR_COMMAND_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p, 4, 3, r)
+#define RDD_CPU_TX_MESSAGE_DESCRIPTOR_COMMAND_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p, 4, 3, v)
+#define RDD_CPU_TX_MESSAGE_DESCRIPTOR_MESSAGE_TYPE_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 7, 0, 4, r)
+#define RDD_CPU_TX_MESSAGE_DESCRIPTOR_MESSAGE_TYPE_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 7, 0, 4, v)
+#if defined DSL_63138
+
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_SIZE     32
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DHD_TX_POST_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_PTR()	( RDD_DHD_TX_POST_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_TX_POST_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	next_rule_cfg_id    	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	next_group_id       	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rule_type           	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	lookup_mode         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	hit_action          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	miss_action         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1           	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2           	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	generic_rule_index_1	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	generic_rule_index_2	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_mask            	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_DTS;
+
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_NEXT_RULE_CFG_ID_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p, 3, 5, r)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_NEXT_RULE_CFG_ID_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p, 3, 5, v)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_NEXT_GROUP_ID_READ(r, p)                        FIELD_MREAD_16((uint8_t *)p, 6, 5, r)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_NEXT_GROUP_ID_WRITE(v, p)                       FIELD_MWRITE_16((uint8_t *)p, 6, 5, v)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_RULE_TYPE_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 1, 3, 3, r)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_RULE_TYPE_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 1, 3, 3, v)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_LOOKUP_MODE_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 1, 1, 2, r)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_LOOKUP_MODE_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 1, 1, 2, v)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_HIT_ACTION_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 1, 0, 1, r)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_HIT_ACTION_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 1, 0, 1, v)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_MISS_ACTION_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 2, 7, 1, r)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_MISS_ACTION_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 2, 7, 1, v)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_GENERIC_RULE_INDEX_1_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 4, 2, 2, r)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_GENERIC_RULE_INDEX_1_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 4, 2, 2, v)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_GENERIC_RULE_INDEX_2_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 4, 0, 2, r)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_GENERIC_RULE_INDEX_2_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 4, 0, 2, v)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_KEY_MASK_READ(r, p)                             FIELD_MREAD_32((uint8_t *)p + 4, 0, 24, r)
+#define RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_KEY_MASK_WRITE(v, p)                            FIELD_MWRITE_32((uint8_t *)p + 4, 0, 24, v)
+#if defined DSL_63138
+
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	valid                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	context_index          	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bucket_overflow_counter	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command_list_length_64 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_extend             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	protocol               	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_port               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dst_port               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_ip                 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dst_ip                 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONNECTION_ENTRY_DTS;
+
+#define RDD_CONNECTION_ENTRY_VALID_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_CONNECTION_ENTRY_VALID_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_CONNECTION_ENTRY_CONTEXT_INDEX_READ(r, p)                           FIELD_MREAD_16((uint8_t *)p, 0, 15, r)
+#define RDD_CONNECTION_ENTRY_CONTEXT_INDEX_WRITE(v, p)                          FIELD_MWRITE_16((uint8_t *)p, 0, 15, v)
+#define RDD_CONNECTION_ENTRY_BUCKET_OVERFLOW_COUNTER_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 2, 5, 3, r)
+#define RDD_CONNECTION_ENTRY_BUCKET_OVERFLOW_COUNTER_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 2, 5, 3, v)
+#define RDD_CONNECTION_ENTRY_COMMAND_LIST_LENGTH_64_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 2, 1, 4, r)
+#define RDD_CONNECTION_ENTRY_COMMAND_LIST_LENGTH_64_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 2, 1, 4, v)
+#define RDD_CONNECTION_ENTRY_KEY_EXTEND_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 2, 0, 1, r)
+#define RDD_CONNECTION_ENTRY_KEY_EXTEND_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 2, 0, 1, v)
+#define RDD_CONNECTION_ENTRY_PROTOCOL_READ(r, p)                                MREAD_8((uint8_t *)p + 3, r)
+#define RDD_CONNECTION_ENTRY_PROTOCOL_WRITE(v, p)                               MWRITE_8((uint8_t *)p + 3, v)
+#define RDD_CONNECTION_ENTRY_SRC_PORT_READ(r, p)                                MREAD_16((uint8_t *)p + 4, r)
+#define RDD_CONNECTION_ENTRY_SRC_PORT_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_CONNECTION_ENTRY_DST_PORT_READ(r, p)                                MREAD_16((uint8_t *)p + 6, r)
+#define RDD_CONNECTION_ENTRY_DST_PORT_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_CONNECTION_ENTRY_SRC_IP_READ(r, p)                                  MREAD_32((uint8_t *)p + 8, r)
+#define RDD_CONNECTION_ENTRY_SRC_IP_WRITE(v, p)                                 MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_CONNECTION_ENTRY_DST_IP_READ(r, p)                                  MREAD_32((uint8_t *)p + 12, r)
+#define RDD_CONNECTION_ENTRY_DST_IP_WRITE(v, p)                                 MWRITE_32((uint8_t *)p + 12, v)
+#if defined DSL_63138
+
+#define RDD_DS_CONNECTION_CACHE_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CACHE_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CACHE_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CACHE_BUFFER_PTR()	( RDD_DS_CONNECTION_CACHE_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CACHE_BUFFER_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	valid            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command          	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipsec            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cpu_rx_queue     	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	upstream         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	sa_update        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	sa_index         	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	abs_flag         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1        	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error            	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	esphdr_offset    	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	abs_address_index	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_IPSEC_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_VALID_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_VALID_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_VALID_L_READ( wv )                           FIELD_GET( wv, 31, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_VALID_L_WRITE( v, wv )                       FIELD_SET( v, 31, 1, wv )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_COMMAND_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p, 4, 3, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_COMMAND_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p, 4, 3, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_COMMAND_L_READ( wv )                         FIELD_GET( wv, 28, 3 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_COMMAND_L_WRITE( v, wv )                     FIELD_SET( v, 28, 3, wv )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_IPSEC_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p, 2, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_IPSEC_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p, 2, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_IPSEC_L_READ( wv )                           FIELD_GET( wv, 26, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_IPSEC_L_WRITE( v, wv )                       FIELD_SET( v, 26, 1, wv )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_CPU_RX_QUEUE_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p, 6, 4, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_CPU_RX_QUEUE_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p, 6, 4, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_CPU_RX_QUEUE_L_READ( wv )                    FIELD_GET( wv, 22, 4 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_CPU_RX_QUEUE_L_WRITE( v, wv )                FIELD_SET( v, 22, 4, wv )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_UPSTREAM_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 1, 5, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_UPSTREAM_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 1, 5, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_UPSTREAM_L_READ( wv )                        FIELD_GET( wv, 21, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_UPSTREAM_L_WRITE( v, wv )                    FIELD_SET( v, 21, 1, wv )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_SA_UPDATE_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 1, 4, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_SA_UPDATE_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 1, 4, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_SA_UPDATE_L_READ( wv )                       FIELD_GET( wv, 20, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_SA_UPDATE_L_WRITE( v, wv )                   FIELD_SET( v, 20, 1, wv )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_SA_INDEX_READ(r, p)                          FIELD_MREAD_32((uint8_t *)p + 0, 14, 6, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_SA_INDEX_WRITE(v, p)                         FIELD_MWRITE_32((uint8_t *)p + 0, 14, 6, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_SA_INDEX_L_READ( wv )                        FIELD_GET( wv, 14, 6 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_SA_INDEX_L_WRITE( v, wv )                    FIELD_SET( v, 14, 6, wv )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_PACKET_LENGTH_READ(r, p)                     FIELD_MREAD_16((uint8_t *)p + 2, 0, 14, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_PACKET_LENGTH_WRITE(v, p)                    FIELD_MWRITE_16((uint8_t *)p + 2, 0, 14, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_PACKET_LENGTH_L_READ( wv )                   FIELD_GET( wv, 0, 14 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_PACKET_LENGTH_L_WRITE( v, wv )               FIELD_SET( v, 0, 14, wv )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ABS_FLAG_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ABS_FLAG_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ABS_FLAG_L_READ( wv )                        FIELD_GET( wv, 31, 1 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ABS_FLAG_L_WRITE( v, wv )                    FIELD_SET( v, 31, 1, wv )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ERROR_READ(r, p)                             FIELD_MREAD_16((uint8_t *)p + 4, 6, 3, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ERROR_WRITE(v, p)                            FIELD_MWRITE_16((uint8_t *)p + 4, 6, 3, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ERROR_L_READ( wv )                           FIELD_GET( wv, 22, 3 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ERROR_L_WRITE( v, wv )                       FIELD_SET( v, 22, 3, wv )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ESPHDR_OFFSET_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 5, 0, 6, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ESPHDR_OFFSET_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 5, 0, 6, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ESPHDR_OFFSET_L_READ( wv )                   FIELD_GET( wv, 16, 6 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ESPHDR_OFFSET_L_WRITE( v, wv )               FIELD_SET( v, 16, 6, wv )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ABS_ADDRESS_INDEX_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 6, 0, 15, r)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ABS_ADDRESS_INDEX_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 6, 0, 15, v)
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ABS_ADDRESS_INDEX_L_READ( wv )               FIELD_GET( wv, 0, 15 )
+#define RDD_CPU_TX_DESCRIPTOR_IPSEC_ABS_ADDRESS_INDEX_L_WRITE( v, wv )           FIELD_SET( v, 0, 15, wv )
+
+typedef struct
+{
+	uint32_t	reserved0    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error        	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cpu_rx_queue 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	upstream     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2    	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_DESCRIPTOR_IPSEC_DTS;
+
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_ERROR_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p, 4, 3, r)
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_ERROR_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p, 4, 3, v)
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_ERROR_L_READ( wv )                       FIELD_GET( wv, 28, 3 )
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_ERROR_L_WRITE( v, wv )                   FIELD_SET( v, 28, 3, wv )
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_CPU_RX_QUEUE_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p, 6, 4, r)
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_CPU_RX_QUEUE_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p, 6, 4, v)
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_CPU_RX_QUEUE_L_READ( wv )                FIELD_GET( wv, 22, 4 )
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_CPU_RX_QUEUE_L_WRITE( v, wv )            FIELD_SET( v, 22, 4, wv )
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_UPSTREAM_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 1, 5, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_UPSTREAM_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 1, 5, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_UPSTREAM_L_READ( wv )                    FIELD_GET( wv, 21, 1 )
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_UPSTREAM_L_WRITE( v, wv )                FIELD_SET( v, 21, 1, wv )
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_PACKET_LENGTH_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 2, 0, 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_PACKET_LENGTH_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 2, 0, 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_PACKET_LENGTH_L_READ( wv )               FIELD_GET( wv, 0, 14 )
+#define RDD_CPU_RX_DESCRIPTOR_IPSEC_PACKET_LENGTH_L_WRITE( v, wv )           FIELD_SET( v, 0, 14, wv )
+
+typedef struct
+{
+	uint32_t	msg_type             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	if_id                	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	common_hdr_flags     	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	epoch                	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	request_id           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_eth_hdr_0         	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_eth_hdr_1         	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_eth_hdr_2         	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_eth_hdr_3         	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flags                	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	seg_cnt              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	metadata_buf_addr_low	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	metadata_buf_addr_hi 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_buf_addr_low    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_buf_addr_hi     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	meta_buf_len         	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_len             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved             	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_DESCRIPTOR_DTS;
+
+#define RDD_DHD_TX_POST_DESCRIPTOR_MSG_TYPE_READ(r, p)                              MREAD_8((uint8_t *)p, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_MSG_TYPE_WRITE(v, p)                             MWRITE_8((uint8_t *)p, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_MSG_TYPE_L_READ( wv )                            FIELD_GET( wv, 24, 8 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_MSG_TYPE_L_WRITE( v, wv )                        FIELD_SET( v, 24, 8, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_IF_ID_READ(r, p)                                 MREAD_8((uint8_t *)p + 1, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_IF_ID_WRITE(v, p)                                MWRITE_8((uint8_t *)p + 1, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_IF_ID_L_READ( wv )                               FIELD_GET( wv, 16, 8 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_IF_ID_L_WRITE( v, wv )                           FIELD_SET( v, 16, 8, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_COMMON_HDR_FLAGS_READ(r, p)                      MREAD_8((uint8_t *)p + 2, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_COMMON_HDR_FLAGS_WRITE(v, p)                     MWRITE_8((uint8_t *)p + 2, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_COMMON_HDR_FLAGS_L_READ( wv )                    FIELD_GET( wv, 8, 8 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_COMMON_HDR_FLAGS_L_WRITE( v, wv )                FIELD_SET( v, 8, 8, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_EPOCH_READ(r, p)                                 MREAD_8((uint8_t *)p + 3, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_EPOCH_WRITE(v, p)                                MWRITE_8((uint8_t *)p + 3, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_EPOCH_L_READ( wv )                               FIELD_GET( wv, 0, 8 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_EPOCH_L_WRITE( v, wv )                           FIELD_SET( v, 0, 8, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_REQUEST_ID_READ(r, p)                            MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_REQUEST_ID_WRITE(v, p)                           MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_REQUEST_ID_L_READ( wv )                          FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_REQUEST_ID_L_WRITE( v, wv )                      FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_0_READ(r, p)                          MREAD_32((uint8_t *)p + 8, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_0_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_0_L_READ( wv )                        FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_0_L_WRITE( v, wv )                    FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_1_READ(r, p)                          MREAD_32((uint8_t *)p + 12, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_1_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_1_L_READ( wv )                        FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_1_L_WRITE( v, wv )                    FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_2_READ(r, p)                          MREAD_32((uint8_t *)p + 16, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_2_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_2_L_READ( wv )                        FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_2_L_WRITE( v, wv )                    FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_3_READ(r, p)                          MREAD_16((uint8_t *)p + 20, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_3_WRITE(v, p)                         MWRITE_16((uint8_t *)p + 20, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_3_L_READ( wv )                        FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_TX_ETH_HDR_3_L_WRITE( v, wv )                    FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_FLAGS_READ(r, p)                                 MREAD_8((uint8_t *)p + 22, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_FLAGS_WRITE(v, p)                                MWRITE_8((uint8_t *)p + 22, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_FLAGS_L_READ( wv )                               FIELD_GET( wv, 8, 8 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_FLAGS_L_WRITE( v, wv )                           FIELD_SET( v, 8, 8, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_SEG_CNT_READ(r, p)                               MREAD_8((uint8_t *)p + 23, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_SEG_CNT_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 23, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_SEG_CNT_L_READ( wv )                             FIELD_GET( wv, 0, 8 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_SEG_CNT_L_WRITE( v, wv )                         FIELD_SET( v, 0, 8, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_METADATA_BUF_ADDR_LOW_READ(r, p)                 MREAD_32((uint8_t *)p + 24, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_METADATA_BUF_ADDR_LOW_WRITE(v, p)                MWRITE_32((uint8_t *)p + 24, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_METADATA_BUF_ADDR_LOW_L_READ( wv )               FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_METADATA_BUF_ADDR_LOW_L_WRITE( v, wv )           FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_METADATA_BUF_ADDR_HI_READ(r, p)                  MREAD_32((uint8_t *)p + 28, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_METADATA_BUF_ADDR_HI_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 28, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_METADATA_BUF_ADDR_HI_L_READ( wv )                FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_METADATA_BUF_ADDR_HI_L_WRITE( v, wv )            FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_BUF_ADDR_LOW_READ(r, p)                     MREAD_32((uint8_t *)p + 32, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_BUF_ADDR_LOW_WRITE(v, p)                    MWRITE_32((uint8_t *)p + 32, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_BUF_ADDR_LOW_L_READ( wv )                   FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_BUF_ADDR_LOW_L_WRITE( v, wv )               FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_BUF_ADDR_HI_READ(r, p)                      MREAD_32((uint8_t *)p + 36, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_BUF_ADDR_HI_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 36, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_BUF_ADDR_HI_L_READ( wv )                    FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_BUF_ADDR_HI_L_WRITE( v, wv )                FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_META_BUF_LEN_READ(r, p)                          MREAD_16((uint8_t *)p + 40, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_META_BUF_LEN_WRITE(v, p)                         MWRITE_16((uint8_t *)p + 40, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_META_BUF_LEN_L_READ( wv )                        FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_META_BUF_LEN_L_WRITE( v, wv )                    FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_LEN_READ(r, p)                              MREAD_16((uint8_t *)p + 42, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_LEN_WRITE(v, p)                             MWRITE_16((uint8_t *)p + 42, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_LEN_L_READ( wv )                            FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_DATA_LEN_L_WRITE( v, wv )                        FIELD_SET( v, 0, 16, wv )
+
+typedef struct
+{
+	uint32_t	request_id        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	prio              	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	if_id             	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flags             	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	copy              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_len          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_buf_addr_low 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_buf_addr_high	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_eth_hdr_0      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_eth_hdr_1      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_eth_hdr_2      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_eth_hdr_3      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flowid_override   	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	info              	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DTS;
+
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_REQUEST_ID_READ(r, p)                         MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_REQUEST_ID_WRITE(v, p)                        MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_REQUEST_ID_L_READ( wv )                       FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_REQUEST_ID_L_WRITE( v, wv )                   FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_PRIO_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 4, 5, 3, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_PRIO_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 4, 5, 3, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_PRIO_L_READ( wv )                             FIELD_GET( wv, 29, 3 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_PRIO_L_WRITE( v, wv )                         FIELD_SET( v, 29, 3, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_IF_ID_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 4, 0, 5, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_IF_ID_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 4, 0, 5, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_IF_ID_L_READ( wv )                            FIELD_GET( wv, 24, 5 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_IF_ID_L_WRITE( v, wv )                        FIELD_SET( v, 24, 5, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_FLAGS_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 5, 1, 7, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_FLAGS_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 5, 1, 7, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_FLAGS_L_READ( wv )                            FIELD_GET( wv, 17, 7 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_FLAGS_L_WRITE( v, wv )                        FIELD_SET( v, 17, 7, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_COPY_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 5, 0, 1, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_COPY_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 5, 0, 1, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_COPY_L_READ( wv )                             FIELD_GET( wv, 16, 1 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_COPY_L_WRITE( v, wv )                         FIELD_SET( v, 16, 1, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_LEN_READ(r, p)                           MREAD_16((uint8_t *)p + 6, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_LEN_WRITE(v, p)                          MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_LEN_L_READ( wv )                         FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_LEN_L_WRITE( v, wv )                     FIELD_SET( v, 0, 16, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_LOW_READ(r, p)                  MREAD_32((uint8_t *)p + 8, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_LOW_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_LOW_L_READ( wv )                FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_LOW_L_WRITE( v, wv )            FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_HIGH_READ(r, p)                 MREAD_32((uint8_t *)p + 12, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_HIGH_WRITE(v, p)                MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_HIGH_L_READ( wv )               FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_HIGH_L_WRITE( v, wv )           FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_0_READ(r, p)                       MREAD_32((uint8_t *)p + 16, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_0_WRITE(v, p)                      MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_0_L_READ( wv )                     FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_0_L_WRITE( v, wv )                 FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_1_READ(r, p)                       MREAD_32((uint8_t *)p + 20, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_1_WRITE(v, p)                      MWRITE_32((uint8_t *)p + 20, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_1_L_READ( wv )                     FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_1_L_WRITE( v, wv )                 FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_2_READ(r, p)                       MREAD_32((uint8_t *)p + 24, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_2_WRITE(v, p)                      MWRITE_32((uint8_t *)p + 24, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_2_L_READ( wv )                     FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_2_L_WRITE( v, wv )                 FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_3_READ(r, p)                       MREAD_16((uint8_t *)p + 28, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_3_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 28, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_3_L_READ( wv )                     FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_TX_ETH_HDR_3_L_WRITE( v, wv )                 FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_FLOWID_OVERRIDE_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 30, 4, 12, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_FLOWID_OVERRIDE_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 30, 4, 12, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_FLOWID_OVERRIDE_L_READ( wv )                  FIELD_GET( wv, 4, 12 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_FLOWID_OVERRIDE_L_WRITE( v, wv )              FIELD_SET( v, 4, 12, wv )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_INFO_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 31, 0, 4, r)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_INFO_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 31, 0, 4, v)
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_INFO_L_READ( wv )                             FIELD_GET( wv, 0, 4 )
+#define RDD_DHD_TX_POST_DESCRIPTOR_CWI32_INFO_L_WRITE( v, wv )                         FIELD_SET( v, 0, 4, wv )
+#define RDD_CPU_TX_MESSAGE_DATA_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER	16
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_CPU_TX_MESSAGE_DATA_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_MESSAGE_DATA_BUFFER_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	union_field1                    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = union_field1, size = 32 bits
+	uint32_t	register_r9                     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	emac_descriptor_ptr             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0                       	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	union_field2                    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = union_field2, size = 32 bits
+	uint32_t	register_r11                    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	eth_tx_queues_pointers_table_ptr	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbh_destination                 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_DTS;
+
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_UNION_FIELD1_READ(r, p)                                     MREAD_32((uint8_t *)p, r)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_UNION_FIELD1_WRITE(v, p)                                    MWRITE_32((uint8_t *)p, v)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_REGISTER_R9_READ(r, p)                                      MREAD_32((uint8_t *)p, r)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_REGISTER_R9_WRITE(v, p)                                     MWRITE_32((uint8_t *)p, v)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_EMAC_DESCRIPTOR_PTR_READ(r, p)                              MREAD_16((uint8_t *)p, r)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_EMAC_DESCRIPTOR_PTR_WRITE(v, p)                             MWRITE_16((uint8_t *)p, v)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_UNION_FIELD2_READ(r, p)                                     MREAD_32((uint8_t *)p + 4, r)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_UNION_FIELD2_WRITE(v, p)                                    MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_REGISTER_R11_READ(r, p)                                     MREAD_32((uint8_t *)p + 4, r)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_REGISTER_R11_WRITE(v, p)                                    MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_ETH_TX_QUEUES_POINTERS_TABLE_PTR_READ(r, p)                 MREAD_16((uint8_t *)p + 4, r)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_ETH_TX_QUEUES_POINTERS_TABLE_PTR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_BBH_DESTINATION_READ(r, p)                                  MREAD_16((uint8_t *)p + 6, r)
+#define RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_BBH_DESTINATION_WRITE(v, p)                                 MWRITE_16((uint8_t *)p + 6, v)
+#if defined DSL_63138
+
+#define RDD_ETH_TX_LOCAL_REGISTERS_SIZE     9
+typedef struct
+{
+	RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_DTS	entry[ RDD_ETH_TX_LOCAL_REGISTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_LOCAL_REGISTERS_DTS;
+
+#define RDD_ETH_TX_LOCAL_REGISTERS_PTR()	( RDD_ETH_TX_LOCAL_REGISTERS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_LOCAL_REGISTERS_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	ingress_filters                 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = ingress_filters, size = 32 bits
+	uint32_t	reserved1                       	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	acl_layer3_filter               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	acl_layer2_filter               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_mac_anti_spoofing_lookup    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tpid_detect_filter              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_fragment_ingress_filter_trap 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_fragment_ingress_filter      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	header_error_ingress_filter_trap	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	header_error_ingress_filter     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_validation_filter            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ingress_filters_bypass          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0                       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vlan_switching_filter           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vlan_us_aggregation_filter      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	timing_1588_ingress_filter      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2                       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dst_mac_lookup                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_mac_lookup                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	local_switching_ingress_filters 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast_filter                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	broadcast_filter                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ethertype_filter                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	icmpv6_filter                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	igmp_filter                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mld_ingress_filter              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhcp_ingress_filter             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DTS;
+
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_INGRESS_FILTERS_READ(r, p)                                  MREAD_32((uint8_t *)p, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_INGRESS_FILTERS_WRITE(v, p)                                 MWRITE_32((uint8_t *)p, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_INGRESS_FILTERS_L_READ( wv )                                FIELD_GET( wv, 0, 32 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_INGRESS_FILTERS_L_WRITE( v, wv )                            FIELD_SET( v, 0, 32, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ACL_LAYER3_FILTER_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p, 0, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ACL_LAYER3_FILTER_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p, 0, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ACL_LAYER3_FILTER_L_READ( wv )                              FIELD_GET( wv, 24, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ACL_LAYER3_FILTER_L_WRITE( v, wv )                          FIELD_SET( v, 24, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ACL_LAYER2_FILTER_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 1, 7, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ACL_LAYER2_FILTER_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 1, 7, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ACL_LAYER2_FILTER_L_READ( wv )                              FIELD_GET( wv, 23, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ACL_LAYER2_FILTER_L_WRITE( v, wv )                          FIELD_SET( v, 23, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_SRC_MAC_ANTI_SPOOFING_LOOKUP_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 1, 6, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_SRC_MAC_ANTI_SPOOFING_LOOKUP_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 1, 6, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_SRC_MAC_ANTI_SPOOFING_LOOKUP_L_READ( wv )                   FIELD_GET( wv, 22, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_SRC_MAC_ANTI_SPOOFING_LOOKUP_L_WRITE( v, wv )               FIELD_SET( v, 22, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_TPID_DETECT_FILTER_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 1, 5, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_TPID_DETECT_FILTER_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 1, 5, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_TPID_DETECT_FILTER_L_READ( wv )                             FIELD_GET( wv, 21, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_TPID_DETECT_FILTER_L_WRITE( v, wv )                         FIELD_SET( v, 21, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_FRAGMENT_INGRESS_FILTER_TRAP_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 1, 4, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_FRAGMENT_INGRESS_FILTER_TRAP_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 1, 4, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_FRAGMENT_INGRESS_FILTER_TRAP_L_READ( wv )                FIELD_GET( wv, 20, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_FRAGMENT_INGRESS_FILTER_TRAP_L_WRITE( v, wv )            FIELD_SET( v, 20, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_FRAGMENT_INGRESS_FILTER_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 1, 3, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_FRAGMENT_INGRESS_FILTER_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 1, 3, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_FRAGMENT_INGRESS_FILTER_L_READ( wv )                     FIELD_GET( wv, 19, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_FRAGMENT_INGRESS_FILTER_L_WRITE( v, wv )                 FIELD_SET( v, 19, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_HEADER_ERROR_INGRESS_FILTER_TRAP_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 1, 2, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_HEADER_ERROR_INGRESS_FILTER_TRAP_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 1, 2, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_HEADER_ERROR_INGRESS_FILTER_TRAP_L_READ( wv )               FIELD_GET( wv, 18, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_HEADER_ERROR_INGRESS_FILTER_TRAP_L_WRITE( v, wv )           FIELD_SET( v, 18, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_HEADER_ERROR_INGRESS_FILTER_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 1, 1, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_HEADER_ERROR_INGRESS_FILTER_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 1, 1, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_HEADER_ERROR_INGRESS_FILTER_L_READ( wv )                    FIELD_GET( wv, 17, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_HEADER_ERROR_INGRESS_FILTER_L_WRITE( v, wv )                FIELD_SET( v, 17, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_VALIDATION_FILTER_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 1, 0, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_VALIDATION_FILTER_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 1, 0, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_VALIDATION_FILTER_L_READ( wv )                           FIELD_GET( wv, 16, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IP_VALIDATION_FILTER_L_WRITE( v, wv )                       FIELD_SET( v, 16, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_INGRESS_FILTERS_BYPASS_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 2, 7, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_INGRESS_FILTERS_BYPASS_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 2, 7, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_INGRESS_FILTERS_BYPASS_L_READ( wv )                         FIELD_GET( wv, 15, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_INGRESS_FILTERS_BYPASS_L_WRITE( v, wv )                     FIELD_SET( v, 15, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_VLAN_SWITCHING_FILTER_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 2, 5, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_VLAN_SWITCHING_FILTER_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 2, 5, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_VLAN_SWITCHING_FILTER_L_READ( wv )                          FIELD_GET( wv, 13, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_VLAN_SWITCHING_FILTER_L_WRITE( v, wv )                      FIELD_SET( v, 13, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_VLAN_US_AGGREGATION_FILTER_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 2, 4, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_VLAN_US_AGGREGATION_FILTER_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 2, 4, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_VLAN_US_AGGREGATION_FILTER_L_READ( wv )                     FIELD_GET( wv, 12, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_VLAN_US_AGGREGATION_FILTER_L_WRITE( v, wv )                 FIELD_SET( v, 12, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_TIMING_1588_INGRESS_FILTER_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 2, 3, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_TIMING_1588_INGRESS_FILTER_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 2, 3, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_TIMING_1588_INGRESS_FILTER_L_READ( wv )                     FIELD_GET( wv, 11, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_TIMING_1588_INGRESS_FILTER_L_WRITE( v, wv )                 FIELD_SET( v, 11, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DST_MAC_LOOKUP_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 2, 1, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DST_MAC_LOOKUP_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 2, 1, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DST_MAC_LOOKUP_L_READ( wv )                                 FIELD_GET( wv, 9, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DST_MAC_LOOKUP_L_WRITE( v, wv )                             FIELD_SET( v, 9, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_SRC_MAC_LOOKUP_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 2, 0, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_SRC_MAC_LOOKUP_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 2, 0, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_SRC_MAC_LOOKUP_L_READ( wv )                                 FIELD_GET( wv, 8, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_SRC_MAC_LOOKUP_L_WRITE( v, wv )                             FIELD_SET( v, 8, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_LOCAL_SWITCHING_INGRESS_FILTERS_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 3, 7, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_LOCAL_SWITCHING_INGRESS_FILTERS_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 3, 7, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_LOCAL_SWITCHING_INGRESS_FILTERS_L_READ( wv )                FIELD_GET( wv, 7, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_LOCAL_SWITCHING_INGRESS_FILTERS_L_WRITE( v, wv )            FIELD_SET( v, 7, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_MULTICAST_FILTER_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 3, 6, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_MULTICAST_FILTER_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 3, 6, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_MULTICAST_FILTER_L_READ( wv )                               FIELD_GET( wv, 6, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_MULTICAST_FILTER_L_WRITE( v, wv )                           FIELD_SET( v, 6, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_BROADCAST_FILTER_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 3, 5, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_BROADCAST_FILTER_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 3, 5, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_BROADCAST_FILTER_L_READ( wv )                               FIELD_GET( wv, 5, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_BROADCAST_FILTER_L_WRITE( v, wv )                           FIELD_SET( v, 5, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ETHERTYPE_FILTER_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 3, 4, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ETHERTYPE_FILTER_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 3, 4, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ETHERTYPE_FILTER_L_READ( wv )                               FIELD_GET( wv, 4, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ETHERTYPE_FILTER_L_WRITE( v, wv )                           FIELD_SET( v, 4, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ICMPV6_FILTER_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 3, 3, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ICMPV6_FILTER_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 3, 3, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ICMPV6_FILTER_L_READ( wv )                                  FIELD_GET( wv, 3, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_ICMPV6_FILTER_L_WRITE( v, wv )                              FIELD_SET( v, 3, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IGMP_FILTER_READ(r, p)                                      FIELD_MREAD_8((uint8_t *)p + 3, 2, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IGMP_FILTER_WRITE(v, p)                                     FIELD_MWRITE_8((uint8_t *)p + 3, 2, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IGMP_FILTER_L_READ( wv )                                    FIELD_GET( wv, 2, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_IGMP_FILTER_L_WRITE( v, wv )                                FIELD_SET( v, 2, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_MLD_INGRESS_FILTER_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 3, 1, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_MLD_INGRESS_FILTER_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 3, 1, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_MLD_INGRESS_FILTER_L_READ( wv )                             FIELD_GET( wv, 1, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_MLD_INGRESS_FILTER_L_WRITE( v, wv )                         FIELD_SET( v, 1, 1, wv )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DHCP_INGRESS_FILTER_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 3, 0, 1, r)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DHCP_INGRESS_FILTER_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 3, 0, 1, v)
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DHCP_INGRESS_FILTER_L_READ( wv )                            FIELD_GET( wv, 0, 1 )
+#define RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DHCP_INGRESS_FILTER_L_WRITE( v, wv )                        FIELD_SET( v, 0, 1, wv )
+#if defined DSL_63138
+
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     2
+typedef struct
+{
+	RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved_fw_only	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	us_flow_control_mode    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0               	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	max_low_threshold       	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	min_high_threshold      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	max_high_threshold      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	low_large_interval_flag 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1               	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	low_drop_constant       	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	high_large_interval_flag	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2               	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	high_drop_constant      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_QUEUE_PROFILE_DTS;
+
+#define RDD_QUEUE_PROFILE_US_FLOW_CONTROL_MODE_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_QUEUE_PROFILE_US_FLOW_CONTROL_MODE_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_QUEUE_PROFILE_MAX_LOW_THRESHOLD_READ(r, p)                        MREAD_16((uint8_t *)p + 2, r)
+#define RDD_QUEUE_PROFILE_MAX_LOW_THRESHOLD_WRITE(v, p)                       MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_QUEUE_PROFILE_MIN_HIGH_THRESHOLD_READ(r, p)                       MREAD_16((uint8_t *)p + 4, r)
+#define RDD_QUEUE_PROFILE_MIN_HIGH_THRESHOLD_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_QUEUE_PROFILE_MAX_HIGH_THRESHOLD_READ(r, p)                       MREAD_16((uint8_t *)p + 6, r)
+#define RDD_QUEUE_PROFILE_MAX_HIGH_THRESHOLD_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_QUEUE_PROFILE_LOW_LARGE_INTERVAL_FLAG_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_QUEUE_PROFILE_LOW_LARGE_INTERVAL_FLAG_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_QUEUE_PROFILE_LOW_DROP_CONSTANT_READ(r, p)                        MREAD_16((uint8_t *)p + 10, r)
+#define RDD_QUEUE_PROFILE_LOW_DROP_CONSTANT_WRITE(v, p)                       MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_QUEUE_PROFILE_HIGH_LARGE_INTERVAL_FLAG_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 12, 7, 1, r)
+#define RDD_QUEUE_PROFILE_HIGH_LARGE_INTERVAL_FLAG_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_QUEUE_PROFILE_HIGH_DROP_CONSTANT_READ(r, p)                       MREAD_16((uint8_t *)p + 14, r)
+#define RDD_QUEUE_PROFILE_HIGH_DROP_CONSTANT_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 14, v)
+#if defined DSL_63138
+
+#define RDD_DS_QUEUE_PROFILE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_QUEUE_PROFILE_DTS	entry[ RDD_DS_QUEUE_PROFILE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_QUEUE_PROFILE_TABLE_DTS;
+
+#define RDD_DS_QUEUE_PROFILE_TABLE_PTR()	( RDD_DS_QUEUE_PROFILE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_QUEUE_PROFILE_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved0     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ssid_multicast	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ssid          	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	radio_idx     	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_id  	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_DESCRIPTOR_DTS;
+
+#define RDD_CPU_TX_DHD_DESCRIPTOR_SSID_MULTICAST_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 4, 6, 1, r)
+#define RDD_CPU_TX_DHD_DESCRIPTOR_SSID_MULTICAST_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 4, 6, 1, v)
+#define RDD_CPU_TX_DHD_DESCRIPTOR_SSID_MULTICAST_L_READ( wv )               FIELD_GET( wv, 30, 1 )
+#define RDD_CPU_TX_DHD_DESCRIPTOR_SSID_MULTICAST_L_WRITE( v, wv )           FIELD_SET( v, 30, 1, wv )
+#define RDD_CPU_TX_DHD_DESCRIPTOR_SSID_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 4, 2, 4, r)
+#define RDD_CPU_TX_DHD_DESCRIPTOR_SSID_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 4, 2, 4, v)
+#define RDD_CPU_TX_DHD_DESCRIPTOR_SSID_L_READ( wv )                         FIELD_GET( wv, 26, 4 )
+#define RDD_CPU_TX_DHD_DESCRIPTOR_SSID_L_WRITE( v, wv )                     FIELD_SET( v, 26, 4, wv )
+#define RDD_CPU_TX_DHD_DESCRIPTOR_RADIO_IDX_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 4, 0, 2, r)
+#define RDD_CPU_TX_DHD_DESCRIPTOR_RADIO_IDX_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 4, 0, 2, v)
+#define RDD_CPU_TX_DHD_DESCRIPTOR_RADIO_IDX_L_READ( wv )                    FIELD_GET( wv, 24, 2 )
+#define RDD_CPU_TX_DHD_DESCRIPTOR_RADIO_IDX_L_WRITE( v, wv )                FIELD_SET( v, 24, 2, wv )
+#define RDD_CPU_TX_DHD_DESCRIPTOR_FLOW_RING_ID_READ(r, p)                   FIELD_MREAD_32((uint8_t *)p + 4, 14, 10, r)
+#define RDD_CPU_TX_DHD_DESCRIPTOR_FLOW_RING_ID_WRITE(v, p)                  FIELD_MWRITE_32((uint8_t *)p + 4, 14, 10, v)
+#define RDD_CPU_TX_DHD_DESCRIPTOR_FLOW_RING_ID_L_READ( wv )                 FIELD_GET( wv, 14, 10 )
+#define RDD_CPU_TX_DHD_DESCRIPTOR_FLOW_RING_ID_L_WRITE( v, wv )             FIELD_SET( v, 14, 10, wv )
+
+typedef struct
+{
+	uint32_t	reserved0     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_msg_type  	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	radio_idx     	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_id  	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	disabled      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	read_idx_valid	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	read_idx      	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2     	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_DTS;
+
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_DHD_MSG_TYPE_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 4, 6, 2, r)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_DHD_MSG_TYPE_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 4, 6, 2, v)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_DHD_MSG_TYPE_L_READ( wv )                 FIELD_GET( wv, 30, 2 )
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_DHD_MSG_TYPE_L_WRITE( v, wv )             FIELD_SET( v, 30, 2, wv )
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_RADIO_IDX_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 4, 4, 2, r)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_RADIO_IDX_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 4, 4, 2, v)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_RADIO_IDX_L_READ( wv )                    FIELD_GET( wv, 28, 2 )
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_RADIO_IDX_L_WRITE( v, wv )                FIELD_SET( v, 28, 2, wv )
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_FLOW_RING_ID_READ(r, p)                   FIELD_MREAD_16((uint8_t *)p + 4, 2, 10, r)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_FLOW_RING_ID_WRITE(v, p)                  FIELD_MWRITE_16((uint8_t *)p + 4, 2, 10, v)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_FLOW_RING_ID_L_READ( wv )                 FIELD_GET( wv, 18, 10 )
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_FLOW_RING_ID_L_WRITE( v, wv )             FIELD_SET( v, 18, 10, wv )
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_DISABLED_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 5, 1, 1, r)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_DISABLED_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 5, 1, 1, v)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_DISABLED_L_READ( wv )                     FIELD_GET( wv, 17, 1 )
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_DISABLED_L_WRITE( v, wv )                 FIELD_SET( v, 17, 1, wv )
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_READ_IDX_VALID_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 5, 0, 1, r)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_READ_IDX_VALID_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 5, 0, 1, v)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_READ_IDX_VALID_L_READ( wv )               FIELD_GET( wv, 16, 1 )
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_READ_IDX_VALID_L_WRITE( v, wv )           FIELD_SET( v, 16, 1, wv )
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_READ_IDX_READ(r, p)                       FIELD_MREAD_16((uint8_t *)p + 6, 6, 10, r)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_READ_IDX_WRITE(v, p)                      FIELD_MWRITE_16((uint8_t *)p + 6, 6, 10, v)
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_READ_IDX_L_READ( wv )                     FIELD_GET( wv, 6, 10 )
+#define RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_READ_IDX_L_WRITE( v, wv )                 FIELD_SET( v, 6, 10, wv )
+
+typedef struct
+{
+	uint32_t	reserved0                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	guaranteed_free_count_incr 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	guaranteed_free_count_delta	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_UPDATE_PD_POOL_QUOTA_MESSAGE_DESCRIPTOR_DTS;
+
+#define RDD_CPU_TX_UPDATE_PD_POOL_QUOTA_MESSAGE_DESCRIPTOR_GUARANTEED_FREE_COUNT_INCR_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_CPU_TX_UPDATE_PD_POOL_QUOTA_MESSAGE_DESCRIPTOR_GUARANTEED_FREE_COUNT_INCR_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_CPU_TX_UPDATE_PD_POOL_QUOTA_MESSAGE_DESCRIPTOR_GUARANTEED_FREE_COUNT_INCR_L_READ( wv )                FIELD_GET( wv, 31, 1 )
+#define RDD_CPU_TX_UPDATE_PD_POOL_QUOTA_MESSAGE_DESCRIPTOR_GUARANTEED_FREE_COUNT_INCR_L_WRITE( v, wv )            FIELD_SET( v, 31, 1, wv )
+#define RDD_CPU_TX_UPDATE_PD_POOL_QUOTA_MESSAGE_DESCRIPTOR_GUARANTEED_FREE_COUNT_DELTA_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 4, 0, 15, r)
+#define RDD_CPU_TX_UPDATE_PD_POOL_QUOTA_MESSAGE_DESCRIPTOR_GUARANTEED_FREE_COUNT_DELTA_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 4, 0, 15, v)
+#define RDD_CPU_TX_UPDATE_PD_POOL_QUOTA_MESSAGE_DESCRIPTOR_GUARANTEED_FREE_COUNT_DELTA_L_READ( wv )               FIELD_GET( wv, 16, 15 )
+#define RDD_CPU_TX_UPDATE_PD_POOL_QUOTA_MESSAGE_DESCRIPTOR_GUARANTEED_FREE_COUNT_DELTA_L_WRITE( v, wv )           FIELD_SET( v, 16, 15, wv )
+#if defined DSL_63138
+
+#define RDD_DS_SQ_ENQUEUE_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DS_SQ_ENQUEUE_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_SQ_ENQUEUE_QUEUE_DTS;
+
+#define RDD_DS_SQ_ENQUEUE_QUEUE_PTR()	( RDD_DS_SQ_ENQUEUE_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_SQ_ENQUEUE_QUEUE_ADDRESS )
+
+#endif
+#define RDD_MULTICAST_HEADER_BUFFER_RESERVED_FW_ONLY_NUMBER	16
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_MULTICAST_HEADER_BUFFER_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MULTICAST_HEADER_BUFFER_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	reserved_fw_only	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_QUEUE_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_PTR()	( RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved_fw_only	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_NULL_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_NULL_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_NULL_BUFFER_DTS;
+
+#define RDD_DS_NULL_BUFFER_PTR()	( RDD_DS_NULL_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_NULL_BUFFER_ADDRESS )
+
+#endif
+#define RDD_RUNNER_FLOW_HEADER_DESCRIPTOR_RESERVED_FW_ONLY_NUMBER	2
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_RUNNER_FLOW_HEADER_DESCRIPTOR_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS;
+
+#if defined DSL_63138
+
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	primitive_address	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPE_COMMAND_PRIMITIVE_ENTRY_DTS;
+
+#define RDD_GPE_COMMAND_PRIMITIVE_ENTRY_PRIMITIVE_ADDRESS_READ(r, p)                 MREAD_16((uint8_t *)p, r)
+#define RDD_GPE_COMMAND_PRIMITIVE_ENTRY_PRIMITIVE_ADDRESS_WRITE(v, p)                MWRITE_16((uint8_t *)p, v)
+#if defined DSL_63138
+
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_GPE_COMMAND_PRIMITIVE_ENTRY_DTS	entry[ RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_PTR()	( RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_FAST_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_ROUTER_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_ROUTER_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_ROUTER_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_ROUTER_INGRESS_QUEUE_PTR()	( RDD_DS_ROUTER_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_ROUTER_INGRESS_QUEUE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	ring_value  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = ring_value, size = 32 bits
+	uint32_t	request_id  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0   	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_type 	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1   	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2   	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ownership   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3   	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	status      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_id	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_COMPLETE_RING_ENTRY_DTS;
+
+#define RDD_DHD_COMPLETE_RING_ENTRY_RING_VALUE_READ(r, p)                   MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_COMPLETE_RING_ENTRY_RING_VALUE_WRITE(v, p)                  MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_COMPLETE_RING_ENTRY_RING_VALUE_L_READ( wv )                 FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_COMPLETE_RING_ENTRY_RING_VALUE_L_WRITE( v, wv )             FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_COMPLETE_RING_ENTRY_REQUEST_ID_READ(r, p)                   MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_COMPLETE_RING_ENTRY_REQUEST_ID_WRITE(v, p)                  MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_COMPLETE_RING_ENTRY_REQUEST_ID_L_READ( wv )                 FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_COMPLETE_RING_ENTRY_REQUEST_ID_L_WRITE( v, wv )             FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_COMPLETE_RING_ENTRY_BUFFER_TYPE_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p, 0, 2, r)
+#define RDD_DHD_COMPLETE_RING_ENTRY_BUFFER_TYPE_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p, 0, 2, v)
+#define RDD_DHD_COMPLETE_RING_ENTRY_BUFFER_TYPE_L_READ( wv )                FIELD_GET( wv, 24, 2 )
+#define RDD_DHD_COMPLETE_RING_ENTRY_BUFFER_TYPE_L_WRITE( v, wv )            FIELD_SET( v, 24, 2, wv )
+#define RDD_DHD_COMPLETE_RING_ENTRY_OWNERSHIP_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p, 0, 2, r)
+#define RDD_DHD_COMPLETE_RING_ENTRY_OWNERSHIP_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p, 0, 2, v)
+#define RDD_DHD_COMPLETE_RING_ENTRY_OWNERSHIP_L_READ( wv )                  FIELD_GET( wv, 24, 2 )
+#define RDD_DHD_COMPLETE_RING_ENTRY_OWNERSHIP_L_WRITE( v, wv )              FIELD_SET( v, 24, 2, wv )
+#define RDD_DHD_COMPLETE_RING_ENTRY_STATUS_READ(r, p)                       MREAD_16((uint8_t *)p + 4, r)
+#define RDD_DHD_COMPLETE_RING_ENTRY_STATUS_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_DHD_COMPLETE_RING_ENTRY_STATUS_L_READ( wv )                     FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_COMPLETE_RING_ENTRY_STATUS_L_WRITE( v, wv )                 FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_COMPLETE_RING_ENTRY_FLOW_RING_ID_READ(r, p)                 MREAD_16((uint8_t *)p + 6, r)
+#define RDD_DHD_COMPLETE_RING_ENTRY_FLOW_RING_ID_WRITE(v, p)                MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_DHD_COMPLETE_RING_ENTRY_FLOW_RING_ID_L_READ( wv )               FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_COMPLETE_RING_ENTRY_FLOW_RING_ID_L_WRITE( v, wv )           FIELD_SET( v, 0, 16, wv )
+#if defined DSL_63138
+
+#define RDD_DHD_COMPLETE_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_COMPLETE_RING_ENTRY_DTS	entry[ RDD_DHD_COMPLETE_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_COMPLETE_RING_BUFFER_DTS;
+
+#define RDD_DHD_COMPLETE_RING_BUFFER_PTR()	( RDD_DHD_COMPLETE_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_COMPLETE_RING_BUFFER_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	reserved_fw_only	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BYTE_1_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry[ RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS;
+
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_PTR()	( RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	ssid_vector     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ring_id         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wifi_queue      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	headroom_size   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_bridge_port 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dma_sync        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	type            	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbh_descriptor_0	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbh_descriptor_1	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	chain_id        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_PARAMETERS_BLOCK_ENTRY_DTS;
+
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_SSID_VECTOR_READ(r, p)                      MREAD_16((uint8_t *)p, r)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_SSID_VECTOR_WRITE(v, p)                     MWRITE_16((uint8_t *)p, v)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_RING_ID_READ(r, p)                          MREAD_8((uint8_t *)p + 2, r)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_RING_ID_WRITE(v, p)                         MWRITE_8((uint8_t *)p + 2, v)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_WIFI_QUEUE_READ(r, p)                       MREAD_8((uint8_t *)p + 3, r)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_WIFI_QUEUE_WRITE(v, p)                      MWRITE_8((uint8_t *)p + 3, v)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_HEADROOM_SIZE_READ(r, p)                    MREAD_8((uint8_t *)p + 4, r)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_HEADROOM_SIZE_WRITE(v, p)                   MWRITE_8((uint8_t *)p + 4, v)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_SRC_BRIDGE_PORT_READ(r, p)                  MREAD_8((uint8_t *)p + 5, r)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_SRC_BRIDGE_PORT_WRITE(v, p)                 MWRITE_8((uint8_t *)p + 5, v)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_DMA_SYNC_READ(r, p)                         MREAD_8((uint8_t *)p + 6, r)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_DMA_SYNC_WRITE(v, p)                        MWRITE_8((uint8_t *)p + 6, v)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_TYPE_READ(r, p)                             MREAD_8((uint8_t *)p + 7, r)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_TYPE_WRITE(v, p)                            MWRITE_8((uint8_t *)p + 7, v)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_BBH_DESCRIPTOR_0_READ(r, p)                 MREAD_32((uint8_t *)p + 8, r)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_BBH_DESCRIPTOR_0_WRITE(v, p)                MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_BBH_DESCRIPTOR_1_READ(r, p)                 MREAD_32((uint8_t *)p + 12, r)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_BBH_DESCRIPTOR_1_WRITE(v, p)                MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_CHAIN_ID_READ(r, p)                         MREAD_16((uint8_t *)p + 16, r)
+#define RDD_CPU_PARAMETERS_BLOCK_ENTRY_CHAIN_ID_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 16, v)
+
+typedef struct
+{
+	uint32_t	wfd_0_ssid_state_vector	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_1_ssid_state_vector	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_2_ssid_state_vector	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_SSID_STATS_STATE_ENTRY_DTS;
+
+#define RDD_WLAN_MCAST_SSID_STATS_STATE_ENTRY_WFD_0_SSID_STATE_VECTOR_READ(r, p)                 MREAD_16((uint8_t *)p, r)
+#define RDD_WLAN_MCAST_SSID_STATS_STATE_ENTRY_WFD_0_SSID_STATE_VECTOR_WRITE(v, p)                MWRITE_16((uint8_t *)p, v)
+#define RDD_WLAN_MCAST_SSID_STATS_STATE_ENTRY_WFD_1_SSID_STATE_VECTOR_READ(r, p)                 MREAD_16((uint8_t *)p + 2, r)
+#define RDD_WLAN_MCAST_SSID_STATS_STATE_ENTRY_WFD_1_SSID_STATE_VECTOR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_WLAN_MCAST_SSID_STATS_STATE_ENTRY_WFD_2_SSID_STATE_VECTOR_READ(r, p)                 MREAD_16((uint8_t *)p + 4, r)
+#define RDD_WLAN_MCAST_SSID_STATS_STATE_ENTRY_WFD_2_SSID_STATE_VECTOR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 4, v)
+
+typedef struct
+{
+	uint16_t	number_of_active_tasks	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TIMER_CONTROL_DESCRIPTOR_DTS;
+
+#define RDD_TIMER_CONTROL_DESCRIPTOR_NUMBER_OF_ACTIVE_TASKS_READ(r, p)                 MREAD_16((uint8_t *)p, r)
+#define RDD_TIMER_CONTROL_DESCRIPTOR_NUMBER_OF_ACTIVE_TASKS_WRITE(v, p)                MWRITE_16((uint8_t *)p, v)
+#define RDD_DHD_L2_HEADER_BUFFER_ENTRY_DHD_L2_BUFFER_DATA_NUMBER	32
+
+typedef struct
+{
+	uint8_t	dhd_l2_buffer_data[RDD_DHD_L2_HEADER_BUFFER_ENTRY_DHD_L2_BUFFER_DATA_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_L2_HEADER_BUFFER_ENTRY_DTS;
+
+#define RDD_DHD_L2_HEADER_BUFFER_ENTRY_DHD_L2_BUFFER_DATA_READ(r, p, i)              MREAD_I_8((uint8_t *)p, i, r)
+#define RDD_DHD_L2_HEADER_BUFFER_ENTRY_DHD_L2_BUFFER_DATA_WRITE(v, p, i)             MWRITE_I_8((uint8_t *)p, i, v)
+#if defined DSL_63138
+
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE     4
+typedef struct
+{
+	RDD_DHD_L2_HEADER_BUFFER_ENTRY_DTS	entry[ RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_HEADER_SCRATCH_DTS;
+
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_PTR()	( RDD_DS_DHD_TX_POST_HEADER_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_HEADER_SCRATCH_ADDRESS )
+
+#endif
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_RESERVED_FW_ONLY_NUMBER	16
+
+typedef struct
+{
+	uint16_t	reserved_fw_only[RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE     5
+typedef struct
+{
+	RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	valid                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vlan_head_index        	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bucket_overflow_counter	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command_list_length_64 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_extend             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_multicast           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	protocol               	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	number_of_tags         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2              	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_ip                 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dst_ip                 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_CONNECTION_ENTRY_DTS;
+
+#define RDD_FC_MCAST_CONNECTION_ENTRY_VALID_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_VALID_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_VLAN_HEAD_INDEX_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p, 0, 7, r)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_VLAN_HEAD_INDEX_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p, 0, 7, v)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_BUCKET_OVERFLOW_COUNTER_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 2, 5, 3, r)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_BUCKET_OVERFLOW_COUNTER_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 2, 5, 3, v)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_COMMAND_LIST_LENGTH_64_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 2, 1, 4, r)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_COMMAND_LIST_LENGTH_64_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 2, 1, 4, v)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_KEY_EXTEND_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 2, 0, 1, r)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_KEY_EXTEND_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 2, 0, 1, v)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_IS_MULTICAST_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 3, 7, 1, r)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_IS_MULTICAST_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 3, 7, 1, v)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_PROTOCOL_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 3, 0, 7, r)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_PROTOCOL_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 3, 0, 7, v)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_NUMBER_OF_TAGS_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 4, 6, 2, r)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_NUMBER_OF_TAGS_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 4, 6, 2, v)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_SRC_IP_READ(r, p)                                  MREAD_32((uint8_t *)p + 8, r)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_SRC_IP_WRITE(v, p)                                 MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_DST_IP_READ(r, p)                                  MREAD_32((uint8_t *)p + 12, r)
+#define RDD_FC_MCAST_CONNECTION_ENTRY_DST_IP_WRITE(v, p)                                 MWRITE_32((uint8_t *)p + 12, v)
+
+typedef struct
+{
+	uint32_t	state                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2             	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	lag_port              	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_wred_high_prio     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_header_length      	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_push               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_command_list_length	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	queue                 	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_offset             	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_PORT_CONTEXT_ENTRY_DTS;
+
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_STATE_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_STATE_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_LAG_PORT_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 1, 6, 2, r)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_LAG_PORT_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 1, 6, 2, v)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_IS_WRED_HIGH_PRIO_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 1, 5, 1, r)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_IS_WRED_HIGH_PRIO_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 1, 5, 1, v)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_L2_HEADER_LENGTH_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 1, 0, 5, r)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_L2_HEADER_LENGTH_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 1, 0, 5, v)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_L2_PUSH_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 2, 7, 1, r)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_L2_PUSH_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 2, 7, 1, v)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_L2_COMMAND_LIST_LENGTH_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 2, 0, 7, r)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_L2_COMMAND_LIST_LENGTH_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 2, 0, 7, v)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_QUEUE_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 3, 5, 3, r)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_QUEUE_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 3, 5, 3, v)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_L2_OFFSET_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 3, 0, 5, r)
+#define RDD_FC_MCAST_PORT_CONTEXT_ENTRY_L2_OFFSET_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 3, 0, 5, v)
+
+typedef struct
+{
+	uint32_t	reserved_fw_only	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONNECTION_TABLE_CONFIG_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DATA_POINTER_DUMMY_TARGET_DTS;
+
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_PTR()	( RDD_DS_DATA_POINTER_DUMMY_TARGET_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DATA_POINTER_DUMMY_TARGET_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved_fw_only	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONTEXT_TABLE_CONFIG_DTS;
+
+
+typedef struct
+{
+	uint8_t	ih_buffer 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PARALLEL_PROCESSING_ENTRY_DTS;
+
+#define RDD_PARALLEL_PROCESSING_ENTRY_IH_BUFFER_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_PARALLEL_PROCESSING_ENTRY_IH_BUFFER_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+#if defined DSL_63138
+
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_ENTRY_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR()	( RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	reserved_fw_only	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PARALLEL_PROCESSING_TASK_REORDER_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_TASK_REORDER_ENTRY_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_PTR()	( RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_PTR()	( RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE     10
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_DTS;
+
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_PTR()	( RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_ABSOLUTE_TX_BBH_COUNTER_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	head_pointer             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tail_pointer             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	guaranteed_free_count    	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	non_guaranteed_free_count	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	guaranteed_threshold     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_DTS;
+
+#define RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_HEAD_POINTER_READ(r, p)                              MREAD_16((uint8_t *)p, r)
+#define RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_HEAD_POINTER_WRITE(v, p)                             MWRITE_16((uint8_t *)p, v)
+#define RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_TAIL_POINTER_READ(r, p)                              MREAD_16((uint8_t *)p + 2, r)
+#define RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_TAIL_POINTER_WRITE(v, p)                             MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_FREE_COUNT_READ(r, p)                     MREAD_16((uint8_t *)p + 4, r)
+#define RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_FREE_COUNT_WRITE(v, p)                    MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_NON_GUARANTEED_FREE_COUNT_READ(r, p)                 MREAD_16((uint8_t *)p + 6, r)
+#define RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_NON_GUARANTEED_FREE_COUNT_WRITE(v, p)                MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_THRESHOLD_READ(r, p)                      MREAD_16((uint8_t *)p + 8, r)
+#define RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_THRESHOLD_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 8, v)
+
+typedef struct
+{
+	uint32_t	reserved_fw_only	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DEBUG_BUFFER_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_DEBUG_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_DEBUG_BUFFER_ENTRY_DTS	entry[ RDD_DS_DEBUG_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DEBUG_BUFFER_DTS;
+
+#define RDD_DS_DEBUG_BUFFER_PTR()	( RDD_DS_DEBUG_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DEBUG_BUFFER_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	ownership 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	reserved  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	skb_index 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FREE_SKB_INDEXES_FIFO_ENTRY_DTS;
+
+#define RDD_FREE_SKB_INDEXES_FIFO_ENTRY_OWNERSHIP_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_FREE_SKB_INDEXES_FIFO_ENTRY_OWNERSHIP_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_FREE_SKB_INDEXES_FIFO_ENTRY_SKB_INDEX_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p, 0, 14, r)
+#define RDD_FREE_SKB_INDEXES_FIFO_ENTRY_SKB_INDEX_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p, 0, 14, v)
+
+#define RDD_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+typedef struct
+{
+	RDD_FREE_SKB_INDEXES_FIFO_ENTRY_DTS	entry[ RDD_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS;
+
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined DSL_63138
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_FLOW_RING_DROP_COUNTER_DTS;
+
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_PTR()	( RDD_DS_DHD_FLOW_RING_DROP_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_FLOW_RING_DROP_COUNTER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_PTR()	( RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS )
+
+#endif
+
+#define RDD_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+typedef struct
+{
+	RDD_FREE_SKB_INDEXES_FIFO_ENTRY_DTS	entry[ RDD_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS;
+
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#define RDD_HASH_BUFFER_RESERVED_FW_ONLY_NUMBER	4
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_HASH_BUFFER_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_HASH_BUFFER_DTS;
+
+#if defined DSL_63138
+
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_RX_DIRECT_DESCRIPTORS_DTS;
+
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_PTR()	( RDD_GPON_RX_DIRECT_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GPON_RX_DIRECT_DESCRIPTORS_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	rx_bbh_descriptor_0           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rx_bbh_descriptor_1           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_bbh_descriptor_0           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_bbh_descriptor_1           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rx_packets                    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rx_octets                     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_packets                    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_octets                     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dropped_packets               	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dropped_no_bpm_buffer         	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dropped_parse_failed          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dropped_linear_length_invalid 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	queue_full                    	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	summary                       	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_header_offset              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_header_length              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_total_length               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_id                         	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_fragment_flags_reserved    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_fragment_flags_df          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_fragment_flags_mf          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_fragment_offset            	:13	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_flags                      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_protocol                   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipv4_csum                     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_header_length          	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	seg_count                     	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	nr_frags                      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	frag_index                    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_udp_header_offset         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_udp_header_length         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_udp_total_length          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_sequence                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_flags                     	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	version                       	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_udp_csum                  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mss                           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mss_adjust                    	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	seg_length                    	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	seg_bytes_left                	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	max_chunk_length              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	chunk_bytes_left              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_bytes_left            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_ptr                   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_length                	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	linear_length                 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_packet_ptr                 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_packet_length              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	udp_first_packet_length       	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	udp_first_packet_ptr          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	udp_first_packet_buffer_number	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bpm_buffer_number             	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length                 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0                     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipv6_ip_id                    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	auth_state_3                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	debug_0                       	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_CONTEXT_ENTRY_DTS;
+
+#define RDD_GSO_CONTEXT_ENTRY_RX_BBH_DESCRIPTOR_0_READ(r, p)                            MREAD_32((uint8_t *)p, r)
+#define RDD_GSO_CONTEXT_ENTRY_RX_BBH_DESCRIPTOR_0_WRITE(v, p)                           MWRITE_32((uint8_t *)p, v)
+#define RDD_GSO_CONTEXT_ENTRY_RX_BBH_DESCRIPTOR_1_READ(r, p)                            MREAD_32((uint8_t *)p + 4, r)
+#define RDD_GSO_CONTEXT_ENTRY_RX_BBH_DESCRIPTOR_1_WRITE(v, p)                           MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_GSO_CONTEXT_ENTRY_TX_BBH_DESCRIPTOR_0_READ(r, p)                            MREAD_32((uint8_t *)p + 8, r)
+#define RDD_GSO_CONTEXT_ENTRY_TX_BBH_DESCRIPTOR_0_WRITE(v, p)                           MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_GSO_CONTEXT_ENTRY_TX_BBH_DESCRIPTOR_1_READ(r, p)                            MREAD_32((uint8_t *)p + 12, r)
+#define RDD_GSO_CONTEXT_ENTRY_TX_BBH_DESCRIPTOR_1_WRITE(v, p)                           MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_GSO_CONTEXT_ENTRY_RX_PACKETS_READ(r, p)                                     MREAD_32((uint8_t *)p + 16, r)
+#define RDD_GSO_CONTEXT_ENTRY_RX_PACKETS_WRITE(v, p)                                    MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_GSO_CONTEXT_ENTRY_RX_OCTETS_READ(r, p)                                      MREAD_32((uint8_t *)p + 20, r)
+#define RDD_GSO_CONTEXT_ENTRY_RX_OCTETS_WRITE(v, p)                                     MWRITE_32((uint8_t *)p + 20, v)
+#define RDD_GSO_CONTEXT_ENTRY_TX_PACKETS_READ(r, p)                                     MREAD_32((uint8_t *)p + 24, r)
+#define RDD_GSO_CONTEXT_ENTRY_TX_PACKETS_WRITE(v, p)                                    MWRITE_32((uint8_t *)p + 24, v)
+#define RDD_GSO_CONTEXT_ENTRY_TX_OCTETS_READ(r, p)                                      MREAD_32((uint8_t *)p + 28, r)
+#define RDD_GSO_CONTEXT_ENTRY_TX_OCTETS_WRITE(v, p)                                     MWRITE_32((uint8_t *)p + 28, v)
+#define RDD_GSO_CONTEXT_ENTRY_DROPPED_PACKETS_READ(r, p)                                MREAD_32((uint8_t *)p + 32, r)
+#define RDD_GSO_CONTEXT_ENTRY_DROPPED_PACKETS_WRITE(v, p)                               MWRITE_32((uint8_t *)p + 32, v)
+#define RDD_GSO_CONTEXT_ENTRY_DROPPED_NO_BPM_BUFFER_READ(r, p)                          MREAD_16((uint8_t *)p + 36, r)
+#define RDD_GSO_CONTEXT_ENTRY_DROPPED_NO_BPM_BUFFER_WRITE(v, p)                         MWRITE_16((uint8_t *)p + 36, v)
+#define RDD_GSO_CONTEXT_ENTRY_DROPPED_PARSE_FAILED_READ(r, p)                           MREAD_16((uint8_t *)p + 38, r)
+#define RDD_GSO_CONTEXT_ENTRY_DROPPED_PARSE_FAILED_WRITE(v, p)                          MWRITE_16((uint8_t *)p + 38, v)
+#define RDD_GSO_CONTEXT_ENTRY_DROPPED_LINEAR_LENGTH_INVALID_READ(r, p)                  MREAD_16((uint8_t *)p + 40, r)
+#define RDD_GSO_CONTEXT_ENTRY_DROPPED_LINEAR_LENGTH_INVALID_WRITE(v, p)                 MWRITE_16((uint8_t *)p + 40, v)
+#define RDD_GSO_CONTEXT_ENTRY_QUEUE_FULL_READ(r, p)                                     MREAD_16((uint8_t *)p + 42, r)
+#define RDD_GSO_CONTEXT_ENTRY_QUEUE_FULL_WRITE(v, p)                                    MWRITE_16((uint8_t *)p + 42, v)
+#define RDD_GSO_CONTEXT_ENTRY_SUMMARY_READ(r, p)                                        MREAD_32((uint8_t *)p + 44, r)
+#define RDD_GSO_CONTEXT_ENTRY_SUMMARY_WRITE(v, p)                                       MWRITE_32((uint8_t *)p + 44, v)
+#define RDD_GSO_CONTEXT_ENTRY_IP_HEADER_OFFSET_READ(r, p)                               MREAD_8((uint8_t *)p + 48, r)
+#define RDD_GSO_CONTEXT_ENTRY_IP_HEADER_OFFSET_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 48, v)
+#define RDD_GSO_CONTEXT_ENTRY_IP_HEADER_LENGTH_READ(r, p)                               MREAD_8((uint8_t *)p + 49, r)
+#define RDD_GSO_CONTEXT_ENTRY_IP_HEADER_LENGTH_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 49, v)
+#define RDD_GSO_CONTEXT_ENTRY_IP_TOTAL_LENGTH_READ(r, p)                                MREAD_16((uint8_t *)p + 50, r)
+#define RDD_GSO_CONTEXT_ENTRY_IP_TOTAL_LENGTH_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 50, v)
+#define RDD_GSO_CONTEXT_ENTRY_IP_ID_READ(r, p)                                          MREAD_16((uint8_t *)p + 52, r)
+#define RDD_GSO_CONTEXT_ENTRY_IP_ID_WRITE(v, p)                                         MWRITE_16((uint8_t *)p + 52, v)
+#define RDD_GSO_CONTEXT_ENTRY_IP_FRAGMENT_FLAGS_RESERVED_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 54, 7, 1, r)
+#define RDD_GSO_CONTEXT_ENTRY_IP_FRAGMENT_FLAGS_RESERVED_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 54, 7, 1, v)
+#define RDD_GSO_CONTEXT_ENTRY_IP_FRAGMENT_FLAGS_DF_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 54, 6, 1, r)
+#define RDD_GSO_CONTEXT_ENTRY_IP_FRAGMENT_FLAGS_DF_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 54, 6, 1, v)
+#define RDD_GSO_CONTEXT_ENTRY_IP_FRAGMENT_FLAGS_MF_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 54, 5, 1, r)
+#define RDD_GSO_CONTEXT_ENTRY_IP_FRAGMENT_FLAGS_MF_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 54, 5, 1, v)
+#define RDD_GSO_CONTEXT_ENTRY_IP_FRAGMENT_OFFSET_READ(r, p)                             FIELD_MREAD_16((uint8_t *)p + 54, 0, 13, r)
+#define RDD_GSO_CONTEXT_ENTRY_IP_FRAGMENT_OFFSET_WRITE(v, p)                            FIELD_MWRITE_16((uint8_t *)p + 54, 0, 13, v)
+#define RDD_GSO_CONTEXT_ENTRY_IP_FLAGS_READ(r, p)                                       MREAD_8((uint8_t *)p + 56, r)
+#define RDD_GSO_CONTEXT_ENTRY_IP_FLAGS_WRITE(v, p)                                      MWRITE_8((uint8_t *)p + 56, v)
+#define RDD_GSO_CONTEXT_ENTRY_IP_PROTOCOL_READ(r, p)                                    MREAD_8((uint8_t *)p + 57, r)
+#define RDD_GSO_CONTEXT_ENTRY_IP_PROTOCOL_WRITE(v, p)                                   MWRITE_8((uint8_t *)p + 57, v)
+#define RDD_GSO_CONTEXT_ENTRY_IPV4_CSUM_READ(r, p)                                      MREAD_16((uint8_t *)p + 58, r)
+#define RDD_GSO_CONTEXT_ENTRY_IPV4_CSUM_WRITE(v, p)                                     MWRITE_16((uint8_t *)p + 58, v)
+#define RDD_GSO_CONTEXT_ENTRY_PACKET_HEADER_LENGTH_READ(r, p)                           MREAD_8((uint8_t *)p + 60, r)
+#define RDD_GSO_CONTEXT_ENTRY_PACKET_HEADER_LENGTH_WRITE(v, p)                          MWRITE_8((uint8_t *)p + 60, v)
+#define RDD_GSO_CONTEXT_ENTRY_SEG_COUNT_READ(r, p)                                      MREAD_8((uint8_t *)p + 61, r)
+#define RDD_GSO_CONTEXT_ENTRY_SEG_COUNT_WRITE(v, p)                                     MWRITE_8((uint8_t *)p + 61, v)
+#define RDD_GSO_CONTEXT_ENTRY_NR_FRAGS_READ(r, p)                                       MREAD_8((uint8_t *)p + 62, r)
+#define RDD_GSO_CONTEXT_ENTRY_NR_FRAGS_WRITE(v, p)                                      MWRITE_8((uint8_t *)p + 62, v)
+#define RDD_GSO_CONTEXT_ENTRY_FRAG_INDEX_READ(r, p)                                     MREAD_8((uint8_t *)p + 63, r)
+#define RDD_GSO_CONTEXT_ENTRY_FRAG_INDEX_WRITE(v, p)                                    MWRITE_8((uint8_t *)p + 63, v)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_UDP_HEADER_OFFSET_READ(r, p)                          MREAD_8((uint8_t *)p + 64, r)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_UDP_HEADER_OFFSET_WRITE(v, p)                         MWRITE_8((uint8_t *)p + 64, v)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_UDP_HEADER_LENGTH_READ(r, p)                          MREAD_8((uint8_t *)p + 65, r)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_UDP_HEADER_LENGTH_WRITE(v, p)                         MWRITE_8((uint8_t *)p + 65, v)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_UDP_TOTAL_LENGTH_READ(r, p)                           MREAD_16((uint8_t *)p + 66, r)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_UDP_TOTAL_LENGTH_WRITE(v, p)                          MWRITE_16((uint8_t *)p + 66, v)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_SEQUENCE_READ(r, p)                                   MREAD_32((uint8_t *)p + 68, r)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_SEQUENCE_WRITE(v, p)                                  MWRITE_32((uint8_t *)p + 68, v)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_FLAGS_READ(r, p)                                      MREAD_8((uint8_t *)p + 72, r)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_FLAGS_WRITE(v, p)                                     MWRITE_8((uint8_t *)p + 72, v)
+#define RDD_GSO_CONTEXT_ENTRY_VERSION_READ(r, p)                                        MREAD_8((uint8_t *)p + 73, r)
+#define RDD_GSO_CONTEXT_ENTRY_VERSION_WRITE(v, p)                                       MWRITE_8((uint8_t *)p + 73, v)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_UDP_CSUM_READ(r, p)                                   MREAD_16((uint8_t *)p + 74, r)
+#define RDD_GSO_CONTEXT_ENTRY_TCP_UDP_CSUM_WRITE(v, p)                                  MWRITE_16((uint8_t *)p + 74, v)
+#define RDD_GSO_CONTEXT_ENTRY_MSS_READ(r, p)                                            MREAD_16((uint8_t *)p + 76, r)
+#define RDD_GSO_CONTEXT_ENTRY_MSS_WRITE(v, p)                                           MWRITE_16((uint8_t *)p + 76, v)
+#define RDD_GSO_CONTEXT_ENTRY_MSS_ADJUST_READ(r, p)                                     MREAD_16((uint8_t *)p + 78, r)
+#define RDD_GSO_CONTEXT_ENTRY_MSS_ADJUST_WRITE(v, p)                                    MWRITE_16((uint8_t *)p + 78, v)
+#define RDD_GSO_CONTEXT_ENTRY_SEG_LENGTH_READ(r, p)                                     MREAD_16((uint8_t *)p + 80, r)
+#define RDD_GSO_CONTEXT_ENTRY_SEG_LENGTH_WRITE(v, p)                                    MWRITE_16((uint8_t *)p + 80, v)
+#define RDD_GSO_CONTEXT_ENTRY_SEG_BYTES_LEFT_READ(r, p)                                 MREAD_16((uint8_t *)p + 82, r)
+#define RDD_GSO_CONTEXT_ENTRY_SEG_BYTES_LEFT_WRITE(v, p)                                MWRITE_16((uint8_t *)p + 82, v)
+#define RDD_GSO_CONTEXT_ENTRY_MAX_CHUNK_LENGTH_READ(r, p)                               MREAD_8((uint8_t *)p + 84, r)
+#define RDD_GSO_CONTEXT_ENTRY_MAX_CHUNK_LENGTH_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 84, v)
+#define RDD_GSO_CONTEXT_ENTRY_CHUNK_BYTES_LEFT_READ(r, p)                               MREAD_8((uint8_t *)p + 85, r)
+#define RDD_GSO_CONTEXT_ENTRY_CHUNK_BYTES_LEFT_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 85, v)
+#define RDD_GSO_CONTEXT_ENTRY_PAYLOAD_BYTES_LEFT_READ(r, p)                             MREAD_16((uint8_t *)p + 86, r)
+#define RDD_GSO_CONTEXT_ENTRY_PAYLOAD_BYTES_LEFT_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 86, v)
+#define RDD_GSO_CONTEXT_ENTRY_PAYLOAD_PTR_READ(r, p)                                    MREAD_32((uint8_t *)p + 88, r)
+#define RDD_GSO_CONTEXT_ENTRY_PAYLOAD_PTR_WRITE(v, p)                                   MWRITE_32((uint8_t *)p + 88, v)
+#define RDD_GSO_CONTEXT_ENTRY_PAYLOAD_LENGTH_READ(r, p)                                 MREAD_16((uint8_t *)p + 92, r)
+#define RDD_GSO_CONTEXT_ENTRY_PAYLOAD_LENGTH_WRITE(v, p)                                MWRITE_16((uint8_t *)p + 92, v)
+#define RDD_GSO_CONTEXT_ENTRY_LINEAR_LENGTH_READ(r, p)                                  MREAD_16((uint8_t *)p + 94, r)
+#define RDD_GSO_CONTEXT_ENTRY_LINEAR_LENGTH_WRITE(v, p)                                 MWRITE_16((uint8_t *)p + 94, v)
+#define RDD_GSO_CONTEXT_ENTRY_TX_PACKET_PTR_READ(r, p)                                  MREAD_32((uint8_t *)p + 96, r)
+#define RDD_GSO_CONTEXT_ENTRY_TX_PACKET_PTR_WRITE(v, p)                                 MWRITE_32((uint8_t *)p + 96, v)
+#define RDD_GSO_CONTEXT_ENTRY_TX_PACKET_LENGTH_READ(r, p)                               MREAD_16((uint8_t *)p + 100, r)
+#define RDD_GSO_CONTEXT_ENTRY_TX_PACKET_LENGTH_WRITE(v, p)                              MWRITE_16((uint8_t *)p + 100, v)
+#define RDD_GSO_CONTEXT_ENTRY_UDP_FIRST_PACKET_LENGTH_READ(r, p)                        MREAD_16((uint8_t *)p + 102, r)
+#define RDD_GSO_CONTEXT_ENTRY_UDP_FIRST_PACKET_LENGTH_WRITE(v, p)                       MWRITE_16((uint8_t *)p + 102, v)
+#define RDD_GSO_CONTEXT_ENTRY_UDP_FIRST_PACKET_PTR_READ(r, p)                           MREAD_32((uint8_t *)p + 104, r)
+#define RDD_GSO_CONTEXT_ENTRY_UDP_FIRST_PACKET_PTR_WRITE(v, p)                          MWRITE_32((uint8_t *)p + 104, v)
+#define RDD_GSO_CONTEXT_ENTRY_UDP_FIRST_PACKET_BUFFER_NUMBER_READ(r, p)                 MREAD_32((uint8_t *)p + 108, r)
+#define RDD_GSO_CONTEXT_ENTRY_UDP_FIRST_PACKET_BUFFER_NUMBER_WRITE(v, p)                MWRITE_32((uint8_t *)p + 108, v)
+#define RDD_GSO_CONTEXT_ENTRY_BPM_BUFFER_NUMBER_READ(r, p)                              MREAD_32((uint8_t *)p + 112, r)
+#define RDD_GSO_CONTEXT_ENTRY_BPM_BUFFER_NUMBER_WRITE(v, p)                             MWRITE_32((uint8_t *)p + 112, v)
+#define RDD_GSO_CONTEXT_ENTRY_PACKET_LENGTH_READ(r, p)                                  MREAD_16((uint8_t *)p + 116, r)
+#define RDD_GSO_CONTEXT_ENTRY_PACKET_LENGTH_WRITE(v, p)                                 MWRITE_16((uint8_t *)p + 116, v)
+#define RDD_GSO_CONTEXT_ENTRY_IPV6_IP_ID_READ(r, p)                                     MREAD_32((uint8_t *)p + 120, r)
+#define RDD_GSO_CONTEXT_ENTRY_IPV6_IP_ID_WRITE(v, p)                                    MWRITE_32((uint8_t *)p + 120, v)
+#define RDD_GSO_CONTEXT_ENTRY_AUTH_STATE_3_READ(r, p)                                   MREAD_32((uint8_t *)p + 124, r)
+#define RDD_GSO_CONTEXT_ENTRY_AUTH_STATE_3_WRITE(v, p)                                  MWRITE_32((uint8_t *)p + 124, v)
+#define RDD_GSO_CONTEXT_ENTRY_DEBUG_0_READ(r, p)                                        MREAD_32((uint8_t *)p + 128, r)
+#define RDD_GSO_CONTEXT_ENTRY_DEBUG_0_WRITE(v, p)                                       MWRITE_32((uint8_t *)p + 128, v)
+#if defined DSL_63138
+
+#define RDD_DS_FW_MAC_ADDRS_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_FW_MAC_ADDRS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FW_MAC_ADDRS_DTS;
+
+#define RDD_DS_FW_MAC_ADDRS_PTR()	( RDD_DS_FW_MAC_ADDRS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FW_MAC_ADDRS_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	dhd_context_ptr 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_host_buf_ptr	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_l2_buf      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ret_addr        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ENQUEUE_PCI_PACKET_CONTEXT_ENTRY_DTS;
+
+#define RDD_ENQUEUE_PCI_PACKET_CONTEXT_ENTRY_DHD_CONTEXT_PTR_READ(r, p)                  MREAD_16((uint8_t *)p, r)
+#define RDD_ENQUEUE_PCI_PACKET_CONTEXT_ENTRY_DHD_CONTEXT_PTR_WRITE(v, p)                 MWRITE_16((uint8_t *)p, v)
+#define RDD_ENQUEUE_PCI_PACKET_CONTEXT_ENTRY_DHD_HOST_BUF_PTR_READ(r, p)                 MREAD_16((uint8_t *)p + 2, r)
+#define RDD_ENQUEUE_PCI_PACKET_CONTEXT_ENTRY_DHD_HOST_BUF_PTR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_ENQUEUE_PCI_PACKET_CONTEXT_ENTRY_DHD_L2_BUF_READ(r, p)                       MREAD_16((uint8_t *)p + 4, r)
+#define RDD_ENQUEUE_PCI_PACKET_CONTEXT_ENTRY_DHD_L2_BUF_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_ENQUEUE_PCI_PACKET_CONTEXT_ENTRY_RET_ADDR_READ(r, p)                         MREAD_16((uint8_t *)p + 6, r)
+#define RDD_ENQUEUE_PCI_PACKET_CONTEXT_ENTRY_RET_ADDR_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 6, v)
+#if defined DSL_63138
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_PTR()	( RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	physical_port	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS;
+
+#define RDD_BROADCOM_SWITCH_PORT_MAPPING_PHYSICAL_PORT_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_BROADCOM_SWITCH_PORT_MAPPING_PHYSICAL_PORT_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+#if defined DSL_63138
+
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_PTR()	( RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_ETH_TX_SCRATCH_SIZE     16
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_ETH_TX_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_SCRATCH_DTS;
+
+#define RDD_ETH_TX_SCRATCH_PTR()	( RDD_ETH_TX_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_SCRATCH_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	mtu_minus_40                      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	us_padding_max_size               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	us_padding_cpu_max_size           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	drop_precedence_eligibility_vector	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_ether_type_1               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_ether_type_2               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_ether_type_3               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	timer_scheduler_period            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	active_policers_vector            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	policers_period                   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ds_rate_shaper_timer              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	us_rate_controller_timer          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	us_rate_limit_sustain_budget_limit	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	hash_based_forwarding_port_count  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inter_lan_scheduling_mode         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	broadcom_switch_port              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mirroring_port                    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ds_connection_miss_action         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	us_pci_flow_cache_enable          	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	global_ingress_config             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pci_ls_dp_eligibility_vector      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ds_ingress_policers_mode          	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	debug_mode                        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SYSTEM_CONFIGURATION_DTS;
+
+#define RDD_SYSTEM_CONFIGURATION_MTU_MINUS_40_READ(r, p)                                       MREAD_16((uint8_t *)p, r)
+#define RDD_SYSTEM_CONFIGURATION_MTU_MINUS_40_WRITE(v, p)                                      MWRITE_16((uint8_t *)p, v)
+#define RDD_SYSTEM_CONFIGURATION_US_PADDING_MAX_SIZE_READ(r, p)                                MREAD_16((uint8_t *)p + 2, r)
+#define RDD_SYSTEM_CONFIGURATION_US_PADDING_MAX_SIZE_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_SYSTEM_CONFIGURATION_US_PADDING_CPU_MAX_SIZE_READ(r, p)                            MREAD_16((uint8_t *)p + 4, r)
+#define RDD_SYSTEM_CONFIGURATION_US_PADDING_CPU_MAX_SIZE_WRITE(v, p)                           MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_SYSTEM_CONFIGURATION_DROP_PRECEDENCE_ELIGIBILITY_VECTOR_READ(r, p)                 MREAD_16((uint8_t *)p + 6, r)
+#define RDD_SYSTEM_CONFIGURATION_DROP_PRECEDENCE_ELIGIBILITY_VECTOR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_SYSTEM_CONFIGURATION_EGRESS_ETHER_TYPE_1_READ(r, p)                                MREAD_16((uint8_t *)p + 8, r)
+#define RDD_SYSTEM_CONFIGURATION_EGRESS_ETHER_TYPE_1_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_SYSTEM_CONFIGURATION_EGRESS_ETHER_TYPE_2_READ(r, p)                                MREAD_16((uint8_t *)p + 10, r)
+#define RDD_SYSTEM_CONFIGURATION_EGRESS_ETHER_TYPE_2_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_SYSTEM_CONFIGURATION_EGRESS_ETHER_TYPE_3_READ(r, p)                                MREAD_16((uint8_t *)p + 12, r)
+#define RDD_SYSTEM_CONFIGURATION_EGRESS_ETHER_TYPE_3_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_SYSTEM_CONFIGURATION_TIMER_SCHEDULER_PERIOD_READ(r, p)                             MREAD_16((uint8_t *)p + 14, r)
+#define RDD_SYSTEM_CONFIGURATION_TIMER_SCHEDULER_PERIOD_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_SYSTEM_CONFIGURATION_ACTIVE_POLICERS_VECTOR_READ(r, p)                             MREAD_16((uint8_t *)p + 16, r)
+#define RDD_SYSTEM_CONFIGURATION_ACTIVE_POLICERS_VECTOR_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 16, v)
+#define RDD_SYSTEM_CONFIGURATION_POLICERS_PERIOD_READ(r, p)                                    MREAD_16((uint8_t *)p + 18, r)
+#define RDD_SYSTEM_CONFIGURATION_POLICERS_PERIOD_WRITE(v, p)                                   MWRITE_16((uint8_t *)p + 18, v)
+#define RDD_SYSTEM_CONFIGURATION_DS_RATE_SHAPER_TIMER_READ(r, p)                               MREAD_16((uint8_t *)p + 20, r)
+#define RDD_SYSTEM_CONFIGURATION_DS_RATE_SHAPER_TIMER_WRITE(v, p)                              MWRITE_16((uint8_t *)p + 20, v)
+#define RDD_SYSTEM_CONFIGURATION_US_RATE_CONTROLLER_TIMER_READ(r, p)                           MREAD_16((uint8_t *)p + 22, r)
+#define RDD_SYSTEM_CONFIGURATION_US_RATE_CONTROLLER_TIMER_WRITE(v, p)                          MWRITE_16((uint8_t *)p + 22, v)
+#define RDD_SYSTEM_CONFIGURATION_US_RATE_LIMIT_SUSTAIN_BUDGET_LIMIT_READ(r, p)                 MREAD_8((uint8_t *)p + 24, r)
+#define RDD_SYSTEM_CONFIGURATION_US_RATE_LIMIT_SUSTAIN_BUDGET_LIMIT_WRITE(v, p)                MWRITE_8((uint8_t *)p + 24, v)
+#define RDD_SYSTEM_CONFIGURATION_HASH_BASED_FORWARDING_PORT_COUNT_READ(r, p)                   MREAD_8((uint8_t *)p + 25, r)
+#define RDD_SYSTEM_CONFIGURATION_HASH_BASED_FORWARDING_PORT_COUNT_WRITE(v, p)                  MWRITE_8((uint8_t *)p + 25, v)
+#define RDD_SYSTEM_CONFIGURATION_INTER_LAN_SCHEDULING_MODE_READ(r, p)                          MREAD_8((uint8_t *)p + 26, r)
+#define RDD_SYSTEM_CONFIGURATION_INTER_LAN_SCHEDULING_MODE_WRITE(v, p)                         MWRITE_8((uint8_t *)p + 26, v)
+#define RDD_SYSTEM_CONFIGURATION_BROADCOM_SWITCH_PORT_READ(r, p)                               MREAD_8((uint8_t *)p + 27, r)
+#define RDD_SYSTEM_CONFIGURATION_BROADCOM_SWITCH_PORT_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 27, v)
+#define RDD_SYSTEM_CONFIGURATION_MIRRORING_PORT_READ(r, p)                                     MREAD_8((uint8_t *)p + 28, r)
+#define RDD_SYSTEM_CONFIGURATION_MIRRORING_PORT_WRITE(v, p)                                    MWRITE_8((uint8_t *)p + 28, v)
+#define RDD_SYSTEM_CONFIGURATION_DS_CONNECTION_MISS_ACTION_READ(r, p)                          MREAD_8((uint8_t *)p + 29, r)
+#define RDD_SYSTEM_CONFIGURATION_DS_CONNECTION_MISS_ACTION_WRITE(v, p)                         MWRITE_8((uint8_t *)p + 29, v)
+#define RDD_SYSTEM_CONFIGURATION_US_PCI_FLOW_CACHE_ENABLE_READ(r, p)                           MREAD_8((uint8_t *)p + 30, r)
+#define RDD_SYSTEM_CONFIGURATION_US_PCI_FLOW_CACHE_ENABLE_WRITE(v, p)                          MWRITE_8((uint8_t *)p + 30, v)
+#define RDD_SYSTEM_CONFIGURATION_GLOBAL_INGRESS_CONFIG_READ(r, p)                              MREAD_8((uint8_t *)p + 31, r)
+#define RDD_SYSTEM_CONFIGURATION_GLOBAL_INGRESS_CONFIG_WRITE(v, p)                             MWRITE_8((uint8_t *)p + 31, v)
+#define RDD_SYSTEM_CONFIGURATION_PCI_LS_DP_ELIGIBILITY_VECTOR_READ(r, p)                       MREAD_16((uint8_t *)p + 32, r)
+#define RDD_SYSTEM_CONFIGURATION_PCI_LS_DP_ELIGIBILITY_VECTOR_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 32, v)
+#define RDD_SYSTEM_CONFIGURATION_DS_INGRESS_POLICERS_MODE_READ(r, p)                           MREAD_8((uint8_t *)p + 34, r)
+#define RDD_SYSTEM_CONFIGURATION_DS_INGRESS_POLICERS_MODE_WRITE(v, p)                          MWRITE_8((uint8_t *)p + 34, v)
+#define RDD_SYSTEM_CONFIGURATION_DEBUG_MODE_READ(r, p)                                         MREAD_8((uint8_t *)p + 35, r)
+#define RDD_SYSTEM_CONFIGURATION_DEBUG_MODE_WRITE(v, p)                                        MWRITE_8((uint8_t *)p + 35, v)
+#if defined DSL_63138
+
+#define RDD_GSO_TX_DHD_L2_BUFFER_SIZE     22
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_GSO_TX_DHD_L2_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_TX_DHD_L2_BUFFER_DTS;
+
+#define RDD_GSO_TX_DHD_L2_BUFFER_PTR()	( RDD_GSO_TX_DHD_L2_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_TX_DHD_L2_BUFFER_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPTV_COUNTERS_BUFFER_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_PTR()	( RDD_DS_DHD_TX_POST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	sa_desc_idx	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_SA_DESC_CAM_DTS;
+
+#define RDD_IPSEC_SA_DESC_CAM_SA_DESC_IDX_READ(r, p)                 MREAD_16((uint8_t *)p, r)
+#define RDD_IPSEC_SA_DESC_CAM_SA_DESC_IDX_WRITE(v, p)                MWRITE_16((uint8_t *)p, v)
+#define RDD_IPSEC_SA_DESC_CAM_SA_DESC_IDX_L_READ( wv )               FIELD_GET( wv, 0, 16 )
+#define RDD_IPSEC_SA_DESC_CAM_SA_DESC_IDX_L_WRITE( v, wv )           FIELD_SET( v, 0, 16, wv )
+#if defined DSL_63138
+
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_CAM_DTS	entry[ RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_SA_DESC_CAM_TABLE_DTS;
+
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_PTR()	( RDD_IPSEC_DS_SA_DESC_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_SA_DESC_CAM_TABLE_ADDRESS )
+
+#endif
+#define RDD_SIXTEEN_BYTES_RESERVED_FW_ONLY_NUMBER	4
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_SIXTEEN_BYTES_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SIXTEEN_BYTES_DTS;
+
+#define RDD_RUNNER_FLOW_IH_RESPONSE_RESERVED_FW_ONLY_NUMBER	2
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_RUNNER_FLOW_IH_RESPONSE_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FLOW_IH_RESPONSE_DTS;
+
+#define RDD_GSO_DESC_ENTRY_FRAG_DATA_NUMBER	18
+#define RDD_GSO_DESC_ENTRY_FRAG_LEN_NUMBER	18
+
+typedef struct
+{
+	uint32_t	data                                              	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	len                                               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	linear_len                                        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mss                                               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0                                         	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_allocated                                      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	nr_frags                                          	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                                         	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	frag_data[RDD_GSO_DESC_ENTRY_FRAG_DATA_NUMBER];
+	uint16_t	frag_len[RDD_GSO_DESC_ENTRY_FRAG_LEN_NUMBER];
+	uint32_t	reserved2                                         	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_DESC_ENTRY_DTS;
+
+#define RDD_GSO_DESC_ENTRY_DATA_READ(r, p)                         MREAD_32((uint8_t *)p, r)
+#define RDD_GSO_DESC_ENTRY_DATA_WRITE(v, p)                        MWRITE_32((uint8_t *)p, v)
+#define RDD_GSO_DESC_ENTRY_LEN_READ(r, p)                          MREAD_16((uint8_t *)p + 4, r)
+#define RDD_GSO_DESC_ENTRY_LEN_WRITE(v, p)                         MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_GSO_DESC_ENTRY_LINEAR_LEN_READ(r, p)                   MREAD_16((uint8_t *)p + 6, r)
+#define RDD_GSO_DESC_ENTRY_LINEAR_LEN_WRITE(v, p)                  MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_GSO_DESC_ENTRY_MSS_READ(r, p)                          MREAD_16((uint8_t *)p + 8, r)
+#define RDD_GSO_DESC_ENTRY_MSS_WRITE(v, p)                         MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_GSO_DESC_ENTRY_IS_ALLOCATED_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 10, 0, 1, r)
+#define RDD_GSO_DESC_ENTRY_IS_ALLOCATED_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 10, 0, 1, v)
+#define RDD_GSO_DESC_ENTRY_NR_FRAGS_READ(r, p)                     MREAD_8((uint8_t *)p + 11, r)
+#define RDD_GSO_DESC_ENTRY_NR_FRAGS_WRITE(v, p)                    MWRITE_8((uint8_t *)p + 11, v)
+#define RDD_GSO_DESC_ENTRY_FRAG_DATA_READ(r, p, i)                 MREAD_I_32((uint8_t *)p + 16, i, r)
+#define RDD_GSO_DESC_ENTRY_FRAG_DATA_WRITE(v, p, i)                MWRITE_I_32((uint8_t *)p + 16, i, v)
+#define RDD_GSO_DESC_ENTRY_FRAG_LEN_READ(r, p, i)                  FIELD_MREAD_I_32((uint8_t *)p + 88, 8, 16, i, r)
+#define RDD_GSO_DESC_ENTRY_FRAG_LEN_WRITE(v, p, i)                 FIELD_MWRITE_I_32((uint8_t *)p + 88, 8, 16, i, v)
+#if defined DSL_63138
+
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_INGRESS_QUEUE_DTS;
+
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_PTR()	( RDD_WLAN_MCAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + WLAN_MCAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_CAM_DTS	entry[ RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_US_SA_DESC_CAM_TABLE_DTS;
+
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_PTR()	( RDD_IPSEC_US_SA_DESC_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_US_SA_DESC_CAM_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE     5
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	status_vector	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_EMACS_STATUS_ENTRY_DTS;
+
+#define RDD_ETH_TX_EMACS_STATUS_ENTRY_STATUS_VECTOR_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_ETH_TX_EMACS_STATUS_ENTRY_STATUS_VECTOR_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_PICO_INGRESS_QUEUE_PTR_DTS;
+
+#if defined DSL_63138
+
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_RX_NORMAL_DESCRIPTORS_DTS;
+
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_PTR()	( RDD_GPON_RX_NORMAL_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GPON_RX_NORMAL_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CPU_TX_DHD_L2_BUFFER_SIZE     22
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_L2_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_L2_BUFFER_DTS;
+
+#define RDD_CPU_TX_DHD_L2_BUFFER_PTR()	( RDD_CPU_TX_DHD_L2_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_DHD_L2_BUFFER_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_DTS;
+
+
+typedef struct
+{
+	uint8_t	egress_port	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_HASH_BASED_FORWARDING_PORT_ENTRY_DTS;
+
+#define RDD_HASH_BASED_FORWARDING_PORT_ENTRY_EGRESS_PORT_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_HASH_BASED_FORWARDING_PORT_ENTRY_EGRESS_PORT_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+#if defined DSL_63138
+
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE     4
+typedef struct
+{
+	RDD_HASH_BASED_FORWARDING_PORT_ENTRY_DTS	entry[ RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_HASH_BASED_FORWARDING_PORT_TABLE_DTS;
+
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_PTR()	( RDD_HASH_BASED_FORWARDING_PORT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + HASH_BASED_FORWARDING_PORT_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved_fw_only	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FIREWALL_IPV6_R16_BUFFER_ENTRY_DTS;
+
+
+typedef struct
+{
+	uint32_t	request_id  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_buf_ptr	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_buf_len	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_buffer   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	radio_idx   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wifi_ssid   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_id	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1   	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	spd_svc_flag	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2   	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	eth_tx_queue	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_CONTEXT_ENTRY_DTS;
+
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_REQUEST_ID_READ(r, p)                   MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_REQUEST_ID_WRITE(v, p)                  MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_DATA_BUF_PTR_READ(r, p)                 MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_DATA_BUF_PTR_WRITE(v, p)                MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_DATA_BUF_LEN_READ(r, p)                 MREAD_16((uint8_t *)p + 8, r)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_DATA_BUF_LEN_WRITE(v, p)                MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_L2_BUFFER_READ(r, p)                    MREAD_16((uint8_t *)p + 10, r)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_L2_BUFFER_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_RADIO_IDX_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 12, 6, 2, r)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_RADIO_IDX_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 12, 6, 2, v)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_WIFI_SSID_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 12, 2, 4, r)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_WIFI_SSID_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 12, 2, 4, v)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_FLOW_RING_ID_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 12, 0, 10, r)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_FLOW_RING_ID_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 12, 0, 10, v)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_SPD_SVC_FLAG_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 14, 0, 1, r)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_SPD_SVC_FLAG_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 14, 0, 1, v)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_ETH_TX_QUEUE_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 15, 0, 3, r)
+#define RDD_DHD_TX_POST_CONTEXT_ENTRY_ETH_TX_QUEUE_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 15, 0, 3, v)
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_PICO_INGRESS_QUEUE_PTR_DTS;
+
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BPM_DDR_BUFFER_HEADROOM_SIZE_DTS;
+
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_DTS;
+
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_FAST_INGRESS_QUEUE_PTR_DTS;
+
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PARALLEL_PROCESSING_IH_BUFFER_PTR_DTS;
+
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ANY_SRC_PORT_FLOW_COUNTER_DTS;
+
+#if defined DSL_63138
+
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_TX_DHD_HOST_BUF_PTR_DTS;
+
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_PTR()	( RDD_GSO_TX_DHD_HOST_BUF_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_TX_DHD_HOST_BUF_PTR_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_HOST_BUF_PTR_DTS;
+
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_PTR()	( RDD_CPU_TX_DHD_HOST_BUF_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_DHD_HOST_BUF_PTR_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_PHYSICAL_PORT_DTS;
+
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_CONGESTION_STATE_ENTRY_DTS;
+
+
+typedef struct
+{
+	uint8_t	dummy_store	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DUMMY_STORE_ENTRY_DTS;
+
+#define RDD_DUMMY_STORE_ENTRY_DUMMY_STORE_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_DUMMY_STORE_ENTRY_DUMMY_STORE_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+
+typedef struct
+{
+	uint8_t	emac_offset	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_INTER_LAN_SCHEDULING_OFFSET_ENTRY_DTS;
+
+#define RDD_ETH_TX_INTER_LAN_SCHEDULING_OFFSET_ENTRY_EMAC_OFFSET_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_ETH_TX_INTER_LAN_SCHEDULING_OFFSET_ENTRY_EMAC_OFFSET_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+
+typedef struct
+{
+	uint8_t	reserved         	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	fc_tcp_ack_mflows	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	fc_accel_mode    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_GLOBAL_CFG_ENTRY_DTS;
+
+#define RDD_FC_GLOBAL_CFG_ENTRY_FC_TCP_ACK_MFLOWS_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 1, 1, r)
+#define RDD_FC_GLOBAL_CFG_ENTRY_FC_TCP_ACK_MFLOWS_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 1, 1, v)
+#define RDD_FC_GLOBAL_CFG_ENTRY_FC_ACCEL_MODE_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p, 0, 1, r)
+#define RDD_FC_GLOBAL_CFG_ENTRY_FC_ACCEL_MODE_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p, 0, 1, v)
+
+typedef struct
+{
+	uint8_t	reserved0       	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	available_slave3	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	available_slave2	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	available_slave1	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	available_slave0	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_DTS;
+
+#define RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE3_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 3, 1, r)
+#define RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE3_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 3, 1, v)
+#define RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE2_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 2, 1, r)
+#define RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE2_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 2, 1, v)
+#define RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE1_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 1, 1, r)
+#define RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE1_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 1, 1, v)
+#define RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE0_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 0, 1, r)
+#define RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE0_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 0, 1, v)
+/* PRIVATE_B */
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_HANDLER_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_IH_BUFFER_DTS	entry[ RDD_US_INGRESS_HANDLER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_HANDLER_BUFFER_DTS;
+
+#define RDD_US_INGRESS_HANDLER_BUFFER_PTR()	( RDD_US_INGRESS_HANDLER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_HANDLER_BUFFER_ADDRESS )
+
+#endif
+#define RDD_CSO_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER	32
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_CSO_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CSO_BUFFER_ENTRY_DTS;
+
+#define RDD_CSO_PSEUDO_HEADER_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER	10
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_CSO_PSEUDO_HEADER_BUFFER_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CSO_PSEUDO_HEADER_BUFFER_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_PTR()	( RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_ADDRESS )
+
+#if defined DSL_63138
+
+#define RDD_US_CPU_REASON_TO_METER_TABLE_SIZE     64
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_US_CPU_REASON_TO_METER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_REASON_TO_METER_TABLE_DTS;
+
+#define RDD_US_CPU_REASON_TO_METER_TABLE_PTR()	( RDD_US_CPU_REASON_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_REASON_TO_METER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_MAIN_PROFILING_BUFFER_RUNNER_DTS;
+
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_PTR()	( RDD_US_MAIN_PROFILING_BUFFER_RUNNER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_LOOKUP_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE ][ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_QUEUE_PROFILE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_QUEUE_PROFILE_DTS	entry[ RDD_US_QUEUE_PROFILE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_QUEUE_PROFILE_TABLE_DTS;
+
+#define RDD_US_QUEUE_PROFILE_TABLE_PTR()	( RDD_US_QUEUE_PROFILE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_QUEUE_PROFILE_TABLE_ADDRESS )
+
+#endif
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_CONTROLLER_ADDR_NUMBER	4
+
+typedef struct
+{
+	uint32_t	reserved0                                                                           	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_limiter_priority                                                               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_limiter_mode                                                                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	schedule                                                                            	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbh_destination                                                                     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_controllers_status                                                             	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_controllers_sustain_vector                                                     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_controllers_peak_vector                                                        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_burst_counter                                                                  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_offset                                                                         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_scheduling_mode                                                                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                                                                           	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ack_pending_epon                                                                    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ack_pending                                                                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	byte_counter                                                                        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	rate_controller_addr[RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_CONTROLLER_ADDR_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_CHANNEL_8_39_DESCRIPTOR_DTS;
+
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_LIMITER_PRIORITY_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p, 1, 1, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_LIMITER_PRIORITY_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p, 1, 1, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_LIMITER_MODE_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p, 0, 1, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_LIMITER_MODE_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p, 0, 1, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_SCHEDULE_READ(r, p)                                        MREAD_8((uint8_t *)p + 1, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_SCHEDULE_WRITE(v, p)                                       MWRITE_8((uint8_t *)p + 1, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_BBH_DESTINATION_READ(r, p)                                 MREAD_16((uint8_t *)p + 2, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_BBH_DESTINATION_WRITE(v, p)                                MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_CONTROLLERS_STATUS_READ(r, p)                         MREAD_32((uint8_t *)p + 4, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_CONTROLLERS_STATUS_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_CONTROLLERS_SUSTAIN_VECTOR_READ(r, p)                 MREAD_32((uint8_t *)p + 8, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_CONTROLLERS_SUSTAIN_VECTOR_WRITE(v, p)                MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_CONTROLLERS_PEAK_VECTOR_READ(r, p)                    MREAD_32((uint8_t *)p + 12, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_CONTROLLERS_PEAK_VECTOR_WRITE(v, p)                   MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_PEAK_BURST_COUNTER_READ(r, p)                              MREAD_16((uint8_t *)p + 16, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_PEAK_BURST_COUNTER_WRITE(v, p)                             MWRITE_16((uint8_t *)p + 16, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_PEAK_OFFSET_READ(r, p)                                     MREAD_8((uint8_t *)p + 18, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_PEAK_OFFSET_WRITE(v, p)                                    MWRITE_8((uint8_t *)p + 18, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_PEAK_SCHEDULING_MODE_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 19, 7, 1, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_PEAK_SCHEDULING_MODE_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 19, 7, 1, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_ACK_PENDING_EPON_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 19, 1, 1, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_ACK_PENDING_EPON_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 19, 1, 1, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_ACK_PENDING_READ(r, p)                                     FIELD_MREAD_8((uint8_t *)p + 19, 0, 1, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_ACK_PENDING_WRITE(v, p)                                    FIELD_MWRITE_8((uint8_t *)p + 19, 0, 1, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_BYTE_COUNTER_READ(r, p)                                    MREAD_32((uint8_t *)p + 20, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_BYTE_COUNTER_WRITE(v, p)                                   MWRITE_32((uint8_t *)p + 20, v)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_CONTROLLER_ADDR_READ(r, p, i)                         MREAD_I_16((uint8_t *)p + 24, i, r)
+#define RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_CONTROLLER_ADDR_WRITE(v, p, i)                        MWRITE_I_16((uint8_t *)p + 24, i, v)
+#if defined DSL_63138
+
+#define RDD_WAN_CHANNELS_8_39_TABLE_SIZE     32
+typedef struct
+{
+	RDD_WAN_CHANNEL_8_39_DESCRIPTOR_DTS	entry[ RDD_WAN_CHANNELS_8_39_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_CHANNELS_8_39_TABLE_DTS;
+
+#define RDD_WAN_CHANNELS_8_39_TABLE_PTR()	( RDD_WAN_CHANNELS_8_39_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_CHANNELS_8_39_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_RUNNER_FLOW_HEADER_BUFFER_DTS	entry[ RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RUNNER_FLOW_HEADER_BUFFER_DTS;
+
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_PTR()	( RDD_US_RUNNER_FLOW_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RUNNER_FLOW_HEADER_BUFFER_ADDRESS )
+
+#endif
+#define RDD_US_POLICER_TABLE_PTR()	( RDD_US_POLICER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_POLICER_TABLE_ADDRESS )
+
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_TX_QUEUE_ADDR_NUMBER	32
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_RESERVED_NUMBER	12
+
+typedef struct
+{
+	uint32_t	queues_status                                                                        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_limiter_status                                                                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	sustain_vector                                                                       	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_vector                                                                          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	tx_queue_addr[RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_TX_QUEUE_ADDR_NUMBER];
+	uint32_t	reserved[RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_RESERVED_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_DTS;
+
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_QUEUES_STATUS_READ(r, p)                       MREAD_32((uint8_t *)p, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_QUEUES_STATUS_WRITE(v, p)                      MWRITE_32((uint8_t *)p, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_RATE_LIMITER_STATUS_READ(r, p)                 MREAD_32((uint8_t *)p + 4, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_RATE_LIMITER_STATUS_WRITE(v, p)                MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_SUSTAIN_VECTOR_READ(r, p)                      MREAD_32((uint8_t *)p + 8, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_SUSTAIN_VECTOR_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_PEAK_VECTOR_READ(r, p)                         MREAD_32((uint8_t *)p + 12, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_PEAK_VECTOR_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_TX_QUEUE_ADDR_READ(r, p, i)                    MREAD_I_16((uint8_t *)p + 16, i, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_TX_QUEUE_ADDR_WRITE(v, p, i)                   MWRITE_I_16((uint8_t *)p + 16, i, v)
+#if defined DSL_63138
+
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE     2
+typedef struct
+{
+	RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_DTS;
+
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_PTR()	( RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved0                         	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ptm_bonding                       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	traffic_class_to_queue_table_index	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wan_channel_id                    	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pbits_to_queue_table_index        	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	crc_calc                          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wan_port_id_or_fstat              	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_WAN_FLOW_ENTRY_DTS;
+
+#define RDD_US_WAN_FLOW_ENTRY_PTM_BONDING_READ(r, p)                                        FIELD_MREAD_8((uint8_t *)p, 1, 1, r)
+#define RDD_US_WAN_FLOW_ENTRY_PTM_BONDING_WRITE(v, p)                                       FIELD_MWRITE_8((uint8_t *)p, 1, 1, v)
+#define RDD_US_WAN_FLOW_ENTRY_TRAFFIC_CLASS_TO_QUEUE_TABLE_INDEX_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p, 6, 3, r)
+#define RDD_US_WAN_FLOW_ENTRY_TRAFFIC_CLASS_TO_QUEUE_TABLE_INDEX_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p, 6, 3, v)
+#define RDD_US_WAN_FLOW_ENTRY_WAN_CHANNEL_ID_READ(r, p)                                     FIELD_MREAD_8((uint8_t *)p + 1, 0, 6, r)
+#define RDD_US_WAN_FLOW_ENTRY_WAN_CHANNEL_ID_WRITE(v, p)                                    FIELD_MWRITE_8((uint8_t *)p + 1, 0, 6, v)
+#define RDD_US_WAN_FLOW_ENTRY_PBITS_TO_QUEUE_TABLE_INDEX_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 2, 5, 3, r)
+#define RDD_US_WAN_FLOW_ENTRY_PBITS_TO_QUEUE_TABLE_INDEX_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 2, 5, 3, v)
+#define RDD_US_WAN_FLOW_ENTRY_CRC_CALC_READ(r, p)                                           FIELD_MREAD_8((uint8_t *)p + 2, 4, 1, r)
+#define RDD_US_WAN_FLOW_ENTRY_CRC_CALC_WRITE(v, p)                                          FIELD_MWRITE_8((uint8_t *)p + 2, 4, 1, v)
+#define RDD_US_WAN_FLOW_ENTRY_WAN_PORT_ID_OR_FSTAT_READ(r, p)                               FIELD_MREAD_16((uint8_t *)p + 2, 0, 12, r)
+#define RDD_US_WAN_FLOW_ENTRY_WAN_PORT_ID_OR_FSTAT_WRITE(v, p)                              FIELD_MWRITE_16((uint8_t *)p + 2, 0, 12, v)
+#if defined DSL_63138
+
+#define RDD_US_WAN_FLOW_TABLE_SIZE     256
+typedef struct
+{
+	RDD_US_WAN_FLOW_ENTRY_DTS	entry[ RDD_US_WAN_FLOW_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_WAN_FLOW_TABLE_DTS;
+
+#define RDD_US_WAN_FLOW_TABLE_PTR()	( RDD_US_WAN_FLOW_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_WAN_FLOW_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_CPU_TX_BBH_DESCRIPTORS_ENTRY_DTS	entry[ RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_BBH_DESCRIPTORS_DTS;
+
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_PTR()	( RDD_US_CPU_TX_BBH_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_BBH_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_FORWARDING_MATRIX_ENTRY_DTS	entry[ RDD_US_FORWARDING_MATRIX_TABLE_SIZE ][ RDD_US_FORWARDING_MATRIX_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FORWARDING_MATRIX_TABLE_DTS;
+
+#define RDD_US_FORWARDING_MATRIX_TABLE_PTR()	( RDD_US_FORWARDING_MATRIX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FORWARDING_MATRIX_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_TIMER_SCHEDULER_PRIMITIVE_ENTRY_DTS	entry[ RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined DSL_63138
+
+typedef struct
+{
+	uint16_t	port_sel  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	reserved0 	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	pkt_eop   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	frag_size 	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DSL_PTM_BOND_TX_HDR_ENTRY_DTS;
+
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_PORT_SEL_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_PORT_SEL_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_PKT_EOP_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p, 4, 1, r)
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_PKT_EOP_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p, 4, 1, v)
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_FRAG_SIZE_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p, 0, 12, r)
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_FRAG_SIZE_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p, 0, 12, v)
+#endif
+#if defined DSL_63138
+
+#define RDD_DSL_PTM_BOND_TX_HDR_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DSL_PTM_BOND_TX_HDR_ENTRY_DTS	entry[ RDD_DSL_PTM_BOND_TX_HDR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DSL_PTM_BOND_TX_HDR_TABLE_DTS;
+
+#define RDD_DSL_PTM_BOND_TX_HDR_TABLE_PTR()	( RDD_DSL_PTM_BOND_TX_HDR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DSL_PTM_BOND_TX_HDR_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	queue          	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	rate_controller	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_QUEUE_ENTRY_DTS;
+
+#define RDD_US_QUEUE_ENTRY_QUEUE_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p, 5, 3, r)
+#define RDD_US_QUEUE_ENTRY_QUEUE_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p, 5, 3, v)
+#define RDD_US_QUEUE_ENTRY_RATE_CONTROLLER_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 0, 5, r)
+#define RDD_US_QUEUE_ENTRY_RATE_CONTROLLER_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 0, 5, v)
+#if defined DSL_63138
+
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE     8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2    8
+typedef struct
+{
+	RDD_US_QUEUE_ENTRY_DTS	entry[ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE ][ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_DTS;
+
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_PTR()	( RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TRAFFIC_CLASS_TO_QUEUE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_RATE_LIMITER_TABLE_SIZE     16
+typedef struct
+{
+	RDD_RATE_LIMITER_ENTRY_DTS	entry[ RDD_US_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_US_RATE_LIMITER_TABLE_PTR()	( RDD_US_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_CPU_RX_METER_TABLE_PTR()	( RDD_US_CPU_RX_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_METER_TABLE_ADDRESS )
+
+#if defined DSL_63138
+
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_BUFFER_ENTRY_DTS	entry[ RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_CONTEXT_BUFFER_DTS;
+
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_PTR()	( RDD_US_CONNECTION_CONTEXT_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CONNECTION_CONTEXT_BUFFER_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	vlan_cmd_index                	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	qos_rule_match                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	qos_rule_overrun_wan_flow_mode	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wan_flow_mapping_mode         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wan_flow_mapping_table        	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	opbit_remark_mode             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipbit_remark_mode             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	qos_mapping_mode              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wan_flow                      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	traffic_class                 	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                     	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	trap_reason                   	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	drop                          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cpu                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	policer_mode                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	policer_id                    	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2                     	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_controller               	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dei_remark_enable             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dei_value                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ic_ip_flow                    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_pbit                    	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inner_pbit                    	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dscp_remarking_mode           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dscp                          	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ecn                           	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_VLAN_CMD_INDEX_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p, 1, 7, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_VLAN_CMD_INDEX_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p, 1, 7, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_QOS_RULE_MATCH_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p, 0, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_QOS_RULE_MATCH_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p, 0, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_QOS_RULE_OVERRUN_WAN_FLOW_MODE_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 1, 7, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_QOS_RULE_OVERRUN_WAN_FLOW_MODE_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 1, 7, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_WAN_FLOW_MAPPING_MODE_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 1, 6, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_WAN_FLOW_MAPPING_MODE_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 1, 6, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_WAN_FLOW_MAPPING_TABLE_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 1, 3, 3, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_WAN_FLOW_MAPPING_TABLE_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 1, 3, 3, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_OPBIT_REMARK_MODE_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 1, 2, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_OPBIT_REMARK_MODE_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 1, 2, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_IPBIT_REMARK_MODE_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 1, 1, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_IPBIT_REMARK_MODE_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 1, 1, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_QOS_MAPPING_MODE_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 1, 0, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_QOS_MAPPING_MODE_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 1, 0, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_WAN_FLOW_READ(r, p)                                       MREAD_8((uint8_t *)p + 2, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_WAN_FLOW_WRITE(v, p)                                      MWRITE_8((uint8_t *)p + 2, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_TRAFFIC_CLASS_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 3, 5, 3, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_TRAFFIC_CLASS_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 3, 5, 3, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_TRAP_REASON_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 3, 0, 3, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_TRAP_REASON_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 3, 0, 3, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DROP_READ(r, p)                                           FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DROP_WRITE(v, p)                                          FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_CPU_READ(r, p)                                            FIELD_MREAD_8((uint8_t *)p + 4, 6, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_CPU_WRITE(v, p)                                           FIELD_MWRITE_8((uint8_t *)p + 4, 6, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_POLICER_MODE_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 4, 5, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_POLICER_MODE_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 4, 5, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_POLICER_ID_READ(r, p)                                     FIELD_MREAD_8((uint8_t *)p + 4, 1, 4, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_POLICER_ID_WRITE(v, p)                                    FIELD_MWRITE_8((uint8_t *)p + 4, 1, 4, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_RATE_CONTROLLER_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 5, 2, 5, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_RATE_CONTROLLER_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 5, 2, 5, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DEI_REMARK_ENABLE_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 5, 1, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DEI_REMARK_ENABLE_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 5, 1, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DEI_VALUE_READ(r, p)                                      FIELD_MREAD_8((uint8_t *)p + 5, 0, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DEI_VALUE_WRITE(v, p)                                     FIELD_MWRITE_8((uint8_t *)p + 5, 0, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_IC_IP_FLOW_READ(r, p)                                     FIELD_MREAD_8((uint8_t *)p + 6, 7, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_IC_IP_FLOW_WRITE(v, p)                                    FIELD_MWRITE_8((uint8_t *)p + 6, 7, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_OUTER_PBIT_READ(r, p)                                     FIELD_MREAD_8((uint8_t *)p + 6, 4, 3, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_OUTER_PBIT_WRITE(v, p)                                    FIELD_MWRITE_8((uint8_t *)p + 6, 4, 3, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_INNER_PBIT_READ(r, p)                                     FIELD_MREAD_8((uint8_t *)p + 6, 1, 3, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_INNER_PBIT_WRITE(v, p)                                    FIELD_MWRITE_8((uint8_t *)p + 6, 1, 3, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DSCP_REMARKING_MODE_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 6, 0, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DSCP_REMARKING_MODE_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 6, 0, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DSCP_READ(r, p)                                           FIELD_MREAD_8((uint8_t *)p + 7, 2, 6, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DSCP_WRITE(v, p)                                          FIELD_MWRITE_8((uint8_t *)p + 7, 2, 6, v)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_ECN_READ(r, p)                                            FIELD_MREAD_8((uint8_t *)p + 7, 0, 2, r)
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_ECN_WRITE(v, p)                                           FIELD_MWRITE_8((uint8_t *)p + 7, 0, 2, v)
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+typedef struct
+{
+	RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS )
+
+#endif
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLER_ADDR_NUMBER	32
+
+typedef struct
+{
+	uint32_t	reserved0                                                                           	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_limiter_priority                                                               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_limiter_mode                                                                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	schedule                                                                            	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbh_destination                                                                     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_controllers_status                                                             	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_controllers_sustain_vector                                                     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_controllers_peak_vector                                                        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_burst_counter                                                                  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_offset                                                                         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_scheduling_mode                                                                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                                                                           	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ack_pending_epon                                                                    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ack_pending                                                                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	byte_counter                                                                        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	rate_controller_addr[RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLER_ADDR_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_CHANNEL_0_7_DESCRIPTOR_DTS;
+
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_LIMITER_PRIORITY_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p, 1, 1, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_LIMITER_PRIORITY_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p, 1, 1, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_LIMITER_MODE_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p, 0, 1, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_LIMITER_MODE_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p, 0, 1, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_SCHEDULE_READ(r, p)                                        MREAD_8((uint8_t *)p + 1, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_SCHEDULE_WRITE(v, p)                                       MWRITE_8((uint8_t *)p + 1, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_BBH_DESTINATION_READ(r, p)                                 MREAD_16((uint8_t *)p + 2, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_BBH_DESTINATION_WRITE(v, p)                                MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLERS_STATUS_READ(r, p)                         MREAD_32((uint8_t *)p + 4, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLERS_STATUS_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLERS_SUSTAIN_VECTOR_READ(r, p)                 MREAD_32((uint8_t *)p + 8, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLERS_SUSTAIN_VECTOR_WRITE(v, p)                MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLERS_PEAK_VECTOR_READ(r, p)                    MREAD_32((uint8_t *)p + 12, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLERS_PEAK_VECTOR_WRITE(v, p)                   MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_PEAK_BURST_COUNTER_READ(r, p)                              MREAD_16((uint8_t *)p + 16, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_PEAK_BURST_COUNTER_WRITE(v, p)                             MWRITE_16((uint8_t *)p + 16, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_PEAK_OFFSET_READ(r, p)                                     MREAD_8((uint8_t *)p + 18, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_PEAK_OFFSET_WRITE(v, p)                                    MWRITE_8((uint8_t *)p + 18, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_PEAK_SCHEDULING_MODE_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 19, 7, 1, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_PEAK_SCHEDULING_MODE_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 19, 7, 1, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_ACK_PENDING_EPON_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 19, 1, 1, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_ACK_PENDING_EPON_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 19, 1, 1, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_ACK_PENDING_READ(r, p)                                     FIELD_MREAD_8((uint8_t *)p + 19, 0, 1, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_ACK_PENDING_WRITE(v, p)                                    FIELD_MWRITE_8((uint8_t *)p + 19, 0, 1, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_BYTE_COUNTER_READ(r, p)                                    MREAD_32((uint8_t *)p + 20, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_BYTE_COUNTER_WRITE(v, p)                                   MWRITE_32((uint8_t *)p + 20, v)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLER_ADDR_READ(r, p, i)                         MREAD_I_16((uint8_t *)p + 24, i, r)
+#define RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLER_ADDR_WRITE(v, p, i)                        MWRITE_I_16((uint8_t *)p + 24, i, v)
+#if defined DSL_63138
+
+#define RDD_WAN_CHANNELS_0_7_TABLE_SIZE     8
+typedef struct
+{
+	RDD_WAN_CHANNEL_0_7_DESCRIPTOR_DTS	entry[ RDD_WAN_CHANNELS_0_7_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_CHANNELS_0_7_TABLE_DTS;
+
+#define RDD_WAN_CHANNELS_0_7_TABLE_PTR()	( RDD_WAN_CHANNELS_0_7_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_CHANNELS_0_7_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_L2_UCAST_CONNECTION_BUFFER_SIZE     4
+typedef struct
+{
+	RDD_FC_L2_UCAST_CONNECTION_ENTRY_DTS	entry[ RDD_US_L2_UCAST_CONNECTION_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_L2_UCAST_CONNECTION_BUFFER_DTS;
+
+#define RDD_US_L2_UCAST_CONNECTION_BUFFER_PTR()	( RDD_US_L2_UCAST_CONNECTION_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_L2_UCAST_CONNECTION_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_DTS;
+
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_PTR()	( RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_CONNECTION_CACHE_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_US_CONNECTION_CACHE_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_CACHE_BUFFER_DTS;
+
+#define RDD_US_CONNECTION_CACHE_BUFFER_PTR()	( RDD_US_CONNECTION_CACHE_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CONNECTION_CACHE_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_PARAMETER_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE ][ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+
+typedef struct
+{
+	uint32_t	msg_type             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	if_id                	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	common_hdr_flags     	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	epoch                	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	request_id           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	meta_buf_len         	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_len             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved             	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	metadata_buf_addr_low	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	metadata_buf_addr_hi 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_buf_addr_low    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_buf_addr_hi     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_POST_DESCRIPTOR_DTS;
+
+#define RDD_DHD_RX_POST_DESCRIPTOR_MSG_TYPE_READ(r, p)                              MREAD_8((uint8_t *)p, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_MSG_TYPE_WRITE(v, p)                             MWRITE_8((uint8_t *)p, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_MSG_TYPE_L_READ( wv )                            FIELD_GET( wv, 24, 8 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_MSG_TYPE_L_WRITE( v, wv )                        FIELD_SET( v, 24, 8, wv )
+#define RDD_DHD_RX_POST_DESCRIPTOR_IF_ID_READ(r, p)                                 MREAD_8((uint8_t *)p + 1, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_IF_ID_WRITE(v, p)                                MWRITE_8((uint8_t *)p + 1, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_IF_ID_L_READ( wv )                               FIELD_GET( wv, 16, 8 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_IF_ID_L_WRITE( v, wv )                           FIELD_SET( v, 16, 8, wv )
+#define RDD_DHD_RX_POST_DESCRIPTOR_COMMON_HDR_FLAGS_READ(r, p)                      MREAD_8((uint8_t *)p + 2, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_COMMON_HDR_FLAGS_WRITE(v, p)                     MWRITE_8((uint8_t *)p + 2, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_COMMON_HDR_FLAGS_L_READ( wv )                    FIELD_GET( wv, 8, 8 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_COMMON_HDR_FLAGS_L_WRITE( v, wv )                FIELD_SET( v, 8, 8, wv )
+#define RDD_DHD_RX_POST_DESCRIPTOR_EPOCH_READ(r, p)                                 MREAD_8((uint8_t *)p + 3, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_EPOCH_WRITE(v, p)                                MWRITE_8((uint8_t *)p + 3, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_EPOCH_L_READ( wv )                               FIELD_GET( wv, 0, 8 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_EPOCH_L_WRITE( v, wv )                           FIELD_SET( v, 0, 8, wv )
+#define RDD_DHD_RX_POST_DESCRIPTOR_REQUEST_ID_READ(r, p)                            MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_REQUEST_ID_WRITE(v, p)                           MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_REQUEST_ID_L_READ( wv )                          FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_REQUEST_ID_L_WRITE( v, wv )                      FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_RX_POST_DESCRIPTOR_META_BUF_LEN_READ(r, p)                          MREAD_16((uint8_t *)p + 8, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_META_BUF_LEN_WRITE(v, p)                         MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_META_BUF_LEN_L_READ( wv )                        FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_META_BUF_LEN_L_WRITE( v, wv )                    FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_LEN_READ(r, p)                              MREAD_16((uint8_t *)p + 10, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_LEN_WRITE(v, p)                             MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_LEN_L_READ( wv )                            FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_LEN_L_WRITE( v, wv )                        FIELD_SET( v, 0, 16, wv )
+#define RDD_DHD_RX_POST_DESCRIPTOR_METADATA_BUF_ADDR_LOW_READ(r, p)                 MREAD_32((uint8_t *)p + 16, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_METADATA_BUF_ADDR_LOW_WRITE(v, p)                MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_METADATA_BUF_ADDR_LOW_L_READ( wv )               FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_METADATA_BUF_ADDR_LOW_L_WRITE( v, wv )           FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_RX_POST_DESCRIPTOR_METADATA_BUF_ADDR_HI_READ(r, p)                  MREAD_32((uint8_t *)p + 20, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_METADATA_BUF_ADDR_HI_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 20, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_METADATA_BUF_ADDR_HI_L_READ( wv )                FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_METADATA_BUF_ADDR_HI_L_WRITE( v, wv )            FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_BUF_ADDR_LOW_READ(r, p)                     MREAD_32((uint8_t *)p + 24, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_BUF_ADDR_LOW_WRITE(v, p)                    MWRITE_32((uint8_t *)p + 24, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_BUF_ADDR_LOW_L_READ( wv )                   FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_BUF_ADDR_LOW_L_WRITE( v, wv )               FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_BUF_ADDR_HI_READ(r, p)                      MREAD_32((uint8_t *)p + 28, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_BUF_ADDR_HI_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 28, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_BUF_ADDR_HI_L_READ( wv )                    FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_DATA_BUF_ADDR_HI_L_WRITE( v, wv )                FIELD_SET( v, 0, 32, wv )
+
+typedef struct
+{
+	uint32_t	msg_type            	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	if_id               	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	common_hdr_flags    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	epoch               	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	request_id          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	compl_msg_hdr_status	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_id        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	meta_buf_len        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_len            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_offset         	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flags               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rx_status_0         	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rx_status_1         	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dma_done_mark       	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_COMPLETE_DESCRIPTOR_DTS;
+
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_MSG_TYPE_READ(r, p)                             MREAD_8((uint8_t *)p, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_MSG_TYPE_WRITE(v, p)                            MWRITE_8((uint8_t *)p, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_MSG_TYPE_L_READ( wv )                           FIELD_GET( wv, 24, 8 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_MSG_TYPE_L_WRITE( v, wv )                       FIELD_SET( v, 24, 8, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_IF_ID_READ(r, p)                                MREAD_8((uint8_t *)p + 1, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_IF_ID_WRITE(v, p)                               MWRITE_8((uint8_t *)p + 1, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_IF_ID_L_READ( wv )                              FIELD_GET( wv, 16, 8 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_IF_ID_L_WRITE( v, wv )                          FIELD_SET( v, 16, 8, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_COMMON_HDR_FLAGS_READ(r, p)                     MREAD_8((uint8_t *)p + 2, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_COMMON_HDR_FLAGS_WRITE(v, p)                    MWRITE_8((uint8_t *)p + 2, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_COMMON_HDR_FLAGS_L_READ( wv )                   FIELD_GET( wv, 8, 8 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_COMMON_HDR_FLAGS_L_WRITE( v, wv )               FIELD_SET( v, 8, 8, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_EPOCH_READ(r, p)                                MREAD_8((uint8_t *)p + 3, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_EPOCH_WRITE(v, p)                               MWRITE_8((uint8_t *)p + 3, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_EPOCH_L_READ( wv )                              FIELD_GET( wv, 0, 8 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_EPOCH_L_WRITE( v, wv )                          FIELD_SET( v, 0, 8, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_REQUEST_ID_READ(r, p)                           MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_REQUEST_ID_WRITE(v, p)                          MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_REQUEST_ID_L_READ( wv )                         FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_REQUEST_ID_L_WRITE( v, wv )                     FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_COMPL_MSG_HDR_STATUS_READ(r, p)                 MREAD_16((uint8_t *)p + 8, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_COMPL_MSG_HDR_STATUS_WRITE(v, p)                MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_COMPL_MSG_HDR_STATUS_L_READ( wv )               FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_COMPL_MSG_HDR_STATUS_L_WRITE( v, wv )           FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_FLOW_RING_ID_READ(r, p)                         MREAD_16((uint8_t *)p + 10, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_FLOW_RING_ID_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_FLOW_RING_ID_L_READ( wv )                       FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_FLOW_RING_ID_L_WRITE( v, wv )                   FIELD_SET( v, 0, 16, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_META_BUF_LEN_READ(r, p)                         MREAD_16((uint8_t *)p + 12, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_META_BUF_LEN_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_META_BUF_LEN_L_READ( wv )                       FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_META_BUF_LEN_L_WRITE( v, wv )                   FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DATA_LEN_READ(r, p)                             MREAD_16((uint8_t *)p + 14, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DATA_LEN_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DATA_LEN_L_READ( wv )                           FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DATA_LEN_L_WRITE( v, wv )                       FIELD_SET( v, 0, 16, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DATA_OFFSET_READ(r, p)                          MREAD_16((uint8_t *)p + 16, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DATA_OFFSET_WRITE(v, p)                         MWRITE_16((uint8_t *)p + 16, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DATA_OFFSET_L_READ( wv )                        FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DATA_OFFSET_L_WRITE( v, wv )                    FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_FLAGS_READ(r, p)                                MREAD_16((uint8_t *)p + 18, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_FLAGS_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 18, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_FLAGS_L_READ( wv )                              FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_FLAGS_L_WRITE( v, wv )                          FIELD_SET( v, 0, 16, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_RX_STATUS_0_READ(r, p)                          MREAD_32((uint8_t *)p + 20, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_RX_STATUS_0_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 20, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_RX_STATUS_0_L_READ( wv )                        FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_RX_STATUS_0_L_WRITE( v, wv )                    FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_RX_STATUS_1_READ(r, p)                          MREAD_32((uint8_t *)p + 24, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_RX_STATUS_1_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 24, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_RX_STATUS_1_L_READ( wv )                        FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_RX_STATUS_1_L_WRITE( v, wv )                    FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DMA_DONE_MARK_READ(r, p)                        MREAD_32((uint8_t *)p + 28, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DMA_DONE_MARK_WRITE(v, p)                       MWRITE_32((uint8_t *)p + 28, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DMA_DONE_MARK_L_READ( wv )                      FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_DMA_DONE_MARK_L_WRITE( v, wv )                  FIELD_SET( v, 0, 32, wv )
+
+typedef struct
+{
+	uint32_t	request_id       	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_buf_addr_low	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_POST_DESCRIPTOR_CWI32_DTS;
+
+#define RDD_DHD_RX_POST_DESCRIPTOR_CWI32_REQUEST_ID_READ(r, p)                        MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_CWI32_REQUEST_ID_WRITE(v, p)                       MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_CWI32_REQUEST_ID_L_READ( wv )                      FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_CWI32_REQUEST_ID_L_WRITE( v, wv )                  FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_RX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_LOW_READ(r, p)                 MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_RX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_LOW_WRITE(v, p)                MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_RX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_LOW_L_READ( wv )               FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_POST_DESCRIPTOR_CWI32_DATA_BUF_ADDR_LOW_L_WRITE( v, wv )           FIELD_SET( v, 0, 32, wv )
+
+typedef struct
+{
+	uint32_t	flags      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	if_id      	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_offset	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_len   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	request_id 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_DTS;
+
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_FLAGS_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p, 5, 3, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_FLAGS_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p, 5, 3, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_FLAGS_L_READ( wv )                     FIELD_GET( wv, 29, 3 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_FLAGS_L_WRITE( v, wv )                 FIELD_SET( v, 29, 3, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_IF_ID_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p, 0, 5, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_IF_ID_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p, 0, 5, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_IF_ID_L_READ( wv )                     FIELD_GET( wv, 24, 5 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_IF_ID_L_WRITE( v, wv )                 FIELD_SET( v, 24, 5, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_DATA_OFFSET_READ(r, p)                 MREAD_8((uint8_t *)p + 1, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_DATA_OFFSET_WRITE(v, p)                MWRITE_8((uint8_t *)p + 1, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_DATA_OFFSET_L_READ( wv )               FIELD_GET( wv, 16, 8 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_DATA_OFFSET_L_WRITE( v, wv )           FIELD_SET( v, 16, 8, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_DATA_LEN_READ(r, p)                    MREAD_16((uint8_t *)p + 2, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_DATA_LEN_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_DATA_LEN_L_READ( wv )                  FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_DATA_LEN_L_WRITE( v, wv )              FIELD_SET( v, 0, 16, wv )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_REQUEST_ID_READ(r, p)                  MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_REQUEST_ID_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_REQUEST_ID_L_READ( wv )                FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_REQUEST_ID_L_WRITE( v, wv )            FIELD_SET( v, 0, 32, wv )
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	current_budget           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	drop_threshold           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	xoff_threshold           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocated_budget_mantisa 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocated_budget_exponent	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	active_pause_flag        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbh_rx_address           	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_RATE_LIMITER_ENTRY_DTS;
+
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_CURRENT_BUDGET_READ(r, p)                            MREAD_32((uint8_t *)p, r)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_CURRENT_BUDGET_WRITE(v, p)                           MWRITE_32((uint8_t *)p, v)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_DROP_THRESHOLD_READ(r, p)                            MREAD_32((uint8_t *)p + 4, r)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_DROP_THRESHOLD_WRITE(v, p)                           MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_XOFF_THRESHOLD_READ(r, p)                            MREAD_32((uint8_t *)p + 8, r)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_XOFF_THRESHOLD_WRITE(v, p)                           MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_ALLOCATED_BUDGET_MANTISA_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p + 12, 2, 14, r)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_ALLOCATED_BUDGET_MANTISA_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p + 12, 2, 14, v)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_ALLOCATED_BUDGET_EXPONENT_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 13, 0, 2, r)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_ALLOCATED_BUDGET_EXPONENT_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 13, 0, 2, v)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_ACTIVE_PAUSE_FLAG_READ(r, p)                         MREAD_8((uint8_t *)p + 14, r)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_ACTIVE_PAUSE_FLAG_WRITE(v, p)                        MWRITE_8((uint8_t *)p + 14, v)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_BBH_RX_ADDRESS_READ(r, p)                            MREAD_8((uint8_t *)p + 15, r)
+#define RDD_INGRESS_RATE_LIMITER_ENTRY_BBH_RX_ADDRESS_WRITE(v, p)                           MWRITE_8((uint8_t *)p + 15, v)
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE     5
+typedef struct
+{
+	RDD_INGRESS_RATE_LIMITER_ENTRY_DTS	entry[ RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_PTR()	( RDD_US_INGRESS_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_SIZE     8
+typedef struct
+{
+	RDD_DSL_PTM_BOND_TX_HDR_ENTRY_DTS	entry[ RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_DTS;
+
+#define RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_PTR()	( RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_RX_PICO_INGRESS_QUEUE_DTS;
+
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_PTR()	( RDD_US_CPU_RX_PICO_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_ROUTER_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_ROUTER_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_ROUTER_INGRESS_QUEUE_DTS;
+
+#define RDD_US_ROUTER_INGRESS_QUEUE_PTR()	( RDD_US_ROUTER_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_ROUTER_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     6
+typedef struct
+{
+	RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	reserved_fw_only	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_ABSOLUTE_TX_COUNTER_DTS;
+
+#if defined DSL_63138
+
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE     40
+typedef struct
+{
+	RDD_GPON_ABSOLUTE_TX_COUNTER_DTS	entry[ RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_DTS;
+
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_PTR()	( RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + GPON_ABSOLUTE_TX_BBH_COUNTER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_GPE_COMMAND_PRIMITIVE_ENTRY_DTS	entry[ RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_PTR()	( RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_RX_FAST_INGRESS_QUEUE_DTS;
+
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_PTR()	( RDD_US_CPU_RX_FAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_DEBUG_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_DEBUG_BUFFER_ENTRY_DTS	entry[ RDD_US_DEBUG_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DEBUG_BUFFER_DTS;
+
+#define RDD_US_DEBUG_BUFFER_PTR()	( RDD_US_DEBUG_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DEBUG_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_FW_MAC_ADDRS_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_US_FW_MAC_ADDRS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FW_MAC_ADDRS_DTS;
+
+#define RDD_US_FW_MAC_ADDRS_PTR()	( RDD_US_FW_MAC_ADDRS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FW_MAC_ADDRS_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE     3
+typedef struct
+{
+	RDD_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS	entry[ RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS;
+
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_PTR()	( RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry[ RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS;
+
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_PTR()	( RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_TX_POST_INGRESS_QUEUE_DTS;
+
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_PTR()	( RDD_US_DHD_TX_POST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DHD_TX_POST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_PTR()	( RDD_RUNNER_FWTRACE_MAINB_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + RUNNER_FWTRACE_MAINB_PARAM_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	wan_channel_ptr	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_ENTRY_DTS;
+
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_ENTRY_WAN_CHANNEL_PTR_READ(r, p)                 MREAD_16((uint8_t *)p, r)
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_ENTRY_WAN_CHANNEL_PTR_WRITE(v, p)                MWRITE_16((uint8_t *)p, v)
+#if defined DSL_63138
+
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE     48
+typedef struct
+{
+	RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_ENTRY_DTS	entry[ RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_DTS;
+
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_PTR()	( RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined DSL_63138
+
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOB_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_PTR()	( RDD_RUNNER_FWTRACE_PICOB_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + RUNNER_FWTRACE_PICOB_PARAM_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	summary                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	linear_length            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_header_length     	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_protocol              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_header_offset         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_header_length         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_total_length          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipv4_csum                	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_udp_header_offset    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_udp_header_length    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_udp_total_length     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_udp_csum             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	max_chunk_length         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	chunk_bytes_left         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	nr_frags                 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	frag_index               	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	frag_len                 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	frag_data                	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	good_csum_packets        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	no_csum_packets          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bad_ipv4_hdr_csum_packets	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bad_tcp_udp_csum_packets 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	fail_code                	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dma_sync                 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	seg_length               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	seg_bytes_left           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_length           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_bytes_left       	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_0               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_ptr              	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_1               	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ddr_payload_offset       	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ddr_src_address          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	saved_ih_buffer_number   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	saved_csum32_ret_addr    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	saved_r16                	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CSO_CONTEXT_ENTRY_DTS;
+
+#define RDD_CSO_CONTEXT_ENTRY_SUMMARY_READ(r, p)                                   MREAD_32((uint8_t *)p, r)
+#define RDD_CSO_CONTEXT_ENTRY_SUMMARY_WRITE(v, p)                                  MWRITE_32((uint8_t *)p, v)
+#define RDD_CSO_CONTEXT_ENTRY_LINEAR_LENGTH_READ(r, p)                             MREAD_16((uint8_t *)p + 4, r)
+#define RDD_CSO_CONTEXT_ENTRY_LINEAR_LENGTH_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_CSO_CONTEXT_ENTRY_PACKET_LENGTH_READ(r, p)                             MREAD_16((uint8_t *)p + 6, r)
+#define RDD_CSO_CONTEXT_ENTRY_PACKET_LENGTH_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_CSO_CONTEXT_ENTRY_PACKET_HEADER_LENGTH_READ(r, p)                      MREAD_8((uint8_t *)p + 8, r)
+#define RDD_CSO_CONTEXT_ENTRY_PACKET_HEADER_LENGTH_WRITE(v, p)                     MWRITE_8((uint8_t *)p + 8, v)
+#define RDD_CSO_CONTEXT_ENTRY_IP_PROTOCOL_READ(r, p)                               MREAD_8((uint8_t *)p + 9, r)
+#define RDD_CSO_CONTEXT_ENTRY_IP_PROTOCOL_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 9, v)
+#define RDD_CSO_CONTEXT_ENTRY_IP_HEADER_OFFSET_READ(r, p)                          MREAD_8((uint8_t *)p + 10, r)
+#define RDD_CSO_CONTEXT_ENTRY_IP_HEADER_OFFSET_WRITE(v, p)                         MWRITE_8((uint8_t *)p + 10, v)
+#define RDD_CSO_CONTEXT_ENTRY_IP_HEADER_LENGTH_READ(r, p)                          MREAD_8((uint8_t *)p + 11, r)
+#define RDD_CSO_CONTEXT_ENTRY_IP_HEADER_LENGTH_WRITE(v, p)                         MWRITE_8((uint8_t *)p + 11, v)
+#define RDD_CSO_CONTEXT_ENTRY_IP_TOTAL_LENGTH_READ(r, p)                           MREAD_16((uint8_t *)p + 12, r)
+#define RDD_CSO_CONTEXT_ENTRY_IP_TOTAL_LENGTH_WRITE(v, p)                          MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_CSO_CONTEXT_ENTRY_IPV4_CSUM_READ(r, p)                                 MREAD_16((uint8_t *)p + 14, r)
+#define RDD_CSO_CONTEXT_ENTRY_IPV4_CSUM_WRITE(v, p)                                MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_CSO_CONTEXT_ENTRY_TCP_UDP_HEADER_OFFSET_READ(r, p)                     MREAD_8((uint8_t *)p + 16, r)
+#define RDD_CSO_CONTEXT_ENTRY_TCP_UDP_HEADER_OFFSET_WRITE(v, p)                    MWRITE_8((uint8_t *)p + 16, v)
+#define RDD_CSO_CONTEXT_ENTRY_TCP_UDP_HEADER_LENGTH_READ(r, p)                     MREAD_8((uint8_t *)p + 17, r)
+#define RDD_CSO_CONTEXT_ENTRY_TCP_UDP_HEADER_LENGTH_WRITE(v, p)                    MWRITE_8((uint8_t *)p + 17, v)
+#define RDD_CSO_CONTEXT_ENTRY_TCP_UDP_TOTAL_LENGTH_READ(r, p)                      MREAD_16((uint8_t *)p + 18, r)
+#define RDD_CSO_CONTEXT_ENTRY_TCP_UDP_TOTAL_LENGTH_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 18, v)
+#define RDD_CSO_CONTEXT_ENTRY_TCP_UDP_CSUM_READ(r, p)                              MREAD_16((uint8_t *)p + 20, r)
+#define RDD_CSO_CONTEXT_ENTRY_TCP_UDP_CSUM_WRITE(v, p)                             MWRITE_16((uint8_t *)p + 20, v)
+#define RDD_CSO_CONTEXT_ENTRY_MAX_CHUNK_LENGTH_READ(r, p)                          MREAD_8((uint8_t *)p + 22, r)
+#define RDD_CSO_CONTEXT_ENTRY_MAX_CHUNK_LENGTH_WRITE(v, p)                         MWRITE_8((uint8_t *)p + 22, v)
+#define RDD_CSO_CONTEXT_ENTRY_CHUNK_BYTES_LEFT_READ(r, p)                          MREAD_8((uint8_t *)p + 23, r)
+#define RDD_CSO_CONTEXT_ENTRY_CHUNK_BYTES_LEFT_WRITE(v, p)                         MWRITE_8((uint8_t *)p + 23, v)
+#define RDD_CSO_CONTEXT_ENTRY_NR_FRAGS_READ(r, p)                                  MREAD_8((uint8_t *)p + 24, r)
+#define RDD_CSO_CONTEXT_ENTRY_NR_FRAGS_WRITE(v, p)                                 MWRITE_8((uint8_t *)p + 24, v)
+#define RDD_CSO_CONTEXT_ENTRY_FRAG_INDEX_READ(r, p)                                MREAD_8((uint8_t *)p + 25, r)
+#define RDD_CSO_CONTEXT_ENTRY_FRAG_INDEX_WRITE(v, p)                               MWRITE_8((uint8_t *)p + 25, v)
+#define RDD_CSO_CONTEXT_ENTRY_FRAG_LEN_READ(r, p)                                  MREAD_16((uint8_t *)p + 26, r)
+#define RDD_CSO_CONTEXT_ENTRY_FRAG_LEN_WRITE(v, p)                                 MWRITE_16((uint8_t *)p + 26, v)
+#define RDD_CSO_CONTEXT_ENTRY_FRAG_DATA_READ(r, p)                                 MREAD_32((uint8_t *)p + 28, r)
+#define RDD_CSO_CONTEXT_ENTRY_FRAG_DATA_WRITE(v, p)                                MWRITE_32((uint8_t *)p + 28, v)
+#define RDD_CSO_CONTEXT_ENTRY_GOOD_CSUM_PACKETS_READ(r, p)                         MREAD_32((uint8_t *)p + 32, r)
+#define RDD_CSO_CONTEXT_ENTRY_GOOD_CSUM_PACKETS_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 32, v)
+#define RDD_CSO_CONTEXT_ENTRY_NO_CSUM_PACKETS_READ(r, p)                           MREAD_32((uint8_t *)p + 36, r)
+#define RDD_CSO_CONTEXT_ENTRY_NO_CSUM_PACKETS_WRITE(v, p)                          MWRITE_32((uint8_t *)p + 36, v)
+#define RDD_CSO_CONTEXT_ENTRY_BAD_IPV4_HDR_CSUM_PACKETS_READ(r, p)                 MREAD_32((uint8_t *)p + 40, r)
+#define RDD_CSO_CONTEXT_ENTRY_BAD_IPV4_HDR_CSUM_PACKETS_WRITE(v, p)                MWRITE_32((uint8_t *)p + 40, v)
+#define RDD_CSO_CONTEXT_ENTRY_BAD_TCP_UDP_CSUM_PACKETS_READ(r, p)                  MREAD_32((uint8_t *)p + 44, r)
+#define RDD_CSO_CONTEXT_ENTRY_BAD_TCP_UDP_CSUM_PACKETS_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 44, v)
+#define RDD_CSO_CONTEXT_ENTRY_FAIL_CODE_READ(r, p)                                 MREAD_8((uint8_t *)p + 48, r)
+#define RDD_CSO_CONTEXT_ENTRY_FAIL_CODE_WRITE(v, p)                                MWRITE_8((uint8_t *)p + 48, v)
+#define RDD_CSO_CONTEXT_ENTRY_DMA_SYNC_READ(r, p)                                  MREAD_8((uint8_t *)p + 49, r)
+#define RDD_CSO_CONTEXT_ENTRY_DMA_SYNC_WRITE(v, p)                                 MWRITE_8((uint8_t *)p + 49, v)
+#define RDD_CSO_CONTEXT_ENTRY_SEG_LENGTH_READ(r, p)                                MREAD_16((uint8_t *)p + 50, r)
+#define RDD_CSO_CONTEXT_ENTRY_SEG_LENGTH_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 50, v)
+#define RDD_CSO_CONTEXT_ENTRY_SEG_BYTES_LEFT_READ(r, p)                            MREAD_16((uint8_t *)p + 52, r)
+#define RDD_CSO_CONTEXT_ENTRY_SEG_BYTES_LEFT_WRITE(v, p)                           MWRITE_16((uint8_t *)p + 52, v)
+#define RDD_CSO_CONTEXT_ENTRY_PAYLOAD_LENGTH_READ(r, p)                            MREAD_16((uint8_t *)p + 54, r)
+#define RDD_CSO_CONTEXT_ENTRY_PAYLOAD_LENGTH_WRITE(v, p)                           MWRITE_16((uint8_t *)p + 54, v)
+#define RDD_CSO_CONTEXT_ENTRY_PAYLOAD_BYTES_LEFT_READ(r, p)                        MREAD_16((uint8_t *)p + 56, r)
+#define RDD_CSO_CONTEXT_ENTRY_PAYLOAD_BYTES_LEFT_WRITE(v, p)                       MWRITE_16((uint8_t *)p + 56, v)
+#define RDD_CSO_CONTEXT_ENTRY_PAYLOAD_PTR_READ(r, p)                               MREAD_32((uint8_t *)p + 60, r)
+#define RDD_CSO_CONTEXT_ENTRY_PAYLOAD_PTR_WRITE(v, p)                              MWRITE_32((uint8_t *)p + 60, v)
+#define RDD_CSO_CONTEXT_ENTRY_DDR_PAYLOAD_OFFSET_READ(r, p)                        MREAD_8((uint8_t *)p + 67, r)
+#define RDD_CSO_CONTEXT_ENTRY_DDR_PAYLOAD_OFFSET_WRITE(v, p)                       MWRITE_8((uint8_t *)p + 67, v)
+#define RDD_CSO_CONTEXT_ENTRY_DDR_SRC_ADDRESS_READ(r, p)                           MREAD_32((uint8_t *)p + 68, r)
+#define RDD_CSO_CONTEXT_ENTRY_DDR_SRC_ADDRESS_WRITE(v, p)                          MWRITE_32((uint8_t *)p + 68, v)
+#define RDD_CSO_CONTEXT_ENTRY_SAVED_IH_BUFFER_NUMBER_READ(r, p)                    MREAD_32((uint8_t *)p + 72, r)
+#define RDD_CSO_CONTEXT_ENTRY_SAVED_IH_BUFFER_NUMBER_WRITE(v, p)                   MWRITE_32((uint8_t *)p + 72, v)
+#define RDD_CSO_CONTEXT_ENTRY_SAVED_CSUM32_RET_ADDR_READ(r, p)                     MREAD_32((uint8_t *)p + 76, r)
+#define RDD_CSO_CONTEXT_ENTRY_SAVED_CSUM32_RET_ADDR_WRITE(v, p)                    MWRITE_32((uint8_t *)p + 76, v)
+#define RDD_CSO_CONTEXT_ENTRY_SAVED_R16_READ(r, p)                                 MREAD_32((uint8_t *)p + 80, r)
+#define RDD_CSO_CONTEXT_ENTRY_SAVED_R16_WRITE(v, p)                                MWRITE_32((uint8_t *)p + 80, v)
+#if defined DSL_63138
+
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE     40
+typedef struct
+{
+	RDD_GPON_ABSOLUTE_TX_COUNTER_DTS	entry[ RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_DTS;
+
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_PTR()	( RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_FLOW_RING_DROP_COUNTER_DTS;
+
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_PTR()	( RDD_US_DHD_FLOW_RING_DROP_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DHD_FLOW_RING_DROP_COUNTER_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	guaranteed_free_count    	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	non_guaranteed_free_count	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	guaranteed_threshold     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_DTS;
+
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_FREE_COUNT_READ(r, p)                     MREAD_16((uint8_t *)p, r)
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_FREE_COUNT_WRITE(v, p)                    MWRITE_16((uint8_t *)p, v)
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_NON_GUARANTEED_FREE_COUNT_READ(r, p)                 MREAD_16((uint8_t *)p + 2, r)
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_NON_GUARANTEED_FREE_COUNT_WRITE(v, p)                MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_THRESHOLD_READ(r, p)                      MREAD_16((uint8_t *)p + 4, r)
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_THRESHOLD_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined DSL_63138
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_PTR()	( RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	flow_id   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_ENTRY_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_ENTRY_FLOW_ID_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_ENTRY_FLOW_ID_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE     32
+typedef struct
+{
+	RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DATA_POINTER_DUMMY_TARGET_SIZE     2
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DATA_POINTER_DUMMY_TARGET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DATA_POINTER_DUMMY_TARGET_DTS;
+
+#define RDD_DATA_POINTER_DUMMY_TARGET_PTR()	( RDD_DATA_POINTER_DUMMY_TARGET_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DATA_POINTER_DUMMY_TARGET_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_PTR()	( RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_WAN_TX_SCRATCH_SIZE     24
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_WAN_TX_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SCRATCH_DTS;
+
+#define RDD_WAN_TX_SCRATCH_PTR()	( RDD_WAN_TX_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_TX_SCRATCH_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE     3
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2    6
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE ][ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_DTS;
+
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_PTR()	( RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_ENTRY_DTS	entry[ RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR()	( RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE     9
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_PTR()	( RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE     14
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_DTS;
+
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_PTR()	( RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + CPU_TX_DHD_LAYER2_HEADER_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_TASK_REORDER_ENTRY_DTS	entry[ RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_PTR()	( RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_PTR()	( RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	exponent  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_CONTROLLER_EXPONENT_ENTRY_DTS;
+
+#define RDD_RATE_CONTROLLER_EXPONENT_ENTRY_EXPONENT_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_RATE_CONTROLLER_EXPONENT_ENTRY_EXPONENT_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+
+#define RDD_RATE_CONTROLLER_EXPONENT_TABLE_SIZE     4
+typedef struct
+{
+	RDD_RATE_CONTROLLER_EXPONENT_ENTRY_DTS	entry[ RDD_RATE_CONTROLLER_EXPONENT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_CONTROLLER_EXPONENT_TABLE_DTS;
+
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_PTR()	( RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS )
+
+
+typedef struct
+{
+	uint16_t	entry     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_DTS;
+
+#define RDD_LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ENTRY_READ(r, p)                 MREAD_16((uint8_t *)p, r)
+#define RDD_LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ENTRY_WRITE(v, p)                MWRITE_16((uint8_t *)p, v)
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_DTS;
+
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_ENQUEUE_INGRESS_QUEUE_PTR_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_ETH1_RX_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_ETH1_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH1_RX_DESCRIPTORS_DTS;
+
+#define RDD_ETH1_RX_DESCRIPTORS_PTR()	( RDD_ETH1_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETH1_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved_fw_only	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_TX_WAN_CHANNEL_INDEX_DTS;
+
+/* COMMON_A */
+#if defined DSL_63138
+
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE     384
+typedef struct
+{
+	RDD_SIXTEEN_BYTES_DTS	entry[ RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_DTS;
+
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_PTR()	( RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DDR_CACHE_FIFO_ADDRESS )
+
+#endif
+#define RDD_RUNNER_SCRATCHPAD_RESERVED_FW_ONLY_NUMBER	64
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_RUNNER_SCRATCHPAD_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_SCRATCHPAD_DTS;
+
+#if defined DSL_63138
+
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_PTR()	( RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + FC_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_PTR()	( RDD_CPU_RX_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + CPU_RX_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_PTR()	( RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_PTR()	( RDD_RUNNER_FWTRACE_MAINA_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_MAINA_BASE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOA_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_PTR()	( RDD_RUNNER_FWTRACE_PICOA_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_PICOA_BASE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	mac_address_high	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mac_address_mid 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mac_address_low 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	radio_index     	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ssid            	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flowring_index  	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1       	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_priority     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reference_count 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_DHD_STATION_ENTRY_DTS;
+
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_MAC_ADDRESS_HIGH_READ(r, p)                 MREAD_16((uint8_t *)p, r)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_MAC_ADDRESS_HIGH_WRITE(v, p)                MWRITE_16((uint8_t *)p, v)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_MAC_ADDRESS_MID_READ(r, p)                  MREAD_16((uint8_t *)p + 2, r)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_MAC_ADDRESS_MID_WRITE(v, p)                 MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_MAC_ADDRESS_LOW_READ(r, p)                  MREAD_16((uint8_t *)p + 4, r)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_MAC_ADDRESS_LOW_WRITE(v, p)                 MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_RADIO_INDEX_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 6, 6, 2, r)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_RADIO_INDEX_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 6, 6, 2, v)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_SSID_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 6, 2, 4, r)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_SSID_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 6, 2, 4, v)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_FLOWRING_INDEX_READ(r, p)                   FIELD_MREAD_16((uint8_t *)p + 6, 0, 10, r)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_FLOWRING_INDEX_WRITE(v, p)                  FIELD_MWRITE_16((uint8_t *)p + 6, 0, 10, v)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_TX_PRIORITY_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 8, 0, 3, r)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_TX_PRIORITY_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 8, 0, 3, v)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_REFERENCE_COUNT_READ(r, p)                  MREAD_8((uint8_t *)p + 9, r)
+#define RDD_WLAN_MCAST_DHD_STATION_ENTRY_REFERENCE_COUNT_WRITE(v, p)                 MWRITE_8((uint8_t *)p + 9, v)
+#if defined DSL_63138
+
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_DHD_STATION_ENTRY_DTS	entry[ RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_DHD_STATION_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_PTR()	( RDD_WLAN_MCAST_DHD_STATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_DHD_STATION_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	cpu_rx_queue	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_REASON_TO_CPU_RX_QUEUE_ENTRY_DTS;
+
+#define RDD_CPU_REASON_TO_CPU_RX_QUEUE_ENTRY_CPU_RX_QUEUE_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_CPU_REASON_TO_CPU_RX_QUEUE_ENTRY_CPU_RX_QUEUE_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+
+#define RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE     2
+#define RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE2    64
+typedef struct
+{
+	RDD_CPU_REASON_TO_CPU_RX_QUEUE_ENTRY_DTS	entry[ RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE ][ RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS;
+
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_PTR()	( RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS )
+
+
+typedef struct
+{
+	uint32_t	user_defined	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mac_addr0   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mac_addr1   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mac_addr2   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mac_addr3   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mac_addr4   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mac_addr5   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aging       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	skip        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_ENTRY_DTS;
+
+#define RDD_MAC_ENTRY_USER_DEFINED_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p, 4, 12, r)
+#define RDD_MAC_ENTRY_USER_DEFINED_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p, 4, 12, v)
+#define RDD_MAC_ENTRY_MAC_ADDR0_READ(r, p)                    FIELD_MREAD_32((uint8_t *)p + 0, 12, 8, r)
+#define RDD_MAC_ENTRY_MAC_ADDR0_WRITE(v, p)                   FIELD_MWRITE_32((uint8_t *)p + 0, 12, 8, v)
+#define RDD_MAC_ENTRY_MAC_ADDR1_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 2, 4, 8, r)
+#define RDD_MAC_ENTRY_MAC_ADDR1_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 2, 4, 8, v)
+#define RDD_MAC_ENTRY_MAC_ADDR2_READ(r, p)                    { uint32_t temp; FIELD_MREAD_32((uint8_t *)p, 0, 4, temp); r = temp << 4; FIELD_MREAD_32(((uint8_t *)p + 4), 28, 4, temp); r = r | temp; }
+#define RDD_MAC_ENTRY_MAC_ADDR2_WRITE(v, p)                   { FIELD_MWRITE_32((uint8_t *)p, 0, 4, ((v & 0xfffffff0) >> 4)); FIELD_MWRITE_32(((uint8_t *)p + 4), 28, 4, (v & 0x0000000f)); }
+#define RDD_MAC_ENTRY_MAC_ADDR3_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 4, 4, 8, r)
+#define RDD_MAC_ENTRY_MAC_ADDR3_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 4, 4, 8, v)
+#define RDD_MAC_ENTRY_MAC_ADDR4_READ(r, p)                    FIELD_MREAD_32((uint8_t *)p + 4, 12, 8, r)
+#define RDD_MAC_ENTRY_MAC_ADDR4_WRITE(v, p)                   FIELD_MWRITE_32((uint8_t *)p + 4, 12, 8, v)
+#define RDD_MAC_ENTRY_MAC_ADDR5_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 6, 4, 8, r)
+#define RDD_MAC_ENTRY_MAC_ADDR5_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 6, 4, 8, v)
+#define RDD_MAC_ENTRY_AGING_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 7, 2, 1, r)
+#define RDD_MAC_ENTRY_AGING_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 7, 2, 1, v)
+#define RDD_MAC_ENTRY_SKIP_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 7, 1, 1, r)
+#define RDD_MAC_ENTRY_SKIP_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 7, 1, 1, v)
+#define RDD_MAC_ENTRY_VALID_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 7, 0, 1, r)
+#define RDD_MAC_ENTRY_VALID_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 7, 0, 1, v)
+#if defined DSL_63138
+
+#define RDD_MAC_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_ENTRY_DTS	entry[ RDD_MAC_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_TABLE_CAM_DTS;
+
+#define RDD_MAC_TABLE_CAM_PTR()	( RDD_MAC_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_TABLE_CAM_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_MAC_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_ENTRY_DTS	entry[ RDD_MAC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_TABLE_DTS;
+
+#define RDD_MAC_TABLE_PTR()	( RDD_MAC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+typedef struct
+{
+	uint32_t	reserved0         	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_offset    	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error_type        	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	source_bridge_port	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number     	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETHWAN2_RX_DESCRIPTOR_DTS;
+
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PAYLOAD_OFFSET_READ(r, p)                     FIELD_MREAD_32((uint8_t *)p + 0, 14, 7, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PAYLOAD_OFFSET_WRITE(v, p)                    FIELD_MWRITE_32((uint8_t *)p + 0, 14, 7, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 2, 0, 14, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 2, 0, 14, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_TYPE_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p + 4, 6, 7, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_TYPE_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p + 4, 6, 7, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_SOURCE_BRIDGE_PORT_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 5, 0, 6, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_SOURCE_BRIDGE_PORT_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 5, 0, 6, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 6, 7, 1, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 6, 7, 1, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 6, 0, 15, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 6, 0, 15, v)
+#endif
+#if defined DSL_63138
+
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE     32
+typedef struct
+{
+	RDD_ETHWAN2_RX_DESCRIPTOR_DTS	entry[ RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETHWAN2_RX_INGRESS_QUEUE_DTS;
+
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_PTR()	( RDD_ETHWAN2_RX_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + ETHWAN2_RX_INGRESS_QUEUE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	trace_on      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	trace_off_perm	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	unused        	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocs        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TRACE_C_ENTRY_DTS;
+
+#define RDD_TRACE_C_ENTRY_TRACE_ON_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_TRACE_C_ENTRY_TRACE_ON_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_TRACE_C_ENTRY_TRACE_OFF_PERM_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 6, 1, r)
+#define RDD_TRACE_C_ENTRY_TRACE_OFF_PERM_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 6, 1, v)
+#define RDD_TRACE_C_ENTRY_UNUSED_READ(r, p)                         FIELD_MREAD_32((uint8_t *)p, 0, 30, r)
+#define RDD_TRACE_C_ENTRY_UNUSED_WRITE(v, p)                        FIELD_MWRITE_32((uint8_t *)p, 0, 30, v)
+#define RDD_TRACE_C_ENTRY_ALLOCS_READ(r, p)                         MREAD_32((uint8_t *)p + 4, r)
+#define RDD_TRACE_C_ENTRY_ALLOCS_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 4, v)
+#if defined DSL_63138
+
+#define RDD_TRACE_C_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TRACE_C_ENTRY_DTS	entry[ RDD_TRACE_C_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TRACE_C_TABLE_DTS;
+
+#define RDD_TRACE_C_TABLE_PTR()	( RDD_TRACE_C_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + TRACE_C_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_PTR()	( RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_MAINA_CURR_OFFSET_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved_fw_only	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FREE_SKB_INDEXES_FIFO_TAIL_DTS;
+
+#if defined DSL_63138
+
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE     2
+typedef struct
+{
+	RDD_FREE_SKB_INDEXES_FIFO_TAIL_DTS	entry[ RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_DTS;
+
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_PTR()	( RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + FREE_SKB_INDEXES_DDR_FIFO_TAIL_ADDRESS )
+
+#endif
+#define RDD_BPM_REPLY_RESERVED_FW_ONLY_NUMBER	12
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_BPM_REPLY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BPM_REPLY_DTS;
+
+
+typedef struct
+{
+	uint32_t	bq_next_idx_or_cpu_tx_frid	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = bq_next_idx_or_cpu_tx_frid, size = 32 bits
+	uint32_t	next_idx          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0         	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1         	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	radio_idx         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_id      	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2         	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	request_id        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wifi_egress_params_u	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = wifi_egress_params_u, size = 32 bits
+	uint32_t	wifi_egress_params	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	priority          	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wifi_ssid         	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_udp            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_tcp            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	spd_svc_flag      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_bridge_port   	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	data_len          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	data_buf_addr_low 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_BACKUP_ENTRY_DTS;
+
+#define RDD_DHD_BACKUP_ENTRY_BQ_NEXT_IDX_OR_CPU_TX_FRID_READ(r, p)         MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_BACKUP_ENTRY_BQ_NEXT_IDX_OR_CPU_TX_FRID_WRITE(v, p)        MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_BACKUP_ENTRY_BQ_NEXT_IDX_OR_CPU_TX_FRID_L_READ( wv )       FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_BACKUP_ENTRY_BQ_NEXT_IDX_OR_CPU_TX_FRID_L_WRITE( v, wv )   FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_BACKUP_ENTRY_NEXT_IDX_READ(r, p)                           MREAD_16((uint8_t *)p, r)
+#define RDD_DHD_BACKUP_ENTRY_NEXT_IDX_WRITE(v, p)                          MWRITE_16((uint8_t *)p, v)
+#define RDD_DHD_BACKUP_ENTRY_NEXT_IDX_L_READ( wv )                         FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_BACKUP_ENTRY_NEXT_IDX_L_WRITE( v, wv )                     FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_BACKUP_ENTRY_VALID_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_DHD_BACKUP_ENTRY_VALID_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_DHD_BACKUP_ENTRY_VALID_L_READ( wv )                            FIELD_GET( wv, 31, 1 )
+#define RDD_DHD_BACKUP_ENTRY_VALID_L_WRITE( v, wv )                        FIELD_SET( v, 31, 1, wv )
+#define RDD_DHD_BACKUP_ENTRY_RADIO_IDX_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p, 2, 2, r)
+#define RDD_DHD_BACKUP_ENTRY_RADIO_IDX_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p, 2, 2, v)
+#define RDD_DHD_BACKUP_ENTRY_RADIO_IDX_L_READ( wv )                        FIELD_GET( wv, 26, 2 )
+#define RDD_DHD_BACKUP_ENTRY_RADIO_IDX_L_WRITE( v, wv )                    FIELD_SET( v, 26, 2, wv )
+#define RDD_DHD_BACKUP_ENTRY_FLOW_RING_ID_READ(r, p)                       FIELD_MREAD_16((uint8_t *)p, 0, 10, r)
+#define RDD_DHD_BACKUP_ENTRY_FLOW_RING_ID_WRITE(v, p)                      FIELD_MWRITE_16((uint8_t *)p, 0, 10, v)
+#define RDD_DHD_BACKUP_ENTRY_FLOW_RING_ID_L_READ( wv )                     FIELD_GET( wv, 16, 10 )
+#define RDD_DHD_BACKUP_ENTRY_FLOW_RING_ID_L_WRITE( v, wv )                 FIELD_SET( v, 16, 10, wv )
+#define RDD_DHD_BACKUP_ENTRY_REQUEST_ID_READ(r, p)                         MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_BACKUP_ENTRY_REQUEST_ID_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_BACKUP_ENTRY_REQUEST_ID_L_READ( wv )                       FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_BACKUP_ENTRY_REQUEST_ID_L_WRITE( v, wv )                   FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_BACKUP_ENTRY_WIFI_EGRESS_PARAMS_U_READ(r, p)               MREAD_32((uint8_t *)p + 8, r)
+#define RDD_DHD_BACKUP_ENTRY_WIFI_EGRESS_PARAMS_U_WRITE(v, p)              MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_DHD_BACKUP_ENTRY_WIFI_EGRESS_PARAMS_U_L_READ( wv )             FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_BACKUP_ENTRY_WIFI_EGRESS_PARAMS_U_L_WRITE( v, wv )         FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_BACKUP_ENTRY_WIFI_EGRESS_PARAMS_READ(r, p)                 MREAD_32((uint8_t *)p + 8, r)
+#define RDD_DHD_BACKUP_ENTRY_WIFI_EGRESS_PARAMS_WRITE(v, p)                MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_DHD_BACKUP_ENTRY_WIFI_EGRESS_PARAMS_L_READ( wv )               FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_BACKUP_ENTRY_WIFI_EGRESS_PARAMS_L_WRITE( v, wv )           FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_BACKUP_ENTRY_PRIORITY_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 8, 5, 3, r)
+#define RDD_DHD_BACKUP_ENTRY_PRIORITY_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 8, 5, 3, v)
+#define RDD_DHD_BACKUP_ENTRY_PRIORITY_L_READ( wv )                         FIELD_GET( wv, 29, 3 )
+#define RDD_DHD_BACKUP_ENTRY_PRIORITY_L_WRITE( v, wv )                     FIELD_SET( v, 29, 3, wv )
+#define RDD_DHD_BACKUP_ENTRY_WIFI_SSID_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 8, 0, 5, r)
+#define RDD_DHD_BACKUP_ENTRY_WIFI_SSID_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 8, 0, 5, v)
+#define RDD_DHD_BACKUP_ENTRY_WIFI_SSID_L_READ( wv )                        FIELD_GET( wv, 24, 5 )
+#define RDD_DHD_BACKUP_ENTRY_WIFI_SSID_L_WRITE( v, wv )                    FIELD_SET( v, 24, 5, wv )
+#define RDD_DHD_BACKUP_ENTRY_IS_UDP_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 9, 7, 1, r)
+#define RDD_DHD_BACKUP_ENTRY_IS_UDP_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 9, 7, 1, v)
+#define RDD_DHD_BACKUP_ENTRY_IS_UDP_L_READ( wv )                           FIELD_GET( wv, 23, 1 )
+#define RDD_DHD_BACKUP_ENTRY_IS_UDP_L_WRITE( v, wv )                       FIELD_SET( v, 23, 1, wv )
+#define RDD_DHD_BACKUP_ENTRY_IS_TCP_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 9, 6, 1, r)
+#define RDD_DHD_BACKUP_ENTRY_IS_TCP_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 9, 6, 1, v)
+#define RDD_DHD_BACKUP_ENTRY_IS_TCP_L_READ( wv )                           FIELD_GET( wv, 22, 1 )
+#define RDD_DHD_BACKUP_ENTRY_IS_TCP_L_WRITE( v, wv )                       FIELD_SET( v, 22, 1, wv )
+#define RDD_DHD_BACKUP_ENTRY_SPD_SVC_FLAG_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 9, 5, 1, r)
+#define RDD_DHD_BACKUP_ENTRY_SPD_SVC_FLAG_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 9, 5, 1, v)
+#define RDD_DHD_BACKUP_ENTRY_SPD_SVC_FLAG_L_READ( wv )                     FIELD_GET( wv, 21, 1 )
+#define RDD_DHD_BACKUP_ENTRY_SPD_SVC_FLAG_L_WRITE( v, wv )                 FIELD_SET( v, 21, 1, wv )
+#define RDD_DHD_BACKUP_ENTRY_SRC_BRIDGE_PORT_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 9, 0, 5, r)
+#define RDD_DHD_BACKUP_ENTRY_SRC_BRIDGE_PORT_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 9, 0, 5, v)
+#define RDD_DHD_BACKUP_ENTRY_SRC_BRIDGE_PORT_L_READ( wv )                  FIELD_GET( wv, 16, 5 )
+#define RDD_DHD_BACKUP_ENTRY_SRC_BRIDGE_PORT_L_WRITE( v, wv )              FIELD_SET( v, 16, 5, wv )
+#define RDD_DHD_BACKUP_ENTRY_DATA_LEN_READ(r, p)                           MREAD_16((uint8_t *)p + 10, r)
+#define RDD_DHD_BACKUP_ENTRY_DATA_LEN_WRITE(v, p)                          MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_DHD_BACKUP_ENTRY_DATA_LEN_L_READ( wv )                         FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_BACKUP_ENTRY_DATA_LEN_L_WRITE( v, wv )                     FIELD_SET( v, 0, 16, wv )
+#define RDD_DHD_BACKUP_ENTRY_DATA_BUF_ADDR_LOW_READ(r, p)                  MREAD_32((uint8_t *)p + 12, r)
+#define RDD_DHD_BACKUP_ENTRY_DATA_BUF_ADDR_LOW_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_DHD_BACKUP_ENTRY_DATA_BUF_ADDR_LOW_L_READ( wv )                FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_BACKUP_ENTRY_DATA_BUF_ADDR_LOW_L_WRITE( v, wv )            FIELD_SET( v, 0, 32, wv )
+
+typedef struct
+{
+	uint16_t	multicast       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	multicast_vector	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	egress_port     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	move_indication 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	mac_type        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	da_action       	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	sa_action       	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_CONTEXT_ENTRY_DTS;
+
+#define RDD_MAC_CONTEXT_ENTRY_MULTICAST_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_MAC_CONTEXT_ENTRY_MULTICAST_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_MAC_CONTEXT_ENTRY_MULTICAST_VECTOR_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 5, 2, r)
+#define RDD_MAC_CONTEXT_ENTRY_MULTICAST_VECTOR_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 5, 2, v)
+#define RDD_MAC_CONTEXT_ENTRY_EGRESS_PORT_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p, 0, 5, r)
+#define RDD_MAC_CONTEXT_ENTRY_EGRESS_PORT_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p, 0, 5, v)
+#define RDD_MAC_CONTEXT_ENTRY_MOVE_INDICATION_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 1, 7, 1, r)
+#define RDD_MAC_CONTEXT_ENTRY_MOVE_INDICATION_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 1, 7, 1, v)
+#define RDD_MAC_CONTEXT_ENTRY_MAC_TYPE_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 1, 6, 1, r)
+#define RDD_MAC_CONTEXT_ENTRY_MAC_TYPE_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 1, 6, 1, v)
+#define RDD_MAC_CONTEXT_ENTRY_DA_ACTION_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 1, 3, 3, r)
+#define RDD_MAC_CONTEXT_ENTRY_DA_ACTION_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 1, 3, 3, v)
+#define RDD_MAC_CONTEXT_ENTRY_SA_ACTION_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 1, 0, 3, r)
+#define RDD_MAC_CONTEXT_ENTRY_SA_ACTION_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 1, 0, 3, v)
+#if defined DSL_63138
+
+#define RDD_MAC_CONTEXT_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_CONTEXT_ENTRY_DTS	entry[ RDD_MAC_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_CONTEXT_TABLE_DTS;
+
+#define RDD_MAC_CONTEXT_TABLE_PTR()	( RDD_MAC_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_CONTEXT_TABLE_ADDRESS )
+
+#endif
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_RESERVED_FW_ONLY_NUMBER	24
+
+typedef struct
+{
+	uint16_t	reserved_fw_only[RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE     32
+typedef struct
+{
+	RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	reserved_fw_only	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BYTES_2_DTS;
+
+#if defined DSL_63138
+
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+typedef struct
+{
+	RDD_BYTES_2_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	valid            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_list_size    	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_proxy_enabled 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_priority      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_0_priority   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_1_priority   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_2_priority   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_0_ssid_vector	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_1_ssid_vector	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_2_ssid_vector	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_FWD_ENTRY_DTS;
+
+#define RDD_WLAN_MCAST_FWD_ENTRY_VALID_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_WLAN_MCAST_FWD_ENTRY_VALID_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_WLAN_MCAST_FWD_ENTRY_DHD_LIST_SIZE_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p, 0, 7, r)
+#define RDD_WLAN_MCAST_FWD_ENTRY_DHD_LIST_SIZE_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p, 0, 7, v)
+#define RDD_WLAN_MCAST_FWD_ENTRY_IS_PROXY_ENABLED_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 1, 6, 1, r)
+#define RDD_WLAN_MCAST_FWD_ENTRY_IS_PROXY_ENABLED_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 1, 6, 1, v)
+#define RDD_WLAN_MCAST_FWD_ENTRY_TX_PRIORITY_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 1, 3, 3, r)
+#define RDD_WLAN_MCAST_FWD_ENTRY_TX_PRIORITY_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 1, 3, 3, v)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_0_PRIORITY_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 1, 2, 1, r)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_0_PRIORITY_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 1, 2, 1, v)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_1_PRIORITY_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 1, 1, 1, r)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_1_PRIORITY_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 1, 1, 1, v)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_2_PRIORITY_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 1, 0, 1, r)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_2_PRIORITY_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 1, 0, 1, v)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_0_SSID_VECTOR_READ(r, p)                 MREAD_16((uint8_t *)p + 2, r)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_0_SSID_VECTOR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_1_SSID_VECTOR_READ(r, p)                 MREAD_16((uint8_t *)p + 4, r)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_1_SSID_VECTOR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_2_SSID_VECTOR_READ(r, p)                 MREAD_16((uint8_t *)p + 6, r)
+#define RDD_WLAN_MCAST_FWD_ENTRY_WFD_2_SSID_VECTOR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 6, v)
+#if defined DSL_63138
+
+#define RDD_WLAN_MCAST_FWD_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_FWD_ENTRY_DTS	entry[ RDD_WLAN_MCAST_FWD_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_FWD_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_FWD_TABLE_PTR()	( RDD_WLAN_MCAST_FWD_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_FWD_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	head_idx            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tail_idx            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_counter      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid_entries_number	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tail_entry          	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	head_entry          	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_threshold    	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	queue_state         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	profile_id          	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved            	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tail_base_entry     	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	profile_en          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	union_field1        	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = union_field1, size = 7 bits
+	uint32_t	reserved0           	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	drop_bit            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_controller_id  	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	queue_mask          	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cache_ptr           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DDR_QUEUE_DESCRIPTOR_DTS;
+
+#define RDD_DDR_QUEUE_DESCRIPTOR_HEAD_IDX_READ(r, p)                             MREAD_16((uint8_t *)p, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_HEAD_IDX_WRITE(v, p)                            MWRITE_16((uint8_t *)p, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_TAIL_IDX_READ(r, p)                             MREAD_16((uint8_t *)p + 2, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_TAIL_IDX_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_PACKET_COUNTER_READ(r, p)                       MREAD_16((uint8_t *)p + 4, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_PACKET_COUNTER_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_VALID_ENTRIES_NUMBER_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 6, 4, 4, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_VALID_ENTRIES_NUMBER_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 6, 4, 4, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_TAIL_ENTRY_READ(r, p)                           FIELD_MREAD_16((uint8_t *)p + 6, 6, 6, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_TAIL_ENTRY_WRITE(v, p)                          FIELD_MWRITE_16((uint8_t *)p + 6, 6, 6, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_HEAD_ENTRY_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 7, 0, 6, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_HEAD_ENTRY_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 7, 0, 6, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_PACKET_THRESHOLD_READ(r, p)                     MREAD_16((uint8_t *)p + 8, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_PACKET_THRESHOLD_WRITE(v, p)                    MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_QUEUE_STATE_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 10, 7, 1, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_QUEUE_STATE_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 10, 7, 1, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_PROFILE_ID_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 10, 2, 5, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_PROFILE_ID_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 10, 2, 5, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_TAIL_BASE_ENTRY_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 11, 0, 6, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_TAIL_BASE_ENTRY_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 11, 0, 6, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_PROFILE_EN_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 12, 7, 1, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_PROFILE_EN_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_UNION_FIELD1_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 12, 0, 7, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_UNION_FIELD1_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 12, 0, 7, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_DROP_BIT_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 12, 0, 1, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_DROP_BIT_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 12, 0, 1, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_RATE_CONTROLLER_ID_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 12, 0, 7, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_RATE_CONTROLLER_ID_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 12, 0, 7, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_QUEUE_MASK_READ(r, p)                           MREAD_8((uint8_t *)p + 13, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_QUEUE_MASK_WRITE(v, p)                          MWRITE_8((uint8_t *)p + 13, v)
+#define RDD_DDR_QUEUE_DESCRIPTOR_CACHE_PTR_READ(r, p)                            MREAD_16((uint8_t *)p + 14, r)
+#define RDD_DDR_QUEUE_DESCRIPTOR_CACHE_PTR_WRITE(v, p)                           MWRITE_16((uint8_t *)p + 14, v)
+#if defined DSL_63138
+
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DDR_QUEUE_DESCRIPTOR_DTS	entry[ RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_PTR()	( RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DESCRIPTOR_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	mac_address_high	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mac_address_low 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reference_count 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1       	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_SSID_MAC_ADDRESS_ENTRY_DTS;
+
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_ENTRY_MAC_ADDRESS_HIGH_READ(r, p)                 MREAD_32((uint8_t *)p, r)
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_ENTRY_MAC_ADDRESS_HIGH_WRITE(v, p)                MWRITE_32((uint8_t *)p, v)
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_ENTRY_MAC_ADDRESS_LOW_READ(r, p)                  MREAD_16((uint8_t *)p + 4, r)
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_ENTRY_MAC_ADDRESS_LOW_WRITE(v, p)                 MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_ENTRY_REFERENCE_COUNT_READ(r, p)                  MREAD_8((uint8_t *)p + 6, r)
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_ENTRY_REFERENCE_COUNT_WRITE(v, p)                 MWRITE_8((uint8_t *)p + 6, v)
+#if defined DSL_63138
+
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE     48
+typedef struct
+{
+	RDD_WLAN_MCAST_SSID_MAC_ADDRESS_ENTRY_DTS	entry[ RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_PTR()	( RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE     8
+typedef struct
+{
+	RDD_DHD_BACKUP_ENTRY_DTS	entry[ RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_POST_REQUEST_QUEUE_DTS;
+
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_PTR()	( RDD_CPU_TX_POST_REQUEST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + CPU_TX_POST_REQUEST_QUEUE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	packets   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bytes     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_SSID_STATS_ENTRY_DTS;
+
+#define RDD_WLAN_MCAST_SSID_STATS_ENTRY_PACKETS_READ(r, p)                 MREAD_32((uint8_t *)p, r)
+#define RDD_WLAN_MCAST_SSID_STATS_ENTRY_PACKETS_WRITE(v, p)                MWRITE_32((uint8_t *)p, v)
+#define RDD_WLAN_MCAST_SSID_STATS_ENTRY_BYTES_READ(r, p)                   MREAD_32((uint8_t *)p + 4, r)
+#define RDD_WLAN_MCAST_SSID_STATS_ENTRY_BYTES_WRITE(v, p)                  MWRITE_32((uint8_t *)p + 4, v)
+#if defined DSL_63138
+
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE     48
+typedef struct
+{
+	RDD_WLAN_MCAST_SSID_STATS_ENTRY_DTS	entry[ RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_SSID_STATS_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_PTR()	( RDD_WLAN_MCAST_SSID_STATS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_SSID_STATS_TABLE_ADDRESS )
+
+#endif
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_RESERVED2_NUMBER	8
+
+typedef struct
+{
+	uint32_t	ds_dhd_doorbell_post                                                	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ds_dhd_doorbell_complete                                            	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ds_rd_fr_r2d_indexes                                                	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ds_wr_fr_r2d_indexes                                                	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_rd_fr_d2r_indexes                                                	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_wr_fr_d2r_indexes                                                	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_complete_packet_counter                                          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_format                                                    	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	idma_active                                                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                                                           	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	coalescing_max_count                                                	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cur_frg_id                                                          	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	coalescing_timeout                                                  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	coalescing_timeout_cntr                                             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	reserved2[RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_RESERVED2_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DTS;
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DS_DHD_DOORBELL_POST_READ(r, p)                       MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DS_DHD_DOORBELL_POST_WRITE(v, p)                      MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DS_DHD_DOORBELL_COMPLETE_READ(r, p)                   MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DS_DHD_DOORBELL_COMPLETE_WRITE(v, p)                  MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DS_RD_FR_R2D_INDEXES_READ(r, p)                       MREAD_16((uint8_t *)p + 8, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DS_RD_FR_R2D_INDEXES_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DS_WR_FR_R2D_INDEXES_READ(r, p)                       MREAD_16((uint8_t *)p + 10, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DS_WR_FR_R2D_INDEXES_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_TX_RD_FR_D2R_INDEXES_READ(r, p)                       MREAD_16((uint8_t *)p + 12, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_TX_RD_FR_D2R_INDEXES_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_TX_WR_FR_D2R_INDEXES_READ(r, p)                       MREAD_16((uint8_t *)p + 14, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_TX_WR_FR_D2R_INDEXES_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_TX_COMPLETE_PACKET_COUNTER_READ(r, p)                 MREAD_16((uint8_t *)p + 16, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_TX_COMPLETE_PACKET_COUNTER_WRITE(v, p)                MWRITE_16((uint8_t *)p + 16, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_FLOW_RING_FORMAT_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 18, 5, 3, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_FLOW_RING_FORMAT_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 18, 5, 3, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_IDMA_ACTIVE_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 18, 4, 1, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_IDMA_ACTIVE_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 18, 4, 1, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_COALESCING_MAX_COUNT_READ(r, p)                       MREAD_8((uint8_t *)p + 20, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_COALESCING_MAX_COUNT_WRITE(v, p)                      MWRITE_8((uint8_t *)p + 20, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_CUR_FRG_ID_READ(r, p)                                 MREAD_8((uint8_t *)p + 21, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_CUR_FRG_ID_WRITE(v, p)                                MWRITE_8((uint8_t *)p + 21, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_COALESCING_TIMEOUT_READ(r, p)                         MREAD_8((uint8_t *)p + 22, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_COALESCING_TIMEOUT_WRITE(v, p)                        MWRITE_8((uint8_t *)p + 22, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_COALESCING_TIMEOUT_CNTR_READ(r, p)                    MREAD_8((uint8_t *)p + 23, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_COALESCING_TIMEOUT_CNTR_WRITE(v, p)                   MWRITE_8((uint8_t *)p + 23, v)
+#if defined DSL_63138
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE     3
+typedef struct
+{
+	RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DTS	entry[ RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_DTS;
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_PTR()	( RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_RADIO_INSTANCE_COMMON_A_DATA_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint16_t	invalid     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	reserved    	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	radio_idx   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	flow_ring_id	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_DTS;
+
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_INVALID_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_INVALID_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_INVALID_L_READ( wv )                    FIELD_GET( wv, 15, 1 )
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_INVALID_L_WRITE( v, wv )                FIELD_SET( v, 15, 1, wv )
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_RADIO_IDX_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p, 2, 2, r)
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_RADIO_IDX_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p, 2, 2, v)
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_RADIO_IDX_L_READ( wv )                  FIELD_GET( wv, 10, 2 )
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_RADIO_IDX_L_WRITE( v, wv )              FIELD_SET( v, 10, 2, wv )
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_FLOW_RING_ID_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p, 0, 10, r)
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_FLOW_RING_ID_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p, 0, 10, v)
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_FLOW_RING_ID_L_READ( wv )               FIELD_GET( wv, 0, 10 )
+#define RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_FLOW_RING_ID_L_WRITE( v, wv )           FIELD_SET( v, 0, 10, wv )
+#if defined DSL_63138
+
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_DTS	entry[ RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS;
+
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_PTR()	( RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	key_index 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_0     	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_1     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aging     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	skip      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	context   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_2     	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_3     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_DTS;
+
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_KEY_INDEX_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 4, 4, r)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_KEY_INDEX_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 4, 4, v)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_KEY_0_READ(r, p)                     FIELD_MREAD_32((uint8_t *)p, 4, 24, r)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_KEY_0_WRITE(v, p)                    FIELD_MWRITE_32((uint8_t *)p, 4, 24, v)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_KEY_1_READ(r, p)                     { uint32_t temp; FIELD_MREAD_32((uint8_t *)p, 0, 4, temp); r = temp << 28; FIELD_MREAD_32(((uint8_t *)p + 4), 4, 28, temp); r = r | temp; }
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_KEY_1_WRITE(v, p)                    { FIELD_MWRITE_32((uint8_t *)p, 0, 4, ((v & 0xf0000000) >> 28)); FIELD_MWRITE_32(((uint8_t *)p + 4), 4, 28, (v & 0x0fffffff)); }
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_AGING_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 7, 2, 1, r)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_AGING_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 7, 2, 1, v)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_SKIP_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 7, 1, 1, r)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_SKIP_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 7, 1, 1, v)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_VALID_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 7, 0, 1, r)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_VALID_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 7, 0, 1, v)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_CONTEXT_READ(r, p)                   MREAD_8((uint8_t *)p + 8, r)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_CONTEXT_WRITE(v, p)                  MWRITE_8((uint8_t *)p + 8, v)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_KEY_2_READ(r, p)                     FIELD_MREAD_32((uint8_t *)p + 8, 0, 24, r)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_KEY_2_WRITE(v, p)                    FIELD_MWRITE_32((uint8_t *)p + 8, 0, 24, v)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_KEY_3_READ(r, p)                     MREAD_32((uint8_t *)p + 12, r)
+#define RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_KEY_3_WRITE(v, p)                    MWRITE_32((uint8_t *)p + 12, v)
+#if defined DSL_63138
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS )
+
+#endif
+#define RDD_PM_COUNTERS_RESERVED_FW_ONLY_NUMBER	1552
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_PM_COUNTERS_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PM_COUNTERS_DTS;
+
+#if defined DSL_63138
+
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE     128
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_DTS;
+
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_PTR()	( RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RATE_SHAPERS_STATUS_DESCRIPTOR_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	current_timeout            	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	current_packet_count       	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	configured_timeout         	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	configured_max_packet_count	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INTERRUPT_COALESCING_CONFIG_DTS;
+
+#define RDD_INTERRUPT_COALESCING_CONFIG_CURRENT_TIMEOUT_READ(r, p)                             FIELD_MREAD_16((uint8_t *)p, 6, 10, r)
+#define RDD_INTERRUPT_COALESCING_CONFIG_CURRENT_TIMEOUT_WRITE(v, p)                            FIELD_MWRITE_16((uint8_t *)p, 6, 10, v)
+#define RDD_INTERRUPT_COALESCING_CONFIG_CURRENT_PACKET_COUNT_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 1, 0, 6, r)
+#define RDD_INTERRUPT_COALESCING_CONFIG_CURRENT_PACKET_COUNT_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 1, 0, 6, v)
+#define RDD_INTERRUPT_COALESCING_CONFIG_CONFIGURED_TIMEOUT_READ(r, p)                          FIELD_MREAD_16((uint8_t *)p + 2, 6, 10, r)
+#define RDD_INTERRUPT_COALESCING_CONFIG_CONFIGURED_TIMEOUT_WRITE(v, p)                         FIELD_MWRITE_16((uint8_t *)p + 2, 6, 10, v)
+#define RDD_INTERRUPT_COALESCING_CONFIG_CONFIGURED_MAX_PACKET_COUNT_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 3, 0, 6, r)
+#define RDD_INTERRUPT_COALESCING_CONFIG_CONFIGURED_MAX_PACKET_COUNT_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 3, 0, 6, v)
+#if defined DSL_63138
+
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INTERRUPT_COALESCING_CONFIG_DTS	entry[ RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INTERRUPT_COALESCING_CONFIG_TABLE_DTS;
+
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_PTR()	( RDD_INTERRUPT_COALESCING_CONFIG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + INTERRUPT_COALESCING_CONFIG_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	flow_id                 	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_chksum_verified      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	source_bridge_port      	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length           	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_offset_flag     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reason                  	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dest_ssid               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2               	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_exception            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	descriptor_type         	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ownership               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	host_data_buffer_pointer	:31	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved4               	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_sync_1588_entry_index	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wl_metadata             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_DESCRIPTOR_DTS;
+
+#define RDD_CPU_RX_DESCRIPTOR_FLOW_ID_READ(r, p)                                  FIELD_MREAD_16((uint8_t *)p, 4, 12, r)
+#define RDD_CPU_RX_DESCRIPTOR_FLOW_ID_WRITE(v, p)                                 FIELD_MWRITE_16((uint8_t *)p, 4, 12, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 1, 3, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 1, 3, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_SOURCE_BRIDGE_PORT_READ(r, p)                       FIELD_MREAD_32((uint8_t *)p + 0, 14, 5, r)
+#define RDD_CPU_RX_DESCRIPTOR_SOURCE_BRIDGE_PORT_WRITE(v, p)                      FIELD_MWRITE_32((uint8_t *)p + 0, 14, 5, v)
+#define RDD_CPU_RX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                            FIELD_MREAD_16((uint8_t *)p + 2, 0, 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                           FIELD_MWRITE_16((uint8_t *)p + 2, 0, 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_PAYLOAD_OFFSET_FLAG_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_PAYLOAD_OFFSET_FLAG_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_REASON_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 4, 1, 6, r)
+#define RDD_CPU_RX_DESCRIPTOR_REASON_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 4, 1, 6, v)
+#define RDD_CPU_RX_DESCRIPTOR_DEST_SSID_READ(r, p)                                FIELD_MREAD_32((uint8_t *)p + 4, 9, 16, r)
+#define RDD_CPU_RX_DESCRIPTOR_DEST_SSID_WRITE(v, p)                               FIELD_MWRITE_32((uint8_t *)p + 4, 9, 16, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_EXCEPTION_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 7, 4, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_EXCEPTION_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 7, 4, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_DESCRIPTOR_TYPE_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 7, 0, 4, r)
+#define RDD_CPU_RX_DESCRIPTOR_DESCRIPTOR_TYPE_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 7, 0, 4, v)
+#define RDD_CPU_RX_DESCRIPTOR_OWNERSHIP_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_OWNERSHIP_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_HOST_DATA_BUFFER_POINTER_READ(r, p)                 FIELD_MREAD_32((uint8_t *)p + 8, 0, 31, r)
+#define RDD_CPU_RX_DESCRIPTOR_HOST_DATA_BUFFER_POINTER_WRITE(v, p)                FIELD_MWRITE_32((uint8_t *)p + 8, 0, 31, v)
+#define RDD_CPU_RX_DESCRIPTOR_IP_SYNC_1588_ENTRY_INDEX_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 13, 0, 4, r)
+#define RDD_CPU_RX_DESCRIPTOR_IP_SYNC_1588_ENTRY_INDEX_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 13, 0, 4, v)
+#define RDD_CPU_RX_DESCRIPTOR_WL_METADATA_READ(r, p)                              MREAD_16((uint8_t *)p + 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_WL_METADATA_WRITE(v, p)                             MWRITE_16((uint8_t *)p + 14, v)
+#if defined DSL_63138
+
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+typedef struct
+{
+	RDD_CPU_RX_DESCRIPTOR_DTS	entry[ RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_DTS;
+
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_PTR()	( RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2    4
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_DS_CONNECTION_BUFFER_TABLE_SIZE ][ RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_BUFFER_TABLE_DTS;
+
+#define RDD_DS_CONNECTION_BUFFER_TABLE_PTR()	( RDD_DS_CONNECTION_BUFFER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_CONNECTION_BUFFER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_MAC_CONTEXT_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_CONTEXT_ENTRY_DTS	entry[ RDD_MAC_CONTEXT_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_CONTEXT_TABLE_CAM_DTS;
+
+#define RDD_MAC_CONTEXT_TABLE_CAM_PTR()	( RDD_MAC_CONTEXT_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_CONTEXT_TABLE_CAM_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_DOORBELL_WRITE_VALUES_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DHD_DOORBELL_WRITE_VALUES_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_DOORBELL_WRITE_VALUES_DTS;
+
+#define RDD_DHD_DOORBELL_WRITE_VALUES_PTR()	( RDD_DHD_DOORBELL_WRITE_VALUES_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_DOORBELL_WRITE_VALUES_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_BACKUP_INDEX_CACHE_DTS;
+
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_PTR()	( RDD_DS_DHD_BACKUP_INDEX_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_DHD_BACKUP_INDEX_CACHE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	size      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	addr      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DDR_QUEUE_ADDRESS_ENTRY_DTS;
+
+#define RDD_DDR_QUEUE_ADDRESS_ENTRY_SIZE_READ(r, p)                      MREAD_16((uint8_t *)p, r)
+#define RDD_DDR_QUEUE_ADDRESS_ENTRY_SIZE_WRITE(v, p)                     MWRITE_16((uint8_t *)p, v)
+#define RDD_DDR_QUEUE_ADDRESS_ENTRY_ADDR_READ(r, p)                      MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DDR_QUEUE_ADDRESS_ENTRY_ADDR_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 4, v)
+#if defined DSL_63138
+
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DDR_QUEUE_ADDRESS_ENTRY_DTS	entry[ RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_PTR()	( RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved0        	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	entries_counter  	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	size_of_entry    	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	number_of_entries	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ring_pointer     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	interrupt_id     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	drop_counter     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RING_DESCRIPTOR_DTS;
+
+#define RDD_RING_DESCRIPTOR_ENTRIES_COUNTER_READ(r, p)                   FIELD_MREAD_16((uint8_t *)p, 0, 11, r)
+#define RDD_RING_DESCRIPTOR_ENTRIES_COUNTER_WRITE(v, p)                  FIELD_MWRITE_16((uint8_t *)p, 0, 11, v)
+#define RDD_RING_DESCRIPTOR_SIZE_OF_ENTRY_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 2, 3, 5, r)
+#define RDD_RING_DESCRIPTOR_SIZE_OF_ENTRY_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 2, 3, 5, v)
+#define RDD_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 2, 0, 11, r)
+#define RDD_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 2, 0, 11, v)
+#define RDD_RING_DESCRIPTOR_RING_POINTER_READ(r, p)                      MREAD_32((uint8_t *)p + 4, r)
+#define RDD_RING_DESCRIPTOR_RING_POINTER_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_RING_DESCRIPTOR_INTERRUPT_ID_READ(r, p)                      MREAD_16((uint8_t *)p + 8, r)
+#define RDD_RING_DESCRIPTOR_INTERRUPT_ID_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_RING_DESCRIPTOR_DROP_COUNTER_READ(r, p)                      MREAD_16((uint8_t *)p + 10, r)
+#define RDD_RING_DESCRIPTOR_DROP_COUNTER_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 10, v)
+#if defined DSL_63138
+
+#define RDD_RING_DESCRIPTORS_TABLE_SIZE     16
+typedef struct
+{
+	RDD_RING_DESCRIPTOR_DTS	entry[ RDD_RING_DESCRIPTORS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RING_DESCRIPTORS_TABLE_DTS;
+
+#define RDD_RING_DESCRIPTORS_TABLE_PTR()	( RDD_RING_DESCRIPTORS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RING_DESCRIPTORS_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint8_t	extension_entry	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_EXTENSION_ENTRY_DTS;
+
+#define RDD_MAC_EXTENSION_ENTRY_EXTENSION_ENTRY_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_MAC_EXTENSION_ENTRY_EXTENSION_ENTRY_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+#if defined DSL_63138
+
+#define RDD_MAC_EXTENSION_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_EXTENSION_ENTRY_DTS	entry[ RDD_MAC_EXTENSION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_EXTENSION_TABLE_DTS;
+
+#define RDD_MAC_EXTENSION_TABLE_PTR()	( RDD_MAC_EXTENSION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_EXTENSION_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE     16
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_DTS;
+
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_PTR()	( RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	flow_ring_base_low    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_base_high   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	size                  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_for_lock_flag	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ssid                  	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flags                 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	backup_first_index    	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	backup_last_index     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	backup_num_entries    	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	phy_size              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_DTS;
+
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLOW_RING_BASE_LOW_READ(r, p)                     MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLOW_RING_BASE_LOW_WRITE(v, p)                    MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLOW_RING_BASE_LOW_L_READ( wv )                   FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLOW_RING_BASE_LOW_L_WRITE( v, wv )               FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLOW_RING_BASE_HIGH_READ(r, p)                    MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLOW_RING_BASE_HIGH_WRITE(v, p)                   MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLOW_RING_BASE_HIGH_L_READ( wv )                  FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLOW_RING_BASE_HIGH_L_WRITE( v, wv )              FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_SIZE_READ(r, p)                                   MREAD_16((uint8_t *)p + 8, r)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_SIZE_WRITE(v, p)                                  MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_SIZE_L_READ( wv )                                 FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_SIZE_L_WRITE( v, wv )                             FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_SSID_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 10, 0, 5, r)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_SSID_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 10, 0, 5, v)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_SSID_L_READ( wv )                                 FIELD_GET( wv, 8, 5 )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_SSID_L_WRITE( v, wv )                             FIELD_SET( v, 8, 5, wv )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLAGS_READ(r, p)                                  MREAD_8((uint8_t *)p + 11, r)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLAGS_WRITE(v, p)                                 MWRITE_8((uint8_t *)p + 11, v)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLAGS_L_READ( wv )                                FIELD_GET( wv, 0, 8 )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_FLAGS_L_WRITE( v, wv )                            FIELD_SET( v, 0, 8, wv )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_FIRST_INDEX_READ(r, p)                     MREAD_16((uint8_t *)p + 12, r)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_FIRST_INDEX_WRITE(v, p)                    MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_FIRST_INDEX_L_READ( wv )                   FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_FIRST_INDEX_L_WRITE( v, wv )               FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_LAST_INDEX_READ(r, p)                      MREAD_16((uint8_t *)p + 14, r)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_LAST_INDEX_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_LAST_INDEX_L_READ( wv )                    FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_LAST_INDEX_L_WRITE( v, wv )                FIELD_SET( v, 0, 16, wv )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_NUM_ENTRIES_READ(r, p)                     MREAD_16((uint8_t *)p + 16, r)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_NUM_ENTRIES_WRITE(v, p)                    MWRITE_16((uint8_t *)p + 16, v)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_NUM_ENTRIES_L_READ( wv )                   FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BACKUP_NUM_ENTRIES_L_WRITE( v, wv )               FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_PHY_SIZE_READ(r, p)                               MREAD_16((uint8_t *)p + 18, r)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_PHY_SIZE_WRITE(v, p)                              MWRITE_16((uint8_t *)p + 18, v)
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_PHY_SIZE_L_READ( wv )                             FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_PHY_SIZE_L_WRITE( v, wv )                         FIELD_SET( v, 0, 16, wv )
+
+typedef struct
+{
+	uint32_t	sustain_scheduling_mode  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_scheduling_mode     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	overall_rate_limiter_mode	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved                 	:13	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_ffi_offset          	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	sustain_ffi_offset       	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	service_queues_status    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_limiter_status      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	sustain_vector           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_vector              	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_CFG_ENTRY_DTS;
+
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_SUSTAIN_SCHEDULING_MODE_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_SUSTAIN_SCHEDULING_MODE_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_PEAK_SCHEDULING_MODE_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p, 6, 1, r)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_PEAK_SCHEDULING_MODE_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p, 6, 1, v)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_OVERALL_RATE_LIMITER_MODE_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 5, 1, r)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_OVERALL_RATE_LIMITER_MODE_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 5, 1, v)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_PEAK_FFI_OFFSET_READ(r, p)                           MREAD_8((uint8_t *)p + 2, r)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_PEAK_FFI_OFFSET_WRITE(v, p)                          MWRITE_8((uint8_t *)p + 2, v)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_SUSTAIN_FFI_OFFSET_READ(r, p)                        MREAD_8((uint8_t *)p + 3, r)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_SUSTAIN_FFI_OFFSET_WRITE(v, p)                       MWRITE_8((uint8_t *)p + 3, v)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_SERVICE_QUEUES_STATUS_READ(r, p)                     MREAD_32((uint8_t *)p + 4, r)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_SERVICE_QUEUES_STATUS_WRITE(v, p)                    MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_RATE_LIMITER_STATUS_READ(r, p)                       MREAD_32((uint8_t *)p + 8, r)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_RATE_LIMITER_STATUS_WRITE(v, p)                      MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_SUSTAIN_VECTOR_READ(r, p)                            MREAD_32((uint8_t *)p + 12, r)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_SUSTAIN_VECTOR_WRITE(v, p)                           MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_PEAK_VECTOR_READ(r, p)                               MREAD_32((uint8_t *)p + 16, r)
+#define RDD_SERVICE_QUEUES_CFG_ENTRY_PEAK_VECTOR_WRITE(v, p)                              MWRITE_32((uint8_t *)p + 16, v)
+
+typedef struct
+{
+	uint32_t	read_idx  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	write_idx 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_POST_REQUEST_QUEUE_IDX_ENTRY_DTS;
+
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_IDX_ENTRY_READ_IDX_READ(r, p)                  MREAD_16((uint8_t *)p, r)
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_IDX_ENTRY_READ_IDX_WRITE(v, p)                 MWRITE_16((uint8_t *)p, v)
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_IDX_ENTRY_READ_IDX_L_READ( wv )                FIELD_GET( wv, 16, 16 )
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_IDX_ENTRY_READ_IDX_L_WRITE( v, wv )            FIELD_SET( v, 16, 16, wv )
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_IDX_ENTRY_WRITE_IDX_READ(r, p)                 MREAD_16((uint8_t *)p + 2, r)
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_IDX_ENTRY_WRITE_IDX_WRITE(v, p)                MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_IDX_ENTRY_WRITE_IDX_L_READ( wv )               FIELD_GET( wv, 0, 16 )
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_IDX_ENTRY_WRITE_IDX_L_WRITE( v, wv )           FIELD_SET( v, 0, 16, wv )
+#if defined DSL_63138
+
+#define RDD_MAC_EXTENSION_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_EXTENSION_ENTRY_DTS	entry[ RDD_MAC_EXTENSION_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_EXTENSION_TABLE_CAM_DTS;
+
+#define RDD_MAC_EXTENSION_TABLE_CAM_PTR()	( RDD_MAC_EXTENSION_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_EXTENSION_TABLE_CAM_ADDRESS )
+
+#endif
+#define RDD_PM_COUNTERS_BUFFER_RESERVED_FW_ONLY_NUMBER	8
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_PM_COUNTERS_BUFFER_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PM_COUNTERS_BUFFER_DTS;
+
+#if defined DSL_63138
+
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE     3
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TX_CPL_DHD_DMA_SCRATCH_DTS;
+
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_PTR()	( RDD_TX_CPL_DHD_DMA_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + TX_CPL_DHD_DMA_SCRATCH_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_SIZE     3
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_TX_POST_BUFFERS_THRESHOLD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_BUFFERS_THRESHOLD_DTS;
+
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_PTR()	( RDD_DHD_TX_POST_BUFFERS_THRESHOLD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_TX_POST_BUFFERS_THRESHOLD_ADDRESS )
+
+#endif
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_PTR()	( RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS )
+
+#if defined DSL_63138
+
+#define RDD_MAIN_A_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_MAIN_A_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAIN_A_DEBUG_TRACE_DTS;
+
+#define RDD_MAIN_A_DEBUG_TRACE_PTR()	( RDD_MAIN_A_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAIN_A_DEBUG_TRACE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_PICO_A_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_PICO_A_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PICO_A_DEBUG_TRACE_DTS;
+
+#define RDD_PICO_A_DEBUG_TRACE_PTR()	( RDD_PICO_A_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + PICO_A_DEBUG_TRACE_ADDRESS )
+
+#endif
+/* COMMON_B */
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_WAN_TX_MIRROR_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_WAN_TX_MIRROR_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_MIRROR_SCRATCHPAD_DTS;
+
+#define RDD_WAN_TX_MIRROR_SCRATCHPAD_PTR()	( RDD_WAN_TX_MIRROR_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_TX_MIRROR_SCRATCHPAD_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+typedef struct
+{
+	RDD_BYTES_2_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS - 0x8000 )
+
+#endif
+
+typedef struct
+{
+	uint32_t	context        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0      	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1      	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pbits          	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	no_outer       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vlan           	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	gem_flow_extend	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aging          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	skip           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_CONTEXT_READ(r, p)                         MREAD_8((uint8_t *)p, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_CONTEXT_WRITE(v, p)                        MWRITE_8((uint8_t *)p, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_PBITS_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 4, 1, 3, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_PBITS_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 4, 1, 3, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_NO_OUTER_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 4, 0, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_NO_OUTER_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 4, 0, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_VLAN_READ(r, p)                            FIELD_MREAD_32((uint8_t *)p + 4, 12, 12, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_VLAN_WRITE(v, p)                           FIELD_MWRITE_32((uint8_t *)p + 4, 12, 12, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_GEM_FLOW_EXTEND_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 6, 4, 8, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_GEM_FLOW_EXTEND_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 6, 4, 8, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_AGING_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 7, 2, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_AGING_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 7, 2, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_SKIP_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 7, 1, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_SKIP_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 7, 1, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_VALID_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 7, 0, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_VALID_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 7, 0, 1, v)
+
+typedef struct
+{
+	uint32_t	context        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0      	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1      	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pbits          	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	no_outer       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vlan           	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_port_extend	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aging          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	skip           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_CONTEXT_READ(r, p)                         MREAD_8((uint8_t *)p, r)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_CONTEXT_WRITE(v, p)                        MWRITE_8((uint8_t *)p, v)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_PBITS_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 4, 1, 3, r)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_PBITS_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 4, 1, 3, v)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_NO_OUTER_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 4, 0, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_NO_OUTER_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 4, 0, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_VLAN_READ(r, p)                            FIELD_MREAD_32((uint8_t *)p + 4, 12, 12, r)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_VLAN_WRITE(v, p)                           FIELD_MWRITE_32((uint8_t *)p + 4, 12, 12, v)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_SRC_PORT_EXTEND_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 6, 4, 5, r)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_SRC_PORT_EXTEND_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 6, 4, 5, v)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_AGING_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 7, 2, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_AGING_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 7, 2, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_SKIP_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 7, 1, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_SKIP_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 7, 1, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_VALID_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 7, 0, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_VALID_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 7, 0, 1, v)
+
+typedef struct
+{
+	uint32_t	context    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_index  	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	gem_flow   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inner_pbits	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	no_inner   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inner_vlan 	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_pbits	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	no_outer   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_vlan 	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aging      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	skip       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_CONTEXT_READ(r, p)                     MREAD_8((uint8_t *)p, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_CONTEXT_WRITE(v, p)                    MWRITE_8((uint8_t *)p, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_KEY_INDEX_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 1, 4, 4, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_KEY_INDEX_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 1, 4, 4, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_GEM_FLOW_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 2, 4, 8, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_GEM_FLOW_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 2, 4, 8, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_INNER_PBITS_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 3, 1, 3, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_INNER_PBITS_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 3, 1, 3, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_NO_INNER_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 3, 0, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_NO_INNER_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 3, 0, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_INNER_VLAN_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p + 4, 4, 12, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_INNER_VLAN_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p + 4, 4, 12, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_OUTER_PBITS_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 5, 1, 3, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_OUTER_PBITS_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 5, 1, 3, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_NO_OUTER_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 5, 0, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_NO_OUTER_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 5, 0, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_OUTER_VLAN_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p + 6, 4, 12, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_OUTER_VLAN_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p + 6, 4, 12, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_AGING_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 7, 2, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_AGING_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 7, 2, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_SKIP_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 7, 1, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_SKIP_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 7, 1, 1, v)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_VALID_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 7, 0, 1, r)
+#define RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_VALID_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 7, 0, 1, v)
+
+typedef struct
+{
+	uint32_t	context        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_index      	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0      	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ssid           	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_bridge_port	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inner_pbits    	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	no_inner       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inner_vlan     	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_pbits    	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	no_outer       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_vlan     	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aging          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	skip           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_CONTEXT_READ(r, p)                         MREAD_8((uint8_t *)p, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_CONTEXT_WRITE(v, p)                        MWRITE_8((uint8_t *)p, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_KEY_INDEX_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 1, 4, 4, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_KEY_INDEX_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 1, 4, 4, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_SSID_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 2, 4, 4, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_SSID_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 2, 4, 4, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_SRC_BRIDGE_PORT_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 2, 4, 8, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_SRC_BRIDGE_PORT_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 2, 4, 8, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_INNER_PBITS_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 3, 1, 3, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_INNER_PBITS_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 3, 1, 3, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_NO_INNER_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 3, 0, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_NO_INNER_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 3, 0, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_INNER_VLAN_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 4, 4, 12, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_INNER_VLAN_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 4, 4, 12, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_OUTER_PBITS_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 5, 1, 3, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_OUTER_PBITS_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 5, 1, 3, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_NO_OUTER_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 5, 0, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_NO_OUTER_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 5, 0, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_OUTER_VLAN_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 6, 4, 12, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_OUTER_VLAN_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 6, 4, 12, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_AGING_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 7, 2, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_AGING_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 7, 2, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_SKIP_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 7, 1, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_SKIP_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 7, 1, 1, v)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_VALID_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 7, 0, 1, r)
+#define RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_VALID_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 7, 0, 1, v)
+
+typedef struct
+{
+	uint32_t	context   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_index 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_0     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_1     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aging     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	skip      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_DTS;
+
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_CONTEXT_READ(r, p)                   MREAD_8((uint8_t *)p, r)
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_CONTEXT_WRITE(v, p)                  MWRITE_8((uint8_t *)p, v)
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_KEY_INDEX_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 1, 4, 4, r)
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_KEY_INDEX_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 1, 4, 4, v)
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_KEY_0_READ(r, p)                     FIELD_MREAD_32((uint8_t *)p + 0, 4, 16, r)
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_KEY_0_WRITE(v, p)                    FIELD_MWRITE_32((uint8_t *)p + 0, 4, 16, v)
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_KEY_1_READ(r, p)                     { uint32_t temp; FIELD_MREAD_32((uint8_t *)p, 0, 4, temp); r = temp << 28; FIELD_MREAD_32(((uint8_t *)p + 4), 4, 28, temp); r = r | temp; }
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_KEY_1_WRITE(v, p)                    { FIELD_MWRITE_32((uint8_t *)p, 0, 4, ((v & 0xf0000000) >> 28)); FIELD_MWRITE_32(((uint8_t *)p + 4), 4, 28, (v & 0x0fffffff)); }
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_AGING_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 7, 2, 1, r)
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_AGING_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 7, 2, 1, v)
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_SKIP_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 7, 1, 1, r)
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_SKIP_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 7, 1, 1, v)
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_VALID_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 7, 0, 1, r)
+#define RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_VALID_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 7, 0, 1, v)
+
+typedef struct
+{
+	uint32_t	head_ptr           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tail_ptr           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_counter     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	index              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved           	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	use_as_scheduler   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	scheduler_index    	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_threshold   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	profile_ptr        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	queue_mask         	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	total_pkt_counter  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	svc_queue_sched_ptr	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_DTS;
+
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_HEAD_PTR_READ(r, p)                            MREAD_16((uint8_t *)p, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_HEAD_PTR_WRITE(v, p)                           MWRITE_16((uint8_t *)p, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_TAIL_PTR_READ(r, p)                            MREAD_16((uint8_t *)p + 2, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_TAIL_PTR_WRITE(v, p)                           MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_PACKET_COUNTER_READ(r, p)                      MREAD_16((uint8_t *)p + 4, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_PACKET_COUNTER_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_INDEX_READ(r, p)                               MREAD_8((uint8_t *)p + 6, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_INDEX_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 6, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_USE_AS_SCHEDULER_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 7, 3, 1, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_USE_AS_SCHEDULER_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 7, 3, 1, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_SCHEDULER_INDEX_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 7, 0, 3, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_SCHEDULER_INDEX_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 7, 0, 3, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_PACKET_THRESHOLD_READ(r, p)                    MREAD_16((uint8_t *)p + 8, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_PACKET_THRESHOLD_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_PROFILE_PTR_READ(r, p)                         MREAD_16((uint8_t *)p + 10, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_PROFILE_PTR_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_QUEUE_MASK_READ(r, p)                          MREAD_32((uint8_t *)p + 12, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_QUEUE_MASK_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_TOTAL_PKT_COUNTER_READ(r, p)                   MREAD_32((uint8_t *)p + 16, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_TOTAL_PKT_COUNTER_WRITE(v, p)                  MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_SVC_QUEUE_SCHED_PTR_READ(r, p)                 MREAD_16((uint8_t *)p + 20, r)
+#define RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_SVC_QUEUE_SCHED_PTR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 20, v)
+#if defined DSL_63138
+
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SERVICE_QUEUES_TABLE_DTS;
+
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_PTR()	( RDD_WAN_TX_SERVICE_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_TX_SERVICE_QUEUES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE2    4
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_US_CONNECTION_BUFFER_TABLE_SIZE ][ RDD_US_CONNECTION_BUFFER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_BUFFER_TABLE_DTS;
+
+#define RDD_US_CONNECTION_BUFFER_TABLE_PTR()	( RDD_US_CONNECTION_BUFFER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_CONNECTION_BUFFER_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPV6_HOST_ADDRESS_CRC_TABLE_DTS;
+
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_PTR()	( RDD_IPV6_HOST_ADDRESS_CRC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + IPV6_HOST_ADDRESS_CRC_TABLE_ADDRESS - 0x8000 )
+
+#endif
+
+typedef struct
+{
+	uint32_t	backup_first_index	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	backup_last_index 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	backup_num_entries	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	phy_size          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_BACKUP_INFO_CACHE_ENTRY_DTS;
+
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_FIRST_INDEX_READ(r, p)                 MREAD_16((uint8_t *)p, r)
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_FIRST_INDEX_WRITE(v, p)                MWRITE_16((uint8_t *)p, v)
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_FIRST_INDEX_L_READ( wv )               FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_FIRST_INDEX_L_WRITE( v, wv )           FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_LAST_INDEX_READ(r, p)                  MREAD_16((uint8_t *)p + 2, r)
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_LAST_INDEX_WRITE(v, p)                 MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_LAST_INDEX_L_READ( wv )                FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_LAST_INDEX_L_WRITE( v, wv )            FIELD_SET( v, 0, 16, wv )
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_NUM_ENTRIES_READ(r, p)                 MREAD_16((uint8_t *)p + 4, r)
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_NUM_ENTRIES_WRITE(v, p)                MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_NUM_ENTRIES_L_READ( wv )               FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_BACKUP_NUM_ENTRIES_L_WRITE( v, wv )           FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_PHY_SIZE_READ(r, p)                           MREAD_16((uint8_t *)p + 6, r)
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_PHY_SIZE_WRITE(v, p)                          MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_PHY_SIZE_L_READ( wv )                         FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_BACKUP_INFO_CACHE_ENTRY_PHY_SIZE_L_WRITE( v, wv )                     FIELD_SET( v, 0, 16, wv )
+#if defined DSL_63138
+
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_BACKUP_INFO_CACHE_ENTRY_DTS	entry[ RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_BACKUP_INFO_CACHE_TABLE_DTS;
+
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_PTR()	( RDD_DHD_BACKUP_INFO_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_BACKUP_INFO_CACHE_TABLE_ADDRESS - 0x8000 )
+
+#endif
+
+typedef struct
+{
+	uint32_t	head_ptr           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tail_ptr           	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_counter     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	index              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved           	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	use_as_scheduler   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	scheduler_index    	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_threshold   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	profile_ptr        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_controller_ptr	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	queue_mask         	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_QUEUE_DESCRIPTOR_DTS;
+
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_HEAD_PTR_READ(r, p)                            MREAD_16((uint8_t *)p, r)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_HEAD_PTR_WRITE(v, p)                           MWRITE_16((uint8_t *)p, v)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_TAIL_PTR_READ(r, p)                            MREAD_16((uint8_t *)p + 2, r)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_TAIL_PTR_WRITE(v, p)                           MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_PACKET_COUNTER_READ(r, p)                      MREAD_16((uint8_t *)p + 4, r)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_PACKET_COUNTER_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_INDEX_READ(r, p)                               MREAD_8((uint8_t *)p + 6, r)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_INDEX_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 6, v)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_USE_AS_SCHEDULER_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 7, 3, 1, r)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_USE_AS_SCHEDULER_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 7, 3, 1, v)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_SCHEDULER_INDEX_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 7, 0, 3, r)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_SCHEDULER_INDEX_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 7, 0, 3, v)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_PACKET_THRESHOLD_READ(r, p)                    MREAD_16((uint8_t *)p + 8, r)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_PACKET_THRESHOLD_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_PROFILE_PTR_READ(r, p)                         MREAD_16((uint8_t *)p + 10, r)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_PROFILE_PTR_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_RATE_CONTROLLER_PTR_READ(r, p)                 MREAD_16((uint8_t *)p + 12, r)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_RATE_CONTROLLER_PTR_WRITE(v, p)                MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_QUEUE_MASK_READ(r, p)                          MREAD_16((uint8_t *)p + 14, r)
+#define RDD_WAN_TX_QUEUE_DESCRIPTOR_QUEUE_MASK_WRITE(v, p)                         MWRITE_16((uint8_t *)p + 14, v)
+#if defined DSL_63138
+
+#define RDD_WAN_TX_QUEUES_TABLE_SIZE     256
+typedef struct
+{
+	RDD_WAN_TX_QUEUE_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_QUEUES_TABLE_DTS;
+
+#define RDD_WAN_TX_QUEUES_TABLE_PTR()	( RDD_WAN_TX_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_TX_QUEUES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_PTR()	( RDD_RUNNER_FWTRACE_MAINB_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_MAINB_BASE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+typedef struct
+{
+	RDD_CPU_RX_DESCRIPTOR_DTS	entry[ RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RING_PACKET_DESCRIPTORS_CACHE_DTS;
+
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_PTR()	( RDD_US_RING_PACKET_DESCRIPTORS_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS - 0x8000 )
+
+#endif
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_THRESHOLDS_NUMBER	4
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_TIMEOUTS_NUMBER	4
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_TIMEOUT_CNTRS_NUMBER	4
+
+typedef struct
+{
+	uint32_t	us_dhd_doorbell_post                                                                                              	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	us_dhd_doorbell_complete                                                                                          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	r2d_wr_fr_desc_base_ptr                                                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	d2r_rd_fr_desc_base_ptr                                                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	r2d_rd_fr_desc_base_ptr                                                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	d2r_wr_fr_desc_base_ptr                                                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rx_post_fr_base_ptr                                                                                               	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_complete_fr_base_ptr                                                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rx_complete_fr_base_ptr                                                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_post_mgmt_fr_base_ptr                                                                                          	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rx_post_r2d_index                                                                                                 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	us_rd_fr_r2d_indexes                                                                                              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	us_wr_fr_r2d_indexes                                                                                              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rx_rd_fr_d2r_indexes                                                                                              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rx_wr_fr_d2r_indexes                                                                                              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	add_llcsnap_header                                                                                                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aggregation_bypass_cpu_tx                                                                                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aggregation_bypass_non_udp_tcp                                                                                    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                                                                                                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	idma_active                                                                                                       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_format                                                                                                  	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aggregation_bypass_tcp_pktlen                                                                                     	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	per_ac_aggregation_thresholds[RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_THRESHOLDS_NUMBER];
+	uint8_t	per_ac_aggregation_timeouts[RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_TIMEOUTS_NUMBER];
+	uint8_t	per_ac_aggregation_timeout_cntrs[RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_TIMEOUT_CNTRS_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_DTS;
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_US_DHD_DOORBELL_POST_READ(r, p)                             MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_US_DHD_DOORBELL_POST_WRITE(v, p)                            MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_US_DHD_DOORBELL_COMPLETE_READ(r, p)                         MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_US_DHD_DOORBELL_COMPLETE_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_R2D_WR_FR_DESC_BASE_PTR_READ(r, p)                          MREAD_32((uint8_t *)p + 8, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_R2D_WR_FR_DESC_BASE_PTR_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_D2R_RD_FR_DESC_BASE_PTR_READ(r, p)                          MREAD_32((uint8_t *)p + 12, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_D2R_RD_FR_DESC_BASE_PTR_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_R2D_RD_FR_DESC_BASE_PTR_READ(r, p)                          MREAD_32((uint8_t *)p + 16, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_R2D_RD_FR_DESC_BASE_PTR_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_D2R_WR_FR_DESC_BASE_PTR_READ(r, p)                          MREAD_32((uint8_t *)p + 20, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_D2R_WR_FR_DESC_BASE_PTR_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 20, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_RX_POST_FR_BASE_PTR_READ(r, p)                              MREAD_32((uint8_t *)p + 24, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_RX_POST_FR_BASE_PTR_WRITE(v, p)                             MWRITE_32((uint8_t *)p + 24, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_TX_COMPLETE_FR_BASE_PTR_READ(r, p)                          MREAD_32((uint8_t *)p + 28, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_TX_COMPLETE_FR_BASE_PTR_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 28, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_RX_COMPLETE_FR_BASE_PTR_READ(r, p)                          MREAD_32((uint8_t *)p + 32, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_RX_COMPLETE_FR_BASE_PTR_WRITE(v, p)                         MWRITE_32((uint8_t *)p + 32, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_TX_POST_MGMT_FR_BASE_PTR_READ(r, p)                         MREAD_32((uint8_t *)p + 36, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_TX_POST_MGMT_FR_BASE_PTR_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 36, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_RX_POST_R2D_INDEX_READ(r, p)                                MREAD_16((uint8_t *)p + 40, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_RX_POST_R2D_INDEX_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 40, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_US_RD_FR_R2D_INDEXES_READ(r, p)                             MREAD_16((uint8_t *)p + 42, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_US_RD_FR_R2D_INDEXES_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 42, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_US_WR_FR_R2D_INDEXES_READ(r, p)                             MREAD_16((uint8_t *)p + 44, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_US_WR_FR_R2D_INDEXES_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 44, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_RX_RD_FR_D2R_INDEXES_READ(r, p)                             MREAD_16((uint8_t *)p + 46, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_RX_RD_FR_D2R_INDEXES_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 46, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_RX_WR_FR_D2R_INDEXES_READ(r, p)                             MREAD_16((uint8_t *)p + 48, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_RX_WR_FR_D2R_INDEXES_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 48, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_ADD_LLCSNAP_HEADER_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 50, 7, 1, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_ADD_LLCSNAP_HEADER_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 50, 7, 1, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_AGGREGATION_BYPASS_CPU_TX_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 50, 6, 1, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_AGGREGATION_BYPASS_CPU_TX_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 50, 6, 1, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_AGGREGATION_BYPASS_NON_UDP_TCP_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 50, 5, 1, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_AGGREGATION_BYPASS_NON_UDP_TCP_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 50, 5, 1, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_IDMA_ACTIVE_READ(r, p)                                      FIELD_MREAD_8((uint8_t *)p + 50, 3, 1, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_IDMA_ACTIVE_WRITE(v, p)                                     FIELD_MWRITE_8((uint8_t *)p + 50, 3, 1, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_FLOW_RING_FORMAT_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 50, 0, 3, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_FLOW_RING_FORMAT_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 50, 0, 3, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_AGGREGATION_BYPASS_TCP_PKTLEN_READ(r, p)                    MREAD_8((uint8_t *)p + 51, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_AGGREGATION_BYPASS_TCP_PKTLEN_WRITE(v, p)                   MWRITE_8((uint8_t *)p + 51, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_THRESHOLDS_READ(r, p, i)                 MREAD_I_8((uint8_t *)p + 52, i, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_THRESHOLDS_WRITE(v, p, i)                MWRITE_I_8((uint8_t *)p + 52, i, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_TIMEOUTS_READ(r, p, i)                   MREAD_I_8((uint8_t *)p + 56, i, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_TIMEOUTS_WRITE(v, p, i)                  MWRITE_I_8((uint8_t *)p + 56, i, v)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_TIMEOUT_CNTRS_READ(r, p, i)              MREAD_I_8((uint8_t *)p + 60, i, r)
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_PER_AC_AGGREGATION_TIMEOUT_CNTRS_WRITE(v, p, i)             MWRITE_I_8((uint8_t *)p + 60, i, v)
+#if defined DSL_63138
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE     3
+typedef struct
+{
+	RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_DTS	entry[ RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_DTS;
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_PTR()	( RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_RADIO_INSTANCE_COMMON_B_DATA_ADDRESS - 0x8000 )
+
+#endif
+#define RDD_DUMMY_RATE_CONTROLLER_DESCRIPTOR_RESERVED_FW_ONLY_NUMBER	16
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_DUMMY_RATE_CONTROLLER_DESCRIPTOR_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DUMMY_RATE_CONTROLLER_DESCRIPTOR_DTS;
+
+
+typedef struct
+{
+	uint32_t	flow_ring_base_low 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_base_high	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	size               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	lock               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved           	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ssid               	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flags              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rd_idx             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wr_idx             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_DTS;
+
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLOW_RING_BASE_LOW_READ(r, p)                  MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLOW_RING_BASE_LOW_WRITE(v, p)                 MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLOW_RING_BASE_LOW_L_READ( wv )                FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLOW_RING_BASE_LOW_L_WRITE( v, wv )            FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLOW_RING_BASE_HIGH_READ(r, p)                 MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLOW_RING_BASE_HIGH_WRITE(v, p)                MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLOW_RING_BASE_HIGH_L_READ( wv )               FIELD_GET( wv, 0, 32 )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLOW_RING_BASE_HIGH_L_WRITE( v, wv )           FIELD_SET( v, 0, 32, wv )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_SIZE_READ(r, p)                                MREAD_16((uint8_t *)p + 8, r)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_SIZE_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_SIZE_L_READ( wv )                              FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_SIZE_L_WRITE( v, wv )                          FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_LOCK_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 10, 7, 1, r)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_LOCK_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 10, 7, 1, v)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_LOCK_L_READ( wv )                              FIELD_GET( wv, 15, 1 )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_LOCK_L_WRITE( v, wv )                          FIELD_SET( v, 15, 1, wv )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_SSID_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 10, 0, 5, r)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_SSID_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 10, 0, 5, v)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_SSID_L_READ( wv )                              FIELD_GET( wv, 8, 5 )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_SSID_L_WRITE( v, wv )                          FIELD_SET( v, 8, 5, wv )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLAGS_READ(r, p)                               MREAD_8((uint8_t *)p + 11, r)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLAGS_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 11, v)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLAGS_L_READ( wv )                             FIELD_GET( wv, 0, 8 )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_FLAGS_L_WRITE( v, wv )                         FIELD_SET( v, 0, 8, wv )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_RD_IDX_READ(r, p)                              MREAD_16((uint8_t *)p + 12, r)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_RD_IDX_WRITE(v, p)                             MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_RD_IDX_L_READ( wv )                            FIELD_GET( wv, 16, 16 )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_RD_IDX_L_WRITE( v, wv )                        FIELD_SET( v, 16, 16, wv )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_WR_IDX_READ(r, p)                              MREAD_16((uint8_t *)p + 14, r)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_WR_IDX_WRITE(v, p)                             MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_WR_IDX_L_READ( wv )                            FIELD_GET( wv, 0, 16 )
+#define RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_WR_IDX_L_WRITE( v, wv )                        FIELD_SET( v, 0, 16, wv )
+#if defined DSL_63138
+
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_DTS	entry[ RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_DTS;
+
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_PTR()	( RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_FLOW_RING_CACHE_CTX_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#define RDD_FC_FLOW_IP_ADDRESSES_ENTRY_SA_DA_ADDRESSES_NUMBER	32
+#define RDD_FC_FLOW_IP_ADDRESSES_ENTRY_RESERVED0_NUMBER	4
+#define RDD_FC_FLOW_IP_ADDRESSES_ENTRY_RESERVED1_NUMBER	4
+
+typedef struct
+{
+	uint8_t	sa_da_addresses[RDD_FC_FLOW_IP_ADDRESSES_ENTRY_SA_DA_ADDRESSES_NUMBER];
+	uint8_t	reserved0[RDD_FC_FLOW_IP_ADDRESSES_ENTRY_RESERVED0_NUMBER];
+	uint32_t	reference_count                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	reserved1[RDD_FC_FLOW_IP_ADDRESSES_ENTRY_RESERVED1_NUMBER];
+	uint32_t	is_ipv6_address                                                           	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_FLOW_IP_ADDRESSES_ENTRY_DTS;
+
+#define RDD_FC_FLOW_IP_ADDRESSES_ENTRY_SA_DA_ADDRESSES_READ(r, p, i)              MREAD_I_8((uint8_t *)p, i, r)
+#define RDD_FC_FLOW_IP_ADDRESSES_ENTRY_SA_DA_ADDRESSES_WRITE(v, p, i)             MWRITE_I_8((uint8_t *)p, i, v)
+#define RDD_FC_FLOW_IP_ADDRESSES_ENTRY_REFERENCE_COUNT_READ(r, p)                 MREAD_32((uint8_t *)p + 36, r)
+#define RDD_FC_FLOW_IP_ADDRESSES_ENTRY_REFERENCE_COUNT_WRITE(v, p)                MWRITE_32((uint8_t *)p + 36, v)
+#define RDD_FC_FLOW_IP_ADDRESSES_ENTRY_IS_IPV6_ADDRESS_READ(r, p)                 MREAD_32((uint8_t *)p + 40, r)
+#define RDD_FC_FLOW_IP_ADDRESSES_ENTRY_IS_IPV6_ADDRESS_WRITE(v, p)                MWRITE_32((uint8_t *)p + 40, v)
+#if defined DSL_63138
+
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE     4
+typedef struct
+{
+	RDD_FC_FLOW_IP_ADDRESSES_ENTRY_DTS	entry[ RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_FLOW_IP_ADDRESSES_TABLE_DTS;
+
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_PTR()	( RDD_FC_FLOW_IP_ADDRESSES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + FC_FLOW_IP_ADDRESSES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_PTR()	( RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_MAINB_CURR_OFFSET_ADDRESS - 0x8000 )
+
+#endif
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_TX_QUEUE_ADDR_NUMBER	8
+
+typedef struct
+{
+	uint32_t	current_peak_budget                                                     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocated_peak_budget_exponent                                          	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocated_peak_budget                                                   	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_budget_limit_exponent                                              	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_budget_limit                                                       	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	current_sustain_budget                                                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	allocated_sustain_budget                                                	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_controller_mask                                                    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wan_channel_ptr                                                         	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	priority_queues_status                                                  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_burst_counter                                                      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_weight                                                             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0                                                               	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	peak_burst_flag                                                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	tx_queue_addr[RDD_US_RATE_CONTROLLER_DESCRIPTOR_TX_QUEUE_ADDR_NUMBER];
+	uint32_t	reserved1                                                               	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RATE_CONTROLLER_DESCRIPTOR_DTS;
+
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_CURRENT_PEAK_BUDGET_READ(r, p)                            MREAD_32((uint8_t *)p, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_CURRENT_PEAK_BUDGET_WRITE(v, p)                           MWRITE_32((uint8_t *)p, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_ALLOCATED_PEAK_BUDGET_EXPONENT_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 4, 6, 2, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_ALLOCATED_PEAK_BUDGET_EXPONENT_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 4, 6, 2, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_ALLOCATED_PEAK_BUDGET_READ(r, p)                          FIELD_MREAD_16((uint8_t *)p + 4, 0, 14, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_ALLOCATED_PEAK_BUDGET_WRITE(v, p)                         FIELD_MWRITE_16((uint8_t *)p + 4, 0, 14, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PEAK_BUDGET_LIMIT_EXPONENT_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 6, 6, 2, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PEAK_BUDGET_LIMIT_EXPONENT_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 6, 6, 2, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PEAK_BUDGET_LIMIT_READ(r, p)                              FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PEAK_BUDGET_LIMIT_WRITE(v, p)                             FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_CURRENT_SUSTAIN_BUDGET_READ(r, p)                         MREAD_32((uint8_t *)p + 8, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_CURRENT_SUSTAIN_BUDGET_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_ALLOCATED_SUSTAIN_BUDGET_READ(r, p)                       MREAD_32((uint8_t *)p + 12, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_ALLOCATED_SUSTAIN_BUDGET_WRITE(v, p)                      MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_RATE_CONTROLLER_MASK_READ(r, p)                           MREAD_32((uint8_t *)p + 16, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_RATE_CONTROLLER_MASK_WRITE(v, p)                          MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_WAN_CHANNEL_PTR_READ(r, p)                                MREAD_16((uint8_t *)p + 20, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_WAN_CHANNEL_PTR_WRITE(v, p)                               MWRITE_16((uint8_t *)p + 20, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PRIORITY_QUEUES_STATUS_READ(r, p)                         MREAD_16((uint8_t *)p + 22, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PRIORITY_QUEUES_STATUS_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 22, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PEAK_BURST_COUNTER_READ(r, p)                             MREAD_16((uint8_t *)p + 24, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PEAK_BURST_COUNTER_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 24, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PEAK_WEIGHT_READ(r, p)                                    MREAD_8((uint8_t *)p + 26, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PEAK_WEIGHT_WRITE(v, p)                                   MWRITE_8((uint8_t *)p + 26, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PEAK_BURST_FLAG_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 27, 0, 1, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_PEAK_BURST_FLAG_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 27, 0, 1, v)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_TX_QUEUE_ADDR_READ(r, p, i)                               MREAD_I_16((uint8_t *)p + 28, i, r)
+#define RDD_US_RATE_CONTROLLER_DESCRIPTOR_TX_QUEUE_ADDR_WRITE(v, p, i)                              MWRITE_I_16((uint8_t *)p + 28, i, v)
+#if defined DSL_63138
+
+#define RDD_US_RATE_CONTROLLERS_TABLE_SIZE     128
+typedef struct
+{
+	RDD_US_RATE_CONTROLLER_DESCRIPTOR_DTS	entry[ RDD_US_RATE_CONTROLLERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RATE_CONTROLLERS_TABLE_DTS;
+
+#define RDD_US_RATE_CONTROLLERS_TABLE_PTR()	( RDD_US_RATE_CONTROLLERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_RATE_CONTROLLERS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_RUNNER_B_SCRATCHPAD_DTS;
+
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_PTR()	( RDD_CPU_RX_RUNNER_B_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + CPU_RX_RUNNER_B_SCRATCHPAD_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     40
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS - 0x8000 )
+
+#endif
+#define RDD_DUMMY_WAN_TX_QUEUE_DESCRIPTOR_RESERVED_FW_ONLY_NUMBER	4
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_DUMMY_WAN_TX_QUEUE_DESCRIPTOR_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DUMMY_WAN_TX_QUEUE_DESCRIPTOR_DTS;
+
+#if defined DSL_63138
+
+#define RDD_IPV4_HOST_ADDRESS_TABLE_SIZE     8
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_IPV4_HOST_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPV4_HOST_ADDRESS_TABLE_DTS;
+
+#define RDD_IPV4_HOST_ADDRESS_TABLE_PTR()	( RDD_IPV4_HOST_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + IPV4_HOST_ADDRESS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     40
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS - 0x8000 )
+
+#endif
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_PTR()	( RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS - 0x8000 )
+
+#if defined DSL_63138
+
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_DTS	entry[ RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS;
+
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_PTR()	( RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#define RDD_PACKET_SRAM_TO_DDR_COPY_BUFFER_RESERVED_FW_ONLY_NUMBER	32
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_PACKET_SRAM_TO_DDR_COPY_BUFFER_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PACKET_SRAM_TO_DDR_COPY_BUFFER_DTS;
+
+#if defined DSL_63138
+
+#define RDD_MAIN_B_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_MAIN_B_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAIN_B_DEBUG_TRACE_DTS;
+
+#define RDD_MAIN_B_DEBUG_TRACE_PTR()	( RDD_MAIN_B_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + MAIN_B_DEBUG_TRACE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_PICO_B_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_PICO_B_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PICO_B_DEBUG_TRACE_DTS;
+
+#define RDD_PICO_B_DEBUG_TRACE_PTR()	( RDD_PICO_B_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + PICO_B_DEBUG_TRACE_ADDRESS - 0x8000 )
+
+#endif
+#define RDD_LAN_INGRESS_FIFO_ENTRY_RESERVED_FW_ONLY_NUMBER	32
+
+typedef struct
+{
+	uint16_t	reserved_fw_only[RDD_LAN_INGRESS_FIFO_ENTRY_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_LAN_INGRESS_FIFO_ENTRY_DTS;
+
+#if defined DSL_63138
+
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOB_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_PTR()	( RDD_RUNNER_FWTRACE_PICOB_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_PICOB_BASE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_BACKUP_INDEX_CACHE_DTS;
+
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_PTR()	( RDD_US_DHD_BACKUP_INDEX_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_DHD_BACKUP_INDEX_CACHE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_DOORBELL_COUNTERS_SIZE     48
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DHD_DOORBELL_COUNTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_DOORBELL_COUNTERS_DTS;
+
+#define RDD_DHD_DOORBELL_COUNTERS_PTR()	( RDD_DHD_DOORBELL_COUNTERS_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_DOORBELL_COUNTERS_ADDRESS - 0x8000 )
+
+#endif
+
+typedef struct
+{
+	uint32_t	dhd_backup_queues_ddr_ptr      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_bq_index_stack_ddr_ptr     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_bq_index_total_entry_count 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_bq_index_used_entry_count  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_bq_index_cache_a_cur_offset	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_bq_index_cache_b_cur_offset	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DTS;
+
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BACKUP_QUEUES_DDR_PTR_READ(r, p)                       MREAD_32((uint8_t *)p, r)
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BACKUP_QUEUES_DDR_PTR_WRITE(v, p)                      MWRITE_32((uint8_t *)p, v)
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BQ_INDEX_STACK_DDR_PTR_READ(r, p)                      MREAD_32((uint8_t *)p + 4, r)
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BQ_INDEX_STACK_DDR_PTR_WRITE(v, p)                     MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BQ_INDEX_TOTAL_ENTRY_COUNT_READ(r, p)                  MREAD_16((uint8_t *)p + 8, r)
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BQ_INDEX_TOTAL_ENTRY_COUNT_WRITE(v, p)                 MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BQ_INDEX_USED_ENTRY_COUNT_READ(r, p)                   MREAD_16((uint8_t *)p + 10, r)
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BQ_INDEX_USED_ENTRY_COUNT_WRITE(v, p)                  MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BQ_INDEX_CACHE_A_CUR_OFFSET_READ(r, p)                 MREAD_16((uint8_t *)p + 12, r)
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BQ_INDEX_CACHE_A_CUR_OFFSET_WRITE(v, p)                MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BQ_INDEX_CACHE_B_CUR_OFFSET_READ(r, p)                 MREAD_16((uint8_t *)p + 14, r)
+#define RDD_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ENTRY_DHD_BQ_INDEX_CACHE_B_CUR_OFFSET_WRITE(v, p)                MWRITE_16((uint8_t *)p + 14, v)
+#if defined DSL_63138
+
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_WAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_ENQUEUE_INGRESS_QUEUE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_PTR()	( RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_ADDRESS - 0x8000 )
+
+#endif
+/* DDR */
+#define RDD_BPM_PACKET_BUFFER_RESERVED_FW_ONLY_NUMBER	512
+
+typedef struct
+{
+	uint32_t	reserved_fw_only[RDD_BPM_PACKET_BUFFER_RESERVED_FW_ONLY_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BPM_PACKET_BUFFER_DTS;
+
+#if defined DSL_63138
+
+#define RDD_BPM_PACKET_BUFFERS_SIZE     7680
+typedef struct
+{
+	RDD_BPM_PACKET_BUFFER_DTS	entry[ RDD_BPM_PACKET_BUFFERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BPM_PACKET_BUFFERS_DTS;
+
+#endif
+
+#define RDD_CONNECTION_TABLE_SIZE     32768
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_CONNECTION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONNECTION_TABLE_DTS;
+
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_NUMBER	104
+
+typedef struct
+{
+	uint32_t	flow_hits                                                             	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_bytes                                                            	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast_flag                                                        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	overflow                                                              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_routed                                                             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_tos_mangle                                                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_l2_accel                                                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mtu                                                                   	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tos                                                                   	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_wred_high_prio                                                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_mapt_us                                                            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_df                                                                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	service_queue_id                                                      	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	drop                                                                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_unicast_wfd_any                                                    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	priority                                                              	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_prio                                                              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_idx                                                               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_phy                                                            	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_addresses_table_index                                              	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	link_specific_union                                                   	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_hit_trap                                                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_ingqos_high_prio                                                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_5                                                            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cpu_reason                                                            	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pathstat_idx                                                          	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_6                                                            	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pppoe_ses_id                                                          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	command_list[RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_NUMBER];
+	uint32_t	valid                                                                 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command_list_length_64                                                	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved4                                                             	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_unicast_wfd_nic                                                    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	connection_direction                                                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	connection_table_index                                                	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_DTS;
+
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_READ(r, p)                                MREAD_32((uint8_t *)p, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_WRITE(v, p)                               MWRITE_32((uint8_t *)p, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_READ(r, p)                               MREAD_32((uint8_t *)p + 4, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_WRITE(v, p)                              MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_OVERFLOW_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 8, 6, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_OVERFLOW_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 8, 5, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 8, 5, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 8, 4, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 8, 4, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_L2_ACCEL_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 8, 3, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_L2_ACCEL_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 8, 3, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_MTU_READ(r, p)                                      FIELD_MREAD_16((uint8_t *)p + 8, 0, 11, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_MTU_WRITE(v, p)                                     FIELD_MWRITE_16((uint8_t *)p + 8, 0, 11, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_TOS_READ(r, p)                                      MREAD_8((uint8_t *)p + 10, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_TOS_WRITE(v, p)                                     MWRITE_8((uint8_t *)p + 10, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_WRED_HIGH_PRIO_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 11, 7, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_WRED_HIGH_PRIO_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 11, 7, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_MAPT_US_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 11, 6, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_MAPT_US_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 11, 6, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_DF_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 11, 5, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_DF_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 11, 5, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_SERVICE_QUEUE_ID_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 11, 0, 5, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_SERVICE_QUEUE_ID_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 11, 0, 5, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_DROP_READ(r, p)                                     FIELD_MREAD_8((uint8_t *)p + 12, 7, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_DROP_WRITE(v, p)                                    FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_ANY_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 12, 6, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_ANY_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 12, 6, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_PRIORITY_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 12, 2, 4, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_PRIORITY_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 12, 2, 4, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_WFD_PRIO_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 12, 1, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_WFD_PRIO_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 12, 1, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_WFD_IDX_READ(r, p)                                  FIELD_MREAD_16((uint8_t *)p + 12, 7, 2, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_WFD_IDX_WRITE(v, p)                                 FIELD_MWRITE_16((uint8_t *)p + 12, 7, 2, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_EGRESS_PHY_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 13, 5, 2, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_EGRESS_PHY_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 13, 5, 2, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IP_ADDRESSES_TABLE_INDEX_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 13, 2, 3, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IP_ADDRESSES_TABLE_INDEX_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 13, 2, 3, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_LINK_SPECIFIC_UNION_READ(r, p)                      FIELD_MREAD_32((uint8_t *)p + 12, 0, 18, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_LINK_SPECIFIC_UNION_WRITE(v, p)                     FIELD_MWRITE_32((uint8_t *)p + 12, 0, 18, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_HIT_TRAP_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 16, 7, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_HIT_TRAP_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 16, 7, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_INGQOS_HIGH_PRIO_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 16, 6, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_INGQOS_HIGH_PRIO_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 16, 6, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_CPU_REASON_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 18, 0, 6, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_CPU_REASON_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 18, 0, 6, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_PATHSTAT_IDX_READ(r, p)                             MREAD_8((uint8_t *)p + 19, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_PATHSTAT_IDX_WRITE(v, p)                            MWRITE_8((uint8_t *)p + 19, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_PPPOE_SES_ID_READ(r, p)                             MREAD_16((uint8_t *)p + 22, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_PPPOE_SES_ID_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 22, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_READ(r, p, i)                          MREAD_I_8((uint8_t *)p + 24, i, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_WRITE(v, p, i)                         MWRITE_I_8((uint8_t *)p + 24, i, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_VALID_READ(r, p)                                    MREAD_8((uint8_t *)p + 128, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_VALID_WRITE(v, p)                                   MWRITE_8((uint8_t *)p + 128, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_LENGTH_64_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 129, 4, 4, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_LENGTH_64_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 129, 4, 4, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_NIC_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 129, 1, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_NIC_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 129, 1, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_CONNECTION_DIRECTION_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 129, 0, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_CONNECTION_DIRECTION_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 129, 0, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_CONNECTION_TABLE_INDEX_READ(r, p)                   MREAD_16((uint8_t *)p + 130, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_CONNECTION_TABLE_INDEX_WRITE(v, p)                  MWRITE_16((uint8_t *)p + 130, v)
+
+typedef struct
+{
+	uint32_t	reserved1      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved4      	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_info    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = egress_info, size = 2 bits
+	uint32_t	lag_port       	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_mode    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	egress_port    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	traffic_class  	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	rate_controller	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_DTS;
+
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_EGRESS_INFO_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 13, 0, 2, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_EGRESS_INFO_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 13, 0, 2, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_LAG_PORT_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 13, 0, 2, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_LAG_PORT_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 13, 0, 2, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_EGRESS_MODE_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 13, 0, 1, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_EGRESS_MODE_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 13, 0, 1, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_EGRESS_PORT_READ(r, p)                     MREAD_8((uint8_t *)p + 14, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_EGRESS_PORT_WRITE(v, p)                    MWRITE_8((uint8_t *)p + 14, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_TRAFFIC_CLASS_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 15, 5, 3, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_TRAFFIC_CLASS_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 15, 5, 3, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_RATE_CONTROLLER_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 15, 0, 5, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_RATE_CONTROLLER_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 15, 0, 5, v)
+
+typedef struct
+{
+	uint32_t	reserved1 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved4 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	chain_idx 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_UCAST_FLOW_CONTEXT_WFD_NIC_ENTRY_DTS;
+
+#define RDD_FC_UCAST_FLOW_CONTEXT_WFD_NIC_ENTRY_CHAIN_IDX_READ(r, p)                 MREAD_16((uint8_t *)p + 14, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_WFD_NIC_ENTRY_CHAIN_IDX_WRITE(v, p)                MWRITE_16((uint8_t *)p + 14, v)
+
+typedef struct
+{
+	uint32_t	reserved1   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved4   	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wifi_ssid   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_id	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_UCAST_FLOW_CONTEXT_WFD_DHD_ENTRY_DTS;
+
+#define RDD_FC_UCAST_FLOW_CONTEXT_WFD_DHD_ENTRY_WIFI_SSID_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 14, 2, 4, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_WFD_DHD_ENTRY_WIFI_SSID_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 14, 2, 4, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_WFD_DHD_ENTRY_FLOW_RING_ID_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 14, 0, 10, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_WFD_DHD_ENTRY_FLOW_RING_ID_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 14, 0, 10, v)
+
+typedef struct
+{
+	uint32_t	reserved1        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3        	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved4        	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhd_flow_priority	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	radio_idx        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wifi_ssid        	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_ring_id     	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_UCAST_FLOW_CONTEXT_RNR_DHD_ENTRY_DTS;
+
+#define RDD_FC_UCAST_FLOW_CONTEXT_RNR_DHD_ENTRY_DHD_FLOW_PRIORITY_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 13, 0, 2, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_RNR_DHD_ENTRY_DHD_FLOW_PRIORITY_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 13, 0, 2, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_RNR_DHD_ENTRY_RADIO_IDX_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 14, 6, 2, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_RNR_DHD_ENTRY_RADIO_IDX_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 14, 6, 2, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_RNR_DHD_ENTRY_WIFI_SSID_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 14, 2, 4, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_RNR_DHD_ENTRY_WIFI_SSID_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 14, 2, 4, v)
+#define RDD_FC_UCAST_FLOW_CONTEXT_RNR_DHD_ENTRY_FLOW_RING_ID_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 14, 0, 10, r)
+#define RDD_FC_UCAST_FLOW_CONTEXT_RNR_DHD_ENTRY_FLOW_RING_ID_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 14, 0, 10, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_NUMBER	104
+
+typedef struct
+{
+	uint32_t	flow_hits                                                                	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_bytes                                                               	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast_flag                                                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	overflow                                                                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_routed                                                                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_tos_mangle                                                            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_l2_accel                                                              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mtu                                                                      	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tos                                                                      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_wred_high_prio                                                        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2                                                                	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	service_queue_id                                                         	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	drop                                                                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_unicast_wfd_any                                                       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	priority                                                                 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_prio                                                                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_idx                                                                  	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_phy                                                               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_addresses_table_index                                                 	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	link_specific_union                                                      	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_hit_trap                                                              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_ingqos_high_prio                                                      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_5                                                               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cpu_reason                                                               	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pathstat_idx                                                             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_6                                                               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pppoe_ses_id                                                             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	command_list[RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_NUMBER];
+	uint32_t	valid                                                                    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command_list_length_64                                                   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved4                                                                	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_unicast_wfd_nic                                                       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	connection_direction                                                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	connection_table_index                                                   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_DTS;
+
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_READ(r, p)                                MREAD_32((uint8_t *)p, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_WRITE(v, p)                               MWRITE_32((uint8_t *)p, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_READ(r, p)                               MREAD_32((uint8_t *)p + 4, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_WRITE(v, p)                              MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_OVERFLOW_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 8, 6, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_OVERFLOW_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 8, 5, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 8, 5, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 8, 4, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 8, 4, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_L2_ACCEL_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 8, 3, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_L2_ACCEL_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 8, 3, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_MTU_READ(r, p)                                      FIELD_MREAD_16((uint8_t *)p + 8, 0, 11, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_MTU_WRITE(v, p)                                     FIELD_MWRITE_16((uint8_t *)p + 8, 0, 11, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_TOS_READ(r, p)                                      MREAD_8((uint8_t *)p + 10, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_TOS_WRITE(v, p)                                     MWRITE_8((uint8_t *)p + 10, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_WRED_HIGH_PRIO_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 11, 7, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_WRED_HIGH_PRIO_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 11, 7, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_SERVICE_QUEUE_ID_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 11, 0, 5, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_SERVICE_QUEUE_ID_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 11, 0, 5, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_DROP_READ(r, p)                                     FIELD_MREAD_8((uint8_t *)p + 12, 7, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_DROP_WRITE(v, p)                                    FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_ANY_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 12, 6, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_ANY_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 12, 6, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_PRIORITY_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 12, 2, 4, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_PRIORITY_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 12, 2, 4, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_WFD_PRIO_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 12, 1, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_WFD_PRIO_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 12, 1, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_WFD_IDX_READ(r, p)                                  FIELD_MREAD_16((uint8_t *)p + 12, 7, 2, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_WFD_IDX_WRITE(v, p)                                 FIELD_MWRITE_16((uint8_t *)p + 12, 7, 2, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_EGRESS_PHY_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 13, 5, 2, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_EGRESS_PHY_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 13, 5, 2, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IP_ADDRESSES_TABLE_INDEX_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 13, 2, 3, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IP_ADDRESSES_TABLE_INDEX_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 13, 2, 3, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_LINK_SPECIFIC_UNION_READ(r, p)                      FIELD_MREAD_32((uint8_t *)p + 12, 0, 18, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_LINK_SPECIFIC_UNION_WRITE(v, p)                     FIELD_MWRITE_32((uint8_t *)p + 12, 0, 18, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_HIT_TRAP_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 16, 7, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_HIT_TRAP_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 16, 7, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_INGQOS_HIGH_PRIO_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 16, 6, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_INGQOS_HIGH_PRIO_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 16, 6, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_CPU_REASON_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 18, 0, 6, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_CPU_REASON_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 18, 0, 6, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_PATHSTAT_IDX_READ(r, p)                             MREAD_8((uint8_t *)p + 19, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_PATHSTAT_IDX_WRITE(v, p)                            MWRITE_8((uint8_t *)p + 19, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_PPPOE_SES_ID_READ(r, p)                             MREAD_16((uint8_t *)p + 22, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_PPPOE_SES_ID_WRITE(v, p)                            MWRITE_16((uint8_t *)p + 22, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_READ(r, p, i)                          MREAD_I_8((uint8_t *)p + 24, i, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_WRITE(v, p, i)                         MWRITE_I_8((uint8_t *)p + 24, i, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_VALID_READ(r, p)                                    MREAD_8((uint8_t *)p + 128, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_VALID_WRITE(v, p)                                   MWRITE_8((uint8_t *)p + 128, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_LENGTH_64_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 129, 4, 4, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_LENGTH_64_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 129, 4, 4, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_NIC_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 129, 1, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_NIC_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 129, 1, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_CONNECTION_DIRECTION_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 129, 0, 1, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_CONNECTION_DIRECTION_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 129, 0, 1, v)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_CONNECTION_TABLE_INDEX_READ(r, p)                   MREAD_16((uint8_t *)p + 130, r)
+#define RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_CONNECTION_TABLE_INDEX_WRITE(v, p)                  MWRITE_16((uint8_t *)p + 130, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_PORT_CONTEXT_NUMBER	8
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_L3_COMMAND_LIST_NUMBER	20
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_RESERVED4_NUMBER	56
+
+typedef struct
+{
+	uint32_t	flow_hits                                                                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_bytes                                                                 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast_flag                                                             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	overflow                                                                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_routed                                                                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_tos_mangle                                                              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	number_of_ports                                                            	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	port_mask                                                                  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2                                                                  	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mtu                                                                        	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tos                                                                        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3                                                                  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wlan_mcast_clients                                                         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wlan_mcast_index                                                           	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mcast_port_header_buffer_ptr                                               	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	port_context[RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_PORT_CONTEXT_NUMBER];
+	uint8_t	l3_command_list[RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_L3_COMMAND_LIST_NUMBER];
+	uint8_t	reserved4[RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_RESERVED4_NUMBER];
+	uint32_t	valid                                                                      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command_list_length_64                                                     	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved5                                                                  	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	connection_direction                                                       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	connection_table_index                                                     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_DTS;
+
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_READ(r, p)                                    MREAD_32((uint8_t *)p, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_WRITE(v, p)                                   MWRITE_32((uint8_t *)p, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_READ(r, p)                                   MREAD_32((uint8_t *)p + 4, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_WRITE(v, p)                                  MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_OVERFLOW_READ(r, p)                                     FIELD_MREAD_8((uint8_t *)p + 8, 6, 1, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_OVERFLOW_WRITE(v, p)                                    FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 8, 5, 1, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 8, 5, 1, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 8, 4, 1, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 8, 4, 1, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_NUMBER_OF_PORTS_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 8, 0, 4, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_NUMBER_OF_PORTS_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 8, 0, 4, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_PORT_MASK_READ(r, p)                                    MREAD_8((uint8_t *)p + 9, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_PORT_MASK_WRITE(v, p)                                   MWRITE_8((uint8_t *)p + 9, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_MTU_READ(r, p)                                          FIELD_MREAD_16((uint8_t *)p + 10, 0, 11, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_MTU_WRITE(v, p)                                         FIELD_MWRITE_16((uint8_t *)p + 10, 0, 11, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_TOS_READ(r, p)                                          MREAD_8((uint8_t *)p + 12, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_TOS_WRITE(v, p)                                         MWRITE_8((uint8_t *)p + 12, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_WLAN_MCAST_CLIENTS_READ(r, p)                           MREAD_8((uint8_t *)p + 14, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_WLAN_MCAST_CLIENTS_WRITE(v, p)                          MWRITE_8((uint8_t *)p + 14, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_WLAN_MCAST_INDEX_READ(r, p)                             MREAD_8((uint8_t *)p + 15, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_WLAN_MCAST_INDEX_WRITE(v, p)                            MWRITE_8((uint8_t *)p + 15, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_MCAST_PORT_HEADER_BUFFER_PTR_READ(r, p)                 MREAD_32((uint8_t *)p + 16, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_MCAST_PORT_HEADER_BUFFER_PTR_WRITE(v, p)                MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_PORT_CONTEXT_READ(r, p, i)                              MREAD_I_32((uint8_t *)p + 20, i, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_PORT_CONTEXT_WRITE(v, p, i)                             MWRITE_I_32((uint8_t *)p + 20, i, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_L3_COMMAND_LIST_READ(r, p, i)                           MREAD_I_8((uint8_t *)p + 52, i, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_L3_COMMAND_LIST_WRITE(v, p, i)                          MWRITE_I_8((uint8_t *)p + 52, i, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_VALID_READ(r, p)                                        MREAD_8((uint8_t *)p + 128, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_VALID_WRITE(v, p)                                       MWRITE_8((uint8_t *)p + 128, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_LENGTH_64_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 129, 4, 4, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_LENGTH_64_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 129, 4, 4, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_CONNECTION_DIRECTION_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 129, 0, 1, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_CONNECTION_DIRECTION_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 129, 0, 1, v)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_CONNECTION_TABLE_INDEX_READ(r, p)                       MREAD_16((uint8_t *)p + 130, r)
+#define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_CONNECTION_TABLE_INDEX_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 130, v)
+#if defined DSL_63138
+
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE     8
+typedef struct
+{
+	RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_DTS	entry[ RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_R2D_WR_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_R2D_WR_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_R2D_WR_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_D2R_RD_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_D2R_RD_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_D2R_RD_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_R2D_RD_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_R2D_RD_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_R2D_RD_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_D2R_WR_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_D2R_WR_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_D2R_WR_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE     524288
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_BACKUP_QUEUES_BUFFER_DTS;
+
+#endif
+#define RDD_WLAN_MCAST_DHD_LIST_ENTRY_ARRAY_DHD_STATION_NUMBER	64
+
+typedef struct
+{
+	uint8_t	dhd_station[RDD_WLAN_MCAST_DHD_LIST_ENTRY_ARRAY_DHD_STATION_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_DHD_LIST_ENTRY_ARRAY_DTS;
+
+#define RDD_WLAN_MCAST_DHD_LIST_ENTRY_ARRAY_DHD_STATION_READ(r, p, i)              MREAD_I_8((uint8_t *)p, i, r)
+#define RDD_WLAN_MCAST_DHD_LIST_ENTRY_ARRAY_DHD_STATION_WRITE(v, p, i)             MWRITE_I_8((uint8_t *)p, i, v)
+#if defined DSL_63138
+
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_DHD_LIST_ENTRY_ARRAY_DTS	entry[ RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_DHD_LIST_TABLE_DTS;
+
+#endif
+
+typedef struct
+{
+	uint8_t	valid     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	index     	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_DHD_LIST_ENTRY_DTS;
+
+#define RDD_WLAN_MCAST_DHD_LIST_ENTRY_VALID_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_WLAN_MCAST_DHD_LIST_ENTRY_VALID_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_WLAN_MCAST_DHD_LIST_ENTRY_INDEX_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 0, 7, r)
+#define RDD_WLAN_MCAST_DHD_LIST_ENTRY_INDEX_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 0, 7, v)
+/* PSRAM */
+/* PRIVATE_A */
+#if defined DSL_63148
+
+#define RDD_INGRESS_HANDLER_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_IH_BUFFER_DTS	entry[ RDD_INGRESS_HANDLER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_HANDLER_BUFFER_DTS;
+
+#define RDD_INGRESS_HANDLER_BUFFER_PTR()	( RDD_INGRESS_HANDLER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + INGRESS_HANDLER_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+typedef struct
+{
+	uint32_t	crc_calc          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wan_port_or_fstat 	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	source_bridge_port	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	absolute_normal   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	last_indication   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pti               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	_1588             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	add_indication    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	header_number     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_offset    	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_location   	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = packet_location, size = 14 bits
+	uint32_t	buffer_number     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	abs_address_index 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_TX_DESCRIPTOR_DTS;
+
+#define RDD_BBH_TX_DESCRIPTOR_CRC_CALC_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_CRC_CALC_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_WAN_PORT_OR_FSTAT_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p, 3, 12, r)
+#define RDD_BBH_TX_DESCRIPTOR_WAN_PORT_OR_FSTAT_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p, 3, 12, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_BRIDGE_PORT_READ(r, p)                 FIELD_MREAD_32((uint8_t *)p + 0, 14, 5, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_BRIDGE_PORT_WRITE(v, p)                FIELD_MWRITE_32((uint8_t *)p + 0, 14, 5, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 2, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 2, 0, 14, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABSOLUTE_NORMAL_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABSOLUTE_NORMAL_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_INDICATION_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 4, 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_INDICATION_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 4, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_PTI_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 4, 4, 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_PTI_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 4, 4, 2, v)
+#define RDD_BBH_TX_DESCRIPTOR__1588_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 4, 3, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR__1588_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 4, 3, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_ADD_INDICATION_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 4, 2, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_ADD_INDICATION_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 4, 2, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_HEADER_NUMBER_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 4, 7, 3, r)
+#define RDD_BBH_TX_DESCRIPTOR_HEADER_NUMBER_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 4, 7, 3, v)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 5, 0, 7, r)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 5, 0, 7, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 6, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 6, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LOCATION_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LOCATION_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_ADDRESS_INDEX_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_ADDRESS_INDEX_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_BUFFER_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CONTEXT_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_PTR()	( RDD_DS_CONNECTION_CONTEXT_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CONTEXT_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_PTR()	( RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE     64
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_REASON_TO_METER_TABLE_DTS;
+
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_PTR()	( RDD_DS_CPU_REASON_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_REASON_TO_METER_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_CPU_RX_METER_TABLE_PTR()	( RDD_DS_CPU_RX_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_METER_TABLE_ADDRESS )
+
+#define RDD_DS_POLICER_TABLE_PTR()	( RDD_DS_POLICER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_POLICER_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_IPSEC_DS_BUFFER_POOL_SIZE     2
+typedef struct
+{
+	RDD_IPSEC_DS_BUFFER_DTS	entry[ RDD_IPSEC_DS_BUFFER_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_BUFFER_POOL_DTS;
+
+#define RDD_IPSEC_DS_BUFFER_POOL_PTR()	( RDD_IPSEC_DS_BUFFER_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_BUFFER_POOL_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_IPSEC_DS_SA_DESC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_DTS	entry[ RDD_IPSEC_DS_SA_DESC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_SA_DESC_TABLE_DTS;
+
+#define RDD_IPSEC_DS_SA_DESC_TABLE_PTR()	( RDD_IPSEC_DS_SA_DESC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_SA_DESC_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_IPSEC_US_SA_DESC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_DTS	entry[ RDD_IPSEC_US_SA_DESC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_US_SA_DESC_TABLE_DTS;
+
+#define RDD_IPSEC_US_SA_DESC_TABLE_PTR()	( RDD_IPSEC_US_SA_DESC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_US_SA_DESC_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_DTS	entry[ RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_PTR()	( RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + SERVICE_QUEUES_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_TIMER_SCHEDULER_PRIMITIVE_ENTRY_DTS	entry[ RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_DTS;
+
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_PTR()	( RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS )
+
+#endif
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_PARAMETER_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE ][ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_RATE_LIMITER_REMAINDER_ENTRY_DTS	entry[ RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_LIMITER_REMAINDER_TABLE_DTS;
+
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_PTR()	( RDD_RATE_LIMITER_REMAINDER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RATE_LIMITER_REMAINDER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+typedef struct
+{
+	RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_FC_MCAST_CONNECTION2_TABLE_SIZE     128
+typedef struct
+{
+	RDD_FC_MCAST_CONNECTION2_ENTRY_DTS	entry[ RDD_FC_MCAST_CONNECTION2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_CONNECTION2_TABLE_DTS;
+
+#define RDD_FC_MCAST_CONNECTION2_TABLE_PTR()	( RDD_FC_MCAST_CONNECTION2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + FC_MCAST_CONNECTION2_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE     72
+typedef struct
+{
+	RDD_ETH_TX_QUEUE_POINTERS_ENTRY_DTS	entry[ RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_QUEUES_POINTERS_TABLE_DTS;
+
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_PTR()	( RDD_ETH_TX_QUEUES_POINTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_QUEUES_POINTERS_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_ETH_TX_QUEUES_TABLE_SIZE     72
+typedef struct
+{
+	RDD_ETH_TX_QUEUE_DESCRIPTOR_DTS	entry[ RDD_ETH_TX_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_QUEUES_TABLE_DTS;
+
+#define RDD_ETH_TX_QUEUES_TABLE_PTR()	( RDD_ETH_TX_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_QUEUES_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_LOOKUP_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE ][ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_FORWARDING_MATRIX_ENTRY_DTS	entry[ RDD_DS_FORWARDING_MATRIX_TABLE_SIZE ][ RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FORWARDING_MATRIX_TABLE_DTS;
+
+#define RDD_DS_FORWARDING_MATRIX_TABLE_PTR()	( RDD_DS_FORWARDING_MATRIX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FORWARDING_MATRIX_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_L2_UCAST_CONNECTION_BUFFER_SIZE     4
+typedef struct
+{
+	RDD_FC_L2_UCAST_CONNECTION_ENTRY_DTS	entry[ RDD_DS_L2_UCAST_CONNECTION_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_L2_UCAST_CONNECTION_BUFFER_DTS;
+
+#define RDD_DS_L2_UCAST_CONNECTION_BUFFER_PTR()	( RDD_DS_L2_UCAST_CONNECTION_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_L2_UCAST_CONNECTION_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_ETH_TX_MAC_TABLE_SIZE     10
+typedef struct
+{
+	RDD_ETH_TX_MAC_DESCRIPTOR_DTS	entry[ RDD_ETH_TX_MAC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_MAC_TABLE_DTS;
+
+#define RDD_ETH_TX_MAC_TABLE_PTR()	( RDD_ETH_TX_MAC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_MAC_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_PTR()	( RDD_RUNNER_FWTRACE_MAINA_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RUNNER_FWTRACE_MAINA_PARAM_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_HANDLER_SKB_DATA_POINTER_DTS;
+
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_PTR()	( RDD_INGRESS_HANDLER_SKB_DATA_POINTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_COMPLETE_RING_DESCRIPTOR_DTS	entry[ RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_DTS;
+
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_PTR()	( RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOA_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_PTR()	( RDD_RUNNER_FWTRACE_PICOA_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RUNNER_FWTRACE_PICOA_PARAM_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_RATE_LIMITER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_RATE_LIMITER_ENTRY_DTS	entry[ RDD_DS_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_DS_RATE_LIMITER_TABLE_PTR()	( RDD_DS_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_WAN_FLOW_TABLE_SIZE     256
+typedef struct
+{
+	RDD_DS_WAN_FLOW_ENTRY_DTS	entry[ RDD_DS_WAN_FLOW_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_WAN_FLOW_TABLE_DTS;
+
+#define RDD_DS_WAN_FLOW_TABLE_PTR()	( RDD_DS_WAN_FLOW_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_WAN_FLOW_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_WAN_UDP_FILTER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DS_WAN_UDP_FILTER_ENTRY_DTS	entry[ RDD_DS_WAN_UDP_FILTER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_WAN_UDP_FILTER_TABLE_DTS;
+
+#define RDD_DS_WAN_UDP_FILTER_TABLE_PTR()	( RDD_DS_WAN_UDP_FILTER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_WAN_UDP_FILTER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE     8
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2    64
+typedef struct
+{
+	RDD_FC_MCAST_PORT_HEADER_ENTRY_DTS	entry[ RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE ][ RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_PORT_HEADER_BUFFER_DTS;
+
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_PTR()	( RDD_FC_MCAST_PORT_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + FC_MCAST_PORT_HEADER_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_MULTICAST_BUFFER_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_PTR()	( RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+typedef struct
+{
+	uint32_t	last_sbn        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	fstat_cell      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_id         	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length   	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	fstat_error     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error_type      	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ih_buffer_number	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number   	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_RX_DESCRIPTOR_DTS;
+
+#define RDD_BBH_RX_DESCRIPTOR_LAST_SBN_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p, 6, 10, r)
+#define RDD_BBH_RX_DESCRIPTOR_LAST_SBN_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p, 6, 10, v)
+#define RDD_BBH_RX_DESCRIPTOR_FSTAT_CELL_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 1, 5, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_FSTAT_CELL_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 1, 5, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_FLOW_ID_READ(r, p)                          FIELD_MREAD_32((uint8_t *)p + 0, 14, 7, r)
+#define RDD_BBH_RX_DESCRIPTOR_FLOW_ID_WRITE(v, p)                         FIELD_MWRITE_32((uint8_t *)p + 0, 14, 7, v)
+#define RDD_BBH_RX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 2, 0, 14, r)
+#define RDD_BBH_RX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 2, 0, 14, v)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_FSTAT_ERROR_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 4, 5, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_FSTAT_ERROR_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 4, 5, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_TYPE_READ(r, p)                       FIELD_MREAD_16((uint8_t *)p + 4, 6, 7, r)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_TYPE_WRITE(v, p)                      FIELD_MWRITE_16((uint8_t *)p + 4, 6, 7, v)
+#define RDD_BBH_RX_DESCRIPTOR_IH_BUFFER_NUMBER_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 5, 0, 6, r)
+#define RDD_BBH_RX_DESCRIPTOR_IH_BUFFER_NUMBER_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 5, 0, 6, v)
+#define RDD_BBH_RX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 6, 7, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 6, 7, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_BBH_RX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#endif
+#if defined DSL_63148
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE     64
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_DTS;
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_PTR()	( RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_LAN_ENQUEUE_SQ_PD_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_ETH0_RX_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_ETH0_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH0_RX_DESCRIPTORS_DTS;
+
+#define RDD_ETH0_RX_DESCRIPTORS_PTR()	( RDD_ETH0_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH0_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_SQ_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_CPU_TX_BBH_DESCRIPTORS_ENTRY_DTS	entry[ RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_TX_BBH_DESCRIPTORS_DTS;
+
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_PTR()	( RDD_DS_CPU_TX_BBH_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_TX_BBH_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+typedef struct
+{
+	uint32_t	reserved0    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1    	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_BPM_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_L_READ( wv )               FIELD_GET( wv, 0, 14 )
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_L_WRITE( v, wv )           FIELD_SET( v, 0, 14, wv )
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_SIZE     32
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DHD_TX_POST_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_PTR()	( RDD_DHD_TX_POST_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_TX_POST_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_CONNECTION_CACHE_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CACHE_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CACHE_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CACHE_BUFFER_PTR()	( RDD_DS_CONNECTION_CACHE_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CACHE_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_ETH_TX_LOCAL_REGISTERS_SIZE     9
+typedef struct
+{
+	RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_DTS	entry[ RDD_ETH_TX_LOCAL_REGISTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_LOCAL_REGISTERS_DTS;
+
+#define RDD_ETH_TX_LOCAL_REGISTERS_PTR()	( RDD_ETH_TX_LOCAL_REGISTERS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_LOCAL_REGISTERS_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     2
+typedef struct
+{
+	RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_QUEUE_PROFILE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_QUEUE_PROFILE_DTS	entry[ RDD_DS_QUEUE_PROFILE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_QUEUE_PROFILE_TABLE_DTS;
+
+#define RDD_DS_QUEUE_PROFILE_TABLE_PTR()	( RDD_DS_QUEUE_PROFILE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_QUEUE_PROFILE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_SQ_ENQUEUE_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DS_SQ_ENQUEUE_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_SQ_ENQUEUE_QUEUE_DTS;
+
+#define RDD_DS_SQ_ENQUEUE_QUEUE_PTR()	( RDD_DS_SQ_ENQUEUE_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_SQ_ENQUEUE_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_PTR()	( RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_NULL_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_NULL_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_NULL_BUFFER_DTS;
+
+#define RDD_DS_NULL_BUFFER_PTR()	( RDD_DS_NULL_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_NULL_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_GPE_COMMAND_PRIMITIVE_ENTRY_DTS	entry[ RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_PTR()	( RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_FAST_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_ROUTER_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_ROUTER_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_ROUTER_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_ROUTER_INGRESS_QUEUE_PTR()	( RDD_DS_ROUTER_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_ROUTER_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_COMPLETE_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_COMPLETE_RING_ENTRY_DTS	entry[ RDD_DHD_COMPLETE_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_COMPLETE_RING_BUFFER_DTS;
+
+#define RDD_DHD_COMPLETE_RING_BUFFER_PTR()	( RDD_DHD_COMPLETE_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_COMPLETE_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry[ RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS;
+
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_PTR()	( RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE     4
+typedef struct
+{
+	RDD_DHD_L2_HEADER_BUFFER_ENTRY_DTS	entry[ RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_HEADER_SCRATCH_DTS;
+
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_PTR()	( RDD_DS_DHD_TX_POST_HEADER_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_HEADER_SCRATCH_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE     5
+typedef struct
+{
+	RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DATA_POINTER_DUMMY_TARGET_DTS;
+
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_PTR()	( RDD_DS_DATA_POINTER_DUMMY_TARGET_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DATA_POINTER_DUMMY_TARGET_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_ENTRY_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR()	( RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_TASK_REORDER_ENTRY_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_PTR()	( RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_PTR()	( RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE     10
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_DTS;
+
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_PTR()	( RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_ABSOLUTE_TX_BBH_COUNTER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_DEBUG_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_DEBUG_BUFFER_ENTRY_DTS	entry[ RDD_DS_DEBUG_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DEBUG_BUFFER_DTS;
+
+#define RDD_DS_DEBUG_BUFFER_PTR()	( RDD_DS_DEBUG_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DEBUG_BUFFER_ADDRESS )
+
+#endif
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_FLOW_RING_DROP_COUNTER_DTS;
+
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_PTR()	( RDD_DS_DHD_FLOW_RING_DROP_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_FLOW_RING_DROP_COUNTER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_PTR()	( RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_RX_DIRECT_DESCRIPTORS_DTS;
+
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_PTR()	( RDD_GPON_RX_DIRECT_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GPON_RX_DIRECT_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_FW_MAC_ADDRS_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_FW_MAC_ADDRS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FW_MAC_ADDRS_DTS;
+
+#define RDD_DS_FW_MAC_ADDRS_PTR()	( RDD_DS_FW_MAC_ADDRS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FW_MAC_ADDRS_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_PTR()	( RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_PTR()	( RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_ETH_TX_SCRATCH_SIZE     16
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_ETH_TX_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_SCRATCH_DTS;
+
+#define RDD_ETH_TX_SCRATCH_PTR()	( RDD_ETH_TX_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_SCRATCH_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_GSO_TX_DHD_L2_BUFFER_SIZE     22
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_GSO_TX_DHD_L2_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_TX_DHD_L2_BUFFER_DTS;
+
+#define RDD_GSO_TX_DHD_L2_BUFFER_PTR()	( RDD_GSO_TX_DHD_L2_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_TX_DHD_L2_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_PTR()	( RDD_DS_DHD_TX_POST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_CAM_DTS	entry[ RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_SA_DESC_CAM_TABLE_DTS;
+
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_PTR()	( RDD_IPSEC_DS_SA_DESC_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_SA_DESC_CAM_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_INGRESS_QUEUE_DTS;
+
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_PTR()	( RDD_WLAN_MCAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + WLAN_MCAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_CAM_DTS	entry[ RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_US_SA_DESC_CAM_TABLE_DTS;
+
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_PTR()	( RDD_IPSEC_US_SA_DESC_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_US_SA_DESC_CAM_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE     5
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_RX_NORMAL_DESCRIPTORS_DTS;
+
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_PTR()	( RDD_GPON_RX_NORMAL_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GPON_RX_NORMAL_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_TX_DHD_L2_BUFFER_SIZE     22
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_L2_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_L2_BUFFER_DTS;
+
+#define RDD_CPU_TX_DHD_L2_BUFFER_PTR()	( RDD_CPU_TX_DHD_L2_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_DHD_L2_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE     4
+typedef struct
+{
+	RDD_HASH_BASED_FORWARDING_PORT_ENTRY_DTS	entry[ RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_HASH_BASED_FORWARDING_PORT_TABLE_DTS;
+
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_PTR()	( RDD_HASH_BASED_FORWARDING_PORT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + HASH_BASED_FORWARDING_PORT_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_TX_DHD_HOST_BUF_PTR_DTS;
+
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_PTR()	( RDD_GSO_TX_DHD_HOST_BUF_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_TX_DHD_HOST_BUF_PTR_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_HOST_BUF_PTR_DTS;
+
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_PTR()	( RDD_CPU_TX_DHD_HOST_BUF_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_DHD_HOST_BUF_PTR_ADDRESS )
+
+#endif
+/* PRIVATE_B */
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_HANDLER_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_IH_BUFFER_DTS	entry[ RDD_US_INGRESS_HANDLER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_HANDLER_BUFFER_DTS;
+
+#define RDD_US_INGRESS_HANDLER_BUFFER_PTR()	( RDD_US_INGRESS_HANDLER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_HANDLER_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_PTR()	( RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_US_CPU_REASON_TO_METER_TABLE_SIZE     64
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_US_CPU_REASON_TO_METER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_REASON_TO_METER_TABLE_DTS;
+
+#define RDD_US_CPU_REASON_TO_METER_TABLE_PTR()	( RDD_US_CPU_REASON_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_REASON_TO_METER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_MAIN_PROFILING_BUFFER_RUNNER_DTS;
+
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_PTR()	( RDD_US_MAIN_PROFILING_BUFFER_RUNNER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_LOOKUP_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE ][ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_QUEUE_PROFILE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_QUEUE_PROFILE_DTS	entry[ RDD_US_QUEUE_PROFILE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_QUEUE_PROFILE_TABLE_DTS;
+
+#define RDD_US_QUEUE_PROFILE_TABLE_PTR()	( RDD_US_QUEUE_PROFILE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_QUEUE_PROFILE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WAN_CHANNELS_8_39_TABLE_SIZE     32
+typedef struct
+{
+	RDD_WAN_CHANNEL_8_39_DESCRIPTOR_DTS	entry[ RDD_WAN_CHANNELS_8_39_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_CHANNELS_8_39_TABLE_DTS;
+
+#define RDD_WAN_CHANNELS_8_39_TABLE_PTR()	( RDD_WAN_CHANNELS_8_39_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_CHANNELS_8_39_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_RUNNER_FLOW_HEADER_BUFFER_DTS	entry[ RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RUNNER_FLOW_HEADER_BUFFER_DTS;
+
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_PTR()	( RDD_US_RUNNER_FLOW_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RUNNER_FLOW_HEADER_BUFFER_ADDRESS )
+
+#endif
+#define RDD_US_POLICER_TABLE_PTR()	( RDD_US_POLICER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_POLICER_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE     2
+typedef struct
+{
+	RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_DTS;
+
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_PTR()	( RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_WAN_FLOW_TABLE_SIZE     256
+typedef struct
+{
+	RDD_US_WAN_FLOW_ENTRY_DTS	entry[ RDD_US_WAN_FLOW_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_WAN_FLOW_TABLE_DTS;
+
+#define RDD_US_WAN_FLOW_TABLE_PTR()	( RDD_US_WAN_FLOW_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_WAN_FLOW_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_CPU_TX_BBH_DESCRIPTORS_ENTRY_DTS	entry[ RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_BBH_DESCRIPTORS_DTS;
+
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_PTR()	( RDD_US_CPU_TX_BBH_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_BBH_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_FORWARDING_MATRIX_ENTRY_DTS	entry[ RDD_US_FORWARDING_MATRIX_TABLE_SIZE ][ RDD_US_FORWARDING_MATRIX_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FORWARDING_MATRIX_TABLE_DTS;
+
+#define RDD_US_FORWARDING_MATRIX_TABLE_PTR()	( RDD_US_FORWARDING_MATRIX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FORWARDING_MATRIX_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_TIMER_SCHEDULER_PRIMITIVE_ENTRY_DTS	entry[ RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+typedef struct
+{
+	uint16_t	port_sel  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	reserved0 	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	pkt_eop   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	frag_size 	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DSL_PTM_BOND_TX_HDR_ENTRY_DTS;
+
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_PORT_SEL_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_PORT_SEL_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_PKT_EOP_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p, 4, 1, r)
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_PKT_EOP_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p, 4, 1, v)
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_FRAG_SIZE_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p, 0, 12, r)
+#define RDD_DSL_PTM_BOND_TX_HDR_ENTRY_FRAG_SIZE_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p, 0, 12, v)
+#endif
+#if defined DSL_63148
+
+#define RDD_DSL_PTM_BOND_TX_HDR_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DSL_PTM_BOND_TX_HDR_ENTRY_DTS	entry[ RDD_DSL_PTM_BOND_TX_HDR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DSL_PTM_BOND_TX_HDR_TABLE_DTS;
+
+#define RDD_DSL_PTM_BOND_TX_HDR_TABLE_PTR()	( RDD_DSL_PTM_BOND_TX_HDR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DSL_PTM_BOND_TX_HDR_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE     8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2    8
+typedef struct
+{
+	RDD_US_QUEUE_ENTRY_DTS	entry[ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE ][ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_DTS;
+
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_PTR()	( RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TRAFFIC_CLASS_TO_QUEUE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_RATE_LIMITER_TABLE_SIZE     16
+typedef struct
+{
+	RDD_RATE_LIMITER_ENTRY_DTS	entry[ RDD_US_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_US_RATE_LIMITER_TABLE_PTR()	( RDD_US_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_CPU_RX_METER_TABLE_PTR()	( RDD_US_CPU_RX_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_METER_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_BUFFER_ENTRY_DTS	entry[ RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_CONTEXT_BUFFER_DTS;
+
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_PTR()	( RDD_US_CONNECTION_CONTEXT_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CONNECTION_CONTEXT_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+typedef struct
+{
+	RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WAN_CHANNELS_0_7_TABLE_SIZE     8
+typedef struct
+{
+	RDD_WAN_CHANNEL_0_7_DESCRIPTOR_DTS	entry[ RDD_WAN_CHANNELS_0_7_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_CHANNELS_0_7_TABLE_DTS;
+
+#define RDD_WAN_CHANNELS_0_7_TABLE_PTR()	( RDD_WAN_CHANNELS_0_7_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_CHANNELS_0_7_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_L2_UCAST_CONNECTION_BUFFER_SIZE     4
+typedef struct
+{
+	RDD_FC_L2_UCAST_CONNECTION_ENTRY_DTS	entry[ RDD_US_L2_UCAST_CONNECTION_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_L2_UCAST_CONNECTION_BUFFER_DTS;
+
+#define RDD_US_L2_UCAST_CONNECTION_BUFFER_PTR()	( RDD_US_L2_UCAST_CONNECTION_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_L2_UCAST_CONNECTION_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_DTS;
+
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_PTR()	( RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_CONNECTION_CACHE_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_US_CONNECTION_CACHE_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_CACHE_BUFFER_DTS;
+
+#define RDD_US_CONNECTION_CACHE_BUFFER_PTR()	( RDD_US_CONNECTION_CACHE_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CONNECTION_CACHE_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_PARAMETER_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE ][ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE     5
+typedef struct
+{
+	RDD_INGRESS_RATE_LIMITER_ENTRY_DTS	entry[ RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_PTR()	( RDD_US_INGRESS_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_SIZE     8
+typedef struct
+{
+	RDD_DSL_PTM_BOND_TX_HDR_ENTRY_DTS	entry[ RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_DTS;
+
+#define RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_PTR()	( RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_RX_PICO_INGRESS_QUEUE_DTS;
+
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_PTR()	( RDD_US_CPU_RX_PICO_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_ROUTER_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_ROUTER_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_ROUTER_INGRESS_QUEUE_DTS;
+
+#define RDD_US_ROUTER_INGRESS_QUEUE_PTR()	( RDD_US_ROUTER_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_ROUTER_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     6
+typedef struct
+{
+	RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE     40
+typedef struct
+{
+	RDD_GPON_ABSOLUTE_TX_COUNTER_DTS	entry[ RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_DTS;
+
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_PTR()	( RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + GPON_ABSOLUTE_TX_BBH_COUNTER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_GPE_COMMAND_PRIMITIVE_ENTRY_DTS	entry[ RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_PTR()	( RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_RX_FAST_INGRESS_QUEUE_DTS;
+
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_PTR()	( RDD_US_CPU_RX_FAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_DEBUG_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_DEBUG_BUFFER_ENTRY_DTS	entry[ RDD_US_DEBUG_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DEBUG_BUFFER_DTS;
+
+#define RDD_US_DEBUG_BUFFER_PTR()	( RDD_US_DEBUG_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DEBUG_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_FW_MAC_ADDRS_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_US_FW_MAC_ADDRS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FW_MAC_ADDRS_DTS;
+
+#define RDD_US_FW_MAC_ADDRS_PTR()	( RDD_US_FW_MAC_ADDRS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FW_MAC_ADDRS_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE     3
+typedef struct
+{
+	RDD_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS	entry[ RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS;
+
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_PTR()	( RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry[ RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS;
+
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_PTR()	( RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_TX_POST_INGRESS_QUEUE_DTS;
+
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_PTR()	( RDD_US_DHD_TX_POST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DHD_TX_POST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_PTR()	( RDD_RUNNER_FWTRACE_MAINB_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + RUNNER_FWTRACE_MAINB_PARAM_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE     48
+typedef struct
+{
+	RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_ENTRY_DTS	entry[ RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_DTS;
+
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_PTR()	( RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOB_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_PTR()	( RDD_RUNNER_FWTRACE_PICOB_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + RUNNER_FWTRACE_PICOB_PARAM_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE     40
+typedef struct
+{
+	RDD_GPON_ABSOLUTE_TX_COUNTER_DTS	entry[ RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_DTS;
+
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_PTR()	( RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_FLOW_RING_DROP_COUNTER_DTS;
+
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_PTR()	( RDD_US_DHD_FLOW_RING_DROP_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DHD_FLOW_RING_DROP_COUNTER_ADDRESS )
+
+#endif
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_PTR()	( RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE     32
+typedef struct
+{
+	RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DATA_POINTER_DUMMY_TARGET_SIZE     2
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DATA_POINTER_DUMMY_TARGET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DATA_POINTER_DUMMY_TARGET_DTS;
+
+#define RDD_DATA_POINTER_DUMMY_TARGET_PTR()	( RDD_DATA_POINTER_DUMMY_TARGET_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DATA_POINTER_DUMMY_TARGET_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_PTR()	( RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WAN_TX_SCRATCH_SIZE     24
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_WAN_TX_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SCRATCH_DTS;
+
+#define RDD_WAN_TX_SCRATCH_PTR()	( RDD_WAN_TX_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_TX_SCRATCH_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE     3
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2    6
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE ][ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_DTS;
+
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_PTR()	( RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_ENTRY_DTS	entry[ RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR()	( RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE     9
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_PTR()	( RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE     14
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_DTS;
+
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_PTR()	( RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + CPU_TX_DHD_LAYER2_HEADER_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_TASK_REORDER_ENTRY_DTS	entry[ RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_PTR()	( RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_PTR()	( RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_PTR()	( RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_ETH1_RX_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_ETH1_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH1_RX_DESCRIPTORS_DTS;
+
+#define RDD_ETH1_RX_DESCRIPTORS_PTR()	( RDD_ETH1_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETH1_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+/* COMMON_A */
+#if defined DSL_63148
+
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE     384
+typedef struct
+{
+	RDD_SIXTEEN_BYTES_DTS	entry[ RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_DTS;
+
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_PTR()	( RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DDR_CACHE_FIFO_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_PTR()	( RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + FC_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_PTR()	( RDD_CPU_RX_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + CPU_RX_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_PTR()	( RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_PTR()	( RDD_RUNNER_FWTRACE_MAINA_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_MAINA_BASE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOA_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_PTR()	( RDD_RUNNER_FWTRACE_PICOA_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_PICOA_BASE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_DHD_STATION_ENTRY_DTS	entry[ RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_DHD_STATION_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_PTR()	( RDD_WLAN_MCAST_DHD_STATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_DHD_STATION_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_PTR()	( RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_MAC_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_ENTRY_DTS	entry[ RDD_MAC_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_TABLE_CAM_DTS;
+
+#define RDD_MAC_TABLE_CAM_PTR()	( RDD_MAC_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_TABLE_CAM_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_MAC_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_ENTRY_DTS	entry[ RDD_MAC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_TABLE_DTS;
+
+#define RDD_MAC_TABLE_PTR()	( RDD_MAC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+typedef struct
+{
+	uint32_t	reserved0         	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_offset    	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error_type        	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	source_bridge_port	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETHWAN2_RX_DESCRIPTOR_DTS;
+
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PAYLOAD_OFFSET_READ(r, p)                     FIELD_MREAD_32((uint8_t *)p + 0, 14, 7, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PAYLOAD_OFFSET_WRITE(v, p)                    FIELD_MWRITE_32((uint8_t *)p + 0, 14, 7, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 2, 0, 14, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 2, 0, 14, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_TYPE_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p + 4, 6, 7, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_TYPE_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p + 4, 6, 7, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_SOURCE_BRIDGE_PORT_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 5, 0, 6, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_SOURCE_BRIDGE_PORT_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 5, 0, 6, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 6, 7, 1, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 6, 7, 1, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#endif
+#if defined DSL_63148
+
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE     32
+typedef struct
+{
+	RDD_ETHWAN2_RX_DESCRIPTOR_DTS	entry[ RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETHWAN2_RX_INGRESS_QUEUE_DTS;
+
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_PTR()	( RDD_ETHWAN2_RX_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + ETHWAN2_RX_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_TRACE_C_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TRACE_C_ENTRY_DTS	entry[ RDD_TRACE_C_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TRACE_C_TABLE_DTS;
+
+#define RDD_TRACE_C_TABLE_PTR()	( RDD_TRACE_C_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + TRACE_C_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_PTR()	( RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_MAINA_CURR_OFFSET_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE     2
+typedef struct
+{
+	RDD_FREE_SKB_INDEXES_FIFO_TAIL_DTS	entry[ RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_DTS;
+
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_PTR()	( RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + FREE_SKB_INDEXES_DDR_FIFO_TAIL_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_MAC_CONTEXT_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_CONTEXT_ENTRY_DTS	entry[ RDD_MAC_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_CONTEXT_TABLE_DTS;
+
+#define RDD_MAC_CONTEXT_TABLE_PTR()	( RDD_MAC_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_CONTEXT_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE     32
+typedef struct
+{
+	RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+typedef struct
+{
+	RDD_BYTES_2_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WLAN_MCAST_FWD_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_FWD_ENTRY_DTS	entry[ RDD_WLAN_MCAST_FWD_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_FWD_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_FWD_TABLE_PTR()	( RDD_WLAN_MCAST_FWD_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_FWD_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DDR_QUEUE_DESCRIPTOR_DTS	entry[ RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_PTR()	( RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DESCRIPTOR_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE     48
+typedef struct
+{
+	RDD_WLAN_MCAST_SSID_MAC_ADDRESS_ENTRY_DTS	entry[ RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_PTR()	( RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE     8
+typedef struct
+{
+	RDD_DHD_BACKUP_ENTRY_DTS	entry[ RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_POST_REQUEST_QUEUE_DTS;
+
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_PTR()	( RDD_CPU_TX_POST_REQUEST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + CPU_TX_POST_REQUEST_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE     48
+typedef struct
+{
+	RDD_WLAN_MCAST_SSID_STATS_ENTRY_DTS	entry[ RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_SSID_STATS_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_PTR()	( RDD_WLAN_MCAST_SSID_STATS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_SSID_STATS_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE     3
+typedef struct
+{
+	RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DTS	entry[ RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_DTS;
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_PTR()	( RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_RADIO_INSTANCE_COMMON_A_DATA_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_DTS	entry[ RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS;
+
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_PTR()	( RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE     128
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_DTS;
+
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_PTR()	( RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RATE_SHAPERS_STATUS_DESCRIPTOR_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INTERRUPT_COALESCING_CONFIG_DTS	entry[ RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INTERRUPT_COALESCING_CONFIG_TABLE_DTS;
+
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_PTR()	( RDD_INTERRUPT_COALESCING_CONFIG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + INTERRUPT_COALESCING_CONFIG_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+typedef struct
+{
+	RDD_CPU_RX_DESCRIPTOR_DTS	entry[ RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_DTS;
+
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_PTR()	( RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2    4
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_DS_CONNECTION_BUFFER_TABLE_SIZE ][ RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_BUFFER_TABLE_DTS;
+
+#define RDD_DS_CONNECTION_BUFFER_TABLE_PTR()	( RDD_DS_CONNECTION_BUFFER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_CONNECTION_BUFFER_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_MAC_CONTEXT_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_CONTEXT_ENTRY_DTS	entry[ RDD_MAC_CONTEXT_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_CONTEXT_TABLE_CAM_DTS;
+
+#define RDD_MAC_CONTEXT_TABLE_CAM_PTR()	( RDD_MAC_CONTEXT_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_CONTEXT_TABLE_CAM_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_DOORBELL_WRITE_VALUES_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DHD_DOORBELL_WRITE_VALUES_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_DOORBELL_WRITE_VALUES_DTS;
+
+#define RDD_DHD_DOORBELL_WRITE_VALUES_PTR()	( RDD_DHD_DOORBELL_WRITE_VALUES_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_DOORBELL_WRITE_VALUES_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_BACKUP_INDEX_CACHE_DTS;
+
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_PTR()	( RDD_DS_DHD_BACKUP_INDEX_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_DHD_BACKUP_INDEX_CACHE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DDR_QUEUE_ADDRESS_ENTRY_DTS	entry[ RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_PTR()	( RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RING_DESCRIPTORS_TABLE_SIZE     16
+typedef struct
+{
+	RDD_RING_DESCRIPTOR_DTS	entry[ RDD_RING_DESCRIPTORS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RING_DESCRIPTORS_TABLE_DTS;
+
+#define RDD_RING_DESCRIPTORS_TABLE_PTR()	( RDD_RING_DESCRIPTORS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RING_DESCRIPTORS_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_MAC_EXTENSION_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_EXTENSION_ENTRY_DTS	entry[ RDD_MAC_EXTENSION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_EXTENSION_TABLE_DTS;
+
+#define RDD_MAC_EXTENSION_TABLE_PTR()	( RDD_MAC_EXTENSION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_EXTENSION_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE     16
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_DTS;
+
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_PTR()	( RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_MAC_EXTENSION_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_EXTENSION_ENTRY_DTS	entry[ RDD_MAC_EXTENSION_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_EXTENSION_TABLE_CAM_DTS;
+
+#define RDD_MAC_EXTENSION_TABLE_CAM_PTR()	( RDD_MAC_EXTENSION_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_EXTENSION_TABLE_CAM_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE     3
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TX_CPL_DHD_DMA_SCRATCH_DTS;
+
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_PTR()	( RDD_TX_CPL_DHD_DMA_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + TX_CPL_DHD_DMA_SCRATCH_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_SIZE     3
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_TX_POST_BUFFERS_THRESHOLD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_BUFFERS_THRESHOLD_DTS;
+
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_PTR()	( RDD_DHD_TX_POST_BUFFERS_THRESHOLD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_TX_POST_BUFFERS_THRESHOLD_ADDRESS )
+
+#endif
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_PTR()	( RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS )
+
+#if defined DSL_63148
+
+#define RDD_MAIN_A_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_MAIN_A_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAIN_A_DEBUG_TRACE_DTS;
+
+#define RDD_MAIN_A_DEBUG_TRACE_PTR()	( RDD_MAIN_A_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAIN_A_DEBUG_TRACE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_PICO_A_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_PICO_A_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PICO_A_DEBUG_TRACE_DTS;
+
+#define RDD_PICO_A_DEBUG_TRACE_PTR()	( RDD_PICO_A_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + PICO_A_DEBUG_TRACE_ADDRESS )
+
+#endif
+/* COMMON_B */
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WAN_TX_MIRROR_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_WAN_TX_MIRROR_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_MIRROR_SCRATCHPAD_DTS;
+
+#define RDD_WAN_TX_MIRROR_SCRATCHPAD_PTR()	( RDD_WAN_TX_MIRROR_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_TX_MIRROR_SCRATCHPAD_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+typedef struct
+{
+	RDD_BYTES_2_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SERVICE_QUEUES_TABLE_DTS;
+
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_PTR()	( RDD_WAN_TX_SERVICE_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_TX_SERVICE_QUEUES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE2    4
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_US_CONNECTION_BUFFER_TABLE_SIZE ][ RDD_US_CONNECTION_BUFFER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_BUFFER_TABLE_DTS;
+
+#define RDD_US_CONNECTION_BUFFER_TABLE_PTR()	( RDD_US_CONNECTION_BUFFER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_CONNECTION_BUFFER_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPV6_HOST_ADDRESS_CRC_TABLE_DTS;
+
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_PTR()	( RDD_IPV6_HOST_ADDRESS_CRC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + IPV6_HOST_ADDRESS_CRC_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_BACKUP_INFO_CACHE_ENTRY_DTS	entry[ RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_BACKUP_INFO_CACHE_TABLE_DTS;
+
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_PTR()	( RDD_DHD_BACKUP_INFO_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_BACKUP_INFO_CACHE_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WAN_TX_QUEUES_TABLE_SIZE     256
+typedef struct
+{
+	RDD_WAN_TX_QUEUE_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_QUEUES_TABLE_DTS;
+
+#define RDD_WAN_TX_QUEUES_TABLE_PTR()	( RDD_WAN_TX_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_TX_QUEUES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_PTR()	( RDD_RUNNER_FWTRACE_MAINB_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_MAINB_BASE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+typedef struct
+{
+	RDD_CPU_RX_DESCRIPTOR_DTS	entry[ RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RING_PACKET_DESCRIPTORS_CACHE_DTS;
+
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_PTR()	( RDD_US_RING_PACKET_DESCRIPTORS_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE     3
+typedef struct
+{
+	RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_DTS	entry[ RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_DTS;
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_PTR()	( RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_RADIO_INSTANCE_COMMON_B_DATA_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_DTS	entry[ RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_DTS;
+
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_PTR()	( RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_FLOW_RING_CACHE_CTX_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE     4
+typedef struct
+{
+	RDD_FC_FLOW_IP_ADDRESSES_ENTRY_DTS	entry[ RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_FLOW_IP_ADDRESSES_TABLE_DTS;
+
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_PTR()	( RDD_FC_FLOW_IP_ADDRESSES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + FC_FLOW_IP_ADDRESSES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_PTR()	( RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_MAINB_CURR_OFFSET_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_RATE_CONTROLLERS_TABLE_SIZE     128
+typedef struct
+{
+	RDD_US_RATE_CONTROLLER_DESCRIPTOR_DTS	entry[ RDD_US_RATE_CONTROLLERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RATE_CONTROLLERS_TABLE_DTS;
+
+#define RDD_US_RATE_CONTROLLERS_TABLE_PTR()	( RDD_US_RATE_CONTROLLERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_RATE_CONTROLLERS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_RUNNER_B_SCRATCHPAD_DTS;
+
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_PTR()	( RDD_CPU_RX_RUNNER_B_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + CPU_RX_RUNNER_B_SCRATCHPAD_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     40
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_IPV4_HOST_ADDRESS_TABLE_SIZE     8
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_IPV4_HOST_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPV4_HOST_ADDRESS_TABLE_DTS;
+
+#define RDD_IPV4_HOST_ADDRESS_TABLE_PTR()	( RDD_IPV4_HOST_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + IPV4_HOST_ADDRESS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     40
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS - 0x8000 )
+
+#endif
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_PTR()	( RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS - 0x8000 )
+
+#if defined DSL_63148
+
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_DTS	entry[ RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS;
+
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_PTR()	( RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_MAIN_B_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_MAIN_B_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAIN_B_DEBUG_TRACE_DTS;
+
+#define RDD_MAIN_B_DEBUG_TRACE_PTR()	( RDD_MAIN_B_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + MAIN_B_DEBUG_TRACE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_PICO_B_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_PICO_B_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PICO_B_DEBUG_TRACE_DTS;
+
+#define RDD_PICO_B_DEBUG_TRACE_PTR()	( RDD_PICO_B_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + PICO_B_DEBUG_TRACE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOB_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_PTR()	( RDD_RUNNER_FWTRACE_PICOB_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_PICOB_BASE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_BACKUP_INDEX_CACHE_DTS;
+
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_PTR()	( RDD_US_DHD_BACKUP_INDEX_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_DHD_BACKUP_INDEX_CACHE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_DOORBELL_COUNTERS_SIZE     48
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DHD_DOORBELL_COUNTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_DOORBELL_COUNTERS_DTS;
+
+#define RDD_DHD_DOORBELL_COUNTERS_PTR()	( RDD_DHD_DOORBELL_COUNTERS_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_DOORBELL_COUNTERS_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_WAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_ENQUEUE_INGRESS_QUEUE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_PTR()	( RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_ADDRESS - 0x8000 )
+
+#endif
+/* DDR */
+#if defined DSL_63148
+
+#define RDD_BPM_PACKET_BUFFERS_SIZE     7680
+typedef struct
+{
+	RDD_BPM_PACKET_BUFFER_DTS	entry[ RDD_BPM_PACKET_BUFFERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BPM_PACKET_BUFFERS_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE     8
+typedef struct
+{
+	RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_DTS	entry[ RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_R2D_WR_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_R2D_WR_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_R2D_WR_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_D2R_RD_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_D2R_RD_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_D2R_RD_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_R2D_RD_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_R2D_RD_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_R2D_RD_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_D2R_WR_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_D2R_WR_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_D2R_WR_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE     524288
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_BACKUP_QUEUES_BUFFER_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_DHD_LIST_ENTRY_ARRAY_DTS	entry[ RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_DHD_LIST_TABLE_DTS;
+
+#endif
+/* PSRAM */
+/* PRIVATE_A */
+#if defined WL4908
+
+#define RDD_INGRESS_HANDLER_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_IH_BUFFER_DTS	entry[ RDD_INGRESS_HANDLER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_HANDLER_BUFFER_DTS;
+
+#define RDD_INGRESS_HANDLER_BUFFER_PTR()	( RDD_INGRESS_HANDLER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + INGRESS_HANDLER_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+typedef struct
+{
+	uint32_t	reserved0            	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wred_bit_reserved0   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_queue_reserved0   	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_port_reserved0	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	header_number        	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	source_bridge_port   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length        	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	absolute_normal      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	misc                 	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = misc, size = 3 bits
+	uint32_t	last_indication      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pti                  	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ring_id              	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	payload_offset       	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ddr_params           	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = ddr_params, size = 2 bits
+	uint32_t	ddr_id               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	packet_location      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = packet_location, size = 16 bits
+	uint32_t	buffer_number        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2            	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	abs_address_index    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_TX_DESCRIPTOR_DTS;
+
+#define RDD_BBH_TX_DESCRIPTOR_WRED_BIT_RESERVED0_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p, 3, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_WRED_BIT_RESERVED0_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p, 3, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_TX_QUEUE_RESERVED0_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p, 0, 3, r)
+#define RDD_BBH_TX_DESCRIPTOR_TX_QUEUE_RESERVED0_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p, 0, 3, v)
+#define RDD_BBH_TX_DESCRIPTOR_EGRESS_PORT_RESERVED0_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 1, 3, 5, r)
+#define RDD_BBH_TX_DESCRIPTOR_EGRESS_PORT_RESERVED0_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 1, 3, 5, v)
+#define RDD_BBH_TX_DESCRIPTOR_HEADER_NUMBER_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 1, 0, 3, r)
+#define RDD_BBH_TX_DESCRIPTOR_HEADER_NUMBER_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 1, 0, 3, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_BRIDGE_PORT_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 2, 4, 4, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_BRIDGE_PORT_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 2, 4, 4, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p + 2, 0, 12, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p + 2, 0, 12, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABSOLUTE_NORMAL_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABSOLUTE_NORMAL_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_MISC_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 4, 4, 3, r)
+#define RDD_BBH_TX_DESCRIPTOR_MISC_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 4, 4, 3, v)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_INDICATION_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 4, 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_INDICATION_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 4, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_PTI_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 4, 4, 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_PTI_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 4, 4, 2, v)
+#define RDD_BBH_TX_DESCRIPTOR_RING_ID_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 4, 4, 3, r)
+#define RDD_BBH_TX_DESCRIPTOR_RING_ID_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 4, 4, 3, v)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_READ(r, p)                        FIELD_MREAD_16((uint8_t *)p + 4, 3, 9, r)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_WRITE(v, p)                       FIELD_MWRITE_16((uint8_t *)p + 4, 3, 9, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 5, 2, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 5, 2, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_DDR_PARAMS_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 5, 0, 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_DDR_PARAMS_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 5, 0, 2, v)
+#define RDD_BBH_TX_DESCRIPTOR_DDR_ID_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 5, 1, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_DDR_ID_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 5, 1, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LOCATION_READ(r, p)                       MREAD_16((uint8_t *)p + 6, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LOCATION_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                         MREAD_16((uint8_t *)p + 6, r)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_ADDRESS_INDEX_READ(r, p)                     FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_ADDRESS_INDEX_WRITE(v, p)                    FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#endif
+#if defined WL4908
+
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_BUFFER_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CONTEXT_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_PTR()	( RDD_DS_CONNECTION_CONTEXT_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CONTEXT_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_PTR()	( RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE     64
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_REASON_TO_METER_TABLE_DTS;
+
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_PTR()	( RDD_DS_CPU_REASON_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_REASON_TO_METER_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_CPU_RX_METER_TABLE_PTR()	( RDD_DS_CPU_RX_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_METER_TABLE_ADDRESS )
+
+#define RDD_DS_POLICER_TABLE_PTR()	( RDD_DS_POLICER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_POLICER_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_IPSEC_DS_BUFFER_POOL_SIZE     2
+typedef struct
+{
+	RDD_IPSEC_DS_BUFFER_DTS	entry[ RDD_IPSEC_DS_BUFFER_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_BUFFER_POOL_DTS;
+
+#define RDD_IPSEC_DS_BUFFER_POOL_PTR()	( RDD_IPSEC_DS_BUFFER_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_BUFFER_POOL_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_IPSEC_DS_SA_DESC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_DTS	entry[ RDD_IPSEC_DS_SA_DESC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_SA_DESC_TABLE_DTS;
+
+#define RDD_IPSEC_DS_SA_DESC_TABLE_PTR()	( RDD_IPSEC_DS_SA_DESC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_SA_DESC_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_IPSEC_US_SA_DESC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_DTS	entry[ RDD_IPSEC_US_SA_DESC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_US_SA_DESC_TABLE_DTS;
+
+#define RDD_IPSEC_US_SA_DESC_TABLE_PTR()	( RDD_IPSEC_US_SA_DESC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_US_SA_DESC_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_DTS	entry[ RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_PTR()	( RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + SERVICE_QUEUES_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_TIMER_SCHEDULER_PRIMITIVE_ENTRY_DTS	entry[ RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_DTS;
+
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_PTR()	( RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS )
+
+#endif
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_PARAMETER_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE ][ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_RATE_LIMITER_REMAINDER_ENTRY_DTS	entry[ RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_LIMITER_REMAINDER_TABLE_DTS;
+
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_PTR()	( RDD_RATE_LIMITER_REMAINDER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RATE_LIMITER_REMAINDER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+typedef struct
+{
+	RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_FC_MCAST_CONNECTION2_TABLE_SIZE     128
+typedef struct
+{
+	RDD_FC_MCAST_CONNECTION2_ENTRY_DTS	entry[ RDD_FC_MCAST_CONNECTION2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_CONNECTION2_TABLE_DTS;
+
+#define RDD_FC_MCAST_CONNECTION2_TABLE_PTR()	( RDD_FC_MCAST_CONNECTION2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + FC_MCAST_CONNECTION2_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE     72
+typedef struct
+{
+	RDD_ETH_TX_QUEUE_POINTERS_ENTRY_DTS	entry[ RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_QUEUES_POINTERS_TABLE_DTS;
+
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_PTR()	( RDD_ETH_TX_QUEUES_POINTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_QUEUES_POINTERS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_WAN_FLOW_TABLE_SIZE     256
+typedef struct
+{
+	RDD_DS_WAN_FLOW_ENTRY_DTS	entry[ RDD_DS_WAN_FLOW_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_WAN_FLOW_TABLE_DTS;
+
+#define RDD_DS_WAN_FLOW_TABLE_PTR()	( RDD_DS_WAN_FLOW_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_WAN_FLOW_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+#define RDD_CONTEXT_CONTINUATION_ENTRY_COMMAND_LIST_NUMBER	68
+
+typedef struct
+{
+	uint32_t	valid                                                               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                                                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	connection_direction                                                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_unicast_wfd_nic                                                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2                                                           	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	connection_table_index                                              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3                                                           	:17	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_index                                                          	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	command_list[RDD_CONTEXT_CONTINUATION_ENTRY_COMMAND_LIST_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONTEXT_CONTINUATION_ENTRY_DTS;
+
+#define RDD_CONTEXT_CONTINUATION_ENTRY_VALID_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_VALID_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_CONNECTION_DIRECTION_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p, 5, 1, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_CONNECTION_DIRECTION_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p, 5, 1, v)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_IS_UNICAST_WFD_NIC_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p, 4, 1, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_IS_UNICAST_WFD_NIC_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p, 4, 1, v)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_CONNECTION_TABLE_INDEX_READ(r, p)                 MREAD_16((uint8_t *)p + 2, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_CONNECTION_TABLE_INDEX_WRITE(v, p)                MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_FLOW_INDEX_READ(r, p)                             FIELD_MREAD_16((uint8_t *)p + 6, 0, 15, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_FLOW_INDEX_WRITE(v, p)                            FIELD_MWRITE_16((uint8_t *)p + 6, 0, 15, v)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_COMMAND_LIST_READ(r, p, i)                        MREAD_I_8((uint8_t *)p + 8, i, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_COMMAND_LIST_WRITE(v, p, i)                       MWRITE_I_8((uint8_t *)p + 8, i, v)
+#endif
+#if defined WL4908
+
+#define RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONTEXT_CONTINUATION_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_PTR()	( RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CONTEXT_REMAINING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_LOOKUP_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE ][ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_FORWARDING_MATRIX_ENTRY_DTS	entry[ RDD_DS_FORWARDING_MATRIX_TABLE_SIZE ][ RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FORWARDING_MATRIX_TABLE_DTS;
+
+#define RDD_DS_FORWARDING_MATRIX_TABLE_PTR()	( RDD_DS_FORWARDING_MATRIX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FORWARDING_MATRIX_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_LAN_TX_ACB_COUNTER_TABLE_SIZE     64
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry[ RDD_LAN_TX_ACB_COUNTER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_LAN_TX_ACB_COUNTER_TABLE_DTS;
+
+#define RDD_LAN_TX_ACB_COUNTER_TABLE_PTR()	( RDD_LAN_TX_ACB_COUNTER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + LAN_TX_ACB_COUNTER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_WAN_UDP_FILTER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DS_WAN_UDP_FILTER_ENTRY_DTS	entry[ RDD_DS_WAN_UDP_FILTER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_WAN_UDP_FILTER_TABLE_DTS;
+
+#define RDD_DS_WAN_UDP_FILTER_TABLE_PTR()	( RDD_DS_WAN_UDP_FILTER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_WAN_UDP_FILTER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_PTR()	( RDD_RUNNER_FWTRACE_MAINA_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RUNNER_FWTRACE_MAINA_PARAM_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_RATE_LIMITER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_RATE_LIMITER_ENTRY_DTS	entry[ RDD_DS_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_DS_RATE_LIMITER_TABLE_PTR()	( RDD_DS_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_ETH_TX_QUEUES_TABLE_SIZE     72
+typedef struct
+{
+	RDD_ETH_TX_QUEUE_DESCRIPTOR_DTS	entry[ RDD_ETH_TX_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_QUEUES_TABLE_DTS;
+
+#define RDD_ETH_TX_QUEUES_TABLE_PTR()	( RDD_ETH_TX_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_QUEUES_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_HANDLER_SKB_DATA_POINTER_DTS;
+
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_PTR()	( RDD_INGRESS_HANDLER_SKB_DATA_POINTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE     8
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2    64
+typedef struct
+{
+	RDD_FC_MCAST_PORT_HEADER_ENTRY_DTS	entry[ RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE ][ RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_PORT_HEADER_BUFFER_DTS;
+
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_PTR()	( RDD_FC_MCAST_PORT_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + FC_MCAST_PORT_HEADER_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+typedef struct
+{
+	uint32_t	last_sbn        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_offset  	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length   	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1       	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error_type      	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ih_buffer_number	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ddr_id          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_RX_DESCRIPTOR_DTS;
+
+#define RDD_BBH_RX_DESCRIPTOR_LAST_SBN_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p, 6, 10, r)
+#define RDD_BBH_RX_DESCRIPTOR_LAST_SBN_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p, 6, 10, v)
+#define RDD_BBH_RX_DESCRIPTOR_PAYLOAD_OFFSET_READ(r, p)                   FIELD_MREAD_32((uint8_t *)p + 0, 13, 9, r)
+#define RDD_BBH_RX_DESCRIPTOR_PAYLOAD_OFFSET_WRITE(v, p)                  FIELD_MWRITE_32((uint8_t *)p + 0, 13, 9, v)
+#define RDD_BBH_RX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 2, 0, 12, r)
+#define RDD_BBH_RX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 2, 0, 12, v)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_TYPE_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 4, 1, 4, r)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_TYPE_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 4, 1, 4, v)
+#define RDD_BBH_RX_DESCRIPTOR_IH_BUFFER_NUMBER_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 4, 3, 6, r)
+#define RDD_BBH_RX_DESCRIPTOR_IH_BUFFER_NUMBER_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 4, 3, 6, v)
+#define RDD_BBH_RX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 5, 2, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 5, 2, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_DDR_ID_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 5, 1, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_DDR_ID_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 5, 1, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                    MREAD_16((uint8_t *)p + 6, r)
+#define RDD_BBH_RX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 6, v)
+#endif
+#if defined WL4908
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE     64
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_DTS;
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_PTR()	( RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_LAN_ENQUEUE_SQ_PD_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_MULTICAST_BUFFER_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_PTR()	( RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_SQ_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_CPU_TX_BBH_DESCRIPTORS_ENTRY_DTS	entry[ RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_TX_BBH_DESCRIPTORS_DTS;
+
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_PTR()	( RDD_DS_CPU_TX_BBH_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_TX_BBH_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908
+
+typedef struct
+{
+	uint32_t	reserved0    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_BPM_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_READ(r, p)                 FIELD_MREAD_32((uint8_t *)p + 4, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_WRITE(v, p)                FIELD_MWRITE_32((uint8_t *)p + 4, 0, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_L_READ( wv )               FIELD_GET( wv, 0, 18 )
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_L_WRITE( v, wv )           FIELD_SET( v, 0, 18, wv )
+#endif
+#if defined WL4908
+
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_SIZE     32
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DHD_TX_POST_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_PTR()	( RDD_DHD_TX_POST_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_TX_POST_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_ETH_TX_LOCAL_REGISTERS_SIZE     9
+typedef struct
+{
+	RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_DTS	entry[ RDD_ETH_TX_LOCAL_REGISTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_LOCAL_REGISTERS_DTS;
+
+#define RDD_ETH_TX_LOCAL_REGISTERS_PTR()	( RDD_ETH_TX_LOCAL_REGISTERS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_LOCAL_REGISTERS_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     2
+typedef struct
+{
+	RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOA_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_PTR()	( RDD_RUNNER_FWTRACE_PICOA_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RUNNER_FWTRACE_PICOA_PARAM_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_COMPLETE_RING_DESCRIPTOR_DTS	entry[ RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_DTS;
+
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_PTR()	( RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_QUEUE_PROFILE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_QUEUE_PROFILE_DTS	entry[ RDD_DS_QUEUE_PROFILE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_QUEUE_PROFILE_TABLE_DTS;
+
+#define RDD_DS_QUEUE_PROFILE_TABLE_PTR()	( RDD_DS_QUEUE_PROFILE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_QUEUE_PROFILE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_SQ_ENQUEUE_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DS_SQ_ENQUEUE_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_SQ_ENQUEUE_QUEUE_DTS;
+
+#define RDD_DS_SQ_ENQUEUE_QUEUE_PTR()	( RDD_DS_SQ_ENQUEUE_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_SQ_ENQUEUE_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_PTR()	( RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+
+typedef struct
+{
+	uint32_t	reserved_fw_only	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BYTES_4_DTS;
+
+#if defined WL4908
+
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_ROUTER_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_ROUTER_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_ROUTER_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_ROUTER_INGRESS_QUEUE_PTR()	( RDD_DS_ROUTER_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_ROUTER_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_NULL_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_NULL_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_NULL_BUFFER_DTS;
+
+#define RDD_DS_NULL_BUFFER_PTR()	( RDD_DS_NULL_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_NULL_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_FAST_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_PTR()	( RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_GPE_COMMAND_PRIMITIVE_ENTRY_DTS	entry[ RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_PTR()	( RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE     4
+typedef struct
+{
+	RDD_DHD_L2_HEADER_BUFFER_ENTRY_DTS	entry[ RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_HEADER_SCRATCH_DTS;
+
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_PTR()	( RDD_DS_DHD_TX_POST_HEADER_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_HEADER_SCRATCH_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE     5
+typedef struct
+{
+	RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_DEBUG_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_DEBUG_BUFFER_ENTRY_DTS	entry[ RDD_DS_DEBUG_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DEBUG_BUFFER_DTS;
+
+#define RDD_DS_DEBUG_BUFFER_PTR()	( RDD_DS_DEBUG_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DEBUG_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_COMPLETE_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_COMPLETE_RING_ENTRY_DTS	entry[ RDD_DHD_COMPLETE_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_COMPLETE_RING_BUFFER_DTS;
+
+#define RDD_DHD_COMPLETE_RING_BUFFER_PTR()	( RDD_DHD_COMPLETE_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_COMPLETE_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_FAST_MALLOC_RESULT_TABLE_SIZE     2
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DS_FAST_MALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FAST_MALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DS_FAST_MALLOC_RESULT_TABLE_PTR()	( RDD_DS_FAST_MALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_MALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE     10
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_DTS;
+
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_PTR()	( RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_ABSOLUTE_TX_BBH_COUNTER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_FW_MAC_ADDRS_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_FW_MAC_ADDRS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FW_MAC_ADDRS_DTS;
+
+#define RDD_DS_FW_MAC_ADDRS_PTR()	( RDD_DS_FW_MAC_ADDRS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FW_MAC_ADDRS_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_PICO_MALLOC_RESULT_TABLE_SIZE     2
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DS_PICO_MALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PICO_MALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DS_PICO_MALLOC_RESULT_TABLE_PTR()	( RDD_DS_PICO_MALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_MALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry[ RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS;
+
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_PTR()	( RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DATA_POINTER_DUMMY_TARGET_DTS;
+
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_PTR()	( RDD_DS_DATA_POINTER_DUMMY_TARGET_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DATA_POINTER_DUMMY_TARGET_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_RX_DIRECT_DESCRIPTORS_DTS;
+
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_PTR()	( RDD_GPON_RX_DIRECT_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GPON_RX_DIRECT_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_ENTRY_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR()	( RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_TASK_REORDER_ENTRY_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_PTR()	( RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_FLOW_RING_DROP_COUNTER_DTS;
+
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_PTR()	( RDD_DS_DHD_FLOW_RING_DROP_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_FLOW_RING_DROP_COUNTER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_PTR()	( RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_PTR()	( RDD_DS_DHD_TX_POST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_INGRESS_QUEUE_DTS;
+
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_PTR()	( RDD_WLAN_MCAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + WLAN_MCAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_PTR()	( RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_PTR()	( RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_CAM_DTS	entry[ RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_SA_DESC_CAM_TABLE_DTS;
+
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_PTR()	( RDD_IPSEC_DS_SA_DESC_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_SA_DESC_CAM_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_CAM_DTS	entry[ RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_US_SA_DESC_CAM_TABLE_DTS;
+
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_PTR()	( RDD_IPSEC_US_SA_DESC_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_US_SA_DESC_CAM_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_ETH_TX_SCRATCH_SIZE     16
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_ETH_TX_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_SCRATCH_DTS;
+
+#define RDD_ETH_TX_SCRATCH_PTR()	( RDD_ETH_TX_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_SCRATCH_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_GSO_TX_DHD_L2_BUFFER_SIZE     22
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_GSO_TX_DHD_L2_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_TX_DHD_L2_BUFFER_DTS;
+
+#define RDD_GSO_TX_DHD_L2_BUFFER_PTR()	( RDD_GSO_TX_DHD_L2_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_TX_DHD_L2_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_TX_DHD_L2_BUFFER_SIZE     22
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_L2_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_L2_BUFFER_DTS;
+
+#define RDD_CPU_TX_DHD_L2_BUFFER_PTR()	( RDD_CPU_TX_DHD_L2_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_DHD_L2_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE     5
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE     4
+typedef struct
+{
+	RDD_HASH_BASED_FORWARDING_PORT_ENTRY_DTS	entry[ RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_HASH_BASED_FORWARDING_PORT_TABLE_DTS;
+
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_PTR()	( RDD_HASH_BASED_FORWARDING_PORT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + HASH_BASED_FORWARDING_PORT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_TX_DHD_HOST_BUF_PTR_DTS;
+
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_PTR()	( RDD_GSO_TX_DHD_HOST_BUF_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_TX_DHD_HOST_BUF_PTR_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_HOST_BUF_PTR_DTS;
+
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_PTR()	( RDD_CPU_TX_DHD_HOST_BUF_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_DHD_HOST_BUF_PTR_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_ETH_TX_MAC_TABLE_SIZE     8
+typedef struct
+{
+	RDD_ETH_TX_MAC_DESCRIPTOR_DTS	entry[ RDD_ETH_TX_MAC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_MAC_TABLE_DTS;
+
+#define RDD_ETH_TX_MAC_TABLE_PTR()	( RDD_ETH_TX_MAC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_MAC_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_RX_NORMAL_DESCRIPTORS_DTS;
+
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_PTR()	( RDD_GPON_RX_NORMAL_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GPON_RX_NORMAL_DESCRIPTORS_ADDRESS )
+
+#endif
+/* PRIVATE_B */
+#if defined WL4908
+
+#define RDD_US_INGRESS_HANDLER_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_IH_BUFFER_DTS	entry[ RDD_US_INGRESS_HANDLER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_HANDLER_BUFFER_DTS;
+
+#define RDD_US_INGRESS_HANDLER_BUFFER_PTR()	( RDD_US_INGRESS_HANDLER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_HANDLER_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_PTR()	( RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_US_CPU_REASON_TO_METER_TABLE_SIZE     64
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_US_CPU_REASON_TO_METER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_REASON_TO_METER_TABLE_DTS;
+
+#define RDD_US_CPU_REASON_TO_METER_TABLE_PTR()	( RDD_US_CPU_REASON_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_REASON_TO_METER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_MAIN_PROFILING_BUFFER_RUNNER_DTS;
+
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_PTR()	( RDD_US_MAIN_PROFILING_BUFFER_RUNNER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_LOOKUP_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE ][ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_QUEUE_PROFILE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_QUEUE_PROFILE_DTS	entry[ RDD_US_QUEUE_PROFILE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_QUEUE_PROFILE_TABLE_DTS;
+
+#define RDD_US_QUEUE_PROFILE_TABLE_PTR()	( RDD_US_QUEUE_PROFILE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_QUEUE_PROFILE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_WAN_CHANNELS_8_39_TABLE_SIZE     32
+typedef struct
+{
+	RDD_WAN_CHANNEL_8_39_DESCRIPTOR_DTS	entry[ RDD_WAN_CHANNELS_8_39_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_CHANNELS_8_39_TABLE_DTS;
+
+#define RDD_WAN_CHANNELS_8_39_TABLE_PTR()	( RDD_WAN_CHANNELS_8_39_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_CHANNELS_8_39_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_RUNNER_FLOW_HEADER_BUFFER_DTS	entry[ RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RUNNER_FLOW_HEADER_BUFFER_DTS;
+
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_PTR()	( RDD_US_RUNNER_FLOW_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RUNNER_FLOW_HEADER_BUFFER_ADDRESS )
+
+#endif
+#define RDD_US_POLICER_TABLE_PTR()	( RDD_US_POLICER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_POLICER_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE     2
+typedef struct
+{
+	RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_DTS;
+
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_PTR()	( RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_WAN_FLOW_TABLE_SIZE     256
+typedef struct
+{
+	RDD_US_WAN_FLOW_ENTRY_DTS	entry[ RDD_US_WAN_FLOW_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_WAN_FLOW_TABLE_DTS;
+
+#define RDD_US_WAN_FLOW_TABLE_PTR()	( RDD_US_WAN_FLOW_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_WAN_FLOW_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_CPU_TX_BBH_DESCRIPTORS_ENTRY_DTS	entry[ RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_BBH_DESCRIPTORS_DTS;
+
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_PTR()	( RDD_US_CPU_TX_BBH_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_BBH_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_FORWARDING_MATRIX_ENTRY_DTS	entry[ RDD_US_FORWARDING_MATRIX_TABLE_SIZE ][ RDD_US_FORWARDING_MATRIX_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FORWARDING_MATRIX_TABLE_DTS;
+
+#define RDD_US_FORWARDING_MATRIX_TABLE_PTR()	( RDD_US_FORWARDING_MATRIX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FORWARDING_MATRIX_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_TIMER_SCHEDULER_PRIMITIVE_ENTRY_DTS	entry[ RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE     8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2    8
+typedef struct
+{
+	RDD_US_QUEUE_ENTRY_DTS	entry[ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE ][ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_DTS;
+
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_PTR()	( RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TRAFFIC_CLASS_TO_QUEUE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_US_RATE_LIMITER_TABLE_SIZE     16
+typedef struct
+{
+	RDD_RATE_LIMITER_ENTRY_DTS	entry[ RDD_US_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_US_RATE_LIMITER_TABLE_PTR()	( RDD_US_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_CPU_RX_METER_TABLE_PTR()	( RDD_US_CPU_RX_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_METER_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_BUFFER_ENTRY_DTS	entry[ RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_CONTEXT_BUFFER_DTS;
+
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_PTR()	( RDD_US_CONNECTION_CONTEXT_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CONNECTION_CONTEXT_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+typedef struct
+{
+	RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_WAN_CHANNELS_0_7_TABLE_SIZE     8
+typedef struct
+{
+	RDD_WAN_CHANNEL_0_7_DESCRIPTOR_DTS	entry[ RDD_WAN_CHANNELS_0_7_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_CHANNELS_0_7_TABLE_DTS;
+
+#define RDD_WAN_CHANNELS_0_7_TABLE_PTR()	( RDD_WAN_CHANNELS_0_7_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_CHANNELS_0_7_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_DTS;
+
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_PTR()	( RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONTEXT_CONTINUATION_ENTRY_DTS	entry[ RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_DTS;
+
+#define RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_PTR()	( RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CONNECTION_CONTEXT_REMAINING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_PARAMETER_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE ][ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DHD_RX_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE     40
+typedef struct
+{
+	RDD_GPON_ABSOLUTE_TX_COUNTER_DTS	entry[ RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_DTS;
+
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_PTR()	( RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + GPON_ABSOLUTE_TX_BBH_COUNTER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE     5
+typedef struct
+{
+	RDD_INGRESS_RATE_LIMITER_ENTRY_DTS	entry[ RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_PTR()	( RDD_US_INGRESS_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_PTR()	( RDD_RUNNER_FWTRACE_MAINB_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + RUNNER_FWTRACE_MAINB_PARAM_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_RX_PICO_INGRESS_QUEUE_DTS;
+
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_PTR()	( RDD_US_CPU_RX_PICO_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_ROUTER_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_ROUTER_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_ROUTER_INGRESS_QUEUE_DTS;
+
+#define RDD_US_ROUTER_INGRESS_QUEUE_PTR()	( RDD_US_ROUTER_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_ROUTER_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     6
+typedef struct
+{
+	RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_RX_FAST_INGRESS_QUEUE_DTS;
+
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_PTR()	( RDD_US_CPU_RX_FAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE     3
+typedef struct
+{
+	RDD_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS	entry[ RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS;
+
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_PTR()	( RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_DEBUG_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_DEBUG_BUFFER_ENTRY_DTS	entry[ RDD_US_DEBUG_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DEBUG_BUFFER_DTS;
+
+#define RDD_US_DEBUG_BUFFER_PTR()	( RDD_US_DEBUG_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DEBUG_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_FW_MAC_ADDRS_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_US_FW_MAC_ADDRS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FW_MAC_ADDRS_DTS;
+
+#define RDD_US_FW_MAC_ADDRS_PTR()	( RDD_US_FW_MAC_ADDRS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FW_MAC_ADDRS_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_TX_POST_INGRESS_QUEUE_DTS;
+
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_PTR()	( RDD_US_DHD_TX_POST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DHD_TX_POST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE     48
+typedef struct
+{
+	RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_ENTRY_DTS	entry[ RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_DTS;
+
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_PTR()	( RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_GPE_COMMAND_PRIMITIVE_ENTRY_DTS	entry[ RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_PTR()	( RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_FAST_MALLOC_RESULT_TABLE_SIZE     2
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_FAST_MALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FAST_MALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_FAST_MALLOC_RESULT_TABLE_PTR()	( RDD_US_FAST_MALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_MALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE     40
+typedef struct
+{
+	RDD_GPON_ABSOLUTE_TX_COUNTER_DTS	entry[ RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_DTS;
+
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_PTR()	( RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOB_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_PTR()	( RDD_RUNNER_FWTRACE_PICOB_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + RUNNER_FWTRACE_PICOB_PARAM_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_FLOW_RING_DROP_COUNTER_DTS;
+
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_PTR()	( RDD_US_DHD_FLOW_RING_DROP_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DHD_FLOW_RING_DROP_COUNTER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_PICO_MALLOC_RESULT_TABLE_SIZE     2
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_PICO_MALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PICO_MALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_PICO_MALLOC_RESULT_TABLE_PTR()	( RDD_US_PICO_MALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_MALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_PTR()	( RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry[ RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS;
+
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_PTR()	( RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_PTR()	( RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE     32
+typedef struct
+{
+	RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_WAN_TX_SCRATCH_SIZE     24
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_WAN_TX_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SCRATCH_DTS;
+
+#define RDD_WAN_TX_SCRATCH_PTR()	( RDD_WAN_TX_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_TX_SCRATCH_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE     3
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2    6
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE ][ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_DTS;
+
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_PTR()	( RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE     9
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_PTR()	( RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE     14
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_DTS;
+
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_PTR()	( RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + CPU_TX_DHD_LAYER2_HEADER_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DATA_POINTER_DUMMY_TARGET_SIZE     2
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DATA_POINTER_DUMMY_TARGET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DATA_POINTER_DUMMY_TARGET_DTS;
+
+#define RDD_DATA_POINTER_DUMMY_TARGET_PTR()	( RDD_DATA_POINTER_DUMMY_TARGET_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DATA_POINTER_DUMMY_TARGET_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_ENTRY_DTS	entry[ RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR()	( RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_TASK_REORDER_ENTRY_DTS	entry[ RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_PTR()	( RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_PTR()	( RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_PTR()	( RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_ETH2_RX_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_ETH2_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH2_RX_DESCRIPTORS_DTS;
+
+#define RDD_ETH2_RX_DESCRIPTORS_PTR()	( RDD_ETH2_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETH2_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_ETH1_RX_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_ETH1_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH1_RX_DESCRIPTORS_DTS;
+
+#define RDD_ETH1_RX_DESCRIPTORS_PTR()	( RDD_ETH1_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETH1_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_ETH0_RX_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_ETH0_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH0_RX_DESCRIPTORS_DTS;
+
+#define RDD_ETH0_RX_DESCRIPTORS_PTR()	( RDD_ETH0_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETH0_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+/* COMMON_A */
+#if defined WL4908
+
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE     256
+typedef struct
+{
+	RDD_SIXTEEN_BYTES_DTS	entry[ RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_DTS;
+
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_PTR()	( RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DDR_CACHE_FIFO_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_PTR()	( RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + FC_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_PTR()	( RDD_CPU_RX_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + CPU_RX_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_DTS;
+
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR()	( RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_PTR()	( RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_PTR()	( RDD_RUNNER_FWTRACE_MAINA_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_MAINA_BASE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOA_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_PTR()	( RDD_RUNNER_FWTRACE_PICOA_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_PICOA_BASE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_DHD_STATION_ENTRY_DTS	entry[ RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_DHD_STATION_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_PTR()	( RDD_WLAN_MCAST_DHD_STATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_DHD_STATION_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_PTR()	( RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_MAC_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_ENTRY_DTS	entry[ RDD_MAC_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_TABLE_CAM_DTS;
+
+#define RDD_MAC_TABLE_CAM_PTR()	( RDD_MAC_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_TABLE_CAM_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_MAC_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_ENTRY_DTS	entry[ RDD_MAC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_TABLE_DTS;
+
+#define RDD_MAC_TABLE_PTR()	( RDD_MAC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+typedef struct
+{
+	uint32_t	reserved0         	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_offset    	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length     	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error_type        	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	source_bridge_port	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ddr_id            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETHWAN2_RX_DESCRIPTOR_DTS;
+
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PAYLOAD_OFFSET_READ(r, p)                     FIELD_MREAD_32((uint8_t *)p + 0, 13, 9, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PAYLOAD_OFFSET_WRITE(v, p)                    FIELD_MWRITE_32((uint8_t *)p + 0, 13, 9, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 2, 0, 12, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 2, 0, 12, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_TYPE_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 4, 1, 4, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_TYPE_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 4, 1, 4, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_SOURCE_BRIDGE_PORT_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 4, 3, 6, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_SOURCE_BRIDGE_PORT_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 4, 3, 6, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 5, 2, 1, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 5, 2, 1, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_DDR_ID_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 5, 1, 1, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_DDR_ID_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 5, 1, 1, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                      MREAD_16((uint8_t *)p + 6, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 6, v)
+#endif
+#if defined WL4908
+
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE     32
+typedef struct
+{
+	RDD_ETHWAN2_RX_DESCRIPTOR_DTS	entry[ RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETHWAN2_RX_INGRESS_QUEUE_DTS;
+
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_PTR()	( RDD_ETHWAN2_RX_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + ETHWAN2_RX_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_TRACE_C_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TRACE_C_ENTRY_DTS	entry[ RDD_TRACE_C_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TRACE_C_TABLE_DTS;
+
+#define RDD_TRACE_C_TABLE_PTR()	( RDD_TRACE_C_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + TRACE_C_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_PTR()	( RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_MAINA_CURR_OFFSET_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE     2
+typedef struct
+{
+	RDD_FREE_SKB_INDEXES_FIFO_TAIL_DTS	entry[ RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_DTS;
+
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_PTR()	( RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + FREE_SKB_INDEXES_DDR_FIFO_TAIL_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_MAC_CONTEXT_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_CONTEXT_ENTRY_DTS	entry[ RDD_MAC_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_CONTEXT_TABLE_DTS;
+
+#define RDD_MAC_CONTEXT_TABLE_PTR()	( RDD_MAC_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_CONTEXT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE     32
+typedef struct
+{
+	RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+typedef struct
+{
+	RDD_BYTES_2_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_WLAN_MCAST_FWD_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_FWD_ENTRY_DTS	entry[ RDD_WLAN_MCAST_FWD_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_FWD_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_FWD_TABLE_PTR()	( RDD_WLAN_MCAST_FWD_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_FWD_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DDR_QUEUE_DESCRIPTOR_DTS	entry[ RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_PTR()	( RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DESCRIPTOR_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE     48
+typedef struct
+{
+	RDD_WLAN_MCAST_SSID_MAC_ADDRESS_ENTRY_DTS	entry[ RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_PTR()	( RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE     8
+typedef struct
+{
+	RDD_DHD_BACKUP_ENTRY_DTS	entry[ RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_POST_REQUEST_QUEUE_DTS;
+
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_PTR()	( RDD_CPU_TX_POST_REQUEST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + CPU_TX_POST_REQUEST_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE     48
+typedef struct
+{
+	RDD_WLAN_MCAST_SSID_STATS_ENTRY_DTS	entry[ RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_SSID_STATS_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_PTR()	( RDD_WLAN_MCAST_SSID_STATS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_SSID_STATS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE     3
+typedef struct
+{
+	RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DTS	entry[ RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_DTS;
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_PTR()	( RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_RADIO_INSTANCE_COMMON_A_DATA_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_DTS	entry[ RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS;
+
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_PTR()	( RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE     128
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_DTS;
+
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_PTR()	( RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RATE_SHAPERS_STATUS_DESCRIPTOR_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INTERRUPT_COALESCING_CONFIG_DTS	entry[ RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INTERRUPT_COALESCING_CONFIG_TABLE_DTS;
+
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_PTR()	( RDD_INTERRUPT_COALESCING_CONFIG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + INTERRUPT_COALESCING_CONFIG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2    4
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_DS_CONNECTION_BUFFER_TABLE_SIZE ][ RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_BUFFER_TABLE_DTS;
+
+#define RDD_DS_CONNECTION_BUFFER_TABLE_PTR()	( RDD_DS_CONNECTION_BUFFER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_CONNECTION_BUFFER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_MAC_CONTEXT_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_CONTEXT_ENTRY_DTS	entry[ RDD_MAC_CONTEXT_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_CONTEXT_TABLE_CAM_DTS;
+
+#define RDD_MAC_CONTEXT_TABLE_CAM_PTR()	( RDD_MAC_CONTEXT_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_CONTEXT_TABLE_CAM_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_DOORBELL_WRITE_VALUES_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DHD_DOORBELL_WRITE_VALUES_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_DOORBELL_WRITE_VALUES_DTS;
+
+#define RDD_DHD_DOORBELL_WRITE_VALUES_PTR()	( RDD_DHD_DOORBELL_WRITE_VALUES_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_DOORBELL_WRITE_VALUES_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_BACKUP_INDEX_CACHE_DTS;
+
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_PTR()	( RDD_DS_DHD_BACKUP_INDEX_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_DHD_BACKUP_INDEX_CACHE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+typedef struct
+{
+	RDD_CPU_RX_DESCRIPTOR_DTS	entry[ RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_DTS;
+
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_PTR()	( RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_RING_DESCRIPTORS_TABLE_SIZE     16
+typedef struct
+{
+	RDD_RING_DESCRIPTOR_DTS	entry[ RDD_RING_DESCRIPTORS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RING_DESCRIPTORS_TABLE_DTS;
+
+#define RDD_RING_DESCRIPTORS_TABLE_PTR()	( RDD_RING_DESCRIPTORS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RING_DESCRIPTORS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DDR_QUEUE_ADDRESS_ENTRY_DTS	entry[ RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_PTR()	( RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_MAC_EXTENSION_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_EXTENSION_ENTRY_DTS	entry[ RDD_MAC_EXTENSION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_EXTENSION_TABLE_DTS;
+
+#define RDD_MAC_EXTENSION_TABLE_PTR()	( RDD_MAC_EXTENSION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_EXTENSION_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE     16
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_DTS;
+
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_PTR()	( RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_MAC_EXTENSION_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_EXTENSION_ENTRY_DTS	entry[ RDD_MAC_EXTENSION_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_EXTENSION_TABLE_CAM_DTS;
+
+#define RDD_MAC_EXTENSION_TABLE_CAM_PTR()	( RDD_MAC_EXTENSION_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_EXTENSION_TABLE_CAM_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE     3
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TX_CPL_DHD_DMA_SCRATCH_DTS;
+
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_PTR()	( RDD_TX_CPL_DHD_DMA_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + TX_CPL_DHD_DMA_SCRATCH_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_SIZE     6
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_TX_POST_BUFFERS_THRESHOLD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_BUFFERS_THRESHOLD_DTS;
+
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_PTR()	( RDD_DHD_TX_POST_BUFFERS_THRESHOLD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_TX_POST_BUFFERS_THRESHOLD_ADDRESS )
+
+#endif
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_PTR()	( RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS )
+
+#if defined WL4908
+
+#define RDD_DHD_TX_POST_BUFFERS_IN_USE_COUNTER_SIZE     2
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_TX_POST_BUFFERS_IN_USE_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_BUFFERS_IN_USE_COUNTER_DTS;
+
+#define RDD_DHD_TX_POST_BUFFERS_IN_USE_COUNTER_PTR()	( RDD_DHD_TX_POST_BUFFERS_IN_USE_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_TX_POST_BUFFERS_IN_USE_COUNTER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_MAIN_A_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_MAIN_A_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAIN_A_DEBUG_TRACE_DTS;
+
+#define RDD_MAIN_A_DEBUG_TRACE_PTR()	( RDD_MAIN_A_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAIN_A_DEBUG_TRACE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_PICO_A_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_PICO_A_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PICO_A_DEBUG_TRACE_DTS;
+
+#define RDD_PICO_A_DEBUG_TRACE_PTR()	( RDD_PICO_A_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + PICO_A_DEBUG_TRACE_ADDRESS )
+
+#endif
+/* COMMON_B */
+#if defined WL4908
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_RUNNER_B_SCRATCHPAD_DTS;
+
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_PTR()	( RDD_CPU_RX_RUNNER_B_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + CPU_RX_RUNNER_B_SCRATCHPAD_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+typedef struct
+{
+	RDD_BYTES_2_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SERVICE_QUEUES_TABLE_DTS;
+
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_PTR()	( RDD_WAN_TX_SERVICE_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_TX_SERVICE_QUEUES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE2    4
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_US_CONNECTION_BUFFER_TABLE_SIZE ][ RDD_US_CONNECTION_BUFFER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_BUFFER_TABLE_DTS;
+
+#define RDD_US_CONNECTION_BUFFER_TABLE_PTR()	( RDD_US_CONNECTION_BUFFER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_CONNECTION_BUFFER_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPV6_HOST_ADDRESS_CRC_TABLE_DTS;
+
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_PTR()	( RDD_IPV6_HOST_ADDRESS_CRC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + IPV6_HOST_ADDRESS_CRC_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_BACKUP_INFO_CACHE_ENTRY_DTS	entry[ RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_BACKUP_INFO_CACHE_TABLE_DTS;
+
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_PTR()	( RDD_DHD_BACKUP_INFO_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_BACKUP_INFO_CACHE_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_WAN_TX_QUEUES_TABLE_SIZE     256
+typedef struct
+{
+	RDD_WAN_TX_QUEUE_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_QUEUES_TABLE_DTS;
+
+#define RDD_WAN_TX_QUEUES_TABLE_PTR()	( RDD_WAN_TX_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_TX_QUEUES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_PTR()	( RDD_RUNNER_FWTRACE_MAINB_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_MAINB_BASE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+typedef struct
+{
+	RDD_CPU_RX_DESCRIPTOR_DTS	entry[ RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RING_PACKET_DESCRIPTORS_CACHE_DTS;
+
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_PTR()	( RDD_US_RING_PACKET_DESCRIPTORS_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_DTS	entry[ RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_DTS;
+
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_PTR()	( RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_FLOW_RING_CACHE_CTX_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE     4
+typedef struct
+{
+	RDD_FC_FLOW_IP_ADDRESSES_ENTRY_DTS	entry[ RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_FLOW_IP_ADDRESSES_TABLE_DTS;
+
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_PTR()	( RDD_FC_FLOW_IP_ADDRESSES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + FC_FLOW_IP_ADDRESSES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_PTR()	( RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_MAINB_CURR_OFFSET_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_RATE_CONTROLLERS_TABLE_SIZE     128
+typedef struct
+{
+	RDD_US_RATE_CONTROLLER_DESCRIPTOR_DTS	entry[ RDD_US_RATE_CONTROLLERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RATE_CONTROLLERS_TABLE_DTS;
+
+#define RDD_US_RATE_CONTROLLERS_TABLE_PTR()	( RDD_US_RATE_CONTROLLERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_RATE_CONTROLLERS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_DTS;
+
+#define RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR()	( RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE     3
+typedef struct
+{
+	RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_DTS	entry[ RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_DTS;
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_PTR()	( RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_RADIO_INSTANCE_COMMON_B_DATA_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     40
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_IPV4_HOST_ADDRESS_TABLE_SIZE     8
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_IPV4_HOST_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPV4_HOST_ADDRESS_TABLE_DTS;
+
+#define RDD_IPV4_HOST_ADDRESS_TABLE_PTR()	( RDD_IPV4_HOST_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + IPV4_HOST_ADDRESS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     40
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_DTS	entry[ RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS;
+
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_PTR()	( RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_MAIN_B_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_MAIN_B_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAIN_B_DEBUG_TRACE_DTS;
+
+#define RDD_MAIN_B_DEBUG_TRACE_PTR()	( RDD_MAIN_B_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + MAIN_B_DEBUG_TRACE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_PICO_B_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_PICO_B_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PICO_B_DEBUG_TRACE_DTS;
+
+#define RDD_PICO_B_DEBUG_TRACE_PTR()	( RDD_PICO_B_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + PICO_B_DEBUG_TRACE_ADDRESS - 0x8000 )
+
+#endif
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_PTR()	( RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS - 0x8000 )
+
+#if defined WL4908
+
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOB_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_PTR()	( RDD_RUNNER_FWTRACE_PICOB_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_PICOB_BASE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_BACKUP_INDEX_CACHE_DTS;
+
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_PTR()	( RDD_US_DHD_BACKUP_INDEX_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_DHD_BACKUP_INDEX_CACHE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_DOORBELL_COUNTERS_SIZE     48
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DHD_DOORBELL_COUNTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_DOORBELL_COUNTERS_DTS;
+
+#define RDD_DHD_DOORBELL_COUNTERS_PTR()	( RDD_DHD_DOORBELL_COUNTERS_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_DOORBELL_COUNTERS_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_WAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_ENQUEUE_INGRESS_QUEUE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_PTR()	( RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_ADDRESS - 0x8000 )
+
+#endif
+/* DDR */
+#if defined WL4908
+
+#define RDD_BPM_PACKET_BUFFERS_SIZE     7680
+typedef struct
+{
+	RDD_BPM_PACKET_BUFFER_DTS	entry[ RDD_BPM_PACKET_BUFFERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BPM_PACKET_BUFFERS_DTS;
+
+#endif
+
+typedef struct
+{
+	uint32_t	valid     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved  	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_extend	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	protocol  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_port  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dst_port  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_ip    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dst_ip    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NAT_CACHE_LKP_ENTRY_DTS;
+
+#define RDD_NAT_CACHE_LKP_ENTRY_VALID_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_NAT_CACHE_LKP_ENTRY_VALID_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_NAT_CACHE_LKP_ENTRY_KEY_EXTEND_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 2, 0, 4, r)
+#define RDD_NAT_CACHE_LKP_ENTRY_KEY_EXTEND_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 2, 0, 4, v)
+#define RDD_NAT_CACHE_LKP_ENTRY_PROTOCOL_READ(r, p)                   MREAD_8((uint8_t *)p + 3, r)
+#define RDD_NAT_CACHE_LKP_ENTRY_PROTOCOL_WRITE(v, p)                  MWRITE_8((uint8_t *)p + 3, v)
+#define RDD_NAT_CACHE_LKP_ENTRY_SRC_PORT_READ(r, p)                   MREAD_16((uint8_t *)p + 4, r)
+#define RDD_NAT_CACHE_LKP_ENTRY_SRC_PORT_WRITE(v, p)                  MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_NAT_CACHE_LKP_ENTRY_DST_PORT_READ(r, p)                   MREAD_16((uint8_t *)p + 6, r)
+#define RDD_NAT_CACHE_LKP_ENTRY_DST_PORT_WRITE(v, p)                  MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_NAT_CACHE_LKP_ENTRY_SRC_IP_READ(r, p)                     MREAD_32((uint8_t *)p + 8, r)
+#define RDD_NAT_CACHE_LKP_ENTRY_SRC_IP_WRITE(v, p)                    MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_NAT_CACHE_LKP_ENTRY_DST_IP_READ(r, p)                     MREAD_32((uint8_t *)p + 12, r)
+#define RDD_NAT_CACHE_LKP_ENTRY_DST_IP_WRITE(v, p)                    MWRITE_32((uint8_t *)p + 12, v)
+
+typedef struct
+{
+	uint32_t	valid       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1   	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_extend  	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	protocol    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2   	:23	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_pure_ack	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tos         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	src_mac_crc 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dst_mac_crc 	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NAT_CACHE_L2_LKP_ENTRY_DTS;
+
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_VALID_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_VALID_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_KEY_EXTEND_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 2, 0, 4, r)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_KEY_EXTEND_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 2, 0, 4, v)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_PROTOCOL_READ(r, p)                     MREAD_8((uint8_t *)p + 3, r)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_PROTOCOL_WRITE(v, p)                    MWRITE_8((uint8_t *)p + 3, v)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_TCP_PURE_ACK_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 6, 0, 1, r)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_TCP_PURE_ACK_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 6, 0, 1, v)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_TOS_READ(r, p)                          MREAD_8((uint8_t *)p + 7, r)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_TOS_WRITE(v, p)                         MWRITE_8((uint8_t *)p + 7, v)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_SRC_MAC_CRC_READ(r, p)                  MREAD_32((uint8_t *)p + 8, r)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_SRC_MAC_CRC_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_DST_MAC_CRC_READ(r, p)                  MREAD_32((uint8_t *)p + 12, r)
+#define RDD_NAT_CACHE_L2_LKP_ENTRY_DST_MAC_CRC_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_NUMBER	36
+
+typedef struct
+{
+	uint32_t	status_0                                                                  	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = status_0, size = 32 bits
+	uint32_t	reserved0                                                                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	natc_hit                                                                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                                                                 	:29	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	activity_status                                                           	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_hits                                                                 	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	flow_bytes                                                                	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast_flag                                                            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	context_continuation_flag                                                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_routed                                                                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_tos_mangle                                                             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_l2_accel                                                               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mtu                                                                       	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tos                                                                       	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_wred_high_prio                                                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_mapt_us                                                                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_df                                                                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	service_queue_id                                                          	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	drop                                                                      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_unicast_wfd_any                                                        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	priority                                                                  	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_prio                                                                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_idx                                                                   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_phy                                                                	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_addresses_table_index                                                  	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	link_specific_union                                                       	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_hit_trap                                                               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_ingqos_high_prio                                                       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_5                                                                	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cpu_reason                                                                	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pathstat_idx                                                              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_6                                                                	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pppoe_ses_id                                                              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	command_list[RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_NUMBER];
+	uint32_t	context_continuation_table_index                                          	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command_list_remaining_length                                             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_DTS;
+
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_STATUS_0_READ(r, p)                                         MREAD_32((uint8_t *)p, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_STATUS_0_WRITE(v, p)                                        MWRITE_32((uint8_t *)p, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_NATC_HIT_READ(r, p)                                         FIELD_MREAD_8((uint8_t *)p, 6, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_NATC_HIT_WRITE(v, p)                                        FIELD_MWRITE_8((uint8_t *)p, 6, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_ACTIVITY_STATUS_READ(r, p)                                  MREAD_8((uint8_t *)p, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_ACTIVITY_STATUS_WRITE(v, p)                                 MWRITE_8((uint8_t *)p, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_READ(r, p)                                        FIELD_MREAD_32((uint8_t *)p + 0, 0, 24, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_WRITE(v, p)                                       FIELD_MWRITE_32((uint8_t *)p + 0, 0, 24, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_READ(r, p)                                       MREAD_32((uint8_t *)p + 4, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_WRITE(v, p)                                      MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_FLAG_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 8, 6, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_FLAG_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_READ(r, p)                                        FIELD_MREAD_8((uint8_t *)p + 8, 5, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_WRITE(v, p)                                       FIELD_MWRITE_8((uint8_t *)p + 8, 5, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 8, 4, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 8, 4, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_L2_ACCEL_READ(r, p)                                      FIELD_MREAD_8((uint8_t *)p + 8, 3, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_L2_ACCEL_WRITE(v, p)                                     FIELD_MWRITE_8((uint8_t *)p + 8, 3, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_MTU_READ(r, p)                                              FIELD_MREAD_16((uint8_t *)p + 8, 0, 11, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_MTU_WRITE(v, p)                                             FIELD_MWRITE_16((uint8_t *)p + 8, 0, 11, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_TOS_READ(r, p)                                              MREAD_8((uint8_t *)p + 10, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_TOS_WRITE(v, p)                                             MWRITE_8((uint8_t *)p + 10, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_WRED_HIGH_PRIO_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 11, 7, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_WRED_HIGH_PRIO_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 11, 7, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_MAPT_US_READ(r, p)                                       FIELD_MREAD_8((uint8_t *)p + 11, 6, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_MAPT_US_WRITE(v, p)                                      FIELD_MWRITE_8((uint8_t *)p + 11, 6, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_DF_READ(r, p)                                            FIELD_MREAD_8((uint8_t *)p + 11, 5, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_DF_WRITE(v, p)                                           FIELD_MWRITE_8((uint8_t *)p + 11, 5, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_SERVICE_QUEUE_ID_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 11, 0, 5, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_SERVICE_QUEUE_ID_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 11, 0, 5, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_DROP_READ(r, p)                                             FIELD_MREAD_8((uint8_t *)p + 12, 7, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_DROP_WRITE(v, p)                                            FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_ANY_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 12, 6, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_ANY_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 12, 6, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_PRIORITY_READ(r, p)                                         FIELD_MREAD_8((uint8_t *)p + 12, 2, 4, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_PRIORITY_WRITE(v, p)                                        FIELD_MWRITE_8((uint8_t *)p + 12, 2, 4, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_WFD_PRIO_READ(r, p)                                         FIELD_MREAD_8((uint8_t *)p + 12, 1, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_WFD_PRIO_WRITE(v, p)                                        FIELD_MWRITE_8((uint8_t *)p + 12, 1, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_WFD_IDX_READ(r, p)                                          FIELD_MREAD_16((uint8_t *)p + 12, 7, 2, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_WFD_IDX_WRITE(v, p)                                         FIELD_MWRITE_16((uint8_t *)p + 12, 7, 2, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_EGRESS_PHY_READ(r, p)                                       FIELD_MREAD_8((uint8_t *)p + 13, 5, 2, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_EGRESS_PHY_WRITE(v, p)                                      FIELD_MWRITE_8((uint8_t *)p + 13, 5, 2, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IP_ADDRESSES_TABLE_INDEX_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 13, 2, 3, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IP_ADDRESSES_TABLE_INDEX_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 13, 2, 3, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_LINK_SPECIFIC_UNION_READ(r, p)                              FIELD_MREAD_32((uint8_t *)p + 12, 0, 18, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_LINK_SPECIFIC_UNION_WRITE(v, p)                             FIELD_MWRITE_32((uint8_t *)p + 12, 0, 18, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_HIT_TRAP_READ(r, p)                                      FIELD_MREAD_8((uint8_t *)p + 16, 7, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_HIT_TRAP_WRITE(v, p)                                     FIELD_MWRITE_8((uint8_t *)p + 16, 7, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_INGQOS_HIGH_PRIO_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 16, 6, 1, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_IS_INGQOS_HIGH_PRIO_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 16, 6, 1, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_CPU_REASON_READ(r, p)                                       FIELD_MREAD_8((uint8_t *)p + 18, 0, 6, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_CPU_REASON_WRITE(v, p)                                      FIELD_MWRITE_8((uint8_t *)p + 18, 0, 6, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_PATHSTAT_IDX_READ(r, p)                                     MREAD_8((uint8_t *)p + 19, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_PATHSTAT_IDX_WRITE(v, p)                                    MWRITE_8((uint8_t *)p + 19, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_PPPOE_SES_ID_READ(r, p)                                     MREAD_16((uint8_t *)p + 22, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_PPPOE_SES_ID_WRITE(v, p)                                    MWRITE_16((uint8_t *)p + 22, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_READ(r, p, i)                                  MREAD_I_8((uint8_t *)p + 24, i, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_WRITE(v, p, i)                                 MWRITE_I_8((uint8_t *)p + 24, i, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_TABLE_INDEX_READ(r, p)                 MREAD_16((uint8_t *)p + 60, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_TABLE_INDEX_WRITE(v, p)                MWRITE_16((uint8_t *)p + 60, v)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_REMAINING_LENGTH_READ(r, p)                    MREAD_16((uint8_t *)p + 62, r)
+#define RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_REMAINING_LENGTH_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 62, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_NUMBER	36
+
+typedef struct
+{
+	uint32_t	status_0                                                                     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = status_0, size = 32 bits
+	uint32_t	reserved0                                                                    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	natc_hit                                                                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                                                                    	:29	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	activity_status                                                              	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_hits                                                                    	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	flow_bytes                                                                   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast_flag                                                               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	context_continuation_flag                                                    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_routed                                                                    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_tos_mangle                                                                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_l2_accel                                                                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mtu                                                                          	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tos                                                                          	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_wred_high_prio                                                            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2                                                                    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	service_queue_id                                                             	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	drop                                                                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_unicast_wfd_any                                                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	priority                                                                     	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_prio                                                                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wfd_idx                                                                      	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_phy                                                                   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_addresses_table_index                                                     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	link_specific_union                                                          	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_hit_trap                                                                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_ingqos_high_prio                                                          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_5                                                                   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cpu_reason                                                                   	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pathstat_idx                                                                 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_6                                                                   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pppoe_ses_id                                                                 	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	command_list[RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_NUMBER];
+	uint32_t	context_continuation_table_index                                             	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command_list_remaining_length                                                	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_DTS;
+
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_STATUS_0_READ(r, p)                                         MREAD_32((uint8_t *)p, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_STATUS_0_WRITE(v, p)                                        MWRITE_32((uint8_t *)p, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_NATC_HIT_READ(r, p)                                         FIELD_MREAD_8((uint8_t *)p, 6, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_NATC_HIT_WRITE(v, p)                                        FIELD_MWRITE_8((uint8_t *)p, 6, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_ACTIVITY_STATUS_READ(r, p)                                  MREAD_8((uint8_t *)p, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_ACTIVITY_STATUS_WRITE(v, p)                                 MWRITE_8((uint8_t *)p, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_READ(r, p)                                        FIELD_MREAD_32((uint8_t *)p + 0, 0, 24, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_WRITE(v, p)                                       FIELD_MWRITE_32((uint8_t *)p + 0, 0, 24, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_READ(r, p)                                       MREAD_32((uint8_t *)p + 4, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_WRITE(v, p)                                      MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_FLAG_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 8, 6, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_FLAG_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_READ(r, p)                                        FIELD_MREAD_8((uint8_t *)p + 8, 5, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_WRITE(v, p)                                       FIELD_MWRITE_8((uint8_t *)p + 8, 5, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 8, 4, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 8, 4, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_L2_ACCEL_READ(r, p)                                      FIELD_MREAD_8((uint8_t *)p + 8, 3, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_L2_ACCEL_WRITE(v, p)                                     FIELD_MWRITE_8((uint8_t *)p + 8, 3, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_MTU_READ(r, p)                                              FIELD_MREAD_16((uint8_t *)p + 8, 0, 11, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_MTU_WRITE(v, p)                                             FIELD_MWRITE_16((uint8_t *)p + 8, 0, 11, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_TOS_READ(r, p)                                              MREAD_8((uint8_t *)p + 10, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_TOS_WRITE(v, p)                                             MWRITE_8((uint8_t *)p + 10, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_WRED_HIGH_PRIO_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 11, 7, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_WRED_HIGH_PRIO_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 11, 7, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_SERVICE_QUEUE_ID_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 11, 0, 5, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_SERVICE_QUEUE_ID_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 11, 0, 5, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_DROP_READ(r, p)                                             FIELD_MREAD_8((uint8_t *)p + 12, 7, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_DROP_WRITE(v, p)                                            FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_ANY_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 12, 6, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_UNICAST_WFD_ANY_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 12, 6, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_PRIORITY_READ(r, p)                                         FIELD_MREAD_8((uint8_t *)p + 12, 2, 4, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_PRIORITY_WRITE(v, p)                                        FIELD_MWRITE_8((uint8_t *)p + 12, 2, 4, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_WFD_PRIO_READ(r, p)                                         FIELD_MREAD_8((uint8_t *)p + 12, 1, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_WFD_PRIO_WRITE(v, p)                                        FIELD_MWRITE_8((uint8_t *)p + 12, 1, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_WFD_IDX_READ(r, p)                                          FIELD_MREAD_16((uint8_t *)p + 12, 7, 2, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_WFD_IDX_WRITE(v, p)                                         FIELD_MWRITE_16((uint8_t *)p + 12, 7, 2, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_EGRESS_PHY_READ(r, p)                                       FIELD_MREAD_8((uint8_t *)p + 13, 5, 2, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_EGRESS_PHY_WRITE(v, p)                                      FIELD_MWRITE_8((uint8_t *)p + 13, 5, 2, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IP_ADDRESSES_TABLE_INDEX_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 13, 2, 3, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IP_ADDRESSES_TABLE_INDEX_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 13, 2, 3, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_LINK_SPECIFIC_UNION_READ(r, p)                              FIELD_MREAD_32((uint8_t *)p + 12, 0, 18, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_LINK_SPECIFIC_UNION_WRITE(v, p)                             FIELD_MWRITE_32((uint8_t *)p + 12, 0, 18, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_HIT_TRAP_READ(r, p)                                      FIELD_MREAD_8((uint8_t *)p + 16, 7, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_HIT_TRAP_WRITE(v, p)                                     FIELD_MWRITE_8((uint8_t *)p + 16, 7, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_INGQOS_HIGH_PRIO_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 16, 6, 1, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_IS_INGQOS_HIGH_PRIO_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 16, 6, 1, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_CPU_REASON_READ(r, p)                                       FIELD_MREAD_8((uint8_t *)p + 18, 0, 6, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_CPU_REASON_WRITE(v, p)                                      FIELD_MWRITE_8((uint8_t *)p + 18, 0, 6, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_PATHSTAT_IDX_READ(r, p)                                     MREAD_8((uint8_t *)p + 19, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_PATHSTAT_IDX_WRITE(v, p)                                    MWRITE_8((uint8_t *)p + 19, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_PPPOE_SES_ID_READ(r, p)                                     MREAD_16((uint8_t *)p + 22, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_PPPOE_SES_ID_WRITE(v, p)                                    MWRITE_16((uint8_t *)p + 22, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_READ(r, p, i)                                  MREAD_I_8((uint8_t *)p + 24, i, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_WRITE(v, p, i)                                 MWRITE_I_8((uint8_t *)p + 24, i, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_TABLE_INDEX_READ(r, p)                 MREAD_16((uint8_t *)p + 60, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_TABLE_INDEX_WRITE(v, p)                MWRITE_16((uint8_t *)p + 60, v)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_REMAINING_LENGTH_READ(r, p)                    MREAD_16((uint8_t *)p + 62, r)
+#define RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_REMAINING_LENGTH_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 62, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_PORT_CONTEXT_NUMBER	8
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_L3_COMMAND_LIST_NUMBER	8
+
+typedef struct
+{
+	uint32_t	flow_hits                                                                      	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_bytes                                                                     	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast_flag                                                                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	context_continuation_flag                                                      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_routed                                                                      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_tos_mangle                                                                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	number_of_ports                                                                	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	port_mask                                                                      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2                                                                      	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mtu                                                                            	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tos                                                                            	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3                                                                      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wlan_mcast_clients                                                             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wlan_mcast_index                                                               	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mcast_port_header_buffer_ptr                                                   	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	port_context[RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_PORT_CONTEXT_NUMBER];
+	uint8_t	l3_command_list[RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_L3_COMMAND_LIST_NUMBER];
+	uint32_t	context_continuation_table_index                                               	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	command_list_remaining_length                                                  	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_DTS;
+
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_READ(r, p)                                        MREAD_32((uint8_t *)p, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_FLOW_HITS_WRITE(v, p)                                       MWRITE_32((uint8_t *)p, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_READ(r, p)                                       MREAD_32((uint8_t *)p + 4, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_FLOW_BYTES_WRITE(v, p)                                      MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_MULTICAST_FLAG_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_FLAG_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 8, 6, 1, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_FLAG_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_READ(r, p)                                        FIELD_MREAD_8((uint8_t *)p + 8, 5, 1, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_IS_ROUTED_WRITE(v, p)                                       FIELD_MWRITE_8((uint8_t *)p + 8, 5, 1, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 8, 4, 1, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_IS_TOS_MANGLE_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 8, 4, 1, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_NUMBER_OF_PORTS_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 8, 0, 4, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_NUMBER_OF_PORTS_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 8, 0, 4, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_PORT_MASK_READ(r, p)                                        MREAD_8((uint8_t *)p + 9, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_PORT_MASK_WRITE(v, p)                                       MWRITE_8((uint8_t *)p + 9, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_MTU_READ(r, p)                                              FIELD_MREAD_16((uint8_t *)p + 10, 0, 11, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_MTU_WRITE(v, p)                                             FIELD_MWRITE_16((uint8_t *)p + 10, 0, 11, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_TOS_READ(r, p)                                              MREAD_8((uint8_t *)p + 12, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_TOS_WRITE(v, p)                                             MWRITE_8((uint8_t *)p + 12, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_WLAN_MCAST_CLIENTS_READ(r, p)                               MREAD_8((uint8_t *)p + 14, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_WLAN_MCAST_CLIENTS_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 14, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_WLAN_MCAST_INDEX_READ(r, p)                                 MREAD_8((uint8_t *)p + 15, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_WLAN_MCAST_INDEX_WRITE(v, p)                                MWRITE_8((uint8_t *)p + 15, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_MCAST_PORT_HEADER_BUFFER_PTR_READ(r, p)                     MREAD_32((uint8_t *)p + 16, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_MCAST_PORT_HEADER_BUFFER_PTR_WRITE(v, p)                    MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_PORT_CONTEXT_READ(r, p, i)                                  MREAD_I_32((uint8_t *)p + 20, i, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_PORT_CONTEXT_WRITE(v, p, i)                                 MWRITE_I_32((uint8_t *)p + 20, i, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_L3_COMMAND_LIST_READ(r, p, i)                               MREAD_I_8((uint8_t *)p + 52, i, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_L3_COMMAND_LIST_WRITE(v, p, i)                              MWRITE_I_8((uint8_t *)p + 52, i, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_TABLE_INDEX_READ(r, p)                 MREAD_16((uint8_t *)p + 60, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_CONTEXT_CONTINUATION_TABLE_INDEX_WRITE(v, p)                MWRITE_16((uint8_t *)p + 60, v)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_REMAINING_LENGTH_READ(r, p)                    MREAD_16((uint8_t *)p + 62, r)
+#define RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_COMMAND_LIST_REMAINING_LENGTH_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 62, v)
+#if defined WL4908
+
+#define RDD_CONTEXT_CONTINUATION_TABLE_SIZE     65536
+typedef struct
+{
+	RDD_CONTEXT_CONTINUATION_ENTRY_DTS	entry[ RDD_CONTEXT_CONTINUATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONTEXT_CONTINUATION_TABLE_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE     8
+typedef struct
+{
+	RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_DTS	entry[ RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_R2D_WR_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_R2D_WR_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_R2D_WR_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_D2R_RD_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_D2R_RD_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_D2R_RD_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_R2D_RD_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_R2D_RD_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_R2D_RD_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_D2R_WR_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_D2R_WR_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_D2R_WR_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE     524288
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_BACKUP_QUEUES_BUFFER_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_DHD_LIST_ENTRY_ARRAY_DTS	entry[ RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_DHD_LIST_TABLE_DTS;
+
+#endif
+/* PSRAM */
+/* PRIVATE_A */
+#if defined WL4908_EAP
+
+#define RDD_INGRESS_HANDLER_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_IH_BUFFER_DTS	entry[ RDD_INGRESS_HANDLER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_HANDLER_BUFFER_DTS;
+
+#define RDD_INGRESS_HANDLER_BUFFER_PTR()	( RDD_INGRESS_HANDLER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + INGRESS_HANDLER_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+typedef struct
+{
+	uint32_t	reserved0            	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	wred_bit_reserved0   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tx_queue_reserved0   	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	egress_port_reserved0	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	header_number        	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	source_bridge_port   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length        	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	absolute_normal      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	misc                 	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = misc, size = 3 bits
+	uint32_t	last_indication      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	pti                  	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ring_id              	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	payload_offset       	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ddr_params           	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = ddr_params, size = 2 bits
+	uint32_t	ddr_id               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+	uint32_t	packet_location      	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+/* fields union = packet_location, size = 16 bits
+	uint32_t	buffer_number        	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2            	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	abs_address_index    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+ end fields union*/
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_TX_DESCRIPTOR_DTS;
+
+#define RDD_BBH_TX_DESCRIPTOR_WRED_BIT_RESERVED0_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p, 3, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_WRED_BIT_RESERVED0_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p, 3, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_TX_QUEUE_RESERVED0_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p, 0, 3, r)
+#define RDD_BBH_TX_DESCRIPTOR_TX_QUEUE_RESERVED0_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p, 0, 3, v)
+#define RDD_BBH_TX_DESCRIPTOR_EGRESS_PORT_RESERVED0_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 1, 3, 5, r)
+#define RDD_BBH_TX_DESCRIPTOR_EGRESS_PORT_RESERVED0_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 1, 3, 5, v)
+#define RDD_BBH_TX_DESCRIPTOR_HEADER_NUMBER_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 1, 0, 3, r)
+#define RDD_BBH_TX_DESCRIPTOR_HEADER_NUMBER_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 1, 0, 3, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_BRIDGE_PORT_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 2, 4, 4, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_BRIDGE_PORT_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 2, 4, 4, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p + 2, 0, 12, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p + 2, 0, 12, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABSOLUTE_NORMAL_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABSOLUTE_NORMAL_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_MISC_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 4, 4, 3, r)
+#define RDD_BBH_TX_DESCRIPTOR_MISC_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 4, 4, 3, v)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_INDICATION_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 4, 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_INDICATION_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 4, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_PTI_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 4, 4, 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_PTI_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 4, 4, 2, v)
+#define RDD_BBH_TX_DESCRIPTOR_RING_ID_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 4, 4, 3, r)
+#define RDD_BBH_TX_DESCRIPTOR_RING_ID_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 4, 4, 3, v)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_READ(r, p)                        FIELD_MREAD_16((uint8_t *)p + 4, 3, 9, r)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_WRITE(v, p)                       FIELD_MWRITE_16((uint8_t *)p + 4, 3, 9, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 5, 2, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 5, 2, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_DDR_PARAMS_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 5, 0, 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_DDR_PARAMS_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 5, 0, 2, v)
+#define RDD_BBH_TX_DESCRIPTOR_DDR_ID_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 5, 1, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_DDR_ID_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 5, 1, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LOCATION_READ(r, p)                       MREAD_16((uint8_t *)p + 6, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LOCATION_WRITE(v, p)                      MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                         MREAD_16((uint8_t *)p + 6, r)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_ADDRESS_INDEX_READ(r, p)                     FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_ADDRESS_INDEX_WRITE(v, p)                    FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_BUFFER_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CONTEXT_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_PTR()	( RDD_DS_CONNECTION_CONTEXT_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CONTEXT_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_PTR()	( RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE     64
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_REASON_TO_METER_TABLE_DTS;
+
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_PTR()	( RDD_DS_CPU_REASON_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_REASON_TO_METER_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_CPU_RX_METER_TABLE_PTR()	( RDD_DS_CPU_RX_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_METER_TABLE_ADDRESS )
+
+#define RDD_DS_POLICER_TABLE_PTR()	( RDD_DS_POLICER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_POLICER_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_IPSEC_DS_BUFFER_POOL_SIZE     2
+typedef struct
+{
+	RDD_IPSEC_DS_BUFFER_DTS	entry[ RDD_IPSEC_DS_BUFFER_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_BUFFER_POOL_DTS;
+
+#define RDD_IPSEC_DS_BUFFER_POOL_PTR()	( RDD_IPSEC_DS_BUFFER_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_BUFFER_POOL_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_IPSEC_DS_SA_DESC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_DTS	entry[ RDD_IPSEC_DS_SA_DESC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_SA_DESC_TABLE_DTS;
+
+#define RDD_IPSEC_DS_SA_DESC_TABLE_PTR()	( RDD_IPSEC_DS_SA_DESC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_SA_DESC_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_IPSEC_US_SA_DESC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_DTS	entry[ RDD_IPSEC_US_SA_DESC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_US_SA_DESC_TABLE_DTS;
+
+#define RDD_IPSEC_US_SA_DESC_TABLE_PTR()	( RDD_IPSEC_US_SA_DESC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_US_SA_DESC_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_SERVICE_QUEUES_RATE_LIMITER_DESCRIPTOR_DTS	entry[ RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_PTR()	( RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + SERVICE_QUEUES_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_TIMER_SCHEDULER_PRIMITIVE_ENTRY_DTS	entry[ RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_DTS;
+
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_PTR()	( RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS )
+
+#endif
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_PARAMETER_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE ][ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_RATE_LIMITER_REMAINDER_ENTRY_DTS	entry[ RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_LIMITER_REMAINDER_TABLE_DTS;
+
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_PTR()	( RDD_RATE_LIMITER_REMAINDER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RATE_LIMITER_REMAINDER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+typedef struct
+{
+	RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_FC_MCAST_CONNECTION2_TABLE_SIZE     128
+typedef struct
+{
+	RDD_FC_MCAST_CONNECTION2_ENTRY_DTS	entry[ RDD_FC_MCAST_CONNECTION2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_CONNECTION2_TABLE_DTS;
+
+#define RDD_FC_MCAST_CONNECTION2_TABLE_PTR()	( RDD_FC_MCAST_CONNECTION2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + FC_MCAST_CONNECTION2_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE     72
+typedef struct
+{
+	RDD_ETH_TX_QUEUE_POINTERS_ENTRY_DTS	entry[ RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_QUEUES_POINTERS_TABLE_DTS;
+
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_PTR()	( RDD_ETH_TX_QUEUES_POINTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_QUEUES_POINTERS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_WAN_FLOW_TABLE_SIZE     256
+typedef struct
+{
+	RDD_DS_WAN_FLOW_ENTRY_DTS	entry[ RDD_DS_WAN_FLOW_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_WAN_FLOW_TABLE_DTS;
+
+#define RDD_DS_WAN_FLOW_TABLE_PTR()	( RDD_DS_WAN_FLOW_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_WAN_FLOW_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+#define RDD_CONTEXT_CONTINUATION_ENTRY_COMMAND_LIST_NUMBER	68
+
+typedef struct
+{
+	uint32_t	valid                                                               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1                                                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	connection_direction                                                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	is_unicast_wfd_nic                                                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2                                                           	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	connection_table_index                                              	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3                                                           	:17	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	flow_index                                                          	:15	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	command_list[RDD_CONTEXT_CONTINUATION_ENTRY_COMMAND_LIST_NUMBER];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONTEXT_CONTINUATION_ENTRY_DTS;
+
+#define RDD_CONTEXT_CONTINUATION_ENTRY_VALID_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_VALID_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_CONNECTION_DIRECTION_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p, 5, 1, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_CONNECTION_DIRECTION_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p, 5, 1, v)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_IS_UNICAST_WFD_NIC_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p, 4, 1, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_IS_UNICAST_WFD_NIC_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p, 4, 1, v)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_CONNECTION_TABLE_INDEX_READ(r, p)                 MREAD_16((uint8_t *)p + 2, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_CONNECTION_TABLE_INDEX_WRITE(v, p)                MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_FLOW_INDEX_READ(r, p)                             FIELD_MREAD_16((uint8_t *)p + 6, 0, 15, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_FLOW_INDEX_WRITE(v, p)                            FIELD_MWRITE_16((uint8_t *)p + 6, 0, 15, v)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_COMMAND_LIST_READ(r, p, i)                        MREAD_I_8((uint8_t *)p + 8, i, r)
+#define RDD_CONTEXT_CONTINUATION_ENTRY_COMMAND_LIST_WRITE(v, p, i)                       MWRITE_I_8((uint8_t *)p + 8, i, v)
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONTEXT_CONTINUATION_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_PTR()	( RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CONTEXT_REMAINING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_LOOKUP_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE ][ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_FORWARDING_MATRIX_ENTRY_DTS	entry[ RDD_DS_FORWARDING_MATRIX_TABLE_SIZE ][ RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FORWARDING_MATRIX_TABLE_DTS;
+
+#define RDD_DS_FORWARDING_MATRIX_TABLE_PTR()	( RDD_DS_FORWARDING_MATRIX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FORWARDING_MATRIX_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_PTR()	( RDD_RUNNER_FWTRACE_MAINA_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RUNNER_FWTRACE_MAINA_PARAM_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_WAN_UDP_FILTER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DS_WAN_UDP_FILTER_ENTRY_DTS	entry[ RDD_DS_WAN_UDP_FILTER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_WAN_UDP_FILTER_TABLE_DTS;
+
+#define RDD_DS_WAN_UDP_FILTER_TABLE_PTR()	( RDD_DS_WAN_UDP_FILTER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_WAN_UDP_FILTER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_COMPLETE_RING_DESCRIPTOR_DTS	entry[ RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_DTS;
+
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_PTR()	( RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOA_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_PTR()	( RDD_RUNNER_FWTRACE_PICOA_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + RUNNER_FWTRACE_PICOA_PARAM_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_RATE_LIMITER_TABLE_SIZE     32
+typedef struct
+{
+	RDD_RATE_LIMITER_ENTRY_DTS	entry[ RDD_DS_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_DS_RATE_LIMITER_TABLE_PTR()	( RDD_DS_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_ETH_TX_QUEUES_TABLE_SIZE     72
+typedef struct
+{
+	RDD_ETH_TX_QUEUE_DESCRIPTOR_DTS	entry[ RDD_ETH_TX_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_QUEUES_TABLE_DTS;
+
+#define RDD_ETH_TX_QUEUES_TABLE_PTR()	( RDD_ETH_TX_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_QUEUES_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_HANDLER_SKB_DATA_POINTER_DTS;
+
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_PTR()	( RDD_INGRESS_HANDLER_SKB_DATA_POINTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE     8
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2    64
+typedef struct
+{
+	RDD_FC_MCAST_PORT_HEADER_ENTRY_DTS	entry[ RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE ][ RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_PORT_HEADER_BUFFER_DTS;
+
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_PTR()	( RDD_FC_MCAST_PORT_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + FC_MCAST_PORT_HEADER_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+typedef struct
+{
+	uint32_t	last_sbn        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_offset  	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	skip            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length   	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1       	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error_type      	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ih_buffer_number	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ddr_id          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number   	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_RX_DESCRIPTOR_DTS;
+
+#define RDD_BBH_RX_DESCRIPTOR_LAST_SBN_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p, 6, 10, r)
+#define RDD_BBH_RX_DESCRIPTOR_LAST_SBN_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p, 6, 10, v)
+#define RDD_BBH_RX_DESCRIPTOR_PAYLOAD_OFFSET_READ(r, p)                   FIELD_MREAD_32((uint8_t *)p + 0, 13, 9, r)
+#define RDD_BBH_RX_DESCRIPTOR_PAYLOAD_OFFSET_WRITE(v, p)                  FIELD_MWRITE_32((uint8_t *)p + 0, 13, 9, v)
+#define RDD_BBH_RX_DESCRIPTOR_SKIP_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 2, 4, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_SKIP_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 2, 4, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 2, 0, 12, r)
+#define RDD_BBH_RX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 2, 0, 12, v)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_TYPE_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 4, 1, 4, r)
+#define RDD_BBH_RX_DESCRIPTOR_ERROR_TYPE_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 4, 1, 4, v)
+#define RDD_BBH_RX_DESCRIPTOR_IH_BUFFER_NUMBER_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 4, 3, 6, r)
+#define RDD_BBH_RX_DESCRIPTOR_IH_BUFFER_NUMBER_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 4, 3, 6, v)
+#define RDD_BBH_RX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 5, 2, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 5, 2, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_DDR_ID_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 5, 1, 1, r)
+#define RDD_BBH_RX_DESCRIPTOR_DDR_ID_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 5, 1, 1, v)
+#define RDD_BBH_RX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                    MREAD_16((uint8_t *)p + 6, r)
+#define RDD_BBH_RX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 6, v)
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE     64
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_DTS;
+
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_PTR()	( RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_LAN_ENQUEUE_SQ_PD_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_MULTICAST_BUFFER_ENTRY_DTS	entry[ RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_DTS;
+
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_PTR()	( RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_SQ_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_CPU_TX_BBH_DESCRIPTORS_ENTRY_DTS	entry[ RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_TX_BBH_DESCRIPTORS_DTS;
+
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_PTR()	( RDD_DS_CPU_TX_BBH_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_TX_BBH_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+typedef struct
+{
+	uint32_t	reserved0    	:32	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_BPM_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_READ(r, p)                 FIELD_MREAD_32((uint8_t *)p + 4, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_WRITE(v, p)                FIELD_MWRITE_32((uint8_t *)p + 4, 0, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_L_READ( wv )               FIELD_GET( wv, 0, 18 )
+#define RDD_CPU_TX_DESCRIPTOR_BPM_BUFFER_NUMBER_L_WRITE( v, wv )           FIELD_SET( v, 0, 18, wv )
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_ETH_TX_LOCAL_REGISTERS_SIZE     9
+typedef struct
+{
+	RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_DTS	entry[ RDD_ETH_TX_LOCAL_REGISTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_LOCAL_REGISTERS_DTS;
+
+#define RDD_ETH_TX_LOCAL_REGISTERS_PTR()	( RDD_ETH_TX_LOCAL_REGISTERS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_LOCAL_REGISTERS_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     2
+typedef struct
+{
+	RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DTS	entry[ RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS;
+
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_PTR()	( RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_QUEUE_PROFILE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_QUEUE_PROFILE_DTS	entry[ RDD_DS_QUEUE_PROFILE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_QUEUE_PROFILE_TABLE_DTS;
+
+#define RDD_DS_QUEUE_PROFILE_TABLE_PTR()	( RDD_DS_QUEUE_PROFILE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_QUEUE_PROFILE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_SQ_ENQUEUE_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DS_SQ_ENQUEUE_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_SQ_ENQUEUE_QUEUE_DTS;
+
+#define RDD_DS_SQ_ENQUEUE_QUEUE_PTR()	( RDD_DS_SQ_ENQUEUE_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_SQ_ENQUEUE_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_PTR()	( RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_DTS;
+
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_PTR()	( RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_NULL_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_NULL_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_NULL_BUFFER_DTS;
+
+#define RDD_DS_NULL_BUFFER_PTR()	( RDD_DS_NULL_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_NULL_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_ROUTER_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_ROUTER_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_ROUTER_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_ROUTER_INGRESS_QUEUE_PTR()	( RDD_DS_ROUTER_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_ROUTER_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_GPE_COMMAND_PRIMITIVE_ENTRY_DTS	entry[ RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_DTS;
+
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_PTR()	( RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_DTS;
+
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_PTR()	( RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_RX_FAST_PD_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_PTR()	( RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_COMPLETE_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_COMPLETE_RING_ENTRY_DTS	entry[ RDD_DHD_COMPLETE_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_COMPLETE_RING_BUFFER_DTS;
+
+#define RDD_DHD_COMPLETE_RING_BUFFER_PTR()	( RDD_DHD_COMPLETE_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_COMPLETE_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_FAST_MALLOC_RESULT_TABLE_SIZE     2
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DS_FAST_MALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FAST_MALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DS_FAST_MALLOC_RESULT_TABLE_PTR()	( RDD_DS_FAST_MALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_MALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_PICO_MALLOC_RESULT_TABLE_SIZE     2
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DS_PICO_MALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PICO_MALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DS_PICO_MALLOC_RESULT_TABLE_PTR()	( RDD_DS_PICO_MALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_MALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE     4
+typedef struct
+{
+	RDD_DHD_L2_HEADER_BUFFER_ENTRY_DTS	entry[ RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_HEADER_SCRATCH_DTS;
+
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_PTR()	( RDD_DS_DHD_TX_POST_HEADER_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_HEADER_SCRATCH_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE     5
+typedef struct
+{
+	RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_DEBUG_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_DEBUG_BUFFER_ENTRY_DTS	entry[ RDD_DS_DEBUG_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DEBUG_BUFFER_DTS;
+
+#define RDD_DS_DEBUG_BUFFER_PTR()	( RDD_DS_DEBUG_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DEBUG_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry[ RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS;
+
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_PTR()	( RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DATA_POINTER_DUMMY_TARGET_DTS;
+
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_PTR()	( RDD_DS_DATA_POINTER_DUMMY_TARGET_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DATA_POINTER_DUMMY_TARGET_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_ENTRY_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR()	( RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS )
+
+#endif
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE     10
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_DTS;
+
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_PTR()	( RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_ABSOLUTE_TX_BBH_COUNTER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_FW_MAC_ADDRS_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_DS_FW_MAC_ADDRS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FW_MAC_ADDRS_DTS;
+
+#define RDD_DS_FW_MAC_ADDRS_PTR()	( RDD_DS_FW_MAC_ADDRS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FW_MAC_ADDRS_ADDRESS )
+
+#endif
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_PTR()	( RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_FLOW_RING_DROP_COUNTER_DTS;
+
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_PTR()	( RDD_DS_DHD_FLOW_RING_DROP_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_FLOW_RING_DROP_COUNTER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_TASK_REORDER_ENTRY_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_PTR()	( RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_PTR()	( RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_ETH_TX_SCRATCH_SIZE     16
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_ETH_TX_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_SCRATCH_DTS;
+
+#define RDD_ETH_TX_SCRATCH_PTR()	( RDD_ETH_TX_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_SCRATCH_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_RX_DIRECT_DESCRIPTORS_DTS;
+
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_PTR()	( RDD_GPON_RX_DIRECT_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GPON_RX_DIRECT_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_INGRESS_QUEUE_DTS;
+
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_PTR()	( RDD_DS_DHD_TX_POST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_GSO_TX_DHD_L2_BUFFER_SIZE     22
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_GSO_TX_DHD_L2_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_TX_DHD_L2_BUFFER_DTS;
+
+#define RDD_GSO_TX_DHD_L2_BUFFER_PTR()	( RDD_GSO_TX_DHD_L2_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_TX_DHD_L2_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_INGRESS_QUEUE_DTS;
+
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_PTR()	( RDD_WLAN_MCAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + WLAN_MCAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_CAM_DTS	entry[ RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_SA_DESC_CAM_TABLE_DTS;
+
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_PTR()	( RDD_IPSEC_DS_SA_DESC_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_SA_DESC_CAM_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE     16
+typedef struct
+{
+	RDD_IPSEC_SA_DESC_CAM_DTS	entry[ RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_US_SA_DESC_CAM_TABLE_DTS;
+
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_PTR()	( RDD_IPSEC_US_SA_DESC_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_US_SA_DESC_CAM_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_TX_DHD_L2_BUFFER_SIZE     22
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_L2_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_L2_BUFFER_DTS;
+
+#define RDD_CPU_TX_DHD_L2_BUFFER_PTR()	( RDD_CPU_TX_DHD_L2_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_DHD_L2_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS;
+
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_PTR()	( RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE     5
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_DTS;
+
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_PTR()	( RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE     4
+typedef struct
+{
+	RDD_HASH_BASED_FORWARDING_PORT_ENTRY_DTS	entry[ RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_HASH_BASED_FORWARDING_PORT_TABLE_DTS;
+
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_PTR()	( RDD_HASH_BASED_FORWARDING_PORT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + HASH_BASED_FORWARDING_PORT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_TX_DHD_HOST_BUF_PTR_DTS;
+
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_PTR()	( RDD_GSO_TX_DHD_HOST_BUF_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_TX_DHD_HOST_BUF_PTR_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_HOST_BUF_PTR_DTS;
+
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_PTR()	( RDD_CPU_TX_DHD_HOST_BUF_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_DHD_HOST_BUF_PTR_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_ETH_TX_MAC_TABLE_SIZE     8
+typedef struct
+{
+	RDD_ETH_TX_MAC_DESCRIPTOR_DTS	entry[ RDD_ETH_TX_MAC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH_TX_MAC_TABLE_DTS;
+
+#define RDD_ETH_TX_MAC_TABLE_PTR()	( RDD_ETH_TX_MAC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_MAC_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_RX_NORMAL_DESCRIPTORS_DTS;
+
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_PTR()	( RDD_GPON_RX_NORMAL_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GPON_RX_NORMAL_DESCRIPTORS_ADDRESS )
+
+#endif
+/* PRIVATE_B */
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_HANDLER_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_IH_BUFFER_DTS	entry[ RDD_US_INGRESS_HANDLER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_HANDLER_BUFFER_DTS;
+
+#define RDD_US_INGRESS_HANDLER_BUFFER_PTR()	( RDD_US_INGRESS_HANDLER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_HANDLER_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_PTR()	( RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_US_CPU_REASON_TO_METER_TABLE_SIZE     64
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_US_CPU_REASON_TO_METER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_REASON_TO_METER_TABLE_DTS;
+
+#define RDD_US_CPU_REASON_TO_METER_TABLE_PTR()	( RDD_US_CPU_REASON_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_REASON_TO_METER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_MAIN_PROFILING_BUFFER_RUNNER_DTS;
+
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_PTR()	( RDD_US_MAIN_PROFILING_BUFFER_RUNNER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_LOOKUP_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE ][ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_QUEUE_PROFILE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_QUEUE_PROFILE_DTS	entry[ RDD_US_QUEUE_PROFILE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_QUEUE_PROFILE_TABLE_DTS;
+
+#define RDD_US_QUEUE_PROFILE_TABLE_PTR()	( RDD_US_QUEUE_PROFILE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_QUEUE_PROFILE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WAN_CHANNELS_8_39_TABLE_SIZE     32
+typedef struct
+{
+	RDD_WAN_CHANNEL_8_39_DESCRIPTOR_DTS	entry[ RDD_WAN_CHANNELS_8_39_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_CHANNELS_8_39_TABLE_DTS;
+
+#define RDD_WAN_CHANNELS_8_39_TABLE_PTR()	( RDD_WAN_CHANNELS_8_39_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_CHANNELS_8_39_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_RUNNER_FLOW_HEADER_BUFFER_DTS	entry[ RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RUNNER_FLOW_HEADER_BUFFER_DTS;
+
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_PTR()	( RDD_US_RUNNER_FLOW_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RUNNER_FLOW_HEADER_BUFFER_ADDRESS )
+
+#endif
+#define RDD_US_POLICER_TABLE_PTR()	( RDD_US_POLICER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_POLICER_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE     2
+typedef struct
+{
+	RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_DTS;
+
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_PTR()	( RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_WAN_FLOW_TABLE_SIZE     256
+typedef struct
+{
+	RDD_US_WAN_FLOW_ENTRY_DTS	entry[ RDD_US_WAN_FLOW_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_WAN_FLOW_TABLE_DTS;
+
+#define RDD_US_WAN_FLOW_TABLE_PTR()	( RDD_US_WAN_FLOW_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_WAN_FLOW_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_CPU_TX_BBH_DESCRIPTORS_ENTRY_DTS	entry[ RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_BBH_DESCRIPTORS_DTS;
+
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_PTR()	( RDD_US_CPU_TX_BBH_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_BBH_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_FORWARDING_MATRIX_ENTRY_DTS	entry[ RDD_US_FORWARDING_MATRIX_TABLE_SIZE ][ RDD_US_FORWARDING_MATRIX_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FORWARDING_MATRIX_TABLE_DTS;
+
+#define RDD_US_FORWARDING_MATRIX_TABLE_PTR()	( RDD_US_FORWARDING_MATRIX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FORWARDING_MATRIX_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_TIMER_SCHEDULER_PRIMITIVE_ENTRY_DTS	entry[ RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_PTR()	( RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE     8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2    8
+typedef struct
+{
+	RDD_US_QUEUE_ENTRY_DTS	entry[ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE ][ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_DTS;
+
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_PTR()	( RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_TRAFFIC_CLASS_TO_QUEUE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS;
+
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_PTR()	( RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS )
+
+#endif
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_PTR()	( RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_US_RATE_LIMITER_TABLE_SIZE     16
+typedef struct
+{
+	RDD_RATE_LIMITER_ENTRY_DTS	entry[ RDD_US_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_US_RATE_LIMITER_TABLE_PTR()	( RDD_US_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_CPU_RX_METER_TABLE_PTR()	( RDD_US_CPU_RX_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_METER_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONNECTION_CONTEXT_BUFFER_ENTRY_DTS	entry[ RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_CONTEXT_BUFFER_DTS;
+
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_PTR()	( RDD_US_CONNECTION_CONTEXT_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CONNECTION_CONTEXT_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+typedef struct
+{
+	RDD_US_INGRESS_CLASSIFICATION_CONTEXT_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WAN_CHANNELS_0_7_TABLE_SIZE     8
+typedef struct
+{
+	RDD_WAN_CHANNEL_0_7_DESCRIPTOR_DTS	entry[ RDD_WAN_CHANNELS_0_7_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_CHANNELS_0_7_TABLE_DTS;
+
+#define RDD_WAN_CHANNELS_0_7_TABLE_PTR()	( RDD_WAN_CHANNELS_0_7_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_CHANNELS_0_7_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_DTS;
+
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_PTR()	( RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE     8
+typedef struct
+{
+	RDD_CONTEXT_CONTINUATION_ENTRY_DTS	entry[ RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_DTS;
+
+#define RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_PTR()	( RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CONNECTION_CONTEXT_REMAINING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+typedef struct
+{
+	RDD_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ENTRY_DTS	entry[ RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS;
+
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_PTR()	( RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+typedef struct
+{
+	RDD_INGRESS_FILTERS_PARAMETER_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE ][ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DHD_RX_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE     40
+typedef struct
+{
+	RDD_GPON_ABSOLUTE_TX_COUNTER_DTS	entry[ RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_DTS;
+
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_PTR()	( RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + GPON_ABSOLUTE_TX_BBH_COUNTER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE     5
+typedef struct
+{
+	RDD_INGRESS_RATE_LIMITER_ENTRY_DTS	entry[ RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_RATE_LIMITER_TABLE_DTS;
+
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_PTR()	( RDD_US_INGRESS_RATE_LIMITER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_RATE_LIMITER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_PTR()	( RDD_RUNNER_FWTRACE_MAINB_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + RUNNER_FWTRACE_MAINB_PARAM_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_RX_PICO_INGRESS_QUEUE_DTS;
+
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_PTR()	( RDD_US_CPU_RX_PICO_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CAPWAPR0_RX_DESCRIPTORS_SIZE     4
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_CAPWAPR0_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CAPWAPR0_RX_DESCRIPTORS_DTS;
+
+#define RDD_CAPWAPR0_RX_DESCRIPTORS_PTR()	( RDD_CAPWAPR0_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + CAPWAPR0_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_ROUTER_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_ROUTER_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_ROUTER_INGRESS_QUEUE_DTS;
+
+#define RDD_US_ROUTER_INGRESS_QUEUE_PTR()	( RDD_US_ROUTER_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_ROUTER_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CAPWAPR1_RX_DESCRIPTORS_SIZE     4
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_CAPWAPR1_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CAPWAPR1_RX_DESCRIPTORS_DTS;
+
+#define RDD_CAPWAPR1_RX_DESCRIPTORS_PTR()	( RDD_CAPWAPR1_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + CAPWAPR1_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_RX_FAST_INGRESS_QUEUE_DTS;
+
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_PTR()	( RDD_US_CPU_RX_FAST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CAPWAPR2_RX_DESCRIPTORS_SIZE     4
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_CAPWAPR2_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CAPWAPR2_RX_DESCRIPTORS_DTS;
+
+#define RDD_CAPWAPR2_RX_DESCRIPTORS_PTR()	( RDD_CAPWAPR2_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + CAPWAPR2_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_PTR()	( RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_FPM_ALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_DEBUG_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_DEBUG_BUFFER_ENTRY_DTS	entry[ RDD_US_DEBUG_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DEBUG_BUFFER_DTS;
+
+#define RDD_US_DEBUG_BUFFER_PTR()	( RDD_US_DEBUG_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DEBUG_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_FW_MAC_ADDRS_SIZE     16
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_US_FW_MAC_ADDRS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FW_MAC_ADDRS_DTS;
+
+#define RDD_US_FW_MAC_ADDRS_PTR()	( RDD_US_FW_MAC_ADDRS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FW_MAC_ADDRS_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_TX_POST_INGRESS_QUEUE_DTS;
+
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_PTR()	( RDD_US_DHD_TX_POST_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DHD_TX_POST_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE     48
+typedef struct
+{
+	RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_ENTRY_DTS	entry[ RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_DTS;
+
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_PTR()	( RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     6
+typedef struct
+{
+	RDD_INGRESS_FILTERS_CONFIGURATION_ENTRY_DTS	entry[ RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS;
+
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_PTR()	( RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE     3
+typedef struct
+{
+	RDD_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS	entry[ RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS;
+
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_PTR()	( RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+typedef struct
+{
+	RDD_GPE_COMMAND_PRIMITIVE_ENTRY_DTS	entry[ RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_DTS;
+
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_PTR()	( RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_FAST_MALLOC_RESULT_TABLE_SIZE     2
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_FAST_MALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FAST_MALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_FAST_MALLOC_RESULT_TABLE_PTR()	( RDD_US_FAST_MALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_MALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_PICO_MALLOC_RESULT_TABLE_SIZE     2
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_US_PICO_MALLOC_RESULT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PICO_MALLOC_RESULT_TABLE_DTS;
+
+#define RDD_US_PICO_MALLOC_RESULT_TABLE_PTR()	( RDD_US_PICO_MALLOC_RESULT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_MALLOC_RESULT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE     40
+typedef struct
+{
+	RDD_GPON_ABSOLUTE_TX_COUNTER_DTS	entry[ RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_DTS;
+
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_PTR()	( RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry[ RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS;
+
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_PTR()	( RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOB_PARAM_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_PTR()	( RDD_RUNNER_FWTRACE_PICOB_PARAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + RUNNER_FWTRACE_PICOB_PARAM_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_FLOW_RING_DROP_COUNTER_DTS;
+
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_PTR()	( RDD_US_DHD_FLOW_RING_DROP_COUNTER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_DHD_FLOW_RING_DROP_COUNTER_ADDRESS )
+
+#endif
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR()	( RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_PTR()	( RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE     32
+typedef struct
+{
+	RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DATA_POINTER_DUMMY_TARGET_SIZE     2
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DATA_POINTER_DUMMY_TARGET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DATA_POINTER_DUMMY_TARGET_DTS;
+
+#define RDD_DATA_POINTER_DUMMY_TARGET_PTR()	( RDD_DATA_POINTER_DUMMY_TARGET_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DATA_POINTER_DUMMY_TARGET_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_PTR()	( RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WAN_TX_SCRATCH_SIZE     24
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_WAN_TX_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SCRATCH_DTS;
+
+#define RDD_WAN_TX_SCRATCH_PTR()	( RDD_WAN_TX_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_TX_SCRATCH_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE     3
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2    6
+typedef struct
+{
+	RDD_CPU_REASON_TO_METER_ENTRY_DTS	entry[ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE ][ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_DTS;
+
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_PTR()	( RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE     9
+typedef struct
+{
+	RDD_BROADCOM_SWITCH_PORT_MAPPING_DTS	entry[ RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_DTS;
+
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_PTR()	( RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE     14
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_DTS;
+
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_PTR()	( RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + CPU_TX_DHD_LAYER2_HEADER_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_ENTRY_DTS	entry[ RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR()	( RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+typedef struct
+{
+	RDD_PARALLEL_PROCESSING_TASK_REORDER_ENTRY_DTS	entry[ RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_PTR()	( RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS;
+
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_PTR()	( RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS )
+
+#endif
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_PTR()	( RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_ETH2_RX_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_ETH2_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH2_RX_DESCRIPTORS_DTS;
+
+#define RDD_ETH2_RX_DESCRIPTORS_PTR()	( RDD_ETH2_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETH2_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_ETH1_RX_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_ETH1_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH1_RX_DESCRIPTORS_DTS;
+
+#define RDD_ETH1_RX_DESCRIPTORS_PTR()	( RDD_ETH1_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETH1_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_ETH0_RX_DESCRIPTORS_SIZE     32
+typedef struct
+{
+	RDD_ETH_RX_DESCRIPTORS_DTS	entry[ RDD_ETH0_RX_DESCRIPTORS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETH0_RX_DESCRIPTORS_DTS;
+
+#define RDD_ETH0_RX_DESCRIPTORS_PTR()	( RDD_ETH0_RX_DESCRIPTORS_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETH0_RX_DESCRIPTORS_ADDRESS )
+
+#endif
+/* COMMON_A */
+#if defined WL4908_EAP
+
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE     256
+typedef struct
+{
+	RDD_SIXTEEN_BYTES_DTS	entry[ RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_DTS;
+
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_PTR()	( RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DDR_CACHE_FIFO_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_PTR()	( RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + FC_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_PTR()	( RDD_CPU_RX_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + CPU_RX_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_DTS;
+
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR()	( RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_DTS;
+
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_PTR()	( RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_PTR()	( RDD_RUNNER_FWTRACE_MAINA_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_MAINA_BASE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOA_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_PTR()	( RDD_RUNNER_FWTRACE_PICOA_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_PICOA_BASE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_DHD_STATION_ENTRY_DTS	entry[ RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_DHD_STATION_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_PTR()	( RDD_WLAN_MCAST_DHD_STATION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_DHD_STATION_TABLE_ADDRESS )
+
+#endif
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_PTR()	( RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_MAC_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_ENTRY_DTS	entry[ RDD_MAC_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_TABLE_CAM_DTS;
+
+#define RDD_MAC_TABLE_CAM_PTR()	( RDD_MAC_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_TABLE_CAM_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_MAC_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_ENTRY_DTS	entry[ RDD_MAC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_TABLE_DTS;
+
+#define RDD_MAC_TABLE_PTR()	( RDD_MAC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+typedef struct
+{
+	uint32_t	reserved0         	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	payload_offset    	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	packet_length     	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved2         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error_type        	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	source_bridge_port	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_memory     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ddr_id            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved3         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	buffer_number     	:16	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETHWAN2_RX_DESCRIPTOR_DTS;
+
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PAYLOAD_OFFSET_READ(r, p)                     FIELD_MREAD_32((uint8_t *)p + 0, 13, 9, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PAYLOAD_OFFSET_WRITE(v, p)                    FIELD_MWRITE_32((uint8_t *)p + 0, 13, 9, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 2, 0, 12, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 2, 0, 12, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_TYPE_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 4, 1, 4, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_ERROR_TYPE_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 4, 1, 4, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_SOURCE_BRIDGE_PORT_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 4, 3, 6, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_SOURCE_BRIDGE_PORT_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 4, 3, 6, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_TARGET_MEMORY_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 5, 2, 1, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_TARGET_MEMORY_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 5, 2, 1, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_DDR_ID_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 5, 1, 1, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_DDR_ID_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 5, 1, 1, v)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_BUFFER_NUMBER_READ(r, p)                      MREAD_16((uint8_t *)p + 6, r)
+#define RDD_ETHWAN2_RX_DESCRIPTOR_BUFFER_NUMBER_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 6, v)
+#endif
+#if defined WL4908_EAP
+
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE     32
+typedef struct
+{
+	RDD_ETHWAN2_RX_DESCRIPTOR_DTS	entry[ RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_ETHWAN2_RX_INGRESS_QUEUE_DTS;
+
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_PTR()	( RDD_ETHWAN2_RX_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + ETHWAN2_RX_INGRESS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_TRACE_C_TABLE_SIZE     4
+typedef struct
+{
+	RDD_TRACE_C_ENTRY_DTS	entry[ RDD_TRACE_C_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TRACE_C_TABLE_DTS;
+
+#define RDD_TRACE_C_TABLE_PTR()	( RDD_TRACE_C_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + TRACE_C_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_PTR()	( RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RUNNER_FWTRACE_MAINA_CURR_OFFSET_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE     2
+typedef struct
+{
+	RDD_FREE_SKB_INDEXES_FIFO_TAIL_DTS	entry[ RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_DTS;
+
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_PTR()	( RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + FREE_SKB_INDEXES_DDR_FIFO_TAIL_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_MAC_CONTEXT_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_CONTEXT_ENTRY_DTS	entry[ RDD_MAC_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_CONTEXT_TABLE_DTS;
+
+#define RDD_MAC_CONTEXT_TABLE_PTR()	( RDD_MAC_CONTEXT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_CONTEXT_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE     32
+typedef struct
+{
+	RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_ENTRY_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+typedef struct
+{
+	RDD_BYTES_2_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WLAN_MCAST_FWD_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_FWD_ENTRY_DTS	entry[ RDD_WLAN_MCAST_FWD_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_FWD_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_FWD_TABLE_PTR()	( RDD_WLAN_MCAST_FWD_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_FWD_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DDR_QUEUE_DESCRIPTOR_DTS	entry[ RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_PTR()	( RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DESCRIPTOR_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE     48
+typedef struct
+{
+	RDD_WLAN_MCAST_SSID_MAC_ADDRESS_ENTRY_DTS	entry[ RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_PTR()	( RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE     8
+typedef struct
+{
+	RDD_DHD_BACKUP_ENTRY_DTS	entry[ RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_POST_REQUEST_QUEUE_DTS;
+
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_PTR()	( RDD_CPU_TX_POST_REQUEST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + CPU_TX_POST_REQUEST_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE     48
+typedef struct
+{
+	RDD_WLAN_MCAST_SSID_STATS_ENTRY_DTS	entry[ RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_SSID_STATS_TABLE_DTS;
+
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_PTR()	( RDD_WLAN_MCAST_SSID_STATS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + WLAN_MCAST_SSID_STATS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE     3
+typedef struct
+{
+	RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DTS	entry[ RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_DTS;
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_PTR()	( RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_RADIO_INSTANCE_COMMON_A_DATA_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_DTS	entry[ RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS;
+
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_PTR()	( RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE     128
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_DTS;
+
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_PTR()	( RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RATE_SHAPERS_STATUS_DESCRIPTOR_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE     16
+typedef struct
+{
+	RDD_INTERRUPT_COALESCING_CONFIG_DTS	entry[ RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INTERRUPT_COALESCING_CONFIG_TABLE_DTS;
+
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_PTR()	( RDD_INTERRUPT_COALESCING_CONFIG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + INTERRUPT_COALESCING_CONFIG_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2    4
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_DS_CONNECTION_BUFFER_TABLE_SIZE ][ RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_CONNECTION_BUFFER_TABLE_DTS;
+
+#define RDD_DS_CONNECTION_BUFFER_TABLE_PTR()	( RDD_DS_CONNECTION_BUFFER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_CONNECTION_BUFFER_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_MAC_CONTEXT_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_CONTEXT_ENTRY_DTS	entry[ RDD_MAC_CONTEXT_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_CONTEXT_TABLE_CAM_DTS;
+
+#define RDD_MAC_CONTEXT_TABLE_CAM_PTR()	( RDD_MAC_CONTEXT_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_CONTEXT_TABLE_CAM_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_DOORBELL_WRITE_VALUES_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_DHD_DOORBELL_WRITE_VALUES_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_DOORBELL_WRITE_VALUES_DTS;
+
+#define RDD_DHD_DOORBELL_WRITE_VALUES_PTR()	( RDD_DHD_DOORBELL_WRITE_VALUES_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_DOORBELL_WRITE_VALUES_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_BACKUP_INDEX_CACHE_DTS;
+
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_PTR()	( RDD_DS_DHD_BACKUP_INDEX_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_DHD_BACKUP_INDEX_CACHE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+typedef struct
+{
+	RDD_CPU_RX_DESCRIPTOR_DTS	entry[ RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_DTS;
+
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_PTR()	( RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_RING_DESCRIPTORS_TABLE_SIZE     16
+typedef struct
+{
+	RDD_RING_DESCRIPTOR_DTS	entry[ RDD_RING_DESCRIPTORS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RING_DESCRIPTORS_TABLE_DTS;
+
+#define RDD_RING_DESCRIPTORS_TABLE_PTR()	( RDD_RING_DESCRIPTORS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + RING_DESCRIPTORS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE     32
+typedef struct
+{
+	RDD_DDR_QUEUE_ADDRESS_ENTRY_DTS	entry[ RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_DTS;
+
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_PTR()	( RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_MAC_EXTENSION_TABLE_SIZE     64
+typedef struct
+{
+	RDD_MAC_EXTENSION_ENTRY_DTS	entry[ RDD_MAC_EXTENSION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_EXTENSION_TABLE_DTS;
+
+#define RDD_MAC_EXTENSION_TABLE_PTR()	( RDD_MAC_EXTENSION_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_EXTENSION_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE     16
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_DTS;
+
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_PTR()	( RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_MAC_EXTENSION_TABLE_CAM_SIZE     32
+typedef struct
+{
+	RDD_MAC_EXTENSION_ENTRY_DTS	entry[ RDD_MAC_EXTENSION_TABLE_CAM_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_EXTENSION_TABLE_CAM_DTS;
+
+#define RDD_MAC_EXTENSION_TABLE_CAM_PTR()	( RDD_MAC_EXTENSION_TABLE_CAM_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAC_EXTENSION_TABLE_CAM_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE     3
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TX_CPL_DHD_DMA_SCRATCH_DTS;
+
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_PTR()	( RDD_TX_CPL_DHD_DMA_SCRATCH_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + TX_CPL_DHD_DMA_SCRATCH_ADDRESS )
+
+#endif
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_PTR()	( RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS )
+
+#if defined WL4908_EAP
+
+#define RDD_MAIN_A_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_MAIN_A_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAIN_A_DEBUG_TRACE_DTS;
+
+#define RDD_MAIN_A_DEBUG_TRACE_PTR()	( RDD_MAIN_A_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + MAIN_A_DEBUG_TRACE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_PICO_A_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_PICO_A_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PICO_A_DEBUG_TRACE_DTS;
+
+#define RDD_PICO_A_DEBUG_TRACE_PTR()	( RDD_PICO_A_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + PICO_A_DEBUG_TRACE_ADDRESS )
+
+#endif
+/* COMMON_B */
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LONG_LOOKUP_ENTRY_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_RUNNER_B_SCRATCHPAD_DTS;
+
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_PTR()	( RDD_CPU_RX_RUNNER_B_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + CPU_RX_RUNNER_B_SCRATCHPAD_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+typedef struct
+{
+	RDD_BYTES_2_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     32
+typedef struct
+{
+	RDD_BBH_RX_DESCRIPTOR_DTS	entry[ RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WAN_TX_SERVICE_QUEUE_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_SERVICE_QUEUES_TABLE_DTS;
+
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_PTR()	( RDD_WAN_TX_SERVICE_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_TX_SERVICE_QUEUES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE2    4
+typedef struct
+{
+	RDD_CONNECTION_ENTRY_DTS	entry[ RDD_US_CONNECTION_BUFFER_TABLE_SIZE ][ RDD_US_CONNECTION_BUFFER_TABLE_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CONNECTION_BUFFER_TABLE_DTS;
+
+#define RDD_US_CONNECTION_BUFFER_TABLE_PTR()	( RDD_US_CONNECTION_BUFFER_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_CONNECTION_BUFFER_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE     16
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPV6_HOST_ADDRESS_CRC_TABLE_DTS;
+
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_PTR()	( RDD_IPV6_HOST_ADDRESS_CRC_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + IPV6_HOST_ADDRESS_CRC_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_BACKUP_INFO_CACHE_ENTRY_DTS	entry[ RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_BACKUP_INFO_CACHE_TABLE_DTS;
+
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_PTR()	( RDD_DHD_BACKUP_INFO_CACHE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_BACKUP_INFO_CACHE_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WAN_TX_QUEUES_TABLE_SIZE     256
+typedef struct
+{
+	RDD_WAN_TX_QUEUE_DESCRIPTOR_DTS	entry[ RDD_WAN_TX_QUEUES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_QUEUES_TABLE_DTS;
+
+#define RDD_WAN_TX_QUEUES_TABLE_PTR()	( RDD_WAN_TX_QUEUES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_TX_QUEUES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_PTR()	( RDD_RUNNER_FWTRACE_MAINB_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_MAINB_BASE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+typedef struct
+{
+	RDD_CPU_RX_DESCRIPTOR_DTS	entry[ RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RING_PACKET_DESCRIPTORS_CACHE_DTS;
+
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_PTR()	( RDD_US_RING_PACKET_DESCRIPTORS_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_CTX_ENTRY_DTS	entry[ RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_DTS;
+
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_PTR()	( RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_FLOW_RING_CACHE_CTX_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE     4
+typedef struct
+{
+	RDD_FC_FLOW_IP_ADDRESSES_ENTRY_DTS	entry[ RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_FC_FLOW_IP_ADDRESSES_TABLE_DTS;
+
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_PTR()	( RDD_FC_FLOW_IP_ADDRESSES_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + FC_FLOW_IP_ADDRESSES_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE     2
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_DTS;
+
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_PTR()	( RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_MAINB_CURR_OFFSET_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_RATE_CONTROLLERS_TABLE_SIZE     128
+typedef struct
+{
+	RDD_US_RATE_CONTROLLER_DESCRIPTOR_DTS	entry[ RDD_US_RATE_CONTROLLERS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RATE_CONTROLLERS_TABLE_DTS;
+
+#define RDD_US_RATE_CONTROLLERS_TABLE_PTR()	( RDD_US_RATE_CONTROLLERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_RATE_CONTROLLERS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE     8
+typedef struct
+{
+	RDD_RUNNER_SCRATCHPAD_DTS	entry[ RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_DTS;
+
+#define RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR()	( RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE     3
+typedef struct
+{
+	RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_DTS	entry[ RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_DTS;
+
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_PTR()	( RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_RADIO_INSTANCE_COMMON_B_DATA_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     40
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_IPV4_HOST_ADDRESS_TABLE_SIZE     8
+typedef struct
+{
+	RDD_FOUR_BYTES_DTS	entry[ RDD_IPV4_HOST_ADDRESS_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPV4_HOST_ADDRESS_TABLE_DTS;
+
+#define RDD_IPV4_HOST_ADDRESS_TABLE_PTR()	( RDD_IPV4_HOST_ADDRESS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + IPV4_HOST_ADDRESS_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     40
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS;
+
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_PTR()	( RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+typedef struct
+{
+	RDD_DHD_FLOW_RING_CACHE_LKP_ENTRY_DTS	entry[ RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS;
+
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_PTR()	( RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_MAIN_B_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_MAIN_B_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAIN_B_DEBUG_TRACE_DTS;
+
+#define RDD_MAIN_B_DEBUG_TRACE_PTR()	( RDD_MAIN_B_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + MAIN_B_DEBUG_TRACE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_PICO_B_DEBUG_TRACE_SIZE     512
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_PICO_B_DEBUG_TRACE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PICO_B_DEBUG_TRACE_DTS;
+
+#define RDD_PICO_B_DEBUG_TRACE_PTR()	( RDD_PICO_B_DEBUG_TRACE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + PICO_B_DEBUG_TRACE_ADDRESS - 0x8000 )
+
+#endif
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_PTR()	( RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS - 0x8000 )
+
+#if defined WL4908_EAP
+
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE     128
+typedef struct
+{
+	RDD_EIGHT_BYTES_DTS	entry[ RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RUNNER_FWTRACE_PICOB_BASE_DTS;
+
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_PTR()	( RDD_RUNNER_FWTRACE_PICOB_BASE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + RUNNER_FWTRACE_PICOB_BASE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE     32
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_DHD_BACKUP_INDEX_CACHE_DTS;
+
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_PTR()	( RDD_US_DHD_BACKUP_INDEX_CACHE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_DHD_BACKUP_INDEX_CACHE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_DOORBELL_COUNTERS_SIZE     48
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_DHD_DOORBELL_COUNTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_DOORBELL_COUNTERS_DTS;
+
+#define RDD_DHD_DOORBELL_COUNTERS_PTR()	( RDD_DHD_DOORBELL_COUNTERS_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DHD_DOORBELL_COUNTERS_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_INGRESS_QUEUE_ENTRY_DTS	entry[ RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_ENQUEUE_INGRESS_QUEUE_DTS;
+
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_PTR()	( RDD_WAN_ENQUEUE_INGRESS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + WAN_ENQUEUE_INGRESS_QUEUE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE     4
+typedef struct
+{
+	RDD_ONE_BYTE_DTS	entry[ RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_DTS;
+
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_PTR()	( RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_ADDRESS - 0x8000 )
+
+#endif
+/* DDR */
+#if defined WL4908_EAP
+
+#define RDD_BPM_PACKET_BUFFERS_SIZE     7680
+typedef struct
+{
+	RDD_BPM_PACKET_BUFFER_DTS	entry[ RDD_BPM_PACKET_BUFFERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BPM_PACKET_BUFFERS_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CONTEXT_CONTINUATION_TABLE_SIZE     65536
+typedef struct
+{
+	RDD_CONTEXT_CONTINUATION_ENTRY_DTS	entry[ RDD_CONTEXT_CONTINUATION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONTEXT_CONTINUATION_TABLE_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE     8
+typedef struct
+{
+	RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_DTS	entry[ RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_R2D_WR_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_R2D_WR_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_R2D_WR_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_D2R_RD_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_D2R_RD_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_D2R_RD_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_R2D_RD_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_R2D_RD_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_R2D_RD_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_D2R_WR_ARR_DDR_BUFFER_SIZE     128
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_D2R_WR_ARR_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_D2R_WR_ARR_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE     524288
+typedef struct
+{
+	RDD_TWO_BYTES_DTS	entry[ RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_BACKUP_QUEUES_BUFFER_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE     64
+typedef struct
+{
+	RDD_WLAN_MCAST_DHD_LIST_ENTRY_ARRAY_DTS	entry[ RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_WLAN_MCAST_DHD_LIST_TABLE_DTS;
+
+#endif
+/* PSRAM */
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_BBH_TX_DESCRIPTOR_DTS        bbh_tx_descriptor;
+	RDD_PACKET_DESCRIPTOR_DTS        packet_descriptor;
+	RDD_SERVICE_QUEUE_DESCRIPTOR_DTS service_queue_descriptor;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_PACKET_DESCRIPTOR_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE     2048
+typedef struct
+{
+	RDD_DS_PACKET_DESCRIPTOR_UNION_DTS	entry[ RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_DTS;
+
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_PTR()	( RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE     2048
+typedef struct
+{
+	RDD_DS_PACKET_DESCRIPTOR_UNION_DTS	entry[ RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_DTS;
+
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_PTR()	( RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE     2048
+typedef struct
+{
+	RDD_DS_PACKET_DESCRIPTOR_UNION_DTS	entry[ RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_DTS;
+
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_PTR()	( RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE     2048
+typedef struct
+{
+	RDD_DS_PACKET_DESCRIPTOR_UNION_DTS	entry[ RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_DTS;
+
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_PTR()	( RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS )
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_CPU_TX_DESCRIPTOR_DS_FAST_DTS      cpu_tx_descriptor_ds_fast;
+	RDD_CPU_TX_MESSAGE_DESCRIPTOR_DTS      cpu_tx_message_descriptor;
+	RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_DTS cpu_tx_descriptor_ds_pico_wifi;
+	RDD_CPU_TX_DESCRIPTOR_ABS_DTS          cpu_tx_descriptor_abs;
+	RDD_CPU_TX_DESCRIPTOR_CORE_DTS         cpu_tx_descriptor_core;
+	RDD_CPU_TX_DESCRIPTOR_US_FAST_DTS      cpu_tx_descriptor_us_fast;
+	RDD_CPU_TX_DESCRIPTOR_DS_PICO_DTS      cpu_tx_descriptor_ds_pico;
+	RDD_CPU_TX_DESCRIPTOR_BPM_DTS          cpu_tx_descriptor_bpm;
+	RDD_CPU_TX_DESCRIPTOR_DTS              cpu_tx_descriptor;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_PICO_DESCRIPTOR_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_GSO_PICO_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_GSO_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_GSO_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_PICO_QUEUE_DTS;
+
+#define RDD_GSO_PICO_QUEUE_PTR()	( RDD_GSO_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_GSO_PICO_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_GSO_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_GSO_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_PICO_QUEUE_DTS;
+
+#define RDD_GSO_PICO_QUEUE_PTR()	( RDD_GSO_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_GSO_PICO_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_GSO_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_GSO_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_PICO_QUEUE_DTS;
+
+#define RDD_GSO_PICO_QUEUE_PTR()	( RDD_GSO_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_GSO_PICO_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_GSO_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_GSO_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_GSO_PICO_QUEUE_DTS;
+
+#define RDD_GSO_PICO_QUEUE_PTR()	( RDD_GSO_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + GSO_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DTS dhd_tx_post_descriptor_cwi32;
+	RDD_DHD_TX_POST_DESCRIPTOR_DTS       dhd_tx_post_descriptor;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_DDR_BUFFER_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE     8
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE2    16
+typedef struct
+{
+	RDD_DHD_TX_POST_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_POST_DDR_BUFFER_SIZE ][ RDD_DHD_TX_POST_DDR_BUFFER_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE     8
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE2    16
+typedef struct
+{
+	RDD_DHD_TX_POST_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_POST_DDR_BUFFER_SIZE ][ RDD_DHD_TX_POST_DDR_BUFFER_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE     8
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE2    16
+typedef struct
+{
+	RDD_DHD_TX_POST_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_POST_DDR_BUFFER_SIZE ][ RDD_DHD_TX_POST_DDR_BUFFER_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE     8
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE2    16
+typedef struct
+{
+	RDD_DHD_TX_POST_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_POST_DDR_BUFFER_SIZE ][ RDD_DHD_TX_POST_DDR_BUFFER_SIZE2 ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_DTS dhd_tx_complete_descriptor_cwi32;
+	RDD_DHD_TX_COMPLETE_DESCRIPTOR_DTS       dhd_tx_complete_descriptor;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_DDR_BUFFER_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE     16
+typedef struct
+{
+	RDD_DHD_TX_COMPLETE_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE     16
+typedef struct
+{
+	RDD_DHD_TX_COMPLETE_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE     16
+typedef struct
+{
+	RDD_DHD_TX_COMPLETE_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE     16
+typedef struct
+{
+	RDD_DHD_TX_COMPLETE_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_CPU_TX_DESCRIPTOR_DS_FAST_DTS                      cpu_tx_descriptor_ds_fast;
+	RDD_CPU_TX_MESSAGE_DESCRIPTOR_DTS                      cpu_tx_message_descriptor;
+	RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_DTS                 cpu_tx_descriptor_ds_pico_wifi;
+	RDD_CPU_TX_DESCRIPTOR_ABS_DTS                          cpu_tx_descriptor_abs;
+	RDD_CPU_TX_UPDATE_PD_POOL_QUOTA_MESSAGE_DESCRIPTOR_DTS cpu_tx_update_pd_pool_quota_message_descriptor;
+	RDD_CPU_TX_DESCRIPTOR_CORE_DTS                         cpu_tx_descriptor_core;
+	RDD_CPU_TX_DESCRIPTOR_US_FAST_DTS                      cpu_tx_descriptor_us_fast;
+	RDD_CPU_TX_DHD_DESCRIPTOR_DTS                          cpu_tx_dhd_descriptor;
+	RDD_CPU_TX_DESCRIPTOR_DS_PICO_DTS                      cpu_tx_descriptor_ds_pico;
+	RDD_CPU_TX_DESCRIPTOR_BPM_DTS                          cpu_tx_descriptor_bpm;
+	RDD_CPU_TX_DESCRIPTOR_DTS                              cpu_tx_descriptor;
+	RDD_CPU_TX_DHD_MESSAGE_DESCRIPTOR_DTS                  cpu_tx_dhd_message_descriptor;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_PICO_DESCRIPTOR_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CPU_TX_PICO_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_CPU_TX_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_PICO_QUEUE_DTS;
+
+#define RDD_CPU_TX_PICO_QUEUE_PTR()	( RDD_CPU_TX_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_CPU_TX_PICO_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_US_CPU_TX_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_PICO_QUEUE_DTS;
+
+#define RDD_US_CPU_TX_PICO_QUEUE_PTR()	( RDD_US_CPU_TX_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_TX_PICO_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_CPU_TX_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_PICO_QUEUE_DTS;
+
+#define RDD_CPU_TX_PICO_QUEUE_PTR()	( RDD_CPU_TX_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_CPU_TX_PICO_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_US_CPU_TX_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_PICO_QUEUE_DTS;
+
+#define RDD_US_CPU_TX_PICO_QUEUE_PTR()	( RDD_US_CPU_TX_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_TX_PICO_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_CPU_TX_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_PICO_QUEUE_DTS;
+
+#define RDD_CPU_TX_PICO_QUEUE_PTR()	( RDD_CPU_TX_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_CPU_TX_PICO_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_US_CPU_TX_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_PICO_QUEUE_DTS;
+
+#define RDD_US_CPU_TX_PICO_QUEUE_PTR()	( RDD_US_CPU_TX_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_TX_PICO_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_CPU_TX_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_PICO_QUEUE_DTS;
+
+#define RDD_CPU_TX_PICO_QUEUE_PTR()	( RDD_CPU_TX_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_CPU_TX_PICO_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_PICO_DESCRIPTOR_UNION_DTS	entry[ RDD_US_CPU_TX_PICO_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_PICO_QUEUE_DTS;
+
+#define RDD_US_CPU_TX_PICO_QUEUE_PTR()	( RDD_US_CPU_TX_PICO_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_PICO_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_DTS        ingress_classification_short_lookup_entry;
+	RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_DTS        ds_ingress_classification_ih_lookup_entry;
+	RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_DTS ds_ingress_classification_optimized_lookup_entry;
+	RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_DTS us_ingress_classification_optimized_lookup_entry;
+	RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_DTS        us_ingress_classification_ih_lookup_entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_CLASSIFICATION_LOOKUP_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_UNION_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_UNION_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_UNION_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_UNION_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_UNION_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_UNION_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_UNION_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_UNION_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_DHD_RX_COMPLETE_DESCRIPTOR_DTS       dhd_rx_complete_descriptor;
+	RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_DTS dhd_rx_complete_descriptor_cwi32;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_COMPLETE_DDR_BUFFER_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE     1024
+typedef struct
+{
+	RDD_DHD_RX_COMPLETE_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_COMPLETE_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE     1024
+typedef struct
+{
+	RDD_DHD_RX_COMPLETE_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_COMPLETE_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE     1024
+typedef struct
+{
+	RDD_DHD_RX_COMPLETE_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_COMPLETE_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE     1024
+typedef struct
+{
+	RDD_DHD_RX_COMPLETE_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_COMPLETE_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_NAT_CACHE_LKP_ENTRY_DTS    nat_cache_lkp_entry;
+	RDD_NAT_CACHE_L2_LKP_ENTRY_DTS nat_cache_l2_lkp_entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NAT_CACHE_LKUP_EXTENSION_ENTRY_UNION_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_NAT_CACHE_EXTENSION_TABLE_SIZE     7
+typedef struct
+{
+	RDD_NAT_CACHE_LKUP_EXTENSION_ENTRY_UNION_DTS	entry[ RDD_NAT_CACHE_EXTENSION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NAT_CACHE_EXTENSION_TABLE_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_NAT_CACHE_EXTENSION_TABLE_SIZE     7
+typedef struct
+{
+	RDD_NAT_CACHE_LKUP_EXTENSION_ENTRY_UNION_DTS	entry[ RDD_NAT_CACHE_EXTENSION_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NAT_CACHE_EXTENSION_TABLE_DTS;
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_INGRESS_CLASSIFICATION_SHORT_LOOKUP_ENTRY_DTS        ingress_classification_short_lookup_entry;
+	RDD_DS_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_DTS        ds_ingress_classification_ih_lookup_entry;
+	RDD_DS_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_DTS ds_ingress_classification_optimized_lookup_entry;
+	RDD_US_INGRESS_CLASSIFICATION_OPTIMIZED_LOOKUP_ENTRY_DTS us_ingress_classification_optimized_lookup_entry;
+	RDD_US_INGRESS_CLASSIFICATION_IH_LOOKUP_ENTRY_DTS        us_ingress_classification_ih_lookup_entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_CLASSIFICATION_LOOKUP_CAM_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_CAM_UNION_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_CAM_UNION_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_CAM_UNION_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_CAM_UNION_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_CAM_UNION_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_CAM_UNION_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_CAM_UNION_DTS	entry[ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS;
+
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_PTR()	( RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+typedef struct
+{
+	RDD_INGRESS_CLASSIFICATION_LOOKUP_CAM_UNION_DTS	entry[ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS;
+
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_PTR()	( RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS - 0x8000 )
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_DHD_RX_COMPLETE_DESCRIPTOR_DTS       dhd_rx_complete_descriptor;
+	RDD_DHD_RX_POST_DESCRIPTOR_CWI32_DTS     dhd_rx_post_descriptor_cwi32;
+	RDD_DHD_RX_POST_DESCRIPTOR_DTS           dhd_rx_post_descriptor;
+	RDD_DHD_RX_COMPLETE_DESCRIPTOR_CWI32_DTS dhd_rx_complete_descriptor_cwi32;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_FLOW_RING_BUFFER_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_PTR()	( RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DHD_RX_COMPLETE_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_POST_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_PTR()	( RDD_DHD_RX_POST_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DHD_RX_POST_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_PTR()	( RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DHD_RX_COMPLETE_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_POST_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_PTR()	( RDD_DHD_RX_POST_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DHD_RX_POST_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_PTR()	( RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DHD_RX_COMPLETE_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_POST_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_PTR()	( RDD_DHD_RX_POST_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DHD_RX_POST_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_PTR()	( RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DHD_RX_COMPLETE_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_POST_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_PTR()	( RDD_DHD_RX_POST_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + DHD_RX_POST_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_DHD_TX_COMPLETE_DESCRIPTOR_CWI32_DTS dhd_tx_complete_descriptor_cwi32;
+	RDD_DHD_TX_COMPLETE_DESCRIPTOR_DTS       dhd_tx_complete_descriptor;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_PTR()	( RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_TX_COMPLETE_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_PTR()	( RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_TX_COMPLETE_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_PTR()	( RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_TX_COMPLETE_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+typedef struct
+{
+	RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_PTR()	( RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DHD_TX_COMPLETE_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_BBH_TX_DESCRIPTOR_DTS bbh_tx_descriptor;
+	RDD_PACKET_DESCRIPTOR_DTS packet_descriptor;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_PACKET_DESCRIPTOR_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE     3072
+typedef struct
+{
+	RDD_US_PACKET_DESCRIPTOR_UNION_DTS	entry[ RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DTS;
+
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_PTR()	( RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE     3072
+typedef struct
+{
+	RDD_US_PACKET_DESCRIPTOR_UNION_DTS	entry[ RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DTS;
+
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_PTR()	( RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE     3072
+typedef struct
+{
+	RDD_US_PACKET_DESCRIPTOR_UNION_DTS	entry[ RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DTS;
+
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_PTR()	( RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE     3072
+typedef struct
+{
+	RDD_US_PACKET_DESCRIPTOR_UNION_DTS	entry[ RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DTS;
+
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_PTR()	( RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS )
+
+#endif
+#if defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_FC_NATC_L2_UCAST_FLOW_CONTEXT_ENTRY_DTS fc_natc_l2_ucast_flow_context_entry;
+	RDD_FC_UCAST_FLOW_CONTEXT_WFD_NIC_ENTRY_DTS fc_ucast_flow_context_wfd_nic_entry;
+	RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_DTS fc_ucast_flow_context_eth_xtm_entry;
+	RDD_FC_NATC_UCAST_FLOW_CONTEXT_ENTRY_DTS    fc_natc_ucast_flow_context_entry;
+	RDD_FC_UCAST_FLOW_CONTEXT_RNR_DHD_ENTRY_DTS fc_ucast_flow_context_rnr_dhd_entry;
+	RDD_FC_UCAST_FLOW_CONTEXT_WFD_DHD_ENTRY_DTS fc_ucast_flow_context_wfd_dhd_entry;
+	RDD_FC_NATC_MCAST_FLOW_CONTEXT_ENTRY_DTS    fc_natc_mcast_flow_context_entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NATC_CONTEXT_ENTRY_UNION_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_NATC_CONTEXT_TABLE_SIZE     65536
+typedef struct
+{
+	RDD_NATC_CONTEXT_ENTRY_UNION_DTS	entry[ RDD_NATC_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NATC_CONTEXT_TABLE_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_NATC_CONTEXT_TABLE_SIZE     65536
+typedef struct
+{
+	RDD_NATC_CONTEXT_ENTRY_UNION_DTS	entry[ RDD_NATC_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NATC_CONTEXT_TABLE_DTS;
+
+#endif
+#if defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_NAT_CACHE_LKP_ENTRY_DTS    nat_cache_lkp_entry;
+	RDD_NAT_CACHE_L2_LKP_ENTRY_DTS nat_cache_l2_lkp_entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NAT_CACHE_LKUP_ENTRY_UNION_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_NAT_CACHE_TABLE_SIZE     65536
+typedef struct
+{
+	RDD_NAT_CACHE_LKUP_ENTRY_UNION_DTS	entry[ RDD_NAT_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NAT_CACHE_TABLE_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_NAT_CACHE_TABLE_SIZE     65536
+typedef struct
+{
+	RDD_NAT_CACHE_LKUP_ENTRY_UNION_DTS	entry[ RDD_NAT_CACHE_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NAT_CACHE_TABLE_DTS;
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_CPU_RX_DESCRIPTOR_IPSEC_DTS cpu_rx_descriptor_ipsec;
+	RDD_CPU_TX_DESCRIPTOR_IPSEC_DTS cpu_tx_descriptor_ipsec;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_DESCRIPTOR_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_IPSEC_DS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_IPSEC_DS_DESCRIPTOR_UNION_DTS	entry[ RDD_IPSEC_DS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_QUEUE_DTS;
+
+#define RDD_IPSEC_DS_QUEUE_PTR()	( RDD_IPSEC_DS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_IPSEC_DS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_IPSEC_DS_DESCRIPTOR_UNION_DTS	entry[ RDD_IPSEC_DS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_QUEUE_DTS;
+
+#define RDD_IPSEC_DS_QUEUE_PTR()	( RDD_IPSEC_DS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_IPSEC_DS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_IPSEC_DS_DESCRIPTOR_UNION_DTS	entry[ RDD_IPSEC_DS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_QUEUE_DTS;
+
+#define RDD_IPSEC_DS_QUEUE_PTR()	( RDD_IPSEC_DS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_IPSEC_DS_QUEUE_SIZE     64
+typedef struct
+{
+	RDD_IPSEC_DS_DESCRIPTOR_UNION_DTS	entry[ RDD_IPSEC_DS_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_IPSEC_DS_QUEUE_DTS;
+
+#define RDD_IPSEC_DS_QUEUE_PTR()	( RDD_IPSEC_DS_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + IPSEC_DS_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_CPU_TX_DESCRIPTOR_DS_FAST_DTS      cpu_tx_descriptor_ds_fast;
+	RDD_CPU_TX_MESSAGE_DESCRIPTOR_DTS      cpu_tx_message_descriptor;
+	RDD_CPU_TX_DESCRIPTOR_DS_PICO_WIFI_DTS cpu_tx_descriptor_ds_pico_wifi;
+	RDD_CPU_TX_DESCRIPTOR_ABS_DTS          cpu_tx_descriptor_abs;
+	RDD_CPU_TX_DESCRIPTOR_CORE_DTS         cpu_tx_descriptor_core;
+	RDD_CPU_TX_DESCRIPTOR_US_FAST_DTS      cpu_tx_descriptor_us_fast;
+	RDD_CPU_TX_DESCRIPTOR_DS_PICO_DTS      cpu_tx_descriptor_ds_pico;
+	RDD_CPU_TX_DESCRIPTOR_BPM_DTS          cpu_tx_descriptor_bpm;
+	RDD_CPU_TX_DESCRIPTOR_DTS              cpu_tx_descriptor;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_FAST_DESCRIPTOR_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CPU_TX_FAST_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_FAST_DESCRIPTOR_UNION_DTS	entry[ RDD_CPU_TX_FAST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_FAST_QUEUE_DTS;
+
+#define RDD_CPU_TX_FAST_QUEUE_PTR()	( RDD_CPU_TX_FAST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_FAST_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138
+
+#define RDD_US_CPU_TX_FAST_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_FAST_DESCRIPTOR_UNION_DTS	entry[ RDD_US_CPU_TX_FAST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_FAST_QUEUE_DTS;
+
+#define RDD_US_CPU_TX_FAST_QUEUE_PTR()	( RDD_US_CPU_TX_FAST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_FAST_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CPU_TX_FAST_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_FAST_DESCRIPTOR_UNION_DTS	entry[ RDD_CPU_TX_FAST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_FAST_QUEUE_DTS;
+
+#define RDD_CPU_TX_FAST_QUEUE_PTR()	( RDD_CPU_TX_FAST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_FAST_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_US_CPU_TX_FAST_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_FAST_DESCRIPTOR_UNION_DTS	entry[ RDD_US_CPU_TX_FAST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_FAST_QUEUE_DTS;
+
+#define RDD_US_CPU_TX_FAST_QUEUE_PTR()	( RDD_US_CPU_TX_FAST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_FAST_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_CPU_TX_FAST_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_FAST_DESCRIPTOR_UNION_DTS	entry[ RDD_CPU_TX_FAST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_FAST_QUEUE_DTS;
+
+#define RDD_CPU_TX_FAST_QUEUE_PTR()	( RDD_CPU_TX_FAST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_FAST_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_US_CPU_TX_FAST_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_FAST_DESCRIPTOR_UNION_DTS	entry[ RDD_US_CPU_TX_FAST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_FAST_QUEUE_DTS;
+
+#define RDD_US_CPU_TX_FAST_QUEUE_PTR()	( RDD_US_CPU_TX_FAST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_FAST_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_CPU_TX_FAST_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_FAST_DESCRIPTOR_UNION_DTS	entry[ RDD_CPU_TX_FAST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_FAST_QUEUE_DTS;
+
+#define RDD_CPU_TX_FAST_QUEUE_PTR()	( RDD_CPU_TX_FAST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + CPU_TX_FAST_QUEUE_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_US_CPU_TX_FAST_QUEUE_SIZE     16
+typedef struct
+{
+	RDD_CPU_TX_FAST_DESCRIPTOR_UNION_DTS	entry[ RDD_US_CPU_TX_FAST_QUEUE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_CPU_TX_FAST_QUEUE_DTS;
+
+#define RDD_US_CPU_TX_FAST_QUEUE_PTR()	( RDD_US_CPU_TX_FAST_QUEUE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_CPU_TX_FAST_QUEUE_ADDRESS )
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_DHD_TX_POST_DESCRIPTOR_CWI32_DTS dhd_tx_post_descriptor_cwi32;
+	RDD_DHD_TX_POST_DESCRIPTOR_DTS       dhd_tx_post_descriptor;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_TX_POST_FLOW_RING_BUFFER_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE     4
+typedef struct
+{
+	RDD_DHD_TX_POST_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_PTR()	( RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE     4
+typedef struct
+{
+	RDD_DHD_TX_POST_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_PTR()	( RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908
+
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE     4
+typedef struct
+{
+	RDD_DHD_TX_POST_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_PTR()	( RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE     4
+typedef struct
+{
+	RDD_DHD_TX_POST_FLOW_RING_BUFFER_UNION_DTS	entry[ RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_DTS;
+
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_PTR()	( RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS )
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_DHD_RX_POST_DESCRIPTOR_CWI32_DTS dhd_rx_post_descriptor_cwi32;
+	RDD_DHD_RX_POST_DESCRIPTOR_DTS       dhd_rx_post_descriptor;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_POST_DDR_BUFFER_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_DHD_RX_POST_DDR_BUFFER_SIZE     1024
+typedef struct
+{
+	RDD_DHD_RX_POST_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_POST_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_POST_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_DHD_RX_POST_DDR_BUFFER_SIZE     1024
+typedef struct
+{
+	RDD_DHD_RX_POST_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_POST_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_POST_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908
+
+#define RDD_DHD_RX_POST_DDR_BUFFER_SIZE     1024
+typedef struct
+{
+	RDD_DHD_RX_POST_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_POST_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_POST_DDR_BUFFER_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+#define RDD_DHD_RX_POST_DDR_BUFFER_SIZE     1024
+typedef struct
+{
+	RDD_DHD_RX_POST_DDR_BUFFER_UNION_DTS	entry[ RDD_DHD_RX_POST_DDR_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DHD_RX_POST_DDR_BUFFER_DTS;
+
+#endif
+#if defined DSL_63138 || defined DSL_63148 || defined WL4908 || defined WL4908_EAP
+
+typedef union
+{
+	RDD_FC_UCAST_FLOW_CONTEXT_ETH_XTM_ENTRY_DTS fc_ucast_flow_context_eth_xtm_entry;
+	RDD_FC_UCAST_FLOW_CONTEXT_WFD_NIC_ENTRY_DTS fc_ucast_flow_context_wfd_nic_entry;
+	RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_DTS         fc_mcast_flow_context_entry;
+	RDD_FC_UCAST_FLOW_CONTEXT_ENTRY_DTS         fc_ucast_flow_context_entry;
+	RDD_FC_UCAST_FLOW_CONTEXT_RNR_DHD_ENTRY_DTS fc_ucast_flow_context_rnr_dhd_entry;
+	RDD_FC_UCAST_FLOW_CONTEXT_WFD_DHD_ENTRY_DTS fc_ucast_flow_context_wfd_dhd_entry;
+	RDD_FC_L2_UCAST_FLOW_CONTEXT_ENTRY_DTS      fc_l2_ucast_flow_context_entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONTEXT_ENTRY_UNION_DTS;
+
+#endif
+#if defined DSL_63138
+
+#define RDD_CONTEXT_TABLE_SIZE     16512
+typedef struct
+{
+	RDD_CONTEXT_ENTRY_UNION_DTS	entry[ RDD_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONTEXT_TABLE_DTS;
+
+#endif
+#if defined DSL_63148
+
+#define RDD_CONTEXT_TABLE_SIZE     16512
+typedef struct
+{
+	RDD_CONTEXT_ENTRY_UNION_DTS	entry[ RDD_CONTEXT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONTEXT_TABLE_DTS;
+
+#endif
+#if defined WL4908
+
+typedef struct
+{
+	RDD_CONTEXT_ENTRY_UNION_DTS	entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONTEXT_TABLE_DTS;
+
+#endif
+#if defined WL4908_EAP
+
+typedef struct
+{
+	RDD_CONTEXT_ENTRY_UNION_DTS	entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CONTEXT_TABLE_DTS;
+
+#endif
+
+#if defined DSL_63138
+typedef enum
+{
+	MODE_FIRST =    0,
+	MODE_DISABLED    = 0,
+	MODE_ENABLED     = 1,
+	MODE_LAST =     1
+} rdd_mode;
+typedef enum
+{
+	SEMAPHORE_IO_FIRST =      272,
+	SEMAPHORE_IO_ADDRESS_0     = 272,
+	SEMAPHORE_IO_ADDRESS_1     = 273,
+	SEMAPHORE_IO_ADDRESS_2     = 274,
+	SEMAPHORE_IO_ADDRESS_3     = 275,
+	SEMAPHORE_IO_ADDRESS_4     = 276,
+	SEMAPHORE_IO_ADDRESS_5     = 277,
+	SEMAPHORE_IO_ADDRESS_7     = 279,
+	SEMAPHORE_IO_ADDRESS_8     = 280,
+	SEMAPHORE_IO_ADDRESS_9     = 281,
+	SEMAPHORE_IO_ADDRESS_10    = 282,
+	SEMAPHORE_IO_ADDRESS_11    = 283,
+	SEMAPHORE_IO_ADDRESS_12    = 284,
+	SEMAPHORE_IO_ADDRESS_13    = 285,
+	SEMAPHORE_IO_ADDRESS_14    = 286,
+	SEMAPHORE_IO_ADDRESS_15    = 287,
+	SEMAPHORE_IO_LAST =       287
+} rdd_semaphore_io;
+typedef enum
+{
+	HASH_RESULT_FIRST =  0,
+	HASH_RESULT_SLOT_0    = 0,
+	HASH_RESULT_SLOT_1    = 1,
+	HASH_RESULT_SLOT_2    = 2,
+	HASH_RESULT_SLOT_3    = 3,
+	HASH_RESULT_SLOT_4    = 4,
+	HASH_RESULT_SLOT_5    = 5,
+	HASH_RESULT_LAST =   5
+} rdd_hash_result;
+typedef enum
+{
+	HASH_RESULT_IO_FIRST =     32,
+	HASH_RESULT_IO_ADDRESS_0    = 32,
+	HASH_RESULT_IO_ADDRESS_1    = 36,
+	HASH_RESULT_IO_ADDRESS_2    = 40,
+	HASH_RESULT_IO_ADDRESS_3    = 44,
+	HASH_RESULT_IO_ADDRESS_4    = 48,
+	HASH_RESULT_IO_ADDRESS_5    = 52,
+	HASH_RESULT_IO_LAST =      52
+} rdd_hash_result_io;
+typedef enum
+{
+	DMA_LOOKUP_RESULT_FIRST =      0,
+	DMA_LOOKUP_RESULT_SLOT_0        = 0,
+	DMA_LOOKUP_RESULT_SLOT_1        = 1,
+	DMA_LOOKUP_RESULT_SLOT_2        = 2,
+	DMA_LOOKUP_RESULT_SLOT_3        = 3,
+	DMA_LOOKUP_RESULT_SLOT_4        = 4,
+	DMA_LOOKUP_RESULT_FOUR_STEPS    = 4,
+	DMA_LOOKUP_RESULT_SLOT_5        = 5,
+	DMA_LOOKUP_RESULT_SLOT_6        = 6,
+	DMA_LOOKUP_RESULT_SLOT_7        = 7,
+	DMA_LOOKUP_RESULT_LAST =       7
+} rdd_dma_lookup_result;
+typedef enum
+{
+	DMA_LOOKUP_RESULT_IO_FIRST =     64,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_0    = 64,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_1    = 68,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_2    = 72,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_3    = 76,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_4    = 80,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_5    = 84,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_6    = 88,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_7    = 92,
+	DMA_LOOKUP_RESULT_IO_LAST =      92
+} rdd_dma_lookup_result_io;
+typedef enum
+{
+	CAM_RESULT_FIRST =   0,
+	CAM_RESULT_SLOT_0     = 0,
+	CAM_RESULT_SLOT_1     = 1,
+	CAM_RESULT_SLOT_2     = 2,
+	CAM_RESULT_SLOT_3     = 3,
+	CAM_RESULT_SLOT_4     = 4,
+	CAM_RESULT_SLOT_5     = 5,
+	CAM_RESULT_SLOT_6     = 6,
+	CAM_RESULT_SLOT_7     = 7,
+	CAM_RESULT_HIT_BIT    = 8,
+	CAM_RESULT_LAST =    8
+} rdd_cam_result;
+typedef enum
+{
+	CAM_RESULT_IO_FIRST =     96,
+	CAM_RESULT_IO_ADDRESS_0    = 96,
+	CAM_RESULT_IO_ADDRESS_1    = 100,
+	CAM_RESULT_IO_ADDRESS_2    = 104,
+	CAM_RESULT_IO_ADDRESS_3    = 108,
+	CAM_RESULT_IO_ADDRESS_4    = 112,
+	CAM_RESULT_IO_ADDRESS_5    = 116,
+	CAM_RESULT_IO_ADDRESS_6    = 120,
+	CAM_RESULT_IO_ADDRESS_7    = 124,
+	CAM_RESULT_IO_LAST =      124
+} rdd_cam_result_io;
+typedef enum
+{
+	CAM_SEARCH_FIRST =     2,
+	CAM_SEARCH_DEPTH_4      = 2,
+	CAM_SEARCH_DEPTH_8      = 3,
+	CAM_SEARCH_DEPTH_16     = 4,
+	CAM_SEARCH_DEPTH_32     = 5,
+	CAM_SEARCH_DEPTH_128    = 7,
+	CAM_SEARCH_LAST =      7
+} rdd_cam_search;
+typedef enum
+{
+	BBH_RX_ERROR_CODE_FIRST =            1,
+	BBH_RX_ERROR_CODE_CRC                 = 1,
+	BBH_RX_ERROR_CODE_NO_BPM              = 2,
+	BBH_RX_ERROR_CODE_NO_SBPM             = 4,
+	BBH_RX_ERROR_CODE_NO_DMA              = 8,
+	BBH_RX_ERROR_CODE_NO_SDMA             = 16,
+	BBH_RX_ERROR_CODE_PACKET_TOO_SHORT    = 32,
+	BBH_RX_ERROR_CODE_PACKET_TOO_LONG     = 64,
+	BBH_RX_ERROR_CODE_LAST =             64
+} rdd_bbh_rx_error_code;
+typedef enum
+{
+	IPSEC_RANGE_IO_FIRST =     524,
+	IPSEC_RANGE_IO_ADDRESS_3    = 524,
+	IPSEC_RANGE_IO_LAST =      524
+} rdd_ipsec_range_io;
+typedef enum
+{
+	RDD_EMAC_FIRST =    0,
+	RDD_EMAC_ID_WIFI     = 0,
+	RDD_EMAC_ID_0        = 1,
+	RDD_EMAC_ID_1        = 2,
+	RDD_EMAC_ID_2        = 3,
+	RDD_EMAC_ID_3        = 4,
+	RDD_EMAC_ID_4        = 5,
+	RDD_EMAC_ID_5        = 6,
+	RDD_EMAC_ID_6        = 7,
+	RDD_EMAC_ID_7        = 8,
+	RDD_EMAC_ID_COUNT    = 9,
+	RDD_EMAC_LAST =     9
+} rdd_rdd_emac;
+typedef enum
+{
+	ACTION_FIRST =     0,
+	ACTION_FORWARD      = 0,
+	ACTION_TRAP         = 1,
+	ACTION_DROP         = 2,
+	ACTION_MULTICAST    = 3,
+	ACTION_LAST =      3
+} rdd_action;
+typedef enum
+{
+	ENET_HEADER_FIRST =             0,
+	ENET_HEADER_DA_OFFSET            = 0,
+	ENET_HEADER_SA_OFFSET            = 6,
+	ENET_HEADER_ETHERTYPE_OFFSET     = 12,
+	ENET_HEADER_CTRL_OPCDE_OFFSET    = 14,
+	ENET_HEADER_SIZE                 = 16,
+	ENET_HEADER_LAST =              16
+} rdd_enet_header;
+typedef enum
+{
+	PFC_FRAME_FIRST =                      0,
+	PFC_FRAME_CLASS_ENABLE_VECTOR_OFFSET    = 0,
+	PFC_FRAME_TIME_0_OFFSET                 = 2,
+	PFC_FRAME_SIZE                          = 18,
+	PFC_FRAME_LAST =                       18
+} rdd_pfc_frame;
+typedef enum
+{
+	IP_PROTO_FIRST =    1,
+	IP_PROTO_ICMP        = 1,
+	IP_PROTO_IPIP        = 4,
+	IP_PROTO_TCP         = 6,
+	IP_PROTO_UDP         = 17,
+	IP_PROTO_IPV6        = 41,
+	IP_PROTO_GRE         = 47,
+	IP_PROTO_UDP_LITE    = 136,
+	IP_PROTO_LAST =     136
+} rdd_ip_proto;
+typedef enum
+{
+	IP_FLAGS_FIRST =                  1,
+	IP_FLAGS_DO_NOT_FRAGMENT_OFFSET    = 1,
+	IP_FLAGS_MORE_FRAGMENTS_OFFSET     = 2,
+	IP_FLAGS_LAST =                   2
+} rdd_ip_flags;
+typedef enum
+{
+	LAYER3_IPV6_HEADER_FIRST =         8,
+	LAYER3_IPV6_HEADER_SRC_IP_OFFSET    = 8,
+	LAYER3_IPV6_HEADER_DST_IP_OFFSET    = 24,
+	LAYER3_IPV6_HEADER_LAST =          24
+} rdd_layer3_ipv6_header;
+typedef enum
+{
+	LAYER3_HEADER_FIRST =                 0,
+	LAYER3_HEADER_TRAFIC_CLASS_OFFSET      = 0,
+	LAYER3_HEADER_TOS_OFFSET               = 1,
+	LAYER3_HEADER_TOTAL_LENGTH_OFFSET      = 2,
+	LAYER3_HEADER_PAYLOAD_LENGTH_OFFSET    = 4,
+	LAYER3_HEADER_FLAGS_OFFSET             = 6,
+	LAYER3_HEADER_HOP_LIMIT_OFFSET         = 7,
+	LAYER3_HEADER_TTL_OFFSET               = 8,
+	LAYER3_HEADER_PROTOCOL_OFFSET          = 9,
+	LAYER3_HEADER_IP_CHECKSUM_OFFSET       = 10,
+	LAYER3_HEADER_SRC_IP_OFFSET            = 12,
+	LAYER3_HEADER_DST_IP_OFFSET            = 16,
+	LAYER3_HEADER_LAST =                  16
+} rdd_layer3_header;
+typedef enum
+{
+	LAYER3_PSEUDO_HEADER_FIRST =             0,
+	LAYER3_PSEUDO_HEADER_SRC_IP_OFFSET        = 0,
+	LAYER3_PSEUDO_HEADER_DST_IP_OFFSET        = 4,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_OFFSET      = 8,
+	LAYER3_PSEUDO_HEADER_LENGTH_OFFSET        = 10,
+	LAYER3_PSEUDO_HEADER_HDR_LENGTH           = 12,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_F_WIDTH     = 16,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_F_OFFSET    = 16,
+	LAYER3_PSEUDO_HEADER_LAST =              16
+} rdd_layer3_pseudo_header;
+typedef enum
+{
+	LAYER3_IPV6_PSEUDO_HEADER_FIRST =           0,
+	LAYER3_IPV6_PSEUDO_HEADER_SRC_IP_OFFSET      = 0,
+	LAYER3_IPV6_PSEUDO_HEADER_DST_IP_OFFSET      = 16,
+	LAYER3_IPV6_PSEUDO_HEADER_LENGTH_OFFSET      = 32,
+	LAYER3_IPV6_PSEUDO_HEADER_PROTOCOL_OFFSET    = 36,
+	LAYER3_IPV6_PSEUDO_HEADER_HDR_LENGTH         = 40,
+	LAYER3_IPV6_PSEUDO_HEADER_LAST =            40
+} rdd_layer3_ipv6_pseudo_header;
+typedef enum
+{
+	LAYER4_HEADER_FIRST =                             0,
+	LAYER4_HEADER_SRC_PORT_OFFSET                      = 0,
+	LAYER4_HEADER_ESP_SPI_OFFSET                       = 0,
+	LAYER4_HEADER_DST_PORT_OFFSET                      = 2,
+	LAYER4_HEADER_UDP_LITE_CHECKSUM_COVERAGE_OFFSET    = 4,
+	LAYER4_HEADER_TCP_LENGTH_F_WIDTH                   = 4,
+	LAYER4_HEADER_UDP_CHECKSUM_OFFSET                  = 6,
+	LAYER4_HEADER_GRE_CALL_ID_OFFSET                   = 6,
+	LAYER4_HEADER_UDP_HDR_LENGTH                       = 8,
+	LAYER4_HEADER_TCP_LENGTH_OFFSET                    = 12,
+	LAYER4_HEADER_TCP_FLAGS_OFFSET                     = 13,
+	LAYER4_HEADER_TCP_CHECKSUM_OFFSET                  = 16,
+	LAYER4_HEADER_TCP_HDR_MIN_LENGTH                   = 20,
+	LAYER4_HEADER_TCP_LENGTH_F_OFFSET                  = 28,
+	LAYER4_HEADER_LAST =                              28
+} rdd_layer4_header;
+typedef enum
+{
+	PARSER_L2_PROTOCOL_FIRST =          1,
+	PARSER_L2_PROTOCOL_PPPOE_D           = 1,
+	PARSER_L2_PROTOCOL_PPPOE_S           = 2,
+	PARSER_L2_PROTOCOL_USER_DEFINED_0    = 8,
+	PARSER_L2_PROTOCOL_USER_DEFINED_1    = 9,
+	PARSER_L2_PROTOCOL_USER_DEFINED_2    = 10,
+	PARSER_L2_PROTOCOL_USER_DEFINED_3    = 11,
+	PARSER_L2_PROTOCOL_ARP               = 12,
+	PARSER_L2_PROTOCOL__1588             = 13,
+	PARSER_L2_PROTOCOL__802_1X           = 14,
+	PARSER_L2_PROTOCOL_MASK              = 15,
+	PARSER_L2_PROTOCOL__802_1AG_CFM      = 15,
+	PARSER_L2_PROTOCOL_LAST =           15
+} rdd_parser_l2_protocol;
+typedef enum
+{
+	PARSER_L3_PROTOCOL_FIRST = 0,
+	PARSER_L3_PROTOCOL_OTHER    = 0,
+	PARSER_L3_PROTOCOL_IPV4     = 1,
+	PARSER_L3_PROTOCOL_IPV6     = 2,
+	PARSER_L3_PROTOCOL_MASK     = 3,
+	PARSER_L3_PROTOCOL_LAST =  3
+} rdd_parser_l3_protocol;
+typedef enum
+{
+	PARSER_L4_PROTOCOL_FIRST =          0,
+	PARSER_L4_PROTOCOL_OTHER             = 0,
+	PARSER_L4_PROTOCOL_TCP               = 1,
+	PARSER_L4_PROTOCOL_UDP               = 2,
+	PARSER_L4_PROTOCOL_IGMP              = 3,
+	PARSER_L4_PROTOCOL_ICMP              = 4,
+	PARSER_L4_PROTOCOL_ICMPV6            = 5,
+	PARSER_L4_PROTOCOL_ESP               = 6,
+	PARSER_L4_PROTOCOL_GRE               = 7,
+	PARSER_L4_PROTOCOL_USER_DEFINED_0    = 8,
+	PARSER_L4_PROTOCOL_USER_DEFINED_1    = 9,
+	PARSER_L4_PROTOCOL_USER_DEFINED_2    = 10,
+	PARSER_L4_PROTOCOL_USER_DEFINED_3    = 11,
+	PARSER_L4_PROTOCOL_RESERVED          = 12,
+	PARSER_L4_PROTOCOL_IPV6              = 13,
+	PARSER_L4_PROTOCOL_AH                = 14,
+	PARSER_L4_PROTOCOL_NOT_PARSED        = 15,
+	PARSER_L4_PROTOCOL_MASK              = 15,
+	PARSER_L4_PROTOCOL_LAST =           15
+} rdd_parser_l4_protocol;
+typedef enum
+{
+	ACTION_ECN_FIRST =            0,
+	ACTION_ECN_REMARKING_OFFSET    = 0,
+	ACTION_ECN_REMARKING_WIDTH     = 2,
+	ACTION_ECN_LAST =             2
+} rdd_action_ecn;
+typedef enum
+{
+	ACTION_DSCP_FIRST =                          2,
+	ACTION_DSCP_REMARKING_OFFSET                  = 2,
+	ACTION_DSCP_REMARKING_TRAFFIC_CLASS_OFFSET    = 4,
+	ACTION_DSCP_REMARKING_WIDTH                   = 6,
+	ACTION_DSCP_REMARKING_TRAFFIC_CLASS_WIDTH     = 8,
+	ACTION_DSCP_LAST =                           8
+} rdd_action_dscp;
+typedef enum
+{
+	ACTION_OUTER_FIRST =                      14,
+	ACTION_OUTER_PBITS_REMARKING_VID_OFFSET    = 14,
+	ACTION_OUTER_LAST =                       14
+} rdd_action_outer;
+typedef enum
+{
+	ACTION_INNER_FIRST =                      18,
+	ACTION_INNER_PBITS_REMARKING_VID_OFFSET    = 18,
+	ACTION_INNER_LAST =                       18
+} rdd_action_inner;
+typedef enum
+{
+	ACTION_PBITS_FIRST =                     2,
+	ACTION_PBITS_REMARKING_DSCP_F_OFFSET      = 2,
+	ACTION_PBITS_REMARKING_PACKET_F_WIDTH     = 3,
+	ACTION_PBITS_REMARKING_DSCP_F_WIDTH       = 6,
+	ACTION_PBITS_REMARKING_PACKET_F_OFFSET    = 13,
+	ACTION_PBITS_LAST =                      13
+} rdd_action_pbits;
+typedef enum
+{
+	ACTION_DS_LITE_FIRST = 40,
+	ACTION_DS_LITE_SIZE    = 40,
+	ACTION_DS_LITE_LAST = 40
+} rdd_action_ds_lite;
+typedef enum
+{
+	DS_ACTION_ID_FIRST =     0,
+	DS_ACTION_ID_TRAP         = 0,
+	DS_ACTION_ID_TTL          = 2,
+	DS_ACTION_ID_DSCP         = 4,
+	DS_ACTION_ID_NAT          = 5,
+	DS_ACTION_ID_GRE          = 6,
+	DS_ACTION_ID_OPBITS       = 7,
+	DS_ACTION_ID_IPBITS       = 8,
+	DS_ACTION_ID_DS_LITE      = 9,
+	DS_ACTION_ID_PPPOE        = 10,
+	DS_ACTION_ID_TOTAL_NUM    = 17,
+	DS_ACTION_ID_LAST =      17
+} rdd_ds_action_id;
+typedef enum
+{
+	US_ACTION_ID_FIRST =     0,
+	US_ACTION_ID_TRAP         = 0,
+	US_ACTION_ID_TTL          = 2,
+	US_ACTION_ID_DSCP         = 4,
+	US_ACTION_ID_NAT          = 5,
+	US_ACTION_ID_GRE          = 6,
+	US_ACTION_ID_OPBITS       = 7,
+	US_ACTION_ID_IPBITS       = 8,
+	US_ACTION_ID_DS_LITE      = 9,
+	US_ACTION_ID_PPPOE        = 10,
+	US_ACTION_ID_TOTAL_NUM    = 17,
+	US_ACTION_ID_LAST =      17
+} rdd_us_action_id;
+typedef enum
+{
+	RDD_VPORT_FIRST = 0,
+	RDD_VPORT_ID_0     = 0,
+	RDD_VPORT_ID_1     = 1,
+	RDD_VPORT_ID_2     = 2,
+	RDD_VPORT_ID_3     = 3,
+	RDD_VPORT_ID_4     = 4,
+	RDD_VPORT_ID_5     = 5,
+	RDD_VPORT_ID_6     = 6,
+	RDD_VPORT_ID_7     = 7,
+	RDD_VPORT_ID_8     = 8,
+	RDD_VPORT_ID_9     = 9,
+	RDD_VPORT_ID_10    = 10,
+	RDD_VPORT_ID_11    = 11,
+	RDD_VPORT_ID_12    = 12,
+	RDD_VPORT_ID_13    = 13,
+	RDD_VPORT_ID_14    = 14,
+	RDD_VPORT_ID_15    = 15,
+	RDD_VPORT_ID_16    = 16,
+	RDD_VPORT_ID_17    = 17,
+	RDD_VPORT_ID_18    = 18,
+	RDD_VPORT_ID_19    = 19,
+	RDD_VPORT_ID_20    = 20,
+	RDD_VPORT_ID_21    = 21,
+	RDD_VPORT_ID_22    = 22,
+	RDD_VPORT_ID_23    = 23,
+	RDD_VPORT_ID_24    = 24,
+	RDD_VPORT_ID_25    = 25,
+	RDD_VPORT_ID_26    = 26,
+	RDD_VPORT_ID_27    = 27,
+	RDD_VPORT_ID_28    = 28,
+	RDD_VPORT_ID_29    = 29,
+	RDD_VPORT_ID_30    = 30,
+	RDD_VPORT_ID_31    = 31,
+	RDD_VPORT_ID_32    = 32,
+	RDD_VPORT_ID_33    = 33,
+	RDD_VPORT_ID_34    = 34,
+	RDD_VPORT_ID_35    = 35,
+	RDD_VPORT_ID_36    = 36,
+	RDD_VPORT_ID_37    = 37,
+	RDD_VPORT_ID_38    = 38,
+	RDD_VPORT_ID_39    = 39,
+	RDD_VPORT_LAST =  39
+} rdd_rdd_vport;
+typedef enum
+{
+	DSCP_TO_FIRST =              6,
+	DSCP_TO_PBITS_SHIFT_OFFSET    = 6,
+	DSCP_TO_LAST =               6
+} rdd_dscp_to;
+typedef enum
+{
+	RESOLUTION_CONTEXT_FIRST =                       0,
+	RESOLUTION_CONTEXT_VIRTUAL_SRC_PORT_OFFSET        = 0,
+	RESOLUTION_CONTEXT_GPE_DMA_OFFSET_WIDTH           = 1,
+	RESOLUTION_CONTEXT_GPE_HEADER_LENGTH_WIDTH        = 1,
+	RESOLUTION_CONTEXT_GPE_HEADER_IH_PTR_WIDTH        = 2,
+	RESOLUTION_CONTEXT_GPE_COMMAND_LIST_PTR_WIDTH     = 2,
+	RESOLUTION_CONTEXT_GPE_PACKET_DRR_PTR_WIDTH       = 4,
+	RESOLUTION_CONTEXT_GPE_HEADER_LENGTH_OFFSET       = 6,
+	RESOLUTION_CONTEXT_GPE_DMA_OFFSET_OFFSET          = 7,
+	RESOLUTION_CONTEXT_GPE_COMMAND_LIST_PTR_OFFSET    = 8,
+	RESOLUTION_CONTEXT_GPE_HEADER_IH_PTR_OFFSET       = 10,
+	RESOLUTION_CONTEXT_GPE_PACKET_DRR_PTR_OFFSET      = 12,
+	RESOLUTION_CONTEXT_LAST =                        12
+} rdd_resolution_context;
+typedef enum
+{
+	FFI_FIRST =        3,
+	FFI_8_LOG2_SIZE     = 3,
+	FFI_16_LOG2_SIZE    = 4,
+	FFI_32_LOG2_SIZE    = 5,
+	FFI_8_SIZE          = 8,
+	FFI_16_SIZE         = 16,
+	FFI_32_SIZE         = 32,
+	FFI_LAST =         32
+} rdd_ffi;
+typedef enum
+{
+	FR_FORMAT_FIRST =     0,
+	FR_FORMAT_WI_WI64      = 0,
+	FR_FORMAT_WI_CWI32     = 1,
+	FR_FORMAT_WI_CWI64     = 2,
+	FR_FORMAT_WI_ACWI32    = 3,
+	FR_FORMAT_WI_ACWI64    = 4,
+	FR_FORMAT_LAST =      4
+} rdd_fr_format;
+typedef enum
+{
+	BACKUP_INDEX_FIRST =     21760,
+	BACKUP_INDEX_FIFO_SIZE    = 21760,
+	BACKUP_INDEX_LAST =      21760
+} rdd_backup_index;
+typedef enum
+{
+	DMA_TYPE_FIRST =      1,
+	DMA_TYPE_IDMA          = 1,
+	DMA_TYPE_HWA_RXPOST    = 5,
+	DMA_TYPE_HWA_TXCPL     = 6,
+	DMA_TYPE_HWA_RXCPL     = 7,
+	DMA_TYPE_LAST =       7
+} rdd_dma_type;
+#endif
+
+#if defined DSL_63148
+typedef enum
+{
+	MODE_FIRST =    0,
+	MODE_DISABLED    = 0,
+	MODE_ENABLED     = 1,
+	MODE_LAST =     1
+} rdd_mode;
+typedef enum
+{
+	SEMAPHORE_IO_FIRST =      272,
+	SEMAPHORE_IO_ADDRESS_0     = 272,
+	SEMAPHORE_IO_ADDRESS_1     = 273,
+	SEMAPHORE_IO_ADDRESS_2     = 274,
+	SEMAPHORE_IO_ADDRESS_3     = 275,
+	SEMAPHORE_IO_ADDRESS_4     = 276,
+	SEMAPHORE_IO_ADDRESS_5     = 277,
+	SEMAPHORE_IO_ADDRESS_7     = 279,
+	SEMAPHORE_IO_ADDRESS_8     = 280,
+	SEMAPHORE_IO_ADDRESS_9     = 281,
+	SEMAPHORE_IO_ADDRESS_10    = 282,
+	SEMAPHORE_IO_ADDRESS_11    = 283,
+	SEMAPHORE_IO_ADDRESS_12    = 284,
+	SEMAPHORE_IO_ADDRESS_13    = 285,
+	SEMAPHORE_IO_ADDRESS_14    = 286,
+	SEMAPHORE_IO_ADDRESS_15    = 287,
+	SEMAPHORE_IO_LAST =       287
+} rdd_semaphore_io;
+typedef enum
+{
+	HASH_RESULT_FIRST =  0,
+	HASH_RESULT_SLOT_0    = 0,
+	HASH_RESULT_SLOT_1    = 1,
+	HASH_RESULT_SLOT_2    = 2,
+	HASH_RESULT_SLOT_3    = 3,
+	HASH_RESULT_SLOT_4    = 4,
+	HASH_RESULT_SLOT_5    = 5,
+	HASH_RESULT_LAST =   5
+} rdd_hash_result;
+typedef enum
+{
+	HASH_RESULT_IO_FIRST =     32,
+	HASH_RESULT_IO_ADDRESS_0    = 32,
+	HASH_RESULT_IO_ADDRESS_1    = 36,
+	HASH_RESULT_IO_ADDRESS_2    = 40,
+	HASH_RESULT_IO_ADDRESS_3    = 44,
+	HASH_RESULT_IO_ADDRESS_4    = 48,
+	HASH_RESULT_IO_ADDRESS_5    = 52,
+	HASH_RESULT_IO_LAST =      52
+} rdd_hash_result_io;
+typedef enum
+{
+	DMA_LOOKUP_RESULT_FIRST =      0,
+	DMA_LOOKUP_RESULT_SLOT_0        = 0,
+	DMA_LOOKUP_RESULT_SLOT_1        = 1,
+	DMA_LOOKUP_RESULT_SLOT_2        = 2,
+	DMA_LOOKUP_RESULT_SLOT_3        = 3,
+	DMA_LOOKUP_RESULT_SLOT_4        = 4,
+	DMA_LOOKUP_RESULT_FOUR_STEPS    = 4,
+	DMA_LOOKUP_RESULT_SLOT_5        = 5,
+	DMA_LOOKUP_RESULT_SLOT_6        = 6,
+	DMA_LOOKUP_RESULT_SLOT_7        = 7,
+	DMA_LOOKUP_RESULT_LAST =       7
+} rdd_dma_lookup_result;
+typedef enum
+{
+	DMA_LOOKUP_RESULT_IO_FIRST =     64,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_0    = 64,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_1    = 68,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_2    = 72,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_3    = 76,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_4    = 80,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_5    = 84,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_6    = 88,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_7    = 92,
+	DMA_LOOKUP_RESULT_IO_LAST =      92
+} rdd_dma_lookup_result_io;
+typedef enum
+{
+	CAM_RESULT_FIRST =   0,
+	CAM_RESULT_SLOT_0     = 0,
+	CAM_RESULT_SLOT_1     = 1,
+	CAM_RESULT_SLOT_2     = 2,
+	CAM_RESULT_SLOT_3     = 3,
+	CAM_RESULT_SLOT_4     = 4,
+	CAM_RESULT_SLOT_5     = 5,
+	CAM_RESULT_SLOT_6     = 6,
+	CAM_RESULT_SLOT_7     = 7,
+	CAM_RESULT_HIT_BIT    = 8,
+	CAM_RESULT_LAST =    8
+} rdd_cam_result;
+typedef enum
+{
+	CAM_RESULT_IO_FIRST =     96,
+	CAM_RESULT_IO_ADDRESS_0    = 96,
+	CAM_RESULT_IO_ADDRESS_1    = 100,
+	CAM_RESULT_IO_ADDRESS_2    = 104,
+	CAM_RESULT_IO_ADDRESS_3    = 108,
+	CAM_RESULT_IO_ADDRESS_4    = 112,
+	CAM_RESULT_IO_ADDRESS_5    = 116,
+	CAM_RESULT_IO_ADDRESS_6    = 120,
+	CAM_RESULT_IO_ADDRESS_7    = 124,
+	CAM_RESULT_IO_LAST =      124
+} rdd_cam_result_io;
+typedef enum
+{
+	CAM_SEARCH_FIRST =     2,
+	CAM_SEARCH_DEPTH_4      = 2,
+	CAM_SEARCH_DEPTH_8      = 3,
+	CAM_SEARCH_DEPTH_16     = 4,
+	CAM_SEARCH_DEPTH_32     = 5,
+	CAM_SEARCH_DEPTH_128    = 7,
+	CAM_SEARCH_LAST =      7
+} rdd_cam_search;
+typedef enum
+{
+	BBH_RX_ERROR_CODE_FIRST =            1,
+	BBH_RX_ERROR_CODE_CRC                 = 1,
+	BBH_RX_ERROR_CODE_NO_BPM              = 2,
+	BBH_RX_ERROR_CODE_NO_SBPM             = 4,
+	BBH_RX_ERROR_CODE_NO_DMA              = 8,
+	BBH_RX_ERROR_CODE_NO_SDMA             = 16,
+	BBH_RX_ERROR_CODE_PACKET_TOO_SHORT    = 32,
+	BBH_RX_ERROR_CODE_PACKET_TOO_LONG     = 64,
+	BBH_RX_ERROR_CODE_LAST =             64
+} rdd_bbh_rx_error_code;
+typedef enum
+{
+	IPSEC_RANGE_IO_FIRST =     524,
+	IPSEC_RANGE_IO_ADDRESS_3    = 524,
+	IPSEC_RANGE_IO_LAST =      524
+} rdd_ipsec_range_io;
+typedef enum
+{
+	RDD_EMAC_FIRST =    0,
+	RDD_EMAC_ID_WIFI     = 0,
+	RDD_EMAC_ID_0        = 1,
+	RDD_EMAC_ID_1        = 2,
+	RDD_EMAC_ID_2        = 3,
+	RDD_EMAC_ID_3        = 4,
+	RDD_EMAC_ID_4        = 5,
+	RDD_EMAC_ID_5        = 6,
+	RDD_EMAC_ID_6        = 7,
+	RDD_EMAC_ID_7        = 8,
+	RDD_EMAC_ID_COUNT    = 9,
+	RDD_EMAC_LAST =     9
+} rdd_rdd_emac;
+typedef enum
+{
+	ACTION_FIRST =     0,
+	ACTION_FORWARD      = 0,
+	ACTION_TRAP         = 1,
+	ACTION_DROP         = 2,
+	ACTION_MULTICAST    = 3,
+	ACTION_LAST =      3
+} rdd_action;
+typedef enum
+{
+	ENET_HEADER_FIRST =             0,
+	ENET_HEADER_DA_OFFSET            = 0,
+	ENET_HEADER_SA_OFFSET            = 6,
+	ENET_HEADER_ETHERTYPE_OFFSET     = 12,
+	ENET_HEADER_CTRL_OPCDE_OFFSET    = 14,
+	ENET_HEADER_SIZE                 = 16,
+	ENET_HEADER_LAST =              16
+} rdd_enet_header;
+typedef enum
+{
+	PFC_FRAME_FIRST =                      0,
+	PFC_FRAME_CLASS_ENABLE_VECTOR_OFFSET    = 0,
+	PFC_FRAME_TIME_0_OFFSET                 = 2,
+	PFC_FRAME_SIZE                          = 18,
+	PFC_FRAME_LAST =                       18
+} rdd_pfc_frame;
+typedef enum
+{
+	IP_PROTO_FIRST =    1,
+	IP_PROTO_ICMP        = 1,
+	IP_PROTO_IPIP        = 4,
+	IP_PROTO_TCP         = 6,
+	IP_PROTO_UDP         = 17,
+	IP_PROTO_IPV6        = 41,
+	IP_PROTO_GRE         = 47,
+	IP_PROTO_UDP_LITE    = 136,
+	IP_PROTO_LAST =     136
+} rdd_ip_proto;
+typedef enum
+{
+	IP_FLAGS_FIRST =                  1,
+	IP_FLAGS_DO_NOT_FRAGMENT_OFFSET    = 1,
+	IP_FLAGS_MORE_FRAGMENTS_OFFSET     = 2,
+	IP_FLAGS_LAST =                   2
+} rdd_ip_flags;
+typedef enum
+{
+	LAYER3_IPV6_HEADER_FIRST =         8,
+	LAYER3_IPV6_HEADER_SRC_IP_OFFSET    = 8,
+	LAYER3_IPV6_HEADER_DST_IP_OFFSET    = 24,
+	LAYER3_IPV6_HEADER_LAST =          24
+} rdd_layer3_ipv6_header;
+typedef enum
+{
+	LAYER3_HEADER_FIRST =                 0,
+	LAYER3_HEADER_TRAFIC_CLASS_OFFSET      = 0,
+	LAYER3_HEADER_TOS_OFFSET               = 1,
+	LAYER3_HEADER_TOTAL_LENGTH_OFFSET      = 2,
+	LAYER3_HEADER_PAYLOAD_LENGTH_OFFSET    = 4,
+	LAYER3_HEADER_FLAGS_OFFSET             = 6,
+	LAYER3_HEADER_HOP_LIMIT_OFFSET         = 7,
+	LAYER3_HEADER_TTL_OFFSET               = 8,
+	LAYER3_HEADER_PROTOCOL_OFFSET          = 9,
+	LAYER3_HEADER_IP_CHECKSUM_OFFSET       = 10,
+	LAYER3_HEADER_SRC_IP_OFFSET            = 12,
+	LAYER3_HEADER_DST_IP_OFFSET            = 16,
+	LAYER3_HEADER_LAST =                  16
+} rdd_layer3_header;
+typedef enum
+{
+	LAYER3_PSEUDO_HEADER_FIRST =             0,
+	LAYER3_PSEUDO_HEADER_SRC_IP_OFFSET        = 0,
+	LAYER3_PSEUDO_HEADER_DST_IP_OFFSET        = 4,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_OFFSET      = 8,
+	LAYER3_PSEUDO_HEADER_LENGTH_OFFSET        = 10,
+	LAYER3_PSEUDO_HEADER_HDR_LENGTH           = 12,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_F_WIDTH     = 16,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_F_OFFSET    = 16,
+	LAYER3_PSEUDO_HEADER_LAST =              16
+} rdd_layer3_pseudo_header;
+typedef enum
+{
+	LAYER3_IPV6_PSEUDO_HEADER_FIRST =           0,
+	LAYER3_IPV6_PSEUDO_HEADER_SRC_IP_OFFSET      = 0,
+	LAYER3_IPV6_PSEUDO_HEADER_DST_IP_OFFSET      = 16,
+	LAYER3_IPV6_PSEUDO_HEADER_LENGTH_OFFSET      = 32,
+	LAYER3_IPV6_PSEUDO_HEADER_PROTOCOL_OFFSET    = 36,
+	LAYER3_IPV6_PSEUDO_HEADER_HDR_LENGTH         = 40,
+	LAYER3_IPV6_PSEUDO_HEADER_LAST =            40
+} rdd_layer3_ipv6_pseudo_header;
+typedef enum
+{
+	LAYER4_HEADER_FIRST =                             0,
+	LAYER4_HEADER_SRC_PORT_OFFSET                      = 0,
+	LAYER4_HEADER_ESP_SPI_OFFSET                       = 0,
+	LAYER4_HEADER_DST_PORT_OFFSET                      = 2,
+	LAYER4_HEADER_UDP_LITE_CHECKSUM_COVERAGE_OFFSET    = 4,
+	LAYER4_HEADER_TCP_LENGTH_F_WIDTH                   = 4,
+	LAYER4_HEADER_UDP_CHECKSUM_OFFSET                  = 6,
+	LAYER4_HEADER_GRE_CALL_ID_OFFSET                   = 6,
+	LAYER4_HEADER_UDP_HDR_LENGTH                       = 8,
+	LAYER4_HEADER_TCP_LENGTH_OFFSET                    = 12,
+	LAYER4_HEADER_TCP_FLAGS_OFFSET                     = 13,
+	LAYER4_HEADER_TCP_CHECKSUM_OFFSET                  = 16,
+	LAYER4_HEADER_TCP_HDR_MIN_LENGTH                   = 20,
+	LAYER4_HEADER_TCP_LENGTH_F_OFFSET                  = 28,
+	LAYER4_HEADER_LAST =                              28
+} rdd_layer4_header;
+typedef enum
+{
+	PARSER_L2_PROTOCOL_FIRST =          1,
+	PARSER_L2_PROTOCOL_PPPOE_D           = 1,
+	PARSER_L2_PROTOCOL_PPPOE_S           = 2,
+	PARSER_L2_PROTOCOL_USER_DEFINED_0    = 8,
+	PARSER_L2_PROTOCOL_USER_DEFINED_1    = 9,
+	PARSER_L2_PROTOCOL_USER_DEFINED_2    = 10,
+	PARSER_L2_PROTOCOL_USER_DEFINED_3    = 11,
+	PARSER_L2_PROTOCOL_ARP               = 12,
+	PARSER_L2_PROTOCOL__1588             = 13,
+	PARSER_L2_PROTOCOL__802_1X           = 14,
+	PARSER_L2_PROTOCOL_MASK              = 15,
+	PARSER_L2_PROTOCOL__802_1AG_CFM      = 15,
+	PARSER_L2_PROTOCOL_LAST =           15
+} rdd_parser_l2_protocol;
+typedef enum
+{
+	PARSER_L3_PROTOCOL_FIRST = 0,
+	PARSER_L3_PROTOCOL_OTHER    = 0,
+	PARSER_L3_PROTOCOL_IPV4     = 1,
+	PARSER_L3_PROTOCOL_IPV6     = 2,
+	PARSER_L3_PROTOCOL_MASK     = 3,
+	PARSER_L3_PROTOCOL_LAST =  3
+} rdd_parser_l3_protocol;
+typedef enum
+{
+	PARSER_L4_PROTOCOL_FIRST =          0,
+	PARSER_L4_PROTOCOL_OTHER             = 0,
+	PARSER_L4_PROTOCOL_TCP               = 1,
+	PARSER_L4_PROTOCOL_UDP               = 2,
+	PARSER_L4_PROTOCOL_IGMP              = 3,
+	PARSER_L4_PROTOCOL_ICMP              = 4,
+	PARSER_L4_PROTOCOL_ICMPV6            = 5,
+	PARSER_L4_PROTOCOL_ESP               = 6,
+	PARSER_L4_PROTOCOL_GRE               = 7,
+	PARSER_L4_PROTOCOL_USER_DEFINED_0    = 8,
+	PARSER_L4_PROTOCOL_USER_DEFINED_1    = 9,
+	PARSER_L4_PROTOCOL_USER_DEFINED_2    = 10,
+	PARSER_L4_PROTOCOL_USER_DEFINED_3    = 11,
+	PARSER_L4_PROTOCOL_RESERVED          = 12,
+	PARSER_L4_PROTOCOL_IPV6              = 13,
+	PARSER_L4_PROTOCOL_AH                = 14,
+	PARSER_L4_PROTOCOL_NOT_PARSED        = 15,
+	PARSER_L4_PROTOCOL_MASK              = 15,
+	PARSER_L4_PROTOCOL_LAST =           15
+} rdd_parser_l4_protocol;
+typedef enum
+{
+	ACTION_ECN_FIRST =            0,
+	ACTION_ECN_REMARKING_OFFSET    = 0,
+	ACTION_ECN_REMARKING_WIDTH     = 2,
+	ACTION_ECN_LAST =             2
+} rdd_action_ecn;
+typedef enum
+{
+	ACTION_DSCP_FIRST =                          2,
+	ACTION_DSCP_REMARKING_OFFSET                  = 2,
+	ACTION_DSCP_REMARKING_TRAFFIC_CLASS_OFFSET    = 4,
+	ACTION_DSCP_REMARKING_WIDTH                   = 6,
+	ACTION_DSCP_REMARKING_TRAFFIC_CLASS_WIDTH     = 8,
+	ACTION_DSCP_LAST =                           8
+} rdd_action_dscp;
+typedef enum
+{
+	ACTION_OUTER_FIRST =                      14,
+	ACTION_OUTER_PBITS_REMARKING_VID_OFFSET    = 14,
+	ACTION_OUTER_LAST =                       14
+} rdd_action_outer;
+typedef enum
+{
+	ACTION_INNER_FIRST =                      18,
+	ACTION_INNER_PBITS_REMARKING_VID_OFFSET    = 18,
+	ACTION_INNER_LAST =                       18
+} rdd_action_inner;
+typedef enum
+{
+	ACTION_PBITS_FIRST =                     2,
+	ACTION_PBITS_REMARKING_DSCP_F_OFFSET      = 2,
+	ACTION_PBITS_REMARKING_PACKET_F_WIDTH     = 3,
+	ACTION_PBITS_REMARKING_DSCP_F_WIDTH       = 6,
+	ACTION_PBITS_REMARKING_PACKET_F_OFFSET    = 13,
+	ACTION_PBITS_LAST =                      13
+} rdd_action_pbits;
+typedef enum
+{
+	ACTION_DS_LITE_FIRST = 40,
+	ACTION_DS_LITE_SIZE    = 40,
+	ACTION_DS_LITE_LAST = 40
+} rdd_action_ds_lite;
+typedef enum
+{
+	DS_ACTION_ID_FIRST =     0,
+	DS_ACTION_ID_TRAP         = 0,
+	DS_ACTION_ID_TTL          = 2,
+	DS_ACTION_ID_DSCP         = 4,
+	DS_ACTION_ID_NAT          = 5,
+	DS_ACTION_ID_GRE          = 6,
+	DS_ACTION_ID_OPBITS       = 7,
+	DS_ACTION_ID_IPBITS       = 8,
+	DS_ACTION_ID_DS_LITE      = 9,
+	DS_ACTION_ID_PPPOE        = 10,
+	DS_ACTION_ID_TOTAL_NUM    = 17,
+	DS_ACTION_ID_LAST =      17
+} rdd_ds_action_id;
+typedef enum
+{
+	US_ACTION_ID_FIRST =     0,
+	US_ACTION_ID_TRAP         = 0,
+	US_ACTION_ID_TTL          = 2,
+	US_ACTION_ID_DSCP         = 4,
+	US_ACTION_ID_NAT          = 5,
+	US_ACTION_ID_GRE          = 6,
+	US_ACTION_ID_OPBITS       = 7,
+	US_ACTION_ID_IPBITS       = 8,
+	US_ACTION_ID_DS_LITE      = 9,
+	US_ACTION_ID_PPPOE        = 10,
+	US_ACTION_ID_TOTAL_NUM    = 17,
+	US_ACTION_ID_LAST =      17
+} rdd_us_action_id;
+typedef enum
+{
+	RDD_VPORT_FIRST = 0,
+	RDD_VPORT_ID_0     = 0,
+	RDD_VPORT_ID_1     = 1,
+	RDD_VPORT_ID_2     = 2,
+	RDD_VPORT_ID_3     = 3,
+	RDD_VPORT_ID_4     = 4,
+	RDD_VPORT_ID_5     = 5,
+	RDD_VPORT_ID_6     = 6,
+	RDD_VPORT_ID_7     = 7,
+	RDD_VPORT_ID_8     = 8,
+	RDD_VPORT_ID_9     = 9,
+	RDD_VPORT_ID_10    = 10,
+	RDD_VPORT_ID_11    = 11,
+	RDD_VPORT_ID_12    = 12,
+	RDD_VPORT_ID_13    = 13,
+	RDD_VPORT_ID_14    = 14,
+	RDD_VPORT_ID_15    = 15,
+	RDD_VPORT_ID_16    = 16,
+	RDD_VPORT_ID_17    = 17,
+	RDD_VPORT_ID_18    = 18,
+	RDD_VPORT_ID_19    = 19,
+	RDD_VPORT_ID_20    = 20,
+	RDD_VPORT_ID_21    = 21,
+	RDD_VPORT_ID_22    = 22,
+	RDD_VPORT_ID_23    = 23,
+	RDD_VPORT_ID_24    = 24,
+	RDD_VPORT_ID_25    = 25,
+	RDD_VPORT_ID_26    = 26,
+	RDD_VPORT_ID_27    = 27,
+	RDD_VPORT_ID_28    = 28,
+	RDD_VPORT_ID_29    = 29,
+	RDD_VPORT_ID_30    = 30,
+	RDD_VPORT_ID_31    = 31,
+	RDD_VPORT_ID_32    = 32,
+	RDD_VPORT_ID_33    = 33,
+	RDD_VPORT_ID_34    = 34,
+	RDD_VPORT_ID_35    = 35,
+	RDD_VPORT_ID_36    = 36,
+	RDD_VPORT_ID_37    = 37,
+	RDD_VPORT_ID_38    = 38,
+	RDD_VPORT_ID_39    = 39,
+	RDD_VPORT_LAST =  39
+} rdd_rdd_vport;
+typedef enum
+{
+	DSCP_TO_FIRST =              6,
+	DSCP_TO_PBITS_SHIFT_OFFSET    = 6,
+	DSCP_TO_LAST =               6
+} rdd_dscp_to;
+typedef enum
+{
+	RESOLUTION_CONTEXT_FIRST =                       0,
+	RESOLUTION_CONTEXT_VIRTUAL_SRC_PORT_OFFSET        = 0,
+	RESOLUTION_CONTEXT_GPE_DMA_OFFSET_WIDTH           = 1,
+	RESOLUTION_CONTEXT_GPE_HEADER_LENGTH_WIDTH        = 1,
+	RESOLUTION_CONTEXT_GPE_HEADER_IH_PTR_WIDTH        = 2,
+	RESOLUTION_CONTEXT_GPE_COMMAND_LIST_PTR_WIDTH     = 2,
+	RESOLUTION_CONTEXT_GPE_PACKET_DRR_PTR_WIDTH       = 4,
+	RESOLUTION_CONTEXT_GPE_HEADER_LENGTH_OFFSET       = 6,
+	RESOLUTION_CONTEXT_GPE_DMA_OFFSET_OFFSET          = 7,
+	RESOLUTION_CONTEXT_GPE_COMMAND_LIST_PTR_OFFSET    = 8,
+	RESOLUTION_CONTEXT_GPE_HEADER_IH_PTR_OFFSET       = 10,
+	RESOLUTION_CONTEXT_GPE_PACKET_DRR_PTR_OFFSET      = 12,
+	RESOLUTION_CONTEXT_LAST =                        12
+} rdd_resolution_context;
+typedef enum
+{
+	FFI_FIRST =        3,
+	FFI_8_LOG2_SIZE     = 3,
+	FFI_16_LOG2_SIZE    = 4,
+	FFI_32_LOG2_SIZE    = 5,
+	FFI_8_SIZE          = 8,
+	FFI_16_SIZE         = 16,
+	FFI_32_SIZE         = 32,
+	FFI_LAST =         32
+} rdd_ffi;
+typedef enum
+{
+	FR_FORMAT_FIRST =     0,
+	FR_FORMAT_WI_WI64      = 0,
+	FR_FORMAT_WI_CWI32     = 1,
+	FR_FORMAT_WI_CWI64     = 2,
+	FR_FORMAT_WI_ACWI32    = 3,
+	FR_FORMAT_WI_ACWI64    = 4,
+	FR_FORMAT_LAST =      4
+} rdd_fr_format;
+typedef enum
+{
+	BACKUP_INDEX_FIRST =     21760,
+	BACKUP_INDEX_FIFO_SIZE    = 21760,
+	BACKUP_INDEX_LAST =      21760
+} rdd_backup_index;
+typedef enum
+{
+	DMA_TYPE_FIRST =      1,
+	DMA_TYPE_IDMA          = 1,
+	DMA_TYPE_HWA_RXPOST    = 5,
+	DMA_TYPE_HWA_TXCPL     = 6,
+	DMA_TYPE_HWA_RXCPL     = 7,
+	DMA_TYPE_LAST =       7
+} rdd_dma_type;
+#endif
+
+#if defined WL4908
+typedef enum
+{
+	MODE_FIRST =    0,
+	MODE_DISABLED    = 0,
+	MODE_ENABLED     = 1,
+	MODE_LAST =     1
+} rdd_mode;
+typedef enum
+{
+	SEMAPHORE_IO_FIRST =      272,
+	SEMAPHORE_IO_ADDRESS_0     = 272,
+	SEMAPHORE_IO_ADDRESS_1     = 273,
+	SEMAPHORE_IO_ADDRESS_2     = 274,
+	SEMAPHORE_IO_ADDRESS_3     = 275,
+	SEMAPHORE_IO_ADDRESS_4     = 276,
+	SEMAPHORE_IO_ADDRESS_5     = 277,
+	SEMAPHORE_IO_ADDRESS_7     = 279,
+	SEMAPHORE_IO_ADDRESS_8     = 280,
+	SEMAPHORE_IO_ADDRESS_9     = 281,
+	SEMAPHORE_IO_ADDRESS_10    = 282,
+	SEMAPHORE_IO_ADDRESS_11    = 283,
+	SEMAPHORE_IO_ADDRESS_12    = 284,
+	SEMAPHORE_IO_ADDRESS_13    = 285,
+	SEMAPHORE_IO_ADDRESS_14    = 286,
+	SEMAPHORE_IO_ADDRESS_15    = 287,
+	SEMAPHORE_IO_LAST =       287
+} rdd_semaphore_io;
+typedef enum
+{
+	HASH_RESULT_FIRST =  0,
+	HASH_RESULT_SLOT_0    = 0,
+	HASH_RESULT_SLOT_1    = 1,
+	HASH_RESULT_SLOT_2    = 2,
+	HASH_RESULT_SLOT_3    = 3,
+	HASH_RESULT_SLOT_4    = 4,
+	HASH_RESULT_SLOT_5    = 5,
+	HASH_RESULT_LAST =   5
+} rdd_hash_result;
+typedef enum
+{
+	HASH_RESULT_IO_FIRST =     32,
+	HASH_RESULT_IO_ADDRESS_0    = 32,
+	HASH_RESULT_IO_ADDRESS_1    = 36,
+	HASH_RESULT_IO_ADDRESS_2    = 40,
+	HASH_RESULT_IO_ADDRESS_3    = 44,
+	HASH_RESULT_IO_ADDRESS_4    = 48,
+	HASH_RESULT_IO_ADDRESS_5    = 52,
+	HASH_RESULT_IO_LAST =      52
+} rdd_hash_result_io;
+typedef enum
+{
+	DMA_LOOKUP_RESULT_FIRST =      0,
+	DMA_LOOKUP_RESULT_SLOT_0        = 0,
+	DMA_LOOKUP_RESULT_SLOT_1        = 1,
+	DMA_LOOKUP_RESULT_SLOT_2        = 2,
+	DMA_LOOKUP_RESULT_SLOT_3        = 3,
+	DMA_LOOKUP_RESULT_SLOT_4        = 4,
+	DMA_LOOKUP_RESULT_FOUR_STEPS    = 4,
+	DMA_LOOKUP_RESULT_SLOT_5        = 5,
+	DMA_LOOKUP_RESULT_SLOT_6        = 6,
+	DMA_LOOKUP_RESULT_SLOT_7        = 7,
+	DMA_LOOKUP_RESULT_LAST =       7
+} rdd_dma_lookup_result;
+typedef enum
+{
+	DMA_LOOKUP_RESULT_IO_FIRST =     64,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_0    = 64,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_1    = 68,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_2    = 72,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_3    = 76,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_4    = 80,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_5    = 84,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_6    = 88,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_7    = 92,
+	DMA_LOOKUP_RESULT_IO_LAST =      92
+} rdd_dma_lookup_result_io;
+typedef enum
+{
+	CAM_RESULT_FIRST =   0,
+	CAM_RESULT_SLOT_0     = 0,
+	CAM_RESULT_SLOT_1     = 1,
+	CAM_RESULT_SLOT_2     = 2,
+	CAM_RESULT_SLOT_3     = 3,
+	CAM_RESULT_SLOT_4     = 4,
+	CAM_RESULT_SLOT_5     = 5,
+	CAM_RESULT_SLOT_6     = 6,
+	CAM_RESULT_SLOT_7     = 7,
+	CAM_RESULT_HIT_BIT    = 8,
+	CAM_RESULT_LAST =    8
+} rdd_cam_result;
+typedef enum
+{
+	CAM_RESULT_IO_FIRST =     96,
+	CAM_RESULT_IO_ADDRESS_0    = 96,
+	CAM_RESULT_IO_ADDRESS_1    = 100,
+	CAM_RESULT_IO_ADDRESS_2    = 104,
+	CAM_RESULT_IO_ADDRESS_3    = 108,
+	CAM_RESULT_IO_ADDRESS_4    = 112,
+	CAM_RESULT_IO_ADDRESS_5    = 116,
+	CAM_RESULT_IO_ADDRESS_6    = 120,
+	CAM_RESULT_IO_ADDRESS_7    = 124,
+	CAM_RESULT_IO_LAST =      124
+} rdd_cam_result_io;
+typedef enum
+{
+	CAM_SEARCH_FIRST =     2,
+	CAM_SEARCH_DEPTH_4      = 2,
+	CAM_SEARCH_DEPTH_8      = 3,
+	CAM_SEARCH_DEPTH_16     = 4,
+	CAM_SEARCH_DEPTH_32     = 5,
+	CAM_SEARCH_DEPTH_128    = 7,
+	CAM_SEARCH_LAST =      7
+} rdd_cam_search;
+typedef enum
+{
+	BBH_RX_ERROR_CODE_FIRST =            1,
+	BBH_RX_ERROR_CODE_CRC                 = 1,
+	BBH_RX_ERROR_CODE_NO_BPM              = 2,
+	BBH_RX_ERROR_CODE_NO_SBPM             = 3,
+	BBH_RX_ERROR_CODE_NO_DMA              = 4,
+	BBH_RX_ERROR_CODE_NO_SDMA             = 5,
+	BBH_RX_ERROR_CODE_PACKET_TOO_SHORT    = 6,
+	BBH_RX_ERROR_CODE_PACKET_TOO_LONG     = 7,
+	BBH_RX_ERROR_CODE_THIRD_FLOW          = 8,
+	BBH_RX_ERROR_CODE_SOP_AFTER_SOP       = 9,
+	BBH_RX_ERROR_CODE_LAST =             9
+} rdd_bbh_rx_error_code;
+typedef enum
+{
+	IPSEC_RANGE_IO_FIRST =     524,
+	IPSEC_RANGE_IO_ADDRESS_3    = 524,
+	IPSEC_RANGE_IO_LAST =      524
+} rdd_ipsec_range_io;
+typedef enum
+{
+	RDD_EMAC_FIRST =    0,
+	RDD_EMAC_ID_WIFI     = 0,
+	RDD_EMAC_ID_0        = 1,
+	RDD_EMAC_ID_1        = 2,
+	RDD_EMAC_ID_2        = 3,
+	RDD_EMAC_ID_3        = 4,
+	RDD_EMAC_ID_4        = 5,
+	RDD_EMAC_ID_5        = 6,
+	RDD_EMAC_ID_6        = 7,
+	RDD_EMAC_ID_7        = 8,
+	RDD_EMAC_ID_COUNT    = 9,
+	RDD_EMAC_LAST =     9
+} rdd_rdd_emac;
+typedef enum
+{
+	FPM_ALLOC_FIRST =              0,
+	FPM_ALLOC_CHUNKS_8_OFFSET       = 0,
+	FPM_ALLOC_CHUNKS_4_OFFSET       = 8,
+	FPM_ALLOC_RESULT_SIZE           = 8,
+	FPM_ALLOC_TOKEN_INDEX_OFFSET    = 12,
+	FPM_ALLOC_CHUNKS_2_OFFSET       = 16,
+	FPM_ALLOC_TOKEN_INDEX_WIDTH     = 18,
+	FPM_ALLOC_CHUNKS_1_OFFSET       = 24,
+	FPM_ALLOC_TOKEN_VALID_OFFSET    = 31,
+	FPM_ALLOC_POOL_BASE             = 2193621504,
+	FPM_ALLOC_POOL0_BASE            = 2193622016,
+	FPM_ALLOC_LAST =               2193622016
+} rdd_fpm_alloc;
+typedef enum
+{
+	ACTION_FIRST =     0,
+	ACTION_FORWARD      = 0,
+	ACTION_TRAP         = 1,
+	ACTION_DROP         = 2,
+	ACTION_MULTICAST    = 3,
+	ACTION_LAST =      3
+} rdd_action;
+typedef enum
+{
+	ENET_HEADER_FIRST =             0,
+	ENET_HEADER_DA_OFFSET            = 0,
+	ENET_HEADER_SA_OFFSET            = 6,
+	ENET_HEADER_ETHERTYPE_OFFSET     = 12,
+	ENET_HEADER_CTRL_OPCDE_OFFSET    = 14,
+	ENET_HEADER_SIZE                 = 16,
+	ENET_HEADER_LAST =              16
+} rdd_enet_header;
+typedef enum
+{
+	PFC_FRAME_FIRST =                      0,
+	PFC_FRAME_CLASS_ENABLE_VECTOR_OFFSET    = 0,
+	PFC_FRAME_TIME_0_OFFSET                 = 2,
+	PFC_FRAME_SIZE                          = 18,
+	PFC_FRAME_LAST =                       18
+} rdd_pfc_frame;
+typedef enum
+{
+	IP_PROTO_FIRST =    1,
+	IP_PROTO_ICMP        = 1,
+	IP_PROTO_IPIP        = 4,
+	IP_PROTO_TCP         = 6,
+	IP_PROTO_UDP         = 17,
+	IP_PROTO_IPV6        = 41,
+	IP_PROTO_GRE         = 47,
+	IP_PROTO_UDP_LITE    = 136,
+	IP_PROTO_LAST =     136
+} rdd_ip_proto;
+typedef enum
+{
+	IP_FLAGS_FIRST =                  1,
+	IP_FLAGS_DO_NOT_FRAGMENT_OFFSET    = 1,
+	IP_FLAGS_MORE_FRAGMENTS_OFFSET     = 2,
+	IP_FLAGS_LAST =                   2
+} rdd_ip_flags;
+typedef enum
+{
+	LAYER3_IPV6_HEADER_FIRST =         8,
+	LAYER3_IPV6_HEADER_SRC_IP_OFFSET    = 8,
+	LAYER3_IPV6_HEADER_DST_IP_OFFSET    = 24,
+	LAYER3_IPV6_HEADER_LAST =          24
+} rdd_layer3_ipv6_header;
+typedef enum
+{
+	LAYER3_HEADER_FIRST =                 0,
+	LAYER3_HEADER_TRAFIC_CLASS_OFFSET      = 0,
+	LAYER3_HEADER_TOS_OFFSET               = 1,
+	LAYER3_HEADER_TOTAL_LENGTH_OFFSET      = 2,
+	LAYER3_HEADER_PAYLOAD_LENGTH_OFFSET    = 4,
+	LAYER3_HEADER_FLAGS_OFFSET             = 6,
+	LAYER3_HEADER_HOP_LIMIT_OFFSET         = 7,
+	LAYER3_HEADER_TTL_OFFSET               = 8,
+	LAYER3_HEADER_PROTOCOL_OFFSET          = 9,
+	LAYER3_HEADER_IP_CHECKSUM_OFFSET       = 10,
+	LAYER3_HEADER_SRC_IP_OFFSET            = 12,
+	LAYER3_HEADER_DST_IP_OFFSET            = 16,
+	LAYER3_HEADER_LAST =                  16
+} rdd_layer3_header;
+typedef enum
+{
+	LAYER3_PSEUDO_HEADER_FIRST =             0,
+	LAYER3_PSEUDO_HEADER_SRC_IP_OFFSET        = 0,
+	LAYER3_PSEUDO_HEADER_DST_IP_OFFSET        = 4,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_OFFSET      = 8,
+	LAYER3_PSEUDO_HEADER_LENGTH_OFFSET        = 10,
+	LAYER3_PSEUDO_HEADER_HDR_LENGTH           = 12,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_F_WIDTH     = 16,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_F_OFFSET    = 16,
+	LAYER3_PSEUDO_HEADER_LAST =              16
+} rdd_layer3_pseudo_header;
+typedef enum
+{
+	LAYER3_IPV6_PSEUDO_HEADER_FIRST =           0,
+	LAYER3_IPV6_PSEUDO_HEADER_SRC_IP_OFFSET      = 0,
+	LAYER3_IPV6_PSEUDO_HEADER_DST_IP_OFFSET      = 16,
+	LAYER3_IPV6_PSEUDO_HEADER_LENGTH_OFFSET      = 32,
+	LAYER3_IPV6_PSEUDO_HEADER_PROTOCOL_OFFSET    = 36,
+	LAYER3_IPV6_PSEUDO_HEADER_HDR_LENGTH         = 40,
+	LAYER3_IPV6_PSEUDO_HEADER_LAST =            40
+} rdd_layer3_ipv6_pseudo_header;
+typedef enum
+{
+	LAYER4_HEADER_FIRST =                             0,
+	LAYER4_HEADER_SRC_PORT_OFFSET                      = 0,
+	LAYER4_HEADER_ESP_SPI_OFFSET                       = 0,
+	LAYER4_HEADER_DST_PORT_OFFSET                      = 2,
+	LAYER4_HEADER_UDP_LITE_CHECKSUM_COVERAGE_OFFSET    = 4,
+	LAYER4_HEADER_TCP_LENGTH_F_WIDTH                   = 4,
+	LAYER4_HEADER_UDP_CHECKSUM_OFFSET                  = 6,
+	LAYER4_HEADER_GRE_CALL_ID_OFFSET                   = 6,
+	LAYER4_HEADER_UDP_HDR_LENGTH                       = 8,
+	LAYER4_HEADER_TCP_LENGTH_OFFSET                    = 12,
+	LAYER4_HEADER_TCP_FLAGS_OFFSET                     = 13,
+	LAYER4_HEADER_TCP_CHECKSUM_OFFSET                  = 16,
+	LAYER4_HEADER_TCP_HDR_MIN_LENGTH                   = 20,
+	LAYER4_HEADER_TCP_LENGTH_F_OFFSET                  = 28,
+	LAYER4_HEADER_LAST =                              28
+} rdd_layer4_header;
+typedef enum
+{
+	PARSER_L2_PROTOCOL_FIRST =          1,
+	PARSER_L2_PROTOCOL_PPPOE_D           = 1,
+	PARSER_L2_PROTOCOL_PPPOE_S           = 2,
+	PARSER_L2_PROTOCOL_USER_DEFINED_0    = 8,
+	PARSER_L2_PROTOCOL_USER_DEFINED_1    = 9,
+	PARSER_L2_PROTOCOL_USER_DEFINED_2    = 10,
+	PARSER_L2_PROTOCOL_USER_DEFINED_3    = 11,
+	PARSER_L2_PROTOCOL_ARP               = 12,
+	PARSER_L2_PROTOCOL__1588             = 13,
+	PARSER_L2_PROTOCOL__802_1X           = 14,
+	PARSER_L2_PROTOCOL_MASK              = 15,
+	PARSER_L2_PROTOCOL__802_1AG_CFM      = 15,
+	PARSER_L2_PROTOCOL_LAST =           15
+} rdd_parser_l2_protocol;
+typedef enum
+{
+	PARSER_L3_PROTOCOL_FIRST = 0,
+	PARSER_L3_PROTOCOL_OTHER    = 0,
+	PARSER_L3_PROTOCOL_IPV4     = 1,
+	PARSER_L3_PROTOCOL_IPV6     = 2,
+	PARSER_L3_PROTOCOL_MASK     = 3,
+	PARSER_L3_PROTOCOL_LAST =  3
+} rdd_parser_l3_protocol;
+typedef enum
+{
+	PARSER_L4_PROTOCOL_FIRST =          0,
+	PARSER_L4_PROTOCOL_OTHER             = 0,
+	PARSER_L4_PROTOCOL_TCP               = 1,
+	PARSER_L4_PROTOCOL_UDP               = 2,
+	PARSER_L4_PROTOCOL_IGMP              = 3,
+	PARSER_L4_PROTOCOL_ICMP              = 4,
+	PARSER_L4_PROTOCOL_ICMPV6            = 5,
+	PARSER_L4_PROTOCOL_ESP               = 6,
+	PARSER_L4_PROTOCOL_GRE               = 7,
+	PARSER_L4_PROTOCOL_USER_DEFINED_0    = 8,
+	PARSER_L4_PROTOCOL_USER_DEFINED_1    = 9,
+	PARSER_L4_PROTOCOL_USER_DEFINED_2    = 10,
+	PARSER_L4_PROTOCOL_USER_DEFINED_3    = 11,
+	PARSER_L4_PROTOCOL_RESERVED          = 12,
+	PARSER_L4_PROTOCOL_IPV6              = 13,
+	PARSER_L4_PROTOCOL_AH                = 14,
+	PARSER_L4_PROTOCOL_NOT_PARSED        = 15,
+	PARSER_L4_PROTOCOL_MASK              = 15,
+	PARSER_L4_PROTOCOL_LAST =           15
+} rdd_parser_l4_protocol;
+typedef enum
+{
+	ACTION_ECN_FIRST =            0,
+	ACTION_ECN_REMARKING_OFFSET    = 0,
+	ACTION_ECN_REMARKING_WIDTH     = 2,
+	ACTION_ECN_LAST =             2
+} rdd_action_ecn;
+typedef enum
+{
+	ACTION_DSCP_FIRST =                          2,
+	ACTION_DSCP_REMARKING_OFFSET                  = 2,
+	ACTION_DSCP_REMARKING_TRAFFIC_CLASS_OFFSET    = 4,
+	ACTION_DSCP_REMARKING_WIDTH                   = 6,
+	ACTION_DSCP_REMARKING_TRAFFIC_CLASS_WIDTH     = 8,
+	ACTION_DSCP_LAST =                           8
+} rdd_action_dscp;
+typedef enum
+{
+	ACTION_OUTER_FIRST =                      14,
+	ACTION_OUTER_PBITS_REMARKING_VID_OFFSET    = 14,
+	ACTION_OUTER_LAST =                       14
+} rdd_action_outer;
+typedef enum
+{
+	ACTION_INNER_FIRST =                      18,
+	ACTION_INNER_PBITS_REMARKING_VID_OFFSET    = 18,
+	ACTION_INNER_LAST =                       18
+} rdd_action_inner;
+typedef enum
+{
+	ACTION_PBITS_FIRST =                     2,
+	ACTION_PBITS_REMARKING_DSCP_F_OFFSET      = 2,
+	ACTION_PBITS_REMARKING_PACKET_F_WIDTH     = 3,
+	ACTION_PBITS_REMARKING_DSCP_F_WIDTH       = 6,
+	ACTION_PBITS_REMARKING_PACKET_F_OFFSET    = 13,
+	ACTION_PBITS_LAST =                      13
+} rdd_action_pbits;
+typedef enum
+{
+	ACTION_DS_LITE_FIRST = 40,
+	ACTION_DS_LITE_SIZE    = 40,
+	ACTION_DS_LITE_LAST = 40
+} rdd_action_ds_lite;
+typedef enum
+{
+	DS_ACTION_ID_FIRST =     0,
+	DS_ACTION_ID_TRAP         = 0,
+	DS_ACTION_ID_TTL          = 2,
+	DS_ACTION_ID_DSCP         = 4,
+	DS_ACTION_ID_NAT          = 5,
+	DS_ACTION_ID_GRE          = 6,
+	DS_ACTION_ID_OPBITS       = 7,
+	DS_ACTION_ID_IPBITS       = 8,
+	DS_ACTION_ID_DS_LITE      = 9,
+	DS_ACTION_ID_PPPOE        = 10,
+	DS_ACTION_ID_TOTAL_NUM    = 17,
+	DS_ACTION_ID_LAST =      17
+} rdd_ds_action_id;
+typedef enum
+{
+	US_ACTION_ID_FIRST =     0,
+	US_ACTION_ID_TRAP         = 0,
+	US_ACTION_ID_TTL          = 2,
+	US_ACTION_ID_DSCP         = 4,
+	US_ACTION_ID_NAT          = 5,
+	US_ACTION_ID_GRE          = 6,
+	US_ACTION_ID_OPBITS       = 7,
+	US_ACTION_ID_IPBITS       = 8,
+	US_ACTION_ID_DS_LITE      = 9,
+	US_ACTION_ID_PPPOE        = 10,
+	US_ACTION_ID_TOTAL_NUM    = 17,
+	US_ACTION_ID_LAST =      17
+} rdd_us_action_id;
+typedef enum
+{
+	RDD_VPORT_FIRST = 0,
+	RDD_VPORT_ID_0     = 0,
+	RDD_VPORT_ID_1     = 1,
+	RDD_VPORT_ID_2     = 2,
+	RDD_VPORT_ID_3     = 3,
+	RDD_VPORT_ID_4     = 4,
+	RDD_VPORT_ID_5     = 5,
+	RDD_VPORT_ID_6     = 6,
+	RDD_VPORT_ID_7     = 7,
+	RDD_VPORT_ID_8     = 8,
+	RDD_VPORT_ID_9     = 9,
+	RDD_VPORT_ID_10    = 10,
+	RDD_VPORT_ID_11    = 11,
+	RDD_VPORT_ID_12    = 12,
+	RDD_VPORT_ID_13    = 13,
+	RDD_VPORT_ID_14    = 14,
+	RDD_VPORT_ID_15    = 15,
+	RDD_VPORT_ID_16    = 16,
+	RDD_VPORT_ID_17    = 17,
+	RDD_VPORT_ID_18    = 18,
+	RDD_VPORT_ID_19    = 19,
+	RDD_VPORT_ID_20    = 20,
+	RDD_VPORT_ID_21    = 21,
+	RDD_VPORT_ID_22    = 22,
+	RDD_VPORT_ID_23    = 23,
+	RDD_VPORT_ID_24    = 24,
+	RDD_VPORT_ID_25    = 25,
+	RDD_VPORT_ID_26    = 26,
+	RDD_VPORT_ID_27    = 27,
+	RDD_VPORT_ID_28    = 28,
+	RDD_VPORT_ID_29    = 29,
+	RDD_VPORT_ID_30    = 30,
+	RDD_VPORT_ID_31    = 31,
+	RDD_VPORT_ID_32    = 32,
+	RDD_VPORT_ID_33    = 33,
+	RDD_VPORT_ID_34    = 34,
+	RDD_VPORT_ID_35    = 35,
+	RDD_VPORT_ID_36    = 36,
+	RDD_VPORT_ID_37    = 37,
+	RDD_VPORT_ID_38    = 38,
+	RDD_VPORT_ID_39    = 39,
+	RDD_VPORT_LAST =  39
+} rdd_rdd_vport;
+typedef enum
+{
+	DSCP_TO_FIRST =              6,
+	DSCP_TO_PBITS_SHIFT_OFFSET    = 6,
+	DSCP_TO_LAST =               6
+} rdd_dscp_to;
+typedef enum
+{
+	RESOLUTION_CONTEXT_FIRST =                       0,
+	RESOLUTION_CONTEXT_VIRTUAL_SRC_PORT_OFFSET        = 0,
+	RESOLUTION_CONTEXT_GPE_DMA_OFFSET_WIDTH           = 1,
+	RESOLUTION_CONTEXT_GPE_HEADER_LENGTH_WIDTH        = 1,
+	RESOLUTION_CONTEXT_GPE_HEADER_IH_PTR_WIDTH        = 2,
+	RESOLUTION_CONTEXT_GPE_COMMAND_LIST_PTR_WIDTH     = 2,
+	RESOLUTION_CONTEXT_GPE_PACKET_DRR_PTR_WIDTH       = 4,
+	RESOLUTION_CONTEXT_GPE_HEADER_LENGTH_OFFSET       = 6,
+	RESOLUTION_CONTEXT_GPE_DMA_OFFSET_OFFSET          = 7,
+	RESOLUTION_CONTEXT_GPE_COMMAND_LIST_PTR_OFFSET    = 8,
+	RESOLUTION_CONTEXT_GPE_HEADER_IH_PTR_OFFSET       = 10,
+	RESOLUTION_CONTEXT_GPE_PACKET_DRR_PTR_OFFSET      = 12,
+	RESOLUTION_CONTEXT_LAST =                        12
+} rdd_resolution_context;
+typedef enum
+{
+	FFI_FIRST =        3,
+	FFI_8_LOG2_SIZE     = 3,
+	FFI_16_LOG2_SIZE    = 4,
+	FFI_32_LOG2_SIZE    = 5,
+	FFI_8_SIZE          = 8,
+	FFI_16_SIZE         = 16,
+	FFI_32_SIZE         = 32,
+	FFI_LAST =         32
+} rdd_ffi;
+typedef enum
+{
+	FR_FORMAT_FIRST =     0,
+	FR_FORMAT_WI_WI64      = 0,
+	FR_FORMAT_WI_CWI32     = 1,
+	FR_FORMAT_WI_CWI64     = 2,
+	FR_FORMAT_WI_ACWI32    = 3,
+	FR_FORMAT_WI_ACWI64    = 4,
+	FR_FORMAT_LAST =      4
+} rdd_fr_format;
+typedef enum
+{
+	BACKUP_INDEX_FIRST =     21760,
+	BACKUP_INDEX_FIFO_SIZE    = 21760,
+	BACKUP_INDEX_LAST =      21760
+} rdd_backup_index;
+typedef enum
+{
+	DMA_TYPE_FIRST =      1,
+	DMA_TYPE_IDMA          = 1,
+	DMA_TYPE_HWA_RXPOST    = 5,
+	DMA_TYPE_HWA_TXCPL     = 6,
+	DMA_TYPE_HWA_RXCPL     = 7,
+	DMA_TYPE_LAST =       7
+} rdd_dma_type;
+#endif
+
+#if defined WL4908_EAP
+typedef enum
+{
+	MODE_FIRST =    0,
+	MODE_DISABLED    = 0,
+	MODE_ENABLED     = 1,
+	MODE_LAST =     1
+} rdd_mode;
+typedef enum
+{
+	SEMAPHORE_IO_FIRST =      272,
+	SEMAPHORE_IO_ADDRESS_0     = 272,
+	SEMAPHORE_IO_ADDRESS_1     = 273,
+	SEMAPHORE_IO_ADDRESS_2     = 274,
+	SEMAPHORE_IO_ADDRESS_3     = 275,
+	SEMAPHORE_IO_ADDRESS_4     = 276,
+	SEMAPHORE_IO_ADDRESS_5     = 277,
+	SEMAPHORE_IO_ADDRESS_7     = 279,
+	SEMAPHORE_IO_ADDRESS_8     = 280,
+	SEMAPHORE_IO_ADDRESS_9     = 281,
+	SEMAPHORE_IO_ADDRESS_10    = 282,
+	SEMAPHORE_IO_ADDRESS_11    = 283,
+	SEMAPHORE_IO_ADDRESS_12    = 284,
+	SEMAPHORE_IO_ADDRESS_13    = 285,
+	SEMAPHORE_IO_ADDRESS_14    = 286,
+	SEMAPHORE_IO_ADDRESS_15    = 287,
+	SEMAPHORE_IO_LAST =       287
+} rdd_semaphore_io;
+typedef enum
+{
+	HASH_RESULT_FIRST =  0,
+	HASH_RESULT_SLOT_0    = 0,
+	HASH_RESULT_SLOT_1    = 1,
+	HASH_RESULT_SLOT_2    = 2,
+	HASH_RESULT_SLOT_3    = 3,
+	HASH_RESULT_SLOT_4    = 4,
+	HASH_RESULT_SLOT_5    = 5,
+	HASH_RESULT_LAST =   5
+} rdd_hash_result;
+typedef enum
+{
+	HASH_RESULT_IO_FIRST =     32,
+	HASH_RESULT_IO_ADDRESS_0    = 32,
+	HASH_RESULT_IO_ADDRESS_1    = 36,
+	HASH_RESULT_IO_ADDRESS_2    = 40,
+	HASH_RESULT_IO_ADDRESS_3    = 44,
+	HASH_RESULT_IO_ADDRESS_4    = 48,
+	HASH_RESULT_IO_ADDRESS_5    = 52,
+	HASH_RESULT_IO_LAST =      52
+} rdd_hash_result_io;
+typedef enum
+{
+	DMA_LOOKUP_RESULT_FIRST =      0,
+	DMA_LOOKUP_RESULT_SLOT_0        = 0,
+	DMA_LOOKUP_RESULT_SLOT_1        = 1,
+	DMA_LOOKUP_RESULT_SLOT_2        = 2,
+	DMA_LOOKUP_RESULT_SLOT_3        = 3,
+	DMA_LOOKUP_RESULT_SLOT_4        = 4,
+	DMA_LOOKUP_RESULT_FOUR_STEPS    = 4,
+	DMA_LOOKUP_RESULT_SLOT_5        = 5,
+	DMA_LOOKUP_RESULT_SLOT_6        = 6,
+	DMA_LOOKUP_RESULT_SLOT_7        = 7,
+	DMA_LOOKUP_RESULT_LAST =       7
+} rdd_dma_lookup_result;
+typedef enum
+{
+	DMA_LOOKUP_RESULT_IO_FIRST =     64,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_0    = 64,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_1    = 68,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_2    = 72,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_3    = 76,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_4    = 80,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_5    = 84,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_6    = 88,
+	DMA_LOOKUP_RESULT_IO_ADDRESS_7    = 92,
+	DMA_LOOKUP_RESULT_IO_LAST =      92
+} rdd_dma_lookup_result_io;
+typedef enum
+{
+	CAM_RESULT_FIRST =   0,
+	CAM_RESULT_SLOT_0     = 0,
+	CAM_RESULT_SLOT_1     = 1,
+	CAM_RESULT_SLOT_2     = 2,
+	CAM_RESULT_SLOT_3     = 3,
+	CAM_RESULT_SLOT_4     = 4,
+	CAM_RESULT_SLOT_5     = 5,
+	CAM_RESULT_SLOT_6     = 6,
+	CAM_RESULT_SLOT_7     = 7,
+	CAM_RESULT_HIT_BIT    = 8,
+	CAM_RESULT_LAST =    8
+} rdd_cam_result;
+typedef enum
+{
+	CAM_RESULT_IO_FIRST =     96,
+	CAM_RESULT_IO_ADDRESS_0    = 96,
+	CAM_RESULT_IO_ADDRESS_1    = 100,
+	CAM_RESULT_IO_ADDRESS_2    = 104,
+	CAM_RESULT_IO_ADDRESS_3    = 108,
+	CAM_RESULT_IO_ADDRESS_4    = 112,
+	CAM_RESULT_IO_ADDRESS_5    = 116,
+	CAM_RESULT_IO_ADDRESS_6    = 120,
+	CAM_RESULT_IO_ADDRESS_7    = 124,
+	CAM_RESULT_IO_LAST =      124
+} rdd_cam_result_io;
+typedef enum
+{
+	CAM_SEARCH_FIRST =     2,
+	CAM_SEARCH_DEPTH_4      = 2,
+	CAM_SEARCH_DEPTH_8      = 3,
+	CAM_SEARCH_DEPTH_16     = 4,
+	CAM_SEARCH_DEPTH_32     = 5,
+	CAM_SEARCH_DEPTH_128    = 7,
+	CAM_SEARCH_LAST =      7
+} rdd_cam_search;
+typedef enum
+{
+	BBH_RX_ERROR_CODE_FIRST =            1,
+	BBH_RX_ERROR_CODE_CRC                 = 1,
+	BBH_RX_ERROR_CODE_NO_BPM              = 2,
+	BBH_RX_ERROR_CODE_NO_SBPM             = 3,
+	BBH_RX_ERROR_CODE_NO_DMA              = 4,
+	BBH_RX_ERROR_CODE_NO_SDMA             = 5,
+	BBH_RX_ERROR_CODE_PACKET_TOO_SHORT    = 6,
+	BBH_RX_ERROR_CODE_PACKET_TOO_LONG     = 7,
+	BBH_RX_ERROR_CODE_THIRD_FLOW          = 8,
+	BBH_RX_ERROR_CODE_SOP_AFTER_SOP       = 9,
+	BBH_RX_ERROR_CODE_LAST =             9
+} rdd_bbh_rx_error_code;
+typedef enum
+{
+	IPSEC_RANGE_IO_FIRST =     524,
+	IPSEC_RANGE_IO_ADDRESS_3    = 524,
+	IPSEC_RANGE_IO_LAST =      524
+} rdd_ipsec_range_io;
+typedef enum
+{
+	RDD_EMAC_FIRST =    0,
+	RDD_EMAC_ID_WIFI     = 0,
+	RDD_EMAC_ID_0        = 1,
+	RDD_EMAC_ID_1        = 2,
+	RDD_EMAC_ID_2        = 3,
+	RDD_EMAC_ID_3        = 4,
+	RDD_EMAC_ID_4        = 5,
+	RDD_EMAC_ID_5        = 6,
+	RDD_EMAC_ID_6        = 7,
+	RDD_EMAC_ID_7        = 8,
+	RDD_EMAC_ID_COUNT    = 9,
+	RDD_EMAC_LAST =     9
+} rdd_rdd_emac;
+typedef enum
+{
+	FPM_ALLOC_FIRST =              0,
+	FPM_ALLOC_CHUNKS_8_OFFSET       = 0,
+	FPM_ALLOC_CHUNKS_4_OFFSET       = 8,
+	FPM_ALLOC_RESULT_SIZE           = 8,
+	FPM_ALLOC_TOKEN_INDEX_OFFSET    = 12,
+	FPM_ALLOC_CHUNKS_2_OFFSET       = 16,
+	FPM_ALLOC_TOKEN_INDEX_WIDTH     = 18,
+	FPM_ALLOC_CHUNKS_1_OFFSET       = 24,
+	FPM_ALLOC_TOKEN_VALID_OFFSET    = 31,
+	FPM_ALLOC_POOL_BASE             = 2193621504,
+	FPM_ALLOC_POOL0_BASE            = 2193622016,
+	FPM_ALLOC_LAST =               2193622016
+} rdd_fpm_alloc;
+typedef enum
+{
+	ACTION_FIRST =     0,
+	ACTION_FORWARD      = 0,
+	ACTION_TRAP         = 1,
+	ACTION_DROP         = 2,
+	ACTION_MULTICAST    = 3,
+	ACTION_LAST =      3
+} rdd_action;
+typedef enum
+{
+	ENET_HEADER_FIRST =             0,
+	ENET_HEADER_DA_OFFSET            = 0,
+	ENET_HEADER_SA_OFFSET            = 6,
+	ENET_HEADER_ETHERTYPE_OFFSET     = 12,
+	ENET_HEADER_CTRL_OPCDE_OFFSET    = 14,
+	ENET_HEADER_SIZE                 = 16,
+	ENET_HEADER_LAST =              16
+} rdd_enet_header;
+typedef enum
+{
+	PFC_FRAME_FIRST =                      0,
+	PFC_FRAME_CLASS_ENABLE_VECTOR_OFFSET    = 0,
+	PFC_FRAME_TIME_0_OFFSET                 = 2,
+	PFC_FRAME_SIZE                          = 18,
+	PFC_FRAME_LAST =                       18
+} rdd_pfc_frame;
+typedef enum
+{
+	IP_PROTO_FIRST =    1,
+	IP_PROTO_ICMP        = 1,
+	IP_PROTO_IPIP        = 4,
+	IP_PROTO_TCP         = 6,
+	IP_PROTO_UDP         = 17,
+	IP_PROTO_IPV6        = 41,
+	IP_PROTO_GRE         = 47,
+	IP_PROTO_UDP_LITE    = 136,
+	IP_PROTO_LAST =     136
+} rdd_ip_proto;
+typedef enum
+{
+	IP_FLAGS_FIRST =                  1,
+	IP_FLAGS_DO_NOT_FRAGMENT_OFFSET    = 1,
+	IP_FLAGS_MORE_FRAGMENTS_OFFSET     = 2,
+	IP_FLAGS_LAST =                   2
+} rdd_ip_flags;
+typedef enum
+{
+	LAYER3_IPV6_HEADER_FIRST =         8,
+	LAYER3_IPV6_HEADER_SRC_IP_OFFSET    = 8,
+	LAYER3_IPV6_HEADER_DST_IP_OFFSET    = 24,
+	LAYER3_IPV6_HEADER_LAST =          24
+} rdd_layer3_ipv6_header;
+typedef enum
+{
+	LAYER3_HEADER_FIRST =                 0,
+	LAYER3_HEADER_TRAFIC_CLASS_OFFSET      = 0,
+	LAYER3_HEADER_TOS_OFFSET               = 1,
+	LAYER3_HEADER_TOTAL_LENGTH_OFFSET      = 2,
+	LAYER3_HEADER_PAYLOAD_LENGTH_OFFSET    = 4,
+	LAYER3_HEADER_FLAGS_OFFSET             = 6,
+	LAYER3_HEADER_HOP_LIMIT_OFFSET         = 7,
+	LAYER3_HEADER_TTL_OFFSET               = 8,
+	LAYER3_HEADER_PROTOCOL_OFFSET          = 9,
+	LAYER3_HEADER_IP_CHECKSUM_OFFSET       = 10,
+	LAYER3_HEADER_SRC_IP_OFFSET            = 12,
+	LAYER3_HEADER_DST_IP_OFFSET            = 16,
+	LAYER3_HEADER_LAST =                  16
+} rdd_layer3_header;
+typedef enum
+{
+	LAYER3_PSEUDO_HEADER_FIRST =             0,
+	LAYER3_PSEUDO_HEADER_SRC_IP_OFFSET        = 0,
+	LAYER3_PSEUDO_HEADER_DST_IP_OFFSET        = 4,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_OFFSET      = 8,
+	LAYER3_PSEUDO_HEADER_LENGTH_OFFSET        = 10,
+	LAYER3_PSEUDO_HEADER_HDR_LENGTH           = 12,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_F_WIDTH     = 16,
+	LAYER3_PSEUDO_HEADER_PROTOCOL_F_OFFSET    = 16,
+	LAYER3_PSEUDO_HEADER_LAST =              16
+} rdd_layer3_pseudo_header;
+typedef enum
+{
+	LAYER3_IPV6_PSEUDO_HEADER_FIRST =           0,
+	LAYER3_IPV6_PSEUDO_HEADER_SRC_IP_OFFSET      = 0,
+	LAYER3_IPV6_PSEUDO_HEADER_DST_IP_OFFSET      = 16,
+	LAYER3_IPV6_PSEUDO_HEADER_LENGTH_OFFSET      = 32,
+	LAYER3_IPV6_PSEUDO_HEADER_PROTOCOL_OFFSET    = 36,
+	LAYER3_IPV6_PSEUDO_HEADER_HDR_LENGTH         = 40,
+	LAYER3_IPV6_PSEUDO_HEADER_LAST =            40
+} rdd_layer3_ipv6_pseudo_header;
+typedef enum
+{
+	LAYER4_HEADER_FIRST =                             0,
+	LAYER4_HEADER_SRC_PORT_OFFSET                      = 0,
+	LAYER4_HEADER_ESP_SPI_OFFSET                       = 0,
+	LAYER4_HEADER_DST_PORT_OFFSET                      = 2,
+	LAYER4_HEADER_UDP_LITE_CHECKSUM_COVERAGE_OFFSET    = 4,
+	LAYER4_HEADER_TCP_LENGTH_F_WIDTH                   = 4,
+	LAYER4_HEADER_UDP_CHECKSUM_OFFSET                  = 6,
+	LAYER4_HEADER_GRE_CALL_ID_OFFSET                   = 6,
+	LAYER4_HEADER_UDP_HDR_LENGTH                       = 8,
+	LAYER4_HEADER_TCP_LENGTH_OFFSET                    = 12,
+	LAYER4_HEADER_TCP_FLAGS_OFFSET                     = 13,
+	LAYER4_HEADER_TCP_CHECKSUM_OFFSET                  = 16,
+	LAYER4_HEADER_TCP_HDR_MIN_LENGTH                   = 20,
+	LAYER4_HEADER_TCP_LENGTH_F_OFFSET                  = 28,
+	LAYER4_HEADER_LAST =                              28
+} rdd_layer4_header;
+typedef enum
+{
+	PARSER_L2_PROTOCOL_FIRST =          1,
+	PARSER_L2_PROTOCOL_PPPOE_D           = 1,
+	PARSER_L2_PROTOCOL_PPPOE_S           = 2,
+	PARSER_L2_PROTOCOL_USER_DEFINED_0    = 8,
+	PARSER_L2_PROTOCOL_USER_DEFINED_1    = 9,
+	PARSER_L2_PROTOCOL_USER_DEFINED_2    = 10,
+	PARSER_L2_PROTOCOL_USER_DEFINED_3    = 11,
+	PARSER_L2_PROTOCOL_ARP               = 12,
+	PARSER_L2_PROTOCOL__1588             = 13,
+	PARSER_L2_PROTOCOL__802_1X           = 14,
+	PARSER_L2_PROTOCOL_MASK              = 15,
+	PARSER_L2_PROTOCOL__802_1AG_CFM      = 15,
+	PARSER_L2_PROTOCOL_LAST =           15
+} rdd_parser_l2_protocol;
+typedef enum
+{
+	PARSER_L3_PROTOCOL_FIRST = 0,
+	PARSER_L3_PROTOCOL_OTHER    = 0,
+	PARSER_L3_PROTOCOL_IPV4     = 1,
+	PARSER_L3_PROTOCOL_IPV6     = 2,
+	PARSER_L3_PROTOCOL_MASK     = 3,
+	PARSER_L3_PROTOCOL_LAST =  3
+} rdd_parser_l3_protocol;
+typedef enum
+{
+	PARSER_L4_PROTOCOL_FIRST =          0,
+	PARSER_L4_PROTOCOL_OTHER             = 0,
+	PARSER_L4_PROTOCOL_TCP               = 1,
+	PARSER_L4_PROTOCOL_UDP               = 2,
+	PARSER_L4_PROTOCOL_IGMP              = 3,
+	PARSER_L4_PROTOCOL_ICMP              = 4,
+	PARSER_L4_PROTOCOL_ICMPV6            = 5,
+	PARSER_L4_PROTOCOL_ESP               = 6,
+	PARSER_L4_PROTOCOL_GRE               = 7,
+	PARSER_L4_PROTOCOL_USER_DEFINED_0    = 8,
+	PARSER_L4_PROTOCOL_USER_DEFINED_1    = 9,
+	PARSER_L4_PROTOCOL_USER_DEFINED_2    = 10,
+	PARSER_L4_PROTOCOL_USER_DEFINED_3    = 11,
+	PARSER_L4_PROTOCOL_RESERVED          = 12,
+	PARSER_L4_PROTOCOL_IPV6              = 13,
+	PARSER_L4_PROTOCOL_AH                = 14,
+	PARSER_L4_PROTOCOL_NOT_PARSED        = 15,
+	PARSER_L4_PROTOCOL_MASK              = 15,
+	PARSER_L4_PROTOCOL_LAST =           15
+} rdd_parser_l4_protocol;
+typedef enum
+{
+	ACTION_ECN_FIRST =            0,
+	ACTION_ECN_REMARKING_OFFSET    = 0,
+	ACTION_ECN_REMARKING_WIDTH     = 2,
+	ACTION_ECN_LAST =             2
+} rdd_action_ecn;
+typedef enum
+{
+	ACTION_DSCP_FIRST =                          2,
+	ACTION_DSCP_REMARKING_OFFSET                  = 2,
+	ACTION_DSCP_REMARKING_TRAFFIC_CLASS_OFFSET    = 4,
+	ACTION_DSCP_REMARKING_WIDTH                   = 6,
+	ACTION_DSCP_REMARKING_TRAFFIC_CLASS_WIDTH     = 8,
+	ACTION_DSCP_LAST =                           8
+} rdd_action_dscp;
+typedef enum
+{
+	ACTION_OUTER_FIRST =                      14,
+	ACTION_OUTER_PBITS_REMARKING_VID_OFFSET    = 14,
+	ACTION_OUTER_LAST =                       14
+} rdd_action_outer;
+typedef enum
+{
+	ACTION_INNER_FIRST =                      18,
+	ACTION_INNER_PBITS_REMARKING_VID_OFFSET    = 18,
+	ACTION_INNER_LAST =                       18
+} rdd_action_inner;
+typedef enum
+{
+	ACTION_PBITS_FIRST =                     2,
+	ACTION_PBITS_REMARKING_DSCP_F_OFFSET      = 2,
+	ACTION_PBITS_REMARKING_PACKET_F_WIDTH     = 3,
+	ACTION_PBITS_REMARKING_DSCP_F_WIDTH       = 6,
+	ACTION_PBITS_REMARKING_PACKET_F_OFFSET    = 13,
+	ACTION_PBITS_LAST =                      13
+} rdd_action_pbits;
+typedef enum
+{
+	ACTION_DS_LITE_FIRST = 40,
+	ACTION_DS_LITE_SIZE    = 40,
+	ACTION_DS_LITE_LAST = 40
+} rdd_action_ds_lite;
+typedef enum
+{
+	DS_ACTION_ID_FIRST =     0,
+	DS_ACTION_ID_TRAP         = 0,
+	DS_ACTION_ID_TTL          = 2,
+	DS_ACTION_ID_DSCP         = 4,
+	DS_ACTION_ID_NAT          = 5,
+	DS_ACTION_ID_GRE          = 6,
+	DS_ACTION_ID_OPBITS       = 7,
+	DS_ACTION_ID_IPBITS       = 8,
+	DS_ACTION_ID_DS_LITE      = 9,
+	DS_ACTION_ID_PPPOE        = 10,
+	DS_ACTION_ID_TOTAL_NUM    = 17,
+	DS_ACTION_ID_LAST =      17
+} rdd_ds_action_id;
+typedef enum
+{
+	US_ACTION_ID_FIRST =     0,
+	US_ACTION_ID_TRAP         = 0,
+	US_ACTION_ID_TTL          = 2,
+	US_ACTION_ID_DSCP         = 4,
+	US_ACTION_ID_NAT          = 5,
+	US_ACTION_ID_GRE          = 6,
+	US_ACTION_ID_OPBITS       = 7,
+	US_ACTION_ID_IPBITS       = 8,
+	US_ACTION_ID_DS_LITE      = 9,
+	US_ACTION_ID_PPPOE        = 10,
+	US_ACTION_ID_TOTAL_NUM    = 17,
+	US_ACTION_ID_LAST =      17
+} rdd_us_action_id;
+typedef enum
+{
+	RDD_VPORT_FIRST = 0,
+	RDD_VPORT_ID_0     = 0,
+	RDD_VPORT_ID_1     = 1,
+	RDD_VPORT_ID_2     = 2,
+	RDD_VPORT_ID_3     = 3,
+	RDD_VPORT_ID_4     = 4,
+	RDD_VPORT_ID_5     = 5,
+	RDD_VPORT_ID_6     = 6,
+	RDD_VPORT_ID_7     = 7,
+	RDD_VPORT_ID_8     = 8,
+	RDD_VPORT_ID_9     = 9,
+	RDD_VPORT_ID_10    = 10,
+	RDD_VPORT_ID_11    = 11,
+	RDD_VPORT_ID_12    = 12,
+	RDD_VPORT_ID_13    = 13,
+	RDD_VPORT_ID_14    = 14,
+	RDD_VPORT_ID_15    = 15,
+	RDD_VPORT_ID_16    = 16,
+	RDD_VPORT_ID_17    = 17,
+	RDD_VPORT_ID_18    = 18,
+	RDD_VPORT_ID_19    = 19,
+	RDD_VPORT_ID_20    = 20,
+	RDD_VPORT_ID_21    = 21,
+	RDD_VPORT_ID_22    = 22,
+	RDD_VPORT_ID_23    = 23,
+	RDD_VPORT_ID_24    = 24,
+	RDD_VPORT_ID_25    = 25,
+	RDD_VPORT_ID_26    = 26,
+	RDD_VPORT_ID_27    = 27,
+	RDD_VPORT_ID_28    = 28,
+	RDD_VPORT_ID_29    = 29,
+	RDD_VPORT_ID_30    = 30,
+	RDD_VPORT_ID_31    = 31,
+	RDD_VPORT_ID_32    = 32,
+	RDD_VPORT_ID_33    = 33,
+	RDD_VPORT_ID_34    = 34,
+	RDD_VPORT_ID_35    = 35,
+	RDD_VPORT_ID_36    = 36,
+	RDD_VPORT_ID_37    = 37,
+	RDD_VPORT_ID_38    = 38,
+	RDD_VPORT_ID_39    = 39,
+	RDD_VPORT_LAST =  39
+} rdd_rdd_vport;
+typedef enum
+{
+	DSCP_TO_FIRST =              6,
+	DSCP_TO_PBITS_SHIFT_OFFSET    = 6,
+	DSCP_TO_LAST =               6
+} rdd_dscp_to;
+typedef enum
+{
+	RESOLUTION_CONTEXT_FIRST =                       0,
+	RESOLUTION_CONTEXT_VIRTUAL_SRC_PORT_OFFSET        = 0,
+	RESOLUTION_CONTEXT_GPE_DMA_OFFSET_WIDTH           = 1,
+	RESOLUTION_CONTEXT_GPE_HEADER_LENGTH_WIDTH        = 1,
+	RESOLUTION_CONTEXT_GPE_HEADER_IH_PTR_WIDTH        = 2,
+	RESOLUTION_CONTEXT_GPE_COMMAND_LIST_PTR_WIDTH     = 2,
+	RESOLUTION_CONTEXT_GPE_PACKET_DRR_PTR_WIDTH       = 4,
+	RESOLUTION_CONTEXT_GPE_HEADER_LENGTH_OFFSET       = 6,
+	RESOLUTION_CONTEXT_GPE_DMA_OFFSET_OFFSET          = 7,
+	RESOLUTION_CONTEXT_GPE_COMMAND_LIST_PTR_OFFSET    = 8,
+	RESOLUTION_CONTEXT_GPE_HEADER_IH_PTR_OFFSET       = 10,
+	RESOLUTION_CONTEXT_GPE_PACKET_DRR_PTR_OFFSET      = 12,
+	RESOLUTION_CONTEXT_LAST =                        12
+} rdd_resolution_context;
+typedef enum
+{
+	FFI_FIRST =        3,
+	FFI_8_LOG2_SIZE     = 3,
+	FFI_16_LOG2_SIZE    = 4,
+	FFI_32_LOG2_SIZE    = 5,
+	FFI_8_SIZE          = 8,
+	FFI_16_SIZE         = 16,
+	FFI_32_SIZE         = 32,
+	FFI_LAST =         32
+} rdd_ffi;
+typedef enum
+{
+	FR_FORMAT_FIRST =     0,
+	FR_FORMAT_WI_WI64      = 0,
+	FR_FORMAT_WI_CWI32     = 1,
+	FR_FORMAT_WI_CWI64     = 2,
+	FR_FORMAT_WI_ACWI32    = 3,
+	FR_FORMAT_WI_ACWI64    = 4,
+	FR_FORMAT_LAST =      4
+} rdd_fr_format;
+typedef enum
+{
+	BACKUP_INDEX_FIRST =     21760,
+	BACKUP_INDEX_FIFO_SIZE    = 21760,
+	BACKUP_INDEX_LAST =      21760
+} rdd_backup_index;
+typedef enum
+{
+	DMA_TYPE_FIRST =      1,
+	DMA_TYPE_IDMA          = 1,
+	DMA_TYPE_HWA_RXPOST    = 5,
+	DMA_TYPE_HWA_TXCPL     = 6,
+	DMA_TYPE_HWA_RXCPL     = 7,
+	DMA_TYPE_LAST =       7
+} rdd_dma_type;
+#endif
+#endif /* _RDD_DATA_STRUCTURES_AUTO_H */
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_defs.h b/arch/arm/mach-bcmbca/rdp/rdd_defs.h
new file mode 100755
index 0000000000..42df2046a5
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_defs.h
@@ -0,0 +1,1380 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef _BL_LILAC_DRV_RUNNER_RDD_DEFS_H
+#define _BL_LILAC_DRV_RUNNER_RDD_DEFS_H
+
+#include "rdpa_types.h"
+#include "rdpa_cpu_basic.h"
+#include "rdd_data_structures_auto.h"
+
+/* Dependency in rdd_wl4908_partial_legacy_conv.h */
+typedef enum {
+    rdd_egress_phy_eth_lan = 0,
+    rdd_egress_phy_wlan,
+    rdd_egress_phy_wan_start,
+    rdd_egress_phy_eth_wan = rdd_egress_phy_wan_start,
+    rdd_egress_phy_dsl,
+    rdd_egress_phy_gpon = rdd_egress_phy_eth_wan,
+    rdd_egress_phy_max   /* can only support 4 types */
+} rdd_egress_phy_t;
+
+#if defined(WL4908)
+#include "rdd_wl4908_partial_legacy_conv.h"
+#endif
+
+/* Runner Device Driver Errors */
+typedef enum
+{
+    BL_LILAC_RDD_OK                                                          = 0,
+    BL_LILAC_RDD_ERROR_MALLOC_FAILED                                         = 10,
+    BL_LILAC_RDD_ERROR_ILLEGAL_BRIDGE_PORT_ID                                = 11,
+    BL_LILAC_RDD_ERROR_ILLEGAL_EMAC_ID                                       = 12,
+    BL_LILAC_RDD_ERROR_ILLEGAL_QUEUE_ID                                      = 13,
+    BL_LILAC_RDD_ERROR_ILLEGAL_WAN_CHANNEL_ID                                = 14,
+    BL_LILAC_RDD_ERROR_ILLEGAL_RATE_CONTROLLER_ID                            = 15,
+    BL_LILAC_RDD_ERROR_ILLEGAL_RATE_SHAPER_ID                                = 16,
+    BL_LILAC_RDD_ERROR_ILLEGAL_POLICER_ID                                    = 17,
+    BL_LILAC_RDD_ERROR_ILLEGAL_DIRECTION                                     = 18,
+    BL_LILAC_RDD_ERROR_ILLEGAL_RUNNER_ID                                     = 19,
+    BL_LILAC_RDD_ERROR_RATE_CONTROLLERS_POOL_OVERFLOW                        = 50,
+    BL_LILAC_RDD_ERROR_RATE_CONTROLLER_NOT_CONFIGURED                        = 52,
+    BL_LILAC_RDD_ERROR_RATE_SHAPER_NOT_CONFIGURED                            = 55,
+    BL_LILAC_RDD_ERROR_GPON_TX_QUEUES_POOL_OVERFLOW                          = 70,
+    BL_LILAC_RDD_ERROR_GPON_TX_QUEUE_NOT_CONFIGURED                          = 72,
+    BL_LILAC_RDD_ERROR_GPON_TX_QUEUE_EMPTY                                   = 73,
+    BL_LILAC_RDD_ERROR_CPU_RX_QUEUE_ILLEGAL                                  = 100,
+    BL_LILAC_RDD_ERROR_CPU_RX_REASON_ILLEGAL                                 = 101,
+    BL_LILAC_RDD_ERROR_CPU_RX_QUEUE_EMPTY                                    = 102,
+    BL_LILAC_RDD_ERROR_CPU_RX_QUEUE_INVALID                                  = 103,
+    BL_LILAC_RDD_ERROR_CPU_TX_QUEUE_FULL                                     = 120,
+    BL_LILAC_RDD_ERROR_CPU_TX_NOT_ALLOWED                                    = 122,
+    BL_LILAC_RDD_ERROR_PCI_TX_QUEUE_EMPTY                                    = 130,
+    BL_LILAC_RDD_ERROR_PCI_QUEUE_THRESHOLD_TOO_SMALL                         = 131,
+    BL_LILAC_RDD_ERROR_ADD_LOOKUP_ENTRY                                      = 150,
+    BL_LILAC_RDD_ERROR_REMOVE_LOOKUP_ENTRY                                   = 151,
+    BL_LILAC_RDD_ERROR_GET_LOOKUP_ENTRY                                      = 152,
+    BL_LILAC_RDD_ERROR_LOOKUP_ENTRY_EXISTS                                   = 153,
+    BL_LILAC_RDD_ERROR_HASH_TABLE_NO_EMPTY_ENTRY                             = 156,
+    BL_LILAC_RDD_ERROR_HASH_TABLE_NO_MATCHING_KEY                            = 157,
+    BL_LILAC_RDD_ERROR_ADD_LOOKUP_NO_EMPTY_ENTRY                             = 158,
+    BL_LILAC_RDD_ERROR_ILLEGAL_MAC_ENTRY_ID                                  = 160,
+    BL_LILAC_RDD_ERROR_GET_MAC_ENTRY                                         = 161,
+    BL_LILAC_RDD_ERROR_MAC_ENTRY_EXISTS                                      = 162,
+    BL_LILAC_RDD_ERROR_MAC_ENTRY_DOESNT_EXIST                                = 163,
+    BL_LILAC_RDD_ERROR_ILLEGAL_ARP_ENTRY_ID                                  = 170,
+    BL_LILAC_RDD_ERROR_ILLEGAL_IPTV_ENTRY_ID                                 = 175,
+    BL_LILAC_RDD_ERROR_INGRESS_CLASSIFICATION_CFG_FULL                       = 180,
+    BL_LILAC_RDD_ERROR_INGRESS_CLASSIFICATION_CFG_ILEGGAL_GROUP_SORT         = 181,
+    BL_LILAC_RDD_ERROR_INGRESS_CLASSIFICATION_CFG_NOT_EXIST                  = 182,
+    BL_LILAC_RDD_ERROR_INGRESS_CLASSIFICATION_CFG_KEY_TOO_LONG               = 183,
+    BL_LILAC_RDD_ERROR_INGRESS_CLASSIFICATION_CFG_LONG_TABLE_FULL            = 184,
+    BL_LILAC_RDD_ERROR_CAM_LOOKUP_TABLE_FULL                                 = 200,
+    BL_LILAC_RDD_ERROR_CAM_LOOKUP_TABLE_EMPTY                                = 201,
+    BL_LILAC_RDD_ERROR_CAM_LOOKUP_FAILED                                     = 202,
+    BL_LILAC_RDD_ERROR_CAM_INSERTION_FAILED                                  = 203,
+    BL_LILAC_RDD_ERROR_BPM_ALLOC_FAIL                                        = 230,
+    BL_LILAC_RDD_ERROR_BPM_FREE_FAIL                                         = 231,
+    BL_LILAC_RDD_ERROR_ILLEGAL_PBITS                                         = 300,
+    BL_LILAC_RDD_ERROR_ILLEGAL_TRAFFIC_CLASS                                 = 301,
+    BL_LILAC_RDD_ERROR_ILLEGAL_WAN_MAPPING_TABLE_INDEX                       = 302,
+    BL_LILAC_RDD_ERROR_ILLEGAL_PBITS_TO_WAN_FLOW_MAPPING_TABLE               = 303,
+    BL_LILAC_RDD_ERROR_ADD_CONTEXT_ENTRY                                     = 350,
+    BL_LILAC_RDD_ERROR_CONTEXT_ENTRY_INVALID                                 = 351,
+    BL_LILAC_RDD_ERROR_ILLEGAL_SUBNET_ID                                     = 360,
+    BL_LILAC_RDD_ERROR_IPTV_TABLE_ENTRY_EXISTS                               = 400,
+    BL_LILAC_RDD_ERROR_IPTV_FORWARDING_TABLE_FULL                            = 401,
+    BL_LILAC_RDD_ERROR_IPTV_SRC_IP_COUNTER_NOT_ZERO                          = 402,
+    BL_LILAC_RDD_ERROR_IPTV_WITH_SRC_IP_ANY_EXISTS                           = 403,
+    BL_LILAC_RDD_ERROR_IPTV_TABLE_ENTRY_NOT_EXISTS                           = 404,
+    BL_LILAC_RDD_ERROR_ILLEGAL_IPTV_TABLE_CACHE_SIZE                         = 405,
+    BL_LILAC_RDD_ERROR_IPTV_SRC_IP_TABLE_FULL                                = 406,
+    BL_LILAC_RDD_ERROR_IPTV_CONTEXT_TABLES_TABLE_FULL                        = 407,
+    BL_LILAC_RDD_ERROR_DDR_CONTEXT_TABLE_TABLE_FULL                          = 408,
+    BL_LILAC_RDD_ERROR_TIMER_TASK_TABLE_FULL                                 = 440,
+    BL_LILAC_RDD_ERROR_TIMER_TASK_PERIOD                                     = 441,
+    BL_LILAC_RDD_ERROR_NO_FREE_SKB                                           = 450,
+    BL_LILAC_RDD_ERROR_1588_TX                                               = 451,
+    BL_LILAC_RDD_ERROR_NO_FREE_GSODESC                                       = 452,
+    BL_LILAC_RDD_ERROR_SPDSVC_RESOURCE_BUSY                                  = 453,
+    BL_LILAC_RDD_ERROR_INGRESS_RATE_LIMITER_BUDGET_TOO_LARGE                 = 460,
+    BL_LILAC_RDD_ERROR_INGRESS_RATE_LIMITER_FLOW_CONTROL_THRESHOLD_TOO_LARGE = 461,
+    BL_LILAC_RDD_ERROR_GPON_SNIFFER_NULL_PD_PTR                              = 500,
+    BL_LILAC_RDD_ERROR_SMC_PPS_SEND_LEN_LESS_THEN_3                          = 600,
+    BL_LILAC_RDD_ERROR_SMC_INVALID_SEND_LENGTH                               = 601,
+    BL_LILAC_RDD_ERROR_SMC_INVALID_RECEIVE_LENGTH                            = 602,
+    BL_LILAC_RDD_ERROR_MTU_INVALID_LENGTH                                    = 603,
+    BL_LILAC_RDD_ERROR_ILLEGAL_IPSEC_SA_DESC_TABLE_INDEX                     = 700,
+    BL_LILAC_RDD_ERROR_IPSEC_AUTH_ALG_INVALID                                = 701,
+    BL_LILAC_RDD_ERROR_IPSEC_CRYPT_ALG_INVALID                               = 702,
+    BL_LILAC_RDD_ERROR_IPSEC_CRYPT_MECH_INVALID                              = 703,
+    BL_LILAC_RDD_ERROR_IPSEC_CRYPT_NXTHDR_INVALID                            = 704,
+    BL_LILAC_RDD_ERROR_IPHOST_TABLE_INDEX_INVALID                            = 705,
+    BL_LILAC_RDD_ERROR_HOST_MAC_TABLE_INDEX_INVALID                          = 706,
+}
+BL_LILAC_RDD_ERROR_DTE;
+
+
+#define BL_LILAC_RDD_IS_WAN_BRIDGE_PORT(__port)                         \
+    ( (__port) == BL_LILAC_RDD_WAN0_BRIDGE_PORT || (__port) == BL_LILAC_RDD_WAN1_BRIDGE_PORT )
+typedef enum
+{
+    BL_LILAC_RDD_WAN0_BRIDGE_PORT           = 0, /* DSL WAN */
+    BL_LILAC_RDD_WAN1_BRIDGE_PORT           = 1, /* ETH WAN */
+    BL_LILAC_RDD_LAN0_BRIDGE_PORT           = 2,
+    BL_LILAC_RDD_LAN1_BRIDGE_PORT           = 3,
+    BL_LILAC_RDD_LAN2_BRIDGE_PORT           = 4,
+    BL_LILAC_RDD_LAN3_BRIDGE_PORT           = 5,
+    BL_LILAC_RDD_LAN4_BRIDGE_PORT           = 6,
+    BL_LILAC_RDD_LAN5_BRIDGE_PORT           = 7,
+    BL_LILAC_RDD_LAN6_BRIDGE_PORT           = 8,
+    BL_LILAC_RDD_LAN7_BRIDGE_PORT           = 9,
+    BL_LILAC_RDD_VIRTUAL_BRIDGE_PORT        = 10, /* Used to represent switch IMP Port */
+    BL_LILAC_RDD_ANY_BRIDGE_PORT            = 11, /* matches any port, used by Speed Service */
+    BL_LILAC_RDD_CPU_BRIDGE_PORT            = 12,
+    BL_LILAC_RDD_PCI_BRIDGE_PORT            = 13, /* must match DRV_BPM_SP_SPARE_1 */
+    BL_LILAC_RDD_WAN_QUASI_BRIDGE_PORT      = 15,
+    BL_LILAC_RDD_WAN_ROUTER_PORT            = 17,
+    BL_LILAC_RDD_WAN_IPTV_BRIDGE_PORT       = 18,
+    BL_LILAC_RDD_MULTICAST_LAN0_BRIDGE_PORT = 0x10,
+    BL_LILAC_RDD_MULTICAST_LAN1_BRIDGE_PORT = 0x20,
+    BL_LILAC_RDD_MULTICAST_LAN2_BRIDGE_PORT = 0x40,
+    BL_LILAC_RDD_MULTICAST_LAN3_BRIDGE_PORT = 0x80,
+    BL_LILAC_RDD_MULTICAST_LAN4_BRIDGE_PORT = 0x100,
+    BL_LILAC_RDD_MULTICAST_PCI_BRIDGE_PORT  = 0x200,
+}
+BL_LILAC_RDD_BRIDGE_PORT_DTE;
+
+#define BL_LILAC_RDD_WAN_BRIDGE_PORT BL_LILAC_RDD_WAN0_BRIDGE_PORT
+
+typedef enum
+{
+    BL_LILAC_RDD_WAN_PHYSICAL_PORT_GPON = 0,
+    BL_LILAC_RDD_WAN_PHYSICAL_PORT_ETH4 = 1,
+    BL_LILAC_RDD_WAN_PHYSICAL_PORT_ETH5 = 2,
+    BL_LILAC_RDD_WAN_PHYSICAL_PORT_ETH0 = 3,
+    BL_LILAC_RDD_WAN_PHYSICAL_PORT_EPON = 4,
+    BL_LILAC_RDD_WAN_PHYSICAL_PORT_DSL  = 5,
+}
+BL_LILAC_RDD_WAN_PHYSICAL_PORT_DTE;
+
+
+#if defined(WL4908)
+#define BL_LILAC_RDD_EMAC_ID_START RDD_EMAC_FIRST
+#define BL_LILAC_RDD_EMAC_ID_PCI RDD_EMAC_ID_WIFI
+#define BL_LILAC_RDD_EMAC_ID_0 RDD_EMAC_ID_0
+#define BL_LILAC_RDD_EMAC_ID_1 RDD_EMAC_ID_1
+#define BL_LILAC_RDD_EMAC_ID_2 RDD_EMAC_ID_2
+#define BL_LILAC_RDD_EMAC_ID_3 RDD_EMAC_ID_3
+#define BL_LILAC_RDD_EMAC_ID_4 RDD_EMAC_ID_4
+#define BL_LILAC_RDD_EMAC_ID_5 RDD_EMAC_ID_5
+#define BL_LILAC_RDD_EMAC_ID_6 RDD_EMAC_ID_6
+#define BL_LILAC_RDD_EMAC_ID_7 RDD_EMAC_ID_7
+#define BL_LILAC_RDD_EMAC_ID_COUNT RDD_EMAC_ID_COUNT
+typedef rdd_rdd_emac  BL_LILAC_RDD_EMAC_ID_DTE;
+#else
+typedef enum
+{
+    BL_LILAC_RDD_EMAC_ID_START = 0,
+    BL_LILAC_RDD_EMAC_ID_PCI  = 0,
+    BL_LILAC_RDD_EMAC_ID_0    = 1,
+    BL_LILAC_RDD_EMAC_ID_1    = 2,
+    BL_LILAC_RDD_EMAC_ID_2    = 3,
+    BL_LILAC_RDD_EMAC_ID_3    = 4,
+    BL_LILAC_RDD_EMAC_ID_4    = 5,
+#if defined(DSL_63138) || defined(DSL_63148)
+    BL_LILAC_RDD_EMAC_ID_5   = 6,
+    BL_LILAC_RDD_EMAC_ID_6   = 7,
+    BL_LILAC_RDD_EMAC_ID_7   = 8,
+#endif
+    BL_LILAC_RDD_EMAC_ID_COUNT   ,
+}
+BL_LILAC_RDD_EMAC_ID_DTE;
+#endif
+
+#define RDD_WAN0_VPORT       RDD_VPORT_ID_0
+#define RDD_LAN0_VPORT       RDD_VPORT_ID_1
+#define RDD_LAN1_VPORT       RDD_VPORT_ID_2
+#define RDD_LAN2_VPORT       RDD_VPORT_ID_3
+#define RDD_LAN3_VPORT       RDD_VPORT_ID_4
+#define RDD_LAN4_VPORT       RDD_VPORT_ID_5
+#define RDD_LAN5_VPORT       RDD_VPORT_ID_6
+#define RDD_LAN6_VPORT       RDD_VPORT_ID_7
+#if !defined(WL4908)
+#define RDD_LAN_VPORT_LAST   RDD_LAN6_VPORT
+#endif
+#define RDD_WLAN0_VPORT      RDD_VPORT_ID_8
+
+typedef rdd_rdd_emac rdd_emac_id_t;
+
+typedef uint32_t rdd_emac_id_vector_t;
+
+static inline rdd_emac_id_vector_t rdd_emac_id_to_vector(rdd_emac_id_t emac, bdmf_boolean is_iptv)
+{
+    return 1LL << emac;
+}
+#define RDD_EMAC_PORT_TO_VECTOR(rdd_emac_id, is_iptv) rdd_emac_id_to_vector(rdd_emac_id, is_iptv)
+
+typedef enum
+{
+    RDD_WAN_CHANNEL_UNASSIGNED = -1,
+    RDD_WAN_CHANNEL_0  = 0,
+    RDD_WAN_CHANNEL_1  = 1,
+    RDD_WAN_CHANNEL_2  = 2,
+    RDD_WAN_CHANNEL_3  = 3,
+    RDD_WAN_CHANNEL_4  = 4,
+    RDD_WAN_CHANNEL_5  = 5,
+    RDD_WAN_CHANNEL_6  = 6,
+    RDD_WAN_CHANNEL_7  = 7,
+    RDD_WAN_CHANNEL_8  = 8,
+    RDD_WAN_CHANNEL_9  = 9,
+    RDD_WAN_CHANNEL_10 = 10,
+    RDD_WAN_CHANNEL_11 = 11,
+    RDD_WAN_CHANNEL_12 = 12,
+    RDD_WAN_CHANNEL_13 = 13,
+    RDD_WAN_CHANNEL_14 = 14,
+    RDD_WAN_CHANNEL_15 = 15,
+    RDD_WAN_CHANNEL_16 = 16,
+    RDD_WAN_CHANNEL_17 = 17,
+    RDD_WAN_CHANNEL_18 = 18,
+    RDD_WAN_CHANNEL_19 = 19,
+    RDD_WAN_CHANNEL_20 = 20,
+    RDD_WAN_CHANNEL_21 = 21,
+    RDD_WAN_CHANNEL_22 = 22,
+    RDD_WAN_CHANNEL_23 = 23,
+    RDD_WAN_CHANNEL_24 = 24,
+    RDD_WAN_CHANNEL_25 = 25,
+    RDD_WAN_CHANNEL_26 = 26,
+    RDD_WAN_CHANNEL_27 = 27,
+    RDD_WAN_CHANNEL_28 = 28,
+    RDD_WAN_CHANNEL_29 = 29,
+    RDD_WAN_CHANNEL_30 = 30,
+    RDD_WAN_CHANNEL_31 = 31,
+    RDD_WAN_CHANNEL_32 = 32,
+    RDD_WAN_CHANNEL_33 = 33,
+    RDD_WAN_CHANNEL_34 = 34,
+    RDD_WAN_CHANNEL_35 = 35,
+    RDD_WAN_CHANNEL_36 = 36,
+    RDD_WAN_CHANNEL_37 = 37,
+    RDD_WAN_CHANNEL_38 = 38,
+    RDD_WAN_CHANNEL_39 = 39,
+}
+RDD_WAN_CHANNEL_ID;
+
+#define RDD_WAN0_CHANNEL_BASE               RDD_WAN_CHANNEL_1
+#define RDD_WAN1_CHANNEL_BASE               RDD_WAN_CHANNEL_0
+
+typedef enum
+{
+    BL_LILAC_RDD_RATE_CONTROLLER_UNASSIGNED = -1,
+    BL_LILAC_RDD_RATE_CONTROLLER_0  = 0,
+    BL_LILAC_RDD_RATE_CONTROLLER_1  = 1,
+    BL_LILAC_RDD_RATE_CONTROLLER_2  = 2,
+    BL_LILAC_RDD_RATE_CONTROLLER_3  = 3,
+    BL_LILAC_RDD_RATE_CONTROLLER_4  = 4,
+    BL_LILAC_RDD_RATE_CONTROLLER_5  = 5,
+    BL_LILAC_RDD_RATE_CONTROLLER_6  = 6,
+    BL_LILAC_RDD_RATE_CONTROLLER_7  = 7,
+    BL_LILAC_RDD_RATE_CONTROLLER_8  = 8,
+    BL_LILAC_RDD_RATE_CONTROLLER_9  = 9,
+    BL_LILAC_RDD_RATE_CONTROLLER_10 = 10,
+    BL_LILAC_RDD_RATE_CONTROLLER_11 = 11,
+    BL_LILAC_RDD_RATE_CONTROLLER_12 = 12,
+    BL_LILAC_RDD_RATE_CONTROLLER_13 = 13,
+    BL_LILAC_RDD_RATE_CONTROLLER_14 = 14,
+    BL_LILAC_RDD_RATE_CONTROLLER_15 = 15,
+    BL_LILAC_RDD_RATE_CONTROLLER_16 = 16,
+    BL_LILAC_RDD_RATE_CONTROLLER_17 = 17,
+    BL_LILAC_RDD_RATE_CONTROLLER_18 = 18,
+    BL_LILAC_RDD_RATE_CONTROLLER_19 = 19,
+    BL_LILAC_RDD_RATE_CONTROLLER_20 = 20,
+    BL_LILAC_RDD_RATE_CONTROLLER_21 = 21,
+    BL_LILAC_RDD_RATE_CONTROLLER_22 = 22,
+    BL_LILAC_RDD_RATE_CONTROLLER_23 = 23,
+    BL_LILAC_RDD_RATE_CONTROLLER_24 = 24,
+    BL_LILAC_RDD_RATE_CONTROLLER_25 = 25,
+    BL_LILAC_RDD_RATE_CONTROLLER_26 = 26,
+    BL_LILAC_RDD_RATE_CONTROLLER_27 = 27,
+    BL_LILAC_RDD_RATE_CONTROLLER_28 = 28,
+    BL_LILAC_RDD_RATE_CONTROLLER_29 = 29,
+    BL_LILAC_RDD_RATE_CONTROLLER_30 = 30,
+    BL_LILAC_RDD_RATE_CONTROLLER_31 = 31,
+    BL_LILAC_RDD_RATE_CONTROLLER_32 = 32,
+    BL_LILAC_RDD_RATE_CONTROLLER_33 = 33,
+    BL_LILAC_RDD_RATE_CONTROLLER_34 = 34,
+    BL_LILAC_RDD_RATE_CONTROLLER_35 = 35,
+    BL_LILAC_RDD_RATE_CONTROLLER_36 = 36,
+    BL_LILAC_RDD_RATE_CONTROLLER_37 = 37,
+    BL_LILAC_RDD_RATE_CONTROLLER_38 = 38,
+    BL_LILAC_RDD_RATE_CONTROLLER_39 = 39,
+    BL_LILAC_RDD_RATE_CONTROLLER_40 = 40,
+    BL_LILAC_RDD_RATE_CONTROLLER_41 = 41,
+    BL_LILAC_RDD_RATE_CONTROLLER_42 = 42,
+    BL_LILAC_RDD_RATE_CONTROLLER_43 = 43,
+    BL_LILAC_RDD_RATE_CONTROLLER_44 = 44,
+    BL_LILAC_RDD_RATE_CONTROLLER_45 = 45,
+    BL_LILAC_RDD_RATE_CONTROLLER_46 = 46,
+    BL_LILAC_RDD_RATE_CONTROLLER_47 = 47,
+    BL_LILAC_RDD_RATE_CONTROLLER_48 = 48,
+    BL_LILAC_RDD_RATE_CONTROLLER_49 = 49,
+    BL_LILAC_RDD_RATE_CONTROLLER_50 = 50,
+    BL_LILAC_RDD_RATE_CONTROLLER_51 = 51,
+    BL_LILAC_RDD_RATE_CONTROLLER_52 = 52,
+    BL_LILAC_RDD_RATE_CONTROLLER_53 = 53,
+    BL_LILAC_RDD_RATE_CONTROLLER_54 = 54,
+    BL_LILAC_RDD_RATE_CONTROLLER_55 = 55,
+    BL_LILAC_RDD_RATE_CONTROLLER_56 = 56,
+    BL_LILAC_RDD_RATE_CONTROLLER_57 = 57,
+    BL_LILAC_RDD_RATE_CONTROLLER_58 = 58,
+    BL_LILAC_RDD_RATE_CONTROLLER_59 = 59,
+    BL_LILAC_RDD_RATE_CONTROLLER_60 = 60,
+    BL_LILAC_RDD_RATE_CONTROLLER_61 = 61,
+    BL_LILAC_RDD_RATE_CONTROLLER_62 = 62,
+    BL_LILAC_RDD_RATE_CONTROLLER_63 = 63,
+    BL_LILAC_RDD_RATE_CONTROLLER_64 = 64,
+    BL_LILAC_RDD_RATE_CONTROLLER_65 = 65,
+    BL_LILAC_RDD_RATE_CONTROLLER_66 = 66,
+    BL_LILAC_RDD_RATE_CONTROLLER_67 = 67,
+    BL_LILAC_RDD_RATE_CONTROLLER_68 = 68,
+    BL_LILAC_RDD_RATE_CONTROLLER_69 = 69,
+    BL_LILAC_RDD_RATE_CONTROLLER_70 = 70,
+    BL_LILAC_RDD_RATE_CONTROLLER_71 = 71,
+    BL_LILAC_RDD_RATE_CONTROLLER_72 = 72,
+    BL_LILAC_RDD_RATE_CONTROLLER_73 = 73,
+    BL_LILAC_RDD_RATE_CONTROLLER_74 = 74,
+    BL_LILAC_RDD_RATE_CONTROLLER_75 = 75,
+    BL_LILAC_RDD_RATE_CONTROLLER_76 = 76,
+    BL_LILAC_RDD_RATE_CONTROLLER_77 = 77,
+    BL_LILAC_RDD_RATE_CONTROLLER_78 = 78,
+    BL_LILAC_RDD_RATE_CONTROLLER_79 = 79,
+    BL_LILAC_RDD_RATE_CONTROLLER_80 = 80,
+    BL_LILAC_RDD_RATE_CONTROLLER_81 = 81,
+    BL_LILAC_RDD_RATE_CONTROLLER_82 = 82,
+    BL_LILAC_RDD_RATE_CONTROLLER_83 = 83,
+    BL_LILAC_RDD_RATE_CONTROLLER_84 = 84,
+    BL_LILAC_RDD_RATE_CONTROLLER_85 = 85,
+    BL_LILAC_RDD_RATE_CONTROLLER_86 = 86,
+    BL_LILAC_RDD_RATE_CONTROLLER_87 = 87,
+    BL_LILAC_RDD_RATE_CONTROLLER_88 = 88,
+    BL_LILAC_RDD_RATE_CONTROLLER_89 = 89,
+    BL_LILAC_RDD_RATE_CONTROLLER_90 = 90,
+    BL_LILAC_RDD_RATE_CONTROLLER_91 = 91,
+    BL_LILAC_RDD_RATE_CONTROLLER_92 = 92,
+    BL_LILAC_RDD_RATE_CONTROLLER_93 = 93,
+    BL_LILAC_RDD_RATE_CONTROLLER_94 = 94,
+    BL_LILAC_RDD_RATE_CONTROLLER_95 = 95,
+    BL_LILAC_RDD_RATE_CONTROLLER_96 = 96,
+    BL_LILAC_RDD_RATE_CONTROLLER_97 = 97,
+    BL_LILAC_RDD_RATE_CONTROLLER_98 = 98,
+    BL_LILAC_RDD_RATE_CONTROLLER_99 = 99,
+    BL_LILAC_RDD_RATE_CONTROLLER_100 = 100,
+    BL_LILAC_RDD_RATE_CONTROLLER_101 = 101,
+    BL_LILAC_RDD_RATE_CONTROLLER_102 = 102,
+    BL_LILAC_RDD_RATE_CONTROLLER_103 = 103,
+    BL_LILAC_RDD_RATE_CONTROLLER_104 = 104,
+    BL_LILAC_RDD_RATE_CONTROLLER_105 = 105,
+    BL_LILAC_RDD_RATE_CONTROLLER_106 = 106,
+    BL_LILAC_RDD_RATE_CONTROLLER_107 = 107,
+    BL_LILAC_RDD_RATE_CONTROLLER_108 = 108,
+    BL_LILAC_RDD_RATE_CONTROLLER_109 = 109,
+    BL_LILAC_RDD_RATE_CONTROLLER_110 = 110,
+    BL_LILAC_RDD_RATE_CONTROLLER_111 = 111,
+    BL_LILAC_RDD_RATE_CONTROLLER_112 = 112,
+    BL_LILAC_RDD_RATE_CONTROLLER_113 = 113,
+    BL_LILAC_RDD_RATE_CONTROLLER_114 = 114,
+    BL_LILAC_RDD_RATE_CONTROLLER_115 = 115,
+    BL_LILAC_RDD_RATE_CONTROLLER_116 = 116,
+    BL_LILAC_RDD_RATE_CONTROLLER_117 = 117,
+    BL_LILAC_RDD_RATE_CONTROLLER_118 = 118,
+    BL_LILAC_RDD_RATE_CONTROLLER_119 = 119,
+    BL_LILAC_RDD_RATE_CONTROLLER_120 = 120,
+    BL_LILAC_RDD_RATE_CONTROLLER_121 = 121,
+    BL_LILAC_RDD_RATE_CONTROLLER_122 = 122,
+    BL_LILAC_RDD_RATE_CONTROLLER_123 = 123,
+    BL_LILAC_RDD_RATE_CONTROLLER_124 = 124,
+    BL_LILAC_RDD_RATE_CONTROLLER_125 = 125,
+    BL_LILAC_RDD_RATE_CONTROLLER_126 = 126,
+    BL_LILAC_RDD_RATE_CONTROLLER_127 = 127,
+}
+BL_LILAC_RDD_RATE_CONTROLLER_ID_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_QUEUE_0 = 0,
+    BL_LILAC_RDD_QUEUE_1 = 1,
+    BL_LILAC_RDD_QUEUE_2 = 2,
+    BL_LILAC_RDD_QUEUE_3 = 3,
+    BL_LILAC_RDD_QUEUE_4 = 4,
+    BL_LILAC_RDD_QUEUE_5 = 5,
+    BL_LILAC_RDD_QUEUE_6 = 6,
+    BL_LILAC_RDD_QUEUE_7 = 7,
+    BL_LILAC_RDD_QUEUE_LAST = 7,
+}
+BL_LILAC_RDD_QUEUE_ID_DTE;
+
+
+typedef enum
+{
+    RDD_WAN_CHANNEL_SCHEDULE_PRIORITY     = 0,
+    RDD_WAN_CHANNEL_SCHEDULE_RATE_CONTROL = 1,
+}
+RDD_WAN_CHANNEL_SCHEDULE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_CPU_RX_QUEUE_0 = 0,
+    BL_LILAC_RDD_CPU_RX_QUEUE_1 = 1,
+    BL_LILAC_RDD_CPU_RX_QUEUE_2 = 2,
+    BL_LILAC_RDD_CPU_RX_QUEUE_3 = 3,
+    BL_LILAC_RDD_CPU_RX_QUEUE_4 = 4,
+    BL_LILAC_RDD_CPU_RX_QUEUE_5 = 5,
+    BL_LILAC_RDD_CPU_RX_QUEUE_6 = 6,
+    BL_LILAC_RDD_CPU_RX_QUEUE_7 = 7,
+}
+BL_LILAC_RDD_CPU_RX_QUEUE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_PCI_TX_QUEUE_0 = 8,
+    BL_LILAC_RDD_PCI_TX_QUEUE_1 = 9,
+    BL_LILAC_RDD_PCI_TX_QUEUE_2 = 10,
+    BL_LILAC_RDD_PCI_TX_QUEUE_3 = 11,
+}
+BL_LILAC_RDD_PCI_TX_QUEUE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_CPU_METER_0       = 0,
+    BL_LILAC_RDD_CPU_METER_1       = 1,
+    BL_LILAC_RDD_CPU_METER_2       = 2,
+    BL_LILAC_RDD_CPU_METER_3       = 3,
+    BL_LILAC_RDD_CPU_METER_4       = 4,
+    BL_LILAC_RDD_CPU_METER_5       = 5,
+    BL_LILAC_RDD_CPU_METER_6       = 6,
+    BL_LILAC_RDD_CPU_METER_7       = 7,
+    BL_LILAC_RDD_CPU_METER_8       = 8,
+    BL_LILAC_RDD_CPU_METER_9       = 9,
+    BL_LILAC_RDD_CPU_METER_10      = 10,
+    BL_LILAC_RDD_CPU_METER_11      = 11,
+    BL_LILAC_RDD_CPU_METER_12      = 12,
+    BL_LILAC_RDD_CPU_METER_13      = 13,
+    BL_LILAC_RDD_CPU_METER_14      = 14,
+    BL_LILAC_RDD_CPU_METER_15      = 15,
+    BL_LILAC_RDD_CPU_METER_DISABLE = 16,
+}
+BL_LILAC_RDD_CPU_METER_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_STATIC_MAC_ADDRESS = 0,
+    BL_LILAC_RDD_BRIDGE_MAC_ADDRESS = 1,
+}
+BL_LILAC_RDD_MAC_ENTRY_TYPE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_DISABLED = 0,
+    BL_LILAC_RDD_ENABLED  = 1,
+}
+BL_LILAC_RDD_CONTROL_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_PPPOE_DISABLED = 0,
+    BL_LILAC_RDD_PPPOE_ENABLED  = 1,
+}
+BL_LILAC_RDD_PPPOE_ENABLE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_DUAL_STACK_LITE_DISABLED = 0,
+    BL_LILAC_RDD_DUAL_STACK_LITE_ENABLED  = 1,
+}
+BL_LILAC_RDD_DUAL_STACK_LITE_ENABLE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_IPV6_DISABLED = 0,
+    BL_LILAC_RDD_IPV6_ENABLED  = 1,
+}
+BL_LILAC_RDD_IPV6_ENABLE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_FORWARD_DISABLE = 0,
+    BL_LILAC_RDD_FORWARD_ENABLE  = 1,
+}
+BL_LILAC_RDD_FORWARD_MATRIX_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_VLAN_SWITCHING_DISABLE = 0,
+    BL_LILAC_RDD_VLAN_SWITCHING_ENABLE  = 1,
+}
+BL_LILAC_RDD_VLAN_SWITCHING_CONFIG_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_VLAN_BINDING_DISABLE = 0,
+    BL_LILAC_RDD_VLAN_BINDING_ENABLE  = 1,
+}
+BL_LILAC_RDD_VLAN_BINDING_CONFIG_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_AGGREGATION_MODE_DISABLED = 0,
+    BL_LILAC_RDD_AGGREGATION_MODE_ENABLED  = 1,
+}
+BL_LILAC_RDD_AGGREGATION_MODE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_BRIDGE_PORT_VECTOR_PCI  = 0x1,
+    BL_LILAC_RDD_BRIDGE_PORT_VECTOR_LAN0 = 0x2,
+    BL_LILAC_RDD_BRIDGE_PORT_VECTOR_LAN1 = 0x4,
+    BL_LILAC_RDD_BRIDGE_PORT_VECTOR_LAN2 = 0x8,
+    BL_LILAC_RDD_BRIDGE_PORT_VECTOR_LAN3 = 0x10,
+    BL_LILAC_RDD_BRIDGE_PORT_VECTOR_LAN4 = 0x20,
+}
+BL_LILAC_RDD_BRIDGE_PORT_VECTOR_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_SUBNET_CLASSIFY_ETHERNET_FLOW = 0,
+    BL_LILAC_RDD_SUBNET_CLASSIFY_MAC_FILTER    = 1,
+}
+BL_LILAC_RDD_SUBNET_CLASSIFY_MODE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_SUBNET_FLOW_CACHE  = 0,
+    BL_LILAC_RDD_SUBNET_BRIDGE      = 1,
+    BL_LILAC_RDD_SUBNET_BRIDGE_IPTV = 2,
+    BL_LILAC_RDD_SUBNET_LAN         = 2,
+}
+BL_LILAC_RDD_SUBNET_ID_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_DS_RATE_CONTROL_DISABLE = 0,
+    BL_LILAC_RDD_DS_RATE_CONTROL_ENABLE  = 1,
+}
+BL_LILAC_RDD_DS_RATE_CONTROL_MODE_DTE;
+
+typedef enum
+{
+    RDD_RATE_LIMITER_EMAC_0                 = 0,
+    RDD_RATE_LIMITER_EMAC_1                 = 1,
+    RDD_RATE_LIMITER_EMAC_2                 = 2,
+    RDD_RATE_LIMITER_EMAC_3                 = 3,
+    RDD_RATE_LIMITER_EMAC_4                 = 4,
+    RDD_RATE_LIMITER_EMAC_5                 = 5,
+    RDD_RATE_LIMITER_EMAC_LAST              = 5,
+    RDD_RATE_LIMITER_SERVICE_QUEUE_0        = 6,
+    RDD_RATE_LIMITER_SERVICE_QUEUE_1        = 7,
+    RDD_RATE_LIMITER_SERVICE_QUEUE_2        = 8,
+    RDD_RATE_LIMITER_SERVICE_QUEUE_3        = 9,
+    RDD_RATE_LIMITER_SERVICE_QUEUE_4        = 10,
+    RDD_RATE_LIMITER_SERVICE_QUEUE_5        = 11,
+    RDD_RATE_LIMITER_SERVICE_QUEUE_6        = 12,
+    RDD_RATE_LIMITER_SERVICE_QUEUE_7        = 13,
+    RDD_RATE_LIMITER_SERVICE_QUEUE_OVERALL  = 14,
+    RDD_RATE_LIMITER_IDLE                   = 15,
+}
+RDD_RATE_LIMITER_ID_DTE;
+
+typedef enum
+{
+    BL_LILAC_RDD_POLICER_0        = 0,
+    BL_LILAC_RDD_POLICER_1        = 1,
+    BL_LILAC_RDD_POLICER_2        = 2,
+    BL_LILAC_RDD_POLICER_3        = 3,
+    BL_LILAC_RDD_POLICER_4        = 4,
+    BL_LILAC_RDD_POLICER_5        = 5,
+    BL_LILAC_RDD_POLICER_6        = 6,
+    BL_LILAC_RDD_POLICER_7        = 7,
+    BL_LILAC_RDD_POLICER_8        = 8,
+    BL_LILAC_RDD_POLICER_9        = 9,
+    BL_LILAC_RDD_POLICER_10       = 10,
+    BL_LILAC_RDD_POLICER_11       = 11,
+    BL_LILAC_RDD_POLICER_12       = 12,
+    BL_LILAC_RDD_POLICER_13       = 13,
+    BL_LILAC_RDD_POLICER_14       = 14,
+    BL_LILAC_RDD_POLICER_15       = 15,
+    BL_LILAC_RDD_POLICER_DISABLED = 16,
+}
+BL_LILAC_RDD_POLICER_ID_DTE;
+
+
+#define BL_LILAC_RDD_IPV4_ADDRESS_BYTE_SIZE     ( 4 )
+#define BL_LILAC_RDD_IPV6_ADDRESS_BYTE_SIZE     ( 16 )
+
+
+typedef enum
+{
+    BL_LILAC_RDD_FILTER_DISABLE = 0,
+    BL_LILAC_RDD_FILTER_ENABLE  = 1,
+}
+BL_LILAC_RDD_FILTER_MODE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_RATE_LIMITER_DISABLE = 0,
+    BL_LILAC_RDD_RATE_LIMITER_ENABLE  = 1,
+}
+BL_LILAC_RDD_RATE_LIMITER_MODE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_RATE_LIMITER_LOW  = 0,
+    BL_LILAC_RDD_RATE_LIMITER_HIGH = 1,
+}
+BL_LILAC_RDD_RATE_LIMITER_PRIORITY_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_FILTER_ACTION_CPU_TRAP = 1,
+    BL_LILAC_RDD_FILTER_ACTION_DROP     = 2,
+}
+BL_LILAC_RDD_FILTER_ACTION_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_ETHER_TYPE_FILTER_USER_0      = 2,
+    BL_LILAC_RDD_ETHER_TYPE_FILTER_USER_1      = 3,
+    BL_LILAC_RDD_ETHER_TYPE_FILTER_USER_2      = 4,
+    BL_LILAC_RDD_ETHER_TYPE_FILTER_USER_3      = 5,
+    BL_LILAC_RDD_ETHER_TYPE_FILTER_PPPOE_D     = 6,
+    BL_LILAC_RDD_ETHER_TYPE_FILTER_PPPOE_S     = 7,
+    BL_LILAC_RDD_ETHER_TYPE_FILTER_ARP         = 8,
+    BL_LILAC_RDD_ETHER_TYPE_FILTER_1588        = 9,
+    BL_LILAC_RDD_ETHER_TYPE_FILTER_802_1X      = 10,
+    BL_LILAC_RDD_ETHER_TYPE_FILTER_802_1AG_CFM = 11,
+}
+BL_LILAC_RDD_ETHER_TYPE_FILTER_NUMBER_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_MAC_LOOKUP_DISABLE = 0,
+    BL_LILAC_RDD_MAC_LOOKUP_ENABLE  = 1,
+}
+BL_LILAC_RDD_MAC_LOOKUP_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_FLOW_BASED_FORWARDING_DISABLED = 0,
+    BL_LILAC_RDD_FLOW_BASED_FORWARDING_ENABLED  = 1,
+}
+BL_LILAC_RDD_FLOW_BASED_MODE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_MAC_FWD_ACTION_FORWARD    = 0,
+    BL_LILAC_RDD_MAC_FWD_ACTION_DROP       = 1,
+    BL_LILAC_RDD_MAC_FWD_ACTION_CPU_TRAP0  = 2,
+    BL_LILAC_RDD_MAC_FWD_ACTION_CPU_TRAP1  = 3,
+    BL_LILAC_RDD_MAC_FWD_ACTION_CPU_TRAP2  = 4,
+    BL_LILAC_RDD_MAC_FWD_ACTION_CPU_TRAP3  = 5,
+    BL_LILAC_RDD_MAC_FWD_ACTION_RATE_LIMIT = 6,
+}
+BL_LILAC_RDD_MAC_FWD_ACTION_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_ACL_LAYER3_FILTER_DISABLE                      = 0,
+    BL_LILAC_RDD_ACL_LAYER3_FILTER_SRC_IP_INCLUSIVE             = 2,
+    BL_LILAC_RDD_ACL_LAYER3_FILTER_SRC_IP_EXCLUSIVE             = 3,
+    BL_LILAC_RDD_ACL_LAYER3_FILTER_SRC_MAC_SRC_IP_INCLUSIVE     = 4,
+    BL_LILAC_RDD_ACL_LAYER3_FILTER_SRC_MAC_SRC_IP_EXCLUSIVE     = 5,
+    BL_LILAC_RDD_ACL_LAYER3_FILTER_SRC_MAC_VID_SRC_IP_INCLUSIVE = 8,
+    BL_LILAC_RDD_ACL_LAYER3_FILTER_SRC_MAC_VID_SRC_IP_EXCLUSIVE = 9,
+}
+BL_LILAC_RDD_ACL_LAYER3_FILTER_MODE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_CRC_CALC_DISABLE = 0,
+    BL_LILAC_RDD_CRC_CALC_ENABLE  = 1,
+}
+BL_LILAC_RDD_TX_CRC_CALC_DTE;
+
+
+typedef enum
+{
+    rdd_vlan_command_transparent                         = 0,
+    rdd_vlan_command_add_tag                             = 1,
+    rdd_vlan_command_remove_tag                          = 2,
+    rdd_vlan_command_replace_tag                         = 3,
+    rdd_vlan_command_add_two_tags                        = 4,
+    rdd_vlan_command_remove_two_tags                     = 5,
+    rdd_vlan_command_add_outer_tag_replace_inner_tag     = 6,
+    rdd_vlan_command_remove_outer_tag_replace_inner_tag  = 7,
+    rdd_vlan_command_add_tag_always                      = 8,
+    rdd_vlan_command_remove_tag_always                   = 9,
+    rdd_vlan_command_replace_outer_tag_replace_inner_tag = 10,
+    rdd_vlan_command_remove_outer_tag_copy               = 11,
+    rdd_vlan_command_add_3rd_tag                         = 12,
+    rdd_max_vlan_command                                 = 13,
+}
+rdd_bridge_vlan_command;
+
+
+typedef enum
+{
+    rdd_pbits_command_transparent = 0,
+    rdd_pbits_command_copy        = 1,
+    rdd_pbits_command_configured  = 2,
+    rdd_pbits_command_remap       = 3,
+    rdd_max_pbits_command         = 4,
+}
+rdd_bridge_pbits_command;
+
+
+typedef enum
+{
+    rdd_tpid_id_0   = 0,
+    rdd_tpid_id_1   = 1,
+    rdd_tpid_id_2   = 2,
+    rdd_tpid_id_3   = 3,
+    rdd_tpid_id_4   = 4,
+    rdd_tpid_id_5   = 5,
+    rdd_tpid_id_6   = 6,
+    rdd_tpid_id_7   = 7,
+}
+rdd_tpid_id;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_UNKNOWN_MAC_CMD_FORWARD  = 1,
+    BL_LILAC_RDD_UNKNOWN_MAC_CMD_CPU_TRAP = 2,
+    BL_LILAC_RDD_UNKNOWN_MAC_CMD_DROP     = 4,
+    BL_LILAC_RDD_UNKNOWN_MAC_CMD_FLOOD    = 8,
+}
+BL_LILAC_RDD_UNKNOWN_MAC_COMMAND_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_MAC_TABLE_SIZE_32   = 0,
+    BL_LILAC_RDD_MAC_TABLE_SIZE_64   = 1,
+    BL_LILAC_RDD_MAC_TABLE_SIZE_128  = 2,
+    BL_LILAC_RDD_MAC_TABLE_SIZE_256  = 3,
+    BL_LILAC_RDD_MAC_TABLE_SIZE_512  = 4,
+    BL_LILAC_RDD_MAC_TABLE_SIZE_1024 = 5,
+    BL_LILAC_RDD_MAC_TABLE_SIZE_2048 = 6,
+    BL_LILAC_RDD_MAC_TABLE_SIZE_4096 = 7,
+}
+BL_LILAC_RDD_MAC_TABLE_SIZE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_MAC_TABLE_MAX_HOP_1    = 0,
+    BL_LILAC_RDD_MAC_TABLE_MAX_HOP_2    = 1,
+    BL_LILAC_RDD_MAC_TABLE_MAX_HOP_4    = 2,
+    BL_LILAC_RDD_MAC_TABLE_MAX_HOP_8    = 3,
+    BL_LILAC_RDD_MAC_TABLE_MAX_HOP_16   = 4,
+    BL_LILAC_RDD_MAC_TABLE_MAX_HOP_32   = 5,
+    BL_LILAC_RDD_MAC_TABLE_MAX_HOP_64   = 6,
+    BL_LILAC_RDD_MAC_TABLE_MAX_HOP_128  = 7,
+    BL_LILAC_RDD_MAC_TABLE_MAX_HOP_256  = 8,
+    BL_LILAC_RDD_MAC_TABLE_MAX_HOP_512  = 9,
+    BL_LILAC_RDD_MAC_TABLE_MAX_HOP_1024 = 10,
+}
+BL_LILAC_RDD_MAC_TABLE_MAX_HOP_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_IGMP_FILTER_NUMBER        = 0,
+    BL_LILAC_RDD_ICMPV6_FILTER_NUMBER      = 1,
+    BL_LILAC_RDD_USER_0_FILTER_NUMBER      = 2,
+    BL_LILAC_RDD_USER_1_FILTER_NUMBER      = 3,
+    BL_LILAC_RDD_USER_2_FILTER_NUMBER      = 4,
+    BL_LILAC_RDD_USER_3_FILTER_NUMBER      = 5,
+    BL_LILAC_RDD_PPPOE_D_FILTER_NUMBER     = 6,
+    BL_LILAC_RDD_PPPOE_S_FILTER_NUMBER     = 7,
+    BL_LILAC_RDD_ARP_FILTER_NUMBER         = 8,
+    BL_LILAC_RDD_1588_FILTER_NUMBER        = 9,
+    BL_LILAC_RDD_802_1X_FILTER_NUMBER      = 10,
+    BL_LILAC_RDD_802_1AG_CFM_FILTER_NUMBER = 11,
+    BL_LILAC_RDD_BROADCAST_FILTER_NUMBER   = 12,
+    BL_LILAC_RDD_MULTICAST_FILTER_NUMBER   = 13,
+    BL_LILAC_RDD_STOP_FILTER_NUMBER        = 14,
+    BL_LILAC_RDD_INGRESS_FILTERS_NUMBER    = 14,
+}
+BL_LILAC_RDD_INGRESS_FILTER_DTE;
+
+
+typedef enum
+{
+    RDD_LAYER4_FILTER_ERROR             = 0,
+    RDD_LAYER4_FILTER_EXCEPTION         = 1,
+    RDD_LAYER4_FILTER_IP_FIRST_FRAGMENT = 2,
+    RDD_LAYER4_FILTER_IP_FRAGMENT       = 3,
+    RDD_LAYER4_FILTER_GRE               = 4,
+    RDD_LAYER4_FILTER_LAYER3_IPV4       = 5,
+    RDD_LAYER4_FILTER_LAYER3_IPV6       = 6,
+    RDD_LAYER4_FILTER_ICMP              = 7,
+    RDD_LAYER4_FILTER_ESP               = 8,
+    RDD_LAYER4_FILTER_AH                = 9,
+    RDD_LAYER4_FILTER_IPV6              = 10,
+    RDD_LAYER4_FILTER_USER_DEFINED_0    = 11,
+    RDD_LAYER4_FILTER_USER_DEFINED_1    = 12,
+    RDD_LAYER4_FILTER_USER_DEFINED_2    = 13,
+    RDD_LAYER4_FILTER_USER_DEFINED_3    = 14,
+    RDD_LAYER4_FILTER_UNKNOWN           = 15,
+}
+RDD_LAYER4_FILTER_INDEX;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_LAYER4_FILTER_FORWARD  = 0,
+    BL_LILAC_RDD_LAYER4_FILTER_CPU_TRAP = 1,
+    BL_LILAC_RDD_LAYER4_FILTER_DROP     = 2,
+}
+BL_LILAC_RDD_LAYER4_FILTER_ACTION_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_FIREWALL_PROTOCOL_TYPE_TCP = 0,
+    BL_LILAC_RDD_FIREWALL_PROTOCOL_TYPE_UDP = 1,
+}
+BL_LILAC_RDD_FIREWALL_PROTOCOL_TYPE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_FLOW_CACHE_PBIT_ACTION_DSCP_COPY  = 0,
+    BL_LILAC_RDD_FLOW_CACHE_PBIT_ACTION_OUTER_COPY = 1,
+    BL_LILAC_RDD_FLOW_CACHE_PBIT_ACTION_INNER_COPY = 2,
+}
+BL_LILAC_RDD_FLOW_CACHE_PBIT_ACTION_DTE;
+
+
+typedef enum
+{
+    RDD_FLOW_CACHE_FORWARD_ACTION_CPU  = 0,
+    RDD_FLOW_CACHE_FORWARD_ACTION_DROP = 1,
+}
+RDD_FLOW_CACHE_FORWARD_ACTION;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_ACL_LAYER2_ACTION_DENY   = 0,
+    BL_LILAC_RDD_ACL_LAYER2_ACTION_ACCEPT = 1,
+}
+BL_LILAC_RDD_ACL_LAYER2_ACTION_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_1588_MODE_DISABLE = 0,
+    BL_LILAC_RDD_1588_MODE_ENABLE  = 1,
+}
+BL_LILAC_RDD_1588_MODE_DTE;
+
+
+typedef enum
+{
+    RDD_1588_TX_THREAD_RETURN_NO_RESULT = 0,
+    RDD_1588_TX_THREAD_RETURN_SUCCESS   = 1,
+    RDD_1588_TX_THREAD_RETURN_FAIL      = 2,
+}
+RDD_1588_TX_THREAD_RESULT_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_INTER_LAN_SCHEDULING_MODE_NORMAL          = 0,
+    BL_LILAC_RDD_INTER_LAN_SCHEDULING_MODE_STRICT_PRIORITY = 1,
+    BL_LILAC_RDD_INTER_LAN_SCHEDULING_MODE_ROUND_ROBIN     = 2,
+}
+BL_LILAC_RDD_INTER_LAN_SCHEDULING_MODE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_UPSTREAM_PADDING_DISABLE = 0,
+    BL_LILAC_RDD_UPSTREAM_PADDING_ENABLE  = 1,
+}
+BL_LILAC_RDD_UPSTREAM_PADDING_MODE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_NO_WAIT = 0,
+    BL_LILAC_RDD_WAIT    = 1,
+}
+BL_LILAC_RDD_CPU_WAIT_DTE;
+
+
+typedef enum
+{
+    RDD_US_PEAK_SCHEDULING_MODE_ROUND_ROBIN     = 0,
+    RDD_US_PEAK_SCHEDULING_MODE_STRICT_PRIORITY = 1,
+}
+RDD_US_PEAK_SCHEDULING_MODE;
+
+
+typedef enum
+{
+    rdd_queue_profile_0         = 0,
+    rdd_queue_profile_1         = 1,
+    rdd_queue_profile_2         = 2,
+    rdd_queue_profile_3         = 3,
+    rdd_queue_profile_4         = 4,
+    rdd_queue_profile_5         = 5,
+    rdd_queue_profile_6         = 6,
+    rdd_queue_profile_7         = 7,
+    rdd_queue_profile_disabled  = 8,
+} rdd_queue_profile;
+
+
+typedef struct
+{
+    uint16_t  min_threshold;
+    uint16_t  max_threshold;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PRIORITY_CLASS_THRESHOLDS;
+
+
+typedef struct
+{
+    RDD_PRIORITY_CLASS_THRESHOLDS  high_priority_class;
+    RDD_PRIORITY_CLASS_THRESHOLDS  low_priority_class;
+    uint32_t                       max_drop_probability;
+    bdmf_boolean                   us_flow_control_mode;                         
+
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_QUEUE_PROFILE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_FLOW_PM_COUNTERS_RX   = 1,
+    BL_LILAC_RDD_FLOW_PM_COUNTERS_TX   = 2,
+    BL_LILAC_RDD_FLOW_PM_COUNTERS_BOTH = 3,
+}
+BL_LILAC_RDD_FLOW_PM_COUNTERS_TYPE_DTE;
+
+
+typedef struct
+{
+    uint32_t  good_rx_packet;
+    uint32_t  good_rx_bytes;
+    uint32_t  good_tx_packet;
+    uint32_t  good_tx_bytes;
+    uint16_t  error_rx_packets_discard;
+    uint16_t  error_tx_packets_discard;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ BL_LILAC_RDD_FLOW_PM_COUNTERS_DTE;
+
+
+typedef struct
+{
+    uint32_t  good_tx_packet;
+    uint16_t  error_tx_packets_discard;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SERVICE_QUEUE_PM_COUNTERS_DTE;
+
+
+typedef struct
+{
+    uint32_t  rx_valid;
+    uint32_t  tx_valid;
+    uint16_t  error_rx_bpm_congestion;
+    uint16_t  bridge_filtered_packets;
+    uint16_t  bridge_tx_packets_discard;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ BL_LILAC_RDD_BRIDGE_PORT_PM_COUNTERS_DTE;
+
+
+typedef struct
+{
+    uint32_t  good_rx_packet;
+    uint32_t  good_tx_packet;
+    uint32_t  good_rx_bytes;
+    uint32_t  good_tx_bytes;
+    uint16_t  rx_dropped_packet;
+    uint16_t  tx_dropped_packet;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ BL_LILAC_RDD_SUBNET_PM_COUNTERS_DTE;
+
+
+typedef struct
+{
+    uint16_t  invalid_layer2_protocol_drop;
+    uint16_t  firewall_drop;
+    uint16_t  acl_oui_drop;
+    uint16_t  acl_l2_drop;
+    uint16_t  acl_l3_drop;
+    uint16_t  dst_mac_non_router_drop;
+    uint16_t  eth_flow_action_drop;
+    uint16_t  sa_lookup_failure_drop;
+    uint16_t  da_lookup_failure_drop;
+    uint16_t  sa_action_drop;
+    uint16_t  da_action_drop;
+    uint16_t  forwarding_matrix_disabled_drop;
+    uint16_t  connection_action_drop;
+    uint16_t  iptv_layer3_drop;
+    uint16_t  local_switching_congestion;
+    uint16_t  vlan_switching_drop;
+    uint16_t  downstream_policers_drop;
+    uint16_t  layer4_filters_drop[ 16 ];
+    uint16_t  ingress_filters_drop[ BL_LILAC_RDD_INGRESS_FILTERS_NUMBER ];
+    uint16_t  ip_validation_filter_drop[ 2 ];
+    uint16_t  emac_loopback_drop;
+    uint16_t  tpid_detect_drop;
+    uint16_t  dual_stack_lite_congestion_drop;
+    uint16_t  invalid_subnet_ip_drop;
+    uint16_t  us_ddr_queue_drop;
+    uint16_t  ds_parallel_processing_no_avialable_slave;
+    uint16_t  ds_parallel_processing_reorder_slaves;
+    uint16_t  absolute_address_list_overflow_drop;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ BL_LILAC_RDD_VARIOUS_COUNTERS_DTE;
+
+
+typedef enum
+{
+    INVALID_LAYER2_PROTOCOL_DROP_COUNTER_MASK    = 0x1,
+    FIREWALL_DROP_COUNTER_MASK                   = 0x2,
+    ACL_OUI_DROP_COUNTER_MASK                    = 0x4,
+    ACL_L2_DROP_COUNTER_MASK                     = 0x8,
+    ACL_L3_DROP_COUNTER_MASK                     = 0x10,
+    DST_MAC_NON_ROUTER_DROP_COUNTER_MASK         = 0x20,
+    ETHERNET_FLOW_ACTION_DROP_COUNTER_MASK       = 0x40,
+    SA_LOOKUP_FAILURE_DROP_COUNTER_MASK          = 0x80,
+    DA_LOOKUP_FAILURE_DROP_COUNTER_MASK          = 0x100,
+    SA_ACTION_DROP_COUNTER_MASK                  = 0x200,
+    DA_ACTION_DROP_COUNTER_MASK                  = 0x400,
+    FORWARDING_MATRIX_DISABLED_DROP_COUNTER_MASK = 0x800,
+    CONNECTION_ACTION_DROP_COUNTER_MASK          = 0x1000,
+    IPTV_LAYER3_DROP_COUNTER_MASK                = 0x2000,
+    LOCAL_SWITCHING_CONGESTION_COUNTER_MASK      = 0x4000,
+    VLAN_SWITCHING_DROP_COUNTER_MASK             = 0x8000,
+    DOWNSTREAM_POLICERS_DROP_COUNTER_MASK        = 0x10000,
+    LAYER4_FILTERS_DROP_COUNTER_MASK             = 0x20000,
+    INGRESS_FILTERS_DROP_COUNTER_MASK            = 0x40000,
+    IP_VALIDATION_FILTER_DROP_COUNTER_MASK       = 0x80000,
+    EMAC_LOOPBACK_DROP_COUNTER_MASK              = 0x100000,
+    TPID_DETECT_DROP_COUNTER_MASK                = 0x200000,
+    DUAL_STACK_LITE_CONGESTION_DROP_COUNTER_MASK = 0x400000,
+    INVALID_SUBNET_IP_DROP_COUNTER_MASK          = 0x800000,
+    EPON_DDR_QUEUEU_DROP_COUNTER_MASK            = 0x800000,
+    ABSOLUTE_ADDRESS_LIST_OVERFLOW_MASK          = 0x1000000,
+}
+RDD_VARIOUS_COUNTERS_MASK;
+
+typedef enum
+{
+    RDD_CHIP_REVISION_A0 = 0,
+    RDD_CHIP_REVISION_B0 = 1,
+}
+BL_LILAC_RDD_CHIP_REVISION_DTE;
+
+#if defined(WL4908)
+typedef struct
+{
+    uint8_t                             *ddr_bm_ptr;
+    uint32_t                            ddr_bm_phys;
+    uint32_t                            ddr1_bm_phys;
+    uint8_t                             *ddr_fm_ptr;
+    uint32_t                            ddr_fm_phys;
+    BL_LILAC_RDD_MAC_TABLE_SIZE_DTE     mac_table_size;
+    BL_LILAC_RDD_MAC_TABLE_SIZE_DTE     iptv_table_size;
+    BL_LILAC_RDD_WAN_PHYSICAL_PORT_DTE  wan_physical_port;
+    uint32_t                            ddr_headroom_size;
+    int16_t                             broadcom_switch_mode;
+    BL_LILAC_RDD_BRIDGE_PORT_DTE        broadcom_switch_physical_port;
+    uint32_t                            bridge_flow_cache_mode;
+    BL_LILAC_RDD_CHIP_REVISION_DTE      chip_revision;
+    uint16_t                            cpu_tx_abs_packet_limit;
+    uint8_t                             *runner_nat_cache_key_ptr; /*Virtual address*/
+    uint8_t                             *runner_nat_cache_context_ptr; /*Virtual address*/
+    uint8_t                             *runner_context_cont_ptr; /*Virtual address*/
+    uint16_t                            token_size;
+    uint8_t                             lp_mode;
+}
+RDD_INIT_PARAMS;
+#else
+typedef struct
+{
+    uint8_t                             *ddr_pool_ptr;       /* virtual address */
+    uint32_t                            ddr_pool_ptr_phys;   /* physical address */
+    uint8_t                             *extra_ddr_pool_ptr; /* virtual address */
+    uint32_t                            extra_ddr_pool_ptr_phys; /* physical address */
+    uint8_t                             *ddr_runner_tables_ptr;  /* virtual address */
+    uint32_t                            ddr_runner_tables_ptr_phys; /* physical address */
+    BL_LILAC_RDD_MAC_TABLE_SIZE_DTE     mac_table_size;
+    BL_LILAC_RDD_MAC_TABLE_SIZE_DTE     iptv_table_size;
+    BL_LILAC_RDD_WAN_PHYSICAL_PORT_DTE  wan_physical_port;
+    uint32_t                            ddr_headroom_size;
+    int16_t                             broadcom_switch_mode;
+    BL_LILAC_RDD_BRIDGE_PORT_DTE        broadcom_switch_physical_port;
+    uint32_t                            bridge_flow_cache_mode;
+    uint16_t                            epon_post_scheduling_queue_size;
+    BL_LILAC_RDD_CHIP_REVISION_DTE      chip_revision;
+    uint16_t                            cpu_tx_abs_packet_limit;
+    BL_LILAC_RDD_BRIDGE_PORT_DTE        lan_direct_to_cpu_port;
+    uint8_t                             lp_mode;
+}
+RDD_INIT_PARAMS;
+#endif
+
+
+typedef struct
+{
+    uint32_t  rate;
+    uint32_t  limit;
+}
+RDD_RATE_LIMIT_PARAMS;
+
+typedef struct
+{
+    uint32_t               sustain_budget;
+    RDD_RATE_LIMIT_PARAMS  peak_budget;
+    uint32_t               peak_weight;
+}
+RDD_RATE_CONTROLLER_PARAMS;
+
+
+typedef struct
+{
+    BL_LILAC_RDD_SUBNET_ID_DTE               subnet_id;
+    BL_LILAC_RDD_FIREWALL_PROTOCOL_TYPE_DTE  protocol;
+    uint32_t                                 dst_port;
+    uint32_t                                 dst_port_last;
+    bdmf_ip_t                                src_ip;
+    uint32_t                                 src_ip_mask;
+    bdmf_ip_t                                dst_ip;
+    uint32_t                                 check_mask_src_ip;
+    uint32_t                                 check_src_ip;
+    uint32_t                                 check_dst_ip;
+    uint32_t                                 next_rule_index;
+}
+RDD_FIREWALL_RULE_PARAMS;
+
+
+typedef struct
+{
+    bdmf_mac_t                         mac_addr;
+    uint16_t                           vlan_id;
+    BL_LILAC_RDD_BRIDGE_PORT_DTE       bridge_port;
+    BL_LILAC_RDD_MAC_ENTRY_TYPE_DTE    entry_type;
+    BL_LILAC_RDD_AGGREGATION_MODE_DTE  aggregation_mode;
+    uint8_t                            extension_entry;
+    BL_LILAC_RDD_MAC_FWD_ACTION_DTE    sa_action;
+    BL_LILAC_RDD_MAC_FWD_ACTION_DTE    da_action;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_MAC_PARAMS;
+
+
+typedef struct
+{
+    uint16_t                             vid;
+    BL_LILAC_RDD_BRIDGE_PORT_VECTOR_DTE  isolation_mode_port_vector;
+    BL_LILAC_RDD_BRIDGE_PORT_VECTOR_DTE  aggregation_mode_port_vector;
+    uint16_t                             aggregation_vid_index;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_LAN_VID_PARAMS;
+
+
+typedef struct
+{
+    uint8_t                       *packet_ptr;
+    uint32_t                      packet_size;
+    BL_LILAC_RDD_BRIDGE_PORT_DTE  src_bridge_port;
+    uint8_t                       wifi_src_ssid_index;
+    uint16_t                      wifi_dst_ssid_vector;
+    uint16_t                      buffer_number;
+}
+RDD_PCI_TX_PARAMS;
+
+
+typedef struct
+{
+    uint8_t                         *packet_ptr;
+    uint32_t                        packet_size;
+    BL_LILAC_RDD_BRIDGE_PORT_DTE    src_bridge_port;
+    uint32_t                        flow_id;
+    rdpa_cpu_reason                 reason;
+    uint16_t                        buffer_number;
+}
+RDD_CPU_RX_PARAMS;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_UPSTREAM_FLOW_CLASSIFY_VID                = 0,
+    BL_LILAC_RDD_UPSTREAM_FLOW_CLASSIFY_VID_PBITS          = 0,
+    BL_LILAC_RDD_UPSTREAM_FLOW_CLASSIFY_VID_SRC_PORT       = 1,
+    BL_LILAC_RDD_UPSTREAM_FLOW_CLASSIFY_VID_PBITS_SRC_PORT = 2,
+}
+BL_LILAC_RDD_UPSTREAM_FLOW_CLASSIFY_MODE_DTE;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_DOWNSTREAM_FLOW_CLASSIFY_WAN_FLOW = 0,
+    BL_LILAC_RDD_DOWNSTREAM_FLOW_CLASSIFY_PACKET   = 1,
+}
+BL_LILAC_RDD_DOWNSTREAM_FLOW_CLASSIFY_MODE_DTE;
+
+typedef struct
+{
+	uint32_t                                vlan_command_id;
+    rdd_bridge_vlan_command                 vlan_command;
+    rdd_bridge_pbits_command                pbits_command;
+    uint16_t                                outer_vid;
+    uint16_t                                inner_vid;
+    uint8_t                                 outer_pbits;
+    uint8_t                                 inner_pbits;
+	bdmf_boolean                            outer_tpid_overwrite_enable;
+	bdmf_boolean                            inner_tpid_overwrite_enable;
+    rdd_tpid_id                             outer_tpid_id; 
+    rdd_tpid_id                             inner_tpid_id; 
+}
+rdd_vlan_command_params;
+
+typedef enum
+{
+    rdd_dei_command_transparent                         = 0,
+    rdd_dei_command_clear                               = 1,
+    rdd_dei_command_set                                 = 2,
+}
+rdd_dei_command;
+
+/** Ingress classification lookup mode */
+typedef enum
+{
+    rdd_ingress_classification_lookup_mode_ih        = 0,
+    rdd_ingress_classification_lookup_mode_optimized = 1,
+    rdd_ingress_classification_lookup_mode_short     = 2,
+    rdd_ingress_classification_lookup_mode_long      = 3,
+} rdd_ingress_classification_lookup_mode;
+
+/** Full flow cache corner case acceleration modes */
+typedef enum
+{
+    rdd_full_fc_acceleration_non_ip       = 0,
+    rdd_full_fc_acceleration_multicast_ip = 1,
+} rdd_full_fc_acceleration_mode;
+
+typedef enum
+{
+    rdd_single_priority_mode = 0,
+    rdd_double_priority_mode = 1,
+} rdd_policer_mode;
+
+
+
+/** CPU TX redesign **/
+typedef enum
+{
+    rdd_cpu_tx_queue_table_fast_a = 0,
+    rdd_cpu_tx_queue_table_fast_b = 1,
+    rdd_cpu_tx_queue_table_pico_a = 2,
+    rdd_cpu_tx_queue_table_pico_b = 3,
+} rdd_cpu_tx_queue_table;
+
+
+typedef enum
+{
+    rdd_cpu_tx_mode_full         = 0,
+    rdd_cpu_tx_mode_interworking = 1,
+    rdd_cpu_tx_mode_egress_enq   = 2,
+} rdd_cpu_tx_mode;
+
+
+typedef enum
+{
+    rdd_host_buffer   = 0,
+    rdd_runner_buffer = 1,
+} rdd_buffer_type;
+
+typedef struct
+{
+    rdpa_traffic_dir  traffic_dir;
+    rdd_cpu_tx_mode   mode;
+    rdd_buffer_type   buffer_type;
+
+    uint8_t   wifi_ssid;
+    uint16_t  wan_flow;
+    rdpa_discard_prty  drop_precedence;
+
+    union 
+    {
+        struct 
+        {
+#if defined(LEGACY_RDP)
+            BL_LILAC_RDD_EMAC_ID_DTE   emac_id;
+#else
+            rdd_emac_id_t              emac_id;
+#endif
+            BL_LILAC_RDD_QUEUE_ID_DTE  queue_id;
+            bdmf_boolean               en_1588;
+        } ds;
+
+        struct
+        {
+            uint32_t                      wan_channel;
+            uint32_t                      rate_controller;
+            uint32_t                      queue;
+            BL_LILAC_RDD_BRIDGE_PORT_DTE  src_bridge_port;
+        } us;
+    } direction;
+    int is_spdsvc_setup_packet;
+} rdd_cpu_tx_args_t;
+
+static inline uint32_t rdd_rate_to_alloc_unit(uint32_t rate, uint32_t period)
+{
+    /* original algorithm cannot provide enough token for the rate */
+#if 0
+    return ((rate + ((1000000 / period) / 2)) / (1000000 / period));
+#endif
+    return rate;
+}
+
+typedef void ( * BL_LILAC_RDD_LOCK_CRITICAL_SECTION_FP_DTE )( bdmf_fastlock * );
+typedef void ( * BL_LILAC_RDD_UNLOCK_CRITICAL_SECTION_FP_DTE )( bdmf_fastlock * );
+typedef void ( * BL_LILAC_RDD_LOCK_CRITICAL_SECTION_FP_IRQ_DTE )( bdmf_fastlock *, unsigned long * );
+typedef void ( * BL_LILAC_RDD_UNLOCK_CRITICAL_SECTION_FP_IRQ_DTE )( bdmf_fastlock *, unsigned long );
+
+#endif
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_ih_defs.h b/arch/arm/mach-bcmbca/rdp/rdd_ih_defs.h
new file mode 100755
index 0000000000..8dc822b644
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_ih_defs.h
@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+/**** This is an autogenerated file with definitions common to FW and SW ****/
+
+#ifndef _RDD_IH_DEFS_H
+#define _RDD_IH_DEFS_H
+
+#include "rdd_runner_defs.h"
+#include "rdp_drv_ih.h"
+
+/* default runner for DS */
+#define DRV_RDD_IH_DS_DEFAULT_RUNNER   ( DRV_IH_RUNNER_CLUSTER_A )/* constant */
+/* default runner for US */
+#define DRV_RDD_IH_US_DEFAULT_RUNNER   ( DRV_IH_RUNNER_CLUSTER_B )/* constant */
+
+/* common for all ports */
+#define DRV_RDD_IH_PACKET_HEADER_OFFSET   ( 18 )
+
+#define DRV_RDD_IH_RUNNER_0_MAXIMAL_NUMBER_OF_BUFFERS   ( 32 )
+#define DRV_RDD_IH_RUNNER_1_MAXIMAL_NUMBER_OF_BUFFERS   ( 32 )
+
+#define DRV_RDD_IH_CAM_SEARCH_ENABLE_UPON_INVALID_LUT_ENTRY   ( 0 )/* constant */
+
+#define DRV_RDD_IH_RUNNER_0_IH_MANAGED_RB_BASE_ADDRESS   ( 0x0 )
+#define DRV_RDD_IH_RUNNER_1_IH_MANAGED_RB_BASE_ADDRESS   ( 0x0 )
+
+/* not in use in 1st phase */
+#define DRV_RDD_IH_RUNNER_0_RUNNER_MANAGED_RB_BASE_ADDRESS   ( 0 )/* constant */
+#define DRV_RDD_IH_RUNNER_1_RUNNER_MANAGED_RB_BASE_ADDRESS   ( 0 )/* constant */
+
+/* not in use in 1st phase */
+#define DRV_RDD_IH_RUNNER_0_IH_CONGESTION_REPORT_ADDRESS   ( 0 )/* constant */
+#define DRV_RDD_IH_RUNNER_1_IH_CONGESTION_REPORT_ADDRESS   ( 0 )/* constant */
+
+/* not in use in 1st phase */
+#define DRV_RDD_IH_RUNNER_0_IH_CONGESTION_REPORT_ENABLE   ( 0 )/* constant */
+#define DRV_RDD_IH_RUNNER_1_IH_CONGESTION_REPORT_ENABLE   ( 0 )/* constant */
+
+/* Lookup tables configuration */
+
+#define DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX			( DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_1 )
+#define DRV_RDD_IH_LOOKUP_TABLE_IPTV_INDEX			( DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_2 )
+#define DRV_RDD_IH_LOOKUP_TABLE_DS_INGRESS_CLASSIFICATION_INDEX			( DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_3 )
+#define DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX			( DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_4 )
+#define DRV_RDD_IH_LOOKUP_TABLE_IPTV_SRC_IP_INDEX			( DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_BROADCOM_SWITCH_LAN_INDEX			( DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_8 )
+#define DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX			( DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_9 )
+
+#define DRV_RDD_IH_LOOKUP_TABLE_1_BASE_ADDRESS   MAC_TABLE_ADDRESS
+#define DRV_RDD_IH_LOOKUP_TABLE_2_BASE_ADDRESS   ( 0x2000 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_BASE_ADDRESS   ( 0xA000 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_BASE_ADDRESS   ( 0xA800 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_BASE_ADDRESS   ( 0x3300 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_BASE_ADDRESS   MAC_TABLE_ADDRESS
+#define DRV_RDD_IH_LOOKUP_TABLE_9_BASE_ADDRESS   MAC_TABLE_ADDRESS
+
+#define DRV_RDD_IH_LOOKUP_TABLE_1_SIZE   ( DRV_IH_LOOKUP_TABLE_SIZE_64_ENTRIES )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_SIZE   ( DRV_IH_LOOKUP_TABLE_SIZE_256_ENTRIES )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_SIZE   ( DRV_IH_LOOKUP_TABLE_SIZE_256_ENTRIES )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SIZE   ( DRV_IH_LOOKUP_TABLE_SIZE_256_ENTRIES )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_SIZE   ( DRV_IH_LOOKUP_TABLE_SIZE_32_ENTRIES )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SIZE   ( DRV_IH_LOOKUP_TABLE_SIZE_64_ENTRIES )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SIZE   ( DRV_IH_LOOKUP_TABLE_SIZE_64_ENTRIES )
+
+#define DRV_RDD_IH_LOOKUP_TABLE_1_SEARCH_DEPTH   ( DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_4_STEPS )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_SEARCH_DEPTH   ( DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_32_STEPS )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_SEARCH_DEPTH   ( DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_32_STEPS )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SEARCH_DEPTH   ( DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_32_STEPS )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_SEARCH_DEPTH   ( DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_32_STEPS )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SEARCH_DEPTH   ( DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_4_STEPS )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SEARCH_DEPTH   ( DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_4_STEPS )
+
+
+/* same for all lookup tables */
+#define DRV_RDD_IH_LOOKUP_TABLE_1_HASH_TYPE   ( DRV_IH_LOOKUP_TABLE_HASH_TYPE_CRC16 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_HASH_TYPE   ( DRV_IH_LOOKUP_TABLE_HASH_TYPE_CRC16 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_HASH_TYPE   ( DRV_IH_LOOKUP_TABLE_HASH_TYPE_CRC16 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_HASH_TYPE   ( DRV_IH_LOOKUP_TABLE_HASH_TYPE_CRC16 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_HASH_TYPE   ( DRV_IH_LOOKUP_TABLE_HASH_TYPE_CRC16 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_HASH_TYPE   ( DRV_IH_LOOKUP_TABLE_HASH_TYPE_CRC16 )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_HASH_TYPE   ( DRV_IH_LOOKUP_TABLE_HASH_TYPE_CRC16 )
+
+#define DRV_RDD_IH_LOOKUP_TABLE_1_SA_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_SA_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_SA_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SA_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_SA_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SA_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SA_ENABLE   ( 1 )
+
+#define DRV_RDD_IH_LOOKUP_TABLE_1_AGING_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_AGING_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_AGING_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_AGING_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_AGING_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_AGING_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_AGING_ENABLE   ( 0 )
+
+#define DRV_RDD_IH_LOOKUP_TABLE_1_CAM_ENABLE   ( 1 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_CAM_ENABLE   ( 1 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_CAM_ENABLE   ( 1 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_CAM_ENABLE   ( 1 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_CAM_ENABLE   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_CAM_ENABLE   ( 1 )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_CAM_ENABLE   ( 1 )
+
+#define DRV_RDD_IH_LOOKUP_TABLE_1_CAM_BASE_ADDRESS   MAC_TABLE_CAM_ADDRESS
+#define DRV_RDD_IH_LOOKUP_TABLE_2_CAM_BASE_ADDRESS   ( 0x3100 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_CAM_BASE_ADDRESS   ( 0x9300 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_CAM_BASE_ADDRESS   ( 0x9C00 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_CAM_BASE_ADDRESS   ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_CAM_BASE_ADDRESS   MAC_TABLE_CAM_ADDRESS
+#define DRV_RDD_IH_LOOKUP_TABLE_9_CAM_BASE_ADDRESS   MAC_TABLE_CAM_ADDRESS
+
+#define DRV_RDD_IH_CONTEXT_TABLE_1_BASE_ADDRESS   MAC_CONTEXT_TABLE_ADDRESS
+#define DRV_RDD_IH_CONTEXT_TABLE_2_BASE_ADDRESS   ( 0x3000 )
+#define DRV_RDD_IH_CONTEXT_TABLE_3_BASE_ADDRESS   ( 0x0 )
+#define DRV_RDD_IH_CONTEXT_TABLE_4_BASE_ADDRESS   ( 0x0 )
+#define DRV_RDD_IH_CONTEXT_TABLE_6_BASE_ADDRESS   ( 0x0 )
+#define DRV_RDD_IH_CONTEXT_TABLE_8_BASE_ADDRESS   MAC_CONTEXT_TABLE_ADDRESS
+#define DRV_RDD_IH_CONTEXT_TABLE_9_BASE_ADDRESS   MAC_CONTEXT_TABLE_ADDRESS
+
+#define DRV_RDD_IH_CONTEXT_TABLE_1_ENTRY_SIZE   ( DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE_2_BYTES )
+#define DRV_RDD_IH_CONTEXT_TABLE_2_ENTRY_SIZE   ( DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE_1_BYTE )
+#define DRV_RDD_IH_CONTEXT_TABLE_3_ENTRY_SIZE   ( DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE_INTERNAL_ENTRY )
+#define DRV_RDD_IH_CONTEXT_TABLE_4_ENTRY_SIZE   ( DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE_INTERNAL_ENTRY )
+#define DRV_RDD_IH_CONTEXT_TABLE_6_ENTRY_SIZE   ( DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE_INTERNAL_ENTRY )
+#define DRV_RDD_IH_CONTEXT_TABLE_8_ENTRY_SIZE   ( DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE_2_BYTES )
+#define DRV_RDD_IH_CONTEXT_TABLE_9_ENTRY_SIZE   ( DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE_2_BYTES )
+
+#define DRV_RDD_IH_CONTEXT_TABLE_1_CAM_BASE_ADDRESS   MAC_CONTEXT_TABLE_CAM_ADDRESS
+#define DRV_RDD_IH_CONTEXT_TABLE_2_CAM_BASE_ADDRESS   ( 0x38E0 )
+#define DRV_RDD_IH_CONTEXT_TABLE_3_CAM_BASE_ADDRESS   ( 0x0 )
+#define DRV_RDD_IH_CONTEXT_TABLE_4_CAM_BASE_ADDRESS   ( 0x0 )
+#define DRV_RDD_IH_CONTEXT_TABLE_6_CAM_BASE_ADDRESS   ( 0x0 )
+#define DRV_RDD_IH_CONTEXT_TABLE_8_CAM_BASE_ADDRESS   MAC_CONTEXT_TABLE_CAM_ADDRESS
+#define DRV_RDD_IH_CONTEXT_TABLE_9_CAM_BASE_ADDRESS   MAC_CONTEXT_TABLE_CAM_ADDRESS
+
+/* Table 1: DST_MAC_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_0_START_OFFSET   ( 2 )
+#define DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_0_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_0_MASK_LOW       ( 0xFFFFFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_0_MASK_HIGH      ( 0xFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_1_DST_MAC_KEY_GLOBAL_MASK           ( 0xFFF )
+
+/* Table 9: SRC_MAC_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_0_START_OFFSET   ( 4 )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_0_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_0_MASK_LOW       ( 0xFFFFFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_0_MASK_HIGH      ( 0xFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_9_SRC_MAC_KEY_GLOBAL_MASK           ( 0xFFF )
+
+/* Table 8: SRC_MAC_BROADCOM_SWITCH_LAN_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SRC_MAC_BROADCOM_SWITCH_LAN_KEY_PART_0_START_OFFSET   ( 4 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SRC_MAC_BROADCOM_SWITCH_LAN_KEY_PART_0_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SRC_MAC_BROADCOM_SWITCH_LAN_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SRC_MAC_BROADCOM_SWITCH_LAN_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SRC_MAC_BROADCOM_SWITCH_LAN_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SRC_MAC_BROADCOM_SWITCH_LAN_KEY_PART_0_MASK_LOW       ( 0xFFFFFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SRC_MAC_BROADCOM_SWITCH_LAN_KEY_PART_0_MASK_HIGH      ( 0xFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SRC_MAC_BROADCOM_SWITCH_LAN_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SRC_MAC_BROADCOM_SWITCH_LAN_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_8_SRC_MAC_BROADCOM_SWITCH_LAN_KEY_GLOBAL_MASK           ( 0xFFF )
+
+/* Table 2: IPTV_DA_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_KEY_PART_0_START_OFFSET   ( 2 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_KEY_PART_0_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_KEY_PART_0_MASK_LOW       ( 0xFFFFFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_KEY_PART_0_MASK_HIGH      ( 0xFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_KEY_GLOBAL_MASK           ( 0xFFF )
+
+/* Table 2: IPTV_DA_VID_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_VID_KEY_PART_0_START_OFFSET   ( 2 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_VID_KEY_PART_0_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_VID_KEY_PART_1_START_OFFSET   ( 2 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_VID_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_VID_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_VID_KEY_PART_0_MASK_LOW       ( 0xFFFFFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_VID_KEY_PART_0_MASK_HIGH      ( 0xFFFFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_VID_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_VID_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_DA_VID_KEY_GLOBAL_MASK           ( 0x7FFF )
+
+/* Table 2: IPTV_L3_DIP_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_KEY_PART_0_START_OFFSET   ( 10 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_KEY_PART_0_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_KEY_PART_0_MASK_LOW       ( 0xFFFFFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_KEY_GLOBAL_MASK           ( 0xFF )
+
+/* Table 2: IPTV_L3_DIP_SIP_VID_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_SIP_VID_KEY_PART_0_START_OFFSET   ( 10 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_SIP_VID_KEY_PART_0_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_SIP_VID_KEY_PART_1_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_SIP_VID_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_SIP_VID_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_SIP_VID_KEY_PART_0_MASK_LOW       ( 0xFFFFFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_SIP_VID_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_SIP_VID_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_SIP_VID_KEY_PART_1_MASK_HIGH      ( 0xFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_2_IPTV_L3_DIP_SIP_VID_KEY_GLOBAL_MASK           ( 0x7FF )
+
+/* Table 6 */
+#define DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_0_START_OFFSET   ( 10 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_0_SHIFT          ( 8 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_0_MASK_LOW       ( 0xFFFFFFFF )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_6_KEY_GLOBAL_MASK           ( 0x1FF )
+
+/* Table 3: VID_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_0_MASK_LOW       ( 0x1FFF00 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 3: PBITS_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_KEY_PART_0_MASK_LOW       ( 0xF00000 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 3: VID_PBITS_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_KEY_PART_0_MASK_LOW       ( 0xFFFF00 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 3: VID_GEM_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_GEM_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_GEM_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_GEM_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_GEM_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_GEM_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_GEM_FLOW_ID )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_GEM_KEY_PART_0_MASK_LOW       ( 0x1FFF00 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_GEM_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_GEM_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_GEM_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_GEM_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 3: PBITS_GEM_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_GEM_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_GEM_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_GEM_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_GEM_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_GEM_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_GEM_FLOW_ID )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_GEM_KEY_PART_0_MASK_LOW       ( 0xF00000 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_GEM_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_GEM_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_GEM_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_PBITS_GEM_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 3: VID_PBITS_GEM_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_GEM_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_GEM_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_GEM_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_GEM_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_GEM_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_GEM_FLOW_ID )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_GEM_KEY_PART_0_MASK_LOW       ( 0xFFFF00 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_GEM_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_GEM_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_GEM_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_VID_PBITS_GEM_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 3: GEM_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_3_GEM_KEY_PART_0_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_GEM_KEY_PART_0_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_GEM_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_GEM_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_GEM_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_GEM_FLOW_ID )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_GEM_KEY_PART_0_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_GEM_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_GEM_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_GEM_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_3_GEM_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 4: VID_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_KEY_PART_0_MASK_LOW       ( 0x1FFF00 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 4: PBITS_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_KEY_PART_0_MASK_LOW       ( 0xF00000 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 4: VID_PBITS_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_KEY_PART_0_MASK_LOW       ( 0xFFFF00 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 4: VID_SRC_PORT_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_SOURCE_PORT )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_0_MASK_LOW       ( 0x1FFF00 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_SRC_PORT_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 4: PBITS_SRC_PORT_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_SRC_PORT_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_SRC_PORT_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_SRC_PORT_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_SRC_PORT_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_SRC_PORT_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_SOURCE_PORT )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_SRC_PORT_KEY_PART_0_MASK_LOW       ( 0xF00000 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_SRC_PORT_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_SRC_PORT_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_SRC_PORT_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_PBITS_SRC_PORT_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 4: VID_PBITS_SRC_PORT_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_SRC_PORT_KEY_PART_0_START_OFFSET   ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_SRC_PORT_KEY_PART_0_SHIFT          ( 6 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_SRC_PORT_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_SRC_PORT_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_SRC_PORT_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_SOURCE_PORT )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_SRC_PORT_KEY_PART_0_MASK_LOW       ( 0xFFFF00 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_SRC_PORT_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_SRC_PORT_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_SRC_PORT_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_VID_PBITS_SRC_PORT_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+/* Table 4: SRC_PORT_METHOD */
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SRC_PORT_KEY_PART_0_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SRC_PORT_KEY_PART_0_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SRC_PORT_KEY_PART_1_START_OFFSET   ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SRC_PORT_KEY_PART_1_SHIFT          ( 0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SRC_PORT_KEY_KEY_EXTENSION         ( DRV_IH_LOOKUP_KEY_EXTENSION_SOURCE_PORT )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SRC_PORT_KEY_PART_0_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SRC_PORT_KEY_PART_0_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SRC_PORT_KEY_PART_1_MASK_LOW       ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SRC_PORT_KEY_PART_1_MASK_HIGH      ( 0x0 )
+#define DRV_RDD_IH_LOOKUP_TABLE_4_SRC_PORT_KEY_GLOBAL_MASK           ( 0x1F3F )
+
+
+/**** Classes configuration ****/
+
+/* Classes indices */
+#define DRV_RDD_IH_CLASS_WAN_CONTROL_INDEX			( 0 )
+#define DRV_RDD_IH_CLASS_IPTV_INDEX			( 1 )
+#define DRV_RDD_IH_CLASS_PCI_INDEX			( 2 )
+#define DRV_RDD_IH_CLASS_WAN_BRIDGED_HIGH_INDEX			( 8 )
+#define DRV_RDD_IH_CLASS_WAN_BRIDGED_LOW_INDEX			( 9 )
+#define DRV_RDD_IH_CLASS_LAN_BRIDGED_ETH0_INDEX			( 10 )
+#define DRV_RDD_IH_CLASS_LAN_BRIDGED_ETH1_INDEX			( 11 )
+#define DRV_RDD_IH_CLASS_LAN_BRIDGED_ETH2_INDEX			( 12 )
+#define DRV_RDD_IH_CLASS_LAN_BRIDGED_ETH3_INDEX			( 13 )
+#define DRV_RDD_IH_CLASS_LAN_BRIDGED_ETH4_INDEX			( 14 )
+
+/* Class 0: WAN_CONTROL */
+#define DRV_RDD_IH_CLASS_0_CLASS_SEARCH_1                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX )
+#define DRV_RDD_IH_CLASS_0_CLASS_SEARCH_2                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX )
+#define DRV_RDD_IH_CLASS_0_CLASS_SEARCH_3                         ( DRV_IH_CLASS_SEARCH_DISABLED )
+#define DRV_RDD_IH_CLASS_0_CLASS_SEARCH_4                         ( DRV_RDD_IH_LOOKUP_TABLE_DS_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_0_DESTINATION_PORT_EXTRACTION            ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1 )
+#define DRV_RDD_IH_CLASS_0_DROP_ON_MISS                           ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )
+#define DRV_RDD_IH_CLASS_0_DSCP_TO_PBITS_TABLE_INDEX              ( 0 )
+#define DRV_RDD_IH_CLASS_0_DIRECT_MODE_DEFAULT                    ( 0 )
+#define DRV_RDD_IH_CLASS_0_DIRECT_MODE_OVERRIDE                   ( 0 )
+#define DRV_RDD_IH_CLASS_0_TARGET_MEMORY_DEFAULT                  ( DRV_IH_TARGET_MEMORY_DDR )
+#define DRV_RDD_IH_CLASS_0_TARGET_MEMORY_OVERRIDE                 ( 1 )
+#define DRV_RDD_IH_CLASS_0_INGRESS_QOS_DEFAULT                    ( DRV_IH_INGRESS_QOS_LOW )
+#define DRV_RDD_IH_CLASS_0_INGRESS_QOS_OVERRIDE                   ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )/* constant */
+#define DRV_RDD_IH_CLASS_0_TARGET_RUNNER_DEFAULT                  ( DRV_RDD_IH_DS_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_0_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE  ( 0 )
+#define DRV_RDD_IH_CLASS_0_TARGET_RUNNER_FOR_DIRECT_MODE          ( DRV_RDD_IH_DS_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_0_LOAD_BALANCING_ENABLE                  ( 0 )/* constant */
+#define DRV_RDD_IH_CLASS_0_PREFERENCE_LOAD_BALANCING_ENABLE       ( 0 )/* constant */
+
+/* Class 1: IPTV */
+#define DRV_RDD_IH_CLASS_1_CLASS_SEARCH_1                         ( DRV_RDD_IH_LOOKUP_TABLE_IPTV_INDEX )
+#define DRV_RDD_IH_CLASS_1_CLASS_SEARCH_2                         ( DRV_IH_CLASS_SEARCH_DISABLED )
+#define DRV_RDD_IH_CLASS_1_CLASS_SEARCH_3                         ( DRV_IH_CLASS_SEARCH_DISABLED )
+#define DRV_RDD_IH_CLASS_1_CLASS_SEARCH_4                         ( DRV_RDD_IH_LOOKUP_TABLE_DS_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_1_DESTINATION_PORT_EXTRACTION            ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )
+#define DRV_RDD_IH_CLASS_1_DROP_ON_MISS                           ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1 )
+#define DRV_RDD_IH_CLASS_1_DSCP_TO_PBITS_TABLE_INDEX              ( 0 )
+#define DRV_RDD_IH_CLASS_1_DIRECT_MODE_DEFAULT                    ( 0 )
+#define DRV_RDD_IH_CLASS_1_DIRECT_MODE_OVERRIDE                   ( 0 )
+#define DRV_RDD_IH_CLASS_1_TARGET_MEMORY_DEFAULT                  ( DRV_IH_TARGET_MEMORY_DDR )
+#define DRV_RDD_IH_CLASS_1_TARGET_MEMORY_OVERRIDE                 ( 0 )
+#define DRV_RDD_IH_CLASS_1_INGRESS_QOS_DEFAULT                    ( DRV_IH_INGRESS_QOS_LOW )
+#define DRV_RDD_IH_CLASS_1_INGRESS_QOS_OVERRIDE                   ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )/* constant */
+#define DRV_RDD_IH_CLASS_1_TARGET_RUNNER_DEFAULT                  ( DRV_RDD_IH_DS_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_1_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE  ( 0 )
+#define DRV_RDD_IH_CLASS_1_TARGET_RUNNER_FOR_DIRECT_MODE          ( DRV_RDD_IH_DS_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_1_LOAD_BALANCING_ENABLE                  ( 0 )/* constant */
+#define DRV_RDD_IH_CLASS_1_PREFERENCE_LOAD_BALANCING_ENABLE       ( 0 )/* constant */
+
+/* Class 2: PCI */
+#define DRV_RDD_IH_CLASS_2_CLASS_SEARCH_1                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX )
+#define DRV_RDD_IH_CLASS_2_CLASS_SEARCH_2                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX )
+#define DRV_RDD_IH_CLASS_2_CLASS_SEARCH_3                         ( DRV_IH_CLASS_SEARCH_DISABLED )
+#define DRV_RDD_IH_CLASS_2_CLASS_SEARCH_4                         ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_2_DESTINATION_PORT_EXTRACTION            ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1 )
+#define DRV_RDD_IH_CLASS_2_DROP_ON_MISS                           ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )
+#define DRV_RDD_IH_CLASS_2_DSCP_TO_PBITS_TABLE_INDEX              ( 0 )
+#define DRV_RDD_IH_CLASS_2_DIRECT_MODE_DEFAULT                    ( 0 )
+#define DRV_RDD_IH_CLASS_2_DIRECT_MODE_OVERRIDE                   ( 1 )
+#define DRV_RDD_IH_CLASS_2_TARGET_MEMORY_DEFAULT                  ( DRV_IH_TARGET_MEMORY_DDR )
+#define DRV_RDD_IH_CLASS_2_TARGET_MEMORY_OVERRIDE                 ( 0 )
+#define DRV_RDD_IH_CLASS_2_INGRESS_QOS_DEFAULT                    ( DRV_IH_INGRESS_QOS_LOW )
+#define DRV_RDD_IH_CLASS_2_INGRESS_QOS_OVERRIDE                   ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )/* constant */
+#define DRV_RDD_IH_CLASS_2_TARGET_RUNNER_DEFAULT                  ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_2_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE  ( 0 )
+#define DRV_RDD_IH_CLASS_2_TARGET_RUNNER_FOR_DIRECT_MODE          ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_2_LOAD_BALANCING_ENABLE                  ( 0 )/* constant */
+#define DRV_RDD_IH_CLASS_2_PREFERENCE_LOAD_BALANCING_ENABLE       ( 0 )/* constant */
+
+/* Class 8: WAN_BRIDGED_HIGH */
+#define DRV_RDD_IH_CLASS_8_CLASS_SEARCH_1                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX )
+#define DRV_RDD_IH_CLASS_8_CLASS_SEARCH_2                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX )
+#define DRV_RDD_IH_CLASS_8_CLASS_SEARCH_3                         ( DRV_IH_CLASS_SEARCH_DISABLED )
+#define DRV_RDD_IH_CLASS_8_CLASS_SEARCH_4                         ( DRV_RDD_IH_LOOKUP_TABLE_DS_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_8_DESTINATION_PORT_EXTRACTION            ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1 )
+#define DRV_RDD_IH_CLASS_8_DROP_ON_MISS                           ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )
+#define DRV_RDD_IH_CLASS_8_DSCP_TO_PBITS_TABLE_INDEX              ( 0 )
+#define DRV_RDD_IH_CLASS_8_DIRECT_MODE_DEFAULT                    ( 0 )
+#define DRV_RDD_IH_CLASS_8_DIRECT_MODE_OVERRIDE                   ( 1 )
+#define DRV_RDD_IH_CLASS_8_TARGET_MEMORY_DEFAULT                  ( DRV_IH_TARGET_MEMORY_DDR )
+#define DRV_RDD_IH_CLASS_8_TARGET_MEMORY_OVERRIDE                 ( 0 )
+#define DRV_RDD_IH_CLASS_8_INGRESS_QOS_DEFAULT                    ( DRV_IH_INGRESS_QOS_HIGH )
+#define DRV_RDD_IH_CLASS_8_INGRESS_QOS_OVERRIDE                   ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )/* constant */
+#define DRV_RDD_IH_CLASS_8_TARGET_RUNNER_DEFAULT                  ( DRV_RDD_IH_DS_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_8_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE  ( 1 )
+#define DRV_RDD_IH_CLASS_8_TARGET_RUNNER_FOR_DIRECT_MODE          ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_8_LOAD_BALANCING_ENABLE                  ( 0 )/* constant */
+#define DRV_RDD_IH_CLASS_8_PREFERENCE_LOAD_BALANCING_ENABLE       ( 0 )/* constant */
+
+/* Class 9: WAN_BRIDGED_LOW */
+#define DRV_RDD_IH_CLASS_9_CLASS_SEARCH_1                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX )
+#define DRV_RDD_IH_CLASS_9_CLASS_SEARCH_2                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX )
+#define DRV_RDD_IH_CLASS_9_CLASS_SEARCH_3                         ( DRV_IH_CLASS_SEARCH_DISABLED )
+#define DRV_RDD_IH_CLASS_9_CLASS_SEARCH_4                         ( DRV_RDD_IH_LOOKUP_TABLE_DS_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_9_DESTINATION_PORT_EXTRACTION            ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1 )
+#define DRV_RDD_IH_CLASS_9_DROP_ON_MISS                           ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )
+#define DRV_RDD_IH_CLASS_9_DSCP_TO_PBITS_TABLE_INDEX              ( 0 )
+#define DRV_RDD_IH_CLASS_9_DIRECT_MODE_DEFAULT                    ( 0 )
+#define DRV_RDD_IH_CLASS_9_DIRECT_MODE_OVERRIDE                   ( 1 )
+#define DRV_RDD_IH_CLASS_9_TARGET_MEMORY_DEFAULT                  ( DRV_IH_TARGET_MEMORY_DDR )
+#define DRV_RDD_IH_CLASS_9_TARGET_MEMORY_OVERRIDE                 ( 0 )
+#define DRV_RDD_IH_CLASS_9_INGRESS_QOS_DEFAULT                    ( DRV_IH_INGRESS_QOS_LOW )
+#define DRV_RDD_IH_CLASS_9_INGRESS_QOS_OVERRIDE                   ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )/* constant */
+#define DRV_RDD_IH_CLASS_9_TARGET_RUNNER_DEFAULT                  ( DRV_RDD_IH_DS_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_9_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE  ( 1 )
+#define DRV_RDD_IH_CLASS_9_TARGET_RUNNER_FOR_DIRECT_MODE          ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_9_LOAD_BALANCING_ENABLE                  ( 0 )/* constant */
+#define DRV_RDD_IH_CLASS_9_PREFERENCE_LOAD_BALANCING_ENABLE       ( 0 )/* constant */
+
+/* Class 10: LAN_BRIDGED_ETH0 */
+#define DRV_RDD_IH_CLASS_10_CLASS_SEARCH_1                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX )
+#define DRV_RDD_IH_CLASS_10_CLASS_SEARCH_2                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX )
+#define DRV_RDD_IH_CLASS_10_CLASS_SEARCH_3                         ( DRV_IH_CLASS_SEARCH_DISABLED )
+#define DRV_RDD_IH_CLASS_10_CLASS_SEARCH_4                         ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_10_DESTINATION_PORT_EXTRACTION            ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1 )
+#define DRV_RDD_IH_CLASS_10_DROP_ON_MISS                           ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )
+#define DRV_RDD_IH_CLASS_10_DSCP_TO_PBITS_TABLE_INDEX              ( 0 )
+#define DRV_RDD_IH_CLASS_10_DIRECT_MODE_DEFAULT                    ( 0 )
+#define DRV_RDD_IH_CLASS_10_DIRECT_MODE_OVERRIDE                   ( 0 )
+#define DRV_RDD_IH_CLASS_10_TARGET_MEMORY_DEFAULT                  ( DRV_IH_TARGET_MEMORY_DDR )
+#define DRV_RDD_IH_CLASS_10_TARGET_MEMORY_OVERRIDE                 ( 1 )
+#define DRV_RDD_IH_CLASS_10_INGRESS_QOS_DEFAULT                    ( DRV_IH_INGRESS_QOS_LOW )
+#define DRV_RDD_IH_CLASS_10_INGRESS_QOS_OVERRIDE                   ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )/* constant */
+#define DRV_RDD_IH_CLASS_10_TARGET_RUNNER_DEFAULT                  ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_10_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE  ( 0 )
+#define DRV_RDD_IH_CLASS_10_TARGET_RUNNER_FOR_DIRECT_MODE          ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_10_LOAD_BALANCING_ENABLE                  ( 0 )/* constant */
+#define DRV_RDD_IH_CLASS_10_PREFERENCE_LOAD_BALANCING_ENABLE       ( 0 )/* constant */
+
+/* Class 11: LAN_BRIDGED_ETH1 */
+#define DRV_RDD_IH_CLASS_11_CLASS_SEARCH_1                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX )
+#define DRV_RDD_IH_CLASS_11_CLASS_SEARCH_2                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX )
+#define DRV_RDD_IH_CLASS_11_CLASS_SEARCH_3                         ( DRV_IH_CLASS_SEARCH_DISABLED )
+#define DRV_RDD_IH_CLASS_11_CLASS_SEARCH_4                         ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_11_DESTINATION_PORT_EXTRACTION            ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1 )
+#define DRV_RDD_IH_CLASS_11_DROP_ON_MISS                           ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )
+#define DRV_RDD_IH_CLASS_11_DSCP_TO_PBITS_TABLE_INDEX              ( 0 )
+#define DRV_RDD_IH_CLASS_11_DIRECT_MODE_DEFAULT                    ( 0 )
+#define DRV_RDD_IH_CLASS_11_DIRECT_MODE_OVERRIDE                   ( 0 )
+#define DRV_RDD_IH_CLASS_11_TARGET_MEMORY_DEFAULT                  ( DRV_IH_TARGET_MEMORY_DDR )
+#define DRV_RDD_IH_CLASS_11_TARGET_MEMORY_OVERRIDE                 ( 1 )
+#define DRV_RDD_IH_CLASS_11_INGRESS_QOS_DEFAULT                    ( DRV_IH_INGRESS_QOS_LOW )
+#define DRV_RDD_IH_CLASS_11_INGRESS_QOS_OVERRIDE                   ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )/* constant */
+#define DRV_RDD_IH_CLASS_11_TARGET_RUNNER_DEFAULT                  ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_11_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE  ( 0 )
+#define DRV_RDD_IH_CLASS_11_TARGET_RUNNER_FOR_DIRECT_MODE          ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_11_LOAD_BALANCING_ENABLE                  ( 0 )/* constant */
+#define DRV_RDD_IH_CLASS_11_PREFERENCE_LOAD_BALANCING_ENABLE       ( 0 )/* constant */
+
+/* Class 12: LAN_BRIDGED_ETH2 */
+#define DRV_RDD_IH_CLASS_12_CLASS_SEARCH_1                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX )
+#define DRV_RDD_IH_CLASS_12_CLASS_SEARCH_2                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX )
+#define DRV_RDD_IH_CLASS_12_CLASS_SEARCH_3                         ( DRV_IH_CLASS_SEARCH_DISABLED )
+#define DRV_RDD_IH_CLASS_12_CLASS_SEARCH_4                         ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_12_DESTINATION_PORT_EXTRACTION            ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1 )
+#define DRV_RDD_IH_CLASS_12_DROP_ON_MISS                           ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )
+#define DRV_RDD_IH_CLASS_12_DSCP_TO_PBITS_TABLE_INDEX              ( 0 )
+#define DRV_RDD_IH_CLASS_12_DIRECT_MODE_DEFAULT                    ( 0 )
+#define DRV_RDD_IH_CLASS_12_DIRECT_MODE_OVERRIDE                   ( 0 )
+#define DRV_RDD_IH_CLASS_12_TARGET_MEMORY_DEFAULT                  ( DRV_IH_TARGET_MEMORY_DDR )
+#define DRV_RDD_IH_CLASS_12_TARGET_MEMORY_OVERRIDE                 ( 1 )
+#define DRV_RDD_IH_CLASS_12_INGRESS_QOS_DEFAULT                    ( DRV_IH_INGRESS_QOS_LOW )
+#define DRV_RDD_IH_CLASS_12_INGRESS_QOS_OVERRIDE                   ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )/* constant */
+#define DRV_RDD_IH_CLASS_12_TARGET_RUNNER_DEFAULT                  ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_12_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE  ( 0 )
+#define DRV_RDD_IH_CLASS_12_TARGET_RUNNER_FOR_DIRECT_MODE          ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_12_LOAD_BALANCING_ENABLE                  ( 0 )/* constant */
+#define DRV_RDD_IH_CLASS_12_PREFERENCE_LOAD_BALANCING_ENABLE       ( 0 )/* constant */
+
+/* Class 13: LAN_BRIDGED_ETH3 */
+#define DRV_RDD_IH_CLASS_13_CLASS_SEARCH_1                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX )
+#define DRV_RDD_IH_CLASS_13_CLASS_SEARCH_2                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX )
+#define DRV_RDD_IH_CLASS_13_CLASS_SEARCH_3                         ( DRV_IH_CLASS_SEARCH_DISABLED )
+#define DRV_RDD_IH_CLASS_13_CLASS_SEARCH_4                         ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_13_DESTINATION_PORT_EXTRACTION            ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1 )
+#define DRV_RDD_IH_CLASS_13_DROP_ON_MISS                           ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )
+#define DRV_RDD_IH_CLASS_13_DSCP_TO_PBITS_TABLE_INDEX              ( 0 )
+#define DRV_RDD_IH_CLASS_13_DIRECT_MODE_DEFAULT                    ( 0 )
+#define DRV_RDD_IH_CLASS_13_DIRECT_MODE_OVERRIDE                   ( 0 )
+#define DRV_RDD_IH_CLASS_13_TARGET_MEMORY_DEFAULT                  ( DRV_IH_TARGET_MEMORY_DDR )
+#define DRV_RDD_IH_CLASS_13_TARGET_MEMORY_OVERRIDE                 ( 1 )
+#define DRV_RDD_IH_CLASS_13_INGRESS_QOS_DEFAULT                    ( DRV_IH_INGRESS_QOS_LOW )
+#define DRV_RDD_IH_CLASS_13_INGRESS_QOS_OVERRIDE                   ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )/* constant */
+#define DRV_RDD_IH_CLASS_13_TARGET_RUNNER_DEFAULT                  ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_13_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE  ( 0 )
+#define DRV_RDD_IH_CLASS_13_TARGET_RUNNER_FOR_DIRECT_MODE          ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_13_LOAD_BALANCING_ENABLE                  ( 0 )/* constant */
+#define DRV_RDD_IH_CLASS_13_PREFERENCE_LOAD_BALANCING_ENABLE       ( 0 )/* constant */
+
+/* Class 14: LAN_BRIDGED_ETH4 */
+#define DRV_RDD_IH_CLASS_14_CLASS_SEARCH_1                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_DA_INDEX )
+#define DRV_RDD_IH_CLASS_14_CLASS_SEARCH_2                         ( DRV_RDD_IH_LOOKUP_TABLE_MAC_SA_INDEX )
+#define DRV_RDD_IH_CLASS_14_CLASS_SEARCH_3                         ( DRV_IH_CLASS_SEARCH_DISABLED )
+#define DRV_RDD_IH_CLASS_14_CLASS_SEARCH_4                         ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_14_DESTINATION_PORT_EXTRACTION            ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1 )
+#define DRV_RDD_IH_CLASS_14_DROP_ON_MISS                           ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )
+#define DRV_RDD_IH_CLASS_14_DSCP_TO_PBITS_TABLE_INDEX              ( 0 )
+#define DRV_RDD_IH_CLASS_14_DIRECT_MODE_DEFAULT                    ( 0 )
+#define DRV_RDD_IH_CLASS_14_DIRECT_MODE_OVERRIDE                   ( 0 )
+#define DRV_RDD_IH_CLASS_14_TARGET_MEMORY_DEFAULT                  ( DRV_IH_TARGET_MEMORY_DDR )
+#define DRV_RDD_IH_CLASS_14_TARGET_MEMORY_OVERRIDE                 ( 1 )
+#define DRV_RDD_IH_CLASS_14_INGRESS_QOS_DEFAULT                    ( DRV_IH_INGRESS_QOS_LOW )
+#define DRV_RDD_IH_CLASS_14_INGRESS_QOS_OVERRIDE                   ( DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED )/* constant */
+#define DRV_RDD_IH_CLASS_14_TARGET_RUNNER_DEFAULT                  ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_14_TARGET_RUNNER_OVERRIDE_IN_DIRECT_MODE  ( 0 )
+#define DRV_RDD_IH_CLASS_14_TARGET_RUNNER_FOR_DIRECT_MODE          ( DRV_RDD_IH_US_DEFAULT_RUNNER )
+#define DRV_RDD_IH_CLASS_14_LOAD_BALANCING_ENABLE                  ( 0 )/* constant */
+#define DRV_RDD_IH_CLASS_14_PREFERENCE_LOAD_BALANCING_ENABLE       ( 0 )/* constant */
+
+/* Class search alternatives, according to user configuration.*/
+#define DRV_RDD_IH_CLASS_10_CLASS_SEARCH_4_ALTERNATIVE  ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_11_CLASS_SEARCH_4_ALTERNATIVE  ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_12_CLASS_SEARCH_4_ALTERNATIVE  ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_13_CLASS_SEARCH_4_ALTERNATIVE  ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_14_CLASS_SEARCH_4_ALTERNATIVE  ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_2_CLASS_SEARCH_4_ALTERNATIVE  ( DRV_RDD_IH_LOOKUP_TABLE_US_INGRESS_CLASSIFICATION_INDEX )
+#define DRV_RDD_IH_CLASS_1_CLASS_SEARCH_2_ALTERNATIVE  ( DRV_IH_CLASS_SEARCH_DISABLED )
+#endif
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_init.c b/arch/arm/mach-bcmbca/rdp/rdd_init.c
new file mode 100755
index 0000000000..dad5928381
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_init.c
@@ -0,0 +1,1595 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#include "rdd.h"
+#include "rdp_mm.h"
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Global Variables                                */
+/*                                                                            */
+/******************************************************************************/
+
+uint8_t                                               *ContextTableBase;
+extern RDD_CONNECTION_TABLE_DTS                       *g_ds_connection_table_ptr;
+extern int                                            g_dbg_lvl;
+extern RDD_FC_MCAST_CONNECTION2_TABLE_DTS             *g_fc_mcast_connection2_table_ptr;
+extern uint8_t                                        *g_runner_ddr_base_addr;
+extern uint32_t                                       g_runner_ddr_base_addr_phys;
+extern uint8_t                                        *g_runner_extra_ddr_base_addr;
+extern uint32_t                                       g_runner_extra_ddr_base_addr_phys;
+extern uint32_t                                       g_ddr_headroom_size;
+extern uint8_t                                        *g_runner_tables_ptr;
+extern uint8_t                                        g_broadcom_switch_mode;
+extern BL_LILAC_RDD_BRIDGE_PORT_DTE                   g_broadcom_switch_physical_port;
+extern uint32_t                                       g_bridge_flow_cache_mode;
+extern uint8_t **g_cpu_tx_skb_pointers_reference_array;
+extern uint8_t *g_dhd_tx_cpu_usage_reference_array;
+extern rdd_phys_addr_t *g_cpu_tx_data_pointers_reference_array;
+extern uint32_t g_cpu_tx_abs_packet_limit;
+extern rdd_phys_addr_t g_free_skb_indexes_fifo_table_physical_address;
+extern rdd_phys_addr_t g_free_skb_indexes_fifo_table_physical_address_last_idx;
+extern uint16_t *g_free_skb_indexes_fifo_table;
+extern RDD_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTE  g_ingress_classification_rule_cfg_table[ 2 ];
+extern uint32_t                                       g_rate_controllers_pool_idx;
+extern uint32_t                                       g_chip_revision;
+extern RDD_WAN_TX_POINTERS_TABLE_DTS                  *wan_tx_pointers_table_ptr;
+rdpa_bpm_buffer_size_t                                g_bpm_buffer_size = LILAC_RDD_RUNNER_PACKET_BUFFER_SIZE;
+
+static BL_LILAC_RDD_ERROR_DTE f_rdd_bpm_initialize ( uint32_t, uint32_t, uint32_t );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_ddr_initialize ( uint32_t, uint32_t, uint32_t );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_psram_initialize ( void );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_scheduler_initialize ( void );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_free_packet_descriptors_pool_initialize ( void );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_global_registers_initialize ( void );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_local_registers_initialize ( void );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_ingress_classification_table_initialize ( void );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_eth_tx_initialize ( void );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_wan_tx_initialize ( void );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_inter_task_queues_initialize ( void );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_pm_counters_initialize ( void );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_transmit_from_abs_address_initialize ( void );
+static BL_LILAC_RDD_ERROR_DTE f_rdd_parallel_processing_initialize ( void );
+
+extern BL_LILAC_RDD_ERROR_DTE rdd_firewall_initialize ( void );
+extern BL_LILAC_RDD_ERROR_DTE rdd_cpu_tx_initialize ( void );
+extern BL_LILAC_RDD_ERROR_DTE rdd_cpu_rx_initialize ( void );
+extern BL_LILAC_RDD_ERROR_DTE f_rdd_mac_table_initialize ( uint32_t, uint32_t );
+extern BL_LILAC_RDD_ERROR_DTE f_rdd_ingress_filters_cam_initialize ( void );
+extern BL_LILAC_RDD_ERROR_DTE f_rdd_layer4_filters_initialize ( void );
+extern BL_LILAC_RDD_ERROR_DTE f_rdd_vlan_matrix_initialize ( void );
+extern BL_LILAC_RDD_ERROR_DTE f_rdd_connection_table_initialize ( void );
+extern BL_LILAC_RDD_ERROR_DTE f_rdd_multicast_initialize ( void );
+extern BL_LILAC_RDD_ERROR_DTE f_rdd_vid_cam_initialize ( void );
+extern BL_LILAC_RDD_ERROR_DTE f_rdd_ds_exponent_table_initialize ( void );
+extern void f_rdd_full_flow_cache_config ( bdmf_boolean );
+
+BL_LILAC_RDD_ERROR_DTE rdd_init ( void )
+{
+    RUNNER_INST_MAIN   *sram_fast_program_ptr;
+    RUNNER_INST_PICO   *sram_pico_program_ptr;
+    RUNNER_COMMON      *sram_common_data_ptr;
+    RUNNER_PRIVATE     *sram_private_data_ptr;
+    RUNNER_CNTXT_MAIN  *sram_fast_context_ptr;
+    RUNNER_CNTXT_PICO  *sram_pico_context_ptr;
+    RUNNER_PRED_MAIN   *sram_fast_prediction_ptr;
+    RUNNER_PRED_PICO   *sram_pico_prediction_ptr;
+
+    /* reset SRAM program memory of both Runners */
+    sram_fast_program_ptr = ( RUNNER_INST_MAIN * )DEVICE_ADDRESS( RUNNER_INST_MAIN_0_OFFSET );
+    rdp_mm_setl ( sram_fast_program_ptr, 0, sizeof ( RUNNER_INST_MAIN ) );
+
+    sram_fast_program_ptr = ( RUNNER_INST_MAIN * )DEVICE_ADDRESS( RUNNER_INST_MAIN_1_OFFSET );
+    rdp_mm_setl ( sram_fast_program_ptr, 0, sizeof ( RUNNER_INST_MAIN ) );
+
+    sram_pico_program_ptr = ( RUNNER_INST_PICO * )DEVICE_ADDRESS( RUNNER_INST_PICO_0_OFFSET );
+    rdp_mm_setl ( sram_pico_program_ptr, 0, sizeof ( RUNNER_INST_PICO ) );
+
+    sram_pico_program_ptr = ( RUNNER_INST_PICO * )DEVICE_ADDRESS( RUNNER_INST_PICO_1_OFFSET );
+    rdp_mm_setl ( sram_fast_program_ptr, 0, sizeof ( RUNNER_INST_PICO ) );
+
+    /* reset SRAM common data memory of both Runners */
+    sram_common_data_ptr = ( RUNNER_COMMON * )DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET );
+    rdp_mm_setl ( sram_common_data_ptr, 0, sizeof ( RUNNER_COMMON ) );
+
+    sram_common_data_ptr = ( RUNNER_COMMON * )DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET );
+    rdp_mm_setl ( sram_common_data_ptr, 0, sizeof ( RUNNER_COMMON ) );
+
+    /* reset SRAM private data memory of both Runners */
+    sram_private_data_ptr = ( RUNNER_PRIVATE * )DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET );
+    rdp_mm_setl ( sram_private_data_ptr, 0, sizeof ( RUNNER_PRIVATE ) );
+
+    sram_private_data_ptr = ( RUNNER_PRIVATE * )DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET );
+    rdp_mm_setl ( sram_private_data_ptr, 0, sizeof ( RUNNER_PRIVATE ) );
+
+    /* reset SRAM context memory of both Runners */
+    sram_fast_context_ptr = ( RUNNER_CNTXT_MAIN * )DEVICE_ADDRESS( RUNNER_CNTXT_MAIN_0_OFFSET );
+    rdp_mm_setl_context ( sram_fast_context_ptr, 0, sizeof ( RUNNER_CNTXT_MAIN ) );
+
+    sram_fast_context_ptr = ( RUNNER_CNTXT_MAIN * )DEVICE_ADDRESS( RUNNER_CNTXT_MAIN_1_OFFSET );
+    rdp_mm_setl_context ( sram_fast_context_ptr, 0, sizeof ( RUNNER_CNTXT_MAIN ) );
+
+    sram_pico_context_ptr = ( RUNNER_CNTXT_PICO * )DEVICE_ADDRESS( RUNNER_CNTXT_PICO_0_OFFSET );
+    rdp_mm_setl_context ( sram_pico_context_ptr, 0, sizeof ( RUNNER_CNTXT_PICO ) );
+
+    sram_pico_context_ptr = ( RUNNER_CNTXT_PICO * )DEVICE_ADDRESS( RUNNER_CNTXT_PICO_1_OFFSET );
+    rdp_mm_setl_context ( sram_pico_context_ptr, 0, sizeof ( RUNNER_CNTXT_PICO ) );
+
+    /* reset SRAM prediction memory of both Runners */
+    sram_fast_prediction_ptr = ( RUNNER_PRED_MAIN * )DEVICE_ADDRESS( RUNNER_PRED_MAIN_0_OFFSET );
+    rdp_mm_setl ( sram_fast_prediction_ptr, 0, sizeof ( RUNNER_PRED_MAIN ) * 2 );
+
+    sram_fast_prediction_ptr = ( RUNNER_PRED_MAIN * )DEVICE_ADDRESS( RUNNER_PRED_MAIN_1_OFFSET );
+    rdp_mm_setl ( sram_fast_prediction_ptr, 0, sizeof ( RUNNER_PRED_MAIN ) * 2 );
+
+    sram_pico_prediction_ptr = ( RUNNER_PRED_PICO * )DEVICE_ADDRESS( RUNNER_PRED_PICO_0_OFFSET );
+    rdp_mm_setl ( sram_pico_prediction_ptr, 0, sizeof ( RUNNER_PRED_PICO ) * 2 );
+
+    sram_pico_prediction_ptr = ( RUNNER_PRED_PICO * )DEVICE_ADDRESS( RUNNER_PRED_PICO_1_OFFSET );
+    rdp_mm_setl ( sram_pico_prediction_ptr, 0, sizeof ( RUNNER_PRED_PICO ) * 2 );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+BL_LILAC_RDD_ERROR_DTE rdd_load_microcode ( uint8_t  *xi_runer_A_microcode_ptr,
+                                            uint8_t  *xi_runer_B_microcode_ptr,
+                                            uint8_t  *xi_runer_C_microcode_ptr,
+                                            uint8_t  *xi_runer_D_microcode_ptr )
+{
+    RUNNER_INST_MAIN  *sram_fast_program_ptr;
+    RUNNER_INST_PICO  *sram_pico_program_ptr;
+
+
+    /* load the code segment into the SRAM program memory of fast Runner B */
+    sram_fast_program_ptr = ( RUNNER_INST_MAIN * )DEVICE_ADDRESS( RUNNER_INST_MAIN_1_OFFSET );
+    MWRITE_BLK_32( sram_fast_program_ptr, xi_runer_B_microcode_ptr, sizeof ( RUNNER_INST_MAIN ) );
+
+    /* load the code segment into the SRAM program memory of pico Runner A */
+    sram_pico_program_ptr = ( RUNNER_INST_PICO * )DEVICE_ADDRESS( RUNNER_INST_PICO_0_OFFSET );
+    MWRITE_BLK_32( sram_pico_program_ptr, xi_runer_C_microcode_ptr, sizeof ( RUNNER_INST_PICO ) );
+
+    /* load the code segment into the SRAM program memory of pico Runner B */
+    sram_pico_program_ptr = ( RUNNER_INST_PICO * )DEVICE_ADDRESS( RUNNER_INST_PICO_1_OFFSET );
+    MWRITE_BLK_32( sram_pico_program_ptr, xi_runer_D_microcode_ptr, sizeof ( RUNNER_INST_PICO ) );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+static void memcpyl_prediction ( void *  __to, void *  __from, unsigned int __n )
+{
+    uint8_t *src = (uint8_t *)__from;
+    uint8_t *dst = (uint8_t *)__to;
+    int i;
+
+    for (i = 0; i < (__n / 2); i++, src += 2, dst += 4)
+    {
+#ifdef _BYTE_ORDER_LITTLE_ENDIAN_
+        *(volatile unsigned int *)dst = swap4bytes((unsigned int)(*(volatile unsigned short *)src));
+#else
+        *(volatile unsigned int *)dst = (unsigned int)(*(volatile unsigned short *)src);
+#endif
+    }
+}
+
+
+BL_LILAC_RDD_ERROR_DTE rdd_load_prediction ( uint8_t  *xi_runer_A_prediction_ptr,
+                                             uint8_t  *xi_runer_B_prediction_ptr,
+                                             uint8_t  *xi_runer_C_prediction_ptr,
+                                             uint8_t  *xi_runer_D_prediction_ptr )
+{
+    RUNNER_PRED_MAIN  *sram_fast_prediction_ptr;
+    RUNNER_PRED_PICO  *sram_pico_prediction_ptr;
+
+    sram_fast_prediction_ptr = ( RUNNER_PRED_MAIN * )DEVICE_ADDRESS( RUNNER_PRED_MAIN_0_OFFSET );
+    memcpyl_prediction ( sram_fast_prediction_ptr, xi_runer_A_prediction_ptr, sizeof ( RUNNER_PRED_MAIN ) );
+
+    sram_fast_prediction_ptr = ( RUNNER_PRED_MAIN * )DEVICE_ADDRESS( RUNNER_PRED_MAIN_1_OFFSET );
+    memcpyl_prediction ( sram_fast_prediction_ptr, xi_runer_B_prediction_ptr, sizeof ( RUNNER_PRED_MAIN ) );
+
+    sram_pico_prediction_ptr = ( RUNNER_PRED_PICO * )DEVICE_ADDRESS( RUNNER_PRED_PICO_0_OFFSET );
+    memcpyl_prediction ( sram_pico_prediction_ptr, xi_runer_C_prediction_ptr, sizeof ( RUNNER_PRED_PICO ) );
+
+    sram_pico_prediction_ptr = ( RUNNER_PRED_PICO * )DEVICE_ADDRESS( RUNNER_PRED_PICO_1_OFFSET );
+    memcpyl_prediction ( sram_pico_prediction_ptr, xi_runer_D_prediction_ptr, sizeof ( RUNNER_PRED_PICO ) );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+BL_LILAC_RDD_ERROR_DTE rdd_runner_enable ( void )
+{
+#if !defined(FIRMWARE_INIT)
+    RUNNER_REGS_CFG_GLOBAL_CTRL  runner_global_control_register;
+
+    /* enable Runner A through the global control register */
+    RUNNER_REGS_0_CFG_GLOBAL_CTRL_READ ( runner_global_control_register );
+    runner_global_control_register.pico_en = LILAC_RDD_TRUE;
+    runner_global_control_register.main_cntxt_reb_en = LILAC_RDD_TRUE;
+    RUNNER_REGS_0_CFG_GLOBAL_CTRL_WRITE ( runner_global_control_register );
+
+    /* enable Runner B through the global control register */
+    RUNNER_REGS_1_CFG_GLOBAL_CTRL_READ ( runner_global_control_register );
+    runner_global_control_register.main_en = LILAC_RDD_TRUE;
+    runner_global_control_register.pico_en = LILAC_RDD_TRUE;
+    runner_global_control_register.main_cntxt_reb_en = LILAC_RDD_TRUE;
+    RUNNER_REGS_1_CFG_GLOBAL_CTRL_WRITE ( runner_global_control_register );
+#endif
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+BL_LILAC_RDD_ERROR_DTE rdd_runner_frequency_set ( uint16_t  xi_runner_frequency )
+{
+#if !defined(FIRMWARE_INIT)
+    RUNNER_REGS_CFG_GLOBAL_CTRL  runner_global_control_register;
+
+    /* set the frequency of the Runner through the global control register */
+    RUNNER_REGS_0_CFG_GLOBAL_CTRL_READ ( runner_global_control_register );
+    runner_global_control_register.micro_sec_val = xi_runner_frequency - 1;
+    RUNNER_REGS_0_CFG_GLOBAL_CTRL_WRITE ( runner_global_control_register );
+
+    RUNNER_REGS_1_CFG_GLOBAL_CTRL_READ ( runner_global_control_register );
+    runner_global_control_register.micro_sec_val = xi_runner_frequency - 1;
+    RUNNER_REGS_1_CFG_GLOBAL_CTRL_WRITE ( runner_global_control_register );
+#endif
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+BL_LILAC_RDD_ERROR_DTE rdd_data_structures_init ( RDD_INIT_PARAMS  *init_params )
+{
+    /* initialize the base address of the packets in the ddr */
+    g_runner_ddr_base_addr = init_params->ddr_pool_ptr;
+    g_runner_ddr_base_addr_phys = init_params->ddr_pool_ptr_phys;
+    g_runner_extra_ddr_base_addr = init_params->extra_ddr_pool_ptr;
+    g_runner_extra_ddr_base_addr_phys = init_params->extra_ddr_pool_ptr_phys;
+    g_runner_tables_ptr = init_params->ddr_runner_tables_ptr;
+    g_ds_connection_table_ptr = ( RDD_CONNECTION_TABLE_DTS * )DsConnectionTableBase;
+#if !defined(FIRMWARE_INIT)
+    /* In simulation these are setup in rdd_sim_alloc_segments */
+    ContextTableBase = g_runner_tables_ptr + CONTEXT_TABLE_ADDRESS;
+#endif
+
+    g_dbg_lvl = 0;
+    g_fc_mcast_connection2_table_ptr = ( RDD_FC_MCAST_CONNECTION2_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + FC_MCAST_CONNECTION2_TABLE_ADDRESS );
+
+    g_ddr_headroom_size = init_params->ddr_headroom_size;
+
+    g_broadcom_switch_mode = init_params->broadcom_switch_mode;
+    g_broadcom_switch_physical_port = init_params->broadcom_switch_physical_port;
+
+    g_bridge_flow_cache_mode = init_params->bridge_flow_cache_mode;
+    g_chip_revision = init_params->chip_revision;
+
+    /* check abs packet limit legal value*/
+    if( ( init_params->cpu_tx_abs_packet_limit <= LILAC_RDD_CPU_TX_SKB_LIMIT_MAX ) &&
+        ( init_params->cpu_tx_abs_packet_limit >= LILAC_RDD_CPU_TX_SKB_LIMIT_MIN ) &&
+        ( init_params->cpu_tx_abs_packet_limit % LILAC_RDD_CPU_TX_SKB_LIMIT_MIN == 0 ) )
+    {
+        g_cpu_tx_abs_packet_limit = init_params->cpu_tx_abs_packet_limit;
+    }
+    else
+    {
+        g_cpu_tx_abs_packet_limit = LILAC_RDD_CPU_TX_SKB_LIMIT_MIN;
+    }
+
+    /* initialize the base address of the BPM base address */
+    f_rdd_bpm_initialize(init_params->ddr_pool_ptr_phys, 0, init_params->extra_ddr_pool_ptr_phys);
+
+    /* initialize runner dma base address */
+    f_rdd_ddr_initialize(init_params->ddr_pool_ptr_phys, 0, g_ddr_headroom_size);
+
+    /* initialize runner dma base address */
+    f_rdd_psram_initialize ();
+
+    /* initialize scheduler */
+    f_rdd_scheduler_initialize ();
+
+    /* create the Runner's free packet descriptors pool */
+    f_rdd_free_packet_descriptors_pool_initialize ();
+
+    /* initialize the CPU-RX mechanism */
+    rdd_cpu_rx_initialize ();
+
+    /* initialize the CPU-TX queue */
+    rdd_cpu_tx_initialize ();
+
+    /* initialize global registers */
+    f_rdd_global_registers_initialize ();
+
+    /* initialize the local registers through the Context memory */
+    f_rdd_local_registers_initialize ();
+
+    /* initialize ethernet tx queues and ports */
+    f_rdd_eth_tx_initialize ();
+
+    /* initialize WAN tx */
+    f_rdd_wan_tx_initialize ();
+
+    /* initialize inter task queues */
+    f_rdd_inter_task_queues_initialize ();
+
+    /* initialize PM counters */
+    f_rdd_pm_counters_initialize ();
+
+    /* initialize ingress classification table */
+    f_rdd_ingress_classification_table_initialize ();
+
+    /* set up the ETH0 EEE mode config message*/
+    MWRITE_32(DEVICE_ADDRESS(RUNNER_PRIVATE_1_OFFSET) + US_ETH0_EEE_MODE_CONFIG_MESSAGE_ADDRESS,
+              (BBH_PERIPHERAL_ETH0_TX<<16)|BBTX_EEE_MODE_CONFIG_MESSAGE);
+
+    /* initialize free skb indexes fifo and pointers*/
+    f_rdd_transmit_from_abs_address_initialize ();
+
+    /* Part of the bridge initialization. */
+    MWRITE_16( (DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS), DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS );
+
+    /* initialize structures supporting parallel processing */
+    f_rdd_parallel_processing_initialize ();
+
+    /* set to not configured */
+    rdd_ethwan2_switch_port_config(0xff);
+
+    /* initialize ds rate limit exponent table */
+    f_rdd_ds_exponent_table_initialize ();
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   f_rdd_bpm_initialize                                                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Runner Initialization - initialize BPM                                   */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function returns the status of the operation                        */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   none                                                                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_runner_ddr_pool_ptr - Packet DDR buffer base address                  */
+/*   xi_extra_ddr_pool_ptr - Packet DDR buffer base address (Multicast)       */
+/*   xi_ddr_headroom_size - configurable headroom in addition to              */
+/*   LILAC_RDD_PACKET_DDR_OFFSET                                              */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   none                                                                     */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+static BL_LILAC_RDD_ERROR_DTE f_rdd_bpm_initialize(uint32_t runner_ddr_pool_phys,
+                                                   uint32_t runner_ddr1_pool_phys,
+                                                   uint32_t runner_extra_ddr_pool_phys)
+{
+    uint32_t *bpm_ddr_base_ptr;
+    uint32_t *bpm_extra_ddr_base_ptr;
+
+    bpm_ddr_base_ptr = (uint32_t *)(DEVICE_ADDRESS(RUNNER_PRIVATE_0_OFFSET) + DS_BPM_DDR_BUFFERS_BASE_ADDRESS);
+    MWRITE_32(bpm_ddr_base_ptr, runner_ddr_pool_phys);
+    bpm_ddr_base_ptr = (uint32_t *)(DEVICE_ADDRESS(RUNNER_PRIVATE_1_OFFSET) + US_BPM_DDR_BUFFERS_BASE_ADDRESS);
+    MWRITE_32(bpm_ddr_base_ptr, runner_ddr_pool_phys);
+
+    bpm_extra_ddr_base_ptr = (uint32_t *)(DEVICE_ADDRESS(RUNNER_PRIVATE_0_OFFSET) + DS_BPM_EXTRA_DDR_BUFFERS_BASE_ADDRESS);
+    MWRITE_32(bpm_extra_ddr_base_ptr, runner_extra_ddr_pool_phys);
+
+    bpm_extra_ddr_base_ptr = (uint32_t *)(DEVICE_ADDRESS(RUNNER_PRIVATE_1_OFFSET) + US_BPM_EXTRA_DDR_BUFFERS_BASE_ADDRESS);
+    MWRITE_32(bpm_extra_ddr_base_ptr, runner_extra_ddr_pool_phys);
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   f_rdd_ddr_initialize                                                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Runner Initialization - initialize the runner ddr config register        */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function returns the status of the operation                        */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   DDR_config Register                                                      */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_runner_ddr_pool_phys - Packet DDR buffer base address                 */
+/*   xi_ddr_headroom_size - configurable headroom in addition to              */
+/*   LILAC_RDD_PACKET_DDR_OFFSET                                              */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   none                                                                     */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+static BL_LILAC_RDD_ERROR_DTE f_rdd_ddr_initialize(uint32_t xi_runner_ddr_pool_phys,
+                                                   uint32_t xi_runner_ddr1_pool_phys,
+                                                   uint32_t xi_ddr_headroom_size)
+{
+    RUNNER_REGS_CFG_DDR_CFG         runner_ddr_config_register;
+    RUNNER_REGS_CFG_DDR_LKUP_MASK0  runner_ddr_lkup_mask0_register;
+    RUNNER_REGS_CFG_DDR_LKUP_MASK1  runner_ddr_lkup_mask1_register;
+    uint32_t                        *ddr_address_ptr; /* DSL */
+
+    runner_ddr_config_register.buffer_offset = LILAC_RDD_PACKET_DDR_OFFSET;
+    runner_ddr_config_register.rserved1 = 0;
+    runner_ddr_config_register.dma_base = (xi_runner_ddr_pool_phys & 0x07E00000) >> 21;
+    runner_ddr_config_register.buffer_size = RDP_CFG_BUF_SIZE_VALUE;
+    runner_ddr_config_register.rserved2 = 0;
+
+    RUNNER_REGS_0_CFG_DDR_CFG_WRITE ( runner_ddr_config_register );
+    RUNNER_REGS_1_CFG_DDR_CFG_WRITE ( runner_ddr_config_register );
+
+    /* DDR lookup for routed packet - 5 tupples */
+    runner_ddr_lkup_mask0_register.global_mask = 0x000001FF;
+
+    RUNNER_REGS_0_CFG_DDR_LKUP_MASK0_WRITE ( runner_ddr_lkup_mask0_register );
+    RUNNER_REGS_1_CFG_DDR_LKUP_MASK0_WRITE ( runner_ddr_lkup_mask0_register );
+
+    /* DDR lookup for IPTV table - destination MAC, destination MAC + VLAN, destination IP */
+    runner_ddr_lkup_mask1_register.global_mask = 0x00000000;
+
+    RUNNER_REGS_0_CFG_DDR_LKUP_MASK1_WRITE ( runner_ddr_lkup_mask1_register );
+    RUNNER_REGS_1_CFG_DDR_LKUP_MASK1_WRITE ( runner_ddr_lkup_mask1_register );
+
+    ddr_address_ptr = ( uint32_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PACKET_BUFFER_SIZE_ASR_8_ADDRESS );
+    MWRITE_8( ddr_address_ptr, g_bpm_buffer_size >> 8 );
+
+    ddr_address_ptr = ( uint32_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PACKET_BUFFER_SIZE_ASR_8_ADDRESS );
+    MWRITE_8( ddr_address_ptr, g_bpm_buffer_size >> 8 );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   f_rdd_psram_initialize                                                   */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Runner Initialization - initialize the runner psram config register      */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function returns the status of the operation                        */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   PSRAM_config Register                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   none                                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   none                                                                     */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+static BL_LILAC_RDD_ERROR_DTE f_rdd_psram_initialize ( void )
+{
+    RUNNER_REGS_CFG_PSRAM_CFG         runner_psram_config_register;
+    RUNNER_REGS_CFG_PSRAM_LKUP_MASK0  runner_psram_lkup_mask0_register;
+
+    runner_psram_config_register.buffer_offset = LILAC_RDD_PACKET_DDR_OFFSET;
+    runner_psram_config_register.rserved1 = 0;
+    runner_psram_config_register.buffer_size = RUNNER_REGS_CFG_PSRAM_CFG_BUFFER_SIZE_BUFFER_SIZE_128BYTE_VALUE;
+    runner_psram_config_register.rserved2 = 0;
+    runner_psram_config_register.dma_base = 0;
+
+    RUNNER_REGS_0_CFG_PSRAM_CFG_WRITE ( runner_psram_config_register );
+    RUNNER_REGS_1_CFG_PSRAM_CFG_WRITE ( runner_psram_config_register );
+
+
+    /* PSRAM lookup for data collection - 5 tupples & layer 2 */
+    runner_psram_lkup_mask0_register.global_mask = 0x0000FFFF;
+
+    RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK0_WRITE ( runner_psram_lkup_mask0_register );
+    RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK0_WRITE ( runner_psram_lkup_mask0_register );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   f_rdd_scheduler_initialize                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Runner Initialization - initialize the scheduler config register         */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function returns the status of the operation                        */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   DDR_config Register                                                      */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   none                                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   none                                                                     */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+static BL_LILAC_RDD_ERROR_DTE f_rdd_scheduler_initialize ( void )
+{
+    uint32_t  runner_scheduler_cfg_register;
+
+    /* fast Runner A - class C */
+    runner_scheduler_cfg_register = ( RUNNER_REGS_CFG_MAIN_SCH_CFG_ARB_CLASS_USE_RR_VALUE << 6 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_USE_CLASS_B_DONT_USE_CLASS_B_VALUE << 5 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_USE_CLASS_A_DONT_USE_CLASS_A_VALUE << 4 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_31_24_RR_VALUE << 3 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_23_16_RR_VALUE << 2 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_15_8_RR_VALUE << 1 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_7_0_STRICT_VALUE << 0 );
+
+    RUNNER_REGS_0_CFG_MAIN_SCH_CFG_WRITE ( runner_scheduler_cfg_register );
+
+    /* fast Runner B - class C */
+    runner_scheduler_cfg_register = ( RUNNER_REGS_CFG_MAIN_SCH_CFG_ARB_CLASS_USE_RR_VALUE << 6 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_USE_CLASS_B_DONT_USE_CLASS_B_VALUE << 5 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_USE_CLASS_A_DONT_USE_CLASS_A_VALUE << 4 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_31_24_RR_VALUE << 3 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_23_16_RR_VALUE << 2 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_15_8_RR_VALUE << 1 ) |
+                                    ( RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_7_0_STRICT_VALUE << 0 );
+
+    RUNNER_REGS_1_CFG_MAIN_SCH_CFG_WRITE ( runner_scheduler_cfg_register );
+
+    /* pico Runner A - class A */
+    runner_scheduler_cfg_register = ( RUNNER_REGS_CFG_PICO_SCH_CFG_ARB_CLASS_USE_RR_VALUE << 6 ) |
+                                    ( RUNNER_REGS_CFG_PICO_SCH_CFG_USE_CLASS_B_DONT_USE_CLASS_B_VALUE << 5 ) |
+                                    ( RUNNER_REGS_CFG_PICO_SCH_CFG_USE_CLASS_A_USE_CLASS_A_VALUE << 4 ) |
+                                    ( RUNNER_REGS_CFG_PICO_SCH_CFG_CLASS_15_8_RR_VALUE << 1 ) |
+                                    ( RUNNER_REGS_CFG_PICO_SCH_CFG_CLASS_7_0_RR_VALUE << 0 );
+
+    RUNNER_REGS_0_CFG_PICO_SCH_CFG_WRITE ( runner_scheduler_cfg_register );
+
+    /* pico Runner B - class A */
+    runner_scheduler_cfg_register = ( RUNNER_REGS_CFG_PICO_SCH_CFG_ARB_CLASS_USE_RR_VALUE << 6 ) |
+                                    ( RUNNER_REGS_CFG_PICO_SCH_CFG_USE_CLASS_B_DONT_USE_CLASS_B_VALUE << 5 ) |
+                                    ( RUNNER_REGS_CFG_PICO_SCH_CFG_USE_CLASS_A_USE_CLASS_A_VALUE << 4 ) |
+                                    ( RUNNER_REGS_CFG_PICO_SCH_CFG_CLASS_15_8_RR_VALUE << 1 ) |
+                                    ( RUNNER_REGS_CFG_PICO_SCH_CFG_CLASS_7_0_RR_VALUE << 0 );
+
+    RUNNER_REGS_1_CFG_PICO_SCH_CFG_WRITE ( runner_scheduler_cfg_register );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   f_rdd_free_packet_descriptors_pool_initialize                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Runner Initialization - initialize the list of the free buffers pool     */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   Upstream pool is implemented as a stack of 3072 packet descriptors       */
+/*   Downstream pool is implemented as a list of 2048 packet descriptors      */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   none                                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   none                                                                     */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+static BL_LILAC_RDD_ERROR_DTE f_rdd_free_packet_descriptors_pool_initialize ( void )
+{
+    RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_DTS                   *ds_free_packet_descriptors_pool_ptr;
+    RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DTS                   *us_free_packet_descriptors_pool_ptr;
+    RDD_PACKET_DESCRIPTOR_DTS                                 *packet_descriptor_ptr;
+    RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_DTS     *free_packet_descriptors_pool_descriptor_ptr;
+    RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_DTS  *us_free_packet_descriptors_pool_descriptor_ptr;
+    uint32_t                                                  next_packet_descriptor_address;
+    uint32_t                                                  i;
+
+    ds_free_packet_descriptors_pool_ptr = ( RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS );
+
+    /* create the free packet descriptors pool as a list of packet descriptors */
+    for ( i = 0; i < RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE; i++ )
+    {
+        packet_descriptor_ptr = &( ds_free_packet_descriptors_pool_ptr->entry[ i ].packet_descriptor );
+
+        /* the last packet descriptor should point to NULL, the others points to the next packet descriptor */
+        if ( i == ( RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE - 1 ) )
+        {
+            next_packet_descriptor_address = 0;
+        }
+        else
+        {
+            next_packet_descriptor_address = DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS + ( i + 1 ) * sizeof(RDD_PACKET_DESCRIPTOR_DTS);
+        }
+
+        RDD_PACKET_DESCRIPTOR_NEXT_PACKET_DESCRIPTOR_POINTER_WRITE ( next_packet_descriptor_address, packet_descriptor_ptr );
+    }
+
+    free_packet_descriptors_pool_descriptor_ptr = ( RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ADDRESS );
+
+    RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_HEAD_POINTER_WRITE ( DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS, free_packet_descriptors_pool_descriptor_ptr );
+
+    RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_TAIL_POINTER_WRITE ( DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS + ( RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE - 1 ) * sizeof(RDD_PACKET_DESCRIPTOR_DTS),
+                                                                           free_packet_descriptors_pool_descriptor_ptr );
+
+    us_free_packet_descriptors_pool_ptr = ( RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS );
+
+    /* create the free packet descriptors pool as a stack of packet descriptors */
+    for ( i = 0; i < RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE; i++ )
+    {
+        packet_descriptor_ptr = &( us_free_packet_descriptors_pool_ptr->entry[ i ].packet_descriptor );
+
+        /* the last packet descriptor should point to NULL, the others points to the next packet descriptor */
+        if ( i == ( RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE - 1 ) )
+        {
+            next_packet_descriptor_address = 0;
+        }
+        else
+        {
+            next_packet_descriptor_address = US_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS + ( i + 1 ) * sizeof(RDD_PACKET_DESCRIPTOR_DTS);
+        }
+
+        RDD_PACKET_DESCRIPTOR_NEXT_PACKET_DESCRIPTOR_POINTER_WRITE ( next_packet_descriptor_address, packet_descriptor_ptr );
+    }
+
+    us_free_packet_descriptors_pool_descriptor_ptr = ( RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ADDRESS );
+
+    RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_THRESHOLD_WRITE ( US_FREE_PACKET_DESCRIPTOR_POOL_GUARANTEED_QUEUE_THRESHOLD, us_free_packet_descriptors_pool_descriptor_ptr );
+    RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_FREE_COUNT_WRITE (US_FREE_PACKET_DESCRIPTOR_POOL_MIN_GUARANTEED_POOL_SIZE, us_free_packet_descriptors_pool_descriptor_ptr );
+    RDD_US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_NON_GUARANTEED_FREE_COUNT_WRITE ( RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE - US_FREE_PACKET_DESCRIPTOR_POOL_MIN_GUARANTEED_POOL_SIZE,  us_free_packet_descriptors_pool_descriptor_ptr );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   f_rdd_global_registers_initialize                                        */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Runner Initialization - initialize the global registers (R1-R7)          */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   Runners global registers (R1-R7)                                         */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   none                                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   none                                                                     */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+static BL_LILAC_RDD_ERROR_DTE f_rdd_global_registers_initialize ( void )
+{
+    uint32_t  *global_register_init_ptr;
+    uint32_t  global_register[ 8 ];
+
+
+    /********** Fast Runner A **********/
+
+    /* zero all global registers */
+    memset ( global_register, 0, sizeof ( global_register ) );
+
+    /* R1 - constant one */
+    global_register[ 1 ] = 1;
+
+    global_register[ 2 ] = ( g_broadcom_switch_mode << DS_GLOBAL_CFG_BROADCOM_SWITCH_MODE_BIT_OFFSET ) |
+                           ( 1 << DS_GLOBAL_CFG_FLOW_CACHE_MODE_BIT_OFFSET ) |
+                           ( g_bridge_flow_cache_mode << DS_GLOBAL_CFG_BRIDGE_FLOW_CACHE_MODE_BIT_OFFSET ) |
+                           ( g_chip_revision << DS_GLOBAL_CFG_CHIP_REVISION_OFFSET );
+
+    global_register[ 3 ] = ( DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS << 16 ) | DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS;
+    global_register[ 4 ] = DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS << 16 | DS_SQ_ENQUEUE_QUEUE_ADDRESS;
+    global_register[ 6 ] = ( DOWNSTREAM_MULTICAST_INGRESS_QUEUE_ADDRESS << 16 ) | DOWNSTREAM_MULTICAST_INGRESS_QUEUE_ADDRESS;
+
+    global_register_init_ptr = ( uint32_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS );
+
+    /* copy the global regsiters to the data SRAM, the firmware will load it from the SRAM at task -1 (initialization task) */
+    MWRITE_BLK_32( global_register_init_ptr, global_register, sizeof ( global_register ) );
+
+
+    /********** Fast Runner B **********/
+
+    /* zero all global registers */
+    memset ( global_register, 0, sizeof ( global_register ) );
+
+    /* R1 - constant one */
+    global_register[ 1 ] = 1;
+
+    /* R2 - head pointer of the free buffers pool stack */
+    global_register[ 2 ] = US_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS;
+
+    /* R4 - Not used */
+
+    global_register[ 7 ] = ( g_broadcom_switch_mode << US_GLOBAL_CFG_BROADCOM_SWITCH_MODE_BIT_OFFSET ) |
+                           ( g_chip_revision << US_GLOBAL_CFG_CHIP_REVISION_OFFSET );
+
+    global_register_init_ptr = ( uint32_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS );
+
+    /* copy the global regsiters to the data SRAM, the firmware will load it from the SRAM at task -1 (initialization task) */
+    MWRITE_BLK_32( global_register_init_ptr, global_register, sizeof ( global_register ) );
+
+
+    /********** Pico Runner A **********/
+
+    /* zero all global registers */
+    memset ( global_register, 0, sizeof ( global_register ) );
+
+    /* R1 - constant one */
+    global_register[ 1 ] = 1;
+
+    global_register[ 2 ] = ( g_chip_revision << DS_GLOBAL_CFG_CHIP_REVISION_OFFSET );
+
+    global_register_init_ptr = ( uint32_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS );
+
+    /* copy the global regsiters to the data SRAM, the firmware will load it from the SRAM at task -1 (initialization task) */
+    MWRITE_BLK_32( global_register_init_ptr, global_register, sizeof ( global_register ) );
+
+
+    /********** Pico Runner B **********/
+
+    /* zero all global registers */
+    memset ( global_register, 0, sizeof ( global_register ) );
+
+    /* R1 - constant one */
+    global_register[ 1 ] = 1;
+
+    global_register[ 3 ] = US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS;
+    global_register[ 3 ] |= US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS << 16;
+
+    /* R4 - context_index_cache_write_index */
+    global_register[ 4 ] = 0;
+    global_register[ 7 ] = ( g_broadcom_switch_mode << US_GLOBAL_CFG_BROADCOM_SWITCH_MODE_BIT_OFFSET ) |
+                           ( g_chip_revision << US_GLOBAL_CFG_CHIP_REVISION_OFFSET );
+
+    global_register_init_ptr = ( uint32_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS );
+
+    MWRITE_BLK_32( global_register_init_ptr, global_register, sizeof ( global_register ) );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   f_rdd_local_registers_initialize                                         */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Runner Initialization - initialize context memeories of 4 Runners        */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   initialize the local registers (R8-R31), 32 threads for fast Runners     */
+/*   and 16 threads for Pico Runners                                          */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   Runners local registers (R8-R31)                                         */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   none                                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   none                                                                     */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+static BL_LILAC_RDD_ERROR_DTE f_rdd_local_registers_initialize ( void )
+{
+    RUNNER_CNTXT_MAIN  *sram_fast_context_ptr;
+    RUNNER_CNTXT_PICO  *sram_pico_context_ptr;
+    static uint32_t    local_register[ 32 ][ 32 ];
+
+    /********** Fast Runner A **********/
+
+    sram_fast_context_ptr = ( RUNNER_CNTXT_MAIN * )DEVICE_ADDRESS( RUNNER_CNTXT_MAIN_0_OFFSET );
+
+    /* read the local registers from the Context memory - maybe it was initialized by the ACE compiler */
+    MREAD_BLK_32( local_register, sram_fast_context_ptr, sizeof ( RUNNER_CNTXT_MAIN ) );
+
+    /* CPU TX fast */
+    local_register[ CPU_TX_FAST_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, cpu_tx_wakeup_request) << 16;
+    local_register[ CPU_TX_FAST_THREAD_NUMBER ][ CS_R8  ] = ( CPU_TX_FAST_QUEUE_ADDRESS << 16 );
+    local_register[ CPU_TX_FAST_THREAD_NUMBER ][ CS_R9  ] = ( INGRESS_HANDLER_BUFFER_ADDRESS << 16 ) | DS_CPU_TX_BBH_DESCRIPTORS_ADDRESS;
+    local_register[ CPU_TX_FAST_THREAD_NUMBER ][ CS_R10 ] = ( BBH_PERIPHERAL_IH << 16 ) | ( LILAC_RDD_IH_BUFFER_BBH_ADDRESS + LILAC_RDD_RUNNER_A_IH_BUFFER_BBH_OFFSET );
+    local_register[ CPU_TX_FAST_THREAD_NUMBER ][ CS_R11 ] = ( BBH_PERIPHERAL_IH << 16 ) | LILAC_RDD_IH_HEADER_DESCRIPTOR_BBH_ADDRESS;
+
+    /* CPU-RX */
+    local_register[ CPU_RX_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, cpu_rx_wakeup_request) << 16;
+    local_register[ CPU_RX_THREAD_NUMBER ][ CS_R8  ] = CPU_RX_FAST_PD_INGRESS_QUEUE_ADDRESS;
+    local_register[ CPU_RX_THREAD_NUMBER ][ CS_R9  ] = DS_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS | ( DS_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS << 16 );
+    local_register[ CPU_RX_THREAD_NUMBER ][ CS_R10 ] = INGRESS_HANDLER_BUFFER_ADDRESS | ( CPU_RX_SQ_PD_INGRESS_QUEUE_ADDRESS << 16 );
+    local_register[ CPU_RX_THREAD_NUMBER ][ CS_R11 ] = DS_CPU_REASON_TO_METER_TABLE_ADDRESS | ( CPU_RX_PD_INGRESS_QUEUE_ADDRESS << 16 );
+
+    /* Timer scheduler */
+    local_register[ TIMER_SCHEDULER_MAIN_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, timer_scheduler_set) << 16;
+    local_register[ TIMER_SCHEDULER_MAIN_THREAD_NUMBER ][ CS_R19 ] = 0;  /* RX_METER_INDEX */
+    local_register[ TIMER_SCHEDULER_MAIN_THREAD_NUMBER ][ CS_R21 ] = DS_CPU_RX_METER_TABLE_ADDRESS;
+
+    /* DS Policers budget allocator */
+    local_register[ POLICER_BUDGET_ALLOCATOR_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, policer_budget_allocator_1st_wakeup_request) << 16;
+
+
+    /* WAN Filters and Classification */
+    local_register[ WAN_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, wan_normal_wakeup_request) << 16;
+    local_register[ WAN_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R8  ] = GPON_RX_NORMAL_DESCRIPTORS_ADDRESS << 16 | BBH_PERIPHERAL_WAN_RX;
+    local_register[ WAN_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R9  ] = CAM_RESULT_SLOT_1 | ( CAM_RESULT_IO_ADDRESS_1 << 16 );
+    local_register[ WAN_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R10 ] = INGRESS_HANDLER_BUFFER_ADDRESS | CPU_REASON_WAN0_TABLE_INDEX << 16;
+    local_register[ WAN_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R13 ] = ( DMA_LOOKUP_RESULT_SLOT_0 << 5 ) | DMA_LOOKUP_RESULT_FOUR_STEPS | ( DMA_LOOKUP_RESULT_IO_ADDRESS_0 << 16 );
+    local_register[ WAN_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R14 ] = WAN_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER;
+
+
+    /* WAN1 Filters and Classification */
+    local_register[ WAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, wan_normal_wakeup_request) << 16;
+    local_register[ WAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R8  ] = ( ETH0_RX_DESCRIPTORS_ADDRESS << 16 ) | BBH_PERIPHERAL_ETH0_RX;
+    local_register[ WAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R9  ] = CAM_RESULT_SLOT_2 | ( CAM_RESULT_IO_ADDRESS_2 << 16 );
+    local_register[ WAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R10 ] = INGRESS_HANDLER_BUFFER_ADDRESS | ( CPU_REASON_WAN1_TABLE_INDEX << 16 );
+    local_register[ WAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R13 ] = ( DMA_LOOKUP_RESULT_SLOT_1 << 5 ) | DMA_LOOKUP_RESULT_FOUR_STEPS | ( DMA_LOOKUP_RESULT_IO_ADDRESS_1 << 16 );
+    local_register[ WAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R14 ] = WAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER;
+
+    /* ETHWAN2 Filters and Classification */
+    // FIXME!!! since this is a different thread from WAN1_FILTER... doesn't it require its own CAM_RESULT and DMA_LOOKUP?
+    local_register[ ETHWAN2_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, ethwan2_normal_wakeup_request) << 16;
+    local_register[ ETHWAN2_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R8  ] = (ETHWAN2_RX_INGRESS_QUEUE_ADDRESS <<16 ) | ( 1 << WAN_FILTERS_AND_CLASSIFICATON_R8_ETHWAN2_INDICATION_OFFSET ) | BBH_PERIPHERAL_ETH0_RX;
+    local_register[ ETHWAN2_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R9  ] = CAM_RESULT_SLOT_2 | ( CAM_RESULT_IO_ADDRESS_2 << 16 );
+    local_register[ ETHWAN2_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R10 ] = INGRESS_HANDLER_BUFFER_ADDRESS | ( CPU_REASON_WAN1_TABLE_INDEX << 16 );
+    local_register[ ETHWAN2_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R13 ] = ( DMA_LOOKUP_RESULT_SLOT_1 << 5 ) | DMA_LOOKUP_RESULT_FOUR_STEPS | ( DMA_LOOKUP_RESULT_IO_ADDRESS_1 << 16 );
+    local_register[ ETHWAN2_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER ][ CS_R14 ] = ETHWAN2_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER;
+    
+    /* FLOW_CACHE */
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, flow_cache_wakeup_request) << 16;
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER ][ CS_R8  ] = ((DS_CONNECTION_BUFFER_TABLE_ADDRESS + 0 * RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2 * sizeof(RDD_CONNECTION_ENTRY_DTS)) << 16) | (DS_L2_UCAST_CONNECTION_BUFFER_ADDRESS + 0x0000);
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER ][ CS_R9  ] = ( DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS << 16 ) | ADDRESS_OF(runner_a, flow_cache_wakeup_request);
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER ][ CS_R10 ] = ( FLOW_CACHE_SLAVE0_VECTOR_MASK << 16 ) | INGRESS_HANDLER_BUFFER_ADDRESS;
+        
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, flow_cache_wakeup_request) << 16;
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER ][ CS_R8  ] = ((DS_CONNECTION_BUFFER_TABLE_ADDRESS + 1 * RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2 * sizeof(RDD_CONNECTION_ENTRY_DTS)) << 16) | (DS_L2_UCAST_CONNECTION_BUFFER_ADDRESS + 0x0010);
+
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER ][ CS_R9  ] = (( DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS + 1 ) << 16 ) | ADDRESS_OF(runner_a, flow_cache_wakeup_request);
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER ][ CS_R10 ] = ( FLOW_CACHE_SLAVE1_VECTOR_MASK << 16 ) | INGRESS_HANDLER_BUFFER_ADDRESS;
+        
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, flow_cache_wakeup_request) << 16;
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER ][ CS_R8  ] = ((DS_CONNECTION_BUFFER_TABLE_ADDRESS + 2 * RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2 * sizeof(RDD_CONNECTION_ENTRY_DTS)) << 16) | (DS_L2_UCAST_CONNECTION_BUFFER_ADDRESS + 0x0020);
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER ][ CS_R9  ] = (( DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS + 2 ) << 16 ) | ADDRESS_OF(runner_a, flow_cache_wakeup_request);
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER ][ CS_R10 ] = ( FLOW_CACHE_SLAVE2_VECTOR_MASK << 16 ) | INGRESS_HANDLER_BUFFER_ADDRESS;
+
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, flow_cache_wakeup_request) << 16;
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER ][ CS_R8  ] = ((DS_CONNECTION_BUFFER_TABLE_ADDRESS + 3 * RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2 * sizeof(RDD_CONNECTION_ENTRY_DTS)) << 16) | (DS_L2_UCAST_CONNECTION_BUFFER_ADDRESS + 0x0030);
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER ][ CS_R9  ] = (( DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS + 3 ) << 16 )  | ADDRESS_OF(runner_a, flow_cache_wakeup_request);
+    local_register[ DOWNSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER ][ CS_R10 ] = ( FLOW_CACHE_SLAVE3_VECTOR_MASK << 16 ) | INGRESS_HANDLER_BUFFER_ADDRESS;
+
+    /* Downstream Multicast */
+    local_register[ DOWNSTREAM_MULTICAST_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, downstream_multicast_wakeup_request) << 16;
+    local_register[ DOWNSTREAM_MULTICAST_THREAD_NUMBER ][ CS_R10 ] = INGRESS_HANDLER_BUFFER_ADDRESS;
+
+    /* Free SKB index */
+    local_register[ FREE_SKB_INDEX_FAST_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_a, free_skb_index_wakeup_request) << 16;
+
+    rdp_mm_cpyl_context ( sram_fast_context_ptr, local_register, sizeof ( RUNNER_CNTXT_MAIN ) );
+
+    /********** Fast Runner B **********/
+
+    sram_fast_context_ptr = ( RUNNER_CNTXT_MAIN * )DEVICE_ADDRESS( RUNNER_CNTXT_MAIN_1_OFFSET );
+
+    /* read the local registers from the Context memory - maybe it was initialized by the ACE compiler */
+    MREAD_BLK_32( local_register, sram_fast_context_ptr, sizeof ( RUNNER_CNTXT_MAIN ) );
+
+    /* CPU-TX */
+    local_register[ CPU_TX_FAST_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_b, cpu_tx_wakeup_request) << 16;
+    local_register[ CPU_TX_FAST_THREAD_NUMBER ][ CS_R8  ] = CPU_TX_FAST_QUEUE_ADDRESS;
+
+    /* CPU-RX */
+    local_register[ CPU_RX_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_b, cpu_rx_wakeup_request) << 16;
+    local_register[ CPU_RX_THREAD_NUMBER ][ CS_R9  ] = US_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS + ( US_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS << 16 );
+    local_register[ CPU_RX_THREAD_NUMBER ][ CS_R10 ] = INGRESS_HANDLER_BUFFER_ADDRESS | (CPU_RX_SQ_PD_INGRESS_QUEUE_ADDRESS << 16);
+    local_register[ CPU_RX_THREAD_NUMBER ][ CS_R11 ] = US_CPU_REASON_TO_METER_TABLE_ADDRESS;
+
+    /* upstream rate controllers budget allocator */
+    local_register[ RATE_CONTROLLER_BUDGET_ALLOCATOR_THREAD_NUMBER ][ CS_R14 ] = US_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS;
+    local_register[ RATE_CONTROLLER_BUDGET_ALLOCATOR_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_b, rate_control_budget_allocator_1st_wakeup_request) << 16;
+    local_register[ RATE_CONTROLLER_BUDGET_ALLOCATOR_THREAD_NUMBER ][ CS_R18 ] = US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_ADDRESS;
+    local_register[ RATE_CONTROLLER_BUDGET_ALLOCATOR_THREAD_NUMBER ][ CS_R31 ] = 0; /* rate_controllers_group */
+
+    /* Timer scheduler */
+    local_register[ TIMER_SCHEDULER_MAIN_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_b, timer_scheduler_set) << 16;
+    local_register[ TIMER_SCHEDULER_MAIN_THREAD_NUMBER ][ CS_R19 ] = 0;  /* RX_METER_INDEX */
+    local_register[ TIMER_SCHEDULER_MAIN_THREAD_NUMBER ][ CS_R20 ] = US_RATE_LIMITER_TABLE_ADDRESS;
+    local_register[ TIMER_SCHEDULER_MAIN_THREAD_NUMBER ][ CS_R21 ] = US_CPU_RX_METER_TABLE_ADDRESS;
+
+    /* US Policers budget allocator */
+    local_register[ POLICER_BUDGET_ALLOCATOR_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_b, policer_budget_allocator_1st_wakeup_request) << 16;
+
+
+    /* WAN1-TX */
+    local_register[ WAN1_TX_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_b, wan_tx_wakeup_request) << 16;
+    local_register[ WAN1_TX_THREAD_NUMBER ][ CS_R8 ] = ( RDD_WAN1_CHANNEL_BASE << 16 ) | ( DATA_POINTER_DUMMY_TARGET_ADDRESS + 4 );
+    local_register[ WAN1_TX_THREAD_NUMBER ][ CS_R9 ] = ( ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS << 16 ) | ETHWAN_ABSOLUTE_TX_BBH_COUNTER_ADDRESS;
+
+    /* WAN enqueue (Flow Cache) */
+    local_register[ WAN_ENQUEUE_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_b, wan_interworking_enqueue_wakeup_request) << 16;
+    local_register[ WAN_ENQUEUE_THREAD_NUMBER ][ CS_R9 ] = ( WAN_ENQUEUE_INGRESS_QUEUE_ADDRESS << 16 ) | ADDRESS_OF(runner_b, wan_interworking_enqueue_wakeup_request);
+    local_register[ WAN_ENQUEUE_THREAD_NUMBER ][ CS_R10  ] = INGRESS_HANDLER_BUFFER_ADDRESS;
+
+    /* Timer 7 */
+    local_register[ US_TIMER_7_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_b, timer_7_1st_wakeup_request) << 16;
+
+    /* Free SKB index */
+    local_register[ FREE_SKB_INDEX_FAST_THREAD_NUMBER ][ CS_R16 ] = ADDRESS_OF(runner_b, free_skb_index_wakeup_request) << 16;
+
+    rdp_mm_cpyl_context ( sram_fast_context_ptr, local_register, sizeof ( RUNNER_CNTXT_MAIN ) );
+
+    /********** Pico Runner A **********/
+
+    sram_pico_context_ptr = ( RUNNER_CNTXT_PICO * )DEVICE_ADDRESS( RUNNER_CNTXT_PICO_0_OFFSET );
+
+    /* read the local registers from the Context memory - maybe it was initialized by the ACE compiler */
+    MREAD_BLK_32( local_register, sram_pico_context_ptr, sizeof ( RUNNER_CNTXT_PICO ) );
+
+    /* CPU-TX */
+    local_register[ CPU_TX_PICO_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_c, cpu_tx_wakeup_request) << 16;
+    local_register[ CPU_TX_PICO_THREAD_NUMBER - 32 ][ CS_R9  ] = CPU_TX_PICO_QUEUE_ADDRESS;
+
+    /* CPU-RX interrupt coalescing timer */
+    local_register[ CPU_RX_INTERRUPT_COALESCING_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_c, cpu_rx_int_coalesce_timer_1st_wakeup_request) << 16;
+
+    /* Timer scheduler */
+    local_register[ TIMER_SCHEDULER_PICO_A_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_c, timer_scheduler_set) << 16;
+    local_register[ TIMER_SCHEDULER_PICO_A_THREAD_NUMBER - 32 ][ CS_R19 ] = 0; /* rate limiter index */
+    local_register[ TIMER_SCHEDULER_PICO_A_THREAD_NUMBER - 32 ][ CS_R20 ] = DS_RATE_LIMITER_TABLE_ADDRESS;
+    local_register[ TIMER_SCHEDULER_PICO_A_THREAD_NUMBER - 32 ][ CS_R21 ] = RATE_LIMITER_REMAINDER_TABLE_ADDRESS;
+
+    /* Local switching LAN enqueue */
+    local_register[ LOCAL_SWITCHING_LAN_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R16 ] = ( ADDRESS_OF(runner_c, lan_enqueue_pd_wakeup_request) << 16 ) | ADDRESS_OF(runner_c, lan_enqueue_pd_wakeup_request);
+    local_register[ LOCAL_SWITCHING_LAN_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R9  ] = LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS;
+    local_register[ LOCAL_SWITCHING_LAN_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R10 ] = DOWNSTREAM_LAN_ENQUEUE_SQ_PD_ADDRESS;
+
+    /* Downstream LAN enqueue */
+    local_register[ DOWNSTREAM_LAN_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_c, lan_enqueue_ih_wakeup_request) << 16 | ADDRESS_OF(runner_c, lan_enqueue_ih_wakeup_request);
+    local_register[ DOWNSTREAM_LAN_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R9  ] = DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS << 16;
+    local_register[ DOWNSTREAM_LAN_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R10  ] = INGRESS_HANDLER_BUFFER_ADDRESS;
+
+    /* Downstream multicast LAN enqueue */
+    local_register[ DOWNSTREAM_MULTICAST_LAN_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R16 ] = ( ADDRESS_OF(runner_c, multicast_lan_enqueue_wakeup_request) << 16 ) | ADDRESS_OF(runner_c, multicast_lan_enqueue_wakeup_request);
+    local_register[ DOWNSTREAM_MULTICAST_LAN_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R9  ] = DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS;
+    local_register[ DOWNSTREAM_MULTICAST_LAN_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R10 ] = INGRESS_HANDLER_BUFFER_ADDRESS;
+
+    /* Free SKB index */
+    local_register[ FREE_SKB_INDEX_PICO_A_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_c, free_skb_index_wakeup_request) << 16;
+    local_register[ FREE_SKB_INDEX_PICO_A_THREAD_NUMBER - 32 ][ CS_R9  ] = 1; /* lag_port EMAC/BBH 1 */
+
+    /* ETH-TX Inter LAN scheduling: thread 42 */
+    local_register[ ETH_TX_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_c, lan_tx_wakeup_request) << 16 | (ADDRESS_OF(runner_c, lan_tx_wakeup_request) );
+    local_register[ ETH_TX_THREAD_NUMBER - 32 ][ CS_R8  ] = 0; /* inter_lan_scheduling_offset */
+
+    /* Timer 7 */
+    local_register[ DS_TIMER_7_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_c, timer_7_1st_wakeup_request) << 16;
+
+    /* Service Queue Enqueue: thread 44 */
+    local_register[ SERVICE_QUEUE_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_c, service_queue_enqueue_wakeup_request) << 16;
+    local_register[ SERVICE_QUEUE_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R9  ] = INGRESS_HANDLER_BUFFER_ADDRESS;
+    local_register[ SERVICE_QUEUE_ENQUEUE_THREAD_NUMBER - 32 ][ CS_R10 ] = DS_SQ_ENQUEUE_QUEUE_ADDRESS;
+
+    /* Service Queue Dequeue: thread 45 */
+    local_register[ SERVICE_QUEUE_DEQUEUE_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_c, service_queue_dequeue_wakeup_request) << 16 | ADDRESS_OF(runner_c, service_queue_dequeue_wakeup_request);
+    local_register[ SERVICE_QUEUE_DEQUEUE_THREAD_NUMBER - 32 ][ CS_R10 ] = DOWNSTREAM_LAN_ENQUEUE_SQ_PD_ADDRESS << 16;
+    local_register[ SERVICE_QUEUE_DEQUEUE_THREAD_NUMBER - 32 ][ CS_R11 ] = CPU_RX_SQ_PD_INGRESS_QUEUE_ADDRESS;
+
+    rdp_mm_cpyl_context ( sram_pico_context_ptr, local_register, sizeof ( RUNNER_CNTXT_PICO ) );
+
+    /********** Pico Runner B **********/
+
+    sram_pico_context_ptr = ( RUNNER_CNTXT_PICO * )DEVICE_ADDRESS( RUNNER_CNTXT_PICO_1_OFFSET );
+
+    /* read the local registers from the Context memory - maybe it was initialized by the ACE compiler */
+    MREAD_BLK_32( local_register, sram_pico_context_ptr, sizeof ( RUNNER_CNTXT_PICO ) );
+
+    /* Timer scheduler */
+    local_register[ TIMER_SCHEDULER_PICO_B_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_d, timer_scheduler_set) << 16;
+    local_register[ TIMER_SCHEDULER_PICO_B_THREAD_NUMBER - 32 ][ CS_R19 ] = 0; /* rate limiter index */
+    local_register[ TIMER_SCHEDULER_PICO_B_THREAD_NUMBER - 32 ][ CS_R20 ] = US_RATE_LIMITER_TABLE_ADDRESS;
+
+#if defined(DSL_63138) || defined(DSL_63148)
+    /* LAN-1 Filters and Classification - used by CFE boot loader */
+    local_register[ LAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_d, lan_normal_wakeup_request) << 16;
+    local_register[ LAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER - 32 ][ CS_R8  ] = ETH1_RX_DESCRIPTORS_ADDRESS;
+    local_register[ LAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER - 32 ][ CS_R10 ] = INGRESS_HANDLER_BUFFER_ADDRESS | ( HASH_RESULT_SLOT_1 << 16 ) | ( HASH_RESULT_IO_ADDRESS_1 << 24 );
+    local_register[ LAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER - 32 ][ CS_R12 ] = ( BBH_PERIPHERAL_ETH1_RX << 16 );
+    local_register[ LAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER - 32 ][ CS_R13 ] = ( DMA_LOOKUP_RESULT_SLOT_3 << 5 ) | DMA_LOOKUP_RESULT_FOUR_STEPS | ( DMA_LOOKUP_RESULT_IO_ADDRESS_3 << 16 );
+#endif
+
+    /* Free SKB index */
+    local_register[ FREE_SKB_INDEX_PICO_B_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_d, free_skb_index_wakeup_request) << 16;
+
+    /* LAN Dispatch */
+    local_register[ LAN_DISPATCH_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_d, lan_dispatch_wakeup_request) << 16;
+    local_register[ LAN_DISPATCH_THREAD_NUMBER - 32 ][ CS_R10  ] = INGRESS_HANDLER_BUFFER_ADDRESS;
+    local_register[ LAN_DISPATCH_THREAD_NUMBER - 32 ][ CS_R8  ] = ETH1_RX_DESCRIPTORS_ADDRESS;
+    local_register[ LAN_DISPATCH_THREAD_NUMBER - 32 ][ CS_R15 ] = BBH_PERIPHERAL_ETH1_RX;
+    local_register[ LAN_DISPATCH_THREAD_NUMBER - 32 ][ CS_R13 ] = ( DMA_LOOKUP_RESULT_SLOT_4 << 5 ) | DMA_LOOKUP_RESULT_FOUR_STEPS | ( DMA_LOOKUP_RESULT_IO_ADDRESS_4 << 16 );
+    local_register[ LAN_DISPATCH_THREAD_NUMBER - 32 ][ CS_R14 ] = LAN_DISPATCH_THREAD_NUMBER;
+
+    /* SLAVE0 */
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_d, flow_cache_wakeup_request) << 16;
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER - 32 ][ CS_R8  ] = (uint32_t) ((US_CONNECTION_BUFFER_TABLE_ADDRESS + 0 * RDD_US_CONNECTION_BUFFER_TABLE_SIZE2 * sizeof(RDD_CONNECTION_ENTRY_DTS)) << 16) | (US_L2_UCAST_CONNECTION_BUFFER_ADDRESS + 0x0000);
+
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER - 32 ][ CS_R9  ] = ( US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS << 16 );
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER - 32 ][ CS_R10 ] = ( FLOW_CACHE_SLAVE0_VECTOR_MASK << 16 ) | INGRESS_HANDLER_BUFFER_ADDRESS;
+        
+    /* SLAVE1 */
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_d, flow_cache_wakeup_request) << 16;
+
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER - 32 ][ CS_R8  ] = (uint32_t) ((US_CONNECTION_BUFFER_TABLE_ADDRESS + 1 * RDD_US_CONNECTION_BUFFER_TABLE_SIZE2 * sizeof(RDD_CONNECTION_ENTRY_DTS)) << 16) | (US_L2_UCAST_CONNECTION_BUFFER_ADDRESS + 0x0010);
+
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER - 32 ][ CS_R9  ] = ( ( US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS + 1 ) << 16 );
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER - 32 ][ CS_R10 ] = ( FLOW_CACHE_SLAVE1_VECTOR_MASK << 16 ) | INGRESS_HANDLER_BUFFER_ADDRESS;
+        
+    /* SLAVE2 */
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_d, flow_cache_wakeup_request) << 16;
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER - 32 ][ CS_R8  ] = (uint32_t) ((US_CONNECTION_BUFFER_TABLE_ADDRESS + 2 * RDD_US_CONNECTION_BUFFER_TABLE_SIZE2 * sizeof(RDD_CONNECTION_ENTRY_DTS)) << 16) | (US_L2_UCAST_CONNECTION_BUFFER_ADDRESS + 0x0020);
+
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER - 32 ][ CS_R9  ] = ( ( US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS + 2 ) << 16 );
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER - 32 ][ CS_R10 ] = ( FLOW_CACHE_SLAVE2_VECTOR_MASK << 16 ) | INGRESS_HANDLER_BUFFER_ADDRESS;
+        
+    /* SLAVE3 */
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER - 32 ][ CS_R16 ] = ADDRESS_OF(runner_d, flow_cache_wakeup_request) << 16;
+
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER - 32 ][ CS_R8  ] = (uint32_t) ((US_CONNECTION_BUFFER_TABLE_ADDRESS + 3 * RDD_US_CONNECTION_BUFFER_TABLE_SIZE2 * sizeof(RDD_CONNECTION_ENTRY_DTS)) << 16) | (US_L2_UCAST_CONNECTION_BUFFER_ADDRESS + 0x0030);
+
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER - 32 ][ CS_R9  ] = ( ( US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS + 3 ) << 16 );
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER - 32 ][ CS_R10 ] = ( FLOW_CACHE_SLAVE3_VECTOR_MASK << 16 ) | INGRESS_HANDLER_BUFFER_ADDRESS;
+
+#if defined(DSL_63138) || defined(DSL_63148)
+    /* SLAVE 0-3 */
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER - 32 ][ CS_R9  ] |= (DSL_PTM_BOND_TX_HDR_TABLE_ADDRESS + 0x00);
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER - 32 ][ CS_R9  ] |= (DSL_PTM_BOND_TX_HDR_TABLE_ADDRESS + 0x10);
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER - 32 ][ CS_R9  ] |= (DSL_PTM_BOND_TX_HDR_TABLE_ADDRESS + 0x20);
+    local_register[ UPSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER - 32 ][ CS_R9  ] |= (DSL_PTM_BOND_TX_HDR_TABLE_ADDRESS + 0x30);
+#endif
+
+    rdp_mm_cpyl_context ( sram_pico_context_ptr, local_register, sizeof ( RUNNER_CNTXT_PICO ) );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+static BL_LILAC_RDD_ERROR_DTE f_rdd_transmit_from_abs_address_initialize ( void )
+{
+    uint8_t   *free_indexes_local_fifo_tail_ptr;
+    uint16_t  *free_indexes_fifo_tail_ptr;
+    uint16_t  skb_enqueued_indexes_fifo;
+    uint16_t  *skb_enqueued_indexes_fifo_ptr;
+    uint8_t   *absolute_tx_counters_ptr;
+    uint16_t  i;
+    uint32_t  *ddr_address_ptr;
+    uint8_t   skb_enqueued_indexes_fifo_size;
+    uint8_t   *skb_enqueued_indexes_fifo_counters_ptr;
+
+#if !defined(FIRMWARE_INIT)
+    bdmf_phys_addr_t phy_addr = 0;
+
+    /* allocate skb pointer array reference (used only by SW) */
+    g_cpu_tx_skb_pointers_reference_array = (uint8_t **)KMALLOC(sizeof(uint8_t *) * g_cpu_tx_abs_packet_limit, 0);
+    g_dhd_tx_cpu_usage_reference_array = (uint8_t *)KMALLOC(g_cpu_tx_abs_packet_limit, 0);
+
+    /* allocate data pointer array pointer (used both by SW & FW) */
+    g_cpu_tx_data_pointers_reference_array = (rdd_phys_addr_t *)rdp_mm_aligned_alloc(sizeof(rdd_phys_addr_t) * g_cpu_tx_abs_packet_limit, &phy_addr);
+
+    ddr_address_ptr = (uint32_t *)(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_ADDRESS );
+    MWRITE_32(ddr_address_ptr, (uint32_t)phy_addr);
+
+    /* allocate Free Indexes table (used both by SW & FW) */
+    g_free_skb_indexes_fifo_table = ( uint16_t * )rdp_mm_aligned_alloc( sizeof( uint16_t ) * g_cpu_tx_abs_packet_limit, &phy_addr );
+
+    g_free_skb_indexes_fifo_table_physical_address = (rdd_phys_addr_t)phy_addr;
+    ddr_address_ptr = ( uint32_t * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_ADDRESS );
+    MWRITE_32( ddr_address_ptr, g_free_skb_indexes_fifo_table_physical_address );
+
+    g_free_skb_indexes_fifo_table_physical_address_last_idx = g_free_skb_indexes_fifo_table_physical_address;
+    g_free_skb_indexes_fifo_table_physical_address_last_idx += (g_cpu_tx_abs_packet_limit - 1) * sizeof(uint16_t);
+    ddr_address_ptr = ( uint32_t * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_ADDRESS );
+    MWRITE_32( ddr_address_ptr, g_free_skb_indexes_fifo_table_physical_address_last_idx );
+
+    /* Fill free indexes FIFO */
+    for ( i = 0; i < g_cpu_tx_abs_packet_limit ; i++ )
+    {
+        g_free_skb_indexes_fifo_table[ i ] = swap2bytes( i );
+        g_cpu_tx_data_pointers_reference_array[ i ] = 0;
+        g_cpu_tx_skb_pointers_reference_array[ i ] = NULL;
+        g_dhd_tx_cpu_usage_reference_array[ i ] = 0;
+    }
+#endif
+
+    /* update all local tail pointers to 0 */
+    free_indexes_local_fifo_tail_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS );
+    MWRITE_8( free_indexes_local_fifo_tail_ptr, 0 );
+    free_indexes_local_fifo_tail_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS );
+    MWRITE_8( free_indexes_local_fifo_tail_ptr, 0 );
+    free_indexes_local_fifo_tail_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS );
+    MWRITE_8( free_indexes_local_fifo_tail_ptr, 0 );
+    free_indexes_local_fifo_tail_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS );
+    MWRITE_8( free_indexes_local_fifo_tail_ptr, 0 );
+
+    free_indexes_fifo_tail_ptr = ( uint16_t * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + FREE_SKB_INDEXES_DDR_FIFO_TAIL_ADDRESS );
+    MWRITE_32( free_indexes_fifo_tail_ptr, g_free_skb_indexes_fifo_table_physical_address );
+
+    /* Initialize pointers to EMAC enqueued indexes FIFO */
+    skb_enqueued_indexes_fifo_ptr = ( uint16_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS );
+    skb_enqueued_indexes_fifo_counters_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_ADDRESS );
+
+    skb_enqueued_indexes_fifo = EMAC_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS;
+
+    for ( i = BL_LILAC_RDD_EMAC_ID_0; i <= BL_LILAC_RDD_EMAC_ID_4; i++ )
+    {
+        MWRITE_16( skb_enqueued_indexes_fifo_ptr, skb_enqueued_indexes_fifo );
+        MWRITE_8(skb_enqueued_indexes_fifo_counters_ptr, 16);
+
+        skb_enqueued_indexes_fifo_ptr++;
+        skb_enqueued_indexes_fifo_counters_ptr++;
+
+        skb_enqueued_indexes_fifo += 32;
+    }
+
+    skb_enqueued_indexes_fifo_ptr = ( uint16_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS );
+
+    skb_enqueued_indexes_fifo = EMAC_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS;
+
+    for ( i = BL_LILAC_RDD_EMAC_ID_0; i <= BL_LILAC_RDD_EMAC_ID_4; i++ )
+    {
+        MWRITE_16( skb_enqueued_indexes_fifo_ptr, skb_enqueued_indexes_fifo );
+
+        skb_enqueued_indexes_fifo_ptr++;
+        skb_enqueued_indexes_fifo += 32;
+    }
+
+    skb_enqueued_indexes_fifo_size = 32;
+
+    /* Initialize pointers to WAN enqueued indexes FIFO */    
+    skb_enqueued_indexes_fifo_ptr = ( uint16_t * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS - sizeof ( RUNNER_COMMON ) );
+
+    skb_enqueued_indexes_fifo = GPON_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS;
+
+    for ( i = 0; i < ( RDD_WAN_CHANNELS_0_7_TABLE_SIZE + RDD_WAN_CHANNELS_8_39_TABLE_SIZE ); i++ )
+    {
+        MWRITE_16( skb_enqueued_indexes_fifo_ptr, skb_enqueued_indexes_fifo );
+
+        skb_enqueued_indexes_fifo_ptr++;
+        skb_enqueued_indexes_fifo += skb_enqueued_indexes_fifo_size;
+    }
+
+
+    skb_enqueued_indexes_fifo_ptr = ( uint16_t * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS - sizeof ( RUNNER_COMMON ) );
+
+    skb_enqueued_indexes_fifo = GPON_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS;
+
+    for ( i = 0; i < ( RDD_WAN_CHANNELS_0_7_TABLE_SIZE + RDD_WAN_CHANNELS_8_39_TABLE_SIZE ); i++ )
+    {
+        MWRITE_16( skb_enqueued_indexes_fifo_ptr, skb_enqueued_indexes_fifo );
+
+        skb_enqueued_indexes_fifo_ptr++;
+        skb_enqueued_indexes_fifo += skb_enqueued_indexes_fifo_size;
+    }
+
+
+    /* Initialize to (-1) 6-bit value BBH and FW absolute TX counters */
+    absolute_tx_counters_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_ABSOLUTE_TX_BBH_COUNTER_ADDRESS );
+
+    for ( i = BL_LILAC_RDD_EMAC_ID_0; i <= BL_LILAC_RDD_EMAC_ID_4; i++ )
+    {
+        MWRITE_8( absolute_tx_counters_ptr, 0x3F );
+        absolute_tx_counters_ptr += 8;
+    }
+
+    absolute_tx_counters_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + EMAC_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS );
+
+    for ( i = BL_LILAC_RDD_EMAC_ID_0; i <= BL_LILAC_RDD_EMAC_ID_4; i++ )
+    {
+        MWRITE_8( absolute_tx_counters_ptr, 0x3F );
+        absolute_tx_counters_ptr ++;
+    }
+
+    absolute_tx_counters_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + GPON_ABSOLUTE_TX_BBH_COUNTER_ADDRESS );
+
+    for ( i = 0; i < ( RDD_WAN_CHANNELS_0_7_TABLE_SIZE + RDD_WAN_CHANNELS_8_39_TABLE_SIZE ); i++ )
+    {
+        MWRITE_8( absolute_tx_counters_ptr, 0x3F );
+        absolute_tx_counters_ptr ++;
+    }
+
+    absolute_tx_counters_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS );
+
+    for ( i = 0; i < ( RDD_WAN_CHANNELS_0_7_TABLE_SIZE + RDD_WAN_CHANNELS_8_39_TABLE_SIZE ); i++ )
+    {
+        MWRITE_8( absolute_tx_counters_ptr, 0x3F );
+        absolute_tx_counters_ptr ++;
+    }
+
+    absolute_tx_counters_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETHWAN_ABSOLUTE_TX_BBH_COUNTER_ADDRESS );
+    MWRITE_8( absolute_tx_counters_ptr, 0x3F );
+
+    absolute_tx_counters_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS );
+    MWRITE_8( absolute_tx_counters_ptr, 0x3F );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+static BL_LILAC_RDD_ERROR_DTE f_rdd_ingress_classification_table_initialize ( void )
+{
+    RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS *ds_rule_cfg_table_ptr;
+    RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTS *us_rule_cfg_table_ptr;
+    RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_DTS *rule_cfg_entry_ptr;
+    uint8_t *rule_cfg_descriptor_ptr;
+    uint32_t rule_cfg_id;
+
+    for (rule_cfg_id = 0; rule_cfg_id < 16; rule_cfg_id++)
+    {
+        g_ingress_classification_rule_cfg_table[ rdpa_dir_ds ].rule_cfg[ rule_cfg_id ].valid = 0;
+        g_ingress_classification_rule_cfg_table[ rdpa_dir_ds ].rule_cfg[ rule_cfg_id ].priority = -1;
+        g_ingress_classification_rule_cfg_table[ rdpa_dir_ds ].rule_cfg[ rule_cfg_id ].rule_type = 0;
+        g_ingress_classification_rule_cfg_table[ rdpa_dir_ds ].rule_cfg[ rule_cfg_id ].next_group_id = 16;
+        g_ingress_classification_rule_cfg_table[ rdpa_dir_ds ].rule_cfg[ rule_cfg_id ].next_rule_cfg_id = 16;
+
+        ds_rule_cfg_table_ptr = RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_PTR();
+
+        rule_cfg_entry_ptr = &( ds_rule_cfg_table_ptr->entry[ rule_cfg_id ] );
+
+        RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_NEXT_RULE_CFG_ID_WRITE ( 16, rule_cfg_entry_ptr );
+        RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_NEXT_GROUP_ID_WRITE ( 16, rule_cfg_entry_ptr );
+
+        g_ingress_classification_rule_cfg_table[ rdpa_dir_us ].rule_cfg[ rule_cfg_id ].valid = 0;
+        g_ingress_classification_rule_cfg_table[ rdpa_dir_us ].rule_cfg[ rule_cfg_id ].priority = -1;
+        g_ingress_classification_rule_cfg_table[ rdpa_dir_us ].rule_cfg[ rule_cfg_id ].rule_type = 0;
+        g_ingress_classification_rule_cfg_table[ rdpa_dir_us ].rule_cfg[ rule_cfg_id ].next_group_id = 16;
+        g_ingress_classification_rule_cfg_table[ rdpa_dir_us ].rule_cfg[ rule_cfg_id ].next_rule_cfg_id = 16;
+
+        us_rule_cfg_table_ptr = RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_PTR();
+
+        rule_cfg_entry_ptr = &( us_rule_cfg_table_ptr->entry[ rule_cfg_id ] );
+
+        RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_NEXT_RULE_CFG_ID_WRITE ( 16, rule_cfg_entry_ptr );
+        RDD_INGRESS_CLASSIFICATION_RULE_CFG_ENTRY_NEXT_GROUP_ID_WRITE ( 16, rule_cfg_entry_ptr );
+    }
+
+    g_ingress_classification_rule_cfg_table[ rdpa_dir_ds ].first_rule_cfg_id = 16;
+    g_ingress_classification_rule_cfg_table[ rdpa_dir_ds ].first_gen_filter_rule_cfg_id = 16;
+    g_ingress_classification_rule_cfg_table[ rdpa_dir_us ].first_rule_cfg_id = 16;
+    g_ingress_classification_rule_cfg_table[ rdpa_dir_us ].first_gen_filter_rule_cfg_id = 16;
+
+    rule_cfg_descriptor_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_ADDRESS );
+
+    MWRITE_8( rule_cfg_descriptor_ptr, 16 );
+
+    rule_cfg_descriptor_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_ADDRESS );
+
+    MWRITE_8( rule_cfg_descriptor_ptr, 16 );
+
+    rule_cfg_descriptor_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_ADDRESS );
+
+    MWRITE_8( rule_cfg_descriptor_ptr, 16 );
+
+    rule_cfg_descriptor_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_ADDRESS );
+
+    MWRITE_8( rule_cfg_descriptor_ptr, 16 );
+    return ( BL_LILAC_RDD_OK );
+}
+
+static BL_LILAC_RDD_ERROR_DTE f_rdd_eth_tx_initialize ( void )
+{
+    RDD_ETH_TX_MAC_TABLE_DTS *eth_tx_mac_table;
+    RDD_ETH_TX_MAC_DESCRIPTOR_DTS *eth_tx_mac_descriptor;
+    RDD_ETH_TX_QUEUES_TABLE_DTS *eth_tx_queues_table;
+    RDD_ETH_TX_QUEUE_DESCRIPTOR_DTS *eth_tx_queue_descriptor;
+    RDD_ETH_TX_QUEUES_POINTERS_TABLE_DTS *eth_tx_queues_pointers_table;
+    RDD_ETH_TX_QUEUE_POINTERS_ENTRY_DTS *eth_tx_queue_pointers_entry;
+    RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_DTS *free_packet_descriptors_pool_descriptor;
+    RDD_ETH_TX_LOCAL_REGISTERS_DTS *eth_tx_local_registers;
+    RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_DTS *eth_tx_local_registers_entry;
+    uint16_t eth_tx_queue_address;
+    uint16_t mac_descriptor_address;
+    uint32_t emac;
+    uint32_t tx_queue;
+
+    eth_tx_mac_table = RDD_ETH_TX_MAC_TABLE_PTR();
+
+    eth_tx_queues_table = RDD_ETH_TX_QUEUES_TABLE_PTR();
+
+    eth_tx_queues_pointers_table = RDD_ETH_TX_QUEUES_POINTERS_TABLE_PTR();
+
+    eth_tx_local_registers = RDD_ETH_TX_LOCAL_REGISTERS_PTR();
+
+    for (emac = BL_LILAC_RDD_EMAC_ID_0; emac < BL_LILAC_RDD_EMAC_ID_COUNT; emac++)
+    {
+        eth_tx_mac_descriptor = &(eth_tx_mac_table->entry[emac]);
+
+        RDD_ETH_TX_MAC_DESCRIPTOR_TX_TASK_NUMBER_WRITE(ETH_TX_THREAD_NUMBER, eth_tx_mac_descriptor);
+        RDD_ETH_TX_MAC_DESCRIPTOR_EMAC_MASK_WRITE((1 << emac), eth_tx_mac_descriptor);
+        RDD_ETH_TX_MAC_DESCRIPTOR_GPIO_FLOW_CONTROL_VECTOR_PTR_WRITE((RDD_GPIO_IO_ADDRESS + (emac - BL_LILAC_RDD_EMAC_ID_0)), eth_tx_mac_descriptor);
+        RDD_ETH_TX_MAC_DESCRIPTOR_PACKET_COUNTERS_PTR_1_WRITE(ETH_TX_MAC_TABLE_ADDRESS +
+            BL_LILAC_RDD_EMAC_ID_1 * sizeof(RDD_ETH_TX_MAC_DESCRIPTOR_DTS) + RDD_EMAC_DESCRIPTOR_EGRESS_COUNTER_OFFSET,
+            eth_tx_mac_descriptor);
+        RDD_ETH_TX_MAC_DESCRIPTOR_BBH_DESTINATION_1_WRITE(BBH_PERIPHERAL_ETH1_TX, eth_tx_mac_descriptor);
+        RDD_ETH_TX_MAC_DESCRIPTOR_EGRESS_PORT_WRITE((emac - BL_LILAC_RDD_EMAC_ID_0), eth_tx_mac_descriptor);
+        RDD_ETH_TX_MAC_DESCRIPTOR_RATE_LIMITER_ID_WRITE(RDD_RATE_LIMITER_IDLE, eth_tx_mac_descriptor);
+
+        for (tx_queue = 0; tx_queue < RDD_EMAC_NUMBER_OF_QUEUES; tx_queue++)
+        {
+            eth_tx_queue_address = ETH_TX_QUEUES_TABLE_ADDRESS +
+                ((emac - BL_LILAC_RDD_EMAC_ID_0) * RDD_EMAC_NUMBER_OF_QUEUES + tx_queue) * sizeof(RDD_ETH_TX_QUEUE_DESCRIPTOR_DTS);
+
+            mac_descriptor_address = ETH_TX_MAC_TABLE_ADDRESS + emac * sizeof(RDD_ETH_TX_MAC_DESCRIPTOR_DTS);
+
+            eth_tx_queue_pointers_entry =
+                &(eth_tx_queues_pointers_table->entry[emac * RDD_EMAC_NUMBER_OF_QUEUES + tx_queue]);
+
+            RDD_ETH_TX_QUEUE_POINTERS_ENTRY_ETH_MAC_POINTER_WRITE(mac_descriptor_address, eth_tx_queue_pointers_entry);
+            RDD_ETH_TX_QUEUE_POINTERS_ENTRY_TX_QUEUE_POINTER_WRITE(eth_tx_queue_address, eth_tx_queue_pointers_entry);
+
+            eth_tx_queue_descriptor = &(eth_tx_queues_table->entry[(emac - BL_LILAC_RDD_EMAC_ID_0) * RDD_EMAC_NUMBER_OF_QUEUES + tx_queue]);
+
+            RDD_ETH_TX_QUEUE_DESCRIPTOR_QUEUE_MASK_WRITE(1 << tx_queue , eth_tx_queue_descriptor);
+            RDD_ETH_TX_QUEUE_DESCRIPTOR_INDEX_WRITE((emac * RDD_EMAC_NUMBER_OF_QUEUES) + tx_queue, eth_tx_queue_descriptor);
+        }
+        eth_tx_local_registers_entry = &(eth_tx_local_registers->entry[emac]);
+
+        RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_EMAC_DESCRIPTOR_PTR_WRITE(ETH_TX_MAC_TABLE_ADDRESS +
+            emac * sizeof(RDD_ETH_TX_MAC_DESCRIPTOR_DTS), eth_tx_local_registers_entry);
+
+        RDD_ETH_TX_LOCAL_REGISTERS_ENTRY_ETH_TX_QUEUES_POINTERS_TABLE_PTR_WRITE(ETH_TX_QUEUES_POINTERS_TABLE_ADDRESS +
+            emac * RDD_EMAC_NUMBER_OF_QUEUES * sizeof(RDD_ETH_TX_QUEUE_POINTERS_ENTRY_DTS), eth_tx_local_registers_entry);
+    }
+
+    free_packet_descriptors_pool_descriptor =
+        (RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_DTS *)(DEVICE_ADDRESS(RUNNER_PRIVATE_0_OFFSET) +
+        FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ADDRESS);
+
+    /*Initial values, will be updated by rdd_tm_ds_free_packet_descriptors_pool_size_update.*/
+    RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_THRESHOLD_WRITE ( DS_FREE_PACKET_DESCRIPTOR_POOL_GUARANTEED_QUEUE_THRESHOLD, free_packet_descriptors_pool_descriptor );
+    RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_GUARANTEED_FREE_COUNT_WRITE (DS_FREE_PACKET_DESCRIPTOR_POOL_MIN_GUARANTEED_POOL_SIZE, free_packet_descriptors_pool_descriptor );
+    RDD_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ENTRY_NON_GUARANTEED_FREE_COUNT_WRITE ( RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE - DS_FREE_PACKET_DESCRIPTOR_POOL_MIN_GUARANTEED_POOL_SIZE, free_packet_descriptors_pool_descriptor );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+
+static BL_LILAC_RDD_ERROR_DTE f_rdd_wan_tx_initialize ( void )
+{
+    RDD_WAN_CHANNELS_0_7_TABLE_DTS          *wan_channels_0_7_table_ptr;
+    RDD_WAN_CHANNEL_0_7_DESCRIPTOR_DTS      *wan_channel_0_7_descriptor_ptr;
+    RDD_WAN_CHANNELS_8_39_TABLE_DTS         *wan_channels_8_39_table_ptr;
+    RDD_WAN_CHANNEL_8_39_DESCRIPTOR_DTS     *wan_channel_8_39_descriptor_ptr;
+    RDD_US_RATE_CONTROLLER_DESCRIPTOR_DTS   *dummy_rate_controller_descriptor_ptr;
+    RDD_WAN_TX_QUEUE_DESCRIPTOR_DTS         *dummy_wan_tx_queue_descriptor_ptr;
+    RDD_RATE_CONTROLLER_EXPONENT_TABLE_DTS  *exponent_table_ptr;
+    RDD_RATE_CONTROLLER_EXPONENT_ENTRY_DTS  *exponent_entry_ptr;
+    uint32_t                                wan_channel_id;
+    uint32_t                                rate_controller_id;
+    uint32_t                                tx_queue_id;
+
+    /* initialize WAN TX pointers table */
+    wan_tx_pointers_table_ptr = ( RDD_WAN_TX_POINTERS_TABLE_DTS * )malloc( sizeof( RDD_WAN_TX_POINTERS_TABLE_DTS ) );
+
+    if ( wan_tx_pointers_table_ptr == NULL)
+    {
+        return ( BL_LILAC_RDD_ERROR_MALLOC_FAILED );
+    }
+
+    memset ( wan_tx_pointers_table_ptr, 0, sizeof ( RDD_WAN_TX_POINTERS_TABLE_DTS ) );
+
+    /* reset the dummy segmentation descriptors threshold to zero in order to drop packets */
+    dummy_wan_tx_queue_descriptor_ptr = ( RDD_WAN_TX_QUEUE_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DUMMY_WAN_TX_QUEUE_DESCRIPTOR_ADDRESS - sizeof ( RUNNER_COMMON ) );
+
+    RDD_WAN_TX_QUEUE_DESCRIPTOR_PACKET_THRESHOLD_WRITE ( 0, dummy_wan_tx_queue_descriptor_ptr );
+    RDD_WAN_TX_QUEUE_DESCRIPTOR_PROFILE_PTR_WRITE ( 0, dummy_wan_tx_queue_descriptor_ptr );
+
+    /* all the queues of the dummy rate controller will point to the dummy queue */
+    dummy_rate_controller_descriptor_ptr = ( RDD_US_RATE_CONTROLLER_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_1_OFFSET ) + DUMMY_RATE_CONTROLLER_DESCRIPTOR_ADDRESS - sizeof ( RUNNER_COMMON ) );
+
+    for ( tx_queue_id = 0; tx_queue_id < RDD_US_RATE_CONTROLLER_DESCRIPTOR_TX_QUEUE_ADDR_NUMBER; tx_queue_id++ )
+    {
+        RDD_US_RATE_CONTROLLER_DESCRIPTOR_TX_QUEUE_ADDR_WRITE ( DUMMY_WAN_TX_QUEUE_DESCRIPTOR_ADDRESS, dummy_rate_controller_descriptor_ptr, tx_queue_id );
+    }
+
+    /* connect all the tconts to the dummy rate rate controller */
+    wan_channels_0_7_table_ptr = ( RDD_WAN_CHANNELS_0_7_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_CHANNELS_0_7_TABLE_ADDRESS );
+
+    for ( wan_channel_id = RDD_WAN_CHANNEL_0; wan_channel_id <= RDD_WAN_CHANNEL_7; wan_channel_id++ )
+    {
+        wan_channel_0_7_descriptor_ptr = &( wan_channels_0_7_table_ptr->entry[ wan_channel_id ] );
+
+        for ( rate_controller_id = BL_LILAC_RDD_RATE_CONTROLLER_0; rate_controller_id <= BL_LILAC_RDD_RATE_CONTROLLER_31; rate_controller_id++ )
+        {
+            RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLER_ADDR_WRITE ( DUMMY_RATE_CONTROLLER_DESCRIPTOR_ADDRESS, wan_channel_0_7_descriptor_ptr, rate_controller_id );
+        }
+    }
+
+    wan_channels_8_39_table_ptr = ( RDD_WAN_CHANNELS_8_39_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_CHANNELS_8_39_TABLE_ADDRESS );
+
+    for ( wan_channel_id = RDD_WAN_CHANNEL_8; wan_channel_id <= RDD_WAN_CHANNEL_39; wan_channel_id++ )
+    {
+        wan_channel_8_39_descriptor_ptr = &( wan_channels_8_39_table_ptr->entry[ wan_channel_id - RDD_WAN_CHANNEL_8 ] );
+
+        for ( rate_controller_id = BL_LILAC_RDD_RATE_CONTROLLER_0; rate_controller_id <= BL_LILAC_RDD_RATE_CONTROLLER_3; rate_controller_id++ )
+        {
+            RDD_WAN_CHANNEL_8_39_DESCRIPTOR_RATE_CONTROLLER_ADDR_WRITE ( DUMMY_RATE_CONTROLLER_DESCRIPTOR_ADDRESS, wan_channel_8_39_descriptor_ptr, rate_controller_id );
+        }
+    }
+
+    g_rate_controllers_pool_idx = 0;
+
+    /* initialize exponents table */
+    exponent_table_ptr = ( RDD_RATE_CONTROLLER_EXPONENT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS );
+
+    exponent_entry_ptr = &( exponent_table_ptr->entry[ 0 ] );
+    RDD_RATE_CONTROLLER_EXPONENT_ENTRY_EXPONENT_WRITE ( RDD_RATE_CONTROL_EXPONENT0, exponent_entry_ptr );
+
+    exponent_entry_ptr = &( exponent_table_ptr->entry[ 1 ] );
+    RDD_RATE_CONTROLLER_EXPONENT_ENTRY_EXPONENT_WRITE ( RDD_RATE_CONTROL_EXPONENT1, exponent_entry_ptr );
+
+    exponent_entry_ptr = &( exponent_table_ptr->entry[ 2 ] );
+    RDD_RATE_CONTROLLER_EXPONENT_ENTRY_EXPONENT_WRITE ( RDD_RATE_CONTROL_EXPONENT2, exponent_entry_ptr );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+static BL_LILAC_RDD_ERROR_DTE f_rdd_inter_task_queues_initialize ( void )
+{
+    uint16_t  *wan_enqueue_ingress_queue_ptr;
+    uint16_t  *ethwan2_rx_ingress_queue_ptr;
+
+    wan_enqueue_ingress_queue_ptr = ( uint16_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + WAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS );
+    MWRITE_16( wan_enqueue_ingress_queue_ptr, WAN_ENQUEUE_INGRESS_QUEUE_ADDRESS );
+
+    ethwan2_rx_ingress_queue_ptr = ( uint16_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETHWAN2_RX_INGRESS_QUEUE_PTR_ADDRESS );
+    MWRITE_16( ethwan2_rx_ingress_queue_ptr, ETHWAN2_RX_INGRESS_QUEUE_ADDRESS );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+static BL_LILAC_RDD_ERROR_DTE f_rdd_pm_counters_initialize ( void )
+{
+    RUNNER_REGS_CFG_CNTR_CFG  runner_counter_cfg_register;
+
+    runner_counter_cfg_register.base_address = ( PM_COUNTERS_ADDRESS >> 3 );
+
+    RUNNER_REGS_0_CFG_CNTR_CFG_WRITE ( runner_counter_cfg_register );
+    RUNNER_REGS_1_CFG_CNTR_CFG_WRITE ( runner_counter_cfg_register );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+
+static BL_LILAC_RDD_ERROR_DTE f_rdd_parallel_processing_initialize ( void )
+{
+    RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS  *ds_context_index_cache_cam;
+    RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_DTS  *us_context_index_cache_cam;
+    RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_DTS                *ds_available_slave_vector_ptr;
+    RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_DTS                *us_available_slave_vector_ptr;
+    RDD_PARALLEL_PROCESSING_IH_BUFFER_PTR_DTS               *ds_slave_ih_buffer_ptr;
+    RDD_PARALLEL_PROCESSING_IH_BUFFER_PTR_DTS               *us_slave_ih_buffer_ptr;
+    uint16_t                                                *ds_context_index_cache_cam_entry;
+    uint16_t                                                *us_context_index_cache_cam_entry;
+    uint8_t                                                 *context_cache_state_ptr;
+    uint8_t                                                 i;
+
+    /* downstream */
+    ds_available_slave_vector_ptr = ( RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_DTS * )( DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS );
+
+    RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE0_WRITE ( LILAC_RDD_TRUE, ds_available_slave_vector_ptr );
+    RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE1_WRITE ( LILAC_RDD_TRUE, ds_available_slave_vector_ptr );
+    RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE2_WRITE ( LILAC_RDD_TRUE, ds_available_slave_vector_ptr );
+    RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE3_WRITE ( LILAC_RDD_TRUE, ds_available_slave_vector_ptr );
+
+    ds_slave_ih_buffer_ptr = ( RDD_PARALLEL_PROCESSING_IH_BUFFER_PTR_DTS * )( DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS );
+
+    MWRITE_16( ds_slave_ih_buffer_ptr, DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS );
+
+    ds_context_index_cache_cam = RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_PTR();
+
+    for ( i = 0; i < RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE; i++ )
+    {
+        ds_context_index_cache_cam_entry = ( uint16_t * ) &ds_context_index_cache_cam->entry[ i ];
+
+        MWRITE_16( ds_context_index_cache_cam_entry, 0xFFFF );
+    }
+
+    /* set context cache in enable mode */
+    context_cache_state_ptr = ( uint8_t * )( DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_ADDRESS );
+
+    MWRITE_8( context_cache_state_ptr, 0x0 );
+
+    /* upstream */
+    us_available_slave_vector_ptr = ( RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_DTS * )( DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS );
+
+    RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE0_WRITE ( LILAC_RDD_TRUE, us_available_slave_vector_ptr );
+    RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE1_WRITE ( LILAC_RDD_TRUE, us_available_slave_vector_ptr );
+    RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE2_WRITE ( LILAC_RDD_TRUE, us_available_slave_vector_ptr );
+    RDD_PARALLEL_PROCESSING_SLAVE_VECTOR_AVAILABLE_SLAVE3_WRITE ( LILAC_RDD_TRUE, us_available_slave_vector_ptr );
+
+    us_slave_ih_buffer_ptr = ( RDD_PARALLEL_PROCESSING_IH_BUFFER_PTR_DTS * )( DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS );
+
+    MWRITE_16( us_slave_ih_buffer_ptr, US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS );
+
+    us_context_index_cache_cam = RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_PTR();
+
+    for ( i = 0; i < RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE; i++ )
+    {
+        us_context_index_cache_cam_entry = ( uint16_t * ) &us_context_index_cache_cam->entry[ i ];
+
+        MWRITE_16( us_context_index_cache_cam_entry, 0xFFFF );
+    }
+
+    /* set context cache in enable mode */
+    context_cache_state_ptr = ( uint8_t * )( DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_ADDRESS );
+
+    MWRITE_8( context_cache_state_ptr, 0x0 );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+BL_LILAC_RDD_ERROR_DTE rdd_ethwan2_switch_port_config ( uint8_t xi_switch_port )
+{
+    uint8_t *ethwan2_switch_port_config_ptr;
+
+    ethwan2_switch_port_config_ptr = ( uint8_t * )(DEVICE_ADDRESS( RUNNER_PRIVATE_1_OFFSET ) + ETHWAN2_SWITCH_PORT_ADDRESS );
+    MWRITE_8( ethwan2_switch_port_config_ptr, xi_switch_port );
+    return ( BL_LILAC_RDD_OK );
+}
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_init.h b/arch/arm/mach-bcmbca/rdp/rdd_init.h
new file mode 100755
index 0000000000..3b958b7d84
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_init.h
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef _BL_LILAC_DRV_RUNNER_INIT_H
+#define _BL_LILAC_DRV_RUNNER_INIT_H
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_init                                                                 */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - initialize the firmware driver                         */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   resets Runner memories (data, program and context), should be called     */
+/*   after reset and before any other API                                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   none                                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_init ( void );
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_load_microcode                                                       */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - load the microcode into the SRAM program memory        */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   Four Runners are loaded (the code is imported as a C code array)         */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_runer_A_microcode_ptr - Fast Runner 0 microcode                       */
+/*   xi_runer_B_microcode_ptr - Fast Runner 1 microcode                       */
+/*   xi_runer_C_microcode_ptr - Pico Runner 0 microcode                       */
+/*   xi_runer_D_microcode_ptr - Pico Runner 1 microcode                       */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_load_microcode ( uint8_t  *xi_runer_A_microcode_ptr,
+                                            uint8_t  *xi_runer_B_microcode_ptr,
+                                            uint8_t  *xi_runer_C_microcode_ptr,
+                                            uint8_t  *xi_runer_D_microcode_ptr );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_load_prediction                                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - load the jump prediction into SRAM                     */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   Four Runners are loaded (the prediction is imported as bin file)         */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_runer_A_prediction_ptr - Fast Runner 0 prediction                     */
+/*   xi_runer_B_prediction_ptr - Fast Runner 1 prediction                     */
+/*   xi_runer_C_prediction_ptr - Pico Runner 0 prediction                     */
+/*   xi_runer_D_prediction_ptr - Pico Runner 1 prediction                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_load_prediction ( uint8_t  *xi_runer_A_prediction_ptr,
+                                             uint8_t  *xi_runer_B_prediction_ptr,
+                                             uint8_t  *xi_runer_C_prediction_ptr,
+                                             uint8_t  *xi_runer_D_prediction_ptr );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_runner_enable                                                        */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - Enables the Runner                                     */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This API move the Runner from halt mode to running mode, firmware starts */
+/*   execute.                                                                 */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   Runner_Global_Control register                                           */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   none                                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_runner_enable ( void );
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_runner_frequency_set                                                 */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - set the frequency of the Runner timers                 */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This API set the frequency of the Runner timers                          */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   Runner_Global_Control register                                           */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_runner_frequency - Runner frequency in MHZ                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_runner_frequency_set ( uint16_t  xi_runner_frequency );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_data_structures_init                                                 */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - initialize all firmware data structures to a default   */
+/*                     state, should be called after reset and                */
+/*                     rdd_init() API and before any other API.               */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures the schedule mechansim of a single TCONT.       */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ddr_pool_ptr - packet DDR buffer base address                         */
+/*   xi_extra_ddr_pool_ptr - packet DDR buffer base address (Multicast)       */
+/*   xi_mac_table_size - Mac lookup table size                                */
+/*   xi_mac_table_search_depth - Mac lookup table maximum search depth        */
+/*   xi_wan_physical_port - GPON EMAC5 or EMAC4                               */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_data_structures_init ( RDD_INIT_PARAMS  *init_params );
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_bbh_reset_firmware_fifo_init                                         */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   actions which are needed after BBH reset                                 */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function need to be called by SW after BBH reset                    */
+/*   1) initialize emac ingress/egress counters                               */
+/*   2) wakeup the runner to initialize BBH descriptor pointer                */
+/*	                       (using error + ploam bits)                         */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_src_bridge_port - bridge port                                         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_bbh_reset_firmware_fifo_init ( BL_LILAC_RDD_BRIDGE_PORT_DTE  xi_src_bridge_port );
+
+/******************************************************************************/
+/*                                                                            */
+/* Description:                                                               */
+/*                                                                            */
+/*   This function sets the switch port for ethwan2.                          */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   None                                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xi_switch_port - ethwan2 switch port                                     */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_ethwan2_switch_port_config ( uint8_t xi_switch_port );
+
+
+#endif /* _BL_LILAC_DRV_RUNNER_INIT_H */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_lookup_engine.h b/arch/arm/mach-bcmbca/rdp/rdd_lookup_engine.h
new file mode 100755
index 0000000000..79264754c4
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_lookup_engine.h
@@ -0,0 +1,592 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef _BL_LILAC_DRV_RUNNER_LOOKUP_ENGINE_H
+#define _BL_LILAC_DRV_RUNNER_LOOKUP_ENGINE_H
+
+
+#define MAC_ENTRY_KEY_MASK_HIGH                         0x0000FFFF
+#define MAC_ENTRY_KEY_MASK_LOW                          0xFFFFFFFF
+#define MAC_ENTRY_INTERNAL_CONTEXT_MASK_HIGH            0xFFF00000
+#define MAC_ENTRY_INTERNAL_CONTEXT_MASK_LOW             0x00000000
+#ifdef UNDEF
+#define DS_FLOW_CLASSIFICATION_ENTRY_KEY_MASK_HIGH      0x00000000
+#define DS_FLOW_CLASSIFICATION_ENTRY_KEY_MASK_LOW       0x00FFFFFF
+#define US_FLOW_CLASSIFICATION_ENTRY_KEY_MASK_HIGH      0x00000000
+#define US_FLOW_CLASSIFICATION_ENTRY_KEY_MASK_LOW       0x00FFFFFF
+#else
+#define INGRESS_CLASSIFICATION_IH_ENTRY_KEY_MASK_HIGH          0x000FFFFF
+#define INGRESS_CLASSIFICATION_IH_ENTRY_KEY_MASK_LOW           0xFFFFFFFF
+#define INGRESS_CLASSIFICATION_OPTIMIZED_ENTRY_KEY_MASK_HIGH   0x000FFFFF
+#define INGRESS_CLASSIFICATION_OPTIMIZED_ENTRY_KEY_MASK_LOW    0xFFFFFFFF
+#define INGRESS_CLASSIFICATION_SHORT_ENTRY_KEY_MASK_HIGH       0x000FFFFF
+#define INGRESS_CLASSIFICATION_SHORT_ENTRY_KEY_MASK_LOW        0xFFFFFFFF
+#define INGRESS_CLASSIFICATION_LONG_ENTRY_KEY_MASK_HIGH        0x00FFFFFF
+#define INGRESS_CLASSIFICATION_LONG_ENTRY_KEY_MASK_LOW         0xFFFFFFFF
+#endif
+#define IPTV_ENTRY_KEY_MASK_HIGH                        0x0FFFFFFF
+#define IPTV_ENTRY_KEY_MASK_LOW                         0xFFFFFFFF
+#define IPTV_ENTRY_INTERNAL_CONTEXT_MASK_HIGH           0xFFF00000
+#define IPTV_ENTRY_INTERNAL_CONTEXT_MASK_LOW            0x00000000
+#define IPTV_L3_ENTRY_KEY_MASK_HIGH                     0x00000000
+#define IPTV_L3_ENTRY_KEY_MASK_LOW                      0xFFFFFFFF
+#define IPTV_L3_SSM_SRC_IP_ENTRY_KEY_MASK_HIGH          0x0FFFFFFF
+#define IPTV_L3_SSM_SRC_IP_ENTRY_KEY_MASK_LOW           0xFFFFFFFF
+
+
+typedef enum
+{
+    BL_LILAC_RDD_MAC_TABLE                             = 0,
+#ifdef UNDEF
+    BL_LILAC_RDD_DS_FLOW_CLASSIFICATION_TABLE = 1,
+    BL_LILAC_RDD_US_FLOW_CLASSIFICATION_TABLE = 2,
+#else
+    BL_LILAC_RDD_DS_INGRESS_CLASSIFICATION_SHORT_TABLE = 1,
+    BL_LILAC_RDD_US_INGRESS_CLASSIFICATION_SHORT_TABLE = 2,
+    BL_LILAC_RDD_DS_INGRESS_CLASSIFICATION_LONG_TABLE  = 3,
+    BL_LILAC_RDD_US_INGRESS_CLASSIFICATION_LONG_TABLE  = 4,
+#endif
+    BL_LILAC_RDD_IPTV_TABLE                            = 7,
+    BL_LILAC_RDD_IPTV_SRC_IP_TABLE                     = 8,
+    BL_LILAC_RDD_MAX_HASH_TABLE                        = 9,
+}
+BL_LILAC_RDD_HASH_TABLE_NUMBER_DTS;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_ADD_ENTRY    = 0,
+    BL_LILAC_RDD_MODIFY_ENTRY = 1,
+    BL_LILAC_RDD_REMOVE_ENTRY = 2,
+}
+BL_LILAC_RDD_HASH_TABLE_WRITE_TYPE_DTS;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_CONTEXT_8_BIT  = 1,
+    BL_LILAC_RDD_CONTEXT_16_BIT = 2,
+    BL_LILAC_RDD_CONTEXT_32_BIT = 4,
+    BL_LILAC_RDD_CONTEXT_64_BIT = 8,
+}
+BL_LILAC_RDD_CONTEXT_ENTRY_SIZE_DTS;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_EXTERNAL_CONTEXT_DISABLE = 0,
+    BL_LILAC_RDD_EXTERNAL_CONTEXT_ENABLE  = 1,
+}
+BL_LILAC_RDD_EXTERNAL_CONTEXT_FLAG_DTS;
+
+
+typedef enum
+{
+    BL_LILAC_RDD_CAM_OPTIMIZATION_DISABLE = 0,
+    BL_LILAC_RDD_CAM_OPTIMIZATION_ENABLE  = 1,
+}
+BL_LILAC_RDD_CAM_OPTIMIZATION_CONTROL_DTS;
+
+
+/* This enumerated type can only include up to 4 values as a hardware limitation */
+typedef enum
+{
+    BL_LILAC_RDD_DDR_GLOBAL_MASK_FIVE_TUPLE_KEY = 0x000001FF,
+    BL_LILAC_RDD_DDR_GLOBAL_MASK_96_BIT_KEY     = 0x00000000,
+    BL_LILAC_RDD_DDR_GLOBAL_MASK_127_BIT_KEY    = 0x7FFFFFFF,
+    BL_LILAC_RDD_DDR_GLOBAL_MASK_RESERVED       = 0xFFFFFFFF
+}
+BL_LILAC_RDD_DDR_GLOBAL_MASK_DTS;
+
+
+typedef struct
+{
+    uint8_t entry[ 16 ];
+}
+RDD_DDR_TABLE_ENTRY_DTS;
+
+
+typedef struct
+{
+    uint8_t entry[ 8 ];
+}
+RDD_64_BIT_TABLE_ENTRY_DTS;
+
+
+typedef struct
+{
+    uint8_t entry[ 4 ];
+}
+RDD_32_BIT_TABLE_ENTRY_DTS;
+
+
+typedef struct
+{
+    uint8_t entry[ 2 ];
+}
+RDD_16_BIT_TABLE_ENTRY_DTS;
+
+
+typedef struct
+{
+    uint8_t entry;
+}
+RDD_8_BIT_TABLE_ENTRY_DTS;
+
+
+typedef struct
+{
+    RDD_64_BIT_TABLE_ENTRY_DTS           *hash_table_ptr;
+    uint8_t                              *context_table_ptr;
+    uint32_t                             hash_table_size;
+    uint32_t                             hash_table_search_depth;
+    uint32_t                             is_external_context;
+    BL_LILAC_RDD_CONTEXT_ENTRY_SIZE_DTS  context_size;
+    uint32_t                             is_extension_cam;
+    RDD_64_BIT_TABLE_ENTRY_DTS           *cam_table_ptr;
+    uint8_t                              *cam_context_table_ptr;
+    uint32_t                             cam_table_size;
+}
+RDD_64_BIT_TABLE_CFG;
+
+
+#define RDD_HASH_TABLE_ENTRY_READ( r, p, i )       MREAD_I_8( ( uint8_t *)p, i, r )
+#define RDD_HASH_TABLE_ENTRY_WRITE( v, p, i )      MWRITE_I_8( ( uint8_t *)p, i, v )
+#define RDD_HASH_TABLE_ENTRY_AGING_READ( r, p )    FIELD_MREAD_32( ( (uint8_t *)p + 4),  2,  1, r )
+#define RDD_HASH_TABLE_ENTRY_SKIP_READ( r, p )     FIELD_MREAD_32( ( (uint8_t *)p + 4),  1,  1, r )
+#define RDD_HASH_TABLE_ENTRY_VALID_READ( r, p )    FIELD_MREAD_32( ( (uint8_t *)p + 4),  0,  1, r )
+#define RDD_HASH_TABLE_ENTRY_AGING_WRITE( v, p )   FIELD_MWRITE_32( ( (uint8_t *)p + 4 ), 2,  1, v )
+#define RDD_HASH_TABLE_ENTRY_SKIP_WRITE( v, p )    FIELD_MWRITE_32( ( (uint8_t *)p + 4 ), 1,  1, v )
+#define RDD_HASH_TABLE_ENTRY_VALID_WRITE( v, p )   FIELD_MWRITE_32( ( (uint8_t *)p + 4 ), 0,  1, v )
+
+
+typedef struct
+{
+    uint32_t  valid		             :1  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+    uint32_t  cache_flag             :1  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+    uint32_t  context_entry_ptr      :25 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t  reserved_0             :5  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+    uint32_t  reserved_1             :32 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+    uint32_t  reserved_2             :32 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+    uint32_t  reserved_3             :32 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DDR_HASH_TABLE_ENTRY;
+
+
+#define RDD_DDR_HASH_TABLE_ENTRY_VALID_READ( r, p )           FIELD_MREAD_32( ( (uint8_t *)p + 0 ), 31,  1, r )
+#define RDD_DDR_HASH_TABLE_ENTRY_CACHE_FLAG_READ( r, p )      FIELD_MREAD_32( ( (uint8_t *)p + 0 ), 30,  1, r )
+#define RDD_DDR_HASH_TABLE_ENTRY_CONTEXT_PTR_READ( r , p )    FIELD_MREAD_32( ( (uint8_t *)p + 0 ), 5,  25, r )
+#define RDD_DDR_HASH_TABLE_ENTRY_VALID_WRITE( v, p )          FIELD_MWRITE_32( ( (uint8_t *)p + 0 ), 31,  1, v )
+#define RDD_DDR_HASH_TABLE_ENTRY_CACHE_FLAG_WRITE( v, p )     FIELD_MWRITE_32( ( (uint8_t *)p + 0 ), 30,  1, v )
+#define RDD_DDR_HASH_TABLE_ENTRY_CONTEXT_PTR_WRITE( v , p )   FIELD_MWRITE_32( ( (uint8_t *)p + 0 ), 5,  25, v )
+
+
+
+typedef struct
+{
+    uint32_t  valid		             :1  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+    uint32_t  reserved_0             :31 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t  reserved_1             :32 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DDR_HASH_TABLE_CONTEXT_ENTRY;
+
+
+#define RDD_DDR_HASH_TABLE_CONTEXT_ENTRY_VALID_READ( r, p )    FIELD_MREAD_32( ( (uint8_t *)p + 0 ), 31,  1, r )
+#define RDD_DDR_HASH_TABLE_CONTEXT_ENTRY_VALID_WRITE( v, p )   FIELD_MWRITE_32( ( (uint8_t *)p + 0 ), 31,  1, v )
+
+
+
+typedef struct
+{
+    RDD_DDR_TABLE_ENTRY_DTS              *hash_table_ptr;
+    uint32_t                             hash_table_size;
+    uint32_t                             hash_table_bucket_size;
+    uint32_t                             is_external_context;
+    uint8_t                              *context_table_ptr;
+    BL_LILAC_RDD_CONTEXT_ENTRY_SIZE_DTS  context_size;
+    uint32_t                             context_table_size;
+    uint32_t                             non_cached_entries_counter;
+    BL_LILAC_RDD_DDR_GLOBAL_MASK_DTS     global_mask;
+    uint32_t                             context_entries_free_list_head;
+    uint32_t                             context_entries_free_list_tail;
+    uint16_t                             *context_entries_free_list;
+    uint32_t                             context_table_offset;
+    uint32_t                             *search_ddr_flag_address;
+}
+RDD_DDR_TABLE_CFG;
+
+
+
+/* CRC */
+#define RDD_CRC_TYPE_16                            0
+#define RDD_CRC_TYPE_32                            1
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_find_hash_entry_64_bit                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Find key in hash table                                                   */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function finds a key in a generic hash table and returns the        */
+/*   status of the operation.                                                 */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   none.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*    *xi_hash_table_cfg - hash table configuration data                      */
+/*    *xi_hash_key - key to be searched in hash table                         */
+/*    *xi_crc_init_value - initial value to be used in hashing the key        */
+/*    xi_mask_high - mask for the high part of the entry                      */
+/*    xi_mask_low - mask for the low part of the entry                        */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*    *xo_entry_index - used for returning the index that was found ( in      */
+/*       case it was found )                                                  */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_find_hash_entry_64_bit ( RDD_64_BIT_TABLE_CFG  *xi_hash_table_cfg,
+                                                    uint8_t               *xi_hash_key,
+                                                    uint32_t              xi_mask_high,
+                                                    uint32_t              xi_mask_low,
+                                                    uint32_t              xi_crc_init_value,
+                                                    uint32_t              *xo_entry_index );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_find_entry_64_bit                                                    */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Find key in hash or in cam table                                         */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function searches hash, and if no match, cam tables                 */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*    *xi_table_cfg - table configuration data                                */
+/*    *xi_cam_key - key to be searched in table                               */
+/*    xi_mask_high - mask for the high part of the entry                      */
+/*    xi_mask_low - mask for the low part of the entry                        */
+/*    xi_crc_init_value - initial crc value for hash                          */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*    *xo_entry_index - used for returning the index that was found ( in      */
+/*    case it was found ). hit in CAM is marked by index >= hash table size   */
+/*                                                                            */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_find_entry_64_bit ( RDD_64_BIT_TABLE_CFG  *xi_table_cfg,
+                                               uint8_t               *xi_key,
+                                               uint32_t              xi_mask_high,
+                                               uint32_t              xi_mask_low,
+                                               uint32_t              xi_crc_init_value,
+                                               uint32_t              *xo_entry_index );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_write_control_bits                                                   */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Write control bits to hash table entry                                   */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function writes control bits to entry, according to the passed      */
+/*       write type.                                                          */
+/*                                                                            */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   none.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*    *xi_table_ptr - pointer to first entry                                  */
+/*    xi_table_size - table size ( used only for remove entry write type )    */
+/*    xi_entry_index - index of the entry                                     */
+/*    xi_write_type - add/modify/remove ( for hash table control bits )       */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*    none.                                                                   */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_write_control_bits ( RDD_64_BIT_TABLE_ENTRY_DTS              *xi_table_ptr,
+                                                uint32_t                                xi_table_size,
+                                                uint32_t                                xi_entry_index,
+                                                BL_LILAC_RDD_HASH_TABLE_WRITE_TYPE_DTS  xi_write_type );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_add_hash_entry_64_bit                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   add hash table entry                                                     */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function adds an entry (and optionally its context) to a hash       */
+/*       table.                                                               */
+/*                                                                            */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   none.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*    *xi_table_cfg - hash table configuration data                           */
+/*    *xi_hash_entry_ptr - key to be hashed                                   */
+/*    *xi_context_entry_ptr - external context to be written                  */
+/*    xi_key_mask_high - mask for the high part of the entry                  */
+/*    xi_key_mask_low - mask for the low part of the entry                    */
+/*    xi_crc_init_value - initial value to be used in hashing the key         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*    *xo_entry_index - the index in table where the entry was added          */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_add_hash_entry_64_bit ( RDD_64_BIT_TABLE_CFG  *xi_table_cfg,
+                                                   uint8_t               *xi_hash_entry_ptr,
+                                                   uint8_t               *xi_context_entry_ptr,
+                                                   uint32_t              xi_key_mask_high,
+                                                   uint32_t              xi_key_mask_low,
+                                                   uint32_t              xi_crc_init_value,
+                                                   uint32_t              *xo_entry_index );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_modify_hash_entry_64_bit                                             */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   modify hash table entry                                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function modifies an entry (and optionally its context) in a hash   */
+/*       table.                                                               */
+/*                                                                            */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   none.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*    *xi_table_cfg - table configuration data                                */
+/*    *xi_hash_entry_ptr - key to be hashed                                   */
+/*    xi_context_entry_ptr - context to be written                            */
+/*    xi_key_mask_high - mask for the high part of the key                    */
+/*    xi_key_mask_low - mask for the low part of the key                      */
+/*    xi_internal_context_mask_high - mask for the high part of the entry     */
+/*    xi_internal_context_mask_low - mask for the low part of the entry       */
+/*    xi_crc_init_value - initial value to be used in hashing the key         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*    *xo_entry_index - the index in table where the entry was modified       */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_modify_hash_entry_64_bit ( RDD_64_BIT_TABLE_CFG  *xi_table_cfg,
+                                                      uint8_t               *xi_hash_entry_ptr,
+                                                      uint8_t               *xi_context_entry_ptr,
+                                                      uint32_t              xi_key_mask_high,
+                                                      uint32_t              xi_key_mask_low,
+                                                      uint32_t              xi_internal_context_mask_high,
+                                                      uint32_t              xi_internal_context_mask_low,
+                                                      uint32_t              xi_crc_init_value,
+                                                      uint32_t              *xo_entry_index );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_remove_hash_entry_64_bit                                             */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   remove hash table entry                                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function removes an entry from a hash table                         */
+/*                                                                            */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   none.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*    *xi_table_cfg - hash table configuration data                           */
+/*    *xi_hash_entry_ptr - key to be hashed                                   */
+/*    xi_crc_init_value - initial value to be used in hashing the key         */
+/*    xi_key_mask_high - mask for the high part of the key                    */
+/*    xi_key_mask_low - mask for the low part of the key                      */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*    *xo_entry_index - the index in table where the entry was removed        */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_remove_hash_entry_64_bit ( RDD_64_BIT_TABLE_CFG                       *xi_table_cfg,
+                                                      uint8_t                                    *xi_hash_entry_ptr,
+                                                      uint32_t                                   xi_key_mask_high,
+                                                      uint32_t                                   xi_key_mask_low,
+                                                      uint32_t                                   xi_crc_init_value,
+                                                      BL_LILAC_RDD_CAM_OPTIMIZATION_CONTROL_DTS  xi_cam_optimization_control,
+                                                      uint32_t                                   *xo_entry_index );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_find_hash_entry_ddr                                                  */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Find key in hash table                                                   */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function finds a key in a generic hash table and returns the        */
+/*   status of the operation.                                                 */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   none.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*    *xi_hash_key - key to be searched in hash table                         */
+/*    xi_hash_table_cfg_ptr - hash table configuration data                   */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*    *xo_entry_index - used for returning the index that was found ( in      */
+/*       case it was found )                                                  */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_find_hash_entry_ddr ( RDD_DDR_TABLE_CFG  *xi_table_cfg_ptr,
+                                                 uint8_t            *xi_hash_key,
+                                                 uint32_t           *xo_entry_index );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_add_hash_entry_ddr                                                   */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   add hash table entry                                                     */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function adds an entry (and optionally its context) to a hash       */
+/*       table.                                                               */
+/*                                                                            */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   none.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*    xi_table_cfg_ptr - hash table configuration data                        */
+/*    *xi_hash_entry_ptr - key to be hashed                                   */
+/*    *xi_context_entry_ptr - external context to be written                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*    *xo_entry_index - the index in table where the entry was added          */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_add_hash_entry_ddr ( RDD_DDR_TABLE_CFG  *xi_table_cfg_ptr,
+                                                uint8_t            *xi_hash_entry_ptr,
+                                                uint8_t            *xi_context_entry_ptr,
+                                                uint32_t           cache_flag,
+                                                uint32_t           *xo_entry_index );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_remove_hash_entry_ddr                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   remove hash table entry                                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function removes an entry from a hash table                         */
+/*                                                                            */
+/*                                                                            */
+/* Registers :                                                                */
+/*                                                                            */
+/*   none.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*    xi_table_cfg_ptr - hash table configuration data                        */
+/*    *xi_hash_entry_ptr - key to be hashed                                   */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*    *xo_entry_index - the index in table where the entry was removed        */
+/*                                      .                                     */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_remove_hash_entry_ddr ( RDD_DDR_TABLE_CFG  *xi_table_cfg_ptr,
+                                                   uint8_t            *xi_hash_entry_ptr,
+                                                   uint32_t           *xo_entry_index );
+
+
+#endif /* _BL_LILAC_DRV_RUNNER_LOOKUP_ENGINE_H */
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_platform.h b/arch/arm/mach-bcmbca/rdp/rdd_platform.h
new file mode 100755
index 0000000000..ab68cb91f7
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_platform.h
@@ -0,0 +1,216 @@
+/*
+   <:copyright-BRCM:2014-2016:DUAL/GPL:standard
+   
+      Copyright (c) 2014-2016 Broadcom 
+      All Rights Reserved
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License, version 2, as published by
+   the Free Software Foundation (the "GPL").
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   
+   A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+   writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.
+   
+   :>
+ */
+
+#ifndef _RDD_PLATFORM_H
+#define _RDD_PLATFORM_H
+
+#include "rdp_map.h"
+#include "access_macros.h"
+
+typedef enum
+{
+    rdd_runner_0, /* 3rd GEN RDP - MAIN A */
+    rdd_runner_1, /* 3rd GEN RDP - MAIN B */
+    rdd_runner_2, /* 3rd GEN RDP - PICO A */
+    rdd_runner_3, /* 3rd GEN RDP - PICO B */
+    rdd_runner_last
+} rdd_runner_t;
+
+typedef enum
+{
+    rdd_mem_0, /* 3rd GEN RDP - PRIVATE A */
+    rdd_mem_1, /* 3rd GEN RDP - PRIVATE B */
+    rdd_mem_last
+} rdd_mem_t;
+
+typedef struct
+{
+    int runner_vector; /* runners pertaining to group */
+    int mem_vector; /* memories pertaining to group */
+} rdd_runner_group_t;
+
+typedef enum
+{
+    rdd_size_8,
+    rdd_size_16,
+    rdd_size_32
+} rdd_entry_size_t;
+
+typedef struct rdd_module
+{
+    rdd_runner_group_t *group;
+    int (*init)(const struct rdd_module *);
+    uint32_t context_offset;
+    uint32_t context_size;
+    uint32_t res_offset;
+    uint32_t cfg_ptr;
+    void *params;
+} rdd_module_t;
+
+static inline void _rdd_module_init(rdd_module_t *module)
+{
+    if (module->init)
+        module->init(module);
+}
+
+/* TODO: REMOVE */
+#define MWRITE_GROUP_BLOCK_32(group, addr, block, size) _rdd_block_write(group, (addr), block, rdd_size_32, size)
+#define MWRITE_GROUP_BLOCK_16(group, addr, block, size) _rdd_block_write(group, (addr), block, rdd_size_16, size)
+
+static inline uint32_t _rdd_mem_to_base_addr(rdd_mem_t mem)
+{
+    switch (mem)
+    {
+    case rdd_mem_0:
+        return RUNNER_PRIVATE_0_OFFSET;
+    case rdd_mem_1:
+        return RUNNER_PRIVATE_1_OFFSET;
+    default:
+        return 0;
+    }
+}
+
+static inline void _rdd_i_write(rdd_runner_group_t *group, uint32_t addr, uint32_t val, uint32_t i,
+    rdd_entry_size_t size)
+{
+    uint32_t *entry;
+    int mem;
+
+    for (mem = rdd_mem_0; mem < rdd_mem_last; mem++)
+    {
+        if (!(group->mem_vector & 1 << mem))
+            continue;
+
+        entry = (uint32_t *)(DEVICE_ADDRESS(_rdd_mem_to_base_addr(mem)) + addr);
+        switch (size)
+        {
+        case rdd_size_32:
+            MWRITE_I_32(entry, i, val);
+            break;
+        case rdd_size_16:
+            MWRITE_I_16(entry, i, val);
+            break;
+        default:
+            MWRITE_I_8(entry, i, val);
+            break;
+        }
+    }
+}
+
+static inline uint32_t _rdd_i_read(rdd_runner_group_t *group, uint32_t addr, uint32_t i, rdd_entry_size_t size)
+{
+    uint32_t *entry;
+    int mem;
+
+    for (mem = rdd_mem_0; mem < rdd_mem_last; mem++)
+    {
+        if (!(group->mem_vector & 1 << mem))
+            continue;
+
+        entry = (uint32_t *)(DEVICE_ADDRESS(_rdd_mem_to_base_addr(mem)) + addr);
+        switch (size)
+        {
+        case rdd_size_32:
+            return MGET_I_32(entry, i);
+        case rdd_size_16:
+            return MGET_I_16(entry, i);
+        default:
+            return MGET_I_8(entry, i);
+        }
+    }
+    return 0;
+}
+
+static inline void _rdd_field_write(rdd_runner_group_t *group, uint32_t addr, uint32_t val, uint32_t lsb, uint32_t width,
+    rdd_entry_size_t size)
+{
+    uint32_t *entry;
+    int mem;
+
+    for (mem = rdd_mem_0; mem < rdd_mem_last; mem++)
+    {
+        if (!(group->mem_vector & 1 << mem))
+            continue;
+
+        entry = (uint32_t *)(DEVICE_ADDRESS(_rdd_mem_to_base_addr(mem)) + addr);
+        switch (size)
+        {
+        case rdd_size_32:
+            FIELD_MWRITE_32(entry, lsb, width, val);
+            break;
+        case rdd_size_16:
+            FIELD_MWRITE_16(entry, lsb, width, val);
+            break;
+        default:
+            FIELD_MWRITE_8(entry, lsb, width, val);
+            break;
+        }
+    }
+}
+
+static inline uint32_t _rdd_field_read(rdd_runner_group_t *group, uint32_t addr, uint32_t lsb, uint32_t width,
+    rdd_entry_size_t size)
+{
+    uint32_t *entry;
+    int mem;
+
+    for (mem = rdd_mem_0; mem < rdd_mem_last; mem++)
+    {
+        if (!(group->mem_vector & 1 << mem))
+            continue;
+
+        entry = (uint32_t *)(DEVICE_ADDRESS(_rdd_mem_to_base_addr(mem)) + addr);
+        switch (size)
+        {
+        case rdd_size_32:
+            return FIELD_MGET_32(entry, lsb, width);
+        case rdd_size_16:
+            return FIELD_MGET_16(entry, lsb, width);
+        default:
+            return FIELD_MGET_8(entry, lsb, width);
+        }
+    }
+    return 0;
+}
+
+static inline void _rdd_block_write(rdd_runner_group_t *group, const uint32_t addr, uint32_t *block,
+    uint32_t block_size, uint32_t size)
+{
+    int mem;
+
+    for (mem = rdd_mem_0; mem < rdd_mem_last; mem++)
+    {
+        if (!(group->mem_vector & 1 << mem))
+            continue;
+        switch (block_size)
+        {
+        case rdd_size_32:
+            MWRITE_BLK_32((uint32_t *)(DEVICE_ADDRESS(_rdd_mem_to_base_addr(mem)) + addr), block, size);
+            break;
+        case rdd_size_16:
+            MWRITE_BLK_16((uint16_t *)(DEVICE_ADDRESS(_rdd_mem_to_base_addr(mem)) + addr), block, size);
+            break;
+        }
+    }
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_runner_defs.h b/arch/arm/mach-bcmbca/rdp/rdd_runner_defs.h
new file mode 100755
index 0000000000..d1febc8660
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_runner_defs.h
@@ -0,0 +1,1107 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef _BL_LILAC_DRV_RUNNER_DEFS_H
+#define _BL_LILAC_DRV_RUNNER_DEFS_H
+
+#ifdef RUNNER_A
+#define BPM_REPLY_ADDRESS                                           ( BPM_REPLY_RUNNER_A_ADDRESS )
+#else
+#define BPM_REPLY_ADDRESS                                           ( BPM_REPLY_RUNNER_B_ADDRESS )
+#endif
+#if defined(WL4908)
+#define BPM_TRANSITION_STATE_ADDRESS                                ( BPM_REPLY_ADDRESS + 0x20 )
+#else
+#define BPM_TRANSITION_STATE_ADDRESS                                ( BPM_REPLY_RUNNER_A_ADDRESS + 0x20 )
+#endif
+
+#define FIREWALL_CFG_REG_RULES_MAP_TABLE_ADDRESS                    ( FIREWALL_CONFIGURATION_REGISTER_ADDRESS )
+#define FIREWALL_CFG_REG_RULES_TABLE_ADDRESS                        ( FIREWALL_CONFIGURATION_REGISTER_ADDRESS + 4 )
+
+#define LOCAL_SWITCHING_MULTICAST_INGRESS_QUEUE_PTR_ADDRESS         ( PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS + d.28 )
+
+#define DMA_SYNCHRONIZATION_DUMMY_ADDRESS                           0xFFFF0000
+#define DDR_ADDRESS_FOR_DMA_SYNC                                    0xFFFF0000
+
+#define BCR_HASH_BASED_FORWARDING_PORT_COUNT_ADDRESS            ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_HASH_BASED_FORWARDING_PORT_COUNT_OFFSET )
+#define BCR_TIMER_SCHEDULER_TIMER_ADDRESS                       ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_TIMER_SCHEDULER_PERIOD_OFFSET )
+#define BCR_POLICERS_TIMER_ADDRESS                              ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_POLICERS_PERIOD_OFFSET )
+#define BCR_ACTIVE_POLICERS_VECTOR_ADDRESS                      ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_ACTIVE_POLICERS_VECTOR_OFFSET )
+#define BCR_INTER_LAN_SCHEDULING_MODE_ADDRESS                   ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_INTER_LAN_SCHEDULING_MODE_OFFSET )
+#define BCR_BROADCOM_SWITCH_PORT_ADDRESS                        ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_BROADCOM_SWITCH_PORT_OFFSET )
+#define BCR_DOWNSTREAM_RATE_SHAPER_TIMER_ADDRESS                ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_DS_RATE_SHAPER_TIMER_OFFSET )
+#define BCR_US_PADDING_MAX_SIZE_ADDRESS                         ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_US_PADDING_MAX_SIZE_OFFSET )
+#define BCR_US_PADDING_CPU_MAX_SIZE_ADDRESS                     ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_US_PADDING_CPU_MAX_SIZE_OFFSET )
+#define BCR_MIRORRING_MODE_ADDRESS                              ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_MIRRORING_PORT_OFFSET )
+#define BCR_US_RATE_CONTROLLER_TIMER_ADDRESS                    ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_US_RATE_CONTROLLER_TIMER_OFFSET )
+#define BCR_US_RATE_LIMIT_SUSTAIN_BUDGET_LIMIT_ADDRESS          ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_US_RATE_LIMIT_SUSTAIN_BUDGET_LIMIT_OFFSET )
+#define BCR_1ST_EGRESS_ETHER_TYPE_ADDRESS                       ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_EGRESS_ETHER_TYPE_1_OFFSET )
+#define BCR_2ND_EGRESS_ETHER_TYPE_ADDRESS                       ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_EGRESS_ETHER_TYPE_2_OFFSET )
+#define BCR_3RD_EGRESS_ETHER_TYPE_ADDRESS                       ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_EGRESS_ETHER_TYPE_3_OFFSET )
+
+/* the following are configured in rdd.. mostly in rdd_tm, not sure if they are used for 63138/63148/4908 */
+#define BCR_DS_CONNECTION_MISS_ACTION_FILTER_ADDRESS            ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_DS_CONNECTION_MISS_ACTION_OFFSET )
+#define BCR_PCI_FLOW_CACHE_MODE_ADDRESS                         ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_US_PCI_FLOW_CACHE_ENABLE_OFFSET )
+#define BCR_INGRESS_GLOBAL_CONFIG_ADDRESS                       ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_GLOBAL_INGRESS_CONFIG_OFFSET )
+#define BCR_LS_DROP_PRECEDENCE_ELIGIBILITY_VECTOR_ADDRESS       ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_PCI_LS_DP_ELIGIBILITY_VECTOR_OFFSET )
+#define BCR_DS_INGRESS_POLICERS_MODE_ADDRESS                    ( SYSTEM_CONFIGURATION_ADDRESS + SYSTEM_CONFIGURATION_DS_INGRESS_POLICERS_MODE_OFFSET )
+
+
+#define PROFILING_BUFFER_MAIN_RUNNER_ADDRESS                        INGRESS_HANDLER_BUFFER_ADDRESS
+
+#define EMAC_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS                   EMAC_ABSOLUTE_TX_BBH_COUNTER_ADDRESS
+
+#define TCONT_NUMBER_OF_RATE_CONTROLLERS                            32
+
+#define CPU_RX_NUMBER_OF_QUEUES                                     15 /* 8 for cpu_host + 7 for cpu_wlan0 */
+
+#define DDR_QUEUE_CHUNK_SIZE                                        4
+
+#define UPSTREAM_RATE_LIMITER_ID                                    8
+
+#define TIMER_SCHEDULER_TASK_PERIOD                                     1000
+#define BL_LILAC_RDD_US_RATE_CONTROL_TIMER_INTERVAL                     4000
+#define UPSTREAM_INGRESS_RATE_LIMITER_BUDGET_ALLOCATOR_TIMER_INTERVAL   1000
+#define POLICER_TIMER_PERIOD                                            4000
+#define POLICER_EXPONENT                                                5
+#define EMAC_RATE_LIMITER_TIMER_PERIOD                                  1000
+#define EMAC_RATE_LIMITER_EXPONENT                                      3
+#define SERVICE_QUEUE_RATE_LIMITER_TIMER_PERIOD                         4000
+#define UPSTREAM_RATE_LIMITER_TIMER_PERIOD                              4000
+#define UPSTREAM_RATE_LIMITER_EXPONENT                                  5
+#define UPSTREAM_QUASI_POLICER_TIMER_PERIOD                             1000
+#define UPSTREAM_QUASI_POLICER_EXPONENT                                 3
+#define RDD_IPV6_HEADER_SIZE                                            40
+#define DDR_PACKET_PAYLOAD_OFFSET                                       18
+#define INTERRUPT_COALESCING_TIMER_PERIOD                               100
+#define TIMER_7_TIMER_PERIOD                                            400 /* usec */
+#define TIMER_7_TIMER_HZ                                                ( 1000000 / TIMER_7_TIMER_PERIOD ) /* sec */
+#define SPDSVC_ETH_IFG                                                  20 /* bytes */
+#define SPDSVC_ETH_CRC_LEN                                              4  /* bytes */
+#define SPDSVC_ETH_OVERHEAD                                             (SPDSVC_ETH_CRC_LEN + SPDSVC_ETH_IFG) /* bytes */
+                                                                        /* Ethernet packet + 2 VLAN Tags + PPPoE + Overhead */
+#define SPDSVC_BUCKET_SIZE_MIN                                          (1514 + 8 + 8 + SPDSVC_ETH_OVERHEAD) /* bytes */
+#define FREE_SKB_INDEX_TIMER_PERIOD                                     65000
+
+/* timer schedular primitive ids */
+#define CPU_RX_METER_BUDGET_ALLOCATE_CODE_ID                        0 /* fast a + fast b */
+#define UPSTREAM_RATE_LIMITER_BUDGET_ALLOCATE_CODE_ID               1 /* fast b */
+#define UPSTREAM_INGRESS_RATE_LIMITER_BUDGET_ALLOCATE_CODE_ID       2 /* pico b */
+#define UPSTREAM_QUASI_BUDGET_ALLOCATE_CODE_ID                      3 /* pico b */
+#define DOWNSTREAM_RATE_LIMITER_BUDGET_ALLOCATE_CODE_ID             4 /* pico a */
+#define FREE_SKB_INDEX_ALLOCATE_CODE_ID                             5 /* fast a+b, pico a+b */
+#define DOWNSTREAM_DHD_TX_POST_CLOSE_AGGREGATION_CODE_ID            6 /* fast a */
+#define DOWNSTREAM_SERVICE_QUEUES_RATE_LIMITER_BUDGET_ALLOCATE_CODE_ID   7 /* pico a */
+
+#define MAC_UNKNOWN_DA_FORWARDING_FILTER_DISABLED                   0xFFFFFFFF
+#define MAC_UNKNOWN_DA_FORWARDING_POLICER_ENABLE_BIT_OFFSET         29
+
+#define WAN_FILTERS_AND_CLASSIFICATON_R8_CPU_INDICATION_OFFSET      15
+#define WAN_FILTERS_AND_CLASSIFICATON_R8_ETHWAN2_INDICATION_OFFSET  14
+
+#define DS_GLOBAL_CFG_FLOW_CACHE_MODE_BIT_OFFSET                    0
+#define US_GLOBAL_CFG_FLOW_CACHE_MODE_BIT_OFFSET                    0
+#define DS_GLOBAL_CFG_BRIDGE_FLOW_CACHE_MODE_BIT_OFFSET             1
+#define US_GLOBAL_CFG_BRIDGE_FLOW_CACHE_MODE_BIT_OFFSET             1
+#define DS_GLOBAL_CFG_BROADCOM_SWITCH_MODE_BIT_OFFSET               2
+#define US_GLOBAL_CFG_BROADCOM_SWITCH_MODE_BIT_OFFSET               2
+#define DS_GLOBAL_CFG_BROADCOM_SWITCH_PHYSICAL_PORT_BIT_OFFSET      3
+#define US_GLOBAL_CFG_EPON_MODE_BIT_OFFSET                          4
+#define DS_GLOBAL_CFG_CHIP_REVISION_OFFSET                          4
+#define GLOBAL_CFG_MIRRORING_MODE_BIT_OFFSET                        5
+#define US_GLOBAL_CFG_CHIP_REVISION_OFFSET                          6
+#define US_GLOBAL_CFG_SPDSVC_CONTEXT_BIT_OFFSET                     7
+#define DS_GLOBAL_CFG_SPDSVC_CONTEXT_BIT_OFFSET                     7
+#ifdef RUNNER_A
+#define GLOBAL_CFG_CHIP_REVISION_OFFSET                             DS_GLOBAL_CFG_CHIP_REVISION_OFFSET
+#else
+#define GLOBAL_CFG_CHIP_REVISION_OFFSET                             US_GLOBAL_CFG_CHIP_REVISION_OFFSET
+#endif
+
+#ifdef RUNNER_A
+#define FW_MAC_ADDRS_COUNT_ADDRESS                               DS_FW_MAC_ADDRS_COUNT_ADDRESS
+#define FW_MAC_ADDRS_ADDRESS                                     DS_FW_MAC_ADDRS_ADDRESS
+#else
+#define FW_MAC_ADDRS_COUNT_ADDRESS                               US_FW_MAC_ADDRS_COUNT_ADDRESS
+#define FW_MAC_ADDRS_ADDRESS                                     US_FW_MAC_ADDRS_ADDRESS
+#endif
+
+/*  downstream global ingress configuration vector */
+#define GLOBAL_INGRESS_CONFIG_MIRRORING                             0
+#define GLOBAL_INGRESS_CONFIG_DS_LITE                               1
+#define GLOBAL_INGRESS_CONFIG_FULL_FLOW_CACHE_MODE                  2
+#define GLOBAL_INGRESS_CONFIG_IP_MULTICAST_FC_ACCELERATION          3
+#define GLOBAL_INGRESS_CONFIG_NON_IP_FC_ACCELRATION                 4
+
+#define THREAD_WAKEUP_REQUEST(x)                                    (((x) << 4) + 1)
+#define CPU_TX_DESCRIPTOR_ADDRESS_MASK                              0xFF80
+
+/* Main A */
+#define CPU_TX_FAST_THREAD_NUMBER                                   0
+#define CPU_RX_THREAD_NUMBER                                        1
+#define TIMER_SCHEDULER_MAIN_THREAD_NUMBER                          4
+#define POLICER_BUDGET_ALLOCATOR_THREAD_NUMBER                      5
+#if defined(DSL_63138) || defined(DSL_63148)
+#define WAN_DIRECT_THREAD_NUMBER                                    7
+#endif
+#define WAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER               8
+#define WAN_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER                9
+#define ETHWAN2_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER            10
+#define DOWNSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER                  11
+#define DOWNSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER                  12
+#define DOWNSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER                  13
+#define DOWNSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER                  14
+#define DHD_TX_COMPLETE_FAST_A_THREAD_NUMBER                        16
+#define DHD1_TX_COMPLETE_FAST_A_THREAD_NUMBER                       17
+#define DHD2_TX_COMPLETE_FAST_A_THREAD_NUMBER                       18
+#define DHD_TX_POST_FAST_A_THREAD_NUMBER                            19
+#if defined(DSL_63138) || defined(DSL_63148)
+#define CPU_DS_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER             25
+#endif
+#define DOWNSTREAM_MULTICAST_THREAD_NUMBER                          28
+#define FREE_SKB_INDEX_FAST_THREAD_NUMBER                           29
+#define IPSEC_DOWNSTREAM_THREAD_NUMBER                              30
+
+/* Pico A */
+#define CPU_TX_PICO_THREAD_NUMBER                                   32
+#define GSO_PICO_THREAD_NUMBER                                      33
+#define TIMER_SCHEDULER_PICO_A_THREAD_NUMBER                        34
+#if defined(WL4908)
+#define DS_RX_BUFFER_COPY_THREAD_NUMBER                             35 
+#endif
+#define WLAN_MCAST_THREAD_NUMBER                                    36
+#define DOWNSTREAM_LAN_ENQUEUE_THREAD_NUMBER                        37
+#define DS_TIMER_7_THREAD_NUMBER                                    38
+#define CPU_RX_INTERRUPT_COALESCING_THREAD_NUMBER                   39
+#define FREE_SKB_INDEX_PICO_A_THREAD_NUMBER                         40
+#define LOCAL_SWITCHING_LAN_ENQUEUE_THREAD_NUMBER                   41
+#define ETH_TX_THREAD_NUMBER                                        42
+#define SERVICE_QUEUE_ENQUEUE_THREAD_NUMBER                         44
+#define SERVICE_QUEUE_DEQUEUE_THREAD_NUMBER                         45
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_THREAD_NUMBER              47
+
+/* Main B */
+//efine CPU_TX_FAST_THREAD_NUMBER                                   0
+//efine CPU_RX_THREAD_NUMBER                                        1
+#define RATE_CONTROLLER_BUDGET_ALLOCATOR_THREAD_NUMBER              3
+//efine TIMER_SCHEDULER_MAIN_THREAD_NUMBER                          4
+//efine POLICER_BUDGET_ALLOCATOR_THREAD_NUMBER                      5
+#define WAN1_TX_THREAD_NUMBER                                       6
+#if defined(DSL_63138) || defined(DSL_63148)
+#define WAN_TX_THREAD_NUMBER                                        7
+#endif
+#define DHD_TX_POST_FAST_B_THREAD_NUMBER                            8
+#if defined(WL4908)
+#define US_RX_BUFFER_COPY_THREAD_NUMBER                             9
+#define US_RX_BUFFER_COPY1_THREAD_NUMBER                            10
+#define US_RX_BUFFER_COPY2_THREAD_NUMBER                            11
+#endif
+#define WAN_ENQUEUE_THREAD_NUMBER                                   21
+#define US_TIMER_7_THREAD_NUMBER                                    27
+//#define FREE_SKB_INDEX_FAST_THREAD_NUMBER                         29
+
+/* Pico B */
+#define UPSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER                    32
+#define UPSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER                    33
+#define UPSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER                    34
+#define UPSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER                    35
+#define FREE_SKB_INDEX_PICO_B_THREAD_NUMBER                         36
+#define TIMER_SCHEDULER_PICO_B_THREAD_NUMBER                        37
+#define CPU_US_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER             38
+#if defined(DSL_63138) || defined(DSL_63148)
+#define LAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER               39
+#endif
+#define DHD_RX_THREAD_NUMBER                                        40
+#define DHD1_RX_THREAD_NUMBER                                       41
+#define DHD2_RX_THREAD_NUMBER                                       42
+#define LAN_DISPATCH_THREAD_NUMBER                                  43
+#if defined(WL4908)
+#define LAN1_DISPATCH_THREAD_NUMBER                                 44
+#define LAN2_DISPATCH_THREAD_NUMBER                                 45
+#endif
+
+/* Main A */
+#define CPU_TX_FAST_THREAD_WAKEUP_REQUEST_VALUE                         THREAD_WAKEUP_REQUEST(CPU_TX_FAST_THREAD_NUMBER)
+#define CPU_RX_THREAD_WAKEUP_REQUEST_VALUE                              THREAD_WAKEUP_REQUEST(CPU_RX_THREAD_NUMBER)
+
+#define TIMER_SCHEDULER_MAIN_THREAD_WAKEUP_REQUEST_VALUE                THREAD_WAKEUP_REQUEST(TIMER_SCHEDULER_MAIN_THREAD_NUMBER)
+#define POLICER_BUDGET_ALLOCATOR_THREAD_WAKEUP_REQUEST_VALUE            THREAD_WAKEUP_REQUEST(POLICER_BUDGET_ALLOCATOR_THREAD_NUMBER)
+#define WAN_DIRECT_THREAD_WAKEUP_REQUEST_VALUE                          THREAD_WAKEUP_REQUEST(WAN_DIRECT_THREAD_NUMBER)
+#define WAN1_FILTERS_AND_CLASSIFICATION_THREAD_WAKEUP_REQUEST_VALUE     THREAD_WAKEUP_REQUEST(WAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER)
+#define WAN_FILTERS_AND_CLASSIFICATION_THREAD_WAKEUP_REQUEST_VALUE      THREAD_WAKEUP_REQUEST(WAN_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER)
+#define ETHWAN2_FILTERS_AND_CLASSIFICATION_THREAD_WAKEUP_REQUEST_VALUE  THREAD_WAKEUP_REQUEST(ETHWAN2_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER)
+#define DOWNSTREAM_FLOW_CACHE_SLAVE0_THREAD_WAKEUP_REQUEST_VALUE        THREAD_WAKEUP_REQUEST(DOWNSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER)
+#define DOWNSTREAM_FLOW_CACHE_SLAVE1_THREAD_WAKEUP_REQUEST_VALUE        THREAD_WAKEUP_REQUEST(DOWNSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER)
+#define DOWNSTREAM_FLOW_CACHE_SLAVE2_THREAD_WAKEUP_REQUEST_VALUE        THREAD_WAKEUP_REQUEST(DOWNSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER)
+#define DOWNSTREAM_FLOW_CACHE_SLAVE3_THREAD_WAKEUP_REQUEST_VALUE        THREAD_WAKEUP_REQUEST(DOWNSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER)
+#define DHD_TX_COMPLETE_FAST_A_THREAD_WAKEUP_REQUEST_VALUE              THREAD_WAKEUP_REQUEST(DHD_TX_COMPLETE_FAST_A_THREAD_NUMBER)
+#define DHD1_TX_COMPLETE_FAST_A_THREAD_WAKEUP_REQUEST_VALUE             THREAD_WAKEUP_REQUEST(DHD1_TX_COMPLETE_FAST_A_THREAD_NUMBER)
+#define DHD2_TX_COMPLETE_FAST_A_THREAD_WAKEUP_REQUEST_VALUE             THREAD_WAKEUP_REQUEST(DHD2_TX_COMPLETE_FAST_A_THREAD_NUMBER)
+#define DHD_TX_POST_FAST_A_THREAD_WAKEUP_REQUEST_VALUE                  THREAD_WAKEUP_REQUEST(DHD_TX_POST_FAST_A_THREAD_NUMBER)
+#if defined(DSL_63138) || defined(DSL_63148)
+#define CPU_DS_CLASSIFICATION_THREAD_WAKEUP_REQUEST_VALUE               THREAD_WAKEUP_REQUEST(CPU_DS_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER)
+#endif
+#define DOWNSTREAM_MULTICAST_THREAD_WAKEUP_REQUEST_VALUE                THREAD_WAKEUP_REQUEST(DOWNSTREAM_MULTICAST_THREAD_NUMBER)
+#define FREE_SKB_INDEX_FAST_THREAD_WAKEUP_REQUEST_VALUE                 THREAD_WAKEUP_REQUEST(FREE_SKB_INDEX_FAST_THREAD_NUMBER)
+#define IPSEC_DOWNSTREAM_THREAD_WAKEUP_REQUEST_VALUE                    THREAD_WAKEUP_REQUEST(IPSEC_DOWNSTREAM_THREAD_NUMBER)
+
+/* Pico A */
+#define CPU_TX_PICO_THREAD_WAKEUP_REQUEST_VALUE                         THREAD_WAKEUP_REQUEST(CPU_TX_PICO_THREAD_NUMBER)
+#define GSO_PICO_THREAD_WAKEUP_REQUEST_VALUE                            THREAD_WAKEUP_REQUEST(GSO_PICO_THREAD_NUMBER)
+#define TIMER_SCHEDULER_PICO_A_THREAD_WAKEUP_REQUEST_VALUE              THREAD_WAKEUP_REQUEST(TIMER_SCHEDULER_PICO_A_THREAD_NUMBER)
+#if defined(WL4908)
+#define DS_RX_BUFFER_COPY_THREAD_WAKEUP_REQUEST_VALUE                   THREAD_WAKEUP_REQUEST(DS_RX_BUFFER_COPY_THREAD_NUMBER)
+#endif
+#define WLAN_MCAST_THREAD_WAKEUP_REQUEST_VALUE                          THREAD_WAKEUP_REQUEST(WLAN_MCAST_THREAD_NUMBER)
+#define DOWNSTREAM_LAN_ENQUEUE_THREAD_WAKEUP_REQUEST_VALUE              THREAD_WAKEUP_REQUEST(DOWNSTREAM_LAN_ENQUEUE_THREAD_NUMBER)
+#define DS_SPDSVC_THREAD_WAKEUP_REQUEST_VALUE                           THREAD_WAKEUP_REQUEST(DS_SPDSVC_THREAD_NUMBER)
+#define CPU_RX_INTERRUPT_COALESCING_THREAD_WAKEUP_REQUEST_VALUE         THREAD_WAKEUP_REQUEST(CPU_RX_INTERRUPT_COALESCING_THREAD_NUMBER)
+#define FREE_SKB_INDEX_PICO_A_THREAD_WAKEUP_REQUEST_VALUE               THREAD_WAKEUP_REQUEST(FREE_SKB_INDEX_PICO_A_THREAD_NUMBER)
+#define LOCAL_SWITCHING_LAN_ENQUEUE_THREAD_WAKEUP_REQUEST_VALUE         THREAD_WAKEUP_REQUEST(LOCAL_SWITCHING_LAN_ENQUEUE_THREAD_NUMBER)
+#define ETH_TX_THREAD_WAKEUP_REQUEST_VALUE                              THREAD_WAKEUP_REQUEST(ETH_TX_THREAD_NUMBER)
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_THREAD_WAKEUP_REQUEST_VALUE    THREAD_WAKEUP_REQUEST(DOWNSTREAM_MULTICAST_LAN_ENQUEUE_THREAD_NUMBER)
+#define SERVICE_QUEUE_ENQUEUE_THREAD_WAKEUP_REQUEST_VALUE               THREAD_WAKEUP_REQUEST(SERVICE_QUEUE_ENQUEUE_THREAD_NUMBER)
+#define SERVICE_QUEUE_DEQUEUE_WAKEUP_THREAD_REQUEST_VALUE               THREAD_WAKEUP_REQUEST(SERVICE_QUEUE_DEQUEUE_THREAD_NUMBER)
+
+/* Main B */
+//efine CPU_TX_FAST_THREAD_WAKEUP_REQUEST_VALUE                         THREAD_WAKEUP_REQUEST(CPU_TX_FAST_THREAD_NUMBER)
+//efine CPU_RX_THREAD_WAKEUP_REQUEST_VALUE                              THREAD_WAKEUP_REQUEST(CPU_RX_THREAD_NUMBER)
+#define RATE_CONTROLLER_BUDGET_ALLOCATOR_THREAD_WAKEUP_REQUEST_VALUE    THREAD_WAKEUP_REQUEST(RATE_CONTROLLER_BUDGET_ALLOCATOR_THREAD_NUMBER)
+//efine TIMER_SCHEDULER_MAIN_THREAD_WAKEUP_REQUEST_VALUE                THREAD_WAKEUP_REQUEST(TIMER_SCHEDULER_MAIN_THREAD_NUMBER)
+//efine POLICER_BUDGET_ALLOCATOR_THREAD_WAKEUP_REQUEST_VALUE            THREAD_WAKEUP_REQUEST(POLICER_BUDGET_ALLOCATOR_THREAD_NUMBER)
+#define WAN1_TX_THREAD_WAKEUP_REQUEST_VALUE                             THREAD_WAKEUP_REQUEST(WAN1_TX_THREAD_NUMBER)
+#if defined(DSL_63138) || defined(DSL_63148)
+#define WAN_TX_THREAD_WAKEUP_REQUEST_VALUE                              THREAD_WAKEUP_REQUEST(WAN_TX_THREAD_NUMBER)
+#endif
+#define DHD_TX_POST_FAST_B_THREAD_WAKEUP_REQUEST_VALUE                  THREAD_WAKEUP_REQUEST(DHD_TX_POST_FAST_B_THREAD_NUMBER)
+#if defined(WL4908)
+#define US_RX_BUFFER_COPY_THREAD_WAKEUP_REQUEST_VALUE                   THREAD_WAKEUP_REQUEST(US_RX_BUFFER_COPY_THREAD_NUMBER)
+#define US_RX_BUFFER_COPY1_THREAD_WAKEUP_REQUEST_VALUE                  THREAD_WAKEUP_REQUEST(US_RX_BUFFER_COPY1_THREAD_NUMBER)
+#define US_RX_BUFFER_COPY2_THREAD_WAKEUP_REQUEST_VALUE                  THREAD_WAKEUP_REQUEST(US_RX_BUFFER_COPY2_THREAD_NUMBER)
+#endif
+#define WAN_ENQUEUE_THREAD_WAKEUP_REQUEST_VALUE                         THREAD_WAKEUP_REQUEST(WAN_ENQUEUE_THREAD_NUMBER)
+#define US_SPDSVC_THREAD_WAKEUP_REQUEST_VALUE                           THREAD_WAKEUP_REQUEST(US_SPDSVC_THREAD_NUMBER)
+//efine FREE_SKB_INDEX_FAST_THREAD_WAKEUP_REQUEST_VALUE                 THREAD_WAKEUP_REQUEST(FREE_SKB_INDEX_FAST_THREAD_NUMBER)
+
+/* Pico B */
+#define UPSTREAM_FLOW_CACHE_SLAVE0_THREAD_WAKEUP_REQUEST_VALUE          THREAD_WAKEUP_REQUEST(UPSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER)
+#define UPSTREAM_FLOW_CACHE_SLAVE1_THREAD_WAKEUP_REQUEST_VALUE          THREAD_WAKEUP_REQUEST(UPSTREAM_FLOW_CACHE_SLAVE1_THREAD_NUMBER)
+#define UPSTREAM_FLOW_CACHE_SLAVE2_THREAD_WAKEUP_REQUEST_VALUE          THREAD_WAKEUP_REQUEST(UPSTREAM_FLOW_CACHE_SLAVE2_THREAD_NUMBER)
+#define UPSTREAM_FLOW_CACHE_SLAVE3_THREAD_WAKEUP_REQUEST_VALUE          THREAD_WAKEUP_REQUEST(UPSTREAM_FLOW_CACHE_SLAVE3_THREAD_NUMBER)
+#define FREE_SKB_INDEX_PICO_B_THREAD_WAKEUP_REQUEST_VALUE               THREAD_WAKEUP_REQUEST(FREE_SKB_INDEX_PICO_B_THREAD_NUMBER)
+#define TIMER_SCHEDULER_PICO_B_THREAD_WAKEUP_REQUEST_VALUE              THREAD_WAKEUP_REQUEST(TIMER_SCHEDULER_PICO_B_THREAD_NUMBER)
+#define CPU_US_CLASSIFICATION_THREAD_WAKEUP_REQUEST_VALUE               THREAD_WAKEUP_REQUEST(CPU_US_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER)
+#if defined(DSL_63138) || defined(DSL_63148)
+#define LAN1_FILTERS_AND_CLASSIFICATION_THREAD_WAKEUP_REQUEST_VALUE     THREAD_WAKEUP_REQUEST(LAN1_FILTERS_AND_CLASSIFICATION_THREAD_NUMBER)
+#endif
+#define DHD_RX_THREAD_WAKEUP_REQUEST_VALUE                              THREAD_WAKEUP_REQUEST(DHD_RX_THREAD_NUMBER)
+#define DHD1_RX_THREAD_WAKEUP_REQUEST_VALUE                             THREAD_WAKEUP_REQUEST(DHD1_RX_THREAD_NUMBER)
+#define DHD2_RX_THREAD_WAKEUP_REQUEST_VALUE                             THREAD_WAKEUP_REQUEST(DHD2_RX_THREAD_NUMBER)
+#define LAN_DISPATCH_THREAD_WAKEUP_REQUEST_VALUE                        THREAD_WAKEUP_REQUEST(LAN_DISPATCH_THREAD_NUMBER)
+#if defined(WL4908)
+#define LAN1_DISPATCH_THREAD_WAKEUP_REQUEST_VALUE                       THREAD_WAKEUP_REQUEST(LAN1_DISPATCH_THREAD_NUMBER)
+#define LAN2_DISPATCH_THREAD_WAKEUP_REQUEST_VALUE                       THREAD_WAKEUP_REQUEST(LAN2_DISPATCH_THREAD_NUMBER)
+#endif
+
+
+#define LAN_FILTERS_LAN_TYPE_CPU_BIT_OFFSET                     31
+#define LAN_FILTERS_LAN_TYPE_DIRECT_TO_CPU_BIT_OFFSET           30
+
+#define SELF_FIRMWARE_WAKEUP_REQUEST_BIT                        2
+
+#define DOWNSTREAM_RX_PACKETS_GROUP                             0
+#define DOWNSTREAM_RX_BYTES_GROUP                               16
+
+/* Each Runner counter group has 16 32bit counters or 32 16bit counters.
+ * There are: 1 eth wan1 + 7 lans = 8 ports --> 64 queues total
+ * Supports 4 counters per queue: tx_bytes, tx_packets, dropped_bytes, dropped_packets
+ * Needs:
+ *     64 32bit counters for tx_bytes --> 4 Runner counter groups: 0, 1, 2, 3
+ *     64 32bit counters for tx_packets --> 4 Runner counter groups: 4, 5, 6, 7
+ *     64 32bit counters for dropped_bytes --> 4 Runner counter groups: 8, 9, 10, 11
+ *     64 16bit counters for dropped_packets --> 2 Runner counter groups: 12, 13
+ * Counter allocation in each counter type is 8 WAN queue counters followed by 56 LAN queue counters. 
+ */
+#define WAN_TX_QUEUES_BYTES_GROUP                               0
+#define WAN_TX_QUEUES_PACKETS_GROUP                             4
+#define WAN_TX_QUEUES_DROPPED_BYTES_GROUP                       8
+#define WAN_TX_QUEUES_DROPPED_PACKETS_GROUP                     12
+
+#define LAN_TX_QUEUES_BYTES_GROUP                               0
+#define LAN_TX_QUEUES_PACKETS_GROUP                             4
+#define LAN_TX_QUEUES_DROPPED_BYTES_GROUP                       8
+#define LAN_TX_QUEUES_DROPPED_PACKETS_GROUP                     12
+
+/* For DSL wan0, we need:
+ *     16 32bit counters for tx_bytes --> 1 Runner counter group: 14
+ *     16 32bit counters for tx_packets --> 1 Runner counter group: 15
+ *     16 32bit counters for dropped_bytes --> 1 Runner counter group: 16
+ *     16 16bit counters for dropped_packets --> 1 Runner counter group: 17
+ */
+#define WAN0_TX_QUEUES_BYTES_GROUP                              14
+#define WAN0_TX_QUEUES_PACKETS_GROUP                            15
+#define WAN0_TX_QUEUES_DROPPED_BYTES_GROUP                      16
+#define WAN0_TX_QUEUES_DROPPED_PACKETS_GROUP                    17
+
+/* For Path Stats, we need:
+ *     64 32bit counters for packets --> 4 Runner counter group: 20
+ *     64 32bit counters for bytes --> 4 Runner counter group: 24
+ */
+#define PATHSTAT_PACKETS_GROUP                                  20
+#define PATHSTAT_BYTES_GROUP                                    24
+
+#define DOWNSTREAM_RX_DROPPED_SUMMARY_GROUP                     32
+#define DHD_SSID_DROP_PACKET_GROUP                              37
+#define UPSTREAM_TX_PACKETS_GROUP                               40
+#define UPSTREAM_TX_BYTES_GROUP                                 56
+#define UPSTREAM_TX_CONGESTION_GROUP                            72
+#define BRIDGE_RX_BPM_CONGESTION_GROUP                          80
+#define BRIDGE_FILTERED_GROUP                                   81
+#define BRIDGE_DOWNSTREAM_TX_CONGESTION_GROUP                   82
+#define WAN_BRIDGE_PORT_GROUP                                   83
+
+/* The first 16 16bit counters of group 82 are used for LAN port tx discards.
+ * The last 8 32bit counters of group 82 are used for LAN port tx packets.
+ *
+ *    16bit counter 0 is reserved.
+ *    16bit counter 1 is for LAN0 tx discard count.
+ *    16bit counter 2 is for LAN1 tx discard count.
+ *    ....
+ *    16bit counter 7 is for LAN6 tx discard count.
+ *
+ *    32bit counter 8 is reserved.
+ *    32bit counter 9 is for LAN0 tx packet count.
+ *    32bit counter 10 is for LAN1 tx packet count.
+ *    ....
+ *    32bit counter 15 is for LAN6 tx packet count.
+ */
+#define LAN_TX_PACKETS_GROUP                                    82
+/* The last 8 32bit counters of group 83 are used for LAN port rx packets.
+ *
+ *    32bit counters 0 - 8 are reserved.
+ *    32bit counter 9 is for LAN0 rx packet count.
+ *    32bit counter 10 is for LAN1 rx packet count.
+ *    ....
+ *    32bit counter 15 is for LAN6 rx packet count.
+ */
+#define LAN_RX_PACKETS_GROUP                                    83
+#define INGRESS_RATE_LIMITER_GROUP                              84
+#define UPSTREAM_VARIOUS_PACKETS_GROUP                          86
+#define DOWNSTREAM_VARIOUS_PACKETS_GROUP                        88
+#define SERVICE_QUEUE_DROP_PACKET_GROUP                         90
+#define CPU_RX_METERS_DROPPED_PACKETS_GROUP                     91
+#define SERVICE_QUEUE_PACKET_GROUP                              92
+#define SUBNET_RX_GROUP                                         92
+#define SUBNET_RX_BYTES_GROUP                                   93
+#define SUBNET_TX_GROUP                                         94
+#define SUBNET_TX_BYTES_GROUP                                   95
+#define CPU_RX_INTERRUPT_COALESCING_GROUP                       96
+
+#define WAN_CRC_ERROR_NORMAL_COUNTER_OFFSET                     0
+#define WAN_CRC_ERROR_IPTV_COUNTER_OFFSET                       1
+#define WAN_BRIDGED_RX_VALID_SUB_GROUP_OFFSET                   1
+#define WAN_IPTV_RX_VALID_SUB_GROUP_OFFSET                      2
+#define LAN_SUBNET_COUNTER_OFFSET                               2
+#define SUBNET_DROPPED_PACKETS_SUB_GROUP_OFFSET                 20
+#define ACL_OUI_DROP_COUNTER_OFFSET                             32
+#define ACL_LAYER2_DROP_COUNTER_OFFSET                          33
+#define ACL_LAYER3_DROP_COUNTER_OFFSET                          34
+#define INGRESS_FILTER_DROP_SUB_GROUP_OFFSET                    0
+#define LAYER4_FILTER_DROP_SUB_GROUP_OFFSET                     16
+#define INVALID_LAYER2_PROTOCOL_DROP_COUNTER_OFFSET             32
+#define FIREWALL_DROP_COUNTER_OFFSET                            33
+#define DST_MAC_NON_ROUTER_COUNTER_OFFSET                       34
+#define ETHERNET_FLOW_DROP_ACTION_COUNTER_OFFSET                35
+#define EMAC_LOOPBACK_DROP_COUNTER                              36
+#define LAN_ENQUEUE_CONGESTION_COUNTER_OFFSET                   36
+#define IH_THRESHOLD_CONGESTION_COUNTER_OFFSET                  36
+#define VLAN_SWITCHING_DROP_COUNTER_OFFSET                      37
+#define SA_LOOKUP_FAILURE_DROP_COUNTER_OFFSET                   38
+#define DA_LOOKUP_FAILURE_DROP_COUNTER_OFFSET                   39
+#define SA_ACTION_DROP_COUNTER_OFFSET                           40
+#define DA_ACTION_DROP_COUNTER_OFFSET                           41
+#define FORWARDING_MATRIX_DISABLED_DROP_COUNTER_OFFSET          42
+#define CONNECTION_ACTION_DROP_COUNTER_OFFSET                   43
+#define IPTV_LAYER3_DROP_COUNTER_OFFSET                         44
+#define DOWNSTREAM_POLICERS_DROP_COUNTER_OFFSET                 45
+#define UPSTREAM_POLICERS_DROP_COUNTER_OFFSET                   45
+#define INGRESS_FILTER_IP_VALIDATIOH_GROUP_OFFSET               46
+#define IP_HEADER_ERROR_DROP_COUNTER_OFFSET                     46
+#define IP_FRAGMENT_DROP_COUNTER_OFFSET                         47
+#define TPID_DETECT_DROP_COUNTER_OFFSET                         48
+#define DUAL_STACK_LITE_CONGESTION_DROP_COUNTER_OFFSET          49
+#define INVALID_SUBNET_IP_DROP_COUNTER_OFFSET                   50
+#define EPON_DDR_QUEUES_COUNTER_OFFSET                          51
+#define DOWNSTREAM_PARALLEL_PROCESSING_NO_SLAVE_WAIT_OFFSET     52
+#define DOWNSTREAM_PARALLEL_PROCESSING_REORDER_WAIT_OFFSET      53
+#define ABSOLUTE_ADDRESS_LIST_OVERFLOW_OFFSET                   54
+#define DHD_IH_CONGESTION_OFFSET                                55 /* DHD_OFFLOAD */
+#define DHD_MALLOC_FAILED_OFFSET                                56 /* DHD_OFFLOAD */
+#define CPU_RX_METERS_DROPPED_PACKETS_UPSTREAM_OFFSET           16
+
+#define BBH_RESET_WORD_1_DESCRIPTOR_VALUE                       0xF0000000
+#define BBH_RESET_WORD_1_DESCRIPTOR_VALUE_MOD_8                 0xF0
+
+#define CPU_RX_INTCOL_TOTALPKTS_OFFSET                          0
+#define CPU_RX_INTCOL_MAXPKTS_OFFSET                            1
+#define CPU_RX_INTCOL_TIMEOUTS_OFFSET                           2
+
+#define BBH_PERIPHERAL_DSL_RX                                   0
+#define BBH_PERIPHERAL_DSL_TX                                   32
+#define BBH_PERIPHERAL_WAN_RX                                   BBH_PERIPHERAL_DSL_RX
+#define BBH_PERIPHERAL_WAN_TX                                   BBH_PERIPHERAL_DSL_TX
+#define BBH_PERIPHERAL_GPON_RX                                  0
+#define BBH_PERIPHERAL_GPON_TX                                  32
+#define BBH_PERIPHERAL_EPON_TX                                  96
+#define BBH_PERIPHERAL_CO_RUNNER                                2
+#define BBH_PERIPHERAL_BPM                                      3
+#define BBH_PERIPHERAL_SBPM                                     7
+#define BBH_PERIPHERAL_ETH0_TX                                  60
+#define BBH_PERIPHERAL_ETH0_RX                                  28
+#define BBH_PERIPHERAL_ETH1_TX                                  44
+#define BBH_PERIPHERAL_ETH1_RX                                  12
+#define BBH_PERIPHERAL_ETH2_TX                                  52
+#define BBH_PERIPHERAL_ETH2_RX                                  20
+#define BBH_PERIPHERAL_ETH3_TX                                  40
+#define BBH_PERIPHERAL_ETH3_RX                                  8
+#define BBH_PERIPHERAL_ETH4_TX                                  48
+#define BBH_PERIPHERAL_ETH4_RX                                  16
+#define BBH_PERIPHERAL_IH                                       6
+#define BBH_PERIPHERAL_MIPS_D                                   14
+
+#define SBPM_REPLY_SET_0                                        ( 0 << 7 )
+#define SBPM_REPLY_SET_1                                        ( 1 << 7 )
+#define SBPM_REPLY_SET_2                                        ( 2 << 7 )
+#define SBPM_REPLY_SET_3                                        ( 3 << 7 )
+#define SBPM_REPLY_SET_0_OFFSET                                 0
+#define SBPM_REPLY_SET_1_OFFSET                                 32
+#define SBPM_REPLY_SET_2_OFFSET                                 64
+#define SBPM_REPLY_SET_3_OFFSET                                 96
+#define SBPM_REPLY_GET_NEXT_OFFSET                              12
+
+#define WAN_SRC_PORT                                            0
+#define ETH0_SRC_PORT                                           1
+#define ETH1_SRC_PORT                                           2
+#define ETH4_SRC_PORT                                           5
+#define MIPS_C_SRC_PORT                                         6
+#define WAN_IPTV_SRC_PORT                                       7
+#define ANY_SRC_PORT                                            11 /* used by Speed Service */
+#define PCI_0_SRC_PORT                                          13 /* must match DRV_BPM_SP_SPARE_1 */
+#define SPARE_0_SRC_PORT                                        12
+#define FAST_RUNNER_A_SRC_PORT                                  14
+#define FAST_RUNNER_B_SRC_PORT                                  15
+
+#define RUNNER_CLUSTER_A_SRC_PORT                               14
+#define RUNNER_CLUSTER_B_SRC_PORT                               15
+
+#define RDD_DS_IH_PACKET_HEADROOM_OFFSET                        18
+#define RDD_US_IH_PACKET_HEADROOM_OFFSET                        18
+#define RDD_LAYER2_HEADER_MINIMUM_LENGTH                        14
+#define RDD_RUNNER_FLOW_RUNNER_A_IH_BUFFER                      14
+#define RDD_RUNNER_FLOW_RUNNER_B_IH_BUFFER                      15
+#define RDD_RUNNER_A_IH_BUFFER_BBH_OFFSET                       ((RDD_RUNNER_FLOW_RUNNER_A_IH_BUFFER * 128 + RDD_DS_IH_PACKET_HEADROOM_OFFSET) / 8)
+#define RDD_RUNNER_B_IH_BUFFER_BBH_OFFSET                       ((RDD_RUNNER_FLOW_RUNNER_B_IH_BUFFER * 128 + RDD_US_IH_PACKET_HEADROOM_OFFSET) / 8)
+#define RDD_IH_BUFFER_BBH_ADDRESS                               0x8000
+#define RDD_IH_HEADER_DESCRIPTOR_BBH_ADDRESS                    0x0
+
+/* Parallel processing */
+#define FLOW_CACHE_SLAVE0_VECTOR_MASK               1
+#define FLOW_CACHE_SLAVE1_VECTOR_MASK               2
+#define FLOW_CACHE_SLAVE2_VECTOR_MASK               4
+#define FLOW_CACHE_SLAVE3_VECTOR_MASK               8
+#define CPU_FLOW_CACHE_VECTOR_MASK                  16
+
+/* Dummy defines for software */
+#define ETH0_RX_DIRECT_DESCRIPTORS_ADDRESS          0
+#define ETH1_RX_DIRECT_DESCRIPTORS_ADDRESS          0
+#define ETH2_RX_DIRECT_DESCRIPTORS_ADDRESS          0
+#define ETH3_RX_DIRECT_DESCRIPTORS_ADDRESS          0
+#define ETH4_RX_DIRECT_DESCRIPTORS_ADDRESS          0
+
+#define ETH0_RX_DIRECT_RUNNER_A_TASK_NUMBER         0
+#define ETH1_RX_DIRECT_RUNNER_A_TASK_NUMBER         0
+#define ETH2_RX_DIRECT_RUNNER_A_TASK_NUMBER         0
+#define ETH3_RX_DIRECT_RUNNER_A_TASK_NUMBER         0
+#define ETH4_RX_DIRECT_RUNNER_A_TASK_NUMBER         0
+
+#define ETH0_RX_DIRECT_RUNNER_B_TASK_NUMBER         0
+#define ETH1_RX_DIRECT_RUNNER_B_TASK_NUMBER         0
+#define ETH2_RX_DIRECT_RUNNER_B_TASK_NUMBER         0
+#define ETH3_RX_DIRECT_RUNNER_B_TASK_NUMBER         0
+#define ETH4_RX_DIRECT_RUNNER_B_TASK_NUMBER         0
+
+#define MAC_ADDRESS_SIZE                            6
+
+/* Per chip limitation, 63138/63148 SAR can only transmit
+ * max PTM frame size of 1984 bytes including FCS (4 bytes).
+ */
+#define PTM_MAX_TX_FRAME_LEN_FCS    1984
+
+/* UNIMAC message to enable/disable EEE LPI mode.*/
+#define BBTX_EEE_MODE_CONFIG_MESSAGE                6
+
+#ifdef RUNNER_A
+#define PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS            DS_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS
+#define FLOW_CACHE_SLAVE0_THREAD_NUMBER                     DOWNSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER
+#define PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS    DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS
+#else
+#define PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS            US_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS
+#define FLOW_CACHE_SLAVE0_THREAD_NUMBER                     UPSTREAM_FLOW_CACHE_SLAVE0_THREAD_NUMBER
+#define PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS    US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS
+#endif
+
+#ifdef RUNNER_A
+#define SPDSVC_CONTEXT_TABLE_ADDRESS                        DS_SPDSVC_CONTEXT_TABLE_ADDRESS
+#define SPDSVC_WAKEUP_REQUEST_VALUE                         DS_SPDSVC_WAKEUP_REQUEST_VALUE
+#else
+#define SPDSVC_CONTEXT_TABLE_ADDRESS                        US_SPDSVC_CONTEXT_TABLE_ADDRESS
+#define SPDSVC_WAKEUP_REQUEST_VALUE                         US_SPDSVC_WAKEUP_REQUEST_VALUE
+#endif
+
+#ifdef RUNNER_A
+#define SPDSVC_SET_CONTEXT() \
+    insert  ds_global_cfg  R1  DS_GLOBAL_CFG_SPDSVC_CONTEXT_BIT_OFFSET  d.1
+#define SPDSVC_RESET_CONTEXT() \
+    insert  ds_global_cfg  R0  DS_GLOBAL_CFG_SPDSVC_CONTEXT_BIT_OFFSET  d.1
+#else /* RUNNER_B */
+#define SPDSVC_SET_CONTEXT() \
+    insert  us_global_cfg  R1  US_GLOBAL_CFG_SPDSVC_CONTEXT_BIT_OFFSET  d.1
+#define SPDSVC_RESET_CONTEXT() \
+    insert  us_global_cfg  R0  US_GLOBAL_CFG_SPDSVC_CONTEXT_BIT_OFFSET  d.1
+#endif
+
+/* DHD */
+#define DHD_DOORBELL_IRQ_NUM                        2
+#define DHD_MSG_TYPE_TX_POST                        0xF
+#define DHD_MSG_TYPE_RX_POST                        0x11
+#define DHD_TX_POST_FLOW_RING_SIZE                  2560
+#define DHD_TX_POST_FLOW_RING_DESCRIPTOR_SIZE       48
+#define DHD_TX_POST_FLOW_RING_SIZE_IN_BYTES         ( DHD_TX_POST_FLOW_RING_SIZE * DHD_TX_POST_FLOW_RING_DESCRIPTOR_SIZE )
+#define DHD_RX_POST_FLOW_RING_SIZE                  1024
+#define DHD_TX_COMPLETE_FLOW_RING_SIZE              1024
+#define DHD_RX_COMPLETE_FLOW_RING_SIZE              1024
+#define DHD_TX_POST_BUFFERS_THRESHOLD               2048
+#define DHD_DATA_LEN                                2048
+#define DHD_RX_POST_RING_NUMBER                     1  
+#define DHD_TX_COMPLETE_RING_NUMBER                 3
+#define DHD_RX_COMPLETE_RING_NUMBER                 4
+
+#define DHD_RADIO_OFFSET_COMMON_A(index)            (DHD_RADIO_INSTANCE_COMMON_A_DATA_ADDRESS + (index * sizeof(RDD_DHD_RADIO_INSTANCE_COMMON_A_ENTRY_DTS)))
+#define DHD_RADIO_OFFSET_COMMON_B(index)            (DHD_RADIO_INSTANCE_COMMON_B_DATA_ADDRESS + (index * sizeof(RDD_DHD_RADIO_INSTANCE_COMMON_B_ENTRY_DTS)))
+
+#define UCAST_DROP_COMMAND_LIST_STRING_SIZE             16
+#define UCAST_DROP_COMMAND_LIST_TIMESTAMP_SIZE          8
+#define UCAST_DROP_COMMAND_LIST_TOTAL_SIZE              ( UCAST_DROP_COMMAND_LIST_STRING_SIZE + UCAST_DROP_COMMAND_LIST_TIMESTAMP_SIZE )
+
+#define WLAN_MCAST_EGRESS_PORT_INDEX   7
+
+/* IPsec operation errors */
+#define IPSEC_OPERATION_OK         0
+#define IPSEC_ICV_CHECK_FAIL       1
+
+/* DS queues with a filling level less than this threshold can allocate Packet Descriptor using the guaranteed PD Pool budget */
+#define DS_FREE_PACKET_DESCRIPTOR_POOL_GUARANTEED_QUEUE_THRESHOLD 8
+
+/* The guaranteed PD Pool budget is sized in function of the number of configured DS queues. To avoid unexpected behavior in
+ * corner cases, e.g. a transient condition when all DS queues are unconfigured, the guaranteed PD Pool budget is clamped
+ * to at least this minimum guaranteed pool size value.
+ */
+#define DS_FREE_PACKET_DESCRIPTOR_POOL_MIN_GUARANTEED_POOL_SIZE  64
+
+/* US queues with a filling level less than this threshold can allocate Packet Descriptor using the guaranteed PD Pool budget */
+#define US_FREE_PACKET_DESCRIPTOR_POOL_GUARANTEED_QUEUE_THRESHOLD 72
+
+/* The guaranteed PD Pool budget is sized in function of the number of configured US queues. To avoid unexpected behavior in
+ * corner cases, e.g. a transient condition when all US queues are unconfigured, the guaranteed PD Pool budget is clamped
+ * to at least this minimum guaranteed pool size value.
+ * Let's say a typical configuration of - 8 queues in US. Each queue with 72 PDs guaranteed. (8*72 = 576 PDS)
+ * NG PDs -> 3072-576 = 2496 PDs.
+ */
+#define US_FREE_PACKET_DESCRIPTOR_POOL_MIN_GUARANTEED_POOL_SIZE  (US_FREE_PACKET_DESCRIPTOR_POOL_GUARANTEED_QUEUE_THRESHOLD*8)
+
+#define INVALID_COUNTER_ID                                       0
+
+#define IPPROTO_IDX_UNDEF      0 /*    Undefined, may be used for L2      */
+
+#define IPPROTO_IDX_OTHER      1 /*  0 IPv6 ext: Hop-by-Hop Option Header 
+                                    61 Any host internel proto            
+                                   114 Any Zero HOP                      
+                                   141 - 252 unassigned range          
+                                   253 - 254 Reserved for experimentation
+                                   255       Raw IP Packets               */
+#define IPPROTO_IDX_IPV6       2 /* 41 IPv6-in-IPv4 tunneling             */
+#define IPPROTO_IDX_GRE        3 /* 47 Cisco GRE tunnels (rfc 1701,1702)  */
+#define IPPROTO_IDX_IPIP       4 /*  4 IPIP tunnels e.g. 4in6             */
+#define IPPROTO_IDX_TCP_ACK    5 /*    TCP pure acknowledgment            */
+#define IPPROTO_IDX_TCP        6 /*  6 Transmission Control Protocol      */
+#define IPPROTO_IDX_UDP        7 /* 17 User Datagram Protocol             */
+
+#define TUPLE_PROTO_PROTOCOL_F_OFFSET                   4
+#define TUPLE_PROTO_PROTOCOL_F_WIDTH                    3
+#define TUPLE_PROTO_PROTOCOL_F_MASK                     0x07
+#define TUPLE_PROTO_PROTOCOL_OFFSET                     0
+#define TUPLE_PROTO_LOOKUP_PORT_F_OFFSET                0
+#define TUPLE_PROTO_LOOKUP_PORT_F_WIDTH                 4
+#define TUPLE_PROTO_LOOKUP_PORT_F_MASK                  0x0F
+#define TUPLE_PROTO_LOOKUP_PORT_OFFSET                  0
+
+/* DEBUG TRACE */
+
+// #define DEBUG_TRACE_ENABLE
+
+#if defined(RUNNER_A) && defined(RUNNER_MAIN)
+#define GLBREG R5
+#define BASEADDR h.7a
+#define MASKINST insert  GLBREG  R1  d.25  d.2
+#elif defined(RUNNER_A) && defined(RUNNER_PICO)
+#define GLBREG R6
+#define BASEADDR h.7c
+#define MASKINST insert  GLBREG  R0  d.25  d.1
+#elif defined(RUNNER_B) && defined(RUNNER_MAIN)
+#define GLBREG R6
+#define BASEADDR h.ea
+#define MASKINST insert  GLBREG  R1  d.25  d.2
+#elif defined(RUNNER_B) && defined(RUNNER_PICO)
+#define GLBREG R6
+#define BASEADDR h.ec
+#define MASKINST insert  GLBREG  R0  d.25  d.1
+#endif
+
+#if !defined(DEBUG_TRACE_ENABLE)
+
+#define DEBUG_ID_TRACE24( id, trace_word )
+#define DEBUG_ID_TRACE24_C( id, trace_word)
+#define DEBUG_ID_TRACE24_CS( id, trace_word)
+#define DEBUG_TRACE32( trace_word )
+#define DEBUG_TRACE32_C( trace_word )
+#define DEBUG_TRACE32_CS( trace_word )
+#define DEBUG_ID_TRACE16_CS( id, trace_word_macro )
+#define DEBUG_TRACE_C_ON()
+#define DEBUG_TRACE_C_OFF()
+#define DEBUG_TRACE_C_OFF_PERM()
+#define DEBUG_TRACE_C_ON_PERM()
+#define DEBUG_TRACE_MEM_C( mem, numbytes )
+#define DEBUG_TRACE_C_TRIG_DELAYED_OFF_PERM()
+#define DEBUG_TRACE_C_DO_DELAYED_OFF_PERM()
+
+#else /* DEBUG_TRACE */
+
+#define DEBUG_ID_TRACE24( id, trace_word ) ;\
+    alu     GLBREG  GLBREG OR BASEADDR <<24 ;\
+    alu     GLBREG  GLBREG AND~ h.ff ;\
+    alu     GLBREG  GLBREG OR id ;\
+    nop ;\
+    stc32   trace_word  GLBREG  high ;\
+    stc8    GLBREG  GLBREG  high ;\
+    alu     GLBREG  GLBREG + d.4 <<16 ;\
+    MASKINST ;\
+    nop ;\
+    stc32   R1  GLBREG  high
+
+#define DEBUG_TRACE32( trace_word ) ;\
+    alu     GLBREG  GLBREG OR BASEADDR <<24 ;\
+    nop ;\
+    stc32   trace_word  GLBREG  high ;\
+    alu     GLBREG  GLBREG + d.4 <<16 ;\
+    MASKINST ;\
+    nop ;\
+    stc32   R1  GLBREG  high
+
+
+// tracec_on: 
+//   bit 0 (1): if set, record traces
+//   bit 1 (2): if set, do not enable bit 0 on TRACE_C_ON
+//   bit 2 (4): if set, and TRACE_C_DELAYED_OFF_PERM called, set bit 1.
+
+
+#define DEBUG_TRACE_C_ON()   DEBUG_TRACE_C_ON_0(__LINE__)
+#define DEBUG_TRACE_C_ON_0(line)   DEBUG_TRACE_C_ON_1(line)
+#define DEBUG_TRACE_C_ON_1(line)   \
+    ldc32  tracec_on  TRACE_C_TABLE_ADDRESS ;\
+    nop ;\
+    alu R0 tracec_on AND h.6 ;\
+    jmp!=0 :debug_trace_c_on_done_##line ds0 ;\
+    alu    tracec_on  tracec_on OR h.1 ;\
+    stc32  tracec_on  TRACE_C_TABLE_ADDRESS ;\
+:debug_trace_c_on_done_##line
+    
+#define DEBUG_TRACE_C_OFF()   \
+    ldc32  tracec_on  TRACE_C_TABLE_ADDRESS ;\
+    nop ;\
+    alu    tracec_on  tracec_on AND~ h.1 ;\
+    stc32  tracec_on  TRACE_C_TABLE_ADDRESS
+
+#define DEBUG_TRACE_C_OFF_PERM() \
+    mov    tracec_on d.2 clear ;\
+    stc32  tracec_on  TRACE_C_TABLE_ADDRESS
+
+#define DEBUG_TRACE_C_ON_PERM() \
+    mov    tracec_on d.1 clear ;\
+    stc32  tracec_on  TRACE_C_TABLE_ADDRESS
+
+#define DEBUG_TRACE_C_TRIG_DELAYED_OFF_PERM() \
+    ldc32  tracec_on  TRACE_C_TABLE_ADDRESS ;\
+    nop ;\
+    nop ;\
+    alu    tracec_on  tracec_on OR h.4 ;\
+    stc32  tracec_on  TRACE_C_TABLE_ADDRESS
+
+
+#define DEBUG_TRACE_C_DO_DELAYED_OFF_PERM()   DEBUG_TRACE_C_DO_DELAYED_OFF_PERM_0(__LINE__)
+#define DEBUG_TRACE_C_DO_DELAYED_OFF_PERM_0(line)   DEBUG_TRACE_C_DO_DELAYED_OFF_PERM_1(line)
+#define DEBUG_TRACE_C_DO_DELAYED_OFF_PERM_1(line)   \
+    ldc32  tracec_on  TRACE_C_TABLE_ADDRESS ;\
+    nop ;\
+    alu R0 tracec_on AND h.4 ;\
+    jmp=0  :debug_trace_c_do_delayed_off_perm_done_##line ;\
+    mov    tracec_on  h.2 ;\
+    stc32  tracec_on  TRACE_C_TABLE_ADDRESS ;\
+:debug_trace_c_do_delayed_off_perm_done_##line
+
+
+
+#define DEBUG_ID_TRACE24_C( id, trace_word ) DEBUG_ID_TRACE24_C_0( id, trace_word, __LINE__ )
+#define DEBUG_ID_TRACE24_C_0( id, trace_word, line ) DEBUG_ID_TRACE24_C_1( id, trace_word, line )
+#define DEBUG_ID_TRACE24_C_1( id, trace_word, line ) \
+    ldc32   tracec_on  TRACE_C_TABLE_ADDRESS ;\
+    nop ;\
+    jmp_clr :debug_id_trace24_c_done_##line tracec_on d.0 ds0;\
+    alu     GLBREG  GLBREG OR BASEADDR <<24 ;\
+    alu     GLBREG  GLBREG AND~ h.ff ;\
+    alu     GLBREG  GLBREG OR id ;\
+    nop ;\
+    stc32   trace_word  GLBREG  high ;\
+    stc8    GLBREG  GLBREG  high ;\
+    alu     GLBREG  GLBREG + d.4 <<16 ;\
+    MASKINST ;\
+    nop ;\
+    stc32   R1  GLBREG  high ;\
+:debug_id_trace24_c_done_##line
+
+#define DEBUG_TRACE32_C( trace_word ) DEBUG_TRACE32_C_0( trace_word, __LINE__ )
+#define DEBUG_TRACE32_C_0( trace_word, line ) DEBUG_TRACE32_C_1( trace_word, line )
+#define DEBUG_TRACE32_C_1( trace_word, line ) \
+    ldc32   tracec_on  TRACE_C_TABLE_ADDRESS ;\
+    nop ;\
+    jmp_clr :debug_trace32_c_done_##line tracec_on d.0 ds0;\
+    stc32   trace_word  GLBREG  high ;\
+    alu     GLBREG  GLBREG + d.4 <<16 ;\
+    MASKINST ;\
+    nop ;\
+    stc32   R1  GLBREG  high; \
+:debug_trace32_c_done_##line
+
+
+#define DEBUG_ID_TRACE24_CS( id, trace_word_macro ) \
+    alu  GLBREG GLBREG AND~ h.ff; \
+    lcall :debug_id_trace24_cs ;\
+    alu  trace_word trace_word_macro + d.0 ;\
+    alu  GLBREG  GLBREG OR id
+
+#define DEBUG_ID_TRACE16_CS( id, trace_word_macro ) \
+    alu  GLBREG GLBREG AND~ h.ff; \
+    mov  trace_word d.0 clear; \
+    lcall :debug_id_trace24_cs ;\
+    insert  trace_word trace_word_macro d.0 d.16; \
+    alu  GLBREG  GLBREG OR id
+    
+
+
+#define DEBUG_TRACE32_CS( trace_word_macro ) \
+    lcall :debug_trace32_cs ;\
+    alu  trace_word trace_word_macro + d.0 ;\
+    nop
+
+#define DEBUG_TRACE_MEM_C( trace_ptr, size ) DEBUG_TRACE_MEM_C_0( trace_ptr, size, __LINE__ )
+#define DEBUG_TRACE_MEM_C_0( trace_ptr, size, line ) DEBUG_TRACE_MEM_C_1( trace_ptr, size, line )
+#define DEBUG_TRACE_MEM_C_1( trace_ptr, size, line ) \
+        alu trace_ptr_local trace_ptr + d.0 ;\
+        ldc32  tracec_on  TRACE_C_TABLE_ADDRESS ;\
+        nop ;\
+        jmp_clr :debug_id_mem_c_done_##line  tracec_on d.0 ds0 ;\
+        alu     trace_end_ptr trace_ptr_local + size ;\
+        nop ;\
+:debug_id_mem_c_loop_##line ;\
+        ld32    trace_word trace_ptr_local ;\
+        alu     GLBREG  GLBREG OR BASEADDR <<24 ;\
+        alu     trace_ptr_local trace_ptr_local + d.4 ;\
+        stc32   trace_word  GLBREG  high ;\
+        alu     GLBREG  GLBREG + d.4 <<16 ;\
+        MASKINST ;\
+        nop ;\
+        jmp_cmp :debug_id_mem_c_loop_##line trace_end_ptr > trace_ptr_local  ;\
+        nop ;\
+        nop ;\
+        stc32   R1  GLBREG  high ;\
+:debug_id_mem_c_done_##line
+
+
+#endif /* DEBUG_TRACE */
+
+
+// Alternate use of debug trace memory space:  For fixed location counters and values instead of circular trace data
+//#define DEBUG_TRACE_FIXED_COUNT_ENABLE
+
+#if !defined(DEBUG_TRACE_FIXED_COUNT_ENABLE)
+
+// Don't define them at all for the negative path unless debugging.  That way the compile will notify us of any left over.
+// #define DEBUG_TRACE_COUNT(c)
+// #define DEBUG_TRACE_WRITE(c,v)
+
+#else
+
+#if defined(DEBUG_TRACE_ENABLE)
+#error DEBUG_TRACE_ENABLE and DEBUG_TRACE_FIXED_COUNT_ENABLE are mutually exclusive, but both are enabled.
+#endif
+    
+#define DEBUG_TRACE_COUNT(c) \
+DECLARE_FULL_REG_VAR ( temp_addr ) ;\
+DECLARE_FULL_REG_VAR ( temp_word ) ;\
+    mov     temp_addr  ((BASEADDR << 8) | (c << 2)) <<16 ;\
+    nop ;\
+    nop ;\
+    ldc32   temp_word  temp_addr  high ;\
+    alu     temp_word  temp_word + d.1 ;\
+    stc32   temp_word  temp_addr  high
+
+#define DEBUG_TRACE_COUNT_REGOFS(c, r, b) \
+DECLARE_FULL_REG_VAR ( temp_addr ) ;\
+DECLARE_FULL_REG_VAR ( temp_word ) ;\
+    mov     temp_addr  ((BASEADDR << 8) | (c << 2)) <<16 ;\
+    insert  temp_addr  r  d.18  b ;\
+    nop ;\
+    nop ;\
+    ldc32   temp_word  temp_addr  high ;\
+    alu     temp_word  temp_word + d.1 ;\
+    stc32   temp_word  temp_addr  high
+
+#define DEBUG_TRACE_WRITE(c,v) \
+DECLARE_FULL_REG_VAR ( temp_addr ) ;\
+    mov     temp_addr  ((BASEADDR << 8) | (c << 2)) <<16 ;\
+    nop ;\
+    nop ;\
+    stc32   v  temp_addr  high
+
+#endif /* DEBUG_TRACE_FIXED_COUNT_ENABLE */
+
+
+/* FW TRACE */
+
+/* Define the following to enable FWTRACE capability in both the Runner FW and driver. */
+//#define RUNNER_FWTRACE
+
+#ifdef RUNNER_FWTRACE
+/* With the FW Trace tool, we'll run the Runner timer counter with a 20ns interval.  Otherwise, it is set to 1us. */
+#define TIMER_PERIOD_NS                         20
+#define TIMER_PERIOD_REG_VALUE                  15 /* 20ns */
+/* 10ns will cause some timer limit register values to exceed 16-bits.   The developer must change them themselves to 0xFFFF to avoid more
+    frequent timer wakeups than expected */
+//#define TIMER_PERIOD_NS                         10
+//#define TIMER_PERIOD_REG_VALUE                  8 /* 10ns */
+
+/* These are the Runner FW Trace Options:  
+        - RUNNER_FWTRACE_32BIT - Define to have 32-bit timestamps.   If not defined, FWTRACE will use 16-bit timestamps.   16-bit is better
+           for a busy Runner snapshot as you won't wrap
+        - FWTRACE_READ_TASKID - If defined, the FW Trace macro will read the thread ID from an I/O register.  If not defined, it will write the 
+           event ID passed into the macro (built using EVID).
+        - FWTRACE_ENABLE_TRACE_ALL - If defined, all FWTRACE_EVENTs through the Runner code are active.  This is useful for tracing everything
+          with standard events (Entry, Exit, DMA start, DMA return).   With or without these events activated, developers can also use 
+          FWTRACE_EVENT_DEV for user defined events.   
+*/           
+//#define RUNNER_FWTRACE_32BIT //- must match RDD define
+#define FWTRACE_READ_TASKID
+#define FWTRACE_ENABLE_TRACE_ALL
+#define FWTRACE_FUNCTION
+
+/* FW Tracing */
+#define RUNNER_FWTRACE_ENABLE_BIT                   15
+#define RUNNER_FWTRACE_ENABLE_MASK_SWAPPED          0x00000080
+#define RUNNER_FWTRACE_ENABLE_MASK_SWAPPED_CLUSTER  0x00800080
+
+/* Event Types */
+#define FW_TRACE_THREAD_ENTRY                   1
+#define FW_TRACE_THREAD_EXIT                    2
+#define FW_TRACE_DMA_RD                         3
+#define FW_TRACE_DMA_RD_RET                     4
+#define FW_TRACE_DMA_WR                         5
+#define FW_TRACE_DMA_WR_RET                     6
+// Additional exit events to distinguish code points
+#define FW_TRACE_THREAD_EXIT_2                  7
+#define FW_TRACE_THREAD_EXIT_3                  8
+#define FW_TRACE_THREAD_EXIT_4                  9
+#define FW_TRACE_THREAD_EXIT_5                  10
+#define FW_TRACE_THREAD_EXIT_6                  11
+#define FW_TRACE_THREAD_EXIT_7                  12
+#define FW_TRACE_THREAD_EXIT_8                  13
+#define FW_TRACE_DMA_RD_2                       14
+#define FW_TRACE_DMA_RD_RET_2                   15
+
+
+
+#ifdef FWTRACE_READ_TASKID
+#define EVID(ThreadNum, EventNum) (EventNum)
+#else
+#ifdef RUNNER_FWTRACE_32BIT
+#define EVID(ThreadNum, EventNum) (EventNum)
+#else
+#define EVID(ThreadNum, EventNum) ((ThreadNum << 8) | (EventNum))
+#endif
+#endif
+
+#ifdef RUNNER_A
+#ifdef RUNNER_MAIN
+    #define RUNNER_FWTRACE_CURR_OFFSET          RUNNER_FWTRACE_MAINA_CURR_OFFSET_ADDRESS
+    #define RUNNER_FWTRACE_BASE                 RUNNER_FWTRACE_MAINA_BASE_ADDRESS
+    #define RUNNER_FWTRACE_PARAM                RUNNER_FWTRACE_MAINA_PARAM_ADDRESS
+#endif /* RUNNER_MAIN*/
+#ifdef RUNNER_PICO
+    #define RUNNER_FWTRACE_CURR_OFFSET          (RUNNER_FWTRACE_MAINA_CURR_OFFSET_ADDRESS+2)
+    #define RUNNER_FWTRACE_BASE                 RUNNER_FWTRACE_PICOA_BASE_ADDRESS
+    #define RUNNER_FWTRACE_PARAM                RUNNER_FWTRACE_PICOA_PARAM_ADDRESS
+#endif /* RUNNER_PICO*/
+#else /* RUNNER_B */
+#ifdef RUNNER_MAIN
+    #define RUNNER_FWTRACE_CURR_OFFSET          RUNNER_FWTRACE_MAINB_CURR_OFFSET_ADDRESS
+    #define RUNNER_FWTRACE_BASE                 RUNNER_FWTRACE_MAINB_BASE_ADDRESS
+    #define RUNNER_FWTRACE_PARAM                RUNNER_FWTRACE_MAINB_PARAM_ADDRESS
+#endif /* RUNNER_MAIN*/
+#ifdef RUNNER_PICO
+    #define RUNNER_FWTRACE_CURR_OFFSET          (RUNNER_FWTRACE_MAINB_CURR_OFFSET_ADDRESS+2)
+    #define RUNNER_FWTRACE_BASE                 RUNNER_FWTRACE_PICOB_BASE_ADDRESS
+    #define RUNNER_FWTRACE_PARAM                RUNNER_FWTRACE_PICOB_PARAM_ADDRESS
+#endif /* RUNNER_PICO*/
+#endif /* IF RUNNER_A */
+
+
+#ifdef FWTRACE_ENABLE_TRACE_ALL
+#define FWTRACE_EVENT( task_id, eventId ) FWTRACE_EVENT_A( task_id, eventId, __LINE__ )
+#else
+#define FWTRACE_EVENT( task_id, eventId )
+#endif
+#define FWTRACE_EVENT_DEV( task_id, eventId ) FWTRACE_EVENT_A( task_id, eventId, __LINE__ )
+
+#define FWTRACE_EVENT_A( task_id, eventId, line ) FWTRACE_EVENT_B( task_id, eventId, line )
+
+/* Currently these macros are hardcoded for 128 entries for 32-bit and 256 for 16-bit timestamps. */
+#ifndef FWTRACE_FUNCTION
+
+#ifdef RUNNER_FWTRACE_32BIT
+#ifdef FWTRACE_READ_TASKID
+#define FWTRACE_EVENT_B( task_id, eventId, line ) ;\
+    ldc16      rnr_fwtrace_tmp     RUNNER_FWTRACE_CURR_OFFSET ;\
+    /* Move in base address for trace */;\
+    mov       rnr_fwtrace_addr RUNNER_FWTRACE_BASE clear ;\
+    /* Check if enabled */ ;\
+    jmp_clr   :task_id##line##_fwtrace_done rnr_fwtrace_tmp RUNNER_FWTRACE_ENABLE_BIT ds1 ;\
+    /* Get current offset address base for task.   Curr pointer is 8 bits in rnr_fwtrace_tmp */ ;\
+    insert    rnr_fwtrace_addr rnr_fwtrace_tmp d.3 d.6 ;\
+    /* Check if one-shot full */ ;\
+    jmp_set   :task_id##line##_fwtrace_done   rnr_fwtrace_tmp d.7 ;\
+    /* Increment pointer now as we require two nops before load */ ;\
+    alu       rnr_fwtrace_tmp rnr_fwtrace_tmp + d.1 ;\
+    stc16      rnr_fwtrace_tmp RUNNER_FWTRACE_CURR_OFFSET;\
+    /* Load reg with taskId, which is bits 20:16 in the periphstatus reg.  Reuse enable register */ ;\
+    ldio32    rnr_fwtrace_tmp PERIPHERALS_STATUS_REGISTER_IO_ADDRESS ;\
+    shift     rnr_fwtrace_tmp asr rnr_fwtrace_tmp d.16 ;\
+    /* Move thread to upper 16 bits, insert event ID into lower, then write */ ;\
+    insert    rnr_fwtrace_tmp rnr_fwtrace_tmp d.16 d.5 ;\
+    mov       rnr_fwtrace_tmp eventId ;\
+    stc32      rnr_fwtrace_tmp rnr_fwtrace_addr ;\
+    /* Write time */ ;\
+    ldio32    rnr_fwtrace_tmp TIMER_VALUE_IO_ADDRESS ;\
+    stc32      rnr_fwtrace_tmp rnr_fwtrace_addr d.4 ;\
+:task_id##line##_fwtrace_done
+#else
+#define FWTRACE_EVENT_B( task_id, eventId, line ) ;\
+    ldc16      rnr_fwtrace_tmp     RUNNER_FWTRACE_CURR_OFFSET ;\
+    /* Move in base address for trace */;\
+    mov       rnr_fwtrace_addr RUNNER_FWTRACE_BASE clear ;\
+    /* Check if enabled */ ;\
+    jmp_clr   :task_id##line##_fwtrace_done rnr_fwtrace_tmp RUNNER_FWTRACE_ENABLE_BIT ds1 ;\
+    /* Get current offset address base for task.   Curr pointer is 8 bits in rnr_fwtrace_tmp */ ;\
+    insert    rnr_fwtrace_addr rnr_fwtrace_tmp d.3 d.6 ;\
+    /* Check if one-shot full */ ;\
+    jmp_set   :task_id##line##_fwtrace_done   rnr_fwtrace_tmp d.7 ;\
+    /* Increment pointer now as we require two nops before load */ ;\
+    alu       rnr_fwtrace_tmp rnr_fwtrace_tmp + d.1 ;\
+    stc16      rnr_fwtrace_tmp RUNNER_FWTRACE_CURR_OFFSET;\
+    mov       rnr_fwtrace_tmp task_id <<16;\
+    mov       rnr_fwtrace_tmp eventId ;\
+    stc32      rnr_fwtrace_tmp rnr_fwtrace_addr ;\
+    /* Write time */ ;\
+    ldio32    rnr_fwtrace_tmp TIMER_VALUE_IO_ADDRESS ;\
+    stc32      rnr_fwtrace_tmp rnr_fwtrace_addr d.4 ;\
+:task_id##line##_fwtrace_done
+#endif // Read Task Id
+#else // 16 bit
+#ifdef FWTRACE_READ_TASKID
+#define FWTRACE_EVENT_B( task_id, eventId, line ) ;\
+    ldc16      rnr_fwtrace_tmp     RUNNER_FWTRACE_CURR_OFFSET ;\
+    /* Move in base address for trace */;\
+    mov       rnr_fwtrace_addr RUNNER_FWTRACE_BASE clear ;\
+    /* Check if enabled.  Bit 15 of 16-bit register */ ;\
+    jmp_clr   :task_id##line##_fwtrace_done rnr_fwtrace_tmp RUNNER_FWTRACE_ENABLE_BIT ds1 ;\
+    /* Get current offset address base for task.   Curr pointer is 8 bits in rnr_fwtrace_tmp */ ;\
+    insert    rnr_fwtrace_addr rnr_fwtrace_tmp d.2 d.8 ;\
+    /* Check if one-shot full */ ;\
+    jmp_set   :task_id##line##_fwtrace_done   rnr_fwtrace_tmp d.8 ;\
+    /* Increment pointer now as we require two nops before load */ ;\
+    alu       rnr_fwtrace_tmp rnr_fwtrace_tmp + d.1 ;\
+    stc16      rnr_fwtrace_tmp RUNNER_FWTRACE_CURR_OFFSET;\
+    /* Load reg with taskId, which is bits 20:16 in the periphstatus reg. */ ;\
+    /* Create 16 bit event ID + thread ID for write */ ;\
+    ldio16    rnr_fwtrace_tmp (PERIPHERALS_STATUS_REGISTER_IO_ADDRESS+2) ;\
+    mov       rnr_fwtrace_tmp eventId <<16;\
+    insert    rnr_fwtrace_tmp rnr_fwtrace_tmp d.24 d.5 ;\
+    shift     rnr_fwtrace_tmp asr rnr_fwtrace_tmp d.16 ;\
+    /* Write event+thread value */ ;\
+    stc16      rnr_fwtrace_tmp rnr_fwtrace_addr ;\
+    alu       rnr_fwtrace_addr rnr_fwtrace_addr + d.2 ;\
+    /* Load time and then write to next 16 bit address */ ;\
+    ldio16    rnr_fwtrace_tmp TIMER_VALUE_IO_ADDRESS ;\
+    /* Write time value */ ;\
+    stc16      rnr_fwtrace_tmp rnr_fwtrace_addr ;\
+:task_id##line##_fwtrace_done
+#else
+#define FWTRACE_EVENT_B( task_id, eventId, line ) ;\
+    ldc16      rnr_fwtrace_tmp     RUNNER_FWTRACE_CURR_OFFSET ;\
+    /* Move in base address for trace */;\
+    mov       rnr_fwtrace_addr RUNNER_FWTRACE_BASE clear ;\
+    /* Check if enabled */ ;\
+    jmp_clr   :task_id##line##_fwtrace_done rnr_fwtrace_tmp RUNNER_FWTRACE_ENABLE_BIT ds1 ;\
+    /* Get current offset address base for task.   Curr pointer is 8 bits in rnr_fwtrace_tmp */ ;\
+    insert    rnr_fwtrace_addr rnr_fwtrace_tmp d.2 d.8 ;\
+    /* Check if one-shot full */ ;\
+    jmp_set   :task_id##line##_fwtrace_done   rnr_fwtrace_tmp d.8 ;\
+    /* Increment pointer now as we require two nops before load */ ;\
+    alu       rnr_fwtrace_tmp rnr_fwtrace_tmp + d.1 ;\
+    stc16      rnr_fwtrace_tmp RUNNER_FWTRACE_CURR_OFFSET;\
+    /* Load time and then merge in event into upper 16 bits */ ;\
+    ldio32    rnr_fwtrace_tmp TIMER_VALUE_IO_ADDRESS ;\
+    mov       rnr_fwtrace_tmp eventId <<16 ;\
+    stc32      rnr_fwtrace_tmp rnr_fwtrace_addr ;\
+:task_id##line##_fwtrace_done
+#endif
+#endif // 16 bit version
+
+#else 
+#define FWTRACE_EVENT_B( task_id, eventId, line ) ;\
+    lcall     :fw_trace_event_b ;\
+    mov      R6 eventId ;\
+    st16     R6 RUNNER_FWTRACE_PARAM;\
+:task_id##line##_fwtrace_done ;
+#endif
+
+#else /* RUNNER_FWTRACE not enabled */
+#define FWTRACE_EVENT( task_id, eventId )
+#define FWTRACE_EVENT_DEV( task_id, eventId )
+
+#endif /* RUNNER_FWTRACE */
+
+#endif
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_runner_defs_auto.h b/arch/arm/mach-bcmbca/rdp/rdd_runner_defs_auto.h
new file mode 100755
index 0000000000..93ebcabad5
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_runner_defs_auto.h
@@ -0,0 +1,8240 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+
+
+/* This is an automated file. Do not edit its contents. */
+
+
+#ifndef _RDD_RUNNER_DEFS_AUTO_H
+#define _RDD_RUNNER_DEFS_AUTO_H
+
+#ifdef DSL_63138
+/* PRIVATE_A */
+#define INGRESS_HANDLER_BUFFER_ADDRESS 0x0000
+#define INGRESS_HANDLER_BUFFER_BYTE_SIZE 0x2000
+#define INGRESS_HANDLER_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_INGRESS_HANDLER_BUFFER_SIZE     32
+#define RDD_INGRESS_HANDLER_BUFFER_LOG2_SIZE     5
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS 0x2000
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_BYTE_SIZE 0x4000
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_LOG2_BYTE_SIZE 0x000e
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE     2048
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_LOG2_SIZE     11
+#define DS_CONNECTION_CONTEXT_BUFFER_ADDRESS 0x6000
+#define DS_CONNECTION_CONTEXT_BUFFER_BYTE_SIZE 0x0400
+#define DS_CONNECTION_CONTEXT_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_LOG2_SIZE     3
+#define DS_GSO_HEADER_BUFFER_ADDRESS 0x6400
+#define DS_GSO_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_GSO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_GSO_PSEUDO_HEADER_BUFFER_ADDRESS 0x6480
+#define DS_GSO_PSEUDO_HEADER_BUFFER_BYTE_SIZE 0x0028
+#define DS_GSO_PSEUDO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x64a8
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0008
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     2
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_ADDRESS 0x64b0
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_BYTE_SIZE 0x0010
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_SIZE     8
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_LOG2_SIZE     3
+#define DS_CPU_REASON_TO_METER_TABLE_ADDRESS 0x64c0
+#define DS_CPU_REASON_TO_METER_TABLE_BYTE_SIZE 0x0040
+#define DS_CPU_REASON_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE     64
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_LOG2_SIZE     6
+#define DS_GSO_CHUNK_BUFFER_ADDRESS 0x6500
+#define DS_GSO_CHUNK_BUFFER_BYTE_SIZE 0x0080
+#define DS_GSO_CHUNK_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_CPU_RX_METER_TABLE_ADDRESS 0x6580
+#define DS_CPU_RX_METER_TABLE_BYTE_SIZE 0x0080
+#define DS_CPU_RX_METER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_CPU_RX_METER_TABLE_SIZE     16
+#define RDD_DS_CPU_RX_METER_TABLE_LOG2_SIZE     4
+#define DS_POLICER_TABLE_ADDRESS 0x6600
+#define DS_POLICER_TABLE_BYTE_SIZE 0x0100
+#define DS_POLICER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_POLICER_TABLE_SIZE     16
+#define RDD_DS_POLICER_TABLE_LOG2_SIZE     4
+#define IPSEC_DS_BUFFER_POOL_ADDRESS 0x6700
+#define IPSEC_DS_BUFFER_POOL_BYTE_SIZE 0x0160
+#define IPSEC_DS_BUFFER_POOL_LOG2_BYTE_SIZE 0x0009
+#define RDD_IPSEC_DS_BUFFER_POOL_SIZE     2
+#define RDD_IPSEC_DS_BUFFER_POOL_LOG2_SIZE     1
+#define IPSEC_DS_SA_DESC_TABLE_ADDRESS 0x6860
+#define IPSEC_DS_SA_DESC_TABLE_BYTE_SIZE 0x0500
+#define IPSEC_DS_SA_DESC_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_IPSEC_DS_SA_DESC_TABLE_SIZE     16
+#define RDD_IPSEC_DS_SA_DESC_TABLE_LOG2_SIZE     4
+#define IPSEC_US_SA_DESC_TABLE_ADDRESS 0x6d60
+#define IPSEC_US_SA_DESC_TABLE_BYTE_SIZE 0x0500
+#define IPSEC_US_SA_DESC_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_IPSEC_US_SA_DESC_TABLE_SIZE     16
+#define RDD_IPSEC_US_SA_DESC_TABLE_LOG2_SIZE     4
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_ADDRESS 0x7260
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_BYTE_SIZE 0x0300
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_LOG2_SIZE     5
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x7560
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define DS_SPDSVC_CONTEXT_TABLE_ADDRESS 0x7580
+#define DS_SPDSVC_CONTEXT_TABLE_BYTE_SIZE 0x0050
+#define DS_SPDSVC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x75d0
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0010
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     3
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS 0x75e0
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_BYTE_SIZE 0x0100
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_LOG2_SIZE     5
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x76e0
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define WLAN_MCAST_CONTROL_TABLE_ADDRESS 0x7700
+#define WLAN_MCAST_CONTROL_TABLE_BYTE_SIZE 0x0094
+#define WLAN_MCAST_CONTROL_TABLE_LOG2_BYTE_SIZE 0x0008
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_ADDRESS 0x7794
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_BYTE_SIZE 0x0004
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DS_TOTAL_PPS_RATE_LIMITER_ADDRESS 0x7798
+#define DS_TOTAL_PPS_RATE_LIMITER_BYTE_SIZE 0x0008
+#define DS_TOTAL_PPS_RATE_LIMITER_LOG2_BYTE_SIZE 0x0003
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS 0x77a0
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_BYTE_SIZE 0x0020
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE     1
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE2    4
+#define RATE_LIMITER_REMAINDER_TABLE_ADDRESS 0x77c0
+#define RATE_LIMITER_REMAINDER_TABLE_BYTE_SIZE 0x0040
+#define RATE_LIMITER_REMAINDER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE     32
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS 0x7800
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_SIZE     8
+#define FC_MCAST_CONNECTION2_TABLE_ADDRESS 0x8000
+#define FC_MCAST_CONNECTION2_TABLE_BYTE_SIZE 0x0800
+#define FC_MCAST_CONNECTION2_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_FC_MCAST_CONNECTION2_TABLE_SIZE     128
+#define RDD_FC_MCAST_CONNECTION2_TABLE_LOG2_SIZE     7
+#define ETH_TX_QUEUES_POINTERS_TABLE_ADDRESS 0x8800
+#define ETH_TX_QUEUES_POINTERS_TABLE_BYTE_SIZE 0x0120
+#define ETH_TX_QUEUES_POINTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE     72
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_LOG2_SIZE     7
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_ADDRESS 0x8920
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_BYTE_SIZE 0x0020
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS 0x8940
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define SBPM_REPLY_ADDRESS 0x8980
+#define SBPM_REPLY_BYTE_SIZE 0x0080
+#define SBPM_REPLY_LOG2_BYTE_SIZE 0x0007
+#define ETH_TX_QUEUES_TABLE_ADDRESS 0x8a00
+#define ETH_TX_QUEUES_TABLE_BYTE_SIZE 0x0480
+#define ETH_TX_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_ETH_TX_QUEUES_TABLE_SIZE     72
+#define RDD_ETH_TX_QUEUES_TABLE_LOG2_SIZE     7
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS 0x8e80
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_BYTE_SIZE 0x0080
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE     1
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE2    4
+#define DS_FORWARDING_MATRIX_TABLE_ADDRESS 0x8f00
+#define DS_FORWARDING_MATRIX_TABLE_BYTE_SIZE 0x0090
+#define DS_FORWARDING_MATRIX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_DS_FORWARDING_MATRIX_TABLE_LOG2_SIZE     4
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2    16
+#define RDD_DS_FORWARDING_MATRIX_TABLE_LOG2_SIZE2    4
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0x8f90
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0010
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS 0x8fa0
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_BYTE_SIZE 0x0020
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_SIZE     2
+#define DS_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0x8fc0
+#define DS_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0040
+#define DS_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_L2_UCAST_CONNECTION_BUFFER_SIZE     4
+#define RDD_DS_L2_UCAST_CONNECTION_BUFFER_LOG2_SIZE     2
+#define ETH_TX_MAC_TABLE_ADDRESS 0x9000
+#define ETH_TX_MAC_TABLE_BYTE_SIZE 0x0140
+#define ETH_TX_MAC_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_ETH_TX_MAC_TABLE_SIZE     10
+#define RDD_ETH_TX_MAC_TABLE_LOG2_SIZE     4
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_ADDRESS 0x9140
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_BYTE_SIZE 0x0030
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINA_PARAM_ADDRESS 0x9170
+#define RUNNER_FWTRACE_MAINA_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINA_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_LOG2_SIZE     1
+#define INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS 0x9180
+#define INGRESS_HANDLER_SKB_DATA_POINTER_BYTE_SIZE 0x0080
+#define INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_SIZE     5
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0x9200
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9240
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9280
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_ADDRESS 0x92c0
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0030
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE     3
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_LOG2_SIZE     2
+#define RUNNER_FWTRACE_PICOA_PARAM_ADDRESS 0x92f0
+#define RUNNER_FWTRACE_PICOA_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_PICOA_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_LOG2_SIZE     1
+#define DS_RATE_LIMITER_TABLE_ADDRESS 0x9300
+#define DS_RATE_LIMITER_TABLE_BYTE_SIZE 0x0100
+#define DS_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_RATE_LIMITER_TABLE_SIZE     32
+#define RDD_DS_RATE_LIMITER_TABLE_LOG2_SIZE     5
+#define DS_WAN_FLOW_TABLE_ADDRESS 0x9400
+#define DS_WAN_FLOW_TABLE_BYTE_SIZE 0x0200
+#define DS_WAN_FLOW_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_WAN_FLOW_TABLE_SIZE     256
+#define RDD_DS_WAN_FLOW_TABLE_LOG2_SIZE     8
+#define DS_WAN_UDP_FILTER_TABLE_ADDRESS 0x9600
+#define DS_WAN_UDP_FILTER_TABLE_BYTE_SIZE 0x0200
+#define DS_WAN_UDP_FILTER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_WAN_UDP_FILTER_TABLE_SIZE     32
+#define RDD_DS_WAN_UDP_FILTER_TABLE_LOG2_SIZE     5
+#define FC_MCAST_PORT_HEADER_BUFFER_ADDRESS 0x9800
+#define FC_MCAST_PORT_HEADER_BUFFER_BYTE_SIZE 0x0200
+#define FC_MCAST_PORT_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE     8
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_LOG2_SIZE     3
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2    64
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_LOG2_SIZE2    6
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_ADDRESS 0x9a00
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_BYTE_SIZE 0x0200
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_LOG2_SIZE     3
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_ADDRESS 0x9c00
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_BYTE_SIZE 0x0200
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_LOG2_BYTE_SIZE 0x0009
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE     64
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_LOG2_SIZE     6
+#define ETH0_RX_DESCRIPTORS_ADDRESS 0x9e00
+#define ETH0_RX_DESCRIPTORS_BYTE_SIZE 0x0100
+#define ETH0_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH0_RX_DESCRIPTORS_SIZE     32
+#define RDD_ETH0_RX_DESCRIPTORS_LOG2_SIZE     5
+#define DS_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x9f00
+#define DS_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x9f80
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_ADDRESS 0xa000
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_BYTE_SIZE 0x0200
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE     64
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_CPU_TX_BBH_DESCRIPTORS_ADDRESS 0xa200
+#define DS_CPU_TX_BBH_DESCRIPTORS_BYTE_SIZE 0x0100
+#define DS_CPU_TX_BBH_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_LOG2_SIZE     5
+#define DS_PROFILING_BUFFER_PICO_RUNNER_ADDRESS 0xa300
+#define DS_PROFILING_BUFFER_PICO_RUNNER_BYTE_SIZE 0x0100
+#define DS_PROFILING_BUFFER_PICO_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define GSO_PICO_QUEUE_ADDRESS 0xa400
+#define GSO_PICO_QUEUE_BYTE_SIZE 0x0200
+#define GSO_PICO_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_GSO_PICO_QUEUE_SIZE     64
+#define RDD_GSO_PICO_QUEUE_LOG2_SIZE     6
+#define DHD_TX_POST_PD_INGRESS_QUEUE_ADDRESS 0xa600
+#define DHD_TX_POST_PD_INGRESS_QUEUE_BYTE_SIZE 0x0100
+#define DHD_TX_POST_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_SIZE     32
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS 0xa700
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_BYTE_SIZE 0x0080
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_SIZE     4
+#define DS_CONNECTION_CACHE_BUFFER_ADDRESS 0xa780
+#define DS_CONNECTION_CACHE_BUFFER_BYTE_SIZE 0x0080
+#define DS_CONNECTION_CACHE_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_CONNECTION_CACHE_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CACHE_BUFFER_LOG2_SIZE     3
+#define IPSEC_DS_QUEUE_ADDRESS 0xa800
+#define IPSEC_DS_QUEUE_BYTE_SIZE 0x0200
+#define IPSEC_DS_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_IPSEC_DS_QUEUE_SIZE     64
+#define RDD_IPSEC_DS_QUEUE_LOG2_SIZE     6
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS 0xaa00
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x00c0
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE     4
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_ADDRESS 0xaac0
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_BYTE_SIZE 0x0040
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0xab00
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     16
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     4
+#define ETH_TX_LOCAL_REGISTERS_ADDRESS 0xab80
+#define ETH_TX_LOCAL_REGISTERS_BYTE_SIZE 0x0048
+#define ETH_TX_LOCAL_REGISTERS_LOG2_BYTE_SIZE 0x0007
+#define RDD_ETH_TX_LOCAL_REGISTERS_SIZE     9
+#define RDD_ETH_TX_LOCAL_REGISTERS_LOG2_SIZE     4
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS 0xabc8
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_BYTE_SIZE 0x0008
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_SIZE     1
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS 0xabd0
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_BYTE_SIZE 0x0010
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_BYTE_SIZE 0x0004
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     8
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_SIZE     3
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xabe0
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define CPU_TX_FAST_QUEUE_ADDRESS 0xac00
+#define CPU_TX_FAST_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_FAST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_FAST_QUEUE_SIZE     16
+#define RDD_CPU_TX_FAST_QUEUE_LOG2_SIZE     4
+#define DS_QUEUE_PROFILE_TABLE_ADDRESS 0xac80
+#define DS_QUEUE_PROFILE_TABLE_BYTE_SIZE 0x0080
+#define DS_QUEUE_PROFILE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_QUEUE_PROFILE_TABLE_SIZE     8
+#define RDD_DS_QUEUE_PROFILE_TABLE_LOG2_SIZE     3
+#define CPU_TX_PICO_QUEUE_ADDRESS 0xad00
+#define CPU_TX_PICO_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_PICO_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_PICO_QUEUE_SIZE     16
+#define RDD_CPU_TX_PICO_QUEUE_LOG2_SIZE     4
+#define DS_SQ_ENQUEUE_QUEUE_ADDRESS 0xad80
+#define DS_SQ_ENQUEUE_QUEUE_BYTE_SIZE 0x0040
+#define DS_SQ_ENQUEUE_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_SQ_ENQUEUE_QUEUE_SIZE     64
+#define RDD_DS_SQ_ENQUEUE_QUEUE_LOG2_SIZE     6
+#define MULTICAST_HEADER_BUFFER_ADDRESS 0xadc0
+#define MULTICAST_HEADER_BUFFER_BYTE_SIZE 0x0040
+#define MULTICAST_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_ADDRESS 0xae00
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_BYTE_SIZE 0x0080
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE     16
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_LOG2_SIZE     4
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS 0xae80
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xaec0
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define DS_NULL_BUFFER_ADDRESS 0xaee0
+#define DS_NULL_BUFFER_BYTE_SIZE 0x0018
+#define DS_NULL_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_NULL_BUFFER_SIZE     3
+#define RDD_DS_NULL_BUFFER_LOG2_SIZE     2
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS 0xaef8
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_BYTE_SIZE 0x0008
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0003
+#define CPU_RX_PD_INGRESS_QUEUE_ADDRESS 0xaf00
+#define CPU_RX_PD_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define CPU_RX_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE     16
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_LOG2_SIZE     4
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_ADDRESS 0xaf80
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE     64
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS 0xafc0
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_ADDRESS 0xb000
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE     16
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_LOG2_SIZE     4
+#define DS_ROUTER_INGRESS_QUEUE_ADDRESS 0xb080
+#define DS_ROUTER_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_ROUTER_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_ROUTER_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_ROUTER_INGRESS_QUEUE_LOG2_SIZE     6
+#define DHD_COMPLETE_RING_BUFFER_ADDRESS 0xb0c0
+#define DHD_COMPLETE_RING_BUFFER_BYTE_SIZE 0x0018
+#define DHD_COMPLETE_RING_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DHD_COMPLETE_RING_BUFFER_SIZE     3
+#define RDD_DHD_COMPLETE_RING_BUFFER_LOG2_SIZE     2
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS 0xb0d8
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_BYTE_SIZE 0x0008
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_SIZE     3
+#define DS_CPU_PARAMETERS_BLOCK_ADDRESS 0xb0e0
+#define DS_CPU_PARAMETERS_BLOCK_BYTE_SIZE 0x0014
+#define DS_CPU_PARAMETERS_BLOCK_LOG2_BYTE_SIZE 0x0005
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_ADDRESS 0xb0f4
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_ADDRESS 0xb0f8
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_BYTE_SIZE 0x0006
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xb0fe
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_TX_POST_HEADER_SCRATCH_ADDRESS 0xb100
+#define DS_DHD_TX_POST_HEADER_SCRATCH_BYTE_SIZE 0x0080
+#define DS_DHD_TX_POST_HEADER_SCRATCH_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE     4
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_LOG2_SIZE     2
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS 0xb180
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_BYTE_SIZE 0x00a0
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_LOG2_BYTE_SIZE 0x0008
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE     5
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_LOG2_SIZE     3
+#define FC_MCAST_CONNECTION_TABLE_PLUS_ADDRESS 0xb220
+#define FC_MCAST_CONNECTION_TABLE_PLUS_BYTE_SIZE 0x0014
+#define FC_MCAST_CONNECTION_TABLE_PLUS_LOG2_BYTE_SIZE 0x0005
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xb234
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_BPM_DDR_BUFFERS_BASE_ADDRESS 0xb238
+#define DS_BPM_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_CONNECTION_TABLE_CONFIG_ADDRESS 0xb23c
+#define DS_CONNECTION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONNECTION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define DS_DATA_POINTER_DUMMY_TARGET_ADDRESS 0xb240
+#define DS_DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0014
+#define DS_DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE     5
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_LOG2_SIZE     3
+#define DS_CONTEXT_TABLE_CONFIG_ADDRESS 0xb254
+#define DS_CONTEXT_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONTEXT_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS 0xb258
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_BYTE_SIZE 0x0004
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_SIZE     2
+#define DS_PARALLEL_PROCESSING_SLAVE_LOCK_ADDRESS 0xb25c
+#define DS_PARALLEL_PROCESSING_SLAVE_LOCK_BYTE_SIZE 0x0004
+#define DS_PARALLEL_PROCESSING_SLAVE_LOCK_LOG2_BYTE_SIZE 0x0002
+#define SERVICE_QUEUES_WLAN_SCRATCH_ADDRESS 0xb260
+#define SERVICE_QUEUES_WLAN_SCRATCH_BYTE_SIZE 0x0014
+#define SERVICE_QUEUES_WLAN_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define DS_CPU_TX_FLUSH_PAUSE_REQUEST_ADDRESS 0xb274
+#define DS_CPU_TX_FLUSH_PAUSE_REQUEST_BYTE_SIZE 0x0004
+#define DS_CPU_TX_FLUSH_PAUSE_REQUEST_LOG2_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS 0xb278
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_BYTE_SIZE 0x0004
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_SIZE     2
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_ADDRESS 0xb27c
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_BYTE_SIZE 0x0004
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_LOG2_BYTE_SIZE 0x0002
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS 0xb280
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xb2c0
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0050
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE     10
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_LOG2_SIZE     4
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ADDRESS 0xb310
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_BYTE_SIZE 0x000a
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0004
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xb31a
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_ADDRESS 0xb31c
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define DS_DEBUG_BUFFER_ADDRESS 0xb320
+#define DS_DEBUG_BUFFER_BYTE_SIZE 0x0080
+#define DS_DEBUG_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_DEBUG_BUFFER_SIZE     32
+#define RDD_DS_DEBUG_BUFFER_LOG2_SIZE     5
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb3a0
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS 0xb3b0
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_BYTE_SIZE 0x0010
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_BYTE_SIZE 0x0004
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     8
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_SIZE     3
+#define DS_DHD_FLOW_RING_DROP_COUNTER_ADDRESS 0xb3c0
+#define DS_DHD_FLOW_RING_DROP_COUNTER_BYTE_SIZE 0x0014
+#define DS_DHD_FLOW_RING_DROP_COUNTER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_LOG2_SIZE     3
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xb3d4
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS 0xb3d8
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_BYTE_SIZE 0x0008
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_SIZE     3
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb3e0
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define HASH_BUFFER_ADDRESS 0xb3f0
+#define HASH_BUFFER_BYTE_SIZE 0x0010
+#define HASH_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define GPON_RX_DIRECT_DESCRIPTORS_ADDRESS 0xb400
+#define GPON_RX_DIRECT_DESCRIPTORS_BYTE_SIZE 0x0100
+#define GPON_RX_DIRECT_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE     32
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_LOG2_SIZE     5
+#define DS_GSO_CONTEXT_TABLE_ADDRESS 0xb500
+#define DS_GSO_CONTEXT_TABLE_BYTE_SIZE 0x0084
+#define DS_GSO_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0008
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xb584
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_FW_MAC_ADDRS_ADDRESS 0xb588
+#define DS_FW_MAC_ADDRS_BYTE_SIZE 0x0080
+#define DS_FW_MAC_ADDRS_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_FW_MAC_ADDRS_SIZE     16
+#define RDD_DS_FW_MAC_ADDRS_LOG2_SIZE     4
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_ADDRESS 0xb608
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_BYTE_SIZE 0x0008
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_LOG2_BYTE_SIZE 0x0003
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS 0xb610
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_BYTE_SIZE 0x0010
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_SIZE     3
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS 0xb620
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_BYTE_SIZE 0x0010
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define ETH_TX_SCRATCH_ADDRESS 0xb630
+#define ETH_TX_SCRATCH_BYTE_SIZE 0x0010
+#define ETH_TX_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define RDD_ETH_TX_SCRATCH_SIZE     16
+#define RDD_ETH_TX_SCRATCH_LOG2_SIZE     4
+#define DS_SYSTEM_CONFIGURATION_ADDRESS 0xb640
+#define DS_SYSTEM_CONFIGURATION_BYTE_SIZE 0x0024
+#define DS_SYSTEM_CONFIGURATION_LOG2_BYTE_SIZE 0x0006
+#define SPDSVC_HOST_BUF_PTR_ADDRESS 0xb664
+#define SPDSVC_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define SPDSVC_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define GSO_TX_DHD_L2_BUFFER_ADDRESS 0xb668
+#define GSO_TX_DHD_L2_BUFFER_BYTE_SIZE 0x0016
+#define GSO_TX_DHD_L2_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_GSO_TX_DHD_L2_BUFFER_SIZE     22
+#define RDD_GSO_TX_DHD_L2_BUFFER_LOG2_SIZE     5
+#define IPTV_COUNTERS_BUFFER_ADDRESS 0xb67e
+#define IPTV_COUNTERS_BUFFER_BYTE_SIZE 0x0002
+#define IPTV_COUNTERS_BUFFER_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_TX_POST_INGRESS_QUEUE_ADDRESS 0xb680
+#define DS_DHD_TX_POST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_DHD_TX_POST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_LOG2_SIZE     6
+#define IPSEC_DS_SA_DESC_CAM_TABLE_ADDRESS 0xb6c0
+#define IPSEC_DS_SA_DESC_CAM_TABLE_BYTE_SIZE 0x0020
+#define IPSEC_DS_SA_DESC_CAM_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE     16
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_LOG2_SIZE     4
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_ADDRESS 0xb6e0
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_BYTE_SIZE 0x0010
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define RUNNER_FLOW_IH_RESPONSE_ADDRESS 0xb6f0
+#define RUNNER_FLOW_IH_RESPONSE_BYTE_SIZE 0x0008
+#define RUNNER_FLOW_IH_RESPONSE_LOG2_BYTE_SIZE 0x0003
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_ADDRESS 0xb6f8
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_BYTE_SIZE 0x0008
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_LOG2_BYTE_SIZE 0x0003
+#define DS_GSO_DESC_TABLE_ADDRESS 0xb700
+#define DS_GSO_DESC_TABLE_BYTE_SIZE 0x0080
+#define DS_GSO_DESC_TABLE_LOG2_BYTE_SIZE 0x0007
+#define WLAN_MCAST_INGRESS_QUEUE_ADDRESS 0xb780
+#define WLAN_MCAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define WLAN_MCAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE     64
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define IPSEC_US_SA_DESC_CAM_TABLE_ADDRESS 0xb7c0
+#define IPSEC_US_SA_DESC_CAM_TABLE_BYTE_SIZE 0x0020
+#define IPSEC_US_SA_DESC_CAM_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE     16
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_LOG2_SIZE     4
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_ADDRESS 0xb7e0
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_BYTE_SIZE 0x0018
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_LOG2_BYTE_SIZE 0x0005
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_ADDRESS 0xb7f8
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_BYTE_SIZE 0x0005
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_LOG2_BYTE_SIZE 0x0003
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE     5
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_LOG2_SIZE     3
+#define ETH_TX_EMACS_STATUS_ADDRESS 0xb7fd
+#define ETH_TX_EMACS_STATUS_BYTE_SIZE 0x0001
+#define ETH_TX_EMACS_STATUS_LOG2_BYTE_SIZE 0x0001
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xb7fe
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define GPON_RX_NORMAL_DESCRIPTORS_ADDRESS 0xb800
+#define GPON_RX_NORMAL_DESCRIPTORS_BYTE_SIZE 0x0100
+#define GPON_RX_NORMAL_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE     32
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_LOG2_SIZE     5
+#define CPU_TX_DHD_L2_BUFFER_ADDRESS 0xb900
+#define CPU_TX_DHD_L2_BUFFER_BYTE_SIZE 0x0016
+#define CPU_TX_DHD_L2_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_CPU_TX_DHD_L2_BUFFER_SIZE     22
+#define RDD_CPU_TX_DHD_L2_BUFFER_LOG2_SIZE     5
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_ADDRESS 0xb916
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_BYTE_SIZE 0x0002
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define HASH_BASED_FORWARDING_PORT_TABLE_ADDRESS 0xb918
+#define HASH_BASED_FORWARDING_PORT_TABLE_BYTE_SIZE 0x0004
+#define HASH_BASED_FORWARDING_PORT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE     4
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_LOG2_SIZE     2
+#define FIREWALL_IPV6_R16_BUFFER_ADDRESS 0xb91c
+#define FIREWALL_IPV6_R16_BUFFER_BYTE_SIZE 0x0004
+#define FIREWALL_IPV6_R16_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_ADDRESS 0xb920
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_ADDRESS 0xb930
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_ADDRESS 0xb940
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb950
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_ADDRESS 0xb952
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xb954
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_ADDRESS 0xb956
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_BYTE_SIZE 0x0002
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_LOG2_BYTE_SIZE 0x0001
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_ADDRESS 0xb958
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_BYTE_SIZE 0x0002
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_LOG2_BYTE_SIZE 0x0001
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_ADDRESS 0xb95a
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS 0xb95c
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_ADDRESS 0xb95e
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_BYTE_SIZE 0x0002
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define GSO_DESC_PTR_ADDRESS 0xb960
+#define GSO_DESC_PTR_BYTE_SIZE 0x0004
+#define GSO_DESC_PTR_LOG2_BYTE_SIZE 0x0002
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_ADDRESS 0xb964
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_BYTE_SIZE 0x0004
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define GSO_TX_DHD_HOST_BUF_PTR_ADDRESS 0xb968
+#define GSO_TX_DHD_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define GSO_TX_DHD_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE     4
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_LOG2_SIZE     2
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_ADDRESS 0xb96c
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_BYTE_SIZE 0x0004
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_LOG2_BYTE_SIZE 0x0002
+#define CPU_TX_DHD_HOST_BUF_PTR_ADDRESS 0xb970
+#define CPU_TX_DHD_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define CPU_TX_DHD_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE     4
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_LOG2_SIZE     2
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_ADDRESS 0xb974
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_BYTE_SIZE 0x0002
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_LOG2_BYTE_SIZE 0x0001
+#define DS_MEMLIB_SEMAPHORE_ADDRESS 0xb976
+#define DS_MEMLIB_SEMAPHORE_BYTE_SIZE 0x0002
+#define DS_MEMLIB_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define WAN_PHYSICAL_PORT_ADDRESS 0xb978
+#define WAN_PHYSICAL_PORT_BYTE_SIZE 0x0002
+#define WAN_PHYSICAL_PORT_LOG2_BYTE_SIZE 0x0001
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb97a
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_RUNNER_CONGESTION_STATE_ADDRESS 0xb97c
+#define DS_RUNNER_CONGESTION_STATE_BYTE_SIZE 0x0002
+#define DS_RUNNER_CONGESTION_STATE_LOG2_BYTE_SIZE 0x0001
+#define GSO_PICO_QUEUE_PTR_ADDRESS 0xb97e
+#define GSO_PICO_QUEUE_PTR_BYTE_SIZE 0x0002
+#define GSO_PICO_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_ADDRESS 0xb980
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_BYTE_SIZE 0x0002
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_ADDRESS 0xb982
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_BYTE_SIZE 0x0002
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_ADDRESS 0xb984
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_BYTE_SIZE 0x0002
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_ADDRESS 0xb986
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_BYTE_SIZE 0x0002
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_DDR_SA_DESC_SIZE_ADDRESS 0xb988
+#define IPSEC_DS_DDR_SA_DESC_SIZE_BYTE_SIZE 0x0002
+#define IPSEC_DS_DDR_SA_DESC_SIZE_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_QUEUE_PTR_ADDRESS 0xb98a
+#define IPSEC_DS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define IPSEC_DS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_IP_LENGTH_ADDRESS 0xb98c
+#define IPSEC_DS_IP_LENGTH_BYTE_SIZE 0x0002
+#define IPSEC_DS_IP_LENGTH_LOG2_BYTE_SIZE 0x0001
+#define PRIVATE_A_DUMMY_STORE_ADDRESS 0xb98e
+#define PRIVATE_A_DUMMY_STORE_BYTE_SIZE 0x0001
+#define PRIVATE_A_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_ADDRESS 0xb98f
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_BYTE_SIZE 0x0001
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_LOG2_BYTE_SIZE 0x0001
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xb990
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xb991
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define CPU_TX_DS_PICO_SEMAPHORE_ADDRESS 0xb992
+#define CPU_TX_DS_PICO_SEMAPHORE_BYTE_SIZE 0x0001
+#define CPU_TX_DS_PICO_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define DS_FC_GLOBAL_CFG_ADDRESS 0xb993
+#define DS_FC_GLOBAL_CFG_BYTE_SIZE 0x0001
+#define DS_FC_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_ADDRESS 0xb994
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_ADDRESS 0xb995
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_PACKET_BUFFER_SIZE_ASR_8_ADDRESS 0xb996
+#define DS_PACKET_BUFFER_SIZE_ASR_8_BYTE_SIZE 0x0001
+#define DS_PACKET_BUFFER_SIZE_ASR_8_LOG2_BYTE_SIZE 0x0001
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb997
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb998
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_ADDRESS 0xb999
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_BYTE_SIZE 0x0001
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS 0xb99a
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_ADDRESS 0xb99b
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_LOG2_BYTE_SIZE 0x0001
+#define DS_IH_CONGESTION_THRESHOLD_ADDRESS 0xb99c
+#define DS_IH_CONGESTION_THRESHOLD_BYTE_SIZE 0x0001
+#define DS_IH_CONGESTION_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define DS_FW_MAC_ADDRS_COUNT_ADDRESS 0xb99d
+#define DS_FW_MAC_ADDRS_COUNT_BYTE_SIZE 0x0001
+#define DS_FW_MAC_ADDRS_COUNT_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_DMA_SYNCHRONIZATION_ADDRESS 0xb99e
+#define DS_DHD_DMA_SYNCHRONIZATION_BYTE_SIZE 0x0001
+#define DS_DHD_DMA_SYNCHRONIZATION_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_SEMAPHORE_ADDRESS 0xb99f
+#define DHD_TX_POST_CPU_SEMAPHORE_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define RING_CACHE_DHD_TXPOST_MUTEX_ADDRESS 0xb9a0
+#define RING_CACHE_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define RING_CACHE_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define COMMON_DHD_TXPOST_MUTEX_ADDRESS 0xb9a1
+#define COMMON_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define COMMON_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define TXCPL_INT_DHD_TXPOST_MUTEX_ADDRESS 0xb9a2
+#define TXCPL_INT_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define TXCPL_INT_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_ADDRESS 0xb9a3
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_BYTE_SIZE 0x0001
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_ADDRESS 0xb9a4
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_BYTE_SIZE 0x0001
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_LOG2_BYTE_SIZE 0x0001
+/* PRIVATE_B */
+#define US_INGRESS_HANDLER_BUFFER_ADDRESS 0x0000
+#define US_INGRESS_HANDLER_BUFFER_BYTE_SIZE 0x2000
+#define US_INGRESS_HANDLER_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_US_INGRESS_HANDLER_BUFFER_SIZE     32
+#define RDD_US_INGRESS_HANDLER_BUFFER_LOG2_SIZE     5
+#define US_CSO_CHUNK_BUFFER_ADDRESS 0x2000
+#define US_CSO_CHUNK_BUFFER_BYTE_SIZE 0x0080
+#define US_CSO_CHUNK_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define US_CSO_PSEUDO_HEADER_BUFFER_ADDRESS 0x2080
+#define US_CSO_PSEUDO_HEADER_BUFFER_BYTE_SIZE 0x0028
+#define US_CSO_PSEUDO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x20a8
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0008
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     2
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_ADDRESS 0x20b0
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_BYTE_SIZE 0x0010
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_SIZE     8
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_LOG2_SIZE     3
+#define US_CPU_REASON_TO_METER_TABLE_ADDRESS 0x20c0
+#define US_CPU_REASON_TO_METER_TABLE_BYTE_SIZE 0x0040
+#define US_CPU_REASON_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_REASON_TO_METER_TABLE_SIZE     64
+#define RDD_US_CPU_REASON_TO_METER_TABLE_LOG2_SIZE     6
+#define US_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS 0x2100
+#define US_MAIN_PROFILING_BUFFER_RUNNER_BYTE_SIZE 0x0100
+#define US_MAIN_PROFILING_BUFFER_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_LOG2_SIZE     5
+#define US_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS 0x2200
+#define US_FREE_PACKET_DESCRIPTORS_POOL_BYTE_SIZE 0x6000
+#define US_FREE_PACKET_DESCRIPTORS_POOL_LOG2_BYTE_SIZE 0x000f
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE     3072
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_LOG2_SIZE     12
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS 0x8200
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_BYTE_SIZE 0x0180
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE     3
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE2    4
+#define US_QUEUE_PROFILE_TABLE_ADDRESS 0x8380
+#define US_QUEUE_PROFILE_TABLE_BYTE_SIZE 0x0080
+#define US_QUEUE_PROFILE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_QUEUE_PROFILE_TABLE_SIZE     8
+#define RDD_US_QUEUE_PROFILE_TABLE_LOG2_SIZE     3
+#define WAN_CHANNELS_8_39_TABLE_ADDRESS 0x8400
+#define WAN_CHANNELS_8_39_TABLE_BYTE_SIZE 0x0400
+#define WAN_CHANNELS_8_39_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WAN_CHANNELS_8_39_TABLE_SIZE     32
+#define RDD_WAN_CHANNELS_8_39_TABLE_LOG2_SIZE     5
+#define US_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x8800
+#define US_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0180
+#define US_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE     3
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_LOG2_SIZE     2
+#define US_SBPM_REPLY_ADDRESS 0x8980
+#define US_SBPM_REPLY_BYTE_SIZE 0x0080
+#define US_SBPM_REPLY_LOG2_BYTE_SIZE 0x0007
+#define US_POLICER_TABLE_ADDRESS 0x8a00
+#define US_POLICER_TABLE_BYTE_SIZE 0x0100
+#define US_POLICER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_POLICER_TABLE_SIZE     16
+#define RDD_US_POLICER_TABLE_LOG2_SIZE     4
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_ADDRESS 0x8b00
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_BYTE_SIZE 0x0100
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE     2
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_LOG2_SIZE     1
+#define US_WAN_FLOW_TABLE_ADDRESS 0x8c00
+#define US_WAN_FLOW_TABLE_BYTE_SIZE 0x0400
+#define US_WAN_FLOW_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_US_WAN_FLOW_TABLE_SIZE     256
+#define RDD_US_WAN_FLOW_TABLE_LOG2_SIZE     8
+#define US_CPU_TX_BBH_DESCRIPTORS_ADDRESS 0x9000
+#define US_CPU_TX_BBH_DESCRIPTORS_BYTE_SIZE 0x0100
+#define US_CPU_TX_BBH_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_LOG2_SIZE     5
+#define US_FORWARDING_MATRIX_TABLE_ADDRESS 0x9100
+#define US_FORWARDING_MATRIX_TABLE_BYTE_SIZE 0x0090
+#define US_FORWARDING_MATRIX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_US_FORWARDING_MATRIX_TABLE_LOG2_SIZE     4
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE2    16
+#define RDD_US_FORWARDING_MATRIX_TABLE_LOG2_SIZE2    4
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x9190
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0010
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     3
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x91a0
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define DSL_PTM_BOND_TX_HDR_TABLE_ADDRESS 0x91c0
+#define DSL_PTM_BOND_TX_HDR_TABLE_BYTE_SIZE 0x0040
+#define DSL_PTM_BOND_TX_HDR_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DSL_PTM_BOND_TX_HDR_TABLE_SIZE     32
+#define RDD_DSL_PTM_BOND_TX_HDR_TABLE_LOG2_SIZE     5
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_ADDRESS 0x9200
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_BYTE_SIZE 0x0040
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE     8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_SIZE     3
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2    8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_SIZE2    3
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9240
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9280
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS 0x92c0
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define US_RATE_LIMITER_TABLE_ADDRESS 0x9300
+#define US_RATE_LIMITER_TABLE_BYTE_SIZE 0x0080
+#define US_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_RATE_LIMITER_TABLE_SIZE     16
+#define RDD_US_RATE_LIMITER_TABLE_LOG2_SIZE     4
+#define US_CPU_RX_METER_TABLE_ADDRESS 0x9380
+#define US_CPU_RX_METER_TABLE_BYTE_SIZE 0x0080
+#define US_CPU_RX_METER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_RX_METER_TABLE_SIZE     16
+#define RDD_US_CPU_RX_METER_TABLE_LOG2_SIZE     4
+#define US_CONNECTION_CONTEXT_BUFFER_ADDRESS 0x9400
+#define US_CONNECTION_CONTEXT_BUFFER_BYTE_SIZE 0x0400
+#define US_CONNECTION_CONTEXT_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE     8
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS 0x9800
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_SIZE     8
+#define WAN_CHANNELS_0_7_TABLE_ADDRESS 0xa000
+#define WAN_CHANNELS_0_7_TABLE_BYTE_SIZE 0x02c0
+#define WAN_CHANNELS_0_7_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WAN_CHANNELS_0_7_TABLE_SIZE     8
+#define RDD_WAN_CHANNELS_0_7_TABLE_LOG2_SIZE     3
+#define US_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0xa2c0
+#define US_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0040
+#define US_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_L2_UCAST_CONNECTION_BUFFER_SIZE     4
+#define RDD_US_L2_UCAST_CONNECTION_BUFFER_LOG2_SIZE     2
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS 0xa300
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_BYTE_SIZE 0x0080
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_SIZE     5
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0xa380
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define US_PROFILING_BUFFER_PICO_RUNNER_ADDRESS 0xa400
+#define US_PROFILING_BUFFER_PICO_RUNNER_BYTE_SIZE 0x0100
+#define US_PROFILING_BUFFER_PICO_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS 0xa500
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_BYTE_SIZE 0x0080
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_SIZE     4
+#define US_CONNECTION_CACHE_BUFFER_ADDRESS 0xa580
+#define US_CONNECTION_CACHE_BUFFER_BYTE_SIZE 0x0080
+#define US_CONNECTION_CACHE_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CONNECTION_CACHE_BUFFER_SIZE     8
+#define RDD_US_CONNECTION_CACHE_BUFFER_LOG2_SIZE     3
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS 0xa600
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_BYTE_SIZE 0x0060
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE     3
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE2    4
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0xa660
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_ADDRESS 0xa680
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_BYTE_SIZE 0x0060
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define US_FC_L2_UCAST_TUPLE_BUFFER_ADDRESS 0xa6e0
+#define US_FC_L2_UCAST_TUPLE_BUFFER_BYTE_SIZE 0x0020
+#define US_FC_L2_UCAST_TUPLE_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define DHD_RX_POST_FLOW_RING_BUFFER_ADDRESS 0xa700
+#define DHD_RX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x0060
+#define DHD_RX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS 0xa760
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_BYTE_SIZE 0x0020
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_SIZE     2
+#define US_INGRESS_RATE_LIMITER_TABLE_ADDRESS 0xa780
+#define US_INGRESS_RATE_LIMITER_TABLE_BYTE_SIZE 0x0050
+#define US_INGRESS_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE     5
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_LOG2_SIZE     3
+#define DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_ADDRESS 0xa7d0
+#define DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_BYTE_SIZE 0x0010
+#define DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_SIZE     8
+#define RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_LOG2_SIZE     3
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xa7e0
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define US_SPDSVC_CONTEXT_TABLE_ADDRESS 0xa800
+#define US_SPDSVC_CONTEXT_TABLE_BYTE_SIZE 0x0050
+#define US_SPDSVC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0xa850
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0010
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xa860
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define US_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS 0xa880
+#define US_CPU_RX_PICO_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_CPU_RX_PICO_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_ADDRESS 0xa8c0
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_BYTE_SIZE 0x0040
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define US_ROUTER_INGRESS_QUEUE_ADDRESS 0xa900
+#define US_ROUTER_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_ROUTER_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_ROUTER_INGRESS_QUEUE_SIZE     64
+#define RDD_US_ROUTER_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_DHD_TX_POST_HEADER_SCRATCH_ADDRESS 0xa940
+#define US_DHD_TX_POST_HEADER_SCRATCH_BYTE_SIZE 0x0020
+#define US_DHD_TX_POST_HEADER_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS 0xa960
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_BYTE_SIZE 0x0018
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_SIZE     3
+#define US_TOTAL_PPS_RATE_LIMITER_ADDRESS 0xa978
+#define US_TOTAL_PPS_RATE_LIMITER_BYTE_SIZE 0x0008
+#define US_TOTAL_PPS_RATE_LIMITER_LOG2_BYTE_SIZE 0x0003
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xa980
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0001
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define PRIVATE_B_DUMMY_STORE_ADDRESS 0xa981
+#define PRIVATE_B_DUMMY_STORE_BYTE_SIZE 0x0001
+#define PRIVATE_B_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xa982
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_ADDRESS 0xa984
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_BYTE_SIZE 0x0004
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_LOG2_BYTE_SIZE 0x0002
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS 0xa988
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_BYTE_SIZE 0x0001
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xa989
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xa98a
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_ADDRESS 0xa98c
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xa990
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0028
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0006
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE     40
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_LOG2_SIZE     6
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS 0xa9b8
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define US_ONE_BUFFER_ADDRESS 0xa9f8
+#define US_ONE_BUFFER_BYTE_SIZE 0x0008
+#define US_ONE_BUFFER_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS 0xaa00
+#define US_CPU_RX_FAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_CPU_RX_FAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_DEBUG_BUFFER_ADDRESS 0xaa40
+#define US_DEBUG_BUFFER_BYTE_SIZE 0x0080
+#define US_DEBUG_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_DEBUG_BUFFER_SIZE     32
+#define RDD_US_DEBUG_BUFFER_LOG2_SIZE     5
+#define US_FW_MAC_ADDRS_ADDRESS 0xaac0
+#define US_FW_MAC_ADDRS_BYTE_SIZE 0x0080
+#define US_FW_MAC_ADDRS_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_FW_MAC_ADDRS_SIZE     16
+#define RDD_US_FW_MAC_ADDRS_LOG2_SIZE     4
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS 0xab40
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_BYTE_SIZE 0x0018
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE     3
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_SIZE     2
+#define US_NULL_BUFFER_ADDRESS 0xab58
+#define US_NULL_BUFFER_BYTE_SIZE 0x0008
+#define US_NULL_BUFFER_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_PARAMETERS_BLOCK_ADDRESS 0xab60
+#define US_CPU_PARAMETERS_BLOCK_BYTE_SIZE 0x0014
+#define US_CPU_PARAMETERS_BLOCK_LOG2_BYTE_SIZE 0x0005
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xab74
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS 0xab78
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_BYTE_SIZE 0x0008
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_SIZE     3
+#define US_DHD_TX_POST_INGRESS_QUEUE_ADDRESS 0xab80
+#define US_DHD_TX_POST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_DHD_TX_POST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS 0xabc0
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x0030
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RUNNER_FWTRACE_MAINB_PARAM_ADDRESS 0xabf0
+#define RUNNER_FWTRACE_MAINB_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINB_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_LOG2_SIZE     1
+#define US_CPU_TX_FAST_QUEUE_ADDRESS 0xac00
+#define US_CPU_TX_FAST_QUEUE_BYTE_SIZE 0x0080
+#define US_CPU_TX_FAST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_TX_FAST_QUEUE_SIZE     16
+#define RDD_US_CPU_TX_FAST_QUEUE_LOG2_SIZE     4
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_ADDRESS 0xac80
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_BYTE_SIZE 0x0060
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE     48
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_LOG2_SIZE     6
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xace0
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define RUNNER_FWTRACE_PICOB_PARAM_ADDRESS 0xacf0
+#define RUNNER_FWTRACE_PICOB_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_PICOB_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_LOG2_SIZE     1
+#define US_CPU_TX_PICO_QUEUE_ADDRESS 0xad00
+#define US_CPU_TX_PICO_QUEUE_BYTE_SIZE 0x0080
+#define US_CPU_TX_PICO_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_TX_PICO_QUEUE_SIZE     16
+#define RDD_US_CPU_TX_PICO_QUEUE_LOG2_SIZE     4
+#define US_CSO_CONTEXT_TABLE_ADDRESS 0xad80
+#define US_CSO_CONTEXT_TABLE_BYTE_SIZE 0x0054
+#define US_CSO_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define US_BPM_DDR_BUFFERS_BASE_ADDRESS 0xadd4
+#define US_BPM_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS 0xadd8
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_BYTE_SIZE 0x0028
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_BYTE_SIZE 0x0006
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE     40
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_SIZE     6
+#define US_DHD_FLOW_RING_DROP_COUNTER_ADDRESS 0xae00
+#define US_DHD_FLOW_RING_DROP_COUNTER_BYTE_SIZE 0x0014
+#define US_DHD_FLOW_RING_DROP_COUNTER_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_LOG2_SIZE     3
+#define US_CONNECTION_TABLE_CONFIG_ADDRESS 0xae14
+#define US_CONNECTION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONNECTION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ADDRESS 0xae18
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_BYTE_SIZE 0x0006
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xae1e
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xae20
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS 0xae30
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_BYTE_SIZE 0x0010
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_SIZE     3
+#define US_SYSTEM_CONFIGURATION_ADDRESS 0xae40
+#define US_SYSTEM_CONFIGURATION_BYTE_SIZE 0x0024
+#define US_SYSTEM_CONFIGURATION_LOG2_BYTE_SIZE 0x0006
+#define US_CONTEXT_TABLE_CONFIG_ADDRESS 0xae64
+#define US_CONTEXT_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONTEXT_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_ADDRESS 0xae68
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_BYTE_SIZE 0x0020
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_LOG2_SIZE     5
+#define DATA_POINTER_DUMMY_TARGET_ADDRESS 0xae88
+#define DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0008
+#define DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0003
+#define RDD_DATA_POINTER_DUMMY_TARGET_SIZE     2
+#define RDD_DATA_POINTER_DUMMY_TARGET_LOG2_SIZE     1
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS 0xae90
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_BYTE_SIZE 0x0010
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define WAN_TX_SCRATCH_ADDRESS 0xaea0
+#define WAN_TX_SCRATCH_BYTE_SIZE 0x0018
+#define WAN_TX_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define RDD_WAN_TX_SCRATCH_SIZE     24
+#define RDD_WAN_TX_SCRATCH_LOG2_SIZE     5
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_ADDRESS 0xaeb8
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_BYTE_SIZE 0x0012
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE     3
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_SIZE     2
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2    6
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_SIZE2    3
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_ADDRESS 0xaeca
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_BYTE_SIZE 0x0002
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS 0xaecc
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_BYTE_SIZE 0x0004
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_SIZE     2
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_ADDRESS 0xaed0
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_BYTE_SIZE 0x0009
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE     9
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xaed9
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_ADDRESS 0xaeda
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_BYTE_SIZE 0x0002
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_SLAVE_LOCK_ADDRESS 0xaedc
+#define US_PARALLEL_PROCESSING_SLAVE_LOCK_BYTE_SIZE 0x0004
+#define US_PARALLEL_PROCESSING_SLAVE_LOCK_LOG2_BYTE_SIZE 0x0002
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_ADDRESS 0xaee0
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_BYTE_SIZE 0x0010
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_ADDRESS 0xaef0
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_ADDRESS 0xaf00
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_BYTE_SIZE 0x000e
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE     14
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_LOG2_SIZE     4
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_ADDRESS 0xaf0e
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS 0xaf10
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_BYTE_SIZE 0x0004
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_SIZE     2
+#define US_CPU_TX_FLUSH_PAUSE_REQUEST_ADDRESS 0xaf14
+#define US_CPU_TX_FLUSH_PAUSE_REQUEST_BYTE_SIZE 0x0004
+#define US_CPU_TX_FLUSH_PAUSE_REQUEST_LOG2_BYTE_SIZE 0x0002
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS 0xaf18
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_BYTE_SIZE 0x0008
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_SIZE     3
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_ADDRESS 0xaf20
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_BYTE_SIZE 0x0004
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_LOG2_BYTE_SIZE 0x0002
+#define IH_BUFFER_BBH_POINTER_ADDRESS 0xaf24
+#define IH_BUFFER_BBH_POINTER_BYTE_SIZE 0x0004
+#define IH_BUFFER_BBH_POINTER_LOG2_BYTE_SIZE 0x0002
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_ADDRESS 0xaf28
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xaf2c
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS 0xaf30
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_BYTE_SIZE 0x0004
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_SIZE     4
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_SIZE     2
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xaf34
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xaf36
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS 0xaf38
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_BYTE_SIZE 0x0002
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_ANY_SRC_PORT_FLOW_COUNTER_ADDRESS 0xaf3a
+#define US_ANY_SRC_PORT_FLOW_COUNTER_BYTE_SIZE 0x0002
+#define US_ANY_SRC_PORT_FLOW_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_ADDRESS 0xaf3c
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_BYTE_SIZE 0x0004
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_ADDRESS 0xaf40
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_BYTE_SIZE 0x0002
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_LOG2_BYTE_SIZE 0x0001
+#define US_MEMLIB_SEMAPHORE_ADDRESS 0xaf42
+#define US_MEMLIB_SEMAPHORE_BYTE_SIZE 0x0002
+#define US_MEMLIB_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_ADDRESS 0xaf44
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_RUNNER_CONGESTION_STATE_ADDRESS 0xaf46
+#define US_RUNNER_CONGESTION_STATE_BYTE_SIZE 0x0002
+#define US_RUNNER_CONGESTION_STATE_LOG2_BYTE_SIZE 0x0001
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xaf48
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_ADDRESS 0xaf4a
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_BYTE_SIZE 0x0002
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_ADDRESS 0xaf4c
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_BYTE_SIZE 0x0002
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_FC_GLOBAL_CFG_ADDRESS 0xaf4e
+#define US_FC_GLOBAL_CFG_BYTE_SIZE 0x0001
+#define US_FC_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0001
+#define ETHWAN2_SWITCH_PORT_ADDRESS 0xaf4f
+#define ETHWAN2_SWITCH_PORT_BYTE_SIZE 0x0001
+#define ETHWAN2_SWITCH_PORT_LOG2_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_ADDRESS 0xaf50
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_ADDRESS 0xaf51
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_PACKET_BUFFER_SIZE_ASR_8_ADDRESS 0xaf52
+#define US_PACKET_BUFFER_SIZE_ASR_8_BYTE_SIZE 0x0001
+#define US_PACKET_BUFFER_SIZE_ASR_8_LOG2_BYTE_SIZE 0x0001
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xaf53
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xaf54
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_ADDRESS 0xaf55
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_BYTE_SIZE 0x0001
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DSL_PTM_BOND_TX_CONTROL_ADDRESS 0xaf56
+#define DSL_PTM_BOND_TX_CONTROL_BYTE_SIZE 0x0001
+#define DSL_PTM_BOND_TX_CONTROL_LOG2_BYTE_SIZE 0x0001
+#define DSL_BUFFER_ALIGNMENT_ADDRESS 0xaf57
+#define DSL_BUFFER_ALIGNMENT_BYTE_SIZE 0x0001
+#define DSL_BUFFER_ALIGNMENT_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS 0xaf58
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_ADDRESS 0xaf59
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_LOG2_BYTE_SIZE 0x0001
+#define US_IH_CONGESTION_THRESHOLD_ADDRESS 0xaf5a
+#define US_IH_CONGESTION_THRESHOLD_BYTE_SIZE 0x0001
+#define US_IH_CONGESTION_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define US_FW_MAC_ADDRS_COUNT_ADDRESS 0xaf5b
+#define US_FW_MAC_ADDRS_COUNT_BYTE_SIZE 0x0001
+#define US_FW_MAC_ADDRS_COUNT_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_DMA_SYNCHRONIZATION_ADDRESS 0xaf5c
+#define US_DHD_DMA_SYNCHRONIZATION_BYTE_SIZE 0x0001
+#define US_DHD_DMA_SYNCHRONIZATION_LOG2_BYTE_SIZE 0x0001
+#define ETH1_RX_DESCRIPTORS_ADDRESS 0xb200
+#define ETH1_RX_DESCRIPTORS_BYTE_SIZE 0x0100
+#define ETH1_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH1_RX_DESCRIPTORS_SIZE     32
+#define RDD_ETH1_RX_DESCRIPTORS_LOG2_SIZE     5
+#define US_RUNNER_FLOW_IH_RESPONSE_ADDRESS 0xb6f0
+#define US_RUNNER_FLOW_IH_RESPONSE_BYTE_SIZE 0x0008
+#define US_RUNNER_FLOW_IH_RESPONSE_LOG2_BYTE_SIZE 0x0003
+#define BBH_TX_WAN_CHANNEL_INDEX_ADDRESS 0xbcb8
+#define BBH_TX_WAN_CHANNEL_INDEX_BYTE_SIZE 0x0004
+#define BBH_TX_WAN_CHANNEL_INDEX_LOG2_BYTE_SIZE 0x0002
+/* COMMON_A */
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_ADDRESS 0x0000
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_BYTE_SIZE 0x1800
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_LOG2_BYTE_SIZE 0x000d
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE     384
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_LOG2_SIZE     9
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS 0x1800
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define CPU_RX_RUNNER_A_SCRATCHPAD_ADDRESS 0x2000
+#define CPU_RX_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define CPU_RX_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS 0x2800
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define RUNNER_FWTRACE_MAINA_BASE_ADDRESS 0x3000
+#define RUNNER_FWTRACE_MAINA_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_MAINA_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_LOG2_SIZE     7
+#define RUNNER_FWTRACE_PICOA_BASE_ADDRESS 0x3400
+#define RUNNER_FWTRACE_PICOA_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_PICOA_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_LOG2_SIZE     7
+#define WLAN_MCAST_DHD_STATION_TABLE_ADDRESS 0x3800
+#define WLAN_MCAST_DHD_STATION_TABLE_BYTE_SIZE 0x0280
+#define WLAN_MCAST_DHD_STATION_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_LOG2_SIZE     6
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS 0x3a80
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_BYTE_SIZE 0x0080
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE     2
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE     1
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE2    64
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE2    6
+#define MAC_TABLE_CAM_ADDRESS 0x3b00
+#define MAC_TABLE_CAM_BYTE_SIZE 0x0100
+#define MAC_TABLE_CAM_LOG2_BYTE_SIZE 0x0008
+#define RDD_MAC_TABLE_CAM_SIZE     32
+#define RDD_MAC_TABLE_CAM_LOG2_SIZE     5
+#define MAC_TABLE_ADDRESS 0x3c00
+#define MAC_TABLE_BYTE_SIZE 0x0200
+#define MAC_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAC_TABLE_SIZE     64
+#define RDD_MAC_TABLE_LOG2_SIZE     6
+#define ETHWAN2_RX_INGRESS_QUEUE_ADDRESS 0x3e00
+#define ETHWAN2_RX_INGRESS_QUEUE_BYTE_SIZE 0x0100
+#define ETHWAN2_RX_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE     32
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_LOG2_SIZE     5
+#define TRACE_C_TABLE_ADDRESS 0x3f00
+#define TRACE_C_TABLE_BYTE_SIZE 0x0020
+#define TRACE_C_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_TRACE_C_TABLE_SIZE     4
+#define RDD_TRACE_C_TABLE_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_ADDRESS 0x3f20
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_LOG2_SIZE     1
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_ADDRESS 0x3f30
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_ADDRESS 0x3f34
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_LOG2_BYTE_SIZE 0x0002
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_ADDRESS 0x3f38
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_BYTE_SIZE 0x0008
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_LOG2_BYTE_SIZE 0x0003
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE     2
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_LOG2_SIZE     1
+#define BPM_REPLY_RUNNER_A_ADDRESS 0x3f40
+#define BPM_REPLY_RUNNER_A_BYTE_SIZE 0x0030
+#define BPM_REPLY_RUNNER_A_LOG2_BYTE_SIZE 0x0006
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_ADDRESS 0x3f70
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_BYTE_SIZE 0x0010
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define MAC_CONTEXT_TABLE_ADDRESS 0x3f80
+#define MAC_CONTEXT_TABLE_BYTE_SIZE 0x0080
+#define MAC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_MAC_CONTEXT_TABLE_SIZE     64
+#define RDD_MAC_CONTEXT_TABLE_LOG2_SIZE     6
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS 0x4000
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_BYTE_SIZE 0x0600
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_LOG2_BYTE_SIZE 0x000b
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE     32
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS 0x4600
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_BYTE_SIZE 0x0200
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_SIZE     8
+#define WLAN_MCAST_FWD_TABLE_ADDRESS 0x4800
+#define WLAN_MCAST_FWD_TABLE_BYTE_SIZE 0x0200
+#define WLAN_MCAST_FWD_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_FWD_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_FWD_TABLE_LOG2_SIZE     6
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_ADDRESS 0x4a00
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_BYTE_SIZE 0x0200
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_LOG2_SIZE     5
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_ADDRESS 0x4c00
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_BYTE_SIZE 0x0180
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE     48
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_LOG2_SIZE     6
+#define CPU_TX_POST_REQUEST_QUEUE_ADDRESS 0x4d80
+#define CPU_TX_POST_REQUEST_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_POST_REQUEST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE     8
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_LOG2_SIZE     3
+#define WLAN_MCAST_SSID_STATS_TABLE_ADDRESS 0x4e00
+#define WLAN_MCAST_SSID_STATS_TABLE_BYTE_SIZE 0x0180
+#define WLAN_MCAST_SSID_STATS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE     48
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_LOG2_SIZE     6
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_ADDRESS 0x4f80
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_BYTE_SIZE 0x0060
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE     3
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_LOG2_SIZE     2
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS 0x4fe0
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_BYTE_SIZE 0x0020
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_SIZE     4
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS 0x5000
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_SIZE     7
+#define PM_COUNTERS_ADDRESS 0x5800
+#define PM_COUNTERS_BYTE_SIZE 0x1840
+#define PM_COUNTERS_LOG2_BYTE_SIZE 0x000d
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_ADDRESS 0x7040
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_BYTE_SIZE 0x0080
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_LOG2_BYTE_SIZE 0x0007
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE     128
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_LOG2_SIZE     7
+#define INTERRUPT_COALESCING_CONFIG_TABLE_ADDRESS 0x70c0
+#define INTERRUPT_COALESCING_CONFIG_TABLE_BYTE_SIZE 0x0040
+#define INTERRUPT_COALESCING_CONFIG_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE     16
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_LOG2_SIZE     4
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS 0x7100
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_BYTE_SIZE 0x0100
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_LOG2_SIZE     4
+#define DS_CONNECTION_BUFFER_TABLE_ADDRESS 0x7200
+#define DS_CONNECTION_BUFFER_TABLE_BYTE_SIZE 0x0140
+#define DS_CONNECTION_BUFFER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_DS_CONNECTION_BUFFER_TABLE_LOG2_SIZE     3
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2    4
+#define RDD_DS_CONNECTION_BUFFER_TABLE_LOG2_SIZE2    2
+#define MAC_CONTEXT_TABLE_CAM_ADDRESS 0x7340
+#define MAC_CONTEXT_TABLE_CAM_BYTE_SIZE 0x0040
+#define MAC_CONTEXT_TABLE_CAM_LOG2_BYTE_SIZE 0x0006
+#define RDD_MAC_CONTEXT_TABLE_CAM_SIZE     32
+#define RDD_MAC_CONTEXT_TABLE_CAM_LOG2_SIZE     5
+#define DHD_DOORBELL_WRITE_VALUES_ADDRESS 0x7380
+#define DHD_DOORBELL_WRITE_VALUES_BYTE_SIZE 0x0040
+#define DHD_DOORBELL_WRITE_VALUES_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_DOORBELL_WRITE_VALUES_SIZE     16
+#define RDD_DHD_DOORBELL_WRITE_VALUES_LOG2_SIZE     4
+#define DS_DHD_BACKUP_INDEX_CACHE_ADDRESS 0x73c0
+#define DS_DHD_BACKUP_INDEX_CACHE_BYTE_SIZE 0x0040
+#define DS_DHD_BACKUP_INDEX_CACHE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE     32
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_LOG2_SIZE     5
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_ADDRESS 0x7400
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_BYTE_SIZE 0x0100
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_LOG2_SIZE     5
+#define RING_DESCRIPTORS_TABLE_ADDRESS 0x7500
+#define RING_DESCRIPTORS_TABLE_BYTE_SIZE 0x0100
+#define RING_DESCRIPTORS_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_RING_DESCRIPTORS_TABLE_SIZE     16
+#define RDD_RING_DESCRIPTORS_TABLE_LOG2_SIZE     4
+#define MAC_EXTENSION_TABLE_ADDRESS 0x7600
+#define MAC_EXTENSION_TABLE_BYTE_SIZE 0x0040
+#define MAC_EXTENSION_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_MAC_EXTENSION_TABLE_SIZE     64
+#define RDD_MAC_EXTENSION_TABLE_LOG2_SIZE     6
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_ADDRESS 0x7640
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_BYTE_SIZE 0x0020
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE     16
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_LOG2_SIZE     4
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_ADDRESS 0x7660
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0014
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_ADDRESS 0x7674
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_ADDRESS 0x7678
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_BYTE_SIZE 0x0008
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_LOG2_BYTE_SIZE 0x0003
+#define SERVICE_QUEUES_CFG_ADDRESS 0x7680
+#define SERVICE_QUEUES_CFG_BYTE_SIZE 0x0014
+#define SERVICE_QUEUES_CFG_LOG2_BYTE_SIZE 0x0005
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_ADDRESS 0x7694
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_BYTE_SIZE 0x0004
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_LOG2_BYTE_SIZE 0x0002
+#define MAC_EXTENSION_TABLE_CAM_ADDRESS 0x7698
+#define MAC_EXTENSION_TABLE_CAM_BYTE_SIZE 0x0020
+#define MAC_EXTENSION_TABLE_CAM_LOG2_BYTE_SIZE 0x0005
+#define RDD_MAC_EXTENSION_TABLE_CAM_SIZE     32
+#define RDD_MAC_EXTENSION_TABLE_CAM_LOG2_SIZE     5
+#define DS_CAM_DHD_DMA_SCRATCH_ADDRESS 0x76b8
+#define DS_CAM_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_CAM_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_ENQ_DHD_DMA_SCRATCH_ADDRESS 0x76bc
+#define DS_ENQ_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_ENQ_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define PM_COUNTERS_BUFFER_ADDRESS 0x76c0
+#define PM_COUNTERS_BUFFER_BYTE_SIZE 0x0020
+#define PM_COUNTERS_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define TX_CPL_DHD_DMA_SCRATCH_ADDRESS 0x76e0
+#define TX_CPL_DHD_DMA_SCRATCH_BYTE_SIZE 0x000c
+#define TX_CPL_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE     3
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_LOG2_SIZE     2
+#define DS_R2D_DHD_DMA_SCRATCH_ADDRESS 0x76ec
+#define DS_R2D_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_R2D_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_CPU_DHD_DMA_SCRATCH_ADDRESS 0x76f0
+#define DS_CPU_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_CPU_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define TIMER_7_TIMER_PERIOD_ADDRESS 0x76f4
+#define TIMER_7_TIMER_PERIOD_BYTE_SIZE 0x0002
+#define TIMER_7_TIMER_PERIOD_LOG2_BYTE_SIZE 0x0001
+#define INTERRUPT_COALESCING_TIMER_PERIOD_ADDRESS 0x76f6
+#define INTERRUPT_COALESCING_TIMER_PERIOD_BYTE_SIZE 0x0002
+#define INTERRUPT_COALESCING_TIMER_PERIOD_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_POST_BUFFERS_THRESHOLD_ADDRESS 0x76f8
+#define DHD_TX_POST_BUFFERS_THRESHOLD_BYTE_SIZE 0x0006
+#define DHD_TX_POST_BUFFERS_THRESHOLD_LOG2_BYTE_SIZE 0x0003
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_SIZE     3
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_LOG2_SIZE     2
+#define INTERRUPT_COALESCING_TIMER_ARMED_ADDRESS 0x76fe
+#define INTERRUPT_COALESCING_TIMER_ARMED_BYTE_SIZE 0x0002
+#define INTERRUPT_COALESCING_TIMER_ARMED_LOG2_BYTE_SIZE 0x0001
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS 0x7700
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_BYTE_SIZE 0x0004
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_SIZE     4
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_SIZE     2
+#define DHD_TX_POST_BUFFERS_IN_USE_COUNTER_ADDRESS 0x7704
+#define DHD_TX_POST_BUFFERS_IN_USE_COUNTER_BYTE_SIZE 0x0002
+#define DHD_TX_POST_BUFFERS_IN_USE_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define COMMON_A_DUMMY_STORE_ADDRESS 0x7706
+#define COMMON_A_DUMMY_STORE_BYTE_SIZE 0x0001
+#define COMMON_A_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define FC_SERVICE_QUEUE_MODE_ADDRESS 0x7707
+#define FC_SERVICE_QUEUE_MODE_BYTE_SIZE 0x0001
+#define FC_SERVICE_QUEUE_MODE_LOG2_BYTE_SIZE 0x0001
+#define MAIN_A_DEBUG_TRACE_ADDRESS 0x7a00
+#define MAIN_A_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define MAIN_A_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAIN_A_DEBUG_TRACE_SIZE     512
+#define RDD_MAIN_A_DEBUG_TRACE_LOG2_SIZE     9
+#define PICO_A_DEBUG_TRACE_ADDRESS 0x7c00
+#define PICO_A_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define PICO_A_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_PICO_A_DEBUG_TRACE_SIZE     512
+#define RDD_PICO_A_DEBUG_TRACE_LOG2_SIZE     9
+/* COMMON_B */
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS 0x8000
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_SIZE     7
+#define WAN_TX_MIRROR_SCRATCHPAD_ADDRESS 0x8800
+#define WAN_TX_MIRROR_SCRATCHPAD_BYTE_SIZE 0x0800
+#define WAN_TX_MIRROR_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_WAN_TX_MIRROR_SCRATCHPAD_SIZE     8
+#define RDD_WAN_TX_MIRROR_SCRATCHPAD_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS 0x9000
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_BYTE_SIZE 0x0200
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_SIZE     8
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0x9200
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0100
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0008
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     32
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS 0x9300
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_BYTE_SIZE 0x0100
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_SIZE     5
+#define WAN_TX_SERVICE_QUEUES_TABLE_ADDRESS 0x9400
+#define WAN_TX_SERVICE_QUEUES_TABLE_BYTE_SIZE 0x0800
+#define WAN_TX_SERVICE_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE     64
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_LOG2_SIZE     6
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS 0x9c00
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_BYTE_SIZE 0x0100
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_SIZE     5
+#define WAN_TX_RUNNER_B_SCRATCHPAD_ADDRESS 0x9d00
+#define WAN_TX_RUNNER_B_SCRATCHPAD_BYTE_SIZE 0x0100
+#define WAN_TX_RUNNER_B_SCRATCHPAD_LOG2_BYTE_SIZE 0x0008
+#define US_CONNECTION_BUFFER_TABLE_ADDRESS 0x9e00
+#define US_CONNECTION_BUFFER_TABLE_BYTE_SIZE 0x0140
+#define US_CONNECTION_BUFFER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_US_CONNECTION_BUFFER_TABLE_LOG2_SIZE     3
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE2    4
+#define RDD_US_CONNECTION_BUFFER_TABLE_LOG2_SIZE2    2
+#define IPV6_HOST_ADDRESS_CRC_TABLE_ADDRESS 0x9f40
+#define IPV6_HOST_ADDRESS_CRC_TABLE_BYTE_SIZE 0x0040
+#define IPV6_HOST_ADDRESS_CRC_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE     16
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_LOG2_SIZE     4
+#define DHD_BACKUP_INFO_CACHE_TABLE_ADDRESS 0x9f80
+#define DHD_BACKUP_INFO_CACHE_TABLE_BYTE_SIZE 0x0080
+#define DHD_BACKUP_INFO_CACHE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE     16
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_LOG2_SIZE     4
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS 0xa000
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_SIZE     8
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS 0xa800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_SIZE     8
+#define WAN_TX_QUEUES_TABLE_ADDRESS 0xb000
+#define WAN_TX_QUEUES_TABLE_BYTE_SIZE 0x1000
+#define WAN_TX_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000c
+#define RDD_WAN_TX_QUEUES_TABLE_SIZE     256
+#define RDD_WAN_TX_QUEUES_TABLE_LOG2_SIZE     8
+#define RUNNER_FWTRACE_MAINB_BASE_ADDRESS 0xc000
+#define RUNNER_FWTRACE_MAINB_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_MAINB_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_LOG2_SIZE     7
+#define US_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS 0xc400
+#define US_RING_PACKET_DESCRIPTORS_CACHE_BYTE_SIZE 0x0100
+#define US_RING_PACKET_DESCRIPTORS_CACHE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_LOG2_SIZE     4
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_ADDRESS 0xc500
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_BYTE_SIZE 0x00c0
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE     3
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_LOG2_SIZE     2
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_ADDRESS 0xc5c0
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_BYTE_SIZE 0x0040
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0006
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_ADDRESS 0xc600
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_BYTE_SIZE 0x0100
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE     16
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_LOG2_SIZE     4
+#define FC_FLOW_IP_ADDRESSES_TABLE_ADDRESS 0xc700
+#define FC_FLOW_IP_ADDRESSES_TABLE_BYTE_SIZE 0x00c0
+#define FC_FLOW_IP_ADDRESSES_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE     4
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_ADDRESS 0xc7c0
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_LOG2_SIZE     1
+#define BPM_REPLY_RUNNER_B_ADDRESS 0xc7d0
+#define BPM_REPLY_RUNNER_B_BYTE_SIZE 0x0030
+#define BPM_REPLY_RUNNER_B_LOG2_BYTE_SIZE 0x0006
+#define US_RATE_CONTROLLERS_TABLE_ADDRESS 0xc800
+#define US_RATE_CONTROLLERS_TABLE_BYTE_SIZE 0x1800
+#define US_RATE_CONTROLLERS_TABLE_LOG2_BYTE_SIZE 0x000d
+#define RDD_US_RATE_CONTROLLERS_TABLE_SIZE     128
+#define RDD_US_RATE_CONTROLLERS_TABLE_LOG2_SIZE     7
+#define CPU_RX_RUNNER_B_SCRATCHPAD_ADDRESS 0xe000
+#define CPU_RX_RUNNER_B_SCRATCHPAD_BYTE_SIZE 0x0800
+#define CPU_RX_RUNNER_B_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE     8
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_LOG2_SIZE     3
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS 0xe800
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_BYTE_SIZE 0x0050
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_BYTE_SIZE 0x0007
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     40
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_SIZE     6
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_ADDRESS 0xe850
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_BYTE_SIZE 0x0010
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_LOG2_BYTE_SIZE 0x0004
+#define IPV4_HOST_ADDRESS_TABLE_ADDRESS 0xe860
+#define IPV4_HOST_ADDRESS_TABLE_BYTE_SIZE 0x0020
+#define IPV4_HOST_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPV4_HOST_ADDRESS_TABLE_SIZE     8
+#define RDD_IPV4_HOST_ADDRESS_TABLE_LOG2_SIZE     3
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS 0xe880
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_BYTE_SIZE 0x0050
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_BYTE_SIZE 0x0007
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     40
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_SIZE     6
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS 0xe8d0
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_BYTE_SIZE 0x0080
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE     2
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE     1
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE2    64
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE2    6
+#define US_DHD_BACKUP_ENTRY_SCRATCH_ADDRESS 0xe950
+#define US_DHD_BACKUP_ENTRY_SCRATCH_BYTE_SIZE 0x0010
+#define US_DHD_BACKUP_ENTRY_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS 0xe960
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_BYTE_SIZE 0x0020
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_SIZE     4
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_ADDRESS 0xe980
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_BYTE_SIZE 0x0080
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_LOG2_BYTE_SIZE 0x0007
+#define MAIN_B_DEBUG_TRACE_ADDRESS 0xea00
+#define MAIN_B_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define MAIN_B_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAIN_B_DEBUG_TRACE_SIZE     512
+#define RDD_MAIN_B_DEBUG_TRACE_LOG2_SIZE     9
+#define PICO_B_DEBUG_TRACE_ADDRESS 0xec00
+#define PICO_B_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define PICO_B_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_PICO_B_DEBUG_TRACE_SIZE     512
+#define RDD_PICO_B_DEBUG_TRACE_LOG2_SIZE     9
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_ADDRESS 0xee00
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_BYTE_SIZE 0x0080
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_LOG2_BYTE_SIZE 0x0007
+#define LAN0_INGRESS_FIFO_ADDRESS 0xee80
+#define LAN0_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN0_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN5_INGRESS_FIFO_ADDRESS 0xeec0
+#define LAN5_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN5_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN1_INGRESS_FIFO_ADDRESS 0xef00
+#define LAN1_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN1_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN6_INGRESS_FIFO_ADDRESS 0xef40
+#define LAN6_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN6_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN2_INGRESS_FIFO_ADDRESS 0xef80
+#define LAN2_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN2_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN7_INGRESS_FIFO_ADDRESS 0xefc0
+#define LAN7_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN7_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define RUNNER_FWTRACE_PICOB_BASE_ADDRESS 0xf000
+#define RUNNER_FWTRACE_PICOB_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_PICOB_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_LOG2_SIZE     7
+#define LAN3_INGRESS_FIFO_ADDRESS 0xf400
+#define LAN3_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN3_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define US_DHD_BACKUP_INDEX_CACHE_ADDRESS 0xf440
+#define US_DHD_BACKUP_INDEX_CACHE_BYTE_SIZE 0x0040
+#define US_DHD_BACKUP_INDEX_CACHE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE     32
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_LOG2_SIZE     5
+#define LAN4_INGRESS_FIFO_ADDRESS 0xf480
+#define LAN4_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN4_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define DHD_DOORBELL_COUNTERS_ADDRESS 0xf4c0
+#define DHD_DOORBELL_COUNTERS_BYTE_SIZE 0x0030
+#define DHD_DOORBELL_COUNTERS_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_DOORBELL_COUNTERS_SIZE     48
+#define RDD_DHD_DOORBELL_COUNTERS_LOG2_SIZE     6
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ADDRESS 0xf4f0
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_BYTE_SIZE 0x0010
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_LOG2_BYTE_SIZE 0x0004
+#define WAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0xf500
+#define WAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define WAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_ADDRESS 0xf540
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0014
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define US_CAM_DHD_DMA_SCRATCH_ADDRESS 0xf554
+#define US_CAM_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_CAM_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_DHD_BACKUP_FLUSH_SCRATCH_ADDRESS 0xf558
+#define US_DHD_BACKUP_FLUSH_SCRATCH_BYTE_SIZE 0x0008
+#define US_DHD_BACKUP_FLUSH_SCRATCH_LOG2_BYTE_SIZE 0x0003
+#define US_ENQ_DHD_DMA_SCRATCH_ADDRESS 0xf560
+#define US_ENQ_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_ENQ_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_R2D_DHD_DMA_SCRATCH_ADDRESS 0xf564
+#define US_R2D_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_R2D_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_ADDRESS 0xf568
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_BYTE_SIZE 0x0004
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE     4
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_LOG2_SIZE     2
+#define COMMON_B_DUMMY_STORE_ADDRESS 0xf56c
+#define COMMON_B_DUMMY_STORE_BYTE_SIZE 0x0001
+#define COMMON_B_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_ADDRESS 0xf56d
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_BYTE_SIZE 0x0001
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_LOG2_BYTE_SIZE 0x0001
+/* DDR */
+#define BPM_PACKET_BUFFERS_ADDRESS 0x0000
+#define BPM_PACKET_BUFFERS_BYTE_SIZE 0xf00000
+#define BPM_PACKET_BUFFERS_LOG2_BYTE_SIZE 0x0018
+#define RDD_BPM_PACKET_BUFFERS_SIZE     7680
+#define RDD_BPM_PACKET_BUFFERS_LOG2_SIZE     13
+#define DS_CONNECTION_TABLE_ADDRESS 0x0000
+#define DS_CONNECTION_TABLE_BYTE_SIZE 0x80000
+#define DS_CONNECTION_TABLE_LOG2_BYTE_SIZE 0x0013
+#define RDD_DS_CONNECTION_TABLE_SIZE     32768
+#define RDD_DS_CONNECTION_TABLE_LOG2_SIZE     15
+#define US_CONNECTION_TABLE_ADDRESS 0x80000
+#define US_CONNECTION_TABLE_BYTE_SIZE 0x80000
+#define US_CONNECTION_TABLE_LOG2_BYTE_SIZE 0x0013
+#define RDD_US_CONNECTION_TABLE_SIZE     32768
+#define RDD_US_CONNECTION_TABLE_LOG2_SIZE     15
+#define CONTEXT_TABLE_ADDRESS 0x100000
+#define CONTEXT_TABLE_BYTE_SIZE 0x214200
+#define CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0016
+#define RDD_CONTEXT_TABLE_SIZE     16512
+#define RDD_CONTEXT_TABLE_LOG2_SIZE     15
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_ADDRESS 0x5d1500
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_BYTE_SIZE 0x00a0
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE     8
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_LOG2_SIZE     3
+#define DHD_RX_POST_DDR_BUFFER_ADDRESS 0x5c1100
+#define DHD_RX_POST_DDR_BUFFER_BYTE_SIZE 0x8000
+#define DHD_RX_POST_DDR_BUFFER_LOG2_BYTE_SIZE 0x000f
+#define RDD_DHD_RX_POST_DDR_BUFFER_SIZE     1024
+#define RDD_DHD_RX_POST_DDR_BUFFER_LOG2_SIZE     10
+#define DHD_RX_COMPLETE_DDR_BUFFER_ADDRESS 0x5c9100
+#define DHD_RX_COMPLETE_DDR_BUFFER_BYTE_SIZE 0x8000
+#define DHD_RX_COMPLETE_DDR_BUFFER_LOG2_BYTE_SIZE 0x000f
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE     1024
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_LOG2_SIZE     10
+#define DHD_TX_POST_DDR_BUFFER_ADDRESS 0x5d15a0
+#define DHD_TX_POST_DDR_BUFFER_BYTE_SIZE 0x1800
+#define DHD_TX_POST_DDR_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE     8
+#define RDD_DHD_TX_POST_DDR_BUFFER_LOG2_SIZE     3
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE2    16
+#define RDD_DHD_TX_POST_DDR_BUFFER_LOG2_SIZE2    4
+#define DHD_TX_COMPLETE_DDR_BUFFER_ADDRESS 0x5d2da0
+#define DHD_TX_COMPLETE_DDR_BUFFER_BYTE_SIZE 0x0100
+#define DHD_TX_COMPLETE_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE     16
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_LOG2_SIZE     4
+#define R2D_WR_ARR_DDR_BUFFER_ADDRESS 0x5d1100
+#define R2D_WR_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define R2D_WR_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_R2D_WR_ARR_DDR_BUFFER_SIZE     128
+#define RDD_R2D_WR_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define D2R_RD_ARR_DDR_BUFFER_ADDRESS 0x5d1200
+#define D2R_RD_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define D2R_RD_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_D2R_RD_ARR_DDR_BUFFER_SIZE     128
+#define RDD_D2R_RD_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define R2D_RD_ARR_DDR_BUFFER_ADDRESS 0x5d1300
+#define R2D_RD_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define R2D_RD_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_R2D_RD_ARR_DDR_BUFFER_SIZE     128
+#define RDD_R2D_RD_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define D2R_WR_ARR_DDR_BUFFER_ADDRESS 0x5d1400
+#define D2R_WR_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define D2R_WR_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_D2R_WR_ARR_DDR_BUFFER_SIZE     128
+#define RDD_D2R_WR_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define DHD_BACKUP_QUEUES_BUFFER_ADDRESS 0x600000
+#define DHD_BACKUP_QUEUES_BUFFER_BYTE_SIZE 0x100000
+#define DHD_BACKUP_QUEUES_BUFFER_LOG2_BYTE_SIZE 0x0014
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE     524288
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_LOG2_SIZE     19
+#define WLAN_MCAST_DHD_LIST_TABLE_ADDRESS 0x5c0000
+#define WLAN_MCAST_DHD_LIST_TABLE_BYTE_SIZE 0x1000
+#define WLAN_MCAST_DHD_LIST_TABLE_LOG2_BYTE_SIZE 0x000c
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_LOG2_SIZE     6
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_ADDRESS 0x5c1000
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_BYTE_SIZE 0x0001
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_LOG2_BYTE_SIZE 0x0001
+/* PSRAM */
+#endif
+#ifdef DSL_63148
+/* PRIVATE_A */
+#define INGRESS_HANDLER_BUFFER_ADDRESS 0x0000
+#define INGRESS_HANDLER_BUFFER_BYTE_SIZE 0x2000
+#define INGRESS_HANDLER_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_INGRESS_HANDLER_BUFFER_SIZE     32
+#define RDD_INGRESS_HANDLER_BUFFER_LOG2_SIZE     5
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS 0x2000
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_BYTE_SIZE 0x4000
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_LOG2_BYTE_SIZE 0x000e
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE     2048
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_LOG2_SIZE     11
+#define DS_CONNECTION_CONTEXT_BUFFER_ADDRESS 0x6000
+#define DS_CONNECTION_CONTEXT_BUFFER_BYTE_SIZE 0x0400
+#define DS_CONNECTION_CONTEXT_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_LOG2_SIZE     3
+#define DS_GSO_HEADER_BUFFER_ADDRESS 0x6400
+#define DS_GSO_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_GSO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_GSO_PSEUDO_HEADER_BUFFER_ADDRESS 0x6480
+#define DS_GSO_PSEUDO_HEADER_BUFFER_BYTE_SIZE 0x0028
+#define DS_GSO_PSEUDO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x64a8
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0008
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     2
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_ADDRESS 0x64b0
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_BYTE_SIZE 0x0010
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_SIZE     8
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_LOG2_SIZE     3
+#define DS_CPU_REASON_TO_METER_TABLE_ADDRESS 0x64c0
+#define DS_CPU_REASON_TO_METER_TABLE_BYTE_SIZE 0x0040
+#define DS_CPU_REASON_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE     64
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_LOG2_SIZE     6
+#define DS_GSO_CHUNK_BUFFER_ADDRESS 0x6500
+#define DS_GSO_CHUNK_BUFFER_BYTE_SIZE 0x0080
+#define DS_GSO_CHUNK_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_CPU_RX_METER_TABLE_ADDRESS 0x6580
+#define DS_CPU_RX_METER_TABLE_BYTE_SIZE 0x0080
+#define DS_CPU_RX_METER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_CPU_RX_METER_TABLE_SIZE     16
+#define RDD_DS_CPU_RX_METER_TABLE_LOG2_SIZE     4
+#define DS_POLICER_TABLE_ADDRESS 0x6600
+#define DS_POLICER_TABLE_BYTE_SIZE 0x0100
+#define DS_POLICER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_POLICER_TABLE_SIZE     16
+#define RDD_DS_POLICER_TABLE_LOG2_SIZE     4
+#define IPSEC_DS_BUFFER_POOL_ADDRESS 0x6700
+#define IPSEC_DS_BUFFER_POOL_BYTE_SIZE 0x0160
+#define IPSEC_DS_BUFFER_POOL_LOG2_BYTE_SIZE 0x0009
+#define RDD_IPSEC_DS_BUFFER_POOL_SIZE     2
+#define RDD_IPSEC_DS_BUFFER_POOL_LOG2_SIZE     1
+#define IPSEC_DS_SA_DESC_TABLE_ADDRESS 0x6860
+#define IPSEC_DS_SA_DESC_TABLE_BYTE_SIZE 0x0500
+#define IPSEC_DS_SA_DESC_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_IPSEC_DS_SA_DESC_TABLE_SIZE     16
+#define RDD_IPSEC_DS_SA_DESC_TABLE_LOG2_SIZE     4
+#define IPSEC_US_SA_DESC_TABLE_ADDRESS 0x6d60
+#define IPSEC_US_SA_DESC_TABLE_BYTE_SIZE 0x0500
+#define IPSEC_US_SA_DESC_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_IPSEC_US_SA_DESC_TABLE_SIZE     16
+#define RDD_IPSEC_US_SA_DESC_TABLE_LOG2_SIZE     4
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_ADDRESS 0x7260
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_BYTE_SIZE 0x0300
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_LOG2_SIZE     5
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x7560
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define DS_SPDSVC_CONTEXT_TABLE_ADDRESS 0x7580
+#define DS_SPDSVC_CONTEXT_TABLE_BYTE_SIZE 0x0050
+#define DS_SPDSVC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x75d0
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0010
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     3
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS 0x75e0
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_BYTE_SIZE 0x0100
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_LOG2_SIZE     5
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x76e0
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define WLAN_MCAST_CONTROL_TABLE_ADDRESS 0x7700
+#define WLAN_MCAST_CONTROL_TABLE_BYTE_SIZE 0x0094
+#define WLAN_MCAST_CONTROL_TABLE_LOG2_BYTE_SIZE 0x0008
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_ADDRESS 0x7794
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_BYTE_SIZE 0x0004
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DS_TOTAL_PPS_RATE_LIMITER_ADDRESS 0x7798
+#define DS_TOTAL_PPS_RATE_LIMITER_BYTE_SIZE 0x0008
+#define DS_TOTAL_PPS_RATE_LIMITER_LOG2_BYTE_SIZE 0x0003
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS 0x77a0
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_BYTE_SIZE 0x0020
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE     1
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE2    4
+#define RATE_LIMITER_REMAINDER_TABLE_ADDRESS 0x77c0
+#define RATE_LIMITER_REMAINDER_TABLE_BYTE_SIZE 0x0040
+#define RATE_LIMITER_REMAINDER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE     32
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS 0x7800
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_SIZE     8
+#define FC_MCAST_CONNECTION2_TABLE_ADDRESS 0x8000
+#define FC_MCAST_CONNECTION2_TABLE_BYTE_SIZE 0x0800
+#define FC_MCAST_CONNECTION2_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_FC_MCAST_CONNECTION2_TABLE_SIZE     128
+#define RDD_FC_MCAST_CONNECTION2_TABLE_LOG2_SIZE     7
+#define ETH_TX_QUEUES_POINTERS_TABLE_ADDRESS 0x8800
+#define ETH_TX_QUEUES_POINTERS_TABLE_BYTE_SIZE 0x0120
+#define ETH_TX_QUEUES_POINTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE     72
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_LOG2_SIZE     7
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_ADDRESS 0x8920
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_BYTE_SIZE 0x0020
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS 0x8940
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define SBPM_REPLY_ADDRESS 0x8980
+#define SBPM_REPLY_BYTE_SIZE 0x0080
+#define SBPM_REPLY_LOG2_BYTE_SIZE 0x0007
+#define ETH_TX_QUEUES_TABLE_ADDRESS 0x8a00
+#define ETH_TX_QUEUES_TABLE_BYTE_SIZE 0x0480
+#define ETH_TX_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_ETH_TX_QUEUES_TABLE_SIZE     72
+#define RDD_ETH_TX_QUEUES_TABLE_LOG2_SIZE     7
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS 0x8e80
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_BYTE_SIZE 0x0080
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE     1
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE2    4
+#define DS_FORWARDING_MATRIX_TABLE_ADDRESS 0x8f00
+#define DS_FORWARDING_MATRIX_TABLE_BYTE_SIZE 0x0090
+#define DS_FORWARDING_MATRIX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_DS_FORWARDING_MATRIX_TABLE_LOG2_SIZE     4
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2    16
+#define RDD_DS_FORWARDING_MATRIX_TABLE_LOG2_SIZE2    4
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0x8f90
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0010
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS 0x8fa0
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_BYTE_SIZE 0x0020
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_SIZE     2
+#define DS_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0x8fc0
+#define DS_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0040
+#define DS_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_L2_UCAST_CONNECTION_BUFFER_SIZE     4
+#define RDD_DS_L2_UCAST_CONNECTION_BUFFER_LOG2_SIZE     2
+#define ETH_TX_MAC_TABLE_ADDRESS 0x9000
+#define ETH_TX_MAC_TABLE_BYTE_SIZE 0x0140
+#define ETH_TX_MAC_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_ETH_TX_MAC_TABLE_SIZE     10
+#define RDD_ETH_TX_MAC_TABLE_LOG2_SIZE     4
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_ADDRESS 0x9140
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_BYTE_SIZE 0x0030
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINA_PARAM_ADDRESS 0x9170
+#define RUNNER_FWTRACE_MAINA_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINA_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_LOG2_SIZE     1
+#define INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS 0x9180
+#define INGRESS_HANDLER_SKB_DATA_POINTER_BYTE_SIZE 0x0080
+#define INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_SIZE     5
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0x9200
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9240
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9280
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_ADDRESS 0x92c0
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0030
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE     3
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_LOG2_SIZE     2
+#define RUNNER_FWTRACE_PICOA_PARAM_ADDRESS 0x92f0
+#define RUNNER_FWTRACE_PICOA_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_PICOA_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_LOG2_SIZE     1
+#define DS_RATE_LIMITER_TABLE_ADDRESS 0x9300
+#define DS_RATE_LIMITER_TABLE_BYTE_SIZE 0x0100
+#define DS_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_RATE_LIMITER_TABLE_SIZE     32
+#define RDD_DS_RATE_LIMITER_TABLE_LOG2_SIZE     5
+#define DS_WAN_FLOW_TABLE_ADDRESS 0x9400
+#define DS_WAN_FLOW_TABLE_BYTE_SIZE 0x0200
+#define DS_WAN_FLOW_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_WAN_FLOW_TABLE_SIZE     256
+#define RDD_DS_WAN_FLOW_TABLE_LOG2_SIZE     8
+#define DS_WAN_UDP_FILTER_TABLE_ADDRESS 0x9600
+#define DS_WAN_UDP_FILTER_TABLE_BYTE_SIZE 0x0200
+#define DS_WAN_UDP_FILTER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_WAN_UDP_FILTER_TABLE_SIZE     32
+#define RDD_DS_WAN_UDP_FILTER_TABLE_LOG2_SIZE     5
+#define FC_MCAST_PORT_HEADER_BUFFER_ADDRESS 0x9800
+#define FC_MCAST_PORT_HEADER_BUFFER_BYTE_SIZE 0x0200
+#define FC_MCAST_PORT_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE     8
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_LOG2_SIZE     3
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2    64
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_LOG2_SIZE2    6
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_ADDRESS 0x9a00
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_BYTE_SIZE 0x0200
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_LOG2_SIZE     3
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_ADDRESS 0x9c00
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_BYTE_SIZE 0x0200
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_LOG2_BYTE_SIZE 0x0009
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE     64
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_LOG2_SIZE     6
+#define ETH0_RX_DESCRIPTORS_ADDRESS 0x9e00
+#define ETH0_RX_DESCRIPTORS_BYTE_SIZE 0x0100
+#define ETH0_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH0_RX_DESCRIPTORS_SIZE     32
+#define RDD_ETH0_RX_DESCRIPTORS_LOG2_SIZE     5
+#define DS_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x9f00
+#define DS_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x9f80
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_ADDRESS 0xa000
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_BYTE_SIZE 0x0200
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE     64
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_CPU_TX_BBH_DESCRIPTORS_ADDRESS 0xa200
+#define DS_CPU_TX_BBH_DESCRIPTORS_BYTE_SIZE 0x0100
+#define DS_CPU_TX_BBH_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_LOG2_SIZE     5
+#define DS_PROFILING_BUFFER_PICO_RUNNER_ADDRESS 0xa300
+#define DS_PROFILING_BUFFER_PICO_RUNNER_BYTE_SIZE 0x0100
+#define DS_PROFILING_BUFFER_PICO_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define GSO_PICO_QUEUE_ADDRESS 0xa400
+#define GSO_PICO_QUEUE_BYTE_SIZE 0x0200
+#define GSO_PICO_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_GSO_PICO_QUEUE_SIZE     64
+#define RDD_GSO_PICO_QUEUE_LOG2_SIZE     6
+#define DHD_TX_POST_PD_INGRESS_QUEUE_ADDRESS 0xa600
+#define DHD_TX_POST_PD_INGRESS_QUEUE_BYTE_SIZE 0x0100
+#define DHD_TX_POST_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_SIZE     32
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS 0xa700
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_BYTE_SIZE 0x0080
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_SIZE     4
+#define DS_CONNECTION_CACHE_BUFFER_ADDRESS 0xa780
+#define DS_CONNECTION_CACHE_BUFFER_BYTE_SIZE 0x0080
+#define DS_CONNECTION_CACHE_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_CONNECTION_CACHE_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CACHE_BUFFER_LOG2_SIZE     3
+#define IPSEC_DS_QUEUE_ADDRESS 0xa800
+#define IPSEC_DS_QUEUE_BYTE_SIZE 0x0200
+#define IPSEC_DS_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_IPSEC_DS_QUEUE_SIZE     64
+#define RDD_IPSEC_DS_QUEUE_LOG2_SIZE     6
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS 0xaa00
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x00c0
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE     4
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_ADDRESS 0xaac0
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_BYTE_SIZE 0x0040
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0xab00
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     16
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     4
+#define ETH_TX_LOCAL_REGISTERS_ADDRESS 0xab80
+#define ETH_TX_LOCAL_REGISTERS_BYTE_SIZE 0x0048
+#define ETH_TX_LOCAL_REGISTERS_LOG2_BYTE_SIZE 0x0007
+#define RDD_ETH_TX_LOCAL_REGISTERS_SIZE     9
+#define RDD_ETH_TX_LOCAL_REGISTERS_LOG2_SIZE     4
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS 0xabc8
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_BYTE_SIZE 0x0008
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_SIZE     1
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS 0xabd0
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_BYTE_SIZE 0x0010
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_BYTE_SIZE 0x0004
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     8
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_SIZE     3
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xabe0
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define CPU_TX_FAST_QUEUE_ADDRESS 0xac00
+#define CPU_TX_FAST_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_FAST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_FAST_QUEUE_SIZE     16
+#define RDD_CPU_TX_FAST_QUEUE_LOG2_SIZE     4
+#define DS_QUEUE_PROFILE_TABLE_ADDRESS 0xac80
+#define DS_QUEUE_PROFILE_TABLE_BYTE_SIZE 0x0080
+#define DS_QUEUE_PROFILE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_QUEUE_PROFILE_TABLE_SIZE     8
+#define RDD_DS_QUEUE_PROFILE_TABLE_LOG2_SIZE     3
+#define CPU_TX_PICO_QUEUE_ADDRESS 0xad00
+#define CPU_TX_PICO_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_PICO_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_PICO_QUEUE_SIZE     16
+#define RDD_CPU_TX_PICO_QUEUE_LOG2_SIZE     4
+#define DS_SQ_ENQUEUE_QUEUE_ADDRESS 0xad80
+#define DS_SQ_ENQUEUE_QUEUE_BYTE_SIZE 0x0040
+#define DS_SQ_ENQUEUE_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_SQ_ENQUEUE_QUEUE_SIZE     64
+#define RDD_DS_SQ_ENQUEUE_QUEUE_LOG2_SIZE     6
+#define MULTICAST_HEADER_BUFFER_ADDRESS 0xadc0
+#define MULTICAST_HEADER_BUFFER_BYTE_SIZE 0x0040
+#define MULTICAST_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_ADDRESS 0xae00
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_BYTE_SIZE 0x0080
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE     16
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_LOG2_SIZE     4
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS 0xae80
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xaec0
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define DS_NULL_BUFFER_ADDRESS 0xaee0
+#define DS_NULL_BUFFER_BYTE_SIZE 0x0018
+#define DS_NULL_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_NULL_BUFFER_SIZE     3
+#define RDD_DS_NULL_BUFFER_LOG2_SIZE     2
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS 0xaef8
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_BYTE_SIZE 0x0008
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0003
+#define CPU_RX_PD_INGRESS_QUEUE_ADDRESS 0xaf00
+#define CPU_RX_PD_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define CPU_RX_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE     16
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_LOG2_SIZE     4
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_ADDRESS 0xaf80
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE     64
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS 0xafc0
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_ADDRESS 0xb000
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE     16
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_LOG2_SIZE     4
+#define DS_ROUTER_INGRESS_QUEUE_ADDRESS 0xb080
+#define DS_ROUTER_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_ROUTER_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_ROUTER_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_ROUTER_INGRESS_QUEUE_LOG2_SIZE     6
+#define DHD_COMPLETE_RING_BUFFER_ADDRESS 0xb0c0
+#define DHD_COMPLETE_RING_BUFFER_BYTE_SIZE 0x0018
+#define DHD_COMPLETE_RING_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DHD_COMPLETE_RING_BUFFER_SIZE     3
+#define RDD_DHD_COMPLETE_RING_BUFFER_LOG2_SIZE     2
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS 0xb0d8
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_BYTE_SIZE 0x0008
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_SIZE     3
+#define DS_CPU_PARAMETERS_BLOCK_ADDRESS 0xb0e0
+#define DS_CPU_PARAMETERS_BLOCK_BYTE_SIZE 0x0014
+#define DS_CPU_PARAMETERS_BLOCK_LOG2_BYTE_SIZE 0x0005
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_ADDRESS 0xb0f4
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_ADDRESS 0xb0f8
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_BYTE_SIZE 0x0006
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xb0fe
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_TX_POST_HEADER_SCRATCH_ADDRESS 0xb100
+#define DS_DHD_TX_POST_HEADER_SCRATCH_BYTE_SIZE 0x0080
+#define DS_DHD_TX_POST_HEADER_SCRATCH_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE     4
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_LOG2_SIZE     2
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS 0xb180
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_BYTE_SIZE 0x00a0
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_LOG2_BYTE_SIZE 0x0008
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE     5
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_LOG2_SIZE     3
+#define FC_MCAST_CONNECTION_TABLE_PLUS_ADDRESS 0xb220
+#define FC_MCAST_CONNECTION_TABLE_PLUS_BYTE_SIZE 0x0014
+#define FC_MCAST_CONNECTION_TABLE_PLUS_LOG2_BYTE_SIZE 0x0005
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xb234
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_BPM_DDR_BUFFERS_BASE_ADDRESS 0xb238
+#define DS_BPM_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_CONNECTION_TABLE_CONFIG_ADDRESS 0xb23c
+#define DS_CONNECTION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONNECTION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define DS_DATA_POINTER_DUMMY_TARGET_ADDRESS 0xb240
+#define DS_DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0014
+#define DS_DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE     5
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_LOG2_SIZE     3
+#define DS_CONTEXT_TABLE_CONFIG_ADDRESS 0xb254
+#define DS_CONTEXT_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONTEXT_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS 0xb258
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_BYTE_SIZE 0x0004
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_SIZE     2
+#define DS_PARALLEL_PROCESSING_SLAVE_LOCK_ADDRESS 0xb25c
+#define DS_PARALLEL_PROCESSING_SLAVE_LOCK_BYTE_SIZE 0x0004
+#define DS_PARALLEL_PROCESSING_SLAVE_LOCK_LOG2_BYTE_SIZE 0x0002
+#define SERVICE_QUEUES_WLAN_SCRATCH_ADDRESS 0xb260
+#define SERVICE_QUEUES_WLAN_SCRATCH_BYTE_SIZE 0x0014
+#define SERVICE_QUEUES_WLAN_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define DS_CPU_TX_FLUSH_PAUSE_REQUEST_ADDRESS 0xb274
+#define DS_CPU_TX_FLUSH_PAUSE_REQUEST_BYTE_SIZE 0x0004
+#define DS_CPU_TX_FLUSH_PAUSE_REQUEST_LOG2_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS 0xb278
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_BYTE_SIZE 0x0004
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_SIZE     2
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_ADDRESS 0xb27c
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_BYTE_SIZE 0x0004
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_LOG2_BYTE_SIZE 0x0002
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS 0xb280
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xb2c0
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0050
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE     10
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_LOG2_SIZE     4
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ADDRESS 0xb310
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_BYTE_SIZE 0x000a
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0004
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xb31a
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_ADDRESS 0xb31c
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define DS_DEBUG_BUFFER_ADDRESS 0xb320
+#define DS_DEBUG_BUFFER_BYTE_SIZE 0x0080
+#define DS_DEBUG_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_DEBUG_BUFFER_SIZE     32
+#define RDD_DS_DEBUG_BUFFER_LOG2_SIZE     5
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb3a0
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS 0xb3b0
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_BYTE_SIZE 0x0010
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_BYTE_SIZE 0x0004
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     8
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_SIZE     3
+#define DS_DHD_FLOW_RING_DROP_COUNTER_ADDRESS 0xb3c0
+#define DS_DHD_FLOW_RING_DROP_COUNTER_BYTE_SIZE 0x0014
+#define DS_DHD_FLOW_RING_DROP_COUNTER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_LOG2_SIZE     3
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xb3d4
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS 0xb3d8
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_BYTE_SIZE 0x0008
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_SIZE     3
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb3e0
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define HASH_BUFFER_ADDRESS 0xb3f0
+#define HASH_BUFFER_BYTE_SIZE 0x0010
+#define HASH_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define GPON_RX_DIRECT_DESCRIPTORS_ADDRESS 0xb400
+#define GPON_RX_DIRECT_DESCRIPTORS_BYTE_SIZE 0x0100
+#define GPON_RX_DIRECT_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE     32
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_LOG2_SIZE     5
+#define DS_GSO_CONTEXT_TABLE_ADDRESS 0xb500
+#define DS_GSO_CONTEXT_TABLE_BYTE_SIZE 0x0084
+#define DS_GSO_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0008
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xb584
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_FW_MAC_ADDRS_ADDRESS 0xb588
+#define DS_FW_MAC_ADDRS_BYTE_SIZE 0x0080
+#define DS_FW_MAC_ADDRS_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_FW_MAC_ADDRS_SIZE     16
+#define RDD_DS_FW_MAC_ADDRS_LOG2_SIZE     4
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_ADDRESS 0xb608
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_BYTE_SIZE 0x0008
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_LOG2_BYTE_SIZE 0x0003
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS 0xb610
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_BYTE_SIZE 0x0010
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_SIZE     3
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS 0xb620
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_BYTE_SIZE 0x0010
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define ETH_TX_SCRATCH_ADDRESS 0xb630
+#define ETH_TX_SCRATCH_BYTE_SIZE 0x0010
+#define ETH_TX_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define RDD_ETH_TX_SCRATCH_SIZE     16
+#define RDD_ETH_TX_SCRATCH_LOG2_SIZE     4
+#define DS_SYSTEM_CONFIGURATION_ADDRESS 0xb640
+#define DS_SYSTEM_CONFIGURATION_BYTE_SIZE 0x0024
+#define DS_SYSTEM_CONFIGURATION_LOG2_BYTE_SIZE 0x0006
+#define SPDSVC_HOST_BUF_PTR_ADDRESS 0xb664
+#define SPDSVC_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define SPDSVC_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define GSO_TX_DHD_L2_BUFFER_ADDRESS 0xb668
+#define GSO_TX_DHD_L2_BUFFER_BYTE_SIZE 0x0016
+#define GSO_TX_DHD_L2_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_GSO_TX_DHD_L2_BUFFER_SIZE     22
+#define RDD_GSO_TX_DHD_L2_BUFFER_LOG2_SIZE     5
+#define IPTV_COUNTERS_BUFFER_ADDRESS 0xb67e
+#define IPTV_COUNTERS_BUFFER_BYTE_SIZE 0x0002
+#define IPTV_COUNTERS_BUFFER_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_TX_POST_INGRESS_QUEUE_ADDRESS 0xb680
+#define DS_DHD_TX_POST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_DHD_TX_POST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_LOG2_SIZE     6
+#define IPSEC_DS_SA_DESC_CAM_TABLE_ADDRESS 0xb6c0
+#define IPSEC_DS_SA_DESC_CAM_TABLE_BYTE_SIZE 0x0020
+#define IPSEC_DS_SA_DESC_CAM_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE     16
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_LOG2_SIZE     4
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_ADDRESS 0xb6e0
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_BYTE_SIZE 0x0010
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define RUNNER_FLOW_IH_RESPONSE_ADDRESS 0xb6f0
+#define RUNNER_FLOW_IH_RESPONSE_BYTE_SIZE 0x0008
+#define RUNNER_FLOW_IH_RESPONSE_LOG2_BYTE_SIZE 0x0003
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_ADDRESS 0xb6f8
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_BYTE_SIZE 0x0008
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_LOG2_BYTE_SIZE 0x0003
+#define DS_GSO_DESC_TABLE_ADDRESS 0xb700
+#define DS_GSO_DESC_TABLE_BYTE_SIZE 0x0080
+#define DS_GSO_DESC_TABLE_LOG2_BYTE_SIZE 0x0007
+#define WLAN_MCAST_INGRESS_QUEUE_ADDRESS 0xb780
+#define WLAN_MCAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define WLAN_MCAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE     64
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define IPSEC_US_SA_DESC_CAM_TABLE_ADDRESS 0xb7c0
+#define IPSEC_US_SA_DESC_CAM_TABLE_BYTE_SIZE 0x0020
+#define IPSEC_US_SA_DESC_CAM_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE     16
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_LOG2_SIZE     4
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_ADDRESS 0xb7e0
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_BYTE_SIZE 0x0018
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_LOG2_BYTE_SIZE 0x0005
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_ADDRESS 0xb7f8
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_BYTE_SIZE 0x0005
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_LOG2_BYTE_SIZE 0x0003
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE     5
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_LOG2_SIZE     3
+#define ETH_TX_EMACS_STATUS_ADDRESS 0xb7fd
+#define ETH_TX_EMACS_STATUS_BYTE_SIZE 0x0001
+#define ETH_TX_EMACS_STATUS_LOG2_BYTE_SIZE 0x0001
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xb7fe
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define GPON_RX_NORMAL_DESCRIPTORS_ADDRESS 0xb800
+#define GPON_RX_NORMAL_DESCRIPTORS_BYTE_SIZE 0x0100
+#define GPON_RX_NORMAL_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE     32
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_LOG2_SIZE     5
+#define CPU_TX_DHD_L2_BUFFER_ADDRESS 0xb900
+#define CPU_TX_DHD_L2_BUFFER_BYTE_SIZE 0x0016
+#define CPU_TX_DHD_L2_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_CPU_TX_DHD_L2_BUFFER_SIZE     22
+#define RDD_CPU_TX_DHD_L2_BUFFER_LOG2_SIZE     5
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_ADDRESS 0xb916
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_BYTE_SIZE 0x0002
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define HASH_BASED_FORWARDING_PORT_TABLE_ADDRESS 0xb918
+#define HASH_BASED_FORWARDING_PORT_TABLE_BYTE_SIZE 0x0004
+#define HASH_BASED_FORWARDING_PORT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE     4
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_LOG2_SIZE     2
+#define FIREWALL_IPV6_R16_BUFFER_ADDRESS 0xb91c
+#define FIREWALL_IPV6_R16_BUFFER_BYTE_SIZE 0x0004
+#define FIREWALL_IPV6_R16_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_ADDRESS 0xb920
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_ADDRESS 0xb930
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_ADDRESS 0xb940
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb950
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_ADDRESS 0xb952
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xb954
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_ADDRESS 0xb956
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_BYTE_SIZE 0x0002
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_LOG2_BYTE_SIZE 0x0001
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_ADDRESS 0xb958
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_BYTE_SIZE 0x0002
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_LOG2_BYTE_SIZE 0x0001
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_ADDRESS 0xb95a
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS 0xb95c
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_ADDRESS 0xb95e
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_BYTE_SIZE 0x0002
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define GSO_DESC_PTR_ADDRESS 0xb960
+#define GSO_DESC_PTR_BYTE_SIZE 0x0004
+#define GSO_DESC_PTR_LOG2_BYTE_SIZE 0x0002
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_ADDRESS 0xb964
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_BYTE_SIZE 0x0004
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define GSO_TX_DHD_HOST_BUF_PTR_ADDRESS 0xb968
+#define GSO_TX_DHD_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define GSO_TX_DHD_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE     4
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_LOG2_SIZE     2
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_ADDRESS 0xb96c
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_BYTE_SIZE 0x0004
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_LOG2_BYTE_SIZE 0x0002
+#define CPU_TX_DHD_HOST_BUF_PTR_ADDRESS 0xb970
+#define CPU_TX_DHD_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define CPU_TX_DHD_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE     4
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_LOG2_SIZE     2
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_ADDRESS 0xb974
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_BYTE_SIZE 0x0002
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_LOG2_BYTE_SIZE 0x0001
+#define DS_MEMLIB_SEMAPHORE_ADDRESS 0xb976
+#define DS_MEMLIB_SEMAPHORE_BYTE_SIZE 0x0002
+#define DS_MEMLIB_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define WAN_PHYSICAL_PORT_ADDRESS 0xb978
+#define WAN_PHYSICAL_PORT_BYTE_SIZE 0x0002
+#define WAN_PHYSICAL_PORT_LOG2_BYTE_SIZE 0x0001
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb97a
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_RUNNER_CONGESTION_STATE_ADDRESS 0xb97c
+#define DS_RUNNER_CONGESTION_STATE_BYTE_SIZE 0x0002
+#define DS_RUNNER_CONGESTION_STATE_LOG2_BYTE_SIZE 0x0001
+#define GSO_PICO_QUEUE_PTR_ADDRESS 0xb97e
+#define GSO_PICO_QUEUE_PTR_BYTE_SIZE 0x0002
+#define GSO_PICO_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_ADDRESS 0xb980
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_BYTE_SIZE 0x0002
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_ADDRESS 0xb982
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_BYTE_SIZE 0x0002
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_ADDRESS 0xb984
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_BYTE_SIZE 0x0002
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_ADDRESS 0xb986
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_BYTE_SIZE 0x0002
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_DDR_SA_DESC_SIZE_ADDRESS 0xb988
+#define IPSEC_DS_DDR_SA_DESC_SIZE_BYTE_SIZE 0x0002
+#define IPSEC_DS_DDR_SA_DESC_SIZE_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_QUEUE_PTR_ADDRESS 0xb98a
+#define IPSEC_DS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define IPSEC_DS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_IP_LENGTH_ADDRESS 0xb98c
+#define IPSEC_DS_IP_LENGTH_BYTE_SIZE 0x0002
+#define IPSEC_DS_IP_LENGTH_LOG2_BYTE_SIZE 0x0001
+#define PRIVATE_A_DUMMY_STORE_ADDRESS 0xb98e
+#define PRIVATE_A_DUMMY_STORE_BYTE_SIZE 0x0001
+#define PRIVATE_A_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_ADDRESS 0xb98f
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_BYTE_SIZE 0x0001
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_LOG2_BYTE_SIZE 0x0001
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xb990
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xb991
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define CPU_TX_DS_PICO_SEMAPHORE_ADDRESS 0xb992
+#define CPU_TX_DS_PICO_SEMAPHORE_BYTE_SIZE 0x0001
+#define CPU_TX_DS_PICO_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define DS_FC_GLOBAL_CFG_ADDRESS 0xb993
+#define DS_FC_GLOBAL_CFG_BYTE_SIZE 0x0001
+#define DS_FC_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_ADDRESS 0xb994
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_ADDRESS 0xb995
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_PACKET_BUFFER_SIZE_ASR_8_ADDRESS 0xb996
+#define DS_PACKET_BUFFER_SIZE_ASR_8_BYTE_SIZE 0x0001
+#define DS_PACKET_BUFFER_SIZE_ASR_8_LOG2_BYTE_SIZE 0x0001
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb997
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb998
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_ADDRESS 0xb999
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_BYTE_SIZE 0x0001
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS 0xb99a
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_ADDRESS 0xb99b
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_LOG2_BYTE_SIZE 0x0001
+#define DS_IH_CONGESTION_THRESHOLD_ADDRESS 0xb99c
+#define DS_IH_CONGESTION_THRESHOLD_BYTE_SIZE 0x0001
+#define DS_IH_CONGESTION_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define DS_FW_MAC_ADDRS_COUNT_ADDRESS 0xb99d
+#define DS_FW_MAC_ADDRS_COUNT_BYTE_SIZE 0x0001
+#define DS_FW_MAC_ADDRS_COUNT_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_DMA_SYNCHRONIZATION_ADDRESS 0xb99e
+#define DS_DHD_DMA_SYNCHRONIZATION_BYTE_SIZE 0x0001
+#define DS_DHD_DMA_SYNCHRONIZATION_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_SEMAPHORE_ADDRESS 0xb99f
+#define DHD_TX_POST_CPU_SEMAPHORE_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define RING_CACHE_DHD_TXPOST_MUTEX_ADDRESS 0xb9a0
+#define RING_CACHE_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define RING_CACHE_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define COMMON_DHD_TXPOST_MUTEX_ADDRESS 0xb9a1
+#define COMMON_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define COMMON_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define TXCPL_INT_DHD_TXPOST_MUTEX_ADDRESS 0xb9a2
+#define TXCPL_INT_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define TXCPL_INT_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_ADDRESS 0xb9a3
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_BYTE_SIZE 0x0001
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_ADDRESS 0xb9a4
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_BYTE_SIZE 0x0001
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_LOG2_BYTE_SIZE 0x0001
+/* PRIVATE_B */
+#define US_INGRESS_HANDLER_BUFFER_ADDRESS 0x0000
+#define US_INGRESS_HANDLER_BUFFER_BYTE_SIZE 0x2000
+#define US_INGRESS_HANDLER_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_US_INGRESS_HANDLER_BUFFER_SIZE     32
+#define RDD_US_INGRESS_HANDLER_BUFFER_LOG2_SIZE     5
+#define US_CSO_CHUNK_BUFFER_ADDRESS 0x2000
+#define US_CSO_CHUNK_BUFFER_BYTE_SIZE 0x0080
+#define US_CSO_CHUNK_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define US_CSO_PSEUDO_HEADER_BUFFER_ADDRESS 0x2080
+#define US_CSO_PSEUDO_HEADER_BUFFER_BYTE_SIZE 0x0028
+#define US_CSO_PSEUDO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x20a8
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0008
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     2
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_ADDRESS 0x20b0
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_BYTE_SIZE 0x0010
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_SIZE     8
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_LOG2_SIZE     3
+#define US_CPU_REASON_TO_METER_TABLE_ADDRESS 0x20c0
+#define US_CPU_REASON_TO_METER_TABLE_BYTE_SIZE 0x0040
+#define US_CPU_REASON_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_REASON_TO_METER_TABLE_SIZE     64
+#define RDD_US_CPU_REASON_TO_METER_TABLE_LOG2_SIZE     6
+#define US_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS 0x2100
+#define US_MAIN_PROFILING_BUFFER_RUNNER_BYTE_SIZE 0x0100
+#define US_MAIN_PROFILING_BUFFER_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_LOG2_SIZE     5
+#define US_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS 0x2200
+#define US_FREE_PACKET_DESCRIPTORS_POOL_BYTE_SIZE 0x6000
+#define US_FREE_PACKET_DESCRIPTORS_POOL_LOG2_BYTE_SIZE 0x000f
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE     3072
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_LOG2_SIZE     12
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS 0x8200
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_BYTE_SIZE 0x0180
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE     3
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE2    4
+#define US_QUEUE_PROFILE_TABLE_ADDRESS 0x8380
+#define US_QUEUE_PROFILE_TABLE_BYTE_SIZE 0x0080
+#define US_QUEUE_PROFILE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_QUEUE_PROFILE_TABLE_SIZE     8
+#define RDD_US_QUEUE_PROFILE_TABLE_LOG2_SIZE     3
+#define WAN_CHANNELS_8_39_TABLE_ADDRESS 0x8400
+#define WAN_CHANNELS_8_39_TABLE_BYTE_SIZE 0x0400
+#define WAN_CHANNELS_8_39_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WAN_CHANNELS_8_39_TABLE_SIZE     32
+#define RDD_WAN_CHANNELS_8_39_TABLE_LOG2_SIZE     5
+#define US_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x8800
+#define US_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0180
+#define US_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE     3
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_LOG2_SIZE     2
+#define US_SBPM_REPLY_ADDRESS 0x8980
+#define US_SBPM_REPLY_BYTE_SIZE 0x0080
+#define US_SBPM_REPLY_LOG2_BYTE_SIZE 0x0007
+#define US_POLICER_TABLE_ADDRESS 0x8a00
+#define US_POLICER_TABLE_BYTE_SIZE 0x0100
+#define US_POLICER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_POLICER_TABLE_SIZE     16
+#define RDD_US_POLICER_TABLE_LOG2_SIZE     4
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_ADDRESS 0x8b00
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_BYTE_SIZE 0x0100
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE     2
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_LOG2_SIZE     1
+#define US_WAN_FLOW_TABLE_ADDRESS 0x8c00
+#define US_WAN_FLOW_TABLE_BYTE_SIZE 0x0400
+#define US_WAN_FLOW_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_US_WAN_FLOW_TABLE_SIZE     256
+#define RDD_US_WAN_FLOW_TABLE_LOG2_SIZE     8
+#define US_CPU_TX_BBH_DESCRIPTORS_ADDRESS 0x9000
+#define US_CPU_TX_BBH_DESCRIPTORS_BYTE_SIZE 0x0100
+#define US_CPU_TX_BBH_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_LOG2_SIZE     5
+#define US_FORWARDING_MATRIX_TABLE_ADDRESS 0x9100
+#define US_FORWARDING_MATRIX_TABLE_BYTE_SIZE 0x0090
+#define US_FORWARDING_MATRIX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_US_FORWARDING_MATRIX_TABLE_LOG2_SIZE     4
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE2    16
+#define RDD_US_FORWARDING_MATRIX_TABLE_LOG2_SIZE2    4
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x9190
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0010
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     3
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x91a0
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define DSL_PTM_BOND_TX_HDR_TABLE_ADDRESS 0x91c0
+#define DSL_PTM_BOND_TX_HDR_TABLE_BYTE_SIZE 0x0040
+#define DSL_PTM_BOND_TX_HDR_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DSL_PTM_BOND_TX_HDR_TABLE_SIZE     32
+#define RDD_DSL_PTM_BOND_TX_HDR_TABLE_LOG2_SIZE     5
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_ADDRESS 0x9200
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_BYTE_SIZE 0x0040
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE     8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_SIZE     3
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2    8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_SIZE2    3
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9240
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9280
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS 0x92c0
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define US_RATE_LIMITER_TABLE_ADDRESS 0x9300
+#define US_RATE_LIMITER_TABLE_BYTE_SIZE 0x0080
+#define US_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_RATE_LIMITER_TABLE_SIZE     16
+#define RDD_US_RATE_LIMITER_TABLE_LOG2_SIZE     4
+#define US_CPU_RX_METER_TABLE_ADDRESS 0x9380
+#define US_CPU_RX_METER_TABLE_BYTE_SIZE 0x0080
+#define US_CPU_RX_METER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_RX_METER_TABLE_SIZE     16
+#define RDD_US_CPU_RX_METER_TABLE_LOG2_SIZE     4
+#define US_CONNECTION_CONTEXT_BUFFER_ADDRESS 0x9400
+#define US_CONNECTION_CONTEXT_BUFFER_BYTE_SIZE 0x0400
+#define US_CONNECTION_CONTEXT_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE     8
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS 0x9800
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_SIZE     8
+#define WAN_CHANNELS_0_7_TABLE_ADDRESS 0xa000
+#define WAN_CHANNELS_0_7_TABLE_BYTE_SIZE 0x02c0
+#define WAN_CHANNELS_0_7_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WAN_CHANNELS_0_7_TABLE_SIZE     8
+#define RDD_WAN_CHANNELS_0_7_TABLE_LOG2_SIZE     3
+#define US_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0xa2c0
+#define US_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0040
+#define US_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_L2_UCAST_CONNECTION_BUFFER_SIZE     4
+#define RDD_US_L2_UCAST_CONNECTION_BUFFER_LOG2_SIZE     2
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS 0xa300
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_BYTE_SIZE 0x0080
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_SIZE     5
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0xa380
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define US_PROFILING_BUFFER_PICO_RUNNER_ADDRESS 0xa400
+#define US_PROFILING_BUFFER_PICO_RUNNER_BYTE_SIZE 0x0100
+#define US_PROFILING_BUFFER_PICO_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS 0xa500
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_BYTE_SIZE 0x0080
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_SIZE     4
+#define US_CONNECTION_CACHE_BUFFER_ADDRESS 0xa580
+#define US_CONNECTION_CACHE_BUFFER_BYTE_SIZE 0x0080
+#define US_CONNECTION_CACHE_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CONNECTION_CACHE_BUFFER_SIZE     8
+#define RDD_US_CONNECTION_CACHE_BUFFER_LOG2_SIZE     3
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS 0xa600
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_BYTE_SIZE 0x0060
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE     3
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE2    4
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0xa660
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_ADDRESS 0xa680
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_BYTE_SIZE 0x0060
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define US_FC_L2_UCAST_TUPLE_BUFFER_ADDRESS 0xa6e0
+#define US_FC_L2_UCAST_TUPLE_BUFFER_BYTE_SIZE 0x0020
+#define US_FC_L2_UCAST_TUPLE_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define DHD_RX_POST_FLOW_RING_BUFFER_ADDRESS 0xa700
+#define DHD_RX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x0060
+#define DHD_RX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS 0xa760
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_BYTE_SIZE 0x0020
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_SIZE     2
+#define US_INGRESS_RATE_LIMITER_TABLE_ADDRESS 0xa780
+#define US_INGRESS_RATE_LIMITER_TABLE_BYTE_SIZE 0x0050
+#define US_INGRESS_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE     5
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_LOG2_SIZE     3
+#define DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_ADDRESS 0xa7d0
+#define DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_BYTE_SIZE 0x0010
+#define DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_SIZE     8
+#define RDD_DSL_PTM_BOND_TX_HDR_DEBUG_TABLE_LOG2_SIZE     3
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xa7e0
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define US_SPDSVC_CONTEXT_TABLE_ADDRESS 0xa800
+#define US_SPDSVC_CONTEXT_TABLE_BYTE_SIZE 0x0050
+#define US_SPDSVC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0xa850
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0010
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xa860
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define US_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS 0xa880
+#define US_CPU_RX_PICO_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_CPU_RX_PICO_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_ADDRESS 0xa8c0
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_BYTE_SIZE 0x0040
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define US_ROUTER_INGRESS_QUEUE_ADDRESS 0xa900
+#define US_ROUTER_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_ROUTER_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_ROUTER_INGRESS_QUEUE_SIZE     64
+#define RDD_US_ROUTER_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_DHD_TX_POST_HEADER_SCRATCH_ADDRESS 0xa940
+#define US_DHD_TX_POST_HEADER_SCRATCH_BYTE_SIZE 0x0020
+#define US_DHD_TX_POST_HEADER_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS 0xa960
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_BYTE_SIZE 0x0018
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_SIZE     3
+#define US_TOTAL_PPS_RATE_LIMITER_ADDRESS 0xa978
+#define US_TOTAL_PPS_RATE_LIMITER_BYTE_SIZE 0x0008
+#define US_TOTAL_PPS_RATE_LIMITER_LOG2_BYTE_SIZE 0x0003
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xa980
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0001
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define PRIVATE_B_DUMMY_STORE_ADDRESS 0xa981
+#define PRIVATE_B_DUMMY_STORE_BYTE_SIZE 0x0001
+#define PRIVATE_B_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xa982
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_ADDRESS 0xa984
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_BYTE_SIZE 0x0004
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_LOG2_BYTE_SIZE 0x0002
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS 0xa988
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_BYTE_SIZE 0x0001
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xa989
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xa98a
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_ADDRESS 0xa98c
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xa990
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0028
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0006
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE     40
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_LOG2_SIZE     6
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS 0xa9b8
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define US_ONE_BUFFER_ADDRESS 0xa9f8
+#define US_ONE_BUFFER_BYTE_SIZE 0x0008
+#define US_ONE_BUFFER_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS 0xaa00
+#define US_CPU_RX_FAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_CPU_RX_FAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_DEBUG_BUFFER_ADDRESS 0xaa40
+#define US_DEBUG_BUFFER_BYTE_SIZE 0x0080
+#define US_DEBUG_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_DEBUG_BUFFER_SIZE     32
+#define RDD_US_DEBUG_BUFFER_LOG2_SIZE     5
+#define US_FW_MAC_ADDRS_ADDRESS 0xaac0
+#define US_FW_MAC_ADDRS_BYTE_SIZE 0x0080
+#define US_FW_MAC_ADDRS_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_FW_MAC_ADDRS_SIZE     16
+#define RDD_US_FW_MAC_ADDRS_LOG2_SIZE     4
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS 0xab40
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_BYTE_SIZE 0x0018
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE     3
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_SIZE     2
+#define US_NULL_BUFFER_ADDRESS 0xab58
+#define US_NULL_BUFFER_BYTE_SIZE 0x0008
+#define US_NULL_BUFFER_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_PARAMETERS_BLOCK_ADDRESS 0xab60
+#define US_CPU_PARAMETERS_BLOCK_BYTE_SIZE 0x0014
+#define US_CPU_PARAMETERS_BLOCK_LOG2_BYTE_SIZE 0x0005
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xab74
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS 0xab78
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_BYTE_SIZE 0x0008
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_SIZE     3
+#define US_DHD_TX_POST_INGRESS_QUEUE_ADDRESS 0xab80
+#define US_DHD_TX_POST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_DHD_TX_POST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS 0xabc0
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x0030
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RUNNER_FWTRACE_MAINB_PARAM_ADDRESS 0xabf0
+#define RUNNER_FWTRACE_MAINB_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINB_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_LOG2_SIZE     1
+#define US_CPU_TX_FAST_QUEUE_ADDRESS 0xac00
+#define US_CPU_TX_FAST_QUEUE_BYTE_SIZE 0x0080
+#define US_CPU_TX_FAST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_TX_FAST_QUEUE_SIZE     16
+#define RDD_US_CPU_TX_FAST_QUEUE_LOG2_SIZE     4
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_ADDRESS 0xac80
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_BYTE_SIZE 0x0060
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE     48
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_LOG2_SIZE     6
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xace0
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define RUNNER_FWTRACE_PICOB_PARAM_ADDRESS 0xacf0
+#define RUNNER_FWTRACE_PICOB_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_PICOB_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_LOG2_SIZE     1
+#define US_CPU_TX_PICO_QUEUE_ADDRESS 0xad00
+#define US_CPU_TX_PICO_QUEUE_BYTE_SIZE 0x0080
+#define US_CPU_TX_PICO_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_TX_PICO_QUEUE_SIZE     16
+#define RDD_US_CPU_TX_PICO_QUEUE_LOG2_SIZE     4
+#define US_CSO_CONTEXT_TABLE_ADDRESS 0xad80
+#define US_CSO_CONTEXT_TABLE_BYTE_SIZE 0x0054
+#define US_CSO_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define US_BPM_DDR_BUFFERS_BASE_ADDRESS 0xadd4
+#define US_BPM_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS 0xadd8
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_BYTE_SIZE 0x0028
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_BYTE_SIZE 0x0006
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE     40
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_SIZE     6
+#define US_DHD_FLOW_RING_DROP_COUNTER_ADDRESS 0xae00
+#define US_DHD_FLOW_RING_DROP_COUNTER_BYTE_SIZE 0x0014
+#define US_DHD_FLOW_RING_DROP_COUNTER_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_LOG2_SIZE     3
+#define US_CONNECTION_TABLE_CONFIG_ADDRESS 0xae14
+#define US_CONNECTION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONNECTION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ADDRESS 0xae18
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_BYTE_SIZE 0x0006
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xae1e
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xae20
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS 0xae30
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_BYTE_SIZE 0x0010
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_SIZE     3
+#define US_SYSTEM_CONFIGURATION_ADDRESS 0xae40
+#define US_SYSTEM_CONFIGURATION_BYTE_SIZE 0x0024
+#define US_SYSTEM_CONFIGURATION_LOG2_BYTE_SIZE 0x0006
+#define US_CONTEXT_TABLE_CONFIG_ADDRESS 0xae64
+#define US_CONTEXT_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONTEXT_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_ADDRESS 0xae68
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_BYTE_SIZE 0x0020
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_LOG2_SIZE     5
+#define DATA_POINTER_DUMMY_TARGET_ADDRESS 0xae88
+#define DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0008
+#define DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0003
+#define RDD_DATA_POINTER_DUMMY_TARGET_SIZE     2
+#define RDD_DATA_POINTER_DUMMY_TARGET_LOG2_SIZE     1
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS 0xae90
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_BYTE_SIZE 0x0010
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define WAN_TX_SCRATCH_ADDRESS 0xaea0
+#define WAN_TX_SCRATCH_BYTE_SIZE 0x0018
+#define WAN_TX_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define RDD_WAN_TX_SCRATCH_SIZE     24
+#define RDD_WAN_TX_SCRATCH_LOG2_SIZE     5
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_ADDRESS 0xaeb8
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_BYTE_SIZE 0x0012
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE     3
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_SIZE     2
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2    6
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_SIZE2    3
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_ADDRESS 0xaeca
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_BYTE_SIZE 0x0002
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS 0xaecc
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_BYTE_SIZE 0x0004
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_SIZE     2
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_ADDRESS 0xaed0
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_BYTE_SIZE 0x0009
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE     9
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xaed9
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_ADDRESS 0xaeda
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_BYTE_SIZE 0x0002
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_SLAVE_LOCK_ADDRESS 0xaedc
+#define US_PARALLEL_PROCESSING_SLAVE_LOCK_BYTE_SIZE 0x0004
+#define US_PARALLEL_PROCESSING_SLAVE_LOCK_LOG2_BYTE_SIZE 0x0002
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_ADDRESS 0xaee0
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_BYTE_SIZE 0x0010
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_ADDRESS 0xaef0
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_ADDRESS 0xaf00
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_BYTE_SIZE 0x000e
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE     14
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_LOG2_SIZE     4
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_ADDRESS 0xaf0e
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS 0xaf10
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_BYTE_SIZE 0x0004
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_SIZE     2
+#define US_CPU_TX_FLUSH_PAUSE_REQUEST_ADDRESS 0xaf14
+#define US_CPU_TX_FLUSH_PAUSE_REQUEST_BYTE_SIZE 0x0004
+#define US_CPU_TX_FLUSH_PAUSE_REQUEST_LOG2_BYTE_SIZE 0x0002
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS 0xaf18
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_BYTE_SIZE 0x0008
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_SIZE     3
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_ADDRESS 0xaf20
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_BYTE_SIZE 0x0004
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_LOG2_BYTE_SIZE 0x0002
+#define IH_BUFFER_BBH_POINTER_ADDRESS 0xaf24
+#define IH_BUFFER_BBH_POINTER_BYTE_SIZE 0x0004
+#define IH_BUFFER_BBH_POINTER_LOG2_BYTE_SIZE 0x0002
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_ADDRESS 0xaf28
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xaf2c
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS 0xaf30
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_BYTE_SIZE 0x0004
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_SIZE     4
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_SIZE     2
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xaf34
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xaf36
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS 0xaf38
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_BYTE_SIZE 0x0002
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_ANY_SRC_PORT_FLOW_COUNTER_ADDRESS 0xaf3a
+#define US_ANY_SRC_PORT_FLOW_COUNTER_BYTE_SIZE 0x0002
+#define US_ANY_SRC_PORT_FLOW_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_ADDRESS 0xaf3c
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_BYTE_SIZE 0x0004
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_ADDRESS 0xaf40
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_BYTE_SIZE 0x0002
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_LOG2_BYTE_SIZE 0x0001
+#define US_MEMLIB_SEMAPHORE_ADDRESS 0xaf42
+#define US_MEMLIB_SEMAPHORE_BYTE_SIZE 0x0002
+#define US_MEMLIB_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_ADDRESS 0xaf44
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_RUNNER_CONGESTION_STATE_ADDRESS 0xaf46
+#define US_RUNNER_CONGESTION_STATE_BYTE_SIZE 0x0002
+#define US_RUNNER_CONGESTION_STATE_LOG2_BYTE_SIZE 0x0001
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xaf48
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_ADDRESS 0xaf4a
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_BYTE_SIZE 0x0002
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_ADDRESS 0xaf4c
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_BYTE_SIZE 0x0002
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_FC_GLOBAL_CFG_ADDRESS 0xaf4e
+#define US_FC_GLOBAL_CFG_BYTE_SIZE 0x0001
+#define US_FC_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0001
+#define ETHWAN2_SWITCH_PORT_ADDRESS 0xaf4f
+#define ETHWAN2_SWITCH_PORT_BYTE_SIZE 0x0001
+#define ETHWAN2_SWITCH_PORT_LOG2_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_ADDRESS 0xaf50
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_ADDRESS 0xaf51
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_PACKET_BUFFER_SIZE_ASR_8_ADDRESS 0xaf52
+#define US_PACKET_BUFFER_SIZE_ASR_8_BYTE_SIZE 0x0001
+#define US_PACKET_BUFFER_SIZE_ASR_8_LOG2_BYTE_SIZE 0x0001
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xaf53
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xaf54
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_ADDRESS 0xaf55
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_BYTE_SIZE 0x0001
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DSL_PTM_BOND_TX_CONTROL_ADDRESS 0xaf56
+#define DSL_PTM_BOND_TX_CONTROL_BYTE_SIZE 0x0001
+#define DSL_PTM_BOND_TX_CONTROL_LOG2_BYTE_SIZE 0x0001
+#define DSL_BUFFER_ALIGNMENT_ADDRESS 0xaf57
+#define DSL_BUFFER_ALIGNMENT_BYTE_SIZE 0x0001
+#define DSL_BUFFER_ALIGNMENT_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS 0xaf58
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_ADDRESS 0xaf59
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_LOG2_BYTE_SIZE 0x0001
+#define US_IH_CONGESTION_THRESHOLD_ADDRESS 0xaf5a
+#define US_IH_CONGESTION_THRESHOLD_BYTE_SIZE 0x0001
+#define US_IH_CONGESTION_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define US_FW_MAC_ADDRS_COUNT_ADDRESS 0xaf5b
+#define US_FW_MAC_ADDRS_COUNT_BYTE_SIZE 0x0001
+#define US_FW_MAC_ADDRS_COUNT_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_DMA_SYNCHRONIZATION_ADDRESS 0xaf5c
+#define US_DHD_DMA_SYNCHRONIZATION_BYTE_SIZE 0x0001
+#define US_DHD_DMA_SYNCHRONIZATION_LOG2_BYTE_SIZE 0x0001
+#define ETH1_RX_DESCRIPTORS_ADDRESS 0xb200
+#define ETH1_RX_DESCRIPTORS_BYTE_SIZE 0x0100
+#define ETH1_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH1_RX_DESCRIPTORS_SIZE     32
+#define RDD_ETH1_RX_DESCRIPTORS_LOG2_SIZE     5
+#define US_RUNNER_FLOW_IH_RESPONSE_ADDRESS 0xb6f0
+#define US_RUNNER_FLOW_IH_RESPONSE_BYTE_SIZE 0x0008
+#define US_RUNNER_FLOW_IH_RESPONSE_LOG2_BYTE_SIZE 0x0003
+#define BBH_TX_WAN_CHANNEL_INDEX_ADDRESS 0xbcb8
+#define BBH_TX_WAN_CHANNEL_INDEX_BYTE_SIZE 0x0004
+#define BBH_TX_WAN_CHANNEL_INDEX_LOG2_BYTE_SIZE 0x0002
+/* COMMON_A */
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_ADDRESS 0x0000
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_BYTE_SIZE 0x1800
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_LOG2_BYTE_SIZE 0x000d
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE     384
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_LOG2_SIZE     9
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS 0x1800
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define CPU_RX_RUNNER_A_SCRATCHPAD_ADDRESS 0x2000
+#define CPU_RX_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define CPU_RX_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS 0x2800
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define RUNNER_FWTRACE_MAINA_BASE_ADDRESS 0x3000
+#define RUNNER_FWTRACE_MAINA_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_MAINA_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_LOG2_SIZE     7
+#define RUNNER_FWTRACE_PICOA_BASE_ADDRESS 0x3400
+#define RUNNER_FWTRACE_PICOA_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_PICOA_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_LOG2_SIZE     7
+#define WLAN_MCAST_DHD_STATION_TABLE_ADDRESS 0x3800
+#define WLAN_MCAST_DHD_STATION_TABLE_BYTE_SIZE 0x0280
+#define WLAN_MCAST_DHD_STATION_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_LOG2_SIZE     6
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS 0x3a80
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_BYTE_SIZE 0x0080
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE     2
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE     1
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE2    64
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE2    6
+#define MAC_TABLE_CAM_ADDRESS 0x3b00
+#define MAC_TABLE_CAM_BYTE_SIZE 0x0100
+#define MAC_TABLE_CAM_LOG2_BYTE_SIZE 0x0008
+#define RDD_MAC_TABLE_CAM_SIZE     32
+#define RDD_MAC_TABLE_CAM_LOG2_SIZE     5
+#define MAC_TABLE_ADDRESS 0x3c00
+#define MAC_TABLE_BYTE_SIZE 0x0200
+#define MAC_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAC_TABLE_SIZE     64
+#define RDD_MAC_TABLE_LOG2_SIZE     6
+#define ETHWAN2_RX_INGRESS_QUEUE_ADDRESS 0x3e00
+#define ETHWAN2_RX_INGRESS_QUEUE_BYTE_SIZE 0x0100
+#define ETHWAN2_RX_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE     32
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_LOG2_SIZE     5
+#define TRACE_C_TABLE_ADDRESS 0x3f00
+#define TRACE_C_TABLE_BYTE_SIZE 0x0020
+#define TRACE_C_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_TRACE_C_TABLE_SIZE     4
+#define RDD_TRACE_C_TABLE_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_ADDRESS 0x3f20
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_LOG2_SIZE     1
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_ADDRESS 0x3f30
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_ADDRESS 0x3f34
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_LOG2_BYTE_SIZE 0x0002
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_ADDRESS 0x3f38
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_BYTE_SIZE 0x0008
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_LOG2_BYTE_SIZE 0x0003
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE     2
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_LOG2_SIZE     1
+#define BPM_REPLY_RUNNER_A_ADDRESS 0x3f40
+#define BPM_REPLY_RUNNER_A_BYTE_SIZE 0x0030
+#define BPM_REPLY_RUNNER_A_LOG2_BYTE_SIZE 0x0006
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_ADDRESS 0x3f70
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_BYTE_SIZE 0x0010
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define MAC_CONTEXT_TABLE_ADDRESS 0x3f80
+#define MAC_CONTEXT_TABLE_BYTE_SIZE 0x0080
+#define MAC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_MAC_CONTEXT_TABLE_SIZE     64
+#define RDD_MAC_CONTEXT_TABLE_LOG2_SIZE     6
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS 0x4000
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_BYTE_SIZE 0x0600
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_LOG2_BYTE_SIZE 0x000b
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE     32
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS 0x4600
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_BYTE_SIZE 0x0200
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_SIZE     8
+#define WLAN_MCAST_FWD_TABLE_ADDRESS 0x4800
+#define WLAN_MCAST_FWD_TABLE_BYTE_SIZE 0x0200
+#define WLAN_MCAST_FWD_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_FWD_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_FWD_TABLE_LOG2_SIZE     6
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_ADDRESS 0x4a00
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_BYTE_SIZE 0x0200
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_LOG2_SIZE     5
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_ADDRESS 0x4c00
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_BYTE_SIZE 0x0180
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE     48
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_LOG2_SIZE     6
+#define CPU_TX_POST_REQUEST_QUEUE_ADDRESS 0x4d80
+#define CPU_TX_POST_REQUEST_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_POST_REQUEST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE     8
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_LOG2_SIZE     3
+#define WLAN_MCAST_SSID_STATS_TABLE_ADDRESS 0x4e00
+#define WLAN_MCAST_SSID_STATS_TABLE_BYTE_SIZE 0x0180
+#define WLAN_MCAST_SSID_STATS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE     48
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_LOG2_SIZE     6
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_ADDRESS 0x4f80
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_BYTE_SIZE 0x0060
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE     3
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_LOG2_SIZE     2
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS 0x4fe0
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_BYTE_SIZE 0x0020
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_SIZE     4
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS 0x5000
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_SIZE     7
+#define PM_COUNTERS_ADDRESS 0x5800
+#define PM_COUNTERS_BYTE_SIZE 0x1840
+#define PM_COUNTERS_LOG2_BYTE_SIZE 0x000d
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_ADDRESS 0x7040
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_BYTE_SIZE 0x0080
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_LOG2_BYTE_SIZE 0x0007
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE     128
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_LOG2_SIZE     7
+#define INTERRUPT_COALESCING_CONFIG_TABLE_ADDRESS 0x70c0
+#define INTERRUPT_COALESCING_CONFIG_TABLE_BYTE_SIZE 0x0040
+#define INTERRUPT_COALESCING_CONFIG_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE     16
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_LOG2_SIZE     4
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS 0x7100
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_BYTE_SIZE 0x0100
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_LOG2_SIZE     4
+#define DS_CONNECTION_BUFFER_TABLE_ADDRESS 0x7200
+#define DS_CONNECTION_BUFFER_TABLE_BYTE_SIZE 0x0140
+#define DS_CONNECTION_BUFFER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_DS_CONNECTION_BUFFER_TABLE_LOG2_SIZE     3
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2    4
+#define RDD_DS_CONNECTION_BUFFER_TABLE_LOG2_SIZE2    2
+#define MAC_CONTEXT_TABLE_CAM_ADDRESS 0x7340
+#define MAC_CONTEXT_TABLE_CAM_BYTE_SIZE 0x0040
+#define MAC_CONTEXT_TABLE_CAM_LOG2_BYTE_SIZE 0x0006
+#define RDD_MAC_CONTEXT_TABLE_CAM_SIZE     32
+#define RDD_MAC_CONTEXT_TABLE_CAM_LOG2_SIZE     5
+#define DHD_DOORBELL_WRITE_VALUES_ADDRESS 0x7380
+#define DHD_DOORBELL_WRITE_VALUES_BYTE_SIZE 0x0040
+#define DHD_DOORBELL_WRITE_VALUES_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_DOORBELL_WRITE_VALUES_SIZE     16
+#define RDD_DHD_DOORBELL_WRITE_VALUES_LOG2_SIZE     4
+#define DS_DHD_BACKUP_INDEX_CACHE_ADDRESS 0x73c0
+#define DS_DHD_BACKUP_INDEX_CACHE_BYTE_SIZE 0x0040
+#define DS_DHD_BACKUP_INDEX_CACHE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE     32
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_LOG2_SIZE     5
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_ADDRESS 0x7400
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_BYTE_SIZE 0x0100
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_LOG2_SIZE     5
+#define RING_DESCRIPTORS_TABLE_ADDRESS 0x7500
+#define RING_DESCRIPTORS_TABLE_BYTE_SIZE 0x0100
+#define RING_DESCRIPTORS_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_RING_DESCRIPTORS_TABLE_SIZE     16
+#define RDD_RING_DESCRIPTORS_TABLE_LOG2_SIZE     4
+#define MAC_EXTENSION_TABLE_ADDRESS 0x7600
+#define MAC_EXTENSION_TABLE_BYTE_SIZE 0x0040
+#define MAC_EXTENSION_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_MAC_EXTENSION_TABLE_SIZE     64
+#define RDD_MAC_EXTENSION_TABLE_LOG2_SIZE     6
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_ADDRESS 0x7640
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_BYTE_SIZE 0x0020
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE     16
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_LOG2_SIZE     4
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_ADDRESS 0x7660
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0014
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_ADDRESS 0x7674
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_ADDRESS 0x7678
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_BYTE_SIZE 0x0008
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_LOG2_BYTE_SIZE 0x0003
+#define SERVICE_QUEUES_CFG_ADDRESS 0x7680
+#define SERVICE_QUEUES_CFG_BYTE_SIZE 0x0014
+#define SERVICE_QUEUES_CFG_LOG2_BYTE_SIZE 0x0005
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_ADDRESS 0x7694
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_BYTE_SIZE 0x0004
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_LOG2_BYTE_SIZE 0x0002
+#define MAC_EXTENSION_TABLE_CAM_ADDRESS 0x7698
+#define MAC_EXTENSION_TABLE_CAM_BYTE_SIZE 0x0020
+#define MAC_EXTENSION_TABLE_CAM_LOG2_BYTE_SIZE 0x0005
+#define RDD_MAC_EXTENSION_TABLE_CAM_SIZE     32
+#define RDD_MAC_EXTENSION_TABLE_CAM_LOG2_SIZE     5
+#define DS_CAM_DHD_DMA_SCRATCH_ADDRESS 0x76b8
+#define DS_CAM_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_CAM_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_ENQ_DHD_DMA_SCRATCH_ADDRESS 0x76bc
+#define DS_ENQ_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_ENQ_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define PM_COUNTERS_BUFFER_ADDRESS 0x76c0
+#define PM_COUNTERS_BUFFER_BYTE_SIZE 0x0020
+#define PM_COUNTERS_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define TX_CPL_DHD_DMA_SCRATCH_ADDRESS 0x76e0
+#define TX_CPL_DHD_DMA_SCRATCH_BYTE_SIZE 0x000c
+#define TX_CPL_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE     3
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_LOG2_SIZE     2
+#define DS_R2D_DHD_DMA_SCRATCH_ADDRESS 0x76ec
+#define DS_R2D_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_R2D_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_CPU_DHD_DMA_SCRATCH_ADDRESS 0x76f0
+#define DS_CPU_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_CPU_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define TIMER_7_TIMER_PERIOD_ADDRESS 0x76f4
+#define TIMER_7_TIMER_PERIOD_BYTE_SIZE 0x0002
+#define TIMER_7_TIMER_PERIOD_LOG2_BYTE_SIZE 0x0001
+#define INTERRUPT_COALESCING_TIMER_PERIOD_ADDRESS 0x76f6
+#define INTERRUPT_COALESCING_TIMER_PERIOD_BYTE_SIZE 0x0002
+#define INTERRUPT_COALESCING_TIMER_PERIOD_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_POST_BUFFERS_THRESHOLD_ADDRESS 0x76f8
+#define DHD_TX_POST_BUFFERS_THRESHOLD_BYTE_SIZE 0x0006
+#define DHD_TX_POST_BUFFERS_THRESHOLD_LOG2_BYTE_SIZE 0x0003
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_SIZE     3
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_LOG2_SIZE     2
+#define INTERRUPT_COALESCING_TIMER_ARMED_ADDRESS 0x76fe
+#define INTERRUPT_COALESCING_TIMER_ARMED_BYTE_SIZE 0x0002
+#define INTERRUPT_COALESCING_TIMER_ARMED_LOG2_BYTE_SIZE 0x0001
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS 0x7700
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_BYTE_SIZE 0x0004
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_SIZE     4
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_SIZE     2
+#define DHD_TX_POST_BUFFERS_IN_USE_COUNTER_ADDRESS 0x7704
+#define DHD_TX_POST_BUFFERS_IN_USE_COUNTER_BYTE_SIZE 0x0002
+#define DHD_TX_POST_BUFFERS_IN_USE_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define COMMON_A_DUMMY_STORE_ADDRESS 0x7706
+#define COMMON_A_DUMMY_STORE_BYTE_SIZE 0x0001
+#define COMMON_A_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define FC_SERVICE_QUEUE_MODE_ADDRESS 0x7707
+#define FC_SERVICE_QUEUE_MODE_BYTE_SIZE 0x0001
+#define FC_SERVICE_QUEUE_MODE_LOG2_BYTE_SIZE 0x0001
+#define MAIN_A_DEBUG_TRACE_ADDRESS 0x7a00
+#define MAIN_A_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define MAIN_A_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAIN_A_DEBUG_TRACE_SIZE     512
+#define RDD_MAIN_A_DEBUG_TRACE_LOG2_SIZE     9
+#define PICO_A_DEBUG_TRACE_ADDRESS 0x7c00
+#define PICO_A_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define PICO_A_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_PICO_A_DEBUG_TRACE_SIZE     512
+#define RDD_PICO_A_DEBUG_TRACE_LOG2_SIZE     9
+/* COMMON_B */
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS 0x8000
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_SIZE     7
+#define WAN_TX_MIRROR_SCRATCHPAD_ADDRESS 0x8800
+#define WAN_TX_MIRROR_SCRATCHPAD_BYTE_SIZE 0x0800
+#define WAN_TX_MIRROR_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_WAN_TX_MIRROR_SCRATCHPAD_SIZE     8
+#define RDD_WAN_TX_MIRROR_SCRATCHPAD_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS 0x9000
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_BYTE_SIZE 0x0200
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_SIZE     8
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0x9200
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0100
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0008
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     32
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS 0x9300
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_BYTE_SIZE 0x0100
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_SIZE     5
+#define WAN_TX_SERVICE_QUEUES_TABLE_ADDRESS 0x9400
+#define WAN_TX_SERVICE_QUEUES_TABLE_BYTE_SIZE 0x0800
+#define WAN_TX_SERVICE_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE     64
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_LOG2_SIZE     6
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS 0x9c00
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_BYTE_SIZE 0x0100
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_SIZE     5
+#define WAN_TX_RUNNER_B_SCRATCHPAD_ADDRESS 0x9d00
+#define WAN_TX_RUNNER_B_SCRATCHPAD_BYTE_SIZE 0x0100
+#define WAN_TX_RUNNER_B_SCRATCHPAD_LOG2_BYTE_SIZE 0x0008
+#define US_CONNECTION_BUFFER_TABLE_ADDRESS 0x9e00
+#define US_CONNECTION_BUFFER_TABLE_BYTE_SIZE 0x0140
+#define US_CONNECTION_BUFFER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_US_CONNECTION_BUFFER_TABLE_LOG2_SIZE     3
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE2    4
+#define RDD_US_CONNECTION_BUFFER_TABLE_LOG2_SIZE2    2
+#define IPV6_HOST_ADDRESS_CRC_TABLE_ADDRESS 0x9f40
+#define IPV6_HOST_ADDRESS_CRC_TABLE_BYTE_SIZE 0x0040
+#define IPV6_HOST_ADDRESS_CRC_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE     16
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_LOG2_SIZE     4
+#define DHD_BACKUP_INFO_CACHE_TABLE_ADDRESS 0x9f80
+#define DHD_BACKUP_INFO_CACHE_TABLE_BYTE_SIZE 0x0080
+#define DHD_BACKUP_INFO_CACHE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE     16
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_LOG2_SIZE     4
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS 0xa000
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_SIZE     8
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS 0xa800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_SIZE     8
+#define WAN_TX_QUEUES_TABLE_ADDRESS 0xb000
+#define WAN_TX_QUEUES_TABLE_BYTE_SIZE 0x1000
+#define WAN_TX_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000c
+#define RDD_WAN_TX_QUEUES_TABLE_SIZE     256
+#define RDD_WAN_TX_QUEUES_TABLE_LOG2_SIZE     8
+#define RUNNER_FWTRACE_MAINB_BASE_ADDRESS 0xc000
+#define RUNNER_FWTRACE_MAINB_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_MAINB_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_LOG2_SIZE     7
+#define US_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS 0xc400
+#define US_RING_PACKET_DESCRIPTORS_CACHE_BYTE_SIZE 0x0100
+#define US_RING_PACKET_DESCRIPTORS_CACHE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_LOG2_SIZE     4
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_ADDRESS 0xc500
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_BYTE_SIZE 0x00c0
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE     3
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_LOG2_SIZE     2
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_ADDRESS 0xc5c0
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_BYTE_SIZE 0x0040
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0006
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_ADDRESS 0xc600
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_BYTE_SIZE 0x0100
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE     16
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_LOG2_SIZE     4
+#define FC_FLOW_IP_ADDRESSES_TABLE_ADDRESS 0xc700
+#define FC_FLOW_IP_ADDRESSES_TABLE_BYTE_SIZE 0x00c0
+#define FC_FLOW_IP_ADDRESSES_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE     4
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_ADDRESS 0xc7c0
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_LOG2_SIZE     1
+#define BPM_REPLY_RUNNER_B_ADDRESS 0xc7d0
+#define BPM_REPLY_RUNNER_B_BYTE_SIZE 0x0030
+#define BPM_REPLY_RUNNER_B_LOG2_BYTE_SIZE 0x0006
+#define US_RATE_CONTROLLERS_TABLE_ADDRESS 0xc800
+#define US_RATE_CONTROLLERS_TABLE_BYTE_SIZE 0x1800
+#define US_RATE_CONTROLLERS_TABLE_LOG2_BYTE_SIZE 0x000d
+#define RDD_US_RATE_CONTROLLERS_TABLE_SIZE     128
+#define RDD_US_RATE_CONTROLLERS_TABLE_LOG2_SIZE     7
+#define CPU_RX_RUNNER_B_SCRATCHPAD_ADDRESS 0xe000
+#define CPU_RX_RUNNER_B_SCRATCHPAD_BYTE_SIZE 0x0800
+#define CPU_RX_RUNNER_B_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE     8
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_LOG2_SIZE     3
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS 0xe800
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_BYTE_SIZE 0x0050
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_BYTE_SIZE 0x0007
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     40
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_SIZE     6
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_ADDRESS 0xe850
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_BYTE_SIZE 0x0010
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_LOG2_BYTE_SIZE 0x0004
+#define IPV4_HOST_ADDRESS_TABLE_ADDRESS 0xe860
+#define IPV4_HOST_ADDRESS_TABLE_BYTE_SIZE 0x0020
+#define IPV4_HOST_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPV4_HOST_ADDRESS_TABLE_SIZE     8
+#define RDD_IPV4_HOST_ADDRESS_TABLE_LOG2_SIZE     3
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS 0xe880
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_BYTE_SIZE 0x0050
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_BYTE_SIZE 0x0007
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     40
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_SIZE     6
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS 0xe8d0
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_BYTE_SIZE 0x0080
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE     2
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE     1
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE2    64
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE2    6
+#define US_DHD_BACKUP_ENTRY_SCRATCH_ADDRESS 0xe950
+#define US_DHD_BACKUP_ENTRY_SCRATCH_BYTE_SIZE 0x0010
+#define US_DHD_BACKUP_ENTRY_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS 0xe960
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_BYTE_SIZE 0x0020
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_SIZE     4
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_ADDRESS 0xe980
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_BYTE_SIZE 0x0080
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_LOG2_BYTE_SIZE 0x0007
+#define MAIN_B_DEBUG_TRACE_ADDRESS 0xea00
+#define MAIN_B_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define MAIN_B_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAIN_B_DEBUG_TRACE_SIZE     512
+#define RDD_MAIN_B_DEBUG_TRACE_LOG2_SIZE     9
+#define PICO_B_DEBUG_TRACE_ADDRESS 0xec00
+#define PICO_B_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define PICO_B_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_PICO_B_DEBUG_TRACE_SIZE     512
+#define RDD_PICO_B_DEBUG_TRACE_LOG2_SIZE     9
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_ADDRESS 0xee00
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_BYTE_SIZE 0x0080
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_LOG2_BYTE_SIZE 0x0007
+#define LAN0_INGRESS_FIFO_ADDRESS 0xee80
+#define LAN0_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN0_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN5_INGRESS_FIFO_ADDRESS 0xeec0
+#define LAN5_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN5_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN1_INGRESS_FIFO_ADDRESS 0xef00
+#define LAN1_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN1_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN6_INGRESS_FIFO_ADDRESS 0xef40
+#define LAN6_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN6_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN2_INGRESS_FIFO_ADDRESS 0xef80
+#define LAN2_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN2_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN7_INGRESS_FIFO_ADDRESS 0xefc0
+#define LAN7_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN7_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define RUNNER_FWTRACE_PICOB_BASE_ADDRESS 0xf000
+#define RUNNER_FWTRACE_PICOB_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_PICOB_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_LOG2_SIZE     7
+#define LAN3_INGRESS_FIFO_ADDRESS 0xf400
+#define LAN3_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN3_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define US_DHD_BACKUP_INDEX_CACHE_ADDRESS 0xf440
+#define US_DHD_BACKUP_INDEX_CACHE_BYTE_SIZE 0x0040
+#define US_DHD_BACKUP_INDEX_CACHE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE     32
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_LOG2_SIZE     5
+#define LAN4_INGRESS_FIFO_ADDRESS 0xf480
+#define LAN4_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN4_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define DHD_DOORBELL_COUNTERS_ADDRESS 0xf4c0
+#define DHD_DOORBELL_COUNTERS_BYTE_SIZE 0x0030
+#define DHD_DOORBELL_COUNTERS_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_DOORBELL_COUNTERS_SIZE     48
+#define RDD_DHD_DOORBELL_COUNTERS_LOG2_SIZE     6
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ADDRESS 0xf4f0
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_BYTE_SIZE 0x0010
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_LOG2_BYTE_SIZE 0x0004
+#define WAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0xf500
+#define WAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define WAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_ADDRESS 0xf540
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0014
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define US_CAM_DHD_DMA_SCRATCH_ADDRESS 0xf554
+#define US_CAM_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_CAM_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_DHD_BACKUP_FLUSH_SCRATCH_ADDRESS 0xf558
+#define US_DHD_BACKUP_FLUSH_SCRATCH_BYTE_SIZE 0x0008
+#define US_DHD_BACKUP_FLUSH_SCRATCH_LOG2_BYTE_SIZE 0x0003
+#define US_ENQ_DHD_DMA_SCRATCH_ADDRESS 0xf560
+#define US_ENQ_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_ENQ_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_R2D_DHD_DMA_SCRATCH_ADDRESS 0xf564
+#define US_R2D_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_R2D_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_ADDRESS 0xf568
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_BYTE_SIZE 0x0004
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE     4
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_LOG2_SIZE     2
+#define COMMON_B_DUMMY_STORE_ADDRESS 0xf56c
+#define COMMON_B_DUMMY_STORE_BYTE_SIZE 0x0001
+#define COMMON_B_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_ADDRESS 0xf56d
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_BYTE_SIZE 0x0001
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_LOG2_BYTE_SIZE 0x0001
+/* DDR */
+#define BPM_PACKET_BUFFERS_ADDRESS 0x0000
+#define BPM_PACKET_BUFFERS_BYTE_SIZE 0xf00000
+#define BPM_PACKET_BUFFERS_LOG2_BYTE_SIZE 0x0018
+#define RDD_BPM_PACKET_BUFFERS_SIZE     7680
+#define RDD_BPM_PACKET_BUFFERS_LOG2_SIZE     13
+#define DS_CONNECTION_TABLE_ADDRESS 0x0000
+#define DS_CONNECTION_TABLE_BYTE_SIZE 0x80000
+#define DS_CONNECTION_TABLE_LOG2_BYTE_SIZE 0x0013
+#define RDD_DS_CONNECTION_TABLE_SIZE     32768
+#define RDD_DS_CONNECTION_TABLE_LOG2_SIZE     15
+#define US_CONNECTION_TABLE_ADDRESS 0x80000
+#define US_CONNECTION_TABLE_BYTE_SIZE 0x80000
+#define US_CONNECTION_TABLE_LOG2_BYTE_SIZE 0x0013
+#define RDD_US_CONNECTION_TABLE_SIZE     32768
+#define RDD_US_CONNECTION_TABLE_LOG2_SIZE     15
+#define CONTEXT_TABLE_ADDRESS 0x100000
+#define CONTEXT_TABLE_BYTE_SIZE 0x214200
+#define CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0016
+#define RDD_CONTEXT_TABLE_SIZE     16512
+#define RDD_CONTEXT_TABLE_LOG2_SIZE     15
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_ADDRESS 0x5d1500
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_BYTE_SIZE 0x00a0
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE     8
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_LOG2_SIZE     3
+#define DHD_RX_POST_DDR_BUFFER_ADDRESS 0x5c1100
+#define DHD_RX_POST_DDR_BUFFER_BYTE_SIZE 0x8000
+#define DHD_RX_POST_DDR_BUFFER_LOG2_BYTE_SIZE 0x000f
+#define RDD_DHD_RX_POST_DDR_BUFFER_SIZE     1024
+#define RDD_DHD_RX_POST_DDR_BUFFER_LOG2_SIZE     10
+#define DHD_RX_COMPLETE_DDR_BUFFER_ADDRESS 0x5c9100
+#define DHD_RX_COMPLETE_DDR_BUFFER_BYTE_SIZE 0x8000
+#define DHD_RX_COMPLETE_DDR_BUFFER_LOG2_BYTE_SIZE 0x000f
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE     1024
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_LOG2_SIZE     10
+#define DHD_TX_POST_DDR_BUFFER_ADDRESS 0x5d15a0
+#define DHD_TX_POST_DDR_BUFFER_BYTE_SIZE 0x1800
+#define DHD_TX_POST_DDR_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE     8
+#define RDD_DHD_TX_POST_DDR_BUFFER_LOG2_SIZE     3
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE2    16
+#define RDD_DHD_TX_POST_DDR_BUFFER_LOG2_SIZE2    4
+#define DHD_TX_COMPLETE_DDR_BUFFER_ADDRESS 0x5d2da0
+#define DHD_TX_COMPLETE_DDR_BUFFER_BYTE_SIZE 0x0100
+#define DHD_TX_COMPLETE_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE     16
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_LOG2_SIZE     4
+#define R2D_WR_ARR_DDR_BUFFER_ADDRESS 0x5d1100
+#define R2D_WR_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define R2D_WR_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_R2D_WR_ARR_DDR_BUFFER_SIZE     128
+#define RDD_R2D_WR_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define D2R_RD_ARR_DDR_BUFFER_ADDRESS 0x5d1200
+#define D2R_RD_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define D2R_RD_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_D2R_RD_ARR_DDR_BUFFER_SIZE     128
+#define RDD_D2R_RD_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define R2D_RD_ARR_DDR_BUFFER_ADDRESS 0x5d1300
+#define R2D_RD_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define R2D_RD_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_R2D_RD_ARR_DDR_BUFFER_SIZE     128
+#define RDD_R2D_RD_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define D2R_WR_ARR_DDR_BUFFER_ADDRESS 0x5d1400
+#define D2R_WR_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define D2R_WR_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_D2R_WR_ARR_DDR_BUFFER_SIZE     128
+#define RDD_D2R_WR_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define DHD_BACKUP_QUEUES_BUFFER_ADDRESS 0x600000
+#define DHD_BACKUP_QUEUES_BUFFER_BYTE_SIZE 0x100000
+#define DHD_BACKUP_QUEUES_BUFFER_LOG2_BYTE_SIZE 0x0014
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE     524288
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_LOG2_SIZE     19
+#define WLAN_MCAST_DHD_LIST_TABLE_ADDRESS 0x5c0000
+#define WLAN_MCAST_DHD_LIST_TABLE_BYTE_SIZE 0x1000
+#define WLAN_MCAST_DHD_LIST_TABLE_LOG2_BYTE_SIZE 0x000c
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_LOG2_SIZE     6
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_ADDRESS 0x5c1000
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_BYTE_SIZE 0x0001
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_LOG2_BYTE_SIZE 0x0001
+/* PSRAM */
+#endif
+#ifdef WL4908
+/* PRIVATE_A */
+#define INGRESS_HANDLER_BUFFER_ADDRESS 0x0000
+#define INGRESS_HANDLER_BUFFER_BYTE_SIZE 0x2000
+#define INGRESS_HANDLER_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_INGRESS_HANDLER_BUFFER_SIZE     32
+#define RDD_INGRESS_HANDLER_BUFFER_LOG2_SIZE     5
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS 0x2000
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_BYTE_SIZE 0x4000
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_LOG2_BYTE_SIZE 0x000e
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE     2048
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_LOG2_SIZE     11
+#define DS_CONNECTION_CONTEXT_BUFFER_ADDRESS 0x6000
+#define DS_CONNECTION_CONTEXT_BUFFER_BYTE_SIZE 0x0400
+#define DS_CONNECTION_CONTEXT_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_LOG2_SIZE     3
+#define DS_GSO_HEADER_BUFFER_ADDRESS 0x6400
+#define DS_GSO_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_GSO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_GSO_PSEUDO_HEADER_BUFFER_ADDRESS 0x6480
+#define DS_GSO_PSEUDO_HEADER_BUFFER_BYTE_SIZE 0x0028
+#define DS_GSO_PSEUDO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x64a8
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0008
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     2
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_ADDRESS 0x64b0
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_BYTE_SIZE 0x0010
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_SIZE     8
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_LOG2_SIZE     3
+#define DS_CPU_REASON_TO_METER_TABLE_ADDRESS 0x64c0
+#define DS_CPU_REASON_TO_METER_TABLE_BYTE_SIZE 0x0040
+#define DS_CPU_REASON_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE     64
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_LOG2_SIZE     6
+#define DS_GSO_CHUNK_BUFFER_ADDRESS 0x6500
+#define DS_GSO_CHUNK_BUFFER_BYTE_SIZE 0x0080
+#define DS_GSO_CHUNK_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_CPU_RX_METER_TABLE_ADDRESS 0x6580
+#define DS_CPU_RX_METER_TABLE_BYTE_SIZE 0x0080
+#define DS_CPU_RX_METER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_CPU_RX_METER_TABLE_SIZE     16
+#define RDD_DS_CPU_RX_METER_TABLE_LOG2_SIZE     4
+#define DS_POLICER_TABLE_ADDRESS 0x6600
+#define DS_POLICER_TABLE_BYTE_SIZE 0x0100
+#define DS_POLICER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_POLICER_TABLE_SIZE     16
+#define RDD_DS_POLICER_TABLE_LOG2_SIZE     4
+#define IPSEC_DS_BUFFER_POOL_ADDRESS 0x6700
+#define IPSEC_DS_BUFFER_POOL_BYTE_SIZE 0x0160
+#define IPSEC_DS_BUFFER_POOL_LOG2_BYTE_SIZE 0x0009
+#define RDD_IPSEC_DS_BUFFER_POOL_SIZE     2
+#define RDD_IPSEC_DS_BUFFER_POOL_LOG2_SIZE     1
+#define IPSEC_DS_SA_DESC_TABLE_ADDRESS 0x6860
+#define IPSEC_DS_SA_DESC_TABLE_BYTE_SIZE 0x0500
+#define IPSEC_DS_SA_DESC_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_IPSEC_DS_SA_DESC_TABLE_SIZE     16
+#define RDD_IPSEC_DS_SA_DESC_TABLE_LOG2_SIZE     4
+#define IPSEC_US_SA_DESC_TABLE_ADDRESS 0x6d60
+#define IPSEC_US_SA_DESC_TABLE_BYTE_SIZE 0x0500
+#define IPSEC_US_SA_DESC_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_IPSEC_US_SA_DESC_TABLE_SIZE     16
+#define RDD_IPSEC_US_SA_DESC_TABLE_LOG2_SIZE     4
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_ADDRESS 0x7260
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_BYTE_SIZE 0x0300
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_LOG2_SIZE     5
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x7560
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define DS_SPDSVC_CONTEXT_TABLE_ADDRESS 0x7580
+#define DS_SPDSVC_CONTEXT_TABLE_BYTE_SIZE 0x0050
+#define DS_SPDSVC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x75d0
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0010
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     3
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS 0x75e0
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_BYTE_SIZE 0x0100
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_LOG2_SIZE     5
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x76e0
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define WLAN_MCAST_CONTROL_TABLE_ADDRESS 0x7700
+#define WLAN_MCAST_CONTROL_TABLE_BYTE_SIZE 0x0094
+#define WLAN_MCAST_CONTROL_TABLE_LOG2_BYTE_SIZE 0x0008
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_ADDRESS 0x7794
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_BYTE_SIZE 0x0004
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DS_TOTAL_PPS_RATE_LIMITER_ADDRESS 0x7798
+#define DS_TOTAL_PPS_RATE_LIMITER_BYTE_SIZE 0x0008
+#define DS_TOTAL_PPS_RATE_LIMITER_LOG2_BYTE_SIZE 0x0003
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS 0x77a0
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_BYTE_SIZE 0x0020
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE     1
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE2    4
+#define RATE_LIMITER_REMAINDER_TABLE_ADDRESS 0x77c0
+#define RATE_LIMITER_REMAINDER_TABLE_BYTE_SIZE 0x0040
+#define RATE_LIMITER_REMAINDER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE     32
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS 0x7800
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_SIZE     8
+#define FC_MCAST_CONNECTION2_TABLE_ADDRESS 0x8000
+#define FC_MCAST_CONNECTION2_TABLE_BYTE_SIZE 0x0800
+#define FC_MCAST_CONNECTION2_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_FC_MCAST_CONNECTION2_TABLE_SIZE     128
+#define RDD_FC_MCAST_CONNECTION2_TABLE_LOG2_SIZE     7
+#define ETH_TX_QUEUES_POINTERS_TABLE_ADDRESS 0x8800
+#define ETH_TX_QUEUES_POINTERS_TABLE_BYTE_SIZE 0x0120
+#define ETH_TX_QUEUES_POINTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE     72
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_LOG2_SIZE     7
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_ADDRESS 0x8920
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_BYTE_SIZE 0x0020
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS 0x8940
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define SBPM_REPLY_ADDRESS 0x8980
+#define SBPM_REPLY_BYTE_SIZE 0x0080
+#define SBPM_REPLY_LOG2_BYTE_SIZE 0x0007
+#define DS_WAN_FLOW_TABLE_ADDRESS 0x8a00
+#define DS_WAN_FLOW_TABLE_BYTE_SIZE 0x0200
+#define DS_WAN_FLOW_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_WAN_FLOW_TABLE_SIZE     256
+#define RDD_DS_WAN_FLOW_TABLE_LOG2_SIZE     8
+#define DS_CONNECTION_CONTEXT_REMAINING_BUFFER_ADDRESS 0x8c00
+#define DS_CONNECTION_CONTEXT_REMAINING_BUFFER_BYTE_SIZE 0x0260
+#define DS_CONNECTION_CONTEXT_REMAINING_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_LOG2_SIZE     3
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS 0x8e60
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_BYTE_SIZE 0x0020
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_SIZE     2
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS 0x8e80
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_BYTE_SIZE 0x0080
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE     1
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE2    4
+#define DS_FORWARDING_MATRIX_TABLE_ADDRESS 0x8f00
+#define DS_FORWARDING_MATRIX_TABLE_BYTE_SIZE 0x0090
+#define DS_FORWARDING_MATRIX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_DS_FORWARDING_MATRIX_TABLE_LOG2_SIZE     4
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2    16
+#define RDD_DS_FORWARDING_MATRIX_TABLE_LOG2_SIZE2    4
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0x8f90
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0010
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0x8fa0
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define LAN_TX_ACB_COUNTER_TABLE_ADDRESS 0x8fc0
+#define LAN_TX_ACB_COUNTER_TABLE_BYTE_SIZE 0x0040
+#define LAN_TX_ACB_COUNTER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_LAN_TX_ACB_COUNTER_TABLE_SIZE     64
+#define RDD_LAN_TX_ACB_COUNTER_TABLE_LOG2_SIZE     6
+#define DS_WAN_UDP_FILTER_TABLE_ADDRESS 0x9000
+#define DS_WAN_UDP_FILTER_TABLE_BYTE_SIZE 0x0200
+#define DS_WAN_UDP_FILTER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_WAN_UDP_FILTER_TABLE_SIZE     32
+#define RDD_DS_WAN_UDP_FILTER_TABLE_LOG2_SIZE     5
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0x9200
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9240
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9280
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_ADDRESS 0x92c0
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_BYTE_SIZE 0x0030
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINA_PARAM_ADDRESS 0x92f0
+#define RUNNER_FWTRACE_MAINA_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINA_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_LOG2_SIZE     1
+#define DS_RATE_LIMITER_TABLE_ADDRESS 0x9300
+#define DS_RATE_LIMITER_TABLE_BYTE_SIZE 0x0100
+#define DS_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_RATE_LIMITER_TABLE_SIZE     32
+#define RDD_DS_RATE_LIMITER_TABLE_LOG2_SIZE     5
+#define ETH_TX_QUEUES_TABLE_ADDRESS 0x9400
+#define ETH_TX_QUEUES_TABLE_BYTE_SIZE 0x0480
+#define ETH_TX_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_ETH_TX_QUEUES_TABLE_SIZE     72
+#define RDD_ETH_TX_QUEUES_TABLE_LOG2_SIZE     7
+#define INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS 0x9880
+#define INGRESS_HANDLER_SKB_DATA_POINTER_BYTE_SIZE 0x0080
+#define INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_SIZE     5
+#define DS_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x9900
+#define DS_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x9980
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define FC_MCAST_PORT_HEADER_BUFFER_ADDRESS 0x9a00
+#define FC_MCAST_PORT_HEADER_BUFFER_BYTE_SIZE 0x0200
+#define FC_MCAST_PORT_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE     8
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_LOG2_SIZE     3
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2    64
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_LOG2_SIZE2    6
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_ADDRESS 0x9c00
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_BYTE_SIZE 0x0200
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_LOG2_BYTE_SIZE 0x0009
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE     64
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_LOG2_SIZE     6
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_ADDRESS 0x9e00
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_BYTE_SIZE 0x0200
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_LOG2_SIZE     3
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_ADDRESS 0xa000
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_BYTE_SIZE 0x0200
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE     64
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_CPU_TX_BBH_DESCRIPTORS_ADDRESS 0xa200
+#define DS_CPU_TX_BBH_DESCRIPTORS_BYTE_SIZE 0x0100
+#define DS_CPU_TX_BBH_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_LOG2_SIZE     5
+#define DS_PROFILING_BUFFER_PICO_RUNNER_ADDRESS 0xa300
+#define DS_PROFILING_BUFFER_PICO_RUNNER_BYTE_SIZE 0x0100
+#define DS_PROFILING_BUFFER_PICO_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define GSO_PICO_QUEUE_ADDRESS 0xa400
+#define GSO_PICO_QUEUE_BYTE_SIZE 0x0200
+#define GSO_PICO_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_GSO_PICO_QUEUE_SIZE     64
+#define RDD_GSO_PICO_QUEUE_LOG2_SIZE     6
+#define DHD_TX_POST_PD_INGRESS_QUEUE_ADDRESS 0xa600
+#define DHD_TX_POST_PD_INGRESS_QUEUE_BYTE_SIZE 0x0100
+#define DHD_TX_POST_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_SIZE     32
+#define RDD_DHD_TX_POST_PD_INGRESS_QUEUE_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS 0xa700
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_BYTE_SIZE 0x0080
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_SIZE     4
+#define ETH_TX_LOCAL_REGISTERS_ADDRESS 0xa780
+#define ETH_TX_LOCAL_REGISTERS_BYTE_SIZE 0x0048
+#define ETH_TX_LOCAL_REGISTERS_LOG2_BYTE_SIZE 0x0007
+#define RDD_ETH_TX_LOCAL_REGISTERS_SIZE     9
+#define RDD_ETH_TX_LOCAL_REGISTERS_LOG2_SIZE     4
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS 0xa7c8
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_BYTE_SIZE 0x0008
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_SIZE     1
+#define RUNNER_FWTRACE_PICOA_PARAM_ADDRESS 0xa7d0
+#define RUNNER_FWTRACE_PICOA_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_PICOA_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_LOG2_SIZE     1
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xa7e0
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define IPSEC_DS_QUEUE_ADDRESS 0xa800
+#define IPSEC_DS_QUEUE_BYTE_SIZE 0x0200
+#define IPSEC_DS_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_IPSEC_DS_QUEUE_SIZE     64
+#define RDD_IPSEC_DS_QUEUE_LOG2_SIZE     6
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS 0xaa00
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x00c0
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE     4
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_ADDRESS 0xaac0
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0030
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE     3
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_LOG2_SIZE     2
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS 0xaaf0
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_BYTE_SIZE 0x0010
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_BYTE_SIZE 0x0004
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     8
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_SIZE     3
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0xab00
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     16
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     4
+#define DS_QUEUE_PROFILE_TABLE_ADDRESS 0xab80
+#define DS_QUEUE_PROFILE_TABLE_BYTE_SIZE 0x0080
+#define DS_QUEUE_PROFILE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_QUEUE_PROFILE_TABLE_SIZE     8
+#define RDD_DS_QUEUE_PROFILE_TABLE_LOG2_SIZE     3
+#define CPU_TX_FAST_QUEUE_ADDRESS 0xac00
+#define CPU_TX_FAST_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_FAST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_FAST_QUEUE_SIZE     16
+#define RDD_CPU_TX_FAST_QUEUE_LOG2_SIZE     4
+#define DS_SQ_ENQUEUE_QUEUE_ADDRESS 0xac80
+#define DS_SQ_ENQUEUE_QUEUE_BYTE_SIZE 0x0040
+#define DS_SQ_ENQUEUE_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_SQ_ENQUEUE_QUEUE_SIZE     64
+#define RDD_DS_SQ_ENQUEUE_QUEUE_LOG2_SIZE     6
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_ADDRESS 0xacc0
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_BYTE_SIZE 0x0040
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define CPU_TX_PICO_QUEUE_ADDRESS 0xad00
+#define CPU_TX_PICO_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_PICO_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_PICO_QUEUE_SIZE     16
+#define RDD_CPU_TX_PICO_QUEUE_LOG2_SIZE     4
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS 0xad80
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_LOG2_SIZE     6
+#define MULTICAST_HEADER_BUFFER_ADDRESS 0xadc0
+#define MULTICAST_HEADER_BUFFER_BYTE_SIZE 0x0040
+#define MULTICAST_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_ADDRESS 0xae00
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_BYTE_SIZE 0x0080
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE     16
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_LOG2_SIZE     4
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_ADDRESS 0xae80
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE     64
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xaec0
+#define DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xaee0
+#define DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define CPU_RX_PD_INGRESS_QUEUE_ADDRESS 0xaf00
+#define CPU_RX_PD_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define CPU_RX_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE     16
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_LOG2_SIZE     4
+#define DS_ROUTER_INGRESS_QUEUE_ADDRESS 0xaf80
+#define DS_ROUTER_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_ROUTER_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_ROUTER_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_ROUTER_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xafc0
+#define DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define DS_NULL_BUFFER_ADDRESS 0xafe0
+#define DS_NULL_BUFFER_BYTE_SIZE 0x0018
+#define DS_NULL_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_NULL_BUFFER_SIZE     3
+#define RDD_DS_NULL_BUFFER_LOG2_SIZE     2
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS 0xaff8
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_BYTE_SIZE 0x0008
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0003
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_ADDRESS 0xb000
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE     16
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_LOG2_SIZE     4
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS 0xb080
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS 0xb0c0
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define DS_DHD_TX_POST_HEADER_SCRATCH_ADDRESS 0xb100
+#define DS_DHD_TX_POST_HEADER_SCRATCH_BYTE_SIZE 0x0080
+#define DS_DHD_TX_POST_HEADER_SCRATCH_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE     4
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_LOG2_SIZE     2
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS 0xb180
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_BYTE_SIZE 0x00a0
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_LOG2_BYTE_SIZE 0x0008
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE     5
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_LOG2_SIZE     3
+#define DS_DEBUG_BUFFER_ADDRESS 0xb220
+#define DS_DEBUG_BUFFER_BYTE_SIZE 0x0080
+#define DS_DEBUG_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_DEBUG_BUFFER_SIZE     32
+#define RDD_DS_DEBUG_BUFFER_LOG2_SIZE     5
+#define DHD_COMPLETE_RING_BUFFER_ADDRESS 0xb2a0
+#define DHD_COMPLETE_RING_BUFFER_BYTE_SIZE 0x0018
+#define DHD_COMPLETE_RING_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DHD_COMPLETE_RING_BUFFER_SIZE     3
+#define RDD_DHD_COMPLETE_RING_BUFFER_LOG2_SIZE     2
+#define DS_FAST_MALLOC_RESULT_TABLE_ADDRESS 0xb2b8
+#define DS_FAST_MALLOC_RESULT_TABLE_BYTE_SIZE 0x0008
+#define DS_FAST_MALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_FAST_MALLOC_RESULT_TABLE_SIZE     2
+#define RDD_DS_FAST_MALLOC_RESULT_TABLE_LOG2_SIZE     1
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xb2c0
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0050
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE     10
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_LOG2_SIZE     4
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ADDRESS 0xb310
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_BYTE_SIZE 0x000a
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0004
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xb31a
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_ADDRESS 0xb31c
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_FW_MAC_ADDRS_ADDRESS 0xb320
+#define DS_FW_MAC_ADDRS_BYTE_SIZE 0x0080
+#define DS_FW_MAC_ADDRS_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_FW_MAC_ADDRS_SIZE     16
+#define RDD_DS_FW_MAC_ADDRS_LOG2_SIZE     4
+#define DS_CPU_PARAMETERS_BLOCK_ADDRESS 0xb3a0
+#define DS_CPU_PARAMETERS_BLOCK_BYTE_SIZE 0x0014
+#define DS_CPU_PARAMETERS_BLOCK_LOG2_BYTE_SIZE 0x0005
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xb3b4
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_PICO_MALLOC_RESULT_TABLE_ADDRESS 0xb3b8
+#define DS_PICO_MALLOC_RESULT_TABLE_BYTE_SIZE 0x0008
+#define DS_PICO_MALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_PICO_MALLOC_RESULT_TABLE_SIZE     2
+#define RDD_DS_PICO_MALLOC_RESULT_TABLE_LOG2_SIZE     1
+#define FC_MCAST_CONNECTION_TABLE_PLUS_ADDRESS 0xb3c0
+#define FC_MCAST_CONNECTION_TABLE_PLUS_BYTE_SIZE 0x0014
+#define FC_MCAST_CONNECTION_TABLE_PLUS_LOG2_BYTE_SIZE 0x0005
+#define DS_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xb3d4
+#define DS_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS 0xb3d8
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_BYTE_SIZE 0x0008
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_SIZE     3
+#define DS_DATA_POINTER_DUMMY_TARGET_ADDRESS 0xb3e0
+#define DS_DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0014
+#define DS_DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE     5
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_LOG2_SIZE     3
+#define DS_BPM_DDR_BUFFERS_BASE_ADDRESS 0xb3f4
+#define DS_BPM_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_ADDRESS 0xb3f8
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_BYTE_SIZE 0x0006
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xb3fe
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define GPON_RX_DIRECT_DESCRIPTORS_ADDRESS 0xb400
+#define GPON_RX_DIRECT_DESCRIPTORS_BYTE_SIZE 0x0100
+#define GPON_RX_DIRECT_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE     32
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_LOG2_SIZE     5
+#define DS_GSO_CONTEXT_TABLE_ADDRESS 0xb500
+#define DS_GSO_CONTEXT_TABLE_BYTE_SIZE 0x0084
+#define DS_GSO_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0008
+#define DS_BPM_DDR_1_BUFFERS_BASE_ADDRESS 0xb584
+#define DS_BPM_DDR_1_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_1_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_CONNECTION_TABLE_CONFIG_ADDRESS 0xb588
+#define DS_CONNECTION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONNECTION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define DS_CONTEXT_TABLE_CONFIG_ADDRESS 0xb58c
+#define DS_CONTEXT_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONTEXT_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS 0xb590
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_BYTE_SIZE 0x0010
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_BYTE_SIZE 0x0004
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     8
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_SIZE     3
+#define SERVICE_QUEUES_WLAN_SCRATCH_ADDRESS 0xb5a0
+#define SERVICE_QUEUES_WLAN_SCRATCH_BYTE_SIZE 0x0014
+#define SERVICE_QUEUES_WLAN_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS 0xb5b4
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_BYTE_SIZE 0x0004
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_SIZE     2
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS 0xb5b8
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_BYTE_SIZE 0x0004
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_SIZE     2
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_ADDRESS 0xb5bc
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_BYTE_SIZE 0x0004
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_LOG2_BYTE_SIZE 0x0002
+#define DS_DHD_FLOW_RING_DROP_COUNTER_ADDRESS 0xb5c0
+#define DS_DHD_FLOW_RING_DROP_COUNTER_BYTE_SIZE 0x0014
+#define DS_DHD_FLOW_RING_DROP_COUNTER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_LOG2_SIZE     3
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_ADDRESS 0xb5d4
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS 0xb5d8
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_BYTE_SIZE 0x0008
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_SIZE     3
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb5e0
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define HASH_BUFFER_ADDRESS 0xb5f0
+#define HASH_BUFFER_BYTE_SIZE 0x0010
+#define HASH_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define DS_GSO_DESC_TABLE_ADDRESS 0xb600
+#define DS_GSO_DESC_TABLE_BYTE_SIZE 0x0080
+#define DS_GSO_DESC_TABLE_LOG2_BYTE_SIZE 0x0007
+#define DS_DHD_TX_POST_INGRESS_QUEUE_ADDRESS 0xb680
+#define DS_DHD_TX_POST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_DHD_TX_POST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_SYSTEM_CONFIGURATION_ADDRESS 0xb6c0
+#define DS_SYSTEM_CONFIGURATION_BYTE_SIZE 0x0024
+#define DS_SYSTEM_CONFIGURATION_LOG2_BYTE_SIZE 0x0006
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xb6e4
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_ADDRESS 0xb6e8
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_BYTE_SIZE 0x0008
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_LOG2_BYTE_SIZE 0x0003
+#define RUNNER_FLOW_IH_RESPONSE_ADDRESS 0xb6f0
+#define RUNNER_FLOW_IH_RESPONSE_BYTE_SIZE 0x0008
+#define RUNNER_FLOW_IH_RESPONSE_LOG2_BYTE_SIZE 0x0003
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_ADDRESS 0xb6f8
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_BYTE_SIZE 0x0008
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_LOG2_BYTE_SIZE 0x0003
+#define WLAN_MCAST_INGRESS_QUEUE_ADDRESS 0xb700
+#define WLAN_MCAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define WLAN_MCAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE     64
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb740
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS 0xb750
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_BYTE_SIZE 0x0010
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_SIZE     3
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS 0xb760
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_BYTE_SIZE 0x0010
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define IPSEC_DS_SA_DESC_CAM_TABLE_ADDRESS 0xb770
+#define IPSEC_DS_SA_DESC_CAM_TABLE_BYTE_SIZE 0x0020
+#define IPSEC_DS_SA_DESC_CAM_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE     16
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_LOG2_SIZE     4
+#define IPSEC_US_SA_DESC_CAM_TABLE_ADDRESS 0xb790
+#define IPSEC_US_SA_DESC_CAM_TABLE_BYTE_SIZE 0x0020
+#define IPSEC_US_SA_DESC_CAM_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE     16
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_LOG2_SIZE     4
+#define ETH_TX_SCRATCH_ADDRESS 0xb7b0
+#define ETH_TX_SCRATCH_BYTE_SIZE 0x0010
+#define ETH_TX_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define RDD_ETH_TX_SCRATCH_SIZE     16
+#define RDD_ETH_TX_SCRATCH_LOG2_SIZE     4
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_ADDRESS 0xb7c0
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_BYTE_SIZE 0x0018
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_LOG2_BYTE_SIZE 0x0005
+#define GSO_TX_DHD_L2_BUFFER_ADDRESS 0xb7d8
+#define GSO_TX_DHD_L2_BUFFER_BYTE_SIZE 0x0016
+#define GSO_TX_DHD_L2_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_GSO_TX_DHD_L2_BUFFER_SIZE     22
+#define RDD_GSO_TX_DHD_L2_BUFFER_LOG2_SIZE     5
+#define IPTV_COUNTERS_BUFFER_ADDRESS 0xb7ee
+#define IPTV_COUNTERS_BUFFER_BYTE_SIZE 0x0002
+#define IPTV_COUNTERS_BUFFER_LOG2_BYTE_SIZE 0x0001
+#define CPU_TX_DHD_L2_BUFFER_ADDRESS 0xb7f0
+#define CPU_TX_DHD_L2_BUFFER_BYTE_SIZE 0x0016
+#define CPU_TX_DHD_L2_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_CPU_TX_DHD_L2_BUFFER_SIZE     22
+#define RDD_CPU_TX_DHD_L2_BUFFER_LOG2_SIZE     5
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xb806
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xb808
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define SPDSVC_HOST_BUF_PTR_ADDRESS 0xb80c
+#define SPDSVC_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define SPDSVC_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_ADDRESS 0xb810
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_BYTE_SIZE 0x0010
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_ADDRESS 0xb820
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_ADDRESS 0xb830
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_ADDRESS 0xb840
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_ADDRESS 0xb850
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_BYTE_SIZE 0x0005
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_LOG2_BYTE_SIZE 0x0003
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE     5
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_LOG2_SIZE     3
+#define ETH_TX_EMACS_STATUS_ADDRESS 0xb855
+#define ETH_TX_EMACS_STATUS_BYTE_SIZE 0x0001
+#define ETH_TX_EMACS_STATUS_LOG2_BYTE_SIZE 0x0001
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_ADDRESS 0xb856
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_BYTE_SIZE 0x0002
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define HASH_BASED_FORWARDING_PORT_TABLE_ADDRESS 0xb858
+#define HASH_BASED_FORWARDING_PORT_TABLE_BYTE_SIZE 0x0004
+#define HASH_BASED_FORWARDING_PORT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE     4
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_LOG2_SIZE     2
+#define DS_CPU_TX_DATA_POINTER_DUMMY_TARGET_ADDRESS 0xb85c
+#define DS_CPU_TX_DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0004
+#define DS_CPU_TX_DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0002
+#define FIREWALL_IPV6_R16_BUFFER_ADDRESS 0xb860
+#define FIREWALL_IPV6_R16_BUFFER_BYTE_SIZE 0x0004
+#define FIREWALL_IPV6_R16_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb864
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_ADDRESS 0xb866
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xb868
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_ADDRESS 0xb86a
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_BYTE_SIZE 0x0002
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_LOG2_BYTE_SIZE 0x0001
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_ADDRESS 0xb86c
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_BYTE_SIZE 0x0002
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_LOG2_BYTE_SIZE 0x0001
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_ADDRESS 0xb86e
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS 0xb870
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_ADDRESS 0xb872
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_BYTE_SIZE 0x0002
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define GSO_DESC_PTR_ADDRESS 0xb874
+#define GSO_DESC_PTR_BYTE_SIZE 0x0004
+#define GSO_DESC_PTR_LOG2_BYTE_SIZE 0x0002
+#define GSO_TX_DHD_HOST_BUF_PTR_ADDRESS 0xb878
+#define GSO_TX_DHD_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define GSO_TX_DHD_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE     4
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_LOG2_SIZE     2
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_ADDRESS 0xb87c
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_BYTE_SIZE 0x0004
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define CPU_TX_DHD_HOST_BUF_PTR_ADDRESS 0xb880
+#define CPU_TX_DHD_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define CPU_TX_DHD_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE     4
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_LOG2_SIZE     2
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_ADDRESS 0xb884
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_BYTE_SIZE 0x0004
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_LOG2_BYTE_SIZE 0x0002
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_ADDRESS 0xb888
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_BYTE_SIZE 0x0002
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_LOG2_BYTE_SIZE 0x0001
+#define DS_MEMLIB_SEMAPHORE_ADDRESS 0xb88a
+#define DS_MEMLIB_SEMAPHORE_BYTE_SIZE 0x0002
+#define DS_MEMLIB_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define WAN_PHYSICAL_PORT_ADDRESS 0xb88c
+#define WAN_PHYSICAL_PORT_BYTE_SIZE 0x0002
+#define WAN_PHYSICAL_PORT_LOG2_BYTE_SIZE 0x0001
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb88e
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_RUNNER_CONGESTION_STATE_ADDRESS 0xb890
+#define DS_RUNNER_CONGESTION_STATE_BYTE_SIZE 0x0002
+#define DS_RUNNER_CONGESTION_STATE_LOG2_BYTE_SIZE 0x0001
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_ADDRESS 0xb892
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_BYTE_SIZE 0x0002
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_LOG2_BYTE_SIZE 0x0001
+#define GSO_PICO_QUEUE_PTR_ADDRESS 0xb894
+#define GSO_PICO_QUEUE_PTR_BYTE_SIZE 0x0002
+#define GSO_PICO_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_ADDRESS 0xb896
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_BYTE_SIZE 0x0002
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_ADDRESS 0xb898
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_BYTE_SIZE 0x0002
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_ADDRESS 0xb89a
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_BYTE_SIZE 0x0002
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_ADDRESS 0xb89c
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_BYTE_SIZE 0x0002
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_DDR_SA_DESC_SIZE_ADDRESS 0xb89e
+#define IPSEC_DS_DDR_SA_DESC_SIZE_BYTE_SIZE 0x0002
+#define IPSEC_DS_DDR_SA_DESC_SIZE_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_QUEUE_PTR_ADDRESS 0xb8a0
+#define IPSEC_DS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define IPSEC_DS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_IP_LENGTH_ADDRESS 0xb8a2
+#define IPSEC_DS_IP_LENGTH_BYTE_SIZE 0x0002
+#define IPSEC_DS_IP_LENGTH_LOG2_BYTE_SIZE 0x0001
+#define PRIVATE_A_DUMMY_STORE_ADDRESS 0xb8a4
+#define PRIVATE_A_DUMMY_STORE_BYTE_SIZE 0x0001
+#define PRIVATE_A_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_ADDRESS 0xb8a5
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_BYTE_SIZE 0x0001
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_LOG2_BYTE_SIZE 0x0001
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xb8a6
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xb8a7
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define CPU_TX_DS_PICO_SEMAPHORE_ADDRESS 0xb8a8
+#define CPU_TX_DS_PICO_SEMAPHORE_BYTE_SIZE 0x0001
+#define CPU_TX_DS_PICO_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define DS_FC_GLOBAL_CFG_ADDRESS 0xb8a9
+#define DS_FC_GLOBAL_CFG_BYTE_SIZE 0x0001
+#define DS_FC_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_ADDRESS 0xb8aa
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_ADDRESS 0xb8ab
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_PACKET_BUFFER_SIZE_ASR_8_ADDRESS 0xb8ac
+#define DS_PACKET_BUFFER_SIZE_ASR_8_BYTE_SIZE 0x0001
+#define DS_PACKET_BUFFER_SIZE_ASR_8_LOG2_BYTE_SIZE 0x0001
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb8ad
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb8ae
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_ADDRESS 0xb8af
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_BYTE_SIZE 0x0001
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS 0xb8b0
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_ADDRESS 0xb8b1
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_LOG2_BYTE_SIZE 0x0001
+#define DS_IH_CONGESTION_THRESHOLD_ADDRESS 0xb8b2
+#define DS_IH_CONGESTION_THRESHOLD_BYTE_SIZE 0x0001
+#define DS_IH_CONGESTION_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define DS_FAST_MALLOC_RESULT_MUTEX_ADDRESS 0xb8b3
+#define DS_FAST_MALLOC_RESULT_MUTEX_BYTE_SIZE 0x0001
+#define DS_FAST_MALLOC_RESULT_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DS_PICO_MALLOC_RESULT_MUTEX_ADDRESS 0xb8b4
+#define DS_PICO_MALLOC_RESULT_MUTEX_BYTE_SIZE 0x0001
+#define DS_PICO_MALLOC_RESULT_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DS_RX_SBPM_TO_FPM_COPY_SEMAPHORE_ADDRESS 0xb8b5
+#define DS_RX_SBPM_TO_FPM_COPY_SEMAPHORE_BYTE_SIZE 0x0001
+#define DS_RX_SBPM_TO_FPM_COPY_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define DS_FW_MAC_ADDRS_COUNT_ADDRESS 0xb8b6
+#define DS_FW_MAC_ADDRS_COUNT_BYTE_SIZE 0x0001
+#define DS_FW_MAC_ADDRS_COUNT_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_DMA_SYNCHRONIZATION_ADDRESS 0xb8b7
+#define DS_DHD_DMA_SYNCHRONIZATION_BYTE_SIZE 0x0001
+#define DS_DHD_DMA_SYNCHRONIZATION_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_SEMAPHORE_ADDRESS 0xb8b8
+#define DHD_TX_POST_CPU_SEMAPHORE_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define RING_CACHE_DHD_TXPOST_MUTEX_ADDRESS 0xb8b9
+#define RING_CACHE_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define RING_CACHE_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define COMMON_DHD_TXPOST_MUTEX_ADDRESS 0xb8ba
+#define COMMON_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define COMMON_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define TXCPL_INT_DHD_TXPOST_MUTEX_ADDRESS 0xb8bb
+#define TXCPL_INT_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define TXCPL_INT_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_ADDRESS 0xb8bc
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_BYTE_SIZE 0x0001
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_ADDRESS 0xb8bd
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_BYTE_SIZE 0x0001
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_LOG2_BYTE_SIZE 0x0001
+#define ETH_TX_MAC_TABLE_ADDRESS 0xbb00
+#define ETH_TX_MAC_TABLE_BYTE_SIZE 0x0100
+#define ETH_TX_MAC_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH_TX_MAC_TABLE_SIZE     8
+#define RDD_ETH_TX_MAC_TABLE_LOG2_SIZE     3
+#define GPON_RX_NORMAL_DESCRIPTORS_ADDRESS 0xbe00
+#define GPON_RX_NORMAL_DESCRIPTORS_BYTE_SIZE 0x0100
+#define GPON_RX_NORMAL_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE     32
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_LOG2_SIZE     5
+/* PRIVATE_B */
+#define US_INGRESS_HANDLER_BUFFER_ADDRESS 0x0000
+#define US_INGRESS_HANDLER_BUFFER_BYTE_SIZE 0x2000
+#define US_INGRESS_HANDLER_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_US_INGRESS_HANDLER_BUFFER_SIZE     32
+#define RDD_US_INGRESS_HANDLER_BUFFER_LOG2_SIZE     5
+#define US_CSO_CHUNK_BUFFER_ADDRESS 0x2000
+#define US_CSO_CHUNK_BUFFER_BYTE_SIZE 0x0080
+#define US_CSO_CHUNK_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define US_CSO_PSEUDO_HEADER_BUFFER_ADDRESS 0x2080
+#define US_CSO_PSEUDO_HEADER_BUFFER_BYTE_SIZE 0x0028
+#define US_CSO_PSEUDO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x20a8
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0008
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     2
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_ADDRESS 0x20b0
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_BYTE_SIZE 0x0010
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_SIZE     8
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_LOG2_SIZE     3
+#define US_CPU_REASON_TO_METER_TABLE_ADDRESS 0x20c0
+#define US_CPU_REASON_TO_METER_TABLE_BYTE_SIZE 0x0040
+#define US_CPU_REASON_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_REASON_TO_METER_TABLE_SIZE     64
+#define RDD_US_CPU_REASON_TO_METER_TABLE_LOG2_SIZE     6
+#define US_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS 0x2100
+#define US_MAIN_PROFILING_BUFFER_RUNNER_BYTE_SIZE 0x0100
+#define US_MAIN_PROFILING_BUFFER_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_LOG2_SIZE     5
+#define US_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS 0x2200
+#define US_FREE_PACKET_DESCRIPTORS_POOL_BYTE_SIZE 0x6000
+#define US_FREE_PACKET_DESCRIPTORS_POOL_LOG2_BYTE_SIZE 0x000f
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE     3072
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_LOG2_SIZE     12
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS 0x8200
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_BYTE_SIZE 0x0180
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE     3
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE2    4
+#define US_QUEUE_PROFILE_TABLE_ADDRESS 0x8380
+#define US_QUEUE_PROFILE_TABLE_BYTE_SIZE 0x0080
+#define US_QUEUE_PROFILE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_QUEUE_PROFILE_TABLE_SIZE     8
+#define RDD_US_QUEUE_PROFILE_TABLE_LOG2_SIZE     3
+#define WAN_CHANNELS_8_39_TABLE_ADDRESS 0x8400
+#define WAN_CHANNELS_8_39_TABLE_BYTE_SIZE 0x0400
+#define WAN_CHANNELS_8_39_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WAN_CHANNELS_8_39_TABLE_SIZE     32
+#define RDD_WAN_CHANNELS_8_39_TABLE_LOG2_SIZE     5
+#define US_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x8800
+#define US_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0180
+#define US_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE     3
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_LOG2_SIZE     2
+#define US_SBPM_REPLY_ADDRESS 0x8980
+#define US_SBPM_REPLY_BYTE_SIZE 0x0080
+#define US_SBPM_REPLY_LOG2_BYTE_SIZE 0x0007
+#define US_POLICER_TABLE_ADDRESS 0x8a00
+#define US_POLICER_TABLE_BYTE_SIZE 0x0100
+#define US_POLICER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_POLICER_TABLE_SIZE     16
+#define RDD_US_POLICER_TABLE_LOG2_SIZE     4
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_ADDRESS 0x8b00
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_BYTE_SIZE 0x0100
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE     2
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_LOG2_SIZE     1
+#define US_WAN_FLOW_TABLE_ADDRESS 0x8c00
+#define US_WAN_FLOW_TABLE_BYTE_SIZE 0x0400
+#define US_WAN_FLOW_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_US_WAN_FLOW_TABLE_SIZE     256
+#define RDD_US_WAN_FLOW_TABLE_LOG2_SIZE     8
+#define US_CPU_TX_BBH_DESCRIPTORS_ADDRESS 0x9000
+#define US_CPU_TX_BBH_DESCRIPTORS_BYTE_SIZE 0x0100
+#define US_CPU_TX_BBH_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_LOG2_SIZE     5
+#define US_FORWARDING_MATRIX_TABLE_ADDRESS 0x9100
+#define US_FORWARDING_MATRIX_TABLE_BYTE_SIZE 0x0090
+#define US_FORWARDING_MATRIX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_US_FORWARDING_MATRIX_TABLE_LOG2_SIZE     4
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE2    16
+#define RDD_US_FORWARDING_MATRIX_TABLE_LOG2_SIZE2    4
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x9190
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0010
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     3
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x91a0
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_ADDRESS 0x91c0
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_BYTE_SIZE 0x0040
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE     8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_SIZE     3
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2    8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_SIZE2    3
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS 0x9200
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9240
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9280
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x92c0
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define US_FC_L2_UCAST_TUPLE_BUFFER_ADDRESS 0x92e0
+#define US_FC_L2_UCAST_TUPLE_BUFFER_BYTE_SIZE 0x0020
+#define US_FC_L2_UCAST_TUPLE_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define US_RATE_LIMITER_TABLE_ADDRESS 0x9300
+#define US_RATE_LIMITER_TABLE_BYTE_SIZE 0x0080
+#define US_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_RATE_LIMITER_TABLE_SIZE     16
+#define RDD_US_RATE_LIMITER_TABLE_LOG2_SIZE     4
+#define US_CPU_RX_METER_TABLE_ADDRESS 0x9380
+#define US_CPU_RX_METER_TABLE_BYTE_SIZE 0x0080
+#define US_CPU_RX_METER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_RX_METER_TABLE_SIZE     16
+#define RDD_US_CPU_RX_METER_TABLE_LOG2_SIZE     4
+#define US_CONNECTION_CONTEXT_BUFFER_ADDRESS 0x9400
+#define US_CONNECTION_CONTEXT_BUFFER_BYTE_SIZE 0x0400
+#define US_CONNECTION_CONTEXT_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE     8
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS 0x9800
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_SIZE     8
+#define WAN_CHANNELS_0_7_TABLE_ADDRESS 0xa000
+#define WAN_CHANNELS_0_7_TABLE_BYTE_SIZE 0x02c0
+#define WAN_CHANNELS_0_7_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WAN_CHANNELS_0_7_TABLE_SIZE     8
+#define RDD_WAN_CHANNELS_0_7_TABLE_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS 0xa2c0
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_BYTE_SIZE 0x0020
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_SIZE     2
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xa2e0
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS 0xa300
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_BYTE_SIZE 0x0080
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_SIZE     5
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0xa380
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define US_CONNECTION_CONTEXT_REMAINING_BUFFER_ADDRESS 0xa400
+#define US_CONNECTION_CONTEXT_REMAINING_BUFFER_BYTE_SIZE 0x0260
+#define US_CONNECTION_CONTEXT_REMAINING_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE     8
+#define RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_LOG2_SIZE     3
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xa660
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS 0xa680
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_BYTE_SIZE 0x0080
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_SIZE     4
+#define US_PROFILING_BUFFER_PICO_RUNNER_ADDRESS 0xa700
+#define US_PROFILING_BUFFER_PICO_RUNNER_BYTE_SIZE 0x0100
+#define US_PROFILING_BUFFER_PICO_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS 0xa800
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_BYTE_SIZE 0x0060
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE     3
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE2    4
+#define DHD_RX_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xa860
+#define DHD_RX_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define DHD_RX_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_ADDRESS 0xa880
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_BYTE_SIZE 0x0060
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xa8e0
+#define US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define DHD_RX_POST_FLOW_RING_BUFFER_ADDRESS 0xa900
+#define DHD_RX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x0060
+#define DHD_RX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xa960
+#define US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xa980
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0001
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define PRIVATE_B_DUMMY_STORE_ADDRESS 0xa981
+#define PRIVATE_B_DUMMY_STORE_BYTE_SIZE 0x0001
+#define PRIVATE_B_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xa982
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_ADDRESS 0xa984
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_BYTE_SIZE 0x0004
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_LOG2_BYTE_SIZE 0x0002
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS 0xa988
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_BYTE_SIZE 0x0001
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xa989
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xa98a
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_ADDRESS 0xa98c
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xa990
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0028
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0006
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE     40
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_LOG2_SIZE     6
+#define US_TOTAL_PPS_RATE_LIMITER_ADDRESS 0xa9b8
+#define US_TOTAL_PPS_RATE_LIMITER_BYTE_SIZE 0x0008
+#define US_TOTAL_PPS_RATE_LIMITER_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_ADDRESS 0xa9c0
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_BYTE_SIZE 0x0040
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define US_INGRESS_RATE_LIMITER_TABLE_ADDRESS 0xaa00
+#define US_INGRESS_RATE_LIMITER_TABLE_BYTE_SIZE 0x0050
+#define US_INGRESS_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE     5
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_LOG2_SIZE     3
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0xaa50
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0010
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xaa60
+#define US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define US_SPDSVC_CONTEXT_TABLE_ADDRESS 0xaa80
+#define US_SPDSVC_CONTEXT_TABLE_BYTE_SIZE 0x0050
+#define US_SPDSVC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RUNNER_FWTRACE_MAINB_PARAM_ADDRESS 0xaad0
+#define RUNNER_FWTRACE_MAINB_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINB_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_LOG2_SIZE     1
+#define US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xaae0
+#define US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define US_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS 0xab00
+#define US_CPU_RX_PICO_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_CPU_RX_PICO_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xab40
+#define US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xab60
+#define US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define US_ROUTER_INGRESS_QUEUE_ADDRESS 0xab80
+#define US_ROUTER_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_ROUTER_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_ROUTER_INGRESS_QUEUE_SIZE     64
+#define RDD_US_ROUTER_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_CPU_TX_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xabc0
+#define US_CPU_TX_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_CPU_TX_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS 0xabe0
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_BYTE_SIZE 0x0018
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_SIZE     3
+#define US_ONE_BUFFER_ADDRESS 0xabf8
+#define US_ONE_BUFFER_BYTE_SIZE 0x0008
+#define US_ONE_BUFFER_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_TX_FAST_QUEUE_ADDRESS 0xac00
+#define US_CPU_TX_FAST_QUEUE_BYTE_SIZE 0x0080
+#define US_CPU_TX_FAST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_TX_FAST_QUEUE_SIZE     16
+#define RDD_US_CPU_TX_FAST_QUEUE_LOG2_SIZE     4
+#define US_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS 0xac80
+#define US_CPU_RX_FAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_CPU_RX_FAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_DHD_TX_POST_HEADER_SCRATCH_ADDRESS 0xacc0
+#define US_DHD_TX_POST_HEADER_SCRATCH_BYTE_SIZE 0x0020
+#define US_DHD_TX_POST_HEADER_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS 0xace0
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_BYTE_SIZE 0x0018
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE     3
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_SIZE     2
+#define US_NULL_BUFFER_ADDRESS 0xacf8
+#define US_NULL_BUFFER_BYTE_SIZE 0x0008
+#define US_NULL_BUFFER_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_TX_PICO_QUEUE_ADDRESS 0xad00
+#define US_CPU_TX_PICO_QUEUE_BYTE_SIZE 0x0080
+#define US_CPU_TX_PICO_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_TX_PICO_QUEUE_SIZE     16
+#define RDD_US_CPU_TX_PICO_QUEUE_LOG2_SIZE     4
+#define US_DEBUG_BUFFER_ADDRESS 0xad80
+#define US_DEBUG_BUFFER_BYTE_SIZE 0x0080
+#define US_DEBUG_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_DEBUG_BUFFER_SIZE     32
+#define RDD_US_DEBUG_BUFFER_LOG2_SIZE     5
+#define US_FW_MAC_ADDRS_ADDRESS 0xae00
+#define US_FW_MAC_ADDRS_BYTE_SIZE 0x0080
+#define US_FW_MAC_ADDRS_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_FW_MAC_ADDRS_SIZE     16
+#define RDD_US_FW_MAC_ADDRS_LOG2_SIZE     4
+#define US_DHD_TX_POST_INGRESS_QUEUE_ADDRESS 0xae80
+#define US_DHD_TX_POST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_DHD_TX_POST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_ADDRESS 0xaec0
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_BYTE_SIZE 0x0060
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE     48
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_LOG2_SIZE     6
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS 0xaf20
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define US_CPU_PARAMETERS_BLOCK_ADDRESS 0xaf60
+#define US_CPU_PARAMETERS_BLOCK_BYTE_SIZE 0x0014
+#define US_CPU_PARAMETERS_BLOCK_LOG2_BYTE_SIZE 0x0005
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xaf74
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define US_FAST_MALLOC_RESULT_TABLE_ADDRESS 0xaf78
+#define US_FAST_MALLOC_RESULT_TABLE_BYTE_SIZE 0x0008
+#define US_FAST_MALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_FAST_MALLOC_RESULT_TABLE_SIZE     2
+#define RDD_US_FAST_MALLOC_RESULT_TABLE_LOG2_SIZE     1
+#define US_CSO_CONTEXT_TABLE_ADDRESS 0xaf80
+#define US_CSO_CONTEXT_TABLE_BYTE_SIZE 0x0054
+#define US_CSO_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define US_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xafd4
+#define US_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS 0xafd8
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_BYTE_SIZE 0x0028
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_BYTE_SIZE 0x0006
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE     40
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_SIZE     6
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS 0xb000
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x0030
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RUNNER_FWTRACE_PICOB_PARAM_ADDRESS 0xb030
+#define RUNNER_FWTRACE_PICOB_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_PICOB_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_LOG2_SIZE     1
+#define US_DHD_FLOW_RING_DROP_COUNTER_ADDRESS 0xb040
+#define US_DHD_FLOW_RING_DROP_COUNTER_BYTE_SIZE 0x0014
+#define US_DHD_FLOW_RING_DROP_COUNTER_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_LOG2_SIZE     3
+#define US_BPM_DDR_BUFFERS_BASE_ADDRESS 0xb054
+#define US_BPM_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define US_PICO_MALLOC_RESULT_TABLE_ADDRESS 0xb058
+#define US_PICO_MALLOC_RESULT_TABLE_BYTE_SIZE 0x0008
+#define US_PICO_MALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_PICO_MALLOC_RESULT_TABLE_SIZE     2
+#define RDD_US_PICO_MALLOC_RESULT_TABLE_LOG2_SIZE     1
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb060
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS 0xb070
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_BYTE_SIZE 0x0010
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_SIZE     3
+#define US_SYSTEM_CONFIGURATION_ADDRESS 0xb080
+#define US_SYSTEM_CONFIGURATION_BYTE_SIZE 0x0024
+#define US_SYSTEM_CONFIGURATION_LOG2_BYTE_SIZE 0x0006
+#define US_BPM_DDR_1_BUFFERS_BASE_ADDRESS 0xb0a4
+#define US_BPM_DDR_1_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_1_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS 0xb0a8
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_BYTE_SIZE 0x0008
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_SIZE     3
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS 0xb0b0
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_BYTE_SIZE 0x0010
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb0c0
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_ADDRESS 0xb0d0
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_BYTE_SIZE 0x0020
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_LOG2_SIZE     5
+#define WAN_TX_SCRATCH_ADDRESS 0xb0f0
+#define WAN_TX_SCRATCH_BYTE_SIZE 0x0018
+#define WAN_TX_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define RDD_WAN_TX_SCRATCH_SIZE     24
+#define RDD_WAN_TX_SCRATCH_LOG2_SIZE     5
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_ADDRESS 0xb108
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_BYTE_SIZE 0x0012
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE     3
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_SIZE     2
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2    6
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_SIZE2    3
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xb11a
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_CONNECTION_TABLE_CONFIG_ADDRESS 0xb11c
+#define US_CONNECTION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONNECTION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_ADDRESS 0xb120
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_BYTE_SIZE 0x0009
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE     9
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xb129
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_ADDRESS 0xb12a
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_BYTE_SIZE 0x0002
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_LOG2_BYTE_SIZE 0x0001
+#define US_CONTEXT_TABLE_CONFIG_ADDRESS 0xb12c
+#define US_CONTEXT_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONTEXT_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_ADDRESS 0xb130
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_BYTE_SIZE 0x0010
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_ADDRESS 0xb140
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_ADDRESS 0xb150
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_BYTE_SIZE 0x000e
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE     14
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_LOG2_SIZE     4
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_ADDRESS 0xb15e
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_BYTE_SIZE 0x0002
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_LOG2_BYTE_SIZE 0x0001
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ADDRESS 0xb160
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_BYTE_SIZE 0x0006
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_ADDRESS 0xb166
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DATA_POINTER_DUMMY_TARGET_ADDRESS 0xb168
+#define DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0008
+#define DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0003
+#define RDD_DATA_POINTER_DUMMY_TARGET_SIZE     2
+#define RDD_DATA_POINTER_DUMMY_TARGET_LOG2_SIZE     1
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS 0xb170
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_BYTE_SIZE 0x0004
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_SIZE     2
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_ADDRESS 0xb174
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_BYTE_SIZE 0x0004
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_LOG2_BYTE_SIZE 0x0002
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS 0xb178
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_BYTE_SIZE 0x0004
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_SIZE     2
+#define IH_BUFFER_BBH_POINTER_ADDRESS 0xb17c
+#define IH_BUFFER_BBH_POINTER_BYTE_SIZE 0x0004
+#define IH_BUFFER_BBH_POINTER_LOG2_BYTE_SIZE 0x0002
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS 0xb180
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_BYTE_SIZE 0x0008
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_SIZE     3
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_ADDRESS 0xb188
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xb18c
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS 0xb190
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_BYTE_SIZE 0x0004
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_SIZE     4
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_SIZE     2
+#define US_CPU_TX_DATA_POINTER_DUMMY_TARGET_ADDRESS 0xb194
+#define US_CPU_TX_DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0004
+#define US_CPU_TX_DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0002
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb198
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb19a
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS 0xb19c
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_BYTE_SIZE 0x0002
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_ANY_SRC_PORT_FLOW_COUNTER_ADDRESS 0xb19e
+#define US_ANY_SRC_PORT_FLOW_COUNTER_BYTE_SIZE 0x0002
+#define US_ANY_SRC_PORT_FLOW_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_ADDRESS 0xb1a0
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_BYTE_SIZE 0x0004
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_ADDRESS 0xb1a4
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_BYTE_SIZE 0x0002
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_LOG2_BYTE_SIZE 0x0001
+#define US_MEMLIB_SEMAPHORE_ADDRESS 0xb1a6
+#define US_MEMLIB_SEMAPHORE_BYTE_SIZE 0x0002
+#define US_MEMLIB_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_ADDRESS 0xb1a8
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_RUNNER_CONGESTION_STATE_ADDRESS 0xb1aa
+#define US_RUNNER_CONGESTION_STATE_BYTE_SIZE 0x0002
+#define US_RUNNER_CONGESTION_STATE_LOG2_BYTE_SIZE 0x0001
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb1ac
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_ADDRESS 0xb1ae
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_BYTE_SIZE 0x0002
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_ADDRESS 0xb1b0
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_BYTE_SIZE 0x0002
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_ADDRESS 0xb1b2
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_BYTE_SIZE 0x0002
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_FC_GLOBAL_CFG_ADDRESS 0xb1b4
+#define US_FC_GLOBAL_CFG_BYTE_SIZE 0x0001
+#define US_FC_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0001
+#define ETHWAN2_SWITCH_PORT_ADDRESS 0xb1b5
+#define ETHWAN2_SWITCH_PORT_BYTE_SIZE 0x0001
+#define ETHWAN2_SWITCH_PORT_LOG2_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_ADDRESS 0xb1b6
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_ADDRESS 0xb1b7
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_PACKET_BUFFER_SIZE_ASR_8_ADDRESS 0xb1b8
+#define US_PACKET_BUFFER_SIZE_ASR_8_BYTE_SIZE 0x0001
+#define US_PACKET_BUFFER_SIZE_ASR_8_LOG2_BYTE_SIZE 0x0001
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb1b9
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb1ba
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_ADDRESS 0xb1bb
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_BYTE_SIZE 0x0001
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DSL_BUFFER_ALIGNMENT_ADDRESS 0xb1bc
+#define DSL_BUFFER_ALIGNMENT_BYTE_SIZE 0x0001
+#define DSL_BUFFER_ALIGNMENT_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS 0xb1bd
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_ADDRESS 0xb1be
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_LOG2_BYTE_SIZE 0x0001
+#define US_IH_CONGESTION_THRESHOLD_ADDRESS 0xb1bf
+#define US_IH_CONGESTION_THRESHOLD_BYTE_SIZE 0x0001
+#define US_IH_CONGESTION_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define US_FAST_MALLOC_RESULT_MUTEX_ADDRESS 0xb1c0
+#define US_FAST_MALLOC_RESULT_MUTEX_BYTE_SIZE 0x0001
+#define US_FAST_MALLOC_RESULT_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_MALLOC_RESULT_MUTEX_ADDRESS 0xb1c1
+#define US_PICO_MALLOC_RESULT_MUTEX_BYTE_SIZE 0x0001
+#define US_PICO_MALLOC_RESULT_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DHD_RX_FPM_ALLOC_RESULT_MUTEX_ADDRESS 0xb1c2
+#define DHD_RX_FPM_ALLOC_RESULT_MUTEX_BYTE_SIZE 0x0001
+#define DHD_RX_FPM_ALLOC_RESULT_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define US_RX_SBPM_TO_FPM_COPY_SEMAPHORE_ADDRESS 0xb1c3
+#define US_RX_SBPM_TO_FPM_COPY_SEMAPHORE_BYTE_SIZE 0x0001
+#define US_RX_SBPM_TO_FPM_COPY_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define US_FW_MAC_ADDRS_COUNT_ADDRESS 0xb1c4
+#define US_FW_MAC_ADDRS_COUNT_BYTE_SIZE 0x0001
+#define US_FW_MAC_ADDRS_COUNT_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_DMA_SYNCHRONIZATION_ADDRESS 0xb1c5
+#define US_DHD_DMA_SYNCHRONIZATION_BYTE_SIZE 0x0001
+#define US_DHD_DMA_SYNCHRONIZATION_LOG2_BYTE_SIZE 0x0001
+#define US_RUNNER_FLOW_IH_RESPONSE_ADDRESS 0xb6f0
+#define US_RUNNER_FLOW_IH_RESPONSE_BYTE_SIZE 0x0008
+#define US_RUNNER_FLOW_IH_RESPONSE_LOG2_BYTE_SIZE 0x0003
+#define ETH2_RX_DESCRIPTORS_ADDRESS 0xba00
+#define ETH2_RX_DESCRIPTORS_BYTE_SIZE 0x0100
+#define ETH2_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH2_RX_DESCRIPTORS_SIZE     32
+#define RDD_ETH2_RX_DESCRIPTORS_LOG2_SIZE     5
+#define ETH1_RX_DESCRIPTORS_ADDRESS 0xbc00
+#define ETH1_RX_DESCRIPTORS_BYTE_SIZE 0x0100
+#define ETH1_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH1_RX_DESCRIPTORS_SIZE     32
+#define RDD_ETH1_RX_DESCRIPTORS_LOG2_SIZE     5
+#define ETH0_RX_DESCRIPTORS_ADDRESS 0xbe00
+#define ETH0_RX_DESCRIPTORS_BYTE_SIZE 0x0100
+#define ETH0_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH0_RX_DESCRIPTORS_SIZE     32
+#define RDD_ETH0_RX_DESCRIPTORS_LOG2_SIZE     5
+#define BBH_TX_WAN_CHANNEL_INDEX_ADDRESS 0xbfe8
+#define BBH_TX_WAN_CHANNEL_INDEX_BYTE_SIZE 0x0004
+#define BBH_TX_WAN_CHANNEL_INDEX_LOG2_BYTE_SIZE 0x0002
+/* COMMON_A */
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_ADDRESS 0x0000
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_BYTE_SIZE 0x1000
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_LOG2_BYTE_SIZE 0x000c
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE     256
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_LOG2_SIZE     8
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS 0x1000
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define CPU_RX_RUNNER_A_SCRATCHPAD_ADDRESS 0x1800
+#define CPU_RX_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define CPU_RX_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_ADDRESS 0x2000
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_BYTE_SIZE 0x0800
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE     8
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_LOG2_SIZE     3
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS 0x2800
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define RUNNER_FWTRACE_MAINA_BASE_ADDRESS 0x3000
+#define RUNNER_FWTRACE_MAINA_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_MAINA_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_LOG2_SIZE     7
+#define RUNNER_FWTRACE_PICOA_BASE_ADDRESS 0x3400
+#define RUNNER_FWTRACE_PICOA_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_PICOA_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_LOG2_SIZE     7
+#define WLAN_MCAST_DHD_STATION_TABLE_ADDRESS 0x3800
+#define WLAN_MCAST_DHD_STATION_TABLE_BYTE_SIZE 0x0280
+#define WLAN_MCAST_DHD_STATION_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_LOG2_SIZE     6
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS 0x3a80
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_BYTE_SIZE 0x0080
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE     2
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE     1
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE2    64
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE2    6
+#define MAC_TABLE_CAM_ADDRESS 0x3b00
+#define MAC_TABLE_CAM_BYTE_SIZE 0x0100
+#define MAC_TABLE_CAM_LOG2_BYTE_SIZE 0x0008
+#define RDD_MAC_TABLE_CAM_SIZE     32
+#define RDD_MAC_TABLE_CAM_LOG2_SIZE     5
+#define MAC_TABLE_ADDRESS 0x3c00
+#define MAC_TABLE_BYTE_SIZE 0x0200
+#define MAC_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAC_TABLE_SIZE     64
+#define RDD_MAC_TABLE_LOG2_SIZE     6
+#define ETHWAN2_RX_INGRESS_QUEUE_ADDRESS 0x3e00
+#define ETHWAN2_RX_INGRESS_QUEUE_BYTE_SIZE 0x0100
+#define ETHWAN2_RX_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE     32
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_LOG2_SIZE     5
+#define TRACE_C_TABLE_ADDRESS 0x3f00
+#define TRACE_C_TABLE_BYTE_SIZE 0x0020
+#define TRACE_C_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_TRACE_C_TABLE_SIZE     4
+#define RDD_TRACE_C_TABLE_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_ADDRESS 0x3f20
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_LOG2_SIZE     1
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_ADDRESS 0x3f30
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_ADDRESS 0x3f34
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_LOG2_BYTE_SIZE 0x0002
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_ADDRESS 0x3f38
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_BYTE_SIZE 0x0008
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_LOG2_BYTE_SIZE 0x0003
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE     2
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_LOG2_SIZE     1
+#define BPM_REPLY_RUNNER_A_ADDRESS 0x3f40
+#define BPM_REPLY_RUNNER_A_BYTE_SIZE 0x0030
+#define BPM_REPLY_RUNNER_A_LOG2_BYTE_SIZE 0x0006
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_ADDRESS 0x3f70
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_BYTE_SIZE 0x0010
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define MAC_CONTEXT_TABLE_ADDRESS 0x3f80
+#define MAC_CONTEXT_TABLE_BYTE_SIZE 0x0080
+#define MAC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_MAC_CONTEXT_TABLE_SIZE     64
+#define RDD_MAC_CONTEXT_TABLE_LOG2_SIZE     6
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS 0x4000
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_BYTE_SIZE 0x0600
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_LOG2_BYTE_SIZE 0x000b
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE     32
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS 0x4600
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_BYTE_SIZE 0x0200
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_SIZE     8
+#define WLAN_MCAST_FWD_TABLE_ADDRESS 0x4800
+#define WLAN_MCAST_FWD_TABLE_BYTE_SIZE 0x0200
+#define WLAN_MCAST_FWD_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_FWD_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_FWD_TABLE_LOG2_SIZE     6
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_ADDRESS 0x4a00
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_BYTE_SIZE 0x0200
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_LOG2_SIZE     5
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_ADDRESS 0x4c00
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_BYTE_SIZE 0x0180
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE     48
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_LOG2_SIZE     6
+#define CPU_TX_POST_REQUEST_QUEUE_ADDRESS 0x4d80
+#define CPU_TX_POST_REQUEST_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_POST_REQUEST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE     8
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_LOG2_SIZE     3
+#define WLAN_MCAST_SSID_STATS_TABLE_ADDRESS 0x4e00
+#define WLAN_MCAST_SSID_STATS_TABLE_BYTE_SIZE 0x0180
+#define WLAN_MCAST_SSID_STATS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE     48
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_LOG2_SIZE     6
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_ADDRESS 0x4f80
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_BYTE_SIZE 0x0060
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE     3
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_LOG2_SIZE     2
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS 0x4fe0
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_BYTE_SIZE 0x0020
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_SIZE     4
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS 0x5000
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_SIZE     7
+#define PM_COUNTERS_ADDRESS 0x5800
+#define PM_COUNTERS_BYTE_SIZE 0x1840
+#define PM_COUNTERS_LOG2_BYTE_SIZE 0x000d
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_ADDRESS 0x7040
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_BYTE_SIZE 0x0080
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_LOG2_BYTE_SIZE 0x0007
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE     128
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_LOG2_SIZE     7
+#define INTERRUPT_COALESCING_CONFIG_TABLE_ADDRESS 0x70c0
+#define INTERRUPT_COALESCING_CONFIG_TABLE_BYTE_SIZE 0x0040
+#define INTERRUPT_COALESCING_CONFIG_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE     16
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_LOG2_SIZE     4
+#define DS_CPU_TX_SCRATCHPAD_ADDRESS 0x7100
+#define DS_CPU_TX_SCRATCHPAD_BYTE_SIZE 0x0100
+#define DS_CPU_TX_SCRATCHPAD_LOG2_BYTE_SIZE 0x0008
+#define DS_CONNECTION_BUFFER_TABLE_ADDRESS 0x7200
+#define DS_CONNECTION_BUFFER_TABLE_BYTE_SIZE 0x0140
+#define DS_CONNECTION_BUFFER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_DS_CONNECTION_BUFFER_TABLE_LOG2_SIZE     3
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2    4
+#define RDD_DS_CONNECTION_BUFFER_TABLE_LOG2_SIZE2    2
+#define MAC_CONTEXT_TABLE_CAM_ADDRESS 0x7340
+#define MAC_CONTEXT_TABLE_CAM_BYTE_SIZE 0x0040
+#define MAC_CONTEXT_TABLE_CAM_LOG2_BYTE_SIZE 0x0006
+#define RDD_MAC_CONTEXT_TABLE_CAM_SIZE     32
+#define RDD_MAC_CONTEXT_TABLE_CAM_LOG2_SIZE     5
+#define DHD_DOORBELL_WRITE_VALUES_ADDRESS 0x7380
+#define DHD_DOORBELL_WRITE_VALUES_BYTE_SIZE 0x0040
+#define DHD_DOORBELL_WRITE_VALUES_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_DOORBELL_WRITE_VALUES_SIZE     16
+#define RDD_DHD_DOORBELL_WRITE_VALUES_LOG2_SIZE     4
+#define DS_DHD_BACKUP_INDEX_CACHE_ADDRESS 0x73c0
+#define DS_DHD_BACKUP_INDEX_CACHE_BYTE_SIZE 0x0040
+#define DS_DHD_BACKUP_INDEX_CACHE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE     32
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_LOG2_SIZE     5
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS 0x7400
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_BYTE_SIZE 0x0100
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_LOG2_SIZE     4
+#define RING_DESCRIPTORS_TABLE_ADDRESS 0x7500
+#define RING_DESCRIPTORS_TABLE_BYTE_SIZE 0x0100
+#define RING_DESCRIPTORS_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_RING_DESCRIPTORS_TABLE_SIZE     16
+#define RDD_RING_DESCRIPTORS_TABLE_LOG2_SIZE     4
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_ADDRESS 0x7600
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_BYTE_SIZE 0x0100
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_LOG2_SIZE     5
+#define MAC_EXTENSION_TABLE_ADDRESS 0x7700
+#define MAC_EXTENSION_TABLE_BYTE_SIZE 0x0040
+#define MAC_EXTENSION_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_MAC_EXTENSION_TABLE_SIZE     64
+#define RDD_MAC_EXTENSION_TABLE_LOG2_SIZE     6
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_ADDRESS 0x7740
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_BYTE_SIZE 0x0020
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE     16
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_LOG2_SIZE     4
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_ADDRESS 0x7760
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0014
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_ADDRESS 0x7774
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_ADDRESS 0x7778
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_BYTE_SIZE 0x0008
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_LOG2_BYTE_SIZE 0x0003
+#define SERVICE_QUEUES_CFG_ADDRESS 0x7780
+#define SERVICE_QUEUES_CFG_BYTE_SIZE 0x0014
+#define SERVICE_QUEUES_CFG_LOG2_BYTE_SIZE 0x0005
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_ADDRESS 0x7794
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_BYTE_SIZE 0x0004
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_LOG2_BYTE_SIZE 0x0002
+#define MAC_EXTENSION_TABLE_CAM_ADDRESS 0x7798
+#define MAC_EXTENSION_TABLE_CAM_BYTE_SIZE 0x0020
+#define MAC_EXTENSION_TABLE_CAM_LOG2_BYTE_SIZE 0x0005
+#define RDD_MAC_EXTENSION_TABLE_CAM_SIZE     32
+#define RDD_MAC_EXTENSION_TABLE_CAM_LOG2_SIZE     5
+#define DS_CAM_DHD_DMA_SCRATCH_ADDRESS 0x77b8
+#define DS_CAM_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_CAM_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_ENQ_DHD_DMA_SCRATCH_ADDRESS 0x77bc
+#define DS_ENQ_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_ENQ_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define PM_COUNTERS_BUFFER_ADDRESS 0x77c0
+#define PM_COUNTERS_BUFFER_BYTE_SIZE 0x0020
+#define PM_COUNTERS_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define TX_CPL_DHD_DMA_SCRATCH_ADDRESS 0x77e0
+#define TX_CPL_DHD_DMA_SCRATCH_BYTE_SIZE 0x000c
+#define TX_CPL_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE     3
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_LOG2_SIZE     2
+#define DS_R2D_DHD_DMA_SCRATCH_ADDRESS 0x77ec
+#define DS_R2D_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_R2D_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DHD_TX_POST_BUFFERS_THRESHOLD_ADDRESS 0x77f0
+#define DHD_TX_POST_BUFFERS_THRESHOLD_BYTE_SIZE 0x000c
+#define DHD_TX_POST_BUFFERS_THRESHOLD_LOG2_BYTE_SIZE 0x0004
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_SIZE     6
+#define RDD_DHD_TX_POST_BUFFERS_THRESHOLD_LOG2_SIZE     3
+#define DS_CPU_DHD_DMA_SCRATCH_ADDRESS 0x77fc
+#define DS_CPU_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_CPU_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS 0x7800
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_BYTE_SIZE 0x0004
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_SIZE     4
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_SIZE     2
+#define TIMER_7_TIMER_PERIOD_ADDRESS 0x7804
+#define TIMER_7_TIMER_PERIOD_BYTE_SIZE 0x0002
+#define TIMER_7_TIMER_PERIOD_LOG2_BYTE_SIZE 0x0001
+#define INTERRUPT_COALESCING_TIMER_PERIOD_ADDRESS 0x7806
+#define INTERRUPT_COALESCING_TIMER_PERIOD_BYTE_SIZE 0x0002
+#define INTERRUPT_COALESCING_TIMER_PERIOD_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_POST_BUFFERS_IN_USE_COUNTER_ADDRESS 0x7808
+#define DHD_TX_POST_BUFFERS_IN_USE_COUNTER_BYTE_SIZE 0x0004
+#define DHD_TX_POST_BUFFERS_IN_USE_COUNTER_LOG2_BYTE_SIZE 0x0002
+#define RDD_DHD_TX_POST_BUFFERS_IN_USE_COUNTER_SIZE     2
+#define RDD_DHD_TX_POST_BUFFERS_IN_USE_COUNTER_LOG2_SIZE     1
+#define INTERRUPT_COALESCING_TIMER_ARMED_ADDRESS 0x780c
+#define INTERRUPT_COALESCING_TIMER_ARMED_BYTE_SIZE 0x0002
+#define INTERRUPT_COALESCING_TIMER_ARMED_LOG2_BYTE_SIZE 0x0001
+#define COMMON_A_DUMMY_STORE_ADDRESS 0x780e
+#define COMMON_A_DUMMY_STORE_BYTE_SIZE 0x0001
+#define COMMON_A_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define FC_SERVICE_QUEUE_MODE_ADDRESS 0x780f
+#define FC_SERVICE_QUEUE_MODE_BYTE_SIZE 0x0001
+#define FC_SERVICE_QUEUE_MODE_LOG2_BYTE_SIZE 0x0001
+#define MAIN_A_DEBUG_TRACE_ADDRESS 0x7a00
+#define MAIN_A_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define MAIN_A_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAIN_A_DEBUG_TRACE_SIZE     512
+#define RDD_MAIN_A_DEBUG_TRACE_LOG2_SIZE     9
+#define PICO_A_DEBUG_TRACE_ADDRESS 0x7c00
+#define PICO_A_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define PICO_A_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_PICO_A_DEBUG_TRACE_SIZE     512
+#define RDD_PICO_A_DEBUG_TRACE_LOG2_SIZE     9
+/* COMMON_B */
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS 0x8000
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_SIZE     7
+#define CPU_RX_RUNNER_B_SCRATCHPAD_ADDRESS 0x8800
+#define CPU_RX_RUNNER_B_SCRATCHPAD_BYTE_SIZE 0x0800
+#define CPU_RX_RUNNER_B_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE     8
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS 0x9000
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_BYTE_SIZE 0x0200
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_SIZE     8
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0x9200
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0100
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0008
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     32
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS 0x9300
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_BYTE_SIZE 0x0100
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_SIZE     5
+#define WAN_TX_SERVICE_QUEUES_TABLE_ADDRESS 0x9400
+#define WAN_TX_SERVICE_QUEUES_TABLE_BYTE_SIZE 0x0800
+#define WAN_TX_SERVICE_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE     64
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_LOG2_SIZE     6
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS 0x9c00
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_BYTE_SIZE 0x0100
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_SIZE     5
+#define US_CPU_TX_SCRATCHPAD_ADDRESS 0x9d00
+#define US_CPU_TX_SCRATCHPAD_BYTE_SIZE 0x0100
+#define US_CPU_TX_SCRATCHPAD_LOG2_BYTE_SIZE 0x0008
+#define US_CONNECTION_BUFFER_TABLE_ADDRESS 0x9e00
+#define US_CONNECTION_BUFFER_TABLE_BYTE_SIZE 0x0140
+#define US_CONNECTION_BUFFER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_US_CONNECTION_BUFFER_TABLE_LOG2_SIZE     3
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE2    4
+#define RDD_US_CONNECTION_BUFFER_TABLE_LOG2_SIZE2    2
+#define IPV6_HOST_ADDRESS_CRC_TABLE_ADDRESS 0x9f40
+#define IPV6_HOST_ADDRESS_CRC_TABLE_BYTE_SIZE 0x0040
+#define IPV6_HOST_ADDRESS_CRC_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE     16
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_LOG2_SIZE     4
+#define DHD_BACKUP_INFO_CACHE_TABLE_ADDRESS 0x9f80
+#define DHD_BACKUP_INFO_CACHE_TABLE_BYTE_SIZE 0x0080
+#define DHD_BACKUP_INFO_CACHE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE     16
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_LOG2_SIZE     4
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS 0xa000
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_SIZE     8
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS 0xa800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_SIZE     8
+#define WAN_TX_QUEUES_TABLE_ADDRESS 0xb000
+#define WAN_TX_QUEUES_TABLE_BYTE_SIZE 0x1000
+#define WAN_TX_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000c
+#define RDD_WAN_TX_QUEUES_TABLE_SIZE     256
+#define RDD_WAN_TX_QUEUES_TABLE_LOG2_SIZE     8
+#define RUNNER_FWTRACE_MAINB_BASE_ADDRESS 0xc000
+#define RUNNER_FWTRACE_MAINB_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_MAINB_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_LOG2_SIZE     7
+#define WAN_TX_RUNNER_B_SCRATCHPAD_ADDRESS 0xc400
+#define WAN_TX_RUNNER_B_SCRATCHPAD_BYTE_SIZE 0x0100
+#define WAN_TX_RUNNER_B_SCRATCHPAD_LOG2_BYTE_SIZE 0x0008
+#define US_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS 0xc500
+#define US_RING_PACKET_DESCRIPTORS_CACHE_BYTE_SIZE 0x0100
+#define US_RING_PACKET_DESCRIPTORS_CACHE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_LOG2_SIZE     4
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_ADDRESS 0xc600
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_BYTE_SIZE 0x0100
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE     16
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_LOG2_SIZE     4
+#define FC_FLOW_IP_ADDRESSES_TABLE_ADDRESS 0xc700
+#define FC_FLOW_IP_ADDRESSES_TABLE_BYTE_SIZE 0x00c0
+#define FC_FLOW_IP_ADDRESSES_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE     4
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_ADDRESS 0xc7c0
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_LOG2_SIZE     1
+#define BPM_REPLY_RUNNER_B_ADDRESS 0xc7d0
+#define BPM_REPLY_RUNNER_B_BYTE_SIZE 0x0030
+#define BPM_REPLY_RUNNER_B_LOG2_BYTE_SIZE 0x0006
+#define US_RATE_CONTROLLERS_TABLE_ADDRESS 0xc800
+#define US_RATE_CONTROLLERS_TABLE_BYTE_SIZE 0x1800
+#define US_RATE_CONTROLLERS_TABLE_LOG2_BYTE_SIZE 0x000d
+#define RDD_US_RATE_CONTROLLERS_TABLE_SIZE     128
+#define RDD_US_RATE_CONTROLLERS_TABLE_LOG2_SIZE     7
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_ADDRESS 0xe000
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_BYTE_SIZE 0x0800
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE     8
+#define RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_LOG2_SIZE     3
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_ADDRESS 0xe800
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_BYTE_SIZE 0x00c0
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE     3
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_LOG2_SIZE     2
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_ADDRESS 0xe8c0
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_BYTE_SIZE 0x0040
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0006
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS 0xe900
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_BYTE_SIZE 0x0050
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_BYTE_SIZE 0x0007
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     40
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_SIZE     6
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_ADDRESS 0xe950
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_BYTE_SIZE 0x0010
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_LOG2_BYTE_SIZE 0x0004
+#define IPV4_HOST_ADDRESS_TABLE_ADDRESS 0xe960
+#define IPV4_HOST_ADDRESS_TABLE_BYTE_SIZE 0x0020
+#define IPV4_HOST_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPV4_HOST_ADDRESS_TABLE_SIZE     8
+#define RDD_IPV4_HOST_ADDRESS_TABLE_LOG2_SIZE     3
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS 0xe980
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_BYTE_SIZE 0x0050
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_BYTE_SIZE 0x0007
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     40
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_SIZE     6
+#define US_DHD_BACKUP_ENTRY_SCRATCH_ADDRESS 0xe9d0
+#define US_DHD_BACKUP_ENTRY_SCRATCH_BYTE_SIZE 0x0010
+#define US_DHD_BACKUP_ENTRY_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS 0xe9e0
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_BYTE_SIZE 0x0020
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_SIZE     4
+#define MAIN_B_DEBUG_TRACE_ADDRESS 0xea00
+#define MAIN_B_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define MAIN_B_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAIN_B_DEBUG_TRACE_SIZE     512
+#define RDD_MAIN_B_DEBUG_TRACE_LOG2_SIZE     9
+#define PICO_B_DEBUG_TRACE_ADDRESS 0xec00
+#define PICO_B_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define PICO_B_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_PICO_B_DEBUG_TRACE_SIZE     512
+#define RDD_PICO_B_DEBUG_TRACE_LOG2_SIZE     9
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS 0xee00
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_BYTE_SIZE 0x0080
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE     2
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE     1
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE2    64
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE2    6
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_ADDRESS 0xee80
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_BYTE_SIZE 0x0080
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_LOG2_BYTE_SIZE 0x0007
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_ADDRESS 0xef00
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_BYTE_SIZE 0x0080
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_LOG2_BYTE_SIZE 0x0007
+#define LAN0_INGRESS_FIFO_ADDRESS 0xef80
+#define LAN0_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN0_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN5_INGRESS_FIFO_ADDRESS 0xefc0
+#define LAN5_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN5_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define RUNNER_FWTRACE_PICOB_BASE_ADDRESS 0xf000
+#define RUNNER_FWTRACE_PICOB_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_PICOB_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_LOG2_SIZE     7
+#define LAN1_INGRESS_FIFO_ADDRESS 0xf400
+#define LAN1_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN1_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN6_INGRESS_FIFO_ADDRESS 0xf440
+#define LAN6_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN6_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN2_INGRESS_FIFO_ADDRESS 0xf480
+#define LAN2_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN2_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN7_INGRESS_FIFO_ADDRESS 0xf4c0
+#define LAN7_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN7_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN3_INGRESS_FIFO_ADDRESS 0xf500
+#define LAN3_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN3_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define US_DHD_BACKUP_INDEX_CACHE_ADDRESS 0xf540
+#define US_DHD_BACKUP_INDEX_CACHE_BYTE_SIZE 0x0040
+#define US_DHD_BACKUP_INDEX_CACHE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE     32
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_LOG2_SIZE     5
+#define LAN4_INGRESS_FIFO_ADDRESS 0xf580
+#define LAN4_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN4_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define DHD_DOORBELL_COUNTERS_ADDRESS 0xf5c0
+#define DHD_DOORBELL_COUNTERS_BYTE_SIZE 0x0030
+#define DHD_DOORBELL_COUNTERS_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_DOORBELL_COUNTERS_SIZE     48
+#define RDD_DHD_DOORBELL_COUNTERS_LOG2_SIZE     6
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ADDRESS 0xf5f0
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_BYTE_SIZE 0x0010
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_LOG2_BYTE_SIZE 0x0004
+#define WAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0xf600
+#define WAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define WAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_ADDRESS 0xf640
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0014
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define US_CAM_DHD_DMA_SCRATCH_ADDRESS 0xf654
+#define US_CAM_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_CAM_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_DHD_BACKUP_FLUSH_SCRATCH_ADDRESS 0xf658
+#define US_DHD_BACKUP_FLUSH_SCRATCH_BYTE_SIZE 0x0008
+#define US_DHD_BACKUP_FLUSH_SCRATCH_LOG2_BYTE_SIZE 0x0003
+#define US_ENQ_DHD_DMA_SCRATCH_ADDRESS 0xf660
+#define US_ENQ_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_ENQ_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_R2D_DHD_DMA_SCRATCH_ADDRESS 0xf664
+#define US_R2D_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_R2D_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_ADDRESS 0xf668
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_BYTE_SIZE 0x0004
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE     4
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_LOG2_SIZE     2
+#define COMMON_B_DUMMY_STORE_ADDRESS 0xf66c
+#define COMMON_B_DUMMY_STORE_BYTE_SIZE 0x0001
+#define COMMON_B_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_ADDRESS 0xf66d
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_BYTE_SIZE 0x0001
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_LOG2_BYTE_SIZE 0x0001
+/* DDR */
+#define BPM_PACKET_BUFFERS_ADDRESS 0x0000
+#define BPM_PACKET_BUFFERS_BYTE_SIZE 0xf00000
+#define BPM_PACKET_BUFFERS_LOG2_BYTE_SIZE 0x0018
+#define RDD_BPM_PACKET_BUFFERS_SIZE     7680
+#define RDD_BPM_PACKET_BUFFERS_LOG2_SIZE     13
+#define CONTEXT_TABLE_ADDRESS 0x0000
+#define CONTEXT_TABLE_BYTE_SIZE 0x0084
+#define CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0008
+#define NAT_CACHE_TABLE_ADDRESS 0x0000
+#define NAT_CACHE_TABLE_BYTE_SIZE 0x100000
+#define NAT_CACHE_TABLE_LOG2_BYTE_SIZE 0x0014
+#define RDD_NAT_CACHE_TABLE_SIZE     65536
+#define RDD_NAT_CACHE_TABLE_LOG2_SIZE     16
+#define NAT_CACHE_EXTENSION_TABLE_ADDRESS 0x0000
+#define NAT_CACHE_EXTENSION_TABLE_BYTE_SIZE 0x0070
+#define NAT_CACHE_EXTENSION_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_NAT_CACHE_EXTENSION_TABLE_SIZE     7
+#define RDD_NAT_CACHE_EXTENSION_TABLE_LOG2_SIZE     3
+#define NATC_CONTEXT_TABLE_ADDRESS 0x0000
+#define NATC_CONTEXT_TABLE_BYTE_SIZE 0x400000
+#define NATC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0016
+#define RDD_NATC_CONTEXT_TABLE_SIZE     65536
+#define RDD_NATC_CONTEXT_TABLE_LOG2_SIZE     16
+#define CONTEXT_CONTINUATION_TABLE_ADDRESS 0x0000
+#define CONTEXT_CONTINUATION_TABLE_BYTE_SIZE 0x4c0000
+#define CONTEXT_CONTINUATION_TABLE_LOG2_BYTE_SIZE 0x0017
+#define RDD_CONTEXT_CONTINUATION_TABLE_SIZE     65536
+#define RDD_CONTEXT_CONTINUATION_TABLE_LOG2_SIZE     16
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_ADDRESS 0x5d1500
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_BYTE_SIZE 0x00a0
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE     8
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_LOG2_SIZE     3
+#define DHD_RX_POST_DDR_BUFFER_ADDRESS 0x5c1100
+#define DHD_RX_POST_DDR_BUFFER_BYTE_SIZE 0x8000
+#define DHD_RX_POST_DDR_BUFFER_LOG2_BYTE_SIZE 0x000f
+#define RDD_DHD_RX_POST_DDR_BUFFER_SIZE     1024
+#define RDD_DHD_RX_POST_DDR_BUFFER_LOG2_SIZE     10
+#define DHD_RX_COMPLETE_DDR_BUFFER_ADDRESS 0x5c9100
+#define DHD_RX_COMPLETE_DDR_BUFFER_BYTE_SIZE 0x8000
+#define DHD_RX_COMPLETE_DDR_BUFFER_LOG2_BYTE_SIZE 0x000f
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE     1024
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_LOG2_SIZE     10
+#define DHD_TX_POST_DDR_BUFFER_ADDRESS 0x5d15a0
+#define DHD_TX_POST_DDR_BUFFER_BYTE_SIZE 0x1800
+#define DHD_TX_POST_DDR_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE     8
+#define RDD_DHD_TX_POST_DDR_BUFFER_LOG2_SIZE     3
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE2    16
+#define RDD_DHD_TX_POST_DDR_BUFFER_LOG2_SIZE2    4
+#define DHD_TX_COMPLETE_DDR_BUFFER_ADDRESS 0x5d2da0
+#define DHD_TX_COMPLETE_DDR_BUFFER_BYTE_SIZE 0x0100
+#define DHD_TX_COMPLETE_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE     16
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_LOG2_SIZE     4
+#define R2D_WR_ARR_DDR_BUFFER_ADDRESS 0x5d1100
+#define R2D_WR_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define R2D_WR_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_R2D_WR_ARR_DDR_BUFFER_SIZE     128
+#define RDD_R2D_WR_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define D2R_RD_ARR_DDR_BUFFER_ADDRESS 0x5d1200
+#define D2R_RD_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define D2R_RD_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_D2R_RD_ARR_DDR_BUFFER_SIZE     128
+#define RDD_D2R_RD_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define R2D_RD_ARR_DDR_BUFFER_ADDRESS 0x5d1300
+#define R2D_RD_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define R2D_RD_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_R2D_RD_ARR_DDR_BUFFER_SIZE     128
+#define RDD_R2D_RD_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define D2R_WR_ARR_DDR_BUFFER_ADDRESS 0x5d1400
+#define D2R_WR_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define D2R_WR_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_D2R_WR_ARR_DDR_BUFFER_SIZE     128
+#define RDD_D2R_WR_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define DHD_BACKUP_QUEUES_BUFFER_ADDRESS 0x600000
+#define DHD_BACKUP_QUEUES_BUFFER_BYTE_SIZE 0x100000
+#define DHD_BACKUP_QUEUES_BUFFER_LOG2_BYTE_SIZE 0x0014
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE     524288
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_LOG2_SIZE     19
+#define WLAN_MCAST_DHD_LIST_TABLE_ADDRESS 0x5c0000
+#define WLAN_MCAST_DHD_LIST_TABLE_BYTE_SIZE 0x1000
+#define WLAN_MCAST_DHD_LIST_TABLE_LOG2_BYTE_SIZE 0x000c
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_LOG2_SIZE     6
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_ADDRESS 0x5c1000
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_BYTE_SIZE 0x0001
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_LOG2_BYTE_SIZE 0x0001
+/* PSRAM */
+#endif
+#ifdef WL4908_EAP
+/* PRIVATE_A */
+#define INGRESS_HANDLER_BUFFER_ADDRESS 0x0000
+#define INGRESS_HANDLER_BUFFER_BYTE_SIZE 0x2000
+#define INGRESS_HANDLER_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_INGRESS_HANDLER_BUFFER_SIZE     32
+#define RDD_INGRESS_HANDLER_BUFFER_LOG2_SIZE     5
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS 0x2000
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_BYTE_SIZE 0x4000
+#define DS_FREE_PACKET_DESCRIPTORS_POOL_LOG2_BYTE_SIZE 0x000e
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_SIZE     2048
+#define RDD_DS_FREE_PACKET_DESCRIPTORS_POOL_LOG2_SIZE     11
+#define DS_CONNECTION_CONTEXT_BUFFER_ADDRESS 0x6000
+#define DS_CONNECTION_CONTEXT_BUFFER_BYTE_SIZE 0x0400
+#define DS_CONNECTION_CONTEXT_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CONTEXT_BUFFER_LOG2_SIZE     3
+#define DS_GSO_HEADER_BUFFER_ADDRESS 0x6400
+#define DS_GSO_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_GSO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_GSO_PSEUDO_HEADER_BUFFER_ADDRESS 0x6480
+#define DS_GSO_PSEUDO_HEADER_BUFFER_BYTE_SIZE 0x0028
+#define DS_GSO_PSEUDO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x64a8
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0008
+#define DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+#define RDD_DS_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     2
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_ADDRESS 0x64b0
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_BYTE_SIZE 0x0010
+#define DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_SIZE     8
+#define RDD_DS_RATE_SHAPER_BUDGET_ALLOCATOR_TABLE_LOG2_SIZE     3
+#define DS_CPU_REASON_TO_METER_TABLE_ADDRESS 0x64c0
+#define DS_CPU_REASON_TO_METER_TABLE_BYTE_SIZE 0x0040
+#define DS_CPU_REASON_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_SIZE     64
+#define RDD_DS_CPU_REASON_TO_METER_TABLE_LOG2_SIZE     6
+#define DS_GSO_CHUNK_BUFFER_ADDRESS 0x6500
+#define DS_GSO_CHUNK_BUFFER_BYTE_SIZE 0x0080
+#define DS_GSO_CHUNK_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_CPU_RX_METER_TABLE_ADDRESS 0x6580
+#define DS_CPU_RX_METER_TABLE_BYTE_SIZE 0x0080
+#define DS_CPU_RX_METER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_CPU_RX_METER_TABLE_SIZE     16
+#define RDD_DS_CPU_RX_METER_TABLE_LOG2_SIZE     4
+#define DS_POLICER_TABLE_ADDRESS 0x6600
+#define DS_POLICER_TABLE_BYTE_SIZE 0x0100
+#define DS_POLICER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_POLICER_TABLE_SIZE     16
+#define RDD_DS_POLICER_TABLE_LOG2_SIZE     4
+#define IPSEC_DS_BUFFER_POOL_ADDRESS 0x6700
+#define IPSEC_DS_BUFFER_POOL_BYTE_SIZE 0x0160
+#define IPSEC_DS_BUFFER_POOL_LOG2_BYTE_SIZE 0x0009
+#define RDD_IPSEC_DS_BUFFER_POOL_SIZE     2
+#define RDD_IPSEC_DS_BUFFER_POOL_LOG2_SIZE     1
+#define IPSEC_DS_SA_DESC_TABLE_ADDRESS 0x6860
+#define IPSEC_DS_SA_DESC_TABLE_BYTE_SIZE 0x0500
+#define IPSEC_DS_SA_DESC_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_IPSEC_DS_SA_DESC_TABLE_SIZE     16
+#define RDD_IPSEC_DS_SA_DESC_TABLE_LOG2_SIZE     4
+#define IPSEC_US_SA_DESC_TABLE_ADDRESS 0x6d60
+#define IPSEC_US_SA_DESC_TABLE_BYTE_SIZE 0x0500
+#define IPSEC_US_SA_DESC_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_IPSEC_US_SA_DESC_TABLE_SIZE     16
+#define RDD_IPSEC_US_SA_DESC_TABLE_LOG2_SIZE     4
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_ADDRESS 0x7260
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_BYTE_SIZE 0x0300
+#define SERVICE_QUEUES_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_RATE_LIMITER_TABLE_LOG2_SIZE     5
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x7560
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_DS_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define DS_SPDSVC_CONTEXT_TABLE_ADDRESS 0x7580
+#define DS_SPDSVC_CONTEXT_TABLE_BYTE_SIZE 0x0050
+#define DS_SPDSVC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x75d0
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0010
+#define DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+#define RDD_DS_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     3
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS 0x75e0
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_BYTE_SIZE 0x0100
+#define DS_MAIN_PROFILING_BUFFER_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+#define RDD_DS_MAIN_PROFILING_BUFFER_RUNNER_LOG2_SIZE     5
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x76e0
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_DS_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define WLAN_MCAST_CONTROL_TABLE_ADDRESS 0x7700
+#define WLAN_MCAST_CONTROL_TABLE_BYTE_SIZE 0x0094
+#define WLAN_MCAST_CONTROL_TABLE_LOG2_BYTE_SIZE 0x0008
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_ADDRESS 0x7794
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_BYTE_SIZE 0x0004
+#define DS_WAN_UDP_FILTER_CONTROL_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DS_TOTAL_PPS_RATE_LIMITER_ADDRESS 0x7798
+#define DS_TOTAL_PPS_RATE_LIMITER_BYTE_SIZE 0x0008
+#define DS_TOTAL_PPS_RATE_LIMITER_LOG2_BYTE_SIZE 0x0003
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS 0x77a0
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_BYTE_SIZE 0x0020
+#define DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE     1
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+#define RDD_DS_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE2    4
+#define RATE_LIMITER_REMAINDER_TABLE_ADDRESS 0x77c0
+#define RATE_LIMITER_REMAINDER_TABLE_BYTE_SIZE 0x0040
+#define RATE_LIMITER_REMAINDER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_SIZE     32
+#define RDD_RATE_LIMITER_REMAINDER_TABLE_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS 0x7800
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_SIZE     8
+#define FC_MCAST_CONNECTION2_TABLE_ADDRESS 0x8000
+#define FC_MCAST_CONNECTION2_TABLE_BYTE_SIZE 0x0800
+#define FC_MCAST_CONNECTION2_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_FC_MCAST_CONNECTION2_TABLE_SIZE     128
+#define RDD_FC_MCAST_CONNECTION2_TABLE_LOG2_SIZE     7
+#define ETH_TX_QUEUES_POINTERS_TABLE_ADDRESS 0x8800
+#define ETH_TX_QUEUES_POINTERS_TABLE_BYTE_SIZE 0x0120
+#define ETH_TX_QUEUES_POINTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_SIZE     72
+#define RDD_ETH_TX_QUEUES_POINTERS_TABLE_LOG2_SIZE     7
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_ADDRESS 0x8920
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_BYTE_SIZE 0x0020
+#define DS_FC_L2_UCAST_TUPLE_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS 0x8940
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+#define RDD_DS_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define SBPM_REPLY_ADDRESS 0x8980
+#define SBPM_REPLY_BYTE_SIZE 0x0080
+#define SBPM_REPLY_LOG2_BYTE_SIZE 0x0007
+#define DS_WAN_FLOW_TABLE_ADDRESS 0x8a00
+#define DS_WAN_FLOW_TABLE_BYTE_SIZE 0x0200
+#define DS_WAN_FLOW_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_WAN_FLOW_TABLE_SIZE     256
+#define RDD_DS_WAN_FLOW_TABLE_LOG2_SIZE     8
+#define DS_CONNECTION_CONTEXT_REMAINING_BUFFER_ADDRESS 0x8c00
+#define DS_CONNECTION_CONTEXT_REMAINING_BUFFER_BYTE_SIZE 0x0260
+#define DS_CONNECTION_CONTEXT_REMAINING_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CONTEXT_REMAINING_BUFFER_LOG2_SIZE     3
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS 0x8e60
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_BYTE_SIZE 0x0020
+#define DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+#define RDD_DS_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_SIZE     2
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS 0x8e80
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_BYTE_SIZE 0x0080
+#define DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE     1
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+#define RDD_DS_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE2    4
+#define DS_FORWARDING_MATRIX_TABLE_ADDRESS 0x8f00
+#define DS_FORWARDING_MATRIX_TABLE_BYTE_SIZE 0x0090
+#define DS_FORWARDING_MATRIX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_DS_FORWARDING_MATRIX_TABLE_LOG2_SIZE     4
+#define RDD_DS_FORWARDING_MATRIX_TABLE_SIZE2    16
+#define RDD_DS_FORWARDING_MATRIX_TABLE_LOG2_SIZE2    4
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0x8f90
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0010
+#define DS_FC_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0x8fa0
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_DS_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_ADDRESS 0x8fc0
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_BYTE_SIZE 0x0030
+#define DHD_TX_COMPLETE_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_TX_COMPLETE_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINA_PARAM_ADDRESS 0x8ff0
+#define RUNNER_FWTRACE_MAINA_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINA_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINA_PARAM_LOG2_SIZE     1
+#define DS_WAN_UDP_FILTER_TABLE_ADDRESS 0x9000
+#define DS_WAN_UDP_FILTER_TABLE_BYTE_SIZE 0x0200
+#define DS_WAN_UDP_FILTER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_WAN_UDP_FILTER_TABLE_SIZE     32
+#define RDD_DS_WAN_UDP_FILTER_TABLE_LOG2_SIZE     5
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0x9200
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9240
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_DS_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9280
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_DS_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_ADDRESS 0x92c0
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0030
+#define DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_SIZE     3
+#define RDD_DHD_COMPLETE_RING_DESCRIPTOR_BUFFER_LOG2_SIZE     2
+#define RUNNER_FWTRACE_PICOA_PARAM_ADDRESS 0x92f0
+#define RUNNER_FWTRACE_PICOA_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_PICOA_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_PICOA_PARAM_LOG2_SIZE     1
+#define DS_RATE_LIMITER_TABLE_ADDRESS 0x9300
+#define DS_RATE_LIMITER_TABLE_BYTE_SIZE 0x0100
+#define DS_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_RATE_LIMITER_TABLE_SIZE     32
+#define RDD_DS_RATE_LIMITER_TABLE_LOG2_SIZE     5
+#define ETH_TX_QUEUES_TABLE_ADDRESS 0x9400
+#define ETH_TX_QUEUES_TABLE_BYTE_SIZE 0x0480
+#define ETH_TX_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_ETH_TX_QUEUES_TABLE_SIZE     72
+#define RDD_ETH_TX_QUEUES_TABLE_LOG2_SIZE     7
+#define INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS 0x9880
+#define INGRESS_HANDLER_SKB_DATA_POINTER_BYTE_SIZE 0x0080
+#define INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+#define RDD_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_SIZE     5
+#define DS_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x9900
+#define DS_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x9980
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define DS_GRE_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define FC_MCAST_PORT_HEADER_BUFFER_ADDRESS 0x9a00
+#define FC_MCAST_PORT_HEADER_BUFFER_BYTE_SIZE 0x0200
+#define FC_MCAST_PORT_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE     8
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_LOG2_SIZE     3
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_SIZE2    64
+#define RDD_FC_MCAST_PORT_HEADER_BUFFER_LOG2_SIZE2    6
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_ADDRESS 0x9c00
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_BYTE_SIZE 0x0200
+#define DOWNSTREAM_LAN_ENQUEUE_SQ_PD_LOG2_BYTE_SIZE 0x0009
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_SIZE     64
+#define RDD_DOWNSTREAM_LAN_ENQUEUE_SQ_PD_LOG2_SIZE     6
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_ADDRESS 0x9e00
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_BYTE_SIZE 0x0200
+#define DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_SIZE     8
+#define RDD_DS_CONNECTION_CONTEXT_MULTICAST_BUFFER_LOG2_SIZE     3
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_ADDRESS 0xa000
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_BYTE_SIZE 0x0200
+#define CPU_RX_SQ_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_SIZE     64
+#define RDD_CPU_RX_SQ_PD_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_CPU_TX_BBH_DESCRIPTORS_ADDRESS 0xa200
+#define DS_CPU_TX_BBH_DESCRIPTORS_BYTE_SIZE 0x0100
+#define DS_CPU_TX_BBH_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+#define RDD_DS_CPU_TX_BBH_DESCRIPTORS_LOG2_SIZE     5
+#define DS_PROFILING_BUFFER_PICO_RUNNER_ADDRESS 0xa300
+#define DS_PROFILING_BUFFER_PICO_RUNNER_BYTE_SIZE 0x0100
+#define DS_PROFILING_BUFFER_PICO_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define GSO_PICO_QUEUE_ADDRESS 0xa400
+#define GSO_PICO_QUEUE_BYTE_SIZE 0x0200
+#define GSO_PICO_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_GSO_PICO_QUEUE_SIZE     64
+#define RDD_GSO_PICO_QUEUE_LOG2_SIZE     6
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS 0xa600
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x00c0
+#define DS_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_SIZE     4
+#define RDD_DS_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_ADDRESS 0xa6c0
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_BYTE_SIZE 0x0040
+#define DS_CPU_TX_MESSAGE_DATA_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS 0xa700
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_BYTE_SIZE 0x0080
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+#define RDD_DS_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_SIZE     4
+#define ETH_TX_LOCAL_REGISTERS_ADDRESS 0xa780
+#define ETH_TX_LOCAL_REGISTERS_BYTE_SIZE 0x0048
+#define ETH_TX_LOCAL_REGISTERS_LOG2_BYTE_SIZE 0x0007
+#define RDD_ETH_TX_LOCAL_REGISTERS_SIZE     9
+#define RDD_ETH_TX_LOCAL_REGISTERS_LOG2_SIZE     4
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS 0xa7c8
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_BYTE_SIZE 0x0008
+#define DS_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     2
+#define RDD_DS_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_SIZE     1
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS 0xa7d0
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_BYTE_SIZE 0x0010
+#define EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_BYTE_SIZE 0x0004
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     8
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_SIZE     3
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xa7e0
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_DS_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define IPSEC_DS_QUEUE_ADDRESS 0xa800
+#define IPSEC_DS_QUEUE_BYTE_SIZE 0x0200
+#define IPSEC_DS_QUEUE_LOG2_BYTE_SIZE 0x0009
+#define RDD_IPSEC_DS_QUEUE_SIZE     64
+#define RDD_IPSEC_DS_QUEUE_LOG2_SIZE     6
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0xaa00
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     16
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     4
+#define DS_QUEUE_PROFILE_TABLE_ADDRESS 0xaa80
+#define DS_QUEUE_PROFILE_TABLE_BYTE_SIZE 0x0080
+#define DS_QUEUE_PROFILE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_QUEUE_PROFILE_TABLE_SIZE     8
+#define RDD_DS_QUEUE_PROFILE_TABLE_LOG2_SIZE     3
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_ADDRESS 0xab00
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_BYTE_SIZE 0x0080
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_SIZE     16
+#define RDD_DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_LOG2_SIZE     4
+#define DS_SQ_ENQUEUE_QUEUE_ADDRESS 0xab80
+#define DS_SQ_ENQUEUE_QUEUE_BYTE_SIZE 0x0040
+#define DS_SQ_ENQUEUE_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_SQ_ENQUEUE_QUEUE_SIZE     64
+#define RDD_DS_SQ_ENQUEUE_QUEUE_LOG2_SIZE     6
+#define MULTICAST_HEADER_BUFFER_ADDRESS 0xabc0
+#define MULTICAST_HEADER_BUFFER_BYTE_SIZE 0x0040
+#define MULTICAST_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define CPU_TX_FAST_QUEUE_ADDRESS 0xac00
+#define CPU_TX_FAST_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_FAST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_FAST_QUEUE_SIZE     16
+#define RDD_CPU_TX_FAST_QUEUE_LOG2_SIZE     4
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS 0xac80
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_CPU_RX_PICO_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xacc0
+#define DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xace0
+#define DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_DS_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define CPU_TX_PICO_QUEUE_ADDRESS 0xad00
+#define CPU_TX_PICO_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_PICO_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_PICO_QUEUE_SIZE     16
+#define RDD_CPU_TX_PICO_QUEUE_LOG2_SIZE     4
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_ADDRESS 0xad80
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DOWNSTREAM_MULTICAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_SIZE     64
+#define RDD_DOWNSTREAM_MULTICAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xadc0
+#define DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_DS_CPU_TX_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define DS_NULL_BUFFER_ADDRESS 0xade0
+#define DS_NULL_BUFFER_BYTE_SIZE 0x0018
+#define DS_NULL_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_NULL_BUFFER_SIZE     3
+#define RDD_DS_NULL_BUFFER_LOG2_SIZE     2
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS 0xadf8
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_BYTE_SIZE 0x0008
+#define DS_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0003
+#define CPU_RX_PD_INGRESS_QUEUE_ADDRESS 0xae00
+#define CPU_RX_PD_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define CPU_RX_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_SIZE     16
+#define RDD_CPU_RX_PD_INGRESS_QUEUE_LOG2_SIZE     4
+#define DS_ROUTER_INGRESS_QUEUE_ADDRESS 0xae80
+#define DS_ROUTER_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_ROUTER_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_ROUTER_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_ROUTER_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS 0xaec0
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define DS_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+#define RDD_DS_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_ADDRESS 0xaf00
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_BYTE_SIZE 0x0080
+#define CPU_RX_FAST_PD_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_SIZE     16
+#define RDD_CPU_RX_FAST_PD_INGRESS_QUEUE_LOG2_SIZE     4
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS 0xaf80
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_CPU_RX_FAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define DHD_COMPLETE_RING_BUFFER_ADDRESS 0xafc0
+#define DHD_COMPLETE_RING_BUFFER_BYTE_SIZE 0x0018
+#define DHD_COMPLETE_RING_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DHD_COMPLETE_RING_BUFFER_SIZE     3
+#define RDD_DHD_COMPLETE_RING_BUFFER_LOG2_SIZE     2
+#define DS_FAST_MALLOC_RESULT_TABLE_ADDRESS 0xafd8
+#define DS_FAST_MALLOC_RESULT_TABLE_BYTE_SIZE 0x0008
+#define DS_FAST_MALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_FAST_MALLOC_RESULT_TABLE_SIZE     2
+#define RDD_DS_FAST_MALLOC_RESULT_TABLE_LOG2_SIZE     1
+#define DS_CPU_PARAMETERS_BLOCK_ADDRESS 0xafe0
+#define DS_CPU_PARAMETERS_BLOCK_BYTE_SIZE 0x0014
+#define DS_CPU_PARAMETERS_BLOCK_LOG2_BYTE_SIZE 0x0005
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_ADDRESS 0xaff4
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_EXTRA_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_PICO_MALLOC_RESULT_TABLE_ADDRESS 0xaff8
+#define DS_PICO_MALLOC_RESULT_TABLE_BYTE_SIZE 0x0008
+#define DS_PICO_MALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_PICO_MALLOC_RESULT_TABLE_SIZE     2
+#define RDD_DS_PICO_MALLOC_RESULT_TABLE_LOG2_SIZE     1
+#define DS_DHD_TX_POST_HEADER_SCRATCH_ADDRESS 0xb000
+#define DS_DHD_TX_POST_HEADER_SCRATCH_BYTE_SIZE 0x0080
+#define DS_DHD_TX_POST_HEADER_SCRATCH_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_SIZE     4
+#define RDD_DS_DHD_TX_POST_HEADER_SCRATCH_LOG2_SIZE     2
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS 0xb080
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_BYTE_SIZE 0x00a0
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_LOG2_BYTE_SIZE 0x0008
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_SIZE     5
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_LOG2_SIZE     3
+#define DS_DEBUG_BUFFER_ADDRESS 0xb120
+#define DS_DEBUG_BUFFER_BYTE_SIZE 0x0080
+#define DS_DEBUG_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_DEBUG_BUFFER_SIZE     32
+#define RDD_DS_DEBUG_BUFFER_LOG2_SIZE     5
+#define FC_MCAST_CONNECTION_TABLE_PLUS_ADDRESS 0xb1a0
+#define FC_MCAST_CONNECTION_TABLE_PLUS_BYTE_SIZE 0x0014
+#define FC_MCAST_CONNECTION_TABLE_PLUS_LOG2_BYTE_SIZE 0x0005
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xb1b4
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS 0xb1b8
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_BYTE_SIZE 0x0008
+#define DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+#define RDD_DS_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_SIZE     3
+#define DS_DATA_POINTER_DUMMY_TARGET_ADDRESS 0xb1c0
+#define DS_DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0014
+#define DS_DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_SIZE     5
+#define RDD_DS_DATA_POINTER_DUMMY_TARGET_LOG2_SIZE     3
+#define DS_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xb1d4
+#define DS_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_ADDRESS 0xb1d8
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_BYTE_SIZE 0x0006
+#define WLAN_MCAST_SSID_STATS_STATE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xb1de
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define DS_MAIN_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define SERVICE_QUEUES_WLAN_SCRATCH_ADDRESS 0xb1e0
+#define SERVICE_QUEUES_WLAN_SCRATCH_BYTE_SIZE 0x0014
+#define SERVICE_QUEUES_WLAN_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define DS_BPM_DDR_BUFFERS_BASE_ADDRESS 0xb1f4
+#define DS_BPM_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_BPM_DDR_1_BUFFERS_BASE_ADDRESS 0xb1f8
+#define DS_BPM_DDR_1_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define DS_BPM_DDR_1_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define DS_CONNECTION_TABLE_CONFIG_ADDRESS 0xb1fc
+#define DS_CONNECTION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONNECTION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define DS_GSO_CONTEXT_TABLE_ADDRESS 0xb200
+#define DS_GSO_CONTEXT_TABLE_BYTE_SIZE 0x0084
+#define DS_GSO_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0008
+#define DS_CONTEXT_TABLE_CONFIG_ADDRESS 0xb284
+#define DS_CONTEXT_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONTEXT_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS 0xb288
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_BYTE_SIZE 0x0004
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+#define RDD_DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_SIZE     2
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_ADDRESS 0xb28c
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_BYTE_SIZE 0x0004
+#define DS_DEBUG_PERIPHERALS_STATUS_REGISTER_LOG2_BYTE_SIZE 0x0002
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS 0xb290
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_BYTE_SIZE 0x0010
+#define EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_BYTE_SIZE 0x0004
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     8
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_SIZE     3
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb2a0
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define HASH_BUFFER_ADDRESS 0xb2b0
+#define HASH_BUFFER_BYTE_SIZE 0x0010
+#define HASH_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xb2c0
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0050
+#define EMAC_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_SIZE     10
+#define RDD_EMAC_ABSOLUTE_TX_BBH_COUNTER_LOG2_SIZE     4
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ADDRESS 0xb310
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_BYTE_SIZE 0x000a
+#define FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0004
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xb31a
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define DS_PICO_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_ADDRESS 0xb31c
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define DS_CONTEXT_CONTINUATION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define DS_FW_MAC_ADDRS_ADDRESS 0xb320
+#define DS_FW_MAC_ADDRS_BYTE_SIZE 0x0080
+#define DS_FW_MAC_ADDRS_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_FW_MAC_ADDRS_SIZE     16
+#define RDD_DS_FW_MAC_ADDRS_LOG2_SIZE     4
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb3a0
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS 0xb3b0
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_BYTE_SIZE 0x0010
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_SIZE     3
+#define DS_DHD_FLOW_RING_DROP_COUNTER_ADDRESS 0xb3c0
+#define DS_DHD_FLOW_RING_DROP_COUNTER_BYTE_SIZE 0x0014
+#define DS_DHD_FLOW_RING_DROP_COUNTER_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+#define RDD_DS_DHD_FLOW_RING_DROP_COUNTER_LOG2_SIZE     3
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xb3d4
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define DS_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS 0xb3d8
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_BYTE_SIZE 0x0004
+#define DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+#define RDD_DS_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_SIZE     2
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xb3dc
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define TIMER_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS 0xb3e0
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_BYTE_SIZE 0x0010
+#define DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+#define RDD_DS_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define ETH_TX_SCRATCH_ADDRESS 0xb3f0
+#define ETH_TX_SCRATCH_BYTE_SIZE 0x0010
+#define ETH_TX_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define RDD_ETH_TX_SCRATCH_SIZE     16
+#define RDD_ETH_TX_SCRATCH_LOG2_SIZE     4
+#define GPON_RX_DIRECT_DESCRIPTORS_ADDRESS 0xb400
+#define GPON_RX_DIRECT_DESCRIPTORS_BYTE_SIZE 0x0100
+#define GPON_RX_DIRECT_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_SIZE     32
+#define RDD_GPON_RX_DIRECT_DESCRIPTORS_LOG2_SIZE     5
+#define DS_GSO_DESC_TABLE_ADDRESS 0xb500
+#define DS_GSO_DESC_TABLE_BYTE_SIZE 0x0080
+#define DS_GSO_DESC_TABLE_LOG2_BYTE_SIZE 0x0007
+#define DS_DHD_TX_POST_INGRESS_QUEUE_ADDRESS 0xb580
+#define DS_DHD_TX_POST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define DS_DHD_TX_POST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+#define RDD_DS_DHD_TX_POST_INGRESS_QUEUE_LOG2_SIZE     6
+#define DS_SYSTEM_CONFIGURATION_ADDRESS 0xb5c0
+#define DS_SYSTEM_CONFIGURATION_BYTE_SIZE 0x0024
+#define DS_SYSTEM_CONFIGURATION_LOG2_BYTE_SIZE 0x0006
+#define SPDSVC_HOST_BUF_PTR_ADDRESS 0xb5e4
+#define SPDSVC_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define SPDSVC_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define GSO_TX_DHD_L2_BUFFER_ADDRESS 0xb5e8
+#define GSO_TX_DHD_L2_BUFFER_BYTE_SIZE 0x0016
+#define GSO_TX_DHD_L2_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_GSO_TX_DHD_L2_BUFFER_SIZE     22
+#define RDD_GSO_TX_DHD_L2_BUFFER_LOG2_SIZE     5
+#define IPTV_COUNTERS_BUFFER_ADDRESS 0xb5fe
+#define IPTV_COUNTERS_BUFFER_BYTE_SIZE 0x0002
+#define IPTV_COUNTERS_BUFFER_LOG2_BYTE_SIZE 0x0001
+#define WLAN_MCAST_INGRESS_QUEUE_ADDRESS 0xb600
+#define WLAN_MCAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define WLAN_MCAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_SIZE     64
+#define RDD_WLAN_MCAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define IPSEC_DS_SA_DESC_CAM_TABLE_ADDRESS 0xb640
+#define IPSEC_DS_SA_DESC_CAM_TABLE_BYTE_SIZE 0x0020
+#define IPSEC_DS_SA_DESC_CAM_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_SIZE     16
+#define RDD_IPSEC_DS_SA_DESC_CAM_TABLE_LOG2_SIZE     4
+#define IPSEC_US_SA_DESC_CAM_TABLE_ADDRESS 0xb660
+#define IPSEC_US_SA_DESC_CAM_TABLE_BYTE_SIZE 0x0020
+#define IPSEC_US_SA_DESC_CAM_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_SIZE     16
+#define RDD_IPSEC_US_SA_DESC_CAM_TABLE_LOG2_SIZE     4
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_ADDRESS 0xb680
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_BYTE_SIZE 0x0018
+#define SERVICE_QUEUES_OVERALL_RATE_LIMITER_LOG2_BYTE_SIZE 0x0005
+#define CPU_TX_DHD_L2_BUFFER_ADDRESS 0xb698
+#define CPU_TX_DHD_L2_BUFFER_BYTE_SIZE 0x0016
+#define CPU_TX_DHD_L2_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define RDD_CPU_TX_DHD_L2_BUFFER_SIZE     22
+#define RDD_CPU_TX_DHD_L2_BUFFER_LOG2_SIZE     5
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xb6ae
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define CPU_TX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_ADDRESS 0xb6b0
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_BYTE_SIZE 0x0010
+#define DS_INGRESS_CLASSIFICATION_KEY_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_ADDRESS 0xb6c0
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define CPU_TX_DS_PICO_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_ADDRESS 0xb6d0
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define WLAN_MCAST_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_ADDRESS 0xb6e0
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define GSO_TX_DS_PICO_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define RUNNER_FLOW_IH_RESPONSE_ADDRESS 0xb6f0
+#define RUNNER_FLOW_IH_RESPONSE_BYTE_SIZE 0x0008
+#define RUNNER_FLOW_IH_RESPONSE_LOG2_BYTE_SIZE 0x0003
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS 0xb6f8
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_BYTE_SIZE 0x0008
+#define DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+#define RDD_DS_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_SIZE     3
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_ADDRESS 0xb700
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_BYTE_SIZE 0x0008
+#define GSO_TX_ENQUEUE_PCI_PACKET_CONTEXT_LOG2_BYTE_SIZE 0x0003
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_ADDRESS 0xb708
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_BYTE_SIZE 0x0008
+#define CPU_TX_ENQUEUE_PCI_PACKET_CONTEXT_LOG2_BYTE_SIZE 0x0003
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_ADDRESS 0xb710
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_BYTE_SIZE 0x0005
+#define EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_LOG2_BYTE_SIZE 0x0003
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_SIZE     5
+#define RDD_EMAC_SKB_ENQUEUED_INDEXES_FIFO_COUNTERS_LOG2_SIZE     3
+#define ETH_TX_EMACS_STATUS_ADDRESS 0xb715
+#define ETH_TX_EMACS_STATUS_BYTE_SIZE 0x0001
+#define ETH_TX_EMACS_STATUS_LOG2_BYTE_SIZE 0x0001
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_ADDRESS 0xb716
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_BYTE_SIZE 0x0002
+#define FREE_PACKET_DESCRIPTORS_POOL_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define HASH_BASED_FORWARDING_PORT_TABLE_ADDRESS 0xb718
+#define HASH_BASED_FORWARDING_PORT_TABLE_BYTE_SIZE 0x0004
+#define HASH_BASED_FORWARDING_PORT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_SIZE     4
+#define RDD_HASH_BASED_FORWARDING_PORT_TABLE_LOG2_SIZE     2
+#define DS_CPU_TX_DATA_POINTER_DUMMY_TARGET_ADDRESS 0xb71c
+#define DS_CPU_TX_DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0004
+#define DS_CPU_TX_DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0002
+#define FIREWALL_IPV6_R16_BUFFER_ADDRESS 0xb720
+#define FIREWALL_IPV6_R16_BUFFER_BYTE_SIZE 0x0004
+#define FIREWALL_IPV6_R16_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb724
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_ADDRESS 0xb726
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define CPU_RX_PD_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xb728
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DS_CPU_RX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_ADDRESS 0xb72a
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_BYTE_SIZE 0x0002
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_LOG2_BYTE_SIZE 0x0001
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_ADDRESS 0xb72c
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_BYTE_SIZE 0x0002
+#define DS_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_LOG2_BYTE_SIZE 0x0001
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_ADDRESS 0xb72e
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DS_CPU_RX_FAST_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS 0xb730
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_BYTE_SIZE 0x0002
+#define DS_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_ADDRESS 0xb732
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_BYTE_SIZE 0x0002
+#define DS_ANY_SRC_PORT_FLOW_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define GSO_DESC_PTR_ADDRESS 0xb734
+#define GSO_DESC_PTR_BYTE_SIZE 0x0004
+#define GSO_DESC_PTR_LOG2_BYTE_SIZE 0x0002
+#define GSO_TX_DHD_HOST_BUF_PTR_ADDRESS 0xb738
+#define GSO_TX_DHD_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define GSO_TX_DHD_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_SIZE     4
+#define RDD_GSO_TX_DHD_HOST_BUF_PTR_LOG2_SIZE     2
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_ADDRESS 0xb73c
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_BYTE_SIZE 0x0004
+#define DS_DHD_TX_POST_HOST_DATA_PTR_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define CPU_TX_DHD_HOST_BUF_PTR_ADDRESS 0xb740
+#define CPU_TX_DHD_HOST_BUF_PTR_BYTE_SIZE 0x0004
+#define CPU_TX_DHD_HOST_BUF_PTR_LOG2_BYTE_SIZE 0x0002
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_SIZE     4
+#define RDD_CPU_TX_DHD_HOST_BUF_PTR_LOG2_SIZE     2
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_ADDRESS 0xb744
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_BYTE_SIZE 0x0004
+#define IPSEC_DS_DDR_SA_DESC_TABLE_PTR_LOG2_BYTE_SIZE 0x0002
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_ADDRESS 0xb748
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_BYTE_SIZE 0x0002
+#define DS_TIMER_7_SCHEDULER_NEXT_ENTRY_LOG2_BYTE_SIZE 0x0001
+#define DS_MEMLIB_SEMAPHORE_ADDRESS 0xb74a
+#define DS_MEMLIB_SEMAPHORE_BYTE_SIZE 0x0002
+#define DS_MEMLIB_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define WAN_PHYSICAL_PORT_ADDRESS 0xb74c
+#define WAN_PHYSICAL_PORT_BYTE_SIZE 0x0002
+#define WAN_PHYSICAL_PORT_LOG2_BYTE_SIZE 0x0001
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb74e
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define DOWNSTREAM_MULTICAST_LAN_ENQUEUE_SERVICE_QUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_RUNNER_CONGESTION_STATE_ADDRESS 0xb750
+#define DS_RUNNER_CONGESTION_STATE_BYTE_SIZE 0x0002
+#define DS_RUNNER_CONGESTION_STATE_LOG2_BYTE_SIZE 0x0001
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_ADDRESS 0xb752
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_BYTE_SIZE 0x0002
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_LOG2_BYTE_SIZE 0x0001
+#define GSO_PICO_QUEUE_PTR_ADDRESS 0xb754
+#define GSO_PICO_QUEUE_PTR_BYTE_SIZE 0x0002
+#define GSO_PICO_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_ADDRESS 0xb756
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_BYTE_SIZE 0x0002
+#define DHD_TX_COMPLETE_BPM_REF_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_ADDRESS 0xb758
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_BYTE_SIZE 0x0002
+#define DHD_TX_POST_CPU_BPM_REF_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_ADDRESS 0xb75a
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_BYTE_SIZE 0x0002
+#define DS_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_ADDRESS 0xb75c
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_BYTE_SIZE 0x0002
+#define DS_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_DDR_SA_DESC_SIZE_ADDRESS 0xb75e
+#define IPSEC_DS_DDR_SA_DESC_SIZE_BYTE_SIZE 0x0002
+#define IPSEC_DS_DDR_SA_DESC_SIZE_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_QUEUE_PTR_ADDRESS 0xb760
+#define IPSEC_DS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define IPSEC_DS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_IP_LENGTH_ADDRESS 0xb762
+#define IPSEC_DS_IP_LENGTH_BYTE_SIZE 0x0002
+#define IPSEC_DS_IP_LENGTH_LOG2_BYTE_SIZE 0x0001
+#define PRIVATE_A_DUMMY_STORE_ADDRESS 0xb764
+#define PRIVATE_A_DUMMY_STORE_BYTE_SIZE 0x0001
+#define PRIVATE_A_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_ADDRESS 0xb765
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_BYTE_SIZE 0x0001
+#define ETH_TX_INTER_LAN_SCHEDULING_OFFSET_LOG2_BYTE_SIZE 0x0001
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xb766
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define DS_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xb767
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define DS_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define CPU_TX_DS_PICO_SEMAPHORE_ADDRESS 0xb768
+#define CPU_TX_DS_PICO_SEMAPHORE_BYTE_SIZE 0x0001
+#define CPU_TX_DS_PICO_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define DS_FC_GLOBAL_CFG_ADDRESS 0xb769
+#define DS_FC_GLOBAL_CFG_BYTE_SIZE 0x0001
+#define DS_FC_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_ADDRESS 0xb76a
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_ADDRESS 0xb76b
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define DS_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_PACKET_BUFFER_SIZE_ASR_8_ADDRESS 0xb76c
+#define DS_PACKET_BUFFER_SIZE_ASR_8_BYTE_SIZE 0x0001
+#define DS_PACKET_BUFFER_SIZE_ASR_8_LOG2_BYTE_SIZE 0x0001
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb76d
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define DS_MAIN_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb76e
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define DS_PICO_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_ADDRESS 0xb76f
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_BYTE_SIZE 0x0001
+#define DS_RUNNER_FLOW_IH_RESPONSE_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS 0xb770
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_SLAVE_VECTOR_LOG2_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_ADDRESS 0xb771
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_BYTE_SIZE 0x0001
+#define DS_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_LOG2_BYTE_SIZE 0x0001
+#define DS_IH_CONGESTION_THRESHOLD_ADDRESS 0xb772
+#define DS_IH_CONGESTION_THRESHOLD_BYTE_SIZE 0x0001
+#define DS_IH_CONGESTION_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define DS_FAST_MALLOC_RESULT_MUTEX_ADDRESS 0xb773
+#define DS_FAST_MALLOC_RESULT_MUTEX_BYTE_SIZE 0x0001
+#define DS_FAST_MALLOC_RESULT_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DS_PICO_MALLOC_RESULT_MUTEX_ADDRESS 0xb774
+#define DS_PICO_MALLOC_RESULT_MUTEX_BYTE_SIZE 0x0001
+#define DS_PICO_MALLOC_RESULT_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DS_RX_SBPM_TO_FPM_COPY_SEMAPHORE_ADDRESS 0xb775
+#define DS_RX_SBPM_TO_FPM_COPY_SEMAPHORE_BYTE_SIZE 0x0001
+#define DS_RX_SBPM_TO_FPM_COPY_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define DS_FW_MAC_ADDRS_COUNT_ADDRESS 0xb776
+#define DS_FW_MAC_ADDRS_COUNT_BYTE_SIZE 0x0001
+#define DS_FW_MAC_ADDRS_COUNT_LOG2_BYTE_SIZE 0x0001
+#define DS_DHD_DMA_SYNCHRONIZATION_ADDRESS 0xb777
+#define DS_DHD_DMA_SYNCHRONIZATION_BYTE_SIZE 0x0001
+#define DS_DHD_DMA_SYNCHRONIZATION_LOG2_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_SEMAPHORE_ADDRESS 0xb778
+#define DHD_TX_POST_CPU_SEMAPHORE_BYTE_SIZE 0x0001
+#define DHD_TX_POST_CPU_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define RING_CACHE_DHD_TXPOST_MUTEX_ADDRESS 0xb779
+#define RING_CACHE_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define RING_CACHE_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define COMMON_DHD_TXPOST_MUTEX_ADDRESS 0xb77a
+#define COMMON_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define COMMON_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define TXCPL_INT_DHD_TXPOST_MUTEX_ADDRESS 0xb77b
+#define TXCPL_INT_DHD_TXPOST_MUTEX_BYTE_SIZE 0x0001
+#define TXCPL_INT_DHD_TXPOST_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_ADDRESS 0xb77c
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_BYTE_SIZE 0x0001
+#define IPSEC_DS_SA_DESC_NEXT_REPLACE_LOG2_BYTE_SIZE 0x0001
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_ADDRESS 0xb77d
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_BYTE_SIZE 0x0001
+#define IPSEC_US_SA_DESC_NEXT_REPLACE_LOG2_BYTE_SIZE 0x0001
+#define ETH_TX_MAC_TABLE_ADDRESS 0xbb00
+#define ETH_TX_MAC_TABLE_BYTE_SIZE 0x0100
+#define ETH_TX_MAC_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH_TX_MAC_TABLE_SIZE     8
+#define RDD_ETH_TX_MAC_TABLE_LOG2_SIZE     3
+#define GPON_RX_NORMAL_DESCRIPTORS_ADDRESS 0xbe00
+#define GPON_RX_NORMAL_DESCRIPTORS_BYTE_SIZE 0x0100
+#define GPON_RX_NORMAL_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_SIZE     32
+#define RDD_GPON_RX_NORMAL_DESCRIPTORS_LOG2_SIZE     5
+/* PRIVATE_B */
+#define US_INGRESS_HANDLER_BUFFER_ADDRESS 0x0000
+#define US_INGRESS_HANDLER_BUFFER_BYTE_SIZE 0x2000
+#define US_INGRESS_HANDLER_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_US_INGRESS_HANDLER_BUFFER_SIZE     32
+#define RDD_US_INGRESS_HANDLER_BUFFER_LOG2_SIZE     5
+#define US_CSO_CHUNK_BUFFER_ADDRESS 0x2000
+#define US_CSO_CHUNK_BUFFER_BYTE_SIZE 0x0080
+#define US_CSO_CHUNK_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define US_CSO_PSEUDO_HEADER_BUFFER_ADDRESS 0x2080
+#define US_CSO_PSEUDO_HEADER_BUFFER_BYTE_SIZE 0x0028
+#define US_CSO_PSEUDO_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x20a8
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0008
+#define US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_SIZE     4
+#define RDD_US_TIMER_7_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     2
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_ADDRESS 0x20b0
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_BYTE_SIZE 0x0010
+#define US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_SIZE     8
+#define RDD_US_RATE_CONTROL_BUDGET_ALLOCATOR_TABLE_LOG2_SIZE     3
+#define US_CPU_REASON_TO_METER_TABLE_ADDRESS 0x20c0
+#define US_CPU_REASON_TO_METER_TABLE_BYTE_SIZE 0x0040
+#define US_CPU_REASON_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_REASON_TO_METER_TABLE_SIZE     64
+#define RDD_US_CPU_REASON_TO_METER_TABLE_LOG2_SIZE     6
+#define US_MAIN_PROFILING_BUFFER_RUNNER_ADDRESS 0x2100
+#define US_MAIN_PROFILING_BUFFER_RUNNER_BYTE_SIZE 0x0100
+#define US_MAIN_PROFILING_BUFFER_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_SIZE     32
+#define RDD_US_MAIN_PROFILING_BUFFER_RUNNER_LOG2_SIZE     5
+#define US_FREE_PACKET_DESCRIPTORS_POOL_ADDRESS 0x2200
+#define US_FREE_PACKET_DESCRIPTORS_POOL_BYTE_SIZE 0x6000
+#define US_FREE_PACKET_DESCRIPTORS_POOL_LOG2_BYTE_SIZE 0x000f
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_SIZE     3072
+#define RDD_US_FREE_PACKET_DESCRIPTORS_POOL_LOG2_SIZE     12
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_ADDRESS 0x8200
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_BYTE_SIZE 0x0180
+#define US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE     3
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_SIZE2    16
+#define RDD_US_INGRESS_FILTERS_LOOKUP_TABLE_LOG2_SIZE2    4
+#define US_QUEUE_PROFILE_TABLE_ADDRESS 0x8380
+#define US_QUEUE_PROFILE_TABLE_BYTE_SIZE 0x0080
+#define US_QUEUE_PROFILE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_QUEUE_PROFILE_TABLE_SIZE     8
+#define RDD_US_QUEUE_PROFILE_TABLE_LOG2_SIZE     3
+#define WAN_CHANNELS_8_39_TABLE_ADDRESS 0x8400
+#define WAN_CHANNELS_8_39_TABLE_BYTE_SIZE 0x0400
+#define WAN_CHANNELS_8_39_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WAN_CHANNELS_8_39_TABLE_SIZE     32
+#define RDD_WAN_CHANNELS_8_39_TABLE_LOG2_SIZE     5
+#define US_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0x8800
+#define US_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0180
+#define US_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_SIZE     3
+#define RDD_US_RUNNER_FLOW_HEADER_BUFFER_LOG2_SIZE     2
+#define US_SBPM_REPLY_ADDRESS 0x8980
+#define US_SBPM_REPLY_BYTE_SIZE 0x0080
+#define US_SBPM_REPLY_LOG2_BYTE_SIZE 0x0007
+#define US_POLICER_TABLE_ADDRESS 0x8a00
+#define US_POLICER_TABLE_BYTE_SIZE 0x0100
+#define US_POLICER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_POLICER_TABLE_SIZE     16
+#define RDD_US_POLICER_TABLE_LOG2_SIZE     4
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_ADDRESS 0x8b00
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_BYTE_SIZE 0x0100
+#define WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_SIZE     2
+#define RDD_WAN_TX_SERVICE_QUEUE_SCHEDULER_TABLE_LOG2_SIZE     1
+#define US_WAN_FLOW_TABLE_ADDRESS 0x8c00
+#define US_WAN_FLOW_TABLE_BYTE_SIZE 0x0400
+#define US_WAN_FLOW_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_US_WAN_FLOW_TABLE_SIZE     256
+#define RDD_US_WAN_FLOW_TABLE_LOG2_SIZE     8
+#define US_CPU_TX_BBH_DESCRIPTORS_ADDRESS 0x9000
+#define US_CPU_TX_BBH_DESCRIPTORS_BYTE_SIZE 0x0100
+#define US_CPU_TX_BBH_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_SIZE     32
+#define RDD_US_CPU_TX_BBH_DESCRIPTORS_LOG2_SIZE     5
+#define US_FORWARDING_MATRIX_TABLE_ADDRESS 0x9100
+#define US_FORWARDING_MATRIX_TABLE_BYTE_SIZE 0x0090
+#define US_FORWARDING_MATRIX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE     9
+#define RDD_US_FORWARDING_MATRIX_TABLE_LOG2_SIZE     4
+#define RDD_US_FORWARDING_MATRIX_TABLE_SIZE2    16
+#define RDD_US_FORWARDING_MATRIX_TABLE_LOG2_SIZE2    4
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_ADDRESS 0x9190
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_BYTE_SIZE 0x0010
+#define US_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_SIZE     8
+#define RDD_US_TIMER_SCHEDULER_PRIMITIVE_TABLE_LOG2_SIZE     3
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x91a0
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_US_MAIN_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_ADDRESS 0x91c0
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_BYTE_SIZE 0x0040
+#define US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE     8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_SIZE     3
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_SIZE2    8
+#define RDD_US_TRAFFIC_CLASS_TO_QUEUE_TABLE_LOG2_SIZE2    3
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_ADDRESS 0x9200
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_KEY_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9240
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_US_FAST_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_ADDRESS 0x9280
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_BYTE_SIZE 0x0040
+#define US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_SIZE     16
+#define RDD_US_PICO_CPU_TX_DESCRIPTOR_ABS_DATA_PTR_QUEUE_LOG2_SIZE     4
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_ADDRESS 0x92c0
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_BYTE_SIZE 0x0020
+#define US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_SIZE     4
+#define RDD_US_PICO_TIMER_TASK_DESCRIPTOR_TABLE_LOG2_SIZE     2
+#define US_FC_L2_UCAST_TUPLE_BUFFER_ADDRESS 0x92e0
+#define US_FC_L2_UCAST_TUPLE_BUFFER_BYTE_SIZE 0x0020
+#define US_FC_L2_UCAST_TUPLE_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define US_RATE_LIMITER_TABLE_ADDRESS 0x9300
+#define US_RATE_LIMITER_TABLE_BYTE_SIZE 0x0080
+#define US_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_RATE_LIMITER_TABLE_SIZE     16
+#define RDD_US_RATE_LIMITER_TABLE_LOG2_SIZE     4
+#define US_CPU_RX_METER_TABLE_ADDRESS 0x9380
+#define US_CPU_RX_METER_TABLE_BYTE_SIZE 0x0080
+#define US_CPU_RX_METER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_RX_METER_TABLE_SIZE     16
+#define RDD_US_CPU_RX_METER_TABLE_LOG2_SIZE     4
+#define US_CONNECTION_CONTEXT_BUFFER_ADDRESS 0x9400
+#define US_CONNECTION_CONTEXT_BUFFER_BYTE_SIZE 0x0400
+#define US_CONNECTION_CONTEXT_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_SIZE     8
+#define RDD_US_CONNECTION_CONTEXT_BUFFER_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_ADDRESS 0x9800
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_CONTEXT_TABLE_LOG2_SIZE     8
+#define WAN_CHANNELS_0_7_TABLE_ADDRESS 0xa000
+#define WAN_CHANNELS_0_7_TABLE_BYTE_SIZE 0x02c0
+#define WAN_CHANNELS_0_7_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WAN_CHANNELS_0_7_TABLE_SIZE     8
+#define RDD_WAN_CHANNELS_0_7_TABLE_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_ADDRESS 0xa2c0
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_BYTE_SIZE 0x0020
+#define US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_SIZE     4
+#define RDD_US_INGRESS_CLASSIFICATION_GENERIC_RULE_CFG_TABLE_LOG2_SIZE     2
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xa2e0
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_US_FAST_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_ADDRESS 0xa300
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_BYTE_SIZE 0x0080
+#define US_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_SIZE     32
+#define RDD_US_INGRESS_HANDLER_SKB_DATA_POINTER_LOG2_SIZE     5
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_ADDRESS 0xa380
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_BYTE_SIZE 0x0080
+#define US_GRE_RUNNER_FLOW_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define US_CONNECTION_CONTEXT_REMAINING_BUFFER_ADDRESS 0xa400
+#define US_CONNECTION_CONTEXT_REMAINING_BUFFER_BYTE_SIZE 0x0260
+#define US_CONNECTION_CONTEXT_REMAINING_BUFFER_LOG2_BYTE_SIZE 0x000a
+#define RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_SIZE     8
+#define RDD_US_CONNECTION_CONTEXT_REMAINING_BUFFER_LOG2_SIZE     3
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0xa660
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020
+#define US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_SIZE     8
+#define RDD_US_PICO_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_ADDRESS 0xa680
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_BYTE_SIZE 0x0080
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_SIZE     16
+#define RDD_US_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_LOG2_SIZE     4
+#define US_PROFILING_BUFFER_PICO_RUNNER_ADDRESS 0xa700
+#define US_PROFILING_BUFFER_PICO_RUNNER_BYTE_SIZE 0x0100
+#define US_PROFILING_BUFFER_PICO_RUNNER_LOG2_BYTE_SIZE 0x0008
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_ADDRESS 0xa800
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_BYTE_SIZE 0x0060
+#define US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE     3
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_SIZE2    16
+#define RDD_US_INGRESS_FILTERS_PARAMETER_TABLE_LOG2_SIZE2    4
+#define DHD_RX_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xa860
+#define DHD_RX_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define DHD_RX_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_DHD_RX_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_ADDRESS 0xa880
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_BYTE_SIZE 0x0060
+#define DHD_RX_COMPLETE_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_RX_COMPLETE_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xa8e0
+#define US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_0_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define DHD_RX_POST_FLOW_RING_BUFFER_ADDRESS 0xa900
+#define DHD_RX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x0060
+#define DHD_RX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_SIZE     3
+#define RDD_DHD_RX_POST_FLOW_RING_BUFFER_LOG2_SIZE     2
+#define US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xa960
+#define US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_0_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xa980
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0001
+#define ETHWAN_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define PRIVATE_B_DUMMY_STORE_ADDRESS 0xa981
+#define PRIVATE_B_DUMMY_STORE_BYTE_SIZE 0x0001
+#define PRIVATE_B_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xa982
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define US_MAIN_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_ADDRESS 0xa984
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_BYTE_SIZE 0x0004
+#define US_ETH0_EEE_MODE_CONFIG_MESSAGE_LOG2_BYTE_SIZE 0x0002
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS 0xa988
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_BYTE_SIZE 0x0001
+#define ETHWAN_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xa989
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_ADDRESS 0xa98a
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_BYTE_SIZE 0x0002
+#define US_PICO_TIMER_CONTROL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_ADDRESS 0xa98c
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_EXTRA_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_ADDRESS 0xa990
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_BYTE_SIZE 0x0028
+#define GPON_ABSOLUTE_TX_BBH_COUNTER_LOG2_BYTE_SIZE 0x0006
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_SIZE     40
+#define RDD_GPON_ABSOLUTE_TX_BBH_COUNTER_LOG2_SIZE     6
+#define US_TOTAL_PPS_RATE_LIMITER_ADDRESS 0xa9b8
+#define US_TOTAL_PPS_RATE_LIMITER_BYTE_SIZE 0x0008
+#define US_TOTAL_PPS_RATE_LIMITER_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_ADDRESS 0xa9c0
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_BYTE_SIZE 0x0040
+#define US_CPU_TX_MESSAGE_DATA_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define US_INGRESS_RATE_LIMITER_TABLE_ADDRESS 0xaa00
+#define US_INGRESS_RATE_LIMITER_TABLE_BYTE_SIZE 0x0050
+#define US_INGRESS_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_SIZE     5
+#define RDD_US_INGRESS_RATE_LIMITER_TABLE_LOG2_SIZE     3
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_ADDRESS 0xaa50
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_BYTE_SIZE 0x0010
+#define US_FC_L2_UCAST_CONNECTION_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xaa60
+#define US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_1_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define US_SPDSVC_CONTEXT_TABLE_ADDRESS 0xaa80
+#define US_SPDSVC_CONTEXT_TABLE_BYTE_SIZE 0x0050
+#define US_SPDSVC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RUNNER_FWTRACE_MAINB_PARAM_ADDRESS 0xaad0
+#define RUNNER_FWTRACE_MAINB_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINB_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINB_PARAM_LOG2_SIZE     1
+#define US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xaae0
+#define US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_1_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define US_CPU_RX_PICO_INGRESS_QUEUE_ADDRESS 0xab00
+#define US_CPU_RX_PICO_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_CPU_RX_PICO_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_SIZE     64
+#define RDD_US_CPU_RX_PICO_INGRESS_QUEUE_LOG2_SIZE     6
+#define CAPWAPR0_RX_DESCRIPTORS_ADDRESS 0xab40
+#define CAPWAPR0_RX_DESCRIPTORS_BYTE_SIZE 0x0020
+#define CAPWAPR0_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0005
+#define RDD_CAPWAPR0_RX_DESCRIPTORS_SIZE     4
+#define RDD_CAPWAPR0_RX_DESCRIPTORS_LOG2_SIZE     2
+#define US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xab60
+#define US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_2_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define US_ROUTER_INGRESS_QUEUE_ADDRESS 0xab80
+#define US_ROUTER_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_ROUTER_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_ROUTER_INGRESS_QUEUE_SIZE     64
+#define RDD_US_ROUTER_INGRESS_QUEUE_LOG2_SIZE     6
+#define CAPWAPR1_RX_DESCRIPTORS_ADDRESS 0xabc0
+#define CAPWAPR1_RX_DESCRIPTORS_BYTE_SIZE 0x0020
+#define CAPWAPR1_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0005
+#define RDD_CAPWAPR1_RX_DESCRIPTORS_SIZE     4
+#define RDD_CAPWAPR1_RX_DESCRIPTORS_LOG2_SIZE     2
+#define US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xabe0
+#define US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_2_MCAST_RX_SBPM_TO_FPM_COPY_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define US_CPU_TX_FAST_QUEUE_ADDRESS 0xac00
+#define US_CPU_TX_FAST_QUEUE_BYTE_SIZE 0x0080
+#define US_CPU_TX_FAST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_TX_FAST_QUEUE_SIZE     16
+#define RDD_US_CPU_TX_FAST_QUEUE_LOG2_SIZE     4
+#define US_CPU_RX_FAST_INGRESS_QUEUE_ADDRESS 0xac80
+#define US_CPU_RX_FAST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_CPU_RX_FAST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_SIZE     64
+#define RDD_US_CPU_RX_FAST_INGRESS_QUEUE_LOG2_SIZE     6
+#define CAPWAPR2_RX_DESCRIPTORS_ADDRESS 0xacc0
+#define CAPWAPR2_RX_DESCRIPTORS_BYTE_SIZE 0x0020
+#define CAPWAPR2_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0005
+#define RDD_CAPWAPR2_RX_DESCRIPTORS_SIZE     4
+#define RDD_CAPWAPR2_RX_DESCRIPTORS_LOG2_SIZE     2
+#define US_CPU_TX_FPM_ALLOC_RESULT_TABLE_ADDRESS 0xace0
+#define US_CPU_TX_FPM_ALLOC_RESULT_TABLE_BYTE_SIZE 0x0020
+#define US_CPU_TX_FPM_ALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_SIZE     8
+#define RDD_US_CPU_TX_FPM_ALLOC_RESULT_TABLE_LOG2_SIZE     3
+#define US_CPU_TX_PICO_QUEUE_ADDRESS 0xad00
+#define US_CPU_TX_PICO_QUEUE_BYTE_SIZE 0x0080
+#define US_CPU_TX_PICO_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_TX_PICO_QUEUE_SIZE     16
+#define RDD_US_CPU_TX_PICO_QUEUE_LOG2_SIZE     4
+#define US_DEBUG_BUFFER_ADDRESS 0xad80
+#define US_DEBUG_BUFFER_BYTE_SIZE 0x0080
+#define US_DEBUG_BUFFER_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_DEBUG_BUFFER_SIZE     32
+#define RDD_US_DEBUG_BUFFER_LOG2_SIZE     5
+#define US_FW_MAC_ADDRS_ADDRESS 0xae00
+#define US_FW_MAC_ADDRS_BYTE_SIZE 0x0080
+#define US_FW_MAC_ADDRS_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_FW_MAC_ADDRS_SIZE     16
+#define RDD_US_FW_MAC_ADDRS_LOG2_SIZE     4
+#define US_DHD_TX_POST_INGRESS_QUEUE_ADDRESS 0xae80
+#define US_DHD_TX_POST_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define US_DHD_TX_POST_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_SIZE     64
+#define RDD_US_DHD_TX_POST_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_ADDRESS 0xaec0
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_BYTE_SIZE 0x0060
+#define US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_SIZE     48
+#define RDD_US_OVERALL_RATE_LIMITER_WAN_CHANNEL_PTR_TABLE_LOG2_SIZE     6
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_ADDRESS 0xaf20
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_BYTE_SIZE 0x0018
+#define US_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_SIZE     6
+#define RDD_US_INGRESS_FILTERS_CONFIGURATION_TABLE_LOG2_SIZE     3
+#define US_ONE_BUFFER_ADDRESS 0xaf38
+#define US_ONE_BUFFER_BYTE_SIZE 0x0008
+#define US_ONE_BUFFER_LOG2_BYTE_SIZE 0x0003
+#define US_DHD_TX_POST_HEADER_SCRATCH_ADDRESS 0xaf40
+#define US_DHD_TX_POST_HEADER_SCRATCH_BYTE_SIZE 0x0020
+#define US_DHD_TX_POST_HEADER_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_ADDRESS 0xaf60
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_BYTE_SIZE 0x0018
+#define US_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_SIZE     3
+#define RDD_US_RUNNER_FLOW_HEADER_DESCRIPTOR_LOG2_SIZE     2
+#define US_NULL_BUFFER_ADDRESS 0xaf78
+#define US_NULL_BUFFER_BYTE_SIZE 0x0008
+#define US_NULL_BUFFER_LOG2_BYTE_SIZE 0x0003
+#define US_CSO_CONTEXT_TABLE_ADDRESS 0xaf80
+#define US_CSO_CONTEXT_TABLE_BYTE_SIZE 0x0054
+#define US_CSO_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xafd4
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_ADDRESS 0xafd8
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_BYTE_SIZE 0x0040
+#define US_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_SIZE     32
+#define RDD_US_GPE_COMMAND_PRIMITIVE_TABLE_LOG2_SIZE     5
+#define US_FAST_MALLOC_RESULT_TABLE_ADDRESS 0xb018
+#define US_FAST_MALLOC_RESULT_TABLE_BYTE_SIZE 0x0008
+#define US_FAST_MALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_FAST_MALLOC_RESULT_TABLE_SIZE     2
+#define RDD_US_FAST_MALLOC_RESULT_TABLE_LOG2_SIZE     1
+#define US_CPU_PARAMETERS_BLOCK_ADDRESS 0xb020
+#define US_CPU_PARAMETERS_BLOCK_BYTE_SIZE 0x0014
+#define US_CPU_PARAMETERS_BLOCK_LOG2_BYTE_SIZE 0x0005
+#define US_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_ADDRESS 0xb034
+#define US_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_1_OPTIMIZED_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define US_PICO_MALLOC_RESULT_TABLE_ADDRESS 0xb038
+#define US_PICO_MALLOC_RESULT_TABLE_BYTE_SIZE 0x0008
+#define US_PICO_MALLOC_RESULT_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_PICO_MALLOC_RESULT_TABLE_SIZE     2
+#define RDD_US_PICO_MALLOC_RESULT_TABLE_LOG2_SIZE     1
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS 0xb040
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x0030
+#define US_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0006
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_ADDRESS 0xb070
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_BYTE_SIZE 0x0028
+#define GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_BYTE_SIZE 0x0006
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_SIZE     40
+#define RDD_GPON_ABSOLUTE_TX_FIRMWARE_COUNTER_LOG2_SIZE     6
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_ADDRESS 0xb098
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_BYTE_SIZE 0x0008
+#define US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_SIZE     8
+#define RDD_US_BUF_SIZE_TO_TOKEN_COUNT_LOG2_TABLE_LOG2_SIZE     3
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb0a0
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_US_FAST_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define RUNNER_FWTRACE_PICOB_PARAM_ADDRESS 0xb0b0
+#define RUNNER_FWTRACE_PICOB_PARAM_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_PICOB_PARAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_SIZE     2
+#define RDD_RUNNER_FWTRACE_PICOB_PARAM_LOG2_SIZE     1
+#define US_DHD_FLOW_RING_DROP_COUNTER_ADDRESS 0xb0c0
+#define US_DHD_FLOW_RING_DROP_COUNTER_BYTE_SIZE 0x0014
+#define US_DHD_FLOW_RING_DROP_COUNTER_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_SIZE     5
+#define RDD_US_DHD_FLOW_RING_DROP_COUNTER_LOG2_SIZE     3
+#define US_BPM_DDR_BUFFERS_BASE_ADDRESS 0xb0d4
+#define US_BPM_DDR_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_ADDRESS 0xb0d8
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_BYTE_SIZE 0x0006
+#define US_FREE_PACKET_DESCRIPTORS_POOL_DESCRIPTOR_LOG2_BYTE_SIZE 0x0003
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_ADDRESS 0xb0de
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define US_CPU_RX_PICO_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_ADDRESS 0xb0e0
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_BYTE_SIZE 0x0010
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_SIZE     8
+#define RDD_US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_LOG2_SIZE     3
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_ADDRESS 0xb0f0
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_BYTE_SIZE 0x0010
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_SIZE     8
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_CAM_LOG2_SIZE     3
+#define US_SYSTEM_CONFIGURATION_ADDRESS 0xb100
+#define US_SYSTEM_CONFIGURATION_BYTE_SIZE 0x0024
+#define US_SYSTEM_CONFIGURATION_LOG2_BYTE_SIZE 0x0006
+#define US_BPM_DDR_1_BUFFERS_BASE_ADDRESS 0xb124
+#define US_BPM_DDR_1_BUFFERS_BASE_BYTE_SIZE 0x0004
+#define US_BPM_DDR_1_BUFFERS_BASE_LOG2_BYTE_SIZE 0x0002
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_ADDRESS 0xb128
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_BYTE_SIZE 0x0020
+#define US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_DEFAULT_FLOWS_TABLE_LOG2_SIZE     5
+#define DATA_POINTER_DUMMY_TARGET_ADDRESS 0xb148
+#define DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0008
+#define DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0003
+#define RDD_DATA_POINTER_DUMMY_TARGET_SIZE     2
+#define RDD_DATA_POINTER_DUMMY_TARGET_LOG2_SIZE     1
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_ADDRESS 0xb150
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_BYTE_SIZE 0x0010
+#define US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_SIZE     16
+#define RDD_US_BRIDGE_PORT_TO_LOOKUP_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define WAN_TX_SCRATCH_ADDRESS 0xb160
+#define WAN_TX_SCRATCH_BYTE_SIZE 0x0018
+#define WAN_TX_SCRATCH_LOG2_BYTE_SIZE 0x0005
+#define RDD_WAN_TX_SCRATCH_SIZE     24
+#define RDD_WAN_TX_SCRATCH_LOG2_SIZE     5
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_ADDRESS 0xb178
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_BYTE_SIZE 0x0012
+#define CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE     3
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_SIZE     2
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_SIZE2    6
+#define RDD_CPU_REASON_AND_SRC_BRIDGE_PORT_TO_METER_TABLE_LOG2_SIZE2    3
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_ADDRESS 0xb18a
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_BYTE_SIZE 0x0002
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_LOG2_BYTE_SIZE 0x0001
+#define US_CONNECTION_TABLE_CONFIG_ADDRESS 0xb18c
+#define US_CONNECTION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONNECTION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_ADDRESS 0xb190
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_BYTE_SIZE 0x0009
+#define BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_SIZE     9
+#define RDD_BROADCOM_SWITCH_PORT_TO_BRIDGE_PORT_MAPPING_TABLE_LOG2_SIZE     4
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_ADDRESS 0xb199
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_BYTE_SIZE 0x0001
+#define US_PICO_FREE_SKB_INDEXES_FIFO_LOCAL_TABLE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_ADDRESS 0xb19a
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_BYTE_SIZE 0x0002
+#define US_BPM_DDR_BUFFER_HEADROOM_SIZE_2_BYTE_RESOLUTION_LOG2_BYTE_SIZE 0x0001
+#define US_CONTEXT_TABLE_CONFIG_ADDRESS 0xb19c
+#define US_CONTEXT_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONTEXT_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_ADDRESS 0xb1a0
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_BYTE_SIZE 0x0010
+#define US_INGRESS_CLASSIFICATION_KEY_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_ADDRESS 0xb1b0
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_BYTE_SIZE 0x0010
+#define CPU_TX_DS_EGRESS_DHD_TX_POST_CONTEXT_LOG2_BYTE_SIZE 0x0004
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_ADDRESS 0xb1c0
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_BYTE_SIZE 0x000e
+#define CPU_TX_DHD_LAYER2_HEADER_BUFFER_LOG2_BYTE_SIZE 0x0004
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_SIZE     14
+#define RDD_CPU_TX_DHD_LAYER2_HEADER_BUFFER_LOG2_SIZE     4
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_ADDRESS 0xb1ce
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define US_CPU_RX_FAST_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_ADDRESS 0xb1d0
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_BYTE_SIZE 0x0004
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_SIZE     4
+#define RDD_US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_LOG2_SIZE     2
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_ADDRESS 0xb1d4
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_BYTE_SIZE 0x0004
+#define US_DEBUG_PERIPHERALS_STATUS_REGISTER_LOG2_BYTE_SIZE 0x0002
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_ADDRESS 0xb1d8
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_BYTE_SIZE 0x0004
+#define US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_SIZE     4
+#define RDD_US_PARALLEL_PROCESSING_TASK_REORDER_FIFO_LOG2_SIZE     2
+#define IH_BUFFER_BBH_POINTER_ADDRESS 0xb1dc
+#define IH_BUFFER_BBH_POINTER_BYTE_SIZE 0x0004
+#define IH_BUFFER_BBH_POINTER_LOG2_BYTE_SIZE 0x0002
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_ADDRESS 0xb1e0
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_BYTE_SIZE 0x0008
+#define US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_BYTE_SIZE 0x0003
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_SIZE     8
+#define RDD_US_PARALLEL_PROCESSING_CONTEXT_INDEX_CACHE_TABLE_LOG2_SIZE     3
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_ADDRESS 0xb1e8
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_BYTE_SIZE 0x0004
+#define US_CONTEXT_CONTINUATION_TABLE_CONFIG_LOG2_BYTE_SIZE 0x0002
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_ADDRESS 0xb1ec
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_BYTE_SIZE 0x0004
+#define US_DHD_TX_POST_DOORBELL_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS 0xb1f0
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_BYTE_SIZE 0x0004
+#define US_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_SIZE     4
+#define RDD_US_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_SIZE     2
+#define US_CPU_TX_DATA_POINTER_DUMMY_TARGET_ADDRESS 0xb1f4
+#define US_CPU_TX_DATA_POINTER_DUMMY_TARGET_BYTE_SIZE 0x0004
+#define US_CPU_TX_DATA_POINTER_DUMMY_TARGET_LOG2_BYTE_SIZE 0x0002
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb1f8
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define LOCAL_SWITCHING_MULTICAST_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb1fa
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_ADDRESS 0xb1fc
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_BYTE_SIZE 0x0002
+#define US_PARALLEL_PROCESSING_IH_BUFFER_VECTOR_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_ANY_SRC_PORT_FLOW_COUNTER_ADDRESS 0xb1fe
+#define US_ANY_SRC_PORT_FLOW_COUNTER_BYTE_SIZE 0x0002
+#define US_ANY_SRC_PORT_FLOW_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_ADDRESS 0xb200
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_BYTE_SIZE 0x0004
+#define US_DHD_TX_POST_HOST_DATA_PTR_BUFFER_LOG2_BYTE_SIZE 0x0002
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_ADDRESS 0xb204
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_BYTE_SIZE 0x0002
+#define US_TIMER_7_SCHEDULER_NEXT_ENTRY_LOG2_BYTE_SIZE 0x0001
+#define US_MEMLIB_SEMAPHORE_ADDRESS 0xb206
+#define US_MEMLIB_SEMAPHORE_BYTE_SIZE 0x0002
+#define US_MEMLIB_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_ADDRESS 0xb208
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define ETHWAN2_RX_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_RUNNER_CONGESTION_STATE_ADDRESS 0xb20a
+#define US_RUNNER_CONGESTION_STATE_BYTE_SIZE 0x0002
+#define US_RUNNER_CONGESTION_STATE_LOG2_BYTE_SIZE 0x0001
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_ADDRESS 0xb20c
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_BYTE_SIZE 0x0002
+#define WAN_ENQUEUE_INGRESS_QUEUE_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_ADDRESS 0xb20e
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_BYTE_SIZE 0x0002
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_PTR_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_ADDRESS 0xb210
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_BYTE_SIZE 0x0002
+#define US_DHD_BPM_CONGESTION_UG3_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_ADDRESS 0xb212
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_BYTE_SIZE 0x0002
+#define US_DHD_BPM_CONGESTION_ALLOC_FAIL_DROP_COUNTER_LOG2_BYTE_SIZE 0x0001
+#define US_FC_GLOBAL_CFG_ADDRESS 0xb214
+#define US_FC_GLOBAL_CFG_BYTE_SIZE 0x0001
+#define US_FC_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0001
+#define ETHWAN2_SWITCH_PORT_ADDRESS 0xb215
+#define ETHWAN2_SWITCH_PORT_BYTE_SIZE 0x0001
+#define ETHWAN2_SWITCH_PORT_LOG2_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_ADDRESS 0xb216
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_ADDRESS 0xb217
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_BYTE_SIZE 0x0001
+#define US_INGRESS_CLASSIFICATION_IP_FLOW_RULE_CFG_DESCRIPTOR_LOG2_BYTE_SIZE 0x0001
+#define US_PACKET_BUFFER_SIZE_ASR_8_ADDRESS 0xb218
+#define US_PACKET_BUFFER_SIZE_ASR_8_BYTE_SIZE 0x0001
+#define US_PACKET_BUFFER_SIZE_ASR_8_LOG2_BYTE_SIZE 0x0001
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb219
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define US_MAIN_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_ADDRESS 0xb21a
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_BYTE_SIZE 0x0001
+#define US_PICO_DMA_SYNCRONIZATION_ADDRESS_LOG2_BYTE_SIZE 0x0001
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_ADDRESS 0xb21b
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_BYTE_SIZE 0x0001
+#define US_RUNNER_FLOW_IH_RESPONSE_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DSL_BUFFER_ALIGNMENT_ADDRESS 0xb21c
+#define DSL_BUFFER_ALIGNMENT_BYTE_SIZE 0x0001
+#define DSL_BUFFER_ALIGNMENT_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_ADDRESS 0xb21d
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_SLAVE_VECTOR_LOG2_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_ADDRESS 0xb21e
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_BYTE_SIZE 0x0001
+#define US_PARALLEL_PROCESSING_CONTEXT_CACHE_MODE_LOG2_BYTE_SIZE 0x0001
+#define US_IH_CONGESTION_THRESHOLD_ADDRESS 0xb21f
+#define US_IH_CONGESTION_THRESHOLD_BYTE_SIZE 0x0001
+#define US_IH_CONGESTION_THRESHOLD_LOG2_BYTE_SIZE 0x0001
+#define US_FAST_MALLOC_RESULT_MUTEX_ADDRESS 0xb220
+#define US_FAST_MALLOC_RESULT_MUTEX_BYTE_SIZE 0x0001
+#define US_FAST_MALLOC_RESULT_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define US_PICO_MALLOC_RESULT_MUTEX_ADDRESS 0xb221
+#define US_PICO_MALLOC_RESULT_MUTEX_BYTE_SIZE 0x0001
+#define US_PICO_MALLOC_RESULT_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define DHD_RX_FPM_ALLOC_RESULT_MUTEX_ADDRESS 0xb222
+#define DHD_RX_FPM_ALLOC_RESULT_MUTEX_BYTE_SIZE 0x0001
+#define DHD_RX_FPM_ALLOC_RESULT_MUTEX_LOG2_BYTE_SIZE 0x0001
+#define US_RX_SBPM_TO_FPM_COPY_SEMAPHORE_ADDRESS 0xb223
+#define US_RX_SBPM_TO_FPM_COPY_SEMAPHORE_BYTE_SIZE 0x0001
+#define US_RX_SBPM_TO_FPM_COPY_SEMAPHORE_LOG2_BYTE_SIZE 0x0001
+#define US_FW_MAC_ADDRS_COUNT_ADDRESS 0xb224
+#define US_FW_MAC_ADDRS_COUNT_BYTE_SIZE 0x0001
+#define US_FW_MAC_ADDRS_COUNT_LOG2_BYTE_SIZE 0x0001
+#define US_DHD_DMA_SYNCHRONIZATION_ADDRESS 0xb225
+#define US_DHD_DMA_SYNCHRONIZATION_BYTE_SIZE 0x0001
+#define US_DHD_DMA_SYNCHRONIZATION_LOG2_BYTE_SIZE 0x0001
+#define US_RUNNER_FLOW_IH_RESPONSE_ADDRESS 0xb6f0
+#define US_RUNNER_FLOW_IH_RESPONSE_BYTE_SIZE 0x0008
+#define US_RUNNER_FLOW_IH_RESPONSE_LOG2_BYTE_SIZE 0x0003
+#define ETH2_RX_DESCRIPTORS_ADDRESS 0xba00
+#define ETH2_RX_DESCRIPTORS_BYTE_SIZE 0x0100
+#define ETH2_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH2_RX_DESCRIPTORS_SIZE     32
+#define RDD_ETH2_RX_DESCRIPTORS_LOG2_SIZE     5
+#define ETH1_RX_DESCRIPTORS_ADDRESS 0xbc00
+#define ETH1_RX_DESCRIPTORS_BYTE_SIZE 0x0100
+#define ETH1_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH1_RX_DESCRIPTORS_SIZE     32
+#define RDD_ETH1_RX_DESCRIPTORS_LOG2_SIZE     5
+#define ETH0_RX_DESCRIPTORS_ADDRESS 0xbe00
+#define ETH0_RX_DESCRIPTORS_BYTE_SIZE 0x0100
+#define ETH0_RX_DESCRIPTORS_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETH0_RX_DESCRIPTORS_SIZE     32
+#define RDD_ETH0_RX_DESCRIPTORS_LOG2_SIZE     5
+#define BBH_TX_WAN_CHANNEL_INDEX_ADDRESS 0xbfe8
+#define BBH_TX_WAN_CHANNEL_INDEX_BYTE_SIZE 0x0004
+#define BBH_TX_WAN_CHANNEL_INDEX_LOG2_BYTE_SIZE 0x0002
+/* COMMON_A */
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_ADDRESS 0x0000
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_BYTE_SIZE 0x1000
+#define SERVICE_QUEUES_DDR_CACHE_FIFO_LOG2_BYTE_SIZE 0x000c
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_SIZE     256
+#define RDD_SERVICE_QUEUES_DDR_CACHE_FIFO_LOG2_SIZE     8
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS 0x1000
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define FC_MCAST_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_FC_MCAST_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define CPU_RX_RUNNER_A_SCRATCHPAD_ADDRESS 0x1800
+#define CPU_RX_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define CPU_RX_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_CPU_RX_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_ADDRESS 0x2000
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_BYTE_SIZE 0x0800
+#define DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE     8
+#define RDD_DS_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_LOG2_SIZE     3
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_ADDRESS 0x2800
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_BYTE_SIZE 0x0800
+#define WLAN_MCAST_RUNNER_A_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_SIZE     8
+#define RDD_WLAN_MCAST_RUNNER_A_SCRATCHPAD_LOG2_SIZE     3
+#define RUNNER_FWTRACE_MAINA_BASE_ADDRESS 0x3000
+#define RUNNER_FWTRACE_MAINA_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_MAINA_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_MAINA_BASE_LOG2_SIZE     7
+#define RUNNER_FWTRACE_PICOA_BASE_ADDRESS 0x3400
+#define RUNNER_FWTRACE_PICOA_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_PICOA_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_PICOA_BASE_LOG2_SIZE     7
+#define WLAN_MCAST_DHD_STATION_TABLE_ADDRESS 0x3800
+#define WLAN_MCAST_DHD_STATION_TABLE_BYTE_SIZE 0x0280
+#define WLAN_MCAST_DHD_STATION_TABLE_LOG2_BYTE_SIZE 0x000a
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_DHD_STATION_TABLE_LOG2_SIZE     6
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS 0x3a80
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_BYTE_SIZE 0x0080
+#define DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE     2
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE     1
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE2    64
+#define RDD_DS_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE2    6
+#define MAC_TABLE_CAM_ADDRESS 0x3b00
+#define MAC_TABLE_CAM_BYTE_SIZE 0x0100
+#define MAC_TABLE_CAM_LOG2_BYTE_SIZE 0x0008
+#define RDD_MAC_TABLE_CAM_SIZE     32
+#define RDD_MAC_TABLE_CAM_LOG2_SIZE     5
+#define MAC_TABLE_ADDRESS 0x3c00
+#define MAC_TABLE_BYTE_SIZE 0x0200
+#define MAC_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAC_TABLE_SIZE     64
+#define RDD_MAC_TABLE_LOG2_SIZE     6
+#define ETHWAN2_RX_INGRESS_QUEUE_ADDRESS 0x3e00
+#define ETHWAN2_RX_INGRESS_QUEUE_BYTE_SIZE 0x0100
+#define ETHWAN2_RX_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0008
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_SIZE     32
+#define RDD_ETHWAN2_RX_INGRESS_QUEUE_LOG2_SIZE     5
+#define TRACE_C_TABLE_ADDRESS 0x3f00
+#define TRACE_C_TABLE_BYTE_SIZE 0x0020
+#define TRACE_C_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_TRACE_C_TABLE_SIZE     4
+#define RDD_TRACE_C_TABLE_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_ADDRESS 0x3f20
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINA_CURR_OFFSET_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINA_CURR_OFFSET_LOG2_SIZE     1
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_ADDRESS 0x3f30
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_ADDRESS 0x3f34
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_FREE_SKB_INDEXES_FIFO_TABLE_LAST_ENTRY_LOG2_BYTE_SIZE 0x0002
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_ADDRESS 0x3f38
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_BYTE_SIZE 0x0008
+#define FREE_SKB_INDEXES_DDR_FIFO_TAIL_LOG2_BYTE_SIZE 0x0003
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_SIZE     2
+#define RDD_FREE_SKB_INDEXES_DDR_FIFO_TAIL_LOG2_SIZE     1
+#define BPM_REPLY_RUNNER_A_ADDRESS 0x3f40
+#define BPM_REPLY_RUNNER_A_BYTE_SIZE 0x0030
+#define BPM_REPLY_RUNNER_A_LOG2_BYTE_SIZE 0x0006
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_ADDRESS 0x3f70
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_BYTE_SIZE 0x0010
+#define DS_DHD_BACKUP_ENTRY_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define MAC_CONTEXT_TABLE_ADDRESS 0x3f80
+#define MAC_CONTEXT_TABLE_BYTE_SIZE 0x0080
+#define MAC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_MAC_CONTEXT_TABLE_SIZE     64
+#define RDD_MAC_CONTEXT_TABLE_LOG2_SIZE     6
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_ADDRESS 0x4000
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_BYTE_SIZE 0x0600
+#define GPON_SKB_ENQUEUED_INDEXES_FIFO_LOG2_BYTE_SIZE 0x000b
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_SIZE     32
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FIFO_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS 0x4600
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_BYTE_SIZE 0x0200
+#define DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_SIZE     8
+#define WLAN_MCAST_FWD_TABLE_ADDRESS 0x4800
+#define WLAN_MCAST_FWD_TABLE_BYTE_SIZE 0x0200
+#define WLAN_MCAST_FWD_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_FWD_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_FWD_TABLE_LOG2_SIZE     6
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_ADDRESS 0x4a00
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_BYTE_SIZE 0x0200
+#define SERVICE_QUEUES_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_DESCRIPTOR_TABLE_LOG2_SIZE     5
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_ADDRESS 0x4c00
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_BYTE_SIZE 0x0180
+#define WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE     48
+#define RDD_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_LOG2_SIZE     6
+#define CPU_TX_POST_REQUEST_QUEUE_ADDRESS 0x4d80
+#define CPU_TX_POST_REQUEST_QUEUE_BYTE_SIZE 0x0080
+#define CPU_TX_POST_REQUEST_QUEUE_LOG2_BYTE_SIZE 0x0007
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_SIZE     8
+#define RDD_CPU_TX_POST_REQUEST_QUEUE_LOG2_SIZE     3
+#define WLAN_MCAST_SSID_STATS_TABLE_ADDRESS 0x4e00
+#define WLAN_MCAST_SSID_STATS_TABLE_BYTE_SIZE 0x0180
+#define WLAN_MCAST_SSID_STATS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_SIZE     48
+#define RDD_WLAN_MCAST_SSID_STATS_TABLE_LOG2_SIZE     6
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_ADDRESS 0x4f80
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_BYTE_SIZE 0x0060
+#define DHD_RADIO_INSTANCE_COMMON_A_DATA_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_SIZE     3
+#define RDD_DHD_RADIO_INSTANCE_COMMON_A_DATA_LOG2_SIZE     2
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS 0x4fe0
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_BYTE_SIZE 0x0020
+#define DS_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+#define RDD_DS_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_SIZE     4
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS 0x5000
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_SIZE     7
+#define PM_COUNTERS_ADDRESS 0x5800
+#define PM_COUNTERS_BYTE_SIZE 0x1840
+#define PM_COUNTERS_LOG2_BYTE_SIZE 0x000d
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_ADDRESS 0x7040
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_BYTE_SIZE 0x0080
+#define RATE_SHAPERS_STATUS_DESCRIPTOR_LOG2_BYTE_SIZE 0x0007
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_SIZE     128
+#define RDD_RATE_SHAPERS_STATUS_DESCRIPTOR_LOG2_SIZE     7
+#define INTERRUPT_COALESCING_CONFIG_TABLE_ADDRESS 0x70c0
+#define INTERRUPT_COALESCING_CONFIG_TABLE_BYTE_SIZE 0x0040
+#define INTERRUPT_COALESCING_CONFIG_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_SIZE     16
+#define RDD_INTERRUPT_COALESCING_CONFIG_TABLE_LOG2_SIZE     4
+#define DS_CPU_TX_SCRATCHPAD_ADDRESS 0x7100
+#define DS_CPU_TX_SCRATCHPAD_BYTE_SIZE 0x0100
+#define DS_CPU_TX_SCRATCHPAD_LOG2_BYTE_SIZE 0x0008
+#define DS_CONNECTION_BUFFER_TABLE_ADDRESS 0x7200
+#define DS_CONNECTION_BUFFER_TABLE_BYTE_SIZE 0x0140
+#define DS_CONNECTION_BUFFER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_DS_CONNECTION_BUFFER_TABLE_LOG2_SIZE     3
+#define RDD_DS_CONNECTION_BUFFER_TABLE_SIZE2    4
+#define RDD_DS_CONNECTION_BUFFER_TABLE_LOG2_SIZE2    2
+#define MAC_CONTEXT_TABLE_CAM_ADDRESS 0x7340
+#define MAC_CONTEXT_TABLE_CAM_BYTE_SIZE 0x0040
+#define MAC_CONTEXT_TABLE_CAM_LOG2_BYTE_SIZE 0x0006
+#define RDD_MAC_CONTEXT_TABLE_CAM_SIZE     32
+#define RDD_MAC_CONTEXT_TABLE_CAM_LOG2_SIZE     5
+#define DHD_DOORBELL_WRITE_VALUES_ADDRESS 0x7380
+#define DHD_DOORBELL_WRITE_VALUES_BYTE_SIZE 0x0040
+#define DHD_DOORBELL_WRITE_VALUES_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_DOORBELL_WRITE_VALUES_SIZE     16
+#define RDD_DHD_DOORBELL_WRITE_VALUES_LOG2_SIZE     4
+#define DS_DHD_BACKUP_INDEX_CACHE_ADDRESS 0x73c0
+#define DS_DHD_BACKUP_INDEX_CACHE_BYTE_SIZE 0x0040
+#define DS_DHD_BACKUP_INDEX_CACHE_LOG2_BYTE_SIZE 0x0006
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_SIZE     32
+#define RDD_DS_DHD_BACKUP_INDEX_CACHE_LOG2_SIZE     5
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS 0x7400
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_BYTE_SIZE 0x0100
+#define DS_RING_PACKET_DESCRIPTORS_CACHE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+#define RDD_DS_RING_PACKET_DESCRIPTORS_CACHE_LOG2_SIZE     4
+#define RING_DESCRIPTORS_TABLE_ADDRESS 0x7500
+#define RING_DESCRIPTORS_TABLE_BYTE_SIZE 0x0100
+#define RING_DESCRIPTORS_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_RING_DESCRIPTORS_TABLE_SIZE     16
+#define RDD_RING_DESCRIPTORS_TABLE_LOG2_SIZE     4
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_ADDRESS 0x7600
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_BYTE_SIZE 0x0100
+#define SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_SIZE     32
+#define RDD_SERVICE_QUEUES_DDR_QUEUE_ADDRESS_TABLE_LOG2_SIZE     5
+#define MAC_EXTENSION_TABLE_ADDRESS 0x7700
+#define MAC_EXTENSION_TABLE_BYTE_SIZE 0x0040
+#define MAC_EXTENSION_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_MAC_EXTENSION_TABLE_SIZE     64
+#define RDD_MAC_EXTENSION_TABLE_LOG2_SIZE     6
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_ADDRESS 0x7740
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_BYTE_SIZE 0x0020
+#define DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_SIZE     16
+#define RDD_DHD_FLOW_RING_SHADOW_WR_PTR_TABLE_LOG2_SIZE     4
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_ADDRESS 0x7760
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0014
+#define DS_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_ADDRESS 0x7774
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_BYTE_SIZE 0x0004
+#define DDR_ADDRESS_FOR_SKB_DATA_POINTERS_TABLE_LOG2_BYTE_SIZE 0x0002
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_ADDRESS 0x7778
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_BYTE_SIZE 0x0008
+#define DS_DHD_BACKUP_FLUSH_SCRATCH_LOG2_BYTE_SIZE 0x0003
+#define SERVICE_QUEUES_CFG_ADDRESS 0x7780
+#define SERVICE_QUEUES_CFG_BYTE_SIZE 0x0014
+#define SERVICE_QUEUES_CFG_LOG2_BYTE_SIZE 0x0005
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_ADDRESS 0x7794
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_BYTE_SIZE 0x0004
+#define CPU_TX_POST_REQUEST_QUEUE_IDX_LOG2_BYTE_SIZE 0x0002
+#define MAC_EXTENSION_TABLE_CAM_ADDRESS 0x7798
+#define MAC_EXTENSION_TABLE_CAM_BYTE_SIZE 0x0020
+#define MAC_EXTENSION_TABLE_CAM_LOG2_BYTE_SIZE 0x0005
+#define RDD_MAC_EXTENSION_TABLE_CAM_SIZE     32
+#define RDD_MAC_EXTENSION_TABLE_CAM_LOG2_SIZE     5
+#define DS_CAM_DHD_DMA_SCRATCH_ADDRESS 0x77b8
+#define DS_CAM_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_CAM_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_ENQ_DHD_DMA_SCRATCH_ADDRESS 0x77bc
+#define DS_ENQ_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_ENQ_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define PM_COUNTERS_BUFFER_ADDRESS 0x77c0
+#define PM_COUNTERS_BUFFER_BYTE_SIZE 0x0020
+#define PM_COUNTERS_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define TX_CPL_DHD_DMA_SCRATCH_ADDRESS 0x77e0
+#define TX_CPL_DHD_DMA_SCRATCH_BYTE_SIZE 0x000c
+#define TX_CPL_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_SIZE     3
+#define RDD_TX_CPL_DHD_DMA_SCRATCH_LOG2_SIZE     2
+#define DS_R2D_DHD_DMA_SCRATCH_ADDRESS 0x77ec
+#define DS_R2D_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_R2D_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define DS_CPU_DHD_DMA_SCRATCH_ADDRESS 0x77f0
+#define DS_CPU_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define DS_CPU_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define TIMER_7_TIMER_PERIOD_ADDRESS 0x77f4
+#define TIMER_7_TIMER_PERIOD_BYTE_SIZE 0x0002
+#define TIMER_7_TIMER_PERIOD_LOG2_BYTE_SIZE 0x0001
+#define INTERRUPT_COALESCING_TIMER_PERIOD_ADDRESS 0x77f6
+#define INTERRUPT_COALESCING_TIMER_PERIOD_BYTE_SIZE 0x0002
+#define INTERRUPT_COALESCING_TIMER_PERIOD_LOG2_BYTE_SIZE 0x0001
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS 0x77f8
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_BYTE_SIZE 0x0004
+#define DS_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_SIZE     4
+#define RDD_DS_RATE_CONTROLLER_EXPONENT_TABLE_LOG2_SIZE     2
+#define INTERRUPT_COALESCING_TIMER_ARMED_ADDRESS 0x77fc
+#define INTERRUPT_COALESCING_TIMER_ARMED_BYTE_SIZE 0x0002
+#define INTERRUPT_COALESCING_TIMER_ARMED_LOG2_BYTE_SIZE 0x0001
+#define COMMON_A_DUMMY_STORE_ADDRESS 0x77fe
+#define COMMON_A_DUMMY_STORE_BYTE_SIZE 0x0001
+#define COMMON_A_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define FC_SERVICE_QUEUE_MODE_ADDRESS 0x77ff
+#define FC_SERVICE_QUEUE_MODE_BYTE_SIZE 0x0001
+#define FC_SERVICE_QUEUE_MODE_LOG2_BYTE_SIZE 0x0001
+#define MAIN_A_DEBUG_TRACE_ADDRESS 0x7a00
+#define MAIN_A_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define MAIN_A_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAIN_A_DEBUG_TRACE_SIZE     512
+#define RDD_MAIN_A_DEBUG_TRACE_LOG2_SIZE     9
+#define PICO_A_DEBUG_TRACE_ADDRESS 0x7c00
+#define PICO_A_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define PICO_A_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_PICO_A_DEBUG_TRACE_SIZE     512
+#define RDD_PICO_A_DEBUG_TRACE_LOG2_SIZE     9
+/* COMMON_B */
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_ADDRESS 0x8000
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_SIZE     128
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_LONG_TABLE_LOG2_SIZE     7
+#define CPU_RX_RUNNER_B_SCRATCHPAD_ADDRESS 0x8800
+#define CPU_RX_RUNNER_B_SCRATCHPAD_BYTE_SIZE 0x0800
+#define CPU_RX_RUNNER_B_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_SIZE     8
+#define RDD_CPU_RX_RUNNER_B_SCRATCHPAD_LOG2_SIZE     3
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_ADDRESS 0x9000
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_BYTE_SIZE 0x0200
+#define US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_COUNTERS_TABLE_LOG2_SIZE     8
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0x9200
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0100
+#define LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0008
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_SIZE     32
+#define RDD_LOCAL_SWITCHING_LAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     5
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS 0x9300
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_BYTE_SIZE 0x0100
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_SIZE     5
+#define WAN_TX_SERVICE_QUEUES_TABLE_ADDRESS 0x9400
+#define WAN_TX_SERVICE_QUEUES_TABLE_BYTE_SIZE 0x0800
+#define WAN_TX_SERVICE_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_SIZE     64
+#define RDD_WAN_TX_SERVICE_QUEUES_TABLE_LOG2_SIZE     6
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_ADDRESS 0x9c00
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_BYTE_SIZE 0x0100
+#define US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_SIZE     32
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_CAM_TABLE_LOG2_SIZE     5
+#define US_CPU_TX_SCRATCHPAD_ADDRESS 0x9d00
+#define US_CPU_TX_SCRATCHPAD_BYTE_SIZE 0x0100
+#define US_CPU_TX_SCRATCHPAD_LOG2_BYTE_SIZE 0x0008
+#define US_CONNECTION_BUFFER_TABLE_ADDRESS 0x9e00
+#define US_CONNECTION_BUFFER_TABLE_BYTE_SIZE 0x0140
+#define US_CONNECTION_BUFFER_TABLE_LOG2_BYTE_SIZE 0x0009
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE     5
+#define RDD_US_CONNECTION_BUFFER_TABLE_LOG2_SIZE     3
+#define RDD_US_CONNECTION_BUFFER_TABLE_SIZE2    4
+#define RDD_US_CONNECTION_BUFFER_TABLE_LOG2_SIZE2    2
+#define IPV6_HOST_ADDRESS_CRC_TABLE_ADDRESS 0x9f40
+#define IPV6_HOST_ADDRESS_CRC_TABLE_BYTE_SIZE 0x0040
+#define IPV6_HOST_ADDRESS_CRC_TABLE_LOG2_BYTE_SIZE 0x0006
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_SIZE     16
+#define RDD_IPV6_HOST_ADDRESS_CRC_TABLE_LOG2_SIZE     4
+#define DHD_BACKUP_INFO_CACHE_TABLE_ADDRESS 0x9f80
+#define DHD_BACKUP_INFO_CACHE_TABLE_BYTE_SIZE 0x0080
+#define DHD_BACKUP_INFO_CACHE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_SIZE     16
+#define RDD_DHD_BACKUP_INFO_CACHE_TABLE_LOG2_SIZE     4
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS 0xa000
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_BYTE_SIZE 0x0800
+#define DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+#define RDD_DS_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_SIZE     8
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_ADDRESS 0xa800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_BYTE_SIZE 0x0800
+#define US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_SIZE     256
+#define RDD_US_INGRESS_CLASSIFICATION_LOOKUP_TABLE_LOG2_SIZE     8
+#define WAN_TX_QUEUES_TABLE_ADDRESS 0xb000
+#define WAN_TX_QUEUES_TABLE_BYTE_SIZE 0x1000
+#define WAN_TX_QUEUES_TABLE_LOG2_BYTE_SIZE 0x000c
+#define RDD_WAN_TX_QUEUES_TABLE_SIZE     256
+#define RDD_WAN_TX_QUEUES_TABLE_LOG2_SIZE     8
+#define RUNNER_FWTRACE_MAINB_BASE_ADDRESS 0xc000
+#define RUNNER_FWTRACE_MAINB_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_MAINB_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_MAINB_BASE_LOG2_SIZE     7
+#define WAN_TX_RUNNER_B_SCRATCHPAD_ADDRESS 0xc400
+#define WAN_TX_RUNNER_B_SCRATCHPAD_BYTE_SIZE 0x0100
+#define WAN_TX_RUNNER_B_SCRATCHPAD_LOG2_BYTE_SIZE 0x0008
+#define US_RING_PACKET_DESCRIPTORS_CACHE_ADDRESS 0xc500
+#define US_RING_PACKET_DESCRIPTORS_CACHE_BYTE_SIZE 0x0100
+#define US_RING_PACKET_DESCRIPTORS_CACHE_LOG2_BYTE_SIZE 0x0008
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_SIZE     16
+#define RDD_US_RING_PACKET_DESCRIPTORS_CACHE_LOG2_SIZE     4
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_ADDRESS 0xc600
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_BYTE_SIZE 0x0100
+#define DHD_FLOW_RING_CACHE_CTX_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE     16
+#define RDD_DHD_FLOW_RING_CACHE_CTX_TABLE_LOG2_SIZE     4
+#define FC_FLOW_IP_ADDRESSES_TABLE_ADDRESS 0xc700
+#define FC_FLOW_IP_ADDRESSES_TABLE_BYTE_SIZE 0x00c0
+#define FC_FLOW_IP_ADDRESSES_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_SIZE     4
+#define RDD_FC_FLOW_IP_ADDRESSES_TABLE_LOG2_SIZE     2
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_ADDRESS 0xc7c0
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_BYTE_SIZE 0x0010
+#define RUNNER_FWTRACE_MAINB_CURR_OFFSET_LOG2_BYTE_SIZE 0x0004
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_SIZE     2
+#define RDD_RUNNER_FWTRACE_MAINB_CURR_OFFSET_LOG2_SIZE     1
+#define BPM_REPLY_RUNNER_B_ADDRESS 0xc7d0
+#define BPM_REPLY_RUNNER_B_BYTE_SIZE 0x0030
+#define BPM_REPLY_RUNNER_B_LOG2_BYTE_SIZE 0x0006
+#define US_RATE_CONTROLLERS_TABLE_ADDRESS 0xc800
+#define US_RATE_CONTROLLERS_TABLE_BYTE_SIZE 0x1800
+#define US_RATE_CONTROLLERS_TABLE_LOG2_BYTE_SIZE 0x000d
+#define RDD_US_RATE_CONTROLLERS_TABLE_SIZE     128
+#define RDD_US_RATE_CONTROLLERS_TABLE_LOG2_SIZE     7
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_ADDRESS 0xe000
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_BYTE_SIZE 0x0800
+#define US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_LOG2_BYTE_SIZE 0x000b
+#define RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_SIZE     8
+#define RDD_US_RX_SBPM_TO_FPM_COPY_SCRATCHPAD_LOG2_SIZE     3
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_ADDRESS 0xe800
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_BYTE_SIZE 0x00c0
+#define DHD_RADIO_INSTANCE_COMMON_B_DATA_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_SIZE     3
+#define RDD_DHD_RADIO_INSTANCE_COMMON_B_DATA_LOG2_SIZE     2
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_ADDRESS 0xe8c0
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_BYTE_SIZE 0x0040
+#define DUMMY_RATE_CONTROLLER_DESCRIPTOR_LOG2_BYTE_SIZE 0x0006
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_ADDRESS 0xe900
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_BYTE_SIZE 0x0050
+#define GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_BYTE_SIZE 0x0007
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_SIZE     40
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_FREE_PTR_LOG2_SIZE     6
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_ADDRESS 0xe950
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_BYTE_SIZE 0x0010
+#define DUMMY_WAN_TX_QUEUE_DESCRIPTOR_LOG2_BYTE_SIZE 0x0004
+#define IPV4_HOST_ADDRESS_TABLE_ADDRESS 0xe960
+#define IPV4_HOST_ADDRESS_TABLE_BYTE_SIZE 0x0020
+#define IPV4_HOST_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_IPV4_HOST_ADDRESS_TABLE_SIZE     8
+#define RDD_IPV4_HOST_ADDRESS_TABLE_LOG2_SIZE     3
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_ADDRESS 0xe980
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_BYTE_SIZE 0x0050
+#define GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_BYTE_SIZE 0x0007
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_SIZE     40
+#define RDD_GPON_SKB_ENQUEUED_INDEXES_PUT_PTR_LOG2_SIZE     6
+#define US_DHD_BACKUP_ENTRY_SCRATCH_ADDRESS 0xe9d0
+#define US_DHD_BACKUP_ENTRY_SCRATCH_BYTE_SIZE 0x0010
+#define US_DHD_BACKUP_ENTRY_SCRATCH_LOG2_BYTE_SIZE 0x0004
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS 0xe9e0
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_BYTE_SIZE 0x0020
+#define US_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_BYTE_SIZE 0x0005
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE     16
+#define RDD_US_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_SIZE     4
+#define MAIN_B_DEBUG_TRACE_ADDRESS 0xea00
+#define MAIN_B_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define MAIN_B_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_MAIN_B_DEBUG_TRACE_SIZE     512
+#define RDD_MAIN_B_DEBUG_TRACE_LOG2_SIZE     9
+#define PICO_B_DEBUG_TRACE_ADDRESS 0xec00
+#define PICO_B_DEBUG_TRACE_BYTE_SIZE 0x0200
+#define PICO_B_DEBUG_TRACE_LOG2_BYTE_SIZE 0x0009
+#define RDD_PICO_B_DEBUG_TRACE_SIZE     512
+#define RDD_PICO_B_DEBUG_TRACE_LOG2_SIZE     9
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_ADDRESS 0xee00
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_BYTE_SIZE 0x0080
+#define US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE     2
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE     1
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_SIZE2    64
+#define RDD_US_CPU_REASON_TO_CPU_RX_QUEUE_TABLE_LOG2_SIZE2    6
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_ADDRESS 0xee80
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_BYTE_SIZE 0x0080
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_1_LOG2_BYTE_SIZE 0x0007
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_ADDRESS 0xef00
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_BYTE_SIZE 0x0080
+#define PACKET_SRAM_TO_DDR_COPY_BUFFER_2_LOG2_BYTE_SIZE 0x0007
+#define LAN0_INGRESS_FIFO_ADDRESS 0xef80
+#define LAN0_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN0_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN5_INGRESS_FIFO_ADDRESS 0xefc0
+#define LAN5_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN5_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define RUNNER_FWTRACE_PICOB_BASE_ADDRESS 0xf000
+#define RUNNER_FWTRACE_PICOB_BASE_BYTE_SIZE 0x0400
+#define RUNNER_FWTRACE_PICOB_BASE_LOG2_BYTE_SIZE 0x000a
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_SIZE     128
+#define RDD_RUNNER_FWTRACE_PICOB_BASE_LOG2_SIZE     7
+#define LAN1_INGRESS_FIFO_ADDRESS 0xf400
+#define LAN1_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN1_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN6_INGRESS_FIFO_ADDRESS 0xf440
+#define LAN6_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN6_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN2_INGRESS_FIFO_ADDRESS 0xf480
+#define LAN2_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN2_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN7_INGRESS_FIFO_ADDRESS 0xf4c0
+#define LAN7_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN7_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define LAN3_INGRESS_FIFO_ADDRESS 0xf500
+#define LAN3_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN3_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define US_DHD_BACKUP_INDEX_CACHE_ADDRESS 0xf540
+#define US_DHD_BACKUP_INDEX_CACHE_BYTE_SIZE 0x0040
+#define US_DHD_BACKUP_INDEX_CACHE_LOG2_BYTE_SIZE 0x0006
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_SIZE     32
+#define RDD_US_DHD_BACKUP_INDEX_CACHE_LOG2_SIZE     5
+#define LAN4_INGRESS_FIFO_ADDRESS 0xf580
+#define LAN4_INGRESS_FIFO_BYTE_SIZE 0x0040
+#define LAN4_INGRESS_FIFO_LOG2_BYTE_SIZE 0x0006
+#define DHD_DOORBELL_COUNTERS_ADDRESS 0xf5c0
+#define DHD_DOORBELL_COUNTERS_BYTE_SIZE 0x0030
+#define DHD_DOORBELL_COUNTERS_LOG2_BYTE_SIZE 0x0006
+#define RDD_DHD_DOORBELL_COUNTERS_SIZE     48
+#define RDD_DHD_DOORBELL_COUNTERS_LOG2_SIZE     6
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_ADDRESS 0xf5f0
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_BYTE_SIZE 0x0010
+#define US_DHD_BACKUP_QUEUE_MANAGEMENT_INFO_LOG2_BYTE_SIZE 0x0004
+#define WAN_ENQUEUE_INGRESS_QUEUE_ADDRESS 0xf600
+#define WAN_ENQUEUE_INGRESS_QUEUE_BYTE_SIZE 0x0040
+#define WAN_ENQUEUE_INGRESS_QUEUE_LOG2_BYTE_SIZE 0x0006
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_SIZE     64
+#define RDD_WAN_ENQUEUE_INGRESS_QUEUE_LOG2_SIZE     6
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_ADDRESS 0xf640
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0014
+#define US_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0005
+#define US_CAM_DHD_DMA_SCRATCH_ADDRESS 0xf654
+#define US_CAM_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_CAM_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_DHD_BACKUP_FLUSH_SCRATCH_ADDRESS 0xf658
+#define US_DHD_BACKUP_FLUSH_SCRATCH_BYTE_SIZE 0x0008
+#define US_DHD_BACKUP_FLUSH_SCRATCH_LOG2_BYTE_SIZE 0x0003
+#define US_ENQ_DHD_DMA_SCRATCH_ADDRESS 0xf660
+#define US_ENQ_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_ENQ_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define US_R2D_DHD_DMA_SCRATCH_ADDRESS 0xf664
+#define US_R2D_DHD_DMA_SCRATCH_BYTE_SIZE 0x0004
+#define US_R2D_DHD_DMA_SCRATCH_LOG2_BYTE_SIZE 0x0002
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_ADDRESS 0xf668
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_BYTE_SIZE 0x0004
+#define CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_LOG2_BYTE_SIZE 0x0002
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_SIZE     4
+#define RDD_CPU_TX_DESCRIPTOR_QUEUE_TAIL_TABLE_LOG2_SIZE     2
+#define COMMON_B_DUMMY_STORE_ADDRESS 0xf66c
+#define COMMON_B_DUMMY_STORE_BYTE_SIZE 0x0001
+#define COMMON_B_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_ADDRESS 0xf66d
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_BYTE_SIZE 0x0001
+#define DHD_FLOW_RING_CACHE_CTX_NEXT_INDEX_LOG2_BYTE_SIZE 0x0001
+/* DDR */
+#define BPM_PACKET_BUFFERS_ADDRESS 0x0000
+#define BPM_PACKET_BUFFERS_BYTE_SIZE 0xf00000
+#define BPM_PACKET_BUFFERS_LOG2_BYTE_SIZE 0x0018
+#define RDD_BPM_PACKET_BUFFERS_SIZE     7680
+#define RDD_BPM_PACKET_BUFFERS_LOG2_SIZE     13
+#define CONTEXT_TABLE_ADDRESS 0x0000
+#define CONTEXT_TABLE_BYTE_SIZE 0x0084
+#define CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0008
+#define NAT_CACHE_TABLE_ADDRESS 0x0000
+#define NAT_CACHE_TABLE_BYTE_SIZE 0x100000
+#define NAT_CACHE_TABLE_LOG2_BYTE_SIZE 0x0014
+#define RDD_NAT_CACHE_TABLE_SIZE     65536
+#define RDD_NAT_CACHE_TABLE_LOG2_SIZE     16
+#define NAT_CACHE_EXTENSION_TABLE_ADDRESS 0x0000
+#define NAT_CACHE_EXTENSION_TABLE_BYTE_SIZE 0x0070
+#define NAT_CACHE_EXTENSION_TABLE_LOG2_BYTE_SIZE 0x0007
+#define RDD_NAT_CACHE_EXTENSION_TABLE_SIZE     7
+#define RDD_NAT_CACHE_EXTENSION_TABLE_LOG2_SIZE     3
+#define NATC_CONTEXT_TABLE_ADDRESS 0x0000
+#define NATC_CONTEXT_TABLE_BYTE_SIZE 0x400000
+#define NATC_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0016
+#define RDD_NATC_CONTEXT_TABLE_SIZE     65536
+#define RDD_NATC_CONTEXT_TABLE_LOG2_SIZE     16
+#define CONTEXT_CONTINUATION_TABLE_ADDRESS 0x0000
+#define CONTEXT_CONTINUATION_TABLE_BYTE_SIZE 0x4c0000
+#define CONTEXT_CONTINUATION_TABLE_LOG2_BYTE_SIZE 0x0017
+#define RDD_CONTEXT_CONTINUATION_TABLE_SIZE     65536
+#define RDD_CONTEXT_CONTINUATION_TABLE_LOG2_SIZE     16
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_ADDRESS 0x5d1500
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_BYTE_SIZE 0x00a0
+#define DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_SIZE     8
+#define RDD_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_TABLE_LOG2_SIZE     3
+#define DHD_RX_POST_DDR_BUFFER_ADDRESS 0x5c1100
+#define DHD_RX_POST_DDR_BUFFER_BYTE_SIZE 0x8000
+#define DHD_RX_POST_DDR_BUFFER_LOG2_BYTE_SIZE 0x000f
+#define RDD_DHD_RX_POST_DDR_BUFFER_SIZE     1024
+#define RDD_DHD_RX_POST_DDR_BUFFER_LOG2_SIZE     10
+#define DHD_RX_COMPLETE_DDR_BUFFER_ADDRESS 0x5c9100
+#define DHD_RX_COMPLETE_DDR_BUFFER_BYTE_SIZE 0x8000
+#define DHD_RX_COMPLETE_DDR_BUFFER_LOG2_BYTE_SIZE 0x000f
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_SIZE     1024
+#define RDD_DHD_RX_COMPLETE_DDR_BUFFER_LOG2_SIZE     10
+#define DHD_TX_POST_DDR_BUFFER_ADDRESS 0x5d15a0
+#define DHD_TX_POST_DDR_BUFFER_BYTE_SIZE 0x1800
+#define DHD_TX_POST_DDR_BUFFER_LOG2_BYTE_SIZE 0x000d
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE     8
+#define RDD_DHD_TX_POST_DDR_BUFFER_LOG2_SIZE     3
+#define RDD_DHD_TX_POST_DDR_BUFFER_SIZE2    16
+#define RDD_DHD_TX_POST_DDR_BUFFER_LOG2_SIZE2    4
+#define DHD_TX_COMPLETE_DDR_BUFFER_ADDRESS 0x5d2da0
+#define DHD_TX_COMPLETE_DDR_BUFFER_BYTE_SIZE 0x0100
+#define DHD_TX_COMPLETE_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_SIZE     16
+#define RDD_DHD_TX_COMPLETE_DDR_BUFFER_LOG2_SIZE     4
+#define R2D_WR_ARR_DDR_BUFFER_ADDRESS 0x5d1100
+#define R2D_WR_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define R2D_WR_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_R2D_WR_ARR_DDR_BUFFER_SIZE     128
+#define RDD_R2D_WR_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define D2R_RD_ARR_DDR_BUFFER_ADDRESS 0x5d1200
+#define D2R_RD_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define D2R_RD_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_D2R_RD_ARR_DDR_BUFFER_SIZE     128
+#define RDD_D2R_RD_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define R2D_RD_ARR_DDR_BUFFER_ADDRESS 0x5d1300
+#define R2D_RD_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define R2D_RD_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_R2D_RD_ARR_DDR_BUFFER_SIZE     128
+#define RDD_R2D_RD_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define D2R_WR_ARR_DDR_BUFFER_ADDRESS 0x5d1400
+#define D2R_WR_ARR_DDR_BUFFER_BYTE_SIZE 0x0100
+#define D2R_WR_ARR_DDR_BUFFER_LOG2_BYTE_SIZE 0x0008
+#define RDD_D2R_WR_ARR_DDR_BUFFER_SIZE     128
+#define RDD_D2R_WR_ARR_DDR_BUFFER_LOG2_SIZE     7
+#define DHD_BACKUP_QUEUES_BUFFER_ADDRESS 0x600000
+#define DHD_BACKUP_QUEUES_BUFFER_BYTE_SIZE 0x100000
+#define DHD_BACKUP_QUEUES_BUFFER_LOG2_BYTE_SIZE 0x0014
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_SIZE     524288
+#define RDD_DHD_BACKUP_QUEUES_BUFFER_LOG2_SIZE     19
+#define WLAN_MCAST_DHD_LIST_TABLE_ADDRESS 0x5c0000
+#define WLAN_MCAST_DHD_LIST_TABLE_BYTE_SIZE 0x1000
+#define WLAN_MCAST_DHD_LIST_TABLE_LOG2_BYTE_SIZE 0x000c
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE     64
+#define RDD_WLAN_MCAST_DHD_LIST_TABLE_LOG2_SIZE     6
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_ADDRESS 0x5c1000
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_BYTE_SIZE 0x0001
+#define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_LOG2_BYTE_SIZE 0x0001
+/* PSRAM */
+#endif
+#endif /* _RDD_RUNNER_DEFS_AUTO_H */
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_tm.c b/arch/arm/mach-bcmbca/rdp/rdd_tm.c
new file mode 100755
index 0000000000..e84bfd2bad
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_tm.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#include "rdd.h"
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Global Variables                                */
+/*                                                                            */
+/******************************************************************************/
+
+extern uint8_t *ContextTableBase;
+extern uint8_t *g_runner_ddr_base_addr;
+extern uint8_t *g_runner_tables_ptr;
+extern uint32_t                                     g_ddr_headroom_size;
+extern uint32_t                                     g_rate_controllers_pool_idx;
+extern BL_LILAC_RDD_BRIDGE_PORT_DTE                 g_broadcom_switch_physical_port;
+extern RDD_WAN_TX_POINTERS_TABLE_DTS                *wan_tx_pointers_table_ptr;
+extern bdmf_fastlock                                int_lock_irq;
+extern rdpa_bpm_buffer_size_t g_bpm_buffer_size;
+
+
+BL_LILAC_RDD_ERROR_DTE f_rdd_ds_exponent_table_initialize ( void )
+{
+    RDD_RATE_CONTROLLER_EXPONENT_TABLE_DTS    *exponent_table_ptr;
+    RDD_RATE_CONTROLLER_EXPONENT_ENTRY_DTS    *exponent_entry_ptr;
+
+    /* initialize exponents table */
+    exponent_table_ptr = ( RDD_RATE_CONTROLLER_EXPONENT_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_COMMON_0_OFFSET ) + DS_RATE_CONTROLLER_EXPONENT_TABLE_ADDRESS );
+
+    exponent_entry_ptr = &( exponent_table_ptr->entry[ 0 ] );
+    RDD_RATE_CONTROLLER_EXPONENT_ENTRY_EXPONENT_WRITE ( RDD_RATE_CONTROL_EXPONENT0, exponent_entry_ptr );
+
+    exponent_entry_ptr = &( exponent_table_ptr->entry[ 1 ] );
+    RDD_RATE_CONTROLLER_EXPONENT_ENTRY_EXPONENT_WRITE ( RDD_RATE_CONTROL_EXPONENT1, exponent_entry_ptr );
+
+    exponent_entry_ptr = &( exponent_table_ptr->entry[ 2 ] );
+    RDD_RATE_CONTROLLER_EXPONENT_ENTRY_EXPONENT_WRITE ( RDD_RATE_CONTROL_EXPONENT2, exponent_entry_ptr );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+BL_LILAC_RDD_ERROR_DTE rdd_eth_tx_queue_config ( BL_LILAC_RDD_EMAC_ID_DTE   xi_emac_id,
+                                                 BL_LILAC_RDD_QUEUE_ID_DTE  xi_queue_id,
+                                                 uint16_t                   xi_packet_threshold,
+                                                 rdd_queue_profile          xi_profile_id,
+                                                 uint8_t                    xi_counter_id )
+{
+    RDD_ETH_TX_QUEUE_DESCRIPTOR_DTS       *eth_tx_queue_descriptor_ptr;
+    RDD_ETH_TX_QUEUES_POINTERS_TABLE_DTS  *eth_tx_queues_pointers_table_ptr;
+    RDD_ETH_TX_QUEUE_POINTERS_ENTRY_DTS   *eth_tx_queue_pointers_entry_ptr;
+    uint16_t                              eth_tx_queue_descriptor_offset;
+    uint16_t                              queue_profile_address;
+
+    /* check the validity of the input parameters - emac id */
+    if ( ( xi_emac_id < BL_LILAC_RDD_EMAC_ID_START ) || ( xi_emac_id >= BL_LILAC_RDD_EMAC_ID_COUNT ) )
+    {
+        return ( BL_LILAC_RDD_ERROR_ILLEGAL_EMAC_ID );
+    }
+
+    /* check the validity of the input parameters - emac tx queue id */
+    if ( xi_queue_id > BL_LILAC_RDD_QUEUE_LAST )
+    {
+        return ( BL_LILAC_RDD_ERROR_ILLEGAL_QUEUE_ID );
+    }
+
+	if ( xi_emac_id == BL_LILAC_RDD_EMAC_ID_PCI )
+    {
+        /* PCI TX has 4 queues */
+        if (  xi_queue_id > BL_LILAC_RDD_QUEUE_3 )
+        {
+            return ( BL_LILAC_RDD_ERROR_ILLEGAL_QUEUE_ID );
+        }
+
+        if ( ( xi_profile_id == rdd_queue_profile_disabled ) && ( xi_packet_threshold > 0 ) )
+        {
+            /* PCI TX fifo imposes queue configuration larger than fifo size */
+            if ( xi_packet_threshold <= LILAC_RDD_PCI_TX_FIFO_SIZE )
+            {
+                return ( BL_LILAC_RDD_ERROR_PCI_QUEUE_THRESHOLD_TOO_SMALL );
+            }
+
+            xi_packet_threshold -= LILAC_RDD_PCI_TX_FIFO_SIZE;
+        }
+    }
+
+    eth_tx_queues_pointers_table_ptr = ( RDD_ETH_TX_QUEUES_POINTERS_TABLE_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + ETH_TX_QUEUES_POINTERS_TABLE_ADDRESS );
+
+    eth_tx_queue_pointers_entry_ptr = &( eth_tx_queues_pointers_table_ptr->entry[ xi_emac_id * RDD_EMAC_NUMBER_OF_QUEUES + xi_queue_id ] );
+
+    RDD_ETH_TX_QUEUE_POINTERS_ENTRY_TX_QUEUE_POINTER_READ ( eth_tx_queue_descriptor_offset, eth_tx_queue_pointers_entry_ptr );
+
+    eth_tx_queue_descriptor_ptr = ( RDD_ETH_TX_QUEUE_DESCRIPTOR_DTS * )(DEVICE_ADDRESS( RUNNER_PRIVATE_0_OFFSET ) + eth_tx_queue_descriptor_offset );
+
+    if ( xi_profile_id == rdd_queue_profile_disabled )
+    {
+        queue_profile_address = 0;
+    }
+    else
+    {
+        queue_profile_address = DS_QUEUE_PROFILE_TABLE_ADDRESS + xi_profile_id * sizeof ( RDD_QUEUE_PROFILE_DTS );
+    }
+
+    RDD_ETH_TX_QUEUE_DESCRIPTOR_PACKET_THRESHOLD_WRITE ( xi_packet_threshold, eth_tx_queue_descriptor_ptr );
+    RDD_ETH_TX_QUEUE_DESCRIPTOR_PROFILE_PTR_WRITE ( queue_profile_address, eth_tx_queue_descriptor_ptr );
+
+    return ( BL_LILAC_RDD_OK );
+}
+
+BL_LILAC_RDD_ERROR_DTE rdd_mdu_mode_pointer_get ( BL_LILAC_RDD_EMAC_ID_DTE  xi_emac_id,
+                                                  uint16_t                  *xo_mdu_mode_pointer )
+{
+    /* check the validity of the input parameters - emac id */
+    if ( ( xi_emac_id < BL_LILAC_RDD_EMAC_ID_0 ) || ( xi_emac_id >= BL_LILAC_RDD_EMAC_ID_COUNT ) )
+    {
+        return ( BL_LILAC_RDD_ERROR_ILLEGAL_EMAC_ID );
+    }
+
+    *xo_mdu_mode_pointer = ETH_TX_MAC_TABLE_ADDRESS + xi_emac_id * sizeof ( RDD_ETH_TX_MAC_DESCRIPTOR_DTS ) + LILAC_RDD_EMAC_EGRESS_COUNTER_OFFSET;
+
+    return ( BL_LILAC_RDD_OK );
+}
diff --git a/arch/arm/mach-bcmbca/rdp/rdd_tm.h b/arch/arm/mach-bcmbca/rdp/rdd_tm.h
new file mode 100755
index 0000000000..3c05947a7a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdd_tm.h
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef _BL_LILAC_DRV_RUNNER_TM_H
+#define _BL_LILAC_DRV_RUNNER_TM_H
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   rdd_eth_tx_queue_config                                                  */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   Firmware Driver - configure downstream Ethernet TX queue behind an EMAC. */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   configures EMAC TX queue:                                                */
+/*   - the packet threshold indicates how many packets can be TX pending      */
+/*     behind a TX queue.                                                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_emac_id - EMAC port index (ETH0 - ETH4)                               */
+/*   xi_queue_id - ETH TX queue index                                         */
+/*   xi_packet_threshold - ETH TX queue packet threshold. Overriden if WRED   */
+/*   and/or drop precedence is used                                           */
+/*   xi_profile_id - profile ID. If WRED and drop precedence not used, should */
+/*   be rdd_queue_profile_disabled. If enabled, xi_packet_threshold MUST be   */
+/*   equal to minimum low threshold in profile.                               */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   BL_LILAC_RDD_ERROR_DTE - Return status                                   */
+/*     BL_LILAC_RDD_OK - No error                                             */
+/*     BL_LILAC_RDD_ERROR_ILLEGAL_EMAC_ID - EMAC index is illegal.            */
+/*     BL_LILAC_RDD_ERROR_ILLEGAL_QUEUE_ID - queue index is greater then 7    */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_eth_tx_queue_config ( BL_LILAC_RDD_EMAC_ID_DTE   xi_emac_id,
+                                                 BL_LILAC_RDD_QUEUE_ID_DTE  xi_queue_id,
+                                                 uint16_t                   xi_packet_threshold,
+                                                 rdd_queue_profile          xi_profile_id,
+                                                 uint8_t                    xi_counter_id );
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Description:                                                               */
+/*                                                                            */
+/*   This function returns emac egress counter value for mdu mode.            */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_emac_id                                                               */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_mdu_mode_pointer                                                      */
+/*                                                                            */
+/******************************************************************************/
+BL_LILAC_RDD_ERROR_DTE rdd_mdu_mode_pointer_get ( BL_LILAC_RDD_EMAC_ID_DTE  xi_emac_id,
+                                                  uint16_t                  *xo_mdu_mode_pointer );
+
+#endif /* _BL_LILAC_DRV_RUNNER_TM_H */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_bbh.h b/arch/arm/mach-bcmbca/rdp/rdp_bbh.h
new file mode 100755
index 0000000000..6ac37eb972
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_bbh.h
@@ -0,0 +1,13913 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/             
+
+#ifndef __RDP_BBH_H_INCLUDED
+#define __RDP_BBH_H_INCLUDED
+
+/*  File automatically generated by Reggae at 15/08/2013  10:54:27   */
+
+#include "access_macros.h"
+#include "packing.h"
+#include "rdp_map.h"
+/*****************************************************************************************/
+/* The Broad-Bus Handler (BBH) purpose is to manage the interface between the Peripheral */
+/* s (GPON, EPON and SGMII) and between the IH, the Runners, the SRAM/DDR DMA and the SR */
+/* AM/DDR BPM in two levels: the physical level and the protocol level.   In the physica */
+/* l level the BBH manages the interfaces both for the RX and TX units. It manages a FIF */
+/* O based interface with the GPON, EPON or EMAC peripherals and the BB interface with t */
+/* he IH, the Runners, the DDR/SRAM DMA and the DDR/SRAM BPM.    In the protocol level t */
+/* he BBH manages the RX and TX protocol between the Peripheral and the IH, the Runners, */
+/*  the DDR/SRAM DMA and the DDR/SRAM BPM.   On the RX side the BBH reads the data from  */
+/* the peripheral’s FIFO and writes the packet header into the IH. After the IH header p */
+/* rocessing it reassembles the incoming data in the DDR or in the SRAM, using their DMA */
+/*  and writes a packet descriptor (in the Runner SRAM) for each Packet. It is also resp */
+/* onsible of sending wakeup requests to the Runner for every PD it sends. It manages th */
+/* e DDR/SRAM buffers, using the BPM  On the TX side it either gets an indication of the */
+/*  TX FIFO capacity from the Peripheral (GPON) or gets a request for packet (EPON). The */
+/* n it requests a PD from the Runner accordingly. For both EPON and GPON peripherals it */
+/*  also manages a round-robin algorithm for the requests of the different queues. Accor */
+/* ding to the Runner PD, the BBH will then read the data from the DDR or from the SRAM, */
+/*  using their DMA. Upon reading the whole packet from the DDR, the BBH will release th */
+/* e DDR/SRAM buffer, using the BPM.                                                     */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Blocks offsets                                                                        */
+/*****************************************************************************************/
+/*****************************************************************************************/
+/* Functions offsets and addresses                                                       */
+/*****************************************************************************************/
+#define BBH_RX_0_GENERAL_CONFIGURATION_OFFSET 	( 0x00000000 )
+#define BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS	( BBH_RX_0_OFFSET + BBH_RX_0_GENERAL_CONFIGURATION_OFFSET )
+
+#define BBH_RX_0_PM_COUNTERS_OFFSET 	( 0x00000100 )
+#define BBH_RX_0_PM_COUNTERS_ADDRESS	( BBH_RX_0_OFFSET + BBH_RX_0_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_0_DEBUG_OFFSET 	( 0x00000200 )
+#define BBH_RX_0_DEBUG_ADDRESS	( BBH_RX_0_OFFSET + BBH_RX_0_DEBUG_OFFSET )
+
+#define BBH_RX_0_PER_FLOW_PM_COUNTERS_OFFSET 	( 0x00000400 )
+#define BBH_RX_0_PER_FLOW_PM_COUNTERS_ADDRESS	( BBH_RX_0_OFFSET + BBH_RX_0_PER_FLOW_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_OFFSET 	( 0x00000000 )
+#define BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS	( BBH_RX_1_OFFSET + BBH_RX_1_GENERAL_CONFIGURATION_OFFSET )
+
+#define BBH_RX_1_PM_COUNTERS_OFFSET 	( 0x00000100 )
+#define BBH_RX_1_PM_COUNTERS_ADDRESS	( BBH_RX_1_OFFSET + BBH_RX_1_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_1_DEBUG_OFFSET 	( 0x00000200 )
+#define BBH_RX_1_DEBUG_ADDRESS	( BBH_RX_1_OFFSET + BBH_RX_1_DEBUG_OFFSET )
+
+#define BBH_RX_1_PER_FLOW_PM_COUNTERS_OFFSET 	( 0x00000400 )
+#define BBH_RX_1_PER_FLOW_PM_COUNTERS_ADDRESS	( BBH_RX_1_OFFSET + BBH_RX_1_PER_FLOW_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_OFFSET 	( 0x00000000 )
+#define BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS	( BBH_RX_2_OFFSET + BBH_RX_2_GENERAL_CONFIGURATION_OFFSET )
+
+#define BBH_RX_2_PM_COUNTERS_OFFSET 	( 0x00000100 )
+#define BBH_RX_2_PM_COUNTERS_ADDRESS	( BBH_RX_2_OFFSET + BBH_RX_2_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_2_DEBUG_OFFSET 	( 0x00000200 )
+#define BBH_RX_2_DEBUG_ADDRESS	( BBH_RX_2_OFFSET + BBH_RX_2_DEBUG_OFFSET )
+
+#define BBH_RX_2_PER_FLOW_PM_COUNTERS_OFFSET 	( 0x00000400 )
+#define BBH_RX_2_PER_FLOW_PM_COUNTERS_ADDRESS	( BBH_RX_2_OFFSET + BBH_RX_2_PER_FLOW_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_OFFSET 	( 0x00000000 )
+#define BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS	( BBH_RX_3_OFFSET + BBH_RX_3_GENERAL_CONFIGURATION_OFFSET )
+
+#define BBH_RX_3_PM_COUNTERS_OFFSET 	( 0x00000100 )
+#define BBH_RX_3_PM_COUNTERS_ADDRESS	( BBH_RX_3_OFFSET + BBH_RX_3_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_3_DEBUG_OFFSET 	( 0x00000200 )
+#define BBH_RX_3_DEBUG_ADDRESS	( BBH_RX_3_OFFSET + BBH_RX_3_DEBUG_OFFSET )
+
+#define BBH_RX_3_PER_FLOW_PM_COUNTERS_OFFSET 	( 0x00000400 )
+#define BBH_RX_3_PER_FLOW_PM_COUNTERS_ADDRESS	( BBH_RX_3_OFFSET + BBH_RX_3_PER_FLOW_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_OFFSET 	( 0x00000000 )
+#define BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS	( BBH_RX_4_OFFSET + BBH_RX_4_GENERAL_CONFIGURATION_OFFSET )
+
+#define BBH_RX_4_PM_COUNTERS_OFFSET 	( 0x00000100 )
+#define BBH_RX_4_PM_COUNTERS_ADDRESS	( BBH_RX_4_OFFSET + BBH_RX_4_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_4_DEBUG_OFFSET 	( 0x00000200 )
+#define BBH_RX_4_DEBUG_ADDRESS	( BBH_RX_4_OFFSET + BBH_RX_4_DEBUG_OFFSET )
+
+#define BBH_RX_4_PER_FLOW_PM_COUNTERS_OFFSET 	( 0x00000400 )
+#define BBH_RX_4_PER_FLOW_PM_COUNTERS_ADDRESS	( BBH_RX_4_OFFSET + BBH_RX_4_PER_FLOW_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_OFFSET 	( 0x00000000 )
+#define BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS	( BBH_RX_5_OFFSET + BBH_RX_5_GENERAL_CONFIGURATION_OFFSET )
+
+#define BBH_RX_5_PM_COUNTERS_OFFSET 	( 0x00000100 )
+#define BBH_RX_5_PM_COUNTERS_ADDRESS	( BBH_RX_5_OFFSET + BBH_RX_5_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_5_DEBUG_OFFSET 	( 0x00000200 )
+#define BBH_RX_5_DEBUG_ADDRESS	( BBH_RX_5_OFFSET + BBH_RX_5_DEBUG_OFFSET )
+
+#define BBH_RX_5_PER_FLOW_PM_COUNTERS_OFFSET 	( 0x00000400 )
+#define BBH_RX_5_PER_FLOW_PM_COUNTERS_ADDRESS	( BBH_RX_5_OFFSET + BBH_RX_5_PER_FLOW_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_OFFSET 	( 0x00000000 )
+#define BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS	( BBH_RX_6_OFFSET + BBH_RX_6_GENERAL_CONFIGURATION_OFFSET )
+
+#define BBH_RX_6_PM_COUNTERS_OFFSET 	( 0x00000100 )
+#define BBH_RX_6_PM_COUNTERS_ADDRESS	( BBH_RX_6_OFFSET + BBH_RX_6_PM_COUNTERS_OFFSET )
+
+#define BBH_RX_6_DEBUG_OFFSET 	( 0x00000200 )
+#define BBH_RX_6_DEBUG_ADDRESS	( BBH_RX_6_OFFSET + BBH_RX_6_DEBUG_OFFSET )
+
+#define BBH_RX_6_PER_FLOW_PM_COUNTERS_OFFSET 	( 0x00000400 )
+#define BBH_RX_6_PER_FLOW_PM_COUNTERS_ADDRESS	( BBH_RX_6_OFFSET + BBH_RX_6_PER_FLOW_PM_COUNTERS_OFFSET )
+
+#define BBH_TX_0_CONFIGURATIONS_OFFSET 	( 0x00000000 )
+#define BBH_TX_0_CONFIGURATIONS_ADDRESS	( BBH_TX_0_OFFSET + BBH_TX_0_CONFIGURATIONS_OFFSET )
+
+#define BBH_TX_0_DEBUG_OFFSET 	( 0x00000100 )
+#define BBH_TX_0_DEBUG_ADDRESS	( BBH_TX_0_OFFSET + BBH_TX_0_DEBUG_OFFSET )
+
+#define BBH_TX_0_PD_FIFO_OFFSET 	( 0x00000200 )
+#define BBH_TX_0_PD_FIFO_ADDRESS	( BBH_TX_0_OFFSET + BBH_TX_0_PD_FIFO_OFFSET )
+
+#define BBH_TX_0_CONTEXT_OFFSET 	( 0x00000600 )
+#define BBH_TX_0_CONTEXT_ADDRESS	( BBH_TX_0_OFFSET + BBH_TX_0_CONTEXT_OFFSET )
+
+#define BBH_TX_0_EPON_PD_FIFO_OFFSET 	( 0x00000700 )
+#define BBH_TX_0_EPON_PD_FIFO_ADDRESS	( BBH_TX_0_OFFSET + BBH_TX_0_EPON_PD_FIFO_OFFSET )
+
+#define BBH_TX_0_EPON_CFG_OFFSET 	( 0x00001000 )
+#define BBH_TX_0_EPON_CFG_ADDRESS	( BBH_TX_0_OFFSET + BBH_TX_0_EPON_CFG_OFFSET )
+
+#define BBH_TX_0_EPON_DBG_OFFSET 	( 0x00001100 )
+#define BBH_TX_0_EPON_DBG_ADDRESS	( BBH_TX_0_OFFSET + BBH_TX_0_EPON_DBG_OFFSET )
+
+#define BBH_TX_0_EPON_STS_FIFO_OFFSET 	( 0x00001700 )
+#define BBH_TX_0_EPON_STS_FIFO_ADDRESS	( BBH_TX_0_OFFSET + BBH_TX_0_EPON_STS_FIFO_OFFSET )
+
+#define BBH_TX_1_CONFIGURATIONS_OFFSET 	( 0x00000000 )
+#define BBH_TX_1_CONFIGURATIONS_ADDRESS	( BBH_TX_1_OFFSET + BBH_TX_1_CONFIGURATIONS_OFFSET )
+
+#define BBH_TX_1_DEBUG_OFFSET 	( 0x00000100 )
+#define BBH_TX_1_DEBUG_ADDRESS	( BBH_TX_1_OFFSET + BBH_TX_1_DEBUG_OFFSET )
+
+#define BBH_TX_1_PD_FIFO_OFFSET 	( 0x00000200 )
+#define BBH_TX_1_PD_FIFO_ADDRESS	( BBH_TX_1_OFFSET + BBH_TX_1_PD_FIFO_OFFSET )
+
+#define BBH_TX_1_CONTEXT_OFFSET 	( 0x00000600 )
+#define BBH_TX_1_CONTEXT_ADDRESS	( BBH_TX_1_OFFSET + BBH_TX_1_CONTEXT_OFFSET )
+
+#define BBH_TX_1_EPON_PD_FIFO_OFFSET 	( 0x00000700 )
+#define BBH_TX_1_EPON_PD_FIFO_ADDRESS	( BBH_TX_1_OFFSET + BBH_TX_1_EPON_PD_FIFO_OFFSET )
+
+#define BBH_TX_1_EPON_CFG_OFFSET 	( 0x00001000 )
+#define BBH_TX_1_EPON_CFG_ADDRESS	( BBH_TX_1_OFFSET + BBH_TX_1_EPON_CFG_OFFSET )
+
+#define BBH_TX_1_EPON_DBG_OFFSET 	( 0x00001100 )
+#define BBH_TX_1_EPON_DBG_ADDRESS	( BBH_TX_1_OFFSET + BBH_TX_1_EPON_DBG_OFFSET )
+
+#define BBH_TX_1_EPON_STS_FIFO_OFFSET 	( 0x00001700 )
+#define BBH_TX_1_EPON_STS_FIFO_ADDRESS	( BBH_TX_1_OFFSET + BBH_TX_1_EPON_STS_FIFO_OFFSET )
+
+#define BBH_TX_2_CONFIGURATIONS_OFFSET 	( 0x00000000 )
+#define BBH_TX_2_CONFIGURATIONS_ADDRESS	( BBH_TX_2_OFFSET + BBH_TX_2_CONFIGURATIONS_OFFSET )
+
+#define BBH_TX_2_DEBUG_OFFSET 	( 0x00000100 )
+#define BBH_TX_2_DEBUG_ADDRESS	( BBH_TX_2_OFFSET + BBH_TX_2_DEBUG_OFFSET )
+
+#define BBH_TX_2_PD_FIFO_OFFSET 	( 0x00000200 )
+#define BBH_TX_2_PD_FIFO_ADDRESS	( BBH_TX_2_OFFSET + BBH_TX_2_PD_FIFO_OFFSET )
+
+#define BBH_TX_2_CONTEXT_OFFSET 	( 0x00000600 )
+#define BBH_TX_2_CONTEXT_ADDRESS	( BBH_TX_2_OFFSET + BBH_TX_2_CONTEXT_OFFSET )
+
+#define BBH_TX_2_EPON_PD_FIFO_OFFSET 	( 0x00000700 )
+#define BBH_TX_2_EPON_PD_FIFO_ADDRESS	( BBH_TX_2_OFFSET + BBH_TX_2_EPON_PD_FIFO_OFFSET )
+
+#define BBH_TX_2_EPON_CFG_OFFSET 	( 0x00001000 )
+#define BBH_TX_2_EPON_CFG_ADDRESS	( BBH_TX_2_OFFSET + BBH_TX_2_EPON_CFG_OFFSET )
+
+#define BBH_TX_2_EPON_DBG_OFFSET 	( 0x00001100 )
+#define BBH_TX_2_EPON_DBG_ADDRESS	( BBH_TX_2_OFFSET + BBH_TX_2_EPON_DBG_OFFSET )
+
+#define BBH_TX_2_EPON_STS_FIFO_OFFSET 	( 0x00001700 )
+#define BBH_TX_2_EPON_STS_FIFO_ADDRESS	( BBH_TX_2_OFFSET + BBH_TX_2_EPON_STS_FIFO_OFFSET )
+
+#define BBH_TX_3_CONFIGURATIONS_OFFSET 	( 0x00000000 )
+#define BBH_TX_3_CONFIGURATIONS_ADDRESS	( BBH_TX_3_OFFSET + BBH_TX_3_CONFIGURATIONS_OFFSET )
+
+#define BBH_TX_3_DEBUG_OFFSET 	( 0x00000100 )
+#define BBH_TX_3_DEBUG_ADDRESS	( BBH_TX_3_OFFSET + BBH_TX_3_DEBUG_OFFSET )
+
+#define BBH_TX_3_PD_FIFO_OFFSET 	( 0x00000200 )
+#define BBH_TX_3_PD_FIFO_ADDRESS	( BBH_TX_3_OFFSET + BBH_TX_3_PD_FIFO_OFFSET )
+
+#define BBH_TX_3_CONTEXT_OFFSET 	( 0x00000600 )
+#define BBH_TX_3_CONTEXT_ADDRESS	( BBH_TX_3_OFFSET + BBH_TX_3_CONTEXT_OFFSET )
+
+#define BBH_TX_3_EPON_PD_FIFO_OFFSET 	( 0x00000700 )
+#define BBH_TX_3_EPON_PD_FIFO_ADDRESS	( BBH_TX_3_OFFSET + BBH_TX_3_EPON_PD_FIFO_OFFSET )
+
+#define BBH_TX_3_EPON_CFG_OFFSET 	( 0x00001000 )
+#define BBH_TX_3_EPON_CFG_ADDRESS	( BBH_TX_3_OFFSET + BBH_TX_3_EPON_CFG_OFFSET )
+
+#define BBH_TX_3_EPON_DBG_OFFSET 	( 0x00001100 )
+#define BBH_TX_3_EPON_DBG_ADDRESS	( BBH_TX_3_OFFSET + BBH_TX_3_EPON_DBG_OFFSET )
+
+#define BBH_TX_3_EPON_STS_FIFO_OFFSET 	( 0x00001700 )
+#define BBH_TX_3_EPON_STS_FIFO_ADDRESS	( BBH_TX_3_OFFSET + BBH_TX_3_EPON_STS_FIFO_OFFSET )
+
+#define BBH_TX_4_CONFIGURATIONS_OFFSET 	( 0x00000000 )
+#define BBH_TX_4_CONFIGURATIONS_ADDRESS	( BBH_TX_4_OFFSET + BBH_TX_4_CONFIGURATIONS_OFFSET )
+
+#define BBH_TX_4_DEBUG_OFFSET 	( 0x00000100 )
+#define BBH_TX_4_DEBUG_ADDRESS	( BBH_TX_4_OFFSET + BBH_TX_4_DEBUG_OFFSET )
+
+#define BBH_TX_4_PD_FIFO_OFFSET 	( 0x00000200 )
+#define BBH_TX_4_PD_FIFO_ADDRESS	( BBH_TX_4_OFFSET + BBH_TX_4_PD_FIFO_OFFSET )
+
+#define BBH_TX_4_CONTEXT_OFFSET 	( 0x00000600 )
+#define BBH_TX_4_CONTEXT_ADDRESS	( BBH_TX_4_OFFSET + BBH_TX_4_CONTEXT_OFFSET )
+
+#define BBH_TX_4_EPON_PD_FIFO_OFFSET 	( 0x00000700 )
+#define BBH_TX_4_EPON_PD_FIFO_ADDRESS	( BBH_TX_4_OFFSET + BBH_TX_4_EPON_PD_FIFO_OFFSET )
+
+#define BBH_TX_4_EPON_CFG_OFFSET 	( 0x00001000 )
+#define BBH_TX_4_EPON_CFG_ADDRESS	( BBH_TX_4_OFFSET + BBH_TX_4_EPON_CFG_OFFSET )
+
+#define BBH_TX_4_EPON_DBG_OFFSET 	( 0x00001100 )
+#define BBH_TX_4_EPON_DBG_ADDRESS	( BBH_TX_4_OFFSET + BBH_TX_4_EPON_DBG_OFFSET )
+
+#define BBH_TX_4_EPON_STS_FIFO_OFFSET 	( 0x00001700 )
+#define BBH_TX_4_EPON_STS_FIFO_ADDRESS	( BBH_TX_4_OFFSET + BBH_TX_4_EPON_STS_FIFO_OFFSET )
+
+#define BBH_TX_5_CONFIGURATIONS_OFFSET 	( 0x00000000 )
+#define BBH_TX_5_CONFIGURATIONS_ADDRESS	( BBH_TX_5_OFFSET + BBH_TX_5_CONFIGURATIONS_OFFSET )
+
+#define BBH_TX_5_DEBUG_OFFSET 	( 0x00000100 )
+#define BBH_TX_5_DEBUG_ADDRESS	( BBH_TX_5_OFFSET + BBH_TX_5_DEBUG_OFFSET )
+
+#define BBH_TX_5_PD_FIFO_OFFSET 	( 0x00000200 )
+#define BBH_TX_5_PD_FIFO_ADDRESS	( BBH_TX_5_OFFSET + BBH_TX_5_PD_FIFO_OFFSET )
+
+#define BBH_TX_5_CONTEXT_OFFSET 	( 0x00000600 )
+#define BBH_TX_5_CONTEXT_ADDRESS	( BBH_TX_5_OFFSET + BBH_TX_5_CONTEXT_OFFSET )
+
+#define BBH_TX_5_EPON_PD_FIFO_OFFSET 	( 0x00000700 )
+#define BBH_TX_5_EPON_PD_FIFO_ADDRESS	( BBH_TX_5_OFFSET + BBH_TX_5_EPON_PD_FIFO_OFFSET )
+
+#define BBH_TX_5_EPON_CFG_OFFSET 	( 0x00001000 )
+#define BBH_TX_5_EPON_CFG_ADDRESS	( BBH_TX_5_OFFSET + BBH_TX_5_EPON_CFG_OFFSET )
+
+#define BBH_TX_5_EPON_DBG_OFFSET 	( 0x00001100 )
+#define BBH_TX_5_EPON_DBG_ADDRESS	( BBH_TX_5_OFFSET + BBH_TX_5_EPON_DBG_OFFSET )
+
+#define BBH_TX_5_EPON_STS_FIFO_OFFSET 	( 0x00001700 )
+#define BBH_TX_5_EPON_STS_FIFO_ADDRESS	( BBH_TX_5_OFFSET + BBH_TX_5_EPON_STS_FIFO_OFFSET )
+
+#define BBH_TX_6_CONFIGURATIONS_OFFSET 	( 0x00000000 )
+#define BBH_TX_6_CONFIGURATIONS_ADDRESS	( BBH_TX_6_OFFSET + BBH_TX_6_CONFIGURATIONS_OFFSET )
+
+#define BBH_TX_6_DEBUG_OFFSET 	( 0x00000100 )
+#define BBH_TX_6_DEBUG_ADDRESS	( BBH_TX_6_OFFSET + BBH_TX_6_DEBUG_OFFSET )
+
+#define BBH_TX_6_PD_FIFO_OFFSET 	( 0x00000200 )
+#define BBH_TX_6_PD_FIFO_ADDRESS	( BBH_TX_6_OFFSET + BBH_TX_6_PD_FIFO_OFFSET )
+
+#define BBH_TX_6_CONTEXT_OFFSET 	( 0x00000600 )
+#define BBH_TX_6_CONTEXT_ADDRESS	( BBH_TX_6_OFFSET + BBH_TX_6_CONTEXT_OFFSET )
+
+#define BBH_TX_6_EPON_PD_FIFO_OFFSET 	( 0x00000700 )
+#define BBH_TX_6_EPON_PD_FIFO_ADDRESS	( BBH_TX_6_OFFSET + BBH_TX_6_EPON_PD_FIFO_OFFSET )
+
+#define BBH_TX_6_EPON_CFG_OFFSET 	( 0x00001000 )
+#define BBH_TX_6_EPON_CFG_ADDRESS	( BBH_TX_6_OFFSET + BBH_TX_6_EPON_CFG_OFFSET )
+
+#define BBH_TX_6_EPON_DBG_OFFSET 	( 0x00001100 )
+#define BBH_TX_6_EPON_DBG_ADDRESS	( BBH_TX_6_OFFSET + BBH_TX_6_EPON_DBG_OFFSET )
+
+#define BBH_TX_6_EPON_STS_FIFO_OFFSET 	( 0x00001700 )
+#define BBH_TX_6_EPON_STS_FIFO_ADDRESS	( BBH_TX_6_OFFSET + BBH_TX_6_EPON_STS_FIFO_OFFSET )
+
+/*   'd' is module index   */
+/*   'i' is block index    */
+/*   'j' is function index */
+/*   'e' is function entry */
+/*   'k' is register index */
+
+/*****************************************************************************************/
+/* Broad-Bus_configuration                                                               */
+/* Each BBH unit has its own position on the BB tree. This position defines the Route ad */
+/* dress when approaching the Runner, S/DMA, S/BPM and IH.                               */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_R4_DEFAULT_VALUE                       ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_R4_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_BPMROUTE_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_BPMROUTE_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_R3_DEFAULT_VALUE                       ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_R3_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_DMAROUTE_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_DMAROUTE_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_R2_DEFAULT_VALUE                       ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_R2_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RUNNER1ROUTE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RUNNER1ROUTE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_R1_DEFAULT_VALUE                       ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_R1_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RUNNER0ROUTE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RUNNER0ROUTE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_OFFSET ( 0x00000000 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_BBCFG_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_BBCFG_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_BBCFG_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_BBCFG_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_BBCFG_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_BBCFG_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_BBCFG_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_BBCFG_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_BBCFG_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_BBCFG_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_BBCFG_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_BBCFG_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_BBCFG_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_BBCFG_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_BBCFG_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_BBCFG_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_BBCFG_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_BBCFG_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_BBCFG_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_BBCFG_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_BBCFG_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_BBCFG_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_BBCFG_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_BBCFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_route */
+	uint32_t bpmroute    	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_route */
+	uint32_t dmaroute    	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner1_route */
+	uint32_t runner1route	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner0_route */
+	uint32_t runner0route	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_BBCFG ;
+#else
+typedef struct
+{	uint32_t runner0route	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner0_route */
+	uint32_t r1          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t runner1route	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner1_route */
+	uint32_t r2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t dmaroute    	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_route */
+	uint32_t r3          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t bpmroute    	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_route */
+	uint32_t r4          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_BBCFG ;
+#endif
+
+/*****************************************************************************************/
+/* Broad-Bus_configuration                                                               */
+/* Each BBH unit has its own position on the BB tree. This position defines the Route ad */
+/* dress when approaching the Runner, S/DMA, S/BPM and IH.                               */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_R4_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_R4_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_SBPMROUTE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_SBPMROUTE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_R3_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_R3_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_SDMAROUTE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_SDMAROUTE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_R2_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_R2_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_IHROUTE_DEFAULT_VALUE               ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_IHROUTE_DEFAULT_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_R1_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_R1_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_OFFSET ( 0x00000004 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_BBCFG1_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG1_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_BBCFG1_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_BBCFG1_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_BBCFG1_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG1_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_BBCFG1_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_BBCFG1_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_BBCFG1_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG1_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_BBCFG1_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_BBCFG1_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_BBCFG1_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG1_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_BBCFG1_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_BBCFG1_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_BBCFG1_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG1_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_BBCFG1_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_BBCFG1_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_BBCFG1_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG1_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_BBCFG1_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_BBCFG1_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_BBCFG1_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG1_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_BBCFG1_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_BBCFG1_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_BBCFG1_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_BBCFG1_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG1_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_BBCFG1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_route */
+	uint32_t sbpmroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA_route */
+	uint32_t sdmaroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_route */
+	uint32_t ihroute  	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1       	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_BBCFG1 ;
+#else
+typedef struct
+{	uint32_t r1       	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t ihroute  	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_route */
+	uint32_t r2       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t sdmaroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA_route */
+	uint32_t r3       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t sbpmroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_route */
+	uint32_t r4       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_BBCFG1 ;
+#endif
+
+/*****************************************************************************************/
+/* DDR_configuration                                                                     */
+/* The BBH reassembles the incoming data in the DDR. The data is stored in a fixed buffe */
+/* rs structure.   This register defines the DDR buffer size and the TM base address in  */
+/* the DDR.                                                                              */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_DDRTMBASE_DDRTMBASE_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_DDRTMBASE_DDRTMBASE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_R2_DEFAULT_VALUE                      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_R2_DEFAULT_VALUE_RESET_VALUE          ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_BUFSIZE_BUF2K_VALUE                   ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_BUFSIZE_BUF2K_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_BUFSIZE_BUF4K_VALUE                   ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_BUFSIZE_BUF16K_VALUE                  ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_BUFSIZE_R_VALUE                       ( 0x3 )
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_BPMMSG_14_BIT_BN_WIDTH_VALUE          ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_BPMMSG_15_BIT_BN_WIDTH_VALUE          ( 0x1 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_OFFSET ( 0x00000008 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_DDRCFG_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DDRCFG_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_DDRCFG_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_DDRCFG_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_DDRCFG_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DDRCFG_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_DDRCFG_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_DDRCFG_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_DDRCFG_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DDRCFG_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_DDRCFG_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_DDRCFG_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_DDRCFG_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DDRCFG_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_DDRCFG_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_DDRCFG_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_DDRCFG_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DDRCFG_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_DDRCFG_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_DDRCFG_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_DDRCFG_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DDRCFG_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_DDRCFG_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_DDRCFG_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_DDRCFG_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DDRCFG_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_DDRCFG_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_DDRCFG_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_DDRCFG_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_DDRCFG_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_DDRCFG_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_DDRCFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DDRTMBASE */
+	uint32_t ddrtmbase	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	uint32_t bpmmsg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_buffer_size */
+	uint32_t bufsize  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_DDRCFG ;
+#else
+typedef struct
+{	uint32_t bufsize  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	uint32_t bpmmsg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	/* DDR_buffer_size */
+	uint32_t r2       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t ddrtmbase	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDRTMBASE */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_DDRCFG ;
+#endif
+
+/*****************************************************************************************/
+/* Runner_PD_base_address                                                                */
+/* For every reassembled packet in the DDR the BBH writes a packet descriptor (PD) into  */
+/* the Runner. The PDs are arranged in a predefined address space in the Runner SRAM and */
+/*  managed in a cyclic FIFO style.   This register defines the base address of this cyc */
+/* lic FIFO.                                                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_PDBASE_DIRECT_PDBASE_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDBASE_DIRECT_PDBASE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDBASE_NORMAL_PDBASE_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDBASE_NORMAL_PDBASE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_PDBASE_OFFSET ( 0x0000000C )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_PDBASE_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDBASE_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_PDBASE_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_PDBASE_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_PDBASE_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDBASE_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_PDBASE_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_PDBASE_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_PDBASE_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDBASE_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_PDBASE_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_PDBASE_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_PDBASE_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDBASE_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_PDBASE_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_PDBASE_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_PDBASE_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDBASE_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_PDBASE_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_PDBASE_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_PDBASE_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDBASE_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_PDBASE_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_PDBASE_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_PDBASE_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDBASE_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_PDBASE_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_PDBASE_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_PDBASE_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_PDBASE_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_PDBASE_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_PDBASE_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_PDBASE_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PD_base_address_for_direct_queue */
+	uint32_t direct	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_base_address_for_normal_queue */
+	uint32_t normal	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_PDBASE ;
+#else
+typedef struct
+{	uint32_t normal	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_base_address_for_normal_queue */
+	uint32_t direct	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_base_address_for_direct_queue */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_PDBASE ;
+#endif
+
+/*****************************************************************************************/
+/* Ruuner_PD_size                                                                        */
+/* For every reassembled packet in the DDR the BBH writes a packet descriptor (PD) into  */
+/* the Runner. The PDs are arranged in a predefined address space in the Runner SRAM and */
+/*  managed in a cyclic FIFO style.   This register defines the size of this cyclic FIFO */
+/* .                                                                                     */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_R2_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_R2_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_DIRECT_MIN_VALUE_VALUE           ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_DIRECT_DEFAULT_VALUE             ( 0x20 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_DIRECT_DEFAULT_VALUE_RESET_VALUE ( 0x20 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_DIRECT_MAX_VALUE_VALUE           ( 0x40 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_R1_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_R1_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_NORMAL_MIN_VALUE_VALUE           ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_NORMAL_DEFAULT_VALUE             ( 0x20 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_NORMAL_DEFAULT_VALUE_RESET_VALUE ( 0x20 )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_NORMAL_MAX_VALUE_VALUE           ( 0x40 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_OFFSET ( 0x00000010 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_PDSIZE_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDSIZE_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_PDSIZE_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_PDSIZE_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_PDSIZE_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDSIZE_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_PDSIZE_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_PDSIZE_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_PDSIZE_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDSIZE_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_PDSIZE_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_PDSIZE_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_PDSIZE_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDSIZE_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_PDSIZE_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_PDSIZE_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_PDSIZE_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDSIZE_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_PDSIZE_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_PDSIZE_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_PDSIZE_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDSIZE_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_PDSIZE_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_PDSIZE_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_PDSIZE_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDSIZE_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_PDSIZE_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_PDSIZE_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_PDSIZE_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_PDSIZE_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_PDSIZE_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_PDSIZE_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2    	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Number_Of_PDs_for_direct_queue */
+	uint32_t direct	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1    	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Number_Of_PDs_for_normal_queue */
+	uint32_t normal	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_PDSIZE ;
+#else
+typedef struct
+{	uint32_t normal	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Number_Of_PDs_for_normal_queue */
+	uint32_t r1    	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t direct	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Number_Of_PDs_for_direct_queue */
+	uint32_t r2    	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_PDSIZE ;
+#endif
+
+/*****************************************************************************************/
+/* Runner_task                                                                           */
+/* For every reassembled packet in the DDR the BBH writes a packet descriptor (PD) into  */
+/* the Runner. The PDs are arranged in a predefined address space in the Runner SRAM and */
+/*  managed in a cyclic FIFO style.   For every PD written into the Runner, the BBH wake */
+/* s the relevantThread. This register defines the Runner thread number for both Runners */
+/*  and both queues (normal or direct).                                                  */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_R4_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_R4_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_DIRECT1_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_DIRECT1_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_R3_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_R3_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_NORMAL1_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_NORMAL1_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_R2_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_R2_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_DIRECT0_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_DIRECT0_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_R1_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_R1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_NORMAL0_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_NORMAL0_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_OFFSET ( 0x00000014 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_RUNNERTASK_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_RUNNERTASK_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_RUNNERTASK_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_RUNNERTASK_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_RUNNERTASK_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_RUNNERTASK_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_RUNNERTASK_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_RUNNERTASK_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_RUNNERTASK_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_RUNNERTASK_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_RUNNERTASK_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_RUNNERTASK_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_RUNNERTASK_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_RUNNERTASK_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Direct_1_thread */
+	uint32_t direct1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Normal_1_thread */
+	uint32_t normal1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Direct_0_thread */
+	uint32_t direct0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Normal_0_thread */
+	uint32_t normal0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK ;
+#else
+typedef struct
+{	uint32_t normal0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Normal_0_thread */
+	uint32_t r1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t direct0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Direct_0_thread */
+	uint32_t r2     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t normal1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Normal_1_thread */
+	uint32_t r3     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t direct1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Direct_1_thread */
+	uint32_t r4     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK ;
+#endif
+
+/*****************************************************************************************/
+/* DMA_address_configuration                                                             */
+/* The BBH reassembles the incoming data in the DDR. The Data is written into the DDR us */
+/* ing the DMA. The data is organized in a configurable number of chunks of 128 bytes.   */
+/* The BBH arranges the written data in the DMA in these chunks. It arranges the data in */
+/*  a predefined address space in the DMA memory and manages the chunks in a cyclic FIFO */
+/*  style.  For every write chunk the BBH writes a write descriptor. The write descripto */
+/* rs are arranged in a predefined space in the DMA memory and managed in a cyclic FIFO  */
+/* style as well.  This register defines the Data and descriptors base addresses.        */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_DMAADDR_R2_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMAADDR_R2_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMAADDR_DESCBASE_BASEADDR_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMAADDR_DESCBASE_BASEADDR_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMAADDR_R1_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMAADDR_R1_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMAADDR_DATABASE_BASEADDR_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMAADDR_DATABASE_BASEADDR_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_DMAADDR_OFFSET ( 0x00000018 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_DMAADDR_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMAADDR_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_DMAADDR_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_DMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_DMAADDR_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMAADDR_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_DMAADDR_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_DMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_DMAADDR_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMAADDR_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_DMAADDR_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_DMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_DMAADDR_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMAADDR_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_DMAADDR_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_DMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_DMAADDR_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMAADDR_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_DMAADDR_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_DMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_DMAADDR_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMAADDR_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_DMAADDR_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_DMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_DMAADDR_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMAADDR_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_DMAADDR_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_DMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_DMAADDR_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_DMAADDR_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_DMAADDR_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_DMAADDR_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_DMAADDR_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2      	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Descriptor_base_address */
+	uint32_t descbase	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1      	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Data_base_address */
+	uint32_t database	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_DMAADDR ;
+#else
+typedef struct
+{	uint32_t database	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Data_base_address */
+	uint32_t r1      	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t descbase	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Descriptor_base_address */
+	uint32_t r2      	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_DMAADDR ;
+#endif
+
+/*****************************************************************************************/
+/* DMA_configuration                                                                     */
+/* The BBH reassembles the incoming data in the DDR. The Data is written into the DDR us */
+/* ing the DMA. The data is organized in a configurable number of chunks of 128 bytes.   */
+/* The BBH arranges the written data in the DMA in these chunks. It arranges the data in */
+/*  a predefined address space in the DMA memory and manages the chunks in a cyclic FIFO */
+/*  style.  For every write chunk the BBH writes a write descriptor. The write descripto */
+/* rs are arranged in a predefined space in the DMA memory and managed in a cyclic FIFO  */
+/* style as well.    The BBH handles the congestion over the DMA write chunks according  */
+/* to 2 priorities (low + high, exclusive). This field defines the number of occupied wr */
+/* ite chunks for dropping normal or high priority packets. If the number of occupied ch */
+/* unk is lower than this threshold, then all packets are passed. If the number of occup */
+/* ied chunk is equal or higher than this threshold, then only exclusive priority packet */
+/* s are passed.    This register defines the Data and descriptors FIFO sizes and the ex */
+/* clusive threshold.                                                                    */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_R2_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_R2_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_EXCLTH_MIN_VALUE_VALUE            ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_EXCLTH_DEFAULT_VALUE              ( 0x8 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_EXCLTH_DEFAULT_VALUE_RESET_VALUE  ( 0x8 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_EXCLTH_MAX_VALUE_VALUE            ( 0x40 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_R1_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_R1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_NUMOFCD_MIN_VALUE_VALUE           ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_NUMOFCD_DEFAULT_VALUE             ( 0x10 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_NUMOFCD_DEFAULT_VALUE_RESET_VALUE ( 0x10 )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_NUMOFCD_MAX_VALUE_VALUE           ( 0x40 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_OFFSET ( 0x0000001C )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_DMACFG_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMACFG_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_DMACFG_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_DMACFG_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_DMACFG_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMACFG_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_DMACFG_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_DMACFG_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_DMACFG_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMACFG_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_DMACFG_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_DMACFG_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_DMACFG_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMACFG_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_DMACFG_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_DMACFG_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_DMACFG_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMACFG_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_DMACFG_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_DMACFG_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_DMACFG_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMACFG_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_DMACFG_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_DMACFG_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_DMACFG_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMACFG_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_DMACFG_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_DMACFG_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_DMACFG_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_DMACFG_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_DMACFG_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_DMACFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2     	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Exclusive_threshold */
+	uint32_t exclth 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Number_of_Chunk-Descriptors */
+	uint32_t numofcd	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_DMACFG ;
+#else
+typedef struct
+{	uint32_t numofcd	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Number_of_Chunk-Descriptors */
+	uint32_t r1     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t exclth 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Exclusive_threshold */
+	uint32_t r2     	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_DMACFG ;
+#endif
+
+/*****************************************************************************************/
+/* SDMA_address_configuration                                                            */
+/* The BBH reassembles the incoming data in the SRAM. The Data is written into the SRAM  */
+/* using the SDMA. The data is organized in a configurable number of chunks of 128 bytes */
+/* .  The BBH arranges the written data in the SDMA in these chunks. It arranges the dat */
+/* a in a predefined address space in the SDMA memory and manages the chunks in a cyclic */
+/*  FIFO style.  For every write chunk the BBH writes a write descriptor. The write desc */
+/* riptors are arranged in a predefined space in the SDMA memory and managed in a cyclic */
+/*  FIFO style as well.  This register defines the Data and descriptors base addresses.  */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_R2_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_R2_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DESCBASE_BASEADDR_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DESCBASE_BASEADDR_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_R1_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_R1_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DATABASE_BASEADDR_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DATABASE_BASEADDR_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_OFFSET ( 0x00000020 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_SDMAADDR_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_SDMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_SDMAADDR_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_SDMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_SDMAADDR_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_SDMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_SDMAADDR_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_SDMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_SDMAADDR_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_SDMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_SDMAADDR_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_SDMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_SDMAADDR_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_SDMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2      	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Descriptor_base_address */
+	uint32_t descbase	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1      	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Data_base_address */
+	uint32_t database	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_SDMAADDR ;
+#else
+typedef struct
+{	uint32_t database	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Data_base_address */
+	uint32_t r1      	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t descbase	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Descriptor_base_address */
+	uint32_t r2      	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_SDMAADDR ;
+#endif
+
+/*****************************************************************************************/
+/* SDMA_configuration                                                                    */
+/* The BBH reassembles the incoming data in the SRAM. The Data is written into the SRAM  */
+/* using the SDMA. The data is organized in a configurable number of chunks of 128 bytes */
+/* .  The BBH arranges the written data in the SDMA in these chunks. It arranges the dat */
+/* a in a predefined address space in the SDMA memory and manages the chunks in a cyclic */
+/*  FIFO style.  For every write chunk the BBH writes a write descriptor. The write desc */
+/* riptors are arranged in a predefined space in the SDMA memory and managed in a cyclic */
+/*  FIFO style as well.    The BBH handles the congestion over the SDMA write chunks acc */
+/* ording to 2 priorities (low + high, exclusive). This field defines the number of occu */
+/* pied write chunks for dropping normal or high priority packets. If the number of occu */
+/* pied chunk is lower than this threshold, then all packets are passed. If the number o */
+/* f occupied chunk is equal or higher than this threshold, then only exclusive priority */
+/*  packets are passed.    This register defines the Data and descriptors FIFO sizes and */
+/*  the exclusive threshold.                                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_R2_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_R2_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_MIN_VALUE_VALUE            ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_DEFAULT_VALUE              ( 0x8 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_DEFAULT_VALUE_RESET_VALUE  ( 0x8 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_MAX_VALUE_VALUE            ( 0x40 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_R1_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_R1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_MIN_VALUE_VALUE           ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_DEFAULT_VALUE             ( 0x10 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_DEFAULT_VALUE_RESET_VALUE ( 0x10 )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_MAX_VALUE_VALUE           ( 0x40 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_OFFSET ( 0x00000024 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_SDMACFG_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMACFG_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_SDMACFG_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_SDMACFG_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_SDMACFG_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMACFG_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_SDMACFG_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_SDMACFG_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_SDMACFG_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMACFG_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_SDMACFG_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_SDMACFG_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_SDMACFG_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMACFG_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_SDMACFG_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_SDMACFG_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_SDMACFG_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMACFG_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_SDMACFG_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_SDMACFG_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_SDMACFG_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMACFG_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_SDMACFG_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_SDMACFG_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_SDMACFG_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMACFG_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_SDMACFG_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_SDMACFG_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_SDMACFG_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_SDMACFG_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_SDMACFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2     	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Exclusive_threshold */
+	uint32_t exclth 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Number_of_Chunk-Descriptors */
+	uint32_t numofcd	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_SDMACFG ;
+#else
+typedef struct
+{	uint32_t numofcd	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Number_of_Chunk-Descriptors */
+	uint32_t r1     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t exclth 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Exclusive_threshold */
+	uint32_t r2     	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_SDMACFG ;
+#endif
+
+/*****************************************************************************************/
+/* Minimum_Packet_size                                                                   */
+/* There are 4 global configuration for Minimum packet size. Each flow can get one out o */
+/* f these 4 global configurations.  Packets shorter than this threshold will be discard */
+/* ed.  Min packet size should keep the following restriction:  Min packet size < 128 –  */
+/* SOP offset                                                                            */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT3_MINPKT_VALUE             ( 0x40 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT3_MINPKT_VALUE_RESET_VALUE ( 0x40 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT3_MAX_VALUE_VALUE          ( 0x60 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT2_MINPKT_VALUE             ( 0x40 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT2_MINPKT_VALUE_RESET_VALUE ( 0x40 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT2_MAX_VALUE_VALUE          ( 0x60 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT1_MINPKT_VALUE             ( 0x40 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT1_MINPKT_VALUE_RESET_VALUE ( 0x40 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT1_MAX_VALUE_VALUE          ( 0x60 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT0_MINPKT_VALUE             ( 0x40 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT0_MINPKT_VALUE_RESET_VALUE ( 0x40 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT0_MAX_VALUE_VALUE          ( 0x60 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_OFFSET ( 0x00000028 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_MINPKT0_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKT0_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MINPKT0_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MINPKT0_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_MINPKT0_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKT0_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MINPKT0_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MINPKT0_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_MINPKT0_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKT0_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MINPKT0_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MINPKT0_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_MINPKT0_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKT0_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MINPKT0_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MINPKT0_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_MINPKT0_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKT0_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MINPKT0_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MINPKT0_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_MINPKT0_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKT0_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MINPKT0_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MINPKT0_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_MINPKT0_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKT0_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MINPKT0_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MINPKT0_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_MINPKT0_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_MINPKT0_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_MINPKT0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Minimum_Packet_3 */
+	uint32_t minpkt3	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_Packet_2 */
+	uint32_t minpkt2	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_Packet_1 */
+	uint32_t minpkt1	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_Packet_0 */
+	uint32_t minpkt0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MINPKT0 ;
+#else
+typedef struct
+{	uint32_t minpkt0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_Packet_0 */
+	uint32_t minpkt1	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_Packet_1 */
+	uint32_t minpkt2	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_Packet_2 */
+	uint32_t minpkt3	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_Packet_3 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MINPKT0 ;
+#endif
+
+/*****************************************************************************************/
+/* Maximum_Packet_size_0                                                                 */
+/* There are 4 global configuration for Maximum packet size. Each flow can get one out o */
+/* f these 4 global configurations.  Packets longer than this threshold will be discarde */
+/* d.  It should not exceed the DDR buffer size and should keep the following restrictio */
+/* n:  Max packet size <= DDR buffer size – SOP offset - reassembly offset*8             */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_R2_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_R2_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT1_MAXPKT_VALUE             ( 0x600 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT1_MAXPKT_VALUE_RESET_VALUE ( 0x600 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_R1_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_R1_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT0_MAXPKT_VALUE             ( 0x600 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT0_MAXPKT_VALUE_RESET_VALUE ( 0x600 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_OFFSET ( 0x0000002C )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT0_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT0_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT0_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT0_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT0_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT0_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT0_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT0_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT0_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT0_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT0_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT0_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT0_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT0_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_Packet_1 */
+	uint32_t maxpkt1	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_Packet_0 */
+	uint32_t maxpkt0	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MAXPKT0 ;
+#else
+typedef struct
+{	uint32_t maxpkt0	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_Packet_0 */
+	uint32_t r1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t maxpkt1	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_Packet_1 */
+	uint32_t r2     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MAXPKT0 ;
+#endif
+
+/*****************************************************************************************/
+/* Maximum_Packet_size_1                                                                 */
+/* There are 4 global configuration for Maximum packet size. Each flow can get one out o */
+/* f these 4 global configurations.  Packets longer than this threshold will be discarde */
+/* d.  It should not exceed the DDR buffer size and should keep the following restrictio */
+/* n:  Max packet size <= DDR buffer size – SOP offset - reassembly offset*8             */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_R2_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_R2_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT3_MAXPKT_VALUE             ( 0x600 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT3_MAXPKT_VALUE_RESET_VALUE ( 0x600 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_R1_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_R1_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT2_MAXPKT_VALUE             ( 0x600 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT2_MAXPKT_VALUE_RESET_VALUE ( 0x600 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_OFFSET ( 0x00000030 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT1_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT1_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT1_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT1_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT1_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT1_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT1_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT1_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT1_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT1_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT1_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT1_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT1_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT1_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_Packet_3 */
+	uint32_t maxpkt3	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_Packet_2 */
+	uint32_t maxpkt2	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MAXPKT1 ;
+#else
+typedef struct
+{	uint32_t maxpkt2	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_Packet_2 */
+	uint32_t r1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t maxpkt3	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_Packet_3 */
+	uint32_t r2     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MAXPKT1 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_configuration                                                                      */
+/* The BBH writes the packets header into the IH. The start of data offset is configurab */
+/* le.  The IH has 16 ingress buffer for all ingress ports.    This register defines the */
+/*  SOP (start of packet) offset and the ingress buffers which are assigned to the BBH.  */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCFG_R1_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCFG_R1_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCFG_SOPOFFSET_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCFG_SOPOFFSET_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCFG_IHBUFEN_DEFAULT_VALUE               ( 0xF )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCFG_IHBUFEN_DEFAULT_VALUE_RESET_VALUE   ( 0xF )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCFG_OFFSET ( 0x00000034 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCFG_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCFG_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCFG_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCFG_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCFG_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCFG_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCFG_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCFG_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCFG_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCFG_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCFG_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCFG_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCFG_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCFG_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCFG_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCFG_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCFG_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCFG_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCFG_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCFG_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCFG_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCFG_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCFG_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCFG_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCFG_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCFG_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCFG_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCFG_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_IHCFG_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCFG_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_IHCFG_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCFG_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_IHCFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1       	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SOP_offset */
+	uint32_t sopoffset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_buffer_enable */
+	uint32_t ihbufen  	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHCFG ;
+#else
+typedef struct
+{	uint32_t ihbufen  	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_buffer_enable */
+	uint32_t sopoffset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SOP_offset */
+	uint32_t r1       	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHCFG ;
+#endif
+
+/*****************************************************************************************/
+/* Flow_control_configuration                                                            */
+/* The BBH manages a flow control indication towards the Ethernet MAC with the following */
+/*  considerations:  - 	According to the level of the DDR and/or SRAM allocated buffers  */
+/* (status from the BPM).  - 	According to a FW request.    This register defines which  */
+/* of the above will be considerred (may consider more than one).                        */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_R2_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_R2_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_DMADROPEN_DISABLE_VALUE              ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_DMADROPEN_ENABLE_VALUE               ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_DMADROPEN_ENABLE_VALUE_RESET_VALUE   ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMDROPEN_DISABLE_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMDROPEN_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMDROPEN_ENABLE_VALUE              ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_BPMDROPEN_DISABLE_VALUE              ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_BPMDROPEN_DISABLE_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_BPMDROPEN_ENABLE_VALUE               ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_R1_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_R1_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RUNNEREN_DEFAULT_VALUE               ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RUNNEREN_DEFAULT_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMEN_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMEN_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_BPMEN_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_BPMEN_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_OFFSET ( 0x00000038 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_FLOWCTRL_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_FLOWCTRL_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_FLOWCTRL_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_FLOWCTRL_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_FLOWCTRL_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_FLOWCTRL_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_FLOWCTRL_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_FLOWCTRL_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_FLOWCTRL_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_FLOWCTRL_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_FLOWCTRL_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_FLOWCTRL_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_FLOWCTRL_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_FLOWCTRL_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2        	: 21 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_drop_enable */
+	uint32_t dmadropen 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_drop_enable */
+	uint32_t sbpmdropen	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_drop_enable */
+	uint32_t bpmdropen 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_enable */
+	uint32_t runneren  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_enable */
+	uint32_t sbpmen    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_enable */
+	uint32_t bpmen     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL ;
+#else
+typedef struct
+{	uint32_t bpmen     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_enable */
+	uint32_t sbpmen    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_enable */
+	uint32_t runneren  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_enable */
+	uint32_t r1        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t bpmdropen 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_drop_enable */
+	uint32_t sbpmdropen	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_drop_enable */
+	uint32_t dmadropen 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_drop_enable */
+	uint32_t r2        	: 21 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL ;
+#endif
+
+/*****************************************************************************************/
+/* Per_flow_threshold.                                                                   */
+/* The DS has 256 flows. There are 4 configuration which are per flow:  1. IH class numb */
+/* er (4 bits)   2. IH class override enable (1 bit)  3. Minimum packet size (2 bits).   */
+/* 4. Maximum packet size (2 bits).    Flows 0-31 will have full options 9 bit configura */
+/* tions.  Flows 32-X will have set 0 configuration (9 global bits).  Flows (X+1)-255 wi */
+/* ll have set 1 configurations (additional 9 global bits).  X is configurable.    For E */
+/* thernet – flow 0 should be configured.    This register defines the  threshold (x).   */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_R3_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_R3_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_DEFAULT_VALUE             ( 0x20 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_DEFAULT_VALUE_RESET_VALUE ( 0x20 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_MIN_VALUE_VALUE           ( 0x20 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_MAX_VALUE_VALUE           ( 0xFF )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_OFFSET ( 0x0000003C )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWTH_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWTH_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWTH_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWTH_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWTH_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWTH_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWTH_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWTH_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWTH_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWTH_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWTH_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWTH_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWTH_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWTH_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r3    	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_threshold */
+	uint32_t flowth	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH ;
+#else
+typedef struct
+{	uint32_t flowth	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_threshold */
+	uint32_t r3    	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH ;
+#endif
+
+/*****************************************************************************************/
+/* Per_flow_sets.                                                                        */
+/* The DS has 256 flows. There are 4 configuration which are per flow:  1. IH class numb */
+/* er (4 bits)   2. IH class override enable (1 bit)  3. Minimum packet size (2 bits).   */
+/* 4. Maximum packet size (2 bits).    Flows 0-31 will have full options 9 bit configura */
+/* tions.  Flows 32-X will have set 0 configuration (9 global bits).  Flows (X+1)-255 wi */
+/* ll have set 1 configurations (additional 9 global bits).  X is configurable.    For E */
+/* thernet – flow 0 should be configured.    This register defines the 2 sets of the gen */
+/* eral configurations.                                                                  */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_R2_DEFAULT_VALUE                        ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_R2_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OVERRIDE1_NO_OVERRIDE_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OVERRIDE1_NO_OVERRIDE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OVERRIDE1_OVERRIDE_VALUE                ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_IHCLASS1_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_IHCLASS1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_GLOBAL_0_VALUE               ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_GLOBAL_0_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_GLOBAL_1_VALUE               ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_GLOBAL_2_VALUE               ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_GLOBAL_3_VALUE               ( 0x3 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_GLOBAL_0_VALUE               ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_GLOBAL_0_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_GLOBAL_1_VALUE               ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_GLOBAL_2_VALUE               ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_GLOBAL_3_VALUE               ( 0x3 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_R1_DEFAULT_VALUE                        ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_R1_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OVERRIDE0_NO_OVERRIDE_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OVERRIDE0_NO_OVERRIDE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OVERRIDE0_OVERRIDE_VALUE                ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_IHCLASS0_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_IHCLASS0_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_GLOBAL_0_VALUE               ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_GLOBAL_0_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_GLOBAL_1_VALUE               ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_GLOBAL_2_VALUE               ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_GLOBAL_3_VALUE               ( 0x3 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_GLOBAL_0_VALUE               ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_GLOBAL_0_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_GLOBAL_1_VALUE               ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_GLOBAL_2_VALUE               ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_GLOBAL_3_VALUE               ( 0x3 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OFFSET ( 0x00000040 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWSETS_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWSETS_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWSETS_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWSETS_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWSETS_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWSETS_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWSETS_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWSETS_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWSETS_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWSETS_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWSETS_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWSETS_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWSETS_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWSETS_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2        	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_override */
+	uint32_t override1 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_number */
+	uint32_t ihclass1  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_packet_size_select_1 */
+	uint32_t maxpktsel1	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_packet_size_select_1 */
+	uint32_t minpktsel1	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1        	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_override */
+	uint32_t override0 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_number */
+	uint32_t ihclass0  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_packet_size_select_0 */
+	uint32_t maxpktsel0	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_packet_size_select_0 */
+	uint32_t minpktsel0	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS ;
+#else
+typedef struct
+{	uint32_t minpktsel0	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_packet_size_select_0 */
+	uint32_t maxpktsel0	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_packet_size_select_0 */
+	uint32_t ihclass0  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_number */
+	uint32_t override0 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_override */
+	uint32_t r1        	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t minpktsel1	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_packet_size_select_1 */
+	uint32_t maxpktsel1	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_packet_size_select_1 */
+	uint32_t ihclass1  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_number */
+	uint32_t override1 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_override */
+	uint32_t r2        	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS ;
+#endif
+
+/*****************************************************************************************/
+/* IH_class_select_0                                                                     */
+/* The DS has 256 flows. There are 4 configuration which are per flow:  1. IH class numb */
+/* er (4 bits)   2. IH class override enable (1 bit)  3. Minimum packet size (2 bits).   */
+/* 4. Maximum packet size (2 bits).    Flows 0-31 will have full options 9 bit configura */
+/* tions.  Flows 32-X will have set 0 configuration (9 global bits).  Flows (X+1)-255 wi */
+/* ll have set 1 configurations (additional 9 global bits).  X is configurable.    For E */
+/* thernet – flow 0 should be configured.    This register defines the IH class for flow */
+/*  0-7.                                                                                 */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_IHCLASS_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_IHCLASS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_OFFSET ( 0x00000044 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS0_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS0_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS0_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS0_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS0_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS0_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS0_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS0_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS0_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS0_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS0_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS0_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS0_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS0_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_class */
+	uint32_t ihclass	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHCLASS0 ;
+#else
+typedef struct
+{	uint32_t ihclass	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHCLASS0 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_class_select_1                                                                     */
+/* The DS has 256 flows. There are 4 configuration which are per flow:  1. IH class numb */
+/* er (4 bits)   2. IH class override enable (1 bit)  3. Minimum packet size (2 bits).   */
+/* 4. Maximum packet size (2 bits).    Flows 0-31 will have full options 9 bit configura */
+/* tions.  Flows 32-X will have set 0 configuration (9 global bits).  Flows (X+1)-255 wi */
+/* ll have set 1 configurations (additional 9 global bits).  X is configurable.    For E */
+/* thernet – flow 0 should be configured.    This register defines the IH class for flow */
+/*  8-15.                                                                                */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_IHCLASS_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_IHCLASS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_OFFSET ( 0x00000048 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS1_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS1_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS1_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS1_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS1_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS1_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS1_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS1_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS1_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS1_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS1_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS1_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS1_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS1_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_class */
+	uint32_t ihclass	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHCLASS1 ;
+#else
+typedef struct
+{	uint32_t ihclass	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHCLASS1 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_class_select_2                                                                     */
+/* The DS has 256 flows. There are 4 configuration which are per flow:  1. IH class numb */
+/* er (4 bits)   2. IH class override enable (1 bit)  3. Minimum packet size (2 bits).   */
+/* 4. Maximum packet size (2 bits).    Flows 0-31 will have full options 9 bit configura */
+/* tions.  Flows 32-X will have set 0 configuration (9 global bits).  Flows (X+1)-255 wi */
+/* ll have set 1 configurations (additional 9 global bits).  X is configurable.    For E */
+/* thernet – flow 0 should be configured.    This register defines the IH class for flow */
+/*  16-23.                                                                               */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_IHCLASS_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_IHCLASS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_OFFSET ( 0x0000004C )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS2_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS2_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS2_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS2_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS2_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS2_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS2_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS2_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS2_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS2_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS2_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS2_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS2_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS2_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_class */
+	uint32_t ihclass	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHCLASS2 ;
+#else
+typedef struct
+{	uint32_t ihclass	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHCLASS2 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_class_select_3                                                                     */
+/* The DS has 256 flows. There are 4 configuration which are per flow:  1. IH class numb */
+/* er (4 bits)   2. IH class override enable (1 bit)  3. Minimum packet size (2 bits).   */
+/* 4. Maximum packet size (2 bits).    Flows 0-31 will have full options 9 bit configura */
+/* tions.  Flows 32-X will have set 0 configuration (9 global bits).  Flows (X+1)-255 wi */
+/* ll have set 1 configurations (additional 9 global bits).  X is configurable.    For E */
+/* thernet – flow 0 should be configured.    This register defines the IH class for flow */
+/*  24-31.                                                                               */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_IHCLASS_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_IHCLASS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_OFFSET ( 0x00000050 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS3_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS3_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS3_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS3_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS3_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS3_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS3_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS3_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS3_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS3_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS3_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS3_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS3_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS3_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_class */
+	uint32_t ihclass	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHCLASS3 ;
+#else
+typedef struct
+{	uint32_t ihclass	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHCLASS3 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_class_override                                                                     */
+/* The DS has 256 flows. There are 4 configuration which are per flow:  1. IH class numb */
+/* er (4 bits)   2. IH class override enable (1 bit)  3. Minimum packet size (2 bits).   */
+/* 4. Maximum packet size (2 bits).    Flows 0-31 will have full options 9 bit configura */
+/* tions.  Flows 32-X will have set 0 configuration (9 global bits).  Flows (X+1)-255 wi */
+/* ll have set 1 configurations (additional 9 global bits).  X is configurable.    For E */
+/* thernet – flow 0 should be configured.    This register defines the IH class select o */
+/* verride for flow 0-31.                                                                */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_IHOVERRIDE_NO_OVERRIDE_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_IHOVERRIDE_NO_OVERRIDE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_IHOVERRIDE_OVERRIDE_VALUE                ( 0x1 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_OFFSET ( 0x00000054 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHOVERRIDE_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_IHOVERRIDE_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHOVERRIDE_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_IHOVERRIDE_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHOVERRIDE_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_IHOVERRIDE_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHOVERRIDE_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_IHOVERRIDE_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHOVERRIDE_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_IHOVERRIDE_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHOVERRIDE_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_IHOVERRIDE_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHOVERRIDE_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_IHOVERRIDE_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_class_override */
+	uint32_t ihoverride	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE ;
+#else
+typedef struct
+{	uint32_t ihoverride	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_override */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE ;
+#endif
+
+/*****************************************************************************************/
+/* Minimum_packet_select_0                                                               */
+/* The DS has 256 flows. There are 4 configuration which are per flow:  1. IH class numb */
+/* er (4 bits)   2. IH class override enable (1 bit)  3. Minimum packet size (2 bits).   */
+/* 4. Maximum packet size (2 bits).    Flows 0-31 will have full options 9 bit configura */
+/* tions.  Flows 32-X will have set 0 configuration (9 global bits).  Flows (X+1)-255 wi */
+/* ll have set 1 configurations (additional 9 global bits).  X is configurable.    For E */
+/* thernet – flow 0 should be configured.    This register defines the minimum packet si */
+/* ze select for flow 0-15.                                                              */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_GLOBAL_0_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_GLOBAL_0_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_GLOBAL_1_VALUE             ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_GLOBAL_2_VALUE             ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_GLOBAL_3_VALUE             ( 0x3 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_OFFSET ( 0x00000058 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Mimimum_packet_size_select */
+	uint32_t minpktsel	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0 ;
+#else
+typedef struct
+{	uint32_t minpktsel	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Mimimum_packet_size_select */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0 ;
+#endif
+
+/*****************************************************************************************/
+/* Minimum_packet_select_1                                                               */
+/* The DS has 256 flows. There are 4 configuration which are per flow:  1. IH class numb */
+/* er (4 bits)   2. IH class override enable (1 bit)  3. Minimum packet size (2 bits).   */
+/* 4. Maximum packet size (2 bits).    Flows 0-31 will have full options 9 bit configura */
+/* tions.  Flows 32-X will have set 0 configuration (9 global bits).  Flows (X+1)-255 wi */
+/* ll have set 1 configurations (additional 9 global bits).  X is configurable.    For E */
+/* thernet – flow 0 should be configured.    This register defines the minimum packet si */
+/* ze select for flow 16-31.                                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_GLOBAL_0_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_GLOBAL_0_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_GLOBAL_1_VALUE             ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_GLOBAL_2_VALUE             ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_GLOBAL_3_VALUE             ( 0x3 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_OFFSET ( 0x0000005C )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Mimimum_packet_size_select */
+	uint32_t minpktsel	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1 ;
+#else
+typedef struct
+{	uint32_t minpktsel	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Mimimum_packet_size_select */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1 ;
+#endif
+
+/*****************************************************************************************/
+/* Maximum_packet_select_0                                                               */
+/* The DS has 256 flows. There are 4 configuration which are per flow:  1. IH class numb */
+/* er (4 bits)   2. IH class override enable (1 bit)  3. Minimum packet size (2 bits).   */
+/* 4. Maximum packet size (2 bits).    Flows 0-31 will have full options 9 bit configura */
+/* tions.  Flows 32-X will have set 0 configuration (9 global bits).  Flows (X+1)-255 wi */
+/* ll have set 1 configurations (additional 9 global bits).  X is configurable.    For E */
+/* thernet – flow 0 should be configured.    This register defines the maximum packet si */
+/* ze select for flow 0-15.                                                              */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_GLOBAL_0_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_GLOBAL_0_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_GLOBAL_1_VALUE             ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_GLOBAL_2_VALUE             ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_GLOBAL_3_VALUE             ( 0x3 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_OFFSET ( 0x00000060 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Maximum_packet_size_select */
+	uint32_t maxpktsel	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0 ;
+#else
+typedef struct
+{	uint32_t maxpktsel	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_packet_size_select */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0 ;
+#endif
+
+/*****************************************************************************************/
+/* Maximum_packet_select_1                                                               */
+/* The DS has 256 flows. There are 4 configuration which are per flow:  1. IH class numb */
+/* er (4 bits)   2. IH class override enable (1 bit)  3. Minimum packet size (2 bits).   */
+/* 4. Maximum packet size (2 bits).    Flows 0-31 will have full options 9 bit configura */
+/* tions.  Flows 32-X will have set 0 configuration (9 global bits).  Flows (X+1)-255 wi */
+/* ll have set 1 configurations (additional 9 global bits).  X is configurable.    For E */
+/* thernet – flow 0 should be configured.    This register defines the maximum packet si */
+/* ze select for flow 16-31.                                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_GLOBAL_0_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_GLOBAL_0_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_GLOBAL_1_VALUE             ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_GLOBAL_2_VALUE             ( 0x2 )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_GLOBAL_3_VALUE             ( 0x3 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_OFFSET ( 0x00000064 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Maximum_packet_size_select */
+	uint32_t maxpktsel	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1 ;
+#else
+typedef struct
+{	uint32_t maxpktsel	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_packet_size_select */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1 ;
+#endif
+
+/*****************************************************************************************/
+/* PLOAM_configurations                                                                  */
+/* PLOAM has the following 2 configuration:  1. IH class number (4 bits)   2. IH class o */
+/* verride enable (1 bit)                                                                */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_R1_DEFAULT_VALUE                         ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_R1_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_IHOVERRIDE_NO_OVERRIDE_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_IHOVERRIDE_NO_OVERRIDE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_IHOVERRIDE_OVERRIDE_VALUE                ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_IHCLASS_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_IHCLASS_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_OFFSET ( 0x00000068 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_PLOAMCFG_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_PLOAMCFG_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_PLOAMCFG_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_PLOAMCFG_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_PLOAMCFG_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_PLOAMCFG_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_PLOAMCFG_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_PLOAMCFG_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_PLOAMCFG_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_PLOAMCFG_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_PLOAMCFG_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_PLOAMCFG_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_PLOAMCFG_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_PLOAMCFG_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1        	: 27 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PLOAM_IH_override */
+	uint32_t ihoverride	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PLOAM_IH_class */
+	uint32_t ihclass   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG ;
+#else
+typedef struct
+{	uint32_t ihclass   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PLOAM_IH_class */
+	uint32_t ihoverride	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PLOAM_IH_override */
+	uint32_t r1        	: 27 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG ;
+#endif
+
+/*****************************************************************************************/
+/* RX_reset_command                                                                      */
+/* This register enable reset of internal units (for WA perposes).                       */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_R_DEFAULT_VALUE                                   ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_R_DEFAULT_VALUE_RESET_VALUE                       ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RNRRST_RESET_IS_NOT_ACTIVE_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RNRRST_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RNRRST_RESET_IS_ACTIVE_VALUE                      ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SDMARST_RESET_IS_NOT_ACTIVE_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SDMARST_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SDMARST_RESET_IS_ACTIVE_VALUE                     ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_DMARST_RESET_IS_NOT_ACTIVE_VALUE                  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_DMARST_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_DMARST_RESET_IS_ACTIVE_VALUE                      ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CNTXTRST_RESET_IS_NOT_ACTIVE_VALUE                ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CNTXTRST_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CNTXTRST_RESET_IS_ACTIVE_VALUE                    ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_PWUFIFORST_RESET_IS_NOT_ACTIVE_VALUE              ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_PWUFIFORST_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_PWUFIFORST_RESET_IS_ACTIVE_VALUE                  ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RESFIFORST_RESET_IS_NOT_ACTIVE_VALUE              ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RESFIFORST_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RESFIFORST_RESET_IS_ACTIVE_VALUE                  ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SBPMFIFORST_RESET_IS_NOT_ACTIVE_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SBPMFIFORST_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SBPMFIFORST_RESET_IS_ACTIVE_VALUE                 ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BPMFIFORST_RESET_IS_NOT_ACTIVE_VALUE              ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BPMFIFORST_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BPMFIFORST_RESET_IS_ACTIVE_VALUE                  ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_REFIFORST_RESET_IS_NOT_ACTIVE_VALUE               ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_REFIFORST_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_REFIFORST_RESET_IS_ACTIVE_VALUE                   ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_IHBUFEN_RESET_IS_NOT_ACTIVE_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_IHBUFEN_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_IHBUFEN_RESET_IS_ACTIVE_VALUE                     ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_IHCNTXT_RESET_IS_NOT_ACTIVE_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_IHCNTXT_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_IHCNTXT_RESET_IS_ACTIVE_VALUE                     ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BURSTBUFRST_RESET_IS_NOT_ACTIVE_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BURSTBUFRST_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BURSTBUFRST_RESET_IS_ACTIVE_VALUE                 ( 0x1 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INBUFRST_RESET_IS_NOT_ACTIVE_VALUE                ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INBUFRST_RESET_IS_NOT_ACTIVE_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INBUFRST_RESET_IS_ACTIVE_VALUE                    ( 0x1 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_OFFSET ( 0x0000006C )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_RXRSTRST_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_RXRSTRST_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_RXRSTRST_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_RXRSTRST_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_RXRSTRST_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_RXRSTRST_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_RXRSTRST_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_RXRSTRST_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_RXRSTRST_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_RXRSTRST_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_RXRSTRST_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_RXRSTRST_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_RXRSTRST_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_RXRSTRST_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r          	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_write_pointer_reset_command */
+	uint32_t rnrrst     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA_write_pointer_reset_command */
+	uint32_t sdmarst    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_write_pointer_reset_command */
+	uint32_t dmarst     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_reset_command */
+	uint32_t cntxtrst   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pre_wakeup_FIFO_reset_command */
+	uint32_t pwufiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Response_FIFO_reset_command */
+	uint32_t resfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_FIFO_reset_command */
+	uint32_t sbpmfiforst	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_FIFO_reset_command */
+	uint32_t bpmfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reassembly_FIFO_reset_command */
+	uint32_t refiforst  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_buf_en_reset_command */
+	uint32_t ihbufen    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_context_reset_command */
+	uint32_t ihcntxt    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Burst_buf_reset_command */
+	uint32_t burstbufrst	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Input_buf_reset_command */
+	uint32_t inbufrst   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_RXRSTRST ;
+#else
+typedef struct
+{	uint32_t inbufrst   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Input_buf_reset_command */
+	uint32_t burstbufrst	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Burst_buf_reset_command */
+	uint32_t ihcntxt    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_context_reset_command */
+	uint32_t ihbufen    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_buf_en_reset_command */
+	uint32_t refiforst  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reassembly_FIFO_reset_command */
+	uint32_t bpmfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_FIFO_reset_command */
+	uint32_t sbpmfiforst	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_FIFO_reset_command */
+	uint32_t resfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Response_FIFO_reset_command */
+	uint32_t pwufiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pre_wakeup_FIFO_reset_command */
+	uint32_t cntxtrst   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_reset_command */
+	uint32_t dmarst     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_write_pointer_reset_command */
+	uint32_t sdmarst    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA_write_pointer_reset_command */
+	uint32_t rnrrst     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_write_pointer_reset_command */
+	uint32_t r          	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_RXRSTRST ;
+#endif
+
+/*****************************************************************************************/
+/* RX_debug_select                                                                       */
+/* Selects one out of 10 possible debug vectors                                          */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_R1_RESET_VALUE_VALUE                   ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_R1_RESET_VALUE_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RXDBGSEL_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RXDBGSEL_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_OFFSET ( 0x00000070 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_RXDBGSEL_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_RXDBGSEL_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_RXDBGSEL_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_RXDBGSEL_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_RXDBGSEL_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_RXDBGSEL_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_RXDBGSEL_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_RXDBGSEL_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_RXDBGSEL_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_RXDBGSEL_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_RXDBGSEL_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_RXDBGSEL_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_RXDBGSEL_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_RXDBGSEL_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1      	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RX_debug_select */
+	uint32_t rxdbgsel	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL ;
+#else
+typedef struct
+{	uint32_t rxdbgsel	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RX_debug_select */
+	uint32_t r1      	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL ;
+#endif
+
+/*****************************************************************************************/
+/* Reassembly_offset                                                                     */
+/* The BBH writes the packets header into the IH. If the rest of the packet is written i */
+/* nto the DDR, then the address is according to the reassembly offset configurations (t */
+/* his configuration is in 8-bytes resolutions):  128 + 8 * <reassembly_offset>          */
+/*****************************************************************************************/
+
+#define BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_R1_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_R1_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET_MAX_VALUE_VALUE           ( 0x32 )
+
+
+#define BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET ( 0x00000074 )
+
+#define BBH_RX_0_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS   	( BBH_RX_0_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET )
+#define BBH_RX_0_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_READ( r ) 	READ_32( ( BBH_RX_0_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (r) )
+#define BBH_RX_0_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_WRITE( v )	WRITE_32( ( BBH_RX_0_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (v) )
+
+#define BBH_RX_1_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS   	( BBH_RX_1_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET )
+#define BBH_RX_1_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_READ( r ) 	READ_32( ( BBH_RX_1_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (r) )
+#define BBH_RX_1_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_WRITE( v )	WRITE_32( ( BBH_RX_1_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (v) )
+
+#define BBH_RX_2_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS   	( BBH_RX_2_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET )
+#define BBH_RX_2_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_READ( r ) 	READ_32( ( BBH_RX_2_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (r) )
+#define BBH_RX_2_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_WRITE( v )	WRITE_32( ( BBH_RX_2_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (v) )
+
+#define BBH_RX_3_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS   	( BBH_RX_3_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET )
+#define BBH_RX_3_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_READ( r ) 	READ_32( ( BBH_RX_3_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (r) )
+#define BBH_RX_3_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_WRITE( v )	WRITE_32( ( BBH_RX_3_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (v) )
+
+#define BBH_RX_4_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS   	( BBH_RX_4_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET )
+#define BBH_RX_4_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_READ( r ) 	READ_32( ( BBH_RX_4_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (r) )
+#define BBH_RX_4_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_WRITE( v )	WRITE_32( ( BBH_RX_4_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (v) )
+
+#define BBH_RX_5_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS   	( BBH_RX_5_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET )
+#define BBH_RX_5_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_READ( r ) 	READ_32( ( BBH_RX_5_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (r) )
+#define BBH_RX_5_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_WRITE( v )	WRITE_32( ( BBH_RX_5_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (v) )
+
+#define BBH_RX_6_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS   	( BBH_RX_6_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET )
+#define BBH_RX_6_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_READ( r ) 	READ_32( ( BBH_RX_6_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (r) )
+#define BBH_RX_6_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_WRITE( v )	WRITE_32( ( BBH_RX_6_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ARRAY [ ] ;
+
+#define BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_WRITE( i, v )	WRITE_32( BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ARRAY [ i ], (v) )
+#define BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_READ( i, r ) 	READ_32( BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1    	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reassemly_offset */
+	uint32_t offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET ;
+#else
+typedef struct
+{	uint32_t offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reassemly_offset */
+	uint32_t r1    	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET ;
+#endif
+
+/*****************************************************************************************/
+/* SOP_after_SOP_error                                                                   */
+/* This counter counts the packets drop due to SOP after SOP error.  This counter is cle */
+/* ared when read and freezes when reaches the maximum value.                            */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_SOPASOP_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_SOPASOP_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_SOPASOP_OFFSET ( 0x00000000 )
+
+#define BBH_RX_0_PM_COUNTERS_SOPASOP_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_SOPASOP_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_SOPASOP_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_SOPASOP_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_SOPASOP_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_SOPASOP_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_SOPASOP_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_SOPASOP_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_SOPASOP_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_SOPASOP_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_SOPASOP_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_SOPASOP_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_SOPASOP_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_SOPASOP_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_SOPASOP_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_SOPASOP_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_SOPASOP_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_SOPASOP_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_SOPASOP_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_SOPASOP_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_SOPASOP_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_SOPASOP_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_SOPASOP_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_SOPASOP_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_SOPASOP_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_SOPASOP_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_SOPASOP_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_SOPASOP_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_SOPASOP_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_SOPASOP_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_SOPASOP_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_SOPASOP_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_SOPASOP_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_SOPASOP_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_SOPASOP_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_SOPASOP_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_SOPASOP_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_SOPASOP_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_SOPASOP_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_SOPASOP_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_SOPASOP_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_SOPASOP_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_SOPASOP_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_SOPASOP_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_SOPASOP_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_SOPASOP_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_SOPASOP_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_SOPASOP ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_SOPASOP ;
+#endif
+
+/*****************************************************************************************/
+/* Third_flow_error                                                                      */
+/* This counter counts the packets drop due to Third flow error.  This counter is cleare */
+/* d when read and freezes when reaches the maximum value.                               */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_THIRDFLOW_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_THIRDFLOW_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_THIRDFLOW_OFFSET ( 0x00000004 )
+
+#define BBH_RX_0_PM_COUNTERS_THIRDFLOW_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_THIRDFLOW_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_THIRDFLOW_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_THIRDFLOW_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_THIRDFLOW_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_THIRDFLOW_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_THIRDFLOW_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_THIRDFLOW_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_THIRDFLOW_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_THIRDFLOW_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_THIRDFLOW_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_THIRDFLOW_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_THIRDFLOW_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_THIRDFLOW_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_THIRDFLOW_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_THIRDFLOW_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_THIRDFLOW_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_THIRDFLOW_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_THIRDFLOW_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_THIRDFLOW_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_THIRDFLOW_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_THIRDFLOW_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_THIRDFLOW_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_THIRDFLOW_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_THIRDFLOW_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_THIRDFLOW_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_THIRDFLOW_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_THIRDFLOW_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_THIRDFLOW_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_THIRDFLOW_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_THIRDFLOW_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_THIRDFLOW_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_THIRDFLOW_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_THIRDFLOW_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_THIRDFLOW_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_THIRDFLOW_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_THIRDFLOW_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_THIRDFLOW_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_THIRDFLOW_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_THIRDFLOW_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_THIRDFLOW_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_THIRDFLOW_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_THIRDFLOW_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_THIRDFLOW_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_THIRDFLOW_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_THIRDFLOW_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_THIRDFLOW_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_THIRDFLOW ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_THIRDFLOW ;
+#endif
+
+/*****************************************************************************************/
+/* Incoming_packets                                                                      */
+/* This counter counts the number of incoming good packets.  It counts the packets from  */
+/* all flows together.  This counter is cleared when read and freezes when reaches the m */
+/* aximum value.                                                                         */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_INPKT_INPKT_GOOD_PACKETS_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_INPKT_INPKT_GOOD_PACKETS_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_INPKT_OFFSET ( 0x00000008 )
+
+#define BBH_RX_0_PM_COUNTERS_INPKT_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_INPKT_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_INPKT_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_INPKT_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_INPKT_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_INPKT_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_INPKT_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_INPKT_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_INPKT_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_INPKT_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_INPKT_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_INPKT_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_INPKT_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_INPKT_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_INPKT_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_INPKT_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_INPKT_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_INPKT_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_INPKT_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_INPKT_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_INPKT_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_INPKT_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_INPKT_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_INPKT_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_INPKT_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_INPKT_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_INPKT_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_INPKT_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_INPKT_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_INPKT_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_INPKT_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_INPKT_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_INPKT_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_INPKT_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_INPKT_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_INPKT_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_INPKT_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_INPKT_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_INPKT_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_INPKT_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_INPKT_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_INPKT_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_INPKT_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_INPKT_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_INPKT_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_INPKT_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_INPKT_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Incoming_packets */
+	uint32_t inpkt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_INPKT ;
+#else
+typedef struct
+{	uint32_t inpkt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Incoming_packets */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_INPKT ;
+#endif
+
+/*****************************************************************************************/
+/* Too_short_error                                                                       */
+/* This counter counts the packets drop due to Too short error.  This counter is cleared */
+/*  when read and freezes when reaches the maximum value.                                */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_TOOSHORT_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_TOOSHORT_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_TOOSHORT_OFFSET ( 0x0000000C )
+
+#define BBH_RX_0_PM_COUNTERS_TOOSHORT_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOSHORT_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_TOOSHORT_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_TOOSHORT_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_TOOSHORT_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_TOOSHORT_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_TOOSHORT_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOSHORT_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_TOOSHORT_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_TOOSHORT_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_TOOSHORT_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_TOOSHORT_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_TOOSHORT_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOSHORT_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_TOOSHORT_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_TOOSHORT_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_TOOSHORT_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_TOOSHORT_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_TOOSHORT_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOSHORT_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_TOOSHORT_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_TOOSHORT_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_TOOSHORT_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_TOOSHORT_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_TOOSHORT_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOSHORT_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_TOOSHORT_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_TOOSHORT_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_TOOSHORT_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_TOOSHORT_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_TOOSHORT_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOSHORT_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_TOOSHORT_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_TOOSHORT_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_TOOSHORT_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_TOOSHORT_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_TOOSHORT_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOSHORT_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_TOOSHORT_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_TOOSHORT_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_TOOSHORT_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_TOOSHORT_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_TOOSHORT_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_TOOSHORT_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_TOOSHORT_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_TOOSHORT_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_TOOSHORT_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_TOOSHORT ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_TOOSHORT ;
+#endif
+
+/*****************************************************************************************/
+/* Too_long_error                                                                        */
+/* This counter counts the packets drop due to Too long error.  This counter is cleared  */
+/* when read and freezes when reaches the maximum value.                                 */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_TOOLONG_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_TOOLONG_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_TOOLONG_OFFSET ( 0x00000010 )
+
+#define BBH_RX_0_PM_COUNTERS_TOOLONG_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOLONG_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_TOOLONG_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_TOOLONG_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_TOOLONG_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_TOOLONG_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_TOOLONG_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOLONG_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_TOOLONG_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_TOOLONG_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_TOOLONG_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_TOOLONG_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_TOOLONG_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOLONG_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_TOOLONG_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_TOOLONG_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_TOOLONG_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_TOOLONG_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_TOOLONG_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOLONG_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_TOOLONG_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_TOOLONG_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_TOOLONG_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_TOOLONG_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_TOOLONG_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOLONG_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_TOOLONG_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_TOOLONG_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_TOOLONG_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_TOOLONG_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_TOOLONG_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOLONG_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_TOOLONG_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_TOOLONG_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_TOOLONG_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_TOOLONG_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_TOOLONG_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOLONG_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_TOOLONG_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_TOOLONG_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_TOOLONG_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_TOOLONG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_TOOLONG_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_TOOLONG_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_TOOLONG_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_TOOLONG_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_TOOLONG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_TOOLONG ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_TOOLONG ;
+#endif
+
+/*****************************************************************************************/
+/* CRC_error                                                                             */
+/* This counter counts the packets drop due to CRC error.  This counter is cleared when  */
+/* read and freezes when reaches the maximum value.                                      */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_CRCERROR_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_CRCERROR_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_CRCERROR_OFFSET ( 0x00000014 )
+
+#define BBH_RX_0_PM_COUNTERS_CRCERROR_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERROR_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_CRCERROR_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_CRCERROR_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_CRCERROR_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_CRCERROR_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_CRCERROR_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERROR_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_CRCERROR_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_CRCERROR_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_CRCERROR_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_CRCERROR_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_CRCERROR_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERROR_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_CRCERROR_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_CRCERROR_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_CRCERROR_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_CRCERROR_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_CRCERROR_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERROR_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_CRCERROR_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_CRCERROR_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_CRCERROR_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_CRCERROR_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_CRCERROR_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERROR_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_CRCERROR_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_CRCERROR_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_CRCERROR_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_CRCERROR_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_CRCERROR_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERROR_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_CRCERROR_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_CRCERROR_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_CRCERROR_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_CRCERROR_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_CRCERROR_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERROR_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_CRCERROR_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_CRCERROR_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_CRCERROR_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_CRCERROR_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_CRCERROR_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_CRCERROR_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_CRCERROR_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_CRCERROR_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_CRCERROR_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_CRCERROR ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_CRCERROR ;
+#endif
+
+/*****************************************************************************************/
+/* IPTV_error                                                                            */
+/* This counter counts the packets drop due to IPTV error.  This counter is cleared when */
+/*  read and freezes when reaches the maximum value.                                     */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_IPTV_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_IPTV_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_IPTV_OFFSET ( 0x00000018 )
+
+#define BBH_RX_0_PM_COUNTERS_IPTV_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IPTV_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_IPTV_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_IPTV_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_IPTV_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_IPTV_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_IPTV_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IPTV_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_IPTV_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_IPTV_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_IPTV_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_IPTV_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_IPTV_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IPTV_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_IPTV_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_IPTV_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_IPTV_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_IPTV_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_IPTV_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IPTV_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_IPTV_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_IPTV_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_IPTV_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_IPTV_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_IPTV_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IPTV_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_IPTV_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_IPTV_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_IPTV_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_IPTV_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_IPTV_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IPTV_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_IPTV_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_IPTV_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_IPTV_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_IPTV_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_IPTV_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IPTV_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_IPTV_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_IPTV_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_IPTV_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_IPTV_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_IPTV_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_IPTV_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_IPTV_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_IPTV_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_IPTV_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_IPTV ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_IPTV ;
+#endif
+
+/*****************************************************************************************/
+/* Runner_congestion_error                                                               */
+/* This counter counts the packets drop due to Runner congestion error.  This counter is */
+/*  cleared when read and freezes when reaches the maximum value.                        */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_RUNNERCONG_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_RUNNERCONG_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_RUNNERCONG_OFFSET ( 0x0000001C )
+
+#define BBH_RX_0_PM_COUNTERS_RUNNERCONG_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_RUNNERCONG_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_RUNNERCONG_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_RUNNERCONG_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_RUNNERCONG_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_RUNNERCONG_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_RUNNERCONG_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_RUNNERCONG_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_RUNNERCONG_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_RUNNERCONG_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_RUNNERCONG_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_RUNNERCONG_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_RUNNERCONG_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_RUNNERCONG_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_RUNNERCONG_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_RUNNERCONG_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_RUNNERCONG_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_RUNNERCONG_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_RUNNERCONG_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_RUNNERCONG_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_RUNNERCONG_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_RUNNERCONG_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_RUNNERCONG_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_RUNNERCONG_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_RUNNERCONG_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_RUNNERCONG_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_RUNNERCONG_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_RUNNERCONG_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_RUNNERCONG_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_RUNNERCONG_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_RUNNERCONG_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_RUNNERCONG_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_RUNNERCONG_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_RUNNERCONG_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_RUNNERCONG_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_RUNNERCONG_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_RUNNERCONG_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_RUNNERCONG_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_RUNNERCONG_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_RUNNERCONG_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_RUNNERCONG_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_RUNNERCONG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_RUNNERCONG_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_RUNNERCONG_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_RUNNERCONG_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_RUNNERCONG_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_RUNNERCONG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_RUNNERCONG ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_RUNNERCONG ;
+#endif
+
+/*****************************************************************************************/
+/* No_BPM_BN_error                                                                       */
+/* This counter counts the packets drop due to No BPM BN error.  This counter is cleared */
+/*  when read and freezes when reaches the maximum value.                                */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_NOBPMBN_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_NOBPMBN_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_NOBPMBN_OFFSET ( 0x00000020 )
+
+#define BBH_RX_0_PM_COUNTERS_NOBPMBN_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBN_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_NOBPMBN_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_NOBPMBN_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_NOBPMBN_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_NOBPMBN_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_NOBPMBN_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBN_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_NOBPMBN_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_NOBPMBN_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_NOBPMBN_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_NOBPMBN_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_NOBPMBN_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBN_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_NOBPMBN_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_NOBPMBN_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_NOBPMBN_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_NOBPMBN_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_NOBPMBN_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBN_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_NOBPMBN_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_NOBPMBN_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_NOBPMBN_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_NOBPMBN_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_NOBPMBN_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBN_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_NOBPMBN_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_NOBPMBN_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_NOBPMBN_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_NOBPMBN_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_NOBPMBN_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBN_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_NOBPMBN_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_NOBPMBN_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_NOBPMBN_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_NOBPMBN_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_NOBPMBN_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBN_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_NOBPMBN_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_NOBPMBN_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_NOBPMBN_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_NOBPMBN_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_NOBPMBN_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_NOBPMBN_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_NOBPMBN_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_NOBPMBN_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_NOBPMBN_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_NOBPMBN ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_NOBPMBN ;
+#endif
+
+/*****************************************************************************************/
+/* NO_SBPM_SBN_error                                                                     */
+/* This counter counts the packets drop due to NO SBPM SBN error.  This counter is clear */
+/* ed when read and freezes when reaches the maximum value.                              */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_NOSBPMSBN_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_NOSBPMSBN_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_NOSBPMSBN_OFFSET ( 0x00000024 )
+
+#define BBH_RX_0_PM_COUNTERS_NOSBPMSBN_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSBPMSBN_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_NOSBPMSBN_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_NOSBPMSBN_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_NOSBPMSBN_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSBPMSBN_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_NOSBPMSBN_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_NOSBPMSBN_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_NOSBPMSBN_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSBPMSBN_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_NOSBPMSBN_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_NOSBPMSBN_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_NOSBPMSBN_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSBPMSBN_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_NOSBPMSBN_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_NOSBPMSBN_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_NOSBPMSBN_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSBPMSBN_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_NOSBPMSBN_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_NOSBPMSBN_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_NOSBPMSBN_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSBPMSBN_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_NOSBPMSBN_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_NOSBPMSBN_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_NOSBPMSBN_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSBPMSBN_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_NOSBPMSBN_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_NOSBPMSBN_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_NOSBPMSBN_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_NOSBPMSBN_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_NOSBPMSBN_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_NOSBPMSBN_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_NOSBPMSBN_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_NOSBPMSBN ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_NOSBPMSBN ;
+#endif
+
+/*****************************************************************************************/
+/* No_DMA_CD_error                                                                       */
+/* This counter counts the packets drop due to No DMA CD error.  This counter is cleared */
+/*  when read and freezes when reaches the maximum value.                                */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_NODMACD_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_NODMACD_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_NODMACD_OFFSET ( 0x00000028 )
+
+#define BBH_RX_0_PM_COUNTERS_NODMACD_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NODMACD_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_NODMACD_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_NODMACD_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_NODMACD_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_NODMACD_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_NODMACD_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NODMACD_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_NODMACD_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_NODMACD_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_NODMACD_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_NODMACD_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_NODMACD_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NODMACD_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_NODMACD_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_NODMACD_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_NODMACD_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_NODMACD_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_NODMACD_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NODMACD_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_NODMACD_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_NODMACD_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_NODMACD_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_NODMACD_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_NODMACD_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NODMACD_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_NODMACD_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_NODMACD_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_NODMACD_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_NODMACD_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_NODMACD_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NODMACD_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_NODMACD_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_NODMACD_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_NODMACD_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_NODMACD_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_NODMACD_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NODMACD_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_NODMACD_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_NODMACD_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_NODMACD_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_NODMACD_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_NODMACD_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_NODMACD_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_NODMACD_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_NODMACD_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_NODMACD_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_NODMACD ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_NODMACD ;
+#endif
+
+/*****************************************************************************************/
+/* No_SDMA_CD_error                                                                      */
+/* This counter counts the packets drop due to No SDMA CD error.  This counter is cleare */
+/* d when read and freezes when reaches the maximum value.                               */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_NOSDMACD_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_NOSDMACD_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_NOSDMACD_OFFSET ( 0x0000002C )
+
+#define BBH_RX_0_PM_COUNTERS_NOSDMACD_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSDMACD_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_NOSDMACD_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_NOSDMACD_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_NOSDMACD_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_NOSDMACD_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_NOSDMACD_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSDMACD_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_NOSDMACD_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_NOSDMACD_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_NOSDMACD_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_NOSDMACD_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_NOSDMACD_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSDMACD_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_NOSDMACD_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_NOSDMACD_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_NOSDMACD_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_NOSDMACD_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_NOSDMACD_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSDMACD_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_NOSDMACD_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_NOSDMACD_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_NOSDMACD_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_NOSDMACD_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_NOSDMACD_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSDMACD_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_NOSDMACD_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_NOSDMACD_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_NOSDMACD_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_NOSDMACD_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_NOSDMACD_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSDMACD_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_NOSDMACD_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_NOSDMACD_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_NOSDMACD_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_NOSDMACD_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_NOSDMACD_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSDMACD_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_NOSDMACD_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_NOSDMACD_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_NOSDMACD_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_NOSDMACD_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_NOSDMACD_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_NOSDMACD_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_NOSDMACD_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_NOSDMACD_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_NOSDMACD_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_NOSDMACD ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_NOSDMACD ;
+#endif
+
+/*****************************************************************************************/
+/* IH_drop_ploam_error                                                                   */
+/* This counter counts the PLOAMs drop due to Runner congestion or IPTV errors.  This co */
+/* unter is cleared when read and freezes when reaches the maximum value.                */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_IHDROPPLOAM_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_IHDROPPLOAM_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_IHDROPPLOAM_OFFSET ( 0x00000030 )
+
+#define BBH_RX_0_PM_COUNTERS_IHDROPPLOAM_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IHDROPPLOAM_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_IHDROPPLOAM_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_IHDROPPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_IHDROPPLOAM_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IHDROPPLOAM_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_IHDROPPLOAM_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_IHDROPPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_IHDROPPLOAM_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IHDROPPLOAM_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_IHDROPPLOAM_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_IHDROPPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_IHDROPPLOAM_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IHDROPPLOAM_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_IHDROPPLOAM_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_IHDROPPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_IHDROPPLOAM_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IHDROPPLOAM_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_IHDROPPLOAM_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_IHDROPPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_IHDROPPLOAM_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IHDROPPLOAM_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_IHDROPPLOAM_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_IHDROPPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_IHDROPPLOAM_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IHDROPPLOAM_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_IHDROPPLOAM_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_IHDROPPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_IHDROPPLOAM_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_IHDROPPLOAM_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_IHDROPPLOAM_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_IHDROPPLOAM_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_IHDROPPLOAM_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_IHDROPPLOAM ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_IHDROPPLOAM ;
+#endif
+
+/*****************************************************************************************/
+/* No_BPM_BN_PLOAM_error                                                                 */
+/* This counter counts the PLOAMs drop due to No BPM BN error.  This counter is cleared  */
+/* when read and freezes when reaches the maximum value.                                 */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_OFFSET ( 0x00000034 )
+
+#define BBH_RX_0_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_NOBPMBNPLOAM_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_NOBPMBNPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_NOBPMBNPLOAM_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_NOBPMBNPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_NOBPMBNPLOAM_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_NOBPMBNPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_NOBPMBNPLOAM_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_NOBPMBNPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_NOBPMBNPLOAM_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_NOBPMBNPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_NOBPMBNPLOAM_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_NOBPMBNPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_NOBPMBNPLOAM_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_NOBPMBNPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_NOBPMBNPLOAM ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_NOBPMBNPLOAM ;
+#endif
+
+/*****************************************************************************************/
+/* CRC_PLOAM_error                                                                       */
+/* This counter counts the PLOAMs drop due to CRC error.  This counter is cleared when r */
+/* ead and freezes when reaches the maximum value.                                       */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_OFFSET ( 0x00000038 )
+
+#define BBH_RX_0_PM_COUNTERS_CRCERRORPLOAM_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERRORPLOAM_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_CRCERRORPLOAM_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_CRCERRORPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_CRCERRORPLOAM_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERRORPLOAM_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_CRCERRORPLOAM_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_CRCERRORPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_CRCERRORPLOAM_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERRORPLOAM_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_CRCERRORPLOAM_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_CRCERRORPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_CRCERRORPLOAM_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERRORPLOAM_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_CRCERRORPLOAM_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_CRCERRORPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_CRCERRORPLOAM_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERRORPLOAM_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_CRCERRORPLOAM_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_CRCERRORPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_CRCERRORPLOAM_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERRORPLOAM_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_CRCERRORPLOAM_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_CRCERRORPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_CRCERRORPLOAM_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERRORPLOAM_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_CRCERRORPLOAM_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_CRCERRORPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_CRCERRORPLOAM_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_CRCERRORPLOAM_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_CRCERRORPLOAM_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_CRCERRORPLOAM ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_CRCERRORPLOAM ;
+#endif
+
+/*****************************************************************************************/
+/* Epon_sync_fifo_overrun                                                                */
+/* This counter counts the events of EPON sync FIFO overrun.  This counter is cleared wh */
+/* en read and freezes when reaches the maximum value.                                   */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_EPNFIFOVERUN_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_EPNFIFOVERUN_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_EPNFIFOVERUN_OFFSET ( 0x0000003C )
+
+#define BBH_RX_0_PM_COUNTERS_EPNFIFOVERUN_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVERUN_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_EPNFIFOVERUN_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_EPNFIFOVERUN_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_EPNFIFOVERUN_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVERUN_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_EPNFIFOVERUN_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_EPNFIFOVERUN_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_EPNFIFOVERUN_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVERUN_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_EPNFIFOVERUN_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_EPNFIFOVERUN_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_EPNFIFOVERUN_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVERUN_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_EPNFIFOVERUN_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_EPNFIFOVERUN_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_EPNFIFOVERUN_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVERUN_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_EPNFIFOVERUN_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_EPNFIFOVERUN_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_EPNFIFOVERUN_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVERUN_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_EPNFIFOVERUN_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_EPNFIFOVERUN_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_EPNFIFOVERUN_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVERUN_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_EPNFIFOVERUN_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_EPNFIFOVERUN_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_EPNFIFOVERUN_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_EPNFIFOVERUN_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_EPNFIFOVERUN_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_EPNFIFOVERUN_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_EPNFIFOVERUN_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_EPNFIFOVERUN ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_EPNFIFOVERUN ;
+#endif
+
+/*****************************************************************************************/
+/* Epon_sync_fifo_overrun_hdr                                                            */
+/* This counter counts the events of EPON sync FIFO overrun when header arrives.  This c */
+/* ounter is cleared when read and freezes when reaches the maximum value.               */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_OFFSET ( 0x00000040 )
+
+#define BBH_RX_0_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_EPNFIFOVRNHDR_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_EPNFIFOVRNHDR_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_EPNFIFOVRNHDR_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_EPNFIFOVRNHDR_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_EPNFIFOVRNHDR_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_EPNFIFOVRNHDR_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_EPNFIFOVRNHDR_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_EPNFIFOVRNHDR_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_EPNFIFOVRNHDR_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_EPNFIFOVRNHDR_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_EPNFIFOVRNHDR_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_EPNFIFOVRNHDR_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_EPNFIFOVRNHDR_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_EPNFIFOVRNHDR_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_EPNFIFOVRNHDR_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR ;
+#endif
+
+/*****************************************************************************************/
+/* Epon_type_error                                                                       */
+/* This counter counts the events of EPON type sequence which is wrong, meaning no sop a */
+/* fter header, or sop/header in the middle of packet (before eop).  This counter is cle */
+/* ared when read and freezes when reaches the maximum value.                            */
+/*****************************************************************************************/
+
+#define BBH_RX_PM_COUNTERS_EPONTYPERROR_PMVALUE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PM_COUNTERS_EPONTYPERROR_PMVALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PM_COUNTERS_EPONTYPERROR_OFFSET ( 0x00000044 )
+
+#define BBH_RX_0_PM_COUNTERS_EPONTYPERROR_ADDRESS   	( BBH_RX_0_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPONTYPERROR_OFFSET )
+#define BBH_RX_0_PM_COUNTERS_EPONTYPERROR_READ( r ) 	READ_32( ( BBH_RX_0_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (r) )
+#define BBH_RX_0_PM_COUNTERS_EPONTYPERROR_WRITE( v )	WRITE_32( ( BBH_RX_0_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (v) )
+
+#define BBH_RX_1_PM_COUNTERS_EPONTYPERROR_ADDRESS   	( BBH_RX_1_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPONTYPERROR_OFFSET )
+#define BBH_RX_1_PM_COUNTERS_EPONTYPERROR_READ( r ) 	READ_32( ( BBH_RX_1_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (r) )
+#define BBH_RX_1_PM_COUNTERS_EPONTYPERROR_WRITE( v )	WRITE_32( ( BBH_RX_1_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (v) )
+
+#define BBH_RX_2_PM_COUNTERS_EPONTYPERROR_ADDRESS   	( BBH_RX_2_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPONTYPERROR_OFFSET )
+#define BBH_RX_2_PM_COUNTERS_EPONTYPERROR_READ( r ) 	READ_32( ( BBH_RX_2_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (r) )
+#define BBH_RX_2_PM_COUNTERS_EPONTYPERROR_WRITE( v )	WRITE_32( ( BBH_RX_2_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (v) )
+
+#define BBH_RX_3_PM_COUNTERS_EPONTYPERROR_ADDRESS   	( BBH_RX_3_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPONTYPERROR_OFFSET )
+#define BBH_RX_3_PM_COUNTERS_EPONTYPERROR_READ( r ) 	READ_32( ( BBH_RX_3_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (r) )
+#define BBH_RX_3_PM_COUNTERS_EPONTYPERROR_WRITE( v )	WRITE_32( ( BBH_RX_3_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (v) )
+
+#define BBH_RX_4_PM_COUNTERS_EPONTYPERROR_ADDRESS   	( BBH_RX_4_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPONTYPERROR_OFFSET )
+#define BBH_RX_4_PM_COUNTERS_EPONTYPERROR_READ( r ) 	READ_32( ( BBH_RX_4_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (r) )
+#define BBH_RX_4_PM_COUNTERS_EPONTYPERROR_WRITE( v )	WRITE_32( ( BBH_RX_4_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (v) )
+
+#define BBH_RX_5_PM_COUNTERS_EPONTYPERROR_ADDRESS   	( BBH_RX_5_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPONTYPERROR_OFFSET )
+#define BBH_RX_5_PM_COUNTERS_EPONTYPERROR_READ( r ) 	READ_32( ( BBH_RX_5_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (r) )
+#define BBH_RX_5_PM_COUNTERS_EPONTYPERROR_WRITE( v )	WRITE_32( ( BBH_RX_5_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (v) )
+
+#define BBH_RX_6_PM_COUNTERS_EPONTYPERROR_ADDRESS   	( BBH_RX_6_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPONTYPERROR_OFFSET )
+#define BBH_RX_6_PM_COUNTERS_EPONTYPERROR_READ( r ) 	READ_32( ( BBH_RX_6_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (r) )
+#define BBH_RX_6_PM_COUNTERS_EPONTYPERROR_WRITE( v )	WRITE_32( ( BBH_RX_6_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_PM_COUNTERS_EPONTYPERROR_ARRAY [ ] ;
+
+#define BBH_RX_PM_COUNTERS_EPONTYPERROR_WRITE( i, v )	WRITE_32( BBH_RX_PM_COUNTERS_EPONTYPERROR_ARRAY [ i ], (v) )
+#define BBH_RX_PM_COUNTERS_EPONTYPERROR_READ( i, r ) 	READ_32( BBH_RX_PM_COUNTERS_EPONTYPERROR_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PM_counter_value */
+	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_EPONTYPERROR ;
+#else
+typedef struct
+{	uint32_t pmvalue	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PM_counter_value */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS_EPONTYPERROR ;
+#endif
+
+/*****************************************************************************************/
+/* Context_0_LSB                                                                         */
+/* In the case of GPON peripheral, DS flows may arrive interleaved. The BBH supports par */
+/* allel reassembly of up to two interleaved flows (out of 256). For the reassembly proc */
+/* ess the BBH stores a double flow context.                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_CNTXTX0LSB_R2_DEFAULT_VALUE                            ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0LSB_R2_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0LSB_CUROFFSET_CURRENT_OFFSET_VALUE              ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0LSB_CUROFFSET_CURRENT_OFFSET_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0LSB_FLOWID_FLOW_ID_VALUE                        ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0LSB_FLOWID_FLOW_ID_VALUE_RESET_VALUE            ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0LSB_R1_DEFAULT_VALUE                            ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0LSB_R1_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0LSB_INREASS_NOT_IN_REASSEMBLY_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0LSB_INREASS_NOT_IN_REASSEMBLY_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0LSB_INREASS_IN_REASSEMBLY_VALUE                 ( 0x1 )
+
+
+#define BBH_RX_DEBUG_CNTXTX0LSB_OFFSET ( 0x00000000 )
+
+#define BBH_RX_0_DEBUG_CNTXTX0LSB_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0LSB_OFFSET )
+#define BBH_RX_0_DEBUG_CNTXTX0LSB_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_CNTXTX0LSB_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_CNTXTX0LSB_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_CNTXTX0LSB_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_CNTXTX0LSB_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0LSB_OFFSET )
+#define BBH_RX_1_DEBUG_CNTXTX0LSB_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_CNTXTX0LSB_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_CNTXTX0LSB_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_CNTXTX0LSB_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_CNTXTX0LSB_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0LSB_OFFSET )
+#define BBH_RX_2_DEBUG_CNTXTX0LSB_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_CNTXTX0LSB_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_CNTXTX0LSB_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_CNTXTX0LSB_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_CNTXTX0LSB_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0LSB_OFFSET )
+#define BBH_RX_3_DEBUG_CNTXTX0LSB_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_CNTXTX0LSB_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_CNTXTX0LSB_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_CNTXTX0LSB_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_CNTXTX0LSB_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0LSB_OFFSET )
+#define BBH_RX_4_DEBUG_CNTXTX0LSB_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_CNTXTX0LSB_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_CNTXTX0LSB_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_CNTXTX0LSB_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_CNTXTX0LSB_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0LSB_OFFSET )
+#define BBH_RX_5_DEBUG_CNTXTX0LSB_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_CNTXTX0LSB_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_CNTXTX0LSB_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_CNTXTX0LSB_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_CNTXTX0LSB_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0LSB_OFFSET )
+#define BBH_RX_6_DEBUG_CNTXTX0LSB_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_CNTXTX0LSB_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_CNTXTX0LSB_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_CNTXTX0LSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_CNTXTX0LSB_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_CNTXTX0LSB_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_CNTXTX0LSB_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_CNTXTX0LSB_READ( i, r ) 	READ_32( BBH_RX_DEBUG_CNTXTX0LSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_offset */
+	uint32_t curoffset	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_ID */
+	uint32_t flowid   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_reassembly */
+	uint32_t inreass  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_CNTXTX0LSB ;
+#else
+typedef struct
+{	uint32_t inreass  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_reassembly */
+	uint32_t r1       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t flowid   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_ID */
+	uint32_t curoffset	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_offset */
+	uint32_t r2       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_CNTXTX0LSB ;
+#endif
+
+/*****************************************************************************************/
+/* Context_0_MSB                                                                         */
+/* In the case of GPON peripheral, DS flows may arrive interleaved. The BBH supports par */
+/* allel reassembly of up to two interleaved flows (out of 256). For the reassembly proc */
+/* ess the BBH stores a double flow context.                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_CNTXTX0MSB_R2_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0MSB_R2_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0MSB_FIRSTBN_BN_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0MSB_FIRSTBN_BN_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0MSB_R1_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0MSB_R1_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0MSB_CURBN_BN_VALUE               ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX0MSB_CURBN_BN_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define BBH_RX_DEBUG_CNTXTX0MSB_OFFSET ( 0x00000004 )
+
+#define BBH_RX_0_DEBUG_CNTXTX0MSB_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0MSB_OFFSET )
+#define BBH_RX_0_DEBUG_CNTXTX0MSB_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_CNTXTX0MSB_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_CNTXTX0MSB_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_CNTXTX0MSB_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_CNTXTX0MSB_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0MSB_OFFSET )
+#define BBH_RX_1_DEBUG_CNTXTX0MSB_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_CNTXTX0MSB_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_CNTXTX0MSB_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_CNTXTX0MSB_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_CNTXTX0MSB_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0MSB_OFFSET )
+#define BBH_RX_2_DEBUG_CNTXTX0MSB_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_CNTXTX0MSB_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_CNTXTX0MSB_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_CNTXTX0MSB_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_CNTXTX0MSB_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0MSB_OFFSET )
+#define BBH_RX_3_DEBUG_CNTXTX0MSB_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_CNTXTX0MSB_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_CNTXTX0MSB_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_CNTXTX0MSB_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_CNTXTX0MSB_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0MSB_OFFSET )
+#define BBH_RX_4_DEBUG_CNTXTX0MSB_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_CNTXTX0MSB_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_CNTXTX0MSB_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_CNTXTX0MSB_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_CNTXTX0MSB_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0MSB_OFFSET )
+#define BBH_RX_5_DEBUG_CNTXTX0MSB_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_CNTXTX0MSB_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_CNTXTX0MSB_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_CNTXTX0MSB_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_CNTXTX0MSB_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0MSB_OFFSET )
+#define BBH_RX_6_DEBUG_CNTXTX0MSB_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_CNTXTX0MSB_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_CNTXTX0MSB_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_CNTXTX0MSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_CNTXTX0MSB_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_CNTXTX0MSB_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_CNTXTX0MSB_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_CNTXTX0MSB_READ( i, r ) 	READ_32( BBH_RX_DEBUG_CNTXTX0MSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* First_BN */
+	uint32_t firstbn	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_BN */
+	uint32_t curbn  	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_CNTXTX0MSB ;
+#else
+typedef struct
+{	uint32_t curbn  	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_BN */
+	uint32_t r1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t firstbn	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* First_BN */
+	uint32_t r2     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_CNTXTX0MSB ;
+#endif
+
+/*****************************************************************************************/
+/* Context_1_LSB                                                                         */
+/* In the case of GPON peripheral, DS flows may arrive interleaved. The BBH supports par */
+/* allel reassembly of up to two interleaved flows (out of 256). For the reassembly proc */
+/* ess the BBH stores a double flow context.                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_CNTXTX1LSB_R2_DEFAULT_VALUE                            ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1LSB_R2_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1LSB_CUROFFSET_CURRENT_OFFSET_VALUE              ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1LSB_CUROFFSET_CURRENT_OFFSET_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1LSB_FLOWID_FLOW_ID_VALUE                        ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1LSB_FLOWID_FLOW_ID_VALUE_RESET_VALUE            ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1LSB_R1_DEFAULT_VALUE                            ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1LSB_R1_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1LSB_INREASS_NOT_IN_REASSEMBLY_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1LSB_INREASS_NOT_IN_REASSEMBLY_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1LSB_INREASS_IN_REASSEMBLY_VALUE                 ( 0x1 )
+
+
+#define BBH_RX_DEBUG_CNTXTX1LSB_OFFSET ( 0x00000008 )
+
+#define BBH_RX_0_DEBUG_CNTXTX1LSB_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1LSB_OFFSET )
+#define BBH_RX_0_DEBUG_CNTXTX1LSB_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_CNTXTX1LSB_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_CNTXTX1LSB_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_CNTXTX1LSB_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_CNTXTX1LSB_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1LSB_OFFSET )
+#define BBH_RX_1_DEBUG_CNTXTX1LSB_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_CNTXTX1LSB_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_CNTXTX1LSB_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_CNTXTX1LSB_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_CNTXTX1LSB_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1LSB_OFFSET )
+#define BBH_RX_2_DEBUG_CNTXTX1LSB_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_CNTXTX1LSB_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_CNTXTX1LSB_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_CNTXTX1LSB_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_CNTXTX1LSB_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1LSB_OFFSET )
+#define BBH_RX_3_DEBUG_CNTXTX1LSB_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_CNTXTX1LSB_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_CNTXTX1LSB_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_CNTXTX1LSB_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_CNTXTX1LSB_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1LSB_OFFSET )
+#define BBH_RX_4_DEBUG_CNTXTX1LSB_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_CNTXTX1LSB_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_CNTXTX1LSB_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_CNTXTX1LSB_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_CNTXTX1LSB_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1LSB_OFFSET )
+#define BBH_RX_5_DEBUG_CNTXTX1LSB_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_CNTXTX1LSB_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_CNTXTX1LSB_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_CNTXTX1LSB_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_CNTXTX1LSB_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1LSB_OFFSET )
+#define BBH_RX_6_DEBUG_CNTXTX1LSB_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_CNTXTX1LSB_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_CNTXTX1LSB_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_CNTXTX1LSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_CNTXTX1LSB_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_CNTXTX1LSB_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_CNTXTX1LSB_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_CNTXTX1LSB_READ( i, r ) 	READ_32( BBH_RX_DEBUG_CNTXTX1LSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_offset */
+	uint32_t curoffset	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_ID */
+	uint32_t flowid   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_reassembly */
+	uint32_t inreass  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_CNTXTX1LSB ;
+#else
+typedef struct
+{	uint32_t inreass  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_reassembly */
+	uint32_t r1       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t flowid   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_ID */
+	uint32_t curoffset	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_offset */
+	uint32_t r2       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_CNTXTX1LSB ;
+#endif
+
+/*****************************************************************************************/
+/* Context_1_MSB                                                                         */
+/* In the case of GPON peripheral, DS flows may arrive interleaved. The BBH supports par */
+/* allel reassembly of up to two interleaved flows (out of 256). For the reassembly proc */
+/* ess the BBH stores a double flow context.                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_CNTXTX1MSB_R2_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1MSB_R2_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1MSB_FIRSTBN_BN_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1MSB_FIRSTBN_BN_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1MSB_R1_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1MSB_R1_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1MSB_CURBN_BN_VALUE               ( 0x0 )
+#define BBH_RX_DEBUG_CNTXTX1MSB_CURBN_BN_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define BBH_RX_DEBUG_CNTXTX1MSB_OFFSET ( 0x0000000C )
+
+#define BBH_RX_0_DEBUG_CNTXTX1MSB_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1MSB_OFFSET )
+#define BBH_RX_0_DEBUG_CNTXTX1MSB_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_CNTXTX1MSB_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_CNTXTX1MSB_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_CNTXTX1MSB_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_CNTXTX1MSB_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1MSB_OFFSET )
+#define BBH_RX_1_DEBUG_CNTXTX1MSB_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_CNTXTX1MSB_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_CNTXTX1MSB_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_CNTXTX1MSB_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_CNTXTX1MSB_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1MSB_OFFSET )
+#define BBH_RX_2_DEBUG_CNTXTX1MSB_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_CNTXTX1MSB_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_CNTXTX1MSB_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_CNTXTX1MSB_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_CNTXTX1MSB_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1MSB_OFFSET )
+#define BBH_RX_3_DEBUG_CNTXTX1MSB_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_CNTXTX1MSB_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_CNTXTX1MSB_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_CNTXTX1MSB_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_CNTXTX1MSB_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1MSB_OFFSET )
+#define BBH_RX_4_DEBUG_CNTXTX1MSB_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_CNTXTX1MSB_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_CNTXTX1MSB_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_CNTXTX1MSB_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_CNTXTX1MSB_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1MSB_OFFSET )
+#define BBH_RX_5_DEBUG_CNTXTX1MSB_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_CNTXTX1MSB_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_CNTXTX1MSB_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_CNTXTX1MSB_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_CNTXTX1MSB_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1MSB_OFFSET )
+#define BBH_RX_6_DEBUG_CNTXTX1MSB_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_CNTXTX1MSB_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_CNTXTX1MSB_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_CNTXTX1MSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_CNTXTX1MSB_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_CNTXTX1MSB_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_CNTXTX1MSB_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_CNTXTX1MSB_READ( i, r ) 	READ_32( BBH_RX_DEBUG_CNTXTX1MSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* First_BN */
+	uint32_t firstbn	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_BN */
+	uint32_t curbn  	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_CNTXTX1MSB ;
+#else
+typedef struct
+{	uint32_t curbn  	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_BN */
+	uint32_t r1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t firstbn	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* First_BN */
+	uint32_t r2     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_CNTXTX1MSB ;
+#endif
+
+/*****************************************************************************************/
+/* IH_context_0                                                                          */
+/* In the case of GPON peripheral, DS flows may arrive interleaved. The BBH supports par */
+/* allel reassembly of up to two interleaved flows (out of 256). For the reassembly proc */
+/* ess the BBH stores a double flow context.                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_IHCNTXT0_R2_DEFAULT_VALUE                             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_R2_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_CUROFFSET_CURRENT_OFFSET_VALUE               ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_CUROFFSET_CURRENT_OFFSET_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_FLOWID_FLOW_ID_VALUE                         ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_FLOWID_FLOW_ID_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_BUFNUM_BUFFER_NUMBER_VALUE                   ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_BUFNUM_BUFFER_NUMBER_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_R1_DEFAULT_VALUE                             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_R1_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_BUFVALID_NOT_IN_REASSEMBLY_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_BUFVALID_NOT_IN_REASSEMBLY_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_BUFVALID_IN_REASSEMBLY_VALUE                 ( 0x1 )
+#define BBH_RX_DEBUG_IHCNTXT0_INREASS_NOT_IN_REASSEMBLY_VALUE              ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_INREASS_NOT_IN_REASSEMBLY_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT0_INREASS_IN_REASSEMBLY_VALUE                  ( 0x1 )
+
+
+#define BBH_RX_DEBUG_IHCNTXT0_OFFSET ( 0x00000010 )
+
+#define BBH_RX_0_DEBUG_IHCNTXT0_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT0_OFFSET )
+#define BBH_RX_0_DEBUG_IHCNTXT0_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_IHCNTXT0_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_IHCNTXT0_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_IHCNTXT0_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_IHCNTXT0_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT0_OFFSET )
+#define BBH_RX_1_DEBUG_IHCNTXT0_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_IHCNTXT0_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_IHCNTXT0_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_IHCNTXT0_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_IHCNTXT0_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT0_OFFSET )
+#define BBH_RX_2_DEBUG_IHCNTXT0_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_IHCNTXT0_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_IHCNTXT0_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_IHCNTXT0_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_IHCNTXT0_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT0_OFFSET )
+#define BBH_RX_3_DEBUG_IHCNTXT0_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_IHCNTXT0_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_IHCNTXT0_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_IHCNTXT0_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_IHCNTXT0_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT0_OFFSET )
+#define BBH_RX_4_DEBUG_IHCNTXT0_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_IHCNTXT0_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_IHCNTXT0_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_IHCNTXT0_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_IHCNTXT0_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT0_OFFSET )
+#define BBH_RX_5_DEBUG_IHCNTXT0_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_IHCNTXT0_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_IHCNTXT0_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_IHCNTXT0_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_IHCNTXT0_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT0_OFFSET )
+#define BBH_RX_6_DEBUG_IHCNTXT0_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_IHCNTXT0_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_IHCNTXT0_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_IHCNTXT0_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_IHCNTXT0_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_IHCNTXT0_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_IHCNTXT0_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_IHCNTXT0_READ( i, r ) 	READ_32( BBH_RX_DEBUG_IHCNTXT0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_offset */
+	uint32_t curoffset	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_ID */
+	uint32_t flowid   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_number */
+	uint32_t bufnum   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_valid */
+	uint32_t bufvalid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_reassembly */
+	uint32_t inreass  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_IHCNTXT0 ;
+#else
+typedef struct
+{	uint32_t inreass  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_reassembly */
+	uint32_t bufvalid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_valid */
+	uint32_t r1       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t bufnum   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_number */
+	uint32_t flowid   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_ID */
+	uint32_t curoffset	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_offset */
+	uint32_t r2       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_IHCNTXT0 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_context_1                                                                          */
+/* In the case of GPON peripheral, DS flows may arrive interleaved. The BBH supports par */
+/* allel reassembly of up to two interleaved flows (out of 256). For the reassembly proc */
+/* ess the BBH stores a double flow context.                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_IHCNTXT1_R2_DEFAULT_VALUE                             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_R2_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_CUROFFSET_CURRENT_OFFSET_VALUE               ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_CUROFFSET_CURRENT_OFFSET_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_FLOWID_FLOW_ID_VALUE                         ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_FLOWID_FLOW_ID_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_BUFNUM_BUFFER_NUMBER_VALUE                   ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_BUFNUM_BUFFER_NUMBER_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_R1_DEFAULT_VALUE                             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_R1_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_BUFVALID_NOT_IN_REASSEMBLY_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_BUFVALID_NOT_IN_REASSEMBLY_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_BUFVALID_IN_REASSEMBLY_VALUE                 ( 0x1 )
+#define BBH_RX_DEBUG_IHCNTXT1_INREASS_NOT_IN_REASSEMBLY_VALUE              ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_INREASS_NOT_IN_REASSEMBLY_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXT1_INREASS_IN_REASSEMBLY_VALUE                  ( 0x1 )
+
+
+#define BBH_RX_DEBUG_IHCNTXT1_OFFSET ( 0x00000014 )
+
+#define BBH_RX_0_DEBUG_IHCNTXT1_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT1_OFFSET )
+#define BBH_RX_0_DEBUG_IHCNTXT1_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_IHCNTXT1_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_IHCNTXT1_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_IHCNTXT1_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_IHCNTXT1_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT1_OFFSET )
+#define BBH_RX_1_DEBUG_IHCNTXT1_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_IHCNTXT1_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_IHCNTXT1_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_IHCNTXT1_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_IHCNTXT1_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT1_OFFSET )
+#define BBH_RX_2_DEBUG_IHCNTXT1_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_IHCNTXT1_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_IHCNTXT1_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_IHCNTXT1_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_IHCNTXT1_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT1_OFFSET )
+#define BBH_RX_3_DEBUG_IHCNTXT1_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_IHCNTXT1_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_IHCNTXT1_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_IHCNTXT1_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_IHCNTXT1_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT1_OFFSET )
+#define BBH_RX_4_DEBUG_IHCNTXT1_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_IHCNTXT1_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_IHCNTXT1_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_IHCNTXT1_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_IHCNTXT1_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT1_OFFSET )
+#define BBH_RX_5_DEBUG_IHCNTXT1_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_IHCNTXT1_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_IHCNTXT1_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_IHCNTXT1_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_IHCNTXT1_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT1_OFFSET )
+#define BBH_RX_6_DEBUG_IHCNTXT1_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_IHCNTXT1_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_IHCNTXT1_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_IHCNTXT1_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_IHCNTXT1_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_IHCNTXT1_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_IHCNTXT1_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_IHCNTXT1_READ( i, r ) 	READ_32( BBH_RX_DEBUG_IHCNTXT1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_offset */
+	uint32_t curoffset	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_ID */
+	uint32_t flowid   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_number */
+	uint32_t bufnum   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_valid */
+	uint32_t bufvalid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_reassembly */
+	uint32_t inreass  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_IHCNTXT1 ;
+#else
+typedef struct
+{	uint32_t inreass  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_reassembly */
+	uint32_t bufvalid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_valid */
+	uint32_t r1       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t bufnum   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_number */
+	uint32_t flowid   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_ID */
+	uint32_t curoffset	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_offset */
+	uint32_t r2       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_IHCNTXT1 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_context_PLOAM                                                                      */
+/* In the case of GPON peripheral, DS flows may arrive interleaved. The BBH supports par */
+/* allel reassembly of up to two interleaved flows (out of 256). For the reassembly proc */
+/* ess the BBH stores a double flow context.                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_IHCNTXTP_R2_DEFAULT_VALUE                             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_R2_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_CUROFFSET_CURRENT_OFFSET_VALUE               ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_CUROFFSET_CURRENT_OFFSET_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_FLOWID_FLOW_ID_VALUE                         ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_FLOWID_FLOW_ID_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_BUFNUM_BUFFER_NUMBER_VALUE                   ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_BUFNUM_BUFFER_NUMBER_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_R1_DEFAULT_VALUE                             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_R1_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_BUFVALID_NOT_IN_REASSEMBLY_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_BUFVALID_NOT_IN_REASSEMBLY_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_BUFVALID_IN_REASSEMBLY_VALUE                 ( 0x1 )
+#define BBH_RX_DEBUG_IHCNTXTP_INREASS_NOT_IN_REASSEMBLY_VALUE              ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_INREASS_NOT_IN_REASSEMBLY_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_DEBUG_IHCNTXTP_INREASS_IN_REASSEMBLY_VALUE                  ( 0x1 )
+
+
+#define BBH_RX_DEBUG_IHCNTXTP_OFFSET ( 0x00000018 )
+
+#define BBH_RX_0_DEBUG_IHCNTXTP_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXTP_OFFSET )
+#define BBH_RX_0_DEBUG_IHCNTXTP_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_IHCNTXTP_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_IHCNTXTP_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_IHCNTXTP_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_IHCNTXTP_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXTP_OFFSET )
+#define BBH_RX_1_DEBUG_IHCNTXTP_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_IHCNTXTP_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_IHCNTXTP_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_IHCNTXTP_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_IHCNTXTP_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXTP_OFFSET )
+#define BBH_RX_2_DEBUG_IHCNTXTP_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_IHCNTXTP_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_IHCNTXTP_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_IHCNTXTP_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_IHCNTXTP_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXTP_OFFSET )
+#define BBH_RX_3_DEBUG_IHCNTXTP_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_IHCNTXTP_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_IHCNTXTP_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_IHCNTXTP_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_IHCNTXTP_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXTP_OFFSET )
+#define BBH_RX_4_DEBUG_IHCNTXTP_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_IHCNTXTP_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_IHCNTXTP_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_IHCNTXTP_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_IHCNTXTP_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXTP_OFFSET )
+#define BBH_RX_5_DEBUG_IHCNTXTP_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_IHCNTXTP_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_IHCNTXTP_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_IHCNTXTP_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_IHCNTXTP_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXTP_OFFSET )
+#define BBH_RX_6_DEBUG_IHCNTXTP_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_IHCNTXTP_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_IHCNTXTP_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_IHCNTXTP_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_IHCNTXTP_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_IHCNTXTP_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_IHCNTXTP_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_IHCNTXTP_READ( i, r ) 	READ_32( BBH_RX_DEBUG_IHCNTXTP_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_offset */
+	uint32_t curoffset	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_ID */
+	uint32_t flowid   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_number */
+	uint32_t bufnum   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_valid */
+	uint32_t bufvalid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_reassembly */
+	uint32_t inreass  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_IHCNTXTP ;
+#else
+typedef struct
+{	uint32_t inreass  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_reassembly */
+	uint32_t bufvalid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_valid */
+	uint32_t r1       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t bufnum   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_number */
+	uint32_t flowid   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_ID */
+	uint32_t curoffset	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Current_offset */
+	uint32_t r2       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_IHCNTXTP ;
+#endif
+
+/*****************************************************************************************/
+/* IH_free_buffer                                                                        */
+/* This array describes the status of the 16 IH buffers - free = 1, occupied = 0.        */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_IHFREEBUF_R1_RESET_VALUE_VALUE                ( 0x0 )
+#define BBH_RX_DEBUG_IHFREEBUF_R1_RESET_VALUE_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_RX_DEBUG_IHFREEBUF_IHFREEBUF_BUFFREE_VALUE             ( 0xFFFF )
+#define BBH_RX_DEBUG_IHFREEBUF_IHFREEBUF_BUFFREE_VALUE_RESET_VALUE ( 0xFFFF )
+
+
+#define BBH_RX_DEBUG_IHFREEBUF_OFFSET ( 0x0000001C )
+
+#define BBH_RX_0_DEBUG_IHFREEBUF_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_IHFREEBUF_OFFSET )
+#define BBH_RX_0_DEBUG_IHFREEBUF_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_IHFREEBUF_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_IHFREEBUF_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_IHFREEBUF_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_IHFREEBUF_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_IHFREEBUF_OFFSET )
+#define BBH_RX_1_DEBUG_IHFREEBUF_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_IHFREEBUF_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_IHFREEBUF_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_IHFREEBUF_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_IHFREEBUF_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_IHFREEBUF_OFFSET )
+#define BBH_RX_2_DEBUG_IHFREEBUF_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_IHFREEBUF_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_IHFREEBUF_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_IHFREEBUF_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_IHFREEBUF_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_IHFREEBUF_OFFSET )
+#define BBH_RX_3_DEBUG_IHFREEBUF_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_IHFREEBUF_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_IHFREEBUF_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_IHFREEBUF_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_IHFREEBUF_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_IHFREEBUF_OFFSET )
+#define BBH_RX_4_DEBUG_IHFREEBUF_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_IHFREEBUF_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_IHFREEBUF_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_IHFREEBUF_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_IHFREEBUF_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_IHFREEBUF_OFFSET )
+#define BBH_RX_5_DEBUG_IHFREEBUF_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_IHFREEBUF_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_IHFREEBUF_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_IHFREEBUF_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_IHFREEBUF_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_IHFREEBUF_OFFSET )
+#define BBH_RX_6_DEBUG_IHFREEBUF_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_IHFREEBUF_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_IHFREEBUF_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_IHFREEBUF_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_IHFREEBUF_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_IHFREEBUF_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_IHFREEBUF_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_IHFREEBUF_READ( i, r ) 	READ_32( BBH_RX_DEBUG_IHFREEBUF_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1       	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_free_buffer */
+	uint32_t ihfreebuf	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_IHFREEBUF ;
+#else
+typedef struct
+{	uint32_t ihfreebuf	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_free_buffer */
+	uint32_t r1       	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_IHFREEBUF ;
+#endif
+
+/*****************************************************************************************/
+/* Pre_wakeup_fifo_used_words                                                            */
+/* Pre wakeup FIFO used words                                                            */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_PWUW_R1_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_PWUW_R1_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_PWUW_UW_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_PWUW_UW_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_DEBUG_PWUW_OFFSET ( 0x00000020 )
+
+#define BBH_RX_0_DEBUG_PWUW_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_PWUW_OFFSET )
+#define BBH_RX_0_DEBUG_PWUW_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_PWUW_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_PWUW_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_PWUW_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_PWUW_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_PWUW_OFFSET )
+#define BBH_RX_1_DEBUG_PWUW_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_PWUW_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_PWUW_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_PWUW_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_PWUW_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_PWUW_OFFSET )
+#define BBH_RX_2_DEBUG_PWUW_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_PWUW_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_PWUW_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_PWUW_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_PWUW_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_PWUW_OFFSET )
+#define BBH_RX_3_DEBUG_PWUW_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_PWUW_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_PWUW_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_PWUW_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_PWUW_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_PWUW_OFFSET )
+#define BBH_RX_4_DEBUG_PWUW_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_PWUW_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_PWUW_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_PWUW_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_PWUW_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_PWUW_OFFSET )
+#define BBH_RX_5_DEBUG_PWUW_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_PWUW_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_PWUW_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_PWUW_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_PWUW_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_PWUW_OFFSET )
+#define BBH_RX_6_DEBUG_PWUW_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_PWUW_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_PWUW_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_PWUW_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_PWUW_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_PWUW_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_PWUW_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_PWUW_READ( i, r ) 	READ_32( BBH_RX_DEBUG_PWUW_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Used_words */
+	uint32_t uw	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_PWUW ;
+#else
+typedef struct
+{	uint32_t uw	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Used_words */
+	uint32_t r1	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_PWUW ;
+#endif
+
+/*****************************************************************************************/
+/* ACK_counters                                                                          */
+/* The register reflects 3 ACK counters:  DMA  SDMA  CONNECT                             */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_ACKCNT_R1_RESET_VALUE_VALUE                  ( 0x0 )
+#define BBH_RX_DEBUG_ACKCNT_R1_RESET_VALUE_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_DEBUG_ACKCNT_CONNECT_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_ACKCNT_CONNECT_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_ACKCNT_SDMA_RESET_VALUE_VALUE                ( 0x0 )
+#define BBH_RX_DEBUG_ACKCNT_SDMA_RESET_VALUE_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_RX_DEBUG_ACKCNT_DMA_RESET_VALUE_VALUE                 ( 0x0 )
+#define BBH_RX_DEBUG_ACKCNT_DMA_RESET_VALUE_VALUE_RESET_VALUE     ( 0x0 )
+
+
+#define BBH_RX_DEBUG_ACKCNT_OFFSET ( 0x00000024 )
+
+#define BBH_RX_0_DEBUG_ACKCNT_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_ACKCNT_OFFSET )
+#define BBH_RX_0_DEBUG_ACKCNT_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_ACKCNT_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_ACKCNT_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_ACKCNT_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_ACKCNT_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_ACKCNT_OFFSET )
+#define BBH_RX_1_DEBUG_ACKCNT_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_ACKCNT_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_ACKCNT_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_ACKCNT_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_ACKCNT_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_ACKCNT_OFFSET )
+#define BBH_RX_2_DEBUG_ACKCNT_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_ACKCNT_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_ACKCNT_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_ACKCNT_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_ACKCNT_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_ACKCNT_OFFSET )
+#define BBH_RX_3_DEBUG_ACKCNT_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_ACKCNT_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_ACKCNT_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_ACKCNT_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_ACKCNT_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_ACKCNT_OFFSET )
+#define BBH_RX_4_DEBUG_ACKCNT_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_ACKCNT_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_ACKCNT_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_ACKCNT_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_ACKCNT_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_ACKCNT_OFFSET )
+#define BBH_RX_5_DEBUG_ACKCNT_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_ACKCNT_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_ACKCNT_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_ACKCNT_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_ACKCNT_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_ACKCNT_OFFSET )
+#define BBH_RX_6_DEBUG_ACKCNT_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_ACKCNT_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_ACKCNT_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_ACKCNT_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_ACKCNT_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_ACKCNT_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_ACKCNT_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_ACKCNT_READ( i, r ) 	READ_32( BBH_RX_DEBUG_ACKCNT_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1     	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Connect */
+	uint32_t connect	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA */
+	uint32_t sdma   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA */
+	uint32_t dma    	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_ACKCNT ;
+#else
+typedef struct
+{	uint32_t dma    	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA */
+	uint32_t sdma   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA */
+	uint32_t connect	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Connect */
+	uint32_t r1     	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_ACKCNT ;
+#endif
+
+/*****************************************************************************************/
+/* Runner_counters                                                                       */
+/* The register reflects 4 Runner pending descriptors counters:  Runner 0 normal  Runner */
+/*  0 direct  Runner 1 normal  Runner 1 direct                                           */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_RNRCNT_R4_RESET_VALUE_VALUE              ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R4_RESET_VALUE_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R1D_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R1D_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R3_RESET_VALUE_VALUE              ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R3_RESET_VALUE_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R1N_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R1N_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R2_RESET_VALUE_VALUE              ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R2_RESET_VALUE_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R0D_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R0D_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R1_RESET_VALUE_VALUE              ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R1_RESET_VALUE_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R0N_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_RNRCNT_R0N_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_DEBUG_RNRCNT_OFFSET ( 0x00000028 )
+
+#define BBH_RX_0_DEBUG_RNRCNT_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_RNRCNT_OFFSET )
+#define BBH_RX_0_DEBUG_RNRCNT_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_RNRCNT_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_RNRCNT_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_RNRCNT_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_RNRCNT_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_RNRCNT_OFFSET )
+#define BBH_RX_1_DEBUG_RNRCNT_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_RNRCNT_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_RNRCNT_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_RNRCNT_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_RNRCNT_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_RNRCNT_OFFSET )
+#define BBH_RX_2_DEBUG_RNRCNT_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_RNRCNT_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_RNRCNT_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_RNRCNT_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_RNRCNT_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_RNRCNT_OFFSET )
+#define BBH_RX_3_DEBUG_RNRCNT_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_RNRCNT_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_RNRCNT_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_RNRCNT_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_RNRCNT_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_RNRCNT_OFFSET )
+#define BBH_RX_4_DEBUG_RNRCNT_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_RNRCNT_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_RNRCNT_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_RNRCNT_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_RNRCNT_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_RNRCNT_OFFSET )
+#define BBH_RX_5_DEBUG_RNRCNT_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_RNRCNT_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_RNRCNT_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_RNRCNT_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_RNRCNT_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_RNRCNT_OFFSET )
+#define BBH_RX_6_DEBUG_RNRCNT_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_RNRCNT_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_RNRCNT_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_RNRCNT_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_RNRCNT_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_RNRCNT_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_RNRCNT_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_RNRCNT_READ( i, r ) 	READ_32( BBH_RX_DEBUG_RNRCNT_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_1_direct */
+	uint32_t r1d	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_1_normal */
+	uint32_t r1n	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_0_direct */
+	uint32_t r0d	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_0_normal */
+	uint32_t r0n	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_RNRCNT ;
+#else
+typedef struct
+{	uint32_t r0n	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_0_normal */
+	uint32_t r1 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r0d	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_0_direct */
+	uint32_t r2 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1n	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_1_normal */
+	uint32_t r3 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1d	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_1_direct */
+	uint32_t r4 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_RNRCNT ;
+#endif
+
+/*****************************************************************************************/
+/* Debug_vector                                                                          */
+/* selected debug vector                                                                 */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_DBGVEC_R1_RESET_VALUE_VALUE                 ( 0x0 )
+#define BBH_RX_DEBUG_DBGVEC_R1_RESET_VALUE_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_RX_DEBUG_DBGVEC_DBGVEC_RESET_VALUE_VALUE             ( 0x11000 )
+#define BBH_RX_DEBUG_DBGVEC_DBGVEC_RESET_VALUE_VALUE_RESET_VALUE ( 0x11000 )
+
+
+#define BBH_RX_DEBUG_DBGVEC_OFFSET ( 0x0000002C )
+
+#define BBH_RX_0_DEBUG_DBGVEC_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_DBGVEC_OFFSET )
+#define BBH_RX_0_DEBUG_DBGVEC_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_DBGVEC_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_DBGVEC_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_DBGVEC_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_DBGVEC_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_DBGVEC_OFFSET )
+#define BBH_RX_1_DEBUG_DBGVEC_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_DBGVEC_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_DBGVEC_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_DBGVEC_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_DBGVEC_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_DBGVEC_OFFSET )
+#define BBH_RX_2_DEBUG_DBGVEC_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_DBGVEC_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_DBGVEC_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_DBGVEC_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_DBGVEC_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_DBGVEC_OFFSET )
+#define BBH_RX_3_DEBUG_DBGVEC_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_DBGVEC_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_DBGVEC_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_DBGVEC_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_DBGVEC_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_DBGVEC_OFFSET )
+#define BBH_RX_4_DEBUG_DBGVEC_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_DBGVEC_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_DBGVEC_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_DBGVEC_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_DBGVEC_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_DBGVEC_OFFSET )
+#define BBH_RX_5_DEBUG_DBGVEC_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_DBGVEC_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_DBGVEC_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_DBGVEC_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_DBGVEC_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_DBGVEC_OFFSET )
+#define BBH_RX_6_DEBUG_DBGVEC_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_DBGVEC_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_DBGVEC_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_DBGVEC_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_DBGVEC_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_DBGVEC_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_DBGVEC_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_DBGVEC_READ( i, r ) 	READ_32( BBH_RX_DEBUG_DBGVEC_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1    	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Debug_vector */
+	uint32_t dbgvec	: 21 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_DBGVEC ;
+#else
+typedef struct
+{	uint32_t dbgvec	: 21 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Debug_vector */
+	uint32_t r1    	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_DBGVEC ;
+#endif
+
+/*****************************************************************************************/
+/* DDR_BN_FIFO                                                                           */
+/* The BBH RX hold a FIFO with 8 BN.                                                     */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_BNFIFO_R2_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_DEBUG_BNFIFO_R2_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_DEBUG_BNFIFO_VALID_NOT_VALID_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_BNFIFO_VALID_NOT_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_BNFIFO_VALID_VALID_VALUE                 ( 0x1 )
+#define BBH_RX_DEBUG_BNFIFO_R1_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_DEBUG_BNFIFO_R1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_DEBUG_BNFIFO_BNENTRY_BN_VALUE                  ( 0x0 )
+#define BBH_RX_DEBUG_BNFIFO_BNENTRY_BN_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define BBH_RX_DEBUG_BNFIFO_OFFSET ( 0x00000030 )
+
+#define BBH_RX_0_DEBUG_BNFIFO_ADDRESS        	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_BNFIFO_OFFSET )
+#define BBH_RX_0_DEBUG_BNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_0_DEBUG_BNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_0_DEBUG_BNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_0_DEBUG_BNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_1_DEBUG_BNFIFO_ADDRESS        	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_BNFIFO_OFFSET )
+#define BBH_RX_1_DEBUG_BNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_1_DEBUG_BNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_1_DEBUG_BNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_1_DEBUG_BNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_2_DEBUG_BNFIFO_ADDRESS        	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_BNFIFO_OFFSET )
+#define BBH_RX_2_DEBUG_BNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_2_DEBUG_BNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_2_DEBUG_BNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_2_DEBUG_BNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_3_DEBUG_BNFIFO_ADDRESS        	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_BNFIFO_OFFSET )
+#define BBH_RX_3_DEBUG_BNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_3_DEBUG_BNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_3_DEBUG_BNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_3_DEBUG_BNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_4_DEBUG_BNFIFO_ADDRESS        	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_BNFIFO_OFFSET )
+#define BBH_RX_4_DEBUG_BNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_4_DEBUG_BNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_4_DEBUG_BNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_4_DEBUG_BNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_5_DEBUG_BNFIFO_ADDRESS        	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_BNFIFO_OFFSET )
+#define BBH_RX_5_DEBUG_BNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_5_DEBUG_BNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_5_DEBUG_BNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_5_DEBUG_BNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_6_DEBUG_BNFIFO_ADDRESS        	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_BNFIFO_OFFSET )
+#define BBH_RX_6_DEBUG_BNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_6_DEBUG_BNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_6_DEBUG_BNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_6_DEBUG_BNFIFO_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_BNFIFO_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_BNFIFO_WRITE( i, k, v )	WRITE_I_32( BBH_RX_DEBUG_BNFIFO_ARRAY [ i ], (k), (v) )
+#define BBH_RX_DEBUG_BNFIFO_READ( i, k, r ) 	READ_I_32( BBH_RX_DEBUG_BNFIFO_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VALID */
+	uint32_t valid  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BN_entry */
+	uint32_t bnentry	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_BNFIFO ;
+#else
+typedef struct
+{	uint32_t bnentry	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BN_entry */
+	uint32_t r1     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t valid  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VALID */
+	uint32_t r2     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_BNFIFO ;
+#endif
+
+/*****************************************************************************************/
+/* SRAM_BN_FIFO                                                                          */
+/* The BBH RX hold a FIFO with 8 BN.                                                     */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_SBNFIFO_R2_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_DEBUG_SBNFIFO_R2_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_DEBUG_SBNFIFO_VALID_NOT_VALID_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_SBNFIFO_VALID_NOT_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_SBNFIFO_VALID_VALID_VALUE                 ( 0x1 )
+#define BBH_RX_DEBUG_SBNFIFO_R1_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_RX_DEBUG_SBNFIFO_R1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_RX_DEBUG_SBNFIFO_BNENTRY_BN_VALUE                  ( 0x0 )
+#define BBH_RX_DEBUG_SBNFIFO_BNENTRY_BN_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define BBH_RX_DEBUG_SBNFIFO_OFFSET ( 0x00000050 )
+
+#define BBH_RX_0_DEBUG_SBNFIFO_ADDRESS        	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_SBNFIFO_OFFSET )
+#define BBH_RX_0_DEBUG_SBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_0_DEBUG_SBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_0_DEBUG_SBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_0_DEBUG_SBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_1_DEBUG_SBNFIFO_ADDRESS        	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_SBNFIFO_OFFSET )
+#define BBH_RX_1_DEBUG_SBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_1_DEBUG_SBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_1_DEBUG_SBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_1_DEBUG_SBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_2_DEBUG_SBNFIFO_ADDRESS        	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_SBNFIFO_OFFSET )
+#define BBH_RX_2_DEBUG_SBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_2_DEBUG_SBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_2_DEBUG_SBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_2_DEBUG_SBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_3_DEBUG_SBNFIFO_ADDRESS        	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_SBNFIFO_OFFSET )
+#define BBH_RX_3_DEBUG_SBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_3_DEBUG_SBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_3_DEBUG_SBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_3_DEBUG_SBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_4_DEBUG_SBNFIFO_ADDRESS        	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_SBNFIFO_OFFSET )
+#define BBH_RX_4_DEBUG_SBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_4_DEBUG_SBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_4_DEBUG_SBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_4_DEBUG_SBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_5_DEBUG_SBNFIFO_ADDRESS        	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_SBNFIFO_OFFSET )
+#define BBH_RX_5_DEBUG_SBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_5_DEBUG_SBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_5_DEBUG_SBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_5_DEBUG_SBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_6_DEBUG_SBNFIFO_ADDRESS        	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_SBNFIFO_OFFSET )
+#define BBH_RX_6_DEBUG_SBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_6_DEBUG_SBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_6_DEBUG_SBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_6_DEBUG_SBNFIFO_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_SBNFIFO_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_SBNFIFO_WRITE( i, k, v )	WRITE_I_32( BBH_RX_DEBUG_SBNFIFO_ARRAY [ i ], (k), (v) )
+#define BBH_RX_DEBUG_SBNFIFO_READ( i, k, r ) 	READ_I_32( BBH_RX_DEBUG_SBNFIFO_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VALID */
+	uint32_t valid  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BN_entry */
+	uint32_t bnentry	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_SBNFIFO ;
+#else
+typedef struct
+{	uint32_t bnentry	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BN_entry */
+	uint32_t r1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t valid  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VALID */
+	uint32_t r2     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_SBNFIFO ;
+#endif
+
+/*****************************************************************************************/
+/* IH_response_FIFO                                                                      */
+/* The BBH RX hold a FIFO with 16 IH 2nd responses.                                      */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_RESFIFO_R2_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_DEBUG_RESFIFO_R2_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_RX_DEBUG_RESFIFO_VALID_NOT_VALID_VALUE               ( 0x0 )
+#define BBH_RX_DEBUG_RESFIFO_VALID_NOT_VALID_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_DEBUG_RESFIFO_VALID_VALID_VALUE                   ( 0x1 )
+#define BBH_RX_DEBUG_RESFIFO_R1_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_RX_DEBUG_RESFIFO_R1_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_RX_DEBUG_RESFIFO_RESENTRY_RESPONSE_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_RESFIFO_RESENTRY_RESPONSE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_DEBUG_RESFIFO_OFFSET ( 0x00000070 )
+
+#define BBH_RX_0_DEBUG_RESFIFO_ADDRESS        	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_RESFIFO_OFFSET )
+#define BBH_RX_0_DEBUG_RESFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_0_DEBUG_RESFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_0_DEBUG_RESFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_0_DEBUG_RESFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_1_DEBUG_RESFIFO_ADDRESS        	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_RESFIFO_OFFSET )
+#define BBH_RX_1_DEBUG_RESFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_1_DEBUG_RESFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_1_DEBUG_RESFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_1_DEBUG_RESFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_2_DEBUG_RESFIFO_ADDRESS        	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_RESFIFO_OFFSET )
+#define BBH_RX_2_DEBUG_RESFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_2_DEBUG_RESFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_2_DEBUG_RESFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_2_DEBUG_RESFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_3_DEBUG_RESFIFO_ADDRESS        	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_RESFIFO_OFFSET )
+#define BBH_RX_3_DEBUG_RESFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_3_DEBUG_RESFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_3_DEBUG_RESFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_3_DEBUG_RESFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_4_DEBUG_RESFIFO_ADDRESS        	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_RESFIFO_OFFSET )
+#define BBH_RX_4_DEBUG_RESFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_4_DEBUG_RESFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_4_DEBUG_RESFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_4_DEBUG_RESFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_5_DEBUG_RESFIFO_ADDRESS        	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_RESFIFO_OFFSET )
+#define BBH_RX_5_DEBUG_RESFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_5_DEBUG_RESFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_5_DEBUG_RESFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_5_DEBUG_RESFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_RX_6_DEBUG_RESFIFO_ADDRESS        	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_RESFIFO_OFFSET )
+#define BBH_RX_6_DEBUG_RESFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_6_DEBUG_RESFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_6_DEBUG_RESFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_6_DEBUG_RESFIFO_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_RESFIFO_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_RESFIFO_WRITE( i, k, v )	WRITE_I_32( BBH_RX_DEBUG_RESFIFO_ARRAY [ i ], (k), (v) )
+#define BBH_RX_DEBUG_RESFIFO_READ( i, k, r ) 	READ_I_32( BBH_RX_DEBUG_RESFIFO_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2      	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VALID */
+	uint32_t valid   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Response_entry */
+	uint32_t resentry	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_RESFIFO ;
+#else
+typedef struct
+{	uint32_t resentry	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Response_entry */
+	uint32_t r1      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t valid   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VALID */
+	uint32_t r2      	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_RESFIFO ;
+#endif
+
+/*****************************************************************************************/
+/* Epon_sync_fifo_used_words                                                             */
+/* EPON sync FIFO used words                                                             */
+/*****************************************************************************************/
+
+#define BBH_RX_DEBUG_ESUW_R1_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_ESUW_R1_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_RX_DEBUG_ESUW_UW_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_RX_DEBUG_ESUW_UW_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_DEBUG_ESUW_OFFSET ( 0x000000B0 )
+
+#define BBH_RX_0_DEBUG_ESUW_ADDRESS   	( BBH_RX_0_DEBUG_ADDRESS + BBH_RX_DEBUG_ESUW_OFFSET )
+#define BBH_RX_0_DEBUG_ESUW_READ( r ) 	READ_32( ( BBH_RX_0_DEBUG_ESUW_ADDRESS ), (r) )
+#define BBH_RX_0_DEBUG_ESUW_WRITE( v )	WRITE_32( ( BBH_RX_0_DEBUG_ESUW_ADDRESS ), (v) )
+
+#define BBH_RX_1_DEBUG_ESUW_ADDRESS   	( BBH_RX_1_DEBUG_ADDRESS + BBH_RX_DEBUG_ESUW_OFFSET )
+#define BBH_RX_1_DEBUG_ESUW_READ( r ) 	READ_32( ( BBH_RX_1_DEBUG_ESUW_ADDRESS ), (r) )
+#define BBH_RX_1_DEBUG_ESUW_WRITE( v )	WRITE_32( ( BBH_RX_1_DEBUG_ESUW_ADDRESS ), (v) )
+
+#define BBH_RX_2_DEBUG_ESUW_ADDRESS   	( BBH_RX_2_DEBUG_ADDRESS + BBH_RX_DEBUG_ESUW_OFFSET )
+#define BBH_RX_2_DEBUG_ESUW_READ( r ) 	READ_32( ( BBH_RX_2_DEBUG_ESUW_ADDRESS ), (r) )
+#define BBH_RX_2_DEBUG_ESUW_WRITE( v )	WRITE_32( ( BBH_RX_2_DEBUG_ESUW_ADDRESS ), (v) )
+
+#define BBH_RX_3_DEBUG_ESUW_ADDRESS   	( BBH_RX_3_DEBUG_ADDRESS + BBH_RX_DEBUG_ESUW_OFFSET )
+#define BBH_RX_3_DEBUG_ESUW_READ( r ) 	READ_32( ( BBH_RX_3_DEBUG_ESUW_ADDRESS ), (r) )
+#define BBH_RX_3_DEBUG_ESUW_WRITE( v )	WRITE_32( ( BBH_RX_3_DEBUG_ESUW_ADDRESS ), (v) )
+
+#define BBH_RX_4_DEBUG_ESUW_ADDRESS   	( BBH_RX_4_DEBUG_ADDRESS + BBH_RX_DEBUG_ESUW_OFFSET )
+#define BBH_RX_4_DEBUG_ESUW_READ( r ) 	READ_32( ( BBH_RX_4_DEBUG_ESUW_ADDRESS ), (r) )
+#define BBH_RX_4_DEBUG_ESUW_WRITE( v )	WRITE_32( ( BBH_RX_4_DEBUG_ESUW_ADDRESS ), (v) )
+
+#define BBH_RX_5_DEBUG_ESUW_ADDRESS   	( BBH_RX_5_DEBUG_ADDRESS + BBH_RX_DEBUG_ESUW_OFFSET )
+#define BBH_RX_5_DEBUG_ESUW_READ( r ) 	READ_32( ( BBH_RX_5_DEBUG_ESUW_ADDRESS ), (r) )
+#define BBH_RX_5_DEBUG_ESUW_WRITE( v )	WRITE_32( ( BBH_RX_5_DEBUG_ESUW_ADDRESS ), (v) )
+
+#define BBH_RX_6_DEBUG_ESUW_ADDRESS   	( BBH_RX_6_DEBUG_ADDRESS + BBH_RX_DEBUG_ESUW_OFFSET )
+#define BBH_RX_6_DEBUG_ESUW_READ( r ) 	READ_32( ( BBH_RX_6_DEBUG_ESUW_ADDRESS ), (r) )
+#define BBH_RX_6_DEBUG_ESUW_WRITE( v )	WRITE_32( ( BBH_RX_6_DEBUG_ESUW_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_RX_DEBUG_ESUW_ARRAY [ ] ;
+
+#define BBH_RX_DEBUG_ESUW_WRITE( i, v )	WRITE_32( BBH_RX_DEBUG_ESUW_ARRAY [ i ], (v) )
+#define BBH_RX_DEBUG_ESUW_READ( i, r ) 	READ_32( BBH_RX_DEBUG_ESUW_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Used_words */
+	uint32_t uw	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_ESUW ;
+#else
+typedef struct
+{	uint32_t uw	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Used_words */
+	uint32_t r1	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG_ESUW ;
+#endif
+
+/*****************************************************************************************/
+/* Per_flo_error                                                                         */
+/* This set of 256 counters counts the packets dropped by IH per flow.  These counters a */
+/* re cleared when read and freeze when reaches the maximum value.  The SW should clear  */
+/* these counters in initialization stage by reading each of them.                       */
+/*****************************************************************************************/
+
+#define BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_R1_RESERVED_VALUE               ( 0x0 )
+#define BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_R1_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_PMCNT_DEFAULT_VALUE             ( 0x0 )
+#define BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_PMCNT_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_OFFSET ( 0x00000000 )
+
+#define BBH_RX_0_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS        	( BBH_RX_0_PER_FLOW_PM_COUNTERS_ADDRESS + BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_OFFSET )
+#define BBH_RX_0_PER_FLOW_PM_COUNTERS_PERFLOWPM_READ_I( r, i ) 	READ_I_32( ( BBH_RX_0_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (r) )
+#define BBH_RX_0_PER_FLOW_PM_COUNTERS_PERFLOWPM_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_0_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (v) )
+
+#define BBH_RX_1_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS        	( BBH_RX_1_PER_FLOW_PM_COUNTERS_ADDRESS + BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_OFFSET )
+#define BBH_RX_1_PER_FLOW_PM_COUNTERS_PERFLOWPM_READ_I( r, i ) 	READ_I_32( ( BBH_RX_1_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (r) )
+#define BBH_RX_1_PER_FLOW_PM_COUNTERS_PERFLOWPM_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_1_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (v) )
+
+#define BBH_RX_2_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS        	( BBH_RX_2_PER_FLOW_PM_COUNTERS_ADDRESS + BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_OFFSET )
+#define BBH_RX_2_PER_FLOW_PM_COUNTERS_PERFLOWPM_READ_I( r, i ) 	READ_I_32( ( BBH_RX_2_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (r) )
+#define BBH_RX_2_PER_FLOW_PM_COUNTERS_PERFLOWPM_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_2_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (v) )
+
+#define BBH_RX_3_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS        	( BBH_RX_3_PER_FLOW_PM_COUNTERS_ADDRESS + BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_OFFSET )
+#define BBH_RX_3_PER_FLOW_PM_COUNTERS_PERFLOWPM_READ_I( r, i ) 	READ_I_32( ( BBH_RX_3_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (r) )
+#define BBH_RX_3_PER_FLOW_PM_COUNTERS_PERFLOWPM_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_3_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (v) )
+
+#define BBH_RX_4_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS        	( BBH_RX_4_PER_FLOW_PM_COUNTERS_ADDRESS + BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_OFFSET )
+#define BBH_RX_4_PER_FLOW_PM_COUNTERS_PERFLOWPM_READ_I( r, i ) 	READ_I_32( ( BBH_RX_4_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (r) )
+#define BBH_RX_4_PER_FLOW_PM_COUNTERS_PERFLOWPM_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_4_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (v) )
+
+#define BBH_RX_5_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS        	( BBH_RX_5_PER_FLOW_PM_COUNTERS_ADDRESS + BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_OFFSET )
+#define BBH_RX_5_PER_FLOW_PM_COUNTERS_PERFLOWPM_READ_I( r, i ) 	READ_I_32( ( BBH_RX_5_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (r) )
+#define BBH_RX_5_PER_FLOW_PM_COUNTERS_PERFLOWPM_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_5_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (v) )
+
+#define BBH_RX_6_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS        	( BBH_RX_6_PER_FLOW_PM_COUNTERS_ADDRESS + BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_OFFSET )
+#define BBH_RX_6_PER_FLOW_PM_COUNTERS_PERFLOWPM_READ_I( r, i ) 	READ_I_32( ( BBH_RX_6_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (r) )
+#define BBH_RX_6_PER_FLOW_PM_COUNTERS_PERFLOWPM_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_6_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_ARRAY [ ] ;
+
+#define BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_WRITE( i, k, v )	WRITE_I_32( BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_ARRAY [ i ], (k), (v) )
+#define BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_READ( i, k, r ) 	READ_I_32( BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1   	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Per_flow_PM */
+	uint32_t pmcnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM ;
+#else
+typedef struct
+{	uint32_t pmcnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Per_flow_PM */
+	uint32_t r1   	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM ;
+#endif
+
+/*****************************************************************************************/
+/* BB_Cfg                                                                                */
+/* Each BBH unit has its own position on the BB tree. This position defines the Route ad */
+/* dress when approaching the Runner, S/DMA or S/BPM.                                    */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_R4_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_R4_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_BPMROUTE_BPM_ROUTE_VALUE                   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_BPMROUTE_BPM_ROUTE_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_R3_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_R3_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_RUNNERROUTE_RUNNER_ROUTE_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_RUNNERROUTE_RUNNER_ROUTE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_R2_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_R2_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_DMAROUTE_DMA_ROUTE_VALUE                   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_DMAROUTE_DMA_ROUTE_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_R1_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_R1_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_OFFSET ( 0x00000000 )
+
+#define BBH_TX_0_CONFIGURATIONS_BBCFG_TX_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG_TX_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_BBCFG_TX_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_BBCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_BBCFG_TX_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG_TX_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_BBCFG_TX_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_BBCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_BBCFG_TX_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG_TX_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_BBCFG_TX_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_BBCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_BBCFG_TX_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG_TX_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_BBCFG_TX_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_BBCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_BBCFG_TX_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG_TX_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_BBCFG_TX_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_BBCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_BBCFG_TX_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG_TX_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_BBCFG_TX_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_BBCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_BBCFG_TX_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG_TX_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_BBCFG_TX_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_BBCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_BBCFG_TX_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_BBCFG_TX_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_BBCFG_TX_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_BBCFG_TX_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_route_address */
+	uint32_t bpmroute   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_route_address */
+	uint32_t runnerroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_route_address */
+	uint32_t dmaroute   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1         	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_BBCFG_TX ;
+#else
+typedef struct
+{	uint32_t r1         	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t dmaroute   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_route_address */
+	uint32_t r2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t runnerroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_route_address */
+	uint32_t r3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t bpmroute   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_route_address */
+	uint32_t r4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_BBCFG_TX ;
+#endif
+
+/*****************************************************************************************/
+/* BB_Cfg_1                                                                              */
+/* Each BBH unit has its own position on the BB tree. This position defines the Route ad */
+/* dress when approaching the Runner, S/DMA or S/BPM.  This register is relevalt only fo */
+/* r Ethernet.                                                                           */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_R3_DEFAULT_VALUE                            ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_R3_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_RNRSTSROUTE_RNR_STS_ROUTE_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_RNRSTSROUTE_RNR_STS_ROUTE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_R2_DEFAULT_VALUE                            ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_R2_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_SBPMROUTE_BPM_ROUTE_VALUE                   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_SBPMROUTE_BPM_ROUTE_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_R1_DEFAULT_VALUE                            ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_R1_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_SDMAROUTE_DMA_ROUTE_VALUE                   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_SDMAROUTE_DMA_ROUTE_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_OFFSET ( 0x00000004 )
+
+#define BBH_TX_0_CONFIGURATIONS_BBCFG1_TX_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG1_TX_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_BBCFG1_TX_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_BBCFG1_TX_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_BBCFG1_TX_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG1_TX_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_BBCFG1_TX_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_BBCFG1_TX_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_BBCFG1_TX_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG1_TX_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_BBCFG1_TX_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_BBCFG1_TX_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_BBCFG1_TX_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG1_TX_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_BBCFG1_TX_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_BBCFG1_TX_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_BBCFG1_TX_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG1_TX_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_BBCFG1_TX_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_BBCFG1_TX_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_BBCFG1_TX_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG1_TX_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_BBCFG1_TX_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_BBCFG1_TX_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_BBCFG1_TX_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG1_TX_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_BBCFG1_TX_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_BBCFG1_TX_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_BBCFG1_TX_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_BBCFG1_TX_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_BBCFG1_TX_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_BBCFG1_TX_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r3         	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* runner_sts_route_address */
+	uint32_t rnrstsroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_route_address */
+	uint32_t sbpmroute  	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA_route_address */
+	uint32_t sdmaroute  	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_BBCFG1_TX ;
+#else
+typedef struct
+{	uint32_t sdmaroute  	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA_route_address */
+	uint32_t r1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t sbpmroute  	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_route_address */
+	uint32_t r2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t rnrstsroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* runner_sts_route_address */
+	uint32_t r3         	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_BBCFG1_TX ;
+#endif
+
+/*****************************************************************************************/
+/* DDR_cfg                                                                               */
+/* The BBH reads the packet from the DDR. The Packet is arranged in the DDR in the follo */
+/* wing way:  There are four Header Numbers located in a dedicated part of the DDR. Addr */
+/* ess of these headers = Base (configurable) + 256 (4 headers) * BN; And a single Heade */
+/* r Number located at the buffer. In addition there is a configurable payload start off */
+/* set (4 bits). The Hn and Offset are delivered in the PD. In addition there is a confi */
+/* gurable offset resolution (1, 2 and 4 bytes) and configurable header size. Order of t */
+/* ransmission is: if H0 is required=> Then H0 is transmitted and consecutive to that is */
+/*  the packet payload (main stream applications). If Hn is required then Hn is transmit */
+/* ted and then packet payload (which will start at the PO).  When transmitting a packet */
+/*  with HN=0, the transmission will be as follows:  Start address = Offset* OFFSET_RESO */
+/* LUTION + 0 * HEADER_SIZE  Transmission then continues until the packet is over.  When */
+/*  transmitting a packet with HN>0, the transmission will be as follows:  Start address */
+/*  = <HN BASE> + (HN-1) * 64  HN BASE is a pointer to the first extra buffer in DDR whi */
+/* ch is allocated for HN headers. The size of each extra buffer is 256 bytes, fixed. Th */
+/* e transmission is HEADER_SIZE bytes long, and then transmission jumps to a new addres */
+/* s for the rest of the packet:  Continue address = Offset*OFFSET_RESOLUTION + HEADER_S */
+/* IZE                                                                                   */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_R4_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_R4_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_TXOFFSET_RST_VALUE_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_TXOFFSET_RST_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_R3_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_R3_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_HNSIZE_MIN_VALUE_VALUE               ( 0x4 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_HNSIZE_MAX_VALUE_VALUE               ( 0x40 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_HNSIZE_MAX_VALUE_VALUE_RESET_VALUE   ( 0x40 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_R2_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_R2_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_RES_1B_VALUE               ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_RES_1B_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_RES_2B_VALUE               ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_R1_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_R1_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_BUF_2K_VALUE                 ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_BUF_2K_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_BUF_4K_VALUE                 ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_BUF_16K_VALUE                ( 0x2 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_BUF_2_5K_VALUE               ( 0x3 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_BPMMSG_14_BIT_BN_WIDTH_VALUE         ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_BPMMSG_15_BIT_BN_WIDTH_VALUE         ( 0x1 )
+
+
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_OFFSET ( 0x00000008 )
+
+#define BBH_TX_0_CONFIGURATIONS_DDRCFG_TX_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRCFG_TX_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_DDRCFG_TX_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_DDRCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_DDRCFG_TX_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRCFG_TX_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_DDRCFG_TX_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_DDRCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_DDRCFG_TX_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRCFG_TX_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_DDRCFG_TX_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_DDRCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_DDRCFG_TX_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRCFG_TX_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_DDRCFG_TX_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_DDRCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_DDRCFG_TX_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRCFG_TX_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_DDRCFG_TX_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_DDRCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_DDRCFG_TX_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRCFG_TX_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_DDRCFG_TX_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_DDRCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_DDRCFG_TX_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRCFG_TX_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_DDRCFG_TX_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_DDRCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_DDRCFG_TX_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_DDRCFG_TX_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_DDRCFG_TX_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_DDRCFG_TX_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4       	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TX_offset */
+	uint32_t txoffset 	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HN_size */
+	uint32_t hnsize   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PO_bytes_resulotion */
+	uint32_t byteresul	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1       	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	uint32_t bpmmsg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	uint32_t r0       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_buffer_size */
+	uint32_t bufsize  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_DDRCFG_TX ;
+#else
+typedef struct
+{	uint32_t bufsize  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_buffer_size */
+	uint32_t r0       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	uint32_t bpmmsg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	uint32_t r1       	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t byteresul	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PO_bytes_resulotion */
+	uint32_t r2       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t hnsize   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HN_size */
+	uint32_t r3       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t txoffset 	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TX_offset */
+	uint32_t r4       	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_DDRCFG_TX ;
+#endif
+
+/*****************************************************************************************/
+/* HN_BASE                                                                               */
+/* The BBH reads the packet from the DDR. The Packet is arranged in the DDR in the follo */
+/* wing way:  There are seven Header Numbers located in a dedicated part of the DDR. Add */
+/* ress of these headers = Base (configurable) + 512 (7 headers) * BN; And a single Head */
+/* er Number located at the buffer. In addition there is a configurable payload start of */
+/* fset (4 bits). The Hn and Offset are delivered in the PD. In addition there is a conf */
+/* igurable offset resolution (1, 2 and 4 bytes) and configurable header size. Order of  */
+/* transmission is: if H0 is required=> Then H0 is transmitted and consecutive to that i */
+/* s the packet payload (main stream applications). If Hn is required then Hn is transmi */
+/* tted and then packet payload (which will start at the PO). (Motivation: In the case o */
+/* f Multicast packets with a different VLAN manipulation command per EMAC the main buff */
+/* ers are not replicated, but the Runner/CPU created a unique header per copy of the mu */
+/* lticast packet).  When transmitting a packet with HN=0, the transmission will be as f */
+/* ollows:  Start address = Offset* OFFSET_RESOLUTION + 0 * HEADER_SIZE  Transmission th */
+/* en continues until the packet is over.  When transmitting a packet with HN>0, the tra */
+/* nsmission will be as follows:  Start address = <HN BASE> + (HN-1) * 64  HN BASE is a  */
+/* pointer to the first extra buffer in DDR which is allocated for HN headers. The size  */
+/* of each extra buffer is 512 bytes, fixed. The transmission is HEADER_SIZE bytes long, */
+/*  and then transmission jumps to a new address for the rest of the packet:  Continue a */
+/* ddress = Offset*OFFSET_RESOLUTION + HEADER_SIZE                                       */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_HNBASE_HNBASE_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_HNBASE_HNBASE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_HNBASE_OFFSET ( 0x0000000C )
+
+#define BBH_TX_0_CONFIGURATIONS_HNBASE_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_HNBASE_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_HNBASE_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_HNBASE_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_HNBASE_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_HNBASE_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_HNBASE_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_HNBASE_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_HNBASE_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_HNBASE_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_HNBASE_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_HNBASE_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_HNBASE_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_HNBASE_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_HNBASE_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_HNBASE_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_HNBASE_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_HNBASE_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_HNBASE_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_HNBASE_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_HNBASE_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_HNBASE_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_HNBASE_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_HNBASE_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_HNBASE_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_HNBASE_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_HNBASE_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_HNBASE_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_HNBASE_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_HNBASE_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_HNBASE_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_HNBASE_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_HNBASE_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_HNBASE_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_HNBASE_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_HNBASE_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_HNBASE_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_HNBASE_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_HNBASE_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_HNBASE_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_HNBASE_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_HNBASE_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_HNBASE_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_HNBASE_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_HNBASE_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_HNBASE_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_HNBASE_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* HN_base */
+	uint32_t hnbase	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_HNBASE ;
+#else
+typedef struct
+{	uint32_t hnbase	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HN_base */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_HNBASE ;
+#endif
+
+/*****************************************************************************************/
+/* Task_numbers_LSB                                                                      */
+/* The BBH manages 40 queues for GPON or 32 queues for EPON.  Each of the first 8 Queues */
+/*  may have a unique Runner task number.  Queues 8-39 have all the same configurable ta */
+/* sk number.  This register defines the tasks for Queues 0-3.  For Ethernet queue 0 sho */
+/* uld be configured.                                                                    */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_TASKLSB_R4_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_R4_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_TASK3_TASK_NUMBER_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_TASK3_TASK_NUMBER_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_R3_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_R3_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_TASK2_TASK_NUMBER_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_TASK2_TASK_NUMBER_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_R2_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_R2_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_TASK1_TASK_NUMBER_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_TASK1_TASK_NUMBER_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_R1_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_R1_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_TASK0_TASK_NUMBER_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_TASK0_TASK_NUMBER_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_TASKLSB_OFFSET ( 0x00000010 )
+
+#define BBH_TX_0_CONFIGURATIONS_TASKLSB_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKLSB_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_TASKLSB_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKLSB_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_TASKLSB_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKLSB_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_TASKLSB_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKLSB_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_TASKLSB_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKLSB_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_TASKLSB_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKLSB_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_TASKLSB_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKLSB_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_TASKLSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_TASKLSB_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_TASKLSB_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_TASKLSB_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_TASKLSB_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_TASKLSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_3 */
+	uint32_t task3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_2 */
+	uint32_t task2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_1 */
+	uint32_t task1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_0 */
+	uint32_t task0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_TASKLSB ;
+#else
+typedef struct
+{	uint32_t task0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_0 */
+	uint32_t r1   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_1 */
+	uint32_t r2   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_2 */
+	uint32_t r3   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_3 */
+	uint32_t r4   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_TASKLSB ;
+#endif
+
+/*****************************************************************************************/
+/* Task_numbers_MSB                                                                      */
+/* The BBH manages 40 queues for GPON or 32 queues for EPON.  Each of the first 8 Queues */
+/*  may have a unique Runner task number.  Queues 8-39 have all the same configurable ta */
+/* sk number.  This register defines the tasks for Queues 4-7.  For Ethernet queue 0 sho */
+/* uld be configured.                                                                    */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_TASKMSB_R4_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_R4_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_TASK7_TASK_NUMBER_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_TASK7_TASK_NUMBER_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_R3_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_R3_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_TASK6_TASK_NUMBER_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_TASK6_TASK_NUMBER_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_R2_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_R2_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_TASK5_TASK_NUMBER_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_TASK5_TASK_NUMBER_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_R1_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_R1_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_TASK4_TASK_NUMBER_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_TASK4_TASK_NUMBER_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_TASKMSB_OFFSET ( 0x00000014 )
+
+#define BBH_TX_0_CONFIGURATIONS_TASKMSB_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKMSB_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_TASKMSB_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKMSB_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_TASKMSB_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKMSB_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_TASKMSB_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKMSB_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_TASKMSB_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKMSB_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_TASKMSB_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKMSB_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_TASKMSB_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKMSB_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_TASKMSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_TASKMSB_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_TASKMSB_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_TASKMSB_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_TASKMSB_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_TASKMSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_7 */
+	uint32_t task7	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_6 */
+	uint32_t task6	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_5 */
+	uint32_t task5	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_4 */
+	uint32_t task4	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_TASKMSB ;
+#else
+typedef struct
+{	uint32_t task4	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_4 */
+	uint32_t r1   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task5	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_5 */
+	uint32_t r2   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task6	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_6 */
+	uint32_t r3   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task7	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_7 */
+	uint32_t r4   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_TASKMSB ;
+#endif
+
+/*****************************************************************************************/
+/* Task_numbers_8-39                                                                     */
+/* The BBH manages 40 queues for GPON or 32 queues for EPON.  Each of the first 8 Queues */
+/*  may have a unique Runner task number.  Queues 8-39 have all the same configurable ta */
+/* sk number.  This register defines the tasks for Queues 8-39.  For Ethernet queue 0 sh */
+/* ould be configured.                                                                   */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_TASK8_39_R1_DEFAULT_VALUE                       ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASK8_39_R1_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASK8_39_TASK8_39_TASK_NUMBER_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TASK8_39_TASK8_39_TASK_NUMBER_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_TASK8_39_OFFSET ( 0x00000018 )
+
+#define BBH_TX_0_CONFIGURATIONS_TASK8_39_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASK8_39_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_TASK8_39_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASK8_39_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_TASK8_39_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASK8_39_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_TASK8_39_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASK8_39_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_TASK8_39_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASK8_39_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_TASK8_39_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASK8_39_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_TASK8_39_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASK8_39_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_TASK8_39_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_TASK8_39_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_TASK8_39_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_TASK8_39_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_TASK8_39_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_TASK8_39_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1      	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_8-39 */
+	uint32_t task8_39	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_TASK8_39 ;
+#else
+typedef struct
+{	uint32_t task8_39	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_8-39 */
+	uint32_t r1      	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_TASK8_39 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO_size_0_7                                                                      */
+/* The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per TCONT/LLID). For  */
+/* each queue it manages a PD FIFO.   A total of 128 PDs (GPON) or 256 PDs (EPON) are av */
+/* ailable for all queues.   For each Queue the SW configures the base and the size with */
+/* in these 128/256 PDs.  This register defines the PD FIFO size for queues 0-7.  For Et */
+/* hernet queue 0 should be configured.                                                  */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE7_MAX_GPON_VALUE                 ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE7_DEFAULT_GPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE7_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE7_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE7_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE7_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE6_MAX_GPON_VALUE                 ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE6_DEFAULT_GPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE6_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE6_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE6_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE6_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE5_MAX_GPON_VALUE                 ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE5_DEFAULT_GPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE5_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE5_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE5_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE5_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE4_MAX_GPON_VALUE                 ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE4_DEFAULT_GPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE4_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE4_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE4_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE4_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE3_MAX_GPON_VALUE                 ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE3_DEFAULT_GPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE3_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE3_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE3_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE3_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE2_MAX_GPON_VALUE                 ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE2_DEFAULT_GPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE2_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE2_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE2_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE2_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE1_MAX_GPON_VALUE                 ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE1_DEFAULT_GPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE1_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE1_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE1_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE1_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE0_MAX_GPON_VALUE                 ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE0_DEFAULT_GPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE0_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE0_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE0_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_FIFOSIZE0_MAX_EPON_VALUE                 ( 0xF )
+
+
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_OFFSET ( 0x0000001C )
+
+#define BBH_TX_0_CONFIGURATIONS_PDSIZE0_7_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE0_7_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_PDSIZE0_7_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_PDSIZE0_7_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_PDSIZE0_7_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE0_7_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_PDSIZE0_7_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_PDSIZE0_7_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_PDSIZE0_7_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE0_7_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_PDSIZE0_7_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_PDSIZE0_7_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_PDSIZE0_7_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE0_7_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_PDSIZE0_7_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_PDSIZE0_7_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_PDSIZE0_7_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE0_7_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_PDSIZE0_7_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_PDSIZE0_7_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_PDSIZE0_7_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE0_7_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_PDSIZE0_7_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_PDSIZE0_7_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_PDSIZE0_7_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE0_7_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_PDSIZE0_7_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_PDSIZE0_7_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_PDSIZE0_7_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_PDSIZE0_7_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_PDSIZE0_7_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_PDSIZE0_7_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* FIFO_size_7 */
+	uint32_t fifosize7	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_6 */
+	uint32_t fifosize6	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_5 */
+	uint32_t fifosize5	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_4 */
+	uint32_t fifosize4	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_3 */
+	uint32_t fifosize3	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_2 */
+	uint32_t fifosize2	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_1 */
+	uint32_t fifosize1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_0 */
+	uint32_t fifosize0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDSIZE0_7 ;
+#else
+typedef struct
+{	uint32_t fifosize0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_0 */
+	uint32_t fifosize1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_1 */
+	uint32_t fifosize2	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_2 */
+	uint32_t fifosize3	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_3 */
+	uint32_t fifosize4	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_4 */
+	uint32_t fifosize5	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_5 */
+	uint32_t fifosize6	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_6 */
+	uint32_t fifosize7	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_7 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDSIZE0_7 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO_size_8_39                                                                     */
+/* The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per queue). For each  */
+/* queue it manages a PD FIFO.   A total of 128 PDs for GPON and 256 PDs for EPON are av */
+/* ailable for all queues.   For each Queue the SW configures the base and the size with */
+/* in these 128/256 PDs.  This register defines the PD FIFO size for TCONTs 8-39.        */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_R3_DEFAULT_VALUE                             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_R3_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE32_39_MAX_EPON_VALUE                 ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE32_39_DEFAULT_EPON_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE32_39_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE32_39_DEFAULT_GPON_VALUE             ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE32_39_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE32_39_MAX_GPON_VALUE                 ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE24_31_DEFAULT_GPON_VALUE             ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE24_31_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE24_31_DEFAULT_EPON_VALUE             ( 0x4 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE24_31_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x4 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE24_31_MAX_GPON_VALUE                 ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE24_31_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE16_23_DEFAULT_GPON_VALUE             ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE16_23_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE16_23_DEFAULT_EPON_VALUE             ( 0x4 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE16_23_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x4 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE16_23_MAX_GPON_VALUE                 ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE16_23_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE8_15_DEFAULT_GPON_VALUE              ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE8_15_DEFAULT_GPON_VALUE_RESET_VALUE  ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE8_15_DEFAULT_EPON_VALUE              ( 0x4 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE8_15_DEFAULT_EPON_VALUE_RESET_VALUE  ( 0x4 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE8_15_MAX_GPON_VALUE                  ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_FIFOSIZE8_15_MAX_EPON_VALUE                  ( 0xF )
+
+
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_OFFSET ( 0x00000020 )
+
+#define BBH_TX_0_CONFIGURATIONS_PDSIZE8_39_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE8_39_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_PDSIZE8_39_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_PDSIZE8_39_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_PDSIZE8_39_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE8_39_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_PDSIZE8_39_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_PDSIZE8_39_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_PDSIZE8_39_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE8_39_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_PDSIZE8_39_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_PDSIZE8_39_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_PDSIZE8_39_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE8_39_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_PDSIZE8_39_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_PDSIZE8_39_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_PDSIZE8_39_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE8_39_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_PDSIZE8_39_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_PDSIZE8_39_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_PDSIZE8_39_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE8_39_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_PDSIZE8_39_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_PDSIZE8_39_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_PDSIZE8_39_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE8_39_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_PDSIZE8_39_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_PDSIZE8_39_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_PDSIZE8_39_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_PDSIZE8_39_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_PDSIZE8_39_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_PDSIZE8_39_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r3           	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_32_39 */
+	uint32_t fifosize32_39	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_24_31 */
+	uint32_t fifosize24_31	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_16_23 */
+	uint32_t fifosize16_23	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_8_15 */
+	uint32_t fifosize8_15 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDSIZE8_39 ;
+#else
+typedef struct
+{	uint32_t fifosize8_15 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_8_15 */
+	uint32_t fifosize16_23	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_16_23 */
+	uint32_t fifosize24_31	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_24_31 */
+	uint32_t fifosize32_39	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_32_39 */
+	uint32_t r3           	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDSIZE8_39 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO_base_0_3                                                                      */
+/* The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each TCONT/LLID). For  */
+/* each queue it manages a PD FIFO.   A total of 128 PDs (GPON) or 256 (EPON) are availa */
+/* ble for all queues.   For each Queue the SW configures the base and the size within t */
+/* hese 128/256 PDs.  This register defines the PD FIFO base for TCONTs 0-3.  This confi */
+/* guration is irrelevant for Ethernet.                                                  */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE3_DEFAULT_GPON_VALUE             ( 0x18 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE3_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x18 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE3_DEFAULT_EPON_VALUE             ( 0x30 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE3_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x30 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE3_MAX_GPON_VALUE                 ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE3_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE2_DEFAULT_GPON_VALUE             ( 0x10 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE2_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x10 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE2_DEFAULT_EPON_VALUE             ( 0x20 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE2_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x20 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE2_MAX_GPON_VALUE                 ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE2_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE1_DEFAULT_GPON_VALUE             ( 0x8 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE1_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x8 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE1_DEFAULT_EPON_VALUE             ( 0x10 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE1_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x10 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE1_MAX_GPON_VALUE                 ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE1_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE0_DEFAULT_EPON_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE0_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE0_DEFAULT_GPON_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE0_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE0_MAX_GPON_VALUE                 ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_FIFOBASE0_MAX_EPON_VALUE                 ( 0xFF )
+
+
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_OFFSET ( 0x00000024 )
+
+#define BBH_TX_0_CONFIGURATIONS_PDBASE0_3_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE0_3_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_PDBASE0_3_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE0_3_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_PDBASE0_3_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE0_3_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_PDBASE0_3_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE0_3_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_PDBASE0_3_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE0_3_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_PDBASE0_3_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE0_3_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_PDBASE0_3_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE0_3_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_PDBASE0_3_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_PDBASE0_3_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_PDBASE0_3_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_PDBASE0_3_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* FIFO_base_3 */
+	uint32_t fifobase3	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_2 */
+	uint32_t fifobase2	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_1 */
+	uint32_t fifobase1	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_0 */
+	uint32_t fifobase0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDBASE0_3 ;
+#else
+typedef struct
+{	uint32_t fifobase0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_0 */
+	uint32_t fifobase1	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_1 */
+	uint32_t fifobase2	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_2 */
+	uint32_t fifobase3	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_3 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDBASE0_3 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO_base_4_7                                                                      */
+/* The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each TCONT/LLID). For  */
+/* each queue it manages a PD FIFO.   A total of 128 PDs (GPON) or 256 (EPON) are availa */
+/* ble for all queues.   For each Queue the SW configures the base and the size within t */
+/* hese 128/256 PDs.  This register defines the PD FIFO base for TCONTs 4-7.  This confi */
+/* guration is irrelevant for Ethernet.                                                  */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE7_DEFAULT_GPON_VALUE             ( 0x38 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE7_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x38 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE7_DEFAULT_EPON_VALUE             ( 0x70 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE7_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x70 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE7_MAX_GPON_VALUE                 ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE7_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE6_DEFAULT_GPON_VALUE             ( 0x30 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE6_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x30 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE6_DEFAULT_EPON_VALUE             ( 0x60 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE6_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x60 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE6_MAX_GPON_VALUE                 ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE6_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE5_DEFAULT_GPON_VALUE             ( 0x28 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE5_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x28 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE5_DEFAULT_EPON_VALUE             ( 0x50 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE5_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x50 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE5_MAX_GPON_VALUE                 ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE5_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE4_DEFAULT_GPON_VALUE             ( 0x20 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE4_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x20 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE4_DEFAULT_EPON_VALUE             ( 0x40 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE4_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x40 )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE4_MAX_GPON_VALUE                 ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_FIFOBASE4_MAX_EPON_VALUE                 ( 0xFF )
+
+
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_OFFSET ( 0x00000028 )
+
+#define BBH_TX_0_CONFIGURATIONS_PDBASE4_7_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE4_7_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_PDBASE4_7_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE4_7_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_PDBASE4_7_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE4_7_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_PDBASE4_7_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE4_7_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_PDBASE4_7_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE4_7_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_PDBASE4_7_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE4_7_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_PDBASE4_7_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE4_7_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_PDBASE4_7_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_PDBASE4_7_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_PDBASE4_7_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_PDBASE4_7_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* FIFO_base_7 */
+	uint32_t fifobase7	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_6 */
+	uint32_t fifobase6	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_5 */
+	uint32_t fifobase5	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_4 */
+	uint32_t fifobase4	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDBASE4_7 ;
+#else
+typedef struct
+{	uint32_t fifobase4	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_4 */
+	uint32_t fifobase5	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_5 */
+	uint32_t fifobase6	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_6 */
+	uint32_t fifobase7	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_7 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDBASE4_7 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO_base_8_39                                                                     */
+/* The BBH manages 40 queues (GPON) or 32 queus (EPON). For each queue it manages a PD F */
+/* IFO.   A total of 128 PDs (GPON) or 256 PDs (EPON) are available for all queues.   Fo */
+/* r each Queue the SW configures the base and the size within these 128/256 PDs.  This  */
+/* register defines the PD FIFO base for queues 8-39.  This configuration is irrelevant  */
+/* for Ethernet.                                                                         */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE32_39_DEFAULT_EPON_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE32_39_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE32_39_MAX_EPON_VALUE                 ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE32_39_DEFAULT_GPON_VALUE             ( 0x70 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE32_39_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x70 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE32_39_MAX_GPON_VALUE                 ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE24_31_DEFAULT_GPON_VALUE             ( 0x60 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE24_31_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x60 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE24_31_MAX_GPON_VALUE                 ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE24_31_DEFAULT_EPON_VALUE             ( 0xD0 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE24_31_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xD0 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE24_31_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE16_23_DEFAULT_GPON_VALUE             ( 0x50 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE16_23_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x50 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE16_23_MAX_GPON_VALUE                 ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE16_23_DEFAULT_EPON_VALUE             ( 0xA8 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE16_23_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xA8 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE16_23_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE8_15_DEFAULT_GPON_VALUE              ( 0x40 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE8_15_DEFAULT_GPON_VALUE_RESET_VALUE  ( 0x40 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE8_15_MAX_GPON_VALUE                  ( 0x7F )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE8_15_DEFAULT_EPON_VALUE              ( 0x80 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE8_15_DEFAULT_EPON_VALUE_RESET_VALUE  ( 0x80 )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_FIFOBASE8_15_MAX_EPON_VALUE                  ( 0xFF )
+
+
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_OFFSET ( 0x0000002C )
+
+#define BBH_TX_0_CONFIGURATIONS_PDBASE8_39_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE8_39_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_PDBASE8_39_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE8_39_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_PDBASE8_39_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE8_39_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_PDBASE8_39_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE8_39_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_PDBASE8_39_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE8_39_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_PDBASE8_39_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE8_39_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_PDBASE8_39_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE8_39_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_PDBASE8_39_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_PDBASE8_39_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_PDBASE8_39_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_PDBASE8_39_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* FIFO_base_32_39 */
+	uint32_t fifobase32_39	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_24_31 */
+	uint32_t fifobase24_31	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_16_23 */
+	uint32_t fifobase16_23	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_8_15 */
+	uint32_t fifobase8_15 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDBASE8_39 ;
+#else
+typedef struct
+{	uint32_t fifobase8_15 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_8_15 */
+	uint32_t fifobase16_23	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_16_23 */
+	uint32_t fifobase24_31	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_24_31 */
+	uint32_t fifobase32_39	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_32_39 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDBASE8_39 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_bytes_threshold_EN                                                                 */
+/* The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO.  The PDs pre */
+/*  fetch is limited either by the PD FIFO configurable size or according to the total n */
+/* umber of bytes (deducting bytes already requested/transmitted) for preventing HOL. Fu */
+/* ll configuration for the first 8 TCONT and one configuration per group of 8 TCONTs fo */
+/* r the rest.                                                                           */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED1_DEFAULT_VALUE                      ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED1_DEFAULT_VALUE_RESET_VALUE          ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_PD_LIMIT_DISABLE_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_PD_LIMIT_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_PD_LIMIT_ENABLE_VALUE              ( 0x1 )
+
+
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_OFFSET ( 0x00000030 )
+
+#define BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_enable */
+	uint32_t pdlimiten	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN ;
+#else
+typedef struct
+{	uint32_t pdlimiten	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_enable */
+	uint32_t reserved1	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN ;
+#endif
+
+/*****************************************************************************************/
+/* PD_bytes_threshold                                                                    */
+/* The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO.  The PDs pre */
+/*  fetch is limited either by the PD FIFO configurable size or according to the total n */
+/* umber of bytes (deducting bytes already requested/transmitted) for preventing HOL. Fu */
+/* ll configuration for the first 8 TCONT and one configuration for the rest (TCONTs 8-3 */
+/* 9).  Registers 0-3 define the configuration for the first 8 TCONT and register 4 defi */
+/* nes the configuration for TCONTs 8-39 (in the even field).                            */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_R2_RESET_VALUE_VALUE                  ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_R2_RESET_VALUE_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_PDLIMITEVEN_DEFAULT_VALUE             ( 0x180 )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_PDLIMITEVEN_DEFAULT_VALUE_RESET_VALUE ( 0x180 )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_R1_RESET_VALUE_VALUE                  ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_R1_RESET_VALUE_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_PDLIMITODD_DEFAULT_VALUE              ( 0x180 )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_PDLIMITODD_DEFAULT_VALUE_RESET_VALUE  ( 0x180 )
+
+
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_OFFSET ( 0x00000034 )
+
+#define BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_ADDRESS        	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_ADDRESS        	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_ADDRESS        	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_ADDRESS        	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_ADDRESS        	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_ADDRESS        	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_ADDRESS        	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_PD_BYTE_TH_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_WRITE( i, k, v )	WRITE_I_32( BBH_TX_CONFIGURATIONS_PD_BYTE_TH_ARRAY [ i ], (k), (v) )
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_READ( i, k, r ) 	READ_I_32( BBH_TX_CONFIGURATIONS_PD_BYTE_TH_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2         	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_even */
+	uint32_t pdlimiteven	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1         	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_odd */
+	uint32_t pdlimitodd 	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PD_BYTE_TH ;
+#else
+typedef struct
+{	uint32_t pdlimitodd 	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_odd */
+	uint32_t r1         	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t pdlimiteven	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_even */
+	uint32_t r2         	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PD_BYTE_TH ;
+#endif
+
+/*****************************************************************************************/
+/* DMA_configurations                                                                    */
+/* The BBH reads the packet data from the DDR in chunks (with a maximal size of 128 byte */
+/* s).  For each chunk the BBH writes a read request (descriptor) into the DMA memory sp */
+/* ace. The read descriptors are arranged in a predefined space in the DMA memory and ma */
+/* naged in a cyclic FIFO style.   A special configuration limits the maximum number of  */
+/* read requests.                                                                        */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_R4_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_R4_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_EPNURGNT_NORMAL_VALUE                ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_EPNURGNT_NORMAL_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_EPNURGNT_URGENT_VALUE                ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_R3_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_R3_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_MAXREQ_MIN_VALUE_VALUE               ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_MAXREQ_MAX_VALUE_VALUE               ( 0x8 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_MAXREQ_MAX_VALUE_VALUE_RESET_VALUE   ( 0x8 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_R2_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_R2_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_DESCBASE_DESC_BASE_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_DESCBASE_DESC_BASE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_OFFSET ( 0x0000004C )
+
+#define BBH_TX_0_CONFIGURATIONS_DMACFG_TX_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DMACFG_TX_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_DMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_DMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_DMACFG_TX_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DMACFG_TX_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_DMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_DMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_DMACFG_TX_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DMACFG_TX_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_DMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_DMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_DMACFG_TX_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DMACFG_TX_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_DMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_DMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_DMACFG_TX_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DMACFG_TX_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_DMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_DMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_DMACFG_TX_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DMACFG_TX_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_DMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_DMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_DMACFG_TX_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DMACFG_TX_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_DMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_DMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_DMACFG_TX_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_DMACFG_TX_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_DMACFG_TX_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_DMACFG_TX_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4      	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Epon_read_urgent */
+	uint32_t epnurgnt	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_number_of_requests */
+	uint32_t maxreq  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2      	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Descriptor_FIFO_base */
+	uint32_t descbase	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_DMACFG_TX ;
+#else
+typedef struct
+{	uint32_t descbase	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Descriptor_FIFO_base */
+	uint32_t r2      	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t maxreq  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_number_of_requests */
+	uint32_t r3      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t epnurgnt	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Epon_read_urgent */
+	uint32_t r4      	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_DMACFG_TX ;
+#endif
+
+/*****************************************************************************************/
+/* SDMA_configurations                                                                   */
+/* The BBH reads the packet data from the SRAM in a fixed size chunks (128 bytes).  For  */
+/* each chunk the BBH writes a read request (descriptor) into the SDMA memory space. The */
+/*  read descriptors are arranged in a predefined space in the SDMA memory and managed i */
+/* n a cyclic FIFO style.   A special configuration limits the maximum number of read re */
+/* quests.  This register is relevalt only for Ethernet.                                 */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_R2_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_R2_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_MAXREQ_MIN_VALUE_VALUE               ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_MAXREQ_MAX_VALUE_VALUE               ( 0x4 )
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_MAXREQ_MAX_VALUE_VALUE_RESET_VALUE   ( 0x4 )
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_R1_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_R1_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_DESCBASE_DESC_BASE_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_DESCBASE_DESC_BASE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_OFFSET ( 0x00000050 )
+
+#define BBH_TX_0_CONFIGURATIONS_SDMACFG_TX_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SDMACFG_TX_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_SDMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_SDMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_SDMACFG_TX_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SDMACFG_TX_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_SDMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_SDMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_SDMACFG_TX_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SDMACFG_TX_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_SDMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_SDMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_SDMACFG_TX_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SDMACFG_TX_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_SDMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_SDMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_SDMACFG_TX_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SDMACFG_TX_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_SDMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_SDMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_SDMACFG_TX_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SDMACFG_TX_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_SDMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_SDMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_SDMACFG_TX_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SDMACFG_TX_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_SDMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_SDMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_SDMACFG_TX_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_SDMACFG_TX_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_SDMACFG_TX_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_SDMACFG_TX_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2      	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_number_of_requests */
+	uint32_t maxreq  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1      	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Descriptor_FIFO_base */
+	uint32_t descbase	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_SDMACFG_TX ;
+#else
+typedef struct
+{	uint32_t descbase	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Descriptor_FIFO_base */
+	uint32_t r1      	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t maxreq  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_number_of_requests */
+	uint32_t r2      	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_SDMACFG_TX ;
+#endif
+
+/*****************************************************************************************/
+/* Runner_configurations                                                                 */
+/* TCONT address:  The BBH requests a Packet descriptor from the Runner. The BBH sends a */
+/*  wake-up request to the Runner (for a new PD). The wake-up request is written to addr */
+/* ess 0x8000 in the Runner.    In the case of GPON peripheral the BBH writes the TCONT  */
+/* number in a predefined address at the Runner SRAM and then sends a wake-up request to */
+/*  the Runner.   This register defines the TCONT address within the Runner address spac */
+/* e.  SKB address:  When the packet is transmitted from absolute address, then, instead */
+/*  of releasing the BN, the BBH writes a 6 bits read counter into the Runner SRAM. It w */
+/* rites it into a pre-defined address + TCONT_NUM (for Ethernet TCONT_NUM = 0).  This r */
+/* egister defines the SKB free base address within the Runner address                   */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_RUNNERCFG_SKBADDR_SKB_ADDRESS_VALUE                 ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_RUNNERCFG_SKBADDR_SKB_ADDRESS_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_RUNNERCFG_TCONTADDR_TCONT_ADDRESS_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_RUNNERCFG_TCONTADDR_TCONT_ADDRESS_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_RUNNERCFG_OFFSET ( 0x00000054 )
+
+#define BBH_TX_0_CONFIGURATIONS_RUNNERCFG_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_RUNNERCFG_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_RUNNERCFG_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_RUNNERCFG_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_RUNNERCFG_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_RUNNERCFG_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_RUNNERCFG_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_RUNNERCFG_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_RUNNERCFG_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_RUNNERCFG_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_RUNNERCFG_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_RUNNERCFG_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_RUNNERCFG_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_RUNNERCFG_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_RUNNERCFG_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_RUNNERCFG_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_RUNNERCFG_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_RUNNERCFG_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_RUNNERCFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* SKB_address */
+	uint32_t skbaddr  	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TCONT_address */
+	uint32_t tcontaddr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_RUNNERCFG ;
+#else
+typedef struct
+{	uint32_t tcontaddr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TCONT_address */
+	uint32_t skbaddr  	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SKB_address */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_RUNNERCFG ;
+#endif
+
+/*****************************************************************************************/
+/* MDU_CFG                                                                               */
+/* The BBH supports a special configurable mode to enable a faster packet bridging (for  */
+/* EMAC and EPON only):  -There will be a special configurable mode for transferring the */
+/*  PD from the Runner into the BBH TX (for downstream only).   -The Runner wont ACK the */
+/*  BBH; therefore the BBH wont wake the TX task.   -The Runner will push the PDs into t */
+/* he BBH (without any wakeup from the BBH).   -Each time that the BBH reads a PD from t */
+/* he PD FIFO, it will write the read pointer into a pre-defined address in the Runner ( */
+/* enable by configuration). The pointer is 6 bits width (one bit larger than needed to  */
+/* distinguish between full and empty).  -The Runner should manage the congestion over t */
+/* he PD FIFO (in the BBH) by reading the BBH read pointer prior to each PD write.   -PD */
+/*  drop should be done by the Runner only. The BBH will drop PD when the FIFO is full a */
+/* nd will count each drop. The BBH wont release the BN in this case.  FOR EMAC BBH, a p */
+/* re PD FIFO of 32 entries is added (no change of the first BN FIFO).    For EPON BBH,  */
+/* there will be a full threshold, which can be smaller than the actual size of the FIFO */
+/* . When the BBH will move from full to not full state, the BBH will wakeup the Runner. */
+/*                                                                                       */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_MDUMODE_PTRADDR_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_MDUMODE_PTRADDR_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_MDUMODE_R1_RESET_VALUE_VALUE                  ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_MDUMODE_R1_RESET_VALUE_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_MDUMODE_MDUEN_DIS_VALUE                       ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_MDUMODE_MDUEN_DIS_VALUE_RESET_VALUE           ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_MDUMODE_MDUEN_EN_VALUE                        ( 0x1 )
+
+
+#define BBH_TX_CONFIGURATIONS_MDUMODE_OFFSET ( 0x00000058 )
+
+#define BBH_TX_0_CONFIGURATIONS_MDUMODE_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MDUMODE_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_MDUMODE_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MDUMODE_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_MDUMODE_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MDUMODE_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_MDUMODE_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MDUMODE_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_MDUMODE_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MDUMODE_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_MDUMODE_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MDUMODE_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_MDUMODE_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MDUMODE_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_MDUMODE_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_MDUMODE_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_MDUMODE_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_MDUMODE_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_MDUMODE_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_MDUMODE_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PTRADDR */
+	uint32_t ptraddr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MDU_EN */
+	uint32_t mduen  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_MDUMODE ;
+#else
+typedef struct
+{	uint32_t mduen  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MDU_EN */
+	uint32_t r1     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t ptraddr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PTRADDR */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_MDUMODE ;
+#endif
+
+/*****************************************************************************************/
+/* DDR_TM_BASE                                                                           */
+/* The BBH calculate the DDR physical address according to the Buffer number and buffer  */
+/* size and then adds the DDR TM base.  The value of this register should match the rele */
+/* vant registers value in the BBH RX and in the Runner.                                 */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_DDRTMBASE_DDRTMBASE_DDR_TM_BASE_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DDRTMBASE_DDRTMBASE_DDR_TM_BASE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_DDRTMBASE_OFFSET ( 0x0000005C )
+
+#define BBH_TX_0_CONFIGURATIONS_DDRTMBASE_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRTMBASE_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_DDRTMBASE_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_DDRTMBASE_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_DDRTMBASE_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRTMBASE_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_DDRTMBASE_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_DDRTMBASE_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_DDRTMBASE_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRTMBASE_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_DDRTMBASE_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_DDRTMBASE_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_DDRTMBASE_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRTMBASE_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_DDRTMBASE_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_DDRTMBASE_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_DDRTMBASE_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRTMBASE_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_DDRTMBASE_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_DDRTMBASE_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_DDRTMBASE_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRTMBASE_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_DDRTMBASE_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_DDRTMBASE_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_DDRTMBASE_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRTMBASE_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_DDRTMBASE_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_DDRTMBASE_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_DDRTMBASE_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_DDRTMBASE_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_DDRTMBASE_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_DDRTMBASE_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_DDRTMBASE_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DDR_TM_BASE */
+	uint32_t ddrtmbase	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_DDRTMBASE ;
+#else
+typedef struct
+{	uint32_t ddrtmbase	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_TM_BASE */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_DDRTMBASE ;
+#endif
+
+/*****************************************************************************************/
+/* Debug_select                                                                          */
+/* This register selects 1 of 8 debug vectors.  The selected vector is reflected to DBGO */
+/* UTREG.                                                                                */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_DBGSEL_R1_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DBGSEL_R1_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DBGSEL_DBGSEL_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_DBGSEL_DBGSEL_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_DBGSEL_OFFSET ( 0x00000060 )
+
+#define BBH_TX_0_CONFIGURATIONS_DBGSEL_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DBGSEL_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_DBGSEL_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_DBGSEL_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_DBGSEL_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_DBGSEL_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_DBGSEL_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DBGSEL_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_DBGSEL_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_DBGSEL_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_DBGSEL_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_DBGSEL_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_DBGSEL_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DBGSEL_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_DBGSEL_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_DBGSEL_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_DBGSEL_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_DBGSEL_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_DBGSEL_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DBGSEL_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_DBGSEL_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_DBGSEL_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_DBGSEL_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_DBGSEL_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_DBGSEL_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DBGSEL_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_DBGSEL_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_DBGSEL_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_DBGSEL_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_DBGSEL_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_DBGSEL_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DBGSEL_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_DBGSEL_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_DBGSEL_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_DBGSEL_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_DBGSEL_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_DBGSEL_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DBGSEL_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_DBGSEL_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_DBGSEL_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_DBGSEL_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_DBGSEL_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_DBGSEL_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_DBGSEL_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_DBGSEL_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_DBGSEL_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_DBGSEL_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1    	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* debug_select */
+	uint32_t dbgsel	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_DBGSEL ;
+#else
+typedef struct
+{	uint32_t dbgsel	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* debug_select */
+	uint32_t r1    	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_DBGSEL ;
+#endif
+
+/*****************************************************************************************/
+/* TX_reset_command                                                                      */
+/* This register enables reset of internal units (for possible WA purposes).             */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_R1_DEFAULT_VALUE                       ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_R1_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_REQFIFORST_NO_RESET_VALUE              ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_REQFIFORST_NO_RESET_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_REQFIFORST_RESET_VALUE                 ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_STSFIFORST_NO_RESET_VALUE              ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_STSFIFORST_NO_RESET_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_STSFIFORST_RESET_VALUE                 ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_NO_RESET_VALUE               ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_NO_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_RESET_VALUE                  ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_NO_RESET_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_NO_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_RESET_VALUE                ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_NO_RESET_VALUE              ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_NO_RESET_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_RESET_VALUE                 ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_OKFIFORST_NO_RESET_VALUE               ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_OKFIFORST_NO_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_OKFIFORST_RESET_VALUE                  ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_NO_RESET_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_NO_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_RESET_VALUE                ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_NO_RESET_VALUE              ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_NO_RESET_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_RESET_VALUE                 ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_NO_RESET_VALUE              ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_NO_RESET_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_RESET_VALUE                 ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_NO_RESET_VALUE               ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_NO_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_RESET_VALUE                  ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_PDFIFORST_NO_RESET_VALUE               ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_PDFIFORST_NO_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_PDFIFORST_RESET_VALUE                  ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_CNTXTRST_NO_RESET_VALUE                ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_CNTXTRST_NO_RESET_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_CNTXTRST_RESET_VALUE                   ( 0x1 )
+
+
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_OFFSET ( 0x00000064 )
+
+#define BBH_TX_0_CONFIGURATIONS_TXRSTCMD_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TXRSTCMD_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_TXRSTCMD_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_TXRSTCMD_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_TXRSTCMD_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TXRSTCMD_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_TXRSTCMD_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_TXRSTCMD_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_TXRSTCMD_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TXRSTCMD_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_TXRSTCMD_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_TXRSTCMD_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_TXRSTCMD_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TXRSTCMD_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_TXRSTCMD_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_TXRSTCMD_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_TXRSTCMD_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TXRSTCMD_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_TXRSTCMD_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_TXRSTCMD_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_TXRSTCMD_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TXRSTCMD_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_TXRSTCMD_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_TXRSTCMD_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_TXRSTCMD_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TXRSTCMD_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_TXRSTCMD_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_TXRSTCMD_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_TXRSTCMD_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_TXRSTCMD_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_TXRSTCMD_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_TXRSTCMD_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1         	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* REQ_FIFO_reset */
+	uint32_t reqfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* STS_FIFOs_reset */
+	uint32_t stsfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SKB_PTR_reset */
+	uint32_t skbptrrst  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SRAM_FIFO_reset */
+	uint32_t sramfiforst	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_FIFO_reset */
+	uint32_t ddrfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Order_Keeper_FIFO_reset */
+	uint32_t okfiforst  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_FIFO_reset */
+	uint32_t sbpmfiforst	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_FIFO_reset */
+	uint32_t bpmfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA_write_pointer_reset */
+	uint32_t sdmaptrrst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_write_pointer_reset */
+	uint32_t dmaptrrst  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PDs_FIFOs_reset */
+	uint32_t pdfiforst  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_reset */
+	uint32_t cntxtrst   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_TXRSTCMD ;
+#else
+typedef struct
+{	uint32_t cntxtrst   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_reset */
+	uint32_t pdfiforst  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PDs_FIFOs_reset */
+	uint32_t dmaptrrst  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_write_pointer_reset */
+	uint32_t sdmaptrrst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA_write_pointer_reset */
+	uint32_t bpmfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_FIFO_reset */
+	uint32_t sbpmfiforst	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_FIFO_reset */
+	uint32_t okfiforst  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Order_Keeper_FIFO_reset */
+	uint32_t ddrfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_FIFO_reset */
+	uint32_t sramfiforst	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SRAM_FIFO_reset */
+	uint32_t skbptrrst  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SKB_PTR_reset */
+	uint32_t stsfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* STS_FIFOs_reset */
+	uint32_t reqfiforst 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* REQ_FIFO_reset */
+	uint32_t r1         	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_TXRSTCMD ;
+#endif
+
+/*****************************************************************************************/
+/* EMAC1588                                                                              */
+/* EMAC configuration for 1588. An option to force the BBH to wait till the EMAC FIFO is */
+/*  empty before issuing a DMA read command (of a 1588 packet only).  This register is r */
+/* elevant for Ethernet only.                                                            */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_EMAC1588_R1_RESERVED_VALUE                        ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_EMAC1588_R1_RESERVED_VALUE_RESET_VALUE            ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_EMAC1588_EMAC1588_DONTWAITEMPTY_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_EMAC1588_EMAC1588_DONTWAITEMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_EMAC1588_EMAC1588_WAITEMPTY_VALUE                 ( 0x1 )
+
+
+#define BBH_TX_CONFIGURATIONS_EMAC1588_OFFSET ( 0x00000068 )
+
+#define BBH_TX_0_CONFIGURATIONS_EMAC1588_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_EMAC1588_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_EMAC1588_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_EMAC1588_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_EMAC1588_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_EMAC1588_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_EMAC1588_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_EMAC1588_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_EMAC1588_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_EMAC1588_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_EMAC1588_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_EMAC1588_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_EMAC1588_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_EMAC1588_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_EMAC1588_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_EMAC1588_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_EMAC1588_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_EMAC1588_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_EMAC1588_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_EMAC1588_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_EMAC1588_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_EMAC1588_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_EMAC1588_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_EMAC1588_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_EMAC1588_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_EMAC1588_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_EMAC1588_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_EMAC1588_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_EMAC1588_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_EMAC1588_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_EMAC1588_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_EMAC1588_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_EMAC1588_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_EMAC1588_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_EMAC1588_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_EMAC1588_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_EMAC1588_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_EMAC1588_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_EMAC1588_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_EMAC1588_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_EMAC1588_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_EMAC1588_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_EMAC1588_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_EMAC1588_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_EMAC1588_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_EMAC1588_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_EMAC1588_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1      	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC1588 */
+	uint32_t emac1588	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_EMAC1588 ;
+#else
+typedef struct
+{	uint32_t emac1588	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC1588 */
+	uint32_t r1      	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_EMAC1588 ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_configurations                                                                   */
+/* When packet transmission is done, the BBH releases the SBPM buffers.  This register d */
+/* efines which release command is used:  1. Normal free with context  2. Special free w */
+/* ith context  3. free without context                                                  */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_SBPMCFG_R1_RESERVED_VALUE                          ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_SBPMCFG_R1_RESERVED_VALUE_RESET_VALUE              ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_SBPMCFG_SPECIALFREE_NORMAL_VALUE                   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_SBPMCFG_SPECIALFREE_SPECIAL_VALUE                  ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_SBPMCFG_SPECIALFREE_SPECIAL_VALUE_RESET_VALUE      ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_WITH_CONTEXT_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_WITH_CONTEXT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_WITHOUT_CONTEXT_VALUE          ( 0x1 )
+
+
+#define BBH_TX_CONFIGURATIONS_SBPMCFG_OFFSET ( 0x0000006C )
+
+#define BBH_TX_0_CONFIGURATIONS_SBPMCFG_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SBPMCFG_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_SBPMCFG_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_SBPMCFG_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_SBPMCFG_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_SBPMCFG_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_SBPMCFG_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SBPMCFG_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_SBPMCFG_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_SBPMCFG_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_SBPMCFG_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_SBPMCFG_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_SBPMCFG_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SBPMCFG_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_SBPMCFG_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_SBPMCFG_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_SBPMCFG_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_SBPMCFG_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_SBPMCFG_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SBPMCFG_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_SBPMCFG_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_SBPMCFG_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_SBPMCFG_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_SBPMCFG_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_SBPMCFG_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SBPMCFG_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_SBPMCFG_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_SBPMCFG_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_SBPMCFG_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_SBPMCFG_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_SBPMCFG_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SBPMCFG_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_SBPMCFG_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_SBPMCFG_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_SBPMCFG_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_SBPMCFG_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_SBPMCFG_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SBPMCFG_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_SBPMCFG_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_SBPMCFG_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_SBPMCFG_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_SBPMCFG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_SBPMCFG_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_SBPMCFG_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_SBPMCFG_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_SBPMCFG_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_SBPMCFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1         	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Special_free_with_context_en */
+	uint32_t specialfree	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Free_without_context_en */
+	uint32_t freenocntxt	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_SBPMCFG ;
+#else
+typedef struct
+{	uint32_t freenocntxt	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Free_without_context_en */
+	uint32_t specialfree	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Special_free_with_context_en */
+	uint32_t r1         	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_SBPMCFG ;
+#endif
+
+/*****************************************************************************************/
+/* PD_WKUP_THRESH_0_7                                                                    */
+/* The BBH manages 32 queues for EPON (FIFO per LLID). For each queue it manages a PD FI */
+/* FO.   When a FIFO occupancy is above this wakeup threshold, the BBH will not wake-up  */
+/* the Runner for sending a new PD. This threshold does not represent the actual size of */
+/*  the FIFO. If a PD will arrive from the Runner when the FIFO is above the threshold,  */
+/* it will not be dropped unless the FIFO is actually full.  Relevant only for EPON BBH. */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH7_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH7_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH7_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH6_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH6_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH6_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH5_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH5_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH5_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH4_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH4_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH4_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH3_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH3_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH3_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH2_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH2_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH2_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH1_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH1_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH1_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH0_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH0_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WKUPTHRESH0_MAX_EPON_VALUE                 ( 0xF )
+
+
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_OFFSET ( 0x00000070 )
+
+#define BBH_TX_0_CONFIGURATIONS_PDWKUPH0_7_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH0_7_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_PDWKUPH0_7_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_PDWKUPH0_7_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_PDWKUPH0_7_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH0_7_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_PDWKUPH0_7_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_PDWKUPH0_7_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_PDWKUPH0_7_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH0_7_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_PDWKUPH0_7_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_PDWKUPH0_7_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_PDWKUPH0_7_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH0_7_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_PDWKUPH0_7_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_PDWKUPH0_7_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_PDWKUPH0_7_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH0_7_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_PDWKUPH0_7_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_PDWKUPH0_7_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_PDWKUPH0_7_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH0_7_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_PDWKUPH0_7_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_PDWKUPH0_7_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_PDWKUPH0_7_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH0_7_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_PDWKUPH0_7_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_PDWKUPH0_7_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_PDWKUPH0_7_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_PDWKUPH0_7_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH0_7_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_PDWKUPH0_7_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* FIFO_wake_up_threshold_7 */
+	uint32_t wkupthresh7	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_6 */
+	uint32_t wkupthresh6	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_5 */
+	uint32_t wkupthresh5	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_4 */
+	uint32_t wkupthresh4	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_3 */
+	uint32_t wkupthresh3	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_2 */
+	uint32_t wkupthresh2	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_1 */
+	uint32_t wkupthresh1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_0 */
+	uint32_t wkupthresh0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDWKUPH0_7 ;
+#else
+typedef struct
+{	uint32_t wkupthresh0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_0 */
+	uint32_t wkupthresh1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_1 */
+	uint32_t wkupthresh2	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_2 */
+	uint32_t wkupthresh3	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_3 */
+	uint32_t wkupthresh4	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_4 */
+	uint32_t wkupthresh5	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_5 */
+	uint32_t wkupthresh6	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_6 */
+	uint32_t wkupthresh7	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_7 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDWKUPH0_7 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_WKUP_THRESH_8_31                                                                   */
+/* The BBH manages 32 queues for EPON (FIFO per LLID). For each queue it manages a PD FI */
+/* FO.   When a FIFO occupancy is above this wakeup threshold, the BBH will not wake-up  */
+/* the Runner for sending a new PD. This threshold does not represent the actual size of */
+/*  the FIFO. If a PD will arrive from the Runner when the FIFO is above the threshold,  */
+/* it will not be dropped unless the FIFO is actually full.  For queues 8-31, this confi */
+/* guration is per octet.  Relevant only for EPON BBH.                                   */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_R2_DEFAULT_VALUE                               ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_R2_DEFAULT_VALUE_RESET_VALUE                   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_WKUPTHRESH24_31_DEFAULT_EPON_VALUE             ( 0x2 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_WKUPTHRESH24_31_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x2 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_WKUPTHRESH24_31_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_R1_DEFAULT_VALUE                               ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_R1_DEFAULT_VALUE_RESET_VALUE                   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_WKUPTHRESH16_23_DEFAULT_EPON_VALUE             ( 0x2 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_WKUPTHRESH16_23_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x2 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_WKUPTHRESH16_23_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_R0_DEFAULT_VALUE                               ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_R0_DEFAULT_VALUE_RESET_VALUE                   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_WKUPTHRESH8_15_DEFAULT_EPON_VALUE              ( 0x2 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_WKUPTHRESH8_15_DEFAULT_EPON_VALUE_RESET_VALUE  ( 0x2 )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_WKUPTHRESH8_15_MAX_EPON_VALUE                  ( 0xF )
+
+
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_OFFSET ( 0x00000074 )
+
+#define BBH_TX_0_CONFIGURATIONS_PDWKUPH8_31_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH8_31_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_PDWKUPH8_31_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH8_31_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_PDWKUPH8_31_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH8_31_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_PDWKUPH8_31_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH8_31_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_PDWKUPH8_31_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH8_31_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_PDWKUPH8_31_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH8_31_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_PDWKUPH8_31_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH8_31_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_PDWKUPH8_31_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_PDWKUPH8_31_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_PDWKUPH8_31_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_PDWKUPH8_31_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2             	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_24_31 */
+	uint32_t wkupthresh24_31	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_16_23 */
+	uint32_t wkupthresh16_23	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r0             	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_8_15 */
+	uint32_t wkupthresh8_15 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDWKUPH8_31 ;
+#else
+typedef struct
+{	uint32_t wkupthresh8_15 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_8_15 */
+	uint32_t r0             	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t wkupthresh16_23	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_16_23 */
+	uint32_t r1             	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t wkupthresh24_31	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_24_31 */
+	uint32_t r2             	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDWKUPH8_31 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_EMPTY_THRESHOLD                                                                    */
+/* The BBH manages 32 queues for EPON (FIFO per LLID). For each queue it manages a PD FI */
+/* FO. Usually, the BBH orders PDs from the Runner in RR between all queues. In EPON BBH */
+/* , if a FIFO occupancy is below this threshold, the queue will have higher priority in */
+/*  PD ordering arbitration (with RR between all the empty queues).  This configuration  */
+/* is global for all queues.  Relevant only for EPON BBH.                                */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_PDEMPTY_R1_DEFAULT_VALUE                ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDEMPTY_R1_DEFAULT_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDEMPTY_EMPTY_MIN_VALUE                 ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_PDEMPTY_EMPTY_DEFAULT_VALUE             ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_PDEMPTY_EMPTY_DEFAULT_VALUE_RESET_VALUE ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_PDEMPTY_EMPTY_MAX_VALUE                 ( 0xF )
+
+
+#define BBH_TX_CONFIGURATIONS_PDEMPTY_OFFSET ( 0x00000078 )
+
+#define BBH_TX_0_CONFIGURATIONS_PDEMPTY_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDEMPTY_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_PDEMPTY_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDEMPTY_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_PDEMPTY_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDEMPTY_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_PDEMPTY_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDEMPTY_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_PDEMPTY_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDEMPTY_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_PDEMPTY_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDEMPTY_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_PDEMPTY_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDEMPTY_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_PDEMPTY_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_PDEMPTY_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_PDEMPTY_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_PDEMPTY_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_PDEMPTY_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_PDEMPTY_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Empty_thershold */
+	uint32_t empty	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDEMPTY ;
+#else
+typedef struct
+{	uint32_t empty	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Empty_thershold */
+	uint32_t r1   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_PDEMPTY ;
+#endif
+
+/*****************************************************************************************/
+/* ETH_TRANSMIT_TH                                                                       */
+/* This register contains the Transmit threshold configurations for both DDR/PSRAM packe */
+/* ts; packet is transmitted only if the amount of bytes in the TX FIFO is higher or equ */
+/* al to the transmit threshold or if the whole packet is in the TX FIFO                 */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_ETHTT_R3_DEFAULT_VALUE                   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_R3_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_URGENTEN_DISABLE_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_URGENTEN_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_URGENTEN_ENABLE_VALUE              ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_ACCEN_DISABLE_VALUE                ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_ACCEN_DISABLE_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_ACCEN_ENABLE_VALUE                 ( 0x1 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_R1_DEFAULT_VALUE                   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_R1_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_SRAMTT_DEFAULT_VALUE               ( 0x20 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_SRAMTT_DEFAULT_VALUE_RESET_VALUE   ( 0x20 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_R2_DEFAULT_VALUE                   ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_R2_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_DDRTT_DEFAULT_VALUE                ( 0x1C0 )
+#define BBH_TX_CONFIGURATIONS_ETHTT_DDRTT_DEFAULT_VALUE_RESET_VALUE    ( 0x1C0 )
+
+
+#define BBH_TX_CONFIGURATIONS_ETHTT_OFFSET ( 0x0000007C )
+
+#define BBH_TX_0_CONFIGURATIONS_ETHTT_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_ETHTT_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_ETHTT_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_ETHTT_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_ETHTT_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_ETHTT_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_ETHTT_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_ETHTT_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_ETHTT_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_ETHTT_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_ETHTT_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_ETHTT_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_ETHTT_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_ETHTT_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_ETHTT_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_ETHTT_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_ETHTT_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_ETHTT_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_ETHTT_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_ETHTT_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_ETHTT_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_ETHTT_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_ETHTT_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_ETHTT_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_ETHTT_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_ETHTT_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_ETHTT_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_ETHTT_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_ETHTT_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_ETHTT_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_ETHTT_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_ETHTT_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_ETHTT_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_ETHTT_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_ETHTT_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_ETHTT_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_ETHTT_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_ETHTT_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_ETHTT_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_ETHTT_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_ETHTT_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_ETHTT_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_ETHTT_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_ETHTT_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_ETHTT_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_ETHTT_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_ETHTT_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r3      	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* URGENT_EN */
+	uint32_t urgenten	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ACCURATE_REQ_EN */
+	uint32_t accen   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1      	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SRAM_TRANSMIT_TH */
+	uint32_t sramtt  	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2      	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_TRANSMIT_TH */
+	uint32_t ddrtt   	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_ETHTT ;
+#else
+typedef struct
+{	uint32_t ddrtt   	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_TRANSMIT_TH */
+	uint32_t r2      	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t sramtt  	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SRAM_TRANSMIT_TH */
+	uint32_t r1      	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t accen   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ACCURATE_REQ_EN */
+	uint32_t urgenten	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* URGENT_EN */
+	uint32_t r3      	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_ETHTT ;
+#endif
+
+/*****************************************************************************************/
+/* DSL_MAXWLEN                                                                           */
+/* VDSL max word len    relevant only for VDSL BBH                                       */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_MAXWLEN_R1_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_MAXWLEN_R1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_MAXWLEN_MAXWLEN_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_MAXWLEN_MAXWLEN_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_MAXWLEN_OFFSET ( 0x00000080 )
+
+#define BBH_TX_0_CONFIGURATIONS_MAXWLEN_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MAXWLEN_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_MAXWLEN_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_MAXWLEN_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_MAXWLEN_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_MAXWLEN_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_MAXWLEN_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MAXWLEN_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_MAXWLEN_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_MAXWLEN_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_MAXWLEN_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_MAXWLEN_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_MAXWLEN_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MAXWLEN_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_MAXWLEN_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_MAXWLEN_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_MAXWLEN_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_MAXWLEN_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_MAXWLEN_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MAXWLEN_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_MAXWLEN_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_MAXWLEN_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_MAXWLEN_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_MAXWLEN_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_MAXWLEN_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MAXWLEN_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_MAXWLEN_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_MAXWLEN_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_MAXWLEN_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_MAXWLEN_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_MAXWLEN_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MAXWLEN_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_MAXWLEN_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_MAXWLEN_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_MAXWLEN_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_MAXWLEN_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_MAXWLEN_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MAXWLEN_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_MAXWLEN_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_MAXWLEN_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_MAXWLEN_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_MAXWLEN_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_MAXWLEN_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_MAXWLEN_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_MAXWLEN_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_MAXWLEN_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_MAXWLEN_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1     	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* max_word_len */
+	uint32_t maxwlen	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_MAXWLEN ;
+#else
+typedef struct
+{	uint32_t maxwlen	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* max_word_len */
+	uint32_t r1     	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_MAXWLEN ;
+#endif
+
+/*****************************************************************************************/
+/* DSL_FLUSH                                                                             */
+/* VDSL Flush indication    relevant only for VDSL BBH                                   */
+/*****************************************************************************************/
+
+#define BBH_TX_CONFIGURATIONS_FLUSH_R1_DEFAULT_VALUE                ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_FLUSH_R1_DEFAULT_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_FLUSH_FLUSH_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_CONFIGURATIONS_FLUSH_FLUSH_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_CONFIGURATIONS_FLUSH_OFFSET ( 0x00000084 )
+
+#define BBH_TX_0_CONFIGURATIONS_FLUSH_ADDRESS   	( BBH_TX_0_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_FLUSH_OFFSET )
+#define BBH_TX_0_CONFIGURATIONS_FLUSH_READ( r ) 	READ_32( ( BBH_TX_0_CONFIGURATIONS_FLUSH_ADDRESS ), (r) )
+#define BBH_TX_0_CONFIGURATIONS_FLUSH_WRITE( v )	WRITE_32( ( BBH_TX_0_CONFIGURATIONS_FLUSH_ADDRESS ), (v) )
+
+#define BBH_TX_1_CONFIGURATIONS_FLUSH_ADDRESS   	( BBH_TX_1_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_FLUSH_OFFSET )
+#define BBH_TX_1_CONFIGURATIONS_FLUSH_READ( r ) 	READ_32( ( BBH_TX_1_CONFIGURATIONS_FLUSH_ADDRESS ), (r) )
+#define BBH_TX_1_CONFIGURATIONS_FLUSH_WRITE( v )	WRITE_32( ( BBH_TX_1_CONFIGURATIONS_FLUSH_ADDRESS ), (v) )
+
+#define BBH_TX_2_CONFIGURATIONS_FLUSH_ADDRESS   	( BBH_TX_2_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_FLUSH_OFFSET )
+#define BBH_TX_2_CONFIGURATIONS_FLUSH_READ( r ) 	READ_32( ( BBH_TX_2_CONFIGURATIONS_FLUSH_ADDRESS ), (r) )
+#define BBH_TX_2_CONFIGURATIONS_FLUSH_WRITE( v )	WRITE_32( ( BBH_TX_2_CONFIGURATIONS_FLUSH_ADDRESS ), (v) )
+
+#define BBH_TX_3_CONFIGURATIONS_FLUSH_ADDRESS   	( BBH_TX_3_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_FLUSH_OFFSET )
+#define BBH_TX_3_CONFIGURATIONS_FLUSH_READ( r ) 	READ_32( ( BBH_TX_3_CONFIGURATIONS_FLUSH_ADDRESS ), (r) )
+#define BBH_TX_3_CONFIGURATIONS_FLUSH_WRITE( v )	WRITE_32( ( BBH_TX_3_CONFIGURATIONS_FLUSH_ADDRESS ), (v) )
+
+#define BBH_TX_4_CONFIGURATIONS_FLUSH_ADDRESS   	( BBH_TX_4_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_FLUSH_OFFSET )
+#define BBH_TX_4_CONFIGURATIONS_FLUSH_READ( r ) 	READ_32( ( BBH_TX_4_CONFIGURATIONS_FLUSH_ADDRESS ), (r) )
+#define BBH_TX_4_CONFIGURATIONS_FLUSH_WRITE( v )	WRITE_32( ( BBH_TX_4_CONFIGURATIONS_FLUSH_ADDRESS ), (v) )
+
+#define BBH_TX_5_CONFIGURATIONS_FLUSH_ADDRESS   	( BBH_TX_5_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_FLUSH_OFFSET )
+#define BBH_TX_5_CONFIGURATIONS_FLUSH_READ( r ) 	READ_32( ( BBH_TX_5_CONFIGURATIONS_FLUSH_ADDRESS ), (r) )
+#define BBH_TX_5_CONFIGURATIONS_FLUSH_WRITE( v )	WRITE_32( ( BBH_TX_5_CONFIGURATIONS_FLUSH_ADDRESS ), (v) )
+
+#define BBH_TX_6_CONFIGURATIONS_FLUSH_ADDRESS   	( BBH_TX_6_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_FLUSH_OFFSET )
+#define BBH_TX_6_CONFIGURATIONS_FLUSH_READ( r ) 	READ_32( ( BBH_TX_6_CONFIGURATIONS_FLUSH_ADDRESS ), (r) )
+#define BBH_TX_6_CONFIGURATIONS_FLUSH_WRITE( v )	WRITE_32( ( BBH_TX_6_CONFIGURATIONS_FLUSH_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_CONFIGURATIONS_FLUSH_ARRAY [ ] ;
+
+#define BBH_TX_CONFIGURATIONS_FLUSH_WRITE( i, v )	WRITE_32( BBH_TX_CONFIGURATIONS_FLUSH_ARRAY [ i ], (v) )
+#define BBH_TX_CONFIGURATIONS_FLUSH_READ( i, r ) 	READ_32( BBH_TX_CONFIGURATIONS_FLUSH_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1   	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* flush */
+	uint32_t flush	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_FLUSH ;
+#else
+typedef struct
+{	uint32_t flush	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* flush */
+	uint32_t r1   	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS_FLUSH ;
+#endif
+
+/*****************************************************************************************/
+/* SRAM_PD_counter                                                                       */
+/* This counter counts the number of packets which were transmitted from the SRAM.  It c */
+/* ounts the packets for all TCONTs together.  This counter is cleared when read and fre */
+/* ezes when maximum value is reached.  This counter is relevant for Ethernet only.      */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_SRAMPD_SRAMPD_SRAM_PD_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_SRAMPD_SRAMPD_SRAM_PD_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_DEBUG_SRAMPD_OFFSET ( 0x00000000 )
+
+#define BBH_TX_0_DEBUG_SRAMPD_ADDRESS   	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_SRAMPD_OFFSET )
+#define BBH_TX_0_DEBUG_SRAMPD_READ( r ) 	READ_32( ( BBH_TX_0_DEBUG_SRAMPD_ADDRESS ), (r) )
+#define BBH_TX_0_DEBUG_SRAMPD_WRITE( v )	WRITE_32( ( BBH_TX_0_DEBUG_SRAMPD_ADDRESS ), (v) )
+
+#define BBH_TX_1_DEBUG_SRAMPD_ADDRESS   	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_SRAMPD_OFFSET )
+#define BBH_TX_1_DEBUG_SRAMPD_READ( r ) 	READ_32( ( BBH_TX_1_DEBUG_SRAMPD_ADDRESS ), (r) )
+#define BBH_TX_1_DEBUG_SRAMPD_WRITE( v )	WRITE_32( ( BBH_TX_1_DEBUG_SRAMPD_ADDRESS ), (v) )
+
+#define BBH_TX_2_DEBUG_SRAMPD_ADDRESS   	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_SRAMPD_OFFSET )
+#define BBH_TX_2_DEBUG_SRAMPD_READ( r ) 	READ_32( ( BBH_TX_2_DEBUG_SRAMPD_ADDRESS ), (r) )
+#define BBH_TX_2_DEBUG_SRAMPD_WRITE( v )	WRITE_32( ( BBH_TX_2_DEBUG_SRAMPD_ADDRESS ), (v) )
+
+#define BBH_TX_3_DEBUG_SRAMPD_ADDRESS   	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_SRAMPD_OFFSET )
+#define BBH_TX_3_DEBUG_SRAMPD_READ( r ) 	READ_32( ( BBH_TX_3_DEBUG_SRAMPD_ADDRESS ), (r) )
+#define BBH_TX_3_DEBUG_SRAMPD_WRITE( v )	WRITE_32( ( BBH_TX_3_DEBUG_SRAMPD_ADDRESS ), (v) )
+
+#define BBH_TX_4_DEBUG_SRAMPD_ADDRESS   	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_SRAMPD_OFFSET )
+#define BBH_TX_4_DEBUG_SRAMPD_READ( r ) 	READ_32( ( BBH_TX_4_DEBUG_SRAMPD_ADDRESS ), (r) )
+#define BBH_TX_4_DEBUG_SRAMPD_WRITE( v )	WRITE_32( ( BBH_TX_4_DEBUG_SRAMPD_ADDRESS ), (v) )
+
+#define BBH_TX_5_DEBUG_SRAMPD_ADDRESS   	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_SRAMPD_OFFSET )
+#define BBH_TX_5_DEBUG_SRAMPD_READ( r ) 	READ_32( ( BBH_TX_5_DEBUG_SRAMPD_ADDRESS ), (r) )
+#define BBH_TX_5_DEBUG_SRAMPD_WRITE( v )	WRITE_32( ( BBH_TX_5_DEBUG_SRAMPD_ADDRESS ), (v) )
+
+#define BBH_TX_6_DEBUG_SRAMPD_ADDRESS   	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_SRAMPD_OFFSET )
+#define BBH_TX_6_DEBUG_SRAMPD_READ( r ) 	READ_32( ( BBH_TX_6_DEBUG_SRAMPD_ADDRESS ), (r) )
+#define BBH_TX_6_DEBUG_SRAMPD_WRITE( v )	WRITE_32( ( BBH_TX_6_DEBUG_SRAMPD_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_SRAMPD_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_SRAMPD_WRITE( i, v )	WRITE_32( BBH_TX_DEBUG_SRAMPD_ARRAY [ i ], (v) )
+#define BBH_TX_DEBUG_SRAMPD_READ( i, r ) 	READ_32( BBH_TX_DEBUG_SRAMPD_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* SRAM_PD */
+	uint32_t srampd	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_SRAMPD ;
+#else
+typedef struct
+{	uint32_t srampd	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SRAM_PD */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_SRAMPD ;
+#endif
+
+/*****************************************************************************************/
+/* DDR_PD_counter                                                                        */
+/* This counter counts the number of packets which were transmitted from the DDR.  It co */
+/* unts the packets for all TCONTs together.  This counter is cleared when read and free */
+/* zes when maximum value is reached.                                                    */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_DDRPD_DDRPD_DDR_PD_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_DDRPD_DDRPD_DDR_PD_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_DEBUG_DDRPD_OFFSET ( 0x00000004 )
+
+#define BBH_TX_0_DEBUG_DDRPD_ADDRESS   	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_DDRPD_OFFSET )
+#define BBH_TX_0_DEBUG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_0_DEBUG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_0_DEBUG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_0_DEBUG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_1_DEBUG_DDRPD_ADDRESS   	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_DDRPD_OFFSET )
+#define BBH_TX_1_DEBUG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_1_DEBUG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_1_DEBUG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_1_DEBUG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_2_DEBUG_DDRPD_ADDRESS   	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_DDRPD_OFFSET )
+#define BBH_TX_2_DEBUG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_2_DEBUG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_2_DEBUG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_2_DEBUG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_3_DEBUG_DDRPD_ADDRESS   	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_DDRPD_OFFSET )
+#define BBH_TX_3_DEBUG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_3_DEBUG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_3_DEBUG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_3_DEBUG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_4_DEBUG_DDRPD_ADDRESS   	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_DDRPD_OFFSET )
+#define BBH_TX_4_DEBUG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_4_DEBUG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_4_DEBUG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_4_DEBUG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_5_DEBUG_DDRPD_ADDRESS   	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_DDRPD_OFFSET )
+#define BBH_TX_5_DEBUG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_5_DEBUG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_5_DEBUG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_5_DEBUG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_6_DEBUG_DDRPD_ADDRESS   	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_DDRPD_OFFSET )
+#define BBH_TX_6_DEBUG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_6_DEBUG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_6_DEBUG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_6_DEBUG_DDRPD_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_DDRPD_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_DDRPD_WRITE( i, v )	WRITE_32( BBH_TX_DEBUG_DDRPD_ARRAY [ i ], (v) )
+#define BBH_TX_DEBUG_DDRPD_READ( i, r ) 	READ_32( BBH_TX_DEBUG_DDRPD_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DDR_PD */
+	uint32_t ddrpd	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_DDRPD ;
+#else
+typedef struct
+{	uint32_t ddrpd	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_PD */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_DDRPD ;
+#endif
+
+/*****************************************************************************************/
+/* PD_DROP_counter                                                                       */
+/* This counter counts the number of PDs which were dropped due to PD FIFO full.  It cou */
+/* nts the packets for all TCONTs together.  This counter is cleared when read and freez */
+/* es when maximum value is reached.  This counter is relevant for Ethernet only.        */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_PDDROP_R1_RESERVED_VALUE               ( 0x0 )
+#define BBH_TX_DEBUG_PDDROP_R1_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_TX_DEBUG_PDDROP_PDDROP_PDDROP_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_PDDROP_PDDROP_PDDROP_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_DEBUG_PDDROP_OFFSET ( 0x00000008 )
+
+#define BBH_TX_0_DEBUG_PDDROP_ADDRESS   	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_PDDROP_OFFSET )
+#define BBH_TX_0_DEBUG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_0_DEBUG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_0_DEBUG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_0_DEBUG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_1_DEBUG_PDDROP_ADDRESS   	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_PDDROP_OFFSET )
+#define BBH_TX_1_DEBUG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_1_DEBUG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_1_DEBUG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_1_DEBUG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_2_DEBUG_PDDROP_ADDRESS   	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_PDDROP_OFFSET )
+#define BBH_TX_2_DEBUG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_2_DEBUG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_2_DEBUG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_2_DEBUG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_3_DEBUG_PDDROP_ADDRESS   	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_PDDROP_OFFSET )
+#define BBH_TX_3_DEBUG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_3_DEBUG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_3_DEBUG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_3_DEBUG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_4_DEBUG_PDDROP_ADDRESS   	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_PDDROP_OFFSET )
+#define BBH_TX_4_DEBUG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_4_DEBUG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_4_DEBUG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_4_DEBUG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_5_DEBUG_PDDROP_ADDRESS   	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_PDDROP_OFFSET )
+#define BBH_TX_5_DEBUG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_5_DEBUG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_5_DEBUG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_5_DEBUG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_6_DEBUG_PDDROP_ADDRESS   	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_PDDROP_OFFSET )
+#define BBH_TX_6_DEBUG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_6_DEBUG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_6_DEBUG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_6_DEBUG_PDDROP_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_PDDROP_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_PDDROP_WRITE( i, v )	WRITE_32( BBH_TX_DEBUG_PDDROP_ARRAY [ i ], (v) )
+#define BBH_TX_DEBUG_PDDROP_READ( i, r ) 	READ_32( BBH_TX_DEBUG_PDDROP_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1    	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_DROP */
+	uint32_t pddrop	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDDROP ;
+#else
+typedef struct
+{	uint32_t pddrop	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_DROP */
+	uint32_t r1    	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDDROP ;
+#endif
+
+/*****************************************************************************************/
+/* PD_equal_0_counter                                                                    */
+/* This counter counts the number of PDs with packet length equal zero.  It counts the p */
+/* ackets for all TCONTs together.  This counter is cleared when read and freezes when m */
+/* aximum value is reached.                                                              */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_PDEQ0_R1_RESERVED_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_PDEQ0_R1_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_DEBUG_PDEQ0_PDEQ0_PDEQ0_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_PDEQ0_PDEQ0_PDEQ0_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_DEBUG_PDEQ0_OFFSET ( 0x0000000C )
+
+#define BBH_TX_0_DEBUG_PDEQ0_ADDRESS   	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEQ0_OFFSET )
+#define BBH_TX_0_DEBUG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_0_DEBUG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_0_DEBUG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_0_DEBUG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_1_DEBUG_PDEQ0_ADDRESS   	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEQ0_OFFSET )
+#define BBH_TX_1_DEBUG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_1_DEBUG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_1_DEBUG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_1_DEBUG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_2_DEBUG_PDEQ0_ADDRESS   	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEQ0_OFFSET )
+#define BBH_TX_2_DEBUG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_2_DEBUG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_2_DEBUG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_2_DEBUG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_3_DEBUG_PDEQ0_ADDRESS   	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEQ0_OFFSET )
+#define BBH_TX_3_DEBUG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_3_DEBUG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_3_DEBUG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_3_DEBUG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_4_DEBUG_PDEQ0_ADDRESS   	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEQ0_OFFSET )
+#define BBH_TX_4_DEBUG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_4_DEBUG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_4_DEBUG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_4_DEBUG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_5_DEBUG_PDEQ0_ADDRESS   	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEQ0_OFFSET )
+#define BBH_TX_5_DEBUG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_5_DEBUG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_5_DEBUG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_5_DEBUG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_6_DEBUG_PDEQ0_ADDRESS   	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEQ0_OFFSET )
+#define BBH_TX_6_DEBUG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_6_DEBUG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_6_DEBUG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_6_DEBUG_PDEQ0_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_PDEQ0_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_PDEQ0_WRITE( i, v )	WRITE_32( BBH_TX_DEBUG_PDEQ0_ARRAY [ i ], (v) )
+#define BBH_TX_DEBUG_PDEQ0_READ( i, r ) 	READ_32( BBH_TX_DEBUG_PDEQ0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1   	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_equal_0 */
+	uint32_t pdeq0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDEQ0 ;
+#else
+typedef struct
+{	uint32_t pdeq0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_equal_0 */
+	uint32_t r1   	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDEQ0 ;
+#endif
+
+/*****************************************************************************************/
+/* Get_next_is_null_counter                                                              */
+/* This counter counts the number Get next responses with a null BN.  It counts the pack */
+/* ets for all TCONTs together.  This counter is cleared when read and freezes when maxi */
+/* mum value is reached.  This counter is relevant for Ethernet only.                    */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_GETNEXTNULL_R1_RESERVED_VALUE                         ( 0x0 )
+#define BBH_TX_DEBUG_GETNEXTNULL_R1_RESERVED_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_GETNEXTNULL_GETNEXTNULL_GETNEXTNULL_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_GETNEXTNULL_GETNEXTNULL_GETNEXTNULL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_DEBUG_GETNEXTNULL_OFFSET ( 0x00000010 )
+
+#define BBH_TX_0_DEBUG_GETNEXTNULL_ADDRESS   	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTNULL_OFFSET )
+#define BBH_TX_0_DEBUG_GETNEXTNULL_READ( r ) 	READ_32( ( BBH_TX_0_DEBUG_GETNEXTNULL_ADDRESS ), (r) )
+#define BBH_TX_0_DEBUG_GETNEXTNULL_WRITE( v )	WRITE_32( ( BBH_TX_0_DEBUG_GETNEXTNULL_ADDRESS ), (v) )
+
+#define BBH_TX_1_DEBUG_GETNEXTNULL_ADDRESS   	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTNULL_OFFSET )
+#define BBH_TX_1_DEBUG_GETNEXTNULL_READ( r ) 	READ_32( ( BBH_TX_1_DEBUG_GETNEXTNULL_ADDRESS ), (r) )
+#define BBH_TX_1_DEBUG_GETNEXTNULL_WRITE( v )	WRITE_32( ( BBH_TX_1_DEBUG_GETNEXTNULL_ADDRESS ), (v) )
+
+#define BBH_TX_2_DEBUG_GETNEXTNULL_ADDRESS   	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTNULL_OFFSET )
+#define BBH_TX_2_DEBUG_GETNEXTNULL_READ( r ) 	READ_32( ( BBH_TX_2_DEBUG_GETNEXTNULL_ADDRESS ), (r) )
+#define BBH_TX_2_DEBUG_GETNEXTNULL_WRITE( v )	WRITE_32( ( BBH_TX_2_DEBUG_GETNEXTNULL_ADDRESS ), (v) )
+
+#define BBH_TX_3_DEBUG_GETNEXTNULL_ADDRESS   	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTNULL_OFFSET )
+#define BBH_TX_3_DEBUG_GETNEXTNULL_READ( r ) 	READ_32( ( BBH_TX_3_DEBUG_GETNEXTNULL_ADDRESS ), (r) )
+#define BBH_TX_3_DEBUG_GETNEXTNULL_WRITE( v )	WRITE_32( ( BBH_TX_3_DEBUG_GETNEXTNULL_ADDRESS ), (v) )
+
+#define BBH_TX_4_DEBUG_GETNEXTNULL_ADDRESS   	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTNULL_OFFSET )
+#define BBH_TX_4_DEBUG_GETNEXTNULL_READ( r ) 	READ_32( ( BBH_TX_4_DEBUG_GETNEXTNULL_ADDRESS ), (r) )
+#define BBH_TX_4_DEBUG_GETNEXTNULL_WRITE( v )	WRITE_32( ( BBH_TX_4_DEBUG_GETNEXTNULL_ADDRESS ), (v) )
+
+#define BBH_TX_5_DEBUG_GETNEXTNULL_ADDRESS   	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTNULL_OFFSET )
+#define BBH_TX_5_DEBUG_GETNEXTNULL_READ( r ) 	READ_32( ( BBH_TX_5_DEBUG_GETNEXTNULL_ADDRESS ), (r) )
+#define BBH_TX_5_DEBUG_GETNEXTNULL_WRITE( v )	WRITE_32( ( BBH_TX_5_DEBUG_GETNEXTNULL_ADDRESS ), (v) )
+
+#define BBH_TX_6_DEBUG_GETNEXTNULL_ADDRESS   	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTNULL_OFFSET )
+#define BBH_TX_6_DEBUG_GETNEXTNULL_READ( r ) 	READ_32( ( BBH_TX_6_DEBUG_GETNEXTNULL_ADDRESS ), (r) )
+#define BBH_TX_6_DEBUG_GETNEXTNULL_WRITE( v )	WRITE_32( ( BBH_TX_6_DEBUG_GETNEXTNULL_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_GETNEXTNULL_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_GETNEXTNULL_WRITE( i, v )	WRITE_32( BBH_TX_DEBUG_GETNEXTNULL_ARRAY [ i ], (v) )
+#define BBH_TX_DEBUG_GETNEXTNULL_READ( i, r ) 	READ_32( BBH_TX_DEBUG_GETNEXTNULL_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1         	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Get_next_is_null */
+	uint32_t getnextnull	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_GETNEXTNULL ;
+#else
+typedef struct
+{	uint32_t getnextnull	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Get_next_is_null */
+	uint32_t r1         	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_GETNEXTNULL ;
+#endif
+
+/*****************************************************************************************/
+/* PD_Full_LSB                                                                           */
+/* Full indication of the PD FIFOs.                                                      */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_PDFULLLSB_PDFULL_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_PDFULLLSB_PDFULL_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_DEBUG_PDFULLLSB_OFFSET ( 0x00000020 )
+
+#define BBH_TX_0_DEBUG_PDFULLLSB_ADDRESS   	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLLSB_OFFSET )
+#define BBH_TX_0_DEBUG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_0_DEBUG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_0_DEBUG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_0_DEBUG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_1_DEBUG_PDFULLLSB_ADDRESS   	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLLSB_OFFSET )
+#define BBH_TX_1_DEBUG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_1_DEBUG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_1_DEBUG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_1_DEBUG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_2_DEBUG_PDFULLLSB_ADDRESS   	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLLSB_OFFSET )
+#define BBH_TX_2_DEBUG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_2_DEBUG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_2_DEBUG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_2_DEBUG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_3_DEBUG_PDFULLLSB_ADDRESS   	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLLSB_OFFSET )
+#define BBH_TX_3_DEBUG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_3_DEBUG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_3_DEBUG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_3_DEBUG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_4_DEBUG_PDFULLLSB_ADDRESS   	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLLSB_OFFSET )
+#define BBH_TX_4_DEBUG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_4_DEBUG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_4_DEBUG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_4_DEBUG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_5_DEBUG_PDFULLLSB_ADDRESS   	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLLSB_OFFSET )
+#define BBH_TX_5_DEBUG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_5_DEBUG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_5_DEBUG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_5_DEBUG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_6_DEBUG_PDFULLLSB_ADDRESS   	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLLSB_OFFSET )
+#define BBH_TX_6_DEBUG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_6_DEBUG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_6_DEBUG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_6_DEBUG_PDFULLLSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_PDFULLLSB_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_PDFULLLSB_WRITE( i, v )	WRITE_32( BBH_TX_DEBUG_PDFULLLSB_ARRAY [ i ], (v) )
+#define BBH_TX_DEBUG_PDFULLLSB_READ( i, r ) 	READ_32( BBH_TX_DEBUG_PDFULLLSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PD_full */
+	uint32_t pdfull	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDFULLLSB ;
+#else
+typedef struct
+{	uint32_t pdfull	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_full */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDFULLLSB ;
+#endif
+
+/*****************************************************************************************/
+/* PD_Full_MSB                                                                           */
+/* Full indication of the PD FIFOs.                                                      */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_PDFULLMSB_R1_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_TX_DEBUG_PDFULLMSB_R1_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_TX_DEBUG_PDFULLMSB_PDFULL_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_PDFULLMSB_PDFULL_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_DEBUG_PDFULLMSB_OFFSET ( 0x00000024 )
+
+#define BBH_TX_0_DEBUG_PDFULLMSB_ADDRESS   	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLMSB_OFFSET )
+#define BBH_TX_0_DEBUG_PDFULLMSB_READ( r ) 	READ_32( ( BBH_TX_0_DEBUG_PDFULLMSB_ADDRESS ), (r) )
+#define BBH_TX_0_DEBUG_PDFULLMSB_WRITE( v )	WRITE_32( ( BBH_TX_0_DEBUG_PDFULLMSB_ADDRESS ), (v) )
+
+#define BBH_TX_1_DEBUG_PDFULLMSB_ADDRESS   	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLMSB_OFFSET )
+#define BBH_TX_1_DEBUG_PDFULLMSB_READ( r ) 	READ_32( ( BBH_TX_1_DEBUG_PDFULLMSB_ADDRESS ), (r) )
+#define BBH_TX_1_DEBUG_PDFULLMSB_WRITE( v )	WRITE_32( ( BBH_TX_1_DEBUG_PDFULLMSB_ADDRESS ), (v) )
+
+#define BBH_TX_2_DEBUG_PDFULLMSB_ADDRESS   	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLMSB_OFFSET )
+#define BBH_TX_2_DEBUG_PDFULLMSB_READ( r ) 	READ_32( ( BBH_TX_2_DEBUG_PDFULLMSB_ADDRESS ), (r) )
+#define BBH_TX_2_DEBUG_PDFULLMSB_WRITE( v )	WRITE_32( ( BBH_TX_2_DEBUG_PDFULLMSB_ADDRESS ), (v) )
+
+#define BBH_TX_3_DEBUG_PDFULLMSB_ADDRESS   	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLMSB_OFFSET )
+#define BBH_TX_3_DEBUG_PDFULLMSB_READ( r ) 	READ_32( ( BBH_TX_3_DEBUG_PDFULLMSB_ADDRESS ), (r) )
+#define BBH_TX_3_DEBUG_PDFULLMSB_WRITE( v )	WRITE_32( ( BBH_TX_3_DEBUG_PDFULLMSB_ADDRESS ), (v) )
+
+#define BBH_TX_4_DEBUG_PDFULLMSB_ADDRESS   	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLMSB_OFFSET )
+#define BBH_TX_4_DEBUG_PDFULLMSB_READ( r ) 	READ_32( ( BBH_TX_4_DEBUG_PDFULLMSB_ADDRESS ), (r) )
+#define BBH_TX_4_DEBUG_PDFULLMSB_WRITE( v )	WRITE_32( ( BBH_TX_4_DEBUG_PDFULLMSB_ADDRESS ), (v) )
+
+#define BBH_TX_5_DEBUG_PDFULLMSB_ADDRESS   	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLMSB_OFFSET )
+#define BBH_TX_5_DEBUG_PDFULLMSB_READ( r ) 	READ_32( ( BBH_TX_5_DEBUG_PDFULLMSB_ADDRESS ), (r) )
+#define BBH_TX_5_DEBUG_PDFULLMSB_WRITE( v )	WRITE_32( ( BBH_TX_5_DEBUG_PDFULLMSB_ADDRESS ), (v) )
+
+#define BBH_TX_6_DEBUG_PDFULLMSB_ADDRESS   	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLMSB_OFFSET )
+#define BBH_TX_6_DEBUG_PDFULLMSB_READ( r ) 	READ_32( ( BBH_TX_6_DEBUG_PDFULLMSB_ADDRESS ), (r) )
+#define BBH_TX_6_DEBUG_PDFULLMSB_WRITE( v )	WRITE_32( ( BBH_TX_6_DEBUG_PDFULLMSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_PDFULLMSB_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_PDFULLMSB_WRITE( i, v )	WRITE_32( BBH_TX_DEBUG_PDFULLMSB_ARRAY [ i ], (v) )
+#define BBH_TX_DEBUG_PDFULLMSB_READ( i, r ) 	READ_32( BBH_TX_DEBUG_PDFULLMSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1    	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_full */
+	uint32_t pdfull	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDFULLMSB ;
+#else
+typedef struct
+{	uint32_t pdfull	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_full */
+	uint32_t r1    	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDFULLMSB ;
+#endif
+
+/*****************************************************************************************/
+/* PD_empty_LSB                                                                          */
+/* Empty indication of the PD FIFOs.                                                     */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_PDEMPTYLSB_PDEMPTY_DEFAULT_VALUE             ( 0xFFFFFFFF )
+#define BBH_TX_DEBUG_PDEMPTYLSB_PDEMPTY_DEFAULT_VALUE_RESET_VALUE ( 0xFFFFFFFF )
+
+
+#define BBH_TX_DEBUG_PDEMPTYLSB_OFFSET ( 0x00000028 )
+
+#define BBH_TX_0_DEBUG_PDEMPTYLSB_ADDRESS   	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_0_DEBUG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_0_DEBUG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_0_DEBUG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_0_DEBUG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_1_DEBUG_PDEMPTYLSB_ADDRESS   	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_1_DEBUG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_1_DEBUG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_1_DEBUG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_1_DEBUG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_2_DEBUG_PDEMPTYLSB_ADDRESS   	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_2_DEBUG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_2_DEBUG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_2_DEBUG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_2_DEBUG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_3_DEBUG_PDEMPTYLSB_ADDRESS   	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_3_DEBUG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_3_DEBUG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_3_DEBUG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_3_DEBUG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_4_DEBUG_PDEMPTYLSB_ADDRESS   	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_4_DEBUG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_4_DEBUG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_4_DEBUG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_4_DEBUG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_5_DEBUG_PDEMPTYLSB_ADDRESS   	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_5_DEBUG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_5_DEBUG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_5_DEBUG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_5_DEBUG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_6_DEBUG_PDEMPTYLSB_ADDRESS   	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_6_DEBUG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_6_DEBUG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_6_DEBUG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_6_DEBUG_PDEMPTYLSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_PDEMPTYLSB_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_PDEMPTYLSB_WRITE( i, v )	WRITE_32( BBH_TX_DEBUG_PDEMPTYLSB_ARRAY [ i ], (v) )
+#define BBH_TX_DEBUG_PDEMPTYLSB_READ( i, r ) 	READ_32( BBH_TX_DEBUG_PDEMPTYLSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PD_empty */
+	uint32_t pdempty	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDEMPTYLSB ;
+#else
+typedef struct
+{	uint32_t pdempty	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_empty */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDEMPTYLSB ;
+#endif
+
+/*****************************************************************************************/
+/* PD_empty_MSB                                                                          */
+/* Empty indication of the PD FIFOs.                                                     */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_PDEMPTYMSB_R1_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_TX_DEBUG_PDEMPTYMSB_R1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_DEBUG_PDEMPTYMSB_PDEMPTY_DEFAULT_VALUE             ( 0xFF )
+#define BBH_TX_DEBUG_PDEMPTYMSB_PDEMPTY_DEFAULT_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define BBH_TX_DEBUG_PDEMPTYMSB_OFFSET ( 0x0000002C )
+
+#define BBH_TX_0_DEBUG_PDEMPTYMSB_ADDRESS   	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYMSB_OFFSET )
+#define BBH_TX_0_DEBUG_PDEMPTYMSB_READ( r ) 	READ_32( ( BBH_TX_0_DEBUG_PDEMPTYMSB_ADDRESS ), (r) )
+#define BBH_TX_0_DEBUG_PDEMPTYMSB_WRITE( v )	WRITE_32( ( BBH_TX_0_DEBUG_PDEMPTYMSB_ADDRESS ), (v) )
+
+#define BBH_TX_1_DEBUG_PDEMPTYMSB_ADDRESS   	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYMSB_OFFSET )
+#define BBH_TX_1_DEBUG_PDEMPTYMSB_READ( r ) 	READ_32( ( BBH_TX_1_DEBUG_PDEMPTYMSB_ADDRESS ), (r) )
+#define BBH_TX_1_DEBUG_PDEMPTYMSB_WRITE( v )	WRITE_32( ( BBH_TX_1_DEBUG_PDEMPTYMSB_ADDRESS ), (v) )
+
+#define BBH_TX_2_DEBUG_PDEMPTYMSB_ADDRESS   	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYMSB_OFFSET )
+#define BBH_TX_2_DEBUG_PDEMPTYMSB_READ( r ) 	READ_32( ( BBH_TX_2_DEBUG_PDEMPTYMSB_ADDRESS ), (r) )
+#define BBH_TX_2_DEBUG_PDEMPTYMSB_WRITE( v )	WRITE_32( ( BBH_TX_2_DEBUG_PDEMPTYMSB_ADDRESS ), (v) )
+
+#define BBH_TX_3_DEBUG_PDEMPTYMSB_ADDRESS   	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYMSB_OFFSET )
+#define BBH_TX_3_DEBUG_PDEMPTYMSB_READ( r ) 	READ_32( ( BBH_TX_3_DEBUG_PDEMPTYMSB_ADDRESS ), (r) )
+#define BBH_TX_3_DEBUG_PDEMPTYMSB_WRITE( v )	WRITE_32( ( BBH_TX_3_DEBUG_PDEMPTYMSB_ADDRESS ), (v) )
+
+#define BBH_TX_4_DEBUG_PDEMPTYMSB_ADDRESS   	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYMSB_OFFSET )
+#define BBH_TX_4_DEBUG_PDEMPTYMSB_READ( r ) 	READ_32( ( BBH_TX_4_DEBUG_PDEMPTYMSB_ADDRESS ), (r) )
+#define BBH_TX_4_DEBUG_PDEMPTYMSB_WRITE( v )	WRITE_32( ( BBH_TX_4_DEBUG_PDEMPTYMSB_ADDRESS ), (v) )
+
+#define BBH_TX_5_DEBUG_PDEMPTYMSB_ADDRESS   	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYMSB_OFFSET )
+#define BBH_TX_5_DEBUG_PDEMPTYMSB_READ( r ) 	READ_32( ( BBH_TX_5_DEBUG_PDEMPTYMSB_ADDRESS ), (r) )
+#define BBH_TX_5_DEBUG_PDEMPTYMSB_WRITE( v )	WRITE_32( ( BBH_TX_5_DEBUG_PDEMPTYMSB_ADDRESS ), (v) )
+
+#define BBH_TX_6_DEBUG_PDEMPTYMSB_ADDRESS   	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYMSB_OFFSET )
+#define BBH_TX_6_DEBUG_PDEMPTYMSB_READ( r ) 	READ_32( ( BBH_TX_6_DEBUG_PDEMPTYMSB_ADDRESS ), (r) )
+#define BBH_TX_6_DEBUG_PDEMPTYMSB_WRITE( v )	WRITE_32( ( BBH_TX_6_DEBUG_PDEMPTYMSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_PDEMPTYMSB_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_PDEMPTYMSB_WRITE( i, v )	WRITE_32( BBH_TX_DEBUG_PDEMPTYMSB_ARRAY [ i ], (v) )
+#define BBH_TX_DEBUG_PDEMPTYMSB_READ( i, r ) 	READ_32( BBH_TX_DEBUG_PDEMPTYMSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1     	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_empty */
+	uint32_t pdempty	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDEMPTYMSB ;
+#else
+typedef struct
+{	uint32_t pdempty	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_empty */
+	uint32_t r1     	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDEMPTYMSB ;
+#endif
+
+/*****************************************************************************************/
+/* PD_VALID                                                                              */
+/* The BBH manages 40 queues (1 for each TCONT). For each queue it manages a PD FIFO.    */
+/* A total of 128 PDs are available for all queue.  The SW may read these PDs.  The PD v */
+/* alid register indicates whether the relevant PD is valid.  The first register refers  */
+/* to PDs 0-31.  The second register refers to PDs 32-63.  The third register refers to  */
+/* PDs 64-95.  The fourth register refers to PDs 96-127.    This register is irrelevant  */
+/* for Ethernet. For Ethernet, the valid indication is part of the PD.    This register  */
+/* is also irrelevant for EPON. For EPON PD FIDOs validinformation, refer to EPON_PD_VAL */
+/* ID registers in this section.                                                         */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_PDVALID_VALID_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_PDVALID_VALID_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_DEBUG_PDVALID_OFFSET ( 0x00000030 )
+
+#define BBH_TX_0_DEBUG_PDVALID_ADDRESS        	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_PDVALID_OFFSET )
+#define BBH_TX_0_DEBUG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_DEBUG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_0_DEBUG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_DEBUG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_DEBUG_PDVALID_ADDRESS        	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_PDVALID_OFFSET )
+#define BBH_TX_1_DEBUG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_DEBUG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_1_DEBUG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_DEBUG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_DEBUG_PDVALID_ADDRESS        	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_PDVALID_OFFSET )
+#define BBH_TX_2_DEBUG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_DEBUG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_2_DEBUG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_DEBUG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_DEBUG_PDVALID_ADDRESS        	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_PDVALID_OFFSET )
+#define BBH_TX_3_DEBUG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_DEBUG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_3_DEBUG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_DEBUG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_DEBUG_PDVALID_ADDRESS        	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_PDVALID_OFFSET )
+#define BBH_TX_4_DEBUG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_DEBUG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_4_DEBUG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_DEBUG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_DEBUG_PDVALID_ADDRESS        	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_PDVALID_OFFSET )
+#define BBH_TX_5_DEBUG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_DEBUG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_5_DEBUG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_DEBUG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_DEBUG_PDVALID_ADDRESS        	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_PDVALID_OFFSET )
+#define BBH_TX_6_DEBUG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_DEBUG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_6_DEBUG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_DEBUG_PDVALID_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_PDVALID_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_PDVALID_WRITE( i, k, v )	WRITE_I_32( BBH_TX_DEBUG_PDVALID_ARRAY [ i ], (k), (v) )
+#define BBH_TX_DEBUG_PDVALID_READ( i, k, r ) 	READ_I_32( BBH_TX_DEBUG_PDVALID_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* valid */
+	uint32_t valid	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDVALID ;
+#else
+typedef struct
+{	uint32_t valid	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* valid */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_PDVALID ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_FIFO                                                                              */
+/* After reading a whole packet from the DDR, the BBH clears the BPM pointer. For that r */
+/* eason it keeps a FIFO (of 8 entries) with the pointers to be cleared.                 */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_BPMFIFO_R4_DEFAULT_VALUE                      ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_R4_DEFAULT_VALUE_RESET_VALUE          ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_VALID_NOT_VALID_VALUE                 ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_VALID_NOT_VALID_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_VALID_VALID_VALUE                     ( 0x1 )
+#define BBH_TX_DEBUG_BPMFIFO_R3_DEFAULT_VALUE                      ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_R3_DEFAULT_VALUE_RESET_VALUE          ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_P1588_NOT_1588_VALUE                  ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_P1588_NOT_1588_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_P1588_IS1588_VALUE                    ( 0x1 )
+#define BBH_TX_DEBUG_BPMFIFO_ABS_NOT_ABSOLUTE_VALUE                ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_ABS_NOT_ABSOLUTE_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_ABS_ABSOLUTE_VALUE                    ( 0x1 )
+#define BBH_TX_DEBUG_BPMFIFO_R2_DEFAULT_VALUE                      ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_R2_DEFAULT_VALUE_RESET_VALUE          ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_SRCPORT_SOURCE_PORT_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_SRCPORT_SOURCE_PORT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_R1_DEFAULT_VALUE                      ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_R1_DEFAULT_VALUE_RESET_VALUE          ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_BN_BN_VALUE                           ( 0x0 )
+#define BBH_TX_DEBUG_BPMFIFO_BN_BN_VALUE_RESET_VALUE               ( 0x0 )
+
+
+#define BBH_TX_DEBUG_BPMFIFO_OFFSET ( 0x00000040 )
+
+#define BBH_TX_0_DEBUG_BPMFIFO_ADDRESS        	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_BPMFIFO_OFFSET )
+#define BBH_TX_0_DEBUG_BPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_DEBUG_BPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_0_DEBUG_BPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_DEBUG_BPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_DEBUG_BPMFIFO_ADDRESS        	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_BPMFIFO_OFFSET )
+#define BBH_TX_1_DEBUG_BPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_DEBUG_BPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_1_DEBUG_BPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_DEBUG_BPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_DEBUG_BPMFIFO_ADDRESS        	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_BPMFIFO_OFFSET )
+#define BBH_TX_2_DEBUG_BPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_DEBUG_BPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_2_DEBUG_BPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_DEBUG_BPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_DEBUG_BPMFIFO_ADDRESS        	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_BPMFIFO_OFFSET )
+#define BBH_TX_3_DEBUG_BPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_DEBUG_BPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_3_DEBUG_BPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_DEBUG_BPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_DEBUG_BPMFIFO_ADDRESS        	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_BPMFIFO_OFFSET )
+#define BBH_TX_4_DEBUG_BPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_DEBUG_BPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_4_DEBUG_BPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_DEBUG_BPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_DEBUG_BPMFIFO_ADDRESS        	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_BPMFIFO_OFFSET )
+#define BBH_TX_5_DEBUG_BPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_DEBUG_BPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_5_DEBUG_BPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_DEBUG_BPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_DEBUG_BPMFIFO_ADDRESS        	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_BPMFIFO_OFFSET )
+#define BBH_TX_6_DEBUG_BPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_DEBUG_BPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_6_DEBUG_BPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_DEBUG_BPMFIFO_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_BPMFIFO_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_BPMFIFO_WRITE( i, k, v )	WRITE_I_32( BBH_TX_DEBUG_BPMFIFO_ARRAY [ i ], (k), (v) )
+#define BBH_TX_DEBUG_BPMFIFO_READ( i, k, r ) 	READ_I_32( BBH_TX_DEBUG_BPMFIFO_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Valid */
+	uint32_t valid  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* P1588 */
+	uint32_t p1588  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Absolute */
+	uint32_t abs    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Source_port */
+	uint32_t srcport	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BN */
+	uint32_t bn     	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_BPMFIFO ;
+#else
+typedef struct
+{	uint32_t bn     	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BN */
+	uint32_t r1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t srcport	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Source_port */
+	uint32_t r2     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t abs    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Absolute */
+	uint32_t p1588  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* P1588 */
+	uint32_t r3     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t valid  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Valid */
+	uint32_t r4     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_BPMFIFO ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_FIFO                                                                             */
+/* After reading a whole packet from the SRAM, the BBH clears the SBPM pointer. For that */
+/*  reason it keeps a FIFO (of 4 entries) with the pointers to be cleared.  Relevant onl */
+/* y for Ethernet.                                                                       */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_SBPMFIFO_VALID_NOT_VALID_VALUE                 ( 0x0 )
+#define BBH_TX_DEBUG_SBPMFIFO_VALID_NOT_VALID_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_TX_DEBUG_SBPMFIFO_VALID_VALID_VALUE                     ( 0x1 )
+#define BBH_TX_DEBUG_SBPMFIFO_LASTBN_BN_VALUE                       ( 0x0 )
+#define BBH_TX_DEBUG_SBPMFIFO_LASTBN_BN_VALUE_RESET_VALUE           ( 0x0 )
+#define BBH_TX_DEBUG_SBPMFIFO_SRCPORT_SOURCE_PORT_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_SBPMFIFO_SRCPORT_SOURCE_PORT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_DEBUG_SBPMFIFO_HEADBN_BN_VALUE                       ( 0x0 )
+#define BBH_TX_DEBUG_SBPMFIFO_HEADBN_BN_VALUE_RESET_VALUE           ( 0x0 )
+
+
+#define BBH_TX_DEBUG_SBPMFIFO_OFFSET ( 0x00000060 )
+
+#define BBH_TX_0_DEBUG_SBPMFIFO_ADDRESS        	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_SBPMFIFO_OFFSET )
+#define BBH_TX_0_DEBUG_SBPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_DEBUG_SBPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_0_DEBUG_SBPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_DEBUG_SBPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_DEBUG_SBPMFIFO_ADDRESS        	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_SBPMFIFO_OFFSET )
+#define BBH_TX_1_DEBUG_SBPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_DEBUG_SBPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_1_DEBUG_SBPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_DEBUG_SBPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_DEBUG_SBPMFIFO_ADDRESS        	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_SBPMFIFO_OFFSET )
+#define BBH_TX_2_DEBUG_SBPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_DEBUG_SBPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_2_DEBUG_SBPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_DEBUG_SBPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_DEBUG_SBPMFIFO_ADDRESS        	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_SBPMFIFO_OFFSET )
+#define BBH_TX_3_DEBUG_SBPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_DEBUG_SBPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_3_DEBUG_SBPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_DEBUG_SBPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_DEBUG_SBPMFIFO_ADDRESS        	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_SBPMFIFO_OFFSET )
+#define BBH_TX_4_DEBUG_SBPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_DEBUG_SBPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_4_DEBUG_SBPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_DEBUG_SBPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_DEBUG_SBPMFIFO_ADDRESS        	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_SBPMFIFO_OFFSET )
+#define BBH_TX_5_DEBUG_SBPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_DEBUG_SBPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_5_DEBUG_SBPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_DEBUG_SBPMFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_DEBUG_SBPMFIFO_ADDRESS        	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_SBPMFIFO_OFFSET )
+#define BBH_TX_6_DEBUG_SBPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_DEBUG_SBPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_6_DEBUG_SBPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_DEBUG_SBPMFIFO_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_SBPMFIFO_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_SBPMFIFO_WRITE( i, k, v )	WRITE_I_32( BBH_TX_DEBUG_SBPMFIFO_ARRAY [ i ], (k), (v) )
+#define BBH_TX_DEBUG_SBPMFIFO_READ( i, k, r ) 	READ_I_32( BBH_TX_DEBUG_SBPMFIFO_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Valid */
+	uint32_t valid  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Last_BN */
+	uint32_t lastbn 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Source_port */
+	uint32_t srcport	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HEAD_BN */
+	uint32_t headbn 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_SBPMFIFO ;
+#else
+typedef struct
+{	uint32_t headbn 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HEAD_BN */
+	uint32_t srcport	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Source_port */
+	uint32_t lastbn 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Last_BN */
+	uint32_t valid  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Valid */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_SBPMFIFO ;
+#endif
+
+/*****************************************************************************************/
+/* First_BN_FIFO                                                                         */
+/* The SBPM Get next unit will maintain a “first BN” FIFO (8 entries). Each PD, which ar */
+/* rives from the Runner, is checked and if it describes a SRAM packet which exceeds 128 */
+/*  bytes (including the SOP offset and multicast transmission) it is written into “firs */
+/* t BN” FIFO.   Relevant only for Ethernet.                                             */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_FIRSTBNFIFO_R3_DEFAULT_VALUE                   ( 0x0 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_R3_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_VALID_NOT_VALID_VALUE              ( 0x0 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_VALID_NOT_VALID_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_VALID_VALID_VALUE                  ( 0x1 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_R2_DEFAULT_VALUE                   ( 0x0 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_R2_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_NUMOFSBN_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_NUMOFSBN_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_R1_DEFAULT_VALUE                   ( 0x0 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_R1_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_HEADBN_BN_VALUE                    ( 0x0 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_HEADBN_BN_VALUE_RESET_VALUE        ( 0x0 )
+
+
+#define BBH_TX_DEBUG_FIRSTBNFIFO_OFFSET ( 0x00000080 )
+
+#define BBH_TX_0_DEBUG_FIRSTBNFIFO_ADDRESS        	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_FIRSTBNFIFO_OFFSET )
+#define BBH_TX_0_DEBUG_FIRSTBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_0_DEBUG_FIRSTBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_DEBUG_FIRSTBNFIFO_ADDRESS        	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_FIRSTBNFIFO_OFFSET )
+#define BBH_TX_1_DEBUG_FIRSTBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_1_DEBUG_FIRSTBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_DEBUG_FIRSTBNFIFO_ADDRESS        	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_FIRSTBNFIFO_OFFSET )
+#define BBH_TX_2_DEBUG_FIRSTBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_2_DEBUG_FIRSTBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_DEBUG_FIRSTBNFIFO_ADDRESS        	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_FIRSTBNFIFO_OFFSET )
+#define BBH_TX_3_DEBUG_FIRSTBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_3_DEBUG_FIRSTBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_DEBUG_FIRSTBNFIFO_ADDRESS        	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_FIRSTBNFIFO_OFFSET )
+#define BBH_TX_4_DEBUG_FIRSTBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_4_DEBUG_FIRSTBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_DEBUG_FIRSTBNFIFO_ADDRESS        	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_FIRSTBNFIFO_OFFSET )
+#define BBH_TX_5_DEBUG_FIRSTBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_5_DEBUG_FIRSTBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_DEBUG_FIRSTBNFIFO_ADDRESS        	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_FIRSTBNFIFO_OFFSET )
+#define BBH_TX_6_DEBUG_FIRSTBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_6_DEBUG_FIRSTBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_FIRSTBNFIFO_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_FIRSTBNFIFO_WRITE( i, k, v )	WRITE_I_32( BBH_TX_DEBUG_FIRSTBNFIFO_ARRAY [ i ], (k), (v) )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_READ( i, k, r ) 	READ_I_32( BBH_TX_DEBUG_FIRSTBNFIFO_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r3      	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Valid */
+	uint32_t valid   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Number_of_SBN */
+	uint32_t numofsbn	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1      	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HEAD_BN */
+	uint32_t headbn  	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_FIRSTBNFIFO ;
+#else
+typedef struct
+{	uint32_t headbn  	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HEAD_BN */
+	uint32_t r1      	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t numofsbn	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Number_of_SBN */
+	uint32_t r2      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t valid   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Valid */
+	uint32_t r3      	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_FIRSTBNFIFO ;
+#endif
+
+/*****************************************************************************************/
+/* Get_next_FIFO                                                                         */
+/* When reading a packet from the SRAM, the BBH should request the next buffer in the pa */
+/* cket’s linked list. Doing it during the packet transmission might damage the performa */
+/* nce; therefore the BBH maintains a pre-fetch of “next” buffers FIFO.  Relevant only f */
+/* or Ethernet.                                                                          */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_GETNEXTFIFO_R2_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_TX_DEBUG_GETNEXTFIFO_R2_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_DEBUG_GETNEXTFIFO_VALID_NOT_VALID_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_GETNEXTFIFO_VALID_NOT_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_DEBUG_GETNEXTFIFO_VALID_VALID_VALUE                 ( 0x1 )
+#define BBH_TX_DEBUG_GETNEXTFIFO_R1_DEFAULT_VALUE                  ( 0x0 )
+#define BBH_TX_DEBUG_GETNEXTFIFO_R1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_DEBUG_GETNEXTFIFO_HEADBN_BN_VALUE                   ( 0x0 )
+#define BBH_TX_DEBUG_GETNEXTFIFO_HEADBN_BN_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define BBH_TX_DEBUG_GETNEXTFIFO_OFFSET ( 0x000000A0 )
+
+#define BBH_TX_0_DEBUG_GETNEXTFIFO_ADDRESS        	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTFIFO_OFFSET )
+#define BBH_TX_0_DEBUG_GETNEXTFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_0_DEBUG_GETNEXTFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_DEBUG_GETNEXTFIFO_ADDRESS        	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTFIFO_OFFSET )
+#define BBH_TX_1_DEBUG_GETNEXTFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_1_DEBUG_GETNEXTFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_DEBUG_GETNEXTFIFO_ADDRESS        	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTFIFO_OFFSET )
+#define BBH_TX_2_DEBUG_GETNEXTFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_2_DEBUG_GETNEXTFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_DEBUG_GETNEXTFIFO_ADDRESS        	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTFIFO_OFFSET )
+#define BBH_TX_3_DEBUG_GETNEXTFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_3_DEBUG_GETNEXTFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_DEBUG_GETNEXTFIFO_ADDRESS        	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTFIFO_OFFSET )
+#define BBH_TX_4_DEBUG_GETNEXTFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_4_DEBUG_GETNEXTFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_DEBUG_GETNEXTFIFO_ADDRESS        	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTFIFO_OFFSET )
+#define BBH_TX_5_DEBUG_GETNEXTFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_5_DEBUG_GETNEXTFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_DEBUG_GETNEXTFIFO_ADDRESS        	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTFIFO_OFFSET )
+#define BBH_TX_6_DEBUG_GETNEXTFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_6_DEBUG_GETNEXTFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_GETNEXTFIFO_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_GETNEXTFIFO_WRITE( i, k, v )	WRITE_I_32( BBH_TX_DEBUG_GETNEXTFIFO_ARRAY [ i ], (k), (v) )
+#define BBH_TX_DEBUG_GETNEXTFIFO_READ( i, k, r ) 	READ_I_32( BBH_TX_DEBUG_GETNEXTFIFO_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2    	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Valid */
+	uint32_t valid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1    	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HEAD_BN */
+	uint32_t headbn	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_GETNEXTFIFO ;
+#else
+typedef struct
+{	uint32_t headbn	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HEAD_BN */
+	uint32_t r1    	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t valid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Valid */
+	uint32_t r2    	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_GETNEXTFIFO ;
+#endif
+
+/*****************************************************************************************/
+/* Debug_out_reg                                                                         */
+/* Holds the selected debug vector (1 of 8) according to DBGSEL                          */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_DBGOUTREG_R1_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_TX_DEBUG_DBGOUTREG_R1_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_TX_DEBUG_DBGOUTREG_DBGVEC_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_DBGOUTREG_DBGVEC_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_DEBUG_DBGOUTREG_OFFSET ( 0x000000C0 )
+
+#define BBH_TX_0_DEBUG_DBGOUTREG_ADDRESS   	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_DBGOUTREG_OFFSET )
+#define BBH_TX_0_DEBUG_DBGOUTREG_READ( r ) 	READ_32( ( BBH_TX_0_DEBUG_DBGOUTREG_ADDRESS ), (r) )
+#define BBH_TX_0_DEBUG_DBGOUTREG_WRITE( v )	WRITE_32( ( BBH_TX_0_DEBUG_DBGOUTREG_ADDRESS ), (v) )
+
+#define BBH_TX_1_DEBUG_DBGOUTREG_ADDRESS   	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_DBGOUTREG_OFFSET )
+#define BBH_TX_1_DEBUG_DBGOUTREG_READ( r ) 	READ_32( ( BBH_TX_1_DEBUG_DBGOUTREG_ADDRESS ), (r) )
+#define BBH_TX_1_DEBUG_DBGOUTREG_WRITE( v )	WRITE_32( ( BBH_TX_1_DEBUG_DBGOUTREG_ADDRESS ), (v) )
+
+#define BBH_TX_2_DEBUG_DBGOUTREG_ADDRESS   	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_DBGOUTREG_OFFSET )
+#define BBH_TX_2_DEBUG_DBGOUTREG_READ( r ) 	READ_32( ( BBH_TX_2_DEBUG_DBGOUTREG_ADDRESS ), (r) )
+#define BBH_TX_2_DEBUG_DBGOUTREG_WRITE( v )	WRITE_32( ( BBH_TX_2_DEBUG_DBGOUTREG_ADDRESS ), (v) )
+
+#define BBH_TX_3_DEBUG_DBGOUTREG_ADDRESS   	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_DBGOUTREG_OFFSET )
+#define BBH_TX_3_DEBUG_DBGOUTREG_READ( r ) 	READ_32( ( BBH_TX_3_DEBUG_DBGOUTREG_ADDRESS ), (r) )
+#define BBH_TX_3_DEBUG_DBGOUTREG_WRITE( v )	WRITE_32( ( BBH_TX_3_DEBUG_DBGOUTREG_ADDRESS ), (v) )
+
+#define BBH_TX_4_DEBUG_DBGOUTREG_ADDRESS   	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_DBGOUTREG_OFFSET )
+#define BBH_TX_4_DEBUG_DBGOUTREG_READ( r ) 	READ_32( ( BBH_TX_4_DEBUG_DBGOUTREG_ADDRESS ), (r) )
+#define BBH_TX_4_DEBUG_DBGOUTREG_WRITE( v )	WRITE_32( ( BBH_TX_4_DEBUG_DBGOUTREG_ADDRESS ), (v) )
+
+#define BBH_TX_5_DEBUG_DBGOUTREG_ADDRESS   	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_DBGOUTREG_OFFSET )
+#define BBH_TX_5_DEBUG_DBGOUTREG_READ( r ) 	READ_32( ( BBH_TX_5_DEBUG_DBGOUTREG_ADDRESS ), (r) )
+#define BBH_TX_5_DEBUG_DBGOUTREG_WRITE( v )	WRITE_32( ( BBH_TX_5_DEBUG_DBGOUTREG_ADDRESS ), (v) )
+
+#define BBH_TX_6_DEBUG_DBGOUTREG_ADDRESS   	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_DBGOUTREG_OFFSET )
+#define BBH_TX_6_DEBUG_DBGOUTREG_READ( r ) 	READ_32( ( BBH_TX_6_DEBUG_DBGOUTREG_ADDRESS ), (r) )
+#define BBH_TX_6_DEBUG_DBGOUTREG_WRITE( v )	WRITE_32( ( BBH_TX_6_DEBUG_DBGOUTREG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_DBGOUTREG_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_DBGOUTREG_WRITE( i, v )	WRITE_32( BBH_TX_DEBUG_DBGOUTREG_ARRAY [ i ], (v) )
+#define BBH_TX_DEBUG_DBGOUTREG_READ( i, r ) 	READ_32( BBH_TX_DEBUG_DBGOUTREG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1    	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Debug_vector */
+	uint32_t dbgvec	: 21 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_DBGOUTREG ;
+#else
+typedef struct
+{	uint32_t dbgvec	: 21 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Debug_vector */
+	uint32_t r1    	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_DBGOUTREG ;
+#endif
+
+/*****************************************************************************************/
+/* EPON_PD_VALID                                                                         */
+/* The BBH manages 32 queues. For each queue it manages a PD FIFO.   A total of 256 PDs  */
+/* are available for all queue.  The SW may read these PDs.  The PD valid register indic */
+/* ates whether the relevant PD is valid.  The first register refers to PDs 0-31.  The s */
+/* econd register refers to PDs 32-63 and so on.                                         */
+/*****************************************************************************************/
+
+#define BBH_TX_DEBUG_EPNPDVALID_VALID_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_DEBUG_EPNPDVALID_VALID_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_DEBUG_EPNPDVALID_OFFSET ( 0x000000D0 )
+
+#define BBH_TX_0_DEBUG_EPNPDVALID_ADDRESS        	( BBH_TX_0_DEBUG_ADDRESS + BBH_TX_DEBUG_EPNPDVALID_OFFSET )
+#define BBH_TX_0_DEBUG_EPNPDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_DEBUG_EPNPDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_0_DEBUG_EPNPDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_DEBUG_EPNPDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_DEBUG_EPNPDVALID_ADDRESS        	( BBH_TX_1_DEBUG_ADDRESS + BBH_TX_DEBUG_EPNPDVALID_OFFSET )
+#define BBH_TX_1_DEBUG_EPNPDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_DEBUG_EPNPDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_1_DEBUG_EPNPDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_DEBUG_EPNPDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_DEBUG_EPNPDVALID_ADDRESS        	( BBH_TX_2_DEBUG_ADDRESS + BBH_TX_DEBUG_EPNPDVALID_OFFSET )
+#define BBH_TX_2_DEBUG_EPNPDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_DEBUG_EPNPDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_2_DEBUG_EPNPDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_DEBUG_EPNPDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_DEBUG_EPNPDVALID_ADDRESS        	( BBH_TX_3_DEBUG_ADDRESS + BBH_TX_DEBUG_EPNPDVALID_OFFSET )
+#define BBH_TX_3_DEBUG_EPNPDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_DEBUG_EPNPDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_3_DEBUG_EPNPDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_DEBUG_EPNPDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_DEBUG_EPNPDVALID_ADDRESS        	( BBH_TX_4_DEBUG_ADDRESS + BBH_TX_DEBUG_EPNPDVALID_OFFSET )
+#define BBH_TX_4_DEBUG_EPNPDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_DEBUG_EPNPDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_4_DEBUG_EPNPDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_DEBUG_EPNPDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_DEBUG_EPNPDVALID_ADDRESS        	( BBH_TX_5_DEBUG_ADDRESS + BBH_TX_DEBUG_EPNPDVALID_OFFSET )
+#define BBH_TX_5_DEBUG_EPNPDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_DEBUG_EPNPDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_5_DEBUG_EPNPDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_DEBUG_EPNPDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_DEBUG_EPNPDVALID_ADDRESS        	( BBH_TX_6_DEBUG_ADDRESS + BBH_TX_DEBUG_EPNPDVALID_OFFSET )
+#define BBH_TX_6_DEBUG_EPNPDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_DEBUG_EPNPDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_6_DEBUG_EPNPDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_DEBUG_EPNPDVALID_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_DEBUG_EPNPDVALID_ARRAY [ ] ;
+
+#define BBH_TX_DEBUG_EPNPDVALID_WRITE( i, k, v )	WRITE_I_32( BBH_TX_DEBUG_EPNPDVALID_ARRAY [ i ], (k), (v) )
+#define BBH_TX_DEBUG_EPNPDVALID_READ( i, k, r ) 	READ_I_32( BBH_TX_DEBUG_EPNPDVALID_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* valid */
+	uint32_t valid	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_EPNPDVALID ;
+#else
+typedef struct
+{	uint32_t valid	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* valid */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG_EPNPDVALID ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO                                                                               */
+/* The SW may read the PD RAM.  This RAM includes a total of 128 PDs.  A special registe */
+/* r marks the valid PDs.  Each PD occupies 2 addresses of 32 bits - the odd address ref */
+/* ers to the LSB word of the entry.  Please refer to BBH LLD for the context of the PD. */
+/*****************************************************************************************/
+
+#define BBH_TX_PD_FIFO_PDFIFO_PDENTRY_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_PD_FIFO_PDFIFO_PDENTRY_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_PD_FIFO_PDFIFO_OFFSET ( 0x00000000 )
+
+#define BBH_TX_0_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_0_PD_FIFO_ADDRESS + BBH_TX_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_0_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_0_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_1_PD_FIFO_ADDRESS + BBH_TX_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_1_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_1_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_2_PD_FIFO_ADDRESS + BBH_TX_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_2_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_2_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_3_PD_FIFO_ADDRESS + BBH_TX_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_3_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_3_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_4_PD_FIFO_ADDRESS + BBH_TX_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_4_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_4_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_5_PD_FIFO_ADDRESS + BBH_TX_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_5_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_5_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_6_PD_FIFO_ADDRESS + BBH_TX_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_6_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_6_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_PD_FIFO_PDFIFO_ARRAY [ ] ;
+
+#define BBH_TX_PD_FIFO_PDFIFO_WRITE( i, k, v )	WRITE_I_32( BBH_TX_PD_FIFO_PDFIFO_ARRAY [ i ], (k), (v) )
+#define BBH_TX_PD_FIFO_PDFIFO_READ( i, k, r ) 	READ_I_32( BBH_TX_PD_FIFO_PDFIFO_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PD_entry */
+	uint32_t pdentry	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_PD_FIFO_PDFIFO ;
+#else
+typedef struct
+{	uint32_t pdentry	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_entry */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_PD_FIFO_PDFIFO ;
+#endif
+
+/*****************************************************************************************/
+/* Segmentation_context                                                                  */
+/* Segmentation context                                                                  */
+/*****************************************************************************************/
+
+#define BBH_TX_CONTEXT_SEGCNTXT_RMNCHUNK_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_RMNCHUNK_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_BN_DEFAULT_VALUE                   ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_BN_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_SRCPORT_DEFAULT_VALUE              ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_SRCPORT_DEFAULT_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_PENDREQ_DEFAULT_VALUE              ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_PENDREQ_DEFAULT_VALUE_RESET_VALUE  ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_ABS_NOT_ABSOLUTE_VALUE             ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_ABS_NOT_ABSOLUTE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_ABS_ABSOLUTE_VALUE                 ( 0x1 )
+#define BBH_TX_CONTEXT_SEGCNTXT_INSEG_NOT_IN_SEG_VALUE             ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_INSEG_NOT_IN_SEG_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_CONTEXT_SEGCNTXT_INSEG_IN_SEG_VALUE                 ( 0x1 )
+
+
+#define BBH_TX_CONTEXT_SEGCNTXT_OFFSET ( 0x00000000 )
+
+#define BBH_TX_0_CONTEXT_SEGCNTXT_ADDRESS        	( BBH_TX_0_CONTEXT_ADDRESS + BBH_TX_CONTEXT_SEGCNTXT_OFFSET )
+#define BBH_TX_0_CONTEXT_SEGCNTXT_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_CONTEXT_SEGCNTXT_ADDRESS ), (i), (r) )
+#define BBH_TX_0_CONTEXT_SEGCNTXT_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_CONTEXT_SEGCNTXT_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_CONTEXT_SEGCNTXT_ADDRESS        	( BBH_TX_1_CONTEXT_ADDRESS + BBH_TX_CONTEXT_SEGCNTXT_OFFSET )
+#define BBH_TX_1_CONTEXT_SEGCNTXT_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_CONTEXT_SEGCNTXT_ADDRESS ), (i), (r) )
+#define BBH_TX_1_CONTEXT_SEGCNTXT_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_CONTEXT_SEGCNTXT_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_CONTEXT_SEGCNTXT_ADDRESS        	( BBH_TX_2_CONTEXT_ADDRESS + BBH_TX_CONTEXT_SEGCNTXT_OFFSET )
+#define BBH_TX_2_CONTEXT_SEGCNTXT_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_CONTEXT_SEGCNTXT_ADDRESS ), (i), (r) )
+#define BBH_TX_2_CONTEXT_SEGCNTXT_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_CONTEXT_SEGCNTXT_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_CONTEXT_SEGCNTXT_ADDRESS        	( BBH_TX_3_CONTEXT_ADDRESS + BBH_TX_CONTEXT_SEGCNTXT_OFFSET )
+#define BBH_TX_3_CONTEXT_SEGCNTXT_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_CONTEXT_SEGCNTXT_ADDRESS ), (i), (r) )
+#define BBH_TX_3_CONTEXT_SEGCNTXT_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_CONTEXT_SEGCNTXT_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_CONTEXT_SEGCNTXT_ADDRESS        	( BBH_TX_4_CONTEXT_ADDRESS + BBH_TX_CONTEXT_SEGCNTXT_OFFSET )
+#define BBH_TX_4_CONTEXT_SEGCNTXT_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_CONTEXT_SEGCNTXT_ADDRESS ), (i), (r) )
+#define BBH_TX_4_CONTEXT_SEGCNTXT_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_CONTEXT_SEGCNTXT_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_CONTEXT_SEGCNTXT_ADDRESS        	( BBH_TX_5_CONTEXT_ADDRESS + BBH_TX_CONTEXT_SEGCNTXT_OFFSET )
+#define BBH_TX_5_CONTEXT_SEGCNTXT_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_CONTEXT_SEGCNTXT_ADDRESS ), (i), (r) )
+#define BBH_TX_5_CONTEXT_SEGCNTXT_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_CONTEXT_SEGCNTXT_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_CONTEXT_SEGCNTXT_ADDRESS        	( BBH_TX_6_CONTEXT_ADDRESS + BBH_TX_CONTEXT_SEGCNTXT_OFFSET )
+#define BBH_TX_6_CONTEXT_SEGCNTXT_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_CONTEXT_SEGCNTXT_ADDRESS ), (i), (r) )
+#define BBH_TX_6_CONTEXT_SEGCNTXT_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_CONTEXT_SEGCNTXT_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_CONTEXT_SEGCNTXT_ARRAY [ ] ;
+
+#define BBH_TX_CONTEXT_SEGCNTXT_WRITE( i, k, v )	WRITE_I_32( BBH_TX_CONTEXT_SEGCNTXT_ARRAY [ i ], (k), (v) )
+#define BBH_TX_CONTEXT_SEGCNTXT_READ( i, k, r ) 	READ_I_32( BBH_TX_CONTEXT_SEGCNTXT_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Remaining_chunks */
+	uint32_t rmnchunk	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_Number */
+	uint32_t bn      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Source_port */
+	uint32_t srcport 	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pending_requests */
+	uint32_t pendreq 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Absolute */
+	uint32_t abs     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_segmentation */
+	uint32_t inseg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONTEXT_SEGCNTXT ;
+#else
+typedef struct
+{	uint32_t inseg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* In_segmentation */
+	uint32_t abs     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Absolute */
+	uint32_t pendreq 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pending_requests */
+	uint32_t srcport 	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Source_port */
+	uint32_t bn      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_Number */
+	uint32_t rmnchunk	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Remaining_chunks */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONTEXT_SEGCNTXT ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO                                                                               */
+/* The SW may read the PD RAM.  This RAM includes a total of 256 PDs.  A special registe */
+/* r marks the valid PDs.  Each PD occupies 2 addresses of 32 bits - the odd address ref */
+/* ers to the LSB word of the entry.  Please refer to BBH LLD for the context of the PD. */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_PD_FIFO_PDFIFO_PDENTRY_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_EPON_PD_FIFO_PDFIFO_PDENTRY_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_EPON_PD_FIFO_PDFIFO_OFFSET ( 0x00000000 )
+
+#define BBH_TX_0_EPON_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_0_EPON_PD_FIFO_ADDRESS + BBH_TX_EPON_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_0_EPON_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_0_EPON_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_EPON_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_1_EPON_PD_FIFO_ADDRESS + BBH_TX_EPON_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_1_EPON_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_1_EPON_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_EPON_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_2_EPON_PD_FIFO_ADDRESS + BBH_TX_EPON_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_2_EPON_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_2_EPON_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_EPON_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_3_EPON_PD_FIFO_ADDRESS + BBH_TX_EPON_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_3_EPON_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_3_EPON_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_EPON_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_4_EPON_PD_FIFO_ADDRESS + BBH_TX_EPON_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_4_EPON_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_4_EPON_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_EPON_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_5_EPON_PD_FIFO_ADDRESS + BBH_TX_EPON_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_5_EPON_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_5_EPON_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_EPON_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_6_EPON_PD_FIFO_ADDRESS + BBH_TX_EPON_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_6_EPON_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_6_EPON_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_EPON_PD_FIFO_PDFIFO_ARRAY [ ] ;
+
+#define BBH_TX_EPON_PD_FIFO_PDFIFO_WRITE( i, k, v )	WRITE_I_32( BBH_TX_EPON_PD_FIFO_PDFIFO_ARRAY [ i ], (k), (v) )
+#define BBH_TX_EPON_PD_FIFO_PDFIFO_READ( i, k, r ) 	READ_I_32( BBH_TX_EPON_PD_FIFO_PDFIFO_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PD_entry */
+	uint32_t pdentry	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_PD_FIFO_PDFIFO ;
+#else
+typedef struct
+{	uint32_t pdentry	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_entry */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_PD_FIFO_PDFIFO ;
+#endif
+
+/*****************************************************************************************/
+/* Task_numbers_LSB                                                                      */
+/* The BBH manages 40 queues for GPON or 32 queues for EPON.  Each of the first 8 Queues */
+/*  may have a unique Runner task number.  Queues 8-39 have all the same configurable ta */
+/* sk number.  This register defines the tasks for Queues 0-3.  For Ethernet queue 0 sho */
+/* uld be configured.                                                                    */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_TASKLSB_R4_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKLSB_R4_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKLSB_TASK3_TASK_NUMBER_VALUE             ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKLSB_TASK3_TASK_NUMBER_VALUE_RESET_VALUE ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKLSB_R3_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKLSB_R3_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKLSB_TASK2_TASK_NUMBER_VALUE             ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKLSB_TASK2_TASK_NUMBER_VALUE_RESET_VALUE ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKLSB_R2_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKLSB_R2_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKLSB_TASK1_TASK_NUMBER_VALUE             ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKLSB_TASK1_TASK_NUMBER_VALUE_RESET_VALUE ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKLSB_R1_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKLSB_R1_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKLSB_TASK0_TASK_NUMBER_VALUE             ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKLSB_TASK0_TASK_NUMBER_VALUE_RESET_VALUE ( 0x6 )
+
+
+#define BBH_TX_EPON_CFG_TASKLSB_OFFSET ( 0x00000000 )
+
+#define BBH_TX_0_EPON_CFG_TASKLSB_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKLSB_OFFSET )
+#define BBH_TX_0_EPON_CFG_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_TASKLSB_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKLSB_OFFSET )
+#define BBH_TX_1_EPON_CFG_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_TASKLSB_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKLSB_OFFSET )
+#define BBH_TX_2_EPON_CFG_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_TASKLSB_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKLSB_OFFSET )
+#define BBH_TX_3_EPON_CFG_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_TASKLSB_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKLSB_OFFSET )
+#define BBH_TX_4_EPON_CFG_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_TASKLSB_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKLSB_OFFSET )
+#define BBH_TX_5_EPON_CFG_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_TASKLSB_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_TASKLSB_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKLSB_OFFSET )
+#define BBH_TX_6_EPON_CFG_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_TASKLSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_TASKLSB_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_TASKLSB_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_TASKLSB_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_TASKLSB_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_TASKLSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_3 */
+	uint32_t task3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_2 */
+	uint32_t task2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_1 */
+	uint32_t task1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_0 */
+	uint32_t task0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_TASKLSB ;
+#else
+typedef struct
+{	uint32_t task0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_0 */
+	uint32_t r1   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_1 */
+	uint32_t r2   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_2 */
+	uint32_t r3   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_3 */
+	uint32_t r4   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_TASKLSB ;
+#endif
+
+/*****************************************************************************************/
+/* Task_numbers_MSB                                                                      */
+/* The BBH manages 40 queues for GPON or 32 queues for EPON.  Each of the first 8 Queues */
+/*  may have a unique Runner task number.  Queues 8-39 have all the same configurable ta */
+/* sk number.  This register defines the tasks for Queues 4-7.  For Ethernet queue 0 sho */
+/* uld be configured.                                                                    */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_TASKMSB_R4_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKMSB_R4_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKMSB_TASK7_TASK_NUMBER_VALUE             ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKMSB_TASK7_TASK_NUMBER_VALUE_RESET_VALUE ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKMSB_R3_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKMSB_R3_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKMSB_TASK6_TASK_NUMBER_VALUE             ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKMSB_TASK6_TASK_NUMBER_VALUE_RESET_VALUE ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKMSB_R2_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKMSB_R2_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKMSB_TASK5_TASK_NUMBER_VALUE             ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKMSB_TASK5_TASK_NUMBER_VALUE_RESET_VALUE ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKMSB_R1_DEFAULT_VALUE                    ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKMSB_R1_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define BBH_TX_EPON_CFG_TASKMSB_TASK4_TASK_NUMBER_VALUE             ( 0x6 )
+#define BBH_TX_EPON_CFG_TASKMSB_TASK4_TASK_NUMBER_VALUE_RESET_VALUE ( 0x6 )
+
+
+#define BBH_TX_EPON_CFG_TASKMSB_OFFSET ( 0x00000004 )
+
+#define BBH_TX_0_EPON_CFG_TASKMSB_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKMSB_OFFSET )
+#define BBH_TX_0_EPON_CFG_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_TASKMSB_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKMSB_OFFSET )
+#define BBH_TX_1_EPON_CFG_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_TASKMSB_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKMSB_OFFSET )
+#define BBH_TX_2_EPON_CFG_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_TASKMSB_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKMSB_OFFSET )
+#define BBH_TX_3_EPON_CFG_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_TASKMSB_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKMSB_OFFSET )
+#define BBH_TX_4_EPON_CFG_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_TASKMSB_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKMSB_OFFSET )
+#define BBH_TX_5_EPON_CFG_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_TASKMSB_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_TASKMSB_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKMSB_OFFSET )
+#define BBH_TX_6_EPON_CFG_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_TASKMSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_TASKMSB_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_TASKMSB_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_TASKMSB_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_TASKMSB_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_TASKMSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_7 */
+	uint32_t task7	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_6 */
+	uint32_t task6	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_5 */
+	uint32_t task5	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_4 */
+	uint32_t task4	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_TASKMSB ;
+#else
+typedef struct
+{	uint32_t task4	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_4 */
+	uint32_t r1   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task5	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_5 */
+	uint32_t r2   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task6	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_6 */
+	uint32_t r3   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t task7	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_7 */
+	uint32_t r4   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_TASKMSB ;
+#endif
+
+/*****************************************************************************************/
+/* Task_numbers_8-39                                                                     */
+/* The BBH manages 40 queues for GPON or 32 queues for EPON.  Each of the first 8 Queues */
+/*  may have a unique Runner task number.  Queues 8-39 have all the same configurable ta */
+/* sk number.  This register defines the tasks for Queues 8-39.  For Ethernet queue 0 sh */
+/* ould be configured.                                                                   */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_TASK8_39_R1_DEFAULT_VALUE                       ( 0x0 )
+#define BBH_TX_EPON_CFG_TASK8_39_R1_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define BBH_TX_EPON_CFG_TASK8_39_TASK8_39_TASK_NUMBER_VALUE             ( 0x6 )
+#define BBH_TX_EPON_CFG_TASK8_39_TASK8_39_TASK_NUMBER_VALUE_RESET_VALUE ( 0x6 )
+
+
+#define BBH_TX_EPON_CFG_TASK8_39_OFFSET ( 0x00000008 )
+
+#define BBH_TX_0_EPON_CFG_TASK8_39_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASK8_39_OFFSET )
+#define BBH_TX_0_EPON_CFG_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_TASK8_39_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASK8_39_OFFSET )
+#define BBH_TX_1_EPON_CFG_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_TASK8_39_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASK8_39_OFFSET )
+#define BBH_TX_2_EPON_CFG_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_TASK8_39_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASK8_39_OFFSET )
+#define BBH_TX_3_EPON_CFG_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_TASK8_39_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASK8_39_OFFSET )
+#define BBH_TX_4_EPON_CFG_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_TASK8_39_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASK8_39_OFFSET )
+#define BBH_TX_5_EPON_CFG_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_TASK8_39_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_TASK8_39_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASK8_39_OFFSET )
+#define BBH_TX_6_EPON_CFG_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_TASK8_39_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_TASK8_39_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_TASK8_39_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_TASK8_39_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_TASK8_39_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_TASK8_39_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1      	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_8-39 */
+	uint32_t task8_39	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_TASK8_39 ;
+#else
+typedef struct
+{	uint32_t task8_39	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_8-39 */
+	uint32_t r1      	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_TASK8_39 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO_size_0_3                                                                      */
+/* The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per TCONT/LLID). For  */
+/* each queue it manages a PD FIFO.   A total of 128 PDs (GPON) or 256 PDs (EPON) are av */
+/* ailable for all queues.   For each Queue the SW configures the base and the size with */
+/* in these 128/256 PDs.  This register defines the PD FIFO size for queues 0-3.         */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PDSIZE0_3_R4_DEFAULT_VALUE                         ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_R4_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE3_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE3_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE3_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_R3_DEFAULT_VALUE                         ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_R3_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE2_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE2_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE2_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_R2_DEFAULT_VALUE                         ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_R2_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE1_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE1_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE1_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_R1_DEFAULT_VALUE                         ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_R1_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE0_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE0_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_FIFOSIZE0_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+
+
+#define BBH_TX_EPON_CFG_PDSIZE0_3_OFFSET ( 0x0000000C )
+
+#define BBH_TX_0_EPON_CFG_PDSIZE0_3_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE0_3_OFFSET )
+#define BBH_TX_0_EPON_CFG_PDSIZE0_3_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_PDSIZE0_3_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_PDSIZE0_3_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_PDSIZE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_PDSIZE0_3_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE0_3_OFFSET )
+#define BBH_TX_1_EPON_CFG_PDSIZE0_3_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_PDSIZE0_3_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_PDSIZE0_3_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_PDSIZE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_PDSIZE0_3_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE0_3_OFFSET )
+#define BBH_TX_2_EPON_CFG_PDSIZE0_3_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_PDSIZE0_3_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_PDSIZE0_3_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_PDSIZE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_PDSIZE0_3_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE0_3_OFFSET )
+#define BBH_TX_3_EPON_CFG_PDSIZE0_3_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_PDSIZE0_3_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_PDSIZE0_3_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_PDSIZE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_PDSIZE0_3_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE0_3_OFFSET )
+#define BBH_TX_4_EPON_CFG_PDSIZE0_3_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_PDSIZE0_3_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_PDSIZE0_3_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_PDSIZE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_PDSIZE0_3_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE0_3_OFFSET )
+#define BBH_TX_5_EPON_CFG_PDSIZE0_3_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_PDSIZE0_3_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_PDSIZE0_3_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_PDSIZE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_PDSIZE0_3_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE0_3_OFFSET )
+#define BBH_TX_6_EPON_CFG_PDSIZE0_3_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_PDSIZE0_3_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_PDSIZE0_3_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_PDSIZE0_3_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PDSIZE0_3_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PDSIZE0_3_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_PDSIZE0_3_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_PDSIZE0_3_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_PDSIZE0_3_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_3 */
+	uint32_t fifosize3	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_2 */
+	uint32_t fifosize2	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_1 */
+	uint32_t fifosize1	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_0 */
+	uint32_t fifosize0	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDSIZE0_3 ;
+#else
+typedef struct
+{	uint32_t fifosize0	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_0 */
+	uint32_t r1       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t fifosize1	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_1 */
+	uint32_t r2       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t fifosize2	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_2 */
+	uint32_t r3       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t fifosize3	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_3 */
+	uint32_t r4       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDSIZE0_3 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO_size_4_7                                                                      */
+/* The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per TCONT/LLID). For  */
+/* each queue it manages a PD FIFO.   A total of 128 PDs (GPON) or 256 PDs (EPON) are av */
+/* ailable for all queues.   For each Queue the SW configures the base and the size with */
+/* in these 128/256 PDs.  This register defines the PD FIFO size for queues 4-7.         */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PDSIZE4_7_R4_DEFAULT_VALUE                         ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_R4_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE7_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE7_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE7_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_R3_DEFAULT_VALUE                         ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_R3_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE6_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE6_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE6_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_R2_DEFAULT_VALUE                         ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_R2_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE5_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE5_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE5_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_R1_DEFAULT_VALUE                         ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_R1_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE4_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE4_DEFAULT_EPON_VALUE             ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_FIFOSIZE4_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xF )
+
+
+#define BBH_TX_EPON_CFG_PDSIZE4_7_OFFSET ( 0x00000010 )
+
+#define BBH_TX_0_EPON_CFG_PDSIZE4_7_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE4_7_OFFSET )
+#define BBH_TX_0_EPON_CFG_PDSIZE4_7_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_PDSIZE4_7_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_PDSIZE4_7_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_PDSIZE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_PDSIZE4_7_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE4_7_OFFSET )
+#define BBH_TX_1_EPON_CFG_PDSIZE4_7_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_PDSIZE4_7_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_PDSIZE4_7_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_PDSIZE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_PDSIZE4_7_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE4_7_OFFSET )
+#define BBH_TX_2_EPON_CFG_PDSIZE4_7_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_PDSIZE4_7_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_PDSIZE4_7_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_PDSIZE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_PDSIZE4_7_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE4_7_OFFSET )
+#define BBH_TX_3_EPON_CFG_PDSIZE4_7_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_PDSIZE4_7_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_PDSIZE4_7_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_PDSIZE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_PDSIZE4_7_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE4_7_OFFSET )
+#define BBH_TX_4_EPON_CFG_PDSIZE4_7_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_PDSIZE4_7_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_PDSIZE4_7_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_PDSIZE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_PDSIZE4_7_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE4_7_OFFSET )
+#define BBH_TX_5_EPON_CFG_PDSIZE4_7_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_PDSIZE4_7_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_PDSIZE4_7_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_PDSIZE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_PDSIZE4_7_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE4_7_OFFSET )
+#define BBH_TX_6_EPON_CFG_PDSIZE4_7_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_PDSIZE4_7_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_PDSIZE4_7_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_PDSIZE4_7_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PDSIZE4_7_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PDSIZE4_7_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_PDSIZE4_7_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_PDSIZE4_7_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_PDSIZE4_7_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_7 */
+	uint32_t fifosize7	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_6 */
+	uint32_t fifosize6	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_5 */
+	uint32_t fifosize5	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_4 */
+	uint32_t fifosize4	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDSIZE4_7 ;
+#else
+typedef struct
+{	uint32_t fifosize4	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_4 */
+	uint32_t r1       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t fifosize5	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_5 */
+	uint32_t r2       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t fifosize6	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_6 */
+	uint32_t r3       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t fifosize7	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_7 */
+	uint32_t r4       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDSIZE4_7 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO_size_8_31                                                                     */
+/* The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per queue). For each  */
+/* queue it manages a PD FIFO.   A total of 128 PDs for GPON and 256 PDs for EPON are av */
+/* ailable for all queues.   For each Queue the SW configures the base and the size with */
+/* in these 128/256 PDs.  This register defines the PD FIFO size for TCONTs 8-31.        */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PDSIZE8_31_R3_DEFAULT_VALUE                             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_R3_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_FIFOSIZE24_31_DEFAULT_EPON_VALUE             ( 0x4 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_FIFOSIZE24_31_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x4 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_FIFOSIZE24_31_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_R2_DEFAULT_VALUE                             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_R2_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_FIFOSIZE16_23_DEFAULT_EPON_VALUE             ( 0x4 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_FIFOSIZE16_23_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x4 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_FIFOSIZE16_23_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_R1_DEFAULT_VALUE                             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_R1_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_FIFOSIZE8_15_DEFAULT_EPON_VALUE              ( 0x4 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_FIFOSIZE8_15_DEFAULT_EPON_VALUE_RESET_VALUE  ( 0x4 )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_FIFOSIZE8_15_MAX_EPON_VALUE                  ( 0xF )
+
+
+#define BBH_TX_EPON_CFG_PDSIZE8_31_OFFSET ( 0x00000014 )
+
+#define BBH_TX_0_EPON_CFG_PDSIZE8_31_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE8_31_OFFSET )
+#define BBH_TX_0_EPON_CFG_PDSIZE8_31_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_PDSIZE8_31_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_PDSIZE8_31_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_PDSIZE8_31_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_PDSIZE8_31_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE8_31_OFFSET )
+#define BBH_TX_1_EPON_CFG_PDSIZE8_31_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_PDSIZE8_31_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_PDSIZE8_31_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_PDSIZE8_31_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_PDSIZE8_31_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE8_31_OFFSET )
+#define BBH_TX_2_EPON_CFG_PDSIZE8_31_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_PDSIZE8_31_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_PDSIZE8_31_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_PDSIZE8_31_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_PDSIZE8_31_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE8_31_OFFSET )
+#define BBH_TX_3_EPON_CFG_PDSIZE8_31_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_PDSIZE8_31_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_PDSIZE8_31_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_PDSIZE8_31_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_PDSIZE8_31_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE8_31_OFFSET )
+#define BBH_TX_4_EPON_CFG_PDSIZE8_31_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_PDSIZE8_31_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_PDSIZE8_31_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_PDSIZE8_31_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_PDSIZE8_31_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE8_31_OFFSET )
+#define BBH_TX_5_EPON_CFG_PDSIZE8_31_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_PDSIZE8_31_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_PDSIZE8_31_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_PDSIZE8_31_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_PDSIZE8_31_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE8_31_OFFSET )
+#define BBH_TX_6_EPON_CFG_PDSIZE8_31_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_PDSIZE8_31_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_PDSIZE8_31_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_PDSIZE8_31_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PDSIZE8_31_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PDSIZE8_31_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_PDSIZE8_31_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_PDSIZE8_31_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_PDSIZE8_31_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r3           	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_24_31 */
+	uint32_t fifosize24_31	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_16_23 */
+	uint32_t fifosize16_23	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_8_15 */
+	uint32_t fifosize8_15 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDSIZE8_31 ;
+#else
+typedef struct
+{	uint32_t fifosize8_15 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_8_15 */
+	uint32_t r1           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t fifosize16_23	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_16_23 */
+	uint32_t r2           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t fifosize24_31	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_size_24_31 */
+	uint32_t r3           	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDSIZE8_31 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO_base_0_3                                                                      */
+/* The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each TCONT/LLID). For  */
+/* each queue it manages a PD FIFO.   A total of 128 PDs (GPON) or 256 (EPON) are availa */
+/* ble for all queues.   For each Queue the SW configures the base and the size within t */
+/* hese 128/256 PDs.  This register defines the PD FIFO base for TCONTs 0-3.  This confi */
+/* guration is irrelevant for Ethernet.                                                  */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE3_DEFAULT_EPON_VALUE             ( 0x30 )
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE3_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x30 )
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE3_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE2_DEFAULT_EPON_VALUE             ( 0x20 )
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE2_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x20 )
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE2_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE1_DEFAULT_EPON_VALUE             ( 0x10 )
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE1_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x10 )
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE1_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE0_DEFAULT_EPON_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE0_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_EPON_CFG_PDBASE0_3_FIFOBASE0_MAX_EPON_VALUE                 ( 0xFF )
+
+
+#define BBH_TX_EPON_CFG_PDBASE0_3_OFFSET ( 0x00000018 )
+
+#define BBH_TX_0_EPON_CFG_PDBASE0_3_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE0_3_OFFSET )
+#define BBH_TX_0_EPON_CFG_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_PDBASE0_3_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE0_3_OFFSET )
+#define BBH_TX_1_EPON_CFG_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_PDBASE0_3_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE0_3_OFFSET )
+#define BBH_TX_2_EPON_CFG_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_PDBASE0_3_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE0_3_OFFSET )
+#define BBH_TX_3_EPON_CFG_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_PDBASE0_3_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE0_3_OFFSET )
+#define BBH_TX_4_EPON_CFG_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_PDBASE0_3_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE0_3_OFFSET )
+#define BBH_TX_5_EPON_CFG_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_PDBASE0_3_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_PDBASE0_3_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE0_3_OFFSET )
+#define BBH_TX_6_EPON_CFG_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_PDBASE0_3_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PDBASE0_3_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PDBASE0_3_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_PDBASE0_3_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_PDBASE0_3_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_PDBASE0_3_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* FIFO_base_3 */
+	uint32_t fifobase3	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_2 */
+	uint32_t fifobase2	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_1 */
+	uint32_t fifobase1	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_0 */
+	uint32_t fifobase0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDBASE0_3 ;
+#else
+typedef struct
+{	uint32_t fifobase0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_0 */
+	uint32_t fifobase1	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_1 */
+	uint32_t fifobase2	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_2 */
+	uint32_t fifobase3	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_3 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDBASE0_3 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO_base_4_7                                                                      */
+/* The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each TCONT/LLID). For  */
+/* each queue it manages a PD FIFO.   A total of 128 PDs (GPON) or 256 (EPON) are availa */
+/* ble for all queues.   For each Queue the SW configures the base and the size within t */
+/* hese 128/256 PDs.  This register defines the PD FIFO base for TCONTs 4-7.  This confi */
+/* guration is irrelevant for Ethernet.                                                  */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE7_DEFAULT_EPON_VALUE             ( 0x70 )
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE7_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x70 )
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE7_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE6_DEFAULT_EPON_VALUE             ( 0x60 )
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE6_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x60 )
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE6_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE5_DEFAULT_EPON_VALUE             ( 0x50 )
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE5_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x50 )
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE5_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE4_DEFAULT_EPON_VALUE             ( 0x40 )
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE4_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x40 )
+#define BBH_TX_EPON_CFG_PDBASE4_7_FIFOBASE4_MAX_EPON_VALUE                 ( 0xFF )
+
+
+#define BBH_TX_EPON_CFG_PDBASE4_7_OFFSET ( 0x0000001C )
+
+#define BBH_TX_0_EPON_CFG_PDBASE4_7_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE4_7_OFFSET )
+#define BBH_TX_0_EPON_CFG_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_PDBASE4_7_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE4_7_OFFSET )
+#define BBH_TX_1_EPON_CFG_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_PDBASE4_7_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE4_7_OFFSET )
+#define BBH_TX_2_EPON_CFG_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_PDBASE4_7_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE4_7_OFFSET )
+#define BBH_TX_3_EPON_CFG_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_PDBASE4_7_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE4_7_OFFSET )
+#define BBH_TX_4_EPON_CFG_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_PDBASE4_7_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE4_7_OFFSET )
+#define BBH_TX_5_EPON_CFG_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_PDBASE4_7_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_PDBASE4_7_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE4_7_OFFSET )
+#define BBH_TX_6_EPON_CFG_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_PDBASE4_7_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PDBASE4_7_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PDBASE4_7_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_PDBASE4_7_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_PDBASE4_7_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_PDBASE4_7_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* FIFO_base_7 */
+	uint32_t fifobase7	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_6 */
+	uint32_t fifobase6	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_5 */
+	uint32_t fifobase5	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_4 */
+	uint32_t fifobase4	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDBASE4_7 ;
+#else
+typedef struct
+{	uint32_t fifobase4	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_4 */
+	uint32_t fifobase5	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_5 */
+	uint32_t fifobase6	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_6 */
+	uint32_t fifobase7	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_7 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDBASE4_7 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO_base_8_39                                                                     */
+/* The BBH manages 40 queues (GPON) or 32 queus (EPON). For each queue it manages a PD F */
+/* IFO.   A total of 128 PDs (GPON) or 256 PDs (EPON) are available for all queues.   Fo */
+/* r each Queue the SW configures the base and the size within these 128/256 PDs.  This  */
+/* register defines the PD FIFO base for queues 8-39.  This configuration is irrelevant  */
+/* for Ethernet.                                                                         */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE32_39_MAX_EPON_VALUE                 ( 0x0 )
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE32_39_DEFAULT_GPON_VALUE             ( 0x70 )
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE32_39_DEFAULT_GPON_VALUE_RESET_VALUE ( 0x70 )
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE24_31_DEFAULT_EPON_VALUE             ( 0xD0 )
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE24_31_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xD0 )
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE24_31_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE16_23_DEFAULT_EPON_VALUE             ( 0xA8 )
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE16_23_DEFAULT_EPON_VALUE_RESET_VALUE ( 0xA8 )
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE16_23_MAX_EPON_VALUE                 ( 0xFF )
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE8_15_DEFAULT_EPON_VALUE              ( 0x80 )
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE8_15_DEFAULT_EPON_VALUE_RESET_VALUE  ( 0x80 )
+#define BBH_TX_EPON_CFG_PDBASE8_39_FIFOBASE8_15_MAX_EPON_VALUE                  ( 0xFF )
+
+
+#define BBH_TX_EPON_CFG_PDBASE8_39_OFFSET ( 0x00000020 )
+
+#define BBH_TX_0_EPON_CFG_PDBASE8_39_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE8_39_OFFSET )
+#define BBH_TX_0_EPON_CFG_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_PDBASE8_39_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE8_39_OFFSET )
+#define BBH_TX_1_EPON_CFG_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_PDBASE8_39_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE8_39_OFFSET )
+#define BBH_TX_2_EPON_CFG_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_PDBASE8_39_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE8_39_OFFSET )
+#define BBH_TX_3_EPON_CFG_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_PDBASE8_39_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE8_39_OFFSET )
+#define BBH_TX_4_EPON_CFG_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_PDBASE8_39_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE8_39_OFFSET )
+#define BBH_TX_5_EPON_CFG_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_PDBASE8_39_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_PDBASE8_39_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE8_39_OFFSET )
+#define BBH_TX_6_EPON_CFG_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_PDBASE8_39_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PDBASE8_39_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PDBASE8_39_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_PDBASE8_39_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_PDBASE8_39_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_PDBASE8_39_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* FIFO_base_32_39 */
+	uint32_t fifobase32_39	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_24_31 */
+	uint32_t fifobase24_31	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_16_23 */
+	uint32_t fifobase16_23	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_8_15 */
+	uint32_t fifobase8_15 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDBASE8_39 ;
+#else
+typedef struct
+{	uint32_t fifobase8_15 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_8_15 */
+	uint32_t fifobase16_23	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_16_23 */
+	uint32_t fifobase24_31	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_24_31 */
+	uint32_t fifobase32_39	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_base_32_39 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDBASE8_39 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_bytes_threshold_EN                                                                 */
+/* The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO.  The PDs pre */
+/*  fetch is limited either by the PD FIFO configurable size or according to the total n */
+/* umber of bytes (deducting bytes already requested/transmitted) for preventing HOL. Fu */
+/* ll configuration for the first 8 TCONT and one configuration per group of 8 TCONTs fo */
+/* r the rest.                                                                           */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_EN_RESERVED1_DEFAULT_VALUE                      ( 0x0 )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_EN_RESERVED1_DEFAULT_VALUE_RESET_VALUE          ( 0x0 )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_EN_PDLIMITEN_PD_LIMIT_DISABLE_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_EN_PDLIMITEN_PD_LIMIT_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_EN_PDLIMITEN_PD_LIMIT_ENABLE_VALUE              ( 0x1 )
+
+
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_EN_OFFSET ( 0x00000024 )
+
+#define BBH_TX_0_EPON_CFG_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_0_EPON_CFG_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_1_EPON_CFG_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_2_EPON_CFG_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_3_EPON_CFG_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_4_EPON_CFG_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_5_EPON_CFG_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_6_EPON_CFG_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PD_BYTE_TH_EN_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_EN_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_PD_BYTE_TH_EN_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_EN_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_PD_BYTE_TH_EN_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_enable */
+	uint32_t pdlimiten	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PD_BYTE_TH_EN ;
+#else
+typedef struct
+{	uint32_t pdlimiten	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_enable */
+	uint32_t reserved1	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PD_BYTE_TH_EN ;
+#endif
+
+/*****************************************************************************************/
+/* PD_bytes_threshold                                                                    */
+/* The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO.  The PDs pre */
+/*  fetch is limited either by the PD FIFO configurable size or according to the total n */
+/* umber of bytes (deducting bytes already requested/transmitted) for preventing HOL. Fu */
+/* ll configuration for the first 8 TCONT and one configuration for the rest (TCONTs 8-3 */
+/* 9).  Registers 0-3 define the configuration for the first 8 TCONT and register 4 defi */
+/* nes the configuration for TCONTs 8-39 (in the even field).                            */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_R2_RESET_VALUE_VALUE                  ( 0x0 )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_R2_RESET_VALUE_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_PDLIMITEVEN_DEFAULT_VALUE             ( 0x180 )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_PDLIMITEVEN_DEFAULT_VALUE_RESET_VALUE ( 0x180 )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_R1_RESET_VALUE_VALUE                  ( 0x0 )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_R1_RESET_VALUE_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_PDLIMITODD_DEFAULT_VALUE              ( 0x180 )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_PDLIMITODD_DEFAULT_VALUE_RESET_VALUE  ( 0x180 )
+
+
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_OFFSET ( 0x00000028 )
+
+#define BBH_TX_0_EPON_CFG_PD_BYTE_TH_ADDRESS        	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_OFFSET )
+#define BBH_TX_0_EPON_CFG_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_0_EPON_CFG_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_EPON_CFG_PD_BYTE_TH_ADDRESS        	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_OFFSET )
+#define BBH_TX_1_EPON_CFG_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_1_EPON_CFG_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_EPON_CFG_PD_BYTE_TH_ADDRESS        	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_OFFSET )
+#define BBH_TX_2_EPON_CFG_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_2_EPON_CFG_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_EPON_CFG_PD_BYTE_TH_ADDRESS        	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_OFFSET )
+#define BBH_TX_3_EPON_CFG_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_3_EPON_CFG_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_EPON_CFG_PD_BYTE_TH_ADDRESS        	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_OFFSET )
+#define BBH_TX_4_EPON_CFG_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_4_EPON_CFG_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_EPON_CFG_PD_BYTE_TH_ADDRESS        	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_OFFSET )
+#define BBH_TX_5_EPON_CFG_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_5_EPON_CFG_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_EPON_CFG_PD_BYTE_TH_ADDRESS        	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_OFFSET )
+#define BBH_TX_6_EPON_CFG_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_6_EPON_CFG_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PD_BYTE_TH_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_WRITE( i, k, v )	WRITE_I_32( BBH_TX_EPON_CFG_PD_BYTE_TH_ARRAY [ i ], (k), (v) )
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_READ( i, k, r ) 	READ_I_32( BBH_TX_EPON_CFG_PD_BYTE_TH_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2         	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_even */
+	uint32_t pdlimiteven	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1         	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_odd */
+	uint32_t pdlimitodd 	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PD_BYTE_TH ;
+#else
+typedef struct
+{	uint32_t pdlimitodd 	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_odd */
+	uint32_t r1         	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t pdlimiteven	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_limit_even */
+	uint32_t r2         	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PD_BYTE_TH ;
+#endif
+
+/*****************************************************************************************/
+/* Runner_configurations                                                                 */
+/* TCONT/LLID address:  The BBH requests a Packet descriptor from the Runner. The BBH se */
+/* nds a wake-up request to the Runner (for a new PD). The wake-up request is written to */
+/*  address 0x8000 in the Runner.    In the case of GPON/EPON peripheral the BBH writes  */
+/* the TCONT/LLID number in a predefined address at the Runner SRAM and then sends a wak */
+/* e-up request to the Runner.   This register defines the TCONT/LLID address within the */
+/*  Runner address space.                                                                */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_RUNNERCFG_R0_DEFAULT_VALUE                          ( 0x0 )
+#define BBH_TX_EPON_CFG_RUNNERCFG_R0_DEFAULT_VALUE_RESET_VALUE              ( 0x0 )
+#define BBH_TX_EPON_CFG_RUNNERCFG_TCONTADDR_TCONT_ADDRESS_VALUE             ( 0x1797 )
+#define BBH_TX_EPON_CFG_RUNNERCFG_TCONTADDR_TCONT_ADDRESS_VALUE_RESET_VALUE ( 0x1797 )
+
+
+#define BBH_TX_EPON_CFG_RUNNERCFG_OFFSET ( 0x0000003C )
+
+#define BBH_TX_0_EPON_CFG_RUNNERCFG_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_RUNNERCFG_OFFSET )
+#define BBH_TX_0_EPON_CFG_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_RUNNERCFG_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_RUNNERCFG_OFFSET )
+#define BBH_TX_1_EPON_CFG_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_RUNNERCFG_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_RUNNERCFG_OFFSET )
+#define BBH_TX_2_EPON_CFG_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_RUNNERCFG_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_RUNNERCFG_OFFSET )
+#define BBH_TX_3_EPON_CFG_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_RUNNERCFG_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_RUNNERCFG_OFFSET )
+#define BBH_TX_4_EPON_CFG_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_RUNNERCFG_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_RUNNERCFG_OFFSET )
+#define BBH_TX_5_EPON_CFG_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_RUNNERCFG_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_RUNNERCFG_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_RUNNERCFG_OFFSET )
+#define BBH_TX_6_EPON_CFG_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_RUNNERCFG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_RUNNERCFG_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_RUNNERCFG_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_RUNNERCFG_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_RUNNERCFG_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_RUNNERCFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r0       	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TCONT_address */
+	uint32_t tcontaddr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_RUNNERCFG ;
+#else
+typedef struct
+{	uint32_t tcontaddr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TCONT_address */
+	uint32_t r0       	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_RUNNERCFG ;
+#endif
+
+/*****************************************************************************************/
+/* MDU_CFG                                                                               */
+/* The BBH supports a special configurable mode to enable a faster packet bridging:  -Th */
+/* ere will be a special configurable mode for transferring the PD from the Runner into  */
+/* the BBH TX.    -The Runner wont ACK the BBH; therefore the BBH wont wake the TX task. */
+/*    -The Runner will push the PDs into the BBH (without any wakeup from the BBH).   -E */
+/* ach time that the BBH reads a PD from the PD FIFO, it will write the read pointer int */
+/* o a pre-defined address in the Runner (enable by configuration). The pointer is 6 bit */
+/* s width (one bit larger than needed to distinguish between full and empty).  -The Run */
+/* ner should manage the congestion over the PD FIFO (in the BBH) by reading the BBH rea */
+/* d pointer prior to each PD write.   -PD drop should be done by the Runner only. The B */
+/* BH will drop PD when the FIFO is full and will count each drop. The BBH wont release  */
+/* the BN in this case.  For EPON BBH, there will be a full threshold, which can be smal */
+/* ler than the actual size of the FIFO. When the BBH will move from full to not full st */
+/* ate, the BBH will wakeup the Runner.                                                  */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_MDUMODE_PTRADDR_RESET_VALUE_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_MDUMODE_PTRADDR_RESET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_EPON_CFG_MDUMODE_R1_RESET_VALUE_VALUE                  ( 0x0 )
+#define BBH_TX_EPON_CFG_MDUMODE_R1_RESET_VALUE_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_EPON_CFG_MDUMODE_MDUEN_DIS_VALUE                       ( 0x0 )
+#define BBH_TX_EPON_CFG_MDUMODE_MDUEN_DIS_VALUE_RESET_VALUE           ( 0x0 )
+#define BBH_TX_EPON_CFG_MDUMODE_MDUEN_EN_VALUE                        ( 0x1 )
+
+
+#define BBH_TX_EPON_CFG_MDUMODE_OFFSET ( 0x00000040 )
+
+#define BBH_TX_0_EPON_CFG_MDUMODE_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_MDUMODE_OFFSET )
+#define BBH_TX_0_EPON_CFG_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_MDUMODE_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_MDUMODE_OFFSET )
+#define BBH_TX_1_EPON_CFG_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_MDUMODE_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_MDUMODE_OFFSET )
+#define BBH_TX_2_EPON_CFG_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_MDUMODE_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_MDUMODE_OFFSET )
+#define BBH_TX_3_EPON_CFG_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_MDUMODE_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_MDUMODE_OFFSET )
+#define BBH_TX_4_EPON_CFG_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_MDUMODE_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_MDUMODE_OFFSET )
+#define BBH_TX_5_EPON_CFG_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_MDUMODE_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_MDUMODE_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_MDUMODE_OFFSET )
+#define BBH_TX_6_EPON_CFG_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_MDUMODE_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_MDUMODE_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_MDUMODE_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_MDUMODE_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_MDUMODE_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_MDUMODE_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PTRADDR */
+	uint32_t ptraddr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MDU_EN */
+	uint32_t mduen  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_MDUMODE ;
+#else
+typedef struct
+{	uint32_t mduen  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MDU_EN */
+	uint32_t r1     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t ptraddr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PTRADDR */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_MDUMODE ;
+#endif
+
+/*****************************************************************************************/
+/* REQ_CFG                                                                               */
+/* Configurations related to EPON Request interface.                                     */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_REQCFG_R1_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_TX_EPON_CFG_REQCFG_R1_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_TX_EPON_CFG_REQCFG_CMP_WIDTH_WIDTH_11_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_REQCFG_CMP_WIDTH_WIDTH_11_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_EPON_CFG_REQCFG_CMP_WIDTH_WIDTH_14_VALUE             ( 0x1 )
+#define BBH_TX_EPON_CFG_REQCFG_STPLENERR_CONTINUE_VALUE             ( 0x0 )
+#define BBH_TX_EPON_CFG_REQCFG_STPLENERR_CONTINUE_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_EPON_CFG_REQCFG_STPLENERR_STOP_VALUE                 ( 0x1 )
+
+
+#define BBH_TX_EPON_CFG_REQCFG_OFFSET ( 0x00000044 )
+
+#define BBH_TX_0_EPON_CFG_REQCFG_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_REQCFG_OFFSET )
+#define BBH_TX_0_EPON_CFG_REQCFG_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_REQCFG_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_REQCFG_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_REQCFG_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_REQCFG_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_REQCFG_OFFSET )
+#define BBH_TX_1_EPON_CFG_REQCFG_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_REQCFG_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_REQCFG_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_REQCFG_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_REQCFG_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_REQCFG_OFFSET )
+#define BBH_TX_2_EPON_CFG_REQCFG_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_REQCFG_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_REQCFG_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_REQCFG_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_REQCFG_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_REQCFG_OFFSET )
+#define BBH_TX_3_EPON_CFG_REQCFG_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_REQCFG_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_REQCFG_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_REQCFG_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_REQCFG_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_REQCFG_OFFSET )
+#define BBH_TX_4_EPON_CFG_REQCFG_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_REQCFG_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_REQCFG_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_REQCFG_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_REQCFG_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_REQCFG_OFFSET )
+#define BBH_TX_5_EPON_CFG_REQCFG_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_REQCFG_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_REQCFG_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_REQCFG_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_REQCFG_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_REQCFG_OFFSET )
+#define BBH_TX_6_EPON_CFG_REQCFG_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_REQCFG_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_REQCFG_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_REQCFG_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_REQCFG_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_REQCFG_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_REQCFG_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_REQCFG_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_REQCFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1       	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* comp_width */
+	uint32_t cmp_width	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Stop_on_len_error */
+	uint32_t stplenerr	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_REQCFG ;
+#else
+typedef struct
+{	uint32_t stplenerr	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Stop_on_len_error */
+	uint32_t cmp_width	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* comp_width */
+	uint32_t r1       	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_REQCFG ;
+#endif
+
+/*****************************************************************************************/
+/* PD_WKUP_THRESH_0_3                                                                    */
+/* The BBH manages 32 queues for EPON (FIFO per LLID). For each queue it manages a PD FI */
+/* FO.   When a FIFO occupancy is above this wakeup threshold, the BBH will not wake-up  */
+/* the Runner for sending a new PD. This threshold does not represent the actual size of */
+/*  the FIFO. If a PD will arrive from the Runner when the FIFO is above the threshold,  */
+/* it will not be dropped unless the FIFO is actually full.  Relevant only for EPON BBH. */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_R4_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_R4_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH3_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH3_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH3_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_R3_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_R3_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH2_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH2_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH2_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_R2_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_R2_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH1_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH1_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH1_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_R1_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_R1_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH0_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH0_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WKUPTHRESH0_MAX_EPON_VALUE                 ( 0xF )
+
+
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_OFFSET ( 0x00000048 )
+
+#define BBH_TX_0_EPON_CFG_PDWKUPH0_3_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH0_3_OFFSET )
+#define BBH_TX_0_EPON_CFG_PDWKUPH0_3_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_PDWKUPH0_3_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_PDWKUPH0_3_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_PDWKUPH0_3_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_PDWKUPH0_3_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH0_3_OFFSET )
+#define BBH_TX_1_EPON_CFG_PDWKUPH0_3_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_PDWKUPH0_3_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_PDWKUPH0_3_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_PDWKUPH0_3_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_PDWKUPH0_3_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH0_3_OFFSET )
+#define BBH_TX_2_EPON_CFG_PDWKUPH0_3_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_PDWKUPH0_3_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_PDWKUPH0_3_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_PDWKUPH0_3_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_PDWKUPH0_3_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH0_3_OFFSET )
+#define BBH_TX_3_EPON_CFG_PDWKUPH0_3_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_PDWKUPH0_3_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_PDWKUPH0_3_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_PDWKUPH0_3_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_PDWKUPH0_3_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH0_3_OFFSET )
+#define BBH_TX_4_EPON_CFG_PDWKUPH0_3_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_PDWKUPH0_3_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_PDWKUPH0_3_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_PDWKUPH0_3_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_PDWKUPH0_3_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH0_3_OFFSET )
+#define BBH_TX_5_EPON_CFG_PDWKUPH0_3_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_PDWKUPH0_3_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_PDWKUPH0_3_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_PDWKUPH0_3_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_PDWKUPH0_3_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH0_3_OFFSET )
+#define BBH_TX_6_EPON_CFG_PDWKUPH0_3_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_PDWKUPH0_3_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_PDWKUPH0_3_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_PDWKUPH0_3_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PDWKUPH0_3_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_PDWKUPH0_3_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_PDWKUPH0_3_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_PDWKUPH0_3_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_3 */
+	uint32_t wkupthresh3	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_2 */
+	uint32_t wkupthresh2	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_1 */
+	uint32_t wkupthresh1	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_0 */
+	uint32_t wkupthresh0	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDWKUPH0_3 ;
+#else
+typedef struct
+{	uint32_t wkupthresh0	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_0 */
+	uint32_t r1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t wkupthresh1	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_1 */
+	uint32_t r2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t wkupthresh2	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_2 */
+	uint32_t r3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t wkupthresh3	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_3 */
+	uint32_t r4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDWKUPH0_3 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_WKUP_THRESH_4_7                                                                    */
+/* The BBH manages 32 queues for EPON (FIFO per LLID). For each queue it manages a PD FI */
+/* FO.   When a FIFO occupancy is above this wakeup threshold, the BBH will not wake-up  */
+/* the Runner for sending a new PD. This threshold does not represent the actual size of */
+/*  the FIFO. If a PD will arrive from the Runner when the FIFO is above the threshold,  */
+/* it will not be dropped unless the FIFO is actually full.  Relevant only for EPON BBH. */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_R4_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_R4_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH7_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH7_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH7_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_R3_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_R3_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH6_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH6_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH6_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_R2_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_R2_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH5_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH5_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH5_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_R1_DEFAULT_VALUE                           ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_R1_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH4_DEFAULT_EPON_VALUE             ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH4_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x7 )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WKUPTHRESH4_MAX_EPON_VALUE                 ( 0xF )
+
+
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_OFFSET ( 0x0000004C )
+
+#define BBH_TX_0_EPON_CFG_PDWKUPH4_7_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH4_7_OFFSET )
+#define BBH_TX_0_EPON_CFG_PDWKUPH4_7_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_PDWKUPH4_7_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_PDWKUPH4_7_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_PDWKUPH4_7_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_PDWKUPH4_7_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH4_7_OFFSET )
+#define BBH_TX_1_EPON_CFG_PDWKUPH4_7_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_PDWKUPH4_7_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_PDWKUPH4_7_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_PDWKUPH4_7_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_PDWKUPH4_7_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH4_7_OFFSET )
+#define BBH_TX_2_EPON_CFG_PDWKUPH4_7_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_PDWKUPH4_7_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_PDWKUPH4_7_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_PDWKUPH4_7_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_PDWKUPH4_7_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH4_7_OFFSET )
+#define BBH_TX_3_EPON_CFG_PDWKUPH4_7_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_PDWKUPH4_7_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_PDWKUPH4_7_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_PDWKUPH4_7_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_PDWKUPH4_7_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH4_7_OFFSET )
+#define BBH_TX_4_EPON_CFG_PDWKUPH4_7_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_PDWKUPH4_7_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_PDWKUPH4_7_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_PDWKUPH4_7_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_PDWKUPH4_7_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH4_7_OFFSET )
+#define BBH_TX_5_EPON_CFG_PDWKUPH4_7_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_PDWKUPH4_7_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_PDWKUPH4_7_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_PDWKUPH4_7_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_PDWKUPH4_7_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH4_7_OFFSET )
+#define BBH_TX_6_EPON_CFG_PDWKUPH4_7_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_PDWKUPH4_7_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_PDWKUPH4_7_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_PDWKUPH4_7_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PDWKUPH4_7_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_PDWKUPH4_7_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_PDWKUPH4_7_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_PDWKUPH4_7_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_7 */
+	uint32_t wkupthresh7	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_6 */
+	uint32_t wkupthresh6	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_5 */
+	uint32_t wkupthresh5	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_4 */
+	uint32_t wkupthresh4	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDWKUPH4_7 ;
+#else
+typedef struct
+{	uint32_t wkupthresh4	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_4 */
+	uint32_t r1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t wkupthresh5	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_5 */
+	uint32_t r2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t wkupthresh6	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_6 */
+	uint32_t r3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t wkupthresh7	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_7 */
+	uint32_t r4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDWKUPH4_7 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_WKUP_THRESH_8_31                                                                   */
+/* The BBH manages 32 queues for EPON (FIFO per LLID). For each queue it manages a PD FI */
+/* FO.   When a FIFO occupancy is above this wakeup threshold, the BBH will not wake-up  */
+/* the Runner for sending a new PD. This threshold does not represent the actual size of */
+/*  the FIFO. If a PD will arrive from the Runner when the FIFO is above the threshold,  */
+/* it will not be dropped unless the FIFO is actually full.  For queues 8-31, this confi */
+/* guration is per octet.  Relevant only for EPON BBH.                                   */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_R2_DEFAULT_VALUE                               ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_R2_DEFAULT_VALUE_RESET_VALUE                   ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_WKUPTHRESH24_31_DEFAULT_EPON_VALUE             ( 0x2 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_WKUPTHRESH24_31_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x2 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_WKUPTHRESH24_31_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_R1_DEFAULT_VALUE                               ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_R1_DEFAULT_VALUE_RESET_VALUE                   ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_WKUPTHRESH16_23_DEFAULT_EPON_VALUE             ( 0x2 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_WKUPTHRESH16_23_DEFAULT_EPON_VALUE_RESET_VALUE ( 0x2 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_WKUPTHRESH16_23_MAX_EPON_VALUE                 ( 0xF )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_R0_DEFAULT_VALUE                               ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_R0_DEFAULT_VALUE_RESET_VALUE                   ( 0x0 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_WKUPTHRESH8_15_DEFAULT_EPON_VALUE              ( 0x2 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_WKUPTHRESH8_15_DEFAULT_EPON_VALUE_RESET_VALUE  ( 0x2 )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_WKUPTHRESH8_15_MAX_EPON_VALUE                  ( 0xF )
+
+
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_OFFSET ( 0x00000050 )
+
+#define BBH_TX_0_EPON_CFG_PDWKUPH8_31_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH8_31_OFFSET )
+#define BBH_TX_0_EPON_CFG_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_PDWKUPH8_31_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH8_31_OFFSET )
+#define BBH_TX_1_EPON_CFG_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_PDWKUPH8_31_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH8_31_OFFSET )
+#define BBH_TX_2_EPON_CFG_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_PDWKUPH8_31_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH8_31_OFFSET )
+#define BBH_TX_3_EPON_CFG_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_PDWKUPH8_31_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH8_31_OFFSET )
+#define BBH_TX_4_EPON_CFG_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_PDWKUPH8_31_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH8_31_OFFSET )
+#define BBH_TX_5_EPON_CFG_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_PDWKUPH8_31_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_PDWKUPH8_31_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH8_31_OFFSET )
+#define BBH_TX_6_EPON_CFG_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_PDWKUPH8_31_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PDWKUPH8_31_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_PDWKUPH8_31_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_PDWKUPH8_31_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_PDWKUPH8_31_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r2             	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_24_31 */
+	uint32_t wkupthresh24_31	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_16_23 */
+	uint32_t wkupthresh16_23	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r0             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_8_15 */
+	uint32_t wkupthresh8_15 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDWKUPH8_31 ;
+#else
+typedef struct
+{	uint32_t wkupthresh8_15 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_8_15 */
+	uint32_t r0             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t wkupthresh16_23	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_16_23 */
+	uint32_t r1             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t wkupthresh24_31	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FIFO_wake_up_threshold_24_31 */
+	uint32_t r2             	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDWKUPH8_31 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_EMPTY_THRESHOLD                                                                    */
+/* The BBH manages 32 queues for EPON (FIFO per LLID). For each queue it manages a PD FI */
+/* FO. Usually, the BBH orders PDs from the Runner in RR between all queues. In EPON BBH */
+/* , if a FIFO occupancy is below this threshold, the queue will have higher priority in */
+/*  PD ordering arbitration (with RR between all the empty queues).  This configuration  */
+/* is global for all queues.  Relevant only for EPON BBH.                                */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_CFG_PDEMPTY_R1_DEFAULT_VALUE                ( 0x0 )
+#define BBH_TX_EPON_CFG_PDEMPTY_R1_DEFAULT_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_TX_EPON_CFG_PDEMPTY_EMPTY_MIN_VALUE                 ( 0x0 )
+#define BBH_TX_EPON_CFG_PDEMPTY_EMPTY_DEFAULT_VALUE             ( 0x1 )
+#define BBH_TX_EPON_CFG_PDEMPTY_EMPTY_DEFAULT_VALUE_RESET_VALUE ( 0x1 )
+#define BBH_TX_EPON_CFG_PDEMPTY_EMPTY_MAX_VALUE                 ( 0xF )
+
+
+#define BBH_TX_EPON_CFG_PDEMPTY_OFFSET ( 0x00000054 )
+
+#define BBH_TX_0_EPON_CFG_PDEMPTY_ADDRESS   	( BBH_TX_0_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDEMPTY_OFFSET )
+#define BBH_TX_0_EPON_CFG_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_0_EPON_CFG_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_CFG_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_CFG_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_CFG_PDEMPTY_ADDRESS   	( BBH_TX_1_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDEMPTY_OFFSET )
+#define BBH_TX_1_EPON_CFG_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_1_EPON_CFG_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_CFG_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_CFG_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_CFG_PDEMPTY_ADDRESS   	( BBH_TX_2_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDEMPTY_OFFSET )
+#define BBH_TX_2_EPON_CFG_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_2_EPON_CFG_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_CFG_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_CFG_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_CFG_PDEMPTY_ADDRESS   	( BBH_TX_3_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDEMPTY_OFFSET )
+#define BBH_TX_3_EPON_CFG_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_3_EPON_CFG_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_CFG_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_CFG_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_CFG_PDEMPTY_ADDRESS   	( BBH_TX_4_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDEMPTY_OFFSET )
+#define BBH_TX_4_EPON_CFG_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_4_EPON_CFG_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_CFG_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_CFG_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_CFG_PDEMPTY_ADDRESS   	( BBH_TX_5_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDEMPTY_OFFSET )
+#define BBH_TX_5_EPON_CFG_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_5_EPON_CFG_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_CFG_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_CFG_PDEMPTY_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_CFG_PDEMPTY_ADDRESS   	( BBH_TX_6_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDEMPTY_OFFSET )
+#define BBH_TX_6_EPON_CFG_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_6_EPON_CFG_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_CFG_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_CFG_PDEMPTY_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_CFG_PDEMPTY_ARRAY [ ] ;
+
+#define BBH_TX_EPON_CFG_PDEMPTY_WRITE( i, v )	WRITE_32( BBH_TX_EPON_CFG_PDEMPTY_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_CFG_PDEMPTY_READ( i, r ) 	READ_32( BBH_TX_EPON_CFG_PDEMPTY_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1   	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Empty_thershold */
+	uint32_t empty	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDEMPTY ;
+#else
+typedef struct
+{	uint32_t empty	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Empty_thershold */
+	uint32_t r1   	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG_PDEMPTY ;
+#endif
+
+/*****************************************************************************************/
+/* DDR_PD_counter                                                                        */
+/* This counter counts the number of packets which were transmitted from the DDR.  It co */
+/* unts the packets for all TCONTs together.  This counter is cleared when read and free */
+/* zes when maximum value is reached.                                                    */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_DBG_DDRPD_DDRPD_DDR_PD_VALUE             ( 0x0 )
+#define BBH_TX_EPON_DBG_DDRPD_DDRPD_DDR_PD_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_EPON_DBG_DDRPD_OFFSET ( 0x00000004 )
+
+#define BBH_TX_0_EPON_DBG_DDRPD_ADDRESS   	( BBH_TX_0_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_DDRPD_OFFSET )
+#define BBH_TX_0_EPON_DBG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_0_EPON_DBG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_DBG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_DBG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_DBG_DDRPD_ADDRESS   	( BBH_TX_1_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_DDRPD_OFFSET )
+#define BBH_TX_1_EPON_DBG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_1_EPON_DBG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_DBG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_DBG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_DBG_DDRPD_ADDRESS   	( BBH_TX_2_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_DDRPD_OFFSET )
+#define BBH_TX_2_EPON_DBG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_2_EPON_DBG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_DBG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_DBG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_DBG_DDRPD_ADDRESS   	( BBH_TX_3_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_DDRPD_OFFSET )
+#define BBH_TX_3_EPON_DBG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_3_EPON_DBG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_DBG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_DBG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_DBG_DDRPD_ADDRESS   	( BBH_TX_4_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_DDRPD_OFFSET )
+#define BBH_TX_4_EPON_DBG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_4_EPON_DBG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_DBG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_DBG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_DBG_DDRPD_ADDRESS   	( BBH_TX_5_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_DDRPD_OFFSET )
+#define BBH_TX_5_EPON_DBG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_5_EPON_DBG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_DBG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_DBG_DDRPD_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_DBG_DDRPD_ADDRESS   	( BBH_TX_6_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_DDRPD_OFFSET )
+#define BBH_TX_6_EPON_DBG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_6_EPON_DBG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_DBG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_DBG_DDRPD_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_DBG_DDRPD_ARRAY [ ] ;
+
+#define BBH_TX_EPON_DBG_DDRPD_WRITE( i, v )	WRITE_32( BBH_TX_EPON_DBG_DDRPD_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_DBG_DDRPD_READ( i, r ) 	READ_32( BBH_TX_EPON_DBG_DDRPD_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DDR_PD */
+	uint32_t ddrpd	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_DDRPD ;
+#else
+typedef struct
+{	uint32_t ddrpd	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_PD */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_DDRPD ;
+#endif
+
+/*****************************************************************************************/
+/* PD_DROP_counter                                                                       */
+/* This counter counts the number of PDs which were dropped due to PD FIFO full.  It cou */
+/* nts the packets for all TCONTs together.  This counter is cleared when read and freez */
+/* es when maximum value is reached.  This counter is relevant for Ethernet only.        */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_DBG_PDDROP_R1_RESERVED_VALUE               ( 0x0 )
+#define BBH_TX_EPON_DBG_PDDROP_R1_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_TX_EPON_DBG_PDDROP_PDDROP_PDDROP_VALUE             ( 0x0 )
+#define BBH_TX_EPON_DBG_PDDROP_PDDROP_PDDROP_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_EPON_DBG_PDDROP_OFFSET ( 0x00000008 )
+
+#define BBH_TX_0_EPON_DBG_PDDROP_ADDRESS   	( BBH_TX_0_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDDROP_OFFSET )
+#define BBH_TX_0_EPON_DBG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_0_EPON_DBG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_DBG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_DBG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_DBG_PDDROP_ADDRESS   	( BBH_TX_1_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDDROP_OFFSET )
+#define BBH_TX_1_EPON_DBG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_1_EPON_DBG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_DBG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_DBG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_DBG_PDDROP_ADDRESS   	( BBH_TX_2_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDDROP_OFFSET )
+#define BBH_TX_2_EPON_DBG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_2_EPON_DBG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_DBG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_DBG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_DBG_PDDROP_ADDRESS   	( BBH_TX_3_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDDROP_OFFSET )
+#define BBH_TX_3_EPON_DBG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_3_EPON_DBG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_DBG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_DBG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_DBG_PDDROP_ADDRESS   	( BBH_TX_4_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDDROP_OFFSET )
+#define BBH_TX_4_EPON_DBG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_4_EPON_DBG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_DBG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_DBG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_DBG_PDDROP_ADDRESS   	( BBH_TX_5_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDDROP_OFFSET )
+#define BBH_TX_5_EPON_DBG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_5_EPON_DBG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_DBG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_DBG_PDDROP_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_DBG_PDDROP_ADDRESS   	( BBH_TX_6_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDDROP_OFFSET )
+#define BBH_TX_6_EPON_DBG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_6_EPON_DBG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_DBG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_DBG_PDDROP_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_DBG_PDDROP_ARRAY [ ] ;
+
+#define BBH_TX_EPON_DBG_PDDROP_WRITE( i, v )	WRITE_32( BBH_TX_EPON_DBG_PDDROP_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_DBG_PDDROP_READ( i, r ) 	READ_32( BBH_TX_EPON_DBG_PDDROP_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1    	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_DROP */
+	uint32_t pddrop	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_PDDROP ;
+#else
+typedef struct
+{	uint32_t pddrop	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_DROP */
+	uint32_t r1    	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_PDDROP ;
+#endif
+
+/*****************************************************************************************/
+/* PD_equal_0_counter                                                                    */
+/* This counter counts the number of PDs with packet length equal zero.  It counts the p */
+/* ackets for all TCONTs together.  This counter is cleared when read and freezes when m */
+/* aximum value is reached.                                                              */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_DBG_PDEQ0_R1_RESERVED_VALUE             ( 0x0 )
+#define BBH_TX_EPON_DBG_PDEQ0_R1_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_EPON_DBG_PDEQ0_PDEQ0_PDEQ0_VALUE             ( 0x0 )
+#define BBH_TX_EPON_DBG_PDEQ0_PDEQ0_PDEQ0_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_EPON_DBG_PDEQ0_OFFSET ( 0x0000000C )
+
+#define BBH_TX_0_EPON_DBG_PDEQ0_ADDRESS   	( BBH_TX_0_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEQ0_OFFSET )
+#define BBH_TX_0_EPON_DBG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_0_EPON_DBG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_DBG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_DBG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_DBG_PDEQ0_ADDRESS   	( BBH_TX_1_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEQ0_OFFSET )
+#define BBH_TX_1_EPON_DBG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_1_EPON_DBG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_DBG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_DBG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_DBG_PDEQ0_ADDRESS   	( BBH_TX_2_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEQ0_OFFSET )
+#define BBH_TX_2_EPON_DBG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_2_EPON_DBG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_DBG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_DBG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_DBG_PDEQ0_ADDRESS   	( BBH_TX_3_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEQ0_OFFSET )
+#define BBH_TX_3_EPON_DBG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_3_EPON_DBG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_DBG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_DBG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_DBG_PDEQ0_ADDRESS   	( BBH_TX_4_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEQ0_OFFSET )
+#define BBH_TX_4_EPON_DBG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_4_EPON_DBG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_DBG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_DBG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_DBG_PDEQ0_ADDRESS   	( BBH_TX_5_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEQ0_OFFSET )
+#define BBH_TX_5_EPON_DBG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_5_EPON_DBG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_DBG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_DBG_PDEQ0_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_DBG_PDEQ0_ADDRESS   	( BBH_TX_6_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEQ0_OFFSET )
+#define BBH_TX_6_EPON_DBG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_6_EPON_DBG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_DBG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_DBG_PDEQ0_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_DBG_PDEQ0_ARRAY [ ] ;
+
+#define BBH_TX_EPON_DBG_PDEQ0_WRITE( i, v )	WRITE_32( BBH_TX_EPON_DBG_PDEQ0_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_DBG_PDEQ0_READ( i, r ) 	READ_32( BBH_TX_EPON_DBG_PDEQ0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1   	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_equal_0 */
+	uint32_t pdeq0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_PDEQ0 ;
+#else
+typedef struct
+{	uint32_t pdeq0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_equal_0 */
+	uint32_t r1   	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_PDEQ0 ;
+#endif
+
+/*****************************************************************************************/
+/* PD_Full_LSB                                                                           */
+/* Full indication of the PD FIFOs.                                                      */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_DBG_PDFULLLSB_PDFULL_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_EPON_DBG_PDFULLLSB_PDFULL_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_EPON_DBG_PDFULLLSB_OFFSET ( 0x00000020 )
+
+#define BBH_TX_0_EPON_DBG_PDFULLLSB_ADDRESS   	( BBH_TX_0_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDFULLLSB_OFFSET )
+#define BBH_TX_0_EPON_DBG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_0_EPON_DBG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_DBG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_DBG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_DBG_PDFULLLSB_ADDRESS   	( BBH_TX_1_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDFULLLSB_OFFSET )
+#define BBH_TX_1_EPON_DBG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_1_EPON_DBG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_DBG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_DBG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_DBG_PDFULLLSB_ADDRESS   	( BBH_TX_2_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDFULLLSB_OFFSET )
+#define BBH_TX_2_EPON_DBG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_2_EPON_DBG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_DBG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_DBG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_DBG_PDFULLLSB_ADDRESS   	( BBH_TX_3_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDFULLLSB_OFFSET )
+#define BBH_TX_3_EPON_DBG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_3_EPON_DBG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_DBG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_DBG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_DBG_PDFULLLSB_ADDRESS   	( BBH_TX_4_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDFULLLSB_OFFSET )
+#define BBH_TX_4_EPON_DBG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_4_EPON_DBG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_DBG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_DBG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_DBG_PDFULLLSB_ADDRESS   	( BBH_TX_5_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDFULLLSB_OFFSET )
+#define BBH_TX_5_EPON_DBG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_5_EPON_DBG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_DBG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_DBG_PDFULLLSB_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_DBG_PDFULLLSB_ADDRESS   	( BBH_TX_6_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDFULLLSB_OFFSET )
+#define BBH_TX_6_EPON_DBG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_6_EPON_DBG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_DBG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_DBG_PDFULLLSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_DBG_PDFULLLSB_ARRAY [ ] ;
+
+#define BBH_TX_EPON_DBG_PDFULLLSB_WRITE( i, v )	WRITE_32( BBH_TX_EPON_DBG_PDFULLLSB_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_DBG_PDFULLLSB_READ( i, r ) 	READ_32( BBH_TX_EPON_DBG_PDFULLLSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PD_full */
+	uint32_t pdfull	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_PDFULLLSB ;
+#else
+typedef struct
+{	uint32_t pdfull	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_full */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_PDFULLLSB ;
+#endif
+
+/*****************************************************************************************/
+/* PD_empty_LSB                                                                          */
+/* Empty indication of the PD FIFOs.                                                     */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_DBG_PDEMPTYLSB_PDEMPTY_DEFAULT_VALUE             ( 0xFFFFFFFF )
+#define BBH_TX_EPON_DBG_PDEMPTYLSB_PDEMPTY_DEFAULT_VALUE_RESET_VALUE ( 0xFFFFFFFF )
+
+
+#define BBH_TX_EPON_DBG_PDEMPTYLSB_OFFSET ( 0x00000028 )
+
+#define BBH_TX_0_EPON_DBG_PDEMPTYLSB_ADDRESS   	( BBH_TX_0_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_0_EPON_DBG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_0_EPON_DBG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_DBG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_DBG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_DBG_PDEMPTYLSB_ADDRESS   	( BBH_TX_1_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_1_EPON_DBG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_1_EPON_DBG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_DBG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_DBG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_DBG_PDEMPTYLSB_ADDRESS   	( BBH_TX_2_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_2_EPON_DBG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_2_EPON_DBG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_DBG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_DBG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_DBG_PDEMPTYLSB_ADDRESS   	( BBH_TX_3_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_3_EPON_DBG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_3_EPON_DBG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_DBG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_DBG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_DBG_PDEMPTYLSB_ADDRESS   	( BBH_TX_4_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_4_EPON_DBG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_4_EPON_DBG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_DBG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_DBG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_DBG_PDEMPTYLSB_ADDRESS   	( BBH_TX_5_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_5_EPON_DBG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_5_EPON_DBG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_DBG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_DBG_PDEMPTYLSB_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_DBG_PDEMPTYLSB_ADDRESS   	( BBH_TX_6_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_6_EPON_DBG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_6_EPON_DBG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_DBG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_DBG_PDEMPTYLSB_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_DBG_PDEMPTYLSB_ARRAY [ ] ;
+
+#define BBH_TX_EPON_DBG_PDEMPTYLSB_WRITE( i, v )	WRITE_32( BBH_TX_EPON_DBG_PDEMPTYLSB_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_DBG_PDEMPTYLSB_READ( i, r ) 	READ_32( BBH_TX_EPON_DBG_PDEMPTYLSB_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PD_empty */
+	uint32_t pdempty	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_PDEMPTYLSB ;
+#else
+typedef struct
+{	uint32_t pdempty	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_empty */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_PDEMPTYLSB ;
+#endif
+
+/*****************************************************************************************/
+/* EPON_PD_VALID                                                                         */
+/* The BBH manages 32 queues. For each queue it manages a PD FIFO.   A total of 256 PDs  */
+/* are available for all queue.  The SW may read these PDs.  The PD valid register indic */
+/* ates whether the relevant PD is valid.  The first register refers to PDs 0-31.  The s */
+/* econd register refers to PDs 32-63 and so on.                                         */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_DBG_PDVALID_VALID_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_EPON_DBG_PDVALID_VALID_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_EPON_DBG_PDVALID_OFFSET ( 0x000000D0 )
+
+#define BBH_TX_0_EPON_DBG_PDVALID_ADDRESS        	( BBH_TX_0_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDVALID_OFFSET )
+#define BBH_TX_0_EPON_DBG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_EPON_DBG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_0_EPON_DBG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_EPON_DBG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_EPON_DBG_PDVALID_ADDRESS        	( BBH_TX_1_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDVALID_OFFSET )
+#define BBH_TX_1_EPON_DBG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_EPON_DBG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_1_EPON_DBG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_EPON_DBG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_EPON_DBG_PDVALID_ADDRESS        	( BBH_TX_2_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDVALID_OFFSET )
+#define BBH_TX_2_EPON_DBG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_EPON_DBG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_2_EPON_DBG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_EPON_DBG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_EPON_DBG_PDVALID_ADDRESS        	( BBH_TX_3_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDVALID_OFFSET )
+#define BBH_TX_3_EPON_DBG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_EPON_DBG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_3_EPON_DBG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_EPON_DBG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_EPON_DBG_PDVALID_ADDRESS        	( BBH_TX_4_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDVALID_OFFSET )
+#define BBH_TX_4_EPON_DBG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_EPON_DBG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_4_EPON_DBG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_EPON_DBG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_EPON_DBG_PDVALID_ADDRESS        	( BBH_TX_5_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDVALID_OFFSET )
+#define BBH_TX_5_EPON_DBG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_EPON_DBG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_5_EPON_DBG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_EPON_DBG_PDVALID_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_EPON_DBG_PDVALID_ADDRESS        	( BBH_TX_6_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDVALID_OFFSET )
+#define BBH_TX_6_EPON_DBG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_EPON_DBG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_6_EPON_DBG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_EPON_DBG_PDVALID_ADDRESS ), (i), (v) )
+
+
+extern uint32_t BBH_TX_EPON_DBG_PDVALID_ARRAY [ ] ;
+
+#define BBH_TX_EPON_DBG_PDVALID_WRITE( i, k, v )	WRITE_I_32( BBH_TX_EPON_DBG_PDVALID_ARRAY [ i ], (k), (v) )
+#define BBH_TX_EPON_DBG_PDVALID_READ( i, k, r ) 	READ_I_32( BBH_TX_EPON_DBG_PDVALID_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* valid */
+	uint32_t valid	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_PDVALID ;
+#else
+typedef struct
+{	uint32_t valid	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* valid */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_PDVALID ;
+#endif
+
+/*****************************************************************************************/
+/* REQ_length_error_counter                                                              */
+/* This counter counts the number of times a length error (mismatch between a request fr */
+/* om the MAC and a PD from the Runner) occured.  This counter is cleared when read and  */
+/* freezes when maximum value is reached.                                                */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_DBG_LENERR_R1_DEFAULT_VALUE                 ( 0x0 )
+#define BBH_TX_EPON_DBG_LENERR_R1_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define BBH_TX_EPON_DBG_LENERR_LENERR_LEN_ERR_VALUE             ( 0x0 )
+#define BBH_TX_EPON_DBG_LENERR_LENERR_LEN_ERR_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_EPON_DBG_LENERR_OFFSET ( 0x000000F0 )
+
+#define BBH_TX_0_EPON_DBG_LENERR_ADDRESS   	( BBH_TX_0_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_LENERR_OFFSET )
+#define BBH_TX_0_EPON_DBG_LENERR_READ( r ) 	READ_32( ( BBH_TX_0_EPON_DBG_LENERR_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_DBG_LENERR_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_DBG_LENERR_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_DBG_LENERR_ADDRESS   	( BBH_TX_1_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_LENERR_OFFSET )
+#define BBH_TX_1_EPON_DBG_LENERR_READ( r ) 	READ_32( ( BBH_TX_1_EPON_DBG_LENERR_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_DBG_LENERR_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_DBG_LENERR_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_DBG_LENERR_ADDRESS   	( BBH_TX_2_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_LENERR_OFFSET )
+#define BBH_TX_2_EPON_DBG_LENERR_READ( r ) 	READ_32( ( BBH_TX_2_EPON_DBG_LENERR_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_DBG_LENERR_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_DBG_LENERR_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_DBG_LENERR_ADDRESS   	( BBH_TX_3_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_LENERR_OFFSET )
+#define BBH_TX_3_EPON_DBG_LENERR_READ( r ) 	READ_32( ( BBH_TX_3_EPON_DBG_LENERR_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_DBG_LENERR_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_DBG_LENERR_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_DBG_LENERR_ADDRESS   	( BBH_TX_4_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_LENERR_OFFSET )
+#define BBH_TX_4_EPON_DBG_LENERR_READ( r ) 	READ_32( ( BBH_TX_4_EPON_DBG_LENERR_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_DBG_LENERR_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_DBG_LENERR_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_DBG_LENERR_ADDRESS   	( BBH_TX_5_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_LENERR_OFFSET )
+#define BBH_TX_5_EPON_DBG_LENERR_READ( r ) 	READ_32( ( BBH_TX_5_EPON_DBG_LENERR_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_DBG_LENERR_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_DBG_LENERR_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_DBG_LENERR_ADDRESS   	( BBH_TX_6_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_LENERR_OFFSET )
+#define BBH_TX_6_EPON_DBG_LENERR_READ( r ) 	READ_32( ( BBH_TX_6_EPON_DBG_LENERR_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_DBG_LENERR_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_DBG_LENERR_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_DBG_LENERR_ARRAY [ ] ;
+
+#define BBH_TX_EPON_DBG_LENERR_WRITE( i, v )	WRITE_32( BBH_TX_EPON_DBG_LENERR_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_DBG_LENERR_READ( i, r ) 	READ_32( BBH_TX_EPON_DBG_LENERR_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1    	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LEN_ERR */
+	uint32_t lenerr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_LENERR ;
+#else
+typedef struct
+{	uint32_t lenerr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LEN_ERR */
+	uint32_t r1    	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_LENERR ;
+#endif
+
+/*****************************************************************************************/
+/* Flushed_packets_counter                                                               */
+/* This counter counts the number of packets that were flushed (bn was released without  */
+/* sending the data to the EPON MAC) due to flush request.  The counter is global for al */
+/* l queues.  The counter is read clear.                                                 */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_DBG_FLUSHPKTS_R1_DEFAULT_VALUE                     ( 0x0 )
+#define BBH_TX_EPON_DBG_FLUSHPKTS_R1_DEFAULT_VALUE_RESET_VALUE         ( 0x0 )
+#define BBH_TX_EPON_DBG_FLUSHPKTS_FLSHPKTS_FLSH_PKTS_VALUE             ( 0x0 )
+#define BBH_TX_EPON_DBG_FLUSHPKTS_FLSHPKTS_FLSH_PKTS_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_EPON_DBG_FLUSHPKTS_OFFSET ( 0x000000F4 )
+
+#define BBH_TX_0_EPON_DBG_FLUSHPKTS_ADDRESS   	( BBH_TX_0_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_FLUSHPKTS_OFFSET )
+#define BBH_TX_0_EPON_DBG_FLUSHPKTS_READ( r ) 	READ_32( ( BBH_TX_0_EPON_DBG_FLUSHPKTS_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_DBG_FLUSHPKTS_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_DBG_FLUSHPKTS_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_DBG_FLUSHPKTS_ADDRESS   	( BBH_TX_1_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_FLUSHPKTS_OFFSET )
+#define BBH_TX_1_EPON_DBG_FLUSHPKTS_READ( r ) 	READ_32( ( BBH_TX_1_EPON_DBG_FLUSHPKTS_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_DBG_FLUSHPKTS_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_DBG_FLUSHPKTS_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_DBG_FLUSHPKTS_ADDRESS   	( BBH_TX_2_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_FLUSHPKTS_OFFSET )
+#define BBH_TX_2_EPON_DBG_FLUSHPKTS_READ( r ) 	READ_32( ( BBH_TX_2_EPON_DBG_FLUSHPKTS_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_DBG_FLUSHPKTS_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_DBG_FLUSHPKTS_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_DBG_FLUSHPKTS_ADDRESS   	( BBH_TX_3_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_FLUSHPKTS_OFFSET )
+#define BBH_TX_3_EPON_DBG_FLUSHPKTS_READ( r ) 	READ_32( ( BBH_TX_3_EPON_DBG_FLUSHPKTS_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_DBG_FLUSHPKTS_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_DBG_FLUSHPKTS_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_DBG_FLUSHPKTS_ADDRESS   	( BBH_TX_4_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_FLUSHPKTS_OFFSET )
+#define BBH_TX_4_EPON_DBG_FLUSHPKTS_READ( r ) 	READ_32( ( BBH_TX_4_EPON_DBG_FLUSHPKTS_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_DBG_FLUSHPKTS_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_DBG_FLUSHPKTS_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_DBG_FLUSHPKTS_ADDRESS   	( BBH_TX_5_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_FLUSHPKTS_OFFSET )
+#define BBH_TX_5_EPON_DBG_FLUSHPKTS_READ( r ) 	READ_32( ( BBH_TX_5_EPON_DBG_FLUSHPKTS_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_DBG_FLUSHPKTS_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_DBG_FLUSHPKTS_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_DBG_FLUSHPKTS_ADDRESS   	( BBH_TX_6_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_FLUSHPKTS_OFFSET )
+#define BBH_TX_6_EPON_DBG_FLUSHPKTS_READ( r ) 	READ_32( ( BBH_TX_6_EPON_DBG_FLUSHPKTS_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_DBG_FLUSHPKTS_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_DBG_FLUSHPKTS_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_DBG_FLUSHPKTS_ARRAY [ ] ;
+
+#define BBH_TX_EPON_DBG_FLUSHPKTS_WRITE( i, v )	WRITE_32( BBH_TX_EPON_DBG_FLUSHPKTS_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_DBG_FLUSHPKTS_READ( i, r ) 	READ_32( BBH_TX_EPON_DBG_FLUSHPKTS_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1      	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FLSH_PKTS */
+	uint32_t flshpkts	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_FLUSHPKTS ;
+#else
+typedef struct
+{	uint32_t flshpkts	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FLSH_PKTS */
+	uint32_t r1      	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_FLUSHPKTS ;
+#endif
+
+/*****************************************************************************************/
+/* REQ_FIFO_address                                                                      */
+/* Address in REQ FIFO for SW read. Total number of entries in the FIFO is 8.            */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_DBG_REQFIFOADD_R1_DEFAULT_VALUE               ( 0x0 )
+#define BBH_TX_EPON_DBG_REQFIFOADD_R1_DEFAULT_VALUE_RESET_VALUE   ( 0x0 )
+#define BBH_TX_EPON_DBG_REQFIFOADD_ADRS_ADDRESS_VALUE             ( 0x0 )
+#define BBH_TX_EPON_DBG_REQFIFOADD_ADRS_ADDRESS_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_EPON_DBG_REQFIFOADD_OFFSET ( 0x00000100 )
+
+#define BBH_TX_0_EPON_DBG_REQFIFOADD_ADDRESS   	( BBH_TX_0_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFOADD_OFFSET )
+#define BBH_TX_0_EPON_DBG_REQFIFOADD_READ( r ) 	READ_32( ( BBH_TX_0_EPON_DBG_REQFIFOADD_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_DBG_REQFIFOADD_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_DBG_REQFIFOADD_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_DBG_REQFIFOADD_ADDRESS   	( BBH_TX_1_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFOADD_OFFSET )
+#define BBH_TX_1_EPON_DBG_REQFIFOADD_READ( r ) 	READ_32( ( BBH_TX_1_EPON_DBG_REQFIFOADD_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_DBG_REQFIFOADD_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_DBG_REQFIFOADD_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_DBG_REQFIFOADD_ADDRESS   	( BBH_TX_2_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFOADD_OFFSET )
+#define BBH_TX_2_EPON_DBG_REQFIFOADD_READ( r ) 	READ_32( ( BBH_TX_2_EPON_DBG_REQFIFOADD_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_DBG_REQFIFOADD_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_DBG_REQFIFOADD_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_DBG_REQFIFOADD_ADDRESS   	( BBH_TX_3_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFOADD_OFFSET )
+#define BBH_TX_3_EPON_DBG_REQFIFOADD_READ( r ) 	READ_32( ( BBH_TX_3_EPON_DBG_REQFIFOADD_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_DBG_REQFIFOADD_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_DBG_REQFIFOADD_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_DBG_REQFIFOADD_ADDRESS   	( BBH_TX_4_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFOADD_OFFSET )
+#define BBH_TX_4_EPON_DBG_REQFIFOADD_READ( r ) 	READ_32( ( BBH_TX_4_EPON_DBG_REQFIFOADD_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_DBG_REQFIFOADD_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_DBG_REQFIFOADD_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_DBG_REQFIFOADD_ADDRESS   	( BBH_TX_5_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFOADD_OFFSET )
+#define BBH_TX_5_EPON_DBG_REQFIFOADD_READ( r ) 	READ_32( ( BBH_TX_5_EPON_DBG_REQFIFOADD_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_DBG_REQFIFOADD_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_DBG_REQFIFOADD_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_DBG_REQFIFOADD_ADDRESS   	( BBH_TX_6_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFOADD_OFFSET )
+#define BBH_TX_6_EPON_DBG_REQFIFOADD_READ( r ) 	READ_32( ( BBH_TX_6_EPON_DBG_REQFIFOADD_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_DBG_REQFIFOADD_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_DBG_REQFIFOADD_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_DBG_REQFIFOADD_ARRAY [ ] ;
+
+#define BBH_TX_EPON_DBG_REQFIFOADD_WRITE( i, v )	WRITE_32( BBH_TX_EPON_DBG_REQFIFOADD_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_DBG_REQFIFOADD_READ( i, r ) 	READ_32( BBH_TX_EPON_DBG_REQFIFOADD_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1  	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Address */
+	uint32_t adrs	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_REQFIFOADD ;
+#else
+typedef struct
+{	uint32_t adrs	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Address */
+	uint32_t r1  	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_REQFIFOADD ;
+#endif
+
+/*****************************************************************************************/
+/* REQ_FIFO_data                                                                         */
+/* Read data from the REQ FIFO                                                           */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_DBG_REQFIFODATA_R1_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_EPON_DBG_REQFIFODATA_R1_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define BBH_TX_EPON_DBG_REQFIFODATA_FLUSH_Q_VALUE                ( 0x0 )
+#define BBH_TX_EPON_DBG_REQFIFODATA_FLUSH_Q_VALUE_RESET_VALUE    ( 0x0 )
+#define BBH_TX_EPON_DBG_REQFIFODATA_LEN_Q_VALUE                  ( 0x0 )
+#define BBH_TX_EPON_DBG_REQFIFODATA_LEN_Q_VALUE_RESET_VALUE      ( 0x0 )
+#define BBH_TX_EPON_DBG_REQFIFODATA_Q_Q_VALUE                    ( 0x0 )
+#define BBH_TX_EPON_DBG_REQFIFODATA_Q_Q_VALUE_RESET_VALUE        ( 0x0 )
+
+
+#define BBH_TX_EPON_DBG_REQFIFODATA_OFFSET ( 0x00000104 )
+
+#define BBH_TX_0_EPON_DBG_REQFIFODATA_ADDRESS   	( BBH_TX_0_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFODATA_OFFSET )
+#define BBH_TX_0_EPON_DBG_REQFIFODATA_READ( r ) 	READ_32( ( BBH_TX_0_EPON_DBG_REQFIFODATA_ADDRESS ), (r) )
+#define BBH_TX_0_EPON_DBG_REQFIFODATA_WRITE( v )	WRITE_32( ( BBH_TX_0_EPON_DBG_REQFIFODATA_ADDRESS ), (v) )
+
+#define BBH_TX_1_EPON_DBG_REQFIFODATA_ADDRESS   	( BBH_TX_1_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFODATA_OFFSET )
+#define BBH_TX_1_EPON_DBG_REQFIFODATA_READ( r ) 	READ_32( ( BBH_TX_1_EPON_DBG_REQFIFODATA_ADDRESS ), (r) )
+#define BBH_TX_1_EPON_DBG_REQFIFODATA_WRITE( v )	WRITE_32( ( BBH_TX_1_EPON_DBG_REQFIFODATA_ADDRESS ), (v) )
+
+#define BBH_TX_2_EPON_DBG_REQFIFODATA_ADDRESS   	( BBH_TX_2_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFODATA_OFFSET )
+#define BBH_TX_2_EPON_DBG_REQFIFODATA_READ( r ) 	READ_32( ( BBH_TX_2_EPON_DBG_REQFIFODATA_ADDRESS ), (r) )
+#define BBH_TX_2_EPON_DBG_REQFIFODATA_WRITE( v )	WRITE_32( ( BBH_TX_2_EPON_DBG_REQFIFODATA_ADDRESS ), (v) )
+
+#define BBH_TX_3_EPON_DBG_REQFIFODATA_ADDRESS   	( BBH_TX_3_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFODATA_OFFSET )
+#define BBH_TX_3_EPON_DBG_REQFIFODATA_READ( r ) 	READ_32( ( BBH_TX_3_EPON_DBG_REQFIFODATA_ADDRESS ), (r) )
+#define BBH_TX_3_EPON_DBG_REQFIFODATA_WRITE( v )	WRITE_32( ( BBH_TX_3_EPON_DBG_REQFIFODATA_ADDRESS ), (v) )
+
+#define BBH_TX_4_EPON_DBG_REQFIFODATA_ADDRESS   	( BBH_TX_4_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFODATA_OFFSET )
+#define BBH_TX_4_EPON_DBG_REQFIFODATA_READ( r ) 	READ_32( ( BBH_TX_4_EPON_DBG_REQFIFODATA_ADDRESS ), (r) )
+#define BBH_TX_4_EPON_DBG_REQFIFODATA_WRITE( v )	WRITE_32( ( BBH_TX_4_EPON_DBG_REQFIFODATA_ADDRESS ), (v) )
+
+#define BBH_TX_5_EPON_DBG_REQFIFODATA_ADDRESS   	( BBH_TX_5_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFODATA_OFFSET )
+#define BBH_TX_5_EPON_DBG_REQFIFODATA_READ( r ) 	READ_32( ( BBH_TX_5_EPON_DBG_REQFIFODATA_ADDRESS ), (r) )
+#define BBH_TX_5_EPON_DBG_REQFIFODATA_WRITE( v )	WRITE_32( ( BBH_TX_5_EPON_DBG_REQFIFODATA_ADDRESS ), (v) )
+
+#define BBH_TX_6_EPON_DBG_REQFIFODATA_ADDRESS   	( BBH_TX_6_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFODATA_OFFSET )
+#define BBH_TX_6_EPON_DBG_REQFIFODATA_READ( r ) 	READ_32( ( BBH_TX_6_EPON_DBG_REQFIFODATA_ADDRESS ), (r) )
+#define BBH_TX_6_EPON_DBG_REQFIFODATA_WRITE( v )	WRITE_32( ( BBH_TX_6_EPON_DBG_REQFIFODATA_ADDRESS ), (v) )
+
+
+extern uint32_t BBH_TX_EPON_DBG_REQFIFODATA_ARRAY [ ] ;
+
+#define BBH_TX_EPON_DBG_REQFIFODATA_WRITE( i, v )	WRITE_32( BBH_TX_EPON_DBG_REQFIFODATA_ARRAY [ i ], (v) )
+#define BBH_TX_EPON_DBG_REQFIFODATA_READ( i, r ) 	READ_32( BBH_TX_EPON_DBG_REQFIFODATA_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Req_flush */
+	uint32_t flush	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Req_length */
+	uint32_t len  	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Req_Q */
+	uint32_t q    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_REQFIFODATA ;
+#else
+typedef struct
+{	uint32_t q    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Req_Q */
+	uint32_t len  	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Req_length */
+	uint32_t flush	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Req_flush */
+	uint32_t r1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG_REQFIFODATA ;
+#endif
+
+/*****************************************************************************************/
+/* PD_FIFO                                                                               */
+/* The SW may read the PD RAM.  This RAM includes a total of 256 PDs.  A special registe */
+/* r marks the valid PDs.  Each PD occupies 2 addresses of 32 bits - the odd address ref */
+/* ers to the LSB word of the entry.  Please refer to BBH LLD for the context of the PD. */
+/*****************************************************************************************/
+
+#define BBH_TX_EPON_STS_FIFO_PDFIFO_PDENTRY_DEFAULT_VALUE             ( 0x0 )
+#define BBH_TX_EPON_STS_FIFO_PDFIFO_PDENTRY_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BBH_TX_EPON_STS_FIFO_PDFIFO_OFFSET ( 0x00000000 )
+
+#define BBH_TX_0_EPON_STS_FIFO_PDFIFO_ADDRESS        	( BBH_TX_0_EPON_STS_FIFO_ADDRESS + BBH_TX_EPON_STS_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_0_EPON_STS_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_0_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_0_EPON_STS_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_0_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_1_EPON_STS_FIFO_PDFIFO_ADDRESS        	( BBH_TX_1_EPON_STS_FIFO_ADDRESS + BBH_TX_EPON_STS_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_1_EPON_STS_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_1_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_1_EPON_STS_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_1_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_2_EPON_STS_FIFO_PDFIFO_ADDRESS        	( BBH_TX_2_EPON_STS_FIFO_ADDRESS + BBH_TX_EPON_STS_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_2_EPON_STS_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_2_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_2_EPON_STS_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_2_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_3_EPON_STS_FIFO_PDFIFO_ADDRESS        	( BBH_TX_3_EPON_STS_FIFO_ADDRESS + BBH_TX_EPON_STS_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_3_EPON_STS_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_3_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_3_EPON_STS_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_3_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_4_EPON_STS_FIFO_PDFIFO_ADDRESS        	( BBH_TX_4_EPON_STS_FIFO_ADDRESS + BBH_TX_EPON_STS_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_4_EPON_STS_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_4_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_4_EPON_STS_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_4_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_5_EPON_STS_FIFO_PDFIFO_ADDRESS        	( BBH_TX_5_EPON_STS_FIFO_ADDRESS + BBH_TX_EPON_STS_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_5_EPON_STS_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_5_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_5_EPON_STS_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_5_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+#define BBH_TX_6_EPON_STS_FIFO_PDFIFO_ADDRESS        	( BBH_TX_6_EPON_STS_FIFO_ADDRESS + BBH_TX_EPON_STS_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_6_EPON_STS_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_6_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_6_EPON_STS_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_6_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+
+
+/* XXX: Temporary added for EPON bring-up manually, should be generated by Reggae automatically */
+
+#define BBH_RX_7_GENERAL_CONFIGURATION_OFFSET 	( 0x00000000 )
+#define BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS	( BBH_RX_7_OFFSET + BBH_RX_7_GENERAL_CONFIGURATION_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_OFFSET 	( 0x00000100 )
+#define BBH_RX_7_PM_COUNTERS_ADDRESS	( BBH_RX_7_OFFSET + BBH_RX_7_PM_COUNTERS_OFFSET )
+#define BBH_RX_7_DEBUG_OFFSET 	( 0x00000200 )
+#define BBH_RX_7_DEBUG_ADDRESS	( BBH_RX_7_OFFSET + BBH_RX_7_DEBUG_OFFSET )
+#define BBH_RX_7_PER_FLOW_PM_COUNTERS_OFFSET 	( 0x00000400 )
+#define BBH_RX_7_PER_FLOW_PM_COUNTERS_ADDRESS	( BBH_RX_7_OFFSET + BBH_RX_7_PER_FLOW_PM_COUNTERS_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_OFFSET 	( 0x00000000 )
+#define BBH_TX_7_CONFIGURATIONS_ADDRESS	( BBH_TX_7_OFFSET + BBH_TX_7_CONFIGURATIONS_OFFSET )
+#define BBH_TX_7_DEBUG_OFFSET 	( 0x00000100 )
+#define BBH_TX_7_DEBUG_ADDRESS	( BBH_TX_7_OFFSET + BBH_TX_7_DEBUG_OFFSET )
+#define BBH_TX_7_PD_FIFO_OFFSET 	( 0x00000200 )
+#define BBH_TX_7_PD_FIFO_ADDRESS	( BBH_TX_7_OFFSET + BBH_TX_7_PD_FIFO_OFFSET )
+#define BBH_TX_7_CONTEXT_OFFSET 	( 0x00000600 )
+#define BBH_TX_7_CONTEXT_ADDRESS	( BBH_TX_7_OFFSET + BBH_TX_7_CONTEXT_OFFSET )
+#define BBH_TX_7_EPON_PD_FIFO_OFFSET 	( 0x00000700 )
+#define BBH_TX_7_EPON_PD_FIFO_ADDRESS	( BBH_TX_7_OFFSET + BBH_TX_7_EPON_PD_FIFO_OFFSET )
+#define BBH_TX_7_EPON_CFG_OFFSET 	( 0x00001000 )
+#define BBH_TX_7_EPON_CFG_ADDRESS	( BBH_TX_7_OFFSET + BBH_TX_7_EPON_CFG_OFFSET )
+#define BBH_TX_7_EPON_DBG_OFFSET 	( 0x00001100 )
+#define BBH_TX_7_EPON_DBG_ADDRESS	( BBH_TX_7_OFFSET + BBH_TX_7_EPON_DBG_OFFSET )
+#define BBH_TX_7_EPON_STS_FIFO_OFFSET 	( 0x00001700 )
+#define BBH_TX_7_EPON_STS_FIFO_ADDRESS	( BBH_TX_7_OFFSET + BBH_TX_7_EPON_STS_FIFO_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_BBCFG_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_BBCFG_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_BBCFG_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_BBCFG_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_BBCFG1_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_BBCFG1_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_BBCFG1_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_BBCFG1_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_BBCFG1_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_DDRCFG_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DDRCFG_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_DDRCFG_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_DDRCFG_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_DDRCFG_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PDBASE_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDBASE_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PDBASE_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PDBASE_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_PDBASE_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PDSIZE_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PDSIZE_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PDSIZE_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PDSIZE_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_PDSIZE_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_RUNNERTASK_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_RUNNERTASK_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_DMAADDR_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMAADDR_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_DMAADDR_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_DMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_DMAADDR_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_DMACFG_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_DMACFG_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_DMACFG_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_DMACFG_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_DMACFG_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_SDMAADDR_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_SDMAADDR_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_SDMACFG_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_SDMACFG_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_SDMACFG_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_SDMACFG_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_SDMACFG_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MINPKT0_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKT0_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MINPKT0_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MINPKT0_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MINPKT0_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT0_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT0_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT1_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT1_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCFG_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCFG_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCFG_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCFG_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHCFG_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_FLOWCTRL_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_FLOWCTRL_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWTH_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWTH_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWSETS_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWSETS_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS0_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS0_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS1_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS1_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS2_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS2_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS3_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS3_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHOVERRIDE_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_IHOVERRIDE_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL0_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL0_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL1_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL1_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PLOAMCFG_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_PLOAMCFG_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_RXRSTRST_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_RXRSTRST_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_RXDBGSEL_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_RXDBGSEL_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS ), (v) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS   	( BBH_RX_7_GENERAL_CONFIGURATION_ADDRESS + BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_OFFSET )
+#define BBH_RX_7_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_READ( r ) 	READ_32( ( BBH_RX_7_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (r) )
+#define BBH_RX_7_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_WRITE( v )	WRITE_32( ( BBH_RX_7_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_SOPASOP_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_SOPASOP_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_SOPASOP_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_SOPASOP_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_SOPASOP_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_SOPASOP_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_THIRDFLOW_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_THIRDFLOW_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_THIRDFLOW_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_THIRDFLOW_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_THIRDFLOW_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_THIRDFLOW_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_INPKT_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_INPKT_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_INPKT_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_INPKT_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_INPKT_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_INPKT_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_TOOSHORT_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOSHORT_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_TOOSHORT_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_TOOSHORT_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_TOOSHORT_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_TOOSHORT_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_TOOLONG_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_TOOLONG_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_TOOLONG_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_TOOLONG_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_TOOLONG_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_TOOLONG_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_CRCERROR_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERROR_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_CRCERROR_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_CRCERROR_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_CRCERROR_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_CRCERROR_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_IPTV_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IPTV_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_IPTV_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_IPTV_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_IPTV_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_IPTV_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_RUNNERCONG_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_RUNNERCONG_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_RUNNERCONG_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_RUNNERCONG_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_RUNNERCONG_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_RUNNERCONG_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_NOBPMBN_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBN_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_NOBPMBN_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_NOBPMBN_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_NOBPMBN_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_NOBPMBN_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_NOSBPMSBN_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSBPMSBN_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_NOSBPMSBN_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_NOSBPMSBN_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_NOSBPMSBN_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_NODMACD_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NODMACD_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_NODMACD_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_NODMACD_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_NODMACD_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_NODMACD_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_NOSDMACD_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOSDMACD_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_NOSDMACD_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_NOSDMACD_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_NOSDMACD_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_NOSDMACD_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_IHDROPPLOAM_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_IHDROPPLOAM_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_IHDROPPLOAM_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_IHDROPPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_IHDROPPLOAM_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_NOBPMBNPLOAM_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_NOBPMBNPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_CRCERRORPLOAM_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_CRCERRORPLOAM_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_CRCERRORPLOAM_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_CRCERRORPLOAM_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_CRCERRORPLOAM_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_EPNFIFOVERUN_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPNFIFOVERUN_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_EPNFIFOVERUN_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_EPNFIFOVERUN_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_EPNFIFOVERUN_ADDRESS ), (v) )
+#define BBH_RX_7_PM_COUNTERS_EPONTYPERROR_ADDRESS   	( BBH_RX_7_PM_COUNTERS_ADDRESS + BBH_RX_PM_COUNTERS_EPONTYPERROR_OFFSET )
+#define BBH_RX_7_PM_COUNTERS_EPONTYPERROR_READ( r ) 	READ_32( ( BBH_RX_7_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (r) )
+#define BBH_RX_7_PM_COUNTERS_EPONTYPERROR_WRITE( v )	WRITE_32( ( BBH_RX_7_PM_COUNTERS_EPONTYPERROR_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_CNTXTX0LSB_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0LSB_OFFSET )
+#define BBH_RX_7_DEBUG_CNTXTX0LSB_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_CNTXTX0LSB_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_CNTXTX0LSB_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_CNTXTX0LSB_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_CNTXTX0MSB_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX0MSB_OFFSET )
+#define BBH_RX_7_DEBUG_CNTXTX0MSB_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_CNTXTX0MSB_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_CNTXTX0MSB_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_CNTXTX0MSB_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_CNTXTX1LSB_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1LSB_OFFSET )
+#define BBH_RX_7_DEBUG_CNTXTX1LSB_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_CNTXTX1LSB_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_CNTXTX1LSB_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_CNTXTX1LSB_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_CNTXTX1MSB_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_CNTXTX1MSB_OFFSET )
+#define BBH_RX_7_DEBUG_CNTXTX1MSB_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_CNTXTX1MSB_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_CNTXTX1MSB_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_CNTXTX1MSB_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_IHCNTXT0_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT0_OFFSET )
+#define BBH_RX_7_DEBUG_IHCNTXT0_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_IHCNTXT0_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_IHCNTXT0_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_IHCNTXT0_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_IHCNTXT1_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXT1_OFFSET )
+#define BBH_RX_7_DEBUG_IHCNTXT1_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_IHCNTXT1_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_IHCNTXT1_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_IHCNTXT1_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_IHCNTXTP_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_IHCNTXTP_OFFSET )
+#define BBH_RX_7_DEBUG_IHCNTXTP_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_IHCNTXTP_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_IHCNTXTP_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_IHCNTXTP_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_IHFREEBUF_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_IHFREEBUF_OFFSET )
+#define BBH_RX_7_DEBUG_IHFREEBUF_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_IHFREEBUF_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_IHFREEBUF_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_IHFREEBUF_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_PWUW_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_PWUW_OFFSET )
+#define BBH_RX_7_DEBUG_PWUW_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_PWUW_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_PWUW_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_PWUW_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_ACKCNT_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_ACKCNT_OFFSET )
+#define BBH_RX_7_DEBUG_ACKCNT_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_ACKCNT_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_ACKCNT_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_ACKCNT_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_RNRCNT_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_RNRCNT_OFFSET )
+#define BBH_RX_7_DEBUG_RNRCNT_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_RNRCNT_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_RNRCNT_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_RNRCNT_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_DBGVEC_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_DBGVEC_OFFSET )
+#define BBH_RX_7_DEBUG_DBGVEC_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_DBGVEC_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_DBGVEC_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_DBGVEC_ADDRESS ), (v) )
+#define BBH_RX_7_DEBUG_BNFIFO_ADDRESS        	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_BNFIFO_OFFSET )
+#define BBH_RX_7_DEBUG_BNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_7_DEBUG_BNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_7_DEBUG_BNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_7_DEBUG_BNFIFO_ADDRESS ), (i), (v) )
+#define BBH_RX_7_DEBUG_SBNFIFO_ADDRESS        	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_SBNFIFO_OFFSET )
+#define BBH_RX_7_DEBUG_SBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_7_DEBUG_SBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_7_DEBUG_SBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_7_DEBUG_SBNFIFO_ADDRESS ), (i), (v) )
+#define BBH_RX_7_DEBUG_RESFIFO_ADDRESS        	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_RESFIFO_OFFSET )
+#define BBH_RX_7_DEBUG_RESFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_RX_7_DEBUG_RESFIFO_ADDRESS ), (i), (r) )
+#define BBH_RX_7_DEBUG_RESFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_7_DEBUG_RESFIFO_ADDRESS ), (i), (v) )
+#define BBH_RX_7_DEBUG_ESUW_ADDRESS   	( BBH_RX_7_DEBUG_ADDRESS + BBH_RX_DEBUG_ESUW_OFFSET )
+#define BBH_RX_7_DEBUG_ESUW_READ( r ) 	READ_32( ( BBH_RX_7_DEBUG_ESUW_ADDRESS ), (r) )
+#define BBH_RX_7_DEBUG_ESUW_WRITE( v )	WRITE_32( ( BBH_RX_7_DEBUG_ESUW_ADDRESS ), (v) )
+#define BBH_RX_7_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS        	( BBH_RX_7_PER_FLOW_PM_COUNTERS_ADDRESS + BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_OFFSET )
+#define BBH_RX_7_PER_FLOW_PM_COUNTERS_PERFLOWPM_READ_I( r, i ) 	READ_I_32( ( BBH_RX_7_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (r) )
+#define BBH_RX_7_PER_FLOW_PM_COUNTERS_PERFLOWPM_WRITE_I( v, i )	WRITE_I_32( ( BBH_RX_7_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS ), (i), (v) )
+#define BBH_TX_7_CONFIGURATIONS_BBCFG_TX_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG_TX_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_BBCFG_TX_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_BBCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_BBCFG_TX_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_BBCFG1_TX_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_BBCFG1_TX_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_BBCFG1_TX_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_BBCFG1_TX_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_BBCFG1_TX_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_DDRCFG_TX_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRCFG_TX_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_DDRCFG_TX_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_DDRCFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_DDRCFG_TX_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_HNBASE_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_HNBASE_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_HNBASE_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_HNBASE_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_HNBASE_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_HNBASE_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_TASKLSB_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKLSB_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_TASKLSB_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_TASKMSB_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASKMSB_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_TASKMSB_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_TASK8_39_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TASK8_39_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_TASK8_39_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_PDSIZE0_7_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE0_7_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_PDSIZE0_7_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_PDSIZE0_7_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_PDSIZE0_7_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_PDSIZE8_39_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDSIZE8_39_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_PDSIZE8_39_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_PDSIZE8_39_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_PDSIZE8_39_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_PDBASE0_3_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE0_3_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_PDBASE0_3_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_PDBASE4_7_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE4_7_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_PDBASE4_7_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_PDBASE8_39_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDBASE8_39_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_PDBASE8_39_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_ADDRESS        	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PD_BYTE_TH_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_ADDRESS ), (i), (v) )
+#define BBH_TX_7_CONFIGURATIONS_DMACFG_TX_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DMACFG_TX_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_DMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_DMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_DMACFG_TX_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_SDMACFG_TX_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SDMACFG_TX_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_SDMACFG_TX_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_SDMACFG_TX_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_SDMACFG_TX_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_RUNNERCFG_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_RUNNERCFG_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_RUNNERCFG_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_MDUMODE_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MDUMODE_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_MDUMODE_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_DDRTMBASE_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DDRTMBASE_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_DDRTMBASE_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_DDRTMBASE_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_DDRTMBASE_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_DBGSEL_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_DBGSEL_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_DBGSEL_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_DBGSEL_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_DBGSEL_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_DBGSEL_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_TXRSTCMD_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_TXRSTCMD_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_TXRSTCMD_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_TXRSTCMD_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_TXRSTCMD_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_EMAC1588_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_EMAC1588_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_EMAC1588_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_EMAC1588_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_EMAC1588_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_EMAC1588_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_SBPMCFG_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_SBPMCFG_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_SBPMCFG_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_SBPMCFG_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_SBPMCFG_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_SBPMCFG_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_PDWKUPH0_7_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH0_7_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_PDWKUPH0_7_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_PDWKUPH0_7_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_PDWKUPH0_7_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_PDWKUPH8_31_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDWKUPH8_31_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_PDWKUPH8_31_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_PDEMPTY_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_PDEMPTY_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_PDEMPTY_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_ETHTT_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_ETHTT_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_ETHTT_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_ETHTT_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_ETHTT_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_ETHTT_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_MAXWLEN_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_MAXWLEN_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_MAXWLEN_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_MAXWLEN_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_MAXWLEN_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_MAXWLEN_ADDRESS ), (v) )
+#define BBH_TX_7_CONFIGURATIONS_FLUSH_ADDRESS   	( BBH_TX_7_CONFIGURATIONS_ADDRESS + BBH_TX_CONFIGURATIONS_FLUSH_OFFSET )
+#define BBH_TX_7_CONFIGURATIONS_FLUSH_READ( r ) 	READ_32( ( BBH_TX_7_CONFIGURATIONS_FLUSH_ADDRESS ), (r) )
+#define BBH_TX_7_CONFIGURATIONS_FLUSH_WRITE( v )	WRITE_32( ( BBH_TX_7_CONFIGURATIONS_FLUSH_ADDRESS ), (v) )
+#define BBH_TX_7_DEBUG_SRAMPD_ADDRESS   	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_SRAMPD_OFFSET )
+#define BBH_TX_7_DEBUG_SRAMPD_READ( r ) 	READ_32( ( BBH_TX_7_DEBUG_SRAMPD_ADDRESS ), (r) )
+#define BBH_TX_7_DEBUG_SRAMPD_WRITE( v )	WRITE_32( ( BBH_TX_7_DEBUG_SRAMPD_ADDRESS ), (v) )
+#define BBH_TX_7_DEBUG_DDRPD_ADDRESS   	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_DDRPD_OFFSET )
+#define BBH_TX_7_DEBUG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_7_DEBUG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_7_DEBUG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_7_DEBUG_DDRPD_ADDRESS ), (v) )
+#define BBH_TX_7_DEBUG_PDDROP_ADDRESS   	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_PDDROP_OFFSET )
+#define BBH_TX_7_DEBUG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_7_DEBUG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_7_DEBUG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_7_DEBUG_PDDROP_ADDRESS ), (v) )
+#define BBH_TX_7_DEBUG_PDEQ0_ADDRESS   	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEQ0_OFFSET )
+#define BBH_TX_7_DEBUG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_7_DEBUG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_7_DEBUG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_7_DEBUG_PDEQ0_ADDRESS ), (v) )
+#define BBH_TX_7_DEBUG_GETNEXTNULL_ADDRESS   	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTNULL_OFFSET )
+#define BBH_TX_7_DEBUG_GETNEXTNULL_READ( r ) 	READ_32( ( BBH_TX_7_DEBUG_GETNEXTNULL_ADDRESS ), (r) )
+#define BBH_TX_7_DEBUG_GETNEXTNULL_WRITE( v )	WRITE_32( ( BBH_TX_7_DEBUG_GETNEXTNULL_ADDRESS ), (v) )
+#define BBH_TX_7_DEBUG_PDFULLLSB_ADDRESS   	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLLSB_OFFSET )
+#define BBH_TX_7_DEBUG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_7_DEBUG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_7_DEBUG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_7_DEBUG_PDFULLLSB_ADDRESS ), (v) )
+#define BBH_TX_7_DEBUG_PDFULLMSB_ADDRESS   	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_PDFULLMSB_OFFSET )
+#define BBH_TX_7_DEBUG_PDFULLMSB_READ( r ) 	READ_32( ( BBH_TX_7_DEBUG_PDFULLMSB_ADDRESS ), (r) )
+#define BBH_TX_7_DEBUG_PDFULLMSB_WRITE( v )	WRITE_32( ( BBH_TX_7_DEBUG_PDFULLMSB_ADDRESS ), (v) )
+#define BBH_TX_7_DEBUG_PDEMPTYLSB_ADDRESS   	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_7_DEBUG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_7_DEBUG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_7_DEBUG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_7_DEBUG_PDEMPTYLSB_ADDRESS ), (v) )
+#define BBH_TX_7_DEBUG_PDEMPTYMSB_ADDRESS   	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_PDEMPTYMSB_OFFSET )
+#define BBH_TX_7_DEBUG_PDEMPTYMSB_READ( r ) 	READ_32( ( BBH_TX_7_DEBUG_PDEMPTYMSB_ADDRESS ), (r) )
+#define BBH_TX_7_DEBUG_PDEMPTYMSB_WRITE( v )	WRITE_32( ( BBH_TX_7_DEBUG_PDEMPTYMSB_ADDRESS ), (v) )
+#define BBH_TX_7_DEBUG_PDVALID_ADDRESS        	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_PDVALID_OFFSET )
+#define BBH_TX_7_DEBUG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_DEBUG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_7_DEBUG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_DEBUG_PDVALID_ADDRESS ), (i), (v) )
+#define BBH_TX_7_DEBUG_BPMFIFO_ADDRESS        	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_BPMFIFO_OFFSET )
+#define BBH_TX_7_DEBUG_BPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_DEBUG_BPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_7_DEBUG_BPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_DEBUG_BPMFIFO_ADDRESS ), (i), (v) )
+#define BBH_TX_7_DEBUG_SBPMFIFO_ADDRESS        	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_SBPMFIFO_OFFSET )
+#define BBH_TX_7_DEBUG_SBPMFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_DEBUG_SBPMFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_7_DEBUG_SBPMFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_DEBUG_SBPMFIFO_ADDRESS ), (i), (v) )
+#define BBH_TX_7_DEBUG_FIRSTBNFIFO_ADDRESS        	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_FIRSTBNFIFO_OFFSET )
+#define BBH_TX_7_DEBUG_FIRSTBNFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_7_DEBUG_FIRSTBNFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_DEBUG_FIRSTBNFIFO_ADDRESS ), (i), (v) )
+#define BBH_TX_7_DEBUG_GETNEXTFIFO_ADDRESS        	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_GETNEXTFIFO_OFFSET )
+#define BBH_TX_7_DEBUG_GETNEXTFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_7_DEBUG_GETNEXTFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_DEBUG_GETNEXTFIFO_ADDRESS ), (i), (v) )
+#define BBH_TX_7_DEBUG_DBGOUTREG_ADDRESS   	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_DBGOUTREG_OFFSET )
+#define BBH_TX_7_DEBUG_DBGOUTREG_READ( r ) 	READ_32( ( BBH_TX_7_DEBUG_DBGOUTREG_ADDRESS ), (r) )
+#define BBH_TX_7_DEBUG_DBGOUTREG_WRITE( v )	WRITE_32( ( BBH_TX_7_DEBUG_DBGOUTREG_ADDRESS ), (v) )
+#define BBH_TX_7_DEBUG_EPNPDVALID_ADDRESS        	( BBH_TX_7_DEBUG_ADDRESS + BBH_TX_DEBUG_EPNPDVALID_OFFSET )
+#define BBH_TX_7_DEBUG_EPNPDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_DEBUG_EPNPDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_7_DEBUG_EPNPDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_DEBUG_EPNPDVALID_ADDRESS ), (i), (v) )
+#define BBH_TX_7_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_7_PD_FIFO_ADDRESS + BBH_TX_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_7_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_7_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+#define BBH_TX_7_CONTEXT_SEGCNTXT_ADDRESS        	( BBH_TX_7_CONTEXT_ADDRESS + BBH_TX_CONTEXT_SEGCNTXT_OFFSET )
+#define BBH_TX_7_CONTEXT_SEGCNTXT_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_CONTEXT_SEGCNTXT_ADDRESS ), (i), (r) )
+#define BBH_TX_7_CONTEXT_SEGCNTXT_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_CONTEXT_SEGCNTXT_ADDRESS ), (i), (v) )
+#define BBH_TX_7_EPON_PD_FIFO_PDFIFO_ADDRESS        	( BBH_TX_7_EPON_PD_FIFO_ADDRESS + BBH_TX_EPON_PD_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_7_EPON_PD_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_7_EPON_PD_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_EPON_PD_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+#define BBH_TX_7_EPON_CFG_TASKLSB_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKLSB_OFFSET )
+#define BBH_TX_7_EPON_CFG_TASKLSB_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_TASKLSB_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_TASKLSB_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_TASKLSB_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_TASKMSB_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASKMSB_OFFSET )
+#define BBH_TX_7_EPON_CFG_TASKMSB_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_TASKMSB_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_TASKMSB_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_TASKMSB_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_TASK8_39_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_TASK8_39_OFFSET )
+#define BBH_TX_7_EPON_CFG_TASK8_39_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_TASK8_39_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_TASK8_39_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_TASK8_39_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PDSIZE0_3_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE0_3_OFFSET )
+#define BBH_TX_7_EPON_CFG_PDSIZE0_3_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_PDSIZE0_3_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_PDSIZE0_3_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_PDSIZE0_3_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PDSIZE4_7_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE4_7_OFFSET )
+#define BBH_TX_7_EPON_CFG_PDSIZE4_7_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_PDSIZE4_7_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_PDSIZE4_7_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_PDSIZE4_7_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PDSIZE8_31_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDSIZE8_31_OFFSET )
+#define BBH_TX_7_EPON_CFG_PDSIZE8_31_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_PDSIZE8_31_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_PDSIZE8_31_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_PDSIZE8_31_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PDBASE0_3_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE0_3_OFFSET )
+#define BBH_TX_7_EPON_CFG_PDBASE0_3_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_PDBASE0_3_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_PDBASE0_3_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_PDBASE0_3_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PDBASE4_7_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE4_7_OFFSET )
+#define BBH_TX_7_EPON_CFG_PDBASE4_7_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_PDBASE4_7_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_PDBASE4_7_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_PDBASE4_7_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PDBASE8_39_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDBASE8_39_OFFSET )
+#define BBH_TX_7_EPON_CFG_PDBASE8_39_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_PDBASE8_39_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_PDBASE8_39_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_PDBASE8_39_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PD_BYTE_TH_EN_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_EN_OFFSET )
+#define BBH_TX_7_EPON_CFG_PD_BYTE_TH_EN_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_PD_BYTE_TH_EN_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_PD_BYTE_TH_EN_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PD_BYTE_TH_ADDRESS        	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PD_BYTE_TH_OFFSET )
+#define BBH_TX_7_EPON_CFG_PD_BYTE_TH_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (r) )
+#define BBH_TX_7_EPON_CFG_PD_BYTE_TH_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_EPON_CFG_PD_BYTE_TH_ADDRESS ), (i), (v) )
+#define BBH_TX_7_EPON_CFG_RUNNERCFG_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_RUNNERCFG_OFFSET )
+#define BBH_TX_7_EPON_CFG_RUNNERCFG_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_RUNNERCFG_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_RUNNERCFG_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_RUNNERCFG_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_MDUMODE_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_MDUMODE_OFFSET )
+#define BBH_TX_7_EPON_CFG_MDUMODE_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_MDUMODE_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_MDUMODE_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_MDUMODE_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_REQCFG_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_REQCFG_OFFSET )
+#define BBH_TX_7_EPON_CFG_REQCFG_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_REQCFG_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_REQCFG_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_REQCFG_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PDWKUPH0_3_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH0_3_OFFSET )
+#define BBH_TX_7_EPON_CFG_PDWKUPH0_3_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_PDWKUPH0_3_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_PDWKUPH0_3_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_PDWKUPH0_3_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PDWKUPH4_7_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH4_7_OFFSET )
+#define BBH_TX_7_EPON_CFG_PDWKUPH4_7_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_PDWKUPH4_7_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_PDWKUPH4_7_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_PDWKUPH4_7_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PDWKUPH8_31_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDWKUPH8_31_OFFSET )
+#define BBH_TX_7_EPON_CFG_PDWKUPH8_31_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_PDWKUPH8_31_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_PDWKUPH8_31_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_PDWKUPH8_31_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_CFG_PDEMPTY_ADDRESS   	( BBH_TX_7_EPON_CFG_ADDRESS + BBH_TX_EPON_CFG_PDEMPTY_OFFSET )
+#define BBH_TX_7_EPON_CFG_PDEMPTY_READ( r ) 	READ_32( ( BBH_TX_7_EPON_CFG_PDEMPTY_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_CFG_PDEMPTY_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_CFG_PDEMPTY_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_DBG_DDRPD_ADDRESS   	( BBH_TX_7_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_DDRPD_OFFSET )
+#define BBH_TX_7_EPON_DBG_DDRPD_READ( r ) 	READ_32( ( BBH_TX_7_EPON_DBG_DDRPD_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_DBG_DDRPD_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_DBG_DDRPD_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_DBG_PDDROP_ADDRESS   	( BBH_TX_7_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDDROP_OFFSET )
+#define BBH_TX_7_EPON_DBG_PDDROP_READ( r ) 	READ_32( ( BBH_TX_7_EPON_DBG_PDDROP_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_DBG_PDDROP_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_DBG_PDDROP_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_DBG_PDEQ0_ADDRESS   	( BBH_TX_7_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEQ0_OFFSET )
+#define BBH_TX_7_EPON_DBG_PDEQ0_READ( r ) 	READ_32( ( BBH_TX_7_EPON_DBG_PDEQ0_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_DBG_PDEQ0_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_DBG_PDEQ0_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_DBG_PDFULLLSB_ADDRESS   	( BBH_TX_7_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDFULLLSB_OFFSET )
+#define BBH_TX_7_EPON_DBG_PDFULLLSB_READ( r ) 	READ_32( ( BBH_TX_7_EPON_DBG_PDFULLLSB_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_DBG_PDFULLLSB_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_DBG_PDFULLLSB_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_DBG_PDEMPTYLSB_ADDRESS   	( BBH_TX_7_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDEMPTYLSB_OFFSET )
+#define BBH_TX_7_EPON_DBG_PDEMPTYLSB_READ( r ) 	READ_32( ( BBH_TX_7_EPON_DBG_PDEMPTYLSB_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_DBG_PDEMPTYLSB_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_DBG_PDEMPTYLSB_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_DBG_PDVALID_ADDRESS        	( BBH_TX_7_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_PDVALID_OFFSET )
+#define BBH_TX_7_EPON_DBG_PDVALID_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_EPON_DBG_PDVALID_ADDRESS ), (i), (r) )
+#define BBH_TX_7_EPON_DBG_PDVALID_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_EPON_DBG_PDVALID_ADDRESS ), (i), (v) )
+#define BBH_TX_7_EPON_DBG_LENERR_ADDRESS   	( BBH_TX_7_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_LENERR_OFFSET )
+#define BBH_TX_7_EPON_DBG_LENERR_READ( r ) 	READ_32( ( BBH_TX_7_EPON_DBG_LENERR_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_DBG_LENERR_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_DBG_LENERR_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_DBG_FLUSHPKTS_ADDRESS   	( BBH_TX_7_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_FLUSHPKTS_OFFSET )
+#define BBH_TX_7_EPON_DBG_FLUSHPKTS_READ( r ) 	READ_32( ( BBH_TX_7_EPON_DBG_FLUSHPKTS_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_DBG_FLUSHPKTS_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_DBG_FLUSHPKTS_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_DBG_REQFIFOADD_ADDRESS   	( BBH_TX_7_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFOADD_OFFSET )
+#define BBH_TX_7_EPON_DBG_REQFIFOADD_READ( r ) 	READ_32( ( BBH_TX_7_EPON_DBG_REQFIFOADD_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_DBG_REQFIFOADD_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_DBG_REQFIFOADD_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_DBG_REQFIFODATA_ADDRESS   	( BBH_TX_7_EPON_DBG_ADDRESS + BBH_TX_EPON_DBG_REQFIFODATA_OFFSET )
+#define BBH_TX_7_EPON_DBG_REQFIFODATA_READ( r ) 	READ_32( ( BBH_TX_7_EPON_DBG_REQFIFODATA_ADDRESS ), (r) )
+#define BBH_TX_7_EPON_DBG_REQFIFODATA_WRITE( v )	WRITE_32( ( BBH_TX_7_EPON_DBG_REQFIFODATA_ADDRESS ), (v) )
+#define BBH_TX_7_EPON_STS_FIFO_PDFIFO_ADDRESS        	( BBH_TX_7_EPON_STS_FIFO_ADDRESS + BBH_TX_EPON_STS_FIFO_PDFIFO_OFFSET )
+#define BBH_TX_7_EPON_STS_FIFO_PDFIFO_READ_I( r, i ) 	READ_I_32( ( BBH_TX_7_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (r) )
+#define BBH_TX_7_EPON_STS_FIFO_PDFIFO_WRITE_I( v, i )	WRITE_I_32( ( BBH_TX_7_EPON_STS_FIFO_PDFIFO_ADDRESS ), (i), (v) )
+
+
+
+extern uint32_t BBH_TX_EPON_STS_FIFO_PDFIFO_ARRAY [ ] ;
+
+#define BBH_TX_EPON_STS_FIFO_PDFIFO_WRITE( i, k, v )	WRITE_I_32( BBH_TX_EPON_STS_FIFO_PDFIFO_ARRAY [ i ], (k), (v) )
+#define BBH_TX_EPON_STS_FIFO_PDFIFO_READ( i, k, r ) 	READ_I_32( BBH_TX_EPON_STS_FIFO_PDFIFO_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PD_entry */
+	uint32_t pdentry	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_STS_FIFO_PDFIFO ;
+#else
+typedef struct
+{	uint32_t pdentry	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_entry */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_STS_FIFO_PDFIFO ;
+#endif
+
+typedef struct
+{
+	/* Broad-Bus_configuration */
+	BBH_RX_GENERAL_CONFIGURATION_BBCFG bbcfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Broad-Bus_configuration */
+	BBH_RX_GENERAL_CONFIGURATION_BBCFG1 bbcfg1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_configuration */
+	BBH_RX_GENERAL_CONFIGURATION_DDRCFG ddrcfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_PD_base_address */
+	BBH_RX_GENERAL_CONFIGURATION_PDBASE pdbase __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ruuner_PD_size */
+	BBH_RX_GENERAL_CONFIGURATION_PDSIZE pdsize __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_task */
+	BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK runnertask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_address_configuration */
+	BBH_RX_GENERAL_CONFIGURATION_DMAADDR dmaaddr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_configuration */
+	BBH_RX_GENERAL_CONFIGURATION_DMACFG dmacfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA_address_configuration */
+	BBH_RX_GENERAL_CONFIGURATION_SDMAADDR sdmaaddr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA_configuration */
+	BBH_RX_GENERAL_CONFIGURATION_SDMACFG sdmacfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_Packet_size */
+	BBH_RX_GENERAL_CONFIGURATION_MINPKT0 minpkt0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_Packet_size_0 */
+	BBH_RX_GENERAL_CONFIGURATION_MAXPKT0 maxpkt0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_Packet_size_1 */
+	BBH_RX_GENERAL_CONFIGURATION_MAXPKT1 maxpkt1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_configuration */
+	BBH_RX_GENERAL_CONFIGURATION_IHCFG ihcfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flow_control_configuration */
+	BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL flowctrl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Per_flow_threshold. */
+	BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH perflowth __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Per_flow_sets. */
+	BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS perflowsets __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_select_0 */
+	BBH_RX_GENERAL_CONFIGURATION_IHCLASS0 ihclass0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_select_1 */
+	BBH_RX_GENERAL_CONFIGURATION_IHCLASS1 ihclass1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_select_2 */
+	BBH_RX_GENERAL_CONFIGURATION_IHCLASS2 ihclass2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_select_3 */
+	BBH_RX_GENERAL_CONFIGURATION_IHCLASS3 ihclass3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_class_override */
+	BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE ihoverride __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_packet_select_0 */
+	BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0 minpktsel0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Minimum_packet_select_1 */
+	BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1 minpktsel1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_packet_select_0 */
+	BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0 maxpktsel0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Maximum_packet_select_1 */
+	BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1 maxpktsel1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PLOAM_configurations */
+	BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG ploamcfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RX_reset_command */
+	BBH_RX_GENERAL_CONFIGURATION_RXRSTRST rxrstrst __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RX_debug_select */
+	BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL rxdbgsel __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reassembly_offset */
+	BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET reassemblyoffset __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_GENERAL_CONFIGURATION ;
+
+typedef struct
+{
+	/* SOP_after_SOP_error */
+	BBH_RX_PM_COUNTERS_SOPASOP sopasop __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Third_flow_error */
+	BBH_RX_PM_COUNTERS_THIRDFLOW thirdflow __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Incoming_packets */
+	BBH_RX_PM_COUNTERS_INPKT inpkt __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Too_short_error */
+	BBH_RX_PM_COUNTERS_TOOSHORT tooshort __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Too_long_error */
+	BBH_RX_PM_COUNTERS_TOOLONG toolong __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CRC_error */
+	BBH_RX_PM_COUNTERS_CRCERROR crcerror __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IPTV_error */
+	BBH_RX_PM_COUNTERS_IPTV iptv __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_congestion_error */
+	BBH_RX_PM_COUNTERS_RUNNERCONG runnercong __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* No_BPM_BN_error */
+	BBH_RX_PM_COUNTERS_NOBPMBN nobpmbn __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* NO_SBPM_SBN_error */
+	BBH_RX_PM_COUNTERS_NOSBPMSBN nosbpmsbn __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* No_DMA_CD_error */
+	BBH_RX_PM_COUNTERS_NODMACD nodmacd __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* No_SDMA_CD_error */
+	BBH_RX_PM_COUNTERS_NOSDMACD nosdmacd __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_drop_ploam_error */
+	BBH_RX_PM_COUNTERS_IHDROPPLOAM ihdropploam __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* No_BPM_BN_PLOAM_error */
+	BBH_RX_PM_COUNTERS_NOBPMBNPLOAM nobpmbnploam __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CRC_PLOAM_error */
+	BBH_RX_PM_COUNTERS_CRCERRORPLOAM crcerrorploam __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Epon_sync_fifo_overrun */
+	BBH_RX_PM_COUNTERS_EPNFIFOVERUN epnfifoverun __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Epon_sync_fifo_overrun_hdr */
+	BBH_RX_PM_COUNTERS_EPNFIFOVRNHDR epnfifovrnhdr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Epon_type_error */
+	BBH_RX_PM_COUNTERS_EPONTYPERROR epontyperror __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PM_COUNTERS ;
+
+/*****************************************************************************************/
+/* Debug features.                                                                       */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define BBH_RX_DEBUG_BNFIFO_NUMBER ( 8 )
+#define BBH_RX_DEBUG_SBNFIFO_NUMBER ( 8 )
+#define BBH_RX_DEBUG_RESFIFO_NUMBER ( 16 )
+typedef struct
+{
+	/* Context_0_LSB */
+	BBH_RX_DEBUG_CNTXTX0LSB cntxtx0lsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_0_MSB */
+	BBH_RX_DEBUG_CNTXTX0MSB cntxtx0msb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_1_LSB */
+	BBH_RX_DEBUG_CNTXTX1LSB cntxtx1lsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_1_MSB */
+	BBH_RX_DEBUG_CNTXTX1MSB cntxtx1msb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_context_0 */
+	BBH_RX_DEBUG_IHCNTXT0 ihcntxt0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_context_1 */
+	BBH_RX_DEBUG_IHCNTXT1 ihcntxt1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_context_PLOAM */
+	BBH_RX_DEBUG_IHCNTXTP ihcntxtp __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_free_buffer */
+	BBH_RX_DEBUG_IHFREEBUF ihfreebuf __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pre_wakeup_fifo_used_words */
+	BBH_RX_DEBUG_PWUW pwuw __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ACK_counters */
+	BBH_RX_DEBUG_ACKCNT ackcnt __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_counters */
+	BBH_RX_DEBUG_RNRCNT rnrcnt __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Debug_vector */
+	BBH_RX_DEBUG_DBGVEC dbgvec __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_BN_FIFO */
+	BBH_RX_DEBUG_BNFIFO bnfifo [ BBH_RX_DEBUG_BNFIFO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SRAM_BN_FIFO */
+	BBH_RX_DEBUG_SBNFIFO sbnfifo [ BBH_RX_DEBUG_SBNFIFO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_response_FIFO */
+	BBH_RX_DEBUG_RESFIFO resfifo [ BBH_RX_DEBUG_RESFIFO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Epon_sync_fifo_used_words */
+	BBH_RX_DEBUG_ESUW esuw __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_DEBUG ;
+
+/*****************************************************************************************/
+/* The BBH naintains per flow PM packets dropped by IH.  These registers are relevant fo */
+/* r GPON only.                                                                          */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_NUMBER ( 256 )
+typedef struct
+{
+	/* Per_flo_error */
+	BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM perflowpm [ BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX_PER_FLOW_PM_COUNTERS ;
+
+/*****************************************************************************************/
+/* These configurations and control registers contain parameters that determine the BBH  */
+/* TX functionality.                                                                     */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define BBH_TX_CONFIGURATIONS_PD_BYTE_TH_NUMBER ( 5 )
+typedef struct
+{
+	/* BB_Cfg */
+	BBH_TX_CONFIGURATIONS_BBCFG_TX bbcfg_tx __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BB_Cfg_1 */
+	BBH_TX_CONFIGURATIONS_BBCFG1_TX bbcfg1_tx __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_cfg */
+	BBH_TX_CONFIGURATIONS_DDRCFG_TX ddrcfg_tx __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HN_BASE */
+	BBH_TX_CONFIGURATIONS_HNBASE hnbase __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_numbers_LSB */
+	BBH_TX_CONFIGURATIONS_TASKLSB tasklsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_numbers_MSB */
+	BBH_TX_CONFIGURATIONS_TASKMSB taskmsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_numbers_8-39 */
+	BBH_TX_CONFIGURATIONS_TASK8_39 task8_39 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_FIFO_size_0_7 */
+	BBH_TX_CONFIGURATIONS_PDSIZE0_7 pdsize0_7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_FIFO_size_8_39 */
+	BBH_TX_CONFIGURATIONS_PDSIZE8_39 pdsize8_39 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_FIFO_base_0_3 */
+	BBH_TX_CONFIGURATIONS_PDBASE0_3 pdbase0_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_FIFO_base_4_7 */
+	BBH_TX_CONFIGURATIONS_PDBASE4_7 pdbase4_7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_FIFO_base_8_39 */
+	BBH_TX_CONFIGURATIONS_PDBASE8_39 pdbase8_39 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_bytes_threshold_EN */
+	BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN pd_byte_th_en __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_bytes_threshold */
+	BBH_TX_CONFIGURATIONS_PD_BYTE_TH pd_byte_th [ BBH_TX_CONFIGURATIONS_PD_BYTE_TH_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 4 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_configurations */
+	BBH_TX_CONFIGURATIONS_DMACFG_TX dmacfg_tx __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SDMA_configurations */
+	BBH_TX_CONFIGURATIONS_SDMACFG_TX sdmacfg_tx __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_configurations */
+	BBH_TX_CONFIGURATIONS_RUNNERCFG runnercfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MDU_CFG */
+	BBH_TX_CONFIGURATIONS_MDUMODE mdumode __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_TM_BASE */
+	BBH_TX_CONFIGURATIONS_DDRTMBASE ddrtmbase __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Debug_select */
+	BBH_TX_CONFIGURATIONS_DBGSEL dbgsel __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TX_reset_command */
+	BBH_TX_CONFIGURATIONS_TXRSTCMD txrstcmd __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC1588 */
+	BBH_TX_CONFIGURATIONS_EMAC1588 emac1588 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_configurations */
+	BBH_TX_CONFIGURATIONS_SBPMCFG sbpmcfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_WKUP_THRESH_0_7 */
+	BBH_TX_CONFIGURATIONS_PDWKUPH0_7 pdwkuph0_7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_WKUP_THRESH_8_31 */
+	BBH_TX_CONFIGURATIONS_PDWKUPH8_31 pdwkuph8_31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_EMPTY_THRESHOLD */
+	BBH_TX_CONFIGURATIONS_PDEMPTY pdempty __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH_TRANSMIT_TH */
+	BBH_TX_CONFIGURATIONS_ETHTT ethtt __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSL_MAXWLEN */
+	BBH_TX_CONFIGURATIONS_MAXWLEN maxwlen __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSL_FLUSH */
+	BBH_TX_CONFIGURATIONS_FLUSH flush __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONFIGURATIONS ;
+
+/*****************************************************************************************/
+/* Debug features                                                                        */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define BBH_TX_DEBUG_PDVALID_NUMBER ( 4 )
+#define BBH_TX_DEBUG_BPMFIFO_NUMBER ( 8 )
+#define BBH_TX_DEBUG_SBPMFIFO_NUMBER ( 4 )
+#define BBH_TX_DEBUG_FIRSTBNFIFO_NUMBER ( 8 )
+#define BBH_TX_DEBUG_GETNEXTFIFO_NUMBER ( 8 )
+#define BBH_TX_DEBUG_EPNPDVALID_NUMBER ( 8 )
+typedef struct
+{
+	/* SRAM_PD_counter */
+	BBH_TX_DEBUG_SRAMPD srampd __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_PD_counter */
+	BBH_TX_DEBUG_DDRPD ddrpd __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_DROP_counter */
+	BBH_TX_DEBUG_PDDROP pddrop __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_equal_0_counter */
+	BBH_TX_DEBUG_PDEQ0 pdeq0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Get_next_is_null_counter */
+	BBH_TX_DEBUG_GETNEXTNULL getnextnull __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 12 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_Full_LSB */
+	BBH_TX_DEBUG_PDFULLLSB pdfulllsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_Full_MSB */
+	BBH_TX_DEBUG_PDFULLMSB pdfullmsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_empty_LSB */
+	BBH_TX_DEBUG_PDEMPTYLSB pdemptylsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_empty_MSB */
+	BBH_TX_DEBUG_PDEMPTYMSB pdemptymsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_VALID */
+	BBH_TX_DEBUG_PDVALID pdvalid [ BBH_TX_DEBUG_PDVALID_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_FIFO */
+	BBH_TX_DEBUG_BPMFIFO bpmfifo [ BBH_TX_DEBUG_BPMFIFO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_FIFO */
+	BBH_TX_DEBUG_SBPMFIFO sbpmfifo [ BBH_TX_DEBUG_SBPMFIFO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved2 [ 16 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* First_BN_FIFO */
+	BBH_TX_DEBUG_FIRSTBNFIFO firstbnfifo [ BBH_TX_DEBUG_FIRSTBNFIFO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Get_next_FIFO */
+	BBH_TX_DEBUG_GETNEXTFIFO getnextfifo [ BBH_TX_DEBUG_GETNEXTFIFO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Debug_out_reg */
+	BBH_TX_DEBUG_DBGOUTREG dbgoutreg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved3 [ 12 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EPON_PD_VALID */
+	BBH_TX_DEBUG_EPNPDVALID epnpdvalid [ BBH_TX_DEBUG_EPNPDVALID_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_DEBUG ;
+
+/*****************************************************************************************/
+/* PD FIFOs RAM for GPON and ETH.  For EPON PD FIFOs, refer to EPON_PD_FIFO section.     */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define BBH_TX_PD_FIFO_PDFIFO_NUMBER ( 256 )
+typedef struct
+{
+	/* PD_FIFO */
+	BBH_TX_PD_FIFO_PDFIFO pdfifo [ BBH_TX_PD_FIFO_PDFIFO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_PD_FIFO ;
+
+/*****************************************************************************************/
+/* Segmentation context                                                                  */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define BBH_TX_CONTEXT_SEGCNTXT_NUMBER ( 40 )
+typedef struct
+{
+	/* Segmentation_context */
+	BBH_TX_CONTEXT_SEGCNTXT segcntxt [ BBH_TX_CONTEXT_SEGCNTXT_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_CONTEXT ;
+
+/*****************************************************************************************/
+/* PD FIFOs RAM for EPON.                                                                */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define BBH_TX_EPON_PD_FIFO_PDFIFO_NUMBER ( 512 )
+typedef struct
+{
+	/* PD_FIFO */
+	BBH_TX_EPON_PD_FIFO_PDFIFO pdfifo [ BBH_TX_EPON_PD_FIFO_PDFIFO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_PD_FIFO ;
+
+/*****************************************************************************************/
+/* These configurations and control registers contain parameters that determine the EPON */
+/*  BBH TX specific functionality. For global configurations, refer to Configurations se */
+/* ction.    In this section, all the configurations that are related to PDs are reffere */
+/* d to EPON status messages.                                                            */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define BBH_TX_EPON_CFG_PD_BYTE_TH_NUMBER ( 5 )
+typedef struct
+{
+	/* Task_numbers_LSB */
+	BBH_TX_EPON_CFG_TASKLSB tasklsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_numbers_MSB */
+	BBH_TX_EPON_CFG_TASKMSB taskmsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_numbers_8-39 */
+	BBH_TX_EPON_CFG_TASK8_39 task8_39 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_FIFO_size_0_3 */
+	BBH_TX_EPON_CFG_PDSIZE0_3 pdsize0_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_FIFO_size_4_7 */
+	BBH_TX_EPON_CFG_PDSIZE4_7 pdsize4_7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_FIFO_size_8_31 */
+	BBH_TX_EPON_CFG_PDSIZE8_31 pdsize8_31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_FIFO_base_0_3 */
+	BBH_TX_EPON_CFG_PDBASE0_3 pdbase0_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_FIFO_base_4_7 */
+	BBH_TX_EPON_CFG_PDBASE4_7 pdbase4_7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_FIFO_base_8_39 */
+	BBH_TX_EPON_CFG_PDBASE8_39 pdbase8_39 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_bytes_threshold_EN */
+	BBH_TX_EPON_CFG_PD_BYTE_TH_EN pd_byte_th_en __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_bytes_threshold */
+	BBH_TX_EPON_CFG_PD_BYTE_TH pd_byte_th [ BBH_TX_EPON_CFG_PD_BYTE_TH_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_configurations */
+	BBH_TX_EPON_CFG_RUNNERCFG runnercfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MDU_CFG */
+	BBH_TX_EPON_CFG_MDUMODE mdumode __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* REQ_CFG */
+	BBH_TX_EPON_CFG_REQCFG reqcfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_WKUP_THRESH_0_3 */
+	BBH_TX_EPON_CFG_PDWKUPH0_3 pdwkuph0_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_WKUP_THRESH_4_7 */
+	BBH_TX_EPON_CFG_PDWKUPH4_7 pdwkuph4_7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_WKUP_THRESH_8_31 */
+	BBH_TX_EPON_CFG_PDWKUPH8_31 pdwkuph8_31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_EMPTY_THRESHOLD */
+	BBH_TX_EPON_CFG_PDEMPTY pdempty __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_CFG ;
+
+/*****************************************************************************************/
+/* Debug features of EPON Status interface. In this section, a PD is reffered to Status  */
+/* message and not a regular packet descriptor.                                          */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define BBH_TX_EPON_DBG_PDVALID_NUMBER ( 8 )
+typedef struct
+{
+	/* DDR_PD_counter */
+	BBH_TX_EPON_DBG_DDRPD ddrpd __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_DROP_counter */
+	BBH_TX_EPON_DBG_PDDROP pddrop __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_equal_0_counter */
+	BBH_TX_EPON_DBG_PDEQ0 pdeq0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 16 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_Full_LSB */
+	BBH_TX_EPON_DBG_PDFULLLSB pdfulllsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved2 [ 4 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PD_empty_LSB */
+	BBH_TX_EPON_DBG_PDEMPTYLSB pdemptylsb __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved3 [ 164 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EPON_PD_VALID */
+	BBH_TX_EPON_DBG_PDVALID pdvalid [ BBH_TX_EPON_DBG_PDVALID_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* REQ_length_error_counter */
+	BBH_TX_EPON_DBG_LENERR lenerr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Flushed_packets_counter */
+	BBH_TX_EPON_DBG_FLUSHPKTS flushpkts __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved4 [ 8 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* REQ_FIFO_address */
+	BBH_TX_EPON_DBG_REQFIFOADD reqfifoadd __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* REQ_FIFO_data */
+	BBH_TX_EPON_DBG_REQFIFODATA reqfifodata __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_DBG ;
+
+/*****************************************************************************************/
+/* Status FIFOs RAM for EPON.                                                            */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define BBH_TX_EPON_STS_FIFO_PDFIFO_NUMBER ( 512 )
+typedef struct
+{
+	/* PD_FIFO */
+	BBH_TX_EPON_STS_FIFO_PDFIFO pdfifo [ BBH_TX_EPON_STS_FIFO_PDFIFO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX_EPON_STS_FIFO ;
+
+typedef struct
+{
+	/* general_configuration function */
+	BBH_RX_GENERAL_CONFIGURATION general_configuration __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved0 [ 136 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pm_counters function */
+	BBH_RX_PM_COUNTERS pm_counters __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 184 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* debug function */
+	BBH_RX_DEBUG debug __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved2 [ 332 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* per_flow_pm_counters function */
+	BBH_RX_PER_FLOW_PM_COUNTERS per_flow_pm_counters __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_RX ;
+
+typedef struct
+{
+	/* configurations function */
+	BBH_TX_CONFIGURATIONS configurations __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved0 [ 124 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* debug function */
+	BBH_TX_DEBUG debug __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 56 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pd_fifo function */
+	BBH_TX_PD_FIFO pd_fifo __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* context function */
+	BBH_TX_CONTEXT context __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved2 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* epon_pd_fifo function */
+	BBH_TX_EPON_PD_FIFO epon_pd_fifo __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved3 [ 256 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* epon_cfg function */
+	BBH_TX_EPON_CFG epon_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved4 [ 168 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* epon_dbg function */
+	BBH_TX_EPON_DBG epon_dbg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved5 [ 1468 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* epon_sts_fifo function */
+	BBH_TX_EPON_STS_FIFO epon_sts_fifo __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BBH_TX ;
+
+#define BBH_RX_NUMBER ( 7 )
+#define BBH_TX_NUMBER ( 7 )
+typedef struct
+{
+	/* RX */
+	BBH_RX rx [ BBH_RX_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 39564 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TX */
+	BBH_TX tx [ BBH_TX_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ 
+BBH_FOR_ALL ;
+#endif /* BBH_H_INCLUDED */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_bbh_arrays.c b/arch/arm/mach-bcmbca/rdp/rdp_bbh_arrays.c
new file mode 100755
index 0000000000..62e82994a8
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_bbh_arrays.c
@@ -0,0 +1,2241 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/ 
+/*  File automatically generated by Reggae at 17/01/2013  10:24:42   */
+
+#include "rdp_subsystem_common.h"
+#include "rdp_bbh.h"
+
+#ifdef __OREN__
+#define NUM_OF_BBH_BLOCKS 8
+#else
+#define NUM_OF_BBH_BLOCKS 7
+#endif
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_BBCFG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_BBCFG_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_BBCFG_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_BBCFG_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_BBCFG_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_BBCFG_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_BBCFG_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_BBCFG_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_BBCFG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_BBCFG_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_BBCFG1_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_BBCFG1_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_BBCFG1_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_BBCFG1_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_BBCFG1_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_BBCFG1_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_BBCFG1_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_BBCFG1_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_BBCFG1_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_BBCFG1_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_DDRCFG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_DDRCFG_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_DDRCFG_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_DDRCFG_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_DDRCFG_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_DDRCFG_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_DDRCFG_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_DDRCFG_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_DDRCFG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_DDRCFG_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_PDBASE_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_PDBASE_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_PDBASE_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_PDBASE_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_PDBASE_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_PDBASE_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_PDBASE_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_PDBASE_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_PDBASE_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_PDBASE_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_PDSIZE_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_PDSIZE_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_PDSIZE_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_PDSIZE_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_PDSIZE_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_PDSIZE_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_PDSIZE_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_PDSIZE_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_PDSIZE_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_PDSIZE_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_RUNNERTASK_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_DMAADDR_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_DMAADDR_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_DMAADDR_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_DMAADDR_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_DMAADDR_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_DMAADDR_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_DMAADDR_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_DMAADDR_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_DMAADDR_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_DMAADDR_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_DMACFG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_DMACFG_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_DMACFG_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_DMACFG_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_DMACFG_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_DMACFG_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_DMACFG_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_DMACFG_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_DMACFG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_DMACFG_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_SDMAADDR_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_SDMACFG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_SDMACFG_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_SDMACFG_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_SDMACFG_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_SDMACFG_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_SDMACFG_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_SDMACFG_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_SDMACFG_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_SDMACFG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_SDMACFG_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_MINPKT0_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_MINPKT0_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_MINPKT0_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_MINPKT0_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_MINPKT0_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_MINPKT0_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_MINPKT0_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_MINPKT0_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_MINPKT0_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_MINPKT0_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT0_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_MAXPKT1_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_IHCFG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_IHCFG_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_IHCFG_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_IHCFG_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_IHCFG_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_IHCFG_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_IHCFG_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_IHCFG_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_IHCFG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_IHCFG_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_FLOWCTRL_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWTH_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_PERFLOWSETS_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS0_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS1_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS2_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_IHCLASS3_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS,
+#ifdef __OREN__
+    BBH_RX_7_GENERAL_CONFIGURATION_IHOVERRIDE_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL0_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_MINPKTSEL1_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL0_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_MAXPKTSEL1_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_PLOAMCFG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_RXRSTRST_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_RXDBGSEL_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_ARRAY);
+
+uint32_t BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS,
+	BBH_RX_1_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS,
+	BBH_RX_2_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS,
+	BBH_RX_3_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS,
+	BBH_RX_4_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS,
+	BBH_RX_5_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS,
+	BBH_RX_6_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_SOPASOP_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_SOPASOP_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_SOPASOP_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_SOPASOP_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_SOPASOP_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_SOPASOP_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_SOPASOP_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_SOPASOP_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_SOPASOP_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_SOPASOP_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_THIRDFLOW_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_THIRDFLOW_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_THIRDFLOW_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_THIRDFLOW_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_THIRDFLOW_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_THIRDFLOW_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_THIRDFLOW_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_THIRDFLOW_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_THIRDFLOW_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_THIRDFLOW_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_INPKT_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_INPKT_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_INPKT_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_INPKT_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_INPKT_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_INPKT_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_INPKT_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_INPKT_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_INPKT_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_INPKT_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_TOOSHORT_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_TOOSHORT_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_TOOSHORT_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_TOOSHORT_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_TOOSHORT_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_TOOSHORT_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_TOOSHORT_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_TOOSHORT_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_TOOSHORT_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_TOOSHORT_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_TOOLONG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_TOOLONG_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_TOOLONG_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_TOOLONG_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_TOOLONG_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_TOOLONG_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_TOOLONG_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_TOOLONG_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_TOOLONG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_TOOLONG_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_CRCERROR_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_CRCERROR_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_CRCERROR_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_CRCERROR_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_CRCERROR_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_CRCERROR_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_CRCERROR_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_CRCERROR_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_CRCERROR_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_CRCERROR_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_IPTV_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_IPTV_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_IPTV_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_IPTV_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_IPTV_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_IPTV_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_IPTV_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_IPTV_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_IPTV_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_IPTV_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_RUNNERCONG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_RUNNERCONG_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_RUNNERCONG_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_RUNNERCONG_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_RUNNERCONG_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_RUNNERCONG_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_RUNNERCONG_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_RUNNERCONG_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_RUNNERCONG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_RUNNERCONG_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_NOBPMBN_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_NOBPMBN_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_NOBPMBN_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_NOBPMBN_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_NOBPMBN_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_NOBPMBN_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_NOBPMBN_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_NOBPMBN_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_NOBPMBN_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_NOBPMBN_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_NOSBPMSBN_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_NOSBPMSBN_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_NOSBPMSBN_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_NOSBPMSBN_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_NOSBPMSBN_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_NOSBPMSBN_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_NOSBPMSBN_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_NOSBPMSBN_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_NOSBPMSBN_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_NOSBPMSBN_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_NODMACD_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_NODMACD_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_NODMACD_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_NODMACD_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_NODMACD_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_NODMACD_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_NODMACD_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_NODMACD_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_NODMACD_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_NODMACD_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_NOSDMACD_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_NOSDMACD_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_NOSDMACD_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_NOSDMACD_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_NOSDMACD_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_NOSDMACD_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_NOSDMACD_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_NOSDMACD_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_NOSDMACD_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_NOSDMACD_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_IHDROPPLOAM_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_IHDROPPLOAM_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_IHDROPPLOAM_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_IHDROPPLOAM_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_IHDROPPLOAM_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_IHDROPPLOAM_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_IHDROPPLOAM_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_IHDROPPLOAM_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_IHDROPPLOAM_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_IHDROPPLOAM_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_NOBPMBNPLOAM_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_NOBPMBNPLOAM_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_CRCERRORPLOAM_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_CRCERRORPLOAM_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_CRCERRORPLOAM_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_CRCERRORPLOAM_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_CRCERRORPLOAM_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_CRCERRORPLOAM_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_CRCERRORPLOAM_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_CRCERRORPLOAM_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_CRCERRORPLOAM_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_CRCERRORPLOAM_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_EPNFIFOVERUN_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_EPNFIFOVERUN_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_EPNFIFOVERUN_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_EPNFIFOVERUN_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_EPNFIFOVERUN_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_EPNFIFOVERUN_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_EPNFIFOVERUN_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_EPNFIFOVERUN_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_EPNFIFOVERUN_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_EPNFIFOVERUN_ARRAY);
+
+uint32_t BBH_RX_PM_COUNTERS_EPONTYPERROR_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PM_COUNTERS_EPONTYPERROR_ADDRESS,
+	BBH_RX_1_PM_COUNTERS_EPONTYPERROR_ADDRESS,
+	BBH_RX_2_PM_COUNTERS_EPONTYPERROR_ADDRESS,
+	BBH_RX_3_PM_COUNTERS_EPONTYPERROR_ADDRESS,
+	BBH_RX_4_PM_COUNTERS_EPONTYPERROR_ADDRESS,
+	BBH_RX_5_PM_COUNTERS_EPONTYPERROR_ADDRESS,
+	BBH_RX_6_PM_COUNTERS_EPONTYPERROR_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PM_COUNTERS_EPONTYPERROR_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PM_COUNTERS_EPONTYPERROR_ARRAY);
+
+uint32_t BBH_RX_DEBUG_CNTXTX0LSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_CNTXTX0LSB_ADDRESS,
+	BBH_RX_1_DEBUG_CNTXTX0LSB_ADDRESS,
+	BBH_RX_2_DEBUG_CNTXTX0LSB_ADDRESS,
+	BBH_RX_3_DEBUG_CNTXTX0LSB_ADDRESS,
+	BBH_RX_4_DEBUG_CNTXTX0LSB_ADDRESS,
+	BBH_RX_5_DEBUG_CNTXTX0LSB_ADDRESS,
+	BBH_RX_6_DEBUG_CNTXTX0LSB_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_CNTXTX0LSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_CNTXTX0LSB_ARRAY);
+
+uint32_t BBH_RX_DEBUG_CNTXTX0MSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_CNTXTX0MSB_ADDRESS,
+	BBH_RX_1_DEBUG_CNTXTX0MSB_ADDRESS,
+	BBH_RX_2_DEBUG_CNTXTX0MSB_ADDRESS,
+	BBH_RX_3_DEBUG_CNTXTX0MSB_ADDRESS,
+	BBH_RX_4_DEBUG_CNTXTX0MSB_ADDRESS,
+	BBH_RX_5_DEBUG_CNTXTX0MSB_ADDRESS,
+	BBH_RX_6_DEBUG_CNTXTX0MSB_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_CNTXTX0MSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_CNTXTX0MSB_ARRAY);
+
+uint32_t BBH_RX_DEBUG_CNTXTX1LSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_CNTXTX1LSB_ADDRESS,
+	BBH_RX_1_DEBUG_CNTXTX1LSB_ADDRESS,
+	BBH_RX_2_DEBUG_CNTXTX1LSB_ADDRESS,
+	BBH_RX_3_DEBUG_CNTXTX1LSB_ADDRESS,
+	BBH_RX_4_DEBUG_CNTXTX1LSB_ADDRESS,
+	BBH_RX_5_DEBUG_CNTXTX1LSB_ADDRESS,
+	BBH_RX_6_DEBUG_CNTXTX1LSB_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_CNTXTX1LSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_CNTXTX1LSB_ARRAY);
+
+uint32_t BBH_RX_DEBUG_CNTXTX1MSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_CNTXTX1MSB_ADDRESS,
+	BBH_RX_1_DEBUG_CNTXTX1MSB_ADDRESS,
+	BBH_RX_2_DEBUG_CNTXTX1MSB_ADDRESS,
+	BBH_RX_3_DEBUG_CNTXTX1MSB_ADDRESS,
+	BBH_RX_4_DEBUG_CNTXTX1MSB_ADDRESS,
+	BBH_RX_5_DEBUG_CNTXTX1MSB_ADDRESS,
+	BBH_RX_6_DEBUG_CNTXTX1MSB_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_CNTXTX1MSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_CNTXTX1MSB_ARRAY);
+
+uint32_t BBH_RX_DEBUG_IHCNTXT0_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_IHCNTXT0_ADDRESS,
+	BBH_RX_1_DEBUG_IHCNTXT0_ADDRESS,
+	BBH_RX_2_DEBUG_IHCNTXT0_ADDRESS,
+	BBH_RX_3_DEBUG_IHCNTXT0_ADDRESS,
+	BBH_RX_4_DEBUG_IHCNTXT0_ADDRESS,
+	BBH_RX_5_DEBUG_IHCNTXT0_ADDRESS,
+	BBH_RX_6_DEBUG_IHCNTXT0_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_IHCNTXT0_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_IHCNTXT0_ARRAY);
+
+uint32_t BBH_RX_DEBUG_IHCNTXT1_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_IHCNTXT1_ADDRESS,
+	BBH_RX_1_DEBUG_IHCNTXT1_ADDRESS,
+	BBH_RX_2_DEBUG_IHCNTXT1_ADDRESS,
+	BBH_RX_3_DEBUG_IHCNTXT1_ADDRESS,
+	BBH_RX_4_DEBUG_IHCNTXT1_ADDRESS,
+	BBH_RX_5_DEBUG_IHCNTXT1_ADDRESS,
+	BBH_RX_6_DEBUG_IHCNTXT1_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_IHCNTXT1_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_IHCNTXT1_ARRAY);
+
+uint32_t BBH_RX_DEBUG_IHCNTXTP_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_IHCNTXTP_ADDRESS,
+	BBH_RX_1_DEBUG_IHCNTXTP_ADDRESS,
+	BBH_RX_2_DEBUG_IHCNTXTP_ADDRESS,
+	BBH_RX_3_DEBUG_IHCNTXTP_ADDRESS,
+	BBH_RX_4_DEBUG_IHCNTXTP_ADDRESS,
+	BBH_RX_5_DEBUG_IHCNTXTP_ADDRESS,
+	BBH_RX_6_DEBUG_IHCNTXTP_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_IHCNTXTP_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_IHCNTXTP_ARRAY);
+
+uint32_t BBH_RX_DEBUG_IHFREEBUF_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_IHFREEBUF_ADDRESS,
+	BBH_RX_1_DEBUG_IHFREEBUF_ADDRESS,
+	BBH_RX_2_DEBUG_IHFREEBUF_ADDRESS,
+	BBH_RX_3_DEBUG_IHFREEBUF_ADDRESS,
+	BBH_RX_4_DEBUG_IHFREEBUF_ADDRESS,
+	BBH_RX_5_DEBUG_IHFREEBUF_ADDRESS,
+	BBH_RX_6_DEBUG_IHFREEBUF_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_IHFREEBUF_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_IHFREEBUF_ARRAY);
+
+uint32_t BBH_RX_DEBUG_PWUW_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_PWUW_ADDRESS,
+	BBH_RX_1_DEBUG_PWUW_ADDRESS,
+	BBH_RX_2_DEBUG_PWUW_ADDRESS,
+	BBH_RX_3_DEBUG_PWUW_ADDRESS,
+	BBH_RX_4_DEBUG_PWUW_ADDRESS,
+	BBH_RX_5_DEBUG_PWUW_ADDRESS,
+	BBH_RX_6_DEBUG_PWUW_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_PWUW_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_PWUW_ARRAY);
+
+uint32_t BBH_RX_DEBUG_ACKCNT_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_ACKCNT_ADDRESS,
+	BBH_RX_1_DEBUG_ACKCNT_ADDRESS,
+	BBH_RX_2_DEBUG_ACKCNT_ADDRESS,
+	BBH_RX_3_DEBUG_ACKCNT_ADDRESS,
+	BBH_RX_4_DEBUG_ACKCNT_ADDRESS,
+	BBH_RX_5_DEBUG_ACKCNT_ADDRESS,
+	BBH_RX_6_DEBUG_ACKCNT_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_ACKCNT_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_ACKCNT_ARRAY);
+
+uint32_t BBH_RX_DEBUG_RNRCNT_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_RNRCNT_ADDRESS,
+	BBH_RX_1_DEBUG_RNRCNT_ADDRESS,
+	BBH_RX_2_DEBUG_RNRCNT_ADDRESS,
+	BBH_RX_3_DEBUG_RNRCNT_ADDRESS,
+	BBH_RX_4_DEBUG_RNRCNT_ADDRESS,
+	BBH_RX_5_DEBUG_RNRCNT_ADDRESS,
+	BBH_RX_6_DEBUG_RNRCNT_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_RNRCNT_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_RNRCNT_ARRAY);
+
+uint32_t BBH_RX_DEBUG_DBGVEC_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_DBGVEC_ADDRESS,
+	BBH_RX_1_DEBUG_DBGVEC_ADDRESS,
+	BBH_RX_2_DEBUG_DBGVEC_ADDRESS,
+	BBH_RX_3_DEBUG_DBGVEC_ADDRESS,
+	BBH_RX_4_DEBUG_DBGVEC_ADDRESS,
+	BBH_RX_5_DEBUG_DBGVEC_ADDRESS,
+	BBH_RX_6_DEBUG_DBGVEC_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_DBGVEC_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_DBGVEC_ARRAY);
+
+uint32_t BBH_RX_DEBUG_BNFIFO_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_BNFIFO_ADDRESS,
+	BBH_RX_1_DEBUG_BNFIFO_ADDRESS,
+	BBH_RX_2_DEBUG_BNFIFO_ADDRESS,
+	BBH_RX_3_DEBUG_BNFIFO_ADDRESS,
+	BBH_RX_4_DEBUG_BNFIFO_ADDRESS,
+	BBH_RX_5_DEBUG_BNFIFO_ADDRESS,
+	BBH_RX_6_DEBUG_BNFIFO_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_BNFIFO_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_BNFIFO_ARRAY);
+
+uint32_t BBH_RX_DEBUG_SBNFIFO_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_SBNFIFO_ADDRESS,
+	BBH_RX_1_DEBUG_SBNFIFO_ADDRESS,
+	BBH_RX_2_DEBUG_SBNFIFO_ADDRESS,
+	BBH_RX_3_DEBUG_SBNFIFO_ADDRESS,
+	BBH_RX_4_DEBUG_SBNFIFO_ADDRESS,
+	BBH_RX_5_DEBUG_SBNFIFO_ADDRESS,
+	BBH_RX_6_DEBUG_SBNFIFO_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_SBNFIFO_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_SBNFIFO_ARRAY);
+
+uint32_t BBH_RX_DEBUG_RESFIFO_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_RESFIFO_ADDRESS,
+	BBH_RX_1_DEBUG_RESFIFO_ADDRESS,
+	BBH_RX_2_DEBUG_RESFIFO_ADDRESS,
+	BBH_RX_3_DEBUG_RESFIFO_ADDRESS,
+	BBH_RX_4_DEBUG_RESFIFO_ADDRESS,
+	BBH_RX_5_DEBUG_RESFIFO_ADDRESS,
+	BBH_RX_6_DEBUG_RESFIFO_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_RESFIFO_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_RESFIFO_ARRAY);
+
+uint32_t BBH_RX_DEBUG_ESUW_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_DEBUG_ESUW_ADDRESS,
+	BBH_RX_1_DEBUG_ESUW_ADDRESS,
+	BBH_RX_2_DEBUG_ESUW_ADDRESS,
+	BBH_RX_3_DEBUG_ESUW_ADDRESS,
+	BBH_RX_4_DEBUG_ESUW_ADDRESS,
+	BBH_RX_5_DEBUG_ESUW_ADDRESS,
+	BBH_RX_6_DEBUG_ESUW_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_DEBUG_ESUW_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_DEBUG_ESUW_ARRAY);
+
+uint32_t BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_RX_0_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS,
+	BBH_RX_1_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS,
+	BBH_RX_2_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS,
+	BBH_RX_3_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS,
+	BBH_RX_4_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS,
+	BBH_RX_5_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS,
+	BBH_RX_6_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS,
+#ifdef __OREN__
+	BBH_RX_7_PER_FLOW_PM_COUNTERS_PERFLOWPM_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_RX_PER_FLOW_PM_COUNTERS_PERFLOWPM_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_BBCFG_TX_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_BBCFG_TX_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_BBCFG_TX_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_BBCFG_TX_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_BBCFG_TX_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_BBCFG_TX_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_BBCFG_TX_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_BBCFG_TX_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_BBCFG_TX_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_BBCFG_TX_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_BBCFG1_TX_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_BBCFG1_TX_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_BBCFG1_TX_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_BBCFG1_TX_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_BBCFG1_TX_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_BBCFG1_TX_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_BBCFG1_TX_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_BBCFG1_TX_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_BBCFG1_TX_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_BBCFG1_TX_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_DDRCFG_TX_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_DDRCFG_TX_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_DDRCFG_TX_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_DDRCFG_TX_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_DDRCFG_TX_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_DDRCFG_TX_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_DDRCFG_TX_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_DDRCFG_TX_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_DDRCFG_TX_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_DDRCFG_TX_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_HNBASE_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_HNBASE_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_HNBASE_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_HNBASE_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_HNBASE_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_HNBASE_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_HNBASE_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_HNBASE_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_HNBASE_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_HNBASE_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_TASKLSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_TASKLSB_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_TASKLSB_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_TASKLSB_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_TASKLSB_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_TASKLSB_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_TASKLSB_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_TASKLSB_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_TASKLSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_TASKLSB_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_TASKMSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_TASKMSB_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_TASKMSB_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_TASKMSB_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_TASKMSB_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_TASKMSB_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_TASKMSB_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_TASKMSB_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_TASKMSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_TASKMSB_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_TASK8_39_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_TASK8_39_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_TASK8_39_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_TASK8_39_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_TASK8_39_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_TASK8_39_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_TASK8_39_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_TASK8_39_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_TASK8_39_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_TASK8_39_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_PDSIZE0_7_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_PDSIZE0_7_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_PDSIZE0_7_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_PDSIZE0_7_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_PDSIZE0_7_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_PDSIZE0_7_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_PDSIZE0_7_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_PDSIZE0_7_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_PDSIZE0_7_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_PDSIZE0_7_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_PDSIZE8_39_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_PDSIZE8_39_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_PDSIZE8_39_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_PDSIZE8_39_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_PDSIZE8_39_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_PDSIZE8_39_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_PDSIZE8_39_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_PDSIZE8_39_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_PDSIZE8_39_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_PDSIZE8_39_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_PDBASE0_3_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_PDBASE0_3_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_PDBASE0_3_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_PDBASE0_3_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_PDBASE0_3_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_PDBASE0_3_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_PDBASE0_3_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_PDBASE0_3_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_PDBASE0_3_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_PDBASE0_3_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_PDBASE4_7_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_PDBASE4_7_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_PDBASE4_7_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_PDBASE4_7_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_PDBASE4_7_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_PDBASE4_7_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_PDBASE4_7_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_PDBASE4_7_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_PDBASE4_7_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_PDBASE4_7_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_PDBASE8_39_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_PDBASE8_39_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_PDBASE8_39_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_PDBASE8_39_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_PDBASE8_39_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_PDBASE8_39_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_PDBASE8_39_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_PDBASE8_39_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_PDBASE8_39_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_PDBASE8_39_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_EN_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_PD_BYTE_TH_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_PD_BYTE_TH_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_PD_BYTE_TH_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_PD_BYTE_TH_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_PD_BYTE_TH_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_PD_BYTE_TH_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_PD_BYTE_TH_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_PD_BYTE_TH_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_PD_BYTE_TH_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_PD_BYTE_TH_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_DMACFG_TX_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_DMACFG_TX_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_DMACFG_TX_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_DMACFG_TX_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_DMACFG_TX_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_DMACFG_TX_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_DMACFG_TX_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_DMACFG_TX_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_DMACFG_TX_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_DMACFG_TX_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_SDMACFG_TX_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_SDMACFG_TX_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_SDMACFG_TX_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_SDMACFG_TX_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_SDMACFG_TX_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_SDMACFG_TX_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_SDMACFG_TX_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_SDMACFG_TX_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_SDMACFG_TX_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_SDMACFG_TX_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_RUNNERCFG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_RUNNERCFG_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_RUNNERCFG_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_RUNNERCFG_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_RUNNERCFG_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_RUNNERCFG_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_RUNNERCFG_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_RUNNERCFG_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_RUNNERCFG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_RUNNERCFG_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_MDUMODE_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_MDUMODE_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_MDUMODE_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_MDUMODE_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_MDUMODE_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_MDUMODE_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_MDUMODE_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_MDUMODE_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_MDUMODE_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_MDUMODE_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_DDRTMBASE_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_DDRTMBASE_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_DDRTMBASE_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_DDRTMBASE_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_DDRTMBASE_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_DDRTMBASE_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_DDRTMBASE_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_DDRTMBASE_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_DDRTMBASE_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_DDRTMBASE_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_DBGSEL_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_DBGSEL_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_DBGSEL_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_DBGSEL_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_DBGSEL_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_DBGSEL_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_DBGSEL_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_DBGSEL_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_DBGSEL_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_DBGSEL_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_TXRSTCMD_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_TXRSTCMD_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_TXRSTCMD_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_TXRSTCMD_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_TXRSTCMD_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_TXRSTCMD_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_TXRSTCMD_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_TXRSTCMD_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_TXRSTCMD_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_TXRSTCMD_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_EMAC1588_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_EMAC1588_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_EMAC1588_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_EMAC1588_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_EMAC1588_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_EMAC1588_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_EMAC1588_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_EMAC1588_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_EMAC1588_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_EMAC1588_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_SBPMCFG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_SBPMCFG_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_SBPMCFG_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_SBPMCFG_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_SBPMCFG_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_SBPMCFG_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_SBPMCFG_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_SBPMCFG_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_SBPMCFG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_SBPMCFG_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_PDWKUPH0_7_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_PDWKUPH0_7_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_PDWKUPH0_7_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_PDWKUPH0_7_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_PDWKUPH0_7_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_PDWKUPH0_7_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_PDWKUPH0_7_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_PDWKUPH0_7_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_PDWKUPH0_7_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_PDWKUPH0_7_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_PDWKUPH8_31_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_PDWKUPH8_31_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_PDWKUPH8_31_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_PDWKUPH8_31_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_PDWKUPH8_31_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_PDWKUPH8_31_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_PDWKUPH8_31_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_PDWKUPH8_31_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_PDWKUPH8_31_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_PDWKUPH8_31_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_PDEMPTY_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_PDEMPTY_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_PDEMPTY_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_PDEMPTY_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_PDEMPTY_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_PDEMPTY_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_PDEMPTY_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_PDEMPTY_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_PDEMPTY_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_PDEMPTY_ARRAY);
+
+uint32_t BBH_TX_CONFIGURATIONS_ETHTT_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONFIGURATIONS_ETHTT_ADDRESS,
+	BBH_TX_1_CONFIGURATIONS_ETHTT_ADDRESS,
+	BBH_TX_2_CONFIGURATIONS_ETHTT_ADDRESS,
+	BBH_TX_3_CONFIGURATIONS_ETHTT_ADDRESS,
+	BBH_TX_4_CONFIGURATIONS_ETHTT_ADDRESS,
+	BBH_TX_5_CONFIGURATIONS_ETHTT_ADDRESS,
+	BBH_TX_6_CONFIGURATIONS_ETHTT_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONFIGURATIONS_ETHTT_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONFIGURATIONS_ETHTT_ARRAY);
+
+uint32_t BBH_TX_DEBUG_SRAMPD_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_SRAMPD_ADDRESS,
+	BBH_TX_1_DEBUG_SRAMPD_ADDRESS,
+	BBH_TX_2_DEBUG_SRAMPD_ADDRESS,
+	BBH_TX_3_DEBUG_SRAMPD_ADDRESS,
+	BBH_TX_4_DEBUG_SRAMPD_ADDRESS,
+	BBH_TX_5_DEBUG_SRAMPD_ADDRESS,
+	BBH_TX_6_DEBUG_SRAMPD_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_SRAMPD_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_SRAMPD_ARRAY);
+
+uint32_t BBH_TX_DEBUG_DDRPD_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_DDRPD_ADDRESS,
+	BBH_TX_1_DEBUG_DDRPD_ADDRESS,
+	BBH_TX_2_DEBUG_DDRPD_ADDRESS,
+	BBH_TX_3_DEBUG_DDRPD_ADDRESS,
+	BBH_TX_4_DEBUG_DDRPD_ADDRESS,
+	BBH_TX_5_DEBUG_DDRPD_ADDRESS,
+	BBH_TX_6_DEBUG_DDRPD_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_DDRPD_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_DDRPD_ARRAY);
+
+uint32_t BBH_TX_DEBUG_PDDROP_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_PDDROP_ADDRESS,
+	BBH_TX_1_DEBUG_PDDROP_ADDRESS,
+	BBH_TX_2_DEBUG_PDDROP_ADDRESS,
+	BBH_TX_3_DEBUG_PDDROP_ADDRESS,
+	BBH_TX_4_DEBUG_PDDROP_ADDRESS,
+	BBH_TX_5_DEBUG_PDDROP_ADDRESS,
+	BBH_TX_6_DEBUG_PDDROP_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_PDDROP_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_PDDROP_ARRAY);
+
+uint32_t BBH_TX_DEBUG_PDEQ0_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_PDEQ0_ADDRESS,
+	BBH_TX_1_DEBUG_PDEQ0_ADDRESS,
+	BBH_TX_2_DEBUG_PDEQ0_ADDRESS,
+	BBH_TX_3_DEBUG_PDEQ0_ADDRESS,
+	BBH_TX_4_DEBUG_PDEQ0_ADDRESS,
+	BBH_TX_5_DEBUG_PDEQ0_ADDRESS,
+	BBH_TX_6_DEBUG_PDEQ0_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_PDEQ0_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_PDEQ0_ARRAY);
+
+uint32_t BBH_TX_DEBUG_GETNEXTNULL_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_GETNEXTNULL_ADDRESS,
+	BBH_TX_1_DEBUG_GETNEXTNULL_ADDRESS,
+	BBH_TX_2_DEBUG_GETNEXTNULL_ADDRESS,
+	BBH_TX_3_DEBUG_GETNEXTNULL_ADDRESS,
+	BBH_TX_4_DEBUG_GETNEXTNULL_ADDRESS,
+	BBH_TX_5_DEBUG_GETNEXTNULL_ADDRESS,
+	BBH_TX_6_DEBUG_GETNEXTNULL_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_GETNEXTNULL_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_GETNEXTNULL_ARRAY);
+
+uint32_t BBH_TX_DEBUG_PDFULLLSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_PDFULLLSB_ADDRESS,
+	BBH_TX_1_DEBUG_PDFULLLSB_ADDRESS,
+	BBH_TX_2_DEBUG_PDFULLLSB_ADDRESS,
+	BBH_TX_3_DEBUG_PDFULLLSB_ADDRESS,
+	BBH_TX_4_DEBUG_PDFULLLSB_ADDRESS,
+	BBH_TX_5_DEBUG_PDFULLLSB_ADDRESS,
+	BBH_TX_6_DEBUG_PDFULLLSB_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_PDFULLLSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_PDFULLLSB_ARRAY);
+
+uint32_t BBH_TX_DEBUG_PDFULLMSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_PDFULLMSB_ADDRESS,
+	BBH_TX_1_DEBUG_PDFULLMSB_ADDRESS,
+	BBH_TX_2_DEBUG_PDFULLMSB_ADDRESS,
+	BBH_TX_3_DEBUG_PDFULLMSB_ADDRESS,
+	BBH_TX_4_DEBUG_PDFULLMSB_ADDRESS,
+	BBH_TX_5_DEBUG_PDFULLMSB_ADDRESS,
+	BBH_TX_6_DEBUG_PDFULLMSB_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_PDFULLMSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_PDFULLMSB_ARRAY);
+
+uint32_t BBH_TX_DEBUG_PDEMPTYLSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_1_DEBUG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_2_DEBUG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_3_DEBUG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_4_DEBUG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_5_DEBUG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_6_DEBUG_PDEMPTYLSB_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_PDEMPTYLSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_PDEMPTYLSB_ARRAY);
+
+uint32_t BBH_TX_DEBUG_PDEMPTYMSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_PDEMPTYMSB_ADDRESS,
+	BBH_TX_1_DEBUG_PDEMPTYMSB_ADDRESS,
+	BBH_TX_2_DEBUG_PDEMPTYMSB_ADDRESS,
+	BBH_TX_3_DEBUG_PDEMPTYMSB_ADDRESS,
+	BBH_TX_4_DEBUG_PDEMPTYMSB_ADDRESS,
+	BBH_TX_5_DEBUG_PDEMPTYMSB_ADDRESS,
+	BBH_TX_6_DEBUG_PDEMPTYMSB_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_PDEMPTYMSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_PDEMPTYMSB_ARRAY);
+
+uint32_t BBH_TX_DEBUG_PDVALID_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_PDVALID_ADDRESS,
+	BBH_TX_1_DEBUG_PDVALID_ADDRESS,
+	BBH_TX_2_DEBUG_PDVALID_ADDRESS,
+	BBH_TX_3_DEBUG_PDVALID_ADDRESS,
+	BBH_TX_4_DEBUG_PDVALID_ADDRESS,
+	BBH_TX_5_DEBUG_PDVALID_ADDRESS,
+	BBH_TX_6_DEBUG_PDVALID_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_PDVALID_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_PDVALID_ARRAY);
+
+uint32_t BBH_TX_DEBUG_BPMFIFO_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_BPMFIFO_ADDRESS,
+	BBH_TX_1_DEBUG_BPMFIFO_ADDRESS,
+	BBH_TX_2_DEBUG_BPMFIFO_ADDRESS,
+	BBH_TX_3_DEBUG_BPMFIFO_ADDRESS,
+	BBH_TX_4_DEBUG_BPMFIFO_ADDRESS,
+	BBH_TX_5_DEBUG_BPMFIFO_ADDRESS,
+	BBH_TX_6_DEBUG_BPMFIFO_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_BPMFIFO_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_BPMFIFO_ARRAY);
+
+uint32_t BBH_TX_DEBUG_SBPMFIFO_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_SBPMFIFO_ADDRESS,
+	BBH_TX_1_DEBUG_SBPMFIFO_ADDRESS,
+	BBH_TX_2_DEBUG_SBPMFIFO_ADDRESS,
+	BBH_TX_3_DEBUG_SBPMFIFO_ADDRESS,
+	BBH_TX_4_DEBUG_SBPMFIFO_ADDRESS,
+	BBH_TX_5_DEBUG_SBPMFIFO_ADDRESS,
+	BBH_TX_6_DEBUG_SBPMFIFO_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_SBPMFIFO_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_SBPMFIFO_ARRAY);
+
+uint32_t BBH_TX_DEBUG_FIRSTBNFIFO_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_FIRSTBNFIFO_ADDRESS,
+	BBH_TX_1_DEBUG_FIRSTBNFIFO_ADDRESS,
+	BBH_TX_2_DEBUG_FIRSTBNFIFO_ADDRESS,
+	BBH_TX_3_DEBUG_FIRSTBNFIFO_ADDRESS,
+	BBH_TX_4_DEBUG_FIRSTBNFIFO_ADDRESS,
+	BBH_TX_5_DEBUG_FIRSTBNFIFO_ADDRESS,
+	BBH_TX_6_DEBUG_FIRSTBNFIFO_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_FIRSTBNFIFO_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_FIRSTBNFIFO_ARRAY);
+
+uint32_t BBH_TX_DEBUG_GETNEXTFIFO_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_GETNEXTFIFO_ADDRESS,
+	BBH_TX_1_DEBUG_GETNEXTFIFO_ADDRESS,
+	BBH_TX_2_DEBUG_GETNEXTFIFO_ADDRESS,
+	BBH_TX_3_DEBUG_GETNEXTFIFO_ADDRESS,
+	BBH_TX_4_DEBUG_GETNEXTFIFO_ADDRESS,
+	BBH_TX_5_DEBUG_GETNEXTFIFO_ADDRESS,
+	BBH_TX_6_DEBUG_GETNEXTFIFO_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_GETNEXTFIFO_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_GETNEXTFIFO_ARRAY);
+
+uint32_t BBH_TX_DEBUG_DBGOUTREG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_DBGOUTREG_ADDRESS,
+	BBH_TX_1_DEBUG_DBGOUTREG_ADDRESS,
+	BBH_TX_2_DEBUG_DBGOUTREG_ADDRESS,
+	BBH_TX_3_DEBUG_DBGOUTREG_ADDRESS,
+	BBH_TX_4_DEBUG_DBGOUTREG_ADDRESS,
+	BBH_TX_5_DEBUG_DBGOUTREG_ADDRESS,
+	BBH_TX_6_DEBUG_DBGOUTREG_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_DBGOUTREG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_DBGOUTREG_ARRAY);
+
+uint32_t BBH_TX_DEBUG_EPNPDVALID_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_DEBUG_EPNPDVALID_ADDRESS,
+	BBH_TX_1_DEBUG_EPNPDVALID_ADDRESS,
+	BBH_TX_2_DEBUG_EPNPDVALID_ADDRESS,
+	BBH_TX_3_DEBUG_EPNPDVALID_ADDRESS,
+	BBH_TX_4_DEBUG_EPNPDVALID_ADDRESS,
+	BBH_TX_5_DEBUG_EPNPDVALID_ADDRESS,
+	BBH_TX_6_DEBUG_EPNPDVALID_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_DEBUG_EPNPDVALID_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_DEBUG_EPNPDVALID_ARRAY);
+
+uint32_t BBH_TX_PD_FIFO_PDFIFO_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_1_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_2_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_3_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_4_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_5_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_6_PD_FIFO_PDFIFO_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_PD_FIFO_PDFIFO_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_PD_FIFO_PDFIFO_ARRAY);
+
+uint32_t BBH_TX_CONTEXT_SEGCNTXT_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_CONTEXT_SEGCNTXT_ADDRESS,
+	BBH_TX_1_CONTEXT_SEGCNTXT_ADDRESS,
+	BBH_TX_2_CONTEXT_SEGCNTXT_ADDRESS,
+	BBH_TX_3_CONTEXT_SEGCNTXT_ADDRESS,
+	BBH_TX_4_CONTEXT_SEGCNTXT_ADDRESS,
+	BBH_TX_5_CONTEXT_SEGCNTXT_ADDRESS,
+	BBH_TX_6_CONTEXT_SEGCNTXT_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_CONTEXT_SEGCNTXT_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_CONTEXT_SEGCNTXT_ARRAY);
+
+uint32_t BBH_TX_EPON_PD_FIFO_PDFIFO_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_1_EPON_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_2_EPON_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_3_EPON_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_4_EPON_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_5_EPON_PD_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_6_EPON_PD_FIFO_PDFIFO_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_PD_FIFO_PDFIFO_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_PD_FIFO_PDFIFO_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_TASKLSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_TASKLSB_ADDRESS,
+	BBH_TX_1_EPON_CFG_TASKLSB_ADDRESS,
+	BBH_TX_2_EPON_CFG_TASKLSB_ADDRESS,
+	BBH_TX_3_EPON_CFG_TASKLSB_ADDRESS,
+	BBH_TX_4_EPON_CFG_TASKLSB_ADDRESS,
+	BBH_TX_5_EPON_CFG_TASKLSB_ADDRESS,
+	BBH_TX_6_EPON_CFG_TASKLSB_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_TASKLSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_TASKLSB_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_TASKMSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_TASKMSB_ADDRESS,
+	BBH_TX_1_EPON_CFG_TASKMSB_ADDRESS,
+	BBH_TX_2_EPON_CFG_TASKMSB_ADDRESS,
+	BBH_TX_3_EPON_CFG_TASKMSB_ADDRESS,
+	BBH_TX_4_EPON_CFG_TASKMSB_ADDRESS,
+	BBH_TX_5_EPON_CFG_TASKMSB_ADDRESS,
+	BBH_TX_6_EPON_CFG_TASKMSB_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_TASKMSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_TASKMSB_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_TASK8_39_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_TASK8_39_ADDRESS,
+	BBH_TX_1_EPON_CFG_TASK8_39_ADDRESS,
+	BBH_TX_2_EPON_CFG_TASK8_39_ADDRESS,
+	BBH_TX_3_EPON_CFG_TASK8_39_ADDRESS,
+	BBH_TX_4_EPON_CFG_TASK8_39_ADDRESS,
+	BBH_TX_5_EPON_CFG_TASK8_39_ADDRESS,
+	BBH_TX_6_EPON_CFG_TASK8_39_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_TASK8_39_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_TASK8_39_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PDSIZE0_3_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PDSIZE0_3_ADDRESS,
+	BBH_TX_1_EPON_CFG_PDSIZE0_3_ADDRESS,
+	BBH_TX_2_EPON_CFG_PDSIZE0_3_ADDRESS,
+	BBH_TX_3_EPON_CFG_PDSIZE0_3_ADDRESS,
+	BBH_TX_4_EPON_CFG_PDSIZE0_3_ADDRESS,
+	BBH_TX_5_EPON_CFG_PDSIZE0_3_ADDRESS,
+	BBH_TX_6_EPON_CFG_PDSIZE0_3_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PDSIZE0_3_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PDSIZE0_3_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PDSIZE4_7_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PDSIZE4_7_ADDRESS,
+	BBH_TX_1_EPON_CFG_PDSIZE4_7_ADDRESS,
+	BBH_TX_2_EPON_CFG_PDSIZE4_7_ADDRESS,
+	BBH_TX_3_EPON_CFG_PDSIZE4_7_ADDRESS,
+	BBH_TX_4_EPON_CFG_PDSIZE4_7_ADDRESS,
+	BBH_TX_5_EPON_CFG_PDSIZE4_7_ADDRESS,
+	BBH_TX_6_EPON_CFG_PDSIZE4_7_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PDSIZE4_7_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PDSIZE4_7_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PDSIZE8_31_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PDSIZE8_31_ADDRESS,
+	BBH_TX_1_EPON_CFG_PDSIZE8_31_ADDRESS,
+	BBH_TX_2_EPON_CFG_PDSIZE8_31_ADDRESS,
+	BBH_TX_3_EPON_CFG_PDSIZE8_31_ADDRESS,
+	BBH_TX_4_EPON_CFG_PDSIZE8_31_ADDRESS,
+	BBH_TX_5_EPON_CFG_PDSIZE8_31_ADDRESS,
+	BBH_TX_6_EPON_CFG_PDSIZE8_31_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PDSIZE8_31_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PDSIZE8_31_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PDBASE0_3_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PDBASE0_3_ADDRESS,
+	BBH_TX_1_EPON_CFG_PDBASE0_3_ADDRESS,
+	BBH_TX_2_EPON_CFG_PDBASE0_3_ADDRESS,
+	BBH_TX_3_EPON_CFG_PDBASE0_3_ADDRESS,
+	BBH_TX_4_EPON_CFG_PDBASE0_3_ADDRESS,
+	BBH_TX_5_EPON_CFG_PDBASE0_3_ADDRESS,
+	BBH_TX_6_EPON_CFG_PDBASE0_3_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PDBASE0_3_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PDBASE0_3_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PDBASE4_7_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PDBASE4_7_ADDRESS,
+	BBH_TX_1_EPON_CFG_PDBASE4_7_ADDRESS,
+	BBH_TX_2_EPON_CFG_PDBASE4_7_ADDRESS,
+	BBH_TX_3_EPON_CFG_PDBASE4_7_ADDRESS,
+	BBH_TX_4_EPON_CFG_PDBASE4_7_ADDRESS,
+	BBH_TX_5_EPON_CFG_PDBASE4_7_ADDRESS,
+	BBH_TX_6_EPON_CFG_PDBASE4_7_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PDBASE4_7_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PDBASE4_7_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PDBASE8_39_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PDBASE8_39_ADDRESS,
+	BBH_TX_1_EPON_CFG_PDBASE8_39_ADDRESS,
+	BBH_TX_2_EPON_CFG_PDBASE8_39_ADDRESS,
+	BBH_TX_3_EPON_CFG_PDBASE8_39_ADDRESS,
+	BBH_TX_4_EPON_CFG_PDBASE8_39_ADDRESS,
+	BBH_TX_5_EPON_CFG_PDBASE8_39_ADDRESS,
+	BBH_TX_6_EPON_CFG_PDBASE8_39_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PDBASE8_39_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PDBASE8_39_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PD_BYTE_TH_EN_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_1_EPON_CFG_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_2_EPON_CFG_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_3_EPON_CFG_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_4_EPON_CFG_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_5_EPON_CFG_PD_BYTE_TH_EN_ADDRESS,
+	BBH_TX_6_EPON_CFG_PD_BYTE_TH_EN_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PD_BYTE_TH_EN_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PD_BYTE_TH_EN_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PD_BYTE_TH_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PD_BYTE_TH_ADDRESS,
+	BBH_TX_1_EPON_CFG_PD_BYTE_TH_ADDRESS,
+	BBH_TX_2_EPON_CFG_PD_BYTE_TH_ADDRESS,
+	BBH_TX_3_EPON_CFG_PD_BYTE_TH_ADDRESS,
+	BBH_TX_4_EPON_CFG_PD_BYTE_TH_ADDRESS,
+	BBH_TX_5_EPON_CFG_PD_BYTE_TH_ADDRESS,
+	BBH_TX_6_EPON_CFG_PD_BYTE_TH_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PD_BYTE_TH_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PD_BYTE_TH_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_RUNNERCFG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_RUNNERCFG_ADDRESS,
+	BBH_TX_1_EPON_CFG_RUNNERCFG_ADDRESS,
+	BBH_TX_2_EPON_CFG_RUNNERCFG_ADDRESS,
+	BBH_TX_3_EPON_CFG_RUNNERCFG_ADDRESS,
+	BBH_TX_4_EPON_CFG_RUNNERCFG_ADDRESS,
+	BBH_TX_5_EPON_CFG_RUNNERCFG_ADDRESS,
+	BBH_TX_6_EPON_CFG_RUNNERCFG_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_RUNNERCFG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_RUNNERCFG_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_MDUMODE_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_MDUMODE_ADDRESS,
+	BBH_TX_1_EPON_CFG_MDUMODE_ADDRESS,
+	BBH_TX_2_EPON_CFG_MDUMODE_ADDRESS,
+	BBH_TX_3_EPON_CFG_MDUMODE_ADDRESS,
+	BBH_TX_4_EPON_CFG_MDUMODE_ADDRESS,
+	BBH_TX_5_EPON_CFG_MDUMODE_ADDRESS,
+	BBH_TX_6_EPON_CFG_MDUMODE_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_MDUMODE_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_MDUMODE_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_REQCFG_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_REQCFG_ADDRESS,
+	BBH_TX_1_EPON_CFG_REQCFG_ADDRESS,
+	BBH_TX_2_EPON_CFG_REQCFG_ADDRESS,
+	BBH_TX_3_EPON_CFG_REQCFG_ADDRESS,
+	BBH_TX_4_EPON_CFG_REQCFG_ADDRESS,
+	BBH_TX_5_EPON_CFG_REQCFG_ADDRESS,
+	BBH_TX_6_EPON_CFG_REQCFG_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_REQCFG_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_REQCFG_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PDWKUPH0_3_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PDWKUPH0_3_ADDRESS,
+	BBH_TX_1_EPON_CFG_PDWKUPH0_3_ADDRESS,
+	BBH_TX_2_EPON_CFG_PDWKUPH0_3_ADDRESS,
+	BBH_TX_3_EPON_CFG_PDWKUPH0_3_ADDRESS,
+	BBH_TX_4_EPON_CFG_PDWKUPH0_3_ADDRESS,
+	BBH_TX_5_EPON_CFG_PDWKUPH0_3_ADDRESS,
+	BBH_TX_6_EPON_CFG_PDWKUPH0_3_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PDWKUPH0_3_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PDWKUPH0_3_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PDWKUPH4_7_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PDWKUPH4_7_ADDRESS,
+	BBH_TX_1_EPON_CFG_PDWKUPH4_7_ADDRESS,
+	BBH_TX_2_EPON_CFG_PDWKUPH4_7_ADDRESS,
+	BBH_TX_3_EPON_CFG_PDWKUPH4_7_ADDRESS,
+	BBH_TX_4_EPON_CFG_PDWKUPH4_7_ADDRESS,
+	BBH_TX_5_EPON_CFG_PDWKUPH4_7_ADDRESS,
+	BBH_TX_6_EPON_CFG_PDWKUPH4_7_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PDWKUPH4_7_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PDWKUPH4_7_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PDWKUPH8_31_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PDWKUPH8_31_ADDRESS,
+	BBH_TX_1_EPON_CFG_PDWKUPH8_31_ADDRESS,
+	BBH_TX_2_EPON_CFG_PDWKUPH8_31_ADDRESS,
+	BBH_TX_3_EPON_CFG_PDWKUPH8_31_ADDRESS,
+	BBH_TX_4_EPON_CFG_PDWKUPH8_31_ADDRESS,
+	BBH_TX_5_EPON_CFG_PDWKUPH8_31_ADDRESS,
+	BBH_TX_6_EPON_CFG_PDWKUPH8_31_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PDWKUPH8_31_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PDWKUPH8_31_ARRAY);
+
+uint32_t BBH_TX_EPON_CFG_PDEMPTY_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_CFG_PDEMPTY_ADDRESS,
+	BBH_TX_1_EPON_CFG_PDEMPTY_ADDRESS,
+	BBH_TX_2_EPON_CFG_PDEMPTY_ADDRESS,
+	BBH_TX_3_EPON_CFG_PDEMPTY_ADDRESS,
+	BBH_TX_4_EPON_CFG_PDEMPTY_ADDRESS,
+	BBH_TX_5_EPON_CFG_PDEMPTY_ADDRESS,
+	BBH_TX_6_EPON_CFG_PDEMPTY_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_CFG_PDEMPTY_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_CFG_PDEMPTY_ARRAY);
+
+uint32_t BBH_TX_EPON_DBG_DDRPD_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_DBG_DDRPD_ADDRESS,
+	BBH_TX_1_EPON_DBG_DDRPD_ADDRESS,
+	BBH_TX_2_EPON_DBG_DDRPD_ADDRESS,
+	BBH_TX_3_EPON_DBG_DDRPD_ADDRESS,
+	BBH_TX_4_EPON_DBG_DDRPD_ADDRESS,
+	BBH_TX_5_EPON_DBG_DDRPD_ADDRESS,
+	BBH_TX_6_EPON_DBG_DDRPD_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_DBG_DDRPD_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_DBG_DDRPD_ARRAY);
+
+uint32_t BBH_TX_EPON_DBG_PDDROP_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_DBG_PDDROP_ADDRESS,
+	BBH_TX_1_EPON_DBG_PDDROP_ADDRESS,
+	BBH_TX_2_EPON_DBG_PDDROP_ADDRESS,
+	BBH_TX_3_EPON_DBG_PDDROP_ADDRESS,
+	BBH_TX_4_EPON_DBG_PDDROP_ADDRESS,
+	BBH_TX_5_EPON_DBG_PDDROP_ADDRESS,
+	BBH_TX_6_EPON_DBG_PDDROP_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_DBG_PDDROP_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_DBG_PDDROP_ARRAY);
+
+uint32_t BBH_TX_EPON_DBG_PDEQ0_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_DBG_PDEQ0_ADDRESS,
+	BBH_TX_1_EPON_DBG_PDEQ0_ADDRESS,
+	BBH_TX_2_EPON_DBG_PDEQ0_ADDRESS,
+	BBH_TX_3_EPON_DBG_PDEQ0_ADDRESS,
+	BBH_TX_4_EPON_DBG_PDEQ0_ADDRESS,
+	BBH_TX_5_EPON_DBG_PDEQ0_ADDRESS,
+	BBH_TX_6_EPON_DBG_PDEQ0_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_DBG_PDEQ0_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_DBG_PDEQ0_ARRAY);
+
+uint32_t BBH_TX_EPON_DBG_PDFULLLSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_DBG_PDFULLLSB_ADDRESS,
+	BBH_TX_1_EPON_DBG_PDFULLLSB_ADDRESS,
+	BBH_TX_2_EPON_DBG_PDFULLLSB_ADDRESS,
+	BBH_TX_3_EPON_DBG_PDFULLLSB_ADDRESS,
+	BBH_TX_4_EPON_DBG_PDFULLLSB_ADDRESS,
+	BBH_TX_5_EPON_DBG_PDFULLLSB_ADDRESS,
+	BBH_TX_6_EPON_DBG_PDFULLLSB_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_DBG_PDFULLLSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_DBG_PDFULLLSB_ARRAY);
+
+uint32_t BBH_TX_EPON_DBG_PDEMPTYLSB_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_DBG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_1_EPON_DBG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_2_EPON_DBG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_3_EPON_DBG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_4_EPON_DBG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_5_EPON_DBG_PDEMPTYLSB_ADDRESS,
+	BBH_TX_6_EPON_DBG_PDEMPTYLSB_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_DBG_PDEMPTYLSB_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_DBG_PDEMPTYLSB_ARRAY);
+
+uint32_t BBH_TX_EPON_DBG_PDVALID_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_DBG_PDVALID_ADDRESS,
+	BBH_TX_1_EPON_DBG_PDVALID_ADDRESS,
+	BBH_TX_2_EPON_DBG_PDVALID_ADDRESS,
+	BBH_TX_3_EPON_DBG_PDVALID_ADDRESS,
+	BBH_TX_4_EPON_DBG_PDVALID_ADDRESS,
+	BBH_TX_5_EPON_DBG_PDVALID_ADDRESS,
+	BBH_TX_6_EPON_DBG_PDVALID_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_DBG_PDVALID_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_DBG_PDVALID_ARRAY);
+
+uint32_t BBH_TX_EPON_DBG_LENERR_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_DBG_LENERR_ADDRESS,
+	BBH_TX_1_EPON_DBG_LENERR_ADDRESS,
+	BBH_TX_2_EPON_DBG_LENERR_ADDRESS,
+	BBH_TX_3_EPON_DBG_LENERR_ADDRESS,
+	BBH_TX_4_EPON_DBG_LENERR_ADDRESS,
+	BBH_TX_5_EPON_DBG_LENERR_ADDRESS,
+	BBH_TX_6_EPON_DBG_LENERR_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_DBG_LENERR_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_DBG_LENERR_ARRAY);
+
+uint32_t BBH_TX_EPON_DBG_FLUSHPKTS_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_DBG_FLUSHPKTS_ADDRESS,
+	BBH_TX_1_EPON_DBG_FLUSHPKTS_ADDRESS,
+	BBH_TX_2_EPON_DBG_FLUSHPKTS_ADDRESS,
+	BBH_TX_3_EPON_DBG_FLUSHPKTS_ADDRESS,
+	BBH_TX_4_EPON_DBG_FLUSHPKTS_ADDRESS,
+	BBH_TX_5_EPON_DBG_FLUSHPKTS_ADDRESS,
+	BBH_TX_6_EPON_DBG_FLUSHPKTS_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_DBG_FLUSHPKTS_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_DBG_FLUSHPKTS_ARRAY);
+
+uint32_t BBH_TX_EPON_DBG_REQFIFOADD_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_DBG_REQFIFOADD_ADDRESS,
+	BBH_TX_1_EPON_DBG_REQFIFOADD_ADDRESS,
+	BBH_TX_2_EPON_DBG_REQFIFOADD_ADDRESS,
+	BBH_TX_3_EPON_DBG_REQFIFOADD_ADDRESS,
+	BBH_TX_4_EPON_DBG_REQFIFOADD_ADDRESS,
+	BBH_TX_5_EPON_DBG_REQFIFOADD_ADDRESS,
+	BBH_TX_6_EPON_DBG_REQFIFOADD_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_DBG_REQFIFOADD_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_DBG_REQFIFOADD_ARRAY);
+
+uint32_t BBH_TX_EPON_DBG_REQFIFODATA_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_DBG_REQFIFODATA_ADDRESS,
+	BBH_TX_1_EPON_DBG_REQFIFODATA_ADDRESS,
+	BBH_TX_2_EPON_DBG_REQFIFODATA_ADDRESS,
+	BBH_TX_3_EPON_DBG_REQFIFODATA_ADDRESS,
+	BBH_TX_4_EPON_DBG_REQFIFODATA_ADDRESS,
+	BBH_TX_5_EPON_DBG_REQFIFODATA_ADDRESS,
+	BBH_TX_6_EPON_DBG_REQFIFODATA_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_DBG_REQFIFODATA_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_DBG_REQFIFODATA_ARRAY);
+
+uint32_t BBH_TX_EPON_STS_FIFO_PDFIFO_ARRAY [ NUM_OF_BBH_BLOCKS ] =
+{
+	BBH_TX_0_EPON_STS_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_1_EPON_STS_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_2_EPON_STS_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_3_EPON_STS_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_4_EPON_STS_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_5_EPON_STS_FIFO_PDFIFO_ADDRESS,
+	BBH_TX_6_EPON_STS_FIFO_PDFIFO_ADDRESS,
+#ifdef __OREN__
+	BBH_TX_7_EPON_STS_FIFO_PDFIFO_ADDRESS,
+#endif
+} ;
+
+EXPORT_SYMBOL(BBH_TX_EPON_STS_FIFO_PDFIFO_ARRAY);
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_bpm.h b/arch/arm/mach-bcmbca/rdp/rdp_bpm.h
new file mode 100755
index 0000000000..f395c17215
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_bpm.h
@@ -0,0 +1,3328 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/             
+
+#ifndef __BPM_H_INCLUDED
+#define __BPM_H_INCLUDED
+
+/*  File automatically generated by Reggae at 15/08/2013  10:54:33   */
+
+#include "access_macros.h"
+#include "packing.h"
+#include "rdp_map.h"
+
+/*****************************************************************************************/
+/* BPM module is resposible for DDR buffers pool managment. Total there are 15K buffers  */
+/* (BNs). BPM module has an interface with Broad Bus handlers of Ethernet MACs (0-4), GP */
+/* ON, Runner A, Runner B, MIPS-C and MIPS-D.                                            */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Blocks offsets                                                                        */
+/*****************************************************************************************/
+/*****************************************************************************************/
+/* Functions offsets and addresses                                                       */
+/*****************************************************************************************/
+#define BPM_MODULE_REGS_OFFSET 	( 0x00000000 )
+#define BPM_MODULE_REGS_ADDRESS	( BPM_MODULE_OFFSET + BPM_MODULE_REGS_OFFSET )
+
+/*   'd' is module index   */
+/*   'i' is block index    */
+/*   'j' is function index */
+/*   'e' is function entry */
+/*   'k' is register index */
+
+/*****************************************************************************************/
+/* Request_pointer                                                                       */
+/* CPU request a free pointer from BPM by WRITE tp ptr_req (data pattern is not importan */
+/* t)  BPM in its turn will de assert bit req indicating that a valid pointer is ready f */
+/* or cpu usage  (see ptr bits description). This register returns to default values by  */
+/* soft reset.                                                                           */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_REQ_PTR_RDY_NOT_READY_VALUE                                          ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_RDY_NOT_READY_VALUE_RESET_VALUE                              ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_RDY_READY_VALUE                                              ( 0x1 )
+#define BPM_MODULE_REGS_REQ_PTR_BSY_NOT_BUSY_VALUE                                           ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_BSY_NOT_BUSY_VALUE_RESET_VALUE                               ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_BSY_BUSY_VALUE                                               ( 0x1 )
+#define BPM_MODULE_REGS_REQ_PTR_RSV_RSV_VALUE                                                ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_RSV_RSV_VALUE_RESET_VALUE                                    ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_SP_ADDR_SOURCE_ADRESS_OF_PORT_FOR_BN_ALLOC_VALUE             ( 0x6 )
+#define BPM_MODULE_REGS_REQ_PTR_SP_ADDR_SOURCE_ADRESS_OF_PORT_FOR_BN_ALLOC_VALUE_RESET_VALUE ( 0x6 )
+#define BPM_MODULE_REGS_REQ_PTR_NACK_STATUS_CPU_IN_ACK_STATE_VALUE                           ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_NACK_STATUS_CPU_IN_ACK_STATE_VALUE_RESET_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_NACK_STATUS_CPU_IN_NACK_STATE_VALUE                          ( 0x1 )
+#define BPM_MODULE_REGS_REQ_PTR_BN_RSV_VALUE                                                 ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_BN_RSV_VALUE_RESET_VALUE                                     ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_BN_VALID_NOT_VALID_VALUE                                     ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_BN_VALID_NOT_VALID_VALUE_RESET_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_REQ_PTR_BN_VALID_VALID_VALUE                                         ( 0x1 )
+
+
+#define BPM_MODULE_REGS_REQ_PTR_OFFSET ( 0x00000000 )
+
+#define BPM_MODULE_REGS_REQ_PTR_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_REQ_PTR_OFFSET )
+#define BPM_MODULE_REGS_REQ_PTR_READ( r ) 	READ_32( ( BPM_MODULE_REGS_REQ_PTR_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_REQ_PTR_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_REQ_PTR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Ready_bit_for_Alloc_request */
+	uint32_t rdy        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Busy_bit_for_Alloc_request */
+	uint32_t bsy        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv        	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* nack_status */
+	uint32_t nack_status	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* source_port_address */
+	uint32_t sp_addr    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bufer_number */
+	uint32_t bn         	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bufer_number_valid */
+	uint32_t bn_valid   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_REQ_PTR ;
+#else
+typedef struct
+	/* bufer_number_valid */
+{	uint32_t bn_valid   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	/* bufer_number_valid */
+
+	uint32_t bn         	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	/* bufer_number */
+
+	uint32_t sp_addr    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	/* source_port_address */
+
+	uint32_t nack_status	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	/* nack_status */
+
+	uint32_t rsv        	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	/* rsv */
+
+	uint32_t bsy        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	/* Busy_bit_for_Alloc_request */
+
+	uint32_t rdy        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	/* Ready_bit_for_Alloc_request */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_REQ_PTR ;
+#endif
+
+/*****************************************************************************************/
+/* Free_pointer                                                                          */
+/* Free buffer pointer from cpu to bpm. When cpu requests bmp to release an occupied poi */
+/* nter, it WRITes ro free_ptrt reg. Once the buffer is free, bpm will de assert the REA */
+/* DY bi and de-assert BUSY bit, indicating completion of the free process.   This regis */
+/* ter returns to default values by soft reset.                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_FREE_PTR_RDY_VALUE_ON_POWER_OR_REQUEST__IN_PROGRESS_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_RDY_VALUE_ON_POWER_OR_REQUEST__IN_PROGRESS_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_RDY_REQUEST_NOT_IN_PROGRESS_VALUE                            ( 0x1 )
+#define BPM_MODULE_REGS_FREE_PTR_BSY_REQUEST_NOT__IN_PROGRESS_VALUE                           ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_BSY_REQUEST_NOT__IN_PROGRESS_VALUE_RESET_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_BSY_REQUEST__IN_PROGRESS_VALUE                               ( 0x1 )
+#define BPM_MODULE_REGS_FREE_PTR_RSV2_RESERVED_VALUE                                          ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_RSV2_RESERVED_VALUE_RESET_VALUE                              ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_OWN_SA_RESERVED_VALUE                                        ( 0x6 )
+#define BPM_MODULE_REGS_FREE_PTR_OWN_SA_RESERVED_VALUE_RESET_VALUE                            ( 0x6 )
+#define BPM_MODULE_REGS_FREE_PTR_RSV1_RESERVED_VALUE                                          ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_RSV1_RESERVED_VALUE_RESET_VALUE                              ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_BN_POINTER_ADDRESS_VALUE                                     ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_BN_POINTER_ADDRESS_VALUE_RESET_VALUE                         ( 0x0 )
+
+
+#define BPM_MODULE_REGS_FREE_PTR_OFFSET ( 0x00000004 )
+
+#define BPM_MODULE_REGS_FREE_PTR_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_FREE_PTR_OFFSET )
+#define BPM_MODULE_REGS_FREE_PTR_READ( r ) 	READ_32( ( BPM_MODULE_REGS_FREE_PTR_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_FREE_PTR_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_FREE_PTR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* ready */
+	uint32_t rdy   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t bsy   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2  	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Owner_Source_Address_of_BN */
+	uint32_t own_sa	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Bufer_Number */
+	uint32_t bn    	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_FREE_PTR ;
+#else
+typedef struct
+{	uint32_t bn    	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Bufer_Number */
+	uint32_t rsv1  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t own_sa	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Owner_Source_Address_of_BN */
+	uint32_t rsv2  	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t bsy   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t rdy   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ready */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_FREE_PTR ;
+#endif
+
+/*****************************************************************************************/
+/* Multi_Cast_Counter_set_for_pointer                                                    */
+/* MCNT request pointer from cpu to bpm. When cpu requests bmp to set MCNT an occupied p */
+/* ointer, it will set bit req. Once the MCNT of  buffer is set, bpm will de assert the  */
+/* bit request, indicating completion of the MCNT setting  process.   This register retu */
+/* rns to default values by soft reset.                                                  */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_MCNT_PTR_RDY_REQUEST_IN_PROGRESS_OR_POWER_RESET_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_RDY_REQUEST_IN_PROGRESS_OR_POWER_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_RDY_REQUEST_IS_NOT_IN_PROGRESS_VALUE                     ( 0x1 )
+#define BPM_MODULE_REGS_MCNT_PTR_BSY_REQUEST_IS_NOT_PROGRESS_VALUE                        ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_BSY_REQUEST_IS_NOT_PROGRESS_VALUE_RESET_VALUE            ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_BSY_REQUEST_IN_PROGRESS_VALUE                            ( 0x1 )
+#define BPM_MODULE_REGS_MCNT_PTR_RSV2_RSV_VALUE                                           ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_RSV2_RSV_VALUE_RESET_VALUE                               ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_MCNT_RSV_VALUE                                           ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_MCNT_RSV_VALUE_RESET_VALUE                               ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_RSV1_RSV_VALUE                                           ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_RSV1_RSV_VALUE_RESET_VALUE                               ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_BN_RDY_DEFUALT_VALUE_VALUE                               ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_BN_RDY_DEFUALT_VALUE_VALUE_RESET_VALUE                   ( 0x0 )
+
+
+#define BPM_MODULE_REGS_MCNT_PTR_OFFSET ( 0x00000008 )
+
+#define BPM_MODULE_REGS_MCNT_PTR_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_MCNT_PTR_OFFSET )
+#define BPM_MODULE_REGS_MCNT_PTR_READ( r ) 	READ_32( ( BPM_MODULE_REGS_MCNT_PTR_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_MCNT_PTR_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_MCNT_PTR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* ready */
+	uint32_t rdy 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t bsy 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MCNT */
+	uint32_t mcnt	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Bufer_Number */
+	uint32_t bn  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_MCNT_PTR ;
+#else
+typedef struct
+{	uint32_t bn  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Bufer_Number */
+	uint32_t rsv1	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t mcnt	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MCNT */
+	uint32_t rsv2	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t bsy 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t rdy 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ready */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_MCNT_PTR ;
+#endif
+
+/*****************************************************************************************/
+/* Init_of_BPM_Core_RAMs                                                                 */
+/* Init RAMs request. When cpu requests bmp to init RAMSr, it will WRITE to ram_init reg */
+/* ister (pattern is not important). Once the RAMs are initilizied, bpm will de assert t */
+/* he busy bit (BSY) and will assrt ready bit (RDY), indicating completion of the init R */
+/* AM  process.   This register returns to default values by TM  reset.                  */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_RAM_INIT_RDY_NON_BUSY_VALUE              ( 0x0 )
+#define BPM_MODULE_REGS_RAM_INIT_RDY_NON_BUSY_VALUE_RESET_VALUE  ( 0x0 )
+#define BPM_MODULE_REGS_RAM_INIT_RDY_BUSY_VALUE                  ( 0x1 )
+#define BPM_MODULE_REGS_RAM_INIT_BSY_NOT_READY_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_RAM_INIT_BSY_NOT_READY_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_RAM_INIT_BSY_READY_VALUE                 ( 0x1 )
+#define BPM_MODULE_REGS_RAM_INIT_RSV_RSV_VALUE                   ( 0x0 )
+#define BPM_MODULE_REGS_RAM_INIT_RSV_RSV_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define BPM_MODULE_REGS_RAM_INIT_OFFSET ( 0x0000000C )
+
+#define BPM_MODULE_REGS_RAM_INIT_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_RAM_INIT_OFFSET )
+#define BPM_MODULE_REGS_RAM_INIT_READ( r ) 	READ_32( ( BPM_MODULE_REGS_RAM_INIT_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_RAM_INIT_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_RAM_INIT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* ready */
+	uint32_t rdy	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t bsy	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_RAM_INIT ;
+#else
+typedef struct
+{	uint32_t rsv	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t bsy	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t rdy	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ready */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_RAM_INIT ;
+#endif
+
+/*****************************************************************************************/
+/* free_pointer_interrupt                                                                */
+/* Free pointer interrupt indication and pointer number will hold untill read clear by S */
+/* W.  This happen if there is a pointer that is already in bpm hand but some user want  */
+/* to free it again                                                                      */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_FREE_PTR_INT_RSV_DEFUALT_VALUE_VALUE                 ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_INT_RSV_DEFUALT_VALUE_VALUE_RESET_VALUE     ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_INT_INTSP_SOURCE_PORT_IRQ_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_INT_INTSP_SOURCE_PORT_IRQ_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_INT_PTRNUM_DEFUALT_VALUE_VALUE              ( 0x0 )
+#define BPM_MODULE_REGS_FREE_PTR_INT_PTRNUM_DEFUALT_VALUE_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define BPM_MODULE_REGS_FREE_PTR_INT_OFFSET ( 0x00000010 )
+
+#define BPM_MODULE_REGS_FREE_PTR_INT_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_FREE_PTR_INT_OFFSET )
+#define BPM_MODULE_REGS_FREE_PTR_INT_READ( r ) 	READ_32( ( BPM_MODULE_REGS_FREE_PTR_INT_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_FREE_PTR_INT_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_FREE_PTR_INT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t rsv   	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Source_Port_IRQ */
+	uint32_t intsp 	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pointer_number */
+	uint32_t ptrnum	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_FREE_PTR_INT ;
+#else
+typedef struct
+{	uint32_t ptrnum	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pointer_number */
+	uint32_t intsp 	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Source_Port_IRQ */
+	uint32_t rsv   	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_FREE_PTR_INT ;
+#endif
+
+/*****************************************************************************************/
+/* Read_ram_address                                                                      */
+/* If CPU wants to read data from one of RAMs, it has to indicate in the register the RA */
+/* M number out of 6 RAMs and the address. Issue a req and when data is ready the bit wi */
+/* ll go down.    Address field in the selected RAM. Each RAM includes 80 rows. In order */
+/*  to re-create BN from the RAM data there is an convention procedure: (1) 5-lowest bit */
+/* s in BN says where BN is located in row (2) 7-middle bits says location of row in RAM */
+/* , in order to convert middle field of BN from 7-bit row location, please refer to Lil */
+/* ac issue 916 in Bugzilla. (3) 3-highest bits say which memory is used for BN storage  */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_READ_RAM_ADDR_REQ_DEFUALT_VALUE_VALUE                 ( 0x0 )
+#define BPM_MODULE_REGS_READ_RAM_ADDR_REQ_DEFUALT_VALUE_VALUE_RESET_VALUE     ( 0x0 )
+#define BPM_MODULE_REGS_READ_RAM_ADDR_RSV_RSV_VALUE                           ( 0x0 )
+#define BPM_MODULE_REGS_READ_RAM_ADDR_RSV_RSV_VALUE_RESET_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_READ_RAM_ADDR_SELRAM_DEFUALT_VALUE_VALUE              ( 0x0 )
+#define BPM_MODULE_REGS_READ_RAM_ADDR_SELRAM_DEFUALT_VALUE_VALUE_RESET_VALUE  ( 0x0 )
+#define BPM_MODULE_REGS_READ_RAM_ADDR_RAMADDR_DEFUALT_VALUE_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_READ_RAM_ADDR_RAMADDR_DEFUALT_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_READ_RAM_ADDR_OFFSET ( 0x00000014 )
+
+#define BPM_MODULE_REGS_READ_RAM_ADDR_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_READ_RAM_ADDR_OFFSET )
+#define BPM_MODULE_REGS_READ_RAM_ADDR_READ( r ) 	READ_32( ( BPM_MODULE_REGS_READ_RAM_ADDR_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_READ_RAM_ADDR_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_READ_RAM_ADDR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* req_read */
+	uint32_t req    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv    	: 21 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* select_1_ram_out_of_6 */
+	uint32_t selram 	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ram_addr */
+	uint32_t ramaddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_READ_RAM_ADDR ;
+#else
+typedef struct
+{	uint32_t ramaddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ram_addr */
+	uint32_t selram 	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* select_1_ram_out_of_6 */
+	uint32_t rsv    	: 21 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t req    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* req_read */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_READ_RAM_ADDR ;
+#endif
+
+/*****************************************************************************************/
+/* MCNT_pointer_interrupt                                                                */
+/* MCNT pointer interrupt indication and pointer number will hold untill read clear by s */
+/* w.  This happen if there is a pointer that is already in bpm hand but some user want  */
+/* to free it again                                                                      */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_MCNT_PTR_INT_RSV_DEFUALT_VALUE_VALUE                 ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_INT_RSV_DEFUALT_VALUE_VALUE_RESET_VALUE     ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_INT_INTSP_IRQ_SOURCE_PORT_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_INT_INTSP_IRQ_SOURCE_PORT_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_INT_PTRNUM_DEFUALT_VALUE_VALUE              ( 0x0 )
+#define BPM_MODULE_REGS_MCNT_PTR_INT_PTRNUM_DEFUALT_VALUE_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define BPM_MODULE_REGS_MCNT_PTR_INT_OFFSET ( 0x00000018 )
+
+#define BPM_MODULE_REGS_MCNT_PTR_INT_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_MCNT_PTR_INT_OFFSET )
+#define BPM_MODULE_REGS_MCNT_PTR_INT_READ( r ) 	READ_32( ( BPM_MODULE_REGS_MCNT_PTR_INT_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_MCNT_PTR_INT_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_MCNT_PTR_INT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IRQ_Source_Port */
+	uint32_t intsp 	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pointer_number */
+	uint32_t ptrnum	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_MCNT_PTR_INT ;
+#else
+typedef struct
+{	uint32_t ptrnum	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pointer_number */
+	uint32_t intsp 	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IRQ_Source_Port */
+	uint32_t rsv   	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_MCNT_PTR_INT ;
+#endif
+
+/*****************************************************************************************/
+/* read_ram_data0                                                                        */
+/* Read RAM data after a read ram bits 31-0 req                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_READ_RAM_DATA0_DATA_DEFUALT_VALUE_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_READ_RAM_DATA0_DATA_DEFUALT_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_READ_RAM_DATA0_OFFSET ( 0x0000001C )
+
+#define BPM_MODULE_REGS_READ_RAM_DATA0_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_READ_RAM_DATA0_OFFSET )
+#define BPM_MODULE_REGS_READ_RAM_DATA0_READ( r ) 	READ_32( ( BPM_MODULE_REGS_READ_RAM_DATA0_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_READ_RAM_DATA0_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_READ_RAM_DATA0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* data */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_READ_RAM_DATA0 ;
+#else
+typedef struct
+{	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_READ_RAM_DATA0 ;
+#endif
+
+/*****************************************************************************************/
+/* read_ram_data1                                                                        */
+/* Read RAM data after a read ram bits 63-32 req                                         */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_READ_RAM_DATA1_DATA_DEFUALT_VALUE_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_READ_RAM_DATA1_DATA_DEFUALT_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_READ_RAM_DATA1_OFFSET ( 0x00000020 )
+
+#define BPM_MODULE_REGS_READ_RAM_DATA1_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_READ_RAM_DATA1_OFFSET )
+#define BPM_MODULE_REGS_READ_RAM_DATA1_READ( r ) 	READ_32( ( BPM_MODULE_REGS_READ_RAM_DATA1_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_READ_RAM_DATA1_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_READ_RAM_DATA1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* data */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_READ_RAM_DATA1 ;
+#else
+typedef struct
+{	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_READ_RAM_DATA1 ;
+#endif
+
+/*****************************************************************************************/
+/* read_ram_data2                                                                        */
+/* Read RAM data after a read ram bits 96-64 req                                         */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_READ_RAM_DATA2_DATA_DEFUALT_VALUE_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_READ_RAM_DATA2_DATA_DEFUALT_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_READ_RAM_DATA2_OFFSET ( 0x00000024 )
+
+#define BPM_MODULE_REGS_READ_RAM_DATA2_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_READ_RAM_DATA2_OFFSET )
+#define BPM_MODULE_REGS_READ_RAM_DATA2_READ( r ) 	READ_32( ( BPM_MODULE_REGS_READ_RAM_DATA2_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_READ_RAM_DATA2_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_READ_RAM_DATA2_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* data */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_READ_RAM_DATA2 ;
+#else
+typedef struct
+{	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_READ_RAM_DATA2 ;
+#endif
+
+/*****************************************************************************************/
+/* Source_Port_enable                                                                    */
+/* Source Ports Enable                                                                   */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_SP_EN_RSV_RSV_VALUE                                 ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_RSV_RSV_VALUE_RESET_VALUE                     ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC4_EN_EMAC4_SP_DISABLE_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC4_EN_EMAC4_SP_DISABLE_VALUE_RESET_VALUE   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC4_EN_EMAC4_SP_ENABLE_VALUE                ( 0x1 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC3_EN_EMAC3_SP_DISABLE_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC3_EN_EMAC3_SP_DISABLE_VALUE_RESET_VALUE   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC3_EN_EMAC3_SP_ENABLE_VALUE                ( 0x1 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC2_EN_EMAC2_SP_DISABLE_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC2_EN_EMAC2_SP_DISABLE_VALUE_RESET_VALUE   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC2_EN_EMAC2_SP_ENABLE_VALUE                ( 0x1 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC1_EN_EMAC1_SP_DISABLE_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC1_EN_EMAC1_SP_DISABLE_VALUE_RESET_VALUE   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC1_EN_EMAC1_SP_ENABLE_VALUE                ( 0x1 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC0_EN_EMAC0_SP_DISABLE_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC0_EN_EMAC0_SP_DISABLE_VALUE_RESET_VALUE   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_EMAC0_EN_EMAC0_SP_ENABLE_VALUE                ( 0x1 )
+#define BPM_MODULE_REGS_BPM_SP_EN_GPON_EN_GPON_SP_DISABLE_VALUE                 ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_GPON_EN_GPON_SP_DISABLE_VALUE_RESET_VALUE     ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_GPON_EN_GPON_SP_ENABLE_VALUE                  ( 0x1 )
+#define BPM_MODULE_REGS_BPM_SP_EN_RNRB_EN_RUNNER_B_SP_DISABLE_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_RNRB_EN_RUNNER_B_SP_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_RNRB_EN_RUNNER_B_SP_ENABLE_VALUE              ( 0x1 )
+#define BPM_MODULE_REGS_BPM_SP_EN_RNRA_EN_RUNNER_A_DISABLE_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_RNRA_EN_RUNNER_A_DISABLE_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SP_EN_RNRA_EN_RUNNER_A__ENABLE_VALUE                ( 0x1 )
+
+
+#define BPM_MODULE_REGS_BPM_SP_EN_OFFSET ( 0x00000028 )
+
+#define BPM_MODULE_REGS_BPM_SP_EN_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_SP_EN_OFFSET )
+#define BPM_MODULE_REGS_BPM_SP_EN_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_SP_EN_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_SP_EN_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_SP_EN_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv     	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC4_SP_EN */
+	uint32_t emac4_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC3_SP_EN */
+	uint32_t emac3_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC2_SP_EN */
+	uint32_t emac2_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC1_SP_EN */
+	uint32_t emac1_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC0_SP_EN */
+	uint32_t emac0_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_SP_EN */
+	uint32_t gpon_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_B_SP_EN */
+	uint32_t rnrb_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_A_SP_EN */
+	uint32_t rnra_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_SP_EN ;
+#else
+typedef struct
+{	uint32_t rnra_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_A_SP_EN */
+	uint32_t rnrb_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_B_SP_EN */
+	uint32_t gpon_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_SP_EN */
+	uint32_t emac0_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC0_SP_EN */
+	uint32_t emac1_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC1_SP_EN */
+	uint32_t emac2_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC2_SP_EN */
+	uint32_t emac3_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC3_SP_EN */
+	uint32_t emac4_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC4_SP_EN */
+	uint32_t rsv     	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_SP_EN ;
+#endif
+
+/*****************************************************************************************/
+/* Global_Threshold                                                                      */
+/* Global Threshold for Allocated Buffers. There are 6 options: 1K, 2K,3k …6K buffers.   */
+/* BPM will issue BN in the accepted range upon to Global threshold setup.  Ths register */
+/*  also holds global hysteresis value for ACK/NACK transition setting                   */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_GL_TRSH_RSV2_RSV_VALUE                               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_RSV2_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAH_GL_BAH_VALUE                          ( 0x400 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAH_GL_BAH_VALUE_RESET_VALUE              ( 0x400 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_RSV_RSV_VALUE                                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_RSV_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_2P5K_VALUE           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_5K_VALUE             ( 0x1 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_5K_VALUE_RESET_VALUE ( 0x1 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_7P5K_VALUE           ( 0x2 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_10K_VALUE            ( 0x3 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_12P5K_VALUE          ( 0x4 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_15K_VALUE            ( 0x5 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_17p5K_VALUE          ( 0x6 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_20K_VALUE            ( 0x7 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_22p5K_VALUE          ( 0x8 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_25K_VALUE            ( 0x9 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_27p5K_VALUE          ( 0xA )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_GLOBAL_THRESHOLD_30K_VALUE            ( 0xB )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_RSV1_VALUE                            ( 0x6 )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_GL_BAT_RSV_VALUE                             ( 0x7 )
+
+
+#define BPM_MODULE_REGS_BPM_GL_TRSH_OFFSET ( 0x0000002C )
+
+#define BPM_MODULE_REGS_BPM_GL_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_GL_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_GL_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_GL_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_GL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GL_BAH */
+	uint32_t gl_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv   	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GL_BAT */
+	uint32_t gl_bat	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_GL_TRSH ;
+#else
+typedef struct
+{	uint32_t gl_bat	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GL_BAT */
+	uint32_t rsv   	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t gl_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GL_BAH */
+	uint32_t rsv2  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_GL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG0_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG0  Ths register also holds UG0 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_RSV2_RSV_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_UG0_BAH_BAH_VALUE             ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_UG0_BAH_BAH_VALUE_RESET_VALUE ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_RSV_RSV1_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_RSV_RSV1_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_UG0_BAT_BAT_VALUE             ( 0x1400 )
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_UG0_BAT_BAT_VALUE_RESET_VALUE ( 0x1400 )
+
+
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_OFFSET ( 0x00000030 )
+
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG0_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG0_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG0_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG0_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG0_TRSH ;
+#else
+typedef struct
+{	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG0_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG1_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG1  Ths register also holds UG1 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_RSV2_RSV_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_UG0_BAH_BAH_VALUE             ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_UG0_BAH_BAH_VALUE_RESET_VALUE ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_RSV_RSV1_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_RSV_RSV1_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_UG0_BAT_BAT_VALUE             ( 0x1400 )
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_UG0_BAT_BAT_VALUE_RESET_VALUE ( 0x1400 )
+
+
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_OFFSET ( 0x00000034 )
+
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG1_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG1_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG1_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG1_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG1_TRSH ;
+#else
+typedef struct
+{	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG1_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG2_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG2  Ths register also holds UG2 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_RSV2_RSV_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_UG0_BAH_BAH_VALUE             ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_UG0_BAH_BAH_VALUE_RESET_VALUE ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_RSV_RSV1_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_RSV_RSV1_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_UG0_BAT_BAT_VALUE             ( 0x1400 )
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_UG0_BAT_BAT_VALUE_RESET_VALUE ( 0x1400 )
+
+
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_OFFSET ( 0x00000038 )
+
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG2_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG2_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG2_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG2_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG2_TRSH ;
+#else
+typedef struct
+{	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG2_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG3_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG3  Ths register also holds UG3 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_RSV2_RSV_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_UG0_BAH_BAH_VALUE             ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_UG0_BAH_BAH_VALUE_RESET_VALUE ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_RSV_RSV1_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_RSV_RSV1_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_UG0_BAT_BAT_VALUE             ( 0x1400 )
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_UG0_BAT_BAT_VALUE_RESET_VALUE ( 0x1400 )
+
+
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_OFFSET ( 0x0000003C )
+
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG3_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG3_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG3_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG3_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG3_TRSH ;
+#else
+typedef struct
+{	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG3_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG4_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG4  Ths register also holds UG4 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_RSV2_RSV_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_UG0_BAH_BAH_VALUE             ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_UG0_BAH_BAH_VALUE_RESET_VALUE ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_RSV_RSV1_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_RSV_RSV1_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_UG0_BAT_BAT_VALUE             ( 0x1400 )
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_UG0_BAT_BAT_VALUE_RESET_VALUE ( 0x1400 )
+
+
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_OFFSET ( 0x00000040 )
+
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG4_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG4_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG4_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG4_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG4_TRSH ;
+#else
+typedef struct
+{	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG4_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG5_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG5  Ths register also holds UG5 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_RSV2_RSV_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_UG0_BAH_BAH_VALUE             ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_UG0_BAH_BAH_VALUE_RESET_VALUE ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_RSV_RSV1_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_RSV_RSV1_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_UG0_BAT_BAT_VALUE             ( 0x1400 )
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_UG0_BAT_BAT_VALUE_RESET_VALUE ( 0x1400 )
+
+
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_OFFSET ( 0x00000044 )
+
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG5_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG5_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG5_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG5_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG5_TRSH ;
+#else
+typedef struct
+{	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG5_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG6_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG6  Ths register also holds UG6 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_RSV2_RSV_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_UG0_BAH_BAH_VALUE             ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_UG0_BAH_BAH_VALUE_RESET_VALUE ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_RSV_RSV1_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_RSV_RSV1_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_UG0_BAT_BAT_VALUE             ( 0x1400 )
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_UG0_BAT_BAT_VALUE_RESET_VALUE ( 0x1400 )
+
+
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_OFFSET ( 0x00000048 )
+
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG6_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG6_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG6_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG6_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG6_TRSH ;
+#else
+typedef struct
+{	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG6_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG7_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG7  Ths register also holds UG7 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_RSV2_RSV_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_UG0_BAH_BAH_VALUE             ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_UG0_BAH_BAH_VALUE_RESET_VALUE ( 0x200 )
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_RSV_RSV1_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_RSV_RSV1_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_UG0_BAT_BAT_VALUE             ( 0x1400 )
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_UG0_BAT_BAT_VALUE_RESET_VALUE ( 0x1400 )
+
+
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_OFFSET ( 0x0000004C )
+
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG7_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG7_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG7_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG7_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG7_TRSH ;
+#else
+typedef struct
+{	uint32_t ug0_bat	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAT */
+	uint32_t rsv    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug0_bah	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAH */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG7_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_UG_MAP_R0                                                                         */
+/* This register is using for mapping of following Source Ports to UG0…7:  -CPU (or MIPS */
+/* C)  -Runner A  -Runner B  -GPON MAC  -Eth0-3 MAC                                      */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_EMAC3_EMAC3_MAP_VALUE             ( 0x7 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_EMAC3_EMAC3_MAP_VALUE_RESET_VALUE ( 0x7 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_EMAC2_EMAC2_MAP_VALUE             ( 0x6 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_EMAC2_EMAC2_MAP_VALUE_RESET_VALUE ( 0x6 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_EMAC1_EMAC1_MAP_VALUE             ( 0x5 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_EMAC1_EMAC1_MAP_VALUE_RESET_VALUE ( 0x5 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_EMAC0_EMAC0_MAP_VALUE             ( 0x4 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_EMAC0_EMAC0_MAP_VALUE_RESET_VALUE ( 0x4 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_GPON_GPON_MAP_VALUE               ( 0x3 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_GPON_GPON_MAP_VALUE_RESET_VALUE   ( 0x3 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_RNR_B_RNR_B_MAP_VALUE             ( 0x2 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_RNR_B_RNR_B_MAP_VALUE_RESET_VALUE ( 0x2 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_RNR_A_RNR_A_MAP_VALUE             ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_RNR_A_RNR_A_MAP_VALUE_RESET_VALUE ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_CPU__CPU_MAP_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_CPU__CPU_MAP_VALUE_RESET_VALUE    ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_OFFSET ( 0x00000050 )
+
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG_MAP_R0_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG_MAP_R0_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R0_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG_MAP_R0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* EMAC3_mapping */
+	uint32_t emac3	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC2_mapping */
+	uint32_t emac2	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC1_mapping */
+	uint32_t emac1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC0_mapping */
+	uint32_t emac0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_mapping */
+	uint32_t gpon 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_B_mapping */
+	uint32_t rnr_b	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_A_mapping */
+	uint32_t rnr_a	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CPU_mapping */
+	uint32_t cpu_ 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG_MAP_R0 ;
+#else
+typedef struct
+{	uint32_t cpu_ 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CPU_mapping */
+	uint32_t rnr_a	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_A_mapping */
+	uint32_t rnr_b	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_B_mapping */
+	uint32_t gpon 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_mapping */
+	uint32_t emac0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC0_mapping */
+	uint32_t emac1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC1_mapping */
+	uint32_t emac2	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC2_mapping */
+	uint32_t emac3	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC3_mapping */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG_MAP_R0 ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_dbg                                                                               */
+/* BPM select the debug bus                                                              */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_DBG_RSV_RSV_VALUE                           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_DBG_RSV_RSV_VALUE_RESET_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_DBG_SEL_DBG_DEFUALT_VALUE_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_DBG_SEL_DBG_DEFUALT_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_DBG_OFFSET ( 0x00000054 )
+
+#define BPM_MODULE_REGS_BPM_DBG_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_DBG_OFFSET )
+#define BPM_MODULE_REGS_BPM_DBG_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_DBG_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_DBG_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_DBG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* select */
+	uint32_t sel	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_DBG ;
+#else
+typedef struct
+{	uint32_t sel	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* select */
+	uint32_t rsv	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_DBG ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_UG0_BAC                                                                           */
+/* BPM UG0 allocated BN counter                                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG0_BAC_RSV_RSV_VALUE                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG0_BAC_RSV_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG0_BAC_UG0BAC_BAC_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG0_BAC_UG0BAC_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_UG0_BAC_OFFSET ( 0x00000058 )
+
+#define BPM_MODULE_REGS_BPM_UG0_BAC_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG0_BAC_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG0_BAC_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG0_BAC_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG0_BAC_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG0_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAC */
+	uint32_t ug0bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG0_BAC ;
+#else
+typedef struct
+{	uint32_t ug0bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAC */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG0_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_UG1_BAC                                                                           */
+/* BPM UG1 allocated BN Counter                                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG1_BAC_RSV_RSV_VALUE                   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG1_BAC_RSV_RSV_VALUE_RESET_VALUE       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG1_BAC_UG1BAC_UG1BAC_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG1_BAC_UG1BAC_UG1BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_UG1_BAC_OFFSET ( 0x0000005C )
+
+#define BPM_MODULE_REGS_BPM_UG1_BAC_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG1_BAC_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG1_BAC_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG1_BAC_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG1_BAC_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG1_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAC */
+	uint32_t ug1bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG1_BAC ;
+#else
+typedef struct
+{	uint32_t ug1bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG1_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_UG2_BAC                                                                           */
+/* BPM UG2 allocated BN Counter                                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG2_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG2_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG2_BAC_UG2BAC_UG2_BAC_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG2_BAC_UG2BAC_UG2_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_UG2_BAC_OFFSET ( 0x00000060 )
+
+#define BPM_MODULE_REGS_BPM_UG2_BAC_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG2_BAC_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG2_BAC_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG2_BAC_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG2_BAC_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG2_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAC */
+	uint32_t ug2bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG2_BAC ;
+#else
+typedef struct
+{	uint32_t ug2bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG2_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_UG3_BAC                                                                           */
+/* BPM UG3 allocated BN Counter                                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG3_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG3_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG3_BAC_UG3BAC_UG3_BAC_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG3_BAC_UG3BAC_UG3_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_UG3_BAC_OFFSET ( 0x00000064 )
+
+#define BPM_MODULE_REGS_BPM_UG3_BAC_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG3_BAC_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG3_BAC_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG3_BAC_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG3_BAC_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG3_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAC */
+	uint32_t ug3bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG3_BAC ;
+#else
+typedef struct
+{	uint32_t ug3bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG3_BAC */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG3_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_UG4_BAC                                                                           */
+/* BPM UG4 allocated BN Counter                                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG4_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG4_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG4_BAC_UG4BAC_UG4_BAC_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG4_BAC_UG4BAC_UG4_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_UG4_BAC_OFFSET ( 0x00000068 )
+
+#define BPM_MODULE_REGS_BPM_UG4_BAC_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG4_BAC_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG4_BAC_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG4_BAC_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG4_BAC_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG4_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t ug4bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG4_BAC ;
+#else
+typedef struct
+{	uint32_t ug4bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG4_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_UG5_BAC                                                                           */
+/* BPM UG5 allocated BN Counter                                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG5_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG5_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG5_BAC_UG5BAC_UG5_BAC_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG5_BAC_UG5BAC_UG5_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_UG5_BAC_OFFSET ( 0x0000006C )
+
+#define BPM_MODULE_REGS_BPM_UG5_BAC_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG5_BAC_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG5_BAC_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG5_BAC_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG5_BAC_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG5_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t ug5bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG5_BAC ;
+#else
+typedef struct
+{	uint32_t ug5bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG5_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_UG6_BAC                                                                           */
+/* BPM UG6 allocated BN Counter                                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG6_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG6_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG6_BAC_UG6BAC_UG6_BAC_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG6_BAC_UG6BAC_UG6_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_UG6_BAC_OFFSET ( 0x00000070 )
+
+#define BPM_MODULE_REGS_BPM_UG6_BAC_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG6_BAC_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG6_BAC_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG6_BAC_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG6_BAC_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG6_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t ug6bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG6_BAC ;
+#else
+typedef struct
+{	uint32_t ug6bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG6_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_UG7_BAC                                                                           */
+/* BPM UG7 allocated BN Counter                                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG7_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG7_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG7_BAC_UG7BAC_UG7_BAC_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG7_BAC_UG7BAC_UG7_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_UG7_BAC_OFFSET ( 0x00000074 )
+
+#define BPM_MODULE_REGS_BPM_UG7_BAC_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG7_BAC_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG7_BAC_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG7_BAC_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG7_BAC_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG7_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t ug7bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG7_BAC ;
+#else
+typedef struct
+{	uint32_t ug7bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG7_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_GL_BAC                                                                            */
+/* BPM global BN Counter                                                                 */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_GL_BAC_RSV_RSV_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_GL_BAC_RSV_RSV_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_BPM_GL_BAC_BAC_BAC_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_GL_BAC_BAC_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_GL_BAC_OFFSET ( 0x00000078 )
+
+#define BPM_MODULE_REGS_BPM_GL_BAC_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_GL_BAC_OFFSET )
+#define BPM_MODULE_REGS_BPM_GL_BAC_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_GL_BAC_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_GL_BAC_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_GL_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_GL_BAC ;
+#else
+typedef struct
+{	uint32_t bac	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_GL_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_route_address_register_0                                                          */
+/* BPM route addresses of Runner A/B, GPON RX and EMAC0 RX.   Route address configuratio */
+/* n is defined according to topological structure of broad bus                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_RADDR0_RSV4_RSV4_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR0_RSV4_RSV4_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR0_EMAC0_RX_RADDR_EMAC0_RX_ROUTE_ADDRESS_VALUE             ( 0x1F )
+#define BPM_MODULE_REGS_BPM_RADDR0_EMAC0_RX_RADDR_EMAC0_RX_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x1F )
+#define BPM_MODULE_REGS_BPM_RADDR0_RSV3_RSV3_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR0_RSV3_RSV3_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR0_GPON_RX_RADDR_GPON_RX_ROUTE_ADDRESS_VALUE               ( 0x1 )
+#define BPM_MODULE_REGS_BPM_RADDR0_GPON_RX_RADDR_GPON_RX_ROUTE_ADDRESS_VALUE_RESET_VALUE   ( 0x1 )
+#define BPM_MODULE_REGS_BPM_RADDR0_RSV2_RSV_VALUE                                          ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR0_RSV2_RSV_VALUE_RESET_VALUE                              ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR0_RUNB_RADDR_RUNNER_B_ROUTE_ADDRESS_VALUE                 ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR0_RUNB_RADDR_RUNNER_B_ROUTE_ADDRESS_VALUE_RESET_VALUE     ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR0_RSV_RSV_VALUE                                           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR0_RSV_RSV_VALUE_RESET_VALUE                               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR0_RUNA_RADDR_RUNNER_A_ROUTE_ADDRESS_VALUE                 ( 0x2 )
+#define BPM_MODULE_REGS_BPM_RADDR0_RUNA_RADDR_RUNNER_A_ROUTE_ADDRESS_VALUE_RESET_VALUE     ( 0x2 )
+
+
+#define BPM_MODULE_REGS_BPM_RADDR0_OFFSET ( 0x00000084 )
+
+#define BPM_MODULE_REGS_BPM_RADDR0_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_RADDR0_OFFSET )
+#define BPM_MODULE_REGS_BPM_RADDR0_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_RADDR0_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_RADDR0_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_RADDR0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv4 */
+	uint32_t rsv4          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* emac0_Rx_route_address */
+	uint32_t emac0_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gpon_Rx_route_address */
+	uint32_t gpon_rx_raddr 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* runner_B_route_address */
+	uint32_t runb_raddr    	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* runner_A_route_address */
+	uint32_t runa_raddr    	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RADDR0 ;
+#else
+typedef struct
+{	uint32_t runa_raddr    	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* runner_A_route_address */
+	uint32_t rsv           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t runb_raddr    	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* runner_B_route_address */
+	uint32_t rsv2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t gpon_rx_raddr 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gpon_Rx_route_address */
+	uint32_t rsv3          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t emac0_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* emac0_Rx_route_address */
+	uint32_t rsv4          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RADDR0 ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_route_address_register_1                                                          */
+/* BPM route addresses of EMAC 1/2/3/4 RX.  Route address configuration is defined accor */
+/* ding to topological structure of broad bus                                            */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_RADDR1_RSV4_RSV_VALUE                                                       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR1_RSV4_RSV_VALUE_RESET_VALUE                                           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR1_EMAC4_RX_RADDR_EMAC4_RX_ROUTE_ADDRESS_VALUE                          ( 0x11 )
+#define BPM_MODULE_REGS_BPM_RADDR1_EMAC4_RX_RADDR_EMAC4_RX_ROUTE_ADDRESS_VALUE_RESET_VALUE              ( 0x11 )
+#define BPM_MODULE_REGS_BPM_RADDR1_RSV3_RSV_VALUE                                                       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR1_RSV3_RSV_VALUE_RESET_VALUE                                           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR1_EMAC3_RX_RADDR_CONFIGURABLE_EMAC3_RX_ROUTE_ADDRESS_VALUE             ( 0x9 )
+#define BPM_MODULE_REGS_BPM_RADDR1_EMAC3_RX_RADDR_CONFIGURABLE_EMAC3_RX_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x9 )
+#define BPM_MODULE_REGS_BPM_RADDR1_RSV2_RSV2_VALUE                                                      ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR1_RSV2_RSV2_VALUE_RESET_VALUE                                          ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR1_EMAC2_RX_RADDR_EMAC2_ROUTE_ADDRESS_VALUE                             ( 0x17 )
+#define BPM_MODULE_REGS_BPM_RADDR1_EMAC2_RX_RADDR_EMAC2_ROUTE_ADDRESS_VALUE_RESET_VALUE                 ( 0x17 )
+#define BPM_MODULE_REGS_BPM_RADDR1_RSV_RSV_VALUE                                                        ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR1_RSV_RSV_VALUE_RESET_VALUE                                            ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR1_EMAC1_RX_RADDR_EMAC1_ROUTE_ADDRESS_VALUE                             ( 0xF )
+#define BPM_MODULE_REGS_BPM_RADDR1_EMAC1_RX_RADDR_EMAC1_ROUTE_ADDRESS_VALUE_RESET_VALUE                 ( 0xF )
+
+
+#define BPM_MODULE_REGS_BPM_RADDR1_OFFSET ( 0x00000088 )
+
+#define BPM_MODULE_REGS_BPM_RADDR1_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_RADDR1_OFFSET )
+#define BPM_MODULE_REGS_BPM_RADDR1_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_RADDR1_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_RADDR1_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_RADDR1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv4          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* emac4_rx_route_address */
+	uint32_t emac4_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv3          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* emac3_rx_route_address */
+	uint32_t emac3_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* emac2_rx_route_address */
+	uint32_t emac2_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* emac1_rx__route_address */
+	uint32_t emac1_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RADDR1 ;
+#else
+typedef struct
+{	uint32_t emac1_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* emac1_rx__route_address */
+	uint32_t rsv           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t emac2_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* emac2_rx_route_address */
+	uint32_t rsv2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t emac3_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* emac3_rx_route_address */
+	uint32_t rsv3          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t emac4_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* emac4_rx_route_address */
+	uint32_t rsv4          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RADDR1 ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_runner_message_control_register                                                   */
+/* BPM runner message control register includes enables for wake-up messages, select con */
+/* trol bit for transition message and task numbers for wake-up messages to Runners      */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_MIPSD_RPLY_TN_RSV_VALUE                                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_MIPSD_RPLY_TN_RSV_VALUE_RESET_VALUE                                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_TRANS_WKUP_TN_ASK_NUMBER_FOR_RUNNER_ANB_TRANSITION_WAKEUP_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_TRANS_WKUP_TN_ASK_NUMBER_FOR_RUNNER_ANB_TRANSITION_WAKEUP_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RSV3_RSV_VALUE                                                                  ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RSV3_RSV_VALUE_RESET_VALUE                                                      ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_B_RPLY_WKUP_TN_TASK_NUMBER_FOR_RUNNER_B_WAKE_UP_ON_REPLY_VALUE              ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_B_RPLY_WKUP_TN_TASK_NUMBER_FOR_RUNNER_B_WAKE_UP_ON_REPLY_VALUE_RESET_VALUE  ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RSV2_RSV_VALUE                                                                  ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RSV2_RSV_VALUE_RESET_VALUE                                                      ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_A_RPLY_WKUP_TN_TASK_NUMBER_FOR_RUNNER_A_WAKE_UP_ON_REPLY_VALUE              ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_A_RPLY_WKUP_TN_TASK_NUMBER_FOR_RUNNER_A_WAKE_UP_ON_REPLY_VALUE_RESET_VALUE  ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_MIPSD_RPLY_WKUP_EN_REPLY_WAKE_UP_DISABLE_VALUE                                  ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_MIPSD_RPLY_WKUP_EN_REPLY_WAKE_UP_DISABLE_VALUE_RESET_VALUE                      ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_MIPSD_RPLY_WKUP_EN_REPLY_WAKE_UP_ENABLE_VALUE                                   ( 0x1 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_SEL_TRANS_MSG_TRANSITION_MESSAGE_SELECTED_TO_RUNNER_A_VALUE                 ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_SEL_TRANS_MSG_TRANSITION_MESSAGE_SELECTED_TO_RUNNER_A_VALUE_RESET_VALUE     ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_SEL_TRANS_MSG_TRANSITION_MESSAGE_SELECTED_TO_RUNNER_B_VALUE                 ( 0x1 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_TRANS_WKUP_EN_TRANSITION_WAKE_UP_DISABLE_VALUE                              ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_TRANS_WKUP_EN_TRANSITION_WAKE_UP_DISABLE_VALUE_RESET_VALUE                  ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_TRANS_WKUP_EN_TRANSITION_WAKE_UP_ENABLE_VALUE                               ( 0x1 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_RPLY_WKUP_EN_REPLY_WAKE_UP_DISABLE_VALUE                                    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_RPLY_WKUP_EN_REPLY_WAKE_UP_DISABLE_VALUE_RESET_VALUE                        ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_RPLY_WKUP_EN_REPLY_WAKE_UP_ENABLE_VALUE                                     ( 0x1 )
+
+
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_OFFSET ( 0x0000008C )
+
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_OFFSET )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MIPSD_RPLY_TN */
+	uint32_t mipsd_rply_tn     	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_Number_for_Runner_Transition_WakeUp */
+	uint32_t rnr_trans_wkup_tn 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv3              	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_Number_for_Runner_B_Wake_Up_on_Reply */
+	uint32_t rnr_b_rply_wkup_tn	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv2              	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_Number_for_Runner_A_Wake_Up_on_Reply */
+	uint32_t rnr_a_rply_wkup_tn	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MIPSD_Reply_Wake_Up_enable */
+	uint32_t mipsd_rply_wkup_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_Selector_for_Transition_Message */
+	uint32_t rnr_sel_trans_msg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_Transition_Wake_Up_enable */
+	uint32_t rnr_trans_wkup_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_Reply_Wake_Up_enable */
+	uint32_t rnr_rply_wkup_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RNR_MSG_CTRL ;
+#else
+typedef struct
+{	uint32_t rnr_rply_wkup_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_Reply_Wake_Up_enable */
+	uint32_t rnr_trans_wkup_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_Transition_Wake_Up_enable */
+	uint32_t rnr_sel_trans_msg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_Selector_for_Transition_Message */
+	uint32_t mipsd_rply_wkup_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MIPSD_Reply_Wake_Up_enable */
+	uint32_t rnr_a_rply_wkup_tn	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_Number_for_Runner_A_Wake_Up_on_Reply */
+	uint32_t rsv2              	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rnr_b_rply_wkup_tn	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_Number_for_Runner_B_Wake_Up_on_Reply */
+	uint32_t rsv3              	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rnr_trans_wkup_tn 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Task_Number_for_Runner_Transition_WakeUp */
+	uint32_t mipsd_rply_tn     	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MIPSD_RPLY_TN */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RNR_MSG_CTRL ;
+#endif
+
+/*****************************************************************************************/
+/* Runner_Target_address_for_Reply_message                                               */
+/* Runner Target address for Reply message as results of Alloc request from Runner. The  */
+/* register is separeted to two fields: for runner A and B                               */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_RNR_RPLY_TA_RNR_B_TA_TARGET_ADDRESS_FOR_RUNNER_B_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_RPLY_TA_RNR_B_TA_TARGET_ADDRESS_FOR_RUNNER_B_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_RPLY_TA_RNR_A_TA_TARGET_ADDRESS_FOR_RUNNER_A_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RNR_RPLY_TA_RNR_A_TA_TARGET_ADDRESS_FOR_RUNNER_A_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_RNR_RPLY_TA_OFFSET ( 0x00000090 )
+
+#define BPM_MODULE_REGS_BPM_RNR_RPLY_TA_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_RNR_RPLY_TA_OFFSET )
+#define BPM_MODULE_REGS_BPM_RNR_RPLY_TA_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_RNR_RPLY_TA_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_RNR_RPLY_TA_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_RNR_RPLY_TA_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Target_address_for_Runner_B */
+	uint32_t rnr_b_ta	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Target_address_for_Runner_A */
+	uint32_t rnr_a_ta	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RNR_RPLY_TA ;
+#else
+typedef struct
+{	uint32_t rnr_a_ta	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Target_address_for_Runner_A */
+	uint32_t rnr_b_ta	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Target_address_for_Runner_B */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RNR_RPLY_TA ;
+#endif
+
+/*****************************************************************************************/
+/* Runner_Target_Address_for_Wake-Up_message_on_Reply                                    */
+/* Runner Target Address for Wake-Up message for both Runners  as result of Reply to All */
+/* oc request whenever Wake-Up is on                                                     */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA_RNR_B_TADDR_RPLY_WKUP_TARGET_ADDRESS_ON_WAKE_UP_REPLY_TO_RUNNER_B_VALUE             ( 0x8000 )
+#define BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA_RNR_B_TADDR_RPLY_WKUP_TARGET_ADDRESS_ON_WAKE_UP_REPLY_TO_RUNNER_B_VALUE_RESET_VALUE ( 0x8000 )
+#define BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA_RNR_A_TADDR_RPLY_WKUP_TARGET_ADDRESS_ON_WAKE_UP_REPLY_TO_RUNNER_A_VALUE             ( 0x8000 )
+#define BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA_RNR_A_TADDR_RPLY_WKUP_TARGET_ADDRESS_ON_WAKE_UP_REPLY_TO_RUNNER_A_VALUE_RESET_VALUE ( 0x8000 )
+
+
+#define BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA_OFFSET ( 0x00000094 )
+
+#define BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA_OFFSET )
+#define BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Target_Address_on_Wake_Up_reply_to_Runner_B */
+	uint32_t rnr_b_taddr_rply_wkup	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Target_Address_on_Wake_Up_reply_to_Runner_A */
+	uint32_t rnr_a_taddr_rply_wkup	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA ;
+#else
+typedef struct
+{	uint32_t rnr_a_taddr_rply_wkup	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Target_Address_on_Wake_Up_reply_to_Runner_A */
+	uint32_t rnr_b_taddr_rply_wkup	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Target_Address_on_Wake_Up_reply_to_Runner_B */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_Status_register                                                            */
+/* This register is status set of all 8 Ugs: - ACK/NACK state (according to current numb */
+/* er of allocated BNs for the UG and appropriate UG Buffer Allocated Max/Hysteresis thr */
+/* esholds)    - EXCLUSIVE/NON_EXCLUSIVE state (according to current number of allocated */
+/*  BNs for the UG and appropriate UG Exclusive/Hysteresis thresholds)                   */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG_STATUS_RSV2_RSV_VALUE                                       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_RSV2_RSV_VALUE_RESET_VALUE                           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG7_EXCL_STTS_NON_EXCL_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG7_EXCL_STTS_NON_EXCL_VALUE_RESET_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG7_EXCL_STTS_EXCL_VALUE                             ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG6_EXCL_STTS_NON_EXCL_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG6_EXCL_STTS_NON_EXCL_VALUE_RESET_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG6_EXCL_STTS_EXCL_VALUE                             ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG5_EXCL_STTS_NON_EXCL_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG5_EXCL_STTS_NON_EXCL_VALUE_RESET_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG5_EXCL_STTS_EXCL_VALUE                             ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG4_EXCL_STTS_NON_EXCL_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG4_EXCL_STTS_NON_EXCL_VALUE_RESET_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG4_EXCL_STTS_EXCL_VALUE                             ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG3_EXCL_STTS_NON_EXCL_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG3_EXCL_STTS_NON_EXCL_VALUE_RESET_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG3_EXCL_STTS_EXCL_VALUE                             ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG2_EXCL_STTS_NON_EXCL_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG2_EXCL_STTS_NON_EXCL_VALUE_RESET_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG2_EXCL_STTS_EXCL_VALUE                             ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG1_EXCL_STTS_NON_EXCL_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG1_EXCL_STTS_NON_EXCL_VALUE_RESET_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG1_EXCL_STTS_EXCL_VALUE                             ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG0_EXCL_STTS_NON_EXCL_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG0_EXCL_STTS_NON_EXCL_VALUE_RESET_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG0_EXCL_STTS_EXCL_VALUE                             ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_RSV1_GPON_IS_NOT_IN_EXCLUSIVE_MODE_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_RSV1_GPON_IS_NOT_IN_EXCLUSIVE_MODE_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_RSV1_GPON_IS_IN_EXCLUSIVE_MODE_VALUE                 ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG7_STTS_UG7_STATUS_NACK_VALUE                       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG7_STTS_UG7_STATUS_NACK_VALUE_RESET_VALUE           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG7_STTS_UG7_STATUS_ACK_VALUE                        ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG6_STTS_UG6_STATUS_NACK_VALUE                       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG6_STTS_UG6_STATUS_NACK_VALUE_RESET_VALUE           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG6_STTS_UG6_STATUS_ACK_VALUE                        ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG5_STTS_UG5_STATUS_NACK_VALUE                       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG5_STTS_UG5_STATUS_NACK_VALUE_RESET_VALUE           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG5_STTS_UG5_STATUS_ACK_VALUE                        ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG4_STTS_UG4_STATUS_NACK_VALUE                       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG4_STTS_UG4_STATUS_NACK_VALUE_RESET_VALUE           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG4_STTS_UG4_STATUS_ACK_VALUE                        ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG3_STTS_UG3_STATUS_NACK_VALUE                       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG3_STTS_UG3_STATUS_NACK_VALUE_RESET_VALUE           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG3_STTS_UG3_STATUS_ACK_VALUE                        ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG2_STTS_UG2_STATUS_NACK_VALUE                       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG2_STTS_UG2_STATUS_NACK_VALUE_RESET_VALUE           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG2_STTS_UG2_STATUS_ACK_VALUE                        ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG1_STTS_UG1_STATUS_NACK_VALUE                       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG1_STTS_UG1_STATUS_NACK_VALUE_RESET_VALUE           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG1_STTS_UG1_STATUS_ACK_VALUE                        ( 0x1 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG0_STTS_UG0_STATUS_NACK_VALUE                       ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG0_STTS_UG0_STATUS_NACK_VALUE_RESET_VALUE           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_UG0_STTS_UG0_STATUS_ACK_VALUE                        ( 0x1 )
+
+
+#define BPM_MODULE_REGS_BPM_UG_STATUS_OFFSET ( 0x00000098 )
+
+#define BPM_MODULE_REGS_BPM_UG_STATUS_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG_STATUS_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG_STATUS_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG_STATUS_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG_STATUS_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv2 */
+	uint32_t rsv2         	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG7_excl_status */
+	uint32_t ug7_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG6_excl_status */
+	uint32_t ug6_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG5_excl_status */
+	uint32_t ug5_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG4_excl_status */
+	uint32_t ug4_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG3_excl_status */
+	uint32_t ug3_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG2_excl_status */
+	uint32_t ug2_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG1_excl_status */
+	uint32_t ug1_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_excl_status */
+	uint32_t ug0_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t rsv1         	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG7_status */
+	uint32_t ug7_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG6_status */
+	uint32_t ug6_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG5_status */
+	uint32_t ug5_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG4_status */
+	uint32_t ug4_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG3_status */
+	uint32_t ug3_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG2_status */
+	uint32_t ug2_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG1_status */
+	uint32_t ug1_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_status */
+	uint32_t ug0_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG_STATUS ;
+#else
+typedef struct
+{	uint32_t ug0_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_status */
+	uint32_t ug1_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG1_status */
+	uint32_t ug2_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG2_status */
+	uint32_t ug3_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG3_status */
+	uint32_t ug4_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG4_status */
+	uint32_t ug5_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG5_status */
+	uint32_t ug6_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG6_status */
+	uint32_t ug7_stts     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG7_status */
+	uint32_t rsv1         	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t ug0_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_excl_status */
+	uint32_t ug1_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG1_excl_status */
+	uint32_t ug2_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG2_excl_status */
+	uint32_t ug3_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG3_excl_status */
+	uint32_t ug4_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG4_excl_status */
+	uint32_t ug5_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG5_excl_status */
+	uint32_t ug6_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG6_excl_status */
+	uint32_t ug7_excl_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG7_excl_status */
+	uint32_t rsv2         	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG_STATUS ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_ISR_register                                                                      */
+/* This register includes status bits of each BPM source interrupt (at also can be cause */
+/* d by test interrupt trigger)                                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_ISR_RSV_RSV_VALUE                                     ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ISR_RSV_RSV_VALUE_RESET_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ISR_MCNT_ISR_MCNT_ISR_IS_NON_ACTIVE_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ISR_MCNT_ISR_MCNT_ISR_IS_NON_ACTIVE_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ISR_MCNT_ISR_MCNT_ISR_IS_ACTIVE_VALUE                 ( 0x1 )
+#define BPM_MODULE_REGS_BPM_ISR_FREE_ISR_FREE_ISR_IS_INACTIVE_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ISR_FREE_ISR_FREE_ISR_IS_INACTIVE_VALUE_RESET_VALUE   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ISR_FREE_ISR_FREE_ISR_IS_ACTIVE_VALUE                 ( 0x1 )
+
+
+#define BPM_MODULE_REGS_BPM_ISR_OFFSET ( 0x0000009C )
+
+#define BPM_MODULE_REGS_BPM_ISR_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_ISR_OFFSET )
+#define BPM_MODULE_REGS_BPM_ISR_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_ISR_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_ISR_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_ISR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv     	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MCNT_Interrupt_source */
+	uint32_t mcnt_isr	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Free_Interrupt_source */
+	uint32_t free_isr	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_ISR ;
+#else
+typedef struct
+{	uint32_t free_isr	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Free_Interrupt_source */
+	uint32_t mcnt_isr	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MCNT_Interrupt_source */
+	uint32_t rsv     	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_ISR ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_IER_register                                                                      */
+/* This register includes enable controls per each source. Enable bit affects on BPM IRQ */
+/*  output to Interrupt Controller                                                       */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_IER_RSV_RSV_VALUE                                ( 0x0 )
+#define BPM_MODULE_REGS_BPM_IER_RSV_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define BPM_MODULE_REGS_BPM_IER_MCNT_IER_MCNT_IRQ_DISABLED_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_IER_MCNT_IER_MCNT_IRQ_DISABLED_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_BPM_IER_MCNT_IER_MCNT_IRQ_ENABLED_VALUE              ( 0x1 )
+#define BPM_MODULE_REGS_BPM_IER_FREE_IER_FREE_IRQ_DISABLED_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_IER_FREE_IER_FREE_IRQ_DISABLED_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_BPM_IER_FREE_IER_FREE_IRQ_ENABLED_VALUE              ( 0x1 )
+
+
+#define BPM_MODULE_REGS_BPM_IER_OFFSET ( 0x00000100 )
+
+#define BPM_MODULE_REGS_BPM_IER_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_IER_OFFSET )
+#define BPM_MODULE_REGS_BPM_IER_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_IER_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_IER_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_IER_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv     	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Enable_for_MCNT_IRQ */
+	uint32_t mcnt_ier	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Enable_for_Free_IRQ */
+	uint32_t free_ier	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_IER ;
+#else
+typedef struct
+{	uint32_t free_ier	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Enable_for_Free_IRQ */
+	uint32_t mcnt_ier	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Enable_for_MCNT_IRQ */
+	uint32_t rsv     	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_IER ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_ITR_register                                                                      */
+/* This register allows emulate BPM IRQs by serring relevant bit in ITR register         */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_ITR_RSV_RSV_VALUE                                     ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ITR_RSV_RSV_VALUE_RESET_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ITR_MCNT_ITR_MCNT_IRQ_DISABLED_VALUE                  ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ITR_MCNT_ITR_MCNT_IRQ_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ITR_MCNT_ITR_MCNT_IRQ_ENABLED_VALUE                   ( 0x1 )
+#define BPM_MODULE_REGS_BPM_ITR_FREE_ITR_FREE_TEST_IRQ_DISABLED_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ITR_FREE_ITR_FREE_TEST_IRQ_DISABLED_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_BPM_ITR_FREE_ITR_FREE_TEST_IRQ_ENABLED_VALUE              ( 0x1 )
+
+
+#define BPM_MODULE_REGS_BPM_ITR_OFFSET ( 0x00000104 )
+
+#define BPM_MODULE_REGS_BPM_ITR_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_ITR_OFFSET )
+#define BPM_MODULE_REGS_BPM_ITR_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_ITR_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_ITR_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_ITR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv     	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MCNT_Test_IRQ */
+	uint32_t mcnt_itr	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Free_Test_IRQ */
+	uint32_t free_itr	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_ITR ;
+#else
+typedef struct
+{	uint32_t free_itr	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Free_Test_IRQ */
+	uint32_t mcnt_itr	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MCNT_Test_IRQ */
+	uint32_t rsv     	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_ITR ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_UG_MAP_R1                                                                         */
+/* Each Source Port is mapped to specified UG. This register is using for mapping of  th */
+/* e following Source Ports to UG0…7:  -Eth MAC4  -MIPSD  -PCIe 0/1  -USB 0/1  -Two spar */
+/* e ports                                                                               */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_SPARE1_SPARE2_MAP_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_SPARE1_SPARE2_MAP_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_SPARE0_SPARE1_MAP_VALUE             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_SPARE0_SPARE1_MAP_VALUE_RESET_VALUE ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_USB1_SPARE0_MAP_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_USB1_SPARE0_MAP_VALUE_RESET_VALUE   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_USB0_USB_MAP_VALUE                  ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_USB0_USB_MAP_VALUE_RESET_VALUE      ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_PCIE1_PCIE1_MAP_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_PCIE1_PCIE1_MAP_VALUE_RESET_VALUE   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_PCIE0_PCIE0_MAP_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_PCIE0_PCIE0_MAP_VALUE_RESET_VALUE   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_MIPSD_EMAC5_MAP_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_MIPSD_EMAC5_MAP_VALUE_RESET_VALUE   ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_EMAC4_EMAC4_MAP_VALUE               ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_EMAC4_EMAC4_MAP_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_OFFSET ( 0x00000108 )
+
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG_MAP_R1_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG_MAP_R1_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG_MAP_R1_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG_MAP_R1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Spare1_mapping */
+	uint32_t spare1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Spare0_mapping */
+	uint32_t spare0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USB1_mapping */
+	uint32_t usb1  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USB0_mapping */
+	uint32_t usb0  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE1_mapping */
+	uint32_t pcie1 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE0_mapping */
+	uint32_t pcie0 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MIPSD_mapping */
+	uint32_t mipsd 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC4_mapping */
+	uint32_t emac4 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG_MAP_R1 ;
+#else
+typedef struct
+{	uint32_t emac4 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC4_mapping */
+	uint32_t mipsd 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MIPSD_mapping */
+	uint32_t pcie0 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE0_mapping */
+	uint32_t pcie1 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE1_mapping */
+	uint32_t usb0  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USB0_mapping */
+	uint32_t usb1  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USB1_mapping */
+	uint32_t spare0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Spare0_mapping */
+	uint32_t spare1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Spare1_mapping */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG_MAP_R1 ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_0_Exclusive_Thresholds                                                     */
+/* User Group 0 Exclusive Thresholds: high exclusive threshold (when the high threshold  */
+/* is crossed up - BPM sends Enter EXCLUSIVE message to al BBH clients in this group) an */
+/* d hysteresis to low threshold (when this threshold is crossed down - BPM sends Exit E */
+/* XCLUSIVE message to al BBH clients in this group). The exclusive status is also aplie */
+/* d in reply messages                                                                   */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_RSV2_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_RSV2_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE             ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE_RESET_VALUE ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_RSV1_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_RSV1_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE                ( 0x1000 )
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE_RESET_VALUE    ( 0x1000 )
+
+
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_OFFSET ( 0x0000010C )
+
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_1_Exclusive_Thresholds                                                     */
+/* User Group 1 Exclusive Thresholds: high exclusive threshold (when the high threshold  */
+/* is crossed up - BPM sends Enter EXCLUSIVE message to al BBH clients in this group) an */
+/* d hysteresis to low threshold (when this threshold is crossed down - BPM sends Exit E */
+/* XCLUSIVE message to al BBH clients in this group). The exclusive status is also aplie */
+/* d in reply messages                                                                   */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_RSV2_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_RSV2_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE             ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE_RESET_VALUE ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_RSV1_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_RSV1_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE                ( 0x1000 )
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE_RESET_VALUE    ( 0x1000 )
+
+
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_OFFSET ( 0x00000110 )
+
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_2_Exclusive_Thresholds                                                     */
+/* User Group 2 Exclusive Thresholds: high exclusive threshold (when the high threshold  */
+/* is crossed up - BPM sends Enter EXCLUSIVE message to al BBH clients in this group) an */
+/* d hysteresis to low threshold (when this threshold is crossed down - BPM sends Exit E */
+/* XCLUSIVE message to al BBH clients in this group). The exclusive status is also aplie */
+/* d in reply messages                                                                   */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_RSV2_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_RSV2_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE             ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE_RESET_VALUE ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_RSV1_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_RSV1_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE                ( 0x1000 )
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE_RESET_VALUE    ( 0x1000 )
+
+
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_OFFSET ( 0x00000114 )
+
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_3_Exclusive_Thresholds                                                     */
+/* User Group 3 Exclusive Thresholds: high exclusive threshold (when the high threshold  */
+/* is crossed up - BPM sends Enter EXCLUSIVE message to al BBH clients in this group) an */
+/* d hysteresis to low threshold (when this threshold is crossed down - BPM sends Exit E */
+/* XCLUSIVE message to al BBH clients in this group). The exclusive status is also aplie */
+/* d in reply messages                                                                   */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_RSV2_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_RSV2_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE             ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE_RESET_VALUE ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_RSV1_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_RSV1_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE                ( 0x1000 )
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE_RESET_VALUE    ( 0x1000 )
+
+
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_OFFSET ( 0x00000118 )
+
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_4_Exclusive_Thresholds                                                     */
+/* User Group 4 Exclusive Thresholds: high exclusive threshold (when the high threshold  */
+/* is crossed up - BPM sends Enter EXCLUSIVE message to al BBH clients in this group) an */
+/* d hysteresis to low threshold (when this threshold is crossed down - BPM sends Exit E */
+/* XCLUSIVE message to al BBH clients in this group). The exclusive status is also aplie */
+/* d in reply messages                                                                   */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_RSV2_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_RSV2_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE             ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE_RESET_VALUE ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_RSV1_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_RSV1_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE                ( 0x1000 )
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE_RESET_VALUE    ( 0x1000 )
+
+
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_OFFSET ( 0x0000011C )
+
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_5_Exclusive_Thresholds                                                     */
+/* User Group 5 Exclusive Thresholds: high exclusive threshold (when the high threshold  */
+/* is crossed up - BPM sends Enter EXCLUSIVE message to al BBH clients in this group) an */
+/* d hysteresis to low threshold (when this threshold is crossed down - BPM sends Exit E */
+/* XCLUSIVE message to al BBH clients in this group). The exclusive status is also aplie */
+/* d in reply messages                                                                   */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_RSV2_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_RSV2_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE             ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE_RESET_VALUE ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_RSV1_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_RSV1_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE                ( 0x1000 )
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE_RESET_VALUE    ( 0x1000 )
+
+
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_OFFSET ( 0x00000120 )
+
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_6_Exclusive_Thresholds                                                     */
+/* User Group 6 Exclusive Thresholds: high exclusive threshold (when the high threshold  */
+/* is crossed up - BPM sends Enter EXCLUSIVE message to al BBH clients in this group) an */
+/* d hysteresis to low threshold (when this threshold is crossed down - BPM sends Exit E */
+/* XCLUSIVE message to al BBH clients in this group). The exclusive status is also aplie */
+/* d in reply messages                                                                   */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_RSV2_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_RSV2_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE             ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE_RESET_VALUE ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_RSV1_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_RSV1_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE                ( 0x1000 )
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE_RESET_VALUE    ( 0x1000 )
+
+
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_OFFSET ( 0x00000124 )
+
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_7_Exclusive_Thresholds                                                     */
+/* User Group 7 Exclusive Thresholds: high exclusive threshold (when the high threshold  */
+/* is crossed up - BPM sends Enter EXCLUSIVE message to al BBH clients in this group) an */
+/* d hysteresis to low threshold (when this threshold is crossed down - BPM sends Exit E */
+/* XCLUSIVE message to al BBH clients in this group). The exclusive status is also aplie */
+/* d in reply messages                                                                   */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_RSV2_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_RSV2_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE             ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_UG_EXCL_HYST_UG_EXCLUSIVE_HYSTERESIS_VALUE_RESET_VALUE ( 0x100 )
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_RSV1_RSV_VALUE                                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_RSV1_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE                ( 0x1000 )
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_UG_EXCL_TR_UG_EXCLUSIVE_THRESHOLD_VALUE_RESET_VALUE    ( 0x1000 )
+
+
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_OFFSET ( 0x00000128 )
+
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_OFFSET )
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_excl_tr  	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_high_threshold */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ug_excl_hyst	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_exclusive_hysteresis */
+	uint32_t rsv2        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_route_address_register_2                                                          */
+/* BPM route addresses of MIPSD                                                          */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_RADDR2_RSV_RSV_VALUE                                     ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR2_RSV_RSV_VALUE_RESET_VALUE                         ( 0x0 )
+#define BPM_MODULE_REGS_BPM_RADDR2_MIPSD_RADDR_MIPSD_ROUTE_ADDRESS_VALUE             ( 0x6 )
+#define BPM_MODULE_REGS_BPM_RADDR2_MIPSD_RADDR_MIPSD_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x6 )
+
+
+#define BPM_MODULE_REGS_BPM_RADDR2_OFFSET ( 0x0000012C )
+
+#define BPM_MODULE_REGS_BPM_RADDR2_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_RADDR2_OFFSET )
+#define BPM_MODULE_REGS_BPM_RADDR2_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_RADDR2_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_RADDR2_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_RADDR2_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv        	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MIPSD_route_address */
+	uint32_t mipsd_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RADDR2 ;
+#else
+typedef struct
+{	uint32_t mipsd_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MIPSD_route_address */
+	uint32_t rsv        	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_RADDR2 ;
+#endif
+
+/*****************************************************************************************/
+/* BPM_MIPSD_RPLY_TA                                                                     */
+/* Target address for Reply message as results of Alloc request from MIPSD. The register */
+/*  is separeted to two fields:   (1) for regular reply on Alloc   (2) for wake-up reply */
+/*  (as regular Runner default = 0x8000)                                                 */
+/*****************************************************************************************/
+
+#define BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA_RPLY_TA_BROADBUS_ADDRESS_VALUE                  ( 0x0 )
+#define BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA_RPLY_TA_BROADBUS_ADDRESS_VALUE_RESET_VALUE      ( 0x0 )
+#define BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA_WKUP_RPLY_TA_BROADBUS_ADDRESS_VALUE             ( 0x8000 )
+#define BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA_WKUP_RPLY_TA_BROADBUS_ADDRESS_VALUE_RESET_VALUE ( 0x8000 )
+
+
+#define BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA_OFFSET ( 0x00000130 )
+
+#define BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA_OFFSET )
+#define BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RPLY_TA */
+	uint32_t rply_ta     	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* WKUP_RPLY_TA */
+	uint32_t wkup_rply_ta	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA ;
+#else
+typedef struct
+{	uint32_t wkup_rply_ta	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* WKUP_RPLY_TA */
+	uint32_t rply_ta     	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RPLY_TA */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA ;
+#endif
+
+#define BPM_MODULE_REGS_BPM_SPARE_BN_MSG_FORMAT_14_BIT_BN_WIDTH                           ( 0x0 )
+#define BPM_MODULE_REGS_BPM_SPARE_BN_MSG_FORMAT_15_BIT_BN_WIDTH                           ( 0x1 )
+#define BPM_MODULE_REGS_BPM_SPARE_OFFSET ( 0x0000013C )
+#define BPM_MODULE_REGS_BPM_SPARE_ADDRESS   	( BPM_MODULE_REGS_ADDRESS + BPM_MODULE_REGS_BPM_SPARE_OFFSET )
+#define BPM_MODULE_REGS_BPM_SPARE_READ( r ) 	READ_32( ( BPM_MODULE_REGS_BPM_SPARE_ADDRESS ), (r) )
+#define BPM_MODULE_REGS_BPM_SPARE_WRITE( v )	WRITE_32( ( BPM_MODULE_REGS_BPM_SPARE_ADDRESS ), (v) )
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	uint32_t rsv        	: 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	uint32_t bn_msg_format 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	uint32_t spare_bits		: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_SPARE ;
+#else
+typedef struct
+{	uint32_t spare_bits		: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	uint32_t bn_msg_format 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	uint32_t rsv        	: 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS_BPM_SPARE ;
+#endif
+typedef struct
+{
+	/* Request_pointer */
+	BPM_MODULE_REGS_REQ_PTR req_ptr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Free_pointer */
+	BPM_MODULE_REGS_FREE_PTR free_ptr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Multi_Cast_Counter_set_for_pointer */
+	BPM_MODULE_REGS_MCNT_PTR mcnt_ptr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Init_of_BPM_Core_RAMs */
+	BPM_MODULE_REGS_RAM_INIT ram_init __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* free_pointer_interrupt */
+	BPM_MODULE_REGS_FREE_PTR_INT free_ptr_int __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Read_ram_address */
+	BPM_MODULE_REGS_READ_RAM_ADDR read_ram_addr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MCNT_pointer_interrupt */
+	BPM_MODULE_REGS_MCNT_PTR_INT mcnt_ptr_int __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* read_ram_data0 */
+	BPM_MODULE_REGS_READ_RAM_DATA0 read_ram_data0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* read_ram_data1 */
+	BPM_MODULE_REGS_READ_RAM_DATA1 read_ram_data1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* read_ram_data2 */
+	BPM_MODULE_REGS_READ_RAM_DATA2 read_ram_data2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Source_Port_enable */
+	BPM_MODULE_REGS_BPM_SP_EN bpm_sp_en __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Threshold */
+	BPM_MODULE_REGS_BPM_GL_TRSH bpm_gl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_Threshold */
+	BPM_MODULE_REGS_BPM_UG0_TRSH bpm_ug0_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG1_Threshold */
+	BPM_MODULE_REGS_BPM_UG1_TRSH bpm_ug1_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG2_Threshold */
+	BPM_MODULE_REGS_BPM_UG2_TRSH bpm_ug2_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG3_Threshold */
+	BPM_MODULE_REGS_BPM_UG3_TRSH bpm_ug3_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG4_Threshold */
+	BPM_MODULE_REGS_BPM_UG4_TRSH bpm_ug4_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG5_Threshold */
+	BPM_MODULE_REGS_BPM_UG5_TRSH bpm_ug5_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG6_Threshold */
+	BPM_MODULE_REGS_BPM_UG6_TRSH bpm_ug6_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG7_Threshold */
+	BPM_MODULE_REGS_BPM_UG7_TRSH bpm_ug7_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_UG_MAP_R0 */
+	BPM_MODULE_REGS_BPM_UG_MAP_R0 bpm_ug_map_r0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_dbg */
+	BPM_MODULE_REGS_BPM_DBG bpm_dbg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_UG0_BAC */
+	BPM_MODULE_REGS_BPM_UG0_BAC bpm_ug0_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_UG1_BAC */
+	BPM_MODULE_REGS_BPM_UG1_BAC bpm_ug1_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_UG2_BAC */
+	BPM_MODULE_REGS_BPM_UG2_BAC bpm_ug2_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_UG3_BAC */
+	BPM_MODULE_REGS_BPM_UG3_BAC bpm_ug3_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_UG4_BAC */
+	BPM_MODULE_REGS_BPM_UG4_BAC bpm_ug4_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_UG5_BAC */
+	BPM_MODULE_REGS_BPM_UG5_BAC bpm_ug5_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_UG6_BAC */
+	BPM_MODULE_REGS_BPM_UG6_BAC bpm_ug6_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_UG7_BAC */
+	BPM_MODULE_REGS_BPM_UG7_BAC bpm_ug7_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_GL_BAC */
+	BPM_MODULE_REGS_BPM_GL_BAC bpm_gl_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 8 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_route_address_register_0 */
+	BPM_MODULE_REGS_BPM_RADDR0 bpm_raddr0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_route_address_register_1 */
+	BPM_MODULE_REGS_BPM_RADDR1 bpm_raddr1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_runner_message_control_register */
+	BPM_MODULE_REGS_BPM_RNR_MSG_CTRL bpm_rnr_msg_ctrl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_Target_address_for_Reply_message */
+	BPM_MODULE_REGS_BPM_RNR_RPLY_TA bpm_rnr_rply_ta __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_Target_Address_for_Wake-Up_message_on_Reply */
+	BPM_MODULE_REGS_BPM_RNR_WKUP_RPLY_TA bpm_rnr_wkup_rply_ta __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_Status_register */
+	BPM_MODULE_REGS_BPM_UG_STATUS bpm_ug_status __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_ISR_register */
+	BPM_MODULE_REGS_BPM_ISR bpm_isr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved2 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_IER_register */
+	BPM_MODULE_REGS_BPM_IER bpm_ier __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_ITR_register */
+	BPM_MODULE_REGS_BPM_ITR bpm_itr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_UG_MAP_R1 */
+	BPM_MODULE_REGS_BPM_UG_MAP_R1 bpm_ug_map_r1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_0_Exclusive_Thresholds */
+	BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH bpm_ug0_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_1_Exclusive_Thresholds */
+	BPM_MODULE_REGS_BPM_UG1_EXCL_TRSH bpm_ug1_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_2_Exclusive_Thresholds */
+	BPM_MODULE_REGS_BPM_UG2_EXCL_TRSH bpm_ug2_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_3_Exclusive_Thresholds */
+	BPM_MODULE_REGS_BPM_UG3_EXCL_TRSH bpm_ug3_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_4_Exclusive_Thresholds */
+	BPM_MODULE_REGS_BPM_UG4_EXCL_TRSH bpm_ug4_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_5_Exclusive_Thresholds */
+	BPM_MODULE_REGS_BPM_UG5_EXCL_TRSH bpm_ug5_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_6_Exclusive_Thresholds */
+	BPM_MODULE_REGS_BPM_UG6_EXCL_TRSH bpm_ug6_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_7_Exclusive_Thresholds */
+	BPM_MODULE_REGS_BPM_UG7_EXCL_TRSH bpm_ug7_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_route_address_register_2 */
+	BPM_MODULE_REGS_BPM_RADDR2 bpm_raddr2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BPM_MIPSD_RPLY_TA */
+	BPM_MODULE_REGS_BPM_MIPSD_RPLY_TA bpm_mipsd_rply_ta __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	BPM_MODULE_REGS_BPM_SPARE bpm_spare __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE_REGS ;
+
+typedef struct
+{
+	/* regs function */
+	BPM_MODULE_REGS regs __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+BPM_MODULE ;
+
+typedef struct
+{
+	/* MODULE */
+	BPM_MODULE module __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ 
+BPM_FOR_ALL ;
+#endif /* BPM_H_INCLUDED */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring.c b/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring.c
new file mode 100755
index 0000000000..0317351de0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring.c
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+   
+ */
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the implementation of the Runner CPU ring interface     */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+#define INTERN_PRINT printf
+
+#if !defined(RDP_SIM) || defined(XRDP)
+#include "rdp_cpu_ring.h"
+#include "rdp_cpu_ring_inline.h"
+#include "rdp_mm.h"
+
+#define ____cacheline_aligned
+#define shell_print(dummy,format,...) xprintf(format, ##__VA_ARGS__)
+
+#if !defined(XRDP) && !defined(__KERNEL__) && !defined(__UBOOT__)
+#error "rdp_cpu_ring is supported only in CFE and Kernel modules or XRDP simulator"
+#endif
+
+RING_DESCTIPTOR ____cacheline_aligned host_ring[D_NUM_OF_RING_DESCRIPTORS] =
+    { };
+EXPORT_SYMBOL(host_ring);
+
+/*delete a preallocated ring*/
+int rdp_cpu_ring_delete_ring(uint32_t ring_id)
+{
+	RING_DESCTIPTOR *pDescriptor;
+	int rc;
+
+	pDescriptor = &host_ring[ring_id];
+	if (!pDescriptor->num_of_entries) {
+		INTERN_PRINT("ERROR:deleting ring_id %d which does not exists!",
+			     ring_id);
+		return -1;
+	}
+
+	rc = rdp_cpu_ring_buffers_free(pDescriptor);
+	if (rc) {
+		INTERN_PRINT
+		    ("ERROR: failed free ring buffers ring_id %d, err %d\n",
+		     ring_id, rc);
+		return rc;
+	}
+
+	/* free any buffers in buff_cache */
+	while (pDescriptor->buff_cache_cnt) {
+		pDescriptor->databuf_free(pDescriptor->
+					  buff_cache[--pDescriptor->
+						     buff_cache_cnt], 0,
+					  pDescriptor);
+	}
+
+	/*free buff_cache */
+	if (pDescriptor->buff_cache)
+		CACHED_FREE(pDescriptor->buff_cache);
+
+	/*delete the ring of descriptors in case of non-coherent */
+#ifndef RDP_SIM
+	if (pDescriptor->base) {
+		rdp_mm_aligned_free((void *)(pDescriptor->base),
+				    pDescriptor->num_of_entries *
+				    pDescriptor->size_of_entry);
+	}
+#endif
+	pDescriptor->num_of_entries = 0;
+
+	return 0;
+}
+
+EXPORT_SYMBOL(rdp_cpu_ring_delete_ring);
+
+int rdp_cpu_ring_create_ring(uint32_t ring_id,
+			     uint8_t ring_type,
+			     uint32_t entries,
+			     bdmf_phys_addr_t * ring_head,
+			     uint32_t packetSize,
+			     RING_CB_FUNC * ringCb, uint32_t ring_prio)
+{
+	return rdp_cpu_ring_create_ring_ex(ring_id, ring_type, entries,
+					   ring_head, NULL, packetSize, ringCb,
+					   ring_prio);
+}
+
+EXPORT_SYMBOL(rdp_cpu_ring_create_ring);
+
+/* Using void * instead of (rdpa_cpu_rxq_ic_cfg_t *) to avoid CFE compile errors*/
+int rdp_cpu_ring_create_ring_ex(uint32_t ring_id,
+				uint8_t ring_type,
+				uint32_t entries,
+				bdmf_phys_addr_t * ring_head,
+				bdmf_phys_addr_t * rw_idx_addr,
+				uint32_t packetSize,
+				RING_CB_FUNC * ringCb, uint32_t ring_prio)
+{
+	RING_DESCTIPTOR *pDescriptor;
+	bdmf_phys_addr_t phy_addr = 0;
+
+	if (ring_id >= RING_ID_NUM_OF) {
+		INTERN_PRINT("ERROR: ring_id %d out of range(%d)", ring_id,
+			     RING_ID_NUM_OF);
+		return -1;
+	}
+
+	pDescriptor = &host_ring[ring_id];
+
+	if (pDescriptor->num_of_entries) {
+		INTERN_PRINT
+		    ("ERROR: ring_id %d already exists! must be deleted first",
+		     ring_id);
+		return -1;
+	}
+
+	if (!entries) {
+		INTERN_PRINT("ERROR: can't create ring with 0 packets\n");
+		return -1;
+	}
+
+	/*set ring parameters */
+	pDescriptor->ring_id = ring_id;
+	pDescriptor->num_of_entries = entries;
+	pDescriptor->num_of_entries_mask = pDescriptor->num_of_entries - 1;
+	pDescriptor->ring_prio = ring_prio;
+
+#ifdef XRDP
+	if (ring_type == rdpa_ring_feed)
+		pDescriptor->size_of_entry = sizeof(CPU_FEED_DESCRIPTOR);
+	else if (ring_type == rdpa_ring_recycle)
+		pDescriptor->size_of_entry = sizeof(CPU_RECYCLE_DESCRIPTOR);
+	else if (ring_type == rdpa_ring_cpu_tx)
+		pDescriptor->size_of_entry =
+		    sizeof(RDD_RING_CPU_TX_DESCRIPTOR_DTS);
+	else if (ring_type == rdpa_ring_data)
+#endif
+		pDescriptor->size_of_entry = sizeof(CPU_RX_DESCRIPTOR);
+
+	INTERN_PRINT
+	    ("Creating CPU ring for queue number %d with %d packets descriptor=0x%p, size_of_entry %d\n",
+	     ring_id, entries, pDescriptor, pDescriptor->size_of_entry);
+
+	pDescriptor->buff_cache_cnt = 0;
+	pDescriptor->packet_size = packetSize;
+	pDescriptor->type = ring_type;
+
+	pDescriptor->databuf_alloc = rdp_databuf_alloc;
+	pDescriptor->databuf_free = rdp_databuf_free;
+	pDescriptor->data_dump = rdp_packet_dump;
+
+	if (ringCb) {		/* overwrite if needed */
+		pDescriptor->data_dump = ringCb->data_dump;
+		pDescriptor->buff_mem_context = ringCb->buff_mem_context;
+#ifndef XRDP
+		pDescriptor->databuf_alloc = ringCb->databuf_alloc;
+		pDescriptor->databuf_free = ringCb->databuf_free;
+#endif
+	}
+
+	/*TODO:update the comment  allocate buff_cache which helps to reduce the overhead of when 
+	 * allocating data buffers to ring descriptor */
+	pDescriptor->buff_cache =
+	    (uint8_t
+	     **) (CACHED_MALLOC_ATOMIC(sizeof(uint8_t *) * MAX_BUFS_IN_CACHE));
+	if (pDescriptor->buff_cache == NULL) {
+		INTERN_PRINT
+		    ("failed to allocate memory for cache of data buffers \n");
+		return -1;
+	}
+
+	/*allocate ring descriptors - must be non-cacheable memory */
+	pDescriptor->base =
+	    rdp_mm_aligned_alloc((pDescriptor->size_of_entry * entries),
+				 &phy_addr);
+	if (pDescriptor->base == NULL) {
+		INTERN_PRINT("failed to allocate memory for ring descriptor\n");
+		rdp_cpu_ring_delete_ring(ring_id);
+		return -1;
+	}
+
+	if (rdp_cpu_ring_buffers_init(pDescriptor, ring_id))
+		return -1;
+
+#ifndef XRDP
+	/*set the ring header to the first entry */
+	pDescriptor->head = (CPU_RX_DESCRIPTOR *) pDescriptor->base;
+
+	/*using pointer arithmetics calculate the end of the ring */
+	pDescriptor->end = (CPU_RX_DESCRIPTOR *) pDescriptor->base + entries;
+#endif
+
+	*ring_head = phy_addr;
+
+#ifndef XRDP
+	INTERN_PRINT("Done initializing Ring %d Base=0x%pK End=0x%pK "
+		     "calculated entries= %ld RDD Base=%lxK descriptor=0x%p\n",
+		     ring_id, pDescriptor->base, pDescriptor->end,
+		     (long)(pDescriptor->end -
+			    (CPU_RX_DESCRIPTOR *) pDescriptor->base),
+		     (unsigned long)phy_addr, pDescriptor);
+#else
+	INTERN_PRINT
+	    ("Done initializing Ring %d Base=0x%p num of entries= %d RDD Base=%lx descriptor=0x%p\n",
+	     ring_id, pDescriptor->base, pDescriptor->num_of_entries,
+	     (unsigned long)phy_addr, pDescriptor);
+#endif
+
+	return 0;
+}
+
+EXPORT_SYMBOL(rdp_cpu_ring_create_ring_ex);
+
+#if defined(__UBOOT__) || !(defined(CONFIG_BCM63138) || defined(CONFIG_BCM63148))
+/*this API copies the next available packet from ring to given pointer*/
+int rdp_cpu_ring_read_packet_copy(uint32_t ring_id, CPU_RX_PARAMS * rxParams)
+{
+	RING_DESCTIPTOR *pDescriptor = &host_ring[ring_id];
+#ifndef XRDP
+	volatile CPU_RX_DESCRIPTOR *pTravel =
+	    (volatile CPU_RX_DESCRIPTOR *)pDescriptor->head;
+#endif
+	void *client_pdata;
+	uint32_t ret = 0;
+
+	/* Data offset field is field ONLY in CFE driver on BCM6858 
+	 * To ensure correct work of another platforms the data offset field should be zeroed */
+	rxParams->data_offset = 0;
+
+	client_pdata = (void *)rxParams->data_ptr;
+
+#ifndef XRDP
+	ret = ReadPacketFromRing(pDescriptor, pTravel, rxParams);
+#else
+	ret = ReadPacketFromRing(pDescriptor, rxParams);
+#endif
+	if (ret)
+		goto exit;
+
+	/*copy the data to user buffer */
+	/*TODO: investigate why INV_RANGE is needed before memcpy, */
+	INV_RANGE((rxParams->data_ptr + rxParams->data_offset),
+		  rxParams->packet_size);
+	memcpy(client_pdata,
+	       (void *)(rxParams->data_ptr + rxParams->data_offset),
+	       rxParams->packet_size);
+
+	/*Assign the data buffer back to ring */
+	INV_RANGE((rxParams->data_ptr + rxParams->data_offset),
+		  rxParams->packet_size);
+#ifndef XRDP
+	AssignPacketBuffertoRing(pDescriptor, pTravel, rxParams->data_ptr);
+#else
+	AssignPacketBuffertoRing(pDescriptor, rxParams->data_ptr);
+#endif
+
+exit:
+	rxParams->data_ptr = client_pdata;
+	return ret;
+}
+#endif
+
+/* Callback Functions */
+
+void rdp_packet_dump(uint32_t ringId, rdpa_cpu_rx_info_t * info)
+{
+	char name[10];
+
+	sprintf(name, "Queue-%d", ringId);
+#if !defined( __UBOOT__) && defined(__KERNEL__)
+	rdpa_cpu_rx_dump_packet(name, rdpa_cpu_host, ringId, info, 0);
+#endif
+}
+
+EXPORT_SYMBOL(rdp_packet_dump);
+
+void *rdp_databuf_alloc(RING_DESCTIPTOR * pDescriptor)
+{
+	void *pBuf = KMALLOC(BCM_PKTBUF_SIZE, 64);
+
+	if (pBuf) {
+		INV_RANGE(pBuf, BCM_PKTBUF_SIZE);
+		return pBuf;
+	}
+	return NULL;
+}
+
+void rdp_databuf_free(void *pBuf, uint32_t context,
+		      RING_DESCTIPTOR * pDescriptor)
+{
+	KFREE(pBuf);
+}
+
+#endif
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring.h b/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring.h
new file mode 100755
index 0000000000..8b26b81ca7
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring.h
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the implementation of the Runner CPU ring interface     */
+/*                                                                            */
+/******************************************************************************/
+
+#ifndef _RDP_CPU_RING_H_
+#define _RDP_CPU_RING_H_
+
+#if !defined(RDP_SIM) || defined(XRDP)
+
+#if defined(__KERNEL__) || defined(__UBOOT__)
+#include "bcm_pkt_lengths.h"
+#include "bcm_mm.h"
+#if defined(__UBOOT__) && defined(XRDP)
+#include "rdp_subsystem_common.h"
+#endif
+#endif
+
+#include "rdpa_types.h"
+#include "rdpa_cpu_basic.h"
+#include "rdd.h"
+#include "rdp_cpu_ring_defs.h"
+
+#ifdef __UBOOT__
+
+#ifndef XRDP
+#define RDP_CPU_RING_MAX_QUEUES	1
+#define RDP_WLAN_MAX_QUEUES		0
+#endif
+#define rdpa_cpu_rx_info_t int
+
+#else
+
+#include "rdpa_cpu.h"
+#include "bdmf_system.h"
+#include "bdmf_shell.h"
+#include "bdmf_dev.h"
+
+#ifdef XRDP
+#include "rdd_cpu_rx.h"
+#define RDPA_PKT_MIN_ALIGN 128
+#ifndef RDP_SIM
+#define DEF_DATA_RING_SIZE  1024
+#else
+#define DEF_DATA_RING_SIZE  128
+#endif
+
+#define RECYCLE_RING_SIZE  (DEF_DATA_RING_SIZE * RDD_CPU_RING_DESCRIPTORS_TABLE_SIZE)
+#define FEED_RING_SIZE     (DEF_DATA_RING_SIZE * RDD_CPU_RING_DESCRIPTORS_TABLE_SIZE)
+#else
+#define RDPA_PKT_MIN_ALIGN 0
+#define RDP_CPU_RING_MAX_QUEUES		RDPA_CPU_MAX_QUEUES
+#define RDP_WLAN_MAX_QUEUES		RDPA_WLAN_MAX_QUEUES
+#endif
+
+/* extern const bdmf_attr_enum_table_t rdpa_cpu_reason_enum_table; */
+#endif
+
+#ifdef RDP_SIM
+#include "rdp_cpu_sim.h"
+#define BCM_PKTBUF_SIZE 2048
+#endif
+
+
+#ifndef XRDP 
+#define CPU_RING_DEBUG
+#endif
+#ifdef CPU_RING_DEBUG
+    #define DO_DEBUG(a_) a_
+#else
+    #define DO_DEBUG(a_) 
+#endif
+
+
+typedef struct
+{
+   uint8_t* data_ptr;
+   uint8_t data_offset;
+   uint16_t packet_size;
+   uint16_t flow_id;
+   uint16_t reason;
+   uint16_t src_bridge_port;
+   uint16_t dst_ssid;
+   uint16_t ptp_index;
+   uint16_t free_index;
+   uint32_t wl_metadata;
+ 
+#ifdef XRDP
+   uint8_t  color;
+   uint8_t  mcast_tx_prio:3;
+#else
+   uint8_t  reserved:3;   
+#endif
+   uint8_t  is_rx_offload:1;
+   uint8_t  is_ipsec_upstream:1;
+   uint8_t  is_ucast:1;
+   uint8_t  is_exception:1;
+   uint8_t  is_csum_verified:1;
+#ifdef CONFIG_CPU_REDIRECT_MODE_SUPPORT
+   uint8_t  cpu_redirect_egress_queue;
+   uint8_t  cpu_redirect_wan_flow;
+#endif
+   uint8_t  omci_enc_key_index;
+}
+CPU_RX_PARAMS;
+
+
+#define MAX_BUFS_IN_CACHE 32
+typedef struct RING_DESCTIPTOR RING_DESCTIPTOR;
+typedef void* (*databuf_alloc_func)(RING_DESCTIPTOR *pDescriptor);
+typedef void (*databuf_free_func)(void *pBuf, uint32_t context, RING_DESCTIPTOR *pDescriptor);
+typedef void (*data_dump_func)(uint32_t rindId, rdpa_cpu_rx_info_t *info);
+typedef void* (*memory_create_func)(RING_DESCTIPTOR *pDescriptor);
+typedef void (*memory_delete_func)(void *buffMem);
+
+struct RING_DESCTIPTOR
+{
+    uint32_t	   ring_id;
+    uint32_t       ring_prio; 
+    uint32_t	   num_of_entries;
+    uint32_t	   num_of_entries_mask;
+    uint32_t	   size_of_entry;
+    uint32_t	   packet_size;
+    rdpa_ring_type_t type;
+    void* base;
+#ifndef XRDP
+    CPU_RX_DESCRIPTOR* head;
+    CPU_RX_DESCRIPTOR* end;
+#endif
+    uint32_t           buff_cache_cnt;
+    uint8_t **buff_cache;
+    void *buff_mem_context;
+    databuf_alloc_func databuf_alloc;
+    databuf_free_func databuf_free;
+    data_dump_func data_dump;
+    memory_create_func memory_create;
+    memory_delete_func memory_delete;
+#ifdef XRDP
+    uint16_t shadow_read_idx;
+    uint16_t shadow_write_idx;
+    uint16_t accum_inc;
+    uint16_t lowest_filling_level;
+    uint16_t *read_idx;
+    uint16_t *write_idx;
+#endif /* XRDP */
+#ifdef CPU_RING_DEBUG
+    uint32_t stats_received; /* for every queue */
+    uint32_t stats_dropped;  /* for every queue */
+    uint32_t stats_buff_err; /* buffer allocation failure */
+    int dump_enable;
+#endif /* CPU_RING_DEBUG */
+};
+
+typedef struct
+{
+#ifndef XRDP
+    databuf_alloc_func databuf_alloc;
+    databuf_free_func databuf_free;
+#endif
+    data_dump_func data_dump;
+    void *buff_mem_context;
+} RING_CB_FUNC;
+
+int rdp_cpu_ring_read_packet_copy(uint32_t ringId, CPU_RX_PARAMS* rxParams);
+
+int rdp_cpu_ring_create_ring(uint32_t ring_id,
+                             uint8_t ring_type,
+                             uint32_t entries,
+                             bdmf_phys_addr_t *ring_head, uint32_t packetSize,
+                             RING_CB_FUNC *cbFunc,
+                             uint32_t prio);
+
+int rdp_cpu_ring_create_ring_ex(uint32_t ring_id,
+                                uint8_t ring_type,
+                                uint32_t entries,
+                                bdmf_phys_addr_t* ring_head,
+                                bdmf_phys_addr_t* rw_idx_addr,
+                                uint32_t packetSize,
+                                RING_CB_FUNC* ringCb,
+                                uint32_t prio);
+
+int rdp_cpu_ring_delete_ring(uint32_t ringId);
+
+int cpu_ring_shell_admin_ring(void *shell_priv, uint32_t ring_id, uint32_t admin_status);
+
+/* Callback Functions */
+
+void rdp_packet_dump(uint32_t ringId, rdpa_cpu_rx_info_t *info);
+
+/* BPM (or CFE)*/
+
+void* rdp_databuf_alloc(RING_DESCTIPTOR *pDescriptor);
+
+void rdp_databuf_free(void *pBuf, uint32_t context, RING_DESCTIPTOR *pDescriptor);
+
+/* Kmem_Cache */
+
+void* rdp_databuf_alloc_cache(RING_DESCTIPTOR *pDescriptor);
+
+void rdp_databuf_free_cache(void *pBuf, uint32_t context, RING_DESCTIPTOR *pDescriptor);
+
+extern bdmf_fastlock feed_ring_lock;
+
+#else /* !defined(RDP_SIM) || defined(XRDP) */
+#include "rdp_cpu_ring_sim.h"
+#define RDP_CPU_RING_MAX_QUEUES        RDPA_CPU_MAX_QUEUES
+#define RDP_WLAN_MAX_QUEUES        RDPA_WLAN_MAX_QUEUES
+#endif /* !defined(RDP_SIM) || defined(XRDP) */
+
+/*array of possible rings private data*/
+#ifndef XRDP
+#define RING_ID_NUM_OF (RDP_CPU_RING_MAX_QUEUES + RDP_WLAN_MAX_QUEUES)
+#endif
+#define D_NUM_OF_RING_DESCRIPTORS RING_ID_NUM_OF
+#endif /* _RDP_CPU_RING_H_ */
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring_defs.h b/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring_defs.h
new file mode 100755
index 0000000000..dc6e75eb13
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring_defs.h
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ *  
+ */
+
+
+#ifndef _RDP_CPU_RING_DEFS_H
+#define _RDP_CPU_RING_DEFS_H
+
+#include "access_macros.h"
+
+typedef enum
+{
+    OWNERSHIP_RUNNER,
+    OWNERSHIP_HOST
+}E_DESCRIPTOR_OWNERSHIP;
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+    union{
+        uint32_t word0;
+        struct{
+            uint32_t    flow_id:12;
+            uint32_t    is_chksum_verified:1;
+            uint32_t    source_port:5;
+            uint32_t    packet_length:14;
+        };
+        struct{
+            uint32_t    reserved7:1;
+            uint32_t    ipsec_error:3;
+            uint32_t    reserved8:2;
+            uint32_t    cpu_rx_queue:4;
+            uint32_t    is_ipsec_upstream:1;
+            uint32_t    reserved9:1;
+            uint32_t    is_checksum_verified:1;
+            uint32_t    src_port:5;
+            uint32_t    pkt_length:14;
+        };
+    };
+    union{
+        uint32_t word1;
+        struct{
+            uint32_t    payload_offset_flag:1;
+            uint32_t    reason:6;
+            uint32_t    dst_ssid:16;
+            uint32_t    reserved1:4;
+            uint32_t    is_exception:1;
+            uint32_t    descriptor_type:4;
+            /* uint32_t  abs_flag:1; */
+            /* uint32_t  flow_id:8; */
+
+        };
+    };
+    union{
+        uint32_t word2;
+        struct{
+            uint32_t    ownership:1;
+            uint32_t    reserved2:2;
+            uint32_t    host_buffer_data_pointer:29;
+        };
+    };
+    union{
+        uint32_t word3;
+        struct{
+            uint16_t    is_rx_offload:1;
+            uint16_t    is_ucast:1;
+            uint16_t    wl_tx_prio:4;
+            uint16_t    reserved4:6;
+            uint16_t    ip_sync_1588_idx:4;
+            union {
+                uint16_t ssid_vector;
+                uint16_t wl_metadata;
+                struct{
+                    uint16_t    wl_tx_priority:2; /* Must be removed with Oren FW change */
+                    uint16_t    wl_chain_id:14;
+                };
+                struct{
+                    uint16_t    reserved6:2;
+                    uint16_t    ssid:4;
+                    uint16_t    flow_ring_idx:10;
+                };
+            };
+        };
+    };
+}
+CPU_RX_DESCRIPTOR;
+#else
+typedef struct
+{
+    union{
+        uint32_t word0;
+        struct{
+            uint32_t    packet_length:14;
+            uint32_t    source_port:5;
+            uint32_t    is_chksum_verified:1;
+            uint32_t    flow_id:12;
+            /* uint32_t  descriptor_type:4; */
+            /* uint32_t  reserved0:9; */
+        };
+        struct{
+            uint32_t    pkt_length:14;
+            uint32_t    src_port:5;
+            uint32_t    is_checksum_verified:1;
+            uint32_t    reserved9:1;
+            uint32_t    is_ipsec_upstream:1;
+            uint32_t    cpu_rx_queue:4;
+            uint32_t    reserved8:2;
+            uint32_t    ipsec_error:3;
+            uint32_t    reserved7:1;
+        };
+    };
+
+    union{
+        uint32_t word1;
+        struct{
+            /* uint32_t  flow_id:8; */
+            /* uint32_t  abs_flag:1; */
+            uint32_t    descriptor_type:4;
+            uint32_t    is_exception:1;
+            uint32_t    reserved1:4;
+            uint32_t    dst_ssid:16;
+            uint32_t    reason:6;
+            uint32_t    payload_offset_flag:1;
+        };
+    };
+
+    union{
+        uint32_t word2;
+        uint32_t data_ptr;
+        struct{
+            uint32_t    host_buffer_data_pointer:31;
+            uint32_t    ownership:1;
+        };
+    };
+    union{
+        uint32_t word3;
+        struct{
+            union {
+                uint16_t free_index;
+                uint16_t wl_metadata;
+                uint16_t ssid_vector;
+                struct {
+                    uint16_t    flow_ring_idx:10;
+                    uint16_t    ssid:4;
+                    uint16_t    reserved6:2;
+                };
+                struct {
+                    uint16_t    wl_chain_id:14;
+                    uint16_t    wl_tx_priority:2;
+                };
+            };
+            uint16_t    ip_sync_1588_idx:4;
+            uint16_t    reserved4:6;
+            uint16_t    wl_tx_prio:4;
+            uint16_t    is_ucast:1;
+            uint16_t    is_rx_offload:1;
+        };
+    };
+}
+CPU_RX_DESCRIPTOR;
+#endif
+
+#endif /*_RDP_CPU_RING_DEFS_H */
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring_inline.h b/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring_inline.h
new file mode 100755
index 0000000000..2eb675b4fa
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_cpu_ring_inline.h
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the implementation of the Runner CPU ring interface     */
+/*                                                                            */
+/******************************************************************************/
+
+#ifndef _RDP_CPU_RING_INLINE_H_
+#define _RDP_CPU_RING_INLINE_H_
+
+#ifndef RDP_SIM
+
+#include "rdp_cpu_ring.h"
+
+#if defined(__KERNEL__) || defined(__UBOOT__)
+
+static inline void AssignPacketBuffertoRing(RING_DESCTIPTOR *pDescriptor, volatile CPU_RX_DESCRIPTOR *pTravel, void *pBuf)
+{
+   /* assign the buffer address to ring and set the ownership to runner
+    * by clearing  bit 31 which is used as ownership flag */
+
+   pTravel->word2 = swap4bytes(((VIRT_TO_PHYS(pBuf)) & 0x7fffffff));
+
+   /* advance the head ptr, wrap around if needed*/
+   if (++pDescriptor->head == pDescriptor->end) 
+      pDescriptor->head = pDescriptor->base;
+}
+
+#if defined(BCM_DSL_RDP)
+static inline int ReadPacketFromRing(RING_DESCTIPTOR *pDescriptor, volatile CPU_RX_DESCRIPTOR *pTravel, CPU_RX_PARAMS *rxParams)
+{
+   /* pTravel is in uncached mem so reading 32bits at a time into
+      cached mem improves performance*/
+   CPU_RX_DESCRIPTOR	    rxDesc;
+
+   rxDesc.word2 = pTravel->word2;
+   //printk("ReadPacketFromRing addr=%p ddr= %x\n",pTravel, rxDesc.word2);
+   rxDesc.word2 = swap4bytes(rxDesc.word2);
+
+   //printk("ReadPacketFromRing swapped bufaddr= %x\n", rxDesc.word2);
+   if ((rxDesc.word2 & 0x80000000))
+   {
+      rxDesc.ownership = 0; /*clear the ownership bit */
+      rxParams->data_ptr = (uint8_t *)PHYS_TO_CACHED(rxDesc.word2);
+
+      rxDesc.word0 = pTravel->word0;
+      rxDesc.word0 = swap4bytes(rxDesc.word0);
+
+      rxParams->packet_size = rxDesc.packet_length;
+      rxParams->src_bridge_port = (BL_LILAC_RDD_BRIDGE_PORT_DTE)rxDesc.source_port;
+      rxParams->flow_id = rxDesc.flow_id;
+
+#if defined(CONFIG_RUNNER_CSO)
+      rxParams->is_csum_verified = rxDesc.is_chksum_verified;
+#endif
+      rxDesc.word1 = pTravel->word1;
+      rxDesc.word1 = swap4bytes(rxDesc.word1);
+
+      rxParams->dst_ssid = rxDesc.dst_ssid;
+
+      rxDesc.word3 = pTravel->word3;
+      rxDesc.word3 = swap4bytes(rxDesc.word3);
+
+      if (rxDesc.is_rx_offload)
+      {
+          rxParams->reason            = rdpa_cpu_rx_reason_ipsec; /* hardcoded, in use by ipsec only */
+          rxParams->free_index        = rxDesc.free_index;
+          rxParams->is_rx_offload     = rxDesc.is_rx_offload;
+          rxParams->is_ipsec_upstream = rxDesc.is_ipsec_upstream;
+      }
+      else
+      {
+          rxParams->reason      = (rdpa_cpu_reason)rxDesc.reason;
+          rxParams->wl_metadata = rxDesc.wl_metadata;
+          rxParams->ptp_index   = pTravel->ip_sync_1588_idx;
+          rxParams->wl_metadata = 0;
+      }
+
+      return 0;
+   }
+
+   return BL_LILAC_RDD_ERROR_CPU_RX_QUEUE_EMPTY;
+}
+
+#else
+static inline int ReadPacketFromRing(RING_DESCTIPTOR *pDescriptor, volatile CPU_RX_DESCRIPTOR *pTravel, CPU_RX_PARAMS *rxParams)
+{
+   /* pTravel is in uncached mem so reading 32bits at a time into
+      cached mem improves performance*/
+   CPU_RX_DESCRIPTOR	    rxDesc;
+
+   rxDesc.word2 = pTravel->word2;
+   if ((rxDesc.ownership == OWNERSHIP_HOST))
+   {
+      rxParams->data_ptr = (uint8_t *)PHYS_TO_CACHED(rxDesc.word2);
+
+      rxDesc.word0 = pTravel->word0;
+      rxParams->packet_size = rxDesc.packet_length;
+      rxParams->src_bridge_port = (BL_LILAC_RDD_BRIDGE_PORT_DTE)rxDesc.source_port;
+      rxParams->flow_id = rxDesc.flow_id;
+
+      rxDesc.word1 = pTravel->word1 ;
+      rxParams->reason = (rdpa_cpu_reason)rxDesc.reason;
+      rxParams->dst_ssid = rxDesc.dst_ssid;
+      rxDesc.word3 = pTravel->word3 ;
+      rxParams->wl_metadata = rxDesc.wl_metadata;
+      rxParams->ptp_index = pTravel->ip_sync_1588_idx;
+
+      return 0;
+   }
+
+   return BL_LILAC_RDD_ERROR_CPU_RX_QUEUE_EMPTY;
+}
+#endif
+
+static inline int rdp_cpu_ring_buffers_free(RING_DESCTIPTOR *pDescriptor)
+{
+    volatile CPU_RX_DESCRIPTOR *pTravel;
+    uint32_t i;
+
+    for (pTravel =(volatile CPU_RX_DESCRIPTOR*)pDescriptor->base, i = 0 ; i < pDescriptor->num_of_entries;
+        pTravel++, i++)
+    {
+        if (pTravel->word2)
+        {
+#ifdef _BYTE_ORDER_LITTLE_ENDIAN_
+            // little-endian ownership is MSb of LSB
+            pTravel->word2 = swap4bytes(pTravel->word2 | 0x80);
+#else
+            // big-endian ownership is MSb of MSB
+            pTravel->ownership = OWNERSHIP_HOST;
+#endif
+            pDescriptor->databuf_free((void *)PHYS_TO_CACHED(pTravel->host_buffer_data_pointer), 0, pDescriptor);
+            pTravel->word2 = 0;
+        }
+    }
+
+    return 0;
+}
+
+static inline int rdp_cpu_ring_buffers_init(RING_DESCTIPTOR *pDescriptor, uint32_t ring_id)
+{
+	volatile CPU_RX_DESCRIPTOR *pTravel;
+	void *dataPtr;
+	uint32_t i;
+
+	for (pTravel =(volatile CPU_RX_DESCRIPTOR*)pDescriptor->base, i = 0; i < pDescriptor->num_of_entries;
+        pTravel++ ,i++)
+	{
+		memset((void*)pTravel,0,sizeof(*pTravel));
+
+        /*allocate actual packet in DDR*/
+
+		dataPtr = pDescriptor->databuf_alloc(pDescriptor);
+
+		if (dataPtr)
+		{
+#ifdef _BYTE_ORDER_LITTLE_ENDIAN_
+			/* since ARM is little-endian and runner is big-endian
+			 * we need to byte-swap dataPtr and clear ownership
+			 */
+			pTravel->word2 = swap4bytes(VIRT_TO_PHYS(dataPtr)) & ~0x80;
+#else
+			pTravel->host_buffer_data_pointer = VIRT_TO_PHYS(dataPtr);
+			pTravel->ownership = OWNERSHIP_RUNNER;
+#endif        
+		}
+		else
+		{
+			pTravel->host_buffer_data_pointer = 0; /* NULL */
+			printk("failed to allocate packet map entry=%d\n", i);
+			rdp_cpu_ring_delete_ring(ring_id);
+			return -1;
+		}
+	}
+    return 0;
+}
+
+#endif /* defined(__KERNEL__) || defined(__UBOOT__) */
+#endif /* RDP_SIM */
+
+static inline int rdp_cpu_ring_is_ownership_host(volatile CPU_RX_DESCRIPTOR *pTravel)
+{
+#ifdef _BYTE_ORDER_LITTLE_ENDIAN_
+	return pTravel->word2 & 0x80;
+#else
+	return pTravel->ownership == OWNERSHIP_HOST;
+#endif    
+}
+
+static inline void rdp_cpu_ring_set_ownership_runner(volatile CPU_RX_DESCRIPTOR *pTravel)
+{
+#ifdef _BYTE_ORDER_LITTLE_ENDIAN_
+    pTravel->word2 &= ~0x80;
+#else
+    pTravel->ownership = OWNERSHIP_RUNNER;
+#endif    
+}
+
+#endif /* _RDP_CPU_RING_INLINE_H_ */
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_dma.h b/arch/arm/mach-bcmbca/rdp/rdp_dma.h
new file mode 100755
index 0000000000..a5bf5a9b36
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_dma.h
@@ -0,0 +1,1862 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/             
+
+#ifndef __DMA_H_INCLUDED
+#define __DMA_H_INCLUDED
+
+/*  File automatically generated by Reggae at 15/08/2013  10:54:36   */
+
+#include "access_macros.h"
+#include "packing.h"
+#include "rdp_map.h"
+
+/*****************************************************************************************/
+/* The Direct Memory Access (DMA) module serves peripheral (EMACs and GPON) requests for */
+/*  writes and reads from DDR and packet SRAM.    DMA connects the peripherals to DDR. S */
+/* DMA connects the same peripherals to packet SRAM.                                     */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Blocks offsets                                                                        */
+/*****************************************************************************************/
+/*****************************************************************************************/
+/* Functions offsets and addresses                                                       */
+/*****************************************************************************************/
+#define DMA_REGS_0_CONFIG_OFFSET 	( 0x00000000 )
+#define DMA_REGS_0_CONFIG_ADDRESS	( DMA_REGS_0_OFFSET + DMA_REGS_0_CONFIG_OFFSET )
+
+#define DMA_REGS_0_DEBUG_OFFSET 	( 0x00000100 )
+#define DMA_REGS_0_DEBUG_ADDRESS	( DMA_REGS_0_OFFSET + DMA_REGS_0_DEBUG_OFFSET )
+
+#define DMA_REGS_1_CONFIG_OFFSET 	( 0x00000000 )
+#define DMA_REGS_1_CONFIG_ADDRESS	( DMA_REGS_1_OFFSET + DMA_REGS_1_CONFIG_OFFSET )
+
+#define DMA_REGS_1_DEBUG_OFFSET 	( 0x00000100 )
+#define DMA_REGS_1_DEBUG_ADDRESS	( DMA_REGS_1_OFFSET + DMA_REGS_1_DEBUG_OFFSET )
+
+/*   'd' is module index   */
+/*   'i' is block index    */
+/*   'j' is function index */
+/*   'e' is function entry */
+/*   'k' is register index */
+
+/*****************************************************************************************/
+/* BB_SOURCE                                                                             */
+/* Broadbus source address of DMA and SDMA                                               */
+/*****************************************************************************************/
+
+#define DMA_REGS_CONFIG_SOURCE_R1_DEFAULT_VALUE                      ( 0x0 )
+#define DMA_REGS_CONFIG_SOURCE_R1_DEFAULT_VALUE_RESET_VALUE          ( 0x0 )
+#define DMA_REGS_CONFIG_SOURCE_SOURCE_DEFAULT_DMA_VALUE              ( 0x16 )
+#define DMA_REGS_CONFIG_SOURCE_SOURCE_DEFAULT_DMA_VALUE_RESET_VALUE  ( 0x16 )
+#define DMA_REGS_CONFIG_SOURCE_SOURCE_DEFAULT_SDMA_VALUE             ( 0x18 )
+#define DMA_REGS_CONFIG_SOURCE_SOURCE_DEFAULT_SDMA_VALUE_RESET_VALUE ( 0x18 )
+
+
+#define DMA_REGS_CONFIG_SOURCE_OFFSET ( 0x00000000 )
+
+#define DMA_REGS_0_CONFIG_SOURCE_ADDRESS   	( DMA_REGS_0_CONFIG_ADDRESS + DMA_REGS_CONFIG_SOURCE_OFFSET )
+#define DMA_REGS_0_CONFIG_SOURCE_READ( r ) 	READ_32( ( DMA_REGS_0_CONFIG_SOURCE_ADDRESS ), (r) )
+#define DMA_REGS_0_CONFIG_SOURCE_WRITE( v )	WRITE_32( ( DMA_REGS_0_CONFIG_SOURCE_ADDRESS ), (v) )
+
+#define DMA_REGS_1_CONFIG_SOURCE_ADDRESS   	( DMA_REGS_1_CONFIG_ADDRESS + DMA_REGS_CONFIG_SOURCE_OFFSET )
+#define DMA_REGS_1_CONFIG_SOURCE_READ( r ) 	READ_32( ( DMA_REGS_1_CONFIG_SOURCE_ADDRESS ), (r) )
+#define DMA_REGS_1_CONFIG_SOURCE_WRITE( v )	WRITE_32( ( DMA_REGS_1_CONFIG_SOURCE_ADDRESS ), (v) )
+
+
+extern uint32_t DMA_REGS_CONFIG_SOURCE_ARRAY [ ] ;
+
+#define DMA_REGS_CONFIG_SOURCE_WRITE( i, v )	WRITE_32( DMA_REGS_CONFIG_SOURCE_ARRAY [ i ], (v) )
+#define DMA_REGS_CONFIG_SOURCE_READ( i, r ) 	READ_32( DMA_REGS_CONFIG_SOURCE_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1    	: 27 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bb_source */
+	uint32_t source	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_SOURCE ;
+#else
+typedef struct
+{	uint32_t source	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bb_source */
+	uint32_t r1    	: 27 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_SOURCE ;
+#endif
+
+/*****************************************************************************************/
+/* MEMORY_ALLOCATION                                                                     */
+/* This array of registers defines the memory allocation for the peripherals, for upstre */
+/* am.  The allocation is of number of 128byte buffers out of the total 32 buffers for s */
+/* dma or 96 buffers in dma  in the upload data RAM.  For the DMA, the buffers are divid */
+/* ed between 2 physical RAMs 964 in the first, 32 in the second). The decision which cl */
+/* ients FIFO is located in which memory is done by the register in address 0x98.  The a */
+/* llocation is done by defining a base address (aligned to 128 bytes) and the number of */
+/*  allocated buffers.  Note that the memory allocation should not contain wrap around.  */
+/* For example, if three buffers are needed, do not allocate buffers 30, 31 and 0.   The */
+/*  number of allocated CDs is the same of data buffers - one chunk descriptor per buffe */
+/* r, therefore allocation in CD RAM is defined only by offset address.    The order of  */
+/* peripherals within the array is:  Ethernet 0  Ethernet 1  Ethernet 2  Ethernet 3  Eth */
+/* ernet 4  GPON/EPON                                                                    */
+/*****************************************************************************************/
+
+#define DMA_REGS_CONFIG_MALLOC_R3_R3_VALUE                                      ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_R3_R3_VALUE_RESET_VALUE                          ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_EMAC0_VALUE                 ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_EMAC0_VALUE_RESET_VALUE     ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_EMAC0_VALUE                ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_EMAC0_VALUE_RESET_VALUE    ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_EMAC1_VALUE                ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_EMAC1_VALUE_RESET_VALUE    ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_EMAC1_VALUE                 ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_EMAC1_VALUE_RESET_VALUE     ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_EMAC2_VALUE                ( 0xA )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_EMAC2_VALUE_RESET_VALUE    ( 0xA )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_EMAC3_VALUE                ( 0xF )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_EMAC3_VALUE_RESET_VALUE    ( 0xF )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_EMAC2_VALUE                 ( 0x12 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_EMAC2_VALUE_RESET_VALUE     ( 0x12 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_EMAC4_VALUE                ( 0x14 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_EMAC4_VALUE_RESET_VALUE    ( 0x14 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_GPON_VALUE                 ( 0x19 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_SDMA_GPON_VALUE_RESET_VALUE     ( 0x19 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_EMAC3_VALUE                 ( 0x1B )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_EMAC3_VALUE_RESET_VALUE     ( 0x1B )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_EMAC4_VALUE                 ( 0x24 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_EMAC4_VALUE_RESET_VALUE     ( 0x24 )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_GPON_VALUE                  ( 0x2D )
+#define DMA_REGS_CONFIG_MALLOC_CDOFFSET_DEFAULT_DMA_GPON_VALUE_RESET_VALUE      ( 0x2D )
+#define DMA_REGS_CONFIG_MALLOC_R2_R2_VALUE                                      ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_R2_R2_VALUE_RESET_VALUE                          ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_MIN_DMA_SDMA_VALUE                     ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_EMAC0_VALUE               ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_EMAC0_VALUE_RESET_VALUE   ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_EMAC1_VALUE               ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_EMAC1_VALUE_RESET_VALUE   ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_EMAC2_VALUE               ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_EMAC2_VALUE_RESET_VALUE   ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_EMAC3_VALUE               ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_EMAC3_VALUE_RESET_VALUE   ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_EMAC4_VALUE               ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_EMAC4_VALUE_RESET_VALUE   ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_GPON_VALUE                ( 0x7 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_SDMA_GPON_VALUE_RESET_VALUE    ( 0x7 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_EMAC0_VALUE                ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_EMAC0_VALUE_RESET_VALUE    ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_EMAC1_VALUE                ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_EMAC1_VALUE_RESET_VALUE    ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_EMAC2_VALUE                ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_EMAC2_VALUE_RESET_VALUE    ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_EMAC3_VALUE                ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_EMAC3_VALUE_RESET_VALUE    ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_EMAC4_VALUE                ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_EMAC4_VALUE_RESET_VALUE    ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_GPON_VALUE                 ( 0x12 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_DEFAULT_DMA_GPON_VALUE_RESET_VALUE     ( 0x12 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_MAX_SDMA_VALUE                         ( 0x20 )
+#define DMA_REGS_CONFIG_MALLOC_NUMOFBUFF_MAX_DMA_VALUE                          ( 0x3F )
+#define DMA_REGS_CONFIG_MALLOC_R1_R1_VALUE                                      ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_R1_R1_VALUE_RESET_VALUE                          ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_EMAC0_VALUE              ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_EMAC0_VALUE_RESET_VALUE  ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_EMAC0_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_EMAC0_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_EMAC1_VALUE             ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_EMAC1_VALUE_RESET_VALUE ( 0x5 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_EMAC1_VALUE              ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_EMAC1_VALUE_RESET_VALUE  ( 0x9 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_EMAC2_VALUE             ( 0xA )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_EMAC2_VALUE_RESET_VALUE ( 0xA )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_EMAC3_VALUE             ( 0xF )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_EMAC3_VALUE_RESET_VALUE ( 0xF )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_EMAC2_VALUE              ( 0x12 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_EMAC2_VALUE_RESET_VALUE  ( 0x12 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_EMAC4_VALUE             ( 0x14 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_EMAC4_VALUE_RESET_VALUE ( 0x14 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_GPON_VALUE              ( 0x19 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_SDMA_GPON_VALUE_RESET_VALUE  ( 0x19 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_EMAC3_VALUE              ( 0x1B )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_EMAC3_VALUE_RESET_VALUE  ( 0x1B )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_EMAC4_VALUE              ( 0x24 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_EMAC4_VALUE_RESET_VALUE  ( 0x24 )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_GPON_VALUE               ( 0x2D )
+#define DMA_REGS_CONFIG_MALLOC_DATATOFFSET_DEFAULT_DMA_GPON_VALUE_RESET_VALUE   ( 0x2D )
+
+
+#define DMA_REGS_CONFIG_MALLOC_OFFSET ( 0x00000004 )
+
+#define DMA_REGS_0_CONFIG_MALLOC_ADDRESS        	( DMA_REGS_0_CONFIG_ADDRESS + DMA_REGS_CONFIG_MALLOC_OFFSET )
+#define DMA_REGS_0_CONFIG_MALLOC_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_0_CONFIG_MALLOC_ADDRESS ), (i), (r) )
+#define DMA_REGS_0_CONFIG_MALLOC_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_0_CONFIG_MALLOC_ADDRESS ), (i), (v) )
+
+#define DMA_REGS_1_CONFIG_MALLOC_ADDRESS        	( DMA_REGS_1_CONFIG_ADDRESS + DMA_REGS_CONFIG_MALLOC_OFFSET )
+#define DMA_REGS_1_CONFIG_MALLOC_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_1_CONFIG_MALLOC_ADDRESS ), (i), (r) )
+#define DMA_REGS_1_CONFIG_MALLOC_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_1_CONFIG_MALLOC_ADDRESS ), (i), (v) )
+
+
+extern uint32_t DMA_REGS_CONFIG_MALLOC_ARRAY [ ] ;
+
+#define DMA_REGS_CONFIG_MALLOC_WRITE( i, k, v )	WRITE_I_32( DMA_REGS_CONFIG_MALLOC_ARRAY [ i ], (k), (v) )
+#define DMA_REGS_CONFIG_MALLOC_READ( i, k, r ) 	READ_I_32( DMA_REGS_CONFIG_MALLOC_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved3 */
+	uint32_t r3         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CD_memory_offset_address */
+	uint32_t cdoffset   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved2 */
+	uint32_t r2         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* number_of_buffers */
+	uint32_t numofbuff  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved1 */
+	uint32_t r1         	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data_memory_offset_address */
+	uint32_t datatoffset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_MALLOC ;
+#else
+typedef struct
+{	uint32_t datatoffset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data_memory_offset_address */
+	uint32_t r1         	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved1 */
+	uint32_t numofbuff  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* number_of_buffers */
+	uint32_t r2         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved2 */
+	uint32_t cdoffset   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CD_memory_offset_address */
+	uint32_t r3         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved3 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_MALLOC ;
+#endif
+
+/*****************************************************************************************/
+/* READ_REQ_BASE_ADDRESS                                                                 */
+/* This array of registers controls the base address of each peripheral within the read  */
+/* requests RAM.   Each peripheral gets memory enough for storing up to 8 read requests  */
+/* (total of 48 requests in the RAM), starting from a configurable base address.  The ba */
+/* se address is aligned to 8 therefore the only  valid values are:  0, 8, 16, 24, 32, 4 */
+/* 0.                                                                                    */
+/*****************************************************************************************/
+
+#define DMA_REGS_CONFIG_READ_BASE_R1_R1_VALUE                          ( 0x0 )
+#define DMA_REGS_CONFIG_READ_BASE_R1_R1_VALUE_RESET_VALUE              ( 0x0 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_MIN_VALUE                       ( 0x0 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_EMAC0_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_EMAC0_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_EMAC1_VALUE             ( 0x8 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_EMAC1_VALUE_RESET_VALUE ( 0x8 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_EMAC2_VALUE             ( 0x10 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_EMAC2_VALUE_RESET_VALUE ( 0x10 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_EMAC3_VALUE             ( 0x18 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_EMAC3_VALUE_RESET_VALUE ( 0x18 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_EMAC4_VALUE             ( 0x20 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_EMAC4_VALUE_RESET_VALUE ( 0x20 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_GPON_VALUE              ( 0x28 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_DEFAULT_GPON_VALUE_RESET_VALUE  ( 0x28 )
+#define DMA_REGS_CONFIG_READ_BASE_BASE_MAX_VALUE                       ( 0x28 )
+
+
+#define DMA_REGS_CONFIG_READ_BASE_OFFSET ( 0x0000001C )
+
+#define DMA_REGS_0_CONFIG_READ_BASE_ADDRESS        	( DMA_REGS_0_CONFIG_ADDRESS + DMA_REGS_CONFIG_READ_BASE_OFFSET )
+#define DMA_REGS_0_CONFIG_READ_BASE_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_0_CONFIG_READ_BASE_ADDRESS ), (i), (r) )
+#define DMA_REGS_0_CONFIG_READ_BASE_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_0_CONFIG_READ_BASE_ADDRESS ), (i), (v) )
+
+#define DMA_REGS_1_CONFIG_READ_BASE_ADDRESS        	( DMA_REGS_1_CONFIG_ADDRESS + DMA_REGS_CONFIG_READ_BASE_OFFSET )
+#define DMA_REGS_1_CONFIG_READ_BASE_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_1_CONFIG_READ_BASE_ADDRESS ), (i), (r) )
+#define DMA_REGS_1_CONFIG_READ_BASE_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_1_CONFIG_READ_BASE_ADDRESS ), (i), (v) )
+
+
+extern uint32_t DMA_REGS_CONFIG_READ_BASE_ARRAY [ ] ;
+
+#define DMA_REGS_CONFIG_READ_BASE_WRITE( i, k, v )	WRITE_I_32( DMA_REGS_CONFIG_READ_BASE_ARRAY [ i ], (k), (v) )
+#define DMA_REGS_CONFIG_READ_BASE_READ( i, k, r ) 	READ_I_32( DMA_REGS_CONFIG_READ_BASE_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved1 */
+	uint32_t r1  	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* base_address */
+	uint32_t base	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_READ_BASE ;
+#else
+typedef struct
+{	uint32_t base	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* base_address */
+	uint32_t r1  	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved1 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_READ_BASE ;
+#endif
+
+/*****************************************************************************************/
+/* URGENT_THRESHOLDS                                                                     */
+/* the in/out of urgent thresholds mark the number of write requests in the queue in whi */
+/* ch the peripherals priority is changed. The two thresholds should create hysteresis.  */
+/*  The moving into urgent threshold must always be greater than the moving out of urgen */
+/* t threshold.                                                                          */
+/*****************************************************************************************/
+
+#define DMA_REGS_CONFIG_U_THRESH_R2_R2_VALUE                                   ( 0x0 )
+#define DMA_REGS_CONFIG_U_THRESH_R2_R2_VALUE_RESET_VALUE                       ( 0x0 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_MIN_VALUE                            ( 0x0 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_EMAC0_VALUE             ( 0x2 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_EMAC0_VALUE_RESET_VALUE ( 0x2 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_EMAC1_VALUE             ( 0x2 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_EMAC1_VALUE_RESET_VALUE ( 0x2 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_EMAC2_VALUE             ( 0x2 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_EMAC2_VALUE_RESET_VALUE ( 0x2 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_EMAC3_VALUE             ( 0x2 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_EMAC3_VALUE_RESET_VALUE ( 0x2 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_EMAC4_VALUE             ( 0x2 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_EMAC4_VALUE_RESET_VALUE ( 0x2 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_GPON_VALUE              ( 0x4 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_SDMA_GPON_VALUE_RESET_VALUE  ( 0x4 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_EMAC0_VALUE              ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_EMAC0_VALUE_RESET_VALUE  ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_EMAC1_VALUE              ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_EMAC1_VALUE_RESET_VALUE  ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_EMAC2_VALUE              ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_EMAC2_VALUE_RESET_VALUE  ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_EMAC3_VALUE              ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_EMAC3_VALUE_RESET_VALUE  ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_EMAC4_VALUE              ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_EMAC4_VALUE_RESET_VALUE  ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_GPON_VALUE               ( 0xC )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_DEFAULT_DMA_GPON_VALUE_RESET_VALUE   ( 0xC )
+#define DMA_REGS_CONFIG_U_THRESH_OUT_OF_U_MAX_VALUE                            ( 0x1F )
+#define DMA_REGS_CONFIG_U_THRESH_R1_R1_VALUE                                   ( 0x0 )
+#define DMA_REGS_CONFIG_U_THRESH_R1_R1_VALUE_RESET_VALUE                       ( 0x0 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_MIN_VALUE                              ( 0x0 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_EMAC0_VALUE               ( 0x3 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_EMAC0_VALUE_RESET_VALUE   ( 0x3 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_EMAC1_VALUE               ( 0x3 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_EMAC1_VALUE_RESET_VALUE   ( 0x3 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_EMAC2_VALUE               ( 0x3 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_EMAC2_VALUE_RESET_VALUE   ( 0x3 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_EMAC3_VALUE               ( 0x3 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_EMAC3_VALUE_RESET_VALUE   ( 0x3 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_EMAC4_VALUE               ( 0x3 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_EMAC4_VALUE_RESET_VALUE   ( 0x3 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_GPON_VALUE                ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_SDMA_GPON_VALUE_RESET_VALUE    ( 0x5 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_EMAC0_VALUE                ( 0x7 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_EMAC0_VALUE_RESET_VALUE    ( 0x7 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_EMAC1_VALUE                ( 0x7 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_EMAC1_VALUE_RESET_VALUE    ( 0x7 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_EMAC2_VALUE                ( 0x7 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_EMAC2_VALUE_RESET_VALUE    ( 0x7 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_EMAC3_VALUE                ( 0x7 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_EMAC3_VALUE_RESET_VALUE    ( 0x7 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_EMAC4_VALUE                ( 0x7 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_EMAC4_VALUE_RESET_VALUE    ( 0x7 )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_GPON_VALUE                 ( 0xE )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_DEFAULT_DMA_GPON_VALUE_RESET_VALUE     ( 0xE )
+#define DMA_REGS_CONFIG_U_THRESH_INTO_U_MAX_VALUE                              ( 0x1F )
+
+
+#define DMA_REGS_CONFIG_U_THRESH_OFFSET ( 0x00000034 )
+
+#define DMA_REGS_0_CONFIG_U_THRESH_ADDRESS        	( DMA_REGS_0_CONFIG_ADDRESS + DMA_REGS_CONFIG_U_THRESH_OFFSET )
+#define DMA_REGS_0_CONFIG_U_THRESH_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_0_CONFIG_U_THRESH_ADDRESS ), (i), (r) )
+#define DMA_REGS_0_CONFIG_U_THRESH_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_0_CONFIG_U_THRESH_ADDRESS ), (i), (v) )
+
+#define DMA_REGS_1_CONFIG_U_THRESH_ADDRESS        	( DMA_REGS_1_CONFIG_ADDRESS + DMA_REGS_CONFIG_U_THRESH_OFFSET )
+#define DMA_REGS_1_CONFIG_U_THRESH_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_1_CONFIG_U_THRESH_ADDRESS ), (i), (r) )
+#define DMA_REGS_1_CONFIG_U_THRESH_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_1_CONFIG_U_THRESH_ADDRESS ), (i), (v) )
+
+
+extern uint32_t DMA_REGS_CONFIG_U_THRESH_ARRAY [ ] ;
+
+#define DMA_REGS_CONFIG_U_THRESH_WRITE( i, k, v )	WRITE_I_32( DMA_REGS_CONFIG_U_THRESH_ARRAY [ i ], (k), (v) )
+#define DMA_REGS_CONFIG_U_THRESH_READ( i, k, r ) 	READ_I_32( DMA_REGS_CONFIG_U_THRESH_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved2 */
+	uint32_t r2      	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* out_of_urgent_threshold */
+	uint32_t out_of_u	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved1 */
+	uint32_t r1      	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* into_urgent_threshold */
+	uint32_t into_u  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_U_THRESH ;
+#else
+typedef struct
+{	uint32_t into_u  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* into_urgent_threshold */
+	uint32_t r1      	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved1 */
+	uint32_t out_of_u	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* out_of_urgent_threshold */
+	uint32_t r2      	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved2 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_U_THRESH ;
+#endif
+
+/*****************************************************************************************/
+/* STRICT_PRIORITY                                                                       */
+/* The arbitration between the requests of the different peripherals is done in two stag */
+/* es:  1. Strict priority - chooses the peripherals with the highest priority among all */
+/*  perpherals who have a request pending.  2. Weighted Round-Robin between all peripher */
+/* als with the same priority.    This array of registers allow configuration of the pri */
+/* ority of each peripheral (both rx and tx) in the following manner:  There are 8 level */
+/* s of priorities, when each bit in the register represents a different level of priori */
+/* ty. One should assert the relevant bit according to the desired priority -   For the  */
+/* lowest  - 00000001  For the highest - 10000000                                        */
+/*****************************************************************************************/
+
+#define DMA_REGS_CONFIG_PRI_R1_R2_VALUE                        ( 0x0 )
+#define DMA_REGS_CONFIG_PRI_R1_R2_VALUE_RESET_VALUE            ( 0x0 )
+#define DMA_REGS_CONFIG_PRI_TXPRI_LOW_VALUE                    ( 0x1 )
+#define DMA_REGS_CONFIG_PRI_TXPRI_DEFAULT_TX_VALUE             ( 0x80 )
+#define DMA_REGS_CONFIG_PRI_TXPRI_DEFAULT_TX_VALUE_RESET_VALUE ( 0x80 )
+#define DMA_REGS_CONFIG_PRI_TXPRI_HIGH_VALUE                   ( 0x80 )
+#define DMA_REGS_CONFIG_PRI_RXPRI_LOW_VALUE                    ( 0x1 )
+#define DMA_REGS_CONFIG_PRI_RXPRI_DEFAULT_RX_VALUE             ( 0x80 )
+#define DMA_REGS_CONFIG_PRI_RXPRI_DEFAULT_RX_VALUE_RESET_VALUE ( 0x80 )
+#define DMA_REGS_CONFIG_PRI_RXPRI_HIGH_VALUE                   ( 0x80 )
+
+
+#define DMA_REGS_CONFIG_PRI_OFFSET ( 0x0000004C )
+
+#define DMA_REGS_0_CONFIG_PRI_ADDRESS        	( DMA_REGS_0_CONFIG_ADDRESS + DMA_REGS_CONFIG_PRI_OFFSET )
+#define DMA_REGS_0_CONFIG_PRI_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_0_CONFIG_PRI_ADDRESS ), (i), (r) )
+#define DMA_REGS_0_CONFIG_PRI_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_0_CONFIG_PRI_ADDRESS ), (i), (v) )
+
+#define DMA_REGS_1_CONFIG_PRI_ADDRESS        	( DMA_REGS_1_CONFIG_ADDRESS + DMA_REGS_CONFIG_PRI_OFFSET )
+#define DMA_REGS_1_CONFIG_PRI_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_1_CONFIG_PRI_ADDRESS ), (i), (r) )
+#define DMA_REGS_1_CONFIG_PRI_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_1_CONFIG_PRI_ADDRESS ), (i), (v) )
+
+
+extern uint32_t DMA_REGS_CONFIG_PRI_ARRAY [ ] ;
+
+#define DMA_REGS_CONFIG_PRI_WRITE( i, k, v )	WRITE_I_32( DMA_REGS_CONFIG_PRI_ARRAY [ i ], (k), (v) )
+#define DMA_REGS_CONFIG_PRI_READ( i, k, r ) 	READ_I_32( DMA_REGS_CONFIG_PRI_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved2 */
+	uint32_t r1   	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* priority_of_tx_side */
+	uint32_t txpri	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* priority_of_rx_side */
+	uint32_t rxpri	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_PRI ;
+#else
+typedef struct
+{	uint32_t rxpri	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* priority_of_rx_side */
+	uint32_t txpri	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* priority_of_tx_side */
+	uint32_t r1   	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved2 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_PRI ;
+#endif
+
+/*****************************************************************************************/
+/* WEIGHT_OF_ROUND_ROBIN                                                                 */
+/* The second phase of the arbitration between requests is weighted round robin between  */
+/* requests of peripherals with the same priority.  This array of registers allow config */
+/* urtion of the weight of each peripheral (rx and tx). The actual weight will be weight */
+/*  + 1, meaning configuration of 0 is actual weight of 1.                               */
+/*****************************************************************************************/
+
+#define DMA_REGS_CONFIG_WEIGHT_R2_DEFAULT_VALUE                              ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_R2_DEFAULT_VALUE_RESET_VALUE                  ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_TXWEIGHT_MIN_VALUE                            ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_TXWEIGHT_MIN_VALUE_RESET_VALUE                ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_TXWEIGHT_DEFAULT_SDMA_VALUE                   ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_TXWEIGHT_DEFAULT_SDMA_VALUE_RESET_VALUE       ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_TXWEIGHT_DEFAULT_EMAC_DMA_VALUE               ( 0x1 )
+#define DMA_REGS_CONFIG_WEIGHT_TXWEIGHT_DEFAULT_EMAC_DMA_VALUE_RESET_VALUE   ( 0x1 )
+#define DMA_REGS_CONFIG_WEIGHT_TXWEIGHT_DEFAULT_GPON_DMA_VALUE               ( 0x3 )
+#define DMA_REGS_CONFIG_WEIGHT_TXWEIGHT_DEFAULT_GPON_DMA_VALUE_RESET_VALUE   ( 0x3 )
+#define DMA_REGS_CONFIG_WEIGHT_TXWEIGHT_MAX_VALUE                            ( 0x7 )
+#define DMA_REGS_CONFIG_WEIGHT_R1_DEFAULT_VALUE                              ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_R1_DEFAULT_VALUE_RESET_VALUE                  ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_RXWEIGHT_DEFAULT_EMACS_DMA_VALUE              ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_RXWEIGHT_DEFAULT_EMACS_DMA_VALUE_RESET_VALUE  ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_RXWEIGHT_MIN_VALUE                            ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_RXWEIGHT_MIN_VALUE_RESET_VALUE                ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_RXWEIGHT_DEFAULT_EMACS_SDMA_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_RXWEIGHT_DEFAULT_EMACS_SDMA_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_WEIGHT_RXWEIGHT_DEFAULT_GPON_DMA_VALUE               ( 0x1 )
+#define DMA_REGS_CONFIG_WEIGHT_RXWEIGHT_DEFAULT_GPON_DMA_VALUE_RESET_VALUE   ( 0x1 )
+#define DMA_REGS_CONFIG_WEIGHT_RXWEIGHT_DEFAULT_GPON_SDMA_VALUE              ( 0x1 )
+#define DMA_REGS_CONFIG_WEIGHT_RXWEIGHT_DEFAULT_GPON_SDMA_VALUE_RESET_VALUE  ( 0x1 )
+#define DMA_REGS_CONFIG_WEIGHT_RXWEIGHT_MAX_VALUE                            ( 0x7 )
+
+
+#define DMA_REGS_CONFIG_WEIGHT_OFFSET ( 0x00000064 )
+
+#define DMA_REGS_0_CONFIG_WEIGHT_ADDRESS        	( DMA_REGS_0_CONFIG_ADDRESS + DMA_REGS_CONFIG_WEIGHT_OFFSET )
+#define DMA_REGS_0_CONFIG_WEIGHT_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_0_CONFIG_WEIGHT_ADDRESS ), (i), (r) )
+#define DMA_REGS_0_CONFIG_WEIGHT_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_0_CONFIG_WEIGHT_ADDRESS ), (i), (v) )
+
+#define DMA_REGS_1_CONFIG_WEIGHT_ADDRESS        	( DMA_REGS_1_CONFIG_ADDRESS + DMA_REGS_CONFIG_WEIGHT_OFFSET )
+#define DMA_REGS_1_CONFIG_WEIGHT_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_1_CONFIG_WEIGHT_ADDRESS ), (i), (r) )
+#define DMA_REGS_1_CONFIG_WEIGHT_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_1_CONFIG_WEIGHT_ADDRESS ), (i), (v) )
+
+
+extern uint32_t DMA_REGS_CONFIG_WEIGHT_ARRAY [ ] ;
+
+#define DMA_REGS_CONFIG_WEIGHT_WRITE( i, k, v )	WRITE_I_32( DMA_REGS_CONFIG_WEIGHT_ARRAY [ i ], (k), (v) )
+#define DMA_REGS_CONFIG_WEIGHT_READ( i, k, r ) 	READ_I_32( DMA_REGS_CONFIG_WEIGHT_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r2      	: 21 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* weight_of_tx_side */
+	uint32_t txweight	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1      	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* weight_of_rx_side */
+	uint32_t rxweight	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_WEIGHT ;
+#else
+typedef struct
+{	uint32_t rxweight	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* weight_of_rx_side */
+	uint32_t r1      	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t txweight	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* weight_of_tx_side */
+	uint32_t r2      	: 21 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_WEIGHT ;
+#endif
+
+/*****************************************************************************************/
+/* BB_ROUTE_DMA_PERIPH                                                                   */
+/* Broadbus route address from the DMA to the peripherals. Register per peripheral (rx a */
+/* nd tx). The route address is same for DMA and SDMA because of the symmetry of the BB  */
+/* tree.                                                                                 */
+/*****************************************************************************************/
+
+#define DMA_REGS_CONFIG_BB_ROUTE_R2_R2_VALUE                             ( 0x0 )
+#define DMA_REGS_CONFIG_BB_ROUTE_R2_R2_VALUE_RESET_VALUE                 ( 0x0 )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_GPON_VALUE              ( 0x11 )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_GPON_VALUE_RESET_VALUE  ( 0x11 )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_EMAC3_VALUE             ( 0x12 )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_EMAC3_VALUE_RESET_VALUE ( 0x12 )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_EMAC1_VALUE             ( 0x16 )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_EMAC1_VALUE_RESET_VALUE ( 0x16 )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_EMAC4_VALUE             ( 0x19 )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_EMAC4_VALUE_RESET_VALUE ( 0x19 )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_EMAC2_VALUE             ( 0x1A )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_EMAC2_VALUE_RESET_VALUE ( 0x1A )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_EMAC0_VALUE             ( 0x1E )
+#define DMA_REGS_CONFIG_BB_ROUTE_TXROUTE_DEFAULT_EMAC0_VALUE_RESET_VALUE ( 0x1E )
+#define DMA_REGS_CONFIG_BB_ROUTE_R1_R1_VALUE                             ( 0x0 )
+#define DMA_REGS_CONFIG_BB_ROUTE_R1_R1_VALUE_RESET_VALUE                 ( 0x0 )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_GPON_VALUE              ( 0x1 )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_GPON_VALUE_RESET_VALUE  ( 0x1 )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_EMAC3_VALUE             ( 0x2 )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_EMAC3_VALUE_RESET_VALUE ( 0x2 )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_EMAC1_VALUE             ( 0x6 )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_EMAC1_VALUE_RESET_VALUE ( 0x6 )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_EMAC4_VALUE             ( 0x9 )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_EMAC4_VALUE_RESET_VALUE ( 0x9 )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_EMAC2_VALUE             ( 0xA )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_EMAC2_VALUE_RESET_VALUE ( 0xA )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_EMAC0_VALUE             ( 0xE )
+#define DMA_REGS_CONFIG_BB_ROUTE_RXROUTE_DEFAULT_EMAC0_VALUE_RESET_VALUE ( 0xE )
+
+
+#define DMA_REGS_CONFIG_BB_ROUTE_OFFSET ( 0x0000007C )
+
+#define DMA_REGS_0_CONFIG_BB_ROUTE_ADDRESS        	( DMA_REGS_0_CONFIG_ADDRESS + DMA_REGS_CONFIG_BB_ROUTE_OFFSET )
+#define DMA_REGS_0_CONFIG_BB_ROUTE_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_0_CONFIG_BB_ROUTE_ADDRESS ), (i), (r) )
+#define DMA_REGS_0_CONFIG_BB_ROUTE_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_0_CONFIG_BB_ROUTE_ADDRESS ), (i), (v) )
+
+#define DMA_REGS_1_CONFIG_BB_ROUTE_ADDRESS        	( DMA_REGS_1_CONFIG_ADDRESS + DMA_REGS_CONFIG_BB_ROUTE_OFFSET )
+#define DMA_REGS_1_CONFIG_BB_ROUTE_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_1_CONFIG_BB_ROUTE_ADDRESS ), (i), (r) )
+#define DMA_REGS_1_CONFIG_BB_ROUTE_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_1_CONFIG_BB_ROUTE_ADDRESS ), (i), (v) )
+
+
+extern uint32_t DMA_REGS_CONFIG_BB_ROUTE_ARRAY [ ] ;
+
+#define DMA_REGS_CONFIG_BB_ROUTE_WRITE( i, k, v )	WRITE_I_32( DMA_REGS_CONFIG_BB_ROUTE_ARRAY [ i ], (k), (v) )
+#define DMA_REGS_CONFIG_BB_ROUTE_READ( i, k, r ) 	READ_I_32( DMA_REGS_CONFIG_BB_ROUTE_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved2 */
+	uint32_t r2     	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bb_route_to_tx_side */
+	uint32_t txroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved1 */
+	uint32_t r1     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bb_route_to_rx_side */
+	uint32_t rxroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_BB_ROUTE ;
+#else
+typedef struct
+{	uint32_t rxroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bb_route_to_rx_side */
+	uint32_t r1     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved1 */
+	uint32_t txroute	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bb_route_to_tx_side */
+	uint32_t r2     	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved2 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_BB_ROUTE ;
+#endif
+
+/*****************************************************************************************/
+/* POINTERS_RESET                                                                        */
+/* Resets the pointers of the peripherals FIFOs within the DMA. Bit per peripheral side  */
+/* (rx and tx).  For rx side resets the data and CD FIFOs.  For tx side resets the read  */
+/* requests FIFO.                                                                        */
+/*****************************************************************************************/
+
+#define DMA_REGS_CONFIG_PTRRST_R1_DEFAULT_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_R1_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_GPONTX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_GPONTX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_GPONTX_RESET_VALUE           ( 0x1 )
+#define DMA_REGS_CONFIG_PTRRST_GPONRX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_GPONRX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_GPONRX_RESET_VALUE           ( 0x1 )
+#define DMA_REGS_CONFIG_PTRRST_ETH4TX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH4TX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH4TX_RESET_VALUE           ( 0x1 )
+#define DMA_REGS_CONFIG_PTRRST_ETH4RX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH4RX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH4RX_RESET_VALUE           ( 0x1 )
+#define DMA_REGS_CONFIG_PTRRST_ETH3TX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH3TX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH3TX_RESET_VALUE           ( 0x1 )
+#define DMA_REGS_CONFIG_PTRRST_ETH3RX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH3RX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH3RX_RESET_VALUE           ( 0x1 )
+#define DMA_REGS_CONFIG_PTRRST_ETH2TX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH2TX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH2TX_RESET_VALUE           ( 0x1 )
+#define DMA_REGS_CONFIG_PTRRST_ETH2RX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH2RX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH2RX_RESET_VALUE           ( 0x1 )
+#define DMA_REGS_CONFIG_PTRRST_ETH1TX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH1TX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH1TX_RESET_VALUE           ( 0x1 )
+#define DMA_REGS_CONFIG_PTRRST_ETH1RX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH1RX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH1RX_RESET_VALUE           ( 0x1 )
+#define DMA_REGS_CONFIG_PTRRST_ETH0TX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH0TX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH0TX_RESET_VALUE           ( 0x1 )
+#define DMA_REGS_CONFIG_PTRRST_ETH0RX_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH0RX_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_PTRRST_ETH0RX_RESET_VALUE           ( 0x1 )
+
+
+#define DMA_REGS_CONFIG_PTRRST_OFFSET ( 0x00000094 )
+
+#define DMA_REGS_0_CONFIG_PTRRST_ADDRESS   	( DMA_REGS_0_CONFIG_ADDRESS + DMA_REGS_CONFIG_PTRRST_OFFSET )
+#define DMA_REGS_0_CONFIG_PTRRST_READ( r ) 	READ_32( ( DMA_REGS_0_CONFIG_PTRRST_ADDRESS ), (r) )
+#define DMA_REGS_0_CONFIG_PTRRST_WRITE( v )	WRITE_32( ( DMA_REGS_0_CONFIG_PTRRST_ADDRESS ), (v) )
+
+#define DMA_REGS_1_CONFIG_PTRRST_ADDRESS   	( DMA_REGS_1_CONFIG_ADDRESS + DMA_REGS_CONFIG_PTRRST_OFFSET )
+#define DMA_REGS_1_CONFIG_PTRRST_READ( r ) 	READ_32( ( DMA_REGS_1_CONFIG_PTRRST_ADDRESS ), (r) )
+#define DMA_REGS_1_CONFIG_PTRRST_WRITE( v )	WRITE_32( ( DMA_REGS_1_CONFIG_PTRRST_ADDRESS ), (v) )
+
+
+extern uint32_t DMA_REGS_CONFIG_PTRRST_ARRAY [ ] ;
+
+#define DMA_REGS_CONFIG_PTRRST_WRITE( i, v )	WRITE_32( DMA_REGS_CONFIG_PTRRST_ARRAY [ i ], (v) )
+#define DMA_REGS_CONFIG_PTRRST_READ( i, r ) 	READ_32( DMA_REGS_CONFIG_PTRRST_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1    	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gpon_tx_reset */
+	uint32_t gpontx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gpon_rx_reset */
+	uint32_t gponrx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_4_tx_reset */
+	uint32_t eth4tx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_4_rx_reset */
+	uint32_t eth4rx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_3_tx_reset */
+	uint32_t eth3tx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_3_rx_reset */
+	uint32_t eth3rx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_2_tx_reset */
+	uint32_t eth2tx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_2_rx_reset */
+	uint32_t eth2rx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_1_tx_reset */
+	uint32_t eth1tx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_1_rx_reset */
+	uint32_t eth1rx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_0_tx_reset */
+	uint32_t eth0tx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_0_rx_reset */
+	uint32_t eth0rx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_PTRRST ;
+#else
+typedef struct
+{	uint32_t eth0rx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_0_rx_reset */
+	uint32_t eth0tx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_0_tx_reset */
+	uint32_t eth1rx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_1_rx_reset */
+	uint32_t eth1tx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_1_tx_reset */
+	uint32_t eth2rx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_2_rx_reset */
+	uint32_t eth2tx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_2_tx_reset */
+	uint32_t eth3rx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_3_rx_reset */
+	uint32_t eth3tx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_3_tx_reset */
+	uint32_t eth4rx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_4_rx_reset */
+	uint32_t eth4tx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ethernet_4_tx_reset */
+	uint32_t gponrx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gpon_rx_reset */
+	uint32_t gpontx	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gpon_tx_reset */
+	uint32_t r1    	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_PTRRST ;
+#endif
+
+/*****************************************************************************************/
+/* MEM_SEL                                                                               */
+/* For DMA, there are 2 data memories for write data (upstream), Each client has a confi */
+/* gurable number of 128 bytes buffers in one of the memories (see MEMORY_ALLOCATION reg */
+/* ister).  The first memory has total of 64 byffers, while the second has 32 buffers.   */
+/* This register configures in which one of the memories the clients buffers are located */
+/*  (1 bit per client, 0 first memory, 1 second memory).  The CD buffers will also be lo */
+/* cated accordingly.                                                                    */
+/*****************************************************************************************/
+
+#define DMA_REGS_CONFIG_MEM_SEL_R1_RESERVED_VALUE               ( 0x0 )
+#define DMA_REGS_CONFIG_MEM_SEL_R1_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define DMA_REGS_CONFIG_MEM_SEL_MEM_SEL_FIRST_VALUE             ( 0x0 )
+#define DMA_REGS_CONFIG_MEM_SEL_MEM_SEL_FIRST_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_CONFIG_MEM_SEL_MEM_SEL_SECOND_VALUE            ( 0x1 )
+
+
+#define DMA_REGS_CONFIG_MEM_SEL_OFFSET ( 0x00000098 )
+
+#define DMA_REGS_0_CONFIG_MEM_SEL_ADDRESS   	( DMA_REGS_0_CONFIG_ADDRESS + DMA_REGS_CONFIG_MEM_SEL_OFFSET )
+#define DMA_REGS_0_CONFIG_MEM_SEL_READ( r ) 	READ_32( ( DMA_REGS_0_CONFIG_MEM_SEL_ADDRESS ), (r) )
+#define DMA_REGS_0_CONFIG_MEM_SEL_WRITE( v )	WRITE_32( ( DMA_REGS_0_CONFIG_MEM_SEL_ADDRESS ), (v) )
+
+#define DMA_REGS_1_CONFIG_MEM_SEL_ADDRESS   	( DMA_REGS_1_CONFIG_ADDRESS + DMA_REGS_CONFIG_MEM_SEL_OFFSET )
+#define DMA_REGS_1_CONFIG_MEM_SEL_READ( r ) 	READ_32( ( DMA_REGS_1_CONFIG_MEM_SEL_ADDRESS ), (r) )
+#define DMA_REGS_1_CONFIG_MEM_SEL_WRITE( v )	WRITE_32( ( DMA_REGS_1_CONFIG_MEM_SEL_ADDRESS ), (v) )
+
+
+extern uint32_t DMA_REGS_CONFIG_MEM_SEL_ARRAY [ ] ;
+
+#define DMA_REGS_CONFIG_MEM_SEL_WRITE( i, v )	WRITE_32( DMA_REGS_CONFIG_MEM_SEL_ARRAY [ i ], (v) )
+#define DMA_REGS_CONFIG_MEM_SEL_READ( i, r ) 	READ_32( DMA_REGS_CONFIG_MEM_SEL_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1     	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mem_sel */
+	uint32_t mem_sel	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_MEM_SEL ;
+#else
+typedef struct
+{	uint32_t mem_sel	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mem_sel */
+	uint32_t r1     	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG_MEM_SEL ;
+#endif
+
+/*****************************************************************************************/
+/* NOT_EMPTY_VECTOR                                                                      */
+/* Each peripheral, according to its source address, is represented in a bit on the not  */
+/* empty vector.  If the bit is asserted, the requests queue of the relevant peripheral  */
+/* is not empty.  The not empty vector is used by the DMA scheduler to determine which p */
+/* eripheral is the next to be served.                                                   */
+/*****************************************************************************************/
+
+#define DMA_REGS_DEBUG_NEMPTY_R1_R1_VALUE                      ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_R1_R1_VALUE_RESET_VALUE          ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_GPONTXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_GPONTXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_GPONTXNE_NOT_EMPTY_VALUE         ( 0x1 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH4TXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH4TXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH4TXNE_NOT_EMPTY_VALUE         ( 0x1 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH3TXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH3TXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH3TXNE_NOT_EMPTY_VALUE         ( 0x1 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH2TXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH2TXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH2TXNE_NOT_EMPTY_VALUE         ( 0x1 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH1TXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH1TXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH1TXNE_NOT_EMPTY_VALUE         ( 0x1 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH0TXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH0TXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH0TXNE_NOT_EMPTY_VALUE         ( 0x1 )
+#define DMA_REGS_DEBUG_NEMPTY_GPONRXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_GPONRXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_GPONRXNE_NOT_EMPTY_VALUE         ( 0x1 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH4RXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH4RXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH4RXNE_NOT_EMPTY_VALUE         ( 0x1 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH3RXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH3RXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH3RXNE_NOR_EMPTY_VALUE         ( 0x1 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH2RXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH2RXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH2RXNE_NOT_EMPTY_VALUE         ( 0x1 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH1RXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH1RXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH1RXNE_NOT_EMPTY_VALUE         ( 0x1 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH0RXNE_EMPTY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH0RXNE_EMPTY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_NEMPTY_ETH0RXNE_NOT_EMPTY_VALUE         ( 0x1 )
+
+
+#define DMA_REGS_DEBUG_NEMPTY_OFFSET ( 0x00000000 )
+
+#define DMA_REGS_0_DEBUG_NEMPTY_ADDRESS   	( DMA_REGS_0_DEBUG_ADDRESS + DMA_REGS_DEBUG_NEMPTY_OFFSET )
+#define DMA_REGS_0_DEBUG_NEMPTY_READ( r ) 	READ_32( ( DMA_REGS_0_DEBUG_NEMPTY_ADDRESS ), (r) )
+#define DMA_REGS_0_DEBUG_NEMPTY_WRITE( v )	WRITE_32( ( DMA_REGS_0_DEBUG_NEMPTY_ADDRESS ), (v) )
+
+#define DMA_REGS_1_DEBUG_NEMPTY_ADDRESS   	( DMA_REGS_1_DEBUG_ADDRESS + DMA_REGS_DEBUG_NEMPTY_OFFSET )
+#define DMA_REGS_1_DEBUG_NEMPTY_READ( r ) 	READ_32( ( DMA_REGS_1_DEBUG_NEMPTY_ADDRESS ), (r) )
+#define DMA_REGS_1_DEBUG_NEMPTY_WRITE( v )	WRITE_32( ( DMA_REGS_1_DEBUG_NEMPTY_ADDRESS ), (v) )
+
+
+extern uint32_t DMA_REGS_DEBUG_NEMPTY_ARRAY [ ] ;
+
+#define DMA_REGS_DEBUG_NEMPTY_WRITE( i, v )	WRITE_32( DMA_REGS_DEBUG_NEMPTY_ARRAY [ i ], (v) )
+#define DMA_REGS_DEBUG_NEMPTY_READ( i, r ) 	READ_32( DMA_REGS_DEBUG_NEMPTY_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved1 */
+	uint32_t r1      	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_TX_not_empty_indications */
+	uint32_t gpontxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet4_TX_not_empty_indications */
+	uint32_t eth4txne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet3_TX_not_empty_indications */
+	uint32_t eth3txne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet2_TX_not_empty_indications */
+	uint32_t eth2txne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet1_TX_not_empty_indications */
+	uint32_t eth1txne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet0_TX_not_empty_indications */
+	uint32_t eth0txne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_RX_not_empty_indications */
+	uint32_t gponrxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet4_RX_not_empty_indications */
+	uint32_t eth4rxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet3_RX_not_empty_indications */
+	uint32_t eth3rxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet2_RX_not_empty_indications */
+	uint32_t eth2rxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet1_RX_not_empty_indications */
+	uint32_t eth1rxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet0_RX_not_empty_indications */
+	uint32_t eth0rxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_NEMPTY ;
+#else
+typedef struct
+{	uint32_t eth0rxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet0_RX_not_empty_indications */
+	uint32_t eth1rxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet1_RX_not_empty_indications */
+	uint32_t eth2rxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet2_RX_not_empty_indications */
+	uint32_t eth3rxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet3_RX_not_empty_indications */
+	uint32_t eth4rxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet4_RX_not_empty_indications */
+	uint32_t gponrxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_RX_not_empty_indications */
+	uint32_t eth0txne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet0_TX_not_empty_indications */
+	uint32_t eth1txne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet1_TX_not_empty_indications */
+	uint32_t eth2txne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet2_TX_not_empty_indications */
+	uint32_t eth3txne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet3_TX_not_empty_indications */
+	uint32_t eth4txne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet4_TX_not_empty_indications */
+	uint32_t gpontxne	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_TX_not_empty_indications */
+	uint32_t r1      	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved1 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_NEMPTY ;
+#endif
+
+/*****************************************************************************************/
+/* URGENT_VECTOR                                                                         */
+/* Each peripheral, according to its source address, is represented in a bit on the urge */
+/* nt vector.  If the bit is asserted, the requests queue of the relevant peripheral is  */
+/* in urgent state.  The urgent vector is used by the DMA scheduler to determine which p */
+/* eripheral is the next to be served.                                                   */
+/*****************************************************************************************/
+
+#define DMA_REGS_DEBUG_URGNT_R1_R1_VALUE                          ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_R1_R1_VALUE_RESET_VALUE              ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_GPONTXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_GPONTXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_GPONTXU_URGENT_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_URGNT_ETH4TXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH4TXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH4TXU_URGENT_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_URGNT_ETH3TXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH3TXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH3TXU_URGENT_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_URGNT_ETH2TXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH2TXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH2TXU_URGENT_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_URGNT_ETH1TXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH1TXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH1TXU_URGENT_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_URGNT_ETH0TXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH0TXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH0TXU_URGENT_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_URGNT_GPONRXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_GPONRXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_GPONRXU_URGENT_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_URGNT_ETH4RXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH4RXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH4RXU_URGENT_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_URGNT_ETH3RXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH3RXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH3RXU_URGENT_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_URGNT_ETH2RXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH2RXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH2RXU_URGENT_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_URGNT_ETH1RXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH1RXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH1RXU_URGENT_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_URGNT_ETH0RXU_NOT_URGENT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH0RXU_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_URGNT_ETH0RXU_URGENT_VALUE                 ( 0x1 )
+
+
+#define DMA_REGS_DEBUG_URGNT_OFFSET ( 0x00000004 )
+
+#define DMA_REGS_0_DEBUG_URGNT_ADDRESS   	( DMA_REGS_0_DEBUG_ADDRESS + DMA_REGS_DEBUG_URGNT_OFFSET )
+#define DMA_REGS_0_DEBUG_URGNT_READ( r ) 	READ_32( ( DMA_REGS_0_DEBUG_URGNT_ADDRESS ), (r) )
+#define DMA_REGS_0_DEBUG_URGNT_WRITE( v )	WRITE_32( ( DMA_REGS_0_DEBUG_URGNT_ADDRESS ), (v) )
+
+#define DMA_REGS_1_DEBUG_URGNT_ADDRESS   	( DMA_REGS_1_DEBUG_ADDRESS + DMA_REGS_DEBUG_URGNT_OFFSET )
+#define DMA_REGS_1_DEBUG_URGNT_READ( r ) 	READ_32( ( DMA_REGS_1_DEBUG_URGNT_ADDRESS ), (r) )
+#define DMA_REGS_1_DEBUG_URGNT_WRITE( v )	WRITE_32( ( DMA_REGS_1_DEBUG_URGNT_ADDRESS ), (v) )
+
+
+extern uint32_t DMA_REGS_DEBUG_URGNT_ARRAY [ ] ;
+
+#define DMA_REGS_DEBUG_URGNT_WRITE( i, v )	WRITE_32( DMA_REGS_DEBUG_URGNT_ARRAY [ i ], (v) )
+#define DMA_REGS_DEBUG_URGNT_READ( i, r ) 	READ_32( DMA_REGS_DEBUG_URGNT_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved1 */
+	uint32_t r1     	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_TX_urgent_indication */
+	uint32_t gpontxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet4_TX_urgent_indication */
+	uint32_t eth4txu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet3_TX_urgent_indication */
+	uint32_t eth3txu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet2_TX_urgent_indication */
+	uint32_t eth2txu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet1_TX_urgent_indication */
+	uint32_t eth1txu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet0_TX_urgent_indication */
+	uint32_t eth0txu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_RX_urgent_indication */
+	uint32_t gponrxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet4_RX_urgent_indication */
+	uint32_t eth4rxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet3_RX_urgent_indication */
+	uint32_t eth3rxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet2_RX_urgent_indication */
+	uint32_t eth2rxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet1_RX_urgent_indication */
+	uint32_t eth1rxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet0_RX_urgent_indication */
+	uint32_t eth0rxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_URGNT ;
+#else
+typedef struct
+{	uint32_t eth0rxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet0_RX_urgent_indication */
+	uint32_t eth1rxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet1_RX_urgent_indication */
+	uint32_t eth2rxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet2_RX_urgent_indication */
+	uint32_t eth3rxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet3_RX_urgent_indication */
+	uint32_t eth4rxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet4_RX_urgent_indication */
+	uint32_t gponrxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_RX_urgent_indication */
+	uint32_t eth0txu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet0_TX_urgent_indication */
+	uint32_t eth1txu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet1_TX_urgent_indication */
+	uint32_t eth2txu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet2_TX_urgent_indication */
+	uint32_t eth3txu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet3_TX_urgent_indication */
+	uint32_t eth4txu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethernet4_TX_urgent_indication */
+	uint32_t gpontxu	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_TX_urgent_indication */
+	uint32_t r1     	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved1 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_URGNT ;
+#endif
+
+/*****************************************************************************************/
+/* SELECTED_SOURCE_NUM                                                                   */
+/* The decision of the dma schedule rand the next peripheral to be served, represented b */
+/* y its source address                                                                  */
+/*****************************************************************************************/
+
+#define DMA_REGS_DEBUG_SELSRC_R1_R1_VALUE                       ( 0x0 )
+#define DMA_REGS_DEBUG_SELSRC_R1_R1_VALUE_RESET_VALUE           ( 0x0 )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_ETH0_RX_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_ETH0_RX_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_ETH1_RX_VALUE             ( 0x1 )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_ETH2_RX_VALUE             ( 0x2 )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_ETH3_RX_VALUE             ( 0x3 )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_ETH4_RX_VALUE             ( 0x4 )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_GPON_RX_VALUE             ( 0x5 )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_ETH0_TX_VALUE             ( 0x8 )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_ETH1_TX_VALUE             ( 0x9 )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_ETH2_TX_VALUE             ( 0xA )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_ETH3_TX_VALUE             ( 0xB )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_ETH4_TX_VALUE             ( 0xC )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_GPON_TX_VALUE             ( 0xD )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_DEFAULT_VALUE             ( 0x1F )
+#define DMA_REGS_DEBUG_SELSRC_SEL_SRC_DEFAULT_VALUE_RESET_VALUE ( 0x1F )
+
+
+#define DMA_REGS_DEBUG_SELSRC_OFFSET ( 0x00000008 )
+
+#define DMA_REGS_0_DEBUG_SELSRC_ADDRESS   	( DMA_REGS_0_DEBUG_ADDRESS + DMA_REGS_DEBUG_SELSRC_OFFSET )
+#define DMA_REGS_0_DEBUG_SELSRC_READ( r ) 	READ_32( ( DMA_REGS_0_DEBUG_SELSRC_ADDRESS ), (r) )
+#define DMA_REGS_0_DEBUG_SELSRC_WRITE( v )	WRITE_32( ( DMA_REGS_0_DEBUG_SELSRC_ADDRESS ), (v) )
+
+#define DMA_REGS_1_DEBUG_SELSRC_ADDRESS   	( DMA_REGS_1_DEBUG_ADDRESS + DMA_REGS_DEBUG_SELSRC_OFFSET )
+#define DMA_REGS_1_DEBUG_SELSRC_READ( r ) 	READ_32( ( DMA_REGS_1_DEBUG_SELSRC_ADDRESS ), (r) )
+#define DMA_REGS_1_DEBUG_SELSRC_WRITE( v )	WRITE_32( ( DMA_REGS_1_DEBUG_SELSRC_ADDRESS ), (v) )
+
+
+extern uint32_t DMA_REGS_DEBUG_SELSRC_ARRAY [ ] ;
+
+#define DMA_REGS_DEBUG_SELSRC_WRITE( i, v )	WRITE_32( DMA_REGS_DEBUG_SELSRC_ARRAY [ i ], (v) )
+#define DMA_REGS_DEBUG_SELSRC_READ( i, r ) 	READ_32( DMA_REGS_DEBUG_SELSRC_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved1 */
+	uint32_t r1     	: 27 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* selected_source */
+	uint32_t sel_src	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_SELSRC ;
+#else
+typedef struct
+{	uint32_t sel_src	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* selected_source */
+	uint32_t r1     	: 27 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved1 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_SELSRC ;
+#endif
+
+/*****************************************************************************************/
+/* REQUEST_COUNTERS_RX                                                                   */
+/* the number of write requests currently pending for each rx peripheral.                */
+/*****************************************************************************************/
+
+#define DMA_REGS_DEBUG_REQ_CNT_RX_R1_R1_VALUE                   ( 0x0 )
+#define DMA_REGS_DEBUG_REQ_CNT_RX_R1_R1_VALUE_RESET_VALUE       ( 0x0 )
+#define DMA_REGS_DEBUG_REQ_CNT_RX_REQ_CNT_MIN_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_REQ_CNT_RX_REQ_CNT_MIN_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_REQ_CNT_RX_REQ_CNT_MAX_VALUE             ( 0x20 )
+
+
+#define DMA_REGS_DEBUG_REQ_CNT_RX_OFFSET ( 0x0000000C )
+
+#define DMA_REGS_0_DEBUG_REQ_CNT_RX_ADDRESS        	( DMA_REGS_0_DEBUG_ADDRESS + DMA_REGS_DEBUG_REQ_CNT_RX_OFFSET )
+#define DMA_REGS_0_DEBUG_REQ_CNT_RX_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_0_DEBUG_REQ_CNT_RX_ADDRESS ), (i), (r) )
+#define DMA_REGS_0_DEBUG_REQ_CNT_RX_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_0_DEBUG_REQ_CNT_RX_ADDRESS ), (i), (v) )
+
+#define DMA_REGS_1_DEBUG_REQ_CNT_RX_ADDRESS        	( DMA_REGS_1_DEBUG_ADDRESS + DMA_REGS_DEBUG_REQ_CNT_RX_OFFSET )
+#define DMA_REGS_1_DEBUG_REQ_CNT_RX_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_1_DEBUG_REQ_CNT_RX_ADDRESS ), (i), (r) )
+#define DMA_REGS_1_DEBUG_REQ_CNT_RX_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_1_DEBUG_REQ_CNT_RX_ADDRESS ), (i), (v) )
+
+
+extern uint32_t DMA_REGS_DEBUG_REQ_CNT_RX_ARRAY [ ] ;
+
+#define DMA_REGS_DEBUG_REQ_CNT_RX_WRITE( i, k, v )	WRITE_I_32( DMA_REGS_DEBUG_REQ_CNT_RX_ARRAY [ i ], (k), (v) )
+#define DMA_REGS_DEBUG_REQ_CNT_RX_READ( i, k, r ) 	READ_I_32( DMA_REGS_DEBUG_REQ_CNT_RX_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved1 */
+	uint32_t r1     	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* write_requests_counter */
+	uint32_t req_cnt	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_REQ_CNT_RX ;
+#else
+typedef struct
+{	uint32_t req_cnt	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* write_requests_counter */
+	uint32_t r1     	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved1 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_REQ_CNT_RX ;
+#endif
+
+/*****************************************************************************************/
+/* REQUEST_COUNTERS_TX                                                                   */
+/* the number of read requestscurrently pending for each TX peripheral.                  */
+/*****************************************************************************************/
+
+#define DMA_REGS_DEBUG_REQ_CNT_TX_R1_R3_VALUE                   ( 0x0 )
+#define DMA_REGS_DEBUG_REQ_CNT_TX_R1_R3_VALUE_RESET_VALUE       ( 0x0 )
+#define DMA_REGS_DEBUG_REQ_CNT_TX_REQ_CNT_MIN_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_REQ_CNT_TX_REQ_CNT_MIN_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_REQ_CNT_TX_REQ_CNT_MAX_VALUE             ( 0x8 )
+
+
+#define DMA_REGS_DEBUG_REQ_CNT_TX_OFFSET ( 0x00000024 )
+
+#define DMA_REGS_0_DEBUG_REQ_CNT_TX_ADDRESS        	( DMA_REGS_0_DEBUG_ADDRESS + DMA_REGS_DEBUG_REQ_CNT_TX_OFFSET )
+#define DMA_REGS_0_DEBUG_REQ_CNT_TX_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_0_DEBUG_REQ_CNT_TX_ADDRESS ), (i), (r) )
+#define DMA_REGS_0_DEBUG_REQ_CNT_TX_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_0_DEBUG_REQ_CNT_TX_ADDRESS ), (i), (v) )
+
+#define DMA_REGS_1_DEBUG_REQ_CNT_TX_ADDRESS        	( DMA_REGS_1_DEBUG_ADDRESS + DMA_REGS_DEBUG_REQ_CNT_TX_OFFSET )
+#define DMA_REGS_1_DEBUG_REQ_CNT_TX_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_1_DEBUG_REQ_CNT_TX_ADDRESS ), (i), (r) )
+#define DMA_REGS_1_DEBUG_REQ_CNT_TX_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_1_DEBUG_REQ_CNT_TX_ADDRESS ), (i), (v) )
+
+
+extern uint32_t DMA_REGS_DEBUG_REQ_CNT_TX_ARRAY [ ] ;
+
+#define DMA_REGS_DEBUG_REQ_CNT_TX_WRITE( i, k, v )	WRITE_I_32( DMA_REGS_DEBUG_REQ_CNT_TX_ARRAY [ i ], (k), (v) )
+#define DMA_REGS_DEBUG_REQ_CNT_TX_READ( i, k, r ) 	READ_I_32( DMA_REGS_DEBUG_REQ_CNT_TX_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1     	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* read_requests_counter */
+	uint32_t req_cnt	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_REQ_CNT_TX ;
+#else
+typedef struct
+{	uint32_t req_cnt	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* read_requests_counter */
+	uint32_t r1     	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_REQ_CNT_TX ;
+#endif
+
+/*****************************************************************************************/
+/* ACC_REQUEST_COUNTERS_RX                                                               */
+/* the accumulated number of write requests served so far for each peripheral. Wrap arou */
+/* nd on max value, not read clear.                                                      */
+/*****************************************************************************************/
+
+#define DMA_REGS_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_CNT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_CNT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define DMA_REGS_DEBUG_REQ_CNT_RX_ACC_OFFSET ( 0x0000003C )
+
+#define DMA_REGS_0_DEBUG_REQ_CNT_RX_ACC_ADDRESS        	( DMA_REGS_0_DEBUG_ADDRESS + DMA_REGS_DEBUG_REQ_CNT_RX_ACC_OFFSET )
+#define DMA_REGS_0_DEBUG_REQ_CNT_RX_ACC_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_0_DEBUG_REQ_CNT_RX_ACC_ADDRESS ), (i), (r) )
+#define DMA_REGS_0_DEBUG_REQ_CNT_RX_ACC_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_0_DEBUG_REQ_CNT_RX_ACC_ADDRESS ), (i), (v) )
+
+#define DMA_REGS_1_DEBUG_REQ_CNT_RX_ACC_ADDRESS        	( DMA_REGS_1_DEBUG_ADDRESS + DMA_REGS_DEBUG_REQ_CNT_RX_ACC_OFFSET )
+#define DMA_REGS_1_DEBUG_REQ_CNT_RX_ACC_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_1_DEBUG_REQ_CNT_RX_ACC_ADDRESS ), (i), (r) )
+#define DMA_REGS_1_DEBUG_REQ_CNT_RX_ACC_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_1_DEBUG_REQ_CNT_RX_ACC_ADDRESS ), (i), (v) )
+
+
+extern uint32_t DMA_REGS_DEBUG_REQ_CNT_RX_ACC_ARRAY [ ] ;
+
+#define DMA_REGS_DEBUG_REQ_CNT_RX_ACC_WRITE( i, k, v )	WRITE_I_32( DMA_REGS_DEBUG_REQ_CNT_RX_ACC_ARRAY [ i ], (k), (v) )
+#define DMA_REGS_DEBUG_REQ_CNT_RX_ACC_READ( i, k, r ) 	READ_I_32( DMA_REGS_DEBUG_REQ_CNT_RX_ACC_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* write_requests_counter */
+	uint32_t req_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_REQ_CNT_RX_ACC ;
+#else
+typedef struct
+{	uint32_t req_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* write_requests_counter */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_REQ_CNT_RX_ACC ;
+#endif
+
+/*****************************************************************************************/
+/* ACC_REQUEST_COUNTERS_TX                                                               */
+/* the accumulated number of read requests served so far for each peripheral. Wrap aroun */
+/* d on max value, not read clear.                                                       */
+/*****************************************************************************************/
+
+#define DMA_REGS_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_CNT_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_CNT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define DMA_REGS_DEBUG_REQ_CNT_TX_ACC_OFFSET ( 0x00000054 )
+
+#define DMA_REGS_0_DEBUG_REQ_CNT_TX_ACC_ADDRESS        	( DMA_REGS_0_DEBUG_ADDRESS + DMA_REGS_DEBUG_REQ_CNT_TX_ACC_OFFSET )
+#define DMA_REGS_0_DEBUG_REQ_CNT_TX_ACC_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_0_DEBUG_REQ_CNT_TX_ACC_ADDRESS ), (i), (r) )
+#define DMA_REGS_0_DEBUG_REQ_CNT_TX_ACC_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_0_DEBUG_REQ_CNT_TX_ACC_ADDRESS ), (i), (v) )
+
+#define DMA_REGS_1_DEBUG_REQ_CNT_TX_ACC_ADDRESS        	( DMA_REGS_1_DEBUG_ADDRESS + DMA_REGS_DEBUG_REQ_CNT_TX_ACC_OFFSET )
+#define DMA_REGS_1_DEBUG_REQ_CNT_TX_ACC_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_1_DEBUG_REQ_CNT_TX_ACC_ADDRESS ), (i), (r) )
+#define DMA_REGS_1_DEBUG_REQ_CNT_TX_ACC_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_1_DEBUG_REQ_CNT_TX_ACC_ADDRESS ), (i), (v) )
+
+
+extern uint32_t DMA_REGS_DEBUG_REQ_CNT_TX_ACC_ARRAY [ ] ;
+
+#define DMA_REGS_DEBUG_REQ_CNT_TX_ACC_WRITE( i, k, v )	WRITE_I_32( DMA_REGS_DEBUG_REQ_CNT_TX_ACC_ARRAY [ i ], (k), (v) )
+#define DMA_REGS_DEBUG_REQ_CNT_TX_ACC_READ( i, k, r ) 	READ_I_32( DMA_REGS_DEBUG_REQ_CNT_TX_ACC_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* write_requests_counter */
+	uint32_t req_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_REQ_CNT_TX_ACC ;
+#else
+typedef struct
+{	uint32_t req_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* write_requests_counter */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_REQ_CNT_TX_ACC ;
+#endif
+
+/*****************************************************************************************/
+/* RAM_ADDRES                                                                            */
+/* the address and cs of the ram the user wishes to read using the indirect access read  */
+/* mechanism.                                                                            */
+/*****************************************************************************************/
+
+#define DMA_REGS_DEBUG_RDADD_R2_DEFAULT_VALUE              ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_R2_DEFAULT_VALUE_RESET_VALUE  ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_CDCS1_OFF_VALUE               ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_CDCS1_OFF_VALUE_RESET_VALUE   ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_CDCS1_ON_VALUE                ( 0x1 )
+#define DMA_REGS_DEBUG_RDADD_DATACS1_OFF_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_DATACS1_OFF_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_DATACS1_ON_VALUE              ( 0x1 )
+#define DMA_REGS_DEBUG_RDADD_RDCS_OFF_VALUE                ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_RDCS_OFF_VALUE_RESET_VALUE    ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_RDCS_ON_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_RDADD_RRCS_OFF_VALUE                ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_RRCS_OFF_VALUE_RESET_VALUE    ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_RRCS_ON_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_RDADD_CDCS_OFF_VALUE                ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_CDCS_OFF_VALUE_RESET_VALUE    ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_CDCS_ON_VALUE                 ( 0x1 )
+#define DMA_REGS_DEBUG_RDADD_DATACS_OFF_VALUE              ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_DATACS_OFF_VALUE_RESET_VALUE  ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_DATACS_ON_VALUE               ( 0x1 )
+#define DMA_REGS_DEBUG_RDADD_R1_DEFAULT_VALUE              ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_R1_DEFAULT_VALUE_RESET_VALUE  ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_ADDRESS_ADD_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_RDADD_ADDRESS_ADD_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define DMA_REGS_DEBUG_RDADD_OFFSET ( 0x00000100 )
+
+#define DMA_REGS_0_DEBUG_RDADD_ADDRESS   	( DMA_REGS_0_DEBUG_ADDRESS + DMA_REGS_DEBUG_RDADD_OFFSET )
+#define DMA_REGS_0_DEBUG_RDADD_READ( r ) 	READ_32( ( DMA_REGS_0_DEBUG_RDADD_ADDRESS ), (r) )
+#define DMA_REGS_0_DEBUG_RDADD_WRITE( v )	WRITE_32( ( DMA_REGS_0_DEBUG_RDADD_ADDRESS ), (v) )
+
+#define DMA_REGS_1_DEBUG_RDADD_ADDRESS   	( DMA_REGS_1_DEBUG_ADDRESS + DMA_REGS_DEBUG_RDADD_OFFSET )
+#define DMA_REGS_1_DEBUG_RDADD_READ( r ) 	READ_32( ( DMA_REGS_1_DEBUG_RDADD_ADDRESS ), (r) )
+#define DMA_REGS_1_DEBUG_RDADD_WRITE( v )	WRITE_32( ( DMA_REGS_1_DEBUG_RDADD_ADDRESS ), (v) )
+
+
+extern uint32_t DMA_REGS_DEBUG_RDADD_ARRAY [ ] ;
+
+#define DMA_REGS_DEBUG_RDADD_WRITE( i, v )	WRITE_32( DMA_REGS_DEBUG_RDADD_ARRAY [ i ], (v) )
+#define DMA_REGS_DEBUG_RDADD_READ( i, r ) 	READ_32( DMA_REGS_DEBUG_RDADD_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r2     	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cd_ram_cs1 */
+	uint32_t cdcs1  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data_ram_cs_1 */
+	uint32_t datacs1	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rd_data_cs */
+	uint32_t rdcs   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rr_ram_cd */
+	uint32_t rrcs   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cd_ram_cs */
+	uint32_t cdcs   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data_ram_cs */
+	uint32_t datacs 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1     	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* address */
+	uint32_t address	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_RDADD ;
+#else
+typedef struct
+{	uint32_t address	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* address */
+	uint32_t r1     	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t datacs 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data_ram_cs */
+	uint32_t cdcs   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cd_ram_cs */
+	uint32_t rrcs   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rr_ram_cd */
+	uint32_t rdcs   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rd_data_cs */
+	uint32_t datacs1	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data_ram_cs_1 */
+	uint32_t cdcs1  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cd_ram_cs1 */
+	uint32_t r2     	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_RDADD ;
+#endif
+
+/*****************************************************************************************/
+/* INDIRECT_READ_REQUEST_VALID                                                           */
+/* After determining the address and cs, the user should assert this bit for indicating  */
+/* that the address and cs are valid.                                                    */
+/*****************************************************************************************/
+
+#define DMA_REGS_DEBUG_RDVALID_R1_DEFAULT_VALUE                  ( 0x0 )
+#define DMA_REGS_DEBUG_RDVALID_R1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define DMA_REGS_DEBUG_RDVALID_VALID_NOT_VALID_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_RDVALID_VALID_NOT_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_RDVALID_VALID_VALID_VALUE                 ( 0x1 )
+
+
+#define DMA_REGS_DEBUG_RDVALID_OFFSET ( 0x00000104 )
+
+#define DMA_REGS_0_DEBUG_RDVALID_ADDRESS   	( DMA_REGS_0_DEBUG_ADDRESS + DMA_REGS_DEBUG_RDVALID_OFFSET )
+#define DMA_REGS_0_DEBUG_RDVALID_READ( r ) 	READ_32( ( DMA_REGS_0_DEBUG_RDVALID_ADDRESS ), (r) )
+#define DMA_REGS_0_DEBUG_RDVALID_WRITE( v )	WRITE_32( ( DMA_REGS_0_DEBUG_RDVALID_ADDRESS ), (v) )
+
+#define DMA_REGS_1_DEBUG_RDVALID_ADDRESS   	( DMA_REGS_1_DEBUG_ADDRESS + DMA_REGS_DEBUG_RDVALID_OFFSET )
+#define DMA_REGS_1_DEBUG_RDVALID_READ( r ) 	READ_32( ( DMA_REGS_1_DEBUG_RDVALID_ADDRESS ), (r) )
+#define DMA_REGS_1_DEBUG_RDVALID_WRITE( v )	WRITE_32( ( DMA_REGS_1_DEBUG_RDVALID_ADDRESS ), (v) )
+
+
+extern uint32_t DMA_REGS_DEBUG_RDVALID_ARRAY [ ] ;
+
+#define DMA_REGS_DEBUG_RDVALID_WRITE( i, v )	WRITE_32( DMA_REGS_DEBUG_RDVALID_ARRAY [ i ], (v) )
+#define DMA_REGS_DEBUG_RDVALID_READ( i, r ) 	READ_32( DMA_REGS_DEBUG_RDVALID_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1   	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* valid */
+	uint32_t valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_RDVALID ;
+#else
+typedef struct
+{	uint32_t valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* valid */
+	uint32_t r1   	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_RDVALID ;
+#endif
+
+/*****************************************************************************************/
+/* INDIRECT_READ_DATA                                                                    */
+/* The returned read data from the selected RAM. Array of 4 registers (128 bits total).  */
+/*  The width of the different memories is as follows:  write data - 128 bits  chunk des */
+/* criptors - 36 bits  read requests - 42 bits  read data - 64 bits    The the memories  */
+/* with width smaller than 128, the data will appear in the first registers of the array */
+/* , for example:  data from the cd RAM will appear in - {reg1[5:0], reg0[31:0]}.        */
+/*****************************************************************************************/
+
+#define DMA_REGS_DEBUG_RDDATA_DATA_DATA_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_RDDATA_DATA_DATA_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define DMA_REGS_DEBUG_RDDATA_OFFSET ( 0x00000108 )
+
+#define DMA_REGS_0_DEBUG_RDDATA_ADDRESS        	( DMA_REGS_0_DEBUG_ADDRESS + DMA_REGS_DEBUG_RDDATA_OFFSET )
+#define DMA_REGS_0_DEBUG_RDDATA_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_0_DEBUG_RDDATA_ADDRESS ), (i), (r) )
+#define DMA_REGS_0_DEBUG_RDDATA_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_0_DEBUG_RDDATA_ADDRESS ), (i), (v) )
+
+#define DMA_REGS_1_DEBUG_RDDATA_ADDRESS        	( DMA_REGS_1_DEBUG_ADDRESS + DMA_REGS_DEBUG_RDDATA_OFFSET )
+#define DMA_REGS_1_DEBUG_RDDATA_READ_I( r, i ) 	READ_I_32( ( DMA_REGS_1_DEBUG_RDDATA_ADDRESS ), (i), (r) )
+#define DMA_REGS_1_DEBUG_RDDATA_WRITE_I( v, i )	WRITE_I_32( ( DMA_REGS_1_DEBUG_RDDATA_ADDRESS ), (i), (v) )
+
+
+extern uint32_t DMA_REGS_DEBUG_RDDATA_ARRAY [ ] ;
+
+#define DMA_REGS_DEBUG_RDDATA_WRITE( i, k, v )	WRITE_I_32( DMA_REGS_DEBUG_RDDATA_ARRAY [ i ], (k), (v) )
+#define DMA_REGS_DEBUG_RDDATA_READ( i, k, r ) 	READ_I_32( DMA_REGS_DEBUG_RDDATA_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* data */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_RDDATA ;
+#else
+typedef struct
+{	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_RDDATA ;
+#endif
+
+/*****************************************************************************************/
+/* READ_DATA_READY                                                                       */
+/* When assertd indicats that the data in the previous array is valid.Willremain asserte */
+/* d until the user deasserts the valid bit in regiser RDVALID.                          */
+/*****************************************************************************************/
+
+#define DMA_REGS_DEBUG_RDDATARDY_R1_DEFAULT_VALUE                  ( 0x0 )
+#define DMA_REGS_DEBUG_RDDATARDY_R1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define DMA_REGS_DEBUG_RDDATARDY_READY_NOT_READY_VALUE             ( 0x0 )
+#define DMA_REGS_DEBUG_RDDATARDY_READY_NOT_READY_VALUE_RESET_VALUE ( 0x0 )
+#define DMA_REGS_DEBUG_RDDATARDY_READY_READY_VALUE                 ( 0x1 )
+
+
+#define DMA_REGS_DEBUG_RDDATARDY_OFFSET ( 0x00000118 )
+
+#define DMA_REGS_0_DEBUG_RDDATARDY_ADDRESS   	( DMA_REGS_0_DEBUG_ADDRESS + DMA_REGS_DEBUG_RDDATARDY_OFFSET )
+#define DMA_REGS_0_DEBUG_RDDATARDY_READ( r ) 	READ_32( ( DMA_REGS_0_DEBUG_RDDATARDY_ADDRESS ), (r) )
+#define DMA_REGS_0_DEBUG_RDDATARDY_WRITE( v )	WRITE_32( ( DMA_REGS_0_DEBUG_RDDATARDY_ADDRESS ), (v) )
+
+#define DMA_REGS_1_DEBUG_RDDATARDY_ADDRESS   	( DMA_REGS_1_DEBUG_ADDRESS + DMA_REGS_DEBUG_RDDATARDY_OFFSET )
+#define DMA_REGS_1_DEBUG_RDDATARDY_READ( r ) 	READ_32( ( DMA_REGS_1_DEBUG_RDDATARDY_ADDRESS ), (r) )
+#define DMA_REGS_1_DEBUG_RDDATARDY_WRITE( v )	WRITE_32( ( DMA_REGS_1_DEBUG_RDDATARDY_ADDRESS ), (v) )
+
+
+extern uint32_t DMA_REGS_DEBUG_RDDATARDY_ARRAY [ ] ;
+
+#define DMA_REGS_DEBUG_RDDATARDY_WRITE( i, v )	WRITE_32( DMA_REGS_DEBUG_RDDATARDY_ARRAY [ i ], (v) )
+#define DMA_REGS_DEBUG_RDDATARDY_READ( i, r ) 	READ_32( DMA_REGS_DEBUG_RDDATARDY_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1   	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ready */
+	uint32_t ready	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_RDDATARDY ;
+#else
+typedef struct
+{	uint32_t ready	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ready */
+	uint32_t r1   	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG_RDDATARDY ;
+#endif
+
+/*****************************************************************************************/
+/* The registers in this section allow configuration of the following:  1. memory alloca */
+/* tions  2. priority and weight for arbitration  3. urgent thresholds  4. route address */
+/* es    Most of the registers control the configuration of a single peripheral. They ar */
+/* e arranged in arrays according to their configuration topic.    The order of peripher */
+/* als within each array is:  Ethernet 0  Ethernet 1  Ethernet 2  Ethernet 3  Ethernet 4 */
+/*   GPON                                                                                */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define DMA_REGS_CONFIG_MALLOC_NUMBER ( 6 )
+#define DMA_REGS_CONFIG_READ_BASE_NUMBER ( 6 )
+#define DMA_REGS_CONFIG_U_THRESH_NUMBER ( 6 )
+#define DMA_REGS_CONFIG_PRI_NUMBER ( 6 )
+#define DMA_REGS_CONFIG_WEIGHT_NUMBER ( 6 )
+#define DMA_REGS_CONFIG_BB_ROUTE_NUMBER ( 6 )
+typedef struct
+{
+	/* BB_SOURCE */
+	DMA_REGS_CONFIG_SOURCE source __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MEMORY_ALLOCATION */
+	DMA_REGS_CONFIG_MALLOC malloc [ DMA_REGS_CONFIG_MALLOC_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* READ_REQ_BASE_ADDRESS */
+	DMA_REGS_CONFIG_READ_BASE read_base [ DMA_REGS_CONFIG_READ_BASE_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* URGENT_THRESHOLDS */
+	DMA_REGS_CONFIG_U_THRESH u_thresh [ DMA_REGS_CONFIG_U_THRESH_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* STRICT_PRIORITY */
+	DMA_REGS_CONFIG_PRI pri [ DMA_REGS_CONFIG_PRI_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* WEIGHT_OF_ROUND_ROBIN */
+	DMA_REGS_CONFIG_WEIGHT weight [ DMA_REGS_CONFIG_WEIGHT_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BB_ROUTE_DMA_PERIPH */
+	DMA_REGS_CONFIG_BB_ROUTE bb_route [ DMA_REGS_CONFIG_BB_ROUTE_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* POINTERS_RESET */
+	DMA_REGS_CONFIG_PTRRST ptrrst __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MEM_SEL */
+	DMA_REGS_CONFIG_MEM_SEL mem_sel __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_CONFIG ;
+
+/*****************************************************************************************/
+/* request counters per peripheral                                                       */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define DMA_REGS_DEBUG_REQ_CNT_RX_NUMBER ( 6 )
+#define DMA_REGS_DEBUG_REQ_CNT_TX_NUMBER ( 6 )
+#define DMA_REGS_DEBUG_REQ_CNT_RX_ACC_NUMBER ( 6 )
+#define DMA_REGS_DEBUG_REQ_CNT_TX_ACC_NUMBER ( 6 )
+#define DMA_REGS_DEBUG_RDDATA_NUMBER ( 4 )
+typedef struct
+{
+	/* NOT_EMPTY_VECTOR */
+	DMA_REGS_DEBUG_NEMPTY nempty __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* URGENT_VECTOR */
+	DMA_REGS_DEBUG_URGNT urgnt __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SELECTED_SOURCE_NUM */
+	DMA_REGS_DEBUG_SELSRC selsrc __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* REQUEST_COUNTERS_RX */
+	DMA_REGS_DEBUG_REQ_CNT_RX req_cnt_rx [ DMA_REGS_DEBUG_REQ_CNT_RX_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* REQUEST_COUNTERS_TX */
+	DMA_REGS_DEBUG_REQ_CNT_TX req_cnt_tx [ DMA_REGS_DEBUG_REQ_CNT_TX_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ACC_REQUEST_COUNTERS_RX */
+	DMA_REGS_DEBUG_REQ_CNT_RX_ACC req_cnt_rx_acc [ DMA_REGS_DEBUG_REQ_CNT_RX_ACC_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ACC_REQUEST_COUNTERS_TX */
+	DMA_REGS_DEBUG_REQ_CNT_TX_ACC req_cnt_tx_acc [ DMA_REGS_DEBUG_REQ_CNT_TX_ACC_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 148 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RAM_ADDRES */
+	DMA_REGS_DEBUG_RDADD rdadd __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* INDIRECT_READ_REQUEST_VALID */
+	DMA_REGS_DEBUG_RDVALID rdvalid __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* INDIRECT_READ_DATA */
+	DMA_REGS_DEBUG_RDDATA rddata [ DMA_REGS_DEBUG_RDDATA_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* READ_DATA_READY */
+	DMA_REGS_DEBUG_RDDATARDY rddatardy __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS_DEBUG ;
+
+typedef struct
+{
+	/* config function */
+	DMA_REGS_CONFIG config __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved0 [ 100 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* debug function */
+	DMA_REGS_DEBUG debug __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+DMA_REGS ;
+
+#define DMA_REGS_NUMBER ( 2 )
+typedef struct
+{
+	/* REGS */
+	DMA_REGS regs [ DMA_REGS_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ 
+DMA_FOR_ALL ;
+#endif /* DMA_H_INCLUDED */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_dma_arrays.c b/arch/arm/mach-bcmbca/rdp/rdp_dma_arrays.c
new file mode 100755
index 0000000000..8e6c880e5b
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_dma_arrays.c
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/
+
+/*  File automatically generated by Reggae at 15/01/2013  09:25:30   */
+
+/* Addresses for Multiple blocks and/or functions */
+
+#include "rdp_subsystem_common.h"
+#include "rdp_dma.h"
+
+uint32_t DMA_REGS_CONFIG_SOURCE_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_CONFIG_SOURCE_ADDRESS,
+	DMA_REGS_1_CONFIG_SOURCE_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_CONFIG_SOURCE_ARRAY);
+
+uint32_t DMA_REGS_CONFIG_MALLOC_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_CONFIG_MALLOC_ADDRESS,
+	DMA_REGS_1_CONFIG_MALLOC_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_CONFIG_MALLOC_ARRAY);
+
+uint32_t DMA_REGS_CONFIG_READ_BASE_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_CONFIG_READ_BASE_ADDRESS,
+	DMA_REGS_1_CONFIG_READ_BASE_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_CONFIG_READ_BASE_ARRAY);
+
+uint32_t DMA_REGS_CONFIG_U_THRESH_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_CONFIG_U_THRESH_ADDRESS,
+	DMA_REGS_1_CONFIG_U_THRESH_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_CONFIG_U_THRESH_ARRAY);
+
+uint32_t DMA_REGS_CONFIG_PRI_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_CONFIG_PRI_ADDRESS,
+	DMA_REGS_1_CONFIG_PRI_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_CONFIG_PRI_ARRAY);
+
+uint32_t DMA_REGS_CONFIG_WEIGHT_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_CONFIG_WEIGHT_ADDRESS,
+	DMA_REGS_1_CONFIG_WEIGHT_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_CONFIG_WEIGHT_ARRAY);
+
+uint32_t DMA_REGS_CONFIG_BB_ROUTE_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_CONFIG_BB_ROUTE_ADDRESS,
+	DMA_REGS_1_CONFIG_BB_ROUTE_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_CONFIG_BB_ROUTE_ARRAY);
+
+uint32_t DMA_REGS_CONFIG_PTRRST_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_CONFIG_PTRRST_ADDRESS,
+	DMA_REGS_1_CONFIG_PTRRST_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_CONFIG_PTRRST_ARRAY);
+
+uint32_t DMA_REGS_CONFIG_MEM_SEL_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_CONFIG_MEM_SEL_ADDRESS,
+	DMA_REGS_1_CONFIG_MEM_SEL_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_CONFIG_MEM_SEL_ARRAY);
+
+uint32_t DMA_REGS_DEBUG_NEMPTY_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_DEBUG_NEMPTY_ADDRESS,
+	DMA_REGS_1_DEBUG_NEMPTY_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_DEBUG_NEMPTY_ARRAY);
+
+uint32_t DMA_REGS_DEBUG_URGNT_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_DEBUG_URGNT_ADDRESS,
+	DMA_REGS_1_DEBUG_URGNT_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_DEBUG_URGNT_ARRAY);
+
+uint32_t DMA_REGS_DEBUG_SELSRC_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_DEBUG_SELSRC_ADDRESS,
+	DMA_REGS_1_DEBUG_SELSRC_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_DEBUG_SELSRC_ARRAY);
+
+uint32_t DMA_REGS_DEBUG_REQ_CNT_RX_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_DEBUG_REQ_CNT_RX_ADDRESS,
+	DMA_REGS_1_DEBUG_REQ_CNT_RX_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_DEBUG_REQ_CNT_RX_ARRAY);
+
+uint32_t DMA_REGS_DEBUG_REQ_CNT_TX_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_DEBUG_REQ_CNT_TX_ADDRESS,
+	DMA_REGS_1_DEBUG_REQ_CNT_TX_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_DEBUG_REQ_CNT_TX_ARRAY);
+
+uint32_t DMA_REGS_DEBUG_REQ_CNT_RX_ACC_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_DEBUG_REQ_CNT_RX_ACC_ADDRESS,
+	DMA_REGS_1_DEBUG_REQ_CNT_RX_ACC_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_DEBUG_REQ_CNT_RX_ACC_ARRAY);
+
+uint32_t DMA_REGS_DEBUG_REQ_CNT_TX_ACC_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_DEBUG_REQ_CNT_TX_ACC_ADDRESS,
+	DMA_REGS_1_DEBUG_REQ_CNT_TX_ACC_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_DEBUG_REQ_CNT_TX_ACC_ARRAY);
+
+uint32_t DMA_REGS_DEBUG_RDADD_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_DEBUG_RDADD_ADDRESS,
+	DMA_REGS_1_DEBUG_RDADD_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_DEBUG_RDADD_ARRAY);
+
+uint32_t DMA_REGS_DEBUG_RDVALID_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_DEBUG_RDVALID_ADDRESS,
+	DMA_REGS_1_DEBUG_RDVALID_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_DEBUG_RDVALID_ARRAY);
+
+uint32_t DMA_REGS_DEBUG_RDDATA_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_DEBUG_RDDATA_ADDRESS,
+	DMA_REGS_1_DEBUG_RDDATA_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_DEBUG_RDDATA_ARRAY);
+
+uint32_t DMA_REGS_DEBUG_RDDATARDY_ARRAY [ 2 ] =
+{
+	DMA_REGS_0_DEBUG_RDDATARDY_ADDRESS,
+	DMA_REGS_1_DEBUG_RDDATARDY_ADDRESS
+} ;
+
+EXPORT_SYMBOL(DMA_REGS_DEBUG_RDDATARDY_ARRAY);
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_drv_bbh.c b/arch/arm/mach-bcmbca/rdp/rdp_drv_bbh.c
new file mode 100755
index 0000000000..53c5e6886c
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_drv_bbh.c
@@ -0,0 +1,1042 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the implementation of the Lilac BBH driver              */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+
+#include "rdp_subsystem_common.h"
+#include "rdp_drv_bbh.h"
+
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+
+#define CS_NUMBER_OF_BITS_IN_REGISTER                                     ( 32 )
+
+#define CS_RX_MAXIMAL_FLOW_INDEX_FOR_MINPKTSEL0_AND_MAXPKTSEL0_REGISTERS  ( 15 )
+
+#define CS_RX_FIELD_LENGTH_FOR_MINPKTSEL_AND_MAXPKTSEL_REGISTERS          ( 2 )
+
+#define CS_RX_MAXIMAL_FLOW_INDEX_FOR_IHCLASS0_REGISTER                    ( 7 )
+#define CS_RX_MAXIMAL_FLOW_INDEX_FOR_IHCLASS1_REGISTER                    ( 15 )
+#define CS_RX_MAXIMAL_FLOW_INDEX_FOR_IHCLASS2_REGISTER                    ( 23 )
+                                                                                 
+#define CS_RX_FIELD_LENGTH_FOR_IHCLASS_REGISTERS                          ( 4 )
+
+/* ingress buffer size */
+#define CS_DRV_BBH_RX_INGRESS_BUFFER_SIZE                              ( 128 )
+
+/* DDR buffer size */
+#define CS_DRV_BBH_RX_DDR_BUFFER_SIZE_2K                              ( 2048 )
+#define CS_DRV_BBH_RX_DDR_BUFFER_SIZE_2_5K                            ( 2560 )
+#define CS_DRV_BBH_RX_DDR_BUFFER_SIZE_4K                              ( 4096 )
+#define CS_DRV_BBH_RX_DDR_BUFFER_SIZE_16K                             ( 16384 )
+
+/* The max Tcont number in the GMP */
+#define CS_DRV_MAX_NUM_OF_TCONTS_SW									  ( 32 )
+/* The max physical Tcont id number */
+#define CS_DRV_MAX_NUM_OF_TCONTS_PHYSICAL							  ( 39 )
+
+/******************************************************************************/
+/*                                                                            */
+/* Macros definitions                                                         */
+/*                                                                            */
+/******************************************************************************/
+
+/* gets a sequence of bits out of a given value (value), according to a given length (length)
+   and ls_bit_number */
+#define MS_GET_BITS( value , ls_bit_number, length )			     ( ( ( value ) >> ( ls_bit_number ) ) & ( ( 1 << ( length ) ) - 1 ) )
+
+/* writes a sequence of bits (write_value) with a given length (length) to a given
+   value (value). the offset is according to ls_bit_number */
+#define MS_SET_BITS( value , ls_bit_number , length , write_value )  ( ( value ) &= ~ ( ( ( 1 << ( length ) ) - 1 ) << ( ls_bit_number ) ) , ( value ) |= ( ( write_value ) << ( ls_bit_number ) ) )
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Global variables definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Functions prototypes                                                       */
+/*                                                                            */
+/******************************************************************************/
+
+uint8_t f_convert_tx_pd_fifo_size_from_user_to_hw_format ( uint8_t xi_pd_fifo_size ) ;
+uint8_t f_convert_tx_pd_fifo_size_from_hw_to_user_format ( uint8_t xi_pd_fifo_size ) ;
+
+int32_t f_minimum_packet_size_is_valid ( uint8_t xi_minimum_packet_size ,
+                                                 uint8_t xi_packet_header_offset ) ;
+int32_t f_maximum_packet_size_is_valid ( uint16_t xi_maximum_packet_size ,
+                                                 uint8_t xi_packet_header_offset ,
+                                                 uint8_t xi_reassembly_offset_in_8_byte,
+                                                 uint8_t xi_ddr_buffer_size ) ;
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* API functions implementations                                              */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_bbh_tx_set_configuration                                       */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   BBH Driver - TX Set configuration                                        */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets configuration of the TX part of BBH block.            */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_port_index - Port index                                               */
+/*                                                                            */
+/*   xi_bbh_tx_configuration - BBH TX configuration.                          */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_BBH_ERROR - Return code                                       */
+/*     DRV_BBH_NO_ERROR - No error                                      */
+/*     DRV_BBH_INVALID_PORT_INDEX - Invalid port index                  */
+/*                                                                            */
+/******************************************************************************/
+DRV_BBH_ERROR fi_bl_drv_bbh_tx_set_configuration ( DRV_BBH_PORT_INDEX xi_port_index ,
+                                                          const DRV_BBH_TX_CONFIGURATION * xi_bbh_tx_configuration )
+{
+
+    BBH_TX_CONFIGURATIONS_BBCFG_TX tx_bbcfg_tx ;
+    BBH_TX_CONFIGURATIONS_BBCFG1_TX tx_bbcfg1_tx ;
+    BBH_TX_CONFIGURATIONS_DDRCFG_TX tx_ddrcfg_tx ;
+    BBH_TX_CONFIGURATIONS_HNBASE tx_hnbase ;
+    BBH_TX_CONFIGURATIONS_TASKLSB tx_tasklsb ;
+    BBH_TX_CONFIGURATIONS_TASKMSB tx_taskmsb ;
+    BBH_TX_CONFIGURATIONS_TASK8_39 tx_task8_39 ;
+    BBH_TX_CONFIGURATIONS_PDSIZE0_7 tx_pdsize0_7 ;
+    BBH_TX_CONFIGURATIONS_PDSIZE8_39 tx_pdsize8_39 ;
+    BBH_TX_CONFIGURATIONS_PDBASE0_3 tx_pdbase0_3 ;
+    BBH_TX_CONFIGURATIONS_PDBASE4_7 tx_pdbase4_7 ;
+    BBH_TX_CONFIGURATIONS_PDBASE8_39 tx_pdbase8_39 ;
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN tx_pd_byte_th_en ;
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH tx_pd_byte_th ;
+    BBH_TX_CONFIGURATIONS_DMACFG_TX tx_dmacfg_tx ;
+    BBH_TX_CONFIGURATIONS_SDMACFG_TX tx_sdmacfg_tx ;
+    BBH_TX_CONFIGURATIONS_RUNNERCFG tx_runnercfg ;
+    BBH_TX_CONFIGURATIONS_MDUMODE tx_mdumode ;
+    BBH_TX_CONFIGURATIONS_DDRTMBASE tx_ddrtmbase ;
+    BBH_TX_CONFIGURATIONS_EMAC1588 tx_emac1588 ;
+
+#if defined(DSL_63138) || defined(DSL_63148)
+    if ( xi_port_index != DRV_BBH_EMAC_0 &&
+         xi_port_index != DRV_BBH_EMAC_1 &&
+         xi_port_index != DRV_BBH_DSL)
+#else
+    if ( xi_port_index >= DRV_BBH_NUMBER_OF_PORTS )
+#endif         
+    {
+        return ( DRV_BBH_INVALID_PORT_INDEX ) ;
+    }
+
+    if ( ( xi_bbh_tx_configuration->multicast_header_size < DRV_BBH_MINIMAL_MULTICAST_HEADER_SIZE ) ||
+         ( xi_bbh_tx_configuration->multicast_header_size > DRV_BBH_MAXIMAL_MULTICAST_HEADER_SIZE ) )
+    {
+        return ( DRV_BBH_INVALID_MULTICAST_HEADER_SIZE ) ;
+    }
+
+    if ( ( xi_bbh_tx_configuration->pd_fifo_size_0 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_0 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_1 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_1 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_2 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_2 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_3 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_3 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_4 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_4 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_5 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_5 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_6 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_6 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_7 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_7 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_8_15 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_8_15 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_16_23 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_16_23 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_24_31 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_24_31 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_32_39 < DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_bbh_tx_configuration->pd_fifo_size_32_39 > DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE ) )
+    {
+        return ( DRV_BBH_INVALID_TX_PD_FIFO_SIZE ) ;
+    }
+
+    if ( ( xi_bbh_tx_configuration->pd_prefetch_byte_threshold_0_in_32_byte > DRV_BBH_TX_MAXIMAL_PD_PREFETCH_BYTE_THRESHOLD_IN_32_BYTE ) ||
+         ( xi_bbh_tx_configuration->pd_prefetch_byte_threshold_1_in_32_byte > DRV_BBH_TX_MAXIMAL_PD_PREFETCH_BYTE_THRESHOLD_IN_32_BYTE ) ||
+         ( xi_bbh_tx_configuration->pd_prefetch_byte_threshold_2_in_32_byte > DRV_BBH_TX_MAXIMAL_PD_PREFETCH_BYTE_THRESHOLD_IN_32_BYTE ) ||
+         ( xi_bbh_tx_configuration->pd_prefetch_byte_threshold_3_in_32_byte > DRV_BBH_TX_MAXIMAL_PD_PREFETCH_BYTE_THRESHOLD_IN_32_BYTE ) ||
+         ( xi_bbh_tx_configuration->pd_prefetch_byte_threshold_4_in_32_byte > DRV_BBH_TX_MAXIMAL_PD_PREFETCH_BYTE_THRESHOLD_IN_32_BYTE ) ||
+         ( xi_bbh_tx_configuration->pd_prefetch_byte_threshold_5_in_32_byte > DRV_BBH_TX_MAXIMAL_PD_PREFETCH_BYTE_THRESHOLD_IN_32_BYTE ) ||
+         ( xi_bbh_tx_configuration->pd_prefetch_byte_threshold_6_in_32_byte > DRV_BBH_TX_MAXIMAL_PD_PREFETCH_BYTE_THRESHOLD_IN_32_BYTE ) ||
+         ( xi_bbh_tx_configuration->pd_prefetch_byte_threshold_7_in_32_byte > DRV_BBH_TX_MAXIMAL_PD_PREFETCH_BYTE_THRESHOLD_IN_32_BYTE ) ||
+         ( xi_bbh_tx_configuration->pd_prefetch_byte_threshold_8_39_in_32_byte > DRV_BBH_TX_MAXIMAL_PD_PREFETCH_BYTE_THRESHOLD_IN_32_BYTE ) )
+    {
+        return ( DRV_BBH_INVALID_PD_PREFETCH_BYTE_THRESHOLD ) ;
+    }
+
+    if ( ( xi_bbh_tx_configuration->dma_read_requests_maximal_number < DRV_BBH_TX_MINIMAL_VALUE_FOR_DMA_READ_REQUESTS_MAXIMAL_NUMBER ) ||
+         ( xi_bbh_tx_configuration->dma_read_requests_maximal_number > DRV_BBH_TX_MAXIMAL_VALUE_FOR_DMA_READ_REQUESTS_MAXIMAL_NUMBER ) )
+    {
+        return ( DRV_BBH_INVALID_DMA_READ_REQUESTS_MAXIMAL_NUMBER ) ;
+    }
+
+    if ( ( xi_bbh_tx_configuration->sdma_read_requests_maximal_number < DRV_BBH_TX_MINIMAL_VALUE_FOR_SDMA_READ_REQUESTS_MAXIMAL_NUMBER ) ||
+         ( xi_bbh_tx_configuration->sdma_read_requests_maximal_number > DRV_BBH_TX_MAXIMAL_VALUE_FOR_SDMA_READ_REQUESTS_MAXIMAL_NUMBER ) )
+    {
+        return ( DRV_BBH_INVALID_SDMA_READ_REQUESTS_MAXIMAL_NUMBER ) ;
+    }
+
+
+    BBH_TX_CONFIGURATIONS_BBCFG_TX_READ( xi_port_index , tx_bbcfg_tx ) ;
+    tx_bbcfg_tx.dmaroute = xi_bbh_tx_configuration->dma_route_address ;
+    tx_bbcfg_tx.runnerroute = xi_bbh_tx_configuration->runner_route_address ;
+    tx_bbcfg_tx.bpmroute = xi_bbh_tx_configuration->bpm_route_address ;
+    BBH_TX_CONFIGURATIONS_BBCFG_TX_WRITE( xi_port_index , tx_bbcfg_tx ) ;
+
+    BBH_TX_CONFIGURATIONS_BBCFG1_TX_READ( xi_port_index , tx_bbcfg1_tx ) ;
+    tx_bbcfg1_tx.sdmaroute = xi_bbh_tx_configuration->sdma_route_address;
+    tx_bbcfg1_tx.sbpmroute = xi_bbh_tx_configuration->sbpm_route_address;
+    tx_bbcfg1_tx.rnrstsroute = xi_bbh_tx_configuration->runner_sts_route ;
+    BBH_TX_CONFIGURATIONS_BBCFG1_TX_WRITE( xi_port_index , tx_bbcfg1_tx ) ;
+
+    BBH_TX_CONFIGURATIONS_DDRCFG_TX_READ( xi_port_index , tx_ddrcfg_tx ) ;
+    tx_ddrcfg_tx.bufsize = xi_bbh_tx_configuration->ddr_buffer_size ;
+    tx_ddrcfg_tx.bpmmsg = xi_bbh_tx_configuration->ddr_bpm_message_format ;
+    tx_ddrcfg_tx.byteresul = xi_bbh_tx_configuration->payload_offset_resolution ;
+    tx_ddrcfg_tx.hnsize = xi_bbh_tx_configuration->multicast_header_size ;
+    BBH_TX_CONFIGURATIONS_DDRCFG_TX_WRITE( xi_port_index , tx_ddrcfg_tx ) ;
+
+    BBH_TX_CONFIGURATIONS_HNBASE_READ( xi_port_index , tx_hnbase ) ;
+    tx_hnbase.hnbase = xi_bbh_tx_configuration->multicast_headers_base_address_in_byte ;
+    BBH_TX_CONFIGURATIONS_HNBASE_WRITE( xi_port_index , tx_hnbase ) ;
+
+    BBH_TX_CONFIGURATIONS_TASKLSB_READ( xi_port_index , tx_tasklsb ) ;
+    tx_tasklsb.task0 = xi_bbh_tx_configuration->task_0 ;
+    tx_tasklsb.task1 = xi_bbh_tx_configuration->task_1 ;
+    tx_tasklsb.task2 = xi_bbh_tx_configuration->task_2 ;
+    tx_tasklsb.task3 = xi_bbh_tx_configuration->task_3 ;
+    BBH_TX_CONFIGURATIONS_TASKLSB_WRITE( xi_port_index , tx_tasklsb ) ;
+
+    BBH_TX_CONFIGURATIONS_TASKMSB_READ( xi_port_index , tx_taskmsb ) ;
+    tx_taskmsb.task4 = xi_bbh_tx_configuration->task_4 ;
+    tx_taskmsb.task5 = xi_bbh_tx_configuration->task_5 ;
+    tx_taskmsb.task6 = xi_bbh_tx_configuration->task_6 ;
+    tx_taskmsb.task7 = xi_bbh_tx_configuration->task_7 ;
+    BBH_TX_CONFIGURATIONS_TASKMSB_WRITE( xi_port_index , tx_taskmsb ) ;
+
+    BBH_TX_CONFIGURATIONS_TASK8_39_READ( xi_port_index , tx_task8_39 ) ;
+    tx_task8_39.task8_39 = xi_bbh_tx_configuration->task_8_39 ;
+    BBH_TX_CONFIGURATIONS_TASK8_39_WRITE( xi_port_index , tx_task8_39 ) ;
+
+    BBH_TX_CONFIGURATIONS_PDSIZE0_7_READ( xi_port_index , tx_pdsize0_7 ) ;
+    tx_pdsize0_7.fifosize0 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_0 ) ;
+    tx_pdsize0_7.fifosize1 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_1 ) ;
+    tx_pdsize0_7.fifosize2 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_2 ) ;
+    tx_pdsize0_7.fifosize3 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_3 ) ;
+    tx_pdsize0_7.fifosize4 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_4 ) ;
+    tx_pdsize0_7.fifosize5 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_5 ) ;
+    tx_pdsize0_7.fifosize6 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_6 ) ;
+    tx_pdsize0_7.fifosize7 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_7 ) ;
+    BBH_TX_CONFIGURATIONS_PDSIZE0_7_WRITE( xi_port_index , tx_pdsize0_7 ) ;
+
+    BBH_TX_CONFIGURATIONS_PDSIZE8_39_READ( xi_port_index , tx_pdsize8_39 ) ;
+    tx_pdsize8_39.fifosize8_15 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_8_15 ) ;
+    tx_pdsize8_39.fifosize16_23 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_16_23 ) ;
+    tx_pdsize8_39.fifosize24_31 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_24_31 ) ;
+    tx_pdsize8_39.fifosize32_39 = f_convert_tx_pd_fifo_size_from_user_to_hw_format ( xi_bbh_tx_configuration->pd_fifo_size_32_39 ) ;
+    BBH_TX_CONFIGURATIONS_PDSIZE8_39_WRITE( xi_port_index , tx_pdsize8_39 ) ;
+
+    BBH_TX_CONFIGURATIONS_PDBASE0_3_READ( xi_port_index , tx_pdbase0_3 ) ;
+    tx_pdbase0_3.fifobase0 = xi_bbh_tx_configuration->pd_fifo_base_0 ;
+    tx_pdbase0_3.fifobase1 = xi_bbh_tx_configuration->pd_fifo_base_1 ;
+    tx_pdbase0_3.fifobase2 = xi_bbh_tx_configuration->pd_fifo_base_2 ;
+    tx_pdbase0_3.fifobase3 = xi_bbh_tx_configuration->pd_fifo_base_3 ;
+    BBH_TX_CONFIGURATIONS_PDBASE0_3_WRITE( xi_port_index , tx_pdbase0_3 ) ;
+
+    BBH_TX_CONFIGURATIONS_PDBASE4_7_READ( xi_port_index , tx_pdbase4_7 ) ;
+    tx_pdbase4_7.fifobase4 = xi_bbh_tx_configuration->pd_fifo_base_4 ;
+    tx_pdbase4_7.fifobase5 = xi_bbh_tx_configuration->pd_fifo_base_5 ;
+    tx_pdbase4_7.fifobase6 = xi_bbh_tx_configuration->pd_fifo_base_6 ;
+    tx_pdbase4_7.fifobase7 = xi_bbh_tx_configuration->pd_fifo_base_7 ;
+    BBH_TX_CONFIGURATIONS_PDBASE4_7_WRITE( xi_port_index , tx_pdbase4_7 ) ;
+
+    BBH_TX_CONFIGURATIONS_PDBASE8_39_READ( xi_port_index , tx_pdbase8_39 ) ;
+    tx_pdbase8_39.fifobase8_15 = xi_bbh_tx_configuration->pd_fifo_base_8_15 ;
+    tx_pdbase8_39.fifobase16_23 = xi_bbh_tx_configuration->pd_fifo_base_16_23 ;
+    tx_pdbase8_39.fifobase24_31 = xi_bbh_tx_configuration->pd_fifo_base_24_31 ;
+    tx_pdbase8_39.fifobase32_39 = xi_bbh_tx_configuration->pd_fifo_base_32_39 ;
+    BBH_TX_CONFIGURATIONS_PDBASE8_39_WRITE( xi_port_index , tx_pdbase8_39 ) ;
+
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_READ( xi_port_index , tx_pd_byte_th_en ) ;
+    tx_pd_byte_th_en.pdlimiten = xi_bbh_tx_configuration->pd_prefetch_byte_threshold_enable ;
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_EN_WRITE( xi_port_index , tx_pd_byte_th_en ) ;
+
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_READ( xi_port_index , 0 , tx_pd_byte_th ) ;
+    tx_pd_byte_th.pdlimiteven = xi_bbh_tx_configuration->pd_prefetch_byte_threshold_0_in_32_byte ;
+    tx_pd_byte_th.pdlimitodd = xi_bbh_tx_configuration->pd_prefetch_byte_threshold_1_in_32_byte ;
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_WRITE( xi_port_index , 0 , tx_pd_byte_th ) ;
+
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_READ( xi_port_index , 1 , tx_pd_byte_th ) ;
+    tx_pd_byte_th.pdlimiteven = xi_bbh_tx_configuration->pd_prefetch_byte_threshold_2_in_32_byte ;
+    tx_pd_byte_th.pdlimitodd = xi_bbh_tx_configuration->pd_prefetch_byte_threshold_3_in_32_byte ;
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_WRITE( xi_port_index , 1 , tx_pd_byte_th ) ;
+
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_READ( xi_port_index , 2 , tx_pd_byte_th ) ;
+    tx_pd_byte_th.pdlimiteven = xi_bbh_tx_configuration->pd_prefetch_byte_threshold_4_in_32_byte ;
+    tx_pd_byte_th.pdlimitodd = xi_bbh_tx_configuration->pd_prefetch_byte_threshold_5_in_32_byte ;
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_WRITE( xi_port_index , 2 , tx_pd_byte_th ) ;
+
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_READ( xi_port_index , 3 , tx_pd_byte_th ) ;
+    tx_pd_byte_th.pdlimiteven = xi_bbh_tx_configuration->pd_prefetch_byte_threshold_6_in_32_byte ;
+    tx_pd_byte_th.pdlimitodd = xi_bbh_tx_configuration->pd_prefetch_byte_threshold_7_in_32_byte ;
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_WRITE( xi_port_index , 3 , tx_pd_byte_th ) ;
+
+    /* TCONTs 8-39 have a common configuration */
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_READ( xi_port_index , 4 , tx_pd_byte_th ) ;
+    tx_pd_byte_th.pdlimiteven = xi_bbh_tx_configuration->pd_prefetch_byte_threshold_8_39_in_32_byte ;
+    BBH_TX_CONFIGURATIONS_PD_BYTE_TH_WRITE( xi_port_index , 4 , tx_pd_byte_th ) ;
+
+    BBH_TX_CONFIGURATIONS_DMACFG_TX_READ( xi_port_index , tx_dmacfg_tx ) ;
+    tx_dmacfg_tx.descbase = xi_bbh_tx_configuration->dma_read_requests_fifo_base_address ;
+    tx_dmacfg_tx.maxreq = xi_bbh_tx_configuration->dma_read_requests_maximal_number ;
+    tx_dmacfg_tx.epnurgnt = xi_bbh_tx_configuration->epnurgnt ;
+    BBH_TX_CONFIGURATIONS_DMACFG_TX_WRITE( xi_port_index , tx_dmacfg_tx ) ;
+
+    BBH_TX_CONFIGURATIONS_SDMACFG_TX_READ( xi_port_index , tx_sdmacfg_tx ) ;
+    tx_sdmacfg_tx.descbase = xi_bbh_tx_configuration->sdma_read_requests_fifo_base_address ;
+    tx_sdmacfg_tx.maxreq = xi_bbh_tx_configuration->sdma_read_requests_maximal_number ;
+    BBH_TX_CONFIGURATIONS_SDMACFG_TX_WRITE( xi_port_index , tx_sdmacfg_tx ) ;
+
+    BBH_TX_CONFIGURATIONS_RUNNERCFG_READ( xi_port_index , tx_runnercfg ) ;
+    tx_runnercfg.tcontaddr = xi_bbh_tx_configuration->tcont_address_in_8_byte ;
+    tx_runnercfg.skbaddr = xi_bbh_tx_configuration->skb_address ;
+    BBH_TX_CONFIGURATIONS_RUNNERCFG_WRITE( xi_port_index , tx_runnercfg ) ;
+
+    BBH_TX_CONFIGURATIONS_MDUMODE_READ( xi_port_index , tx_mdumode ) ;
+    tx_mdumode.mduen = xi_bbh_tx_configuration->mdu_mode_enable ;
+    tx_mdumode.ptraddr = xi_bbh_tx_configuration->mdu_mode_read_pointer_address_in_8_byte ;
+    BBH_TX_CONFIGURATIONS_MDUMODE_WRITE( xi_port_index , tx_mdumode ) ;
+
+    BBH_TX_CONFIGURATIONS_DDRTMBASE_READ( xi_port_index , tx_ddrtmbase ) ;
+    tx_ddrtmbase.ddrtmbase = xi_bbh_tx_configuration->ddr_tm_base_address ;
+    BBH_TX_CONFIGURATIONS_DDRTMBASE_WRITE( xi_port_index , tx_ddrtmbase ) ;
+
+    BBH_TX_CONFIGURATIONS_EMAC1588_READ( xi_port_index , tx_emac1588 ) ;
+    tx_emac1588.emac1588 = xi_bbh_tx_configuration->emac_1588_enable ;
+    BBH_TX_CONFIGURATIONS_EMAC1588_WRITE( xi_port_index , tx_emac1588 ) ;
+
+    return ( DRV_BBH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_bbh_tx_set_configuration ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_bbh_rx_set_configuration                                       */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   BBH Driver - RX Set configuration                                        */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets configuration of the RX part of BBH block.            */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_port_index - Port index                                               */
+/*                                                                            */
+/*   xi_rx_configuration - RX configuration                                   */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_BBH_ERROR - Return code                                       */
+/*     DRV_BBH_NO_ERROR - No error                                      */
+/*     DRV_BBH_INVALID_PORT_INDEX - Invalid port index                  */
+/*                                                                            */
+/******************************************************************************/
+DRV_BBH_ERROR fi_bl_drv_bbh_rx_set_configuration ( DRV_BBH_PORT_INDEX xi_port_index ,
+                                                          const DRV_BBH_RX_CONFIGURATION * xi_rx_configuration )
+{
+    BBH_RX_GENERAL_CONFIGURATION_BBCFG rx_bbcfg ;
+    BBH_RX_GENERAL_CONFIGURATION_BBCFG1 rx_bbcfg1 ;
+    BBH_RX_GENERAL_CONFIGURATION_DDRCFG rx_ddrcfg ;
+    BBH_RX_GENERAL_CONFIGURATION_PDBASE rx_pdbase ;
+    BBH_RX_GENERAL_CONFIGURATION_PDSIZE rx_pdsize ;
+    BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK rx_runnertask ;
+    BBH_RX_GENERAL_CONFIGURATION_DMAADDR rx_dmaaddr ;
+    BBH_RX_GENERAL_CONFIGURATION_DMACFG rx_dmacfg ;
+    BBH_RX_GENERAL_CONFIGURATION_SDMAADDR rx_sdmaaddr ;
+    BBH_RX_GENERAL_CONFIGURATION_SDMACFG rx_sdmacfg ;
+    BBH_RX_GENERAL_CONFIGURATION_MINPKT0 rx_minpkt0 ;
+    BBH_RX_GENERAL_CONFIGURATION_MAXPKT0 rx_maxpkt0 ;
+    BBH_RX_GENERAL_CONFIGURATION_MAXPKT1 rx_maxpkt1 ;
+    BBH_RX_GENERAL_CONFIGURATION_IHCFG rx_ihcfg ;
+    BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH rx_perflowth ;
+    BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG rx_ploamcfg ;
+    BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET rx_reassemblyoffset ;
+    DRV_BBH_ERROR error_code ;
+
+#if defined(DSL_63138) || defined(DSL_63148)
+    if ( xi_port_index != DRV_BBH_EMAC_0 &&
+         xi_port_index != DRV_BBH_EMAC_1 &&
+         xi_port_index != DRV_BBH_DSL)
+#else
+    if ( xi_port_index >= DRV_BBH_NUMBER_OF_PORTS )
+#endif    
+    {
+        return ( DRV_BBH_INVALID_PORT_INDEX ) ;
+    }
+
+    if ( ( xi_rx_configuration->pd_fifo_size_normal_queue < DRV_BBH_RX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_rx_configuration->pd_fifo_size_normal_queue > DRV_BBH_RX_MAXIMAL_PD_FIFO_SIZE ) )
+    {
+        return ( DRV_BBH_INVALID_RX_PD_FIFO_SIZE ) ;
+    }
+
+    if ( ( xi_rx_configuration->pd_fifo_size_direct_queue < DRV_BBH_RX_MINIMAL_PD_FIFO_SIZE ) ||
+         ( xi_rx_configuration->pd_fifo_size_direct_queue > DRV_BBH_RX_MAXIMAL_PD_FIFO_SIZE ) )
+    {
+        return ( DRV_BBH_INVALID_RX_PD_FIFO_SIZE ) ;
+    }
+
+    if ( ( xi_rx_configuration->dma_data_and_chunk_descriptor_fifos_size < DRV_BBH_RX_MINIMAL_DMA_OR_SDMA_DATA_FIFO_SIZE ) ||
+         ( xi_rx_configuration->dma_data_and_chunk_descriptor_fifos_size > DRV_BBH_RX_MAXIMAL_DMA_OR_SDMA_DATA_FIFO_SIZE ) )
+    {
+        return ( DRV_BBH_INVALID_DMA_DATA_AND_CHUNK_DESCRIPTOR_FIFOS_SIZE ) ;
+    }
+
+    if ( ( xi_rx_configuration->dma_exclusive_threshold < DRV_BBH_RX_MINIMAL_DMA_OR_SDMA_DATA_FIFO_SIZE ) ||
+         ( xi_rx_configuration->dma_exclusive_threshold > DRV_BBH_RX_MAXIMAL_DMA_OR_SDMA_DATA_FIFO_SIZE ) )
+    {
+        return ( DRV_BBH_INVALID_DMA_EXCLUSIVE_THRESHOLD ) ;
+    }
+
+    if ( ( xi_rx_configuration->sdma_data_and_chunk_descriptor_fifos_size < DRV_BBH_RX_MINIMAL_DMA_OR_SDMA_DATA_FIFO_SIZE ) ||
+         ( xi_rx_configuration->sdma_data_and_chunk_descriptor_fifos_size > DRV_BBH_RX_MAXIMAL_DMA_OR_SDMA_DATA_FIFO_SIZE ) )
+    {
+        return ( DRV_BBH_INVALID_SDMA_DATA_AND_CHUNK_DESCRIPTOR_FIFOS_SIZE ) ;
+    }
+
+    if ( ( xi_rx_configuration->sdma_exclusive_threshold < DRV_BBH_RX_MINIMAL_DMA_OR_SDMA_DATA_FIFO_SIZE ) ||
+         ( xi_rx_configuration->sdma_exclusive_threshold > DRV_BBH_RX_MAXIMAL_DMA_OR_SDMA_DATA_FIFO_SIZE ) )
+    {
+        return ( DRV_BBH_INVALID_SDMA_EXCLUSIVE_THRESHOLD ) ;
+    }
+
+    if ( ( ! f_minimum_packet_size_is_valid ( xi_rx_configuration->minimum_packet_size_0 , xi_rx_configuration->packet_header_offset ) ) ||
+         ( ! f_minimum_packet_size_is_valid ( xi_rx_configuration->minimum_packet_size_1 , xi_rx_configuration->packet_header_offset ) ) ||
+         ( ! f_minimum_packet_size_is_valid ( xi_rx_configuration->minimum_packet_size_2 , xi_rx_configuration->packet_header_offset ) ) ||
+         ( ! f_minimum_packet_size_is_valid ( xi_rx_configuration->minimum_packet_size_3 , xi_rx_configuration->packet_header_offset ) ) )
+    {
+        return ( DRV_BBH_INVALID_MINIMUM_PACKET_SIZE ) ;
+    }
+
+    if ( ( ! f_maximum_packet_size_is_valid ( xi_rx_configuration->maximum_packet_size_0 ,
+                                              xi_rx_configuration->packet_header_offset ,
+                                              xi_rx_configuration->reassembly_offset_in_8_byte,
+                                              xi_rx_configuration->ddr_buffer_size ) ) ||
+         ( ! f_maximum_packet_size_is_valid ( xi_rx_configuration->maximum_packet_size_1 ,
+                                              xi_rx_configuration->packet_header_offset ,
+                                              xi_rx_configuration->reassembly_offset_in_8_byte,
+                                              xi_rx_configuration->ddr_buffer_size ) ) ||
+         ( ! f_maximum_packet_size_is_valid ( xi_rx_configuration->maximum_packet_size_2 ,
+                                              xi_rx_configuration->packet_header_offset ,
+                                              xi_rx_configuration->reassembly_offset_in_8_byte,
+                                              xi_rx_configuration->ddr_buffer_size ) ) ||
+         ( ! f_maximum_packet_size_is_valid ( xi_rx_configuration->maximum_packet_size_3 ,
+                                              xi_rx_configuration->packet_header_offset ,
+                                              xi_rx_configuration->reassembly_offset_in_8_byte,
+                                              xi_rx_configuration->ddr_buffer_size ) ) )
+    {
+        return ( DRV_BBH_INVALID_MAXIMUM_PACKET_SIZE ) ;
+    }
+
+    if ( xi_rx_configuration->packet_header_offset > DRV_BBH_RX_MAXIMAL_PACKET_HEADER_OFFSET )
+    {
+        return ( DRV_BBH_INVALID_PACKET_HEADER_OFFSET ) ;
+    }
+
+    if ( xi_rx_configuration->flows_32_255_group_divider < DRV_BBH_RX_MINIMAL_FLOWS_32_255_GROUP_DIVIDER )
+    {
+        return ( DRV_BBH_INVALID_FLOWS_32_255_GROUP_DIVIDER ) ;
+    }
+
+    if ( xi_rx_configuration->ploam_default_ih_class > DRV_BBH_RX_MAXIMAL_IH_CLASS )
+    {
+        return ( DRV_BBH_INVALID_IH_CLASS ) ;
+    }
+
+    if ( xi_rx_configuration->reassembly_offset_in_8_byte > DRV_BBH_RX_MAXIMAL_REASSEMBLY_OFFSET_IN_8_BYTE )
+    {
+        return ( DRV_BBH_INVALID_REASSEMBLY_OFFSET ) ;
+    }
+
+
+    BBH_RX_GENERAL_CONFIGURATION_BBCFG_READ( xi_port_index , rx_bbcfg ) ;
+    rx_bbcfg.runner0route = xi_rx_configuration->runner_0_route_address ;
+    rx_bbcfg.runner1route = xi_rx_configuration->runner_1_route_address ;
+    rx_bbcfg.dmaroute = xi_rx_configuration->dma_route_address ;
+    rx_bbcfg.bpmroute = xi_rx_configuration->bpm_route_address ;
+    BBH_RX_GENERAL_CONFIGURATION_BBCFG_WRITE( xi_port_index , rx_bbcfg ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_BBCFG1_READ( xi_port_index , rx_bbcfg1 ) ;
+    rx_bbcfg1.ihroute = xi_rx_configuration->ih_route_address ;
+    rx_bbcfg1.sdmaroute = xi_rx_configuration->sdma_route_address ;
+    rx_bbcfg1.sbpmroute = xi_rx_configuration->sbpm_route_address ;
+    BBH_RX_GENERAL_CONFIGURATION_BBCFG1_WRITE( xi_port_index , rx_bbcfg1 ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_DDRCFG_READ( xi_port_index , rx_ddrcfg ) ;
+    rx_ddrcfg.bufsize = xi_rx_configuration->ddr_buffer_size ;
+    rx_ddrcfg.bpmmsg = xi_rx_configuration->ddr_bpm_message_format ;
+    rx_ddrcfg.ddrtmbase = xi_rx_configuration->ddr_tm_base_address ;
+    BBH_RX_GENERAL_CONFIGURATION_DDRCFG_WRITE( xi_port_index , rx_ddrcfg ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_PDBASE_READ( xi_port_index , rx_pdbase ) ;
+    rx_pdbase.normal = xi_rx_configuration->pd_fifo_base_address_normal_queue_in_8_byte ;
+    rx_pdbase.direct = xi_rx_configuration->pd_fifo_base_address_direct_queue_in_8_byte ;
+    BBH_RX_GENERAL_CONFIGURATION_PDBASE_WRITE( xi_port_index , rx_pdbase ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_PDSIZE_READ( xi_port_index , rx_pdsize ) ;
+    rx_pdsize.normal = xi_rx_configuration->pd_fifo_size_normal_queue ;
+    rx_pdsize.direct = xi_rx_configuration->pd_fifo_size_direct_queue ;
+    BBH_RX_GENERAL_CONFIGURATION_PDSIZE_WRITE( xi_port_index , rx_pdsize ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_READ( xi_port_index , rx_runnertask ) ;
+    rx_runnertask.normal0 = xi_rx_configuration->runner_0_task_normal_queue ;
+    rx_runnertask.direct0 = xi_rx_configuration->runner_0_task_direct_queue ;
+    rx_runnertask.normal1 = xi_rx_configuration->runner_1_task_normal_queue ;
+    rx_runnertask.direct1 = xi_rx_configuration->runner_1_task_direct_queue ;
+    BBH_RX_GENERAL_CONFIGURATION_RUNNERTASK_WRITE( xi_port_index , rx_runnertask ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_DMAADDR_READ( xi_port_index , rx_dmaaddr ) ;
+    rx_dmaaddr.database = xi_rx_configuration->dma_data_fifo_base_address ;
+    rx_dmaaddr.descbase = xi_rx_configuration->dma_chunk_descriptor_fifo_base_address ;
+    BBH_RX_GENERAL_CONFIGURATION_DMAADDR_WRITE( xi_port_index , rx_dmaaddr ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_DMACFG_READ( xi_port_index , rx_dmacfg ) ;
+    rx_dmacfg.numofcd = xi_rx_configuration->dma_data_and_chunk_descriptor_fifos_size ;
+    rx_dmacfg.exclth = xi_rx_configuration->dma_exclusive_threshold ;
+    BBH_RX_GENERAL_CONFIGURATION_DMACFG_WRITE( xi_port_index , rx_dmacfg ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_READ( xi_port_index , rx_sdmaaddr ) ;
+    rx_sdmaaddr.database = xi_rx_configuration->sdma_data_fifo_base_address ;
+    rx_sdmaaddr.descbase = xi_rx_configuration->sdma_chunk_descriptor_fifo_base_address ;
+    BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_WRITE( xi_port_index , rx_sdmaaddr ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_SDMACFG_READ( xi_port_index , rx_sdmacfg ) ;
+    rx_sdmacfg.numofcd = xi_rx_configuration->sdma_data_and_chunk_descriptor_fifos_size ;
+    rx_sdmacfg.exclth = xi_rx_configuration->sdma_exclusive_threshold ;
+    BBH_RX_GENERAL_CONFIGURATION_SDMACFG_WRITE( xi_port_index , rx_sdmacfg ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_MINPKT0_READ( xi_port_index , rx_minpkt0 ) ;
+    rx_minpkt0.minpkt0 = xi_rx_configuration->minimum_packet_size_0 ;
+    rx_minpkt0.minpkt1 = xi_rx_configuration->minimum_packet_size_1 ;
+    rx_minpkt0.minpkt2 = xi_rx_configuration->minimum_packet_size_2 ;
+    rx_minpkt0.minpkt3 = xi_rx_configuration->minimum_packet_size_3 ;
+    BBH_RX_GENERAL_CONFIGURATION_MINPKT0_WRITE( xi_port_index , rx_minpkt0 ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_READ( xi_port_index , rx_maxpkt0 ) ;
+    rx_maxpkt0.maxpkt0 = xi_rx_configuration->maximum_packet_size_0 ;
+    rx_maxpkt0.maxpkt1 = xi_rx_configuration->maximum_packet_size_1 ;
+    BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_WRITE( xi_port_index , rx_maxpkt0 ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_READ( xi_port_index , rx_maxpkt1 ) ;
+    rx_maxpkt1.maxpkt2 = xi_rx_configuration->maximum_packet_size_2 ;
+    rx_maxpkt1.maxpkt3 = xi_rx_configuration->maximum_packet_size_3 ;
+    BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_WRITE( xi_port_index , rx_maxpkt1 ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_IHCFG_READ( xi_port_index , rx_ihcfg ) ;
+    rx_ihcfg.ihbufen = xi_rx_configuration->ih_ingress_buffers_bitmask ;
+    rx_ihcfg.sopoffset = xi_rx_configuration->packet_header_offset ;
+    BBH_RX_GENERAL_CONFIGURATION_IHCFG_WRITE( xi_port_index , rx_ihcfg ) ;
+
+
+    error_code = fi_bl_drv_bbh_rx_set_triggers_of_flow_control_and_drop ( xi_port_index ,
+                                                                                xi_rx_configuration->flow_control_triggers_bitmask ,
+                                                                                xi_rx_configuration->drop_triggers_bitmask ) ;
+    if ( error_code != DRV_BBH_NO_ERROR )
+    {
+        return ( error_code ) ;
+    }
+
+
+    BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_READ( xi_port_index , rx_perflowth ) ;
+    rx_perflowth.flowth = xi_rx_configuration->flows_32_255_group_divider ;
+    BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_WRITE( xi_port_index , rx_perflowth ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_READ( xi_port_index , rx_ploamcfg ) ;
+    rx_ploamcfg.ihclass = xi_rx_configuration->ploam_default_ih_class ;
+    rx_ploamcfg.ihoverride = xi_rx_configuration->ploam_ih_class_override ;
+    BBH_RX_GENERAL_CONFIGURATION_PLOAMCFG_WRITE( xi_port_index , rx_ploamcfg ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_READ( xi_port_index , rx_reassemblyoffset ) ;
+    rx_reassemblyoffset.offset = xi_rx_configuration->reassembly_offset_in_8_byte ;
+    BBH_RX_GENERAL_CONFIGURATION_REASSEMBLYOFFSET_WRITE( xi_port_index , rx_reassemblyoffset ) ;
+
+    return ( DRV_BBH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_bbh_rx_set_configuration ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_bbh_rx_set_triggers_of_flow_control_and_drop                   */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   BBH Driver - RX Set triggers for flow control and drop                   */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets triggers for sending flow control to MAC, and         */
+/*   triggers for dropping packets. For flow control, there are 3 possible    */
+/*   triggers: BPM is in exclusive state, SBPM is in exclusive state, Runner  */
+/*   request. For drop, there are 2 possible triggers: BPM is in exclusive    */
+/*   state, SBPM is in exclusive state. The triggers are turned on/off        */
+/*   according to the given bitmask. Values of the enumeration                */
+/*   DRV_BBH_RX_FLOW_CONTROL_TRIGGER should be ORed, as a        */
+/*   description of the desired triggers for flow control. Values of the      */
+/*   enumeration DRV_BBH_RX_DROP_TRIGGER should be ORed, as a    */
+/*   description of the desired triggers for drop.                            */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_port_index - Port index                                               */
+/*                                                                            */
+/*   xi_flow_control_triggers_bitmask - Flow control triggers bitmask         */
+/*                                                                            */
+/*   xi_drop_triggers_bitmask - Drop triggers bitmask                         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_BBH_ERROR - Return code                                       */
+/*     DRV_BBH_NO_ERROR - No error                                      */
+/*     DRV_BBH_INVALID_PORT_INDEX - Invalid port index                  */
+/*                                                                            */
+/******************************************************************************/
+DRV_BBH_ERROR fi_bl_drv_bbh_rx_set_triggers_of_flow_control_and_drop ( DRV_BBH_PORT_INDEX xi_port_index ,
+                                                                              uint8_t xi_flow_control_triggers_bitmask ,
+                                                                              uint8_t xi_drop_triggers_bitmask )
+{
+    BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL rx_flowctrl ;
+    int32_t flow_control_trigger_bpm_is_in_exclusive_state_enable ;
+    int32_t flow_control_trigger_sbpm_is_in_exclusive_state_enable ;
+    int32_t flow_control_trigger_runner_request_enable ;
+    int32_t drop_trigger_bpm_is_in_exclusive_state_enable ;
+    int32_t drop_trigger_sbpm_is_in_exclusive_state_enable ;
+
+#if defined(DSL_63138) || defined(DSL_63148)
+    if ( xi_port_index != DRV_BBH_EMAC_0 &&
+         xi_port_index != DRV_BBH_EMAC_1 &&
+         xi_port_index != DRV_BBH_DSL)
+#else
+    if ( xi_port_index >= DRV_BBH_NUMBER_OF_PORTS )
+#endif    
+    {
+        return ( DRV_BBH_INVALID_PORT_INDEX ) ;
+    }
+
+
+    if ( ( xi_flow_control_triggers_bitmask & DRV_BBH_RX_FLOW_CONTROL_TRIGGER_BPM_IS_IN_EXCLUSIVE_STATE ) == 0 )
+    {
+        flow_control_trigger_bpm_is_in_exclusive_state_enable =  0 ;
+    }
+    else
+    {
+        flow_control_trigger_bpm_is_in_exclusive_state_enable =  1 ;
+    }
+
+    if ( ( xi_flow_control_triggers_bitmask & DRV_BBH_RX_FLOW_CONTROL_TRIGGER_SBPM_IS_IN_EXCLUSIVE_STATE ) == 0 )
+    {
+        flow_control_trigger_sbpm_is_in_exclusive_state_enable =  0 ;
+    }
+    else
+    {
+        flow_control_trigger_sbpm_is_in_exclusive_state_enable =  1 ;
+    }
+
+    if ( ( xi_flow_control_triggers_bitmask & DRV_BBH_RX_FLOW_CONTROL_TRIGGER_RUNNER_REQUEST ) == 0 )
+    {
+        flow_control_trigger_runner_request_enable =  0 ;
+    }
+    else
+    {
+        flow_control_trigger_runner_request_enable =  1 ;
+    }
+
+
+    if ( ( xi_drop_triggers_bitmask & DRV_BBH_RX_DROP_TRIGGER_BPM_IS_IN_EXCLUSIVE_STATE ) == 0 )
+    {
+        drop_trigger_bpm_is_in_exclusive_state_enable =  0 ;
+    }
+    else
+    {
+        drop_trigger_bpm_is_in_exclusive_state_enable =  1 ;
+    }
+
+    if ( ( xi_drop_triggers_bitmask & DRV_BBH_RX_DROP_TRIGGER_SBPM_IS_IN_EXCLUSIVE_STATE ) == 0 )
+    {
+        drop_trigger_sbpm_is_in_exclusive_state_enable =  0 ;
+    }
+    else
+    {
+        drop_trigger_sbpm_is_in_exclusive_state_enable =  1 ;
+    }
+
+
+    BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_READ( xi_port_index , rx_flowctrl ) ;
+    rx_flowctrl.bpmen = flow_control_trigger_bpm_is_in_exclusive_state_enable ;
+    rx_flowctrl.sbpmen = flow_control_trigger_sbpm_is_in_exclusive_state_enable ;
+    rx_flowctrl.runneren = flow_control_trigger_runner_request_enable ;
+    rx_flowctrl.bpmdropen = drop_trigger_bpm_is_in_exclusive_state_enable ;
+    rx_flowctrl.sbpmdropen = drop_trigger_sbpm_is_in_exclusive_state_enable ;
+    BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_WRITE( xi_port_index , rx_flowctrl ) ;
+
+    return ( DRV_BBH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_bbh_rx_set_triggers_of_flow_control_and_drop ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_bbh_rx_set_per_flow_configuration                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   BBH Driver - RX Set per flow configuration                               */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets per-flow configuration in the RX part of BBH block.   */
+/*   Each one of flows 0-31 has its own configuration. Flows 32-255 are       */
+/*   divided into 2 groups (32 to x, x+1 to 255). Each group has its own      */
+/*   configuration. The groups-divider (x) is configured in "RX Set           */
+/*   configuration" API. In Ethernet case, only flow 0 is relevant.           */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_port_index - Port index                                               */
+/*                                                                            */
+/*   xi_flow_index - Flow index                                               */
+/*                                                                            */
+/*   xi_per_flow_configuration - Per flow configuration                       */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_BBH_ERROR - Return code                                       */
+/*     DRV_BBH_NO_ERROR - No error                                      */
+/*     DRV_BBH_INVALID_PORT_INDEX - Invalid port index                  */
+/*                                                                            */
+/******************************************************************************/
+DRV_BBH_ERROR fi_bl_drv_bbh_rx_set_per_flow_configuration ( DRV_BBH_PORT_INDEX xi_port_index ,
+                                                                   DRV_BBH_RX_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION xi_flow_index ,
+                                                                   const DRV_BBH_PER_FLOW_CONFIGURATION * xi_per_flow_configuration )
+{
+    BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS rx_perflowsets ;
+    BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0 rx_minpktsel ;
+    BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0 rx_maxpktsel ;
+    BBH_RX_GENERAL_CONFIGURATION_IHCLASS0 rx_ihclass ;
+    BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE rx_ihoverride ;
+
+
+#if defined(DSL_63138) || defined(DSL_63148)
+    if ( xi_port_index != DRV_BBH_EMAC_0 &&
+         xi_port_index != DRV_BBH_EMAC_1 &&
+         xi_port_index != DRV_BBH_DSL)
+#else
+    if ( xi_port_index >= DRV_BBH_NUMBER_OF_PORTS )
+#endif    
+    {
+        return ( DRV_BBH_INVALID_PORT_INDEX ) ;
+    }
+
+    if ( xi_flow_index > DRV_BBH_RX_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION_GROUP_1 )
+    {
+        return ( DRV_BBH_INVALID_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION ) ;
+    }
+
+    /* for Ethernet port, only flow 0 is relevant */
+    if ( xi_port_index != DRV_BBH_GPON
+#if defined(__OREN__)
+        && xi_port_index != DRV_BBH_EPON
+#endif
+        && xi_flow_index > 0 )
+    {
+        return ( DRV_BBH_ILLEGAL_FLOW_INDEX_FOR_ETHERNET_PORT ) ;
+    }
+
+    if ( xi_per_flow_configuration->minimum_packet_size_selection > DRV_BBH_RX_MAXIMAL_SELECTION_FOR_MINIMUM_OR_MAXIMUM_PACKET_SIZE )
+    {
+        return ( DRV_BBH_INVALID_MINIMUM_PACKET_SIZE_SELECTION ) ;
+    }
+
+    if ( xi_per_flow_configuration->maximum_packet_size_selection > DRV_BBH_RX_MAXIMAL_SELECTION_FOR_MINIMUM_OR_MAXIMUM_PACKET_SIZE )
+    {
+        return ( DRV_BBH_INVALID_MAXIMUM_PACKET_SIZE_SELECTION ) ;
+    }
+
+    if ( xi_per_flow_configuration->default_ih_class > DRV_BBH_RX_MAXIMAL_IH_CLASS )
+    {
+        return ( DRV_BBH_INVALID_IH_CLASS ) ;
+    }
+
+
+    /* if it is one of the two groups */
+    if ( xi_flow_index >= DRV_BBH_RX_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION_GROUP_0 )
+    {
+        BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_READ( xi_port_index , rx_perflowsets ) ;
+
+        switch ( xi_flow_index )
+        {
+        case DRV_BBH_RX_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION_GROUP_0:
+            rx_perflowsets.minpktsel0 = xi_per_flow_configuration->minimum_packet_size_selection ;
+            rx_perflowsets.maxpktsel0 = xi_per_flow_configuration->maximum_packet_size_selection ;
+            rx_perflowsets.ihclass0 = xi_per_flow_configuration->default_ih_class ;
+            rx_perflowsets.override0 = xi_per_flow_configuration->ih_class_override ;
+            break ;
+
+        case DRV_BBH_RX_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION_GROUP_1:
+            rx_perflowsets.minpktsel1 = xi_per_flow_configuration->minimum_packet_size_selection ;
+            rx_perflowsets.maxpktsel1 = xi_per_flow_configuration->maximum_packet_size_selection ;
+            rx_perflowsets.ihclass1 = xi_per_flow_configuration->default_ih_class ;
+            rx_perflowsets.override1 = xi_per_flow_configuration->ih_class_override ;
+            break ;
+        }
+
+        BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_WRITE( xi_port_index , rx_perflowsets ) ;
+
+        return ( DRV_BBH_NO_ERROR ) ;
+    }
+
+
+    /* if it is one of flows 0-31: */
+
+    /* minimum & maximum packet length selection */
+
+    /* flows 0-15 */
+    if ( xi_flow_index <= CS_RX_MAXIMAL_FLOW_INDEX_FOR_MINPKTSEL0_AND_MAXPKTSEL0_REGISTERS )
+    {
+        BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_READ( xi_port_index , rx_minpktsel ) ;
+        BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_READ( xi_port_index , rx_maxpktsel ) ;
+    }
+    /* flows 16-31 */
+    else
+    {
+        BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_READ( xi_port_index , rx_minpktsel ) ;
+        BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_READ( xi_port_index , rx_maxpktsel ) ;
+    }
+
+    MS_SET_BITS( rx_minpktsel.minpktsel ,
+                 ( xi_flow_index * CS_RX_FIELD_LENGTH_FOR_MINPKTSEL_AND_MAXPKTSEL_REGISTERS ) % CS_NUMBER_OF_BITS_IN_REGISTER ,
+                 CS_RX_FIELD_LENGTH_FOR_MINPKTSEL_AND_MAXPKTSEL_REGISTERS ,
+                 xi_per_flow_configuration->minimum_packet_size_selection ) ;
+
+    MS_SET_BITS( rx_maxpktsel.maxpktsel ,
+                 ( xi_flow_index * CS_RX_FIELD_LENGTH_FOR_MINPKTSEL_AND_MAXPKTSEL_REGISTERS ) % CS_NUMBER_OF_BITS_IN_REGISTER ,
+                 CS_RX_FIELD_LENGTH_FOR_MINPKTSEL_AND_MAXPKTSEL_REGISTERS ,
+                 xi_per_flow_configuration->maximum_packet_size_selection ) ;
+
+    /* flows 0-15 */
+    if ( xi_flow_index <= CS_RX_MAXIMAL_FLOW_INDEX_FOR_MINPKTSEL0_AND_MAXPKTSEL0_REGISTERS )
+    {
+
+        BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_WRITE( xi_port_index , rx_minpktsel ) ;
+
+        BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_WRITE( xi_port_index , rx_maxpktsel ) ;
+    }
+    /* flows 16-31 */
+    else
+    {
+
+        BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_WRITE( xi_port_index , rx_minpktsel ) ;
+
+        BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_WRITE( xi_port_index , rx_maxpktsel ) ;
+    }
+
+
+    /* default IH class */
+
+    /* flows 0-7 */
+    if ( xi_flow_index <= CS_RX_MAXIMAL_FLOW_INDEX_FOR_IHCLASS0_REGISTER )
+    {
+        BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_READ( xi_port_index , rx_ihclass ) ;
+    }
+    /* flows 8-15 */
+    else if ( xi_flow_index <= CS_RX_MAXIMAL_FLOW_INDEX_FOR_IHCLASS1_REGISTER )
+    {
+        BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_READ( xi_port_index , rx_ihclass ) ;
+    }
+    /* flows 16-23 */
+    else if ( xi_flow_index <= CS_RX_MAXIMAL_FLOW_INDEX_FOR_IHCLASS2_REGISTER )
+    {
+        BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_READ( xi_port_index , rx_ihclass ) ;
+    }
+    /* flows 24-31 */
+    else
+    {
+        BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_READ( xi_port_index , rx_ihclass ) ;
+    }
+
+
+    MS_SET_BITS( rx_ihclass.ihclass ,
+                 ( xi_flow_index * CS_RX_FIELD_LENGTH_FOR_IHCLASS_REGISTERS ) % CS_NUMBER_OF_BITS_IN_REGISTER ,
+                 CS_RX_FIELD_LENGTH_FOR_IHCLASS_REGISTERS ,
+                 xi_per_flow_configuration->default_ih_class ) ;
+
+    /* flows 0-7 */
+    if ( xi_flow_index <= CS_RX_MAXIMAL_FLOW_INDEX_FOR_IHCLASS0_REGISTER )
+    {
+        BBH_RX_GENERAL_CONFIGURATION_IHCLASS0_WRITE( xi_port_index , rx_ihclass ) ;
+
+    }
+    /* flows 8-15 */
+    else if ( xi_flow_index <= CS_RX_MAXIMAL_FLOW_INDEX_FOR_IHCLASS1_REGISTER )
+    {
+        BBH_RX_GENERAL_CONFIGURATION_IHCLASS1_WRITE( xi_port_index , rx_ihclass ) ;
+
+    }
+    /* flows 16-23 */
+    else if ( xi_flow_index <= CS_RX_MAXIMAL_FLOW_INDEX_FOR_IHCLASS2_REGISTER )
+    {
+        BBH_RX_GENERAL_CONFIGURATION_IHCLASS2_WRITE( xi_port_index , rx_ihclass ) ;
+
+    }
+    /* flows 24-31 */
+    else
+    {
+        BBH_RX_GENERAL_CONFIGURATION_IHCLASS3_WRITE( xi_port_index , rx_ihclass ) ;
+
+    }
+
+
+    /* IH class override */
+
+    BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_READ( xi_port_index , rx_ihoverride ) ;
+
+    MS_SET_BITS( rx_ihoverride.ihoverride ,
+                 xi_flow_index ,
+                 1 ,
+                 xi_per_flow_configuration->ih_class_override ) ;
+
+    BBH_RX_GENERAL_CONFIGURATION_IHOVERRIDE_WRITE( xi_port_index , rx_ihoverride ) ;
+
+
+    return ( DRV_BBH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_bbh_rx_set_per_flow_configuration ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Internal functions implementation                                          */
+/*                                                                            */
+/******************************************************************************/
+
+/* this function assumes that the input paramter is valid! */
+uint8_t f_convert_tx_pd_fifo_size_from_user_to_hw_format ( uint8_t xi_pd_fifo_size )
+{
+    return ( xi_pd_fifo_size - 1 ) ;
+}
+
+/* this function assumes that the input paramter is valid! */
+uint8_t f_convert_tx_pd_fifo_size_from_hw_to_user_format ( uint8_t xi_pd_fifo_size )
+{
+    return ( xi_pd_fifo_size + 1 ) ;
+}
+
+int32_t f_minimum_packet_size_is_valid ( uint8_t xi_minimum_packet_size ,
+                                                 uint8_t xi_packet_header_offset )
+{
+    if ( xi_minimum_packet_size > DRV_BBH_RX_MAXIMAL_VALUE_FOR_MINIMUM_PACKET_SIZE )
+    {
+        return (  0 ) ;
+    }
+
+    if ( xi_minimum_packet_size >= CS_DRV_BBH_RX_INGRESS_BUFFER_SIZE - xi_packet_header_offset )
+    {
+        return (  0 ) ;
+    }
+
+    return (  1 ) ;
+}
+
+
+int32_t f_maximum_packet_size_is_valid ( uint16_t xi_maximum_packet_size ,
+                                                 uint8_t xi_packet_header_offset ,
+                                                 uint8_t xi_reassembly_offset_in_8_byte,
+                                                 uint8_t xi_ddr_buffer_size )
+{
+    uint16_t ddr_buffer_size_in_byte;
+    uint16_t reassembly_offset_in_byte = xi_reassembly_offset_in_8_byte * 8 ;
+    
+    if ( xi_maximum_packet_size > DRV_BBH_RX_MAXIMAL_VALUE_FOR_MAXIMUM_PACKET_SIZE )
+    {
+        return (  0 ) ;
+    }
+
+    switch ( xi_ddr_buffer_size )
+    {
+    case DRV_BBH_DDR_BUFFER_SIZE_2_KB:
+    default:
+        ddr_buffer_size_in_byte = CS_DRV_BBH_RX_DDR_BUFFER_SIZE_2K;
+        break;
+    case DRV_BBH_DDR_BUFFER_SIZE_2_5_KB:
+        ddr_buffer_size_in_byte = CS_DRV_BBH_RX_DDR_BUFFER_SIZE_2_5K;
+        break;
+    case DRV_BBH_DDR_BUFFER_SIZE_4_KB:
+        ddr_buffer_size_in_byte = CS_DRV_BBH_RX_DDR_BUFFER_SIZE_4K;
+        break;
+    case DRV_BBH_DDR_BUFFER_SIZE_16_KB:
+        ddr_buffer_size_in_byte = CS_DRV_BBH_RX_DDR_BUFFER_SIZE_16K;
+        break;
+    }
+
+    if ( xi_maximum_packet_size > ddr_buffer_size_in_byte - xi_packet_header_offset - reassembly_offset_in_byte )
+    {
+        return (  0 ) ;
+    }
+
+    return (  1 ) ;
+}
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_drv_bbh.h b/arch/arm/mach-bcmbca/rdp/rdp_drv_bbh.h
new file mode 100755
index 0000000000..f03e8a2925
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_drv_bbh.h
@@ -0,0 +1,977 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/             
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This header file defines all datatypes and functions exported for the      */
+/* Lilac BBH driver.                                                          */
+/*                                                                            */
+/******************************************************************************/
+
+
+#ifndef DRV_BBH_H_INCLUDED
+#define DRV_BBH_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+
+#include "rdp_bbh.h"
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Error codes returned by BBH driver APIs                                    */
+/******************************************************************************/
+typedef enum
+{
+    DRV_BBH_NO_ERROR ,
+    DRV_BBH_INVALID_PORT_INDEX ,
+    DRV_BBH_INVALID_MULTICAST_HEADER_SIZE ,
+    DRV_BBH_INVALID_TX_PD_FIFO_SIZE ,
+    DRV_BBH_INVALID_PD_PREFETCH_BYTE_THRESHOLD ,
+    DRV_BBH_INVALID_DMA_READ_REQUESTS_MAXIMAL_NUMBER ,
+    DRV_BBH_INVALID_SDMA_READ_REQUESTS_MAXIMAL_NUMBER ,
+    DRV_BBH_INVALID_RX_PD_FIFO_SIZE ,
+    DRV_BBH_INVALID_DMA_DATA_AND_CHUNK_DESCRIPTOR_FIFOS_SIZE ,
+    DRV_BBH_INVALID_DMA_EXCLUSIVE_THRESHOLD ,
+    DRV_BBH_INVALID_SDMA_DATA_AND_CHUNK_DESCRIPTOR_FIFOS_SIZE ,
+    DRV_BBH_INVALID_SDMA_EXCLUSIVE_THRESHOLD ,
+    DRV_BBH_INVALID_MINIMUM_PACKET_SIZE ,
+    DRV_BBH_INVALID_MAXIMUM_PACKET_SIZE ,
+    DRV_BBH_INVALID_PACKET_HEADER_OFFSET ,
+    DRV_BBH_INVALID_FLOWS_32_255_GROUP_DIVIDER ,
+    DRV_BBH_INVALID_IH_CLASS ,
+    DRV_BBH_INVALID_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION ,
+    DRV_BBH_ILLEGAL_FLOW_INDEX_FOR_ETHERNET_PORT ,
+    DRV_BBH_INVALID_MINIMUM_PACKET_SIZE_SELECTION ,
+    DRV_BBH_INVALID_MAXIMUM_PACKET_SIZE_SELECTION ,
+    DRV_BBH_INVALID_REASSEMBLY_OFFSET ,
+    DRV_BBH_API_IS_FOR_GPON_PORT_ONLY,
+    DRV_BBH_TCONT_ID_IS_OUT_OF_RANGE
+}
+DRV_BBH_ERROR ;
+
+/* Minimal Multicast header size */
+#define DRV_BBH_MINIMAL_MULTICAST_HEADER_SIZE                                  ( 4 )
+/* Maximal Multicast header size */                                           
+#define DRV_BBH_MAXIMAL_MULTICAST_HEADER_SIZE                                  ( 64 )
+                                                                              
+/* Minimal PD FIFO size in TX */                                              
+#define DRV_BBH_TX_MINIMAL_PD_FIFO_SIZE                                        ( 1 )
+/* Maximal PD FIFO size in TX */                                              
+#define DRV_BBH_TX_MAXIMAL_PD_FIFO_SIZE                                        ( 8 )
+
+/* Maximal PD prefetch byte threshold, in 32 byte resolution */
+#define DRV_BBH_TX_MAXIMAL_PD_PREFETCH_BYTE_THRESHOLD_IN_32_BYTE               ( 4095 )
+
+/* Minimal value for DMA read requests maximal number */
+#define DRV_BBH_TX_MINIMAL_VALUE_FOR_DMA_READ_REQUESTS_MAXIMAL_NUMBER          ( 1 )
+/* Maximal value for DMA read requests maximal number */
+#define DRV_BBH_TX_MAXIMAL_VALUE_FOR_DMA_READ_REQUESTS_MAXIMAL_NUMBER          ( 8 )
+
+/* Minimal value for SDMA read requests maximal number */
+#define DRV_BBH_TX_MINIMAL_VALUE_FOR_SDMA_READ_REQUESTS_MAXIMAL_NUMBER         ( 1 )
+/* Maximal value for SDMA read requests maximal number */
+#define DRV_BBH_TX_MAXIMAL_VALUE_FOR_SDMA_READ_REQUESTS_MAXIMAL_NUMBER         ( 4 )
+
+
+/* Minimal PD FIFO size in RX */
+#define DRV_BBH_RX_MINIMAL_PD_FIFO_SIZE                                        ( 2 )
+/* Maximal PD FIFO size in RX */
+#define DRV_BBH_RX_MAXIMAL_PD_FIFO_SIZE                                        ( 64 )
+
+/* Minimal DMA/SDMA data FIFO size */
+#define DRV_BBH_RX_MINIMAL_DMA_OR_SDMA_DATA_FIFO_SIZE                          ( 2 )
+/* Maximal DMA/SDMA data FIFO size */
+#define DRV_BBH_RX_MAXIMAL_DMA_OR_SDMA_DATA_FIFO_SIZE                          ( 64 )
+
+/* Maximal value for minimum packet size in RX */
+#define DRV_BBH_RX_MAXIMAL_VALUE_FOR_MINIMUM_PACKET_SIZE                       ( 96 )
+
+/* Maximal value for maximum packet size in RX */
+#define DRV_BBH_RX_MAXIMAL_VALUE_FOR_MAXIMUM_PACKET_SIZE                       ( 16383 )
+
+/* Maximal packet header offset */
+#define DRV_BBH_RX_MAXIMAL_PACKET_HEADER_OFFSET                                ( 63 )
+
+/* Number of Flows */
+#define DRV_BBH_RX_NUMBER_OF_FLOWS                                             ( 256 )
+
+/* Minimal Flows 32-255 group divider */
+#define DRV_BBH_RX_MINIMAL_FLOWS_32_255_GROUP_DIVIDER                          ( 32 )
+
+/* Maximal IH class */
+#define DRV_BBH_RX_MAXIMAL_IH_CLASS                                            ( 15 )
+
+/* Maximal selection for minimum or maximum packet size */
+#define DRV_BBH_RX_MAXIMAL_SELECTION_FOR_MINIMUM_OR_MAXIMUM_PACKET_SIZE        ( 3 )
+
+/* Maximal reassembly offset (in 8 byte resolution) */
+#define DRV_BBH_RX_MAXIMAL_REASSEMBLY_OFFSET_IN_8_BYTE                         ( 50 )
+
+
+/******************************************************************************/
+/* BBH Port index: there are 7 instances of the BBH block. BBH 0-5 refer to   */
+/* EMAC 0-5 and BBH 6 refers to GPON (EMAC 5 is the one MUXed with GPON).     */
+/******************************************************************************/
+typedef enum
+{
+    DRV_BBH_EMAC_0 ,
+    DRV_BBH_EMAC_1 ,
+    DRV_BBH_EMAC_2 ,
+    DRV_BBH_EMAC_3 ,
+    DRV_BBH_EMAC_4 ,
+    DRV_BBH_EMAC_5 ,
+    DRV_BBH_GPON ,
+    DRV_BBH_DSL = DRV_BBH_GPON ,
+    DRV_BBH_EPON,
+    DRV_BBH_NUMBER_OF_PORTS
+}
+DRV_BBH_PORT_INDEX ;
+
+
+/******************************************************************************/
+typedef enum
+{
+    DRV_BBH_DDR_BPM_MESSAGE_FORMAT_14_BIT_BN_WIDTH ,
+    DRV_BBH_DDR_BPM_MESSAGE_FORMAT_15_BIT_BN_WIDTH
+}
+DRV_BBH_DDR_BPM_MESSAGE_FORMAT ;
+/* DDR buffer size                                                            */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_BBH_DDR_BUFFER_SIZE_2_KB ,
+    DRV_BBH_DDR_BUFFER_SIZE_4_KB ,
+    DRV_BBH_DDR_BUFFER_SIZE_16_KB ,
+    DRV_BBH_DDR_BUFFER_SIZE_2_5_KB
+}
+DRV_BBH_DDR_BUFFER_SIZE ;
+
+
+/******************************************************************************/
+/* Payload offset resolution                                                  */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_BBH_PAYLOAD_OFFSET_RESOLUTION_1_B ,
+    DRV_BBH_PAYLOAD_OFFSET_RESOLUTION_2_B
+}
+DRV_BBH_PAYLOAD_OFFSET_RESOLUTION ;
+
+
+/******************************************************************************/
+/* BBH TX internal units                                                      */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_BBH_TX_INTERNAL_UNIT_SEGMENTATION_CONTEXT_TABLE = 1 << 0 ,
+    DRV_BBH_TX_INTERNAL_UNIT_ALL_40_PDS_FIFOS = 1 << 1 ,
+    DRV_BBH_TX_INTERNAL_UNIT_WRITE_POINTER_IN_THE_DMA = 1 << 2 ,
+    DRV_BBH_TX_INTERNAL_UNIT_WRITE_POINTER_IN_THE_SDMA = 1 << 3 ,
+    DRV_BBH_TX_INTERNAL_UNIT_BPM_RELEASE_FIFO = 1 << 4 ,
+    DRV_BBH_TX_INTERNAL_UNIT_SBPM_RELEASE_FIFO = 1 << 5 ,
+    DRV_BBH_TX_INTERNAL_UNIT_ORDER_KEEPER_FIFO = 1 << 6 ,
+    DRV_BBH_TX_INTERNAL_UNIT_DDR_DATA_FIFO = 1 << 7 ,
+    DRV_BBH_TX_INTERNAL_UNIT_SRAM_DATA_FIFO = 1 << 8 ,
+    DRV_BBH_TX_INTERNAL_UNIT_SKB_POINTERS = 1 << 9
+}
+DRV_BBH_TX_INTERNAL_UNIT ;
+
+
+/******************************************************************************/
+/* Flow control triggers                                                      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_BBH_RX_FLOW_CONTROL_TRIGGER_BPM_IS_IN_EXCLUSIVE_STATE = 1 << 0 ,
+    DRV_BBH_RX_FLOW_CONTROL_TRIGGER_SBPM_IS_IN_EXCLUSIVE_STATE = 1 << 1 ,
+    DRV_BBH_RX_FLOW_CONTROL_TRIGGER_RUNNER_REQUEST = 1 << 2 ,
+}
+DRV_BBH_RX_FLOW_CONTROL_TRIGGER ;
+
+
+/******************************************************************************/
+/* Drop triggers                                                              */
+/******************************************************************************/
+typedef enum
+{
+    DRV_BBH_RX_DROP_TRIGGER_BPM_IS_IN_EXCLUSIVE_STATE = 1 << 0 ,
+    DRV_BBH_RX_DROP_TRIGGER_SBPM_IS_IN_EXCLUSIVE_STATE = 1 << 1 ,
+}
+DRV_BBH_RX_DROP_TRIGGER ;
+
+
+/******************************************************************************/
+/* Flow index for per flow configuration:                                     */
+/* Each one of flows 0-31 has its own configuration. Flows 32-255 are divided */
+/* into 2 groups (32 to x, x+1 to 255). Each group has its own configuration. */
+/* The groups-divider (x) is configured in "RX Set configuration" API.        */
+/* The allowed values for this type are: 0-31,                                */
+/* DRV_BBH_RX_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION_GROUP_0,      */
+/* DRV_BBH_RX_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION_GROUP_1       */
+/******************************************************************************/
+typedef uint8_t DRV_BBH_RX_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION ;
+#define DRV_BBH_RX_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION_GROUP_0    ( 32 )
+#define DRV_BBH_RX_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION_GROUP_1    ( 33 )
+
+
+/******************************************************************************/
+/* BBH RX internal units                                                      */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_BBH_RX_INTERNAL_UNIT_INPUT_BUFFER = 1 << 0 ,
+    DRV_BBH_RX_INTERNAL_UNIT_BURST_BUFFER = 1 << 1 ,
+    DRV_BBH_RX_INTERNAL_UNIT_IH_CONTEXT = 1 << 2 ,
+    DRV_BBH_RX_INTERNAL_UNIT_IH_BUFFER_ENABLE = 1 << 3 ,
+    DRV_BBH_RX_INTERNAL_UNIT_REASSEMBLY_FIFO = 1 << 4 ,
+    DRV_BBH_RX_INTERNAL_UNIT_BPM_FIFO = 1 << 5 ,
+    DRV_BBH_RX_INTERNAL_UNIT_SBPM_FIFO = 1 << 6 ,
+    DRV_BBH_RX_INTERNAL_UNIT_IH_RESPONSE_FIFO = 1 << 7 ,
+    DRV_BBH_RX_INTERNAL_UNIT_PRE_WAKEUP_FIFO = 1 << 8 ,
+    DRV_BBH_RX_INTERNAL_UNIT_REASSEMBLY_CONTEXT_TABLE = 1 << 9 ,
+    DRV_BBH_RX_INTERNAL_UNIT_DMA_WRITE_POINTER = 1 << 10 ,
+    DRV_BBH_RX_INTERNAL_UNIT_SDMA_WRITE_POINTER = 1 << 11 ,
+    DRV_BBH_RX_INTERNAL_UNIT_RUNNER_WRITE_POINTER = 1 << 12
+}
+DRV_BBH_RX_INTERNAL_UNIT ;
+
+
+/******************************************************************************/
+/* TX configuration                                                           */
+/******************************************************************************/
+typedef struct
+{
+    /* DMA route address. */
+    uint8_t dma_route_address ;
+
+    /* BPM route address. */
+    uint8_t bpm_route_address ;
+
+    /* SDMA route address. */
+    uint8_t sdma_route_address ;
+
+    /* SBPM route address. */
+    uint8_t sbpm_route_address ;
+
+    /* Runner route address. */
+    uint8_t runner_route_address ;
+
+    /* Runner route address. */
+	uint8_t runner_sts_route ;
+
+    /* The data is arranged in the DDR in a fixed size buffers. */
+    DRV_BBH_DDR_BUFFER_SIZE ddr_buffer_size ;
+
+    DRV_BBH_DDR_BPM_MESSAGE_FORMAT ddr_bpm_message_format ;
+    /* The payload offset itself is indicated in the PD sent from runner to
+       BBH. */
+    DRV_BBH_PAYLOAD_OFFSET_RESOLUTION payload_offset_resolution ;
+
+    /* Multicast header size. */
+    uint8_t multicast_header_size ;
+
+    /* Multicast headers base address, in byte resolution. This base address
+       should be aligned to 512 bytes, therefore the 9 LSB bits are always
+       zero (and will be ignored). The address is relative to DDR TM base. */
+    uint32_t multicast_headers_base_address_in_byte ;
+
+    /* Runner task to be woken up, per TCONT. In Ethernet case, only Task 0
+       is relevant. */
+    uint8_t task_0 ;
+
+    /* Runner task to be woken up, per TCONT. In Ethernet case, only Task 0
+       is relevant. */
+    uint8_t task_1 ;
+
+    /* Runner task to be woken up, per TCONT. In Ethernet case, only Task 0
+       is relevant. */
+    uint8_t task_2 ;
+
+    /* Runner task to be woken up, per TCONT. In Ethernet case, only Task 0
+       is relevant. */
+    uint8_t task_3 ;
+
+    /* Runner task to be woken up, per TCONT. In Ethernet case, only Task 0
+       is relevant. */
+    uint8_t task_4 ;
+
+    /* Runner task to be woken up, per TCONT. In Ethernet case, only Task 0
+       is relevant. */
+    uint8_t task_5 ;
+
+    /* Runner task to be woken up, per TCONT. In Ethernet case, only Task 0
+       is relevant. */
+    uint8_t task_6 ;
+
+    /* Runner task to be woken up, per TCONT. In Ethernet case, only Task 0
+       is relevant. */
+    uint8_t task_7 ;
+
+    /* Runner task to be woken up, for TCONTs 8-39. In Ethernet case, only
+       Task 0 is relevant. */
+    uint8_t task_8_39 ;
+
+    /* PD FIFO size, per TCONT. A total of 128 PDs is available for all
+       queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_0 ;
+
+    /* PD FIFO size, per TCONT. A total of 128 PDs is available for all
+       queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_1 ;
+
+    /* PD FIFO size, per TCONT. A total of 128 PDs is available for all
+       queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_2 ;
+
+    /* PD FIFO size, per TCONT. A total of 128 PDs is available for all
+       queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_3 ;
+
+    /* PD FIFO size, per TCONT. A total of 128 PDs is available for all
+       queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_4 ;
+
+    /* PD FIFO size, per TCONT. A total of 128 PDs is available for all
+       queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_5 ;
+
+    /* PD FIFO size, per TCONT. A total of 128 PDs is available for all
+       queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_6 ;
+
+    /* PD FIFO size, per TCONT. A total of 128 PDs is available for all
+       queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_7 ;
+
+    /* PD FIFO size, for TCONTs 8-15. A total of 128 PDs is available for all
+       queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_8_15 ;
+
+    /* PD FIFO size, for TCONTs 16-23. A total of 128 PDs is available for
+       all queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_16_23 ;
+
+    /* PD FIFO size, for TCONTs 24-31. A total of 128 PDs is available for
+       all queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_24_31 ;
+
+    /* PD FIFO size, for TCONTs 32-39. A total of 128 PDs is available for
+       all queues. For Ethernet, queue 0 should be configured. */
+    uint8_t pd_fifo_size_32_39 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_0 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_1 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_2 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_3 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_4 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_5 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_6 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_7 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_8_15 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_16_23 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_24_31 ;
+
+    /* Base within the 128 PDs array. Should correspond to the FIFOs sizes
+       configuration. */
+    uint8_t pd_fifo_base_32_39 ;
+
+    /* PD prefetch byte threshold enable (for preventing HOL blocking). */
+    int32_t pd_prefetch_byte_threshold_enable ;
+
+    /* PD prefetch byte threshold (in 32 byte resolution), per TCONT.
+       Relevant if "PD prefetch byte threshold enable" is set. */
+    uint16_t pd_prefetch_byte_threshold_0_in_32_byte ;
+
+    /* PD prefetch byte threshold (in 32 byte resolution), per TCONT.
+       Relevant if "PD prefetch byte threshold enable" is set. */
+    uint16_t pd_prefetch_byte_threshold_1_in_32_byte ;
+
+    /* PD prefetch byte threshold (in 32 byte resolution), per TCONT.
+       Relevant if "PD prefetch byte threshold enable" is set. */
+    uint16_t pd_prefetch_byte_threshold_2_in_32_byte ;
+
+    /* PD prefetch byte threshold (in 32 byte resolution), per TCONT.
+       Relevant if "PD prefetch byte threshold enable" is set. */
+    uint16_t pd_prefetch_byte_threshold_3_in_32_byte ;
+
+    /* PD prefetch byte threshold (in 32 byte resolution), per TCONT.
+       Relevant if "PD prefetch byte threshold enable" is set. */
+    uint16_t pd_prefetch_byte_threshold_4_in_32_byte ;
+
+    /* PD prefetch byte threshold (in 32 byte resolution), per TCONT.
+       Relevant if "PD prefetch byte threshold enable" is set. */
+    uint16_t pd_prefetch_byte_threshold_5_in_32_byte ;
+
+    /* PD prefetch byte threshold (in 32 byte resolution), per TCONT.
+       Relevant if "PD prefetch byte threshold enable" is set. */
+    uint16_t pd_prefetch_byte_threshold_6_in_32_byte ;
+
+    /* PD prefetch byte threshold (in 32 byte resolution), per TCONT.
+       Relevant if "PD prefetch byte threshold enable" is set. */
+    uint16_t pd_prefetch_byte_threshold_7_in_32_byte ;
+
+    /* PD prefetch byte threshold (in 32 byte resolution), for TCONTs 8-39.
+       Relevant if "PD prefetch byte threshold enable" is set. */
+    uint16_t pd_prefetch_byte_threshold_8_39_in_32_byte ;
+
+    /* This value should be identical to the relevant configuration in the
+       DMA. */
+    uint8_t dma_read_requests_fifo_base_address ;
+
+    /* DMA read requests maximal number. */
+    uint8_t dma_read_requests_maximal_number ;
+
+  	/* Epon_read_urgent */
+    uint8_t epnurgnt ;
+
+    /* The value should be identical to the relevant configuration in the
+       SDMA. */
+    uint8_t sdma_read_requests_fifo_base_address ;
+
+    /* SDMA read requests maximal number */
+    uint8_t sdma_read_requests_maximal_number ;
+
+    /* Defines the TCONT address within the Runner address space. The address
+       is in 8 bytes resolution. In GPON case, the BBH writes the relevant
+       TCONT number into this address before sending a wake-up request to the
+       Runner, for requesting a PD. */
+    uint16_t tcont_address_in_8_byte ;
+
+    /* When the packet is transmitted from absolute address, instead of
+       releasing the BN, the BBH writes a 6 bits read counter into the Runner
+       SRAM. It writes it into a pre-defined address + TCONT_NUM. This value
+       defines the SKB free base address within the Runner address. */
+    uint16_t skb_address ;
+
+    /* In MDU mode, the runner pushes PDs to BBH without any wakeups from the
+       BBH. Despite its name, this mode may be used in SFU case as well. */
+    int32_t mdu_mode_enable ;
+
+    /* In MDU mode, Each time that the BBH reads a PD from the PD FIFO, it'll
+       write the read pointer into this address (in the Runner). The address
+       is in 8-bytes resolution. */
+    uint16_t mdu_mode_read_pointer_address_in_8_byte ;
+
+    /* The address is in bytes resolution. Should be aligned to 128 bytes.
+       Should match the relevant registers value in the BBH RX and in the
+       Runner. */
+    uint32_t ddr_tm_base_address ;
+
+    /* When this bit is set, the BBH will wait till the EMAC FIFO is empty
+       before issuing a DMA read command (of a 1588 packet only). This
+       configuration is relevant for Ethernet only. */
+    int32_t emac_1588_enable ;
+}
+DRV_BBH_TX_CONFIGURATION ;
+
+
+/******************************************************************************/
+/* TX Counters                                                                */
+/******************************************************************************/
+typedef struct
+{
+    /* This counter counts the number of packets which were transmitted from
+       the SRAM. This counter is relevant for Ethernet only. */
+    uint32_t tx_packets_from_sram ;
+
+    /* This counter counts the number of packets which were transmitted from
+       the DDR. It counts the packets for all TCONTs together. */
+    uint32_t tx_packets_from_ddr ;
+
+    /* This counter counts the number of PDs which were dropped due to PD
+       FIFO full. This counter is relevant for Ethernet only. */
+    uint16_t dropped_pd ;
+
+    /* This counter counts the number of PDs with packet length equal zero.
+       It counts the packets for all TCONTs together. */
+    uint16_t pd_with_zero_packet_length ;
+
+    /* This counter counts the number Get next responses with a null BN. This
+       counter is relevant for Ethernet only. */
+    uint16_t get_next_null ;
+}
+DRV_BBH_TX_COUNTERS ;
+
+
+/******************************************************************************/
+/* RX configuration                                                           */
+/******************************************************************************/
+typedef struct
+{
+    /* DMA route address. */
+    uint8_t dma_route_address ;
+
+    /* BPM route address. */
+    uint8_t bpm_route_address ;
+
+    /* SDMA route address. */
+    uint8_t sdma_route_address ;
+
+    /* SBPM route address. */
+    uint8_t sbpm_route_address ;
+
+    /* Runner 0 route address. */
+    uint8_t runner_0_route_address ;
+
+    /* Runner 1 route address. */
+    uint8_t runner_1_route_address ;
+
+    /* IH route address. */
+    uint8_t ih_route_address ;
+
+    /* The data is arranged in the DDR in a fixed size buffers. */
+    DRV_BBH_DDR_BUFFER_SIZE ddr_buffer_size ;
+
+    DRV_BBH_DDR_BPM_MESSAGE_FORMAT ddr_bpm_message_format ;
+    /* The address is in bytes resolution. Should be aligned to 128 bytes.
+       Should match the relevant registers value in the BBH TX and in the
+       Runner. */
+    uint32_t ddr_tm_base_address ;
+
+    /* For every reassembled packet in the DDR the BBH writes a packet
+       descriptor (PD) into the Runner. The PDs are arranged in a predefined
+       address space in the Runner SRAM and managed in a cyclic FIFO style.
+       The address is in 8-byte resolution. Same configuration for both
+       Runner 0 and 1. */
+    uint16_t pd_fifo_base_address_normal_queue_in_8_byte ;
+
+    /* The address is in 8-byte resolution. Same configuration for both
+       Runner 0 and 1. */
+    uint16_t pd_fifo_base_address_direct_queue_in_8_byte ;
+
+    /* Same configuration for both Runner 0 and 1. This value should be
+       identical to the number of RIBs (runner ingress buffers) configuration
+       in the IH block. */
+    uint8_t pd_fifo_size_normal_queue ;
+
+    /* Same configuration for both Runner 0 and 1. This value should be
+       identical to the number of IH ingress buffers configuration in the IH
+       block. */
+    uint8_t pd_fifo_size_direct_queue ;
+
+    /* For every PD written into the Runner, the BBH wakes the relevant
+       task. */
+    uint8_t runner_0_task_normal_queue ;
+
+    /* For every PD written into the Runner, the BBH wakes the relevant
+       task. */
+    uint8_t runner_0_task_direct_queue ;
+
+    /* For every PD written into the Runner, the BBH wakes the relevant
+       task. */
+    uint8_t runner_1_task_normal_queue ;
+
+    /* For every PD written into the Runner, the BBH wakes the relevant
+       task. */
+    uint8_t runner_1_task_direct_queue ;
+
+    /* The address is in chunk resolution (128 bytes). The value should be
+       identical to the relevant configuration in the DMA. */
+    uint8_t dma_data_fifo_base_address ;
+
+    /* The address is in chunk descriptor resolution (8 bytes). The value
+       should be identical to the relevant configuration in the DMA. */
+    uint8_t dma_chunk_descriptor_fifo_base_address ;
+
+    /* This value defines the size of both data FIFO and chunk descriptor
+       FIFO. */
+    uint8_t dma_data_and_chunk_descriptor_fifos_size ;
+
+    /* This value defines the number of occupied DMA write chunks for
+       dropping low or high priority packets. */
+    uint8_t dma_exclusive_threshold ;
+
+    /* The address is in chunk resolution (128 bytes). The value should be
+       identical to the relevant configuration in the SDMA. */
+    uint8_t sdma_data_fifo_base_address ;
+
+    /* The address is in chunk descriptor resolution (8 bytes). The value
+       should be identical to the relevant configuration in the SDMA. */
+    uint8_t sdma_chunk_descriptor_fifo_base_address ;
+
+    /* This value defines the size of both data FIFO and chunk descriptor
+       FIFO. */
+    uint8_t sdma_data_and_chunk_descriptor_fifos_size ;
+
+    /* This value defines the number of occupied SDMA write chunks for
+       dropping low or high priority packets. */
+    uint8_t sdma_exclusive_threshold ;
+
+    /* There are 4 global configurations for Minimum packet size. Each flow
+       can get one out of these 4 global configurations. Packets shorter than
+       this threshold will be discarded. */
+    uint8_t minimum_packet_size_0 ;
+
+    /* There are 4 global configurations for Minimum packet size. Each flow
+       can get one out of these 4 global configurations. Packets shorter than
+       this threshold will be discarded. */
+    uint8_t minimum_packet_size_1 ;
+
+    /* There are 4 global configurations for Minimum packet size. Each flow
+       can get one out of these 4 global configurations. Packets shorter than
+       this threshold will be discarded. */
+    uint8_t minimum_packet_size_2 ;
+
+    /* There are 4 global configurations for Minimum packet size. Each flow
+       can get one out of these 4 global configurations. Packets shorter than
+       this threshold will be discarded. */
+    uint8_t minimum_packet_size_3 ;
+
+    /* There are 4 global configurations for Maximum packet size. Each flow
+       can get one out of these 4 global configurations. Packets longer than
+       this threshold will be discarded. Should not exceed DDR buffer size. */
+    uint16_t maximum_packet_size_0 ;
+
+    /* There are 4 global configurations for Maximum packet size. Each flow
+       can get one out of these 4 global configurations. Packets longer than
+       this threshold will be discarded. Should not exceed DDR buffer size. */
+    uint16_t maximum_packet_size_1 ;
+
+    /* There are 4 global configurations for Maximum packet size. Each flow
+       can get one out of these 4 global configurations. Packets longer than
+       this threshold will be discarded. Should not exceed DDR buffer size. */
+    uint16_t maximum_packet_size_2 ;
+
+    /* There are 4 global configurations for Maximum packet size. Each flow
+       can get one out of these 4 global configurations. Packets longer than
+       this threshold will be discarded. Should not exceed DDR buffer size. */
+    uint16_t maximum_packet_size_3 ;
+
+    /* Each bit in the bitmask corresponds to 1 of the 16 IH ingress buffers.
+       The bitmask specifies which ingress buffers are assigned to the
+       relevant BBH. This configuration should correspond to the IH ingress
+       queue configurations. */
+    uint16_t ih_ingress_buffers_bitmask ;
+
+    /* Packet header offset in the ingress buffer. This value should match
+       the relevant configuration in the IH block and in the Runner. */
+    uint8_t packet_header_offset ;
+
+    /* Triggers for flow control to MAC. Values of the enumeration
+       DRV_BBH_RX_FLOW_CONTROL_TRIGGER should be ORed, as a description
+       of the desired triggers. */
+    uint8_t flow_control_triggers_bitmask ;
+
+    /* Triggers for drop. Values of the enumeration
+       DRV_BBH_RX_DROP_TRIGGER should be ORed, as a description of the
+       desired triggers. */
+    uint8_t drop_triggers_bitmask ;
+
+    /* DS Flows 0-31 have full configuration each. Flows 32-255 are divided
+       into 2 groups: 32-x, (x+1)-255. Each group has its configuration. This
+       value defines the divider (x). Relevant for GPON only. */
+    uint8_t flows_32_255_group_divider ;
+
+    /* Default IH class for PLOAM. Relevant for GPON only. */
+    uint8_t ploam_default_ih_class ;
+
+    /* IH class override for PLOAM. Relevant for GPON only. */
+    int32_t ploam_ih_class_override ;
+
+    /* The BBH writes the packets header into the IH. If the rest of the packet
+       is written into the DDR, then the address is according to the reassembly
+       offset configurations  */
+    uint8_t reassembly_offset_in_8_byte ;
+}
+DRV_BBH_RX_CONFIGURATION ;
+
+
+/******************************************************************************/
+/* Per flow configuration                                                     */
+/******************************************************************************/
+typedef struct
+{
+    /* Selects one of the 4 global configurations configured in "RX Set per
+       flow configuration" API. */
+    uint8_t minimum_packet_size_selection ;
+
+    /* Selects one of the 4 global configurations configured in "RX Set per
+       flow configuration" API. */
+    uint8_t maximum_packet_size_selection ;
+
+    /* Default IH class. */
+    uint8_t default_ih_class ;
+
+    /* IH class override. */
+    int32_t ih_class_override ;
+}
+DRV_BBH_PER_FLOW_CONFIGURATION ;
+
+
+/******************************************************************************/
+/* RX Counters                                                                */
+/******************************************************************************/
+typedef struct
+{
+    /* This counter counts the number of incoming good packets. It counts the
+       packets from all flows together. */
+    uint32_t incoming_packets ;
+
+    /* This counter counts the packets drop due to Too short error. */
+    uint32_t too_short_error ;
+
+    /* This counter counts the packets drop due to Too long error. */
+    uint32_t too_long_error ;
+
+    /* This counter counts the packets drop due to CRC error. */
+    uint32_t crc_error ;
+
+    /* This counter counts the packets drop due to Runner Congestion
+       indication (by IH). */
+    uint32_t runner_congestion ;
+
+    /* This counter counts the packets drop due to No BPM BN error. */
+    uint32_t no_bpm_bn_error ;
+
+    /* This counter counts the packets drop due to No SBPM SBN error. */
+    uint32_t no_sbpm_sbn_error ;
+
+    /* This counter counts the packets drop due to No DMA CD error. */
+    uint32_t no_dma_cd_error ;
+
+    /* This counter counts the packets drop due to No SDMA CD error. */
+    uint32_t no_sdma_cd_error ;
+}
+DRV_BBH_RX_COUNTERS ;
+
+
+/******************************************************************************/
+/* RX Error Counters                                                          */
+/******************************************************************************/
+typedef struct
+{
+    /* This counter counts the packets drop due to SOP after SOP error. */
+    uint32_t sop_after_sop_error ;
+
+    /* This counter counts the packets drop due to Third flow error. */
+    uint32_t third_flow_error ;
+
+    /* This counter counts the PLOAMs drop due to Runner Congestion or IPTV
+       Filter errors. */
+    uint32_t ih_drop_error_for_ploam ;
+
+    /* This counter counts the PLOAMs drop due to No BPM BN error. */
+    uint32_t no_bpm_bn_error_for_ploam ;
+
+    /* This counter counts the PLOAMs drop due to CRC error. */
+    uint32_t crc_error_for_ploam ;
+}
+DRV_BBH_RX_ERROR_COUNTERS ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Functions prototypes                                                       */
+/*                                                                            */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_bbh_tx_set_configuration                                       */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   BBH Driver - TX Set configuration                                        */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets configuration of the TX part of BBH block.            */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_port_index - Port index                                               */
+/*                                                                            */
+/*   xi_bbh_tx_configuration - BBH TX configuration.                          */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_BBH_ERROR - Return code                                       */
+/*     DRV_BBH_NO_ERROR - No error                                      */
+/*     DRV_BBH_INVALID_PORT_INDEX - Invalid port index                  */
+/*                                                                            */
+/******************************************************************************/
+DRV_BBH_ERROR fi_bl_drv_bbh_tx_set_configuration ( DRV_BBH_PORT_INDEX xi_port_index ,
+                                                          const DRV_BBH_TX_CONFIGURATION * xi_bbh_tx_configuration ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_bbh_rx_set_configuration                                       */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   BBH Driver - RX Set configuration                                        */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets configuration of the RX part of BBH block.            */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_port_index - Port index                                               */
+/*                                                                            */
+/*   xi_rx_configuration - RX configuration                                   */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_BBH_ERROR - Return code                                       */
+/*     DRV_BBH_NO_ERROR - No error                                      */
+/*     DRV_BBH_INVALID_PORT_INDEX - Invalid port index                  */
+/*                                                                            */
+/******************************************************************************/
+DRV_BBH_ERROR fi_bl_drv_bbh_rx_set_configuration ( DRV_BBH_PORT_INDEX xi_port_index ,
+                                                          const DRV_BBH_RX_CONFIGURATION * xi_rx_configuration ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_bbh_rx_set_triggers_of_flow_control_and_drop                   */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   BBH Driver - RX Set triggers for flow control and drop                   */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets triggers for sending flow control to MAC, and         */
+/*   triggers for dropping packets. For flow control, there are 3 possible    */
+/*   triggers: BPM is in exclusive state, SBPM is in exclusive state, Runner  */
+/*   request. For drop, there are 2 possible triggers: BPM is in exclusive    */
+/*   state, SBPM is in exclusive state. The triggers are turned on/off        */
+/*   according to the given bitmask. Values of the enumeration                */
+/*   DRV_BBH_RX_FLOW_CONTROL_TRIGGER should be ORed, as a        */
+/*   description of the desired triggers for flow control. Values of the      */
+/*   enumeration DRV_BBH_RX_DROP_TRIGGER should be ORed, as a    */
+/*   description of the desired triggers for drop.                            */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_port_index - Port index                                               */
+/*                                                                            */
+/*   xi_flow_control_triggers_bitmask - Flow control triggers bitmask         */
+/*                                                                            */
+/*   xi_drop_triggers_bitmask - Drop triggers bitmask                         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_BBH_ERROR - Return code                                       */
+/*     DRV_BBH_NO_ERROR - No error                                      */
+/*     DRV_BBH_INVALID_PORT_INDEX - Invalid port index                  */
+/*                                                                            */
+/******************************************************************************/
+DRV_BBH_ERROR fi_bl_drv_bbh_rx_set_triggers_of_flow_control_and_drop ( DRV_BBH_PORT_INDEX xi_port_index ,
+                                                                              uint8_t xi_flow_control_triggers_bitmask ,
+                                                                              uint8_t xi_drop_triggers_bitmask ) ;
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_bbh_rx_set_per_flow_configuration                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   BBH Driver - RX Set per flow configuration                               */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets per-flow configuration in the RX part of BBH block.   */
+/*   Each one of flows 0-31 has its own configuration. Flows 32-255 are       */
+/*   divided into 2 groups (32 to x, x+1 to 255). Each group has its own      */
+/*   configuration. The groups-divider (x) is configured in "RX Set           */
+/*   configuration" API. In Ethernet case, only flow 0 is relevant.           */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_port_index - Port index                                               */
+/*                                                                            */
+/*   xi_flow_index - Flow index                                               */
+/*                                                                            */
+/*   xi_per_flow_configuration - Per flow configuration                       */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_BBH_ERROR - Return code                                       */
+/*     DRV_BBH_NO_ERROR - No error                                      */
+/*     DRV_BBH_INVALID_PORT_INDEX - Invalid port index                  */
+/*                                                                            */
+/******************************************************************************/
+DRV_BBH_ERROR fi_bl_drv_bbh_rx_set_per_flow_configuration ( DRV_BBH_PORT_INDEX xi_port_index ,
+                                                                   DRV_BBH_RX_FLOW_INDEX_FOR_PER_FLOW_CONFIGURATION xi_flow_index ,
+                                                                   const DRV_BBH_PER_FLOW_CONFIGURATION * xi_per_flow_configuration ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_drv_bpm.c b/arch/arm/mach-bcmbca/rdp/rdp_drv_bpm.c
new file mode 100755
index 0000000000..cade427db4
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_drv_bpm.c
@@ -0,0 +1,708 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the implementation of the Lilac BPM driver              */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+
+#include "rdp_subsystem_common.h"
+#include "rdp_drv_bpm.h"
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Default values definitions                                                 */
+/*                                                                            */
+/******************************************************************************/
+
+#define CS_DRV_BPM_SINGLE_MEM               ( 2560 )
+#define CS_DRV_BPM_BN_ALIGMENT              ( 1536 )
+#define CS_DRV_BPM_UG_ALIGMENT              ( 4 )
+#if defined(DSL_63138)
+#define CS_DRV_BPM_GLOBAL_THRESHOLD_MASK    ( 0xf )
+#define CS_DRV_BPM_FREE_BUFFER_PTR_MASK     ( 0x7fff )
+#define CS_DRV_BPM_MCNT_BUFFER_PTR_MASK     ( 0x7fff )
+#define CS_DRV_BPM_UG_MASK                  ( 0x7fff )
+#define CS_DRV_BPM_GLOBAL_HYSTERSIS_MASK    ( 0x7fff )
+#else
+#define CS_DRV_BPM_GLOBAL_THRESHOLD_MASK    ( 0x7 )
+#define CS_DRV_BPM_FREE_BUFFER_PTR_MASK     ( 0x3fff )
+#define CS_DRV_BPM_MCNT_BUFFER_PTR_MASK     ( 0x3fff )
+#define CS_DRV_BPM_UG_MASK                  ( 0x3fff )
+#define CS_DRV_BPM_GLOBAL_HYSTERSIS_MASK    ( 0x3fff )
+#endif
+#define CS_DRV_BPM_FREE_BUFFER_OWNER_MASK   ( 0x1f )
+#define CS_DRV_BPM_MCNT_VALUE_MASK          ( 0x7 )
+#define CS_DRV_BPM_WAKEUP_TN_MASK           ( 0x3f )
+#define CS_DRV_BPM_MEM_SELECT_MASK          ( 0x7000 )
+#define CS_DRV_BPM_ADDRESS_FIELD_MASK       ( 0xfe0 )
+#define CS_DRV_BPM_BITS_INDEX_MASK          ( 0x1f )
+#define CS_DRV_BPM_NUM_OF_BITS_FOR_BN       ( 3 )
+#define CS_DRV_BPM_RNR_TA                   ( 0x1540 )
+
+/* Low */
+#define CS_LOW      (  0 )
+/* High */
+#define CS_HIGH     (  1  )
+
+/******************************************************************************/
+/*                                                                            */
+/* Macros definitions                                                         */
+/*                                                                            */
+/******************************************************************************/
+
+/* gets bit #i from a given number */
+#define MS_DRV_BPM_GET_BIT_I( number , i )   ( ( ( 1 << i ) & ( number ) ) >> i )
+
+/******************************************************************************/
+/*                                                                            */
+/* static function declaration                                                */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/* Init & cleanup module, license                                             */
+/*                                                                            */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/* API functions implementations                                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_init					                                   */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - BPM initialize    	                                           */
+/*                                                                             */
+/* Abstract:                                                                   */
+/* BPM module initialization is made once in the system lifetime               */
+/* This API performs the following:                                            */
+/*  1.	Write a value to register ram_init.                                    */
+/*  2.	Setting Route Addresses to each Source Port                            */
+/*  3.	Set BPM global threshold, thresholds for all UG and Exclusive UGs      */
+/*      according to input parameters.                                         */   
+/*  4.	Mapping SP to UGs using registers BPM_UG_MAP_0, BPM_UG_MAP_1.          */
+/*This function sets general configuration of the BPM block                    */
+/*	                                                                           */
+/*                                                                             */
+/* Input: 																	   */
+/*   global_configuration - global threshold and hysteresis (struct)           */
+/*   ug_configuration  - user groups threshold and hysteresis (struct)         */
+/*   xi_replay_address - runner replay address                                  */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_init(DRV_BPM_GLOBAL_CONFIGURATION    * xi_global_configuration, 
+                                         DRV_BPM_USER_GROUPS_THRESHOLDS  * xi_ug_configuration,
+                                         uint16_t                             xi_replay_address,
+                                         E_DRV_BPM_SPARE_MESSAGE_FORMAT xi_bpm_spare_message_format )
+{
+    BPM_MODULE_REGS_RAM_INIT   bpm_init;     
+    DRV_BPM_ERROR     error;
+    BPM_MODULE_REGS_BPM_RADDR0 raddr0;
+    BPM_MODULE_REGS_BPM_RADDR1 raddr1;
+    BPM_MODULE_REGS_BPM_RADDR2 raddr2;
+    uint8_t                      ug_index;
+    DRV_BPM_RUNNER_MSG_CTRL_PARAMS runner_msg_ctrl_params ;
+    BPM_MODULE_REGS_BPM_SPARE bpm_spare_register;
+
+    /* Write to register ram_init value */
+    BPM_MODULE_REGS_RAM_INIT_READ(bpm_init);
+    bpm_init.bsy = BPM_MODULE_REGS_RAM_INIT_BSY_READY_VALUE;
+    bpm_init.rdy = BPM_MODULE_REGS_RAM_INIT_RDY_BUSY_VALUE;
+    BPM_MODULE_REGS_RAM_INIT_WRITE(bpm_init);
+
+    /* Set BPM global configuration  */
+    error = fi_bl_drv_bpm_set_global_threshold ( xi_global_configuration->threshold , xi_global_configuration->hysteresis );
+
+    /* Set User Group [0-7] threshold configuration*/
+    for ( ug_index = 0 ; ug_index < DRV_BPM_NUMBER_OF_USER_GROUPS  ; ug_index++  ) 
+    {
+        error = fi_bl_drv_bpm_set_user_group_thresholds ( ug_index, &xi_ug_configuration->ug_arr[ug_index] );
+        if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+        {
+            return ( error );
+        }
+    }
+
+	/* Write to register bpm_raddr0 value 0x1F010002 :
+	 	emac0 Rx route address = 0x1f
+		gpon Rx route address = 0x01
+		runner B route address = 0x02
+		runner A route address = 0 */
+    BPM_MODULE_REGS_BPM_RADDR0_READ (raddr0 );
+    raddr0.emac0_rx_raddr = BPM_MODULE_REGS_BPM_RADDR0_EMAC0_RX_RADDR_EMAC0_RX_ROUTE_ADDRESS_VALUE ;
+    raddr0.gpon_rx_raddr  = BPM_MODULE_REGS_BPM_RADDR0_GPON_RX_RADDR_GPON_RX_ROUTE_ADDRESS_VALUE ;
+    raddr0.runa_raddr = BPM_MODULE_REGS_BPM_RADDR0_RUNA_RADDR_RUNNER_A_ROUTE_ADDRESS_VALUE;
+    raddr0.runb_raddr = BPM_MODULE_REGS_BPM_RADDR0_RUNB_RADDR_RUNNER_B_ROUTE_ADDRESS_VALUE;
+    BPM_MODULE_REGS_BPM_RADDR0_WRITE( raddr0 );
+
+    /* Write to register bpm_raddr1 value 0x1109170f 
+		emac4 rx route address = 0x11
+		emac3 rx route address = 0x9
+		emac2 rx route address = 0x1b
+		emac1 rx route address = 0x0f*/	
+    BPM_MODULE_REGS_BPM_RADDR1_READ( raddr1 );
+    raddr1.emac1_rx_raddr = BPM_MODULE_REGS_BPM_RADDR1_EMAC1_RX_RADDR_EMAC1_ROUTE_ADDRESS_VALUE;
+    raddr1.emac2_rx_raddr = BPM_MODULE_REGS_BPM_RADDR1_EMAC2_RX_RADDR_EMAC2_ROUTE_ADDRESS_VALUE;
+    raddr1.emac3_rx_raddr = BPM_MODULE_REGS_BPM_RADDR1_EMAC3_RX_RADDR_CONFIGURABLE_EMAC3_RX_ROUTE_ADDRESS_VALUE;
+    raddr1.emac4_rx_raddr = BPM_MODULE_REGS_BPM_RADDR1_EMAC4_RX_RADDR_EMAC4_RX_ROUTE_ADDRESS_VALUE ;
+    BPM_MODULE_REGS_BPM_RADDR1_WRITE( raddr1 );
+
+    /* Write to register bpm_raddr2 value 0x06 */	
+    BPM_MODULE_REGS_BPM_RADDR2_READ ( raddr2 );
+    raddr2.mipsd_raddr = BPM_MODULE_REGS_BPM_RADDR2_MIPSD_RADDR_MIPSD_ROUTE_ADDRESS_VALUE;
+    BPM_MODULE_REGS_BPM_RADDR2_WRITE( raddr2 );
+
+    /* Each Source Port is mapped to specified UG. */
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_MIPS_C , DRV_BPM_USER_GROUP_7 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_RNR_A , DRV_BPM_USER_GROUP_6 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_RNR_B , DRV_BPM_USER_GROUP_6 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_GPON , DRV_BPM_USER_GROUP_5 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_EMAC0 , DRV_BPM_USER_GROUP_0 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_EMAC1 , DRV_BPM_USER_GROUP_1 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_EMAC2 , DRV_BPM_USER_GROUP_2 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_EMAC3 , DRV_BPM_USER_GROUP_3 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_EMAC4 , DRV_BPM_USER_GROUP_4 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_USB0 , DRV_BPM_USER_GROUP_4 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_USB1 , DRV_BPM_USER_GROUP_4 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_PCI0 , DRV_BPM_USER_GROUP_4 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_PCI1 , DRV_BPM_USER_GROUP_4 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_MIPS_D , DRV_BPM_USER_GROUP_7 );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_sp_enable ( DRV_BPM_SP_RNR_A , DRV_BPM_ENABLE );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_bpm_sp_enable ( DRV_BPM_SP_RNR_B , DRV_BPM_ENABLE );
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    /* Set Runner Message Control parameters */
+    error = fi_bl_drv_bpm_get_runner_msg_ctrl ( & runner_msg_ctrl_params ) ;
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    runner_msg_ctrl_params.runner_a_reply_target_address = xi_replay_address >> 3 ;
+    runner_msg_ctrl_params.runner_b_reply_target_address = xi_replay_address >> 3 ;
+
+    error = fi_bl_drv_bpm_set_runner_msg_ctrl ( & runner_msg_ctrl_params ) ;
+    if ( error !=  DRV_BPM_ERROR_NO_ERROR ) 
+    {
+        return ( error );
+    }
+
+    BPM_MODULE_REGS_BPM_SPARE_READ( bpm_spare_register );
+    bpm_spare_register.bn_msg_format = xi_bpm_spare_message_format;
+    BPM_MODULE_REGS_BPM_SPARE_WRITE( bpm_spare_register );
+    return ( DRV_BPM_ERROR_NO_ERROR );
+
+}
+EXPORT_SYMBOL ( fi_bl_drv_bpm_init );
+
+/*******************************************************************************/
+/* fi_bl_drv_bpm_sp_enable					       */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Source Ports Enable	                                       */
+/*                                                                             */
+/* Abstract:                                                                   */
+/* Source Ports Enable	                                                       */
+/*                                                                             */
+/* Registers:                                                                  */
+/* BPM_SP_EN                                                                   */
+/*                                                                             */
+/* Input:								       */
+/*                                                                             */
+/*    xi_source_port - One of the BPM source port: GPON, EMAC0-4, RNR_A/B      */
+/*                                                                             */
+/*    xi_enable - enable/ disable                                              */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 			       */		
+/*   DRV_BPM_ERROR_INVALID_SOURCE_PORT - invalid source port       */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_sp_enable(DRV_BPM_SP_USR xi_source_port, 
+                                                         E_DRV_BPM_ENABLE xi_enable )
+{
+    BPM_MODULE_REGS_BPM_SP_EN bpm_sp_enable;
+
+    BPM_MODULE_REGS_BPM_SP_EN_READ( bpm_sp_enable);
+
+    switch(xi_source_port)
+    {
+        case DRV_BPM_SP_RNR_A:
+            bpm_sp_enable.rnra_en = xi_enable;
+            break;
+        case DRV_BPM_SP_RNR_B:
+            bpm_sp_enable.rnrb_en = xi_enable;
+            break;
+        case DRV_BPM_SP_GPON:
+            bpm_sp_enable.gpon_en = xi_enable;
+            break;
+        case DRV_BPM_SP_EMAC0:
+            bpm_sp_enable.emac0_en = xi_enable;
+            break;
+        case DRV_BPM_SP_EMAC1:
+            bpm_sp_enable.emac1_en = xi_enable;
+            break;
+        case DRV_BPM_SP_EMAC2:
+            bpm_sp_enable.emac2_en = xi_enable;
+            break;
+        case DRV_BPM_SP_EMAC3:
+            bpm_sp_enable.emac3_en = xi_enable;
+            break;
+        case DRV_BPM_SP_EMAC4:
+            bpm_sp_enable.emac4_en = xi_enable;
+            break;
+        default:
+            return ( DRV_BPM_ERROR_INVALID_SOURCE_PORT );
+    }
+
+    BPM_MODULE_REGS_BPM_SP_EN_WRITE( bpm_sp_enable);
+
+    return ( DRV_BPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_bpm_sp_enable );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_set_global_threshold                                    */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Set BPM Global threshold                                       */
+/*                                                                             */
+/* Abstract:                                                                   */
+/* This function sets the global Threshold for Allocated Buffers.              */
+/*                                                                             */
+/* Input:																	   */
+/*                                                                             */
+/*   xi_global_threshold - Global Threshold for Allocated Buffers              */
+/*   xi_global_hystersis - Global Buffer Allocation Hysteresis threshold       */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_set_global_threshold ( DRV_BPM_GLOBAL_THRESHOLD xi_global_threshold,
+                                                                      uint32_t xi_global_hysteresis )
+{
+    BPM_MODULE_REGS_BPM_GL_TRSH global_configuration;
+
+    BPM_MODULE_REGS_BPM_GL_TRSH_READ(global_configuration);
+
+    global_configuration.gl_bah = ( xi_global_hysteresis & CS_DRV_BPM_GLOBAL_HYSTERSIS_MASK);
+    global_configuration.gl_bat = ( xi_global_threshold  & CS_DRV_BPM_GLOBAL_THRESHOLD_MASK);
+
+    BPM_MODULE_REGS_BPM_GL_TRSH_WRITE(global_configuration);
+
+    return ( DRV_BPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_bpm_set_global_threshold );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_set_user_group_thresholds                               */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Set BPM User Group threshold configuration                     */
+/*                                                                             */
+/* Abstract:                                                                   */
+/* Threshold for Allocated Buffers of UG                                       */
+/* Ths register also holds UG0 hysteresis value for ACK/NACK transition setting*/
+/* This register is affected by soft reset.                                    */
+/*                                                                             */
+/* Input:																	   */
+/*	xi_ug - user group 														   */			
+/*  xi_configuration - thresholds configuration for the user group (struct)    */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_set_user_group_thresholds (DRV_BPM_USER_GROUP xi_ug, 
+                                                                          DRV_BPM_USER_GROUP_CONFIGURATION * xi_configuration)
+{
+    DRV_BPM_UG_THRESHOLD ug_configuration;
+    DRV_BPM_UG_THRESHOLD ug_exclusive_configuration;
+    uint32_t ug_start_address = ( BPM_MODULE_REGS_BPM_UG0_TRSH_ADDRESS + CS_DRV_BPM_UG_ALIGMENT * xi_ug );
+    uint32_t ug_exclusive_start_address = ( BPM_MODULE_REGS_BPM_UG0_EXCL_TRSH_ADDRESS + CS_DRV_BPM_UG_ALIGMENT * xi_ug );
+
+    READ_32( ug_start_address, ug_configuration);
+
+    ug_configuration.ug_hysteresis = ( xi_configuration->hysteresis & CS_DRV_BPM_UG_MASK );
+    ug_configuration.ug_threshold =  ( xi_configuration->threshold & CS_DRV_BPM_UG_MASK );
+
+    WRITE_32( ug_start_address, ug_configuration);	
+
+    READ_32( ug_exclusive_start_address , ug_exclusive_configuration);
+
+    ug_exclusive_configuration.ug_hysteresis = ( xi_configuration->exclusive_hysteresis & CS_DRV_BPM_UG_MASK );
+    ug_exclusive_configuration.ug_threshold =  ( xi_configuration->exclusive_threshold  & CS_DRV_BPM_UG_MASK );
+
+    WRITE_32( ug_exclusive_start_address , ug_exclusive_configuration);
+
+    return ( DRV_BPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_bpm_set_user_group_thresholds );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_set_user_group_mapping                                  */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Set User Group Mapping                                         */
+/*                                                                             */
+/* Abstract:                                                                   */
+/* This function maps a User group for a specific Source port                  */
+/*                                                                             */
+/* Input:                                              			               */
+/*	xi_source_port - One of BPM source ports		                           */
+/*  xi_user_group  - one of BPM User group 0-7                                 */
+/*                                                                             */
+/* Output:  error code                                                         */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*	 DRV_BPM_ERROR_INVALID_SOURCE_PORT - invalid source port   	   */
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_USR  xi_source_port,
+                                                                        DRV_BPM_USER_GROUP xi_user_group )
+{
+    BPM_MODULE_REGS_BPM_UG_MAP_R0  bpm_ug_mapping_r0;
+    BPM_MODULE_REGS_BPM_UG_MAP_R1  bpm_ug_mapping_r1;
+
+    BPM_MODULE_REGS_BPM_UG_MAP_R0_READ(bpm_ug_mapping_r0);
+    BPM_MODULE_REGS_BPM_UG_MAP_R1_READ(bpm_ug_mapping_r1);
+
+    switch ( xi_source_port )
+    {   
+        case DRV_BPM_SP_MIPS_C:
+            bpm_ug_mapping_r0.cpu_ = xi_user_group;
+            break ;
+        case DRV_BPM_SP_EMAC0:
+            bpm_ug_mapping_r0.emac0 = xi_user_group;
+            break ;
+        case DRV_BPM_SP_EMAC1:
+            bpm_ug_mapping_r0.emac1 = xi_user_group;
+            break ;
+        case DRV_BPM_SP_EMAC2:
+            bpm_ug_mapping_r0.emac2 = xi_user_group;
+            break ;
+        case DRV_BPM_SP_EMAC3:
+            bpm_ug_mapping_r0.emac3 = xi_user_group;
+            break ;
+        case DRV_BPM_SP_EMAC4:
+            bpm_ug_mapping_r1.emac4= xi_user_group;
+            break ;
+        case DRV_BPM_SP_GPON:
+            bpm_ug_mapping_r0.gpon = xi_user_group;
+            break ;
+        case DRV_BPM_SP_RNR_A:
+            bpm_ug_mapping_r0.rnr_a = xi_user_group;
+            break ;
+        case DRV_BPM_SP_RNR_B:
+            bpm_ug_mapping_r0.rnr_b = xi_user_group;
+            break ;
+        case DRV_BPM_SP_USB0:
+            bpm_ug_mapping_r1.usb0 = xi_user_group;
+            break ;
+        case DRV_BPM_SP_USB1:
+            bpm_ug_mapping_r1.usb1= xi_user_group;
+            break ;
+        case DRV_BPM_SP_PCI0:
+            bpm_ug_mapping_r1.pcie0 = xi_user_group;
+            break ;
+        case DRV_BPM_SP_PCI1:
+            bpm_ug_mapping_r1.pcie1 = xi_user_group;
+            break ;
+        case DRV_BPM_SP_MIPS_D:
+            bpm_ug_mapping_r1.mipsd = xi_user_group;
+            break ;
+        case DRV_BPM_SP_SPARE_0:
+            bpm_ug_mapping_r1.spare0 = xi_user_group;
+            break ;
+        case DRV_BPM_SP_SPARE_1:
+            bpm_ug_mapping_r1.spare1 = xi_user_group;
+            break ;
+        default:
+            return ( DRV_BPM_ERROR_INVALID_SOURCE_PORT );
+    }
+
+    BPM_MODULE_REGS_BPM_UG_MAP_R0_WRITE (bpm_ug_mapping_r0);
+    BPM_MODULE_REGS_BPM_UG_MAP_R1_WRITE (bpm_ug_mapping_r1);
+
+    return ( DRV_BPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_bpm_set_user_group_mapping );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_req_buffer                                              */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Request Buffer                                                 */
+/*                                                                             */
+/* Abstract:                                                                   */
+/* cpu requests a free buffer pointer                                          */
+/*                                                                             */
+/* Input:                                                                      */
+/*     xi_source_port - used by CPU for Buffer Request allocation on behalf    */
+/*     another port                                                            */
+/*     xo_bn - returned 14 bits of DDR buffer pointer value                    */
+/*                                                                             */
+/* Output:  error code                                                         */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*	 DRV_BPM_ERROR_BPM_BUSY - BPM busy in previous operation	   */	
+/*	 DRV_BPM_ERROR_NO_FREE_BUFFER - BPM has no free buffer         */	
+/*                                              to allocate                    */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_req_buffer(DRV_BPM_SP_USR xi_source_port,
+                                                          uint32_t * const xo_bn)
+{
+	
+    BPM_MODULE_REGS_REQ_PTR req_ptr;
+    int32_t num_count = 10;
+
+    BPM_MODULE_REGS_REQ_PTR_READ(req_ptr);
+    req_ptr.sp_addr = xi_source_port;
+    BPM_MODULE_REGS_REQ_PTR_WRITE(req_ptr);
+
+    while( num_count-- > 0 )
+    { 
+        BPM_MODULE_REGS_REQ_PTR_READ(req_ptr);
+        if(  req_ptr.bsy != BPM_MODULE_REGS_REQ_PTR_BSY_BUSY_VALUE )
+        {
+            break;
+        }
+    }
+
+    if( num_count == -1 )
+    {
+        return ( DRV_BPM_ERROR_BPM_BUSY );
+    }
+    else
+    {
+        if( req_ptr.nack_status == BPM_MODULE_REGS_REQ_PTR_NACK_STATUS_CPU_IN_NACK_STATE_VALUE )
+        {
+            return ( DRV_BPM_ERROR_NO_FREE_BUFFER );
+        } 
+        else /* buffer number is valid */
+        {
+            * xo_bn = req_ptr.bn;
+        }
+    }
+
+    return ( DRV_BPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_bpm_req_buffer );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_set_runner_msg_ctrl                                     */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM Driver - Set Runner message control                                     */
+/*                                                                             */
+/* Abstract:                                                                   */
+/* Enables runner wake-up messages, 										   */
+/* select control bit for transition message and task numbers for wake-up      */
+/* messages to Runners														   */ 
+/*                                                                             */
+/* Registers:                                                                  */
+/* BPM_RNR_MSG_CTRL,BPM_RNR_RPLY_TA                                            */
+/*                                                                             */
+/* Input:																	   */
+/*                                                                             */
+/*  xi_runner_messsage_control_parameters - struct                             */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_set_runner_msg_ctrl(DRV_BPM_RUNNER_MSG_CTRL_PARAMS  * xi_runner_msg_ctrl_params)
+{
+    BPM_MODULE_REGS_BPM_RNR_MSG_CTRL runner_message_control;
+    BPM_MODULE_REGS_BPM_RNR_RPLY_TA  bpm_rnr_rply_ta_register;
+
+    BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_READ( runner_message_control );
+
+    runner_message_control.rnr_rply_wkup_en = ( xi_runner_msg_ctrl_params->reply_wakeup_enable ==  1 ) ? 
+        DRV_BPM_ENABLE : DRV_BPM_DISABLE ;
+    runner_message_control.rnr_trans_wkup_en = ( xi_runner_msg_ctrl_params->transition_wakeup_enable ==  1 ) ? 
+        DRV_BPM_ENABLE : DRV_BPM_DISABLE ;
+    runner_message_control.rnr_sel_trans_msg =  ( xi_runner_msg_ctrl_params->select_transition_msg ==  1 ) ? 
+        BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_SEL_TRANS_MSG_TRANSITION_MESSAGE_SELECTED_TO_RUNNER_B_VALUE : 
+        BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_RNR_SEL_TRANS_MSG_TRANSITION_MESSAGE_SELECTED_TO_RUNNER_A_VALUE ;
+    runner_message_control.rnr_a_rply_wkup_tn = xi_runner_msg_ctrl_params->runner_a_reply_wakeup_task_number & CS_DRV_BPM_WAKEUP_TN_MASK;
+    runner_message_control.rnr_b_rply_wkup_tn = xi_runner_msg_ctrl_params->runner_b_reply_wakeup_task_number & CS_DRV_BPM_WAKEUP_TN_MASK;
+    runner_message_control.rnr_trans_wkup_tn =  xi_runner_msg_ctrl_params->runner_transition_wakeup_task_number & CS_DRV_BPM_WAKEUP_TN_MASK; 	
+
+    BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_WRITE( runner_message_control );
+
+    BPM_MODULE_REGS_BPM_RNR_RPLY_TA_READ ( bpm_rnr_rply_ta_register );
+
+    bpm_rnr_rply_ta_register.rnr_a_ta = xi_runner_msg_ctrl_params->runner_a_reply_target_address ;
+    bpm_rnr_rply_ta_register.rnr_b_ta = xi_runner_msg_ctrl_params->runner_b_reply_target_address ;
+
+    BPM_MODULE_REGS_BPM_RNR_RPLY_TA_WRITE (bpm_rnr_rply_ta_register);
+
+    return ( DRV_BPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_bpm_set_runner_msg_ctrl );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_get_runner_msg_ctrl                                     */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM Driver - Get Runner message control                                     */
+/*                                                                             */
+/* Abstract:                                                                   */
+/* Enables runner wake-up messages, 										   */
+/* select control bit for transition message and task numbers for wake-up      */
+/* messages to Runners														   */
+/*                                                                             */
+/* Registers:                                                                  */
+/* BPM_RNR_MSG_CTRL,BPM_RNR_RPLY_TA                                            */
+/*                                                                             */
+/* Input:																	   */
+/*                                                                             */
+/*  xo_runner_messsage_control_parameters - struct                             */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_get_runner_msg_ctrl(DRV_BPM_RUNNER_MSG_CTRL_PARAMS * const xo_runner_msg_ctrl_params)
+{
+    BPM_MODULE_REGS_BPM_RNR_MSG_CTRL runner_message_control;
+    BPM_MODULE_REGS_BPM_RNR_RPLY_TA  bpm_rnr_rply_ta_register;
+
+    BPM_MODULE_REGS_BPM_RNR_MSG_CTRL_READ( runner_message_control );
+
+    xo_runner_msg_ctrl_params->reply_wakeup_enable = ( runner_message_control.rnr_rply_wkup_en ==  1 ) ?
+        DRV_BPM_ENABLE : DRV_BPM_DISABLE;
+
+    xo_runner_msg_ctrl_params->transition_wakeup_enable =  ( runner_message_control.rnr_trans_wkup_en ==  1 ) ?
+        DRV_BPM_ENABLE : DRV_BPM_DISABLE;
+
+    xo_runner_msg_ctrl_params->select_transition_msg = ( runner_message_control.rnr_sel_trans_msg ==  1 )  ?
+        DRV_BPM_ENABLE : DRV_BPM_DISABLE;
+
+    xo_runner_msg_ctrl_params->runner_a_reply_wakeup_task_number = runner_message_control.rnr_a_rply_wkup_tn;
+    xo_runner_msg_ctrl_params->runner_b_reply_wakeup_task_number = runner_message_control.rnr_b_rply_wkup_tn;	
+    xo_runner_msg_ctrl_params->runner_transition_wakeup_task_number = runner_message_control.rnr_trans_wkup_tn;		
+		
+    BPM_MODULE_REGS_BPM_RNR_RPLY_TA_READ (bpm_rnr_rply_ta_register);
+
+    xo_runner_msg_ctrl_params->runner_a_reply_target_address = ( uint16_t ) bpm_rnr_rply_ta_register.rnr_a_ta;
+    xo_runner_msg_ctrl_params->runner_b_reply_target_address = ( uint16_t ) bpm_rnr_rply_ta_register.rnr_b_ta;
+
+    return ( DRV_BPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_bpm_get_runner_msg_ctrl );
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_drv_bpm.h b/arch/arm/mach-bcmbca/rdp/rdp_drv_bpm.h
new file mode 100755
index 0000000000..0b5adadd4d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_drv_bpm.h
@@ -0,0 +1,585 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/             
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This header file defines all datatypes and functions exported for the      */
+/* Lilac BPM driver.                                                          */
+/*                                                                            */
+/******************************************************************************/
+
+#ifndef LILAC_DRV_BPM_H_INCLUDED
+#define LILAC_DRV_BPM_H_INCLUDED
+
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+#include "rdp_bpm.h"
+
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Error codes returned by BPM driver APIs                                    */
+/******************************************************************************/
+typedef enum
+{
+	DRV_BPM_ERROR_NO_ERROR = 0,
+    DRV_BPM_ERROR_BPM_BUSY ,
+    DRV_BPM_ERROR_NO_FREE_BUFFER,
+    DRV_BPM_ERROR_INVALID_SOURCE_PORT,
+    DRV_BPM_ERROR_INVALID_USER_GROUP
+	
+}DRV_BPM_ERROR;
+
+
+/******************************************************************************/
+/* BPM source ports                                                           */
+/******************************************************************************/
+typedef enum
+{
+	DRV_BPM_SP_GPON = 0,
+	DRV_BPM_SP_EMAC0,
+	DRV_BPM_SP_EMAC1,
+	DRV_BPM_SP_EMAC2,
+	DRV_BPM_SP_EMAC3,
+	DRV_BPM_SP_EMAC4,
+    DRV_BPM_SP_MIPS_C,
+    DRV_BPM_SP_MIPS_D,
+    DRV_BPM_SP_PCI0,
+    DRV_BPM_SP_PCI1,
+    DRV_BPM_SP_USB0,
+    DRV_BPM_SP_USB1,
+    DRV_BPM_SP_SPARE_0,
+    DRV_BPM_SP_SPARE_1,
+    DRV_BPM_SP_RNR_A,
+    DRV_BPM_SP_RNR_B
+	
+}DRV_BPM_SP_USR;
+
+/******************************************************************************/
+/* BPM Global threshold values                                                */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+	DRV_BPM_GLOBAL_THRESHOLD_2_5K = 0,
+	DRV_BPM_GLOBAL_THRESHOLD_5K,
+    DRV_BPM_GLOBAL_THRESHOLD_7_5K,
+	DRV_BPM_GLOBAL_THRESHOLD_10K,
+	DRV_BPM_GLOBAL_THRESHOLD_12_5K,
+	DRV_BPM_GLOBAL_THRESHOLD_15K,
+    DRV_BPM_GLOBAL_THRESHOLD_17_5K,
+    DRV_BPM_GLOBAL_THRESHOLD_20K,
+    DRV_BPM_GLOBAL_THRESHOLD_22_5K,
+    DRV_BPM_GLOBAL_THRESHOLD_25K,
+    DRV_BPM_GLOBAL_THRESHOLD_27_5K,
+    DRV_BPM_GLOBAL_THRESHOLD_30K
+	
+}DRV_BPM_GLOBAL_THRESHOLD;
+
+/******************************************************************************/
+/* BPM User Groups index:                                                     */
+/******************************************************************************/
+typedef enum
+{
+	DRV_BPM_USER_GROUP_0,
+	DRV_BPM_USER_GROUP_1,
+    DRV_BPM_USER_GROUP_2,
+	DRV_BPM_USER_GROUP_3,
+	DRV_BPM_USER_GROUP_4,
+    DRV_BPM_USER_GROUP_5,
+    DRV_BPM_USER_GROUP_6,
+    DRV_BPM_USER_GROUP_7,
+    DRV_BPM_NUMBER_OF_USER_GROUPS
+	
+}DRV_BPM_USER_GROUP;
+
+/******************************************************************************/
+/* Boolean                                                                    */
+/******************************************************************************/
+typedef enum
+{
+	DRV_BPM_DISABLE = 0,
+	DRV_BPM_ENABLE = 1
+	
+}E_DRV_BPM_ENABLE;
+
+/******************************************************************************/
+/* BPM Global Configuration struct                                            */
+/******************************************************************************/
+typedef struct
+{
+    /* Global hysteresis */
+    uint32_t hysteresis ;
+
+    /* Global threshold */
+    DRV_BPM_GLOBAL_THRESHOLD threshold  ;
+} 
+DRV_BPM_GLOBAL_CONFIGURATION ;
+
+
+/******************************************************************************/
+/* BPM User Group mapping struct                                              */
+/******************************************************************************/
+typedef struct
+{
+  	DRV_BPM_USER_GROUP sp_gpon_mapping;
+	DRV_BPM_USER_GROUP sp_emac0_mapping;
+	DRV_BPM_USER_GROUP sp_emac1_mapping;
+	DRV_BPM_USER_GROUP sp_emac2_mapping;
+	DRV_BPM_USER_GROUP sp_emac3_mapping;
+	DRV_BPM_USER_GROUP sp_emac4_mapping;
+    DRV_BPM_USER_GROUP sp_mips_c_mapping;
+    DRV_BPM_USER_GROUP sp_mips_d_mapping;
+    DRV_BPM_USER_GROUP sp_pci0_mapping;
+    DRV_BPM_USER_GROUP sp_pci1_mapping;
+    DRV_BPM_USER_GROUP sp_usb0_mapping;
+    DRV_BPM_USER_GROUP sp_usb1_mapping;
+    DRV_BPM_USER_GROUP sp_rnr_a_mapping;
+    DRV_BPM_USER_GROUP sp_rnr_b_mapping;
+} 
+DRV_BPM_USER_GROUP_MAPPING ;
+
+/******************************************************************************/
+/* BPM User Group thresholds struct                                           */
+/******************************************************************************/
+#if defined(DSL_63138)
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+    /* rsv */
+    uint32_t rsv2          : 1 ;
+    /* UG hysteresis */
+    uint32_t ug_hysteresis : 15 ;
+    /* reserved */
+    uint32_t rsv           : 1  ;
+    /*  UG threshold */
+    uint32_t ug_threshold  : 15 ;
+} 
+DRV_BPM_UG_THRESHOLD ;
+#else
+typedef struct
+{
+    /*  UG threshold */
+    uint32_t ug_threshold  : 15 ;
+    /* reserved */
+    uint32_t rsv           : 1  ;
+    /* UG hysteresis */
+    uint32_t ug_hysteresis : 15 ;
+    /* rsv */
+    uint32_t rsv2          : 1 ;
+} 
+DRV_BPM_UG_THRESHOLD ;
+#endif
+#else // DSL_63138
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+    /* rsv */
+    uint32_t rsv2          : 2 ;
+    /* UG hysteresis */
+    uint32_t ug_hysteresis : 14 ;
+    /* reserved */
+    uint32_t rsv           : 2  ;
+    /*  UG threshold */
+    uint32_t ug_threshold  : 14 ;
+} 
+DRV_BPM_UG_THRESHOLD ;
+#else
+typedef struct
+{
+    /*  UG threshold */
+    uint32_t ug_threshold  : 14 ;
+    /* reserved */
+    uint32_t rsv           : 2  ;
+    /* UG hysteresis */
+    uint32_t ug_hysteresis : 14 ;
+    /* rsv */
+    uint32_t rsv2          : 2 ;
+} 
+DRV_BPM_UG_THRESHOLD ;
+#endif
+#endif // DSL_63138
+
+/******************************************************************************/
+/* BPM User Group configuration struct                                           */
+/******************************************************************************/
+typedef struct
+{
+    /*  threshold */
+    uint32_t threshold  ;
+
+    /*  hysteresis */
+    uint32_t hysteresis ;
+
+    /*  Exclusive threshold */
+    uint32_t exclusive_threshold  ;
+
+    /*  Exclusive hysteresis */
+    uint32_t exclusive_hysteresis ;
+
+} 
+DRV_BPM_USER_GROUP_CONFIGURATION ;
+
+/******************************************************************************/
+/* BPM User Group thresholds struct  - contains array of 8 user groups        */
+/******************************************************************************/
+typedef struct
+{
+    DRV_BPM_USER_GROUP_CONFIGURATION ug_arr[ DRV_BPM_NUMBER_OF_USER_GROUPS ]   ;
+} 
+DRV_BPM_USER_GROUPS_THRESHOLDS ;
+
+/*******************************************************************************/
+/*  Runner message control parameters - struct                                 */
+/*******************************************************************************/
+typedef struct
+{
+    /* Enable/Disable wake-up message after each reply on *Alloc request from Runner */
+    E_DRV_BPM_ENABLE reply_wakeup_enable ;
+
+    /* Enable/Disable  wake-up message after each   transition state of any peripheral */
+	E_DRV_BPM_ENABLE transition_wakeup_enable;
+
+    /*select for sending transition message: Runner A or B*/
+	E_DRV_BPM_ENABLE select_transition_msg;
+
+    /*Task number for Runner A Wake-Up  as result of Reply on Alloc request*/
+	uint32_t  runner_a_reply_wakeup_task_number;
+
+    /*Task number for Runner B Wake-Up  as result of Reply on Alloc request*/
+	uint32_t  runner_b_reply_wakeup_task_number;
+
+    /*Task number for any slected Runner Wake-Up as result of Transition*/
+	uint32_t  runner_transition_wakeup_task_number;
+
+    /*Target address for Runner A*/
+    uint16_t  runner_a_reply_target_address; 
+
+    /*Target address for Runner B*/
+    uint16_t  runner_b_reply_target_address;
+} 
+DRV_BPM_RUNNER_MSG_CTRL_PARAMS ;
+
+/*******************************************************************************/
+/*  MIPS D message control parameters - struct                                 */
+/*******************************************************************************/
+typedef struct
+{
+    /*Enable/Disable wake-up message */
+    E_DRV_BPM_ENABLE mips_d_reply_wakeup_enable;
+
+    /*Task number for Runner A Wake-Up as resultof Reply on Alloc request*/
+    uint16_t  mips_d_reply_wakeup_task_number ;
+
+    /*Target address for MIPS-D*/
+    uint16_t  mips_d_reply_target_address ;
+} 
+DRV_BPM_MIPS_D_MSG_CTRL_PARAMS ;
+
+
+/******************************************************************************/
+/* BPM User Group status struct                                               */
+/******************************************************************************/
+typedef struct
+{
+    /*User group status - ack/nack*/
+    E_DRV_BPM_ENABLE ug_status ;
+
+    /*User group exclusive status - non-exclusive/exclusive*/
+    E_DRV_BPM_ENABLE ug_exclusive_status ;
+} 
+DRV_BPM_USER_GROUP_STATUS ;
+
+/******************************************************************************/
+/* BPM Interrupts status struct                                               */
+/******************************************************************************/
+typedef struct
+{
+    E_DRV_BPM_ENABLE free_interrupt ;
+	E_DRV_BPM_ENABLE multicast_counter_interrupt;
+} 
+DRV_BPM_ISR ;
+
+typedef enum
+{
+    DRV_SPARE_BN_MESSAGE_FORMAT_14_bit_BN_WIDTH ,
+    DRV_SPARE_BN_MESSAGE_FORMAT_15_bit_BN_WIDTH
+} 
+E_DRV_BPM_SPARE_MESSAGE_FORMAT ;
+
+/*******************************************************************************/
+/*                                                                             */
+/* Functions prototypes                                                        */
+/*                                                                             */
+/*******************************************************************************/
+
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_init					                                   */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - BPM initialize    	                                           */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* BPM module initialization is made once in the system lifetime               */
+/* This API performs the following:                                            */
+/*  1.	Write a value to register ram_init.                                    */
+/*  2.	Setting Route Addresses to each Source Port                            */
+/*  3.	Set BPM global threshold, thresholds for all UG and Exclusive UGs      */
+/*      according to input parameters.                                         */   
+/*  4.	Mapping SP to UGs using registers BPM_UG_MAP_0, BPM_UG_MAP_1.          */
+/*This function sets general configuration of the BPM block                    */
+/*	                                                                           */
+/*                                                                             */
+/* Input: 																	   */
+/*   global_configuration - global threshold and hysteresis (struct)           */
+/*   ug_configuration  - user groups threshold and hysteresis (struct)         */
+/*   xi_replay_address - runner replay address                                  */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_init(DRV_BPM_GLOBAL_CONFIGURATION    * xi_global_configuration, 
+                                         DRV_BPM_USER_GROUPS_THRESHOLDS  * xi_ug_configuration,
+                                         uint16_t                             xi_replay_address,
+                                         E_DRV_BPM_SPARE_MESSAGE_FORMAT xi_bpm_spare_message_format ) ;
+
+/*******************************************************************************/
+/*fi_bl_drv_bpm_sp_enable					                               */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Source Ports Enable	                                           */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* Source Ports Enable	                                                       */
+/*                                                                             */
+/* Registers:                                                                  */
+/* BPM_SP_EN                                                                   */
+/*                                                                             */
+/* Input:																	   */
+/*                                                                             */
+/*    xi_source_port - One of the BPM source port: GPON, EMAC0-4, RNR_A/B      */
+/*                                                                             */
+/*    xi_enable - enable/ disable                                              */
+/*                                                                             */
+/* Output:  error code                                                         */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*	 DRV_BPM_ERROR_INVALID_SOURCE_PORT - invalid source port   	   */	
+/*   DRV_BPM_ERROR_INVALID_SOURCE_PORT - invalid source port       */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_sp_enable(DRV_BPM_SP_USR xi_source_port, 
+                                                         E_DRV_BPM_ENABLE xi_enable );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_set_global_threshold                                    */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Set BPM Global threshold                                       */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function sets the global Threshold for Allocated Buffers.              */
+/*                                                                             */
+/* Input:																	   */
+/*                                                                             */
+/*   xi_global_threshold - Global Threshold for Allocated Buffers              */
+/*   xi_global_hystersis - Global Buffer Allocation Hysteresis threshold       */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_set_global_threshold ( DRV_BPM_GLOBAL_THRESHOLD xi_global_threshold,
+                                                                      uint32_t xi_global_hysteresis );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_get_global_threshold                                    */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Get BPM Global threshold                                       */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function returns the global Threshold for Allocated Buffers.           */
+/*                                                                             */
+/* Input:																	   */
+/*                                                                             */
+/*   xo_global_threshold -  Global Threshold for Allocated Buffers             */
+/*   xo_global_hysteresis - Global Buffer Allocation Hysteresis threshold      */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_get_global_threshold (DRV_BPM_GLOBAL_THRESHOLD * const xo_global_threshold,
+                                                                     uint32_t * const xo_global_hysteresis );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_set_user_group_thresholds                               */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Set BPM User Group threshold configuration                     */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* Threshold for Allocated Buffers of UG                                       */
+/* Ths register also holds UG0 hysteresis value for ACK/NACK transition setting*/
+/* This register is affected by soft reset.                                    */
+/*                                                                             */
+/* Input:																	   */
+/*	xi_ug - user group 														   */			
+/*  xi_configuration - thresholds configuration for the user group (struct)    */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_set_user_group_thresholds (DRV_BPM_USER_GROUP xi_ug, 
+                                                                          DRV_BPM_USER_GROUP_CONFIGURATION * xi_configuration);
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_get_user_group_thresholds                               */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Get BPM User Group threshold configuration                     */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function returns Threshold for Allocated Buffers of UG                 */
+/*                                                                             */
+/* Input:																	   */
+/*	xi_ug - user group 														   */			
+/*  xo_configuration - thresholds configuration for the user group (struct)    */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_get_user_group_thresholds (DRV_BPM_USER_GROUP xi_ug, 
+                                                                          DRV_BPM_USER_GROUP_CONFIGURATION * const  xo_configuration);
+
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_set_user_group_mapping                                  */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Set User Group Mapping                                         */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function maps a User group for a specific Source port                  */
+/*                                                                             */
+/* Input:                                              			               */
+/*	xi_source_port - One of BPM source ports		                           */
+/*  xi_user_group  - one of BPM User group 0-7                                 */
+/*                                                                             */
+/* Output:  error code                                                         */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*	 DRV_BPM_ERROR_INVALID_SOURCE_PORT - invalid source port   	   */
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_set_user_group_mapping ( DRV_BPM_SP_USR  xi_source_port,
+                                                                        DRV_BPM_USER_GROUP xi_user_group );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_req_buffer                                              */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Request Buffer                                                 */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* cpu requests a free buffer pointer                                          */
+/*                                                                             */
+/* Input:                                                                      */
+/*     xi_source_port - used by CPU for Buffer Request allocation on behalf    */
+/*     another port                                                            */
+/*     xo_bn - returned 14 bits of DDR buffer pointer value                    */
+/*                                                                             */
+/* Output:  error code                                                         */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*	 DRV_BPM_ERROR_BPM_BUSY - BPM busy in previous operation		   */	
+/*	 DRV_BPM_ERROR_NO_FREE_BUFFER - BPM has no free buffer to allocate*/	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_req_buffer(DRV_BPM_SP_USR xi_source_port,
+                                                          uint32_t * const xo_bn);
+
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_set_runner_msg_ctrl                                     */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM Driver - Set Runner message control                                     */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* Enables runner wake-up messages, 										   */
+/* select control bit for transition message and task numbers for wake-up      */
+/* messages to Runners														   */ 
+/*                                                                             */
+/* Registers:                                                                  */
+/* BPM_RNR_MSG_CTRL,BPM_RNR_RPLY_TA                                            */
+/*                                                                             */
+/* Input:																	   */
+/*                                                                             */
+/*  xi_runner_messsage_control_parameters - struct                             */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_set_runner_msg_ctrl(DRV_BPM_RUNNER_MSG_CTRL_PARAMS  * xi_runner_messsage_control_parameters);
+
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_bpm_get_runner_msg_ctrl                                     */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM Driver - Get Runner message control                                     */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* Enables runner wake-up messages, 										   */
+/* select control bit for transition message and task numbers for wake-up      */
+/* messages to Runners														   */
+/*                                                                             */
+/* Registers:                                                                  */
+/* BPM_RNR_MSG_CTRL,BPM_RNR_RPLY_TA                                            */
+/*                                                                             */
+/* Input:																	   */
+/*                                                                             */
+/*  xo_runner_messsage_control_parameters - struct                             */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_BPM_ERROR - error code                                   */
+/*	 DRV_BPM_ERROR_NO_ERROR - no error 					           */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_BPM_ERROR fi_bl_drv_bpm_get_runner_msg_ctrl(DRV_BPM_RUNNER_MSG_CTRL_PARAMS * const xo_runner_messsage_control_parameters);
+
+#endif
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_drv_ih.c b/arch/arm/mach-bcmbca/rdp/rdp_drv_ih.c
new file mode 100755
index 0000000000..24507e3231
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_drv_ih.c
@@ -0,0 +1,1877 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the implementation of the Lilac IH driver               */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+
+#include "rdp_subsystem_common.h"
+#include "rdp_drv_ih.h"
+
+#define IH_ENG_TRIPLE_TAG_DETECTION_BIT_SHIFT 8
+
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+
+/* "all ones" (bitwise) value */
+#define CS_ALL_ONES_VALUE ( 0xFFFFFFFF )
+
+/* bit 12 in an address to common memory, selectes between the two sections */
+#define CS_COMMON_MEMORY_SECTION_SELECTION_BIT  ( 12 )
+
+/* there are 2 registesr which store the classifier-to-class mapping.
+   each register stores mapping of 8 classifiers */
+#define CS_NUMBER_OF_CLASSIFIERS_IN_CLASSIFIER_TO_CLASS_MAPPING_REGISTERS  ( 8 )
+
+/* each register stores configuration of 4 ingress queues */
+#define CS_NUMBER_OF_INGRESS_QUEUES_IN_PRIORITY_AND_CONGESTION_THRESHOLD_REGISTERS  ( 4 )
+
+/* each DSCP-to-TCI table resides in 8 registers */
+#define CS_NUMBER_OF_REGISTERS_OF_DSCP_TO_TCI_TABLE  ( 8 )
+
+/* each register stores 8 entries */
+#define CS_NUMBER_OF_ENTRIES_IN_DSCP_TO_TCI_TABLE_REGISTER  ( 8 )
+
+static  DRV_IH_TARGET_MATRIX_PER_SP_CONFIG trgt_mtrx_sp_shadow[DRV_IH_TARGET_MATRIX_NUMBER_OF_DESTINATION_PORTS] = {};
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Macros definitions                                                         */
+/*                                                                            */
+/******************************************************************************/
+
+/* gets bit #i from a given number */
+#define MS_GET_BIT_I( number , i )   ( ( ( 1 << ( i ) ) & ( number ) ) >> ( i ) )
+/* sets bit #i of a given number to a given value */
+#define MS_SET_BIT_I( number , i , bit_value )   ( ( number ) &= ( ~ ( 1 << ( i ) ) )  , ( number ) |= ( ( bit_value ) << ( i ) ) )
+
+
+/* the following macros are for accessing, using the same macro, a register
+   in a sequence of several identical registers. these macros use arrays of
+   addresses of the corresponding registers. it is needed since the offset
+   betweeen the registers is not uniform */
+
+uint32_t gs_lookup_configuration_lkup_tbl_lut_cfg_address [ DRV_IH_NUMBER_OF_LOOKUP_TABLES ] =
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_ADDRESS
+} ;
+
+
+uint32_t gs_lookup_configuration_lkup_tbl_cam_cfg_address [ DRV_IH_NUMBER_OF_LOOKUP_TABLES ] =
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_ADDRESS
+} ;
+
+
+
+uint32_t gs_lookup_configuration_lkup_tbl_lut_cnxt_cfg_address [ DRV_IH_NUMBER_OF_LOOKUP_TABLES ] =
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_ADDRESS
+} ;
+
+
+
+uint32_t gs_lookup_configuration_lkup_tbl_cam_cnxt_cfg_address [ DRV_IH_NUMBER_OF_LOOKUP_TABLES ] =
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_ADDRESS
+} ;
+
+
+
+uint32_t gs_lookup_configuration_lkup_tbl_key_cfg_address [ DRV_IH_NUMBER_OF_LOOKUP_TABLES ] =
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_ADDRESS
+} ;
+
+
+uint32_t gs_lookup_configuration_lkup_tbl_key_p0_maskl_address [ DRV_IH_NUMBER_OF_LOOKUP_TABLES ] =
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_ADDRESS
+} ;
+
+
+uint32_t gs_lookup_configuration_lkup_tbl_key_p0_maskh_address [ DRV_IH_NUMBER_OF_LOOKUP_TABLES ] =
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_ADDRESS
+} ;
+
+
+uint32_t gs_lookup_configuration_lkup_tbl_key_p1_maskl_address [ DRV_IH_NUMBER_OF_LOOKUP_TABLES ] =
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_ADDRESS
+} ;
+
+
+uint32_t gs_lookup_configuration_lkup_tbl_key_p1_maskh_address [ DRV_IH_NUMBER_OF_LOOKUP_TABLES ] =
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_ADDRESS
+} ;
+
+
+
+uint32_t gs_lookup_configuration_lkup_tbl_gl_mask_address [ DRV_IH_NUMBER_OF_LOOKUP_TABLES ] =
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_ADDRESS ,
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_ADDRESS
+} ;
+
+
+uint32_t gs_general_configuration_ih_class_search_cfg_address [ DRV_IH_NUMBER_OF_CLASSES ] =
+{
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_ADDRESS
+} ;
+
+
+uint32_t gs_general_configuration_ih_class_general_cfg_address [ DRV_IH_NUMBER_OF_CLASSES ] =
+{
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_ADDRESS ,
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_ADDRESS
+} ;
+
+/*** Lookup table configuration ***/
+
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TLUT_CFG_READ_I( r , i )                  READ_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_lut_cfg_address [ i ] ) , (r) )
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TLUT_CFG_WRITE_I( v , i )                 WRITE_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_lut_cfg_address [ i ] ) , (v) )
+                                                                                         
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TCAM_CFG_READ_I( r , i )                  READ_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_cam_cfg_address [ i ] ) , (r) )
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TCAM_CFG_WRITE_I( v , i )                 WRITE_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_cam_cfg_address [ i ] ) , (v) )
+                                                                                         
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TLUT_CNXT_CFG_READ_I( r , i )             READ_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_lut_cnxt_cfg_address [ i ] ) , (r) )
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TLUT_CNXT_CFG_WRITE_I( v , i )            WRITE_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_lut_cnxt_cfg_address [ i ] ) , (v) )
+
+#define MS_DRV_IH_LOOKUP_LOOKUP_CONFIGURATION_LKUP_TCAM_CNXT_CFG_READ_I( r , i )      READ_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_cam_cnxt_cfg_address [ i ] ) , (r) )
+#define MS_DRV_IH_LOOKUP_LOOKUP_CONFIGURATION_LKUP_TCAM_CNXT_CFG_WRITE_I( v , i )     WRITE_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_cam_cnxt_cfg_address [ i ] ) , (v) )
+
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_CFG_READ_I( r , i )                  READ_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_key_cfg_address [ i ] ) , (r) )
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_CFG_WRITE_I( v , i )                 WRITE_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_key_cfg_address [ i ] ) , (v) )
+
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P0_MASKL_READ_I( r , i )             READ_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_key_p0_maskl_address [ i ] ) , (r) )
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P0_MASKL_WRITE_I( v , i )            WRITE_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_key_p0_maskl_address [ i ] ) , (v) )
+                                                                                         
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P0_MASKH_READ_I( r , i )             READ_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_key_p0_maskh_address [ i ] ) , (r) )
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P0_MASKH_WRITE_I( v , i )            WRITE_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_key_p0_maskh_address [ i ] ) , (v) )
+                                                                                         
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P1_MASKL_READ_I( r , i )             READ_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_key_p1_maskl_address [ i ] ) , (r) )
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P1_MASKL_WRITE_I( v , i )            WRITE_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_key_p1_maskl_address [ i ] ) , (v) )
+                                                                                         
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P1_MASKH_READ_I( r , i )             READ_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_key_p1_maskh_address [ i ] ) , (r) )
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P1_MASKH_WRITE_I( v , i )            WRITE_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_key_p1_maskh_address [ i ] ) , (v) )
+
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_READ_I( r , i )                 READ_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_gl_mask_address [ i ] ) , (r) )
+#define MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_WRITE_I( v , i )                WRITE_32( DEVICE_ADDRESS( gs_lookup_configuration_lkup_tbl_gl_mask_address [ i ] ) , (v) )
+
+
+/*** Class configuration ***/
+
+#define MS_DRV_IH_GENERAL_CONFIGURATION_IH_CLASS_SEARCH_CFG_READ_I( r , i )              READ_32( DEVICE_ADDRESS( gs_general_configuration_ih_class_search_cfg_address [ i ] ) , (r) )
+#define MS_DRV_IH_GENERAL_CONFIGURATION_IH_CLASS_SEARCH_CFG_WRITE_I( v , i )             WRITE_32( DEVICE_ADDRESS( gs_general_configuration_ih_class_search_cfg_address [ i ] ) , (v) )
+
+#define MS_DRV_IH_GENERAL_CONFIGURATION_IH_CLASS_GENERAL_CFG_READ_I( r , i )             READ_32( DEVICE_ADDRESS( gs_general_configuration_ih_class_general_cfg_address [ i ] ) , (r) )
+#define MS_DRV_IH_GENERAL_CONFIGURATION_IH_CLASS_GENERAL_CFG_WRITE_I( v , i )            WRITE_32( DEVICE_ADDRESS( gs_general_configuration_ih_class_general_cfg_address [ i ] ) , (v) )
+
+/******************************************************************************/
+/* Common memory section                                                      */
+/* There are 2 sections in the runners common memory: A and B.                */
+/******************************************************************************/
+typedef enum
+{
+    CS_COMMON_MEMORY_SECTION_A ,
+    CS_COMMON_MEMORY_SECTION_B
+}
+DRV_IH_COMMON_MEMORY_SECTION_DTS ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Global variables definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+int32_t gs_class_is_configured [ DRV_IH_NUMBER_OF_CLASSES ] = { 0 } ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Functions prototypes                                                       */
+/*                                                                            */
+/******************************************************************************/
+
+int32_t f_check_item_index( uint32_t xi_item_index ,
+                                    uint32_t xi_number_of_items ) ;
+
+DRV_IH_ERROR f_configure_lut_all_parameters ( uint8_t xi_table_index ,
+                                                           const DRV_IH_LOOKUP_TABLE_60_BIT_KEY_CONFIG * xi_lookup_table_60_bit_key_config ,
+                                                           int32_t xi_five_tupple_enable ) ;
+
+
+DRV_IH_ERROR fi_get_lut_all_parameters ( uint8_t xi_table_index ,
+                                                      DRV_IH_LOOKUP_TABLE_60_BIT_KEY_CONFIG * const xo_lookup_table_60_bit_key_config ,
+                                                      int32_t * const xo_five_tupple_enable ) ;
+
+DRV_IH_COMMON_MEMORY_SECTION_DTS f_get_lookup_table_location( uint8_t xi_table_index ) ;
+
+int32_t f_verify_class_search_validity( DRV_IH_CLASS_SEARCH xi_class_search ,
+                                                DRV_IH_COMMON_MEMORY_SECTION_DTS xi_desired_lookup_table_location ) ;
+
+/* In 120 bit key lookup table, each key value actually occupies two table
+   entries. therefore it is needed to multiply by 2 the maximal search depth
+   and table size parameters obtained from the user. */
+int32_t f_multiply_by_2_table_size ( DRV_IH_LOOKUP_TABLE_SIZE xi_table_size ,
+                                             DRV_IH_LOOKUP_TABLE_SIZE * xo_multiplied_table_size ) ;
+int32_t f_divide_by_2_table_size ( DRV_IH_LOOKUP_TABLE_SIZE xi_table_size ,
+                                           DRV_IH_LOOKUP_TABLE_SIZE * xo_divided_table_size ) ;
+int32_t f_multiply_by_2_maximal_search_depth ( DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH xi_maximal_search_depth ,
+                                                       DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH * xo_multiplied_maximal_search_depth ) ;
+int32_t f_divide_by_2_maximal_search_depth ( DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH xi_maximal_search_depth ,
+                                                     DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH * xo_divided_maximal_search_depth ) ;
+
+void p_mac_address_array_to_hw_format ( uint8_t xi_mac_address [ DRV_IH_NUMBER_OF_BYTES_IN_MAC_ADDRESS ] ,
+                                        uint32_t * xo_address_4_ls_bytes ,
+                                        uint16_t * xo_addres_2_ms_bytes ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Init & cleanup module, license                                             */
+/*                                                                            */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/* API functions implementations                                              */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_general_configuration                                   */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set general configuration                                    */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets general configuration of the IH block.                */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ih_general_config - IH general configuration.                         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_general_configuration ( const DRV_IH_GENERAL_CONFIG * xi_ih_general_config )
+{
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR rnra_ihrsp_addr ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR rnrb_ihrsp_addr ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR rnra_cngs_rpt_addr ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR rnrb_cngs_rpt_addr ;
+    IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG rnr_cngs_rpt_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG ih_misc_cfg ;
+
+
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_READ( rnra_ihrsp_addr ) ;
+    rnra_ihrsp_addr.rnra_ihrsp_addr = xi_ih_general_config->runner_a_ih_response_address ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_WRITE( rnra_ihrsp_addr ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_READ( rnrb_ihrsp_addr ) ;
+    rnrb_ihrsp_addr.rnrb_ihrsp_addr = xi_ih_general_config->runner_b_ih_response_address ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_WRITE( rnrb_ihrsp_addr ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_READ( rnra_cngs_rpt_addr ) ;
+    rnra_cngs_rpt_addr.rnra_cngs_rpt_addr = xi_ih_general_config->runner_a_ih_congestion_report_address ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_WRITE( rnra_cngs_rpt_addr ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_READ( rnrb_cngs_rpt_addr ) ;
+    rnrb_cngs_rpt_addr.rnrb_cngs_rpt_addr = xi_ih_general_config->runner_b_ih_congestion_report_address ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_WRITE( rnrb_cngs_rpt_addr ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_READ( rnr_cngs_rpt_cfg ) ;
+    rnr_cngs_rpt_cfg.rnra_cngs_rpt_en = xi_ih_general_config->runner_a_ih_congestion_report_enable ;
+    rnr_cngs_rpt_cfg.rnrb_cngs_rpt_en = xi_ih_general_config->runner_b_ih_congestion_report_enable ;
+    IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_WRITE( rnr_cngs_rpt_cfg ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_READ( ih_misc_cfg ) ;
+    ih_misc_cfg.lut_en_direct_mode = xi_ih_general_config->lut_searches_enable_in_direct_mode ;
+    ih_misc_cfg.sn_stamp_dm_pkt = xi_ih_general_config->sn_stamping_enable_in_direct_mode ;
+    ih_misc_cfg.hlength_min_trsh = xi_ih_general_config->header_length_minimum ;
+    ih_misc_cfg.cngs_dscrd_dis = xi_ih_general_config->congestion_discard_disable ;
+    ih_misc_cfg.nval_cam_search_en = xi_ih_general_config->cam_search_enable_upon_invalid_lut_entry ;
+    IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_WRITE( ih_misc_cfg ) ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL ( fi_bl_drv_ih_set_general_configuration ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_packet_header_offsets                                   */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set packet header offsets                                    */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets packet header offset for each physical port.          */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_packet_header_offsets - Packet header offsets                         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_packet_header_offsets ( const DRV_IH_PACKET_HEADER_OFFSETS * xi_packet_header_offsets )
+{
+    IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG phl_offset_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG phh_offset_cfg ;
+
+
+    IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_READ( phl_offset_cfg ) ;
+    phl_offset_cfg.eth0_ph_offset = xi_packet_header_offsets->eth0_packet_header_offset ;
+    phl_offset_cfg.eth1_ph_offset = xi_packet_header_offsets->eth1_packet_header_offset ;
+    phl_offset_cfg.eth2_ph_offset = xi_packet_header_offsets->eth2_packet_header_offset ;
+    phl_offset_cfg.eth3_ph_offset = xi_packet_header_offsets->eth3_packet_header_offset ;
+    IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_WRITE( phl_offset_cfg ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_READ( phh_offset_cfg ) ;
+    phh_offset_cfg.eth4_ph_offset = xi_packet_header_offsets->eth4_packet_header_offset ;
+    phh_offset_cfg.gpon_ph_offset = xi_packet_header_offsets->gpon_packet_header_offset ;
+    phh_offset_cfg.rnra_ph_offset = xi_packet_header_offsets->runner_a_packet_header_offset ;
+    phh_offset_cfg.rnrb_ph_offset = xi_packet_header_offsets->runner_b_packet_header_offset ;
+    IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_WRITE( phh_offset_cfg ) ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL ( fi_bl_drv_ih_set_packet_header_offsets ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_runner_buffers_configuration                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Runner Buffers configuration                             */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets runner-buffers related configuration, for each        */
+/*   runner.                                                                  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_runner_buffers_config - Runner Buffers Configuration                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_runner_buffers_configuration ( const DRV_IH_RUNNER_BUFFERS_CONFIG * xi_runner_buffers_config )
+{
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE rnra_rb_base ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE rnrb_rb_base ;
+    IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG rbpm_bat_cfg ;
+
+
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_READ( rnra_rb_base ) ;
+    rnra_rb_base.rnra_common_rb_base = xi_runner_buffers_config->runner_a_ih_managed_rb_base_address ;
+    rnra_rb_base.rnra_asigned_rb_base = xi_runner_buffers_config->runner_a_runner_managed_rb_base_address ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_WRITE( rnra_rb_base ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_READ( rnrb_rb_base ) ;
+    rnrb_rb_base.rnrb_common_rb_base = xi_runner_buffers_config->runner_b_ih_managed_rb_base_address ;
+    rnrb_rb_base.rnrb_asigned_rb_base = xi_runner_buffers_config->runner_b_runner_managed_rb_base_address ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_WRITE( rnrb_rb_base ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_READ( rbpm_bat_cfg ) ;
+    rbpm_bat_cfg.rnra_bpm_bat = xi_runner_buffers_config->runner_a_maximal_number_of_buffers ;
+    rbpm_bat_cfg.rnrb_bpm_bat = xi_runner_buffers_config->runner_b_maximal_number_of_buffers ;
+    IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_WRITE( rbpm_bat_cfg ) ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL ( fi_bl_drv_ih_set_runner_buffers_configuration ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_runners_load_thresholds                                 */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Runners Load Thresholds                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets thresholds related to runner load, for each runner.   */
+/*   The thresholds are in number of occupied Runner Buffers.                 */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_runners_load_thresholds - Runners Load Thresholds (in number of       */
+/*     occupied Runner Buffers)                                               */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_runners_load_thresholds ( const DRV_IH_RUNNERS_LOAD_THRESHOLDS * xi_runners_load_thresholds )
+{
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG rnra_cngs_trsh_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG rnrb_cngs_trsh_cfg ;
+
+
+    if ( xi_runners_load_thresholds->runner_a_high_congestion_threshold > DRV_IH_MAXIMAL_VALUE_FOR_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS )
+    {
+        return ( DRV_IH_ERROR_INVALID_NUMBER_OF_RUNNER_BUFFERS ) ;
+    }
+
+    if ( xi_runners_load_thresholds->runner_b_high_congestion_threshold > DRV_IH_MAXIMAL_VALUE_FOR_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS )
+    {
+        return ( DRV_IH_ERROR_INVALID_NUMBER_OF_RUNNER_BUFFERS ) ;
+    }
+
+    if ( xi_runners_load_thresholds->runner_a_exclusive_congestion_threshold > DRV_IH_MAXIMAL_VALUE_FOR_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS )
+    {
+        return ( DRV_IH_ERROR_INVALID_NUMBER_OF_RUNNER_BUFFERS ) ;
+    }
+
+    if ( xi_runners_load_thresholds->runner_b_exclusive_congestion_threshold > DRV_IH_MAXIMAL_VALUE_FOR_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS )
+    {
+        return ( DRV_IH_ERROR_INVALID_NUMBER_OF_RUNNER_BUFFERS ) ;
+    }
+
+    if ( xi_runners_load_thresholds->runner_a_load_balancing_threshold > DRV_IH_MAXIMAL_VALUE_FOR_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS )
+    {
+        return ( DRV_IH_ERROR_INVALID_NUMBER_OF_RUNNER_BUFFERS ) ;
+    }
+
+    if ( xi_runners_load_thresholds->runner_b_load_balancing_threshold > DRV_IH_MAXIMAL_VALUE_FOR_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS )
+    {
+        return ( DRV_IH_ERROR_INVALID_NUMBER_OF_RUNNER_BUFFERS ) ;
+    }
+
+    if ( xi_runners_load_thresholds->runner_a_load_balancing_hysteresis > DRV_IH_MAXIMAL_VALUE_FOR_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS )
+    {
+        return ( DRV_IH_ERROR_INVALID_NUMBER_OF_RUNNER_BUFFERS ) ;
+    }
+
+    if ( xi_runners_load_thresholds->runner_b_load_balancing_hysteresis > DRV_IH_MAXIMAL_VALUE_FOR_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS )
+    {
+        return ( DRV_IH_ERROR_INVALID_NUMBER_OF_RUNNER_BUFFERS ) ;
+    }
+
+
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_READ( rnra_cngs_trsh_cfg ) ;
+    rnra_cngs_trsh_cfg.high_cngs_trsh = xi_runners_load_thresholds->runner_a_high_congestion_threshold ;
+    rnra_cngs_trsh_cfg.excl_cngs_trsh = xi_runners_load_thresholds->runner_a_exclusive_congestion_threshold ;
+    rnra_cngs_trsh_cfg.lb_thsh = xi_runners_load_thresholds->runner_a_load_balancing_threshold ;
+    rnra_cngs_trsh_cfg.lb_hyst = xi_runners_load_thresholds->runner_a_load_balancing_hysteresis ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_WRITE( rnra_cngs_trsh_cfg ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_READ( rnrb_cngs_trsh_cfg ) ;
+    rnrb_cngs_trsh_cfg.high_cngs_trsh = xi_runners_load_thresholds->runner_b_high_congestion_threshold ;
+    rnrb_cngs_trsh_cfg.excl_cngs_trsh = xi_runners_load_thresholds->runner_b_exclusive_congestion_threshold ;
+    rnrb_cngs_trsh_cfg.lb_thsh = xi_runners_load_thresholds->runner_b_load_balancing_threshold ;
+    rnrb_cngs_trsh_cfg.lb_hyst = xi_runners_load_thresholds->runner_b_load_balancing_hysteresis ;
+    IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_WRITE( rnrb_cngs_trsh_cfg ) ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL ( fi_bl_drv_ih_set_runners_load_thresholds ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_route_addresses                                         */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Route Addresses                                          */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets route address for each physical port. The route       */
+/*   address is used for broad-bus access for sending responses, message and  */
+/*   data.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_route_addresses - Route Addresses                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_route_addresses ( const DRV_IH_ROUTE_ADDRESSES * xi_route_addresses )
+{
+    IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG raddr0_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG raddr1_cfg ;
+
+
+    IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_READ( raddr0_cfg ) ;
+    raddr0_cfg.eth0_raddr = xi_route_addresses->eth0_route_address ;
+    raddr0_cfg.eth1_raddr = xi_route_addresses->eth1_route_address ;
+    raddr0_cfg.eth2_raddr = xi_route_addresses->eth2_route_address ;
+    raddr0_cfg.eth3_raddr = xi_route_addresses->eth3_route_address ;
+    IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_WRITE( raddr0_cfg ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_READ( raddr1_cfg ) ;
+    raddr1_cfg.eth4_raddr = xi_route_addresses->eth4_route_address ;
+    raddr1_cfg.gpon_raddr = xi_route_addresses->gpon_route_address ;
+    raddr1_cfg.rnra_raddr = xi_route_addresses->runner_a_route_address ;
+    raddr1_cfg.rnrb_raddr = xi_route_addresses->runner_b_route_address ;
+    IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_WRITE( raddr1_cfg ) ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL ( fi_bl_drv_ih_set_route_addresses ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_logical_ports_configuration                             */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Logical Ports Configuration                              */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets configuration of the following logical ports:         */
+/*   Ethernet 0-4, GPON, Runner A, Runner B and PCIE 0-1. The following       */
+/*   parameters are configured per port: Parsing layer depth, Proprietary tag */
+/*   size.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_logical_ports_config - Logical Ports Configuration                    */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_logical_ports_configuration ( const DRV_IH_LOGICAL_PORTS_CONFIG * xi_logical_ports_config )
+{
+    IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG parse_layer_per_port_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0 prop_size_per_port_cfg0 ;
+    IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1 prop_size_per_port_cfg1 ;
+
+
+    IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_READ( parse_layer_per_port_cfg ) ;
+    parse_layer_per_port_cfg.eth0_parse_layer_stg = xi_logical_ports_config->eth0_config.parsing_layer_depth ;
+    parse_layer_per_port_cfg.eth1_parse_layer_stg = xi_logical_ports_config->eth1_config.parsing_layer_depth ;
+    parse_layer_per_port_cfg.eth2_parse_layer_stg = xi_logical_ports_config->eth2_config.parsing_layer_depth ;
+    parse_layer_per_port_cfg.eth3_parse_layer_stg = xi_logical_ports_config->eth3_config.parsing_layer_depth ;
+    parse_layer_per_port_cfg.eth4_parse_layer_stg = xi_logical_ports_config->eth4_config.parsing_layer_depth ;
+    parse_layer_per_port_cfg.gpon_parse_layer_stg = xi_logical_ports_config->gpon_config.parsing_layer_depth ;
+    parse_layer_per_port_cfg.rnra_parse_layer_stg = xi_logical_ports_config->runner_a_config.parsing_layer_depth ;
+    parse_layer_per_port_cfg.rnrb_parse_layer_stg = xi_logical_ports_config->runner_b_config.parsing_layer_depth ;
+    parse_layer_per_port_cfg.pcie0_parse_layer_stg = xi_logical_ports_config->pcie0_config.parsing_layer_depth ;
+    parse_layer_per_port_cfg.pcie1_parse_layer_stg = xi_logical_ports_config->pcie1_config.parsing_layer_depth ;
+    IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_WRITE( parse_layer_per_port_cfg ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_READ( prop_size_per_port_cfg0 ) ;
+    prop_size_per_port_cfg0.eth0_prop_tag_size = xi_logical_ports_config->eth0_config.proprietary_tag_size ;
+    prop_size_per_port_cfg0.eth1_prop_tag_size = xi_logical_ports_config->eth1_config.proprietary_tag_size ;
+    prop_size_per_port_cfg0.eth2_prop_tag_size = xi_logical_ports_config->eth2_config.proprietary_tag_size ;
+    prop_size_per_port_cfg0.eth3_prop_tag_size = xi_logical_ports_config->eth3_config.proprietary_tag_size ;
+    prop_size_per_port_cfg0.eth4_prop_tag_size = xi_logical_ports_config->eth4_config.proprietary_tag_size ;
+    prop_size_per_port_cfg0.gpon_prop_tag_size = xi_logical_ports_config->gpon_config.proprietary_tag_size ;
+    prop_size_per_port_cfg0.rnra_prop_tag_size = xi_logical_ports_config->runner_a_config.proprietary_tag_size ;
+    prop_size_per_port_cfg0.rnrb_prop_tag_size = xi_logical_ports_config->runner_b_config.proprietary_tag_size ;
+    IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_WRITE( prop_size_per_port_cfg0 ) ;
+
+    IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_READ( prop_size_per_port_cfg1 ) ;
+    prop_size_per_port_cfg1.pcie0_prop_tag_size = xi_logical_ports_config->pcie0_config.proprietary_tag_size ;
+    prop_size_per_port_cfg1.pcie1_prop_tag_size = xi_logical_ports_config->pcie1_config.proprietary_tag_size ;
+    IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_WRITE( prop_size_per_port_cfg1 ) ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL ( fi_bl_drv_ih_set_logical_ports_configuration ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_lut_60_bit_key                                    */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure Lookup Table 60 bit key                            */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures a lookup table with 60-bit key. There is a      */
+/*   total of 10 tables. Note that when configuring a lookup table with       */
+/*   120-bit key (with dedicated API), it occupies 2 tables. The lookup key   */
+/*   is obtained by ORing two 60-bit parts taken from the parser result. Each */
+/*   part has a configurable offset, and optionally a shift & rotate          */
+/*   operation. Initially 64 bits are taken from the configured offset, then  */
+/*   shift & rotate is optionally done, then the 4 MS-bits are omitted. Then  */
+/*   each part is masked with its own mask. Then ORing the left 60 bits of    */
+/*   the 2 parts yields the key. Then a key-extension can optionally be done, */
+/*   i.e. ORing the MS-bits of the key with one of the following values: (1)  */
+/*   5-bit Source Port from Header Descriptor. (2) 8-bit GEM Flow ID from     */
+/*   Header Descriptor. (3) 1-bit WAN/LAN indication extracted from           */
+/*   configuration of the source port. The global mask is applied on both key */
+/*   & LUT entry when comparing between them. Move indication: When "Source   */
+/*   port search enable" parameter is enabled, additional comparison will be  */
+/*   done, between source-port (from Header descriptor) and bits 56:52 of LUT */
+/*   entry, where source-port value should reside. In this case, the global   */
+/*   mask must mask these bits for the regular comparison between the key and */
+/*   LUT entry, which would be a MAC address comparison. If both comparisons  */
+/*   match, the result would be "hit". If only MAC address comparison         */
+/*   matches, the result would be "move".                                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_table_index - Table index                                             */
+/*                                                                            */
+/*   xi_lookup_table_60_bit_key_config - Lookup table 60 bit key              */
+/*     configuration                                                          */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_lut_60_bit_key ( uint8_t xi_table_index ,
+                                                            const DRV_IH_LOOKUP_TABLE_60_BIT_KEY_CONFIG * xi_lookup_table_60_bit_key_config )
+{
+    DRV_IH_ERROR error_code ;
+
+    /* five_tupple_enable parameter is false here since it's a 60 bit key */
+    error_code = f_configure_lut_all_parameters( xi_table_index ,
+                                                 xi_lookup_table_60_bit_key_config ,
+                                                 0 ) ;
+
+    return ( error_code ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_ih_configure_lut_60_bit_key ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_class                                             */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure Class                                              */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures an IH class. Ingress handler class is type of   */
+/*   ingress traffic, e.g. IPTV, bridged, routed. Each class includes         */
+/*   predefined set of settings, such as: target runner, destination memory,  */
+/*   QoS, definition of look-up searches. There are up to 16 classes. Each    */
+/*   physical port has a default class (For GPON port, default class is per   */
+/*   GEM flow). IH may override the default class according to                */
+/*   enable-override configuration and to classification based on reduced     */
+/*   Parser results, called "Classifier Key Word" (Parser Summary Word plus   */
+/*   source port). Default classes and override-enable configurations are in  */
+/*   BBH. In runner flow, runner assigns an initial class (which can be       */
+/*   overridden by IH). Class override is done using classifiers, which are   */
+/*   configured using Configure Classifier API.                               */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_class_index - Class index                                             */
+/*                                                                            */
+/*   xi_class_config - Class Configuration                                    */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*     DRV_IH_ERROR_CLASS_SEARCH_AND_LUT_LOCATION_MISMATCH - mismatch      */
+/*       between class search and lookup table location                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_class ( uint8_t xi_class_index ,
+                                                   const DRV_IH_CLASS_CONFIG * xi_class_config )
+{
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG ih_class_search_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG ih_class_general_cfg ;
+    int32_t result ;
+
+    result = f_check_item_index( xi_class_index ,
+                                 DRV_IH_NUMBER_OF_CLASSES ) ;
+    if ( result == 0 )
+    {
+        return ( DRV_IH_ERROR_INVALID_INDEX ) ;
+    }
+
+    result = f_check_item_index( xi_class_config->dscp_to_tci_table_index ,
+                                 DRV_IH_NUMBER_OF_DSCP_TO_TCI_TABLES ) ;
+    if ( result == 0 )
+    {
+        return ( DRV_IH_ERROR_INVALID_INDEX ) ;
+    }
+
+    /* Tables used for searches 1 & 2 must be located at common memory A */
+
+    result = f_verify_class_search_validity( xi_class_config->class_search_1 ,
+                                             CS_COMMON_MEMORY_SECTION_A ) ;
+    if ( result == 0 )
+    {
+        return ( DRV_IH_ERROR_CLASS_SEARCH_AND_LUT_LOCATION_MISMATCH ) ;
+    }
+
+    result = f_verify_class_search_validity( xi_class_config->class_search_2 ,
+                                             CS_COMMON_MEMORY_SECTION_A ) ;
+    if ( result == 0 )
+    {
+        return ( DRV_IH_ERROR_CLASS_SEARCH_AND_LUT_LOCATION_MISMATCH ) ;
+    }
+
+    /* Tables used for searches 3 & 4 must be located at common memory B */
+
+    result = f_verify_class_search_validity( xi_class_config->class_search_3 ,
+                                             CS_COMMON_MEMORY_SECTION_B ) ;
+    if ( result == 0 )
+    {
+        return ( DRV_IH_ERROR_CLASS_SEARCH_AND_LUT_LOCATION_MISMATCH ) ;
+    }
+
+    result = f_verify_class_search_validity( xi_class_config->class_search_4 ,
+                                             CS_COMMON_MEMORY_SECTION_B ) ;
+    if ( result == 0 )
+    {
+        return ( DRV_IH_ERROR_CLASS_SEARCH_AND_LUT_LOCATION_MISMATCH ) ;
+    }
+
+    MS_DRV_IH_GENERAL_CONFIGURATION_IH_CLASS_SEARCH_CFG_READ_I( ih_class_search_cfg , xi_class_index ) ;
+    ih_class_search_cfg.search1_lkup_tbl_ref = xi_class_config->class_search_1 ;
+    ih_class_search_cfg.search2_lkup_tbl_ref = xi_class_config->class_search_2 ;
+    ih_class_search_cfg.search3_lkup_tbl_ref = xi_class_config->class_search_3 ;
+    ih_class_search_cfg.search4_lkup_tbl_ref = xi_class_config->class_search_4 ;
+    ih_class_search_cfg.dp_extr_cfg = xi_class_config->destination_port_extraction ;
+    ih_class_search_cfg.drop_on_miss_extr_cfg = xi_class_config->drop_on_miss ;
+    ih_class_search_cfg.qos_extr_cfg = xi_class_config->ingress_qos_override ;
+    MS_DRV_IH_GENERAL_CONFIGURATION_IH_CLASS_SEARCH_CFG_WRITE_I( ih_class_search_cfg , xi_class_index ) ;
+
+    MS_DRV_IH_GENERAL_CONFIGURATION_IH_CLASS_GENERAL_CFG_READ_I( ih_class_general_cfg , xi_class_index ) ;
+    ih_class_general_cfg.dscp2tci_trans_tbl = xi_class_config->dscp_to_tci_table_index ;
+    ih_class_general_cfg.dm_default = xi_class_config->direct_mode_default ;
+    ih_class_general_cfg.dm_override = xi_class_config->direct_mode_override ;
+    ih_class_general_cfg.tm_default = xi_class_config->target_memory_default ;
+    ih_class_general_cfg.tm_override = xi_class_config->target_memory_override ;
+    ih_class_general_cfg.qos_default = xi_class_config->ingress_qos_default ;
+    /* qos_override paramter is actually redundant (qos_extr_cfg is sufficient), so it is not exposed to the user */
+    ih_class_general_cfg.qos_override = ( xi_class_config->ingress_qos_override == DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED ? 0 : 1 ) ;
+    ih_class_general_cfg.tr_default = xi_class_config->target_runner_default ;
+    ih_class_general_cfg.rnr_ovr_dm = xi_class_config->target_runner_override_in_direct_mode ;
+    ih_class_general_cfg.rnr_default_dm = xi_class_config->target_runner_for_direct_mode ;
+    ih_class_general_cfg.lb_en = xi_class_config->load_balancing_enable ;
+    ih_class_general_cfg.pref_lb_en = xi_class_config->preference_load_balancing_enable ;
+    MS_DRV_IH_GENERAL_CONFIGURATION_IH_CLASS_GENERAL_CFG_WRITE_I( ih_class_general_cfg , xi_class_index ) ;
+
+    gs_class_is_configured [ xi_class_index ] = 1 ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_ih_configure_class ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_source_port_to_ingress_queue_mapping                    */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set source port to ingress queue mapping                     */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets the mapping of physical source ports (eth0-4, GPON,   */
+/*   runner A, runner B) to ingress queues. There are 8 ingress queues. BBH   */
+/*   or runner (in case of runner flow) writes the Header Descriptor to one   */
+/*   of these queues, according to the configuration of the source port.      */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_source_port_to_ingress_queue_mapping - Source port to ingress queue   */
+/*     mapping                                                                */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_source_port_to_ingress_queue_mapping ( const DRV_IH_SOURCE_PORT_TO_INGRESS_QUEUE_MAPPING * xi_source_port_to_ingress_queue_mapping )
+{
+    IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG sp2iq_map_cfg ;
+
+
+    if ( ( xi_source_port_to_ingress_queue_mapping->eth0_ingress_queue >= DRV_IH_NUMBER_OF_INGRESS_QUEUES ) ||
+         ( xi_source_port_to_ingress_queue_mapping->eth1_ingress_queue >= DRV_IH_NUMBER_OF_INGRESS_QUEUES ) ||
+         ( xi_source_port_to_ingress_queue_mapping->eth2_ingress_queue >= DRV_IH_NUMBER_OF_INGRESS_QUEUES ) ||
+         ( xi_source_port_to_ingress_queue_mapping->eth3_ingress_queue >= DRV_IH_NUMBER_OF_INGRESS_QUEUES ) ||
+         ( xi_source_port_to_ingress_queue_mapping->eth4_ingress_queue >= DRV_IH_NUMBER_OF_INGRESS_QUEUES ) ||
+         ( xi_source_port_to_ingress_queue_mapping->gpon_ingress_queue >= DRV_IH_NUMBER_OF_INGRESS_QUEUES ) ||
+         ( xi_source_port_to_ingress_queue_mapping->runner_a_ingress_queue >= DRV_IH_NUMBER_OF_INGRESS_QUEUES ) ||
+         ( xi_source_port_to_ingress_queue_mapping->runner_b_ingress_queue >= DRV_IH_NUMBER_OF_INGRESS_QUEUES ) )
+    {
+        return ( DRV_IH_ERROR_INVALID_INGRESS_QUEUE ) ;
+    }
+
+
+    IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_READ( sp2iq_map_cfg ) ;
+    sp2iq_map_cfg.eth0_iq_map = xi_source_port_to_ingress_queue_mapping->eth0_ingress_queue ;
+    sp2iq_map_cfg.eth1_iq_map = xi_source_port_to_ingress_queue_mapping->eth1_ingress_queue ;
+    sp2iq_map_cfg.eth2_iq_map = xi_source_port_to_ingress_queue_mapping->eth2_ingress_queue ;
+    sp2iq_map_cfg.eth3_iq_map = xi_source_port_to_ingress_queue_mapping->eth3_ingress_queue ;
+    sp2iq_map_cfg.eth4_iq_map = xi_source_port_to_ingress_queue_mapping->eth4_ingress_queue ;
+    sp2iq_map_cfg.gpon_iq_map = xi_source_port_to_ingress_queue_mapping->gpon_ingress_queue ;
+    sp2iq_map_cfg.rnra_iq_map = xi_source_port_to_ingress_queue_mapping->runner_a_ingress_queue ;
+    sp2iq_map_cfg.rnrb_iq_map = xi_source_port_to_ingress_queue_mapping->runner_b_ingress_queue ;
+    IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_WRITE( sp2iq_map_cfg ) ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_ih_set_source_port_to_ingress_queue_mapping ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_ingress_queue                                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure ingress queue                                      */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures an ingress queue. There are 8 queues. All of    */
+/*   them reside in the same Ingress-queue (IQ) array of 16 entries (ingress  */
+/*   buffers). E.g. queue 0 occupies entries 0-1, queue 1 occupies entries    */
+/*   2-3, etc.                                                                */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ingress_queue_index - Ingress queue index                             */
+/*                                                                            */
+/*   xi_ingress_queue_config - Ingress queue configuration                    */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_ingress_queue ( uint8_t xi_ingress_queue_index ,
+                                                           const DRV_IH_INGRESS_QUEUE_CONFIG * xi_ingress_queue_config )
+{
+    IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG iq_base_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG iq_size_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG iq_weight_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG iql_prior_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG iqh_prior_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG iql_cngs_thrs_cfg ;
+    IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG iqh_cngs_thrs_cfg ;
+    int32_t result ;
+    uint8_t queue_size_encoding ;
+
+
+    result = f_check_item_index( xi_ingress_queue_index ,
+                                 DRV_IH_NUMBER_OF_INGRESS_QUEUES ) ;
+    if ( result == 0 )
+    {
+        return ( DRV_IH_ERROR_INVALID_INDEX ) ;
+    }
+
+    if ( xi_ingress_queue_config->base_location >= DRV_IH_INGRESS_QUEUES_ARRAY_SIZE )
+    {
+        return ( DRV_IH_ERROR_INVALID_INGRESS_QUEUE_BASE_LOCATION ) ;
+    }
+
+    if ( ( xi_ingress_queue_config->size > DRV_IH_INGRESS_QUEUES_ARRAY_SIZE ) ||
+         ( xi_ingress_queue_config->size < DRV_IH_MINIMAL_INGRESS_QUEUE_SIZE) )
+    {
+        return ( DRV_IH_ERROR_INVALID_INGRESS_QUEUE_SIZE ) ;
+    }
+
+    if ( xi_ingress_queue_config->priority > DRV_IH_MAXIMAL_INGRESS_QUEUE_PRIORITY )
+    {
+        return ( DRV_IH_ERROR_INVALID_INGRESS_QUEUE_PRIORITY ) ;
+    }
+
+    if ( xi_ingress_queue_config->weight > DRV_IH_MAXIMAL_INGRESS_QUEUE_WEIGHT )
+    {
+        return ( DRV_IH_ERROR_INVALID_INGRESS_QUEUE_WEIGHT ) ;
+    }
+
+    if ( xi_ingress_queue_config->congestion_threshold > DRV_IH_MAXIMAL_INGRESS_QUEUE_CONGESTION_THRESHOLD )
+    {
+        return ( DRV_IH_ERROR_INVALID_NUMBER_OF_RUNNER_BUFFERS ) ;
+    }
+
+
+    /* in HW, the value 0 for size means 16 (it is 4-bit field) */
+    queue_size_encoding = xi_ingress_queue_config->size ;
+    if ( queue_size_encoding == DRV_IH_INGRESS_QUEUES_ARRAY_SIZE )
+    {
+        queue_size_encoding = 0 ;
+    }
+
+
+    /* handle configuration which resides in one register for all queues */
+
+    IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_READ( iq_base_cfg ) ;
+    IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_READ( iq_size_cfg ) ;
+    IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_READ( iq_weight_cfg ) ;
+
+    switch ( xi_ingress_queue_index )
+    {
+    case 0:
+        iq_base_cfg.iq0_base = xi_ingress_queue_config->base_location ;
+        iq_size_cfg.iq0_size = queue_size_encoding ;
+        iq_weight_cfg.iq0_weight = xi_ingress_queue_config->weight ;
+        break ;
+    case 1:
+        iq_base_cfg.iq1_base = xi_ingress_queue_config->base_location ;
+        iq_size_cfg.iq1_size = queue_size_encoding ;
+        iq_weight_cfg.iq1_weight = xi_ingress_queue_config->weight ;
+        break ;
+    case 2:
+        iq_base_cfg.iq2_base = xi_ingress_queue_config->base_location ;
+        iq_size_cfg.iq2_size = queue_size_encoding ;
+        iq_weight_cfg.iq2_weight = xi_ingress_queue_config->weight ;
+        break ;
+    case 3:
+        iq_base_cfg.iq3_base = xi_ingress_queue_config->base_location ;
+        iq_size_cfg.iq3_size = queue_size_encoding ;
+        iq_weight_cfg.iq3_weight = xi_ingress_queue_config->weight ;
+        break ;
+    case 4:
+        iq_base_cfg.iq4_base = xi_ingress_queue_config->base_location ;
+        iq_size_cfg.iq4_size = queue_size_encoding ;
+        iq_weight_cfg.iq4_weight = xi_ingress_queue_config->weight ;
+        break ;
+    case 5:
+        iq_base_cfg.iq5_base = xi_ingress_queue_config->base_location ;
+        iq_size_cfg.iq5_size = queue_size_encoding ;
+        iq_weight_cfg.iq5_weight = xi_ingress_queue_config->weight ;
+        break ;
+    case 6:
+        iq_base_cfg.iq6_base = xi_ingress_queue_config->base_location ;
+        iq_size_cfg.iq6_size = queue_size_encoding ;
+        iq_weight_cfg.iq6_weight = xi_ingress_queue_config->weight ;
+        break ;
+    case 7:
+        iq_base_cfg.iq7_base = xi_ingress_queue_config->base_location ;
+        iq_size_cfg.iq7_size = queue_size_encoding ;
+        iq_weight_cfg.iq7_weight = xi_ingress_queue_config->weight ;
+        break ;
+    }
+    
+    IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_WRITE( iq_base_cfg ) ;
+    IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_WRITE( iq_size_cfg ) ;
+    IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_WRITE( iq_weight_cfg ) ;
+
+    /* handle configuration which is split into 2 registers */
+
+    if ( xi_ingress_queue_index < CS_NUMBER_OF_INGRESS_QUEUES_IN_PRIORITY_AND_CONGESTION_THRESHOLD_REGISTERS )
+    {
+        IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_READ( iql_prior_cfg ) ;
+        IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_READ( iql_cngs_thrs_cfg ) ;
+
+        switch ( xi_ingress_queue_index )
+        {
+        case 0:
+            /* "one hot" format */
+            iql_prior_cfg.iq0_prior = ( 1 << xi_ingress_queue_config->priority ) ;
+            iql_cngs_thrs_cfg.iq0_cngs_thrs = xi_ingress_queue_config->congestion_threshold ;
+            break ;
+        case 1:
+            /* "one hot" format */
+            iql_prior_cfg.iq1_prior = ( 1 << xi_ingress_queue_config->priority ) ;
+            iql_cngs_thrs_cfg.iq1_cngs_thrs = xi_ingress_queue_config->congestion_threshold ;
+            break ;
+        case 2:
+            /* "one hot" format */
+            iql_prior_cfg.iq2_prior = ( 1 << xi_ingress_queue_config->priority ) ;
+            iql_cngs_thrs_cfg.iq2_cngs_thrs = xi_ingress_queue_config->congestion_threshold ;
+            break ;
+        case 3:
+            /* "one hot" format */
+            iql_prior_cfg.iq3_prior = ( 1 << xi_ingress_queue_config->priority ) ;
+            iql_cngs_thrs_cfg.iq3_cngs_thrs = xi_ingress_queue_config->congestion_threshold ;
+            break ;
+        }
+
+        IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_WRITE( iql_prior_cfg ) ;
+        IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_WRITE( iql_cngs_thrs_cfg ) ;
+    }
+    else
+    {
+        IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_READ( iqh_prior_cfg ) ;
+        IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_READ( iqh_cngs_thrs_cfg ) ;
+
+        switch ( xi_ingress_queue_index )
+        {
+        case 4:
+            /* "one hot" format */
+            iqh_prior_cfg.iq4_prior = ( 1 << xi_ingress_queue_config->priority ) ;
+            iqh_cngs_thrs_cfg.iq4_cngs_thrs = xi_ingress_queue_config->congestion_threshold ;
+            break ;
+        case 5:
+            /* "one hot" format */
+            iqh_prior_cfg.iq5_prior = ( 1 << xi_ingress_queue_config->priority ) ;
+            iqh_cngs_thrs_cfg.iq5_cngs_thrs = xi_ingress_queue_config->congestion_threshold ;
+            break ;
+        case 6:
+            /* "one hot" format */
+            iqh_prior_cfg.iq6_prior = ( 1 << xi_ingress_queue_config->priority ) ;
+            iqh_cngs_thrs_cfg.iq6_cngs_thrs = xi_ingress_queue_config->congestion_threshold ;
+            break ;
+        case 7:
+            /* "one hot" format */
+            iqh_prior_cfg.iq7_prior = ( 1 << xi_ingress_queue_config->priority ) ;
+            iqh_cngs_thrs_cfg.iq7_cngs_thrs = xi_ingress_queue_config->congestion_threshold ;
+            break ;
+        }
+
+        IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_WRITE( iqh_prior_cfg ) ;
+        IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_WRITE( iqh_cngs_thrs_cfg ) ;
+    }
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_ih_configure_ingress_queue ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_target_matrix                                           */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Target Matrix                                            */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets the per-source-port configuration in the target       */
+/*   matrix, i.e. all entries which belong to the given source port.          */
+/*   Each entry consists of the following parameters: target memory           */
+/*   (DDR/SRAM), direct mode (true/false).                                    */
+/*   The function will fail when trying to configure an "Always DDR" entry    */
+/*   with Target memory = SRAM, or "Always SRAM" entry with                   */
+/*   Target memory = DDR.                                                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_source_port - Source port                                             */
+/*                                                                            */
+/*   xi_per_sp_config - Per-source-port configuration                         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_target_matrix ( DRV_IH_TARGET_MATRIX_SOURCE_PORT xi_source_port ,
+                                                     const DRV_IH_TARGET_MATRIX_PER_SP_CONFIG * xi_per_sp_config )
+{
+    /* we will use this variable for any source port, not only for eth0 (the registers are similar) */
+    IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG trgt_mtrx_sp_cfg ;
+
+
+    if ( xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ALWAYS_DDR ].target_memory == DRV_IH_TARGET_MEMORY_SRAM )
+    {
+        return ( DRV_IH_ERROR_DESTINATION_PORT_AND_TARGET_MEMORY_MISMATCH ) ;
+    }
+
+    if ( xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ALWAYS_SRAM ].target_memory == DRV_IH_TARGET_MEMORY_DDR )
+    {
+        return ( DRV_IH_ERROR_DESTINATION_PORT_AND_TARGET_MEMORY_MISMATCH ) ;
+    }
+
+
+    /* Here we don't do read-modify-write, we only write.
+       this is because these registers are write-only. */
+
+    trgt_mtrx_sp_cfg.dp_eth0_tm_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH0 ].target_memory ;
+    trgt_mtrx_sp_cfg.dp_eth0_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH0 ].direct_mode ;
+
+    trgt_mtrx_sp_cfg.dp_eth1_tm_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH1 ].target_memory ;
+    trgt_mtrx_sp_cfg.dp_eth1_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH1 ].direct_mode ;
+
+    trgt_mtrx_sp_cfg.dp_eth2_tm_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH2 ].target_memory ;
+    trgt_mtrx_sp_cfg.dp_eth2_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH2 ].direct_mode ;
+
+    trgt_mtrx_sp_cfg.dp_eth3_tm_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH3 ].target_memory ;
+    trgt_mtrx_sp_cfg.dp_eth3_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH3 ].direct_mode ;
+
+    trgt_mtrx_sp_cfg.dp_eth4_tm_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH4 ].target_memory ;
+    trgt_mtrx_sp_cfg.dp_eth4_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH4 ].direct_mode ;
+
+    trgt_mtrx_sp_cfg.dp_gpon_tm_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_GPON ].target_memory ;
+    trgt_mtrx_sp_cfg.dp_gpon_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_GPON ].direct_mode ;
+
+    trgt_mtrx_sp_cfg.dp_pcie0_tm_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE0 ].target_memory ;
+    trgt_mtrx_sp_cfg.dp_pcie0_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE0 ].direct_mode ;
+
+    trgt_mtrx_sp_cfg.dp_pcie1_tm_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE1 ].target_memory ;
+    trgt_mtrx_sp_cfg.dp_pcie1_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE1 ].direct_mode ;
+
+    trgt_mtrx_sp_cfg.dp_cpu_tm_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_CPU ].target_memory ;
+    trgt_mtrx_sp_cfg.dp_cpu_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_CPU ].direct_mode ;
+
+    trgt_mtrx_sp_cfg.dp_mc_tm_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_MULTICAST ].target_memory ;
+    trgt_mtrx_sp_cfg.dp_mc_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_MULTICAST ].direct_mode ;
+
+    /* no configuration of target memory for "ALWAYS_DDR" port */
+    trgt_mtrx_sp_cfg.dp_ddr_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ALWAYS_DDR ].direct_mode ;
+
+    /* no configuration of target memory for "ALWAYS_SRAM" port */
+    trgt_mtrx_sp_cfg.dp_sram_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ALWAYS_SRAM ].direct_mode ;
+
+    trgt_mtrx_sp_cfg.dp_spare_tm_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_SPARE ].target_memory ;
+    trgt_mtrx_sp_cfg.dp_spare_ls_cfg = xi_per_sp_config->entry [ DRV_IH_TARGET_MATRIX_DESTINATION_PORT_SPARE ].direct_mode ;
+
+    trgt_mtrx_sp_cfg.rsv1 = IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_RSV1_RSV_VALUE ;
+    trgt_mtrx_sp_cfg.rsv2 = IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_RSV2_RSV_VALUE ;
+    
+    /* write entry according to souce port */
+    switch ( xi_source_port )
+    {
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH0:
+        IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_WRITE( trgt_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH1:
+        IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_WRITE( trgt_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH2:
+        IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_WRITE( trgt_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH3:
+        IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_WRITE( trgt_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH4:
+        IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_WRITE( trgt_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_GPON:
+        IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_WRITE( trgt_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_PCIE0:
+        IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_WRITE( trgt_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_PCIE1:
+        IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_WRITE( trgt_mtrx_sp_cfg ) ;
+        break ;
+    default:
+        return ( DRV_IH_ERROR_INVALID_PORT ) ;
+        break ;
+    }
+
+    /* create shadow */
+    memcpy((uint8_t *)&(trgt_mtrx_sp_shadow[xi_source_port]), (uint8_t *)xi_per_sp_config, sizeof(DRV_IH_TARGET_MATRIX_PER_SP_CONFIG));
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_ih_set_target_matrix ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_forward                                                 */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Target Forward                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets the "forward-enable" bit for the given source         */
+/*   port and destination port.                                               */
+/*   The "forward-enable" is only indication to FW (IH doesn't drop if        */
+/*   forwarding is disabled).                                                 */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_source_port - Source port                                             */
+/*                                                                            */
+/*   xi_destination_port - Destination port                                   */
+/*                                                                            */
+/*   xi_forward - Forward                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_forward ( DRV_IH_TARGET_MATRIX_SOURCE_PORT xi_source_port ,
+                                               DRV_IH_TARGET_MATRIX_DESTINATION_PORT xi_destination_port ,
+                                               int32_t xi_forward )
+{
+    /* we will use this variable for any source port, not only for eth0 (the registers are similar) */
+    IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG fw_en_mtrx_sp_cfg ;
+
+
+    /* read entry according to souce port */
+    switch ( xi_source_port )
+    {
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH0:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_READ( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH1:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_READ( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH2:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_READ( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH3:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_READ( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH4:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_READ( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_GPON:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_READ( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_PCIE0:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_READ( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_PCIE1:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_READ( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    default:
+        return ( DRV_IH_ERROR_INVALID_PORT ) ;
+        break ;
+    }
+
+    /* modify entry according to destination port */
+    switch ( xi_destination_port )
+    {
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH0:
+        fw_en_mtrx_sp_cfg.dp_eth0_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH1:
+        fw_en_mtrx_sp_cfg.dp_eth1_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH2:
+        fw_en_mtrx_sp_cfg.dp_eth2_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH3:
+        fw_en_mtrx_sp_cfg.dp_eth3_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH4:
+        fw_en_mtrx_sp_cfg.dp_eth4_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_GPON:
+        fw_en_mtrx_sp_cfg.dp_gpon_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE0:
+        fw_en_mtrx_sp_cfg.dp_pcie0_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE1:
+        fw_en_mtrx_sp_cfg.dp_pcie1_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_CPU:
+        fw_en_mtrx_sp_cfg.dp_cpu_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_MULTICAST:
+        fw_en_mtrx_sp_cfg.dp_mc_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ALWAYS_DDR:
+        fw_en_mtrx_sp_cfg.dp_ddr_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ALWAYS_SRAM:
+        fw_en_mtrx_sp_cfg.dp_sram_fw_en_cfg = xi_forward ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_DESTINATION_PORT_SPARE:
+        fw_en_mtrx_sp_cfg.dp_spare_fw_en_cfg = xi_forward ;
+        break ;
+    default:
+        return ( DRV_IH_ERROR_INVALID_PORT ) ;
+        break ;
+    }
+    
+    /* write entry according to souce port */
+    switch ( xi_source_port )
+    {
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH0:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_WRITE( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH1:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_WRITE( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH2:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_WRITE( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH3:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_WRITE( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH4:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_WRITE( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_GPON:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_WRITE( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_PCIE0:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_WRITE( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    case DRV_IH_TARGET_MATRIX_SOURCE_PORT_PCIE1:
+        IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_WRITE( fw_en_mtrx_sp_cfg ) ;
+        break ;
+    default:
+        return ( DRV_IH_ERROR_INVALID_PORT ) ;
+        break ;
+    }
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_ih_set_forward ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_wan_ports                                         */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure WAN ports                                          */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures, for each logical port, whether it belongs to   */
+/*   WAN traffic. IH uses this configuration for WAN indication in the parser */
+/*   result (and Classifier Key Word).                                        */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_wan_ports_config - WAN ports configuration                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_wan_ports ( const DRV_IH_WAN_PORTS_CONFIG * xi_wan_ports_config )
+{
+    IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG wan_per_port_cfg ;
+
+    IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_READ( wan_per_port_cfg ) ;
+    wan_per_port_cfg.eth0_trf_map = xi_wan_ports_config->eth0 ;
+    wan_per_port_cfg.eth1_trf_map = xi_wan_ports_config->eth1 ;
+    wan_per_port_cfg.eth2_trf_map = xi_wan_ports_config->eth2 ;
+    wan_per_port_cfg.eth3_trf_map = xi_wan_ports_config->eth3 ;
+    wan_per_port_cfg.eth4_trf_map = xi_wan_ports_config->eth4 ;
+    wan_per_port_cfg.gpon_trf_map = xi_wan_ports_config->gpon ;
+    wan_per_port_cfg.rnra_trf_map = xi_wan_ports_config->runner_a ;
+    wan_per_port_cfg.rnrb_trf_map = xi_wan_ports_config->runner_b ;
+    wan_per_port_cfg.pcie0_trf_map = xi_wan_ports_config->pcie0 ;
+    wan_per_port_cfg.pcie1_trf_map = xi_wan_ports_config->pcie1 ;
+    IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_WRITE( wan_per_port_cfg ) ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_ih_configure_wan_ports ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_parser                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure Parser                                             */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures general parameters in the parser accelerator in */
+/*   IH.                                                                      */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_parser_config - Parser Configuration                                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_parser ( const DRV_IH_PARSER_CONFIG * xi_parser_config )
+{
+    IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG parser_cfg ;
+    IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG ipv6_hdr_ext_fltr_mask_cfg ;
+    IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE snap_org_code ;
+    IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG gre_protocol_cfg ;
+    IH_REGS_PARSER_CORE_CONFIGURATION_ENG  eng_cfg ;
+
+    IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_READ( parser_cfg ) ;
+    parser_cfg.tcp_flags_filt = xi_parser_config->tcp_flags ;
+    parser_cfg.exception_en = xi_parser_config->exception_status_bits ;
+    parser_cfg.ppp_code_1_ipv6 = xi_parser_config->ppp_code_1_ipv6 ;
+    IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_WRITE( parser_cfg ) ;
+
+    IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_READ( ipv6_hdr_ext_fltr_mask_cfg ) ;
+    ipv6_hdr_ext_fltr_mask_cfg.hop_by_hop_match = MS_GET_BIT_I( xi_parser_config->ipv6_extension_header_bitmask , 0 ) ;
+    ipv6_hdr_ext_fltr_mask_cfg.routing_eh = MS_GET_BIT_I( xi_parser_config->ipv6_extension_header_bitmask , 1 ) ;
+    ipv6_hdr_ext_fltr_mask_cfg.dest_opt_eh = MS_GET_BIT_I( xi_parser_config->ipv6_extension_header_bitmask , 2 ) ;
+    IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_WRITE( ipv6_hdr_ext_fltr_mask_cfg ) ;
+
+    IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_READ( snap_org_code ) ;
+    snap_org_code.code = xi_parser_config->snap_user_defined_organization_code ;
+    snap_org_code.en_rfc1042 = xi_parser_config->snap_rfc1042_encapsulation_enable ;
+    snap_org_code.en_8021q = xi_parser_config->snap_802_1q_encapsulation_enable ;
+    IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_WRITE( snap_org_code ) ;
+
+    IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_READ( gre_protocol_cfg ) ;
+    gre_protocol_cfg.gre_protocol = xi_parser_config->gre_protocol ;
+    IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_WRITE( gre_protocol_cfg ) ;
+    IH_REGS_PARSER_CORE_CONFIGURATION_ENG_READ( eng_cfg ) ;
+    eng_cfg.cfg = xi_parser_config->eng_cfg ;
+    IH_REGS_PARSER_CORE_CONFIGURATION_ENG_WRITE( eng_cfg ) ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL( fi_bl_drv_ih_configure_parser ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Internal functions implementation                                          */
+/*                                                                            */
+/******************************************************************************/
+
+
+/* this function checks validity of item index, comparing to number of items.
+   this function is intended for items whose legal indices are 0 to xi_number_of_items - 1.
+   in case of invalid index, this function returns false and prints to logger a compatible
+   message. otherwise, true is returned. */
+int32_t f_check_item_index( uint32_t xi_item_index ,
+                                    uint32_t xi_number_of_items )
+{
+    if ( xi_item_index >= xi_number_of_items )
+    {
+
+        return ( 0 ) ;
+    }
+
+    return ( 1 ) ;
+}
+
+
+/* this function configures all paramters of a lookup table, including
+   "five tupple enable" paramter which is not exposed to the user.
+   this function perfroms validity checks of parameters. */
+DRV_IH_ERROR f_configure_lut_all_parameters ( uint8_t xi_table_index ,
+                                                           const DRV_IH_LOOKUP_TABLE_60_BIT_KEY_CONFIG * xi_lookup_table_60_bit_key_config ,
+                                                           int32_t xi_five_tupple_enable )
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG lkup_tbl_lut_cfg ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG lkup_tbl_cam_cfg ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG lkup_tbl_lut_cnxt_cfg ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG lkup_tbl_cam_cnxt_cfg ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG lkup_tbl_key_cfg ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL lkup_tbl_key_p0_maskl ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH lkup_tbl_key_p0_maskh ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL lkup_tbl_key_p1_maskl ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH lkup_tbl_key_p1_maskh ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK lkup_tbl_gl_mask ;
+    int32_t result ;
+
+
+    result = f_check_item_index( xi_table_index ,
+                                 DRV_IH_NUMBER_OF_LOOKUP_TABLES ) ;
+    if ( result == 0 )
+    {
+        return ( DRV_IH_ERROR_INVALID_INDEX ) ;
+    }
+
+    if ( ( xi_lookup_table_60_bit_key_config->part_0_start_offset_in_4_byte > DRV_IH_MAXIMAL_START_OFFSET_SEATCH_KEY_PART ) || 
+         ( xi_lookup_table_60_bit_key_config->part_1_start_offset_in_4_byte > DRV_IH_MAXIMAL_START_OFFSET_SEATCH_KEY_PART ) )
+    {
+        return ( DRV_IH_ERROR_INVALID_START_OFFSET_SEATCH_KEY_PART ) ;
+    }
+
+    if ( ( xi_lookup_table_60_bit_key_config->part_0_shift_offset_in_4_bit > DRV_IH_MAXIMAL_SHIFT_OFFSET_SEATCH_KEY_PART ) || 
+         ( xi_lookup_table_60_bit_key_config->part_1_shift_offset_in_4_bit > DRV_IH_MAXIMAL_SHIFT_OFFSET_SEATCH_KEY_PART ) )
+    {
+        return ( DRV_IH_ERROR_INVALID_SHIFT_OFFSET_SEATCH_KEY_PART ) ;
+    }
+
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TLUT_CFG_READ_I( lkup_tbl_lut_cfg , xi_table_index ) ;
+    lkup_tbl_lut_cfg.base_address = xi_lookup_table_60_bit_key_config->table_base_address_in_8_byte ;
+
+    lkup_tbl_lut_cfg.table_size = xi_lookup_table_60_bit_key_config->table_size ;
+
+    lkup_tbl_lut_cfg.max_hop = xi_lookup_table_60_bit_key_config->maximal_search_depth ;
+
+    lkup_tbl_lut_cfg.hash_type = xi_lookup_table_60_bit_key_config->hash_type ;
+
+    lkup_tbl_lut_cfg.sa_search_en = xi_lookup_table_60_bit_key_config->sa_search_enable ;
+
+    lkup_tbl_lut_cfg.aging_en = xi_lookup_table_60_bit_key_config->aging_enable ;
+
+    lkup_tbl_lut_cfg.five_tuple_en = xi_five_tupple_enable ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TLUT_CFG_WRITE_I( lkup_tbl_lut_cfg , xi_table_index ) ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TCAM_CFG_READ_I( lkup_tbl_cam_cfg , xi_table_index ) ;
+    lkup_tbl_cam_cfg.cam_en = xi_lookup_table_60_bit_key_config->cam_enable ;
+    lkup_tbl_cam_cfg.base_address = xi_lookup_table_60_bit_key_config->cam_base_address_in_8_byte ;
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TCAM_CFG_WRITE_I( lkup_tbl_cam_cfg , xi_table_index ) ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TLUT_CNXT_CFG_READ_I( lkup_tbl_lut_cnxt_cfg , xi_table_index ) ;
+    lkup_tbl_lut_cnxt_cfg.base_address = xi_lookup_table_60_bit_key_config->context_table_base_address_in_8_byte ;
+    lkup_tbl_lut_cnxt_cfg.cnxt_entry_size = xi_lookup_table_60_bit_key_config->context_table_entry_size ;
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TLUT_CNXT_CFG_WRITE_I( lkup_tbl_lut_cnxt_cfg , xi_table_index ) ;
+
+    MS_DRV_IH_LOOKUP_LOOKUP_CONFIGURATION_LKUP_TCAM_CNXT_CFG_READ_I( lkup_tbl_cam_cnxt_cfg , xi_table_index ) ;
+    lkup_tbl_cam_cnxt_cfg.base_address = xi_lookup_table_60_bit_key_config->cam_context_base_address_in_8_byte ;
+    MS_DRV_IH_LOOKUP_LOOKUP_CONFIGURATION_LKUP_TCAM_CNXT_CFG_WRITE_I( lkup_tbl_cam_cnxt_cfg , xi_table_index ) ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_CFG_READ_I( lkup_tbl_key_cfg , xi_table_index ) ;
+    lkup_tbl_key_cfg.start_offset_p0 = xi_lookup_table_60_bit_key_config->part_0_start_offset_in_4_byte ;
+    lkup_tbl_key_cfg.shift_offset_p0 = xi_lookup_table_60_bit_key_config->part_0_shift_offset_in_4_bit ;
+    lkup_tbl_key_cfg.start_offset_p1 = xi_lookup_table_60_bit_key_config->part_1_start_offset_in_4_byte ;
+    lkup_tbl_key_cfg.shift_offset_p1 = xi_lookup_table_60_bit_key_config->part_1_shift_offset_in_4_bit ;
+    lkup_tbl_key_cfg.key_ext = xi_lookup_table_60_bit_key_config->key_extension ;
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_CFG_WRITE_I( lkup_tbl_key_cfg , xi_table_index ) ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P0_MASKL_READ_I( lkup_tbl_key_p0_maskl , xi_table_index ) ;
+    lkup_tbl_key_p0_maskl.maskl = xi_lookup_table_60_bit_key_config->part_0_mask_low ;
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P0_MASKL_WRITE_I( lkup_tbl_key_p0_maskl , xi_table_index ) ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P0_MASKH_READ_I( lkup_tbl_key_p0_maskh , xi_table_index ) ;
+    lkup_tbl_key_p0_maskh.maskh = xi_lookup_table_60_bit_key_config->part_0_mask_high ;
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P0_MASKH_WRITE_I( lkup_tbl_key_p0_maskh , xi_table_index ) ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P1_MASKL_READ_I( lkup_tbl_key_p1_maskl , xi_table_index ) ;
+    lkup_tbl_key_p1_maskl.maskl = xi_lookup_table_60_bit_key_config->part_1_mask_low ;
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P1_MASKL_WRITE_I( lkup_tbl_key_p1_maskl , xi_table_index ) ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P1_MASKH_READ_I( lkup_tbl_key_p1_maskh , xi_table_index ) ;
+    lkup_tbl_key_p1_maskh.maskh = xi_lookup_table_60_bit_key_config->part_1_mask_high ;
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P1_MASKH_WRITE_I( lkup_tbl_key_p1_maskh , xi_table_index ) ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_READ_I( lkup_tbl_gl_mask , xi_table_index ) ;
+    lkup_tbl_gl_mask.mask_nibble_code = xi_lookup_table_60_bit_key_config->global_mask_in_4_bit ;
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_WRITE_I( lkup_tbl_gl_mask , xi_table_index ) ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+
+
+/* this function gets all paramters configuration of a lookup table, including
+   "five tupple enable" paramter which is not exposed to the user. */
+/* this function is exported for IHD shell commands */
+DRV_IH_ERROR fi_get_lut_all_parameters ( uint8_t xi_table_index ,
+                                                      DRV_IH_LOOKUP_TABLE_60_BIT_KEY_CONFIG * const xo_lookup_table_60_bit_key_config ,
+                                                      int32_t * const xo_five_tupple_enable )
+{
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG lkup_tbl_lut_cfg ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG lkup_tbl_cam_cfg ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG lkup_tbl_lut_cnxt_cfg ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG lkup_tbl_cam_cnxt_cfg ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG lkup_tbl_key_cfg ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL lkup_tbl_key_p0_maskl ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH lkup_tbl_key_p0_maskh ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL lkup_tbl_key_p1_maskl ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH lkup_tbl_key_p1_maskh ;
+    IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK lkup_tbl_gl_mask ;
+    int32_t result ;
+
+    result = f_check_item_index( xi_table_index ,
+                                 DRV_IH_NUMBER_OF_LOOKUP_TABLES ) ;
+    if ( result == 0 )
+    {
+        return ( DRV_IH_ERROR_INVALID_INDEX ) ;
+    }
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TLUT_CFG_READ_I( lkup_tbl_lut_cfg , xi_table_index ) ;
+    xo_lookup_table_60_bit_key_config->table_base_address_in_8_byte = lkup_tbl_lut_cfg.base_address ;
+    xo_lookup_table_60_bit_key_config->table_size = lkup_tbl_lut_cfg.table_size ;
+    xo_lookup_table_60_bit_key_config->maximal_search_depth = lkup_tbl_lut_cfg.max_hop ;
+    xo_lookup_table_60_bit_key_config->hash_type = lkup_tbl_lut_cfg.hash_type ;
+    xo_lookup_table_60_bit_key_config->sa_search_enable = lkup_tbl_lut_cfg.sa_search_en ;
+    xo_lookup_table_60_bit_key_config->aging_enable = lkup_tbl_lut_cfg.aging_en ;
+    * xo_five_tupple_enable = lkup_tbl_lut_cfg.five_tuple_en ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TCAM_CFG_READ_I( lkup_tbl_cam_cfg , xi_table_index ) ;
+    xo_lookup_table_60_bit_key_config->cam_enable = lkup_tbl_cam_cfg.cam_en ;
+    xo_lookup_table_60_bit_key_config->cam_base_address_in_8_byte = lkup_tbl_cam_cfg.base_address ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TLUT_CNXT_CFG_READ_I( lkup_tbl_lut_cnxt_cfg , xi_table_index ) ;
+    xo_lookup_table_60_bit_key_config->context_table_base_address_in_8_byte = lkup_tbl_lut_cnxt_cfg.base_address ;
+    xo_lookup_table_60_bit_key_config->context_table_entry_size = lkup_tbl_lut_cnxt_cfg.cnxt_entry_size ;
+
+    MS_DRV_IH_LOOKUP_LOOKUP_CONFIGURATION_LKUP_TCAM_CNXT_CFG_READ_I( lkup_tbl_cam_cnxt_cfg , xi_table_index ) ;
+    xo_lookup_table_60_bit_key_config->cam_context_base_address_in_8_byte = lkup_tbl_cam_cnxt_cfg.base_address ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_CFG_READ_I( lkup_tbl_key_cfg , xi_table_index ) ;
+    xo_lookup_table_60_bit_key_config->part_0_start_offset_in_4_byte = lkup_tbl_key_cfg.start_offset_p0 ;
+    xo_lookup_table_60_bit_key_config->part_0_shift_offset_in_4_bit = lkup_tbl_key_cfg.shift_offset_p0 ;
+    xo_lookup_table_60_bit_key_config->part_1_start_offset_in_4_byte = lkup_tbl_key_cfg.start_offset_p1 ;
+    xo_lookup_table_60_bit_key_config->part_1_shift_offset_in_4_bit = lkup_tbl_key_cfg.shift_offset_p1 ;
+    xo_lookup_table_60_bit_key_config->key_extension = lkup_tbl_key_cfg.key_ext ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P0_MASKL_READ_I( lkup_tbl_key_p0_maskl , xi_table_index ) ;
+    xo_lookup_table_60_bit_key_config->part_0_mask_low = lkup_tbl_key_p0_maskl.maskl ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P0_MASKH_READ_I( lkup_tbl_key_p0_maskh , xi_table_index ) ;
+    xo_lookup_table_60_bit_key_config->part_0_mask_high = lkup_tbl_key_p0_maskh.maskh ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P1_MASKL_READ_I( lkup_tbl_key_p1_maskl , xi_table_index ) ;
+    xo_lookup_table_60_bit_key_config->part_1_mask_low = lkup_tbl_key_p1_maskl.maskl ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TKEY_P1_MASKH_READ_I( lkup_tbl_key_p1_maskh , xi_table_index ) ;
+    xo_lookup_table_60_bit_key_config->part_1_mask_high = lkup_tbl_key_p1_maskh.maskh ;
+
+    MS_DRV_IH_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_READ_I( lkup_tbl_gl_mask , xi_table_index ) ;
+    xo_lookup_table_60_bit_key_config->global_mask_in_4_bit = lkup_tbl_gl_mask.mask_nibble_code ;
+
+    return ( DRV_IH_NO_ERROR ) ;
+}
+EXPORT_SYMBOL ( fi_get_lut_all_parameters ) ;
+
+
+/* checks in which common memory section a lookup table is located.
+   this function assumes that xi_table_index is valid! */
+DRV_IH_COMMON_MEMORY_SECTION_DTS f_get_lookup_table_location( uint8_t xi_table_index )
+{
+    DRV_IH_LOOKUP_TABLE_60_BIT_KEY_CONFIG lookup_table_config ;
+    int32_t five_tupple_enable ;
+    uint8_t common_memory_section_selection_bit ;
+
+    fi_get_lut_all_parameters ( xi_table_index ,
+                                & lookup_table_config ,
+                                & five_tupple_enable ) ;
+
+    common_memory_section_selection_bit = MS_GET_BIT_I( lookup_table_config.table_base_address_in_8_byte ,
+                                                        CS_COMMON_MEMORY_SECTION_SELECTION_BIT ) ;
+
+    if ( common_memory_section_selection_bit == 0 )
+    {
+
+        return ( CS_COMMON_MEMORY_SECTION_A ) ;
+    }
+    else
+    {
+
+        return ( CS_COMMON_MEMORY_SECTION_B ) ;
+    }
+}
+
+
+/* verifies that the lookup table of a given class search is located at the desired location */
+int32_t f_verify_class_search_validity( DRV_IH_CLASS_SEARCH xi_class_search ,
+                                                DRV_IH_COMMON_MEMORY_SECTION_DTS xi_desired_lookup_table_location )
+{
+    DRV_IH_COMMON_MEMORY_SECTION_DTS lookup_table_location ;
+
+    if ( xi_class_search != DRV_IH_CLASS_SEARCH_DISABLED )
+    {
+        lookup_table_location = f_get_lookup_table_location( xi_class_search ) ;
+
+        if ( lookup_table_location != xi_desired_lookup_table_location )
+        {
+
+            return ( 0 ) ;
+        }
+    }
+
+
+    return ( 1 ) ;
+}
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_drv_ih.h b/arch/arm/mach-bcmbca/rdp/rdp_drv_ih.h
new file mode 100755
index 0000000000..851b214c29
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_drv_ih.h
@@ -0,0 +1,2756 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/             
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This header file defines all datatypes and functions exported for the      */
+/* Lilac IH driver                                                            */
+/*                                                                            */
+/******************************************************************************/
+
+
+#ifndef DRV_IH_H_INCLUDED
+#define DRV_IH_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+
+#include "rdp_ih.h"
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Error codes returned by IH driver APIs                                     */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_NO_ERROR ,
+    DRV_IH_ERROR_INVALID_INDEX ,
+    DRV_IH_ERROR_INVALID_NUMBER_OF_RUNNER_BUFFERS ,
+    DRV_IH_ERROR_INVALID_INGRESS_QUEUE ,
+    DRV_IH_ERROR_INVALID_INGRESS_QUEUE_BASE_LOCATION ,
+    DRV_IH_ERROR_INVALID_INGRESS_QUEUE_SIZE ,
+    DRV_IH_ERROR_INVALID_INGRESS_QUEUE_PRIORITY ,
+    DRV_IH_ERROR_INVALID_INGRESS_QUEUE_WEIGHT ,
+    DRV_IH_ERROR_DESTINATION_PORT_AND_TARGET_MEMORY_MISMATCH ,
+    DRV_IH_ERROR_INVALID_PORT ,
+    DRV_IH_ERROR_INVALID_L3_OFFSET ,
+    DRV_IH_ERROR_INVALID_VID ,
+    DRV_IH_ERROR_INVALID_DSCP ,
+    DRV_IH_ERROR_INVALID_TCI ,
+    DRV_IH_ERROR_INVALID_TABLE_SIZE ,
+    DRV_IH_ERROR_INVALID_MAXIMAL_SEARCH_DEPTH ,
+    DRV_IH_ERROR_INVALID_START_OFFSET_SEATCH_KEY_PART ,
+    DRV_IH_ERROR_INVALID_SHIFT_OFFSET_SEATCH_KEY_PART ,
+    DRV_IH_ERROR_TABLE_IS_NOT_60_BIT_KEY ,
+    DRV_IH_ERROR_TABLE_IS_NOT_120_BIT_KEY ,
+    DRV_IH_ERROR_CLASS_SEARCH_AND_LUT_LOCATION_MISMATCH ,
+    DRV_IH_ERROR_VALUE_IS_WRITE_ONLY
+}
+DRV_IH_ERROR ;
+
+/* Maximal value for maximal number of runner buffers allocated to runner */
+#define DRV_IH_MAXIMAL_VALUE_FOR_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS ( 64 )
+/* Maximal ingress queue congestion threshold.
+   Needed to allow threshold=65 for following scenario: maximal number of
+   runner buffers is 64, and we want to never reach the threshold (i.e.
+   IH will never stop serving the queue).  */
+#define DRV_IH_MAXIMAL_INGRESS_QUEUE_CONGESTION_THRESHOLD         ( DRV_IH_MAXIMAL_VALUE_FOR_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS + 1 )
+/* Number of lookup tables */                                
+#define DRV_IH_NUMBER_OF_LOOKUP_TABLES                            ( 10 )
+/* Number of classes */                                             
+#define DRV_IH_NUMBER_OF_CLASSES                                  ( 16 )
+/* Number of classifiers */                                         
+#define DRV_IH_NUMBER_OF_CLASSIFIERS                              ( 16 )
+/* maximal start offset for part (0 or 1) of a search key (in 4 byte resolution) */
+#define DRV_IH_MAXIMAL_START_OFFSET_SEATCH_KEY_PART               ( 14 )
+/* maximal shift offset for part (0 or 1) of a search key (in 4 bit resolution) */
+#define DRV_IH_MAXIMAL_SHIFT_OFFSET_SEATCH_KEY_PART               ( 15 )
+/* Number of DSCP-to-TCI tables. these tables are used for untagged IP packets */
+#define DRV_IH_NUMBER_OF_DSCP_TO_TCI_TABLES                       ( 2 )
+/* Number of ingress queues */                                      
+#define DRV_IH_NUMBER_OF_INGRESS_QUEUES                           ( 8 )
+/* Ingress queues array size */                                     
+#define DRV_IH_INGRESS_QUEUES_ARRAY_SIZE                          ( 16 )
+/* Minimal ingress queue size. */                                     
+#define DRV_IH_MINIMAL_INGRESS_QUEUE_SIZE                         ( 1 )
+/* Maximal ingress queue priority. lower priority value means lower priority. */
+#define DRV_IH_MAXIMAL_INGRESS_QUEUE_PRIORITY                      ( 7 )
+/* Maximal ingress queue weight. lower weight value means lower weight.
+   Weight is relevant only for two or more queues with the same priority */
+#define DRV_IH_MAXIMAL_INGRESS_QUEUE_WEIGHT                        ( 15 )
+/* number of bytes in MAC address */                                 
+#define DRV_IH_NUMBER_OF_BYTES_IN_MAC_ADDRESS                      ( 6 )
+/* number of DA filters with mask */                                 
+#define DRV_IH_NUMBER_OF_DA_FILTERS_WITH_MASK                      ( 2 )
+/* number of DA filters (with and without mask) */                   
+#define DRV_IH_NUMBER_OF_DA_FILTERS                                ( 8 )
+/* Number of user-defined ethertypes */                              
+#define DRV_IH_NUMBER_OF_USER_DEFINED_ETHERTYPES                   ( 4 )
+/* Maximal L3 offset */
+#define DRV_IH_MAXIMAL_L3_OFFSET                                   ( 15 )
+/* Number of user-defined IP L4 protocols */
+#define DRV_IH_NUMBER_OF_USER_DEFINED_IP_L4_PROTOCOLS              ( 4 )
+/* Number of PPP Protocol Codes */
+#define DRV_IH_NUMBER_OF_PPP_PROTOCOL_CODES                        ( 2 )
+/* Number of VID filters */                                   
+#define DRV_IH_NUMBER_OF_VID_FILTERS                               ( 12 )
+/* Maximal VID value */                                       
+#define DRV_IH_MAXIMAL_VID_VALUE                                   ( 4095 )
+/* Number of IP filters */                                    
+#define DRV_IH_NUMBER_OF_IP_FILTERS                                ( 4 )
+/* Maximal DSCP value */                                      
+#define DRV_IH_MAXIMAL_DSCP_VALUE                                  ( 63 )
+/* Maximal TCI value */                                       
+#define DRV_IH_MAXIMAL_TCI_VALUE                                   ( 7 )
+
+
+/******************************************************************************/
+/* General configuration                                                      */
+/******************************************************************************/
+typedef struct
+{
+    /* In runner flow, IH response is sent to runner after completing writing
+       the runner buffer. */
+    uint16_t runner_a_ih_response_address ;
+
+    /* In runner flow, IH response is sent to runner after completing writing
+       the runner buffer. */
+    uint16_t runner_b_ih_response_address ;
+
+    /* In case of change of runner congestion state, IH sends Runner
+       Congestion report to predefined buffer with number of allocated RBs
+       for relevant runner. */
+    uint16_t runner_a_ih_congestion_report_address ;
+
+    /* In case of change of runner congestion state, IH sends Runner
+       Congestion report to predefined buffer with number of allocated RBs
+       for relevant runner. */
+    uint16_t runner_b_ih_congestion_report_address ;
+
+    /* Runner A IH congestion report enable */
+    int32_t runner_a_ih_congestion_report_enable ;
+
+    /* Runner B IH congestion report enable */
+    int32_t runner_b_ih_congestion_report_enable ;
+
+    /* Enable/disable LUT searches when the default direct mode of a class is
+       enabled. */
+    int32_t lut_searches_enable_in_direct_mode ;
+
+    /* SN stamping enable in direct mode. */
+    int32_t sn_stamping_enable_in_direct_mode ;
+
+    /* If a packet's header length is below this threshold, IH will disable
+       Parsing & Look-up processing, however the RIB will be assigned + and
+       stamped with SN. */
+    uint8_t header_length_minimum ;
+
+    /* When this field is set to true, IH will ignore the runner congestion
+       state, and discard packets only when there are no available RIBs. */
+    int32_t congestion_discard_disable ;
+
+    /* If true, IH will go to CAM (if CAM is enabled) upon encountering an
+       invalid LUT entry. If false, IH will stop the search. */
+    int32_t cam_search_enable_upon_invalid_lut_entry ;
+}
+DRV_IH_GENERAL_CONFIG ;
+
+
+/******************************************************************************/
+/* Packet header offsets                                                      */
+/******************************************************************************/
+typedef struct
+{
+    /* Eth0 packet header offset */
+    uint8_t eth0_packet_header_offset ;
+
+    /* Eth1 packet header offset */
+    uint8_t eth1_packet_header_offset ;
+
+    /* Eth2 packet header offset */
+    uint8_t eth2_packet_header_offset ;
+
+    /* Eth3 packet header offset */
+    uint8_t eth3_packet_header_offset ;
+
+    /* Eth4 packet header offset */
+    uint8_t eth4_packet_header_offset ;
+
+    /* GPON packet header offset */
+    uint8_t gpon_packet_header_offset ;
+
+    /* Runner A packet header offset */
+    uint8_t runner_a_packet_header_offset ;
+
+    /* Runner B packet header offset */
+    uint8_t runner_b_packet_header_offset ;
+}
+DRV_IH_PACKET_HEADER_OFFSETS ;
+
+
+/******************************************************************************/
+/* Runner maximal number of buffers                                           */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS_16 ,
+    DRV_IH_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS_24 ,
+    DRV_IH_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS_32 ,
+    DRV_IH_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS_48 ,
+    DRV_IH_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS_64
+}
+DRV_IH_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS ;
+
+
+/******************************************************************************/
+/* Runner Buffers Configuration                                               */
+/******************************************************************************/
+typedef struct
+{
+    /* Runner A IH managed RB base address */
+    uint16_t runner_a_ih_managed_rb_base_address ;
+
+    /* Runner B IH managed RB base address */
+    uint16_t runner_b_ih_managed_rb_base_address ;
+
+    /* Runner A runner managed RB base address */
+    uint16_t runner_a_runner_managed_rb_base_address ;
+
+    /* Runner B runner managed RB base address */
+    uint16_t runner_b_runner_managed_rb_base_address ;
+
+    /* Runner A maximal number of buffers */
+    DRV_IH_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS runner_a_maximal_number_of_buffers ;
+
+    /* Runner B maximal number of buffers */
+    DRV_IH_RUNNER_MAXIMAL_NUMBER_OF_BUFFERS runner_b_maximal_number_of_buffers ;
+}
+DRV_IH_RUNNER_BUFFERS_CONFIG ;
+
+
+/******************************************************************************/
+/* Runners Load Thresholds                                                    */
+/******************************************************************************/
+typedef struct
+{
+    /* Threshold for dropping low priority packets */
+    uint8_t runner_a_high_congestion_threshold ;
+
+    /* Threshold for dropping low priority packets */
+    uint8_t runner_b_high_congestion_threshold ;
+
+    /* Threshold for dropping low & high priority packets */
+    uint8_t runner_a_exclusive_congestion_threshold ;
+
+    /* Threshold for dropping low & high priority packets */
+    uint8_t runner_b_exclusive_congestion_threshold ;
+
+    /* Threshold for turning-on load balancing */
+    uint8_t runner_a_load_balancing_threshold ;
+
+    /* Threshold for turning-on load balancing */
+    uint8_t runner_b_load_balancing_threshold ;
+
+    /* Threshold for turning-off load balancing */
+    uint8_t runner_a_load_balancing_hysteresis ;
+
+    /* Threshold for turning-off load balancing */
+    uint8_t runner_b_load_balancing_hysteresis ;
+}
+DRV_IH_RUNNERS_LOAD_THRESHOLDS ;
+
+
+/******************************************************************************/
+/* Route Addresses                                                            */
+/******************************************************************************/
+typedef struct
+{
+    /* Eth0 route address */
+    uint8_t eth0_route_address ;
+
+    /* Eth1 route address */
+    uint8_t eth1_route_address ;
+
+    /* Eth2 route address */
+    uint8_t eth2_route_address ;
+
+    /* Eth3 route address */
+    uint8_t eth3_route_address ;
+
+    /* Eth4 route address */
+    uint8_t eth4_route_address ;
+
+    /* GPON route address */
+    uint8_t gpon_route_address ;
+
+    /* Runner A route address */
+    uint8_t runner_a_route_address ;
+
+    /* Runner B route address */
+    uint8_t runner_b_route_address ;
+}
+DRV_IH_ROUTE_ADDRESSES ;
+
+
+/******************************************************************************/
+/* Parsing layer depth                                                        */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_PARSING_LAYER_DEPTH_VLAN ,
+    DRV_IH_PARSING_LAYER_DEPTH_LAYER2 ,
+    DRV_IH_PARSING_LAYER_DEPTH_LAYER3 ,
+    DRV_IH_PARSING_LAYER_DEPTH_LAYER4
+}
+DRV_IH_PARSING_LAYER_DEPTH ;
+
+
+/******************************************************************************/
+/* Proprietary tag size                                                       */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_PROPRIETARY_TAG_SIZE_0 = 0 ,
+	DRV_IH_PROPRIETARY_TAG_SIZE_4 = 4 ,
+	DRV_IH_PROPRIETARY_TAG_SIZE_6 = 6 ,
+	DRV_IH_PROPRIETARY_TAG_SIZE_8 = 8
+}
+DRV_IH_PROPRIETARY_TAG_SIZE ;
+
+
+/******************************************************************************/
+/* Logical Port Configuration                                                 */
+/******************************************************************************/
+typedef struct
+{
+    /* Parsing layer depth */
+    DRV_IH_PARSING_LAYER_DEPTH parsing_layer_depth ;
+
+    /* Proprietary tag size */
+    DRV_IH_PROPRIETARY_TAG_SIZE proprietary_tag_size ;
+}
+DRV_IH_LOGICAL_PORT_CONFIG ;
+
+
+/******************************************************************************/
+/* Logical Ports Configuration                                                */
+/******************************************************************************/
+typedef struct
+{
+    /* Eth0 configuration */
+    DRV_IH_LOGICAL_PORT_CONFIG eth0_config ;
+
+    /* Eth1 configuration */
+    DRV_IH_LOGICAL_PORT_CONFIG eth1_config ;
+
+    /* Eth2 configuration */
+    DRV_IH_LOGICAL_PORT_CONFIG eth2_config ;
+
+    /* Eth3 configuration */
+    DRV_IH_LOGICAL_PORT_CONFIG eth3_config ;
+
+    /* Eth4 configuration */
+    DRV_IH_LOGICAL_PORT_CONFIG eth4_config ;
+
+    /* GPON configuration */
+    DRV_IH_LOGICAL_PORT_CONFIG gpon_config ;
+
+    /* Runner A configuration */
+    DRV_IH_LOGICAL_PORT_CONFIG runner_a_config ;
+
+    /* Runner B configuration */
+    DRV_IH_LOGICAL_PORT_CONFIG runner_b_config ;
+
+    /* PCIE0 configuration */
+    DRV_IH_LOGICAL_PORT_CONFIG pcie0_config ;
+
+    /* PCIE1 configuration */
+    DRV_IH_LOGICAL_PORT_CONFIG pcie1_config ;
+}
+DRV_IH_LOGICAL_PORTS_CONFIG ;
+
+
+
+
+/******************************************************************************/
+/* Lookup table size                                                          */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_LOOKUP_TABLE_SIZE_32_ENTRIES ,
+    DRV_IH_LOOKUP_TABLE_SIZE_64_ENTRIES ,
+    DRV_IH_LOOKUP_TABLE_SIZE_128_ENTRIES ,
+    DRV_IH_LOOKUP_TABLE_SIZE_256_ENTRIES ,
+    DRV_IH_LOOKUP_TABLE_SIZE_512_ENTRIES ,
+    DRV_IH_LOOKUP_TABLE_SIZE_1024_ENTRIES ,
+    DRV_IH_LOOKUP_TABLE_SIZE_2048_ENTRIES ,
+    DRV_IH_LOOKUP_TABLE_SIZE_4096_ENTRIES
+}
+DRV_IH_LOOKUP_TABLE_SIZE ;
+
+
+/******************************************************************************/
+/* Lookup table hash type                                                     */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_LOOKUP_TABLE_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS ,
+    DRV_IH_LOOKUP_TABLE_HASH_TYPE_CRC16
+}
+DRV_IH_LOOKUP_TABLE_HASH_TYPE ;
+
+
+
+/******************************************************************************/
+/* Lookup table maximal search depth                                          */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_1_STEP ,
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_2_STEPS ,
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_4_STEPS ,
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_8_STEPS ,
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_16_STEPS ,
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_32_STEPS ,
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_64_STEPS ,
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_128_STEPS ,
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_256_STEPS ,
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_512_STEPS ,
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH_1024_STEPS
+}
+DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH ;
+
+
+/******************************************************************************/
+/* Lookup context table entry size                                            */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE_1_BYTE ,
+    DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE_2_BYTES ,
+    DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE_4_BYTES ,
+    DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE_INTERNAL_ENTRY
+}
+DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE ;
+
+
+/******************************************************************************/
+/* Lookup key extension                                                       */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_LOOKUP_KEY_EXTENSION_DISABLE ,
+    DRV_IH_LOOKUP_KEY_EXTENSION_SOURCE_PORT ,
+    DRV_IH_LOOKUP_KEY_EXTENSION_GEM_FLOW_ID ,
+    DRV_IH_LOOKUP_KEY_EXTENSION_WAN
+}
+DRV_IH_LOOKUP_KEY_EXTENSION ;
+
+
+/******************************************************************************/
+/* Lookup table 60 bit key configuration                                      */
+/******************************************************************************/
+typedef struct
+{
+    /* Table base address in 8 byte resolution */
+    uint16_t table_base_address_in_8_byte ;
+
+    /* Table size */
+    DRV_IH_LOOKUP_TABLE_SIZE table_size ;
+
+    /* Maximal search depth */
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH maximal_search_depth ;
+
+    /* Hash type */
+    DRV_IH_LOOKUP_TABLE_HASH_TYPE hash_type ;
+
+    /* This flag invokes additional comparison of source port for "move"
+       indication */
+    int32_t sa_search_enable ;
+
+    /* When this flag is enabled, look-up engine will de-assert aging bit in
+       case of search match */
+    int32_t aging_enable ;
+
+    /* CAM enable */
+    int32_t cam_enable ;
+
+    /* CAM base address in 8 byte resolution */
+    uint16_t cam_base_address_in_8_byte ;
+
+    /* Context table base address in 8 byte resolution */
+    uint16_t context_table_base_address_in_8_byte ;
+
+    /* Context table entry size */
+    DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE context_table_entry_size ;
+
+    /* CAM context base address in 8 byte resolution */
+    uint16_t cam_context_base_address_in_8_byte ;
+
+    /* Part 0 start offset in 4 byte resolution */
+    uint8_t part_0_start_offset_in_4_byte ;
+
+    /* Part 0 shift offset in 4 bit resolution */
+    uint8_t part_0_shift_offset_in_4_bit ;
+
+    /* Part 1 start offset in 4 byte resolution */
+    uint8_t part_1_start_offset_in_4_byte ;
+
+    /* Part 1 shift offset in 4 bit resolution */
+    uint8_t part_1_shift_offset_in_4_bit ;
+
+    /* Extension option for search key (always concatenated with MS bits) */
+    DRV_IH_LOOKUP_KEY_EXTENSION key_extension ;
+
+    /* Lower 32 bits of part 0 mask */
+    uint32_t part_0_mask_low ;
+
+    /* higher 28 bits of part 0 mask */
+    uint32_t part_0_mask_high ;
+
+    /* Lower 32 bits of part 1 mask */
+    uint32_t part_1_mask_low ;
+
+    /* higher 28 bits of part 1 mask */
+    uint32_t part_1_mask_high ;
+
+    /* Global mask in 4 bit resolution (only 15 LS bits are used, 15*4=60
+       bits mask) */
+    uint16_t global_mask_in_4_bit ;
+}
+DRV_IH_LOOKUP_TABLE_60_BIT_KEY_CONFIG ;
+
+
+/******************************************************************************/
+/* Lookup table 120 bit key configuration                                     */
+/******************************************************************************/
+typedef struct
+{
+    /* Table base address in 8 byte resolution */
+    uint16_t table_base_address_in_8_byte ;
+
+    /* Table size */
+    DRV_IH_LOOKUP_TABLE_SIZE table_size ;
+
+    /* Maximal search depth */
+    DRV_IH_LOOKUP_TABLE_MAXIMAL_SEARCH_DEPTH maximal_search_depth ;
+
+    /* Hash type */
+    DRV_IH_LOOKUP_TABLE_HASH_TYPE hash_type ;
+
+    /* When this flag is enabled, look-up engine will de-assert aging bit in
+       case of search match */
+    int32_t aging_enable ;
+
+    /* CAM enable */
+    int32_t cam_enable ;
+
+    /* CAM base address in 8 byte resolution */
+    uint16_t cam_base_address_in_8_byte ;
+
+    /* Context table base address in 8 byte resolution */
+    uint16_t context_table_base_address_in_8_byte ;
+
+    /* Context table entry size */
+    DRV_IH_LOOKUP_CONTEXT_TABLE_ENTRY_SIZE context_table_entry_size ;
+
+    /* CAM context base address in 8 byte resolution */
+    uint16_t cam_context_base_address_in_8_byte ;
+
+    /* Primary key part 0 start offset in 4 byte resolution */
+    uint8_t primary_key_part_0_start_offset_in_4_byte ;
+
+    /* Primary key part 0 shift offset in 4 bit resolution */
+    uint8_t primary_key_part_0_shift_offset_in_4_bit ;
+
+    /* Primary key part 1 start offset in 4 byte resolution */
+    uint8_t primary_key_part_1_start_offset_in_4_byte ;
+
+    /* Primary key part 1 shift offset in 4 bit resolution */
+    uint8_t primary_key_part_1_shift_offset_in_4_bit ;
+
+    /* Extension option for search key (always concatenated with MS bits) */
+    DRV_IH_LOOKUP_KEY_EXTENSION primary_key_extension ;
+
+    /* Lower 32 bits of part 0 mask */
+    uint32_t primary_key_part_0_mask_low ;
+
+    /* higher 28 bits of part 0 mask */
+    uint32_t primary_key_part_0_mask_high ;
+
+    /* Lower 32 bits of part 1 mask */
+    uint32_t primary_key_part_1_mask_low ;
+
+    /* higher 28 bits of part 1 mask */
+    uint32_t primary_key_part_1_mask_high ;
+
+    /* Secondary key part 0 start offset in 4 byte resolution */
+    uint8_t secondary_key_part_0_start_offset_in_4_byte ;
+
+    /* Secondary key part 0 shift offset in 4 bit resolution */
+    uint8_t secondary_key_part_0_shift_offset_in_4_bit ;
+
+    /* Secondary key part 1 start offset in 4 byte resolution */
+    uint8_t secondary_key_part_1_start_offset_in_4_byte ;
+
+    /* Secondary key part 1 shift offset in 4 bit resolution */
+    uint8_t secondary_key_part_1_shift_offset_in_4_bit ;
+
+    /* Extension option for search key (always concatenated with MS bits) */
+    DRV_IH_LOOKUP_KEY_EXTENSION secondary_key_extension ;
+
+    /* Lower 32 bits of part 0 mask */
+    uint32_t secondary_key_part_0_mask_low ;
+
+    /* higher 28 bits of part 0 mask */
+    uint32_t secondary_key_part_0_mask_high ;
+
+    /* Lower 32 bits of part 1 mask */
+    uint32_t secondary_key_part_1_mask_low ;
+
+    /* higher 28 bits of part 1 mask */
+    uint32_t secondary_key_part_1_mask_high ;
+
+    /* Global mask in 4 bit resolution (only 15 LS bits are used, 15*4=60
+       bits mask) */
+    uint16_t global_mask_in_4_bit ;
+}
+DRV_IH_LOOKUP_TABLE_120_BIT_KEY_CONFIG ;
+
+
+/******************************************************************************/
+/* Class search                                                               */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_0 ,
+    DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_1 ,
+    DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_2 ,
+    DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_3 ,
+    DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_4 ,
+    DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_5 ,
+    DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_6 ,
+    DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_7 ,
+    DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_8 ,
+    DRV_IH_CLASS_SEARCH_LOOKUP_TABLE_9 ,
+    DRV_IH_CLASS_SEARCH_DISABLED       = 15
+}
+DRV_IH_CLASS_SEARCH ;
+
+
+/******************************************************************************/
+/* Operation based on class search                                            */
+/* There are several operations which can be either diabled or based on       */
+/* search 1 or based on search 3.                                             */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_OPERATION_DISABLED ,
+    DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH1 ,
+    DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH_BASED_ON_SEARCH3
+}
+DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH ;
+
+
+/******************************************************************************/
+/* Target memory                                                              */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_TARGET_MEMORY_DDR ,
+    DRV_IH_TARGET_MEMORY_SRAM
+}
+DRV_IH_TARGET_MEMORY ;
+
+
+/******************************************************************************/
+/* Ingress QOS                                                                */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_INGRESS_QOS_LOW = 0 ,
+    DRV_IH_INGRESS_QOS_HIGH = 1 ,
+    DRV_IH_INGRESS_QOS_EXCLUSIVE = 3
+}
+DRV_IH_INGRESS_QOS ;
+
+
+/******************************************************************************/
+/* Runner cluster                                                             */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_RUNNER_CLUSTER_A ,
+    DRV_IH_RUNNER_CLUSTER_B
+}
+DRV_IH_RUNNER_CLUSTER ;
+
+
+/******************************************************************************/
+/* Class Configuration                                                        */
+/******************************************************************************/
+typedef struct
+{
+    /* Class search 1 */
+    DRV_IH_CLASS_SEARCH class_search_1 ;
+
+    /* Class search 2 */
+    DRV_IH_CLASS_SEARCH class_search_2 ;
+
+    /* Class search 3 */
+    DRV_IH_CLASS_SEARCH class_search_3 ;
+
+    /* Class search 4 */
+    DRV_IH_CLASS_SEARCH class_search_4 ;
+
+    /* Destination Port extraction. Destination Port is used when accessing target matrix. */
+    DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH destination_port_extraction ;
+
+    /* Drop on miss */
+    DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH drop_on_miss ;
+
+    /* DSCP to TCI table index. Used for untagged IP packets. */
+    uint8_t dscp_to_tci_table_index ;
+
+    /* Direct mode default */
+    int32_t direct_mode_default ;
+
+    /* Direct mode override. If true, direct-mode is taken from Target Matrix */
+    int32_t direct_mode_override ;
+
+    /* Target memory default */
+    DRV_IH_TARGET_MEMORY target_memory_default ;
+
+    /* Target memory override. If true, target memory is taken from Target
+       Matrix */
+    int32_t target_memory_override ;
+
+    /* Ingress QoS default */
+    DRV_IH_INGRESS_QOS ingress_qos_default ;
+
+    /* Ingress QoS override. */
+    DRV_IH_OPERATION_BASED_ON_CLASS_SEARCH ingress_qos_override ;
+
+    /* Target Runner Default */
+    DRV_IH_RUNNER_CLUSTER target_runner_default ;
+
+    /* Target Runner override in direct mode. If enabled, no load balancing
+       is performed. Direct mode decision might be done based on Target
+       Matrix. */
+    int32_t target_runner_override_in_direct_mode ;
+
+    /* Target Runner for direct mode. If "Target Runner override in direct
+       mode" is enabled, this target runner is chosen instead of the default
+       target runner */
+    DRV_IH_RUNNER_CLUSTER target_runner_for_direct_mode ;
+
+    /* Load balancing enable. Enable: Behavior according to Preference Load
+       Balancing. Disable: default target runner is used. */
+    int32_t load_balancing_enable ;
+
+    /* Preference Load Balancing enable. Enable: prefer default runner.
+       Disable: prefer previous runner. Irrelevant if load balancing is
+       disabled. */
+    int32_t preference_load_balancing_enable ;
+}
+DRV_IH_CLASS_CONFIG ;
+
+
+/******************************************************************************/
+/* Logical port                                                               */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_LOGICAL_PORT_ETH0      = 0x0 ,
+    DRV_IH_LOGICAL_PORT_ETH1      = 0x1 ,
+    DRV_IH_LOGICAL_PORT_ETH2      = 0x2 ,
+    DRV_IH_LOGICAL_PORT_ETH3      = 0x3 ,
+    DRV_IH_LOGICAL_PORT_ETH4      = 0x4,
+    DRV_IH_LOGICAL_PORT_GPON      = 0x5 ,
+    DRV_IH_LOGICAL_PORT_RUNNER_A  = 0x6 ,
+    DRV_IH_LOGICAL_PORT_RUNNER_B  = 0xE ,
+    DRV_IH_LOGICAL_PORT_PCIE0     = 0x7 ,
+    DRV_IH_LOGICAL_PORT_PCIE1     = 0x8
+}
+DRV_IH_LOGICAL_PORT ;
+
+
+/******************************************************************************/
+/* L2 protocol                                                                */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_L2_PROTOCOL_UNKNOWN = 0x0 ,
+    DRV_IH_L2_PROTOCOL_PPPOE_DISCOVERY = 0x1 ,
+    DRV_IH_L2_PROTOCOL_PPPOE_SESSION = 0x2 ,
+    DRV_IH_L2_PROTOCOL_IPV4OE = 0x4 ,
+    DRV_IH_L2_PROTOCOL_IPV6OE = 0x5 ,
+    DRV_IH_L2_PROTOCOL_USER_DEFINED_0 = 0x8 ,
+    DRV_IH_L2_PROTOCOL_USER_DEFINED_1 = 0x9 ,
+    DRV_IH_L2_PROTOCOL_USER_DEFINED_2 = 0xA ,
+    DRV_IH_L2_PROTOCOL_USER_DEFINED_3 = 0xB ,
+    DRV_IH_L2_PROTOCOL_ARP = 0xC ,
+    DRV_IH_L2_PROTOCOL_TYPE1588 = 0xD ,
+    DRV_IH_L2_PROTOCOL_TYPE8021X = 0xE ,
+    DRV_IH_L2_PROTOCOL_TYPE8011AGCFM = 0xF
+}
+DRV_IH_L2_PROTOCOL ;
+
+
+/******************************************************************************/
+/* L3 protocol                                                                */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_L3_PROTOCOL_NONE ,
+    DRV_IH_L3_PROTOCOL_IPV4 ,
+    DRV_IH_L3_PROTOCOL_IPV6
+}
+DRV_IH_L3_PROTOCOL ;
+
+
+/******************************************************************************/
+/* L4 protocol                                                                */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_L4_PROTOCOL_NONE = 0x0 ,
+    DRV_IH_L4_PROTOCOL_TCP = 0x1 ,
+    DRV_IH_L4_PROTOCOL_UDP = 0x2 ,
+    DRV_IH_L4_PROTOCOL_IGMP = 0x3 ,
+    DRV_IH_L4_PROTOCOL_ICMP = 0x4 ,
+    DRV_IH_L4_PROTOCOL_ICMPV6 = 0x5 ,
+    DRV_IH_L4_PROTOCOL_ESP = 0x6 ,
+    DRV_IH_L4_PROTOCOL_GRE = 0x7 ,
+    DRV_IH_L4_PROTOCOL_USER_DEFINED_0 = 0x8 ,
+    DRV_IH_L4_PROTOCOL_USER_DEFINED_1 = 0x9 ,
+    DRV_IH_L4_PROTOCOL_USER_DEFINED_2 = 0xA ,
+    DRV_IH_L4_PROTOCOL_USER_DEFINED_3 = 0xB ,
+    DRV_IH_L4_PROTOCOL_IPV6 = 0xD ,
+    DRV_IH_L4_PROTOCOL_AH = 0xE ,
+    DRV_IH_L4_PROTOCOL_NOT_PARSED = 0XF
+}
+DRV_IH_L4_PROTOCOL ;
+
+
+/******************************************************************************/
+/* Classifier configuration                                                   */
+/******************************************************************************/
+typedef struct
+{
+    /* L2 protocol */
+    DRV_IH_L2_PROTOCOL l2_protocol ;
+
+    /* L3 protocol */
+    DRV_IH_L3_PROTOCOL l3_protocol ;
+
+    /* L4 protocol */
+    DRV_IH_L4_PROTOCOL l4_protocol ;
+
+    /* DA filter any hit */
+    int32_t da_filter_any_hit ;
+
+    /* Matched DA filter (There are 6 DA filters) */
+    uint8_t matched_da_filter ;
+
+    /* Multicast DA indication */
+    int32_t multicast_da_indication ;
+
+    /* Broadcast DA indication */
+    int32_t broadcast_da_indication ;
+
+    /* VID filter any hit */
+    int32_t vid_filter_any_hit ;
+
+    /* Matched VID filter (There are 12 VID filters) */
+    uint8_t matched_vid_filter ;
+
+    /* IP filter any hit */
+    int32_t ip_filter_any_hit ;
+
+    /* Matched IP filter (There are 4 IP filters) */
+    uint8_t matched_ip_filter ;
+
+    /* WAN indication */
+    int32_t wan_indication ;
+
+    /* Five tuple valid */
+    int32_t five_tuple_valid ;
+
+    /* Logical source port */
+    DRV_IH_LOGICAL_PORT logical_source_port ;
+
+    /* Error */
+    int32_t error ;
+
+    /* 32 bit mask */
+    uint32_t mask ;
+
+    /* Resulting class */
+    uint8_t resulting_class ;
+}
+DRV_IH_CLASSIFIER_CONFIG ;
+
+
+/******************************************************************************/
+/* Source port to ingress queue mapping                                       */
+/******************************************************************************/
+typedef struct
+{
+    /* Eth0 ingress queue */
+    uint8_t eth0_ingress_queue ;
+
+    /* Eth1 ingress queue */
+    uint8_t eth1_ingress_queue ;
+
+    /* Eth2 ingress queue */
+    uint8_t eth2_ingress_queue ;
+
+    /* Eth3 ingress queue */
+    uint8_t eth3_ingress_queue ;
+
+    /* Eth4 ingress queue */
+    uint8_t eth4_ingress_queue ;
+
+    /* GPON ingress queue */
+    uint8_t gpon_ingress_queue ;
+
+    /* Runner A ingress queue */
+    uint8_t runner_a_ingress_queue ;
+
+    /* Runner B ingress queue */
+    uint8_t runner_b_ingress_queue ;
+}
+DRV_IH_SOURCE_PORT_TO_INGRESS_QUEUE_MAPPING ;
+
+
+/******************************************************************************/
+/* Ingress queue configuration                                                */
+/******************************************************************************/
+typedef struct
+{
+    /* Base location in the 16-entries ingress queue array */
+    uint8_t base_location ;
+
+    /* Size. Sum of sizes of all queues is up to 16 */
+    uint8_t size ;
+
+    /* Priority. lower value means lower priority. allowed values: 0-7 */
+    uint8_t priority ;
+
+    /* Weight. lower weight value means lower weight. Weight is relevant only
+       for two or more queues with the same priority. */
+    uint8_t weight ;
+
+    /* Congestion threshold. When the number of total Runner Buffers (either
+       Runner A or Runner B) reaches the defined threshold per queue - IH
+       stops serving this queue. */
+    uint8_t congestion_threshold ;
+}
+DRV_IH_INGRESS_QUEUE_CONFIG ;
+
+
+/******************************************************************************/
+/* Target Matrix source port                                                  */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH0 ,
+    DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH1 ,
+    DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH2 ,
+    DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH3 ,
+    DRV_IH_TARGET_MATRIX_SOURCE_PORT_ETH4 ,
+    DRV_IH_TARGET_MATRIX_SOURCE_PORT_GPON ,
+    DRV_IH_TARGET_MATRIX_SOURCE_PORT_PCIE0 ,
+    DRV_IH_TARGET_MATRIX_SOURCE_PORT_PCIE1 ,
+
+    DRV_IH_TARGET_MATRIX_NUMBER_OF_SOURCE_PORTS
+}
+DRV_IH_TARGET_MATRIX_SOURCE_PORT ;
+
+
+/******************************************************************************/
+/* Target Matrix destination port                                             */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH0 ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH1 ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH2 ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH3 ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ETH4 ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_GPON ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE0 ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_PCIE1 ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_CPU ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_MULTICAST ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ALWAYS_DDR ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_ALWAYS_SRAM ,
+    DRV_IH_TARGET_MATRIX_DESTINATION_PORT_SPARE ,
+
+    DRV_IH_TARGET_MATRIX_NUMBER_OF_DESTINATION_PORTS
+}
+DRV_IH_TARGET_MATRIX_DESTINATION_PORT ;
+
+
+/******************************************************************************/
+/* Target matrix entry                                                        */
+/******************************************************************************/
+typedef struct
+{
+    /* target memory */
+    DRV_IH_TARGET_MEMORY target_memory ;
+
+    /* direct mode */
+    int32_t direct_mode ;
+}
+DRV_IH_TARGET_MATRIX_ENTRY ;
+
+
+
+/******************************************************************************/
+/* Target matrix per SP configuration                                         */
+/******************************************************************************/
+typedef struct
+{
+    /* an array of all entries of a certain source port. */
+    DRV_IH_TARGET_MATRIX_ENTRY entry [ DRV_IH_TARGET_MATRIX_NUMBER_OF_DESTINATION_PORTS ] ;
+}
+DRV_IH_TARGET_MATRIX_PER_SP_CONFIG ;
+
+
+/******************************************************************************/
+/* WAN ports configuration                                                    */
+/* value of true indicates that the corresponding port belongs to WAN         */
+/******************************************************************************/
+typedef struct
+{
+    /* Eth0 */
+    int32_t eth0 ;
+
+    /* Eth1 */
+    int32_t eth1 ;
+
+    /* Eth2 */
+    int32_t eth2 ;
+
+    /* Eth3 */
+    int32_t eth3 ;
+
+    /* Eth4 */
+    int32_t eth4 ;
+
+    /* GPON */
+    int32_t gpon ;
+
+    /* Runner A */
+    int32_t runner_a ;
+
+    /* Runner B */
+    int32_t runner_b ;
+
+    /* PCIE0 */
+    int32_t pcie0 ;
+
+    /* PCIE1 */
+    int32_t pcie1 ;
+}
+DRV_IH_WAN_PORTS_CONFIG ;
+
+
+/******************************************************************************/
+/* Ethertypes for QTAG nesting                                                */
+/* The first 2 Ethertypes indices are for the user defined Ethertypes         */
+/* configured by Set Ethertypes for QTAG Identification API.                  */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_ETHERTYPE_FOR_QTAG_NESTING_USER_DEFIEND_0 ,
+    DRV_IH_ETHERTYPE_FOR_QTAG_NESTING_USER_DEFIEND_1 ,
+    DRV_IH_ETHERTYPE_FOR_QTAG_NESTING_8100 ,
+    DRV_IH_ETHERTYPE_FOR_QTAG_NESTING_88A8 ,
+    DRV_IH_ETHERTYPE_FOR_QTAG_NESTING_9100 ,
+    DRV_IH_ETHERTYPE_FOR_QTAG_NESTING_9200 ,
+
+    DRV_IH_NUMBER_OF_ETHERTYPES_FOR_QTAG_NESTING
+}
+DRV_IH_ETHERTYPE_FOR_QTAG_NESTING ;
+
+
+/******************************************************************************/
+/* Critical Bits                                                              */
+/******************************************************************************/
+typedef struct
+{
+    int32_t iq_fifo_full ;
+
+    int32_t iq0_fifo_full ;
+
+    int32_t iq1_fifo_full ;
+
+    int32_t iq2_fifo_full ;
+
+    int32_t iq3_fifo_full ;
+
+    int32_t iq4_fifo_full ;
+
+    int32_t iq5_fifo_full ;
+
+    int32_t iq6_fifo_full ;
+
+    int32_t iq7_fifo_full ;
+
+    int32_t lookup_1_stuck ;
+
+    int32_t lookup_2_stuck ;
+
+    int32_t lookup_3_stuck ;
+
+    int32_t lookup_4_stuck ;
+
+    int32_t look_up_packet_command_fifo_full ;
+
+    int32_t egress_tx_data_fifo_full ;
+
+    int32_t egress_tx_message_fifo_full ;
+
+    int32_t egress_queue_packet_command_fifo_full ;
+}
+DRV_IH_CRITICAL_BITS ;
+
+
+/******************************************************************************/
+/* Parser Configuration                                                       */
+/******************************************************************************/
+typedef struct
+{
+    /* Defines which TCP flags set will cause TCP_FLAG bit in summary word to
+       be set */
+    uint8_t tcp_flags ;
+
+    /* 4-bits mask which defines which status bits will cause exception bit
+       in summary word to be set. The cause vector is {IP fragment, IP
+       version error, IP checksum error, IP header length error}. */
+    uint8_t exception_status_bits ;
+
+    /* when this flag is set, PPP with code 1 is identified as IPV6 (instead of IPV4) */
+    int32_t ppp_code_1_ipv6 ;
+
+    /* 3-bits mask which defines which IPV6 extension headers types will cause 
+       'IPV6 extension header' indication in the summary word. the bits order is:
+       {Destination Options (MSB), Routing Header, Hop-by-Hop Options (LSB)} */
+    uint8_t ipv6_extension_header_bitmask ; 
+
+    /* SNAP user defined organization Code. 24 bit value. This is a
+       user-defined code which is used in addition to RFC1042 and 802.1Q (in
+       case they are enalbed). */
+    uint32_t snap_user_defined_organization_code ;
+
+    /* SNAP RFC1042 encapsulation enable. */
+    int32_t snap_rfc1042_encapsulation_enable ;
+
+    /* SNAP 802.1Q encapsulation enable. */
+    int32_t snap_802_1q_encapsulation_enable ;
+
+    /* GRE protocol. Used for VPN. 16 bit value which is compared to "Protocol
+       type" field of the GRE header. */
+    uint16_t gre_protocol ;
+
+	uint32_t eng_cfg;
+}
+DRV_IH_PARSER_CONFIG ;
+
+
+/******************************************************************************/
+/* IP Filter Selection                                                        */
+/* The enumeration values are compatible with the values used by the HW.      */
+/******************************************************************************/
+typedef enum
+{
+    DRV_IH_IP_FILTER_SELECTION_SOURCE_IP ,
+    DRV_IH_IP_FILTER_SELECTION_DESTINATION_IP
+}
+DRV_IH_IP_FILTER_SELECTION ;
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Functions prototypes                                                       */
+/*                                                                            */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_general_configuration                                   */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set general configuration                                    */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets general configuration of the IH block.                */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ih_general_config - IH general configuration.                         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_general_configuration ( const DRV_IH_GENERAL_CONFIG * xi_ih_general_config ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_packet_header_offsets                                   */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set packet header offsets                                    */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets packet header offset for each physical port.          */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_packet_header_offsets - Packet header offsets                         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_packet_header_offsets ( const DRV_IH_PACKET_HEADER_OFFSETS * xi_packet_header_offsets ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_runner_buffers_configuration                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Runner Buffers configuration                             */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets runner-buffers related configuration, for each        */
+/*   runner.                                                                  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_runner_buffers_config - Runner Buffers Configuration                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_runner_buffers_configuration ( const DRV_IH_RUNNER_BUFFERS_CONFIG * xi_runner_buffers_config ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_runners_load_thresholds                                 */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Runners Load Thresholds                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets thresholds related to runner load, for each runner.   */
+/*   The thresholds are in number of occupied Runner Buffers.                 */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_runners_load_thresholds - Runners Load Thresholds (in number of       */
+/*     occupied Runner Buffers)                                               */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_runners_load_thresholds ( const DRV_IH_RUNNERS_LOAD_THRESHOLDS * xi_runners_load_thresholds ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_route_addresses                                         */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Route Addresses                                          */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets route address for each physical port. The route       */
+/*   address is used for broad-bus access for sending responses, message and  */
+/*   data.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_route_addresses - Route Addresses                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_route_addresses ( const DRV_IH_ROUTE_ADDRESSES * xi_route_addresses ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_logical_ports_configuration                             */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Logical Ports Configuration                              */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets configuration of the following logical ports:         */
+/*   Ethernet 0-4, GPON, Runner A, Runner B and PCIE 0-1. The following       */
+/*   parameters are configured per port: Parsing layer depth, Proprietary tag */
+/*   size.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_logical_ports_config - Logical Ports Configuration                    */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_logical_ports_configuration ( const DRV_IH_LOGICAL_PORTS_CONFIG * xi_logical_ports_config ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_lut_60_bit_key                                    */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure Lookup Table 60 bit key                            */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures a lookup table with 60-bit key. There is a      */
+/*   total of 10 tables. Note that when configuring a lookup table with       */
+/*   120-bit key (with dedicated API), it occupies 2 tables. The lookup key   */
+/*   is obtained by ORing two 60-bit parts taken from the parser result. Each */
+/*   part has a configurable offset, and optionally a shift & rotate          */
+/*   operation. Initially 64 bits are taken from the configured offset, then  */
+/*   shift & rotate is optionally done, then the 4 MS-bits are omitted. Then  */
+/*   each part is masked with its own mask. Then ORing the left 60 bits of    */
+/*   the 2 parts yields the key. Then a key-extension can optionally be done, */
+/*   i.e. ORing the MS-bits of the key with one of the following values: (1)  */
+/*   5-bit Source Port from Header Descriptor. (2) 8-bit GEM Flow ID from     */
+/*   Header Descriptor. (3) 1-bit WAN/LAN indication extracted from           */
+/*   configuration of the source port. The global mask is applied on both key */
+/*   & LUT entry when comparing between them. Move indication: When "Source   */
+/*   port search enable" parameter is enabled, additional comparison will be  */
+/*   done, between source-port (from Header descriptor) and bits 56:52 of LUT */
+/*   entry, where source-port value should reside. In this case, the global   */
+/*   mask must mask these bits for the regular comparison between the key and */
+/*   LUT entry, which would be a MAC address comparison. If both comparisons  */
+/*   match, the result would be "hit". If only MAC address comparison         */
+/*   matches, the result would be "move".                                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_table_index - Table index                                             */
+/*                                                                            */
+/*   xi_lookup_table_60_bit_key_config - Lookup table 60 bit key              */
+/*     configuration                                                          */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_lut_60_bit_key ( uint8_t xi_table_index ,
+                                                            const DRV_IH_LOOKUP_TABLE_60_BIT_KEY_CONFIG * xi_lookup_table_60_bit_key_config ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_class                                             */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure Class                                              */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures an IH class. Ingress handler class is type of   */
+/*   ingress traffic, e.g. IPTV, bridged, routed. Each class includes         */
+/*   predefined set of settings, such as: target runner, destination memory,  */
+/*   QoS, definition of look-up searches. There are up to 16 classes. Each    */
+/*   physical port has a default class (For GPON port, default class is per   */
+/*   GEM flow). IH may override the default class according to                */
+/*   enable-override configuration and to classification based on reduced     */
+/*   Parser results, called "Classifier Key Word" (Parser Summary Word plus   */
+/*   source port). Default classes and override-enable configurations are in  */
+/*   BBH. In runner flow, runner assigns an initial class (which can be       */
+/*   overridden by IH). Class override is done using classifiers, which are   */
+/*   configured using Configure Classifier API.                               */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_class_index - Class index                                             */
+/*                                                                            */
+/*   xi_class_config - Class Configuration                                    */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_class ( uint8_t xi_class_index ,
+                                                   const DRV_IH_CLASS_CONFIG * xi_class_config ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_classifier_configuration                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get Classifier configuration                                 */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets the configuration of a Classifier.                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_classifier_index - Classifier index                                   */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_classifier_config - Classifier configuration                          */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_classifier_configuration ( uint8_t xi_classifier_index ,
+                                                                DRV_IH_CLASSIFIER_CONFIG * const xo_classifier_config ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_remove_classifier                                           */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Remove Classifier                                            */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function removes a classifier which was configured by Configure     */
+/*   Classifier API. There is no "enable" bit - this function actually sets   */
+/*   the mask to 0 and the key to 11...1 (bitwise) so there will never be a   */
+/*   match.                                                                   */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_classifier_index - Classifier index                                   */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_remove_classifier ( uint8_t xi_classifier_index ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_source_port_to_ingress_queue_mapping                    */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set source port to ingress queue mapping                     */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets the mapping of physical source ports (eth0-4, GPON,   */
+/*   runner A, runner B) to ingress queues. There are 8 ingress queues. BBH   */
+/*   or runner (in case of runner flow) writes the Header Descriptor to one   */
+/*   of these queues, according to the configuration of the source port.      */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_source_port_to_ingress_queue_mapping - Source port to ingress queue   */
+/*     mapping                                                                */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_source_port_to_ingress_queue_mapping ( const DRV_IH_SOURCE_PORT_TO_INGRESS_QUEUE_MAPPING * xi_source_port_to_ingress_queue_mapping ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_ingress_queue                                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure ingress queue                                      */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures an ingress queue. There are 8 queues. All of    */
+/*   them reside in the same Ingress-queue (IQ) array of 16 entries (ingress  */
+/*   buffers). E.g. queue 0 occupies entries 0-1, queue 1 occupies entries    */
+/*   2-3, etc.                                                                */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ingress_queue_index - Ingress queue index                             */
+/*                                                                            */
+/*   xi_ingress_queue_config - Ingress queue configuration                    */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_ingress_queue ( uint8_t xi_ingress_queue_index ,
+                                                           const DRV_IH_INGRESS_QUEUE_CONFIG * xi_ingress_queue_config ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_target_matrix                                           */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Target Matrix                                            */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets the per-source-port configuration in the target       */
+/*   matrix, i.e. all entries which belong to the given source port.          */
+/*   Each entry consists of the following parameters: target memory           */
+/*   (DDR/SRAM), direct mode (true/false).                                    */
+/*   The function will fail when trying to configure an "Always DDR" entry    */
+/*   with Target memory = SRAM, or "Always SRAM" entry with                   */
+/*   Target memory = DDR.                                                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_source_port - Source port                                             */
+/*                                                                            */
+/*   xi_per_sp_config - Per-source-port configuration                         */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_target_matrix ( DRV_IH_TARGET_MATRIX_SOURCE_PORT xi_source_port ,
+                                                     const DRV_IH_TARGET_MATRIX_PER_SP_CONFIG * xi_per_sp_config ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_forward                                                 */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Target Forward                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets the "forward-enable" bit for the given source         */
+/*   port and destination port.                                               */
+/*   The "forward-enable" is only indication to FW (IH doesn't drop if        */
+/*   forwarding is disabled).                                                 */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_source_port - Source port                                             */
+/*                                                                            */
+/*   xi_destination_port - Destination port                                   */
+/*                                                                            */
+/*   xi_forward - Forward                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_forward ( DRV_IH_TARGET_MATRIX_SOURCE_PORT xi_source_port ,
+                                               DRV_IH_TARGET_MATRIX_DESTINATION_PORT xi_destination_port ,
+                                               int32_t xi_forward ) ;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_wan_ports                                         */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure WAN ports                                          */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures, for each logical port, whether it belongs to   */
+/*   WAN traffic. IH uses this configuration for WAN indication in the parser */
+/*   result (and Classifier Key Word).                                        */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_wan_ports_config - WAN ports configuration                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_wan_ports ( const DRV_IH_WAN_PORTS_CONFIG * xi_wan_ports_config ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_allocated_runner_buffers_counters                       */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get allocated runner buffers counters                        */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function returns the current number of allocated Runner Buffers of  */
+/*   each runner.                                                             */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_runner_a_counter - Runner A counter                                   */
+/*                                                                            */
+/*   xo_runner_b_counter - Runner B counter                                   */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_allocated_runner_buffers_counters ( uint32_t * const xo_runner_a_counter ,
+                                                                         uint32_t * const xo_runner_b_counter ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_critical_bits                                           */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get Critical Bits                                            */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function returns the status of the critical bits (debug             */
+/*   indications).                                                            */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_critical_bits - Critical Bits                                         */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_critical_bits ( DRV_IH_CRITICAL_BITS * const xo_critical_bits ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_parser                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure Parser                                             */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures general parameters in the parser accelerator in */
+/*   IH.                                                                      */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_parser_config - Parser Configuration                                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_parser ( const DRV_IH_PARSER_CONFIG * xi_parser_config ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_da_filter_enable_status                                 */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get DA filter enable status                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets the enable status of a DA filter.                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_filter_index - Filter index                                           */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_enable - Enable                                                       */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_da_filter_enable_status ( uint8_t xi_filter_index ,
+                                                               int32_t * const xo_enable ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_ethertypes_for_qtag_identification                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set Ethertypes for QTAG identification                       */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets two user-defined Ethertypes for QTAG (VLAN tag)       */
+/*   identification.                                                          */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ethertype_0 - Ethertype 0                                             */
+/*                                                                            */
+/*   xi_ethertype_1 - Ethertype 1                                             */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_ethertypes_for_qtag_identification ( uint16_t xi_ethertype_0 ,
+                                                                          uint16_t xi_ethertype_1 ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_ethertypes_for_qtag_identification                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get Ethertypes for QTAG identification                       */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets the two user-defined Ethertypes for QTAG (VLAN tag)   */
+/*   identification                                                           */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_ethertype_0 - Ethertype 0                                             */
+/*                                                                            */
+/*   xo_ethertype_1 - Ethertype 1                                             */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_ethertypes_for_qtag_identification ( uint16_t * const xo_ethertype_0 ,
+                                                                          uint16_t * const xo_ethertype_1 ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_qtag_nesting                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure QTAG Nesting                                       */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures, for 6 possible Ethertypes, whether each        */
+/*   Ethertype can be used for QTAG identification, as inner and as outer     */
+/*   tag. Note that when packet has a single tag, parser treats it as outer   */
+/*   tag.                                                                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ethertype_index - Ethertype index                                     */
+/*                                                                            */
+/*   xi_use_as_outer - Use as outer                                           */
+/*                                                                            */
+/*   xi_use_as_inner - Use as inner                                           */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_qtag_nesting ( DRV_IH_ETHERTYPE_FOR_QTAG_NESTING xi_ethertype_index ,
+                                                          int32_t xi_use_as_outer ,
+                                                          int32_t xi_use_as_inner ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_qtag_nesting_configuration                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get QTAG Nesting configuration                               */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets the QTAG Nesting configuration of an Ethertype.       */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ethertype_index - Ethertype index                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_use_as_outer - Use as outer                                           */
+/*                                                                            */
+/*   xo_use_as_inner - Use as inner                                           */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_qtag_nesting_configuration ( DRV_IH_ETHERTYPE_FOR_QTAG_NESTING xi_ethertype_index ,
+                                                                  int32_t * const xo_use_as_outer ,
+                                                                  int32_t * const xo_use_as_inner ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_user_ethertype                                    */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure User Ethertype                                     */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures user defined Ethertype, to be indicated in "L2  */
+/*   Protocol" field in parser result. There are up to 4 user defined         */
+/*   Ethertypes. For such an Ethertype, the API configures which L3 protocol  */
+/*   comes after it, and its offset (for L3 parsing). In order to take        */
+/*   effect, the user Ethertype should be enabled using Enable User Ethertype */
+/*   API.                                                                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ethertype_index - Ethertype index                                     */
+/*                                                                            */
+/*   xi_ethertype_value - Ethertype value                                     */
+/*                                                                            */
+/*   xi_l3_protocol - L3 protocol                                             */
+/*                                                                            */
+/*   xi_l3_offset - L3 offset                                                 */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_user_ethertype ( uint8_t xi_ethertype_index ,
+                                                            uint16_t xi_ethertype_value ,
+                                                            DRV_IH_L3_PROTOCOL xi_l3_protocol ,
+                                                            uint8_t xi_l3_offset ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_user_ethertype_configuration                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get User Ethertype configuration                             */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets user defined Ethertype configuration.                 */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ethertype_index - Ethertype index                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_ethertype_value - Ethertype value                                     */
+/*                                                                            */
+/*   xo_l3_protocol - L3 protocol                                             */
+/*                                                                            */
+/*   xo_l3_offset - L3 offset                                                 */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_user_ethertype_configuration ( uint8_t xi_ethertype_index ,
+                                                                    uint16_t * const xo_ethertype_value ,
+                                                                    DRV_IH_L3_PROTOCOL * const xo_l3_protocol ,
+                                                                    uint8_t * const xo_l3_offset ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_enable_user_ethertype                                       */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Enable User Ethertype                                        */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function enables/disables a user-defined Ethertype which was        */
+/*   configured by Configure User Ethertype API.                              */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ethertype_index - Ethertype index                                     */
+/*                                                                            */
+/*   xi_enable - Enable                                                       */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_enable_user_ethertype ( uint8_t xi_ethertype_index ,
+                                                         int32_t xi_enable ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_user_ethertype_enable_status                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get User Ethertype enable status                             */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets the enable status of a user-defined Ethertype.        */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ethertype_index - Ethertype index                                     */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_enable - Enable                                                       */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_user_ethertype_enable_status ( uint8_t xi_ethertype_index ,
+                                                                    int32_t * const xo_enable ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_user_ip_l4_protocol                                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set user IP L4 protocol                                      */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets a user-defined L4 Protocol ID to be matched to        */
+/*   Protocol field in IP header and to be indicated in the output summary    */
+/*   word. There are up to 4 user-defined L4 protocols.                       */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_l4_protocol_index - L4 protocol index                                 */
+/*                                                                            */
+/*   xi_l4_protocol_value - L4 protocol value                                 */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_user_ip_l4_protocol ( uint8_t xi_l4_protocol_index ,
+                                                           uint8_t xi_l4_protocol_value ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_user_ip_l4_protocol                                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get user IP L4 protocol                                      */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets a user-defined L4 Protocol.                           */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_l4_protocol_index - L4 protocol index                                 */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_l4_protocol_value - L4 protocol value                                 */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_user_ip_l4_protocol ( uint8_t xi_l4_protocol_index ,
+                                                           uint8_t * const xo_l4_protocol_value ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_ppp_code                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set PPP code                                                 */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets PPP Protocol Code to indicate L3 is IP.               */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ppp_code_index - PPP code index                                       */
+/*                                                                            */
+/*   xi_ppp_code - PPP code                                                   */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_ppp_code ( uint8_t xi_ppp_code_index ,
+                                                uint16_t xi_ppp_code ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_ppp_code                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get PPP code                                                 */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets PPP Protocol Code.                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_ppp_code_index - PPP code index                                       */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_ppp_code - PPP code                                                   */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_ppp_code ( uint8_t xi_ppp_code_index ,
+                                                uint16_t * const xo_ppp_code ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_vid_filter                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set VID filter                                               */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets a VID filter. There are up to 12 VID filters. The     */
+/*   filter has to be enabled by Enable VID filter API in order to take       */
+/*   effect.                                                                  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_filter_index - Filter index                                           */
+/*                                                                            */
+/*   xi_vid - VID                                                             */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_vid_filter ( uint8_t xi_filter_index ,
+                                                  uint16_t xi_vid ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_vid_filter                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get VID filter                                               */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets a VID filter. There are up to 12 VID filters.         */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_filter_index - Filter index                                           */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_vid - VID                                                             */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_vid_filter ( uint8_t xi_filter_index ,
+                                                  uint16_t * const xo_vid ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_enable_vid_filter                                           */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Enable VID filter                                            */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function enables/disables a VID filter. There are up to 12 VID      */
+/*   filters. Before enabling a filter, it should be configured by Set VID    */
+/*   filter API.                                                              */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_filter_index - Filter index                                           */
+/*                                                                            */
+/*   xi_enable - Enable                                                       */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_enable_vid_filter ( uint8_t xi_filter_index ,
+                                                     int32_t xi_enable ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_vid_filter_enable_status                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get VID filter enable status                                 */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets the enable status of a VID filter. There are up to 12 */
+/*   VID filters.                                                             */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_filter_index - Filter index                                           */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_enable - Enable                                                       */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_vid_filter_enable_status ( uint8_t xi_filter_index ,
+                                                                int32_t * const xo_enable ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_ip_filter                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set IP filter                                                */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets an IP filter. There are up to 4 IP filters. The       */
+/*   filter has to be enabled by Enable IP filter API in order to take        */
+/*   effect.                                                                  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_filter_index - Filter index                                           */
+/*                                                                            */
+/*   xi_ip_address - IP address                                               */
+/*                                                                            */
+/*   xi_ip_address_mask - IP address mask                                     */
+/*                                                                            */
+/*   xi_selection - selection (SIP/DIP)                                       */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_ip_filter ( uint8_t xi_filter_index ,
+                                                 uint32_t xi_ip_address ,
+                                                 uint32_t xi_ip_address_mask ,
+                                                 DRV_IH_IP_FILTER_SELECTION xi_selection ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_ip_filter                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get IP filter                                                */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets an IP filter. There are up to 4 IP filters.           */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_filter_index - Filter index                                           */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_ip_address - IP address                                               */
+/*                                                                            */
+/*   xo_ip_address_mask - IP address mask                                     */
+/*                                                                            */
+/*   xo_selection - selection (SIP/DIP)                                       */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_ip_filter ( uint8_t xi_filter_index ,
+                                                 uint32_t * const xo_ip_address ,
+                                                 uint32_t * const xo_ip_address_mask ,
+                                                 DRV_IH_IP_FILTER_SELECTION * const xo_selection ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_enable_ip_filter                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Enable IP filter                                             */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function enables/disables an IP filter. There are up to 4 IP        */
+/*   filters. Before enabling a filter, it should be configured by Set IP     */
+/*   filter API.                                                              */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_filter_index - Filter index                                           */
+/*                                                                            */
+/*   xi_enable - Enable                                                       */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_enable_ip_filter ( uint8_t xi_filter_index ,
+                                                    int32_t xi_enable ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_ip_filter_enable_status                                 */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get IP filter enable status                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets the enable status of an IP filter. There are up to 4  */
+/*   IP filters.                                                              */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_filter_index - Filter index                                           */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_enable - Enable                                                       */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_ip_filter_enable_status ( uint8_t xi_filter_index ,
+                                                               int32_t * const xo_enable ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_dscp_to_tci_table_entry                                 */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set DSCP to TCI table entry                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets an entry in a DSCP to TCI table. There are 2 such     */
+/*   tables. Each class is configured with one of these tables. The table has */
+/*   to be enabled by Enable DSCP to TCI table API in order to take effect.   */
+/*   If a class is configured with a table which is not enabled, the TCI will */
+/*   be 0.                                                                    */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_table_index - Table index                                             */
+/*                                                                            */
+/*   xi_dscp - DSCP                                                           */
+/*                                                                            */
+/*   xi_tci - TCI                                                             */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_dscp_to_tci_table_entry ( uint8_t xi_table_index ,
+                                                               uint8_t xi_dscp ,
+                                                               uint8_t xi_tci ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_dscp_to_tci_table_entry                                 */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get DSCP to TCI table entry                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets an entry in a DSCP to TCI table. There are 2 such     */
+/*   tables.                                                                  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_table_index - Table index                                             */
+/*                                                                            */
+/*   xi_dscp - DSCP                                                           */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_tci - TCI                                                             */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_dscp_to_tci_table_entry ( uint8_t xi_table_index ,
+                                                               uint8_t xi_dscp ,
+                                                               uint8_t * const xo_tci ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_set_default_tci                                             */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Set default TCI                                              */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function sets default TCI, per DSCP to TCI table. The default is    */
+/*   used in case of non-IP untagged packet. The default TCI will take effect */
+/*   only after enabling the DSCP to TCI table, by Enable DSCP to TCI table   */
+/*   API. If a class is configured with a table which is not enabled, the TCI */
+/*   will be 0.                                                               */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_table_index - Table index                                             */
+/*                                                                            */
+/*   xi_default_tci - Default TCI                                             */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_set_default_tci ( uint8_t xi_table_index ,
+                                                   uint8_t xi_default_tci ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_default_tci                                             */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get default TCI                                              */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets the default TCI, per DSCP to TCI table.               */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_table_index - Table index                                             */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_default_tci - Default TCI                                             */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_default_tci ( uint8_t xi_table_index ,
+                                                   uint8_t * const xo_default_tci ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_enable_dscp_to_tci_table                                    */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Enable DSCP to TCI table                                     */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function enables/disables a DSCP to TCI table. There are 2 such     */
+/*   tables. Each class is configured with one of these tables. Before        */
+/*   enabling a table, it should be configured by Set DSCP to TCI table API   */
+/*   and Set default TCI API.                                                 */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_table_index - Table index                                             */
+/*                                                                            */
+/*   xi_enable - Enable                                                       */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_enable_dscp_to_tci_table ( uint8_t xi_table_index ,
+                                                            int32_t xi_enable ) ;
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_get_dscp_to_tci_table_enable_status                         */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Get DSCP to TCI table enable status                          */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function gets the enable status of a DSCP to TCI table. There are 2 */
+/*   such tables.                                                             */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_table_index - Table index                                             */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   xo_enable - Enable                                                       */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                        */
+/*     DRV_IH_NO_ERROR - No error                                       */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                       */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_get_dscp_to_tci_table_enable_status ( uint8_t xi_table_index ,
+                                                                       int32_t * const xo_enable ) ;
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   fi_bl_drv_ih_configure_parser_core_cfg_eng_3rd_tag_detection             */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   IH Driver - Configure Parser ENG register                                */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function configures the ENG register (bits 8-13 are for triple      */
+/*   tag detection)                                                           */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   xi_enable - ENG register bit value                                       */
+/*                                                                            */
+/*   xi_tpid_index - ENG register internal bit index                          */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*   DRV_IH_ERROR - Return code                                               */
+/*     DRV_IH_NO_ERROR - No error                                             */
+/*     DRV_IH_ERROR_INVALID_INDEX - Invalid index                             */
+/*                                                                            */
+/******************************************************************************/
+DRV_IH_ERROR fi_bl_drv_ih_configure_parser_core_cfg_eng_3rd_tag_detection ( uint32_t xi_enable,
+		uint8_t xi_tpid_index );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_drv_sbpm.c b/arch/arm/mach-bcmbca/rdp/rdp_drv_sbpm.c
new file mode 100755
index 0000000000..07180162ce
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_drv_sbpm.c
@@ -0,0 +1,720 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the implementation of the Lilac BPM driver              */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+
+
+#include "packing.h"
+#include "rdp_subsystem_common.h"
+#include "rdp_drv_sbpm.h"
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Default values definitions                                                 */
+/*                                                                            */
+/******************************************************************************/
+
+#define  CS_DRV_SBPM_MAX_NUMBER_OF_BUFFERS        ( 0x3FF )
+#define  CS_DRV_SBPM_THRESHOLD_MASK               ( 0x3FF )
+#define  CS_DRV_SBPM_NULL_VALUE                   ( 0x3FF )
+#define  CS_DRV_SBPM_UG_ALIGNMENT                 ( 4 )
+#define  CS_DRV_SBPM_NUMBER_OF_TRIALS_ON_REQUEST  ( 10 )
+#define  CS_DRV_SBPM_IIR_LOW_PART_MASK            ( 0x1ff )
+#define  CS_DRV_SBPM_IIR_HIGH_PART_MASK           ( 0xffe00 )
+#define  CS_DRV_SBPM_IIR_SHIFT                    ( 22 )
+#define  CS_DRV_SBPM_MAX_MULTICAST_VALUE          ( 7 )
+#define  CS_DRV_SBPM_SBPM_EXCL_MEM_GAP            ( SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_ADDRESS - SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_ADDRESS )
+#define  CS_DRV_SBPM_SEARCH_DEPTH                 ( 0x2b )
+
+/* Low */
+#define CS_LOW      ( 0 )
+/* High */
+#define CS_HIGH     ( 1  )
+
+/******************************************************************************/
+/*                                                                            */
+/* Macros definitions                                                         */
+/*                                                                            */
+/******************************************************************************/
+
+/* gets bit #i from a given number */
+#define MS_DRV_SBPM_GET_BIT_I( number , i )   ( ( ( 1 << i ) & ( number ) ) >> i )
+
+/******************************************************************************/
+/*                                                                            */
+/* static function declaration                                                */
+/*                                                                            */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Init & cleanup module, license                                             */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/* API functions implementations                                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_init                                                   */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM driver - BPM initialize                                                   */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function initialize and sets general configuration of the SBPM block.  */
+/* SBPM module initialization is made once in the system lifetime              */
+/*                                                                             */
+/* This API performs the following:                                            */
+/*  1.    Disable all SBPM source ports.                                         */
+/*  2.    Builds the free linked list using the HW accelerator.                  */
+/*  3.    Sets SBPM configuration:                                               */
+/*      a.    Global threshold.                                                  */
+/*      b.    User group configuration (threshold, hysteresis, exclusive         */
+/*          threshold/ hysteresis).                                            */
+/*      c.    Sets route address of each source port.                            */
+/*      d.    Source port to user group mapping.                                 */
+/*                                                                             */
+/* Input:                                                                        */
+/*   xi_base_address - The start address of the BN list                        */
+/*   xi_list_size  - The number of buffers in the list                         */
+/*   xi_global_configuration - global threshold and hysteresis (struct)        */
+/*   xi_user_group_configuration  - user groups threshold and hysteresis (struct)      */
+/*   xi_replay_address - runner replay address                                  */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*       DRV_SBPM_ERROR_NO_ERROR - no error                            */
+/*     DRV_SBPM_ERROR_BUFFER_NUMBER_EXCEEDS_MAXIMUM_VALUE -        */
+/*         the amount of buffers exceeds the maximum value                     */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_init ( uint16_t xi_base_address ,
+                                            uint16_t xi_list_size,
+                                            uint16_t xi_replay_address,
+                                            const DRV_SBPM_GLOBAL_CONFIGURATION    * xi_global_configuration,
+                                            const DRV_SBPM_USER_GROUPS_THRESHOLDS  * xi_user_group_configuration)
+
+{
+    SBPM_BLOCK_REGS_SBPM_SP_EN sbpm_sp_enable;
+    SBPM_BLOCK_REGS_INIT_FREE_LIST  sbpm_init;
+#ifndef __UBOOT__
+    DRV_SBPM_ISR     default_interrupts_mask;
+#endif
+    DRV_SBPM_ERROR   error;
+    SBPM_BLOCK_REGS_RADDR_0   raddr0;
+    SBPM_BLOCK_REGS_RADDR_1   raddr1;
+    SBPM_BLOCK_REGS_RADDR_2   raddr2;
+    SBPM_BLOCK_REGS_RADDR_3   raddr3;
+    uint8_t                     ug_index;
+    DRV_SBPM_ERROR_HANDLING_PARAMETERS error_handling_params ;
+    DRV_SBPM_RUNNER_MSG_CTRL_PARAMS runner_msg_ctrl_params ;
+    
+
+    /*Validate parameters*/
+    if ( xi_base_address + xi_list_size > CS_DRV_SBPM_MAX_NUMBER_OF_BUFFERS )
+    {
+        return ( DRV_SBPM_ERROR_BUFFER_NUMBER_EXCEEDS_MAXIMUM_VALUE );
+    }
+
+
+    /*disable all SBPM source ports*/
+    SBPM_BLOCK_REGS_SBPM_SP_EN_READ( sbpm_sp_enable ) ;
+    sbpm_sp_enable.rnra_sp_en = DRV_SBPM_DISABLE;
+    sbpm_sp_enable.rnrb_sp_en = DRV_SBPM_DISABLE;
+    sbpm_sp_enable.gpon_sp_en = DRV_SBPM_DISABLE;
+    sbpm_sp_enable.eth0_sp_en = DRV_SBPM_DISABLE;
+    sbpm_sp_enable.eth1_sp_en = DRV_SBPM_DISABLE;
+    sbpm_sp_enable.eth2_sp_en = DRV_SBPM_DISABLE;
+    sbpm_sp_enable.eth3_sp_en = DRV_SBPM_DISABLE;
+    sbpm_sp_enable.eth4_sp_en = DRV_SBPM_DISABLE;
+    SBPM_BLOCK_REGS_SBPM_SP_EN_WRITE( sbpm_sp_enable ) ;
+
+
+    /* Write to register init_free_list - Builds the free linked list using the HW accelerator */
+    SBPM_BLOCK_REGS_INIT_FREE_LIST_READ(sbpm_init);
+
+    sbpm_init.init_num_bn = xi_list_size;
+    sbpm_init.init_head_bn_addr = xi_base_address;
+    sbpm_init.bsy = SBPM_BLOCK_REGS_INIT_FREE_LIST_BSY_NO_REQUEST_VALUE;
+    sbpm_init.rdy= SBPM_BLOCK_REGS_INIT_FREE_LIST_RDY_DEFAULT_VALUE;
+    sbpm_init.init_en = DRV_SBPM_ENABLE;
+
+    SBPM_BLOCK_REGS_INIT_FREE_LIST_WRITE(sbpm_init);
+
+    /* Set BPM global configuration  */
+    error = fi_bl_drv_sbpm_set_global_threshold ( xi_global_configuration->threshold , xi_global_configuration->hysteresis );
+
+    /* Set User Group [0-7] threshold configuration*/
+    for ( ug_index = 0 ; ug_index < DRV_SBPM_NUMBER_OF_USER_GROUPS  ; ug_index++  )
+    {
+            error = fi_bl_drv_sbpm_set_user_group_thresholds ( ug_index, &xi_user_group_configuration->ug_arr[ug_index] );
+            if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+            {
+                return ( error );
+            }
+    }
+
+    /*     Set route address of each source port*/
+    SBPM_BLOCK_REGS_RADDR_0_READ (raddr0 );
+    raddr0.eth0_tx_raddr = SBPM_BLOCK_REGS_RADDR_0_ETH0_TX_RADDR_ETH0_TX_RADDR_VALUE;
+    raddr0.eth0_rx_raddr = SBPM_BLOCK_REGS_RADDR_0_ETH0_RX_RADDR_ETH0_RX_RADDR_VALUE;
+    raddr0.eth1_tx_raddr = SBPM_BLOCK_REGS_RADDR_0_ETH1_TX_RADDR_ETH1_TX_RADDR_VALUE ;
+    raddr0.eth1_rx_raddr = SBPM_BLOCK_REGS_RADDR_0_ETH1_RX_RADDR_ETH1_RX_RADDR_VALUE ;
+    SBPM_BLOCK_REGS_RADDR_0_WRITE( raddr0 );
+
+    SBPM_BLOCK_REGS_RADDR_1_READ (raddr1 );
+    raddr1.eth2_tx_raddr = SBPM_BLOCK_REGS_RADDR_1_ETH2_TX_RADDR_ETH2_TX_RADDR_VALUE ;
+    raddr1.eth2_rx_raddr = SBPM_BLOCK_REGS_RADDR_1_ETH2_RX_RADDR_ETH2_RX_RADDR_VALUE ;
+    raddr1.eth3_tx_raddr = SBPM_BLOCK_REGS_RADDR_1_ETH3_TX_RADDR_ETH3_TX_RADDR_VALUE;
+    raddr1.eth3_rx_raddr = SBPM_BLOCK_REGS_RADDR_1_ETH3_RX_RADDR_ETH3_RX_ADDR_VALUE;
+    SBPM_BLOCK_REGS_RADDR_1_WRITE( raddr1 );
+
+    SBPM_BLOCK_REGS_RADDR_2_READ (raddr2 );
+    raddr2.eth4_tx_raddr = SBPM_BLOCK_REGS_RADDR_2_ETH4_TX_RADDR_ETH4_TX_RADDR_VALUE ;
+    raddr2.eth4_rx_raddr = SBPM_BLOCK_REGS_RADDR_2_ETH4_RX_RADDR_ETH4_RX_ADDR_VALUE ;
+    raddr2.gpon_tx_raddr = SBPM_BLOCK_REGS_RADDR_2_GPON_TX_RADDR_GPON_TX_RADDR_VALUE;
+    raddr2.gpon_rx_raddr = SBPM_BLOCK_REGS_RADDR_2_GPON_RX_RADDR_GPON_RX_RADDR_VALUE;
+    SBPM_BLOCK_REGS_RADDR_2_WRITE( raddr2 );
+
+    SBPM_BLOCK_REGS_RADDR_3_READ (raddr3 );
+    raddr3.mipsd_raddr = SBPM_BLOCK_REGS_RADDR_3_MIPSD_RADDR_MIPSD_RADDR_VALUE ;
+    raddr3.rnrb_raddr = SBPM_BLOCK_REGS_RADDR_3_RNRB_RADDR_RNRB_RADDR_VALUE ;
+    raddr3.rnra_raddr = SBPM_BLOCK_REGS_RADDR_3_RNRA_RADDR_RNRA_RADDR_VALUE;
+    SBPM_BLOCK_REGS_RADDR_3_WRITE( raddr3 );
+
+    /* Each Source Port is mapped to specified UG. */
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_EMAC0 , DRV_SBPM_USER_GROUP_0 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_EMAC1 , DRV_SBPM_USER_GROUP_1 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_EMAC2 , DRV_SBPM_USER_GROUP_2 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_EMAC3 , DRV_SBPM_USER_GROUP_3 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_EMAC4 , DRV_SBPM_USER_GROUP_4 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_USB0 , DRV_SBPM_USER_GROUP_4 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_USB1 , DRV_SBPM_USER_GROUP_4 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_PCI0 , DRV_SBPM_USER_GROUP_4 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_PCI1 , DRV_SBPM_USER_GROUP_4 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_GPON , DRV_SBPM_USER_GROUP_5 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_RNR_A , DRV_SBPM_USER_GROUP_6 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_RNR_B , DRV_SBPM_USER_GROUP_6 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_MIPS_C , DRV_SBPM_USER_GROUP_7 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    error = fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_MIPS_D , DRV_SBPM_USER_GROUP_7 );
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    /*Enable Interrupts in interrupt enablae register*/
+#ifndef __UBOOT__
+    default_interrupts_mask.bac_underrun = DRV_SBPM_ENABLE;
+    default_interrupts_mask.multicast_counter_overflow = DRV_SBPM_ENABLE;
+    default_interrupts_mask.check_last_error = DRV_SBPM_ENABLE;
+    default_interrupts_mask.max_search_error = DRV_SBPM_ENABLE;
+    error = fi_bl_drv_sbpm_set_interrupt_enable_register ( &default_interrupts_mask);
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+#endif
+    /* Set Error Handling Parameters */
+    error_handling_params.search_deapth = CS_DRV_SBPM_SEARCH_DEPTH ;
+    error_handling_params.max_search_enable = DRV_SBPM_DISABLE ;
+    error_handling_params.check_last_enable = DRV_SBPM_ENABLE ;
+    error_handling_params.freeze_counters = DRV_SBPM_DISABLE ;
+
+    error = fi_bl_drv_sbpm_set_error_handling_parameters ( & error_handling_params ) ;
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    /* Set Runner Message Control parameters */
+    error = fi_bl_drv_sbpm_get_runner_msg_ctrl ( & runner_msg_ctrl_params ) ;
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    runner_msg_ctrl_params.runner_reply_target_address = xi_replay_address >> 3 ;
+
+    error = fi_bl_drv_sbpm_set_runner_msg_ctrl ( & runner_msg_ctrl_params ) ;
+    if ( error !=  DRV_SBPM_ERROR_NO_ERROR )
+    {
+        return ( error );
+    }
+
+    return ( DRV_SBPM_ERROR_NO_ERROR );
+
+}
+EXPORT_SYMBOL ( fi_bl_drv_sbpm_init );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_sp_enable                                                    */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Source Ports Enable                                            */
+/*                                                                             */
+/* Abstract:                                                                   */
+/* Source Ports Enable                                                         */
+/*                                                                             */
+/* Registers:                                                                  */
+/* BPM_SP_EN                                                                   */
+/*                                                                             */
+/* Input:                                                                      */
+/*                                                                             */
+/*    xi_sp_enable - source port enable of each port.                          */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                        */
+/*     DRV_SBPM_ERROR_NO_ERROR - no error                                */
+/*   DRV_SBPM_ERROR_INVALID_SOURCE_PORT - invalid source port            */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_sp_enable ( const DRV_SBPM_SP_ENABLE * xi_sp_enable )
+{
+    SBPM_BLOCK_REGS_SBPM_SP_EN sbpm_sp_enable ;
+
+    SBPM_BLOCK_REGS_SBPM_SP_EN_READ( sbpm_sp_enable ) ;
+
+    sbpm_sp_enable.rnra_sp_en = xi_sp_enable->rnra_sp_enable ;
+    sbpm_sp_enable.rnrb_sp_en = xi_sp_enable->rnrb_sp_enable ;
+    sbpm_sp_enable.eth0_sp_en = xi_sp_enable->eth0_sp_enable ;
+    sbpm_sp_enable.eth1_sp_en = xi_sp_enable->eth1_sp_enable ;
+    sbpm_sp_enable.eth2_sp_en = xi_sp_enable->eth2_sp_enable ;
+    sbpm_sp_enable.eth3_sp_en = xi_sp_enable->eth3_sp_enable ;
+    sbpm_sp_enable.eth4_sp_en = xi_sp_enable->eth4_sp_enable ;
+    sbpm_sp_enable.gpon_sp_en = xi_sp_enable->gpon_or_eth5_sp_enable ;
+
+    SBPM_BLOCK_REGS_SBPM_SP_EN_WRITE( sbpm_sp_enable) ;
+
+    return ( DRV_SBPM_ERROR_NO_ERROR ) ;
+}
+EXPORT_SYMBOL ( fi_bl_drv_sbpm_sp_enable ) ;
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_set_global_threshold                                   */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM driver - Set SBPM Global threshold                                     */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function sets the global Threshold for Allocated Buffers.              */
+/*                                                                             */
+/* Input:                                                                       */
+/*                                                                             */
+/*   xi_global_threshold - Global Threshold for Allocated Buffers              */
+/*   xi_global_hystersis - how many BNs need to free in order to get out from  */
+/*                         global NACK state                                   */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*     DRV_SBPM_ERROR_NO_ERROR - no error                            */
+/*                                                                             */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_set_global_threshold ( uint16_t xi_global_threshold,
+                                                                        uint16_t xi_global_hysteresis )
+{
+    SBPM_BLOCK_REGS_SBPM_GL_TRSH global_configuration;
+
+    SBPM_BLOCK_REGS_SBPM_GL_TRSH_READ(global_configuration);
+
+    global_configuration.gl_bah = ( xi_global_hysteresis & CS_DRV_SBPM_THRESHOLD_MASK );
+    global_configuration.gl_bat = ( xi_global_threshold  & CS_DRV_SBPM_THRESHOLD_MASK );
+
+    SBPM_BLOCK_REGS_SBPM_GL_TRSH_WRITE(global_configuration);
+
+    return ( DRV_SBPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_sbpm_set_global_threshold );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_set_user_group_thresholds                              */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM driver - Set SBPM User Group threshold configuration                   */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function sets the threshold and hysteresis for a specific user group.  */
+/*                                                                             */
+/* Input:                                                                       */
+/*    xi_user_group - user group                                                            */
+/*  xi_configuration - thresholds configuration for the user group (struct)    */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*     DRV_SBPM_ERROR_NO_ERROR - no error                            */
+/*   DRV_SBPM_ERROR_INVALID_USER_GROUP -user group id out of range */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_set_user_group_thresholds (DRV_SBPM_USER_GROUP xi_user_group,
+                                                                            const DRV_SBPM_USER_GROUP_CONFIGURATION * xi_configuration)
+{
+    DRV_SBPM_UG_THRESHOLD ug_configuration;
+    DRV_SBPM_UG_THRESHOLD ug_exclusive_configuration;
+    uint32_t ug_start_address;
+    uint32_t ug_exclusive_start_address;
+
+    if ( ! ME_DRV_SBPM_USER_GROUP_IN_RANGE ( xi_user_group ) )
+    {
+        return ( DRV_SBPM_ERROR_INVALID_USER_GROUP );
+    }
+
+    ug_start_address = ( uint32_t ) ( SBPM_BLOCK_REGS_SBPM_UG0_TRSH_ADDRESS + CS_DRV_SBPM_UG_ALIGNMENT * ( uint32_t ) xi_user_group );
+
+    if ( xi_user_group == DRV_SBPM_USER_GROUP_0 )
+    {
+        ug_exclusive_start_address = ( uint32_t )  SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_ADDRESS;
+    }
+    else
+    {
+        ug_exclusive_start_address = ( uint32_t ) ( SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_ADDRESS + CS_DRV_SBPM_SBPM_EXCL_MEM_GAP + CS_DRV_SBPM_UG_ALIGNMENT * ( uint32_t ) ( xi_user_group - 1 ) );
+    }
+
+    READ_32( ug_start_address, ug_configuration);
+
+    ug_configuration.ug_hysteresis = ( uint32_t ) ( xi_configuration->hysteresis & CS_DRV_SBPM_THRESHOLD_MASK );
+    ug_configuration.ug_threshold =  ( uint32_t ) ( xi_configuration->threshold & CS_DRV_SBPM_THRESHOLD_MASK );
+
+    WRITE_32( ug_start_address, ug_configuration);
+
+
+    READ_32( ug_exclusive_start_address , ug_exclusive_configuration);
+
+    ug_exclusive_configuration.ug_hysteresis = ( uint32_t ) ( xi_configuration->exclusive_hysteresis & CS_DRV_SBPM_THRESHOLD_MASK );
+    ug_exclusive_configuration.ug_threshold =  ( uint32_t ) ( xi_configuration->exclusive_threshold  & CS_DRV_SBPM_THRESHOLD_MASK );
+
+    WRITE_32( ug_exclusive_start_address , ug_exclusive_configuration);
+
+    return ( DRV_SBPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_sbpm_set_user_group_thresholds );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_set_user_group_mapping                                 */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM driver - Set User Group Mapping                                        */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function maps a User group for a specific Source port                  */
+/*                                                                             */
+/* Input:                                                                         */
+/*    xi_source_port - One of SBPM source ports                                   */
+/*  xi_user_group  - one of SBPM User group 0-7                                */
+/*                                                                             */
+/* Output:  error code                                                         */
+/*     DRV_SBPM_ERROR_NO_ERROR - no error                            */
+/*     DRV_SBPM_ERROR_INVALID_SOURCE_PORT - invalid source port      */
+/*   DRV_SBPM_ERROR_INVALID_USER_GROUP -user group id out of range */
+/*                                                                             */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_USR  xi_source_port,
+                                                                          DRV_SBPM_USER_GROUP xi_user_group )
+{
+    SBPM_BLOCK_REGS_SBPM_UG_MAP_0  sbpm_ug_mapping_r0;
+    SBPM_BLOCK_REGS_UG_MAP_REG_1  sbpm_ug_mapping_r1;
+
+    SBPM_BLOCK_REGS_SBPM_UG_MAP_0_READ(sbpm_ug_mapping_r0);
+    SBPM_BLOCK_REGS_UG_MAP_REG_1_READ (sbpm_ug_mapping_r1);
+
+    if ( ! ME_DRV_SBPM_USER_GROUP_IN_RANGE ( xi_user_group ) )
+    {
+        return ( DRV_SBPM_ERROR_INVALID_USER_GROUP );
+    }
+
+    switch ( xi_source_port )
+    {
+    case DRV_SBPM_SP_MIPS_C:
+        sbpm_ug_mapping_r0.cpu = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_EMAC0:
+        sbpm_ug_mapping_r0.emac0 = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_EMAC1:
+        sbpm_ug_mapping_r0.emac1 = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_EMAC2:
+        sbpm_ug_mapping_r0.emac2 = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_EMAC3:
+        sbpm_ug_mapping_r0.emac3 = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_EMAC4:
+        sbpm_ug_mapping_r1.emac4= xi_user_group;
+        break ;
+    case DRV_SBPM_SP_GPON:
+        sbpm_ug_mapping_r0.gpon = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_RNR_A:
+        sbpm_ug_mapping_r0.rnra = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_RNR_B:
+        sbpm_ug_mapping_r0.rnrb = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_USB0:
+        sbpm_ug_mapping_r1.usb0 = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_USB1:
+        sbpm_ug_mapping_r1.usb1= xi_user_group;
+        break ;
+    case DRV_SBPM_SP_PCI0:
+        sbpm_ug_mapping_r1.pcie0 = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_PCI1:
+        sbpm_ug_mapping_r1.pcie1 = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_MIPS_D:
+        sbpm_ug_mapping_r1.mipsd = xi_user_group;
+        break ;
+    case DRV_SBPM_SP_SPARE_0:
+        sbpm_ug_mapping_r1.spare0 = xi_user_group;
+        break ;
+   case DRV_SBPM_SP_SPARE_1:
+        sbpm_ug_mapping_r1.spare1 = xi_user_group;
+        break ;
+    default:
+        return ( DRV_SBPM_ERROR_INVALID_SOURCE_PORT );
+    }
+
+    SBPM_BLOCK_REGS_SBPM_UG_MAP_0_WRITE (sbpm_ug_mapping_r0);
+    SBPM_BLOCK_REGS_UG_MAP_REG_1_WRITE (sbpm_ug_mapping_r1);
+
+   return ( DRV_SBPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_sbpm_set_user_group_mapping );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_set_error_handling_parameters                          */
+/*                                                                             */
+/* Title:                                                                      */
+/*                                                                             */
+/*  SBPM driver - Set Error Handling Parameters                                   */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/*                                                                             */
+/* This function set the parameters and thresholds used for error handling:    */
+/*   maximum search threshold in case of free buffer without context, enabling */
+/*   max search, and enabling checking last BN.                                */
+/*                                                                             */
+/* Registers:                                                                  */
+/*                                                                             */
+/*  SBPM_IER                                                                   */
+/*                                                                             */
+/* Input:                                                                         */
+/*                                                                             */
+/*    xi_sbpm_error_handling_parameters - SBPM Error handling parameters (struct)*/
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*     DRV_SBPM_ERROR_NO_ERROR - no error                            */
+/*                                                                             */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_set_error_handling_parameters ( const DRV_SBPM_ERROR_HANDLING_PARAMETERS * xi_sbpm_error_handling_parameters )
+{
+    SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS error_handling_reg ;
+
+    SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_READ ( error_handling_reg ) ;
+
+    error_handling_reg.search_depth =  xi_sbpm_error_handling_parameters -> search_deapth ;
+    error_handling_reg.max_search_en =  xi_sbpm_error_handling_parameters -> max_search_enable ;
+    error_handling_reg.chck_last_en =  xi_sbpm_error_handling_parameters -> check_last_enable ;
+    error_handling_reg.freeze_in_error =  xi_sbpm_error_handling_parameters -> freeze_counters ;
+
+    SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_WRITE ( error_handling_reg);
+
+    return ( DRV_SBPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_sbpm_set_error_handling_parameters );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_set_runner_msg_ctrl                                    */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM Driver - Set Runner message control                                    */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/*This function sets the runner control parameters which includes enables for  */
+/*wake-up and status messages, select control bit for runner to receive message*/
+/*and task number for wake-up messages to Runners.                             */
+/*                                                                             */
+/* Registers:                                                                  */
+/* SBPM_RNR_MSG_CTRL,SBPM_RNR_RPLY_TA                                          */
+/*                                                                             */
+/* Input:                                                                       */
+/*                                                                             */
+/*  xi_runner_messsage_control_parameters - struct                             */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*     DRV_SBPM_ERROR_NO_ERROR - no error                            */
+/*                                                                             */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_set_runner_msg_ctrl(DRV_SBPM_RUNNER_MSG_CTRL_PARAMS  * xi_runner_messsage_control_parameters)
+{
+    SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL runner_message_control;
+    SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA       runner_rply_ta_register;
+
+    SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_READ (runner_message_control);
+
+    runner_message_control.task_num = xi_runner_messsage_control_parameters -> runner_reply_wakeup_task_number;
+    runner_message_control.stat_wkup_en = xi_runner_messsage_control_parameters -> status_wakeup_enable ?
+        DRV_SBPM_ENABLE : DRV_SBPM_DISABLE;
+    runner_message_control.stat_msg_en = xi_runner_messsage_control_parameters -> status_message_enable ?
+        DRV_SBPM_ENABLE : DRV_SBPM_DISABLE;
+    runner_message_control.rnr_num = xi_runner_messsage_control_parameters-> select_runner ?
+        SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_RNR_NUM_RUNNER_B_VALUE :
+        SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_RNR_NUM_RUNNER_A_VALUE ;
+    runner_message_control.rnr_stat_msg_base_addr = xi_runner_messsage_control_parameters -> message_base_address;
+
+    SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_WRITE (runner_message_control);
+
+
+    SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_READ (runner_rply_ta_register);
+
+    runner_rply_ta_register.rnr_reply_msg_base_addr = xi_runner_messsage_control_parameters -> runner_reply_target_address ;
+
+    SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_WRITE (runner_rply_ta_register);
+
+    return ( DRV_SBPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_sbpm_set_runner_msg_ctrl );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_get_runner_msg_ctrl                                    */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM Driver - Get Runner message control                                    */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function returns the runner control parameters which includes enables  */
+/* for wake-up and status messages, select control bit for runner to receive   */
+/* message and task number for wake-up messages to Runners.                    */
+/*                                                                             */
+/* Registers:                                                                  */
+/* SBPM_RNR_MSG_CTRL,SBPM_RNR_RPLY_TA                                          */
+/*                                                                             */
+/* Input:                                                                       */
+/*                                                                             */
+/*  xo_runner_messsage_control_parameters - struct                             */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*     DRV_SBPM_ERROR_NO_ERROR - no error                            */
+/*                                                                             */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_get_runner_msg_ctrl(DRV_SBPM_RUNNER_MSG_CTRL_PARAMS * const xo_runner_messsage_control_parameters)
+{
+    SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL runner_message_control;
+    SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA       runner_rply_ta_register;
+
+    SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_READ (runner_message_control);
+
+    xo_runner_messsage_control_parameters -> runner_reply_wakeup_task_number = runner_message_control.task_num ;
+    xo_runner_messsage_control_parameters -> status_wakeup_enable = runner_message_control.stat_wkup_en ?
+        DRV_SBPM_ENABLE : DRV_SBPM_DISABLE;
+    xo_runner_messsage_control_parameters -> status_message_enable = runner_message_control.stat_msg_en ?
+        DRV_SBPM_ENABLE : DRV_SBPM_DISABLE;
+    xo_runner_messsage_control_parameters-> select_runner = runner_message_control.rnr_num  ?
+        DRV_SBPM_RUNNER_SELECT_RUNNER_B :
+        DRV_SBPM_RUNNER_SELECT_RUNNER_A ;
+    xo_runner_messsage_control_parameters -> message_base_address = runner_message_control.rnr_stat_msg_base_addr ;
+
+    SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_READ (runner_rply_ta_register);
+
+    xo_runner_messsage_control_parameters -> runner_reply_target_address = runner_rply_ta_register.rnr_reply_msg_base_addr  ;
+
+    return ( DRV_SBPM_ERROR_NO_ERROR );
+}
+EXPORT_SYMBOL ( fi_bl_drv_sbpm_get_runner_msg_ctrl );
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_drv_sbpm.h b/arch/arm/mach-bcmbca/rdp/rdp_drv_sbpm.h
new file mode 100755
index 0000000000..8f2f6c3d9f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_drv_sbpm.h
@@ -0,0 +1,583 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/             
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This header file defines all datatypes and functions exported for the      */
+/* Lilac SBPM driver.                                                          */
+/*                                                                            */
+/******************************************************************************/
+
+#ifndef LILAC_DRV_SBPM_H_INCLUDED
+#define LILAC_DRV_SBPM_H_INCLUDED
+
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+#include "rdp_sbpm.h"
+
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Error codes returned by SBPM driver APIs                                    */
+/******************************************************************************/
+typedef enum
+{
+	DRV_SBPM_ERROR_NO_ERROR = 0,
+    DRV_SBPM_ERROR_SBPM_BUSY ,
+    DRV_SBPM_ERROR_NO_FREE_BUFFER,
+    DRV_SBPM_ERROR_INVALID_SOURCE_PORT,
+    DRV_SBPM_ERROR_INVALID_USER_GROUP,
+    DRV_SBPM_ERROR_BUFFER_NUMBER_EXCEEDS_MAXIMUM_VALUE,
+    DRV_SBPM_ERROR_TRYING_TO_CONNECT_TO_NULL_POINTER,
+    DRV_SBPM_ERROR_TRYING_TO_FREE_NULL_POINTER,
+    DRV_SBPM_ERROR_MULTICAST_VALUE_EXCEEDS_MAXIMUM_VALUE
+	
+}DRV_SBPM_ERROR;
+
+
+/******************************************************************************/
+/* BPM source ports                                                           */
+/******************************************************************************/
+typedef enum
+{
+	DRV_SBPM_SP_GPON,
+	DRV_SBPM_SP_EMAC0,
+	DRV_SBPM_SP_EMAC1,
+	DRV_SBPM_SP_EMAC2,
+	DRV_SBPM_SP_EMAC3,
+	DRV_SBPM_SP_EMAC4,
+    DRV_SBPM_SP_MIPS_C,
+    DRV_SBPM_SP_MIPS_D,
+    DRV_SBPM_SP_PCI0,
+    DRV_SBPM_SP_PCI1,
+    DRV_SBPM_SP_USB0,
+    DRV_SBPM_SP_USB1,
+    DRV_SBPM_SP_SPARE_0,
+    DRV_SBPM_SP_SPARE_1,
+    DRV_SBPM_SP_RNR_A,
+    DRV_SBPM_SP_RNR_B,
+    DRV_SBPM_SP_NUMBER_OF_SOURCE_PORTS
+	
+}DRV_SBPM_SP_USR;
+
+
+/******************************************************************************/
+/* BPM User Groups index:                                                     */
+/******************************************************************************/
+typedef enum
+{
+	DRV_SBPM_USER_GROUP_0,
+	DRV_SBPM_USER_GROUP_1,
+    DRV_SBPM_USER_GROUP_2,
+	DRV_SBPM_USER_GROUP_3,
+	DRV_SBPM_USER_GROUP_4,
+    DRV_SBPM_USER_GROUP_5,
+    DRV_SBPM_USER_GROUP_6,
+    DRV_SBPM_USER_GROUP_7,
+    DRV_SBPM_NUMBER_OF_USER_GROUPS
+	
+}DRV_SBPM_USER_GROUP;
+
+#define ME_DRV_SBPM_USER_GROUP_IN_RANGE(v)       ( (v) >= DRV_SBPM_USER_GROUP_0 && (v) < DRV_SBPM_NUMBER_OF_USER_GROUPS )
+
+
+/******************************************************************************/
+/* Boolean                                                                    */
+/******************************************************************************/
+typedef enum
+{
+	DRV_SBPM_DISABLE = 0,
+	DRV_SBPM_ENABLE = 1
+	
+}E_DRV_SBPM_ENABLE;
+
+/******************************************************************************/
+/* Ack state                                                                   */
+/******************************************************************************/
+typedef enum
+{
+	DRV_SBPM_NACK_STATE = 0,
+	DRV_SBPM_ACK_STATE = 1
+	
+}E_DRV_SBPM_ACK_STATE;
+
+/******************************************************************************/
+/* Exclusive state                                                            */
+/******************************************************************************/
+typedef enum
+{
+	DRV_SBPM_NON_EXCLUSIVE_STATE = 0,
+	DRV_SBPM_EXCLUSIVE_STATE = 1
+	
+}E_DRV_SBPM_EXCLUSIVE_STATE;
+
+/******************************************************************************/
+/* Runner selection for receiving status messages                             */
+/******************************************************************************/
+typedef enum
+{
+	DRV_SBPM_RUNNER_SELECT_RUNNER_A = 0,
+	DRV_SBPM_RUNNER_SELECT_RUNNER_B = 1
+	
+}DRV_SBPM_RUNNER_SELECT;
+
+
+/******************************************************************************/
+/* SBPM Global Configuration struct                                           */
+/******************************************************************************/
+typedef struct
+{
+    /* Global hysteresis */
+    uint32_t hysteresis ;
+
+    /* Global threshold */
+    uint32_t threshold  ;
+} 
+DRV_SBPM_GLOBAL_CONFIGURATION ;
+
+
+/******************************************************************************/
+/* BPM User Group mapping struct                                              */
+/******************************************************************************/
+typedef struct
+{
+  	DRV_SBPM_USER_GROUP sp_gpon_mapping;
+	DRV_SBPM_USER_GROUP sp_emac0_mapping;
+	DRV_SBPM_USER_GROUP sp_emac1_mapping;
+	DRV_SBPM_USER_GROUP sp_emac2_mapping;
+	DRV_SBPM_USER_GROUP sp_emac3_mapping;
+	DRV_SBPM_USER_GROUP sp_emac4_mapping;
+    DRV_SBPM_USER_GROUP sp_mips_c_mapping;
+    DRV_SBPM_USER_GROUP sp_mips_d_mapping;
+    DRV_SBPM_USER_GROUP sp_pci0_mapping;
+    DRV_SBPM_USER_GROUP sp_pci1_mapping;
+    DRV_SBPM_USER_GROUP sp_usb0_mapping;
+    DRV_SBPM_USER_GROUP sp_usb1_mapping;
+    DRV_SBPM_USER_GROUP sp_rnr_a_mapping;
+    DRV_SBPM_USER_GROUP sp_rnr_b_mapping;
+} 
+DRV_SBPM_USER_GROUP_MAPPING ;
+
+/******************************************************************************/
+/* SBPM User Group thresholds struct                                           */
+/******************************************************************************/
+typedef struct
+{
+    /* rsv */
+    uint32_t rsv2          : 6 ;
+    /* UG hysteresis */
+    uint32_t ug_hysteresis : 10 ;
+    /* reserved */
+    uint32_t rsv           : 6  ;
+    /*  UG threshold */
+    uint32_t ug_threshold  : 10 ;
+} 
+DRV_SBPM_UG_THRESHOLD ;
+
+/******************************************************************************/
+/* SBPM User Group configuration struct                                           */
+/******************************************************************************/
+typedef struct
+{
+    /*  threshold */
+    uint32_t threshold  ;
+
+    /*  hysteresis */
+    uint32_t hysteresis ;
+
+    /*  Exclusive threshold */
+    uint32_t exclusive_threshold  ;
+
+    /*  Exclusive hysteresis */
+    uint32_t exclusive_hysteresis ;
+
+} 
+DRV_SBPM_USER_GROUP_CONFIGURATION ;
+
+/******************************************************************************/
+/* SBPM User Group thresholds struct  - contains array of 8 user groups        */
+/******************************************************************************/
+typedef struct
+{
+    DRV_SBPM_USER_GROUP_CONFIGURATION ug_arr[ DRV_SBPM_NUMBER_OF_USER_GROUPS ]   ;
+} 
+DRV_SBPM_USER_GROUPS_THRESHOLDS ;
+
+/******************************************************************************/
+/* Source port enable struct                                                  */
+/******************************************************************************/
+typedef struct
+{
+    int32_t rnra_sp_enable ;
+
+    int32_t rnrb_sp_enable ;
+
+    int32_t eth0_sp_enable ;
+
+    int32_t eth1_sp_enable ;
+
+    int32_t eth2_sp_enable ;
+
+    int32_t eth3_sp_enable ;
+
+    int32_t eth4_sp_enable ;
+
+    int32_t gpon_or_eth5_sp_enable ;
+} 
+DRV_SBPM_SP_ENABLE ;
+
+/*******************************************************************************/
+/*  Runner message control parameters - struct                                 */
+/*******************************************************************************/
+typedef struct
+{
+
+    /*Task number for runner used in SBPM Status Message Wake-Up */
+    uint16_t  runner_reply_wakeup_task_number ;
+
+    /* Enable/Disable wake-up message after each reply on Alloc request from Runner */
+    E_DRV_SBPM_ENABLE status_wakeup_enable ;
+
+    /* Enable/Disable  wake-up message after each   transition state of any peripheral */
+	E_DRV_SBPM_ENABLE status_message_enable;
+
+    /*select runner for receiving status messages: Runner A or B*/
+	DRV_SBPM_RUNNER_SELECT select_runner;
+
+    /*status message base address */
+    uint16_t  message_base_address; 
+
+    /*Target address for both Runners*/
+    uint16_t  runner_reply_target_address; 
+
+} 
+DRV_SBPM_RUNNER_MSG_CTRL_PARAMS ;
+
+/*******************************************************************************/
+/*  wakeup reply set parameters - struct                                       */
+/*******************************************************************************/
+typedef struct
+{
+    /*Task number for Wake-Up as resultof reply */
+    uint16_t  reply_wakeup_task_number ;
+
+    /*Enable/Disable wake-up message on alloc reply message */
+    E_DRV_SBPM_ENABLE alloc_reply_wakeup_enable;
+
+    /*Enable/Disable wake-up message on bn connect reply message */
+    E_DRV_SBPM_ENABLE connect_reply_wakeup_enable;
+
+    /*Enable/Disable wake-up message on get_next reply message */
+    E_DRV_SBPM_ENABLE get_next_reply_wakeup_enable;
+
+    /*Enable/Disable wake-up message on multicast update reply message */
+    E_DRV_SBPM_ENABLE mcnt_reply_wakeup_enable;
+} 
+DRV_SBPM_WAKEUP_REPLY_SET_PARAMS ;
+
+/*******************************************************************************/
+/*  MIPS D message control parameters - struct                                 */
+/*******************************************************************************/
+typedef struct
+{
+    /*Task number for Wake-Up as resultof Reply on Alloc request*/
+    DRV_SBPM_WAKEUP_REPLY_SET_PARAMS  mips_d_wakeup_reply_set ;
+
+    /*Target address for MIPS-D*/
+    uint16_t  mips_d_reply_target_address ;
+
+} 
+DRV_SBPM_MIPS_D_MSG_CTRL_PARAMS ;
+
+/******************************************************************************/
+/* SBPM User Group status struct                                               */
+/******************************************************************************/
+typedef struct
+{
+    /*User group status - ack/nack*/
+    E_DRV_SBPM_ACK_STATE ug_status ;
+
+    /*User group exclusive status - non-exclusive/exclusive*/
+    E_DRV_SBPM_EXCLUSIVE_STATE ug_exclusive_status ;
+} 
+DRV_SBPM_USER_GROUP_STATUS ;
+
+/******************************************************************************/
+/* SBPM Interrupts status struct                                               */
+/******************************************************************************/
+typedef struct
+{
+    E_DRV_SBPM_ENABLE bac_underrun ;
+	E_DRV_SBPM_ENABLE multicast_counter_overflow;
+    E_DRV_SBPM_ENABLE check_last_error;
+    E_DRV_SBPM_ENABLE max_search_error;
+} 
+DRV_SBPM_ISR ;
+
+/******************************************************************************/
+/* SBPM Interrupt information struct                                           */
+/******************************************************************************/
+typedef struct
+{
+    uint16_t cmd_sa ;
+	uint16_t cmd_type ;
+    uint32_t cmd_data [2] ; 
+} 
+DRV_SBPM_IIR ;
+
+/******************************************************************************/
+/* SBPM Error Handling parameters struct                                      */
+/******************************************************************************/
+typedef struct
+{
+    uint16_t search_deapth ;
+	E_DRV_SBPM_ENABLE max_search_enable ;
+    E_DRV_SBPM_ENABLE check_last_enable  ; 
+    E_DRV_SBPM_ENABLE freeze_counters;
+} 
+DRV_SBPM_ERROR_HANDLING_PARAMETERS ;
+
+/*******************************************************************************/
+/*                                                                             */
+/* Functions prototypes                                                        */
+/*                                                                             */
+/*******************************************************************************/
+
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_init					                               */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM driver - BPM initialize    	                                           */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function initialize and sets general configuration of the SBPM block.  */
+/* SBPM module initialization is made once in the system lifetime              */
+/*                                                                             */
+/* This API performs the following:                                            */
+/*  1.	Disable all SBPM source ports.                                         */
+/*  2.	Builds the free linked list using the HW accelerator.                  */
+/*  3.	Sets SBPM configuration:                                               */
+/*      a.	Global threshold.                                                  */
+/*      b.	User group configuration (threshold, hysteresis, exclusive         */
+/*          threshold/ hysteresis).                                            */
+/*      c.	Sets route address of each source port.                            */
+/*      d.	Source port to user group mapping.                                 */
+/*                                                                             */
+/* Input: 																	   */
+/*   xi_base_address - The start address of the BN list                        */
+/*   xi_list_size  - The number of buffers in the list                         */
+/*   xi_global_configuration - global threshold and hysteresis (struct)        */
+/*   xi_user_group_configuration  - user groups threshold and hysteresis (struct)      */
+/*   xi_replay_address - runner replay address                                  */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*	   DRV_SBPM_ERROR_NO_ERROR - no error 					       */	
+/*     DRV_SBPM_ERROR_BUFFER_NUMBER_EXCEEDS_MAXIMUM_VALUE -        */
+/*         the amount of buffers exceeds the maximum value                     */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_init(uint16_t xi_base_address ,
+                                          uint16_t xi_list_size,
+                                          uint16_t xi_replay_address,
+                                          const DRV_SBPM_GLOBAL_CONFIGURATION    * xi_global_configuration,
+                                          const DRV_SBPM_USER_GROUPS_THRESHOLDS  * xi_user_group_configuration ) ;
+
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_sp_enable                                                    */
+/*                                                                             */
+/* Title:                                                                      */
+/* BPM driver - Source Ports Enable                                            */
+/*                                                                             */
+/* Abstract:                                                                   */
+/* Source Ports Enable                                                         */
+/*                                                                             */
+/* Registers:                                                                  */
+/* BPM_SP_EN                                                                   */
+/*                                                                             */
+/* Input:                                                                      */
+/*                                                                             */
+/*    xi_sp_enable - source port enable of each port.                          */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                        */
+/*     DRV_SBPM_ERROR_NO_ERROR - no error                                */
+/*   DRV_SBPM_ERROR_INVALID_SOURCE_PORT - invalid source port            */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_sp_enable ( const DRV_SBPM_SP_ENABLE * xi_sp_enable ) ;
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_set_global_threshold                                   */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM driver - Set SBPM Global threshold                                     */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function sets the global Threshold for Allocated Buffers.              */
+/*                                                                             */
+/* Input:																	   */
+/*                                                                             */
+/*   xi_global_threshold - Global Threshold for Allocated Buffers              */
+/*   xi_global_hystersis - how many BNs need to free in order to get out from  */
+/*                         global NACK state                                   */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*	 DRV_SBPM_ERROR_NO_ERROR - no error 					       */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_set_global_threshold ( uint16_t xi_global_threshold,
+                                                                        uint16_t xi_global_hysteresis );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_set_user_group_thresholds                              */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM driver - Set SBPM User Group threshold configuration                   */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function sets the threshold and hysteresis for a specific user group.  */
+/*                                                                             */
+/* Input:																	   */
+/*	xi_user_group - user group 														   */			
+/*  xi_configuration - thresholds configuration for the user group (struct)    */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*	 DRV_SBPM_ERROR_NO_ERROR - no error 					       */	
+/*   DRV_SBPM_ERROR_INVALID_USER_GROUP -user group id out of range */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_set_user_group_thresholds (DRV_SBPM_USER_GROUP xi_user_group, 
+                                                                            const DRV_SBPM_USER_GROUP_CONFIGURATION * xi_configuration);
+
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_set_user_group_mapping                                 */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM driver - Set User Group Mapping                                        */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function maps a User group for a specific Source port                  */
+/*                                                                             */
+/* Input:                                              			               */
+/*	xi_source_port - One of SBPM source ports		                           */
+/*  xi_user_group  - one of SBPM User group 0-7                                */
+/*                                                                             */
+/* Output:  error code                                                         */
+/*	 DRV_SBPM_ERROR_NO_ERROR - no error 					       */	
+/*	 DRV_SBPM_ERROR_INVALID_SOURCE_PORT - invalid source port      */
+/*   DRV_SBPM_ERROR_INVALID_USER_GROUP -user group id out of range */
+/*                                                                             */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_set_user_group_mapping ( DRV_SBPM_SP_USR  xi_source_port,
+                                                                          DRV_SBPM_USER_GROUP xi_user_group );
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_set_error_handling_parameters                          */
+/*                                                                             */
+/* Title:                                                                      */
+/*                                                                             */
+/*  SBPM driver - Set Error Handling Parameters	                               */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/*                                                                             */
+/* This function set the parameters and thresholds used for error handling:    */
+/*   maximum search threshold in case of free buffer without context, enabling */
+/*   max search, and enabling checking last BN.                                */
+/*                                                                             */
+/* Registers:                                                                  */
+/*                                                                             */
+/*  SBPM_IER                                                                   */
+/*                                                                             */
+/* Input:                                              			               */
+/*                                                                             */
+/*	xi_sbpm_error_handling_parameters - SBPM Error handling parameters (struct)*/	
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*	 DRV_SBPM_ERROR_NO_ERROR - no error 					       */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_set_error_handling_parameters ( const DRV_SBPM_ERROR_HANDLING_PARAMETERS * xi_sbpm_error_handling_parameters );
+
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_set_runner_msg_ctrl                                    */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM Driver - Set Runner message control                                    */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/*This function sets the runner control parameters which includes enables for  */
+/*wake-up and status messages, select control bit for runner to receive message*/
+/*and task number for wake-up messages to Runners.                             */ 
+/*                                                                             */
+/* Registers:                                                                  */
+/* SBPM_RNR_MSG_CTRL,SBPM_RNR_RPLY_TA                                          */
+/*                                                                             */
+/* Input:																	   */
+/*                                                                             */
+/*  xi_runner_messsage_control_parameters - struct                             */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*	 DRV_SBPM_ERROR_NO_ERROR - no error 					       */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_set_runner_msg_ctrl(DRV_SBPM_RUNNER_MSG_CTRL_PARAMS  * xi_runner_messsage_control_parameters);
+
+
+/*******************************************************************************/
+/*                                                                             */
+/* fi_bl_drv_sbpm_get_runner_msg_ctrl                                    */
+/*                                                                             */
+/* Title:                                                                      */
+/* SBPM Driver - Get Runner message control                                    */
+/*                                                                             */
+/* Abstruct:                                                                   */
+/* This function returns the runner control parameters which includes enables  */
+/* for wake-up and status messages, select control bit for runner to receive   */
+/* message and task number for wake-up messages to Runners.                    */ 
+/*                                                                             */
+/* Registers:                                                                  */
+/* SBPM_RNR_MSG_CTRL,SBPM_RNR_RPLY_TA                                          */
+/*                                                                             */
+/* Input:																	   */
+/*                                                                             */
+/*  xo_runner_messsage_control_parameters - struct                             */
+/*                                                                             */
+/* Output:                                                                     */
+/*   DRV_SBPM_ERROR - error code                                  */
+/*	 DRV_SBPM_ERROR_NO_ERROR - no error 					       */	
+/*                                                                             */
+/*******************************************************************************/
+DRV_SBPM_ERROR fi_bl_drv_sbpm_get_runner_msg_ctrl(DRV_SBPM_RUNNER_MSG_CTRL_PARAMS * const xo_runner_messsage_control_parameters);
+
+#endif
+
+
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_ih.h b/arch/arm/mach-bcmbca/rdp/rdp_ih.h
new file mode 100755
index 0000000000..91dea7c0ca
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_ih.h
@@ -0,0 +1,28579 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/             
+
+#ifndef __IH_H_INCLUDED
+#define __IH_H_INCLUDED
+
+/*  File automatically generated by Reggae at 15/08/2013  10:54:43   */
+
+#include "access_macros.h"
+#include "packing.h"
+#include "rdp_map.h"
+
+/*****************************************************************************************/
+/* Lilac Ingres Handler. Ingres Handler in Lilac is responsible for incoming ingres traf */
+/* fic pre-processing. It includes re-used accelerators from Ginger: Parser & Look-up en */
+/* gine. The main features of IH (Ingres Handler) are as following: (1) Runner proccessi */
+/* ng offload (Parsing, Lookup engine), (2) Ingres QoS, (3) Target Memory decision: DDR  */
+/* or SRAM, (4) Runner load balancing                                                    */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Blocks offsets                                                                        */
+/*****************************************************************************************/
+/*****************************************************************************************/
+/* Functions offsets and addresses                                                       */
+/*****************************************************************************************/
+#define IH_REGS_LOOKUP_CONFIGURATION_OFFSET 	( 0x00000000 )
+#define IH_REGS_LOOKUP_CONFIGURATION_ADDRESS	( IH_REGS_OFFSET + IH_REGS_LOOKUP_CONFIGURATION_OFFSET )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_OFFSET 	( 0x00000400 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS	( IH_REGS_OFFSET + IH_REGS_PARSER_CORE_CONFIGURATION_OFFSET )
+
+#define IH_REGS_GENERAL_CONFIGURATION_OFFSET 	( 0x00000800 )
+#define IH_REGS_GENERAL_CONFIGURATION_ADDRESS	( IH_REGS_OFFSET + IH_REGS_GENERAL_CONFIGURATION_OFFSET )
+
+/*   'd' is module index   */
+/*   'i' is block index    */
+/*   'j' is function index */
+/*   'e' is function entry */
+/*   'k' is register index */
+
+/*****************************************************************************************/
+/* LKUP_TBL0_LUT_CFG                                                                     */
+/* Look-up table 0:  Configuration of LUT: table params + main flag                      */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_RESERVED_RESERVED_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_RESERVED_RESERVED_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_OFFSET ( 0x00000000 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t reserved     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG ;
+#else
+typedef struct
+{
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t reserved     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL1_LUT_CFG                                                                     */
+/* Look-up table 1:  Configuration of LUT: table params + main flags                     */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_OFFSET ( 0x00000004 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG ;
+#else
+typedef struct
+{
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL2_LUT_CFG                                                                     */
+/* Look-up table 2:  Configuration of LUT: table params + main flags                     */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_OFFSET ( 0x00000008 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG ;
+#else
+typedef struct
+{
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL3_LUT_CFG                                                                     */
+/* Look-up table 3:  Configuration of LUT: table params + main flags                     */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_OFFSET ( 0x0000000C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG ;
+#else
+typedef struct
+{
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL4_LUT_CFG                                                                     */
+/* Look-up table 4:  Configuration of LUT: table params + main flags                     */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_OFFSET ( 0x00000010 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG ;
+#else
+typedef struct
+{
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL5_LUT_CFG                                                                     */
+/* Look-up table 5:  Configuration of LUT: table params + main flags                     */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_OFFSET ( 0x00000014 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG ;
+#else
+typedef struct
+{
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL6_LUT_CFG                                                                     */
+/* Look-up table 6:  Configuration of LUT: table params + main flags                     */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_OFFSET ( 0x00000018 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG ;
+#else
+typedef struct
+{
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL7_LUT_CFG                                                                     */
+/* Look-up table 7:  Configuration of LUT: table params + main flags                     */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_OFFSET ( 0x0000001C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG ;
+#else
+typedef struct
+{
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL8_LUT_CFG                                                                     */
+/* Look-up table 8:  Configuration of LUT: table params + main flags                     */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_OFFSET ( 0x00000020 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG ;
+#else
+typedef struct
+{
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL9_LUT_CFG                                                                     */
+/* Look-up table 9:  Configuration of LUT: table params + main flags                     */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_OFFSET ( 0x00000024 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG ;
+#else
+typedef struct
+{
+	/* Table_base_address */
+	uint32_t base_address 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sa_search_en */
+	uint32_t sa_search_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* aging_en */
+	uint32_t aging_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* five_tuple_en */
+	uint32_t five_tuple_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL0_CAM_CFG                                                                     */
+/* Look-up table 0: CAM configurations (base addr + cam extention enable)                */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_OFFSET ( 0x00000028 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL1_CAM_CFG                                                                     */
+/* Look-up table 1: CAM configurations (base CAM addr + CAM extention enable)            */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_OFFSET ( 0x0000002C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL2_CAM_CFG                                                                     */
+/* Look-up table 2: CAM configurations (base addr + cam extention enable)                */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_OFFSET ( 0x00000030 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL3_CAM_CFG                                                                     */
+/* Look-up table 3: CAM configurations (CAM base addr + CAM extention enable)            */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_OFFSET ( 0x00000034 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL4_CAM_CFG                                                                     */
+/* Look-up table 4: CAM configurations (CAM base addr + CAM extention enable)            */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_OFFSET ( 0x00000038 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL5_CAM_CFG                                                                     */
+/* Look-up table 5: CAM configurations (CAM base addr + CAM extention enable)            */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_OFFSET ( 0x0000003C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL6_CAM_CFG                                                                     */
+/* Look-up table 6: CAM configurations (CAM base addr + CAM extention enable)            */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_OFFSET ( 0x00000040 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL7_CAM_CFG                                                                     */
+/* Look-up table 7: CAM configurations (CAM base addr + CAM extention enable)            */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_OFFSET ( 0x00000044 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL8_CAM_CFG                                                                     */
+/* Look-up table 8: CAM configurations (CAM base addr + CAM extention enable)            */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_OFFSET ( 0x00000048 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL9_CAM_CFG                                                                     */
+/* Look-up table 9: CAM configurations (CAM base addr + CAM extention enable)            */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_OFFSET ( 0x0000004C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL0_LUT_CNXT_CFG                                                                */
+/* Look-up table 0: LUT Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_OFFSET ( 0x00000050 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL1_LUT_CNXT_CFG                                                                */
+/* Look-up table 1: LUT Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_OFFSET ( 0x00000054 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL2_LUT_CNXT_CFG                                                                */
+/* Look-up table 2: LUT Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_OFFSET ( 0x00000058 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL3_LUT_CNXT_CFG                                                                */
+/* Look-up table 3: LUT Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_OFFSET ( 0x0000005C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL4_LUT_CNXT_CFG                                                                */
+/* Look-up table 4: LUT Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_OFFSET ( 0x00000060 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL5_LUT_CNXT_CFG                                                                */
+/* Look-up table 5: LUT Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_OFFSET ( 0x00000064 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL6_LUT_CNXT_CFG                                                                */
+/* Look-up table 6: LUT Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_RESREVED_RESERVED_VALUE                               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_RESREVED_RESERVED_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_OFFSET ( 0x00000068 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved       	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved       	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL7_LUT_CNXT_CFG                                                                */
+/* Look-up table 7: LUT Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_OFFSET ( 0x0000006C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL8_LUT_CNXT_CFG                                                                */
+/* Look-up table 8: LUT Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_OFFSET ( 0x00000070 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL9_LUT_CNXT_CFG                                                                */
+/* Look-up table 9: LUT Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_OFFSET ( 0x00000074 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_entry_size */
+	uint32_t cnxt_entry_size	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL0_CAM_CNXT_CFG                                                                */
+/* Look-up table 0: CAM Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_OFFSET ( 0x0000007C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL1_CAM_CNXT_CFG                                                                */
+/* Look-up table 1: CAM Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_OFFSET ( 0x00000080 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL2_CAM_CNXT_CFG                                                                */
+/* Look-up table 2: CAM Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_OFFSET ( 0x00000084 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL3_CAM_CNXT_CFG                                                                */
+/* Look-up table 3: CAM Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_OFFSET ( 0x00000088 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL4_CAM_CNXT_CFG                                                                */
+/* Look-up table 4: CAM Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_OFFSET ( 0x0000008C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL5_CAM_CNXT_CFG                                                                */
+/* Look-up table 5: CAM Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_OFFSET ( 0x00000090 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL6_CAM_CNXT_CFG                                                                */
+/* Look-up table 6: CAM Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_OFFSET ( 0x00000094 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL7_CAM_CNXT_CFG                                                                */
+/* Look-up table 7: CAM Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_OFFSET ( 0x00000098 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL8_CAM_CNXT_CFG                                                                */
+/* Look-up table 8: CAM Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_OFFSET ( 0x0000009C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL9_CAM_CNXT_CFG                                                                */
+/* Look-up table 9: CAM Context Table configurations (base addr + entry context size)    */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_OFFSET ( 0x00000100 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG ;
+#else
+typedef struct
+{
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL0_KEY_CFG                                                                     */
+/* Look-up table 0: Search key configuration parameters.    Key is based on two parts, e */
+/* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
+/* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
+/* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
+/*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
+/*  then two parts are ORed.  There is an option to add source port/GEM flow ID/WAN (tak */
+/* en from Ingres Header Descriptor) to LSB of the search key.                           */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_OFFSET ( 0x00000104 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG ;
+#else
+typedef struct
+{
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL0_KEY_P0_MASKL                                                                */
+/* Look-up table 0: MAsk on bits [31:0] of Part 0    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_OFFSET ( 0x00000108 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL0_KEY_P0_MASKH                                                                */
+/* Look-up table 0: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_OFFSET ( 0x0000010C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL0_KEY_P1_MASKL                                                                */
+/* Look-up table 0: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_OFFSET ( 0x00000110 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL0_KEY_P1_MASKH                                                                */
+/* Look-up table 0: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_OFFSET ( 0x00000114 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL1_KEY_CFG                                                                     */
+/* Look-up table 1: Search key configuration parameters.    Key is based on two parts, e */
+/* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
+/* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
+/* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
+/*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
+/*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
+/* eader Descriptor) to 5 MSB of the search key.                                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_OFFSET ( 0x00000118 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG ;
+#else
+typedef struct
+{
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL1_KEY_P0_MASKL                                                                */
+/* Look-up table 0: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_OFFSET ( 0x0000011C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL1_KEY_P0_MASKH                                                                */
+/* Look-up table 0: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_OFFSET ( 0x00000120 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL1_KEY_P1_MASKL                                                                */
+/* Look-up table 1: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_OFFSET ( 0x00000124 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL1_KEY_P1_MASKH                                                                */
+/* Look-up table 1: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_OFFSET ( 0x00000128 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL2_KEY_CFG                                                                     */
+/* Look-up table 2: Search key configuration parameters.    Key is based on two parts, e */
+/* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
+/* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
+/* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
+/*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
+/*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
+/* eader Descriptor) to 5 MSB of the search key.                                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_OFFSET ( 0x0000012C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG ;
+#else
+typedef struct
+{
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL2_KEY_P0_MASKL                                                                */
+/* Look-up table 0: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_OFFSET ( 0x00000130 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL2_KEY_P0_MASKH                                                                */
+/* Look-up table 2: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_OFFSET ( 0x00000134 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL2_KEY_P1_MASKL                                                                */
+/* Look-up table 1: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_OFFSET ( 0x00000138 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL2_KEY_P1_MASKH                                                                */
+/* Look-up table 3: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_OFFSET ( 0x0000013C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL3_KEY_CFG                                                                     */
+/* Look-up table 2: Search key configuration parameters.    Key is based on two parts, e */
+/* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
+/* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
+/* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
+/*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
+/*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
+/* eader Descriptor) to 5 MSB of the search key.                                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_OFFSET ( 0x00000140 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG ;
+#else
+typedef struct
+{
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL3_KEY_P0_MASKL                                                                */
+/* Look-up table 3: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_OFFSET ( 0x00000144 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL3_KEY_P0_MASKH                                                                */
+/* Look-up table 2: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_OFFSET ( 0x00000148 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL3_KEY_P1_MASKL                                                                */
+/* Look-up table 1: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_OFFSET ( 0x0000014C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL3_KEY_P1_MASKH                                                                */
+/* Look-up table 3: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_OFFSET ( 0x00000150 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL4_KEY_CFG                                                                     */
+/* Look-up table 4: Search key configuration parameters.    Key is based on two parts, e */
+/* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
+/* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
+/* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
+/*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
+/*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
+/* eader Descriptor) to 5 MSB of the search key.                                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_OFFSET ( 0x00000154 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG ;
+#else
+typedef struct
+{
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL4_KEY_P0_MASKL                                                                */
+/* Look-up table 4: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_OFFSET ( 0x00000158 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL4_KEY_P0_MASKH                                                                */
+/* Look-up table 4: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_OFFSET ( 0x0000015C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL4_KEY_P1_MASKL                                                                */
+/* Look-up table 4: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_OFFSET ( 0x00000160 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL4_KEY_P1_MASKH                                                                */
+/* Look-up table 4: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_OFFSET ( 0x00000164 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL5_KEY_CFG                                                                     */
+/* Look-up table 5: Search key configuration parameters.    Key is based on two parts, e */
+/* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
+/* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
+/* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
+/*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
+/*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
+/* eader Descriptor) to 5 MSB of the search key.                                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_OFFSET ( 0x00000168 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG ;
+#else
+typedef struct
+{
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL5_KEY_P0_MASKL                                                                */
+/* Look-up table 4: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_OFFSET ( 0x0000016C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL5_KEY_P0_MASKH                                                                */
+/* Look-up table 5: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_OFFSET ( 0x00000170 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL5_KEY_P1_MASKL                                                                */
+/* Look-up table 5: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_OFFSET ( 0x00000174 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL5_KEY_P1_MASKH                                                                */
+/* Look-up table 5: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_OFFSET ( 0x00000178 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL6_KEY_CFG                                                                     */
+/* Look-up table 6: Search key configuration parameters.    Key is based on two parts, e */
+/* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
+/* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
+/* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
+/*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
+/*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
+/* eader Descriptor) to 5 MSB of the search key.                                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_OFFSET ( 0x0000017C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG ;
+#else
+typedef struct
+{
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL6_KEY_P0_MASKL                                                                */
+/* Look-up table 6: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_OFFSET ( 0x00000180 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL6_KEY_P0_MASKH                                                                */
+/* Look-up table 6: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_OFFSET ( 0x00000184 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL6_KEY_P1_MASKL                                                                */
+/* Look-up table 6: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_OFFSET ( 0x00000188 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL6_KEY_P1_MASKH                                                                */
+/* Look-up table 6: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_OFFSET ( 0x0000018C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL7_KEY_CFG                                                                     */
+/* Look-up table 7: Search key configuration parameters.    Key is based on two parts, e */
+/* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
+/* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
+/* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
+/*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
+/*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
+/* eader Descriptor) to 5 MSB of the search key.                                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_OFFSET ( 0x00000190 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG ;
+#else
+typedef struct
+{
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL7_KEY_P0_MASKL                                                                */
+/* Look-up table 7: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_OFFSET ( 0x00000194 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL7_KEY_P0_MASKH                                                                */
+/* Look-up table 7: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_OFFSET ( 0x00000198 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL7_KEY_P1_MASKL                                                                */
+/* Look-up table 7: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_OFFSET ( 0x0000019C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL7_KEY_P1_MASKH                                                                */
+/* Look-up table 7: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_OFFSET ( 0x00000200 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL8_KEY_CFG                                                                     */
+/* Look-up table 8: Search key configuration parameters.    Key is based on two parts, e */
+/* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
+/* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
+/* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
+/*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
+/*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
+/* eader Descriptor) to 5 MSB of the search key.                                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_OFFSET ( 0x00000204 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG ;
+#else
+typedef struct
+{
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL8_KEY_P0_MASKL                                                                */
+/* Look-up table 8: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_OFFSET ( 0x00000208 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL8_KEY_P0_MASKH                                                                */
+/* Look-up table 8: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_OFFSET ( 0x0000020C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL8_KEY_P1_MASKL                                                                */
+/* Look-up table 8: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_OFFSET ( 0x00000210 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL8_KEY_P1_MASKH                                                                */
+/* Look-up table 8: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_OFFSET ( 0x00000214 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL9_KEY_CFG                                                                     */
+/* Look-up table 9: Search key configuration parameters.    Key is based on two parts, e */
+/* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
+/* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
+/* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
+/*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
+/*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
+/* eader Descriptor) to 5 MSB of the search key.                                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_OFFSET ( 0x00000218 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG ;
+#else
+typedef struct
+{
+	/* start_offset_p0 */
+	uint32_t start_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p0 */
+	uint32_t shift_offset_p0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* start_offset_p1 */
+	uint32_t start_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* shift_offset_p1 */
+	uint32_t shift_offset_p1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_EXT */
+	uint32_t key_ext        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t resreved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL9_KEY_P0_MASKL                                                                */
+/* Look-up table 9: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_OFFSET ( 0x0000021C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL9_KEY_P0_MASKH                                                                */
+/* Look-up table 9: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_OFFSET ( 0x00000220 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL9_KEY_P1_MASKL                                                                */
+/* Look-up table 9: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
+/* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
+/* ts own mask that represnted by two registers: MASKL and MASKH                         */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_OFFSET ( 0x00000224 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL ;
+#else
+typedef struct
+{
+	/* MASKL */
+	uint32_t maskl	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL9_KEY_P1_MASKH                                                                */
+/* Look-up table 9: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
+/* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
+/* its own mask that represnted by two registers: MASKL and MASKH                        */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_OFFSET ( 0x00000228 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH ;
+#else
+typedef struct
+{
+	/* MASKH */
+	uint32_t maskh   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL0_GL_MASK                                                                     */
+/* Look-up table 0: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
+/* ) On general key generation, the global mask is ANDed with final result of key (after */
+/*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
+/* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
+/* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
+/* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
+/* 00FF                                                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_OFFSET ( 0x0000022C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK ;
+#else
+typedef struct
+{
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL1_GL_MASK                                                                     */
+/* Look-up table 1: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
+/* ) On general key generation, the global mask is ANDed with final result of key (after */
+/*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
+/* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
+/* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
+/* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
+/* 00FF                                                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_OFFSET ( 0x00000230 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK ;
+#else
+typedef struct
+{
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL2_GL_MASK                                                                     */
+/* Look-up table 2: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
+/* ) On general key generation, the global mask is ANDed with final result of key (after */
+/*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
+/* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
+/* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
+/* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
+/* 00FF                                                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_OFFSET ( 0x00000234 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK ;
+#else
+typedef struct
+{
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL3_GL_MASK                                                                     */
+/* Look-up table 3: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
+/* ) On general key generation, the global mask is ANDed with final result of key (after */
+/*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
+/* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
+/* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
+/* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
+/* 00FF                                                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_OFFSET ( 0x00000238 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK ;
+#else
+typedef struct
+{
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL4_GL_MASK                                                                     */
+/* Look-up table 4: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
+/* ) On general key generation, the global mask is ANDed with final result of key (after */
+/*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
+/* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
+/* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
+/* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
+/* 00FF                                                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_OFFSET ( 0x0000023C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK ;
+#else
+typedef struct
+{
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL5_GL_MASK                                                                     */
+/* Look-up table 5: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
+/* ) On general key generation, the global mask is ANDed with final result of key (after */
+/*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
+/* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
+/* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
+/* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
+/* 00FF                                                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_OFFSET ( 0x00000240 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK ;
+#else
+typedef struct
+{
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL6_GL_MASK                                                                     */
+/* Look-up table 6: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
+/* ) On general key generation, the global mask is ANDed with final result of key (after */
+/*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
+/* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
+/* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
+/* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
+/* 00FF                                                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_OFFSET ( 0x00000244 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK ;
+#else
+typedef struct
+{
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL7_GL_MASK                                                                     */
+/* Look-up table 7: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
+/* ) On general key generation, the global mask is ANDed with final result of key (after */
+/*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
+/* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
+/* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
+/* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
+/* 00FF                                                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_OFFSET ( 0x00000248 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK ;
+#else
+typedef struct
+{
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL8_GL_MASK                                                                     */
+/* Look-up table 8: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
+/* ) On general key generation, the global mask is ANDed with final result of key (after */
+/*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
+/* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
+/* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
+/* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
+/* 00FF                                                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_OFFSET ( 0x0000024C )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK ;
+#else
+typedef struct
+{
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK ;
+#endif
+
+/*****************************************************************************************/
+/* LKUP_TBL9_GL_MASK                                                                     */
+/* Look-up table 9: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
+/* ) On general key generation, the global mask is ANDed with final result of key (after */
+/*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
+/* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
+/* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
+/* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
+/* 00FF                                                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_OFFSET ( 0x00000250 )
+
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_ADDRESS   	( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_OFFSET )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_READ( r ) 	READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_ADDRESS ), (r) )
+#define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_WRITE( v )	WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK ;
+#else
+typedef struct
+{
+	/* MASK_NIBBLE_CODE */
+	uint32_t mask_nibble_code	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT0_VAL_L                                                                        */
+/* Config DA filter 31:0                                                                 */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_OFFSET ( 0x00000000 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L ;
+#else
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT0_MASK_L                                                                       */
+/* Config DA Filter mask 15:0                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT0_MASK_L_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT0_MASK_L_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_OFFSET ( 0x00000004 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_MASK_L */
+	uint32_t da_filt0_mask_l	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L ;
+#else
+typedef struct
+{
+	/* DA_FILT_MASK_L */
+	uint32_t da_filt0_mask_l	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT0_CFG_H                                                                        */
+/* DA Filter0 Value & Mask highest bits 15:0                                             */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_DA_FILT_MASK_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_DA_FILT_MASK_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_DA_FILT_VAL_MSB_FILTER_CONFIG_VALUE              ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_DA_FILT_VAL_MSB_FILTER_CONFIG_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_OFFSET ( 0x00000008 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_MASK_MSB */
+	uint32_t da_filt_mask_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT_VAL_MSB */
+	uint32_t da_filt_val_msb 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H ;
+#else
+typedef struct
+{
+	/* DA_FILT_VAL_MSB */
+	uint32_t da_filt_val_msb 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT_MASK_MSB */
+	uint32_t da_filt_mask_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H ;
+#endif
+
+/*****************************************************************************************/
+/* PARSER_CFG                                                                            */
+/* Parser Configuration                                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_RESERVED1_RESERVED_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_EXCEPTION_EN_0_DEFAULT_VALUE              ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_EXCEPTION_EN_0_DEFAULT_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_PPP_CODE_1_IPV6_DEFAULT_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_PPP_CODE_1_IPV6_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_EXCEPTION_EN_RESET_VALUE                  ( 0xF )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_EXCEPTION_EN_RESET_VALUE_RESET_VALUE      ( 0xF )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_TCP_FLAGS_FILT_RESET_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_TCP_FLAGS_FILT_RESET_VALUE_RESET_VALUE    ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_OFFSET ( 0x0000000C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RESERVED */
+	uint32_t reserved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exception_en_0 */
+	uint32_t exception_en_0 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ppp_code_1_ipv6 */
+	uint32_t ppp_code_1_ipv6	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EXCEPTION_EN */
+	uint32_t exception_en   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TCP_FLAGS_TCP_FILTER */
+	uint32_t tcp_flags_filt 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG ;
+#else
+typedef struct
+{
+	/* TCP_FLAGS_TCP_FILTER */
+	uint32_t tcp_flags_filt 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EXCEPTION_EN */
+	uint32_t exception_en   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ppp_code_1_ipv6 */
+	uint32_t ppp_code_1_ipv6	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exception_en_0 */
+	uint32_t exception_en_0 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESERVED */
+	uint32_t reserved1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* QTAG_Ethertype                                                                        */
+/* Ethertype values to identify the presence of VLAN QTAG                                */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_RESET_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_OFFSET ( 0x00000010 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Ethertyp_for_Qtag_1 */
+	uint32_t ethtype_qtag_1	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethertyp_for_Qtag_0 */
+	uint32_t ethtype_qtag_0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE ;
+#else
+typedef struct
+{
+	/* Ethertyp_for_Qtag_0 */
+	uint32_t ethtype_qtag_0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ethertyp_for_Qtag_1 */
+	uint32_t ethtype_qtag_1	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE ;
+#endif
+
+/*****************************************************************************************/
+/* QTAG_Nesting                                                                          */
+/* Qtag Nesting config                                                                   */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED1_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED1_RESET_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG5_NEST_DISABLED_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG5_NEST_DISABLED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG4_NEST_DISABLED_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG4_NEST_DISABLED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG3_NEST_DISABLED_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG3_NEST_DISABLED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG2_NEST_RESET_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG2_NEST_RESET_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG1_NEST_DISABLED_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG1_NEST_DISABLED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG0_NEST_DISABLED_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG0_NEST_DISABLED_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_OFFSET ( 0x00000014 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1 	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_5_Nesting_Config */
+	uint32_t qtag5_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_4_Nesting_Config */
+	uint32_t qtag4_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_3_Nesting_Config */
+	uint32_t qtag3_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_2_Nesting_Config */
+	uint32_t qtag2_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_1_Nesting_Config */
+	uint32_t qtag1_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_0_Nesting_Config */
+	uint32_t qtag0_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST ;
+#else
+typedef struct
+{
+	/* QTAG_0_Nesting_Config */
+	uint32_t qtag0_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_1_Nesting_Config */
+	uint32_t qtag1_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_2_Nesting_Config */
+	uint32_t qtag2_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_3_Nesting_Config */
+	uint32_t qtag3_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_4_Nesting_Config */
+	uint32_t qtag4_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_5_Nesting_Config */
+	uint32_t qtag5_nest	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1 	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST ;
+#endif
+
+/*****************************************************************************************/
+/* Snap_organization_code                                                                */
+/* Identifies SNAP tunneling organization code                                           */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED1_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED1_RESET_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_DISABLED_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_DISABLED_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_ENABLED_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_DISABLED_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_DISABLED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_ENABLED_VALUE              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_RESET_VALUE                      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_RESET_VALUE_RESET_VALUE          ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_OFFSET ( 0x00000018 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t reserved1 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* 802.1Q_ehternet_encapsulation */
+	uint32_t en_8021q  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RFC1042_ethernet_encapsulation_enable */
+	uint32_t en_rfc1042	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Organization_Code */
+	uint32_t code      	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE ;
+#else
+typedef struct
+{
+	/* Organization_Code */
+	uint32_t code      	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RFC1042_ethernet_encapsulation_enable */
+	uint32_t en_rfc1042	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* 802.1Q_ehternet_encapsulation */
+	uint32_t en_8021q  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t reserved1 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE ;
+#endif
+
+/*****************************************************************************************/
+/* User_Ethertype_configurtion_0_1                                                       */
+/* Configures user Ethertype values                                                      */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_RESET_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_OFFSET ( 0x0000001C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* User_Ethertype_1 */
+	uint32_t ethype_1	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_0 */
+	uint32_t ethype_0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1 ;
+#else
+typedef struct
+{
+	/* User_Ethertype_0 */
+	uint32_t ethype_0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_1 */
+	uint32_t ethype_1	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1 ;
+#endif
+
+/*****************************************************************************************/
+/* User_Ethertype_configurtion_2_3                                                       */
+/* Configures user Ethertype values                                                      */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_RESET_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_OFFSET ( 0x00000020 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* User_Ethertype_3 */
+	uint32_t ethype_3	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_2 */
+	uint32_t ethype_2	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3 ;
+#else
+typedef struct
+{
+	/* User_Ethertype_2 */
+	uint32_t ethype_2	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_3 */
+	uint32_t ethype_3	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3 ;
+#endif
+
+/*****************************************************************************************/
+/* User_Ethertype_Configuration                                                          */
+/* Configure protocol and enables user Ethertype                                         */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RSV_RESET_VALUE                               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RSV_RESET_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_RESET_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_RESER_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_RESER_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_RESER_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_RESER_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_RESER_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_RESER_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_RESER_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_RESER_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_OFFSET ( 0x00000024 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* User_Ethertype_2_L3_Offset */
+	uint32_t ethtype_user_offset_3	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_2_L3_Offset */
+	uint32_t ethtype_user_offset_2	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_1_L3_Offset */
+	uint32_t ethtype_user_offset_1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_0_L3_Offset */
+	uint32_t ethtype_user_offset_0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv                  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_Enable */
+	uint32_t ethtype_user_en      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_3 */
+	uint32_t ethtype_user_prot_3  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_2 */
+	uint32_t ethtype_user_prot_2  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_1 */
+	uint32_t ethtype_user_prot_1  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_0_protocol */
+	uint32_t ethtype_user_prot_0  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG ;
+#else
+typedef struct
+{
+	/* User_Ethertype_0_protocol */
+	uint32_t ethtype_user_prot_0  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_1 */
+	uint32_t ethtype_user_prot_1  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_2 */
+	uint32_t ethtype_user_prot_2  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_3 */
+	uint32_t ethtype_user_prot_3  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_Enable */
+	uint32_t ethtype_user_en      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv                  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_0_L3_Offset */
+	uint32_t ethtype_user_offset_0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_1_L3_Offset */
+	uint32_t ethtype_user_offset_1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_2_L3_Offset */
+	uint32_t ethtype_user_offset_2	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_2_L3_Offset */
+	uint32_t ethtype_user_offset_3	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG ;
+#endif
+
+/*****************************************************************************************/
+/* VID_Configuration_0_1                                                                 */
+/* Config VID Filter 0 & 1                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_RESET_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_ENABLE_VALUE              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED_1_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_RESET_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_RESET_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_ENABLE_VALUE              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED_0_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_RESET_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_OFFSET ( 0x00000028 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* VID_1_Enable */
+	uint32_t vid_1_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_1 */
+	uint32_t vid_1     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_0_Enable */
+	uint32_t vid_0_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_0 */
+	uint32_t vid_0     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1 ;
+#else
+typedef struct
+{
+	/* VID_0 */
+	uint32_t vid_0     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_0_Enable */
+	uint32_t vid_0_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_1 */
+	uint32_t vid_1     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_1_Enable */
+	uint32_t vid_1_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1 ;
+#endif
+
+/*****************************************************************************************/
+/* VID_Configuration_2_3                                                                 */
+/* Config VID Filter 2 & 3                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_RESET_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_ENABLE_VALUE              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED_1_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_RESET_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_RESET_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_ENABLE_VALUE              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED_0_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_RESET_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_OFFSET ( 0x0000002C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* VID_3_Enable */
+	uint32_t vid_3_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_3 */
+	uint32_t vid_3     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_2_Enable */
+	uint32_t vid_2_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_2 */
+	uint32_t vid_2     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3 ;
+#else
+typedef struct
+{
+	/* VID_2 */
+	uint32_t vid_2     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_2_Enable */
+	uint32_t vid_2_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_3 */
+	uint32_t vid_3     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_3_Enable */
+	uint32_t vid_3_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3 ;
+#endif
+
+/*****************************************************************************************/
+/* VID_Configuration_4_5                                                                 */
+/* Config VID Filter 4 & 5                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_RESET_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_ENABLE_VALUE              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED_1_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_RESET_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_RESET_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_ENABLE_VALUE              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED_0_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_RESET_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_OFFSET ( 0x00000030 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* VID_5_Enable */
+	uint32_t vid_5_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_5 */
+	uint32_t vid_5     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_4_Enable */
+	uint32_t vid_4_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_4 */
+	uint32_t vid_4     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5 ;
+#else
+typedef struct
+{
+	/* VID_4 */
+	uint32_t vid_4     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_4_Enable */
+	uint32_t vid_4_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_5 */
+	uint32_t vid_5     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_5_Enable */
+	uint32_t vid_5_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5 ;
+#endif
+
+/*****************************************************************************************/
+/* VID_Configuration_6_7                                                                 */
+/* Config VID Filter 6 & 7                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_RESET_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_ENABLE_VALUE              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED_1_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_RESET_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_RESET_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_ENABLE_VALUE              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED_0_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_RESET_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_OFFSET ( 0x00000034 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* VID_7_Enable */
+	uint32_t vid_7_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_7 */
+	uint32_t vid_7     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_6_Enable */
+	uint32_t vid_6_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_6 */
+	uint32_t vid_6     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7 ;
+#else
+typedef struct
+{
+	/* VID_6 */
+	uint32_t vid_6     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_6_Enable */
+	uint32_t vid_6_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_7 */
+	uint32_t vid_7     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_7_Enable */
+	uint32_t vid_7_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7 ;
+#endif
+
+/*****************************************************************************************/
+/* VID_Configuration_8_9                                                                 */
+/* Config VID Filter 8 & 9                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_9_EN_RESET_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_9_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_9_EN_ENABLE_VALUE              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_RESERVED_1_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_9_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_9_RESET_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_8_EN_RESET_VALUE               ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_8_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_8_EN_ENABLE_VALUE              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_RESERVED_0_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_8_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_8_RESET_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_OFFSET ( 0x00000038 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* VID_9_Enable */
+	uint32_t vid_9_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_9 */
+	uint32_t vid_9     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_8_Enable */
+	uint32_t vid_8_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_8 */
+	uint32_t vid_8     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9 ;
+#else
+typedef struct
+{
+	/* VID_8 */
+	uint32_t vid_8     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_8_Enable */
+	uint32_t vid_8_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_9 */
+	uint32_t vid_9     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_9_Enable */
+	uint32_t vid_9_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9 ;
+#endif
+
+/*****************************************************************************************/
+/* VID_Configuration_10_11                                                               */
+/* Config VID Filter 10 & 11                                                             */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_11_EN_RESET_VALUE              ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_11_EN_RESET_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_11_EN_ENABLE_VALUE             ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_RESERVED_1_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_11_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_11_RESET_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_10_EN_RESET_VALUE              ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_10_EN_RESET_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_10_EN_ENABLE_VALUE             ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_RESERVED_0_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_10_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_10_RESET_VALUE_RESET_VALUE     ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_OFFSET ( 0x0000003C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* VID_11_Enable */
+	uint32_t vid_11_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_11 */
+	uint32_t vid_11    	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_10_Enable */
+	uint32_t vid_10_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_10 */
+	uint32_t vid_10    	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11 ;
+#else
+typedef struct
+{
+	/* VID_10 */
+	uint32_t vid_10    	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_10_Enable */
+	uint32_t vid_10_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_11 */
+	uint32_t vid_11    	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved_1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_11_Enable */
+	uint32_t vid_11_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11 ;
+#endif
+
+/*****************************************************************************************/
+/* User_defined_IP_Protocl                                                               */
+/* IP Protocols to be matched to IP Protocol field and to be indicated in the output sum */
+/* mary word                                                                             */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_RESET_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_OFFSET ( 0x00000040 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* USER__IP_protocol_3 */
+	uint32_t user_ip_prot_3	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USER_IP_protocol_2 */
+	uint32_t user_ip_prot_2	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USER_IP_protocol_1 */
+	uint32_t user_ip_prot_1	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USER_IP_protocol_0 */
+	uint32_t user_ip_prot_0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT ;
+#else
+typedef struct
+{
+	/* USER_IP_protocol_0 */
+	uint32_t user_ip_prot_0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USER_IP_protocol_1 */
+	uint32_t user_ip_prot_1	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USER_IP_protocol_2 */
+	uint32_t user_ip_prot_2	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USER__IP_protocol_3 */
+	uint32_t user_ip_prot_3	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT ;
+#endif
+
+/*****************************************************************************************/
+/* PPP_IP_Protocol_Code                                                                  */
+/* PPP Protocol Code to indicate L3 is IP                                                */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_RESET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_RESET_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_OFFSET ( 0x00000044 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PPP_Protocol_Code_1 */
+	uint32_t ppp_code_1	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PPP_Protocol_Code_0 */
+	uint32_t ppp_code_0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE ;
+#else
+typedef struct
+{
+	/* PPP_Protocol_Code_0 */
+	uint32_t ppp_code_0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PPP_Protocol_Code_1 */
+	uint32_t ppp_code_1	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE ;
+#endif
+
+/*****************************************************************************************/
+/* IP_FILTER0_CFG                                                                        */
+/* Config the IP Address filtering.   Notice that the enable bit is located in the IP_FI */
+/* LTERS_CFG[4]                                                                          */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_OFFSET ( 0x00000048 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IP_address */
+	uint32_t ip_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG ;
+#else
+typedef struct
+{
+	/* IP_address */
+	uint32_t ip_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IP_FILTER1_CFG                                                                        */
+/* Config the IP Address filtering.   Notice that the enable bit is located in the IP_FI */
+/* LTERS_CFG[5]                                                                          */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_OFFSET ( 0x0000004C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IP_address */
+	uint32_t ip_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG ;
+#else
+typedef struct
+{
+	/* IP_address */
+	uint32_t ip_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IP_FILTER2_CFG                                                                        */
+/* Config the IP Address filtering.   Notice that the enable bit is located in the IP_FI */
+/* LTERS_CFG[6]                                                                          */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_OFFSET ( 0x00000050 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IP_address */
+	uint32_t ip_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG ;
+#else
+typedef struct
+{
+	/* IP_address */
+	uint32_t ip_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IP_FILTER3_CFG                                                                        */
+/* Config the IP Address filtering.   Notice that the enable bit is located in the IP_FI */
+/* LTERS_CFG[7]                                                                          */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_OFFSET ( 0x00000054 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IP_address */
+	uint32_t ip_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG ;
+#else
+typedef struct
+{
+	/* IP_address */
+	uint32_t ip_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT1_VAL_L                                                                        */
+/* Config DA filter1 31:0                                                                */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_OFFSET ( 0x00000058 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L ;
+#else
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT1_MASK_L                                                                       */
+/* Config DA Filter1 mask 31:0                                                           */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT0_MASK_L_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT0_MASK_L_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_OFFSET ( 0x0000005C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_MASK_L */
+	uint32_t da_filt0_mask_l	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L ;
+#else
+typedef struct
+{
+	/* DA_FILT_MASK_L */
+	uint32_t da_filt0_mask_l	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT1_CFG_H                                                                        */
+/* DA Filter1 Value & Mask highest bits 15:0                                             */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_DA_FILT_MASK_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_DA_FILT_MASK_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_DA_FILT_VAL_MSB_FILTER_CONFIG_VALUE              ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_DA_FILT_VAL_MSB_FILTER_CONFIG_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_OFFSET ( 0x00000060 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_MASK_MSB */
+	uint32_t da_filt_mask_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT_VAL_MSB */
+	uint32_t da_filt_val_msb 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H ;
+#else
+typedef struct
+{
+	/* DA_FILT_VAL_MSB */
+	uint32_t da_filt_val_msb 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT_MASK_MSB */
+	uint32_t da_filt_mask_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT2_VAL_L                                                                        */
+/* Config DA filter2 31:0                                                                */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_OFFSET ( 0x00000064 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L ;
+#else
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT2_VAL_H                                                                        */
+/* Config DA filter2 47:32                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_OFFSET ( 0x00000068 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H ;
+#else
+typedef struct
+{
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT3_VAL_L                                                                        */
+/* Config DA filter3 31:0                                                                */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_OFFSET ( 0x0000006C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L ;
+#else
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT3_VAL_H                                                                        */
+/* Config DA filter3 47:32                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_OFFSET ( 0x00000070 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H ;
+#else
+typedef struct
+{
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT4_VAL_L                                                                        */
+/* Config DA filter4 31:0                                                                */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_OFFSET ( 0x00000074 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L ;
+#else
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT4_VAL_H                                                                        */
+/* Config DA Filter4 47:32                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_OFFSET ( 0x00000078 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H ;
+#else
+typedef struct
+{
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT5_VAL_L                                                                        */
+/* Config DA filter5 31:0                                                                */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_OFFSET ( 0x0000007C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L ;
+#else
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT5_VAL_H                                                                        */
+/* Config DA Filter5 47:32                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_OFFSET ( 0x00000080 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H ;
+#else
+typedef struct
+{
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT_VALID_CFG                                                                     */
+/* Valid configuration of all DA filters: there is a dedicated bit per each DA filter th */
+/* at says if the current DA filter is valid or not. Used for on-the-fly DA filter value */
+/*  (mask) modifications, since the DA filter parameters are not assigned on single SW r */
+/* egister.                                                                              */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_RSV_FILTER_CONFIG_VALUE                    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_RSV_FILTER_CONFIG_VALUE_RESET_VALUE        ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT7_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT7_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT7_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT6_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT6_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT6_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT5_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT5_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT5_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT4_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT4_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT4_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT3_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT3_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT3_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT2_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT2_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT2_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT1_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT1_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT1_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT0_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT0_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT0_VALID_VALID_VALUE                 ( 0x1 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_OFFSET ( 0x00000084 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv           	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT7_VALID */
+	uint32_t da_filt7_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT6_VALID */
+	uint32_t da_filt6_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT5_VALID */
+	uint32_t da_filt5_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT4_VALID */
+	uint32_t da_filt4_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT3_VALID */
+	uint32_t da_filt3_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT2_VALID */
+	uint32_t da_filt2_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT1_VALID */
+	uint32_t da_filt1_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT0_VALID */
+	uint32_t da_filt0_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG ;
+#else
+typedef struct
+{
+	/* DA_FILT0_VALID */
+	uint32_t da_filt0_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT1_VALID */
+	uint32_t da_filt1_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT2_VALID */
+	uint32_t da_filt2_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT3_VALID */
+	uint32_t da_filt3_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT4_VALID */
+	uint32_t da_filt4_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT5_VALID */
+	uint32_t da_filt5_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT6_VALID */
+	uint32_t da_filt6_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT7_VALID */
+	uint32_t da_filt7_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv           	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IP_FILTER0_MASK_CFG                                                                   */
+/* Config the IP Address masking.   Notice that the enable bit is located in the IP_FILT */
+/* ERS_CFG[4]                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_OFFSET ( 0x00000088 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IP_address_mask */
+	uint32_t ip_address_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG ;
+#else
+typedef struct
+{
+	/* IP_address_mask */
+	uint32_t ip_address_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IP_FILTER1_MASK_CFG                                                                   */
+/* Config the IP Address masking.   Notice that the enable bit is located in the IP_FILT */
+/* ERS_CFG[5]                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_OFFSET ( 0x0000008C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IP_address_mask */
+	uint32_t ip_address_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG ;
+#else
+typedef struct
+{
+	/* IP_address_mask */
+	uint32_t ip_address_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IP_FILTER2_MASK_CFG                                                                   */
+/* Config the IP Address masking.   Notice that the enable bit is located in the IP_FILT */
+/* ERS_CFG[6]                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_OFFSET ( 0x00000090 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IP_address_mask */
+	uint32_t ip_address_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG ;
+#else
+typedef struct
+{
+	/* IP_address_mask */
+	uint32_t ip_address_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IP_FILTER3_MASK_CFG                                                                   */
+/* Config the IP Address masking.   Notice that the enable bit is located in the IP_FILT */
+/* ERS_CFG[7]                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_OFFSET ( 0x00000094 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IP_address_mask */
+	uint32_t ip_address_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG ;
+#else
+typedef struct
+{
+	/* IP_address_mask */
+	uint32_t ip_address_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IP_FILTERS_CFG                                                                        */
+/* IP Address Filters (0..3) configurations:    (1) SIP or DIP selection config per each */
+/*  filter  (1) Valid bit per each filter                                                */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RSV_NON_VALID_VALUE                          ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RSV_NON_VALID_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RSV_VALID_VALUE                              ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_SIP_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_SIP_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_DIP_VALUE                  ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_SIP_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_SIP_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_DIP_VALUE                  ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_SIP_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_SIP_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_DIP_VALUE                  ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_SIP_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_SIP_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_DIP_VALUE                  ( 0x1 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_OFFSET ( 0x00000098 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv              	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER3_VALID */
+	uint32_t ip_filter3_valid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER2_VALID */
+	uint32_t ip_filter2_valid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER1_VALID */
+	uint32_t ip_filter1_valid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER0_VALID */
+	uint32_t ip_filter0_valid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER3_DIP_EN */
+	uint32_t ip_filter3_dip_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER2_DIP_EN */
+	uint32_t ip_filter2_dip_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER1_DIP_EN */
+	uint32_t ip_filter1_dip_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER0_DIP_EN */
+	uint32_t ip_filter0_dip_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG ;
+#else
+typedef struct
+{
+	/* IP_FILTER0_DIP_EN */
+	uint32_t ip_filter0_dip_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER1_DIP_EN */
+	uint32_t ip_filter1_dip_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER2_DIP_EN */
+	uint32_t ip_filter2_dip_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER3_DIP_EN */
+	uint32_t ip_filter3_dip_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER0_VALID */
+	uint32_t ip_filter0_valid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER1_VALID */
+	uint32_t ip_filter1_valid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER2_VALID */
+	uint32_t ip_filter2_valid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER3_VALID */
+	uint32_t ip_filter3_valid 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv              	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* GRE_PROTOCOL_CFG                                                                      */
+/* GRE Protocol                                                                          */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RSV_NON_VALID_VALUE                     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RSV_NON_VALID_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RSV_VALID_VALUE                         ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_PROTOCOL_VALUE             ( 0x880B )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_PROTOCOL_VALUE_RESET_VALUE ( 0x880B )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_OFFSET ( 0x0000009C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv         	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GRE_PROTOCOL */
+	uint32_t gre_protocol	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG ;
+#else
+typedef struct
+{
+	/* GRE_PROTOCOL */
+	uint32_t gre_protocol	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv         	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL0_R0                                                                      */
+/* DSCP to TCI Conversion Table 0.  Register 0 that stores convetion code for the follow */
+/* ing DSCP values: 0x0..0x7.    Used for conversion in case of IP untagged packet    Th */
+/* e coding of each field is done in the following way:  TCI converted field should matc */
+/* h DSCP index (from 0 to 63). This index is applied by the following equation: registe */
+/* r_index*8+octet(or field) index                                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_OFFSET ( 0x00000100 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL0_R1                                                                      */
+/* DSCP to TCI Conversion Table 0.  Register 1 that stores convetion code for the follow */
+/* ing DSCP values: 0x8..0xf.    Used for conversion in case of IP untagged packet    Th */
+/* e coding of each field is done in the following way:  TCI converted field should matc */
+/* h DSCP index (from 0 to 63). This index is applied by the following equation: registe */
+/* r_index*8+octet(or field) index                                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_OFFSET ( 0x00000104 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL0_R2                                                                      */
+/* DSCP to TCI Conversion Table 0.  Register 2 that stores convetion code for the follow */
+/* ing DSCP values: 0x10..0x17.    Used for conversion in case of IP untagged packet     */
+/* The coding of each field is done in the following way:  TCI converted field should ma */
+/* tch DSCP index (from 0 to 63). This index is applied by the following equation: regis */
+/* ter_index*8+octet(or field) index                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_OFFSET ( 0x00000108 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL0_R3                                                                      */
+/* DSCP to TCI Conversion Table 0.  Register 3 that stores convetion code for the follow */
+/* ing DSCP values: 0x18..0x1f.    Used for conversion in case of IP untagged packet     */
+/* The coding of each field is done in the following way:  TCI converted field should ma */
+/* tch DSCP index (from 0 to 63). This index is applied by the following equation: regis */
+/* ter_index*8+octet(or field) index                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_OFFSET ( 0x0000010C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL0_R4                                                                      */
+/* DSCP to TCI Conversion Table 0.  Register 4 that stores conversion code for the follo */
+/* wing DSCP values: 0x20..0x27.    Used for conversion in case of IP untagged packet    */
+/*  The coding of each field is done in the following way:  TCI converted field should m */
+/* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
+/* ster_index*8+octet(or field) index                                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_OFFSET ( 0x00000110 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL0_R5                                                                      */
+/* DSCP to TCI Conversion Table 0.  Register 5 that stores conversion code for the follo */
+/* wing DSCP values: 0x28..0x2f.    Used for conversion in case of IP untagged packet    */
+/*  The coding of each field is done in the following way:  TCI converted field should m */
+/* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
+/* ster_index*8+octet(or field) index                                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_OFFSET ( 0x00000114 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL0_R6                                                                      */
+/* DSCP to TCI Conversion Table 0.  Register 6 that stores conversion code for the follo */
+/* wing DSCP values: 0x30..0x37.    Used for conversion in case of IP untagged packet    */
+/*  The coding of each field is done in the following way:  TCI converted field should m */
+/* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
+/* ster_index*8+octet(or field) index                                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_OFFSET ( 0x00000118 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL0_R7                                                                      */
+/* DSCP to TCI Conversion Table 0.  Register 7 that stores conversion code for the follo */
+/* wing DSCP values: 0x3c..0x3f.    Used for conversion in case of IP untagged packet    */
+/*    The coding of each field is done in the following way:  TCI converted field should */
+/*  match DSCP index (from 0 to 63). This index is applied by the following equation: re */
+/* gister_index*8+octet(or field) index                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_OFFSET ( 0x0000011C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL1_R0                                                                      */
+/* DSCP to TCI Conversion Table 1.  Register 0 that stores convetion code for the follow */
+/* ing DSCP values: 0x0..0x7.    Used for conversion in case of IP untagged packet    Th */
+/* e coding of each field is done in the following way:  TCI converted field should matc */
+/* h DSCP index (from 0 to 63). This index is applied by the following equation: registe */
+/* r_index*8+octet(or field) index                                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_OFFSET ( 0x00000120 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL1_R1                                                                      */
+/* DSCP to TCI Conversion Table 1.  Register 1 that stores convetion code for the follow */
+/* ing DSCP values: 0x8..0xf.    Used for conversion in case of IP untagged packet    Th */
+/* e coding of each field is done in the following way:  TCI converted field should matc */
+/* h DSCP index (from 0 to 63). This index is applied by the following equation: registe */
+/* r_index*8+octet(or field) index                                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_OFFSET ( 0x00000124 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL1_R2                                                                      */
+/* DSCP to TCI Conversion Table 1.  Register 2 that stores convetion code for the follow */
+/* ing DSCP values: 0x10..0x17.    Used for conversion in case of IP untagged packet     */
+/* The coding of each field is done in the following way:  TCI converted field should ma */
+/* tch DSCP index (from 0 to 63). This index is applied by the following equation: regis */
+/* ter_index*8+octet(or field) index                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_OFFSET ( 0x00000128 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL1_R3                                                                      */
+/* DSCP to TCI Conversion Table 1.  Register 3 that stores convetion code for the follow */
+/* ing DSCP values: 0x18..0x1f.    Used for conversion in case of IP untagged packet     */
+/* The coding of each field is done in the following way:  TCI converted field should ma */
+/* tch DSCP index (from 0 to 63). This index is applied by the following equation: regis */
+/* ter_index*8+octet(or field) index                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_OFFSET ( 0x0000012C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL1_R4                                                                      */
+/* DSCP to TCI Conversion Table 1.  Register 4 that stores conversion code for the follo */
+/* wing DSCP values: 0x20..0x27.    Used for conversion in case of IP untagged packet    */
+/*  The coding of each field is done in the following way:  TCI converted field should m */
+/* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
+/* ster_index*8+octet(or field) index                                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_OFFSET ( 0x00000130 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL1_R5                                                                      */
+/* DSCP to TCI Conversion Table 1.  Register 5 that stores conversion code for the follo */
+/* wing DSCP values: 0x28..0x2f.    Used for conversion in case of IP untagged packet    */
+/*  The coding of each field is done in the following way:  TCI converted field should m */
+/* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
+/* ster_index*8+octet(or field) index                                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_OFFSET ( 0x00000134 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL1_R6                                                                      */
+/* DSCP to TCI Conversion Table 1.  Register 6 that stores conversion code for the follo */
+/* wing DSCP values: 0x30..0x37.    Used for conversion in case of IP untagged packet    */
+/*  The coding of each field is done in the following way:  TCI converted field should m */
+/* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
+/* ster_index*8+octet(or field) index                                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_OFFSET ( 0x00000138 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP2TCI_TBL1_R7                                                                      */
+/* DSCP to TCI Conversion Table 1.  Register 7 that stores conversion code for the follo */
+/* wing DSCP values: 0x3c..0x3f.    Used for conversion in case of IP untagged packet    */
+/*  The coding of each field is done in the following way:  TCI converted field should m */
+/* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
+/* ster_index*8+octet(or field) index                                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV8_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O7_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV7_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O6_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV6_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O5_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV5_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O4_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV4_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O3_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV3_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O2_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV2_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O1_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV1_RSV_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O0_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_OFFSET ( 0x0000013C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7 ;
+#else
+typedef struct
+{
+	/* DSCP_O0 */
+	uint32_t dscp_o0	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O1 */
+	uint32_t dscp_o1	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O2 */
+	uint32_t dscp_o2	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O3 */
+	uint32_t dscp_o3	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv4 */
+	uint32_t rsv4   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O4 */
+	uint32_t dscp_o4	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv5 */
+	uint32_t rsv5   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O5 */
+	uint32_t dscp_o5	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv6 */
+	uint32_t rsv6   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O6 */
+	uint32_t dscp_o6	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv7 */
+	uint32_t rsv7   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_O7 */
+	uint32_t dscp_o7	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv8 */
+	uint32_t rsv8   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7 ;
+#endif
+
+/*****************************************************************************************/
+/* DEFAULT_TCI_TBL0                                                                      */
+/* Default TCI Table 0.  Used for conversion in case of non-IP untagged packet           */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_RSV_RSV_VALUE                     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_DEFAULT_TCI_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_DEFAULT_TCI_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_OFFSET ( 0x00000140 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv        	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DEFAULT_TCI */
+	uint32_t default_tci	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0 ;
+#else
+typedef struct
+{
+	/* DEFAULT_TCI */
+	uint32_t default_tci	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv        	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0 ;
+#endif
+
+/*****************************************************************************************/
+/* DEFAULT_TCI_TBL1                                                                      */
+/* Default TCI Table 1.  Used for conversion in case of non-IP untagged packet           */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_RSV_RSV_VALUE                     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_DEFAULT_TCI_TCI_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_DEFAULT_TCI_TCI_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_OFFSET ( 0x00000144 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv        	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DEFAULT_TCI */
+	uint32_t default_tci	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1 ;
+#else
+typedef struct
+{
+	/* DEFAULT_TCI */
+	uint32_t default_tci	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv        	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1 ;
+#endif
+
+/*****************************************************************************************/
+/* DSCP_TBL_VALID_CFG                                                                    */
+/* Valid configuration of DSCP Tables                                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_RSV_FILTER_CONFIG_VALUE                ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_RSV_FILTER_CONFIG_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL1_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL1_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL1_VALID_VALID_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL0_VALID_NON_VALID_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL0_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL0_VALID_VALID_VALUE                 ( 0x1 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_OFFSET ( 0x00000148 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv       	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TBL1_VALID */
+	uint32_t tbl1_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TBL0_VALID */
+	uint32_t tbl0_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG ;
+#else
+typedef struct
+{
+	/* TBL0_VALID */
+	uint32_t tbl0_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TBL1_VALID */
+	uint32_t tbl1_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv       	: 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT6_VAL_L                                                                        */
+/* Config DA filter6 31:0                                                                */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_OFFSET ( 0x0000014C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L ;
+#else
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT6_VAL_H                                                                        */
+/* Config DA Filter6 47:32                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_OFFSET ( 0x00000150 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H ;
+#else
+typedef struct
+{
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT7_VAL_L                                                                        */
+/* Config DA filter7 31:0                                                                */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_OFFSET ( 0x00000154 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L ;
+#else
+typedef struct
+{
+	/* DA_FILT_LSB */
+	uint32_t da_filt_lsb	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L ;
+#endif
+
+/*****************************************************************************************/
+/* DA_FILT7_VAL_H                                                                        */
+/* Config DA Filter7 47:32                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_OFFSET ( 0x00000158 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H ;
+#else
+typedef struct
+{
+	/* DA_FILT_MSB */
+	uint32_t da_filt_msb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv        	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H ;
+#endif
+
+/*****************************************************************************************/
+/* IPV6_HDR_EXT_FLTR_MASK_CFG                                                            */
+/* IPV6 Header Extension Filter Mask register                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RSV_FILTER_CONFIG_VALUE                 ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RSV_FILTER_CONFIG_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_MASK_VALUE                  ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_MASK_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_UNMASK_VALUE                ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_MASK_VALUE                   ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_MASK_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_UNMASK_VALUE                 ( 0x1 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_MASK_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_MASK_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_UNMASK_VALUE           ( 0x1 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_OFFSET ( 0x0000015C )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv             	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* dest_opt_eh */
+	uint32_t dest_opt_eh     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* routing_eh */
+	uint32_t routing_eh      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* hop_by_hop_match */
+	uint32_t hop_by_hop_match	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG ;
+#else
+typedef struct
+{
+	/* hop_by_hop_match */
+	uint32_t hop_by_hop_match	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* routing_eh */
+	uint32_t routing_eh      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* dest_opt_eh */
+	uint32_t dest_opt_eh     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv             	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* ENG                                                                                   */
+/* Engineering Configuration reserved for Broadlight use                                 */
+/*****************************************************************************************/
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_CFG_RESET_VALUE             ( 0x0 )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_CFG_RESET_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_OFFSET ( 0x00000160 )
+
+#define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_ADDRESS   	( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_ENG_OFFSET )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_READ( r ) 	READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_ENG_ADDRESS ), (r) )
+#define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_WRITE( v )	WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_ENG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* CFG */
+	uint32_t cfg	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_ENG ;
+#else
+typedef struct
+{
+	/* CFG */
+	uint32_t cfg	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION_ENG ;
+#endif
+
+/*****************************************************************************************/
+/* SP2IQ_MAP_CFG                                                                         */
+/* Source Port mapping to IH Ingress Queue num, says per physical port to which IQ it be */
+/* longs (from 0 to 7)                                                                   */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_RNRB_IQ_MAP_MAP_VALUE_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_RNRB_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_RNRA_IQ_MAP_MAP_VALUE_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_RNRA_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_GPON_IQ_MAP_MAP_VALUE_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_GPON_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH4_IQ_MAP_MAP_VALUE_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH4_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH3_IQ_MAP_MAP_VALUE_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH3_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH2_IQ_MAP_MAP_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH2_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH1_IQ_MAP_MAP_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH1_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH0_IQ_MAP_MAP_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH0_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_OFFSET ( 0x00000000 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RNRB_IQ_MAP */
+	uint32_t rnrb_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_IQ_MAP */
+	uint32_t rnra_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_IQ_MAP */
+	uint32_t gpon_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_IQ_MAP */
+	uint32_t eth4_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_IQ_MAP */
+	uint32_t eth3_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_IQ_MAP */
+	uint32_t eth2_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_IQ_MAP */
+	uint32_t eth1_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH0_IQ_MAP */
+	uint32_t eth0_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG ;
+#else
+typedef struct
+{
+	/* ETH0_IQ_MAP */
+	uint32_t eth0_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_IQ_MAP */
+	uint32_t eth1_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_IQ_MAP */
+	uint32_t eth2_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_IQ_MAP */
+	uint32_t eth3_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_IQ_MAP */
+	uint32_t eth4_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_IQ_MAP */
+	uint32_t gpon_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_IQ_MAP */
+	uint32_t rnra_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_IQ_MAP */
+	uint32_t rnrb_iq_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IQ_BASE_CFG                                                                           */
+/* Base location of each Ingres Queue in 16-entry IQ array.  Note: this configuration sh */
+/* ould be aligned with configuration of IQ size.    Default configuration of IQ array:  */
+/*    IQ#  Port   Num of Ingres Buffers  ==================================  0  : Eth0 : */
+/*     2   1  : Eth1 :    2   2  : Eth2 :    2   3  : Eth3 :    2   4  : Eth4 :    2  5  */
+/*  : GPON :    4  6  : RNRA :    1  7  : RNRB :    1                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ7_BASE_BASE_VALUE_VALUE             ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ7_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ6_BASE_BASE_VALUE_VALUE             ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ6_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ5_BASE_BASE_VALUE_VALUE             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ5_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ4_BASE_BASE_VALUE_VALUE             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ4_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ3_BASE_BASE_VALUE_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ3_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ2_BASE_BASE_VALUE_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ2_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ1_BASE_BASE_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ1_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ0_BASE_BASE_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ0_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_OFFSET ( 0x00000004 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IQ7_BASE */
+	uint32_t iq7_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_BASE */
+	uint32_t iq6_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_BASE */
+	uint32_t iq5_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_BASE */
+	uint32_t iq4_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_BASE */
+	uint32_t iq3_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_BASE */
+	uint32_t iq2_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_BASE */
+	uint32_t iq1_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ0_BASE */
+	uint32_t iq0_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG ;
+#else
+typedef struct
+{
+	/* IQ0_BASE */
+	uint32_t iq0_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_BASE */
+	uint32_t iq1_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_BASE */
+	uint32_t iq2_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_BASE */
+	uint32_t iq3_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_BASE */
+	uint32_t iq4_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_BASE */
+	uint32_t iq5_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_BASE */
+	uint32_t iq6_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ7_BASE */
+	uint32_t iq7_base	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IQ_SIZE_CFG                                                                           */
+/* Size (= num of ingress buffers) per each Ingres Queue in 16-entry IQ array.    Note:  */
+/* this configuration should be aligned with configuration of IQ base.  Total num of ent */
+/* eties should be <= 16  Note: value 0x0 means that number of entries is sixteen!!    D */
+/* efault configuration of IQ array:    IQ#  Port   Num of Ingres Buffers  ============= */
+/* =====================  0  : Eth0 :    2   1  : Eth1 :    2   2  : Eth2 :    2   3  :  */
+/* Eth3 :    2   4  : Eth4 :    2  5  : GPON :    4  6  : RNRA :    1  7  : RNRB :    1  */
+/*                                                                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ7_SIZE_SIZE_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ7_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ6_SIZE_SIZE_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ6_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ5_SIZE_SIZE_VALUE_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ5_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ4_SIZE_SIZE_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ4_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ3_SIZE_SIZE_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ3_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ2_SIZE_SIZE_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ2_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ1_SIZE_SIZE_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ1_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ0_SIZE_SIZE_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ0_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x2 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_OFFSET ( 0x00000008 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IQ7_SIZE */
+	uint32_t iq7_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_SIZE */
+	uint32_t iq6_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_SIZE */
+	uint32_t iq5_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_SIZE */
+	uint32_t iq4_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_SIZE */
+	uint32_t iq3_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_SIZE */
+	uint32_t iq2_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_SIZE */
+	uint32_t iq1_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ0_SIZE */
+	uint32_t iq0_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG ;
+#else
+typedef struct
+{
+	/* IQ0_SIZE */
+	uint32_t iq0_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_SIZE */
+	uint32_t iq1_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_SIZE */
+	uint32_t iq2_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_SIZE */
+	uint32_t iq3_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_SIZE */
+	uint32_t iq4_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_SIZE */
+	uint32_t iq5_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_SIZE */
+	uint32_t iq6_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ7_SIZE */
+	uint32_t iq7_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IQL_PRIOR_CFG                                                                         */
+/* Priority of each Ingres Queues [3...0].    Note: this configuration defined by one ho */
+/* t (8 bits max)    Default configuration of IQ array:    IQ#  Port   Priority  ======= */
+/* ===========================  0  : Eth0 :    8b010   1  : Eth1 :    8b010   2  : Eth2  */
+/* :    8b010   3  : Eth3 :    8b010   4  : Eth4 :    8b010  5  : GPON :    8b100  6  :  */
+/* RNRA :    8b001  7  : RNRB :    8b001                                                 */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ3_PRIOR_PRIOR_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ3_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ2_PRIOR_PRIOR_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ2_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ1_PRIOR_PRIOR_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ1_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ0_PRIOR_PRIOR_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ0_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x2 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_OFFSET ( 0x0000000C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IQ3_PRIOR */
+	uint32_t iq3_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_PRIOR */
+	uint32_t iq2_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_PRIOR */
+	uint32_t iq1_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ0_PRIOR */
+	uint32_t iq0_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG ;
+#else
+typedef struct
+{
+	/* IQ0_PRIOR */
+	uint32_t iq0_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_PRIOR */
+	uint32_t iq1_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_PRIOR */
+	uint32_t iq2_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_PRIOR */
+	uint32_t iq3_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IQH_PRIOR_CFG                                                                         */
+/* Priority of each Ingres Queues [7...4].    Note: this configuration defined by one ho */
+/* t (8 bits max)    Default configuration of IQ array:    IQ#  Port   Priority  ======= */
+/* ===========================  0  : Eth0 :    8b010   1  : Eth1 :    8b010   2  : Eth2  */
+/* :    8b010   3  : Eth3 :    8b010   4  : Eth4 :    8b010  5  : GPON :    8b100  6  :  */
+/* RNRA :    8b001  7  : RNRB :    8b001                                                 */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ7_PRIOR_PRIOR_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ7_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ6_PRIOR_PRIOR_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ6_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ5_PRIOR_PRIOR_VALUE_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ5_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ4_PRIOR_PRIOR_VALUE_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ4_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x2 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_OFFSET ( 0x00000010 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IQ7_PRIOR */
+	uint32_t iq7_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_PRIOR */
+	uint32_t iq6_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_PRIOR */
+	uint32_t iq5_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_PRIOR */
+	uint32_t iq4_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG ;
+#else
+typedef struct
+{
+	/* IQ4_PRIOR */
+	uint32_t iq4_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_PRIOR */
+	uint32_t iq5_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_PRIOR */
+	uint32_t iq6_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ7_PRIOR */
+	uint32_t iq7_prior	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* PHL_OFFSET_CFG                                                                        */
+/* Packet Header offset per Ingres Physical port in byte resolution    Note: this config */
+/* uration says where the Header of packet is started. This configuration is used both b */
+/* y Parser and by Egress Queue DMA. The motivation: store room in the beginning of Runn */
+/* er Buffer for FW    Default configuration of Packet Header offset is 0x0.             */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV4_RSV_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV4_RSV_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH3_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH3_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV3_RSV_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV3_RSV_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH2_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH2_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV2_RSV_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV2_RSV_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH1_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH1_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV1_RSV_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV1_RSV_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH0_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH0_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_OFFSET ( 0x00000014 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV4 */
+	uint32_t rsv4          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_PH_OFFSET */
+	uint32_t eth3_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV3 */
+	uint32_t rsv3          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_PH_OFFSET */
+	uint32_t eth2_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_PH_OFFSET */
+	uint32_t eth1_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t rsv1          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH0_PH_OFFSET */
+	uint32_t eth0_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG ;
+#else
+typedef struct
+{
+	/* ETH0_PH_OFFSET */
+	uint32_t eth0_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t rsv1          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_PH_OFFSET */
+	uint32_t eth1_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_PH_OFFSET */
+	uint32_t eth2_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV3 */
+	uint32_t rsv3          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_PH_OFFSET */
+	uint32_t eth3_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV4 */
+	uint32_t rsv4          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* PHH_OFFSET_CFG                                                                        */
+/* Packet Header offset per Ingres Physical port in byte resolution    Note: this config */
+/* uration says where the Header of packet is started. This configuration is used both b */
+/* y Parser and by Egress Queue DMA. The motivation: store room in the beginning of Runn */
+/* er Buffer for FW    Default configuration of Packet Header offset is 0x0.             */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV4_RSV_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV4_RSV_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RNRB_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RNRB_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV3_RSV_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV3_RSV_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RNRA_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RNRA_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV2_RSV_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV2_RSV_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_GPON_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_GPON_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV1_RSV_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV1_RSV_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_ETH4_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_ETH4_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_OFFSET ( 0x00000018 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV4 */
+	uint32_t rsv4          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_PH_OFFSET */
+	uint32_t rnrb_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV3 */
+	uint32_t rsv3          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_PH_OFFSET */
+	uint32_t rnra_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_PH_OFFSET */
+	uint32_t gpon_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t rsv1          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_PH_OFFSET */
+	uint32_t eth4_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG ;
+#else
+typedef struct
+{
+	/* ETH4_PH_OFFSET */
+	uint32_t eth4_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t rsv1          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_PH_OFFSET */
+	uint32_t gpon_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_PH_OFFSET */
+	uint32_t rnra_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV3 */
+	uint32_t rsv3          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_PH_OFFSET */
+	uint32_t rnrb_ph_offset	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV4 */
+	uint32_t rsv4          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IQ_WEIGHT_CFG                                                                         */
+/* Weight Arbiration of each Ingres Queue     Note: this configuration has a meaning oly */
+/*  for two or more  queus with the same priority     Default configuration of IQ array: */
+/*     IQ#  Port   Weight  ==================================  0  : Eth0 :    1   1  : E */
+/* th1 :    1   2  : Eth2 :    1   3  : Eth3 :    1   4  : Eth4 :    1  5  : GPON :    1 */
+/*   6  : RNRA :    1  7  : RNRB :    1                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ7_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ7_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ6_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ6_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ5_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ5_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ4_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ4_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ3_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ3_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ2_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ2_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ1_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ1_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ0_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ0_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_OFFSET ( 0x00000020 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IQ7_WEIGHT */
+	uint32_t iq7_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_WEIGHT */
+	uint32_t iq6_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_WEIGHT */
+	uint32_t iq5_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_WEIGHT */
+	uint32_t iq4_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_WEIGHT */
+	uint32_t iq3_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_WEIGHT */
+	uint32_t iq2_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_WEIGHT */
+	uint32_t iq1_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ0_WEIGHT */
+	uint32_t iq0_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG ;
+#else
+typedef struct
+{
+	/* IQ0_WEIGHT */
+	uint32_t iq0_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_WEIGHT */
+	uint32_t iq1_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_WEIGHT */
+	uint32_t iq2_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_WEIGHT */
+	uint32_t iq3_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_WEIGHT */
+	uint32_t iq4_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_WEIGHT */
+	uint32_t iq5_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_WEIGHT */
+	uint32_t iq6_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ7_WEIGHT */
+	uint32_t iq7_weight	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IQL_CNGS_THRS_CFG                                                                     */
+/* Ingres  congestion threshold of Low Ingres Queues[ 3...0].     When the number of tot */
+/* al Runner Buffers (eigher Runner A or Runner B) reachs the defined threshold per queu */
+/* e  - Ingres Handler stops serving this queue till one of two events will occur:  (1)  */
+/* num of Runner buffers is decreased down to threshold  (2) one of BBH clients that ass */
+/* igned to the queue will get Service Enable message initiated in appropriate MAC (by r */
+/* eaching predefined threshold in Data FIFO).    Note: this configuration should be ali */
+/* gned with a threshold of max runner buffers (per each Runner)    Default configuratio */
+/* n of IQ array (always allow servecing, do not stop on ingress congestion):    IQ#  Po */
+/* rt   Priority  ==================================  0  : Eth0 :   32   1  : Eth1 :   3 */
+/* 2    2  : Eth2 :   32    3  : Eth3 :   32    4  : Eth4 :   32   5  : GPON :   32   6  */
+/*  : RNRA :   32   7  : RNRB :   32                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV4_RSV_VALUE                                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV4_RSV_VALUE_RESET_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ3_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ3_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV3_RSV_VALUE                                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV3_RSV_VALUE_RESET_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ2_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ2_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV2_RSV_VALUE                                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV2_RSV_VALUE_RESET_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ1_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ1_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV1_RSV_VALUE                                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV1_RSV_VALUE_RESET_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ0_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ0_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_OFFSET ( 0x00000024 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV4 */
+	uint32_t rsv4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_CNGS_THRS */
+	uint32_t iq3_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV3 */
+	uint32_t rsv3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_CNGS_THRS */
+	uint32_t iq2_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_CNGS_THRS */
+	uint32_t iq1_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ0_CNGS_THRS */
+	uint32_t iq0_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG ;
+#else
+typedef struct
+{
+	/* IQ0_CNGS_THRS */
+	uint32_t iq0_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_CNGS_THRS */
+	uint32_t iq1_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_CNGS_THRS */
+	uint32_t iq2_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV3 */
+	uint32_t rsv3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_CNGS_THRS */
+	uint32_t iq3_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV4 */
+	uint32_t rsv4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IQH_CNGS_THRS_CFG                                                                     */
+/* Ingres  congestion threshold of Low Ingres Queues[ 7...4].     When the number of tot */
+/* al Runner Buffers (eigher Runner A or Runner B) reachs the defined threshold per queu */
+/* e  - Ingres Handler stops serving this queue till one of two events will occur:  (1)  */
+/* num of Runner buffers is decreased down to threshold  (2) one of BBH clients that ass */
+/* igned to the queue will get Service Enable message initiated in appropriate MAC (by r */
+/* eaching predefined threshold in Data FIFO).    Note: this configuration should be ali */
+/* gned with a threshold of max runner buffers (per each Runner)    Default configuratio */
+/* n of IQ array (always allow servecing, do not stop on ingress congestion):    IQ#  Po */
+/* rt   Priority  ==================================  0  : Eth0 :   32   1  : Eth1 :   3 */
+/* 2    2  : Eth2 :   32    3  : Eth3 :   32    4  : Eth4 :   32   5  : GPON :   32   6  */
+/*  : RNRA :   32   7  : RNRB :   32                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV4_RSV_VALUE                                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV4_RSV_VALUE_RESET_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ7_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ7_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV3_RSV_VALUE                                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV3_RSV_VALUE_RESET_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ6_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ6_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV2_RSV_VALUE                                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV2_RSV_VALUE_RESET_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ5_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ5_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV1_RSV_VALUE                                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV1_RSV_VALUE_RESET_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ4_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ4_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_OFFSET ( 0x00000028 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV4 */
+	uint32_t rsv4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ7_CNGS_THRS */
+	uint32_t iq7_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV3 */
+	uint32_t rsv3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_CNGS_THRS */
+	uint32_t iq6_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_CNGS_THRS */
+	uint32_t iq5_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_CNGS_THRS */
+	uint32_t iq4_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG ;
+#else
+typedef struct
+{
+	/* IQ4_CNGS_THRS */
+	uint32_t iq4_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_CNGS_THRS */
+	uint32_t iq5_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_CNGS_THRS */
+	uint32_t iq6_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV3 */
+	uint32_t rsv3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ7_CNGS_THRS */
+	uint32_t iq7_cngs_thrs	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV4 */
+	uint32_t rsv4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* RNRA_RB_BASE                                                                          */
+/* Base Address of Runner Buffers sending for Runner A     The major part of Runner Buff */
+/* ers are managed by Ingres Handler per Runner.  The number of Runner Buffers is define */
+/* d per Runner, max number of managed buffers is 64; default is 32    However there are */
+/*  assigned Runner Buffers managed by Runner itself (FW pipe), the number of assigned n */
+/* on-managed Runner Buffer is up to FW control(up to 4 RIBs)  The base address of assig */
+/* ned buffers is different from the common managed buffers.    Each Runner Buffer has o */
+/* ffset of 0x32 according to its on number.     Note: Default configuration of base add */
+/* ress is 0x0.                                                                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_RNRA_ASIGNED_RB_BASE_BASE_ADDRESS_OFFSET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_RNRA_ASIGNED_RB_BASE_BASE_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_RNRA_COMMON_RB_BASE_BASE_ADDRESS_OFFSET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_RNRA_COMMON_RB_BASE_BASE_ADDRESS_OFFSET_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_OFFSET ( 0x00000030 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RNRA_ASIGNED_RB_BASE */
+	uint32_t rnra_asigned_rb_base	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_COMMON_RB_BASE */
+	uint32_t rnra_common_rb_base 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE ;
+#else
+typedef struct
+{
+	/* RNRA_COMMON_RB_BASE */
+	uint32_t rnra_common_rb_base 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_ASIGNED_RB_BASE */
+	uint32_t rnra_asigned_rb_base	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE ;
+#endif
+
+/*****************************************************************************************/
+/* RNRB_RB_BASE                                                                          */
+/* Base Address of Runner Buffers sending for Runner B     The major part of Runner Buff */
+/* ers are managed by Ingres Handler per Runner.  The number of Runner Buffers is define */
+/* d per Runner, max number of managed buffers is 64; default is 32    However there are */
+/*  assigned Runner Buffers managed by Runner itself (FW pipe), the number of assigned n */
+/* on-managed Runner Buffer is up to FW control(up to 4 RIBs)  The base address of assig */
+/* ned buffers is different from the common managed buffers.    Each Runner Buffer has o */
+/* ffset of 0x32 according to its on number.     Note: Default configuration of base add */
+/* ress is 0x0.                                                                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_RNRB_ASIGNED_RB_BASE_BASE_ADDRESS_OFFSET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_RNRB_ASIGNED_RB_BASE_BASE_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_RNRB_COMMON_RB_BASE_BASE_ADDRESS_OFFSET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_RNRB_COMMON_RB_BASE_BASE_ADDRESS_OFFSET_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_OFFSET ( 0x00000034 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RNRB_ASIGNED_RB_BASE */
+	uint32_t rnrb_asigned_rb_base	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_COMMON_RB_BASE */
+	uint32_t rnrb_common_rb_base 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE ;
+#else
+typedef struct
+{
+	/* RNRB_COMMON_RB_BASE */
+	uint32_t rnrb_common_rb_base 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_ASIGNED_RB_BASE */
+	uint32_t rnrb_asigned_rb_base	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE ;
+#endif
+
+/*****************************************************************************************/
+/* RNRA_IHRSP_ADDR                                                                       */
+/* Address of IH response for Runner A     The content of IH Response is defined in chap */
+/* ter 3.1.3.15 in strpublicLilacArchTMIHmicro_archLilac_IH_LLD_v0.5.doc                 */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_RSV_RSV_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_RSV_RSV_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_RNRA_IHRSP_ADDR_ADDRESS_OFFSET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_RNRA_IHRSP_ADDR_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_OFFSET ( 0x00000038 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv            	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_IHRSP_ADDR */
+	uint32_t rnra_ihrsp_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR ;
+#else
+typedef struct
+{
+	/* RNRA_IHRSP_ADDR */
+	uint32_t rnra_ihrsp_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv            	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR ;
+#endif
+
+/*****************************************************************************************/
+/* RNRB_IHRSP_ADDR                                                                       */
+/* Address of IH response for Runner B     The content of IH Response is defined in chap */
+/* ter 3.1.3.15 in strpublicLilacArchTMIHmicro_archLilac_IH_LLD_v0.5.doc                 */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_RSV_RSV_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_RSV_RSV_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_RNRB_IHRSP_ADDR_ADDRESS_OFFSET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_RNRB_IHRSP_ADDR_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_OFFSET ( 0x0000003C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv            	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_IHRSP_ADDR */
+	uint32_t rnrb_ihrsp_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR ;
+#else
+typedef struct
+{
+	/* RNRB_IHRSP_ADDR */
+	uint32_t rnrb_ihrsp_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv            	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR ;
+#endif
+
+/*****************************************************************************************/
+/* RNRA_CNGS_RPT_ADDR                                                                    */
+/* Address of IH congestion report for Runner A     IH sends the total number of the Run */
+/* ner when the congestion state is changed.    Default address is 0x0                   */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_RSV_RSV_VALUE                                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_RSV_RSV_VALUE_RESET_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_RNRA_CNGS_RPT_ADDR_ADDRESS_OFFSET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_RNRA_CNGS_RPT_ADDR_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_OFFSET ( 0x00000040 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_CNGS_RPT_ADDR */
+	uint32_t rnra_cngs_rpt_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR ;
+#else
+typedef struct
+{
+	/* RNRA_CNGS_RPT_ADDR */
+	uint32_t rnra_cngs_rpt_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR ;
+#endif
+
+/*****************************************************************************************/
+/* RNRB_CNGS_RPT_ADDR                                                                    */
+/* Address of IH congestion report for Runner B     IH sends the total number of the Run */
+/* ner when the congestion state is changed.    Default address is 0x0                   */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_RSV_RSV_VALUE                                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_RSV_RSV_VALUE_RESET_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_RNRB_CNGS_RPT_ADDR_ADDRESS_OFFSET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_RNRB_CNGS_RPT_ADDR_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_OFFSET ( 0x00000044 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_CNGS_RPT_ADDR */
+	uint32_t rnrb_cngs_rpt_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR ;
+#else
+typedef struct
+{
+	/* RNRB_CNGS_RPT_ADDR */
+	uint32_t rnrb_cngs_rpt_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR ;
+#endif
+
+/*****************************************************************************************/
+/* RNR_CNGS_RPT_CFG                                                                      */
+/* Enable of sending Congestion Report per each Runner.    IH sends the total number of  */
+/* the Runner when the congestion state is changed. The sending of this report is upon t */
+/* o enabled per Runner.    Default address is 0x0 (not to send report)                  */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_THRESHOLD_DISABLE_DIS_CNGS_RPT_SEND_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_THRESHOLD_DISABLE_DIS_CNGS_RPT_SEND_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_THRESHOLD_DISABLE_EN_CNGS_RPT_SEND_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RSV_RSV_VALUE                                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RSV_RSV_VALUE_RESET_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRB_CNGS_RPT_EN_DIS_CNGS_RPT_SEND_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRB_CNGS_RPT_EN_DIS_CNGS_RPT_SEND_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRB_CNGS_RPT_EN_EN_CNGS_RPT_SEND_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRA_CNGS_RPT_EN_DIS_CNGS_RPT_SEND_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRA_CNGS_RPT_EN_DIS_CNGS_RPT_SEND_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRA_CNGS_RPT_EN_EN_CNGS_RPT_SEND_VALUE               ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_OFFSET ( 0x00000048 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* THRESHOLD_DISABLE */
+	uint32_t threshold_disable	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv              	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_CNGS_RPT_EN */
+	uint32_t rnrb_cngs_rpt_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_CNGS_RPT_EN */
+	uint32_t rnra_cngs_rpt_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG ;
+#else
+typedef struct
+{
+	/* RNRA_CNGS_RPT_EN */
+	uint32_t rnra_cngs_rpt_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_CNGS_RPT_EN */
+	uint32_t rnrb_cngs_rpt_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv              	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THRESHOLD_DISABLE */
+	uint32_t threshold_disable	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* RADDR0_CFG                                                                            */
+/* Route Addres configuration of following ports: Eth0, Eth1, Eth2, Eth3.    Used for br */
+/* oadbus access for the following ports: for sending responses, message and data.       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV4_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV4_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH3_RADDR_ROUTE_ADDRESS_VALUE             ( 0x48 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH3_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x48 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV3_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV3_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH2_RADDR_ROUTE_ADDRESS_VALUE             ( 0x54 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH2_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x54 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH1_RADDR_ROUTE_ADDRESS_VALUE             ( 0x4C )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH1_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x4C )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV1_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV1_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH0_RADDR_ROUTE_ADDRESS_VALUE             ( 0x5C )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH0_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x5C )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_OFFSET ( 0x0000004C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV4 */
+	uint32_t rsv4      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_RADDR */
+	uint32_t eth3_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_RADDR */
+	uint32_t eth2_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_RADDR */
+	uint32_t eth1_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH0_RADDR */
+	uint32_t eth0_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG ;
+#else
+typedef struct
+{
+	/* ETH0_RADDR */
+	uint32_t eth0_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_RADDR */
+	uint32_t eth1_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_RADDR */
+	uint32_t eth2_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_RADDR */
+	uint32_t eth3_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV4 */
+	uint32_t rsv4      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* RADDR1_CFG                                                                            */
+/* Route Addres configuration of following ports: Eth4, GPON, Runner A, Runner B    Used */
+/*  for broadbus access for the following ports: for sending responses, message and data */
+/* .                                                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV4_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV4_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RNRB_RADDR_ROUTE_ADDRESS_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RNRB_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV3_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV3_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RNRA_RADDR_ROUTE_ADDRESS_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RNRA_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_GPON_RADDR_ROUTE_ADDRESS_VALUE             ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_GPON_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV1_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV1_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_ETH4_RADDR_ROUTE_ADDRESS_VALUE             ( 0x50 )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_ETH4_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x50 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_OFFSET ( 0x00000050 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV4 */
+	uint32_t rsv4      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_RADDR */
+	uint32_t rnrb_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_RADDR */
+	uint32_t rnra_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_RADDR */
+	uint32_t gpon_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_RADDR */
+	uint32_t eth4_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG ;
+#else
+typedef struct
+{
+	/* ETH4_RADDR */
+	uint32_t eth4_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_RADDR */
+	uint32_t gpon_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_RADDR */
+	uint32_t rnra_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_RADDR */
+	uint32_t rnrb_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV4 */
+	uint32_t rsv4      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* RBPM_BAT_CFG                                                                          */
+/* Runner Buffer Allocation Threshold (per Runner)    IH manages pool of common Runner B */
+/* uffers per each Runner. The maximal number of buffers is defined by the following opt */
+/* ions:  0x0 - 16 max buffers  0x1 - 24 max buffers  0x2 - 32 max buffers  0x3 - 48 max */
+/*  buffers  0x4 - 64 max buffers    Default is 0x0 (32 buffers)                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RSV2_RSV_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RSV2_RSV_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_16_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_24_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_32_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_32_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_48_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_64_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RSV1_RSV_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RSV1_RSV_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_16_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_24_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_32_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_32_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_48_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_64_VALUE             ( 0x4 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_OFFSET ( 0x00000054 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2        	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_BPM_BAT */
+	uint32_t rnrb_bpm_bat	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_BPM_BAT */
+	uint32_t rnra_bpm_bat	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG ;
+#else
+typedef struct
+{
+	/* RNRA_BPM_BAT */
+	uint32_t rnra_bpm_bat	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t rsv1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_BPM_BAT */
+	uint32_t rnrb_bpm_bat	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2        	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* RBPM_BAC_STAT                                                                         */
+/* Runner Buffer Allocated Counter (per Runner) - represents the status of allocated buf */
+/* fers at moment of read access to register    Background:  IH manages pool of common R */
+/* unner Buffers per each Runner. The maximal number of buffers is defined by the follow */
+/* ing options:  0x0 - 16 max buffers  0x1 - 24 max buffers  0x2 - 32 max buffers  0x3 - */
+/*  48 max buffers  0x4 - 64 max buffers    Default is 0x0 (no buffers)                  */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RSV2_RSV_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RSV2_RSV_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RNRB_BPM_BAC_BAC_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RNRB_BPM_BAC_BAC_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RNRA_BPM_BAC_BAC_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RNRA_BPM_BAC_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_OFFSET ( 0x00000058 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv2 */
+	uint32_t rsv2        	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_BPM_BAC */
+	uint32_t rnrb_bpm_bac	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_BPM_BAC */
+	uint32_t rnra_bpm_bac	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT ;
+#else
+typedef struct
+{
+	/* RNRA_BPM_BAC */
+	uint32_t rnra_bpm_bac	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_BPM_BAC */
+	uint32_t rnrb_bpm_bac	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2        	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT ;
+#endif
+
+/*****************************************************************************************/
+/* TRGT_MTRX_ETH0_SP_CFG                                                                 */
+/* Target matrix configuration for Source Port Eth0    Used for decision on Target memor */
+/* y and Local switch as function of extracted destination port that can be as following */
+/* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe  - Multicast (MC)  - CPU  - */
+/*  Always DDR (relevant for local switch info)  - Always SRAM(relevant for local switch */
+/*  info)                                                                                */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_OFFSET ( 0x0000005C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* TRGT_MTRX_ETH1_SP_CFG                                                                 */
+/* Target matrix configuration for Source Port Eth1    Used for decision on Target memor */
+/* y and Local switch as function of extracted destination port that can be as following */
+/* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU */
+/*   - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local swi */
+/* tch info)  -Spare                                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_OFFSET ( 0x00000060 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* TRGT_MTRX_ETH2_SP_CFG                                                                 */
+/* Target matrix configuration for Source Port Eth2    Used for decision on Target memor */
+/* y and Local switch as function of extracted destination port that can be as following */
+/* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU */
+/*   - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local swi */
+/* tch info)  -Spare                                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_OFFSET ( 0x00000064 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* TRGT_MTRX_ETH3_SP_CFG                                                                 */
+/* Target matrix configuration for Source Port Eth3    Used for decision on Target memor */
+/* y and Local switch as function of extracted destination port that can be as following */
+/* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU */
+/*   - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local swi */
+/* tch info)  -Spare                                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_OFFSET ( 0x00000068 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* TRGT_MTRX_ETH4_SP_CFG                                                                 */
+/* Target matrix configuration for Source Port Eth4    Used for decision on Target memor */
+/* y and Local switch as function of extracted destination port that can be as following */
+/* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU */
+/*   - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local swi */
+/* tch info)  -Spare                                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_OFFSET ( 0x0000006C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* TRGT_MTRX_GPON_SP_CFG                                                                 */
+/* Target matrix configuration for Source Port GPON    Used for decision on Target memor */
+/* y and Local switch as function of extracted destination port that can be as following */
+/* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU */
+/*   - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local swi */
+/* tch info)  -Spare                                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_OFFSET ( 0x00000070 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_MISC_CFG                                                                           */
+/* Ingres handler Miscellenous Control:    - Look-up enable in Direct Mode  - Serail Num */
+/* ber stamping enable for Short Packets                                                 */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_RSV_RSV_VALUE                                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_RSV_RSV_VALUE_RESET_VALUE                                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_NVAL_CAM_SEARCH_EN_DIS_SEARCH_IN_CAM_AFTER_INVAL_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_NVAL_CAM_SEARCH_EN_DIS_SEARCH_IN_CAM_AFTER_INVAL_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_NVAL_CAM_SEARCH_EN_EN_SEARCH_IN_CAM_AFTER_INVAL_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_CNGS_DSCRD_DIS_CNGS_DISCARD_EN_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_CNGS_DSCRD_DIS_CNGS_DISCARD_EN_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_CNGS_DSCRD_DIS_CNGS_DISCARD_DIS_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_HLENGTH_MIN_TRSH_HLENGTH_MIN_TRSH_VAL_VALUE                        ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_HLENGTH_MIN_TRSH_HLENGTH_MIN_TRSH_VAL_VALUE_RESET_VALUE            ( 0x40 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_SN_STAMP_DM_PKT_DIS_STAMPING_SN_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_SN_STAMP_DM_PKT_DIS_STAMPING_SN_VALUE_RESET_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_SN_STAMP_DM_PKT_EN_STAMPING_SN_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_LUT_EN_DIRECT_MODE_DISABLE_LOOKUP_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_LUT_EN_DIRECT_MODE_ENABLE_LOOKUP_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_LUT_EN_DIRECT_MODE_ENABLE_LOOKUP_VALUE_RESET_VALUE                 ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_OFFSET ( 0x00000074 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* NVAL_CAM_SEARCH_EN */
+	uint32_t nval_cam_search_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CNGS_DSCRD_DIS */
+	uint32_t cngs_dscrd_dis    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HLENGTH_MIN_TRSH */
+	uint32_t hlength_min_trsh  	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_STAMP_DM_PKT */
+	uint32_t sn_stamp_dm_pkt   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LUT_EN_DIRECT_MODE */
+	uint32_t lut_en_direct_mode	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG ;
+#else
+typedef struct
+{
+	/* LUT_EN_DIRECT_MODE */
+	uint32_t lut_en_direct_mode	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_STAMP_DM_PKT */
+	uint32_t sn_stamp_dm_pkt   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HLENGTH_MIN_TRSH */
+	uint32_t hlength_min_trsh  	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CNGS_DSCRD_DIS */
+	uint32_t cngs_dscrd_dis    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* NVAL_CAM_SEARCH_EN */
+	uint32_t nval_cam_search_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY0                                                                         */
+/* IH Class - Key0 configuration    Note: used for IH class identification by Parser Cla */
+/* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
+/* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
+/* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
+/* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
+/* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_OFFSET ( 0x00000078 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY1                                                                         */
+/* IH Class - Key1 configuration    Note: used for IH class identification by Parser Cla */
+/* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
+/* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
+/* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
+/* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
+/* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_OFFSET ( 0x0000007C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY2                                                                         */
+/* IH Class - Key2 configuration    Note: used for IH class identification by Parser Cla */
+/* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
+/* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
+/* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
+/* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
+/* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_OFFSET ( 0x00000080 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY3                                                                         */
+/* IH Class - Key3 configuration    Note: used for IH class identification by Parser Cla */
+/* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
+/* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
+/* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
+/* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
+/* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_OFFSET ( 0x00000084 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY4                                                                         */
+/* IH Class - Key4 configuration    Note: used for IH class identification by Parser Cla */
+/* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
+/* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
+/* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
+/* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
+/* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_OFFSET ( 0x00000088 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY5                                                                         */
+/* IH Class - Key5 configuration    Note: used for IH class identification by Parser Cla */
+/* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
+/* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
+/* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
+/* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
+/* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_OFFSET ( 0x0000008C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY6                                                                         */
+/* IH Class - Key6 configuration    Note: used for IH class identification by Parser Cla */
+/* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
+/* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
+/* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
+/* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
+/* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_OFFSET ( 0x00000090 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY7                                                                         */
+/* IH Class - Key7 configuration    Note: used for IH class identification by Parser Cla */
+/* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
+/* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
+/* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
+/* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
+/* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_OFFSET ( 0x00000094 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY8                                                                         */
+/* IH Class - Key8 configuration    Note: used for IH class identification by Parser Cla */
+/* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
+/* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
+/* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
+/* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
+/* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_OFFSET ( 0x00000098 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY9                                                                         */
+/* IH Class - Key9 configuration    Note: used for IH class identification by Parser Cla */
+/* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
+/* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
+/* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
+/* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
+/* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_OFFSET ( 0x0000009C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY10                                                                        */
+/* IH Class - Key10 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_OFFSET ( 0x00000100 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY11                                                                        */
+/* IH Class - Key11 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_OFFSET ( 0x00000104 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY12                                                                        */
+/* IH Class - Key12 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_OFFSET ( 0x00000108 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY13                                                                        */
+/* IH Class - Key13 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_OFFSET ( 0x0000010C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY14                                                                        */
+/* IH Class - Key14 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_OFFSET ( 0x00000110 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_KEY15                                                                        */
+/* IH Class - Key15 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_OFFSET ( 0x00000114 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_L2 */
+	uint32_t ih_class_key_l2        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L3 */
+	uint32_t ih_class_key_l3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_L4 */
+	uint32_t ih_class_key_l4        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_FLTR */
+	uint32_t ih_class_key_da_fltr   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_DA_ANYHIT */
+	uint32_t ih_class_key_da_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_MC_FLTR */
+	uint32_t ih_class_key_mc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_BC_FLTR */
+	uint32_t ih_class_key_bc_fltr   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_FLTR */
+	uint32_t ih_class_key_vid_fltr  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_VID_ANYHIT */
+	uint32_t ih_class_key_vid_anyhit	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_FLTR */
+	uint32_t ih_class_key_ip_fltr   	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_IP_ANYHIT */
+	uint32_t ih_class_key_ip_anyhit 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_WAN_FLTR */
+	uint32_t ih_class_key_wan_fltr  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_5TPL_FLTR */
+	uint32_t ih_class_key_5tpl_fltr 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_SP */
+	uint32_t ih_class_key_sp        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY_ERR */
+	uint32_t ih_class_key_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK0                                                                        */
+/* IH Class - Mask0 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_OFFSET ( 0x00000118 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK1                                                                        */
+/* IH Class - Mask1 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_OFFSET ( 0x0000011C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK2                                                                        */
+/* IH Class - Mask2 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_OFFSET ( 0x00000120 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK3                                                                        */
+/* IH Class - Mask3 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_OFFSET ( 0x00000124 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK4                                                                        */
+/* IH Class - Mask4 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_OFFSET ( 0x00000128 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK5                                                                        */
+/* IH Class - Mask5 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_OFFSET ( 0x0000012C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK6                                                                        */
+/* IH Class - Mask6 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_OFFSET ( 0x00000130 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK7                                                                        */
+/* IH Class - Mask7 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_OFFSET ( 0x00000134 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK8                                                                        */
+/* IH Class - Mask8 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_OFFSET ( 0x00000138 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK9                                                                        */
+/* IH Class - Mask9 configuration    Note: used for IH class identification by Parser Cl */
+/* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
+/* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
+/* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
+/* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
+/* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_OFFSET ( 0x0000013C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK10                                                                       */
+/* IH Class - Mask10 configuration    Note: used for IH class identification by Parser C */
+/* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
+/*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
+/*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
+/* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
+/*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_OFFSET ( 0x00000140 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK11                                                                       */
+/* IH Class - Mask11 configuration    Note: used for IH class identification by Parser C */
+/* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
+/*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
+/*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
+/* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
+/*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_OFFSET ( 0x00000144 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK12                                                                       */
+/* IH Class - Mask12 configuration    Note: used for IH class identification by Parser C */
+/* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
+/*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
+/*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
+/* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
+/*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_OFFSET ( 0x00000148 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK13                                                                       */
+/* IH Class - Mask13 configuration    Note: used for IH class identification by Parser C */
+/* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
+/*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
+/*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
+/* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
+/*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_OFFSET ( 0x0000014C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK14                                                                       */
+/* IH Class - Mask13 configuration    Note: used for IH class identification by Parser C */
+/* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
+/*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
+/*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
+/* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
+/*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_OFFSET ( 0x00000150 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS_MASK15                                                                       */
+/* IH Class - Mask15 configuration    Note: used for IH class identification by Parser C */
+/* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
+/*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
+/*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
+/* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
+/*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_OFFSET ( 0x00000154 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15 ;
+#else
+typedef struct
+{
+	/* IH_CLASS_KEY_MASK */
+	uint32_t ih_class_mask	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS0_GENERAL_CFG                                                                 */
+/* Set of defaults (general parameters) for IH class0    These parameters used for defau */
+/* lt setting per current IH class, used also as characterization of this ingres traffic */
+/* .    The set of aparametrs include:    o	Ingres QoS setting for class & override enab */
+/* le by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct  */
+/* mode setting per class & override enable by LUT   o	Default target Runner setting per */
+/*  class & load balancing enable + preference enable for load balancing  o	DSCP to TCI  */
+/* translation: reference to translation table  o	                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_OFFSET ( 0x00000158 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS1_GENERAL_CFG                                                                 */
+/* Set of defaults (general parameters) for IH class1    These parameters used for defau */
+/* lt setting per current IH class, used also as characterization of this ingres traffic */
+/* .    The set of aparametrs include:    o	Ingres QoS setting for class & override enab */
+/* le by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct  */
+/* mode setting per class & override enable by LUT   o	Default target Runner setting per */
+/*  class & load balancing enable + preference enable for load balancing  o	DSCP to TCI  */
+/* translation: reference to translation table  o	                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_OFFSET ( 0x0000015C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS2_GENERAL_CFG                                                                 */
+/* Set of defaults (general parameters) for IH class2    These parameters used for defau */
+/* lt setting per current IH class, used also as characterization of this ingres traffic */
+/* .    The set of aparametrs include:    o	Ingres QoS setting for class & override enab */
+/* le by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct  */
+/* mode setting per class & override enable by LUT   o	Default target Runner setting per */
+/*  class & load balancing enable + preference enable for load balancing  o	DSCP to TCI  */
+/* translation: reference to translation table  o	                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_OFFSET ( 0x00000160 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS3_GENERAL_CFG                                                                 */
+/* Set of defaults (general parameters) for IH class3    These parameters used for defau */
+/* lt setting per current IH class, used also as characterization of this ingres traffic */
+/* .    The set of aparametrs include:    o	Ingres QoS setting for class & override enab */
+/* le by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct  */
+/* mode setting per class & override enable by LUT   o	Default target Runner setting per */
+/*  class & load balancing enable + preference enable for load balancing  o	DSCP to TCI  */
+/* translation: reference to translation table  o	                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_OFFSET ( 0x00000164 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS4_GENERAL_CFG                                                                 */
+/* Set of defaults (general parameters) for IH class4    These parameters used for defau */
+/* lt setting per current IH class, used also as characterization of this ingres traffic */
+/* .    The set of aparametrs include:    o	Ingres QoS setting for class & override enab */
+/* le by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct  */
+/* mode setting per class & override enable by LUT   o	Default target Runner setting per */
+/*  class & load balancing enable + preference enable for load balancing  o	DSCP to TCI  */
+/* translation: reference to translation table  o	                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_OFFSET ( 0x00000168 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS5_GENERAL_CFG                                                                 */
+/* Set of defaults (general parameters) for IH class5    These parameters used for defau */
+/* lt setting per current IH class, used also as characterization of this ingres traffic */
+/* .    The set of aparametrs include:    o	Ingres QoS setting for class & override enab */
+/* le by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct  */
+/* mode setting per class & override enable by LUT   o	Default target Runner setting per */
+/*  class & load balancing enable + preference enable for load balancing  o	DSCP to TCI  */
+/* translation: reference to translation table  o	                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_OFFSET ( 0x0000016C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS6_GENERAL_CFG                                                                 */
+/* Set of defaults (general parameters) for IH class6    These parameters used for defau */
+/* lt setting per current IH class, used also as characterization of this ingres traffic */
+/* .    The set of aparametrs include:    o	Ingres QoS setting for class & override enab */
+/* le by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct  */
+/* mode setting per class & override enable by LUT   o	Default target Runner setting per */
+/*  class & load balancing enable + preference enable for load balancing  o	DSCP to TCI  */
+/* translation: reference to translation table  o	                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_OFFSET ( 0x00000170 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS7_GENERAL_CFG                                                                 */
+/* Set of defaults (general parameters) for IH class7    These parameters used for defau */
+/* lt setting per current IH class, used also as characterization of this ingres traffic */
+/* .    The set of aparametrs include:    o	Ingres QoS setting for class & override enab */
+/* le by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct  */
+/* mode setting per class & override enable by LUT   o	Default target Runner setting per */
+/*  class & load balancing enable + preference enable for load balancing  o	DSCP to TCI  */
+/* translation: reference to translation table  o	                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_OFFSET ( 0x00000174 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS8_GENERAL_CFG                                                                 */
+/* Set of defaults (general parameters) for IH class8    These parameters used for defau */
+/* lt setting per current IH class, used also as characterization of this ingres traffic */
+/* .    The set of aparametrs include:    o	Ingres QoS setting for class & override enab */
+/* le by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct  */
+/* mode setting per class & override enable by LUT   o	Default target Runner setting per */
+/*  class & load balancing enable + preference enable for load balancing  o	DSCP to TCI  */
+/* translation: reference to translation table  o	                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_OFFSET ( 0x00000178 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS9_GENERAL_CFG                                                                 */
+/* Set of defaults (general parameters) for IH class9    These parameters used for defau */
+/* lt setting per current IH class, used also as characterization of this ingres traffic */
+/* .    The set of aparametrs include:    o	Ingres QoS setting for class & override enab */
+/* le by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct  */
+/* mode setting per class & override enable by LUT   o	Default target Runner setting per */
+/*  class & load balancing enable + preference enable for load balancing  o	DSCP to TCI  */
+/* translation: reference to translation table  o	                                       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_OFFSET ( 0x0000017C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS10_GENERAL_CFG                                                                */
+/* Set of defaults (general parameters) for IH class10    These parameters used for defa */
+/* ult setting per current IH class, used also as characterization of this ingres traffi */
+/* c.    The set of aparametrs include:    o	Ingres QoS setting for class & override ena */
+/* ble by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct */
+/*  mode setting per class & override enable by LUT   o	Default target Runner setting pe */
+/* r class & load balancing enable + preference enable for load balancing  o	DSCP to TCI */
+/*  translation: reference to translation table  o	                                      */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_OFFSET ( 0x00000180 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS11_GENERAL_CFG                                                                */
+/* Set of defaults (general parameters) for IH class11    These parameters used for defa */
+/* ult setting per current IH class, used also as characterization of this ingres traffi */
+/* c.    The set of aparametrs include:    o	Ingres QoS setting for class & override ena */
+/* ble by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct */
+/*  mode setting per class & override enable by LUT   o	Default target Runner setting pe */
+/* r class & load balancing enable + preference enable for load balancing  o	DSCP to TCI */
+/*  translation: reference to translation table  o	                                      */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_OFFSET ( 0x00000184 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS12_GENERAL_CFG                                                                */
+/* Set of defaults (general parameters) for IH class12    These parameters used for defa */
+/* ult setting per current IH class, used also as characterization of this ingres traffi */
+/* c.    The set of aparametrs include:    o	Ingres QoS setting for class & override ena */
+/* ble by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct */
+/*  mode setting per class & override enable by LUT   o	Default target Runner setting pe */
+/* r class & load balancing enable + preference enable for load balancing  o	DSCP to TCI */
+/*  translation: reference to translation table  o	                                      */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_OFFSET ( 0x00000188 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS13_GENERAL_CFG                                                                */
+/* Set of defaults (general parameters) for IH class13    These parameters used for defa */
+/* ult setting per current IH class, used also as characterization of this ingres traffi */
+/* c.    The set of aparametrs include:    o	Ingres QoS setting for class & override ena */
+/* ble by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct */
+/*  mode setting per class & override enable by LUT   o	Default target Runner setting pe */
+/* r class & load balancing enable + preference enable for load balancing  o	DSCP to TCI */
+/*  translation: reference to translation table  o	                                      */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_OFFSET ( 0x0000018C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS14_GENERAL_CFG                                                                */
+/* Set of defaults (general parameters) for IH class14    These parameters used for defa */
+/* ult setting per current IH class, used also as characterization of this ingres traffi */
+/* c.    The set of aparametrs include:    o	Ingres QoS setting for class & override ena */
+/* ble by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct */
+/*  mode setting per class & override enable by LUT   o	Default target Runner setting pe */
+/* r class & load balancing enable + preference enable for load balancing  o	DSCP to TCI */
+/*  translation: reference to translation table  o	                                      */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_OFFSET ( 0x00000190 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS15_GENERAL_CFG                                                                */
+/* Set of defaults (general parameters) for IH class15    These parameters used for defa */
+/* ult setting per current IH class, used also as characterization of this ingres traffi */
+/* c.    The set of aparametrs include:    o	Ingres QoS setting for class & override ena */
+/* ble by LUT  o	Destination memory setting per class & override enable by LUT  o	Direct */
+/*  mode setting per class & override enable by LUT   o	Default target Runner setting pe */
+/* r class & load balancing enable + preference enable for load balancing  o	DSCP to TCI */
+/*  translation: reference to translation table  o	                                      */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_OFFSET ( 0x00000194 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG ;
+#else
+typedef struct
+{
+	/* QOS_DEFAULT */
+	uint32_t qos_default       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_OVERRIDE */
+	uint32_t qos_override      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_DEFAULT */
+	uint32_t tm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TM_OVERRIDE */
+	uint32_t tm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_DEFAULT */
+	uint32_t dm_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DM_OVERRIDE */
+	uint32_t dm_override       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TR_DEFAULT */
+	uint32_t tr_default        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_EN */
+	uint32_t lb_en             	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PREF_LB_EN */
+	uint32_t pref_lb_en        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TRANS_TBL */
+	uint32_t dscp2tci_trans_tbl	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_OVR_DM */
+	uint32_t rnr_ovr_dm        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_DEFAULT_DM */
+	uint32_t rnr_default_dm    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv               	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS0_SEARCH_CFG                                                                  */
+/* Set of search parametrs for IH class0    These parameters used for search setting per */
+/*  current IH class, used also as characterization of this ingres traffic.    The set o */
+/* f search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sear */
+/* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
+/* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
+/* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
+/*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
+/*  miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or no */
+/* n of them)                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_OFFSET ( 0x00000198 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS1_SEARCH_CFG                                                                  */
+/* Set of search parametrs for IH class1    These parameters used for search setting per */
+/*  current IH class, used also as characterization of this ingres traffic.    The set o */
+/* f search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sear */
+/* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
+/* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
+/* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
+/*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
+/*  miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or no */
+/* n of them)                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_OFFSET ( 0x0000019C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS2_SEARCH_CFG                                                                  */
+/* Set of search parametrs for IH class2    These parameters used for search setting per */
+/*  current IH class, used also as characterization of this ingres traffic.    The set o */
+/* f search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sear */
+/* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
+/* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
+/* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
+/*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
+/*  miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or no */
+/* n of them)                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_OFFSET ( 0x00000200 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS3_SEARCH_CFG                                                                  */
+/* Set of search parametrs for IH class3    These parameters used for search setting per */
+/*  current IH class, used also as characterization of this ingres traffic.    The set o */
+/* f search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sear */
+/* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
+/* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
+/* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
+/*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
+/*  miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or no */
+/* n of them)                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_OFFSET ( 0x00000204 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS4_SEARCH_CFG                                                                  */
+/* Set of search parametrs for IH class1    These parameters used for search setting per */
+/*  current IH class, used also as characterization of this ingres traffic.    The set o */
+/* f search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sear */
+/* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
+/* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
+/* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
+/*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
+/*  miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or no */
+/* n of them)                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_OFFSET ( 0x00000208 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS5_SEARCH_CFG                                                                  */
+/* Set of search parametrs for IH class5    These parameters used for search setting per */
+/*  current IH class, used also as characterization of this ingres traffic.    The set o */
+/* f search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sear */
+/* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
+/* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
+/* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
+/*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
+/*  miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or no */
+/* n of them)                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_OFFSET ( 0x0000020C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS6_SEARCH_CFG                                                                  */
+/* Set of search parametrs for IH class6    These parameters used for search setting per */
+/*  current IH class, used also as characterization of this ingres traffic.    The set o */
+/* f search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sear */
+/* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
+/* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
+/* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
+/*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
+/*  miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or no */
+/* n of them)                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_OFFSET ( 0x00000210 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS7_SEARCH_CFG                                                                  */
+/* Set of search parametrs for IH class7    These parameters used for search setting per */
+/*  current IH class, used also as characterization of this ingres traffic.    The set o */
+/* f search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sear */
+/* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
+/* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
+/* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
+/*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
+/*  miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or no */
+/* n of them)                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_OFFSET ( 0x00000214 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS8_SEARCH_CFG                                                                  */
+/* Set of search parametrs for IH class8    These parameters used for search setting per */
+/*  current IH class, used also as characterization of this ingres traffic.    The set o */
+/* f search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sear */
+/* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
+/* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
+/* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
+/*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
+/*  miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or no */
+/* n of them)                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_OFFSET ( 0x00000218 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS9_SEARCH_CFG                                                                  */
+/* Set of search parametrs for IH class9    These parameters used for search setting per */
+/*  current IH class, used also as characterization of this ingres traffic.    The set o */
+/* f search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sear */
+/* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
+/* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
+/* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
+/*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
+/*  miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or no */
+/* n of them)                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_OFFSET ( 0x0000021C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS10_SEARCH_CFG                                                                 */
+/* Set of search parametrs for IH class10    These parameters used for search setting pe */
+/* r current IH class, used also as characterization of this ingres traffic.    The set  */
+/* of search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sea */
+/* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
+/* for DA search, but with different key settings)    QoS extraction info:   - extract f */
+/* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
+/* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
+/* n miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or n */
+/* on of them)                                                                           */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_OFFSET ( 0x00000220 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS11_SEARCH_CFG                                                                 */
+/* Set of search parametrs for IH class11    These parameters used for search setting pe */
+/* r current IH class, used also as characterization of this ingres traffic.    The set  */
+/* of search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sea */
+/* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
+/* for DA search, but with different key settings)    QoS extraction info:   - extract f */
+/* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
+/* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
+/* n miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or n */
+/* on of them)                                                                           */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_OFFSET ( 0x00000224 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS12_SEARCH_CFG                                                                 */
+/* Set of search parametrs for IH class12    These parameters used for search setting pe */
+/* r current IH class, used also as characterization of this ingres traffic.    The set  */
+/* of search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sea */
+/* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
+/* for DA search, but with different key settings)    QoS extraction info:   - extract f */
+/* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
+/* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
+/* n miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or n */
+/* on of them)                                                                           */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_OFFSET ( 0x00000228 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS13_SEARCH_CFG                                                                 */
+/* Set of search parametrs for IH class13    These parameters used for search setting pe */
+/* r current IH class, used also as characterization of this ingres traffic.    The set  */
+/* of search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sea */
+/* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
+/* for DA search, but with different key settings)    QoS extraction info:   - extract f */
+/* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
+/* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
+/* n miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or n */
+/* on of them)                                                                           */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_OFFSET ( 0x0000022C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS14_SEARCH_CFG                                                                 */
+/* Set of search parametrs for IH class14    These parameters used for search setting pe */
+/* r current IH class, used also as characterization of this ingres traffic.    The set  */
+/* of search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sea */
+/* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
+/* for DA search, but with different key settings)    QoS extraction info:   - extract f */
+/* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
+/* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
+/* n miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or n */
+/* on of them)                                                                           */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_OFFSET ( 0x00000230 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLASS15_SEARCH_CFG                                                                 */
+/* Set of search parametrs for IH class15    These parameters used for search setting pe */
+/* r current IH class, used also as characterization of this ingres traffic.    The set  */
+/* of search parametrs include:    o	Detailed assignment of 4 LUT tables for up to 4 sea */
+/* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
+/* for DA search, but with different key settings)    QoS extraction info:   - extract f */
+/* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
+/* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
+/* n miss info:   - consider “drop on miss” from search 1 or from search 3 (one hot or n */
+/* on of them)                                                                           */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_OFFSET ( 0x00000234 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG ;
+#else
+typedef struct
+{
+	/* SEARCH1_LKUP_TBL_REF */
+	uint32_t search1_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH2_LKUP_TBL_REF */
+	uint32_t search2_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH3_LKUP_TBL_REF */
+	uint32_t search3_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SEARCH4_LKUP_TBL_REF */
+	uint32_t search4_lkup_tbl_ref 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QOS_EXTR_CFG */
+	uint32_t qos_extr_cfg         	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_EXTR_CFG */
+	uint32_t dp_extr_cfg          	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DROP_ON_MISS_EXTR_CFG */
+	uint32_t drop_on_miss_extr_cfg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* RNRA_CNGS_TRSH_CFG                                                                    */
+/* Congestion thresholds of Runner A    Includes:  - Load balaning congestion threshold  */
+/* (start load balanicng upon to enable bit)  - Load balancing hysteresis  - High priori */
+/* ty congestion threshold (drop low priority packets)  - Exclusive priority congestion  */
+/* threshold (drop low/high priority packets)    Note: should be according to max number */
+/*  of RBs                                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV4_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV4_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_EXCL_CNGS_TRSH_THRESHOLD_VALUE             ( 0x1C )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_EXCL_CNGS_TRSH_THRESHOLD_VALUE_RESET_VALUE ( 0x1C )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV3_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV3_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_HIGH_CNGS_TRSH_THRESHOLD_VALUE             ( 0x16 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_HIGH_CNGS_TRSH_THRESHOLD_VALUE_RESET_VALUE ( 0x16 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_LB_HYST_THRESHOLD_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_LB_HYST_THRESHOLD_VALUE_RESET_VALUE        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV1_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV1_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_LB_THSH_THRESHOLD_VALUE                    ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_LB_THSH_THRESHOLD_VALUE_RESET_VALUE        ( 0x8 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_OFFSET ( 0x00000238 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV4 */
+	uint32_t rsv4          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EXCL_CNGS_TRSH */
+	uint32_t excl_cngs_trsh	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HIGH_CNGS_TRSH */
+	uint32_t high_cngs_trsh	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_HYST */
+	uint32_t lb_hyst       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_THSH */
+	uint32_t lb_thsh       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG ;
+#else
+typedef struct
+{
+	/* LB_THSH */
+	uint32_t lb_thsh       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_HYST */
+	uint32_t lb_hyst       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HIGH_CNGS_TRSH */
+	uint32_t high_cngs_trsh	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EXCL_CNGS_TRSH */
+	uint32_t excl_cngs_trsh	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV4 */
+	uint32_t rsv4          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* RNRB_CNGS_TRSH_CFG                                                                    */
+/* Congestion thresholds of Runner B    Includes:  - Load balaning congestion threshold  */
+/* (start load balanicng upon to enable bit)  - Load balancing hysteresis  - High priori */
+/* ty congestion threshold (drop low priority packets)  - Exclusive priority congestion  */
+/* threshold (drop low/high priority packets)    Note: should be according to max number */
+/*  of RBs                                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV4_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV4_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_EXCL_CNGS_TRSH_THRESHOLD_VALUE             ( 0x1C )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_EXCL_CNGS_TRSH_THRESHOLD_VALUE_RESET_VALUE ( 0x1C )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV3_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV3_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_HIGH_CNGS_TRSH_THRESHOLD_VALUE             ( 0x16 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_HIGH_CNGS_TRSH_THRESHOLD_VALUE_RESET_VALUE ( 0x16 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_LB_HYST_THRESHOLD_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_LB_HYST_THRESHOLD_VALUE_RESET_VALUE        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV1_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV1_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_LB_THSH_THRESHOLD_VALUE                    ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_LB_THSH_THRESHOLD_VALUE_RESET_VALUE        ( 0x8 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_OFFSET ( 0x0000023C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV4 */
+	uint32_t rsv4          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EXCL_CNGS_TRSH */
+	uint32_t excl_cngs_trsh	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HIGH_CNGS_TRSH */
+	uint32_t high_cngs_trsh	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_HYST */
+	uint32_t lb_hyst       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_THSH */
+	uint32_t lb_thsh       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG ;
+#else
+typedef struct
+{
+	/* LB_THSH */
+	uint32_t lb_thsh       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LB_HYST */
+	uint32_t lb_hyst       	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+	uint32_t rsv2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HIGH_CNGS_TRSH */
+	uint32_t high_cngs_trsh	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv3 */
+	uint32_t rsv3          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EXCL_CNGS_TRSH */
+	uint32_t excl_cngs_trsh	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV4 */
+	uint32_t rsv4          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* WAN_PER_PORT_CFG                                                                      */
+/* Each phyisical ingres port has its own configuration if it belongs to WAN or non-WAN  */
+/* traffic                                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RSV_RSV_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RSV_RSV_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE1_TRF_MAP_NON_WAN_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE1_TRF_MAP_NON_WAN_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE1_TRF_MAP_WAN_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE0_TRF_MAP_NON_WAN_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE0_TRF_MAP_NON_WAN_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE0_TRF_MAP_WAN_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRB_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRB_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRB_TRF_MAP_WAN_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRA_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRA_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRA_TRF_MAP_WAN_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_GPON_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_GPON_TRF_MAP_WAN_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_GPON_TRF_MAP_WAN_VALUE_RESET_VALUE      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH4_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH4_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH4_TRF_MAP_WAN_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH3_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH3_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH3_TRF_MAP_WAN_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH2_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH2_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH2_TRF_MAP_WAN_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH1_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH1_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH1_TRF_MAP_WAN_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH0_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH0_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH0_TRF_MAP_WAN_VALUE                  ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_OFFSET ( 0x00000240 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv          	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE1_TRF_MAP */
+	uint32_t pcie1_trf_map	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE0_TRF_MAP */
+	uint32_t pcie0_trf_map	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_TRF_MAP */
+	uint32_t rnrb_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_TRF_MAP */
+	uint32_t rnra_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_TRF_MAP */
+	uint32_t gpon_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_TRF_MAP */
+	uint32_t eth4_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_TRF_MAP */
+	uint32_t eth3_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_TRF_MAP */
+	uint32_t eth2_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_TRF_MAP */
+	uint32_t eth1_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH0_TRF_MAP */
+	uint32_t eth0_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG ;
+#else
+typedef struct
+{
+	/* ETH0_TRF_MAP */
+	uint32_t eth0_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_TRF_MAP */
+	uint32_t eth1_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_TRF_MAP */
+	uint32_t eth2_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_TRF_MAP */
+	uint32_t eth3_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_TRF_MAP */
+	uint32_t eth4_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_TRF_MAP */
+	uint32_t gpon_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_TRF_MAP */
+	uint32_t rnra_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_TRF_MAP */
+	uint32_t rnrb_trf_map 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE0_TRF_MAP */
+	uint32_t pcie0_trf_map	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE1_TRF_MAP */
+	uint32_t pcie1_trf_map	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv          	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* PARSE_LAYER_PER_PORT_CFG                                                              */
+/* Each phyisical ingres port has its own configuration related to Parsing Layer Depth   */
+/* Note: pcie0 and pcie1 are sharing same configuration                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RSV_RSV_VALUE                                       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RSV_RSV_VALUE_RESET_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_PCIE1_PARSE_LAYER_STG_PARSE_LAYER_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_PCIE1_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_PCIE0_PARSE_LAYER_STG_PARSE_LAYER_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_PCIE0_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RNRB_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RNRB_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RNRA_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RNRA_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_GPON_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_GPON_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH4_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH4_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH3_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH3_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH2_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH2_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH1_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH1_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH0_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH0_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_OFFSET ( 0x00000244 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                  	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE1_PARSE_LAYER_STG */
+	uint32_t pcie1_parse_layer_stg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE0_PARSE_LAYER_STG */
+	uint32_t pcie0_parse_layer_stg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_PARSE_LAYER_STG */
+	uint32_t rnrb_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_PARSE_LAYER_STG */
+	uint32_t rnra_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_PARSE_LAYER_STG */
+	uint32_t gpon_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_PARSE_LAYER_STG */
+	uint32_t eth4_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_PARSE_LAYER_STG */
+	uint32_t eth3_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_PARSE_LAYER_STG */
+	uint32_t eth2_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_PARSE_LAYER_STG */
+	uint32_t eth1_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH0_PARSE_LAYER_STG */
+	uint32_t eth0_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG ;
+#else
+typedef struct
+{
+	/* ETH0_PARSE_LAYER_STG */
+	uint32_t eth0_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_PARSE_LAYER_STG */
+	uint32_t eth1_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_PARSE_LAYER_STG */
+	uint32_t eth2_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_PARSE_LAYER_STG */
+	uint32_t eth3_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_PARSE_LAYER_STG */
+	uint32_t eth4_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_PARSE_LAYER_STG */
+	uint32_t gpon_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_PARSE_LAYER_STG */
+	uint32_t rnra_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_PARSE_LAYER_STG */
+	uint32_t rnrb_parse_layer_stg 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE0_PARSE_LAYER_STG */
+	uint32_t pcie0_parse_layer_stg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE1_PARSE_LAYER_STG */
+	uint32_t pcie1_parse_layer_stg	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                  	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* PROP_SIZE_PER_PORT_CFG0                                                               */
+/* Each phyisical ingres port has its own configuration related to Propitiatory tag size */
+/* , valid option are 0, 4 ,6 or 8 bytes.  The option of 2 bytes is reserved for user, b */
+/* ut supported by HW. This option should be masked by driver API.  This register is rel */
+/* ated to following source ports (source port is taken from Packet Header Descriptor):  */
+/*  - Eth0-4  - GPON (or Eth5)  - Runner A/B                                             */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_OFFSET ( 0x00000248 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RNRB_PROP_TAG_SIZE */
+	uint32_t rnrb_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_PROP_TAG_SIZE */
+	uint32_t rnra_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_PROP_TAG_SIZE */
+	uint32_t gpon_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_PROP_TAG_SIZE */
+	uint32_t eth4_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_PROP_TAG_SIZE */
+	uint32_t eth3_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_PROP_TAG_SIZE */
+	uint32_t eth2_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_PROP_TAG_SIZE */
+	uint32_t eth1_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH0_PROP_TAG_SIZE */
+	uint32_t eth0_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0 ;
+#else
+typedef struct
+{
+	/* ETH0_PROP_TAG_SIZE */
+	uint32_t eth0_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_PROP_TAG_SIZE */
+	uint32_t eth1_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_PROP_TAG_SIZE */
+	uint32_t eth2_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_PROP_TAG_SIZE */
+	uint32_t eth3_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_PROP_TAG_SIZE */
+	uint32_t eth4_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_PROP_TAG_SIZE */
+	uint32_t gpon_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_PROP_TAG_SIZE */
+	uint32_t rnra_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_PROP_TAG_SIZE */
+	uint32_t rnrb_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0 ;
+#endif
+
+/*****************************************************************************************/
+/* PROP_SIZE_PER_PORT_CFG1                                                               */
+/* Each phyisical ingres port has its own configuration related to Propitiatory tag size */
+/* , valid option are 0, 4 ,6 or 8 bytes.  The option of 2 bytes is reserved for user, b */
+/* ut supported by HW. This option should be masked by driver API.  This register is rel */
+/* ated to following source ports (source port is taken from Packet Header Descriptor):  */
+/*  - Pcie0  - Pcie1                                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_RSV_RSV_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_RSV_RSV_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_OFFSET ( 0x0000024C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE1_PROP_TAG_SIZE */
+	uint32_t pcie1_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE0_PROP_TAG_SIZE */
+	uint32_t pcie0_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1 ;
+#else
+typedef struct
+{
+	/* PCIE0_PROP_TAG_SIZE */
+	uint32_t pcie0_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE1_PROP_TAG_SIZE */
+	uint32_t pcie1_prop_tag_size	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv                	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1 ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLSF_MAPL_CFG                                                                      */
+/* There are 16 Classifier sets (keys+mask) that in case of match performs mapping of ma */
+/* tched set to IH class. The register includes Class ID for lowest sets [0...7]         */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET7_MAP_CLASS_ID_VALUE             ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET7_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x7 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET6_MAP_CLASS_ID_VALUE             ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET6_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x6 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET5_MAP_CLASS_ID_VALUE             ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET5_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x5 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET4_MAP_CLASS_ID_VALUE             ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET4_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x4 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET3_MAP_CLASS_ID_VALUE             ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET3_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x3 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET2_MAP_CLASS_ID_VALUE             ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET2_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x2 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET1_MAP_CLASS_ID_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET1_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET0_MAP_CLASS_ID_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET0_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_OFFSET ( 0x00000250 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* CLSF_SET7_MAP */
+	uint32_t clsf_set7_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET6_MAP */
+	uint32_t clsf_set6_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET5_MAP */
+	uint32_t clsf_set5_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET4_MAP */
+	uint32_t clsf_set4_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET3_MAP */
+	uint32_t clsf_set3_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET2_MAP */
+	uint32_t clsf_set2_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET1_MAP */
+	uint32_t clsf_set1_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET0_MAP */
+	uint32_t clsf_set0_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG ;
+#else
+typedef struct
+{
+	/* CLSF_SET0_MAP */
+	uint32_t clsf_set0_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET1_MAP */
+	uint32_t clsf_set1_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET2_MAP */
+	uint32_t clsf_set2_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET3_MAP */
+	uint32_t clsf_set3_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET4_MAP */
+	uint32_t clsf_set4_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET5_MAP */
+	uint32_t clsf_set5_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET6_MAP */
+	uint32_t clsf_set6_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET7_MAP */
+	uint32_t clsf_set7_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* IH_CLSF_MAPH_CFG                                                                      */
+/* There are 16 Classifier sets (keys+mask) that in case of match performs mapping of ma */
+/* tched set to IH class. The register includes Class ID for highest sets [8...15]       */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET15_MAP_CLASS_ID_VALUE             ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET15_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xF )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET14_MAP_CLASS_ID_VALUE             ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET14_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xE )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET13_MAP_CLASS_ID_VALUE             ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET13_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xD )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET12_MAP_CLASS_ID_VALUE             ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET12_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xC )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET11_MAP_CLASS_ID_VALUE             ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET11_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xB )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET10_MAP_CLASS_ID_VALUE             ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET10_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xA )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET9_MAP_CLASS_ID_VALUE              ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET9_MAP_CLASS_ID_VALUE_RESET_VALUE  ( 0x9 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET8_MAP_CLASS_ID_VALUE              ( 0x8 )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET8_MAP_CLASS_ID_VALUE_RESET_VALUE  ( 0x8 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_OFFSET ( 0x00000254 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* CLSF_SET15_MAP */
+	uint32_t clsf_set15_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET14_MAP */
+	uint32_t clsf_set14_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET13_MAP */
+	uint32_t clsf_set13_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET12_MAP */
+	uint32_t clsf_set12_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET11_MAP */
+	uint32_t clsf_set11_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET10_MAP */
+	uint32_t clsf_set10_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET9_MAP */
+	uint32_t clsf_set9_map 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET8_MAP */
+	uint32_t clsf_set8_map 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG ;
+#else
+typedef struct
+{
+	/* CLSF_SET8_MAP */
+	uint32_t clsf_set8_map 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET9_MAP */
+	uint32_t clsf_set9_map 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET10_MAP */
+	uint32_t clsf_set10_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET11_MAP */
+	uint32_t clsf_set11_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET12_MAP */
+	uint32_t clsf_set12_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET13_MAP */
+	uint32_t clsf_set13_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET14_MAP */
+	uint32_t clsf_set14_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CLSF_SET15_MAP */
+	uint32_t clsf_set15_map	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* TRGT_MTRX_PCIE0_SP_CFG                                                                */
+/* Target matrix configuration for Source Port PCIE0    Used for decision on Target memo */
+/* ry and Local switch as function of extracted destination port that can be as followin */
+/* g:  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CP */
+/* U  - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local sw */
+/* itch info)  -Spare                                                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_OFFSET ( 0x00000258 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* TRGT_MTRX_PCIE1_SP_CFG                                                                */
+/* Target matrix configuration for Source Port PCIE0    Used for decision on Target memo */
+/* ry and Local switch as function of extracted destination port that can be as followin */
+/* g:  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CP */
+/* U  - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local sw */
+/* itch info)  -Spare                                                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_OFFSET ( 0x0000025C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_TM_CFG */
+	uint32_t dp_eth0_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_TM_CFG */
+	uint32_t dp_eth1_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_TM_CFG */
+	uint32_t dp_eth2_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_TM_CFG */
+	uint32_t dp_eth3_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_TM_CFG */
+	uint32_t dp_eth4_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_TM_CFG */
+	uint32_t dp_gpon_tm_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_TM_CFG */
+	uint32_t dp_pcie0_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_TM_CFG */
+	uint32_t dp_cpu_tm_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_TM_CFG */
+	uint32_t dp_mc_tm_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_TM_CFG */
+	uint32_t dp_pcie1_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_TM_CFG */
+	uint32_t dp_spare_tm_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv1           	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_LS_CFG */
+	uint32_t dp_eth0_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_LS_CFG */
+	uint32_t dp_eth1_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_LS_CFG */
+	uint32_t dp_eth2_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_LS_CFG */
+	uint32_t dp_eth3_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_LS_CFG */
+	uint32_t dp_eth4_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_LS_CFG */
+	uint32_t dp_gpon_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_LS_CFG */
+	uint32_t dp_pcie0_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_LS_CFG */
+	uint32_t dp_cpu_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_LS_CFG */
+	uint32_t dp_mc_ls_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_LS_CFG */
+	uint32_t dp_ddr_ls_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_LS_CFG */
+	uint32_t dp_sram_ls_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_LS_CFG */
+	uint32_t dp_pcie1_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_LS_CFG */
+	uint32_t dp_spare_ls_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* FW_EN_MTRX_ETH0_SP_CFG                                                                */
+/* Forward Enable configurations for each path in target matrix, while Source Port = Eth */
+/* 0    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
+/* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
+/* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
+/* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_OFFSET ( 0x00000260 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* FW_EN_MTRX_ETH1_SP_CFG                                                                */
+/* Forward Enable configurations for each path in target matrix, while Source Port = Eth */
+/* 1    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
+/* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
+/* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
+/* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_OFFSET ( 0x00000264 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* FW_EN_MTRX_ETH2_SP_CFG                                                                */
+/* Forward Enable configurations for each path in target matrix, while Source Port = Eth */
+/* 2    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
+/* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
+/* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
+/* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_OFFSET ( 0x00000268 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* FW_EN_MTRX_ETH3_SP_CFG                                                                */
+/* Forward Enable configurations for each path in target matrix, while Source Port = Eth */
+/* 3    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
+/* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
+/* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
+/* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_OFFSET ( 0x0000026C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* FW_EN_MTRX_ETH4_SP_CFG                                                                */
+/* Forward Enable configurations for each path in target matrix, while Source Port = Eth */
+/* 4    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
+/* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
+/* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
+/* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_OFFSET ( 0x00000270 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* FW_EN_MTRX_GPON_SP_CFG                                                                */
+/* Forward Enable configurations for each path in target matrix, while Source Port = GPO */
+/* N    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
+/* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
+/* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
+/* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_OFFSET ( 0x00000274 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* FW_EN_MTRX_PCIE0_SP_CFG                                                               */
+/* Forward Enable configurations for each path in target matrix, while Source Port = PCI */
+/* E0    Used by FW as enable information for each path in Target Matrix. Forwarded in R */
+/* IB, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  - */
+/*  Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local s */
+/* witch info)  - Always SRAM(relevant for local switch info)  -Spare                    */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_OFFSET ( 0x00000278 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* FW_EN_MTRX_PCIE1_SP_CFG                                                               */
+/* Forward Enable configurations for each path in target matrix, while Source Port = PCI */
+/* E1    Used by FW as enable information for each path in Target Matrix. Forwarded in R */
+/* IB, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  - */
+/*  Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local s */
+/* witch info)  - Always SRAM(relevant for local switch info)  -Spare                    */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_OFFSET ( 0x0000027C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG ;
+#else
+typedef struct
+{
+	/* DP_ETH0_FW_EN_CFG */
+	uint32_t dp_eth0_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH1_FW_EN_CFG */
+	uint32_t dp_eth1_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH2_FW_EN_CFG */
+	uint32_t dp_eth2_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH3_FW_EN_CFG */
+	uint32_t dp_eth3_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_ETH4_FW_EN_CFG */
+	uint32_t dp_eth4_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_GPON_FW_EN_CFG */
+	uint32_t dp_gpon_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE0_FW_EN_CFG */
+	uint32_t dp_pcie0_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_MC_FW_EN_CFG */
+	uint32_t dp_mc_fw_en_cfg   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_CPU_FW_EN_CFG */
+	uint32_t dp_cpu_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_DDR_FW_EN_CFG */
+	uint32_t dp_ddr_fw_en_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SRAM_FW_EN_CFG */
+	uint32_t dp_sram_fw_en_cfg 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_PCIE1_FW_EN_CFG */
+	uint32_t dp_pcie1_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DP_SPARE_FW_EN_CFG */
+	uint32_t dp_spare_fw_en_cfg	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SPARE */
+	uint32_t spare             	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2              	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* PH_MEM_RD_RQST_CFG                                                                    */
+/* Packet Header Memory Read request register.    The read of Packet Header memory is us */
+/* ed for debug needs. We can actually print out all Ingress Buffers = (Packet Headers f */
+/* iled by BBH/Runner to their slots). The read is done by inderect way: user puts addre */
+/* ss of RAM (address space from 0x0 to 0xFF) and performs polling on BSY bit, while the */
+/*  BSY=0 -> read succeeded and data is ready in registers PH_MEM_RD_DATA_LOW/PH_MEM_RD_ */
+/* DATA_HIGH                                                                             */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_PH_MEM_RD_RQST_BSY_NON_BUSY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_PH_MEM_RD_RQST_BSY_NON_BUSY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_PH_MEM_RD_RQST_BSY_BUSY_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_RSV_RSV_VALUE                                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_RSV_RSV_VALUE_RESET_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_PH_MEM_RD_RQST_ADDR_VALUE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_PH_MEM_RD_RQST_ADDR_VALUE_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_OFFSET ( 0x00000280 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* PH_MEM_RD_RQST_BSY */
+	uint32_t ph_mem_rd_rqst_bsy 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv                	: 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PH_MEM_RD_RQST_ADDR */
+	uint32_t ph_mem_rd_rqst_addr	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG ;
+#else
+typedef struct
+{
+	/* PH_MEM_RD_RQST_ADDR */
+	uint32_t ph_mem_rd_rqst_addr	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv                	: 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PH_MEM_RD_RQST_BSY */
+	uint32_t ph_mem_rd_rqst_bsy 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* PH_MEM_RD_DATA_LOW                                                                    */
+/* Packet Header Memory Read data low [31:0]    The read of Packet Header memory is used */
+/*  for debug needs. We can actually print out all Ingress Buffers = (Packet Headers fil */
+/* ed by BBH/Runner to their slots). The read is done by inderect way: user puts address */
+/*  of RAM (address space from 0x0 to 0xFF) and performs polling on BSY bit, while the B */
+/* SY=0 -> read succeeded and data is ready in registers PH_MEM_RD_DATA_LOW/PH_MEM_RD_DA */
+/* TA_HIGH                                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_DATA_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_DATA_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_OFFSET ( 0x00000284 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DATA */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW ;
+#else
+typedef struct
+{
+	/* DATA */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW ;
+#endif
+
+/*****************************************************************************************/
+/* PH_MEM_RD_DATA_HIGH                                                                   */
+/* Packet Header Memory Read data high [63:32]    The read of Packet Header memory is us */
+/* ed for debug needs. We can actually print out all Ingress Buffers = (Packet Headers f */
+/* iled by BBH/Runner to their slots). The read is done by inderect way: user puts addre */
+/* ss of RAM (address space from 0x0 to 0xFF) and performs polling on BSY bit, while the */
+/*  BSY=0 -> read succeeded and data is ready in registers PH_MEM_RD_DATA_LOW/PH_MEM_RD_ */
+/* DATA_HIGH                                                                             */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_DATA_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_DATA_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_OFFSET ( 0x00000288 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DATA */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH ;
+#else
+typedef struct
+{
+	/* DATA */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH ;
+#endif
+
+/*****************************************************************************************/
+/* SN_REG_0                                                                              */
+/* Serial Number status register0 for ports:  - Eth0  - Eth1    This register is used fo */
+/* r debug only                                                                          */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_SN_ETH1_SN_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_SN_ETH1_SN_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_SN_ETH0_SN_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_SN_ETH0_SN_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_OFFSET ( 0x0000028C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* SN_ETH1 */
+	uint32_t sn_eth1	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_ETH0 */
+	uint32_t sn_eth0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_SN_REG_0 ;
+#else
+typedef struct
+{
+	/* SN_ETH0 */
+	uint32_t sn_eth0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_ETH1 */
+	uint32_t sn_eth1	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_SN_REG_0 ;
+#endif
+
+/*****************************************************************************************/
+/* SN_REG_1                                                                              */
+/* Serial Number status register1 for ports:  - Eth2  - Eth3  This register is used for  */
+/* debug only                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_SN_ETH3_SN_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_SN_ETH3_SN_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_SN_ETH2_SN_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_SN_ETH2_SN_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_OFFSET ( 0x00000290 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* SN_ETH3 */
+	uint32_t sn_eth3	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_ETH2 */
+	uint32_t sn_eth2	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_SN_REG_1 ;
+#else
+typedef struct
+{
+	/* SN_ETH2 */
+	uint32_t sn_eth2	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_ETH3 */
+	uint32_t sn_eth3	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_SN_REG_1 ;
+#endif
+
+/*****************************************************************************************/
+/* SN_REG_2                                                                              */
+/* Serial Number status register2 for ports:  - Eth4  - GPON  This register is used for  */
+/* debug only                                                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_SN_GPON_SN_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_SN_GPON_SN_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_SN_ETH4_SN_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_SN_ETH4_SN_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_OFFSET ( 0x00000294 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* SN_GPON */
+	uint32_t sn_gpon	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_ETH4 */
+	uint32_t sn_eth4	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_SN_REG_2 ;
+#else
+typedef struct
+{
+	/* SN_ETH4 */
+	uint32_t sn_eth4	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_GPON */
+	uint32_t sn_gpon	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_SN_REG_2 ;
+#endif
+
+/*****************************************************************************************/
+/* SN_REG_3                                                                              */
+/* Serial Number status register3 for ports:  - Runner A  - Runner B  This register is u */
+/* sed for debug only                                                                    */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_SN_RNRB_SN_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_SN_RNRB_SN_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_SN_RNRA_SN_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_SN_RNRA_SN_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_OFFSET ( 0x00000298 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* SN_RNRB */
+	uint32_t sn_rnrb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_RNRA */
+	uint32_t sn_rnra	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_SN_REG_3 ;
+#else
+typedef struct
+{
+	/* SN_RNRA */
+	uint32_t sn_rnra	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_RNRB */
+	uint32_t sn_rnrb	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_SN_REG_3 ;
+#endif
+
+/*****************************************************************************************/
+/* LOCAL_MEM_RD_RQST_CFG                                                                 */
+/* Local Memory Read request register.    The read of one of 5 Local memories is used fo */
+/* r debug needs. We can actually print out all in-pipe Runner Buffers = (Packet Headers */
+/*  + Parser results + Look-up results: memory filling depends on pipe stage). The read  */
+/* is done by inderect way: user puts RAM number(0,1,2,3 or 4) & address of RAM (address */
+/*  space from 0x0 to 0x1F) and performs polling on BSY bit, while the BSY=0 -> read suc */
+/* ceeded and data is ready in registers LOCAL_MEM_RD_DATA_LOW/LOCAL_MEM_RD_DATA_HIGH    */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_BSY_NON_BUSY_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_BSY_NON_BUSY_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_BSY_BUSY_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_RSV_RSV_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_RSV_RSV_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_NUM_VALUE_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_NUM_VALUE_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_ADDR_VALUE_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_ADDR_VALUE_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_OFFSET ( 0x0000029C )
+
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* LOCAL_MEM_RD_RQST_BSY */
+	uint32_t local_mem_rd_rqst_bsy 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv                   	: 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LOCAL_MEM_RD_RQST_NUM */
+	uint32_t local_mem_rd_rqst_num 	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LOCAL_MEM_RD_RQST_ADDR */
+	uint32_t local_mem_rd_rqst_addr	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG ;
+#else
+typedef struct
+{
+	/* LOCAL_MEM_RD_RQST_ADDR */
+	uint32_t local_mem_rd_rqst_addr	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LOCAL_MEM_RD_RQST_NUM */
+	uint32_t local_mem_rd_rqst_num 	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv                   	: 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LOCAL_MEM_RD_RQST_BSY */
+	uint32_t local_mem_rd_rqst_bsy 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* LOCAL_MEM_RD_DATA_LOW                                                                 */
+/* Packet Header Memory Read data low [31:0]    The read of Packet Header memory is used */
+/*  for debug needs. We can actually print out all Ingress Buffers = (Packet Headers fil */
+/* ed by BBH/Runner to their slots). The read is done by inderect way: user puts address */
+/*  of RAM (address space from 0x0 to 0xFF) and performs polling on BSY bit, while the B */
+/* SY=0 -> read succeeded and data is ready in registers PH_MEM_RD_DATA_LOW/PH_MEM_RD_DA */
+/* TA_HIGH                                                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_DATA_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_DATA_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_OFFSET ( 0x000002A0 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DATA */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW ;
+#else
+typedef struct
+{
+	/* DATA */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW ;
+#endif
+
+/*****************************************************************************************/
+/* LOCAL_MEM_RD_DATA_HIGH                                                                */
+/* Packet Header Memory Read data high [63:32]    The read of Packet Header memory is us */
+/* ed for debug needs. We can actually print out all Ingress Buffers = (Packet Headers f */
+/* iled by BBH/Runner to their slots). The read is done by inderect way: user puts addre */
+/* ss of RAM (address space from 0x0 to 0xFF) and performs polling on BSY bit, while the */
+/*  BSY=0 -> read succeeded and data is ready in registers PH_MEM_RD_DATA_LOW/PH_MEM_RD_ */
+/* DATA_HIGH                                                                             */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_DATA_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_DATA_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_OFFSET ( 0x000002A4 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* DATA */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH ;
+#else
+typedef struct
+{
+	/* DATA */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH ;
+#endif
+
+/*****************************************************************************************/
+/* DBG_KEY1_LOW                                                                          */
+/* Serach Key1 low part [31:0]    The read of Search Key is used for debug needs. We can */
+/*  actually print out all generated key (according to key configs + parser results). Ke */
+/* y of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIGH  */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_KEY_VALUE_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_OFFSET ( 0x000002A8 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW ;
+#else
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW ;
+#endif
+
+/*****************************************************************************************/
+/* DBG_KEY1_HIGH                                                                         */
+/* Serach Key1 high part [63:32]    The read of Search Key is used for debug needs. We c */
+/* an actually print out all generated key (according to key configs + parser results).  */
+/* Key of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIG */
+/* H                                                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_RSV_RSV_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_KEY_VALUE_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_OFFSET ( 0x000002AC )
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_VALUE */
+	uint32_t key_value	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH ;
+#else
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH ;
+#endif
+
+/*****************************************************************************************/
+/* DBG_KEY2_LOW                                                                          */
+/* Search Key2 low part [31:0]    The read of Search Key is used for debug needs. We can */
+/*  actually print out all generated key (according to key configs + parser results). Ke */
+/* y of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIGH  */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_KEY_VALUE_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_OFFSET ( 0x000002B0 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW ;
+#else
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW ;
+#endif
+
+/*****************************************************************************************/
+/* DBG_KEY2_HIGH                                                                         */
+/* Search Key2 high part [63:32]    The read of Search Key is used for debug needs. We c */
+/* an actually print out all generated key (according to key configs + parser results).  */
+/* Key of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIG */
+/* H                                                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_RSV_RSV_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_KEY_VALUE_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_OFFSET ( 0x000002B4 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_VALUE */
+	uint32_t key_value	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH ;
+#else
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH ;
+#endif
+
+/*****************************************************************************************/
+/* DBG_KEY3_LOW                                                                          */
+/* Search Key3 low part [31:0]    The read of Search Key is used for debug needs. We can */
+/*  actually print out all generated key (according to key configs + parser results). Ke */
+/* y of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIGH  */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_KEY_VALUE_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_OFFSET ( 0x000002B8 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW ;
+#else
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW ;
+#endif
+
+/*****************************************************************************************/
+/* DBG_KEY3_HIGH                                                                         */
+/* Search Key3 high part [63:32]    The read of Search Key is used for debug needs. We c */
+/* an actually print out all generated key (according to key configs + parser results).  */
+/* Key of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIG */
+/* H                                                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_RSV_RSV_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_KEY_VALUE_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_OFFSET ( 0x000002BC )
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_VALUE */
+	uint32_t key_value	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH ;
+#else
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH ;
+#endif
+
+/*****************************************************************************************/
+/* DBG_KEY4_LOW                                                                          */
+/* Search Key4 low part [31:0]    The read of Search Key is used for debug needs. We can */
+/*  actually print out all generated key (according to key configs + parser results). Ke */
+/* y of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIGH  */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_KEY_VALUE_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_OFFSET ( 0x000002C0 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW ;
+#else
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW ;
+#endif
+
+/*****************************************************************************************/
+/* DBG_KEY4_HIGH                                                                         */
+/* Search Key4 high part [63:32]    The read of Search Key is used for debug needs. We c */
+/* an actually print out all generated key (according to key configs + parser results).  */
+/* Key of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIG */
+/* H                                                                                     */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_RSV_RSV_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_KEY_VALUE_VALUE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_OFFSET ( 0x000002C4 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* KEY_VALUE */
+	uint32_t key_value	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH ;
+#else
+typedef struct
+{
+	/* KEY_VALUE */
+	uint32_t key_value	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv      	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH ;
+#endif
+
+/*****************************************************************************************/
+/* DBG_IQ_STAT                                                                           */
+/* Status debug register for Ingress Queue    Ingress Queue status is used for debug nee */
+/* ds. We can actually print out several status, like Main IQ FIFO statuses, local RAM o */
+/* ccupancy status, each ingress queue status                                            */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_RSV2_RSV_VALUE                                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_RSV2_RSV_VALUE_RESET_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_FULL_FULL_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_FULL_FULL_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_FULL_FULL_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_FULL_FULL_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_FULL_FULL_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_FULL_FULL_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_FULL_FULL_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_FULL_FULL_VALUE                       ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_FULL_NOT_FULL_VALUE                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_FULL_NOT_FULL_VALUE_RESET_VALUE        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_FULL_FULL_VALUE                        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_EMPTY_NON_EMPTY_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_EMPTY_EMPTY_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE          ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_RSV_RSV_VALUE                                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_RSV_RSV_VALUE_RESET_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM4_STTS_NON_OCCUPIED_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM4_STTS_NON_OCCUPIED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM4_STTS_OCCUPIED_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM3_STTS_NON_OCCUPIED_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM3_STTS_NON_OCCUPIED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM3_STTS_OCCUPIED_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM2_STTS_NON_OCCUPIED_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM2_STTS_NON_OCCUPIED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM2_STTS_OCCUPIED_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM1_STTS_NON_OCCUPIED_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM1_STTS_NON_OCCUPIED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM1_STTS_OCCUPIED_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM0_STTS_NON_OCCUPIED_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM0_STTS_NON_OCCUPIED_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM0_STTS_OCCUPIED_VALUE                 ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_OFFSET ( 0x000002C8 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2           	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ7_FIFO_FULL */
+	uint32_t iq7_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_FIFO_FULL */
+	uint32_t iq6_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_FIFO_FULL */
+	uint32_t iq5_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_FIFO_FULL */
+	uint32_t iq4_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_FIFO_FULL */
+	uint32_t iq3_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_FIFO_FULL */
+	uint32_t iq2_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_FIFO_FULL */
+	uint32_t iq1_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ0_FIFO_FULL */
+	uint32_t iq0_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ7_FIFO_EMPTY */
+	uint32_t iq7_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_FIFO_EMPTY */
+	uint32_t iq6_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_FIFO_EMPTY */
+	uint32_t iq5_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_FIFO_EMPTY */
+	uint32_t iq4_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_FIFO_EMPTY */
+	uint32_t iq3_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_FIFO_EMPTY */
+	uint32_t iq2_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_FIFO_EMPTY */
+	uint32_t iq1_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ0_FIFO_EMPTY */
+	uint32_t iq0_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ_FIFO_FULL */
+	uint32_t iq_fifo_full   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ_FIFO_EMPTY */
+	uint32_t iq_fifo_empty  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv            	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Local_ram4_stts */
+	uint32_t local_ram4_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Local_ram3_stts */
+	uint32_t local_ram3_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Local_ram2_stts */
+	uint32_t local_ram2_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Local_ram1_stts */
+	uint32_t local_ram1_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Local_ram0_stts */
+	uint32_t local_ram0_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT ;
+#else
+typedef struct
+{
+	/* Local_ram0_stts */
+	uint32_t local_ram0_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Local_ram1_stts */
+	uint32_t local_ram1_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Local_ram2_stts */
+	uint32_t local_ram2_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Local_ram3_stts */
+	uint32_t local_ram3_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Local_ram4_stts */
+	uint32_t local_ram4_stts	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv            	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ_FIFO_EMPTY */
+	uint32_t iq_fifo_empty  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ_FIFO_FULL */
+	uint32_t iq_fifo_full   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ0_FIFO_EMPTY */
+	uint32_t iq0_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_FIFO_EMPTY */
+	uint32_t iq1_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_FIFO_EMPTY */
+	uint32_t iq2_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_FIFO_EMPTY */
+	uint32_t iq3_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_FIFO_EMPTY */
+	uint32_t iq4_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_FIFO_EMPTY */
+	uint32_t iq5_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_FIFO_EMPTY */
+	uint32_t iq6_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ7_FIFO_EMPTY */
+	uint32_t iq7_fifo_empty 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ0_FIFO_FULL */
+	uint32_t iq0_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ1_FIFO_FULL */
+	uint32_t iq1_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ2_FIFO_FULL */
+	uint32_t iq2_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ3_FIFO_FULL */
+	uint32_t iq3_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ4_FIFO_FULL */
+	uint32_t iq4_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ5_FIFO_FULL */
+	uint32_t iq5_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ6_FIFO_FULL */
+	uint32_t iq6_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ7_FIFO_FULL */
+	uint32_t iq7_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+	uint32_t rsv2           	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT ;
+#endif
+
+/*****************************************************************************************/
+/* DBG_RBOUT_SEL                                                                         */
+/* Debug Runner Buffer output selection                                                  */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_RSV_RSV_VALUE                                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_RSV_RSV_VALUE_RESET_VALUE                      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_SHRTPKT_OUT_DISABLE_VALUE                  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_SHRTPKT_OUT_DISABLE_VALUE_RESET_VALUE      ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_SHRTPKT_OUT_ENABLE_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_BAC_BBHCLASS_OUT_DISABLE_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_BAC_BBHCLASS_OUT_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_BAC_BBHCLASS_OUT_ENABLE_VALUE              ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY4_OUT_DISABLE_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY4_OUT_DISABLE_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY4_OUT_ENABLE_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY3_OUT_DISABLE_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY3_OUT_DISABLE_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY3_OUT_ENABLE_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY2_OUT_DISABLE_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY2_OUT_DISABLE_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY2_OUT_ENABLE_VALUE                      ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY1_OUT_DISABLE_VALUE                     ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY1_OUT_DISABLE_VALUE_RESET_VALUE         ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY1_OUT_ENABLE_VALUE                      ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_OFFSET ( 0x000002CC )
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv                 	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_SHRTPKT_OUT */
+	uint32_t dbg_shrtpkt_out     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_BAC_ORGCLASS_OUT */
+	uint32_t dbg_bac_bbhclass_out	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY4_OUT */
+	uint32_t dbg_key4_out        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY3_OUT */
+	uint32_t dbg_key3_out        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY2_OUT */
+	uint32_t dbg_key2_out        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY1_OUT */
+	uint32_t dbg_key1_out        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL ;
+#else
+typedef struct
+{
+	/* DBG_KEY1_OUT */
+	uint32_t dbg_key1_out        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY2_OUT */
+	uint32_t dbg_key2_out        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY3_OUT */
+	uint32_t dbg_key3_out        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY4_OUT */
+	uint32_t dbg_key4_out        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_BAC_ORGCLASS_OUT */
+	uint32_t dbg_bac_bbhclass_out	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_SHRTPKT_OUT */
+	uint32_t dbg_shrtpkt_out     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv                 	: 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL ;
+#endif
+
+/*****************************************************************************************/
+/* DBG_CRITICAL_STAT                                                                     */
+/* Status/alarm register, which includes indicators of system failures: like stuck in lo */
+/* ok-up procedure, egress FIFO full, etc.                                               */
+/*****************************************************************************************/
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_RSV_RSV_VALUE                                    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_RSV_RSV_VALUE_RESET_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_PKT_CMD_FIFO_FULL_NOT_FULL_VALUE              ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_PKT_CMD_FIFO_FULL_NOT_FULL_VALUE_RESET_VALUE  ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_PKT_CMD_FIFO_FULL_FULL_VALUE                  ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_MSGTX_FIFO_FULL_NOT_FULL_VALUE                ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_MSGTX_FIFO_FULL_NOT_FULL_VALUE_RESET_VALUE    ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_MSGTX_FIFO_FULL_FULL_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_DATATX_FIFO_FULL_NOT_FULL_VALUE               ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_DATATX_FIFO_FULL_NOT_FULL_VALUE_RESET_VALUE   ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_DATATX_FIFO_FULL_FULL_VALUE                   ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LUT_PKT_CMD_FIFO_FULL_NOT_FULL_VALUE             ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LUT_PKT_CMD_FIFO_FULL_NOT_FULL_VALUE_RESET_VALUE ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LUT_PKT_CMD_FIFO_FULL_FULL_VALUE                 ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP4_STUCK_N_STUCK_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP4_STUCK_N_NOT_STUCK_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP4_STUCK_N_NOT_STUCK_VALUE_RESET_VALUE        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP3_STUCK_N_STUCK_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP3_STUCK_N_NOT_STUCK_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP3_STUCK_N_NOT_STUCK_VALUE_RESET_VALUE        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP2_STUCK_N_STUCK_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP2_STUCK_N_NOT_STUCK_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP2_STUCK_N_NOT_STUCK_VALUE_RESET_VALUE        ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP1_STUCK_N_STUCK_VALUE                        ( 0x0 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP1_STUCK_N_NOT_STUCK_VALUE                    ( 0x1 )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP1_STUCK_N_NOT_STUCK_VALUE_RESET_VALUE        ( 0x1 )
+
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_OFFSET ( 0x000002D0 )
+
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_ADDRESS   	( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_OFFSET )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_READ( r ) 	READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_ADDRESS ), (r) )
+#define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_WRITE( v )	WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv                  	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EQ_PKT_CMD_FIFO_FULL */
+	uint32_t eq_pkt_cmd_fifo_full 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EQ_MSGTX_FIFO_FULL */
+	uint32_t eq_msgtx_fifo_full   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EQ_DATATX_FIFO_FULL */
+	uint32_t eq_datatx_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LUT_PKT_CMD_FIFO_FULL */
+	uint32_t lut_pkt_cmd_fifo_full	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP4_STUCK_N */
+	uint32_t lkup4_stuck_n        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP3_STUCK_N */
+	uint32_t lkup3_stuck_n        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP2_STUCK_N */
+	uint32_t lkup2_stuck_n        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP1_STUCK_N */
+	uint32_t lkup1_stuck_n        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT ;
+#else
+typedef struct
+{
+	/* LKUP1_STUCK_N */
+	uint32_t lkup1_stuck_n        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP2_STUCK_N */
+	uint32_t lkup2_stuck_n        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP3_STUCK_N */
+	uint32_t lkup3_stuck_n        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP4_STUCK_N */
+	uint32_t lkup4_stuck_n        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LUT_PKT_CMD_FIFO_FULL */
+	uint32_t lut_pkt_cmd_fifo_full	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EQ_DATATX_FIFO_FULL */
+	uint32_t eq_datatx_fifo_full  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EQ_MSGTX_FIFO_FULL */
+	uint32_t eq_msgtx_fifo_full   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EQ_PKT_CMD_FIFO_FULL */
+	uint32_t eq_pkt_cmd_fifo_full 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+	uint32_t rsv                  	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT ;
+#endif
+
+typedef struct
+{
+	/* LKUP_TBL0_LUT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG lkup_tbl0_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL1_LUT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG lkup_tbl1_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL2_LUT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG lkup_tbl2_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL3_LUT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG lkup_tbl3_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL4_LUT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG lkup_tbl4_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL5_LUT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG lkup_tbl5_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL6_LUT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG lkup_tbl6_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL7_LUT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG lkup_tbl7_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL8_LUT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG lkup_tbl8_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL9_LUT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG lkup_tbl9_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL0_CAM_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG lkup_tbl0_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL1_CAM_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG lkup_tbl1_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL2_CAM_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG lkup_tbl2_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL3_CAM_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG lkup_tbl3_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL4_CAM_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG lkup_tbl4_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL5_CAM_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG lkup_tbl5_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL6_CAM_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG lkup_tbl6_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL7_CAM_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG lkup_tbl7_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL8_CAM_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG lkup_tbl8_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL9_CAM_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG lkup_tbl9_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL0_LUT_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG lkup_tbl0_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL1_LUT_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG lkup_tbl1_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL2_LUT_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG lkup_tbl2_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL3_LUT_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG lkup_tbl3_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL4_LUT_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG lkup_tbl4_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL5_LUT_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG lkup_tbl5_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL6_LUT_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG lkup_tbl6_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL7_LUT_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG lkup_tbl7_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL8_LUT_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG lkup_tbl8_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL9_LUT_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG lkup_tbl9_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 4 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL0_CAM_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG lkup_tbl0_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL1_CAM_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG lkup_tbl1_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL2_CAM_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG lkup_tbl2_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL3_CAM_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG lkup_tbl3_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL4_CAM_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG lkup_tbl4_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL5_CAM_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG lkup_tbl5_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL6_CAM_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG lkup_tbl6_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL7_CAM_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG lkup_tbl7_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL8_CAM_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG lkup_tbl8_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved2 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL9_CAM_CNXT_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG lkup_tbl9_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL0_KEY_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG lkup_tbl0_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL0_KEY_P0_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL lkup_tbl0_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL0_KEY_P0_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH lkup_tbl0_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL0_KEY_P1_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL lkup_tbl0_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL0_KEY_P1_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH lkup_tbl0_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL1_KEY_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG lkup_tbl1_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL1_KEY_P0_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL lkup_tbl1_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL1_KEY_P0_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH lkup_tbl1_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL1_KEY_P1_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL lkup_tbl1_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL1_KEY_P1_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH lkup_tbl1_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL2_KEY_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG lkup_tbl2_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL2_KEY_P0_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL lkup_tbl2_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL2_KEY_P0_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH lkup_tbl2_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL2_KEY_P1_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL lkup_tbl2_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL2_KEY_P1_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH lkup_tbl2_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL3_KEY_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG lkup_tbl3_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL3_KEY_P0_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL lkup_tbl3_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL3_KEY_P0_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH lkup_tbl3_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL3_KEY_P1_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL lkup_tbl3_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL3_KEY_P1_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH lkup_tbl3_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL4_KEY_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG lkup_tbl4_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL4_KEY_P0_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL lkup_tbl4_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL4_KEY_P0_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH lkup_tbl4_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL4_KEY_P1_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL lkup_tbl4_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL4_KEY_P1_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH lkup_tbl4_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL5_KEY_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG lkup_tbl5_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL5_KEY_P0_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL lkup_tbl5_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL5_KEY_P0_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH lkup_tbl5_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL5_KEY_P1_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL lkup_tbl5_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL5_KEY_P1_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH lkup_tbl5_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL6_KEY_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG lkup_tbl6_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL6_KEY_P0_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL lkup_tbl6_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL6_KEY_P0_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH lkup_tbl6_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL6_KEY_P1_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL lkup_tbl6_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL6_KEY_P1_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH lkup_tbl6_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL7_KEY_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG lkup_tbl7_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL7_KEY_P0_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL lkup_tbl7_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL7_KEY_P0_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH lkup_tbl7_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL7_KEY_P1_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL lkup_tbl7_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved3 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL7_KEY_P1_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH lkup_tbl7_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL8_KEY_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG lkup_tbl8_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL8_KEY_P0_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL lkup_tbl8_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL8_KEY_P0_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH lkup_tbl8_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL8_KEY_P1_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL lkup_tbl8_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL8_KEY_P1_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH lkup_tbl8_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL9_KEY_CFG */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG lkup_tbl9_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL9_KEY_P0_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL lkup_tbl9_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL9_KEY_P0_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH lkup_tbl9_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL9_KEY_P1_MASKL */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL lkup_tbl9_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL9_KEY_P1_MASKH */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH lkup_tbl9_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL0_GL_MASK */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK lkup_tbl0_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL1_GL_MASK */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK lkup_tbl1_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL2_GL_MASK */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK lkup_tbl2_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL3_GL_MASK */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK lkup_tbl3_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL4_GL_MASK */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK lkup_tbl4_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL5_GL_MASK */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK lkup_tbl5_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL6_GL_MASK */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK lkup_tbl6_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL7_GL_MASK */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK lkup_tbl7_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL8_GL_MASK */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK lkup_tbl8_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LKUP_TBL9_GL_MASK */
+	IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK lkup_tbl9_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_LOOKUP_CONFIGURATION ;
+
+typedef struct
+{
+	/* DA_FILT0_VAL_L */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L da_filt0_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT0_MASK_L */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L da_filt0_mask_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT0_CFG_H */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H da_filt0_cfg_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PARSER_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG parser_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_Ethertype */
+	IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE qtag_ethtype __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* QTAG_Nesting */
+	IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST qtag_nest __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Snap_organization_code */
+	IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE snap_org_code __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_configurtion_0_1 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1 user_ethtype_0_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_configurtion_2_3 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3 user_ethtype_2_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Ethertype_Configuration */
+	IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG user_ethtype_config __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_Configuration_0_1 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1 vid_0_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_Configuration_2_3 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3 vid_2_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_Configuration_4_5 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5 vid_4_5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_Configuration_6_7 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7 vid_6_7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_Configuration_8_9 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9 vid_8_9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* VID_Configuration_10_11 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11 vid_10_11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_defined_IP_Protocl */
+	IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT user_ip_prot __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PPP_IP_Protocol_Code */
+	IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE ppp_ip_prot_code __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER0_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG ip_filter0_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER1_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG ip_filter1_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER2_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG ip_filter2_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER3_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG ip_filter3_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT1_VAL_L */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L da_filt1_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT1_MASK_L */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L da_filt1_mask_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT1_CFG_H */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H da_filt1_cfg_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT2_VAL_L */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L da_filt2_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT2_VAL_H */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H da_filt2_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT3_VAL_L */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L da_filt3_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT3_VAL_H */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H da_filt3_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT4_VAL_L */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L da_filt4_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT4_VAL_H */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H da_filt4_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT5_VAL_L */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L da_filt5_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT5_VAL_H */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H da_filt5_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT_VALID_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG da_filt_valid_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER0_MASK_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG ip_filter0_mask_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER1_MASK_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG ip_filter1_mask_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER2_MASK_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG ip_filter2_mask_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTER3_MASK_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG ip_filter3_mask_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IP_FILTERS_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG ip_filters_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GRE_PROTOCOL_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG gre_protocol_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL0_R0 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0 dscp2tci_tbl0_r0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL0_R1 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1 dscp2tci_tbl0_r1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL0_R2 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2 dscp2tci_tbl0_r2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL0_R3 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3 dscp2tci_tbl0_r3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL0_R4 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4 dscp2tci_tbl0_r4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL0_R5 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5 dscp2tci_tbl0_r5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL0_R6 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6 dscp2tci_tbl0_r6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL0_R7 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7 dscp2tci_tbl0_r7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL1_R0 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0 dscp2tci_tbl1_r0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL1_R1 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1 dscp2tci_tbl1_r1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL1_R2 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2 dscp2tci_tbl1_r2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL1_R3 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3 dscp2tci_tbl1_r3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL1_R4 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4 dscp2tci_tbl1_r4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL1_R5 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5 dscp2tci_tbl1_r5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL1_R6 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6 dscp2tci_tbl1_r6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP2TCI_TBL1_R7 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7 dscp2tci_tbl1_r7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DEFAULT_TCI_TBL0 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0 default_tci_tbl0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DEFAULT_TCI_TBL1 */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1 default_tci_tbl1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DSCP_TBL_VALID_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG dscp_tbl_valid_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT6_VAL_L */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L da_filt6_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT6_VAL_H */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H da_filt6_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT7_VAL_L */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L da_filt7_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DA_FILT7_VAL_H */
+	IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H da_filt7_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IPV6_HDR_EXT_FLTR_MASK_CFG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG ipv6_hdr_ext_fltr_mask_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENG */
+	IH_REGS_PARSER_CORE_CONFIGURATION_ENG eng __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_PARSER_CORE_CONFIGURATION ;
+
+typedef struct
+{
+	/* SP2IQ_MAP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG sp2iq_map_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ_BASE_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG iq_base_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ_SIZE_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG iq_size_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQL_PRIOR_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG iql_prior_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQH_PRIOR_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG iqh_prior_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PHL_OFFSET_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG phl_offset_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PHH_OFFSET_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG phh_offset_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 4 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQ_WEIGHT_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG iq_weight_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQL_CNGS_THRS_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG iql_cngs_thrs_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IQH_CNGS_THRS_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG iqh_cngs_thrs_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved2 [ 4 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_RB_BASE */
+	IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE rnra_rb_base __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_RB_BASE */
+	IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE rnrb_rb_base __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_IHRSP_ADDR */
+	IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR rnra_ihrsp_addr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_IHRSP_ADDR */
+	IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR rnrb_ihrsp_addr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_CNGS_RPT_ADDR */
+	IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR rnra_cngs_rpt_addr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_CNGS_RPT_ADDR */
+	IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR rnrb_cngs_rpt_addr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_CNGS_RPT_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG rnr_cngs_rpt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RADDR0_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG raddr0_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RADDR1_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG raddr1_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RBPM_BAT_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG rbpm_bat_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RBPM_BAC_STAT */
+	IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT rbpm_bac_stat __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRGT_MTRX_ETH0_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG trgt_mtrx_eth0_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRGT_MTRX_ETH1_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG trgt_mtrx_eth1_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRGT_MTRX_ETH2_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG trgt_mtrx_eth2_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRGT_MTRX_ETH3_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG trgt_mtrx_eth3_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRGT_MTRX_ETH4_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG trgt_mtrx_eth4_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRGT_MTRX_GPON_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG trgt_mtrx_gpon_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_MISC_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG ih_misc_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY0 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0 ih_class_key0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY1 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1 ih_class_key1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY2 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2 ih_class_key2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY3 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3 ih_class_key3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY4 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4 ih_class_key4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY5 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5 ih_class_key5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY6 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6 ih_class_key6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY7 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7 ih_class_key7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY8 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8 ih_class_key8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY9 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9 ih_class_key9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved3 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY10 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10 ih_class_key10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY11 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11 ih_class_key11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY12 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12 ih_class_key12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY13 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13 ih_class_key13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY14 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14 ih_class_key14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_KEY15 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15 ih_class_key15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK0 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0 ih_class_mask0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK1 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1 ih_class_mask1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK2 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2 ih_class_mask2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK3 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3 ih_class_mask3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK4 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4 ih_class_mask4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK5 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5 ih_class_mask5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK6 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6 ih_class_mask6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK7 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7 ih_class_mask7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK8 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8 ih_class_mask8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK9 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9 ih_class_mask9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK10 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10 ih_class_mask10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK11 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11 ih_class_mask11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK12 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12 ih_class_mask12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK13 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13 ih_class_mask13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK14 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14 ih_class_mask14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS_MASK15 */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15 ih_class_mask15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS0_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG ih_class0_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS1_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG ih_class1_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS2_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG ih_class2_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS3_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG ih_class3_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS4_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG ih_class4_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS5_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG ih_class5_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS6_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG ih_class6_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS7_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG ih_class7_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS8_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG ih_class8_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS9_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG ih_class9_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS10_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG ih_class10_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS11_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG ih_class11_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS12_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG ih_class12_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS13_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG ih_class13_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS14_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG ih_class14_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS15_GENERAL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG ih_class15_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS0_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG ih_class0_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS1_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG ih_class1_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved4 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS2_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG ih_class2_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS3_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG ih_class3_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS4_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG ih_class4_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS5_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG ih_class5_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS6_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG ih_class6_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS7_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG ih_class7_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS8_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG ih_class8_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS9_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG ih_class9_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS10_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG ih_class10_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS11_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG ih_class11_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS12_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG ih_class12_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS13_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG ih_class13_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS14_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG ih_class14_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLASS15_SEARCH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG ih_class15_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_CNGS_TRSH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG rnra_cngs_trsh_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_CNGS_TRSH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG rnrb_cngs_trsh_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* WAN_PER_PORT_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG wan_per_port_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PARSE_LAYER_PER_PORT_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG parse_layer_per_port_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROP_SIZE_PER_PORT_CFG0 */
+	IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0 prop_size_per_port_cfg0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROP_SIZE_PER_PORT_CFG1 */
+	IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1 prop_size_per_port_cfg1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLSF_MAPL_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG ih_clsf_mapl_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IH_CLSF_MAPH_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG ih_clsf_maph_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRGT_MTRX_PCIE0_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG trgt_mtrx_pcie0_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRGT_MTRX_PCIE1_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG trgt_mtrx_pcie1_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FW_EN_MTRX_ETH0_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG fw_en_mtrx_eth0_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FW_EN_MTRX_ETH1_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG fw_en_mtrx_eth1_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FW_EN_MTRX_ETH2_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG fw_en_mtrx_eth2_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FW_EN_MTRX_ETH3_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG fw_en_mtrx_eth3_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FW_EN_MTRX_ETH4_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG fw_en_mtrx_eth4_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FW_EN_MTRX_GPON_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG fw_en_mtrx_gpon_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FW_EN_MTRX_PCIE0_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG fw_en_mtrx_pcie0_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FW_EN_MTRX_PCIE1_SP_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG fw_en_mtrx_pcie1_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PH_MEM_RD_RQST_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG ph_mem_rd_rqst_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PH_MEM_RD_DATA_LOW */
+	IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW ph_mem_rd_data_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PH_MEM_RD_DATA_HIGH */
+	IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH ph_mem_rd_data_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_REG_0 */
+	IH_REGS_GENERAL_CONFIGURATION_SN_REG_0 sn_reg_0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_REG_1 */
+	IH_REGS_GENERAL_CONFIGURATION_SN_REG_1 sn_reg_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_REG_2 */
+	IH_REGS_GENERAL_CONFIGURATION_SN_REG_2 sn_reg_2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SN_REG_3 */
+	IH_REGS_GENERAL_CONFIGURATION_SN_REG_3 sn_reg_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LOCAL_MEM_RD_RQST_CFG */
+	IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG local_mem_rd_rqst_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LOCAL_MEM_RD_DATA_LOW */
+	IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW local_mem_rd_data_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LOCAL_MEM_RD_DATA_HIGH */
+	IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH local_mem_rd_data_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY1_LOW */
+	IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW dbg_key1_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY1_HIGH */
+	IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH dbg_key1_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY2_LOW */
+	IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW dbg_key2_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY2_HIGH */
+	IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH dbg_key2_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY3_LOW */
+	IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW dbg_key3_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY3_HIGH */
+	IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH dbg_key3_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY4_LOW */
+	IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW dbg_key4_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_KEY4_HIGH */
+	IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH dbg_key4_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_IQ_STAT */
+	IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT dbg_iq_stat __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_RBOUT_SEL */
+	IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL dbg_rbout_sel __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DBG_CRITICAL_STAT */
+	IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT dbg_critical_stat __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS_GENERAL_CONFIGURATION ;
+
+typedef struct
+{
+	/* lookup_configuration function */
+	IH_REGS_LOOKUP_CONFIGURATION lookup_configuration __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved0 [ 624 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* parser_core_configuration function */
+	IH_REGS_PARSER_CORE_CONFIGURATION parser_core_configuration __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 764 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* general_configuration function */
+	IH_REGS_GENERAL_CONFIGURATION general_configuration __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+IH_REGS ;
+
+typedef struct
+{
+	/* REGS */
+	IH_REGS regs __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ 
+IH_FOR_ALL ;
+#endif /* IH_H_INCLUDED */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_map.h b/arch/arm/mach-bcmbca/rdp/rdp_map.h
new file mode 100755
index 0000000000..c6b7ed822d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_map.h
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/             
+
+#ifndef __9631X8_RDP_MAP_H
+#define __9631X8_RDP_MAP_H
+
+#include <asm/arch/rdp.h>
+
+/*****************************************************************************************/
+/* BBH Blocks offsets                                                                        */
+/*****************************************************************************************/
+#define BBH_TX_0_OFFSET				( RDP_BASE + 0x000e8000 )
+#define BBH_TX_1_OFFSET				( RDP_BASE + 0x000ea000 )
+#define BBH_TX_2_OFFSET				( RDP_BASE + 0x000ec000 )
+#define BBH_TX_3_OFFSET				( RDP_BASE + 0x000ee000 )
+#define BBH_TX_4_OFFSET				( RDP_BASE + 0x000f0000 )
+#define BBH_TX_5_OFFSET				( RDP_BASE + 0x000f2000 )
+#define BBH_TX_6_OFFSET				( RDP_BASE + 0x000f4000 )
+#define BBH_TX_7_OFFSET				( RDP_BASE + 0x000f6000 )
+#define BBH_RX_0_OFFSET				( RDP_BASE + 0x000de000 )
+#define BBH_RX_1_OFFSET				( RDP_BASE + 0x000de800 )
+#define BBH_RX_2_OFFSET				( RDP_BASE + 0x000df000 )
+#define BBH_RX_3_OFFSET				( RDP_BASE + 0x000df800 )
+#define BBH_RX_4_OFFSET				( RDP_BASE + 0x000e0000 )
+#define BBH_RX_5_OFFSET				( RDP_BASE + 0x000e0400 )
+#define BBH_RX_6_OFFSET				( RDP_BASE + 0x000e1000 )
+#define BBH_RX_7_OFFSET				( RDP_BASE + 0x000e2000 )
+/*****************************************************************************************/
+/* BPM Blocks offsets                                                                        */
+/*****************************************************************************************/
+#define BPM_MODULE_OFFSET			( RDP_BASE + 0x000c4000 )
+/*****************************************************************************************/
+/* SBPM Blocks offsets                                                                        */
+/*****************************************************************************************/
+#define SBPM_BLOCK_OFFSET			( RDP_BASE + 0x000c8000 )
+/*****************************************************************************************/
+/* DMA Blocks offsets                                                                        */
+/*****************************************************************************************/
+#define DMA_REGS_0_OFFSET			( RDP_BASE + 0x000d1000 )
+#define DMA_REGS_1_OFFSET			( RDP_BASE + 0x000d1800 )
+/*****************************************************************************************/
+/* IH Blocks offsets                                                                        */
+/*****************************************************************************************/
+#define IH_REGS_OFFSET				( RDP_BASE + 0x000d0000 )
+/*****************************************************************************************/
+/* PSRAM Blocks offsets                                                                        */
+/*****************************************************************************************/
+#define PSRAM_BLOCK_OFFSET			( RDP_BASE + 0x000a0000  )
+/*****************************************************************************************/
+/* RUNNER Blocks offsets                                                                        */
+/*****************************************************************************************/
+#define RUNNER_COMMON_0_OFFSET		( RDP_BASE + 0x00000000 )
+#define RUNNER_COMMON_1_OFFSET		( RDP_BASE + 0x00040000 )
+#define RUNNER_PRIVATE_0_OFFSET		( RDP_BASE + 0x00010000 )
+#define RUNNER_PRIVATE_1_OFFSET		( RDP_BASE + 0x00050000 )
+#define RUNNER_INST_MAIN_0_OFFSET	( RDP_BASE + 0x00020000 )
+#define RUNNER_INST_MAIN_1_OFFSET	( RDP_BASE + 0x00060000 )
+#define RUNNER_CNTXT_MAIN_0_OFFSET	( RDP_BASE + 0x00028000 )
+#define RUNNER_CNTXT_MAIN_1_OFFSET	( RDP_BASE + 0x00068000 )
+#define RUNNER_PRED_MAIN_0_OFFSET	( RDP_BASE + 0x0002c000 )
+#define RUNNER_PRED_MAIN_1_OFFSET	( RDP_BASE + 0x0006c000 )
+#define RUNNER_INST_PICO_0_OFFSET	( RDP_BASE + 0x00030000 )
+#define RUNNER_INST_PICO_1_OFFSET	( RDP_BASE + 0x00070000 )
+#define RUNNER_CNTXT_PICO_0_OFFSET	( RDP_BASE + 0x00038000 )
+#define RUNNER_CNTXT_PICO_1_OFFSET	( RDP_BASE + 0x00078000 )
+#define RUNNER_PRED_PICO_0_OFFSET	( RDP_BASE + 0x0003c000 )
+#define RUNNER_PRED_PICO_1_OFFSET	( RDP_BASE + 0x0007c000 )
+#define RUNNER_REGS_0_OFFSET		( RDP_BASE + 0x00099000 )
+#define RUNNER_REGS_1_OFFSET		( RDP_BASE + 0x0009a000 )
+/*****************************************************************************************/
+/* UBUS MASTER Blocks offsets                                                            */
+/*****************************************************************************************/
+#define UBUS_MASTER_1_RDP_UBUS_MASTER_BRDG_REG_EN           ( RDP_BASE + 0x000d2000 )
+#define UBUS_MASTER_1_RDP_UBUS_MASTER_BRDG_REG_REQ_CNTRL    ( RDP_BASE + 0x000d2004 )
+#define UBUS_MASTER_1_RDP_UBUS_MASTER_BRDG_REG_HP           ( RDP_BASE + 0x000d200c )
+#define UBUS_MASTER_2_RDP_UBUS_MASTER_BRDG_REG_EN           ( RDP_BASE + 0x000d2400 )
+#define UBUS_MASTER_2_RDP_UBUS_MASTER_BRDG_REG_REQ_CNTRL    ( RDP_BASE + 0x000d2404 )
+#define UBUS_MASTER_2_RDP_UBUS_MASTER_BRDG_REG_HP           ( RDP_BASE + 0x000d240c )
+#define UBUS_MASTER_3_RDP_UBUS_MASTER_BRDG_REG_EN           ( RDP_BASE + 0x000d2800 )
+#define UBUS_MASTER_3_RDP_UBUS_MASTER_BRDG_REG_REQ_CNTRL    ( RDP_BASE + 0x000d2804 )
+#define UBUS_MASTER_3_RDP_UBUS_MASTER_BRDG_REG_HP           ( RDP_BASE + 0x000d280c )
+
+#endif
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_misc.c b/arch/arm/mach-bcmbca/rdp/rdp_misc.c
new file mode 100644
index 0000000000..15cc3dd7af
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_misc.c
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include "hwapi_mac.h"
+#include "rdp_drv_bbh.h"
+#include "rdp_ubus.h"
+
+int rdp_post_init(void)
+{
+    /* Ethernet WAN */
+    mac_hwapi_init_emac(DRV_BBH_EMAC_0);
+    mac_hwapi_set_unimac_cfg(DRV_BBH_EMAC_0,1);
+    mac_hwapi_set_rxtx_enable(DRV_BBH_EMAC_0,0,0);/* Ethernet WAN EMAC will be enabled when the WAN service gets created */
+    mac_hwapi_set_tx_max_frame_len(DRV_BBH_EMAC_0, 2048); /* Why do we set the max frame len here 'hard-coded' ??? FIXME */
+
+    /* SF2 */
+    mac_hwapi_init_emac(DRV_BBH_EMAC_1);
+    mac_hwapi_set_unimac_cfg(DRV_BBH_EMAC_1,1);
+    mac_hwapi_set_rxtx_enable(DRV_BBH_EMAC_1,1,1);
+    mac_hwapi_set_tx_max_frame_len(DRV_BBH_EMAC_1, 2048); /* Why do we set the max frame len here 'hard-coded' ??? FIXME */
+    mac_hwapi_set_backpressure_ext(DRV_BBH_EMAC_1, 1); /* Enable backpressure towards SF2 */
+
+    return 0;
+}
+
+void rdp_enable_ubus_masters(void)
+{
+    UBUS_UBUS_MASTER_BRDG_REG_EN ubus_en;
+    UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL ubus_req_ctl;
+    UBUS_UBUS_MASTER_BRDG_REG_HP ubus_hp;
+
+    /* Configuration taken from simulation registers. */
+
+    /*first Ubus Master*/
+    READ_32(UBUS_MASTER_1_RDP_UBUS_MASTER_BRDG_REG_REQ_CNTRL,ubus_req_ctl);
+    ubus_req_ctl.max_pkt_len = 0x90;
+    ubus_req_ctl.endian_mode = UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_ENDIAN_MODE_LB_VALUE;
+    WRITE_32(UBUS_MASTER_1_RDP_UBUS_MASTER_BRDG_REG_REQ_CNTRL,ubus_req_ctl);
+
+    READ_32(UBUS_MASTER_1_RDP_UBUS_MASTER_BRDG_REG_HP,ubus_hp);
+    ubus_hp.hp_en = 1;
+    ubus_hp.hp_cnt_high = 1;
+    ubus_hp.hp_cnt_total = 2;
+    WRITE_32(UBUS_MASTER_1_RDP_UBUS_MASTER_BRDG_REG_HP,ubus_hp);
+
+    READ_32(UBUS_MASTER_1_RDP_UBUS_MASTER_BRDG_REG_EN,ubus_en);
+    ubus_en.en = 1;
+    WRITE_32(UBUS_MASTER_1_RDP_UBUS_MASTER_BRDG_REG_EN,ubus_en);
+
+    /*second Ubus Master*/
+    READ_32(UBUS_MASTER_2_RDP_UBUS_MASTER_BRDG_REG_REQ_CNTRL,ubus_req_ctl);
+    ubus_req_ctl.max_pkt_len = 0x90;
+    ubus_req_ctl.endian_mode = UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_ENDIAN_MODE_LB_VALUE;
+    WRITE_32(UBUS_MASTER_2_RDP_UBUS_MASTER_BRDG_REG_REQ_CNTRL,ubus_req_ctl);
+
+    READ_32(UBUS_MASTER_2_RDP_UBUS_MASTER_BRDG_REG_HP,ubus_hp);
+    ubus_hp.hp_en = 1;
+    ubus_hp.hp_cnt_high = 11;
+    ubus_hp.hp_cnt_total = 13;
+    WRITE_32(UBUS_MASTER_2_RDP_UBUS_MASTER_BRDG_REG_HP,ubus_hp);
+
+    READ_32(UBUS_MASTER_2_RDP_UBUS_MASTER_BRDG_REG_EN,ubus_en);
+    ubus_en.en = 1;
+    WRITE_32(UBUS_MASTER_2_RDP_UBUS_MASTER_BRDG_REG_EN,ubus_en);
+
+    /*third Ubus Master*/
+    READ_32(UBUS_MASTER_3_RDP_UBUS_MASTER_BRDG_REG_REQ_CNTRL,ubus_req_ctl);
+    ubus_req_ctl.max_pkt_len = 0x90;
+    ubus_req_ctl.endian_mode = UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_ENDIAN_MODE_LB_VALUE;
+    WRITE_32(UBUS_MASTER_3_RDP_UBUS_MASTER_BRDG_REG_REQ_CNTRL,ubus_req_ctl);
+
+    READ_32(UBUS_MASTER_3_RDP_UBUS_MASTER_BRDG_REG_HP,ubus_hp);
+    ubus_hp.hp_en = 1;
+    ubus_hp.hp_comb = 1;
+    ubus_hp.hp_cnt_high = 1;
+    ubus_hp.hp_cnt_total = 6;
+    WRITE_32(UBUS_MASTER_3_RDP_UBUS_MASTER_BRDG_REG_HP,ubus_hp);
+
+    READ_32(UBUS_MASTER_3_RDP_UBUS_MASTER_BRDG_REG_EN,ubus_en);
+    ubus_en.en = 1;
+    WRITE_32(UBUS_MASTER_3_RDP_UBUS_MASTER_BRDG_REG_EN,ubus_en);
+
+    // UBUS arbitration configuration, done through clocks and reset (via PMC)
+}
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_mm.h b/arch/arm/mach-bcmbca/rdp/rdp_mm.h
new file mode 100755
index 0000000000..7e16a9b598
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_mm.h
@@ -0,0 +1,180 @@
+/*
+    <:copyright-BRCM:2014-2016:DUAL/GPL:standard
+    
+       Copyright (c) 2014-2016 Broadcom 
+       All Rights Reserved
+    
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License, version 2, as published by
+    the Free Software Foundation (the "GPL").
+    
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+    
+    
+    A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+    writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+    Boston, MA 02111-1307, USA.
+    
+    :>
+*/
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains inline functions for runner host memory management      */
+/*                                                                            */
+/******************************************************************************/
+#ifndef _RDP_MM_H_
+#define _RDP_MM_H_
+#include "bdmf_data_types.h"
+
+#if !defined(RDP_SIM)
+#define rdp_mm_aligned_alloc(_size, _phy_addr_p) __rdp_mm_aligned_alloc((_size), (_phy_addr_p), GFP_DMA)
+#define rdp_mm_aligned_alloc_atomic(_size, _phy_addr_p) __rdp_mm_aligned_alloc((_size), (_phy_addr_p), GFP_ATOMIC)
+
+#if defined(__UBOOT__)
+#undef rdp_mm_aligned_alloc
+#undef rdp_mm_aligned_alloc_atomic
+#define rdp_mm_aligned_alloc(_size, _phy_addr_p) __rdp_mm_aligned_alloc((_size), (_phy_addr_p), 0)
+#define rdp_mm_aligned_alloc_atomic(_size, _phy_addr_p) __rdp_mm_aligned_alloc((_size), (_phy_addr_p), 0)
+#endif
+
+static inline void *__rdp_mm_aligned_alloc(uint32_t size,
+					   bdmf_phys_addr_t * phy_addr_p,
+					   gfp_t gfp)
+{
+#if !defined(__UBOOT__) && defined(__KERNEL__) && (defined(CONFIG_ARM) || defined(CONFIG_ARM64))
+	dma_addr_t phy_addr;
+	uint32_t size_padded_aligned = (size + (sizeof(dma_addr_t) << 1) - 1) & ~(sizeof(dma_addr_t) - 1);	/* must be multiple of pointer size */
+	dma_addr_t *mem;
+
+	if (rdp_dummy_dev == NULL)
+		return NULL;
+
+	/* memory allocation of dma_alloc_coherent for ARM is aligned to page size which is aligned to cache */
+	mem =
+	    (dma_addr_t *) dma_alloc_coherent(rdp_dummy_dev,
+					      size_padded_aligned, &phy_addr,
+					      gfp);
+	if (unlikely(mem == NULL))
+		return NULL;
+	/*  printk("\n\tsize %u, size32 %u, mem %p, &mem[size] %p, phy_addr 0x%08x\n\n", size, size32, mem, &mem[(size32-sizeof(void *))>>2], phy_addr); */
+	mem[(size_padded_aligned / sizeof(dma_addr_t)) - 1] = phy_addr;
+	*phy_addr_p = (bdmf_phys_addr_t) phy_addr;
+	return (void *)mem;
+#else
+	/* we are trying to make sure the start of the ring is cache line aligned,
+	 * and we need an additional memory to hold (void *) just right before the
+	 * start of the ring. So we are allocating 1 more cache line + sizeof(void *) */
+	unsigned long cache_line = DMA_CACHE_LINE;
+	void *mem =
+	    (void *)NONCACHED_MALLOC_ATOMIC(size + cache_line + sizeof(void *));
+	void **ptr =
+	    (void **)(((uintptr_t) mem + cache_line + (sizeof(void *))) &
+		      ~(cache_line - 1));
+	ptr[-1] = mem;
+	*phy_addr_p = VIRT_TO_PHYS(ptr);
+
+	return (void *)ptr;
+#endif
+}
+
+static inline void rdp_mm_aligned_free(void *ptr, uint32_t size)
+{
+#if !defined(__UBOOT__) && defined(__KERNEL__) && (defined(CONFIG_ARM) || defined(CONFIG_ARM64))
+	uint32_t size_padded_aligned = (size + (sizeof(void *) << 1) - 1) & ~(sizeof(void *) - 1);	/* must be multiple of pointer size */
+	dma_addr_t *mem = ptr;
+	dma_addr_t phy_addr =
+	    mem[(size_padded_aligned / sizeof(dma_addr_t)) - 1];
+	dma_free_coherent(rdp_dummy_dev, size_padded_aligned, ptr, phy_addr);
+#else
+	NONCACHED_FREE(((void **)ptr)[-1]);
+#endif
+}
+
+#else /* for simulator */
+
+#define rdp_mm_aligned_alloc(_size, _phy_addr_p) __rdp_mm_aligned_alloc((_size), (_phy_addr_p))
+#define rdp_mm_aligned_alloc_atomic(_size, _phy_addr_p) __rdp_mm_aligned_alloc((_size), (_phy_addr_p))
+static inline void *__rdp_mm_aligned_alloc(uint32_t size,
+					   bdmf_phys_addr_t * phy_addr_p)
+{
+#ifdef XRDP
+	void *mem;
+	void **ptr;
+	uint32_t size_padded_aligned;
+
+	size_padded_aligned = (2 * size) + sizeof(void *);
+	mem = bdmf_alloc_rsv(size_padded_aligned, phy_addr_p);
+	if (!mem)
+		return NULL;
+	*phy_addr_p += (size + sizeof(void *));
+	*phy_addr_p &= ~(size - 1);
+	ptr = rsv_phys_to_virt(*phy_addr_p);
+	ptr[-1] = mem;
+	return ptr;
+#else
+	void *phys_addr = malloc(size);
+
+	*phy_addr_p = (bdmf_phys_addr_t) phys_addr;
+	return phys_addr;
+#endif
+}
+
+static inline void rdp_mm_aligned_free(void *ptr, uint32_t size)
+{
+#ifdef XRDP
+/* in case of simulator we don't free the memory because we don't manage shared memory segments */
+#ifdef XRDP_EMULATION
+	bdmf_free(((void **)ptr)[-1]);
+#endif
+#else
+	free(ptr);
+#endif
+}
+#endif
+
+static inline void rdp_mm_setl_context(void *__to, unsigned int __val,
+				       unsigned int __n)
+{
+	volatile unsigned int *dst = (volatile unsigned int *)__to;
+	int i;
+
+	for (i = 0; i < (__n / 4); i++, dst++) {
+		if ((i & 0x3) == 3)
+			continue;
+
+		*dst = __val;	/* DSL */
+	}
+}
+
+static inline void rdp_mm_setl(void *__to, unsigned int __val, unsigned int __n)
+{
+	volatile unsigned int *dst = (volatile unsigned int *)__to;
+	int i;
+
+	for (i = 0; i < (__n / 4); i++, dst++) {
+		*dst = __val;	/* DSL */
+	}
+}
+
+static inline void rdp_mm_cpyl_context(void *__to, void *__from,
+				       unsigned int __n)
+{
+	volatile unsigned int *src = (unsigned int *)__from;
+	volatile unsigned int *dst = (unsigned int *)__to;
+	int i, n = __n / 4;
+
+	for (i = 0; i < n; i++, src++, dst++) {
+		if ((i & 0x3) == 3)
+			continue;
+
+		*dst = swap4bytes(*src);
+	}
+}
+
+#endif
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_runner.h b/arch/arm/mach-bcmbca/rdp/rdp_runner.h
new file mode 100755
index 0000000000..9667f571ba
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_runner.h
@@ -0,0 +1,7018 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/             
+
+#ifndef __RUNNER_H_INCLUDED
+#define __RUNNER_H_INCLUDED
+
+/*  File automatically generated by Reggae at 15/08/2013  10:55:07   */
+
+#include "access_macros.h"
+#ifndef __PACKING_ATTRIBUTE_STRUCT_END__
+#include "packing.h"
+#endif
+#include "rdp_map.h"
+
+/*****************************************************************************************/
+/* Runner VPB address space                                                              */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Blocks offsets                                                                        */
+/*****************************************************************************************/
+/*****************************************************************************************/
+/* Functions offsets and addresses                                                       */
+/*****************************************************************************************/
+#define RUNNER_COMMON_0_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_COMMON_0_MEM_ADDRESS	( RUNNER_COMMON_0_OFFSET + RUNNER_COMMON_0_MEM_OFFSET )
+
+/** Number of entries of the function into block **/
+#define RUNNER_COMMON_MEM_COUNTER ( 4096 )
+/** Number of registers per entry **/
+#define RUNNER_COMMON_MEM_IN_OFFSET ( 8 )
+
+#define RUNNER_COMMON_1_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_COMMON_1_MEM_ADDRESS	( RUNNER_COMMON_1_OFFSET + RUNNER_COMMON_1_MEM_OFFSET )
+
+#define RUNNER_PRIVATE_0_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_PRIVATE_0_MEM_ADDRESS	( RUNNER_PRIVATE_0_OFFSET + RUNNER_PRIVATE_0_MEM_OFFSET )
+
+/** Number of entries of the function into block **/
+#define RUNNER_PRIVATE_MEM_COUNTER ( 6144 )
+/** Number of registers per entry **/
+#define RUNNER_PRIVATE_MEM_IN_OFFSET ( 8 )
+
+#define RUNNER_PRIVATE_1_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_PRIVATE_1_MEM_ADDRESS	( RUNNER_PRIVATE_1_OFFSET + RUNNER_PRIVATE_1_MEM_OFFSET )
+
+#define RUNNER_INST_MAIN_0_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_INST_MAIN_0_MEM_ADDRESS	( RUNNER_INST_MAIN_0_OFFSET + RUNNER_INST_MAIN_0_MEM_OFFSET )
+
+/** Number of entries of the function into block **/
+#define RUNNER_INST_MAIN_MEM_COUNTER ( 7168 )
+
+/** Number of registers per entry **/
+#define RUNNER_INST_MAIN_MEM_IN_OFFSET ( 4 )
+
+#define RUNNER_INST_MAIN_1_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_INST_MAIN_1_MEM_ADDRESS	( RUNNER_INST_MAIN_1_OFFSET + RUNNER_INST_MAIN_1_MEM_OFFSET )
+
+#define RUNNER_CNTXT_MAIN_0_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_CNTXT_MAIN_0_MEM_ADDRESS	( RUNNER_CNTXT_MAIN_0_OFFSET + RUNNER_CNTXT_MAIN_0_MEM_OFFSET )
+
+/** Number of entries of the function into block **/
+#define RUNNER_CNTXT_MAIN_MEM_COUNTER ( 1024 )
+/** Number of registers per entry **/
+#define RUNNER_CNTXT_MAIN_MEM_IN_OFFSET ( 4 )
+
+#define RUNNER_CNTXT_MAIN_1_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_CNTXT_MAIN_1_MEM_ADDRESS	( RUNNER_CNTXT_MAIN_1_OFFSET + RUNNER_CNTXT_MAIN_1_MEM_OFFSET )
+
+#define RUNNER_PRED_MAIN_0_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_PRED_MAIN_0_MEM_ADDRESS	( RUNNER_PRED_MAIN_0_OFFSET + RUNNER_PRED_MAIN_0_MEM_OFFSET )
+
+#define RUNNER_PRED_MAIN_1_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_PRED_MAIN_1_MEM_ADDRESS	( RUNNER_PRED_MAIN_1_OFFSET + RUNNER_PRED_MAIN_1_MEM_OFFSET )
+
+#define RUNNER_INST_PICO_0_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_INST_PICO_0_MEM_ADDRESS	( RUNNER_INST_PICO_0_OFFSET + RUNNER_INST_PICO_0_MEM_OFFSET )
+
+/** Number of entries of the function into block **/
+#define RUNNER_INST_PICO_MEM_COUNTER ( 4096 )
+
+/** Number of registers per entry **/
+#define RUNNER_INST_PICO_MEM_IN_OFFSET ( 4 )
+
+#define RUNNER_INST_PICO_1_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_INST_PICO_1_MEM_ADDRESS	( RUNNER_INST_PICO_1_OFFSET + RUNNER_INST_PICO_1_MEM_OFFSET )
+
+#define RUNNER_CNTXT_PICO_0_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_CNTXT_PICO_0_MEM_ADDRESS	( RUNNER_CNTXT_PICO_0_OFFSET + RUNNER_CNTXT_PICO_0_MEM_OFFSET )
+
+/** Number of entries of the function into block **/
+#define RUNNER_CNTXT_PICO_MEM_COUNTER ( 512 )
+/** Number of registers per entry **/
+#define RUNNER_CNTXT_PICO_MEM_IN_OFFSET ( 4 )
+
+#define RUNNER_CNTXT_PICO_1_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_CNTXT_PICO_1_MEM_ADDRESS	( RUNNER_CNTXT_PICO_1_OFFSET + RUNNER_CNTXT_PICO_1_MEM_OFFSET )
+
+#define RUNNER_PRED_PICO_0_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_PRED_PICO_0_MEM_ADDRESS	( RUNNER_PRED_PICO_0_OFFSET + RUNNER_PRED_PICO_0_MEM_OFFSET )
+
+#define RUNNER_PRED_PICO_1_MEM_OFFSET 	( 0x00000000 )
+#define RUNNER_PRED_PICO_1_MEM_ADDRESS	( RUNNER_PRED_PICO_1_OFFSET + RUNNER_PRED_PICO_1_MEM_OFFSET )
+
+#define RUNNER_REGS_0_CFG_OFFSET 	( 0x00000000 )
+#define RUNNER_REGS_0_CFG_ADDRESS	( RUNNER_REGS_0_OFFSET + RUNNER_REGS_0_CFG_OFFSET )
+
+#define RUNNER_REGS_1_CFG_OFFSET 	( 0x00000000 )
+#define RUNNER_REGS_1_CFG_ADDRESS	( RUNNER_REGS_1_OFFSET + RUNNER_REGS_1_CFG_OFFSET )
+
+/*   'd' is module index   */
+/*   'i' is block index    */
+/*   'j' is function index */
+/*   'e' is function entry */
+/*   'k' is register index */
+
+/*****************************************************************************************/
+/* Data_memory_entry                                                                     */
+/* Data memory entry                                                                     */
+/*****************************************************************************************/
+
+#define RUNNER_COMMON_MEM_HIGH_DATA_MEM_DATA_VALUE             ( 0x0 )
+#define RUNNER_COMMON_MEM_HIGH_DATA_MEM_DATA_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_COMMON_MEM_HIGH_OFFSET ( 0x00000000 )
+
+#define RUNNER_COMMON_0_MEM_HIGH_ADDRESS      	( RUNNER_COMMON_0_MEM_ADDRESS + RUNNER_COMMON_MEM_HIGH_OFFSET )
+#define RUNNER_COMMON_0_MEM_HIGH_READ( e, r ) 	READ_32( ( RUNNER_COMMON_0_MEM_HIGH_ADDRESS  + e * 8 ), (r) )
+#define RUNNER_COMMON_0_MEM_HIGH_WRITE( e, v )	WRITE_32( ( RUNNER_COMMON_0_MEM_HIGH_ADDRESS + e * 8 ), (v) )
+
+#define RUNNER_COMMON_1_MEM_HIGH_ADDRESS      	( RUNNER_COMMON_1_MEM_ADDRESS + RUNNER_COMMON_MEM_HIGH_OFFSET )
+#define RUNNER_COMMON_1_MEM_HIGH_READ( e, r ) 	READ_32( ( RUNNER_COMMON_1_MEM_HIGH_ADDRESS  + e * 8 ), (r) )
+#define RUNNER_COMMON_1_MEM_HIGH_WRITE( e, v )	WRITE_32( ( RUNNER_COMMON_1_MEM_HIGH_ADDRESS + e * 8 ), (v) )
+
+
+extern uint32_t RUNNER_COMMON_MEM_HIGH_ARRAY [ ] ;
+
+#define RUNNER_COMMON_MEM_HIGH_WRITE( i, e, v )	WRITE_32( RUNNER_COMMON_MEM_HIGH_ARRAY [ i ] + e * 8, (v) )
+#define RUNNER_COMMON_MEM_HIGH_READ( i, e, r ) 	READ_32( RUNNER_COMMON_MEM_HIGH_ARRAY [ i ] + e * 8, (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* data_memory */
+	uint32_t data_mem	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_COMMON_MEM_HIGH ;
+#else
+typedef struct
+{	uint32_t data_mem	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data_memory */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_COMMON_MEM_HIGH ;
+#endif
+
+/*****************************************************************************************/
+/* Data_memory_entry                                                                     */
+/* Data memory entry                                                                     */
+/*****************************************************************************************/
+
+#define RUNNER_COMMON_MEM_LOW_DATA_MEM_DATA_VALUE             ( 0x0 )
+#define RUNNER_COMMON_MEM_LOW_DATA_MEM_DATA_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_COMMON_MEM_LOW_OFFSET ( 0x00000004 )
+
+#define RUNNER_COMMON_0_MEM_LOW_ADDRESS      	( RUNNER_COMMON_0_MEM_ADDRESS + RUNNER_COMMON_MEM_LOW_OFFSET )
+#define RUNNER_COMMON_0_MEM_LOW_READ( e, r ) 	READ_32( ( RUNNER_COMMON_0_MEM_LOW_ADDRESS  + e * 8 ), (r) )
+#define RUNNER_COMMON_0_MEM_LOW_WRITE( e, v )	WRITE_32( ( RUNNER_COMMON_0_MEM_LOW_ADDRESS + e * 8 ), (v) )
+
+#define RUNNER_COMMON_1_MEM_LOW_ADDRESS      	( RUNNER_COMMON_1_MEM_ADDRESS + RUNNER_COMMON_MEM_LOW_OFFSET )
+#define RUNNER_COMMON_1_MEM_LOW_READ( e, r ) 	READ_32( ( RUNNER_COMMON_1_MEM_LOW_ADDRESS  + e * 8 ), (r) )
+#define RUNNER_COMMON_1_MEM_LOW_WRITE( e, v )	WRITE_32( ( RUNNER_COMMON_1_MEM_LOW_ADDRESS + e * 8 ), (v) )
+
+
+extern uint32_t RUNNER_COMMON_MEM_LOW_ARRAY [ ] ;
+
+#define RUNNER_COMMON_MEM_LOW_WRITE( i, e, v )	WRITE_32( RUNNER_COMMON_MEM_LOW_ARRAY [ i ] + e * 8, (v) )
+#define RUNNER_COMMON_MEM_LOW_READ( i, e, r ) 	READ_32( RUNNER_COMMON_MEM_LOW_ARRAY [ i ] + e * 8, (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* data_memory */
+	uint32_t data_mem	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_COMMON_MEM_LOW ;
+#else
+typedef struct
+{	uint32_t data_mem	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data_memory */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_COMMON_MEM_LOW ;
+#endif
+
+/*****************************************************************************************/
+/* Data_memory_entry                                                                     */
+/* Data memory entry                                                                     */
+/*****************************************************************************************/
+
+#define RUNNER_PRIVATE_MEM_HIGH_DATA_MEM_DATA_VALUE             ( 0x0 )
+#define RUNNER_PRIVATE_MEM_HIGH_DATA_MEM_DATA_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_PRIVATE_MEM_HIGH_OFFSET ( 0x00000000 )
+
+#define RUNNER_PRIVATE_0_MEM_HIGH_ADDRESS      	( RUNNER_PRIVATE_0_MEM_ADDRESS + RUNNER_PRIVATE_MEM_HIGH_OFFSET )
+#define RUNNER_PRIVATE_0_MEM_HIGH_READ( e, r ) 	READ_32( ( RUNNER_PRIVATE_0_MEM_HIGH_ADDRESS  + e * 8 ), (r) )
+#define RUNNER_PRIVATE_0_MEM_HIGH_WRITE( e, v )	WRITE_32( ( RUNNER_PRIVATE_0_MEM_HIGH_ADDRESS + e * 8 ), (v) )
+
+#define RUNNER_PRIVATE_1_MEM_HIGH_ADDRESS      	( RUNNER_PRIVATE_1_MEM_ADDRESS + RUNNER_PRIVATE_MEM_HIGH_OFFSET )
+#define RUNNER_PRIVATE_1_MEM_HIGH_READ( e, r ) 	READ_32( ( RUNNER_PRIVATE_1_MEM_HIGH_ADDRESS  + e * 8 ), (r) )
+#define RUNNER_PRIVATE_1_MEM_HIGH_WRITE( e, v )	WRITE_32( ( RUNNER_PRIVATE_1_MEM_HIGH_ADDRESS + e * 8 ), (v) )
+
+
+extern uint32_t RUNNER_PRIVATE_MEM_HIGH_ARRAY [ ] ;
+
+#define RUNNER_PRIVATE_MEM_HIGH_WRITE( i, e, v )	WRITE_32( RUNNER_PRIVATE_MEM_HIGH_ARRAY [ i ] + e * 8, (v) )
+#define RUNNER_PRIVATE_MEM_HIGH_READ( i, e, r ) 	READ_32( RUNNER_PRIVATE_MEM_HIGH_ARRAY [ i ] + e * 8, (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* data_memory */
+	uint32_t data_mem	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRIVATE_MEM_HIGH ;
+#else
+typedef struct
+{	uint32_t data_mem	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data_memory */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRIVATE_MEM_HIGH ;
+#endif
+
+/*****************************************************************************************/
+/* Data_memory_entry                                                                     */
+/* Data memory entry                                                                     */
+/*****************************************************************************************/
+
+#define RUNNER_PRIVATE_MEM_LOW_DATA_MEM_DATA_VALUE             ( 0x0 )
+#define RUNNER_PRIVATE_MEM_LOW_DATA_MEM_DATA_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_PRIVATE_MEM_LOW_OFFSET ( 0x00000004 )
+
+#define RUNNER_PRIVATE_0_MEM_LOW_ADDRESS      	( RUNNER_PRIVATE_0_MEM_ADDRESS + RUNNER_PRIVATE_MEM_LOW_OFFSET )
+#define RUNNER_PRIVATE_0_MEM_LOW_READ( e, r ) 	READ_32( ( RUNNER_PRIVATE_0_MEM_LOW_ADDRESS  + e * 8 ), (r) )
+#define RUNNER_PRIVATE_0_MEM_LOW_WRITE( e, v )	WRITE_32( ( RUNNER_PRIVATE_0_MEM_LOW_ADDRESS + e * 8 ), (v) )
+
+#define RUNNER_PRIVATE_1_MEM_LOW_ADDRESS      	( RUNNER_PRIVATE_1_MEM_ADDRESS + RUNNER_PRIVATE_MEM_LOW_OFFSET )
+#define RUNNER_PRIVATE_1_MEM_LOW_READ( e, r ) 	READ_32( ( RUNNER_PRIVATE_1_MEM_LOW_ADDRESS  + e * 8 ), (r) )
+#define RUNNER_PRIVATE_1_MEM_LOW_WRITE( e, v )	WRITE_32( ( RUNNER_PRIVATE_1_MEM_LOW_ADDRESS + e * 8 ), (v) )
+
+
+extern uint32_t RUNNER_PRIVATE_MEM_LOW_ARRAY [ ] ;
+
+#define RUNNER_PRIVATE_MEM_LOW_WRITE( i, e, v )	WRITE_32( RUNNER_PRIVATE_MEM_LOW_ARRAY [ i ] + e * 8, (v) )
+#define RUNNER_PRIVATE_MEM_LOW_READ( i, e, r ) 	READ_32( RUNNER_PRIVATE_MEM_LOW_ARRAY [ i ] + e * 8, (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* data_memory */
+	uint32_t data_mem	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRIVATE_MEM_LOW ;
+#else
+typedef struct
+{	uint32_t data_mem	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data_memory */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRIVATE_MEM_LOW ;
+#endif
+
+/*****************************************************************************************/
+/* Instruction_memory_entry                                                              */
+/* Instruction memory entry                                                              */
+/*****************************************************************************************/
+
+#define RUNNER_INST_MAIN_MEM_ENTRY_INSTRUCTION_INSTRUCTION_VALUE             ( 0x0 )
+#define RUNNER_INST_MAIN_MEM_ENTRY_INSTRUCTION_INSTRUCTION_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_INST_MAIN_MEM_ENTRY_OFFSET ( 0x00000000 )
+
+#define RUNNER_INST_MAIN_0_MEM_ENTRY_ADDRESS      	( RUNNER_INST_MAIN_0_MEM_ADDRESS + RUNNER_INST_MAIN_MEM_ENTRY_OFFSET )
+#define RUNNER_INST_MAIN_0_MEM_ENTRY_READ( e, r ) 	READ_32( ( RUNNER_INST_MAIN_0_MEM_ENTRY_ADDRESS  + e * 4 ), (r) )
+#define RUNNER_INST_MAIN_0_MEM_ENTRY_WRITE( e, v )	WRITE_32( ( RUNNER_INST_MAIN_0_MEM_ENTRY_ADDRESS + e * 4 ), (v) )
+
+#define RUNNER_INST_MAIN_1_MEM_ENTRY_ADDRESS      	( RUNNER_INST_MAIN_1_MEM_ADDRESS + RUNNER_INST_MAIN_MEM_ENTRY_OFFSET )
+#define RUNNER_INST_MAIN_1_MEM_ENTRY_READ( e, r ) 	READ_32( ( RUNNER_INST_MAIN_1_MEM_ENTRY_ADDRESS  + e * 4 ), (r) )
+#define RUNNER_INST_MAIN_1_MEM_ENTRY_WRITE( e, v )	WRITE_32( ( RUNNER_INST_MAIN_1_MEM_ENTRY_ADDRESS + e * 4 ), (v) )
+
+
+extern uint32_t RUNNER_INST_MAIN_MEM_ENTRY_ARRAY [ ] ;
+
+#define RUNNER_INST_MAIN_MEM_ENTRY_WRITE( i, e, v )	WRITE_32( RUNNER_INST_MAIN_MEM_ENTRY_ARRAY [ i ] + e * 4, (v) )
+#define RUNNER_INST_MAIN_MEM_ENTRY_READ( i, e, r ) 	READ_32( RUNNER_INST_MAIN_MEM_ENTRY_ARRAY [ i ] + e * 4, (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Instructions_memory */
+	uint32_t instruction	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_INST_MAIN_MEM_ENTRY ;
+#else
+typedef struct
+{	uint32_t instruction	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Instructions_memory */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_INST_MAIN_MEM_ENTRY ;
+#endif
+
+/*****************************************************************************************/
+/* Context_mem_entry                                                                     */
+/* Context mem entry                                                                     */
+/*****************************************************************************************/
+
+#define RUNNER_CNTXT_MAIN_MEM_ENTRY_CONTEXT_ENTRY_CONTEXT_MEM_ENTRY_VALUE             ( 0x0 )
+#define RUNNER_CNTXT_MAIN_MEM_ENTRY_CONTEXT_ENTRY_CONTEXT_MEM_ENTRY_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_CNTXT_MAIN_MEM_ENTRY_OFFSET ( 0x00000000 )
+
+#define RUNNER_CNTXT_MAIN_0_MEM_ENTRY_ADDRESS      	( RUNNER_CNTXT_MAIN_0_MEM_ADDRESS + RUNNER_CNTXT_MAIN_MEM_ENTRY_OFFSET )
+#define RUNNER_CNTXT_MAIN_0_MEM_ENTRY_READ( e, r ) 	READ_32( ( RUNNER_CNTXT_MAIN_0_MEM_ENTRY_ADDRESS  + e * 4 ), (r) )
+#define RUNNER_CNTXT_MAIN_0_MEM_ENTRY_WRITE( e, v )	WRITE_32( ( RUNNER_CNTXT_MAIN_0_MEM_ENTRY_ADDRESS + e * 4 ), (v) )
+
+#define RUNNER_CNTXT_MAIN_1_MEM_ENTRY_ADDRESS      	( RUNNER_CNTXT_MAIN_1_MEM_ADDRESS + RUNNER_CNTXT_MAIN_MEM_ENTRY_OFFSET )
+#define RUNNER_CNTXT_MAIN_1_MEM_ENTRY_READ( e, r ) 	READ_32( ( RUNNER_CNTXT_MAIN_1_MEM_ENTRY_ADDRESS  + e * 4 ), (r) )
+#define RUNNER_CNTXT_MAIN_1_MEM_ENTRY_WRITE( e, v )	WRITE_32( ( RUNNER_CNTXT_MAIN_1_MEM_ENTRY_ADDRESS + e * 4 ), (v) )
+
+
+extern uint32_t RUNNER_CNTXT_MAIN_MEM_ENTRY_ARRAY [ ] ;
+
+#define RUNNER_CNTXT_MAIN_MEM_ENTRY_WRITE( i, e, v )	WRITE_32( RUNNER_CNTXT_MAIN_MEM_ENTRY_ARRAY [ i ] + e * 4, (v) )
+#define RUNNER_CNTXT_MAIN_MEM_ENTRY_READ( i, e, r ) 	READ_32( RUNNER_CNTXT_MAIN_MEM_ENTRY_ARRAY [ i ] + e * 4, (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Context_mem_entry */
+	uint32_t context_entry	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_CNTXT_MAIN_MEM_ENTRY ;
+#else
+typedef struct
+{	uint32_t context_entry	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_mem_entry */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_CNTXT_MAIN_MEM_ENTRY ;
+#endif
+
+/*****************************************************************************************/
+/* prediction_memory_core                                                                */
+/* Prediction memory MAIN core                                                           */
+/*****************************************************************************************/
+
+
+
+#define RUNNER_PRED_MAIN_MEM_ENTRY_OFFSET ( 0x00000000 )
+
+#define RUNNER_PRED_MAIN_0_MEM_ENTRY_ADDRESS        	( RUNNER_PRED_MAIN_0_MEM_ADDRESS + RUNNER_PRED_MAIN_MEM_ENTRY_OFFSET )
+#define RUNNER_PRED_MAIN_0_MEM_ENTRY_READ_I( r, i ) 	READ_I_16( ( RUNNER_PRED_MAIN_0_MEM_ENTRY_ADDRESS ), (i), (r) )
+#define RUNNER_PRED_MAIN_0_MEM_ENTRY_WRITE_I( v, i )	WRITE_I_16( ( RUNNER_PRED_MAIN_0_MEM_ENTRY_ADDRESS ), (i), (v) )
+
+#define RUNNER_PRED_MAIN_1_MEM_ENTRY_ADDRESS        	( RUNNER_PRED_MAIN_1_MEM_ADDRESS + RUNNER_PRED_MAIN_MEM_ENTRY_OFFSET )
+#define RUNNER_PRED_MAIN_1_MEM_ENTRY_READ_I( r, i ) 	READ_I_16( ( RUNNER_PRED_MAIN_1_MEM_ENTRY_ADDRESS ), (i), (r) )
+#define RUNNER_PRED_MAIN_1_MEM_ENTRY_WRITE_I( v, i )	WRITE_I_16( ( RUNNER_PRED_MAIN_1_MEM_ENTRY_ADDRESS ), (i), (v) )
+
+
+extern uint32_t RUNNER_PRED_MAIN_MEM_ENTRY_ARRAY [ ] ;
+
+#define RUNNER_PRED_MAIN_MEM_ENTRY_WRITE( i, k, v )	WRITE_I_16( RUNNER_PRED_MAIN_MEM_ENTRY_ARRAY [ i ], (k), (v) )
+#define RUNNER_PRED_MAIN_MEM_ENTRY_READ( i, k, r ) 	READ_I_16( RUNNER_PRED_MAIN_MEM_ENTRY_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MEM_PRED_MAIN */
+	uint16_t pred_mem	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRED_MAIN_MEM_ENTRY ;
+#else
+typedef struct
+{	uint16_t pred_mem	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MEM_PRED_MAIN */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRED_MAIN_MEM_ENTRY ;
+#endif
+
+/*****************************************************************************************/
+/* Instruction_memory_entry                                                              */
+/* Instruction memory entry                                                              */
+/*****************************************************************************************/
+
+#define RUNNER_INST_PICO_MEM_ENTRY_INSTRUCTION_INSTRUCTION_VALUE             ( 0x0 )
+#define RUNNER_INST_PICO_MEM_ENTRY_INSTRUCTION_INSTRUCTION_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_INST_PICO_MEM_ENTRY_OFFSET ( 0x00000000 )
+
+#define RUNNER_INST_PICO_0_MEM_ENTRY_ADDRESS      	( RUNNER_INST_PICO_0_MEM_ADDRESS + RUNNER_INST_PICO_MEM_ENTRY_OFFSET )
+#define RUNNER_INST_PICO_0_MEM_ENTRY_READ( e, r ) 	READ_32( ( RUNNER_INST_PICO_0_MEM_ENTRY_ADDRESS  + e * 4 ), (r) )
+#define RUNNER_INST_PICO_0_MEM_ENTRY_WRITE( e, v )	WRITE_32( ( RUNNER_INST_PICO_0_MEM_ENTRY_ADDRESS + e * 4 ), (v) )
+
+#define RUNNER_INST_PICO_1_MEM_ENTRY_ADDRESS      	( RUNNER_INST_PICO_1_MEM_ADDRESS + RUNNER_INST_PICO_MEM_ENTRY_OFFSET )
+#define RUNNER_INST_PICO_1_MEM_ENTRY_READ( e, r ) 	READ_32( ( RUNNER_INST_PICO_1_MEM_ENTRY_ADDRESS  + e * 4 ), (r) )
+#define RUNNER_INST_PICO_1_MEM_ENTRY_WRITE( e, v )	WRITE_32( ( RUNNER_INST_PICO_1_MEM_ENTRY_ADDRESS + e * 4 ), (v) )
+
+
+extern uint32_t RUNNER_INST_PICO_MEM_ENTRY_ARRAY [ ] ;
+
+#define RUNNER_INST_PICO_MEM_ENTRY_WRITE( i, e, v )	WRITE_32( RUNNER_INST_PICO_MEM_ENTRY_ARRAY [ i ] + e * 4, (v) )
+#define RUNNER_INST_PICO_MEM_ENTRY_READ( i, e, r ) 	READ_32( RUNNER_INST_PICO_MEM_ENTRY_ARRAY [ i ] + e * 4, (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Instructions_memory */
+	uint32_t instruction	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_INST_PICO_MEM_ENTRY ;
+#else
+typedef struct
+{	uint32_t instruction	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Instructions_memory */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_INST_PICO_MEM_ENTRY ;
+#endif
+
+/*****************************************************************************************/
+/* Context_mem_entry                                                                     */
+/* Context mem entry                                                                     */
+/*****************************************************************************************/
+
+#define RUNNER_CNTXT_PICO_MEM_ENTRY_CONTEXT_ENTRY_CONTEXT_MEM_ENTRY_VALUE             ( 0x0 )
+#define RUNNER_CNTXT_PICO_MEM_ENTRY_CONTEXT_ENTRY_CONTEXT_MEM_ENTRY_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_CNTXT_PICO_MEM_ENTRY_OFFSET ( 0x00000000 )
+
+#define RUNNER_CNTXT_PICO_0_MEM_ENTRY_ADDRESS      	( RUNNER_CNTXT_PICO_0_MEM_ADDRESS + RUNNER_CNTXT_PICO_MEM_ENTRY_OFFSET )
+#define RUNNER_CNTXT_PICO_0_MEM_ENTRY_READ( e, r ) 	READ_32( ( RUNNER_CNTXT_PICO_0_MEM_ENTRY_ADDRESS  + e * 4 ), (r) )
+#define RUNNER_CNTXT_PICO_0_MEM_ENTRY_WRITE( e, v )	WRITE_32( ( RUNNER_CNTXT_PICO_0_MEM_ENTRY_ADDRESS + e * 4 ), (v) )
+
+#define RUNNER_CNTXT_PICO_1_MEM_ENTRY_ADDRESS      	( RUNNER_CNTXT_PICO_1_MEM_ADDRESS + RUNNER_CNTXT_PICO_MEM_ENTRY_OFFSET )
+#define RUNNER_CNTXT_PICO_1_MEM_ENTRY_READ( e, r ) 	READ_32( ( RUNNER_CNTXT_PICO_1_MEM_ENTRY_ADDRESS  + e * 4 ), (r) )
+#define RUNNER_CNTXT_PICO_1_MEM_ENTRY_WRITE( e, v )	WRITE_32( ( RUNNER_CNTXT_PICO_1_MEM_ENTRY_ADDRESS + e * 4 ), (v) )
+
+
+extern uint32_t RUNNER_CNTXT_PICO_MEM_ENTRY_ARRAY [ ] ;
+
+#define RUNNER_CNTXT_PICO_MEM_ENTRY_WRITE( i, e, v )	WRITE_32( RUNNER_CNTXT_PICO_MEM_ENTRY_ARRAY [ i ] + e * 4, (v) )
+#define RUNNER_CNTXT_PICO_MEM_ENTRY_READ( i, e, r ) 	READ_32( RUNNER_CNTXT_PICO_MEM_ENTRY_ARRAY [ i ] + e * 4, (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Context_mem_entry */
+	uint32_t context_entry	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_CNTXT_PICO_MEM_ENTRY ;
+#else
+typedef struct
+{	uint32_t context_entry	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Context_mem_entry */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_CNTXT_PICO_MEM_ENTRY ;
+#endif
+
+/*****************************************************************************************/
+/* Prediction_memory_pico                                                                */
+/* Prediction memory PICO core                                                           */
+/*****************************************************************************************/
+
+
+
+#define RUNNER_PRED_PICO_MEM_ENTRY_OFFSET ( 0x00000000 )
+
+#define RUNNER_PRED_PICO_0_MEM_ENTRY_ADDRESS        	( RUNNER_PRED_PICO_0_MEM_ADDRESS + RUNNER_PRED_PICO_MEM_ENTRY_OFFSET )
+#define RUNNER_PRED_PICO_0_MEM_ENTRY_READ_I( r, i ) 	READ_I_16( ( RUNNER_PRED_PICO_0_MEM_ENTRY_ADDRESS ), (i), (r) )
+#define RUNNER_PRED_PICO_0_MEM_ENTRY_WRITE_I( v, i )	WRITE_I_16( ( RUNNER_PRED_PICO_0_MEM_ENTRY_ADDRESS ), (i), (v) )
+
+#define RUNNER_PRED_PICO_1_MEM_ENTRY_ADDRESS        	( RUNNER_PRED_PICO_1_MEM_ADDRESS + RUNNER_PRED_PICO_MEM_ENTRY_OFFSET )
+#define RUNNER_PRED_PICO_1_MEM_ENTRY_READ_I( r, i ) 	READ_I_16( ( RUNNER_PRED_PICO_1_MEM_ENTRY_ADDRESS ), (i), (r) )
+#define RUNNER_PRED_PICO_1_MEM_ENTRY_WRITE_I( v, i )	WRITE_I_16( ( RUNNER_PRED_PICO_1_MEM_ENTRY_ADDRESS ), (i), (v) )
+
+
+extern uint32_t RUNNER_PRED_PICO_MEM_ENTRY_ARRAY [ ] ;
+
+#define RUNNER_PRED_PICO_MEM_ENTRY_WRITE( i, k, v )	WRITE_I_16( RUNNER_PRED_PICO_MEM_ENTRY_ARRAY [ i ], (k), (v) )
+#define RUNNER_PRED_PICO_MEM_ENTRY_READ( i, k, r ) 	READ_I_16( RUNNER_PRED_PICO_MEM_ENTRY_ARRAY [ i ], (k), (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MEM_PRED_PICO */
+	uint16_t mem_pred_pico	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRED_PICO_MEM_ENTRY ;
+#else
+typedef struct
+{	uint16_t mem_pred_pico	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MEM_PRED_PICO */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRED_PICO_MEM_ENTRY ;
+#endif
+
+/*****************************************************************************************/
+/* Global_control                                                                        */
+/* Global control                                                                        */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_RESERVED2_RESREVED_VALUE                          ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_RESERVED2_RESREVED_VALUE_RESET_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_MAIN_CNTXT_REB_EN_DISABLE_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_MAIN_CNTXT_REB_EN_DISABLE_VALUE_RESET_VALUE       ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_MAIN_CNTXT_REB_EN_ENABLE_VALUE                    ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_RESERVED1_RESREVED_VALUE                          ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_RESERVED1_RESREVED_VALUE_RESET_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PRVT_B_LS_0_REGULER_MODE_VALUE                    ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PRVT_B_LS_0_LS_VALUE                              ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PRVT_B_LS_0_LS_VALUE_RESET_VALUE                  ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PRVT_A_LS_0_REGULER_MODE_VALUE                    ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PRVT_A_LS_0_LS_VALUE                              ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PRVT_A_LS_0_LS_VALUE_RESET_VALUE                  ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_CMN_LS_0_REGULER_MODE_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_CMN_LS_0_LS_VALUE                                 ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_CMN_LS_0_LS_VALUE_RESET_VALUE                     ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_DMA_LS_0_REGULER_MODE_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_DMA_LS_0_LS_VALUE                                 ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_DMA_LS_0_LS_VALUE_RESET_VALUE                     ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PRED_LS_0_REGULER_MODE_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PRED_LS_0_LS_VALUE                                ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PRED_LS_0_LS_VALUE_RESET_VALUE                    ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_CNTXT_LS_0_REGULER_MODE_VALUE                     ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_CNTXT_LS_0_LS_VALUE                               ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_CNTXT_LS_0_LS_VALUE_RESET_VALUE                   ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PGM_LS_0_REGULER_MODE_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PGM_LS_0_LS_VALUE                                 ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PGM_LS_0_LS_VALUE_RESET_VALUE                     ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_MICRO_SEC_VAL_DEFAULT_FREQUENCY_VALUE             ( 0x15E )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_MICRO_SEC_VAL_DEFAULT_FREQUENCY_VALUE_RESET_VALUE ( 0x15E )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_RESERVED0_RESREVED_VALUE                          ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_RESERVED0_RESREVED_VALUE_RESET_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PICO_EN_RUNNER_DISABLED_VALUE                     ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PICO_EN_RUNNER_DISABLED_VALUE_RESET_VALUE         ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_PICO_EN_RUNNER_ENABLED_VALUE                      ( 0x1 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_MAIN_EN_RUNNER_DISABLED_VALUE                     ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_MAIN_EN_RUNNER_DISABLED_VALUE_RESET_VALUE         ( 0x0 )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_MAIN_EN_RUNNER_ENABLED_VALUE                      ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_OFFSET ( 0x00000000 )
+
+#define RUNNER_REGS_0_CFG_GLOBAL_CTRL_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_GLOBAL_CTRL_OFFSET )
+#define RUNNER_REGS_0_CFG_GLOBAL_CTRL_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_GLOBAL_CTRL_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_GLOBAL_CTRL_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_GLOBAL_CTRL_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_GLOBAL_CTRL_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_GLOBAL_CTRL_OFFSET )
+#define RUNNER_REGS_1_CFG_GLOBAL_CTRL_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_GLOBAL_CTRL_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_GLOBAL_CTRL_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_GLOBAL_CTRL_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_GLOBAL_CTRL_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_GLOBAL_CTRL_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_GLOBAL_CTRL_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_GLOBAL_CTRL_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t reserved2        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* main_cntx_reb_en */
+	uint32_t main_cntxt_reb_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t reserved1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PRVT_B_mem_tie_to_0 */
+	uint32_t prvt_b_ls_0      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PRVT_A_mem_tie_to_0 */
+	uint32_t prvt_a_ls_0      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CMN_mem_tie_to_0 */
+	uint32_t cmn_ls_0         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_mem_tie_to_0 */
+	uint32_t dma_ls_0         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PRED_mem_tie_to_0 */
+	uint32_t pred_ls_0        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CNTXT_mem_tie_to_0 */
+	uint32_t cntxt_ls_0       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PGM_mem_tie_to_0 */
+	uint32_t pgm_ls_0         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Micro_sec_val */
+	uint32_t micro_sec_val    	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t reserved0        	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PICO_enable */
+	uint32_t pico_en          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MAIN_enable */
+	uint32_t main_en          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_GLOBAL_CTRL ;
+#else
+typedef struct
+{	uint32_t main_en          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MAIN_enable */
+	uint32_t pico_en          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PICO_enable */
+	uint32_t reserved0        	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t micro_sec_val    	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Micro_sec_val */
+	uint32_t pgm_ls_0         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PGM_mem_tie_to_0 */
+	uint32_t cntxt_ls_0       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CNTXT_mem_tie_to_0 */
+	uint32_t pred_ls_0        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PRED_mem_tie_to_0 */
+	uint32_t dma_ls_0         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_mem_tie_to_0 */
+	uint32_t cmn_ls_0         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CMN_mem_tie_to_0 */
+	uint32_t prvt_a_ls_0      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PRVT_A_mem_tie_to_0 */
+	uint32_t prvt_b_ls_0      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PRVT_B_mem_tie_to_0 */
+	uint32_t reserved1        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+	uint32_t main_cntxt_reb_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* main_cntx_reb_en */
+	uint32_t reserved2        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_GLOBAL_CTRL ;
+#endif
+
+/*****************************************************************************************/
+/* CPU_Wakeup                                                                            */
+/* Writing to this register generates a request towards the runner scheduler.            */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_CPU_WAKEUP_RESERVED0_RESERVED_VALUE                ( 0x0 )
+#define RUNNER_REGS_CFG_CPU_WAKEUP_RESERVED0_RESERVED_VALUE_RESET_VALUE    ( 0x0 )
+#define RUNNER_REGS_CFG_CPU_WAKEUP_URGENT_REQ_NOT_URGENT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_CPU_WAKEUP_URGENT_REQ_NOT_URGENT_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_CPU_WAKEUP_URGENT_REQ_URGENT_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_CPU_WAKEUP_REQ_TRGT_MAIN_VALUE                     ( 0x0 )
+#define RUNNER_REGS_CFG_CPU_WAKEUP_REQ_TRGT_MAIN_VALUE_RESET_VALUE         ( 0x0 )
+#define RUNNER_REGS_CFG_CPU_WAKEUP_REQ_TRGT_PICO_VALUE                     ( 0x1 )
+#define RUNNER_REGS_CFG_CPU_WAKEUP_THREAD_NUM_DEFAULT_VALUE                ( 0x0 )
+#define RUNNER_REGS_CFG_CPU_WAKEUP_THREAD_NUM_DEFAULT_VALUE_RESET_VALUE    ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_CPU_WAKEUP_OFFSET ( 0x00000004 )
+
+#define RUNNER_REGS_0_CFG_CPU_WAKEUP_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_CPU_WAKEUP_OFFSET )
+#define RUNNER_REGS_0_CFG_CPU_WAKEUP_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_CPU_WAKEUP_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_CPU_WAKEUP_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_CPU_WAKEUP_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_CPU_WAKEUP_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_CPU_WAKEUP_OFFSET )
+#define RUNNER_REGS_1_CFG_CPU_WAKEUP_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_CPU_WAKEUP_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_CPU_WAKEUP_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_CPU_WAKEUP_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_CPU_WAKEUP_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_CPU_WAKEUP_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_CPU_WAKEUP_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_CPU_WAKEUP_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_CPU_WAKEUP_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved0 	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Urgent_Request */
+	uint32_t urgent_req	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Req_target */
+	uint32_t req_trgt  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Thread_Number */
+	uint32_t thread_num	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_CPU_WAKEUP ;
+#else
+typedef struct
+{	uint32_t thread_num	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Thread_Number */
+	uint32_t req_trgt  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Req_target */
+	uint32_t urgent_req	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Urgent_Request */
+	uint32_t reserved0 	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_CPU_WAKEUP ;
+#endif
+
+/*****************************************************************************************/
+/* Interrupt_Control                                                                     */
+/* Interrupt control                                                                     */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_INT_CTRL_RESERVED0_RESERVED_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_RESERVED0_RESERVED_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT9_STS_INTERRUPT_IS_NOT_SET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT9_STS_INTERRUPT_IS_NOT_SET_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT9_STS_INTERRUPT_IS_SET_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT8_STS_INTERRUPT_IS_NOT_SET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT8_STS_INTERRUPT_IS_NOT_SET_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT8_STS_INTERRUPT_IS_SET_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT7_STS_INTERRUPT_IS_NOT_SET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT7_STS_INTERRUPT_IS_NOT_SET_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT7_STS_INTERRUPT_IS_SET_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT6_STS_INTERRUPT_IS_NOT_SET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT6_STS_INTERRUPT_IS_NOT_SET_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT6_STS_INTERRUPT_IS_SET_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT5_STS_INTERRUPT_IS_NOT_SET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT5_STS_INTERRUPT_IS_NOT_SET_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT5_STS_INTERRUPT_IS_SET_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT4_STS_INTERRUPT_IS_NOT_SET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT4_STS_INTERRUPT_IS_NOT_SET_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT4_STS_INTERRUPT_IS_SET_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT3_STS_INTERRUPT_IS_NOT_SET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT3_STS_INTERRUPT_IS_NOT_SET_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT3_STS_INTERRUPT_IS_SET_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT2_STS_INTERRUPT_IS_NOT_SET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT2_STS_INTERRUPT_IS_NOT_SET_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT2_STS_INTERRUPT_IS_SET_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT1_STS_INTERRUPT_CLEARED_VALUE                ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT1_STS_INTERRUPT_CLEARED_VALUE_RESET_VALUE    ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT0_STS_INTERRUPT_CLEARED_VALUE                ( 0x0 )
+#define RUNNER_REGS_CFG_INT_CTRL_INT0_STS_INTERRUPT_CLEARED_VALUE_RESET_VALUE    ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_INT_CTRL_OFFSET ( 0x00000008 )
+
+#define RUNNER_REGS_0_CFG_INT_CTRL_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_INT_CTRL_OFFSET )
+#define RUNNER_REGS_0_CFG_INT_CTRL_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_INT_CTRL_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_INT_CTRL_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_INT_CTRL_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_INT_CTRL_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_INT_CTRL_OFFSET )
+#define RUNNER_REGS_1_CFG_INT_CTRL_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_INT_CTRL_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_INT_CTRL_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_INT_CTRL_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_INT_CTRL_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_INT_CTRL_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_INT_CTRL_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_INT_CTRL_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_INT_CTRL_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt9_status */
+	uint32_t int9_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt8_status */
+	uint32_t int8_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt7_status */
+	uint32_t int7_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt6_status */
+	uint32_t int6_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt5_status */
+	uint32_t int5_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt4_status */
+	uint32_t int4_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt3_status */
+	uint32_t int3_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt2_status */
+	uint32_t int2_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_1_status */
+	uint32_t int1_sts 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_0_status */
+	uint32_t int0_sts 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_INT_CTRL ;
+#else
+typedef struct
+{	uint32_t int0_sts 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_0_status */
+	uint32_t int1_sts 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_1_status */
+	uint32_t int2_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt2_status */
+	uint32_t int3_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt3_status */
+	uint32_t int4_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt4_status */
+	uint32_t int5_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt5_status */
+	uint32_t int6_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt6_status */
+	uint32_t int7_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt7_status */
+	uint32_t int8_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt8_status */
+	uint32_t int9_sts 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt9_status */
+	uint32_t reserved0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_INT_CTRL ;
+#endif
+
+/*****************************************************************************************/
+/* Interrupt_Mask                                                                        */
+/* Interrupt mask                                                                        */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_INT_MASK_RESERVED0_RESERVED_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_RESERVED0_RESERVED_VALUE_RESET_VALUE       ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT9_MASK_INTERRUPT_MASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT9_MASK_INTERRUPT_MASK_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT8_MASK_INTERRUPT_MASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT8_MASK_INTERRUPT_MASK_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT7_MASK_INTERRUPT_MASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT7_MASK_INTERRUPT_MASK_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT6_MASK_INTERRUPT_MASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT6_MASK_INTERRUPT_MASK_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT5_MASK_INTERRUPT_MASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT5_MASK_INTERRUPT_MASK_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT4_MASK_INTERRUPT_MASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT4_MASK_INTERRUPT_MASK_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT3_MASK_INTERRUPT_MASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT3_MASK_INTERRUPT_MASK_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT2_MASK_INTERRUPT_MASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT2_MASK_INTERRUPT_MASK_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT1_MASK_INTERRUPT_MASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT1_MASK_INTERRUPT_MASK_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT0_MASK_INTERRUPT_MASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_INT_MASK_INT0_MASK_INTERRUPT_MASK_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_INT_MASK_OFFSET ( 0x0000000C )
+
+#define RUNNER_REGS_0_CFG_INT_MASK_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_INT_MASK_OFFSET )
+#define RUNNER_REGS_0_CFG_INT_MASK_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_INT_MASK_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_INT_MASK_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_INT_MASK_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_INT_MASK_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_INT_MASK_OFFSET )
+#define RUNNER_REGS_1_CFG_INT_MASK_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_INT_MASK_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_INT_MASK_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_INT_MASK_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_INT_MASK_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_INT_MASK_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_INT_MASK_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_INT_MASK_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_INT_MASK_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_9_mask */
+	uint32_t int9_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_8_mask */
+	uint32_t int8_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Inerrupt_7_mask */
+	uint32_t int7_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_6_mask */
+	uint32_t int6_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_5_mask */
+	uint32_t int5_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_4_mask */
+	uint32_t int4_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_3_mask */
+	uint32_t int3_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_2_mask */
+	uint32_t int2_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_1_mask */
+	uint32_t int1_mask	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_0_mask */
+	uint32_t int0_mask	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_INT_MASK ;
+#else
+typedef struct
+{	uint32_t int0_mask	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_0_mask */
+	uint32_t int1_mask	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_1_mask */
+	uint32_t int2_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_2_mask */
+	uint32_t int3_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_3_mask */
+	uint32_t int4_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_4_mask */
+	uint32_t int5_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_5_mask */
+	uint32_t int6_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_6_mask */
+	uint32_t int7_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Inerrupt_7_mask */
+	uint32_t int8_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_8_mask */
+	uint32_t int9_mask	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_9_mask */
+	uint32_t reserved0	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_INT_MASK ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_table_Configuration                                                           */
+/* Look-up table Configuration                                                           */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP0_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEP_1_VALUE                                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEP_1_VALUE_RESET_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEPS_2_VALUE                                 ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEPS_4_VALUE                                 ( 0x2 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEPS_8_VALUE                                 ( 0x3 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEPS_16_VALUE                                ( 0x4 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEPS_32_VALUE                                ( 0x5 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEPS_64_VALUE                                ( 0x6 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEPS_128_VALUE                               ( 0x7 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEPS_256_VALUE                               ( 0x8 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEPS_512_VALUE                               ( 0x9 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_STEPS_1K_VALUE                                ( 0xA )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define RUNNER_REGS_CFG_LKUP0_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define RUNNER_REGS_CFG_LKUP0_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_TABLE_SIZE_ENTRIES_32_VALUE                           ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_TABLE_SIZE_ENTRIES_32_VALUE_RESET_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_TABLE_SIZE_ENTRIES_64_VALUE                           ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_TABLE_SIZE_ENTRIES_128_VALUE                          ( 0x2 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_TABLE_SIZE_ENTRIES_256_VALUE                          ( 0x3 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_TABLE_SIZE_ENTRIES_512_VALUE                          ( 0x4 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_TABLE_SIZE_ENTRIES_1K_VALUE                           ( 0x5 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_TABLE_SIZE_ENTRIES_2K_VALUE                           ( 0x6 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_TABLE_SIZE_ENTRIES_4K_VALUE                           ( 0x7 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_LKUP0_CFG_OFFSET ( 0x00000010 )
+
+#define RUNNER_REGS_0_CFG_LKUP0_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP0_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP0_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP0_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP0_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP0_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP0_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP0_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP0_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP0_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP0_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP0_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP0_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP0_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP0_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP0_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP0_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop     	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP0_CFG ;
+#else
+typedef struct
+{	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t r1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t table_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t hash_type   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t max_hop     	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t reserved1   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP0_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_table_Configuration                                                           */
+/* Look-up table Configuration                                                           */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP1_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEP_1_VALUE                                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEP_1_VALUE_RESET_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEPS_2_VALUE                                 ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEPS_4_VALUE                                 ( 0x2 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEPS_8_VALUE                                 ( 0x3 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEPS_16_VALUE                                ( 0x4 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEPS_32_VALUE                                ( 0x5 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEPS_64_VALUE                                ( 0x6 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEPS_128_VALUE                               ( 0x7 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEPS_256_VALUE                               ( 0x8 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEPS_512_VALUE                               ( 0x9 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_STEPS_1K_VALUE                                ( 0xA )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define RUNNER_REGS_CFG_LKUP1_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define RUNNER_REGS_CFG_LKUP1_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_TABLE_SIZE_ENTRIES_32_VALUE                           ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_TABLE_SIZE_ENTRIES_32_VALUE_RESET_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_TABLE_SIZE_ENTRIES_64_VALUE                           ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_TABLE_SIZE_ENTRIES_128_VALUE                          ( 0x2 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_TABLE_SIZE_ENTRIES_256_VALUE                          ( 0x3 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_TABLE_SIZE_ENTRIES_512_VALUE                          ( 0x4 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_TABLE_SIZE_ENTRIES_1K_VALUE                           ( 0x5 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_TABLE_SIZE_ENTRIES_2K_VALUE                           ( 0x6 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_TABLE_SIZE_ENTRIES_4K_VALUE                           ( 0x7 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_RESERVED0_RESERVED_VALUE                              ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_RESERVED0_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_LKUP1_CFG_OFFSET ( 0x00000014 )
+
+#define RUNNER_REGS_0_CFG_LKUP1_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP1_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP1_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP1_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP1_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP1_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP1_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP1_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP1_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP1_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP1_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP1_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP1_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP1_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP1_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP1_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP1_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop     	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP1_CFG ;
+#else
+typedef struct
+{	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t table_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t hash_type   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t max_hop     	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t reserved1   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP1_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_table_Configuration                                                           */
+/* Look-up table Configuration                                                           */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP2_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEP_1_VALUE                                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEP_1_VALUE_RESET_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEPS_2_VALUE                                 ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEPS_4_VALUE                                 ( 0x2 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEPS_8_VALUE                                 ( 0x3 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEPS_16_VALUE                                ( 0x4 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEPS_32_VALUE                                ( 0x5 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEPS_64_VALUE                                ( 0x6 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEPS_128_VALUE                               ( 0x7 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEPS_256_VALUE                               ( 0x8 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEPS_512_VALUE                               ( 0x9 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_STEPS_1K_VALUE                                ( 0xA )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define RUNNER_REGS_CFG_LKUP2_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define RUNNER_REGS_CFG_LKUP2_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_TABLE_SIZE_ENTRIES_32_VALUE                           ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_TABLE_SIZE_ENTRIES_32_VALUE_RESET_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_TABLE_SIZE_ENTRIES_64_VALUE                           ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_TABLE_SIZE_ENTRIES_128_VALUE                          ( 0x2 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_TABLE_SIZE_ENTRIES_256_VALUE                          ( 0x3 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_TABLE_SIZE_ENTRIES_512_VALUE                          ( 0x4 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_TABLE_SIZE_ENTRIES_1K_VALUE                           ( 0x5 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_TABLE_SIZE_ENTRIES_2K_VALUE                           ( 0x6 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_TABLE_SIZE_ENTRIES_4K_VALUE                           ( 0x7 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_RESERVED0_RESERVED_VALUE                              ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_RESERVED0_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_LKUP2_CFG_OFFSET ( 0x00000018 )
+
+#define RUNNER_REGS_0_CFG_LKUP2_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP2_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP2_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP2_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP2_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP2_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP2_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP2_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP2_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP2_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP2_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP2_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP2_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP2_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP2_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP2_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP2_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop     	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP2_CFG ;
+#else
+typedef struct
+{	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t table_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t hash_type   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t max_hop     	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t reserved1   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP2_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_table_Configuration                                                           */
+/* Look-up table Configuration                                                           */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP3_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEP_1_VALUE                                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEP_1_VALUE_RESET_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEPS_2_VALUE                                 ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEPS_4_VALUE                                 ( 0x2 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEPS_8_VALUE                                 ( 0x3 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEPS_16_VALUE                                ( 0x4 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEPS_32_VALUE                                ( 0x5 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEPS_64_VALUE                                ( 0x6 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEPS_128_VALUE                               ( 0x7 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEPS_256_VALUE                               ( 0x8 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEPS_512_VALUE                               ( 0x9 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_STEPS_1K_VALUE                                ( 0xA )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
+#define RUNNER_REGS_CFG_LKUP3_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
+#define RUNNER_REGS_CFG_LKUP3_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_TABLE_SIZE_ENTRIES_32_VALUE                           ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_TABLE_SIZE_ENTRIES_32_VALUE_RESET_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_TABLE_SIZE_ENTRIES_64_VALUE                           ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_TABLE_SIZE_ENTRIES_128_VALUE                          ( 0x2 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_TABLE_SIZE_ENTRIES_256_VALUE                          ( 0x3 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_TABLE_SIZE_ENTRIES_512_VALUE                          ( 0x4 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_TABLE_SIZE_ENTRIES_1K_VALUE                           ( 0x5 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_TABLE_SIZE_ENTRIES_2K_VALUE                           ( 0x6 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_TABLE_SIZE_ENTRIES_4K_VALUE                           ( 0x7 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_RESERVED0_RESERVED_VALUE                              ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_RESERVED0_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_LKUP3_CFG_OFFSET ( 0x0000001C )
+
+#define RUNNER_REGS_0_CFG_LKUP3_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP3_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP3_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP3_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP3_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP3_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP3_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP3_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP3_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP3_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP3_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP3_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP3_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP3_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP3_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP3_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP3_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t max_hop     	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t hash_type   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t table_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP3_CFG ;
+#else
+typedef struct
+{	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_base_address */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t table_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Table_Size */
+	uint32_t hash_type   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Hash_Type */
+	uint32_t max_hop     	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Hop */
+	uint32_t reserved1   	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP3_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_table_CAM_configuration                                                       */
+/* Look-up table CAM configuration                                                       */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_RESERVED0_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_RESERVED0_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_OFFSET ( 0x00000020 )
+
+#define RUNNER_REGS_0_CFG_LKUP0_CAM_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP0_CAM_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP0_CAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP0_CAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP0_CAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP0_CAM_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP0_CAM_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP0_CAM_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP0_CAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP0_CAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP0_CAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP0_CAM_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP0_CAM_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP0_CAM_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP0_CAM_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP0_CAM_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP0_CAM_CFG ;
+#else
+typedef struct
+{	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP0_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_table_CAM_configuration                                                       */
+/* Look-up table CAM configuration                                                       */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_RESERVED0_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_RESERVED0_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_OFFSET ( 0x00000024 )
+
+#define RUNNER_REGS_0_CFG_LKUP1_CAM_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP1_CAM_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP1_CAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP1_CAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP1_CAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP1_CAM_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP1_CAM_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP1_CAM_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP1_CAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP1_CAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP1_CAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP1_CAM_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP1_CAM_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP1_CAM_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP1_CAM_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP1_CAM_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP1_CAM_CFG ;
+#else
+typedef struct
+{	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP1_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_table_CAM_configuration                                                       */
+/* Look-up table CAM configuration                                                       */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_RESERVED0_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_RESERVED0_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_OFFSET ( 0x00000028 )
+
+#define RUNNER_REGS_0_CFG_LKUP2_CAM_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP2_CAM_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP2_CAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP2_CAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP2_CAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP2_CAM_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP2_CAM_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP2_CAM_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP2_CAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP2_CAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP2_CAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP2_CAM_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP2_CAM_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP2_CAM_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP2_CAM_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP2_CAM_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP2_CAM_CFG ;
+#else
+typedef struct
+{	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP2_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_table_CAM_configuration                                                       */
+/* Look-up table CAM configuration                                                       */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_RESERVED0_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_RESERVED0_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_OFFSET ( 0x0000002C )
+
+#define RUNNER_REGS_0_CFG_LKUP3_CAM_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP3_CAM_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP3_CAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP3_CAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP3_CAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP3_CAM_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP3_CAM_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP3_CAM_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP3_CAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP3_CAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP3_CAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP3_CAM_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP3_CAM_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP3_CAM_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP3_CAM_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP3_CAM_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Resreved */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP3_CAM_CFG ;
+#else
+typedef struct
+{	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t reserved0   	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t cam_en      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_enable */
+	uint32_t resreved1   	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Resreved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP3_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* PSRAM_config_Register                                                                 */
+/* PSRAM config Register. Contains configurations such as buffer size and ddr base addre */
+/* ss that are used for PSRAM address calculations (from buffer number) when DMA instruc */
+/* tion addr_calc flag is set.                                                           */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PSRAM_CFG_RSERVED2_RSERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_RSERVED2_RSERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_DMA_BASE_DEFAULT_VALUE                       ( 0x30 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_DMA_BASE_DEFAULT_VALUE_RESET_VALUE           ( 0x30 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_BUFFER_SIZE_BUFFER_SIZE_2K_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_BUFFER_SIZE_BUFFER_SIZE_2K_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_BUFFER_SIZE_BUFFER_SIZE_4K_VALUE             ( 0x1 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_BUFFER_SIZE_BUFFER_SIZE_16K_VALUE            ( 0x2 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_BUFFER_SIZE_BUFFER_SIZE_128BYTE_VALUE        ( 0x3 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_RSERVED1_RSERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_RSERVED1_RSERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_BUFFER_OFFSET_DEFAULT_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_CFG_BUFFER_OFFSET_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PSRAM_CFG_OFFSET ( 0x00000030 )
+
+#define RUNNER_REGS_0_CFG_PSRAM_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PSRAM_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_PSRAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PSRAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PSRAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PSRAM_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PSRAM_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PSRAM_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_PSRAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PSRAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PSRAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PSRAM_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PSRAM_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PSRAM_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PSRAM_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PSRAM_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PSRAM_CFG_ARRAY [ i ], (r) )  
+
+#ifdef CONFIG_BCM6848
+/* XXX: Please apply this change to DSL platforms if start using PSRAM for DSL */
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Rserved */
+	uint32_t rserved2     	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+    /* New Address calc */
+	uint32_t new_address_calc : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_base_address */
+	uint32_t dma_base     	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_size */
+	uint32_t buffer_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+	uint32_t rserved1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_Offset */
+	uint32_t buffer_offset	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_CFG ;
+#else
+typedef struct
+{	
+	/* Buffer_Offset */
+    uint32_t buffer_offset	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+	uint32_t rserved1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_size */
+	uint32_t buffer_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_base_address */
+	uint32_t dma_base     	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	
+    /* New Address calc */
+	uint32_t new_address_calc : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+	uint32_t rserved2     	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_CFG ;
+#endif
+#else
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Rserved */
+	uint32_t rserved2     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_base_address */
+	uint32_t dma_base     	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_size */
+	uint32_t buffer_size  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+	uint32_t rserved1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_Offset */
+	uint32_t buffer_offset	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_CFG ;
+#else
+typedef struct
+{	uint32_t buffer_offset	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_Offset */
+	uint32_t rserved1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+	uint32_t buffer_size  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_size */
+	uint32_t dma_base     	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_base_address */
+	uint32_t rserved2     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_CFG ;
+#endif
+#endif
+
+/*****************************************************************************************/
+/* CAM_configuration                                                                     */
+/* CAM configuration                                                                     */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_CAM_CFG_RESERVED0_RESERVED_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_CAM_CFG_RESERVED0_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_CAM_CFG_STOP_VALUE_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_CAM_CFG_STOP_VALUE_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_CAM_CFG_OFFSET ( 0x00000034 )
+
+#define RUNNER_REGS_0_CFG_CAM_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_CAM_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_CAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_CAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_CAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_CAM_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_CAM_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_CAM_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_CAM_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_CAM_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_CAM_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_CAM_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_CAM_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_CAM_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_CAM_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_CAM_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_CAM_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserevd */
+	uint32_t reserved0 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Stop_Value */
+	uint32_t stop_value	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_CAM_CFG ;
+#else
+typedef struct
+{	uint32_t stop_value	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Stop_Value */
+	uint32_t reserved0 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserevd */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_CAM_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Counters_Configuration                                                                */
+/* Counters Configuration                                                                */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_CNTR_CFG_RESERVED0_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_CNTR_CFG_RESERVED0_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_CNTR_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_CNTR_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_CNTR_CFG_OFFSET ( 0x00000038 )
+
+#define RUNNER_REGS_0_CFG_CNTR_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_CNTR_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_CNTR_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_CNTR_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_CNTR_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_CNTR_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_CNTR_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_CNTR_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_CNTR_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_CNTR_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_CNTR_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_CNTR_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_CNTR_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_CNTR_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_CNTR_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_CNTR_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_CNTR_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved0   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_CNTR_CFG ;
+#else
+typedef struct
+{	uint32_t base_address	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Base_Address */
+	uint32_t reserved0   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_CNTR_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* DDR_config_Register                                                                   */
+/* DDR config Register. Contains configurations such as buffer size and ddr base address */
+/*  that are used for DDR address calculations (from buffer number) when DMA instruction */
+/*  addr_calc flag is set.                                                               */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_DDR_CFG_RSERVED2_RSERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_CFG_RSERVED2_RSERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_CFG_DMA_BASE_DEFAULT_VALUE                       ( 0x30 )
+#define RUNNER_REGS_CFG_DDR_CFG_DMA_BASE_DEFAULT_VALUE_RESET_VALUE           ( 0x30 )
+#define RUNNER_REGS_CFG_DDR_CFG_BUFFER_SIZE_BUFFER_SIZE_2K_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_CFG_BUFFER_SIZE_BUFFER_SIZE_2K_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_CFG_BUFFER_SIZE_BUFFER_SIZE_4K_VALUE             ( 0x1 )
+#define RUNNER_REGS_CFG_DDR_CFG_BUFFER_SIZE_BUFFER_SIZE_16K_VALUE            ( 0x2 )
+#define RUNNER_REGS_CFG_DDR_CFG_BUFFER_SIZE_RESERVED_VALUE                   ( 0x3 )
+#define RUNNER_REGS_CFG_DDR_CFG_RSERVED1_RSERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_CFG_RSERVED1_RSERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_CFG_BUFFER_OFFSET_DEFAULT_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_CFG_BUFFER_OFFSET_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_DDR_CFG_OFFSET ( 0x0000003C )
+
+#define RUNNER_REGS_0_CFG_DDR_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_DDR_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_DDR_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_DDR_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_DDR_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_DDR_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_DDR_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_DDR_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_DDR_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_DDR_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_DDR_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_DDR_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_DDR_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_DDR_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_DDR_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_DDR_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_DDR_CFG_ARRAY [ i ], (r) )  
+
+#if defined(CONFIG_BCM6848) || defined(DSL_63138)
+/* XXX: Please apply this change to DSL platforms if start using PSRAM for DSL */
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Rserved */
+	uint32_t rserved2     	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+    /* New Address calc */
+	uint32_t new_address_calc : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_base_address */
+	uint32_t dma_base     	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_size */
+	uint32_t buffer_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+	uint32_t rserved1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_Offset */
+	uint32_t buffer_offset	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_CFG ;
+#else
+typedef struct
+{	uint32_t buffer_offset	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_Offset */
+	uint32_t rserved1     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+	uint32_t buffer_size  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_size */
+	uint32_t dma_base     	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+    /* New Address calc */
+	uint32_t new_address_calc : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+	uint32_t rserved2     	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_CFG ;
+#endif
+#else
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Rserved */
+	uint32_t rserved2     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_base_address */
+	uint32_t dma_base     	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_size */
+	uint32_t buffer_size  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+	uint32_t rserved1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_Offset */
+	uint32_t buffer_offset	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_CFG ;
+#else
+typedef struct
+{	uint32_t buffer_offset	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_Offset */
+	uint32_t rserved1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+	uint32_t buffer_size  	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Buffer_size */
+	uint32_t dma_base     	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DMA_base_address */
+	uint32_t rserved2     	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Rserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_CFG ;
+#endif
+#endif
+
+/*****************************************************************************************/
+/* Semaphore_Status_and_Control                                                          */
+/* This register is used for taking and releasing the Semaphores 0-3                     */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RESERVED3_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RESERVED3_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RELEASE3_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RELEASE3_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS3_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS3_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS3_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RESERVED2_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RESERVED2_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RELEASE2_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RELEASE2_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS2_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS2_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS2_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RESERVED1_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RESERVED1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RELEASE1_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RELEASE1_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS1_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS1_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS1_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RESERVED0_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RESERVED0_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RELEASE0_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_RELEASE0_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS0_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS0_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_STATUS0_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_OFFSET ( 0x00000040 )
+
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_0_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_OFFSET )
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_0_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_0_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_0_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_0_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_0_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_OFFSET )
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_0_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_0_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_0_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_0_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_3_Release_Request */
+	uint32_t release3 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_3_Status */
+	uint32_t status3  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_2_Release_Request */
+	uint32_t release2 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_2_Status */
+	uint32_t status2  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_1_Release_Request */
+	uint32_t release1 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_1_Status */
+	uint32_t status1  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved_for_eco */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_0_Release_Request */
+	uint32_t release0 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_0_Status */
+	uint32_t status0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0 ;
+#else
+typedef struct
+{	uint32_t status0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_0_Status */
+	uint32_t release0 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_0_Release_Request */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved_for_eco */
+	uint32_t status1  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_1_Status */
+	uint32_t release1 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_1_Release_Request */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status2  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_2_Status */
+	uint32_t release2 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_2_Release_Request */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status3  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_3_Status */
+	uint32_t release3 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_3_Release_Request */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0 ;
+#endif
+
+/*****************************************************************************************/
+/* Semaphore_Status_and_Control                                                          */
+/* This register is used for taking and releasing the Semaphores 4-7                     */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RESERVED3_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RESERVED3_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RELEASE7_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RELEASE7_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS7_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS7_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS7_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RESERVED2_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RESERVED2_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RELEASE6_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RELEASE6_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS6_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS6_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS6_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RESERVED1_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RESERVED1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RELEASE5_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RELEASE5_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS5_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS5_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS5_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RESERVED0_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RESERVED0_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RELEASE4_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_RELEASE4_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS4_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS4_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_STATUS4_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_OFFSET ( 0x00000044 )
+
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_1_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_OFFSET )
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_1_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_1_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_1_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_1_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_1_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_OFFSET )
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_1_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_1_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_1_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_1_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7Release_Request */
+	uint32_t release7 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7_Status */
+	uint32_t status7  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Release_Request */
+	uint32_t release6 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Status */
+	uint32_t status6  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Release_Request */
+	uint32_t release5 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Status */
+	uint32_t status5  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Release_Request */
+	uint32_t release4 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Status */
+	uint32_t status4  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1 ;
+#else
+typedef struct
+{	uint32_t status4  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Status */
+	uint32_t release4 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Release_Request */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status5  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Status */
+	uint32_t release5 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Release_Request */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status6  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Status */
+	uint32_t release6 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Release_Request */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status7  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7_Status */
+	uint32_t release7 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7Release_Request */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1 ;
+#endif
+
+/*****************************************************************************************/
+/* Semaphore_Status_and_Control                                                          */
+/* This register is used for taking and releasing the Semaphores 8-11                    */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RESERVED3_RESERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RESERVED3_RESERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RELEASE11_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RELEASE11_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS11_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS11_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS11_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RESERVED2_RESERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RESERVED2_RESERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RELEASE10_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RELEASE10_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS10_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS10_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS10_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RESERVED1_RESERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RESERVED1_RESERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RELEASE9_DEFAULT_VALUE                         ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RELEASE9_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS9_OWNERSHIP_NOT_TAKEN_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS9_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE  ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS9_OWNERSHIP_TAKEN_VALUE                  ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RESERVED0_RESERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RESERVED0_RESERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RELEASE8_DEFAULT_VALUE                         ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_RELEASE8_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS8_OWNERSHIP_NOT_TAKEN_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS8_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE  ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_STATUS8_OWNERSHIP_TAKEN_VALUE                  ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_OFFSET ( 0x00000048 )
+
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_2_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_OFFSET )
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_2_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_2_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_2_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_2_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_2_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_OFFSET )
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_2_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_2_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_2_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_2_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_11_Release_Request */
+	uint32_t release11	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_11_Status */
+	uint32_t status11 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_10_Release_Request */
+	uint32_t release10	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_10_Status */
+	uint32_t status10 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_9_Release_Request */
+	uint32_t release9 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_9_Status */
+	uint32_t status9  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_8_Release_Request */
+	uint32_t release8 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_8_Status */
+	uint32_t status8  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2 ;
+#else
+typedef struct
+{	uint32_t status8  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_8_Status */
+	uint32_t release8 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_8_Release_Request */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status9  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_9_Status */
+	uint32_t release9 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_9_Release_Request */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status10 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_10_Status */
+	uint32_t release10	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_10_Release_Request */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status11 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_11_Status */
+	uint32_t release11	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_11_Release_Request */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2 ;
+#endif
+
+/*****************************************************************************************/
+/* Semaphore_Status_and_Control                                                          */
+/* This register is used for taking and releasing the Semaphores 12-15                   */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RESERVED3_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RESERVED3_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RELEASE7_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RELEASE7_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS7_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS7_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS7_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RESERVED2_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RESERVED2_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RELEASE6_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RELEASE6_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS6_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS6_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS6_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RESERVED1_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RESERVED1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RELEASE5_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RELEASE5_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS5_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS5_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS5_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RESERVED0_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RESERVED0_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RELEASE4_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_RELEASE4_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS4_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS4_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_STATUS4_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_OFFSET ( 0x0000004C )
+
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_3_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_OFFSET )
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_3_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_3_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_3_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MIPSC_SEMAPHOR_STS_3_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_3_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_OFFSET )
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_3_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_3_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_3_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MIPSC_SEMAPHOR_STS_3_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7Release_Request */
+	uint32_t release7 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7_Status */
+	uint32_t status7  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Release_Request */
+	uint32_t release6 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Status */
+	uint32_t status6  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Release_Request */
+	uint32_t release5 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Status */
+	uint32_t status5  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Release_Request */
+	uint32_t release4 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Status */
+	uint32_t status4  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3 ;
+#else
+typedef struct
+{	uint32_t status4  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Status */
+	uint32_t release4 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Release_Request */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status5  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Status */
+	uint32_t release5 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Release_Request */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status6  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Status */
+	uint32_t release6 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Release_Request */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status7  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7_Status */
+	uint32_t release7 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7Release_Request */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3 ;
+#endif
+
+/*****************************************************************************************/
+/* DDR_look-up_Global_Mask                                                               */
+/* DDR look-up Global Mask                                                               */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK0_RESERVED0_RESERVED_VALUE                                    ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK0_RESERVED0_RESERVED_VALUE_RESET_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK0_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK0_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK0_OFFSET ( 0x00000050 )
+
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK0_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_DDR_LKUP_MASK0_OFFSET )
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK0_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_DDR_LKUP_MASK0_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK0_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_DDR_LKUP_MASK0_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK0_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_DDR_LKUP_MASK0_OFFSET )
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK0_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_DDR_LKUP_MASK0_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK0_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_DDR_LKUP_MASK0_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_DDR_LKUP_MASK0_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK0_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_DDR_LKUP_MASK0_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK0_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_DDR_LKUP_MASK0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved0 */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_LKUP_MASK0 ;
+#else
+typedef struct
+{	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved0 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_LKUP_MASK0 ;
+#endif
+
+/*****************************************************************************************/
+/* DDR_look-up_Global_Mask                                                               */
+/* DDR look-up Global Mask                                                               */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK1_RESERVED0_RESERVED_VALUE                                    ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK1_RESERVED0_RESERVED_VALUE_RESET_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK1_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK1_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK1_OFFSET ( 0x00000054 )
+
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK1_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_DDR_LKUP_MASK1_OFFSET )
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK1_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_DDR_LKUP_MASK1_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK1_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_DDR_LKUP_MASK1_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK1_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_DDR_LKUP_MASK1_OFFSET )
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK1_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_DDR_LKUP_MASK1_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK1_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_DDR_LKUP_MASK1_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_DDR_LKUP_MASK1_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK1_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_DDR_LKUP_MASK1_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK1_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_DDR_LKUP_MASK1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved0 */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_LKUP_MASK1 ;
+#else
+typedef struct
+{	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved0 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_LKUP_MASK1 ;
+#endif
+
+/*****************************************************************************************/
+/* DDR_look-up_Global_Mask                                                               */
+/* DDR look-up Global Mask                                                               */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK2_RESERVED0_RESERVED_VALUE                                    ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK2_RESERVED0_RESERVED_VALUE_RESET_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK2_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK2_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK2_OFFSET ( 0x00000058 )
+
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK2_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_DDR_LKUP_MASK2_OFFSET )
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK2_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_DDR_LKUP_MASK2_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK2_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_DDR_LKUP_MASK2_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK2_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_DDR_LKUP_MASK2_OFFSET )
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK2_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_DDR_LKUP_MASK2_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK2_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_DDR_LKUP_MASK2_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_DDR_LKUP_MASK2_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK2_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_DDR_LKUP_MASK2_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK2_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_DDR_LKUP_MASK2_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved0 */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_LKUP_MASK2 ;
+#else
+typedef struct
+{	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved0 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_LKUP_MASK2 ;
+#endif
+
+/*****************************************************************************************/
+/* DDR_look-up_Global_Mask                                                               */
+/* DDR look-up Global Mask                                                               */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK3_RESERVED0_RESERVED_VALUE                                    ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK3_RESERVED0_RESERVED_VALUE_RESET_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK3_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK3_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK3_OFFSET ( 0x0000005C )
+
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK3_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_DDR_LKUP_MASK3_OFFSET )
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK3_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_DDR_LKUP_MASK3_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_DDR_LKUP_MASK3_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_DDR_LKUP_MASK3_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK3_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_DDR_LKUP_MASK3_OFFSET )
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK3_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_DDR_LKUP_MASK3_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_DDR_LKUP_MASK3_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_DDR_LKUP_MASK3_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_DDR_LKUP_MASK3_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK3_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_DDR_LKUP_MASK3_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_DDR_LKUP_MASK3_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_DDR_LKUP_MASK3_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved0 */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_LKUP_MASK3 ;
+#else
+typedef struct
+{	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved0 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_DDR_LKUP_MASK3 ;
+#endif
+
+/*****************************************************************************************/
+/* PSRAM_look-up_Global_Mask                                                             */
+/* PSRAM look-up Global Mask                                                             */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_RESERVED0_RESERVED_VALUE                                    ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_RESERVED0_RESERVED_VALUE_RESET_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_OFFSET ( 0x00000060 )
+
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK0_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_OFFSET )
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK0_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK0_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK0_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK0_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK0_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_OFFSET )
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK0_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK0_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK0_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK0_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PSRAM_LKUP_MASK0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved0 */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_LKUP_MASK0 ;
+#else
+typedef struct
+{	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved0 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_LKUP_MASK0 ;
+#endif
+
+/*****************************************************************************************/
+/* PSRAM_look-up_Global_Mask                                                             */
+/* PSRAM look-up Global Mask                                                             */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_RESERVED0_RESERVED_VALUE                                    ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_RESERVED0_RESERVED_VALUE_RESET_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_OFFSET ( 0x00000064 )
+
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK1_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_OFFSET )
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK1_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK1_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK1_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK1_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK1_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_OFFSET )
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK1_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK1_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK1_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK1_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PSRAM_LKUP_MASK1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved0 */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_LKUP_MASK1 ;
+#else
+typedef struct
+{	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved0 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_LKUP_MASK1 ;
+#endif
+
+/*****************************************************************************************/
+/* PSRAM_look-up_Global_Mask                                                             */
+/* PSRAM look-up Global Mask                                                             */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_RESERVED0_RESERVED_VALUE                                    ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_RESERVED0_RESERVED_VALUE_RESET_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_OFFSET ( 0x00000068 )
+
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK2_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_OFFSET )
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK2_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK2_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK2_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK2_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK2_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_OFFSET )
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK2_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK2_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK2_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK2_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PSRAM_LKUP_MASK2_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved0 */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_LKUP_MASK2 ;
+#else
+typedef struct
+{	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved0 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_LKUP_MASK2 ;
+#endif
+
+/*****************************************************************************************/
+/* PSRAM_look-up_Global_Mask                                                             */
+/* PSRAM look-up Global Mask                                                             */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_RESERVED0_RESERVED_VALUE                                    ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_RESERVED0_RESERVED_VALUE_RESET_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_GLOBAL_MASK_KEY_5_TUPLE_KEY_DEFAULT_VALUE_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_OFFSET ( 0x0000006C )
+
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK3_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_OFFSET )
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK3_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK3_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK3_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PSRAM_LKUP_MASK3_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK3_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_OFFSET )
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK3_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK3_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK3_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PSRAM_LKUP_MASK3_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PSRAM_LKUP_MASK3_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved0 */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_LKUP_MASK3 ;
+#else
+typedef struct
+{	uint32_t global_mask	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Mask */
+	uint32_t reserved0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved0 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PSRAM_LKUP_MASK3 ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_global_mask                                                                   */
+/* Look-up global mask                                                                   */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_RESERVED1_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_RESERVED1_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_BASE_ADDRESS_DEFAULT_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_OFFSET ( 0x00000070 )
+
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK0_H_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK0_H_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK0_H_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK0_H_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK0_H_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK0_H_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK0_H_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK0_H_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK0_H_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK0_H_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_H */
+	uint32_t base_address	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H ;
+#else
+typedef struct
+{	uint32_t base_address	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_H */
+	uint32_t reserved1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_global_mask                                                                   */
+/* Look-up global mask                                                                   */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L_BASE_ADDRESS_DEFAULT_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L_OFFSET ( 0x00000074 )
+
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK0_L_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK0_L_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK0_L_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK0_L_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK0_L_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK0_L_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK0_L_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK0_L_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK0_L_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK0_L_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Global_mask_L */
+	uint32_t base_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L ;
+#else
+typedef struct
+{	uint32_t base_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_L */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_global_mask                                                                   */
+/* Look-up global mask                                                                   */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_RESERVED1_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_RESERVED1_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_BASE_ADDRESS_DEFAULT_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_OFFSET ( 0x00000078 )
+
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK1_H_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK1_H_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK1_H_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK1_H_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK1_H_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK1_H_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK1_H_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK1_H_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK1_H_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK1_H_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_H */
+	uint32_t base_address	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H ;
+#else
+typedef struct
+{	uint32_t base_address	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_H */
+	uint32_t reserved1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_global_mask                                                                   */
+/* Look-up global mask                                                                   */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L_BASE_ADDRESS_DEFAULT_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L_OFFSET ( 0x0000007C )
+
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK1_L_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK1_L_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK1_L_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK1_L_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK1_L_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK1_L_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK1_L_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK1_L_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK1_L_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK1_L_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Global_mask_L */
+	uint32_t base_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L ;
+#else
+typedef struct
+{	uint32_t base_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_L */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_global_mask                                                                   */
+/* Look-up global mask                                                                   */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_RESERVED1_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_RESERVED1_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_BASE_ADDRESS_DEFAULT_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_OFFSET ( 0x00000080 )
+
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK2_H_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK2_H_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK2_H_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK2_H_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK2_H_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK2_H_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK2_H_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK2_H_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK2_H_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK2_H_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_H */
+	uint32_t base_address	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H ;
+#else
+typedef struct
+{	uint32_t base_address	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_H */
+	uint32_t reserved1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_global_mask                                                                   */
+/* Look-up global mask                                                                   */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L_BASE_ADDRESS_DEFAULT_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L_OFFSET ( 0x00000084 )
+
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK2_L_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK2_L_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK2_L_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK2_L_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK2_L_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK2_L_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK2_L_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK2_L_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK2_L_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK2_L_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Global_mask_L */
+	uint32_t base_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L ;
+#else
+typedef struct
+{	uint32_t base_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_L */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_global_mask                                                                   */
+/* Look-up global mask                                                                   */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_RESERVED1_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_RESERVED1_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_BASE_ADDRESS_DEFAULT_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_OFFSET ( 0x00000088 )
+
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK3_H_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK3_H_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK3_H_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK3_H_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK3_H_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK3_H_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK3_H_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK3_H_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK3_H_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK3_H_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_H */
+	uint32_t base_address	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H ;
+#else
+typedef struct
+{	uint32_t base_address	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_H */
+	uint32_t reserved1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H ;
+#endif
+
+/*****************************************************************************************/
+/* Look-up_global_mask                                                                   */
+/* Look-up global mask                                                                   */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L_BASE_ADDRESS_DEFAULT_VALUE             ( 0xFF )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0xFF )
+
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L_OFFSET ( 0x0000008C )
+
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK3_L_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK3_L_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK3_L_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP_GLBL_MASK3_L_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP_GLBL_MASK3_L_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK3_L_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK3_L_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK3_L_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP_GLBL_MASK3_L_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP_GLBL_MASK3_L_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Global_mask_L */
+	uint32_t base_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L ;
+#else
+typedef struct
+{	uint32_t base_address	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_mask_L */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L ;
+#endif
+
+/*****************************************************************************************/
+/* Look_up_configuration                                                                 */
+/* Lookup hash configuration.                                                            */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_LKUP_CFG_R1_RESERVED_VALUE                                  ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_CFG_R1_RESERVED_VALUE_RESET_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_CFG_LKUP_NVAL_CAM_SEARCH_DONT_SEARCH_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_CFG_LKUP_NVAL_CAM_SEARCH_DONT_SEARCH_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_LKUP_CFG_LKUP_NVAL_CAM_SEARCH_SEARCH_VALUE                  ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_LKUP_CFG_OFFSET ( 0x00000090 )
+
+#define RUNNER_REGS_0_CFG_LKUP_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_LKUP_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_LKUP_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_LKUP_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_LKUP_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_LKUP_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_LKUP_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_LKUP_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_LKUP_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_LKUP_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_LKUP_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_LKUP_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_LKUP_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_LKUP_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_LKUP_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_LKUP_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t r1                  	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Lkup_nval_cam_search */
+	uint32_t lkup_nval_cam_search	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_CFG ;
+#else
+typedef struct
+{	uint32_t lkup_nval_cam_search	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Lkup_nval_cam_search */
+	uint32_t r1                  	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_LKUP_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Main_profiling_sts                                                                    */
+/* main profiling status                                                                 */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_TRACE_WRITE_PNT_TRACE_WRITE_POINTER_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_TRACE_WRITE_PNT_TRACE_WRITE_POINTER_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_RESERVED2_RESERVED2_VALUE                                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_RESERVED2_RESERVED2_VALUE_RESET_VALUE                     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_PROFILING_ACTIVE_PROFILING_VALUE                          ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_PROFILING_ACTIVE_PROFILING_VALUE_RESET_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_IDLE_NO_ACTIVE_TASK_IDLE_NO_ACTIVE_TASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_IDLE_NO_ACTIVE_TASK_IDLE_NO_ACTIVE_TASK_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_CURR_THREAD_NUM_CURR_THREAD_VALUE                         ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_CURR_THREAD_NUM_CURR_THREAD_VALUE_RESET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_RESERVED1_RESERVED_VALUE                                  ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_RESERVED1_RESERVED_VALUE_RESET_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_AGU_NEXT_PC_DEFAULT_VALUE                                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_AGU_NEXT_PC_DEFAULT_VALUE_RESET_VALUE                     ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_OFFSET ( 0x000000B0 )
+
+#define RUNNER_REGS_0_CFG_MAIN_PROFILING_STS_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_PROFILING_STS_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_PROFILING_STS_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_PROFILING_STS_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_PROFILING_STS_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_PROFILING_STS_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_PROFILING_STS_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_PROFILING_STS_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_PROFILING_STS_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_PROFILING_STS_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_PROFILING_STS_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_PROFILING_STS_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_PROFILING_STS_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_PROFILING_STS_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_STS_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_PROFILING_STS_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Trace_write_pointer */
+	uint32_t trace_write_pnt    	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved2 */
+	uint32_t reserved2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Profiling_active */
+	uint32_t profiling_active   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IDLE_no_active_task */
+	uint32_t idle_no_active_task	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CURR_thread_num */
+	uint32_t curr_thread_num    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved1 */
+	uint32_t reserved1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* AGU_next_pc */
+	uint32_t agu_next_pc        	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_PROFILING_STS ;
+#else
+typedef struct
+{	uint32_t agu_next_pc        	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* AGU_next_pc */
+	uint32_t reserved1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved1 */
+	uint32_t curr_thread_num    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CURR_thread_num */
+	uint32_t idle_no_active_task	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IDLE_no_active_task */
+	uint32_t profiling_active   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Profiling_active */
+	uint32_t reserved2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved2 */
+	uint32_t trace_write_pnt    	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Trace_write_pointer */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_PROFILING_STS ;
+#endif
+
+/*****************************************************************************************/
+/* Main_profiling_cfg                                                                    */
+/* main profiling confuguration                                                          */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_TRACE_BASE_ADDR_RESERVED_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_TRACE_BASE_ADDR_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_PROF_STOP_RESERVED_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_PROF_STOP_RESERVED_VALUE_RESET_VALUE       ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_PROF_START_RESERVED_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_PROF_START_RESERVED_VALUE_RESET_VALUE      ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_RSV1_RSV_VALUE                             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_RSV1_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_TRACE_PC_EN_RESERVED_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_TRACE_PC_EN_RESERVED_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_PROF_TASK2_RESERVED_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_PROF_TASK2_RESERVED_VALUE_RESET_VALUE      ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_PROF_TASK1_RESERVED_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_PROF_TASK1_RESERVED_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_OFFSET ( 0x000000B4 )
+
+#define RUNNER_REGS_0_CFG_MAIN_PROFILING_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_PROFILING_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_PROFILING_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_PROFILING_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_PROFILING_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_PROFILING_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_PROFILING_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_PROFILING_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_PROFILING_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_PROFILING_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_PROFILING_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_PROFILING_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_PROFILING_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_PROFILING_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_PROFILING_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_PROFILING_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRACE_BASE_ADDR */
+	uint32_t trace_base_addr	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_STOP */
+	uint32_t prof_stop      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_START */
+	uint32_t prof_start     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t rsv1           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRACE_PC_EN */
+	uint32_t trace_pc_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_TASK2 */
+	uint32_t prof_task2     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_TASK1 */
+	uint32_t prof_task1     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_PROFILING_CFG ;
+#else
+typedef struct
+{	uint32_t prof_task1     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_TASK1 */
+	uint32_t prof_task2     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_TASK2 */
+	uint32_t trace_pc_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRACE_PC_EN */
+	uint32_t rsv1           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t prof_start     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_START */
+	uint32_t prof_stop      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_STOP */
+	uint32_t trace_base_addr	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRACE_BASE_ADDR */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_PROFILING_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Main_stall_cnt1                                                                       */
+/* main stall count                                                                      */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT1_ACC_STALL_CNT_RESERVED1_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT1_ACC_STALL_CNT_RESERVED1_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT1_LD_STALL_CNT_RESERVED1_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT1_LD_STALL_CNT_RESERVED1_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT1_OFFSET ( 0x000000B8 )
+
+#define RUNNER_REGS_0_CFG_MAIN_STALL_CNT1_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_STALL_CNT1_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_STALL_CNT1_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_STALL_CNT1_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_STALL_CNT1_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_STALL_CNT1_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_STALL_CNT1_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_STALL_CNT1_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_STALL_CNT1_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_STALL_CNT1_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_STALL_CNT1_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_STALL_CNT1_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_STALL_CNT1_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT1_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_STALL_CNT1_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT1_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_STALL_CNT1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* ACC_STALL_CNT */
+	uint32_t acc_stall_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LD_STALL_CNT */
+	uint32_t ld_stall_cnt 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_STALL_CNT1 ;
+#else
+typedef struct
+{	uint32_t ld_stall_cnt 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LD_STALL_CNT */
+	uint32_t acc_stall_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ACC_STALL_CNT */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_STALL_CNT1 ;
+#endif
+
+/*****************************************************************************************/
+/* Main_stall_cnt2                                                                       */
+/* main stall count                                                                      */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT2_STORE_STALL_CNT_RESERVED0_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT2_STORE_STALL_CNT_RESERVED0_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT2_LDIO_STALL_CNT_RESERVED0_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT2_LDIO_STALL_CNT_RESERVED0_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT2_OFFSET ( 0x000000BC )
+
+#define RUNNER_REGS_0_CFG_MAIN_STALL_CNT2_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_STALL_CNT2_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_STALL_CNT2_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_STALL_CNT2_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_STALL_CNT2_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_STALL_CNT2_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_STALL_CNT2_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_STALL_CNT2_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_STALL_CNT2_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_STALL_CNT2_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_STALL_CNT2_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_STALL_CNT2_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_STALL_CNT2_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT2_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_STALL_CNT2_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_STALL_CNT2_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_STALL_CNT2_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* STORE_STALL_CNT */
+	uint32_t store_stall_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LDIO_STALL_CNT */
+	uint32_t ldio_stall_cnt 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_STALL_CNT2 ;
+#else
+typedef struct
+{	uint32_t ldio_stall_cnt 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LDIO_STALL_CNT */
+	uint32_t store_stall_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* STORE_STALL_CNT */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_STALL_CNT2 ;
+#endif
+
+/*****************************************************************************************/
+/* Main_task_cnt1                                                                        */
+/* main task1 count                                                                      */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_TASK1_CNT_TASK1_CNT_RESERVED_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_TASK1_CNT_TASK1_CNT_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_TASK1_CNT_OFFSET ( 0x000000C0 )
+
+#define RUNNER_REGS_0_CFG_MAIN_TASK1_CNT_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_TASK1_CNT_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_TASK1_CNT_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_TASK1_CNT_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_TASK1_CNT_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_TASK1_CNT_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_TASK1_CNT_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_TASK1_CNT_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_TASK1_CNT_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_TASK1_CNT_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_TASK1_CNT_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_TASK1_CNT_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_TASK1_CNT_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_TASK1_CNT_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_TASK1_CNT_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_TASK1_CNT_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_TASK1_CNT_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* TASK1_CNT */
+	uint32_t task1_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_TASK1_CNT ;
+#else
+typedef struct
+{	uint32_t task1_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TASK1_CNT */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_TASK1_CNT ;
+#endif
+
+/*****************************************************************************************/
+/* Main_task_cnt2                                                                        */
+/* main task2 count                                                                      */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_TASK2_CNT_TASK2_CNT_RESERVED_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_TASK2_CNT_TASK2_CNT_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_TASK2_CNT_OFFSET ( 0x000000C4 )
+
+#define RUNNER_REGS_0_CFG_MAIN_TASK2_CNT_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_TASK2_CNT_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_TASK2_CNT_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_TASK2_CNT_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_TASK2_CNT_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_TASK2_CNT_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_TASK2_CNT_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_TASK2_CNT_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_TASK2_CNT_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_TASK2_CNT_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_TASK2_CNT_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_TASK2_CNT_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_TASK2_CNT_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_TASK2_CNT_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_TASK2_CNT_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_TASK2_CNT_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_TASK2_CNT_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* TASK2_CNT */
+	uint32_t task2_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_TASK2_CNT ;
+#else
+typedef struct
+{	uint32_t task2_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TASK2_CNT */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_TASK2_CNT ;
+#endif
+
+/*****************************************************************************************/
+/* Main_idle_cnt1                                                                        */
+/* main idle count                                                                       */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_IDLE_CNT1_IDLE_CNT_RESERVED_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_IDLE_CNT1_IDLE_CNT_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_IDLE_CNT1_OFFSET ( 0x000000C8 )
+
+#define RUNNER_REGS_0_CFG_MAIN_IDLE_CNT1_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_IDLE_CNT1_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_IDLE_CNT1_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_IDLE_CNT1_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_IDLE_CNT1_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_IDLE_CNT1_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_IDLE_CNT1_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_IDLE_CNT1_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_IDLE_CNT1_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_IDLE_CNT1_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_IDLE_CNT1_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_IDLE_CNT1_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_IDLE_CNT1_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_IDLE_CNT1_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_IDLE_CNT1_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_IDLE_CNT1_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_IDLE_CNT1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IDLE */
+	uint32_t idle_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_IDLE_CNT1 ;
+#else
+typedef struct
+{	uint32_t idle_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IDLE */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_IDLE_CNT1 ;
+#endif
+
+/*****************************************************************************************/
+/* Version                                                                               */
+/* Version register                                                                      */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_VERSION_ADDR_VERSION_VERSION_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_VERSION_ADDR_VERSION_VERSION_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_VERSION_ADDR_OFFSET ( 0x000000E0 )
+
+#define RUNNER_REGS_0_CFG_VERSION_ADDR_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_VERSION_ADDR_OFFSET )
+#define RUNNER_REGS_0_CFG_VERSION_ADDR_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_VERSION_ADDR_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_VERSION_ADDR_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_VERSION_ADDR_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_VERSION_ADDR_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_VERSION_ADDR_OFFSET )
+#define RUNNER_REGS_1_CFG_VERSION_ADDR_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_VERSION_ADDR_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_VERSION_ADDR_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_VERSION_ADDR_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_VERSION_ADDR_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_VERSION_ADDR_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_VERSION_ADDR_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_VERSION_ADDR_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_VERSION_ADDR_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Version */
+	uint32_t version	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_VERSION_ADDR ;
+#else
+typedef struct
+{	uint32_t version	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Version */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_VERSION_ADDR ;
+#endif
+
+/*****************************************************************************************/
+/* Ramrd_mask_config                                                                     */
+/* Ramrd mask for range search. The register holds 2 mask that can be chosen by runner c */
+/* ore for range seraches.                                                               */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK1_MASK_VALUE_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK1_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK0_MASK_VALUE_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK0_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_OFFSET ( 0x000000EC )
+
+#define RUNNER_REGS_0_CFG_RAMRD_RANGE_MASK_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_RAMRD_RANGE_MASK_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_RAMRD_RANGE_MASK_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_RAMRD_RANGE_MASK_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_RAMRD_RANGE_MASK_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_RAMRD_RANGE_MASK_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_RAMRD_RANGE_MASK_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_RAMRD_RANGE_MASK_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_RAMRD_RANGE_MASK_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_RAMRD_RANGE_MASK_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* MASK1 */
+	uint32_t mask1	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK0 */
+	uint32_t mask0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG ;
+#else
+typedef struct
+{	uint32_t mask0	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK0 */
+	uint32_t mask1	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MASK1 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Metal_fix                                                                             */
+/* 32 bit register for metal fixes.                                                      */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_METAL_FIX_REG_METAL_FIX_METAL_FIX_REG_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_METAL_FIX_REG_METAL_FIX_METAL_FIX_REG_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_METAL_FIX_REG_OFFSET ( 0x000000F0 )
+
+#define RUNNER_REGS_0_CFG_METAL_FIX_REG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_METAL_FIX_REG_OFFSET )
+#define RUNNER_REGS_0_CFG_METAL_FIX_REG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_METAL_FIX_REG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_METAL_FIX_REG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_METAL_FIX_REG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_METAL_FIX_REG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_METAL_FIX_REG_OFFSET )
+#define RUNNER_REGS_1_CFG_METAL_FIX_REG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_METAL_FIX_REG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_METAL_FIX_REG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_METAL_FIX_REG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_METAL_FIX_REG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_METAL_FIX_REG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_METAL_FIX_REG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_METAL_FIX_REG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_METAL_FIX_REG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Metal_fix */
+	uint32_t metal_fix	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_METAL_FIX_REG ;
+#else
+typedef struct
+{	uint32_t metal_fix	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Metal_fix */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_METAL_FIX_REG ;
+#endif
+
+/*****************************************************************************************/
+/* Timer_target                                                                          */
+/* Controls which timer is associated with which core                                    */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_TIMER_TARGET_RESERVED_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_RESERVED_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_0_2_MAIN_CORE_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_0_2_MAIN_CORE_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_0_2_PICO_CORE_VALUE             ( 0x1 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_1_3_MAIN_CORE_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_1_3_MAIN_CORE_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_1_3_PICO_CORE_VALUE             ( 0x1 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_4_6_MAIN_CORE_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_4_6_MAIN_CORE_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_4_6_PICO_CORE_VALUE             ( 0x1 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_5_7_MAIN_CORE_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_5_7_MAIN_CORE_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_TIMER_TARGET_TIMER_5_7_PICO_CORE_VALUE             ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_TIMER_TARGET_OFFSET ( 0x000000F4 )
+
+#define RUNNER_REGS_0_CFG_TIMER_TARGET_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_TIMER_TARGET_OFFSET )
+#define RUNNER_REGS_0_CFG_TIMER_TARGET_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_TIMER_TARGET_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_TIMER_TARGET_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_TIMER_TARGET_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_TIMER_TARGET_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_TIMER_TARGET_OFFSET )
+#define RUNNER_REGS_1_CFG_TIMER_TARGET_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_TIMER_TARGET_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_TIMER_TARGET_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_TIMER_TARGET_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_TIMER_TARGET_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_TIMER_TARGET_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_TIMER_TARGET_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_TIMER_TARGET_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_TIMER_TARGET_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved 	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Timer_0_2 */
+	uint32_t timer_0_2	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Timer_1_3 */
+	uint32_t timer_1_3	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Timer_4_6 */
+	uint32_t timer_4_6	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Timer_5_7 */
+	uint32_t timer_5_7	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_TIMER_TARGET ;
+#else
+typedef struct
+{	uint32_t timer_5_7	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Timer_5_7 */
+	uint32_t timer_4_6	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Timer_4_6 */
+	uint32_t timer_1_3	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Timer_1_3 */
+	uint32_t timer_0_2	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Timer_0_2 */
+	uint32_t reserved 	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_TIMER_TARGET ;
+#endif
+
+/*****************************************************************************************/
+/* Scheduler_main_config                                                                 */
+/* Main scheduler configuration                                                          */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_RESERVED_DEFAULT_VALUE                         ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_RESERVED_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_ARB_CLASS_USE_STRICT_VALUE                     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_ARB_CLASS_USE_STRICT_VALUE_RESET_VALUE         ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_ARB_CLASS_USE_RR_VALUE                         ( 0x1 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_USE_CLASS_B_DONT_USE_CLASS_B_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_USE_CLASS_B_DONT_USE_CLASS_B_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_USE_CLASS_B_USE_CLASS_B_VALUE                  ( 0x1 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_USE_CLASS_A_DONT_USE_CLASS_A_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_USE_CLASS_A_DONT_USE_CLASS_A_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_USE_CLASS_A_USE_CLASS_A_VALUE                  ( 0x1 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_31_24_STRICT_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_31_24_STRICT_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_31_24_RR_VALUE                           ( 0x1 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_23_16_STRICT_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_23_16_STRICT_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_23_16_RR_VALUE                           ( 0x1 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_15_8_STIRCT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_15_8_STIRCT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_15_8_RR_VALUE                            ( 0x1 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_7_0_STRICT_VALUE                         ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_7_0_STRICT_VALUE_RESET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_CLASS_7_0_RR_VALUE                             ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_OFFSET ( 0x000000F8 )
+
+#define RUNNER_REGS_0_CFG_MAIN_SCH_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_SCH_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_SCH_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_SCH_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_SCH_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_SCH_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_SCH_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_SCH_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_SCH_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_SCH_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_SCH_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_SCH_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_SCH_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_SCH_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_SCH_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_SCH_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserver */
+	uint32_t reserved   	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* New_class_arb */
+	uint32_t arb_class  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Use_class_b */
+	uint32_t use_class_b	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Use_class_a */
+	uint32_t use_class_a	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_31_24 */
+	uint32_t class_31_24	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_23_16 */
+	uint32_t class_23_16	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_15_8 */
+	uint32_t class_15_8 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_7_0 */
+	uint32_t class_7_0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_SCH_CFG ;
+#else
+typedef struct
+{	uint32_t class_7_0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_7_0 */
+	uint32_t class_15_8 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_15_8 */
+	uint32_t class_23_16	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_23_16 */
+	uint32_t class_31_24	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_31_24 */
+	uint32_t use_class_a	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Use_class_a */
+	uint32_t use_class_b	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Use_class_b */
+	uint32_t arb_class  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* New_class_arb */
+	uint32_t reserved   	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserver */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_SCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Scheduler_pico_config                                                                 */
+/* Pico scheduler configuration                                                          */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_RESERVED_DEFAULT_VALUE                         ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_RESERVED_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_ARB_CLASS_USE_STRICT_VALUE                     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_ARB_CLASS_USE_STRICT_VALUE_RESET_VALUE         ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_ARB_CLASS_USE_RR_VALUE                         ( 0x1 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_USE_CLASS_B_DONT_USE_CLASS_B_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_USE_CLASS_B_DONT_USE_CLASS_B_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_USE_CLASS_B_USE_CLASS_B_VALUE                  ( 0x1 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_USE_CLASS_A_DONT_USE_CLASS_A_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_USE_CLASS_A_DONT_USE_CLASS_A_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_USE_CLASS_A_USE_CLASS_A_VALUE                  ( 0x1 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_R1_RESERVE_VALUE                               ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_R1_RESERVE_VALUE_RESET_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_R0_RESERVE_VALUE                               ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_R0_RESERVE_VALUE_RESET_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_CLASS_15_8_STIRCT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_CLASS_15_8_STIRCT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_CLASS_15_8_RR_VALUE                            ( 0x1 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_CLASS_7_0_STRICT_VALUE                         ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_CLASS_7_0_STRICT_VALUE_RESET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_CLASS_7_0_RR_VALUE                             ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_OFFSET ( 0x000000FC )
+
+#define RUNNER_REGS_0_CFG_PICO_SCH_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_SCH_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_SCH_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_SCH_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_SCH_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_SCH_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_SCH_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_SCH_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_SCH_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_SCH_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_SCH_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_SCH_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_SCH_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_SCH_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_SCH_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_SCH_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserver */
+	uint32_t reserved   	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* New_class_arb */
+	uint32_t arb_class  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Use_class_b */
+	uint32_t use_class_b	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Use_class_a */
+	uint32_t use_class_a	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* R1 */
+	uint32_t r1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* R0 */
+	uint32_t r0         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_15_8 */
+	uint32_t class_15_8 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_7_0 */
+	uint32_t class_7_0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_SCH_CFG ;
+#else
+typedef struct
+{	uint32_t class_7_0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_7_0 */
+	uint32_t class_15_8 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* class_15_8 */
+	uint32_t r0         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* R0 */
+	uint32_t r1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* R1 */
+	uint32_t use_class_a	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Use_class_a */
+	uint32_t use_class_b	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Use_class_b */
+	uint32_t arb_class  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* New_class_arb */
+	uint32_t reserved   	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserver */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_SCH_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Main_bkpt_0                                                                           */
+/* main break point                                                                      */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_RSV_DEFAULT_VALUE                    ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_RSV_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_USE_THREAD_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_USE_THREAD_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_ENABLE_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_ENABLE_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_THREAD_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_THREAD_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_ADDR_DEFAULT_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_ADDR_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_OFFSET ( 0x00000110 )
+
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_0_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_0_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_0_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_0_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_0_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_0_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_0_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_0_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_0_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_0_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_0_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_0_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_BKPT_0_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_BKPT_0_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_BKPT_0_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_BKPT_0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_0 ;
+#else
+typedef struct
+{	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_0 ;
+#endif
+
+/*****************************************************************************************/
+/* Main_bkpt_1                                                                           */
+/* main break point 1                                                                    */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_RSV_DEFAULT_VALUE                    ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_RSV_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_USE_THREAD_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_USE_THREAD_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_ENABLE_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_ENABLE_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_THREAD_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_THREAD_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_ADDR_DEFAULT_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_ADDR_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_OFFSET ( 0x00000114 )
+
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_1_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_1_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_1_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_1_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_1_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_1_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_1_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_1_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_1_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_1_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_1_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_1_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_BKPT_1_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_BKPT_1_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_BKPT_1_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_BKPT_1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_1 ;
+#else
+typedef struct
+{	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_1 ;
+#endif
+
+/*****************************************************************************************/
+/* Main_bkpt_2                                                                           */
+/* main break point 2                                                                    */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_RSV_DEFAULT_VALUE                    ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_RSV_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_USE_THREAD_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_USE_THREAD_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_ENABLE_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_ENABLE_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_THREAD_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_THREAD_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_ADDR_DEFAULT_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_ADDR_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_OFFSET ( 0x00000118 )
+
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_2_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_2_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_2_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_2_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_2_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_2_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_2_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_2_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_2_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_2_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_2_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_2_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_BKPT_2_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_BKPT_2_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_BKPT_2_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_BKPT_2_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_2 ;
+#else
+typedef struct
+{	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_2 ;
+#endif
+
+/*****************************************************************************************/
+/* Main_bkpt_3                                                                           */
+/* main break point 3                                                                    */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_RSV_DEFAULT_VALUE                    ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_RSV_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_USE_THREAD_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_USE_THREAD_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_ENABLE_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_ENABLE_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_THREAD_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_THREAD_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_ADDR_DEFAULT_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_ADDR_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_OFFSET ( 0x0000011C )
+
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_3_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_3_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_3_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_3_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_3_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_3_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_3_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_3_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_3_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_3_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_3_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_3_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_BKPT_3_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_BKPT_3_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_BKPT_3_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_BKPT_3_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_3 ;
+#else
+typedef struct
+{	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_3 ;
+#endif
+
+/*****************************************************************************************/
+/* Main_bkpt_immediate                                                                   */
+/* main break point immediate                                                            */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_IMM_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_IMM_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_IMM_ENABLE_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_IMM_ENABLE_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_IMM_OFFSET ( 0x00000120 )
+
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_IMM_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_IMM_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_IMM_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_IMM_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_IMM_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_IMM_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_IMM_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_IMM_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_IMM_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_IMM_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_IMM_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_IMM_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_BKPT_IMM_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_IMM_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_BKPT_IMM_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_BKPT_IMM_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_BKPT_IMM_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved2 */
+	uint32_t reserved	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE_IMM */
+	uint32_t enable  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_IMM ;
+#else
+typedef struct
+{	uint32_t enable  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE_IMM */
+	uint32_t reserved	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved2 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_IMM ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_bkpt_0                                                                           */
+/* pico break point 0                                                                    */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_BKPT_0_RSV_DEFAULT_VALUE                    ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_0_RSV_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_0_USE_THREAD_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_0_USE_THREAD_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_0_ENABLE_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_0_ENABLE_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_0_THREAD_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_0_THREAD_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_0_ADDR_DEFAULT_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_0_ADDR_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_BKPT_0_OFFSET ( 0x00000124 )
+
+#define RUNNER_REGS_0_CFG_PICO_BKPT_0_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_0_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_0_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_0_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_0_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_0_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_BKPT_0_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_0_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_0_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_0_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_0_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_0_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_BKPT_0_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_BKPT_0_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_BKPT_0_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_BKPT_0_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_BKPT_0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_0 ;
+#else
+typedef struct
+{	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_0 ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_bkpt_1                                                                           */
+/* pico break point 1                                                                    */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_BKPT_1_RSV_DEFAULT_VALUE                    ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_1_RSV_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_1_USE_THREAD_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_1_USE_THREAD_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_1_ENABLE_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_1_ENABLE_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_1_THREAD_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_1_THREAD_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_1_ADDR_DEFAULT_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_1_ADDR_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_BKPT_1_OFFSET ( 0x00000128 )
+
+#define RUNNER_REGS_0_CFG_PICO_BKPT_1_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_1_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_1_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_1_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_1_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_1_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_BKPT_1_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_1_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_1_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_1_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_1_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_1_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_BKPT_1_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_BKPT_1_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_BKPT_1_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_BKPT_1_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_BKPT_1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_1 ;
+#else
+typedef struct
+{	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_1 ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_bkpt_2                                                                           */
+/* pico break point 2                                                                    */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_BKPT_2_RSV_DEFAULT_VALUE                    ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_2_RSV_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_2_USE_THREAD_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_2_USE_THREAD_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_2_ENABLE_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_2_ENABLE_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_2_THREAD_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_2_THREAD_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_2_ADDR_DEFAULT_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_2_ADDR_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_BKPT_2_OFFSET ( 0x0000012C )
+
+#define RUNNER_REGS_0_CFG_PICO_BKPT_2_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_2_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_2_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_2_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_2_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_2_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_BKPT_2_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_2_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_2_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_2_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_2_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_2_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_BKPT_2_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_BKPT_2_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_BKPT_2_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_BKPT_2_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_BKPT_2_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_2 ;
+#else
+typedef struct
+{	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_2 ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_bkpt_3                                                                           */
+/* pico break point 3                                                                    */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_BKPT_3_RSV_DEFAULT_VALUE                    ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_3_RSV_DEFAULT_VALUE_RESET_VALUE        ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_3_USE_THREAD_DEFAULT_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_3_USE_THREAD_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_3_ENABLE_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_3_ENABLE_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_3_THREAD_DEFAULT_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_3_THREAD_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_3_ADDR_DEFAULT_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_3_ADDR_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_BKPT_3_OFFSET ( 0x00000130 )
+
+#define RUNNER_REGS_0_CFG_PICO_BKPT_3_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_3_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_3_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_3_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_3_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_3_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_BKPT_3_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_3_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_3_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_3_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_3_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_3_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_BKPT_3_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_BKPT_3_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_BKPT_3_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_BKPT_3_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_BKPT_3_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_3 ;
+#else
+typedef struct
+{	uint32_t addr      	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ADDR */
+	uint32_t thread    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* THREAD */
+	uint32_t enable    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE */
+	uint32_t use_thread	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USE_THREAD */
+	uint32_t rsv       	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_3 ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_bkpt_immediate                                                                   */
+/* pico break point immediate                                                            */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_BKPT_IMM_RESERVED_RESERVED_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_IMM_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_IMM_ENABLE_RESERVED_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_IMM_ENABLE_RESERVED_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_BKPT_IMM_OFFSET ( 0x00000134 )
+
+#define RUNNER_REGS_0_CFG_PICO_BKPT_IMM_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_IMM_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_IMM_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_IMM_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_IMM_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_IMM_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_BKPT_IMM_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_IMM_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_IMM_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_IMM_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_IMM_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_IMM_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_BKPT_IMM_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_BKPT_IMM_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_BKPT_IMM_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_BKPT_IMM_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_BKPT_IMM_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved2 */
+	uint32_t reserved	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE_IMM */
+	uint32_t enable  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_IMM ;
+#else
+typedef struct
+{	uint32_t enable  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ENABLE_IMM */
+	uint32_t reserved	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved2 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_IMM ;
+#endif
+
+/*****************************************************************************************/
+/* cfg_1588                                                                              */
+/* 1588 configuration (Master and Slave)                                                 */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_CFG_1588_RSV1_RESERVED0_VALUE                           ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_RSV1_RESERVED0_VALUE_RESET_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_SLV_1588_WKUP_DIS_ENABLE_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_SLV_1588_WKUP_DIS_DISABLE_VALUE                ( 0x1 )
+#define RUNNER_REGS_CFG_CFG_1588_SLV_1588_WKUP_DIS_DISABLE_VALUE_RESET_VALUE    ( 0x1 )
+#define RUNNER_REGS_CFG_CFG_1588_SLV_1588_CORE_SEL_MAIN_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_SLV_1588_CORE_SEL_MAIN_VALUE_RESET_VALUE       ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_SLV_1588_CORE_SEL_PICO_VALUE                   ( 0x1 )
+#define RUNNER_REGS_CFG_CFG_1588_SLV_1588_THRD_NUM_RESERVED0_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_SLV_1588_THRD_NUM_RESERVED0_VALUE_RESET_VALUE  ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_RSV0_RESERVED0_VALUE                           ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_RSV0_RESERVED0_VALUE_RESET_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_MSTR_1588_WKUP_DIS_ENABLE_VALUE                ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_MSTR_1588_WKUP_DIS_DISABLE_VALUE               ( 0x1 )
+#define RUNNER_REGS_CFG_CFG_1588_MSTR_1588_WKUP_DIS_DISABLE_VALUE_RESET_VALUE   ( 0x1 )
+#define RUNNER_REGS_CFG_CFG_1588_MSTR_1588_CORE_SEL_MAIN_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_MSTR_1588_CORE_SEL_MAIN_VALUE_RESET_VALUE      ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_MSTR_1588_CORE_SEL_PICO_VALUE                  ( 0x1 )
+#define RUNNER_REGS_CFG_CFG_1588_MSTR_1588_THRD_NUM_RESERVED0_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_1588_MSTR_1588_THRD_NUM_RESERVED0_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_CFG_1588_OFFSET ( 0x00000138 )
+
+#define RUNNER_REGS_0_CFG_CFG_1588_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_CFG_1588_OFFSET )
+#define RUNNER_REGS_0_CFG_CFG_1588_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_CFG_1588_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_CFG_1588_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_CFG_1588_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_CFG_1588_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_CFG_1588_OFFSET )
+#define RUNNER_REGS_1_CFG_CFG_1588_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_CFG_1588_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_CFG_1588_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_CFG_1588_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_CFG_1588_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_CFG_1588_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_CFG_1588_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_CFG_1588_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_CFG_1588_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV1 */
+	uint32_t rsv1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SLV_1588_WKUP_DIS */
+	uint32_t slv_1588_wkup_dis 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SLV_1588_CORE_SEL */
+	uint32_t slv_1588_core_sel 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SLV_1588_THRD_NUM */
+	uint32_t slv_1588_thrd_num 	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV0 */
+	uint32_t rsv0              	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MSTR_1588_WKUP_DIS */
+	uint32_t mstr_1588_wkup_dis	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MSTR_1588_CORE_SEL */
+	uint32_t mstr_1588_core_sel	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MSTR_1588_THRD_NUM */
+	uint32_t mstr_1588_thrd_num	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_CFG_1588 ;
+#else
+typedef struct
+{	uint32_t mstr_1588_thrd_num	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MSTR_1588_THRD_NUM */
+	uint32_t mstr_1588_core_sel	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MSTR_1588_CORE_SEL */
+	uint32_t mstr_1588_wkup_dis	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MSTR_1588_WKUP_DIS */
+	uint32_t rsv0              	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV0 */
+	uint32_t slv_1588_thrd_num 	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SLV_1588_THRD_NUM */
+	uint32_t slv_1588_core_sel 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SLV_1588_CORE_SEL */
+	uint32_t slv_1588_wkup_dis 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SLV_1588_WKUP_DIS */
+	uint32_t rsv1              	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_CFG_1588 ;
+#endif
+
+/*****************************************************************************************/
+/* cfg_8k                                                                                */
+/* 8K configuration                                                                      */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_CFG_8K_RSV_RESERVED0_VALUE                          ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_8K_RSV_RESERVED0_VALUE_RESET_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_8K_GPON_8K_CORE_SEL_MAIN_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_8K_GPON_8K_CORE_SEL_MAIN_VALUE_RESET_VALUE      ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_8K_GPON_8K_CORE_SEL_PICO_VALUE                  ( 0x1 )
+#define RUNNER_REGS_CFG_CFG_8K_GPON_8K_WKUP_DIS_ENABLE_VALUE                ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_8K_GPON_8K_WKUP_DIS_DISABLE_VALUE               ( 0x1 )
+#define RUNNER_REGS_CFG_CFG_8K_GPON_8K_WKUP_DIS_DISABLE_VALUE_RESET_VALUE   ( 0x1 )
+#define RUNNER_REGS_CFG_CFG_8K_GPON_8K_THRD_NUM_RESERVED0_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_CFG_8K_GPON_8K_THRD_NUM_RESERVED0_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_CFG_8K_OFFSET ( 0x0000013C )
+
+#define RUNNER_REGS_0_CFG_CFG_8K_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_CFG_8K_OFFSET )
+#define RUNNER_REGS_0_CFG_CFG_8K_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_CFG_8K_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_CFG_8K_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_CFG_8K_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_CFG_8K_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_CFG_8K_OFFSET )
+#define RUNNER_REGS_1_CFG_CFG_8K_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_CFG_8K_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_CFG_8K_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_CFG_8K_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_CFG_8K_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_CFG_8K_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_CFG_8K_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_CFG_8K_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_CFG_8K_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv             	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_8K_CORE_SEL */
+	uint32_t gpon_8k_core_sel	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_8K_WKUP_DIS */
+	uint32_t gpon_8k_wkup_dis	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_8K_THRD_NUM */
+	uint32_t gpon_8k_thrd_num	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_CFG_8K ;
+#else
+typedef struct
+{	uint32_t gpon_8k_thrd_num	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_8K_THRD_NUM */
+	uint32_t gpon_8k_wkup_dis	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_8K_WKUP_DIS */
+	uint32_t gpon_8k_core_sel	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_8K_CORE_SEL */
+	uint32_t rsv             	: 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_CFG_8K ;
+#endif
+
+/*****************************************************************************************/
+/* Semaphore_Status_and_Control                                                          */
+/* This register is used for taking and releasing the Semaphores 0-3                     */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RESERVED3_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RESERVED3_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RELEASE3_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RELEASE3_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS3_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS3_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS3_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RESERVED2_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RESERVED2_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RELEASE2_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RELEASE2_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS2_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS2_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS2_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RESERVED1_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RESERVED1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RELEASE1_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RELEASE1_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS1_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS1_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS1_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RESERVED0_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RESERVED0_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RELEASE0_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_RELEASE0_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS0_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS0_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_STATUS0_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_OFFSET ( 0x00000140 )
+
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_0_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_OFFSET )
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_0_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_0_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_0_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_0_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_0_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_OFFSET )
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_0_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_0_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_0_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_0_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_3_Release_Request */
+	uint32_t release3 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_3_Status */
+	uint32_t status3  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_2_Release_Request */
+	uint32_t release2 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_2_Status */
+	uint32_t status2  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_1_Release_Request */
+	uint32_t release1 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_1_Status */
+	uint32_t status1  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_0_Release_Request */
+	uint32_t release0 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_0_Status */
+	uint32_t status0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0 ;
+#else
+typedef struct
+{	uint32_t status0  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_0_Status */
+	uint32_t release0 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_0_Release_Request */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status1  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_1_Status */
+	uint32_t release1 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_1_Release_Request */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status2  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_2_Status */
+	uint32_t release2 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_2_Release_Request */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status3  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_3_Status */
+	uint32_t release3 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_3_Release_Request */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0 ;
+#endif
+
+/*****************************************************************************************/
+/* Semaphore_Status_and_Control                                                          */
+/* This register is used for taking and releasing the Semaphores 4-7                     */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RESERVED3_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RESERVED3_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RELEASE7_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RELEASE7_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS7_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS7_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS7_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RESERVED2_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RESERVED2_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RELEASE6_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RELEASE6_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS6_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS6_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS6_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RESERVED1_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RESERVED1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RELEASE5_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RELEASE5_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS5_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS5_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS5_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RESERVED0_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RESERVED0_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RELEASE4_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_RELEASE4_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS4_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS4_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_STATUS4_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_OFFSET ( 0x00000144 )
+
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_1_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_OFFSET )
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_1_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_1_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_1_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_1_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_1_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_OFFSET )
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_1_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_1_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_1_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_1_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7Release_Request */
+	uint32_t release7 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7_Status */
+	uint32_t status7  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Release_Request */
+	uint32_t release6 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Status */
+	uint32_t status6  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Release_Request */
+	uint32_t release5 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Status */
+	uint32_t status5  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Release_Request */
+	uint32_t release4 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Status */
+	uint32_t status4  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1 ;
+#else
+typedef struct
+{	uint32_t status4  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Status */
+	uint32_t release4 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Release_Request */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status5  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Status */
+	uint32_t release5 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Release_Request */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status6  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Status */
+	uint32_t release6 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Release_Request */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status7  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7_Status */
+	uint32_t release7 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7Release_Request */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1 ;
+#endif
+
+/*****************************************************************************************/
+/* Semaphore_Status_and_Control                                                          */
+/* This register is used for taking and releasing the Semaphores 8-11                    */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RESERVED3_RESERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RESERVED3_RESERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RELEASE11_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RELEASE11_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS11_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS11_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS11_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RESERVED2_RESERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RESERVED2_RESERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RELEASE10_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RELEASE10_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS10_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS10_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS10_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RESERVED1_RESERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RESERVED1_RESERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RELEASE9_DEFAULT_VALUE                         ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RELEASE9_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS9_OWNERSHIP_NOT_TAKEN_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS9_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE  ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS9_OWNERSHIP_TAKEN_VALUE                  ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RESERVED0_RESERVED_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RESERVED0_RESERVED_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RELEASE8_DEFAULT_VALUE                         ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_RELEASE8_DEFAULT_VALUE_RESET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS8_OWNERSHIP_NOT_TAKEN_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS8_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE  ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_STATUS8_OWNERSHIP_TAKEN_VALUE                  ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_OFFSET ( 0x00000148 )
+
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_2_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_OFFSET )
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_2_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_2_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_2_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_2_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_2_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_OFFSET )
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_2_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_2_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_2_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_2_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_11_Release_Request */
+	uint32_t release11	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_11_Status */
+	uint32_t status11 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_10_Release_Request */
+	uint32_t release10	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_10_Status */
+	uint32_t status10 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_9_Release_Request */
+	uint32_t release9 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_9_Status */
+	uint32_t status9  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_8_Release_Request */
+	uint32_t release8 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_8_Status */
+	uint32_t status8  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2 ;
+#else
+typedef struct
+{	uint32_t status8  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_8_Status */
+	uint32_t release8 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_8_Release_Request */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status9  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_9_Status */
+	uint32_t release9 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_9_Release_Request */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status10 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_10_Status */
+	uint32_t release10	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_10_Release_Request */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status11 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_11_Status */
+	uint32_t release11	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_11_Release_Request */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2 ;
+#endif
+
+/*****************************************************************************************/
+/* Semaphore_Status_and_Control                                                          */
+/* This register is used for taking and releasing the Semaphores 12-15                   */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RESERVED3_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RESERVED3_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RELEASE7_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RELEASE7_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS7_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS7_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS7_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RESERVED2_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RESERVED2_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RELEASE6_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RELEASE6_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS6_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS6_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS6_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RESERVED1_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RESERVED1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RELEASE5_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RELEASE5_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS5_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS5_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS5_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RESERVED0_RESERVED_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RESERVED0_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RELEASE4_DEFAULT_VALUE                        ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_RELEASE4_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS4_OWNERSHIP_NOT_TAKEN_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS4_OWNERSHIP_NOT_TAKEN_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_STATUS4_OWNERSHIP_TAKEN_VALUE                 ( 0x1 )
+
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_OFFSET ( 0x0000014C )
+
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_3_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_OFFSET )
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_3_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_3_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_3_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MIPSD_SEMAPHOR_STS_3_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_3_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_OFFSET )
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_3_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_3_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_3_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MIPSD_SEMAPHOR_STS_3_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Reserved */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7Release_Request */
+	uint32_t release7 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7_Status */
+	uint32_t status7  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Release_Request */
+	uint32_t release6 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Status */
+	uint32_t status6  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Release_Request */
+	uint32_t release5 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Status */
+	uint32_t status5  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Release_Request */
+	uint32_t release4 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Status */
+	uint32_t status4  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3 ;
+#else
+typedef struct
+{	uint32_t status4  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Status */
+	uint32_t release4 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_4_Release_Request */
+	uint32_t reserved0	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status5  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Status */
+	uint32_t release5 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_5_Release_Request */
+	uint32_t reserved1	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status6  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Status */
+	uint32_t release6 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_6_Release_Request */
+	uint32_t reserved2	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint32_t status7  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7_Status */
+	uint32_t release7 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_7Release_Request */
+	uint32_t reserved3	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3 ;
+#endif
+
+/*****************************************************************************************/
+/* Main_jump_cnt                                                                         */
+/* Mispredicted jumps count                                                              */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_JMP_CNT_TAKEN_JMP_CNT_RESERVED0_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_JMP_CNT_TAKEN_JMP_CNT_RESERVED0_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_JMP_CNT_UNTAKEN_JMP_CNT_RESERVED0_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_JMP_CNT_UNTAKEN_JMP_CNT_RESERVED0_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_JMP_CNT_OFFSET ( 0x00000150 )
+
+#define RUNNER_REGS_0_CFG_MAIN_JMP_CNT_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_JMP_CNT_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_JMP_CNT_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_JMP_CNT_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_JMP_CNT_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_JMP_CNT_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_JMP_CNT_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_JMP_CNT_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_JMP_CNT_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_JMP_CNT_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_JMP_CNT_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_JMP_CNT_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_JMP_CNT_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_JMP_CNT_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_JMP_CNT_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_JMP_CNT_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_JMP_CNT_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* UNTAKEN_JMP_CNT */
+	uint32_t untaken_jmp_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+	
+	/* TAKEN_JMP_CNT */
+	uint32_t taken_jmp_cnt  	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;	
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_JMP_CNT ;
+#else
+typedef struct
+{	
+	/* TAKEN_JMP_CNT */
+	uint32_t taken_jmp_cnt  	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UNTAKEN_JMP_CNT */
+	uint32_t untaken_jmp_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_JMP_CNT ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_jump_cnt                                                                         */
+/* Mispredicted jumps count                                                              */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_JMP_CNT_TAKEN_JMP_CNT_RESERVED0_VALUE               ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_JMP_CNT_TAKEN_JMP_CNT_RESERVED0_VALUE_RESET_VALUE   ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_JMP_CNT_UNTAKEN_JMP_CNT_RESERVED0_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_JMP_CNT_UNTAKEN_JMP_CNT_RESERVED0_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_JMP_CNT_OFFSET ( 0x00000154 )
+
+#define RUNNER_REGS_0_CFG_PICO_JMP_CNT_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_JMP_CNT_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_JMP_CNT_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_JMP_CNT_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_JMP_CNT_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_JMP_CNT_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_JMP_CNT_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_JMP_CNT_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_JMP_CNT_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_JMP_CNT_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_JMP_CNT_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_JMP_CNT_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_JMP_CNT_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_JMP_CNT_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_JMP_CNT_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_JMP_CNT_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_JMP_CNT_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* TAKEN_JMP_CNT */
+	uint32_t taken_jmp_cnt  	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UNTAKEN_JMP_CNT */
+	uint32_t untaken_jmp_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_JMP_CNT ;
+#else
+typedef struct
+{	uint32_t untaken_jmp_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UNTAKEN_JMP_CNT */
+	uint32_t taken_jmp_cnt  	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TAKEN_JMP_CNT */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_JMP_CNT ;
+#endif
+
+/*****************************************************************************************/
+/* MAIN_BKPT_CFG                                                                         */
+/* Main breakpoint configuration                                                         */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_RSV_RESERVED0_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_RSV_RESERVED0_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_STEP_MODE_RESERVED0_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_STEP_MODE_RESERVED0_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_NEW_FLAGS_VAL_RESERVED0_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_NEW_FLAGS_VAL_RESERVED0_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_NEW_PC_VAL_RESERVED0_VALUE                ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_NEW_PC_VAL_RESERVED0_VALUE_RESET_VALUE    ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_HANDLER_ADDR_RESERVED0_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_HANDLER_ADDR_RESERVED0_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_OFFSET ( 0x00000158 )
+
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_BKPT_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_BKPT_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_BKPT_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_BKPT_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* STEP_MODE */
+	uint32_t step_mode    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* NEW_FLAGS_VAL */
+	uint32_t new_flags_val	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* NEW_PC_VAL */
+	uint32_t new_pc_val   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HANDLER_ADDR */
+	uint32_t handler_addr 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_CFG ;
+#else
+typedef struct
+{	uint32_t handler_addr 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HANDLER_ADDR */
+	uint32_t new_pc_val   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* NEW_PC_VAL */
+	uint32_t new_flags_val	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* NEW_FLAGS_VAL */
+	uint32_t step_mode    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* STEP_MODE */
+	uint32_t rsv          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* PICO_BKPT_CFG                                                                         */
+/* Pico breakpoint configuration                                                         */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_RSV_RESERVED0_VALUE                       ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_RSV_RESERVED0_VALUE_RESET_VALUE           ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_STEP_MODE_RESERVED0_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_STEP_MODE_RESERVED0_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_NEW_FLAGS_VAL_RESERVED0_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_NEW_FLAGS_VAL_RESERVED0_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_NEW_PC_VAL_RESERVED0_VALUE                ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_NEW_PC_VAL_RESERVED0_VALUE_RESET_VALUE    ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_HANDLER_ADDR_RESERVED0_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_HANDLER_ADDR_RESERVED0_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_OFFSET ( 0x0000015C )
+
+#define RUNNER_REGS_0_CFG_PICO_BKPT_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_BKPT_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_BKPT_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_BKPT_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_BKPT_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_BKPT_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* STEP_MODE */
+	uint32_t step_mode    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* NEW_FLAGS_VAL */
+	uint32_t new_flags_val	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* NEW_PC_VAL */
+	uint32_t new_pc_val   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HANDLER_ADDR */
+	uint32_t handler_addr 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_CFG ;
+#else
+typedef struct
+{	uint32_t handler_addr 	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HANDLER_ADDR */
+	uint32_t new_pc_val   	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* NEW_PC_VAL */
+	uint32_t new_flags_val	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* NEW_FLAGS_VAL */
+	uint32_t step_mode    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* STEP_MODE */
+	uint32_t rsv          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* MAIN_BKPT_STS                                                                         */
+/* Main breakpoint status                                                                */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_STS_RSV_RESERVED0_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_STS_RSV_RESERVED0_VALUE_RESET_VALUE       ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_STS_ACTIVE_RESERVED0_VALUE                ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_STS_ACTIVE_RESERVED0_VALUE_RESET_VALUE    ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_STS_RSV1_RESERVED0_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_STS_RSV1_RESERVED0_VALUE_RESET_VALUE      ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_STS_BKPT_ADDR_RESERVED0_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_MAIN_BKPT_STS_BKPT_ADDR_RESERVED0_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_STS_OFFSET ( 0x00000160 )
+
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_STS_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_STS_OFFSET )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_STS_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_STS_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_MAIN_BKPT_STS_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_MAIN_BKPT_STS_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_STS_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_MAIN_BKPT_STS_OFFSET )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_STS_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_STS_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_MAIN_BKPT_STS_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_MAIN_BKPT_STS_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_MAIN_BKPT_STS_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_MAIN_BKPT_STS_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_MAIN_BKPT_STS_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_MAIN_BKPT_STS_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_MAIN_BKPT_STS_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv      	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ACTIVE */
+	uint32_t active   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t rsv1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BKPT_ADDR */
+	uint32_t bkpt_addr	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_STS ;
+#else
+typedef struct
+{	uint32_t bkpt_addr	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BKPT_ADDR */
+	uint32_t rsv1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t active   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ACTIVE */
+	uint32_t rsv      	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_MAIN_BKPT_STS ;
+#endif
+
+/*****************************************************************************************/
+/* PICO_BKPT_STS                                                                         */
+/* Pico breakpoint status                                                                */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_BKPT_STS_RSV_RESERVED0_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_STS_RSV_RESERVED0_VALUE_RESET_VALUE       ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_STS_ACTIVE_RESERVED0_VALUE                ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_STS_ACTIVE_RESERVED0_VALUE_RESET_VALUE    ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_STS_RSV1_RESERVED0_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_STS_RSV1_RESERVED0_VALUE_RESET_VALUE      ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_STS_BKPT_ADDR_RESERVED0_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_BKPT_STS_BKPT_ADDR_RESERVED0_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_BKPT_STS_OFFSET ( 0x00000164 )
+
+#define RUNNER_REGS_0_CFG_PICO_BKPT_STS_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_STS_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_STS_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_STS_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_BKPT_STS_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_BKPT_STS_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_BKPT_STS_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_BKPT_STS_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_STS_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_STS_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_BKPT_STS_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_BKPT_STS_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_BKPT_STS_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_BKPT_STS_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_BKPT_STS_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_BKPT_STS_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_BKPT_STS_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV */
+	uint32_t rsv      	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ACTIVE */
+	uint32_t active   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t rsv1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BKPT_ADDR */
+	uint32_t bkpt_addr	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_STS ;
+#else
+typedef struct
+{	uint32_t bkpt_addr	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BKPT_ADDR */
+	uint32_t rsv1     	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t active   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ACTIVE */
+	uint32_t rsv      	: 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_BKPT_STS ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_profiling_sts                                                                    */
+/* Pico profiling status                                                                 */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_TRACE_WRITE_PNT_TRACE_WRITE_POINTER_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_TRACE_WRITE_PNT_TRACE_WRITE_POINTER_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_RESERVED2_RESERVED2_VALUE                                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_RESERVED2_RESERVED2_VALUE_RESET_VALUE                     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_PROFILING_ACTIVE_PROFILING_VALUE                          ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_PROFILING_ACTIVE_PROFILING_VALUE_RESET_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_IDLE_NO_ACTIVE_TASK_IDLE_NO_ACTIVE_TASK_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_IDLE_NO_ACTIVE_TASK_IDLE_NO_ACTIVE_TASK_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_CURR_THREAD_NUM_CURR_THREAD_VALUE                         ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_CURR_THREAD_NUM_CURR_THREAD_VALUE_RESET_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_RESERVED1_RESERVED_VALUE                                  ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_RESERVED1_RESERVED_VALUE_RESET_VALUE                      ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_AGU_NEXT_PC_DEFAULT_VALUE                                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_AGU_NEXT_PC_DEFAULT_VALUE_RESET_VALUE                     ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_OFFSET ( 0x000001B0 )
+
+#define RUNNER_REGS_0_CFG_PICO_PROFILING_STS_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_PROFILING_STS_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_PROFILING_STS_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_PROFILING_STS_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_PROFILING_STS_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_PROFILING_STS_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_PROFILING_STS_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_PROFILING_STS_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_PROFILING_STS_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_PROFILING_STS_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_PROFILING_STS_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_PROFILING_STS_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_PROFILING_STS_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_PROFILING_STS_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_PROFILING_STS_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_PROFILING_STS_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Trace_write_pointer */
+	uint32_t trace_write_pnt    	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved2 */
+	uint32_t reserved2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Profiling_active */
+	uint32_t profiling_active   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IDLE_no_active_task */
+	uint32_t idle_no_active_task	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CURR_thread_num */
+	uint32_t curr_thread_num    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved1 */
+	uint32_t reserved1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* AGU_next_pc */
+	uint32_t agu_next_pc        	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_PROFILING_STS ;
+#else
+typedef struct
+{	uint32_t agu_next_pc        	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* AGU_next_pc */
+	uint32_t reserved1          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved1 */
+	uint32_t curr_thread_num    	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CURR_thread_num */
+	uint32_t idle_no_active_task	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IDLE_no_active_task */
+	uint32_t profiling_active   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Profiling_active */
+	uint32_t reserved2          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved2 */
+	uint32_t trace_write_pnt    	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Trace_write_pointer */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_PROFILING_STS ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_profiling_cfg                                                                    */
+/* Pico profiling confuguration                                                          */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_RSV2_RSV_VALUE                             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_TRACE_BASE_ADDR_RESERVED_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_TRACE_BASE_ADDR_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_PROF_STOP_RESERVED_VALUE                   ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_PROF_STOP_RESERVED_VALUE_RESET_VALUE       ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_PROF_START_RESERVED_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_PROF_START_RESERVED_VALUE_RESET_VALUE      ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_RSV1_RSV_VALUE                             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_RSV1_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_TRACE_PC_EN_RESERVED_VALUE                 ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_TRACE_PC_EN_RESERVED_VALUE_RESET_VALUE     ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_PROF_TASK2_RESERVED_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_PROF_TASK2_RESERVED_VALUE_RESET_VALUE      ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_PROF_TASK1_RESERVED_VALUE                  ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_PROF_TASK1_RESERVED_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_OFFSET ( 0x000001B4 )
+
+#define RUNNER_REGS_0_CFG_PICO_PROFILING_CFG_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_PROFILING_CFG_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_PROFILING_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_PROFILING_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_PROFILING_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_PROFILING_CFG_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_PROFILING_CFG_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_PROFILING_CFG_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_PROFILING_CFG_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_PROFILING_CFG_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_PROFILING_CFG_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_PROFILING_CFG_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_PROFILING_CFG_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_PROFILING_CFG_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_PROFILING_CFG_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_PROFILING_CFG_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* RSV2 */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRACE_BASE_ADDR */
+	uint32_t trace_base_addr	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_STOP */
+	uint32_t prof_stop      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_START */
+	uint32_t prof_start     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t rsv1           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRACE_PC_EN */
+	uint32_t trace_pc_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_TASK2 */
+	uint32_t prof_task2     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_TASK1 */
+	uint32_t prof_task1     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_PROFILING_CFG ;
+#else
+typedef struct
+{	uint32_t prof_task1     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_TASK1 */
+	uint32_t prof_task2     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_TASK2 */
+	uint32_t trace_pc_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRACE_PC_EN */
+	uint32_t rsv1           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV1 */
+	uint32_t prof_start     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_START */
+	uint32_t prof_stop      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PROF_STOP */
+	uint32_t trace_base_addr	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TRACE_BASE_ADDR */
+	uint32_t rsv2           	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RSV2 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_PROFILING_CFG ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_stall_cnt1                                                                       */
+/* Pico stall count                                                                      */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_STALL_CNT1_ACC_STALL_CNT_RESERVED1_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_STALL_CNT1_ACC_STALL_CNT_RESERVED1_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_STALL_CNT1_LD_STALL_CNT_RESERVED1_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_STALL_CNT1_LD_STALL_CNT_RESERVED1_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_STALL_CNT1_OFFSET ( 0x000001B8 )
+
+#define RUNNER_REGS_0_CFG_PICO_STALL_CNT1_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_STALL_CNT1_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_STALL_CNT1_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_STALL_CNT1_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_STALL_CNT1_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_STALL_CNT1_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_STALL_CNT1_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_STALL_CNT1_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_STALL_CNT1_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_STALL_CNT1_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_STALL_CNT1_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_STALL_CNT1_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_STALL_CNT1_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_STALL_CNT1_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_STALL_CNT1_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_STALL_CNT1_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_STALL_CNT1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* ACC_STALL_CNT */
+	uint32_t acc_stall_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LD_STALL_CNT */
+	uint32_t ld_stall_cnt 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_STALL_CNT1 ;
+#else
+typedef struct
+{	uint32_t ld_stall_cnt 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LD_STALL_CNT */
+	uint32_t acc_stall_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ACC_STALL_CNT */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_STALL_CNT1 ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_stall_cnt2                                                                       */
+/* pico stall count                                                                      */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_STALL_CNT2_STORE_STALL_CNT_RESERVED0_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_STALL_CNT2_STORE_STALL_CNT_RESERVED0_VALUE_RESET_VALUE ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_STALL_CNT2_LDIO_STALL_CNT_RESERVED0_VALUE              ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_STALL_CNT2_LDIO_STALL_CNT_RESERVED0_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_STALL_CNT2_OFFSET ( 0x000001BC )
+
+#define RUNNER_REGS_0_CFG_PICO_STALL_CNT2_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_STALL_CNT2_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_STALL_CNT2_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_STALL_CNT2_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_STALL_CNT2_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_STALL_CNT2_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_STALL_CNT2_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_STALL_CNT2_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_STALL_CNT2_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_STALL_CNT2_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_STALL_CNT2_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_STALL_CNT2_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_STALL_CNT2_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_STALL_CNT2_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_STALL_CNT2_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_STALL_CNT2_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_STALL_CNT2_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* STORE_STALL_CNT */
+	uint32_t store_stall_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LDIO_STALL_CNT */
+	uint32_t ldio_stall_cnt 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_STALL_CNT2 ;
+#else
+typedef struct
+{	uint32_t ldio_stall_cnt 	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* LDIO_STALL_CNT */
+	uint32_t store_stall_cnt	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* STORE_STALL_CNT */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_STALL_CNT2 ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_task_cnt1                                                                        */
+/* pico count count                                                                      */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_TASK_CNT1_TASK1_CNT_RESERVED_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_TASK_CNT1_TASK1_CNT_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_TASK_CNT1_OFFSET ( 0x000001C0 )
+
+#define RUNNER_REGS_0_CFG_PICO_TASK_CNT1_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_TASK_CNT1_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_TASK_CNT1_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_TASK_CNT1_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_TASK_CNT1_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_TASK_CNT1_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_TASK_CNT1_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_TASK_CNT1_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_TASK_CNT1_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_TASK_CNT1_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_TASK_CNT1_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_TASK_CNT1_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_TASK_CNT1_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_TASK_CNT1_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_TASK_CNT1_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_TASK_CNT1_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_TASK_CNT1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* TASK1_CNT */
+	uint32_t task1_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_TASK_CNT1 ;
+#else
+typedef struct
+{	uint32_t task1_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TASK1_CNT */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_TASK_CNT1 ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_task_cnt2                                                                        */
+/* pico count                                                                            */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_TASK_CNT2_TASK2_CNT_RESERVED_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_TASK_CNT2_TASK2_CNT_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_TASK_CNT2_OFFSET ( 0x000001C4 )
+
+#define RUNNER_REGS_0_CFG_PICO_TASK_CNT2_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_TASK_CNT2_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_TASK_CNT2_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_TASK_CNT2_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_TASK_CNT2_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_TASK_CNT2_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_TASK_CNT2_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_TASK_CNT2_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_TASK_CNT2_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_TASK_CNT2_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_TASK_CNT2_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_TASK_CNT2_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_TASK_CNT2_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_TASK_CNT2_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_TASK_CNT2_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_TASK_CNT2_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_TASK_CNT2_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* TASK2_CNT */
+	uint32_t task2_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_TASK_CNT2 ;
+#else
+typedef struct
+{	uint32_t task2_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* TASK2_CNT */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_TASK_CNT2 ;
+#endif
+
+/*****************************************************************************************/
+/* Pico_idle_cnt                                                                         */
+/* pico idle count                                                                       */
+/*****************************************************************************************/
+
+#define RUNNER_REGS_CFG_PICO_IDLE_CNT1_IDLE_CNT_RESERVED_VALUE             ( 0x0 )
+#define RUNNER_REGS_CFG_PICO_IDLE_CNT1_IDLE_CNT_RESERVED_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define RUNNER_REGS_CFG_PICO_IDLE_CNT1_OFFSET ( 0x000001C8 )
+
+#define RUNNER_REGS_0_CFG_PICO_IDLE_CNT1_ADDRESS   	( RUNNER_REGS_0_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_IDLE_CNT1_OFFSET )
+#define RUNNER_REGS_0_CFG_PICO_IDLE_CNT1_READ( r ) 	READ_32( ( RUNNER_REGS_0_CFG_PICO_IDLE_CNT1_ADDRESS ), (r) )
+#define RUNNER_REGS_0_CFG_PICO_IDLE_CNT1_WRITE( v )	WRITE_32( ( RUNNER_REGS_0_CFG_PICO_IDLE_CNT1_ADDRESS ), (v) )
+
+#define RUNNER_REGS_1_CFG_PICO_IDLE_CNT1_ADDRESS   	( RUNNER_REGS_1_CFG_ADDRESS + RUNNER_REGS_CFG_PICO_IDLE_CNT1_OFFSET )
+#define RUNNER_REGS_1_CFG_PICO_IDLE_CNT1_READ( r ) 	READ_32( ( RUNNER_REGS_1_CFG_PICO_IDLE_CNT1_ADDRESS ), (r) )
+#define RUNNER_REGS_1_CFG_PICO_IDLE_CNT1_WRITE( v )	WRITE_32( ( RUNNER_REGS_1_CFG_PICO_IDLE_CNT1_ADDRESS ), (v) )
+
+
+extern uint32_t RUNNER_REGS_CFG_PICO_IDLE_CNT1_ARRAY [ ] ;
+
+#define RUNNER_REGS_CFG_PICO_IDLE_CNT1_WRITE( i, v )	WRITE_32( RUNNER_REGS_CFG_PICO_IDLE_CNT1_ARRAY [ i ], (v) )
+#define RUNNER_REGS_CFG_PICO_IDLE_CNT1_READ( i, r ) 	READ_32( RUNNER_REGS_CFG_PICO_IDLE_CNT1_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* IDLE */
+	uint32_t idle_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_IDLE_CNT1 ;
+#else
+typedef struct
+{	uint32_t idle_cnt	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* IDLE */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG_PICO_IDLE_CNT1 ;
+#endif
+
+typedef struct
+{
+	/* Data_memory_entry */
+	RUNNER_COMMON_MEM_HIGH high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Data_memory_entry */
+	RUNNER_COMMON_MEM_LOW low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_COMMON_MEM ;
+
+typedef struct
+{
+	/* Data_memory_entry */
+	RUNNER_PRIVATE_MEM_HIGH high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Data_memory_entry */
+	RUNNER_PRIVATE_MEM_LOW low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRIVATE_MEM ;
+
+typedef struct
+{
+	/* Instruction_memory_entry */
+	RUNNER_INST_MAIN_MEM_ENTRY entry __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_INST_MAIN_MEM ;
+
+typedef struct
+{
+	/* Context_mem_entry */
+	RUNNER_CNTXT_MAIN_MEM_ENTRY entry __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_CNTXT_MAIN_MEM ;
+
+/*****************************************************************************************/
+/* Prediction memory MAIN core                                                           */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+/* Due to prediction memory folding issue - relevant only for 6838 and 6838_G9991 */
+#ifdef BCM96838
+#define RUNNER_PRED_MAIN_MEM_ENTRY_NUMBER ( 384 )
+#else
+#define RUNNER_PRED_MAIN_MEM_ENTRY_NUMBER ( 448 )
+#endif
+
+typedef struct
+{
+	/* prediction_memory_core */
+	RUNNER_PRED_MAIN_MEM_ENTRY entry [ RUNNER_PRED_MAIN_MEM_ENTRY_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRED_MAIN_MEM ;
+
+typedef struct
+{
+	/* Instruction_memory_entry */
+	RUNNER_INST_PICO_MEM_ENTRY entry __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_INST_PICO_MEM ;
+
+typedef struct
+{
+	/* Context_mem_entry */
+	RUNNER_CNTXT_PICO_MEM_ENTRY entry __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_CNTXT_PICO_MEM ;
+
+/*****************************************************************************************/
+/* Prediction memory PICO core                                                           */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Registers array numbers                                                               */
+/*****************************************************************************************/
+#define RUNNER_PRED_PICO_MEM_ENTRY_NUMBER ( 256 )
+
+typedef struct
+{
+	/* Prediction_memory_pico */
+	RUNNER_PRED_PICO_MEM_ENTRY entry [ RUNNER_PRED_PICO_MEM_ENTRY_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRED_PICO_MEM ;
+
+typedef struct
+{
+	/* Global_control */
+	RUNNER_REGS_CFG_GLOBAL_CTRL global_ctrl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CPU_Wakeup */
+	RUNNER_REGS_CFG_CPU_WAKEUP cpu_wakeup __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_Control */
+	RUNNER_REGS_CFG_INT_CTRL int_ctrl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Interrupt_Mask */
+	RUNNER_REGS_CFG_INT_MASK int_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_table_Configuration */
+	RUNNER_REGS_CFG_LKUP0_CFG lkup0_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_table_Configuration */
+	RUNNER_REGS_CFG_LKUP1_CFG lkup1_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_table_Configuration */
+	RUNNER_REGS_CFG_LKUP2_CFG lkup2_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_table_Configuration */
+	RUNNER_REGS_CFG_LKUP3_CFG lkup3_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_table_CAM_configuration */
+	RUNNER_REGS_CFG_LKUP0_CAM_CFG lkup0_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_table_CAM_configuration */
+	RUNNER_REGS_CFG_LKUP1_CAM_CFG lkup1_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_table_CAM_configuration */
+	RUNNER_REGS_CFG_LKUP2_CAM_CFG lkup2_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_table_CAM_configuration */
+	RUNNER_REGS_CFG_LKUP3_CAM_CFG lkup3_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PSRAM_config_Register */
+	RUNNER_REGS_CFG_PSRAM_CFG psram_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CAM_configuration */
+	RUNNER_REGS_CFG_CAM_CFG cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Counters_Configuration */
+	RUNNER_REGS_CFG_CNTR_CFG cntr_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_config_Register */
+	RUNNER_REGS_CFG_DDR_CFG ddr_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_Status_and_Control */
+	RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_0 mipsc_semaphor_sts_0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_Status_and_Control */
+	RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_1 mipsc_semaphor_sts_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_Status_and_Control */
+	RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_2 mipsc_semaphor_sts_2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_Status_and_Control */
+	RUNNER_REGS_CFG_MIPSC_SEMAPHOR_STS_3 mipsc_semaphor_sts_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_look-up_Global_Mask */
+	RUNNER_REGS_CFG_DDR_LKUP_MASK0 ddr_lkup_mask0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_look-up_Global_Mask */
+	RUNNER_REGS_CFG_DDR_LKUP_MASK1 ddr_lkup_mask1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_look-up_Global_Mask */
+	RUNNER_REGS_CFG_DDR_LKUP_MASK2 ddr_lkup_mask2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DDR_look-up_Global_Mask */
+	RUNNER_REGS_CFG_DDR_LKUP_MASK3 ddr_lkup_mask3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PSRAM_look-up_Global_Mask */
+	RUNNER_REGS_CFG_PSRAM_LKUP_MASK0 psram_lkup_mask0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PSRAM_look-up_Global_Mask */
+	RUNNER_REGS_CFG_PSRAM_LKUP_MASK1 psram_lkup_mask1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PSRAM_look-up_Global_Mask */
+	RUNNER_REGS_CFG_PSRAM_LKUP_MASK2 psram_lkup_mask2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PSRAM_look-up_Global_Mask */
+	RUNNER_REGS_CFG_PSRAM_LKUP_MASK3 psram_lkup_mask3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_global_mask */
+	RUNNER_REGS_CFG_LKUP_GLBL_MASK0_H lkup_glbl_mask0_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_global_mask */
+	RUNNER_REGS_CFG_LKUP_GLBL_MASK0_L lkup_glbl_mask0_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_global_mask */
+	RUNNER_REGS_CFG_LKUP_GLBL_MASK1_H lkup_glbl_mask1_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_global_mask */
+	RUNNER_REGS_CFG_LKUP_GLBL_MASK1_L lkup_glbl_mask1_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_global_mask */
+	RUNNER_REGS_CFG_LKUP_GLBL_MASK2_H lkup_glbl_mask2_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_global_mask */
+	RUNNER_REGS_CFG_LKUP_GLBL_MASK2_L lkup_glbl_mask2_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_global_mask */
+	RUNNER_REGS_CFG_LKUP_GLBL_MASK3_H lkup_glbl_mask3_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look-up_global_mask */
+	RUNNER_REGS_CFG_LKUP_GLBL_MASK3_L lkup_glbl_mask3_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Look_up_configuration */
+	RUNNER_REGS_CFG_LKUP_CFG lkup_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 28 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_profiling_sts */
+	RUNNER_REGS_CFG_MAIN_PROFILING_STS main_profiling_sts __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_profiling_cfg */
+	RUNNER_REGS_CFG_MAIN_PROFILING_CFG main_profiling_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_stall_cnt1 */
+	RUNNER_REGS_CFG_MAIN_STALL_CNT1 main_stall_cnt1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_stall_cnt2 */
+	RUNNER_REGS_CFG_MAIN_STALL_CNT2 main_stall_cnt2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_task_cnt1 */
+	RUNNER_REGS_CFG_MAIN_TASK1_CNT main_task1_cnt __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_task_cnt2 */
+	RUNNER_REGS_CFG_MAIN_TASK2_CNT main_task2_cnt __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_idle_cnt1 */
+	RUNNER_REGS_CFG_MAIN_IDLE_CNT1 main_idle_cnt1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved2 [ 20 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Version */
+	RUNNER_REGS_CFG_VERSION_ADDR version_addr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved3 [ 8 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Ramrd_mask_config */
+	RUNNER_REGS_CFG_RAMRD_RANGE_MASK_CFG ramrd_range_mask_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Metal_fix */
+	RUNNER_REGS_CFG_METAL_FIX_REG metal_fix_reg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Timer_target */
+	RUNNER_REGS_CFG_TIMER_TARGET timer_target __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Scheduler_main_config */
+	RUNNER_REGS_CFG_MAIN_SCH_CFG main_sch_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Scheduler_pico_config */
+	RUNNER_REGS_CFG_PICO_SCH_CFG pico_sch_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved4 [ 16 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_bkpt_0 */
+	RUNNER_REGS_CFG_MAIN_BKPT_0 main_bkpt_0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_bkpt_1 */
+	RUNNER_REGS_CFG_MAIN_BKPT_1 main_bkpt_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_bkpt_2 */
+	RUNNER_REGS_CFG_MAIN_BKPT_2 main_bkpt_2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_bkpt_3 */
+	RUNNER_REGS_CFG_MAIN_BKPT_3 main_bkpt_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_bkpt_immediate */
+	RUNNER_REGS_CFG_MAIN_BKPT_IMM main_bkpt_imm __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_bkpt_0 */
+	RUNNER_REGS_CFG_PICO_BKPT_0 pico_bkpt_0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_bkpt_1 */
+	RUNNER_REGS_CFG_PICO_BKPT_1 pico_bkpt_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_bkpt_2 */
+	RUNNER_REGS_CFG_PICO_BKPT_2 pico_bkpt_2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_bkpt_3 */
+	RUNNER_REGS_CFG_PICO_BKPT_3 pico_bkpt_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_bkpt_immediate */
+	RUNNER_REGS_CFG_PICO_BKPT_IMM pico_bkpt_imm __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cfg_1588 */
+	RUNNER_REGS_CFG_CFG_1588 cfg_1588 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cfg_8k */
+	RUNNER_REGS_CFG_CFG_8K cfg_8k __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_Status_and_Control */
+	RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_0 mipsd_semaphor_sts_0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_Status_and_Control */
+	RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_1 mipsd_semaphor_sts_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_Status_and_Control */
+	RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_2 mipsd_semaphor_sts_2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Semaphore_Status_and_Control */
+	RUNNER_REGS_CFG_MIPSD_SEMAPHOR_STS_3 mipsd_semaphor_sts_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Main_jump_cnt */
+	RUNNER_REGS_CFG_MAIN_JMP_CNT main_jmp_cnt __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_jump_cnt */
+	RUNNER_REGS_CFG_PICO_JMP_CNT pico_jmp_cnt __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MAIN_BKPT_CFG */
+	RUNNER_REGS_CFG_MAIN_BKPT_CFG main_bkpt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PICO_BKPT_CFG */
+	RUNNER_REGS_CFG_PICO_BKPT_CFG pico_bkpt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MAIN_BKPT_STS */
+	RUNNER_REGS_CFG_MAIN_BKPT_STS main_bkpt_sts __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PICO_BKPT_STS */
+	RUNNER_REGS_CFG_PICO_BKPT_STS pico_bkpt_sts __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved5 [ 72 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_profiling_sts */
+	RUNNER_REGS_CFG_PICO_PROFILING_STS pico_profiling_sts __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_profiling_cfg */
+	RUNNER_REGS_CFG_PICO_PROFILING_CFG pico_profiling_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_stall_cnt1 */
+	RUNNER_REGS_CFG_PICO_STALL_CNT1 pico_stall_cnt1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_stall_cnt2 */
+	RUNNER_REGS_CFG_PICO_STALL_CNT2 pico_stall_cnt2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_task_cnt1 */
+	RUNNER_REGS_CFG_PICO_TASK_CNT1 pico_task_cnt1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_task_cnt2 */
+	RUNNER_REGS_CFG_PICO_TASK_CNT2 pico_task_cnt2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Pico_idle_cnt */
+	RUNNER_REGS_CFG_PICO_IDLE_CNT1 pico_idle_cnt1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS_CFG ;
+
+typedef struct
+{
+	/* mem function */
+	RUNNER_COMMON_MEM mem [ RUNNER_COMMON_MEM_COUNTER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_COMMON ;
+
+typedef struct
+{
+	/* mem function */
+	RUNNER_PRIVATE_MEM mem [ RUNNER_PRIVATE_MEM_COUNTER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRIVATE ;
+
+typedef struct
+{
+	/* mem function */
+	RUNNER_INST_MAIN_MEM mem [ RUNNER_INST_MAIN_MEM_COUNTER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_INST_MAIN ;
+
+typedef struct
+{
+	/* mem function */
+	RUNNER_CNTXT_MAIN_MEM mem [ RUNNER_CNTXT_MAIN_MEM_COUNTER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_CNTXT_MAIN ;
+
+typedef struct
+{
+	/* mem function */
+	RUNNER_PRED_MAIN_MEM mem __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRED_MAIN ;
+
+typedef struct
+{
+	/* mem function */
+	RUNNER_INST_PICO_MEM mem [ RUNNER_INST_PICO_MEM_COUNTER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_INST_PICO ;
+
+typedef struct
+{
+	/* mem function */
+	RUNNER_CNTXT_PICO_MEM mem [ RUNNER_CNTXT_PICO_MEM_COUNTER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_CNTXT_PICO ;
+
+typedef struct
+{
+	/* mem function */
+	RUNNER_PRED_PICO_MEM mem __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_PRED_PICO ;
+
+typedef struct
+{
+	/* cfg function */
+	RUNNER_REGS_CFG cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+RUNNER_REGS ;
+
+#define RUNNER_COMMON_NUMBER ( 2 )
+#define RUNNER_PRIVATE_NUMBER ( 2 )
+#define RUNNER_INST_MAIN_NUMBER ( 2 )
+#define RUNNER_CNTXT_MAIN_NUMBER ( 2 )
+#define RUNNER_PRED_MAIN_NUMBER ( 2 )
+#define RUNNER_INST_PICO_NUMBER ( 2 )
+#define RUNNER_CNTXT_PICO_NUMBER ( 2 )
+#define RUNNER_PRED_PICO_NUMBER ( 2 )
+#define RUNNER_REGS_NUMBER ( 2 )
+typedef struct
+{
+	/* COMMON */
+	RUNNER_COMMON common [ RUNNER_COMMON_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 65528 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PRIVATE */
+	RUNNER_PRIVATE private [ RUNNER_PRIVATE_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved2 [ 65528 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* INST_MAIN */
+	RUNNER_INST_MAIN inst_main [ RUNNER_INST_MAIN_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved3 [ 32764 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CNTXT_MAIN */
+	RUNNER_CNTXT_MAIN cntxt_main [ RUNNER_CNTXT_MAIN_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved4 [ 16380 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PRED_MAIN */
+	RUNNER_PRED_MAIN pred_main [ RUNNER_PRED_MAIN_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved5 [ 15488 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* INST_PICO */
+	RUNNER_INST_PICO inst_pico [ RUNNER_INST_PICO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved6 [ 32764 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CNTXT_PICO */
+	RUNNER_CNTXT_PICO cntxt_pico [ RUNNER_CNTXT_PICO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved7 [ 16380 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PRED_PICO */
+	RUNNER_PRED_PICO pred_pico [ RUNNER_PRED_PICO_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved8 [ 380416 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* REGS */
+	RUNNER_REGS regs [ RUNNER_REGS_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ 
+RUNNER_FOR_ALL ;
+#endif /* RUNNER_H_INCLUDED */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_sbpm.h b/arch/arm/mach-bcmbca/rdp/rdp_sbpm.h
new file mode 100755
index 0000000000..c71fe9f381
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_sbpm.h
@@ -0,0 +1,4315 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+     
+*/             
+
+#ifndef __SBPM_H_INCLUDED
+#define __SBPM_H_INCLUDED
+
+/*  File automatically generated by Reggae at 15/08/2013  10:55:11   */
+
+#include "access_macros.h"
+#include "packing.h"
+#include "rdp_map.h"
+
+/*****************************************************************************************/
+/* The SRAM BPM (SBPM) is responsible for managing the pool of free SRAM buffers.   The  */
+/* buffers are linked to each other in a linked list (each buffer points to the next buf */
+/* fer).     The linked list is kept in a dedicated SRAM. Two kinds of linked lists are  */
+/* kept:       	* Free buffers list - each time a buffer is given to one of the users, i */
+/* t will be the buffer at the head of the list and the next buffer in the list          */
+/*  will be marked as the new head. Each time a buffer is freed by one of the users, it  */
+/* will be linked back to the list as the new tail.       	* Packet linked list - a list */
+/*  per packet which hold the order of buffers in which each packet is stored.    The SB */
+/* PM also supports flow control and decoupling of upstream/downstream/local switching r */
+/* esources by managing buffers counters and configurable thresholds per user group.  Fo */
+/* r maximum utilization of the memory for different packet size the allocation of memor */
+/* y is handled in chunks of 128 bytes.                                                  */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Blocks offsets                                                                        */
+/*****************************************************************************************/
+/*****************************************************************************************/
+/* Functions offsets and addresses                                                       */
+/*****************************************************************************************/
+#define SBPM_BLOCK_REGS_OFFSET 	( 0x00000000 )
+#define SBPM_BLOCK_REGS_ADDRESS	( SBPM_BLOCK_OFFSET + SBPM_BLOCK_REGS_OFFSET )
+
+/*   'd' is module index   */
+/*   'i' is block index    */
+/*   'j' is function index */
+/*   'e' is function entry */
+/*   'k' is register index */
+
+/*****************************************************************************************/
+/* init_free_list                                                                        */
+/* request for building the free list using HW accelerator                               */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_RDY_DEFAULT_VALUE                           ( 0x0 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_RDY_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_BSY_NO_REQUEST_VALUE                        ( 0x0 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_BSY_NO_REQUEST_VALUE_RESET_VALUE            ( 0x0 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_BSY_REQUEST_IN_PROGRESS_VALUE               ( 0x1 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_RSV_DEFAULT_VALUE                           ( 0x0 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_RSV_DEFAULT_VALUE_RESET_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_INIT_EN_DEFAULT_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_INIT_EN_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_INIT_NUM_BN_DEFAULT_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_INIT_NUM_BN_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_INIT_HEAD_BN_ADDR_DEFAULT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_INIT_HEAD_BN_ADDR_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_OFFSET ( 0x00000000 )
+
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_INIT_FREE_LIST_OFFSET )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_INIT_FREE_LIST_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_INIT_FREE_LIST_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_INIT_FREE_LIST_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* ready */
+	uint32_t rdy              	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t bsy              	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv              	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* init_en */
+	uint32_t init_en          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* init_num_bn */
+	uint32_t init_num_bn      	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* init_head_bn_addr */
+	uint32_t init_head_bn_addr	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_INIT_FREE_LIST ;
+#else
+typedef struct
+{	uint32_t init_head_bn_addr	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* init_head_bn_addr */
+	uint32_t init_num_bn      	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* init_num_bn */
+	uint32_t init_en          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* init_en */
+	uint32_t rsv              	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t bsy              	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t rdy              	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ready */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_INIT_FREE_LIST ;
+#endif
+
+/*****************************************************************************************/
+/* bn_alloc                                                                              */
+/* request for a new buffer                                                              */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_BN_ALLOC_RSV2_RSV_VALUE                      ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RSV2_RSV_VALUE_RESET_VALUE          ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_SA_SOURCE_ADDRESS_VALUE             ( 0x6 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_SA_SOURCE_ADDRESS_VALUE_RESET_VALUE ( 0x6 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RSV1_DEFAULT_VALUE                  ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RSV1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_BN_ALLOC_OFFSET ( 0x00000004 )
+
+#define SBPM_BLOCK_REGS_BN_ALLOC_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_BN_ALLOC_OFFSET )
+#define SBPM_BLOCK_REGS_BN_ALLOC_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_BN_ALLOC_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_BN_ALLOC_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_BN_ALLOC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* source_address */
+	uint32_t sa  	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_ALLOC ;
+#else
+typedef struct
+{	uint32_t rsv1	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t sa  	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* source_address */
+	uint32_t rsv2	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_ALLOC ;
+#endif
+
+/*****************************************************************************************/
+/* bn_alloc_rply                                                                         */
+/* reply for a new buffer alloc                                                          */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_RDY_DEFAULT_VALUE                        ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_RDY_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_BUSY_DEFAULT_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_BUSY_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_RSV_DEFAULT_VALUE                        ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_RSV_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_EXCL_DEFAULT_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_EXCL_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_NACK_DEFAULT_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_NACK_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_ACK_DEFAULT_VALUE                        ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_ACK_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_ALLOC_BN_DEFAULT_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_ALLOC_BN_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_DEFAULT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_OFFSET ( 0x00000008 )
+
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_BN_ALLOC_RPLY_OFFSET )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_BN_ALLOC_RPLY_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_BN_ALLOC_RPLY_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_BN_ALLOC_RPLY_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rdy */
+	uint32_t rdy           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t busy          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv           	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* excl */
+	uint32_t excl          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* nack */
+	uint32_t nack          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ack */
+	uint32_t ack           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_bn */
+	uint32_t alloc_bn      	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_bn_valid */
+	uint32_t alloc_bn_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_ALLOC_RPLY ;
+#else
+typedef struct
+{	uint32_t alloc_bn_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_bn_valid */
+	uint32_t alloc_bn      	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_bn */
+	uint32_t ack           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ack */
+	uint32_t nack          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* nack */
+	uint32_t excl          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* excl */
+	uint32_t rsv           	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t busy          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t rdy           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rdy */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_ALLOC_RPLY ;
+#endif
+
+/*****************************************************************************************/
+/* bn_free_with_contxt_low                                                               */
+/* Request for freeing buffers of a packet offline with context (lower 32-bit)           */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_RSV3_RSV2_VALUE                     ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_RSV3_RSV2_VALUE_RESET_VALUE         ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_OFFSET_VALUE                 ( 0x1 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_OFFSET_VALUE_RESET_VALUE     ( 0x1 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_RSV2_RSV_VALUE                      ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_RSV2_RSV_VALUE_RESET_VALUE          ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_SA_SOURCE_ADDRESS_VALUE             ( 0x6 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_SA_SOURCE_ADDRESS_VALUE_RESET_VALUE ( 0x6 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_RSV1_DEFAULT_VALUE                  ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_RSV1_DEFAULT_VALUE_RESET_VALUE      ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_HEAD_BN_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_HEAD_BN_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET ( 0x0000000C )
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* offset */
+	uint32_t offset 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv2   	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* source_address */
+	uint32_t sa     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* head_bn */
+	uint32_t head_bn	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW ;
+#else
+typedef struct
+{	uint32_t head_bn	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* head_bn */
+	uint32_t rsv1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t sa     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* source_address */
+	uint32_t rsv2   	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t offset 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* offset */
+	uint32_t rsv3   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW ;
+#endif
+
+/*****************************************************************************************/
+/* bn_free_with_contxt_high                                                              */
+/* Request for freeing buffers of a packet offline with context (higher 32-bit)          */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH_RSV_RSERVED_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH_RSV_RSERVED_VALUE_RESET_VALUE     ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_DEFAULT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH_OFFSET ( 0x00000010 )
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH_OFFSET )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv    	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* last_BN */
+	uint32_t last_bn	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH ;
+#else
+typedef struct
+{	uint32_t last_bn	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* last_BN */
+	uint32_t rsv    	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH ;
+#endif
+
+/*****************************************************************************************/
+/* mcst_inc                                                                              */
+/* Multicast counter increment. Contains the BN, which is head of the packet to be multi */
+/* cast and its counter value                                                            */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_MCST_INC_RSV2_RESERVED_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_RSV2_RESERVED_VALUE_RESET_VALUE     ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_ACK_REQ_ACK_REQ_VALUE               ( 0x1 )
+#define SBPM_BLOCK_REGS_MCST_INC_ACK_REQ_ACK_REQ_VALUE_RESET_VALUE   ( 0x1 )
+#define SBPM_BLOCK_REGS_MCST_INC_MCST_VAL_MCST_VAL_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_MCST_VAL_MCST_VAL_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_RSV1_RSERVED_VALUE                  ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_RSV1_RSERVED_VALUE_RESET_VALUE      ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_BN_BN_VALUE                         ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_BN_BN_VALUE_RESET_VALUE             ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_MCST_INC_OFFSET ( 0x00000014 )
+
+#define SBPM_BLOCK_REGS_MCST_INC_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_MCST_INC_OFFSET )
+#define SBPM_BLOCK_REGS_MCST_INC_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_MCST_INC_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_MCST_INC_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_MCST_INC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t rsv2    	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ack_req */
+	uint32_t ack_req 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_val */
+	uint32_t mcst_val	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv1    	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bufer_number */
+	uint32_t bn      	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_MCST_INC ;
+#else
+typedef struct
+{	uint32_t bn      	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bufer_number */
+	uint32_t rsv1    	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t mcst_val	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_val */
+	uint32_t ack_req 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ack_req */
+	uint32_t rsv2    	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_MCST_INC ;
+#endif
+
+/*****************************************************************************************/
+/* mcst_inc_rply                                                                         */
+/* mcst_inc_rply                                                                         */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_RDY_DEFAULT_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_RDY_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_BSY_DEFAULT_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_BSY_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_RSV_DEFAULT_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_RSV_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_MCST_ACK_MCST_ACK_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_MCST_ACK_MCST_ACK_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_OFFSET ( 0x00000018 )
+
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_MCST_INC_RPLY_OFFSET )
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_MCST_INC_RPLY_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_MCST_INC_RPLY_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_MCST_INC_RPLY_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* ready */
+	uint32_t rdy     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t bsy     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv     	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_ack */
+	uint32_t mcst_ack	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_MCST_INC_RPLY ;
+#else
+typedef struct
+{	uint32_t mcst_ack	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_ack */
+	uint32_t rsv     	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t bsy     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t rdy     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ready */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_MCST_INC_RPLY ;
+#endif
+
+/*****************************************************************************************/
+/* bn_connect                                                                            */
+/* request for connection between two buffers in a linked list. The connection request m */
+/* ay be replied with ACK message if the ACK request bit is asserted.  This command is u */
+/* sed as write command.                                                                 */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_BN_CONNECT_RSV_DEFAULT_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_WR_REQ_WR_REQ_VALUE                     ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_WR_REQ_WR_REQ_VALUE_RESET_VALUE         ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_ACK_REQ_ACK_REQ_VALUE                   ( 0x1 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_ACK_REQ_ACK_REQ_VALUE_RESET_VALUE       ( 0x1 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_POINTED_BN_POINTED_BN_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_POINTED_BN_POINTED_BN_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_BN_BN_VALUE                             ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_BN_BN_VALUE_RESET_VALUE                 ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_BN_CONNECT_OFFSET ( 0x0000001C )
+
+#define SBPM_BLOCK_REGS_BN_CONNECT_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_BN_CONNECT_OFFSET )
+#define SBPM_BLOCK_REGS_BN_CONNECT_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_BN_CONNECT_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_BN_CONNECT_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_BN_CONNECT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* wr_req */
+	uint32_t wr_req    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ack_req */
+	uint32_t ack_req   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pointed_bn */
+	uint32_t pointed_bn	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn */
+	uint32_t bn        	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_CONNECT ;
+#else
+typedef struct
+{	uint32_t bn        	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn */
+	uint32_t pointed_bn	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pointed_bn */
+	uint32_t ack_req   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ack_req */
+	uint32_t wr_req    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* wr_req */
+	uint32_t rsv       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_CONNECT ;
+#endif
+
+/*****************************************************************************************/
+/* bn_connect_rply                                                                       */
+/* bn_connect_rply                                                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_RDY_READY_BIT_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_RDY_READY_BIT_VALUE_RESET_VALUE           ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_BUSY_BUSY_BIT_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_BUSY_BUSY_BIT_VALUE_RESET_VALUE           ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_RSV_RSV_VALUE                             ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_RSV_RSV_VALUE_RESET_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_CONNECT_ACK_CONNECT_ACK_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_CONNECT_ACK_CONNECT_ACK_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_OFFSET ( 0x00000020 )
+
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_BN_CONNECT_RPLY_OFFSET )
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_BN_CONNECT_RPLY_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_BN_CONNECT_RPLY_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_BN_CONNECT_RPLY_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rdy */
+	uint32_t rdy        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t busy       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv        	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_ack */
+	uint32_t connect_ack	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_CONNECT_RPLY ;
+#else
+typedef struct
+{	uint32_t connect_ack	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_ack */
+	uint32_t rsv        	: 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t busy       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t rdy        	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rdy */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_CONNECT_RPLY ;
+#endif
+
+/*****************************************************************************************/
+/* get_next                                                                              */
+/* a pointer to a buffer in a packet linked list and request for the next buffer in the  */
+/* list  this command is used as read command.                                           */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_GET_NEXT_RSV_DEFAULT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RSV_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_BN_BN_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_BN_BN_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_GET_NEXT_OFFSET ( 0x00000024 )
+
+#define SBPM_BLOCK_REGS_GET_NEXT_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_GET_NEXT_OFFSET )
+#define SBPM_BLOCK_REGS_GET_NEXT_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_GET_NEXT_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_GET_NEXT_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_GET_NEXT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bufer_number */
+	uint32_t bn 	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_GET_NEXT ;
+#else
+typedef struct
+{	uint32_t bn 	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bufer_number */
+	uint32_t rsv	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_GET_NEXT ;
+#endif
+
+/*****************************************************************************************/
+/* get_next_rply                                                                         */
+/* get_next_rply                                                                         */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_RDY_RDY_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_RDY_RDY_VALUE_RESET_VALUE           ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_BUSY_BUSY_VALUE                     ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_BUSY_BUSY_VALUE_RESET_VALUE         ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_RSV_DEFAULT_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_RSV_DEFAULT_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_MCNT_VAL_MCNT_VAL_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_MCNT_VAL_MCNT_VAL_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_BN_NULL_BN_NULL_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_BN_NULL_BN_NULL_VALUE_RESET_VALUE   ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_CONSTANT_CONSTANT_VALUE             ( 0x8 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_CONSTANT_CONSTANT_VALUE_RESET_VALUE ( 0x8 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_NEXT_BN_NEXT_BN_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_NEXT_BN_NEXT_BN_VALUE_RESET_VALUE   ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_BN_VALID_BN_VALID_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_BN_VALID_BN_VALID_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_OFFSET ( 0x00000028 )
+
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_GET_NEXT_RPLY_OFFSET )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_GET_NEXT_RPLY_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_GET_NEXT_RPLY_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_GET_NEXT_RPLY_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rdy */
+	uint32_t rdy     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t busy    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv     	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcnt_val */
+	uint32_t mcnt_val	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_null */
+	uint32_t bn_null 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* constant */
+	uint32_t constant	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* next_bn */
+	uint32_t next_bn 	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_valid */
+	uint32_t bn_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_GET_NEXT_RPLY ;
+#else
+typedef struct
+{	uint32_t bn_valid	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_valid */
+	uint32_t next_bn 	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* next_bn */
+	uint32_t constant	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* constant */
+	uint32_t bn_null 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_null */
+	uint32_t mcnt_val	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcnt_val */
+	uint32_t rsv     	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t busy    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t rdy     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rdy */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_GET_NEXT_RPLY ;
+#endif
+
+/*****************************************************************************************/
+/* bn_free_without_contxt                                                                */
+/* bn_free_without_contxt                                                                */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_DEFAULT_VALUE               ( 0x1 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_DEFAULT_VALUE_RESET_VALUE   ( 0x1 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RSV2_RESERVED_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RSV2_RESERVED_VALUE_RESET_VALUE     ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_SA_SOURCE_ADDRESS_VALUE             ( 0x6 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_SA_SOURCE_ADDRESS_VALUE_RESET_VALUE ( 0x6 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RSV1_RSV_VALUE                      ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RSV1_RSV_VALUE_RESET_VALUE          ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_HEAD_BN_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_HEAD_BN_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_OFFSET ( 0x00000038 )
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_OFFSET )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* ack_req */
+	uint32_t ack_req	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv2   	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* source_address */
+	uint32_t sa     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* head_bn */
+	uint32_t head_bn	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT ;
+#else
+typedef struct
+{	uint32_t head_bn	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* head_bn */
+	uint32_t rsv1   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t sa     	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* source_address */
+	uint32_t rsv2   	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ack_req	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ack_req */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT ;
+#endif
+
+/*****************************************************************************************/
+/* bn_free_without_contxt_rply                                                           */
+/* bn_free_without_contxt_rply                                                           */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_READY_BIT_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_READY_BIT_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_BUSY_BIT_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_BUSY_BIT_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RSV2_RESERVED_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RSV2_RESERVED_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_STAT_EXCL_STAT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_STAT_EXCL_STAT_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_NACK_STAT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_NACK_STAT_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_ACK_STATUS_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_ACK_STATUS_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RSV1_RSERVED_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RSV1_RSERVED_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_FREE_ACK_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_FREE_ACK_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_OFFSET ( 0x0000003C )
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_OFFSET )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rdy */
+	uint32_t rdy      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bsy */
+	uint32_t bsy      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv2     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* excl_stat */
+	uint32_t excl_stat	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* nack_stat */
+	uint32_t nack_stat	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ack_stat */
+	uint32_t ack_stat 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1     	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* free_ack */
+	uint32_t free_ack 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY ;
+#else
+typedef struct
+{	uint32_t free_ack 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* free_ack */
+	uint32_t rsv1     	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ack_stat 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ack_stat */
+	uint32_t nack_stat	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* nack_stat */
+	uint32_t excl_stat	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* excl_stat */
+	uint32_t rsv2     	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t bsy      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bsy */
+	uint32_t rdy      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rdy */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY ;
+#endif
+
+/*****************************************************************************************/
+/* bn_free_with_contxt_rply                                                              */
+/* bn_free_with_contxt_rply                                                              */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_READY_BIT_VALUE                           ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_READY_BIT_VALUE_RESET_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_BUSY_BIT_VALUE                           ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_BUSY_BIT_VALUE_RESET_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_RSV2_RESERVED_VALUE                           ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_RSV2_RESERVED_VALUE_RESET_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_STATE_EXCLUSIVE_STATUS_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_STATE_EXCLUSIVE_STATUS_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_NACK_STATUS_VALUE                  ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_NACK_STATUS_VALUE_RESET_VALUE      ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_ACK_STATUS_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_ACK_STATUS_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_RSV1_RESERVED_VALUE                           ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_RSV1_RESERVED_VALUE_RESET_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_FREE_ACK_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_FREE_ACK_VALUE_RESET_VALUE           ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_OFFSET ( 0x00000040 )
+
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_OFFSET )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rdy */
+	uint32_t rdy       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t busy      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv2      	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* excl_satate */
+	uint32_t excl_state	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* nack_state */
+	uint32_t nack_state	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ack_state */
+	uint32_t ack_state 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* free_ack */
+	uint32_t free_ack  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY ;
+#else
+typedef struct
+{	uint32_t free_ack  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* free_ack */
+	uint32_t rsv1      	: 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ack_state 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ack_state */
+	uint32_t nack_state	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* nack_state */
+	uint32_t excl_state	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* excl_satate */
+	uint32_t rsv2      	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t busy      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* busy */
+	uint32_t rdy       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rdy */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_SP_EN                                                                            */
+/* Source Port enable of SBPM allows configuration of active (ENABLED) ports that have d */
+/* irect I/F to SBPM block. The client that was defined as disabled port (for example fi */
+/* eld of EMAC4 = 0x0) will state in NACK state always till it will be enabled. All BBH  */
+/* ports that goes from disable to enable state gets ACK message vaa broad see (SBPM spe */
+/* c section 11.3.3)                                                                     */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_RSV4_RSV_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_RSV4_RSV_VALUE_RESET_VALUE           ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH4_SP_EN_DISABLE_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH4_SP_EN_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH4_SP_EN_ENABLE_VALUE              ( 0x1 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH3_SP_EN_DISABLE_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH3_SP_EN_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH3_SP_EN_ENABLE_VALUE              ( 0x1 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH2_SP_EN_DISABLE_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH2_SP_EN_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH2_SP_EN_ENABLE_VALUE              ( 0x1 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH1_SP_EN_DISABLE_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH1_SP_EN_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH1_SP_EN_ENABLE_VALUE              ( 0x1 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH0_SP_EN_DISABLE_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH0_SP_EN_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ETH0_SP_EN_ENABLE_VALUE              ( 0x1 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_GPON_SP_EN_DISABLE_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_GPON_SP_EN_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_GPON_SP_EN_ENABLE_VALUE              ( 0x1 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_RNRB_SP_EN_DISABLE_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_RNRB_SP_EN_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_RNRB_SP_EN_ENABLE_VALUE              ( 0x1 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_RNRA_SP_EN_DISABLE_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_RNRA_SP_EN_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_RNRA_SP_EN_ENABLE_VALUE              ( 0x1 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_OFFSET ( 0x00000048 )
+
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_SP_EN_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_SP_EN_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_SP_EN_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_SP_EN_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv4      	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_SP_EN */
+	uint32_t eth4_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_SP_EN */
+	uint32_t eth3_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_SP_EN */
+	uint32_t eth2_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_SP_EN */
+	uint32_t eth1_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH0_SP_EN */
+	uint32_t eth0_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_SP_EN */
+	uint32_t gpon_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_SP_EN */
+	uint32_t rnrb_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_SP_EN */
+	uint32_t rnra_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_SP_EN ;
+#else
+typedef struct
+{	uint32_t rnra_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRA_SP_EN */
+	uint32_t rnrb_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNRB_SP_EN */
+	uint32_t gpon_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_SP_EN */
+	uint32_t eth0_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH0_SP_EN */
+	uint32_t eth1_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH1_SP_EN */
+	uint32_t eth2_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH2_SP_EN */
+	uint32_t eth3_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH3_SP_EN */
+	uint32_t eth4_sp_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ETH4_SP_EN */
+	uint32_t rsv4      	: 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_SP_EN ;
+#endif
+
+/*****************************************************************************************/
+/* Global_Threshold                                                                      */
+/* Global Threshold for Allocated Buffers.  SBPM will issue BN in the accepted range upo */
+/* n to Global threshold setup.  Ths register also holds global hysteresis value for ACK */
+/* /NACK transition setting                                                              */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_RSV2_RSV_VALUE                                             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_RSV2_RSV_VALUE_RESET_VALUE                                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_GL_BAH_GL_BAH_VALUE                                        ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_GL_BAH_GL_BAH_VALUE_RESET_VALUE                            ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_RSV_RSV_VALUE                                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_RSV_RSV_VALUE_RESET_VALUE                                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_GL_BAT_GLOBAL_BUFFER_ALLOCATED_THRESHOLD_VALUE             ( 0x3FF )
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_GL_BAT_GLOBAL_BUFFER_ALLOCATED_THRESHOLD_VALUE_RESET_VALUE ( 0x3FF )
+
+
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_OFFSET ( 0x0000004C )
+
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_GL_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_GL_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_GL_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_GL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv2 */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GL_BAH */
+	uint32_t gl_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GL_BAT */
+	uint32_t gl_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_GL_TRSH ;
+#else
+typedef struct
+{	uint32_t gl_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GL_BAT */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv1 */
+	uint32_t gl_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GL_BAH */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv2 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_GL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG0_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG0  Ths register also holds UG0 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_RSV2_RSV_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_RSV2_RSV_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_UG_BAH_UG0_BAH_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_UG_BAH_UG0_BAH_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_UG_BAT_UG0_BAT_VALUE             ( 0x3FF )
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_UG_BAT_UG0_BAT_VALUE_RESET_VALUE ( 0x3FF )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_OFFSET ( 0x00000050 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG0_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG0_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG0_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG0_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG0_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG0_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG1_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG1  Ths register also holds UG1 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_RSV2_RSV_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_RSV2_RSV_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_UG_BAH_UG0_BAH_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_UG_BAH_UG0_BAH_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_UG_BAT_UG0_BAT_VALUE             ( 0x3FF )
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_UG_BAT_UG0_BAT_VALUE_RESET_VALUE ( 0x3FF )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_OFFSET ( 0x00000054 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG1_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG1_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG1_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG1_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG1_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG1_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG2_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG2  Ths register also holds UG1 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_RSV2_RSV_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_RSV2_RSV_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_UG_BAH_UG0_BAH_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_UG_BAH_UG0_BAH_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_UG_BAT_UG0_BAT_VALUE             ( 0x3FF )
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_UG_BAT_UG0_BAT_VALUE_RESET_VALUE ( 0x3FF )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_OFFSET ( 0x00000058 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG2_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG2_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG2_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG2_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG2_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG2_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG3_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG3  Ths register also holds UG3 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_RSV2_RSV_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_RSV2_RSV_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_UG_BAH_UG0_BAH_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_UG_BAH_UG0_BAH_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_UG_BAT_UG0_BAT_VALUE             ( 0x3FF )
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_UG_BAT_UG0_BAT_VALUE_RESET_VALUE ( 0x3FF )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_OFFSET ( 0x0000005C )
+
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG3_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG3_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG3_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG3_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG3_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG3_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG4_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG4  Ths register also holds UG4 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_RSV2_RSV_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_RSV2_RSV_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_UG_BAH_UG0_BAH_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_UG_BAH_UG0_BAH_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_UG_BAT_UG0_BAT_VALUE             ( 0x3FF )
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_UG_BAT_UG0_BAT_VALUE_RESET_VALUE ( 0x3FF )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_OFFSET ( 0x00000060 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG4_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG4_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG4_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG4_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG4_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG4_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG5_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG5  Ths register also holds UG5 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_RSV2_RSV_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_RSV2_RSV_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_UG_BAH_UG0_BAH_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_UG_BAH_UG0_BAH_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_UG_BAT_UG0_BAT_VALUE             ( 0x3FF )
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_UG_BAT_UG0_BAT_VALUE_RESET_VALUE ( 0x3FF )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_OFFSET ( 0x00000064 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG5_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG5_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG5_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG5_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG5_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG5_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG6_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG6  Ths register also holds UG6 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_RSV2_RSV_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_RSV2_RSV_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_UG_BAH_UG0_BAH_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_UG_BAH_UG0_BAH_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_UG_BAT_UG0_BAT_VALUE             ( 0x3FF )
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_UG_BAT_UG0_BAT_VALUE_RESET_VALUE ( 0x3FF )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_OFFSET ( 0x00000068 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG6_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG6_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG6_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG6_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG6_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG6_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* UG7_Threshold                                                                         */
+/* Threshold for Allocated Buffers of UG7  Ths register also holds UG6 hysteresis value  */
+/* for ACK/NACK transition setting                                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_RSV2_RSV_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_RSV2_RSV_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_UG_BAH_UG0_BAH_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_UG_BAH_UG0_BAH_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_UG_BAT_UG0_BAT_VALUE             ( 0x3FF )
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_UG_BAT_UG0_BAT_VALUE_RESET_VALUE ( 0x3FF )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_OFFSET ( 0x0000006C )
+
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG7_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG7_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG7_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG7_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG7_TRSH ;
+#else
+typedef struct
+{	uint32_t ug_bat	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAT */
+	uint32_t rsv   	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t ug_bah	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_BAH */
+	uint32_t rsv2  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG7_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_map_register_0                                                             */
+/* Each Source Port is mapped to specified UG. This register is using for mapping of SP  */
+/* to UG0…7                                                                              */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_EMAC3_EMAC3_MAP_VALUE             ( 0x7 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_EMAC3_EMAC3_MAP_VALUE_RESET_VALUE ( 0x7 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_EMAC2_EMAC2_MAP_VALUE             ( 0x6 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_EMAC2_EMAC2_MAP_VALUE_RESET_VALUE ( 0x6 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_EMAC1_EMAC2_MAP_VALUE             ( 0x5 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_EMAC1_EMAC2_MAP_VALUE_RESET_VALUE ( 0x5 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_EMAC0_EMAC0_MAP_VALUE             ( 0x4 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_EMAC0_EMAC0_MAP_VALUE_RESET_VALUE ( 0x4 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_GPON_GPON_MAP_VALUE               ( 0x3 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_GPON_GPON_MAP_VALUE_RESET_VALUE   ( 0x3 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_RNRB_RNR_B_MAP_VALUE              ( 0x2 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_RNRB_RNR_B_MAP_VALUE_RESET_VALUE  ( 0x2 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_RNRA_RNR_A_MAP_VALUE              ( 0x1 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_RNRA_RNR_A_MAP_VALUE_RESET_VALUE  ( 0x1 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_CPU_CPU_MAP_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_CPU_CPU_MAP_VALUE_RESET_VALUE     ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_OFFSET ( 0x00000070 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG_MAP_0_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG_MAP_0_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG_MAP_0_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG_MAP_0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* EMAC3_mapping */
+	uint32_t emac3	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC2_mapping */
+	uint32_t emac2	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC1_mapping */
+	uint32_t emac1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC0_mapping */
+	uint32_t emac0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_mapping */
+	uint32_t gpon 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_B_mapping */
+	uint32_t rnrb 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_A_mapping */
+	uint32_t rnra 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CPU_mapping */
+	uint32_t cpu  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG_MAP_0 ;
+#else
+typedef struct
+{	uint32_t cpu  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CPU_mapping */
+	uint32_t rnra 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_A_mapping */
+	uint32_t rnrb 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RNR_B_mapping */
+	uint32_t gpon 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPON_mapping */
+	uint32_t emac0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC0_mapping */
+	uint32_t emac1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC1_mapping */
+	uint32_t emac2	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC2_mapping */
+	uint32_t emac3	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC3_mapping */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG_MAP_0 ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_dbg                                                                              */
+/* SBPM select the debug bus                                                             */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_DBG_RSV_RSV_VALUE                           ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_RSV_RSV_VALUE_RESET_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_SEL_DBG_DEFUALT_VALUE_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_SEL_DBG_DEFUALT_VALUE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_DBG_OFFSET ( 0x00000074 )
+
+#define SBPM_BLOCK_REGS_SBPM_DBG_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_DBG_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_DBG_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_DBG_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_DBG_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_DBG_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* select */
+	uint32_t sel	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_DBG ;
+#else
+typedef struct
+{	uint32_t sel	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* select */
+	uint32_t rsv	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_DBG ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG0_BAC                                                                          */
+/* SBPM UG0 allocated BN counter                                                         */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG0_BAC_RSV_RSV_VALUE                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_BAC_RSV_RSV_VALUE_RESET_VALUE    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_BAC_UG0BAC_BAC_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_BAC_UG0BAC_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG0_BAC_OFFSET ( 0x00000078 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG0_BAC_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG0_BAC_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG0_BAC_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG0_BAC_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG0_BAC_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG0_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAC */
+	uint32_t ug0bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG0_BAC ;
+#else
+typedef struct
+{	uint32_t ug0bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_BAC */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG0_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG1_BAC                                                                          */
+/* SBPM UG1 allocated BN Counter                                                         */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG1_BAC_RSV_RSV_VALUE                   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_BAC_RSV_RSV_VALUE_RESET_VALUE       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_BAC_UG1BAC_UG1BAC_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_BAC_UG1BAC_UG1BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG1_BAC_OFFSET ( 0x0000007C )
+
+#define SBPM_BLOCK_REGS_SBPM_UG1_BAC_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG1_BAC_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG1_BAC_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG1_BAC_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG1_BAC_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG1_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t ug1bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG1_BAC ;
+#else
+typedef struct
+{	uint32_t ug1bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG1_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG2_BAC                                                                          */
+/* SBPM UG2 allocated BN Counter                                                         */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG2_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_BAC_UG2BAC_UG2_BAC_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_BAC_UG2BAC_UG2_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG2_BAC_OFFSET ( 0x00000080 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG2_BAC_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG2_BAC_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG2_BAC_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG2_BAC_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG2_BAC_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG2_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t ug2bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG2_BAC ;
+#else
+typedef struct
+{	uint32_t ug2bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG2_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG3_BAC                                                                          */
+/* SBPM UG3 allocated BN Counter                                                         */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG3_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_BAC_UG3BAC_UG3_BAC_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_BAC_UG3BAC_UG3_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG3_BAC_OFFSET ( 0x00000084 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG3_BAC_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG3_BAC_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG3_BAC_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG3_BAC_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG3_BAC_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG3_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG3_BAC */
+	uint32_t ug3bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG3_BAC ;
+#else
+typedef struct
+{	uint32_t ug3bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG3_BAC */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG3_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG4_BAC                                                                          */
+/* SBPM UG4 allocated BN Counter                                                         */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG4_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_BAC_UG4BAC_UG4_BAC_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_BAC_UG4BAC_UG4_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG4_BAC_OFFSET ( 0x00000088 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG4_BAC_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG4_BAC_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG4_BAC_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG4_BAC_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG4_BAC_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG4_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t ug4bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG4_BAC ;
+#else
+typedef struct
+{	uint32_t ug4bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG4_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG5_BAC                                                                          */
+/* SBPM UG5 allocated BN Counter                                                         */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG5_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_BAC_UG5BAC_UG5_BAC_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_BAC_UG5BAC_UG5_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG5_BAC_OFFSET ( 0x0000008C )
+
+#define SBPM_BLOCK_REGS_SBPM_UG5_BAC_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG5_BAC_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG5_BAC_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG5_BAC_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG5_BAC_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG5_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t ug5bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG5_BAC ;
+#else
+typedef struct
+{	uint32_t ug5bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG5_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG6_BAC                                                                          */
+/* SBPM UG6 allocated BN Counter                                                         */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG6_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_BAC_UG6BAC_UG6_BAC_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_BAC_UG6BAC_UG6_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG6_BAC_OFFSET ( 0x00000090 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG6_BAC_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG6_BAC_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG6_BAC_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG6_BAC_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG6_BAC_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG6_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t ug6bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG6_BAC ;
+#else
+typedef struct
+{	uint32_t ug6bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG6_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG7_BAC                                                                          */
+/* SBPM UG7 allocated BN Counter                                                         */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG7_BAC_RSV_RSV_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_BAC_RSV_RSV_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_BAC_UG7BAC_UG7_BAC_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_BAC_UG7BAC_UG7_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG7_BAC_OFFSET ( 0x00000094 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG7_BAC_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG7_BAC_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG7_BAC_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG7_BAC_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG7_BAC_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG7_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t ug7bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG7_BAC ;
+#else
+typedef struct
+{	uint32_t ug7bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv   	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG7_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_GL_BAC                                                                           */
+/* SBPM global BN Counter                                                                */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_GL_BAC_RSV_RSV_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_GL_BAC_RSV_RSV_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_GL_BAC_BAC_BAC_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_GL_BAC_BAC_BAC_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_GL_BAC_OFFSET ( 0x00000098 )
+
+#define SBPM_BLOCK_REGS_SBPM_GL_BAC_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_GL_BAC_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_GL_BAC_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_GL_BAC_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_GL_BAC_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_GL_BAC_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_GL_BAC ;
+#else
+typedef struct
+{	uint32_t bac	: 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BAC */
+	uint32_t rsv	: 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_GL_BAC ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG0_Exclusive_threshold                                                          */
+/* SBPM UG0 Exclusive high and hysteresis threshold                                      */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_RSV2_RSV2_VALUE                                                            ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_RSV2_RSV2_VALUE_RESET_VALUE                                                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_RSV_RSV_VALUE                                                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_RSV_RSV_VALUE_RESET_VALUE                                                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE                 ( 0x300 )
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE     ( 0x300 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_OFFSET ( 0x0000009C )
+
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG1_Exclusive_threshold                                                          */
+/* SBPM UG1 Exclusive high and hysteresis threshold                                      */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_RSV2_RSV2_VALUE                                                            ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_RSV2_RSV2_VALUE_RESET_VALUE                                                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_RSV_RSV_VALUE                                                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_RSV_RSV_VALUE_RESET_VALUE                                                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE                 ( 0x300 )
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE     ( 0x300 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_OFFSET ( 0x00000100 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG2_Exclusive_threshold                                                          */
+/* SBPM UG2 Exclusive high and hysteresis threshold                                      */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_RSV2_RSV2_VALUE                                                            ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_RSV2_RSV2_VALUE_RESET_VALUE                                                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_RSV_RSV_VALUE                                                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_RSV_RSV_VALUE_RESET_VALUE                                                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE                 ( 0x300 )
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE     ( 0x300 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_OFFSET ( 0x00000104 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG3_Exclusive_threshold                                                          */
+/* SBPM UG3 Exclusive high and hysteresis threshold                                      */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_RSV2_RSV2_VALUE                                                            ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_RSV2_RSV2_VALUE_RESET_VALUE                                                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_RSV_RSV_VALUE                                                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_RSV_RSV_VALUE_RESET_VALUE                                                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE                 ( 0x300 )
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE     ( 0x300 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_OFFSET ( 0x00000108 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG4_Exclusive_threshold                                                          */
+/* SBPM UG4 Exclusive high and hysteresis threshold                                      */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_RSV2_RSV2_VALUE                                                            ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_RSV2_RSV2_VALUE_RESET_VALUE                                                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_RSV_RSV_VALUE                                                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_RSV_RSV_VALUE_RESET_VALUE                                                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE                 ( 0x300 )
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE     ( 0x300 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_OFFSET ( 0x0000010C )
+
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG5_Exclusive_threshold                                                          */
+/* SBPM UG5 Exclusive high and hysteresis threshold                                      */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_RSV2_RSV2_VALUE                                                            ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_RSV2_RSV2_VALUE_RESET_VALUE                                                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_RSV_RSV_VALUE                                                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_RSV_RSV_VALUE_RESET_VALUE                                                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE                 ( 0x300 )
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE     ( 0x300 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_OFFSET ( 0x00000110 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG6_Exclusive_threshold                                                          */
+/* SBPM UG6 Exclusive high and hysteresis threshold                                      */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_RSV2_RSV2_VALUE                                                            ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_RSV2_RSV2_VALUE_RESET_VALUE                                                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_RSV_RSV_VALUE                                                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_RSV_RSV_VALUE_RESET_VALUE                                                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE                 ( 0x300 )
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE     ( 0x300 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_OFFSET ( 0x00000114 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_UG7_Exclusive_threshold                                                          */
+/* SBPM UG7 Exclusive high and hysteresis threshold                                      */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_RSV2_RSV2_VALUE                                                            ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_RSV2_RSV2_VALUE_RESET_VALUE                                                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE             ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_EXCLH_EXCLUSIVE_HYSTERES_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE ( 0x100 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_RSV_RSV_VALUE                                                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_RSV_RSV_VALUE_RESET_VALUE                                                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE                 ( 0x300 )
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_EXCLT_EXCLUSIVE_HIGH_THRESHOLD_FOR_ALLOCATED_BUFFERS_VALUE_RESET_VALUE     ( 0x300 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_OFFSET ( 0x00000118 )
+
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH ;
+#else
+typedef struct
+{	uint32_t exclt	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_high_threshold */
+	uint32_t rsv  	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t exclh	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* exclusive_histeresis_threshold */
+	uint32_t rsv2 	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_Status_register                                                            */
+/* This register is status set of all 8 Ugs: Ack/NACK state and in addition Exclusive st */
+/* ate pereach of 8 UGs                                                                  */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_RSV2_RSV_VALUE                         ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_RSV2_RSV_VALUE_RESET_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_UG_EXCL_STTS_UG_STAT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_UG_EXCL_STTS_UG_STAT_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_RSV1_RSV_VALUE                         ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_RSV1_RSV_VALUE_RESET_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_UG_ACK_STTS_UG_STAT_VALUE              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_UG_ACK_STTS_UG_STAT_VALUE_RESET_VALUE  ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_OFFSET ( 0x0000011C )
+
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_UG_STATUS_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_UG_STATUS_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_UG_STATUS_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_UG_STATUS_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv2        	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_EXCL_STTS */
+	uint32_t ug_excl_stts	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1        	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_ACK_STTS */
+	uint32_t ug_ack_stts 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG_STATUS ;
+#else
+typedef struct
+{	uint32_t ug_ack_stts 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_ACK_STTS */
+	uint32_t rsv1        	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t ug_excl_stts	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG_EXCL_STTS */
+	uint32_t rsv2        	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_UG_STATUS ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_runner_status_message_control_register                                           */
+/* BPM runner status message control register                                            */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_RSV_DEFAULT_VALUE                                                                          ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_RSV_DEFAULT_VALUE_RESET_VALUE                                                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_RNR_STAT_MSG_BASE_ADDR_BASE_ADDRESS_IN_RUNNER_FOR_STATUS_MESSAGE_SENDING_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_RNR_STAT_MSG_BASE_ADDR_BASE_ADDRESS_IN_RUNNER_FOR_STATUS_MESSAGE_SENDING_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_RNR_NUM_RUNNER_A_VALUE                                                                     ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_RNR_NUM_RUNNER_A_VALUE_RESET_VALUE                                                         ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_RNR_NUM_RUNNER_B_VALUE                                                                     ( 0x1 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_STAT_MSG_EN_DEFAULT_VALUE                                                                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_STAT_MSG_EN_DEFAULT_VALUE_RESET_VALUE                                                      ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_STAT_WKUP_EN_DEFAULT_VALUE                                                                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_STAT_WKUP_EN_DEFAULT_VALUE_RESET_VALUE                                                     ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_TASK_NUM_DEFAULT_VALUE                                                                     ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_TASK_NUM_DEFAULT_VALUE_RESET_VALUE                                                         ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_OFFSET ( 0x00000120 )
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* runner_status_message_base_addr */
+	uint32_t rnr_stat_msg_base_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_num */
+	uint32_t rnr_num               	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* send_status_message_enable */
+	uint32_t stat_msg_en           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* send_status_Wake_Up_enable */
+	uint32_t stat_wkup_en          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t task_num              	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL ;
+#else
+typedef struct
+{	uint32_t task_num              	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t stat_wkup_en          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* send_status_Wake_Up_enable */
+	uint32_t stat_msg_en           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* send_status_message_enable */
+	uint32_t rnr_num               	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_num */
+	uint32_t rnr_stat_msg_base_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* runner_status_message_base_addr */
+	uint32_t rsv                   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL ;
+#endif
+
+/*****************************************************************************************/
+/* Runner_Target_address_for_Reply_message                                               */
+/* Runner Target address for Reply message as results of Alloc request from Runner. The  */
+/* register is  for runner A and B                                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_RSV_DEFAULT_VALUE                                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_RSV_DEFAULT_VALUE_RESET_VALUE                     ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_RNR_REPLY_MSG_BASE_ADDR_DEFAULT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_RNR_REPLY_MSG_BASE_ADDR_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_OFFSET ( 0x00000124 )
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                    	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Target_address_for_Runner_A_B */
+	uint32_t rnr_reply_msg_base_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA ;
+#else
+typedef struct
+{	uint32_t rnr_reply_msg_base_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Target_address_for_Runner_A_B */
+	uint32_t rsv                    	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA ;
+#endif
+
+/*****************************************************************************************/
+/* sbpm_rnr_wkup_rply_set_0                                                              */
+/* sbpm_rnr_wkup_rply_set 0                                                              */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_RSV_DEFAULT_VALUE                             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_RSV_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_MCST_WAKE_UP_EN_DEFAULT_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_MCST_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_GET_NEXT_WAKE_UP_EN_DEFAULT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_GET_NEXT_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_CONNECT_WAKE_UP_EN_DEFAULT_VALUE              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_CONNECT_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_ALLOC_WAKE_UP_EN_DEFAULT_VALUE                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_ALLOC_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_TASK_NUM_DEFAULT_VALUE                        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_TASK_NUM_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_OFFSET ( 0x00000128 )
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_wake_up_en */
+	uint32_t mcst_wake_up_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next_wake_up_en */
+	uint32_t get_next_wake_up_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_wake_up_en */
+	uint32_t connect_wake_up_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_wake_up_en */
+	uint32_t alloc_wake_up_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t task_num           	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0 ;
+#else
+typedef struct
+{	uint32_t task_num           	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t alloc_wake_up_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_wake_up_en */
+	uint32_t connect_wake_up_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_wake_up_en */
+	uint32_t get_next_wake_up_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next_wake_up_en */
+	uint32_t mcst_wake_up_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_wake_up_en */
+	uint32_t rsv                	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0 ;
+#endif
+
+/*****************************************************************************************/
+/* sbpm_rnr_wkup_rply_set_1                                                              */
+/* sbpm_rnr_wkup_rply_set 1                                                              */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_RSV_DEFAULT_VALUE                             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_RSV_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_MCST_WAKE_UP_EN_DEFAULT_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_MCST_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_GET_NEXT_WAKE_UP_EN_DEFAULT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_GET_NEXT_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_CONNECT_WAKE_UP_EN_DEFAULT_VALUE              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_CONNECT_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_ALLOC_WAKE_UP_EN_DEFAULT_VALUE                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_ALLOC_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_TASK_NUM_DEFAULT_VALUE                        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_TASK_NUM_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_OFFSET ( 0x0000012C )
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_wake_up_en */
+	uint32_t mcst_wake_up_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next_wake_up_en */
+	uint32_t get_next_wake_up_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_wake_up_en */
+	uint32_t connect_wake_up_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_wake_up_en */
+	uint32_t alloc_wake_up_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t task_num           	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1 ;
+#else
+typedef struct
+{	uint32_t task_num           	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t alloc_wake_up_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_wake_up_en */
+	uint32_t connect_wake_up_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_wake_up_en */
+	uint32_t get_next_wake_up_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next_wake_up_en */
+	uint32_t mcst_wake_up_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_wake_up_en */
+	uint32_t rsv                	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1 ;
+#endif
+
+/*****************************************************************************************/
+/* sbpm_rnr_wkup_rply_set_2                                                              */
+/* sbpm_rnr_wkup_rply_set 2                                                              */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_RSV_DEFAULT_VALUE                             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_RSV_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_MCST_WAKE_UP_EN_DEFAULT_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_MCST_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_GET_NEXT_WAKE_UP_EN_DEFAULT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_GET_NEXT_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_CONNECT_WAKE_UP_EN_DEFAULT_VALUE              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_CONNECT_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_ALLOC_WAKE_UP_EN_DEFAULT_VALUE                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_ALLOC_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_TASK_NUM_DEFAULT_VALUE                        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_TASK_NUM_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_OFFSET ( 0x00000130 )
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_wake_up_en */
+	uint32_t mcst_wake_up_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next_wake_up_en */
+	uint32_t get_next_wake_up_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_wake_up_en */
+	uint32_t connect_wake_up_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_wake_up_en */
+	uint32_t alloc_wake_up_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t task_num           	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2 ;
+#else
+typedef struct
+{	uint32_t task_num           	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t alloc_wake_up_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_wake_up_en */
+	uint32_t connect_wake_up_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_wake_up_en */
+	uint32_t get_next_wake_up_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next_wake_up_en */
+	uint32_t mcst_wake_up_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_wake_up_en */
+	uint32_t rsv                	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2 ;
+#endif
+
+/*****************************************************************************************/
+/* sbpm_rnr_wkup_rply_set_3                                                              */
+/* sbpm_rnr_wkup_rply_set 3                                                              */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_RSV_DEFAULT_VALUE                             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_RSV_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_MCST_WAKE_UP_EN_DEFAULT_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_MCST_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_GET_NEXT_WAKE_UP_EN_DEFAULT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_GET_NEXT_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_CONNECT_WAKE_UP_EN_DEFAULT_VALUE              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_CONNECT_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_ALLOC_WAKE_UP_EN_DEFAULT_VALUE                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_ALLOC_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_TASK_NUM_DEFAULT_VALUE                        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_TASK_NUM_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_OFFSET ( 0x00000134 )
+
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_wake_up_en */
+	uint32_t mcst_wake_up_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next_wake_up_en */
+	uint32_t get_next_wake_up_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_wake_up_en */
+	uint32_t connect_wake_up_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_wake_up_en */
+	uint32_t alloc_wake_up_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t task_num           	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3 ;
+#else
+typedef struct
+{	uint32_t task_num           	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t alloc_wake_up_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_wake_up_en */
+	uint32_t connect_wake_up_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_wake_up_en */
+	uint32_t get_next_wake_up_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next_wake_up_en */
+	uint32_t mcst_wake_up_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_wake_up_en */
+	uint32_t rsv                	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3 ;
+#endif
+
+/*****************************************************************************************/
+/* error_handling_params                                                                 */
+/* Parameters and thresholds used for Error handling: error detection, max search enable */
+/*  and threshold, etc.                                                                  */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_RSV_RESERVED_VALUE                            ( 0x0 )
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_RSV_RESERVED_VALUE_RESET_VALUE                ( 0x0 )
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_FREEZE_EN_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_FREEZE_EN_VALUE_RESET_VALUE   ( 0x0 )
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_CHCK_LAST_EN_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_CHCK_LAST_EN_VALUE_RESET_VALUE   ( 0x0 )
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_MAX_SEARCH_EN_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_MAX_SEARCH_EN_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_SEARCH_DEPTH_VALUE               ( 0x4 )
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_SEARCH_DEPTH_VALUE_RESET_VALUE   ( 0x4 )
+
+
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_OFFSET ( 0x00000138 )
+
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_OFFSET )
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t rsv            	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* freeze_in_error */
+	uint32_t freeze_in_error	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* chck_last_en */
+	uint32_t chck_last_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* max_search_en */
+	uint32_t max_search_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* search_depth */
+	uint32_t search_depth   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS ;
+#else
+typedef struct
+{	uint32_t search_depth   	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* search_depth */
+	uint32_t max_search_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* max_search_en */
+	uint32_t chck_last_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* chck_last_en */
+	uint32_t freeze_in_error	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* freeze_in_error */
+	uint32_t rsv            	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_ISR                                                                              */
+/* SBPM ISR (Interrupt Status register)                                                  */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_ISR_RSV_RESERVED_VALUE                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ISR_RSV_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ISR_MAX_SEARCH_ERR_MAX_SEARCH_ERR_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ISR_MAX_SEARCH_ERR_MAX_SEARCH_ERR_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ISR_CHECK_LAST_ERR_CHECK_LAST_ERR_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ISR_CHECK_LAST_ERR_CHECK_LAST_ERR_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ISR_MCST_OVERFLOW_MC_OVERFLOW_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ISR_MCST_OVERFLOW_MC_OVERFLOW_VALUE_RESET_VALUE     ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ISR_BAC_UNDERRUN_BAC_UNDERRUN_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ISR_BAC_UNDERRUN_BAC_UNDERRUN_VALUE_RESET_VALUE     ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_ISR_OFFSET ( 0x0000013C )
+
+#define SBPM_BLOCK_REGS_SBPM_ISR_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_ISR_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_ISR_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_ISR_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_ISR_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_ISR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t rsv           	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* max_search_err */
+	uint32_t max_search_err	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* check_last_err */
+	uint32_t check_last_err	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_overflow */
+	uint32_t mcst_overflow 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bac_underrun */
+	uint32_t bac_underrun  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_ISR ;
+#else
+typedef struct
+{	uint32_t bac_underrun  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bac_underrun */
+	uint32_t mcst_overflow 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_overflow */
+	uint32_t check_last_err	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* check_last_err */
+	uint32_t max_search_err	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* max_search_err */
+	uint32_t rsv           	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_ISR ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_IER                                                                              */
+/* SBPM IER (Interrupt Enable register)                                                  */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_IER_RSV_RESRVED_VALUE                                           ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IER_RSV_RESRVED_VALUE_RESET_VALUE                               ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IER_NULL_CONNECT_IRQ_EN_NULL_CONNECT_IRQ_EN_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IER_NULL_CONNECT_IRQ_EN_NULL_CONNECT_IRQ_EN_VALUE_RESET_VALUE   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IER_MAX_SRCH_ERR_IRQ_EN_MAX_SRCH_ERR_IRQ_EN_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IER_MAX_SRCH_ERR_IRQ_EN_MAX_SRCH_ERR_IRQ_EN_VALUE_RESET_VALUE   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IER_LAST_ERR_IRQ_EN_LAST_ERR_IRQ_EN_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IER_LAST_ERR_IRQ_EN_LAST_ERR_IRQ_EN_VALUE_RESET_VALUE           ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IER_MCST_OVERFLW_IRQ_EN__MCST_OVERFLW_IRQ_EN__VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IER_MCST_OVERFLW_IRQ_EN__MCST_OVERFLW_IRQ_EN__VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IER_BAC_UNDERRUN_IRQ_EN_BAC_UNDERRUN_IRQ_EN_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IER_BAC_UNDERRUN_IRQ_EN_BAC_UNDERRUN_IRQ_EN_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_IER_OFFSET ( 0x00000140 )
+
+#define SBPM_BLOCK_REGS_SBPM_IER_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_IER_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_IER_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_IER_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_IER_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_IER_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t rsv                 	: 27 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* null_connect_irq_en */
+	uint32_t null_connect_irq_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* max_srch_err_irq_en */
+	uint32_t max_srch_err_irq_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* last_err_irq_en */
+	uint32_t last_err_irq_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_overflow_irq_en */
+	uint32_t mcst_overflw_irq_en_	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bac_underrun_irq_en */
+	uint32_t bac_underrun_irq_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_IER ;
+#else
+typedef struct
+{	uint32_t bac_underrun_irq_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bac_underrun_irq_en */
+	uint32_t mcst_overflw_irq_en_	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_overflow_irq_en */
+	uint32_t last_err_irq_en     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* last_err_irq_en */
+	uint32_t max_srch_err_irq_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* max_srch_err_irq_en */
+	uint32_t null_connect_irq_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* null_connect_irq_en */
+	uint32_t rsv                 	: 27 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_IER ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_ITR                                                                              */
+/* SBPM ITR (Interrupt test register)                                                    */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_ITR_RSV_RSV_VALUE                                                   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ITR_RSV_RSV_VALUE_RESET_VALUE                                       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ITR_MAX_SRCH_ERR_TEST_IRQ_MAX_SRCH_ERR_TEST_IRQ_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ITR_MAX_SRCH_ERR_TEST_IRQ_MAX_SRCH_ERR_TEST_IRQ_VALUE_RESET_VALUE   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ITR_LAST_ERR_TEST_IRQ_LAST_ERR_TEST_IRQ_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ITR_LAST_ERR_TEST_IRQ_LAST_ERR_TEST_IRQ_VALUE_RESET_VALUE           ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ITR_MCST_OVERFLOW_TEST_IRQ_MCST_OVERFLOW_TEST_IRQ_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ITR_MCST_OVERFLOW_TEST_IRQ_MCST_OVERFLOW_TEST_IRQ_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ITR_BAC_UNDERRUN_TEST_IRQ_BAC_UNDERRUN_TEST_IRQ_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_ITR_BAC_UNDERRUN_TEST_IRQ_BAC_UNDERRUN_TEST_IRQ_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_ITR_OFFSET ( 0x00000144 )
+
+#define SBPM_BLOCK_REGS_SBPM_ITR_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_ITR_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_ITR_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_ITR_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_ITR_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_ITR_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t rsv                   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* max_srch_err_test_irq */
+	uint32_t max_srch_err_test_irq 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* last_err_test_irq */
+	uint32_t last_err_test_irq     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_overflow_test_irq */
+	uint32_t mcst_overflow_test_irq	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bac_underrun_test_irq */
+	uint32_t bac_underrun_test_irq 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_ITR ;
+#else
+typedef struct
+{	uint32_t bac_underrun_test_irq 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bac_underrun_test_irq */
+	uint32_t mcst_overflow_test_irq	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_overflow_test_irq */
+	uint32_t last_err_test_irq     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* last_err_test_irq */
+	uint32_t max_srch_err_test_irq 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* max_srch_err_test_irq */
+	uint32_t rsv                   	: 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_ITR ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_IIR_low_register                                                                 */
+/* SBPM IIR low (Interrupt information register)                                         */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_IIR_LOW_CMD_DATA_22TO0_CMD_DATA_22_TO0_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IIR_LOW_CMD_DATA_22TO0_CMD_DATA_22_TO0_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IIR_LOW_CMD_TA_CMD_TA_VALUE                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IIR_LOW_CMD_TA_CMD_TA_VALUE_RESET_VALUE                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IIR_LOW_CMD_SA_CMD_SA_VALUE                              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IIR_LOW_CMD_SA_CMD_SA_VALUE_RESET_VALUE                  ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_IIR_LOW_OFFSET ( 0x00000148 )
+
+#define SBPM_BLOCK_REGS_SBPM_IIR_LOW_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_IIR_LOW_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_IIR_LOW_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_IIR_LOW_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_IIR_LOW_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_IIR_LOW_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* cmd_data_22to0 */
+	uint32_t cmd_data_22to0	: 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cmd_ta */
+	uint32_t cmd_ta        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cmd_sa */
+	uint32_t cmd_sa        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_IIR_LOW ;
+#else
+typedef struct
+{	uint32_t cmd_sa        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cmd_sa */
+	uint32_t cmd_ta        	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cmd_ta */
+	uint32_t cmd_data_22to0	: 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cmd_data_22to0 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_IIR_LOW ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_IIR_high_register                                                                */
+/* SBPM IIR high (Interrupt information register)                                        */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_IIR_HIGH_RSV_CMD_UG_VALUE                                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IIR_HIGH_RSV_CMD_UG_VALUE_RESET_VALUE                      ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IIR_HIGH_CMD_DATA_23TO42_CMD_DATA_23TO39_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_IIR_HIGH_CMD_DATA_23TO42_CMD_DATA_23TO39_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_IIR_HIGH_OFFSET ( 0x0000014C )
+
+#define SBPM_BLOCK_REGS_SBPM_IIR_HIGH_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_IIR_HIGH_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_IIR_HIGH_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_IIR_HIGH_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_IIR_HIGH_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_IIR_HIGH_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv            	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cmd_data_23to39 */
+	uint32_t cmd_data_23to42	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_IIR_HIGH ;
+#else
+typedef struct
+{	uint32_t cmd_data_23to42	: 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* cmd_data_23to39 */
+	uint32_t rsv            	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_IIR_HIGH ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_DBG_VEC0                                                                         */
+/* SBPM debug vector0 includes 21 bit of control/state machine of CMD pipe               */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_RSV_RESERVED_VALUE                      ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_RSV_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_RX_FIFO_SA_SA_VALUE                     ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_RX_FIFO_SA_SA_VALUE_RESET_VALUE         ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_GN_CNXT_SM_STATE_VALUE                  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_GN_CNXT_SM_STATE_VALUE_RESET_VALUE      ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_STATE_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_STATE_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_STATE_VALUE              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_STATE_VALUE_RESET_VALUE  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_MCINT_SM_STATE_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_MCINT_SM_STATE_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_CNNCT_SM_STATE_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_CNNCT_SM_STATE_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_ALLOC_SM_STATE_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_ALLOC_SM_STATE_VALUE_RESET_VALUE        ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_OFFSET ( 0x00000150 )
+
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_DBG_VEC0_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_DBG_VEC0_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC0_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_DBG_VEC0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t rsv            	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RX_FIFO_SA */
+	uint32_t rx_fifo_sa     	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GN_CNXT_SM */
+	uint32_t gn_cnxt_sm     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FREE_WO_CNXT_SM */
+	uint32_t free_wo_cnxt_sm	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FREE_W_CNXT_SM */
+	uint32_t free_w_cnxt_sm 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MCINC_SM */
+	uint32_t mcint_sm       	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CNNCT_SM */
+	uint32_t cnnct_sm       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ALLOC_SM */
+	uint32_t alloc_sm       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_DBG_VEC0 ;
+#else
+typedef struct
+{	uint32_t alloc_sm       	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ALLOC_SM */
+	uint32_t cnnct_sm       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CNNCT_SM */
+	uint32_t mcint_sm       	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MCINC_SM */
+	uint32_t free_w_cnxt_sm 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FREE_W_CNXT_SM */
+	uint32_t free_wo_cnxt_sm	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* FREE_WO_CNXT_SM */
+	uint32_t gn_cnxt_sm     	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GN_CNXT_SM */
+	uint32_t rx_fifo_sa     	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RX_FIFO_SA */
+	uint32_t rsv            	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_DBG_VEC0 ;
+#endif
+
+/*****************************************************************************************/
+/* SBPM_DBG_VEC1                                                                         */
+/* SBPM debug vector1 includes 21 bit of control/state machine of CMD pipe  				         */
+/*                                                                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC1_RSV_RESERVED_VALUE                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC1_RSV_RESERVED_VALUE_RESET_VALUE    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_SA_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_SA_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC1_RX_FIFO_TA_SA_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC1_RX_FIFO_TA_SA_VALUE_RESET_VALUE   ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC1_OFFSET ( 0x00000154 )
+
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC1_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_DBG_VEC1_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC1_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_DBG_VEC1_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_DBG_VEC1_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_DBG_VEC1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t rsv         	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RX_FIFO_DATA */
+	uint32_t rx_fifo_data	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RX_FIFO_TA */
+	uint32_t rx_fifo_ta  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_DBG_VEC1 ;
+#else
+typedef struct
+{	uint32_t rx_fifo_ta  	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RX_FIFO_TA */
+	uint32_t rx_fifo_data	: 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RX_FIFO_DATA */
+	uint32_t rsv         	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_DBG_VEC1 ;
+#endif
+
+/*****************************************************************************************/
+/* Route_Address0__config                                                                */
+/* Route Address 0 config includes ETH0/1 RX/TX                                          */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_RADDR_0_RSV4_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_0_RSV4_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_0_ETH1_TX_RADDR_ETH1_TX_RADDR_VALUE             ( 0x2F )
+#define SBPM_BLOCK_REGS_RADDR_0_ETH1_TX_RADDR_ETH1_TX_RADDR_VALUE_RESET_VALUE ( 0x2F )
+#define SBPM_BLOCK_REGS_RADDR_0_RSV3_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_0_RSV3_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_0_ETH1_RX_RADDR_ETH1_RX_RADDR_VALUE             ( 0xF )
+#define SBPM_BLOCK_REGS_RADDR_0_ETH1_RX_RADDR_ETH1_RX_RADDR_VALUE_RESET_VALUE ( 0xF )
+#define SBPM_BLOCK_REGS_RADDR_0_RSV2_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_0_RSV2_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_0_ETH0_TX_RADDR_ETH0_TX_RADDR_VALUE             ( 0x3F )
+#define SBPM_BLOCK_REGS_RADDR_0_ETH0_TX_RADDR_ETH0_TX_RADDR_VALUE_RESET_VALUE ( 0x3F )
+#define SBPM_BLOCK_REGS_RADDR_0_RSV1_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_0_RSV1_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_0_ETH0_RX_RADDR_ETH0_RX_RADDR_VALUE             ( 0x1F )
+#define SBPM_BLOCK_REGS_RADDR_0_ETH0_RX_RADDR_ETH0_RX_RADDR_VALUE_RESET_VALUE ( 0x1F )
+
+
+#define SBPM_BLOCK_REGS_RADDR_0_OFFSET ( 0x00000158 )
+
+#define SBPM_BLOCK_REGS_RADDR_0_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_RADDR_0_OFFSET )
+#define SBPM_BLOCK_REGS_RADDR_0_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_RADDR_0_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_RADDR_0_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_RADDR_0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth1_tx_raddr */
+	uint32_t eth1_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth1_rx_raddr */
+	uint32_t eth1_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth0_tx_raddr */
+	uint32_t eth0_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth0_rx_raddr */
+	uint32_t eth0_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_RADDR_0 ;
+#else
+typedef struct
+{	uint32_t eth0_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth0_rx_raddr */
+	uint32_t rsv1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t eth0_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth0_tx_raddr */
+	uint32_t rsv2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t eth1_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth1_rx_raddr */
+	uint32_t rsv3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t eth1_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth1_tx_raddr */
+	uint32_t rsv4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_RADDR_0 ;
+#endif
+
+/*****************************************************************************************/
+/* Route_Address1__config                                                                */
+/* Route Address 1 config  includes ETH2/3 RX/TX reg                                     */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_RADDR_1_RSV4_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_1_RSV4_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_1_ETH3_TX_RADDR_ETH3_TX_RADDR_VALUE             ( 0x29 )
+#define SBPM_BLOCK_REGS_RADDR_1_ETH3_TX_RADDR_ETH3_TX_RADDR_VALUE_RESET_VALUE ( 0x29 )
+#define SBPM_BLOCK_REGS_RADDR_1_RSV3_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_1_RSV3_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_1_ETH3_RX_RADDR_ETH3_RX_ADDR_VALUE              ( 0x9 )
+#define SBPM_BLOCK_REGS_RADDR_1_ETH3_RX_RADDR_ETH3_RX_ADDR_VALUE_RESET_VALUE  ( 0x9 )
+#define SBPM_BLOCK_REGS_RADDR_1_RSV2_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_1_RSV2_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_1_ETH2_TX_RADDR_ETH2_TX_RADDR_VALUE             ( 0x37 )
+#define SBPM_BLOCK_REGS_RADDR_1_ETH2_TX_RADDR_ETH2_TX_RADDR_VALUE_RESET_VALUE ( 0x37 )
+#define SBPM_BLOCK_REGS_RADDR_1_RSV1_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_1_RSV1_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_1_ETH2_RX_RADDR_ETH2_RX_RADDR_VALUE             ( 0x17 )
+#define SBPM_BLOCK_REGS_RADDR_1_ETH2_RX_RADDR_ETH2_RX_RADDR_VALUE_RESET_VALUE ( 0x17 )
+
+
+#define SBPM_BLOCK_REGS_RADDR_1_OFFSET ( 0x0000015C )
+
+#define SBPM_BLOCK_REGS_RADDR_1_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_RADDR_1_OFFSET )
+#define SBPM_BLOCK_REGS_RADDR_1_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_RADDR_1_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_RADDR_1_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_RADDR_1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth3_tx_raddr */
+	uint32_t eth3_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth3_rx_raddr */
+	uint32_t eth3_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth2_tx_raddr */
+	uint32_t eth2_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth2_rx_raddr */
+	uint32_t eth2_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_RADDR_1 ;
+#else
+typedef struct
+{	uint32_t eth2_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth2_rx_raddr */
+	uint32_t rsv1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t eth2_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth2_tx_raddr */
+	uint32_t rsv2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t eth3_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth3_rx_raddr */
+	uint32_t rsv3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t eth3_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth3_tx_raddr */
+	uint32_t rsv4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_RADDR_1 ;
+#endif
+
+/*****************************************************************************************/
+/* Route_Address2__config                                                                */
+/* Route Address 2 config  includes GPON/ETH4 RX/Txreg                                   */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_RADDR_2_RSV4_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_2_RSV4_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_2_ETH4_TX_RADDR_ETH4_TX_RADDR_VALUE             ( 0x31 )
+#define SBPM_BLOCK_REGS_RADDR_2_ETH4_TX_RADDR_ETH4_TX_RADDR_VALUE_RESET_VALUE ( 0x31 )
+#define SBPM_BLOCK_REGS_RADDR_2_RSV3_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_2_RSV3_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_2_ETH4_RX_RADDR_ETH4_RX_ADDR_VALUE              ( 0x11 )
+#define SBPM_BLOCK_REGS_RADDR_2_ETH4_RX_RADDR_ETH4_RX_ADDR_VALUE_RESET_VALUE  ( 0x11 )
+#define SBPM_BLOCK_REGS_RADDR_2_RSV2_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_2_RSV2_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_2_GPON_TX_RADDR_GPON_TX_RADDR_VALUE             ( 0x21 )
+#define SBPM_BLOCK_REGS_RADDR_2_GPON_TX_RADDR_GPON_TX_RADDR_VALUE_RESET_VALUE ( 0x21 )
+#define SBPM_BLOCK_REGS_RADDR_2_RSV1_RSV_VALUE                                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_2_RSV1_RSV_VALUE_RESET_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_2_GPON_RX_RADDR_GPON_RX_RADDR_VALUE             ( 0x1 )
+#define SBPM_BLOCK_REGS_RADDR_2_GPON_RX_RADDR_GPON_RX_RADDR_VALUE_RESET_VALUE ( 0x1 )
+
+
+#define SBPM_BLOCK_REGS_RADDR_2_OFFSET ( 0x00000160 )
+
+#define SBPM_BLOCK_REGS_RADDR_2_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_RADDR_2_OFFSET )
+#define SBPM_BLOCK_REGS_RADDR_2_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_RADDR_2_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_RADDR_2_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_RADDR_2_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth4_tx_raddr */
+	uint32_t eth4_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth4_rx_raddr */
+	uint32_t eth4_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gpon_tx_raddr */
+	uint32_t gpon_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gpon_rx_raddr */
+	uint32_t gpon_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_RADDR_2 ;
+#else
+typedef struct
+{	uint32_t gpon_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gpon_rx_raddr */
+	uint32_t rsv1         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t gpon_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gpon_tx_raddr */
+	uint32_t rsv2         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t eth4_rx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth4_rx_raddr */
+	uint32_t rsv3         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t eth4_tx_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eth4_tx_raddr */
+	uint32_t rsv4         	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_RADDR_2 ;
+#endif
+
+/*****************************************************************************************/
+/* Route_Address3__config                                                                */
+/* Route Address 3 config  reg includes definition of route address of Runner A/B        */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_RADDR_3_RSV3_RSV_VALUE                            ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_3_RSV3_RSV_VALUE_RESET_VALUE                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_3_MIPSD_RADDR_MIPSD_RADDR_VALUE             ( 0x6 )
+#define SBPM_BLOCK_REGS_RADDR_3_MIPSD_RADDR_MIPSD_RADDR_VALUE_RESET_VALUE ( 0x6 )
+#define SBPM_BLOCK_REGS_RADDR_3_RSV2_RSV_VALUE                            ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_3_RSV2_RSV_VALUE_RESET_VALUE                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_3_RNRB_RADDR_RNRB_RADDR_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_3_RNRB_RADDR_RNRB_RADDR_VALUE_RESET_VALUE   ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_3_RSV1_RSV_VALUE                            ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_3_RSV1_RSV_VALUE_RESET_VALUE                ( 0x0 )
+#define SBPM_BLOCK_REGS_RADDR_3_RNRA_RADDR_RNRA_RADDR_VALUE               ( 0x2 )
+#define SBPM_BLOCK_REGS_RADDR_3_RNRA_RADDR_RNRA_RADDR_VALUE_RESET_VALUE   ( 0x2 )
+
+
+#define SBPM_BLOCK_REGS_RADDR_3_OFFSET ( 0x00000164 )
+
+#define SBPM_BLOCK_REGS_RADDR_3_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_RADDR_3_OFFSET )
+#define SBPM_BLOCK_REGS_RADDR_3_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_RADDR_3_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_RADDR_3_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_RADDR_3_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv3       	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mipsd_raddr */
+	uint32_t mipsd_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv2       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rnrb_raddr */
+	uint32_t rnrb_raddr 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rsv1       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rnra_raddr */
+	uint32_t rnra_raddr 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_RADDR_3 ;
+#else
+typedef struct
+{	uint32_t rnra_raddr 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rnra_raddr */
+	uint32_t rsv1       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t rnrb_raddr 	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rnrb_raddr */
+	uint32_t rsv2       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+	uint32_t mipsd_raddr	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mipsd_raddr */
+	uint32_t rsv3       	: 9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_RADDR_3 ;
+#endif
+
+/*****************************************************************************************/
+/* User_Group_mapping_register_1                                                         */
+/* Configuration of mappins source ports to User G                                       */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_SPARE1_SPARE1_MAP_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_SPARE1_SPARE1_MAP_VALUE_RESET_VALUE   ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_SPARE0_SPARE0_MAP_VALUE               ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_SPARE0_SPARE0_MAP_VALUE_RESET_VALUE   ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_USB1_USB_MAP_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_USB1_USB_MAP_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_USB0_USB_MAP_VALUE                    ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_USB0_USB_MAP_VALUE_RESET_VALUE        ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_PCIE1_PCIE1_MAP_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_PCIE1_PCIE1_MAP_VALUE_RESET_VALUE     ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_PCIE0_PCIE0_MAP_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_PCIE0_PCIE0_MAP_VALUE_RESET_VALUE     ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_MIPSD_EMAC4_MAPPING_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_MIPSD_EMAC4_MAPPING_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_EMAC4_EMAC4_MAPPING_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_EMAC4_EMAC4_MAPPING_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_OFFSET ( 0x00000168 )
+
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_UG_MAP_REG_1_OFFSET )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_UG_MAP_REG_1_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_UG_MAP_REG_1_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_UG_MAP_REG_1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* spare1_map */
+	uint32_t spare1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* spare0_map */
+	uint32_t spare0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USB1_map */
+	uint32_t usb1  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USB0_map */
+	uint32_t usb0  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE1_map */
+	uint32_t pcie1 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE0_map */
+	uint32_t pcie0 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MIPSD_map */
+	uint32_t mipsd 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC4_map */
+	uint32_t emac4 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_UG_MAP_REG_1 ;
+#else
+typedef struct
+{	uint32_t emac4 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* EMAC4_map */
+	uint32_t mipsd 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MIPSD_map */
+	uint32_t pcie0 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE0_map */
+	uint32_t pcie1 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* PCIE1_map */
+	uint32_t usb0  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USB0_map */
+	uint32_t usb1  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* USB1_map */
+	uint32_t spare0	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* spare0_map */
+	uint32_t spare1	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* spare1_map */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_UG_MAP_REG_1 ;
+#endif
+
+/*****************************************************************************************/
+/* MIPSD_Target_address_for_Reply_message                                                */
+/* MIPSD Target address for Reply message as results of Alloc request from MIPSD.        */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA_RSV_DEFAULT_VALUE                                   ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA_RSV_DEFAULT_VALUE_RESET_VALUE                       ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA_MIPSD_REPLY_MSG_BASE_ADDR_DEFAULT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA_MIPSD_REPLY_MSG_BASE_ADDR_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA_OFFSET ( 0x0000016C )
+
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                      	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Target_address_for_MIPSD */
+	uint32_t mipsd_reply_msg_base_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA ;
+#else
+typedef struct
+{	uint32_t mipsd_reply_msg_base_addr	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Target_address_for_MIPSD */
+	uint32_t rsv                      	: 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA ;
+#endif
+
+/*****************************************************************************************/
+/* sbpm_mipsd_wkup_rply_set                                                              */
+/* sbpm_mipsd_wkup_rply_set                                                              */
+/*****************************************************************************************/
+
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_RSV_DEFAULT_VALUE                             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_RSV_DEFAULT_VALUE_RESET_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_MCST_WAKE_UP_EN_DEFAULT_VALUE                 ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_MCST_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE     ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_GET_NEXT_WAKE_UP_EN_DEFAULT_VALUE             ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_GET_NEXT_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_CONNECT_WAKE_UP_EN_DEFAULT_VALUE              ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_CONNECT_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE  ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_ALLOC_WAKE_UP_EN_DEFAULT_VALUE                ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_ALLOC_WAKE_UP_EN_DEFAULT_VALUE_RESET_VALUE    ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_TASK_NUM_DEFAULT_VALUE                        ( 0x0 )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_TASK_NUM_DEFAULT_VALUE_RESET_VALUE            ( 0x0 )
+
+
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_OFFSET ( 0x00000170 )
+
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_ADDRESS   	( SBPM_BLOCK_REGS_ADDRESS + SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_OFFSET )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_READ( r ) 	READ_32( ( SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_ADDRESS ), (r) )
+#define SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_WRITE( v )	WRITE_32( ( SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* rsv */
+	uint32_t rsv                	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_wake_up_en */
+	uint32_t mcst_wake_up_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next_wake_up_en */
+	uint32_t get_next_wake_up_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_wake_up_en */
+	uint32_t connect_wake_up_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_wake_up_en */
+	uint32_t alloc_wake_up_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t task_num           	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET ;
+#else
+typedef struct
+{	uint32_t task_num           	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* task_number */
+	uint32_t alloc_wake_up_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* alloc_wake_up_en */
+	uint32_t connect_wake_up_en 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* connect_wake_up_en */
+	uint32_t get_next_wake_up_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next_wake_up_en */
+	uint32_t mcst_wake_up_en    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_wake_up_en */
+	uint32_t rsv                	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* rsv */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET ;
+#endif
+
+typedef struct
+{
+	/* init_free_list */
+	SBPM_BLOCK_REGS_INIT_FREE_LIST init_free_list __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_alloc */
+	SBPM_BLOCK_REGS_BN_ALLOC bn_alloc __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_alloc_rply */
+	SBPM_BLOCK_REGS_BN_ALLOC_RPLY bn_alloc_rply __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_free_with_contxt_low */
+	SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_LOW bn_free_with_contxt_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_free_with_contxt_high */
+	SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_HIGH bn_free_with_contxt_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_inc */
+	SBPM_BLOCK_REGS_MCST_INC mcst_inc __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mcst_inc_rply */
+	SBPM_BLOCK_REGS_MCST_INC_RPLY mcst_inc_rply __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_connect */
+	SBPM_BLOCK_REGS_BN_CONNECT bn_connect __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_connect_rply */
+	SBPM_BLOCK_REGS_BN_CONNECT_RPLY bn_connect_rply __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next */
+	SBPM_BLOCK_REGS_GET_NEXT get_next __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* get_next_rply */
+	SBPM_BLOCK_REGS_GET_NEXT_RPLY get_next_rply __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 12 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_free_without_contxt */
+	SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT bn_free_without_contxt __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_free_without_contxt_rply */
+	SBPM_BLOCK_REGS_BN_FREE_WITHOUT_CONTXT_RPLY bn_free_without_contxt_rply __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* bn_free_with_contxt_rply */
+	SBPM_BLOCK_REGS_BN_FREE_WITH_CONTXT_RPLY bn_free_with_contxt_rply __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved2 [ 4 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_SP_EN */
+	SBPM_BLOCK_REGS_SBPM_SP_EN sbpm_sp_en __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Global_Threshold */
+	SBPM_BLOCK_REGS_SBPM_GL_TRSH sbpm_gl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG0_Threshold */
+	SBPM_BLOCK_REGS_SBPM_UG0_TRSH sbpm_ug0_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG1_Threshold */
+	SBPM_BLOCK_REGS_SBPM_UG1_TRSH sbpm_ug1_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG2_Threshold */
+	SBPM_BLOCK_REGS_SBPM_UG2_TRSH sbpm_ug2_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG3_Threshold */
+	SBPM_BLOCK_REGS_SBPM_UG3_TRSH sbpm_ug3_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG4_Threshold */
+	SBPM_BLOCK_REGS_SBPM_UG4_TRSH sbpm_ug4_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG5_Threshold */
+	SBPM_BLOCK_REGS_SBPM_UG5_TRSH sbpm_ug5_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG6_Threshold */
+	SBPM_BLOCK_REGS_SBPM_UG6_TRSH sbpm_ug6_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UG7_Threshold */
+	SBPM_BLOCK_REGS_SBPM_UG7_TRSH sbpm_ug7_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_map_register_0 */
+	SBPM_BLOCK_REGS_SBPM_UG_MAP_0 sbpm_ug_map_0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_dbg */
+	SBPM_BLOCK_REGS_SBPM_DBG sbpm_dbg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG0_BAC */
+	SBPM_BLOCK_REGS_SBPM_UG0_BAC sbpm_ug0_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG1_BAC */
+	SBPM_BLOCK_REGS_SBPM_UG1_BAC sbpm_ug1_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG2_BAC */
+	SBPM_BLOCK_REGS_SBPM_UG2_BAC sbpm_ug2_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG3_BAC */
+	SBPM_BLOCK_REGS_SBPM_UG3_BAC sbpm_ug3_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG4_BAC */
+	SBPM_BLOCK_REGS_SBPM_UG4_BAC sbpm_ug4_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG5_BAC */
+	SBPM_BLOCK_REGS_SBPM_UG5_BAC sbpm_ug5_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG6_BAC */
+	SBPM_BLOCK_REGS_SBPM_UG6_BAC sbpm_ug6_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG7_BAC */
+	SBPM_BLOCK_REGS_SBPM_UG7_BAC sbpm_ug7_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_GL_BAC */
+	SBPM_BLOCK_REGS_SBPM_GL_BAC sbpm_gl_bac __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG0_Exclusive_threshold */
+	SBPM_BLOCK_REGS_SBPM_UG0_EXCL_TRSH sbpm_ug0_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved3 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG1_Exclusive_threshold */
+	SBPM_BLOCK_REGS_SBPM_UG1_EXCL_TRSH sbpm_ug1_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG2_Exclusive_threshold */
+	SBPM_BLOCK_REGS_SBPM_UG2_EXCL_TRSH sbpm_ug2_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG3_Exclusive_threshold */
+	SBPM_BLOCK_REGS_SBPM_UG3_EXCL_TRSH sbpm_ug3_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG4_Exclusive_threshold */
+	SBPM_BLOCK_REGS_SBPM_UG4_EXCL_TRSH sbpm_ug4_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG5_Exclusive_threshold */
+	SBPM_BLOCK_REGS_SBPM_UG5_EXCL_TRSH sbpm_ug5_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG6_Exclusive_threshold */
+	SBPM_BLOCK_REGS_SBPM_UG6_EXCL_TRSH sbpm_ug6_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_UG7_Exclusive_threshold */
+	SBPM_BLOCK_REGS_SBPM_UG7_EXCL_TRSH sbpm_ug7_excl_trsh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_Status_register */
+	SBPM_BLOCK_REGS_SBPM_UG_STATUS sbpm_ug_status __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_runner_status_message_control_register */
+	SBPM_BLOCK_REGS_SBPM_RNR_STAT_MSG_CTRL sbpm_rnr_stat_msg_ctrl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Runner_Target_address_for_Reply_message */
+	SBPM_BLOCK_REGS_SBPM_RNR_RPLY_TA sbpm_rnr_rply_ta __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sbpm_rnr_wkup_rply_set_0 */
+	SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET0 sbpm_rnr_wkup_rply_set0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sbpm_rnr_wkup_rply_set_1 */
+	SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET1 sbpm_rnr_wkup_rply_set1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sbpm_rnr_wkup_rply_set_2 */
+	SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET2 sbpm_rnr_wkup_rply_set2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sbpm_rnr_wkup_rply_set_3 */
+	SBPM_BLOCK_REGS_SBPM_RNR_WKUP_RPLY_SET3 sbpm_rnr_wkup_rply_set3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* error_handling_params */
+	SBPM_BLOCK_REGS_ERROR_HANDLING_PARAMS error_handling_params __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_ISR */
+	SBPM_BLOCK_REGS_SBPM_ISR sbpm_isr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_IER */
+	SBPM_BLOCK_REGS_SBPM_IER sbpm_ier __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_ITR */
+	SBPM_BLOCK_REGS_SBPM_ITR sbpm_itr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_IIR_low_register */
+	SBPM_BLOCK_REGS_SBPM_IIR_LOW sbpm_iir_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_IIR_high_register */
+	SBPM_BLOCK_REGS_SBPM_IIR_HIGH sbpm_iir_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_DBG_VEC0 */
+	SBPM_BLOCK_REGS_SBPM_DBG_VEC0 sbpm_dbg_vec0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* SBPM_DBG_VEC1 */
+	SBPM_BLOCK_REGS_SBPM_DBG_VEC1 sbpm_dbg_vec1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Route_Address0__config */
+	SBPM_BLOCK_REGS_RADDR_0 raddr_0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Route_Address1__config */
+	SBPM_BLOCK_REGS_RADDR_1 raddr_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Route_Address2__config */
+	SBPM_BLOCK_REGS_RADDR_2 raddr_2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Route_Address3__config */
+	SBPM_BLOCK_REGS_RADDR_3 raddr_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* User_Group_mapping_register_1 */
+	SBPM_BLOCK_REGS_UG_MAP_REG_1 ug_map_reg_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* MIPSD_Target_address_for_Reply_message */
+	SBPM_BLOCK_REGS_SBPM_MIPSD_RPLY_TA sbpm_mipsd_rply_ta __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* sbpm_mipsd_wkup_rply_set */
+	SBPM_BLOCK_REGS_SBPM_MIPSD_WKUP_RPLY_SET sbpm_mipsd_wkup_rply_set __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK_REGS ;
+
+typedef struct
+{
+	/* regs function */
+	SBPM_BLOCK_REGS regs __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+SBPM_BLOCK ;
+
+typedef struct
+{
+	/* BLOCK */
+	SBPM_BLOCK block __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ 
+SBPM_FOR_ALL ;
+#endif /* SBPM_H_INCLUDED */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_subsystem_common.h b/arch/arm/mach-bcmbca/rdp/rdp_subsystem_common.h
new file mode 100755
index 0000000000..dab6464d69
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_subsystem_common.h
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2012 Broadcom
+ */
+/*
+* 
+*/
+
+#ifndef __RDP_SUBSYSTEM_COMMON__
+#define __RDP_SUBSYSTEM_COMMON__
+
+#if defined(__KERNEL__) || defined(__UBOOT__)
+
+#include <common.h>
+#include <linux/compat.h>
+#include <linux/delay.h>
+
+#ifndef printk
+  #define printk printf
+#endif
+
+#elif defined(RDP_SIM)
+
+#include "bdmf_system.h"
+
+#define mdelay(n) ({unsigned long _msec=(n); while(_msec--) bdmf_usleep(1000);})
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-bcmbca/rdp/rdp_ubus.h b/arch/arm/mach-bcmbca/rdp/rdp_ubus.h
new file mode 100755
index 0000000000..a55db0bcf7
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdp_ubus.h
@@ -0,0 +1,1162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2013 Broadcom Corporation
+   All Rights Reserved
+
+     
+*/             
+
+#ifndef __UBUS_H_INCLUDED
+#define __UBUS_H_INCLUDED
+
+/*  File automatically generated by Reggae at 15/08/2013  10:55:15   */
+
+#include "access_macros.h"
+#include "packing.h"
+
+
+/*****************************************************************************************/
+/* Ubus registers including Master and Slave ports                                       */
+/*****************************************************************************************/
+
+/*****************************************************************************************/
+/* Functions offsets and addresses                                                       */
+/*****************************************************************************************/
+#define UBUS_UBUS_MASTER_0_BRDG_REG_OFFSET 	( 0x00000000 )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_ADDRESS	( UBUS_UBUS_MASTER_0_OFFSET + UBUS_UBUS_MASTER_0_BRDG_REG_OFFSET )
+
+#define UBUS_UBUS_MASTER_1_BRDG_REG_OFFSET 	( 0x00000000 )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_ADDRESS	( UBUS_UBUS_MASTER_1_OFFSET + UBUS_UBUS_MASTER_1_BRDG_REG_OFFSET )
+
+#define UBUS_UBUS_MASTER_2_BRDG_REG_OFFSET 	( 0x00000000 )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_ADDRESS	( UBUS_UBUS_MASTER_2_OFFSET + UBUS_UBUS_MASTER_2_BRDG_REG_OFFSET )
+
+#define UBUS_UBUS_SLAVE_BRDG_REG_OFFSET 	( 0x00000000 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_ADDRESS	( UBUS_UBUS_SLAVE_OFFSET + UBUS_UBUS_SLAVE_BRDG_REG_OFFSET )
+
+#define UBUS_UBUS_MISC_EGPHY_OFFSET 	( 0x00000000 )
+#define UBUS_UBUS_MISC_EGPHY_ADDRESS	( UBUS_UBUS_MISC_OFFSET + UBUS_UBUS_MISC_EGPHY_OFFSET )
+
+/*   'd' is module index   */
+/*   'i' is block index    */
+/*   'j' is function index */
+/*   'e' is function entry */
+/*   'k' is register index */
+
+/*****************************************************************************************/
+/* BRDG_EN                                                                               */
+/* bridge enable                                                                         */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MASTER_BRDG_REG_EN_R0_RSRV_VALUE                ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_EN_R0_RSRV_VALUE_RESET_VALUE    ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_EN_EN_DISABLE_VALUE             ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_EN_EN_DISABLE_VALUE_RESET_VALUE ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_EN_EN_ENABLE_VALUE              ( 0x1 )
+
+
+#define UBUS_UBUS_MASTER_BRDG_REG_EN_OFFSET ( 0x00000000 )
+
+#define UBUS_UBUS_MASTER_0_BRDG_REG_EN_ADDRESS   	( UBUS_UBUS_MASTER_0_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_EN_OFFSET )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_EN_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_EN_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_EN_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_EN_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_1_BRDG_REG_EN_ADDRESS   	( UBUS_UBUS_MASTER_1_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_EN_OFFSET )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_EN_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_EN_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_EN_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_EN_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_2_BRDG_REG_EN_ADDRESS   	( UBUS_UBUS_MASTER_2_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_EN_OFFSET )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_EN_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_EN_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_EN_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_EN_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r0	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BRDG_ENABLE */
+	uint32_t en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_EN ;
+#else
+typedef struct
+{	uint32_t en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* BRDG_ENABLE */
+	uint32_t r0	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_EN ;
+#endif
+
+/*****************************************************************************************/
+/* RQUSTOR_CTRL                                                                          */
+/* Requestor side contol. These registers are releated to ubus requestor control         */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_MAX_PKT_LEN_MAX_PACKET_LEN_VALUE             ( 0x90 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_MAX_PKT_LEN_MAX_PACKET_LEN_VALUE_RESET_VALUE ( 0x90 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_R0_RSRV_VALUE                                ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_R0_RSRV_VALUE_RESET_VALUE                    ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_DEV_ERR_NORMAL_VALUE                         ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_DEV_ERR_NORMAL_VALUE_RESET_VALUE             ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_DEV_ERR_ERR_VALUE                            ( 0x1 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_REQOUT_ESWAP_NO_SWAP_VALUE                   ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_REQOUT_ESWAP_NO_SWAP_VALUE_RESET_VALUE       ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_REQOUT_ESWAP_SWAP_VALUE                      ( 0x1 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_REPIN_ESWAP_NO_SWAP_VALUE                    ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_REPIN_ESWAP_NO_SWAP_VALUE_RESET_VALUE        ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_REPIN_ESWAP_SWAP_VALUE                       ( 0x1 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_ENDIAN_MODE_LL_VALUE                         ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_ENDIAN_MODE_LB_VALUE                         ( 0x1 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_ENDIAN_MODE_BL_VALUE                         ( 0x2 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_ENDIAN_MODE_BB_VALUE                         ( 0x3 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_ENDIAN_MODE_BB_VALUE_RESET_VALUE             ( 0x3 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_R1_RSRV_VALUE                                ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_R1_RSRV_VALUE_RESET_VALUE                    ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_PKT_TAG_TAG_DIS_VALUE                        ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_PKT_TAG_TAG_DIS_VALUE_RESET_VALUE            ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_PKT_TAG_TAG_EN_VALUE                         ( 0x1 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_PKT_ID_PKT_ID_VALUE                          ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_PKT_ID_PKT_ID_VALUE_RESET_VALUE              ( 0x0 )
+
+
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_OFFSET ( 0x00000004 )
+
+#define UBUS_UBUS_MASTER_0_BRDG_REG_REQ_CNTRL_ADDRESS   	( UBUS_UBUS_MASTER_0_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_OFFSET )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_REQ_CNTRL_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_REQ_CNTRL_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_REQ_CNTRL_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_REQ_CNTRL_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_1_BRDG_REG_REQ_CNTRL_ADDRESS   	( UBUS_UBUS_MASTER_1_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_OFFSET )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_REQ_CNTRL_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_REQ_CNTRL_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_REQ_CNTRL_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_REQ_CNTRL_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_2_BRDG_REG_REQ_CNTRL_ADDRESS   	( UBUS_UBUS_MASTER_2_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_OFFSET )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_REQ_CNTRL_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_REQ_CNTRL_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_REQ_CNTRL_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_REQ_CNTRL_ADDRESS ), (v) )
+
+
+extern uint32_t UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_ARRAY [ ] ;
+
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_WRITE( i, v )	WRITE_32( UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_ARRAY [ i ], (v) )
+#define UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_READ( i, r ) 	READ_32( UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* Max_Packet_len */
+	uint32_t max_pkt_len 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r0          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* dev_error */
+	uint32_t dev_err     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reqout_eswap */
+	uint32_t reqout_eswap	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* repin_eswap */
+	uint32_t repin_eswap 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* endian_mode */
+	uint32_t endian_mode 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1          	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* packet_tag */
+	uint32_t pkt_tag     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* packet_id */
+	uint32_t pkt_id      	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL ;
+#else
+typedef struct
+{	uint32_t pkt_id      	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* packet_id */
+	uint32_t pkt_tag     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* packet_tag */
+	uint32_t r1          	: 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t endian_mode 	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* endian_mode */
+	uint32_t repin_eswap 	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* repin_eswap */
+	uint32_t reqout_eswap	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reqout_eswap */
+	uint32_t dev_err     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* dev_error */
+	uint32_t r0          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t max_pkt_len 	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Max_Packet_len */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL ;
+#endif
+
+/*****************************************************************************************/
+/* HYST_CTRL                                                                             */
+/* control the command / data queue full and empty indications.                          */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_R1_RSRV_VALUE                       ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_R1_RSRV_VALUE_RESET_VALUE           ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_DATA_SPACE_DSPACE_VALUE             ( 0xC )
+#define UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_DATA_SPACE_DSPACE_VALUE_RESET_VALUE ( 0xC )
+#define UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_R0_RSRV_VALUE                       ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_R0_RSRV_VALUE_RESET_VALUE           ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_CMD_SPACE_HSPACE_VALUE              ( 0xC )
+#define UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_CMD_SPACE_HSPACE_VALUE_RESET_VALUE  ( 0xC )
+
+
+#define UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_OFFSET ( 0x00000008 )
+
+#define UBUS_UBUS_MASTER_0_BRDG_REG_HYST_CTRL_ADDRESS   	( UBUS_UBUS_MASTER_0_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_OFFSET )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_HYST_CTRL_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_HYST_CTRL_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_HYST_CTRL_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_HYST_CTRL_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_1_BRDG_REG_HYST_CTRL_ADDRESS   	( UBUS_UBUS_MASTER_1_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_OFFSET )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_HYST_CTRL_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_HYST_CTRL_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_HYST_CTRL_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_HYST_CTRL_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_2_BRDG_REG_HYST_CTRL_ADDRESS   	( UBUS_UBUS_MASTER_2_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_OFFSET )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_HYST_CTRL_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_HYST_CTRL_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_HYST_CTRL_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_HYST_CTRL_ADDRESS ), (v) )
+
+
+extern uint32_t UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_ARRAY [ ] ;
+
+#define UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_WRITE( i, v )	WRITE_32( UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_ARRAY [ i ], (v) )
+#define UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_READ( i, r ) 	READ_32( UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1        	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DATA_SPACE */
+	uint32_t data_space	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r0        	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CMD_SPACE */
+	uint32_t cmd_space 	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL ;
+#else
+typedef struct
+{	uint32_t cmd_space 	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* CMD_SPACE */
+	uint32_t r0        	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t data_space	: 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* DATA_SPACE */
+	uint32_t r1        	: 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL ;
+#endif
+
+/*****************************************************************************************/
+/* High_Priority                                                                         */
+/* controls the high priority mechanism                                                  */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_R2_RSRV_VALUE                               ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_R2_RSRV_VALUE_RESET_VALUE                   ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_CNT_TOTAL_HP_CNT_TOTAL_VALUE             ( 0xF )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_CNT_TOTAL_HP_CNT_TOTAL_VALUE_RESET_VALUE ( 0xF )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_R1_RSRV_VALUE                               ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_R1_RSRV_VALUE_RESET_VALUE                   ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_CNT_HIGH_HP_CNT_HIGH_VALUE               ( 0x8 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_CNT_HIGH_HP_CNT_HIGH_VALUE_RESET_VALUE   ( 0x8 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_R0_RSRV_VALUE                               ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_R0_RSRV_VALUE_RESET_VALUE                   ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_COMB_SEL_VALUE                           ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_COMB_SEL_VALUE_RESET_VALUE               ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_COMB_COMBINE_VALUE                       ( 0x1 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_SEL_EXTERNAL_VALUE                       ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_SEL_EXTERNAL_VALUE_RESET_VALUE           ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_SEL_INTERNAL_VALUE                       ( 0x1 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_EN_DISABLE_VALUE                         ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_EN_DISABLE_VALUE_RESET_VALUE             ( 0x0 )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_HP_EN_EN_VALUE                              ( 0x1 )
+
+
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_OFFSET ( 0x0000000C )
+
+#define UBUS_UBUS_MASTER_0_BRDG_REG_HP_ADDRESS   	( UBUS_UBUS_MASTER_0_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_HP_OFFSET )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_HP_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_HP_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_HP_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_HP_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_1_BRDG_REG_HP_ADDRESS   	( UBUS_UBUS_MASTER_1_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_HP_OFFSET )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_HP_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_HP_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_HP_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_HP_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_2_BRDG_REG_HP_ADDRESS   	( UBUS_UBUS_MASTER_2_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_HP_OFFSET )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_HP_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_HP_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_HP_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_HP_ADDRESS ), (v) )
+
+
+extern uint32_t UBUS_UBUS_MASTER_BRDG_REG_HP_ARRAY [ ] ;
+
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_WRITE( i, v )	WRITE_32( UBUS_UBUS_MASTER_BRDG_REG_HP_ARRAY [ i ], (v) )
+#define UBUS_UBUS_MASTER_BRDG_REG_HP_READ( i, r ) 	READ_32( UBUS_UBUS_MASTER_BRDG_REG_HP_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r2          	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* hp_cnt_total */
+	uint32_t hp_cnt_total	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1          	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* hp_cnt_high */
+	uint32_t hp_cnt_high 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r0          	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* hp_combine */
+	uint32_t hp_comb     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* hp_sel */
+	uint32_t hp_sel      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* hp_en */
+	uint32_t hp_en       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_HP ;
+#else
+typedef struct
+{	uint32_t hp_en       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* hp_en */
+	uint32_t hp_sel      	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* hp_sel */
+	uint32_t hp_comb     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* hp_combine */
+	uint32_t r0          	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t hp_cnt_high 	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* hp_cnt_high */
+	uint32_t r1          	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t hp_cnt_total	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* hp_cnt_total */
+	uint32_t r2          	: 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_HP ;
+#endif
+
+/*****************************************************************************************/
+/* REPLY_ADDRESS                                                                         */
+/* holds the termination address used for the read reply command                         */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD_ADD_REPLY_ADD_VALUE             ( 0xFFFF0000 )
+#define UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD_ADD_REPLY_ADD_VALUE_RESET_VALUE ( 0xFFFF0000 )
+
+
+#define UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD_OFFSET ( 0x00000010 )
+
+#define UBUS_UBUS_MASTER_0_BRDG_REG_REPLY_ADD_ADDRESS   	( UBUS_UBUS_MASTER_0_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD_OFFSET )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_REPLY_ADD_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_REPLY_ADD_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_REPLY_ADD_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_REPLY_ADD_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_1_BRDG_REG_REPLY_ADD_ADDRESS   	( UBUS_UBUS_MASTER_1_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD_OFFSET )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_REPLY_ADD_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_REPLY_ADD_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_REPLY_ADD_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_REPLY_ADD_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_2_BRDG_REG_REPLY_ADD_ADDRESS   	( UBUS_UBUS_MASTER_2_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD_OFFSET )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_REPLY_ADD_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_REPLY_ADD_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_REPLY_ADD_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_REPLY_ADD_ADDRESS ), (v) )
+
+
+extern uint32_t UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD_ARRAY [ ] ;
+
+#define UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD_WRITE( i, v )	WRITE_32( UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD_ARRAY [ i ], (v) )
+#define UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD_READ( i, r ) 	READ_32( UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* address */
+	uint32_t add	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD ;
+#else
+typedef struct
+{	uint32_t add	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* address */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD ;
+#endif
+
+/*****************************************************************************************/
+/* REPLY_DATA                                                                            */
+/* holds the data value for the read reply command. the data held in this register will  */
+/* be returned to runner                                                                 */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA_DATA_REPLY_DATA_VALUE             ( 0xDEADBEAF )
+#define UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA_DATA_REPLY_DATA_VALUE_RESET_VALUE ( 0xDEADBEAF )
+
+
+#define UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA_OFFSET ( 0x00000014 )
+
+#define UBUS_UBUS_MASTER_0_BRDG_REG_REPLY_DATA_ADDRESS   	( UBUS_UBUS_MASTER_0_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA_OFFSET )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_REPLY_DATA_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_REPLY_DATA_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_0_BRDG_REG_REPLY_DATA_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_0_BRDG_REG_REPLY_DATA_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_1_BRDG_REG_REPLY_DATA_ADDRESS   	( UBUS_UBUS_MASTER_1_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA_OFFSET )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_REPLY_DATA_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_REPLY_DATA_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_1_BRDG_REG_REPLY_DATA_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_1_BRDG_REG_REPLY_DATA_ADDRESS ), (v) )
+
+#define UBUS_UBUS_MASTER_2_BRDG_REG_REPLY_DATA_ADDRESS   	( UBUS_UBUS_MASTER_2_BRDG_REG_ADDRESS + UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA_OFFSET )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_REPLY_DATA_READ( r ) 	READ_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_REPLY_DATA_ADDRESS ), (r) )
+#define UBUS_UBUS_MASTER_2_BRDG_REG_REPLY_DATA_WRITE( v )	WRITE_32( ( UBUS_UBUS_MASTER_2_BRDG_REG_REPLY_DATA_ADDRESS ), (v) )
+
+
+extern uint32_t UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA_ARRAY [ ] ;
+
+#define UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA_WRITE( i, v )	WRITE_32( UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA_ARRAY [ i ], (v) )
+#define UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA_READ( i, r ) 	READ_32( UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA_ARRAY [ i ], (r) )  
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* data */
+	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA ;
+#else
+typedef struct
+{	uint32_t data	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* data */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA ;
+#endif
+
+/*****************************************************************************************/
+/* BRDG_EN                                                                               */
+/* bridge enable                                                                         */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_SLAVE_BRDG_REG_EN_R0_RSRV_VALUE                 ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_EN_R0_RSRV_VALUE_RESET_VALUE     ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_EN_INIT_INIT_0_VALUE             ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_EN_INIT_INIT_0_VALUE_RESET_VALUE ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_EN_INIT_INIT_1_VALUE             ( 0x1 )
+
+
+#define UBUS_UBUS_SLAVE_BRDG_REG_EN_OFFSET ( 0x00000000 )
+
+#define UBUS_UBUS_SLAVE_BRDG_REG_EN_ADDRESS   	( UBUS_UBUS_SLAVE_BRDG_REG_ADDRESS + UBUS_UBUS_SLAVE_BRDG_REG_EN_OFFSET )
+#define UBUS_UBUS_SLAVE_BRDG_REG_EN_READ( r ) 	READ_32( ( UBUS_UBUS_SLAVE_BRDG_REG_EN_ADDRESS ), (r) )
+#define UBUS_UBUS_SLAVE_BRDG_REG_EN_WRITE( v )	WRITE_32( ( UBUS_UBUS_SLAVE_BRDG_REG_EN_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r0  	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* init */
+	uint32_t init	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_SLAVE_BRDG_REG_EN ;
+#else
+typedef struct
+{	uint32_t init	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* init */
+	uint32_t r0  	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_SLAVE_BRDG_REG_EN ;
+#endif
+
+/*****************************************************************************************/
+/* RESPONDER_CTRL                                                                        */
+/* Responder side contol. These registers are releated to ubus Responder control         */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_DEV_TIMEOUT_DEV_TIMEOUT_VALUE             ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_DEV_TIMEOUT_DEV_TIMEOUT_VALUE_RESET_VALUE ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_DEV_TIMEOUT_EN_DISABLE_VALUE              ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_DEV_TIMEOUT_EN_DISABLE_VALUE_RESET_VALUE  ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_DEV_TIMEOUT_EN_ENABLE_VALUE               ( 0x1 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_DEV_ERR_NORMAL_VALUE                      ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_DEV_ERR_NORMAL_VALUE_RESET_VALUE          ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_DEV_ERR_ERR_VALUE                         ( 0x1 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_DEV_CLKEN_DISABLE_VALUE                   ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_DEV_CLKEN_ENABLE_VALUE                    ( 0x1 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_DEV_CLKEN_ENABLE_VALUE_RESET_VALUE        ( 0x1 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_REQOUT_ESWAP_NO_SWAP_VALUE                ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_REQOUT_ESWAP_NO_SWAP_VALUE_RESET_VALUE    ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_REQOUT_ESWAP_SWAP_VALUE                   ( 0x1 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_REPIN_ESWAP_NO_SWAP_VALUE                 ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_REPIN_ESWAP_NO_SWAP_VALUE_RESET_VALUE     ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_REPIN_ESWAP_SWAP_VALUE                    ( 0x1 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_R0_RSRV_VALUE                             ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_R0_RSRV_VALUE_RESET_VALUE                 ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_MASK_ID_MASK_ID_VALUE                     ( 0xFF )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_MASK_ID_MASK_ID_VALUE_RESET_VALUE         ( 0xFF )
+
+
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_OFFSET ( 0x00000004 )
+
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_ADDRESS   	( UBUS_UBUS_SLAVE_BRDG_REG_ADDRESS + UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_OFFSET )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_READ( r ) 	READ_32( ( UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_ADDRESS ), (r) )
+#define UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_WRITE( v )	WRITE_32( ( UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* dev_timeout */
+	uint32_t dev_timeout   	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* dev_timeout_en */
+	uint32_t dev_timeout_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* dev_error */
+	uint32_t dev_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* dev_clk_en */
+	uint32_t dev_clken     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reqout_eswap */
+	uint32_t reqout_eswap  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* repin_eswap */
+	uint32_t repin_eswap   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r0            	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mask_id */
+	uint32_t mask_id       	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL ;
+#else
+typedef struct
+{	uint32_t mask_id       	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* mask_id */
+	uint32_t r0            	: 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t repin_eswap   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* repin_eswap */
+	uint32_t reqout_eswap  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reqout_eswap */
+	uint32_t dev_clken     	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* dev_clk_en */
+	uint32_t dev_err       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* dev_error */
+	uint32_t dev_timeout_en	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* dev_timeout_en */
+	uint32_t dev_timeout   	: 11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* dev_timeout */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL ;
+#endif
+
+/*****************************************************************************************/
+/* HYST_CTRL                                                                             */
+/* control the command / data queue full and empty indications.                          */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_R1_RSRV_VALUE                         ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_R1_RSRV_VALUE_RESET_VALUE             ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_SECLEV_EN_DISABLE_VALUE               ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_SECLEV_EN_DISABLE_VALUE_RESET_VALUE   ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_SECLEV_EN_ENABLE_VALUE                ( 0x1 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_SECLEV_CFG_CFG_0_VALUE                ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_SECLEV_CFG_CFG_0_VALUE_RESET_VALUE    ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_SECLEV_CFG_CFG_1_VALUE                ( 0x1 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_R0_RSRV_VALUE                         ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_R0_RSRV_VALUE_RESET_VALUE             ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_SECLEV_STRAP_SECLEV_VALUE             ( 0x0 )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_SECLEV_STRAP_SECLEV_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_OFFSET ( 0x00000008 )
+
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_ADDRESS   	( UBUS_UBUS_SLAVE_BRDG_REG_ADDRESS + UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_OFFSET )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_READ( r ) 	READ_32( ( UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_ADDRESS ), (r) )
+#define UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_WRITE( v )	WRITE_32( ( UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r1          	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* seclev_en */
+	uint32_t seclev_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* seclev_config */
+	uint32_t seclev_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r0          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* seclev_strap */
+	uint32_t seclev_strap	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL ;
+#else
+typedef struct
+{	uint32_t seclev_strap	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* seclev_strap */
+	uint32_t r0          	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t seclev_cfg  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* seclev_config */
+	uint32_t seclev_en   	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* seclev_en */
+	uint32_t r1          	: 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL ;
+#endif
+
+/*****************************************************************************************/
+/* GPHY_OUT                                                                              */
+/* gphy registers output from CR to GPHY                                                 */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_R0_RSRV_VALUE                              ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_R0_RSRV_VALUE_RESET_VALUE                  ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_PHY_TEST_EN_REGULAR_MODE_VALUE             ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_PHY_TEST_EN_REGULAR_MODE_VALUE_RESET_VALUE ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_PHY_TEST_EN_TEST_MODE_VALUE                ( 0x1 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_PHYA_PHYA_VALUE                            ( 0x1 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_PHYA_PHYA_VALUE_RESET_VALUE                ( 0x1 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_GPHY_CK25_DIS_CK_25_DIS_VALUE              ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_GPHY_CK25_DIS_CK_25_DIS_VALUE_RESET_VALUE  ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_IDDQ_BIAS_IDDQ_BIAS_VALUE                  ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_IDDQ_BIAS_IDDQ_BIAS_VALUE_RESET_VALUE      ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_DLL_EN_DLL_EN_VALUE                        ( 0x1 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_DLL_EN_DLL_EN_VALUE_RESET_VALUE            ( 0x1 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_PWRDWN_EXT_PWRDWN_VALUE                    ( 0xF )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_PWRDWN_EXT_PWRDWN_VALUE_RESET_VALUE        ( 0xF )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_R1_GPHY_CK25_DIS_VALUE                     ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_R1_GPHY_CK25_DIS_VALUE_RESET_VALUE         ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_RST_RST_VALUE                              ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_RST_NOT_RST_VALUE                          ( 0x1 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_RST_NOT_RST_VALUE_RESET_VALUE              ( 0x1 )
+
+
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_OFFSET ( 0x00000000 )
+
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_ADDRESS   	( UBUS_UBUS_MISC_EGPHY_ADDRESS + UBUS_UBUS_MISC_EGPHY_GPHY_OUT_OFFSET )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_READ( r ) 	READ_32( ( UBUS_UBUS_MISC_EGPHY_GPHY_OUT_ADDRESS ), (r) )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_OUT_WRITE( v )	WRITE_32( ( UBUS_UBUS_MISC_EGPHY_GPHY_OUT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r0           	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* phy_test_en */
+	uint32_t phy_test_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* phya */
+	uint32_t phya         	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gphy_ck25_disable */
+	uint32_t gphy_ck25_dis	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* i_mac_gphy_cfg_iddq_bias */
+	uint32_t iddq_bias    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* i_mac_gphy_cfg_ext_force_dll_en */
+	uint32_t dll_en       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* i_mac_gphy_cfg_ext_pwrdown */
+	uint32_t pwrdwn       	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t r1           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* i_mac_gphy_cfg_reset_b */
+	uint32_t rst          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_GPHY_OUT ;
+#else
+typedef struct
+{	uint32_t rst          	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* i_mac_gphy_cfg_reset_b */
+	uint32_t r1           	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+	uint32_t pwrdwn       	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* i_mac_gphy_cfg_ext_pwrdown */
+	uint32_t dll_en       	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* i_mac_gphy_cfg_ext_force_dll_en */
+	uint32_t iddq_bias    	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* i_mac_gphy_cfg_iddq_bias */
+	uint32_t gphy_ck25_dis	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* gphy_ck25_disable */
+	uint32_t phya         	: 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* phya */
+	uint32_t phy_test_en  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* phy_test_en */
+	uint32_t r0           	: 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_GPHY_OUT ;
+#endif
+
+/*****************************************************************************************/
+/* RGMII_OUT                                                                             */
+/* RGMII registers output from CR to GPHY                                                */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_R0_RSRV_VALUE                        ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_R0_RSRV_VALUE_RESET_VALUE            ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_ID_MODE_ID_MODE_VALUE                ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_ID_MODE_ID_MODE_VALUE_RESET_VALUE    ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_REF_SEL_REFSEL_VALUE                 ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_REF_SEL_REFSEL_VALUE_RESET_VALUE     ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_PORT_MODE_PORTMODE_VALUE             ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_PORT_MODE_PORTMODE_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_OFFSET ( 0x00000004 )
+
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_ADDRESS   	( UBUS_UBUS_MISC_EGPHY_ADDRESS + UBUS_UBUS_MISC_EGPHY_RGMII_OUT_OFFSET )
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_READ( r ) 	READ_32( ( UBUS_UBUS_MISC_EGPHY_RGMII_OUT_ADDRESS ), (r) )
+#define UBUS_UBUS_MISC_EGPHY_RGMII_OUT_WRITE( v )	WRITE_32( ( UBUS_UBUS_MISC_EGPHY_RGMII_OUT_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r0       	: 27 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* o_cfg_id_mode_disable */
+	uint32_t id_mode  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* o_cfg_rvmii_ref_sel */
+	uint32_t ref_sel  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* o_cfg_port_mode */
+	uint32_t port_mode	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_RGMII_OUT ;
+#else
+typedef struct
+{	uint32_t port_mode	: 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* o_cfg_port_mode */
+	uint32_t ref_sel  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* o_cfg_rvmii_ref_sel */
+	uint32_t id_mode  	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* o_cfg_id_mode_disable */
+	uint32_t r0       	: 27 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_RGMII_OUT ;
+#endif
+
+/*****************************************************************************************/
+/* GPHY_IN                                                                               */
+/* gphy inputs from GPHY block                                                           */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_LNKSPD_1_LNKSPD_1_VALUE                             ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_LNKSPD_1_LNKSPD_1_VALUE_RESET_VALUE                 ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_LNKSPD_2_LNKSPD_2_VALUE                             ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_LNKSPD_2_LNKSPD_2_VALUE_RESET_VALUE                 ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_LNKSPD_3_LNKSPD_3_VALUE                             ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_LNKSPD_3_LNKSPD_3_VALUE_RESET_VALUE                 ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_LNKSPD_4_LNKSPD_4_VALUE                             ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_LNKSPD_4_LNKSPD_4_VALUE_RESET_VALUE                 ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_FDXLED_N_FDXLED_N_VALUE                             ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_FDXLED_N_FDXLED_N_VALUE_RESET_VALUE                 ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_PAUSE_RES_TX_PAUSE_RES_TX_VALUE                     ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_PAUSE_RES_TX_PAUSE_RES_TX_VALUE_RESET_VALUE         ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_PAUSE_RES_RX_PAUSE_RES_RX_VALUE                     ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_PAUSE_RES_RX_PAUSE_RES_RX_VALUE_RESET_VALUE         ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_LOCK_RCVRY_CLK_LOCK_RCVRY_CLK_VALUE                 ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_LOCK_RCVRY_CLK_LOCK_RCVRY_CLK_VALUE_RESET_VALUE     ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_ENRGY_DET_MASKED_ENRGY_DET_MASKED_VALUE             ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_ENRGY_DET_MASKED_ENRGY_DET_MASKED_VALUE_RESET_VALUE ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_ENRGY_DET_APD_ENRGY_DET_APD_VALUE                   ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_ENRGY_DET_APD_ENRGY_DET_APD_VALUE_RESET_VALUE       ( 0x0 )
+
+
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_OFFSET ( 0x00000008 )
+
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_ADDRESS   	( UBUS_UBUS_MISC_EGPHY_ADDRESS + UBUS_UBUS_MISC_EGPHY_GPHY_IN_OFFSET )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_READ( r ) 	READ_32( ( UBUS_UBUS_MISC_EGPHY_GPHY_IN_ADDRESS ), (r) )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN_WRITE( v )	WRITE_32( ( UBUS_UBUS_MISC_EGPHY_GPHY_IN_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* linkspd_n1 */
+	uint32_t lnkspd_1        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* linkspd_n2 */
+	uint32_t lnkspd_2        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* linkspd_n3 */
+	uint32_t lnkspd_3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* linkspd_n4 */
+	uint32_t lnkspd_4        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* fdxled_n */
+	uint32_t fdxled_n        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pause_resolution_tx */
+	uint32_t pause_res_tx    	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pause_resolution_rx */
+	uint32_t pause_res_rx    	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* lock_recovery_clock */
+	uint32_t lock_rcvry_clk  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* energy_det_masked */
+	uint32_t enrgy_det_masked	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* energy_det_apd */
+	uint32_t enrgy_det_apd   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_GPHY_IN ;
+#else
+typedef struct
+{	uint32_t enrgy_det_apd   	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* energy_det_apd */
+	uint32_t enrgy_det_masked	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* energy_det_masked */
+	uint32_t lock_rcvry_clk  	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* lock_recovery_clock */
+	uint32_t pause_res_rx    	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pause_resolution_rx */
+	uint32_t pause_res_tx    	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pause_resolution_tx */
+	uint32_t fdxled_n        	: 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* fdxled_n */
+	uint32_t lnkspd_4        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* linkspd_n4 */
+	uint32_t lnkspd_3        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* linkspd_n3 */
+	uint32_t lnkspd_2        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* linkspd_n2 */
+	uint32_t lnkspd_1        	: 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* linkspd_n1 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_GPHY_IN ;
+#endif
+
+/*****************************************************************************************/
+/* GPHY_IN_2                                                                             */
+/* gphy inputs from GPHY block 2                                                         */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN2_R0_RSRV_VALUE                       ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN2_R0_RSRV_VALUE_RESET_VALUE           ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN2_PLL_LOCK_PLL_LOCK_VALUE             ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN2_PLL_LOCK_PLL_LOCK_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN2_OFFSET ( 0x0000000C )
+
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN2_ADDRESS   	( UBUS_UBUS_MISC_EGPHY_ADDRESS + UBUS_UBUS_MISC_EGPHY_GPHY_IN2_OFFSET )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN2_READ( r ) 	READ_32( ( UBUS_UBUS_MISC_EGPHY_GPHY_IN2_ADDRESS ), (r) )
+#define UBUS_UBUS_MISC_EGPHY_GPHY_IN2_WRITE( v )	WRITE_32( ( UBUS_UBUS_MISC_EGPHY_GPHY_IN2_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* reserved */
+	uint32_t r0      	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pll_freq_lock */
+	uint32_t pll_lock	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_GPHY_IN2 ;
+#else
+typedef struct
+{	uint32_t pll_lock	: 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* pll_freq_lock */
+	uint32_t r0      	: 31 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* reserved */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_GPHY_IN2 ;
+#endif
+
+/*****************************************************************************************/
+/* ECO_REG_0_RST                                                                         */
+/* ECO registers reset value is 0                                                        */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MISC_EGPHY_ECO_0_ECO_RST_0_PLL_LOCK_VALUE             ( 0x0 )
+#define UBUS_UBUS_MISC_EGPHY_ECO_0_ECO_RST_0_PLL_LOCK_VALUE_RESET_VALUE ( 0x0 )
+
+
+#define UBUS_UBUS_MISC_EGPHY_ECO_0_OFFSET ( 0x00000010 )
+
+#define UBUS_UBUS_MISC_EGPHY_ECO_0_ADDRESS   	( UBUS_UBUS_MISC_EGPHY_ADDRESS + UBUS_UBUS_MISC_EGPHY_ECO_0_OFFSET )
+#define UBUS_UBUS_MISC_EGPHY_ECO_0_READ( r ) 	READ_32( ( UBUS_UBUS_MISC_EGPHY_ECO_0_ADDRESS ), (r) )
+#define UBUS_UBUS_MISC_EGPHY_ECO_0_WRITE( v )	WRITE_32( ( UBUS_UBUS_MISC_EGPHY_ECO_0_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* eco_rst_0 */
+	uint32_t eco_rst_0	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_ECO_0 ;
+#else
+typedef struct
+{	uint32_t eco_rst_0	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eco_rst_0 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_ECO_0 ;
+#endif
+
+/*****************************************************************************************/
+/* ECO_REG_1_RST                                                                         */
+/* ECO registers reset value is 1                                                        */
+/*****************************************************************************************/
+
+#define UBUS_UBUS_MISC_EGPHY_ECO_1_ECO_RST_1_PLL_LOCK_VALUE             ( 0xFFFFFFFF )
+#define UBUS_UBUS_MISC_EGPHY_ECO_1_ECO_RST_1_PLL_LOCK_VALUE_RESET_VALUE ( 0xFFFFFFFF )
+
+
+#define UBUS_UBUS_MISC_EGPHY_ECO_1_OFFSET ( 0x00000014 )
+
+#define UBUS_UBUS_MISC_EGPHY_ECO_1_ADDRESS   	( UBUS_UBUS_MISC_EGPHY_ADDRESS + UBUS_UBUS_MISC_EGPHY_ECO_1_OFFSET )
+#define UBUS_UBUS_MISC_EGPHY_ECO_1_READ( r ) 	READ_32( ( UBUS_UBUS_MISC_EGPHY_ECO_1_ADDRESS ), (r) )
+#define UBUS_UBUS_MISC_EGPHY_ECO_1_WRITE( v )	WRITE_32( ( UBUS_UBUS_MISC_EGPHY_ECO_1_ADDRESS ), (v) )
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	/* eco_regs_rst_1 */
+	uint32_t eco_rst_1	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_ECO_1 ;
+#else
+typedef struct
+{	uint32_t eco_rst_1	: 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* eco_regs_rst_1 */
+}
+__PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY_ECO_1 ;
+#endif
+
+typedef struct
+{
+	/* BRDG_EN */
+	UBUS_UBUS_MASTER_BRDG_REG_EN en __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RQUSTOR_CTRL */
+	UBUS_UBUS_MASTER_BRDG_REG_REQ_CNTRL req_cntrl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HYST_CTRL */
+	UBUS_UBUS_MASTER_BRDG_REG_HYST_CTRL hyst_ctrl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* High_Priority */
+	UBUS_UBUS_MASTER_BRDG_REG_HP hp __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* REPLY_ADDRESS */
+	UBUS_UBUS_MASTER_BRDG_REG_REPLY_ADD reply_add __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* REPLY_DATA */
+	UBUS_UBUS_MASTER_BRDG_REG_REPLY_DATA reply_data __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER_BRDG_REG ;
+
+typedef struct
+{
+	/* BRDG_EN */
+	UBUS_UBUS_SLAVE_BRDG_REG_EN en __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RESPONDER_CTRL */
+	UBUS_UBUS_SLAVE_BRDG_REG_RES_CNTRL res_cntrl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* HYST_CTRL */
+	UBUS_UBUS_SLAVE_BRDG_REG_HYST_CTRL hyst_ctrl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_SLAVE_BRDG_REG ;
+
+typedef struct
+{
+	/* GPHY_OUT */
+	UBUS_UBUS_MISC_EGPHY_GPHY_OUT gphy_out __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* RGMII_OUT */
+	UBUS_UBUS_MISC_EGPHY_RGMII_OUT rgmii_out __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPHY_IN */
+	UBUS_UBUS_MISC_EGPHY_GPHY_IN gphy_in __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* GPHY_IN_2 */
+	UBUS_UBUS_MISC_EGPHY_GPHY_IN2 gphy_in2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ECO_REG_0_RST */
+	UBUS_UBUS_MISC_EGPHY_ECO_0 eco_0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* ECO_REG_1_RST */
+	UBUS_UBUS_MISC_EGPHY_ECO_1 eco_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC_EGPHY ;
+
+typedef struct
+{
+	/* brdg_reg function */
+	UBUS_UBUS_MASTER_BRDG_REG brdg_reg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MASTER ;
+
+typedef struct
+{
+	/* brdg_reg function */
+	UBUS_UBUS_SLAVE_BRDG_REG brdg_reg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_SLAVE ;
+
+typedef struct
+{
+	/* egphy function */
+	UBUS_UBUS_MISC_EGPHY egphy __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+ __PACKING_ATTRIBUTE_STRUCT_END__
+UBUS_UBUS_MISC ;
+
+#define UBUS_UBUS_MASTER_NUMBER ( 3 )
+typedef struct
+{
+	/* UBUS_MASTER */
+	UBUS_UBUS_MASTER ubus_master [ UBUS_UBUS_MASTER_NUMBER ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved1 [ 3048 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UBUS_SLAVE */
+	UBUS_UBUS_SLAVE ubus_slave __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* Reserved */
+	uint8_t reserved2 [ 1012 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+
+	/* UBUS_MISC */
+	UBUS_UBUS_MISC ubus_misc __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ 
+UBUS_FOR_ALL ;
+#endif /* UBUS_H_INCLUDED */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdpa_config.h b/arch/arm/mach-bcmbca/rdp/rdpa_config.h
new file mode 100644
index 0000000000..c5457cee54
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdpa_config.h
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+* 
+*/
+
+
+#ifndef RDPA_CONFIG_H_
+#define RDPA_CONFIG_H_
+
+/*****************************************************************************/
+/** MTU                                                                     **/
+/*****************************************************************************/
+#if defined(CONFIG_BCM_JUMBO_FRAME) && defined(CONFIG_BCM_MAX_MTU_SIZE)
+#ifndef ENET_MAX_MTU_EXTRA_SIZE
+#define ENET_MAX_MTU_EXTRA_SIZE  32
+#endif
+#define RDPA_MTU (CONFIG_BCM_MAX_MTU_SIZE + ENET_MAX_MTU_EXTRA_SIZE)
+#elif defined(CONFIG_BCM_JUMBO_FRAME)
+#if defined(BCM_DSL_RDP) || defined(BCM_DSL_XRDP)
+/* defined in bcm_pkt_lengths.h
+ * ENET_MAX_MTU_PAYLOAD_SIZE = 2048 (mini jumbo)
+ * ENET_MAX_MTU_EXTRA_SIZE   = 30 (EH_SIZE(14) + VLANTAG(4) + VLANTAG(4) + BRCMTAG(4) + FCS(4))
+ * RDPA_MTU = 2048 + 30 = 2078
+ */
+#define RDPA_MTU 2078
+#else
+/*RDPA_BPM_BUFFER_2K = 1958+ENET_MAX_MTU_EXTRA_SIZE+18+40*/
+#define RDPA_MTU 1990
+#endif /*DSL*/
+#else
+#define RDPA_MTU 1536
+#endif
+
+#ifndef RDPA_MIN_MTU
+#define RDPA_MIN_MTU 64
+#endif
+
+/*****************************************************************************/
+/* The minimal headroom size within an SKB buffer                            */
+/*****************************************************************************/
+#ifndef RDPA_MIN_SKB_HEADROOM_SIZE
+#define RDPA_MIN_SKB_HEADROOM_SIZE 0
+#endif
+
+#ifndef RDPA_DS_LITE_HEADROOM_SIZE
+#define RDPA_DS_LITE_HEADROOM_SIZE 40
+#endif
+
+/*---------------------------------------------------------------------------*/
+/*  Define BL's PON parameters                                   */
+/*---------------------------------------------------------------------------*/
+
+
+/*****************************************************************************/
+/**  SF Threshold - 3 to 8                                                  **/
+/*****************************************************************************/
+#ifndef RDPA_SF_THRESHOLD
+#define RDPA_SF_THRESHOLD 3
+#endif
+
+/*****************************************************************************/
+/**  SD Threshold - 4 to 9                                                  **/
+/*****************************************************************************/
+#ifndef RDPA_SD_THRESHOLD
+#define RDPA_SD_THRESHOLD 4
+#endif
+
+/*****************************************************************************/
+/**  TO1 Timeout                                                            **/
+/*****************************************************************************/
+#ifndef RDPA_TO1_TIMEOUT
+#define RDPA_TO1_TIMEOUT 20000
+#endif
+
+/*****************************************************************************/
+/**  TO2 Timeout                                                            **/
+/*****************************************************************************/
+#ifndef RDPA_TO2_TIMEOUT
+#define RDPA_TO2_TIMEOUT 100
+#endif
+
+/*****************************************************************************/
+/**  DWELL_TIMER Timeout                                                    **/
+/*****************************************************************************/
+#ifndef RDPA_DWELL_TIMER_TIMEOUT
+#define RDPA_DWELL_TIMER_TIMEOUT 10000
+#endif
+
+/*****************************************************************************/
+/**  TO6 Timeout                                                            **/
+/*****************************************************************************/
+#ifndef RDPA_TO6_TIMEOUT
+#define RDPA_TO6_TIMEOUT 10000
+#endif
+
+/*****************************************************************************/
+/**  BER interval - 1000 to 5000 msec                                       **/
+/*****************************************************************************/
+#ifndef RDPA_BER_INTERVAL
+#define RDPA_BER_INTERVAL 1000
+#endif
+
+/*****************************************************************************/
+/**  Minminal response time - Minimum 10 usec                                  **/
+/*****************************************************************************/
+#ifndef RDPA_MIN_RESPONSE_TIME
+#define RDPA_MIN_RESPONSE_TIME 35
+#endif
+
+
+/*****************************************************************************/
+/**  TX Data Polarity mode - Positive/Negative                              **/
+/*****************************************************************************/
+#ifndef RDPA_TX_DATA_POLARITY_MODE
+#define RDPA_TX_DATA_POLARITY_MODE 0
+#endif
+
+
+/*****************************************************************************/
+/**  RX Data Polarity mode - Positive/Negative                              **/
+/*****************************************************************************/
+#ifndef RDPA_RX_DIN_POLARITY_MODE
+#define RDPA_RX_DIN_POLARITY_MODE 0
+#endif
+
+/*****************************************************************************/
+/**  Number of pysnc for LOF assertion - 1 to 15                            **/
+/*****************************************************************************/
+#ifndef RDPA_RX_LOF_ASSERTION
+#define RDPA_RX_LOF_ASSERTION 4
+#endif
+
+/*****************************************************************************/
+/**  Number of pysnc for LOF clear - 1 to 15                                **/
+/*****************************************************************************/
+#ifndef RDPA_RX_LOF_CLEAR
+#define RDPA_RX_LOF_CLEAR 1
+#endif
+
+/*****************************************************************************/
+/**  DV setup pattern - 16 bits                                             **/
+/*****************************************************************************/
+#ifndef RDPA_DV_SETUP_PATTERN
+#ifdef CONFIG_BCM6858
+#define RDPA_DV_SETUP_PATTERN 0xFFFF
+#else
+#define RDPA_DV_SETUP_PATTERN 0x0FFF
+#endif
+#endif
+
+/*****************************************************************************/
+/**  DV hold pattern - 16 bits                                              **/
+/*****************************************************************************/
+#ifndef RDPA_DV_HOLD_PATTERN
+#ifdef CONFIG_BCM6858
+#define RDPA_DV_HOLD_PATTERN 0xFFFF
+#else
+#define RDPA_DV_HOLD_PATTERN 0xFFF0
+#endif
+#endif
+
+/*****************************************************************************/
+/**  DV polarity - High/Low                                                 **/
+/*****************************************************************************/
+#ifndef RDPA_DV_POLARITY
+#define RDPA_DV_POLARITY rdpa_polarity_active_high
+#endif
+
+/*****************************************************************************/
+/** task priority                                                           **/
+/*****************************************************************************/
+#ifndef RDPA_TASK_PRIORITY
+#define RDPA_TASK_PRIORITY 50
+#endif
+
+/*****************************************************************************/
+/** Power calibration mode - Disable/Enable                                 **/
+/*****************************************************************************/
+#ifndef RDPA_POWER_CALIBRATION_MODE
+#define RDPA_POWER_CALIBRATION_MODE 0 /* 0 for disable, 1 for enable */
+#endif
+
+/*****************************************************************************/
+/** Power calibration pattern - 32 bits                                     **/
+/*****************************************************************************/
+#ifndef RDPA_POWER_CALIBRATION_PATTERN
+#define RDPA_POWER_CALIBRATION_PATTERN 0xAAAAAAAA
+#endif
+
+/*****************************************************************************/
+/** Power calibration size (bytes) - muliply of 4 bytes, up to 508 bytes    **/
+/*****************************************************************************/
+#ifndef RDPA_POWER_CALIBRATION_SIZE
+#define RDPA_POWER_CALIBRATION_SIZE 72
+#endif
+
+/*---------------------------------------------------------------------------*/
+/*  Define BL's Bridge parameters                                */
+/*---------------------------------------------------------------------------*/
+
+/*****************************************************************************/
+/** VLAN Ethernet type detect 1 - 16 bits                                   **/
+/*****************************************************************************/
+#ifndef RDPA_VLAN_ETH_TYPE_DETECT_1
+#define RDPA_VLAN_ETH_TYPE_DETECT_1 0x8100
+#endif
+
+/*****************************************************************************/
+/** VLAN Ethernet type detect 2 - 16 bits                                   **/
+/*****************************************************************************/
+#ifndef RDPA_VLAN_ETH_TYPE_DETECT_2
+#define RDPA_VLAN_ETH_TYPE_DETECT_2 0x88A8
+#endif
+
+/*****************************************************************************/
+/** VLAN Ethernet type detect 3 - 16 bits                                   **/
+/*****************************************************************************/
+#ifndef RDPA_VLAN_ETH_TYPE_DETECT_3
+#define RDPA_VLAN_ETH_TYPE_DETECT_3 0xffff /*invalid */
+#endif
+
+/*****************************************************************************/
+/** VLAN Ethernet type detect 4 - 16 bits                                   **/
+/*****************************************************************************/
+#ifndef RDPA_VLAN_ETH_TYPE_DETECT_4
+#define RDPA_VLAN_ETH_TYPE_DETECT_4 0xffff /*invalid */
+#endif
+
+/*****************************************************************************/
+/** US ETH QOS mode **/
+/*****************************************************************************/
+#ifndef RDPA_US_QOS_AND_SCHEDULE_METHOD_ETH_MAX_TCONT_NUM
+#define RDPA_US_QOS_AND_SCHEDULE_METHOD_ETH_MAX_TCONT_NUM 8
+#endif
+
+/*****************************************************************************/
+/** US scheduling - max number of US rate controllers                       **/
+/*****************************************************************************/
+#ifndef RDPA_MAX_US_RATE_CONTROLLERS
+#define RDPA_MAX_US_RATE_CONTROLLERS    128
+#endif
+
+/*****************************************************************************/
+/** US scheduling - max number of US channels                               **/
+/*****************************************************************************/
+#ifndef RDPA_MAX_US_CHANNELS
+#if defined(BCM_DSL_XRDP)
+#define RDPA_MAX_US_CHANNELS            50
+#else
+#define RDPA_MAX_US_CHANNELS            40
+#endif
+#endif
+
+#endif /* RDPA_CONFIG_H_ */
diff --git a/arch/arm/mach-bcmbca/rdp/rdpa_cpu.h b/arch/arm/mach-bcmbca/rdp/rdpa_cpu.h
new file mode 100755
index 0000000000..382474461e
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdpa_cpu.h
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+* 
+*/
+
+#ifndef RDPA_CPU_H_
+#define RDPA_CPU_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "rdpa_types.h"
+#include "rdpa_cpu_basic.h"
+
+/** \defgroup cpu CPU Interface
+ * Functions in this module:
+ * - Send packets from the host to any egress port or to virtual "bridge" port
+ * - Receive packets via one of host termination (CPU_RX) or Wi-Fi acceleration (WLAN_TX) queues
+ * - Connect per-port and/or per-receive queue interrupt handlers
+ * - Configure CPU trap reason --> queue mapping
+ *
+ * Runner to host traffic management parameters can be configured similarly to any other egress queue.
+ * Initial port level (CPU, WLAN0, WLAN1) configuration is done using the appropriate port configuration
+ * that fixes parameters such as scheduling type, number of queues, etc.\n
+ * @{
+ */
+
+/** \defgroup isr Interrupt Control
+ * \ingroup cpu
+ * Functions in this group allow to
+ * - Register / unregister per-queue interrupt handler
+ * - Enable / disable / clear per-queue interrupt
+ * @{
+ */
+
+/** Enable CPU queue interrupt
+ * \param[in]   port        port. rdpa_cpu, rdpa_wlan0, rdpa_wlan1
+ * \param[in]   queue       Queue index < num_queues in port tm configuration
+ */
+void rdpa_cpu_int_enable(rdpa_cpu_port port, int queue);
+
+/** Disable CPU queue interrupt
+ * \param[in]   port        port. rdpa_cpu, rdpa_wlan0, rdpa_wlan1
+ * \param[in]   queue       Queue index < num_queues in port tm configuration
+ */
+void rdpa_cpu_int_disable(rdpa_cpu_port port, int queue);
+
+/** Clear CPU queue interrupt
+ * \param[in]   port        port. rdpa_cpu, rdpa_wlan0, rdpa_wlan1
+ * \param[in]   queue       Queue index < num_queues in port tm configuration
+ */
+void rdpa_cpu_int_clear(rdpa_cpu_port port, int queue);
+
+/** Enable Runner interrupt
+ * \param[in]   intr_idx    Interrupt index < 32
+ */
+void rdpa_rnr_int_enable(uint8_t intr_idx);
+
+/** Disable Runner interrupt
+ * \param[in]   intr_idx    Interrupt index < 32
+ */
+void rdpa_rnr_int_disable(uint8_t intr_idx);
+
+/** Clear Runner interrupt
+ * \param[in]   intr_idx    Interrupt index < 32
+ */
+void rdpa_rnr_int_clear(uint8_t intr_idx);
+
+/** @} end of isr Doxygen group */
+
+/** \defgroup cpu_rx Receive
+ * \ingroup cpu
+ * Functions in this group allow to
+ * - Register/unregister per-port and per-queue interrupt handlers
+ * - Register/unregister packet handler
+ * - Pull received packets from port (scheduling) or queue
+ * @{
+ */
+
+/** CPU meter SR validation constants */
+
+
+#ifdef XRDP
+#define RDPA_CPU_METER_MAX_SR       500000     /**< Max CPU meter SR value in pps */
+#define RDPA_CPU_METER_MIN_SR       10         /**< Min CPU meter SR value in pps */
+#define RDPA_CPU_METER_SR_QUANTA    10         /**< CPU meter SR must be a multiple of quanta */
+#else
+#define RDPA_CPU_METER_MAX_SR       40000       /**< Max CPU meter SR value in pps */
+#define RDPA_CPU_METER_MIN_SR       100         /**< Min CPU meter SR value in pps */
+#define RDPA_CPU_METER_SR_QUANTA    100         /**< CPU meter SR must be a multiple of quanta */
+#endif
+
+
+
+/** Reason index. Underlying type of cpu_reason_index aggregate */
+typedef struct
+{
+    rdpa_traffic_dir dir;       /**< Traffic direction */
+    rdpa_cpu_reason reason;     /**< CPU reason */
+#if defined(BCM_DSL_RDP)
+    int table_index;            /**< reason table index */
+#endif
+    int entry_index;            /* Reserved for internal use. */
+} rdpa_cpu_reason_index_t;
+
+/** Reason configuration structure.
+ * Underlying structure for cpu_reason_cfg aggregate
+ */
+typedef struct
+{
+    bdmf_index queue;           /**< reason --> queue mapping */
+    bdmf_index meter;           /**< CPU interface meter index < RDPA_CPU_MAX_METERS or BDMF_INDEX_UNDEFINED */
+    rdpa_ports meter_ports;     /**< Mask of ports for which the policer is active */
+} rdpa_cpu_reason_cfg_t;
+
+/** CPU meter configuration
+ * Underlying structure for cpu_meter_cfg aggregate
+ */
+typedef struct
+{
+    uint32_t sir;               /**< SIR ( packets per sec ) */
+    uint32_t burst_size;        /**< Burst size ( packets ) */
+} rdpa_cpu_meter_cfg_t;
+
+/** L4 dst port to reason configuration
+ * Underlying structure for l4_dst_port_to_reason aggregate
+ */
+typedef struct
+{
+    bdmf_boolean is_tcp;        /**< TCP or UDP */
+    uint16_t l4_dst_port;       /**< l4 dst port */
+    rdpa_cpu_reason reason;     /**< rdpa cpu reason */
+    bdmf_boolean is_static;     /**< static or dynamic */
+    uint8_t refcnt;             /**< reference count */
+} rdpa_l4_dst_port_to_reason_cfg_t;
+
+/** Receive packet info */
+typedef struct
+{
+    rdpa_cpu_reason reason;     /**< trap reason */
+    rdpa_if src_port;           /**< source port */
+    uint16_t vport;
+    uint32_t reason_data;       /**< Reason-specific data.
+                                     For CPU port it usually contains src_flow
+                                     For Wi-Fi port it contains source SSID index in 16 MSB and destination SSID vector in 16 LSB
+                                     It can contain other reason-specific info (such as OAM info, etc.).
+                                */
+    void *data;        /**<data pointer or FPM/BPM hw token*/
+    uint32_t size;        /**<data size */
+    uint32_t data_offset;    /**<data offset inside pointer */
+    struct {
+        uint32_t rx_csum_verified:1;
+        uint32_t reserved:31;
+    };
+    uint32_t dest_ssid;   /** <when traffic is to be forward to WFD */
+    uint32_t wl_metadata; /** wlan metadata */
+    uint16_t ptp_index; /**< index of ptp RX entry */
+    uint8_t mcast_tx_prio; /**< TX priority (0-7) for multicast traffic \XRDP limited */
+    uint8_t color;
+    uint8_t is_exception;
+    uint8_t is_rx_offload;
+    uint8_t is_ucast;
+    uint8_t omci_encrypted_key_index; /**< encrption key-index in NGPON modes */
+} rdpa_cpu_rx_info_t;
+
+/* Extended CPU info (debugging) */
+typedef struct
+{
+    uint8_t valid;                      /**< 1 means that the following fields contain valid data */
+    struct bdmf_object *egress_object;  /**< Egress object (port, tcont, llid) */
+    uint32_t egress_queue_id;           /**< Egress queue_id */
+    uint16_t wan_flow;                  /**< Egress/ingress WAN flow */
+} rdpa_cpu_rx_ext_info_t;
+
+typedef void (*rdpa_cpu_rxq_rx_isr_cb_t)(long isr_priv);
+typedef void (*rdpa_cpu_rxq_rx_cb_t)(long priv, bdmf_sysb sysb, rdpa_cpu_rx_info_t *info);
+typedef void (*rdpa_cpu_rxq_dump_data_cb_t)(bdmf_index queue, bdmf_boolean enabled);
+
+/** Host receive configuration.
+ * Underlying structure of cpu_rx_cfg aggregate.
+ */
+typedef struct {
+    bdmf_boolean  ic_enable; /**< True - Enable. False - Disable */
+#define RDPA_CPU_IC_MAX_PKT_CNT       63
+    uint8_t  ic_max_pktcnt;  /**< Interrupt Coalescing max packet count.
+                                  MAX value 63
+                             */
+#define RDPA_CPU_IC_MAX_TIMEOUT_IN_US 1023
+    uint16_t ic_timeout_us;  /**< The hardware timer period is configured to
+                                  100 us. This means that the timeout period
+                                  will round up to the next 100 us.
+                                  For example, if the timeout is 201 us,
+                                  a timeout will not be identified until 300us.
+                                  This means for practical purposes, the
+                                  timeout value is 100 us, 200 us, 300 us,
+                                  400 us, 500 us, 600 us, 700 us, 800 us,
+                                  900 us, 1000 us and 1100 us.
+                             */
+} rdpa_cpu_rxq_ic_cfg_t;
+
+typedef struct {
+    uint32_t received;
+    uint32_t queued;
+    uint32_t dropped;
+} extern_rxq_stat_t;
+
+typedef void (*extern_rxq_stat_callback)(int qid, extern_rxq_stat_t *stat, bdmf_boolean clear);
+
+typedef void (*reason_stat_extern_callback_t)(uint32_t *stat, rdpa_cpu_reason_index_t *rindex);
+
+#define RDPA_CPU_QUEUE_MAX_SIZE  1024       /**< Maximal Host queue size */
+#define RDPA_CPU_QUEUE_MIN_SIZE  64         /**< Minimal Host queue size */
+#define RDPA_CPU_WLAN_QUEUE_MAX_SIZE  1024  /**< Maximal WFD queue size */
+#define RDPA_FEED_QUEUE_MAX_SIZE  (1024 * 32)  /**< Maximal FEED queue size */
+#if !defined(RDP_SIM) 
+#define RDPA_CPU_TX_RING_HIGH_PRIO_SIZE (1024 *2)  /**< Maximal CPU_TX queue for high priority size */
+#define RDPA_CPU_TX_RING_LOW_PRIO_SIZE (1024 *2)  /**< Maximal CPU_TX queue for low priority size */
+#define RDPA_CPU_TX_RING_SIZE (1024 *2) /**< Maximal CPU_TX queue size for validation */
+#define RDPA_CPU_TX_RING_EXLUSIVE_RESERVED_SIZE 128 /**< Minimal CPU_TX queue size for high priority packets reservation */
+#else
+#define RDPA_CPU_TX_RING_HIGH_PRIO_SIZE (64)  /**< Maximal CPU_TX queue for high priority size */
+#define RDPA_CPU_TX_RING_LOW_PRIO_SIZE (64)  /**< Maximal CPU_TX queue for low priority size */
+#define RDPA_CPU_TX_RING_SIZE (64) /**< Maximal CPU_TX queue size for validation */
+#define RDPA_CPU_TX_RING_EXLUSIVE_RESERVED_SIZE 2 /**< Minimal CPU_TX queue size for high priority packets reservation */
+#endif
+#define RING_NORMAL_PRIO  0
+#define RING_HIGH_PRIO    1   
+
+/** Receive packet info
+*   Underlying structure for cpu_rxq_cfg aggregate
+*/
+typedef struct {
+    /** ISR callback
+     * If set ISR is connected to the appropriate port+queue
+     * \param[in]   isr_priv
+     */
+    rdpa_cpu_rxq_rx_isr_cb_t rx_isr;
+    void *ring_head;            /**< Allocated by client ring */
+    uint32_t size;              /**< Queue size */
+    rdpa_ring_type_t type;               /**< ring type \XRDP_LIMITED */
+    bdmf_boolean dump;          /**< Dump rx data */
+    long isr_priv;              /**< Parameter to be passed to isr callback */
+    rdpa_cpu_rxq_ic_cfg_t ic_cfg; /**< Interrupt Coalescing config */
+    rdpa_cpu_rxq_dump_data_cb_t rx_dump_data_cb; /**< Dump RX data callback */
+    extern_rxq_stat_callback rxq_stat; /**< Optional internal statistics callback */
+    long unsigned int irq_affinity_mask; /**< Queue ISR affinity mask - every bit represents CPU */
+    uint32_t  ring_prio;         /**< Queue Priority - used for buffer allocation request \RDP_LIMITED  */
+} rdpa_cpu_rxq_cfg_t;
+
+/** Receive statistics.
+ * Underlying structure for cpu_rx_stat aggregate
+ */
+typedef struct
+{
+    uint32_t received;      /**< Packets passed to rx callback */
+    uint32_t queued;        /**< Packets in the queue */
+    uint32_t dropped;       /**< Packets dropped by RDD / FW */
+    uint32_t interrupts;    /**< interrupts */
+} rdpa_cpu_rx_stat_t;
+
+/** Cpu loopback type
+ */
+typedef enum
+{
+    rdpa_cpu_loopback_ipsec,      /**< IPsec offload packet loopback */
+
+    rdpa_cpu_loopback__num_of
+} rdpa_cpu_loopback_type;
+
+/** Pull a single received packet from host queue.
+ * This function pulls a single packet from the host queue.
+ * \param[in]   port            CPU port (host, wlan0, wlan1, wlan2)
+ * \param[in]   queue           Queue index < num_queues in rdpa_port_tm_cfg_t or UNASSIGNED
+ * \param[out]  info            Packet info
+ * \return =0:packet pulled ok,  <0:int error code\n
+ */
+int rdpa_cpu_packet_get(rdpa_cpu_port port, bdmf_index queue, rdpa_cpu_rx_info_t *info);
+
+/** Pull a single received packet from host queue with extended RX info.
+ * Extended info is only available for packets redirected to CPU
+ * using system.rx_cpu_redirect attribute
+ *
+ * This function pulls a single packet from the host queue.
+ * \param[in]   port            CPU port (host0, host1, ..)
+ * \param[in]   queue           Queue index < num_queues in rdpa_port_tm_cfg_t or UNASSIGNED
+ * \param[out]  info            Packet info
+ * \param[out]  ext_info        Packet extended info
+ * \return =0:packet pulled ok,  <0:int error code\n
+ */
+int rdpa_cpu_packet_get_redirected(rdpa_cpu_port port, bdmf_index queue,
+    rdpa_cpu_rx_info_t *info, rdpa_cpu_rx_ext_info_t *ext_info);
+
+#define CPU_RX_PACKETS_BULK_SIZE 32
+/** Pull a bulk of received packets from host queue.
+ * This function pulls a bulk of packets from the host queue.
+ * \param[in]   port            CPU port (host, wlan0, wlan1, wlan2)
+ * \param[in]   queue           Queue index < num_queues in rdpa_port_tm_cfg_t or UNASSIGNED
+ * \param[out]  info            Array of packet info structures, sizeof of array is CPU_RX_PACKETS_BULK_SIZE
+ * \param[in]   max_count       Maximal number of packets to read, up to CPU_RX_PACKETS_BULK_SIZE
+ * \param[out]  count           Number of packets actually read
+ * \return =0:no errors occured, <0:int error code\n
+ */
+int rdpa_cpu_packets_bulk_get(rdpa_cpu_port port, bdmf_index queue, rdpa_cpu_rx_info_t *info, int max_count, int *count);
+
+
+/** Pull a single offloaded packet from host queue.
+ * This function receives a single packet that was offloaded from CPU.
+ * \param[in]   loopback_type   Loopback type
+ * \param[in]   queue           Queue index < num_queues in rdpa_port_tm_cfg_t or UNASSIGNED
+ * \param[out]  sysb            Packet data (buffer)
+ * \param[out]  info            Packet info
+ * \return =1:packet pulled ok, ==0:no packet pulled, <0:int error code\n
+ */
+int rdpa_cpu_loopback_packet_get(rdpa_cpu_loopback_type loopback_type, bdmf_index queue,
+                                 bdmf_sysb *sysb, rdpa_cpu_rx_info_t *info);
+
+/** Pull a bulk of received FKB packets from host queue.
+ * This function pulls a bulk of packets from the host queue.
+ * Buffers will be provided with the FKB envelope.
+ * Up to the maximum number of buffers specified via the budget parameter will be returned
+ * to the caller.
+ *
+ * \param[in]   queue_id            CPU RX Queue ID
+ * \param[in]   budget              Maximum number of packets to be read
+ * \param[in]   rx_pkts             Array of received packets
+ * \param[in]   rdpa_cpu_data_p     Opaque CPU handle retrieved via ::rdpa_cpu_data_get() API
+ * \return Number of received packets\n
+ */
+int rdpa_cpu_wfd_bulk_fkb_get(bdmf_index queue_id, unsigned int budget, void **rx_pkts, void *rdpa_cpu_data_p);
+
+/** Pull a bulk of received SKB packets from host queue.
+ * This function pulls a bulk of packets from the host queue.
+ * Buffers will be provided with tghe SKB envelope.
+ * Up to the maximum number of buffers specified via the budget parameter will be returned
+ * to the caller.
+ * \param[in]   queue_id            CPU RX Queue ID
+ * \param[in]   budget              Maximum number of packets to be read
+ * \param[in]   rx_pkts             Array of received packets
+ * \param[in]   rdpa_cpu_data_p     Opaque CPU handle retrieved via ::rdpa_cpu_data_get() API
+ * \return Number of received packets\n
+*/
+int rdpa_cpu_wfd_bulk_skb_get(bdmf_index queue_id, unsigned int budget, void **rx_pkts, void *rdpa_cpu_data_p);
+/** Retrieves Opaque CPU handle
+ * \param[in]   rdpa_cpu_type      CPU port identifier ::rdpa_cpu_port
+ * \return Opaque CPU handle.
+*/
+void *rdpa_cpu_data_get(int rdpa_cpu_type);
+
+
+/** @} end of cpu_rx Doxygen group */
+
+/** \defgroup cpu_tx Transmit
+ * \ingroup cpu
+ * Packets can be transmitted
+ * - via specific port/queue
+ * - using FW bridging & classification logic
+ *
+ * All rdpa_cpu_send_to_xx functions return int error code
+ * - If rc==0, buffer ownership is passed to RDPA. The buffer will be released when safe.
+ * - If rc!=0, buffer ownership stays with the caller
+ * @{
+ */
+
+/** Extra data that can be passed along with the packet to be transmitted */
+typedef union
+{
+    uint32_t u32;
+    struct {
+        uint32_t is_spdsvc_setup_packet :1;  /**<when set, indicates that a Speed Service Setup packet is being transmitted */
+        uint32_t lag_port               :2;  /**<Runner to external switch lag port (EMAC) */
+        uint32_t tc_id                  :6;  /**<traffic class value assigned with this packet */
+        uint32_t unused                 :23;
+    };
+} rdpa_cpu_tx_extra_info_t;
+
+/** Transmit statistics */
+typedef struct
+{
+    uint32_t tx_ok;                     /**< Successfully passed to RDD for transmission */
+    uint32_t tx_invalid_queue;          /**< Discarded because transmit queue is not configured */
+    uint32_t tx_no_buf;                 /**< Discarded because couldn't allocate BPM buffer */
+    uint32_t tx_too_long;               /**< Discarded packets with length > max MTU size */
+    uint32_t tx_rdd_error;              /**< Discarded because RDD returned error */
+} rdpa_cpu_tx_stat_t;
+
+
+/** Send system buffer
+ *
+ * \param[in]   sysb        System buffer. Released regardless on the function outcome
+ * \param[in]   info        Tx info
+ * \return 0=OK or int error code\n
+ */
+int rdpa_cpu_send_sysb(bdmf_sysb sysb, const rdpa_cpu_tx_info_t *info);
+
+/** Send system buffer allocated from FPM
+ *
+ * \param[in] sysb System buffer. Released regardless on the function outcome
+ * \param[in] info Tx info
+ * \return 0=OK or int error code\n
+ */
+int rdpa_cpu_send_sysb_fpm(bdmf_sysb sysb, const rdpa_cpu_tx_info_t *info);
+
+int rdpa_cpu_send_wfd_to_bridge(bdmf_sysb sysb, const rdpa_cpu_tx_info_t *info, size_t offset_next);
+
+#if defined(BCM_DSL_RDP) || defined(BCM_DSL_XRDP)
+/** Send system buffer to Ethernet/DSL WAN Interface
+ *
+ * \param[in]   sysb          System buffer. Released regardless on the function outcome
+ * \param[in]   egress_queue  Ethernet Egress Queue
+ * \return 0=OK or int error code\n
+ */
+int rdpa_cpu_tx_port_enet_or_dsl_wan(bdmf_sysb sysb, uint32_t egress_queue, rdpa_flow wan_flow, rdpa_if wan_if,
+                                     rdpa_cpu_tx_extra_info_t extra_info);
+
+/** Send system buffer to Ethernet LAN Interface
+ *
+ * \param[in]   sysb          System buffer. Released regardless on the function outcome
+ * \param[in]   egress_queue  Ethernet Egress Queue
+ * \param[in]   phys_port     Ethernet LAN physical port
+ * \return 0=OK or int error code\n
+ */
+int rdpa_cpu_tx_port_enet_lan(bdmf_sysb sysb, uint32_t egress_queue,
+                              uint32_t phys_port, rdpa_cpu_tx_extra_info_t extra_info);
+
+/** Send system buffer to Flow Cache Offload
+ *
+ * \param[in] sysb: System buffer. Released regardless on the function outcome
+ * \param[in] cpu_rx_queue: CPU Rx Queue index, in case of Runner Flow miss
+ * \param[in] dirty: Indicates whether a packet flush from D$ is required
+ * \return 0=OK or int error code\n
+ */
+int rdpa_cpu_tx_flow_cache_offload(bdmf_sysb sysb, uint32_t cpu_rx_queue, int dirty);
+
+/** Frees the given free index and returns a pointer to the associated
+ *  System Buffer. It is up to the caller to process the System Buffer.
+ *
+ * \param[in] free_index: Runner free index
+ * \return: Pointer to the associated system buffer\n
+ */
+bdmf_sysb rdpa_cpu_return_free_index(uint16_t free_index);
+
+/** Receive a system buffer (FKB type) from an Ethernet Interface
+ *
+ * \param[in]   queue         CPU RX Queue ID
+ * \param[in]   sysb          System buffer
+ * \param[in]   src_port      Source RDPA Interface
+ * \return 0=OK or int error code\n
+ */
+int rdpa_cpu_host_packet_get_enet(bdmf_index queue, bdmf_sysb *sysb, rdpa_if *src_port);
+
+/** Free all pending Tx Buffers
+ */
+void rdpa_cpu_tx_reclaim(void);
+
+/** Send system buffer to IPsec Offload
+ *
+ * \param[in] sysb: System buffer.
+ * \param[in] dir: Indicates whether the packet is upstream or downstream.
+ * \param[in] esphdr_offset: ESP header byte offset into the packet.
+ * \param[in] sa_index: Entry index of the ddr SA descriptor table.
+ * \param[in] sa_update: 0- sa_index entry of the ddr sa descriptor table is new.
+ *                       1- sa_index entry of the ddr sa descriptor table has been updated..
+ * \param[in] cpu_qid:  Runner - HostCPU queue id
+ * \return 0=OK or int error code\n
+ */
+int rdpa_cpu_tx_ipsec_offload(bdmf_sysb sysb, rdpa_traffic_dir dir, uint8_t esphdr_offset,
+                              uint8_t sa_index, uint8_t sa_update, uint8_t cpu_qid);
+#endif
+
+/** Send raw packet
+ *
+ * \param[in]   data        Packet data
+ * \param[in]   length      Packet length
+ * \param[in]   info        Info
+ * \return 0=OK or int error code\n
+ */
+int rdpa_cpu_send_raw(void *data, uint32_t length, const rdpa_cpu_tx_info_t *info);
+
+/** Get cpu queue emptiness status
+ *
+ * \param[in]   port        CPU port (CPU, PCI1, PCI2)
+ * \param[in]   queue       Queue index < num_queues in rdpa_port_tm_cfg_t or UNASSIGNED
+ * \return 0=no packets are waiting or at least one packet in queue\n
+ */
+int rdpa_cpu_queue_not_empty(rdpa_cpu_port port, bdmf_index queue);
+
+/** Get cpu queue fullness status
+ *
+ * \param[in]   port        CPU port (CPU, PCI1, PCI2)
+ * \param[in]   queue       Queue index < num_queues in rdpa_port_tm_cfg_t or UNASSIGNED
+ * \return 1 = if queue is full or 0 if there is still place to put packets\n
+ */
+int rdpa_cpu_queue_is_full(rdpa_cpu_port port, bdmf_index queue);
+
+
+/** Get the Time Of Day from the FW FIFO, by the ptp index
+ * \param[in]   ptp_index ptp_index is an entry of struct rdpa_cpu_rx_info_t and is copied from struct
+ *                                      CPU_RX_PARAMS on each received packet. It is only relevant on ptp 1588 packets.
+ *                                      By this index we get the corresponding Time Of Day of the received packet.
+ * \param[out]  tod_h                   4 most bytes of the TOD
+ * \param[out]  tod_l                   4 least bytes of the TOD
+ * \param[out]  local_counter_delta     time propagation delta between HW and NP
+ * \return 0=OK or int error code\n */
+int rdpa_cpu_ptp_1588_get_tod(uint16_t ptp_index, uint32_t *tod_h,
+    uint32_t *tod_l, uint16_t *local_counter_delta);
+
+/** Send ptp-1588 system buffer
+*
+* \param[in]   sysb        System buffer. Released regardless on the function outcome
+* \param[in]   info        Tx info
+* \return 0=OK or int error code\n
+*/
+int rdpa_cpu_send_sysb_ptp(bdmf_sysb sysb, const rdpa_cpu_tx_info_t *info);
+
+/** Send system buffer - Special function to send EPON Dying
+ *  Gasp:
+ *
+ * \param[in]   sysb        System buffer. Released regardless on the function outcome
+ * \param[in]   info        Tx info
+ * \return 0=OK or int error code\n
+ *
+ *  */
+int rdpa_cpu_send_epon_dying_gasp(bdmf_sysb sysb, const rdpa_cpu_tx_info_t *info);
+
+/** Check if the reason is supported by port metering
+ * \param[in]   reason        reason to test
+ * \return 0=OK or int error code\n
+ */
+int rdpa_cpu_is_per_port_metering_supported(rdpa_cpu_reason reason);
+
+
+/** @} end of cpu_tx Doxygen group */
+/** @} end of cpu Doxygen group */
+
+rdpa_ports rdpa_ports_all_lan(void);
+
+void rdpa_cpu_rx_dump_packet(char *name, rdpa_cpu_port port,
+    bdmf_index queue, rdpa_cpu_rx_info_t *info, uint32_t dst_ssid);
+
+#ifdef XRDP
+/** Platform buffer */
+typedef void *bdmf_pbuf_t;
+
+static inline void bdmf_pbuf_init(uint32_t size, uint32_t offset) { }
+static inline void bdmf_pbuf_free(bdmf_pbuf_t *pbuf) { }
+static inline int bdmf_pbuf_alloc(void *data, uint32_t length, uint16_t source, bdmf_pbuf_t *pbuf) { return 0; }
+#endif
+
+#if defined(CONFIG_BCM_FCACHE_CLASSIFICATION_BYPASS)
+#define L2_FLOW_P_LEN  4
+typedef struct {
+    union {
+        struct {
+            BE_DECL(
+                uint32_t incarn     :  3; 
+                uint32_t src_port   :  6;
+                uint32_t self       : 23; 
+            )
+            LE_DECL(
+                uint32_t self       : 23;
+                uint32_t src_port   : 6;
+                uint32_t incarn     : 3;
+            )
+        } id;
+        uint32_t word;
+    };
+} fc_class_ctx_t;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* RDPA_CPU_H_ */
+
diff --git a/arch/arm/mach-bcmbca/rdp/rdpa_cpu_basic.h b/arch/arm/mach-bcmbca/rdp/rdpa_cpu_basic.h
new file mode 100755
index 0000000000..b9c61c0ddd
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdpa_cpu_basic.h
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+*  
+*/
+
+
+#ifndef RDPA_CPU_BASIC_H_
+#define RDPA_CPU_BASIC_H_
+
+/** \addtogroup cpu CPU Interface
+ *
+ * @{
+ */
+
+/** CPU trap reasons */
+typedef enum
+{
+    rdpa_cpu_reason_min = 0,
+
+    rdpa_cpu_rx_reason_oam                 = 0, /**< OAM packet */
+    rdpa_cpu_rx_reason_omci                = 1, /**< OMCI packet */
+    rdpa_cpu_rx_reason_flow                = 2,
+    rdpa_cpu_rx_reason_mcast               = 3, /**< Multicat packet */
+    rdpa_cpu_rx_reason_bcast               = 4, /**< Broadcast packet */
+    rdpa_cpu_rx_reason_igmp                = 5, /**< Igmp packet */
+    rdpa_cpu_rx_reason_icmpv6              = 6, /**< Icmpv6 packet */
+    rdpa_cpu_rx_reason_mac_trap_0          = 7,
+    rdpa_cpu_rx_reason_mac_trap_1          = 8,
+    rdpa_cpu_rx_reason_mac_trap_2          = 9,
+    rdpa_cpu_rx_reason_mac_trap_3          = 10,
+    rdpa_cpu_rx_reason_dhcp                = 11, /**< DHCP packet */
+    rdpa_cpu_rx_reason_non_tcp_udp         = 12, /**< Packet is non TCP or UDP */
+    rdpa_cpu_rx_reason_local_ip            = 13, /**< CPU ingress packet copy */
+    rdpa_cpu_rx_reason_hdr_err             = 14, /**< Packet with IP header error */
+    rdpa_cpu_rx_reason_sa_moved            = 15, /**< SA move indication*/
+    rdpa_cpu_rx_reason_unknown_sa          = 16, /**< Unknown SA indication */
+    rdpa_cpu_rx_reason_unknown_da          = 17, /**< Unknown DA indication */
+    rdpa_cpu_rx_reason_ip_frag             = 18, /**< Packet is fragmented */
+    rdpa_cpu_rx_reason_mac_spoofing        = 19, /**< Mac spoofing \XRDP_LIMITED */
+    rdpa_cpu_rx_reason_direct_flow         = 20, /**< Direct flow */
+    rdpa_cpu_rx_reason_mcast_miss          = 21, /**< Multicast flow lookup miss */
+    rdpa_cpu_rx_reason_ipsec               = 22, /**< IPSec RX offload */
+    rdpa_cpu_rx_reason_reserved_0          = 23, /* */
+    rdpa_cpu_rx_reason_reserved_1          = 24, /* */
+    rdpa_cpu_rx_reason_reserved_2          = 25, /* */
+    rdpa_cpu_rx_reason_l2cp                = 26, /* \XRDP_LIMITED */
+    rdpa_cpu_rx_reason_cpu_mirroring       = 27, /* */
+    rdpa_cpu_rx_reason_etype_udef_0        = 28, /**< User defined ethertype 1 */
+    rdpa_cpu_rx_reason_etype_udef_1        = 29, /**< User defined ethertype 2 */
+    rdpa_cpu_rx_reason_etype_udef_2        = 30, /**< User defined ethertype 3 */
+    rdpa_cpu_rx_reason_etype_udef_3        = 31, /**< User defined ethertype 4 */
+    rdpa_cpu_rx_reason_etype_pppoe_d       = 32, /**< PPPoE Discovery */
+    rdpa_cpu_rx_reason_etype_pppoe_s       = 33, /**< PPPoE Source */
+    rdpa_cpu_rx_reason_etype_arp           = 34, /**< Packet with ethertype Arp */
+    rdpa_cpu_rx_reason_etype_ptp_1588      = 35, /**< Packet with ethertype 1588 */
+    rdpa_cpu_rx_reason_etype_802_1x        = 36, /**< Packet with ethertype 802_1x */
+    rdpa_cpu_rx_reason_etype_802_1ag_cfm   = 37, /**< Packet with ethertype v801 Lag CFG*/
+    rdpa_cpu_rx_reason_pci_ip_flow_miss_1  = 38, /**< DHD PCI flow miss radio 1 */
+    rdpa_cpu_rx_reason_pci_ip_flow_miss_2  = 39, /**< DHD PCI flow miss radio 2 */
+    rdpa_cpu_rx_reason_pci_ip_flow_miss_3  = 40, /**< DHD PCI flow miss radio 3 */
+    rdpa_cpu_rx_reason_ip_flow_miss        = 41, /**< Flow miss indication */
+    rdpa_cpu_rx_reason_tcp_flags           = 42, /**< TCP flag indication */
+    rdpa_cpu_rx_reason_ttl_expired         = 43, /**< TTL expired indication */
+    rdpa_cpu_rx_reason_mtu_exceeded        = 44, /**< MTU exceeded indication */
+    rdpa_cpu_rx_reason_l4_icmp             = 45, /**< layer-4 ICMP protocol */
+    rdpa_cpu_rx_reason_l4_esp              = 46, /**< layer-4 ESP protocol */
+    rdpa_cpu_rx_reason_l4_gre              = 47, /**< layer-4 GRE protocol */
+    rdpa_cpu_rx_reason_l4_ah               = 48, /**< layer-4 AH protocol */
+    rdpa_cpu_rx_reason_parser_error        = 49, /**< Error when parsing packet \XRDP_LIMITED */
+    rdpa_cpu_rx_reason_l4_ipv6             = 50, /**< layer-4 IPV6 protocol */
+    rdpa_cpu_rx_reason_l4_udef_0           = 51, /**< User defined layer-4 1 */
+    rdpa_cpu_rx_reason_l4_udef_1           = 52, /**< User defined layer-4 2 */
+    rdpa_cpu_rx_reason_l4_udef_2           = 53, /**< User defined layer-4 3 */
+    rdpa_cpu_rx_reason_l4_udef_3           = 54, /**< User defined layer-4 4 */
+    rdpa_cpu_rx_reason_cpu_redirect        = 55, /**< CPU redirect */
+    rdpa_cpu_rx_reason_udef_0              = 56, /**< User defined 1 */
+    rdpa_cpu_rx_reason_udef_1              = 57, /**< User defined 2 */
+    rdpa_cpu_rx_reason_udef_2              = 58, /**< User defined 3 */
+    rdpa_cpu_rx_reason_udef_3              = 59, /**< User defined 4 */
+    rdpa_cpu_rx_reason_udef_4              = 60, /**< User defined 5 */
+    rdpa_cpu_rx_reason_udef_5              = 61, /**< User defined 6 */
+    rdpa_cpu_rx_reason_udef_6              = 62, /**< User defined 7 */
+    rdpa_cpu_rx_reason_udef_7              = 63, /**< User defined 8 */
+    rdpa_cpu_reason__num_of
+} rdpa_cpu_reason;
+
+#if defined(CONFIG_BCM_REASON_TO_SKB_MARK) || defined(BCM_REASON_TO_SKB_MARK)
+#define WEB_ACCESS_IC_TRAP_REASON  rdpa_cpu_rx_reason_udef_6
+#define WEB_ACCESS_SKB_MARK_PORT   0x5A
+#endif
+
+#if defined(CONFIG_BCM_DSL_XRDP) || defined(CONFIG_BCM_DSL_RDP)
+#define rdpa_cpu_rx_reason_hit_trap_high    rdpa_cpu_rx_reason_udef_4
+#define rdpa_cpu_rx_reason_hit_trap_low     rdpa_cpu_rx_reason_udef_5
+#define rdpa_cpu_rx_reason_ingqos           rdpa_cpu_rx_reason_udef_6
+#define RDPACTL_IC_TRAP_REASON_HIGH         (rdpa_cpu_rx_reason_ingqos - rdpa_cpu_rx_reason_udef_0)
+#define rdpa_cpu_rx_reason_tcpspdtst        rdpa_cpu_rx_reason_udef_7
+#else
+#define rdpa_cpu_rx_reason_tcpspdtst        rdpa_cpu_rx_reason_udef_7
+#endif
+
+/** CPU port */
+typedef enum
+{
+    rdpa_cpu_port_first = 0,
+#ifndef XRDP
+    rdpa_cpu_host = rdpa_cpu_port_first,      /**< Host RX */
+    rdpa_cpu_wlan0,     /**< WLAN 0 TX */
+    rdpa_cpu_wlan1,     /* Reserved for future use */
+#else
+    rdpa_cpu0 = rdpa_cpu_port_first,
+    rdpa_cpu_host = rdpa_cpu0, /**< Host RX */
+    rdpa_cpu1,
+    rdpa_cpu_xtm = rdpa_cpu1, /**< XTM RX */
+    rdpa_cpu2,
+    rdpa_cpu3,
+    rdpa_cpu4,
+    rdpa_cpu_wlan0 = rdpa_cpu4,     /**< WLAN 0 TX */
+    rdpa_cpu5,
+    rdpa_cpu_wlan1 = rdpa_cpu5,
+    rdpa_cpu6,
+    rdpa_cpu_wlan2 = rdpa_cpu6,
+#endif
+    rdpa_cpu_port__num_of,
+    rdpa_cpu_none
+} rdpa_cpu_port;
+
+#define RDPA_CPU_MAX_QUEUES 8 /**< Max number of queues on host port */
+#ifndef XRDP
+#define RDPA_WLAN_MAX_QUEUES 7 /**< Max number of queues on WLAN port */
+#endif
+
+/** TC */
+#define RDPA_CPU_TC_DEFAULT 0
+#define RDPA_CPU_TC_NUM 8
+
+/** CPU reason table indicies */
+#define CPU_REASON_LAN_TABLE_INDEX  0
+#define CPU_REASON_WAN0_TABLE_INDEX 0
+#define CPU_REASON_WAN1_TABLE_INDEX 1
+
+/** @} end of cpu Doxygen group */
+
+/** TC definition */
+typedef enum
+{
+    rdpa_cpu_tc0            = 0, 
+    rdpa_cpu_tc1            = 1, 
+    rdpa_cpu_tc2            = 2,
+    rdpa_cpu_tc3            = 3, 
+    rdpa_cpu_tc4            = 4, 
+    rdpa_cpu_tc5            = 5,
+    rdpa_cpu_tc6            = 6, 
+    rdpa_cpu_tc7            = 7,
+    rdpa_cpu_tc__num_of,
+} rdpa_cpu_tc;
+
+/** \addtogroup cpu_tx Transmit
+ *
+ * @{
+ */
+
+/** CPU tx packet insertion point */
+typedef enum
+{
+    rdpa_cpu_tx_port = 0,           /**< Egress port and priority are specified explicitly. This is the most common mode */
+    rdpa_cpu_tx_egress = 0,         /**< Egress port and priority are specified explicitly. This is the most common mode same as rdpa_cpu_tx_egress*/
+    rdpa_cpu_tx_bridge = 1,         /**< Before bridge forwarding decision, before classification */
+    rdpa_cpu_tx_ingress = 1,        /**< Before bridge forwarding decision, before classification same as rdpa_cpu_tx_bridge*/
+
+    rdpa_cpu_tx_entry__num_of   /**< Number of CPU TX entries */
+} rdpa_cpu_tx_method;
+
+/** Extra data that can be passed along with the packet to be transmitted */
+typedef struct
+{
+    rdpa_cpu_tx_method method;  /**< Packet transmit method */
+    rdpa_if port;               /**< Destination port for method=port, source port for method=bridge */
+    rdpa_cpu_port cpu_port;     /**< CPU object index \XRDP_LIMITED */
+    uint8_t ssid;               /**< SSID, in use when port is wlan */
+    uint8_t lag_index;          /**< lag_index, in use when port is an SF2 port */
+
+    union {
+        /* queue_id in the following substructures must overlap */
+        struct {
+            uint32_t queue_id;          /**< Egress queue id */
+        } lan;
+
+        struct {
+            uint32_t queue_id;          /**< Egress queue id. method=port only */
+            rdpa_flow flow;             /**< Destination flow for method=port, Source flow for method=bridge,port=wan */
+        } wan;
+
+        uint32_t oam_data;              /**< Extra data entry-specific */
+    } x;
+    uint32_t data;   /**<data pointer or FPM/BPM hw token */
+    uint16_t data_offset;    /**<data offset inside pointer */
+    uint16_t data_size; /**<size of actuall data */
+
+    union{
+
+        struct {
+            uint8_t is_spdsvc_setup_packet:1; /**<when set, indicates that a Speed Service Setup packet is being transmitted */
+            uint8_t no_lock:1;            /**< BOOL flag, TRUE=never lock QM access, only for send dying gasp. Default should be FALSE!! */
+            uint8_t reserved:6;
+            } bits;
+         uint8_t flags; 
+    };
+    rdpa_discard_prty drop_precedence; /**< Indicates drop precedence */
+    uint32_t spdt_so_mark; /**< Socket mark for Speed Test */
+#ifdef CONFIG_BCM_PTP_1588    
+    uint32_t ptp_info;
+#endif
+} rdpa_cpu_tx_info_t;
+
+/** @} end of cpu_tx Doxygen group */
+
+#endif /* RDPA_CPU_BASIC_H_ */
diff --git a/arch/arm/mach-bcmbca/rdp/rdpa_types.h b/arch/arm/mach-bcmbca/rdp/rdpa_types.h
new file mode 100755
index 0000000000..8c21d55881
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/rdpa_types.h
@@ -0,0 +1,937 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ *  
+ */
+
+
+#ifndef _RDPA_TYPES_H_
+#define _RDPA_TYPES_H_
+
+/** \defgroup types Commonly used types and constants
+ * @{
+ */
+
+#include "bdmf_data_types.h"
+
+/** Traffic direction */
+typedef enum
+{
+    rdpa_dir_ds,        /**< Downstream */
+    rdpa_dir_us         /**< Upstream */
+} rdpa_traffic_dir;
+
+/** Direction + index, Underlying structure for rdpa_dir_index aggregate */
+typedef struct
+{
+    rdpa_traffic_dir dir;       /** Traffic direction */
+    bdmf_index index;           /** Index */
+} rdpa_dir_index_t;
+
+/** PPPoE header */
+typedef struct
+{
+    uint32_t session;   /**< PPPoE session ID */
+} rdpa_pppoe_t;
+
+/** PBIT */
+typedef uint8_t rdpa_pbit;
+
+/** DSCP */
+typedef uint8_t rdpa_dscp;
+
+/** DSCP pbit dei */
+typedef struct
+{
+    uint8_t pbit;   /**< pbit */
+    uint8_t dei;    /**< pbit */
+} rdpa_pbit_dei_t;
+
+/** Priority */
+typedef uint8_t rdpa_prty;
+
+/** TCONT index */
+typedef uint8_t rdpa_tcont;
+
+/** Dual Stack lite tunnel ID */
+/* this enum is the only modification needed in order to add more than one tunnel */
+typedef enum
+{
+    rdpa_ds_lite_tunnel_0, 
+    rdpa_ds_lite_max_tunnel_id = rdpa_ds_lite_tunnel_0
+} rdpa_ds_lite_tunnel_id;
+
+/** GEM flow ID (internal index) */
+typedef uint16_t rdpa_gem;
+
+/** Ethernet/GEM flow ID */
+typedef uint16_t rdpa_flow;
+
+#define GBE_WAN_FLOW_ID 0 /* not used by xDSL WAN Mode. flows 1-15 are used by DSL WAN modes for 16 channels in multiples upto 255.
+                           *  Any other values would collide with the DSL WAN flows. 
+                           *  values 0x0, 0x10, 0x20... are unused. */
+
+
+/** UNASSIGNED value */
+#define RDPA_VALUE_UNASSIGNED ((unsigned)-1)
+#define RDPA_VALUE_UNMATCHED RDPA_VALUE_UNASSIGNED
+
+/** ANY value */
+#define RDPA_VALUE_ANY ((unsigned)-2)
+
+/** VID/PBIT/DEI */
+#define RDPA_VID_UNTAGGED ((unsigned)-3)
+#define RDPA_MAX_VID 4095
+#define RDPA_MAX_PBIT 7
+#define RDPA_MAX_DEI  1
+
+/** Layer-4 PROTOCOL definitions */
+#define RDPA_INVALID_PROTOCOL (0xFF)
+
+/** TPID Detect.
+ *  A set of TPID values, both pre- and user-defined,
+ *  used to apply tagging classification rules on incoming
+ *  traffic. Accordingly, every packet is classified as Single
+ *  or Double tagged. */
+typedef enum
+{
+    rdpa_tpid_detect_0x8100, /**< Pre-Defined, 0x8100 */
+    rdpa_tpid_detect_0x88A8, /**< Pre-Defined, 0x88A8 */
+    rdpa_tpid_detect_0x9100, /**< Pre-Defined, 0x9100 */
+    rdpa_tpid_detect_0x9200, /**< Pre-Defined, 0x9200 */
+
+    rdpa_tpid_detect_udef_1, /**< User-Defined, #1    */
+    rdpa_tpid_detect_udef_2, /**< User-Defined, #2    */
+
+    rdpa_tpid_detect__num_of
+} rdpa_tpid_detect_t;
+
+
+/** Forwarding action */
+typedef enum
+{
+    rdpa_forward_action_none    = 0,    /** ACL */
+    rdpa_forward_action_forward = 1,    /**< Forward */
+    rdpa_forward_action_host    = 2,    /**< Trap to the host */
+    rdpa_forward_action_drop    = 4,    /**< Discard */
+    rdpa_forward_action_flood   = 8,    /**< Flood, for DA lookup only */
+    rdpa_forward_action_skip   = 16     /**< Skip - used for generic filter for increment counter action only \ XRDP limited */
+} rdpa_forward_action;
+
+/** Filtering action */
+typedef enum {
+    rdpa_filter_action_allow,   /**< Allow through */
+    rdpa_filter_action_deny     /**< Block packet */
+} rdpa_filter_action;
+
+/** QoS mapping method */
+typedef enum
+{
+    rdpa_qos_method_flow,        /**< Flow-based QoS mapping */
+    rdpa_qos_method_pbit       /**< Pbit-based QoS mapping */
+} rdpa_qos_method;
+
+/** Allow frame types */
+typedef enum
+{
+    rdpa_port_allow_any,        /**< Allow tagged and untagged frames */
+    rdpa_port_allow_tagged,     /**< Allow tagged frames only */
+    rdpa_port_allow_untagged,   /**< Allow untagged frames only */
+} rdpa_port_frame_allow;
+
+/** Forwarding mode */
+typedef enum
+{
+    rdpa_forwarding_mode_pkt,   /**< Packet-based forwarding */
+    rdpa_forwarding_mode_flow,  /**< Flow-based forwarding */
+} rdpa_forwarding_mode;
+
+/** DS Ethernet flow classification mode */
+typedef enum
+{
+    rdpa_classify_mode_pkt,     /**< Packet-based classification */
+    rdpa_classify_mode_flow,    /**< Flow-based classification */
+} rdpa_classify_mode;
+
+/** Discard priority */
+typedef enum
+{
+    rdpa_discard_prty_low,      /**< Low priority for Ingress QoS: traffic dropped under high ingress congestion */
+    rdpa_discard_prty_high      /**< High priority for Ingress QoS: traffic passed under high ingress congresion */
+} rdpa_discard_prty;
+
+/** Flow destination */
+typedef enum
+{
+    rdpa_flow_dest_none,        /**< Not set */
+
+    rdpa_flow_dest_iptv,        /**< IPTV */
+    rdpa_flow_dest_eth,         /**< Flow */
+    rdpa_flow_dest_omci,        /**< OMCI */
+
+    rdpa_flow_dest__num_of,     /* Number of values in rdpa_flow_destination enum */
+} rdpa_flow_destination;
+
+/** WAN technology */
+typedef enum
+{
+    rdpa_wan_none,              /**< Not configured */
+    rdpa_wan_gpon,              /**< GPON */
+    rdpa_wan_xgpon,             /**< XGPON */
+    rdpa_wan_epon,              /**< EPON */
+    rdpa_wan_xepon,             /**< XEPON */
+    rdpa_wan_gbe,               /**< GbE */
+    rdpa_wan_dsl,               /**< xDSL */
+    rdpa_wan_type__num_of
+} rdpa_wan_type;
+
+/** Link speed */
+typedef enum
+{
+    rdpa_speed_none,            /**< Not configured */
+    rdpa_speed_100m,            /**< Speed of 100 Mega */
+    rdpa_speed_1g,              /**< Speed of 1 Giga */
+    rdpa_speed_2_5g,            /**< Speed of 2.5 Giga */
+    rdpa_speed_5g,              /**< Speed of 5 Giga */
+    rdpa_speed_10g,             /**< Speed of 10 Giga */
+} rdpa_speed_type;
+
+/** Simple statistics */
+typedef struct
+{
+    uint32_t packets;           /**< Packets */
+    uint32_t bytes;             /**< Bytes */
+} rdpa_stat_t;
+
+/** Generic 1-way statistics */
+typedef struct
+{
+    rdpa_stat_t passed;         /**< Passed statistics */
+    rdpa_stat_t discarded;      /**< Discarded statistics */
+} rdpa_stat_1way_t;
+
+/** Tx+Rx statistics */
+typedef struct
+{
+    rdpa_stat_1way_t tx;        /**< Transmit statistics */
+    rdpa_stat_1way_t rx;        /**< Receive statistics */
+} rdpa_stat_tx_rx_t;
+
+/** Tx+Rx statistics for passed packets + bytes  */
+typedef struct
+{
+    rdpa_stat_t tx;             /**< Transmit statistics */
+    rdpa_stat_t rx;             /**< Receive statistics */
+} rdpa_stat_tx_rx_valid_t;
+
+/** RDPA interface (port).
+ * The enum includes physical and virtual ports that
+ * can appear in bridging / routing rules as ingress or egress interface.
+ * The port list does not include VLAN-based virtual interfaces and tunnels.
+ * Aggregation ports, such as PCI and SWITCH, can be used in 2-level scheduling.
+ */
+typedef enum
+{
+    rdpa_if_first,          /*< First interface */
+
+    /** WAN ports */
+    rdpa_if_wan0 = rdpa_if_first, /**< WAN0 port */
+    rdpa_if_wan1,           /**< WAN1 port */
+    rdpa_if_wan2,           /**< WAN2 port */
+    rdpa_if_wan_max = rdpa_if_wan2,
+    /** LAN ports */
+    rdpa_if_lan0,           /**< LAN0 port */
+    rdpa_if_lan1,           /**< LAN1 port */
+    rdpa_if_lan2,           /**< LAN2 port */
+    rdpa_if_lan3,           /**< LAN3 port */
+    rdpa_if_lan4,           /**< LAN4 port */
+    rdpa_if_lan5,           /**< LAN5 port */
+    rdpa_if_lan6,           /**< LAN6 port */
+    rdpa_if_lan7,           /**< LAN7 port */
+#if defined(BCM_DSL_RDP) || defined(BCM_DSL_XRDP)
+    rdpa_if_lan_max = rdpa_if_lan7,
+#else /* DSL Platforms */
+    rdpa_if_lan8,           /**< LAN8 port */
+    rdpa_if_lan9,           /**< LAN9 port */
+    rdpa_if_lan10,           /**< LAN10 port */
+    rdpa_if_lan11,           /**< LAN11 port */
+    rdpa_if_lan12,           /**< LAN12 port */
+    rdpa_if_lan13,           /**< LAN13 port */
+    rdpa_if_lan14,           /**< LAN14 port */
+    rdpa_if_lan15,           /**< LAN15 port */
+    rdpa_if_lan16,           /**< LAN16 port */
+    rdpa_if_lan17,           /**< LAN17 port */
+    rdpa_if_lan18,           /**< LAN18 port */
+    rdpa_if_lan19,           /**< LAN19 port */
+    rdpa_if_lan20,           /**< LAN20 port */
+    rdpa_if_lan21,           /**< LAN21 port */
+#ifdef G9991
+    rdpa_if_lan22,           /**< LAN22 port */
+    rdpa_if_lan23,           /**< LAN23 port */
+    rdpa_if_lan24,           /**< LAN24 port */
+    rdpa_if_lan25,           /**< LAN25 port */
+    rdpa_if_lan26,           /**< LAN26 port */
+    rdpa_if_lan27,           /**< LAN27 port */
+    rdpa_if_lan28,           /**< LAN28 port */
+    rdpa_if_lan29,           /**< LAN29 port */
+    rdpa_if_lan_max = rdpa_if_lan29,
+#else
+    rdpa_if_lan_max = rdpa_if_lan21,
+#endif
+#endif /* PON Platforms */
+    /** Special ports */
+    rdpa_if_lag0,           /**< Physical emac0 port */
+    rdpa_if_lag1,           /**< Physical emac1 port */
+    rdpa_if_lag2,           /**< Physical emac2 port */
+    rdpa_if_lag3,           /**< Physical emac3 port */
+    rdpa_if_lag4,           /**< Physical emac4 port */
+    rdpa_if_lag_max = rdpa_if_lag4,
+
+    /** Switch aggregate port */
+    rdpa_if_switch,         /**< LAN switch port */
+
+#ifndef XRDP
+    /** CPU ports for WLAN usage (local termination) */
+    rdpa_if_wlan0,
+    rdpa_if_cpu_first = rdpa_if_wlan0,
+    rdpa_if_wlan1,
+    rdpa_if_wlan_last = rdpa_if_wlan1,
+    /** CPU (local termination) */
+    rdpa_if_cpu,                /**< CPU port (local termination) */
+
+    rdpa_if_max_mcast_port = rdpa_if_cpu, /* only above ports could be part of mcast egress port mask */
+
+    /** Wi-Fi logical ports (SSIDs) */
+    rdpa_if_ssid0,          /**< Wi-Fi: SSID0 */
+    rdpa_if_ssid1,          /**< Wi-Fi: SSID1 */
+    rdpa_if_ssid2,          /**< Wi-Fi: SSID2 */
+    rdpa_if_ssid3,          /**< Wi-Fi: SSID3 */
+    rdpa_if_ssid4,          /**< Wi-Fi: SSID4 */
+    rdpa_if_ssid5,          /**< Wi-Fi: SSID5 */
+    rdpa_if_ssid6,          /**< Wi-Fi: SSID6 */
+    rdpa_if_ssid7,          /**< Wi-Fi: SSID7 */
+    rdpa_if_ssid8,          /**< Wi-Fi: SSID8 */
+    rdpa_if_ssid9,          /**< Wi-Fi: SSID9 */
+    rdpa_if_ssid10,         /**< Wi-Fi: SSID10 */
+    rdpa_if_ssid11,         /**< Wi-Fi: SSID11 */
+    rdpa_if_ssid12,         /**< Wi-Fi: SSID12 */
+    rdpa_if_ssid13,         /**< Wi-Fi: SSID13 */
+    rdpa_if_ssid14,         /**< Wi-Fi: SSID14 */
+    rdpa_if_ssid15,         /**< Wi-Fi: SSID15 */
+    rdpa_if_cpu_last = rdpa_if_ssid15,
+#else
+    /** CPU ports (local termination) */
+    rdpa_if_cpu0, /**< CPU0 port (local termination) */
+    rdpa_if_cpu_first = rdpa_if_cpu0,
+    rdpa_if_cpu = rdpa_if_cpu0,
+    rdpa_if_max_mcast_port = rdpa_if_cpu, /* only above ports could be part of mcast egress port mask */
+    rdpa_if_cpu1,           /**< CPU1 port (local termination) */
+    rdpa_if_cpu2,           /**< CPU2 port (local termination) */
+    rdpa_if_cpu3,           /**< CPU3 port (local termination) */
+    rdpa_if_wlan0,           /**< CPU port (local termination) reserved for WLAN0 */
+    rdpa_if_wlan1,           /**< CPU port (local termination) reserved for WLAN1 */
+    rdpa_if_wlan2,           /**< CPU port (local termination) reserved for WLAN2 */
+    rdpa_if_wlan_last = rdpa_if_wlan2,
+    rdpa_if_cpu_last = rdpa_if_wlan2,
+#endif
+
+    rdpa_if_bond0,          /**< Virtual Port bonding interface 0 */
+    rdpa_if_bond1,          /**< Virtual Port bonding interface 1 */
+    rdpa_if_bond2,          /**< Virtual Port bonding interface 2 */
+    rdpa_if_bond_max = rdpa_if_bond2,
+    rdpa_if_any,            /**< Any Port */
+
+
+    rdpa_if__number_of,
+
+    rdpa_if_none            /**< No port */
+
+} rdpa_if;
+
+typedef enum 
+{
+    rdpa_wlan_ssid0,
+    rdpa_wlan_ssid1,
+    rdpa_wlan_ssid2,
+    rdpa_wlan_ssid3,
+    rdpa_wlan_ssid4,
+    rdpa_wlan_ssid5,
+    rdpa_wlan_ssid6,
+    rdpa_wlan_ssid7,
+    rdpa_wlan_ssid8,
+    rdpa_wlan_ssid9,
+    rdpa_wlan_ssid10,
+    rdpa_wlan_ssid11,
+    rdpa_wlan_ssid12,
+    rdpa_wlan_ssid13,
+    rdpa_wlan_ssid14,
+    rdpa_wlan_ssid15,
+} rdpa_wlan_ssid;
+
+/** EMAC id */
+typedef enum
+{
+    rdpa_emac0,             /**< EMAC0 */
+    rdpa_emac1,             /**< EMAC1 */
+    rdpa_emac2,             /**< EMAC2 */
+    rdpa_emac3,             /**< EMAC3 */
+    rdpa_emac4,             /**< EMAC4 */
+    rdpa_emac5,             /**< EMAC5 */
+    rdpa_emac6,             /**< EMAC6 */
+    rdpa_emac7,             /**< EMAC7 */
+    rdpa_emac__num_of,      /* Max number of EMACs */
+    rdpa_emac_none,      /**< Indicates virtual port */
+} rdpa_emac;
+
+/** EMAC mode */
+typedef enum
+{
+    rdpa_emac_mode_sgmii,   /**< SGMII */
+    rdpa_emac_mode_hisgmii, /**< HISGMII */
+    rdpa_emac_mode_qsgmii,  /**< QSGMII */
+    rdpa_emac_mode_ss_smii, /**< SS SMII */
+    rdpa_emac_mode_rgmii,   /**< RGMII */
+    rdpa_emac_mode_mii,     /**< MII */
+    rdpa_emac_mode_tmii,    /**< TMII */
+
+    rdpa_emac_mode__num_of, /* Number of EMAC modes */
+} rdpa_emac_mode;
+
+
+/** EMAC rates */
+typedef enum
+{
+    rdpa_emac_rate_10m,     /**< 10 Mbps */
+    rdpa_emac_rate_100m,    /**< 100 Mbps */
+    rdpa_emac_rate_1g,      /**< 1 Gbps */
+    rdpa_emac_rate_2_5g,    /**< 2.5 Gbps */
+
+    rdpa_emac_rate__num_of, /* Number of rates */
+} rdpa_emac_rate;
+
+/** EMAC configuration */
+typedef struct
+{
+    char loopback;      /**< 1 = line loopback */
+    rdpa_emac_rate rate;       /**< EMAC rate */
+    char generate_crc;  /**< 1 = generate CRC */
+    char full_duplex;   /**< 1 = full duplex */
+    char pad_short;     /**< 1 = pad short frames */
+    char allow_too_long;/**< 1 = allow long frames */
+    char check_length;  /**< 1 = check frame length */
+    uint32_t preamble_length;   /**< Preamble length */
+    uint32_t back2back_gap;     /**< Back2Back inter-packet gap */
+    uint32_t non_back2back_gap; /**< Non Back2Back inter-packet gap */
+    uint32_t min_interframe_gap; /**< Min inter-frame gap */
+    char rx_flow_control;/**< 1 = enable RX flow control */
+    char tx_flow_control;/**< 1 = enable TX flow control */
+} rdpa_emac_cfg_t;
+
+/** RX RMON counters.
+ * Underlying type for emac_rx_stat aggregate type.
+ */
+typedef struct
+{
+    uint32_t byte;              /**< Receive Byte Counter */
+    uint32_t packet;            /**< Receive Packet Counter */
+    uint32_t frame_64;          /**< Receive 64 Byte Frame Counter */
+    uint32_t frame_65_127;      /**< Receive 65 to 127 Byte Frame Counter */
+    uint32_t frame_128_255;     /**< Receive 128 to 255 Byte Frame Counter */
+    uint32_t frame_256_511;     /**< Receive 256 to 511 Byte Frame Counter */
+    uint32_t frame_512_1023;    /**< Receive 512 to 1023 Byte Frame Counter */
+    uint32_t frame_1024_1518;   /**< Receive 1024 to 1518 Byte Frame Counter */
+    uint32_t frame_1519_mtu;    /**< Receive 1519 to MTU Frame Counter */
+    uint32_t multicast_packet;  /**< Receive Multicast Packet */
+    uint32_t broadcast_packet;  /**< Receive Broadcast Packet */
+    uint32_t unicast_packet;    /**< Receive Unicast Packet */
+    uint32_t alignment_error;   /**< Receive Alignment error */
+    uint32_t frame_length_error;/**< Receive Frame Length Error Counter */
+    uint32_t code_error;        /**< Receive Code Error Counter */
+    uint32_t carrier_sense_error;/**< Receive Carrier sense error */
+    uint32_t fcs_error;         /**< Receive FCS Error Counter */
+    uint32_t control_frame;     /**< Receive Control Frame Counter */
+    uint32_t pause_control_frame;/**< Receive Pause Control Frame */
+    uint32_t unknown_opcode;    /**< Receive Unknown opcode */
+    uint32_t undersize_packet;  /**< Receive Undersize Packet */
+    uint32_t oversize_packet;   /**< Receive Oversize Packet */
+    uint32_t fragments;         /**< Receive Fragments */
+    uint32_t jabber;            /**< Receive Jabber counter */
+    uint32_t overflow;          /**< Receive Overflow counter */
+} rdpa_emac_rx_stat_t;
+
+/** Tx RMON counters.
+ * Underlying type for emac_tx_stat aggregate type.
+ */
+typedef struct
+{
+    uint32_t byte;              /**< Transmit Byte Counter */
+    uint32_t packet;            /**< Transmit Packet Counter */
+    uint32_t frame_64;          /**< Transmit 64 Byte Frame Counter */
+    uint32_t frame_65_127;      /**< Transmit 65 to 127 Byte Frame Counter */
+    uint32_t frame_128_255;     /**< Transmit 128 to 255 Byte Frame Counter */
+    uint32_t frame_256_511;     /**< Transmit 256 to 511 Byte Frame Counter */
+    uint32_t frame_512_1023;    /**< Transmit 512 to 1023 Byte Frame Counter */
+    uint32_t frame_1024_1518;   /**< Transmit 1024 to 1518 Byte Frame Counter */
+    uint32_t frame_1519_mtu;    /**< Transmit 1519 to MTU Frame Counter */
+    uint32_t fcs_error;         /**< Transmit FCS Error */
+    uint32_t multicast_packet;  /**< Transmit Multicast Packet */
+    uint32_t broadcast_packet;  /**< Transmit Broadcast Packet */
+    uint32_t unicast_packet;    /**< Transmit Unicast Packet */
+    uint32_t excessive_collision; /**< Transmit Excessive collision counter */
+    uint32_t late_collision;    /**< Transmit Late collision counter */
+    uint32_t single_collision;  /**< Transmit Single collision frame counter */
+    uint32_t multiple_collision;/**< Transmit Multiple collision frame counter */
+    uint32_t total_collision;   /**< Transmit Total Collision Counter */
+    uint32_t pause_control_frame; /**< Transmit PAUSE Control Frame */
+    uint32_t deferral_packet;   /**< Transmit Deferral Packet */
+    uint32_t excessive_deferral_packet; /**< Transmit Excessive Deferral Packet */
+    uint32_t jabber_frame;      /**< Transmit Jabber Frame */
+    uint32_t control_frame;     /**< Transmit Control Frame */
+    uint32_t oversize_frame;    /**< Transmit Oversize Frame counter */
+    uint32_t undersize_frame;   /**< Transmit Undersize Frame */
+    uint32_t fragments_frame;   /**< Transmit Fragments Frame counter */
+    uint32_t error;             /**< Transmission errors*/
+    uint32_t underrun;          /**< Transmission underrun */
+} rdpa_emac_tx_stat_t;
+
+/** Emac statistics */
+typedef struct
+{
+    rdpa_emac_rx_stat_t rx; /**< Emac Receive Statistics */
+    rdpa_emac_tx_stat_t tx; /**< Emac Transmit Statistics */
+} rdpa_emac_stat_t;
+
+/** RDPA EMAC mask
+ * A combination of \ref rdpa_emac_id constants.
+ */
+typedef unsigned int rdpa_emacs;
+
+/** RDPA emac mask.
+ * \param[in] __emac EMAC
+ * \return EMAC - Mask representation
+ */
+static inline rdpa_emacs rdpa_emac_id(rdpa_emac __emac)
+{
+    return 1 << (__emac);
+}
+
+/** RDPA port mask
+ * A combination of \ref rdpa_if_id constants.
+ */
+typedef uint64_t rdpa_ports __attribute__((aligned(8)));
+
+/** RDPA interface (port) mask.
+ * Can be combined in rdpa_ports mask to specify multiple ports in the same operation.
+ * \param[in] __if Interface
+ * \return Interface - Mask representation
+ */
+static inline rdpa_ports rdpa_if_id(rdpa_if __if)
+{
+    return 1LL << (__if);
+}
+
+/** All WAN ports */
+#define RDPA_PORT_ALL_WAN   (rdpa_if_id(rdpa_if_wan0) | rdpa_if_id(rdpa_if_wan1) | rdpa_if_id(rdpa_if_wan2))
+
+/** Check if interface is WAN interface
+ * \param[in]   __if     Interface
+ * \return 1 WAN, 0 otherwise
+ */
+static inline int rdpa_if_is_wan(rdpa_if __if)
+{
+    return (RDPA_PORT_ALL_WAN & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+/** Map a given WAN type to the corresponding WAN interface per the platform support.
+ * \param[in]   __wan    WAN type 
+ * \return Interface (rdpa_if_wan0/1/2) or rdpa_if_none if wan_type is not supported on the platform
+ */
+static inline rdpa_if rdpa_wan_type_to_if(rdpa_wan_type __wan)
+{
+#if defined(DSL_63138) || defined(DSL_63148) || defined(CHIP_63138) || defined(CHIP_63148)
+   switch (__wan) {
+      case rdpa_wan_gbe       :
+         return (rdpa_if_wan0);
+      case rdpa_wan_dsl       :
+         return (rdpa_if_wan1);
+      default                 :
+         return (rdpa_if_none);
+   }
+#elif defined(WL4908) || defined(CHIP_4908)
+   switch (__wan) {
+      case rdpa_wan_gbe       :
+         return (rdpa_if_wan0);
+      default                 :
+         return (rdpa_if_none);
+   }
+#elif defined(BCM63158) || defined(CHIP_63158)
+   switch (__wan) {
+      case rdpa_wan_gbe       :
+         return (rdpa_if_wan0);
+      case rdpa_wan_dsl       :
+         return (rdpa_if_wan1);
+      case rdpa_wan_gpon      :
+      case rdpa_wan_xgpon     :
+      case rdpa_wan_epon      :
+      case rdpa_wan_xepon     :
+         return (rdpa_if_wan2);
+      default                 :
+         return (rdpa_if_none);
+   }
+#elif defined(BCM63146) || defined(CHIP_63146)
+   switch (__wan) {
+      case rdpa_wan_gbe       :
+         return (rdpa_if_wan0);
+      case rdpa_wan_dsl       :
+         return (rdpa_if_wan1);
+      default                 :
+         return (rdpa_if_none);
+   }
+#else /* PON Platforms */
+   switch (__wan) {
+      case rdpa_wan_gpon      :
+      case rdpa_wan_xgpon     :
+      case rdpa_wan_epon      :
+      case rdpa_wan_xepon     :
+         return (rdpa_if_wan0);
+      case rdpa_wan_gbe       :
+#ifdef CONFIG_MULTI_WAN_SUPPORT
+         return (rdpa_if_wan1);
+#else
+         return (rdpa_if_wan0);
+#endif
+      default                 :
+         return (rdpa_if_none);
+   }
+#endif /* PON Platforms */
+}
+
+/** All LAN MACs */
+#ifndef XRDP
+#define RDPA_PORT_ALL_LOOKUP_PORTS \
+    (rdpa_if_id(rdpa_if_wan0) | rdpa_if_id(rdpa_if_lan0) | rdpa_if_id(rdpa_if_lan1) | rdpa_if_id(rdpa_if_lan2) | \
+        rdpa_if_id(rdpa_if_lan3) | rdpa_if_id(rdpa_if_lan4))
+#endif
+/** All LAN MACs */
+#ifdef G9991
+#define RDPA_PORT_ALL_LAN_MACS \
+    (rdpa_if_id(rdpa_if_lan0) | rdpa_if_id(rdpa_if_lan1) | rdpa_if_id(rdpa_if_lan2) | \
+     rdpa_if_id(rdpa_if_lan3) | rdpa_if_id(rdpa_if_lan4) | rdpa_if_id(rdpa_if_lan5) | \
+     rdpa_if_id(rdpa_if_lan6) | rdpa_if_id(rdpa_if_lan7) | rdpa_if_id(rdpa_if_lan8) | \
+     rdpa_if_id(rdpa_if_lan9) | rdpa_if_id(rdpa_if_lan10) | rdpa_if_id(rdpa_if_lan11) | \
+     rdpa_if_id(rdpa_if_lan12) | rdpa_if_id(rdpa_if_lan13) | rdpa_if_id(rdpa_if_lan14) | \
+     rdpa_if_id(rdpa_if_lan15) | rdpa_if_id(rdpa_if_lan16) | rdpa_if_id(rdpa_if_lan17) | \
+     rdpa_if_id(rdpa_if_lan18) | rdpa_if_id(rdpa_if_lan19) | rdpa_if_id(rdpa_if_lan20) | \
+     rdpa_if_id(rdpa_if_lan21) | rdpa_if_id(rdpa_if_lan22) | rdpa_if_id(rdpa_if_lan23) | \
+     rdpa_if_id(rdpa_if_lan24) | rdpa_if_id(rdpa_if_lan25) | rdpa_if_id(rdpa_if_lan26) | \
+     rdpa_if_id(rdpa_if_lan27) | rdpa_if_id(rdpa_if_lan28) | rdpa_if_id(rdpa_if_lan29))
+#elif defined(BCM_DSL_RDP) || defined(BCM_DSL_XRDP)
+#define RDPA_PORT_ALL_LAN_MACS \
+    (rdpa_if_id(rdpa_if_lan0) | rdpa_if_id(rdpa_if_lan1) | rdpa_if_id(rdpa_if_lan2) | \
+     rdpa_if_id(rdpa_if_lan3) | rdpa_if_id(rdpa_if_lan4) | rdpa_if_id(rdpa_if_lan5) | \
+     rdpa_if_id(rdpa_if_lan6) | rdpa_if_id(rdpa_if_lan7))
+#else
+#define RDPA_PORT_ALL_LAN_MACS \
+    (rdpa_if_id(rdpa_if_lan0) | rdpa_if_id(rdpa_if_lan1) | rdpa_if_id(rdpa_if_lan2) | \
+     rdpa_if_id(rdpa_if_lan3) | rdpa_if_id(rdpa_if_lan4) | rdpa_if_id(rdpa_if_lan5) | \
+     rdpa_if_id(rdpa_if_lan6) | rdpa_if_id(rdpa_if_lan7) | rdpa_if_id(rdpa_if_lan8) | \
+     rdpa_if_id(rdpa_if_lan9) | rdpa_if_id(rdpa_if_lan10) | rdpa_if_id(rdpa_if_lan11) | \
+     rdpa_if_id(rdpa_if_lan12) | rdpa_if_id(rdpa_if_lan13) | rdpa_if_id(rdpa_if_lan14) | \
+     rdpa_if_id(rdpa_if_lan15) | rdpa_if_id(rdpa_if_lan16) | rdpa_if_id(rdpa_if_lan17) | \
+     rdpa_if_id(rdpa_if_lan18) | rdpa_if_id(rdpa_if_lan19) | rdpa_if_id(rdpa_if_lan20) | \
+     rdpa_if_id(rdpa_if_lan21))
+#endif
+
+/** All physical ports */
+#define RDPA_PORT_LAG_AND_SWITCH_PORTS \
+    (rdpa_if_id(rdpa_if_lag0) | rdpa_if_id(rdpa_if_lag1) | rdpa_if_id(rdpa_if_lag2) | \
+        rdpa_if_id(rdpa_if_lag3) | rdpa_if_id(rdpa_if_lag4) | rdpa_if_id(rdpa_if_switch))
+
+/** All EMACs */
+#ifndef XRDP
+#define RDPA_PORT_ALL_EMACS \
+    (rdpa_emac_id(rdpa_emac0) | rdpa_emac_id(rdpa_emac1) | rdpa_emac_id(rdpa_emac2) | \
+        rdpa_emac_id(rdpa_emac3) | rdpa_emac_id(rdpa_emac4) | rdpa_emac_id(rdpa_emac5))
+#else
+#define RDPA_PORT_ALL_EMACS \
+    (rdpa_emac_id(rdpa_emac0) | rdpa_emac_id(rdpa_emac1) | rdpa_emac_id(rdpa_emac2) | \
+        rdpa_emac_id(rdpa_emac3) | rdpa_emac_id(rdpa_emac4) | rdpa_emac_id(rdpa_emac5) |\
+        rdpa_emac_id(rdpa_emac6))
+#endif
+
+/** All LAN ports */
+#define RDPA_PORT_ALL_LAN (RDPA_PORT_ALL_LAN_MACS)
+/** All LAN ports and physical */
+#define RDPA_PORT_ALL_LAN_AND_LAG (RDPA_PORT_ALL_LAN_MACS | RDPA_PORT_LAG_AND_SWITCH_PORTS)
+
+/** Check if interface is LAN interface (LAN EMAC port or LAN switch port, not including Wi-Fi ports)
+ * \param[in]   __if     Interface
+ * \return 1 LAN (port or switch), 0 otherwise
+ */
+static inline int rdpa_if_is_lan(rdpa_if __if)
+{
+    return (RDPA_PORT_ALL_LAN & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+/** Check if interface is LAN interface (LAN EMAC port, not including WiFi ports)
+ * \param[in]   __if     Interface
+ * \return 1 LAN , 0 otherwise
+ */
+static inline int rdpa_if_is_lan_mac(rdpa_if __if)
+{
+    return (RDPA_PORT_ALL_LAN_MACS & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+/** Check if interface is LAN interface (LAN EMAC port or physical port)
+ * \param[in]   __if     Interface
+ * \return 1 LAN (port or phisical), 0 otherwise
+ */
+static inline int rdpa_if_is_lan_lag_and_switch(rdpa_if __if)
+{
+    return (RDPA_PORT_ALL_LAN_AND_LAG & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+
+/** Check if interface is LAG interface (physical port)
+ * \param[in]   __if     Interface
+ * \return 1 LAN (port or phisical), 0 otherwise
+ */
+static inline int rdpa_if_is_lag_and_switch(rdpa_if __if)
+{
+    return (RDPA_PORT_LAG_AND_SWITCH_PORTS & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+/** All WLAN ports */
+#ifdef XRDP
+#define RDPA_PORT_ALL_WLAN \
+    (rdpa_if_id(rdpa_if_wlan0) | rdpa_if_id(rdpa_if_wlan1) | rdpa_if_id(rdpa_if_wlan2))
+#else
+#define RDPA_PORT_ALL_WLAN \
+    (rdpa_if_id(rdpa_if_wlan0) | rdpa_if_id(rdpa_if_wlan1))
+#endif
+
+/** Check if interface is WLAN (PCI port)
+ * \param[in]   __if     Interface
+ * \return 1 if WLAN port, 0 otherwise
+ */
+static inline int rdpa_if_is_wlan(rdpa_if __if)
+{
+    return (RDPA_PORT_ALL_WLAN & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+#if defined(CONFIG_BCM_PON_XRDP) || defined(BCM_DSL_XRDP)
+#define WL_NUM_OF_SSID_PER_UNIT        16
+#else
+#define WL_NUM_OF_SSID_PER_UNIT        8
+#endif /* CONFIG_BCM_PON */
+
+/** All Bond ports */
+#define RDPA_PORT_ALL_BOND \
+    (rdpa_if_id(rdpa_if_bond0) | rdpa_if_id(rdpa_if_bond1) | rdpa_if_id(rdpa_if_bond2))
+
+/** Check if interface is Bonded
+ * \param[in]   __if     Interface
+ * \return 1 if Bond port, 0 otherwise
+ */
+static inline int rdpa_if_is_bond(rdpa_if __if)
+{
+    return (RDPA_PORT_ALL_BOND & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+
+#ifndef XRDP
+/** All WiFi virtual interfaces */
+#define RDPA_PORT_ALL_SSIDS \
+    (rdpa_if_id(rdpa_if_ssid0) | rdpa_if_id(rdpa_if_ssid1) | rdpa_if_id(rdpa_if_ssid2) | rdpa_if_id(rdpa_if_ssid3) | \
+        rdpa_if_id(rdpa_if_ssid4) | rdpa_if_id(rdpa_if_ssid5) | rdpa_if_id(rdpa_if_ssid6) | rdpa_if_id(rdpa_if_ssid7) | \
+        rdpa_if_id(rdpa_if_ssid8) | rdpa_if_id(rdpa_if_ssid9) | rdpa_if_id(rdpa_if_ssid10) | rdpa_if_id(rdpa_if_ssid11) | \
+        rdpa_if_id(rdpa_if_ssid12) | rdpa_if_id(rdpa_if_ssid13) | rdpa_if_id(rdpa_if_ssid14) | rdpa_if_id(rdpa_if_ssid15))
+
+/** Check if interface is Wi-Fi SSID
+ * \param[in]   __if     Interface
+ * \return 1 Wi-Fi SSID, 0 otherwise
+ */
+static inline int rdpa_if_is_wifi(rdpa_if __if)
+{
+    return (RDPA_PORT_ALL_SSIDS & rdpa_if_id(__if)) ? 1 : 0;
+}
+#else
+static inline int rdpa_if_is_wifi(rdpa_if __if)
+{
+    return rdpa_if_is_wlan(__if);
+}
+#endif
+
+static inline int rdpa_if_is_cpu_port(rdpa_if __if)
+{
+    return __if >= rdpa_if_cpu_first && __if <= rdpa_if_cpu_last;
+}
+
+/** Check if interface is either LAN interface (LAN EMAC port or LAN switch port) or Wi-Fi SSID
+ * \param[in] __if Interface
+ * \return 1 LAN interface or Wi-Fi SSID, 0 otherwise
+ */
+static inline int rdpa_if_is_lan_or_wifi(rdpa_if __if)
+{
+    return rdpa_if_is_lan(__if) || rdpa_if_is_wifi(__if);
+}
+
+/** Check if interface is either LAN interface (LAN EMAC port or LAN switch port) or WLAN (PCI port)
+ * \param[in] __if Interface
+ * \return 1 LAN interface or WLAN, 0 otherwise
+ */
+static inline int rdpa_if_is_lan_or_cpu(rdpa_if __if)
+{
+    return rdpa_if_is_lan(__if) || rdpa_if_is_cpu_port(__if);
+}
+
+/** Check if interface is CPU and not WLAN (PCI port)
+ * \param[in] __if Interface
+ * \return 1 if pure CPU, 0 otherwise
+ */
+static inline int rdpa_if_is_cpu_not_wlan(rdpa_if __if)
+{
+    return rdpa_if_is_cpu_port(__if) && (!rdpa_if_is_wlan(__if));
+}
+
+
+/** All MACs */
+#define RDPA_PORT_ALL_MACS (RDPA_PORT_ALL_LAN_MACS | RDPA_PORT_ALL_WAN)
+
+/** Check if port mask contains single port
+ * \param[in] ports Port Mask
+ * \return 1 if mask contains a single port , 0 otherwise
+ */
+static inline int rdpa_port_is_single(rdpa_ports ports)
+{
+    return (ports & (ports - 1)) == 0;
+}
+
+/** Check if port mask contains wan0 port
+ * \param[in] ports Port Mask
+ * \return 1 if mask contains a wan0 port , 0 otherwise
+ */
+static inline int rdpa_ports_contains_wan0_if(rdpa_ports ports)
+{
+    return ports & rdpa_if_id(rdpa_if_wan0); /* FIXME - MULTI-WAN XPON */
+}
+
+/** System operation mode */
+typedef enum
+{
+    rdpa_method_prv,          /**< Used to configure system in Provision mode */
+    rdpa_method_fc,           /**< Used to configure system in Flow Cache mode */
+} rdpa_operation_mode;
+
+/** IPTV entries lookup method */
+typedef enum
+{
+    iptv_lookup_method_mac, /**< Perform IPTV entry lookup by MAC address (L2) */
+    iptv_lookup_method_mac_vid, /**< Perform IPTV entry lookup by MAC address and VID (L2) */
+    iptv_lookup_method_group_ip, /**< Perform IPTV entry lookup by Multicast Group IP address (IGMPv2/MLDv1) */
+    iptv_lookup_method_group_ip_src_ip, /**< Perform IPTV entry lookup by Multicast Group IP and Source IP
+                                             addresses (IGMPv3/MLDv2). Source IP address is optional. */
+    iptv_lookup_method_group_ip_src_ip_vid /**< Perform IPTV entry lookup by Multicast Group IP and Source IP
+                                                addresses and VID. Source IP address is optional. */
+} rdpa_iptv_lookup_method;
+
+/** EPON mode */
+typedef enum
+{
+    rdpa_epon_none,            /**< not EPON mode */ 
+    rdpa_epon_ctc,             /**< CTC OAM mode */
+    rdpa_epon_cuc,             /**< CUC OAM mode */
+    rdpa_epon_dpoe,            /**< DPOE OAM mode */
+    rdpa_epon_bcm,             /**< BCM OAM mode */
+    rdpa_epon_ctc_dyn,         /**< CTC OAM dynamic mode  */
+    rdpa_epon_cuc_dyn,         /**< CUC OAM dynamic mode  */
+    rdpa_epon_last,
+} rdpa_epon_mode;
+
+/** Packet offset type */
+typedef enum
+{
+    RDPA_OFFSET_L2, /**< Offset of L2 header */
+    RDPA_OFFSET_L3, /**< Offset of L3 header */
+    RDPA_OFFSET_L4, /**< Offset of L4 header */
+} rdpa_offset_t;
+
+/* BPM buffer size */
+typedef enum
+{
+    RDPA_BPM_BUFFER_2K = 2048,
+    RDPA_BPM_BUFFER_2_5K = 2560,
+    RDPA_BPM_BUFFER_4K = 4096,
+    RDPA_BPM_BUFFER_16K = 16384,
+} rdpa_bpm_buffer_size_t;
+
+/** WiFi Acceleration type */
+typedef enum
+{
+    RDPA_WL_ACCEL_NONE = 0,     /**< Acceleration disabled */
+    RDPA_WL_ACCEL_WFD,          /**< WFD Acceleration type */
+    RDPA_WL_ACCEL_DHD_OFFLOAD   /**< DHD Offload Acceleration type */
+} rdpa_wl_accel_t;
+
+/** CPU ring type */
+typedef enum {
+    rdpa_ring_data = 0,         /**< Data ring */
+    rdpa_ring_recycle = 1,      /**< Recycle ring */
+    rdpa_ring_feed = 2,         /**< Feed ring */
+    rdpa_ring_cpu_tx = 3,       /**< Cpu tx PD ring */
+} rdpa_ring_type_t;
+
+typedef enum {
+    rdpa_proto_filter_ipv4,
+    rdpa_proto_filter_ipv6,
+    rdpa_proto_filter_pppoe,
+    rdpa_proto_filter_non_ip,
+    rdpa_proto_filter_any,
+    rdpa_proto_filter_last = rdpa_proto_filter_any,
+} rdpa_proto_filter_t;
+
+/** Protocol Filters mask, defines allowed protocols */
+typedef enum {
+    rdpa_proto_filter_ipv4_mask = (1 << rdpa_proto_filter_ipv4),     /**< Allow IPv4 traffic */
+    rdpa_proto_filter_ipv6_mask = (1 << rdpa_proto_filter_ipv6),     /**< Allow IPv6 traffic */
+    rdpa_proto_filter_pppoe_mask = (1 << rdpa_proto_filter_pppoe),   /**< Allow PPPoE traffic */ 
+    rdpa_proto_filter_non_ip_mask = (1 << rdpa_proto_filter_non_ip), /**< Allow Non-IP traffic */
+    rdpa_proto_filter_any_mask = (1 << rdpa_proto_filter_any),       /**< Allow any traffic */
+} rdpa_proto_filter_fields;
+
+typedef uint32_t rdpa_proto_filters_mask_t; /**< Mask of \ref rdpa_proto_filter_fields (enabled protocols) */
+
+/** @} end of types Doxygen group */
+
+typedef struct
+{
+    int src;
+    int dest;
+} int2int_map_t;
+
+static inline int int2int_map(int2int_map_t *map, int src, int last)
+{
+    for (; map->src != last && map->src != src; map++)
+        ;
+    return map->dest;
+}
+
+static inline int int2int_map_r(int2int_map_t *map, int src, int last)
+{
+    for (; map->src != last && map->dest != src; map++)
+        ;
+    return map->src;
+}
+
+typedef enum
+{
+    RDPA_FLOW_UNKNOWN,
+    RDPA_FLOW_TUPLE_L3,
+    RDPA_FLOW_TUPLE_L2,
+    RDPA_FLOW_MC,
+} rdpa_flow_t;
+
+#endif /* _RDPA_TYPES_H_ */
+
diff --git a/arch/arm/mach-bcmbca/rdp/unimac_drv.h b/arch/arm/mach-bcmbca/rdp/unimac_drv.h
new file mode 100755
index 0000000000..6432b9166f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/unimac_drv.h
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2013 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the definition for the Unimac block 			          */
+/*                                                                            */
+/******************************************************************************/
+#ifndef __UNIMAC_DRV_H
+#define __UNIMAC_DRV_H
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+#include <common.h>
+#include <linux/compat.h>
+#include <asm/arch/unimac.h>
+#include "hwapi_mac.h"
+#if defined(CONFIG_BCM47622)
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+#define _BYTE_ORDER_LITTLE_ENDIAN_
+#endif
+#define WRITE_32(a, r)			( *(volatile uint32_t*)(a) = *(uint32_t*)&(r) )
+#define READ_32(a, r)			( *(volatile uint32_t*)&(r) = *(volatile uint32_t*) (a) )
+#define VAL32(_a)			( *(volatile uint32_t*)(_a))
+#else
+#include "access_macros.h"
+#endif
+
+#if defined(CONFIG_BCM6846) || defined(CONFIG_BCM63158) || defined(CONFIG_BCM6856) || defined(CONFIG_BCM47622) || defined(CONFIG_BCM6878)
+#define swap2bytes(x)    (x)
+#define swap4bytes(x)    (x)
+#define swap4bytes64(x)  (x)
+#endif
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+
+#define UNIMAC_CONFIGURATION_UMAC_0_UMAC_DUMMY              UNIMAC_CFG_BASE + 0x0000    /* UniMAC Dummy Register */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_HD_BKP_CNTL         UNIMAC_CFG_BASE + 0x0004    /* UniMAC Half Duplex Backpressure Control Register */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD                 UNIMAC_CFG_BASE + 0x0008    /* UniMAC Command Register */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_MAC0                UNIMAC_CFG_BASE + 0x000c    /* UniMAC MAC address first 4 bytes*/
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_MAC1                UNIMAC_CFG_BASE + 0x0010    /* UniMAC MAC address 2 last bytes*/
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_FRM_LEN             UNIMAC_CFG_BASE + 0x0014    /* UniMAC Frame Length */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_QUNAT         UNIMAC_CFG_BASE + 0x0018    /* UniMAC Pause Quanta */
+#define UNIMAC_CONFIGURATION_UMAC_0_SFD_OFFSET              UNIMAC_CFG_BASE + 0x0040    /* UniMAC EFM Preamble Length */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_MODE                UNIMAC_CFG_BASE + 0x0044    /* UniMAC Mode */
+#define UNIMAC_CONFIGURATION_UMAC_0_FRM_TAG0                UNIMAC_CFG_BASE + 0x0048    /* UniMAC Preamble Outer TAG 0 */
+#define UNIMAC_CONFIGURATION_UMAC_0_FRM_TAG1                UNIMAC_CFG_BASE + 0x004c    /* UniMAC Preamble Outer TAG 1 */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_TX_IPG_LEN          UNIMAC_CFG_BASE + 0x005c    /* UniMAC Inter Packet Gap */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_CTRL            UNIMAC_CFG_BASE + 0x0064    /* UniMAC Energy Efficient Ethernet Control */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_LPI_TIMER       UNIMAC_CFG_BASE + 0x0068    /* EEE LPI timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_WAKE_TIMER      UNIMAC_CFG_BASE + 0x006c    /* EEE wakeup timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_REF_COUNT       UNIMAC_CFG_BASE + 0x0070    /* UniMAC Energy Efficient Ethernet Ref Clock Speed */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_MII_LPI_TIMER   UNIMAC_CFG_BASE + 0x0068    /* MII EEE LPI timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_GMII_LPI_TIMER  UNIMAC_CFG_BASE + 0x006c    /* GMII EEE LPI timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_MII_WAKE_TIMER  UNIMAC_CFG_BASE + 0x0080    /* MII EEE wakeup timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_GMII_WAKE_TIMER UNIMAC_CFG_BASE + 0x0084    /* GMII EEE wakeup timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_CNTRL         UNIMAC_CFG_BASE + 0x0330    /* UniMAC Repetitive Pause Control in TX direction */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_RX_MAX_PKT_SIZE     UNIMAC_CFG_BASE + 0x0608    /* UniMAC RX MAX packet Size Register */
+
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR64      UNIMAC_MIB_BASE + 0x0000    /* Receive 64B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR127     UNIMAC_MIB_BASE + 0x0004    /* Receive 65B to 127B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR255     UNIMAC_MIB_BASE + 0x0008    /* Receive 128B to 255B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR511     UNIMAC_MIB_BASE + 0x000c    /* Receive 256B to 511B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR1023    UNIMAC_MIB_BASE + 0x0010    /* Receive 512B to 1023B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR1518    UNIMAC_MIB_BASE + 0x0014    /* Receive 1024B to 1518B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRMGV     UNIMAC_MIB_BASE + 0x0018    /* Receive 1519B to 1522B Good VLAN Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR2047    UNIMAC_MIB_BASE + 0x001c    /* Receive 1519B to 2047B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR4095    UNIMAC_MIB_BASE + 0x0020    /* Receive 2048B to 4095B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR9216    UNIMAC_MIB_BASE + 0x0024    /* Receive 4096B to 9216B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRPKT     UNIMAC_MIB_BASE + 0x0028    /* Receive Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRBYT     UNIMAC_MIB_BASE + 0x002c    /* Receive Byte Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRMCA     UNIMAC_MIB_BASE + 0x0030    /* Receive Multicast Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRBCA     UNIMAC_MIB_BASE + 0x0034    /* Receive Broadcast Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRFCS     UNIMAC_MIB_BASE + 0x0038    /* Receive FCS Error Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRXCF     UNIMAC_MIB_BASE + 0x003c    /* Receive Control Frame Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRXPF     UNIMAC_MIB_BASE + 0x0040    /* Receive Pause Frame Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRXUO     UNIMAC_MIB_BASE + 0x0044    /* Receive Unknown OP Code Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRALN     UNIMAC_MIB_BASE + 0x0048    /* Receive Alignmenet Error Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRFLR     UNIMAC_MIB_BASE + 0x004c    /* Receive Frame Length Out Of Range Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRCDE     UNIMAC_MIB_BASE + 0x0050    /* Receive Code Error Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRFCR     UNIMAC_MIB_BASE + 0x0054    /* Receive Carrier Sense Error Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GROVR     UNIMAC_MIB_BASE + 0x0058    /* Receive Oversize Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRJBR     UNIMAC_MIB_BASE + 0x005c    /* Receive Jabber Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRMTUE    UNIMAC_MIB_BASE + 0x0060    /* Receive MTU Error Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRPOK     UNIMAC_MIB_BASE + 0x0064    /* Receive Good Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRUC      UNIMAC_MIB_BASE + 0x0068    /* Receive Unicast Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRPPP     UNIMAC_MIB_BASE + 0x006c    /* Receive PPP Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRCRC     UNIMAC_MIB_BASE + 0x0070    /* Receive CRC Match Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR64      UNIMAC_MIB_BASE + 0x0080    /* Transmit 64B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR127     UNIMAC_MIB_BASE + 0x0084    /* Transmit 65B to 127B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR255     UNIMAC_MIB_BASE + 0x0088    /* Transmit 128B to 255B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR511     UNIMAC_MIB_BASE + 0x008c    /* Transmit 256B to 511B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR1023    UNIMAC_MIB_BASE + 0x0090    /* Transmit 512B to 1023B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR1518    UNIMAC_MIB_BASE + 0x0094    /* Transmit 1024B to 1518B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TRMGV     UNIMAC_MIB_BASE + 0x0098    /* Transmit 1519B to 1522B Good VLAN Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR2047    UNIMAC_MIB_BASE + 0x009c    /* Transmit 1519B to 2047B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR4095    UNIMAC_MIB_BASE + 0x00a0    /* Transmit 2048B to 4095B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR9216    UNIMAC_MIB_BASE + 0x00a4    /* Transmit 4096B to 9216B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTPKT     UNIMAC_MIB_BASE + 0x00a8    /* Transmit Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTMCA     UNIMAC_MIB_BASE + 0x00ac    /* Transmit Multicast Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTBCA     UNIMAC_MIB_BASE + 0x00b0    /* Transmit Broadcast Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTXPF     UNIMAC_MIB_BASE + 0x00b4    /* Transmit Pause Frame Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTXCF     UNIMAC_MIB_BASE + 0x00b8    /* Transmit Control Frame Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTFCS     UNIMAC_MIB_BASE + 0x00bc    /* Transmit FCS Error Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTOVR     UNIMAC_MIB_BASE + 0x00c0    /* Transmit Oversize Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTDRF     UNIMAC_MIB_BASE + 0x00c4    /* Transmit Deferral Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTEDF     UNIMAC_MIB_BASE + 0x00c8    /* Transmit Excessive Deferral Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTSCL     UNIMAC_MIB_BASE + 0x00cc    /* Transmit Single Collision Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTMCL     UNIMAC_MIB_BASE + 0x00d0    /* Transmit Multiple Collision Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTLCL     UNIMAC_MIB_BASE + 0x00d4    /* Transmit Late Collision Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTXCL     UNIMAC_MIB_BASE + 0x00d8    /* Transmit Excessive Collision Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTFRG     UNIMAC_MIB_BASE + 0x00dc    /* Transmit Fragments Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTNCL     UNIMAC_MIB_BASE + 0x00e0    /* Transmit Total Collision Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTJBR     UNIMAC_MIB_BASE + 0x00e4    /* Transmit Jabber Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTBYT     UNIMAC_MIB_BASE + 0x00e8    /* Transmit Byte Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTPOK     UNIMAC_MIB_BASE + 0x00ec    /* Transmit Good Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTUC      UNIMAC_MIB_BASE + 0x00f0    /* Transmit Unicast Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_RRPKT     UNIMAC_MIB_BASE + 0x0100    /* Receive RUNT Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_RRUND     UNIMAC_MIB_BASE + 0x0104    /* Receive RUNT Packet And Contain A Valid FCS */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_RRFRG     UNIMAC_MIB_BASE + 0x0108    /* Receive RUNT Packet And Contain Invalid FCS or Alignment Error */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_RRBYT     UNIMAC_MIB_BASE + 0x010c    /* Receive RUNT Packet Byte Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_MIB_CNTRL UNIMAC_MIB_BASE + 0x0180    /* MIB Control Register */
+
+#if defined(CONFIG_BCM47622)
+#define UNIMAC_TOPCTRL_MIB_MAX_PKT_SIZE                     SYSPORT_0_BASE  + 0x0028    /* Value by MIB to differentiate regular and oversized packets */
+#else
+#define UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG                   UNIMAC_TOP_BASE + 0x0000    /* UNIMAC_CFG Register */
+#define UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1              UNIMAC_TOP_BASE + 0x0004    /* UNIMAC_EXT_CFG1 Register */
+#define UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2              UNIMAC_TOP_BASE + 0x0008    /* UNIMAC_EXT_CFG2 Register */
+#endif
+
+#if defined(CONFIG_BCM47622)
+#define MAX_NUM_OF_EMACS                                                        2
+#define UNIMAC_CONF_INSTANCE_OFFSET(e)                          ((e)?(SYSPORT_1_UMAC_BASE-SYSPORT_UMAC_BASE):0)
+#define UNIMAC_MIB_INSTANCE_OFFSET(e)                           ((e)?(SYSPORT_1_MIB_BASE-SYSPORT_MIB_BASE):0)
+#define UNIMAC_TOPCTRL_INSTANCE_OFFSET(e)                       ((e)?(SYSPORT_1_BASE-SYSPORT_0_BASE):0)
+#else
+#define MAX_NUM_OF_EMACS                                                        rdpa_emac__num_of
+#define UNIMAC_CONF_INSTANCE_OFFSET(e)                          (0x1000/*UNIMAC_CONF_EMAC_OFFSET*/*(e))
+#define UNIMAC_MISC_INSTANCE_OFFSET(e)                          ( 0x400/*UNIMAC_MISC_EMAC_OFFSET*/*(e))
+#define UNIMAC_MIB_INSTANCE_OFFSET(e)                           ( 0x400/*UNIMAC_MIB_EMAC_OFFSET*/ *(e))
+#endif
+
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_HD_BKP_CNTL_ipg_config_rx_MASK          0x0000007c
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_HD_BKP_CNTL_ipg_config_rx_SHIFT         2
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_HD_BKP_CNTL_hd_fc_ena_MASK              0x00000001
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_HD_BKP_CNTL_hd_fc_ena_SHIFT             0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_txrx_en_config_MASK                 0x20000000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_txrx_en_config_SHIFT                29
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_tx_pause_ignore_MASK                0x10000000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_tx_pause_ignore_SHIFT               28
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rmt_loop_ena_MASK                   0x02000000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rmt_loop_ena_SHIFT                  25
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_cntl_frm_ena_MASK                   0x00800000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_cntl_frm_ena_SHIFT                  23
+#if defined(CONFIG_BCM47622)
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_override_rx_MASK                 0x00040000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_override_rx_SHIFT                18
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_override_tx_MASK                 0x00020000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_override_tx_SHIFT                17
+#endif
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_lcl_loop_ena_MASK                   0x00008000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_lcl_loop_ena_SHIFT                  15
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_reset_MASK                       0x00002000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_reset_SHIFT                      13
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_hd_ena_MASK                         0x00000400
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_hd_ena_SHIFT                        10
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rx_pause_ignore_MASK                0x00000100
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rx_pause_ignore_SHIFT               8
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_pause_fwd_MASK                      0x00000080
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_pause_fwd_SHIFT                     7
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_crc_fwd_MASK                        0x00000040
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_crc_fwd_SHIFT                       6
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_pad_en_MASK                         0x00000020
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_pad_en_SHIFT                        5
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_eth_speed_MASK                      0x0000000c
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_eth_speed_SHIFT                     2
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rx_ena_MASK                         0x00000002
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rx_ena_SHIFT                        1
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_tx_ena_MASK                         0x00000001
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_tx_ena_SHIFT                        0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_FRM_LEN_frame_length_MASK               0x00003fff
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_FRM_LEN_frame_length_SHIFT              0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_TX_IPG_LEN_tx_ipg_len_MASK              0x0000007f
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_TX_IPG_LEN_tx_ipg_len_SHIFT             0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_TX_IPG_LEN_tx_min_pkt_size_MASK         0x00007F00
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_TX_IPG_LEN_tx_min_pkt_size_SHIFT        8
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_RX_MAX_PKT_SIZE_max_pkt_size_MASK       0x00003fff
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_RX_MAX_PKT_SIZE_max_pkt_size_SHIFT      0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_CNTRL_pause_control_en_MASK       0x00020000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_CNTRL_pause_control_en_SHIFT      17
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_CNTRL_pause_timer_MASK            0x0001ffff
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_CNTRL_pause_timer_SHIFT           0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_QUNAT_pause_quant_MASK            0x0000ffff
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_QUNAT_pause_quant_SHIFT           0
+
+#define UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT          1 << 16
+
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_MIB_CNTRL_rx_cnt_st_MASK      0x00000001
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_MIB_CNTRL_rx_cnt_st_SHIFT     0
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_MIB_CNTRL_tx_cnt_rst_MASK     0x00000004
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_MIB_CNTRL_tx_cnt_rst_SHIFT    2
+
+/* Macros for reading and writing UNIMAC_CONFIGURATION registers*/
+
+#define UNIMAC_READ32_REG(e,r,o) READ_32( UNIMAC_CONFIGURATION_UMAC_0_RDP_##r + UNIMAC_CONF_INSTANCE_OFFSET(e) , (o) )
+
+#define UNIMAC_WRITE32_REG(e,r,i) WRITE_32( UNIMAC_CONFIGURATION_UMAC_0_RDP_##r  + UNIMAC_CONF_INSTANCE_OFFSET(e) , (i) )
+
+#define UNIMAC_READ_FIELD(e,r,f,o) \
+	 ( *(volatile uint32_t*)&(o) = (swap4bytes(VAL32(UNIMAC_CONFIGURATION_UMAC_0_RDP_##r + UNIMAC_CONF_INSTANCE_OFFSET(e) ))   & \
+		 UNIMAC_CONFIGURATION_UMAC_0_RDP_##r##_##f##_MASK ) >> UNIMAC_CONFIGURATION_UMAC_0_RDP_##r##_##f##_SHIFT  )
+
+#define UNIMAC_WRITE_FIELD(e,r,f,i) \
+	    ( ( VAL32(UNIMAC_CONFIGURATION_UMAC_0_RDP_##r + UNIMAC_CONF_INSTANCE_OFFSET(e) ) ) = \
+		( VAL32(UNIMAC_CONFIGURATION_UMAC_0_RDP_##r +  UNIMAC_CONF_INSTANCE_OFFSET(e))  & swap4bytes(~UNIMAC_CONFIGURATION_UMAC_0_RDP_##r##_##f##_MASK) ) | \
+		( swap4bytes(( (i) << UNIMAC_CONFIGURATION_UMAC_0_RDP_##r##_##f##_SHIFT ) & UNIMAC_CONFIGURATION_UMAC_0_RDP_##r##_##f##_MASK)) )
+
+/*Macros for reading and Writing UNIMAC_MIB counters*/
+
+#define UNIMAC_READ32_MIB(e,r,o) READ_32( UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r + UNIMAC_MIB_INSTANCE_OFFSET(e) , (o) )
+
+#define UNIMAC_WRITE32_MIB(e,r,i) WRITE_32( UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r  + UNIMAC_MIB_INSTANCE_OFFSET(e) , (i) )
+
+#define UNIMAC_READ_MIB_FIELD(e,r,f,o) \
+	 ( *(volatile uint32_t*)&(o) = (* ((volatile uint32_t*) DEVICE_ADDRESS(UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r + UNIMAC_MIB_INSTANCE_OFFSET(e) ) )  & \
+		 UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r##_##f##_MASK ) >> UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r##_##f##_SHIFT  )
+
+#define UNIMAC_WRITE_MIB_FIELD(e,r,f,i) \
+	    ( ( VAL32(UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r + UNIMAC_MIB_INSTANCE_OFFSET(e)) ) = \
+		( VAL32(UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r +  UNIMAC_MIB_INSTANCE_OFFSET(e))  & swap4bytes(~UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r##_##f##_MASK) ) | \
+		( swap4bytes(( (i) << UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r##_##f##_SHIFT ) & UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r##_##f##_MASK)) )
+
+
+typedef enum
+{
+	UNIMAC_SPEED_10,
+	UNIMAC_SPEED_100,
+	UNIMAC_SPEED_1000,
+	UNIMAC_SPEED_2500
+}UNIMAC_SPEED;
+
+typedef enum
+{
+	UNIMAC_DUPLEX_HALF,
+	UNIMAC_DUPLEX_FULL
+}UNIMAC_DUPLEX;
+
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct 
+{
+	/*Reserved bit must be written with 0.  A read returns an unknown value.*/
+	uint32_t	reserved3:1;
+	/*Disable RX side RUNT filtering. 0: Enable  RUNT filtering.Reset value is 0x0. */
+	uint32_t	runt_filter_dis:1;
+	/*	This mode only works in auto-config mode: 
+		0: After auto-config, TX_ENA and RX_ENA bits are set to 1. 1: After auto-config, TX_ENA and RX_ENA bits are set to 0,    
+		meaning SW will have to come in and enable TX and RX.Reset value is 0x0. */
+	uint32_t	txrx_en_config:1;
+	/*Ignore TX PAUSE frame transmit request.Reset value is 0x0. */
+	uint32_t	tx_pause_ignore:1;
+	/*Enable extract/insert of EFM headers.Reset value is 0x0. */
+	uint32_t	prbl_ena:1;
+	/*This bit currently not used.Reset value is 0x0.*/
+	uint32_t	rx_err_disc:1;  
+	/*Enable remote loopback at the fifo system side. 0: Normal operation.Reset value is 0x0. */
+	uint32_t	rmt_loop_ena:1;
+	/*Payload length check. 0: Check payload length with Length/Type field. 1: Check disabled.Reset value is 0x1. */
+	uint32_t	no_lgth_check:1;
+	/*	MAC control frame enable. 1: MAC control frames with opcode other than 0x0001 are accepted and forwarded to the client interface.
+		0: MAC control frames with opcode other than 0x0000 and 0x0001 are silently discarded.
+		Reset value is 0x0.
+	*/
+	uint32_t	cntl_frm_ena:1; 
+	/*Enable/Disable auto-configuration. 1: Enable  0: Disable Reset value is 0x0. */
+	uint32_t	ena_ext_config:1;
+	/*Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved2:6;
+	/*Enable GMII/MII loopback 1: Loopback enabled. 0: Normal operation.Reset value is 0x0. */
+	uint32_t 	lcl_loop_ena:1;
+	/*Reserved bit must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved1:1;
+	/*RX and RX engines are put in reset. 0: come out of SW reset.Reset value is 0x0. */
+	uint32_t	sw_reset:1; 
+	/* Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved0:2;
+	/* Ignored when RTH_SPEED[1]==1, gigabit mode. 1: half duplex 0: full duplex Reset value is 0x0.*/
+	uint32_t	hd_ena:1;
+	/*	The MAC overwrites the source MAC address with a programmed MAC address in register MAC_0 and MAC_1." 
+		0: Not modify the source address received from the transmit application client.
+		Reset value is 0x0.
+	*/
+	uint32_t	tx_addr_ins:1;
+	/*	Receive PAUSE frames are ignored by the MAC. 
+		0: The tramsmit process is stiooed for the amount of time specified in the pause wuanta received within the PAUSE frame.
+		Reset value is 0x0. 
+	*/
+	uint32_t	rx_pause_ignore:1;
+	/* 	PAUSE frames are forwarded to the user application. 
+		0: The PAUSE frames are terminated and discarded in the MAC.Reset value is 0x1. 
+	*/
+	uint32_t	pause_fwd:1;
+	/*	The CRC field of received frames is transmitted to the user application. 
+		0: The CRC field is stripped from the frame.Reset value is 0x1. 
+	*/
+	uint32_t	crc_fwd:1;
+	/*  Padding is removed along with crc field before the frame is sent to the user application. 
+		0: No padding is removed by the MAC.
+		Reset value is 0x0.
+	*/
+	uint32_t	pad_en:1; 
+	/* All frames are received without Unicast address filtering. 
+	   0: Reset value is 0x1. */
+	uint32_t 	promis_en:1;
+	/*00: 10Mbps, 01: 100Mbps, 10: 1000Mbps, 11: 2500Mbps Reset value is 0x2. */
+	uint32_t	eth_speed:2;
+	/* 	The MAC receive function is enabled. 0: The MAC receive function is disabled. 
+		The enable works on packet boundary meaning that only on the assertion on the bit during every 0->1 transition of rx_dv.
+		Reset value is 0x0. 
+	*/	
+	uint32_t	rx_ena:1;
+	/*	The MAC transmit function is enabled. 0: The MAC transmit function is disabled.
+		The enable works on packet boundary meaning that only on the assertion of the bit during every SOP.
+		Reset value is 0x0. 
+	*/
+	uint32_t    tx_ena:1;
+
+}S_UNIMAC_CMD_REG;
+
+typedef struct
+{
+
+	/* Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved:26;
+	/*Link status indication.Reset value is 0x0. */
+	uint32_t	mac_link_stat:1; 
+	/* 1: MAC Tx pause enabled. 0: MAC Tx pause disabled.Reset value is 0x1. */
+	uint32_t	mac_tx_pause:1;
+	/*1: MAC Rx pause enabled. 0: MAC Rx pause disabled.Reset value is 0x1. */
+	uint32_t	mac_rx_pause:1; 
+	/*1: Half duplex. 0: Full duplex. Reset value is 0x0. */
+	uint32_t	mac_duplex:1;
+	/* 00: 10Mbps, 01: 100Mbps, 10: 1Gbps, 11: 2.5Gbps Reset value is 0x2. 	*/
+	uint32_t	mac_speed:2;
+
+}S_UNIMAC_STAT_REG;
+
+typedef struct
+{
+	uint32_t	reserved:15;
+	uint32_t	pp_gen:1; 
+	uint32_t	pp_pse_en:8; 
+	uint32_t	launch_en:1; 
+	uint32_t	ext_tx_flow:1; 
+	uint32_t	mac_crc_owrt:1; 
+	uint32_t	mac_crc_fwd:1; 
+	uint32_t	txcrcerr:1;
+	uint32_t	ss_mode_mii:1; 
+	uint32_t	gport_mode:1;
+	uint32_t	gmii_direct:1;
+
+}S_UNIMAC_CFG_REG;
+
+typedef struct
+{
+    uint32_t    reserved:7;
+    uint32_t    rxfifo_congestion_threshold:9;
+    uint32_t    reserved1:2;
+    uint32_t    max_pkt_size:14;
+
+}S_UNIMAC_TOP_CFG1_REG;
+
+typedef struct
+{
+	uint32_t	reserved:24;
+	uint32_t	lp_idle_prediction_mode:1; 
+	uint32_t	dis_eee_10m:1; 
+	uint32_t	eee_txclk_dis:1; 
+	uint32_t	rx_fifo_check:1; 
+	uint32_t	eee_en:1;
+	uint32_t	en_lpi_tx_pause:1; 
+	uint32_t	en_lpi_tx_pfc:1;
+	uint32_t	en_lpi_rx_pause:1;
+}S_UNIMAC_EEE_CTRL_REG;
+
+#else /* little endian */
+
+typedef struct 
+{
+	/*	The MAC transmit function is enabled. 0: The MAC transmit function is disabled.
+		The enable works on packet boundary meaning that only on the assertion of the bit during every SOP.
+		Reset value is 0x0. 
+	*/
+	uint32_t    tx_ena:1;
+	/* 	The MAC receive function is enabled. 0: The MAC receive function is disabled. 
+		The enable works on packet boundary meaning that only on the assertion on the bit during every 0->1 transition of rx_dv.
+		Reset value is 0x0. 
+	*/	
+	uint32_t	rx_ena:1;
+	/*00: 10Mbps, 01: 100Mbps, 10: 1000Mbps, 11: 2500Mbps Reset value is 0x2. */
+	uint32_t	eth_speed:2;
+	/* All frames are received without Unicast address filtering. 
+	   0: Reset value is 0x1. */
+	uint32_t 	promis_en:1;
+	/*  Padding is removed along with crc field before the frame is sent to the user application. 
+		0: No padding is removed by the MAC.
+		Reset value is 0x0.
+	*/
+	uint32_t	pad_en:1; 
+	/*	The CRC field of received frames is transmitted to the user application. 
+		0: The CRC field is stripped from the frame.Reset value is 0x1. 
+	*/
+	uint32_t	crc_fwd:1;
+	/* 	PAUSE frames are forwarded to the user application. 
+		0: The PAUSE frames are terminated and discarded in the MAC.Reset value is 0x1. 
+	*/
+	uint32_t	pause_fwd:1;
+	/*	Receive PAUSE frames are ignored by the MAC. 
+		0: The tramsmit process is stiooed for the amount of time specified in the pause wuanta received within the PAUSE frame.
+		Reset value is 0x0. 
+	*/
+	uint32_t	rx_pause_ignore:1;
+	/*	The MAC overwrites the source MAC address with a programmed MAC address in register MAC_0 and MAC_1." 
+		0: Not modify the source address received from the transmit application client.
+		Reset value is 0x0.
+	*/
+	uint32_t	tx_addr_ins:1;
+	/* Ignored when RTH_SPEED[1]==1, gigabit mode. 1: half duplex 0: full duplex Reset value is 0x0.*/
+	uint32_t	hd_ena:1;
+	/* Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved0:2;
+	/*RX and RX engines are put in reset. 0: come out of SW reset.Reset value is 0x0. */
+	uint32_t	sw_reset:1; 
+	/*Reserved bit must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved1:1;
+	/*Enable GMII/MII loopback 1: Loopback enabled. 0: Normal operation.Reset value is 0x0. */
+	uint32_t 	lcl_loop_ena:1;
+#if defined(CONFIG_BCM47622)
+	uint32_t	mac_loop_con:1;
+	uint32_t	sw_override_tx:1;
+	uint32_t	sw_override_rx:1;
+	uint32_t	reserved2:2;
+	uint32_t	en_internal_tx_crs:1;
+#else
+	/*Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved2:6;
+#endif
+	/*Enable/Disable auto-configuration. 1: Enable  0: Disable Reset value is 0x0. */
+	uint32_t	ena_ext_config:1;
+	/*	MAC control frame enable. 1: MAC control frames with opcode other than 0x0001 are accepted and forwarded to the client interface.
+		0: MAC control frames with opcode other than 0x0000 and 0x0001 are silently discarded.
+		Reset value is 0x0.
+	*/
+	uint32_t	cntl_frm_ena:1; 
+	/*Payload length check. 0: Check payload length with Length/Type field. 1: Check disabled.Reset value is 0x1. */
+	uint32_t	no_lgth_check:1;
+	/*Enable remote loopback at the fifo system side. 0: Normal operation.Reset value is 0x0. */
+	uint32_t	rmt_loop_ena:1;
+	/*This bit currently not used.Reset value is 0x0.*/
+	uint32_t	rx_err_disc:1;  
+	/*Enable extract/insert of EFM headers.Reset value is 0x0. */
+	uint32_t	prbl_ena:1;
+	/*Ignore TX PAUSE frame transmit request.Reset value is 0x0. */
+	uint32_t	tx_pause_ignore:1;
+	/*	This mode only works in auto-config mode: 
+		0: After auto-config, TX_ENA and RX_ENA bits are set to 1. 1: After auto-config, TX_ENA and RX_ENA bits are set to 0,    
+		meaning SW will have to come in and enable TX and RX.Reset value is 0x0. */
+	uint32_t	txrx_en_config:1;
+	/*Disable RX side RUNT filtering. 0: Enable  RUNT filtering.Reset value is 0x0. */
+	uint32_t	runt_filter_dis:1;
+	/*Reserved bit must be written with 0.  A read returns an unknown value.*/
+	uint32_t	reserved3:1;
+
+}S_UNIMAC_CMD_REG;
+
+typedef struct
+{
+
+	/* 00: 10Mbps, 01: 100Mbps, 10: 1Gbps, 11: 2.5Gbps Reset value is 0x2. 	*/
+	uint32_t	mac_speed:2;
+	/*1: Half duplex. 0: Full duplex. Reset value is 0x0. */
+	uint32_t	mac_duplex:1;
+	/*1: MAC Rx pause enabled. 0: MAC Rx pause disabled.Reset value is 0x1. */
+	uint32_t	mac_rx_pause:1; 
+	/* 1: MAC Tx pause enabled. 0: MAC Tx pause disabled.Reset value is 0x1. */
+	uint32_t	mac_tx_pause:1;
+	/*Link status indication.Reset value is 0x0. */
+	uint32_t	mac_link_stat:1; 
+	/* Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved:26;
+
+}S_UNIMAC_STAT_REG;
+
+#if defined(CONFIG_BCM47622)
+typedef struct
+{
+    uint32_t    max_pkt_size:14;
+    uint32_t    reserved1:18;
+
+}S_UNIMAC_TOPCTRL_MAX_PKT_SZ_REG;
+
+#else   //!47622
+typedef struct
+{
+	uint32_t	gmii_direct:1;
+	uint32_t	gport_mode:1;
+	uint32_t	ss_mode_mii:1; 
+	uint32_t	txcrcerr:1;
+	uint32_t	mac_crc_fwd:1; 
+	uint32_t	mac_crc_owrt:1; 
+	uint32_t	ext_tx_flow:1; 
+	uint32_t	launch_en:1; 
+	uint32_t	pp_pse_en:8; 
+	uint32_t	pp_gen:1; 
+	uint32_t	reserved:15;
+
+}S_UNIMAC_CFG_REG;
+
+typedef struct
+{
+    uint32_t    max_pkt_size:14;
+    uint32_t    reserved1:2;
+    uint32_t    rxfifo_congestion_threshold:9;
+    uint32_t    reserved:7;
+
+}S_UNIMAC_TOP_CFG1_REG;
+
+typedef struct
+{
+    /* RX FIFO Threshold - This is the fifo located between the UNIMAC IP and BBH.
+       Once the threshold is reached pause is sent. This configuration is in
+       16-byte resolution the number of bytes in a FIFO line */
+    uint32_t    rxfifo_pause_threshod:9;
+    uint32_t    reserved1:7;
+    /* Backpressure enable for internal unimac */
+    uint32_t    backpressure_enable_int:1;
+    /* Backpressure enable for external switch */
+    uint32_t    backpressure_enable_ext:1;
+    /* Enable the mechanism for always receiving data from UNIMAC IP and
+       dropping overrun words in the unimac glue FIFO. */
+    uint32_t    fifo_overrun_ctl_en:1;
+    /* When setting this bit RX recovered clock will also input the
+       clk25 pll ref clk in the UNIMAC.*/
+    uint32_t    remote_loopback_en:1;
+    uint32_t    reserved2:12;
+
+}S_UNIMAC_TOP_CFG2_REG;
+#endif //!47622
+
+typedef struct
+{
+	uint32_t	en_lpi_rx_pause:1;
+	uint32_t	en_lpi_tx_pfc:1;
+	uint32_t	en_lpi_tx_pause:1; 
+	uint32_t	eee_en:1;
+	uint32_t	rx_fifo_check:1; 
+	uint32_t	eee_txclk_dis:1; 
+	uint32_t	dis_eee_10m:1; 
+	uint32_t	lp_idle_prediction_mode:1; 
+	uint32_t	reserved:24;
+}S_UNIMAC_EEE_CTRL_REG;
+
+#endif
+
+#endif
+
diff --git a/arch/arm/mach-bcmbca/rdp/unimac_drv_impl1.c b/arch/arm/mach-bcmbca/rdp/unimac_drv_impl1.c
new file mode 100755
index 0000000000..c27916d196
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rdp/unimac_drv_impl1.c
@@ -0,0 +1,1680 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2013 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the implementation of the HwApiMac for unimac           */
+/*                                                                            */
+/******************************************************************************/
+
+
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+#include "unimac_drv.h"
+#if defined(__UBOOT__) && !defined(CONFIG_BCM6856) && !defined(CONFIG_BCM6878)
+static void get_rdp_freq(uint32_t *rdp_freq) { }
+#else
+#include "clk_rst.h"
+#endif
+
+#if defined(CONFIG_BCM63138) || defined(CONFIG_BCM63148)
+#include "rdp_drv_bbh.h"
+#endif
+
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+#define UNIMAC_SWRESET_ON  			1
+#define UNIMAC_SWRESET_OFF 			0
+#define UNIMAC_DEFAULT_IPG 			12
+#define UNIMAC_DEFAULT_PAUSE_QUANTA 0xffff
+#define UNIMAC_DEFAULT_PAUSE_TIMER 	0x1ffff
+#define UNIMAC_MAX_FRAME_LENGHT		0xffff
+
+#ifdef  __UBOOT__    
+#define  mac_unlikely(a) a      
+#else
+#define  mac_unlikely(a) unlikely(a)
+#endif
+
+#define UNIMAC_NUMBER_OF_SPEEDS 	( UNIMAC_SPEED_2500 + 1 )
+#define UNIMAC_NUMBER_OF_DUPLEXES	( UNIMAC_DUPLEX_FULL + 1 )
+
+static uint32_t ipgSpeedTable[UNIMAC_NUMBER_OF_SPEEDS][UNIMAC_NUMBER_OF_DUPLEXES] =
+{
+    {0x000a,0x000a},
+    {0x000a,0x000a},
+    {0x0005,0x0005},
+    {0x0005,0x0005}
+};
+
+static uint32_t enabled_emac;
+
+#if defined(CONFIG_BCM4908)
+#include "bcm_map_part.h"
+uint8_t *soc_base_address;      // used by DEVICE_ADDRESS()
+#endif
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_configuration                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get configuration                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   get the configuratin of a mac port	,note that current status of emac	  */
+/*   might be different than configuration when working in autoneg			  */
+/*	to get the current status use mac_hwapi_get_mac_status API				  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    emac_cfg -  structure holds the current configuration of the mac  port  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_configuration(rdpa_emac emacNum,rdpa_emac_cfg_t *emac_cfg)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    emac_cfg->allow_too_long		=	0;//no such
+    emac_cfg->back2back_gap			=	0;//no such
+    emac_cfg->check_length			=	!mCfgReg.no_lgth_check;
+    emac_cfg->full_duplex			=	!mCfgReg.hd_ena;
+    emac_cfg->generate_crc			=	0;
+    emac_cfg->loopback				=	mCfgReg.rmt_loop_ena;
+    emac_cfg->non_back2back_gap		= 	0;//no such
+    emac_cfg->pad_short				= 	0;//no such
+    emac_cfg->rate					=	mCfgReg.eth_speed;
+    emac_cfg->rx_flow_control		=	!mCfgReg.rx_pause_ignore;
+    emac_cfg->tx_flow_control		=	!mCfgReg.tx_pause_ignore;
+
+    UNIMAC_READ_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,emac_cfg->min_interframe_gap);
+    UNIMAC_READ_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,emac_cfg->preamble_length);
+}
+EXPORT_SYMBOL(mac_hwapi_get_configuration);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_configuration                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set configuration                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   set the configuratin of a mac port                                       */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   emac_cfg -  structure holds the current configuration of the mac  port   */
+/*                                                                            */
+/* Output:                                                                    */
+/*      																	  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_configuration(rdpa_emac emacNum,rdpa_emac_cfg_t *emac_cfg)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*first put the mac in reset to enable config change*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,1);
+
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+
+    /*now mac configuration can be changed */
+    if(!mCfgReg.ena_ext_config) /* Change only if auto_config is not set */
+    {
+        mCfgReg.eth_speed           = emac_cfg->rate;
+        mCfgReg.hd_ena	            = !emac_cfg->full_duplex;
+        mCfgReg.rx_pause_ignore     = !emac_cfg->rx_flow_control;
+        mCfgReg.tx_pause_ignore     = !emac_cfg->tx_flow_control;
+        /*set the interframe gap*/
+        UNIMAC_WRITE_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,ipgSpeedTable[emac_cfg->rate][(unsigned)emac_cfg->full_duplex]);
+    }
+    else
+    {
+        /*set the interframe gap*/
+        UNIMAC_WRITE_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,emac_cfg->min_interframe_gap);
+    }
+
+    mCfgReg.no_lgth_check	      =	!emac_cfg->check_length;
+    mCfgReg.pad_en                = emac_cfg->pad_short;
+    mCfgReg.rmt_loop_ena	      =	emac_cfg->loopback;
+
+
+    UNIMAC_WRITE32_REG(emacNum,CMD,mCfgReg);
+
+
+    /* set the preamble length */
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,emac_cfg->preamble_length);
+
+    /* when link up at 10M, hold unimac reset longer per ASIC team */
+    if (emac_cfg->rate == rdpa_emac_rate_10m)
+        udelay(1000);
+
+    /*release the sw_reset bit*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,0);
+}
+EXPORT_SYMBOL(mac_hwapi_set_configuration);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_duplex		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port duplex                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the dulplex of a port												  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    full_duples  :  1 = full dulplex,0 = half_duplex						  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_duplex(rdpa_emac emacNum,int32_t *full_duplex)
+{
+    /*read field and reverse polarity*/
+    int32_t fieldData;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,hd_ena,fieldData);
+    *full_duplex = !fieldData;
+}
+EXPORT_SYMBOL(mac_hwapi_get_duplex);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_duplex		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port duplex                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the dulplex of a port												  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    full_duples  :  1 = full dulplex,0 = half_duplex						  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_duplex(rdpa_emac emacNum,int32_t full_duplex)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    if (!mCfgReg.ena_ext_config) /* Change only if auto_config is not set */
+    {
+        /*write the dulplex field in reverse polarity,must be set in sw_reset state*/
+        S_HWAPI_MAC_STATUS  macMode;
+
+        UNIMAC_READ32_REG(emacNum,MODE,macMode);
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,hd_ena,full_duplex ?  0 : 1);
+
+        /*when setting the duplex we have to set new IPG value*/
+        //UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN ,tx_ipg_len,ipgSpeedTable[macMode.mac_speed][macMode.mac_duplex]);
+
+        /*take the mac out of sw_reset*/
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+    }
+}
+EXPORT_SYMBOL(mac_hwapi_set_duplex);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_speed		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port speed rate                                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the speed of a port													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                              							                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*      rate -   enum of the speed                                            */
+/******************************************************************************/
+void mac_hwapi_get_speed(rdpa_emac emacNum,rdpa_emac_rate *rate)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*read the speed field*/
+    UNIMAC_READ_FIELD(emacNum,CMD,eth_speed,*rate);
+}
+EXPORT_SYMBOL(mac_hwapi_get_speed);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_speed		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port speed rate                                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the speed of a port													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*      rate -   enum of the speed   						                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                   							              */
+/******************************************************************************/
+
+void mac_hwapi_set_speed(rdpa_emac emacNum,rdpa_emac_rate rate)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    if (!mCfgReg.ena_ext_config) /* Change only if auto_config is not set */
+    {
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,eth_speed,rate);
+
+
+        UNIMAC_WRITE_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,ipgSpeedTable[rate][0]);
+
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+    }
+}
+EXPORT_SYMBOL(mac_hwapi_set_speed);
+
+void mac_hwapi_set_external_conf(rdpa_emac emacNum, int enable)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    mCfgReg.ena_ext_config = enable;
+    UNIMAC_WRITE32_REG(emacNum,CMD,mCfgReg);
+}
+EXPORT_SYMBOL(mac_hwapi_set_external_conf);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rxtx_enable                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx and rx enable                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get tx and rx enable													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                             								  */
+/*                                                                            */
+/* Output:                                                                    */
+/*       rxtxEnable  - boolean enable   	                                  */
+/******************************************************************************/
+void mac_hwapi_get_rxtx_enable(rdpa_emac emacNum,int32_t *rxEnable,int32_t *txEnable)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,tx_ena,*txEnable);
+    UNIMAC_READ_FIELD(emacNum,CMD,rx_ena,*rxEnable);
+}
+EXPORT_SYMBOL(mac_hwapi_get_rxtx_enable);
+
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_rxtx_enable                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx and rx enable                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set tx and rx enable													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    rxtxEnable  - boolean enable                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_rxtx_enable(rdpa_emac emacNum,int32_t rxEnable,int32_t txEnable)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,tx_ena,txEnable);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,rx_ena,rxEnable);
+}
+EXPORT_SYMBOL(mac_hwapi_set_rxtx_enable);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_sw_reset		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port software reset                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the sw reset bit of emac port										  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    swReset  :  1 = reset,0 = not reset									  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_sw_reset(rdpa_emac emacNum,int32_t *swReset)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,sw_reset,*swReset);
+}
+EXPORT_SYMBOL(mac_hwapi_get_sw_reset);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_sw_reset		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port software reset                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the sw reset bit of emac port										  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   swReset  :  1 = reset,0 = not reset	                                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*    								  										  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_sw_reset(rdpa_emac emacNum,int32_t swReset)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,swReset);
+}
+EXPORT_SYMBOL(mac_hwapi_set_sw_reset);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_min_pkt_size                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get tx minimum packet size                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*  Get the unimac configuration for minimum tx packet size                   */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    min_pkt_size  :  14...125                                               */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_min_pkt_size(rdpa_emac emacNum,int32_t *min_pkt_size)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,TX_IPG_LEN,tx_min_pkt_size,*min_pkt_size);
+}
+EXPORT_SYMBOL(mac_hwapi_get_tx_min_pkt_size);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_min_pkt_size                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx minimum packet size                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*  Set the unimac configuration for minimum tx packet size                   */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*   min_pkt_size  :  14...125                                                */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_min_pkt_size(rdpa_emac emacNum,int32_t min_pkt_size)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+#if defined(CONFIG_BCM4908) || defined(CONFIG_BCM63158) || defined(CONFIG_BCM47622)
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_min_pkt_size,min_pkt_size);
+#endif
+}
+EXPORT_SYMBOL(mac_hwapi_set_tx_min_pkt_size);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_max_frame_len                                           */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port TX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the port maximum transmit unit size in bytes						  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                              										      */
+/*                                                                            */
+/* Output:                                                                    */
+/*    maxTxFrameLen - size of frame in bytes 								  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM47622)
+void mac_hwapi_get_tx_max_frame_len(rdpa_emac emacNum,uint32_t *maxTxFrameLen )
+{
+    S_UNIMAC_TOPCTRL_MAX_PKT_SZ_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOPCTRL_MIB_MAX_PKT_SIZE + UNIMAC_TOPCTRL_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(address,cfgreg);
+
+    *maxTxFrameLen = cfgreg.max_pkt_size;
+}
+#else //!47622
+void mac_hwapi_get_tx_max_frame_len(rdpa_emac emacNum,uint32_t *maxTxFrameLen )
+{
+    S_UNIMAC_TOP_CFG1_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(address,cfgreg);
+
+    *maxTxFrameLen = cfgreg.max_pkt_size;
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_get_tx_max_frame_len);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port TX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the port maximum transmit unit size in bytes						  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    maxTxFrameLen - size of frame in bytes                         	      */
+/*                                                                            */
+/* Output:                                                                    */
+/*   																		  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM47622)
+void mac_hwapi_set_tx_max_frame_len(rdpa_emac emacNum,uint32_t maxTxFrameLen )
+{
+
+    S_UNIMAC_TOPCTRL_MAX_PKT_SZ_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOPCTRL_MIB_MAX_PKT_SIZE + UNIMAC_TOPCTRL_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxTxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,FRM_LEN,frame_length,UNIMAC_MAX_FRAME_LENGHT);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#else //!47622
+void mac_hwapi_set_tx_max_frame_len(rdpa_emac emacNum,uint32_t maxTxFrameLen )
+{
+
+    S_UNIMAC_TOP_CFG1_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxTxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,FRM_LEN,frame_length,UNIMAC_MAX_FRAME_LENGHT);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_set_tx_max_frame_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port RX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the port maximum receive unit size in bytes							  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                           	     										  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   maxRxFrameLen - size of current MRU									  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM47622)
+void mac_hwapi_get_rx_max_frame_len(rdpa_emac emacNum,uint32_t *maxRxFrameLen )
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,FRM_LEN,frame_length,*maxRxFrameLen );
+}
+#else //!47622
+void mac_hwapi_get_rx_max_frame_len(rdpa_emac emacNum,uint32_t *maxRxFrameLen )
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,RX_MAX_PKT_SIZE,max_pkt_size,*maxRxFrameLen );
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_get_rx_max_frame_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_rx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port RX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the port maximum receive unit size in bytes							  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    maxRxFrameLen - size of current MRU        							  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   									  									  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM47622)
+void mac_hwapi_set_rx_max_frame_len(rdpa_emac emacNum,uint32_t maxRxFrameLen )
+{
+    S_UNIMAC_TOPCTRL_MAX_PKT_SZ_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOPCTRL_MIB_MAX_PKT_SIZE + UNIMAC_TOPCTRL_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxRxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,FRM_LEN,frame_length,maxRxFrameLen);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#else //!47622
+void mac_hwapi_set_rx_max_frame_len(rdpa_emac emacNum,uint32_t maxRxFrameLen )
+{
+    S_UNIMAC_TOP_CFG1_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxRxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,RX_MAX_PKT_SIZE,max_pkt_size,maxRxFrameLen);
+
+    /*put emac out sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_set_rx_max_frame_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_igp_len	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port inter frame gap                                 	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the inter frame gap	size in bytes									  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   txIpgLen - length in bytes                                               */
+/*                                                                            */
+/* Output:                                                                    */
+/*    																		  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_igp_len(rdpa_emac emacNum,uint32_t txIpgLen )
+{
+    /*we assume that txIpgLen called with bits time resolution*/
+    uint32_t	newIpg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    txIpgLen += 7;
+    newIpg = txIpgLen / 8;
+
+    if (newIpg < 8)
+    {
+        newIpg = 8;
+    } else if (newIpg > 27)
+    {
+        newIpg = 27;
+    }
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,newIpg );
+
+    /*put emac out sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+
+}
+EXPORT_SYMBOL(mac_hwapi_set_tx_igp_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_igp_len	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port inter frame gap                                 	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the inter frame gap	size in bytes									  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                      							          */
+/*                                                                            */
+/* Output:                                                                    */
+/*    txIpgLen - length in bytes    										  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_igp_len(rdpa_emac emacNum,uint32_t *txIpgLen )
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,*txIpgLen );
+
+}
+EXPORT_SYMBOL(mac_hwapi_get_tx_igp_len);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_mac_status	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port status                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the status of mac													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    macStatus  :  														  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_mac_status(rdpa_emac emacNum,S_HWAPI_MAC_STATUS *macStatus)
+{
+
+}
+EXPORT_SYMBOL(mac_hwapi_get_mac_status);
+
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_flow_control                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*           																  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   flowControl - structure with parameters of tx and rx flow control		  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM47622)
+void mac_hwapi_get_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    uint32_t	rxFlow, txFlow;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,rx_pause_ignore,rxFlow);
+    UNIMAC_READ_FIELD(emacNum,CMD,tx_pause_ignore,txFlow);
+    flowControl->rxFlowEnable	= !rxFlow;
+    flowControl->txFlowEnable	= !txFlow;
+}
+#else //!47622
+void mac_hwapi_get_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    uint32_t	rxFlow, txFlow, value;
+    uintptr_t	misc_top_address;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    misc_top_address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+    READ_32(misc_top_address, value);
+
+
+    if(value & UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT)
+    {
+        UNIMAC_READ_FIELD(emacNum,CMD,rx_pause_ignore,rxFlow);
+        UNIMAC_READ_FIELD(emacNum,CMD,tx_pause_ignore,txFlow);
+        flowControl->rxFlowEnable	= !rxFlow;
+        flowControl->txFlowEnable	= !txFlow;
+    }
+    else
+    {
+        flowControl->rxFlowEnable = 0;
+        flowControl->txFlowEnable = 0;
+    }
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_get_flow_control);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_pause_params                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   flowControl - structure with parameters of tx and rx flow control        */
+/*                                                                            */
+/* Output:                                                                    */
+/*   						  												  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_pause_params(rdpa_emac emacNum,int32_t pauseCtrlEnable,uint32_t pauseTimer,uint32_t pauseQuanta)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_control_en,pauseCtrlEnable );
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_timer,pauseTimer );
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_QUNAT,pause_quant,pauseQuanta );
+}
+EXPORT_SYMBOL(mac_hwapi_set_pause_params);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_flow_control                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   flowControl - structure with parameters of tx and rx flow control        */
+/*                                                                            */
+/* Output:                                                                    */
+/*   						  												  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM47622)
+void mac_hwapi_set_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_override_rx, 1);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_override_tx, 1);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,rx_pause_ignore, !flowControl->rxFlowEnable);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,tx_pause_ignore, !flowControl->txFlowEnable);
+}
+#else //!47622
+void mac_hwapi_set_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    uintptr_t misc_top_address;
+    uint32_t value;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,rx_pause_ignore, !flowControl->rxFlowEnable);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,tx_pause_ignore, !flowControl->txFlowEnable);
+    misc_top_address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+    READ_32(misc_top_address, value);
+
+    if(flowControl->rxFlowEnable || flowControl->txFlowEnable)
+        value |= UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT;
+    else
+        value &= ~UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT;
+
+    WRITE_32(misc_top_address, value);
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_set_flow_control);
+
+
+static rdpa_emac_rx_stat_t rxCountersLast[MAX_NUM_OF_EMACS];
+#define UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, param) \
+    do{\
+        uint32_t  paramCurrent = rxCounters->param; \
+        if(mac_unlikely(rxCounters->param < rxCountersLast[emacNum].param)){    \
+            rxCounters->param += (0xFFFFFFFF-rxCountersLast[emacNum].param)+1;    \
+        }else{  \
+            rxCounters->param -= rxCountersLast[emacNum].param; \
+        }   \
+        rxCountersLast[emacNum].param   = paramCurrent; \
+    }while(0)
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rx_counters	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	get the rx counters of port                           	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the rx counters of port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    rxCounters  :  structure filled with counters							  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_rx_counters(rdpa_emac emacNum,rdpa_emac_rx_stat_t *rxCounters)
+{
+    uint32_t		tempVal;
+
+    if (!(enabled_emac & (1 << emacNum)))
+    {
+        memset(rxCounters, 0, sizeof(rdpa_emac_rx_stat_t));
+        return;
+    }
+
+    UNIMAC_READ32_MIB(emacNum,GRALN,rxCounters->alignment_error);
+    UNIMAC_READ32_MIB(emacNum,GRBCA,rxCounters->broadcast_packet);
+    UNIMAC_READ32_MIB(emacNum,GRUC, rxCounters->unicast_packet);
+    UNIMAC_READ32_MIB(emacNum,GRBYT,rxCounters->byte);
+    UNIMAC_READ32_MIB(emacNum,RRBYT,tempVal);
+    rxCounters->byte                    +=	tempVal;
+    UNIMAC_READ32_MIB(emacNum,GRFCR,rxCounters->carrier_sense_error);
+    UNIMAC_READ32_MIB(emacNum,GRCDE,rxCounters->code_error);
+    UNIMAC_READ32_MIB(emacNum,GRXCF,rxCounters->control_frame);
+    UNIMAC_READ32_MIB(emacNum,GRFCS,rxCounters->fcs_error);
+    rxCounters->fragments				=	0;//?????
+    UNIMAC_READ32_MIB(emacNum,GR255,rxCounters->frame_128_255);
+    UNIMAC_READ32_MIB(emacNum,GR2047,tempVal);
+    rxCounters->frame_1519_mtu			=	tempVal;
+    UNIMAC_READ32_MIB(emacNum,GR4095,tempVal);
+    rxCounters->frame_1519_mtu			+=	tempVal;
+    UNIMAC_READ32_MIB(emacNum,GR9216,tempVal);
+    rxCounters->frame_1519_mtu			+=	tempVal;
+
+    UNIMAC_READ32_MIB(emacNum,GR511,rxCounters->frame_256_511);
+
+    UNIMAC_READ32_MIB(emacNum,GR1023,rxCounters->frame_512_1023);
+
+    UNIMAC_READ32_MIB(emacNum,GR1518,rxCounters->frame_1024_1518);
+
+    UNIMAC_READ32_MIB(emacNum,GR64,rxCounters->frame_64);
+
+    UNIMAC_READ32_MIB(emacNum,GR127,rxCounters->frame_65_127);
+
+    UNIMAC_READ32_MIB(emacNum,GRFLR,rxCounters->frame_length_error);
+
+    UNIMAC_READ32_MIB(emacNum,GRJBR,rxCounters->jabber);
+
+    UNIMAC_READ32_MIB(emacNum,GRMCA,rxCounters->multicast_packet);
+
+    rxCounters->overflow				=	0;//no matched counter
+    UNIMAC_READ32_MIB(emacNum,GROVR,rxCounters->oversize_packet);
+	
+    UNIMAC_READ32_MIB(emacNum,RRPKT,rxCounters->undersize_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GRPKT,rxCounters->packet);
+    
+    UNIMAC_READ32_MIB(emacNum,GRXPF,rxCounters->pause_control_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GRXUO,rxCounters->unknown_opcode);
+
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, alignment_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, broadcast_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, unicast_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, byte);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, carrier_sense_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, code_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, control_frame);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, fcs_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_64);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_65_127);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_128_255);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_256_511);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_512_1023);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_1024_1518);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_1519_mtu);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_length_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, jabber);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, multicast_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, oversize_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, undersize_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, pause_control_frame);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, unknown_opcode);
+}
+EXPORT_SYMBOL(mac_hwapi_get_rx_counters);
+
+
+static rdpa_emac_tx_stat_t txCountersLast[MAX_NUM_OF_EMACS];
+#define UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, param) \
+    do{\
+        uint32_t  paramCurrent = txCounters->param; \
+        if(mac_unlikely(txCounters->param < txCountersLast[emacNum].param)){    \
+            txCounters->param += (0xFFFFFFFF-txCountersLast[emacNum].param)+1;    \
+        }else{  \
+            txCounters->param -= txCountersLast[emacNum].param; \
+        }   \
+        txCountersLast[emacNum].param   = paramCurrent; \
+    }while(0)
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_counters	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	get the tx counters of port                           	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the tx counters of port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    txCounters  :  structure filled with counters							  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_counters(rdpa_emac emacNum,rdpa_emac_tx_stat_t *txCounters)
+{
+    /*fill the rdpa counters structure*/
+    uint32_t		tempVal;
+
+    if (!(enabled_emac & (1 << emacNum)))
+    {
+        memset(txCounters, 0, sizeof(rdpa_emac_tx_stat_t));
+        return;
+    }
+
+    UNIMAC_READ32_MIB(emacNum,GTBYT,txCounters->byte);
+
+    UNIMAC_READ32_MIB(emacNum,GTBCA,txCounters->broadcast_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTMCA, txCounters->multicast_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTUC, txCounters->unicast_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTXCF,txCounters->control_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTDRF,txCounters->deferral_packet);
+
+
+    UNIMAC_READ32_MIB(emacNum,GTNCL,tempVal);
+    txCounters->error						= tempVal;
+    UNIMAC_READ32_MIB(emacNum,GTOVR,tempVal);
+    txCounters->error						+= tempVal;
+    UNIMAC_READ32_MIB(emacNum,GTFCS,tempVal);
+    txCounters->error						+= tempVal;
+    UNIMAC_READ32_MIB(emacNum,GTEDF,txCounters->excessive_deferral_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTFCS,txCounters->fcs_error	);
+
+    UNIMAC_READ32_MIB(emacNum,GTFRG,txCounters->fragments_frame);
+
+    UNIMAC_READ32_MIB(emacNum,TR1518,txCounters->frame_1024_1518);
+
+    UNIMAC_READ32_MIB(emacNum,TR255,  txCounters->frame_128_255);
+
+    UNIMAC_READ32_MIB(emacNum,TR2047,  tempVal);
+    txCounters->frame_1519_mtu			=   tempVal;
+    UNIMAC_READ32_MIB(emacNum,TR4095,  tempVal);
+    txCounters->frame_1519_mtu			+=   tempVal;
+    UNIMAC_READ32_MIB(emacNum,TR9216,  tempVal);
+    txCounters->frame_1519_mtu			+=   tempVal;
+    UNIMAC_READ32_MIB(emacNum,TR511,  txCounters->frame_256_511);
+
+    UNIMAC_READ32_MIB(emacNum,TR1023, txCounters->frame_512_1023);
+
+    UNIMAC_READ32_MIB(emacNum,TR64,txCounters->frame_64);
+
+    UNIMAC_READ32_MIB(emacNum,TR127, txCounters->frame_65_127);
+
+    UNIMAC_READ32_MIB(emacNum,GTJBR, txCounters->jabber_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTLCL, txCounters->late_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTMCL, txCounters->multiple_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTOVR,txCounters->oversize_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTPOK, txCounters->packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTXPF, txCounters->pause_control_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTSCL, txCounters->single_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTNCL, txCounters->total_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTXCL, txCounters->excessive_collision);
+
+    txCounters->underrun					=	0;
+    txCounters->undersize_frame				=	0;
+
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, byte);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, broadcast_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, multicast_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, unicast_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, deferral_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, excessive_deferral_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, control_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, jabber_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, oversize_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, pause_control_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, fragments_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, error);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, fcs_error);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_64);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_65_127);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_128_255);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_256_511);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_512_1023);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_1024_1518);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_1519_mtu);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, single_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, total_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, late_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, multiple_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, excessive_collision);
+}
+EXPORT_SYMBOL(mac_hwapi_get_tx_counters);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_init_emac	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_init_emac(rdpa_emac emacNum)
+{
+    /*configure the emac and put it in automatic speed mode*/
+    S_UNIMAC_CMD_REG	mCfgReg;
+    uint32_t max_frame_length = UNIMAC_MAX_FRAME_LENGHT;
+
+#if defined(CONFIG_BCM4908)
+    soc_base_address = RDP_BASE;
+#endif
+
+    /*before calling this function make sure you pull out of reset the emac */
+
+    /*put the emac in sw_reset state*/
+    //UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    /* Do the initialization */
+#ifndef CONFIG_BRCM_QEMU    
+    mCfgReg.tx_ena          =   0;
+    mCfgReg.rx_ena          =   0;
+#else 
+    printk("%s RX TX Enable no PHY EXIST\n",__FUNCTION__);
+    mCfgReg.tx_ena      =   1;
+    mCfgReg.rx_ena      =   1;
+
+#endif 
+    /* for 63138 - even though the EMAC_1 is connected to SF2 @ 2Gbps, we still set the link to 1G.
+     * Actual speed of the link is derived from SF2 based on the speed set for IMP port#8.  */
+    mCfgReg.eth_speed		=	UNIMAC_SPEED_1000;
+    mCfgReg.promis_en		=	1;
+    mCfgReg.pad_en			=	0;
+    mCfgReg.pause_fwd		=	1;
+    mCfgReg.crc_fwd			=	1;
+    mCfgReg.ena_ext_config	=	0;
+    mCfgReg.rx_pause_ignore	=	0;
+    mCfgReg.tx_pause_ignore	=	0;
+    mCfgReg.tx_addr_ins		=	0;
+    mCfgReg.lcl_loop_ena	=	0;
+    mCfgReg.cntl_frm_ena	=	1;
+    mCfgReg.no_lgth_check	=	1;
+    mCfgReg.rmt_loop_ena	=	0;
+    mCfgReg.rx_err_disc		=	0;
+    mCfgReg.prbl_ena		=	0;
+    mCfgReg.cntl_frm_ena	=	1;
+
+    /*write the configuration */
+    UNIMAC_WRITE32_REG(emacNum,CMD,mCfgReg);
+    UNIMAC_WRITE32_REG(emacNum,FRM_LEN, max_frame_length);
+
+    /*take out the emac from sw_reset state*/
+    //UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+#if 0
+    /*configure the pause control*/
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_timer,UNIMAC_DEFAULT_PAUSE_TIMER);
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_control_en,1);
+
+    /*configure the pause quanta*/
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_QUNAT,pause_quant,UNIMAC_DEFAULT_PAUSE_QUANTA);
+
+    /*write default ipg*/
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,UNIMAC_DEFAULT_IPG);
+#endif
+    memset(&rxCountersLast, 0, MAX_NUM_OF_EMACS*sizeof(rdpa_emac_rx_stat_t));
+    memset(&txCountersLast, 0, MAX_NUM_OF_EMACS*sizeof(rdpa_emac_tx_stat_t));
+
+    enabled_emac |= (1 << emacNum);
+
+    /*emac is ready to go!*/
+}
+EXPORT_SYMBOL(mac_hwapi_init_emac);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_loopback	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_loopback(rdpa_emac emacNum,MAC_LPBK *loopback)
+{
+    S_UNIMAC_CMD_REG	mCmdReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCmdReg);
+
+    if (mCmdReg.lcl_loop_ena && mCmdReg.rmt_loop_ena)
+    {
+        *loopback = MAC_LPBK_BOTH;
+    }
+    else if (mCmdReg.lcl_loop_ena)
+    {
+        *loopback = MAC_LPBK_LOCAL;
+    }
+    else if (mCmdReg.rmt_loop_ena)
+    {
+        *loopback = MAC_LPBK_REMOTE;
+    }
+    else
+    {
+        *loopback = MAC_LPBK_NONE;
+    }
+
+}
+EXPORT_SYMBOL(mac_hwapi_get_loopback);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_loopback	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	set loopback type of the mac	                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_loopback(rdpa_emac emacNum,MAC_LPBK loopback)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put the emac in sw_reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+    switch(loopback)
+    {
+        case MAC_LPBK_BOTH:
+            UNIMAC_WRITE_FIELD(emacNum,CMD,rmt_loop_ena,1);
+            UNIMAC_WRITE_FIELD(emacNum,CMD, lcl_loop_ena,1);
+            break;
+        case MAC_LPBK_LOCAL:
+            UNIMAC_WRITE_FIELD(emacNum,CMD, lcl_loop_ena,1);
+            break;
+        case MAC_LPBK_REMOTE:
+            UNIMAC_WRITE_FIELD(emacNum,CMD,rmt_loop_ena,1);
+            break;
+        case MAC_LPBK_NONE:
+            UNIMAC_WRITE_FIELD(emacNum,CMD,rmt_loop_ena,0);
+            UNIMAC_WRITE_FIELD(emacNum,CMD, lcl_loop_ena,0);
+            break;
+        default:
+
+            break;
+    }
+    /* take out the emac from sw_reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+
+}
+EXPORT_SYMBOL(mac_hwapi_set_loopback);
+
+#if !defined(CONFIG_BCM47622)
+void mac_hwapi_set_unimac_cfg(rdpa_emac emacNum, int32_t enabled)
+{
+    S_UNIMAC_CFG_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(address,cfgreg);
+    cfgreg.gmii_direct = enabled ? 1 : 0;
+    WRITE_32(address,cfgreg);
+}
+EXPORT_SYMBOL(mac_hwapi_set_unimac_cfg);
+#endif //!47622
+
+void mac_hwapi_modify_flow_control_pause_pkt_addr ( rdpa_emac emacNum,bdmf_mac_t mac)
+{
+    uint32_t value = *(uint32_t*)(&(mac.b[4])) >> 16 ;
+    uintptr_t mac_address = (uintptr_t)UNIMAC_CONFIGURATION_UMAC_0_RDP_MAC0 + UNIMAC_CONF_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    WRITE_32(mac_address, *(uint32_t*)mac.b);
+
+    mac_address = (uintptr_t)UNIMAC_CONFIGURATION_UMAC_0_RDP_MAC1 + UNIMAC_CONF_INSTANCE_OFFSET(emacNum);
+    WRITE_32(mac_address, value);
+
+}
+EXPORT_SYMBOL(mac_hwapi_modify_flow_control_pause_pkt_addr);
+
+#if !defined(CONFIG_BCM47622)
+void mac_hwapi_set_backpressure_ext(rdpa_emac emacNum,int32_t enable)
+{
+#if defined(CONFIG_BCM63138) || defined(CONFIG_BCM63148) || defined(CONFIG_BCM4908) || defined(CONFIG_BCM63158)
+    S_UNIMAC_TOP_CFG2_REG cfgreg;
+    uintptr_t misc_top_address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(misc_top_address,cfgreg);
+    cfgreg.backpressure_enable_ext = (enable ? 1 : 0);
+    WRITE_32(misc_top_address,cfgreg);
+#endif
+}
+EXPORT_SYMBOL(mac_hwapi_set_backpressure_ext);
+#endif //!47622
+
+void mac_hwapi_set_eee(rdpa_emac emacNum, int32_t enable)
+{
+    uint32_t eee_ref_count = 0;
+    uint32_t eee_wake_timer = 0;
+    uint32_t eee_lpi_timer = 0;
+
+    S_UNIMAC_EEE_CTRL_REG eee_ctrl;
+    S_HWAPI_MAC_STATUS  mac_mode;
+
+    /* Determine EEE timers only when EEE is enabled */
+    if (enable)
+    {
+#if defined(CONFIG_BCM63158) || defined(CONFIG_BCM6856) || defined(CONFIG_BCM47622) || defined(CONFIG_BCM6878)
+        eee_ref_count = 0xfa; /* 250 Mhz */;
+#else
+        get_rdp_freq(&eee_ref_count);
+        eee_ref_count /= 2;
+#endif
+
+        /* Read actual mac speed */
+        UNIMAC_READ32_REG(emacNum, MODE, mac_mode);
+
+        switch (mac_mode.mac_speed) {
+        case rdpa_emac_rate_100m: /* 100Mbps */
+            {
+                eee_lpi_timer = 0x3c; /* 60 uS */
+                eee_wake_timer = 0x1e; /* 30 uS */
+                break;
+            }
+        case rdpa_emac_rate_1g: /* 1000Mbps */
+            {
+                eee_lpi_timer = 0x22; /* 34 uS */
+                eee_wake_timer = 0x11; /* 17 uS */
+                break;
+            }
+        case rdpa_emac_rate_2_5g: /* 2500Mbps */
+            {
+                eee_lpi_timer = 0x3c; /* 60 uS */
+                eee_wake_timer = 0x1e; /* 30 uS */
+                break;
+            }
+        default:
+            break;
+        }
+    }
+
+    UNIMAC_READ32_REG(emacNum, EEE_CTRL, eee_ctrl);
+    eee_ctrl.eee_en = enable ? 1 : 0;
+    UNIMAC_WRITE32_REG(emacNum, EEE_CTRL, eee_ctrl);
+    UNIMAC_WRITE32_REG(emacNum, EEE_REF_COUNT, eee_ref_count);
+
+#if defined(CONFIG_BCM6856)
+    if (mac_mode.mac_speed == rdpa_emac_rate_100m)
+    {
+        UNIMAC_WRITE32_REG(emacNum, EEE_MII_LPI_TIMER, eee_lpi_timer);
+        UNIMAC_WRITE32_REG(emacNum, EEE_MII_WAKE_TIMER, eee_wake_timer);
+    }
+    else
+    {
+        UNIMAC_WRITE32_REG(emacNum, EEE_GMII_LPI_TIMER, eee_lpi_timer);
+        UNIMAC_WRITE32_REG(emacNum, EEE_GMII_WAKE_TIMER, eee_wake_timer);
+    }
+#else
+    UNIMAC_WRITE32_REG(emacNum, EEE_LPI_TIMER, eee_lpi_timer);
+    UNIMAC_WRITE32_REG(emacNum, EEE_WAKE_TIMER, eee_wake_timer);
+#endif
+}
+EXPORT_SYMBOL(mac_hwapi_set_eee);
diff --git a/arch/arm/mach-bcmbca/rng/Makefile b/arch/arm/mach-bcmbca/rng/Makefile
new file mode 100644
index 0000000000..709675655d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rng/Makefile
@@ -0,0 +1,3 @@
+
+obj-y +=                \
+    rng.o    \
diff --git a/arch/arm/mach-bcmbca/rng/rng.c b/arch/arm/mach-bcmbca/rng/rng.c
new file mode 100644
index 0000000000..a0a8f6931f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/rng/rng.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2019 Broadcom Ltd.
+ */
+/*
+ * 
+ */
+// BCMFORMAT: notabs reindent:uncrustify:bcm_minimal_i4.cfg
+
+#include <common.h>
+#include <linux/types.h>
+#include "linux/printk.h"
+#include <asm/arch/rng.h>
+#include <asm/arch/misc.h>
+#include "bcm_rng.h"
+
+
+int rng_pac_lock(uint32_t perm)
+{
+    uint32_t startRegion;
+    if (perm == RNG_PERM_DISABLE_ALL)  {
+        RNG->perm = perm; 
+    } else {
+        RNG->perm |= perm; 
+    }
+}
+
diff --git a/arch/arm/mach-bcmbca/spl_ddrinit.c b/arch/arm/mach-bcmbca/spl_ddrinit.c
new file mode 100644
index 0000000000..870ae0bb14
--- /dev/null
+++ b/arch/arm/mach-bcmbca/spl_ddrinit.c
@@ -0,0 +1,328 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <hash.h>
+#include "spl_ddrinit.h"
+#include "spl_env.h"
+#ifdef CONFIG_BCMBCA_DDRC_SCRAMBLER
+#include "asm/arch/rng.h"
+#endif
+#include "asm/arch/ddr.h"
+#include "asm/arch/misc.h"
+#include "boot_blob.h"
+#include "tpl_params.h"
+#include "early_abort.h"
+
+uint32_t ddr_size=0;
+uint32_t mcb_sel = 0;
+uint32_t safe_mode = 0;
+
+uint8_t* ddr_stdalone = NULL;
+int ddr_stdsize = BOOT_BLOB_MAX_DDR_SIZE;
+int early_reset = 0;
+
+uint32_t get_ddr_size()
+{
+	return ddr_size;
+}
+
+#ifdef CONFIG_BCMBCA_DDRC_SCRAMBLER
+static int sec_gen_sha256(uint8_t * buf, int buf_len, uint8_t * hash,
+			  int hash_len)
+{
+	struct hash_algo *algo;
+	void *ctx;
+	int ret = 0;
+	const char *algo_name = "sha256";
+
+	/* Calculate hash of the esbc key */
+	ret = hash_progressive_lookup_algo(algo_name, &algo);
+	if (ret)
+		return ret;
+
+	ret = -1;
+	if (algo->digest_size != hash_len)
+		return ret;
+
+	ret = algo->hash_init(algo, &ctx);
+	if (ret)
+		return ret;
+
+	ret = algo->hash_update(algo, ctx, buf, buf_len, 1);
+	if (ret)
+		return ret;
+
+	/* Copy hash at destination buffer */
+	ret = algo->hash_finish(algo, ctx, hash, algo->digest_size);
+	if (ret)
+		return ret;
+
+	return ret;
+}
+
+static int ddr_gen_scramber_seed(uint32_t * seed)
+{
+	int timeout = 0, i = 0, ret = -1;
+	uint32_t random[16];
+	uint32_t digest[8];
+
+	/* make sure RNG is ready for random number. In 4908 platform it is on automaticall by hardware */
+	while ((RNG->intStatus & RNG_INT_STATUS_NIST_FAIL) == 0x0
+	       && (RNG->intStatus & RNG_INT_STATUS_FIFO_FULL) == 0x0) {
+		udelay(1);
+		timeout++;
+		if (timeout > 500000) {
+			printf("memc_setup_scrambler RNG time out\r\n");
+			return -1;
+		}
+	}
+
+	/* fetch 16 words from RNG and run them through the SHA256 to get zeros and ones balanced RN */
+	i = 0;
+	while (i < 16) {
+		if (RNG->fifoCnt & 0xff) {
+			random[i] = RNG->rngFifoData;
+			i++;
+		}
+	}
+
+	ret = sec_gen_sha256((uint8_t *) random, 64, (uint8_t *) digest, 32);
+	if (ret != 0)
+		return ret;
+
+	for (i = 0; i < 4; i++) {
+		seed[i] = digest[i];
+	}
+
+	return 0;
+}
+#endif
+
+static int load_mcb(uint32_t selector, uint8_t * mcb, int* len)
+{
+	int ret = 0;
+	
+	if ((ret = load_boot_blob(MCB_TABLE_MAGIC, selector, mcb, len)) == BOOT_BLOB_NOT_IN_HASTTBL
+	   && (selector&BP_DDR_TEMP_MASK) == BP_DDR_TEMP_NORMAL) {
+		/* If normal temperature mcb not found, try the ASR mcb. It works for normal T too */
+		ret = load_boot_blob(MCB_TABLE_MAGIC, selector|BP_DDR_TEMP_EXTENDED_ASR, mcb, len);
+	}
+
+	return ret;
+}
+
+static int get_mcb_selector(uint32_t mcb_mode, uint32_t sel, uint32_t* mcb)
+{
+	int size = MCB_SIZE;
+
+#ifdef CONFIG_BCMBCA_DDR_DEF_MCBSEL
+	mcb_sel = CONFIG_BCMBCA_DDR_DEF_MCBSEL;
+	if ((mcb_mode&SPL_DDR_INIT_MCB_OVRD) && (mcb_mode&SPL_DDR_INIT_DDR4_SAFE_MODE)) { 
+#ifdef CONFIG_BCMBCA_DDR4_DEF_MCBSEL
+		mcb_sel = CONFIG_BCMBCA_DDR4_DEF_MCBSEL;
+#endif
+	}
+#else
+#error "Must define mcb default selector value in mach-bcmbca/bcm<chip>/Kconfig!"
+#endif
+
+	if (!IS_JTAG_LOADED(boot_params)) {
+#ifdef CONFIG_BCMBCA_DDR_MCBSEL_OVERRIDE
+#if (CONFIG_BCMBCA_DDR_MCBSEL_OVERRIDE_VALUE==0x0)
+#error "Must define mcb selector override value in bcm9<chip>_defconfig!"
+#else
+		mcb_sel = CONFIG_BCMBCA_DDR_MCBSEL_OVERRIDE_VALUE;
+		printf("Using forced mcb selector value %x\n", mcb_sel);
+#endif
+#else
+		void *ebuffer;
+		char msel[32];
+		/* load mcb_sel from environment variables */
+		/* We'll borrow the DDR init buffer to do this */
+		if (mcb_mode & SPL_DDR_INIT_MCB_OVRD) {
+			if (mcb_mode&SPL_DDR_INIT_MCB_SEL) {
+				mcb_sel = sel;
+			} else {
+				safe_mode = 1;
+			}
+		} else {
+			ebuffer = load_spl_env((void *)CONFIG_BCMBCA_DDR_LOADADDR);
+			if ( (NULL != ebuffer) && (0 == get_spl_env_val(ebuffer, "MCB", msel, sizeof(msel)))) {
+				mcb_sel = simple_strtoul(msel, NULL, 16);
+				if (strstr(msel,"reset")) {
+					printf("EARLY RESET REQUESTED\n");
+					early_reset = 1;
+				}
+			}
+			else {
+				safe_mode = 1;
+				printf("no mcb specified explicitly, use safe mode\n");
+			}
+		}
+#endif
+		if (load_mcb(BP_DDR_SEL_VALUE(mcb_sel), (void *)mcb, &size)) {
+			printf("mcb selector 0x%x not found ", BP_DDR_SEL_VALUE(mcb_sel));
+			mcb_sel = CONFIG_BCMBCA_DDR_DEF_MCBSEL;
+			safe_mode = 1;
+			printf("using  0x%x instead\n",mcb_sel);
+			size = MCB_SIZE;
+			if (load_mcb(mcb_sel, (void*)mcb, &size)) {
+				printf("mcb load failed\n");
+				return -1;
+			}
+		}
+	} else {
+		memcpy(mcb, (uint8_t *)(CONFIG_BCMBCA_DDR_LOADADDR + CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE + JTAG_LOAD_MCB_BIN_OFFSET), MCB_SIZE);
+		mcb_sel =
+		    *(uint32_t *) (CONFIG_BCMBCA_DDR_LOADADDR + CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE);
+	}
+
+	return 0;
+}
+
+static int load_ddr_stdalone(int is_ddr4, void *ddr_bin, int *len)
+{
+	return load_boot_blob(is_ddr4 ? DDR4_TABLE_MAGIC : DDR3_TABLE_MAGIC, 0,
+			      ddr_bin, len);
+}
+
+static ddr_init_func load_ddrinit(void)
+{
+	ddr_init_func ddr_init;
+
+	ddr_stdalone = (uint8_t*)CONFIG_BCMBCA_DDR_LOADADDR;
+	ddr_init = (ddr_init_func) ddr_stdalone;
+	
+	if (!IS_JTAG_LOADED(boot_params)) {
+#if defined(CONFIG_BCMBCA_DDR_REGINIT)
+		ddr_init = (ddr_init_func) ddr_init_reg;
+#else
+		if (load_ddr_stdalone(BP_DDR_IS_DDR4(mcb_sel), (void *)ddr_stdalone, &ddr_stdsize)) {
+			printf("failed to load ddr standalone module!\n");
+			return (ddr_init_func)NULL;
+		}
+
+		flush_dcache_all();
+		invalidate_icache_all();
+#if defined(CONFIG_BCMBCA_DPFE)
+		/* DPFE need a wrapper function to call the standalone */
+		ddr_init = (ddr_init_func) ddr_init_dpfe;
+#endif
+
+#endif
+	} else {
+		flush_dcache_all();
+		invalidate_icache_all();
+#if defined(CONFIG_BCMBCA_DPFE)
+		/* DPFE need a wrapper function to call the standalone */		
+		ddr_init = (ddr_init_func) ddr_init_dpfe;
+		ddr_stdsize=CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE;
+#endif
+	}
+
+	return ddr_init;
+}
+
+static int run_ddrinit(ddr_init_func ddr_init, uint32_t* mcb_ptr)
+{
+	uint32_t seed[4];
+	ddr_init_param param;
+
+#ifdef CONFIG_BCMBCA_DDRC_SCRAMBLER
+	if (ddr_gen_scramber_seed(seed))
+		return -1;
+#endif
+
+	printf("mcb selector 0x%x checksum 0x%x safe_mode %d\n", mcb_sel, ((uint32_t*)mcb_ptr)[3],safe_mode);
+	param.mcb_sel = mcb_sel;
+	param.mcb = mcb_ptr;
+	param.seed = seed;
+	param.safe_mode = safe_mode;
+	param.ddr_size = &ddr_size;
+#if defined(CONFIG_BCMBCA_DPFE)
+	param.dpfe_stdalone = (void*)ddr_stdalone;
+	/* add extra space for stdalone bss size */
+	param.dpfe_segbuf = (uint8_t*)(ALIGN((uintptr_t)ddr_stdalone+ddr_stdsize+0x2000, 64));
+
+	printf("dpfe stdalone addr %p, seg buf %p\n", param.dpfe_stdalone, param.dpfe_segbuf);
+#endif
+
+	return (*ddr_init) (&param);
+}
+
+void spl_list_mcb_sel(void)
+{
+	struct overlays* entry;
+	int i = 0;
+
+	printf("\nMCB selector Mask 0x%08x:\n", BP_DDR_CONFIG_MASK&~BP_DDR_TEMP_EXTENDED_ASR);
+	printf("Supported MCB selectors:\n");
+
+	do {
+		entry =  get_boot_blob_hash_entry(i);
+		if (!entry)
+			break;
+
+		if (entry->ovltype == MCB_TABLE_MAGIC) {
+			printf("\t0x%08x\n", entry->selector&BP_DDR_CONFIG_MASK);
+		}
+		i++;
+	} while (1);
+}
+
+/* This function is calle by arch_cpu_init very early during the boot
+   to turn on DDR VREF_DQ voltage as soon as possible. Otherwise it may 
+   be too late when ddr library to turn it
+*/
+void spl_ddrinit_prepare(void)
+{
+#ifdef CONFIG_BCMBCA_DDRC_EARLY_VREF_DQ
+	u32 reg = 0;
+
+	while (!(MEMC->CHN_TIM_PHY_ST&MEMC_CHN_TIM_PHY_ST_PHY_ST_POWER_UP));
+
+	MEMC->PhyControl.VREF_DAC_CTRL &= ~DDRPHY_VREF_DAC_CTRL_PDN_MASK;
+
+	reg = MEMC->PhyControl.VREF_DAC_CTRL;
+	reg &= ~(DDRPHY_VREF_DAC_CTRL_DAC0_MASK|DDRPHY_VREF_DAC_CTRL_DAC1_MASK);
+	reg |= (0x20<<DDRPHY_VREF_DAC_CTRL_DAC0_SHIFT|0x20<<DDRPHY_VREF_DAC_CTRL_DAC1_SHIFT);
+	MEMC->PhyControl.VREF_DAC_CTRL = reg;
+#endif
+}
+
+int spl_ddrinit(uint32_t mcb_mode, uint32_t sel)
+{
+	ddr_init_func ddr_init;
+	uint32_t mcb[MCB_SIZE/sizeof(uint32_t)];
+
+#if !defined(CONFIG_BCMBCA_DDR_REGINIT)
+	if (get_mcb_selector(mcb_mode, sel, mcb))
+		hang();
+#endif
+
+	if ((ddr_init = load_ddrinit()) == NULL)
+		hang();
+
+	if( run_ddrinit(ddr_init, mcb))
+		hang();
+
+	if (IS_JTAG_LOADED(boot_params)) {
+		printf("disable mmu?");
+		icache_disable();
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+		dcache_disable();
+#endif
+
+		jtag_spl_done: for (;;);
+	}
+	if (early_reset) {
+		printf("EARLY_RESET HERE!\n");
+#if defined(BCM_LOWLEVEL_RESET)
+		BCM_LOWLEVEL_RESET();
+#endif
+	}
+	return 0;
+}
diff --git a/arch/arm/mach-bcmbca/ubus/Makefile b/arch/arm/mach-bcmbca/ubus/Makefile
new file mode 100644
index 0000000000..d6e8d469f4
--- /dev/null
+++ b/arch/arm/mach-bcmbca/ubus/Makefile
@@ -0,0 +1,5 @@
+BRCM_CHIP = $(patsubst "bcm%",%,$(CONFIG_SYS_SOC))
+EXTRA_CFLAGS += -DCONFIG_BCM9$(BRCM_CHIP)
+
+obj-y +=				\
+	bcm_ubus_impl1.o	\
diff --git a/arch/arm/mach-bcmbca/ubus/bcm_ubus_impl1.c b/arch/arm/mach-bcmbca/ubus/bcm_ubus_impl1.c
new file mode 100644
index 0000000000..2850cfec62
--- /dev/null
+++ b/arch/arm/mach-bcmbca/ubus/bcm_ubus_impl1.c
@@ -0,0 +1,1617 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Broadcom
+ */
+/*
+ * 
+ */
+
+/* BCM UBUS4 supporting routines */
+
+#if defined(__UBOOT__)
+#include <linux/types.h>
+#include "linux/printk.h"
+#include <asm/arch/ubus4.h>
+#endif
+
+#include "bcm_ubus4.h"
+
+//#define ENABLE_UBUS_REMAP_DEBUG_LOG     
+#ifdef  ENABLE_UBUS_REMAP_DEBUG_LOG
+#define UBUS_REMAP_DEBUG_LOG(fmt, ...) printk("%s:%d "fmt, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#else
+#define UBUS_REMAP_DEBUG_LOG(fmt, ...)  
+#endif
+
+#ifdef CONFIG_BCM_UBUS_DECODE_REMAP
+#define DECODE_WIN0 0
+#define DECODE_WIN1 1
+#define CACHE_BIT_OFF 0
+#define CACHE_BIT_ON 1
+#endif
+
+extern unsigned long getMemorySize(void);
+#define MST_START_DDR_ADDR              0
+
+#if !defined(_CFE_) && !defined(__UBOOT__)
+#include <linux/module.h>
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+
+#define PROC_DIR            "driver/ubus"
+#define UBUS_DECODE_FILE      "decode_cfg"
+#define UBUS_TOKENS_FILE      "tokens"
+static struct proc_dir_entry *proc_dir;
+static struct proc_dir_entry *proc_decode_cfg, *proc_tokens;
+
+static ssize_t ubus_decode_get_proc(struct file *file, char *buff, size_t len, loff_t *offset);
+static ssize_t ubus_tokens_get_proc(struct file *file, char *buff, size_t len, loff_t *offset);
+
+static const struct file_operations ubus_decode_proc_fops = {
+    .read  = ubus_decode_get_proc,
+};
+
+static const struct file_operations ubus_tokens_proc_fops = {
+    .read  = ubus_tokens_get_proc,
+};
+#endif
+
+#ifdef CONFIG_BCM_UBUS_DECODE_REMAP
+/* CONFIG_BCM_FPM_COHERENCY_EXCLUDE is the case when all the memory is coherent except for FPM pool,
+ * since CCI-400 won't sustain 10G traffic load. In that case we remap FPM pool area to be non-coherent
+ */
+#if defined(CONFIG_BCM_FPM_COHERENCY_EXCLUDE)
+static uint32_t fpm_pool_addr;
+static uint32_t fpm_pool_size;
+#endif /* CONFIG_BCM_FPM_COHERENCY_EXCLUDE */
+
+unsigned int g_board_size_power_of_2;
+EXPORT_SYMBOL(g_board_size_power_of_2);
+#endif /* CONFIG_BCM_UBUS_DECODE_REMAP */
+
+ub_mst_addr_map_t ub_mst_addr_map_tbl[] =
+{
+#if IS_BCMCHIP(63158)
+    {UBUS_PORT_ID_BIU,    MST_PORT_NODE_B53_PHYS_BASE},
+    {UBUS_PORT_ID_PER,    MST_PORT_NODE_PER_PHYS_BASE},
+    {UBUS_PORT_ID_USB,    MST_PORT_NODE_USB_PHYS_BASE},
+    {UBUS_PORT_ID_SPU,    MST_PORT_NODE_SPU_PHYS_BASE},
+    {UBUS_PORT_ID_DSL,    MST_PORT_NODE_DSL_PHYS_BASE},
+    {UBUS_PORT_ID_PERDMA, MST_PORT_NODE_PER_DMA_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE0,  MST_PORT_NODE_PCIE0_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE2,  MST_PORT_NODE_PCIE2_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE3,  MST_PORT_NODE_PCIE3_PHYS_BASE},
+    {UBUS_PORT_ID_DSLCPU, MST_PORT_NODE_DSLCPU_PHYS_BASE},
+    {UBUS_PORT_ID_PMC,    MST_PORT_NODE_PMC_PHYS_BASE},
+    {UBUS_PORT_ID_SWH,    MST_PORT_NODE_SWH_PHYS_BASE},
+    {UBUS_PORT_ID_QM,     MST_PORT_NODE_QM_PHYS_BASE},
+    {UBUS_PORT_ID_DQM,    MST_PORT_NODE_DQM_PHYS_BASE},
+    {UBUS_PORT_ID_DMA0,   MST_PORT_NODE_DMA0_PHYS_BASE},
+    {UBUS_PORT_ID_NATC,   MST_PORT_NODE_NATC_PHYS_BASE},
+    {UBUS_PORT_ID_RQ0,    MST_PORT_NODE_RQ0_PHYS_BASE},
+#elif IS_BCMCHIP(63178)
+    {UBUS_PORT_ID_BIU,    MST_PORT_NODE_CPU_PHYS_BASE},
+    {UBUS_PORT_ID_PER,    MST_PORT_NODE_PER_PHYS_BASE},
+    {UBUS_PORT_ID_USB,    MST_PORT_NODE_USB_PHYS_BASE},
+    {UBUS_PORT_ID_DSL,    MST_PORT_NODE_DSL_PHYS_BASE},
+    {UBUS_PORT_ID_DSLCPU, MST_PORT_NODE_DSLCPU_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE0,  MST_PORT_NODE_PCIE0_PHYS_BASE},
+    {UBUS_PORT_ID_PMC,    MST_PORT_NODE_PMC_PHYS_BASE},
+    {UBUS_PORT_ID_SWH,    MST_PORT_NODE_SWH_PHYS_BASE},
+    {UBUS_PORT_ID_WIFI,   MST_PORT_NODE_WIFI_PHYS_BASE},
+#elif IS_BCMCHIP(47622)
+    {UBUS_PORT_ID_BIU,    MST_PORT_NODE_CPU_PHYS_BASE},
+    {UBUS_PORT_ID_PER,    MST_PORT_NODE_PER_PHYS_BASE},
+    {UBUS_PORT_ID_USB,    MST_PORT_NODE_USB_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE0,  MST_PORT_NODE_PCIE0_PHYS_BASE},
+    {UBUS_PORT_ID_PMC,    MST_PORT_NODE_PMC_PHYS_BASE},
+    {UBUS_PORT_ID_SYSPORT,  MST_PORT_NODE_SYSPORT_PHYS_BASE},
+    {UBUS_PORT_ID_SYSPORT1, MST_PORT_NODE_SYSPORT1_PHYS_BASE},
+    {UBUS_PORT_ID_WIFI,   MST_PORT_NODE_WIFI_PHYS_BASE},
+    {UBUS_PORT_ID_WIFI1,  MST_PORT_NODE_WIFI1_PHYS_BASE},
+    {UBUS_PORT_ID_SPU,    MST_PORT_NODE_SPU_PHYS_BASE},
+#elif IS_BCMCHIP(6858)
+    {UBUS_PORT_ID_BIU,       MST_PORT_NODE_B53_PHYS_BASE},
+    {UBUS_PORT_ID_PER,       MST_PORT_NODE_PER_PHYS_BASE},
+    {UBUS_PORT_ID_USB,       MST_PORT_NODE_USB_PHYS_BASE},
+    {UBUS_PORT_ID_PERDMA,    MST_PORT_NODE_PER_DMA_PHYS_BASE},
+    {UBUS_PORT_ID_SPU,       MST_PORT_NODE_SPU_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE0,     MST_PORT_NODE_PCIE0_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE2,     MST_PORT_NODE_PCIE2_PHYS_BASE},
+    {UBUS_PORT_ID_PMC,       MST_PORT_NODE_PMC_PHYS_BASE},
+    {UBUS_PORT_ID_QM,        MST_PORT_NODE_QM_PHYS_BASE},
+    {UBUS_PORT_ID_DQM,       MST_PORT_NODE_DQM_PHYS_BASE},
+    {UBUS_PORT_ID_DMA0,      MST_PORT_NODE_DMA0_PHYS_BASE},
+    {UBUS_PORT_ID_DMA1,      MST_PORT_NODE_DMA1_PHYS_BASE},
+    {UBUS_PORT_ID_NATC,      MST_PORT_NODE_NATC_PHYS_BASE},
+    {UBUS_PORT_ID_TOP_BUFF,  MST_PORT_NODE_TOP_BUFF_PHYS_BASE},
+    {UBUS_PORT_ID_XRDP_BUFF, MST_PORT_NODE_XRDP_BUFF_PHYS_BASE},
+    {UBUS_PORT_ID_RQ0,       MST_PORT_NODE_RQ0_PHYS_BASE},
+    {UBUS_PORT_ID_RQ1,       MST_PORT_NODE_RQ1_PHYS_BASE},
+    {UBUS_PORT_ID_RQ2,       MST_PORT_NODE_RQ2_PHYS_BASE},
+    {UBUS_PORT_ID_RQ3,       MST_PORT_NODE_RQ3_PHYS_BASE},
+#elif IS_BCMCHIP(6878)
+    {UBUS_PORT_ID_BIU,       MST_PORT_NODE_B53_PHYS_BASE},
+    {UBUS_PORT_ID_PER,       MST_PORT_NODE_PER_PHYS_BASE},
+    {UBUS_PORT_ID_USB,       MST_PORT_NODE_USB_PHYS_BASE},
+    {UBUS_PORT_ID_WIFI,      MST_PORT_NODE_WIFI_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE0,     MST_PORT_NODE_PCIE0_PHYS_BASE},
+    {UBUS_PORT_ID_QM,        MST_PORT_NODE_QM_PHYS_BASE},
+    {UBUS_PORT_ID_DMA0,      MST_PORT_NODE_DMA0_PHYS_BASE},
+    {UBUS_PORT_ID_RQ0,       MST_PORT_NODE_RQ0_PHYS_BASE},
+#elif IS_BCMCHIP(6855)
+    {UBUS_PORT_ID_BIU,       MST_PORT_NODE_B53_PHYS_BASE},
+    {UBUS_PORT_ID_PER,       MST_PORT_NODE_PER_PHYS_BASE},
+    {UBUS_PORT_ID_USB,       MST_PORT_NODE_USB_PHYS_BASE},
+    {UBUS_PORT_ID_WIFI,      MST_PORT_NODE_WIFI_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE0,     MST_PORT_NODE_PCIE0_PHYS_BASE},
+    {UBUS_PORT_ID_DMA0,      MST_PORT_NODE_DMA0_PHYS_BASE},
+    {UBUS_PORT_ID_DMA1,      MST_PORT_NODE_DMA1_PHYS_BASE},
+    {UBUS_PORT_ID_DMA2,      MST_PORT_NODE_DMA2_PHYS_BASE},
+    {UBUS_PORT_ID_QM,        MST_PORT_NODE_QM_PHYS_BASE},
+    {UBUS_PORT_ID_RQ0,       MST_PORT_NODE_RQ0_PHYS_BASE},
+    {UBUS_PORT_ID_RQ1,       MST_PORT_NODE_RQ1_PHYS_BASE},
+#elif IS_BCMCHIP(6846)
+    {UBUS_PORT_ID_BIU,       MST_PORT_NODE_B53_PHYS_BASE},
+    {UBUS_PORT_ID_PER,       MST_PORT_NODE_PER_PHYS_BASE},
+    {UBUS_PORT_ID_USB,       MST_PORT_NODE_USB_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE0,     MST_PORT_NODE_PCIE0_PHYS_BASE},
+    {UBUS_PORT_ID_QM,        MST_PORT_NODE_QM_PHYS_BASE},
+    {UBUS_PORT_ID_DQM,       MST_PORT_NODE_DQM_PHYS_BASE},
+    {UBUS_PORT_ID_DMA0,      MST_PORT_NODE_DMA0_PHYS_BASE},
+    {UBUS_PORT_ID_NATC,      MST_PORT_NODE_NATC_PHYS_BASE},
+    {UBUS_PORT_ID_RQ0,       MST_PORT_NODE_RQ0_PHYS_BASE},
+#elif IS_BCMCHIP(6856)
+    {UBUS_PORT_ID_BIU,       MST_PORT_NODE_B53_PHYS_BASE},
+    {UBUS_PORT_ID_PER,       MST_PORT_NODE_PER_PHYS_BASE},
+    {UBUS_PORT_ID_USB,       MST_PORT_NODE_USB_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE2,     MST_PORT_NODE_PCIE2_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE0,     MST_PORT_NODE_PCIE0_PHYS_BASE},
+    {UBUS_PORT_ID_QM,        MST_PORT_NODE_QM_PHYS_BASE},
+    {UBUS_PORT_ID_DQM,       MST_PORT_NODE_DQM_PHYS_BASE},
+    {UBUS_PORT_ID_DMA0,      MST_PORT_NODE_DMA0_PHYS_BASE},
+    {UBUS_PORT_ID_NATC,      MST_PORT_NODE_NATC_PHYS_BASE},
+    {UBUS_PORT_ID_DMA1,      MST_PORT_NODE_DMA1_PHYS_BASE},
+    {UBUS_PORT_ID_RQ0,       MST_PORT_NODE_RQ0_PHYS_BASE},
+    {UBUS_PORT_ID_RQ1,       MST_PORT_NODE_RQ1_PHYS_BASE},
+#elif IS_BCMCHIP(63146)
+    {UBUS_PORT_ID_BIU,       MST_PORT_NODE_B53_PHYS_BASE},
+    {UBUS_PORT_ID_PER,       MST_PORT_NODE_PER_PHYS_BASE},
+    {UBUS_PORT_ID_USB,       MST_PORT_NODE_USB_PHYS_BASE},
+    {UBUS_PORT_ID_DSL,       MST_PORT_NODE_DSL_PHYS_BASE},
+    {UBUS_PORT_ID_DSLCPU,    MST_PORT_NODE_DSLCPU_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE0,     MST_PORT_NODE_PCIE0_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE1,     MST_PORT_NODE_PCIE1_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE2,     MST_PORT_NODE_PCIE2_PHYS_BASE},
+    {UBUS_PORT_ID_DMA0,      MST_PORT_NODE_DMA0_PHYS_BASE},
+    {UBUS_PORT_ID_DMA1,      MST_PORT_NODE_DMA1_PHYS_BASE},
+    {UBUS_PORT_ID_RQ0,       MST_PORT_NODE_RQ0_PHYS_BASE},
+    {UBUS_PORT_ID_QM,        MST_PORT_NODE_QM_PHYS_BASE},
+#elif IS_BCMCHIP(4912)
+    {UBUS_PORT_ID_BIU,       MST_PORT_NODE_B53_PHYS_BASE},
+    {UBUS_PORT_ID_PER,       MST_PORT_NODE_PER_PHYS_BASE},
+    {UBUS_PORT_ID_USB,       MST_PORT_NODE_USB_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE0,     MST_PORT_NODE_PCIE0_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE1,     MST_PORT_NODE_PCIE1_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE2,     MST_PORT_NODE_PCIE2_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE3,     MST_PORT_NODE_PCIE3_PHYS_BASE},
+    {UBUS_PORT_ID_DMA0,      MST_PORT_NODE_DMA0_PHYS_BASE},
+    {UBUS_PORT_ID_DMA1,      MST_PORT_NODE_DMA1_PHYS_BASE},
+    {UBUS_PORT_ID_DMA2,      MST_PORT_NODE_DMA2_PHYS_BASE},    
+    {UBUS_PORT_ID_RQ0,       MST_PORT_NODE_RQ0_PHYS_BASE},
+    {UBUS_PORT_ID_RQ1,       MST_PORT_NODE_RQ1_PHYS_BASE},    
+    {UBUS_PORT_ID_QM,        MST_PORT_NODE_QM_PHYS_BASE},
+    {UBUS_PORT_ID_SPU,       MST_PORT_NODE_SPU_PHYS_BASE},
+    {UBUS_PORT_ID_MPM,       MST_PORT_NODE_MPM_PHYS_BASE},
+#elif IS_BCMCHIP(6756)
+    {UBUS_PORT_ID_BIU,       MST_PORT_NODE_CPU_PHYS_BASE},
+    {UBUS_PORT_ID_PER,       MST_PORT_NODE_PER_PHYS_BASE},
+    {UBUS_PORT_ID_USB,       MST_PORT_NODE_USB_PHYS_BASE},
+    {UBUS_PORT_ID_PCIE0,     MST_PORT_NODE_PCIE0_PHYS_BASE},
+    {UBUS_PORT_ID_PMC,       MST_PORT_NODE_PMC_PHYS_BASE},
+    {UBUS_PORT_ID_SWH,       MST_PORT_NODE_SWH_PHYS_BASE},
+    {UBUS_PORT_ID_MPM,       MST_PORT_NODE_MPM_PHYS_BASE},
+    {UBUS_PORT_ID_WIFI,      MST_PORT_NODE_WIFI_PHYS_BASE},
+    {UBUS_PORT_ID_WIFI1,     MST_PORT_NODE_WIFI1_PHYS_BASE},
+    {UBUS_PORT_ID_SPU,       MST_PORT_NODE_SPU_PHYS_BASE},      
+#endif
+    {-1, 0}
+};
+
+#if !defined(_CFE_) && !defined(__UBOOT__)
+val_to_str_t ubus_port_id_to_str[] = {
+#if !IS_BCMCHIP(6878) && !IS_BCMCHIP(6855)
+    {UBUS_PORT_ID_MEMC, "MEMC"},
+#endif
+    {UBUS_PORT_ID_BIU, "BIU"},     
+    {UBUS_PORT_ID_USB, "USB"},    
+    {UBUS_PORT_ID_PER, "PER"},    
+    {UBUS_PORT_ID_PCIE0, "PCIE0"},  
+#if IS_BCMCHIP(63178)
+    {UBUS_PORT_ID_DSLCPU, "DSLCPU"},
+    {UBUS_PORT_ID_DSL, "DSL"},  
+    {UBUS_PORT_ID_WIFI, "WIFI"}, 
+    {UBUS_PORT_ID_PMC, "PMC"},    
+    {UBUS_PORT_ID_SWH, "SWH"},    
+    {UBUS_PORT_ID_SYS, "SYS"}, 
+#elif (IS_BCMCHIP(63146) || IS_BCMCHIP(4912))
+    {UBUS_PORT_ID_PCIE1, "PCIE1"},
+    {UBUS_PORT_ID_PCIE2, "PCIE2"},
+    {UBUS_PORT_ID_DMA0,  "DMA0"},
+    {UBUS_PORT_ID_DMA1,  "DMA1"},
+    {UBUS_PORT_ID_RQ0,   "RQ0"},
+    {UBUS_PORT_ID_QM,    "DM"},
+#if IS_BCMCHIP(63146)
+    {UBUS_PORT_ID_DSL, "DSL"},
+    {UBUS_PORT_ID_DSLCPU,"DSLCPU"},
+#endif 
+#if IS_BCMCHIP(4912)
+    {UBUS_PORT_ID_DMA2,  "DMA2"},    
+    {UBUS_PORT_ID_PCIE3, "PCIE3"},
+    {UBUS_PORT_ID_RQ1,   "RQ1"},
+    {UBUS_PORT_ID_MPM,   "MPM"},
+    {UBUS_PORT_ID_SPU,   "SPU"},    
+#endif
+#elif IS_BCMCHIP(47622)
+    {UBUS_PORT_ID_WIFI, "WIFI0"},
+    {UBUS_PORT_ID_WIFI1, "WIFI1"},
+    {UBUS_PORT_ID_PMC, "PMC"},    
+    {UBUS_PORT_ID_SYSPORT, "SYSPORT0"},
+    {UBUS_PORT_ID_SYSPORT1, "SYSPORT1"},
+    {UBUS_PORT_ID_SYS, "SYS"}, 
+    {UBUS_PORT_ID_SPU, "SPU"},
+#elif  IS_BCMCHIP(6756)
+    {UBUS_PORT_ID_WIFI, "WIFI0"},
+    {UBUS_PORT_ID_WIFI1, "WIFI1"},
+    {UBUS_PORT_ID_PMC, "PMC"},    
+    {UBUS_PORT_ID_SWH, "SWH"},
+    {UBUS_PORT_ID_MPM, "MPM"},
+    {UBUS_PORT_ID_SYS, "SYS"}, 
+    {UBUS_PORT_ID_SPU, "SPU"},    
+#else
+    {UBUS_PORT_ID_DMA0, "DMA0"},   
+#if !IS_BCMCHIP(6878) && !IS_BCMCHIP(6855)
+    {UBUS_PORT_ID_DQM, "DQM"},    
+    {UBUS_PORT_ID_NATC, "NATC"},   
+#endif
+    {UBUS_PORT_ID_QM, "QM"},     
+    {UBUS_PORT_ID_RQ0, "RQ0"},    
+#if IS_BCMCHIP(63158)
+    {UBUS_PORT_ID_DSLCPU, "DSLCPU"}, 
+    {UBUS_PORT_ID_DSL, "DSL"},
+    {UBUS_PORT_ID_FPM, "FPM"},    
+    {UBUS_PORT_ID_PCIE2, "PCIE2"},  
+    {UBUS_PORT_ID_PCIE3, "PCIE3"},  
+    {UBUS_PORT_ID_PERDMA, "PERDMA"}, 
+    {UBUS_PORT_ID_PMC, "PMC"},    
+    {UBUS_PORT_ID_PSRAM, "PSRAM"},  
+    {UBUS_PORT_ID_SPU, "SPU"},    
+    {UBUS_PORT_ID_SWH, "SWH"},    
+    {UBUS_PORT_ID_SYS, "SYS"},    
+    {UBUS_PORT_ID_SYSXRDP, "SYSXRDP"},
+    {UBUS_PORT_ID_VPB, "VPB"},    
+    {UBUS_PORT_ID_WAN, "WAN"},
+#elif IS_BCMCHIP(6858)
+    {UBUS_PORT_ID_PERDMA, "PERDMA"},   
+    {UBUS_PORT_ID_SPU, "SPU"},      
+    {UBUS_PORT_ID_PCIE2, "PCIE2"},    
+    {UBUS_PORT_ID_PMC, "PMC"},      
+    {UBUS_PORT_ID_DMA1, "DMA1"},     
+    {UBUS_PORT_ID_TOP_BUFF, "TOP_BUFF"}, 
+    {UBUS_PORT_ID_XRDP_BUFF, "XRDP_BUFF"},
+    {UBUS_PORT_ID_RQ1, "RQ1"},      
+    {UBUS_PORT_ID_RQ2, "RQ2"},      
+    {UBUS_PORT_ID_RQ3, "RQ3"},      
+#elif IS_BCMCHIP(6856)
+    {UBUS_PORT_ID_PCIE2, "PCIE2"},
+    {UBUS_PORT_ID_DMA1, "DMA1"}, 
+    {UBUS_PORT_ID_RQ1, "RQ1"},
+#elif IS_BCMCHIP(6855)
+    {UBUS_PORT_ID_WIFI, "WIFI"},
+    {UBUS_PORT_ID_DMA1, "DMA1"},
+    {UBUS_PORT_ID_DMA2, "DMA2"},
+    {UBUS_PORT_ID_RQ1, "RQ1"},
+#endif
+#endif
+};
+#endif
+
+void ubus_cong_threshold_wr(int port_id, unsigned int val)
+{
+    int i=0;
+
+    while (ub_mst_addr_map_tbl[i].port_id != -1)
+    {
+        if (ub_mst_addr_map_tbl[i].port_id == port_id)
+        {
+            ((MstPortNode*) ub_mst_addr_map_tbl[i].base )->port_cfg[DCM_UBUS_CONGESTION_THRESHOLD] = val;
+            break;
+        }
+        i++;
+    }
+}
+
+/*ubus4 credit table */
+#if IS_BCMCHIP(63158)
+static ubus_credit_cfg_t ubus_credit_tbl[UBUS_NUM_OF_MST_PORTS][UBUS_MAX_PORT_NUM+2] = {
+    /* only includes the non default credit value, default is 4 in 63158 */
+    /* The first credit data in each row inidicates the master port */
+    { {UBUS_PORT_ID_BIU, -1}, {UBUS_PORT_ID_MEMC, 3}, {UBUS_PORT_ID_SYS, 1}, {UBUS_PORT_ID_PSRAM, 8}, {UBUS_PORT_ID_SYSXRDP, 1}, {-1,-1} }, 
+    { {UBUS_PORT_ID_USB, -1}, {UBUS_PORT_ID_BIU, 2}, {UBUS_PORT_ID_SYS, 1}, {-1,-1} },                                                      
+    { {UBUS_PORT_ID_PCIE0, -1}, {UBUS_PORT_ID_BIU, 4}, {UBUS_PORT_ID_PCIE0, 1}, {UBUS_PORT_ID_PER, 1}, {UBUS_PORT_ID_SYS, 1},               
+        {UBUS_PORT_ID_FPM, 1}, {UBUS_PORT_ID_VPB, 1}, {UBUS_PORT_ID_SYSXRDP, 1}, {-1,-1} }, 
+    { {UBUS_PORT_ID_PCIE3, -1}, {UBUS_PORT_ID_BIU, 6}, {UBUS_PORT_ID_SYS, 1}, {UBUS_PORT_ID_FPM, 1}, {UBUS_PORT_ID_VPB, 1}, {-1,-1} },      
+    { {UBUS_PORT_ID_PCIE2, -1}, {UBUS_PORT_ID_BIU, 3}, {UBUS_PORT_ID_SYS, 1}, {UBUS_PORT_ID_FPM, 1}, {UBUS_PORT_ID_VPB, 1}, {-1,-1} },      
+    { {UBUS_PORT_ID_PMC, -1}, {UBUS_PORT_ID_BIU, 1}, {UBUS_PORT_ID_MEMC, 1}, {UBUS_PORT_ID_USB, 1}, {UBUS_PORT_ID_PCIE0, 1},                
+        {UBUS_PORT_ID_PCIE3, 1}, {UBUS_PORT_ID_PCIE2, 1}, {UBUS_PORT_ID_PER, 1}, {UBUS_PORT_ID_PMC, 1}, 
+        {UBUS_PORT_ID_WAN, 1}, {UBUS_PORT_ID_SYS, 1}, {UBUS_PORT_ID_SWH, 1}, {UBUS_PORT_ID_SPU, 1}, 
+        {UBUS_PORT_ID_DSL, 1}, {UBUS_PORT_ID_QM, 1}, {UBUS_PORT_ID_FPM, 1}, {UBUS_PORT_ID_VPB, 1}, 
+        {UBUS_PORT_ID_PSRAM, 1}, {UBUS_PORT_ID_SYSXRDP, 1}, {-1,-1} },
+    { {UBUS_PORT_ID_PER, -1}, {UBUS_PORT_ID_BIU, 1}, {UBUS_PORT_ID_SYS, 1}, {-1,-1} },                                                      
+    { {UBUS_PORT_ID_PERDMA, -1}, {UBUS_PORT_ID_BIU, 5}, {UBUS_PORT_ID_PER, 1}, {UBUS_PORT_ID_SYS, 1}, {UBUS_PORT_ID_DSL, 4},                
+        {UBUS_PORT_ID_PSRAM, 8}, {-1,-1} },
+    { {UBUS_PORT_ID_DSLCPU, -1}, {UBUS_PORT_ID_MEMC, 8}, {UBUS_PORT_ID_PER, 1}, {UBUS_PORT_ID_WAN, 1}, {UBUS_PORT_ID_SYS, 1},               
+        {UBUS_PORT_ID_DSL, 1}, {-1,-1} },
+    { {UBUS_PORT_ID_DSL, -1}, {UBUS_PORT_ID_BIU, 1}, {UBUS_PORT_ID_PER, 1}, {UBUS_PORT_ID_WAN, 1}, {UBUS_PORT_ID_SYS, 1},                   
+        {UBUS_PORT_ID_DSL, 1}, {-1,-1} },
+    { {UBUS_PORT_ID_SPU, -1}, {UBUS_PORT_ID_BIU, 5}, {UBUS_PORT_ID_PER, 1}, {UBUS_PORT_ID_SYS, 1}, {UBUS_PORT_ID_DSL, 4},                   
+        {UBUS_PORT_ID_PSRAM, 8}, {-1,-1} },
+    { {UBUS_PORT_ID_QM, -1}, {UBUS_PORT_ID_BIU, 16}, {UBUS_PORT_ID_SYSXRDP, 1}, {-1,-1} },                                               
+    { {UBUS_PORT_ID_DQM, -1}, {UBUS_PORT_ID_BIU, 1}, {UBUS_PORT_ID_FPM, 2}, {UBUS_PORT_ID_SYSXRDP, 1}, {-1,-1} },           
+    { {UBUS_PORT_ID_NATC, -1}, {UBUS_PORT_ID_BIU, 2}, {UBUS_PORT_ID_SYSXRDP, 1}, {-1,-1} },                                                 
+    { {UBUS_PORT_ID_DMA0, -1}, {UBUS_PORT_ID_BIU, 8}, {UBUS_PORT_ID_SYSXRDP, 1}, {-1,-1} },                                                 
+    { {UBUS_PORT_ID_RQ0, -1}, {UBUS_PORT_ID_BIU, 11}, {UBUS_PORT_ID_USB, 1}, {UBUS_PORT_ID_PCIE0, 2}, {UBUS_PORT_ID_PCIE3, 2},               
+        {UBUS_PORT_ID_PCIE2, 2}, {UBUS_PORT_ID_PER, 1}, {UBUS_PORT_ID_WAN, 1}, {UBUS_PORT_ID_SWH, 1}, 
+        {UBUS_PORT_ID_SPU, 1}, {UBUS_PORT_ID_QM, 10}, {UBUS_PORT_ID_FPM, 2}, {UBUS_PORT_ID_VPB, 2}, 
+        {UBUS_PORT_ID_PSRAM, 10}, {UBUS_PORT_ID_SYSXRDP, 1}, {-1,-1} },
+    { {UBUS_PORT_ID_SWH, -1}, {UBUS_PORT_ID_BIU, 8}, {UBUS_PORT_ID_SYS, 1}, {UBUS_PORT_ID_DSL, 8}, {UBUS_PORT_ID_PSRAM, 8}, {-1,-1} },      
+};
+#elif IS_BCMCHIP(6858)
+static ubus_credit_cfg_t ubus_credit_tbl[UBUS_NUM_OF_MST_PORTS][UBUS_MAX_PORT_NUM+2] = {
+    { {UBUS_PORT_ID_BIU, -1}, {-1,-1} },
+    { {UBUS_PORT_ID_PER, -1}, {UBUS_PORT_ID_MEMC, 1}, {-1,-1} },
+    { {UBUS_PORT_ID_USB, -1}, {UBUS_PORT_ID_MEMC, 4}, {-1,-1} },
+    { {UBUS_PORT_ID_PERDMA, -1}, {UBUS_PORT_ID_BIU, 0} },
+    { {UBUS_PORT_ID_SPU, -1}, {-1,-1} },
+    { {UBUS_PORT_ID_PCIE0, -1}, {UBUS_PORT_ID_RQ0, 1}, {UBUS_PORT_ID_RQ1, 1}, {UBUS_PORT_ID_RQ2, 1}, {UBUS_PORT_ID_RQ3, 1}, {-1,-1} },
+    { {UBUS_PORT_ID_PCIE2, -1}, {UBUS_PORT_ID_RQ0, 1}, {UBUS_PORT_ID_RQ1, 1}, {UBUS_PORT_ID_RQ2, 1}, {UBUS_PORT_ID_RQ3, 1}, {-1,-1} },
+    { {UBUS_PORT_ID_PMC, -1}, {UBUS_PORT_ID_MEMC, 1}, {UBUS_PORT_ID_RQ0, 1}, {UBUS_PORT_ID_RQ1, 1}, {UBUS_PORT_ID_RQ2, 1}, {UBUS_PORT_ID_RQ3, 1}, {-1,-1} },
+    { {UBUS_PORT_ID_QM, -1}, {UBUS_PORT_ID_MEMC, 10}, {-1,-1} },
+    { {UBUS_PORT_ID_DQM, -1}, {UBUS_PORT_ID_MEMC, 7}, {-1,-1} },
+    { {UBUS_PORT_ID_DMA0, -1}, {UBUS_PORT_ID_MEMC, 9}, {-1,-1} },
+    { {UBUS_PORT_ID_DMA1, -1}, {UBUS_PORT_ID_MEMC, 9}, {-1,-1} },
+    { {UBUS_PORT_ID_NATC, -1}, {UBUS_PORT_ID_BIU, 10}, {-1,-1} },
+    { {UBUS_PORT_ID_TOP_BUFF, -1}, {-1,-1} },
+    { {UBUS_PORT_ID_XRDP_BUFF, -1}, {-1,-1} },
+    { {UBUS_PORT_ID_RQ0, -1}, {UBUS_PORT_ID_MEMC, 8}, {UBUS_PORT_ID_XRDP_VPB, 1}, {UBUS_PORT_ID_RQ0, 1}, {-1,-1} },
+    { {UBUS_PORT_ID_RQ1, -1}, {UBUS_PORT_ID_MEMC, 4}, {UBUS_PORT_ID_XRDP_VPB, 1}, {UBUS_PORT_ID_RQ1, 1}, {-1,-1} },
+    { {UBUS_PORT_ID_RQ2, -1}, {UBUS_PORT_ID_MEMC, 4}, {UBUS_PORT_ID_XRDP_VPB, 1}, {UBUS_PORT_ID_RQ2, 1}, {-1,-1} },
+    { {UBUS_PORT_ID_RQ3, -1}, {UBUS_PORT_ID_MEMC, 4}, {UBUS_PORT_ID_XRDP_VPB, 1}, {UBUS_PORT_ID_RQ3, 1}, {-1,-1} },
+};
+#endif
+
+MstPortNode* bcm_get_ubus_mst_addr(int master_port_id)
+{
+    MstPortNode *master_addr = NULL;
+    int i=0;
+
+    while(ub_mst_addr_map_tbl[i].port_id != -1)
+    {
+        if (ub_mst_addr_map_tbl[i].port_id == master_port_id)
+        {
+            master_addr = (MstPortNode*)ub_mst_addr_map_tbl[i].base;
+            break;
+        }
+        i++;
+    }
+
+    return master_addr;
+}
+
+// XXX  Dima To check
+int log2_32 (unsigned int value)
+{
+    unsigned int result = 0;
+    if( value < 1)
+        return 0;
+
+    while (value > 1) {
+        ++result;
+        value >>= 1;
+    }
+
+    return result;
+}
+#if !defined(_CFE_) && !defined(__UBOOT__)
+EXPORT_SYMBOL(log2_32);
+
+static int ubus_master_decode_wnd_cfg(int master_port_id, int win, unsigned int phys_addr, unsigned int size_power_of_2, int port_id, unsigned int cache_bit_en)
+{
+    MstPortNode *master_addr = NULL; 
+    int ret = 0;
+
+#if IS_BCMCHIP(6858)
+    if ((master_port_id==UBUS_PORT_ID_TOP_BUFF) || (master_port_id==UBUS_PORT_ID_XRDP_BUFF))
+        return 0;
+#endif
+
+    UBUS_REMAP_DEBUG_LOG("\x1b[35m port[%d] win[%d] phys_addr[0x%x] power_of_2[%d] port_id[%d] cache_bit[%d]\x1b[0m\n", 
+        master_port_id, win, phys_addr, size_power_of_2, port_id,cache_bit_en);
+
+
+    if((win > 3) || (size_power_of_2 > 31))
+    {
+        printk("\x1b[35m Paramets Error:  win[%d] phys_addr[0x%x] power_of_2[%d] port_id[%d] cache_bit[%d]\x1b[0m\n", 
+            win, phys_addr, size_power_of_2, port_id, cache_bit_en);
+        return -1;
+    }
+
+    master_addr = bcm_get_ubus_mst_addr(master_port_id);
+    if(master_addr)
+    {
+#if IS_BCMCHIP(63158) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(63146) || IS_BCMCHIP(4912) || IS_BCMCHIP(6756)
+        /* 63158 has the all the master connected to the CCI as default so no need to
+           configure the map. Just turn on the cache configuration */
+        if( cache_bit_en )
+        {
+            master_addr->decode_cfg.cache_cfg = 0x1;
+            master_addr->decode_cfg.ctrl &= ~DECODE_CFG_CTRL_CACHE_SEL_MASK;
+            master_addr->decode_cfg.ctrl |= DECODE_CFG_CTRL_CACHE_SEL_CFG_REG;  
+        }
+        else
+        {
+            master_addr->decode_cfg.cache_cfg = 0x0;
+            master_addr->decode_cfg.ctrl &= ~DECODE_CFG_CTRL_CACHE_SEL_MASK;
+            master_addr->decode_cfg.ctrl |= DECODE_CFG_CTRL_CACHE_SEL_DEF;  
+        }
+
+#else
+        if(size_power_of_2)
+        {
+            master_addr->decode_cfg.window[win].base_addr =  (phys_addr>>8);
+            master_addr->decode_cfg.window[win].remap_addr = (phys_addr>>8);
+
+            if( (port_id == UBUS_PORT_ID_BIU) && (cache_bit_en))
+            {
+                master_addr->decode_cfg.window[win].attributes = 
+                    (DECODE_CFG_CACHE_BITS | DECODE_CFG_ENABLE_ADDR_ONLY | (size_power_of_2 << DECODE_CFG_SIZE_SHIFT) | port_id) ;
+                UBUS_REMAP_DEBUG_LOG("\x1b[35m base_addr[0x%x] remap_addr[0x%x] attributes[0x%x]\x1b[0m\n", 
+                    master_addr->decode_cfg.window[win].base_addr, 
+                    master_addr->decode_cfg.window[win].remap_addr,
+                    master_addr->decode_cfg.window[win].attributes);
+            }
+            else
+            {
+                master_addr->decode_cfg.window[win].attributes = 
+                    (DECODE_CFG_ENABLE_ADDR_ONLY | (size_power_of_2 << DECODE_CFG_SIZE_SHIFT) | port_id) ;
+
+                UBUS_REMAP_DEBUG_LOG("\x1b[35m base_addr[0x%x] remap_addr[0x%x] attributes[0x%x]\x1b[0m\n",
+                    master_addr->decode_cfg.window[win].base_addr, 
+                    master_addr->decode_cfg.window[win].remap_addr,
+                    master_addr->decode_cfg.window[win].attributes); 
+            }
+        }
+        else
+        {
+            master_addr->decode_cfg.window[win].base_addr = 0;
+            master_addr->decode_cfg.window[win].remap_addr = 0;
+            master_addr->decode_cfg.window[win].attributes = 0;
+        }
+#endif
+    }
+
+    return ret;
+}
+
+int ubus_decode_pcie_wnd_cfg(unsigned int base, unsigned int size, unsigned int core)
+{
+    /* Not implemented */
+    return -1;
+}
+EXPORT_SYMBOL(ubus_decode_pcie_wnd_cfg);
+#endif
+
+#define SIZE_OF_REG_BYTES     (4)
+#if defined(CONFIG_BCM_UBUS_DECODE_REMAP)
+
+#if IS_BCMCHIP(63158) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(63146) || IS_BCMCHIP(4912) || IS_BCMCHIP(6756)
+int ubus_remap_to_biu_cfg_wlu_srcpid(int srcpid, int enable)
+{
+    volatile CoherencyPortCfgReg_t* cpcfg_reg = (volatile CoherencyPortCfgReg_t * const)UBUS_COHERENCY_PORT_CFG_BASE;
+    int i = 0, reg, bit;
+
+    if( srcpid > MAX_WLU_SRCPID_NUM )
+        return -1;
+
+    if( srcpid == MAX_WLU_SRCPID_NUM ) {
+        for( i = 0; i < MAX_WLU_SRCPID_REG_NUM; i++ )
+            cpcfg_reg->wlu_srcpid[i] = enable ? 0xffffffff : 0;
+    } else {
+        reg = WLU_SRCPID_TO_REG_OFFSET(srcpid);
+        bit = WLU_SRCPID_TO_REG_BIT(srcpid);
+        if( enable ) 
+            cpcfg_reg->wlu_srcpid[reg] |= (0x1<<bit);
+        else 
+            cpcfg_reg->wlu_srcpid[reg] &= ~(0x1<<bit);
+    }
+
+    return 0;
+}
+#endif
+
+#if !IS_BCMCHIP(63158) && !IS_BCMCHIP(63178) && !IS_BCMCHIP(47622) && !IS_BCMCHIP(63146) && !IS_BCMCHIP(4912) && !IS_BCMCHIP(6756)
+static int ubus_remap_to_biu_cfg_queue_srcpid(unsigned long lut_idx, unsigned int *p_srcpid_queus_value)
+{
+    CoherencyPortCfgReg_t *reg_addr = 
+        (CoherencyPortCfgReg_t*)(UBUS_COHERENCY_PORT_CFG_LUT_BASE + lut_idx * SIZE_OF_REG_BYTES); 
+
+    if((lut_idx > 31) || (NULL == p_srcpid_queus_value))
+        return -1;
+
+    reg_addr->queue_cfg = (((p_srcpid_queus_value[0] & 0xf) << SRCPID_TO_QUEUE_0_BITS_SHIFT) |
+        ((p_srcpid_queus_value[1] & 0xf) << SRCPID_TO_QUEUE_1_BITS_SHIFT) |
+        ((p_srcpid_queus_value[2] & 0xf) << SRCPID_TO_QUEUE_2_BITS_SHIFT) |
+        ((p_srcpid_queus_value[3] & 0xf) << SRCPID_TO_QUEUE_3_BITS_SHIFT) |
+        ((p_srcpid_queus_value[4] & 0xf) << SRCPID_TO_QUEUE_4_BITS_SHIFT) |
+        ((p_srcpid_queus_value[5] & 0xf) << SRCPID_TO_QUEUE_5_BITS_SHIFT) |
+        ((p_srcpid_queus_value[6] & 0xf) << SRCPID_TO_QUEUE_6_BITS_SHIFT) |
+        ((p_srcpid_queus_value[7] & 0xf) << SRCPID_TO_QUEUE_7_BITS_SHIFT));
+
+    UBUS_REMAP_DEBUG_LOG("\x1b[35m reg_addr[0x%px] reg_value[0x%x]\x1b[0m\n",
+        (unsigned int*)(reg_addr), reg_addr->queue_cfg); 
+
+    return 0;                        
+}
+
+static int ubus_remap_to_biu_cfg_queue_depth(unsigned long q_depth_idx, unsigned int *p_depth_queus_value)
+{
+    CoherencyPortCfgReg_t *reg_addr = 
+        (CoherencyPortCfgReg_t*)(UBUS_COHERENCY_PORT_CFG_DEPTH_BASE + q_depth_idx * SIZE_OF_REG_BYTES); 
+
+    if((q_depth_idx > 3) || (NULL == p_depth_queus_value))
+        return -1;
+
+    reg_addr->queue_cfg = (((p_depth_queus_value[0] & 0xff) << DEPTH_TO_QUEUE_0_BITS_SHIFT) |
+        ((p_depth_queus_value[1] & 0xff) << DEPTH_TO_QUEUE_1_BITS_SHIFT) |
+        ((p_depth_queus_value[2] & 0xff) << DEPTH_TO_QUEUE_2_BITS_SHIFT) |
+        ((p_depth_queus_value[3] & 0xff) << DEPTH_TO_QUEUE_3_BITS_SHIFT));
+
+    UBUS_REMAP_DEBUG_LOG("\x1b[35m reg_addr[0x%px] reg_value[0x%x]\x1b[0m\n",
+        (unsigned int*)(reg_addr), reg_addr->queue_cfg); 
+
+    return 0;                        
+}
+
+static int ubus_remap_to_biu_cfg_queue_thresh(unsigned long q_thresh_idx, unsigned int *p_thresh_queus_value)
+{
+    CoherencyPortCfgReg_t *reg_addr = 
+        (CoherencyPortCfgReg_t*)(UBUS_COHERENCY_PORT_CFG_CBS_BASE + q_thresh_idx * SIZE_OF_REG_BYTES); 
+
+    if((q_thresh_idx > 8) || (NULL == p_thresh_queus_value))
+        return -1;
+
+    reg_addr->queue_cfg = (((p_thresh_queus_value[0] & 0xffff) << THRESH_TO_QUEUE_0_BITS_SHIFT) |
+        ((p_thresh_queus_value [1] & 0xffff) << THRESH_TO_QUEUE_1_BITS_SHIFT));
+
+    UBUS_REMAP_DEBUG_LOG("\x1b[35m reg_addr[0x%px] reg_value[0x%x]\x1b[0m\n",
+        (unsigned int*)(reg_addr), reg_addr->queue_cfg); 
+
+    return 0;                        
+}
+
+static int ubus_remap_to_biu_cfg_cir_incr(unsigned long q_cirinc_idx, unsigned int *p_cirinc_queus_value)
+{
+    CoherencyPortCfgReg_t *reg_addr =
+        (CoherencyPortCfgReg_t*)(UBUS_COHERENCY_PORT_CFG_CIR_INCR_BASE + q_cirinc_idx * SIZE_OF_REG_BYTES); 
+
+    if((q_cirinc_idx > 3) || (NULL == p_cirinc_queus_value))
+        return -1;
+
+    reg_addr->queue_cfg = (((p_cirinc_queus_value[0] & 0xff) << CIR_INCR_TO_QUEUE_0_BITS_SHIFT) |
+        ((p_cirinc_queus_value [1] & 0xff) << CIR_INCR_TO_QUEUE_1_BITS_SHIFT) |
+        ((p_cirinc_queus_value [2] & 0xff) << CIR_INCR_TO_QUEUE_2_BITS_SHIFT) |
+        ((p_cirinc_queus_value [3] & 0xff) << CIR_INCR_TO_QUEUE_3_BITS_SHIFT));
+
+    UBUS_REMAP_DEBUG_LOG("\x1b[35m reg_addr[0x%px] reg_value[0x%x]\x1b[0m\n",
+        (unsigned int*)(reg_addr), reg_addr->queue_cfg); 
+
+    return 0;                        
+}
+
+static int ubus_remap_to_biu_cfg_ref_cnt(unsigned long q_ref_cnt_idx, unsigned int *p_ref_cnt_value)
+{
+    CoherencyPortCfgReg_t *reg_addr = 
+        (CoherencyPortCfgReg_t*)(UBUS_COHERENCY_PORT_CFG_REF_COUNT_BASE + q_ref_cnt_idx * SIZE_OF_REG_BYTES); 
+
+    if((q_ref_cnt_idx > 1) || (NULL == p_ref_cnt_value))
+        return -1;
+
+    reg_addr->queue_cfg = (((p_ref_cnt_value[0] & 0xf) << REF_CNT_0_BITS_SHIFT) |
+        ((p_ref_cnt_value[1] & 0xf) << REF_CNT_1_BITS_SHIFT) |
+        ((p_ref_cnt_value[2] & 0xf) << REF_CNT_2_BITS_SHIFT) |
+        ((p_ref_cnt_value[3] & 0xf) << REF_CNT_3_BITS_SHIFT) |
+        ((p_ref_cnt_value[4] & 0xf) << REF_CNT_4_BITS_SHIFT) |
+        ((p_ref_cnt_value[5] & 0xf) << REF_CNT_5_BITS_SHIFT) |
+        ((p_ref_cnt_value[6] & 0xf) << REF_CNT_6_BITS_SHIFT) |
+        ((p_ref_cnt_value[7] & 0xf) << REF_CNT_7_BITS_SHIFT));
+
+    UBUS_REMAP_DEBUG_LOG("\x1b[35m  reg_addr[0x%px] reg_value[0x%x]\x1b[0m\n",
+        (unsigned int*)(reg_addr), reg_addr->queue_cfg); 
+
+    return 0;                        
+}
+
+
+#define  SRC_PID_Q_NUM      (8)
+#define  DEPTH_Q_NUM        (4)
+#define  THRESH_Q_NUM       (2)
+#define  CIR_INCR_Q_NUM     (4)
+#define  REF_CNT_NUM        (8)
+static int configure_biu_pid_to_queue(void)
+{
+    int rc = 0;
+    unsigned int srcpid_queus_value[SRC_PID_Q_NUM] = {0};
+    unsigned int depth_queus_value[DEPTH_Q_NUM] = {0};
+    unsigned int thresh_queus_value[THRESH_Q_NUM] = {0};
+    unsigned int cir_incr_queus_value[CIR_INCR_Q_NUM] = {0};
+    unsigned int ref_cnt_value[REF_CNT_NUM] = {0};
+    unsigned long lut_idx;
+    unsigned long depth_idx;
+    unsigned long thresh_idx;
+    unsigned long cir_incr_idx;
+    unsigned long ref_cnt_idx;
+
+    lut_idx = 0;
+    srcpid_queus_value[0] = 0;
+    srcpid_queus_value[1] = 0;
+    srcpid_queus_value[2] = 0;
+    srcpid_queus_value[3] = 0;
+    srcpid_queus_value[4] = 1;
+    srcpid_queus_value[5] = 1;
+    srcpid_queus_value[6] = 1;
+    srcpid_queus_value[7] = 1;
+    rc = ubus_remap_to_biu_cfg_queue_srcpid(lut_idx, srcpid_queus_value);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d]\n",__FILE__, __LINE__);
+        goto exit_;
+    }
+
+    lut_idx = 1;
+    srcpid_queus_value[0] = 0;
+    srcpid_queus_value[1] = 0;
+    srcpid_queus_value[2] = 0;
+    srcpid_queus_value[3] = 2;
+    srcpid_queus_value[4] = 3;
+    srcpid_queus_value[5] = 4;
+    srcpid_queus_value[6] = 3;
+    srcpid_queus_value[7] = 5;
+    rc = ubus_remap_to_biu_cfg_queue_srcpid(lut_idx, srcpid_queus_value);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d]\n",__FILE__, __LINE__);
+        goto exit_;
+    }
+
+    depth_idx = 0;
+    depth_queus_value[0] = 0x10;
+    depth_queus_value[1] = 0x10;
+    depth_queus_value[2] = 8;
+    depth_queus_value[3] = 8;
+    rc = ubus_remap_to_biu_cfg_queue_depth(depth_idx, depth_queus_value);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d]\n",__FILE__, __LINE__);
+        goto exit_;
+    }
+
+    depth_idx = 1;
+    depth_queus_value[0] = 8;
+    depth_queus_value[1] = 8;
+    depth_queus_value[2] = 0;
+    depth_queus_value[3] = 0;
+    rc = ubus_remap_to_biu_cfg_queue_depth(depth_idx, depth_queus_value);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d]\n",__FILE__, __LINE__);
+        goto exit_;
+    }
+
+    thresh_idx = 0;
+    thresh_queus_value[0] = 0x100;
+    thresh_queus_value[1] = 0x100;
+    rc = ubus_remap_to_biu_cfg_queue_thresh(thresh_idx, thresh_queus_value);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d]\n",__FILE__, __LINE__);
+        goto exit_;
+    }
+
+    thresh_idx = 1;
+    thresh_queus_value[0] = 0x1000;
+    thresh_queus_value[1] = 0x400;
+    rc = ubus_remap_to_biu_cfg_queue_thresh(thresh_idx, thresh_queus_value);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d]\n",__FILE__, __LINE__);
+        goto exit_;
+    }
+
+    thresh_idx = 2;
+    thresh_queus_value[0] = 0x400;
+    thresh_queus_value[1] = 0x1000;
+    rc = ubus_remap_to_biu_cfg_queue_thresh(thresh_idx, thresh_queus_value);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d]\n",__FILE__, __LINE__);
+        goto exit_;
+    }
+
+    cir_incr_idx = 0;
+    cir_incr_queus_value[0] = 1;
+    cir_incr_queus_value[1] = 1;
+    cir_incr_queus_value[2] = 4;
+    cir_incr_queus_value[3] = 4;
+    rc = ubus_remap_to_biu_cfg_cir_incr(cir_incr_idx, cir_incr_queus_value);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d]\n",__FILE__, __LINE__);
+        goto exit_;
+    }
+
+    cir_incr_idx = 1;
+    cir_incr_queus_value[0] = 2;
+    cir_incr_queus_value[1] = 3;
+    cir_incr_queus_value[2] = 0;
+    cir_incr_queus_value[3] = 0;
+    rc = ubus_remap_to_biu_cfg_cir_incr(cir_incr_idx, cir_incr_queus_value);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d]\n",__FILE__, __LINE__);
+        goto exit_;
+    }
+
+    ref_cnt_idx = 0;
+    ref_cnt_value[0] = 7;
+    ref_cnt_value[1] = 4;
+    ref_cnt_value[2] = 2;
+    ref_cnt_value[3] = 2;
+    ref_cnt_value[4] = 3;
+    ref_cnt_value[5] = 2;
+    ref_cnt_value[6] = 0;
+    ref_cnt_value[7] = 0;
+    rc = ubus_remap_to_biu_cfg_ref_cnt(ref_cnt_idx, ref_cnt_value);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d]\n",__FILE__, __LINE__);
+        goto exit_;
+    }
+
+exit_:
+    if (rc < 0)
+        printk("Error: line[%d]\n",__LINE__);
+
+    return rc;                       
+}
+#elif IS_BCMCHIP(63158)
+
+/* Helper MACROS */
+#define SIZE_OF_REG_BITS (SIZE_OF_REG_BYTES*8)
+
+#define CLEAR_BITS(r, p, m) (r) = ((r) & ~((m) << (p)))
+#define SET_BITS(r, p, v) (r) = ((r) | ((v) << (p)))
+
+#define BITS_MASK(bits)       ( (1<<(bits)) - 1 )
+#define BITS_POS(fld_num, bits) ( ((fld_num)*(bits)) % SIZE_OF_REG_BITS ) 
+
+#define FIELD_INDEX(fld_num, bits)      ( (fld_num) / (SIZE_OF_REG_BITS/(bits)) )
+
+#define SRCPID_2_LUT_IDX(src_pid)       ( FIELD_INDEX(src_pid, QUE_ID_NUM_BITS) )
+#define QUEUE_2_DEPTH_IDX(que_id)       ( FIELD_INDEX(que_id, DEPTH_NUM_BITS) )
+#define QUEUE_2_CBS_IDX(que_id)         ( FIELD_INDEX(que_id, CBS_NUM_BITS) )
+#define QUEUE_2_CIR_INCR_IDX(que_id)    ( FIELD_INDEX(que_id, CIR_INCR_NUM_BITS) )
+#define QUEUE_2_REF_CNT_IDX(que_id)     ( FIELD_INDEX(que_id, REF_CNT_NUM_BITS) )
+#define QUEUE_2_MAX_BONUS_IDX(que_id)   ( FIELD_INDEX(que_id, MAX_BONUS_NUM_BITS) )
+
+/* DDR Rate/Width mapping to array index */
+typedef enum {
+    eDDR_RATE_WIDTH_2133_32,
+    eDDR_RATE_WIDTH_2133_16,
+    eDDR_RATE_WIDTH_1600_32,
+    eDDR_RATE_WIDTH_1600_16,
+    eDDR_RATE_WIDTH_MAX,
+}eDDR_RATE_WIDTH;
+
+/* Local structure to store configured values */
+typedef struct {
+    char blk_name[8];
+    uint32_t mstr_node;
+    uint32_t src_pid;
+    uint32_t que_id;
+    uint32_t depth;
+    uint32_t ref_cnt[eDDR_RATE_WIDTH_MAX];
+    uint32_t cir;
+    uint32_t cbs;
+    uint32_t bonus;
+}biu_cfg_t;
+
+eDDR_RATE_WIDTH g_ddr_rate_width_idx = eDDR_RATE_WIDTH_2133_32; /* Gets initialized to the correct index based on rate/width */
+
+#define BIU_CFG_MAX_SRC_PID     (UBUS_MAX_PORT_NUM+1)
+
+static biu_cfg_t biu_cfg_port_array[BIU_CFG_MAX_SRC_PID] = {
+    /* queue depth will be set based on ubus credits */
+    [UBUS_PORT_ID_PER]      = { .blk_name = "PCM",    .src_pid = 3,  .que_id = 7,  .cir = 2,  .cbs = 128, .bonus = 0, .ref_cnt = {12, 18, 22, 40 }, .mstr_node = UBUS_PORT_ID_PER},
+    [UBUS_PORT_ID_USB]      = { .blk_name = "USB",    .src_pid = 4,  .que_id = 6,  .cir = 3,  .cbs = 128, .bonus = 0, .ref_cnt = {38, 71, 90, 161}, .mstr_node = UBUS_PORT_ID_USB},
+    [UBUS_PORT_ID_SPU]      = { .blk_name = "SPU",    .src_pid = 5,  .que_id = 9,  .cir = 1,  .cbs = 1,   .bonus = 0, .ref_cnt = {38, 71, 90, 161}, .mstr_node = UBUS_PORT_ID_SPU},
+    [UBUS_PORT_ID_PERDMA]   = { .blk_name = "M2M",    .src_pid = 7,  .que_id = 8,  .cir = 1,  .cbs = 1,   .bonus = 0, .ref_cnt = {38, 71, 90, 161}, .mstr_node = UBUS_PORT_ID_PERDMA},
+    [UBUS_PORT_ID_PCIE0]    = { .blk_name = "PCIe0",  .src_pid = 8,  .que_id = 3,  .cir = 6,  .cbs = 128, .bonus = 0, .ref_cnt = {38, 71, 90, 161}, .mstr_node = UBUS_PORT_ID_PCIE0},
+    [UBUS_PORT_ID_PCIE2]    = { .blk_name = "PCIe2",  .src_pid = 9,  .que_id = 4,  .cir = 3,  .cbs = 128, .bonus = 0, .ref_cnt = {38, 71, 90, 161}, .mstr_node = UBUS_PORT_ID_PCIE2},
+    [UBUS_PORT_ID_PCIE3]    = { .blk_name = "PCIe3",  .src_pid = 10, .que_id = 5,  .cir = 9,  .cbs = 256, .bonus = 0, .ref_cnt = {38, 71, 90, 161}, .mstr_node = UBUS_PORT_ID_PCIE3},
+    [UBUS_PORT_ID_QM]       = { .blk_name = "QM",     .src_pid = 22, .que_id = 10, .cir = 38, .cbs = 512, .bonus = 4, .ref_cnt = {38, 71, 90, 161}, .mstr_node = UBUS_PORT_ID_QM},
+    [UBUS_PORT_ID_DQM]      = { .blk_name = "QM_DQM", .src_pid = 23, .que_id = 1,  .cir = 5,  .cbs = 256, .bonus = 4, .ref_cnt = {6,  9,  11, 20 }, .mstr_node = UBUS_PORT_ID_DQM},
+    [UBUS_PORT_ID_DMA0]     = { .blk_name = "DMA0",   .src_pid = 24, .que_id = 11, .cir = 39, .cbs = 128, .bonus = 4, .ref_cnt = {38, 71, 90, 161}, .mstr_node = UBUS_PORT_ID_DMA0},
+    [UBUS_PORT_ID_NATC]     = { .blk_name = "NAT$",   .src_pid = 26, .que_id = 2,  .cir = 6,  .cbs = 512, .bonus = 4, .ref_cnt = {21, 36, 45, 81 }, .mstr_node = UBUS_PORT_ID_NATC},
+    [UBUS_PORT_ID_RQ0]      = { .blk_name = "RNR",    .src_pid = 32, .que_id = 0,  .cir = 14, .cbs = 256, .bonus = 4, .ref_cnt = {12, 18, 22, 40 }, .mstr_node = UBUS_PORT_ID_RQ0},
+};
+/* Function to dump configuration per source port */
+void dump_biu_cfg_array(biu_cfg_t *p)
+{
+    uint32_t idx;
+    uint32_t depth_total = 0;
+    printk("\n");
+    printk("PID     BLOCK     QUE  DEPTH  REFRESH  CIR_INCR  CBS  BONUS MSTR_NODE\n");
+    for (idx=0; idx < BIU_CFG_MAX_SRC_PID; idx++) {
+        if (p->src_pid) {
+            printk("[%2u] %8s : %4u %5u %7u %8u %8u %4u %6u\n",p->src_pid, p->blk_name, p->que_id, p->depth, p->ref_cnt[0], p->cir, p->cbs, p->bonus, p->mstr_node);
+            depth_total += p->depth;
+        }
+        p++;
+    }
+    printk("TOTAL Depth = Credits = %u\n",depth_total);
+    printk("\n");
+}
+/* Helper function to extract the value based on field index and bits */
+static uint32_t extract_field_value(uint32_t val, uint32_t fld_num, uint32_t bits)
+{
+    uint32_t mask, pos;
+    mask = BITS_MASK(bits);
+    pos = BITS_POS(fld_num, bits);
+    val = (val & (mask << pos));
+    val = val >> pos;
+    return val;
+}
+/* Helper functions to read configured queue id value for a given source port */
+static uint32_t biu_read_queue(uint32_t src_pid)
+{
+    volatile CoherencyPortCfgReg_t* reg_addr = (volatile CoherencyPortCfgReg_t * const)UBUS_COHERENCY_PORT_CFG_BASE;
+    uint32_t idx;
+
+    idx = SRCPID_2_LUT_IDX(src_pid);
+    return extract_field_value(reg_addr->lut[idx], src_pid, QUE_ID_NUM_BITS);
+}
+/* Helper functions to read configured queue depth value for a given queue id */
+static uint32_t biu_read_queue_depth(uint32_t queue_id)
+{
+    volatile CoherencyPortCfgReg_t* reg_addr = (volatile CoherencyPortCfgReg_t * const)UBUS_COHERENCY_PORT_CFG_BASE;
+    uint32_t idx;
+
+    idx = QUEUE_2_DEPTH_IDX(queue_id);
+    return extract_field_value(reg_addr->queue_depth[idx], queue_id, DEPTH_NUM_BITS);
+}
+/* Helper functions to read configured queue cbs value for a given queue id */
+static uint32_t biu_read_queue_cbs(uint32_t queue_id)
+{
+    volatile CoherencyPortCfgReg_t* reg_addr = (volatile CoherencyPortCfgReg_t * const)UBUS_COHERENCY_PORT_CFG_BASE;
+    uint32_t idx;
+
+    idx = QUEUE_2_CBS_IDX(queue_id);
+    return extract_field_value(reg_addr->cbs_thresh[idx], queue_id, CBS_NUM_BITS);
+}
+/* Helper functions to read configured queue cir_incr value for a given queue id */
+static uint32_t biu_read_queue_cir_incr(uint32_t queue_id)
+{
+    volatile CoherencyPortCfgReg_t* reg_addr = (volatile CoherencyPortCfgReg_t * const)UBUS_COHERENCY_PORT_CFG_BASE;
+    uint32_t idx;
+
+    idx = QUEUE_2_CIR_INCR_IDX(queue_id);
+    return extract_field_value(reg_addr->cir_incr[idx], queue_id, CIR_INCR_NUM_BITS);
+}
+/* Helper functions to read configured queue refresh count value for a given queue id */
+static uint32_t biu_read_queue_ref_cnt(uint32_t queue_id)
+{
+    volatile CoherencyPortCfgReg_t* reg_addr = (volatile CoherencyPortCfgReg_t * const)UBUS_COHERENCY_PORT_CFG_BASE;
+    uint32_t idx;
+
+    idx = QUEUE_2_REF_CNT_IDX(queue_id);
+    return extract_field_value(reg_addr->ref_cnt[idx], queue_id, REF_CNT_NUM_BITS);
+}
+/* Helper functions to read configured queue max bonus value for a given queue id */
+static uint32_t biu_read_queue_max_bonus(uint32_t queue_id)
+{
+    volatile CoherencyPortCfgReg_t* reg_addr = (volatile CoherencyPortCfgReg_t * const)UBUS_COHERENCY_PORT_CFG_BASE;
+    uint32_t idx;
+
+    idx = QUEUE_2_MAX_BONUS_IDX(queue_id);
+    return extract_field_value(reg_addr->max_bonus[idx], queue_id, MAX_BONUS_NUM_BITS);
+}
+/* Helper functions to read & dump configuration for all source ports of interest */
+void dump_biu_cfg(void)
+{
+    biu_cfg_t cfg_array[BIU_CFG_MAX_SRC_PID] = {}; 
+    biu_cfg_t *p;
+    uint32_t src_pid;
+    uint32_t que_id;
+
+    for (src_pid = 0; src_pid < BIU_CFG_MAX_SRC_PID; src_pid++) {
+        if (biu_cfg_port_array[src_pid].src_pid) {
+            p = &cfg_array[src_pid];
+            /* Assign static values */
+            memcpy(p->blk_name, biu_cfg_port_array[src_pid].blk_name, sizeof(p->blk_name));
+            p->mstr_node = biu_cfg_port_array[src_pid].mstr_node;
+            p->src_pid = src_pid;
+            /* Assign read values */
+            que_id = p->que_id = biu_read_queue(src_pid);
+            p->depth = biu_read_queue_depth(que_id);
+            p->cbs = biu_read_queue_cbs(que_id);
+            p->cir = biu_read_queue_cir_incr(que_id);
+            p->ref_cnt[g_ddr_rate_width_idx] = biu_read_queue_ref_cnt(que_id);
+            p->bonus = biu_read_queue_max_bonus(que_id);
+        }
+    }
+    dump_biu_cfg_array(cfg_array);
+
+}
+/* Functions to reset all the coherency port configuration */
+static void reset_biu_cfg(void)
+{
+    volatile CoherencyPortCfgReg_t* reg_addr = (volatile CoherencyPortCfgReg_t * const)UBUS_COHERENCY_PORT_CFG_BASE; 
+    int idx;
+    for (idx = 0; idx < ARRAY_SIZE(reg_addr->lut); idx++) {
+        reg_addr->lut[idx] = 0;
+    }
+    for (idx = 0; idx < ARRAY_SIZE(reg_addr->queue_depth); idx++) {
+        reg_addr->queue_depth[idx] = 0;
+    }
+    for (idx = 0; idx < ARRAY_SIZE(reg_addr->cbs_thresh); idx++) {
+        reg_addr->cbs_thresh[idx] = 0;
+    }
+    for (idx = 0; idx < ARRAY_SIZE(reg_addr->cir_incr); idx++) {
+        reg_addr->cir_incr[idx] = 0;
+    }
+    for (idx = 0; idx < ARRAY_SIZE(reg_addr->ref_cnt); idx++) {
+        reg_addr->ref_cnt[idx] = 0;
+    }
+    for (idx = 0; idx < ARRAY_SIZE(reg_addr->max_bonus); idx++) {
+        reg_addr->max_bonus[idx] = 0;
+    }
+}
+
+/* Functions to set coherency port configuration for a given source port */
+void ubus_remap_to_biu_cfg(const biu_cfg_t *biu_cfg_p)
+{
+    volatile CoherencyPortCfgReg_t* reg_addr = (volatile CoherencyPortCfgReg_t * const)UBUS_COHERENCY_PORT_CFG_BASE; 
+    uint8_t idx;
+    uint32_t mask;
+    uint32_t *reg_p;
+    uint8_t pos;
+
+    /* COHERENCY_PORT_CFG_REG_LUT*/
+    idx = SRCPID_2_LUT_IDX(biu_cfg_p->src_pid);
+    reg_p = &reg_addr->lut[idx];
+    mask = BITS_MASK(QUE_ID_NUM_BITS);
+    pos =  BITS_POS(biu_cfg_p->src_pid, QUE_ID_NUM_BITS);
+    CLEAR_BITS(*reg_p, pos, mask);
+    SET_BITS(*reg_p, pos, biu_cfg_p->que_id);
+
+    /* COHERENCY_PORT_CFG_REG_QUEUE_DEPTH */
+    idx = QUEUE_2_DEPTH_IDX(biu_cfg_p->que_id);
+    reg_p = &reg_addr->queue_depth[idx];
+    mask = BITS_MASK(DEPTH_NUM_BITS);
+    pos =  BITS_POS(biu_cfg_p->que_id, DEPTH_NUM_BITS);
+    CLEAR_BITS(*reg_p, pos, mask);
+    SET_BITS(*reg_p, pos, biu_cfg_p->depth);
+
+    /* COHERENCY_PORT_CFG_REG_CBS_THRESH */
+    idx = QUEUE_2_CBS_IDX(biu_cfg_p->que_id);
+    reg_p = &reg_addr->cbs_thresh[idx];
+    mask = BITS_MASK(CBS_NUM_BITS);
+    pos =  BITS_POS(biu_cfg_p->que_id, CBS_NUM_BITS);
+    CLEAR_BITS(*reg_p, pos, mask);
+    SET_BITS(*reg_p, pos, biu_cfg_p->cbs);
+
+    /* COHERENCY_PORT_CFG_REG_CIR_INCR */
+    idx = QUEUE_2_CIR_INCR_IDX(biu_cfg_p->que_id);
+    reg_p = &reg_addr->cir_incr[idx];
+    mask = BITS_MASK(CIR_INCR_NUM_BITS);
+    pos =  BITS_POS(biu_cfg_p->que_id, CIR_INCR_NUM_BITS);
+    CLEAR_BITS(*reg_p, pos, mask);
+    SET_BITS(*reg_p, pos, biu_cfg_p->cir);
+
+    /* COHERENCY_PORT_CFG_REG_REF_CNT */
+    idx = QUEUE_2_REF_CNT_IDX(biu_cfg_p->que_id);
+    reg_p = &reg_addr->ref_cnt[idx];
+    mask = BITS_MASK(REF_CNT_NUM_BITS);
+    pos =  BITS_POS(biu_cfg_p->que_id,REF_CNT_NUM_BITS);
+    CLEAR_BITS(*reg_p, pos, mask);
+    SET_BITS(*reg_p, pos, biu_cfg_p->ref_cnt[g_ddr_rate_width_idx]); /* Value based on DDR rate/width on current board */
+
+    /* COHERENCY_PORT_CFG_REG_MAX_BONUS */
+    idx = QUEUE_2_MAX_BONUS_IDX(biu_cfg_p->que_id);
+    reg_p = &reg_addr->max_bonus[idx];
+    mask = BITS_MASK(MAX_BONUS_NUM_BITS);;
+    pos =  BITS_POS(biu_cfg_p->que_id,MAX_BONUS_NUM_BITS);
+    CLEAR_BITS(*reg_p, pos, mask);
+    SET_BITS(*reg_p, pos, biu_cfg_p->bonus);
+}
+
+/* Helper functions to read DDR configuration in board parameters and return mapped index in array */
+static int get_ddr_rate_width_idx(void)
+{
+    unsigned int memcfg;
+    unsigned int rate_1600;
+    unsigned int width_16;
+    if (BP_SUCCESS == BpGetMemoryConfig( &memcfg) ) {
+
+        rate_1600 = BP_DDR_SPEED_IS_800( (memcfg & BP_DDR_SPEED_MASK<<BP_DDR_SPEED_SHIFT) >> BP_DDR_SPEED_SHIFT ) ? 1 : 0;
+        width_16 = ( (memcfg & BP_DDR_TOTAL_WIDTH_MASK) == BP_DDR_TOTAL_WIDTH_32BIT ) ? 0 : 1;
+
+        switch (rate_1600) {
+        case 0: /* 2133 */
+            switch(width_16) {
+            case 0: return eDDR_RATE_WIDTH_2133_32; /* 32bit */
+            case 1: return eDDR_RATE_WIDTH_2133_16;/* 16bit */
+            }
+        case 1: /* 1600 */
+            switch(width_16) {
+            case 0: return eDDR_RATE_WIDTH_1600_32;/* 32bit */
+            case 1: return eDDR_RATE_WIDTH_1600_16;/* 16bit */
+            }
+        }
+    }
+    pr_err("\n%s : Failed to find the DDR rate and width \n", __FUNCTION__);
+    return eDDR_RATE_WIDTH_2133_32;
+}
+/* Helper functions to read UBUS credits for each source port as queue depth */
+static void set_queue_depth_from_ubus_credits(void)
+{
+    uint32_t i, idx, jdx;
+    uint32_t mstr_node_idx;
+    uint32_t depth_sum = 0;
+    for (idx=0; idx < BIU_CFG_MAX_SRC_PID; idx++) {
+        if (biu_cfg_port_array[idx].src_pid) { /* Valid Entry */
+
+            for ( i = 0; i < UBUS_NUM_OF_MST_PORTS; i++ ) {
+                if (ubus_credit_tbl[i][0].port_id == biu_cfg_port_array[idx].mstr_node)
+                {
+                    mstr_node_idx = i;
+                    break;
+                }
+            }
+
+            for (jdx=0; ubus_credit_tbl[mstr_node_idx][jdx].port_id != -1 ; jdx++) {
+                if (ubus_credit_tbl[mstr_node_idx][jdx].port_id == UBUS_PORT_ID_BIU) {
+                    biu_cfg_port_array[idx].depth = ubus_credit_tbl[mstr_node_idx][jdx].credit;
+                }
+            }
+        }
+    }
+    /* sum of all queue depth must be <= 64 */
+    for (idx=0; idx < BIU_CFG_MAX_SRC_PID; idx++) {
+        if (biu_cfg_port_array[idx].src_pid) { /* Valid Entry */
+            depth_sum += biu_cfg_port_array[idx].depth;
+            if (depth_sum > 64 || !biu_cfg_port_array[idx].depth) {
+                printk("\n%s() : ERROR - queue depth config error %d %d \n",
+                    __FUNCTION__, depth_sum,biu_cfg_port_array[idx].depth);
+                BUG();
+            }
+        }
+    }
+}
+/* Main functions to do coherency port configuration */
+static void configure_biu_pid_to_queue(void)
+{
+    uint32_t idx;
+    /* Reset everything to ZERO */
+    reset_biu_cfg();
+    /* Read DDR rate/width from board and map to array index */
+    g_ddr_rate_width_idx = get_ddr_rate_width_idx();
+    /* queue depths must be same as UBUS credits */
+    set_queue_depth_from_ubus_credits();
+
+    for (idx=0; idx < BIU_CFG_MAX_SRC_PID; idx++) {
+        if (biu_cfg_port_array[idx].src_pid) { /* Valid Entry */
+            ubus_remap_to_biu_cfg(&biu_cfg_port_array[idx]);
+        }
+    }
+
+    dump_biu_cfg();
+}
+#endif
+#endif
+
+#if !defined(_CFE_) && !defined(__UBOOT__)
+#if IS_BCMCHIP(63178)
+void configure_ubus_sar_reg_decode(void)
+{
+    /* work around for HW63178-272 */
+    int win;
+    MstPortNode *master_addr = bcm_get_ubus_mst_addr(UBUS_PORT_ID_BIU);
+
+    for (win = 0; win < 4; win++)
+    {
+        uint32_t *attr = &master_addr->decode_cfg.window[win].attributes;
+
+        if (!GET_FIELD(*attr, DECODE_CFG_ENABLE))
+        {
+            /* this window is free, use it */
+            /* add 0x4000 address range, starting at offset 0x4000 of the SAR register space, to the CPU UBUS master port */
+            master_addr->decode_cfg.window[win].base_addr =  ((SAR_PHYS_BASE + 0x4000)>>8);
+            master_addr->decode_cfg.window[win].remap_addr = ((SAR_PHYS_BASE + 0x4000)>>8);
+            master_addr->decode_cfg.window[win].attributes = 
+                (DECODE_CFG_ENABLE_ADDR_ONLY | (1 << DECODE_CFG_CMD_DTA_SHIFT) |  (14 << DECODE_CFG_SIZE_SHIFT) | UBUS_PORT_ID_DSL);
+            break;
+        }
+    }
+}
+#endif
+
+static char *size_by_exponent_to_str(int exponent)
+{
+    static char buf[8] = {0};
+
+    if (exponent < 20)
+        snprintf(buf, sizeof(buf), "%dK", 1 << (exponent - 10));
+    else
+        snprintf(buf, sizeof(buf), "%dM", 1 << (exponent - 20));
+
+    return buf;
+}
+
+static ssize_t ubus_tokens_get_proc(struct file *file, char *buff, size_t len, loff_t *offset)
+{
+    int i = 1;
+
+    if (*offset)
+        return 0;
+
+    *offset += sprintf(buff, "%9s | %s", " ", enum_val_to_str(ub_mst_addr_map_tbl[0].port_id, ubus_port_id_to_str));
+    while (ub_mst_addr_map_tbl[i].port_id != -1)
+        *offset += sprintf(buff + *offset, " | %s", enum_val_to_str(ub_mst_addr_map_tbl[i++].port_id, ubus_port_id_to_str));
+
+    *offset += sprintf(buff + *offset, "\n---------------------------------------------------------------------------------------------------------------------");
+
+    i = 0;
+    while (ub_mst_addr_map_tbl[i].port_id != -1)
+    {
+        volatile MstPortNode *master_reg = bcm_get_ubus_mst_addr(ub_mst_addr_map_tbl[i].port_id);
+        int j = 0;
+
+        *offset += sprintf(buff + *offset, "\n%9s", enum_val_to_str(ub_mst_addr_map_tbl[i].port_id, ubus_port_id_to_str));
+        while (ub_mst_addr_map_tbl[j].port_id != -1)
+        {
+            uint32_t port_id = ub_mst_addr_map_tbl[j].port_id;
+            uint32_t field_len = strlen(enum_val_to_str(ub_mst_addr_map_tbl[j].port_id, ubus_port_id_to_str));
+
+            if (master_reg->token[port_id] > 256)
+                *offset += sprintf(buff + *offset, " | %*s", field_len, "-");
+            else
+                *offset += sprintf(buff + *offset, " | %*d", field_len, master_reg->token[port_id]);
+            j++;
+        }
+        i++;
+    }
+    *offset += sprintf(buff + *offset, "\n");
+
+    return *offset;
+}
+
+static ssize_t ubus_decode_get_proc(struct file *file, char *buff, size_t len, loff_t *offset)
+{
+    int i = 0;
+
+    if (*offset)
+        return 0;
+
+    *offset += sprintf(buff + *offset, "Master Port (addr)   | Base     | Remap    | Size  | PortId | Cache:Enable:CD:Strict\n");
+    *offset += sprintf(buff + *offset, "------------------------------------------------------------------------------------\n");
+
+    while (ub_mst_addr_map_tbl[i].port_id != -1)
+    {
+        MstPortNode *master_reg = bcm_get_ubus_mst_addr(ub_mst_addr_map_tbl[i].port_id);
+        int win;
+
+        for (win = 0; win < 4; win++)
+        {
+            char dest_port[16];
+            uint32_t *attr = &master_reg->decode_cfg.window[win].attributes;
+
+            if (!GET_FIELD(*attr, DECODE_CFG_ENABLE))
+                continue;
+
+            strncpy(dest_port, 
+                enum_val_to_str(GET_FIELD(*attr, DECODE_CFG_PORT_ID), ubus_port_id_to_str)
+                ? : "-", sizeof(dest_port));
+
+            *offset += sprintf(buff + *offset, "%-9s (%px) | %08x | %08x | %5s |  %3s   | %x:%x:%x:%x\n", 
+                enum_val_to_str(ub_mst_addr_map_tbl[i].port_id, ubus_port_id_to_str),
+                master_reg, 
+                master_reg->decode_cfg.window[win].base_addr, 
+                master_reg->decode_cfg.window[win].remap_addr,
+                size_by_exponent_to_str(GET_FIELD(*attr, DECODE_CFG_SIZE)),
+                dest_port,
+                GET_FIELD(*attr, DECODE_CFG_CACHE_BITS),
+                GET_FIELD(*attr, DECODE_CFG_ENABLE),
+                GET_FIELD(*attr, DECODE_CFG_CMD_DTA),
+                GET_FIELD(*attr, DECODE_CFG_STRICT));
+        }
+        i++;
+    }
+
+    return *offset;
+}
+
+static int create_ubus_proc(void)
+{
+    int rc = 0;
+
+    proc_dir = proc_mkdir(PROC_DIR, NULL);
+    if (!proc_dir) 
+    {
+        pr_err("Failed to create PROC directory %s.\n",
+            PROC_DIR);
+        goto error;
+    }
+
+    if (!(proc_decode_cfg = proc_create(PROC_DIR "/" UBUS_DECODE_FILE, 0644, NULL, &ubus_decode_proc_fops))) 
+        goto error;
+
+    if (!(proc_tokens = proc_create(PROC_DIR "/" UBUS_TOKENS_FILE, 0644, NULL, &ubus_tokens_proc_fops))) 
+        goto error;
+
+    return rc;
+
+error:
+    if (proc_decode_cfg) 
+    {
+        remove_proc_entry(UBUS_DECODE_FILE, proc_dir);
+        proc_decode_cfg = NULL;
+    }	
+
+    if (proc_tokens)
+    {
+        remove_proc_entry(UBUS_TOKENS_FILE, proc_dir);
+        proc_tokens = NULL;
+    }
+    if (proc_dir)
+    {
+        remove_proc_entry(PROC_DIR, NULL);
+        proc_dir = NULL;
+    }
+
+    return -1;	
+}
+#endif // #ifndef _CFE_
+
+#ifdef CONFIG_BCM_UBUS_DECODE_REMAP
+int ubus_master_remap_port(int master_port_id)
+{
+    int rc = 0;
+
+    rc = ubus_master_decode_wnd_cfg(master_port_id, 
+        DECODE_WIN0, 
+        MST_START_DDR_ADDR, 
+        g_board_size_power_of_2, 
+        UBUS_PORT_ID_BIU, 
+        IS_DDR_COHERENT ? CACHE_BIT_ON : CACHE_BIT_OFF);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d] port[%d] address[0x%x] size[%d]: \n",
+            __FILE__, __LINE__, master_port_id, MST_START_DDR_ADDR,g_board_size_power_of_2);
+    }
+#if defined(CONFIG_BCM_FPM_COHERENCY_EXCLUDE)
+    /*
+     * CONFIG_BCM_FPM_COHERENCY_EXCLUDE is the case when all the memory is coherent
+     * except for FPM pool, since CCI-400 won't sustain 10G traffic load. In that
+     * case we remap FPM pool area to be non-coherent
+     */
+    else
+    {
+        rc = ubus_master_decode_wnd_cfg(master_port_id,
+            DECODE_WIN1,
+            fpm_pool_addr,
+            fpm_pool_size,
+            UBUS_PORT_ID_BIU,
+            CACHE_BIT_OFF);
+        if (rc < 0)
+        {
+            printk("Error %s line[%d] port[%d] address[0x%x] size[%d]: \n",
+                __FILE__, __LINE__, master_port_id, MST_START_DDR_ADDR,g_board_size_power_of_2);
+        }
+    }
+#endif /* CONFIG_BCM_FPM_COHERENCY_EXCLUDE */
+    return rc;
+}
+EXPORT_SYMBOL(ubus_master_remap_port);
+
+int remap_ubus_masters_biu(void)
+{
+    int rc = 0;
+    unsigned int i = 0;
+
+    /* Calculate board size of power 2 */
+    g_board_size_power_of_2 = log2_32(getMemorySize());
+
+#if defined(CONFIG_BCM_FPM_COHERENCY_EXCLUDE)
+    rc = BcmMemReserveGetByName(FPMPOOL_BASE_ADDR_STR, NULL, (phys_addr_t*)&fpm_pool_addr, &fpm_pool_size);
+    if (rc < 0)
+    {
+        printk("Error %s line[%d]: failed to get fpm_pool base address\n",
+            __FILE__, __LINE__);
+        goto exit_;
+    }
+    fpm_pool_size = log2_32(fpm_pool_size);
+#endif /* CONFIG_BCM_FPM_COHERENCY_EXCLUDE */
+
+    UBUS_REMAP_DEBUG_LOG("\x1b[35m board_sdram_size[0x%lx] board_size_power_of_2[%d]\x1b[0m\n",
+        getMemorySize(), g_board_size_power_of_2);
+
+    while(ub_mst_addr_map_tbl[i].port_id != -1)
+    {
+        rc = ubus_master_remap_port(ub_mst_addr_map_tbl[i].port_id);
+        if (rc < 0)
+            goto exit_;
+        i++;
+    }
+
+exit_:
+    if (rc < 0)
+        printk("Error: line[%d] rc = %d\n",__LINE__, rc);
+
+    return rc;                       
+}
+#endif /* CONFIG_BCM_UBUS_DECODE_REMAP */
+
+#if IS_BCMCHIP(63158) || IS_BCMCHIP(6858)
+void apply_ubus_credit_each_master(int master)
+{
+    int i, master_idx;
+    ubus_credit_cfg_t credit;
+
+    for ( i = 0; i < UBUS_NUM_OF_MST_PORTS; i++ ) {
+        if (ubus_credit_tbl[i][0].port_id == master)
+        {
+            master_idx = i;
+            break;
+        }
+    }
+
+    if (i == (UBUS_NUM_OF_MST_PORTS)) {
+        printk("Error: master port id %d not found in credit table\n", master);
+        return;
+    }
+
+    for( i = 1; i < UBUS_MAX_PORT_NUM; i++ ) {
+        credit = ubus_credit_tbl[master_idx][i];
+        if( credit.port_id == -1 )
+            break;
+        ubus_master_set_token_credits(master, credit.port_id, credit.credit);
+    }
+    return;
+}
+#if !defined(_CFE_) && !defined(__UBOOT__)
+static void apply_ubus_credit(void) 
+{
+    int i = 0;
+
+    while(ub_mst_addr_map_tbl[i].port_id != -1)
+    {
+        apply_ubus_credit_each_master(ub_mst_addr_map_tbl[i].port_id);
+        i++;
+    }
+
+    return;
+}
+#endif
+#endif
+
+#if IS_BCMCHIP(6858)
+void ubus_master_rte_cfg(void)
+{
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ0, UBUS_PORT_ID_RQ0, 0x9);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ0, UBUS_PORT_ID_RQ1, 0x209);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ0, UBUS_PORT_ID_RQ2, 0x109);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ0, UBUS_PORT_ID_RQ3, 0x309);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ1, UBUS_PORT_ID_RQ0, 0x9);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ1, UBUS_PORT_ID_RQ1, 0x209);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ1, UBUS_PORT_ID_RQ2, 0x109);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ1, UBUS_PORT_ID_RQ3, 0x309);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ2, UBUS_PORT_ID_RQ0, 0x8);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ2, UBUS_PORT_ID_RQ1, 0x208);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ2, UBUS_PORT_ID_RQ2, 0x108);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ2, UBUS_PORT_ID_RQ3, 0x308);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ3, UBUS_PORT_ID_RQ0, 0x8);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ3, UBUS_PORT_ID_RQ1, 0x208);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ3, UBUS_PORT_ID_RQ2, 0x108);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_RQ3, UBUS_PORT_ID_RQ3, 0x308);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DMA0, UBUS_PORT_ID_RQ0, 0x0);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DMA0, UBUS_PORT_ID_RQ1, 0x8);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DMA0, UBUS_PORT_ID_RQ2, 0x4);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DMA0, UBUS_PORT_ID_RQ3, 0xc);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DMA1, UBUS_PORT_ID_RQ0, 0x1);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DMA1, UBUS_PORT_ID_RQ1, 0x9);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DMA1, UBUS_PORT_ID_RQ2, 0x5);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DMA1, UBUS_PORT_ID_RQ3, 0xd);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DQM, UBUS_PORT_ID_RQ0, 0x2);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DQM, UBUS_PORT_ID_RQ1, 0x6);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DQM, UBUS_PORT_ID_RQ2, 0x24);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_DQM, UBUS_PORT_ID_RQ3, 0x64);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_NATC, UBUS_PORT_ID_RQ0, 0x0);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_NATC, UBUS_PORT_ID_RQ1, 0x8);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_NATC, UBUS_PORT_ID_RQ2, 0x4);
+    ubus_master_set_rte_addr(UBUS_PORT_ID_NATC, UBUS_PORT_ID_RQ3, 0xc);
+}
+#endif
+
+#if IS_BCMCHIP(6858) || IS_BCMCHIP(6846) || IS_BCMCHIP(6856)
+// ucb commands
+#define UCB_CMD_RD               0
+#define UCB_CMD_RD_RPLY          1
+#define UCB_CMD_WR               2
+#define UCB_CMD_WR_ACK           3
+#define UCB_CMD_BCAST            4
+
+static void write_reg_thr_sm(uint32_t ucbid, uint32_t addr, uint32_t data)
+{
+    // check if response fifo is full
+    while( UBUSSYSTOP->ReadUcbStatus & 0x40000000);
+
+    UBUSSYSTOP->UcbData = data;
+
+    UBUSSYSTOP->UcbHdr = (addr/4) | (UCB_CMD_WR<<12) | (ucbid<<16) | (0x1<<24);
+
+    // check if resp fifo has data
+    while( !(UBUSSYSTOP->ReadUcbStatus & 0x80000000 ) );
+
+    UBUSSYSTOP->ReadUcbHdr;
+}
+
+static uint32_t read_reg_thr_sm(uint32_t ucbid, uint32_t addr)
+{
+    // check if response fifo is full
+    while( UBUSSYSTOP->ReadUcbStatus & 0x40000000);    
+
+    UBUSSYSTOP->UcbHdr = (addr/4) | (UCB_CMD_RD<<12) | (ucbid<<16) | (0x1<<24);
+
+    // check if resp fifo has data
+    while( !(UBUSSYSTOP->ReadUcbStatus & 0x80000000 ) );
+
+    UBUSSYSTOP->ReadUcbHdr;
+
+    return UBUSSYSTOP->ReadUcbData;
+}
+
+
+void ubus_deregister_port(int ucbid)
+{
+    // Never play with invalid ubus id
+    if (ucbid < 0) return;
+
+    write_reg_thr_sm(ucbid, 0x1c, 0x1);
+
+    // poll status bit for port unregistered
+    while ( read_reg_thr_sm(ucbid, 0x1c) != 0x1 );
+}
+
+void ubus_register_port(int ucbid)
+{
+    // Never play with invalid ubus id
+    if (ucbid < 0) return;
+
+#if IS_BCMCHIP(6858) || IS_BCMCHIP(6846) || IS_BCMCHIP(6856)
+#if IS_BCMCHIP(6858)
+    if ((ucbid==UCB_NODE_ID_MST_USB) || (ucbid==UCB_NODE_ID_SLV_USB) || (ucbid==UCB_NODE_ID_MST_SATA) || (ucbid==UCB_NODE_ID_SLV_SATA))
+#endif
+    {
+        write_reg_thr_sm(ucbid, 0x1c, 0x0);
+        // poll status bit for port registered
+        while ( read_reg_thr_sm(ucbid, 0x1c) != 0x2 );
+    }
+#endif
+}
+#endif
+
+#if IS_BCMCHIP(6858)
+int ubus_master_set_rte_addr(int master_port_id, int port, int val)
+{
+    volatile MstPortNode *master_addr = NULL;
+
+    master_addr = bcm_get_ubus_mst_addr(master_port_id);    
+
+    if (!master_addr) {
+        printk("Error setting ubus rte addr, master %d not found\n", master_port_id);
+        return -1;
+    }
+
+    master_addr->routing_addr[port] = val;
+
+    return 0;
+}
+#endif
+
+void ubus_master_cpu_enable_axi_write_cache(int enable)
+{
+    volatile MstPortNode *master_addr = NULL;
+
+    master_addr = bcm_get_ubus_mst_addr(UBUS_PORT_ID_BIU);
+    if (enable)
+        master_addr->axi_cfg.cfg &= ~AXI_CFG_AWCACHE_BYPASS;
+    else 
+        master_addr->axi_cfg.cfg |= AXI_CFG_AWCACHE_BYPASS;
+
+    return;
+}
+
+/*this function is used to set UBUS route credits per ubus master, should be equivalent configuration at masters*/
+int ubus_master_set_token_credits(int master_port_id, int token, int credits)
+{
+    volatile MstPortNode *master_addr = NULL;
+
+    master_addr = bcm_get_ubus_mst_addr(master_port_id);
+
+    if (!master_addr) {
+        printk("Error setting ubus credits, master %d not found\n", master_port_id);
+        return -1;
+    }
+
+    //printk("Master node %02d(%px) credit for ubus port %02d is 0x%08x\n", node, &master_addr->token[token], token, master_addr->token[token]);
+    master_addr->token[token] = credits;
+    //printk("Master node %02d(%px) credit for ubus port %02d set to %02d, read back 0x%08x\n", node, &master_addr->token[token], token, credits, master_addr->token[token]);
+    return 0;
+}
+#if !defined(_CFE_) && !defined(__UBOOT__)
+EXPORT_SYMBOL(ubus_master_set_token_credits);
+#endif
+
+// This function initialize ubus master port structure
+void ubus_master_port_init(void)
+{
+#if !defined(_CFE_) && !defined(__UBOOT__)
+    int i=0;
+
+    while (ub_mst_addr_map_tbl[i].port_id != -1)
+    {
+        ub_mst_addr_map_tbl[i].base = (uintptr_t)bcm_dev_phy2vir(ub_mst_addr_map_tbl[i].base);
+        i++;
+    }
+#endif
+}
+
+void bcm_ubus_config(void)
+{
+#if !defined(_CFE_) && !defined(__UBOOT__)
+    create_ubus_proc();
+#if IS_BCMCHIP(63158) || IS_BCMCHIP(6858)
+    apply_ubus_credit();
+#endif
+#if IS_BCMCHIP(6878)
+    ubus_master_set_token_credits(UBUS_PORT_ID_PCIE0, UBUS_PORT_ID_VPB, 1);
+#endif
+#endif
+
+#if IS_BCMCHIP(6858)
+    ubus_master_rte_cfg();
+#endif
+
+#ifdef CONFIG_BCM_UBUS_DECODE_REMAP
+    remap_ubus_masters_biu();
+#if IS_BCMCHIP(63158) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(63146) \
+  || IS_BCMCHIP(4912) || IS_BCMCHIP(6756)
+    ubus_remap_to_biu_cfg_wlu_srcpid(MAX_WLU_SRCPID_NUM, 1);
+#endif
+#if !IS_BCMCHIP(63178) && !IS_BCMCHIP(47622) && !IS_BCMCHIP(63146) && !IS_BCMCHIP(4912) \
+  && !IS_BCMCHIP(6756)
+    configure_biu_pid_to_queue();
+#endif
+#endif /* CONFIG_BCM_UBUS_DECODE_REMAP */
+}
diff --git a/arch/arm/mach-bcmbca/xrdp/Makefile b/arch/arm/mach-bcmbca/xrdp/Makefile
new file mode 100755
index 0000000000..5a377c2d25
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/Makefile
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+CHIP_ID := $(patsubst "bcm%",%,$(CONFIG_SYS_SOC))
+
+# Must defined
+KBUILD_CPPFLAGS += -DBDMF_NO_TRACE -D_BYTE_ORDER_LITTLE_ENDIAN_
+KBUILD_CPPFLAGS += -DFIRMWARE_LITTLE_ENDIAN -DXRDP_SIMPLE_NET
+
+UBOOTINCLUDE += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/xrdp
+UBOOTINCLUDE += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/xrdp/$(subst \",,$(CONFIG_SYS_SOC))
+
+obj-y += rdp_platform.o rdd_common.o rdd_cpu_tx_ring.o rdd_cpu_rx.o
+obj-y += rdp_cpu_ring.o access_logging.o ru.o
+
+ifdef CONFIG_BCMBCA_XRDP_GPL
+obj-y += data_path_init_basic.o  rdpa_gpl_sbpm.o
+else
+KBUILD_CPPFLAGS += -DCONFIG_GPL_RDP_GEN
+UBOOTINCLUDE += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/xrdp/xrdp_full
+obj-y += xrdp_full/
+endif
+
+obj-$(CONFIG_BCM6846) += bcm6846/
+obj-$(CONFIG_BCM6856) += bcm6856/
+obj-$(CONFIG_BCM6858) += bcm6858/
+obj-$(CONFIG_BCM6878) += bcm6878/
+obj-$(CONFIG_BCM63146) += bcm63146/
+
diff --git a/arch/arm/mach-bcmbca/xrdp/access_logging.c b/arch/arm/mach-bcmbca/xrdp/access_logging.c
new file mode 100644
index 0000000000..b61a850abf
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/access_logging.c
@@ -0,0 +1,116 @@
+/*
+ * access_logging.c
+ */
+
+#ifdef CONFIG_BCMBCA_XRDP_GPL
+
+#include <common.h>
+#include "access_macros.h"
+#include "access_logging.h"
+
+#define xrdp_usleep(_a) udelay(_a)
+
+#define ACCESS_LOG_PRINT(_args...)  printf(_args);
+
+/* #define ACCESS_LOG_DEBUG_ENABLE */
+
+#ifdef ACCESS_LOG_DEBUG_ENABLE
+#define ACCESS_LOG_DEBUG(_args...)  ACCESS_LOG_PRINT(_args)
+#else
+#define ACCESS_LOG_DEBUG(_args...)
+#endif
+
+extern uintptr_t rdp_runner_core_addr[];
+
+extern int access_log_restore(const access_log_tuple_t *entry_array)
+{
+	int rc = 0;
+	int i;
+	volatile uint32_t *p_addr;
+	uint32_t start_val;
+	uint32_t adaptive_val;
+	const access_log_tuple_t *entry = entry_array;
+	uint32_t addr;
+	uint32_t op;
+	uint32_t size;
+	uint32_t value;
+	addr_op_size_st addr_op_size;
+
+	while (1) {
+		addr_op_size.value = entry->addr_op_size;
+		op = addr_op_size.op_code;
+		size = addr_op_size.size;
+		addr = addr_op_size.addr + 0x82000000;
+		if ((op == ACCESS_LOG_OP_WRITE) ||
+		    (op == ACCESS_LOG_OP_MWRITE) ||
+		    (op == ACCESS_LOG_OP_WRITE_6BYTE_ADDR)) {
+			if (op == ACCESS_LOG_OP_WRITE_6BYTE_ADDR)
+				addr-= 0x82000000;
+
+			if (size == 4)
+				*(volatile uint32_t *)((uintptr_t)addr) = (uint32_t)(entry->value);
+			else if (size == 2)
+				*(volatile uint16_t *)((uintptr_t)addr) = (uint16_t)(entry->value);
+			else if (size == 1)
+				*(volatile uint8_t *)((uintptr_t)addr) = (uint8_t)(entry->value);
+			else {
+				ACCESS_LOG_PRINT("!!!!!!! op=%d: invalid entry size %u\n", op, size);
+				rc = -1;
+				break;
+			}
+			ACCESS_LOG_DEBUG("write op(%d) size(%d) addr 0x%x data 0x%x\n", op, size, addr, entry->value);
+		} else if (op == ACCESS_LOG_OP_SLEEP) {
+			ACCESS_LOG_PRINT("Sleep %u...\n", entry->value);
+			xrdp_usleep(entry->value);
+		} else if (op == ACCESS_LOG_OP_MEMSET) {
+			size = entry->value;
+			++entry;
+			addr = entry->addr_op_size;
+			value = entry->value;
+			ACCESS_LOG_DEBUG("MEMSET(0x%x, %u, %u)\n", addr, value, size);
+			MEMSET((void *)(uintptr_t)addr, value, size);
+		} else if (op == ACCESS_LOG_OP_MEMSET_32) {
+			size = entry->value;
+			++entry;
+			addr = entry->addr_op_size;
+			value = entry->value;
+			ACCESS_LOG_DEBUG("MEMSET_32(0x%x, %u, %u)\n", addr, value, size);
+			MEMSET_32((void *)(uintptr_t)addr, value, size);
+		} else if (op == ACCESS_LOG_OP_MEMSET_ADAPTIVE_32) {
+			size = entry->value;
+			++entry;
+			addr = entry->addr_op_size;
+			value = entry->value;
+			p_addr = (volatile uint32_t *)(uintptr_t)addr;
+			start_val = value & 0xffff;
+			adaptive_val = (value >> 16) & 0xffff;;
+			ACCESS_LOG_DEBUG("MEMSET_ADAPTIVE_32(0x%lx, %u %u, %u)\n", addr, start_val, adaptive_val, size);
+
+			for (i = 0; i < size; i++) {
+				p_addr[i] = (uint32_t)start_val;
+				start_val += adaptive_val;
+			}
+		} else if (op == ACCESS_LOG_OP_SET_CORE_ADDR) {
+			ACCESS_LOG_DEBUG("SET_CORE_ADDR[%u] = 0x%lx\n", entry->value, addr);
+			rdp_runner_core_addr[entry->value] = addr;
+		} else if (op == ACCESS_LOG_OP_STOP)
+			break;
+		else {
+			ACCESS_LOG_PRINT("!!!!!!! op=%d: invalid operation\n", op);
+			rc = -1;
+			break;
+		}
+		++entry;
+	}
+
+	if (entry)
+		ACCESS_LOG_PRINT("%s: %d entries processed\n", __FUNCTION__, (int)(entry - entry_array));
+
+	return rc;
+}
+#else
+
+int access_log_enable;
+
+#endif /* #ifdef CONFIG_BCMBCA_XRDP_GPL */
+
diff --git a/arch/arm/mach-bcmbca/xrdp/access_logging.h b/arch/arm/mach-bcmbca/xrdp/access_logging.h
new file mode 100644
index 0000000000..1db75bf571
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/access_logging.h
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+	
+*/
+
+/*
+ * access_logging.h
+ */
+
+#ifndef _ACCESS_LOGGING_H_
+#define _ACCESS_LOGGING_H_
+
+#include <stdio.h>
+
+typedef enum
+{
+	ACCESS_LOG_OP_WRITE,
+	ACCESS_LOG_OP_MWRITE,
+	ACCESS_LOG_OP_MEMSET,
+	ACCESS_LOG_OP_MEMSET_32,
+	ACCESS_LOG_OP_SLEEP,
+	ACCESS_LOG_OP_SET_CORE_ADDR,
+	ACCESS_LOG_OP_STOP,
+	ACCESS_LOG_OP_MEMSET_ADAPTIVE_32,
+	ACCESS_LOG_OP_WRITE_6BYTE_ADDR,
+} access_log_op_t;
+
+typedef union os_size_st_union {
+	uint32_t value;
+	struct {
+		uint32_t addr : 24;
+		uint32_t op_code : 4;
+		uint32_t size : 4;
+	};
+} addr_op_size_st;
+
+typedef struct access_log_tuple {
+	uint32_t addr_op_size;
+	uint32_t value;
+} access_log_tuple_t;
+
+#if !defined(CONFIG_BCMBCA_XRDP_GPL)
+
+extern int access_log_enable;
+
+static inline void access_log_enable_set(int enable)
+{
+	access_log_enable = enable;
+}
+
+static inline int access_log_enable_get(void)
+{
+	return access_log_enable;
+}
+
+#define ACCESS_LOG_ENTRY_MARK   ">>>"
+
+#define ACCESS_LOG_PRINT(addr, value) \
+	printf(ACCESS_LOG_ENTRY_MARK " 0x%x 0x%x \n", addr, value)
+
+static inline void access_log_log(access_log_op_t op, uint32_t addr,
+				  uint32_t value, uint32_t size)
+{
+	addr_op_size_st addr_op_size;
+	addr_op_size.value = 0;
+
+	if (access_log_enable_get()) {
+		if ((op!= ACCESS_LOG_OP_MEMSET) &&
+		    (op!= ACCESS_LOG_OP_MEMSET_32) &&
+		    (op!= ACCESS_LOG_OP_MEMSET_ADAPTIVE_32)) {
+			/* not memset */
+			if  (((op ==  ACCESS_LOG_OP_WRITE) ||
+			      (op ==  ACCESS_LOG_OP_MWRITE)) &&
+			     (addr < 0x82000000))
+				op = ACCESS_LOG_OP_WRITE_6BYTE_ADDR;
+
+			addr_op_size.addr = addr & 0xFFFFFF;
+			addr_op_size.op_code = op & 0xf;
+			addr_op_size.size = size & 0xf;
+
+			ACCESS_LOG_PRINT(addr_op_size.value, value);
+		} else {
+			/* memset is represented in 2 lines
+			 * first line op code + size
+			 * second line address + value */
+			addr_op_size.op_code = op & 0xF;
+			ACCESS_LOG_PRINT(addr_op_size.value, size);
+			ACCESS_LOG_PRINT(addr, value);
+		}
+	}
+}
+
+#define ACCESS_LOG(_op, _a, _v, _sz) \
+	access_log_log(_op, (unsigned long)(_a), (uint32_t)(_v), (uint32_t)(_sz))
+
+#define ACCESS_LOG_ENABLE_SET(_e)  access_log_enable_set(_e)
+
+#undef xrdp_usleep
+#define xrdp_usleep(_d) \
+	do { \
+		ACCESS_LOG(ACCESS_LOG_OP_SLEEP, 0, _d, 0); \
+		udelay(_d); \
+	} while(0)
+
+
+#else /* #if defined(CONFIG_BCMBCA_XRDP_GPL) */
+
+#define ACCESS_LOG(_op, _a, _v, _sz)
+#define ACCESS_LOG_ENABLE_SET(_e)
+
+extern int access_log_restore(const access_log_tuple_t *entry_array);
+
+#endif /* #if !defined(CONFIG_BCMBCA_XRDP_GPL) */
+#endif /* _ACCESS_LOGGING_H_ */
+
diff --git a/arch/arm/mach-bcmbca/xrdp/access_macros.h b/arch/arm/mach-bcmbca/xrdp/access_macros.h
new file mode 100644
index 0000000000..60a0f9d8dd
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/access_macros.h
@@ -0,0 +1,471 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+	
+*/
+
+#ifndef __ACCESS_MACROS_H_INCLUDED
+#define __ACCESS_MACROS_H_INCLUDED
+
+#include <linux/types.h>
+#include <linux/io.h>
+#include <asm/barriers.h>
+#include "access_logging.h"
+
+/*****************/
+/* Generic swaps */
+/*****************/
+static inline uint16_t __swap2bytes(uint16_t a)
+{
+	return (a << 8) | (a >> 8);
+}
+static inline uint32_t __swap4bytes(uint32_t a)
+{
+	return (a << 24) | ((a & 0xFF00) << 8) |
+		((a & 0xFF0000) >> 8) | (a >> 24);
+}
+
+static inline uint64_t __swap4bytes64(uint64_t a)
+{
+	return __swap4bytes(a) |
+		((uint64_t)__swap4bytes((a>>32) & 0xFFFFFFFF) << 32);
+}
+
+/**************************/
+/* swap2bytes, swap4bytes */
+/**************************/
+#if defined(_BYTE_ORDER_LITTLE_ENDIAN_)
+#if defined(CONFIG_ARM)
+static inline uint16_t swap2bytes(uint16_t a)
+{
+	__asm__("rev16 %0, %1" : "=r" (a) : "r" (a));
+	return a;
+}
+
+#if defined(CONFIG_ARM64)
+static inline uint32_t swap4bytes(uint32_t a)
+{
+	__asm__("rev32 %0, %1" : "=r" (a) : "r" (a));
+	return a;
+}
+
+/* reverses the 4 bytes in each 32-bit element of Xm*/
+static inline uint64_t swap4bytes64(uint64_t a)
+{
+	__asm__("rev32 %0, %1" : "=r" (a) : "r" (a));
+	return a;
+}
+#else
+static inline uint32_t swap4bytes(uint32_t a)
+{
+	__asm__("rev %0, %1" : "=r" (a) : "r" (a));
+	return a;
+}
+#endif
+#else
+#define swap2bytes(x) __swap2bytes(x)
+#define swap4bytes(x) __swap4bytes(x)
+#define swap4bytes64(x) __swap4bytes64(x)
+#endif /* CONFIG_ARM */
+#else /* _BYTE_ORDER_LITTLE_ENDIAN_ */
+#define swap2bytes(x) (x)
+#define swap4bytes(x) (x)
+#define swap4bytes64(x) (x)
+#endif /* _BYTE_ORDER_LITTLE_ENDIAN_ */
+
+#define SWAPBYTES(_buffer, _len) \
+	do { \
+		uint8_t _i; \
+		for (_i = 0; _i < _len; _i += sizeof(uint32_t)) \
+			*((uint32_t *)(&(_buffer[_i]))) = \
+				swap4bytes(*((uint32_t *)(&(_buffer[_i])))); \
+	} while (0)
+
+/******************/
+/* Device address */
+/******************/
+#define DEVICE_ADDRESS(_a) ((volatile uint8_t * const)((uintptr_t)(_a)))
+
+/**********/
+/* MEMSET */
+/**********/
+#if defined(DUAL_ISSUE)
+#define MEMSET(a, v, sz)	_xrdp__memset(a, v, sz)
+#else
+#define MEMSET(a, v, sz)	memset_io(a, v, sz)
+#endif
+
+/******************/
+/* Memory Barrier */
+/******************/
+#define WMB()	__iowmb() /* memory barrier */
+#define RMB()	__iormb() /* memory barrier */
+
+/************************/
+/* Registers and memory */
+/************************/
+
+/* Registers */
+#define VAL32(_a) (*(volatile uint32_t *)(DEVICE_ADDRESS(_a)))
+#define READ_8(a, r) \
+	(*(volatile uint8_t *)&(r) = *(volatile uint8_t *)DEVICE_ADDRESS(a))
+#define READ_16(a, r) \
+	(*(volatile uint16_t *)&(r) = *(volatile uint16_t *)DEVICE_ADDRESS(a))
+#define READ_32(a, r) \
+	(*(volatile uint32_t *)&(r) = *(volatile uint32_t *)DEVICE_ADDRESS(a))
+
+#if defined(XRDP_SIMPLE_NET)
+/*this version use read modify write method to save writes in CFE GPL mode */
+#define WRITE_8(a, r) \
+	do { \
+		uint8_t temp; \
+		uint8_t temp1 = *(uint8_t *)&r; \
+		READ_8(a, temp); \
+		if ((temp != temp1) || (temp != 0)) { \
+			(*(volatile uint8_t *)DEVICE_ADDRESS(a) = *(uint8_t *)&(r)); \
+			ACCESS_LOG(ACCESS_LOG_OP_WRITE, DEVICE_ADDRESS(a), *(uint8_t *)&(r), 1); \
+		} \
+	} while (0)
+#define WRITE_16(a, r) \
+	do { \
+		uint16_t temp; \
+		uint16_t temp1 = *(uint16_t *)&r; \
+		READ_16(a, temp); \
+		if ((temp != temp1) || (temp != 0)) { \
+			(*(volatile uint16_t *)DEVICE_ADDRESS(a) = *(uint16_t *)&(r)); \
+			ACCESS_LOG(ACCESS_LOG_OP_WRITE, DEVICE_ADDRESS(a), *(uint16_t *)&(r), 2); \
+		} \
+	} while (0)
+#define WRITE_32(a, r) \
+	do { \
+		uint32_t temp; \
+		uint32_t temp1 = *(uint32_t *)&r; \
+		READ_32(a, temp); \
+		if ((temp != temp1) || (temp != 0)) { \
+			(*(volatile uint32_t *)DEVICE_ADDRESS(a) = *(uint32_t *)&(r)); \
+			ACCESS_LOG(ACCESS_LOG_OP_WRITE, DEVICE_ADDRESS(a), *(uint32_t *)&(r), 4); \
+		} \
+	} while (0)
+#else
+#define WRITE_8(a, r) \
+	do { \
+		(*(volatile uint8_t *)DEVICE_ADDRESS(a) = *(uint8_t *)&(r)); \
+		ACCESS_LOG(ACCESS_LOG_OP_WRITE, DEVICE_ADDRESS(a), *(uint8_t *)&(r), 1); \
+	} while (0)
+#define WRITE_16(a, r) \
+	do { \
+		(*(volatile uint16_t *)DEVICE_ADDRESS(a) = *(uint16_t *)&(r)); \
+		ACCESS_LOG(ACCESS_LOG_OP_WRITE, DEVICE_ADDRESS(a), *(uint16_t *)&(r), 2); \
+	} while (0)
+#define WRITE_32(a, r) \
+	do { \
+		(*(volatile uint32_t *)DEVICE_ADDRESS(a) = *(uint32_t *)&(r)); \
+		ACCESS_LOG(ACCESS_LOG_OP_WRITE, DEVICE_ADDRESS(a), *(uint32_t *)&(r), 4); \
+	} while (0)
+#endif
+
+#define READ_I_8(a, i, r) (*(volatile uint8_t *)&(r) = *((volatile uint8_t *)DEVICE_ADDRESS(a) + (i)))
+#define READ_I_16(a, i, r) (*(volatile uint16_t *)&(r) = *((volatile uint16_t *)DEVICE_ADDRESS(a) + (i)))
+#define READ_I_32(a, i, r) (*(volatile uint32_t *)&(r) = *((volatile uint32_t *)DEVICE_ADDRESS(a) + (i)))
+
+#define WRITE_I_8(a, i, r) \
+	do { \
+		(*((volatile uint8_t *)DEVICE_ADDRESS(a) + (i)) = *(uint8_t *)&(r)); \
+		ACCESS_LOG(ACCESS_LOG_OP_WRITE, (volatile uint8_t *)DEVICE_ADDRESS(a) + (i), *(uint8_t *)&(r), 1); \
+	} while (0)
+#define WRITE_I_16(a, i, r) \
+	do { \
+		(*((volatile uint16_t *)DEVICE_ADDRESS(a) + (i)) = *(uint16_t *)&(r)); \
+		ACCESS_LOG(ACCESS_LOG_OP_WRITE, (volatile uint16_t *)DEVICE_ADDRESS(a) + (i), *(uint16_t *)&(r), 2); \
+	} while (0)
+#define WRITE_I_32(a, i, r) \
+	do { \
+		(*((volatile uint32_t *)DEVICE_ADDRESS(a) + (i)) = *(uint32_t *)&(r)); \
+		ACCESS_LOG(ACCESS_LOG_OP_WRITE, (volatile uint32_t *)DEVICE_ADDRESS(a) + (i), *(uint32_t *)&(r), 4); \
+	} while (0)
+
+
+/* Memory */
+#define MGET_8(a)	(*(volatile uint8_t *)(a))
+#define MGET_16(a)	swap2bytes(*(volatile uint16_t *)(a))
+#define MGET_32(a)	swap4bytes(*(volatile uint32_t *)(a))
+
+#define MGET_I_8(a, i)	(*((volatile uint8_t *)(a) + (i)))
+#define MGET_I_16(a, i)	swap2bytes(*((volatile uint16_t *)(a) + (i)))
+#define MGET_I_32(a, i)	swap4bytes(*((volatile uint32_t *)(a) + (i)))
+
+#define MWRITE_8(a, r) \
+	do { \
+		(*(volatile uint8_t *)(a) = (uint8_t)(r)); \
+		ACCESS_LOG(ACCESS_LOG_OP_MWRITE, (a), (r), 1); \
+	} while (0)
+#define MWRITE_16(a, r) \
+	do { \
+		(*(volatile uint16_t *)(a) = swap2bytes((uint16_t)(r))); \
+		ACCESS_LOG(ACCESS_LOG_OP_MWRITE, (a), swap2bytes((uint16_t)(r)), 2); \
+	} while (0)
+
+#define MWRITE_32(a, r) \
+	do { \
+		(*(volatile uint32_t *)(a) = swap4bytes((uint32_t)(r))); \
+		ACCESS_LOG(ACCESS_LOG_OP_MWRITE, (a), swap4bytes((uint32_t)(r)), 4); \
+	} while (0)
+
+#define MWRITE_I_8(a, i, r) \
+	do { \
+		(*((volatile uint8_t *)(a) + (i)) = (uint8_t)(r)); \
+		ACCESS_LOG(ACCESS_LOG_OP_MWRITE, ((volatile uint8_t *)(a) + (i)), (r), 1); \
+	} while (0)
+#define MWRITE_I_16(a, i, r) \
+	do { \
+		(*((volatile uint16_t *)(a) + (i)) = swap2bytes((uint16_t)(r))); \
+		ACCESS_LOG(ACCESS_LOG_OP_MWRITE, ((volatile uint16_t *)(a) + (i)), swap2bytes((uint16_t)(r)), 2); \
+	} while (0)
+#define MWRITE_I_32(a, i, r) \
+	do { \
+		(*((volatile uint32_t *)(a) + (i)) = swap4bytes((uint32_t)(r))); \
+		ACCESS_LOG(ACCESS_LOG_OP_MWRITE, ((volatile uint32_t *)(a) + (i)), swap4bytes((uint32_t)(r)), 4); \
+	} while (0)
+#define MWRITE_I_32_NOLOG(a, i, r) \
+	do { \
+		(*((volatile uint32_t *)(a) + (i)) = swap4bytes((uint32_t)(r))); \
+	} while (0)
+
+#if defined(CONFIG_ARM64)
+#define MWRITE_I_64(a, i, r)	(*((volatile uint64_t *)(a) + (i)) = swap4bytes64((uint64_t)(r)))
+#endif
+
+#define MREAD_8(a, r)	((r) = MGET_8(a))
+#define MREAD_16(a, r)	((r) = MGET_16(a))
+#define MREAD_32(a, r)	((r) = MGET_32(a))
+
+#define MREAD_I_8(a, i, r)	((r) = MGET_I_8((a), (i)))
+#define MREAD_I_16(a, i, r)	((r) = MGET_I_16((a), (i)))
+#define MREAD_I_32(a, i, r)	((r) = MGET_I_32((a), (i)))
+
+#if defined(DUAL_ISSUE)
+#define MREAD_BLK_8(d, s, sz)	_xrdp__memcpy(d, s, sz)
+#define MREAD_BLK_16(d, s, sz)	_xrdp__memcpy(d, s, sz)
+#define MREAD_BLK_32(d, s, sz)	_xrdp__memcpy(d, s, sz)
+#else
+#define MREAD_BLK_8(d, s, sz)	memcpy_fromio(d, s, sz)
+#define MREAD_BLK_16(d, s, sz)	memcpy_fromio(d, s, sz)
+#define MREAD_BLK_32(d, s, sz)	memcpy_fromio(d, s, sz)
+#endif
+
+
+/*************/
+/* MEMSET_32 */
+/*************/
+#define MEMSET_32(a, v_32, sz_32) \
+	do { \
+		int __i; \
+		for (__i=0; __i<sz_32; __i++) \
+			MWRITE_I_32_NOLOG(a, __i, v_32); \
+		ACCESS_LOG(ACCESS_LOG_OP_MEMSET_32, a, v_32, sz_32); \
+	} while (0)
+
+#if defined(_CFE_) || defined(RDP_SIM)
+#define MWRITE_BLK_8(d, s, sz) memcpy(d, s, sz)
+#else
+#if defined(CONFIG_BCM6878) || defined(CONFIG_BCM63146)
+#define MWRITE_BLK_8(d, s, sz) \
+	do { \
+		uint32_t i, val; \
+		for (i = 0; i < (sz); i++) { \
+			val = *((volatile uint8_t *)(s) + (i)); \
+			MWRITE_I_8((uint32_t)(d), i, val); \
+		} \
+	} while (0)
+#else
+#if defined(CONFIG_ARM64)
+#define MWRITE_BLK_8(d, s, sz) memcpy_toio(d, s, sz)
+#else
+#define MWRITE_BLK_8(d, s, sz) memcpy(d, s, sz)
+#endif
+#endif
+#endif
+
+#define MWRITE_BLK_16(d, s, sz) \
+	do { \
+		uint32_t i, val; \
+		for (i = 0; i < (sz / 2); i++) { \
+			val = *((volatile uint16_t *)(s) + (i)); \
+			MWRITE_I_16(d, i, val); \
+		} \
+	} while (0)
+#define MWRITE_BLK_32(d, s, sz) \
+	do { \
+		uint32_t i, val; \
+		for (i = 0; i < (sz / 4); i++) { \
+			val = *((volatile uint32_t *)(s) + (i)); \
+			MWRITE_I_32(d, i, val); \
+		} \
+	} while (0)
+
+#define MWRITE_BLK_32_SWAP(d, s, sz) \
+	do { \
+		uint32_t i, val; \
+		for ( i = 0; i < ( sz / 4 ); i++ ) { \
+			val = *((volatile uint32_t*)(s) + (i)); \
+			val = swap4bytes(val); MWRITE_I_32( d, i, val ); \
+		} \
+	} while (0)
+
+#define MWRITE_BLK_16_SWAP(d, s, sz) \
+	do { \
+		uint32_t i, val; \
+		for (i = 0; i < (sz / 2); i++) { \
+			val = *((volatile uint16_t *)(s) + (i)); \
+			val = swap2bytes(val); \
+			MWRITE_I_16((uint32_t)d, i, val); \
+		} \
+	} while (0)
+
+/**************************/
+/* Bit-field access macros
+: v	 -  value
+: lsbn  - ls_bit_number
+: fw	- field_width
+: a	 - address
+: rv	- read_value	  */
+/**************************/
+#define FIELD_GET(v, lsbn, fw)	(((v)>>(lsbn)) & ((unsigned)(1 << (fw)) - 1))
+
+#define FIELD_MGET_32(a, lsbn, fw)	(FIELD_GET(MGET_32(a), (lsbn), (fw)))
+#define FIELD_MGET_16(a, lsbn, fw)	(FIELD_GET(MGET_16(a), (lsbn), (fw)))
+#define FIELD_MGET_8(a, lsbn, fw)	(FIELD_GET(MGET_8(a) , (lsbn), (fw)))
+
+#define FIELD_MREAD_8(a, lsbn, fw, rv)	(rv = FIELD_MGET_8((a), (lsbn), (fw)))
+#define FIELD_MREAD_16(a, lsbn, fw, rv)	(rv = FIELD_MGET_16((a), (lsbn), (fw)))
+#define FIELD_MREAD_32(a, lsbn, fw, rv)	(rv = FIELD_MGET_32((a), (lsbn), (fw)))
+
+#define FIELD_SET(value, ls_bit_number, field_width, write_value) \
+	do { \
+		uint32_t mask; \
+		mask = ((1 << (field_width)) - 1) << (ls_bit_number); \
+		value &=  ~mask; \
+		value |= (write_value) << (ls_bit_number); \
+	} while (0)
+
+#define FIELD_MWRITE_32(address, ls_bit_number, field_width, write_value) \
+	do { \
+		uint32_t current_value = MGET_32(address); \
+		FIELD_SET(current_value, ls_bit_number, field_width, write_value); \
+		MWRITE_32(address, current_value); \
+	} while (0)
+
+#define FIELD_MWRITE_16(address, ls_bit_number, field_width, write_value) \
+	do { \
+		uint16_t current_value = MGET_16(address); \
+		FIELD_SET(current_value, ls_bit_number, field_width, write_value); \
+		MWRITE_16(address, current_value); \
+	} while (0)
+
+#define FIELD_MWRITE_8(address, ls_bit_number, field_width, write_value) \
+	do { \
+		uint8_t current_value = MGET_8(address); \
+		FIELD_SET(current_value, ls_bit_number, field_width, write_value); \
+		MWRITE_8(address, current_value); \
+	} while (0)
+
+#define GROUP_MREAD_I_8(group, addr, i, ret)	(ret = _rdd_i_read(group, (addr), i, rdd_size_8))
+#define GROUP_MREAD_I_16(group, addr, i, ret)	(ret = _rdd_i_read(group, (addr), i, rdd_size_16))
+#define GROUP_MREAD_I_32(group, addr, i, ret)	(ret = _rdd_i_read(group, (addr), i, rdd_size_32))
+
+#define GROUP_MREAD_8(group, addr, ret)		(ret = _rdd_i_read(group, (addr), 0, rdd_size_8))
+#define GROUP_MREAD_16(group, addr, ret)	(ret = _rdd_i_read(group, (addr), 0, rdd_size_16))
+#define GROUP_MREAD_32(group, addr, ret)	(ret = _rdd_i_read(group, (addr), 0, rdd_size_32))
+
+#define GROUP_FIELD_MREAD_8(group, addr, lsb, width, ret) \
+	(ret = _rdd_field_read(group, (addr), lsb, width, rdd_size_8))
+#define GROUP_FIELD_MREAD_16(group, addr, lsb, width, ret) \
+	(ret = _rdd_field_read(group, (addr), lsb, width, rdd_size_16))
+#define GROUP_FIELD_MREAD_32(group, addr, lsb, width, ret) \
+	(ret = _rdd_field_read(group, (addr), lsb, width, rdd_size_32))
+
+#define GROUP_MWRITE_I_8(group, addr, i, val)	_rdd_i_write(group, (addr), val, i, rdd_size_8)
+#define GROUP_MWRITE_I_16(group, addr, i, val)	_rdd_i_write(group, (addr), val, i, rdd_size_16)
+#define GROUP_MWRITE_I_32(group, addr, i, val)	_rdd_i_write(group, (addr), val, i, rdd_size_32)
+
+#define GROUP_MWRITE_8(group, addr, val)	_rdd_i_write(group, (addr), val, 0, rdd_size_8)
+#define GROUP_MWRITE_16(group, addr, val)	_rdd_i_write(group, (addr), val, 0, rdd_size_16)
+#define GROUP_MWRITE_32(group, addr, val)	_rdd_i_write(group, (addr), val, 0, rdd_size_32)
+
+#define GROUP_FIELD_MWRITE_8(group, addr, lsb, width, val) \
+	_rdd_field_write(group, (addr), val, lsb, width, rdd_size_8)
+#define GROUP_FIELD_MWRITE_16(group, addr, lsb, width, val) \
+	_rdd_field_write(group, (addr), val, lsb, width, rdd_size_16)
+#define GROUP_FIELD_MWRITE_32(group, addr, lsb, width, val) \
+	_rdd_field_write(group, (addr), val, lsb, width, rdd_size_32)
+
+#if defined(DUAL_ISSUE)
+static inline void *_xrdp__memcpy(void *dst, void const *src, size_t len) 
+{
+    uint8_t *u8dst_ptr = (uint8_t *)dst;
+    uint8_t const *u8src_ptr = (uint8_t const *)src;
+    uint src_alignment = (uint)((uintptr_t)src & (uintptr_t)(sizeof(uint32_t) - 1));
+    uint dst_alignment = (uint)((uintptr_t)dst & (uintptr_t)(sizeof(uint32_t) - 1));
+
+    if (len >= sizeof(uint32_t) &&  src_alignment == dst_alignment ) 
+    {
+        while (((uintptr_t)u8src_ptr & (uintptr_t)(sizeof(uint32_t) - 1)) != 0) 
+        {
+            *u8dst_ptr++ = *u8src_ptr++;
+            len--;
+        }
+        {
+            uint32_t *u32dst_ptr = (uint32_t *)u8dst_ptr;
+            uint32_t const *u32src_ptr = (uint32_t const *)u8src_ptr;
+    
+            while (len >= sizeof(uint32_t)) 
+            {
+                *u32dst_ptr++ = *u32src_ptr++;
+                len -= sizeof(uint32_t);
+            }
+            u8dst_ptr = (uint8_t *)u32dst_ptr;
+            u8src_ptr = (uint8_t const *)u32src_ptr;
+        }
+    }
+    while (len--) 
+    {
+         *u8dst_ptr++ = *u8src_ptr++;
+    }
+    return dst;
+}
+
+static inline void *_xrdp__memset(void *dst, int v, size_t len)
+{
+    uint8_t  *u8dst_ptr = (uint8_t *)dst;
+    uint8_t  c_val = (uint8_t)v;
+    uint32_t u32_val = (uint32_t)c_val<<24 || (uint32_t)c_val<<16 || (uint32_t)c_val<<8 || (uint32_t)c_val<<24;
+
+    while (len && (((uintptr_t)u8dst_ptr & (uintptr_t)(sizeof(uint32_t) - 1)) != 0))
+    {
+        *u8dst_ptr++ = c_val;
+        len--;
+    }
+    
+    {
+        uint32_t *u32dst_ptr = (uint32_t *)u8dst_ptr;
+        while ( len >= sizeof(uint32_t) ) 
+        {
+            *u32dst_ptr++ = u32_val;
+            len -= sizeof(uint32_t);
+        }
+    }
+
+    while (len) 
+    {
+        *u8dst_ptr++ = c_val;
+        len--;
+    }
+    
+    return dst;
+}
+
+#endif /* defined(DUAL_ISSUE) */
+
+#endif /* __ACCESS_MACROS_H_INCLUDED */
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/Makefile b/arch/arm/mach-bcmbca/xrdp/bcm63146/Makefile
new file mode 100755
index 0000000000..59d9964bf9
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/Makefile
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+UBOOTINCLUDE += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/xrdp -I$(srctree)/arch/$(ARCH)/mach-bcmbca/xrdp/$(subst \",,$(CONFIG_SYS_SOC))
+ifndef CONFIG_BCMBCA_XRDP_GPL
+UBOOTINCLUDE += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/xrdp/xrdp_full
+endif
+
+obj-y += rdd_data_structures_auto.o rdd_map_auto.o
+obj-y += xrdp_drv_drivers_common_ag.o
+obj-y += XRDP_AG.o
+ifdef CONFIG_BCMBCA_XRDP_GPL
+# handcrafted version is to take out the definition of unused registers
+# in GPL version.  Those waste a lot of rodata memory.
+obj-y += xrdp_drv_psram.o xrdp_drv_sbpm.o xrdp_drv_unimac_rdp.o
+obj-y += xrdp_drv_rnr_regs.o
+obj-y += XRDP_PSRAM_GPL.o XRDP_SBPM_GPL.o
+obj-y += XRDP_UNIMAC_RDP_GPL.o XRDP_RNR_REGS_GPL.o
+endif
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_AG.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_AG.c
new file mode 100644
index 0000000000..fe4e878f21
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_AG.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+/******************************************************************************
+ * Chip: XRDP_
+ ******************************************************************************/
+const ru_block_rec *RU_ALL_BLOCKS[] =
+{
+    &QM_BLOCK,
+    &DQM_TOKEN_FIFO_BLOCK,
+    &DQM_BLOCK,
+    &FPM_BLOCK,
+    &RNR_MEM_BLOCK,
+    &RNR_INST_BLOCK,
+    &RNR_CNTXT_BLOCK,
+    &RNR_PRED_BLOCK,
+    &RNR_REGS_BLOCK,
+    &RNR_QUAD_BLOCK,
+    &DSPTCHR_BLOCK,
+    &BBH_TX_BLOCK,
+    &BBH_RX_BLOCK,
+    &UBUS_MSTR_BLOCK,
+    &UBUS_SLV_BLOCK,
+    &SBPM_BLOCK,
+    &DMA_BLOCK,
+    &PSRAM_BLOCK,
+    &UNIMAC_RDP_BLOCK,
+    &UNIMAC_MISC_BLOCK,
+    &TCAM_BLOCK,
+    &HASH_BLOCK,
+    &BAC_IF_BLOCK,
+    &CNPL_BLOCK,
+    &NATC_ENG_BLOCK,
+    &NATC_CTRS_BLOCK,
+    &NATC_DDR_CFG_BLOCK,
+    &NATC_BLOCK,
+    &NATC_TBL_BLOCK,
+    &NATC_KEY_BLOCK,
+    &NATC_INDIR_BLOCK,
+    NULL
+};
+
+/* End of file XRDP_.c */
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_AG.h b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_AG.h
new file mode 100644
index 0000000000..420434ec65
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_AG.h
@@ -0,0 +1,21124 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _XRDP_AG_H_
+#define _XRDP_AG_H_
+
+#include "ru.h"
+
+/******************************************************************************
+ * XRDP_ Fields
+ ******************************************************************************/
+extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_FPM_PREFETCH_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_FPM_PREFETCH_ENABLE_FIELD_MASK  0x00000001
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_FPM_PREFETCH_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_FPM_PREFETCH_ENABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_REORDER_CREDIT_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_REORDER_CREDIT_ENABLE_FIELD_MASK  0x00000002
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_REORDER_CREDIT_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_REORDER_CREDIT_ENABLE_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_POP_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_POP_ENABLE_FIELD_MASK  0x00000004
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_POP_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_POP_ENABLE_FIELD_SHIFT 2
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED0_FIELD_MASK  0x000000f8
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED0_FIELD_WIDTH 5
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_RMT_FIXED_ARB_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RMT_FIXED_ARB_ENABLE_FIELD_MASK  0x00000100
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RMT_FIXED_ARB_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RMT_FIXED_ARB_ENABLE_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_PUSH_FIXED_ARB_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_PUSH_FIXED_ARB_ENABLE_FIELD_MASK  0x00000200
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_PUSH_FIXED_ARB_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_PUSH_FIXED_ARB_ENABLE_FIELD_SHIFT 9
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED1_FIELD;
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED1_FIELD_MASK  0xfffffc00
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED1_FIELD_WIDTH 22
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED1_FIELD_SHIFT 10
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH0_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH0_SW_RST_FIELD_MASK  0x00000001
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH0_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH0_SW_RST_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH1_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH1_SW_RST_FIELD_MASK  0x00000002
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH1_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH1_SW_RST_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH2_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH2_SW_RST_FIELD_MASK  0x00000004
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH2_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH2_SW_RST_FIELD_SHIFT 2
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH3_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH3_SW_RST_FIELD_MASK  0x00000008
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH3_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH3_SW_RST_FIELD_SHIFT 3
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_NORMAL_RMT_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NORMAL_RMT_SW_RST_FIELD_MASK  0x00000010
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NORMAL_RMT_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NORMAL_RMT_SW_RST_FIELD_SHIFT 4
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_RMT_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_RMT_SW_RST_FIELD_MASK  0x00000020
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_RMT_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_RMT_SW_RST_FIELD_SHIFT 5
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_PRE_CM_FIFO_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_PRE_CM_FIFO_SW_RST_FIELD_MASK  0x00000040
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_PRE_CM_FIFO_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_PRE_CM_FIFO_SW_RST_FIELD_SHIFT 6
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_RD_PD_FIFO_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_RD_PD_FIFO_SW_RST_FIELD_MASK  0x00000080
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_RD_PD_FIFO_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_RD_PD_FIFO_SW_RST_FIELD_SHIFT 7
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_WR_PD_FIFO_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_WR_PD_FIFO_SW_RST_FIELD_MASK  0x00000100
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_WR_PD_FIFO_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_WR_PD_FIFO_SW_RST_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB0_OUTPUT_FIFO_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB0_OUTPUT_FIFO_SW_RST_FIELD_MASK  0x00000200
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB0_OUTPUT_FIFO_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB0_OUTPUT_FIFO_SW_RST_FIELD_SHIFT 9
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_OUTPUT_FIFO_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_OUTPUT_FIFO_SW_RST_FIELD_MASK  0x00000400
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_OUTPUT_FIFO_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_OUTPUT_FIFO_SW_RST_FIELD_SHIFT 10
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_INPUT_FIFO_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_INPUT_FIFO_SW_RST_FIELD_MASK  0x00000800
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_INPUT_FIFO_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_INPUT_FIFO_SW_RST_FIELD_SHIFT 11
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_TM_FIFO_PTR_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_TM_FIFO_PTR_SW_RST_FIELD_MASK  0x00001000
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_TM_FIFO_PTR_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_TM_FIFO_PTR_SW_RST_FIELD_SHIFT 12
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_OUT_FIFO_SW_RST_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_OUT_FIFO_SW_RST_FIELD_MASK  0x00002000
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_OUT_FIFO_SW_RST_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_OUT_FIFO_SW_RST_FIELD_SHIFT 13
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_RESERVED0_FIELD_MASK  0xffffc000
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_RESERVED0_FIELD_WIDTH 18
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_PKTS_READ_CLEAR_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_PKTS_READ_CLEAR_ENABLE_FIELD_MASK  0x00000001
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_PKTS_READ_CLEAR_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_PKTS_READ_CLEAR_ENABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_BYTES_READ_CLEAR_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_BYTES_READ_CLEAR_ENABLE_FIELD_MASK  0x00000002
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_BYTES_READ_CLEAR_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_BYTES_READ_CLEAR_ENABLE_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_PKTS_SELECT_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_PKTS_SELECT_FIELD_MASK  0x00000004
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_PKTS_SELECT_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_PKTS_SELECT_FIELD_SHIFT 2
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_BYTES_SELECT_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_BYTES_SELECT_FIELD_MASK  0x00000008
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_BYTES_SELECT_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_BYTES_SELECT_FIELD_SHIFT 3
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_FREE_WITH_CONTEXT_LAST_SEARCH_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FREE_WITH_CONTEXT_LAST_SEARCH_FIELD_MASK  0x00000010
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FREE_WITH_CONTEXT_LAST_SEARCH_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FREE_WITH_CONTEXT_LAST_SEARCH_FIELD_SHIFT 4
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_WRED_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_WRED_DISABLE_FIELD_MASK  0x00000020
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_WRED_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_WRED_DISABLE_FIELD_SHIFT 5
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_DISABLE_FIELD_MASK  0x00000040
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_DISABLE_FIELD_SHIFT 6
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_BYTE_CONGESTION_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_BYTE_CONGESTION_DISABLE_FIELD_MASK  0x00000080
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_BYTE_CONGESTION_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_BYTE_CONGESTION_DISABLE_FIELD_SHIFT 7
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_OCCUPANCY_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_OCCUPANCY_DISABLE_FIELD_MASK  0x00000100
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_OCCUPANCY_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_OCCUPANCY_DISABLE_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_FPM_CONGESTION_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_FPM_CONGESTION_DISABLE_FIELD_MASK  0x00000200
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_FPM_CONGESTION_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_FPM_CONGESTION_DISABLE_FIELD_SHIFT 9
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_DISABLE_FIELD_MASK  0x00000400
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_DISABLE_FIELD_SHIFT 10
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_QUEUE_OCCUPANCY_DDR_COPY_DECISION_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QUEUE_OCCUPANCY_DDR_COPY_DECISION_DISABLE_FIELD_MASK  0x00000800
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QUEUE_OCCUPANCY_DDR_COPY_DECISION_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QUEUE_OCCUPANCY_DDR_COPY_DECISION_DISABLE_FIELD_SHIFT 11
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DDR_COPY_DECISION_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DDR_COPY_DECISION_DISABLE_FIELD_MASK  0x00001000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DDR_COPY_DECISION_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DDR_COPY_DECISION_DISABLE_FIELD_SHIFT 12
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DONT_SEND_MC_BIT_TO_BBH_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DONT_SEND_MC_BIT_TO_BBH_FIELD_MASK  0x00002000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DONT_SEND_MC_BIT_TO_BBH_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DONT_SEND_MC_BIT_TO_BBH_FIELD_SHIFT 13
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_CLOSE_AGGREGATION_ON_TIMEOUT_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_CLOSE_AGGREGATION_ON_TIMEOUT_DISABLE_FIELD_MASK  0x00004000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_CLOSE_AGGREGATION_ON_TIMEOUT_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_CLOSE_AGGREGATION_ON_TIMEOUT_DISABLE_FIELD_SHIFT 14
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_CONGESTION_BUF_RELEASE_MECHANISM_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_CONGESTION_BUF_RELEASE_MECHANISM_DISABLE_FIELD_MASK  0x00008000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_CONGESTION_BUF_RELEASE_MECHANISM_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_CONGESTION_BUF_RELEASE_MECHANISM_DISABLE_FIELD_SHIFT 15
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_BUFFER_GLOBAL_RES_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_BUFFER_GLOBAL_RES_ENABLE_FIELD_MASK  0x00010000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_BUFFER_GLOBAL_RES_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_BUFFER_GLOBAL_RES_ENABLE_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_PRESERVE_PD_WITH_FPM_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_PRESERVE_PD_WITH_FPM_FIELD_MASK  0x00020000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_PRESERVE_PD_WITH_FPM_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_PRESERVE_PD_WITH_FPM_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_RESIDUE_PER_QUEUE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_RESIDUE_PER_QUEUE_FIELD_MASK  0x00040000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_RESIDUE_PER_QUEUE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_RESIDUE_PER_QUEUE_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_GHOST_RPT_UPDATE_AFTER_CLOSE_AGG_EN_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GHOST_RPT_UPDATE_AFTER_CLOSE_AGG_EN_FIELD_MASK  0x00080000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GHOST_RPT_UPDATE_AFTER_CLOSE_AGG_EN_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GHOST_RPT_UPDATE_AFTER_CLOSE_AGG_EN_FIELD_SHIFT 19
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_FLOW_CTRL_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_FLOW_CTRL_DISABLE_FIELD_MASK  0x00100000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_FLOW_CTRL_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_FLOW_CTRL_DISABLE_FIELD_SHIFT 20
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_WRITE_MULTI_SLAVE_EN_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_WRITE_MULTI_SLAVE_EN_FIELD_MASK  0x00200000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_WRITE_MULTI_SLAVE_EN_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_WRITE_MULTI_SLAVE_EN_FIELD_SHIFT 21
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_AGG_PRIORITY_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_AGG_PRIORITY_FIELD_MASK  0x00400000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_AGG_PRIORITY_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_AGG_PRIORITY_FIELD_SHIFT 22
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DROP_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DROP_DISABLE_FIELD_MASK  0x00800000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DROP_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DROP_DISABLE_FIELD_SHIFT 23
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_DDR_WRITE_ALIGNMENT_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_DDR_WRITE_ALIGNMENT_FIELD_MASK  0x01000000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_DDR_WRITE_ALIGNMENT_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_DDR_WRITE_ALIGNMENT_FIELD_SHIFT 24
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_EXCLUSIVE_DONT_DROP_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_EXCLUSIVE_DONT_DROP_FIELD_MASK  0x02000000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_EXCLUSIVE_DONT_DROP_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_EXCLUSIVE_DONT_DROP_FIELD_SHIFT 25
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DQMOL_JIRA_973_FIX_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DQMOL_JIRA_973_FIX_ENABLE_FIELD_MASK  0x04000000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DQMOL_JIRA_973_FIX_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DQMOL_JIRA_973_FIX_ENABLE_FIELD_SHIFT 26
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_GPON_DBR_CEIL_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GPON_DBR_CEIL_FIELD_MASK  0x08000000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GPON_DBR_CEIL_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GPON_DBR_CEIL_FIELD_SHIFT 27
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_WRED_DROPS_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_WRED_DROPS_FIELD_MASK  0x10000000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_WRED_DROPS_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_WRED_DROPS_FIELD_SHIFT 28
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_RESERVED0_FIELD_MASK  0xe0000000
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_RESERVED0_FIELD_WIDTH 3
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_RESERVED0_FIELD_SHIFT 29
+
+extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_FPM_POOL_BP_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_POOL_BP_ENABLE_FIELD_MASK  0x00000001
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_POOL_BP_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_POOL_BP_ENABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_FPM_CONGESTION_BP_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_CONGESTION_BP_ENABLE_FIELD_MASK  0x00000002
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_CONGESTION_BP_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_CONGESTION_BP_ENABLE_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED0_FIELD_MASK  0x0000007c
+#define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED0_FIELD_WIDTH 5
+#define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_GRANULARITY_FIELD;
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_GRANULARITY_FIELD_MASK  0x00000080
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_GRANULARITY_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_GRANULARITY_FIELD_SHIFT 7
+
+extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_FIELD;
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_FIELD_MASK  0x00000300
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_FIELD_WIDTH 2
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_RESERVED1_FIELD;
+#define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED1_FIELD_MASK  0x0000fc00
+#define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED1_FIELD_WIDTH 6
+#define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED1_FIELD_SHIFT 10
+
+extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_FIELD;
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_FIELD_MASK  0x007f0000
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_FIELD_WIDTH 7
+#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_RESERVED2_FIELD;
+#define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED2_FIELD_MASK  0xff800000
+#define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED2_FIELD_WIDTH 9
+#define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED2_FIELD_SHIFT 23
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_DDR_BYTE_CONGESTION_DROP_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_DDR_BYTE_CONGESTION_DROP_ENABLE_FIELD_MASK  0x00000001
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_DDR_BYTE_CONGESTION_DROP_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_DDR_BYTE_CONGESTION_DROP_ENABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_RESERVED0_FIELD_MASK  0xfffffffe
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_RESERVED0_FIELD_WIDTH 31
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_DDR_BYTES_LOWER_THR_FIELD;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_DDR_BYTES_LOWER_THR_FIELD_MASK  0x3fffffff
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_DDR_BYTES_LOWER_THR_FIELD_WIDTH 30
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_DDR_BYTES_LOWER_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_RESERVED0_FIELD_MASK  0xc0000000
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_RESERVED0_FIELD_WIDTH 2
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_FIELD;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_FIELD_MASK  0x3fffffff
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_FIELD_WIDTH 30
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_RESERVED0_FIELD_MASK  0xc0000000
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_RESERVED0_FIELD_WIDTH 2
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_FIELD;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_FIELD_MASK  0x3fffffff
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_FIELD_WIDTH 30
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_RESERVED0_FIELD_MASK  0xc0000000
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_RESERVED0_FIELD_WIDTH 2
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PD_CONGESTION_DROP_ENABLE_FIELD;
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PD_CONGESTION_DROP_ENABLE_FIELD_MASK  0x00000001
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PD_CONGESTION_DROP_ENABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PD_CONGESTION_DROP_ENABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED0_FIELD_MASK  0x000000fe
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED0_FIELD_WIDTH 7
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_FIELD;
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_FIELD_MASK  0x0000ff00
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_FIELD_WIDTH 8
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_FIELD;
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_FIELD_MASK  0x00ff0000
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_FIELD_WIDTH 8
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED1_FIELD;
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED1_FIELD_MASK  0xff000000
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED1_FIELD_WIDTH 8
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED1_FIELD_SHIFT 24
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_FIELD;
+#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_FIELD_MASK  0x0fffffff
+#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_FIELD_WIDTH 28
+#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_RESERVED0_FIELD_MASK  0xf0000000
+#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_RESERVED0_FIELD_WIDTH 4
+#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_FIELD;
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_FIELD_MASK  0x000001ff
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_FIELD_WIDTH 9
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED0_FIELD_MASK  0x0000fe00
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED0_FIELD_WIDTH 7
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_EN_FIELD;
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_EN_FIELD_MASK  0x00010000
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_EN_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED1_FIELD;
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED1_FIELD_MASK  0xfffe0000
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED1_FIELD_WIDTH 15
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_FIELD;
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_FIELD_MASK  0x000003ff
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_FIELD_WIDTH 10
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED0_FIELD_MASK  0x0000fc00
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED0_FIELD_WIDTH 6
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_FIELD;
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_FIELD_MASK  0x00030000
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_FIELD_WIDTH 2
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED1_FIELD;
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED1_FIELD_MASK  0xfffc0000
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED1_FIELD_WIDTH 14
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED1_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_FIELD;
+#define QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_FIELD_MASK  0xffffffff
+#define QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_FIELD_WIDTH 32
+#define QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_FIELD;
+#define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_FIELD_MASK  0xffffffff
+#define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_FIELD_WIDTH 32
+#define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_FIELD;
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_FIELD_MASK  0x000007ff
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_FIELD_WIDTH 11
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED0_FIELD_MASK  0x0000f800
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED0_FIELD_WIDTH 5
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_FIELD;
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_FIELD_MASK  0x07ff0000
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_FIELD_WIDTH 11
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED1_FIELD;
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED1_FIELD_MASK  0xf8000000
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED1_FIELD_WIDTH 5
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED1_FIELD_SHIFT 27
+
+extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_LINE_RATE_FIELD;
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_LINE_RATE_FIELD_MASK  0x00000001
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_LINE_RATE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_LINE_RATE_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_CRC_ADD_DISABLE_FIELD;
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_CRC_ADD_DISABLE_FIELD_MASK  0x00000002
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_CRC_ADD_DISABLE_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_CRC_ADD_DISABLE_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_EN_FIELD;
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_EN_FIELD_MASK  0x00000004
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_EN_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_EN_FIELD_SHIFT 2
+
+extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_FIELD;
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_FIELD_MASK  0x000007f8
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_FIELD_WIDTH 8
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_FIELD_SHIFT 3
+
+extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED0_FIELD_MASK  0x0000f800
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED0_FIELD_WIDTH 5
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_FIELD;
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_FIELD_MASK  0x07ff0000
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_FIELD_WIDTH 11
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED1_FIELD;
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED1_FIELD_MASK  0xf8000000
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED1_FIELD_WIDTH 5
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED1_FIELD_SHIFT 27
+
+extern const ru_field_rec QM_GLOBAL_CFG_DQM_FULL_Q_FULL_FIELD;
+#define QM_GLOBAL_CFG_DQM_FULL_Q_FULL_FIELD_MASK  0xffffffff
+#define QM_GLOBAL_CFG_DQM_FULL_Q_FULL_FIELD_WIDTH 32
+#define QM_GLOBAL_CFG_DQM_FULL_Q_FULL_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_FIELD;
+#define QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_FIELD_MASK  0xffffffff
+#define QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_FIELD_WIDTH 32
+#define QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_FIELD;
+#define QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_FIELD_MASK  0xffffffff
+#define QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_FIELD_WIDTH 32
+#define QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_FIELD;
+#define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_FIELD_MASK  0xffffffff
+#define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_FIELD_WIDTH 32
+#define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_FIELD;
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_FIELD_MASK  0x00000007
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_FIELD_WIDTH 3
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_FIELD;
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_FIELD_MASK  0x00000038
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_FIELD_WIDTH 3
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_FIELD_SHIFT 3
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PD_OCCUPANCY_EN_FIELD;
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PD_OCCUPANCY_EN_FIELD_MASK  0x00000040
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PD_OCCUPANCY_EN_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PD_OCCUPANCY_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PD_OCCUPANCY_VALUE_FIELD;
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PD_OCCUPANCY_VALUE_FIELD_MASK  0x00000780
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PD_OCCUPANCY_VALUE_FIELD_WIDTH 4
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PD_OCCUPANCY_VALUE_FIELD_SHIFT 7
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED0_FIELD_MASK  0xfffff800
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED0_FIELD_WIDTH 21
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_FIELD;
+#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_FIELD_MASK  0x0000ffff
+#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_FIELD_WIDTH 16
+#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_RESERVED0_FIELD_MASK  0xffff0000
+#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_RESERVED0_FIELD_WIDTH 16
+#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_FIELD;
+#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_FIELD_MASK  0x000001ff
+#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_FIELD_WIDTH 9
+#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_FLUSH_EN_FIELD;
+#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_FLUSH_EN_FIELD_MASK  0x00000200
+#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_FLUSH_EN_FIELD_WIDTH 1
+#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_FLUSH_EN_FIELD_SHIFT 9
+
+extern const ru_field_rec QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_RESERVED0_FIELD_MASK  0xfffffc00
+#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_RESERVED0_FIELD_WIDTH 22
+#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_SPARE_ROOM_DDR_HEADROOM_FIELD;
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_DDR_HEADROOM_FIELD_MASK  0x000007ff
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_DDR_HEADROOM_FIELD_WIDTH 11
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_DDR_HEADROOM_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_SPARE_ROOM_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_RESERVED0_FIELD_MASK  0x0000f800
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_RESERVED0_FIELD_WIDTH 5
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_SPARE_ROOM_DDR_TAILROOM_FIELD;
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_DDR_TAILROOM_FIELD_MASK  0x07ff0000
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_DDR_TAILROOM_FIELD_WIDTH 11
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_DDR_TAILROOM_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_GLOBAL_CFG_DDR_SPARE_ROOM_RESERVED1_FIELD;
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_RESERVED1_FIELD_MASK  0xf8000000
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_RESERVED1_FIELD_WIDTH 5
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_RESERVED1_FIELD_SHIFT 27
+
+extern const ru_field_rec QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_DUMMY_PROFILE_0_FIELD;
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_DUMMY_PROFILE_0_FIELD_MASK  0x00000003
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_DUMMY_PROFILE_0_FIELD_WIDTH 2
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_DUMMY_PROFILE_0_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_RESERVED0_FIELD_MASK  0x0000fffc
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_RESERVED0_FIELD_WIDTH 14
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_DUMMY_PROFILE_1_FIELD;
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_DUMMY_PROFILE_1_FIELD_MASK  0x00030000
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_DUMMY_PROFILE_1_FIELD_WIDTH 2
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_DUMMY_PROFILE_1_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_RESERVED1_FIELD;
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_RESERVED1_FIELD_MASK  0xfffc0000
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_RESERVED1_FIELD_WIDTH 14
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_RESERVED1_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_FPM_POOLS_THR_FPM_LOWER_THR_FIELD;
+#define QM_FPM_POOLS_THR_FPM_LOWER_THR_FIELD_MASK  0x0000007f
+#define QM_FPM_POOLS_THR_FPM_LOWER_THR_FIELD_WIDTH 7
+#define QM_FPM_POOLS_THR_FPM_LOWER_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_POOLS_THR_RESERVED0_FIELD;
+#define QM_FPM_POOLS_THR_RESERVED0_FIELD_MASK  0x00000080
+#define QM_FPM_POOLS_THR_RESERVED0_FIELD_WIDTH 1
+#define QM_FPM_POOLS_THR_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec QM_FPM_POOLS_THR_FPM_HIGHER_THR_FIELD;
+#define QM_FPM_POOLS_THR_FPM_HIGHER_THR_FIELD_MASK  0x00007f00
+#define QM_FPM_POOLS_THR_FPM_HIGHER_THR_FIELD_WIDTH 7
+#define QM_FPM_POOLS_THR_FPM_HIGHER_THR_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_FPM_POOLS_THR_RESERVED1_FIELD;
+#define QM_FPM_POOLS_THR_RESERVED1_FIELD_MASK  0xffff8000
+#define QM_FPM_POOLS_THR_RESERVED1_FIELD_WIDTH 17
+#define QM_FPM_POOLS_THR_RESERVED1_FIELD_SHIFT 15
+
+extern const ru_field_rec QM_FPM_USR_GRP_LOWER_THR_FPM_GRP_LOWER_THR_FIELD;
+#define QM_FPM_USR_GRP_LOWER_THR_FPM_GRP_LOWER_THR_FIELD_MASK  0x0000ffff
+#define QM_FPM_USR_GRP_LOWER_THR_FPM_GRP_LOWER_THR_FIELD_WIDTH 16
+#define QM_FPM_USR_GRP_LOWER_THR_FPM_GRP_LOWER_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_USR_GRP_LOWER_THR_RESERVED0_FIELD;
+#define QM_FPM_USR_GRP_LOWER_THR_RESERVED0_FIELD_MASK  0xffff0000
+#define QM_FPM_USR_GRP_LOWER_THR_RESERVED0_FIELD_WIDTH 16
+#define QM_FPM_USR_GRP_LOWER_THR_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_FIELD;
+#define QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_FIELD_MASK  0x0000ffff
+#define QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_FIELD_WIDTH 16
+#define QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_USR_GRP_MID_THR_RESERVED0_FIELD;
+#define QM_FPM_USR_GRP_MID_THR_RESERVED0_FIELD_MASK  0xffff0000
+#define QM_FPM_USR_GRP_MID_THR_RESERVED0_FIELD_WIDTH 16
+#define QM_FPM_USR_GRP_MID_THR_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_FIELD;
+#define QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_FIELD_MASK  0x0000ffff
+#define QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_FIELD_WIDTH 16
+#define QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_USR_GRP_HIGHER_THR_RESERVED0_FIELD;
+#define QM_FPM_USR_GRP_HIGHER_THR_RESERVED0_FIELD_MASK  0xffff0000
+#define QM_FPM_USR_GRP_HIGHER_THR_RESERVED0_FIELD_WIDTH 16
+#define QM_FPM_USR_GRP_HIGHER_THR_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_FPM_USR_GRP_CNT_FPM_UG_CNT_FIELD;
+#define QM_FPM_USR_GRP_CNT_FPM_UG_CNT_FIELD_MASK  0x0000ffff
+#define QM_FPM_USR_GRP_CNT_FPM_UG_CNT_FIELD_WIDTH 16
+#define QM_FPM_USR_GRP_CNT_FPM_UG_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_USR_GRP_CNT_RESERVED0_FIELD;
+#define QM_FPM_USR_GRP_CNT_RESERVED0_FIELD_MASK  0xffff0000
+#define QM_FPM_USR_GRP_CNT_RESERVED0_FIELD_WIDTH 16
+#define QM_FPM_USR_GRP_CNT_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_FIELD;
+#define QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_FIELD_MASK  0x0000003f
+#define QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_FIELD_WIDTH 6
+#define QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RESERVED0_FIELD;
+#define QM_RUNNER_GRP_RNR_CONFIG_RESERVED0_FIELD_MASK  0x000000c0
+#define QM_RUNNER_GRP_RNR_CONFIG_RESERVED0_FIELD_WIDTH 2
+#define QM_RUNNER_GRP_RNR_CONFIG_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_FIELD;
+#define QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_FIELD_MASK  0x00000f00
+#define QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_FIELD_WIDTH 4
+#define QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RESERVED1_FIELD;
+#define QM_RUNNER_GRP_RNR_CONFIG_RESERVED1_FIELD_MASK  0x0000f000
+#define QM_RUNNER_GRP_RNR_CONFIG_RESERVED1_FIELD_WIDTH 4
+#define QM_RUNNER_GRP_RNR_CONFIG_RESERVED1_FIELD_SHIFT 12
+
+extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RNR_ENABLE_FIELD;
+#define QM_RUNNER_GRP_RNR_CONFIG_RNR_ENABLE_FIELD_MASK  0x00010000
+#define QM_RUNNER_GRP_RNR_CONFIG_RNR_ENABLE_FIELD_WIDTH 1
+#define QM_RUNNER_GRP_RNR_CONFIG_RNR_ENABLE_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RESERVED2_FIELD;
+#define QM_RUNNER_GRP_RNR_CONFIG_RESERVED2_FIELD_MASK  0xfffe0000
+#define QM_RUNNER_GRP_RNR_CONFIG_RESERVED2_FIELD_WIDTH 15
+#define QM_RUNNER_GRP_RNR_CONFIG_RESERVED2_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_FIELD;
+#define QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_FIELD_MASK  0x000001ff
+#define QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_FIELD_WIDTH 9
+#define QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED0_FIELD;
+#define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED0_FIELD_MASK  0x0000fe00
+#define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED0_FIELD_WIDTH 7
+#define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_FIELD;
+#define QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_FIELD_MASK  0x01ff0000
+#define QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_FIELD_WIDTH 9
+#define QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED1_FIELD;
+#define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED1_FIELD_MASK  0xfe000000
+#define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED1_FIELD_WIDTH 7
+#define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED0_FIELD;
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED0_FIELD_MASK  0x00000007
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED0_FIELD_WIDTH 3
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED0_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_FIELD;
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_FIELD_MASK  0x00003ff8
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_FIELD_WIDTH 11
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_FIELD_SHIFT 3
+
+extern const ru_field_rec QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED1_FIELD;
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED1_FIELD_MASK  0x0000c000
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED1_FIELD_WIDTH 2
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_FIELD;
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_FIELD_MASK  0x00030000
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_FIELD_WIDTH 2
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED2_FIELD;
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED2_FIELD_MASK  0xfffc0000
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED2_FIELD_WIDTH 14
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED2_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED0_FIELD;
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED0_FIELD_MASK  0x00000007
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED0_FIELD_WIDTH 3
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED0_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_FIELD;
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_FIELD_MASK  0x00003ff8
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_FIELD_WIDTH 11
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_FIELD_SHIFT 3
+
+extern const ru_field_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED1_FIELD;
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED1_FIELD_MASK  0x0000c000
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED1_FIELD_WIDTH 2
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_FIELD;
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_FIELD_MASK  0x00070000
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_FIELD_WIDTH 3
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED2_FIELD;
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED2_FIELD_MASK  0xfff80000
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED2_FIELD_WIDTH 13
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED2_FIELD_SHIFT 19
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_DQM_POP_ON_EMPTY_FIELD;
+#define QM_INTR_CTRL_ISR_QM_DQM_POP_ON_EMPTY_FIELD_MASK  0x00000001
+#define QM_INTR_CTRL_ISR_QM_DQM_POP_ON_EMPTY_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_DQM_POP_ON_EMPTY_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_DQM_PUSH_ON_FULL_FIELD;
+#define QM_INTR_CTRL_ISR_QM_DQM_PUSH_ON_FULL_FIELD_MASK  0x00000002
+#define QM_INTR_CTRL_ISR_QM_DQM_PUSH_ON_FULL_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_DQM_PUSH_ON_FULL_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_CPU_POP_ON_EMPTY_FIELD;
+#define QM_INTR_CTRL_ISR_QM_CPU_POP_ON_EMPTY_FIELD_MASK  0x00000004
+#define QM_INTR_CTRL_ISR_QM_CPU_POP_ON_EMPTY_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_CPU_POP_ON_EMPTY_FIELD_SHIFT 2
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_CPU_PUSH_ON_FULL_FIELD;
+#define QM_INTR_CTRL_ISR_QM_CPU_PUSH_ON_FULL_FIELD_MASK  0x00000008
+#define QM_INTR_CTRL_ISR_QM_CPU_PUSH_ON_FULL_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_CPU_PUSH_ON_FULL_FIELD_SHIFT 3
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_NORMAL_QUEUE_PD_NO_CREDIT_FIELD;
+#define QM_INTR_CTRL_ISR_QM_NORMAL_QUEUE_PD_NO_CREDIT_FIELD_MASK  0x00000010
+#define QM_INTR_CTRL_ISR_QM_NORMAL_QUEUE_PD_NO_CREDIT_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_NORMAL_QUEUE_PD_NO_CREDIT_FIELD_SHIFT 4
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_NON_DELAYED_QUEUE_PD_NO_CREDIT_FIELD;
+#define QM_INTR_CTRL_ISR_QM_NON_DELAYED_QUEUE_PD_NO_CREDIT_FIELD_MASK  0x00000020
+#define QM_INTR_CTRL_ISR_QM_NON_DELAYED_QUEUE_PD_NO_CREDIT_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_NON_DELAYED_QUEUE_PD_NO_CREDIT_FIELD_SHIFT 5
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_NON_VALID_QUEUE_FIELD;
+#define QM_INTR_CTRL_ISR_QM_NON_VALID_QUEUE_FIELD_MASK  0x00000040
+#define QM_INTR_CTRL_ISR_QM_NON_VALID_QUEUE_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_NON_VALID_QUEUE_FIELD_SHIFT 6
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_AGG_COHERENT_INCONSISTENCY_FIELD;
+#define QM_INTR_CTRL_ISR_QM_AGG_COHERENT_INCONSISTENCY_FIELD_MASK  0x00000080
+#define QM_INTR_CTRL_ISR_QM_AGG_COHERENT_INCONSISTENCY_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_AGG_COHERENT_INCONSISTENCY_FIELD_SHIFT 7
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FORCE_COPY_ON_NON_DELAYED_FIELD;
+#define QM_INTR_CTRL_ISR_QM_FORCE_COPY_ON_NON_DELAYED_FIELD_MASK  0x00000100
+#define QM_INTR_CTRL_ISR_QM_FORCE_COPY_ON_NON_DELAYED_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_FORCE_COPY_ON_NON_DELAYED_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FPM_POOL_SIZE_NONEXISTENT_FIELD;
+#define QM_INTR_CTRL_ISR_QM_FPM_POOL_SIZE_NONEXISTENT_FIELD_MASK  0x00000200
+#define QM_INTR_CTRL_ISR_QM_FPM_POOL_SIZE_NONEXISTENT_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_FPM_POOL_SIZE_NONEXISTENT_FIELD_SHIFT 9
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_TARGET_MEM_ABS_CONTRADICTION_FIELD;
+#define QM_INTR_CTRL_ISR_QM_TARGET_MEM_ABS_CONTRADICTION_FIELD_MASK  0x00000400
+#define QM_INTR_CTRL_ISR_QM_TARGET_MEM_ABS_CONTRADICTION_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_TARGET_MEM_ABS_CONTRADICTION_FIELD_SHIFT 10
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_1588_DROP_FIELD;
+#define QM_INTR_CTRL_ISR_QM_1588_DROP_FIELD_MASK  0x00000800
+#define QM_INTR_CTRL_ISR_QM_1588_DROP_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_1588_DROP_FIELD_SHIFT 11
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_1588_MULTICAST_CONTRADICTION_FIELD;
+#define QM_INTR_CTRL_ISR_QM_1588_MULTICAST_CONTRADICTION_FIELD_MASK  0x00001000
+#define QM_INTR_CTRL_ISR_QM_1588_MULTICAST_CONTRADICTION_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_1588_MULTICAST_CONTRADICTION_FIELD_SHIFT 12
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_BYTE_DROP_CNT_OVERRUN_FIELD;
+#define QM_INTR_CTRL_ISR_QM_BYTE_DROP_CNT_OVERRUN_FIELD_MASK  0x00002000
+#define QM_INTR_CTRL_ISR_QM_BYTE_DROP_CNT_OVERRUN_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_BYTE_DROP_CNT_OVERRUN_FIELD_SHIFT 13
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_PKT_DROP_CNT_OVERRUN_FIELD;
+#define QM_INTR_CTRL_ISR_QM_PKT_DROP_CNT_OVERRUN_FIELD_MASK  0x00004000
+#define QM_INTR_CTRL_ISR_QM_PKT_DROP_CNT_OVERRUN_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_PKT_DROP_CNT_OVERRUN_FIELD_SHIFT 14
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_TOTAL_BYTE_CNT_UNDERRUN_FIELD;
+#define QM_INTR_CTRL_ISR_QM_TOTAL_BYTE_CNT_UNDERRUN_FIELD_MASK  0x00008000
+#define QM_INTR_CTRL_ISR_QM_TOTAL_BYTE_CNT_UNDERRUN_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_TOTAL_BYTE_CNT_UNDERRUN_FIELD_SHIFT 15
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_TOTAL_PKT_CNT_UNDERRUN_FIELD;
+#define QM_INTR_CTRL_ISR_QM_TOTAL_PKT_CNT_UNDERRUN_FIELD_MASK  0x00010000
+#define QM_INTR_CTRL_ISR_QM_TOTAL_PKT_CNT_UNDERRUN_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_TOTAL_PKT_CNT_UNDERRUN_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FPM_UG0_UNDERRUN_FIELD;
+#define QM_INTR_CTRL_ISR_QM_FPM_UG0_UNDERRUN_FIELD_MASK  0x00020000
+#define QM_INTR_CTRL_ISR_QM_FPM_UG0_UNDERRUN_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_FPM_UG0_UNDERRUN_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FPM_UG1_UNDERRUN_FIELD;
+#define QM_INTR_CTRL_ISR_QM_FPM_UG1_UNDERRUN_FIELD_MASK  0x00040000
+#define QM_INTR_CTRL_ISR_QM_FPM_UG1_UNDERRUN_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_FPM_UG1_UNDERRUN_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FPM_UG2_UNDERRUN_FIELD;
+#define QM_INTR_CTRL_ISR_QM_FPM_UG2_UNDERRUN_FIELD_MASK  0x00080000
+#define QM_INTR_CTRL_ISR_QM_FPM_UG2_UNDERRUN_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_FPM_UG2_UNDERRUN_FIELD_SHIFT 19
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FPM_UG3_UNDERRUN_FIELD;
+#define QM_INTR_CTRL_ISR_QM_FPM_UG3_UNDERRUN_FIELD_MASK  0x00100000
+#define QM_INTR_CTRL_ISR_QM_FPM_UG3_UNDERRUN_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_FPM_UG3_UNDERRUN_FIELD_SHIFT 20
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_TIMER_WRAPAROUND_FIELD;
+#define QM_INTR_CTRL_ISR_QM_TIMER_WRAPAROUND_FIELD_MASK  0x00200000
+#define QM_INTR_CTRL_ISR_QM_TIMER_WRAPAROUND_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_TIMER_WRAPAROUND_FIELD_SHIFT 21
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_QM_COPY_PLEN_ZERO_FIELD;
+#define QM_INTR_CTRL_ISR_QM_COPY_PLEN_ZERO_FIELD_MASK  0x00400000
+#define QM_INTR_CTRL_ISR_QM_COPY_PLEN_ZERO_FIELD_WIDTH 1
+#define QM_INTR_CTRL_ISR_QM_COPY_PLEN_ZERO_FIELD_SHIFT 22
+
+extern const ru_field_rec QM_INTR_CTRL_ISR_RESERVED0_FIELD;
+#define QM_INTR_CTRL_ISR_RESERVED0_FIELD_MASK  0xff800000
+#define QM_INTR_CTRL_ISR_RESERVED0_FIELD_WIDTH 9
+#define QM_INTR_CTRL_ISR_RESERVED0_FIELD_SHIFT 23
+
+extern const ru_field_rec QM_INTR_CTRL_ISM_ISM_FIELD;
+#define QM_INTR_CTRL_ISM_ISM_FIELD_MASK  0x007fffff
+#define QM_INTR_CTRL_ISM_ISM_FIELD_WIDTH 23
+#define QM_INTR_CTRL_ISM_ISM_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_INTR_CTRL_ISM_RESERVED0_FIELD;
+#define QM_INTR_CTRL_ISM_RESERVED0_FIELD_MASK  0xff800000
+#define QM_INTR_CTRL_ISM_RESERVED0_FIELD_WIDTH 9
+#define QM_INTR_CTRL_ISM_RESERVED0_FIELD_SHIFT 23
+
+extern const ru_field_rec QM_INTR_CTRL_IER_IEM_FIELD;
+#define QM_INTR_CTRL_IER_IEM_FIELD_MASK  0x007fffff
+#define QM_INTR_CTRL_IER_IEM_FIELD_WIDTH 23
+#define QM_INTR_CTRL_IER_IEM_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_INTR_CTRL_IER_RESERVED0_FIELD;
+#define QM_INTR_CTRL_IER_RESERVED0_FIELD_MASK  0xff800000
+#define QM_INTR_CTRL_IER_RESERVED0_FIELD_WIDTH 9
+#define QM_INTR_CTRL_IER_RESERVED0_FIELD_SHIFT 23
+
+extern const ru_field_rec QM_INTR_CTRL_ITR_IST_FIELD;
+#define QM_INTR_CTRL_ITR_IST_FIELD_MASK  0x007fffff
+#define QM_INTR_CTRL_ITR_IST_FIELD_WIDTH 23
+#define QM_INTR_CTRL_ITR_IST_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_INTR_CTRL_ITR_RESERVED0_FIELD;
+#define QM_INTR_CTRL_ITR_RESERVED0_FIELD_MASK  0xff800000
+#define QM_INTR_CTRL_ITR_RESERVED0_FIELD_WIDTH 9
+#define QM_INTR_CTRL_ITR_RESERVED0_FIELD_SHIFT 23
+
+extern const ru_field_rec QM_CLK_GATE_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD;
+#define QM_CLK_GATE_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK  0x00000001
+#define QM_CLK_GATE_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1
+#define QM_CLK_GATE_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED0_FIELD;
+#define QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK  0x000000fe
+#define QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7
+#define QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_CLK_GATE_CLK_GATE_CNTRL_TIMER_VAL_FIELD;
+#define QM_CLK_GATE_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK  0x0000ff00
+#define QM_CLK_GATE_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8
+#define QM_CLK_GATE_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD;
+#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK  0x00010000
+#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1
+#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED1_FIELD;
+#define QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK  0x000e0000
+#define QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3
+#define QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD;
+#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK  0x00700000
+#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3
+#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20
+
+extern const ru_field_rec QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED2_FIELD;
+#define QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK  0x00800000
+#define QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1
+#define QM_CLK_GATE_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23
+
+extern const ru_field_rec QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD;
+#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK  0xff000000
+#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8
+#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_FIELD_MASK  0x000001ff
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_FIELD_WIDTH 9
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED0_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED0_FIELD_MASK  0x0000fe00
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED0_FIELD_WIDTH 7
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_FIELD_MASK  0x00030000
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_FIELD_WIDTH 2
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED1_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED1_FIELD_MASK  0x00fc0000
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED1_FIELD_WIDTH 6
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED1_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_DONE_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_DONE_FIELD_MASK  0x01000000
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_DONE_FIELD_WIDTH 1
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_DONE_FIELD_SHIFT 24
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_ERROR_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_ERROR_FIELD_MASK  0x02000000
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_ERROR_FIELD_WIDTH 1
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_ERROR_FIELD_SHIFT 25
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED2_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED2_FIELD_MASK  0xfc000000
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED2_FIELD_WIDTH 6
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED2_FIELD_SHIFT 26
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_FIELD_MASK  0xffffffff
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_FIELD_WIDTH 32
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_FIELD_MASK  0xffffffff
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_FIELD_WIDTH 32
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_FIELD_MASK  0xffffffff
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_FIELD_WIDTH 32
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_FIELD_MASK  0xffffffff
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_FIELD_WIDTH 32
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_FIELD_MASK  0xffffffff
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_FIELD_WIDTH 32
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_FIELD_MASK  0xffffffff
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_FIELD_WIDTH 32
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_FIELD_MASK  0xffffffff
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_FIELD_WIDTH 32
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_FIELD;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_FIELD_MASK  0xffffffff
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_FIELD_WIDTH 32
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_FIELD_MASK  0x0000000f
+#define QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_FIELD_WIDTH 4
+#define QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_FIELD_MASK  0x00000070
+#define QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_FIELD_WIDTH 3
+#define QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_FIELD_SHIFT 4
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_COPY_TO_DDR_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_COPY_TO_DDR_FIELD_MASK  0x00000080
+#define QM_QUEUE_CONTEXT_CONTEXT_COPY_TO_DDR_FIELD_WIDTH 1
+#define QM_QUEUE_CONTEXT_CONTEXT_COPY_TO_DDR_FIELD_SHIFT 7
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_DDR_COPY_DISABLE_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_DDR_COPY_DISABLE_FIELD_MASK  0x00000100
+#define QM_QUEUE_CONTEXT_CONTEXT_DDR_COPY_DISABLE_FIELD_WIDTH 1
+#define QM_QUEUE_CONTEXT_CONTEXT_DDR_COPY_DISABLE_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_AGGREGATION_DISABLE_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_AGGREGATION_DISABLE_FIELD_MASK  0x00000200
+#define QM_QUEUE_CONTEXT_CONTEXT_AGGREGATION_DISABLE_FIELD_WIDTH 1
+#define QM_QUEUE_CONTEXT_CONTEXT_AGGREGATION_DISABLE_FIELD_SHIFT 9
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_FIELD_MASK  0x00001c00
+#define QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_FIELD_WIDTH 3
+#define QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_FIELD_SHIFT 10
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_EXCLUSIVE_PRIORITY_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_EXCLUSIVE_PRIORITY_FIELD_MASK  0x00002000
+#define QM_QUEUE_CONTEXT_CONTEXT_EXCLUSIVE_PRIORITY_FIELD_WIDTH 1
+#define QM_QUEUE_CONTEXT_CONTEXT_EXCLUSIVE_PRIORITY_FIELD_SHIFT 13
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_Q_802_1AE_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_Q_802_1AE_FIELD_MASK  0x00004000
+#define QM_QUEUE_CONTEXT_CONTEXT_Q_802_1AE_FIELD_WIDTH 1
+#define QM_QUEUE_CONTEXT_CONTEXT_Q_802_1AE_FIELD_SHIFT 14
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_SCI_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_SCI_FIELD_MASK  0x00008000
+#define QM_QUEUE_CONTEXT_CONTEXT_SCI_FIELD_WIDTH 1
+#define QM_QUEUE_CONTEXT_CONTEXT_SCI_FIELD_SHIFT 15
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_FEC_ENABLE_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_FEC_ENABLE_FIELD_MASK  0x00010000
+#define QM_QUEUE_CONTEXT_CONTEXT_FEC_ENABLE_FIELD_WIDTH 1
+#define QM_QUEUE_CONTEXT_CONTEXT_FEC_ENABLE_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_FIELD_MASK  0x000e0000
+#define QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_FIELD_WIDTH 3
+#define QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_SPARE_ROOM_0_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_SPARE_ROOM_0_FIELD_MASK  0x00300000
+#define QM_QUEUE_CONTEXT_CONTEXT_SPARE_ROOM_0_FIELD_WIDTH 2
+#define QM_QUEUE_CONTEXT_CONTEXT_SPARE_ROOM_0_FIELD_SHIFT 20
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_SPARE_ROOM_1_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_SPARE_ROOM_1_FIELD_MASK  0x00c00000
+#define QM_QUEUE_CONTEXT_CONTEXT_SPARE_ROOM_1_FIELD_WIDTH 2
+#define QM_QUEUE_CONTEXT_CONTEXT_SPARE_ROOM_1_FIELD_SHIFT 22
+
+extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_RESERVED0_FIELD;
+#define QM_QUEUE_CONTEXT_CONTEXT_RESERVED0_FIELD_MASK  0xff000000
+#define QM_QUEUE_CONTEXT_CONTEXT_RESERVED0_FIELD_WIDTH 8
+#define QM_QUEUE_CONTEXT_CONTEXT_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_FIELD;
+#define QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_FIELD_MASK  0x00ffffff
+#define QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_FIELD_WIDTH 24
+#define QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_0_FLW_CTRL_EN_FIELD;
+#define QM_WRED_PROFILE_COLOR_MIN_THR_0_FLW_CTRL_EN_FIELD_MASK  0x01000000
+#define QM_WRED_PROFILE_COLOR_MIN_THR_0_FLW_CTRL_EN_FIELD_WIDTH 1
+#define QM_WRED_PROFILE_COLOR_MIN_THR_0_FLW_CTRL_EN_FIELD_SHIFT 24
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_0_RESERVED0_FIELD;
+#define QM_WRED_PROFILE_COLOR_MIN_THR_0_RESERVED0_FIELD_MASK  0xfe000000
+#define QM_WRED_PROFILE_COLOR_MIN_THR_0_RESERVED0_FIELD_WIDTH 7
+#define QM_WRED_PROFILE_COLOR_MIN_THR_0_RESERVED0_FIELD_SHIFT 25
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_FIELD;
+#define QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_FIELD_MASK  0x00ffffff
+#define QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_FIELD_WIDTH 24
+#define QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_1_FLW_CTRL_EN_FIELD;
+#define QM_WRED_PROFILE_COLOR_MIN_THR_1_FLW_CTRL_EN_FIELD_MASK  0x01000000
+#define QM_WRED_PROFILE_COLOR_MIN_THR_1_FLW_CTRL_EN_FIELD_WIDTH 1
+#define QM_WRED_PROFILE_COLOR_MIN_THR_1_FLW_CTRL_EN_FIELD_SHIFT 24
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_1_RESERVED0_FIELD;
+#define QM_WRED_PROFILE_COLOR_MIN_THR_1_RESERVED0_FIELD_MASK  0xfe000000
+#define QM_WRED_PROFILE_COLOR_MIN_THR_1_RESERVED0_FIELD_WIDTH 7
+#define QM_WRED_PROFILE_COLOR_MIN_THR_1_RESERVED0_FIELD_SHIFT 25
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_FIELD;
+#define QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_FIELD_MASK  0x00ffffff
+#define QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_FIELD_WIDTH 24
+#define QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_MAX_THR_0_RESERVED0_FIELD;
+#define QM_WRED_PROFILE_COLOR_MAX_THR_0_RESERVED0_FIELD_MASK  0xff000000
+#define QM_WRED_PROFILE_COLOR_MAX_THR_0_RESERVED0_FIELD_WIDTH 8
+#define QM_WRED_PROFILE_COLOR_MAX_THR_0_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_FIELD;
+#define QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_FIELD_MASK  0x00ffffff
+#define QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_FIELD_WIDTH 24
+#define QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_MAX_THR_1_RESERVED0_FIELD;
+#define QM_WRED_PROFILE_COLOR_MAX_THR_1_RESERVED0_FIELD_MASK  0xff000000
+#define QM_WRED_PROFILE_COLOR_MAX_THR_1_RESERVED0_FIELD_WIDTH 8
+#define QM_WRED_PROFILE_COLOR_MAX_THR_1_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_FIELD;
+#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_FIELD_MASK  0x000000ff
+#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_FIELD_WIDTH 8
+#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_FIELD;
+#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_FIELD_MASK  0x00001f00
+#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_FIELD_WIDTH 5
+#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_0_RESERVED0_FIELD;
+#define QM_WRED_PROFILE_COLOR_SLOPE_0_RESERVED0_FIELD_MASK  0xffffe000
+#define QM_WRED_PROFILE_COLOR_SLOPE_0_RESERVED0_FIELD_WIDTH 19
+#define QM_WRED_PROFILE_COLOR_SLOPE_0_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_FIELD;
+#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_FIELD_MASK  0x000000ff
+#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_FIELD_WIDTH 8
+#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_FIELD;
+#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_FIELD_MASK  0x00001f00
+#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_FIELD_WIDTH 5
+#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_1_RESERVED0_FIELD;
+#define QM_WRED_PROFILE_COLOR_SLOPE_1_RESERVED0_FIELD_MASK  0xffffe000
+#define QM_WRED_PROFILE_COLOR_SLOPE_1_RESERVED0_FIELD_WIDTH 19
+#define QM_WRED_PROFILE_COLOR_SLOPE_1_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_FIELD;
+#define QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_FIELD_MASK  0x3fffffff
+#define QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_FIELD_WIDTH 30
+#define QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_COPY_DECISION_PROFILE_THR_RESERVED0_FIELD;
+#define QM_COPY_DECISION_PROFILE_THR_RESERVED0_FIELD_MASK  0x40000000
+#define QM_COPY_DECISION_PROFILE_THR_RESERVED0_FIELD_WIDTH 1
+#define QM_COPY_DECISION_PROFILE_THR_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec QM_COPY_DECISION_PROFILE_THR_PSRAM_THR_FIELD;
+#define QM_COPY_DECISION_PROFILE_THR_PSRAM_THR_FIELD_MASK  0x80000000
+#define QM_COPY_DECISION_PROFILE_THR_PSRAM_THR_FIELD_WIDTH 1
+#define QM_COPY_DECISION_PROFILE_THR_PSRAM_THR_FIELD_SHIFT 31
+
+extern const ru_field_rec QM_TOTAL_VALID_COUNTER_COUNTER_DATA_FIELD;
+#define QM_TOTAL_VALID_COUNTER_COUNTER_DATA_FIELD_MASK  0xffffffff
+#define QM_TOTAL_VALID_COUNTER_COUNTER_DATA_FIELD_WIDTH 32
+#define QM_TOTAL_VALID_COUNTER_COUNTER_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_DQM_VALID_COUNTER_COUNTER_DATA_FIELD;
+#define QM_DQM_VALID_COUNTER_COUNTER_DATA_FIELD_MASK  0xffffffff
+#define QM_DQM_VALID_COUNTER_COUNTER_DATA_FIELD_WIDTH 32
+#define QM_DQM_VALID_COUNTER_COUNTER_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_DROP_COUNTER_COUNTER_DATA_FIELD;
+#define QM_DROP_COUNTER_COUNTER_DATA_FIELD_MASK  0xffffffff
+#define QM_DROP_COUNTER_COUNTER_DATA_FIELD_WIDTH 32
+#define QM_DROP_COUNTER_COUNTER_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_EPON_RPT_CNT_COUNTER_DATA_FIELD;
+#define QM_EPON_RPT_CNT_COUNTER_DATA_FIELD_MASK  0xffffffff
+#define QM_EPON_RPT_CNT_COUNTER_DATA_FIELD_WIDTH 32
+#define QM_EPON_RPT_CNT_COUNTER_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_FIELD;
+#define QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_FIELD_MASK  0xffffffff
+#define QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_FIELD_WIDTH 32
+#define QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_RD_DATA_POOL0_DATA_FIELD;
+#define QM_RD_DATA_POOL0_DATA_FIELD_MASK  0xffffffff
+#define QM_RD_DATA_POOL0_DATA_FIELD_WIDTH 32
+#define QM_RD_DATA_POOL0_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_RD_DATA_POOL1_DATA_FIELD;
+#define QM_RD_DATA_POOL1_DATA_FIELD_MASK  0xffffffff
+#define QM_RD_DATA_POOL1_DATA_FIELD_WIDTH 32
+#define QM_RD_DATA_POOL1_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_RD_DATA_POOL2_DATA_FIELD;
+#define QM_RD_DATA_POOL2_DATA_FIELD_MASK  0xffffffff
+#define QM_RD_DATA_POOL2_DATA_FIELD_WIDTH 32
+#define QM_RD_DATA_POOL2_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_RD_DATA_POOL3_DATA_FIELD;
+#define QM_RD_DATA_POOL3_DATA_FIELD_MASK  0xffffffff
+#define QM_RD_DATA_POOL3_DATA_FIELD_WIDTH 32
+#define QM_RD_DATA_POOL3_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_PDFIFO_PTR_WR_PTR_FIELD;
+#define QM_PDFIFO_PTR_WR_PTR_FIELD_MASK  0x0000000f
+#define QM_PDFIFO_PTR_WR_PTR_FIELD_WIDTH 4
+#define QM_PDFIFO_PTR_WR_PTR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_PDFIFO_PTR_RESERVED0_FIELD;
+#define QM_PDFIFO_PTR_RESERVED0_FIELD_MASK  0x000000f0
+#define QM_PDFIFO_PTR_RESERVED0_FIELD_WIDTH 4
+#define QM_PDFIFO_PTR_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec QM_PDFIFO_PTR_RD_PTR_FIELD;
+#define QM_PDFIFO_PTR_RD_PTR_FIELD_MASK  0x00000f00
+#define QM_PDFIFO_PTR_RD_PTR_FIELD_WIDTH 4
+#define QM_PDFIFO_PTR_RD_PTR_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_PDFIFO_PTR_RESERVED1_FIELD;
+#define QM_PDFIFO_PTR_RESERVED1_FIELD_MASK  0xfffff000
+#define QM_PDFIFO_PTR_RESERVED1_FIELD_WIDTH 20
+#define QM_PDFIFO_PTR_RESERVED1_FIELD_SHIFT 12
+
+extern const ru_field_rec QM_UPDATE_FIFO_PTR_WR_PTR_FIELD;
+#define QM_UPDATE_FIFO_PTR_WR_PTR_FIELD_MASK  0x000001ff
+#define QM_UPDATE_FIFO_PTR_WR_PTR_FIELD_WIDTH 9
+#define QM_UPDATE_FIFO_PTR_WR_PTR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_UPDATE_FIFO_PTR_RD_PTR_FIELD;
+#define QM_UPDATE_FIFO_PTR_RD_PTR_FIELD_MASK  0x0000fe00
+#define QM_UPDATE_FIFO_PTR_RD_PTR_FIELD_WIDTH 7
+#define QM_UPDATE_FIFO_PTR_RD_PTR_FIELD_SHIFT 9
+
+extern const ru_field_rec QM_UPDATE_FIFO_PTR_RESERVED0_FIELD;
+#define QM_UPDATE_FIFO_PTR_RESERVED0_FIELD_MASK  0xffff0000
+#define QM_UPDATE_FIFO_PTR_RESERVED0_FIELD_WIDTH 16
+#define QM_UPDATE_FIFO_PTR_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_RD_DATA_DATA_FIELD;
+#define QM_RD_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_RD_DATA_DATA_FIELD_WIDTH 32
+#define QM_RD_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_POP_POP_FIELD;
+#define QM_POP_POP_FIELD_MASK  0x00000001
+#define QM_POP_POP_FIELD_WIDTH 1
+#define QM_POP_POP_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_POP_RESERVED0_FIELD;
+#define QM_POP_RESERVED0_FIELD_MASK  0xfffffffe
+#define QM_POP_RESERVED0_FIELD_WIDTH 31
+#define QM_POP_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_CM_COMMON_INPUT_FIFO_DATA_DATA_FIELD;
+#define QM_CM_COMMON_INPUT_FIFO_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_CM_COMMON_INPUT_FIFO_DATA_DATA_FIELD_WIDTH 32
+#define QM_CM_COMMON_INPUT_FIFO_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_NORMAL_RMT_FIFO_DATA_DATA_FIELD;
+#define QM_NORMAL_RMT_FIFO_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_NORMAL_RMT_FIFO_DATA_DATA_FIELD_WIDTH 32
+#define QM_NORMAL_RMT_FIFO_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_NON_DELAYED_RMT_FIFO_DATA_DATA_FIELD;
+#define QM_NON_DELAYED_RMT_FIFO_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_NON_DELAYED_RMT_FIFO_DATA_DATA_FIELD_WIDTH 32
+#define QM_NON_DELAYED_RMT_FIFO_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_EGRESS_DATA_FIFO_DATA_DATA_FIELD;
+#define QM_EGRESS_DATA_FIFO_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_EGRESS_DATA_FIFO_DATA_DATA_FIELD_WIDTH 32
+#define QM_EGRESS_DATA_FIFO_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_EGRESS_RR_FIFO_DATA_DATA_FIELD;
+#define QM_EGRESS_RR_FIFO_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_EGRESS_RR_FIFO_DATA_DATA_FIELD_WIDTH 32
+#define QM_EGRESS_RR_FIFO_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_FIELD;
+#define QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_FIELD_WIDTH 32
+#define QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_FIELD;
+#define QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_FIELD_WIDTH 32
+#define QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_BB_OUTPUT_FIFO_DATA_DATA_FIELD;
+#define QM_BB_OUTPUT_FIFO_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_BB_OUTPUT_FIFO_DATA_DATA_FIELD_WIDTH 32
+#define QM_BB_OUTPUT_FIFO_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_NON_DELAYED_OUT_FIFO_DATA_DATA_FIELD;
+#define QM_NON_DELAYED_OUT_FIFO_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_NON_DELAYED_OUT_FIFO_DATA_DATA_FIELD_WIDTH 32
+#define QM_NON_DELAYED_OUT_FIFO_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CONTEXT_DATA_DATA_FIELD;
+#define QM_CONTEXT_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_CONTEXT_DATA_DATA_FIELD_WIDTH 32
+#define QM_CONTEXT_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_BUFFER_RESERVATION_DATA_DATA_FIELD;
+#define QM_FPM_BUFFER_RESERVATION_DATA_DATA_FIELD_MASK  0x0000ffff
+#define QM_FPM_BUFFER_RESERVATION_DATA_DATA_FIELD_WIDTH 16
+#define QM_FPM_BUFFER_RESERVATION_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_BUFFER_RESERVATION_DATA_RESERVED0_FIELD;
+#define QM_FPM_BUFFER_RESERVATION_DATA_RESERVED0_FIELD_MASK  0xffff0000
+#define QM_FPM_BUFFER_RESERVATION_DATA_RESERVED0_FIELD_WIDTH 16
+#define QM_FPM_BUFFER_RESERVATION_DATA_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_UG_CTRL_FLOW_CTRL_UG0_EN_FIELD;
+#define QM_UG_CTRL_FLOW_CTRL_UG0_EN_FIELD_MASK  0x00000001
+#define QM_UG_CTRL_FLOW_CTRL_UG0_EN_FIELD_WIDTH 1
+#define QM_UG_CTRL_FLOW_CTRL_UG0_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_UG_CTRL_FLOW_CTRL_UG1_EN_FIELD;
+#define QM_UG_CTRL_FLOW_CTRL_UG1_EN_FIELD_MASK  0x00000002
+#define QM_UG_CTRL_FLOW_CTRL_UG1_EN_FIELD_WIDTH 1
+#define QM_UG_CTRL_FLOW_CTRL_UG1_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_UG_CTRL_FLOW_CTRL_UG2_EN_FIELD;
+#define QM_UG_CTRL_FLOW_CTRL_UG2_EN_FIELD_MASK  0x00000004
+#define QM_UG_CTRL_FLOW_CTRL_UG2_EN_FIELD_WIDTH 1
+#define QM_UG_CTRL_FLOW_CTRL_UG2_EN_FIELD_SHIFT 2
+
+extern const ru_field_rec QM_UG_CTRL_FLOW_CTRL_UG3_EN_FIELD;
+#define QM_UG_CTRL_FLOW_CTRL_UG3_EN_FIELD_MASK  0x00000008
+#define QM_UG_CTRL_FLOW_CTRL_UG3_EN_FIELD_WIDTH 1
+#define QM_UG_CTRL_FLOW_CTRL_UG3_EN_FIELD_SHIFT 3
+
+extern const ru_field_rec QM_UG_CTRL_RESERVED0_FIELD;
+#define QM_UG_CTRL_RESERVED0_FIELD_MASK  0xfffffff0
+#define QM_UG_CTRL_RESERVED0_FIELD_WIDTH 28
+#define QM_UG_CTRL_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec QM_STATUS_UG0_FIELD;
+#define QM_STATUS_UG0_FIELD_MASK  0x00000001
+#define QM_STATUS_UG0_FIELD_WIDTH 1
+#define QM_STATUS_UG0_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_STATUS_UG1_FIELD;
+#define QM_STATUS_UG1_FIELD_MASK  0x00000002
+#define QM_STATUS_UG1_FIELD_WIDTH 1
+#define QM_STATUS_UG1_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_STATUS_UG2_FIELD;
+#define QM_STATUS_UG2_FIELD_MASK  0x00000004
+#define QM_STATUS_UG2_FIELD_WIDTH 1
+#define QM_STATUS_UG2_FIELD_SHIFT 2
+
+extern const ru_field_rec QM_STATUS_UG3_FIELD;
+#define QM_STATUS_UG3_FIELD_MASK  0x00000008
+#define QM_STATUS_UG3_FIELD_WIDTH 1
+#define QM_STATUS_UG3_FIELD_SHIFT 3
+
+extern const ru_field_rec QM_STATUS_WRED_FIELD;
+#define QM_STATUS_WRED_FIELD_MASK  0x00000010
+#define QM_STATUS_WRED_FIELD_WIDTH 1
+#define QM_STATUS_WRED_FIELD_SHIFT 4
+
+extern const ru_field_rec QM_STATUS_R0_FIELD;
+#define QM_STATUS_R0_FIELD_MASK  0xffffffe0
+#define QM_STATUS_R0_FIELD_WIDTH 27
+#define QM_STATUS_R0_FIELD_SHIFT 5
+
+extern const ru_field_rec QM_WRED_SOURCE_SRC_FIELD;
+#define QM_WRED_SOURCE_SRC_FIELD_MASK  0xffffffff
+#define QM_WRED_SOURCE_SRC_FIELD_WIDTH 32
+#define QM_WRED_SOURCE_SRC_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_FIELD;
+#define QM_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_FIELD_MASK  0x0000003f
+#define QM_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_FIELD_WIDTH 6
+#define QM_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_FLOW_CTRL_RNR_CFG_RESERVED0_FIELD;
+#define QM_QM_FLOW_CTRL_RNR_CFG_RESERVED0_FIELD_MASK  0x000000c0
+#define QM_QM_FLOW_CTRL_RNR_CFG_RESERVED0_FIELD_WIDTH 2
+#define QM_QM_FLOW_CTRL_RNR_CFG_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec QM_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_FIELD;
+#define QM_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_FIELD_MASK  0x00000f00
+#define QM_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_FIELD_WIDTH 4
+#define QM_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_QM_FLOW_CTRL_RNR_CFG_RESERVED1_FIELD;
+#define QM_QM_FLOW_CTRL_RNR_CFG_RESERVED1_FIELD_MASK  0x0000f000
+#define QM_QM_FLOW_CTRL_RNR_CFG_RESERVED1_FIELD_WIDTH 4
+#define QM_QM_FLOW_CTRL_RNR_CFG_RESERVED1_FIELD_SHIFT 12
+
+extern const ru_field_rec QM_QM_FLOW_CTRL_RNR_CFG_RNR_ENABLE_FIELD;
+#define QM_QM_FLOW_CTRL_RNR_CFG_RNR_ENABLE_FIELD_MASK  0x00010000
+#define QM_QM_FLOW_CTRL_RNR_CFG_RNR_ENABLE_FIELD_WIDTH 1
+#define QM_QM_FLOW_CTRL_RNR_CFG_RNR_ENABLE_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_QM_FLOW_CTRL_RNR_CFG_SRAM_WR_EN_FIELD;
+#define QM_QM_FLOW_CTRL_RNR_CFG_SRAM_WR_EN_FIELD_MASK  0x00020000
+#define QM_QM_FLOW_CTRL_RNR_CFG_SRAM_WR_EN_FIELD_WIDTH 1
+#define QM_QM_FLOW_CTRL_RNR_CFG_SRAM_WR_EN_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_QM_FLOW_CTRL_RNR_CFG_SRAM_WR_ADDR_FIELD;
+#define QM_QM_FLOW_CTRL_RNR_CFG_SRAM_WR_ADDR_FIELD_MASK  0x3ffc0000
+#define QM_QM_FLOW_CTRL_RNR_CFG_SRAM_WR_ADDR_FIELD_WIDTH 12
+#define QM_QM_FLOW_CTRL_RNR_CFG_SRAM_WR_ADDR_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_QM_FLOW_CTRL_RNR_CFG_RESERVED2_FIELD;
+#define QM_QM_FLOW_CTRL_RNR_CFG_RESERVED2_FIELD_MASK  0xc0000000
+#define QM_QM_FLOW_CTRL_RNR_CFG_RESERVED2_FIELD_WIDTH 2
+#define QM_QM_FLOW_CTRL_RNR_CFG_RESERVED2_FIELD_SHIFT 30
+
+extern const ru_field_rec QM_DEBUG_SEL_SELECT_FIELD;
+#define QM_DEBUG_SEL_SELECT_FIELD_MASK  0x0000001f
+#define QM_DEBUG_SEL_SELECT_FIELD_WIDTH 5
+#define QM_DEBUG_SEL_SELECT_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_DEBUG_SEL_RESERVED0_FIELD;
+#define QM_DEBUG_SEL_RESERVED0_FIELD_MASK  0x7fffffe0
+#define QM_DEBUG_SEL_RESERVED0_FIELD_WIDTH 26
+#define QM_DEBUG_SEL_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec QM_DEBUG_SEL_ENABLE_FIELD;
+#define QM_DEBUG_SEL_ENABLE_FIELD_MASK  0x80000000
+#define QM_DEBUG_SEL_ENABLE_FIELD_WIDTH 1
+#define QM_DEBUG_SEL_ENABLE_FIELD_SHIFT 31
+
+extern const ru_field_rec QM_DEBUG_BUS_LSB_DATA_FIELD;
+#define QM_DEBUG_BUS_LSB_DATA_FIELD_MASK  0xffffffff
+#define QM_DEBUG_BUS_LSB_DATA_FIELD_WIDTH 32
+#define QM_DEBUG_BUS_LSB_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_DEBUG_BUS_MSB_DATA_FIELD;
+#define QM_DEBUG_BUS_MSB_DATA_FIELD_MASK  0xffffffff
+#define QM_DEBUG_BUS_MSB_DATA_FIELD_WIDTH 32
+#define QM_DEBUG_BUS_MSB_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_SPARE_CONFIG_DATA_FIELD;
+#define QM_QM_SPARE_CONFIG_DATA_FIELD_MASK  0xffffffff
+#define QM_QM_SPARE_CONFIG_DATA_FIELD_WIDTH 32
+#define QM_QM_SPARE_CONFIG_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GOOD_LVL1_PKTS_CNT_COUNTER_FIELD;
+#define QM_GOOD_LVL1_PKTS_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_GOOD_LVL1_PKTS_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_GOOD_LVL1_PKTS_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GOOD_LVL1_BYTES_CNT_COUNTER_FIELD;
+#define QM_GOOD_LVL1_BYTES_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_GOOD_LVL1_BYTES_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_GOOD_LVL1_BYTES_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GOOD_LVL2_PKTS_CNT_COUNTER_FIELD;
+#define QM_GOOD_LVL2_PKTS_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_GOOD_LVL2_PKTS_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_GOOD_LVL2_PKTS_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GOOD_LVL2_BYTES_CNT_COUNTER_FIELD;
+#define QM_GOOD_LVL2_BYTES_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_GOOD_LVL2_BYTES_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_GOOD_LVL2_BYTES_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_COPIED_PKTS_CNT_COUNTER_FIELD;
+#define QM_COPIED_PKTS_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_COPIED_PKTS_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_COPIED_PKTS_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_COPIED_BYTES_CNT_COUNTER_FIELD;
+#define QM_COPIED_BYTES_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_COPIED_BYTES_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_COPIED_BYTES_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_AGG_PKTS_CNT_COUNTER_FIELD;
+#define QM_AGG_PKTS_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_AGG_PKTS_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_AGG_PKTS_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_AGG_BYTES_CNT_COUNTER_FIELD;
+#define QM_AGG_BYTES_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_AGG_BYTES_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_AGG_BYTES_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_AGG_1_PKTS_CNT_COUNTER_FIELD;
+#define QM_AGG_1_PKTS_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_AGG_1_PKTS_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_AGG_1_PKTS_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_AGG_2_PKTS_CNT_COUNTER_FIELD;
+#define QM_AGG_2_PKTS_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_AGG_2_PKTS_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_AGG_2_PKTS_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_AGG_3_PKTS_CNT_COUNTER_FIELD;
+#define QM_AGG_3_PKTS_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_AGG_3_PKTS_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_AGG_3_PKTS_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_AGG_4_PKTS_CNT_COUNTER_FIELD;
+#define QM_AGG_4_PKTS_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_AGG_4_PKTS_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_AGG_4_PKTS_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_WRED_DROP_CNT_COUNTER_FIELD;
+#define QM_WRED_DROP_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_WRED_DROP_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_WRED_DROP_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_CONGESTION_DROP_CNT_COUNTER_FIELD;
+#define QM_FPM_CONGESTION_DROP_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_FPM_CONGESTION_DROP_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_FPM_CONGESTION_DROP_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_FIELD;
+#define QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_FIELD;
+#define QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_FIELD;
+#define QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_ABS_REQUEUE_CNT_COUNTER_FIELD;
+#define QM_QM_ABS_REQUEUE_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_QM_ABS_REQUEUE_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_QM_ABS_REQUEUE_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_FIELD;
+#define QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO0_STATUS_EMPTY_FIELD;
+#define QM_FPM_PREFETCH_FIFO0_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_FPM_PREFETCH_FIFO0_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_FPM_PREFETCH_FIFO0_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO0_STATUS_FULL_FIELD;
+#define QM_FPM_PREFETCH_FIFO0_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_FPM_PREFETCH_FIFO0_STATUS_FULL_FIELD_WIDTH 1
+#define QM_FPM_PREFETCH_FIFO0_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO0_STATUS_RESERVED0_FIELD;
+#define QM_FPM_PREFETCH_FIFO0_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_FPM_PREFETCH_FIFO0_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_FPM_PREFETCH_FIFO0_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_FIELD;
+#define QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO1_STATUS_EMPTY_FIELD;
+#define QM_FPM_PREFETCH_FIFO1_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_FPM_PREFETCH_FIFO1_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_FPM_PREFETCH_FIFO1_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO1_STATUS_FULL_FIELD;
+#define QM_FPM_PREFETCH_FIFO1_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_FPM_PREFETCH_FIFO1_STATUS_FULL_FIELD_WIDTH 1
+#define QM_FPM_PREFETCH_FIFO1_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO1_STATUS_RESERVED0_FIELD;
+#define QM_FPM_PREFETCH_FIFO1_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_FPM_PREFETCH_FIFO1_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_FPM_PREFETCH_FIFO1_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_FIELD;
+#define QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO2_STATUS_EMPTY_FIELD;
+#define QM_FPM_PREFETCH_FIFO2_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_FPM_PREFETCH_FIFO2_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_FPM_PREFETCH_FIFO2_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO2_STATUS_FULL_FIELD;
+#define QM_FPM_PREFETCH_FIFO2_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_FPM_PREFETCH_FIFO2_STATUS_FULL_FIELD_WIDTH 1
+#define QM_FPM_PREFETCH_FIFO2_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO2_STATUS_RESERVED0_FIELD;
+#define QM_FPM_PREFETCH_FIFO2_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_FPM_PREFETCH_FIFO2_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_FPM_PREFETCH_FIFO2_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_FIELD;
+#define QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO3_STATUS_EMPTY_FIELD;
+#define QM_FPM_PREFETCH_FIFO3_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_FPM_PREFETCH_FIFO3_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_FPM_PREFETCH_FIFO3_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO3_STATUS_FULL_FIELD;
+#define QM_FPM_PREFETCH_FIFO3_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_FPM_PREFETCH_FIFO3_STATUS_FULL_FIELD_WIDTH 1
+#define QM_FPM_PREFETCH_FIFO3_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_FPM_PREFETCH_FIFO3_STATUS_RESERVED0_FIELD;
+#define QM_FPM_PREFETCH_FIFO3_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_FPM_PREFETCH_FIFO3_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_FPM_PREFETCH_FIFO3_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_NORMAL_RMT_FIFO_STATUS_EMPTY_FIELD;
+#define QM_NORMAL_RMT_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_NORMAL_RMT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_NORMAL_RMT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_NORMAL_RMT_FIFO_STATUS_FULL_FIELD;
+#define QM_NORMAL_RMT_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_NORMAL_RMT_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_NORMAL_RMT_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_NORMAL_RMT_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_NORMAL_RMT_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_NORMAL_RMT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_NORMAL_RMT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_NON_DELAYED_RMT_FIFO_STATUS_EMPTY_FIELD;
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_NON_DELAYED_RMT_FIFO_STATUS_FULL_FIELD;
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_NON_DELAYED_RMT_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_NON_DELAYED_OUT_FIFO_STATUS_EMPTY_FIELD;
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_NON_DELAYED_OUT_FIFO_STATUS_FULL_FIELD;
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_NON_DELAYED_OUT_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_PRE_CM_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_PRE_CM_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_PRE_CM_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_PRE_CM_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_PRE_CM_FIFO_STATUS_EMPTY_FIELD;
+#define QM_PRE_CM_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_PRE_CM_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_PRE_CM_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_PRE_CM_FIFO_STATUS_FULL_FIELD;
+#define QM_PRE_CM_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_PRE_CM_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_PRE_CM_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_PRE_CM_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_PRE_CM_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_PRE_CM_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_PRE_CM_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CM_RD_PD_FIFO_STATUS_EMPTY_FIELD;
+#define QM_CM_RD_PD_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_CM_RD_PD_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_CM_RD_PD_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_CM_RD_PD_FIFO_STATUS_FULL_FIELD;
+#define QM_CM_RD_PD_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_CM_RD_PD_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_CM_RD_PD_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_CM_RD_PD_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_CM_RD_PD_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_CM_RD_PD_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_CM_RD_PD_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CM_WR_PD_FIFO_STATUS_EMPTY_FIELD;
+#define QM_CM_WR_PD_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_CM_WR_PD_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_CM_WR_PD_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_CM_WR_PD_FIFO_STATUS_FULL_FIELD;
+#define QM_CM_WR_PD_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_CM_WR_PD_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_CM_WR_PD_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_CM_WR_PD_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_CM_WR_PD_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_CM_WR_PD_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_CM_WR_PD_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_CM_COMMON_INPUT_FIFO_STATUS_EMPTY_FIELD;
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_CM_COMMON_INPUT_FIFO_STATUS_FULL_FIELD;
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_CM_COMMON_INPUT_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_BB0_OUTPUT_FIFO_STATUS_EMPTY_FIELD;
+#define QM_BB0_OUTPUT_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_BB0_OUTPUT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_BB0_OUTPUT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_BB0_OUTPUT_FIFO_STATUS_FULL_FIELD;
+#define QM_BB0_OUTPUT_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_BB0_OUTPUT_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_BB0_OUTPUT_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_BB0_OUTPUT_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_BB0_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_BB0_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_BB0_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_BB1_OUTPUT_FIFO_STATUS_EMPTY_FIELD;
+#define QM_BB1_OUTPUT_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_BB1_OUTPUT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_BB1_OUTPUT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_BB1_OUTPUT_FIFO_STATUS_FULL_FIELD;
+#define QM_BB1_OUTPUT_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_BB1_OUTPUT_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_BB1_OUTPUT_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_BB1_OUTPUT_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_BB1_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_BB1_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_BB1_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_BB1_INPUT_FIFO_STATUS_EMPTY_FIELD;
+#define QM_BB1_INPUT_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_BB1_INPUT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_BB1_INPUT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_BB1_INPUT_FIFO_STATUS_FULL_FIELD;
+#define QM_BB1_INPUT_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_BB1_INPUT_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_BB1_INPUT_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_BB1_INPUT_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_BB1_INPUT_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_BB1_INPUT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_BB1_INPUT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_EGRESS_DATA_FIFO_STATUS_EMPTY_FIELD;
+#define QM_EGRESS_DATA_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_EGRESS_DATA_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_EGRESS_DATA_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_EGRESS_DATA_FIFO_STATUS_FULL_FIELD;
+#define QM_EGRESS_DATA_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_EGRESS_DATA_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_EGRESS_DATA_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_EGRESS_DATA_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_EGRESS_DATA_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_EGRESS_DATA_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_EGRESS_DATA_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_FIELD;
+#define QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x0000ffff
+#define QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16
+#define QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_EGRESS_RR_FIFO_STATUS_EMPTY_FIELD;
+#define QM_EGRESS_RR_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define QM_EGRESS_RR_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define QM_EGRESS_RR_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_EGRESS_RR_FIFO_STATUS_FULL_FIELD;
+#define QM_EGRESS_RR_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define QM_EGRESS_RR_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define QM_EGRESS_RR_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec QM_EGRESS_RR_FIFO_STATUS_RESERVED0_FIELD;
+#define QM_EGRESS_RR_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define QM_EGRESS_RR_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define QM_EGRESS_RR_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec QM_BB_ROUTE_OVR_OVR_EN_FIELD;
+#define QM_BB_ROUTE_OVR_OVR_EN_FIELD_MASK  0x00000001
+#define QM_BB_ROUTE_OVR_OVR_EN_FIELD_WIDTH 1
+#define QM_BB_ROUTE_OVR_OVR_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_BB_ROUTE_OVR_RESERVED0_FIELD;
+#define QM_BB_ROUTE_OVR_RESERVED0_FIELD_MASK  0x000000fe
+#define QM_BB_ROUTE_OVR_RESERVED0_FIELD_WIDTH 7
+#define QM_BB_ROUTE_OVR_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec QM_BB_ROUTE_OVR_DEST_ID_FIELD;
+#define QM_BB_ROUTE_OVR_DEST_ID_FIELD_MASK  0x00003f00
+#define QM_BB_ROUTE_OVR_DEST_ID_FIELD_WIDTH 6
+#define QM_BB_ROUTE_OVR_DEST_ID_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_BB_ROUTE_OVR_RESERVED1_FIELD;
+#define QM_BB_ROUTE_OVR_RESERVED1_FIELD_MASK  0x0000c000
+#define QM_BB_ROUTE_OVR_RESERVED1_FIELD_WIDTH 2
+#define QM_BB_ROUTE_OVR_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec QM_BB_ROUTE_OVR_ROUTE_ADDR_FIELD;
+#define QM_BB_ROUTE_OVR_ROUTE_ADDR_FIELD_MASK  0x03ff0000
+#define QM_BB_ROUTE_OVR_ROUTE_ADDR_FIELD_WIDTH 10
+#define QM_BB_ROUTE_OVR_ROUTE_ADDR_FIELD_SHIFT 16
+
+extern const ru_field_rec QM_BB_ROUTE_OVR_RESERVED2_FIELD;
+#define QM_BB_ROUTE_OVR_RESERVED2_FIELD_MASK  0xfc000000
+#define QM_BB_ROUTE_OVR_RESERVED2_FIELD_WIDTH 6
+#define QM_BB_ROUTE_OVR_RESERVED2_FIELD_SHIFT 26
+
+extern const ru_field_rec QM_QM_INGRESS_STAT_STAT_FIELD;
+#define QM_QM_INGRESS_STAT_STAT_FIELD_MASK  0xffffffff
+#define QM_QM_INGRESS_STAT_STAT_FIELD_WIDTH 32
+#define QM_QM_INGRESS_STAT_STAT_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_EGRESS_STAT_STAT_FIELD;
+#define QM_QM_EGRESS_STAT_STAT_FIELD_MASK  0xffffffff
+#define QM_QM_EGRESS_STAT_STAT_FIELD_WIDTH 32
+#define QM_QM_EGRESS_STAT_STAT_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_CM_STAT_STAT_FIELD;
+#define QM_QM_CM_STAT_STAT_FIELD_MASK  0xffffffff
+#define QM_QM_CM_STAT_STAT_FIELD_WIDTH 32
+#define QM_QM_CM_STAT_STAT_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_FPM_PREFETCH_STAT_STAT_FIELD;
+#define QM_QM_FPM_PREFETCH_STAT_STAT_FIELD_MASK  0xffffffff
+#define QM_QM_FPM_PREFETCH_STAT_STAT_FIELD_WIDTH 32
+#define QM_QM_FPM_PREFETCH_STAT_STAT_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_FIELD;
+#define QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_FIELD_MASK  0x000000ff
+#define QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_FIELD_WIDTH 8
+#define QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_CONNECT_ACK_COUNTER_RESERVED0_FIELD;
+#define QM_QM_CONNECT_ACK_COUNTER_RESERVED0_FIELD_MASK  0xffffff00
+#define QM_QM_CONNECT_ACK_COUNTER_RESERVED0_FIELD_WIDTH 24
+#define QM_QM_CONNECT_ACK_COUNTER_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_FIELD;
+#define QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_FIELD_MASK  0x000000ff
+#define QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_FIELD_WIDTH 8
+#define QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_DDR_WR_REPLY_COUNTER_RESERVED0_FIELD;
+#define QM_QM_DDR_WR_REPLY_COUNTER_RESERVED0_FIELD_MASK  0xffffff00
+#define QM_QM_DDR_WR_REPLY_COUNTER_RESERVED0_FIELD_WIDTH 24
+#define QM_QM_DDR_WR_REPLY_COUNTER_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_FIELD;
+#define QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_FIELD_MASK  0x0fffffff
+#define QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_FIELD_WIDTH 28
+#define QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_DDR_PIPE_BYTE_COUNTER_RESERVED0_FIELD;
+#define QM_QM_DDR_PIPE_BYTE_COUNTER_RESERVED0_FIELD_MASK  0xf0000000
+#define QM_QM_DDR_PIPE_BYTE_COUNTER_RESERVED0_FIELD_WIDTH 4
+#define QM_QM_DDR_PIPE_BYTE_COUNTER_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_FIELD;
+#define QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_FIELD_MASK  0x00007fff
+#define QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_FIELD_WIDTH 15
+#define QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_ABS_REQUEUE_VALID_COUNTER_RESERVED0_FIELD;
+#define QM_QM_ABS_REQUEUE_VALID_COUNTER_RESERVED0_FIELD_MASK  0xffff8000
+#define QM_QM_ABS_REQUEUE_VALID_COUNTER_RESERVED0_FIELD_WIDTH 17
+#define QM_QM_ABS_REQUEUE_VALID_COUNTER_RESERVED0_FIELD_SHIFT 15
+
+extern const ru_field_rec QM_QM_ILLEGAL_PD_CAPTURE_PD_FIELD;
+#define QM_QM_ILLEGAL_PD_CAPTURE_PD_FIELD_MASK  0xffffffff
+#define QM_QM_ILLEGAL_PD_CAPTURE_PD_FIELD_WIDTH 32
+#define QM_QM_ILLEGAL_PD_CAPTURE_PD_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_FIELD;
+#define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_FIELD_MASK  0xffffffff
+#define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_FIELD_WIDTH 32
+#define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_QM_CM_PROCESSED_PD_CAPTURE_PD_FIELD;
+#define QM_QM_CM_PROCESSED_PD_CAPTURE_PD_FIELD_MASK  0xffffffff
+#define QM_QM_CM_PROCESSED_PD_CAPTURE_PD_FIELD_WIDTH 32
+#define QM_QM_CM_PROCESSED_PD_CAPTURE_PD_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_POOL_DROP_CNT_COUNTER_FIELD;
+#define QM_FPM_POOL_DROP_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_FPM_POOL_DROP_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_FPM_POOL_DROP_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_GRP_DROP_CNT_COUNTER_FIELD;
+#define QM_FPM_GRP_DROP_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_FPM_GRP_DROP_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_FPM_GRP_DROP_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_FIELD;
+#define QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_PSRAM_EGRESS_CONG_DRP_CNT_COUNTER_FIELD;
+#define QM_PSRAM_EGRESS_CONG_DRP_CNT_COUNTER_FIELD_MASK  0xffffffff
+#define QM_PSRAM_EGRESS_CONG_DRP_CNT_COUNTER_FIELD_WIDTH 32
+#define QM_PSRAM_EGRESS_CONG_DRP_CNT_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_BACKPRESSURE_STATUS_FIELD;
+#define QM_BACKPRESSURE_STATUS_FIELD_MASK  0x0000000f
+#define QM_BACKPRESSURE_STATUS_FIELD_WIDTH 4
+#define QM_BACKPRESSURE_STATUS_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_BACKPRESSURE_R1_FIELD;
+#define QM_BACKPRESSURE_R1_FIELD_MASK  0xfffffff0
+#define QM_BACKPRESSURE_R1_FIELD_WIDTH 28
+#define QM_BACKPRESSURE_R1_FIELD_SHIFT 4
+
+extern const ru_field_rec QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_ADDR_FIELD;
+#define QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_ADDR_FIELD_MASK  0x0000003f
+#define QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_ADDR_FIELD_WIDTH 6
+#define QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_BBHTX_REQ_OTF_FIELD;
+#define QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_BBHTX_REQ_OTF_FIELD_MASK  0x00000fc0
+#define QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_BBHTX_REQ_OTF_FIELD_WIDTH 6
+#define QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_BBHTX_REQ_OTF_FIELD_SHIFT 6
+
+extern const ru_field_rec QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_RESERVED0_FIELD;
+#define QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_RESERVED0_FIELD_MASK  0xfffff000
+#define QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_RESERVED0_FIELD_WIDTH 20
+#define QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec QM_DATA_DATA_FIELD;
+#define QM_DATA_DATA_FIELD_MASK  0xffffffff
+#define QM_DATA_DATA_FIELD_WIDTH 32
+#define QM_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_TOKEN_FIFO_TOKEN_FIFO_TOKEN_FIELD;
+#define DQM_TOKEN_FIFO_TOKEN_FIFO_TOKEN_FIELD_MASK  0xffffffff
+#define DQM_TOKEN_FIFO_TOKEN_FIFO_TOKEN_FIELD_WIDTH 32
+#define DQM_TOKEN_FIFO_TOKEN_FIFO_TOKEN_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_MAX_ENTRIES_WORDS_RESERVED0_FIELD;
+#define DQM_MAX_ENTRIES_WORDS_RESERVED0_FIELD_MASK  0xfff80000
+#define DQM_MAX_ENTRIES_WORDS_RESERVED0_FIELD_WIDTH 13
+#define DQM_MAX_ENTRIES_WORDS_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec DQM_MAX_ENTRIES_WORDS_MAX_FIELD;
+#define DQM_MAX_ENTRIES_WORDS_MAX_FIELD_MASK  0x0007ffff
+#define DQM_MAX_ENTRIES_WORDS_MAX_FIELD_WIDTH 19
+#define DQM_MAX_ENTRIES_WORDS_MAX_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_FPM_ADDR_FPMADDRESS_FIELD;
+#define DQM_FPM_ADDR_FPMADDRESS_FIELD_MASK  0xffffffff
+#define DQM_FPM_ADDR_FPMADDRESS_FIELD_WIDTH 32
+#define DQM_FPM_ADDR_FPMADDRESS_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_IRQ_STS_RESERVED0_FIELD;
+#define DQM_IRQ_STS_RESERVED0_FIELD_MASK  0xfffffffc
+#define DQM_IRQ_STS_RESERVED0_FIELD_WIDTH 30
+#define DQM_IRQ_STS_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec DQM_IRQ_STS_PUSHFULLQ_FIELD;
+#define DQM_IRQ_STS_PUSHFULLQ_FIELD_MASK  0x00000002
+#define DQM_IRQ_STS_PUSHFULLQ_FIELD_WIDTH 1
+#define DQM_IRQ_STS_PUSHFULLQ_FIELD_SHIFT 1
+
+extern const ru_field_rec DQM_IRQ_STS_POPEMPTYQ_FIELD;
+#define DQM_IRQ_STS_POPEMPTYQ_FIELD_MASK  0x00000001
+#define DQM_IRQ_STS_POPEMPTYQ_FIELD_WIDTH 1
+#define DQM_IRQ_STS_POPEMPTYQ_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_IRQ_MSK_RESERVED0_FIELD;
+#define DQM_IRQ_MSK_RESERVED0_FIELD_MASK  0xfffffffc
+#define DQM_IRQ_MSK_RESERVED0_FIELD_WIDTH 30
+#define DQM_IRQ_MSK_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec DQM_IRQ_MSK_PUSHFULLQ_FIELD;
+#define DQM_IRQ_MSK_PUSHFULLQ_FIELD_MASK  0x00000002
+#define DQM_IRQ_MSK_PUSHFULLQ_FIELD_WIDTH 1
+#define DQM_IRQ_MSK_PUSHFULLQ_FIELD_SHIFT 1
+
+extern const ru_field_rec DQM_IRQ_MSK_POPEMPTYQ_FIELD;
+#define DQM_IRQ_MSK_POPEMPTYQ_FIELD_MASK  0x00000001
+#define DQM_IRQ_MSK_POPEMPTYQ_FIELD_WIDTH 1
+#define DQM_IRQ_MSK_POPEMPTYQ_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_BUF_SIZE_RESERVED0_FIELD;
+#define DQM_BUF_SIZE_RESERVED0_FIELD_MASK  0xfffffffc
+#define DQM_BUF_SIZE_RESERVED0_FIELD_WIDTH 30
+#define DQM_BUF_SIZE_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec DQM_BUF_SIZE_POOL_0_SIZE_FIELD;
+#define DQM_BUF_SIZE_POOL_0_SIZE_FIELD_MASK  0x00000003
+#define DQM_BUF_SIZE_POOL_0_SIZE_FIELD_WIDTH 2
+#define DQM_BUF_SIZE_POOL_0_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_BUF_BASE_BASE_FIELD;
+#define DQM_BUF_BASE_BASE_FIELD_MASK  0xffffffff
+#define DQM_BUF_BASE_BASE_FIELD_WIDTH 32
+#define DQM_BUF_BASE_BASE_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_TOKENS_USED_COUNT_FIELD;
+#define DQM_TOKENS_USED_COUNT_FIELD_MASK  0xffffffff
+#define DQM_TOKENS_USED_COUNT_FIELD_WIDTH 32
+#define DQM_TOKENS_USED_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_NUM_PUSHED_COUNT_FIELD;
+#define DQM_NUM_PUSHED_COUNT_FIELD_MASK  0xffffffff
+#define DQM_NUM_PUSHED_COUNT_FIELD_WIDTH 32
+#define DQM_NUM_PUSHED_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_NUM_POPPED_COUNT_FIELD;
+#define DQM_NUM_POPPED_COUNT_FIELD_MASK  0xffffffff
+#define DQM_NUM_POPPED_COUNT_FIELD_WIDTH 32
+#define DQM_NUM_POPPED_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_DIAG_SEL_RESERVED0_FIELD;
+#define DQM_DIAG_SEL_RESERVED0_FIELD_MASK  0xffffff00
+#define DQM_DIAG_SEL_RESERVED0_FIELD_WIDTH 24
+#define DQM_DIAG_SEL_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec DQM_DIAG_SEL_SEL_FIELD;
+#define DQM_DIAG_SEL_SEL_FIELD_MASK  0x000000ff
+#define DQM_DIAG_SEL_SEL_FIELD_WIDTH 8
+#define DQM_DIAG_SEL_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_DIAG_DATA_DATA_FIELD;
+#define DQM_DIAG_DATA_DATA_FIELD_MASK  0xffffffff
+#define DQM_DIAG_DATA_DATA_FIELD_WIDTH 32
+#define DQM_DIAG_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_IRQ_TST_RESERVED0_FIELD;
+#define DQM_IRQ_TST_RESERVED0_FIELD_MASK  0xfffffffc
+#define DQM_IRQ_TST_RESERVED0_FIELD_WIDTH 30
+#define DQM_IRQ_TST_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec DQM_IRQ_TST_PUSHFULLQTST_FIELD;
+#define DQM_IRQ_TST_PUSHFULLQTST_FIELD_MASK  0x00000002
+#define DQM_IRQ_TST_PUSHFULLQTST_FIELD_WIDTH 1
+#define DQM_IRQ_TST_PUSHFULLQTST_FIELD_SHIFT 1
+
+extern const ru_field_rec DQM_IRQ_TST_POPEMPTYQTST_FIELD;
+#define DQM_IRQ_TST_POPEMPTYQTST_FIELD_MASK  0x00000001
+#define DQM_IRQ_TST_POPEMPTYQTST_FIELD_WIDTH 1
+#define DQM_IRQ_TST_POPEMPTYQTST_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_TOKEN_FIFO_STATUS_RESERVED0_FIELD;
+#define DQM_TOKEN_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffc0000
+#define DQM_TOKEN_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14
+#define DQM_TOKEN_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec DQM_TOKEN_FIFO_STATUS_FULL_FIELD;
+#define DQM_TOKEN_FIFO_STATUS_FULL_FIELD_MASK  0x00020000
+#define DQM_TOKEN_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define DQM_TOKEN_FIFO_STATUS_FULL_FIELD_SHIFT 17
+
+extern const ru_field_rec DQM_TOKEN_FIFO_STATUS_EMPTY_FIELD;
+#define DQM_TOKEN_FIFO_STATUS_EMPTY_FIELD_MASK  0x00010000
+#define DQM_TOKEN_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define DQM_TOKEN_FIFO_STATUS_EMPTY_FIELD_SHIFT 16
+
+extern const ru_field_rec DQM_TOKEN_FIFO_STATUS_RESERVED1_FIELD;
+#define DQM_TOKEN_FIFO_STATUS_RESERVED1_FIELD_MASK  0x0000e000
+#define DQM_TOKEN_FIFO_STATUS_RESERVED1_FIELD_WIDTH 3
+#define DQM_TOKEN_FIFO_STATUS_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec DQM_TOKEN_FIFO_STATUS_LEVEL_FIELD;
+#define DQM_TOKEN_FIFO_STATUS_LEVEL_FIELD_MASK  0x00001f00
+#define DQM_TOKEN_FIFO_STATUS_LEVEL_FIELD_WIDTH 5
+#define DQM_TOKEN_FIFO_STATUS_LEVEL_FIELD_SHIFT 8
+
+extern const ru_field_rec DQM_TOKEN_FIFO_STATUS_RESERVED2_FIELD;
+#define DQM_TOKEN_FIFO_STATUS_RESERVED2_FIELD_MASK  0x000000f0
+#define DQM_TOKEN_FIFO_STATUS_RESERVED2_FIELD_WIDTH 4
+#define DQM_TOKEN_FIFO_STATUS_RESERVED2_FIELD_SHIFT 4
+
+extern const ru_field_rec DQM_TOKEN_FIFO_STATUS_RD_LOC_FIELD;
+#define DQM_TOKEN_FIFO_STATUS_RD_LOC_FIELD_MASK  0x0000000f
+#define DQM_TOKEN_FIFO_STATUS_RD_LOC_FIELD_WIDTH 4
+#define DQM_TOKEN_FIFO_STATUS_RD_LOC_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_NUM_POPPED_NO_COMMIT_COUNT_FIELD;
+#define DQM_NUM_POPPED_NO_COMMIT_COUNT_FIELD_MASK  0xffffffff
+#define DQM_NUM_POPPED_NO_COMMIT_COUNT_FIELD_WIDTH 32
+#define DQM_NUM_POPPED_NO_COMMIT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_STATUS_CURR_LINE_DATA_IS_LOCAL_FIELD;
+#define DQM_STATUS_CURR_LINE_DATA_IS_LOCAL_FIELD_MASK  0x80000000
+#define DQM_STATUS_CURR_LINE_DATA_IS_LOCAL_FIELD_WIDTH 1
+#define DQM_STATUS_CURR_LINE_DATA_IS_LOCAL_FIELD_SHIFT 31
+
+extern const ru_field_rec DQM_STATUS_NEXT_LINE_DATA_IS_LOCAL_FIELD;
+#define DQM_STATUS_NEXT_LINE_DATA_IS_LOCAL_FIELD_MASK  0x40000000
+#define DQM_STATUS_NEXT_LINE_DATA_IS_LOCAL_FIELD_WIDTH 1
+#define DQM_STATUS_NEXT_LINE_DATA_IS_LOCAL_FIELD_SHIFT 30
+
+extern const ru_field_rec DQM_STATUS_RESERVED0_FIELD;
+#define DQM_STATUS_RESERVED0_FIELD_MASK  0x3ff80000
+#define DQM_STATUS_RESERVED0_FIELD_WIDTH 11
+#define DQM_STATUS_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec DQM_STATUS_Q_AVL_TKN_SPACE_FIELD;
+#define DQM_STATUS_Q_AVL_TKN_SPACE_FIELD_MASK  0x0007ffff
+#define DQM_STATUS_Q_AVL_TKN_SPACE_FIELD_WIDTH 19
+#define DQM_STATUS_Q_AVL_TKN_SPACE_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_HEAD_PTR_RESERVED0_FIELD;
+#define DQM_HEAD_PTR_RESERVED0_FIELD_MASK  0xf0000000
+#define DQM_HEAD_PTR_RESERVED0_FIELD_WIDTH 4
+#define DQM_HEAD_PTR_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec DQM_HEAD_PTR_Q_HEAD_PTR_FIELD;
+#define DQM_HEAD_PTR_Q_HEAD_PTR_FIELD_MASK  0x0fffffff
+#define DQM_HEAD_PTR_Q_HEAD_PTR_FIELD_WIDTH 28
+#define DQM_HEAD_PTR_Q_HEAD_PTR_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_TAIL_PTR_RESERVED0_FIELD;
+#define DQM_TAIL_PTR_RESERVED0_FIELD_MASK  0xf0000000
+#define DQM_TAIL_PTR_RESERVED0_FIELD_WIDTH 4
+#define DQM_TAIL_PTR_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec DQM_TAIL_PTR_Q_TAIL_PTR_FIELD;
+#define DQM_TAIL_PTR_Q_TAIL_PTR_FIELD_MASK  0x0fffffff
+#define DQM_TAIL_PTR_Q_TAIL_PTR_FIELD_WIDTH 28
+#define DQM_TAIL_PTR_Q_TAIL_PTR_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_DQMOL_SIZE_RESERVED0_FIELD;
+#define DQM_DQMOL_SIZE_RESERVED0_FIELD_MASK  0xff800000
+#define DQM_DQMOL_SIZE_RESERVED0_FIELD_WIDTH 9
+#define DQM_DQMOL_SIZE_RESERVED0_FIELD_SHIFT 23
+
+extern const ru_field_rec DQM_DQMOL_SIZE_MAX_ENTRIES_FIELD;
+#define DQM_DQMOL_SIZE_MAX_ENTRIES_FIELD_MASK  0x007ffff0
+#define DQM_DQMOL_SIZE_MAX_ENTRIES_FIELD_WIDTH 19
+#define DQM_DQMOL_SIZE_MAX_ENTRIES_FIELD_SHIFT 4
+
+extern const ru_field_rec DQM_DQMOL_SIZE_Q_DISABLE_OFFLOAD_FIELD;
+#define DQM_DQMOL_SIZE_Q_DISABLE_OFFLOAD_FIELD_MASK  0x00000008
+#define DQM_DQMOL_SIZE_Q_DISABLE_OFFLOAD_FIELD_WIDTH 1
+#define DQM_DQMOL_SIZE_Q_DISABLE_OFFLOAD_FIELD_SHIFT 3
+
+extern const ru_field_rec DQM_DQMOL_SIZE_RESERVED1_FIELD;
+#define DQM_DQMOL_SIZE_RESERVED1_FIELD_MASK  0x00000004
+#define DQM_DQMOL_SIZE_RESERVED1_FIELD_WIDTH 1
+#define DQM_DQMOL_SIZE_RESERVED1_FIELD_SHIFT 2
+
+extern const ru_field_rec DQM_DQMOL_SIZE_Q_TKN_SIZE_FIELD;
+#define DQM_DQMOL_SIZE_Q_TKN_SIZE_FIELD_MASK  0x00000003
+#define DQM_DQMOL_SIZE_Q_TKN_SIZE_FIELD_WIDTH 2
+#define DQM_DQMOL_SIZE_Q_TKN_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_DQMOL_CFGA_Q_SIZE_FIELD;
+#define DQM_DQMOL_CFGA_Q_SIZE_FIELD_MASK  0xffff0000
+#define DQM_DQMOL_CFGA_Q_SIZE_FIELD_WIDTH 16
+#define DQM_DQMOL_CFGA_Q_SIZE_FIELD_SHIFT 16
+
+extern const ru_field_rec DQM_DQMOL_CFGA_Q_START_ADDR_FIELD;
+#define DQM_DQMOL_CFGA_Q_START_ADDR_FIELD_MASK  0x0000ffff
+#define DQM_DQMOL_CFGA_Q_START_ADDR_FIELD_WIDTH 16
+#define DQM_DQMOL_CFGA_Q_START_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_DQMOL_CFGB_ENABLE_FIELD;
+#define DQM_DQMOL_CFGB_ENABLE_FIELD_MASK  0x80000000
+#define DQM_DQMOL_CFGB_ENABLE_FIELD_WIDTH 1
+#define DQM_DQMOL_CFGB_ENABLE_FIELD_SHIFT 31
+
+extern const ru_field_rec DQM_DQMOL_CFGB_RESERVED0_FIELD;
+#define DQM_DQMOL_CFGB_RESERVED0_FIELD_MASK  0x7fffffff
+#define DQM_DQMOL_CFGB_RESERVED0_FIELD_WIDTH 31
+#define DQM_DQMOL_CFGB_RESERVED0_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_DQMOL_PUSHTOKEN_TOKEN_FIELD;
+#define DQM_DQMOL_PUSHTOKEN_TOKEN_FIELD_MASK  0xffffffff
+#define DQM_DQMOL_PUSHTOKEN_TOKEN_FIELD_WIDTH 32
+#define DQM_DQMOL_PUSHTOKEN_TOKEN_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_DQMOL_PUSHTOKENNEXT_TOKEN_FIELD;
+#define DQM_DQMOL_PUSHTOKENNEXT_TOKEN_FIELD_MASK  0xffffffff
+#define DQM_DQMOL_PUSHTOKENNEXT_TOKEN_FIELD_WIDTH 32
+#define DQM_DQMOL_PUSHTOKENNEXT_TOKEN_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_DQMOL_POPTOKEN_TOKEN_FIELD;
+#define DQM_DQMOL_POPTOKEN_TOKEN_FIELD_MASK  0xffffffff
+#define DQM_DQMOL_POPTOKEN_TOKEN_FIELD_WIDTH 32
+#define DQM_DQMOL_POPTOKEN_TOKEN_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_DQMOL_POPTOKENNEXT_TOKEN_FIELD;
+#define DQM_DQMOL_POPTOKENNEXT_TOKEN_FIELD_MASK  0xffffffff
+#define DQM_DQMOL_POPTOKENNEXT_TOKEN_FIELD_WIDTH 32
+#define DQM_DQMOL_POPTOKENNEXT_TOKEN_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_WORD0_DATA_FIELD;
+#define DQM_WORD0_DATA_FIELD_MASK  0xffffffff
+#define DQM_WORD0_DATA_FIELD_WIDTH 32
+#define DQM_WORD0_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_WORD1_DATA_FIELD;
+#define DQM_WORD1_DATA_FIELD_MASK  0xffffffff
+#define DQM_WORD1_DATA_FIELD_WIDTH 32
+#define DQM_WORD1_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_WORD2_DATA_FIELD;
+#define DQM_WORD2_DATA_FIELD_MASK  0xffffffff
+#define DQM_WORD2_DATA_FIELD_WIDTH 32
+#define DQM_WORD2_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec DQM_QueueSharedMem_qsmdata_DATA_FIELD;
+#define DQM_QueueSharedMem_qsmdata_DATA_FIELD_MASK  0xffffffff
+#define DQM_QueueSharedMem_qsmdata_DATA_FIELD_WIDTH 32
+#define DQM_QueueSharedMem_qsmdata_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_CTL_TP_MUX_CNTRL_FIELD;
+#define FPM_FPM_CTL_TP_MUX_CNTRL_FIELD_MASK  0xf8000000
+#define FPM_FPM_CTL_TP_MUX_CNTRL_FIELD_WIDTH 5
+#define FPM_FPM_CTL_TP_MUX_CNTRL_FIELD_SHIFT 27
+
+extern const ru_field_rec FPM_FPM_CTL_RESERVED0_FIELD;
+#define FPM_FPM_CTL_RESERVED0_FIELD_MASK  0x04000000
+#define FPM_FPM_CTL_RESERVED0_FIELD_WIDTH 1
+#define FPM_FPM_CTL_RESERVED0_FIELD_SHIFT 26
+
+extern const ru_field_rec FPM_FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_FIELD;
+#define FPM_FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_FIELD_MASK  0x02000000
+#define FPM_FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_FIELD_WIDTH 1
+#define FPM_FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_FIELD_SHIFT 25
+
+extern const ru_field_rec FPM_FPM_CTL_STOP_ALLOC_CACHE_LOAD_FIELD;
+#define FPM_FPM_CTL_STOP_ALLOC_CACHE_LOAD_FIELD_MASK  0x01000000
+#define FPM_FPM_CTL_STOP_ALLOC_CACHE_LOAD_FIELD_WIDTH 1
+#define FPM_FPM_CTL_STOP_ALLOC_CACHE_LOAD_FIELD_SHIFT 24
+
+extern const ru_field_rec FPM_FPM_CTL_RESERVED1_FIELD;
+#define FPM_FPM_CTL_RESERVED1_FIELD_MASK  0x00fc0000
+#define FPM_FPM_CTL_RESERVED1_FIELD_WIDTH 6
+#define FPM_FPM_CTL_RESERVED1_FIELD_SHIFT 18
+
+extern const ru_field_rec FPM_FPM_CTL_POOL2_ENABLE_FIELD;
+#define FPM_FPM_CTL_POOL2_ENABLE_FIELD_MASK  0x00020000
+#define FPM_FPM_CTL_POOL2_ENABLE_FIELD_WIDTH 1
+#define FPM_FPM_CTL_POOL2_ENABLE_FIELD_SHIFT 17
+
+extern const ru_field_rec FPM_FPM_CTL_POOL1_ENABLE_FIELD;
+#define FPM_FPM_CTL_POOL1_ENABLE_FIELD_MASK  0x00010000
+#define FPM_FPM_CTL_POOL1_ENABLE_FIELD_WIDTH 1
+#define FPM_FPM_CTL_POOL1_ENABLE_FIELD_SHIFT 16
+
+extern const ru_field_rec FPM_FPM_CTL_RESERVED2_FIELD;
+#define FPM_FPM_CTL_RESERVED2_FIELD_MASK  0x00008000
+#define FPM_FPM_CTL_RESERVED2_FIELD_WIDTH 1
+#define FPM_FPM_CTL_RESERVED2_FIELD_SHIFT 15
+
+extern const ru_field_rec FPM_FPM_CTL_FPM_BB_SOFT_RESET_FIELD;
+#define FPM_FPM_CTL_FPM_BB_SOFT_RESET_FIELD_MASK  0x00004000
+#define FPM_FPM_CTL_FPM_BB_SOFT_RESET_FIELD_WIDTH 1
+#define FPM_FPM_CTL_FPM_BB_SOFT_RESET_FIELD_SHIFT 14
+
+extern const ru_field_rec FPM_FPM_CTL_RESERVED3_FIELD;
+#define FPM_FPM_CTL_RESERVED3_FIELD_MASK  0x00003fe0
+#define FPM_FPM_CTL_RESERVED3_FIELD_WIDTH 9
+#define FPM_FPM_CTL_RESERVED3_FIELD_SHIFT 5
+
+extern const ru_field_rec FPM_FPM_CTL_INIT_MEM_FIELD;
+#define FPM_FPM_CTL_INIT_MEM_FIELD_MASK  0x00000010
+#define FPM_FPM_CTL_INIT_MEM_FIELD_WIDTH 1
+#define FPM_FPM_CTL_INIT_MEM_FIELD_SHIFT 4
+
+extern const ru_field_rec FPM_FPM_CTL_INIT_MEM_POOL2_FIELD;
+#define FPM_FPM_CTL_INIT_MEM_POOL2_FIELD_MASK  0x00000008
+#define FPM_FPM_CTL_INIT_MEM_POOL2_FIELD_WIDTH 1
+#define FPM_FPM_CTL_INIT_MEM_POOL2_FIELD_SHIFT 3
+
+extern const ru_field_rec FPM_FPM_CTL_RESERVED4_FIELD;
+#define FPM_FPM_CTL_RESERVED4_FIELD_MASK  0x00000007
+#define FPM_FPM_CTL_RESERVED4_FIELD_WIDTH 3
+#define FPM_FPM_CTL_RESERVED4_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_CFG1_RESERVED0_FIELD;
+#define FPM_FPM_CFG1_RESERVED0_FIELD_MASK  0xfffffffe
+#define FPM_FPM_CFG1_RESERVED0_FIELD_WIDTH 31
+#define FPM_FPM_CFG1_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec FPM_FPM_CFG1_POOL1_SEARCH_MODE_FIELD;
+#define FPM_FPM_CFG1_POOL1_SEARCH_MODE_FIELD_MASK  0x00000001
+#define FPM_FPM_CFG1_POOL1_SEARCH_MODE_FIELD_WIDTH 1
+#define FPM_FPM_CFG1_POOL1_SEARCH_MODE_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_WEIGHT_DDR1_FREE_WEIGHT_FIELD;
+#define FPM_FPM_WEIGHT_DDR1_FREE_WEIGHT_FIELD_MASK  0xff000000
+#define FPM_FPM_WEIGHT_DDR1_FREE_WEIGHT_FIELD_WIDTH 8
+#define FPM_FPM_WEIGHT_DDR1_FREE_WEIGHT_FIELD_SHIFT 24
+
+extern const ru_field_rec FPM_FPM_WEIGHT_DDR1_ALLOC_WEIGHT_FIELD;
+#define FPM_FPM_WEIGHT_DDR1_ALLOC_WEIGHT_FIELD_MASK  0x00ff0000
+#define FPM_FPM_WEIGHT_DDR1_ALLOC_WEIGHT_FIELD_WIDTH 8
+#define FPM_FPM_WEIGHT_DDR1_ALLOC_WEIGHT_FIELD_SHIFT 16
+
+extern const ru_field_rec FPM_FPM_WEIGHT_DDR0_FREE_WEIGHT_FIELD;
+#define FPM_FPM_WEIGHT_DDR0_FREE_WEIGHT_FIELD_MASK  0x0000ff00
+#define FPM_FPM_WEIGHT_DDR0_FREE_WEIGHT_FIELD_WIDTH 8
+#define FPM_FPM_WEIGHT_DDR0_FREE_WEIGHT_FIELD_SHIFT 8
+
+extern const ru_field_rec FPM_FPM_WEIGHT_DDR0_ALLOC_WEIGHT_FIELD;
+#define FPM_FPM_WEIGHT_DDR0_ALLOC_WEIGHT_FIELD_MASK  0x000000ff
+#define FPM_FPM_WEIGHT_DDR0_ALLOC_WEIGHT_FIELD_WIDTH 8
+#define FPM_FPM_WEIGHT_DDR0_ALLOC_WEIGHT_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_CFG_RESERVED0_FIELD;
+#define FPM_FPM_BB_CFG_RESERVED0_FIELD_MASK  0xfffffffc
+#define FPM_FPM_BB_CFG_RESERVED0_FIELD_WIDTH 30
+#define FPM_FPM_BB_CFG_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec FPM_FPM_BB_CFG_BB_DDR_SEL_FIELD;
+#define FPM_FPM_BB_CFG_BB_DDR_SEL_FIELD_MASK  0x00000003
+#define FPM_FPM_BB_CFG_BB_DDR_SEL_FIELD_WIDTH 2
+#define FPM_FPM_BB_CFG_BB_DDR_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_RESERVED0_FIELD;
+#define FPM_POOL1_INTR_MSK_RESERVED0_FIELD_MASK  0xffff8000
+#define FPM_POOL1_INTR_MSK_RESERVED0_FIELD_WIDTH 17
+#define FPM_POOL1_INTR_MSK_RESERVED0_FIELD_SHIFT 15
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_MASK  0x00004000
+#define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_SHIFT 14
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_MASK  0x00002000
+#define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_SHIFT 13
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_MASK  0x00001000
+#define FPM_POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_MASK  0x00000800
+#define FPM_POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_SHIFT 11
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_XON_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_XON_MSK_FIELD_MASK  0x00000400
+#define FPM_POOL1_INTR_MSK_XON_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_XON_MSK_FIELD_SHIFT 10
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_XOFF_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_XOFF_MSK_FIELD_MASK  0x00000200
+#define FPM_POOL1_INTR_MSK_XOFF_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_XOFF_MSK_FIELD_SHIFT 9
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_MASK  0x00000100
+#define FPM_POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_SHIFT 8
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_MASK  0x00000080
+#define FPM_POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_SHIFT 7
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_MASK  0x00000040
+#define FPM_POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_SHIFT 6
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_MASK  0x00000020
+#define FPM_POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_SHIFT 5
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_MASK  0x00000010
+#define FPM_POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_SHIFT 4
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_MASK  0x00000008
+#define FPM_POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_SHIFT 3
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_POOL_FULL_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_POOL_FULL_MSK_FIELD_MASK  0x00000004
+#define FPM_POOL1_INTR_MSK_POOL_FULL_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_POOL_FULL_MSK_FIELD_SHIFT 2
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_MASK  0x00000002
+#define FPM_POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_SHIFT 1
+
+extern const ru_field_rec FPM_POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD;
+#define FPM_POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_MASK  0x00000001
+#define FPM_POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_RESERVED0_FIELD;
+#define FPM_POOL1_INTR_STS_RESERVED0_FIELD_MASK  0xffff8000
+#define FPM_POOL1_INTR_STS_RESERVED0_FIELD_WIDTH 17
+#define FPM_POOL1_INTR_STS_RESERVED0_FIELD_SHIFT 15
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD;
+#define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_MASK  0x00004000
+#define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_SHIFT 14
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD;
+#define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_MASK  0x00002000
+#define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_SHIFT 13
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD;
+#define FPM_POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_MASK  0x00001000
+#define FPM_POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD;
+#define FPM_POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_MASK  0x00000800
+#define FPM_POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_SHIFT 11
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_XON_STATE_STS_FIELD;
+#define FPM_POOL1_INTR_STS_XON_STATE_STS_FIELD_MASK  0x00000400
+#define FPM_POOL1_INTR_STS_XON_STATE_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_XON_STATE_STS_FIELD_SHIFT 10
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_XOFF_STATE_STS_FIELD;
+#define FPM_POOL1_INTR_STS_XOFF_STATE_STS_FIELD_MASK  0x00000200
+#define FPM_POOL1_INTR_STS_XOFF_STATE_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_XOFF_STATE_STS_FIELD_SHIFT 9
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_MEMORY_CORRUPT_STS_FIELD;
+#define FPM_POOL1_INTR_STS_MEMORY_CORRUPT_STS_FIELD_MASK  0x00000100
+#define FPM_POOL1_INTR_STS_MEMORY_CORRUPT_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_MEMORY_CORRUPT_STS_FIELD_SHIFT 8
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD;
+#define FPM_POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_MASK  0x00000080
+#define FPM_POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_SHIFT 7
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD;
+#define FPM_POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_MASK  0x00000040
+#define FPM_POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_SHIFT 6
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD;
+#define FPM_POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_MASK  0x00000020
+#define FPM_POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_SHIFT 5
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD;
+#define FPM_POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_MASK  0x00000010
+#define FPM_POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_SHIFT 4
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD;
+#define FPM_POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_MASK  0x00000008
+#define FPM_POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_SHIFT 3
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_POOL_FULL_STS_FIELD;
+#define FPM_POOL1_INTR_STS_POOL_FULL_STS_FIELD_MASK  0x00000004
+#define FPM_POOL1_INTR_STS_POOL_FULL_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_POOL_FULL_STS_FIELD_SHIFT 2
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_FREE_FIFO_FULL_STS_FIELD;
+#define FPM_POOL1_INTR_STS_FREE_FIFO_FULL_STS_FIELD_MASK  0x00000002
+#define FPM_POOL1_INTR_STS_FREE_FIFO_FULL_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_FREE_FIFO_FULL_STS_FIELD_SHIFT 1
+
+extern const ru_field_rec FPM_POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD;
+#define FPM_POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_MASK  0x00000001
+#define FPM_POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_WIDTH 1
+#define FPM_POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_STALL_MSK_RESERVED0_FIELD;
+#define FPM_POOL1_STALL_MSK_RESERVED0_FIELD_MASK  0xfffffe00
+#define FPM_POOL1_STALL_MSK_RESERVED0_FIELD_WIDTH 23
+#define FPM_POOL1_STALL_MSK_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec FPM_POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD;
+#define FPM_POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_MASK  0x00000100
+#define FPM_POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_SHIFT 8
+
+extern const ru_field_rec FPM_POOL1_STALL_MSK_RESERVED1_FIELD;
+#define FPM_POOL1_STALL_MSK_RESERVED1_FIELD_MASK  0x00000080
+#define FPM_POOL1_STALL_MSK_RESERVED1_FIELD_WIDTH 1
+#define FPM_POOL1_STALL_MSK_RESERVED1_FIELD_SHIFT 7
+
+extern const ru_field_rec FPM_POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD;
+#define FPM_POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_MASK  0x00000040
+#define FPM_POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_SHIFT 6
+
+extern const ru_field_rec FPM_POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD;
+#define FPM_POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_MASK  0x00000020
+#define FPM_POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_SHIFT 5
+
+extern const ru_field_rec FPM_POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD;
+#define FPM_POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_MASK  0x00000010
+#define FPM_POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_SHIFT 4
+
+extern const ru_field_rec FPM_POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD;
+#define FPM_POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_MASK  0x00000008
+#define FPM_POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_WIDTH 1
+#define FPM_POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_SHIFT 3
+
+extern const ru_field_rec FPM_POOL1_STALL_MSK_RESERVED2_FIELD;
+#define FPM_POOL1_STALL_MSK_RESERVED2_FIELD_MASK  0x00000007
+#define FPM_POOL1_STALL_MSK_RESERVED2_FIELD_WIDTH 3
+#define FPM_POOL1_STALL_MSK_RESERVED2_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_RESERVED0_FIELD;
+#define FPM_POOL2_INTR_MSK_RESERVED0_FIELD_MASK  0xffff8000
+#define FPM_POOL2_INTR_MSK_RESERVED0_FIELD_WIDTH 17
+#define FPM_POOL2_INTR_MSK_RESERVED0_FIELD_SHIFT 15
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_MASK  0x00004000
+#define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_SHIFT 14
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_MASK  0x00002000
+#define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_SHIFT 13
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_MASK  0x00001000
+#define FPM_POOL2_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_MASK  0x00000800
+#define FPM_POOL2_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_SHIFT 11
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_XON_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_XON_MSK_FIELD_MASK  0x00000400
+#define FPM_POOL2_INTR_MSK_XON_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_XON_MSK_FIELD_SHIFT 10
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_XOFF_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_XOFF_MSK_FIELD_MASK  0x00000200
+#define FPM_POOL2_INTR_MSK_XOFF_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_XOFF_MSK_FIELD_SHIFT 9
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_MASK  0x00000100
+#define FPM_POOL2_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_SHIFT 8
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_MASK  0x00000080
+#define FPM_POOL2_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_SHIFT 7
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_MASK  0x00000040
+#define FPM_POOL2_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_SHIFT 6
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_MASK  0x00000020
+#define FPM_POOL2_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_SHIFT 5
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_MASK  0x00000010
+#define FPM_POOL2_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_SHIFT 4
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_MASK  0x00000008
+#define FPM_POOL2_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_SHIFT 3
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_POOL_FULL_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_POOL_FULL_MSK_FIELD_MASK  0x00000004
+#define FPM_POOL2_INTR_MSK_POOL_FULL_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_POOL_FULL_MSK_FIELD_SHIFT 2
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_MASK  0x00000002
+#define FPM_POOL2_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_SHIFT 1
+
+extern const ru_field_rec FPM_POOL2_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD;
+#define FPM_POOL2_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_MASK  0x00000001
+#define FPM_POOL2_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_RESERVED0_FIELD;
+#define FPM_POOL2_INTR_STS_RESERVED0_FIELD_MASK  0xffff8000
+#define FPM_POOL2_INTR_STS_RESERVED0_FIELD_WIDTH 17
+#define FPM_POOL2_INTR_STS_RESERVED0_FIELD_SHIFT 15
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD;
+#define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_MASK  0x00004000
+#define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_SHIFT 14
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD;
+#define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_MASK  0x00002000
+#define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_SHIFT 13
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD;
+#define FPM_POOL2_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_MASK  0x00001000
+#define FPM_POOL2_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD;
+#define FPM_POOL2_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_MASK  0x00000800
+#define FPM_POOL2_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_SHIFT 11
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_XON_STATE_STS_FIELD;
+#define FPM_POOL2_INTR_STS_XON_STATE_STS_FIELD_MASK  0x00000400
+#define FPM_POOL2_INTR_STS_XON_STATE_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_XON_STATE_STS_FIELD_SHIFT 10
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_XOFF_STATE_STS_FIELD;
+#define FPM_POOL2_INTR_STS_XOFF_STATE_STS_FIELD_MASK  0x00000200
+#define FPM_POOL2_INTR_STS_XOFF_STATE_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_XOFF_STATE_STS_FIELD_SHIFT 9
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_MEMORY_CORRUPT_STS_FIELD;
+#define FPM_POOL2_INTR_STS_MEMORY_CORRUPT_STS_FIELD_MASK  0x00000100
+#define FPM_POOL2_INTR_STS_MEMORY_CORRUPT_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_MEMORY_CORRUPT_STS_FIELD_SHIFT 8
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD;
+#define FPM_POOL2_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_MASK  0x00000080
+#define FPM_POOL2_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_SHIFT 7
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD;
+#define FPM_POOL2_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_MASK  0x00000040
+#define FPM_POOL2_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_SHIFT 6
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD;
+#define FPM_POOL2_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_MASK  0x00000020
+#define FPM_POOL2_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_SHIFT 5
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD;
+#define FPM_POOL2_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_MASK  0x00000010
+#define FPM_POOL2_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_SHIFT 4
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD;
+#define FPM_POOL2_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_MASK  0x00000008
+#define FPM_POOL2_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_SHIFT 3
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_POOL_FULL_STS_FIELD;
+#define FPM_POOL2_INTR_STS_POOL_FULL_STS_FIELD_MASK  0x00000004
+#define FPM_POOL2_INTR_STS_POOL_FULL_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_POOL_FULL_STS_FIELD_SHIFT 2
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_FREE_FIFO_FULL_STS_FIELD;
+#define FPM_POOL2_INTR_STS_FREE_FIFO_FULL_STS_FIELD_MASK  0x00000002
+#define FPM_POOL2_INTR_STS_FREE_FIFO_FULL_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_FREE_FIFO_FULL_STS_FIELD_SHIFT 1
+
+extern const ru_field_rec FPM_POOL2_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD;
+#define FPM_POOL2_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_MASK  0x00000001
+#define FPM_POOL2_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_WIDTH 1
+#define FPM_POOL2_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_STALL_MSK_RESERVED0_FIELD;
+#define FPM_POOL2_STALL_MSK_RESERVED0_FIELD_MASK  0xfffffe00
+#define FPM_POOL2_STALL_MSK_RESERVED0_FIELD_WIDTH 23
+#define FPM_POOL2_STALL_MSK_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec FPM_POOL2_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD;
+#define FPM_POOL2_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_MASK  0x00000100
+#define FPM_POOL2_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_SHIFT 8
+
+extern const ru_field_rec FPM_POOL2_STALL_MSK_RESERVED1_FIELD;
+#define FPM_POOL2_STALL_MSK_RESERVED1_FIELD_MASK  0x00000080
+#define FPM_POOL2_STALL_MSK_RESERVED1_FIELD_WIDTH 1
+#define FPM_POOL2_STALL_MSK_RESERVED1_FIELD_SHIFT 7
+
+extern const ru_field_rec FPM_POOL2_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD;
+#define FPM_POOL2_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_MASK  0x00000040
+#define FPM_POOL2_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_SHIFT 6
+
+extern const ru_field_rec FPM_POOL2_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD;
+#define FPM_POOL2_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_MASK  0x00000020
+#define FPM_POOL2_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_SHIFT 5
+
+extern const ru_field_rec FPM_POOL2_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD;
+#define FPM_POOL2_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_MASK  0x00000010
+#define FPM_POOL2_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_SHIFT 4
+
+extern const ru_field_rec FPM_POOL2_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD;
+#define FPM_POOL2_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_MASK  0x00000008
+#define FPM_POOL2_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_WIDTH 1
+#define FPM_POOL2_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_SHIFT 3
+
+extern const ru_field_rec FPM_POOL2_STALL_MSK_RESERVED2_FIELD;
+#define FPM_POOL2_STALL_MSK_RESERVED2_FIELD_MASK  0x00000007
+#define FPM_POOL2_STALL_MSK_RESERVED2_FIELD_WIDTH 3
+#define FPM_POOL2_STALL_MSK_RESERVED2_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_CFG1_RESERVED0_FIELD;
+#define FPM_POOL1_CFG1_RESERVED0_FIELD_MASK  0xf8000000
+#define FPM_POOL1_CFG1_RESERVED0_FIELD_WIDTH 5
+#define FPM_POOL1_CFG1_RESERVED0_FIELD_SHIFT 27
+
+extern const ru_field_rec FPM_POOL1_CFG1_FPM_BUF_SIZE_FIELD;
+#define FPM_POOL1_CFG1_FPM_BUF_SIZE_FIELD_MASK  0x07000000
+#define FPM_POOL1_CFG1_FPM_BUF_SIZE_FIELD_WIDTH 3
+#define FPM_POOL1_CFG1_FPM_BUF_SIZE_FIELD_SHIFT 24
+
+extern const ru_field_rec FPM_POOL1_CFG1_RESERVED1_FIELD;
+#define FPM_POOL1_CFG1_RESERVED1_FIELD_MASK  0x00ffffff
+#define FPM_POOL1_CFG1_RESERVED1_FIELD_WIDTH 24
+#define FPM_POOL1_CFG1_RESERVED1_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_CFG2_POOL_BASE_ADDRESS_FIELD;
+#define FPM_POOL1_CFG2_POOL_BASE_ADDRESS_FIELD_MASK  0xfffffffc
+#define FPM_POOL1_CFG2_POOL_BASE_ADDRESS_FIELD_WIDTH 30
+#define FPM_POOL1_CFG2_POOL_BASE_ADDRESS_FIELD_SHIFT 2
+
+extern const ru_field_rec FPM_POOL1_CFG2_RESERVED0_FIELD;
+#define FPM_POOL1_CFG2_RESERVED0_FIELD_MASK  0x00000003
+#define FPM_POOL1_CFG2_RESERVED0_FIELD_WIDTH 2
+#define FPM_POOL1_CFG2_RESERVED0_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_FIELD;
+#define FPM_POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_FIELD_MASK  0xfffffffc
+#define FPM_POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_FIELD_WIDTH 30
+#define FPM_POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_FIELD_SHIFT 2
+
+extern const ru_field_rec FPM_POOL1_CFG3_RESERVED0_FIELD;
+#define FPM_POOL1_CFG3_RESERVED0_FIELD_MASK  0x00000003
+#define FPM_POOL1_CFG3_RESERVED0_FIELD_WIDTH 2
+#define FPM_POOL1_CFG3_RESERVED0_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_STAT1_OVRFL_FIELD;
+#define FPM_POOL1_STAT1_OVRFL_FIELD_MASK  0xffff0000
+#define FPM_POOL1_STAT1_OVRFL_FIELD_WIDTH 16
+#define FPM_POOL1_STAT1_OVRFL_FIELD_SHIFT 16
+
+extern const ru_field_rec FPM_POOL1_STAT1_UNDRFL_FIELD;
+#define FPM_POOL1_STAT1_UNDRFL_FIELD_MASK  0x0000ffff
+#define FPM_POOL1_STAT1_UNDRFL_FIELD_WIDTH 16
+#define FPM_POOL1_STAT1_UNDRFL_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_STAT2_POOL_FULL_FIELD;
+#define FPM_POOL1_STAT2_POOL_FULL_FIELD_MASK  0x80000000
+#define FPM_POOL1_STAT2_POOL_FULL_FIELD_WIDTH 1
+#define FPM_POOL1_STAT2_POOL_FULL_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL1_STAT2_RESERVED0_FIELD;
+#define FPM_POOL1_STAT2_RESERVED0_FIELD_MASK  0x40000000
+#define FPM_POOL1_STAT2_RESERVED0_FIELD_WIDTH 1
+#define FPM_POOL1_STAT2_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec FPM_POOL1_STAT2_FREE_FIFO_FULL_FIELD;
+#define FPM_POOL1_STAT2_FREE_FIFO_FULL_FIELD_MASK  0x20000000
+#define FPM_POOL1_STAT2_FREE_FIFO_FULL_FIELD_WIDTH 1
+#define FPM_POOL1_STAT2_FREE_FIFO_FULL_FIELD_SHIFT 29
+
+extern const ru_field_rec FPM_POOL1_STAT2_FREE_FIFO_EMPTY_FIELD;
+#define FPM_POOL1_STAT2_FREE_FIFO_EMPTY_FIELD_MASK  0x10000000
+#define FPM_POOL1_STAT2_FREE_FIFO_EMPTY_FIELD_WIDTH 1
+#define FPM_POOL1_STAT2_FREE_FIFO_EMPTY_FIELD_SHIFT 28
+
+extern const ru_field_rec FPM_POOL1_STAT2_ALLOC_FIFO_FULL_FIELD;
+#define FPM_POOL1_STAT2_ALLOC_FIFO_FULL_FIELD_MASK  0x08000000
+#define FPM_POOL1_STAT2_ALLOC_FIFO_FULL_FIELD_WIDTH 1
+#define FPM_POOL1_STAT2_ALLOC_FIFO_FULL_FIELD_SHIFT 27
+
+extern const ru_field_rec FPM_POOL1_STAT2_ALLOC_FIFO_EMPTY_FIELD;
+#define FPM_POOL1_STAT2_ALLOC_FIFO_EMPTY_FIELD_MASK  0x04000000
+#define FPM_POOL1_STAT2_ALLOC_FIFO_EMPTY_FIELD_WIDTH 1
+#define FPM_POOL1_STAT2_ALLOC_FIFO_EMPTY_FIELD_SHIFT 26
+
+extern const ru_field_rec FPM_POOL1_STAT2_RESERVED1_FIELD;
+#define FPM_POOL1_STAT2_RESERVED1_FIELD_MASK  0x03fc0000
+#define FPM_POOL1_STAT2_RESERVED1_FIELD_WIDTH 8
+#define FPM_POOL1_STAT2_RESERVED1_FIELD_SHIFT 18
+
+extern const ru_field_rec FPM_POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD;
+#define FPM_POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_MASK  0x0003ffff
+#define FPM_POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_WIDTH 18
+#define FPM_POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_STAT3_RESERVED0_FIELD;
+#define FPM_POOL1_STAT3_RESERVED0_FIELD_MASK  0xfffc0000
+#define FPM_POOL1_STAT3_RESERVED0_FIELD_WIDTH 14
+#define FPM_POOL1_STAT3_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec FPM_POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD;
+#define FPM_POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_MASK  0x0003ffff
+#define FPM_POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_WIDTH 18
+#define FPM_POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_STAT4_RESERVED0_FIELD;
+#define FPM_POOL1_STAT4_RESERVED0_FIELD_MASK  0xfffc0000
+#define FPM_POOL1_STAT4_RESERVED0_FIELD_WIDTH 14
+#define FPM_POOL1_STAT4_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec FPM_POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD;
+#define FPM_POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_MASK  0x0003ffff
+#define FPM_POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_WIDTH 18
+#define FPM_POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD;
+#define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_MASK  0x80000000
+#define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_WIDTH 1
+#define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD;
+#define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_MASK  0x7fffffff
+#define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_WIDTH 31
+#define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_STAT6_INVALID_FREE_TOKEN_VALID_FIELD;
+#define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_MASK  0x80000000
+#define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_WIDTH 1
+#define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL1_STAT6_INVALID_FREE_TOKEN_FIELD;
+#define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_FIELD_MASK  0x7fffffff
+#define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_FIELD_WIDTH 31
+#define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD;
+#define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_MASK  0x80000000
+#define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_WIDTH 1
+#define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_FIELD;
+#define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_FIELD_MASK  0x7fffffff
+#define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_FIELD_WIDTH 31
+#define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_STAT8_RESERVED0_FIELD;
+#define FPM_POOL1_STAT8_RESERVED0_FIELD_MASK  0xfffc0000
+#define FPM_POOL1_STAT8_RESERVED0_FIELD_WIDTH 14
+#define FPM_POOL1_STAT8_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec FPM_POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD;
+#define FPM_POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_MASK  0x0003ffff
+#define FPM_POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_WIDTH 18
+#define FPM_POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_STAT1_OVRFL_FIELD;
+#define FPM_POOL2_STAT1_OVRFL_FIELD_MASK  0xffff0000
+#define FPM_POOL2_STAT1_OVRFL_FIELD_WIDTH 16
+#define FPM_POOL2_STAT1_OVRFL_FIELD_SHIFT 16
+
+extern const ru_field_rec FPM_POOL2_STAT1_UNDRFL_FIELD;
+#define FPM_POOL2_STAT1_UNDRFL_FIELD_MASK  0x0000ffff
+#define FPM_POOL2_STAT1_UNDRFL_FIELD_WIDTH 16
+#define FPM_POOL2_STAT1_UNDRFL_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_STAT2_POOL_FULL_FIELD;
+#define FPM_POOL2_STAT2_POOL_FULL_FIELD_MASK  0x80000000
+#define FPM_POOL2_STAT2_POOL_FULL_FIELD_WIDTH 1
+#define FPM_POOL2_STAT2_POOL_FULL_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL2_STAT2_RESERVED0_FIELD;
+#define FPM_POOL2_STAT2_RESERVED0_FIELD_MASK  0x40000000
+#define FPM_POOL2_STAT2_RESERVED0_FIELD_WIDTH 1
+#define FPM_POOL2_STAT2_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec FPM_POOL2_STAT2_FREE_FIFO_FULL_FIELD;
+#define FPM_POOL2_STAT2_FREE_FIFO_FULL_FIELD_MASK  0x20000000
+#define FPM_POOL2_STAT2_FREE_FIFO_FULL_FIELD_WIDTH 1
+#define FPM_POOL2_STAT2_FREE_FIFO_FULL_FIELD_SHIFT 29
+
+extern const ru_field_rec FPM_POOL2_STAT2_FREE_FIFO_EMPTY_FIELD;
+#define FPM_POOL2_STAT2_FREE_FIFO_EMPTY_FIELD_MASK  0x10000000
+#define FPM_POOL2_STAT2_FREE_FIFO_EMPTY_FIELD_WIDTH 1
+#define FPM_POOL2_STAT2_FREE_FIFO_EMPTY_FIELD_SHIFT 28
+
+extern const ru_field_rec FPM_POOL2_STAT2_ALLOC_FIFO_FULL_FIELD;
+#define FPM_POOL2_STAT2_ALLOC_FIFO_FULL_FIELD_MASK  0x08000000
+#define FPM_POOL2_STAT2_ALLOC_FIFO_FULL_FIELD_WIDTH 1
+#define FPM_POOL2_STAT2_ALLOC_FIFO_FULL_FIELD_SHIFT 27
+
+extern const ru_field_rec FPM_POOL2_STAT2_ALLOC_FIFO_EMPTY_FIELD;
+#define FPM_POOL2_STAT2_ALLOC_FIFO_EMPTY_FIELD_MASK  0x04000000
+#define FPM_POOL2_STAT2_ALLOC_FIFO_EMPTY_FIELD_WIDTH 1
+#define FPM_POOL2_STAT2_ALLOC_FIFO_EMPTY_FIELD_SHIFT 26
+
+extern const ru_field_rec FPM_POOL2_STAT2_RESERVED1_FIELD;
+#define FPM_POOL2_STAT2_RESERVED1_FIELD_MASK  0x03fc0000
+#define FPM_POOL2_STAT2_RESERVED1_FIELD_WIDTH 8
+#define FPM_POOL2_STAT2_RESERVED1_FIELD_SHIFT 18
+
+extern const ru_field_rec FPM_POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD;
+#define FPM_POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_MASK  0x0003ffff
+#define FPM_POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_WIDTH 18
+#define FPM_POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_STAT3_RESERVED0_FIELD;
+#define FPM_POOL2_STAT3_RESERVED0_FIELD_MASK  0xfffc0000
+#define FPM_POOL2_STAT3_RESERVED0_FIELD_WIDTH 14
+#define FPM_POOL2_STAT3_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec FPM_POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD;
+#define FPM_POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_MASK  0x0003ffff
+#define FPM_POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_WIDTH 18
+#define FPM_POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_STAT4_RESERVED0_FIELD;
+#define FPM_POOL2_STAT4_RESERVED0_FIELD_MASK  0xfffc0000
+#define FPM_POOL2_STAT4_RESERVED0_FIELD_WIDTH 14
+#define FPM_POOL2_STAT4_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec FPM_POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD;
+#define FPM_POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_MASK  0x0003ffff
+#define FPM_POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_WIDTH 18
+#define FPM_POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD;
+#define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_MASK  0x80000000
+#define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_WIDTH 1
+#define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD;
+#define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_MASK  0x7fffffff
+#define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_WIDTH 31
+#define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_STAT6_INVALID_FREE_TOKEN_VALID_FIELD;
+#define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_MASK  0x80000000
+#define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_WIDTH 1
+#define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL2_STAT6_INVALID_FREE_TOKEN_FIELD;
+#define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_FIELD_MASK  0x7fffffff
+#define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_FIELD_WIDTH 31
+#define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD;
+#define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_MASK  0x80000000
+#define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_WIDTH 1
+#define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_FIELD;
+#define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_FIELD_MASK  0x7fffffff
+#define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_FIELD_WIDTH 31
+#define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_STAT8_RESERVED0_FIELD;
+#define FPM_POOL2_STAT8_RESERVED0_FIELD_MASK  0xfffc0000
+#define FPM_POOL2_STAT8_RESERVED0_FIELD_WIDTH 14
+#define FPM_POOL2_STAT8_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec FPM_POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD;
+#define FPM_POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_MASK  0x0003ffff
+#define FPM_POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_WIDTH 18
+#define FPM_POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_XON_XOFF_CFG_XON_THRESHOLD_FIELD;
+#define FPM_POOL1_XON_XOFF_CFG_XON_THRESHOLD_FIELD_MASK  0xffff0000
+#define FPM_POOL1_XON_XOFF_CFG_XON_THRESHOLD_FIELD_WIDTH 16
+#define FPM_POOL1_XON_XOFF_CFG_XON_THRESHOLD_FIELD_SHIFT 16
+
+extern const ru_field_rec FPM_POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_FIELD;
+#define FPM_POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_FIELD_MASK  0x0000ffff
+#define FPM_POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_FIELD_WIDTH 16
+#define FPM_POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_NOT_EMPTY_CFG_RESERVED0_FIELD;
+#define FPM_FPM_NOT_EMPTY_CFG_RESERVED0_FIELD_MASK  0xffffffc0
+#define FPM_FPM_NOT_EMPTY_CFG_RESERVED0_FIELD_WIDTH 26
+#define FPM_FPM_NOT_EMPTY_CFG_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec FPM_FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_FIELD;
+#define FPM_FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_FIELD_MASK  0x0000003f
+#define FPM_FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_FIELD_WIDTH 6
+#define FPM_FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_MEM_CTL_MEM_WR_FIELD;
+#define FPM_MEM_CTL_MEM_WR_FIELD_MASK  0x80000000
+#define FPM_MEM_CTL_MEM_WR_FIELD_WIDTH 1
+#define FPM_MEM_CTL_MEM_WR_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_MEM_CTL_MEM_RD_FIELD;
+#define FPM_MEM_CTL_MEM_RD_FIELD_MASK  0x40000000
+#define FPM_MEM_CTL_MEM_RD_FIELD_WIDTH 1
+#define FPM_MEM_CTL_MEM_RD_FIELD_SHIFT 30
+
+extern const ru_field_rec FPM_MEM_CTL_MEM_SEL_FIELD;
+#define FPM_MEM_CTL_MEM_SEL_FIELD_MASK  0x30000000
+#define FPM_MEM_CTL_MEM_SEL_FIELD_WIDTH 2
+#define FPM_MEM_CTL_MEM_SEL_FIELD_SHIFT 28
+
+extern const ru_field_rec FPM_MEM_CTL_RESERVED0_FIELD;
+#define FPM_MEM_CTL_RESERVED0_FIELD_MASK  0x0ffc0000
+#define FPM_MEM_CTL_RESERVED0_FIELD_WIDTH 10
+#define FPM_MEM_CTL_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec FPM_MEM_CTL_MEM_ADDR_FIELD;
+#define FPM_MEM_CTL_MEM_ADDR_FIELD_MASK  0x0003fffc
+#define FPM_MEM_CTL_MEM_ADDR_FIELD_WIDTH 16
+#define FPM_MEM_CTL_MEM_ADDR_FIELD_SHIFT 2
+
+extern const ru_field_rec FPM_MEM_CTL_RESERVED1_FIELD;
+#define FPM_MEM_CTL_RESERVED1_FIELD_MASK  0x00000003
+#define FPM_MEM_CTL_RESERVED1_FIELD_WIDTH 2
+#define FPM_MEM_CTL_RESERVED1_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_MEM_DATA1_MEM_DATA1_FIELD;
+#define FPM_MEM_DATA1_MEM_DATA1_FIELD_MASK  0xffffffff
+#define FPM_MEM_DATA1_MEM_DATA1_FIELD_WIDTH 32
+#define FPM_MEM_DATA1_MEM_DATA1_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_MEM_DATA2_MEM_DATA2_FIELD;
+#define FPM_MEM_DATA2_MEM_DATA2_FIELD_MASK  0xffffffff
+#define FPM_MEM_DATA2_MEM_DATA2_FIELD_WIDTH 32
+#define FPM_MEM_DATA2_MEM_DATA2_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_RESERVED0_FIELD;
+#define FPM_TOKEN_RECOVER_CTL_RESERVED0_FIELD_MASK  0xffffff80
+#define FPM_TOKEN_RECOVER_CTL_RESERVED0_FIELD_WIDTH 25
+#define FPM_TOKEN_RECOVER_CTL_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_CLR_RECOVERED_TOKEN_COUNT_FIELD;
+#define FPM_TOKEN_RECOVER_CTL_CLR_RECOVERED_TOKEN_COUNT_FIELD_MASK  0x00000040
+#define FPM_TOKEN_RECOVER_CTL_CLR_RECOVERED_TOKEN_COUNT_FIELD_WIDTH 1
+#define FPM_TOKEN_RECOVER_CTL_CLR_RECOVERED_TOKEN_COUNT_FIELD_SHIFT 6
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_CLR_EXPIRED_TOKEN_COUNT_FIELD;
+#define FPM_TOKEN_RECOVER_CTL_CLR_EXPIRED_TOKEN_COUNT_FIELD_MASK  0x00000020
+#define FPM_TOKEN_RECOVER_CTL_CLR_EXPIRED_TOKEN_COUNT_FIELD_WIDTH 1
+#define FPM_TOKEN_RECOVER_CTL_CLR_EXPIRED_TOKEN_COUNT_FIELD_SHIFT 5
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_FORCE_TOKEN_RECLAIM_FIELD;
+#define FPM_TOKEN_RECOVER_CTL_FORCE_TOKEN_RECLAIM_FIELD_MASK  0x00000010
+#define FPM_TOKEN_RECOVER_CTL_FORCE_TOKEN_RECLAIM_FIELD_WIDTH 1
+#define FPM_TOKEN_RECOVER_CTL_FORCE_TOKEN_RECLAIM_FIELD_SHIFT 4
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_TOKEN_RECLAIM_ENA_FIELD;
+#define FPM_TOKEN_RECOVER_CTL_TOKEN_RECLAIM_ENA_FIELD_MASK  0x00000008
+#define FPM_TOKEN_RECOVER_CTL_TOKEN_RECLAIM_ENA_FIELD_WIDTH 1
+#define FPM_TOKEN_RECOVER_CTL_TOKEN_RECLAIM_ENA_FIELD_SHIFT 3
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_TOKEN_REMARK_ENA_FIELD;
+#define FPM_TOKEN_RECOVER_CTL_TOKEN_REMARK_ENA_FIELD_MASK  0x00000004
+#define FPM_TOKEN_RECOVER_CTL_TOKEN_REMARK_ENA_FIELD_WIDTH 1
+#define FPM_TOKEN_RECOVER_CTL_TOKEN_REMARK_ENA_FIELD_SHIFT 2
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_SINGLE_PASS_ENA_FIELD;
+#define FPM_TOKEN_RECOVER_CTL_SINGLE_PASS_ENA_FIELD_MASK  0x00000002
+#define FPM_TOKEN_RECOVER_CTL_SINGLE_PASS_ENA_FIELD_WIDTH 1
+#define FPM_TOKEN_RECOVER_CTL_SINGLE_PASS_ENA_FIELD_SHIFT 1
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_TOKEN_RECOVER_ENA_FIELD;
+#define FPM_TOKEN_RECOVER_CTL_TOKEN_RECOVER_ENA_FIELD_MASK  0x00000001
+#define FPM_TOKEN_RECOVER_CTL_TOKEN_RECOVER_ENA_FIELD_WIDTH 1
+#define FPM_TOKEN_RECOVER_CTL_TOKEN_RECOVER_ENA_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_SHORT_AGING_TIMER_TIMER_FIELD;
+#define FPM_SHORT_AGING_TIMER_TIMER_FIELD_MASK  0xffffffff
+#define FPM_SHORT_AGING_TIMER_TIMER_FIELD_WIDTH 32
+#define FPM_SHORT_AGING_TIMER_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_LONG_AGING_TIMER_TIMER_FIELD;
+#define FPM_LONG_AGING_TIMER_TIMER_FIELD_MASK  0xffffffff
+#define FPM_LONG_AGING_TIMER_TIMER_FIELD_WIDTH 32
+#define FPM_LONG_AGING_TIMER_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_CACHE_RECYCLE_TIMER_RESERVED0_FIELD;
+#define FPM_CACHE_RECYCLE_TIMER_RESERVED0_FIELD_MASK  0xffff0000
+#define FPM_CACHE_RECYCLE_TIMER_RESERVED0_FIELD_WIDTH 16
+#define FPM_CACHE_RECYCLE_TIMER_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec FPM_CACHE_RECYCLE_TIMER_RECYCLE_TIMER_FIELD;
+#define FPM_CACHE_RECYCLE_TIMER_RECYCLE_TIMER_FIELD_MASK  0x0000ffff
+#define FPM_CACHE_RECYCLE_TIMER_RECYCLE_TIMER_FIELD_WIDTH 16
+#define FPM_CACHE_RECYCLE_TIMER_RECYCLE_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_EXPIRED_TOKEN_COUNT_POOL1_COUNT_FIELD;
+#define FPM_EXPIRED_TOKEN_COUNT_POOL1_COUNT_FIELD_MASK  0xffffffff
+#define FPM_EXPIRED_TOKEN_COUNT_POOL1_COUNT_FIELD_WIDTH 32
+#define FPM_EXPIRED_TOKEN_COUNT_POOL1_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_RECOVERED_TOKEN_COUNT_POOL1_COUNT_FIELD;
+#define FPM_RECOVERED_TOKEN_COUNT_POOL1_COUNT_FIELD_MASK  0xffffffff
+#define FPM_RECOVERED_TOKEN_COUNT_POOL1_COUNT_FIELD_WIDTH 32
+#define FPM_RECOVERED_TOKEN_COUNT_POOL1_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_EXPIRED_TOKEN_COUNT_POOL2_COUNT_FIELD;
+#define FPM_EXPIRED_TOKEN_COUNT_POOL2_COUNT_FIELD_MASK  0xffffffff
+#define FPM_EXPIRED_TOKEN_COUNT_POOL2_COUNT_FIELD_WIDTH 32
+#define FPM_EXPIRED_TOKEN_COUNT_POOL2_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_RECOVERED_TOKEN_COUNT_POOL2_COUNT_FIELD;
+#define FPM_RECOVERED_TOKEN_COUNT_POOL2_COUNT_FIELD_MASK  0xffffffff
+#define FPM_RECOVERED_TOKEN_COUNT_POOL2_COUNT_FIELD_WIDTH 32
+#define FPM_RECOVERED_TOKEN_COUNT_POOL2_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED0_FIELD;
+#define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED0_FIELD_MASK  0xf0000000
+#define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED0_FIELD_WIDTH 4
+#define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL1_START_INDEX_FIELD;
+#define FPM_TOKEN_RECOVER_START_END_POOL1_START_INDEX_FIELD_MASK  0x0fff0000
+#define FPM_TOKEN_RECOVER_START_END_POOL1_START_INDEX_FIELD_WIDTH 12
+#define FPM_TOKEN_RECOVER_START_END_POOL1_START_INDEX_FIELD_SHIFT 16
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED1_FIELD;
+#define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED1_FIELD_MASK  0x0000f000
+#define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED1_FIELD_WIDTH 4
+#define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED1_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL1_END_INDEX_FIELD;
+#define FPM_TOKEN_RECOVER_START_END_POOL1_END_INDEX_FIELD_MASK  0x00000fff
+#define FPM_TOKEN_RECOVER_START_END_POOL1_END_INDEX_FIELD_WIDTH 12
+#define FPM_TOKEN_RECOVER_START_END_POOL1_END_INDEX_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED0_FIELD;
+#define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED0_FIELD_MASK  0xf0000000
+#define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED0_FIELD_WIDTH 4
+#define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL2_START_INDEX_FIELD;
+#define FPM_TOKEN_RECOVER_START_END_POOL2_START_INDEX_FIELD_MASK  0x0fff0000
+#define FPM_TOKEN_RECOVER_START_END_POOL2_START_INDEX_FIELD_WIDTH 12
+#define FPM_TOKEN_RECOVER_START_END_POOL2_START_INDEX_FIELD_SHIFT 16
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED1_FIELD;
+#define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED1_FIELD_MASK  0x0000f000
+#define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED1_FIELD_WIDTH 4
+#define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED1_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL2_END_INDEX_FIELD;
+#define FPM_TOKEN_RECOVER_START_END_POOL2_END_INDEX_FIELD_MASK  0x00000fff
+#define FPM_TOKEN_RECOVER_START_END_POOL2_END_INDEX_FIELD_WIDTH 12
+#define FPM_TOKEN_RECOVER_START_END_POOL2_END_INDEX_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL1_ALLOC_DEALLOC_TOKEN_VALID_FIELD;
+#define FPM_POOL1_ALLOC_DEALLOC_TOKEN_VALID_FIELD_MASK  0x80000000
+#define FPM_POOL1_ALLOC_DEALLOC_TOKEN_VALID_FIELD_WIDTH 1
+#define FPM_POOL1_ALLOC_DEALLOC_TOKEN_VALID_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL1_ALLOC_DEALLOC_RESERVED0_FIELD;
+#define FPM_POOL1_ALLOC_DEALLOC_RESERVED0_FIELD_MASK  0x40000000
+#define FPM_POOL1_ALLOC_DEALLOC_RESERVED0_FIELD_WIDTH 1
+#define FPM_POOL1_ALLOC_DEALLOC_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec FPM_POOL1_ALLOC_DEALLOC_DDR_FIELD;
+#define FPM_POOL1_ALLOC_DEALLOC_DDR_FIELD_MASK  0x20000000
+#define FPM_POOL1_ALLOC_DEALLOC_DDR_FIELD_WIDTH 1
+#define FPM_POOL1_ALLOC_DEALLOC_DDR_FIELD_SHIFT 29
+
+extern const ru_field_rec FPM_POOL1_ALLOC_DEALLOC_TOKEN_INDEX_FIELD;
+#define FPM_POOL1_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_MASK  0x1ffff000
+#define FPM_POOL1_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_WIDTH 17
+#define FPM_POOL1_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_POOL1_ALLOC_DEALLOC_TOKEN_SIZE_FIELD;
+#define FPM_POOL1_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_MASK  0x00000fff
+#define FPM_POOL1_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_WIDTH 12
+#define FPM_POOL1_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL2_ALLOC_DEALLOC_TOKEN_VALID_FIELD;
+#define FPM_POOL2_ALLOC_DEALLOC_TOKEN_VALID_FIELD_MASK  0x80000000
+#define FPM_POOL2_ALLOC_DEALLOC_TOKEN_VALID_FIELD_WIDTH 1
+#define FPM_POOL2_ALLOC_DEALLOC_TOKEN_VALID_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL2_ALLOC_DEALLOC_RESERVED0_FIELD;
+#define FPM_POOL2_ALLOC_DEALLOC_RESERVED0_FIELD_MASK  0x40000000
+#define FPM_POOL2_ALLOC_DEALLOC_RESERVED0_FIELD_WIDTH 1
+#define FPM_POOL2_ALLOC_DEALLOC_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec FPM_POOL2_ALLOC_DEALLOC_DDR_FIELD;
+#define FPM_POOL2_ALLOC_DEALLOC_DDR_FIELD_MASK  0x20000000
+#define FPM_POOL2_ALLOC_DEALLOC_DDR_FIELD_WIDTH 1
+#define FPM_POOL2_ALLOC_DEALLOC_DDR_FIELD_SHIFT 29
+
+extern const ru_field_rec FPM_POOL2_ALLOC_DEALLOC_TOKEN_INDEX_FIELD;
+#define FPM_POOL2_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_MASK  0x1ffff000
+#define FPM_POOL2_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_WIDTH 17
+#define FPM_POOL2_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_POOL2_ALLOC_DEALLOC_TOKEN_SIZE_FIELD;
+#define FPM_POOL2_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_MASK  0x00000fff
+#define FPM_POOL2_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_WIDTH 12
+#define FPM_POOL2_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL3_ALLOC_DEALLOC_TOKEN_VALID_FIELD;
+#define FPM_POOL3_ALLOC_DEALLOC_TOKEN_VALID_FIELD_MASK  0x80000000
+#define FPM_POOL3_ALLOC_DEALLOC_TOKEN_VALID_FIELD_WIDTH 1
+#define FPM_POOL3_ALLOC_DEALLOC_TOKEN_VALID_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL3_ALLOC_DEALLOC_RESERVED0_FIELD;
+#define FPM_POOL3_ALLOC_DEALLOC_RESERVED0_FIELD_MASK  0x40000000
+#define FPM_POOL3_ALLOC_DEALLOC_RESERVED0_FIELD_WIDTH 1
+#define FPM_POOL3_ALLOC_DEALLOC_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec FPM_POOL3_ALLOC_DEALLOC_DDR_FIELD;
+#define FPM_POOL3_ALLOC_DEALLOC_DDR_FIELD_MASK  0x20000000
+#define FPM_POOL3_ALLOC_DEALLOC_DDR_FIELD_WIDTH 1
+#define FPM_POOL3_ALLOC_DEALLOC_DDR_FIELD_SHIFT 29
+
+extern const ru_field_rec FPM_POOL3_ALLOC_DEALLOC_TOKEN_INDEX_FIELD;
+#define FPM_POOL3_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_MASK  0x1ffff000
+#define FPM_POOL3_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_WIDTH 17
+#define FPM_POOL3_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_POOL3_ALLOC_DEALLOC_TOKEN_SIZE_FIELD;
+#define FPM_POOL3_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_MASK  0x00000fff
+#define FPM_POOL3_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_WIDTH 12
+#define FPM_POOL3_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL4_ALLOC_DEALLOC_TOKEN_VALID_FIELD;
+#define FPM_POOL4_ALLOC_DEALLOC_TOKEN_VALID_FIELD_MASK  0x80000000
+#define FPM_POOL4_ALLOC_DEALLOC_TOKEN_VALID_FIELD_WIDTH 1
+#define FPM_POOL4_ALLOC_DEALLOC_TOKEN_VALID_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL4_ALLOC_DEALLOC_RESERVED0_FIELD;
+#define FPM_POOL4_ALLOC_DEALLOC_RESERVED0_FIELD_MASK  0x40000000
+#define FPM_POOL4_ALLOC_DEALLOC_RESERVED0_FIELD_WIDTH 1
+#define FPM_POOL4_ALLOC_DEALLOC_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec FPM_POOL4_ALLOC_DEALLOC_DDR_FIELD;
+#define FPM_POOL4_ALLOC_DEALLOC_DDR_FIELD_MASK  0x20000000
+#define FPM_POOL4_ALLOC_DEALLOC_DDR_FIELD_WIDTH 1
+#define FPM_POOL4_ALLOC_DEALLOC_DDR_FIELD_SHIFT 29
+
+extern const ru_field_rec FPM_POOL4_ALLOC_DEALLOC_TOKEN_INDEX_FIELD;
+#define FPM_POOL4_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_MASK  0x1ffff000
+#define FPM_POOL4_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_WIDTH 17
+#define FPM_POOL4_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_POOL4_ALLOC_DEALLOC_TOKEN_SIZE_FIELD;
+#define FPM_POOL4_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_MASK  0x00000fff
+#define FPM_POOL4_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_WIDTH 12
+#define FPM_POOL4_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_SPARE_SPARE_BITS_FIELD;
+#define FPM_SPARE_SPARE_BITS_FIELD_MASK  0xffffffff
+#define FPM_SPARE_SPARE_BITS_FIELD_WIDTH 32
+#define FPM_SPARE_SPARE_BITS_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_POOL_MULTI_TOKEN_VALID_FIELD;
+#define FPM_POOL_MULTI_TOKEN_VALID_FIELD_MASK  0x80000000
+#define FPM_POOL_MULTI_TOKEN_VALID_FIELD_WIDTH 1
+#define FPM_POOL_MULTI_TOKEN_VALID_FIELD_SHIFT 31
+
+extern const ru_field_rec FPM_POOL_MULTI_RESERVED0_FIELD;
+#define FPM_POOL_MULTI_RESERVED0_FIELD_MASK  0x40000000
+#define FPM_POOL_MULTI_RESERVED0_FIELD_WIDTH 1
+#define FPM_POOL_MULTI_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec FPM_POOL_MULTI_DDR_FIELD;
+#define FPM_POOL_MULTI_DDR_FIELD_MASK  0x20000000
+#define FPM_POOL_MULTI_DDR_FIELD_WIDTH 1
+#define FPM_POOL_MULTI_DDR_FIELD_SHIFT 29
+
+extern const ru_field_rec FPM_POOL_MULTI_TOKEN_INDEX_FIELD;
+#define FPM_POOL_MULTI_TOKEN_INDEX_FIELD_MASK  0x1ffff000
+#define FPM_POOL_MULTI_TOKEN_INDEX_FIELD_WIDTH 17
+#define FPM_POOL_MULTI_TOKEN_INDEX_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_POOL_MULTI_UPDATE_TYPE_FIELD;
+#define FPM_POOL_MULTI_UPDATE_TYPE_FIELD_MASK  0x00000800
+#define FPM_POOL_MULTI_UPDATE_TYPE_FIELD_WIDTH 1
+#define FPM_POOL_MULTI_UPDATE_TYPE_FIELD_SHIFT 11
+
+extern const ru_field_rec FPM_POOL_MULTI_RESERVED1_FIELD;
+#define FPM_POOL_MULTI_RESERVED1_FIELD_MASK  0x00000780
+#define FPM_POOL_MULTI_RESERVED1_FIELD_WIDTH 4
+#define FPM_POOL_MULTI_RESERVED1_FIELD_SHIFT 7
+
+extern const ru_field_rec FPM_POOL_MULTI_TOKEN_MULTI_FIELD;
+#define FPM_POOL_MULTI_TOKEN_MULTI_FIELD_MASK  0x0000007f
+#define FPM_POOL_MULTI_TOKEN_MULTI_FIELD_WIDTH 7
+#define FPM_POOL_MULTI_TOKEN_MULTI_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_FORCE_FORCE_FIELD;
+#define FPM_FPM_BB_FORCE_FORCE_FIELD_MASK  0x00000001
+#define FPM_FPM_BB_FORCE_FORCE_FIELD_WIDTH 1
+#define FPM_FPM_BB_FORCE_FORCE_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_FORCE_RESERVED0_FIELD;
+#define FPM_FPM_BB_FORCE_RESERVED0_FIELD_MASK  0xfffffffe
+#define FPM_FPM_BB_FORCE_RESERVED0_FIELD_WIDTH 31
+#define FPM_FPM_BB_FORCE_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec FPM_FPM_BB_FORCED_CTRL_CTRL_FIELD;
+#define FPM_FPM_BB_FORCED_CTRL_CTRL_FIELD_MASK  0x00000fff
+#define FPM_FPM_BB_FORCED_CTRL_CTRL_FIELD_WIDTH 12
+#define FPM_FPM_BB_FORCED_CTRL_CTRL_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_FORCED_CTRL_RESERVED0_FIELD;
+#define FPM_FPM_BB_FORCED_CTRL_RESERVED0_FIELD_MASK  0xfffff000
+#define FPM_FPM_BB_FORCED_CTRL_RESERVED0_FIELD_WIDTH 20
+#define FPM_FPM_BB_FORCED_CTRL_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec FPM_FPM_BB_FORCED_ADDR_TA_ADDR_FIELD;
+#define FPM_FPM_BB_FORCED_ADDR_TA_ADDR_FIELD_MASK  0x0000ffff
+#define FPM_FPM_BB_FORCED_ADDR_TA_ADDR_FIELD_WIDTH 16
+#define FPM_FPM_BB_FORCED_ADDR_TA_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_FORCED_ADDR_DEST_ADDR_FIELD;
+#define FPM_FPM_BB_FORCED_ADDR_DEST_ADDR_FIELD_MASK  0x003f0000
+#define FPM_FPM_BB_FORCED_ADDR_DEST_ADDR_FIELD_WIDTH 6
+#define FPM_FPM_BB_FORCED_ADDR_DEST_ADDR_FIELD_SHIFT 16
+
+extern const ru_field_rec FPM_FPM_BB_FORCED_ADDR_RESERVED0_FIELD;
+#define FPM_FPM_BB_FORCED_ADDR_RESERVED0_FIELD_MASK  0xffc00000
+#define FPM_FPM_BB_FORCED_ADDR_RESERVED0_FIELD_WIDTH 10
+#define FPM_FPM_BB_FORCED_ADDR_RESERVED0_FIELD_SHIFT 22
+
+extern const ru_field_rec FPM_FPM_BB_FORCED_DATA_DATA_FIELD;
+#define FPM_FPM_BB_FORCED_DATA_DATA_FIELD_MASK  0xffffffff
+#define FPM_FPM_BB_FORCED_DATA_DATA_FIELD_WIDTH 32
+#define FPM_FPM_BB_FORCED_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_DECODE_CFG_DEST_ID_FIELD;
+#define FPM_FPM_BB_DECODE_CFG_DEST_ID_FIELD_MASK  0x0000003f
+#define FPM_FPM_BB_DECODE_CFG_DEST_ID_FIELD_WIDTH 6
+#define FPM_FPM_BB_DECODE_CFG_DEST_ID_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_DECODE_CFG_OVERRIDE_EN_FIELD;
+#define FPM_FPM_BB_DECODE_CFG_OVERRIDE_EN_FIELD_MASK  0x00000040
+#define FPM_FPM_BB_DECODE_CFG_OVERRIDE_EN_FIELD_WIDTH 1
+#define FPM_FPM_BB_DECODE_CFG_OVERRIDE_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec FPM_FPM_BB_DECODE_CFG_ROUTE_ADDR_FIELD;
+#define FPM_FPM_BB_DECODE_CFG_ROUTE_ADDR_FIELD_MASK  0x0001ff80
+#define FPM_FPM_BB_DECODE_CFG_ROUTE_ADDR_FIELD_WIDTH 10
+#define FPM_FPM_BB_DECODE_CFG_ROUTE_ADDR_FIELD_SHIFT 7
+
+extern const ru_field_rec FPM_FPM_BB_DECODE_CFG_RESERVED0_FIELD;
+#define FPM_FPM_BB_DECODE_CFG_RESERVED0_FIELD_MASK  0xfffe0000
+#define FPM_FPM_BB_DECODE_CFG_RESERVED0_FIELD_WIDTH 15
+#define FPM_FPM_BB_DECODE_CFG_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec FPM_FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_FIELD;
+#define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_FIELD_MASK  0x0000000f
+#define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_FIELD_WIDTH 4
+#define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_FIELD;
+#define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_FIELD_MASK  0x000000f0
+#define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_FIELD_WIDTH 4
+#define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_FIELD_SHIFT 4
+
+extern const ru_field_rec FPM_FPM_BB_DBG_CFG_RXFIFO_SW_RST_FIELD;
+#define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_RST_FIELD_MASK  0x00000100
+#define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_RST_FIELD_WIDTH 1
+#define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_RST_FIELD_SHIFT 8
+
+extern const ru_field_rec FPM_FPM_BB_DBG_CFG_TXFIFO_SW_RST_FIELD;
+#define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_RST_FIELD_MASK  0x00000200
+#define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_RST_FIELD_WIDTH 1
+#define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_RST_FIELD_SHIFT 9
+
+extern const ru_field_rec FPM_FPM_BB_DBG_CFG_RESERVED0_FIELD;
+#define FPM_FPM_BB_DBG_CFG_RESERVED0_FIELD_MASK  0xfffffc00
+#define FPM_FPM_BB_DBG_CFG_RESERVED0_FIELD_WIDTH 22
+#define FPM_FPM_BB_DBG_CFG_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_EMPTY_FIELD;
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_EMPTY_FIELD_MASK  0x00000001
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_EMPTY_FIELD_WIDTH 1
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_EMPTY_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_FULL_FIELD;
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_FULL_FIELD_MASK  0x00000002
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_FULL_FIELD_WIDTH 1
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_FULL_FIELD_SHIFT 1
+
+extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED0_FIELD;
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED0_FIELD_MASK  0x000000fc
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED0_FIELD_WIDTH 6
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_FIELD;
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_FIELD_MASK  0x00001f00
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_FIELD_WIDTH 5
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_FIELD_SHIFT 8
+
+extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED1_FIELD;
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED1_FIELD_MASK  0x0000e000
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED1_FIELD_WIDTH 3
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_FIELD;
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_FIELD_MASK  0x001f0000
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_FIELD_WIDTH 5
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_FIELD_SHIFT 16
+
+extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED2_FIELD;
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED2_FIELD_MASK  0x00e00000
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED2_FIELD_WIDTH 3
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED2_FIELD_SHIFT 21
+
+extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_FIELD;
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_FIELD_MASK  0x1f000000
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_FIELD_WIDTH 5
+#define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_FIELD_SHIFT 24
+
+extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED3_FIELD;
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED3_FIELD_MASK  0xe0000000
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED3_FIELD_WIDTH 3
+#define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED3_FIELD_SHIFT 29
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_EMPTY_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_EMPTY_FIELD_MASK  0x00000001
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_EMPTY_FIELD_WIDTH 1
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_EMPTY_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_FULL_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_FULL_FIELD_MASK  0x00000002
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_FULL_FIELD_WIDTH 1
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_FULL_FIELD_SHIFT 1
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED0_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED0_FIELD_MASK  0x000000fc
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED0_FIELD_WIDTH 6
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_FIELD_MASK  0x00001f00
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_FIELD_WIDTH 5
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_FIELD_SHIFT 8
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED1_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED1_FIELD_MASK  0x0000e000
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED1_FIELD_WIDTH 3
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_FIELD_MASK  0x001f0000
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_FIELD_WIDTH 5
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_FIELD_SHIFT 16
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED2_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED2_FIELD_MASK  0x00e00000
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED2_FIELD_WIDTH 3
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED2_FIELD_SHIFT 21
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_FIELD_MASK  0x1f000000
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_FIELD_WIDTH 5
+#define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_FIELD_SHIFT 24
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED3_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED3_FIELD_MASK  0xe0000000
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED3_FIELD_WIDTH 3
+#define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED3_FIELD_SHIFT 29
+
+extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_DATA1_DATA_FIELD;
+#define FPM_FPM_BB_DBG_RXFIFO_DATA1_DATA_FIELD_MASK  0xffffffff
+#define FPM_FPM_BB_DBG_RXFIFO_DATA1_DATA_FIELD_WIDTH 32
+#define FPM_FPM_BB_DBG_RXFIFO_DATA1_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_DATA2_DATA_FIELD;
+#define FPM_FPM_BB_DBG_RXFIFO_DATA2_DATA_FIELD_MASK  0xffffffff
+#define FPM_FPM_BB_DBG_RXFIFO_DATA2_DATA_FIELD_WIDTH 32
+#define FPM_FPM_BB_DBG_RXFIFO_DATA2_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_DATA1_DATA_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_DATA1_DATA_FIELD_MASK  0xffffffff
+#define FPM_FPM_BB_DBG_TXFIFO_DATA1_DATA_FIELD_WIDTH 32
+#define FPM_FPM_BB_DBG_TXFIFO_DATA1_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_DATA2_DATA_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_DATA2_DATA_FIELD_MASK  0xffffffff
+#define FPM_FPM_BB_DBG_TXFIFO_DATA2_DATA_FIELD_WIDTH 32
+#define FPM_FPM_BB_DBG_TXFIFO_DATA2_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_DATA3_DATA_FIELD;
+#define FPM_FPM_BB_DBG_TXFIFO_DATA3_DATA_FIELD_MASK  0xffffffff
+#define FPM_FPM_BB_DBG_TXFIFO_DATA3_DATA_FIELD_WIDTH 32
+#define FPM_FPM_BB_DBG_TXFIFO_DATA3_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_MEM_HIGH_DATA_MEM_FIELD;
+#define RNR_MEM_HIGH_DATA_MEM_FIELD_MASK  0xffffffff
+#define RNR_MEM_HIGH_DATA_MEM_FIELD_WIDTH 32
+#define RNR_MEM_HIGH_DATA_MEM_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_MEM_LOW_DATA_MEM_FIELD;
+#define RNR_MEM_LOW_DATA_MEM_FIELD_MASK  0xffffffff
+#define RNR_MEM_LOW_DATA_MEM_FIELD_WIDTH 32
+#define RNR_MEM_LOW_DATA_MEM_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_INST_MEM_ENTRY_INSTRUCTION_FIELD;
+#define RNR_INST_MEM_ENTRY_INSTRUCTION_FIELD_MASK  0xffffffff
+#define RNR_INST_MEM_ENTRY_INSTRUCTION_FIELD_WIDTH 32
+#define RNR_INST_MEM_ENTRY_INSTRUCTION_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_CNTXT_MEM_ENTRY_CONTEXT_ENTRY_FIELD;
+#define RNR_CNTXT_MEM_ENTRY_CONTEXT_ENTRY_FIELD_MASK  0xffffffff
+#define RNR_CNTXT_MEM_ENTRY_CONTEXT_ENTRY_FIELD_WIDTH 32
+#define RNR_CNTXT_MEM_ENTRY_CONTEXT_ENTRY_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_PRED_MEM_ENTRY_PRED_MEM_FIELD;
+#define RNR_PRED_MEM_ENTRY_PRED_MEM_FIELD_MASK  0x0000ffff
+#define RNR_PRED_MEM_ENTRY_PRED_MEM_FIELD_WIDTH 16
+#define RNR_PRED_MEM_ENTRY_PRED_MEM_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_GLOBAL_CTRL_EN_FIELD;
+#define RNR_REGS_CFG_GLOBAL_CTRL_EN_FIELD_MASK  0x00000001
+#define RNR_REGS_CFG_GLOBAL_CTRL_EN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GLOBAL_CTRL_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_GLOBAL_CTRL_DMA_ILLEGAL_STATUS_FIELD;
+#define RNR_REGS_CFG_GLOBAL_CTRL_DMA_ILLEGAL_STATUS_FIELD_MASK  0x00000002
+#define RNR_REGS_CFG_GLOBAL_CTRL_DMA_ILLEGAL_STATUS_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GLOBAL_CTRL_DMA_ILLEGAL_STATUS_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_REGS_CFG_GLOBAL_CTRL_PREDICTION_OVERRUN_STATUS_FIELD;
+#define RNR_REGS_CFG_GLOBAL_CTRL_PREDICTION_OVERRUN_STATUS_FIELD_MASK  0x00000004
+#define RNR_REGS_CFG_GLOBAL_CTRL_PREDICTION_OVERRUN_STATUS_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GLOBAL_CTRL_PREDICTION_OVERRUN_STATUS_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_REGS_CFG_GLOBAL_CTRL_RESERVED0_FIELD;
+#define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED0_FIELD_MASK  0x000000f8
+#define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED0_FIELD_WIDTH 5
+#define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_REGS_CFG_GLOBAL_CTRL_MICRO_SEC_VAL_FIELD;
+#define RNR_REGS_CFG_GLOBAL_CTRL_MICRO_SEC_VAL_FIELD_MASK  0x00ffff00
+#define RNR_REGS_CFG_GLOBAL_CTRL_MICRO_SEC_VAL_FIELD_WIDTH 16
+#define RNR_REGS_CFG_GLOBAL_CTRL_MICRO_SEC_VAL_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_REGS_CFG_GLOBAL_CTRL_RESERVED1_FIELD;
+#define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED1_FIELD_MASK  0xff000000
+#define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED1_FIELD_WIDTH 8
+#define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED1_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_REGS_CFG_CPU_WAKEUP_THREAD_NUM_FIELD;
+#define RNR_REGS_CFG_CPU_WAKEUP_THREAD_NUM_FIELD_MASK  0x0000000f
+#define RNR_REGS_CFG_CPU_WAKEUP_THREAD_NUM_FIELD_WIDTH 4
+#define RNR_REGS_CFG_CPU_WAKEUP_THREAD_NUM_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_CPU_WAKEUP_RESERVED0_FIELD;
+#define RNR_REGS_CFG_CPU_WAKEUP_RESERVED0_FIELD_MASK  0xfffffff0
+#define RNR_REGS_CFG_CPU_WAKEUP_RESERVED0_FIELD_WIDTH 28
+#define RNR_REGS_CFG_CPU_WAKEUP_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT0_STS_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_INT0_STS_FIELD_MASK  0x000000ff
+#define RNR_REGS_CFG_INT_CTRL_INT0_STS_FIELD_WIDTH 8
+#define RNR_REGS_CFG_INT_CTRL_INT0_STS_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT1_STS_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_INT1_STS_FIELD_MASK  0x0000ff00
+#define RNR_REGS_CFG_INT_CTRL_INT1_STS_FIELD_WIDTH 8
+#define RNR_REGS_CFG_INT_CTRL_INT1_STS_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT2_STS_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_INT2_STS_FIELD_MASK  0x00010000
+#define RNR_REGS_CFG_INT_CTRL_INT2_STS_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_CTRL_INT2_STS_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT3_STS_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_INT3_STS_FIELD_MASK  0x00020000
+#define RNR_REGS_CFG_INT_CTRL_INT3_STS_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_CTRL_INT3_STS_FIELD_SHIFT 17
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT4_STS_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_INT4_STS_FIELD_MASK  0x00040000
+#define RNR_REGS_CFG_INT_CTRL_INT4_STS_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_CTRL_INT4_STS_FIELD_SHIFT 18
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT5_STS_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_INT5_STS_FIELD_MASK  0x00080000
+#define RNR_REGS_CFG_INT_CTRL_INT5_STS_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_CTRL_INT5_STS_FIELD_SHIFT 19
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT6_STS_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_INT6_STS_FIELD_MASK  0x00100000
+#define RNR_REGS_CFG_INT_CTRL_INT6_STS_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_CTRL_INT6_STS_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT7_STS_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_INT7_STS_FIELD_MASK  0x00200000
+#define RNR_REGS_CFG_INT_CTRL_INT7_STS_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_CTRL_INT7_STS_FIELD_SHIFT 21
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT8_STS_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_INT8_STS_FIELD_MASK  0x00400000
+#define RNR_REGS_CFG_INT_CTRL_INT8_STS_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_CTRL_INT8_STS_FIELD_SHIFT 22
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT9_STS_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_INT9_STS_FIELD_MASK  0x00800000
+#define RNR_REGS_CFG_INT_CTRL_INT9_STS_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_CTRL_INT9_STS_FIELD_SHIFT 23
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_RESERVED0_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_RESERVED0_FIELD_MASK  0x7f000000
+#define RNR_REGS_CFG_INT_CTRL_RESERVED0_FIELD_WIDTH 7
+#define RNR_REGS_CFG_INT_CTRL_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_FIT_FAIL_STS_FIELD;
+#define RNR_REGS_CFG_INT_CTRL_FIT_FAIL_STS_FIELD_MASK  0x80000000
+#define RNR_REGS_CFG_INT_CTRL_FIT_FAIL_STS_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_CTRL_FIT_FAIL_STS_FIELD_SHIFT 31
+
+extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT0_MASK_FIELD;
+#define RNR_REGS_CFG_INT_MASK_INT0_MASK_FIELD_MASK  0x000000ff
+#define RNR_REGS_CFG_INT_MASK_INT0_MASK_FIELD_WIDTH 8
+#define RNR_REGS_CFG_INT_MASK_INT0_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT1_MASK_FIELD;
+#define RNR_REGS_CFG_INT_MASK_INT1_MASK_FIELD_MASK  0x0000ff00
+#define RNR_REGS_CFG_INT_MASK_INT1_MASK_FIELD_WIDTH 8
+#define RNR_REGS_CFG_INT_MASK_INT1_MASK_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT2_MASK_FIELD;
+#define RNR_REGS_CFG_INT_MASK_INT2_MASK_FIELD_MASK  0x00010000
+#define RNR_REGS_CFG_INT_MASK_INT2_MASK_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_MASK_INT2_MASK_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT3_MASK_FIELD;
+#define RNR_REGS_CFG_INT_MASK_INT3_MASK_FIELD_MASK  0x00020000
+#define RNR_REGS_CFG_INT_MASK_INT3_MASK_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_MASK_INT3_MASK_FIELD_SHIFT 17
+
+extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT4_MASK_FIELD;
+#define RNR_REGS_CFG_INT_MASK_INT4_MASK_FIELD_MASK  0x00040000
+#define RNR_REGS_CFG_INT_MASK_INT4_MASK_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_MASK_INT4_MASK_FIELD_SHIFT 18
+
+extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT5_MASK_FIELD;
+#define RNR_REGS_CFG_INT_MASK_INT5_MASK_FIELD_MASK  0x00080000
+#define RNR_REGS_CFG_INT_MASK_INT5_MASK_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_MASK_INT5_MASK_FIELD_SHIFT 19
+
+extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT6_MASK_FIELD;
+#define RNR_REGS_CFG_INT_MASK_INT6_MASK_FIELD_MASK  0x00100000
+#define RNR_REGS_CFG_INT_MASK_INT6_MASK_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_MASK_INT6_MASK_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT7_MASK_FIELD;
+#define RNR_REGS_CFG_INT_MASK_INT7_MASK_FIELD_MASK  0x00200000
+#define RNR_REGS_CFG_INT_MASK_INT7_MASK_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_MASK_INT7_MASK_FIELD_SHIFT 21
+
+extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT8_MASK_FIELD;
+#define RNR_REGS_CFG_INT_MASK_INT8_MASK_FIELD_MASK  0x00400000
+#define RNR_REGS_CFG_INT_MASK_INT8_MASK_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_MASK_INT8_MASK_FIELD_SHIFT 22
+
+extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT9_MASK_FIELD;
+#define RNR_REGS_CFG_INT_MASK_INT9_MASK_FIELD_MASK  0x00800000
+#define RNR_REGS_CFG_INT_MASK_INT9_MASK_FIELD_WIDTH 1
+#define RNR_REGS_CFG_INT_MASK_INT9_MASK_FIELD_SHIFT 23
+
+extern const ru_field_rec RNR_REGS_CFG_INT_MASK_RESERVED0_FIELD;
+#define RNR_REGS_CFG_INT_MASK_RESERVED0_FIELD_MASK  0xff000000
+#define RNR_REGS_CFG_INT_MASK_RESERVED0_FIELD_WIDTH 8
+#define RNR_REGS_CFG_INT_MASK_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_DISABLE_DMA_OLD_FLOW_CONTROL_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_DISABLE_DMA_OLD_FLOW_CONTROL_FIELD_MASK  0x00000001
+#define RNR_REGS_CFG_GEN_CFG_DISABLE_DMA_OLD_FLOW_CONTROL_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_DISABLE_DMA_OLD_FLOW_CONTROL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_TEST_FIT_FAIL_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_TEST_FIT_FAIL_FIELD_MASK  0x00000002
+#define RNR_REGS_CFG_GEN_CFG_TEST_FIT_FAIL_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_TEST_FIT_FAIL_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_ZERO_DATA_MEM_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_ZERO_DATA_MEM_FIELD_MASK  0x00000004
+#define RNR_REGS_CFG_GEN_CFG_ZERO_DATA_MEM_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_ZERO_DATA_MEM_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_ZERO_CONTEXT_MEM_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_ZERO_CONTEXT_MEM_FIELD_MASK  0x00000008
+#define RNR_REGS_CFG_GEN_CFG_ZERO_CONTEXT_MEM_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_ZERO_CONTEXT_MEM_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_ZERO_DATA_MEM_DONE_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_ZERO_DATA_MEM_DONE_FIELD_MASK  0x00000010
+#define RNR_REGS_CFG_GEN_CFG_ZERO_DATA_MEM_DONE_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_ZERO_DATA_MEM_DONE_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_ZERO_CONTEXT_MEM_DONE_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_ZERO_CONTEXT_MEM_DONE_FIELD_MASK  0x00000020
+#define RNR_REGS_CFG_GEN_CFG_ZERO_CONTEXT_MEM_DONE_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_ZERO_CONTEXT_MEM_DONE_FIELD_SHIFT 5
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_ENABLE_BREAKPOINT_ON_FIT_FAIL_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_ENABLE_BREAKPOINT_ON_FIT_FAIL_FIELD_MASK  0x00000040
+#define RNR_REGS_CFG_GEN_CFG_ENABLE_BREAKPOINT_ON_FIT_FAIL_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_ENABLE_BREAKPOINT_ON_FIT_FAIL_FIELD_SHIFT 6
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_RESERVED0_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_RESERVED0_FIELD_MASK  0x00000080
+#define RNR_REGS_CFG_GEN_CFG_RESERVED0_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_GDMA_DESC_OFFSET_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_GDMA_DESC_OFFSET_FIELD_MASK  0x0000ff00
+#define RNR_REGS_CFG_GEN_CFG_GDMA_DESC_OFFSET_FIELD_WIDTH 8
+#define RNR_REGS_CFG_GEN_CFG_GDMA_DESC_OFFSET_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_BBTX_TCAM_DEST_SEL_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_BBTX_TCAM_DEST_SEL_FIELD_MASK  0x00010000
+#define RNR_REGS_CFG_GEN_CFG_BBTX_TCAM_DEST_SEL_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_BBTX_TCAM_DEST_SEL_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_BBTX_HASH_DEST_SEL_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_BBTX_HASH_DEST_SEL_FIELD_MASK  0x00020000
+#define RNR_REGS_CFG_GEN_CFG_BBTX_HASH_DEST_SEL_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_BBTX_HASH_DEST_SEL_FIELD_SHIFT 17
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_BBTX_NATC_DEST_SEL_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_BBTX_NATC_DEST_SEL_FIELD_MASK  0x00040000
+#define RNR_REGS_CFG_GEN_CFG_BBTX_NATC_DEST_SEL_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_BBTX_NATC_DEST_SEL_FIELD_SHIFT 18
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_BBTX_CNPL_DEST_SEL_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_BBTX_CNPL_DEST_SEL_FIELD_MASK  0x00080000
+#define RNR_REGS_CFG_GEN_CFG_BBTX_CNPL_DEST_SEL_FIELD_WIDTH 1
+#define RNR_REGS_CFG_GEN_CFG_BBTX_CNPL_DEST_SEL_FIELD_SHIFT 19
+
+extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_RESERVED1_FIELD;
+#define RNR_REGS_CFG_GEN_CFG_RESERVED1_FIELD_MASK  0xfff00000
+#define RNR_REGS_CFG_GEN_CFG_RESERVED1_FIELD_WIDTH 12
+#define RNR_REGS_CFG_GEN_CFG_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_REGS_CFG_CAM_CFG_STOP_VALUE_FIELD;
+#define RNR_REGS_CFG_CAM_CFG_STOP_VALUE_FIELD_MASK  0x0000ffff
+#define RNR_REGS_CFG_CAM_CFG_STOP_VALUE_FIELD_WIDTH 16
+#define RNR_REGS_CFG_CAM_CFG_STOP_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_CAM_CFG_RESERVED0_FIELD;
+#define RNR_REGS_CFG_CAM_CFG_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_REGS_CFG_CAM_CFG_RESERVED0_FIELD_WIDTH 16
+#define RNR_REGS_CFG_CAM_CFG_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_DDR_CFG_DMA_BASE_FIELD;
+#define RNR_REGS_CFG_DDR_CFG_DMA_BASE_FIELD_MASK  0x000fffff
+#define RNR_REGS_CFG_DDR_CFG_DMA_BASE_FIELD_WIDTH 20
+#define RNR_REGS_CFG_DDR_CFG_DMA_BASE_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_FIELD;
+#define RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_FIELD_MASK  0x00700000
+#define RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_FIELD_WIDTH 3
+#define RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_MODE_FIELD;
+#define RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_MODE_FIELD_MASK  0x00800000
+#define RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_MODE_FIELD_WIDTH 1
+#define RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_MODE_FIELD_SHIFT 23
+
+extern const ru_field_rec RNR_REGS_CFG_DDR_CFG_DMA_STATIC_OFFSET_FIELD;
+#define RNR_REGS_CFG_DDR_CFG_DMA_STATIC_OFFSET_FIELD_MASK  0xff000000
+#define RNR_REGS_CFG_DDR_CFG_DMA_STATIC_OFFSET_FIELD_WIDTH 8
+#define RNR_REGS_CFG_DDR_CFG_DMA_STATIC_OFFSET_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_REGS_CFG_PSRAM_CFG_DMA_BASE_FIELD;
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_BASE_FIELD_MASK  0x000fffff
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_BASE_FIELD_WIDTH 20
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_BASE_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_FIELD;
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_FIELD_MASK  0x00700000
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_FIELD_WIDTH 3
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_MODE_FIELD;
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_MODE_FIELD_MASK  0x00800000
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_MODE_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_MODE_FIELD_SHIFT 23
+
+extern const ru_field_rec RNR_REGS_CFG_PSRAM_CFG_DMA_STATIC_OFFSET_FIELD;
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_STATIC_OFFSET_FIELD_MASK  0xff000000
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_STATIC_OFFSET_FIELD_WIDTH 8
+#define RNR_REGS_CFG_PSRAM_CFG_DMA_STATIC_OFFSET_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK0_FIELD;
+#define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK0_FIELD_MASK  0x0000ffff
+#define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK0_FIELD_WIDTH 16
+#define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK0_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK1_FIELD;
+#define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK1_FIELD_MASK  0xffff0000
+#define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK1_FIELD_WIDTH 16
+#define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK1_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_SCH_CFG_SCHEDULER_MODE_FIELD;
+#define RNR_REGS_CFG_SCH_CFG_SCHEDULER_MODE_FIELD_MASK  0x00000007
+#define RNR_REGS_CFG_SCH_CFG_SCHEDULER_MODE_FIELD_WIDTH 3
+#define RNR_REGS_CFG_SCH_CFG_SCHEDULER_MODE_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_SCH_CFG_RESERVED0_FIELD;
+#define RNR_REGS_CFG_SCH_CFG_RESERVED0_FIELD_MASK  0xfffffff8
+#define RNR_REGS_CFG_SCH_CFG_RESERVED0_FIELD_WIDTH 29
+#define RNR_REGS_CFG_SCH_CFG_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_0_EN_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_0_EN_FIELD_MASK  0x00000001
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_0_EN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_0_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_0_USE_THREAD_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_0_USE_THREAD_FIELD_MASK  0x00000002
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_0_USE_THREAD_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_0_USE_THREAD_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_1_EN_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_1_EN_FIELD_MASK  0x00000004
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_1_EN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_1_EN_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_1_USE_THREAD_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_1_USE_THREAD_FIELD_MASK  0x00000008
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_1_USE_THREAD_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_1_USE_THREAD_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_2_EN_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_2_EN_FIELD_MASK  0x00000010
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_2_EN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_2_EN_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_2_USE_THREAD_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_2_USE_THREAD_FIELD_MASK  0x00000020
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_2_USE_THREAD_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_2_USE_THREAD_FIELD_SHIFT 5
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_3_EN_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_3_EN_FIELD_MASK  0x00000040
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_3_EN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_3_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_3_USE_THREAD_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_3_USE_THREAD_FIELD_MASK  0x00000080
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_3_USE_THREAD_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_3_USE_THREAD_FIELD_SHIFT 7
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_4_EN_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_4_EN_FIELD_MASK  0x00000100
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_4_EN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_4_EN_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_4_USE_THREAD_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_4_USE_THREAD_FIELD_MASK  0x00000200
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_4_USE_THREAD_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_4_USE_THREAD_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_5_EN_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_5_EN_FIELD_MASK  0x00000400
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_5_EN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_5_EN_FIELD_SHIFT 10
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_5_USE_THREAD_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_5_USE_THREAD_FIELD_MASK  0x00000800
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_5_USE_THREAD_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_5_USE_THREAD_FIELD_SHIFT 11
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_6_EN_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_6_EN_FIELD_MASK  0x00001000
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_6_EN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_6_EN_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_6_USE_THREAD_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_6_USE_THREAD_FIELD_MASK  0x00002000
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_6_USE_THREAD_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_6_USE_THREAD_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_7_EN_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_7_EN_FIELD_MASK  0x00004000
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_7_EN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_7_EN_FIELD_SHIFT 14
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_7_USE_THREAD_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_7_USE_THREAD_FIELD_MASK  0x00008000
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_7_USE_THREAD_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_BKPT_7_USE_THREAD_FIELD_SHIFT 15
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_STEP_MODE_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_STEP_MODE_FIELD_MASK  0x00010000
+#define RNR_REGS_CFG_BKPT_CFG_STEP_MODE_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_STEP_MODE_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_RESERVED0_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_RESERVED0_FIELD_MASK  0x000e0000
+#define RNR_REGS_CFG_BKPT_CFG_RESERVED0_FIELD_WIDTH 3
+#define RNR_REGS_CFG_BKPT_CFG_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_NEW_FLAGS_VAL_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_NEW_FLAGS_VAL_FIELD_MASK  0x00f00000
+#define RNR_REGS_CFG_BKPT_CFG_NEW_FLAGS_VAL_FIELD_WIDTH 4
+#define RNR_REGS_CFG_BKPT_CFG_NEW_FLAGS_VAL_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_ENABLE_BREAKPOINT_ON_FIT_FAIL_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_ENABLE_BREAKPOINT_ON_FIT_FAIL_FIELD_MASK  0x01000000
+#define RNR_REGS_CFG_BKPT_CFG_ENABLE_BREAKPOINT_ON_FIT_FAIL_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_CFG_ENABLE_BREAKPOINT_ON_FIT_FAIL_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_RESERVED1_FIELD;
+#define RNR_REGS_CFG_BKPT_CFG_RESERVED1_FIELD_MASK  0xfe000000
+#define RNR_REGS_CFG_BKPT_CFG_RESERVED1_FIELD_WIDTH 7
+#define RNR_REGS_CFG_BKPT_CFG_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_IMM_ENABLE_FIELD;
+#define RNR_REGS_CFG_BKPT_IMM_ENABLE_FIELD_MASK  0x00000001
+#define RNR_REGS_CFG_BKPT_IMM_ENABLE_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_IMM_ENABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_IMM_RESERVED0_FIELD;
+#define RNR_REGS_CFG_BKPT_IMM_RESERVED0_FIELD_MASK  0xfffffffe
+#define RNR_REGS_CFG_BKPT_IMM_RESERVED0_FIELD_WIDTH 31
+#define RNR_REGS_CFG_BKPT_IMM_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_STS_BKPT_ADDR_FIELD;
+#define RNR_REGS_CFG_BKPT_STS_BKPT_ADDR_FIELD_MASK  0x00001fff
+#define RNR_REGS_CFG_BKPT_STS_BKPT_ADDR_FIELD_WIDTH 13
+#define RNR_REGS_CFG_BKPT_STS_BKPT_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_STS_RESERVED0_FIELD;
+#define RNR_REGS_CFG_BKPT_STS_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_REGS_CFG_BKPT_STS_RESERVED0_FIELD_WIDTH 3
+#define RNR_REGS_CFG_BKPT_STS_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_STS_ACTIVE_FIELD;
+#define RNR_REGS_CFG_BKPT_STS_ACTIVE_FIELD_MASK  0x00010000
+#define RNR_REGS_CFG_BKPT_STS_ACTIVE_FIELD_WIDTH 1
+#define RNR_REGS_CFG_BKPT_STS_ACTIVE_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_BKPT_STS_RESERVED1_FIELD;
+#define RNR_REGS_CFG_BKPT_STS_RESERVED1_FIELD_MASK  0xfffe0000
+#define RNR_REGS_CFG_BKPT_STS_RESERVED1_FIELD_WIDTH 15
+#define RNR_REGS_CFG_BKPT_STS_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec RNR_REGS_CFG_PC_STS_CURRENT_PC_ADDR_FIELD;
+#define RNR_REGS_CFG_PC_STS_CURRENT_PC_ADDR_FIELD_MASK  0x00001fff
+#define RNR_REGS_CFG_PC_STS_CURRENT_PC_ADDR_FIELD_WIDTH 13
+#define RNR_REGS_CFG_PC_STS_CURRENT_PC_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_PC_STS_RESERVED0_FIELD;
+#define RNR_REGS_CFG_PC_STS_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_REGS_CFG_PC_STS_RESERVED0_FIELD_WIDTH 3
+#define RNR_REGS_CFG_PC_STS_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_REGS_CFG_PC_STS_PC_RET_FIELD;
+#define RNR_REGS_CFG_PC_STS_PC_RET_FIELD_MASK  0x1fff0000
+#define RNR_REGS_CFG_PC_STS_PC_RET_FIELD_WIDTH 13
+#define RNR_REGS_CFG_PC_STS_PC_RET_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_PC_STS_RESERVED1_FIELD;
+#define RNR_REGS_CFG_PC_STS_RESERVED1_FIELD_MASK  0xe0000000
+#define RNR_REGS_CFG_PC_STS_RESERVED1_FIELD_WIDTH 3
+#define RNR_REGS_CFG_PC_STS_RESERVED1_FIELD_SHIFT 29
+
+extern const ru_field_rec RNR_REGS_CFG_EXT_ACC_CFG_ADDR_BASE_FIELD;
+#define RNR_REGS_CFG_EXT_ACC_CFG_ADDR_BASE_FIELD_MASK  0x00001fff
+#define RNR_REGS_CFG_EXT_ACC_CFG_ADDR_BASE_FIELD_WIDTH 13
+#define RNR_REGS_CFG_EXT_ACC_CFG_ADDR_BASE_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_EXT_ACC_CFG_RESERVED0_FIELD;
+#define RNR_REGS_CFG_EXT_ACC_CFG_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_REGS_CFG_EXT_ACC_CFG_RESERVED0_FIELD_WIDTH 3
+#define RNR_REGS_CFG_EXT_ACC_CFG_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_REGS_CFG_EXT_ACC_CFG_ADDR_STEP_0_FIELD;
+#define RNR_REGS_CFG_EXT_ACC_CFG_ADDR_STEP_0_FIELD_MASK  0x000f0000
+#define RNR_REGS_CFG_EXT_ACC_CFG_ADDR_STEP_0_FIELD_WIDTH 4
+#define RNR_REGS_CFG_EXT_ACC_CFG_ADDR_STEP_0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_EXT_ACC_CFG_ADDR_STEP_1_FIELD;
+#define RNR_REGS_CFG_EXT_ACC_CFG_ADDR_STEP_1_FIELD_MASK  0x00f00000
+#define RNR_REGS_CFG_EXT_ACC_CFG_ADDR_STEP_1_FIELD_WIDTH 4
+#define RNR_REGS_CFG_EXT_ACC_CFG_ADDR_STEP_1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_REGS_CFG_EXT_ACC_CFG_START_THREAD_FIELD;
+#define RNR_REGS_CFG_EXT_ACC_CFG_START_THREAD_FIELD_MASK  0x0f000000
+#define RNR_REGS_CFG_EXT_ACC_CFG_START_THREAD_FIELD_WIDTH 4
+#define RNR_REGS_CFG_EXT_ACC_CFG_START_THREAD_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_REGS_CFG_EXT_ACC_CFG_RESERVED1_FIELD;
+#define RNR_REGS_CFG_EXT_ACC_CFG_RESERVED1_FIELD_MASK  0xf0000000
+#define RNR_REGS_CFG_EXT_ACC_CFG_RESERVED1_FIELD_WIDTH 4
+#define RNR_REGS_CFG_EXT_ACC_CFG_RESERVED1_FIELD_SHIFT 28
+
+extern const ru_field_rec RNR_REGS_CFG_FIT_FAIL_CFG_START_ADDR_FIELD;
+#define RNR_REGS_CFG_FIT_FAIL_CFG_START_ADDR_FIELD_MASK  0x00001fff
+#define RNR_REGS_CFG_FIT_FAIL_CFG_START_ADDR_FIELD_WIDTH 13
+#define RNR_REGS_CFG_FIT_FAIL_CFG_START_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_FIT_FAIL_CFG_STOP_ADDR_FIELD;
+#define RNR_REGS_CFG_FIT_FAIL_CFG_STOP_ADDR_FIELD_MASK  0x03ffe000
+#define RNR_REGS_CFG_FIT_FAIL_CFG_STOP_ADDR_FIELD_WIDTH 13
+#define RNR_REGS_CFG_FIT_FAIL_CFG_STOP_ADDR_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_REGS_CFG_FIT_FAIL_CFG_RESERVED0_FIELD;
+#define RNR_REGS_CFG_FIT_FAIL_CFG_RESERVED0_FIELD_MASK  0xfc000000
+#define RNR_REGS_CFG_FIT_FAIL_CFG_RESERVED0_FIELD_WIDTH 6
+#define RNR_REGS_CFG_FIT_FAIL_CFG_RESERVED0_FIELD_SHIFT 26
+
+extern const ru_field_rec RNR_REGS_CFG_STALL_CNT1_STALL_ON_JMP_FULL_CNT_FIELD;
+#define RNR_REGS_CFG_STALL_CNT1_STALL_ON_JMP_FULL_CNT_FIELD_MASK  0x0000ffff
+#define RNR_REGS_CFG_STALL_CNT1_STALL_ON_JMP_FULL_CNT_FIELD_WIDTH 16
+#define RNR_REGS_CFG_STALL_CNT1_STALL_ON_JMP_FULL_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_STALL_CNT1_TOTAL_STALL_CNT_FIELD;
+#define RNR_REGS_CFG_STALL_CNT1_TOTAL_STALL_CNT_FIELD_MASK  0xffff0000
+#define RNR_REGS_CFG_STALL_CNT1_TOTAL_STALL_CNT_FIELD_WIDTH 16
+#define RNR_REGS_CFG_STALL_CNT1_TOTAL_STALL_CNT_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_STALL_CNT2_STALL_ON_ALU_B_FULL_CNT_FIELD;
+#define RNR_REGS_CFG_STALL_CNT2_STALL_ON_ALU_B_FULL_CNT_FIELD_MASK  0x0000ffff
+#define RNR_REGS_CFG_STALL_CNT2_STALL_ON_ALU_B_FULL_CNT_FIELD_WIDTH 16
+#define RNR_REGS_CFG_STALL_CNT2_STALL_ON_ALU_B_FULL_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_STALL_CNT2_STALL_ON_ALU_A_FULL_CNT_FIELD;
+#define RNR_REGS_CFG_STALL_CNT2_STALL_ON_ALU_A_FULL_CNT_FIELD_MASK  0xffff0000
+#define RNR_REGS_CFG_STALL_CNT2_STALL_ON_ALU_A_FULL_CNT_FIELD_WIDTH 16
+#define RNR_REGS_CFG_STALL_CNT2_STALL_ON_ALU_A_FULL_CNT_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_STALL_CNT3_STALL_ON_JMPREG_FIELD;
+#define RNR_REGS_CFG_STALL_CNT3_STALL_ON_JMPREG_FIELD_MASK  0x0000ffff
+#define RNR_REGS_CFG_STALL_CNT3_STALL_ON_JMPREG_FIELD_WIDTH 16
+#define RNR_REGS_CFG_STALL_CNT3_STALL_ON_JMPREG_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_STALL_CNT3_STALL_ON_MEMIO_FULL_CNT_FIELD;
+#define RNR_REGS_CFG_STALL_CNT3_STALL_ON_MEMIO_FULL_CNT_FIELD_MASK  0xffff0000
+#define RNR_REGS_CFG_STALL_CNT3_STALL_ON_MEMIO_FULL_CNT_FIELD_WIDTH 16
+#define RNR_REGS_CFG_STALL_CNT3_STALL_ON_MEMIO_FULL_CNT_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_STALL_CNT4_STALL_ON_WAW_CNT_FIELD;
+#define RNR_REGS_CFG_STALL_CNT4_STALL_ON_WAW_CNT_FIELD_MASK  0x0000ffff
+#define RNR_REGS_CFG_STALL_CNT4_STALL_ON_WAW_CNT_FIELD_WIDTH 16
+#define RNR_REGS_CFG_STALL_CNT4_STALL_ON_WAW_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_STALL_CNT4_ACTIVE_CYCLES_CNT_FIELD;
+#define RNR_REGS_CFG_STALL_CNT4_ACTIVE_CYCLES_CNT_FIELD_MASK  0xffff0000
+#define RNR_REGS_CFG_STALL_CNT4_ACTIVE_CYCLES_CNT_FIELD_WIDTH 16
+#define RNR_REGS_CFG_STALL_CNT4_ACTIVE_CYCLES_CNT_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_TRACE_WRITE_PNT_FIELD;
+#define RNR_REGS_CFG_PROFILING_STS_TRACE_WRITE_PNT_FIELD_MASK  0x00001fff
+#define RNR_REGS_CFG_PROFILING_STS_TRACE_WRITE_PNT_FIELD_WIDTH 13
+#define RNR_REGS_CFG_PROFILING_STS_TRACE_WRITE_PNT_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_IDLE_NO_ACTIVE_TASK_FIELD;
+#define RNR_REGS_CFG_PROFILING_STS_IDLE_NO_ACTIVE_TASK_FIELD_MASK  0x00002000
+#define RNR_REGS_CFG_PROFILING_STS_IDLE_NO_ACTIVE_TASK_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_STS_IDLE_NO_ACTIVE_TASK_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_CURR_THREAD_NUM_FIELD;
+#define RNR_REGS_CFG_PROFILING_STS_CURR_THREAD_NUM_FIELD_MASK  0x0003c000
+#define RNR_REGS_CFG_PROFILING_STS_CURR_THREAD_NUM_FIELD_WIDTH 4
+#define RNR_REGS_CFG_PROFILING_STS_CURR_THREAD_NUM_FIELD_SHIFT 14
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_PROFILING_ACTIVE_FIELD;
+#define RNR_REGS_CFG_PROFILING_STS_PROFILING_ACTIVE_FIELD_MASK  0x00040000
+#define RNR_REGS_CFG_PROFILING_STS_PROFILING_ACTIVE_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_STS_PROFILING_ACTIVE_FIELD_SHIFT 18
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_TRACE_FIFO_OVERRUN_FIELD;
+#define RNR_REGS_CFG_PROFILING_STS_TRACE_FIFO_OVERRUN_FIELD_MASK  0x00080000
+#define RNR_REGS_CFG_PROFILING_STS_TRACE_FIFO_OVERRUN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_STS_TRACE_FIFO_OVERRUN_FIELD_SHIFT 19
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_RESERVED0_FIELD;
+#define RNR_REGS_CFG_PROFILING_STS_RESERVED0_FIELD_MASK  0xfff00000
+#define RNR_REGS_CFG_PROFILING_STS_RESERVED0_FIELD_WIDTH 12
+#define RNR_REGS_CFG_PROFILING_STS_RESERVED0_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_0_TRACE_BASE_ADDR_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_BASE_ADDR_FIELD_MASK  0x00001fff
+#define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_BASE_ADDR_FIELD_WIDTH 13
+#define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_BASE_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_0_RESERVED0_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED0_FIELD_WIDTH 3
+#define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_0_TRACE_MAX_ADDR_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_MAX_ADDR_FIELD_MASK  0x1fff0000
+#define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_MAX_ADDR_FIELD_WIDTH 13
+#define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_MAX_ADDR_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_0_RESERVED1_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED1_FIELD_MASK  0xe0000000
+#define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED1_FIELD_WIDTH 3
+#define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED1_FIELD_SHIFT 29
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_WRAPAROUND_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_WRAPAROUND_FIELD_MASK  0x00000001
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_WRAPAROUND_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_WRAPAROUND_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_MODE_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_MODE_FIELD_MASK  0x00000002
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_MODE_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_MODE_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_IDLE_IN_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_IDLE_IN_FIELD_MASK  0x00000004
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_IDLE_IN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_IDLE_IN_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_WAKEUP_LOG_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_WAKEUP_LOG_FIELD_MASK  0x00000008
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_WAKEUP_LOG_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_WAKEUP_LOG_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_TASK_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_TASK_FIELD_MASK  0x000000f0
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_TASK_FIELD_WIDTH 4
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_TASK_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_IDLE_COUNTER_SOURCE_SEL_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_1_IDLE_COUNTER_SOURCE_SEL_FIELD_MASK  0x00000100
+#define RNR_REGS_CFG_PROFILING_CFG_1_IDLE_COUNTER_SOURCE_SEL_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_CFG_1_IDLE_COUNTER_SOURCE_SEL_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_COUNTERS_SELECTED_TASK_MODE_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_1_COUNTERS_SELECTED_TASK_MODE_FIELD_MASK  0x00000200
+#define RNR_REGS_CFG_PROFILING_CFG_1_COUNTERS_SELECTED_TASK_MODE_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_CFG_1_COUNTERS_SELECTED_TASK_MODE_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_COUNTERS_TASK_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_1_COUNTERS_TASK_FIELD_MASK  0x00003c00
+#define RNR_REGS_CFG_PROFILING_CFG_1_COUNTERS_TASK_FIELD_WIDTH 4
+#define RNR_REGS_CFG_PROFILING_CFG_1_COUNTERS_TASK_FIELD_SHIFT 10
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_RESERVED0_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_1_RESERVED0_FIELD_MASK  0x3fffc000
+#define RNR_REGS_CFG_PROFILING_CFG_1_RESERVED0_FIELD_WIDTH 16
+#define RNR_REGS_CFG_PROFILING_CFG_1_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_RESET_EVENT_FIFO_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_RESET_EVENT_FIFO_FIELD_MASK  0x40000000
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_RESET_EVENT_FIFO_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_RESET_EVENT_FIFO_FIELD_SHIFT 30
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_CLEAR_FIFO_OVERRUN_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_CLEAR_FIFO_OVERRUN_FIELD_MASK  0x80000000
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_CLEAR_FIFO_OVERRUN_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_CLEAR_FIFO_OVERRUN_FIELD_SHIFT 31
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_COUNTER_VAL_FIELD;
+#define RNR_REGS_CFG_PROFILING_COUNTER_VAL_FIELD_MASK  0xffffffff
+#define RNR_REGS_CFG_PROFILING_COUNTER_VAL_FIELD_WIDTH 32
+#define RNR_REGS_CFG_PROFILING_COUNTER_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_2_EN_PROF_ON_SELECTED_PC_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_2_EN_PROF_ON_SELECTED_PC_FIELD_MASK  0x00000001
+#define RNR_REGS_CFG_PROFILING_CFG_2_EN_PROF_ON_SELECTED_PC_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_CFG_2_EN_PROF_ON_SELECTED_PC_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_2_TRIGGER_ON_SECOND_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_2_TRIGGER_ON_SECOND_FIELD_MASK  0x00000002
+#define RNR_REGS_CFG_PROFILING_CFG_2_TRIGGER_ON_SECOND_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_CFG_2_TRIGGER_ON_SECOND_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_2_PC_START_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_2_PC_START_FIELD_MASK  0x00007ffc
+#define RNR_REGS_CFG_PROFILING_CFG_2_PC_START_FIELD_WIDTH 13
+#define RNR_REGS_CFG_PROFILING_CFG_2_PC_START_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_2_PC_STOP_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_2_PC_STOP_FIELD_MASK  0x0fff8000
+#define RNR_REGS_CFG_PROFILING_CFG_2_PC_STOP_FIELD_WIDTH 13
+#define RNR_REGS_CFG_PROFILING_CFG_2_PC_STOP_FIELD_SHIFT 15
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_2_DISABLE_NOPS_AND_UNCOND_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_2_DISABLE_NOPS_AND_UNCOND_FIELD_MASK  0x10000000
+#define RNR_REGS_CFG_PROFILING_CFG_2_DISABLE_NOPS_AND_UNCOND_FIELD_WIDTH 1
+#define RNR_REGS_CFG_PROFILING_CFG_2_DISABLE_NOPS_AND_UNCOND_FIELD_SHIFT 28
+
+extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_2_RESERVED0_FIELD;
+#define RNR_REGS_CFG_PROFILING_CFG_2_RESERVED0_FIELD_MASK  0xe0000000
+#define RNR_REGS_CFG_PROFILING_CFG_2_RESERVED0_FIELD_WIDTH 3
+#define RNR_REGS_CFG_PROFILING_CFG_2_RESERVED0_FIELD_SHIFT 29
+
+extern const ru_field_rec RNR_REGS_CFG_EXEC_CMDS_CNT_EXEC_COUNTER_FIELD;
+#define RNR_REGS_CFG_EXEC_CMDS_CNT_EXEC_COUNTER_FIELD_MASK  0xffffffff
+#define RNR_REGS_CFG_EXEC_CMDS_CNT_EXEC_COUNTER_FIELD_WIDTH 32
+#define RNR_REGS_CFG_EXEC_CMDS_CNT_EXEC_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_IDLE_CNT1_IDLE_CNT_FIELD;
+#define RNR_REGS_CFG_IDLE_CNT1_IDLE_CNT_FIELD_MASK  0xffffffff
+#define RNR_REGS_CFG_IDLE_CNT1_IDLE_CNT_FIELD_WIDTH 32
+#define RNR_REGS_CFG_IDLE_CNT1_IDLE_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_JMP_CNT_UNTAKEN_JMP_CNT_FIELD;
+#define RNR_REGS_CFG_JMP_CNT_UNTAKEN_JMP_CNT_FIELD_MASK  0x0000ffff
+#define RNR_REGS_CFG_JMP_CNT_UNTAKEN_JMP_CNT_FIELD_WIDTH 16
+#define RNR_REGS_CFG_JMP_CNT_UNTAKEN_JMP_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_REGS_CFG_JMP_CNT_TAKEN_JMP_CNT_FIELD;
+#define RNR_REGS_CFG_JMP_CNT_TAKEN_JMP_CNT_FIELD_MASK  0xffff0000
+#define RNR_REGS_CFG_JMP_CNT_TAKEN_JMP_CNT_FIELD_WIDTH 16
+#define RNR_REGS_CFG_JMP_CNT_TAKEN_JMP_CNT_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_REGS_CFG_METAL_FIX_REG_METAL_FIX_FIELD;
+#define RNR_REGS_CFG_METAL_FIX_REG_METAL_FIX_FIELD_MASK  0xffffffff
+#define RNR_REGS_CFG_METAL_FIX_REG_METAL_FIX_FIELD_WIDTH 32
+#define RNR_REGS_CFG_METAL_FIX_REG_METAL_FIX_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_CFG_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_CFG_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_CFG_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_CFG_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_EXCEPTION_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_EXCEPTION_EN_FIELD_MASK  0x000fffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_EXCEPTION_EN_FIELD_WIDTH 20
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_EXCEPTION_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_PROFILE_US_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_PROFILE_US_FIELD_MASK  0x00700000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_PROFILE_US_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_PROFILE_US_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_DISABLE_L2TP_SOURCE_PORT_CHECK_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_DISABLE_L2TP_SOURCE_PORT_CHECK_FIELD_MASK  0x00800000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_DISABLE_L2TP_SOURCE_PORT_CHECK_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_DISABLE_L2TP_SOURCE_PORT_CHECK_FIELD_SHIFT 23
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_TCP_FLAGS_FILT_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_TCP_FLAGS_FILT_FIELD_MASK  0xff000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_TCP_FLAGS_FILT_FIELD_WIDTH 8
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_TCP_FLAGS_FILT_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_FIELD_MASK  0x00000fff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_FIELD_WIDTH 12
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED0_FIELD_MASK  0x00007000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_FIELD_MASK  0x00008000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_FIELD_SHIFT 15
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_FIELD_MASK  0x0fff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_FIELD_WIDTH 12
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED1_FIELD_MASK  0x70000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED1_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED1_FIELD_SHIFT 28
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_FIELD_MASK  0x80000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_FIELD_SHIFT 31
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_FIELD_MASK  0x00000fff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_FIELD_WIDTH 12
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED0_FIELD_MASK  0x00007000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_FIELD_MASK  0x00008000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_FIELD_SHIFT 15
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_FIELD_MASK  0x0fff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_FIELD_WIDTH 12
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED1_FIELD_MASK  0x70000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED1_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED1_FIELD_SHIFT 28
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_FIELD_MASK  0x80000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_FIELD_SHIFT 31
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_FIELD_MASK  0x00000fff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_FIELD_WIDTH 12
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED0_FIELD_MASK  0x00007000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_FIELD_MASK  0x00008000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_FIELD_SHIFT 15
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_FIELD_MASK  0x0fff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_FIELD_WIDTH 12
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED1_FIELD_MASK  0x70000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED1_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED1_FIELD_SHIFT 28
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_FIELD_MASK  0x80000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_FIELD_SHIFT 31
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_FIELD_MASK  0x00000fff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_FIELD_WIDTH 12
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED0_FIELD_MASK  0x00007000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_FIELD_MASK  0x00008000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_FIELD_SHIFT 15
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_FIELD_MASK  0x0fff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_FIELD_WIDTH 12
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED1_FIELD_MASK  0x70000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED1_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED1_FIELD_SHIFT 28
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_FIELD_MASK  0x80000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_FIELD_SHIFT 31
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_FIELD_MASK  0x00000001
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_FIELD_MASK  0x00000002
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_FIELD_MASK  0x00000004
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_FIELD_MASK  0x00000008
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_FIELD_MASK  0x00000010
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_FIELD_MASK  0x00000020
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_FIELD_SHIFT 5
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_FIELD_MASK  0x00000040
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_FIELD_SHIFT 6
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_FIELD_MASK  0x00000080
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_FIELD_SHIFT 7
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RESERVED0_FIELD_MASK  0xffffff00
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RESERVED0_FIELD_WIDTH 24
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_FIELD_MASK  0x00ffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_FIELD_WIDTH 24
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_FIELD_MASK  0x01000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_FIELD_MASK  0x02000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_FIELD_SHIFT 25
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED0_FIELD_MASK  0xfc000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED0_FIELD_WIDTH 6
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED0_FIELD_SHIFT 26
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_FIELD_MASK  0x00000003
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_FIELD_WIDTH 2
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_FIELD_MASK  0x0000000c
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_FIELD_WIDTH 2
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_FIELD_MASK  0x00000030
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_FIELD_WIDTH 2
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_FIELD_MASK  0x000000c0
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_FIELD_WIDTH 2
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_FIELD_SHIFT 6
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_FIELD_MASK  0x00000f00
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_FIELD_WIDTH 4
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RESERVED0_FIELD_MASK  0x0000f000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RESERVED0_FIELD_WIDTH 4
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_FIELD_MASK  0x000f0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_FIELD_WIDTH 4
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_FIELD_MASK  0x00f00000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_FIELD_WIDTH 4
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_FIELD_MASK  0x0f000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_FIELD_WIDTH 4
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_FIELD_MASK  0xf0000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_FIELD_WIDTH 4
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_FIELD_SHIFT 28
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_FIELD_MASK  0x00000001
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_FIELD_MASK  0x00000002
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_FIELD_MASK  0x00000004
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_AH_MATCH_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_AH_MATCH_FIELD_MASK  0x00000008
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_AH_MATCH_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_AH_MATCH_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RESERVED0_FIELD_MASK  0xfffffff0
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RESERVED0_FIELD_WIDTH 28
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_0_FIELD_MASK  0x00000007
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_0_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_0_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_1_FIELD_MASK  0x00000038
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_1_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_1_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_2_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_2_FIELD_MASK  0x000001c0
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_2_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_2_FIELD_SHIFT 6
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_0_FIELD_MASK  0x00000e00
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_0_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_0_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_1_FIELD_MASK  0x00007000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_1_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_1_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_2_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_2_FIELD_MASK  0x00038000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_2_FIELD_WIDTH 3
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_2_FIELD_SHIFT 15
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED0_FIELD_MASK  0x0ffc0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED0_FIELD_WIDTH 10
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_MAX_NUM_OF_VLANS_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_MAX_NUM_OF_VLANS_FIELD_MASK  0xf0000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_MAX_NUM_OF_VLANS_FIELD_WIDTH 4
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_MAX_NUM_OF_VLANS_FIELD_SHIFT 28
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_FIELD_MASK  0x00000fff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_FIELD_WIDTH 12
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_RESERVED0_FIELD_MASK  0xfffff000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_RESERVED0_FIELD_WIDTH 20
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_FIELD_MASK  0x00000fff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_FIELD_WIDTH 12
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_RESERVED0_FIELD_MASK  0xfffff000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_RESERVED0_FIELD_WIDTH 20
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_FIELD_MASK  0x00000fff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_FIELD_WIDTH 12
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_RESERVED0_FIELD_MASK  0xfffff000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_RESERVED0_FIELD_WIDTH 20
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_FIELD_MASK  0x000000ff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_FIELD_WIDTH 8
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_FIELD_MASK  0x0000ff00
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_FIELD_WIDTH 8
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_FIELD_MASK  0x00ff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_FIELD_WIDTH 8
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_FIELD_MASK  0xff000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_FIELD_WIDTH 8
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_DA_FILT_MSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_DA_FILT_MSB_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_DA_FILT_MSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_DA_FILT_MSB_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_DA_FILT_LSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_DA_FILT_LSB_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_DA_FILT_MSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_DA_FILT_MSB_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT_MASK_L_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT_MASK_L_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT_MASK_L_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT_MASK_L_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT_MASK_L_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT_MASK_L_FIELD_MASK  0xffffffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT_MASK_L_FIELD_WIDTH 32
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT_MASK_L_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT0_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT0_VALID_FIELD_MASK  0x00000001
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT0_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT0_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT1_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT1_VALID_FIELD_MASK  0x00000002
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT1_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT1_VALID_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT2_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT2_VALID_FIELD_MASK  0x00000004
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT2_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT2_VALID_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT3_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT3_VALID_FIELD_MASK  0x00000008
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT3_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT3_VALID_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT4_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT4_VALID_FIELD_MASK  0x00000010
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT4_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT4_VALID_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT5_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT5_VALID_FIELD_MASK  0x00000020
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT5_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT5_VALID_FIELD_SHIFT 5
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT6_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT6_VALID_FIELD_MASK  0x00000040
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT6_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT6_VALID_FIELD_SHIFT 6
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT7_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT7_VALID_FIELD_MASK  0x00000080
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT7_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT7_VALID_FIELD_SHIFT 7
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT8_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT8_VALID_FIELD_MASK  0x00000100
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT8_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT8_VALID_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_RESERVED0_FIELD_MASK  0xfffffe00
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_RESERVED0_FIELD_WIDTH 23
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT0_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT0_VALID_FIELD_MASK  0x00000001
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT0_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT0_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT1_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT1_VALID_FIELD_MASK  0x00000002
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT1_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT1_VALID_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT2_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT2_VALID_FIELD_MASK  0x00000004
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT2_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT2_VALID_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT3_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT3_VALID_FIELD_MASK  0x00000008
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT3_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT3_VALID_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT4_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT4_VALID_FIELD_MASK  0x00000010
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT4_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT4_VALID_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT5_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT5_VALID_FIELD_MASK  0x00000020
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT5_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT5_VALID_FIELD_SHIFT 5
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT6_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT6_VALID_FIELD_MASK  0x00000040
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT6_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT6_VALID_FIELD_SHIFT 6
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT7_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT7_VALID_FIELD_MASK  0x00000080
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT7_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT7_VALID_FIELD_SHIFT 7
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT8_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT8_VALID_FIELD_MASK  0x00000100
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT8_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT8_VALID_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_RESERVED0_FIELD_MASK  0xfffffe00
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_RESERVED0_FIELD_WIDTH 23
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT0_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT0_VALID_FIELD_MASK  0x00000001
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT0_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT0_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT1_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT1_VALID_FIELD_MASK  0x00000002
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT1_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT1_VALID_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT2_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT2_VALID_FIELD_MASK  0x00000004
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT2_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT2_VALID_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT3_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT3_VALID_FIELD_MASK  0x00000008
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT3_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT3_VALID_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT4_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT4_VALID_FIELD_MASK  0x00000010
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT4_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT4_VALID_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT5_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT5_VALID_FIELD_MASK  0x00000020
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT5_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT5_VALID_FIELD_SHIFT 5
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT6_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT6_VALID_FIELD_MASK  0x00000040
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT6_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT6_VALID_FIELD_SHIFT 6
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT7_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT7_VALID_FIELD_MASK  0x00000080
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT7_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT7_VALID_FIELD_SHIFT 7
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT8_VALID_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT8_VALID_FIELD_MASK  0x00000100
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT8_VALID_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT8_VALID_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_RESERVED0_FIELD_MASK  0xfffffe00
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_RESERVED0_FIELD_WIDTH 23
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_0_FIELD_MASK  0x0000001f
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_0_FIELD_WIDTH 5
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_0_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_1_FIELD_MASK  0x000003e0
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_1_FIELD_WIDTH 5
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_1_FIELD_SHIFT 5
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_2_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_2_FIELD_MASK  0x00007c00
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_2_FIELD_WIDTH 5
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_2_FIELD_SHIFT 10
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_0_FIELD_MASK  0x00008000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_0_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_0_FIELD_SHIFT 15
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_1_FIELD_MASK  0x00010000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_1_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_1_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_2_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_2_FIELD_MASK  0x00020000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_2_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_2_FIELD_SHIFT 17
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_RESERVED0_FIELD_MASK  0xfffc0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_RESERVED0_FIELD_WIDTH 14
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DOS_ATTACK_MASK_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DOS_ATTACK_MASK_FIELD_MASK  0x0000ffff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DOS_ATTACK_MASK_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DOS_ATTACK_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DOS_ATTACK_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DOS_ATTACK_RESERVED0_FIELD_MASK  0xffff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DOS_ATTACK_RESERVED0_FIELD_WIDTH 16
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DOS_ATTACK_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_V4_SIZE_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_V4_SIZE_FIELD_MASK  0x000007ff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_V4_SIZE_FIELD_WIDTH 11
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_V4_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_RESERVED0_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_RESERVED0_FIELD_MASK  0x0000f800
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_RESERVED0_FIELD_WIDTH 5
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_V6_SIZE_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_V6_SIZE_FIELD_MASK  0x07ff0000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_V6_SIZE_FIELD_WIDTH 11
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_V6_SIZE_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_R1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_R1_FIELD_MASK  0xf8000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_R1_FIELD_WIDTH 5
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_R1_FIELD_SHIFT 27
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L2_TOS_MASK_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L2_TOS_MASK_FIELD_MASK  0x000000ff
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L2_TOS_MASK_FIELD_WIDTH 8
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L2_TOS_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L3_TOS_MASK_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L3_TOS_MASK_FIELD_MASK  0x0000ff00
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L3_TOS_MASK_FIELD_WIDTH 8
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L3_TOS_MASK_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L2_EXCLUDE_SMAC_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L2_EXCLUDE_SMAC_FIELD_MASK  0x00010000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L2_EXCLUDE_SMAC_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L2_EXCLUDE_SMAC_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_TCP_PURE_ACK_MASK_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_TCP_PURE_ACK_MASK_FIELD_MASK  0x00020000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_TCP_PURE_ACK_MASK_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_TCP_PURE_ACK_MASK_FIELD_SHIFT 17
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_INCUDE_DEI_IN_VLANS_CRC_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_INCUDE_DEI_IN_VLANS_CRC_FIELD_MASK  0x00040000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_INCUDE_DEI_IN_VLANS_CRC_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_INCUDE_DEI_IN_VLANS_CRC_FIELD_SHIFT 18
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_KEY_SIZE_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_KEY_SIZE_FIELD_MASK  0x00080000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_KEY_SIZE_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_KEY_SIZE_FIELD_SHIFT 19
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_MAX_NUM_OF_VLANS_IN_CRC_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_MAX_NUM_OF_VLANS_IN_CRC_FIELD_MASK  0x00f00000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_MAX_NUM_OF_VLANS_IN_CRC_FIELD_WIDTH 4
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_MAX_NUM_OF_VLANS_IN_CRC_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L3_TCP_PURE_ACK_MASK_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L3_TCP_PURE_ACK_MASK_FIELD_MASK  0x01000000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L3_TCP_PURE_ACK_MASK_FIELD_WIDTH 1
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_L3_TCP_PURE_ACK_MASK_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_R1_FIELD;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_R1_FIELD_MASK  0xff800000
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_R1_FIELD_WIDTH 9
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_R1_FIELD_SHIFT 23
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_USE_FIFO_FOR_DDR_ONLY_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_USE_FIFO_FOR_DDR_ONLY_FIELD_MASK  0x00000001
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_USE_FIFO_FOR_DDR_ONLY_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_USE_FIFO_FOR_DDR_ONLY_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_TOKEN_ARBITER_IS_RR_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_TOKEN_ARBITER_IS_RR_FIELD_MASK  0x00000002
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_TOKEN_ARBITER_IS_RR_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_TOKEN_ARBITER_IS_RR_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CHICKEN_NO_FLOWCTRL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CHICKEN_NO_FLOWCTRL_FIELD_MASK  0x00000004
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CHICKEN_NO_FLOWCTRL_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CHICKEN_NO_FLOWCTRL_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_FLOW_CTRL_CLEAR_TOKEN_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_FLOW_CTRL_CLEAR_TOKEN_FIELD_MASK  0x00000008
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_FLOW_CTRL_CLEAR_TOKEN_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_FLOW_CTRL_CLEAR_TOKEN_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_DDR_CONGEST_THRESHOLD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_DDR_CONGEST_THRESHOLD_FIELD_MASK  0x000001f0
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_DDR_CONGEST_THRESHOLD_FIELD_WIDTH 5
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_DDR_CONGEST_THRESHOLD_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_PSRAM_CONGEST_THRESHOLD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_PSRAM_CONGEST_THRESHOLD_FIELD_MASK  0x00003e00
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_PSRAM_CONGEST_THRESHOLD_FIELD_WIDTH 5
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_PSRAM_CONGEST_THRESHOLD_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED0_FIELD_MASK  0x00004000
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED0_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_ENABLE_REPLY_THRESHOLD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_ENABLE_REPLY_THRESHOLD_FIELD_MASK  0x00008000
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_ENABLE_REPLY_THRESHOLD_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_ENABLE_REPLY_THRESHOLD_FIELD_SHIFT 15
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_DDR_REPLY_THRESHOLD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_DDR_REPLY_THRESHOLD_FIELD_MASK  0x00ff0000
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_DDR_REPLY_THRESHOLD_FIELD_WIDTH 8
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_DDR_REPLY_THRESHOLD_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_PSRAM_REPLY_THRESHOLD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_PSRAM_REPLY_THRESHOLD_FIELD_MASK  0xff000000
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_PSRAM_REPLY_THRESHOLD_FIELD_WIDTH 8
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_PSRAM_REPLY_THRESHOLD_FIELD_SHIFT 24
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_VAL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_COUNTER_LSB_SEL_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_COUNTER_LSB_SEL_FIELD_MASK  0x0000001f
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_COUNTER_LSB_SEL_FIELD_WIDTH 5
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_COUNTER_LSB_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED0_FIELD_MASK  0x000000e0
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_0_FIELD_MASK  0x00000100
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_0_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_0_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_1_FIELD_MASK  0x00000200
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_1_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_1_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_2_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_2_FIELD_MASK  0x00000400
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_2_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_2_FIELD_SHIFT 10
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_3_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_3_FIELD_MASK  0x00000800
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_3_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_3_FIELD_SHIFT 11
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_4_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_4_FIELD_MASK  0x00001000
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_4_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_4_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_5_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_5_FIELD_MASK  0x00002000
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_5_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_5_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED1_FIELD_MASK  0xffffc000
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED1_FIELD_WIDTH 18
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_ADDR_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_ADDR_FIELD_MASK  0x00001fff
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_ADDR_FIELD_WIDTH 13
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_THREAD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_THREAD_FIELD_MASK  0x000f0000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_THREAD_FIELD_WIDTH 4
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_THREAD_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED1_FIELD_MASK  0xfff00000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED1_FIELD_WIDTH 12
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_ADDR_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_ADDR_FIELD_MASK  0x00001fff
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_ADDR_FIELD_WIDTH 13
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_THREAD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_THREAD_FIELD_MASK  0x000f0000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_THREAD_FIELD_WIDTH 4
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_THREAD_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED1_FIELD_MASK  0xfff00000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED1_FIELD_WIDTH 12
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_ADDR_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_ADDR_FIELD_MASK  0x00001fff
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_ADDR_FIELD_WIDTH 13
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_THREAD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_THREAD_FIELD_MASK  0x000f0000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_THREAD_FIELD_WIDTH 4
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_THREAD_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED1_FIELD_MASK  0xfff00000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED1_FIELD_WIDTH 12
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_ADDR_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_ADDR_FIELD_MASK  0x00001fff
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_ADDR_FIELD_WIDTH 13
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_THREAD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_THREAD_FIELD_MASK  0x000f0000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_THREAD_FIELD_WIDTH 4
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_THREAD_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED1_FIELD_MASK  0xfff00000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED1_FIELD_WIDTH 12
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_ADDR_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_ADDR_FIELD_MASK  0x00001fff
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_ADDR_FIELD_WIDTH 13
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_THREAD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_THREAD_FIELD_MASK  0x000f0000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_THREAD_FIELD_WIDTH 4
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_THREAD_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED1_FIELD_MASK  0xfff00000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED1_FIELD_WIDTH 12
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_ADDR_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_ADDR_FIELD_MASK  0x00001fff
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_ADDR_FIELD_WIDTH 13
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_THREAD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_THREAD_FIELD_MASK  0x000f0000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_THREAD_FIELD_WIDTH 4
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_THREAD_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED1_FIELD_MASK  0xfff00000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED1_FIELD_WIDTH 12
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_ADDR_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_ADDR_FIELD_MASK  0x00001fff
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_ADDR_FIELD_WIDTH 13
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_THREAD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_THREAD_FIELD_MASK  0x000f0000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_THREAD_FIELD_WIDTH 4
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_THREAD_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED1_FIELD_MASK  0xfff00000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED1_FIELD_WIDTH 12
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_ADDR_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_ADDR_FIELD_MASK  0x00001fff
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_ADDR_FIELD_WIDTH 13
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_THREAD_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_THREAD_FIELD_MASK  0x000f0000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_THREAD_FIELD_WIDTH 4
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_THREAD_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED1_FIELD_MASK  0xfff00000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED1_FIELD_WIDTH 12
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_FIELD_MASK  0x00001fff
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_FIELD_WIDTH 13
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED0_FIELD_MASK  0x0000e000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED0_FIELD_WIDTH 3
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_FIELD_MASK  0x1fff0000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_FIELD_WIDTH 13
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED1_FIELD_MASK  0xe0000000
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED1_FIELD_WIDTH 3
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED1_FIELD_SHIFT 29
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_FIELD_MASK  0x000000ff
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_FIELD_WIDTH 8
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_0_FIELD_MASK  0x00000100
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_0_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_0_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_1_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_1_FIELD_MASK  0x00000200
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_1_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_1_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_2_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_2_FIELD_MASK  0x00000400
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_2_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_2_FIELD_SHIFT 10
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_3_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_3_FIELD_MASK  0x00000800
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_3_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_3_FIELD_SHIFT 11
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_4_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_4_FIELD_MASK  0x00001000
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_4_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_4_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_5_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_5_FIELD_MASK  0x00002000
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_5_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_5_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_RESERVED0_FIELD_MASK  0xffffc000
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_RESERVED0_FIELD_WIDTH 18
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_0_STATUS_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_0_STATUS_FIELD_MASK  0x00000001
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_0_STATUS_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_0_STATUS_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_1_STATUS_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_1_STATUS_FIELD_MASK  0x00000002
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_1_STATUS_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_1_STATUS_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_2_STATUS_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_2_STATUS_FIELD_MASK  0x00000004
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_2_STATUS_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_2_STATUS_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_3_STATUS_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_3_STATUS_FIELD_MASK  0x00000008
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_3_STATUS_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_3_STATUS_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_4_STATUS_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_4_STATUS_FIELD_MASK  0x00000010
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_4_STATUS_FIELD_WIDTH 1
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_4_STATUS_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_RESERVED0_FIELD;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_RESERVED0_FIELD_MASK  0xffffffe0
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_RESERVED0_FIELD_WIDTH 27
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RST_FIELD;
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RST_FIELD_MASK  0x00000001
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RST_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RST_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RST_FIELD;
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RST_FIELD_MASK  0x00000002
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RST_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RST_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RST_FIELD;
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RST_FIELD_MASK  0x00000004
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RST_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RST_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED0_FIELD;
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED0_FIELD_MASK  0x000000f8
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED0_FIELD_WIDTH 5
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_FIELD;
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_FIELD_MASK  0x00000f00
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_FIELD_WIDTH 4
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_FIELD;
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_FIELD_MASK  0x0000f000
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_FIELD_WIDTH 4
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_FIELD;
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_FIELD_MASK  0x000f0000
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_FIELD_WIDTH 4
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED1_FIELD;
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED1_FIELD_MASK  0xfff00000
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED1_FIELD_WIDTH 12
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_FULL_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_FULL_FIELD_MASK  0x00000001
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_FULL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_EMPTY_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_EMPTY_FIELD_MASK  0x00000002
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_EMPTY_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED0_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED0_FIELD_MASK  0x0000000c
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED0_FIELD_WIDTH 2
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_MASK  0x000001f0
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_WIDTH 5
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED1_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED1_FIELD_MASK  0x00000e00
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED1_FIELD_WIDTH 3
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED1_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_MASK  0x0001f000
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_WIDTH 5
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED2_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED2_FIELD_MASK  0x000e0000
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED2_FIELD_WIDTH 3
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED2_FIELD_SHIFT 17
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x01f00000
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 5
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED3_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED3_FIELD_MASK  0xfe000000
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED3_FIELD_WIDTH 7
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED3_FIELD_SHIFT 25
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_FULL_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_FULL_FIELD_MASK  0x00000001
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_FULL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_EMPTY_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_EMPTY_FIELD_MASK  0x00000002
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_EMPTY_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_ALMOST_FULL_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_MASK  0x00000004
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED0_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED0_FIELD_MASK  0x00000008
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED0_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_FIELD_MASK  0x000001f0
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_FIELD_WIDTH 5
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED1_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED1_FIELD_MASK  0x00000e00
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED1_FIELD_WIDTH 3
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED1_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_FIELD_MASK  0x0001f000
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_FIELD_WIDTH 5
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED2_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED2_FIELD_MASK  0x000e0000
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED2_FIELD_WIDTH 3
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED2_FIELD_SHIFT 17
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x01f00000
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 5
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED3_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED3_FIELD_MASK  0xfe000000
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED3_FIELD_WIDTH 7
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED3_FIELD_SHIFT 25
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_FULL_FIELD;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_FULL_FIELD_MASK  0x00000001
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_FULL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_EMPTY_FIELD;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_EMPTY_FIELD_MASK  0x00000002
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_EMPTY_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED0_FIELD;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED0_FIELD_MASK  0x0000000c
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED0_FIELD_WIDTH 2
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_MASK  0x000001f0
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_WIDTH 5
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED1_FIELD;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED1_FIELD_MASK  0x00000e00
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED1_FIELD_WIDTH 3
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED1_FIELD_SHIFT 9
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_MASK  0x0001f000
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_WIDTH 5
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_SHIFT 12
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED2_FIELD;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED2_FIELD_MASK  0x000e0000
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED2_FIELD_WIDTH 3
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED2_FIELD_SHIFT 17
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_FIELD;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_FIELD_MASK  0x01f00000
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 5
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 20
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED3_FIELD;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED3_FIELD_MASK  0xfe000000
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED3_FIELD_WIDTH 7
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED3_FIELD_SHIFT 25
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_FULL_FIELD;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_FULL_FIELD_MASK  0x00000001
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_FULL_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_FULL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_EMPTY_FIELD;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_EMPTY_FIELD_MASK  0x00000002
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_EMPTY_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_EMPTY_FIELD_SHIFT 1
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_ALMOST_FULL_FIELD;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_MASK  0x00000004
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_SHIFT 2
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED0_FIELD;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED0_FIELD_MASK  0x00000008
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED0_FIELD_WIDTH 1
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_FIELD;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_FIELD_MASK  0x00001ff0
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_FIELD_WIDTH 9
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_FIELD_SHIFT 4
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED1_FIELD;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED1_FIELD_MASK  0x0000e000
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED1_FIELD_WIDTH 3
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_FIELD;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_FIELD_MASK  0x01ff0000
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_FIELD_WIDTH 9
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_FIELD_SHIFT 16
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED2_FIELD;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED2_FIELD_MASK  0xfe000000
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED2_FIELD_WIDTH 7
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED2_FIELD_SHIFT 25
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_FIELD;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_FIELD_MASK  0x000000ff
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_FIELD_WIDTH 8
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_FIELD;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_FIELD_MASK  0x0001ff00
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_FIELD_WIDTH 9
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_FIELD_SHIFT 8
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_RESERVED0_FIELD;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_RESERVED0_FIELD_MASK  0xfffe0000
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_RESERVED0_FIELD_WIDTH 15
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_FIELD_MASK  0xffffffff
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_FIELD_WIDTH 32
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_FIELD_MASK  0xffffffff
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_FIELD_WIDTH 32
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_FIELD_MASK  0xffffffff
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_FIELD_WIDTH 32
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_FIELD;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_FIELD_MASK  0xffffffff
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_FIELD_WIDTH 32
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_DATA_FIELD;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_DATA_FIELD_MASK  0xffffffff
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_DATA_FIELD_WIDTH 32
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_DATA_FIELD;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_DATA_FIELD_MASK  0xffffffff
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_DATA_FIELD_WIDTH 32
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_FIELD;
+#define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_FIELD;
+#define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_FIELD;
+#define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_FIELD_MASK  0xffffffff
+#define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_FIELD_WIDTH 32
+#define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EN_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EN_FIELD_MASK  0x00000001
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EN_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED0_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED0_FIELD_MASK  0x000000fe
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED0_FIELD_WIDTH 7
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RDY_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RDY_FIELD_MASK  0x00000100
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RDY_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RDY_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED1_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED1_FIELD_MASK  0x0000fe00
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED1_FIELD_WIDTH 7
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED1_FIELD_SHIFT 9
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REORDR_PAR_MOD_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REORDR_PAR_MOD_FIELD_MASK  0x00010000
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REORDR_PAR_MOD_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REORDR_PAR_MOD_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_PER_Q_EGRS_CONGST_EN_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_PER_Q_EGRS_CONGST_EN_FIELD_MASK  0x00020000
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_PER_Q_EGRS_CONGST_EN_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_PER_Q_EGRS_CONGST_EN_FIELD_SHIFT 17
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_DSPTCH_SM_ENH_MOD_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_DSPTCH_SM_ENH_MOD_FIELD_MASK  0x00040000
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_DSPTCH_SM_ENH_MOD_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_DSPTCH_SM_ENH_MOD_FIELD_SHIFT 18
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_INGRS_PIPE_DLY_EN_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_INGRS_PIPE_DLY_EN_FIELD_MASK  0x00080000
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_INGRS_PIPE_DLY_EN_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_INGRS_PIPE_DLY_EN_FIELD_SHIFT 19
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_INGRS_PIPE_DLY_CNT_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_INGRS_PIPE_DLY_CNT_FIELD_MASK  0x00700000
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_INGRS_PIPE_DLY_CNT_FIELD_WIDTH 3
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_INGRS_PIPE_DLY_CNT_FIELD_SHIFT 20
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EGRS_DROP_ONLY_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EGRS_DROP_ONLY_FIELD_MASK  0x00800000
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EGRS_DROP_ONLY_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EGRS_DROP_ONLY_FIELD_SHIFT 23
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_CRDT_EFF_REP_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_CRDT_EFF_REP_FIELD_MASK  0x01000000
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_CRDT_EFF_REP_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_CRDT_EFF_REP_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED2_FIELD;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED2_FIELD_MASK  0xfe000000
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED2_FIELD_WIDTH 7
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED2_FIELD_SHIFT 25
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_VQ_EN_EN_FIELD;
+#define DSPTCHR_REORDER_CFG_VQ_EN_EN_FIELD_MASK  0xffffffff
+#define DSPTCHR_REORDER_CFG_VQ_EN_EN_FIELD_WIDTH 32
+#define DSPTCHR_REORDER_CFG_VQ_EN_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_SRC_ID_FIELD;
+#define DSPTCHR_REORDER_CFG_BB_CFG_SRC_ID_FIELD_MASK  0x0000003f
+#define DSPTCHR_REORDER_CFG_BB_CFG_SRC_ID_FIELD_WIDTH 6
+#define DSPTCHR_REORDER_CFG_BB_CFG_SRC_ID_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_RESERVED0_FIELD;
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED0_FIELD_MASK  0x000000c0
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED0_FIELD_WIDTH 2
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_DST_ID_OVRIDE_FIELD;
+#define DSPTCHR_REORDER_CFG_BB_CFG_DST_ID_OVRIDE_FIELD_MASK  0x00003f00
+#define DSPTCHR_REORDER_CFG_BB_CFG_DST_ID_OVRIDE_FIELD_WIDTH 6
+#define DSPTCHR_REORDER_CFG_BB_CFG_DST_ID_OVRIDE_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_RESERVED1_FIELD;
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED1_FIELD_MASK  0x0000c000
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED1_FIELD_WIDTH 2
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_ROUTE_OVRIDE_FIELD;
+#define DSPTCHR_REORDER_CFG_BB_CFG_ROUTE_OVRIDE_FIELD_MASK  0x03ff0000
+#define DSPTCHR_REORDER_CFG_BB_CFG_ROUTE_OVRIDE_FIELD_WIDTH 10
+#define DSPTCHR_REORDER_CFG_BB_CFG_ROUTE_OVRIDE_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_RESERVED2_FIELD;
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED2_FIELD_MASK  0x0c000000
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED2_FIELD_WIDTH 2
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED2_FIELD_SHIFT 26
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_OVRIDE_EN_FIELD;
+#define DSPTCHR_REORDER_CFG_BB_CFG_OVRIDE_EN_FIELD_MASK  0x10000000
+#define DSPTCHR_REORDER_CFG_BB_CFG_OVRIDE_EN_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_BB_CFG_OVRIDE_EN_FIELD_SHIFT 28
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_RESERVED3_FIELD;
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED3_FIELD_MASK  0xe0000000
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED3_FIELD_WIDTH 3
+#define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED3_FIELD_SHIFT 29
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD;
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK  0x00000001
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED0_FIELD;
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK  0x000000fe
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_FIELD;
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK  0x0000ff00
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD;
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK  0x00010000
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED1_FIELD;
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK  0x000e0000
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD;
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK  0x00700000
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED2_FIELD;
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK  0x00800000
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23
+
+extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD;
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK  0xff000000
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_CONGESTION_INGRS_CONGSTN_FRST_LVL_FIELD;
+#define DSPTCHR_CONGESTION_INGRS_CONGSTN_FRST_LVL_FIELD_MASK  0x00000fff
+#define DSPTCHR_CONGESTION_INGRS_CONGSTN_FRST_LVL_FIELD_WIDTH 12
+#define DSPTCHR_CONGESTION_INGRS_CONGSTN_FRST_LVL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_CONGESTION_INGRS_CONGSTN_SCND_LVL_FIELD;
+#define DSPTCHR_CONGESTION_INGRS_CONGSTN_SCND_LVL_FIELD_MASK  0x00fff000
+#define DSPTCHR_CONGESTION_INGRS_CONGSTN_SCND_LVL_FIELD_WIDTH 12
+#define DSPTCHR_CONGESTION_INGRS_CONGSTN_SCND_LVL_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_CONGESTION_INGRS_CONGSTN_HYST_THRS_FIELD;
+#define DSPTCHR_CONGESTION_INGRS_CONGSTN_HYST_THRS_FIELD_MASK  0xff000000
+#define DSPTCHR_CONGESTION_INGRS_CONGSTN_HYST_THRS_FIELD_WIDTH 8
+#define DSPTCHR_CONGESTION_INGRS_CONGSTN_HYST_THRS_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_CONGESTION_EGRS_CONGSTN_FRST_LVL_FIELD;
+#define DSPTCHR_CONGESTION_EGRS_CONGSTN_FRST_LVL_FIELD_MASK  0x00000fff
+#define DSPTCHR_CONGESTION_EGRS_CONGSTN_FRST_LVL_FIELD_WIDTH 12
+#define DSPTCHR_CONGESTION_EGRS_CONGSTN_FRST_LVL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_CONGESTION_EGRS_CONGSTN_SCND_LVL_FIELD;
+#define DSPTCHR_CONGESTION_EGRS_CONGSTN_SCND_LVL_FIELD_MASK  0x00fff000
+#define DSPTCHR_CONGESTION_EGRS_CONGSTN_SCND_LVL_FIELD_WIDTH 12
+#define DSPTCHR_CONGESTION_EGRS_CONGSTN_SCND_LVL_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_CONGESTION_EGRS_CONGSTN_HYST_THRS_FIELD;
+#define DSPTCHR_CONGESTION_EGRS_CONGSTN_HYST_THRS_FIELD_MASK  0xff000000
+#define DSPTCHR_CONGESTION_EGRS_CONGSTN_HYST_THRS_FIELD_WIDTH 8
+#define DSPTCHR_CONGESTION_EGRS_CONGSTN_HYST_THRS_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_FIELD;
+#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_FIELD_MASK  0x00000fff
+#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_FIELD_WIDTH 12
+#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_FIELD;
+#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_FIELD_MASK  0x00fff000
+#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_FIELD_WIDTH 12
+#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_FIELD;
+#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_FIELD_MASK  0xff000000
+#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_FIELD_WIDTH 8
+#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_CONGESTION_GLBL_CONGSTN_FRST_LVL_FIELD;
+#define DSPTCHR_CONGESTION_GLBL_CONGSTN_FRST_LVL_FIELD_MASK  0x00000fff
+#define DSPTCHR_CONGESTION_GLBL_CONGSTN_FRST_LVL_FIELD_WIDTH 12
+#define DSPTCHR_CONGESTION_GLBL_CONGSTN_FRST_LVL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_CONGESTION_GLBL_CONGSTN_SCND_LVL_FIELD;
+#define DSPTCHR_CONGESTION_GLBL_CONGSTN_SCND_LVL_FIELD_MASK  0x00fff000
+#define DSPTCHR_CONGESTION_GLBL_CONGSTN_SCND_LVL_FIELD_WIDTH 12
+#define DSPTCHR_CONGESTION_GLBL_CONGSTN_SCND_LVL_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_CONGESTION_GLBL_CONGSTN_HYST_THRS_FIELD;
+#define DSPTCHR_CONGESTION_GLBL_CONGSTN_HYST_THRS_FIELD_MASK  0xff000000
+#define DSPTCHR_CONGESTION_GLBL_CONGSTN_HYST_THRS_FIELD_WIDTH 8
+#define DSPTCHR_CONGESTION_GLBL_CONGSTN_HYST_THRS_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_FIELD;
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_FIELD_MASK  0x00000003
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_FIELD_WIDTH 2
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED0_FIELD;
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED0_FIELD_MASK  0x000000fc
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED0_FIELD_WIDTH 6
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_FIELD;
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_FIELD_MASK  0x00000300
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_FIELD_WIDTH 2
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED1_FIELD;
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED1_FIELD_MASK  0x0000fc00
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED1_FIELD_WIDTH 6
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED1_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_FIELD;
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_FIELD_MASK  0x00030000
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_FIELD_WIDTH 2
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED2_FIELD;
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED2_FIELD_MASK  0x00fc0000
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED2_FIELD_WIDTH 6
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED2_FIELD_SHIFT 18
+
+extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_STCKY_FIELD;
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_STCKY_FIELD_MASK  0x03000000
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_STCKY_FIELD_WIDTH 2
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_STCKY_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_STCKY_FIELD;
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_STCKY_FIELD_MASK  0x0c000000
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_STCKY_FIELD_WIDTH 2
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_STCKY_FIELD_SHIFT 26
+
+extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_STCKY_FIELD;
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_STCKY_FIELD_MASK  0x30000000
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_STCKY_FIELD_WIDTH 2
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_STCKY_FIELD_SHIFT 28
+
+extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED3_FIELD;
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED3_FIELD_MASK  0xc0000000
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED3_FIELD_WIDTH 2
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED3_FIELD_SHIFT 30
+
+extern const ru_field_rec DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD;
+#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_MASK  0xffffffff
+#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_WIDTH 32
+#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD;
+#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_MASK  0xffffffff
+#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_WIDTH 32
+#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD;
+#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_MASK  0xffffffff
+#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_WIDTH 32
+#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD;
+#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_MASK  0xffffffff
+#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_WIDTH 32
+#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_FIELD;
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_FIELD_MASK  0x000003ff
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_FIELD_WIDTH 10
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_RESERVED0_FIELD;
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_FIELD;
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_FIELD_MASK  0x000003ff
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_FIELD_WIDTH 10
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_FIELD;
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_FIELD_MASK  0x000ffc00
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_FIELD_WIDTH 10
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_FIELD;
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_FIELD_MASK  0xfff00000
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_FIELD_WIDTH 12
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_FIELD_SHIFT 20
+
+extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_FIELD;
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_FIELD_MASK  0x000003ff
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_FIELD_WIDTH 10
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_EN_FIELD;
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_EN_FIELD_MASK  0x00000400
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_EN_FIELD_WIDTH 1
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_EN_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_FIELD;
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_FIELD_MASK  0xfffff800
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_FIELD_WIDTH 21
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_FIELD_SHIFT 11
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_CRDT_CFG_BB_ID_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_BB_ID_FIELD_MASK  0x000000ff
+#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_BB_ID_FIELD_WIDTH 8
+#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_BB_ID_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_CRDT_CFG_RESERVED0_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_RESERVED0_FIELD_MASK  0x0000ff00
+#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_RESERVED0_FIELD_WIDTH 8
+#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_FIELD_MASK  0xffff0000
+#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_FIELD_WIDTH 16
+#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_FIELD_MASK  0x0000ffff
+#define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_FIELD_WIDTH 16
+#define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_FIELD_MASK  0xffff0000
+#define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_FIELD_WIDTH 16
+#define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q0_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q0_FIELD_MASK  0x00000001
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q0_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q1_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q1_FIELD_MASK  0x00000002
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q1_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q2_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q2_FIELD_MASK  0x00000004
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q2_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q2_FIELD_SHIFT 2
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q3_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q3_FIELD_MASK  0x00000008
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q3_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q3_FIELD_SHIFT 3
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q4_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q4_FIELD_MASK  0x00000010
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q4_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q4_FIELD_SHIFT 4
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q5_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q5_FIELD_MASK  0x00000020
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q5_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q5_FIELD_SHIFT 5
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q6_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q6_FIELD_MASK  0x00000040
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q6_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q6_FIELD_SHIFT 6
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q7_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q7_FIELD_MASK  0x00000080
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q7_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q7_FIELD_SHIFT 7
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q8_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q8_FIELD_MASK  0x00000100
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q8_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q8_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q9_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q9_FIELD_MASK  0x00000200
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q9_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q9_FIELD_SHIFT 9
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q10_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q10_FIELD_MASK  0x00000400
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q10_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q10_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q11_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q11_FIELD_MASK  0x00000800
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q11_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q11_FIELD_SHIFT 11
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q12_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q12_FIELD_MASK  0x00001000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q12_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q12_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q13_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q13_FIELD_MASK  0x00002000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q13_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q13_FIELD_SHIFT 13
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q14_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q14_FIELD_MASK  0x00004000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q14_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q14_FIELD_SHIFT 14
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q15_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q15_FIELD_MASK  0x00008000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q15_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q15_FIELD_SHIFT 15
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q16_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q16_FIELD_MASK  0x00010000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q16_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q16_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q17_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q17_FIELD_MASK  0x00020000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q17_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q17_FIELD_SHIFT 17
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q18_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q18_FIELD_MASK  0x00040000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q18_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q18_FIELD_SHIFT 18
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q19_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q19_FIELD_MASK  0x00080000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q19_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q19_FIELD_SHIFT 19
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q20_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q20_FIELD_MASK  0x00100000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q20_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q20_FIELD_SHIFT 20
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q21_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q21_FIELD_MASK  0x00200000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q21_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q21_FIELD_SHIFT 21
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q22_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q22_FIELD_MASK  0x00400000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q22_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q22_FIELD_SHIFT 22
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q23_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q23_FIELD_MASK  0x00800000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q23_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q23_FIELD_SHIFT 23
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q24_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q24_FIELD_MASK  0x01000000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q24_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q24_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q25_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q25_FIELD_MASK  0x02000000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q25_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q25_FIELD_SHIFT 25
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q26_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q26_FIELD_MASK  0x04000000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q26_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q26_FIELD_SHIFT 26
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q27_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q27_FIELD_MASK  0x08000000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q27_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q27_FIELD_SHIFT 27
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q28_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q28_FIELD_MASK  0x10000000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q28_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q28_FIELD_SHIFT 28
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q29_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q29_FIELD_MASK  0x20000000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q29_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q29_FIELD_SHIFT 29
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q30_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q30_FIELD_MASK  0x40000000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q30_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q30_FIELD_SHIFT 30
+
+extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q31_FIELD;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q31_FIELD_MASK  0x80000000
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q31_FIELD_WIDTH 1
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q31_FIELD_SHIFT 31
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_CMN_POOL_LMT_POOL_LMT_FIELD;
+#define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_POOL_LMT_FIELD_MASK  0x000003ff
+#define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_POOL_LMT_FIELD_WIDTH 10
+#define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_POOL_LMT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_CMN_POOL_LMT_RESERVED0_FIELD;
+#define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_FIELD;
+#define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_FIELD_MASK  0x000003ff
+#define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_FIELD_WIDTH 10
+#define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_RESERVED0_FIELD;
+#define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_FIELD;
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_FIELD_MASK  0x000003ff
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_FIELD_WIDTH 10
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_RESERVED0_FIELD;
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_FIELD;
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_FIELD_MASK  0x000003ff
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_FIELD_WIDTH 10
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_RESERVED0_FIELD;
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_FIELD;
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_FIELD_MASK  0x000003ff
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_FIELD_WIDTH 10
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_RESERVED0_FIELD;
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_FIELD;
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_FIELD_MASK  0x000003ff
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_FIELD_WIDTH 10
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_RESERVED0_FIELD;
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_RNR_POOL_LMT_POOL_LMT_FIELD;
+#define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_POOL_LMT_FIELD_MASK  0x000003ff
+#define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_POOL_LMT_FIELD_WIDTH 10
+#define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_POOL_LMT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_RNR_POOL_LMT_RESERVED0_FIELD;
+#define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_FIELD;
+#define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_FIELD_MASK  0x000003ff
+#define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_FIELD_WIDTH 10
+#define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_RESERVED0_FIELD;
+#define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_FIELD;
+#define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_FIELD_MASK  0x000003ff
+#define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_FIELD_WIDTH 10
+#define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_RESERVED0_FIELD;
+#define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_MASK_MSK_TSK_255_0_MASK_FIELD;
+#define DSPTCHR_MASK_MSK_TSK_255_0_MASK_FIELD_MASK  0xffffffff
+#define DSPTCHR_MASK_MSK_TSK_255_0_MASK_FIELD_WIDTH 32
+#define DSPTCHR_MASK_MSK_TSK_255_0_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_MASK_MSK_Q_MASK_FIELD;
+#define DSPTCHR_MASK_MSK_Q_MASK_FIELD_MASK  0xffffffff
+#define DSPTCHR_MASK_MSK_Q_MASK_FIELD_WIDTH 32
+#define DSPTCHR_MASK_MSK_Q_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_MASK_DLY_Q_MASK_FIELD;
+#define DSPTCHR_MASK_DLY_Q_MASK_FIELD_MASK  0xffffffff
+#define DSPTCHR_MASK_DLY_Q_MASK_FIELD_WIDTH 32
+#define DSPTCHR_MASK_DLY_Q_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_MASK_NON_DLY_Q_MASK_FIELD;
+#define DSPTCHR_MASK_NON_DLY_Q_MASK_FIELD_MASK  0xffffffff
+#define DSPTCHR_MASK_NON_DLY_Q_MASK_FIELD_WIDTH 32
+#define DSPTCHR_MASK_NON_DLY_Q_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_FIELD;
+#define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_FIELD_MASK  0x000000ff
+#define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_FIELD_WIDTH 8
+#define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_RESERVED0_FIELD;
+#define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_RESERVED0_FIELD_MASK  0xffffff00
+#define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_RESERVED0_FIELD_WIDTH 24
+#define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_FIELD;
+#define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_FIELD_MASK  0x000000ff
+#define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_FIELD_WIDTH 8
+#define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_RESERVED0_FIELD;
+#define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_RESERVED0_FIELD_MASK  0xffffff00
+#define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_RESERVED0_FIELD_WIDTH 24
+#define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_FIELD;
+#define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_FIELD_MASK  0x000003ff
+#define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_FIELD_WIDTH 10
+#define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_RESERVED0_FIELD;
+#define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_FIELD;
+#define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_FIELD_MASK  0x000003ff
+#define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_FIELD_WIDTH 10
+#define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_RESERVED0_FIELD;
+#define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q0_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q0_FIELD_MASK  0x00000001
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q0_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q1_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q1_FIELD_MASK  0x00000002
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q1_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q2_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q2_FIELD_MASK  0x00000004
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q2_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q2_FIELD_SHIFT 2
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q3_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q3_FIELD_MASK  0x00000008
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q3_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q3_FIELD_SHIFT 3
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q4_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q4_FIELD_MASK  0x00000010
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q4_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q4_FIELD_SHIFT 4
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q5_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q5_FIELD_MASK  0x00000020
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q5_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q5_FIELD_SHIFT 5
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q6_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q6_FIELD_MASK  0x00000040
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q6_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q6_FIELD_SHIFT 6
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q7_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q7_FIELD_MASK  0x00000080
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q7_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q7_FIELD_SHIFT 7
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q8_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q8_FIELD_MASK  0x00000100
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q8_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q8_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q9_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q9_FIELD_MASK  0x00000200
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q9_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q9_FIELD_SHIFT 9
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q10_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q10_FIELD_MASK  0x00000400
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q10_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q10_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q11_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q11_FIELD_MASK  0x00000800
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q11_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q11_FIELD_SHIFT 11
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q12_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q12_FIELD_MASK  0x00001000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q12_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q12_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q13_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q13_FIELD_MASK  0x00002000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q13_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q13_FIELD_SHIFT 13
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q14_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q14_FIELD_MASK  0x00004000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q14_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q14_FIELD_SHIFT 14
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q15_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q15_FIELD_MASK  0x00008000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q15_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q15_FIELD_SHIFT 15
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q16_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q16_FIELD_MASK  0x00010000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q16_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q16_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q17_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q17_FIELD_MASK  0x00020000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q17_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q17_FIELD_SHIFT 17
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q18_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q18_FIELD_MASK  0x00040000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q18_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q18_FIELD_SHIFT 18
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q19_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q19_FIELD_MASK  0x00080000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q19_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q19_FIELD_SHIFT 19
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q20_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q20_FIELD_MASK  0x00100000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q20_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q20_FIELD_SHIFT 20
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q21_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q21_FIELD_MASK  0x00200000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q21_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q21_FIELD_SHIFT 21
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q22_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q22_FIELD_MASK  0x00400000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q22_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q22_FIELD_SHIFT 22
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q23_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q23_FIELD_MASK  0x00800000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q23_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q23_FIELD_SHIFT 23
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q24_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q24_FIELD_MASK  0x01000000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q24_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q24_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q25_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q25_FIELD_MASK  0x02000000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q25_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q25_FIELD_SHIFT 25
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q26_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q26_FIELD_MASK  0x04000000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q26_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q26_FIELD_SHIFT 26
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q27_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q27_FIELD_MASK  0x08000000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q27_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q27_FIELD_SHIFT 27
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q28_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q28_FIELD_MASK  0x10000000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q28_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q28_FIELD_SHIFT 28
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q29_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q29_FIELD_MASK  0x20000000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q29_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q29_FIELD_SHIFT 29
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q30_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q30_FIELD_MASK  0x40000000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q30_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q30_FIELD_SHIFT 30
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q31_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q31_FIELD_MASK  0x80000000
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q31_FIELD_WIDTH 1
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q31_FIELD_SHIFT 31
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_FIELD_MASK  0x000003ff
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_FIELD_WIDTH 10
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_RESERVED0_FIELD;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_FIELD_MASK  0x000fffff
+#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_FIELD_WIDTH 20
+#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_NGTV_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_NGTV_FIELD_MASK  0x00100000
+#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_NGTV_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_NGTV_FIELD_SHIFT 20
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_FIELD_MASK  0xffe00000
+#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_FIELD_WIDTH 11
+#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_FIELD_SHIFT 21
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q0_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q0_FIELD_MASK  0x00000001
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q0_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q1_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q1_FIELD_MASK  0x00000002
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q1_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q2_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q2_FIELD_MASK  0x00000004
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q2_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q2_FIELD_SHIFT 2
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q3_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q3_FIELD_MASK  0x00000008
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q3_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q3_FIELD_SHIFT 3
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q4_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q4_FIELD_MASK  0x00000010
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q4_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q4_FIELD_SHIFT 4
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q5_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q5_FIELD_MASK  0x00000020
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q5_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q5_FIELD_SHIFT 5
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q6_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q6_FIELD_MASK  0x00000040
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q6_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q6_FIELD_SHIFT 6
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q7_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q7_FIELD_MASK  0x00000080
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q7_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q7_FIELD_SHIFT 7
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q8_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q8_FIELD_MASK  0x00000100
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q8_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q8_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q9_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q9_FIELD_MASK  0x00000200
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q9_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q9_FIELD_SHIFT 9
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q10_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q10_FIELD_MASK  0x00000400
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q10_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q10_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q11_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q11_FIELD_MASK  0x00000800
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q11_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q11_FIELD_SHIFT 11
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q12_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q12_FIELD_MASK  0x00001000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q12_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q12_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q13_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q13_FIELD_MASK  0x00002000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q13_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q13_FIELD_SHIFT 13
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q14_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q14_FIELD_MASK  0x00004000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q14_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q14_FIELD_SHIFT 14
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q15_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q15_FIELD_MASK  0x00008000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q15_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q15_FIELD_SHIFT 15
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q16_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q16_FIELD_MASK  0x00010000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q16_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q16_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q17_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q17_FIELD_MASK  0x00020000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q17_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q17_FIELD_SHIFT 17
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q18_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q18_FIELD_MASK  0x00040000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q18_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q18_FIELD_SHIFT 18
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q19_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q19_FIELD_MASK  0x00080000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q19_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q19_FIELD_SHIFT 19
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q20_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q20_FIELD_MASK  0x00100000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q20_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q20_FIELD_SHIFT 20
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q21_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q21_FIELD_MASK  0x00200000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q21_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q21_FIELD_SHIFT 21
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q22_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q22_FIELD_MASK  0x00400000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q22_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q22_FIELD_SHIFT 22
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q23_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q23_FIELD_MASK  0x00800000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q23_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q23_FIELD_SHIFT 23
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q24_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q24_FIELD_MASK  0x01000000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q24_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q24_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q25_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q25_FIELD_MASK  0x02000000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q25_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q25_FIELD_SHIFT 25
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q26_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q26_FIELD_MASK  0x04000000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q26_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q26_FIELD_SHIFT 26
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q27_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q27_FIELD_MASK  0x08000000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q27_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q27_FIELD_SHIFT 27
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q28_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q28_FIELD_MASK  0x10000000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q28_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q28_FIELD_SHIFT 28
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q29_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q29_FIELD_MASK  0x20000000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q29_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q29_FIELD_SHIFT 29
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q30_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q30_FIELD_MASK  0x40000000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q30_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q30_FIELD_SHIFT 30
+
+extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q31_FIELD;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q31_FIELD_MASK  0x80000000
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q31_FIELD_WIDTH 1
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q31_FIELD_SHIFT 31
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_LB_CFG_LB_MODE_FIELD;
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_LB_MODE_FIELD_MASK  0x00000001
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_LB_MODE_FIELD_WIDTH 1
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_LB_MODE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED0_FIELD;
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED0_FIELD_MASK  0x000000fe
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED0_FIELD_WIDTH 7
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_LB_CFG_SP_THRSHLD_FIELD;
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_SP_THRSHLD_FIELD_MASK  0x00001f00
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_SP_THRSHLD_FIELD_WIDTH 5
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_SP_THRSHLD_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED1_FIELD;
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED1_FIELD_MASK  0xffffe000
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED1_FIELD_WIDTH 19
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR0_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR0_FIELD_MASK  0x0000ffff
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR0_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR0_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR1_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR1_FIELD_MASK  0xffff0000
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR1_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR1_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR2_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR2_FIELD_MASK  0x0000ffff
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR2_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR2_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR3_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR3_FIELD_MASK  0xffff0000
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR3_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR3_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR4_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR4_FIELD_MASK  0x0000ffff
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR4_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR4_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR5_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR5_FIELD_MASK  0xffff0000
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR5_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR5_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR6_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR6_FIELD_MASK  0x0000ffff
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR6_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR6_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR7_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR7_FIELD_MASK  0xffff0000
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR7_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR7_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR8_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR8_FIELD_MASK  0x0000ffff
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR8_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR8_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR9_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR9_FIELD_MASK  0xffff0000
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR9_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR9_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR10_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR10_FIELD_MASK  0x0000ffff
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR10_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR10_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR11_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR11_FIELD_MASK  0xffff0000
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR11_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR11_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR12_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR12_FIELD_MASK  0x0000ffff
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR12_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR12_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR13_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR13_FIELD_MASK  0xffff0000
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR13_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR13_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR14_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR14_FIELD_MASK  0x0000ffff
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR14_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR14_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR15_FIELD;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR15_FIELD_MASK  0xffff0000
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR15_FIELD_WIDTH 16
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR15_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_FIELD;
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_FIELD_MASK  0x00000007
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_FIELD_WIDTH 3
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_FIELD;
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_FIELD_MASK  0x00000038
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_FIELD_WIDTH 3
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_FIELD_SHIFT 3
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_FIELD;
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_FIELD_MASK  0x000001c0
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_FIELD_WIDTH 3
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_FIELD_SHIFT 6
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_FIELD;
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_FIELD_MASK  0x00000e00
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_FIELD_WIDTH 3
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_FIELD_SHIFT 9
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_FIELD;
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_FIELD_MASK  0x00007000
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_FIELD_WIDTH 3
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_FIELD;
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_FIELD_MASK  0x00038000
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_FIELD_WIDTH 3
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_FIELD_SHIFT 15
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_FIELD;
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_FIELD_MASK  0x001c0000
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_FIELD_WIDTH 3
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_FIELD_SHIFT 18
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_FIELD;
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_FIELD_MASK  0x00e00000
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_FIELD_WIDTH 3
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_FIELD_SHIFT 21
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_RESERVED0_FIELD;
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_RESERVED0_FIELD_MASK  0xff000000
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_RESERVED0_FIELD_WIDTH 8
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_FIELD;
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_FIELD_MASK  0x000000ff
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_FIELD_WIDTH 8
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_FIELD;
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_FIELD_MASK  0x0000ff00
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_FIELD_WIDTH 8
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_FIELD;
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_FIELD_MASK  0x00ff0000
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_FIELD_WIDTH 8
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_FIELD;
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_FIELD_MASK  0xff000000
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_FIELD_WIDTH 8
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_FIELD;
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_FIELD_MASK  0x000000ff
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_FIELD_WIDTH 8
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_FIELD;
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_FIELD_MASK  0x0000ff00
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_FIELD_WIDTH 8
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_FIELD;
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_FIELD_MASK  0x00ff0000
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_FIELD_WIDTH 8
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_FIELD;
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_FIELD_MASK  0xff000000
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_FIELD_WIDTH 8
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_RETURN_BUF_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_RETURN_BUF_FIELD_MASK  0x00000001
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_RETURN_BUF_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_RETURN_BUF_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_CNT_DRP_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_CNT_DRP_FIELD_MASK  0x00000002
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_CNT_DRP_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_CNT_DRP_FIELD_SHIFT 1
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_UNKNWN_MSG_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_UNKNWN_MSG_FIELD_MASK  0x00000004
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_UNKNWN_MSG_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_UNKNWN_MSG_FIELD_SHIFT 2
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_OVERFLOW_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_OVERFLOW_FIELD_MASK  0x00000008
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_OVERFLOW_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_OVERFLOW_FIELD_SHIFT 3
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_NEG_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_NEG_FIELD_MASK  0x00000010
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_NEG_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_NEG_FIELD_SHIFT 4
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_RESERVED0_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_RESERVED0_FIELD_MASK  0xffffffe0
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_RESERVED0_FIELD_WIDTH 27
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_FIELD_MASK  0xffffffff
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_FIELD_WIDTH 32
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_FIELD_MASK  0xffffffff
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_FIELD_WIDTH 32
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_FIELD_MASK  0xffffffff
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_FIELD_WIDTH 32
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST0_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST0_INT_FIELD_MASK  0x00000001
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST0_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST0_INT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST1_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST1_INT_FIELD_MASK  0x00000002
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST1_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST1_INT_FIELD_SHIFT 1
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST2_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST2_INT_FIELD_MASK  0x00000004
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST2_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST2_INT_FIELD_SHIFT 2
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST3_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST3_INT_FIELD_MASK  0x00000008
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST3_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST3_INT_FIELD_SHIFT 3
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST4_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST4_INT_FIELD_MASK  0x00000010
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST4_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST4_INT_FIELD_SHIFT 4
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST5_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST5_INT_FIELD_MASK  0x00000020
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST5_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST5_INT_FIELD_SHIFT 5
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST6_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST6_INT_FIELD_MASK  0x00000040
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST6_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST6_INT_FIELD_SHIFT 6
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST7_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST7_INT_FIELD_MASK  0x00000080
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST7_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST7_INT_FIELD_SHIFT 7
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST8_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST8_INT_FIELD_MASK  0x00000100
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST8_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST8_INT_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST9_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST9_INT_FIELD_MASK  0x00000200
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST9_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST9_INT_FIELD_SHIFT 9
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST10_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST10_INT_FIELD_MASK  0x00000400
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST10_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST10_INT_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST11_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST11_INT_FIELD_MASK  0x00000800
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST11_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST11_INT_FIELD_SHIFT 11
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST12_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST12_INT_FIELD_MASK  0x00001000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST12_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST12_INT_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST13_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST13_INT_FIELD_MASK  0x00002000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST13_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST13_INT_FIELD_SHIFT 13
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST14_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST14_INT_FIELD_MASK  0x00004000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST14_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST14_INT_FIELD_SHIFT 14
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST15_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST15_INT_FIELD_MASK  0x00008000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST15_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST15_INT_FIELD_SHIFT 15
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST16_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST16_INT_FIELD_MASK  0x00010000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST16_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST16_INT_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST17_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST17_INT_FIELD_MASK  0x00020000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST17_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST17_INT_FIELD_SHIFT 17
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST18_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST18_INT_FIELD_MASK  0x00040000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST18_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST18_INT_FIELD_SHIFT 18
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST19_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST19_INT_FIELD_MASK  0x00080000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST19_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST19_INT_FIELD_SHIFT 19
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST20_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST20_INT_FIELD_MASK  0x00100000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST20_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST20_INT_FIELD_SHIFT 20
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST21_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST21_INT_FIELD_MASK  0x00200000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST21_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST21_INT_FIELD_SHIFT 21
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST22_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST22_INT_FIELD_MASK  0x00400000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST22_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST22_INT_FIELD_SHIFT 22
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST23_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST23_INT_FIELD_MASK  0x00800000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST23_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST23_INT_FIELD_SHIFT 23
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST24_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST24_INT_FIELD_MASK  0x01000000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST24_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST24_INT_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST25_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST25_INT_FIELD_MASK  0x02000000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST25_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST25_INT_FIELD_SHIFT 25
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST26_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST26_INT_FIELD_MASK  0x04000000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST26_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST26_INT_FIELD_SHIFT 26
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST27_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST27_INT_FIELD_MASK  0x08000000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST27_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST27_INT_FIELD_SHIFT 27
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST28_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST28_INT_FIELD_MASK  0x10000000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST28_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST28_INT_FIELD_SHIFT 28
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST29_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST29_INT_FIELD_MASK  0x20000000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST29_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST29_INT_FIELD_SHIFT 29
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST30_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST30_INT_FIELD_MASK  0x40000000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST30_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST30_INT_FIELD_SHIFT 30
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST31_INT_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST31_INT_FIELD_MASK  0x80000000
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST31_INT_FIELD_WIDTH 1
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST31_INT_FIELD_SHIFT 31
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_FIELD_MASK  0xffffffff
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_FIELD_WIDTH 32
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_FIELD_MASK  0xffffffff
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_FIELD_WIDTH 32
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_FIELD;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_FIELD_MASK  0xffffffff
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_FIELD_WIDTH 32
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_EN_BYP_FIELD;
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_EN_BYP_FIELD_MASK  0x00000001
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_EN_BYP_FIELD_WIDTH 1
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_EN_BYP_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED0_FIELD;
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED0_FIELD_MASK  0x000000fe
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED0_FIELD_WIDTH 7
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_FIELD;
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_FIELD_MASK  0x0000ff00
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_FIELD_WIDTH 8
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_FIELD;
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_FIELD_MASK  0x00ff0000
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_FIELD_WIDTH 8
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED1_FIELD;
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED1_FIELD_MASK  0xff000000
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED1_FIELD_WIDTH 8
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED1_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_FIELD_MASK  0x0000000f
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_FIELD_MASK  0x000000f0
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_FIELD_SHIFT 4
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_FIELD_MASK  0x00000f00
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_FIELD_MASK  0x0000f000
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_FIELD_MASK  0x000f0000
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_FIELD_MASK  0x00f00000
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_FIELD_SHIFT 20
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_FIELD_MASK  0x0f000000
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_FIELD_MASK  0xf0000000
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_FIELD_SHIFT 28
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_FIELD_MASK  0x0000000f
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_FIELD_MASK  0x000000f0
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_FIELD_SHIFT 4
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_FIELD_MASK  0x00000f00
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_FIELD_MASK  0x0000f000
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_FIELD_MASK  0x000f0000
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_FIELD_MASK  0x00f00000
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_FIELD_SHIFT 20
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_FIELD_MASK  0x0f000000
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_FIELD_SHIFT 24
+
+extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_FIELD;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_FIELD_MASK  0xf0000000
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_FIELD_SHIFT 28
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_BUS_CNTRL_DBG_SEL_FIELD;
+#define DSPTCHR_DEBUG_DBG_BUS_CNTRL_DBG_SEL_FIELD_MASK  0x0000001f
+#define DSPTCHR_DEBUG_DBG_BUS_CNTRL_DBG_SEL_FIELD_WIDTH 5
+#define DSPTCHR_DEBUG_DBG_BUS_CNTRL_DBG_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_BUS_CNTRL_RESERVED0_FIELD;
+#define DSPTCHR_DEBUG_DBG_BUS_CNTRL_RESERVED0_FIELD_MASK  0xffffffe0
+#define DSPTCHR_DEBUG_DBG_BUS_CNTRL_RESERVED0_FIELD_WIDTH 27
+#define DSPTCHR_DEBUG_DBG_BUS_CNTRL_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_0_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_0_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_0_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_0_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_1_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_1_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_1_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_1_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_2_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_2_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_2_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_2_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_3_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_3_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_3_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_3_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_4_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_4_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_4_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_4_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_5_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_5_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_5_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_5_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_6_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_6_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_6_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_6_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_7_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_7_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_7_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_7_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_8_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_8_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_8_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_8_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_9_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_9_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_9_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_9_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_10_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_10_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_10_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_10_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_11_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_11_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_11_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_11_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_12_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_12_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_12_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_12_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_13_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_13_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_13_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_13_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_14_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_14_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_14_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_14_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_15_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_15_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_15_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_15_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_16_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_16_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_16_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_16_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_17_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_17_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_17_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_17_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_18_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_18_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_18_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_18_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_19_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_19_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_19_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_19_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_20_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_20_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_20_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_20_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_21_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_21_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_21_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_21_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_22_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_22_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_22_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_22_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_23_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_DBG_VEC_23_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_DBG_VEC_23_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_DBG_VEC_23_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_FIELD;
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_FIELD_MASK  0x00000003
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_FIELD_WIDTH 2
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED0_FIELD;
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED0_FIELD_MASK  0x000000fc
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED0_FIELD_WIDTH 6
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_EN_CNTRS_FIELD;
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_EN_CNTRS_FIELD_MASK  0x00000100
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_EN_CNTRS_FIELD_WIDTH 1
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_EN_CNTRS_FIELD_SHIFT 8
+
+extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_CLR_CNTRS_FIELD;
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_CLR_CNTRS_FIELD_MASK  0x00000200
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_CLR_CNTRS_FIELD_WIDTH 1
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_CLR_CNTRS_FIELD_SHIFT 9
+
+extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED1_FIELD;
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED1_FIELD_MASK  0x0000fc00
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED1_FIELD_WIDTH 6
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED1_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_FIELD;
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_FIELD_MASK  0x000f0000
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_FIELD_WIDTH 4
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_FIELD_SHIFT 16
+
+extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED2_FIELD;
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED2_FIELD_MASK  0xfff00000
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED2_FIELD_WIDTH 12
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED2_FIELD_SHIFT 20
+
+extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_FIELD;
+#define DSPTCHR_DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_FIELD_MASK  0xffffffff
+#define DSPTCHR_DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_FIELD_WIDTH 32
+#define DSPTCHR_DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_HEAD_HEAD_FIELD;
+#define DSPTCHR_QDES_HEAD_HEAD_FIELD_MASK  0xffffffff
+#define DSPTCHR_QDES_HEAD_HEAD_FIELD_WIDTH 32
+#define DSPTCHR_QDES_HEAD_HEAD_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_BFOUT_BFOUT_FIELD;
+#define DSPTCHR_QDES_BFOUT_BFOUT_FIELD_MASK  0xffffffff
+#define DSPTCHR_QDES_BFOUT_BFOUT_FIELD_WIDTH 32
+#define DSPTCHR_QDES_BFOUT_BFOUT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_BUFIN_BUFIN_FIELD;
+#define DSPTCHR_QDES_BUFIN_BUFIN_FIELD_MASK  0xffffffff
+#define DSPTCHR_QDES_BUFIN_BUFIN_FIELD_WIDTH 32
+#define DSPTCHR_QDES_BUFIN_BUFIN_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_TAIL_TAIL_FIELD;
+#define DSPTCHR_QDES_TAIL_TAIL_FIELD_MASK  0xffffffff
+#define DSPTCHR_QDES_TAIL_TAIL_FIELD_WIDTH 32
+#define DSPTCHR_QDES_TAIL_TAIL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_FBDNULL_FBDNULL_FIELD;
+#define DSPTCHR_QDES_FBDNULL_FBDNULL_FIELD_MASK  0x00000001
+#define DSPTCHR_QDES_FBDNULL_FBDNULL_FIELD_WIDTH 1
+#define DSPTCHR_QDES_FBDNULL_FBDNULL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_FBDNULL_RESERVED0_FIELD;
+#define DSPTCHR_QDES_FBDNULL_RESERVED0_FIELD_MASK  0xfffffffe
+#define DSPTCHR_QDES_FBDNULL_RESERVED0_FIELD_WIDTH 31
+#define DSPTCHR_QDES_FBDNULL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec DSPTCHR_QDES_NULLBD_NULLBD_FIELD;
+#define DSPTCHR_QDES_NULLBD_NULLBD_FIELD_MASK  0xffffffff
+#define DSPTCHR_QDES_NULLBD_NULLBD_FIELD_WIDTH 32
+#define DSPTCHR_QDES_NULLBD_NULLBD_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_BUFAVAIL_BUFAVAIL_FIELD;
+#define DSPTCHR_QDES_BUFAVAIL_BUFAVAIL_FIELD_MASK  0xffffffff
+#define DSPTCHR_QDES_BUFAVAIL_BUFAVAIL_FIELD_WIDTH 32
+#define DSPTCHR_QDES_BUFAVAIL_BUFAVAIL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_REG_Q_HEAD_HEAD_FIELD;
+#define DSPTCHR_QDES_REG_Q_HEAD_HEAD_FIELD_MASK  0x000003ff
+#define DSPTCHR_QDES_REG_Q_HEAD_HEAD_FIELD_WIDTH 10
+#define DSPTCHR_QDES_REG_Q_HEAD_HEAD_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_REG_Q_HEAD_RESERVED0_FIELD;
+#define DSPTCHR_QDES_REG_Q_HEAD_RESERVED0_FIELD_MASK  0xfffffc00
+#define DSPTCHR_QDES_REG_Q_HEAD_RESERVED0_FIELD_WIDTH 22
+#define DSPTCHR_QDES_REG_Q_HEAD_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DSPTCHR_QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD;
+#define DSPTCHR_QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_MASK  0xffffffff
+#define DSPTCHR_QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_WIDTH 32
+#define DSPTCHR_QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_FIELD;
+#define DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_FIELD_MASK  0xffffffff
+#define DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_FIELD_WIDTH 32
+#define DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD;
+#define DSPTCHR_QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_MASK  0xffffffff
+#define DSPTCHR_QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_WIDTH 32
+#define DSPTCHR_QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_USE_BUF_AVL_FIELD;
+#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_USE_BUF_AVL_FIELD_MASK  0x00000001
+#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_USE_BUF_AVL_FIELD_WIDTH 1
+#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_USE_BUF_AVL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_DEC_BUFOUT_WHEN_MLTCST_FIELD;
+#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_DEC_BUFOUT_WHEN_MLTCST_FIELD_MASK  0x00000002
+#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_DEC_BUFOUT_WHEN_MLTCST_FIELD_WIDTH 1
+#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_DEC_BUFOUT_WHEN_MLTCST_FIELD_SHIFT 1
+
+extern const ru_field_rec DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_RESERVED0_FIELD;
+#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_RESERVED0_FIELD_MASK  0xfffffffc
+#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_RESERVED0_FIELD_WIDTH 30
+#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec DSPTCHR_FLLDES_HEAD_HEAD_FIELD;
+#define DSPTCHR_FLLDES_HEAD_HEAD_FIELD_MASK  0xffffffff
+#define DSPTCHR_FLLDES_HEAD_HEAD_FIELD_WIDTH 32
+#define DSPTCHR_FLLDES_HEAD_HEAD_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_FLLDES_BFOUT_COUNT_FIELD;
+#define DSPTCHR_FLLDES_BFOUT_COUNT_FIELD_MASK  0xffffffff
+#define DSPTCHR_FLLDES_BFOUT_COUNT_FIELD_WIDTH 32
+#define DSPTCHR_FLLDES_BFOUT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_FLLDES_BFIN_BFIN_FIELD;
+#define DSPTCHR_FLLDES_BFIN_BFIN_FIELD_MASK  0xffffffff
+#define DSPTCHR_FLLDES_BFIN_BFIN_FIELD_WIDTH 32
+#define DSPTCHR_FLLDES_BFIN_BFIN_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_FLLDES_TAIL_TAIL_FIELD;
+#define DSPTCHR_FLLDES_TAIL_TAIL_FIELD_MASK  0xffffffff
+#define DSPTCHR_FLLDES_TAIL_TAIL_FIELD_WIDTH 32
+#define DSPTCHR_FLLDES_TAIL_TAIL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_FLLDES_FLLDROP_DRPCNT_FIELD;
+#define DSPTCHR_FLLDES_FLLDROP_DRPCNT_FIELD_MASK  0xffffffff
+#define DSPTCHR_FLLDES_FLLDROP_DRPCNT_FIELD_WIDTH 32
+#define DSPTCHR_FLLDES_FLLDROP_DRPCNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_FLLDES_LTINT_MINBUF_FIELD;
+#define DSPTCHR_FLLDES_LTINT_MINBUF_FIELD_MASK  0xffffffff
+#define DSPTCHR_FLLDES_LTINT_MINBUF_FIELD_WIDTH 32
+#define DSPTCHR_FLLDES_LTINT_MINBUF_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_FLLDES_BUFAVAIL_BUFAVAIL_FIELD;
+#define DSPTCHR_FLLDES_BUFAVAIL_BUFAVAIL_FIELD_MASK  0xffffffff
+#define DSPTCHR_FLLDES_BUFAVAIL_BUFAVAIL_FIELD_WIDTH 32
+#define DSPTCHR_FLLDES_BUFAVAIL_BUFAVAIL_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_FLLDES_FREEMIN_FREEMIN_FIELD;
+#define DSPTCHR_FLLDES_FREEMIN_FREEMIN_FIELD_MASK  0xffffffff
+#define DSPTCHR_FLLDES_FREEMIN_FREEMIN_FIELD_WIDTH 32
+#define DSPTCHR_FLLDES_FREEMIN_FREEMIN_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_BDRAM_NEXT_DATA_RESERVED0_FIELD;
+#define DSPTCHR_BDRAM_NEXT_DATA_RESERVED0_FIELD_MASK  0x00000003
+#define DSPTCHR_BDRAM_NEXT_DATA_RESERVED0_FIELD_WIDTH 2
+#define DSPTCHR_BDRAM_NEXT_DATA_RESERVED0_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_BDRAM_NEXT_DATA_DATA_FIELD;
+#define DSPTCHR_BDRAM_NEXT_DATA_DATA_FIELD_MASK  0x00000ffc
+#define DSPTCHR_BDRAM_NEXT_DATA_DATA_FIELD_WIDTH 10
+#define DSPTCHR_BDRAM_NEXT_DATA_DATA_FIELD_SHIFT 2
+
+extern const ru_field_rec DSPTCHR_BDRAM_NEXT_DATA_RESERVED1_FIELD;
+#define DSPTCHR_BDRAM_NEXT_DATA_RESERVED1_FIELD_MASK  0xfffff000
+#define DSPTCHR_BDRAM_NEXT_DATA_RESERVED1_FIELD_WIDTH 20
+#define DSPTCHR_BDRAM_NEXT_DATA_RESERVED1_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_BDRAM_PREV_DATA_RESERVED0_FIELD;
+#define DSPTCHR_BDRAM_PREV_DATA_RESERVED0_FIELD_MASK  0x00000003
+#define DSPTCHR_BDRAM_PREV_DATA_RESERVED0_FIELD_WIDTH 2
+#define DSPTCHR_BDRAM_PREV_DATA_RESERVED0_FIELD_SHIFT 0
+
+extern const ru_field_rec DSPTCHR_BDRAM_PREV_DATA_DATA_FIELD;
+#define DSPTCHR_BDRAM_PREV_DATA_DATA_FIELD_MASK  0x00000ffc
+#define DSPTCHR_BDRAM_PREV_DATA_DATA_FIELD_WIDTH 10
+#define DSPTCHR_BDRAM_PREV_DATA_DATA_FIELD_SHIFT 2
+
+extern const ru_field_rec DSPTCHR_BDRAM_PREV_DATA_RESERVED1_FIELD;
+#define DSPTCHR_BDRAM_PREV_DATA_RESERVED1_FIELD_MASK  0xfffff000
+#define DSPTCHR_BDRAM_PREV_DATA_RESERVED1_FIELD_WIDTH 20
+#define DSPTCHR_BDRAM_PREV_DATA_RESERVED1_FIELD_SHIFT 12
+
+extern const ru_field_rec DSPTCHR_PDRAM_DATA_DATA_FIELD;
+#define DSPTCHR_PDRAM_DATA_DATA_FIELD_MASK  0xffffffff
+#define DSPTCHR_PDRAM_DATA_DATA_FIELD_WIDTH 32
+#define DSPTCHR_PDRAM_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD_MASK  0x00000007
+#define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD_WIDTH 3
+#define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD_MASK  0xfffffff8
+#define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD_WIDTH 29
+#define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD_MASK  0x0000003f
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD_MASK  0x000000c0
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD_WIDTH 2
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD_MASK  0x00003f00
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD_MASK  0x0000c000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD_WIDTH 2
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD_MASK  0x003f0000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD_MASK  0x00c00000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD_WIDTH 2
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD_SHIFT 22
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD_MASK  0x3f000000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD_MASK  0xc0000000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD_WIDTH 2
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD_SHIFT 30
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD_MASK  0x0000003f
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD_MASK  0x000000c0
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD_WIDTH 2
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD_MASK  0x00003f00
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD_MASK  0x0000c000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD_WIDTH 2
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD_MASK  0x003f0000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD_MASK  0x00c00000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD_WIDTH 2
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD_SHIFT 22
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD_MASK  0x3f000000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD_MASK  0xc0000000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD_WIDTH 2
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD_SHIFT 30
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD_MASK  0x00000007
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD_WIDTH 3
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD_MASK  0x00000008
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD_MASK  0x00001ff0
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD_WIDTH 9
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD_MASK  0x0000e000
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD_WIDTH 3
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD_MASK  0x007f0000
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD_WIDTH 7
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD_MASK  0x00800000
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD_SHIFT 23
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD_MASK  0x7f000000
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD_WIDTH 7
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD_MASK  0x80000000
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD_SHIFT 31
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD_MASK  0x0000ffff
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD_WIDTH 16
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD_MASK  0xffff0000
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD_WIDTH 16
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD_MASK  0x0000ffff
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD_WIDTH 16
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD_MASK  0x000f0000
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD_WIDTH 4
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD_MASK  0xfff00000
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD_WIDTH 12
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD_SHIFT 20
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD_MASK  0x0000003f
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD_MASK  0x00000fc0
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD_MASK  0x0000f000
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD_WIDTH 4
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD_MASK  0x003f0000
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD_MASK  0x00c00000
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD_WIDTH 2
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD_SHIFT 22
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD_MASK  0x01000000
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_JUMBOURGNT_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_JUMBOURGNT_FIELD_MASK  0x02000000
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_JUMBOURGNT_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_JUMBOURGNT_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD_MASK  0xfc000000
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD_SHIFT 26
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD_MASK  0x0000003f
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD_MASK  0x00000fc0
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD_MASK  0x0000f000
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD_WIDTH 4
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD_MASK  0x003f0000
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD_MASK  0x00c00000
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD_WIDTH 2
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD_SHIFT 22
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD_MASK  0x01000000
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_JUMBOURGNT_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_JUMBOURGNT_FIELD_MASK  0x02000000
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_JUMBOURGNT_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_JUMBOURGNT_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD_MASK  0xfc000000
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD_SHIFT 26
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD_MASK  0x00000001
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD_MASK  0x00000002
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD_MASK  0x000000fc
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD_MASK  0x00001f00
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD_WIDTH 5
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD_MASK  0xffffe000
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD_WIDTH 19
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD_MASK  0xffffffff
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD_WIDTH 32
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD_MASK  0x000000ff
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD_WIDTH 8
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD_MASK  0xffffff00
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD_WIDTH 24
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD_MASK  0x000003ff
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD_WIDTH 10
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD_MASK  0x000ffc00
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD_WIDTH 10
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD_SHIFT 10
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD_MASK  0x3ff00000
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD_WIDTH 10
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD_SHIFT 20
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD_MASK  0xc0000000
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD_WIDTH 2
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD_MASK  0x00000001
+#define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD_MASK  0xfffffffe
+#define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD_WIDTH 31
+#define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD_MASK  0x000003ff
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD_WIDTH 10
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD_MASK  0x0000fc00
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD_WIDTH 6
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD_SHIFT 10
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD_MASK  0x00010000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD_MASK  0xfffe0000
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD_WIDTH 15
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK0_FIELD_MASK  0x0000000f
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK0_FIELD_WIDTH 4
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK1_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK1_FIELD_MASK  0x000000f0
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK1_FIELD_WIDTH 4
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK1_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK2_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK2_FIELD_MASK  0x00000f00
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK2_FIELD_WIDTH 4
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK2_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK3_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK3_FIELD_MASK  0x0000f000
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK3_FIELD_WIDTH 4
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK3_FIELD_SHIFT 12
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK4_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK4_FIELD_MASK  0x000f0000
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK4_FIELD_WIDTH 4
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK4_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK5_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK5_FIELD_MASK  0x00f00000
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK5_FIELD_WIDTH 4
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK5_FIELD_SHIFT 20
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK6_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK6_FIELD_MASK  0x0f000000
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK6_FIELD_WIDTH 4
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK6_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK7_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK7_FIELD_MASK  0xf0000000
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK7_FIELD_WIDTH 4
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK7_FIELD_SHIFT 28
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD_MASK  0x00000001
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD_MASK  0x00000002
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD_MASK  0x00000004
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD_MASK  0x00000008
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD_MASK  0x00000010
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD_MASK  0x00000020
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD_SHIFT 5
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD_MASK  0x00000040
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD_MASK  0x00000080
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD_SHIFT 7
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD_MASK  0x00000100
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD_MASK  0x00000200
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD_MASK  0x00000400
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD_SHIFT 10
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD_MASK  0x00000800
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD_SHIFT 11
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD_MASK  0x00001000
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD_SHIFT 12
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD_MASK  0x00002000
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD_SHIFT 13
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD_MASK  0x00004000
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD_SHIFT 14
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD_MASK  0xffff8000
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD_WIDTH 17
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD_SHIFT 15
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD_MASK  0x0000001f
+#define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD_WIDTH 5
+#define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD_MASK  0xffffffe0
+#define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD_WIDTH 27
+#define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK  0x00000001
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK  0x000000fe
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK  0x0000ff00
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK  0x00010000
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK  0x000e0000
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK  0x00700000
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK  0x00800000
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK  0xff000000
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_GPR_GPR_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_GPR_GPR_FIELD_MASK  0xffffffff
+#define BBH_TX_COMMON_CONFIGURATIONS_GPR_GPR_FIELD_WIDTH 32
+#define BBH_TX_COMMON_CONFIGURATIONS_GPR_GPR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DS_DMA_SUP_DSDMA_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DS_DMA_SUP_DSDMA_FIELD_MASK  0x00000001
+#define BBH_TX_COMMON_CONFIGURATIONS_DS_DMA_SUP_DSDMA_FIELD_WIDTH 1
+#define BBH_TX_COMMON_CONFIGURATIONS_DS_DMA_SUP_DSDMA_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DS_DMA_SUP_RESERVED0_FIELD;
+#define BBH_TX_COMMON_CONFIGURATIONS_DS_DMA_SUP_RESERVED0_FIELD_MASK  0xfffffffe
+#define BBH_TX_COMMON_CONFIGURATIONS_DS_DMA_SUP_RESERVED0_FIELD_WIDTH 31
+#define BBH_TX_COMMON_CONFIGURATIONS_DS_DMA_SUP_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_Q2RNR_Q0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_Q2RNR_Q0_FIELD_MASK  0x00000001
+#define BBH_TX_WAN_CONFIGURATIONS_Q2RNR_Q0_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_Q2RNR_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_Q2RNR_Q1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_Q2RNR_Q1_FIELD_MASK  0x00000002
+#define BBH_TX_WAN_CONFIGURATIONS_Q2RNR_Q1_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_Q2RNR_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_MASK  0xfffffffc
+#define BBH_TX_WAN_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_WIDTH 30
+#define BBH_TX_WAN_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_QPROF_Q0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_Q0_FIELD_MASK  0x00000001
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_Q0_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_QPROF_Q1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_Q1_FIELD_MASK  0x00000002
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_Q1_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_QPROF_DIS0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_DIS0_FIELD_MASK  0x00000004
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_DIS0_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_DIS0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_QPROF_DIS1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_DIS1_FIELD_MASK  0x00000008
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_DIS1_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_DIS1_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_QPROF_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_RESERVED0_FIELD_MASK  0xfffffff0
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_RESERVED0_FIELD_WIDTH 28
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_MASK  0x000001ff
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_WIDTH 9
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_MASK  0x0000fe00
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_WIDTH 7
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_MASK  0x01ff0000
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_WIDTH 9
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_MASK  0xfe000000
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_WIDTH 7
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_MASK  0x000000ff
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_WIDTH 8
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_MASK  0x0000ff00
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_WIDTH 8
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_MASK  0x00ff0000
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_WIDTH 8
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_MASK  0xff000000
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_WIDTH 8
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_MASK  0x0000ffff
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_WIDTH 16
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_MASK  0xffff0000
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_WIDTH 16
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_QMQ_Q0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_QMQ_Q0_FIELD_MASK  0x00000001
+#define BBH_TX_WAN_CONFIGURATIONS_QMQ_Q0_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_QMQ_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_QMQ_Q1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_QMQ_Q1_FIELD_MASK  0x00000002
+#define BBH_TX_WAN_CONFIGURATIONS_QMQ_Q1_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_QMQ_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_QMQ_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_QMQ_RESERVED0_FIELD_MASK  0xfffffffc
+#define BBH_TX_WAN_CONFIGURATIONS_QMQ_RESERVED0_FIELD_WIDTH 30
+#define BBH_TX_WAN_CONFIGURATIONS_QMQ_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSSIZE_FIFOSIZE0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_FIFOSIZE0_FIELD_MASK  0x000001ff
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_FIFOSIZE0_FIELD_WIDTH 9
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_FIFOSIZE0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSSIZE_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_RESERVED0_FIELD_MASK  0x0000fe00
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_RESERVED0_FIELD_WIDTH 7
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSSIZE_FIFOSIZE1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_FIFOSIZE1_FIELD_MASK  0x01ff0000
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_FIFOSIZE1_FIELD_WIDTH 9
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_FIFOSIZE1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSSIZE_RESERVED1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_RESERVED1_FIELD_MASK  0xfe000000
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_RESERVED1_FIELD_WIDTH 7
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_WKUPTHRESH0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_WKUPTHRESH0_FIELD_MASK  0x000000ff
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_WKUPTHRESH0_FIELD_WIDTH 8
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_WKUPTHRESH0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_RESERVED0_FIELD_MASK  0x0000ff00
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_RESERVED0_FIELD_WIDTH 8
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_WKUPTHRESH1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_WKUPTHRESH1_FIELD_MASK  0x00ff0000
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_WKUPTHRESH1_FIELD_WIDTH 8
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_WKUPTHRESH1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_RESERVED1_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_RESERVED1_FIELD_MASK  0xff000000
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_RESERVED1_FIELD_WIDTH 8
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_RESERVED1_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_MASK  0x00000001
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_MASK  0xfffffffe
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_WIDTH 31
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_MASK  0x000000ff
+#define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_WIDTH 8
+#define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_MASK  0xffffff00
+#define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_WIDTH 24
+#define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSEMPTY_EMPTY_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSEMPTY_EMPTY_FIELD_MASK  0x000000ff
+#define BBH_TX_WAN_CONFIGURATIONS_STSEMPTY_EMPTY_FIELD_WIDTH 8
+#define BBH_TX_WAN_CONFIGURATIONS_STSEMPTY_EMPTY_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSEMPTY_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSEMPTY_RESERVED0_FIELD_MASK  0xffffff00
+#define BBH_TX_WAN_CONFIGURATIONS_STSEMPTY_RESERVED0_FIELD_WIDTH 24
+#define BBH_TX_WAN_CONFIGURATIONS_STSEMPTY_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_TCONTADDR_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_TCONTADDR_FIELD_MASK  0x0000ffff
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_TCONTADDR_FIELD_WIDTH 16
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_TCONTADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_RESERVED0_FIELD_MASK  0xffff0000
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_RESERVED0_FIELD_WIDTH 16
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_PTRADDR_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_PTRADDR_FIELD_MASK  0x0000ffff
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_PTRADDR_FIELD_WIDTH 16
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_PTRADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_TASK_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_TASK_FIELD_MASK  0x000f0000
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_TASK_FIELD_WIDTH 4
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_TASK_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_RESERVED0_FIELD_MASK  0xfff00000
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_RESERVED0_FIELD_WIDTH 12
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_RESERVED0_FIELD_SHIFT 20
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_TCONTADDR_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_TCONTADDR_FIELD_MASK  0x0000ffff
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_TCONTADDR_FIELD_WIDTH 16
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_TCONTADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_RESERVED0_FIELD_MASK  0xffff0000
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_RESERVED0_FIELD_WIDTH 16
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_PTRADDR_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_PTRADDR_FIELD_MASK  0x0000ffff
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_PTRADDR_FIELD_WIDTH 16
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_PTRADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_TASK_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_TASK_FIELD_MASK  0x000f0000
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_TASK_FIELD_WIDTH 4
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_TASK_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_RESERVED0_FIELD_MASK  0xfff00000
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_RESERVED0_FIELD_WIDTH 12
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_RESERVED0_FIELD_SHIFT 20
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_STPLENERR_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_STPLENERR_FIELD_MASK  0x00000001
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_STPLENERR_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_STPLENERR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CMP_WIDTH_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CMP_WIDTH_FIELD_MASK  0x00000002
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CMP_WIDTH_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CMP_WIDTH_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CONSIDERFULL_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CONSIDERFULL_FIELD_MASK  0x00000004
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CONSIDERFULL_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CONSIDERFULL_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_ADDCRC_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_ADDCRC_FIELD_MASK  0x00000008
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_ADDCRC_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_ADDCRC_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_REQ_FULL_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_REQ_FULL_FIELD_MASK  0x000000f0
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_REQ_FULL_FIELD_WIDTH 4
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_REQ_FULL_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_RESERVED0_FIELD_MASK  0xffffff00
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_RESERVED0_FIELD_WIDTH 24
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_WDATA_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_WDATA_FIELD_MASK  0x0003ffff
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_WDATA_FIELD_WIDTH 18
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_WDATA_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_A_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_A_FIELD_MASK  0x03fc0000
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_A_FIELD_WIDTH 8
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_A_FIELD_SHIFT 18
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_CMD_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_CMD_FIELD_MASK  0x04000000
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_CMD_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_CMD_FIELD_SHIFT 26
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_RESERVED0_FIELD_MASK  0xf8000000
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_RESERVED0_FIELD_WIDTH 5
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_RESERVED0_FIELD_SHIFT 27
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_TS_EN_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_TS_EN_FIELD_MASK  0x00000001
+#define BBH_TX_WAN_CONFIGURATIONS_TS_EN_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_TS_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_TS_RESERVED0_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_TS_RESERVED0_FIELD_MASK  0xfffffffe
+#define BBH_TX_WAN_CONFIGURATIONS_TS_RESERVED0_FIELD_WIDTH 31
+#define BBH_TX_WAN_CONFIGURATIONS_TS_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_MAXWLEN_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_MAXWLEN_FIELD_MASK  0x0000ffff
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_MAXWLEN_FIELD_WIDTH 16
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_MAXWLEN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_MIN_CREDIT_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_MIN_CREDIT_FIELD_MASK  0x07ff0000
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_MIN_CREDIT_FIELD_WIDTH 11
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_MIN_CREDIT_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_SPARE_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_SPARE_FIELD_MASK  0x38000000
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_SPARE_FIELD_WIDTH 3
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_SPARE_FIELD_SHIFT 27
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_PRIO_EN_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_PRIO_EN_FIELD_MASK  0x40000000
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_PRIO_EN_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_PRIO_EN_FIELD_SHIFT 30
+
+extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_SRST_N_FIELD;
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_SRST_N_FIELD_MASK  0x80000000
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_SRST_N_FIELD_WIDTH 1
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_SRST_N_FIELD_SHIFT 31
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_Q2RNR_Q0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_Q2RNR_Q0_FIELD_MASK  0x00000001
+#define BBH_TX_LAN_CONFIGURATIONS_Q2RNR_Q0_FIELD_WIDTH 1
+#define BBH_TX_LAN_CONFIGURATIONS_Q2RNR_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_Q2RNR_Q1_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_Q2RNR_Q1_FIELD_MASK  0x00000002
+#define BBH_TX_LAN_CONFIGURATIONS_Q2RNR_Q1_FIELD_WIDTH 1
+#define BBH_TX_LAN_CONFIGURATIONS_Q2RNR_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_MASK  0xfffffffc
+#define BBH_TX_LAN_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_WIDTH 30
+#define BBH_TX_LAN_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_QPROF_Q0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_Q0_FIELD_MASK  0x00000001
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_Q0_FIELD_WIDTH 1
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_QPROF_Q1_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_Q1_FIELD_MASK  0x00000002
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_Q1_FIELD_WIDTH 1
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_QPROF_DIS0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_DIS0_FIELD_MASK  0x00000004
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_DIS0_FIELD_WIDTH 1
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_DIS0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_QPROF_DIS1_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_DIS1_FIELD_MASK  0x00000008
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_DIS1_FIELD_WIDTH 1
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_DIS1_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_QPROF_RESERVED0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_RESERVED0_FIELD_MASK  0xfffffff0
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_RESERVED0_FIELD_WIDTH 28
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_MASK  0x000001ff
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_WIDTH 9
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_MASK  0x0000fe00
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_WIDTH 7
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_MASK  0x01ff0000
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_WIDTH 9
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_MASK  0xfe000000
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_WIDTH 7
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_MASK  0x000000ff
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_WIDTH 8
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_MASK  0x0000ff00
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_WIDTH 8
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_MASK  0x00ff0000
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_WIDTH 8
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_MASK  0xff000000
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_WIDTH 8
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_MASK  0x0000ffff
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_WIDTH 16
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_MASK  0xffff0000
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_WIDTH 16
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_QMQ_Q0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_QMQ_Q0_FIELD_MASK  0x00000001
+#define BBH_TX_LAN_CONFIGURATIONS_QMQ_Q0_FIELD_WIDTH 1
+#define BBH_TX_LAN_CONFIGURATIONS_QMQ_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_QMQ_Q1_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_QMQ_Q1_FIELD_MASK  0x00000002
+#define BBH_TX_LAN_CONFIGURATIONS_QMQ_Q1_FIELD_WIDTH 1
+#define BBH_TX_LAN_CONFIGURATIONS_QMQ_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_QMQ_RESERVED0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_QMQ_RESERVED0_FIELD_MASK  0xfffffffc
+#define BBH_TX_LAN_CONFIGURATIONS_QMQ_RESERVED0_FIELD_WIDTH 30
+#define BBH_TX_LAN_CONFIGURATIONS_QMQ_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_MASK  0x00000001
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_WIDTH 1
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_MASK  0xfffffffe
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_WIDTH 31
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_MASK  0x000000ff
+#define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_WIDTH 8
+#define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_MASK  0xffffff00
+#define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_WIDTH 24
+#define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD_MASK  0x000001ff
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD_WIDTH 9
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_MASK  0x0000fe00
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_WIDTH 7
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD_MASK  0x01ff0000
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD_WIDTH 9
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_MASK  0xfe000000
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_WIDTH 7
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_EEE_EN_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_EEE_EN_FIELD_MASK  0x00000001
+#define BBH_TX_LAN_CONFIGURATIONS_EEE_EN_FIELD_WIDTH 1
+#define BBH_TX_LAN_CONFIGURATIONS_EEE_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD_MASK  0xfffffffe
+#define BBH_TX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD_WIDTH 31
+#define BBH_TX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TS_EN_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_TS_EN_FIELD_MASK  0x00000001
+#define BBH_TX_LAN_CONFIGURATIONS_TS_EN_FIELD_WIDTH 1
+#define BBH_TX_LAN_CONFIGURATIONS_TS_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD;
+#define BBH_TX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD_MASK  0xfffffffe
+#define BBH_TX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD_WIDTH 31
+#define BBH_TX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_Q0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_Q0_FIELD_MASK  0x00000001
+#define BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_Q0_FIELD_WIDTH 1
+#define BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_Q1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_Q1_FIELD_MASK  0x00000002
+#define BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_Q1_FIELD_WIDTH 1
+#define BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_MASK  0xfffffffc
+#define BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_WIDTH 30
+#define BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_Q0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_Q0_FIELD_MASK  0x00000001
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_Q0_FIELD_WIDTH 1
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_Q1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_Q1_FIELD_MASK  0x00000002
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_Q1_FIELD_WIDTH 1
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_DIS0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_DIS0_FIELD_MASK  0x00000004
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_DIS0_FIELD_WIDTH 1
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_DIS0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_DIS1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_DIS1_FIELD_MASK  0x00000008
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_DIS1_FIELD_WIDTH 1
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_DIS1_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_RESERVED0_FIELD_MASK  0xfffffff0
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_RESERVED0_FIELD_WIDTH 28
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_MASK  0x000001ff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_WIDTH 9
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_MASK  0x0000fe00
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_WIDTH 7
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_MASK  0x01ff0000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_WIDTH 9
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_MASK  0xfe000000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_WIDTH 7
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_MASK  0x000000ff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_WIDTH 8
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_MASK  0x0000ff00
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_WIDTH 8
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_MASK  0x00ff0000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_WIDTH 8
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_MASK  0xff000000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_WIDTH 8
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_MASK  0x0000ffff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_WIDTH 16
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_MASK  0xffff0000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_WIDTH 16
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_Q0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_Q0_FIELD_MASK  0x00000001
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_Q0_FIELD_WIDTH 1
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_Q0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_Q1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_Q1_FIELD_MASK  0x00000002
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_Q1_FIELD_WIDTH 1
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_Q1_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_RESERVED0_FIELD_MASK  0xfffffffc
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_RESERVED0_FIELD_WIDTH 30
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_MASK  0x00000001
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_WIDTH 1
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_MASK  0xfffffffe
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_WIDTH 31
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_MASK  0x000000ff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_WIDTH 8
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_MASK  0xffffff00
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_WIDTH 24
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_DDRTHRESH_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_DDRTHRESH_FIELD_MASK  0x000001ff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_DDRTHRESH_FIELD_WIDTH 9
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_DDRTHRESH_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED0_FIELD_MASK  0x0000fe00
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED0_FIELD_WIDTH 7
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_SRAMTHRESH_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_SRAMTHRESH_FIELD_MASK  0x01ff0000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_SRAMTHRESH_FIELD_WIDTH 9
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_SRAMTHRESH_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED1_FIELD_MASK  0xfe000000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED1_FIELD_WIDTH 7
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_EEE_EN_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_EN_FIELD_MASK  0x000000ff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_EN_FIELD_WIDTH 8
+#define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_EEE_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_RESERVED0_FIELD_MASK  0xffffff00
+#define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_RESERVED0_FIELD_WIDTH 24
+#define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TS_EN_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TS_EN_FIELD_MASK  0x000000ff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TS_EN_FIELD_WIDTH 8
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TS_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TS_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TS_RESERVED0_FIELD_MASK  0xffffff00
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TS_RESERVED0_FIELD_WIDTH 24
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TS_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE0_FIELD_MASK  0x00000fff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE0_FIELD_WIDTH 12
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED0_FIELD_MASK  0x0000f000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED0_FIELD_WIDTH 4
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE1_FIELD_MASK  0x0fff0000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE1_FIELD_WIDTH 12
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED1_FIELD_MASK  0xf0000000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED1_FIELD_WIDTH 4
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED1_FIELD_SHIFT 28
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE0_FIELD_MASK  0x00000fff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE0_FIELD_WIDTH 12
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED0_FIELD_MASK  0x0000f000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED0_FIELD_WIDTH 4
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE1_FIELD_MASK  0x0fff0000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE1_FIELD_WIDTH 12
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED1_FIELD_MASK  0xf0000000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED1_FIELD_WIDTH 4
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED1_FIELD_SHIFT 28
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE0_FIELD_MASK  0x000001ff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE0_FIELD_WIDTH 9
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED0_FIELD_MASK  0x0000fe00
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED0_FIELD_WIDTH 7
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE1_FIELD_MASK  0x01ff0000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE1_FIELD_WIDTH 9
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED1_FIELD_MASK  0xfe000000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED1_FIELD_WIDTH 7
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE0_FIELD_MASK  0x000001ff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE0_FIELD_WIDTH 9
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED0_FIELD_MASK  0x0000fe00
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED0_FIELD_WIDTH 7
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE1_FIELD_MASK  0x01ff0000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE1_FIELD_WIDTH 9
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED1_FIELD_MASK  0xfe000000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED1_FIELD_WIDTH 7
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W0_FIELD_MASK  0x0000000f
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W0_FIELD_WIDTH 4
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED0_FIELD_MASK  0x0000fff0
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED0_FIELD_WIDTH 12
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W1_FIELD_MASK  0x000f0000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W1_FIELD_WIDTH 4
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED1_FIELD_MASK  0xfff00000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED1_FIELD_WIDTH 12
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH0_FIELD_MASK  0x000001ff
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH0_FIELD_WIDTH 9
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_MASK  0x0000fe00
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_WIDTH 7
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH1_FIELD_MASK  0x01ff0000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH1_FIELD_WIDTH 9
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_MASK  0xfe000000
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_WIDTH 7
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD_MASK  0x0000ffff
+#define BBH_TX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD_MASK  0xffff0000
+#define BBH_TX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD_MASK  0x0000ffff
+#define BBH_TX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD_MASK  0xffff0000
+#define BBH_TX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD_MASK  0x0000ffff
+#define BBH_TX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD_MASK  0xffff0000
+#define BBH_TX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD_MASK  0x0000ffff
+#define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD_MASK  0xffff0000
+#define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD_MASK  0x0000ffff
+#define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD_MASK  0xffff0000
+#define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_LENERR_LENERR_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_LENERR_LENERR_FIELD_MASK  0x0000ffff
+#define BBH_TX_DEBUG_COUNTERS_LENERR_LENERR_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_LENERR_LENERR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD_MASK  0xffff0000
+#define BBH_TX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD_MASK  0x0000ffff
+#define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD_MASK  0xffff0000
+#define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD_WIDTH 16
+#define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD_MASK  0x00000001
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD_MASK  0x00000002
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD_MASK  0x00000004
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD_MASK  0x00000008
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD_MASK  0x00000010
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD_MASK  0x00000020
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD_SHIFT 5
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD_MASK  0x00000040
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD_MASK  0x00000080
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD_SHIFT 7
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD_MASK  0x00000100
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD_MASK  0x00000200
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD_MASK  0x00000400
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD_SHIFT 10
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD_MASK  0x00000800
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD_SHIFT 11
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD_MASK  0x00001000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD_SHIFT 12
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD_MASK  0x00002000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD_SHIFT 13
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD_MASK  0x00004000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD_SHIFT 14
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD_MASK  0x00008000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD_SHIFT 15
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD_MASK  0x00010000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD_MASK  0x00020000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD_SHIFT 17
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD_MASK  0x00040000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD_SHIFT 18
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD_MASK  0x00080000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD_SHIFT 19
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD_MASK  0x00100000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD_SHIFT 20
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD_MASK  0x00200000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD_SHIFT 21
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD_MASK  0x00400000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD_SHIFT 22
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD_MASK  0x00800000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD_SHIFT 23
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD_MASK  0x01000000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD_MASK  0x02000000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD_MASK  0x04000000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD_SHIFT 26
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD_MASK  0x08000000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD_SHIFT 27
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD_MASK  0x10000000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD_SHIFT 28
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD_MASK  0x20000000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD_SHIFT 29
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD_MASK  0x40000000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD_SHIFT 30
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD_MASK  0x80000000
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD_WIDTH 1
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD_SHIFT 31
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD_MASK  0x000007ff
+#define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD_WIDTH 11
+#define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD_MASK  0xfffff800
+#define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD_WIDTH 21
+#define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_FIELD;
+#define BBH_TX_DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_FIELD_MASK  0xffffffff
+#define BBH_TX_DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_FIELD_WIDTH 32
+#define BBH_TX_DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_SDMABBID_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SDMABBID_FIELD_MASK  0x0000003f
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SDMABBID_FIELD_WIDTH 6
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SDMABBID_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED0_FIELD_MASK  0x000000c0
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED0_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_DISPBBID_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_DISPBBID_FIELD_MASK  0x00003f00
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_DISPBBID_FIELD_WIDTH 6
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_DISPBBID_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED1_FIELD_MASK  0x0000c000
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED1_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_SBPMBBID_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SBPMBBID_FIELD_MASK  0x003f0000
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SBPMBBID_FIELD_WIDTH 6
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SBPMBBID_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED2_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED2_FIELD_MASK  0xffc00000
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED2_FIELD_WIDTH 10
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED2_FIELD_SHIFT 22
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_NORMALVIQ_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_NORMALVIQ_FIELD_MASK  0x0000001f
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_NORMALVIQ_FIELD_WIDTH 5
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_NORMALVIQ_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED0_FIELD_MASK  0x000000e0
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED0_FIELD_WIDTH 3
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_EXCLVIQ_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_EXCLVIQ_FIELD_MASK  0x00001f00
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_EXCLVIQ_FIELD_WIDTH 5
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_EXCLVIQ_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED1_FIELD_MASK  0xffffe000
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED1_FIELD_WIDTH 19
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_PATTERNDATALSB_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_PATTERNDATALSB_FIELD_MASK  0xffffffff
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_PATTERNDATALSB_FIELD_WIDTH 32
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_PATTERNDATALSB_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_PATTERNDATAMSB_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_PATTERNDATAMSB_FIELD_MASK  0xffffffff
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_PATTERNDATAMSB_FIELD_WIDTH 32
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_PATTERNDATAMSB_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_PATTERNMASKLSB_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_PATTERNMASKLSB_FIELD_MASK  0xffffffff
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_PATTERNMASKLSB_FIELD_WIDTH 32
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_PATTERNMASKLSB_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_PATTERNMASKMSB_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_PATTERNMASKMSB_FIELD_MASK  0xffffffff
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_PATTERNMASKMSB_FIELD_WIDTH 32
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_PATTERNMASKMSB_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PLOAMEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PLOAMEN_FIELD_MASK  0x00000001
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PLOAMEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PLOAMEN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PRI3EN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PRI3EN_FIELD_MASK  0x00000002
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PRI3EN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PRI3EN_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PAUSEEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PAUSEEN_FIELD_MASK  0x00000004
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PAUSEEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PAUSEEN_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PFCEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PFCEN_FIELD_MASK  0x00000008
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PFCEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PFCEN_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_CTRLEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_CTRLEN_FIELD_MASK  0x00000010
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_CTRLEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_CTRLEN_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_MULTEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_MULTEN_FIELD_MASK  0x00000020
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_MULTEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_MULTEN_FIELD_SHIFT 5
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_OAMEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_OAMEN_FIELD_MASK  0x00000040
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_OAMEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_OAMEN_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED0_FIELD_MASK  0x00000080
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED0_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTENOFFSET_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTENOFFSET_FIELD_MASK  0x00000f00
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTENOFFSET_FIELD_WIDTH 4
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTENOFFSET_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED1_FIELD_MASK  0x0000f000
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED1_FIELD_WIDTH 4
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED1_FIELD_SHIFT 12
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTERNEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTERNEN_FIELD_MASK  0x00010000
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTERNEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTERNEN_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED2_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED2_FIELD_MASK  0x000e0000
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED2_FIELD_WIDTH 3
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED2_FIELD_SHIFT 17
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_EXCEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_EXCEN_FIELD_MASK  0x00100000
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_EXCEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_EXCEN_FIELD_SHIFT 20
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_DISNORMALCHECK_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_DISNORMALCHECK_FIELD_MASK  0x00200000
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_DISNORMALCHECK_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_DISNORMALCHECK_FIELD_SHIFT 21
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED3_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED3_FIELD_MASK  0xffc00000
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED3_FIELD_WIDTH 10
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED3_FIELD_SHIFT 22
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DATABASE_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DATABASE_FIELD_MASK  0x0000003f
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DATABASE_FIELD_WIDTH 6
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DATABASE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED0_FIELD_MASK  0x000000c0
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED0_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DESCBASE_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DESCBASE_FIELD_MASK  0x00003f00
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DESCBASE_FIELD_WIDTH 6
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DESCBASE_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED1_FIELD_MASK  0xffffc000
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED1_FIELD_WIDTH 18
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_FIELD_MASK  0x0000007f
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_FIELD_WIDTH 7
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED0_FIELD_MASK  0x00000080
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED0_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_FIELD_MASK  0x00007f00
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_FIELD_WIDTH 7
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED1_FIELD_MASK  0x00008000
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED1_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED1_FIELD_SHIFT 15
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_COHERENCYEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_COHERENCYEN_FIELD_MASK  0x00010000
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_COHERENCYEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_COHERENCYEN_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED2_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED2_FIELD_MASK  0xfffe0000
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED2_FIELD_WIDTH 15
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED2_FIELD_SHIFT 17
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT0_FIELD_MASK  0x000000ff
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT0_FIELD_WIDTH 8
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT1_FIELD_MASK  0x0000ff00
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT1_FIELD_WIDTH 8
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT1_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT2_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT2_FIELD_MASK  0x00ff0000
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT2_FIELD_WIDTH 8
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT2_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT3_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT3_FIELD_MASK  0xff000000
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT3_FIELD_WIDTH 8
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT3_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT0_FIELD_MASK  0x00003fff
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT0_FIELD_WIDTH 14
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED0_FIELD_MASK  0x0000c000
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED0_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT1_FIELD_MASK  0x3fff0000
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT1_FIELD_WIDTH 14
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT1_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED1_FIELD_MASK  0xc0000000
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED1_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED1_FIELD_SHIFT 30
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT2_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT2_FIELD_MASK  0x00003fff
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT2_FIELD_WIDTH 14
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT2_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED0_FIELD_MASK  0x0000c000
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED0_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT3_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT3_FIELD_MASK  0x3fff0000
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT3_FIELD_WIDTH 14
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT3_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED1_FIELD_MASK  0xc0000000
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED1_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED1_FIELD_SHIFT 30
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_SOPOFFSET_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_SOPOFFSET_FIELD_MASK  0x0000007f
+#define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_SOPOFFSET_FIELD_WIDTH 7
+#define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_SOPOFFSET_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_RESERVED0_FIELD_MASK  0xffffff80
+#define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_RESERVED0_FIELD_WIDTH 25
+#define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_TIMER_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_TIMER_FIELD_MASK  0x00ffffff
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_TIMER_FIELD_WIDTH 24
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_DISPDROPDIS_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_DISPDROPDIS_FIELD_MASK  0x01000000
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_DISPDROPDIS_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_DISPDROPDIS_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SDMADROPDIS_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SDMADROPDIS_FIELD_MASK  0x02000000
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SDMADROPDIS_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SDMADROPDIS_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMDROPDIS_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMDROPDIS_FIELD_MASK  0x04000000
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMDROPDIS_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMDROPDIS_FIELD_SHIFT 26
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED0_FIELD_MASK  0x08000000
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED0_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED0_FIELD_SHIFT 27
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_FCFORCE_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_FCFORCE_FIELD_MASK  0x10000000
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_FCFORCE_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_FCFORCE_FIELD_SHIFT 28
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED1_FIELD_MASK  0xe0000000
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED1_FIELD_WIDTH 3
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED1_FIELD_SHIFT 29
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_CRCOMITDIS_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_CRCOMITDIS_FIELD_MASK  0x00000001
+#define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_CRCOMITDIS_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_CRCOMITDIS_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_RESERVED0_FIELD_MASK  0xfffffffe
+#define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_RESERVED0_FIELD_WIDTH 31
+#define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_ENABLE_PKTEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_ENABLE_PKTEN_FIELD_MASK  0x00000001
+#define BBH_RX_GENERAL_CONFIGURATION_ENABLE_PKTEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_ENABLE_PKTEN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_ENABLE_SBPMEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_ENABLE_SBPMEN_FIELD_MASK  0x00000002
+#define BBH_RX_GENERAL_CONFIGURATION_ENABLE_SBPMEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_ENABLE_SBPMEN_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_ENABLE_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_ENABLE_RESERVED0_FIELD_MASK  0xfffffffc
+#define BBH_RX_GENERAL_CONFIGURATION_ENABLE_RESERVED0_FIELD_WIDTH 30
+#define BBH_RX_GENERAL_CONFIGURATION_ENABLE_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_G9991EN_ENABLE_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_G9991EN_ENABLE_FIELD_MASK  0x00000001
+#define BBH_RX_GENERAL_CONFIGURATION_G9991EN_ENABLE_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_G9991EN_ENABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_G9991EN_BYTES4_7ENABLE_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_G9991EN_BYTES4_7ENABLE_FIELD_MASK  0x00000002
+#define BBH_RX_GENERAL_CONFIGURATION_G9991EN_BYTES4_7ENABLE_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_G9991EN_BYTES4_7ENABLE_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_G9991EN_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_G9991EN_RESERVED0_FIELD_MASK  0xfffffffc
+#define BBH_RX_GENERAL_CONFIGURATION_G9991EN_RESERVED0_FIELD_WIDTH 30
+#define BBH_RX_GENERAL_CONFIGURATION_G9991EN_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_FIELD_MASK  0x000000ff
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_FIELD_WIDTH 8
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_RESERVED0_FIELD_MASK  0xffffff00
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_RESERVED0_FIELD_WIDTH 24
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_FIELD_MASK  0x00000003
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_FIELD_MASK  0x0000000c
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_FIELD_MASK  0x00000030
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_FIELD_MASK  0x000000c0
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_RESERVED0_FIELD_MASK  0xffffff00
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_RESERVED0_FIELD_WIDTH 24
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_FIELD_MASK  0xffffffff
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_FIELD_WIDTH 32
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_FIELD_MASK  0xffffffff
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_FIELD_WIDTH 32
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_FIELD_MASK  0xffffffff
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_FIELD_WIDTH 32
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_FIELD_MASK  0xffffffff
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_FIELD_WIDTH 32
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACMODE_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACMODE_FIELD_MASK  0x00000001
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACMODE_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACMODE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MACMODE_GPONMODE_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_GPONMODE_FIELD_MASK  0x00000002
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_GPONMODE_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_GPONMODE_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACVDSL_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACVDSL_FIELD_MASK  0x00000004
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACVDSL_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACVDSL_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MACMODE_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_RESERVED0_FIELD_MASK  0xfffffff8
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_RESERVED0_FIELD_WIDTH 29
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_MAXREQ_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_MAXREQ_FIELD_MASK  0x0000000f
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_MAXREQ_FIELD_WIDTH 4
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_MAXREQ_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED0_FIELD_MASK  0x000000f0
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED0_FIELD_WIDTH 4
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_PRIDROPEN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_PRIDROPEN_FIELD_MASK  0x00000100
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_PRIDROPEN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_PRIDROPEN_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED1_FIELD_MASK  0x0000fe00
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED1_FIELD_WIDTH 7
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED1_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_CNGSEL_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_CNGSEL_FIELD_MASK  0x00010000
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_CNGSEL_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_CNGSEL_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED2_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED2_FIELD_MASK  0xfffe0000
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED2_FIELD_WIDTH 15
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED2_FIELD_SHIFT 17
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INBUFRST_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INBUFRST_FIELD_MASK  0x00000001
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INBUFRST_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INBUFRST_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BURSTBUFRST_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BURSTBUFRST_FIELD_MASK  0x00000002
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BURSTBUFRST_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BURSTBUFRST_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INGRESSCNTXT_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INGRESSCNTXT_FIELD_MASK  0x00000004
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INGRESSCNTXT_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INGRESSCNTXT_FIELD_SHIFT 2
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CMDFIFORST_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CMDFIFORST_FIELD_MASK  0x00000008
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CMDFIFORST_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CMDFIFORST_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SBPMFIFORST_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SBPMFIFORST_FIELD_MASK  0x00000010
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SBPMFIFORST_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SBPMFIFORST_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_COHERENCYFIFORST_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_COHERENCYFIFORST_FIELD_MASK  0x00000020
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_COHERENCYFIFORST_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_COHERENCYFIFORST_FIELD_SHIFT 5
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CNTXTRST_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CNTXTRST_FIELD_MASK  0x00000040
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CNTXTRST_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CNTXTRST_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SDMARST_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SDMARST_FIELD_MASK  0x00000080
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SDMARST_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SDMARST_FIELD_SHIFT 7
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RESERVED0_FIELD_MASK  0xffffff00
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RESERVED0_FIELD_WIDTH 24
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RXDBGSEL_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RXDBGSEL_FIELD_MASK  0x0000000f
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RXDBGSEL_FIELD_WIDTH 4
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RXDBGSEL_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RESERVED0_FIELD_MASK  0xfffffff0
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RESERVED0_FIELD_WIDTH 28
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_ID_2OVERWR_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_ID_2OVERWR_FIELD_MASK  0x0000003f
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_ID_2OVERWR_FIELD_WIDTH 6
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_ID_2OVERWR_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED0_FIELD_MASK  0x000000c0
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED0_FIELD_WIDTH 2
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_RA_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_RA_FIELD_MASK  0x0003ff00
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_RA_FIELD_WIDTH 10
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_RA_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED1_FIELD_MASK  0x00fc0000
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED1_FIELD_WIDTH 6
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED1_FIELD_SHIFT 18
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_EN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_EN_FIELD_MASK  0x01000000
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_EN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_EN_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED2_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED2_FIELD_MASK  0xfe000000
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED2_FIELD_WIDTH 7
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED2_FIELD_SHIFT 25
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_NONETH_FLOWID_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_NONETH_FLOWID_FIELD_MASK  0x000000ff
+#define BBH_RX_GENERAL_CONFIGURATION_NONETH_FLOWID_FIELD_WIDTH 8
+#define BBH_RX_GENERAL_CONFIGURATION_NONETH_FLOWID_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_NONETH_ENABLE_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_NONETH_ENABLE_FIELD_MASK  0x00000100
+#define BBH_RX_GENERAL_CONFIGURATION_NONETH_ENABLE_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_NONETH_ENABLE_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_NONETH_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_NONETH_RESERVED0_FIELD_MASK  0xfffffe00
+#define BBH_RX_GENERAL_CONFIGURATION_NONETH_RESERVED0_FIELD_WIDTH 23
+#define BBH_RX_GENERAL_CONFIGURATION_NONETH_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK  0x00000001
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED0_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK  0x000000fe
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_TIMER_VAL_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK  0x0000ff00
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK  0x00010000
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED1_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK  0x000e0000
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK  0x00700000
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED2_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK  0x00800000
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23
+
+extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD;
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK  0xff000000
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_INPKT_INPKT_FIELD;
+#define BBH_RX_PM_COUNTERS_INPKT_INPKT_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_INPKT_INPKT_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_INPKT_INPKT_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_THIRDFLOW_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_THIRDFLOW_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_THIRDFLOW_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_THIRDFLOW_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_SOPASOP_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_SOPASOP_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_SOPASOP_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_SOPASOP_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_TOOSHORT_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_TOOSHORT_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_TOOSHORT_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_TOOSHORT_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_TOOLONG_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_TOOLONG_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_TOOLONG_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_TOOLONG_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_CRCERROR_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_CRCERROR_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_CRCERROR_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_CRCERROR_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_ENCRYPTERROR_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_ENCRYPTERROR_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_ENCRYPTERROR_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_ENCRYPTERROR_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_DISPCONG_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_DISPCONG_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_DISPCONG_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_DISPCONG_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_NOSBPMSBN_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_NOSBPMSBN_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_NOSBPMSBN_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_NOSBPMSBN_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_NOSDMACD_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_NOSDMACD_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_NOSDMACD_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_NOSDMACD_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_INPLOAM_INPLOAM_FIELD;
+#define BBH_RX_PM_COUNTERS_INPLOAM_INPLOAM_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_INPLOAM_INPLOAM_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_INPLOAM_INPLOAM_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_CRCERRORPLOAM_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_DISPCONGPLOAM_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_DISPCONGPLOAM_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_DISPCONGPLOAM_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_DISPCONGPLOAM_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_EPONTYPERROR_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_EPONTYPERROR_PMVALUE_FIELD_MASK  0xffffffff
+#define BBH_RX_PM_COUNTERS_EPONTYPERROR_PMVALUE_FIELD_WIDTH 32
+#define BBH_RX_PM_COUNTERS_EPONTYPERROR_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_RUNTERROR_PMVALUE_FIELD;
+#define BBH_RX_PM_COUNTERS_RUNTERROR_PMVALUE_FIELD_MASK  0x0000ffff
+#define BBH_RX_PM_COUNTERS_RUNTERROR_PMVALUE_FIELD_WIDTH 16
+#define BBH_RX_PM_COUNTERS_RUNTERROR_PMVALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_PM_COUNTERS_RUNTERROR_RESERVED0_FIELD;
+#define BBH_RX_PM_COUNTERS_RUNTERROR_RESERVED0_FIELD_MASK  0xffff0000
+#define BBH_RX_PM_COUNTERS_RUNTERROR_RESERVED0_FIELD_WIDTH 16
+#define BBH_RX_PM_COUNTERS_RUNTERROR_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0LSB_INREASS_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0LSB_INREASS_FIELD_MASK  0x00000001
+#define BBH_RX_DEBUG_CNTXTX0LSB_INREASS_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_CNTXTX0LSB_INREASS_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0LSB_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED0_FIELD_MASK  0x000000fe
+#define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED0_FIELD_WIDTH 7
+#define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0LSB_FLOWID_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0LSB_FLOWID_FIELD_MASK  0x0000ff00
+#define BBH_RX_DEBUG_CNTXTX0LSB_FLOWID_FIELD_WIDTH 8
+#define BBH_RX_DEBUG_CNTXTX0LSB_FLOWID_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0LSB_CUROFFSET_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0LSB_CUROFFSET_FIELD_MASK  0x3fff0000
+#define BBH_RX_DEBUG_CNTXTX0LSB_CUROFFSET_FIELD_WIDTH 14
+#define BBH_RX_DEBUG_CNTXTX0LSB_CUROFFSET_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0LSB_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED1_FIELD_MASK  0xc0000000
+#define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED1_FIELD_WIDTH 2
+#define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED1_FIELD_SHIFT 30
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0MSB_CURBN_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0MSB_CURBN_FIELD_MASK  0x00001fff
+#define BBH_RX_DEBUG_CNTXTX0MSB_CURBN_FIELD_WIDTH 13
+#define BBH_RX_DEBUG_CNTXTX0MSB_CURBN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0MSB_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED0_FIELD_MASK  0x0000e000
+#define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED0_FIELD_WIDTH 3
+#define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0MSB_FIRSTBN_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0MSB_FIRSTBN_FIELD_MASK  0x7fff0000
+#define BBH_RX_DEBUG_CNTXTX0MSB_FIRSTBN_FIELD_WIDTH 15
+#define BBH_RX_DEBUG_CNTXTX0MSB_FIRSTBN_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0MSB_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED1_FIELD_MASK  0x80000000
+#define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED1_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED1_FIELD_SHIFT 31
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1LSB_INREASS_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1LSB_INREASS_FIELD_MASK  0x00000001
+#define BBH_RX_DEBUG_CNTXTX1LSB_INREASS_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_CNTXTX1LSB_INREASS_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1LSB_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED0_FIELD_MASK  0x000000fe
+#define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED0_FIELD_WIDTH 7
+#define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1LSB_FLOWID_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1LSB_FLOWID_FIELD_MASK  0x0000ff00
+#define BBH_RX_DEBUG_CNTXTX1LSB_FLOWID_FIELD_WIDTH 8
+#define BBH_RX_DEBUG_CNTXTX1LSB_FLOWID_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1LSB_CUROFFSET_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1LSB_CUROFFSET_FIELD_MASK  0x3fff0000
+#define BBH_RX_DEBUG_CNTXTX1LSB_CUROFFSET_FIELD_WIDTH 14
+#define BBH_RX_DEBUG_CNTXTX1LSB_CUROFFSET_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1LSB_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED1_FIELD_MASK  0xc0000000
+#define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED1_FIELD_WIDTH 2
+#define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED1_FIELD_SHIFT 30
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1MSB_CURBN_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1MSB_CURBN_FIELD_MASK  0x00001fff
+#define BBH_RX_DEBUG_CNTXTX1MSB_CURBN_FIELD_WIDTH 13
+#define BBH_RX_DEBUG_CNTXTX1MSB_CURBN_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1MSB_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED0_FIELD_MASK  0x0000e000
+#define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED0_FIELD_WIDTH 3
+#define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1MSB_FIRSTBN_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1MSB_FIRSTBN_FIELD_MASK  0x7fff0000
+#define BBH_RX_DEBUG_CNTXTX1MSB_FIRSTBN_FIELD_WIDTH 15
+#define BBH_RX_DEBUG_CNTXTX1MSB_FIRSTBN_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1MSB_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED1_FIELD_MASK  0x80000000
+#define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED1_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED1_FIELD_SHIFT 31
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_INREASS_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_INREASS_FIELD_MASK  0x00000001
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_INREASS_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_INREASS_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED0_FIELD_MASK  0x0000000e
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED0_FIELD_WIDTH 3
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_SOP_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_SOP_FIELD_MASK  0x00000010
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_SOP_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_SOP_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED1_FIELD_MASK  0x00000020
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED1_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED1_FIELD_SHIFT 5
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_PRIORITY_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_PRIORITY_FIELD_MASK  0x000000c0
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_PRIORITY_FIELD_WIDTH 2
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_PRIORITY_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_FLOWID_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_FLOWID_FIELD_MASK  0x0000ff00
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_FLOWID_FIELD_WIDTH 8
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_FLOWID_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_CUROFFSET_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_CUROFFSET_FIELD_MASK  0x3fff0000
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_CUROFFSET_FIELD_WIDTH 14
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_CUROFFSET_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED2_FIELD;
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED2_FIELD_MASK  0xc0000000
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED2_FIELD_WIDTH 2
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED2_FIELD_SHIFT 30
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_INREASS_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_INREASS_FIELD_MASK  0x00000001
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_INREASS_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_INREASS_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED0_FIELD_MASK  0x0000000e
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED0_FIELD_WIDTH 3
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_SOP_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_SOP_FIELD_MASK  0x00000010
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_SOP_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_SOP_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED1_FIELD_MASK  0x00000020
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED1_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED1_FIELD_SHIFT 5
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_PRIORITY_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_PRIORITY_FIELD_MASK  0x000000c0
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_PRIORITY_FIELD_WIDTH 2
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_PRIORITY_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_FLOWID_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_FLOWID_FIELD_MASK  0x0000ff00
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_FLOWID_FIELD_WIDTH 8
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_FLOWID_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_CUROFFSET_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_CUROFFSET_FIELD_MASK  0x3fff0000
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_CUROFFSET_FIELD_WIDTH 14
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_CUROFFSET_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED2_FIELD;
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED2_FIELD_MASK  0xc0000000
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED2_FIELD_WIDTH 2
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED2_FIELD_SHIFT 30
+
+extern const ru_field_rec BBH_RX_DEBUG_IBUW_UW_FIELD;
+#define BBH_RX_DEBUG_IBUW_UW_FIELD_MASK  0x00000007
+#define BBH_RX_DEBUG_IBUW_UW_FIELD_WIDTH 3
+#define BBH_RX_DEBUG_IBUW_UW_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_IBUW_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_IBUW_RESERVED0_FIELD_MASK  0xfffffff8
+#define BBH_RX_DEBUG_IBUW_RESERVED0_FIELD_WIDTH 29
+#define BBH_RX_DEBUG_IBUW_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_RX_DEBUG_BBUW_UW_FIELD;
+#define BBH_RX_DEBUG_BBUW_UW_FIELD_MASK  0x0000000f
+#define BBH_RX_DEBUG_BBUW_UW_FIELD_WIDTH 4
+#define BBH_RX_DEBUG_BBUW_UW_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_BBUW_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_BBUW_RESERVED0_FIELD_MASK  0xfffffff0
+#define BBH_RX_DEBUG_BBUW_RESERVED0_FIELD_WIDTH 28
+#define BBH_RX_DEBUG_BBUW_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec BBH_RX_DEBUG_CFUW_UW_FIELD;
+#define BBH_RX_DEBUG_CFUW_UW_FIELD_MASK  0x0000003f
+#define BBH_RX_DEBUG_CFUW_UW_FIELD_WIDTH 6
+#define BBH_RX_DEBUG_CFUW_UW_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_CFUW_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_CFUW_RESERVED0_FIELD_MASK  0xffffffc0
+#define BBH_RX_DEBUG_CFUW_RESERVED0_FIELD_WIDTH 26
+#define BBH_RX_DEBUG_CFUW_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec BBH_RX_DEBUG_ACKCNT_SDMA_FIELD;
+#define BBH_RX_DEBUG_ACKCNT_SDMA_FIELD_MASK  0x0000001f
+#define BBH_RX_DEBUG_ACKCNT_SDMA_FIELD_WIDTH 5
+#define BBH_RX_DEBUG_ACKCNT_SDMA_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_ACKCNT_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_ACKCNT_RESERVED0_FIELD_MASK  0x000000e0
+#define BBH_RX_DEBUG_ACKCNT_RESERVED0_FIELD_WIDTH 3
+#define BBH_RX_DEBUG_ACKCNT_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec BBH_RX_DEBUG_ACKCNT_CONNECT_FIELD;
+#define BBH_RX_DEBUG_ACKCNT_CONNECT_FIELD_MASK  0x00001f00
+#define BBH_RX_DEBUG_ACKCNT_CONNECT_FIELD_WIDTH 5
+#define BBH_RX_DEBUG_ACKCNT_CONNECT_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_DEBUG_ACKCNT_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_ACKCNT_RESERVED1_FIELD_MASK  0xffffe000
+#define BBH_RX_DEBUG_ACKCNT_RESERVED1_FIELD_WIDTH 19
+#define BBH_RX_DEBUG_ACKCNT_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT_NORMAL_FIELD;
+#define BBH_RX_DEBUG_COHERENCYCNT_NORMAL_FIELD_MASK  0x0000001f
+#define BBH_RX_DEBUG_COHERENCYCNT_NORMAL_FIELD_WIDTH 5
+#define BBH_RX_DEBUG_COHERENCYCNT_NORMAL_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_COHERENCYCNT_RESERVED0_FIELD_MASK  0x000000e0
+#define BBH_RX_DEBUG_COHERENCYCNT_RESERVED0_FIELD_WIDTH 3
+#define BBH_RX_DEBUG_COHERENCYCNT_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT_EXCLUSIVE_FIELD;
+#define BBH_RX_DEBUG_COHERENCYCNT_EXCLUSIVE_FIELD_MASK  0x00001f00
+#define BBH_RX_DEBUG_COHERENCYCNT_EXCLUSIVE_FIELD_WIDTH 5
+#define BBH_RX_DEBUG_COHERENCYCNT_EXCLUSIVE_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_COHERENCYCNT_RESERVED1_FIELD_MASK  0xffffe000
+#define BBH_RX_DEBUG_COHERENCYCNT_RESERVED1_FIELD_WIDTH 19
+#define BBH_RX_DEBUG_COHERENCYCNT_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec BBH_RX_DEBUG_DBGVEC_DBGVEC_FIELD;
+#define BBH_RX_DEBUG_DBGVEC_DBGVEC_FIELD_MASK  0x001fffff
+#define BBH_RX_DEBUG_DBGVEC_DBGVEC_FIELD_WIDTH 21
+#define BBH_RX_DEBUG_DBGVEC_DBGVEC_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_DBGVEC_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_DBGVEC_RESERVED0_FIELD_MASK  0xffe00000
+#define BBH_RX_DEBUG_DBGVEC_RESERVED0_FIELD_WIDTH 11
+#define BBH_RX_DEBUG_DBGVEC_RESERVED0_FIELD_SHIFT 21
+
+extern const ru_field_rec BBH_RX_DEBUG_UFUW_UW_FIELD;
+#define BBH_RX_DEBUG_UFUW_UW_FIELD_MASK  0x00000007
+#define BBH_RX_DEBUG_UFUW_UW_FIELD_WIDTH 3
+#define BBH_RX_DEBUG_UFUW_UW_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_UFUW_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_UFUW_RESERVED0_FIELD_MASK  0xfffffff8
+#define BBH_RX_DEBUG_UFUW_RESERVED0_FIELD_WIDTH 29
+#define BBH_RX_DEBUG_UFUW_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_RX_DEBUG_CREDITCNT_NORMAL_FIELD;
+#define BBH_RX_DEBUG_CREDITCNT_NORMAL_FIELD_MASK  0x0000001f
+#define BBH_RX_DEBUG_CREDITCNT_NORMAL_FIELD_WIDTH 5
+#define BBH_RX_DEBUG_CREDITCNT_NORMAL_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_CREDITCNT_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_CREDITCNT_RESERVED0_FIELD_MASK  0x000000e0
+#define BBH_RX_DEBUG_CREDITCNT_RESERVED0_FIELD_WIDTH 3
+#define BBH_RX_DEBUG_CREDITCNT_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec BBH_RX_DEBUG_CREDITCNT_EXCLUSIVE_FIELD;
+#define BBH_RX_DEBUG_CREDITCNT_EXCLUSIVE_FIELD_MASK  0x00001f00
+#define BBH_RX_DEBUG_CREDITCNT_EXCLUSIVE_FIELD_WIDTH 5
+#define BBH_RX_DEBUG_CREDITCNT_EXCLUSIVE_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_DEBUG_CREDITCNT_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_CREDITCNT_RESERVED1_FIELD_MASK  0xffffe000
+#define BBH_RX_DEBUG_CREDITCNT_RESERVED1_FIELD_WIDTH 19
+#define BBH_RX_DEBUG_CREDITCNT_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec BBH_RX_DEBUG_SDMACNT_UCD_FIELD;
+#define BBH_RX_DEBUG_SDMACNT_UCD_FIELD_MASK  0x0000007f
+#define BBH_RX_DEBUG_SDMACNT_UCD_FIELD_WIDTH 7
+#define BBH_RX_DEBUG_SDMACNT_UCD_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_SDMACNT_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_SDMACNT_RESERVED0_FIELD_MASK  0xffffff80
+#define BBH_RX_DEBUG_SDMACNT_RESERVED0_FIELD_WIDTH 25
+#define BBH_RX_DEBUG_SDMACNT_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec BBH_RX_DEBUG_CMFUW_UW_FIELD;
+#define BBH_RX_DEBUG_CMFUW_UW_FIELD_MASK  0x00000007
+#define BBH_RX_DEBUG_CMFUW_UW_FIELD_WIDTH 3
+#define BBH_RX_DEBUG_CMFUW_UW_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_CMFUW_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_CMFUW_RESERVED0_FIELD_MASK  0xfffffff8
+#define BBH_RX_DEBUG_CMFUW_RESERVED0_FIELD_WIDTH 29
+#define BBH_RX_DEBUG_CMFUW_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec BBH_RX_DEBUG_SBNFIFO_BNENTRY_FIELD;
+#define BBH_RX_DEBUG_SBNFIFO_BNENTRY_FIELD_MASK  0x00003fff
+#define BBH_RX_DEBUG_SBNFIFO_BNENTRY_FIELD_WIDTH 14
+#define BBH_RX_DEBUG_SBNFIFO_BNENTRY_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_SBNFIFO_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_SBNFIFO_RESERVED0_FIELD_MASK  0x0000c000
+#define BBH_RX_DEBUG_SBNFIFO_RESERVED0_FIELD_WIDTH 2
+#define BBH_RX_DEBUG_SBNFIFO_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec BBH_RX_DEBUG_SBNFIFO_VALID_FIELD;
+#define BBH_RX_DEBUG_SBNFIFO_VALID_FIELD_MASK  0x00010000
+#define BBH_RX_DEBUG_SBNFIFO_VALID_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_SBNFIFO_VALID_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_DEBUG_SBNFIFO_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_SBNFIFO_RESERVED1_FIELD_MASK  0xfffe0000
+#define BBH_RX_DEBUG_SBNFIFO_RESERVED1_FIELD_WIDTH 15
+#define BBH_RX_DEBUG_SBNFIFO_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec BBH_RX_DEBUG_CMDFIFO_CMDENTRY_FIELD;
+#define BBH_RX_DEBUG_CMDFIFO_CMDENTRY_FIELD_MASK  0xffffffff
+#define BBH_RX_DEBUG_CMDFIFO_CMDENTRY_FIELD_WIDTH 32
+#define BBH_RX_DEBUG_CMDFIFO_CMDENTRY_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_SBNRECYCLEFIFO_BNENTRY_FIELD;
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_BNENTRY_FIELD_MASK  0x00003fff
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_BNENTRY_FIELD_WIDTH 14
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_BNENTRY_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED0_FIELD_MASK  0x0000c000
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED0_FIELD_WIDTH 2
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec BBH_RX_DEBUG_SBNRECYCLEFIFO_VALID_FIELD;
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_VALID_FIELD_MASK  0x00010000
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_VALID_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_VALID_FIELD_SHIFT 16
+
+extern const ru_field_rec BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED1_FIELD_MASK  0xfffe0000
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED1_FIELD_WIDTH 15
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT2_CDSENT_FIELD;
+#define BBH_RX_DEBUG_COHERENCYCNT2_CDSENT_FIELD_MASK  0x0000007f
+#define BBH_RX_DEBUG_COHERENCYCNT2_CDSENT_FIELD_WIDTH 7
+#define BBH_RX_DEBUG_COHERENCYCNT2_CDSENT_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT2_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED0_FIELD_MASK  0x00000080
+#define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED0_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT2_ACKRECEIVED_FIELD;
+#define BBH_RX_DEBUG_COHERENCYCNT2_ACKRECEIVED_FIELD_MASK  0x00007f00
+#define BBH_RX_DEBUG_COHERENCYCNT2_ACKRECEIVED_FIELD_WIDTH 7
+#define BBH_RX_DEBUG_COHERENCYCNT2_ACKRECEIVED_FIELD_SHIFT 8
+
+extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT2_RESERVED1_FIELD;
+#define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED1_FIELD_MASK  0xffff8000
+#define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED1_FIELD_WIDTH 17
+#define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED1_FIELD_SHIFT 15
+
+extern const ru_field_rec BBH_RX_DEBUG_DROPSTATUS_DISPSTATUS_FIELD;
+#define BBH_RX_DEBUG_DROPSTATUS_DISPSTATUS_FIELD_MASK  0x00000001
+#define BBH_RX_DEBUG_DROPSTATUS_DISPSTATUS_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_DROPSTATUS_DISPSTATUS_FIELD_SHIFT 0
+
+extern const ru_field_rec BBH_RX_DEBUG_DROPSTATUS_SDMASTATUS_FIELD;
+#define BBH_RX_DEBUG_DROPSTATUS_SDMASTATUS_FIELD_MASK  0x00000002
+#define BBH_RX_DEBUG_DROPSTATUS_SDMASTATUS_FIELD_WIDTH 1
+#define BBH_RX_DEBUG_DROPSTATUS_SDMASTATUS_FIELD_SHIFT 1
+
+extern const ru_field_rec BBH_RX_DEBUG_DROPSTATUS_RESERVED0_FIELD;
+#define BBH_RX_DEBUG_DROPSTATUS_RESERVED0_FIELD_MASK  0xfffffffc
+#define BBH_RX_DEBUG_DROPSTATUS_RESERVED0_FIELD_WIDTH 30
+#define BBH_RX_DEBUG_DROPSTATUS_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec UBUS_MSTR_EN_EN_FIELD;
+#define UBUS_MSTR_EN_EN_FIELD_MASK  0x00000001
+#define UBUS_MSTR_EN_EN_FIELD_WIDTH 1
+#define UBUS_MSTR_EN_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_MSTR_EN_RESERVED0_FIELD;
+#define UBUS_MSTR_EN_RESERVED0_FIELD_MASK  0xfffffffe
+#define UBUS_MSTR_EN_RESERVED0_FIELD_WIDTH 31
+#define UBUS_MSTR_EN_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec UBUS_MSTR_HYST_CTRL_CMD_SPACE_FIELD;
+#define UBUS_MSTR_HYST_CTRL_CMD_SPACE_FIELD_MASK  0x000003ff
+#define UBUS_MSTR_HYST_CTRL_CMD_SPACE_FIELD_WIDTH 10
+#define UBUS_MSTR_HYST_CTRL_CMD_SPACE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_MSTR_HYST_CTRL_RESERVED0_FIELD;
+#define UBUS_MSTR_HYST_CTRL_RESERVED0_FIELD_MASK  0x0000fc00
+#define UBUS_MSTR_HYST_CTRL_RESERVED0_FIELD_WIDTH 6
+#define UBUS_MSTR_HYST_CTRL_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec UBUS_MSTR_HYST_CTRL_DATA_SPACE_FIELD;
+#define UBUS_MSTR_HYST_CTRL_DATA_SPACE_FIELD_MASK  0x03ff0000
+#define UBUS_MSTR_HYST_CTRL_DATA_SPACE_FIELD_WIDTH 10
+#define UBUS_MSTR_HYST_CTRL_DATA_SPACE_FIELD_SHIFT 16
+
+extern const ru_field_rec UBUS_MSTR_HYST_CTRL_RESERVED1_FIELD;
+#define UBUS_MSTR_HYST_CTRL_RESERVED1_FIELD_MASK  0xfc000000
+#define UBUS_MSTR_HYST_CTRL_RESERVED1_FIELD_WIDTH 6
+#define UBUS_MSTR_HYST_CTRL_RESERVED1_FIELD_SHIFT 26
+
+extern const ru_field_rec UBUS_MSTR_HP_HP_EN_FIELD;
+#define UBUS_MSTR_HP_HP_EN_FIELD_MASK  0x00000001
+#define UBUS_MSTR_HP_HP_EN_FIELD_WIDTH 1
+#define UBUS_MSTR_HP_HP_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_MSTR_HP_RESERVED0_FIELD;
+#define UBUS_MSTR_HP_RESERVED0_FIELD_MASK  0xfffffffe
+#define UBUS_MSTR_HP_RESERVED0_FIELD_WIDTH 31
+#define UBUS_MSTR_HP_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec UBUS_SLV_VPB_BASE_BASE_FIELD;
+#define UBUS_SLV_VPB_BASE_BASE_FIELD_MASK  0xffffffff
+#define UBUS_SLV_VPB_BASE_BASE_FIELD_WIDTH 32
+#define UBUS_SLV_VPB_BASE_BASE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_VPB_MASK_MASK_FIELD;
+#define UBUS_SLV_VPB_MASK_MASK_FIELD_MASK  0xffffffff
+#define UBUS_SLV_VPB_MASK_MASK_FIELD_WIDTH 32
+#define UBUS_SLV_VPB_MASK_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_APB_BASE_BASE_FIELD;
+#define UBUS_SLV_APB_BASE_BASE_FIELD_MASK  0xffffffff
+#define UBUS_SLV_APB_BASE_BASE_FIELD_WIDTH 32
+#define UBUS_SLV_APB_BASE_BASE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_APB_MASK_MASK_FIELD;
+#define UBUS_SLV_APB_MASK_MASK_FIELD_MASK  0xffffffff
+#define UBUS_SLV_APB_MASK_MASK_FIELD_WIDTH 32
+#define UBUS_SLV_APB_MASK_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_DEVICE_0_BASE_BASE_FIELD;
+#define UBUS_SLV_DEVICE_0_BASE_BASE_FIELD_MASK  0xffffffff
+#define UBUS_SLV_DEVICE_0_BASE_BASE_FIELD_WIDTH 32
+#define UBUS_SLV_DEVICE_0_BASE_BASE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_DEVICE_0_MASK_MASK_FIELD;
+#define UBUS_SLV_DEVICE_0_MASK_MASK_FIELD_MASK  0xffffffff
+#define UBUS_SLV_DEVICE_0_MASK_MASK_FIELD_WIDTH 32
+#define UBUS_SLV_DEVICE_0_MASK_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_DEVICE_1_BASE_BASE_FIELD;
+#define UBUS_SLV_DEVICE_1_BASE_BASE_FIELD_MASK  0xffffffff
+#define UBUS_SLV_DEVICE_1_BASE_BASE_FIELD_WIDTH 32
+#define UBUS_SLV_DEVICE_1_BASE_BASE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_DEVICE_1_MASK_MASK_FIELD;
+#define UBUS_SLV_DEVICE_1_MASK_MASK_FIELD_MASK  0xffffffff
+#define UBUS_SLV_DEVICE_1_MASK_MASK_FIELD_WIDTH 32
+#define UBUS_SLV_DEVICE_1_MASK_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_DEVICE_2_BASE_BASE_FIELD;
+#define UBUS_SLV_DEVICE_2_BASE_BASE_FIELD_MASK  0xffffffff
+#define UBUS_SLV_DEVICE_2_BASE_BASE_FIELD_WIDTH 32
+#define UBUS_SLV_DEVICE_2_BASE_BASE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_DEVICE_2_MASK_MASK_FIELD;
+#define UBUS_SLV_DEVICE_2_MASK_MASK_FIELD_MASK  0xffffffff
+#define UBUS_SLV_DEVICE_2_MASK_MASK_FIELD_WIDTH 32
+#define UBUS_SLV_DEVICE_2_MASK_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_RNR_INTR_CTRL_ISR_IST_FIELD;
+#define UBUS_SLV_RNR_INTR_CTRL_ISR_IST_FIELD_MASK  0xffffffff
+#define UBUS_SLV_RNR_INTR_CTRL_ISR_IST_FIELD_WIDTH 32
+#define UBUS_SLV_RNR_INTR_CTRL_ISR_IST_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_RNR_INTR_CTRL_ISM_ISM_FIELD;
+#define UBUS_SLV_RNR_INTR_CTRL_ISM_ISM_FIELD_MASK  0xffffffff
+#define UBUS_SLV_RNR_INTR_CTRL_ISM_ISM_FIELD_WIDTH 32
+#define UBUS_SLV_RNR_INTR_CTRL_ISM_ISM_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_RNR_INTR_CTRL_IER_IEM_FIELD;
+#define UBUS_SLV_RNR_INTR_CTRL_IER_IEM_FIELD_MASK  0xffffffff
+#define UBUS_SLV_RNR_INTR_CTRL_IER_IEM_FIELD_WIDTH 32
+#define UBUS_SLV_RNR_INTR_CTRL_IER_IEM_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_RNR_INTR_CTRL_ITR_IST_FIELD;
+#define UBUS_SLV_RNR_INTR_CTRL_ITR_IST_FIELD_MASK  0xffffffff
+#define UBUS_SLV_RNR_INTR_CTRL_ITR_IST_FIELD_WIDTH 32
+#define UBUS_SLV_RNR_INTR_CTRL_ITR_IST_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_PROFILING_CFG_COUNTER_ENABLE_FIELD;
+#define UBUS_SLV_PROFILING_CFG_COUNTER_ENABLE_FIELD_MASK  0x00000001
+#define UBUS_SLV_PROFILING_CFG_COUNTER_ENABLE_FIELD_WIDTH 1
+#define UBUS_SLV_PROFILING_CFG_COUNTER_ENABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_PROFILING_CFG_PROFILING_START_FIELD;
+#define UBUS_SLV_PROFILING_CFG_PROFILING_START_FIELD_MASK  0x00000002
+#define UBUS_SLV_PROFILING_CFG_PROFILING_START_FIELD_WIDTH 1
+#define UBUS_SLV_PROFILING_CFG_PROFILING_START_FIELD_SHIFT 1
+
+extern const ru_field_rec UBUS_SLV_PROFILING_CFG_MANUAL_STOP_MODE_FIELD;
+#define UBUS_SLV_PROFILING_CFG_MANUAL_STOP_MODE_FIELD_MASK  0x00000004
+#define UBUS_SLV_PROFILING_CFG_MANUAL_STOP_MODE_FIELD_WIDTH 1
+#define UBUS_SLV_PROFILING_CFG_MANUAL_STOP_MODE_FIELD_SHIFT 2
+
+extern const ru_field_rec UBUS_SLV_PROFILING_CFG_DO_MANUAL_STOP_FIELD;
+#define UBUS_SLV_PROFILING_CFG_DO_MANUAL_STOP_FIELD_MASK  0x00000008
+#define UBUS_SLV_PROFILING_CFG_DO_MANUAL_STOP_FIELD_WIDTH 1
+#define UBUS_SLV_PROFILING_CFG_DO_MANUAL_STOP_FIELD_SHIFT 3
+
+extern const ru_field_rec UBUS_SLV_PROFILING_CFG_RESERVED0_FIELD;
+#define UBUS_SLV_PROFILING_CFG_RESERVED0_FIELD_MASK  0xfffffff0
+#define UBUS_SLV_PROFILING_CFG_RESERVED0_FIELD_WIDTH 28
+#define UBUS_SLV_PROFILING_CFG_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec UBUS_SLV_PROFILING_STATUS_PROFILING_ON_FIELD;
+#define UBUS_SLV_PROFILING_STATUS_PROFILING_ON_FIELD_MASK  0x00000001
+#define UBUS_SLV_PROFILING_STATUS_PROFILING_ON_FIELD_WIDTH 1
+#define UBUS_SLV_PROFILING_STATUS_PROFILING_ON_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_PROFILING_STATUS_CYCLES_COUNTER_FIELD;
+#define UBUS_SLV_PROFILING_STATUS_CYCLES_COUNTER_FIELD_MASK  0xfffffffe
+#define UBUS_SLV_PROFILING_STATUS_CYCLES_COUNTER_FIELD_WIDTH 31
+#define UBUS_SLV_PROFILING_STATUS_CYCLES_COUNTER_FIELD_SHIFT 1
+
+extern const ru_field_rec UBUS_SLV_PROFILING_COUNTER_VAL_FIELD;
+#define UBUS_SLV_PROFILING_COUNTER_VAL_FIELD_MASK  0xffffffff
+#define UBUS_SLV_PROFILING_COUNTER_VAL_FIELD_WIDTH 32
+#define UBUS_SLV_PROFILING_COUNTER_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_PROFILING_START_VALUE_VAL_FIELD;
+#define UBUS_SLV_PROFILING_START_VALUE_VAL_FIELD_MASK  0xffffffff
+#define UBUS_SLV_PROFILING_START_VALUE_VAL_FIELD_WIDTH 32
+#define UBUS_SLV_PROFILING_START_VALUE_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_PROFILING_STOP_VALUE_VAL_FIELD;
+#define UBUS_SLV_PROFILING_STOP_VALUE_VAL_FIELD_MASK  0xffffffff
+#define UBUS_SLV_PROFILING_STOP_VALUE_VAL_FIELD_WIDTH 32
+#define UBUS_SLV_PROFILING_STOP_VALUE_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_PROFILING_CYCLE_NUM_PROFILING_CYCLES_NUM_FIELD;
+#define UBUS_SLV_PROFILING_CYCLE_NUM_PROFILING_CYCLES_NUM_FIELD_MASK  0xffffffff
+#define UBUS_SLV_PROFILING_CYCLE_NUM_PROFILING_CYCLES_NUM_FIELD_WIDTH 32
+#define UBUS_SLV_PROFILING_CYCLE_NUM_PROFILING_CYCLES_NUM_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_RX_ACT_EN_FIELD;
+#define UBUS_SLV_LED_CNTRL_RX_ACT_EN_FIELD_MASK  0x00000001
+#define UBUS_SLV_LED_CNTRL_RX_ACT_EN_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_RX_ACT_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_TX_ACT_EN_FIELD;
+#define UBUS_SLV_LED_CNTRL_TX_ACT_EN_FIELD_MASK  0x00000002
+#define UBUS_SLV_LED_CNTRL_TX_ACT_EN_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_TX_ACT_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD;
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_MASK  0x00000004
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_SHIFT 2
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD;
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_MASK  0x00000008
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_SHIFT 3
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD;
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_MASK  0x00000010
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_SHIFT 4
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_ACT_LED_ACT_SEL_FIELD;
+#define UBUS_SLV_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_MASK  0x00000020
+#define UBUS_SLV_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_SHIFT 5
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD;
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_MASK  0x00000040
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_SHIFT 6
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD;
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_MASK  0x00000080
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD;
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_MASK  0x00000100
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_SHIFT 8
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_ACT_LED_POL_SEL_FIELD;
+#define UBUS_SLV_LED_CNTRL_ACT_LED_POL_SEL_FIELD_MASK  0x00000200
+#define UBUS_SLV_LED_CNTRL_ACT_LED_POL_SEL_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_ACT_LED_POL_SEL_FIELD_SHIFT 9
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_LED_SPD_OVRD_FIELD;
+#define UBUS_SLV_LED_CNTRL_LED_SPD_OVRD_FIELD_MASK  0x00001c00
+#define UBUS_SLV_LED_CNTRL_LED_SPD_OVRD_FIELD_WIDTH 3
+#define UBUS_SLV_LED_CNTRL_LED_SPD_OVRD_FIELD_SHIFT 10
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_LNK_STATUS_OVRD_FIELD;
+#define UBUS_SLV_LED_CNTRL_LNK_STATUS_OVRD_FIELD_MASK  0x00002000
+#define UBUS_SLV_LED_CNTRL_LNK_STATUS_OVRD_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_LNK_STATUS_OVRD_FIELD_SHIFT 13
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_SPD_OVRD_EN_FIELD;
+#define UBUS_SLV_LED_CNTRL_SPD_OVRD_EN_FIELD_MASK  0x00004000
+#define UBUS_SLV_LED_CNTRL_SPD_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_SPD_OVRD_EN_FIELD_SHIFT 14
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_LNK_OVRD_EN_FIELD;
+#define UBUS_SLV_LED_CNTRL_LNK_OVRD_EN_FIELD_MASK  0x00008000
+#define UBUS_SLV_LED_CNTRL_LNK_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV_LED_CNTRL_LNK_OVRD_EN_FIELD_SHIFT 15
+
+extern const ru_field_rec UBUS_SLV_LED_CNTRL_R1_FIELD;
+#define UBUS_SLV_LED_CNTRL_R1_FIELD_MASK  0xffff0000
+#define UBUS_SLV_LED_CNTRL_R1_FIELD_WIDTH 16
+#define UBUS_SLV_LED_CNTRL_R1_FIELD_SHIFT 16
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_MASK  0x00000007
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_MASK  0x00000038
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_SHIFT 3
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_MASK  0x000001c0
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_SHIFT 6
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_MASK  0x00000e00
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_SHIFT 9
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_MASK  0x00007000
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_SHIFT 12
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_MASK  0x00038000
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_SHIFT 15
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_MASK  0x001c0000
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED1_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED1_FIELD_MASK  0x00e00000
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED1_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED1_FIELD_SHIFT 21
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_R1_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_R1_FIELD_MASK  0xff000000
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_R1_FIELD_WIDTH 8
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_R1_FIELD_SHIFT 24
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_MASK  0x00000007
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_MASK  0x00000038
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_SHIFT 3
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_MASK  0x000001c0
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_SHIFT 6
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_MASK  0x00000e00
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_SHIFT 9
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_MASK  0x00007000
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_SHIFT 12
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_MASK  0x00038000
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_SHIFT 15
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_MASK  0x001c0000
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_RESERVED1_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_RESERVED1_FIELD_MASK  0x00e00000
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_RESERVED1_FIELD_WIDTH 3
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_RESERVED1_FIELD_SHIFT 21
+
+extern const ru_field_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_R1_FIELD;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_R1_FIELD_MASK  0xff000000
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_R1_FIELD_WIDTH 8
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_R1_FIELD_SHIFT 24
+
+extern const ru_field_rec UBUS_SLV_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD;
+#define UBUS_SLV_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_MASK  0x0000ffff
+#define UBUS_SLV_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_WIDTH 16
+#define UBUS_SLV_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD;
+#define UBUS_SLV_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_MASK  0xffff0000
+#define UBUS_SLV_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_WIDTH 16
+#define UBUS_SLV_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_SHIFT 16
+
+extern const ru_field_rec UBUS_SLV_LED_PWM_CNTRL_PWM_ENABLE_FIELD;
+#define UBUS_SLV_LED_PWM_CNTRL_PWM_ENABLE_FIELD_MASK  0x00000001
+#define UBUS_SLV_LED_PWM_CNTRL_PWM_ENABLE_FIELD_WIDTH 1
+#define UBUS_SLV_LED_PWM_CNTRL_PWM_ENABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_LED_PWM_CNTRL_PWM_POLARITY_FIELD;
+#define UBUS_SLV_LED_PWM_CNTRL_PWM_POLARITY_FIELD_MASK  0x00000002
+#define UBUS_SLV_LED_PWM_CNTRL_PWM_POLARITY_FIELD_WIDTH 1
+#define UBUS_SLV_LED_PWM_CNTRL_PWM_POLARITY_FIELD_SHIFT 1
+
+extern const ru_field_rec UBUS_SLV_LED_PWM_CNTRL_R1_FIELD;
+#define UBUS_SLV_LED_PWM_CNTRL_R1_FIELD_MASK  0xfffffffc
+#define UBUS_SLV_LED_PWM_CNTRL_R1_FIELD_WIDTH 30
+#define UBUS_SLV_LED_PWM_CNTRL_R1_FIELD_SHIFT 2
+
+extern const ru_field_rec UBUS_SLV_LED_INTENSITY_CNTRL_LED_ON_HIGH_FIELD;
+#define UBUS_SLV_LED_INTENSITY_CNTRL_LED_ON_HIGH_FIELD_MASK  0x0000ffff
+#define UBUS_SLV_LED_INTENSITY_CNTRL_LED_ON_HIGH_FIELD_WIDTH 16
+#define UBUS_SLV_LED_INTENSITY_CNTRL_LED_ON_HIGH_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_LED_INTENSITY_CNTRL_LED_ON_LOW_FIELD;
+#define UBUS_SLV_LED_INTENSITY_CNTRL_LED_ON_LOW_FIELD_MASK  0xffff0000
+#define UBUS_SLV_LED_INTENSITY_CNTRL_LED_ON_LOW_FIELD_WIDTH 16
+#define UBUS_SLV_LED_INTENSITY_CNTRL_LED_ON_LOW_FIELD_SHIFT 16
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_CNTRL_PORT_EN_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_MASK  0x0000ffff
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_WIDTH 16
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_MASK  0x00010000
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_WIDTH 1
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_SHIFT 16
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_MASK  0x00020000
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_WIDTH 1
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_SHIFT 17
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_MASK  0x00040000
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_WIDTH 1
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_CNTRL_R1_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_R1_FIELD_MASK  0xfff80000
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_R1_FIELD_WIDTH 13
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_R1_FIELD_SHIFT 19
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_MASK  0x0000ffff
+#define UBUS_SLV_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_WIDTH 16
+#define UBUS_SLV_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_MASK  0xffff0000
+#define UBUS_SLV_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_WIDTH 16
+#define UBUS_SLV_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_SHIFT 16
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_PWM_ENABLE_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_PWM_ENABLE_FIELD_MASK  0x00000001
+#define UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_PWM_ENABLE_FIELD_WIDTH 1
+#define UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_PWM_ENABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_PWM_POLARITY_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_PWM_POLARITY_FIELD_MASK  0x00000002
+#define UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_PWM_POLARITY_FIELD_WIDTH 1
+#define UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_PWM_POLARITY_FIELD_SHIFT 1
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_R1_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_R1_FIELD_MASK  0xfffffffc
+#define UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_R1_FIELD_WIDTH 30
+#define UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_R1_FIELD_SHIFT 2
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_INTENSITY_CNTRL_LED_ON_HIGH_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_INTENSITY_CNTRL_LED_ON_HIGH_FIELD_MASK  0x0000ffff
+#define UBUS_SLV_AGGREGATE_LED_INTENSITY_CNTRL_LED_ON_HIGH_FIELD_WIDTH 16
+#define UBUS_SLV_AGGREGATE_LED_INTENSITY_CNTRL_LED_ON_HIGH_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_AGGREGATE_LED_INTENSITY_CNTRL_LED_ON_LOW_FIELD;
+#define UBUS_SLV_AGGREGATE_LED_INTENSITY_CNTRL_LED_ON_LOW_FIELD_MASK  0xffff0000
+#define UBUS_SLV_AGGREGATE_LED_INTENSITY_CNTRL_LED_ON_LOW_FIELD_WIDTH 16
+#define UBUS_SLV_AGGREGATE_LED_INTENSITY_CNTRL_LED_ON_LOW_FIELD_SHIFT 16
+
+extern const ru_field_rec UBUS_SLV_SW_INIT_CNTRL_SW_INIT_FIELD;
+#define UBUS_SLV_SW_INIT_CNTRL_SW_INIT_FIELD_MASK  0x00000001
+#define UBUS_SLV_SW_INIT_CNTRL_SW_INIT_FIELD_WIDTH 1
+#define UBUS_SLV_SW_INIT_CNTRL_SW_INIT_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV_SW_INIT_CNTRL_RESERVED0_FIELD;
+#define UBUS_SLV_SW_INIT_CNTRL_RESERVED0_FIELD_MASK  0xfffffffe
+#define UBUS_SLV_SW_INIT_CNTRL_RESERVED0_FIELD_WIDTH 31
+#define UBUS_SLV_SW_INIT_CNTRL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec UBUS_SLV__CNTRL_RGMII_MODE_EN_FIELD;
+#define UBUS_SLV__CNTRL_RGMII_MODE_EN_FIELD_MASK  0x00000001
+#define UBUS_SLV__CNTRL_RGMII_MODE_EN_FIELD_WIDTH 1
+#define UBUS_SLV__CNTRL_RGMII_MODE_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__CNTRL_ID_MODE_DIS_FIELD;
+#define UBUS_SLV__CNTRL_ID_MODE_DIS_FIELD_MASK  0x00000002
+#define UBUS_SLV__CNTRL_ID_MODE_DIS_FIELD_WIDTH 1
+#define UBUS_SLV__CNTRL_ID_MODE_DIS_FIELD_SHIFT 1
+
+extern const ru_field_rec UBUS_SLV__CNTRL_PORT_MODE_FIELD;
+#define UBUS_SLV__CNTRL_PORT_MODE_FIELD_MASK  0x0000001c
+#define UBUS_SLV__CNTRL_PORT_MODE_FIELD_WIDTH 3
+#define UBUS_SLV__CNTRL_PORT_MODE_FIELD_SHIFT 2
+
+extern const ru_field_rec UBUS_SLV__CNTRL_RVMII_REF_SEL_FIELD;
+#define UBUS_SLV__CNTRL_RVMII_REF_SEL_FIELD_MASK  0x00000020
+#define UBUS_SLV__CNTRL_RVMII_REF_SEL_FIELD_WIDTH 1
+#define UBUS_SLV__CNTRL_RVMII_REF_SEL_FIELD_SHIFT 5
+
+extern const ru_field_rec UBUS_SLV__CNTRL_RX_PAUSE_EN_FIELD;
+#define UBUS_SLV__CNTRL_RX_PAUSE_EN_FIELD_MASK  0x00000040
+#define UBUS_SLV__CNTRL_RX_PAUSE_EN_FIELD_WIDTH 1
+#define UBUS_SLV__CNTRL_RX_PAUSE_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec UBUS_SLV__CNTRL_TX_PAUSE_EN_FIELD;
+#define UBUS_SLV__CNTRL_TX_PAUSE_EN_FIELD_MASK  0x00000080
+#define UBUS_SLV__CNTRL_TX_PAUSE_EN_FIELD_WIDTH 1
+#define UBUS_SLV__CNTRL_TX_PAUSE_EN_FIELD_SHIFT 7
+
+extern const ru_field_rec UBUS_SLV__CNTRL_TX_CLK_STOP_EN_FIELD;
+#define UBUS_SLV__CNTRL_TX_CLK_STOP_EN_FIELD_MASK  0x00000100
+#define UBUS_SLV__CNTRL_TX_CLK_STOP_EN_FIELD_WIDTH 1
+#define UBUS_SLV__CNTRL_TX_CLK_STOP_EN_FIELD_SHIFT 8
+
+extern const ru_field_rec UBUS_SLV__CNTRL_LPI_COUNT_FIELD;
+#define UBUS_SLV__CNTRL_LPI_COUNT_FIELD_MASK  0x00003e00
+#define UBUS_SLV__CNTRL_LPI_COUNT_FIELD_WIDTH 5
+#define UBUS_SLV__CNTRL_LPI_COUNT_FIELD_SHIFT 9
+
+extern const ru_field_rec UBUS_SLV__CNTRL_RX_ERR_MASK_FIELD;
+#define UBUS_SLV__CNTRL_RX_ERR_MASK_FIELD_MASK  0x00004000
+#define UBUS_SLV__CNTRL_RX_ERR_MASK_FIELD_WIDTH 1
+#define UBUS_SLV__CNTRL_RX_ERR_MASK_FIELD_SHIFT 14
+
+extern const ru_field_rec UBUS_SLV__CNTRL_COL_CRS_MASK_FIELD;
+#define UBUS_SLV__CNTRL_COL_CRS_MASK_FIELD_MASK  0x00008000
+#define UBUS_SLV__CNTRL_COL_CRS_MASK_FIELD_WIDTH 1
+#define UBUS_SLV__CNTRL_COL_CRS_MASK_FIELD_SHIFT 15
+
+extern const ru_field_rec UBUS_SLV__CNTRL_PSEUDO_HD_MODE_EN_FIELD;
+#define UBUS_SLV__CNTRL_PSEUDO_HD_MODE_EN_FIELD_MASK  0x00010000
+#define UBUS_SLV__CNTRL_PSEUDO_HD_MODE_EN_FIELD_WIDTH 1
+#define UBUS_SLV__CNTRL_PSEUDO_HD_MODE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec UBUS_SLV__CNTRL_RESERVED0_FIELD;
+#define UBUS_SLV__CNTRL_RESERVED0_FIELD_MASK  0xfffe0000
+#define UBUS_SLV__CNTRL_RESERVED0_FIELD_WIDTH 15
+#define UBUS_SLV__CNTRL_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec UBUS_SLV__IB_STATUS_SPEED_DECODE_FIELD;
+#define UBUS_SLV__IB_STATUS_SPEED_DECODE_FIELD_MASK  0x00000003
+#define UBUS_SLV__IB_STATUS_SPEED_DECODE_FIELD_WIDTH 2
+#define UBUS_SLV__IB_STATUS_SPEED_DECODE_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__IB_STATUS_DUPLEX_DECODE_FIELD;
+#define UBUS_SLV__IB_STATUS_DUPLEX_DECODE_FIELD_MASK  0x00000004
+#define UBUS_SLV__IB_STATUS_DUPLEX_DECODE_FIELD_WIDTH 1
+#define UBUS_SLV__IB_STATUS_DUPLEX_DECODE_FIELD_SHIFT 2
+
+extern const ru_field_rec UBUS_SLV__IB_STATUS_LINK_DECODE_FIELD;
+#define UBUS_SLV__IB_STATUS_LINK_DECODE_FIELD_MASK  0x00000008
+#define UBUS_SLV__IB_STATUS_LINK_DECODE_FIELD_WIDTH 1
+#define UBUS_SLV__IB_STATUS_LINK_DECODE_FIELD_SHIFT 3
+
+extern const ru_field_rec UBUS_SLV__IB_STATUS_IB_STATUS_OVRD_FIELD;
+#define UBUS_SLV__IB_STATUS_IB_STATUS_OVRD_FIELD_MASK  0x00000010
+#define UBUS_SLV__IB_STATUS_IB_STATUS_OVRD_FIELD_WIDTH 1
+#define UBUS_SLV__IB_STATUS_IB_STATUS_OVRD_FIELD_SHIFT 4
+
+extern const ru_field_rec UBUS_SLV__IB_STATUS_RESERVED0_FIELD;
+#define UBUS_SLV__IB_STATUS_RESERVED0_FIELD_MASK  0xffffffe0
+#define UBUS_SLV__IB_STATUS_RESERVED0_FIELD_WIDTH 27
+#define UBUS_SLV__IB_STATUS_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_CTRI_FIELD;
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_MASK  0x00000003
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_WIDTH 2
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DRNG_FIELD;
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_MASK  0x0000000c
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_WIDTH 2
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_SHIFT 2
+
+extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD;
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_MASK  0x00000010
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_WIDTH 1
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_SHIFT 4
+
+extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD;
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_MASK  0x00000020
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_WIDTH 1
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_SHIFT 5
+
+extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD;
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_MASK  0x00000040
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_WIDTH 1
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_SHIFT 6
+
+extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD;
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_MASK  0x00000080
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_WIDTH 1
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_SHIFT 7
+
+extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESET_FIELD;
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESET_FIELD_MASK  0x00000100
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESET_FIELD_WIDTH 1
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESET_FIELD_SHIFT 8
+
+extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD;
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_MASK  0xfffffe00
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_WIDTH 23
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD;
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_MASK  0x000001ff
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD;
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_MASK  0x0003fe00
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_SHIFT 9
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD;
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_MASK  0x03fc0000
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_WIDTH 8
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD;
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_MASK  0x04000000
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_WIDTH 1
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_SHIFT 26
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD;
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_MASK  0x08000000
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_WIDTH 1
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_SHIFT 27
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD;
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_MASK  0xf0000000
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_WIDTH 4
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD;
+#define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_MASK  0x000001ff
+#define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD;
+#define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_MASK  0x0003fe00
+#define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_SHIFT 9
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_EXP_DATA_1_RESERVED0_FIELD;
+#define UBUS_SLV__ATE_RX_EXP_DATA_1_RESERVED0_FIELD_MASK  0xfffc0000
+#define UBUS_SLV__ATE_RX_EXP_DATA_1_RESERVED0_FIELD_WIDTH 14
+#define UBUS_SLV__ATE_RX_EXP_DATA_1_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD;
+#define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_MASK  0x000001ff
+#define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD;
+#define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_MASK  0x0003fe00
+#define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_SHIFT 9
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_0_RX_OK_FIELD;
+#define UBUS_SLV__ATE_RX_STATUS_0_RX_OK_FIELD_MASK  0x00040000
+#define UBUS_SLV__ATE_RX_STATUS_0_RX_OK_FIELD_WIDTH 1
+#define UBUS_SLV__ATE_RX_STATUS_0_RX_OK_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_0_RESERVED0_FIELD;
+#define UBUS_SLV__ATE_RX_STATUS_0_RESERVED0_FIELD_MASK  0xfff80000
+#define UBUS_SLV__ATE_RX_STATUS_0_RESERVED0_FIELD_WIDTH 13
+#define UBUS_SLV__ATE_RX_STATUS_0_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD;
+#define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_MASK  0x000001ff
+#define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD;
+#define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_MASK  0x0003fe00
+#define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_SHIFT 9
+
+extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_1_RESERVED0_FIELD;
+#define UBUS_SLV__ATE_RX_STATUS_1_RESERVED0_FIELD_MASK  0xfffc0000
+#define UBUS_SLV__ATE_RX_STATUS_1_RESERVED0_FIELD_WIDTH 14
+#define UBUS_SLV__ATE_RX_STATUS_1_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_START_STOP_OVRD_FIELD;
+#define UBUS_SLV__ATE_TX_CNTRL_START_STOP_OVRD_FIELD_MASK  0x00000001
+#define UBUS_SLV__ATE_TX_CNTRL_START_STOP_OVRD_FIELD_WIDTH 1
+#define UBUS_SLV__ATE_TX_CNTRL_START_STOP_OVRD_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_START_STOP_FIELD;
+#define UBUS_SLV__ATE_TX_CNTRL_START_STOP_FIELD_MASK  0x00000002
+#define UBUS_SLV__ATE_TX_CNTRL_START_STOP_FIELD_WIDTH 1
+#define UBUS_SLV__ATE_TX_CNTRL_START_STOP_FIELD_SHIFT 1
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_PKT_GEN_EN_FIELD;
+#define UBUS_SLV__ATE_TX_CNTRL_PKT_GEN_EN_FIELD_MASK  0x00000004
+#define UBUS_SLV__ATE_TX_CNTRL_PKT_GEN_EN_FIELD_WIDTH 1
+#define UBUS_SLV__ATE_TX_CNTRL_PKT_GEN_EN_FIELD_SHIFT 2
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_PKT_CNT_FIELD;
+#define UBUS_SLV__ATE_TX_CNTRL_PKT_CNT_FIELD_MASK  0x000007f8
+#define UBUS_SLV__ATE_TX_CNTRL_PKT_CNT_FIELD_WIDTH 8
+#define UBUS_SLV__ATE_TX_CNTRL_PKT_CNT_FIELD_SHIFT 3
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD;
+#define UBUS_SLV__ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_MASK  0x003ff800
+#define UBUS_SLV__ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_WIDTH 11
+#define UBUS_SLV__ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_SHIFT 11
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_PKT_IPG_FIELD;
+#define UBUS_SLV__ATE_TX_CNTRL_PKT_IPG_FIELD_MASK  0x0fc00000
+#define UBUS_SLV__ATE_TX_CNTRL_PKT_IPG_FIELD_WIDTH 6
+#define UBUS_SLV__ATE_TX_CNTRL_PKT_IPG_FIELD_SHIFT 22
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_RESERVED0_FIELD;
+#define UBUS_SLV__ATE_TX_CNTRL_RESERVED0_FIELD_MASK  0xf0000000
+#define UBUS_SLV__ATE_TX_CNTRL_RESERVED0_FIELD_WIDTH 4
+#define UBUS_SLV__ATE_TX_CNTRL_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_0_TX_DATA_0_FIELD;
+#define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_0_FIELD_MASK  0x000001ff
+#define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_0_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_0_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_0_TX_DATA_1_FIELD;
+#define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_1_FIELD_MASK  0x0003fe00
+#define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_1_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_1_FIELD_SHIFT 9
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_0_RESERVED0_FIELD;
+#define UBUS_SLV__ATE_TX_DATA_0_RESERVED0_FIELD_MASK  0xfffc0000
+#define UBUS_SLV__ATE_TX_DATA_0_RESERVED0_FIELD_WIDTH 14
+#define UBUS_SLV__ATE_TX_DATA_0_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_1_TX_DATA_2_FIELD;
+#define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_2_FIELD_MASK  0x000001ff
+#define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_2_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_2_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_1_TX_DATA_3_FIELD;
+#define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_3_FIELD_MASK  0x0003fe00
+#define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_3_FIELD_WIDTH 9
+#define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_3_FIELD_SHIFT 9
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_1_RESERVED0_FIELD;
+#define UBUS_SLV__ATE_TX_DATA_1_RESERVED0_FIELD_MASK  0xfffc0000
+#define UBUS_SLV__ATE_TX_DATA_1_RESERVED0_FIELD_WIDTH 14
+#define UBUS_SLV__ATE_TX_DATA_1_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_2_TX_DATA_4_FIELD;
+#define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_4_FIELD_MASK  0x000000ff
+#define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_4_FIELD_WIDTH 8
+#define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_4_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_2_TX_DATA_5_FIELD;
+#define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_5_FIELD_MASK  0x0000ff00
+#define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_5_FIELD_WIDTH 8
+#define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_5_FIELD_SHIFT 8
+
+extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_2_ETHER_TYPE_FIELD;
+#define UBUS_SLV__ATE_TX_DATA_2_ETHER_TYPE_FIELD_MASK  0xffff0000
+#define UBUS_SLV__ATE_TX_DATA_2_ETHER_TYPE_FIELD_WIDTH 16
+#define UBUS_SLV__ATE_TX_DATA_2_ETHER_TYPE_FIELD_SHIFT 16
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_MASK  0x0000000f
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED0_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED0_FIELD_MASK  0x00000030
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED0_FIELD_WIDTH 2
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_MASK  0x00000040
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_MASK  0x00000780
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED1_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED1_FIELD_MASK  0x00001800
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED1_FIELD_WIDTH 2
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED1_FIELD_SHIFT 11
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_MASK  0x00002000
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_SHIFT 13
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_MASK  0x0003c000
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_SHIFT 14
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED2_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED2_FIELD_MASK  0x000c0000
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED2_FIELD_WIDTH 2
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED2_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_MASK  0x00100000
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_SHIFT 20
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_MASK  0x01e00000
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_SHIFT 21
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED3_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED3_FIELD_MASK  0x06000000
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED3_FIELD_WIDTH 2
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED3_FIELD_SHIFT 25
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_MASK  0x08000000
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_SHIFT 27
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED4_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED4_FIELD_MASK  0xf0000000
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED4_FIELD_WIDTH 4
+#define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED4_FIELD_SHIFT 28
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_MASK  0x0000000f
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED0_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED0_FIELD_MASK  0x00000030
+#define UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED0_FIELD_WIDTH 2
+#define UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_MASK  0x00000040
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_MASK  0x00000780
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_MASK  0x00000800
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_SHIFT 11
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_MASK  0x0000f000
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_SHIFT 12
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_MASK  0x00010000
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED1_FIELD;
+#define UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED1_FIELD_MASK  0xfffe0000
+#define UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED1_FIELD_WIDTH 15
+#define UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_MASK  0x0000000f
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED0_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED0_FIELD_MASK  0x00000030
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED0_FIELD_WIDTH 2
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_MASK  0x00000040
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_MASK  0x00000780
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED1_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED1_FIELD_MASK  0x00001800
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED1_FIELD_WIDTH 2
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED1_FIELD_SHIFT 11
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_MASK  0x00002000
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_SHIFT 13
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_MASK  0x0003c000
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_SHIFT 14
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED2_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED2_FIELD_MASK  0x000c0000
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED2_FIELD_WIDTH 2
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED2_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_MASK  0x00100000
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_SHIFT 20
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_MASK  0x01e00000
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_SHIFT 21
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED3_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED3_FIELD_MASK  0x06000000
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED3_FIELD_WIDTH 2
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED3_FIELD_SHIFT 25
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_MASK  0x08000000
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_SHIFT 27
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED4_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED4_FIELD_MASK  0xf0000000
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED4_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED4_FIELD_SHIFT 28
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_MASK  0x0000000f
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED0_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED0_FIELD_MASK  0x00000030
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED0_FIELD_WIDTH 2
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_MASK  0x00000040
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_MASK  0x00000780
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED1_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED1_FIELD_MASK  0x00001800
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED1_FIELD_WIDTH 2
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED1_FIELD_SHIFT 11
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_MASK  0x00002000
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_SHIFT 13
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_MASK  0x0003c000
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_SHIFT 14
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED2_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED2_FIELD_MASK  0x000c0000
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED2_FIELD_WIDTH 2
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED2_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_MASK  0x00100000
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_SHIFT 20
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_MASK  0x01e00000
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_SHIFT 21
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED3_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED3_FIELD_MASK  0x06000000
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED3_FIELD_WIDTH 2
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED3_FIELD_SHIFT 25
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_MASK  0x08000000
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_SHIFT 27
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED4_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED4_FIELD_MASK  0xf0000000
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED4_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED4_FIELD_SHIFT 28
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_MASK  0x0000000f
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED0_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED0_FIELD_MASK  0x00000030
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED0_FIELD_WIDTH 2
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_MASK  0x00000040
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_MASK  0x00000780
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED1_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED1_FIELD_MASK  0x00001800
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED1_FIELD_WIDTH 2
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED1_FIELD_SHIFT 11
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_MASK  0x00002000
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_SHIFT 13
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_MASK  0x0003c000
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_WIDTH 4
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_SHIFT 14
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_MASK  0x00040000
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_WIDTH 1
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_SHIFT 18
+
+extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED2_FIELD;
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED2_FIELD_MASK  0xfff80000
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED2_FIELD_WIDTH 13
+#define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED2_FIELD_SHIFT 19
+
+extern const ru_field_rec UBUS_SLV__CLK_RST_CTRL_SWINIT_FIELD;
+#define UBUS_SLV__CLK_RST_CTRL_SWINIT_FIELD_MASK  0x00000001
+#define UBUS_SLV__CLK_RST_CTRL_SWINIT_FIELD_WIDTH 1
+#define UBUS_SLV__CLK_RST_CTRL_SWINIT_FIELD_SHIFT 0
+
+extern const ru_field_rec UBUS_SLV__CLK_RST_CTRL_CLK250EN_FIELD;
+#define UBUS_SLV__CLK_RST_CTRL_CLK250EN_FIELD_MASK  0x00000002
+#define UBUS_SLV__CLK_RST_CTRL_CLK250EN_FIELD_WIDTH 1
+#define UBUS_SLV__CLK_RST_CTRL_CLK250EN_FIELD_SHIFT 1
+
+extern const ru_field_rec UBUS_SLV__CLK_RST_CTRL_RESERVED0_FIELD;
+#define UBUS_SLV__CLK_RST_CTRL_RESERVED0_FIELD_MASK  0xfffffffc
+#define UBUS_SLV__CLK_RST_CTRL_RESERVED0_FIELD_WIDTH 30
+#define UBUS_SLV__CLK_RST_CTRL_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec SBPM_REGS_INIT_FREE_LIST_INIT_BASE_ADDR_FIELD;
+#define SBPM_REGS_INIT_FREE_LIST_INIT_BASE_ADDR_FIELD_MASK  0x00003fff
+#define SBPM_REGS_INIT_FREE_LIST_INIT_BASE_ADDR_FIELD_WIDTH 14
+#define SBPM_REGS_INIT_FREE_LIST_INIT_BASE_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_INIT_FREE_LIST_INIT_OFFSET_FIELD;
+#define SBPM_REGS_INIT_FREE_LIST_INIT_OFFSET_FIELD_MASK  0x0fffc000
+#define SBPM_REGS_INIT_FREE_LIST_INIT_OFFSET_FIELD_WIDTH 14
+#define SBPM_REGS_INIT_FREE_LIST_INIT_OFFSET_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_INIT_FREE_LIST_RESERVED0_FIELD;
+#define SBPM_REGS_INIT_FREE_LIST_RESERVED0_FIELD_MASK  0x30000000
+#define SBPM_REGS_INIT_FREE_LIST_RESERVED0_FIELD_WIDTH 2
+#define SBPM_REGS_INIT_FREE_LIST_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec SBPM_REGS_INIT_FREE_LIST_BSY_FIELD;
+#define SBPM_REGS_INIT_FREE_LIST_BSY_FIELD_MASK  0x40000000
+#define SBPM_REGS_INIT_FREE_LIST_BSY_FIELD_WIDTH 1
+#define SBPM_REGS_INIT_FREE_LIST_BSY_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_INIT_FREE_LIST_RDY_FIELD;
+#define SBPM_REGS_INIT_FREE_LIST_RDY_FIELD_MASK  0x80000000
+#define SBPM_REGS_INIT_FREE_LIST_RDY_FIELD_WIDTH 1
+#define SBPM_REGS_INIT_FREE_LIST_RDY_FIELD_SHIFT 31
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_RESERVED0_FIELD;
+#define SBPM_REGS_BN_ALLOC_RESERVED0_FIELD_MASK  0x00003fff
+#define SBPM_REGS_BN_ALLOC_RESERVED0_FIELD_WIDTH 14
+#define SBPM_REGS_BN_ALLOC_RESERVED0_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_SA_FIELD;
+#define SBPM_REGS_BN_ALLOC_SA_FIELD_MASK  0x000fc000
+#define SBPM_REGS_BN_ALLOC_SA_FIELD_WIDTH 6
+#define SBPM_REGS_BN_ALLOC_SA_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_RESERVED1_FIELD;
+#define SBPM_REGS_BN_ALLOC_RESERVED1_FIELD_MASK  0xfff00000
+#define SBPM_REGS_BN_ALLOC_RESERVED1_FIELD_WIDTH 12
+#define SBPM_REGS_BN_ALLOC_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_FIELD;
+#define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_FIELD_MASK  0x00000001
+#define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_FIELD_WIDTH 1
+#define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_FIELD;
+#define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_FIELD_MASK  0x00007ffe
+#define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_FIELD_WIDTH 14
+#define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_ACK_FIELD;
+#define SBPM_REGS_BN_ALLOC_RPLY_ACK_FIELD_MASK  0x00008000
+#define SBPM_REGS_BN_ALLOC_RPLY_ACK_FIELD_WIDTH 1
+#define SBPM_REGS_BN_ALLOC_RPLY_ACK_FIELD_SHIFT 15
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_NACK_FIELD;
+#define SBPM_REGS_BN_ALLOC_RPLY_NACK_FIELD_MASK  0x00010000
+#define SBPM_REGS_BN_ALLOC_RPLY_NACK_FIELD_WIDTH 1
+#define SBPM_REGS_BN_ALLOC_RPLY_NACK_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_EXCL_HIGH_FIELD;
+#define SBPM_REGS_BN_ALLOC_RPLY_EXCL_HIGH_FIELD_MASK  0x00020000
+#define SBPM_REGS_BN_ALLOC_RPLY_EXCL_HIGH_FIELD_WIDTH 1
+#define SBPM_REGS_BN_ALLOC_RPLY_EXCL_HIGH_FIELD_SHIFT 17
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_EXCL_LOW_FIELD;
+#define SBPM_REGS_BN_ALLOC_RPLY_EXCL_LOW_FIELD_MASK  0x00040000
+#define SBPM_REGS_BN_ALLOC_RPLY_EXCL_LOW_FIELD_WIDTH 1
+#define SBPM_REGS_BN_ALLOC_RPLY_EXCL_LOW_FIELD_SHIFT 18
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_RESERVED0_FIELD;
+#define SBPM_REGS_BN_ALLOC_RPLY_RESERVED0_FIELD_MASK  0x3ff80000
+#define SBPM_REGS_BN_ALLOC_RPLY_RESERVED0_FIELD_WIDTH 11
+#define SBPM_REGS_BN_ALLOC_RPLY_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_BUSY_FIELD;
+#define SBPM_REGS_BN_ALLOC_RPLY_BUSY_FIELD_MASK  0x40000000
+#define SBPM_REGS_BN_ALLOC_RPLY_BUSY_FIELD_WIDTH 1
+#define SBPM_REGS_BN_ALLOC_RPLY_BUSY_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_RDY_FIELD;
+#define SBPM_REGS_BN_ALLOC_RPLY_RDY_FIELD_MASK  0x80000000
+#define SBPM_REGS_BN_ALLOC_RPLY_RDY_FIELD_WIDTH 1
+#define SBPM_REGS_BN_ALLOC_RPLY_RDY_FIELD_SHIFT 31
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_FIELD_MASK  0x00003fff
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_FIELD_WIDTH 14
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_SA_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_SA_FIELD_MASK  0x000fc000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_SA_FIELD_WIDTH 6
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_SA_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_RESERVED0_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_RESERVED0_FIELD_MASK  0x00f00000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_RESERVED0_FIELD_WIDTH 4
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_RESERVED0_FIELD_SHIFT 20
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_FIELD_MASK  0x7f000000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_FIELD_WIDTH 7
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_FIELD_SHIFT 24
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_ACK_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_ACK_FIELD_MASK  0x80000000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_ACK_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_ACK_FIELD_SHIFT 31
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_FIELD_MASK  0x00003fff
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_FIELD_WIDTH 14
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_RESERVED0_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_RESERVED0_FIELD_MASK  0xffffc000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_RESERVED0_FIELD_WIDTH 18
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_MCST_INC_BN_FIELD;
+#define SBPM_REGS_MCST_INC_BN_FIELD_MASK  0x00003fff
+#define SBPM_REGS_MCST_INC_BN_FIELD_WIDTH 14
+#define SBPM_REGS_MCST_INC_BN_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_MCST_INC_MCST_VAL_FIELD;
+#define SBPM_REGS_MCST_INC_MCST_VAL_FIELD_MASK  0x003fc000
+#define SBPM_REGS_MCST_INC_MCST_VAL_FIELD_WIDTH 8
+#define SBPM_REGS_MCST_INC_MCST_VAL_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_MCST_INC_ACK_REQ_FIELD;
+#define SBPM_REGS_MCST_INC_ACK_REQ_FIELD_MASK  0x00400000
+#define SBPM_REGS_MCST_INC_ACK_REQ_FIELD_WIDTH 1
+#define SBPM_REGS_MCST_INC_ACK_REQ_FIELD_SHIFT 22
+
+extern const ru_field_rec SBPM_REGS_MCST_INC_RESERVED0_FIELD;
+#define SBPM_REGS_MCST_INC_RESERVED0_FIELD_MASK  0xff800000
+#define SBPM_REGS_MCST_INC_RESERVED0_FIELD_WIDTH 9
+#define SBPM_REGS_MCST_INC_RESERVED0_FIELD_SHIFT 23
+
+extern const ru_field_rec SBPM_REGS_MCST_INC_RPLY_MCST_ACK_FIELD;
+#define SBPM_REGS_MCST_INC_RPLY_MCST_ACK_FIELD_MASK  0x00000001
+#define SBPM_REGS_MCST_INC_RPLY_MCST_ACK_FIELD_WIDTH 1
+#define SBPM_REGS_MCST_INC_RPLY_MCST_ACK_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_MCST_INC_RPLY_RESERVED0_FIELD;
+#define SBPM_REGS_MCST_INC_RPLY_RESERVED0_FIELD_MASK  0x3ffffffe
+#define SBPM_REGS_MCST_INC_RPLY_RESERVED0_FIELD_WIDTH 29
+#define SBPM_REGS_MCST_INC_RPLY_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_REGS_MCST_INC_RPLY_BSY_FIELD;
+#define SBPM_REGS_MCST_INC_RPLY_BSY_FIELD_MASK  0x40000000
+#define SBPM_REGS_MCST_INC_RPLY_BSY_FIELD_WIDTH 1
+#define SBPM_REGS_MCST_INC_RPLY_BSY_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_MCST_INC_RPLY_RDY_FIELD;
+#define SBPM_REGS_MCST_INC_RPLY_RDY_FIELD_MASK  0x80000000
+#define SBPM_REGS_MCST_INC_RPLY_RDY_FIELD_WIDTH 1
+#define SBPM_REGS_MCST_INC_RPLY_RDY_FIELD_SHIFT 31
+
+extern const ru_field_rec SBPM_REGS_BN_CONNECT_BN_FIELD;
+#define SBPM_REGS_BN_CONNECT_BN_FIELD_MASK  0x00003fff
+#define SBPM_REGS_BN_CONNECT_BN_FIELD_WIDTH 14
+#define SBPM_REGS_BN_CONNECT_BN_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_BN_CONNECT_ACK_REQ_FIELD;
+#define SBPM_REGS_BN_CONNECT_ACK_REQ_FIELD_MASK  0x00004000
+#define SBPM_REGS_BN_CONNECT_ACK_REQ_FIELD_WIDTH 1
+#define SBPM_REGS_BN_CONNECT_ACK_REQ_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_BN_CONNECT_WR_REQ_FIELD;
+#define SBPM_REGS_BN_CONNECT_WR_REQ_FIELD_MASK  0x00008000
+#define SBPM_REGS_BN_CONNECT_WR_REQ_FIELD_WIDTH 1
+#define SBPM_REGS_BN_CONNECT_WR_REQ_FIELD_SHIFT 15
+
+extern const ru_field_rec SBPM_REGS_BN_CONNECT_POINTED_BN_FIELD;
+#define SBPM_REGS_BN_CONNECT_POINTED_BN_FIELD_MASK  0x3fff0000
+#define SBPM_REGS_BN_CONNECT_POINTED_BN_FIELD_WIDTH 14
+#define SBPM_REGS_BN_CONNECT_POINTED_BN_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_BN_CONNECT_RESERVED0_FIELD;
+#define SBPM_REGS_BN_CONNECT_RESERVED0_FIELD_MASK  0xc0000000
+#define SBPM_REGS_BN_CONNECT_RESERVED0_FIELD_WIDTH 2
+#define SBPM_REGS_BN_CONNECT_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_BN_CONNECT_RPLY_CONNECT_ACK_FIELD;
+#define SBPM_REGS_BN_CONNECT_RPLY_CONNECT_ACK_FIELD_MASK  0x00000001
+#define SBPM_REGS_BN_CONNECT_RPLY_CONNECT_ACK_FIELD_WIDTH 1
+#define SBPM_REGS_BN_CONNECT_RPLY_CONNECT_ACK_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_BN_CONNECT_RPLY_RESERVED0_FIELD;
+#define SBPM_REGS_BN_CONNECT_RPLY_RESERVED0_FIELD_MASK  0x3ffffffe
+#define SBPM_REGS_BN_CONNECT_RPLY_RESERVED0_FIELD_WIDTH 29
+#define SBPM_REGS_BN_CONNECT_RPLY_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_REGS_BN_CONNECT_RPLY_BUSY_FIELD;
+#define SBPM_REGS_BN_CONNECT_RPLY_BUSY_FIELD_MASK  0x40000000
+#define SBPM_REGS_BN_CONNECT_RPLY_BUSY_FIELD_WIDTH 1
+#define SBPM_REGS_BN_CONNECT_RPLY_BUSY_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_BN_CONNECT_RPLY_RDY_FIELD;
+#define SBPM_REGS_BN_CONNECT_RPLY_RDY_FIELD_MASK  0x80000000
+#define SBPM_REGS_BN_CONNECT_RPLY_RDY_FIELD_WIDTH 1
+#define SBPM_REGS_BN_CONNECT_RPLY_RDY_FIELD_SHIFT 31
+
+extern const ru_field_rec SBPM_REGS_GET_NEXT_BN_FIELD;
+#define SBPM_REGS_GET_NEXT_BN_FIELD_MASK  0x00003fff
+#define SBPM_REGS_GET_NEXT_BN_FIELD_WIDTH 14
+#define SBPM_REGS_GET_NEXT_BN_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_GET_NEXT_RESERVED0_FIELD;
+#define SBPM_REGS_GET_NEXT_RESERVED0_FIELD_MASK  0xffffc000
+#define SBPM_REGS_GET_NEXT_RESERVED0_FIELD_WIDTH 18
+#define SBPM_REGS_GET_NEXT_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_BN_VALID_FIELD;
+#define SBPM_REGS_GET_NEXT_RPLY_BN_VALID_FIELD_MASK  0x00000001
+#define SBPM_REGS_GET_NEXT_RPLY_BN_VALID_FIELD_WIDTH 1
+#define SBPM_REGS_GET_NEXT_RPLY_BN_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_NEXT_BN_FIELD;
+#define SBPM_REGS_GET_NEXT_RPLY_NEXT_BN_FIELD_MASK  0x00007ffe
+#define SBPM_REGS_GET_NEXT_RPLY_NEXT_BN_FIELD_WIDTH 14
+#define SBPM_REGS_GET_NEXT_RPLY_NEXT_BN_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_BN_NULL_FIELD;
+#define SBPM_REGS_GET_NEXT_RPLY_BN_NULL_FIELD_MASK  0x00008000
+#define SBPM_REGS_GET_NEXT_RPLY_BN_NULL_FIELD_WIDTH 1
+#define SBPM_REGS_GET_NEXT_RPLY_BN_NULL_FIELD_SHIFT 15
+
+extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_MCNT_VAL_FIELD;
+#define SBPM_REGS_GET_NEXT_RPLY_MCNT_VAL_FIELD_MASK  0x00ff0000
+#define SBPM_REGS_GET_NEXT_RPLY_MCNT_VAL_FIELD_WIDTH 8
+#define SBPM_REGS_GET_NEXT_RPLY_MCNT_VAL_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_RESERVED0_FIELD;
+#define SBPM_REGS_GET_NEXT_RPLY_RESERVED0_FIELD_MASK  0x3f000000
+#define SBPM_REGS_GET_NEXT_RPLY_RESERVED0_FIELD_WIDTH 6
+#define SBPM_REGS_GET_NEXT_RPLY_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_BUSY_FIELD;
+#define SBPM_REGS_GET_NEXT_RPLY_BUSY_FIELD_MASK  0x40000000
+#define SBPM_REGS_GET_NEXT_RPLY_BUSY_FIELD_WIDTH 1
+#define SBPM_REGS_GET_NEXT_RPLY_BUSY_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_RDY_FIELD;
+#define SBPM_REGS_GET_NEXT_RPLY_RDY_FIELD_MASK  0x80000000
+#define SBPM_REGS_GET_NEXT_RPLY_RDY_FIELD_WIDTH 1
+#define SBPM_REGS_GET_NEXT_RPLY_RDY_FIELD_SHIFT 31
+
+extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD;
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK  0x00000001
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK  0x000000fe
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_FIELD;
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK  0x0000ff00
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8
+
+extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD;
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK  0x00010000
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED1_FIELD;
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK  0x000e0000
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_FIELD;
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_FIELD_MASK  0x00700000
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_FIELD_WIDTH 3
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_FIELD_SHIFT 20
+
+extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED2_FIELD;
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK  0x00800000
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23
+
+extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD;
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK  0xff000000
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_FIELD_MASK  0x00003fff
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_FIELD_WIDTH 14
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_SA_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_SA_FIELD_MASK  0x000fc000
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_SA_FIELD_WIDTH 6
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_SA_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RESERVED0_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RESERVED0_FIELD_MASK  0x7ff00000
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RESERVED0_FIELD_WIDTH 11
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RESERVED0_FIELD_SHIFT 20
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_FIELD_MASK  0x80000000
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_FIELD_SHIFT 31
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_FIELD_MASK  0x00000001
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED0_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED0_FIELD_MASK  0x00007ffe
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED0_FIELD_WIDTH 14
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_FIELD_MASK  0x00008000
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_FIELD_SHIFT 15
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_FIELD_MASK  0x00010000
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_HIGH_STAT_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_HIGH_STAT_FIELD_MASK  0x00020000
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_HIGH_STAT_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_HIGH_STAT_FIELD_SHIFT 17
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_LOW_STAT_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_LOW_STAT_FIELD_MASK  0x00040000
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_LOW_STAT_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_LOW_STAT_FIELD_SHIFT 18
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED1_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED1_FIELD_MASK  0x3ff80000
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED1_FIELD_WIDTH 11
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED1_FIELD_SHIFT 19
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_FIELD_MASK  0x40000000
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_FIELD;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_FIELD_MASK  0x80000000
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_FIELD_SHIFT 31
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_FIELD_MASK  0x00000001
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED0_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED0_FIELD_MASK  0x00007ffe
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED0_FIELD_WIDTH 14
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_FIELD_MASK  0x00008000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_FIELD_SHIFT 15
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_FIELD_MASK  0x00010000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_HIGH_STATE_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_HIGH_STATE_FIELD_MASK  0x00020000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_HIGH_STATE_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_HIGH_STATE_FIELD_SHIFT 17
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_LOW_STATE_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_LOW_STATE_FIELD_MASK  0x00040000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_LOW_STATE_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_LOW_STATE_FIELD_SHIFT 18
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED1_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED1_FIELD_MASK  0x3ff80000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED1_FIELD_WIDTH 11
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED1_FIELD_SHIFT 19
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_FIELD_MASK  0x40000000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_FIELD;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_FIELD_MASK  0x80000000
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_FIELD_WIDTH 1
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_FIELD_SHIFT 31
+
+extern const ru_field_rec SBPM_REGS_SBPM_GL_TRSH_GL_BAT_FIELD;
+#define SBPM_REGS_SBPM_GL_TRSH_GL_BAT_FIELD_MASK  0x00003fff
+#define SBPM_REGS_SBPM_GL_TRSH_GL_BAT_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_GL_TRSH_GL_BAT_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_GL_TRSH_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_GL_TRSH_RESERVED0_FIELD_MASK  0x0000c000
+#define SBPM_REGS_SBPM_GL_TRSH_RESERVED0_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_GL_TRSH_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_GL_TRSH_GL_BAH_FIELD;
+#define SBPM_REGS_SBPM_GL_TRSH_GL_BAH_FIELD_MASK  0x3fff0000
+#define SBPM_REGS_SBPM_GL_TRSH_GL_BAH_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_GL_TRSH_GL_BAH_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_SBPM_GL_TRSH_RESERVED1_FIELD;
+#define SBPM_REGS_SBPM_GL_TRSH_RESERVED1_FIELD_MASK  0xc0000000
+#define SBPM_REGS_SBPM_GL_TRSH_RESERVED1_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_GL_TRSH_RESERVED1_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_TRSH_UG_BAT_FIELD;
+#define SBPM_REGS_SBPM_UG0_TRSH_UG_BAT_FIELD_MASK  0x00003fff
+#define SBPM_REGS_SBPM_UG0_TRSH_UG_BAT_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG0_TRSH_UG_BAT_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_TRSH_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_UG0_TRSH_RESERVED0_FIELD_MASK  0x0000c000
+#define SBPM_REGS_SBPM_UG0_TRSH_RESERVED0_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG0_TRSH_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_TRSH_UG_BAH_FIELD;
+#define SBPM_REGS_SBPM_UG0_TRSH_UG_BAH_FIELD_MASK  0x3fff0000
+#define SBPM_REGS_SBPM_UG0_TRSH_UG_BAH_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG0_TRSH_UG_BAH_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_TRSH_RESERVED1_FIELD;
+#define SBPM_REGS_SBPM_UG0_TRSH_RESERVED1_FIELD_MASK  0xc0000000
+#define SBPM_REGS_SBPM_UG0_TRSH_RESERVED1_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG0_TRSH_RESERVED1_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_TRSH_UG_BAT_FIELD;
+#define SBPM_REGS_SBPM_UG1_TRSH_UG_BAT_FIELD_MASK  0x00003fff
+#define SBPM_REGS_SBPM_UG1_TRSH_UG_BAT_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG1_TRSH_UG_BAT_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_TRSH_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_UG1_TRSH_RESERVED0_FIELD_MASK  0x0000c000
+#define SBPM_REGS_SBPM_UG1_TRSH_RESERVED0_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG1_TRSH_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_TRSH_UG_BAH_FIELD;
+#define SBPM_REGS_SBPM_UG1_TRSH_UG_BAH_FIELD_MASK  0x3fff0000
+#define SBPM_REGS_SBPM_UG1_TRSH_UG_BAH_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG1_TRSH_UG_BAH_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_TRSH_RESERVED1_FIELD;
+#define SBPM_REGS_SBPM_UG1_TRSH_RESERVED1_FIELD_MASK  0xc0000000
+#define SBPM_REGS_SBPM_UG1_TRSH_RESERVED1_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG1_TRSH_RESERVED1_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_SELECT_BUS_FIELD;
+#define SBPM_REGS_SBPM_DBG_SELECT_BUS_FIELD_MASK  0x0000000f
+#define SBPM_REGS_SBPM_DBG_SELECT_BUS_FIELD_WIDTH 4
+#define SBPM_REGS_SBPM_DBG_SELECT_BUS_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_DBG_RESERVED0_FIELD_MASK  0xfffffff0
+#define SBPM_REGS_SBPM_DBG_RESERVED0_FIELD_WIDTH 28
+#define SBPM_REGS_SBPM_DBG_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_BAC_UG0BAC_FIELD;
+#define SBPM_REGS_SBPM_UG0_BAC_UG0BAC_FIELD_MASK  0x00003fff
+#define SBPM_REGS_SBPM_UG0_BAC_UG0BAC_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG0_BAC_UG0BAC_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_BAC_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_UG0_BAC_RESERVED0_FIELD_MASK  0xffffc000
+#define SBPM_REGS_SBPM_UG0_BAC_RESERVED0_FIELD_WIDTH 18
+#define SBPM_REGS_SBPM_UG0_BAC_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_BAC_UG1BAC_FIELD;
+#define SBPM_REGS_SBPM_UG1_BAC_UG1BAC_FIELD_MASK  0x00003fff
+#define SBPM_REGS_SBPM_UG1_BAC_UG1BAC_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG1_BAC_UG1BAC_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_BAC_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_UG1_BAC_RESERVED0_FIELD_MASK  0xffffc000
+#define SBPM_REGS_SBPM_UG1_BAC_RESERVED0_FIELD_WIDTH 18
+#define SBPM_REGS_SBPM_UG1_BAC_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_GL_BAC_BAC_FIELD;
+#define SBPM_REGS_SBPM_GL_BAC_BAC_FIELD_MASK  0x00003fff
+#define SBPM_REGS_SBPM_GL_BAC_BAC_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_GL_BAC_BAC_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_GL_BAC_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_GL_BAC_RESERVED0_FIELD_MASK  0xffffc000
+#define SBPM_REGS_SBPM_GL_BAC_RESERVED0_FIELD_WIDTH 18
+#define SBPM_REGS_SBPM_GL_BAC_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_FIELD;
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_FIELD_MASK  0x00003fff
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED0_FIELD_MASK  0x0000c000
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED0_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_FIELD;
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_FIELD_MASK  0x3fff0000
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED1_FIELD;
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED1_FIELD_MASK  0xc0000000
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED1_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED1_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_FIELD;
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_FIELD_MASK  0x00003fff
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED0_FIELD_MASK  0x0000c000
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED0_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_FIELD;
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_FIELD_MASK  0x3fff0000
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED1_FIELD;
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED1_FIELD_MASK  0xc0000000
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED1_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED1_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_FIELD;
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_FIELD_MASK  0x00003fff
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED0_FIELD_MASK  0x0000c000
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED0_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_FIELD;
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_FIELD_MASK  0x3fff0000
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED1_FIELD;
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED1_FIELD_MASK  0xc0000000
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED1_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED1_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_FIELD;
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_FIELD_MASK  0x00003fff
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED0_FIELD_MASK  0x0000c000
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED0_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_FIELD;
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_FIELD_MASK  0x3fff0000
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED1_FIELD;
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED1_FIELD_MASK  0xc0000000
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED1_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED1_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG_STATUS_UG_ACK_STTS_FIELD;
+#define SBPM_REGS_SBPM_UG_STATUS_UG_ACK_STTS_FIELD_MASK  0x00000003
+#define SBPM_REGS_SBPM_UG_STATUS_UG_ACK_STTS_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG_STATUS_UG_ACK_STTS_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG_STATUS_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_UG_STATUS_RESERVED0_FIELD_MASK  0x0000fffc
+#define SBPM_REGS_SBPM_UG_STATUS_RESERVED0_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG_STATUS_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_FIELD;
+#define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_FIELD_MASK  0x00030000
+#define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_FIELD;
+#define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_FIELD_MASK  0x000c0000
+#define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_FIELD_SHIFT 18
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG_STATUS_RESERVED1_FIELD;
+#define SBPM_REGS_SBPM_UG_STATUS_RESERVED1_FIELD_MASK  0xfff00000
+#define SBPM_REGS_SBPM_UG_STATUS_RESERVED1_FIELD_WIDTH 12
+#define SBPM_REGS_SBPM_UG_STATUS_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec SBPM_REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_FIELD;
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_FIELD_MASK  0x0000007f
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_FIELD_WIDTH 7
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_FIELD;
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_FIELD_MASK  0x00000080
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_FIELD_WIDTH 1
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_FIELD_SHIFT 7
+
+extern const ru_field_rec SBPM_REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_FIELD;
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_FIELD_MASK  0x00000100
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_FIELD_WIDTH 1
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_FIELD_SHIFT 8
+
+extern const ru_field_rec SBPM_REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_FIELD;
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_FIELD_MASK  0x00000200
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_FIELD_WIDTH 1
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_FIELD_SHIFT 9
+
+extern const ru_field_rec SBPM_REGS_ERROR_HANDLING_PARAMS_RESERVED0_FIELD;
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_RESERVED0_FIELD_MASK  0xfffffc00
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_RESERVED0_FIELD_WIDTH 22
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec SBPM_REGS_SBPM_IIR_ADDR_CMD_SA_FIELD;
+#define SBPM_REGS_SBPM_IIR_ADDR_CMD_SA_FIELD_MASK  0x0000003f
+#define SBPM_REGS_SBPM_IIR_ADDR_CMD_SA_FIELD_WIDTH 6
+#define SBPM_REGS_SBPM_IIR_ADDR_CMD_SA_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_IIR_ADDR_CMD_TA_FIELD;
+#define SBPM_REGS_SBPM_IIR_ADDR_CMD_TA_FIELD_MASK  0x000001c0
+#define SBPM_REGS_SBPM_IIR_ADDR_CMD_TA_FIELD_WIDTH 3
+#define SBPM_REGS_SBPM_IIR_ADDR_CMD_TA_FIELD_SHIFT 6
+
+extern const ru_field_rec SBPM_REGS_SBPM_IIR_ADDR_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_IIR_ADDR_RESERVED0_FIELD_MASK  0xfffffe00
+#define SBPM_REGS_SBPM_IIR_ADDR_RESERVED0_FIELD_WIDTH 23
+#define SBPM_REGS_SBPM_IIR_ADDR_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec SBPM_REGS_SBPM_IIR_LOW_CMD_DATA_0TO31_FIELD;
+#define SBPM_REGS_SBPM_IIR_LOW_CMD_DATA_0TO31_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_IIR_LOW_CMD_DATA_0TO31_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_IIR_LOW_CMD_DATA_0TO31_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_IIR_HIGH_CMD_DATA_32TO63_FIELD;
+#define SBPM_REGS_SBPM_IIR_HIGH_CMD_DATA_32TO63_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_IIR_HIGH_CMD_DATA_32TO63_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_IIR_HIGH_CMD_DATA_32TO63_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_ALLOC_SM_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC0_ALLOC_SM_FIELD_MASK  0x00000003
+#define SBPM_REGS_SBPM_DBG_VEC0_ALLOC_SM_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_DBG_VEC0_ALLOC_SM_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_CNNCT_SM_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC0_CNNCT_SM_FIELD_MASK  0x00000004
+#define SBPM_REGS_SBPM_DBG_VEC0_CNNCT_SM_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC0_CNNCT_SM_FIELD_SHIFT 2
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_MCINT_SM_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC0_MCINT_SM_FIELD_MASK  0x00000078
+#define SBPM_REGS_SBPM_DBG_VEC0_MCINT_SM_FIELD_WIDTH 4
+#define SBPM_REGS_SBPM_DBG_VEC0_MCINT_SM_FIELD_SHIFT 3
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_FIELD_MASK  0x00000780
+#define SBPM_REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_FIELD_WIDTH 4
+#define SBPM_REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_FIELD_SHIFT 7
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_FIELD_MASK  0x00007800
+#define SBPM_REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_FIELD_WIDTH 4
+#define SBPM_REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_FIELD_SHIFT 11
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_GN_SM_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC0_GN_SM_FIELD_MASK  0x00018000
+#define SBPM_REGS_SBPM_DBG_VEC0_GN_SM_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_DBG_VEC0_GN_SM_FIELD_SHIFT 15
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_MULTI_GN_SM_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC0_MULTI_GN_SM_FIELD_MASK  0x001e0000
+#define SBPM_REGS_SBPM_DBG_VEC0_MULTI_GN_SM_FIELD_WIDTH 4
+#define SBPM_REGS_SBPM_DBG_VEC0_MULTI_GN_SM_FIELD_SHIFT 17
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_FREE_LST_HD_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC0_FREE_LST_HD_FIELD_MASK  0xffe00000
+#define SBPM_REGS_SBPM_DBG_VEC0_FREE_LST_HD_FIELD_WIDTH 11
+#define SBPM_REGS_SBPM_DBG_VEC0_FREE_LST_HD_FIELD_SHIFT 21
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_IN2E_VALID_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_IN2E_VALID_FIELD_MASK  0x00000001
+#define SBPM_REGS_SBPM_DBG_VEC1_IN2E_VALID_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_IN2E_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_FIELD_MASK  0x0000001e
+#define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_FIELD_WIDTH 4
+#define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_UG_ACTIVE_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_UG_ACTIVE_FIELD_MASK  0x00000060
+#define SBPM_REGS_SBPM_DBG_VEC1_UG_ACTIVE_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_DBG_VEC1_UG_ACTIVE_FIELD_SHIFT 5
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_TX_CMD_FULL_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_TX_CMD_FULL_FIELD_MASK  0x00000080
+#define SBPM_REGS_SBPM_DBG_VEC1_TX_CMD_FULL_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_TX_CMD_FULL_FIELD_SHIFT 7
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_POP_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_POP_FIELD_MASK  0x00000100
+#define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_POP_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_POP_FIELD_SHIFT 8
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_START_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_START_FIELD_MASK  0x00000200
+#define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_START_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_START_FIELD_SHIFT 9
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_DONE_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_DONE_FIELD_MASK  0x00000400
+#define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_DONE_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_DONE_FIELD_SHIFT 10
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_FIELD_MASK  0x001ff800
+#define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_FIELD_WIDTH 10
+#define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_FIELD_SHIFT 11
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_FREE_DECODE_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_FREE_DECODE_FIELD_MASK  0x00200000
+#define SBPM_REGS_SBPM_DBG_VEC1_FREE_DECODE_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_FREE_DECODE_FIELD_SHIFT 21
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_IN2E_DECODE_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_IN2E_DECODE_FIELD_MASK  0x00400000
+#define SBPM_REGS_SBPM_DBG_VEC1_IN2E_DECODE_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_IN2E_DECODE_FIELD_SHIFT 22
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_FREE_WO_DECODE_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_FREE_WO_DECODE_FIELD_MASK  0x00800000
+#define SBPM_REGS_SBPM_DBG_VEC1_FREE_WO_DECODE_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_FREE_WO_DECODE_FIELD_SHIFT 23
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_GET_NXT_DECODE_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_GET_NXT_DECODE_FIELD_MASK  0x01000000
+#define SBPM_REGS_SBPM_DBG_VEC1_GET_NXT_DECODE_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_GET_NXT_DECODE_FIELD_SHIFT 24
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_MULTI_GET_NXT_DECODE_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GET_NXT_DECODE_FIELD_MASK  0x02000000
+#define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GET_NXT_DECODE_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GET_NXT_DECODE_FIELD_SHIFT 25
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_CNCT_DECODE_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_CNCT_DECODE_FIELD_MASK  0x04000000
+#define SBPM_REGS_SBPM_DBG_VEC1_CNCT_DECODE_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_CNCT_DECODE_FIELD_SHIFT 26
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_FREE_W_DECODE_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_FREE_W_DECODE_FIELD_MASK  0x08000000
+#define SBPM_REGS_SBPM_DBG_VEC1_FREE_W_DECODE_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_FREE_W_DECODE_FIELD_SHIFT 27
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_MCIN_DECODE_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_MCIN_DECODE_FIELD_MASK  0x10000000
+#define SBPM_REGS_SBPM_DBG_VEC1_MCIN_DECODE_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_MCIN_DECODE_FIELD_SHIFT 28
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_ALLOC_DECODE_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_ALLOC_DECODE_FIELD_MASK  0x20000000
+#define SBPM_REGS_SBPM_DBG_VEC1_ALLOC_DECODE_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC1_ALLOC_DECODE_FIELD_SHIFT 29
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC1_RESERVED0_FIELD_MASK  0xc0000000
+#define SBPM_REGS_SBPM_DBG_VEC1_RESERVED0_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_DBG_VEC1_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX_DATA_FULL_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_DATA_FULL_FIELD_MASK  0x00000001
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_DATA_FULL_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_DATA_FULL_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX_FIFO_EMPTY_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_FIFO_EMPTY_FIELD_MASK  0x00000002
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_FIFO_EMPTY_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_FIFO_EMPTY_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_FULL_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_FULL_FIELD_MASK  0x00000004
+#define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_FULL_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_FULL_FIELD_SHIFT 2
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_EMPTY_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_EMPTY_FIELD_MASK  0x00000008
+#define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_EMPTY_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_EMPTY_FIELD_SHIFT 3
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FULL_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FULL_FIELD_MASK  0x00000010
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FULL_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FULL_FIELD_SHIFT 4
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FIFO_EMPTY_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FIFO_EMPTY_FIELD_MASK  0x00000020
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FIFO_EMPTY_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FIFO_EMPTY_FIELD_SHIFT 5
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_FIELD_MASK  0x00000fc0
+#define SBPM_REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_FIELD_WIDTH 6
+#define SBPM_REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_FIELD_SHIFT 6
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX_BBH_SEND_IN_PROGRESS_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_BBH_SEND_IN_PROGRESS_FIELD_MASK  0x00001000
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_BBH_SEND_IN_PROGRESS_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC2_TX_BBH_SEND_IN_PROGRESS_FIELD_SHIFT 12
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_SP_2SEND_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_SP_2SEND_FIELD_MASK  0x0007e000
+#define SBPM_REGS_SBPM_DBG_VEC2_SP_2SEND_FIELD_WIDTH 6
+#define SBPM_REGS_SBPM_DBG_VEC2_SP_2SEND_FIELD_SHIFT 13
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_FIELD_MASK  0x00380000
+#define SBPM_REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_FIELD_WIDTH 3
+#define SBPM_REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_FIELD_SHIFT 19
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_CPU_ACCESS_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_CPU_ACCESS_FIELD_MASK  0x00400000
+#define SBPM_REGS_SBPM_DBG_VEC2_CPU_ACCESS_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC2_CPU_ACCESS_FIELD_SHIFT 22
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_BBH_ACCESS_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_BBH_ACCESS_FIELD_MASK  0x00800000
+#define SBPM_REGS_SBPM_DBG_VEC2_BBH_ACCESS_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC2_BBH_ACCESS_FIELD_SHIFT 23
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_RNR_ACCESS_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_RNR_ACCESS_FIELD_MASK  0x01000000
+#define SBPM_REGS_SBPM_DBG_VEC2_RNR_ACCESS_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC2_RNR_ACCESS_FIELD_SHIFT 24
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC2_RESERVED0_FIELD_MASK  0xfe000000
+#define SBPM_REGS_SBPM_DBG_VEC2_RESERVED0_FIELD_WIDTH 7
+#define SBPM_REGS_SBPM_DBG_VEC2_RESERVED0_FIELD_SHIFT 25
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_ALLOC_RPLY_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC3_ALLOC_RPLY_FIELD_MASK  0x00000001
+#define SBPM_REGS_SBPM_DBG_VEC3_ALLOC_RPLY_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC3_ALLOC_RPLY_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_BN_RPLY_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC3_BN_RPLY_FIELD_MASK  0x00000ffe
+#define SBPM_REGS_SBPM_DBG_VEC3_BN_RPLY_FIELD_WIDTH 11
+#define SBPM_REGS_SBPM_DBG_VEC3_BN_RPLY_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_ALLOC_ACK_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_ALLOC_ACK_FIELD_MASK  0x00001000
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_ALLOC_ACK_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_ALLOC_ACK_FIELD_SHIFT 12
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TX_FIFO_MCINC_ACK_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC3_TX_FIFO_MCINC_ACK_FIELD_MASK  0x00002000
+#define SBPM_REGS_SBPM_DBG_VEC3_TX_FIFO_MCINC_ACK_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC3_TX_FIFO_MCINC_ACK_FIELD_SHIFT 13
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_CNCT_ACK_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_CNCT_ACK_FIELD_MASK  0x00004000
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_CNCT_ACK_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_CNCT_ACK_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_GT_NXT_RPLY_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_GT_NXT_RPLY_FIELD_MASK  0x00008000
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_GT_NXT_RPLY_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_GT_NXT_RPLY_FIELD_SHIFT 15
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_MLTI_GT_NXT_RPLY_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_MLTI_GT_NXT_RPLY_FIELD_MASK  0x00010000
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_MLTI_GT_NXT_RPLY_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_MLTI_GT_NXT_RPLY_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_FIELD_MASK  0x00060000
+#define SBPM_REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_FIELD_WIDTH 2
+#define SBPM_REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_FIELD_SHIFT 17
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_SEND_STT_SM_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC3_SEND_STT_SM_FIELD_MASK  0x00080000
+#define SBPM_REGS_SBPM_DBG_VEC3_SEND_STT_SM_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC3_SEND_STT_SM_FIELD_SHIFT 19
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_IN2ESTTS_CHNG_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_IN2ESTTS_CHNG_FIELD_MASK  0x00100000
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_IN2ESTTS_CHNG_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_IN2ESTTS_CHNG_FIELD_SHIFT 20
+
+extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_DBG_VEC3_RESERVED0_FIELD_MASK  0xffe00000
+#define SBPM_REGS_SBPM_DBG_VEC3_RESERVED0_FIELD_WIDTH 11
+#define SBPM_REGS_SBPM_DBG_VEC3_RESERVED0_FIELD_SHIFT 21
+
+extern const ru_field_rec SBPM_REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_FIELD;
+#define SBPM_REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_FIELD;
+#define SBPM_REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_FIELD;
+#define SBPM_REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_FIELD;
+#define SBPM_REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_FIELD;
+#define SBPM_REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_FIELD;
+#define SBPM_REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_FIELD;
+#define SBPM_REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_FIELD;
+#define SBPM_REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_FIELD;
+#define SBPM_REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_FIELD;
+#define SBPM_REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_FIELD_MASK  0xffffffff
+#define SBPM_REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_FIELD_WIDTH 32
+#define SBPM_REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_RADDR_DECODER_ID_2OVERWR_FIELD;
+#define SBPM_REGS_SBPM_RADDR_DECODER_ID_2OVERWR_FIELD_MASK  0x0000003f
+#define SBPM_REGS_SBPM_RADDR_DECODER_ID_2OVERWR_FIELD_WIDTH 6
+#define SBPM_REGS_SBPM_RADDR_DECODER_ID_2OVERWR_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_RA_FIELD;
+#define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_RA_FIELD_MASK  0x0000ffc0
+#define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_RA_FIELD_WIDTH 10
+#define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_RA_FIELD_SHIFT 6
+
+extern const ru_field_rec SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_VALID_FIELD;
+#define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_VALID_FIELD_MASK  0x00010000
+#define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_VALID_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_VALID_FIELD_SHIFT 16
+
+extern const ru_field_rec SBPM_REGS_SBPM_RADDR_DECODER_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_RADDR_DECODER_RESERVED0_FIELD_MASK  0xfffe0000
+#define SBPM_REGS_SBPM_RADDR_DECODER_RESERVED0_FIELD_WIDTH 15
+#define SBPM_REGS_SBPM_RADDR_DECODER_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec SBPM_REGS_SBPM_WR_DATA_SBPM_WR_DATA_FIELD;
+#define SBPM_REGS_SBPM_WR_DATA_SBPM_WR_DATA_FIELD_MASK  0x003fffff
+#define SBPM_REGS_SBPM_WR_DATA_SBPM_WR_DATA_FIELD_WIDTH 22
+#define SBPM_REGS_SBPM_WR_DATA_SBPM_WR_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_WR_DATA_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_WR_DATA_RESERVED0_FIELD_MASK  0xffc00000
+#define SBPM_REGS_SBPM_WR_DATA_RESERVED0_FIELD_WIDTH 10
+#define SBPM_REGS_SBPM_WR_DATA_RESERVED0_FIELD_SHIFT 22
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG_BAC_MAX_UG0BACMAX_FIELD;
+#define SBPM_REGS_SBPM_UG_BAC_MAX_UG0BACMAX_FIELD_MASK  0x00003fff
+#define SBPM_REGS_SBPM_UG_BAC_MAX_UG0BACMAX_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG_BAC_MAX_UG0BACMAX_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG_BAC_MAX_UG1BACMAX_FIELD;
+#define SBPM_REGS_SBPM_UG_BAC_MAX_UG1BACMAX_FIELD_MASK  0x0fffc000
+#define SBPM_REGS_SBPM_UG_BAC_MAX_UG1BACMAX_FIELD_WIDTH 14
+#define SBPM_REGS_SBPM_UG_BAC_MAX_UG1BACMAX_FIELD_SHIFT 14
+
+extern const ru_field_rec SBPM_REGS_SBPM_UG_BAC_MAX_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_UG_BAC_MAX_RESERVED0_FIELD_MASK  0xf0000000
+#define SBPM_REGS_SBPM_UG_BAC_MAX_RESERVED0_FIELD_WIDTH 4
+#define SBPM_REGS_SBPM_UG_BAC_MAX_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec SBPM_REGS_SBPM_SPARE_GL_BAC_CLEAR_EN_FIELD;
+#define SBPM_REGS_SBPM_SPARE_GL_BAC_CLEAR_EN_FIELD_MASK  0x00000001
+#define SBPM_REGS_SBPM_SPARE_GL_BAC_CLEAR_EN_FIELD_WIDTH 1
+#define SBPM_REGS_SBPM_SPARE_GL_BAC_CLEAR_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_REGS_SBPM_SPARE_RESERVED0_FIELD;
+#define SBPM_REGS_SBPM_SPARE_RESERVED0_FIELD_MASK  0xfffffffe
+#define SBPM_REGS_SBPM_SPARE_RESERVED0_FIELD_WIDTH 31
+#define SBPM_REGS_SBPM_SPARE_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_INTR_CTRL_ISR_BAC_UNDERRUN_FIELD;
+#define SBPM_INTR_CTRL_ISR_BAC_UNDERRUN_FIELD_MASK  0x00000001
+#define SBPM_INTR_CTRL_ISR_BAC_UNDERRUN_FIELD_WIDTH 1
+#define SBPM_INTR_CTRL_ISR_BAC_UNDERRUN_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_INTR_CTRL_ISR_MCST_OVERFLOW_FIELD;
+#define SBPM_INTR_CTRL_ISR_MCST_OVERFLOW_FIELD_MASK  0x00000002
+#define SBPM_INTR_CTRL_ISR_MCST_OVERFLOW_FIELD_WIDTH 1
+#define SBPM_INTR_CTRL_ISR_MCST_OVERFLOW_FIELD_SHIFT 1
+
+extern const ru_field_rec SBPM_INTR_CTRL_ISR_CHECK_LAST_ERR_FIELD;
+#define SBPM_INTR_CTRL_ISR_CHECK_LAST_ERR_FIELD_MASK  0x00000004
+#define SBPM_INTR_CTRL_ISR_CHECK_LAST_ERR_FIELD_WIDTH 1
+#define SBPM_INTR_CTRL_ISR_CHECK_LAST_ERR_FIELD_SHIFT 2
+
+extern const ru_field_rec SBPM_INTR_CTRL_ISR_MAX_SEARCH_ERR_FIELD;
+#define SBPM_INTR_CTRL_ISR_MAX_SEARCH_ERR_FIELD_MASK  0x00000008
+#define SBPM_INTR_CTRL_ISR_MAX_SEARCH_ERR_FIELD_WIDTH 1
+#define SBPM_INTR_CTRL_ISR_MAX_SEARCH_ERR_FIELD_SHIFT 3
+
+extern const ru_field_rec SBPM_INTR_CTRL_ISR_INVALID_IN2E_FIELD;
+#define SBPM_INTR_CTRL_ISR_INVALID_IN2E_FIELD_MASK  0x00000010
+#define SBPM_INTR_CTRL_ISR_INVALID_IN2E_FIELD_WIDTH 1
+#define SBPM_INTR_CTRL_ISR_INVALID_IN2E_FIELD_SHIFT 4
+
+extern const ru_field_rec SBPM_INTR_CTRL_ISR_MULTI_GET_NEXT_NULL_FIELD;
+#define SBPM_INTR_CTRL_ISR_MULTI_GET_NEXT_NULL_FIELD_MASK  0x00000020
+#define SBPM_INTR_CTRL_ISR_MULTI_GET_NEXT_NULL_FIELD_WIDTH 1
+#define SBPM_INTR_CTRL_ISR_MULTI_GET_NEXT_NULL_FIELD_SHIFT 5
+
+extern const ru_field_rec SBPM_INTR_CTRL_ISR_CNCT_NULL_FIELD;
+#define SBPM_INTR_CTRL_ISR_CNCT_NULL_FIELD_MASK  0x00000040
+#define SBPM_INTR_CTRL_ISR_CNCT_NULL_FIELD_WIDTH 1
+#define SBPM_INTR_CTRL_ISR_CNCT_NULL_FIELD_SHIFT 6
+
+extern const ru_field_rec SBPM_INTR_CTRL_ISR_ALLOC_NULL_FIELD;
+#define SBPM_INTR_CTRL_ISR_ALLOC_NULL_FIELD_MASK  0x00000080
+#define SBPM_INTR_CTRL_ISR_ALLOC_NULL_FIELD_WIDTH 1
+#define SBPM_INTR_CTRL_ISR_ALLOC_NULL_FIELD_SHIFT 7
+
+extern const ru_field_rec SBPM_INTR_CTRL_ISR_RESERVED0_FIELD;
+#define SBPM_INTR_CTRL_ISR_RESERVED0_FIELD_MASK  0xffffff00
+#define SBPM_INTR_CTRL_ISR_RESERVED0_FIELD_WIDTH 24
+#define SBPM_INTR_CTRL_ISR_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec SBPM_INTR_CTRL_ISM_ISM_FIELD;
+#define SBPM_INTR_CTRL_ISM_ISM_FIELD_MASK  0xffffffff
+#define SBPM_INTR_CTRL_ISM_ISM_FIELD_WIDTH 32
+#define SBPM_INTR_CTRL_ISM_ISM_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_INTR_CTRL_IER_IEM_FIELD;
+#define SBPM_INTR_CTRL_IER_IEM_FIELD_MASK  0xffffffff
+#define SBPM_INTR_CTRL_IER_IEM_FIELD_WIDTH 32
+#define SBPM_INTR_CTRL_IER_IEM_FIELD_SHIFT 0
+
+extern const ru_field_rec SBPM_INTR_CTRL_ITR_IST_FIELD;
+#define SBPM_INTR_CTRL_ITR_IST_FIELD_MASK  0xffffffff
+#define SBPM_INTR_CTRL_ITR_IST_FIELD_WIDTH 32
+#define SBPM_INTR_CTRL_ITR_IST_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD;
+#define DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD_MASK  0x0000003f
+#define DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD_WIDTH 6
+#define DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD;
+#define DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD_MASK  0xffffffc0
+#define DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD_WIDTH 26
+#define DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD;
+#define DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD_MASK  0x0000003f
+#define DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD_WIDTH 6
+#define DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD;
+#define DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD_MASK  0xffffffc0
+#define DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD_WIDTH 26
+#define DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec DMA_CONFIG_U_THRESH_INTO_U_FIELD;
+#define DMA_CONFIG_U_THRESH_INTO_U_FIELD_MASK  0x0000003f
+#define DMA_CONFIG_U_THRESH_INTO_U_FIELD_WIDTH 6
+#define DMA_CONFIG_U_THRESH_INTO_U_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_U_THRESH_RESERVED0_FIELD;
+#define DMA_CONFIG_U_THRESH_RESERVED0_FIELD_MASK  0x000000c0
+#define DMA_CONFIG_U_THRESH_RESERVED0_FIELD_WIDTH 2
+#define DMA_CONFIG_U_THRESH_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD;
+#define DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD_MASK  0x00003f00
+#define DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD_WIDTH 6
+#define DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD_SHIFT 8
+
+extern const ru_field_rec DMA_CONFIG_U_THRESH_RESERVED1_FIELD;
+#define DMA_CONFIG_U_THRESH_RESERVED1_FIELD_MASK  0xffffc000
+#define DMA_CONFIG_U_THRESH_RESERVED1_FIELD_WIDTH 18
+#define DMA_CONFIG_U_THRESH_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec DMA_CONFIG_PRI_RXPRI_FIELD;
+#define DMA_CONFIG_PRI_RXPRI_FIELD_MASK  0x0000000f
+#define DMA_CONFIG_PRI_RXPRI_FIELD_WIDTH 4
+#define DMA_CONFIG_PRI_RXPRI_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_PRI_TXPRI_FIELD;
+#define DMA_CONFIG_PRI_TXPRI_FIELD_MASK  0x000000f0
+#define DMA_CONFIG_PRI_TXPRI_FIELD_WIDTH 4
+#define DMA_CONFIG_PRI_TXPRI_FIELD_SHIFT 4
+
+extern const ru_field_rec DMA_CONFIG_PRI_RESERVED0_FIELD;
+#define DMA_CONFIG_PRI_RESERVED0_FIELD_MASK  0xffffff00
+#define DMA_CONFIG_PRI_RESERVED0_FIELD_WIDTH 24
+#define DMA_CONFIG_PRI_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD;
+#define DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD_MASK  0x00000007
+#define DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD_WIDTH 3
+#define DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_WEIGHT_RESERVED0_FIELD;
+#define DMA_CONFIG_WEIGHT_RESERVED0_FIELD_MASK  0x000000f8
+#define DMA_CONFIG_WEIGHT_RESERVED0_FIELD_WIDTH 5
+#define DMA_CONFIG_WEIGHT_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD;
+#define DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD_MASK  0x00000700
+#define DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD_WIDTH 3
+#define DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD_SHIFT 8
+
+extern const ru_field_rec DMA_CONFIG_WEIGHT_RESERVED1_FIELD;
+#define DMA_CONFIG_WEIGHT_RESERVED1_FIELD_MASK  0xfffff800
+#define DMA_CONFIG_WEIGHT_RESERVED1_FIELD_WIDTH 21
+#define DMA_CONFIG_WEIGHT_RESERVED1_FIELD_SHIFT 11
+
+extern const ru_field_rec DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD;
+#define DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD_MASK  0x0000003f
+#define DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD_WIDTH 6
+#define DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD;
+#define DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD_MASK  0x000000c0
+#define DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD_WIDTH 2
+#define DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD;
+#define DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD_MASK  0x00003f00
+#define DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD_WIDTH 6
+#define DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD_SHIFT 8
+
+extern const ru_field_rec DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD;
+#define DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD_MASK  0xffffc000
+#define DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD_WIDTH 18
+#define DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec DMA_CONFIG_TARGET_MEM_RXTMEM_FIELD;
+#define DMA_CONFIG_TARGET_MEM_RXTMEM_FIELD_MASK  0x00000001
+#define DMA_CONFIG_TARGET_MEM_RXTMEM_FIELD_WIDTH 1
+#define DMA_CONFIG_TARGET_MEM_RXTMEM_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_TARGET_MEM_RESERVED0_FIELD;
+#define DMA_CONFIG_TARGET_MEM_RESERVED0_FIELD_MASK  0x000000fe
+#define DMA_CONFIG_TARGET_MEM_RESERVED0_FIELD_WIDTH 7
+#define DMA_CONFIG_TARGET_MEM_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec DMA_CONFIG_TARGET_MEM_TXTMEM_FIELD;
+#define DMA_CONFIG_TARGET_MEM_TXTMEM_FIELD_MASK  0x00000100
+#define DMA_CONFIG_TARGET_MEM_TXTMEM_FIELD_WIDTH 1
+#define DMA_CONFIG_TARGET_MEM_TXTMEM_FIELD_SHIFT 8
+
+extern const ru_field_rec DMA_CONFIG_TARGET_MEM_RESERVED1_FIELD;
+#define DMA_CONFIG_TARGET_MEM_RESERVED1_FIELD_MASK  0xfffffe00
+#define DMA_CONFIG_TARGET_MEM_RESERVED1_FIELD_WIDTH 23
+#define DMA_CONFIG_TARGET_MEM_RESERVED1_FIELD_SHIFT 9
+
+extern const ru_field_rec DMA_CONFIG_PTRRST_RSTVEC_FIELD;
+#define DMA_CONFIG_PTRRST_RSTVEC_FIELD_MASK  0x0000ffff
+#define DMA_CONFIG_PTRRST_RSTVEC_FIELD_WIDTH 16
+#define DMA_CONFIG_PTRRST_RSTVEC_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_PTRRST_RESERVED0_FIELD;
+#define DMA_CONFIG_PTRRST_RESERVED0_FIELD_MASK  0xffff0000
+#define DMA_CONFIG_PTRRST_RESERVED0_FIELD_WIDTH 16
+#define DMA_CONFIG_PTRRST_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_DEST_FIELD;
+#define DMA_CONFIG_BBROUTEOVRD_DEST_FIELD_MASK  0x0000003f
+#define DMA_CONFIG_BBROUTEOVRD_DEST_FIELD_WIDTH 6
+#define DMA_CONFIG_BBROUTEOVRD_DEST_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD;
+#define DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD_MASK  0x000000c0
+#define DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD_WIDTH 2
+#define DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD;
+#define DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD_MASK  0x0003ff00
+#define DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD_WIDTH 10
+#define DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD_SHIFT 8
+
+extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD;
+#define DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD_MASK  0x00fc0000
+#define DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD_WIDTH 6
+#define DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD_SHIFT 18
+
+extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD;
+#define DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD_MASK  0x01000000
+#define DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD_WIDTH 1
+#define DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD_SHIFT 24
+
+extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD;
+#define DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD_MASK  0xfe000000
+#define DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD_WIDTH 7
+#define DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD_SHIFT 25
+
+extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD;
+#define DMA_CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK  0x00000001
+#define DMA_CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1
+#define DMA_CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_RESERVED0_FIELD;
+#define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK  0x000000fe
+#define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7
+#define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_FIELD;
+#define DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK  0x0000ff00
+#define DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8
+#define DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8
+
+extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD;
+#define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK  0x00010000
+#define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1
+#define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_RESERVED1_FIELD;
+#define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK  0x000e0000
+#define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3
+#define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD;
+#define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK  0x00700000
+#define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3
+#define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20
+
+extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_RESERVED2_FIELD;
+#define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK  0x00800000
+#define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1
+#define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23
+
+extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD;
+#define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK  0xff000000
+#define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8
+#define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24
+
+extern const ru_field_rec DMA_CONFIG_UBUS_DPIDS_DDR_FIELD;
+#define DMA_CONFIG_UBUS_DPIDS_DDR_FIELD_MASK  0x000000ff
+#define DMA_CONFIG_UBUS_DPIDS_DDR_FIELD_WIDTH 8
+#define DMA_CONFIG_UBUS_DPIDS_DDR_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_UBUS_DPIDS_SRAM_FIELD;
+#define DMA_CONFIG_UBUS_DPIDS_SRAM_FIELD_MASK  0x0000ff00
+#define DMA_CONFIG_UBUS_DPIDS_SRAM_FIELD_WIDTH 8
+#define DMA_CONFIG_UBUS_DPIDS_SRAM_FIELD_SHIFT 8
+
+extern const ru_field_rec DMA_CONFIG_UBUS_DPIDS_RESERVED0_FIELD;
+#define DMA_CONFIG_UBUS_DPIDS_RESERVED0_FIELD_MASK  0xffff0000
+#define DMA_CONFIG_UBUS_DPIDS_RESERVED0_FIELD_WIDTH 16
+#define DMA_CONFIG_UBUS_DPIDS_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec DMA_CONFIG_MAX_OTF_MAX_DDR_FIELD;
+#define DMA_CONFIG_MAX_OTF_MAX_DDR_FIELD_MASK  0x0000ffff
+#define DMA_CONFIG_MAX_OTF_MAX_DDR_FIELD_WIDTH 16
+#define DMA_CONFIG_MAX_OTF_MAX_DDR_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_MAX_OTF_MAX_SRAM_FIELD;
+#define DMA_CONFIG_MAX_OTF_MAX_SRAM_FIELD_MASK  0xffff0000
+#define DMA_CONFIG_MAX_OTF_MAX_SRAM_FIELD_WIDTH 16
+#define DMA_CONFIG_MAX_OTF_MAX_SRAM_FIELD_SHIFT 16
+
+extern const ru_field_rec DMA_CONFIG_UBUS_CREDITS_DDR_FIELD;
+#define DMA_CONFIG_UBUS_CREDITS_DDR_FIELD_MASK  0x0000001f
+#define DMA_CONFIG_UBUS_CREDITS_DDR_FIELD_WIDTH 5
+#define DMA_CONFIG_UBUS_CREDITS_DDR_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_UBUS_CREDITS_RESERVED0_FIELD;
+#define DMA_CONFIG_UBUS_CREDITS_RESERVED0_FIELD_MASK  0x000000e0
+#define DMA_CONFIG_UBUS_CREDITS_RESERVED0_FIELD_WIDTH 3
+#define DMA_CONFIG_UBUS_CREDITS_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec DMA_CONFIG_UBUS_CREDITS_SRAM_FIELD;
+#define DMA_CONFIG_UBUS_CREDITS_SRAM_FIELD_MASK  0x00001f00
+#define DMA_CONFIG_UBUS_CREDITS_SRAM_FIELD_WIDTH 5
+#define DMA_CONFIG_UBUS_CREDITS_SRAM_FIELD_SHIFT 8
+
+extern const ru_field_rec DMA_CONFIG_UBUS_CREDITS_RESERVED1_FIELD;
+#define DMA_CONFIG_UBUS_CREDITS_RESERVED1_FIELD_MASK  0x0000e000
+#define DMA_CONFIG_UBUS_CREDITS_RESERVED1_FIELD_WIDTH 3
+#define DMA_CONFIG_UBUS_CREDITS_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec DMA_CONFIG_UBUS_CREDITS_DDR_SET_FIELD;
+#define DMA_CONFIG_UBUS_CREDITS_DDR_SET_FIELD_MASK  0x00010000
+#define DMA_CONFIG_UBUS_CREDITS_DDR_SET_FIELD_WIDTH 1
+#define DMA_CONFIG_UBUS_CREDITS_DDR_SET_FIELD_SHIFT 16
+
+extern const ru_field_rec DMA_CONFIG_UBUS_CREDITS_SRAM_SET_FIELD;
+#define DMA_CONFIG_UBUS_CREDITS_SRAM_SET_FIELD_MASK  0x00020000
+#define DMA_CONFIG_UBUS_CREDITS_SRAM_SET_FIELD_WIDTH 1
+#define DMA_CONFIG_UBUS_CREDITS_SRAM_SET_FIELD_SHIFT 17
+
+extern const ru_field_rec DMA_CONFIG_UBUS_CREDITS_RESERVED2_FIELD;
+#define DMA_CONFIG_UBUS_CREDITS_RESERVED2_FIELD_MASK  0xfffc0000
+#define DMA_CONFIG_UBUS_CREDITS_RESERVED2_FIELD_WIDTH 14
+#define DMA_CONFIG_UBUS_CREDITS_RESERVED2_FIELD_SHIFT 18
+
+extern const ru_field_rec DMA_CONFIG_PSRAM_BASE_BASE_FIELD;
+#define DMA_CONFIG_PSRAM_BASE_BASE_FIELD_MASK  0xffffffff
+#define DMA_CONFIG_PSRAM_BASE_BASE_FIELD_WIDTH 32
+#define DMA_CONFIG_PSRAM_BASE_BASE_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_CONFIG_DDR_BASE_BASE_FIELD;
+#define DMA_CONFIG_DDR_BASE_BASE_FIELD_MASK  0xffffffff
+#define DMA_CONFIG_DDR_BASE_BASE_FIELD_WIDTH 32
+#define DMA_CONFIG_DDR_BASE_BASE_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_NEMPTY_NEMPTY_FIELD;
+#define DMA_DEBUG_NEMPTY_NEMPTY_FIELD_MASK  0x0000ffff
+#define DMA_DEBUG_NEMPTY_NEMPTY_FIELD_WIDTH 16
+#define DMA_DEBUG_NEMPTY_NEMPTY_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_NEMPTY_RESERVED0_FIELD;
+#define DMA_DEBUG_NEMPTY_RESERVED0_FIELD_MASK  0xffff0000
+#define DMA_DEBUG_NEMPTY_RESERVED0_FIELD_WIDTH 16
+#define DMA_DEBUG_NEMPTY_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec DMA_DEBUG_URGNT_URGNT_FIELD;
+#define DMA_DEBUG_URGNT_URGNT_FIELD_MASK  0x0000ffff
+#define DMA_DEBUG_URGNT_URGNT_FIELD_WIDTH 16
+#define DMA_DEBUG_URGNT_URGNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_URGNT_RESERVED0_FIELD;
+#define DMA_DEBUG_URGNT_RESERVED0_FIELD_MASK  0xffff0000
+#define DMA_DEBUG_URGNT_RESERVED0_FIELD_WIDTH 16
+#define DMA_DEBUG_URGNT_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec DMA_DEBUG_SELSRC_SEL_SRC_FIELD;
+#define DMA_DEBUG_SELSRC_SEL_SRC_FIELD_MASK  0x0000003f
+#define DMA_DEBUG_SELSRC_SEL_SRC_FIELD_WIDTH 6
+#define DMA_DEBUG_SELSRC_SEL_SRC_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_SELSRC_RESERVED0_FIELD;
+#define DMA_DEBUG_SELSRC_RESERVED0_FIELD_MASK  0xffffffc0
+#define DMA_DEBUG_SELSRC_RESERVED0_FIELD_WIDTH 26
+#define DMA_DEBUG_SELSRC_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD;
+#define DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD_MASK  0x0000003f
+#define DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD_WIDTH 6
+#define DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD;
+#define DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD_MASK  0xffffffc0
+#define DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD_WIDTH 26
+#define DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD;
+#define DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD_MASK  0x0000003f
+#define DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD_WIDTH 6
+#define DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD;
+#define DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD_MASK  0xffffffc0
+#define DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD_WIDTH 26
+#define DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD;
+#define DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD_MASK  0xffffffff
+#define DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD_WIDTH 32
+#define DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD;
+#define DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD_MASK  0xffffffff
+#define DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD_WIDTH 32
+#define DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_UBUSCRDT_DDR_FIELD;
+#define DMA_DEBUG_UBUSCRDT_DDR_FIELD_MASK  0x0000001f
+#define DMA_DEBUG_UBUSCRDT_DDR_FIELD_WIDTH 5
+#define DMA_DEBUG_UBUSCRDT_DDR_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_UBUSCRDT_RESERVED0_FIELD;
+#define DMA_DEBUG_UBUSCRDT_RESERVED0_FIELD_MASK  0x000000e0
+#define DMA_DEBUG_UBUSCRDT_RESERVED0_FIELD_WIDTH 3
+#define DMA_DEBUG_UBUSCRDT_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec DMA_DEBUG_UBUSCRDT_SRAM_FIELD;
+#define DMA_DEBUG_UBUSCRDT_SRAM_FIELD_MASK  0x00001f00
+#define DMA_DEBUG_UBUSCRDT_SRAM_FIELD_WIDTH 5
+#define DMA_DEBUG_UBUSCRDT_SRAM_FIELD_SHIFT 8
+
+extern const ru_field_rec DMA_DEBUG_UBUSCRDT_RESERVED1_FIELD;
+#define DMA_DEBUG_UBUSCRDT_RESERVED1_FIELD_MASK  0xffffe000
+#define DMA_DEBUG_UBUSCRDT_RESERVED1_FIELD_WIDTH 19
+#define DMA_DEBUG_UBUSCRDT_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec DMA_DEBUG_UBUSBYTES_DDR_FIELD;
+#define DMA_DEBUG_UBUSBYTES_DDR_FIELD_MASK  0x0000ffff
+#define DMA_DEBUG_UBUSBYTES_DDR_FIELD_WIDTH 16
+#define DMA_DEBUG_UBUSBYTES_DDR_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_UBUSBYTES_SRAM_FIELD;
+#define DMA_DEBUG_UBUSBYTES_SRAM_FIELD_MASK  0xffff0000
+#define DMA_DEBUG_UBUSBYTES_SRAM_FIELD_WIDTH 16
+#define DMA_DEBUG_UBUSBYTES_SRAM_FIELD_SHIFT 16
+
+extern const ru_field_rec DMA_DEBUG_ON_THE_FLY_OTF_FIELD;
+#define DMA_DEBUG_ON_THE_FLY_OTF_FIELD_MASK  0x0000003f
+#define DMA_DEBUG_ON_THE_FLY_OTF_FIELD_WIDTH 6
+#define DMA_DEBUG_ON_THE_FLY_OTF_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_ON_THE_FLY_RESERVED0_FIELD;
+#define DMA_DEBUG_ON_THE_FLY_RESERVED0_FIELD_MASK  0xffffffc0
+#define DMA_DEBUG_ON_THE_FLY_RESERVED0_FIELD_WIDTH 26
+#define DMA_DEBUG_ON_THE_FLY_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec DMA_DEBUG_DBG_SEL_DBGSEL_FIELD;
+#define DMA_DEBUG_DBG_SEL_DBGSEL_FIELD_MASK  0x00000007
+#define DMA_DEBUG_DBG_SEL_DBGSEL_FIELD_WIDTH 3
+#define DMA_DEBUG_DBG_SEL_DBGSEL_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_DBG_SEL_RESERVED0_FIELD;
+#define DMA_DEBUG_DBG_SEL_RESERVED0_FIELD_MASK  0xfffffff8
+#define DMA_DEBUG_DBG_SEL_RESERVED0_FIELD_WIDTH 29
+#define DMA_DEBUG_DBG_SEL_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec DMA_DEBUG_DEBUGOUT_DBG_FIELD;
+#define DMA_DEBUG_DEBUGOUT_DBG_FIELD_MASK  0xffffffff
+#define DMA_DEBUG_DEBUGOUT_DBG_FIELD_WIDTH 32
+#define DMA_DEBUG_DEBUGOUT_DBG_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_RDADD_ADDRESS_FIELD;
+#define DMA_DEBUG_RDADD_ADDRESS_FIELD_MASK  0x000003ff
+#define DMA_DEBUG_RDADD_ADDRESS_FIELD_WIDTH 10
+#define DMA_DEBUG_RDADD_ADDRESS_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_RDADD_RESERVED0_FIELD;
+#define DMA_DEBUG_RDADD_RESERVED0_FIELD_MASK  0x0000fc00
+#define DMA_DEBUG_RDADD_RESERVED0_FIELD_WIDTH 6
+#define DMA_DEBUG_RDADD_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec DMA_DEBUG_RDADD_DATACS_FIELD;
+#define DMA_DEBUG_RDADD_DATACS_FIELD_MASK  0x00010000
+#define DMA_DEBUG_RDADD_DATACS_FIELD_WIDTH 1
+#define DMA_DEBUG_RDADD_DATACS_FIELD_SHIFT 16
+
+extern const ru_field_rec DMA_DEBUG_RDADD_CDCS_FIELD;
+#define DMA_DEBUG_RDADD_CDCS_FIELD_MASK  0x00020000
+#define DMA_DEBUG_RDADD_CDCS_FIELD_WIDTH 1
+#define DMA_DEBUG_RDADD_CDCS_FIELD_SHIFT 17
+
+extern const ru_field_rec DMA_DEBUG_RDADD_RRCS_FIELD;
+#define DMA_DEBUG_RDADD_RRCS_FIELD_MASK  0x00040000
+#define DMA_DEBUG_RDADD_RRCS_FIELD_WIDTH 1
+#define DMA_DEBUG_RDADD_RRCS_FIELD_SHIFT 18
+
+extern const ru_field_rec DMA_DEBUG_RDADD_RESERVED1_FIELD;
+#define DMA_DEBUG_RDADD_RESERVED1_FIELD_MASK  0xfff80000
+#define DMA_DEBUG_RDADD_RESERVED1_FIELD_WIDTH 13
+#define DMA_DEBUG_RDADD_RESERVED1_FIELD_SHIFT 19
+
+extern const ru_field_rec DMA_DEBUG_RDVALID_VALID_FIELD;
+#define DMA_DEBUG_RDVALID_VALID_FIELD_MASK  0x00000001
+#define DMA_DEBUG_RDVALID_VALID_FIELD_WIDTH 1
+#define DMA_DEBUG_RDVALID_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_RDVALID_RESERVED0_FIELD;
+#define DMA_DEBUG_RDVALID_RESERVED0_FIELD_MASK  0xfffffffe
+#define DMA_DEBUG_RDVALID_RESERVED0_FIELD_WIDTH 31
+#define DMA_DEBUG_RDVALID_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec DMA_DEBUG_RDDATARDY_READY_FIELD;
+#define DMA_DEBUG_RDDATARDY_READY_FIELD_MASK  0x00000001
+#define DMA_DEBUG_RDDATARDY_READY_FIELD_WIDTH 1
+#define DMA_DEBUG_RDDATARDY_READY_FIELD_SHIFT 0
+
+extern const ru_field_rec DMA_DEBUG_RDDATARDY_RESERVED0_FIELD;
+#define DMA_DEBUG_RDDATARDY_RESERVED0_FIELD_MASK  0xfffffffe
+#define DMA_DEBUG_RDDATARDY_RESERVED0_FIELD_WIDTH 31
+#define DMA_DEBUG_RDDATARDY_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec DMA_DEBUG_RDDATA_DATA_FIELD;
+#define DMA_DEBUG_RDDATA_DATA_FIELD_MASK  0xffffffff
+#define DMA_DEBUG_RDDATA_DATA_FIELD_WIDTH 32
+#define DMA_DEBUG_RDDATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_MEMORY_DATA_DATA_FIELD;
+#define PSRAM_MEMORY_DATA_DATA_FIELD_MASK  0xffffffff
+#define PSRAM_MEMORY_DATA_DATA_FIELD_WIDTH 32
+#define PSRAM_MEMORY_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_PERM_EN_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_PERM_EN_FIELD_MASK  0x00000001
+#define PSRAM_CONFIGURATIONS_CTRL_PERM_EN_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_PERM_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_COMB_EN_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_COMB_EN_FIELD_MASK  0x00000002
+#define PSRAM_CONFIGURATIONS_CTRL_COMB_EN_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_COMB_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_COMB_FULL_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_COMB_FULL_FIELD_MASK  0x00000004
+#define PSRAM_CONFIGURATIONS_CTRL_COMB_FULL_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_COMB_FULL_FIELD_SHIFT 2
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_BANKS8_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_BANKS8_FIELD_MASK  0x00000008
+#define PSRAM_CONFIGURATIONS_CTRL_BANKS8_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_BANKS8_FIELD_SHIFT 3
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB0_REQIN_ESWAP_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_UB0_REQIN_ESWAP_FIELD_MASK  0x00000010
+#define PSRAM_CONFIGURATIONS_CTRL_UB0_REQIN_ESWAP_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_UB0_REQIN_ESWAP_FIELD_SHIFT 4
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB0_REPOUT_ESWAP_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_UB0_REPOUT_ESWAP_FIELD_MASK  0x00000020
+#define PSRAM_CONFIGURATIONS_CTRL_UB0_REPOUT_ESWAP_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_UB0_REPOUT_ESWAP_FIELD_SHIFT 5
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB1_REQIN_ESWAP_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_UB1_REQIN_ESWAP_FIELD_MASK  0x00000040
+#define PSRAM_CONFIGURATIONS_CTRL_UB1_REQIN_ESWAP_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_UB1_REQIN_ESWAP_FIELD_SHIFT 6
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB1_REPOUT_ESWAP_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_UB1_REPOUT_ESWAP_FIELD_MASK  0x00000080
+#define PSRAM_CONFIGURATIONS_CTRL_UB1_REPOUT_ESWAP_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_UB1_REPOUT_ESWAP_FIELD_SHIFT 7
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB2_REQIN_ESWAP_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_UB2_REQIN_ESWAP_FIELD_MASK  0x00000100
+#define PSRAM_CONFIGURATIONS_CTRL_UB2_REQIN_ESWAP_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_UB2_REQIN_ESWAP_FIELD_SHIFT 8
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB2_REPOUT_ESWAP_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_UB2_REPOUT_ESWAP_FIELD_MASK  0x00000200
+#define PSRAM_CONFIGURATIONS_CTRL_UB2_REPOUT_ESWAP_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_UB2_REPOUT_ESWAP_FIELD_SHIFT 9
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB3_REQIN_ESWAP_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_UB3_REQIN_ESWAP_FIELD_MASK  0x00000400
+#define PSRAM_CONFIGURATIONS_CTRL_UB3_REQIN_ESWAP_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_UB3_REQIN_ESWAP_FIELD_SHIFT 10
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB3_REPOUT_ESWAP_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_UB3_REPOUT_ESWAP_FIELD_MASK  0x00000800
+#define PSRAM_CONFIGURATIONS_CTRL_UB3_REPOUT_ESWAP_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_UB3_REPOUT_ESWAP_FIELD_SHIFT 11
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC0_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC0_FIELD_MASK  0x00001000
+#define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC0_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC0_FIELD_SHIFT 12
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC1_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC1_FIELD_MASK  0x00002000
+#define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC1_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC1_FIELD_SHIFT 13
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC2_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC2_FIELD_MASK  0x00004000
+#define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC2_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC2_FIELD_SHIFT 14
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_WT_0_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_WT_0_FIELD_MASK  0x00038000
+#define PSRAM_CONFIGURATIONS_CTRL_WT_0_FIELD_WIDTH 3
+#define PSRAM_CONFIGURATIONS_CTRL_WT_0_FIELD_SHIFT 15
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_WT_1_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_WT_1_FIELD_MASK  0x001c0000
+#define PSRAM_CONFIGURATIONS_CTRL_WT_1_FIELD_WIDTH 3
+#define PSRAM_CONFIGURATIONS_CTRL_WT_1_FIELD_SHIFT 18
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_WT_2_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_WT_2_FIELD_MASK  0x00e00000
+#define PSRAM_CONFIGURATIONS_CTRL_WT_2_FIELD_WIDTH 3
+#define PSRAM_CONFIGURATIONS_CTRL_WT_2_FIELD_SHIFT 21
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_ARB_RR_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_ARB_RR_FIELD_MASK  0x01000000
+#define PSRAM_CONFIGURATIONS_CTRL_ARB_RR_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_ARB_RR_FIELD_SHIFT 24
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_SCRM_EN_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_SCRM_EN_FIELD_MASK  0x02000000
+#define PSRAM_CONFIGURATIONS_CTRL_SCRM_EN_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CTRL_SCRM_EN_FIELD_SHIFT 25
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_RESERVED0_FIELD;
+#define PSRAM_CONFIGURATIONS_CTRL_RESERVED0_FIELD_MASK  0xfc000000
+#define PSRAM_CONFIGURATIONS_CTRL_RESERVED0_FIELD_WIDTH 6
+#define PSRAM_CONFIGURATIONS_CTRL_RESERVED0_FIELD_SHIFT 26
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_SCRM_SEED_VAL_FIELD;
+#define PSRAM_CONFIGURATIONS_SCRM_SEED_VAL_FIELD_MASK  0xffffffff
+#define PSRAM_CONFIGURATIONS_SCRM_SEED_VAL_FIELD_WIDTH 32
+#define PSRAM_CONFIGURATIONS_SCRM_SEED_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_SCRM_ADDR_VAL_FIELD;
+#define PSRAM_CONFIGURATIONS_SCRM_ADDR_VAL_FIELD_MASK  0xffffffff
+#define PSRAM_CONFIGURATIONS_SCRM_ADDR_VAL_FIELD_WIDTH 32
+#define PSRAM_CONFIGURATIONS_SCRM_ADDR_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD;
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK  0x00000001
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD;
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK  0x000000fe
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD;
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK  0x0000ff00
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD;
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK  0x00010000
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD;
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK  0x000e0000
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD;
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK  0x00700000
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD;
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK  0x00800000
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23
+
+extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD;
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK  0xff000000
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL0MEN_FIELD;
+#define PSRAM_PM_COUNTERS_MUEN_CL0MEN_FIELD_MASK  0x00000001
+#define PSRAM_PM_COUNTERS_MUEN_CL0MEN_FIELD_WIDTH 1
+#define PSRAM_PM_COUNTERS_MUEN_CL0MEN_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL1MEN_FIELD;
+#define PSRAM_PM_COUNTERS_MUEN_CL1MEN_FIELD_MASK  0x00000002
+#define PSRAM_PM_COUNTERS_MUEN_CL1MEN_FIELD_WIDTH 1
+#define PSRAM_PM_COUNTERS_MUEN_CL1MEN_FIELD_SHIFT 1
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL2MEN_FIELD;
+#define PSRAM_PM_COUNTERS_MUEN_CL2MEN_FIELD_MASK  0x00000004
+#define PSRAM_PM_COUNTERS_MUEN_CL2MEN_FIELD_WIDTH 1
+#define PSRAM_PM_COUNTERS_MUEN_CL2MEN_FIELD_SHIFT 2
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL3MEN_FIELD;
+#define PSRAM_PM_COUNTERS_MUEN_CL3MEN_FIELD_MASK  0x00000008
+#define PSRAM_PM_COUNTERS_MUEN_CL3MEN_FIELD_WIDTH 1
+#define PSRAM_PM_COUNTERS_MUEN_CL3MEN_FIELD_SHIFT 3
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL4MEN_FIELD;
+#define PSRAM_PM_COUNTERS_MUEN_CL4MEN_FIELD_MASK  0x00000010
+#define PSRAM_PM_COUNTERS_MUEN_CL4MEN_FIELD_WIDTH 1
+#define PSRAM_PM_COUNTERS_MUEN_CL4MEN_FIELD_SHIFT 4
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL5MEN_FIELD;
+#define PSRAM_PM_COUNTERS_MUEN_CL5MEN_FIELD_MASK  0x00000020
+#define PSRAM_PM_COUNTERS_MUEN_CL5MEN_FIELD_WIDTH 1
+#define PSRAM_PM_COUNTERS_MUEN_CL5MEN_FIELD_SHIFT 5
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL6MEN_FIELD;
+#define PSRAM_PM_COUNTERS_MUEN_CL6MEN_FIELD_MASK  0x00000040
+#define PSRAM_PM_COUNTERS_MUEN_CL6MEN_FIELD_WIDTH 1
+#define PSRAM_PM_COUNTERS_MUEN_CL6MEN_FIELD_SHIFT 6
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_RESERVED0_FIELD;
+#define PSRAM_PM_COUNTERS_MUEN_RESERVED0_FIELD_MASK  0xffffff80
+#define PSRAM_PM_COUNTERS_MUEN_RESERVED0_FIELD_WIDTH 25
+#define PSRAM_PM_COUNTERS_MUEN_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BWCL_TW_FIELD;
+#define PSRAM_PM_COUNTERS_BWCL_TW_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_BWCL_TW_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_BWCL_TW_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BWEN_BWCEN_FIELD;
+#define PSRAM_PM_COUNTERS_BWEN_BWCEN_FIELD_MASK  0x00000001
+#define PSRAM_PM_COUNTERS_BWEN_BWCEN_FIELD_WIDTH 1
+#define PSRAM_PM_COUNTERS_BWEN_BWCEN_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BWEN_RESERVED0_FIELD;
+#define PSRAM_PM_COUNTERS_BWEN_RESERVED0_FIELD_MASK  0x000000fe
+#define PSRAM_PM_COUNTERS_BWEN_RESERVED0_FIELD_WIDTH 7
+#define PSRAM_PM_COUNTERS_BWEN_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BWEN_CBWCEN_FIELD;
+#define PSRAM_PM_COUNTERS_BWEN_CBWCEN_FIELD_MASK  0x00000100
+#define PSRAM_PM_COUNTERS_BWEN_CBWCEN_FIELD_WIDTH 1
+#define PSRAM_PM_COUNTERS_BWEN_CBWCEN_FIELD_SHIFT 8
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BWEN_RESERVED1_FIELD;
+#define PSRAM_PM_COUNTERS_BWEN_RESERVED1_FIELD_MASK  0xfffffe00
+#define PSRAM_PM_COUNTERS_BWEN_RESERVED1_FIELD_WIDTH 23
+#define PSRAM_PM_COUNTERS_BWEN_RESERVED1_FIELD_SHIFT 9
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_MAX_TIME_MAX_FIELD;
+#define PSRAM_PM_COUNTERS_MAX_TIME_MAX_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_MAX_TIME_MAX_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_MAX_TIME_MAX_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_ACC_TIME_MAX_FIELD;
+#define PSRAM_PM_COUNTERS_ACC_TIME_MAX_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_ACC_TIME_MAX_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_ACC_TIME_MAX_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_ACC_REQ_REQ_FIELD;
+#define PSRAM_PM_COUNTERS_ACC_REQ_REQ_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_ACC_REQ_REQ_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_ACC_REQ_REQ_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_FIELD;
+#define PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_FIELD;
+#define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_FIELD;
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_FIELD;
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_FIELD;
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_FIELD;
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_FIELD;
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_FIELD;
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_FIELD;
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_FIELD;
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_ARB_REQ_VAL_FIELD;
+#define PSRAM_PM_COUNTERS_ARB_REQ_VAL_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_ARB_REQ_VAL_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_ARB_REQ_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_ARB_ARB_VAL_FIELD;
+#define PSRAM_PM_COUNTERS_ARB_ARB_VAL_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_ARB_ARB_VAL_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_ARB_ARB_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_ARB_COMB_VAL_FIELD;
+#define PSRAM_PM_COUNTERS_ARB_COMB_VAL_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_ARB_COMB_VAL_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_ARB_COMB_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_FIELD;
+#define PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_FIELD;
+#define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_FIELD_MASK  0xffffffff
+#define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_FIELD_WIDTH 32
+#define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBGSEL_VS_FIELD;
+#define PSRAM_DEBUG_DBGSEL_VS_FIELD_MASK  0x000000ff
+#define PSRAM_DEBUG_DBGSEL_VS_FIELD_WIDTH 8
+#define PSRAM_DEBUG_DBGSEL_VS_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBGSEL_RESERVED0_FIELD;
+#define PSRAM_DEBUG_DBGSEL_RESERVED0_FIELD_MASK  0xffffff00
+#define PSRAM_DEBUG_DBGSEL_RESERVED0_FIELD_WIDTH 24
+#define PSRAM_DEBUG_DBGSEL_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec PSRAM_DEBUG_DBGBUS_VB_FIELD;
+#define PSRAM_DEBUG_DBGBUS_VB_FIELD_MASK  0xffffffff
+#define PSRAM_DEBUG_DBGBUS_VB_FIELD_WIDTH 32
+#define PSRAM_DEBUG_DBGBUS_VB_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_MIPSC_REQ_FIELD;
+#define PSRAM_DEBUG_REQ_VEC_MIPSC_REQ_FIELD_MASK  0x00000001
+#define PSRAM_DEBUG_REQ_VEC_MIPSC_REQ_FIELD_WIDTH 1
+#define PSRAM_DEBUG_REQ_VEC_MIPSC_REQ_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_RNRA_REQ_FIELD;
+#define PSRAM_DEBUG_REQ_VEC_RNRA_REQ_FIELD_MASK  0x00000002
+#define PSRAM_DEBUG_REQ_VEC_RNRA_REQ_FIELD_WIDTH 1
+#define PSRAM_DEBUG_REQ_VEC_RNRA_REQ_FIELD_SHIFT 1
+
+extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_RNRB_REQ_FIELD;
+#define PSRAM_DEBUG_REQ_VEC_RNRB_REQ_FIELD_MASK  0x00000004
+#define PSRAM_DEBUG_REQ_VEC_RNRB_REQ_FIELD_WIDTH 1
+#define PSRAM_DEBUG_REQ_VEC_RNRB_REQ_FIELD_SHIFT 2
+
+extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_SDMA_REQ_FIELD;
+#define PSRAM_DEBUG_REQ_VEC_SDMA_REQ_FIELD_MASK  0x00000008
+#define PSRAM_DEBUG_REQ_VEC_SDMA_REQ_FIELD_WIDTH 1
+#define PSRAM_DEBUG_REQ_VEC_SDMA_REQ_FIELD_SHIFT 3
+
+extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_MIPSD_REQ_FIELD;
+#define PSRAM_DEBUG_REQ_VEC_MIPSD_REQ_FIELD_MASK  0x00000010
+#define PSRAM_DEBUG_REQ_VEC_MIPSD_REQ_FIELD_WIDTH 1
+#define PSRAM_DEBUG_REQ_VEC_MIPSD_REQ_FIELD_SHIFT 4
+
+extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_MIPSDMA_REQ_FIELD;
+#define PSRAM_DEBUG_REQ_VEC_MIPSDMA_REQ_FIELD_MASK  0x00000020
+#define PSRAM_DEBUG_REQ_VEC_MIPSDMA_REQ_FIELD_WIDTH 1
+#define PSRAM_DEBUG_REQ_VEC_MIPSDMA_REQ_FIELD_SHIFT 5
+
+extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_RESERVED0_FIELD;
+#define PSRAM_DEBUG_REQ_VEC_RESERVED0_FIELD_MASK  0xffffffc0
+#define PSRAM_DEBUG_REQ_VEC_RESERVED0_FIELD_WIDTH 26
+#define PSRAM_DEBUG_REQ_VEC_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_FIELD_MASK  0x00000007
+#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_FIELD_WIDTH 3
+#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED0_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED0_FIELD_MASK  0x00000008
+#define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED0_FIELD_WIDTH 1
+#define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_FIELD_MASK  0x0000fff0
+#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_FIELD_WIDTH 12
+#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_FIELD_SHIFT 4
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_CAP_WR_EN_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_WR_EN_FIELD_MASK  0x00010000
+#define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_WR_EN_FIELD_WIDTH 1
+#define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_WR_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_CAP_RD_EN_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_RD_EN_FIELD_MASK  0x00020000
+#define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_RD_EN_FIELD_WIDTH 1
+#define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_RD_EN_FIELD_SHIFT 17
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED1_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED1_FIELD_MASK  0xfffc0000
+#define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED1_FIELD_WIDTH 14
+#define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED1_FIELD_SHIFT 18
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_FIELD_MASK  0x000000ff
+#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_FIELD_WIDTH 8
+#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_FIELD_MASK  0x0000ff00
+#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_FIELD_WIDTH 8
+#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_FIELD_SHIFT 8
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG2_WR_CAP_CNT_RST_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_CFG2_WR_CAP_CNT_RST_FIELD_MASK  0x00010000
+#define PSRAM_DEBUG_DBG_CAP_CFG2_WR_CAP_CNT_RST_FIELD_WIDTH 1
+#define PSRAM_DEBUG_DBG_CAP_CFG2_WR_CAP_CNT_RST_FIELD_SHIFT 16
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG2_RD_CAP_CNT_RST_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_CFG2_RD_CAP_CNT_RST_FIELD_MASK  0x00020000
+#define PSRAM_DEBUG_DBG_CAP_CFG2_RD_CAP_CNT_RST_FIELD_WIDTH 1
+#define PSRAM_DEBUG_DBG_CAP_CFG2_RD_CAP_CNT_RST_FIELD_SHIFT 17
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG2_RESERVED0_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_CFG2_RESERVED0_FIELD_MASK  0xfffc0000
+#define PSRAM_DEBUG_DBG_CAP_CFG2_RESERVED0_FIELD_WIDTH 14
+#define PSRAM_DEBUG_DBG_CAP_CFG2_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_FIELD_MASK  0x000000ff
+#define PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_FIELD_WIDTH 8
+#define PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_FIELD_MASK  0x0000ff00
+#define PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_FIELD_WIDTH 8
+#define PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_FIELD_SHIFT 8
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_W0_CV_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_W0_CV_FIELD_MASK  0xffffffff
+#define PSRAM_DEBUG_DBG_CAP_W0_CV_FIELD_WIDTH 32
+#define PSRAM_DEBUG_DBG_CAP_W0_CV_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_W1_CV_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_W1_CV_FIELD_MASK  0xffffffff
+#define PSRAM_DEBUG_DBG_CAP_W1_CV_FIELD_WIDTH 32
+#define PSRAM_DEBUG_DBG_CAP_W1_CV_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_W2_CV_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_W2_CV_FIELD_MASK  0xffffffff
+#define PSRAM_DEBUG_DBG_CAP_W2_CV_FIELD_WIDTH 32
+#define PSRAM_DEBUG_DBG_CAP_W2_CV_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_W3_CV_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_W3_CV_FIELD_MASK  0xffffffff
+#define PSRAM_DEBUG_DBG_CAP_W3_CV_FIELD_WIDTH 32
+#define PSRAM_DEBUG_DBG_CAP_W3_CV_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_WMSK_CV_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_WMSK_CV_FIELD_MASK  0xffffffff
+#define PSRAM_DEBUG_DBG_CAP_WMSK_CV_FIELD_WIDTH 32
+#define PSRAM_DEBUG_DBG_CAP_WMSK_CV_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_R0_CV_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_R0_CV_FIELD_MASK  0xffffffff
+#define PSRAM_DEBUG_DBG_CAP_R0_CV_FIELD_WIDTH 32
+#define PSRAM_DEBUG_DBG_CAP_R0_CV_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_R1_CV_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_R1_CV_FIELD_MASK  0xffffffff
+#define PSRAM_DEBUG_DBG_CAP_R1_CV_FIELD_WIDTH 32
+#define PSRAM_DEBUG_DBG_CAP_R1_CV_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_R2_CV_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_R2_CV_FIELD_MASK  0xffffffff
+#define PSRAM_DEBUG_DBG_CAP_R2_CV_FIELD_WIDTH 32
+#define PSRAM_DEBUG_DBG_CAP_R2_CV_FIELD_SHIFT 0
+
+extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_R3_CV_FIELD;
+#define PSRAM_DEBUG_DBG_CAP_R3_CV_FIELD_MASK  0xffffffff
+#define PSRAM_DEBUG_DBG_CAP_R3_CV_FIELD_WIDTH 32
+#define PSRAM_DEBUG_DBG_CAP_R3_CV_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_IPG_HD_BKP_CNTL_RESERVED0_FIELD;
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_RESERVED0_FIELD_MASK  0xffffff80
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_RESERVED0_FIELD_WIDTH 25
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec UNIMAC_RDP_IPG_HD_BKP_CNTL_IPG_CONFIG_RX_FIELD;
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_IPG_CONFIG_RX_FIELD_MASK  0x0000007c
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_IPG_CONFIG_RX_FIELD_WIDTH 5
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_IPG_CONFIG_RX_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_IPG_HD_BKP_CNTL_HD_FC_BKOFF_OK_FIELD;
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_HD_FC_BKOFF_OK_FIELD_MASK  0x00000002
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_HD_FC_BKOFF_OK_FIELD_WIDTH 1
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_HD_FC_BKOFF_OK_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_IPG_HD_BKP_CNTL_HD_FC_ENA_FIELD;
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_HD_FC_ENA_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_HD_FC_ENA_FIELD_WIDTH 1
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_HD_FC_ENA_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_RESERVED0_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_RESERVED0_FIELD_MASK  0x80000000
+#define UNIMAC_RDP_COMMAND_CONFIG_RESERVED0_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_RUNT_FILTER_DIS_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_RUNT_FILTER_DIS_FIELD_MASK  0x40000000
+#define UNIMAC_RDP_COMMAND_CONFIG_RUNT_FILTER_DIS_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_RUNT_FILTER_DIS_FIELD_SHIFT 30
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_OOB_EFC_DISAB_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_OOB_EFC_DISAB_FIELD_MASK  0x20000000
+#define UNIMAC_RDP_COMMAND_CONFIG_OOB_EFC_DISAB_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_OOB_EFC_DISAB_FIELD_SHIFT 29
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_IGNORE_TX_PAUSE_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_IGNORE_TX_PAUSE_FIELD_MASK  0x10000000
+#define UNIMAC_RDP_COMMAND_CONFIG_IGNORE_TX_PAUSE_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_IGNORE_TX_PAUSE_FIELD_SHIFT 28
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_FD_TX_URUN_FIX_EN_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_FD_TX_URUN_FIX_EN_FIELD_MASK  0x08000000
+#define UNIMAC_RDP_COMMAND_CONFIG_FD_TX_URUN_FIX_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_FD_TX_URUN_FIX_EN_FIELD_SHIFT 27
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_RESERVED1_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_RESERVED1_FIELD_MASK  0x04000000
+#define UNIMAC_RDP_COMMAND_CONFIG_RESERVED1_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_RESERVED1_FIELD_SHIFT 26
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_LINE_LOOPBACK_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_LINE_LOOPBACK_FIELD_MASK  0x02000000
+#define UNIMAC_RDP_COMMAND_CONFIG_LINE_LOOPBACK_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_LINE_LOOPBACK_FIELD_SHIFT 25
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_NO_LGTH_CHECK_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_NO_LGTH_CHECK_FIELD_MASK  0x01000000
+#define UNIMAC_RDP_COMMAND_CONFIG_NO_LGTH_CHECK_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_NO_LGTH_CHECK_FIELD_SHIFT 24
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_CNTL_FRM_ENA_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_CNTL_FRM_ENA_FIELD_MASK  0x00800000
+#define UNIMAC_RDP_COMMAND_CONFIG_CNTL_FRM_ENA_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_CNTL_FRM_ENA_FIELD_SHIFT 23
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_ENA_EXT_CONFIG_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_ENA_EXT_CONFIG_FIELD_MASK  0x00400000
+#define UNIMAC_RDP_COMMAND_CONFIG_ENA_EXT_CONFIG_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_ENA_EXT_CONFIG_FIELD_SHIFT 22
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_EN_INTERNAL_TX_CRS_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_EN_INTERNAL_TX_CRS_FIELD_MASK  0x00200000
+#define UNIMAC_RDP_COMMAND_CONFIG_EN_INTERNAL_TX_CRS_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_EN_INTERNAL_TX_CRS_FIELD_SHIFT 21
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_BYPASS_OOB_EFC_SYNCHRONIZER_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_BYPASS_OOB_EFC_SYNCHRONIZER_FIELD_MASK  0x00100000
+#define UNIMAC_RDP_COMMAND_CONFIG_BYPASS_OOB_EFC_SYNCHRONIZER_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_BYPASS_OOB_EFC_SYNCHRONIZER_FIELD_SHIFT 20
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_OOB_EFC_MODE_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_OOB_EFC_MODE_FIELD_MASK  0x00080000
+#define UNIMAC_RDP_COMMAND_CONFIG_OOB_EFC_MODE_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_OOB_EFC_MODE_FIELD_SHIFT 19
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_SW_OVERRIDE_RX_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_SW_OVERRIDE_RX_FIELD_MASK  0x00040000
+#define UNIMAC_RDP_COMMAND_CONFIG_SW_OVERRIDE_RX_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_SW_OVERRIDE_RX_FIELD_SHIFT 18
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_SW_OVERRIDE_TX_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_SW_OVERRIDE_TX_FIELD_MASK  0x00020000
+#define UNIMAC_RDP_COMMAND_CONFIG_SW_OVERRIDE_TX_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_SW_OVERRIDE_TX_FIELD_SHIFT 17
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_MAC_LOOP_CON_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_MAC_LOOP_CON_FIELD_MASK  0x00010000
+#define UNIMAC_RDP_COMMAND_CONFIG_MAC_LOOP_CON_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_MAC_LOOP_CON_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_LOOP_ENA_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_LOOP_ENA_FIELD_MASK  0x00008000
+#define UNIMAC_RDP_COMMAND_CONFIG_LOOP_ENA_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_LOOP_ENA_FIELD_SHIFT 15
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_FCS_CORRUPT_URUN_EN_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_FCS_CORRUPT_URUN_EN_FIELD_MASK  0x00004000
+#define UNIMAC_RDP_COMMAND_CONFIG_FCS_CORRUPT_URUN_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_FCS_CORRUPT_URUN_EN_FIELD_SHIFT 14
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_SW_RESET_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_SW_RESET_FIELD_MASK  0x00002000
+#define UNIMAC_RDP_COMMAND_CONFIG_SW_RESET_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_SW_RESET_FIELD_SHIFT 13
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_OVERFLOW_EN_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_OVERFLOW_EN_FIELD_MASK  0x00001000
+#define UNIMAC_RDP_COMMAND_CONFIG_OVERFLOW_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_OVERFLOW_EN_FIELD_SHIFT 12
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_RX_LOW_LATENCY_EN_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_RX_LOW_LATENCY_EN_FIELD_MASK  0x00000800
+#define UNIMAC_RDP_COMMAND_CONFIG_RX_LOW_LATENCY_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_RX_LOW_LATENCY_EN_FIELD_SHIFT 11
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_HD_ENA_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_HD_ENA_FIELD_MASK  0x00000400
+#define UNIMAC_RDP_COMMAND_CONFIG_HD_ENA_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_HD_ENA_FIELD_SHIFT 10
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_TX_ADDR_INS_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_TX_ADDR_INS_FIELD_MASK  0x00000200
+#define UNIMAC_RDP_COMMAND_CONFIG_TX_ADDR_INS_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_TX_ADDR_INS_FIELD_SHIFT 9
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_PAUSE_IGNORE_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_PAUSE_IGNORE_FIELD_MASK  0x00000100
+#define UNIMAC_RDP_COMMAND_CONFIG_PAUSE_IGNORE_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_PAUSE_IGNORE_FIELD_SHIFT 8
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_PAUSE_FWD_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_PAUSE_FWD_FIELD_MASK  0x00000080
+#define UNIMAC_RDP_COMMAND_CONFIG_PAUSE_FWD_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_PAUSE_FWD_FIELD_SHIFT 7
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_CRC_FWD_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_CRC_FWD_FIELD_MASK  0x00000040
+#define UNIMAC_RDP_COMMAND_CONFIG_CRC_FWD_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_CRC_FWD_FIELD_SHIFT 6
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_PAD_EN_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_PAD_EN_FIELD_MASK  0x00000020
+#define UNIMAC_RDP_COMMAND_CONFIG_PAD_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_PAD_EN_FIELD_SHIFT 5
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_PROMIS_EN_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_PROMIS_EN_FIELD_MASK  0x00000010
+#define UNIMAC_RDP_COMMAND_CONFIG_PROMIS_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_PROMIS_EN_FIELD_SHIFT 4
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_ETH_SPEED_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_ETH_SPEED_FIELD_MASK  0x0000000c
+#define UNIMAC_RDP_COMMAND_CONFIG_ETH_SPEED_FIELD_WIDTH 2
+#define UNIMAC_RDP_COMMAND_CONFIG_ETH_SPEED_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_RX_ENA_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_RX_ENA_FIELD_MASK  0x00000002
+#define UNIMAC_RDP_COMMAND_CONFIG_RX_ENA_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_RX_ENA_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_COMMAND_CONFIG_TX_ENA_FIELD;
+#define UNIMAC_RDP_COMMAND_CONFIG_TX_ENA_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_COMMAND_CONFIG_TX_ENA_FIELD_WIDTH 1
+#define UNIMAC_RDP_COMMAND_CONFIG_TX_ENA_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MAC_0_MAC_ADDR0_FIELD;
+#define UNIMAC_RDP_MAC_0_MAC_ADDR0_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_MAC_0_MAC_ADDR0_FIELD_WIDTH 32
+#define UNIMAC_RDP_MAC_0_MAC_ADDR0_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MAC_1_RESERVED0_FIELD;
+#define UNIMAC_RDP_MAC_1_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_MAC_1_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_MAC_1_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_MAC_1_MAC_ADDR1_FIELD;
+#define UNIMAC_RDP_MAC_1_MAC_ADDR1_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_MAC_1_MAC_ADDR1_FIELD_WIDTH 16
+#define UNIMAC_RDP_MAC_1_MAC_ADDR1_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_FRM_LENGTH_RESERVED0_FIELD;
+#define UNIMAC_RDP_FRM_LENGTH_RESERVED0_FIELD_MASK  0xffffc000
+#define UNIMAC_RDP_FRM_LENGTH_RESERVED0_FIELD_WIDTH 18
+#define UNIMAC_RDP_FRM_LENGTH_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec UNIMAC_RDP_FRM_LENGTH_MAXFR_FIELD;
+#define UNIMAC_RDP_FRM_LENGTH_MAXFR_FIELD_MASK  0x00003fff
+#define UNIMAC_RDP_FRM_LENGTH_MAXFR_FIELD_WIDTH 14
+#define UNIMAC_RDP_FRM_LENGTH_MAXFR_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_PAUSE_QUANT_RESERVED0_FIELD;
+#define UNIMAC_RDP_PAUSE_QUANT_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_PAUSE_QUANT_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_PAUSE_QUANT_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_PAUSE_QUANT_PAUSE_QUANT_FIELD;
+#define UNIMAC_RDP_PAUSE_QUANT_PAUSE_QUANT_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_PAUSE_QUANT_PAUSE_QUANT_FIELD_WIDTH 16
+#define UNIMAC_RDP_PAUSE_QUANT_PAUSE_QUANT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TX_TS_SEQ_ID_RESERVED0_FIELD;
+#define UNIMAC_RDP_TX_TS_SEQ_ID_RESERVED0_FIELD_MASK  0xfffe0000
+#define UNIMAC_RDP_TX_TS_SEQ_ID_RESERVED0_FIELD_WIDTH 15
+#define UNIMAC_RDP_TX_TS_SEQ_ID_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec UNIMAC_RDP_TX_TS_SEQ_ID_TSTS_VALID_FIELD;
+#define UNIMAC_RDP_TX_TS_SEQ_ID_TSTS_VALID_FIELD_MASK  0x00010000
+#define UNIMAC_RDP_TX_TS_SEQ_ID_TSTS_VALID_FIELD_WIDTH 1
+#define UNIMAC_RDP_TX_TS_SEQ_ID_TSTS_VALID_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_TX_TS_SEQ_ID_TSTS_SEQ_ID_FIELD;
+#define UNIMAC_RDP_TX_TS_SEQ_ID_TSTS_SEQ_ID_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_TX_TS_SEQ_ID_TSTS_SEQ_ID_FIELD_WIDTH 16
+#define UNIMAC_RDP_TX_TS_SEQ_ID_TSTS_SEQ_ID_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_SFD_OFFSET_RESERVED0_FIELD;
+#define UNIMAC_RDP_SFD_OFFSET_RESERVED0_FIELD_MASK  0xfffffff0
+#define UNIMAC_RDP_SFD_OFFSET_RESERVED0_FIELD_WIDTH 28
+#define UNIMAC_RDP_SFD_OFFSET_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec UNIMAC_RDP_SFD_OFFSET_SFD_OFFSET_FIELD;
+#define UNIMAC_RDP_SFD_OFFSET_SFD_OFFSET_FIELD_MASK  0x0000000f
+#define UNIMAC_RDP_SFD_OFFSET_SFD_OFFSET_FIELD_WIDTH 4
+#define UNIMAC_RDP_SFD_OFFSET_SFD_OFFSET_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MAC_MODE_RESERVED0_FIELD;
+#define UNIMAC_RDP_MAC_MODE_RESERVED0_FIELD_MASK  0xffffffc0
+#define UNIMAC_RDP_MAC_MODE_RESERVED0_FIELD_WIDTH 26
+#define UNIMAC_RDP_MAC_MODE_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec UNIMAC_RDP_MAC_MODE_LINK_STATUS_FIELD;
+#define UNIMAC_RDP_MAC_MODE_LINK_STATUS_FIELD_MASK  0x00000020
+#define UNIMAC_RDP_MAC_MODE_LINK_STATUS_FIELD_WIDTH 1
+#define UNIMAC_RDP_MAC_MODE_LINK_STATUS_FIELD_SHIFT 5
+
+extern const ru_field_rec UNIMAC_RDP_MAC_MODE_MAC_TX_PAUSE_FIELD;
+#define UNIMAC_RDP_MAC_MODE_MAC_TX_PAUSE_FIELD_MASK  0x00000010
+#define UNIMAC_RDP_MAC_MODE_MAC_TX_PAUSE_FIELD_WIDTH 1
+#define UNIMAC_RDP_MAC_MODE_MAC_TX_PAUSE_FIELD_SHIFT 4
+
+extern const ru_field_rec UNIMAC_RDP_MAC_MODE_MAC_RX_PAUSE_FIELD;
+#define UNIMAC_RDP_MAC_MODE_MAC_RX_PAUSE_FIELD_MASK  0x00000008
+#define UNIMAC_RDP_MAC_MODE_MAC_RX_PAUSE_FIELD_WIDTH 1
+#define UNIMAC_RDP_MAC_MODE_MAC_RX_PAUSE_FIELD_SHIFT 3
+
+extern const ru_field_rec UNIMAC_RDP_MAC_MODE_MAC_DUPLEX_FIELD;
+#define UNIMAC_RDP_MAC_MODE_MAC_DUPLEX_FIELD_MASK  0x00000004
+#define UNIMAC_RDP_MAC_MODE_MAC_DUPLEX_FIELD_WIDTH 1
+#define UNIMAC_RDP_MAC_MODE_MAC_DUPLEX_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_MAC_MODE_MAC_SPEED_FIELD;
+#define UNIMAC_RDP_MAC_MODE_MAC_SPEED_FIELD_MASK  0x00000003
+#define UNIMAC_RDP_MAC_MODE_MAC_SPEED_FIELD_WIDTH 2
+#define UNIMAC_RDP_MAC_MODE_MAC_SPEED_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TAG_0_RESERVED0_FIELD;
+#define UNIMAC_RDP_TAG_0_RESERVED0_FIELD_MASK  0xfffe0000
+#define UNIMAC_RDP_TAG_0_RESERVED0_FIELD_WIDTH 15
+#define UNIMAC_RDP_TAG_0_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec UNIMAC_RDP_TAG_0_CONFIG_OUTER_TPID_ENABLE_FIELD;
+#define UNIMAC_RDP_TAG_0_CONFIG_OUTER_TPID_ENABLE_FIELD_MASK  0x00010000
+#define UNIMAC_RDP_TAG_0_CONFIG_OUTER_TPID_ENABLE_FIELD_WIDTH 1
+#define UNIMAC_RDP_TAG_0_CONFIG_OUTER_TPID_ENABLE_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_TAG_0_FRM_TAG_0_FIELD;
+#define UNIMAC_RDP_TAG_0_FRM_TAG_0_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_TAG_0_FRM_TAG_0_FIELD_WIDTH 16
+#define UNIMAC_RDP_TAG_0_FRM_TAG_0_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TAG_1_RESERVED0_FIELD;
+#define UNIMAC_RDP_TAG_1_RESERVED0_FIELD_MASK  0xfffe0000
+#define UNIMAC_RDP_TAG_1_RESERVED0_FIELD_WIDTH 15
+#define UNIMAC_RDP_TAG_1_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec UNIMAC_RDP_TAG_1_CONFIG_INNER_TPID_ENABLE_FIELD;
+#define UNIMAC_RDP_TAG_1_CONFIG_INNER_TPID_ENABLE_FIELD_MASK  0x00010000
+#define UNIMAC_RDP_TAG_1_CONFIG_INNER_TPID_ENABLE_FIELD_WIDTH 1
+#define UNIMAC_RDP_TAG_1_CONFIG_INNER_TPID_ENABLE_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_TAG_1_FRM_TAG_1_FIELD;
+#define UNIMAC_RDP_TAG_1_FRM_TAG_1_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_TAG_1_FRM_TAG_1_FIELD_WIDTH 16
+#define UNIMAC_RDP_TAG_1_FRM_TAG_1_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_RESERVED0_FIELD;
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_RESERVED0_FIELD_MASK  0xfffc0000
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_RESERVED0_FIELD_WIDTH 14
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_FIX_FIELD;
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_FIX_FIELD_MASK  0x00020000
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_FIX_FIELD_WIDTH 1
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_FIX_FIELD_SHIFT 17
+
+extern const ru_field_rec UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_CONTROL_FIELD;
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_CONTROL_FIELD_MASK  0x00010000
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_CONTROL_FIELD_WIDTH 1
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_CONTROL_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_VALUE_FIELD;
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_VALUE_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_VALUE_FIELD_WIDTH 16
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_SCALE_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TX_PREAMBLE_RESERVED0_FIELD;
+#define UNIMAC_RDP_TX_PREAMBLE_RESERVED0_FIELD_MASK  0xfffffff8
+#define UNIMAC_RDP_TX_PREAMBLE_RESERVED0_FIELD_WIDTH 29
+#define UNIMAC_RDP_TX_PREAMBLE_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec UNIMAC_RDP_TX_PREAMBLE_TX_PREAMBLE_FIELD;
+#define UNIMAC_RDP_TX_PREAMBLE_TX_PREAMBLE_FIELD_MASK  0x00000007
+#define UNIMAC_RDP_TX_PREAMBLE_TX_PREAMBLE_FIELD_WIDTH 3
+#define UNIMAC_RDP_TX_PREAMBLE_TX_PREAMBLE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TX_IPG_LENGTH_RESERVED0_FIELD;
+#define UNIMAC_RDP_TX_IPG_LENGTH_RESERVED0_FIELD_MASK  0xffff8000
+#define UNIMAC_RDP_TX_IPG_LENGTH_RESERVED0_FIELD_WIDTH 17
+#define UNIMAC_RDP_TX_IPG_LENGTH_RESERVED0_FIELD_SHIFT 15
+
+extern const ru_field_rec UNIMAC_RDP_TX_IPG_LENGTH_TX_MIN_PKT_SIZE_FIELD;
+#define UNIMAC_RDP_TX_IPG_LENGTH_TX_MIN_PKT_SIZE_FIELD_MASK  0x00007f00
+#define UNIMAC_RDP_TX_IPG_LENGTH_TX_MIN_PKT_SIZE_FIELD_WIDTH 7
+#define UNIMAC_RDP_TX_IPG_LENGTH_TX_MIN_PKT_SIZE_FIELD_SHIFT 8
+
+extern const ru_field_rec UNIMAC_RDP_TX_IPG_LENGTH_RESERVED1_FIELD;
+#define UNIMAC_RDP_TX_IPG_LENGTH_RESERVED1_FIELD_MASK  0x00000080
+#define UNIMAC_RDP_TX_IPG_LENGTH_RESERVED1_FIELD_WIDTH 1
+#define UNIMAC_RDP_TX_IPG_LENGTH_RESERVED1_FIELD_SHIFT 7
+
+extern const ru_field_rec UNIMAC_RDP_TX_IPG_LENGTH_TX_IPG_LENGTH_FIELD;
+#define UNIMAC_RDP_TX_IPG_LENGTH_TX_IPG_LENGTH_FIELD_MASK  0x0000007f
+#define UNIMAC_RDP_TX_IPG_LENGTH_TX_IPG_LENGTH_FIELD_WIDTH 7
+#define UNIMAC_RDP_TX_IPG_LENGTH_TX_IPG_LENGTH_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_PFC_XOFF_TIMER_RESERVED0_FIELD;
+#define UNIMAC_RDP_PFC_XOFF_TIMER_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_PFC_XOFF_TIMER_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_PFC_XOFF_TIMER_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_PFC_XOFF_TIMER_PFC_XOFF_TIMER_FIELD;
+#define UNIMAC_RDP_PFC_XOFF_TIMER_PFC_XOFF_TIMER_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_PFC_XOFF_TIMER_PFC_XOFF_TIMER_FIELD_WIDTH 16
+#define UNIMAC_RDP_PFC_XOFF_TIMER_PFC_XOFF_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_EEE_CTRL_RESERVED0_FIELD;
+#define UNIMAC_RDP_UMAC_EEE_CTRL_RESERVED0_FIELD_MASK  0xffffff00
+#define UNIMAC_RDP_UMAC_EEE_CTRL_RESERVED0_FIELD_WIDTH 24
+#define UNIMAC_RDP_UMAC_EEE_CTRL_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_EEE_CTRL_LP_IDLE_PREDICTION_MODE_FIELD;
+#define UNIMAC_RDP_UMAC_EEE_CTRL_LP_IDLE_PREDICTION_MODE_FIELD_MASK  0x00000080
+#define UNIMAC_RDP_UMAC_EEE_CTRL_LP_IDLE_PREDICTION_MODE_FIELD_WIDTH 1
+#define UNIMAC_RDP_UMAC_EEE_CTRL_LP_IDLE_PREDICTION_MODE_FIELD_SHIFT 7
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_EEE_CTRL_DIS_EEE_10M_FIELD;
+#define UNIMAC_RDP_UMAC_EEE_CTRL_DIS_EEE_10M_FIELD_MASK  0x00000040
+#define UNIMAC_RDP_UMAC_EEE_CTRL_DIS_EEE_10M_FIELD_WIDTH 1
+#define UNIMAC_RDP_UMAC_EEE_CTRL_DIS_EEE_10M_FIELD_SHIFT 6
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_EEE_CTRL_EEE_TXCLK_DIS_FIELD;
+#define UNIMAC_RDP_UMAC_EEE_CTRL_EEE_TXCLK_DIS_FIELD_MASK  0x00000020
+#define UNIMAC_RDP_UMAC_EEE_CTRL_EEE_TXCLK_DIS_FIELD_WIDTH 1
+#define UNIMAC_RDP_UMAC_EEE_CTRL_EEE_TXCLK_DIS_FIELD_SHIFT 5
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_EEE_CTRL_RX_FIFO_CHECK_FIELD;
+#define UNIMAC_RDP_UMAC_EEE_CTRL_RX_FIFO_CHECK_FIELD_MASK  0x00000010
+#define UNIMAC_RDP_UMAC_EEE_CTRL_RX_FIFO_CHECK_FIELD_WIDTH 1
+#define UNIMAC_RDP_UMAC_EEE_CTRL_RX_FIFO_CHECK_FIELD_SHIFT 4
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_EEE_CTRL_EEE_EN_FIELD;
+#define UNIMAC_RDP_UMAC_EEE_CTRL_EEE_EN_FIELD_MASK  0x00000008
+#define UNIMAC_RDP_UMAC_EEE_CTRL_EEE_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_UMAC_EEE_CTRL_EEE_EN_FIELD_SHIFT 3
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_EEE_CTRL_RESERVED1_FIELD;
+#define UNIMAC_RDP_UMAC_EEE_CTRL_RESERVED1_FIELD_MASK  0x00000007
+#define UNIMAC_RDP_UMAC_EEE_CTRL_RESERVED1_FIELD_WIDTH 3
+#define UNIMAC_RDP_UMAC_EEE_CTRL_RESERVED1_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MII_EEE_DELAY_ENTRY_TIMER_MII_EEE_LPI_TIMER_FIELD;
+#define UNIMAC_RDP_MII_EEE_DELAY_ENTRY_TIMER_MII_EEE_LPI_TIMER_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_MII_EEE_DELAY_ENTRY_TIMER_MII_EEE_LPI_TIMER_FIELD_WIDTH 32
+#define UNIMAC_RDP_MII_EEE_DELAY_ENTRY_TIMER_MII_EEE_LPI_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GMII_EEE_DELAY_ENTRY_TIMER_GMII_EEE_LPI_TIMER_FIELD;
+#define UNIMAC_RDP_GMII_EEE_DELAY_ENTRY_TIMER_GMII_EEE_LPI_TIMER_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GMII_EEE_DELAY_ENTRY_TIMER_GMII_EEE_LPI_TIMER_FIELD_WIDTH 32
+#define UNIMAC_RDP_GMII_EEE_DELAY_ENTRY_TIMER_GMII_EEE_LPI_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_EEE_REF_COUNT_RESERVED0_FIELD;
+#define UNIMAC_RDP_UMAC_EEE_REF_COUNT_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_UMAC_EEE_REF_COUNT_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_UMAC_EEE_REF_COUNT_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_EEE_REF_COUNT_EEE_REF_COUNT_FIELD;
+#define UNIMAC_RDP_UMAC_EEE_REF_COUNT_EEE_REF_COUNT_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_UMAC_EEE_REF_COUNT_EEE_REF_COUNT_FIELD_WIDTH 16
+#define UNIMAC_RDP_UMAC_EEE_REF_COUNT_EEE_REF_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD;
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_MASK  0xfffff800
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_WIDTH 21
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_AUTO_ADJUST_FIELD;
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_AUTO_ADJUST_FIELD_MASK  0x00000400
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_AUTO_ADJUST_FIELD_WIDTH 1
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_AUTO_ADJUST_FIELD_SHIFT 10
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_EN_1588_FIELD;
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_EN_1588_FIELD_MASK  0x00000200
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_EN_1588_FIELD_WIDTH 1
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_EN_1588_FIELD_SHIFT 9
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_ADJUST_FIELD;
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_ADJUST_FIELD_MASK  0x000001ff
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_ADJUST_FIELD_WIDTH 9
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_ADJUST_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_RX_PKT_DROP_STATUS_RESERVED0_FIELD;
+#define UNIMAC_RDP_UMAC_RX_PKT_DROP_STATUS_RESERVED0_FIELD_MASK  0xfffffffe
+#define UNIMAC_RDP_UMAC_RX_PKT_DROP_STATUS_RESERVED0_FIELD_WIDTH 31
+#define UNIMAC_RDP_UMAC_RX_PKT_DROP_STATUS_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_RX_PKT_DROP_STATUS_RX_IPG_INVAL_FIELD;
+#define UNIMAC_RDP_UMAC_RX_PKT_DROP_STATUS_RX_IPG_INVAL_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_UMAC_RX_PKT_DROP_STATUS_RX_IPG_INVAL_FIELD_WIDTH 1
+#define UNIMAC_RDP_UMAC_RX_PKT_DROP_STATUS_RX_IPG_INVAL_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_SYMMETRIC_IDLE_THRESHOLD_RESERVED0_FIELD;
+#define UNIMAC_RDP_UMAC_SYMMETRIC_IDLE_THRESHOLD_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_UMAC_SYMMETRIC_IDLE_THRESHOLD_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_UMAC_SYMMETRIC_IDLE_THRESHOLD_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_SYMMETRIC_IDLE_THRESHOLD_THRESHOLD_VALUE_FIELD;
+#define UNIMAC_RDP_UMAC_SYMMETRIC_IDLE_THRESHOLD_THRESHOLD_VALUE_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_UMAC_SYMMETRIC_IDLE_THRESHOLD_THRESHOLD_VALUE_FIELD_WIDTH 16
+#define UNIMAC_RDP_UMAC_SYMMETRIC_IDLE_THRESHOLD_THRESHOLD_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MII_EEE_WAKE_TIMER_RESERVED0_FIELD;
+#define UNIMAC_RDP_MII_EEE_WAKE_TIMER_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_MII_EEE_WAKE_TIMER_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_MII_EEE_WAKE_TIMER_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_MII_EEE_WAKE_TIMER_MII_EEE_WAKE_TIMER_FIELD;
+#define UNIMAC_RDP_MII_EEE_WAKE_TIMER_MII_EEE_WAKE_TIMER_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_MII_EEE_WAKE_TIMER_MII_EEE_WAKE_TIMER_FIELD_WIDTH 16
+#define UNIMAC_RDP_MII_EEE_WAKE_TIMER_MII_EEE_WAKE_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GMII_EEE_WAKE_TIMER_RESERVED0_FIELD;
+#define UNIMAC_RDP_GMII_EEE_WAKE_TIMER_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_GMII_EEE_WAKE_TIMER_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_GMII_EEE_WAKE_TIMER_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_GMII_EEE_WAKE_TIMER_GMII_EEE_WAKE_TIMER_FIELD;
+#define UNIMAC_RDP_GMII_EEE_WAKE_TIMER_GMII_EEE_WAKE_TIMER_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_GMII_EEE_WAKE_TIMER_GMII_EEE_WAKE_TIMER_FIELD_WIDTH 16
+#define UNIMAC_RDP_GMII_EEE_WAKE_TIMER_GMII_EEE_WAKE_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_REV_ID_RESERVED0_FIELD;
+#define UNIMAC_RDP_UMAC_REV_ID_RESERVED0_FIELD_MASK  0xff000000
+#define UNIMAC_RDP_UMAC_REV_ID_RESERVED0_FIELD_WIDTH 8
+#define UNIMAC_RDP_UMAC_REV_ID_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_REV_ID_REVISION_ID_MAJOR_FIELD;
+#define UNIMAC_RDP_UMAC_REV_ID_REVISION_ID_MAJOR_FIELD_MASK  0x00ff0000
+#define UNIMAC_RDP_UMAC_REV_ID_REVISION_ID_MAJOR_FIELD_WIDTH 8
+#define UNIMAC_RDP_UMAC_REV_ID_REVISION_ID_MAJOR_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_REV_ID_REVISION_ID_MINOR_FIELD;
+#define UNIMAC_RDP_UMAC_REV_ID_REVISION_ID_MINOR_FIELD_MASK  0x0000ff00
+#define UNIMAC_RDP_UMAC_REV_ID_REVISION_ID_MINOR_FIELD_WIDTH 8
+#define UNIMAC_RDP_UMAC_REV_ID_REVISION_ID_MINOR_FIELD_SHIFT 8
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_REV_ID_PATCH_FIELD;
+#define UNIMAC_RDP_UMAC_REV_ID_PATCH_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_UMAC_REV_ID_PATCH_FIELD_WIDTH 8
+#define UNIMAC_RDP_UMAC_REV_ID_PATCH_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_TYPE_RESERVED0_FIELD;
+#define UNIMAC_RDP_MAC_PFC_TYPE_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_MAC_PFC_TYPE_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_MAC_PFC_TYPE_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_TYPE_PFC_ETH_TYPE_FIELD;
+#define UNIMAC_RDP_MAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_MAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_WIDTH 16
+#define UNIMAC_RDP_MAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_OPCODE_RESERVED0_FIELD;
+#define UNIMAC_RDP_MAC_PFC_OPCODE_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_MAC_PFC_OPCODE_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_MAC_PFC_OPCODE_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_OPCODE_PFC_OPCODE_FIELD;
+#define UNIMAC_RDP_MAC_PFC_OPCODE_PFC_OPCODE_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_MAC_PFC_OPCODE_PFC_OPCODE_FIELD_WIDTH 16
+#define UNIMAC_RDP_MAC_PFC_OPCODE_PFC_OPCODE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_DA_0_PFC_MACDA_0_FIELD;
+#define UNIMAC_RDP_MAC_PFC_DA_0_PFC_MACDA_0_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_MAC_PFC_DA_0_PFC_MACDA_0_FIELD_WIDTH 32
+#define UNIMAC_RDP_MAC_PFC_DA_0_PFC_MACDA_0_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_DA_1_RESERVED0_FIELD;
+#define UNIMAC_RDP_MAC_PFC_DA_1_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_MAC_PFC_DA_1_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_MAC_PFC_DA_1_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_DA_1_PFC_MACDA_1_FIELD;
+#define UNIMAC_RDP_MAC_PFC_DA_1_PFC_MACDA_1_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_MAC_PFC_DA_1_PFC_MACDA_1_FIELD_WIDTH 16
+#define UNIMAC_RDP_MAC_PFC_DA_1_PFC_MACDA_1_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MACSEC_PROG_TX_CRC_MACSEC_PROG_TX_CRC_FIELD;
+#define UNIMAC_RDP_MACSEC_PROG_TX_CRC_MACSEC_PROG_TX_CRC_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_MACSEC_PROG_TX_CRC_MACSEC_PROG_TX_CRC_FIELD_WIDTH 32
+#define UNIMAC_RDP_MACSEC_PROG_TX_CRC_MACSEC_PROG_TX_CRC_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MACSEC_CNTRL_RESERVED0_FIELD;
+#define UNIMAC_RDP_MACSEC_CNTRL_RESERVED0_FIELD_MASK  0xfffffff0
+#define UNIMAC_RDP_MACSEC_CNTRL_RESERVED0_FIELD_WIDTH 28
+#define UNIMAC_RDP_MACSEC_CNTRL_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec UNIMAC_RDP_MACSEC_CNTRL_DIS_PAUSE_DATA_VAR_IPG_FIELD;
+#define UNIMAC_RDP_MACSEC_CNTRL_DIS_PAUSE_DATA_VAR_IPG_FIELD_MASK  0x00000008
+#define UNIMAC_RDP_MACSEC_CNTRL_DIS_PAUSE_DATA_VAR_IPG_FIELD_WIDTH 1
+#define UNIMAC_RDP_MACSEC_CNTRL_DIS_PAUSE_DATA_VAR_IPG_FIELD_SHIFT 3
+
+extern const ru_field_rec UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_PROGRAM_FIELD;
+#define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_PROGRAM_FIELD_MASK  0x00000004
+#define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_PROGRAM_FIELD_WIDTH 1
+#define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_PROGRAM_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_CORUPT_EN_FIELD;
+#define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_CORUPT_EN_FIELD_MASK  0x00000002
+#define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_CORUPT_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_CORUPT_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_MACSEC_CNTRL_TX_LAUNCH_EN_FIELD;
+#define UNIMAC_RDP_MACSEC_CNTRL_TX_LAUNCH_EN_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_MACSEC_CNTRL_TX_LAUNCH_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_MACSEC_CNTRL_TX_LAUNCH_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TS_STATUS_RESERVED0_FIELD;
+#define UNIMAC_RDP_TS_STATUS_RESERVED0_FIELD_MASK  0xffffffe0
+#define UNIMAC_RDP_TS_STATUS_RESERVED0_FIELD_WIDTH 27
+#define UNIMAC_RDP_TS_STATUS_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec UNIMAC_RDP_TS_STATUS_WORD_AVAIL_FIELD;
+#define UNIMAC_RDP_TS_STATUS_WORD_AVAIL_FIELD_MASK  0x0000001c
+#define UNIMAC_RDP_TS_STATUS_WORD_AVAIL_FIELD_WIDTH 3
+#define UNIMAC_RDP_TS_STATUS_WORD_AVAIL_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_TS_STATUS_TX_TS_FIFO_EMPTY_FIELD;
+#define UNIMAC_RDP_TS_STATUS_TX_TS_FIFO_EMPTY_FIELD_MASK  0x00000002
+#define UNIMAC_RDP_TS_STATUS_TX_TS_FIFO_EMPTY_FIELD_WIDTH 1
+#define UNIMAC_RDP_TS_STATUS_TX_TS_FIFO_EMPTY_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_TS_STATUS_TX_TS_FIFO_FULL_FIELD;
+#define UNIMAC_RDP_TS_STATUS_TX_TS_FIFO_FULL_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_TS_STATUS_TX_TS_FIFO_FULL_FIELD_WIDTH 1
+#define UNIMAC_RDP_TS_STATUS_TX_TS_FIFO_FULL_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TX_TS_DATA_TX_TS_DATA_FIELD;
+#define UNIMAC_RDP_TX_TS_DATA_TX_TS_DATA_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TX_TS_DATA_TX_TS_DATA_FIELD_WIDTH 32
+#define UNIMAC_RDP_TX_TS_DATA_TX_TS_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_PAUSE_REFRESH_CTRL_RESERVED0_FIELD;
+#define UNIMAC_RDP_PAUSE_REFRESH_CTRL_RESERVED0_FIELD_MASK  0xfffc0000
+#define UNIMAC_RDP_PAUSE_REFRESH_CTRL_RESERVED0_FIELD_WIDTH 14
+#define UNIMAC_RDP_PAUSE_REFRESH_CTRL_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec UNIMAC_RDP_PAUSE_REFRESH_CTRL_ENABLE_FIELD;
+#define UNIMAC_RDP_PAUSE_REFRESH_CTRL_ENABLE_FIELD_MASK  0x00020000
+#define UNIMAC_RDP_PAUSE_REFRESH_CTRL_ENABLE_FIELD_WIDTH 1
+#define UNIMAC_RDP_PAUSE_REFRESH_CTRL_ENABLE_FIELD_SHIFT 17
+
+extern const ru_field_rec UNIMAC_RDP_PAUSE_REFRESH_CTRL_REFRESH_TIMER_FIELD;
+#define UNIMAC_RDP_PAUSE_REFRESH_CTRL_REFRESH_TIMER_FIELD_MASK  0x0001ffff
+#define UNIMAC_RDP_PAUSE_REFRESH_CTRL_REFRESH_TIMER_FIELD_WIDTH 17
+#define UNIMAC_RDP_PAUSE_REFRESH_CTRL_REFRESH_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_FLUSH_CONTROL_RESERVED0_FIELD;
+#define UNIMAC_RDP_FLUSH_CONTROL_RESERVED0_FIELD_MASK  0xfffffffe
+#define UNIMAC_RDP_FLUSH_CONTROL_RESERVED0_FIELD_WIDTH 31
+#define UNIMAC_RDP_FLUSH_CONTROL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_FLUSH_CONTROL_FLUSH_FIELD;
+#define UNIMAC_RDP_FLUSH_CONTROL_FLUSH_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_FLUSH_CONTROL_FLUSH_FIELD_WIDTH 1
+#define UNIMAC_RDP_FLUSH_CONTROL_FLUSH_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_RXFIFO_STAT_RESERVED0_FIELD;
+#define UNIMAC_RDP_RXFIFO_STAT_RESERVED0_FIELD_MASK  0xfffffffc
+#define UNIMAC_RDP_RXFIFO_STAT_RESERVED0_FIELD_WIDTH 30
+#define UNIMAC_RDP_RXFIFO_STAT_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_RXFIFO_STAT_RXFIFO_OVERRUN_FIELD;
+#define UNIMAC_RDP_RXFIFO_STAT_RXFIFO_OVERRUN_FIELD_MASK  0x00000002
+#define UNIMAC_RDP_RXFIFO_STAT_RXFIFO_OVERRUN_FIELD_WIDTH 1
+#define UNIMAC_RDP_RXFIFO_STAT_RXFIFO_OVERRUN_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_RXFIFO_STAT_RXFIFO_UNDERRUN_FIELD;
+#define UNIMAC_RDP_RXFIFO_STAT_RXFIFO_UNDERRUN_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_RXFIFO_STAT_RXFIFO_UNDERRUN_FIELD_WIDTH 1
+#define UNIMAC_RDP_RXFIFO_STAT_RXFIFO_UNDERRUN_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TXFIFO_STAT_RESERVED0_FIELD;
+#define UNIMAC_RDP_TXFIFO_STAT_RESERVED0_FIELD_MASK  0xfffffffc
+#define UNIMAC_RDP_TXFIFO_STAT_RESERVED0_FIELD_WIDTH 30
+#define UNIMAC_RDP_TXFIFO_STAT_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_TXFIFO_STAT_TXFIFO_OVERRUN_FIELD;
+#define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_OVERRUN_FIELD_MASK  0x00000002
+#define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_OVERRUN_FIELD_WIDTH 1
+#define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_OVERRUN_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_TXFIFO_STAT_TXFIFO_UNDERRUN_FIELD;
+#define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_UNDERRUN_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_UNDERRUN_FIELD_WIDTH 1
+#define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_UNDERRUN_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_CTRL_RESERVED0_FIELD;
+#define UNIMAC_RDP_MAC_PFC_CTRL_RESERVED0_FIELD_MASK  0xffffffc0
+#define UNIMAC_RDP_MAC_PFC_CTRL_RESERVED0_FIELD_WIDTH 26
+#define UNIMAC_RDP_MAC_PFC_CTRL_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_CTRL_PFC_STATS_EN_FIELD;
+#define UNIMAC_RDP_MAC_PFC_CTRL_PFC_STATS_EN_FIELD_MASK  0x00000020
+#define UNIMAC_RDP_MAC_PFC_CTRL_PFC_STATS_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_MAC_PFC_CTRL_PFC_STATS_EN_FIELD_SHIFT 5
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_CTRL_RX_PASS_PFC_FRM_FIELD;
+#define UNIMAC_RDP_MAC_PFC_CTRL_RX_PASS_PFC_FRM_FIELD_MASK  0x00000010
+#define UNIMAC_RDP_MAC_PFC_CTRL_RX_PASS_PFC_FRM_FIELD_WIDTH 1
+#define UNIMAC_RDP_MAC_PFC_CTRL_RX_PASS_PFC_FRM_FIELD_SHIFT 4
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_CTRL_RESERVED1_FIELD;
+#define UNIMAC_RDP_MAC_PFC_CTRL_RESERVED1_FIELD_MASK  0x00000008
+#define UNIMAC_RDP_MAC_PFC_CTRL_RESERVED1_FIELD_WIDTH 1
+#define UNIMAC_RDP_MAC_PFC_CTRL_RESERVED1_FIELD_SHIFT 3
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_CTRL_FORCE_PFC_XON_FIELD;
+#define UNIMAC_RDP_MAC_PFC_CTRL_FORCE_PFC_XON_FIELD_MASK  0x00000004
+#define UNIMAC_RDP_MAC_PFC_CTRL_FORCE_PFC_XON_FIELD_WIDTH 1
+#define UNIMAC_RDP_MAC_PFC_CTRL_FORCE_PFC_XON_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_CTRL_PFC_RX_ENBL_FIELD;
+#define UNIMAC_RDP_MAC_PFC_CTRL_PFC_RX_ENBL_FIELD_MASK  0x00000002
+#define UNIMAC_RDP_MAC_PFC_CTRL_PFC_RX_ENBL_FIELD_WIDTH 1
+#define UNIMAC_RDP_MAC_PFC_CTRL_PFC_RX_ENBL_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_CTRL_PFC_TX_ENBL_FIELD;
+#define UNIMAC_RDP_MAC_PFC_CTRL_PFC_TX_ENBL_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_MAC_PFC_CTRL_PFC_TX_ENBL_FIELD_WIDTH 1
+#define UNIMAC_RDP_MAC_PFC_CTRL_PFC_TX_ENBL_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_TIMER_FIELD;
+#define UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_TIMER_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_TIMER_FIELD_WIDTH 16
+#define UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_TIMER_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_RESERVED0_FIELD;
+#define UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_RESERVED0_FIELD_MASK  0x0000fffe
+#define UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_RESERVED0_FIELD_WIDTH 15
+#define UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_EN_FIELD;
+#define UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_EN_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR64_COUNT_FIELD;
+#define UNIMAC_RDP_GR64_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GR64_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GR64_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR64_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GR64_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GR64_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GR64_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR127_COUNT_FIELD;
+#define UNIMAC_RDP_GR127_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GR127_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GR127_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR127_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GR127_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GR127_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GR127_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR255_COUNT_FIELD;
+#define UNIMAC_RDP_GR255_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GR255_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GR255_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR255_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GR255_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GR255_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GR255_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR511_COUNT_FIELD;
+#define UNIMAC_RDP_GR511_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GR511_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GR511_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR511_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GR511_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GR511_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GR511_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR1023_COUNT_FIELD;
+#define UNIMAC_RDP_GR1023_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GR1023_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GR1023_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR1023_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GR1023_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GR1023_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GR1023_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR1518_COUNT_FIELD;
+#define UNIMAC_RDP_GR1518_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GR1518_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GR1518_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR1518_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GR1518_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GR1518_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GR1518_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRMGV_COUNT_FIELD;
+#define UNIMAC_RDP_GRMGV_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRMGV_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRMGV_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRMGV_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRMGV_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRMGV_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRMGV_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR2047_COUNT_FIELD;
+#define UNIMAC_RDP_GR2047_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GR2047_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GR2047_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR2047_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GR2047_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GR2047_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GR2047_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR4095_COUNT_FIELD;
+#define UNIMAC_RDP_GR4095_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GR4095_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GR4095_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR4095_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GR4095_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GR4095_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GR4095_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR9216_COUNT_FIELD;
+#define UNIMAC_RDP_GR9216_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GR9216_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GR9216_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GR9216_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GR9216_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GR9216_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GR9216_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRPKT_COUNT_FIELD;
+#define UNIMAC_RDP_GRPKT_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRPKT_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRPKT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRPKT_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRPKT_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRPKT_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRPKT_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRBYT_COUNT_FIELD;
+#define UNIMAC_RDP_GRBYT_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRBYT_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRBYT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRBYT_UPPER_COUNT_U16_FIELD;
+#define UNIMAC_RDP_GRBYT_UPPER_COUNT_U16_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_GRBYT_UPPER_COUNT_U16_FIELD_WIDTH 16
+#define UNIMAC_RDP_GRBYT_UPPER_COUNT_U16_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRMCA_COUNT_FIELD;
+#define UNIMAC_RDP_GRMCA_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRMCA_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRMCA_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRMCA_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRMCA_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRMCA_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRMCA_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRBCA_COUNT_FIELD;
+#define UNIMAC_RDP_GRBCA_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRBCA_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRBCA_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRBCA_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRBCA_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRBCA_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRBCA_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRFCS_COUNT_FIELD;
+#define UNIMAC_RDP_GRFCS_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRFCS_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRFCS_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRFCS_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRFCS_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRFCS_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRFCS_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRXCF_COUNT_FIELD;
+#define UNIMAC_RDP_GRXCF_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRXCF_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRXCF_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRXCF_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRXCF_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRXCF_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRXCF_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRXPF_COUNT_FIELD;
+#define UNIMAC_RDP_GRXPF_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRXPF_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRXPF_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRXPF_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRXPF_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRXPF_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRXPF_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRXUO_COUNT_FIELD;
+#define UNIMAC_RDP_GRXUO_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRXUO_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRXUO_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRXUO_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRXUO_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRXUO_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRXUO_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRALN_COUNT_FIELD;
+#define UNIMAC_RDP_GRALN_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRALN_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRALN_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRALN_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRALN_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRALN_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRALN_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRFLR_COUNT_FIELD;
+#define UNIMAC_RDP_GRFLR_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRFLR_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRFLR_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRFLR_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRFLR_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRFLR_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRFLR_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRCDE_COUNT_FIELD;
+#define UNIMAC_RDP_GRCDE_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRCDE_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRCDE_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRCDE_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRCDE_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRCDE_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRCDE_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRFCR_COUNT_FIELD;
+#define UNIMAC_RDP_GRFCR_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRFCR_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRFCR_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRFCR_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRFCR_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRFCR_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRFCR_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GROVR_COUNT_FIELD;
+#define UNIMAC_RDP_GROVR_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GROVR_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GROVR_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GROVR_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GROVR_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GROVR_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GROVR_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRJBR_COUNT_FIELD;
+#define UNIMAC_RDP_GRJBR_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRJBR_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRJBR_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRJBR_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRJBR_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRJBR_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRJBR_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRMTUE_COUNT_FIELD;
+#define UNIMAC_RDP_GRMTUE_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRMTUE_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRMTUE_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRMTUE_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRMTUE_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRMTUE_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRMTUE_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRPOK_COUNT_FIELD;
+#define UNIMAC_RDP_GRPOK_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRPOK_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRPOK_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRPOK_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRPOK_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRPOK_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRPOK_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRUC_COUNT_FIELD;
+#define UNIMAC_RDP_GRUC_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRUC_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRUC_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRUC_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRUC_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRUC_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRUC_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRPPP_COUNT_FIELD;
+#define UNIMAC_RDP_GRPPP_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRPPP_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRPPP_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRPPP_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRPPP_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRPPP_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRPPP_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRCRC_COUNT_FIELD;
+#define UNIMAC_RDP_GRCRC_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GRCRC_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GRCRC_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GRCRC_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GRCRC_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GRCRC_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GRCRC_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR64_COUNT_FIELD;
+#define UNIMAC_RDP_TR64_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TR64_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_TR64_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR64_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_TR64_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_TR64_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_TR64_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR127_COUNT_FIELD;
+#define UNIMAC_RDP_TR127_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TR127_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_TR127_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR127_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_TR127_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_TR127_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_TR127_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR255_COUNT_FIELD;
+#define UNIMAC_RDP_TR255_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TR255_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_TR255_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR255_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_TR255_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_TR255_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_TR255_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR511_COUNT_FIELD;
+#define UNIMAC_RDP_TR511_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TR511_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_TR511_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR511_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_TR511_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_TR511_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_TR511_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR1023_COUNT_FIELD;
+#define UNIMAC_RDP_TR1023_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TR1023_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_TR1023_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR1023_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_TR1023_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_TR1023_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_TR1023_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR1518_COUNT_FIELD;
+#define UNIMAC_RDP_TR1518_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TR1518_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_TR1518_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR1518_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_TR1518_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_TR1518_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_TR1518_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TRMGV_COUNT_FIELD;
+#define UNIMAC_RDP_TRMGV_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TRMGV_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_TRMGV_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TRMGV_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_TRMGV_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_TRMGV_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_TRMGV_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR2047_COUNT_FIELD;
+#define UNIMAC_RDP_TR2047_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TR2047_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_TR2047_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR2047_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_TR2047_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_TR2047_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_TR2047_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR4095_COUNT_FIELD;
+#define UNIMAC_RDP_TR4095_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TR4095_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_TR4095_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR4095_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_TR4095_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_TR4095_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_TR4095_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR9216_COUNT_FIELD;
+#define UNIMAC_RDP_TR9216_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TR9216_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_TR9216_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TR9216_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_TR9216_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_TR9216_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_TR9216_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTPKT_COUNT_FIELD;
+#define UNIMAC_RDP_GTPKT_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTPKT_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTPKT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTPKT_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTPKT_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTPKT_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTPKT_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTMCA_COUNT_FIELD;
+#define UNIMAC_RDP_GTMCA_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTMCA_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTMCA_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTMCA_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTMCA_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTMCA_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTMCA_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTBCA_COUNT_FIELD;
+#define UNIMAC_RDP_GTBCA_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTBCA_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTBCA_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTBCA_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTBCA_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTBCA_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTBCA_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTXPF_COUNT_FIELD;
+#define UNIMAC_RDP_GTXPF_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTXPF_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTXPF_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTXPF_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTXPF_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTXPF_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTXPF_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTXCF_COUNT_FIELD;
+#define UNIMAC_RDP_GTXCF_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTXCF_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTXCF_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTXCF_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTXCF_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTXCF_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTXCF_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTFCS_COUNT_FIELD;
+#define UNIMAC_RDP_GTFCS_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTFCS_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTFCS_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTFCS_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTFCS_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTFCS_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTFCS_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTOVR_COUNT_FIELD;
+#define UNIMAC_RDP_GTOVR_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTOVR_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTOVR_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTOVR_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTOVR_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTOVR_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTOVR_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTDRF_COUNT_FIELD;
+#define UNIMAC_RDP_GTDRF_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTDRF_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTDRF_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTDRF_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTDRF_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTDRF_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTDRF_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTEDF_COUNT_FIELD;
+#define UNIMAC_RDP_GTEDF_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTEDF_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTEDF_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTEDF_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTEDF_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTEDF_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTEDF_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTSCL_COUNT_FIELD;
+#define UNIMAC_RDP_GTSCL_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTSCL_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTSCL_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTSCL_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTSCL_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTSCL_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTSCL_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTMCL_COUNT_FIELD;
+#define UNIMAC_RDP_GTMCL_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTMCL_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTMCL_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTMCL_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTMCL_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTMCL_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTMCL_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTLCL_COUNT_FIELD;
+#define UNIMAC_RDP_GTLCL_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTLCL_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTLCL_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTLCL_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTLCL_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTLCL_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTLCL_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTXCL_COUNT_FIELD;
+#define UNIMAC_RDP_GTXCL_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTXCL_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTXCL_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTXCL_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTXCL_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTXCL_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTXCL_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTFRG_COUNT_FIELD;
+#define UNIMAC_RDP_GTFRG_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTFRG_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTFRG_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTFRG_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTFRG_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTFRG_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTFRG_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTNCL_COUNT_FIELD;
+#define UNIMAC_RDP_GTNCL_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTNCL_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTNCL_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTNCL_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTNCL_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTNCL_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTNCL_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTJBR_COUNT_FIELD;
+#define UNIMAC_RDP_GTJBR_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTJBR_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTJBR_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTJBR_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTJBR_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTJBR_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTJBR_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTBYT_COUNT_FIELD;
+#define UNIMAC_RDP_GTBYT_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTBYT_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTBYT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTBYT_UPPER_COUNT_U16_FIELD;
+#define UNIMAC_RDP_GTBYT_UPPER_COUNT_U16_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_GTBYT_UPPER_COUNT_U16_FIELD_WIDTH 16
+#define UNIMAC_RDP_GTBYT_UPPER_COUNT_U16_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTPOK_COUNT_FIELD;
+#define UNIMAC_RDP_GTPOK_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTPOK_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTPOK_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTPOK_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTPOK_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTPOK_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTPOK_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTUC_COUNT_FIELD;
+#define UNIMAC_RDP_GTUC_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_GTUC_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_GTUC_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GTUC_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_GTUC_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GTUC_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_GTUC_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_RRPKT_COUNT_FIELD;
+#define UNIMAC_RDP_RRPKT_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_RRPKT_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_RRPKT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_RRPKT_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_RRPKT_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_RRPKT_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_RRPKT_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_RRUND_COUNT_FIELD;
+#define UNIMAC_RDP_RRUND_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_RRUND_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_RRUND_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_RRUND_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_RRUND_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_RRUND_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_RRUND_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_RRFRG_COUNT_FIELD;
+#define UNIMAC_RDP_RRFRG_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_RRFRG_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_RRFRG_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_RRFRG_UPPER_COUNT_U8_FIELD;
+#define UNIMAC_RDP_RRFRG_UPPER_COUNT_U8_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_RRFRG_UPPER_COUNT_U8_FIELD_WIDTH 8
+#define UNIMAC_RDP_RRFRG_UPPER_COUNT_U8_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_RRBYT_COUNT_FIELD;
+#define UNIMAC_RDP_RRBYT_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_RRBYT_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_RRBYT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_RRBYT_UPPER_COUNT_U16_FIELD;
+#define UNIMAC_RDP_RRBYT_UPPER_COUNT_U16_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_RRBYT_UPPER_COUNT_U16_FIELD_WIDTH 16
+#define UNIMAC_RDP_RRBYT_UPPER_COUNT_U16_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MIB_CNTRL_RESERVED0_FIELD;
+#define UNIMAC_RDP_MIB_CNTRL_RESERVED0_FIELD_MASK  0xfffffff8
+#define UNIMAC_RDP_MIB_CNTRL_RESERVED0_FIELD_WIDTH 29
+#define UNIMAC_RDP_MIB_CNTRL_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec UNIMAC_RDP_MIB_CNTRL_TX_CNT_RST_FIELD;
+#define UNIMAC_RDP_MIB_CNTRL_TX_CNT_RST_FIELD_MASK  0x00000004
+#define UNIMAC_RDP_MIB_CNTRL_TX_CNT_RST_FIELD_WIDTH 1
+#define UNIMAC_RDP_MIB_CNTRL_TX_CNT_RST_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_MIB_CNTRL_RUNT_CNT_RST_FIELD;
+#define UNIMAC_RDP_MIB_CNTRL_RUNT_CNT_RST_FIELD_MASK  0x00000002
+#define UNIMAC_RDP_MIB_CNTRL_RUNT_CNT_RST_FIELD_WIDTH 1
+#define UNIMAC_RDP_MIB_CNTRL_RUNT_CNT_RST_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_MIB_CNTRL_RX_CNT_RST_FIELD;
+#define UNIMAC_RDP_MIB_CNTRL_RX_CNT_RST_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_MIB_CNTRL_RX_CNT_RST_FIELD_WIDTH 1
+#define UNIMAC_RDP_MIB_CNTRL_RX_CNT_RST_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MIB_READ_DATA_DATA32_FIELD;
+#define UNIMAC_RDP_MIB_READ_DATA_DATA32_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_MIB_READ_DATA_DATA32_FIELD_WIDTH 32
+#define UNIMAC_RDP_MIB_READ_DATA_DATA32_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MIB_WRITE_DATA_DATA32_FIELD;
+#define UNIMAC_RDP_MIB_WRITE_DATA_DATA32_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_MIB_WRITE_DATA_DATA32_FIELD_WIDTH 32
+#define UNIMAC_RDP_MIB_WRITE_DATA_DATA32_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_PSW_MS_RESERVED0_FIELD;
+#define UNIMAC_RDP_PSW_MS_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_PSW_MS_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_PSW_MS_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_PSW_MS_PSW_47_32_FIELD;
+#define UNIMAC_RDP_PSW_MS_PSW_47_32_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_PSW_MS_PSW_47_32_FIELD_WIDTH 16
+#define UNIMAC_RDP_PSW_MS_PSW_47_32_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_PSW_LS_PSW_31_0_FIELD;
+#define UNIMAC_RDP_PSW_LS_PSW_31_0_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_PSW_LS_PSW_31_0_FIELD_WIDTH 32
+#define UNIMAC_RDP_PSW_LS_PSW_31_0_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_RESERVED0_FIELD;
+#define UNIMAC_RDP_CONTROL_RESERVED0_FIELD_MASK  0x80000000
+#define UNIMAC_RDP_CONTROL_RESERVED0_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_GMII_TX_CLK_GATE_EN_FIELD;
+#define UNIMAC_RDP_CONTROL_GMII_TX_CLK_GATE_EN_FIELD_MASK  0x40000000
+#define UNIMAC_RDP_CONTROL_GMII_TX_CLK_GATE_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_GMII_TX_CLK_GATE_EN_FIELD_SHIFT 30
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_XGMII_SEL_OVRD_FIELD;
+#define UNIMAC_RDP_CONTROL_XGMII_SEL_OVRD_FIELD_MASK  0x20000000
+#define UNIMAC_RDP_CONTROL_XGMII_SEL_OVRD_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_XGMII_SEL_OVRD_FIELD_SHIFT 29
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_MIN_RX_IPG_FIELD;
+#define UNIMAC_RDP_CONTROL_MIN_RX_IPG_FIELD_MASK  0x1f000000
+#define UNIMAC_RDP_CONTROL_MIN_RX_IPG_FIELD_WIDTH 5
+#define UNIMAC_RDP_CONTROL_MIN_RX_IPG_FIELD_SHIFT 24
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_TX_IPG_FIELD;
+#define UNIMAC_RDP_CONTROL_TX_IPG_FIELD_MASK  0x00f80000
+#define UNIMAC_RDP_CONTROL_TX_IPG_FIELD_WIDTH 5
+#define UNIMAC_RDP_CONTROL_TX_IPG_FIELD_SHIFT 19
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_STRICT_PREAMBLE_DIS_FIELD;
+#define UNIMAC_RDP_CONTROL_STRICT_PREAMBLE_DIS_FIELD_MASK  0x00040000
+#define UNIMAC_RDP_CONTROL_STRICT_PREAMBLE_DIS_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_STRICT_PREAMBLE_DIS_FIELD_SHIFT 18
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_GMII_RX_CLK_GATE_EN_FIELD;
+#define UNIMAC_RDP_CONTROL_GMII_RX_CLK_GATE_EN_FIELD_MASK  0x00020000
+#define UNIMAC_RDP_CONTROL_GMII_RX_CLK_GATE_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_GMII_RX_CLK_GATE_EN_FIELD_SHIFT 17
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_RX_START_THRESHOLD_FIELD;
+#define UNIMAC_RDP_CONTROL_RX_START_THRESHOLD_FIELD_MASK  0x0001ff00
+#define UNIMAC_RDP_CONTROL_RX_START_THRESHOLD_FIELD_WIDTH 9
+#define UNIMAC_RDP_CONTROL_RX_START_THRESHOLD_FIELD_SHIFT 8
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_DIC_DIS_FIELD;
+#define UNIMAC_RDP_CONTROL_DIC_DIS_FIELD_MASK  0x00000080
+#define UNIMAC_RDP_CONTROL_DIC_DIS_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_DIC_DIS_FIELD_SHIFT 7
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_XGMII_SEL_FIELD;
+#define UNIMAC_RDP_CONTROL_XGMII_SEL_FIELD_MASK  0x00000040
+#define UNIMAC_RDP_CONTROL_XGMII_SEL_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_XGMII_SEL_FIELD_SHIFT 6
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_STANDARD_MUX_EN_FIELD;
+#define UNIMAC_RDP_CONTROL_STANDARD_MUX_EN_FIELD_MASK  0x00000020
+#define UNIMAC_RDP_CONTROL_STANDARD_MUX_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_STANDARD_MUX_EN_FIELD_SHIFT 5
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_LINK_DOWN_RST_EN_FIELD;
+#define UNIMAC_RDP_CONTROL_LINK_DOWN_RST_EN_FIELD_MASK  0x00000010
+#define UNIMAC_RDP_CONTROL_LINK_DOWN_RST_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_LINK_DOWN_RST_EN_FIELD_SHIFT 4
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_TX_FLUSH_EN_FIELD;
+#define UNIMAC_RDP_CONTROL_TX_FLUSH_EN_FIELD_MASK  0x00000008
+#define UNIMAC_RDP_CONTROL_TX_FLUSH_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_TX_FLUSH_EN_FIELD_SHIFT 3
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_RX_FLUSH_EN_FIELD;
+#define UNIMAC_RDP_CONTROL_RX_FLUSH_EN_FIELD_MASK  0x00000004
+#define UNIMAC_RDP_CONTROL_RX_FLUSH_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_RX_FLUSH_EN_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_XIB_TX_EN_FIELD;
+#define UNIMAC_RDP_CONTROL_XIB_TX_EN_FIELD_MASK  0x00000002
+#define UNIMAC_RDP_CONTROL_XIB_TX_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_XIB_TX_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_CONTROL_XIB_RX_EN_FIELD;
+#define UNIMAC_RDP_CONTROL_XIB_RX_EN_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_CONTROL_XIB_RX_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_CONTROL_XIB_RX_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_EXTENDED_CONTROL_TX_BACKPRESSURE_EN_FIELD;
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_BACKPRESSURE_EN_FIELD_MASK  0x80000000
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_BACKPRESSURE_EN_FIELD_WIDTH 1
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_BACKPRESSURE_EN_FIELD_SHIFT 31
+
+extern const ru_field_rec UNIMAC_RDP_EXTENDED_CONTROL_TX_XON_THRESHOLD_FIELD;
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_XON_THRESHOLD_FIELD_MASK  0x7fc00000
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_XON_THRESHOLD_FIELD_WIDTH 9
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_XON_THRESHOLD_FIELD_SHIFT 22
+
+extern const ru_field_rec UNIMAC_RDP_EXTENDED_CONTROL_TX_XOFF_THRESHOLD_FIELD;
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_XOFF_THRESHOLD_FIELD_MASK  0x003fe000
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_XOFF_THRESHOLD_FIELD_WIDTH 9
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_XOFF_THRESHOLD_FIELD_SHIFT 13
+
+extern const ru_field_rec UNIMAC_RDP_EXTENDED_CONTROL_TX_START_THRESHOLD_FIELD;
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_START_THRESHOLD_FIELD_MASK  0x00001ff0
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_START_THRESHOLD_FIELD_WIDTH 9
+#define UNIMAC_RDP_EXTENDED_CONTROL_TX_START_THRESHOLD_FIELD_SHIFT 4
+
+extern const ru_field_rec UNIMAC_RDP_EXTENDED_CONTROL_RESERVED0_FIELD;
+#define UNIMAC_RDP_EXTENDED_CONTROL_RESERVED0_FIELD_MASK  0x0000000c
+#define UNIMAC_RDP_EXTENDED_CONTROL_RESERVED0_FIELD_WIDTH 2
+#define UNIMAC_RDP_EXTENDED_CONTROL_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_EXTENDED_CONTROL_XGMII_DATA_RATE_FIELD;
+#define UNIMAC_RDP_EXTENDED_CONTROL_XGMII_DATA_RATE_FIELD_MASK  0x00000003
+#define UNIMAC_RDP_EXTENDED_CONTROL_XGMII_DATA_RATE_FIELD_WIDTH 2
+#define UNIMAC_RDP_EXTENDED_CONTROL_XGMII_DATA_RATE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_RESERVED0_FIELD;
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_RESERVED0_FIELD_MASK  0xff000000
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_RESERVED0_FIELD_WIDTH 8
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_MDIV_FIELD;
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_MDIV_FIELD_MASK  0x00ff0000
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_MDIV_FIELD_WIDTH 8
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_MDIV_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_RESERVED1_FIELD;
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_RESERVED1_FIELD_MASK  0x0000ff00
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_RESERVED1_FIELD_WIDTH 8
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_RESERVED1_FIELD_SHIFT 8
+
+extern const ru_field_rec UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_NDIV_FIELD;
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_NDIV_FIELD_MASK  0x000000ff
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_NDIV_FIELD_WIDTH 8
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_NDIV_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_STATUS_RESERVED0_FIELD;
+#define UNIMAC_RDP_STATUS_RESERVED0_FIELD_MASK  0xffffffc0
+#define UNIMAC_RDP_STATUS_RESERVED0_FIELD_WIDTH 26
+#define UNIMAC_RDP_STATUS_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec UNIMAC_RDP_STATUS_RX_FAULT_STATUS_FIELD;
+#define UNIMAC_RDP_STATUS_RX_FAULT_STATUS_FIELD_MASK  0x00000030
+#define UNIMAC_RDP_STATUS_RX_FAULT_STATUS_FIELD_WIDTH 2
+#define UNIMAC_RDP_STATUS_RX_FAULT_STATUS_FIELD_SHIFT 4
+
+extern const ru_field_rec UNIMAC_RDP_STATUS_TX_FIFO_OVERRUN_FIELD;
+#define UNIMAC_RDP_STATUS_TX_FIFO_OVERRUN_FIELD_MASK  0x00000008
+#define UNIMAC_RDP_STATUS_TX_FIFO_OVERRUN_FIELD_WIDTH 1
+#define UNIMAC_RDP_STATUS_TX_FIFO_OVERRUN_FIELD_SHIFT 3
+
+extern const ru_field_rec UNIMAC_RDP_STATUS_TX_FIFO_UNDERRUN_FIELD;
+#define UNIMAC_RDP_STATUS_TX_FIFO_UNDERRUN_FIELD_MASK  0x00000004
+#define UNIMAC_RDP_STATUS_TX_FIFO_UNDERRUN_FIELD_WIDTH 1
+#define UNIMAC_RDP_STATUS_TX_FIFO_UNDERRUN_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_RDP_STATUS_RX_FIFO_UNDERRUN_FIELD;
+#define UNIMAC_RDP_STATUS_RX_FIFO_UNDERRUN_FIELD_MASK  0x00000002
+#define UNIMAC_RDP_STATUS_RX_FIFO_UNDERRUN_FIELD_WIDTH 1
+#define UNIMAC_RDP_STATUS_RX_FIFO_UNDERRUN_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_RDP_STATUS_RX_FIFO_OVERRUN_FIELD;
+#define UNIMAC_RDP_STATUS_RX_FIFO_OVERRUN_FIELD_MASK  0x00000001
+#define UNIMAC_RDP_STATUS_RX_FIFO_OVERRUN_FIELD_WIDTH 1
+#define UNIMAC_RDP_STATUS_RX_FIFO_OVERRUN_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_RX_DISCARD_PACKET_COUNTER_PKT_COUNT_FIELD;
+#define UNIMAC_RDP_RX_DISCARD_PACKET_COUNTER_PKT_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_RX_DISCARD_PACKET_COUNTER_PKT_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_RX_DISCARD_PACKET_COUNTER_PKT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_TX_DISCARD_PACKET_COUNTER_PKT_COUNT_FIELD;
+#define UNIMAC_RDP_TX_DISCARD_PACKET_COUNTER_PKT_COUNT_FIELD_MASK  0xffffffff
+#define UNIMAC_RDP_TX_DISCARD_PACKET_COUNTER_PKT_COUNT_FIELD_WIDTH 32
+#define UNIMAC_RDP_TX_DISCARD_PACKET_COUNTER_PKT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_REV_RESERVED0_FIELD;
+#define UNIMAC_RDP_REV_RESERVED0_FIELD_MASK  0xffff0000
+#define UNIMAC_RDP_REV_RESERVED0_FIELD_WIDTH 16
+#define UNIMAC_RDP_REV_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_RDP_REV_SYS_PORT_REV_FIELD;
+#define UNIMAC_RDP_REV_SYS_PORT_REV_FIELD_MASK  0x0000ffff
+#define UNIMAC_RDP_REV_SYS_PORT_REV_FIELD_WIDTH 16
+#define UNIMAC_RDP_REV_SYS_PORT_REV_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_RXERR_MASK_RESERVED0_FIELD;
+#define UNIMAC_RDP_UMAC_RXERR_MASK_RESERVED0_FIELD_MASK  0xfffc0000
+#define UNIMAC_RDP_UMAC_RXERR_MASK_RESERVED0_FIELD_WIDTH 14
+#define UNIMAC_RDP_UMAC_RXERR_MASK_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec UNIMAC_RDP_UMAC_RXERR_MASK_MAC_RXERR_MASK_FIELD;
+#define UNIMAC_RDP_UMAC_RXERR_MASK_MAC_RXERR_MASK_FIELD_MASK  0x0003ffff
+#define UNIMAC_RDP_UMAC_RXERR_MASK_MAC_RXERR_MASK_FIELD_WIDTH 18
+#define UNIMAC_RDP_UMAC_RXERR_MASK_MAC_RXERR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_RDP_MIB_MAX_PKT_SIZE_RESERVED0_FIELD;
+#define UNIMAC_RDP_MIB_MAX_PKT_SIZE_RESERVED0_FIELD_MASK  0xffffc000
+#define UNIMAC_RDP_MIB_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18
+#define UNIMAC_RDP_MIB_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec UNIMAC_RDP_MIB_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD;
+#define UNIMAC_RDP_MIB_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK  0x00003fff
+#define UNIMAC_RDP_MIB_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14
+#define UNIMAC_RDP_MIB_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_FWD_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_FWD_FIELD_MASK  0x00000001
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_FWD_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_FWD_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_OWRT_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_OWRT_FIELD_MASK  0x00000002
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_OWRT_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_OWRT_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_RESERVED0_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_RESERVED0_FIELD_MASK  0xfffffffc
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_RESERVED0_FIELD_WIDTH 30
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_MAX_PKT_SIZE_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_MAX_PKT_SIZE_FIELD_MASK  0x00003fff
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_MAX_PKT_SIZE_FIELD_WIDTH 14
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_MAX_PKT_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED0_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED0_FIELD_MASK  0x0000c000
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED0_FIELD_WIDTH 2
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RXFIFO_CONGESTION_THRESHOLD_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RXFIFO_CONGESTION_THRESHOLD_FIELD_MASK  0x01ff0000
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RXFIFO_CONGESTION_THRESHOLD_FIELD_WIDTH 9
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RXFIFO_CONGESTION_THRESHOLD_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED1_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED1_FIELD_MASK  0xfe000000
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED1_FIELD_WIDTH 7
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED1_FIELD_SHIFT 25
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RXFIFO_PAUSE_THRESHOLD_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RXFIFO_PAUSE_THRESHOLD_FIELD_MASK  0x000001ff
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RXFIFO_PAUSE_THRESHOLD_FIELD_WIDTH 9
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RXFIFO_PAUSE_THRESHOLD_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED0_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED0_FIELD_MASK  0x0000fe00
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED0_FIELD_WIDTH 7
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT_FIELD_MASK  0x00010000
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT_FIELD_SHIFT 16
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_EXT_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_EXT_FIELD_MASK  0x00020000
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_EXT_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_EXT_FIELD_SHIFT 17
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_FIFO_OVERRUN_CTL_EN_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_FIFO_OVERRUN_CTL_EN_FIELD_MASK  0x00040000
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_FIFO_OVERRUN_CTL_EN_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_FIFO_OVERRUN_CTL_EN_FIELD_SHIFT 18
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REMOTE_LOOPBACK_EN_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REMOTE_LOOPBACK_EN_FIELD_MASK  0x00080000
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REMOTE_LOOPBACK_EN_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REMOTE_LOOPBACK_EN_FIELD_SHIFT 19
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED1_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED1_FIELD_MASK  0xfff00000
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED1_FIELD_WIDTH 12
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED1_FIELD_SHIFT 20
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PORT_RATE_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PORT_RATE_FIELD_MASK  0x00000007
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PORT_RATE_FIELD_WIDTH 3
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PORT_RATE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_TX_DETECT_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_TX_DETECT_FIELD_MASK  0x00000008
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_TX_DETECT_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_TX_DETECT_FIELD_SHIFT 3
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_RX_DETECT_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_RX_DETECT_FIELD_MASK  0x00000010
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_RX_DETECT_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_RX_DETECT_FIELD_SHIFT 4
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_FIELD_MASK  0x00001fe0
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_FIELD_WIDTH 8
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_FIELD_SHIFT 5
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_VALID_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_VALID_FIELD_MASK  0x00002000
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_VALID_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_VALID_FIELD_SHIFT 13
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED0_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED0_FIELD_MASK  0xffffc000
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED0_FIELD_WIDTH 18
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_DEBUG_SEL_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_DEBUG_SEL_FIELD_MASK  0x000000ff
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_DEBUG_SEL_FIELD_WIDTH 8
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_DEBUG_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_RESERVED0_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_RESERVED0_FIELD_MASK  0xffffff00
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_RESERVED0_FIELD_WIDTH 24
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_UNIMAC_RST_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_UNIMAC_RST_FIELD_MASK  0x00000001
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_UNIMAC_RST_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_UNIMAC_RST_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_RESERVED0_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_RESERVED0_FIELD_MASK  0xfffffffe
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_RESERVED0_FIELD_WIDTH 31
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_OVERRUN_COUNTER_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_OVERRUN_COUNTER_FIELD_MASK  0xffffffff
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_OVERRUN_COUNTER_FIELD_WIDTH 32
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_OVERRUN_COUNTER_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_TSI_SIGN_EXT_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_TSI_SIGN_EXT_FIELD_MASK  0x00000001
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_TSI_SIGN_EXT_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_TSI_SIGN_EXT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_OSTS_TIMER_DIS_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_OSTS_TIMER_DIS_FIELD_MASK  0x00000002
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_OSTS_TIMER_DIS_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_OSTS_TIMER_DIS_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_EGR_1588_TS_MODE_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_EGR_1588_TS_MODE_FIELD_MASK  0x00000004
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_EGR_1588_TS_MODE_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_EGR_1588_TS_MODE_FIELD_SHIFT 2
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_RESERVED0_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_RESERVED0_FIELD_MASK  0xfffffff8
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_RESERVED0_FIELD_WIDTH 29
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_GEN_INT_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_GEN_INT_FIELD_MASK  0x00000001
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_GEN_INT_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_GEN_INT_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_RESERVED0_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_RESERVED0_FIELD_MASK  0xfffffffe
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_RESERVED0_FIELD_WIDTH 31
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_VALUE_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_VALUE_FIELD_MASK  0x00000001
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_VALUE_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_RESERVED0_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_RESERVED0_FIELD_MASK  0xfffffffe
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_RESERVED0_FIELD_WIDTH 31
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_VALUE_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_VALUE_FIELD_MASK  0x00000001
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_VALUE_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_RESERVED0_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_RESERVED0_FIELD_MASK  0xfffffffe
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_RESERVED0_FIELD_WIDTH 31
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_VALUE_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_VALUE_FIELD_MASK  0x00000001
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_VALUE_FIELD_WIDTH 1
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_RESERVED0_FIELD;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_RESERVED0_FIELD_MASK  0xfffffffe
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_RESERVED0_FIELD_WIDTH 31
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_FIELD;
+#define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_FIELD_MASK  0xffffffff
+#define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_FIELD_WIDTH 32
+#define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_FIELD;
+#define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_FIELD_MASK  0x000000ff
+#define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_FIELD_WIDTH 8
+#define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_RESERVED0_FIELD;
+#define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_RESERVED0_FIELD_MASK  0xffffff00
+#define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_RESERVED0_FIELD_WIDTH 24
+#define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_FIELD;
+#define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_FIELD_MASK  0xffffffff
+#define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_FIELD_WIDTH 32
+#define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_FIELD;
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_FIELD_MASK  0xffffffff
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_FIELD_WIDTH 32
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_FIELD;
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_FIELD_MASK  0xffffffff
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_FIELD_WIDTH 32
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_FIELD;
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_FIELD_MASK  0xffffffff
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_FIELD_WIDTH 32
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_FIELD;
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_FIELD_MASK  0xffffffff
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_FIELD_WIDTH 32
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_FIELD_MASK  0x0000000f
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_FIELD_WIDTH 4
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_RESERVED0_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_RESERVED0_FIELD_MASK  0xfffffff0
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_RESERVED0_FIELD_WIDTH 28
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_DONE_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_DONE_FIELD_MASK  0x00000001
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_DONE_FIELD_WIDTH 1
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_DONE_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_RESERVED0_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_RESERVED0_FIELD_MASK  0xfffffffe
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_RESERVED0_FIELD_WIDTH 31
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_KEY1_IND_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_KEY1_IND_FIELD_MASK  0x00000001
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_KEY1_IND_FIELD_WIDTH 1
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_KEY1_IND_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_MASK  0x000007fe
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_WIDTH 10
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_SHIFT 1
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_RESERVED0_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_RESERVED0_FIELD_MASK  0xfffff800
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_RESERVED0_FIELD_WIDTH 21
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_VALID_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_VALID_FIELD_MASK  0x00000001
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_VALID_FIELD_WIDTH 1
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_RESERVED0_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_RESERVED0_FIELD_MASK  0xfffffffe
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_RESERVED0_FIELD_WIDTH 31
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_VALID_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_VALID_FIELD_MASK  0x00000001
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_VALID_FIELD_WIDTH 1
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_RESERVED0_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_MASK  0xfffffffe
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_WIDTH 31
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_MATCH_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_MATCH_FIELD_MASK  0x00000001
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_MATCH_FIELD_WIDTH 1
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_MATCH_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED0_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED0_FIELD_MASK  0x0000000e
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED0_FIELD_WIDTH 3
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_FIELD_MASK  0x00003ff0
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_FIELD_WIDTH 10
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_FIELD_SHIFT 4
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED1_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED1_FIELD_MASK  0xffffc000
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED1_FIELD_WIDTH 18
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED1_FIELD_SHIFT 14
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_FIELD_MASK  0xffffffff
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_FIELD_WIDTH 32
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_FIELD;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_FIELD_MASK  0xffffffff
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_FIELD_WIDTH 32
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_SELECT_MODULE_FIELD;
+#define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_SELECT_MODULE_FIELD_MASK  0x00000003
+#define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_SELECT_MODULE_FIELD_WIDTH 2
+#define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_SELECT_MODULE_FIELD_SHIFT 0
+
+extern const ru_field_rec TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_RESERVED0_FIELD;
+#define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_RESERVED0_FIELD_MASK  0xfffffffc
+#define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_RESERVED0_FIELD_WIDTH 30
+#define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_VALUE_FIELD;
+#define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_VALUE_FIELD_MASK  0x00000001
+#define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_VALUE_FIELD_WIDTH 1
+#define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_RESERVED0_FIELD;
+#define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_RESERVED0_FIELD_MASK  0xfffffffe
+#define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_RESERVED0_FIELD_WIDTH 31
+#define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_GENERAL_CONFIGURATION_PAD_HIGH_VAL_FIELD;
+#define HASH_GENERAL_CONFIGURATION_PAD_HIGH_VAL_FIELD_MASK  0x0fffffff
+#define HASH_GENERAL_CONFIGURATION_PAD_HIGH_VAL_FIELD_WIDTH 28
+#define HASH_GENERAL_CONFIGURATION_PAD_HIGH_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_GENERAL_CONFIGURATION_PAD_HIGH_RESERVED0_FIELD;
+#define HASH_GENERAL_CONFIGURATION_PAD_HIGH_RESERVED0_FIELD_MASK  0xf0000000
+#define HASH_GENERAL_CONFIGURATION_PAD_HIGH_RESERVED0_FIELD_WIDTH 4
+#define HASH_GENERAL_CONFIGURATION_PAD_HIGH_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec HASH_GENERAL_CONFIGURATION_PAD_LOW_VAL_FIELD;
+#define HASH_GENERAL_CONFIGURATION_PAD_LOW_VAL_FIELD_MASK  0xffffffff
+#define HASH_GENERAL_CONFIGURATION_PAD_LOW_VAL_FIELD_WIDTH 32
+#define HASH_GENERAL_CONFIGURATION_PAD_LOW_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_VAL_FIELD;
+#define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_VAL_FIELD_MASK  0x0000000f
+#define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_VAL_FIELD_WIDTH 4
+#define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_RESERVED0_FIELD;
+#define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_RESERVED0_FIELD_MASK  0xfffffff0
+#define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_RESERVED0_FIELD_WIDTH 28
+#define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec HASH_GENERAL_CONFIGURATION_UNDO_FIX_FRST_MUL_HIT_FIELD;
+#define HASH_GENERAL_CONFIGURATION_UNDO_FIX_FRST_MUL_HIT_FIELD_MASK  0x00000001
+#define HASH_GENERAL_CONFIGURATION_UNDO_FIX_FRST_MUL_HIT_FIELD_WIDTH 1
+#define HASH_GENERAL_CONFIGURATION_UNDO_FIX_FRST_MUL_HIT_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_GENERAL_CONFIGURATION_UNDO_FIX_RESERVED0_FIELD;
+#define HASH_GENERAL_CONFIGURATION_UNDO_FIX_RESERVED0_FIELD_MASK  0xfffffffe
+#define HASH_GENERAL_CONFIGURATION_UNDO_FIX_RESERVED0_FIELD_WIDTH 31
+#define HASH_GENERAL_CONFIGURATION_UNDO_FIX_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_PM_COUNTERS_HITS_CNT_FIELD;
+#define HASH_PM_COUNTERS_HITS_CNT_FIELD_MASK  0xffffffff
+#define HASH_PM_COUNTERS_HITS_CNT_FIELD_WIDTH 32
+#define HASH_PM_COUNTERS_HITS_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_PM_COUNTERS_SRCHS_CNT_FIELD;
+#define HASH_PM_COUNTERS_SRCHS_CNT_FIELD_MASK  0xffffffff
+#define HASH_PM_COUNTERS_SRCHS_CNT_FIELD_WIDTH 32
+#define HASH_PM_COUNTERS_SRCHS_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_PM_COUNTERS_MISS_CNT_FIELD;
+#define HASH_PM_COUNTERS_MISS_CNT_FIELD_MASK  0xffffffff
+#define HASH_PM_COUNTERS_MISS_CNT_FIELD_WIDTH 32
+#define HASH_PM_COUNTERS_MISS_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_FIELD;
+#define HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_FIELD_MASK  0xffffffff
+#define HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_FIELD_WIDTH 32
+#define HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_FIELD;
+#define HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_FIELD_MASK  0xffffffff
+#define HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_FIELD_WIDTH 32
+#define HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_FIELD;
+#define HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_FIELD_MASK  0xffffffff
+#define HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_FIELD_WIDTH 32
+#define HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_FIELD;
+#define HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_FIELD_MASK  0xffffffff
+#define HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_FIELD_WIDTH 32
+#define HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_PM_COUNTERS_FRZ_CNT_VAL_FIELD;
+#define HASH_PM_COUNTERS_FRZ_CNT_VAL_FIELD_MASK  0x00000001
+#define HASH_PM_COUNTERS_FRZ_CNT_VAL_FIELD_WIDTH 1
+#define HASH_PM_COUNTERS_FRZ_CNT_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_PM_COUNTERS_FRZ_CNT_RESERVED0_FIELD;
+#define HASH_PM_COUNTERS_FRZ_CNT_RESERVED0_FIELD_MASK  0xfffffffe
+#define HASH_PM_COUNTERS_FRZ_CNT_RESERVED0_FIELD_WIDTH 31
+#define HASH_PM_COUNTERS_FRZ_CNT_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_FIELD;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_FIELD_MASK  0x000007ff
+#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_FIELD_WIDTH 11
+#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED0_FIELD;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED0_FIELD_MASK  0x0000f800
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED0_FIELD_WIDTH 5
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_FIELD;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_FIELD_MASK  0x00070000
+#define HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_FIELD_WIDTH 3
+#define HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_FIELD_SHIFT 16
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED1_FIELD;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED1_FIELD_MASK  0x00080000
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED1_FIELD_WIDTH 1
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED1_FIELD_SHIFT 19
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_FIELD;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_FIELD_MASK  0x00f00000
+#define HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_FIELD_WIDTH 4
+#define HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_FIELD_SHIFT 20
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_CAM_EN_FIELD;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_CAM_EN_FIELD_MASK  0x01000000
+#define HASH_LKUP_TBL_CFG_TBL_CFG_CAM_EN_FIELD_WIDTH 1
+#define HASH_LKUP_TBL_CFG_TBL_CFG_CAM_EN_FIELD_SHIFT 24
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_DIRECT_LKUP_EN_FIELD;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_DIRECT_LKUP_EN_FIELD_MASK  0x02000000
+#define HASH_LKUP_TBL_CFG_TBL_CFG_DIRECT_LKUP_EN_FIELD_WIDTH 1
+#define HASH_LKUP_TBL_CFG_TBL_CFG_DIRECT_LKUP_EN_FIELD_SHIFT 25
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_HASH_TYPE_FIELD;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_TYPE_FIELD_MASK  0x04000000
+#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_TYPE_FIELD_WIDTH 1
+#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_TYPE_FIELD_SHIFT 26
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED2_FIELD;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED2_FIELD_MASK  0x08000000
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED2_FIELD_WIDTH 1
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED2_FIELD_SHIFT 27
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_FIELD;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_FIELD_MASK  0x30000000
+#define HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_FIELD_WIDTH 2
+#define HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_FIELD_SHIFT 28
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED3_FIELD;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED3_FIELD_MASK  0xc0000000
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED3_FIELD_WIDTH 2
+#define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED3_FIELD_SHIFT 30
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_FIELD;
+#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_FIELD_MASK  0x0fffffff
+#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_FIELD_WIDTH 28
+#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_RESERVED0_FIELD;
+#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_RESERVED0_FIELD_MASK  0xf0000000
+#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_RESERVED0_FIELD_WIDTH 4
+#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_FIELD;
+#define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_FIELD_MASK  0xffffffff
+#define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_FIELD_WIDTH 32
+#define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_FIELD;
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_FIELD_MASK  0x00000fff
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_FIELD_WIDTH 12
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_FIELD;
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_FIELD_MASK  0x01fff000
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_FIELD_WIDTH 13
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_FIELD_SHIFT 12
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED0_FIELD;
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED0_FIELD_MASK  0x0e000000
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED0_FIELD_WIDTH 3
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED0_FIELD_SHIFT 25
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_FIELD;
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_FIELD_MASK  0x70000000
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_FIELD_WIDTH 3
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_FIELD_SHIFT 28
+
+extern const ru_field_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED1_FIELD;
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED1_FIELD_MASK  0x80000000
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED1_FIELD_WIDTH 1
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED1_FIELD_SHIFT 31
+
+extern const ru_field_rec HASH_CAM_CONFIGURATION_CNTXT_CFG_BASE_ADDRESS_FIELD;
+#define HASH_CAM_CONFIGURATION_CNTXT_CFG_BASE_ADDRESS_FIELD_MASK  0x00000fff
+#define HASH_CAM_CONFIGURATION_CNTXT_CFG_BASE_ADDRESS_FIELD_WIDTH 12
+#define HASH_CAM_CONFIGURATION_CNTXT_CFG_BASE_ADDRESS_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_CONFIGURATION_CNTXT_CFG_RESERVED0_FIELD;
+#define HASH_CAM_CONFIGURATION_CNTXT_CFG_RESERVED0_FIELD_MASK  0xfffff000
+#define HASH_CAM_CONFIGURATION_CNTXT_CFG_RESERVED0_FIELD_WIDTH 20
+#define HASH_CAM_CONFIGURATION_CNTXT_CFG_RESERVED0_FIELD_SHIFT 12
+
+extern const ru_field_rec HASH_CAM_INDIRECT_OP_CMD_FIELD;
+#define HASH_CAM_INDIRECT_OP_CMD_FIELD_MASK  0x0000000f
+#define HASH_CAM_INDIRECT_OP_CMD_FIELD_WIDTH 4
+#define HASH_CAM_INDIRECT_OP_CMD_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_INDIRECT_OP_RESERVED0_FIELD;
+#define HASH_CAM_INDIRECT_OP_RESERVED0_FIELD_MASK  0xfffffff0
+#define HASH_CAM_INDIRECT_OP_RESERVED0_FIELD_WIDTH 28
+#define HASH_CAM_INDIRECT_OP_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec HASH_CAM_INDIRECT_OP_DONE_VAL_FIELD;
+#define HASH_CAM_INDIRECT_OP_DONE_VAL_FIELD_MASK  0x00000001
+#define HASH_CAM_INDIRECT_OP_DONE_VAL_FIELD_WIDTH 1
+#define HASH_CAM_INDIRECT_OP_DONE_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_INDIRECT_OP_DONE_RESERVED0_FIELD;
+#define HASH_CAM_INDIRECT_OP_DONE_RESERVED0_FIELD_MASK  0xfffffffe
+#define HASH_CAM_INDIRECT_OP_DONE_RESERVED0_FIELD_WIDTH 31
+#define HASH_CAM_INDIRECT_OP_DONE_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_CAM_INDIRECT_ADDR_KEY1_IND_FIELD;
+#define HASH_CAM_INDIRECT_ADDR_KEY1_IND_FIELD_MASK  0x00000001
+#define HASH_CAM_INDIRECT_ADDR_KEY1_IND_FIELD_WIDTH 1
+#define HASH_CAM_INDIRECT_ADDR_KEY1_IND_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD;
+#define HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_MASK  0x0000007e
+#define HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_WIDTH 6
+#define HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_CAM_INDIRECT_ADDR_RESERVED0_FIELD;
+#define HASH_CAM_INDIRECT_ADDR_RESERVED0_FIELD_MASK  0xffffff80
+#define HASH_CAM_INDIRECT_ADDR_RESERVED0_FIELD_WIDTH 25
+#define HASH_CAM_INDIRECT_ADDR_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec HASH_CAM_INDIRECT_VLID_IN_VALID_FIELD;
+#define HASH_CAM_INDIRECT_VLID_IN_VALID_FIELD_MASK  0x00000001
+#define HASH_CAM_INDIRECT_VLID_IN_VALID_FIELD_WIDTH 1
+#define HASH_CAM_INDIRECT_VLID_IN_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_INDIRECT_VLID_IN_RESERVED0_FIELD;
+#define HASH_CAM_INDIRECT_VLID_IN_RESERVED0_FIELD_MASK  0xfffffffe
+#define HASH_CAM_INDIRECT_VLID_IN_RESERVED0_FIELD_WIDTH 31
+#define HASH_CAM_INDIRECT_VLID_IN_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_CAM_INDIRECT_VLID_OUT_VALID_FIELD;
+#define HASH_CAM_INDIRECT_VLID_OUT_VALID_FIELD_MASK  0x00000001
+#define HASH_CAM_INDIRECT_VLID_OUT_VALID_FIELD_WIDTH 1
+#define HASH_CAM_INDIRECT_VLID_OUT_VALID_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_INDIRECT_VLID_OUT_RESERVED0_FIELD;
+#define HASH_CAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_MASK  0xfffffffe
+#define HASH_CAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_WIDTH 31
+#define HASH_CAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_CAM_INDIRECT_RSLT_MATCH_FIELD;
+#define HASH_CAM_INDIRECT_RSLT_MATCH_FIELD_MASK  0x00000001
+#define HASH_CAM_INDIRECT_RSLT_MATCH_FIELD_WIDTH 1
+#define HASH_CAM_INDIRECT_RSLT_MATCH_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_INDIRECT_RSLT_RESERVED0_FIELD;
+#define HASH_CAM_INDIRECT_RSLT_RESERVED0_FIELD_MASK  0x0000000e
+#define HASH_CAM_INDIRECT_RSLT_RESERVED0_FIELD_WIDTH 3
+#define HASH_CAM_INDIRECT_RSLT_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_CAM_INDIRECT_RSLT_INDEX_FIELD;
+#define HASH_CAM_INDIRECT_RSLT_INDEX_FIELD_MASK  0x000003f0
+#define HASH_CAM_INDIRECT_RSLT_INDEX_FIELD_WIDTH 6
+#define HASH_CAM_INDIRECT_RSLT_INDEX_FIELD_SHIFT 4
+
+extern const ru_field_rec HASH_CAM_INDIRECT_RSLT_RESERVED1_FIELD;
+#define HASH_CAM_INDIRECT_RSLT_RESERVED1_FIELD_MASK  0xfffffc00
+#define HASH_CAM_INDIRECT_RSLT_RESERVED1_FIELD_WIDTH 22
+#define HASH_CAM_INDIRECT_RSLT_RESERVED1_FIELD_SHIFT 10
+
+extern const ru_field_rec HASH_CAM_INDIRECT_KEY_IN_VALUE_FIELD;
+#define HASH_CAM_INDIRECT_KEY_IN_VALUE_FIELD_MASK  0xffffffff
+#define HASH_CAM_INDIRECT_KEY_IN_VALUE_FIELD_WIDTH 32
+#define HASH_CAM_INDIRECT_KEY_IN_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_INDIRECT_KEY_OUT_VALUE_FIELD;
+#define HASH_CAM_INDIRECT_KEY_OUT_VALUE_FIELD_MASK  0xffffffff
+#define HASH_CAM_INDIRECT_KEY_OUT_VALUE_FIELD_WIDTH 32
+#define HASH_CAM_INDIRECT_KEY_OUT_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_STATUS_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_STATUS_VALUE_FIELD_MASK  0xffffffff
+#define HASH_CAM_BIST_BIST_STATUS_VALUE_FIELD_WIDTH 32
+#define HASH_CAM_BIST_BIST_STATUS_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_COMPARE_EN_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_VALUE_FIELD_MASK  0x00000001
+#define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_VALUE_FIELD_WIDTH 1
+#define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_COMPARE_EN_RESERVED0_FIELD;
+#define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_RESERVED0_FIELD_MASK  0xfffffffe
+#define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_RESERVED0_FIELD_WIDTH 31
+#define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_DATA_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_DBG_DATA_VALUE_FIELD_MASK  0xffffffff
+#define HASH_CAM_BIST_BIST_DBG_DATA_VALUE_FIELD_WIDTH 32
+#define HASH_CAM_BIST_BIST_DBG_DATA_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_FIELD_MASK  0x000000ff
+#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_FIELD_WIDTH 8
+#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_RESERVED0_FIELD;
+#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_RESERVED0_FIELD_MASK  0xffffff00
+#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_RESERVED0_FIELD_WIDTH 24
+#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_DATA_VALID_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_DBG_DATA_VALID_VALUE_FIELD_MASK  0x00000001
+#define HASH_CAM_BIST_BIST_DBG_DATA_VALID_VALUE_FIELD_WIDTH 1
+#define HASH_CAM_BIST_BIST_DBG_DATA_VALID_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_DATA_VALID_RESERVED0_FIELD;
+#define HASH_CAM_BIST_BIST_DBG_DATA_VALID_RESERVED0_FIELD_MASK  0xfffffffe
+#define HASH_CAM_BIST_BIST_DBG_DATA_VALID_RESERVED0_FIELD_WIDTH 31
+#define HASH_CAM_BIST_BIST_DBG_DATA_VALID_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_EN_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_EN_VALUE_FIELD_MASK  0x0000ffff
+#define HASH_CAM_BIST_BIST_EN_VALUE_FIELD_WIDTH 16
+#define HASH_CAM_BIST_BIST_EN_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_EN_RESERVED0_FIELD;
+#define HASH_CAM_BIST_BIST_EN_RESERVED0_FIELD_MASK  0xffff0000
+#define HASH_CAM_BIST_BIST_EN_RESERVED0_FIELD_WIDTH 16
+#define HASH_CAM_BIST_BIST_EN_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_MODE_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_MODE_VALUE_FIELD_MASK  0x00000003
+#define HASH_CAM_BIST_BIST_MODE_VALUE_FIELD_WIDTH 2
+#define HASH_CAM_BIST_BIST_MODE_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_MODE_RESERVED0_FIELD;
+#define HASH_CAM_BIST_BIST_MODE_RESERVED0_FIELD_MASK  0xfffffffc
+#define HASH_CAM_BIST_BIST_MODE_RESERVED0_FIELD_WIDTH 30
+#define HASH_CAM_BIST_BIST_MODE_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_RST_L_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_RST_L_VALUE_FIELD_MASK  0x00000001
+#define HASH_CAM_BIST_BIST_RST_L_VALUE_FIELD_WIDTH 1
+#define HASH_CAM_BIST_BIST_RST_L_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_RST_L_RESERVED0_FIELD;
+#define HASH_CAM_BIST_BIST_RST_L_RESERVED0_FIELD_MASK  0xfffffffe
+#define HASH_CAM_BIST_BIST_RST_L_RESERVED0_FIELD_WIDTH 31
+#define HASH_CAM_BIST_BIST_RST_L_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_FIELD_MASK  0x000000ff
+#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_FIELD_WIDTH 8
+#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_RESERVED0_FIELD;
+#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_RESERVED0_FIELD_MASK  0xffffff00
+#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_RESERVED0_FIELD_WIDTH 24
+#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec HASH_CAM_BIST_DBG_EN_VALUE_FIELD;
+#define HASH_CAM_BIST_DBG_EN_VALUE_FIELD_MASK  0x0000ffff
+#define HASH_CAM_BIST_DBG_EN_VALUE_FIELD_WIDTH 16
+#define HASH_CAM_BIST_DBG_EN_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_DBG_EN_RESERVED0_FIELD;
+#define HASH_CAM_BIST_DBG_EN_RESERVED0_FIELD_MASK  0xffff0000
+#define HASH_CAM_BIST_DBG_EN_RESERVED0_FIELD_WIDTH 16
+#define HASH_CAM_BIST_DBG_EN_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_FIELD_MASK  0x00000007
+#define HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_FIELD_WIDTH 3
+#define HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_CASCADE_SELECT_RESERVED0_FIELD;
+#define HASH_CAM_BIST_BIST_CASCADE_SELECT_RESERVED0_FIELD_MASK  0xfffffff8
+#define HASH_CAM_BIST_BIST_CASCADE_SELECT_RESERVED0_FIELD_WIDTH 29
+#define HASH_CAM_BIST_BIST_CASCADE_SELECT_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_FIELD_MASK  0x0000000f
+#define HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_FIELD_WIDTH 4
+#define HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_BLOCK_SELECT_RESERVED0_FIELD;
+#define HASH_CAM_BIST_BIST_BLOCK_SELECT_RESERVED0_FIELD_MASK  0xfffffff0
+#define HASH_CAM_BIST_BIST_BLOCK_SELECT_RESERVED0_FIELD_WIDTH 28
+#define HASH_CAM_BIST_BIST_BLOCK_SELECT_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_REPAIR_ENABLE_VALUE_FIELD;
+#define HASH_CAM_BIST_BIST_REPAIR_ENABLE_VALUE_FIELD_MASK  0x00000001
+#define HASH_CAM_BIST_BIST_REPAIR_ENABLE_VALUE_FIELD_WIDTH 1
+#define HASH_CAM_BIST_BIST_REPAIR_ENABLE_VALUE_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CAM_BIST_BIST_REPAIR_ENABLE_RESERVED0_FIELD;
+#define HASH_CAM_BIST_BIST_REPAIR_ENABLE_RESERVED0_FIELD_MASK  0xfffffffe
+#define HASH_CAM_BIST_BIST_REPAIR_ENABLE_RESERVED0_FIELD_WIDTH 31
+#define HASH_CAM_BIST_BIST_REPAIR_ENABLE_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_INTR_CTRL_ISR_INVLD_CMD_FIELD;
+#define HASH_INTR_CTRL_ISR_INVLD_CMD_FIELD_MASK  0x00000001
+#define HASH_INTR_CTRL_ISR_INVLD_CMD_FIELD_WIDTH 1
+#define HASH_INTR_CTRL_ISR_INVLD_CMD_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_INTR_CTRL_ISR_MULT_MATCH_FIELD;
+#define HASH_INTR_CTRL_ISR_MULT_MATCH_FIELD_MASK  0x00000002
+#define HASH_INTR_CTRL_ISR_MULT_MATCH_FIELD_WIDTH 1
+#define HASH_INTR_CTRL_ISR_MULT_MATCH_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_INTR_CTRL_ISR_HASH_0_IDX_OVFLV_FIELD;
+#define HASH_INTR_CTRL_ISR_HASH_0_IDX_OVFLV_FIELD_MASK  0x00000004
+#define HASH_INTR_CTRL_ISR_HASH_0_IDX_OVFLV_FIELD_WIDTH 1
+#define HASH_INTR_CTRL_ISR_HASH_0_IDX_OVFLV_FIELD_SHIFT 2
+
+extern const ru_field_rec HASH_INTR_CTRL_ISR_HASH_1_IDX_OVFLV_FIELD;
+#define HASH_INTR_CTRL_ISR_HASH_1_IDX_OVFLV_FIELD_MASK  0x00000008
+#define HASH_INTR_CTRL_ISR_HASH_1_IDX_OVFLV_FIELD_WIDTH 1
+#define HASH_INTR_CTRL_ISR_HASH_1_IDX_OVFLV_FIELD_SHIFT 3
+
+extern const ru_field_rec HASH_INTR_CTRL_ISR_HASH_2_IDX_OVFLV_FIELD;
+#define HASH_INTR_CTRL_ISR_HASH_2_IDX_OVFLV_FIELD_MASK  0x00000010
+#define HASH_INTR_CTRL_ISR_HASH_2_IDX_OVFLV_FIELD_WIDTH 1
+#define HASH_INTR_CTRL_ISR_HASH_2_IDX_OVFLV_FIELD_SHIFT 4
+
+extern const ru_field_rec HASH_INTR_CTRL_ISR_HASH_3_IDX_OVFLV_FIELD;
+#define HASH_INTR_CTRL_ISR_HASH_3_IDX_OVFLV_FIELD_MASK  0x00000020
+#define HASH_INTR_CTRL_ISR_HASH_3_IDX_OVFLV_FIELD_WIDTH 1
+#define HASH_INTR_CTRL_ISR_HASH_3_IDX_OVFLV_FIELD_SHIFT 5
+
+extern const ru_field_rec HASH_INTR_CTRL_ISR_CNTXT_IDX_OVFLV_FIELD;
+#define HASH_INTR_CTRL_ISR_CNTXT_IDX_OVFLV_FIELD_MASK  0x00000040
+#define HASH_INTR_CTRL_ISR_CNTXT_IDX_OVFLV_FIELD_WIDTH 1
+#define HASH_INTR_CTRL_ISR_CNTXT_IDX_OVFLV_FIELD_SHIFT 6
+
+extern const ru_field_rec HASH_INTR_CTRL_ISR_RESERVED0_FIELD;
+#define HASH_INTR_CTRL_ISR_RESERVED0_FIELD_MASK  0xffffff80
+#define HASH_INTR_CTRL_ISR_RESERVED0_FIELD_WIDTH 25
+#define HASH_INTR_CTRL_ISR_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec HASH_INTR_CTRL_ISM_ISM_FIELD;
+#define HASH_INTR_CTRL_ISM_ISM_FIELD_MASK  0xffffffff
+#define HASH_INTR_CTRL_ISM_ISM_FIELD_WIDTH 32
+#define HASH_INTR_CTRL_ISM_ISM_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_INTR_CTRL_IER_IEM_FIELD;
+#define HASH_INTR_CTRL_IER_IEM_FIELD_MASK  0xffffffff
+#define HASH_INTR_CTRL_IER_IEM_FIELD_WIDTH 32
+#define HASH_INTR_CTRL_IER_IEM_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_INTR_CTRL_ITR_IST_FIELD;
+#define HASH_INTR_CTRL_ITR_IST_FIELD_MASK  0xffffffff
+#define HASH_INTR_CTRL_ITR_IST_FIELD_WIDTH 32
+#define HASH_INTR_CTRL_ITR_IST_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG0_VAL_FIELD;
+#define HASH_DEBUG_DBG0_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG0_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG0_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG1_VAL_FIELD;
+#define HASH_DEBUG_DBG1_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG1_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG1_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG2_VAL_FIELD;
+#define HASH_DEBUG_DBG2_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG2_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG2_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG3_VAL_FIELD;
+#define HASH_DEBUG_DBG3_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG3_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG3_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG4_VAL_FIELD;
+#define HASH_DEBUG_DBG4_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG4_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG4_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG5_VAL_FIELD;
+#define HASH_DEBUG_DBG5_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG5_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG5_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG6_VAL_FIELD;
+#define HASH_DEBUG_DBG6_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG6_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG6_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG7_VAL_FIELD;
+#define HASH_DEBUG_DBG7_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG7_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG7_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG8_VAL_FIELD;
+#define HASH_DEBUG_DBG8_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG8_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG8_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG9_VAL_FIELD;
+#define HASH_DEBUG_DBG9_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG9_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG9_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG10_VAL_FIELD;
+#define HASH_DEBUG_DBG10_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG10_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG10_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG11_VAL_FIELD;
+#define HASH_DEBUG_DBG11_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG11_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG11_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG12_VAL_FIELD;
+#define HASH_DEBUG_DBG12_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG12_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG12_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG13_VAL_FIELD;
+#define HASH_DEBUG_DBG13_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG13_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG13_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG14_VAL_FIELD;
+#define HASH_DEBUG_DBG14_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG14_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG14_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG15_VAL_FIELD;
+#define HASH_DEBUG_DBG15_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG15_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG15_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG16_VAL_FIELD;
+#define HASH_DEBUG_DBG16_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG16_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG16_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG17_VAL_FIELD;
+#define HASH_DEBUG_DBG17_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG17_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG17_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG18_VAL_FIELD;
+#define HASH_DEBUG_DBG18_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG18_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG18_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG19_VAL_FIELD;
+#define HASH_DEBUG_DBG19_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG19_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG19_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG20_VAL_FIELD;
+#define HASH_DEBUG_DBG20_VAL_FIELD_MASK  0xffffffff
+#define HASH_DEBUG_DBG20_VAL_FIELD_WIDTH 32
+#define HASH_DEBUG_DBG20_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG_SEL_VAL_FIELD;
+#define HASH_DEBUG_DBG_SEL_VAL_FIELD_MASK  0x0000001f
+#define HASH_DEBUG_DBG_SEL_VAL_FIELD_WIDTH 5
+#define HASH_DEBUG_DBG_SEL_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_DEBUG_DBG_SEL_RESERVED0_FIELD;
+#define HASH_DEBUG_DBG_SEL_RESERVED0_FIELD_MASK  0xffffffe0
+#define HASH_DEBUG_DBG_SEL_RESERVED0_FIELD_WIDTH 27
+#define HASH_DEBUG_DBG_SEL_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec HASH_AGING_RAM_AGING_DATA_FIELD;
+#define HASH_AGING_RAM_AGING_DATA_FIELD_MASK  0xffffffff
+#define HASH_AGING_RAM_AGING_DATA_FIELD_WIDTH 32
+#define HASH_AGING_RAM_AGING_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_FIELD;
+#define HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_FIELD_MASK  0x00ffffff
+#define HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_FIELD_WIDTH 24
+#define HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CONTEXT_RAM_CONTEXT_47_24_RESERVED0_FIELD;
+#define HASH_CONTEXT_RAM_CONTEXT_47_24_RESERVED0_FIELD_MASK  0xff000000
+#define HASH_CONTEXT_RAM_CONTEXT_47_24_RESERVED0_FIELD_WIDTH 8
+#define HASH_CONTEXT_RAM_CONTEXT_47_24_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_FIELD;
+#define HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_FIELD_MASK  0x00ffffff
+#define HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_FIELD_WIDTH 24
+#define HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_CONTEXT_RAM_CONTEXT_23_0_RESERVED0_FIELD;
+#define HASH_CONTEXT_RAM_CONTEXT_23_0_RESERVED0_FIELD_MASK  0xff000000
+#define HASH_CONTEXT_RAM_CONTEXT_23_0_RESERVED0_FIELD_WIDTH 8
+#define HASH_CONTEXT_RAM_CONTEXT_23_0_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_FIELD;
+#define HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_FIELD_MASK  0xffffffff
+#define HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_FIELD_WIDTH 32
+#define HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_RAM_ENG_LOW_SKP_FIELD;
+#define HASH_RAM_ENG_LOW_SKP_FIELD_MASK  0x00000001
+#define HASH_RAM_ENG_LOW_SKP_FIELD_WIDTH 1
+#define HASH_RAM_ENG_LOW_SKP_FIELD_SHIFT 0
+
+extern const ru_field_rec HASH_RAM_ENG_LOW_CFG_FIELD;
+#define HASH_RAM_ENG_LOW_CFG_FIELD_MASK  0x0000000e
+#define HASH_RAM_ENG_LOW_CFG_FIELD_WIDTH 3
+#define HASH_RAM_ENG_LOW_CFG_FIELD_SHIFT 1
+
+extern const ru_field_rec HASH_RAM_ENG_LOW_KEY_11_0_FIELD;
+#define HASH_RAM_ENG_LOW_KEY_11_0_FIELD_MASK  0x0000fff0
+#define HASH_RAM_ENG_LOW_KEY_11_0_FIELD_WIDTH 12
+#define HASH_RAM_ENG_LOW_KEY_11_0_FIELD_SHIFT 4
+
+extern const ru_field_rec HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_FIELD;
+#define HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_FIELD_MASK  0xffff0000
+#define HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_FIELD_WIDTH 16
+#define HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_FIELD_SHIFT 16
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_THR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_THR_FIELD_MASK  0x0000000f
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_THR_FIELD_WIDTH 4
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_RESERVED0_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_RESERVED0_FIELD_MASK  0xfffffff0
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_RESERVED0_FIELD_WIDTH 28
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_EN_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_EN_FIELD_MASK  0x00000001
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_EN_FIELD_WIDTH 1
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED0_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED0_FIELD_MASK  0x0000000e
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED0_FIELD_WIDTH 3
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ID_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ID_FIELD_MASK  0x000003f0
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ID_FIELD_WIDTH 6
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ID_FIELD_SHIFT 4
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED1_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED1_FIELD_MASK  0x0000fc00
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED1_FIELD_WIDTH 6
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED1_FIELD_SHIFT 10
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ADDR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ADDR_FIELD_MASK  0x03ff0000
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ADDR_FIELD_WIDTH 10
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ADDR_FIELD_SHIFT 16
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED2_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED2_FIELD_MASK  0xfc000000
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED2_FIELD_WIDTH 6
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED2_FIELD_SHIFT 26
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_BA_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_BA_FIELD_MASK  0x00000fff
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_BA_FIELD_WIDTH 12
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_BA_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_BT_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_BT_FIELD_MASK  0x0000f000
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_BT_FIELD_WIDTH 4
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_BT_FIELD_SHIFT 12
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_OFST_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_OFST_FIELD_MASK  0x0fff0000
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_OFST_FIELD_WIDTH 12
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_OFST_FIELD_SHIFT 16
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_RESERVED0_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_RESERVED0_FIELD_MASK  0xf0000000
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_RESERVED0_FIELD_WIDTH 4
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK  0x00000001
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK  0x000000fe
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK  0x0000ff00
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK  0x00010000
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK  0x000e0000
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK  0x00700000
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK  0x00800000
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK  0xff000000
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_FIELD_MASK  0x7fffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_FIELD_WIDTH 31
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_VAL_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_VAL_FIELD_MASK  0x80000000
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_VAL_FIELD_WIDTH 1
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_VAL_FIELD_SHIFT 31
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_FIELD_MASK  0x7fffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_FIELD_WIDTH 31
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_VAL_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_VAL_FIELD_MASK  0x80000000
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_VAL_FIELD_WIDTH 1
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_VAL_FIELD_SHIFT 31
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_FIELD_MASK  0x7fffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_FIELD_WIDTH 31
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_VAL_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_VAL_FIELD_MASK  0x80000000
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_VAL_FIELD_WIDTH 1
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_VAL_FIELD_SHIFT 31
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_FIELD_MASK  0x7fffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_FIELD_WIDTH 31
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_VAL_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_VAL_FIELD_MASK  0x80000000
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_VAL_FIELD_WIDTH 1
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_VAL_FIELD_SHIFT 31
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_FIELD_MASK  0x7fffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_FIELD_WIDTH 31
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_VAL_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_VAL_FIELD_MASK  0x80000000
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_VAL_FIELD_WIDTH 1
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_VAL_FIELD_SHIFT 31
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_FIELD_MASK  0xffffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_FIELD_WIDTH 32
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_FIELD_MASK  0xffffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_FIELD_WIDTH 32
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_FIELD_MASK  0xffffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_FIELD_WIDTH 32
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_FIELD_MASK  0xffffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_FIELD_WIDTH 32
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_FIELD_MASK  0xffffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_FIELD_WIDTH 32
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_FIELD_MASK  0xffffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_FIELD_WIDTH 32
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_FIELD_MASK  0xffffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_FIELD_WIDTH 32
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_FIELD_MASK  0xffffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_FIELD_WIDTH 32
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_FIELD_MASK  0xffffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_FIELD_WIDTH 32
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_MASK  0x00000001
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_WIDTH 1
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_SHIFT 0
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_WRAP_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_WRAP_FIELD_MASK  0x00000002
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_WRAP_FIELD_WIDTH 1
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_WRAP_FIELD_SHIFT 1
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_MASK  0xfffffffc
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_WIDTH 30
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_DEBUG_DBG0_VAL_FIELD;
+#define BAC_IF_BACIF_BLOCK_BACIF_DEBUG_DBG0_VAL_FIELD_MASK  0xffffffff
+#define BAC_IF_BACIF_BLOCK_BACIF_DEBUG_DBG0_VAL_FIELD_WIDTH 32
+#define BAC_IF_BACIF_BLOCK_BACIF_DEBUG_DBG0_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_MEMORY_DATA_DATA_FIELD;
+#define CNPL_MEMORY_DATA_DATA_FIELD_MASK  0xffffffff
+#define CNPL_MEMORY_DATA_DATA_FIELD_WIDTH 32
+#define CNPL_MEMORY_DATA_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_BA_FIELD;
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_BA_FIELD_MASK  0x000007ff
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_BA_FIELD_WIDTH 11
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_BA_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CN0_BYTS_FIELD;
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CN0_BYTS_FIELD_MASK  0x00001800
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CN0_BYTS_FIELD_WIDTH 2
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CN0_BYTS_FIELD_SHIFT 11
+
+extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_DOUBLLE_FIELD;
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_DOUBLLE_FIELD_MASK  0x00002000
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_DOUBLLE_FIELD_WIDTH 1
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_DOUBLLE_FIELD_SHIFT 13
+
+extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_WRAP_FIELD;
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_WRAP_FIELD_MASK  0x00004000
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_WRAP_FIELD_WIDTH 1
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_WRAP_FIELD_SHIFT 14
+
+extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CLR_FIELD;
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CLR_FIELD_MASK  0x00008000
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CLR_FIELD_WIDTH 1
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CLR_FIELD_SHIFT 15
+
+extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_RESERVED0_FIELD;
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_RESERVED0_FIELD_MASK  0xffff0000
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_RESERVED0_FIELD_WIDTH 16
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_BK_BA_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_BK_BA_FIELD_MASK  0x000007ff
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_BK_BA_FIELD_WIDTH 11
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_BK_BA_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_PA_BA_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_PA_BA_FIELD_MASK  0x003ff800
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_PA_BA_FIELD_WIDTH 11
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_PA_BA_FIELD_SHIFT 11
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_DOUBLLE_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_DOUBLLE_FIELD_MASK  0x00400000
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_DOUBLLE_FIELD_WIDTH 1
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_DOUBLLE_FIELD_SHIFT 22
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_FC_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_FC_FIELD_MASK  0x00800000
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_FC_FIELD_WIDTH 1
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_FC_FIELD_SHIFT 23
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_N_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_N_FIELD_MASK  0xff000000
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_N_FIELD_WIDTH 8
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_N_FIELD_SHIFT 24
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_ST_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_ST_FIELD_MASK  0x000000ff
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_ST_FIELD_WIDTH 8
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_ST_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_END_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_END_FIELD_MASK  0x0000ff00
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_END_FIELD_WIDTH 8
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_END_FIELD_SHIFT 8
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_RESERVED0_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_RESERVED0_FIELD_MASK  0xffff0000
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_RESERVED0_FIELD_WIDTH 16
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_VEC_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_VEC_FIELD_MASK  0xffffffff
+#define CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_VEC_FIELD_WIDTH 32
+#define CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_VEC_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PER_UP_EN_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PER_UP_EN_FIELD_MASK  0x00000001
+#define CNPL_POLICERS_CONFIGURATIONS_PER_UP_EN_FIELD_WIDTH 1
+#define CNPL_POLICERS_CONFIGURATIONS_PER_UP_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PER_UP_MTU_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PER_UP_MTU_FIELD_MASK  0x00007ffe
+#define CNPL_POLICERS_CONFIGURATIONS_PER_UP_MTU_FIELD_WIDTH 14
+#define CNPL_POLICERS_CONFIGURATIONS_PER_UP_MTU_FIELD_SHIFT 1
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PER_UP_RESERVED0_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PER_UP_RESERVED0_FIELD_MASK  0xffff8000
+#define CNPL_POLICERS_CONFIGURATIONS_PER_UP_RESERVED0_FIELD_WIDTH 17
+#define CNPL_POLICERS_CONFIGURATIONS_PER_UP_RESERVED0_FIELD_SHIFT 15
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_SIZE_PROF_PRF0_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_SIZE_PROF_PRF0_FIELD_MASK  0x0000ffff
+#define CNPL_POLICERS_CONFIGURATIONS_PL_SIZE_PROF_PRF0_FIELD_WIDTH 16
+#define CNPL_POLICERS_CONFIGURATIONS_PL_SIZE_PROF_PRF0_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_SIZE_PROF_PRF1_FIELD;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_SIZE_PROF_PRF1_FIELD_MASK  0xffff0000
+#define CNPL_POLICERS_CONFIGURATIONS_PL_SIZE_PROF_PRF1_FIELD_WIDTH 16
+#define CNPL_POLICERS_CONFIGURATIONS_PL_SIZE_PROF_PRF1_FIELD_SHIFT 16
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_ORDR_NXTLVL_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_ORDR_NXTLVL_FIELD_MASK  0x0000001f
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_ORDR_NXTLVL_FIELD_WIDTH 5
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_ORDR_NXTLVL_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_ORDR_RESERVED0_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_ORDR_RESERVED0_FIELD_MASK  0xffffffe0
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_ORDR_RESERVED0_FIELD_WIDTH 27
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_ORDR_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_RSRV_THR_THR_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_RSRV_THR_THR_FIELD_MASK  0x0003ffff
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_RSRV_THR_THR_FIELD_WIDTH 18
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_RSRV_THR_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_RSRV_THR_RESERVED0_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_RSRV_THR_RESERVED0_FIELD_MASK  0xfffc0000
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_RSRV_THR_RESERVED0_FIELD_WIDTH 14
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_RSRV_THR_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HIPRI_THR_THR_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HIPRI_THR_THR_FIELD_MASK  0x0003ffff
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HIPRI_THR_THR_FIELD_WIDTH 18
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HIPRI_THR_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HIPRI_THR_RESERVED0_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HIPRI_THR_RESERVED0_FIELD_MASK  0xfffc0000
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HIPRI_THR_RESERVED0_FIELD_WIDTH 14
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HIPRI_THR_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_MAX_THR_THR_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_MAX_THR_THR_FIELD_MASK  0x0003ffff
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_MAX_THR_THR_FIELD_WIDTH 18
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_MAX_THR_THR_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_MAX_THR_RESERVED0_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_MAX_THR_RESERVED0_FIELD_MASK  0xfffc0000
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_MAX_THR_RESERVED0_FIELD_WIDTH 14
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_MAX_THR_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR0_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR0_FIELD_MASK  0x0000001f
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR0_FIELD_WIDTH 5
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR0_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED0_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED0_FIELD_MASK  0x000000e0
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED0_FIELD_WIDTH 3
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR1_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR1_FIELD_MASK  0x00001f00
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR1_FIELD_WIDTH 5
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR1_FIELD_SHIFT 8
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED1_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED1_FIELD_MASK  0x0000e000
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED1_FIELD_WIDTH 3
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR2_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR2_FIELD_MASK  0x001f0000
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR2_FIELD_WIDTH 5
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_CTR2_FIELD_SHIFT 16
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED2_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED2_FIELD_MASK  0xffe00000
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED2_FIELD_WIDTH 11
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_RESERVED2_FIELD_SHIFT 21
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_VAL_VAL_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_VAL_VAL_FIELD_MASK  0x0003ffff
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_VAL_VAL_FIELD_WIDTH 18
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_VAL_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_VAL_RESERVED0_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_VAL_RESERVED0_FIELD_MASK  0xfffc0000
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_VAL_RESERVED0_FIELD_WIDTH 14
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_VAL_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_CTRS_VAL_VAL_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_CTRS_VAL_VAL_FIELD_MASK  0x0003ffff
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_CTRS_VAL_VAL_FIELD_WIDTH 18
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_CTRS_VAL_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_CTRS_VAL_RESERVED0_FIELD;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_CTRS_VAL_RESERVED0_FIELD_MASK  0xfffc0000
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_CTRS_VAL_RESERVED0_FIELD_WIDTH 14
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_CTRS_VAL_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec CNPL_SW_IF_SW_CMD_VAL_FIELD;
+#define CNPL_SW_IF_SW_CMD_VAL_FIELD_MASK  0xffffffff
+#define CNPL_SW_IF_SW_CMD_VAL_FIELD_WIDTH 32
+#define CNPL_SW_IF_SW_CMD_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_SW_IF_SW_STAT_CN_RD_ST_FIELD;
+#define CNPL_SW_IF_SW_STAT_CN_RD_ST_FIELD_MASK  0x00000001
+#define CNPL_SW_IF_SW_STAT_CN_RD_ST_FIELD_WIDTH 1
+#define CNPL_SW_IF_SW_STAT_CN_RD_ST_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_SW_IF_SW_STAT_PL_PLC_ST_FIELD;
+#define CNPL_SW_IF_SW_STAT_PL_PLC_ST_FIELD_MASK  0x00000002
+#define CNPL_SW_IF_SW_STAT_PL_PLC_ST_FIELD_WIDTH 1
+#define CNPL_SW_IF_SW_STAT_PL_PLC_ST_FIELD_SHIFT 1
+
+extern const ru_field_rec CNPL_SW_IF_SW_STAT_PL_RD_ST_FIELD;
+#define CNPL_SW_IF_SW_STAT_PL_RD_ST_FIELD_MASK  0x00000004
+#define CNPL_SW_IF_SW_STAT_PL_RD_ST_FIELD_WIDTH 1
+#define CNPL_SW_IF_SW_STAT_PL_RD_ST_FIELD_SHIFT 2
+
+extern const ru_field_rec CNPL_SW_IF_SW_STAT_RESERVED0_FIELD;
+#define CNPL_SW_IF_SW_STAT_RESERVED0_FIELD_MASK  0xfffffff8
+#define CNPL_SW_IF_SW_STAT_RESERVED0_FIELD_WIDTH 29
+#define CNPL_SW_IF_SW_STAT_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec CNPL_SW_IF_SW_PL_RSLT_RESERVED0_FIELD;
+#define CNPL_SW_IF_SW_PL_RSLT_RESERVED0_FIELD_MASK  0x3fffffff
+#define CNPL_SW_IF_SW_PL_RSLT_RESERVED0_FIELD_WIDTH 30
+#define CNPL_SW_IF_SW_PL_RSLT_RESERVED0_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_SW_IF_SW_PL_RSLT_COL_FIELD;
+#define CNPL_SW_IF_SW_PL_RSLT_COL_FIELD_MASK  0xc0000000
+#define CNPL_SW_IF_SW_PL_RSLT_COL_FIELD_WIDTH 2
+#define CNPL_SW_IF_SW_PL_RSLT_COL_FIELD_SHIFT 30
+
+extern const ru_field_rec CNPL_SW_IF_SW_PL_RD_RD_FIELD;
+#define CNPL_SW_IF_SW_PL_RD_RD_FIELD_MASK  0xffffffff
+#define CNPL_SW_IF_SW_PL_RD_RD_FIELD_WIDTH 32
+#define CNPL_SW_IF_SW_PL_RD_RD_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_SW_IF_SW_CNT_RD_RD_FIELD;
+#define CNPL_SW_IF_SW_CNT_RD_RD_FIELD_MASK  0xffffffff
+#define CNPL_SW_IF_SW_CNT_RD_RD_FIELD_WIDTH 32
+#define CNPL_SW_IF_SW_CNT_RD_RD_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_MISC_ARB_PRM_SW_PRIO_FIELD;
+#define CNPL_MISC_ARB_PRM_SW_PRIO_FIELD_MASK  0x00000003
+#define CNPL_MISC_ARB_PRM_SW_PRIO_FIELD_WIDTH 2
+#define CNPL_MISC_ARB_PRM_SW_PRIO_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_MISC_ARB_PRM_RESERVED0_FIELD;
+#define CNPL_MISC_ARB_PRM_RESERVED0_FIELD_MASK  0xfffffffc
+#define CNPL_MISC_ARB_PRM_RESERVED0_FIELD_WIDTH 30
+#define CNPL_MISC_ARB_PRM_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec CNPL_MISC_COL_AWR_EN_EN_FIELD;
+#define CNPL_MISC_COL_AWR_EN_EN_FIELD_MASK  0x00000001
+#define CNPL_MISC_COL_AWR_EN_EN_FIELD_WIDTH 1
+#define CNPL_MISC_COL_AWR_EN_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_MISC_COL_AWR_EN_RESERVED0_FIELD;
+#define CNPL_MISC_COL_AWR_EN_RESERVED0_FIELD_MASK  0xfffffffe
+#define CNPL_MISC_COL_AWR_EN_RESERVED0_FIELD_WIDTH 31
+#define CNPL_MISC_COL_AWR_EN_RESERVED0_FIELD_SHIFT 1
+
+extern const ru_field_rec CNPL_PM_COUNTERS_ENG_CMDS_VAL_FIELD;
+#define CNPL_PM_COUNTERS_ENG_CMDS_VAL_FIELD_MASK  0xffffffff
+#define CNPL_PM_COUNTERS_ENG_CMDS_VAL_FIELD_WIDTH 32
+#define CNPL_PM_COUNTERS_ENG_CMDS_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_PM_COUNTERS_CMD_WAIT_VAL_FIELD;
+#define CNPL_PM_COUNTERS_CMD_WAIT_VAL_FIELD_MASK  0xffffffff
+#define CNPL_PM_COUNTERS_CMD_WAIT_VAL_FIELD_WIDTH 32
+#define CNPL_PM_COUNTERS_CMD_WAIT_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_PM_COUNTERS_TOT_CYC_VAL_FIELD;
+#define CNPL_PM_COUNTERS_TOT_CYC_VAL_FIELD_MASK  0xffffffff
+#define CNPL_PM_COUNTERS_TOT_CYC_VAL_FIELD_WIDTH 32
+#define CNPL_PM_COUNTERS_TOT_CYC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_PM_COUNTERS_GNT_CYC_VAL_FIELD;
+#define CNPL_PM_COUNTERS_GNT_CYC_VAL_FIELD_MASK  0xffffffff
+#define CNPL_PM_COUNTERS_GNT_CYC_VAL_FIELD_WIDTH 32
+#define CNPL_PM_COUNTERS_GNT_CYC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_PM_COUNTERS_ARB_CYC_VAL_FIELD;
+#define CNPL_PM_COUNTERS_ARB_CYC_VAL_FIELD_MASK  0xffffffff
+#define CNPL_PM_COUNTERS_ARB_CYC_VAL_FIELD_WIDTH 32
+#define CNPL_PM_COUNTERS_ARB_CYC_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_PM_COUNTERS_PL_UP_ERR_VAL_FIELD;
+#define CNPL_PM_COUNTERS_PL_UP_ERR_VAL_FIELD_MASK  0xffffffff
+#define CNPL_PM_COUNTERS_PL_UP_ERR_VAL_FIELD_WIDTH 32
+#define CNPL_PM_COUNTERS_PL_UP_ERR_VAL_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD;
+#define CNPL_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_MASK  0x00000001
+#define CNPL_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_WIDTH 1
+#define CNPL_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_PM_COUNTERS_GEN_CFG_WRAP_FIELD;
+#define CNPL_PM_COUNTERS_GEN_CFG_WRAP_FIELD_MASK  0x00000002
+#define CNPL_PM_COUNTERS_GEN_CFG_WRAP_FIELD_WIDTH 1
+#define CNPL_PM_COUNTERS_GEN_CFG_WRAP_FIELD_SHIFT 1
+
+extern const ru_field_rec CNPL_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD;
+#define CNPL_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_MASK  0xfffffffc
+#define CNPL_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_WIDTH 30
+#define CNPL_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec CNPL_DEBUG_DBGSEL_VS_FIELD;
+#define CNPL_DEBUG_DBGSEL_VS_FIELD_MASK  0x0000007f
+#define CNPL_DEBUG_DBGSEL_VS_FIELD_WIDTH 7
+#define CNPL_DEBUG_DBGSEL_VS_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_DEBUG_DBGSEL_RESERVED0_FIELD;
+#define CNPL_DEBUG_DBGSEL_RESERVED0_FIELD_MASK  0xffffff80
+#define CNPL_DEBUG_DBGSEL_RESERVED0_FIELD_WIDTH 25
+#define CNPL_DEBUG_DBGSEL_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec CNPL_DEBUG_DBGBUS_VB_FIELD;
+#define CNPL_DEBUG_DBGBUS_VB_FIELD_MASK  0x001fffff
+#define CNPL_DEBUG_DBGBUS_VB_FIELD_WIDTH 21
+#define CNPL_DEBUG_DBGBUS_VB_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_DEBUG_DBGBUS_RESERVED0_FIELD;
+#define CNPL_DEBUG_DBGBUS_RESERVED0_FIELD_MASK  0xffe00000
+#define CNPL_DEBUG_DBGBUS_RESERVED0_FIELD_WIDTH 11
+#define CNPL_DEBUG_DBGBUS_RESERVED0_FIELD_SHIFT 21
+
+extern const ru_field_rec CNPL_DEBUG_REQ_VEC_REQ_FIELD;
+#define CNPL_DEBUG_REQ_VEC_REQ_FIELD_MASK  0x0000007f
+#define CNPL_DEBUG_REQ_VEC_REQ_FIELD_WIDTH 7
+#define CNPL_DEBUG_REQ_VEC_REQ_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_DEBUG_REQ_VEC_RESERVED0_FIELD;
+#define CNPL_DEBUG_REQ_VEC_RESERVED0_FIELD_MASK  0xffffff80
+#define CNPL_DEBUG_REQ_VEC_RESERVED0_FIELD_WIDTH 25
+#define CNPL_DEBUG_REQ_VEC_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec CNPL_DEBUG_POL_UP_ST_ITR_NUM_FIELD;
+#define CNPL_DEBUG_POL_UP_ST_ITR_NUM_FIELD_MASK  0x000000ff
+#define CNPL_DEBUG_POL_UP_ST_ITR_NUM_FIELD_WIDTH 8
+#define CNPL_DEBUG_POL_UP_ST_ITR_NUM_FIELD_SHIFT 0
+
+extern const ru_field_rec CNPL_DEBUG_POL_UP_ST_POL_NUM_FIELD;
+#define CNPL_DEBUG_POL_UP_ST_POL_NUM_FIELD_MASK  0x0000ff00
+#define CNPL_DEBUG_POL_UP_ST_POL_NUM_FIELD_WIDTH 8
+#define CNPL_DEBUG_POL_UP_ST_POL_NUM_FIELD_SHIFT 8
+
+extern const ru_field_rec CNPL_DEBUG_POL_UP_ST_RESERVED0_FIELD;
+#define CNPL_DEBUG_POL_UP_ST_RESERVED0_FIELD_MASK  0xffff0000
+#define CNPL_DEBUG_POL_UP_ST_RESERVED0_FIELD_WIDTH 16
+#define CNPL_DEBUG_POL_UP_ST_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_ADD_CMD_DDR_MISS_FIELD;
+#define NATC_ENG_COMMAND_STATUS_ADD_CMD_DDR_MISS_FIELD_MASK  0x80000000
+#define NATC_ENG_COMMAND_STATUS_ADD_CMD_DDR_MISS_FIELD_WIDTH 1
+#define NATC_ENG_COMMAND_STATUS_ADD_CMD_DDR_MISS_FIELD_SHIFT 31
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_ADD_CMD_DDR_BIN_FIELD;
+#define NATC_ENG_COMMAND_STATUS_ADD_CMD_DDR_BIN_FIELD_MASK  0x70000000
+#define NATC_ENG_COMMAND_STATUS_ADD_CMD_DDR_BIN_FIELD_WIDTH 3
+#define NATC_ENG_COMMAND_STATUS_ADD_CMD_DDR_BIN_FIELD_SHIFT 28
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_DEL_CMD_DDR_BIN_FIELD;
+#define NATC_ENG_COMMAND_STATUS_DEL_CMD_DDR_BIN_FIELD_MASK  0x0ff00000
+#define NATC_ENG_COMMAND_STATUS_DEL_CMD_DDR_BIN_FIELD_WIDTH 8
+#define NATC_ENG_COMMAND_STATUS_DEL_CMD_DDR_BIN_FIELD_SHIFT 20
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_RESERVED0_FIELD;
+#define NATC_ENG_COMMAND_STATUS_RESERVED0_FIELD_MASK  0x00080000
+#define NATC_ENG_COMMAND_STATUS_RESERVED0_FIELD_WIDTH 1
+#define NATC_ENG_COMMAND_STATUS_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_ADD_CMD_MODE_FIELD;
+#define NATC_ENG_COMMAND_STATUS_ADD_CMD_MODE_FIELD_MASK  0x00040000
+#define NATC_ENG_COMMAND_STATUS_ADD_CMD_MODE_FIELD_WIDTH 1
+#define NATC_ENG_COMMAND_STATUS_ADD_CMD_MODE_FIELD_SHIFT 18
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_DEL_CMD_MODE_FIELD;
+#define NATC_ENG_COMMAND_STATUS_DEL_CMD_MODE_FIELD_MASK  0x00020000
+#define NATC_ENG_COMMAND_STATUS_DEL_CMD_MODE_FIELD_WIDTH 1
+#define NATC_ENG_COMMAND_STATUS_DEL_CMD_MODE_FIELD_SHIFT 17
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_CACHE_FLUSH_FIELD;
+#define NATC_ENG_COMMAND_STATUS_CACHE_FLUSH_FIELD_MASK  0x00010000
+#define NATC_ENG_COMMAND_STATUS_CACHE_FLUSH_FIELD_WIDTH 1
+#define NATC_ENG_COMMAND_STATUS_CACHE_FLUSH_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_DECR_COUNT_FIELD;
+#define NATC_ENG_COMMAND_STATUS_DECR_COUNT_FIELD_MASK  0x00008000
+#define NATC_ENG_COMMAND_STATUS_DECR_COUNT_FIELD_WIDTH 1
+#define NATC_ENG_COMMAND_STATUS_DECR_COUNT_FIELD_SHIFT 15
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_NAT_TBL_FIELD;
+#define NATC_ENG_COMMAND_STATUS_NAT_TBL_FIELD_MASK  0x00007000
+#define NATC_ENG_COMMAND_STATUS_NAT_TBL_FIELD_WIDTH 3
+#define NATC_ENG_COMMAND_STATUS_NAT_TBL_FIELD_SHIFT 12
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_MULTIHASH_COUNT_FIELD;
+#define NATC_ENG_COMMAND_STATUS_MULTIHASH_COUNT_FIELD_MASK  0x00000f00
+#define NATC_ENG_COMMAND_STATUS_MULTIHASH_COUNT_FIELD_WIDTH 4
+#define NATC_ENG_COMMAND_STATUS_MULTIHASH_COUNT_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_CACHE_HIT_FIELD;
+#define NATC_ENG_COMMAND_STATUS_CACHE_HIT_FIELD_MASK  0x00000080
+#define NATC_ENG_COMMAND_STATUS_CACHE_HIT_FIELD_WIDTH 1
+#define NATC_ENG_COMMAND_STATUS_CACHE_HIT_FIELD_SHIFT 7
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_MISS_FIELD;
+#define NATC_ENG_COMMAND_STATUS_MISS_FIELD_MASK  0x00000040
+#define NATC_ENG_COMMAND_STATUS_MISS_FIELD_WIDTH 1
+#define NATC_ENG_COMMAND_STATUS_MISS_FIELD_SHIFT 6
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_ERROR_FIELD;
+#define NATC_ENG_COMMAND_STATUS_ERROR_FIELD_MASK  0x00000020
+#define NATC_ENG_COMMAND_STATUS_ERROR_FIELD_WIDTH 1
+#define NATC_ENG_COMMAND_STATUS_ERROR_FIELD_SHIFT 5
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_BUSY_FIELD;
+#define NATC_ENG_COMMAND_STATUS_BUSY_FIELD_MASK  0x00000010
+#define NATC_ENG_COMMAND_STATUS_BUSY_FIELD_WIDTH 1
+#define NATC_ENG_COMMAND_STATUS_BUSY_FIELD_SHIFT 4
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_UNUSED0_FIELD;
+#define NATC_ENG_COMMAND_STATUS_UNUSED0_FIELD_MASK  0x00000008
+#define NATC_ENG_COMMAND_STATUS_UNUSED0_FIELD_WIDTH 1
+#define NATC_ENG_COMMAND_STATUS_UNUSED0_FIELD_SHIFT 3
+
+extern const ru_field_rec NATC_ENG_COMMAND_STATUS_COMMAND_FIELD;
+#define NATC_ENG_COMMAND_STATUS_COMMAND_FIELD_MASK  0x00000007
+#define NATC_ENG_COMMAND_STATUS_COMMAND_FIELD_WIDTH 3
+#define NATC_ENG_COMMAND_STATUS_COMMAND_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_ENG_HASH_HASH_FIELD;
+#define NATC_ENG_HASH_HASH_FIELD_MASK  0xffffffff
+#define NATC_ENG_HASH_HASH_FIELD_WIDTH 32
+#define NATC_ENG_HASH_HASH_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_ENG_HIT_COUNT_HIT_COUNT_FIELD;
+#define NATC_ENG_HIT_COUNT_HIT_COUNT_FIELD_MASK  0xffffffff
+#define NATC_ENG_HIT_COUNT_HIT_COUNT_FIELD_WIDTH 32
+#define NATC_ENG_HIT_COUNT_HIT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_ENG_BYTE_COUNT_BYTE_COUNT_FIELD;
+#define NATC_ENG_BYTE_COUNT_BYTE_COUNT_FIELD_MASK  0xffffffff
+#define NATC_ENG_BYTE_COUNT_BYTE_COUNT_FIELD_WIDTH 32
+#define NATC_ENG_BYTE_COUNT_BYTE_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_ENG_PKT_LEN_UNUSED_FIELD;
+#define NATC_ENG_PKT_LEN_UNUSED_FIELD_MASK  0xffff0000
+#define NATC_ENG_PKT_LEN_UNUSED_FIELD_WIDTH 16
+#define NATC_ENG_PKT_LEN_UNUSED_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_ENG_PKT_LEN_PKT_LEN_FIELD;
+#define NATC_ENG_PKT_LEN_PKT_LEN_FIELD_MASK  0x0000ffff
+#define NATC_ENG_PKT_LEN_PKT_LEN_FIELD_WIDTH 16
+#define NATC_ENG_PKT_LEN_PKT_LEN_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_ENG_KEY_RESULT_NAT_KEY_RESULT_FIELD;
+#define NATC_ENG_KEY_RESULT_NAT_KEY_RESULT_FIELD_MASK  0xffffffff
+#define NATC_ENG_KEY_RESULT_NAT_KEY_RESULT_FIELD_WIDTH 32
+#define NATC_ENG_KEY_RESULT_NAT_KEY_RESULT_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_CTRS_CACHE_HIT_COUNT_CACHE_HIT_COUNT_FIELD;
+#define NATC_CTRS_CACHE_HIT_COUNT_CACHE_HIT_COUNT_FIELD_MASK  0xffffffff
+#define NATC_CTRS_CACHE_HIT_COUNT_CACHE_HIT_COUNT_FIELD_WIDTH 32
+#define NATC_CTRS_CACHE_HIT_COUNT_CACHE_HIT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_CTRS_CACHE_MISS_COUNT_CACHE_MISS_COUNT_FIELD;
+#define NATC_CTRS_CACHE_MISS_COUNT_CACHE_MISS_COUNT_FIELD_MASK  0xffffffff
+#define NATC_CTRS_CACHE_MISS_COUNT_CACHE_MISS_COUNT_FIELD_WIDTH 32
+#define NATC_CTRS_CACHE_MISS_COUNT_CACHE_MISS_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_CTRS_DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_FIELD;
+#define NATC_CTRS_DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_FIELD_MASK  0xffffffff
+#define NATC_CTRS_DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_FIELD_WIDTH 32
+#define NATC_CTRS_DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_CTRS_DDR_EVICT_COUNT_DDR_EVICT_COUNT_FIELD;
+#define NATC_CTRS_DDR_EVICT_COUNT_DDR_EVICT_COUNT_FIELD_MASK  0xffffffff
+#define NATC_CTRS_DDR_EVICT_COUNT_DDR_EVICT_COUNT_FIELD_WIDTH 32
+#define NATC_CTRS_DDR_EVICT_COUNT_DDR_EVICT_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_CTRS_DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_FIELD;
+#define NATC_CTRS_DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_FIELD_MASK  0xffffffff
+#define NATC_CTRS_DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_FIELD_WIDTH 32
+#define NATC_CTRS_DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_DDR_CFG_SIZE_RESERVED0_FIELD;
+#define NATC_DDR_CFG_SIZE_RESERVED0_FIELD_MASK  0xff000000
+#define NATC_DDR_CFG_SIZE_RESERVED0_FIELD_WIDTH 8
+#define NATC_DDR_CFG_SIZE_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec NATC_DDR_CFG_SIZE_DDR_SIZE_TBL7_FIELD;
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL7_FIELD_MASK  0x00e00000
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL7_FIELD_WIDTH 3
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL7_FIELD_SHIFT 21
+
+extern const ru_field_rec NATC_DDR_CFG_SIZE_DDR_SIZE_TBL6_FIELD;
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL6_FIELD_MASK  0x001c0000
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL6_FIELD_WIDTH 3
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL6_FIELD_SHIFT 18
+
+extern const ru_field_rec NATC_DDR_CFG_SIZE_DDR_SIZE_TBL5_FIELD;
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL5_FIELD_MASK  0x00038000
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL5_FIELD_WIDTH 3
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL5_FIELD_SHIFT 15
+
+extern const ru_field_rec NATC_DDR_CFG_SIZE_DDR_SIZE_TBL4_FIELD;
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL4_FIELD_MASK  0x00007000
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL4_FIELD_WIDTH 3
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL4_FIELD_SHIFT 12
+
+extern const ru_field_rec NATC_DDR_CFG_SIZE_DDR_SIZE_TBL3_FIELD;
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL3_FIELD_MASK  0x00000e00
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL3_FIELD_WIDTH 3
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL3_FIELD_SHIFT 9
+
+extern const ru_field_rec NATC_DDR_CFG_SIZE_DDR_SIZE_TBL2_FIELD;
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL2_FIELD_MASK  0x000001c0
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL2_FIELD_WIDTH 3
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL2_FIELD_SHIFT 6
+
+extern const ru_field_rec NATC_DDR_CFG_SIZE_DDR_SIZE_TBL1_FIELD;
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL1_FIELD_MASK  0x00000038
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL1_FIELD_WIDTH 3
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL1_FIELD_SHIFT 3
+
+extern const ru_field_rec NATC_DDR_CFG_SIZE_DDR_SIZE_TBL0_FIELD;
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL0_FIELD_MASK  0x00000007
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL0_FIELD_WIDTH 3
+#define NATC_DDR_CFG_SIZE_DDR_SIZE_TBL0_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_FIELD;
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_FIELD_MASK  0xff000000
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_FIELD_WIDTH 8
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_FIELD_SHIFT 24
+
+extern const ru_field_rec NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_FIELD;
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_FIELD_MASK  0x00ff0000
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_FIELD_WIDTH 8
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_FIELD;
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_FIELD_MASK  0x0000ff00
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_FIELD_WIDTH 8
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_FIELD;
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_FIELD_MASK  0x000000ff
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_FIELD_WIDTH 8
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_FIELD;
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_FIELD_MASK  0xff000000
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_FIELD_WIDTH 8
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_FIELD_SHIFT 24
+
+extern const ru_field_rec NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_FIELD;
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_FIELD_MASK  0x00ff0000
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_FIELD_WIDTH 8
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_FIELD;
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_FIELD_MASK  0x0000ff00
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_FIELD_WIDTH 8
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_FIELD;
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_FIELD_MASK  0x000000ff
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_FIELD_WIDTH 8
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_DDR_CFG_TOTAL_LEN_RESERVED0_FIELD;
+#define NATC_DDR_CFG_TOTAL_LEN_RESERVED0_FIELD_MASK  0xff000000
+#define NATC_DDR_CFG_TOTAL_LEN_RESERVED0_FIELD_WIDTH 8
+#define NATC_DDR_CFG_TOTAL_LEN_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL7_FIELD;
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL7_FIELD_MASK  0x00e00000
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL7_FIELD_WIDTH 3
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL7_FIELD_SHIFT 21
+
+extern const ru_field_rec NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL6_FIELD;
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL6_FIELD_MASK  0x001c0000
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL6_FIELD_WIDTH 3
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL6_FIELD_SHIFT 18
+
+extern const ru_field_rec NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL5_FIELD;
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL5_FIELD_MASK  0x00038000
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL5_FIELD_WIDTH 3
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL5_FIELD_SHIFT 15
+
+extern const ru_field_rec NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL4_FIELD;
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL4_FIELD_MASK  0x00007000
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL4_FIELD_WIDTH 3
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL4_FIELD_SHIFT 12
+
+extern const ru_field_rec NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL3_FIELD;
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL3_FIELD_MASK  0x00000e00
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL3_FIELD_WIDTH 3
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL3_FIELD_SHIFT 9
+
+extern const ru_field_rec NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL2_FIELD;
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL2_FIELD_MASK  0x000001c0
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL2_FIELD_WIDTH 3
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL2_FIELD_SHIFT 6
+
+extern const ru_field_rec NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL1_FIELD;
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL1_FIELD_MASK  0x00000038
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL1_FIELD_WIDTH 3
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL1_FIELD_SHIFT 3
+
+extern const ru_field_rec NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL0_FIELD;
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL0_FIELD_MASK  0x00000007
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL0_FIELD_WIDTH 3
+#define NATC_DDR_CFG_TOTAL_LEN_TOTAL_LEN_TBL0_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_DDR_CFG_SM_STATUS_RESERVED0_FIELD;
+#define NATC_DDR_CFG_SM_STATUS_RESERVED0_FIELD_MASK  0xfc000000
+#define NATC_DDR_CFG_SM_STATUS_RESERVED0_FIELD_WIDTH 6
+#define NATC_DDR_CFG_SM_STATUS_RESERVED0_FIELD_SHIFT 26
+
+extern const ru_field_rec NATC_DDR_CFG_SM_STATUS_DEBUG_SEL_FIELD;
+#define NATC_DDR_CFG_SM_STATUS_DEBUG_SEL_FIELD_MASK  0x03000000
+#define NATC_DDR_CFG_SM_STATUS_DEBUG_SEL_FIELD_WIDTH 2
+#define NATC_DDR_CFG_SM_STATUS_DEBUG_SEL_FIELD_SHIFT 24
+
+extern const ru_field_rec NATC_DDR_CFG_SM_STATUS_APB_STATE_FIELD;
+#define NATC_DDR_CFG_SM_STATUS_APB_STATE_FIELD_MASK  0x00c00000
+#define NATC_DDR_CFG_SM_STATUS_APB_STATE_FIELD_WIDTH 2
+#define NATC_DDR_CFG_SM_STATUS_APB_STATE_FIELD_SHIFT 22
+
+extern const ru_field_rec NATC_DDR_CFG_SM_STATUS_DDR_REQ_STATE_FIELD;
+#define NATC_DDR_CFG_SM_STATUS_DDR_REQ_STATE_FIELD_MASK  0x00300000
+#define NATC_DDR_CFG_SM_STATUS_DDR_REQ_STATE_FIELD_WIDTH 2
+#define NATC_DDR_CFG_SM_STATUS_DDR_REQ_STATE_FIELD_SHIFT 20
+
+extern const ru_field_rec NATC_DDR_CFG_SM_STATUS_DDR_REP_STATE_FIELD;
+#define NATC_DDR_CFG_SM_STATUS_DDR_REP_STATE_FIELD_MASK  0x000e0000
+#define NATC_DDR_CFG_SM_STATUS_DDR_REP_STATE_FIELD_WIDTH 3
+#define NATC_DDR_CFG_SM_STATUS_DDR_REP_STATE_FIELD_SHIFT 17
+
+extern const ru_field_rec NATC_DDR_CFG_SM_STATUS_RUNNER_CMD_STATE_FIELD;
+#define NATC_DDR_CFG_SM_STATUS_RUNNER_CMD_STATE_FIELD_MASK  0x00010000
+#define NATC_DDR_CFG_SM_STATUS_RUNNER_CMD_STATE_FIELD_WIDTH 1
+#define NATC_DDR_CFG_SM_STATUS_RUNNER_CMD_STATE_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_DDR_CFG_SM_STATUS_WB_STATE_FIELD;
+#define NATC_DDR_CFG_SM_STATUS_WB_STATE_FIELD_MASK  0x00008000
+#define NATC_DDR_CFG_SM_STATUS_WB_STATE_FIELD_WIDTH 1
+#define NATC_DDR_CFG_SM_STATUS_WB_STATE_FIELD_SHIFT 15
+
+extern const ru_field_rec NATC_DDR_CFG_SM_STATUS_NAT_STATE_FIELD;
+#define NATC_DDR_CFG_SM_STATUS_NAT_STATE_FIELD_MASK  0x00007fff
+#define NATC_DDR_CFG_SM_STATUS_NAT_STATE_FIELD_WIDTH 15
+#define NATC_DDR_CFG_SM_STATUS_NAT_STATE_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_CONTROL_STATUS_DDR_ENABLE_FIELD;
+#define NATC_CONTROL_STATUS_DDR_ENABLE_FIELD_MASK  0x80000000
+#define NATC_CONTROL_STATUS_DDR_ENABLE_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_DDR_ENABLE_FIELD_SHIFT 31
+
+extern const ru_field_rec NATC_CONTROL_STATUS_NATC_ADD_COMMAND_SPEEDUP_MODE_FIELD;
+#define NATC_CONTROL_STATUS_NATC_ADD_COMMAND_SPEEDUP_MODE_FIELD_MASK  0x40000000
+#define NATC_CONTROL_STATUS_NATC_ADD_COMMAND_SPEEDUP_MODE_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_NATC_ADD_COMMAND_SPEEDUP_MODE_FIELD_SHIFT 30
+
+extern const ru_field_rec NATC_CONTROL_STATUS_UNUSED0_FIELD;
+#define NATC_CONTROL_STATUS_UNUSED0_FIELD_MASK  0x30000000
+#define NATC_CONTROL_STATUS_UNUSED0_FIELD_WIDTH 2
+#define NATC_CONTROL_STATUS_UNUSED0_FIELD_SHIFT 28
+
+extern const ru_field_rec NATC_CONTROL_STATUS_DDR_64BIT_IN_128BIT_SWAP_CONTROL_FIELD;
+#define NATC_CONTROL_STATUS_DDR_64BIT_IN_128BIT_SWAP_CONTROL_FIELD_MASK  0x08000000
+#define NATC_CONTROL_STATUS_DDR_64BIT_IN_128BIT_SWAP_CONTROL_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_DDR_64BIT_IN_128BIT_SWAP_CONTROL_FIELD_SHIFT 27
+
+extern const ru_field_rec NATC_CONTROL_STATUS_SMEM_32BIT_IN_64BIT_SWAP_CONTROL_FIELD;
+#define NATC_CONTROL_STATUS_SMEM_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_MASK  0x04000000
+#define NATC_CONTROL_STATUS_SMEM_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_SMEM_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_SHIFT 26
+
+extern const ru_field_rec NATC_CONTROL_STATUS_SMEM_8BIT_IN_32BIT_SWAP_CONTROL_FIELD;
+#define NATC_CONTROL_STATUS_SMEM_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_MASK  0x02000000
+#define NATC_CONTROL_STATUS_SMEM_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_SMEM_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_SHIFT 25
+
+extern const ru_field_rec NATC_CONTROL_STATUS_DDR_SWAP_ALL_CONTROL_FIELD;
+#define NATC_CONTROL_STATUS_DDR_SWAP_ALL_CONTROL_FIELD_MASK  0x01000000
+#define NATC_CONTROL_STATUS_DDR_SWAP_ALL_CONTROL_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_DDR_SWAP_ALL_CONTROL_FIELD_SHIFT 24
+
+extern const ru_field_rec NATC_CONTROL_STATUS_REPEATED_KEY_DET_EN_FIELD;
+#define NATC_CONTROL_STATUS_REPEATED_KEY_DET_EN_FIELD_MASK  0x00800000
+#define NATC_CONTROL_STATUS_REPEATED_KEY_DET_EN_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_REPEATED_KEY_DET_EN_FIELD_SHIFT 23
+
+extern const ru_field_rec NATC_CONTROL_STATUS_REG_32BIT_IN_64BIT_SWAP_CONTROL_FIELD;
+#define NATC_CONTROL_STATUS_REG_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_MASK  0x00400000
+#define NATC_CONTROL_STATUS_REG_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_REG_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_SHIFT 22
+
+extern const ru_field_rec NATC_CONTROL_STATUS_REG_8BIT_IN_32BIT_SWAP_CONTROL_FIELD;
+#define NATC_CONTROL_STATUS_REG_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_MASK  0x00200000
+#define NATC_CONTROL_STATUS_REG_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_REG_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_SHIFT 21
+
+extern const ru_field_rec NATC_CONTROL_STATUS_DDR_PENDING_HASH_MODE_FIELD;
+#define NATC_CONTROL_STATUS_DDR_PENDING_HASH_MODE_FIELD_MASK  0x001c0000
+#define NATC_CONTROL_STATUS_DDR_PENDING_HASH_MODE_FIELD_WIDTH 3
+#define NATC_CONTROL_STATUS_DDR_PENDING_HASH_MODE_FIELD_SHIFT 18
+
+extern const ru_field_rec NATC_CONTROL_STATUS_PENDING_FIFO_ENTRY_CHECK_ENABLE_FIELD;
+#define NATC_CONTROL_STATUS_PENDING_FIFO_ENTRY_CHECK_ENABLE_FIELD_MASK  0x00020000
+#define NATC_CONTROL_STATUS_PENDING_FIFO_ENTRY_CHECK_ENABLE_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_PENDING_FIFO_ENTRY_CHECK_ENABLE_FIELD_SHIFT 17
+
+extern const ru_field_rec NATC_CONTROL_STATUS_CACHE_UPDATE_ON_DDR_MISS_FIELD;
+#define NATC_CONTROL_STATUS_CACHE_UPDATE_ON_DDR_MISS_FIELD_MASK  0x00010000
+#define NATC_CONTROL_STATUS_CACHE_UPDATE_ON_DDR_MISS_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_CACHE_UPDATE_ON_DDR_MISS_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_CONTROL_STATUS_DDR_DISABLE_ON_REG_LOOKUP_FIELD;
+#define NATC_CONTROL_STATUS_DDR_DISABLE_ON_REG_LOOKUP_FIELD_MASK  0x00008000
+#define NATC_CONTROL_STATUS_DDR_DISABLE_ON_REG_LOOKUP_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_DDR_DISABLE_ON_REG_LOOKUP_FIELD_SHIFT 15
+
+extern const ru_field_rec NATC_CONTROL_STATUS_NAT_HASH_MODE_FIELD;
+#define NATC_CONTROL_STATUS_NAT_HASH_MODE_FIELD_MASK  0x00007000
+#define NATC_CONTROL_STATUS_NAT_HASH_MODE_FIELD_WIDTH 3
+#define NATC_CONTROL_STATUS_NAT_HASH_MODE_FIELD_SHIFT 12
+
+extern const ru_field_rec NATC_CONTROL_STATUS_MULTI_HASH_LIMIT_FIELD;
+#define NATC_CONTROL_STATUS_MULTI_HASH_LIMIT_FIELD_MASK  0x00000f00
+#define NATC_CONTROL_STATUS_MULTI_HASH_LIMIT_FIELD_WIDTH 4
+#define NATC_CONTROL_STATUS_MULTI_HASH_LIMIT_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_CONTROL_STATUS_DECR_COUNT_WRAPAROUND_ENABLE_FIELD;
+#define NATC_CONTROL_STATUS_DECR_COUNT_WRAPAROUND_ENABLE_FIELD_MASK  0x00000080
+#define NATC_CONTROL_STATUS_DECR_COUNT_WRAPAROUND_ENABLE_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_DECR_COUNT_WRAPAROUND_ENABLE_FIELD_SHIFT 7
+
+extern const ru_field_rec NATC_CONTROL_STATUS_NAT_ARB_ST_FIELD;
+#define NATC_CONTROL_STATUS_NAT_ARB_ST_FIELD_MASK  0x00000060
+#define NATC_CONTROL_STATUS_NAT_ARB_ST_FIELD_WIDTH 2
+#define NATC_CONTROL_STATUS_NAT_ARB_ST_FIELD_SHIFT 5
+
+extern const ru_field_rec NATC_CONTROL_STATUS_NATC_SMEM_INCREMENT_ON_REG_LOOKUP_FIELD;
+#define NATC_CONTROL_STATUS_NATC_SMEM_INCREMENT_ON_REG_LOOKUP_FIELD_MASK  0x00000010
+#define NATC_CONTROL_STATUS_NATC_SMEM_INCREMENT_ON_REG_LOOKUP_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_NATC_SMEM_INCREMENT_ON_REG_LOOKUP_FIELD_SHIFT 4
+
+extern const ru_field_rec NATC_CONTROL_STATUS_NATC_SMEM_CLEAR_BY_UPDATE_DISABLE_FIELD;
+#define NATC_CONTROL_STATUS_NATC_SMEM_CLEAR_BY_UPDATE_DISABLE_FIELD_MASK  0x00000008
+#define NATC_CONTROL_STATUS_NATC_SMEM_CLEAR_BY_UPDATE_DISABLE_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_NATC_SMEM_CLEAR_BY_UPDATE_DISABLE_FIELD_SHIFT 3
+
+extern const ru_field_rec NATC_CONTROL_STATUS_REGFILE_FIFO_RESET_FIELD;
+#define NATC_CONTROL_STATUS_REGFILE_FIFO_RESET_FIELD_MASK  0x00000004
+#define NATC_CONTROL_STATUS_REGFILE_FIFO_RESET_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_REGFILE_FIFO_RESET_FIELD_SHIFT 2
+
+extern const ru_field_rec NATC_CONTROL_STATUS_NATC_ENABLE_FIELD;
+#define NATC_CONTROL_STATUS_NATC_ENABLE_FIELD_MASK  0x00000002
+#define NATC_CONTROL_STATUS_NATC_ENABLE_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_NATC_ENABLE_FIELD_SHIFT 1
+
+extern const ru_field_rec NATC_CONTROL_STATUS_NATC_RESET_FIELD;
+#define NATC_CONTROL_STATUS_NATC_RESET_FIELD_MASK  0x00000001
+#define NATC_CONTROL_STATUS_NATC_RESET_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS_NATC_RESET_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_HASH_MODE_FIELD;
+#define NATC_CONTROL_STATUS2_DDR_HASH_MODE_FIELD_MASK  0xe0000000
+#define NATC_CONTROL_STATUS2_DDR_HASH_MODE_FIELD_WIDTH 3
+#define NATC_CONTROL_STATUS2_DDR_HASH_MODE_FIELD_SHIFT 29
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_32BIT_IN_64BIT_SWAP_CONTROL_FIELD;
+#define NATC_CONTROL_STATUS2_DDR_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_MASK  0x10000000
+#define NATC_CONTROL_STATUS2_DDR_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS2_DDR_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_SHIFT 28
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_8BIT_IN_32BIT_SWAP_CONTROL_FIELD;
+#define NATC_CONTROL_STATUS2_DDR_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_MASK  0x08000000
+#define NATC_CONTROL_STATUS2_DDR_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS2_DDR_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_SHIFT 27
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_CACHE_LOOKUP_BLOCKING_MODE_FIELD;
+#define NATC_CONTROL_STATUS2_CACHE_LOOKUP_BLOCKING_MODE_FIELD_MASK  0x04000000
+#define NATC_CONTROL_STATUS2_CACHE_LOOKUP_BLOCKING_MODE_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS2_CACHE_LOOKUP_BLOCKING_MODE_FIELD_SHIFT 26
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_AGE_TIMER_TICK_FIELD;
+#define NATC_CONTROL_STATUS2_AGE_TIMER_TICK_FIELD_MASK  0x02000000
+#define NATC_CONTROL_STATUS2_AGE_TIMER_TICK_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS2_AGE_TIMER_TICK_FIELD_SHIFT 25
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_AGE_TIMER_FIELD;
+#define NATC_CONTROL_STATUS2_AGE_TIMER_FIELD_MASK  0x01f00000
+#define NATC_CONTROL_STATUS2_AGE_TIMER_FIELD_WIDTH 5
+#define NATC_CONTROL_STATUS2_AGE_TIMER_FIELD_SHIFT 20
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_CACHE_ALGO_FIELD;
+#define NATC_CONTROL_STATUS2_CACHE_ALGO_FIELD_MASK  0x000f0000
+#define NATC_CONTROL_STATUS2_CACHE_ALGO_FIELD_WIDTH 4
+#define NATC_CONTROL_STATUS2_CACHE_ALGO_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_UNUSED2_FIELD;
+#define NATC_CONTROL_STATUS2_UNUSED2_FIELD_MASK  0x0000ff00
+#define NATC_CONTROL_STATUS2_UNUSED2_FIELD_WIDTH 8
+#define NATC_CONTROL_STATUS2_UNUSED2_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_UNUSED1_FIELD;
+#define NATC_CONTROL_STATUS2_UNUSED1_FIELD_MASK  0x000000c0
+#define NATC_CONTROL_STATUS2_UNUSED1_FIELD_WIDTH 2
+#define NATC_CONTROL_STATUS2_UNUSED1_FIELD_SHIFT 6
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_CACHE_UPDATE_ON_REG_DDR_LOOKUP_FIELD;
+#define NATC_CONTROL_STATUS2_CACHE_UPDATE_ON_REG_DDR_LOOKUP_FIELD_MASK  0x00000020
+#define NATC_CONTROL_STATUS2_CACHE_UPDATE_ON_REG_DDR_LOOKUP_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS2_CACHE_UPDATE_ON_REG_DDR_LOOKUP_FIELD_SHIFT 5
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_COUNTER_8BIT_IN_32BIT_SWAP_CONTROL_FIELD;
+#define NATC_CONTROL_STATUS2_DDR_COUNTER_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_MASK  0x00000010
+#define NATC_CONTROL_STATUS2_DDR_COUNTER_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS2_DDR_COUNTER_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_SHIFT 4
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_HASH_SWAP_FIELD;
+#define NATC_CONTROL_STATUS2_DDR_HASH_SWAP_FIELD_MASK  0x00000008
+#define NATC_CONTROL_STATUS2_DDR_HASH_SWAP_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS2_DDR_HASH_SWAP_FIELD_SHIFT 3
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_REPLACE_DUPLICATED_CACHED_ENTRY_ENABLE_FIELD;
+#define NATC_CONTROL_STATUS2_DDR_REPLACE_DUPLICATED_CACHED_ENTRY_ENABLE_FIELD_MASK  0x00000004
+#define NATC_CONTROL_STATUS2_DDR_REPLACE_DUPLICATED_CACHED_ENTRY_ENABLE_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS2_DDR_REPLACE_DUPLICATED_CACHED_ENTRY_ENABLE_FIELD_SHIFT 2
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_LOOKUP_PENDING_FIFO_MODE_DISABLE_FIELD;
+#define NATC_CONTROL_STATUS2_DDR_LOOKUP_PENDING_FIFO_MODE_DISABLE_FIELD_MASK  0x00000002
+#define NATC_CONTROL_STATUS2_DDR_LOOKUP_PENDING_FIFO_MODE_DISABLE_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS2_DDR_LOOKUP_PENDING_FIFO_MODE_DISABLE_FIELD_SHIFT 1
+
+extern const ru_field_rec NATC_CONTROL_STATUS2_UNUSED3_FIELD;
+#define NATC_CONTROL_STATUS2_UNUSED3_FIELD_MASK  0x00000001
+#define NATC_CONTROL_STATUS2_UNUSED3_FIELD_WIDTH 1
+#define NATC_CONTROL_STATUS2_UNUSED3_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_TABLE_CONTROL_SMEM_DIS_TBL7_FIELD;
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL7_FIELD_MASK  0x80000000
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL7_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL7_FIELD_SHIFT 31
+
+extern const ru_field_rec NATC_TABLE_CONTROL_SMEM_DIS_TBL6_FIELD;
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL6_FIELD_MASK  0x40000000
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL6_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL6_FIELD_SHIFT 30
+
+extern const ru_field_rec NATC_TABLE_CONTROL_SMEM_DIS_TBL5_FIELD;
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL5_FIELD_MASK  0x20000000
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL5_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL5_FIELD_SHIFT 29
+
+extern const ru_field_rec NATC_TABLE_CONTROL_SMEM_DIS_TBL4_FIELD;
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL4_FIELD_MASK  0x10000000
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL4_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL4_FIELD_SHIFT 28
+
+extern const ru_field_rec NATC_TABLE_CONTROL_SMEM_DIS_TBL3_FIELD;
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL3_FIELD_MASK  0x08000000
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL3_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL3_FIELD_SHIFT 27
+
+extern const ru_field_rec NATC_TABLE_CONTROL_SMEM_DIS_TBL2_FIELD;
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL2_FIELD_MASK  0x04000000
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL2_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL2_FIELD_SHIFT 26
+
+extern const ru_field_rec NATC_TABLE_CONTROL_SMEM_DIS_TBL1_FIELD;
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL1_FIELD_MASK  0x02000000
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL1_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL1_FIELD_SHIFT 25
+
+extern const ru_field_rec NATC_TABLE_CONTROL_SMEM_DIS_TBL0_FIELD;
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL0_FIELD_MASK  0x01000000
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL0_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_SMEM_DIS_TBL0_FIELD_SHIFT 24
+
+extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL7_FIELD;
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL7_FIELD_MASK  0x00800000
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL7_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL7_FIELD_SHIFT 23
+
+extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL6_FIELD;
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL6_FIELD_MASK  0x00400000
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL6_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL6_FIELD_SHIFT 22
+
+extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL5_FIELD;
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL5_FIELD_MASK  0x00200000
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL5_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL5_FIELD_SHIFT 21
+
+extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL4_FIELD;
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL4_FIELD_MASK  0x00100000
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL4_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL4_FIELD_SHIFT 20
+
+extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL3_FIELD;
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL3_FIELD_MASK  0x00080000
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL3_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL3_FIELD_SHIFT 19
+
+extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL2_FIELD;
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL2_FIELD_MASK  0x00040000
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL2_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL2_FIELD_SHIFT 18
+
+extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL1_FIELD;
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL1_FIELD_MASK  0x00020000
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL1_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL1_FIELD_SHIFT 17
+
+extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL0_FIELD;
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL0_FIELD_MASK  0x00010000
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL0_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL0_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL7_FIELD;
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL7_FIELD_MASK  0x00008000
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL7_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL7_FIELD_SHIFT 15
+
+extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL7_FIELD;
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL7_FIELD_MASK  0x00004000
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL7_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL7_FIELD_SHIFT 14
+
+extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL6_FIELD;
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL6_FIELD_MASK  0x00002000
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL6_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL6_FIELD_SHIFT 13
+
+extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL6_FIELD;
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL6_FIELD_MASK  0x00001000
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL6_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL6_FIELD_SHIFT 12
+
+extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL5_FIELD;
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL5_FIELD_MASK  0x00000800
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL5_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL5_FIELD_SHIFT 11
+
+extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL5_FIELD;
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL5_FIELD_MASK  0x00000400
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL5_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL5_FIELD_SHIFT 10
+
+extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL4_FIELD;
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL4_FIELD_MASK  0x00000200
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL4_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL4_FIELD_SHIFT 9
+
+extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL4_FIELD;
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL4_FIELD_MASK  0x00000100
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL4_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL4_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL3_FIELD;
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL3_FIELD_MASK  0x00000080
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL3_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL3_FIELD_SHIFT 7
+
+extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL3_FIELD;
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL3_FIELD_MASK  0x00000040
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL3_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL3_FIELD_SHIFT 6
+
+extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL2_FIELD;
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL2_FIELD_MASK  0x00000020
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL2_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL2_FIELD_SHIFT 5
+
+extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL2_FIELD;
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL2_FIELD_MASK  0x00000010
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL2_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL2_FIELD_SHIFT 4
+
+extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL1_FIELD;
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL1_FIELD_MASK  0x00000008
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL1_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL1_FIELD_SHIFT 3
+
+extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL1_FIELD;
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL1_FIELD_MASK  0x00000004
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL1_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL1_FIELD_SHIFT 2
+
+extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL0_FIELD;
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL0_FIELD_MASK  0x00000002
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL0_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_KEY_LEN_TBL0_FIELD_SHIFT 1
+
+extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL0_FIELD;
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL0_FIELD_MASK  0x00000001
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL0_FIELD_WIDTH 1
+#define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL0_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_STAT_COUNTER_CONTROL_0_DDR_EVICT_COUNT_EN_FIELD;
+#define NATC_STAT_COUNTER_CONTROL_0_DDR_EVICT_COUNT_EN_FIELD_MASK  0xff000000
+#define NATC_STAT_COUNTER_CONTROL_0_DDR_EVICT_COUNT_EN_FIELD_WIDTH 8
+#define NATC_STAT_COUNTER_CONTROL_0_DDR_EVICT_COUNT_EN_FIELD_SHIFT 24
+
+extern const ru_field_rec NATC_STAT_COUNTER_CONTROL_0_DDR_REQUEST_COUNT_EN_FIELD;
+#define NATC_STAT_COUNTER_CONTROL_0_DDR_REQUEST_COUNT_EN_FIELD_MASK  0x00ff0000
+#define NATC_STAT_COUNTER_CONTROL_0_DDR_REQUEST_COUNT_EN_FIELD_WIDTH 8
+#define NATC_STAT_COUNTER_CONTROL_0_DDR_REQUEST_COUNT_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_STAT_COUNTER_CONTROL_0_CACHE_MISS_COUNT_EN_FIELD;
+#define NATC_STAT_COUNTER_CONTROL_0_CACHE_MISS_COUNT_EN_FIELD_MASK  0x0000ff00
+#define NATC_STAT_COUNTER_CONTROL_0_CACHE_MISS_COUNT_EN_FIELD_WIDTH 8
+#define NATC_STAT_COUNTER_CONTROL_0_CACHE_MISS_COUNT_EN_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_STAT_COUNTER_CONTROL_0_CACHE_HIT_COUNT_EN_FIELD;
+#define NATC_STAT_COUNTER_CONTROL_0_CACHE_HIT_COUNT_EN_FIELD_MASK  0x000000ff
+#define NATC_STAT_COUNTER_CONTROL_0_CACHE_HIT_COUNT_EN_FIELD_WIDTH 8
+#define NATC_STAT_COUNTER_CONTROL_0_CACHE_HIT_COUNT_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_STAT_COUNTER_CONTROL_1_RESERVED0_FIELD;
+#define NATC_STAT_COUNTER_CONTROL_1_RESERVED0_FIELD_MASK  0xfffffe00
+#define NATC_STAT_COUNTER_CONTROL_1_RESERVED0_FIELD_WIDTH 23
+#define NATC_STAT_COUNTER_CONTROL_1_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec NATC_STAT_COUNTER_CONTROL_1_COUNTER_WRAPAROUND_DIS_FIELD;
+#define NATC_STAT_COUNTER_CONTROL_1_COUNTER_WRAPAROUND_DIS_FIELD_MASK  0x00000100
+#define NATC_STAT_COUNTER_CONTROL_1_COUNTER_WRAPAROUND_DIS_FIELD_WIDTH 1
+#define NATC_STAT_COUNTER_CONTROL_1_COUNTER_WRAPAROUND_DIS_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_STAT_COUNTER_CONTROL_1_DDR_BLOCK_COUNT_EN_FIELD;
+#define NATC_STAT_COUNTER_CONTROL_1_DDR_BLOCK_COUNT_EN_FIELD_MASK  0x000000ff
+#define NATC_STAT_COUNTER_CONTROL_1_DDR_BLOCK_COUNT_EN_FIELD_WIDTH 8
+#define NATC_STAT_COUNTER_CONTROL_1_DDR_BLOCK_COUNT_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_3_FIELD;
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_3_FIELD_MASK  0xff000000
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_3_FIELD_WIDTH 8
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_3_FIELD_SHIFT 24
+
+extern const ru_field_rec NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_2_FIELD;
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_2_FIELD_MASK  0x00ff0000
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_2_FIELD_WIDTH 8
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_2_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_1_FIELD;
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_1_FIELD_MASK  0x0000ff00
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_1_FIELD_WIDTH 8
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_1_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_0_FIELD;
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_0_FIELD_MASK  0x000000ff
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_0_FIELD_WIDTH 8
+#define NATC_REGFILE_FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_0_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_7_FIELD;
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_7_FIELD_MASK  0xff000000
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_7_FIELD_WIDTH 8
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_7_FIELD_SHIFT 24
+
+extern const ru_field_rec NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_6_FIELD;
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_6_FIELD_MASK  0x00ff0000
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_6_FIELD_WIDTH 8
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_6_FIELD_SHIFT 16
+
+extern const ru_field_rec NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_5_FIELD;
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_5_FIELD_MASK  0x0000ff00
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_5_FIELD_WIDTH 8
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_5_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_4_FIELD;
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_4_FIELD_MASK  0x000000ff
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_4_FIELD_WIDTH 8
+#define NATC_REGFILE_FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_4_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD;
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD_MASK  0xfffffff8
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD_WIDTH 29
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD_SHIFT 3
+
+extern const ru_field_rec NATC_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD;
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD_MASK  0x00000007
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD_WIDTH 3
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD;
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD_MASK  0xffffff00
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD_WIDTH 24
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD;
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD_MASK  0x000000ff
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD_WIDTH 8
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD;
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD_MASK  0xfffffff8
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD_WIDTH 29
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD_SHIFT 3
+
+extern const ru_field_rec NATC_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD;
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD_MASK  0x00000007
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD_WIDTH 3
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD;
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD_MASK  0xffffff00
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD_WIDTH 24
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD_SHIFT 8
+
+extern const ru_field_rec NATC_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD;
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD_MASK  0x000000ff
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD_WIDTH 8
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_KEY_MASK_KEY_MASK_FIELD;
+#define NATC_KEY_MASK_KEY_MASK_FIELD_MASK  0xffffffff
+#define NATC_KEY_MASK_KEY_MASK_FIELD_WIDTH 32
+#define NATC_KEY_MASK_KEY_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_INDIR_C_INDIR_ADDR_REG_RESERVED0_FIELD;
+#define NATC_INDIR_C_INDIR_ADDR_REG_RESERVED0_FIELD_MASK  0xfffff800
+#define NATC_INDIR_C_INDIR_ADDR_REG_RESERVED0_FIELD_WIDTH 21
+#define NATC_INDIR_C_INDIR_ADDR_REG_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec NATC_INDIR_C_INDIR_ADDR_REG_W_R_FIELD;
+#define NATC_INDIR_C_INDIR_ADDR_REG_W_R_FIELD_MASK  0x00000400
+#define NATC_INDIR_C_INDIR_ADDR_REG_W_R_FIELD_WIDTH 1
+#define NATC_INDIR_C_INDIR_ADDR_REG_W_R_FIELD_SHIFT 10
+
+extern const ru_field_rec NATC_INDIR_C_INDIR_ADDR_REG_NATC_ENTRY_FIELD;
+#define NATC_INDIR_C_INDIR_ADDR_REG_NATC_ENTRY_FIELD_MASK  0x000003ff
+#define NATC_INDIR_C_INDIR_ADDR_REG_NATC_ENTRY_FIELD_WIDTH 10
+#define NATC_INDIR_C_INDIR_ADDR_REG_NATC_ENTRY_FIELD_SHIFT 0
+
+extern const ru_field_rec NATC_INDIR_C_INDIR_DATA_REG_DATA_FIELD;
+#define NATC_INDIR_C_INDIR_DATA_REG_DATA_FIELD_MASK  0xffffffff
+#define NATC_INDIR_C_INDIR_DATA_REG_DATA_FIELD_WIDTH 32
+#define NATC_INDIR_C_INDIR_DATA_REG_DATA_FIELD_SHIFT 0
+
+
+
+/******************************************************************************
+ * XRDP_ Registers
+ ******************************************************************************/
+extern const ru_reg_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_REG;
+#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_REG;
+#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_REG;
+#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec QM_GLOBAL_CFG_FPM_CONTROL_REG;
+#define QM_GLOBAL_CFG_FPM_CONTROL_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_REG;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_REG;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_REG;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_REG;
+#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_REG;
+#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_REG;
+#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec QM_GLOBAL_CFG_ABS_DROP_QUEUE_REG;
+#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec QM_GLOBAL_CFG_AGGREGATION_CTRL_REG;
+#define QM_GLOBAL_CFG_AGGREGATION_CTRL_REG_OFFSET 0x0000002c
+
+extern const ru_reg_rec QM_GLOBAL_CFG_FPM_BASE_ADDR_REG;
+#define QM_GLOBAL_CFG_FPM_BASE_ADDR_REG_OFFSET 0x00000030
+
+extern const ru_reg_rec QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_REG;
+#define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_REG_OFFSET 0x00000034
+
+extern const ru_reg_rec QM_GLOBAL_CFG_DDR_SOP_OFFSET_REG;
+#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_REG_OFFSET 0x00000038
+
+extern const ru_reg_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_REG;
+#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_REG_OFFSET 0x0000003c
+
+extern const ru_reg_rec QM_GLOBAL_CFG_DQM_FULL_REG;
+#define QM_GLOBAL_CFG_DQM_FULL_REG_OFFSET 0x00000040
+
+#define QM_GLOBAL_CFG_DQM_FULL_REG_RAM_CNT 0x00000008
+
+extern const ru_reg_rec QM_GLOBAL_CFG_DQM_NOT_EMPTY_REG;
+#define QM_GLOBAL_CFG_DQM_NOT_EMPTY_REG_OFFSET 0x00000070
+
+#define QM_GLOBAL_CFG_DQM_NOT_EMPTY_REG_RAM_CNT 0x00000008
+
+extern const ru_reg_rec QM_GLOBAL_CFG_DQM_POP_READY_REG;
+#define QM_GLOBAL_CFG_DQM_POP_READY_REG_OFFSET 0x000000a0
+
+#define QM_GLOBAL_CFG_DQM_POP_READY_REG_RAM_CNT 0x00000008
+
+extern const ru_reg_rec QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_REG;
+#define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_REG_OFFSET 0x000000d0
+
+#define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_REG_RAM_CNT 0x00000008
+
+extern const ru_reg_rec QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_REG;
+#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_REG_OFFSET 0x00000100
+
+extern const ru_reg_rec QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_REG;
+#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_REG_OFFSET 0x00000118
+
+extern const ru_reg_rec QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_REG;
+#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_REG_OFFSET 0x0000011c
+
+extern const ru_reg_rec QM_GLOBAL_CFG_DDR_SPARE_ROOM_REG;
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_REG_OFFSET 0x00000120
+
+#define QM_GLOBAL_CFG_DDR_SPARE_ROOM_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_REG;
+#define QM_GLOBAL_CFG_DUMMY_SPARE_ROOM_PROFILE_ID_REG_OFFSET 0x00000130
+
+extern const ru_reg_rec QM_FPM_POOLS_THR_REG;
+#define QM_FPM_POOLS_THR_REG_OFFSET 0x00000200
+
+#define QM_FPM_POOLS_THR_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_FPM_USR_GRP_LOWER_THR_REG;
+#define QM_FPM_USR_GRP_LOWER_THR_REG_OFFSET 0x00000280
+
+#define QM_FPM_USR_GRP_LOWER_THR_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_FPM_USR_GRP_MID_THR_REG;
+#define QM_FPM_USR_GRP_MID_THR_REG_OFFSET 0x00000284
+
+#define QM_FPM_USR_GRP_MID_THR_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_FPM_USR_GRP_HIGHER_THR_REG;
+#define QM_FPM_USR_GRP_HIGHER_THR_REG_OFFSET 0x00000288
+
+#define QM_FPM_USR_GRP_HIGHER_THR_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_FPM_USR_GRP_CNT_REG;
+#define QM_FPM_USR_GRP_CNT_REG_OFFSET 0x0000028c
+
+#define QM_FPM_USR_GRP_CNT_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_RUNNER_GRP_RNR_CONFIG_REG;
+#define QM_RUNNER_GRP_RNR_CONFIG_REG_OFFSET 0x00000300
+
+#define QM_RUNNER_GRP_RNR_CONFIG_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec QM_RUNNER_GRP_QUEUE_CONFIG_REG;
+#define QM_RUNNER_GRP_QUEUE_CONFIG_REG_OFFSET 0x00000304
+
+#define QM_RUNNER_GRP_QUEUE_CONFIG_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec QM_RUNNER_GRP_PDFIFO_CONFIG_REG;
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_REG_OFFSET 0x00000308
+
+#define QM_RUNNER_GRP_PDFIFO_CONFIG_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_REG;
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_REG_OFFSET 0x0000030c
+
+#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec QM_INTR_CTRL_ISR_REG;
+#define QM_INTR_CTRL_ISR_REG_OFFSET 0x00000400
+
+extern const ru_reg_rec QM_INTR_CTRL_ISM_REG;
+#define QM_INTR_CTRL_ISM_REG_OFFSET 0x00000404
+
+extern const ru_reg_rec QM_INTR_CTRL_IER_REG;
+#define QM_INTR_CTRL_IER_REG_OFFSET 0x00000408
+
+extern const ru_reg_rec QM_INTR_CTRL_ITR_REG;
+#define QM_INTR_CTRL_ITR_REG_OFFSET 0x0000040c
+
+extern const ru_reg_rec QM_CLK_GATE_CLK_GATE_CNTRL_REG;
+#define QM_CLK_GATE_CLK_GATE_CNTRL_REG_OFFSET 0x00000500
+
+extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_REG;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_REG_OFFSET 0x00000600
+
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_REG;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_REG_OFFSET 0x00000610
+
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_REG;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_REG_OFFSET 0x00000614
+
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_REG;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_REG_OFFSET 0x00000618
+
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_REG;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_REG_OFFSET 0x0000061c
+
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_REG;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_REG_OFFSET 0x00000620
+
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_REG;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_REG_OFFSET 0x00000624
+
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_REG;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_REG_OFFSET 0x00000628
+
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_REG;
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_REG_OFFSET 0x0000062c
+
+#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_QUEUE_CONTEXT_CONTEXT_REG;
+#define QM_QUEUE_CONTEXT_CONTEXT_REG_OFFSET 0x00000800
+
+#define QM_QUEUE_CONTEXT_CONTEXT_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec QM_WRED_PROFILE_COLOR_MIN_THR_0_REG;
+#define QM_WRED_PROFILE_COLOR_MIN_THR_0_REG_OFFSET 0x00001000
+
+#define QM_WRED_PROFILE_COLOR_MIN_THR_0_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec QM_WRED_PROFILE_COLOR_MIN_THR_1_REG;
+#define QM_WRED_PROFILE_COLOR_MIN_THR_1_REG_OFFSET 0x00001004
+
+#define QM_WRED_PROFILE_COLOR_MIN_THR_1_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec QM_WRED_PROFILE_COLOR_MAX_THR_0_REG;
+#define QM_WRED_PROFILE_COLOR_MAX_THR_0_REG_OFFSET 0x00001010
+
+#define QM_WRED_PROFILE_COLOR_MAX_THR_0_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec QM_WRED_PROFILE_COLOR_MAX_THR_1_REG;
+#define QM_WRED_PROFILE_COLOR_MAX_THR_1_REG_OFFSET 0x00001014
+
+#define QM_WRED_PROFILE_COLOR_MAX_THR_1_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec QM_WRED_PROFILE_COLOR_SLOPE_0_REG;
+#define QM_WRED_PROFILE_COLOR_SLOPE_0_REG_OFFSET 0x00001020
+
+#define QM_WRED_PROFILE_COLOR_SLOPE_0_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec QM_WRED_PROFILE_COLOR_SLOPE_1_REG;
+#define QM_WRED_PROFILE_COLOR_SLOPE_1_REG_OFFSET 0x00001024
+
+#define QM_WRED_PROFILE_COLOR_SLOPE_1_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec QM_COPY_DECISION_PROFILE_THR_REG;
+#define QM_COPY_DECISION_PROFILE_THR_REG_OFFSET 0x00001800
+
+#define QM_COPY_DECISION_PROFILE_THR_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec QM_TOTAL_VALID_COUNTER_COUNTER_REG;
+#define QM_TOTAL_VALID_COUNTER_COUNTER_REG_OFFSET 0x00002000
+
+#define QM_TOTAL_VALID_COUNTER_COUNTER_REG_RAM_CNT 0x000001ff
+
+extern const ru_reg_rec QM_DQM_VALID_COUNTER_COUNTER_REG;
+#define QM_DQM_VALID_COUNTER_COUNTER_REG_OFFSET 0x00003000
+
+#define QM_DQM_VALID_COUNTER_COUNTER_REG_RAM_CNT 0x000000ff
+
+extern const ru_reg_rec QM_DROP_COUNTER_COUNTER_REG;
+#define QM_DROP_COUNTER_COUNTER_REG_OFFSET 0x00004000
+
+#define QM_DROP_COUNTER_COUNTER_REG_RAM_CNT 0x000000ff
+
+extern const ru_reg_rec QM_EPON_RPT_CNT_COUNTER_REG;
+#define QM_EPON_RPT_CNT_COUNTER_REG_OFFSET 0x00005000
+
+#define QM_EPON_RPT_CNT_COUNTER_REG_RAM_CNT 0x000000ff
+
+extern const ru_reg_rec QM_EPON_RPT_CNT_QUEUE_STATUS_REG;
+#define QM_EPON_RPT_CNT_QUEUE_STATUS_REG_OFFSET 0x00005500
+
+#define QM_EPON_RPT_CNT_QUEUE_STATUS_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_RD_DATA_POOL0_REG;
+#define QM_RD_DATA_POOL0_REG_OFFSET 0x00005800
+
+extern const ru_reg_rec QM_RD_DATA_POOL1_REG;
+#define QM_RD_DATA_POOL1_REG_OFFSET 0x00005804
+
+extern const ru_reg_rec QM_RD_DATA_POOL2_REG;
+#define QM_RD_DATA_POOL2_REG_OFFSET 0x00005808
+
+extern const ru_reg_rec QM_RD_DATA_POOL3_REG;
+#define QM_RD_DATA_POOL3_REG_OFFSET 0x0000580c
+
+extern const ru_reg_rec QM_PDFIFO_PTR_REG;
+#define QM_PDFIFO_PTR_REG_OFFSET 0x00006000
+
+#define QM_PDFIFO_PTR_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec QM_UPDATE_FIFO_PTR_REG;
+#define QM_UPDATE_FIFO_PTR_REG_OFFSET 0x00006500
+
+#define QM_UPDATE_FIFO_PTR_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec QM_RD_DATA_REG;
+#define QM_RD_DATA_REG_OFFSET 0x00008800
+
+#define QM_RD_DATA_REG_RAM_CNT 0x00000004
+
+extern const ru_reg_rec QM_POP_REG;
+#define QM_POP_REG_OFFSET 0x00008820
+
+extern const ru_reg_rec QM_CM_COMMON_INPUT_FIFO_DATA_REG;
+#define QM_CM_COMMON_INPUT_FIFO_DATA_REG_OFFSET 0x00009000
+
+#define QM_CM_COMMON_INPUT_FIFO_DATA_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec QM_NORMAL_RMT_FIFO_DATA_REG;
+#define QM_NORMAL_RMT_FIFO_DATA_REG_OFFSET 0x00009100
+
+#define QM_NORMAL_RMT_FIFO_DATA_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec QM_NON_DELAYED_RMT_FIFO_DATA_REG;
+#define QM_NON_DELAYED_RMT_FIFO_DATA_REG_OFFSET 0x00009200
+
+#define QM_NON_DELAYED_RMT_FIFO_DATA_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec QM_EGRESS_DATA_FIFO_DATA_REG;
+#define QM_EGRESS_DATA_FIFO_DATA_REG_OFFSET 0x00009300
+
+#define QM_EGRESS_DATA_FIFO_DATA_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec QM_EGRESS_RR_FIFO_DATA_REG;
+#define QM_EGRESS_RR_FIFO_DATA_REG_OFFSET 0x00009400
+
+#define QM_EGRESS_RR_FIFO_DATA_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec QM_EGRESS_BB_INPUT_FIFO_DATA_REG;
+#define QM_EGRESS_BB_INPUT_FIFO_DATA_REG_OFFSET 0x00009500
+
+#define QM_EGRESS_BB_INPUT_FIFO_DATA_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec QM_EGRESS_BB_OUTPUT_FIFO_DATA_REG;
+#define QM_EGRESS_BB_OUTPUT_FIFO_DATA_REG_OFFSET 0x00009600
+
+#define QM_EGRESS_BB_OUTPUT_FIFO_DATA_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec QM_BB_OUTPUT_FIFO_DATA_REG;
+#define QM_BB_OUTPUT_FIFO_DATA_REG_OFFSET 0x00009700
+
+#define QM_BB_OUTPUT_FIFO_DATA_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec QM_NON_DELAYED_OUT_FIFO_DATA_REG;
+#define QM_NON_DELAYED_OUT_FIFO_DATA_REG_OFFSET 0x00009800
+
+#define QM_NON_DELAYED_OUT_FIFO_DATA_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec QM_CONTEXT_DATA_REG;
+#define QM_CONTEXT_DATA_REG_OFFSET 0x0000a000
+
+#define QM_CONTEXT_DATA_REG_RAM_CNT 0x0000027f
+
+extern const ru_reg_rec QM_FPM_BUFFER_RESERVATION_DATA_REG;
+#define QM_FPM_BUFFER_RESERVATION_DATA_REG_OFFSET 0x0000c000
+
+#define QM_FPM_BUFFER_RESERVATION_DATA_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec QM_UG_CTRL_REG;
+#define QM_UG_CTRL_REG_OFFSET 0x0000c100
+
+extern const ru_reg_rec QM_STATUS_REG;
+#define QM_STATUS_REG_OFFSET 0x0000c104
+
+extern const ru_reg_rec QM_WRED_SOURCE_REG;
+#define QM_WRED_SOURCE_REG_OFFSET 0x0000c108
+
+#define QM_WRED_SOURCE_REG_RAM_CNT 0x00000004
+
+extern const ru_reg_rec QM_QM_FLOW_CTRL_RNR_CFG_REG;
+#define QM_QM_FLOW_CTRL_RNR_CFG_REG_OFFSET 0x0000c130
+
+extern const ru_reg_rec QM_DEBUG_SEL_REG;
+#define QM_DEBUG_SEL_REG_OFFSET 0x00016000
+
+extern const ru_reg_rec QM_DEBUG_BUS_LSB_REG;
+#define QM_DEBUG_BUS_LSB_REG_OFFSET 0x00016004
+
+extern const ru_reg_rec QM_DEBUG_BUS_MSB_REG;
+#define QM_DEBUG_BUS_MSB_REG_OFFSET 0x00016008
+
+extern const ru_reg_rec QM_QM_SPARE_CONFIG_REG;
+#define QM_QM_SPARE_CONFIG_REG_OFFSET 0x0001600c
+
+extern const ru_reg_rec QM_GOOD_LVL1_PKTS_CNT_REG;
+#define QM_GOOD_LVL1_PKTS_CNT_REG_OFFSET 0x00016010
+
+extern const ru_reg_rec QM_GOOD_LVL1_BYTES_CNT_REG;
+#define QM_GOOD_LVL1_BYTES_CNT_REG_OFFSET 0x00016014
+
+extern const ru_reg_rec QM_GOOD_LVL2_PKTS_CNT_REG;
+#define QM_GOOD_LVL2_PKTS_CNT_REG_OFFSET 0x00016018
+
+extern const ru_reg_rec QM_GOOD_LVL2_BYTES_CNT_REG;
+#define QM_GOOD_LVL2_BYTES_CNT_REG_OFFSET 0x0001601c
+
+extern const ru_reg_rec QM_COPIED_PKTS_CNT_REG;
+#define QM_COPIED_PKTS_CNT_REG_OFFSET 0x00016020
+
+extern const ru_reg_rec QM_COPIED_BYTES_CNT_REG;
+#define QM_COPIED_BYTES_CNT_REG_OFFSET 0x00016024
+
+extern const ru_reg_rec QM_AGG_PKTS_CNT_REG;
+#define QM_AGG_PKTS_CNT_REG_OFFSET 0x00016028
+
+extern const ru_reg_rec QM_AGG_BYTES_CNT_REG;
+#define QM_AGG_BYTES_CNT_REG_OFFSET 0x0001602c
+
+extern const ru_reg_rec QM_AGG_1_PKTS_CNT_REG;
+#define QM_AGG_1_PKTS_CNT_REG_OFFSET 0x00016030
+
+extern const ru_reg_rec QM_AGG_2_PKTS_CNT_REG;
+#define QM_AGG_2_PKTS_CNT_REG_OFFSET 0x00016034
+
+extern const ru_reg_rec QM_AGG_3_PKTS_CNT_REG;
+#define QM_AGG_3_PKTS_CNT_REG_OFFSET 0x00016038
+
+extern const ru_reg_rec QM_AGG_4_PKTS_CNT_REG;
+#define QM_AGG_4_PKTS_CNT_REG_OFFSET 0x0001603c
+
+extern const ru_reg_rec QM_WRED_DROP_CNT_REG;
+#define QM_WRED_DROP_CNT_REG_OFFSET 0x00016040
+
+extern const ru_reg_rec QM_FPM_CONGESTION_DROP_CNT_REG;
+#define QM_FPM_CONGESTION_DROP_CNT_REG_OFFSET 0x00016048
+
+extern const ru_reg_rec QM_DDR_PD_CONGESTION_DROP_CNT_REG;
+#define QM_DDR_PD_CONGESTION_DROP_CNT_REG_OFFSET 0x00016050
+
+extern const ru_reg_rec QM_DDR_BYTE_CONGESTION_DROP_CNT_REG;
+#define QM_DDR_BYTE_CONGESTION_DROP_CNT_REG_OFFSET 0x00016054
+
+extern const ru_reg_rec QM_QM_PD_CONGESTION_DROP_CNT_REG;
+#define QM_QM_PD_CONGESTION_DROP_CNT_REG_OFFSET 0x00016058
+
+extern const ru_reg_rec QM_QM_ABS_REQUEUE_CNT_REG;
+#define QM_QM_ABS_REQUEUE_CNT_REG_OFFSET 0x0001605c
+
+extern const ru_reg_rec QM_FPM_PREFETCH_FIFO0_STATUS_REG;
+#define QM_FPM_PREFETCH_FIFO0_STATUS_REG_OFFSET 0x00016060
+
+extern const ru_reg_rec QM_FPM_PREFETCH_FIFO1_STATUS_REG;
+#define QM_FPM_PREFETCH_FIFO1_STATUS_REG_OFFSET 0x00016064
+
+extern const ru_reg_rec QM_FPM_PREFETCH_FIFO2_STATUS_REG;
+#define QM_FPM_PREFETCH_FIFO2_STATUS_REG_OFFSET 0x00016068
+
+extern const ru_reg_rec QM_FPM_PREFETCH_FIFO3_STATUS_REG;
+#define QM_FPM_PREFETCH_FIFO3_STATUS_REG_OFFSET 0x0001606c
+
+extern const ru_reg_rec QM_NORMAL_RMT_FIFO_STATUS_REG;
+#define QM_NORMAL_RMT_FIFO_STATUS_REG_OFFSET 0x00016070
+
+extern const ru_reg_rec QM_NON_DELAYED_RMT_FIFO_STATUS_REG;
+#define QM_NON_DELAYED_RMT_FIFO_STATUS_REG_OFFSET 0x00016074
+
+extern const ru_reg_rec QM_NON_DELAYED_OUT_FIFO_STATUS_REG;
+#define QM_NON_DELAYED_OUT_FIFO_STATUS_REG_OFFSET 0x00016078
+
+extern const ru_reg_rec QM_PRE_CM_FIFO_STATUS_REG;
+#define QM_PRE_CM_FIFO_STATUS_REG_OFFSET 0x0001607c
+
+extern const ru_reg_rec QM_CM_RD_PD_FIFO_STATUS_REG;
+#define QM_CM_RD_PD_FIFO_STATUS_REG_OFFSET 0x00016080
+
+extern const ru_reg_rec QM_CM_WR_PD_FIFO_STATUS_REG;
+#define QM_CM_WR_PD_FIFO_STATUS_REG_OFFSET 0x00016084
+
+extern const ru_reg_rec QM_CM_COMMON_INPUT_FIFO_STATUS_REG;
+#define QM_CM_COMMON_INPUT_FIFO_STATUS_REG_OFFSET 0x00016088
+
+extern const ru_reg_rec QM_BB0_OUTPUT_FIFO_STATUS_REG;
+#define QM_BB0_OUTPUT_FIFO_STATUS_REG_OFFSET 0x0001608c
+
+extern const ru_reg_rec QM_BB1_OUTPUT_FIFO_STATUS_REG;
+#define QM_BB1_OUTPUT_FIFO_STATUS_REG_OFFSET 0x00016090
+
+extern const ru_reg_rec QM_BB1_INPUT_FIFO_STATUS_REG;
+#define QM_BB1_INPUT_FIFO_STATUS_REG_OFFSET 0x00016094
+
+extern const ru_reg_rec QM_EGRESS_DATA_FIFO_STATUS_REG;
+#define QM_EGRESS_DATA_FIFO_STATUS_REG_OFFSET 0x00016098
+
+extern const ru_reg_rec QM_EGRESS_RR_FIFO_STATUS_REG;
+#define QM_EGRESS_RR_FIFO_STATUS_REG_OFFSET 0x0001609c
+
+extern const ru_reg_rec QM_BB_ROUTE_OVR_REG;
+#define QM_BB_ROUTE_OVR_REG_OFFSET 0x000160a0
+
+#define QM_BB_ROUTE_OVR_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec QM_QM_INGRESS_STAT_REG;
+#define QM_QM_INGRESS_STAT_REG_OFFSET 0x000160b0
+
+extern const ru_reg_rec QM_QM_EGRESS_STAT_REG;
+#define QM_QM_EGRESS_STAT_REG_OFFSET 0x000160b4
+
+extern const ru_reg_rec QM_QM_CM_STAT_REG;
+#define QM_QM_CM_STAT_REG_OFFSET 0x000160b8
+
+extern const ru_reg_rec QM_QM_FPM_PREFETCH_STAT_REG;
+#define QM_QM_FPM_PREFETCH_STAT_REG_OFFSET 0x000160bc
+
+extern const ru_reg_rec QM_QM_CONNECT_ACK_COUNTER_REG;
+#define QM_QM_CONNECT_ACK_COUNTER_REG_OFFSET 0x000160c0
+
+extern const ru_reg_rec QM_QM_DDR_WR_REPLY_COUNTER_REG;
+#define QM_QM_DDR_WR_REPLY_COUNTER_REG_OFFSET 0x000160c4
+
+extern const ru_reg_rec QM_QM_DDR_PIPE_BYTE_COUNTER_REG;
+#define QM_QM_DDR_PIPE_BYTE_COUNTER_REG_OFFSET 0x000160c8
+
+extern const ru_reg_rec QM_QM_ABS_REQUEUE_VALID_COUNTER_REG;
+#define QM_QM_ABS_REQUEUE_VALID_COUNTER_REG_OFFSET 0x000160cc
+
+extern const ru_reg_rec QM_QM_ILLEGAL_PD_CAPTURE_REG;
+#define QM_QM_ILLEGAL_PD_CAPTURE_REG_OFFSET 0x000160d0
+
+#define QM_QM_ILLEGAL_PD_CAPTURE_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_QM_INGRESS_PROCESSED_PD_CAPTURE_REG;
+#define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_REG_OFFSET 0x000160e0
+
+#define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_QM_CM_PROCESSED_PD_CAPTURE_REG;
+#define QM_QM_CM_PROCESSED_PD_CAPTURE_REG_OFFSET 0x000160f0
+
+#define QM_QM_CM_PROCESSED_PD_CAPTURE_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_FPM_POOL_DROP_CNT_REG;
+#define QM_FPM_POOL_DROP_CNT_REG_OFFSET 0x00016100
+
+#define QM_FPM_POOL_DROP_CNT_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_FPM_GRP_DROP_CNT_REG;
+#define QM_FPM_GRP_DROP_CNT_REG_OFFSET 0x00016110
+
+#define QM_FPM_GRP_DROP_CNT_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec QM_FPM_BUFFER_RES_DROP_CNT_REG;
+#define QM_FPM_BUFFER_RES_DROP_CNT_REG_OFFSET 0x00016120
+
+extern const ru_reg_rec QM_PSRAM_EGRESS_CONG_DRP_CNT_REG;
+#define QM_PSRAM_EGRESS_CONG_DRP_CNT_REG_OFFSET 0x00016124
+
+extern const ru_reg_rec QM_BACKPRESSURE_REG;
+#define QM_BACKPRESSURE_REG_OFFSET 0x00016128
+
+extern const ru_reg_rec QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_REG;
+#define QM_GLOBAL_CFG2_BBHTX_FIFO_ADDR_REG_OFFSET 0x00016200
+
+extern const ru_reg_rec QM_DATA_REG;
+#define QM_DATA_REG_OFFSET 0x00020000
+
+#define QM_DATA_REG_RAM_CNT 0x000003ff
+
+extern const ru_reg_rec DQM_TOKEN_FIFO_TOKEN_FIFO_REG;
+#define DQM_TOKEN_FIFO_TOKEN_FIFO_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec DQM_MAX_ENTRIES_WORDS_REG;
+#define DQM_MAX_ENTRIES_WORDS_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec DQM_FPM_ADDR_REG;
+#define DQM_FPM_ADDR_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec DQM_IRQ_STS_REG;
+#define DQM_IRQ_STS_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec DQM_IRQ_MSK_REG;
+#define DQM_IRQ_MSK_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec DQM_BUF_SIZE_REG;
+#define DQM_BUF_SIZE_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec DQM_BUF_BASE_REG;
+#define DQM_BUF_BASE_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec DQM_TOKENS_USED_REG;
+#define DQM_TOKENS_USED_REG_OFFSET 0x00000030
+
+extern const ru_reg_rec DQM_NUM_PUSHED_REG;
+#define DQM_NUM_PUSHED_REG_OFFSET 0x00000034
+
+extern const ru_reg_rec DQM_NUM_POPPED_REG;
+#define DQM_NUM_POPPED_REG_OFFSET 0x00000038
+
+extern const ru_reg_rec DQM_DIAG_SEL_REG;
+#define DQM_DIAG_SEL_REG_OFFSET 0x0000003c
+
+extern const ru_reg_rec DQM_DIAG_DATA_REG;
+#define DQM_DIAG_DATA_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec DQM_IRQ_TST_REG;
+#define DQM_IRQ_TST_REG_OFFSET 0x00000044
+
+extern const ru_reg_rec DQM_TOKEN_FIFO_STATUS_REG;
+#define DQM_TOKEN_FIFO_STATUS_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec DQM_NUM_POPPED_NO_COMMIT_REG;
+#define DQM_NUM_POPPED_NO_COMMIT_REG_OFFSET 0x0000008c
+
+extern const ru_reg_rec DQM_STATUS_REG;
+#define DQM_STATUS_REG_OFFSET 0x000007cc
+
+#define DQM_STATUS_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_HEAD_PTR_REG;
+#define DQM_HEAD_PTR_REG_OFFSET 0x00000fcc
+
+#define DQM_HEAD_PTR_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_TAIL_PTR_REG;
+#define DQM_TAIL_PTR_REG_OFFSET 0x00000fd0
+
+#define DQM_TAIL_PTR_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_DQMOL_SIZE_REG;
+#define DQM_DQMOL_SIZE_REG_OFFSET 0x00001fcc
+
+#define DQM_DQMOL_SIZE_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_DQMOL_CFGA_REG;
+#define DQM_DQMOL_CFGA_REG_OFFSET 0x00001fd0
+
+#define DQM_DQMOL_CFGA_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_DQMOL_CFGB_REG;
+#define DQM_DQMOL_CFGB_REG_OFFSET 0x00001fd4
+
+#define DQM_DQMOL_CFGB_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_DQMOL_PUSHTOKEN_REG;
+#define DQM_DQMOL_PUSHTOKEN_REG_OFFSET 0x00001fdc
+
+#define DQM_DQMOL_PUSHTOKEN_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_DQMOL_PUSHTOKENNEXT_REG;
+#define DQM_DQMOL_PUSHTOKENNEXT_REG_OFFSET 0x00001fe0
+
+#define DQM_DQMOL_PUSHTOKENNEXT_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_DQMOL_POPTOKEN_REG;
+#define DQM_DQMOL_POPTOKEN_REG_OFFSET 0x00001fe4
+
+#define DQM_DQMOL_POPTOKEN_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_DQMOL_POPTOKENNEXT_REG;
+#define DQM_DQMOL_POPTOKENNEXT_REG_OFFSET 0x00001fe8
+
+#define DQM_DQMOL_POPTOKENNEXT_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_WORD0_REG;
+#define DQM_WORD0_REG_OFFSET 0x00004fcc
+
+#define DQM_WORD0_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_WORD1_REG;
+#define DQM_WORD1_REG_OFFSET 0x00004fd0
+
+#define DQM_WORD1_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_WORD2_REG;
+#define DQM_WORD2_REG_OFFSET 0x00004fd4
+
+#define DQM_WORD2_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec DQM_QueueSharedMem_qsmdata_REG;
+#define DQM_QueueSharedMem_qsmdata_REG_OFFSET 0x0001ffcc
+
+#define DQM_QueueSharedMem_qsmdata_REG_RAM_CNT 0x00003c00
+
+extern const ru_reg_rec FPM_FPM_CTL_REG;
+#define FPM_FPM_CTL_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec FPM_FPM_CFG1_REG;
+#define FPM_FPM_CFG1_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec FPM_FPM_WEIGHT_REG;
+#define FPM_FPM_WEIGHT_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec FPM_FPM_BB_CFG_REG;
+#define FPM_FPM_BB_CFG_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec FPM_POOL1_INTR_MSK_REG;
+#define FPM_POOL1_INTR_MSK_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec FPM_POOL1_INTR_STS_REG;
+#define FPM_POOL1_INTR_STS_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec FPM_POOL1_STALL_MSK_REG;
+#define FPM_POOL1_STALL_MSK_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec FPM_POOL2_INTR_MSK_REG;
+#define FPM_POOL2_INTR_MSK_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec FPM_POOL2_INTR_STS_REG;
+#define FPM_POOL2_INTR_STS_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec FPM_POOL2_STALL_MSK_REG;
+#define FPM_POOL2_STALL_MSK_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec FPM_POOL1_CFG1_REG;
+#define FPM_POOL1_CFG1_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec FPM_POOL1_CFG2_REG;
+#define FPM_POOL1_CFG2_REG_OFFSET 0x00000044
+
+extern const ru_reg_rec FPM_POOL1_CFG3_REG;
+#define FPM_POOL1_CFG3_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec FPM_POOL1_STAT1_REG;
+#define FPM_POOL1_STAT1_REG_OFFSET 0x00000050
+
+extern const ru_reg_rec FPM_POOL1_STAT2_REG;
+#define FPM_POOL1_STAT2_REG_OFFSET 0x00000054
+
+extern const ru_reg_rec FPM_POOL1_STAT3_REG;
+#define FPM_POOL1_STAT3_REG_OFFSET 0x00000058
+
+extern const ru_reg_rec FPM_POOL1_STAT4_REG;
+#define FPM_POOL1_STAT4_REG_OFFSET 0x0000005c
+
+extern const ru_reg_rec FPM_POOL1_STAT5_REG;
+#define FPM_POOL1_STAT5_REG_OFFSET 0x00000060
+
+extern const ru_reg_rec FPM_POOL1_STAT6_REG;
+#define FPM_POOL1_STAT6_REG_OFFSET 0x00000064
+
+extern const ru_reg_rec FPM_POOL1_STAT7_REG;
+#define FPM_POOL1_STAT7_REG_OFFSET 0x00000068
+
+extern const ru_reg_rec FPM_POOL1_STAT8_REG;
+#define FPM_POOL1_STAT8_REG_OFFSET 0x0000006c
+
+extern const ru_reg_rec FPM_POOL2_STAT1_REG;
+#define FPM_POOL2_STAT1_REG_OFFSET 0x00000070
+
+extern const ru_reg_rec FPM_POOL2_STAT2_REG;
+#define FPM_POOL2_STAT2_REG_OFFSET 0x00000074
+
+extern const ru_reg_rec FPM_POOL2_STAT3_REG;
+#define FPM_POOL2_STAT3_REG_OFFSET 0x00000078
+
+extern const ru_reg_rec FPM_POOL2_STAT4_REG;
+#define FPM_POOL2_STAT4_REG_OFFSET 0x0000007c
+
+extern const ru_reg_rec FPM_POOL2_STAT5_REG;
+#define FPM_POOL2_STAT5_REG_OFFSET 0x00000080
+
+extern const ru_reg_rec FPM_POOL2_STAT6_REG;
+#define FPM_POOL2_STAT6_REG_OFFSET 0x00000084
+
+extern const ru_reg_rec FPM_POOL2_STAT7_REG;
+#define FPM_POOL2_STAT7_REG_OFFSET 0x00000088
+
+extern const ru_reg_rec FPM_POOL2_STAT8_REG;
+#define FPM_POOL2_STAT8_REG_OFFSET 0x0000008c
+
+extern const ru_reg_rec FPM_POOL1_XON_XOFF_CFG_REG;
+#define FPM_POOL1_XON_XOFF_CFG_REG_OFFSET 0x000000c0
+
+extern const ru_reg_rec FPM_FPM_NOT_EMPTY_CFG_REG;
+#define FPM_FPM_NOT_EMPTY_CFG_REG_OFFSET 0x000000d0
+
+extern const ru_reg_rec FPM_MEM_CTL_REG;
+#define FPM_MEM_CTL_REG_OFFSET 0x00000100
+
+extern const ru_reg_rec FPM_MEM_DATA1_REG;
+#define FPM_MEM_DATA1_REG_OFFSET 0x00000104
+
+extern const ru_reg_rec FPM_MEM_DATA2_REG;
+#define FPM_MEM_DATA2_REG_OFFSET 0x00000108
+
+extern const ru_reg_rec FPM_TOKEN_RECOVER_CTL_REG;
+#define FPM_TOKEN_RECOVER_CTL_REG_OFFSET 0x00000130
+
+extern const ru_reg_rec FPM_SHORT_AGING_TIMER_REG;
+#define FPM_SHORT_AGING_TIMER_REG_OFFSET 0x00000134
+
+extern const ru_reg_rec FPM_LONG_AGING_TIMER_REG;
+#define FPM_LONG_AGING_TIMER_REG_OFFSET 0x00000138
+
+extern const ru_reg_rec FPM_CACHE_RECYCLE_TIMER_REG;
+#define FPM_CACHE_RECYCLE_TIMER_REG_OFFSET 0x0000013c
+
+extern const ru_reg_rec FPM_EXPIRED_TOKEN_COUNT_POOL1_REG;
+#define FPM_EXPIRED_TOKEN_COUNT_POOL1_REG_OFFSET 0x00000140
+
+extern const ru_reg_rec FPM_RECOVERED_TOKEN_COUNT_POOL1_REG;
+#define FPM_RECOVERED_TOKEN_COUNT_POOL1_REG_OFFSET 0x00000144
+
+extern const ru_reg_rec FPM_EXPIRED_TOKEN_COUNT_POOL2_REG;
+#define FPM_EXPIRED_TOKEN_COUNT_POOL2_REG_OFFSET 0x00000148
+
+extern const ru_reg_rec FPM_RECOVERED_TOKEN_COUNT_POOL2_REG;
+#define FPM_RECOVERED_TOKEN_COUNT_POOL2_REG_OFFSET 0x0000014c
+
+extern const ru_reg_rec FPM_TOKEN_RECOVER_START_END_POOL1_REG;
+#define FPM_TOKEN_RECOVER_START_END_POOL1_REG_OFFSET 0x00000150
+
+extern const ru_reg_rec FPM_TOKEN_RECOVER_START_END_POOL2_REG;
+#define FPM_TOKEN_RECOVER_START_END_POOL2_REG_OFFSET 0x00000154
+
+extern const ru_reg_rec FPM_POOL1_ALLOC_DEALLOC_REG;
+#define FPM_POOL1_ALLOC_DEALLOC_REG_OFFSET 0x00000400
+
+extern const ru_reg_rec FPM_POOL2_ALLOC_DEALLOC_REG;
+#define FPM_POOL2_ALLOC_DEALLOC_REG_OFFSET 0x00000408
+
+extern const ru_reg_rec FPM_POOL3_ALLOC_DEALLOC_REG;
+#define FPM_POOL3_ALLOC_DEALLOC_REG_OFFSET 0x00000410
+
+extern const ru_reg_rec FPM_POOL4_ALLOC_DEALLOC_REG;
+#define FPM_POOL4_ALLOC_DEALLOC_REG_OFFSET 0x00000418
+
+extern const ru_reg_rec FPM_SPARE_REG;
+#define FPM_SPARE_REG_OFFSET 0x00000420
+
+extern const ru_reg_rec FPM_POOL_MULTI_REG;
+#define FPM_POOL_MULTI_REG_OFFSET 0x00000424
+
+extern const ru_reg_rec FPM_FPM_BB_FORCE_REG;
+#define FPM_FPM_BB_FORCE_REG_OFFSET 0x00030000
+
+extern const ru_reg_rec FPM_FPM_BB_FORCED_CTRL_REG;
+#define FPM_FPM_BB_FORCED_CTRL_REG_OFFSET 0x00030004
+
+extern const ru_reg_rec FPM_FPM_BB_FORCED_ADDR_REG;
+#define FPM_FPM_BB_FORCED_ADDR_REG_OFFSET 0x00030008
+
+extern const ru_reg_rec FPM_FPM_BB_FORCED_DATA_REG;
+#define FPM_FPM_BB_FORCED_DATA_REG_OFFSET 0x0003000c
+
+extern const ru_reg_rec FPM_FPM_BB_DECODE_CFG_REG;
+#define FPM_FPM_BB_DECODE_CFG_REG_OFFSET 0x00030010
+
+extern const ru_reg_rec FPM_FPM_BB_DBG_CFG_REG;
+#define FPM_FPM_BB_DBG_CFG_REG_OFFSET 0x00030014
+
+extern const ru_reg_rec FPM_FPM_BB_DBG_RXFIFO_STS_REG;
+#define FPM_FPM_BB_DBG_RXFIFO_STS_REG_OFFSET 0x00030018
+
+extern const ru_reg_rec FPM_FPM_BB_DBG_TXFIFO_STS_REG;
+#define FPM_FPM_BB_DBG_TXFIFO_STS_REG_OFFSET 0x0003001c
+
+extern const ru_reg_rec FPM_FPM_BB_DBG_RXFIFO_DATA1_REG;
+#define FPM_FPM_BB_DBG_RXFIFO_DATA1_REG_OFFSET 0x00030020
+
+extern const ru_reg_rec FPM_FPM_BB_DBG_RXFIFO_DATA2_REG;
+#define FPM_FPM_BB_DBG_RXFIFO_DATA2_REG_OFFSET 0x00030024
+
+extern const ru_reg_rec FPM_FPM_BB_DBG_TXFIFO_DATA1_REG;
+#define FPM_FPM_BB_DBG_TXFIFO_DATA1_REG_OFFSET 0x00030028
+
+extern const ru_reg_rec FPM_FPM_BB_DBG_TXFIFO_DATA2_REG;
+#define FPM_FPM_BB_DBG_TXFIFO_DATA2_REG_OFFSET 0x0003002c
+
+extern const ru_reg_rec FPM_FPM_BB_DBG_TXFIFO_DATA3_REG;
+#define FPM_FPM_BB_DBG_TXFIFO_DATA3_REG_OFFSET 0x00030030
+
+extern const ru_reg_rec RNR_MEM_HIGH_REG;
+#define RNR_MEM_HIGH_REG_OFFSET 0x00000000
+
+#define RNR_MEM_HIGH_REG_RAM_CNT 0x000007ff
+
+extern const ru_reg_rec RNR_MEM_LOW_REG;
+#define RNR_MEM_LOW_REG_OFFSET 0x00000004
+
+#define RNR_MEM_LOW_REG_RAM_CNT 0x000007ff
+
+extern const ru_reg_rec RNR_INST_MEM_ENTRY_REG;
+#define RNR_INST_MEM_ENTRY_REG_OFFSET 0x00000000
+
+#define RNR_INST_MEM_ENTRY_REG_RAM_CNT 0x00001fff
+
+extern const ru_reg_rec RNR_CNTXT_MEM_ENTRY_REG;
+#define RNR_CNTXT_MEM_ENTRY_REG_OFFSET 0x00000000
+
+#define RNR_CNTXT_MEM_ENTRY_REG_RAM_CNT 0x000001ff
+
+extern const ru_reg_rec RNR_PRED_MEM_ENTRY_REG;
+#define RNR_PRED_MEM_ENTRY_REG_OFFSET 0x00000000
+
+#define RNR_PRED_MEM_ENTRY_REG_RAM_CNT 0x000001ff
+
+extern const ru_reg_rec RNR_REGS_CFG_GLOBAL_CTRL_REG;
+#define RNR_REGS_CFG_GLOBAL_CTRL_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec RNR_REGS_CFG_CPU_WAKEUP_REG;
+#define RNR_REGS_CFG_CPU_WAKEUP_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec RNR_REGS_CFG_INT_CTRL_REG;
+#define RNR_REGS_CFG_INT_CTRL_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec RNR_REGS_CFG_INT_MASK_REG;
+#define RNR_REGS_CFG_INT_MASK_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec RNR_REGS_CFG_GEN_CFG_REG;
+#define RNR_REGS_CFG_GEN_CFG_REG_OFFSET 0x00000030
+
+extern const ru_reg_rec RNR_REGS_CFG_CAM_CFG_REG;
+#define RNR_REGS_CFG_CAM_CFG_REG_OFFSET 0x00000034
+
+extern const ru_reg_rec RNR_REGS_CFG_DDR_CFG_REG;
+#define RNR_REGS_CFG_DDR_CFG_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec RNR_REGS_CFG_PSRAM_CFG_REG;
+#define RNR_REGS_CFG_PSRAM_CFG_REG_OFFSET 0x00000044
+
+extern const ru_reg_rec RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_REG;
+#define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec RNR_REGS_CFG_SCH_CFG_REG;
+#define RNR_REGS_CFG_SCH_CFG_REG_OFFSET 0x0000004c
+
+extern const ru_reg_rec RNR_REGS_CFG_BKPT_CFG_REG;
+#define RNR_REGS_CFG_BKPT_CFG_REG_OFFSET 0x00000050
+
+extern const ru_reg_rec RNR_REGS_CFG_BKPT_IMM_REG;
+#define RNR_REGS_CFG_BKPT_IMM_REG_OFFSET 0x00000054
+
+extern const ru_reg_rec RNR_REGS_CFG_BKPT_STS_REG;
+#define RNR_REGS_CFG_BKPT_STS_REG_OFFSET 0x00000058
+
+extern const ru_reg_rec RNR_REGS_CFG_PC_STS_REG;
+#define RNR_REGS_CFG_PC_STS_REG_OFFSET 0x0000005c
+
+extern const ru_reg_rec RNR_REGS_CFG_EXT_ACC_CFG_REG;
+#define RNR_REGS_CFG_EXT_ACC_CFG_REG_OFFSET 0x00000060
+
+extern const ru_reg_rec RNR_REGS_CFG_FIT_FAIL_CFG_REG;
+#define RNR_REGS_CFG_FIT_FAIL_CFG_REG_OFFSET 0x00000064
+
+extern const ru_reg_rec RNR_REGS_CFG_STALL_CNT1_REG;
+#define RNR_REGS_CFG_STALL_CNT1_REG_OFFSET 0x000000a0
+
+extern const ru_reg_rec RNR_REGS_CFG_STALL_CNT2_REG;
+#define RNR_REGS_CFG_STALL_CNT2_REG_OFFSET 0x000000a4
+
+extern const ru_reg_rec RNR_REGS_CFG_STALL_CNT3_REG;
+#define RNR_REGS_CFG_STALL_CNT3_REG_OFFSET 0x000000a8
+
+extern const ru_reg_rec RNR_REGS_CFG_STALL_CNT4_REG;
+#define RNR_REGS_CFG_STALL_CNT4_REG_OFFSET 0x000000ac
+
+extern const ru_reg_rec RNR_REGS_CFG_PROFILING_STS_REG;
+#define RNR_REGS_CFG_PROFILING_STS_REG_OFFSET 0x000000b0
+
+extern const ru_reg_rec RNR_REGS_CFG_PROFILING_CFG_0_REG;
+#define RNR_REGS_CFG_PROFILING_CFG_0_REG_OFFSET 0x000000b4
+
+extern const ru_reg_rec RNR_REGS_CFG_PROFILING_CFG_1_REG;
+#define RNR_REGS_CFG_PROFILING_CFG_1_REG_OFFSET 0x000000b8
+
+extern const ru_reg_rec RNR_REGS_CFG_PROFILING_COUNTER_REG;
+#define RNR_REGS_CFG_PROFILING_COUNTER_REG_OFFSET 0x000000bc
+
+extern const ru_reg_rec RNR_REGS_CFG_PROFILING_CFG_2_REG;
+#define RNR_REGS_CFG_PROFILING_CFG_2_REG_OFFSET 0x000000c0
+
+extern const ru_reg_rec RNR_REGS_CFG_EXEC_CMDS_CNT_REG;
+#define RNR_REGS_CFG_EXEC_CMDS_CNT_REG_OFFSET 0x000000c4
+
+extern const ru_reg_rec RNR_REGS_CFG_IDLE_CNT1_REG;
+#define RNR_REGS_CFG_IDLE_CNT1_REG_OFFSET 0x000000c8
+
+extern const ru_reg_rec RNR_REGS_CFG_JMP_CNT_REG;
+#define RNR_REGS_CFG_JMP_CNT_REG_OFFSET 0x000000cc
+
+extern const ru_reg_rec RNR_REGS_CFG_METAL_FIX_REG_REG;
+#define RNR_REGS_CFG_METAL_FIX_REG_REG_OFFSET 0x000000f0
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_REG_OFFSET 0x0000002c
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_REG_OFFSET 0x00000038
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_REG_OFFSET 0x0000003c
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_REG_OFFSET 0x00000044
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_REG_OFFSET 0x0000004c
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_REG_OFFSET 0x00000050
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_REG_OFFSET 0x00000054
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_REG_OFFSET 0x00000058
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_REG_OFFSET 0x0000005c
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_REG_OFFSET 0x00000060
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_REG_OFFSET 0x00000064
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_REG_OFFSET 0x00000068
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_REG_OFFSET 0x00000070
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_REG_OFFSET 0x00000074
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_REG_OFFSET 0x00000078
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_REG_OFFSET 0x0000007c
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_REG_OFFSET 0x00000080
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_REG_OFFSET 0x00000084
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_REG_OFFSET 0x00000088
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_REG_OFFSET 0x0000008c
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_REG_OFFSET 0x00000090
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_REG_OFFSET 0x00000094
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_REG_OFFSET 0x00000098
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_REG_OFFSET 0x0000009c
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_REG_OFFSET 0x000000a0
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_REG_OFFSET 0x000000a4
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_REG_OFFSET 0x000000a8
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_REG_OFFSET 0x000000ac
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_REG_OFFSET 0x000000b0
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_REG_OFFSET 0x000000b4
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_REG_OFFSET 0x000000c8
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_REG_OFFSET 0x000000cc
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_REG_OFFSET 0x000000d0
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_REG_OFFSET 0x000000d4
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_REG_OFFSET 0x000000d8
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_REG_OFFSET 0x000000dc
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_REG_OFFSET 0x000000e0
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_REG_OFFSET 0x000000e4
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_REG_OFFSET 0x000000e8
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DOS_ATTACK_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_DOS_ATTACK_REG_OFFSET 0x000000ec
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_ICMP_MAX_SIZE_REG_OFFSET 0x000000f0
+
+extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_REG;
+#define RNR_QUAD_PARSER_CORE_CONFIGURATION_KEY_CFG_REG_OFFSET 0x000000f8
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_REG_OFFSET 0x00000100
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_REG;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_REG_OFFSET 0x00000104
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_REG;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_REG_OFFSET 0x00000108
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_REG;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_REG_OFFSET 0x0000010c
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_REG;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_REG_OFFSET 0x00000110
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_REG;
+#define RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_REG_OFFSET 0x00000114
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_REG;
+#define RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_REG_OFFSET 0x00000118
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_REG;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_REG_OFFSET 0x0000011c
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_REG;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_REG_OFFSET 0x00000120
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_REG;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_REG_OFFSET 0x00000124
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_REG;
+#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_REG_OFFSET 0x00000128
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_REG;
+#define RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_REG_OFFSET 0x0000012c
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_REG;
+#define RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_REG_OFFSET 0x00000130
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_REG_OFFSET 0x00000134
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_REG_OFFSET 0x00000140
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_REG_OFFSET 0x00000144
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_REG_OFFSET 0x00000148
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_REG_OFFSET 0x0000014c
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_REG_OFFSET 0x00000150
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_REG_OFFSET 0x00000154
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_REG_OFFSET 0x00000158
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_REG_OFFSET 0x0000015c
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_REG_OFFSET 0x00000160
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_REG;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_REG_OFFSET 0x00000170
+
+extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_REG;
+#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_REG_OFFSET 0x00000174
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_FIFO_CONFIG_REG;
+#define RNR_QUAD_DEBUG_FIFO_CONFIG_REG_OFFSET 0x00000200
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_REG;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_REG_OFFSET 0x00000204
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_REG;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_REG_OFFSET 0x00000208
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_REG;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_REG_OFFSET 0x0000020c
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_REG;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_REG_OFFSET 0x00000210
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_REG;
+#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_REG_OFFSET 0x00000214
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_REG;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_REG_OFFSET 0x00000220
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_REG;
+#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_REG_OFFSET 0x00000224
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_REG;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_REG_OFFSET 0x00000228
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_REG;
+#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_REG_OFFSET 0x0000022c
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_REG;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_REG_OFFSET 0x00000230
+
+extern const ru_reg_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_REG;
+#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_REG_OFFSET 0x00000234
+
+extern const ru_reg_rec RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_REG;
+#define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_REG_OFFSET 0x00000400
+
+#define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_REG_RAM_CNT 0x00000023
+
+extern const ru_reg_rec RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_REG;
+#define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_REG_OFFSET 0x00000600
+
+#define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_REG;
+#define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_REG_OFFSET 0x00000640
+
+#define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REG;
+#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec DSPTCHR_REORDER_CFG_VQ_EN_REG;
+#define DSPTCHR_REORDER_CFG_VQ_EN_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec DSPTCHR_REORDER_CFG_BB_CFG_REG;
+#define DSPTCHR_REORDER_CFG_BB_CFG_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_REG;
+#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec DSPTCHR_CONGESTION_INGRS_CONGSTN_REG;
+#define DSPTCHR_CONGESTION_INGRS_CONGSTN_REG_OFFSET 0x00000080
+
+#define DSPTCHR_CONGESTION_INGRS_CONGSTN_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_CONGESTION_EGRS_CONGSTN_REG;
+#define DSPTCHR_CONGESTION_EGRS_CONGSTN_REG_OFFSET 0x00000100
+
+#define DSPTCHR_CONGESTION_EGRS_CONGSTN_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_REG;
+#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_REG_OFFSET 0x00000180
+
+extern const ru_reg_rec DSPTCHR_CONGESTION_GLBL_CONGSTN_REG;
+#define DSPTCHR_CONGESTION_GLBL_CONGSTN_REG_OFFSET 0x00000184
+
+extern const ru_reg_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_REG;
+#define DSPTCHR_CONGESTION_CONGSTN_STATUS_REG_OFFSET 0x00000188
+
+extern const ru_reg_rec DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_REG;
+#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_REG_OFFSET 0x0000018c
+
+extern const ru_reg_rec DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_REG;
+#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_REG_OFFSET 0x00000190
+
+extern const ru_reg_rec DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_REG;
+#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_REG_OFFSET 0x00000194
+
+extern const ru_reg_rec DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_REG;
+#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_REG_OFFSET 0x00000198
+
+extern const ru_reg_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_REG;
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_REG_OFFSET 0x00000280
+
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_REG;
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_REG_OFFSET 0x00000300
+
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_REG;
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_REG_OFFSET 0x00000380
+
+#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_QUEUE_MAPPING_CRDT_CFG_REG;
+#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_REG_OFFSET 0x00000400
+
+#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_REG;
+#define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_REG_OFFSET 0x00000480
+
+#define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_REG;
+#define DSPTCHR_QUEUE_MAPPING_Q_DEST_REG_OFFSET 0x000004c0
+
+extern const ru_reg_rec DSPTCHR_POOL_SIZES_CMN_POOL_LMT_REG;
+#define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_REG_OFFSET 0x000004d0
+
+extern const ru_reg_rec DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_REG;
+#define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_REG_OFFSET 0x000004d4
+
+extern const ru_reg_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_REG;
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_REG_OFFSET 0x000004d8
+
+extern const ru_reg_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_REG;
+#define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_REG_OFFSET 0x000004dc
+
+extern const ru_reg_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_REG;
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_REG_OFFSET 0x000004e0
+
+extern const ru_reg_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_REG;
+#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_REG_OFFSET 0x000004e4
+
+extern const ru_reg_rec DSPTCHR_POOL_SIZES_RNR_POOL_LMT_REG;
+#define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_REG_OFFSET 0x000004e8
+
+extern const ru_reg_rec DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_REG;
+#define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_REG_OFFSET 0x000004ec
+
+extern const ru_reg_rec DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_REG;
+#define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_REG_OFFSET 0x000004f0
+
+extern const ru_reg_rec DSPTCHR_MASK_MSK_TSK_255_0_REG;
+#define DSPTCHR_MASK_MSK_TSK_255_0_REG_OFFSET 0x00000500
+
+#define DSPTCHR_MASK_MSK_TSK_255_0_REG_RAM_CNT 0x0000003f
+
+extern const ru_reg_rec DSPTCHR_MASK_MSK_Q_REG;
+#define DSPTCHR_MASK_MSK_Q_REG_OFFSET 0x00000600
+
+#define DSPTCHR_MASK_MSK_Q_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DSPTCHR_MASK_DLY_Q_REG;
+#define DSPTCHR_MASK_DLY_Q_REG_OFFSET 0x00000620
+
+extern const ru_reg_rec DSPTCHR_MASK_NON_DLY_Q_REG;
+#define DSPTCHR_MASK_NON_DLY_Q_REG_OFFSET 0x00000624
+
+extern const ru_reg_rec DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_REG;
+#define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_REG_OFFSET 0x00000630
+
+extern const ru_reg_rec DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_REG;
+#define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_REG_OFFSET 0x00000634
+
+extern const ru_reg_rec DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_REG;
+#define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_REG_OFFSET 0x00000638
+
+extern const ru_reg_rec DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_REG;
+#define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_REG_OFFSET 0x00000680
+
+#define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_REG;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_REG_OFFSET 0x00000770
+
+extern const ru_reg_rec DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_REG;
+#define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_REG_OFFSET 0x00000774
+
+extern const ru_reg_rec DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_REG;
+#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_REG_OFFSET 0x00000780
+
+#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_REG;
+#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_REG_OFFSET 0x00000800
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_LB_CFG_REG;
+#define DSPTCHR_LOAD_BALANCING_LB_CFG_REG_OFFSET 0x00000850
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_REG;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_REG_OFFSET 0x00000860
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_REG;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_REG_OFFSET 0x00000864
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_REG;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_REG_OFFSET 0x00000868
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_REG;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_REG_OFFSET 0x0000086c
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_REG;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_REG_OFFSET 0x00000870
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_REG;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_REG_OFFSET 0x00000874
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_REG;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_REG_OFFSET 0x00000878
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_REG;
+#define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_REG_OFFSET 0x0000087c
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_REG;
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_REG_OFFSET 0x00000900
+
+#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_REG;
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_REG_OFFSET 0x00000980
+
+extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_REG;
+#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_REG_OFFSET 0x00000984
+
+extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_REG;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_REG_OFFSET 0x00000990
+
+extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_REG;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_REG_OFFSET 0x00000994
+
+extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_REG;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_REG_OFFSET 0x00000998
+
+extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_REG;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_REG_OFFSET 0x0000099c
+
+extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_REG;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_REG_OFFSET 0x000009a0
+
+extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_REG;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_REG_OFFSET 0x000009a4
+
+extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_REG;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_REG_OFFSET 0x000009a8
+
+extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_REG;
+#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_REG_OFFSET 0x000009ac
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_REG;
+#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_REG_OFFSET 0x000009b0
+
+extern const ru_reg_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_REG;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_REG_OFFSET 0x000009b4
+
+extern const ru_reg_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_REG;
+#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_REG_OFFSET 0x000009b8
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_BUS_CNTRL_REG;
+#define DSPTCHR_DEBUG_DBG_BUS_CNTRL_REG_OFFSET 0x000009bc
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_0_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_0_REG_OFFSET 0x000009c0
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_1_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_1_REG_OFFSET 0x000009c4
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_2_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_2_REG_OFFSET 0x000009c8
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_3_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_3_REG_OFFSET 0x000009cc
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_4_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_4_REG_OFFSET 0x000009d0
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_5_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_5_REG_OFFSET 0x000009d4
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_6_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_6_REG_OFFSET 0x000009d8
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_7_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_7_REG_OFFSET 0x000009dc
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_8_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_8_REG_OFFSET 0x000009e0
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_9_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_9_REG_OFFSET 0x000009e4
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_10_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_10_REG_OFFSET 0x000009e8
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_11_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_11_REG_OFFSET 0x000009ec
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_12_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_12_REG_OFFSET 0x000009f0
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_13_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_13_REG_OFFSET 0x000009f4
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_14_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_14_REG_OFFSET 0x000009f8
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_15_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_15_REG_OFFSET 0x000009fc
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_16_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_16_REG_OFFSET 0x00000a00
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_17_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_17_REG_OFFSET 0x00000a04
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_18_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_18_REG_OFFSET 0x00000a08
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_19_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_19_REG_OFFSET 0x00000a0c
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_20_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_20_REG_OFFSET 0x00000a10
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_21_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_21_REG_OFFSET 0x00000a14
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_22_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_22_REG_OFFSET 0x00000a18
+
+extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_23_REG;
+#define DSPTCHR_DEBUG_DBG_VEC_23_REG_OFFSET 0x00000a1c
+
+extern const ru_reg_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_REG;
+#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_REG_OFFSET 0x00000a70
+
+extern const ru_reg_rec DSPTCHR_DEBUG_STATISTICS_DBG_CNT_REG;
+#define DSPTCHR_DEBUG_STATISTICS_DBG_CNT_REG_OFFSET 0x00000a80
+
+#define DSPTCHR_DEBUG_STATISTICS_DBG_CNT_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_QDES_HEAD_REG;
+#define DSPTCHR_QDES_HEAD_REG_OFFSET 0x00002000
+
+#define DSPTCHR_QDES_HEAD_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_QDES_BFOUT_REG;
+#define DSPTCHR_QDES_BFOUT_REG_OFFSET 0x00002004
+
+#define DSPTCHR_QDES_BFOUT_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_QDES_BUFIN_REG;
+#define DSPTCHR_QDES_BUFIN_REG_OFFSET 0x00002008
+
+#define DSPTCHR_QDES_BUFIN_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_QDES_TAIL_REG;
+#define DSPTCHR_QDES_TAIL_REG_OFFSET 0x0000200c
+
+#define DSPTCHR_QDES_TAIL_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_QDES_FBDNULL_REG;
+#define DSPTCHR_QDES_FBDNULL_REG_OFFSET 0x00002010
+
+#define DSPTCHR_QDES_FBDNULL_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_QDES_NULLBD_REG;
+#define DSPTCHR_QDES_NULLBD_REG_OFFSET 0x00002014
+
+#define DSPTCHR_QDES_NULLBD_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_QDES_BUFAVAIL_REG;
+#define DSPTCHR_QDES_BUFAVAIL_REG_OFFSET 0x00002018
+
+#define DSPTCHR_QDES_BUFAVAIL_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_QDES_REG_Q_HEAD_REG;
+#define DSPTCHR_QDES_REG_Q_HEAD_REG_OFFSET 0x00002600
+
+#define DSPTCHR_QDES_REG_Q_HEAD_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec DSPTCHR_QDES_REG_VIQ_HEAD_VLD_REG;
+#define DSPTCHR_QDES_REG_VIQ_HEAD_VLD_REG_OFFSET 0x00002680
+
+extern const ru_reg_rec DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_REG;
+#define DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_REG_OFFSET 0x00002684
+
+extern const ru_reg_rec DSPTCHR_QDES_REG_VEQ_HEAD_VLD_REG;
+#define DSPTCHR_QDES_REG_VEQ_HEAD_VLD_REG_OFFSET 0x00002688
+
+extern const ru_reg_rec DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_REG;
+#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_REG_OFFSET 0x0000268c
+
+extern const ru_reg_rec DSPTCHR_FLLDES_HEAD_REG;
+#define DSPTCHR_FLLDES_HEAD_REG_OFFSET 0x00002700
+
+extern const ru_reg_rec DSPTCHR_FLLDES_BFOUT_REG;
+#define DSPTCHR_FLLDES_BFOUT_REG_OFFSET 0x00002704
+
+extern const ru_reg_rec DSPTCHR_FLLDES_BFIN_REG;
+#define DSPTCHR_FLLDES_BFIN_REG_OFFSET 0x00002708
+
+extern const ru_reg_rec DSPTCHR_FLLDES_TAIL_REG;
+#define DSPTCHR_FLLDES_TAIL_REG_OFFSET 0x0000270c
+
+extern const ru_reg_rec DSPTCHR_FLLDES_FLLDROP_REG;
+#define DSPTCHR_FLLDES_FLLDROP_REG_OFFSET 0x00002710
+
+extern const ru_reg_rec DSPTCHR_FLLDES_LTINT_REG;
+#define DSPTCHR_FLLDES_LTINT_REG_OFFSET 0x00002714
+
+extern const ru_reg_rec DSPTCHR_FLLDES_BUFAVAIL_REG;
+#define DSPTCHR_FLLDES_BUFAVAIL_REG_OFFSET 0x00002720
+
+extern const ru_reg_rec DSPTCHR_FLLDES_FREEMIN_REG;
+#define DSPTCHR_FLLDES_FREEMIN_REG_OFFSET 0x00002724
+
+extern const ru_reg_rec DSPTCHR_BDRAM_NEXT_DATA_REG;
+#define DSPTCHR_BDRAM_NEXT_DATA_REG_OFFSET 0x00003000
+
+#define DSPTCHR_BDRAM_NEXT_DATA_REG_RAM_CNT 0x000003ff
+
+extern const ru_reg_rec DSPTCHR_BDRAM_PREV_DATA_REG;
+#define DSPTCHR_BDRAM_PREV_DATA_REG_OFFSET 0x00004000
+
+#define DSPTCHR_BDRAM_PREV_DATA_REG_RAM_CNT 0x000003ff
+
+extern const ru_reg_rec DSPTCHR_PDRAM_DATA_REG;
+#define DSPTCHR_PDRAM_DATA_REG_OFFSET 0x00008000
+
+#define DSPTCHR_PDRAM_DATA_REG_RAM_CNT 0x00000fff
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_REG_OFFSET 0x00000010
+
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_REG_OFFSET 0x00000018
+
+#define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_REG_OFFSET 0x0000002c
+
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_REG_OFFSET 0x00000034
+
+#define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_REG_OFFSET 0x0000003c
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_REG_OFFSET 0x00000044
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_REG_OFFSET 0x000000a0
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REG_OFFSET 0x000000b0
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_REG_OFFSET 0x000000b4
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_REG_OFFSET 0x000000b8
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_GPR_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_GPR_REG_OFFSET 0x000000bc
+
+extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DS_DMA_SUP_REG;
+#define BBH_TX_COMMON_CONFIGURATIONS_DS_DMA_SUP_REG_OFFSET 0x000000c0
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_Q2RNR_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_Q2RNR_REG_OFFSET 0x00000100
+
+#define BBH_TX_WAN_CONFIGURATIONS_Q2RNR_REG_RAM_CNT 0x00000013
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_QPROF_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_REG_OFFSET 0x00000150
+
+#define BBH_TX_WAN_CONFIGURATIONS_QPROF_REG_RAM_CNT 0x00000013
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_PDSIZE_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_REG_OFFSET 0x000001a0
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_REG_OFFSET 0x000001a4
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_REG_OFFSET 0x000001a8
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_QMQ_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_QMQ_REG_OFFSET 0x000001b0
+
+#define BBH_TX_WAN_CONFIGURATIONS_QMQ_REG_RAM_CNT 0x00000013
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_STSSIZE_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_STSSIZE_REG_OFFSET 0x00000200
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_STSWKUPH_REG_OFFSET 0x00000204
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_REG_OFFSET 0x00000300
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_REG_OFFSET 0x00000304
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_STSEMPTY_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_STSEMPTY_REG_OFFSET 0x00000308
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_REG_OFFSET 0x00000310
+
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_REG_OFFSET 0x00000320
+
+#define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_REG_OFFSET 0x00000330
+
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_REG_OFFSET 0x00000340
+
+#define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_REG_OFFSET 0x00000350
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_REG_OFFSET 0x00000354
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_TS_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_TS_REG_OFFSET 0x00000358
+
+extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_REG;
+#define BBH_TX_WAN_CONFIGURATIONS_DSL_CFG_REG_OFFSET 0x00000360
+
+extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_Q2RNR_REG;
+#define BBH_TX_LAN_CONFIGURATIONS_Q2RNR_REG_OFFSET 0x00000400
+
+extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_QPROF_REG;
+#define BBH_TX_LAN_CONFIGURATIONS_QPROF_REG_OFFSET 0x00000450
+
+extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_PDSIZE_REG;
+#define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_REG_OFFSET 0x000004a0
+
+extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_REG;
+#define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_REG_OFFSET 0x000004a4
+
+extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_REG;
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_REG_OFFSET 0x000004a8
+
+extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_QMQ_REG;
+#define BBH_TX_LAN_CONFIGURATIONS_QMQ_REG_OFFSET 0x000004b0
+
+extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_REG;
+#define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_REG_OFFSET 0x00000600
+
+extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_REG;
+#define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_REG_OFFSET 0x00000604
+
+extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_REG;
+#define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_REG_OFFSET 0x00000608
+
+extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_EEE_REG;
+#define BBH_TX_LAN_CONFIGURATIONS_EEE_REG_OFFSET 0x0000060c
+
+extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_TS_REG;
+#define BBH_TX_LAN_CONFIGURATIONS_TS_REG_OFFSET 0x00000610
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_REG_OFFSET 0x00000700
+
+#define BBH_TX_UNIFIED_CONFIGURATIONS_Q2RNR_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_REG_OFFSET 0x00000750
+
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QPROF_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_REG_OFFSET 0x000007a0
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_REG_OFFSET 0x000007a4
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_REG_OFFSET 0x000007a8
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_REG_OFFSET 0x000007b0
+
+#define BBH_TX_UNIFIED_CONFIGURATIONS_QMQ_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_REG_OFFSET 0x00000900
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_REG_OFFSET 0x00000904
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_REG_OFFSET 0x00000908
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_EEE_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_REG_OFFSET 0x0000090c
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_TS_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TS_REG_OFFSET 0x00000910
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_REG_OFFSET 0x00000920
+
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_REG_OFFSET 0x00000940
+
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_REG_OFFSET 0x00000960
+
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_REG_OFFSET 0x00000980
+
+#define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_REG_OFFSET 0x000009a0
+
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_REG;
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_REG_OFFSET 0x000009e0
+
+#define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SRAMPD_REG;
+#define BBH_TX_DEBUG_COUNTERS_SRAMPD_REG_OFFSET 0x00000a00
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_DDRPD_REG;
+#define BBH_TX_DEBUG_COUNTERS_DDRPD_REG_OFFSET 0x00000a04
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_PDDROP_REG;
+#define BBH_TX_DEBUG_COUNTERS_PDDROP_REG_OFFSET 0x00000a08
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_STSCNT_REG;
+#define BBH_TX_DEBUG_COUNTERS_STSCNT_REG_OFFSET 0x00000a10
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_STSDROP_REG;
+#define BBH_TX_DEBUG_COUNTERS_STSDROP_REG_OFFSET 0x00000a14
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_MSGCNT_REG;
+#define BBH_TX_DEBUG_COUNTERS_MSGCNT_REG_OFFSET 0x00000a18
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_MSGDROP_REG;
+#define BBH_TX_DEBUG_COUNTERS_MSGDROP_REG_OFFSET 0x00000a1c
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_REG;
+#define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_REG_OFFSET 0x00000a20
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_REG;
+#define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_REG_OFFSET 0x00000a24
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_LENERR_REG;
+#define BBH_TX_DEBUG_COUNTERS_LENERR_REG_OFFSET 0x00000a28
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_AGGRLENERR_REG;
+#define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_REG_OFFSET 0x00000a2c
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SRAMPKT_REG;
+#define BBH_TX_DEBUG_COUNTERS_SRAMPKT_REG_OFFSET 0x00000a30
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_DDRPKT_REG;
+#define BBH_TX_DEBUG_COUNTERS_DDRPKT_REG_OFFSET 0x00000a34
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SRAMBYTE_REG;
+#define BBH_TX_DEBUG_COUNTERS_SRAMBYTE_REG_OFFSET 0x00000a38
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_DDRBYTE_REG;
+#define BBH_TX_DEBUG_COUNTERS_DDRBYTE_REG_OFFSET 0x00000a3c
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_REG;
+#define BBH_TX_DEBUG_COUNTERS_SWRDEN_REG_OFFSET 0x00000a40
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SWRDADDR_REG;
+#define BBH_TX_DEBUG_COUNTERS_SWRDADDR_REG_OFFSET 0x00000a44
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SWRDDATA_REG;
+#define BBH_TX_DEBUG_COUNTERS_SWRDDATA_REG_OFFSET 0x00000a48
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_REG;
+#define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_REG_OFFSET 0x00000a50
+
+#define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_REG;
+#define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_REG_OFFSET 0x00000a70
+
+#define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_DBGOUTREG_REG;
+#define BBH_TX_DEBUG_COUNTERS_DBGOUTREG_REG_OFFSET 0x00000b00
+
+#define BBH_TX_DEBUG_COUNTERS_DBGOUTREG_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_IN_SEGMENTATION_REG;
+#define BBH_TX_DEBUG_COUNTERS_IN_SEGMENTATION_REG_OFFSET 0x00000b80
+
+#define BBH_TX_DEBUG_COUNTERS_IN_SEGMENTATION_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_BBCFG_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MINPKT0_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_REG_OFFSET 0x0000002c
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_REG_OFFSET 0x00000030
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_REG_OFFSET 0x00000034
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_REG_OFFSET 0x00000038
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_ENABLE_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_ENABLE_REG_OFFSET 0x0000003c
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_G9991EN_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_G9991EN_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_REG_OFFSET 0x00000044
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_REG_OFFSET 0x00000050
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_REG_OFFSET 0x00000054
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_REG_OFFSET 0x00000058
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_REG_OFFSET 0x0000005c
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MACMODE_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_MACMODE_REG_OFFSET 0x00000060
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_REG_OFFSET 0x00000064
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_REG_OFFSET 0x00000068
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_REG_OFFSET 0x0000006c
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_REG_OFFSET 0x00000070
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_NONETH_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_NONETH_REG_OFFSET 0x00000074
+
+extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_REG;
+#define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_REG_OFFSET 0x00000078
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_INPKT_REG;
+#define BBH_RX_PM_COUNTERS_INPKT_REG_OFFSET 0x00000100
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_THIRDFLOW_REG;
+#define BBH_RX_PM_COUNTERS_THIRDFLOW_REG_OFFSET 0x00000104
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_SOPASOP_REG;
+#define BBH_RX_PM_COUNTERS_SOPASOP_REG_OFFSET 0x00000108
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_TOOSHORT_REG;
+#define BBH_RX_PM_COUNTERS_TOOSHORT_REG_OFFSET 0x0000010c
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_TOOLONG_REG;
+#define BBH_RX_PM_COUNTERS_TOOLONG_REG_OFFSET 0x00000110
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_CRCERROR_REG;
+#define BBH_RX_PM_COUNTERS_CRCERROR_REG_OFFSET 0x00000114
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_ENCRYPTERROR_REG;
+#define BBH_RX_PM_COUNTERS_ENCRYPTERROR_REG_OFFSET 0x00000118
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_DISPCONG_REG;
+#define BBH_RX_PM_COUNTERS_DISPCONG_REG_OFFSET 0x0000011c
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_NOSBPMSBN_REG;
+#define BBH_RX_PM_COUNTERS_NOSBPMSBN_REG_OFFSET 0x00000124
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_NOSDMACD_REG;
+#define BBH_RX_PM_COUNTERS_NOSDMACD_REG_OFFSET 0x0000012c
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_INPLOAM_REG;
+#define BBH_RX_PM_COUNTERS_INPLOAM_REG_OFFSET 0x00000130
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_CRCERRORPLOAM_REG;
+#define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_REG_OFFSET 0x00000134
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_DISPCONGPLOAM_REG;
+#define BBH_RX_PM_COUNTERS_DISPCONGPLOAM_REG_OFFSET 0x00000138
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_REG;
+#define BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_REG_OFFSET 0x0000013c
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_REG;
+#define BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_REG_OFFSET 0x00000140
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_EPONTYPERROR_REG;
+#define BBH_RX_PM_COUNTERS_EPONTYPERROR_REG_OFFSET 0x00000144
+
+extern const ru_reg_rec BBH_RX_PM_COUNTERS_RUNTERROR_REG;
+#define BBH_RX_PM_COUNTERS_RUNTERROR_REG_OFFSET 0x00000148
+
+extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX0LSB_REG;
+#define BBH_RX_DEBUG_CNTXTX0LSB_REG_OFFSET 0x00000200
+
+extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX0MSB_REG;
+#define BBH_RX_DEBUG_CNTXTX0MSB_REG_OFFSET 0x00000204
+
+extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX1LSB_REG;
+#define BBH_RX_DEBUG_CNTXTX1LSB_REG_OFFSET 0x00000208
+
+extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX1MSB_REG;
+#define BBH_RX_DEBUG_CNTXTX1MSB_REG_OFFSET 0x0000020c
+
+extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX0INGRESS_REG;
+#define BBH_RX_DEBUG_CNTXTX0INGRESS_REG_OFFSET 0x00000210
+
+extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX1INGRESS_REG;
+#define BBH_RX_DEBUG_CNTXTX1INGRESS_REG_OFFSET 0x00000214
+
+extern const ru_reg_rec BBH_RX_DEBUG_IBUW_REG;
+#define BBH_RX_DEBUG_IBUW_REG_OFFSET 0x00000218
+
+extern const ru_reg_rec BBH_RX_DEBUG_BBUW_REG;
+#define BBH_RX_DEBUG_BBUW_REG_OFFSET 0x0000021c
+
+extern const ru_reg_rec BBH_RX_DEBUG_CFUW_REG;
+#define BBH_RX_DEBUG_CFUW_REG_OFFSET 0x00000220
+
+extern const ru_reg_rec BBH_RX_DEBUG_ACKCNT_REG;
+#define BBH_RX_DEBUG_ACKCNT_REG_OFFSET 0x00000224
+
+extern const ru_reg_rec BBH_RX_DEBUG_COHERENCYCNT_REG;
+#define BBH_RX_DEBUG_COHERENCYCNT_REG_OFFSET 0x00000228
+
+extern const ru_reg_rec BBH_RX_DEBUG_DBGVEC_REG;
+#define BBH_RX_DEBUG_DBGVEC_REG_OFFSET 0x0000022c
+
+extern const ru_reg_rec BBH_RX_DEBUG_UFUW_REG;
+#define BBH_RX_DEBUG_UFUW_REG_OFFSET 0x00000230
+
+extern const ru_reg_rec BBH_RX_DEBUG_CREDITCNT_REG;
+#define BBH_RX_DEBUG_CREDITCNT_REG_OFFSET 0x00000234
+
+extern const ru_reg_rec BBH_RX_DEBUG_SDMACNT_REG;
+#define BBH_RX_DEBUG_SDMACNT_REG_OFFSET 0x00000238
+
+extern const ru_reg_rec BBH_RX_DEBUG_CMFUW_REG;
+#define BBH_RX_DEBUG_CMFUW_REG_OFFSET 0x0000023c
+
+extern const ru_reg_rec BBH_RX_DEBUG_SBNFIFO_REG;
+#define BBH_RX_DEBUG_SBNFIFO_REG_OFFSET 0x00000240
+
+#define BBH_RX_DEBUG_SBNFIFO_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec BBH_RX_DEBUG_CMDFIFO_REG;
+#define BBH_RX_DEBUG_CMDFIFO_REG_OFFSET 0x00000280
+
+#define BBH_RX_DEBUG_CMDFIFO_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec BBH_RX_DEBUG_SBNRECYCLEFIFO_REG;
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_REG_OFFSET 0x00000290
+
+#define BBH_RX_DEBUG_SBNRECYCLEFIFO_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec BBH_RX_DEBUG_COHERENCYCNT2_REG;
+#define BBH_RX_DEBUG_COHERENCYCNT2_REG_OFFSET 0x000002a0
+
+extern const ru_reg_rec BBH_RX_DEBUG_DROPSTATUS_REG;
+#define BBH_RX_DEBUG_DROPSTATUS_REG_OFFSET 0x000002a4
+
+extern const ru_reg_rec UBUS_MSTR_EN_REG;
+#define UBUS_MSTR_EN_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec UBUS_MSTR_HYST_CTRL_REG;
+#define UBUS_MSTR_HYST_CTRL_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec UBUS_MSTR_HP_REG;
+#define UBUS_MSTR_HP_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec UBUS_SLV_VPB_BASE_REG;
+#define UBUS_SLV_VPB_BASE_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec UBUS_SLV_VPB_MASK_REG;
+#define UBUS_SLV_VPB_MASK_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec UBUS_SLV_APB_BASE_REG;
+#define UBUS_SLV_APB_BASE_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec UBUS_SLV_APB_MASK_REG;
+#define UBUS_SLV_APB_MASK_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec UBUS_SLV_DEVICE_0_BASE_REG;
+#define UBUS_SLV_DEVICE_0_BASE_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec UBUS_SLV_DEVICE_0_MASK_REG;
+#define UBUS_SLV_DEVICE_0_MASK_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec UBUS_SLV_DEVICE_1_BASE_REG;
+#define UBUS_SLV_DEVICE_1_BASE_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec UBUS_SLV_DEVICE_1_MASK_REG;
+#define UBUS_SLV_DEVICE_1_MASK_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec UBUS_SLV_DEVICE_2_BASE_REG;
+#define UBUS_SLV_DEVICE_2_BASE_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec UBUS_SLV_DEVICE_2_MASK_REG;
+#define UBUS_SLV_DEVICE_2_MASK_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec UBUS_SLV_RNR_INTR_CTRL_ISR_REG;
+#define UBUS_SLV_RNR_INTR_CTRL_ISR_REG_OFFSET 0x00000080
+
+extern const ru_reg_rec UBUS_SLV_RNR_INTR_CTRL_ISM_REG;
+#define UBUS_SLV_RNR_INTR_CTRL_ISM_REG_OFFSET 0x00000084
+
+extern const ru_reg_rec UBUS_SLV_RNR_INTR_CTRL_IER_REG;
+#define UBUS_SLV_RNR_INTR_CTRL_IER_REG_OFFSET 0x00000088
+
+extern const ru_reg_rec UBUS_SLV_RNR_INTR_CTRL_ITR_REG;
+#define UBUS_SLV_RNR_INTR_CTRL_ITR_REG_OFFSET 0x0000008c
+
+extern const ru_reg_rec UBUS_SLV_PROFILING_CFG_REG;
+#define UBUS_SLV_PROFILING_CFG_REG_OFFSET 0x00000100
+
+extern const ru_reg_rec UBUS_SLV_PROFILING_STATUS_REG;
+#define UBUS_SLV_PROFILING_STATUS_REG_OFFSET 0x00000104
+
+extern const ru_reg_rec UBUS_SLV_PROFILING_COUNTER_REG;
+#define UBUS_SLV_PROFILING_COUNTER_REG_OFFSET 0x00000108
+
+extern const ru_reg_rec UBUS_SLV_PROFILING_START_VALUE_REG;
+#define UBUS_SLV_PROFILING_START_VALUE_REG_OFFSET 0x0000010c
+
+extern const ru_reg_rec UBUS_SLV_PROFILING_STOP_VALUE_REG;
+#define UBUS_SLV_PROFILING_STOP_VALUE_REG_OFFSET 0x00000110
+
+extern const ru_reg_rec UBUS_SLV_PROFILING_CYCLE_NUM_REG;
+#define UBUS_SLV_PROFILING_CYCLE_NUM_REG_OFFSET 0x00000114
+
+extern const ru_reg_rec UBUS_SLV_LED_CNTRL_REG;
+#define UBUS_SLV_LED_CNTRL_REG_OFFSET 0x00000200
+
+#define UBUS_SLV_LED_CNTRL_REG_RAM_CNT 0x00000004
+
+extern const ru_reg_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_REG;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_REG_OFFSET 0x00000220
+
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_SEL_REG_RAM_CNT 0x00000004
+
+extern const ru_reg_rec UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_REG;
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_REG_OFFSET 0x00000240
+
+#define UBUS_SLV_LED_LINK_AND_SPEED_ENCODING_REG_RAM_CNT 0x00000004
+
+extern const ru_reg_rec UBUS_SLV_LED_BLINK_RATE_CNTRL_REG;
+#define UBUS_SLV_LED_BLINK_RATE_CNTRL_REG_OFFSET 0x00000260
+
+extern const ru_reg_rec UBUS_SLV_LED_PWM_CNTRL_REG;
+#define UBUS_SLV_LED_PWM_CNTRL_REG_OFFSET 0x00000264
+
+extern const ru_reg_rec UBUS_SLV_LED_INTENSITY_CNTRL_REG;
+#define UBUS_SLV_LED_INTENSITY_CNTRL_REG_OFFSET 0x00000268
+
+extern const ru_reg_rec UBUS_SLV_AGGREGATE_LED_CNTRL_REG;
+#define UBUS_SLV_AGGREGATE_LED_CNTRL_REG_OFFSET 0x0000026c
+
+extern const ru_reg_rec UBUS_SLV_AGGREGATE_LED_BLINK_RATE_CNTRL_REG;
+#define UBUS_SLV_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_OFFSET 0x00000270
+
+extern const ru_reg_rec UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_REG;
+#define UBUS_SLV_AGGREGATE_LED_PWM_CNTRL_REG_OFFSET 0x00000274
+
+extern const ru_reg_rec UBUS_SLV_AGGREGATE_LED_INTENSITY_CNTRL_REG;
+#define UBUS_SLV_AGGREGATE_LED_INTENSITY_CNTRL_REG_OFFSET 0x00000278
+
+extern const ru_reg_rec UBUS_SLV_SW_INIT_CNTRL_REG;
+#define UBUS_SLV_SW_INIT_CNTRL_REG_OFFSET 0x0000027c
+
+extern const ru_reg_rec UBUS_SLV__CNTRL_REG;
+#define UBUS_SLV__CNTRL_REG_OFFSET 0x00000300
+
+extern const ru_reg_rec UBUS_SLV__IB_STATUS_REG;
+#define UBUS_SLV__IB_STATUS_REG_OFFSET 0x00000304
+
+extern const ru_reg_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_REG;
+#define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_REG_OFFSET 0x00000308
+
+extern const ru_reg_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_REG;
+#define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_REG_OFFSET 0x0000030c
+
+extern const ru_reg_rec UBUS_SLV__ATE_RX_EXP_DATA_1_REG;
+#define UBUS_SLV__ATE_RX_EXP_DATA_1_REG_OFFSET 0x00000310
+
+extern const ru_reg_rec UBUS_SLV__ATE_RX_STATUS_0_REG;
+#define UBUS_SLV__ATE_RX_STATUS_0_REG_OFFSET 0x00000314
+
+extern const ru_reg_rec UBUS_SLV__ATE_RX_STATUS_1_REG;
+#define UBUS_SLV__ATE_RX_STATUS_1_REG_OFFSET 0x00000318
+
+extern const ru_reg_rec UBUS_SLV__ATE_TX_CNTRL_REG;
+#define UBUS_SLV__ATE_TX_CNTRL_REG_OFFSET 0x0000031c
+
+extern const ru_reg_rec UBUS_SLV__ATE_TX_DATA_0_REG;
+#define UBUS_SLV__ATE_TX_DATA_0_REG_OFFSET 0x00000320
+
+extern const ru_reg_rec UBUS_SLV__ATE_TX_DATA_1_REG;
+#define UBUS_SLV__ATE_TX_DATA_1_REG_OFFSET 0x00000324
+
+extern const ru_reg_rec UBUS_SLV__ATE_TX_DATA_2_REG;
+#define UBUS_SLV__ATE_TX_DATA_2_REG_OFFSET 0x00000328
+
+extern const ru_reg_rec UBUS_SLV__TX_DELAY_CNTRL_0_REG;
+#define UBUS_SLV__TX_DELAY_CNTRL_0_REG_OFFSET 0x0000032c
+
+extern const ru_reg_rec UBUS_SLV__TX_DELAY_CNTRL_1_REG;
+#define UBUS_SLV__TX_DELAY_CNTRL_1_REG_OFFSET 0x00000330
+
+extern const ru_reg_rec UBUS_SLV__RX_DELAY_CNTRL_0_REG;
+#define UBUS_SLV__RX_DELAY_CNTRL_0_REG_OFFSET 0x00000334
+
+extern const ru_reg_rec UBUS_SLV__RX_DELAY_CNTRL_1_REG;
+#define UBUS_SLV__RX_DELAY_CNTRL_1_REG_OFFSET 0x00000338
+
+extern const ru_reg_rec UBUS_SLV__RX_DELAY_CNTRL_2_REG;
+#define UBUS_SLV__RX_DELAY_CNTRL_2_REG_OFFSET 0x0000033c
+
+extern const ru_reg_rec UBUS_SLV__CLK_RST_CTRL_REG;
+#define UBUS_SLV__CLK_RST_CTRL_REG_OFFSET 0x00000340
+
+extern const ru_reg_rec SBPM_REGS_INIT_FREE_LIST_REG;
+#define SBPM_REGS_INIT_FREE_LIST_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec SBPM_REGS_BN_ALLOC_REG;
+#define SBPM_REGS_BN_ALLOC_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec SBPM_REGS_BN_ALLOC_RPLY_REG;
+#define SBPM_REGS_BN_ALLOC_RPLY_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_REG;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_REG;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec SBPM_REGS_MCST_INC_REG;
+#define SBPM_REGS_MCST_INC_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec SBPM_REGS_MCST_INC_RPLY_REG;
+#define SBPM_REGS_MCST_INC_RPLY_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec SBPM_REGS_BN_CONNECT_REG;
+#define SBPM_REGS_BN_CONNECT_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec SBPM_REGS_BN_CONNECT_RPLY_REG;
+#define SBPM_REGS_BN_CONNECT_RPLY_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec SBPM_REGS_GET_NEXT_REG;
+#define SBPM_REGS_GET_NEXT_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec SBPM_REGS_GET_NEXT_RPLY_REG;
+#define SBPM_REGS_GET_NEXT_RPLY_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_REG;
+#define SBPM_REGS_SBPM_CLK_GATE_CNTRL_REG_OFFSET 0x0000002c
+
+extern const ru_reg_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_REG;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_REG_OFFSET 0x00000038
+
+extern const ru_reg_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_REG;
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_REG_OFFSET 0x0000003c
+
+extern const ru_reg_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_REG;
+#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec SBPM_REGS_SBPM_GL_TRSH_REG;
+#define SBPM_REGS_SBPM_GL_TRSH_REG_OFFSET 0x0000004c
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG0_TRSH_REG;
+#define SBPM_REGS_SBPM_UG0_TRSH_REG_OFFSET 0x00000050
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG1_TRSH_REG;
+#define SBPM_REGS_SBPM_UG1_TRSH_REG_OFFSET 0x00000054
+
+extern const ru_reg_rec SBPM_REGS_SBPM_DBG_REG;
+#define SBPM_REGS_SBPM_DBG_REG_OFFSET 0x00000074
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG0_BAC_REG;
+#define SBPM_REGS_SBPM_UG0_BAC_REG_OFFSET 0x00000078
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG1_BAC_REG;
+#define SBPM_REGS_SBPM_UG1_BAC_REG_OFFSET 0x0000007c
+
+extern const ru_reg_rec SBPM_REGS_SBPM_GL_BAC_REG;
+#define SBPM_REGS_SBPM_GL_BAC_REG_OFFSET 0x00000098
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_REG;
+#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_REG_OFFSET 0x0000009c
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_REG;
+#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_REG_OFFSET 0x00000100
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_REG;
+#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_REG_OFFSET 0x00000104
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_REG;
+#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_REG_OFFSET 0x00000108
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG_STATUS_REG;
+#define SBPM_REGS_SBPM_UG_STATUS_REG_OFFSET 0x0000011c
+
+extern const ru_reg_rec SBPM_REGS_ERROR_HANDLING_PARAMS_REG;
+#define SBPM_REGS_ERROR_HANDLING_PARAMS_REG_OFFSET 0x00000138
+
+extern const ru_reg_rec SBPM_REGS_SBPM_IIR_ADDR_REG;
+#define SBPM_REGS_SBPM_IIR_ADDR_REG_OFFSET 0x00000144
+
+extern const ru_reg_rec SBPM_REGS_SBPM_IIR_LOW_REG;
+#define SBPM_REGS_SBPM_IIR_LOW_REG_OFFSET 0x00000148
+
+extern const ru_reg_rec SBPM_REGS_SBPM_IIR_HIGH_REG;
+#define SBPM_REGS_SBPM_IIR_HIGH_REG_OFFSET 0x0000014c
+
+extern const ru_reg_rec SBPM_REGS_SBPM_DBG_VEC0_REG;
+#define SBPM_REGS_SBPM_DBG_VEC0_REG_OFFSET 0x00000150
+
+extern const ru_reg_rec SBPM_REGS_SBPM_DBG_VEC1_REG;
+#define SBPM_REGS_SBPM_DBG_VEC1_REG_OFFSET 0x00000154
+
+extern const ru_reg_rec SBPM_REGS_SBPM_DBG_VEC2_REG;
+#define SBPM_REGS_SBPM_DBG_VEC2_REG_OFFSET 0x00000174
+
+extern const ru_reg_rec SBPM_REGS_SBPM_DBG_VEC3_REG;
+#define SBPM_REGS_SBPM_DBG_VEC3_REG_OFFSET 0x00000178
+
+extern const ru_reg_rec SBPM_REGS_SBPM_SP_BBH_LOW_REG;
+#define SBPM_REGS_SBPM_SP_BBH_LOW_REG_OFFSET 0x0000017c
+
+extern const ru_reg_rec SBPM_REGS_SBPM_SP_BBH_HIGH_REG;
+#define SBPM_REGS_SBPM_SP_BBH_HIGH_REG_OFFSET 0x00000180
+
+extern const ru_reg_rec SBPM_REGS_SBPM_SP_RNR_LOW_REG;
+#define SBPM_REGS_SBPM_SP_RNR_LOW_REG_OFFSET 0x00000184
+
+extern const ru_reg_rec SBPM_REGS_SBPM_SP_RNR_HIGH_REG;
+#define SBPM_REGS_SBPM_SP_RNR_HIGH_REG_OFFSET 0x00000188
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG_MAP_LOW_REG;
+#define SBPM_REGS_SBPM_UG_MAP_LOW_REG_OFFSET 0x0000018c
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG_MAP_HIGH_REG;
+#define SBPM_REGS_SBPM_UG_MAP_HIGH_REG_OFFSET 0x00000190
+
+extern const ru_reg_rec SBPM_REGS_SBPM_NACK_MASK_LOW_REG;
+#define SBPM_REGS_SBPM_NACK_MASK_LOW_REG_OFFSET 0x00000194
+
+extern const ru_reg_rec SBPM_REGS_SBPM_NACK_MASK_HIGH_REG;
+#define SBPM_REGS_SBPM_NACK_MASK_HIGH_REG_OFFSET 0x00000198
+
+extern const ru_reg_rec SBPM_REGS_SBPM_EXCL_MASK_LOW_REG;
+#define SBPM_REGS_SBPM_EXCL_MASK_LOW_REG_OFFSET 0x0000019c
+
+extern const ru_reg_rec SBPM_REGS_SBPM_EXCL_MASK_HIGH_REG;
+#define SBPM_REGS_SBPM_EXCL_MASK_HIGH_REG_OFFSET 0x000001a0
+
+extern const ru_reg_rec SBPM_REGS_SBPM_RADDR_DECODER_REG;
+#define SBPM_REGS_SBPM_RADDR_DECODER_REG_OFFSET 0x000001a4
+
+extern const ru_reg_rec SBPM_REGS_SBPM_WR_DATA_REG;
+#define SBPM_REGS_SBPM_WR_DATA_REG_OFFSET 0x000001a8
+
+extern const ru_reg_rec SBPM_REGS_SBPM_UG_BAC_MAX_REG;
+#define SBPM_REGS_SBPM_UG_BAC_MAX_REG_OFFSET 0x000001ac
+
+extern const ru_reg_rec SBPM_REGS_SBPM_SPARE_REG;
+#define SBPM_REGS_SBPM_SPARE_REG_OFFSET 0x000001b0
+
+extern const ru_reg_rec SBPM_INTR_CTRL_ISR_REG;
+#define SBPM_INTR_CTRL_ISR_REG_OFFSET 0x00000200
+
+extern const ru_reg_rec SBPM_INTR_CTRL_ISM_REG;
+#define SBPM_INTR_CTRL_ISM_REG_OFFSET 0x00000204
+
+extern const ru_reg_rec SBPM_INTR_CTRL_IER_REG;
+#define SBPM_INTR_CTRL_IER_REG_OFFSET 0x00000208
+
+extern const ru_reg_rec SBPM_INTR_CTRL_ITR_REG;
+#define SBPM_INTR_CTRL_ITR_REG_OFFSET 0x0000020c
+
+extern const ru_reg_rec DMA_CONFIG_NUM_OF_WRITES_REG;
+#define DMA_CONFIG_NUM_OF_WRITES_REG_OFFSET 0x00000000
+
+#define DMA_CONFIG_NUM_OF_WRITES_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DMA_CONFIG_NUM_OF_READS_REG;
+#define DMA_CONFIG_NUM_OF_READS_REG_OFFSET 0x00000020
+
+#define DMA_CONFIG_NUM_OF_READS_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DMA_CONFIG_U_THRESH_REG;
+#define DMA_CONFIG_U_THRESH_REG_OFFSET 0x00000040
+
+#define DMA_CONFIG_U_THRESH_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DMA_CONFIG_PRI_REG;
+#define DMA_CONFIG_PRI_REG_OFFSET 0x00000060
+
+#define DMA_CONFIG_PRI_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DMA_CONFIG_WEIGHT_REG;
+#define DMA_CONFIG_WEIGHT_REG_OFFSET 0x00000080
+
+#define DMA_CONFIG_WEIGHT_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DMA_CONFIG_PERIPH_SOURCE_REG;
+#define DMA_CONFIG_PERIPH_SOURCE_REG_OFFSET 0x000000a0
+
+#define DMA_CONFIG_PERIPH_SOURCE_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DMA_CONFIG_TARGET_MEM_REG;
+#define DMA_CONFIG_TARGET_MEM_REG_OFFSET 0x000000c0
+
+#define DMA_CONFIG_TARGET_MEM_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DMA_CONFIG_PTRRST_REG;
+#define DMA_CONFIG_PTRRST_REG_OFFSET 0x000000e0
+
+extern const ru_reg_rec DMA_CONFIG_BBROUTEOVRD_REG;
+#define DMA_CONFIG_BBROUTEOVRD_REG_OFFSET 0x000000e4
+
+extern const ru_reg_rec DMA_CONFIG_CLK_GATE_CNTRL_REG;
+#define DMA_CONFIG_CLK_GATE_CNTRL_REG_OFFSET 0x000000e8
+
+extern const ru_reg_rec DMA_CONFIG_UBUS_DPIDS_REG;
+#define DMA_CONFIG_UBUS_DPIDS_REG_OFFSET 0x000000ec
+
+extern const ru_reg_rec DMA_CONFIG_MAX_OTF_REG;
+#define DMA_CONFIG_MAX_OTF_REG_OFFSET 0x000000f0
+
+extern const ru_reg_rec DMA_CONFIG_UBUS_CREDITS_REG;
+#define DMA_CONFIG_UBUS_CREDITS_REG_OFFSET 0x000000f4
+
+extern const ru_reg_rec DMA_CONFIG_PSRAM_BASE_REG;
+#define DMA_CONFIG_PSRAM_BASE_REG_OFFSET 0x000000f8
+
+extern const ru_reg_rec DMA_CONFIG_DDR_BASE_REG;
+#define DMA_CONFIG_DDR_BASE_REG_OFFSET 0x000000fc
+
+extern const ru_reg_rec DMA_DEBUG_NEMPTY_REG;
+#define DMA_DEBUG_NEMPTY_REG_OFFSET 0x00000100
+
+extern const ru_reg_rec DMA_DEBUG_URGNT_REG;
+#define DMA_DEBUG_URGNT_REG_OFFSET 0x00000104
+
+extern const ru_reg_rec DMA_DEBUG_SELSRC_REG;
+#define DMA_DEBUG_SELSRC_REG_OFFSET 0x00000108
+
+extern const ru_reg_rec DMA_DEBUG_REQ_CNT_RX_REG;
+#define DMA_DEBUG_REQ_CNT_RX_REG_OFFSET 0x00000120
+
+#define DMA_DEBUG_REQ_CNT_RX_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DMA_DEBUG_REQ_CNT_TX_REG;
+#define DMA_DEBUG_REQ_CNT_TX_REG_OFFSET 0x00000140
+
+#define DMA_DEBUG_REQ_CNT_TX_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DMA_DEBUG_REQ_CNT_RX_ACC_REG;
+#define DMA_DEBUG_REQ_CNT_RX_ACC_REG_OFFSET 0x00000160
+
+#define DMA_DEBUG_REQ_CNT_RX_ACC_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DMA_DEBUG_REQ_CNT_TX_ACC_REG;
+#define DMA_DEBUG_REQ_CNT_TX_ACC_REG_OFFSET 0x00000180
+
+#define DMA_DEBUG_REQ_CNT_TX_ACC_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec DMA_DEBUG_UBUSCRDT_REG;
+#define DMA_DEBUG_UBUSCRDT_REG_OFFSET 0x000001a0
+
+extern const ru_reg_rec DMA_DEBUG_UBUSBYTES_REG;
+#define DMA_DEBUG_UBUSBYTES_REG_OFFSET 0x000001a4
+
+extern const ru_reg_rec DMA_DEBUG_ON_THE_FLY_REG;
+#define DMA_DEBUG_ON_THE_FLY_REG_OFFSET 0x000001a8
+
+extern const ru_reg_rec DMA_DEBUG_DBG_SEL_REG;
+#define DMA_DEBUG_DBG_SEL_REG_OFFSET 0x000001ac
+
+extern const ru_reg_rec DMA_DEBUG_DEBUGOUT_REG;
+#define DMA_DEBUG_DEBUGOUT_REG_OFFSET 0x000001b0
+
+extern const ru_reg_rec DMA_DEBUG_RDADD_REG;
+#define DMA_DEBUG_RDADD_REG_OFFSET 0x00000200
+
+extern const ru_reg_rec DMA_DEBUG_RDVALID_REG;
+#define DMA_DEBUG_RDVALID_REG_OFFSET 0x00000204
+
+extern const ru_reg_rec DMA_DEBUG_RDDATARDY_REG;
+#define DMA_DEBUG_RDDATARDY_REG_OFFSET 0x00000208
+
+extern const ru_reg_rec DMA_DEBUG_RDDATA_REG;
+#define DMA_DEBUG_RDDATA_REG_OFFSET 0x00000210
+
+#define DMA_DEBUG_RDDATA_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec PSRAM_MEMORY_DATA_REG;
+#define PSRAM_MEMORY_DATA_REG_OFFSET 0x00000000
+
+#define PSRAM_MEMORY_DATA_REG_RAM_CNT 0x0000bfff
+
+extern const ru_reg_rec PSRAM_CONFIGURATIONS_CTRL_REG;
+#define PSRAM_CONFIGURATIONS_CTRL_REG_OFFSET 0x008a2800
+
+extern const ru_reg_rec PSRAM_CONFIGURATIONS_SCRM_SEED_REG;
+#define PSRAM_CONFIGURATIONS_SCRM_SEED_REG_OFFSET 0x008a2804
+
+extern const ru_reg_rec PSRAM_CONFIGURATIONS_SCRM_ADDR_REG;
+#define PSRAM_CONFIGURATIONS_SCRM_ADDR_REG_OFFSET 0x008a2808
+
+extern const ru_reg_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_REG;
+#define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_REG_OFFSET 0x008a280c
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_MUEN_REG;
+#define PSRAM_PM_COUNTERS_MUEN_REG_OFFSET 0x008a2900
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_BWCL_REG;
+#define PSRAM_PM_COUNTERS_BWCL_REG_OFFSET 0x008a2904
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_BWEN_REG;
+#define PSRAM_PM_COUNTERS_BWEN_REG_OFFSET 0x008a2908
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_MAX_TIME_REG;
+#define PSRAM_PM_COUNTERS_MAX_TIME_REG_OFFSET 0x008a2910
+
+#define PSRAM_PM_COUNTERS_MAX_TIME_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_ACC_TIME_REG;
+#define PSRAM_PM_COUNTERS_ACC_TIME_REG_OFFSET 0x008a2930
+
+#define PSRAM_PM_COUNTERS_ACC_TIME_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_ACC_REQ_REG;
+#define PSRAM_PM_COUNTERS_ACC_REQ_REG_OFFSET 0x008a2950
+
+#define PSRAM_PM_COUNTERS_ACC_REQ_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_LAST_ACC_TIME_REG;
+#define PSRAM_PM_COUNTERS_LAST_ACC_TIME_REG_OFFSET 0x008a2970
+
+#define PSRAM_PM_COUNTERS_LAST_ACC_TIME_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_LAST_ACC_REQ_REG;
+#define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REG_OFFSET 0x008a2990
+
+#define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_REG;
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_REG_OFFSET 0x008a29b0
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_REG;
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_REG_OFFSET 0x008a29b4
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_WR_CNT_REG;
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_REG_OFFSET 0x008a29b8
+
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_RD_CNT_REG;
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_REG_OFFSET 0x008a29d8
+
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_REG;
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_REG_OFFSET 0x008a29f8
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_REG;
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_REG_OFFSET 0x008a29fc
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_REG;
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_REG_OFFSET 0x008a2a00
+
+#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_REG;
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_REG_OFFSET 0x008a2a20
+
+#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_ARB_REQ_REG;
+#define PSRAM_PM_COUNTERS_ARB_REQ_REG_OFFSET 0x008a2a40
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_ARB_ARB_REG;
+#define PSRAM_PM_COUNTERS_ARB_ARB_REG_OFFSET 0x008a2a44
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_ARB_COMB_REG;
+#define PSRAM_PM_COUNTERS_ARB_COMB_REG_OFFSET 0x008a2a48
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_ARB_COMB_4_REG;
+#define PSRAM_PM_COUNTERS_ARB_COMB_4_REG_OFFSET 0x008a2a4c
+
+extern const ru_reg_rec PSRAM_PM_COUNTERS_ARB_COMB_BANKS_REG;
+#define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_REG_OFFSET 0x008a2a50
+
+extern const ru_reg_rec PSRAM_DEBUG_DBGSEL_REG;
+#define PSRAM_DEBUG_DBGSEL_REG_OFFSET 0x008a2b00
+
+extern const ru_reg_rec PSRAM_DEBUG_DBGBUS_REG;
+#define PSRAM_DEBUG_DBGBUS_REG_OFFSET 0x008a2b04
+
+extern const ru_reg_rec PSRAM_DEBUG_REQ_VEC_REG;
+#define PSRAM_DEBUG_REQ_VEC_REG_OFFSET 0x008a2b08
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_CFG1_REG;
+#define PSRAM_DEBUG_DBG_CAP_CFG1_REG_OFFSET 0x008a2b80
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_CFG2_REG;
+#define PSRAM_DEBUG_DBG_CAP_CFG2_REG_OFFSET 0x008a2b84
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_ST_REG;
+#define PSRAM_DEBUG_DBG_CAP_ST_REG_OFFSET 0x008a2b88
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_W0_REG;
+#define PSRAM_DEBUG_DBG_CAP_W0_REG_OFFSET 0x008a2b90
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_W1_REG;
+#define PSRAM_DEBUG_DBG_CAP_W1_REG_OFFSET 0x008a2b94
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_W2_REG;
+#define PSRAM_DEBUG_DBG_CAP_W2_REG_OFFSET 0x008a2b98
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_W3_REG;
+#define PSRAM_DEBUG_DBG_CAP_W3_REG_OFFSET 0x008a2b9c
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_WMSK_REG;
+#define PSRAM_DEBUG_DBG_CAP_WMSK_REG_OFFSET 0x008a2ba0
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_R0_REG;
+#define PSRAM_DEBUG_DBG_CAP_R0_REG_OFFSET 0x008a2bb0
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_R1_REG;
+#define PSRAM_DEBUG_DBG_CAP_R1_REG_OFFSET 0x008a2bb4
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_R2_REG;
+#define PSRAM_DEBUG_DBG_CAP_R2_REG_OFFSET 0x008a2bb8
+
+extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_R3_REG;
+#define PSRAM_DEBUG_DBG_CAP_R3_REG_OFFSET 0x008a2bbc
+
+extern const ru_reg_rec UNIMAC_RDP_IPG_HD_BKP_CNTL_REG;
+#define UNIMAC_RDP_IPG_HD_BKP_CNTL_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec UNIMAC_RDP_COMMAND_CONFIG_REG;
+#define UNIMAC_RDP_COMMAND_CONFIG_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec UNIMAC_RDP_MAC_0_REG;
+#define UNIMAC_RDP_MAC_0_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec UNIMAC_RDP_MAC_1_REG;
+#define UNIMAC_RDP_MAC_1_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec UNIMAC_RDP_FRM_LENGTH_REG;
+#define UNIMAC_RDP_FRM_LENGTH_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec UNIMAC_RDP_PAUSE_QUANT_REG;
+#define UNIMAC_RDP_PAUSE_QUANT_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec UNIMAC_RDP_TX_TS_SEQ_ID_REG;
+#define UNIMAC_RDP_TX_TS_SEQ_ID_REG_OFFSET 0x00000038
+
+extern const ru_reg_rec UNIMAC_RDP_SFD_OFFSET_REG;
+#define UNIMAC_RDP_SFD_OFFSET_REG_OFFSET 0x0000003c
+
+extern const ru_reg_rec UNIMAC_RDP_MAC_MODE_REG;
+#define UNIMAC_RDP_MAC_MODE_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec UNIMAC_RDP_TAG_0_REG;
+#define UNIMAC_RDP_TAG_0_REG_OFFSET 0x00000044
+
+extern const ru_reg_rec UNIMAC_RDP_TAG_1_REG;
+#define UNIMAC_RDP_TAG_1_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_REG;
+#define UNIMAC_RDP_RX_PAUSE_QUANTA_SCALE_REG_OFFSET 0x0000004c
+
+extern const ru_reg_rec UNIMAC_RDP_TX_PREAMBLE_REG;
+#define UNIMAC_RDP_TX_PREAMBLE_REG_OFFSET 0x00000050
+
+extern const ru_reg_rec UNIMAC_RDP_TX_IPG_LENGTH_REG;
+#define UNIMAC_RDP_TX_IPG_LENGTH_REG_OFFSET 0x00000058
+
+extern const ru_reg_rec UNIMAC_RDP_PFC_XOFF_TIMER_REG;
+#define UNIMAC_RDP_PFC_XOFF_TIMER_REG_OFFSET 0x0000005c
+
+extern const ru_reg_rec UNIMAC_RDP_UMAC_EEE_CTRL_REG;
+#define UNIMAC_RDP_UMAC_EEE_CTRL_REG_OFFSET 0x00000060
+
+extern const ru_reg_rec UNIMAC_RDP_MII_EEE_DELAY_ENTRY_TIMER_REG;
+#define UNIMAC_RDP_MII_EEE_DELAY_ENTRY_TIMER_REG_OFFSET 0x00000064
+
+extern const ru_reg_rec UNIMAC_RDP_GMII_EEE_DELAY_ENTRY_TIMER_REG;
+#define UNIMAC_RDP_GMII_EEE_DELAY_ENTRY_TIMER_REG_OFFSET 0x00000068
+
+extern const ru_reg_rec UNIMAC_RDP_UMAC_EEE_REF_COUNT_REG;
+#define UNIMAC_RDP_UMAC_EEE_REF_COUNT_REG_OFFSET 0x0000006c
+
+extern const ru_reg_rec UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_REG;
+#define UNIMAC_RDP_UMAC_TIMESTAMP_ADJUST_REG_OFFSET 0x00000070
+
+extern const ru_reg_rec UNIMAC_RDP_UMAC_RX_PKT_DROP_STATUS_REG;
+#define UNIMAC_RDP_UMAC_RX_PKT_DROP_STATUS_REG_OFFSET 0x00000074
+
+extern const ru_reg_rec UNIMAC_RDP_UMAC_SYMMETRIC_IDLE_THRESHOLD_REG;
+#define UNIMAC_RDP_UMAC_SYMMETRIC_IDLE_THRESHOLD_REG_OFFSET 0x00000078
+
+extern const ru_reg_rec UNIMAC_RDP_MII_EEE_WAKE_TIMER_REG;
+#define UNIMAC_RDP_MII_EEE_WAKE_TIMER_REG_OFFSET 0x0000007c
+
+extern const ru_reg_rec UNIMAC_RDP_GMII_EEE_WAKE_TIMER_REG;
+#define UNIMAC_RDP_GMII_EEE_WAKE_TIMER_REG_OFFSET 0x00000080
+
+extern const ru_reg_rec UNIMAC_RDP_UMAC_REV_ID_REG;
+#define UNIMAC_RDP_UMAC_REV_ID_REG_OFFSET 0x00000084
+
+extern const ru_reg_rec UNIMAC_RDP_MAC_PFC_TYPE_REG;
+#define UNIMAC_RDP_MAC_PFC_TYPE_REG_OFFSET 0x000002fc
+
+extern const ru_reg_rec UNIMAC_RDP_MAC_PFC_OPCODE_REG;
+#define UNIMAC_RDP_MAC_PFC_OPCODE_REG_OFFSET 0x00000300
+
+extern const ru_reg_rec UNIMAC_RDP_MAC_PFC_DA_0_REG;
+#define UNIMAC_RDP_MAC_PFC_DA_0_REG_OFFSET 0x00000304
+
+extern const ru_reg_rec UNIMAC_RDP_MAC_PFC_DA_1_REG;
+#define UNIMAC_RDP_MAC_PFC_DA_1_REG_OFFSET 0x00000308
+
+extern const ru_reg_rec UNIMAC_RDP_MACSEC_PROG_TX_CRC_REG;
+#define UNIMAC_RDP_MACSEC_PROG_TX_CRC_REG_OFFSET 0x0000030c
+
+extern const ru_reg_rec UNIMAC_RDP_MACSEC_CNTRL_REG;
+#define UNIMAC_RDP_MACSEC_CNTRL_REG_OFFSET 0x00000310
+
+extern const ru_reg_rec UNIMAC_RDP_TS_STATUS_REG;
+#define UNIMAC_RDP_TS_STATUS_REG_OFFSET 0x00000314
+
+extern const ru_reg_rec UNIMAC_RDP_TX_TS_DATA_REG;
+#define UNIMAC_RDP_TX_TS_DATA_REG_OFFSET 0x00000318
+
+extern const ru_reg_rec UNIMAC_RDP_PAUSE_REFRESH_CTRL_REG;
+#define UNIMAC_RDP_PAUSE_REFRESH_CTRL_REG_OFFSET 0x0000032c
+
+extern const ru_reg_rec UNIMAC_RDP_FLUSH_CONTROL_REG;
+#define UNIMAC_RDP_FLUSH_CONTROL_REG_OFFSET 0x00000330
+
+extern const ru_reg_rec UNIMAC_RDP_RXFIFO_STAT_REG;
+#define UNIMAC_RDP_RXFIFO_STAT_REG_OFFSET 0x00000334
+
+extern const ru_reg_rec UNIMAC_RDP_TXFIFO_STAT_REG;
+#define UNIMAC_RDP_TXFIFO_STAT_REG_OFFSET 0x00000338
+
+extern const ru_reg_rec UNIMAC_RDP_MAC_PFC_CTRL_REG;
+#define UNIMAC_RDP_MAC_PFC_CTRL_REG_OFFSET 0x0000033c
+
+extern const ru_reg_rec UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_REG;
+#define UNIMAC_RDP_MAC_PFC_REFRESH_CTRL_REG_OFFSET 0x00000340
+
+extern const ru_reg_rec UNIMAC_RDP_GR64_REG;
+#define UNIMAC_RDP_GR64_REG_OFFSET 0x000003fc
+
+extern const ru_reg_rec UNIMAC_RDP_GR64_UPPER_REG;
+#define UNIMAC_RDP_GR64_UPPER_REG_OFFSET 0x00000400
+
+extern const ru_reg_rec UNIMAC_RDP_GR127_REG;
+#define UNIMAC_RDP_GR127_REG_OFFSET 0x00000404
+
+extern const ru_reg_rec UNIMAC_RDP_GR127_UPPER_REG;
+#define UNIMAC_RDP_GR127_UPPER_REG_OFFSET 0x00000408
+
+extern const ru_reg_rec UNIMAC_RDP_GR255_REG;
+#define UNIMAC_RDP_GR255_REG_OFFSET 0x0000040c
+
+extern const ru_reg_rec UNIMAC_RDP_GR255_UPPER_REG;
+#define UNIMAC_RDP_GR255_UPPER_REG_OFFSET 0x00000410
+
+extern const ru_reg_rec UNIMAC_RDP_GR511_REG;
+#define UNIMAC_RDP_GR511_REG_OFFSET 0x00000414
+
+extern const ru_reg_rec UNIMAC_RDP_GR511_UPPER_REG;
+#define UNIMAC_RDP_GR511_UPPER_REG_OFFSET 0x00000418
+
+extern const ru_reg_rec UNIMAC_RDP_GR1023_REG;
+#define UNIMAC_RDP_GR1023_REG_OFFSET 0x0000041c
+
+extern const ru_reg_rec UNIMAC_RDP_GR1023_UPPER_REG;
+#define UNIMAC_RDP_GR1023_UPPER_REG_OFFSET 0x00000420
+
+extern const ru_reg_rec UNIMAC_RDP_GR1518_REG;
+#define UNIMAC_RDP_GR1518_REG_OFFSET 0x00000424
+
+extern const ru_reg_rec UNIMAC_RDP_GR1518_UPPER_REG;
+#define UNIMAC_RDP_GR1518_UPPER_REG_OFFSET 0x00000428
+
+extern const ru_reg_rec UNIMAC_RDP_GRMGV_REG;
+#define UNIMAC_RDP_GRMGV_REG_OFFSET 0x0000042c
+
+extern const ru_reg_rec UNIMAC_RDP_GRMGV_UPPER_REG;
+#define UNIMAC_RDP_GRMGV_UPPER_REG_OFFSET 0x00000430
+
+extern const ru_reg_rec UNIMAC_RDP_GR2047_REG;
+#define UNIMAC_RDP_GR2047_REG_OFFSET 0x00000434
+
+extern const ru_reg_rec UNIMAC_RDP_GR2047_UPPER_REG;
+#define UNIMAC_RDP_GR2047_UPPER_REG_OFFSET 0x00000438
+
+extern const ru_reg_rec UNIMAC_RDP_GR4095_REG;
+#define UNIMAC_RDP_GR4095_REG_OFFSET 0x0000043c
+
+extern const ru_reg_rec UNIMAC_RDP_GR4095_UPPER_REG;
+#define UNIMAC_RDP_GR4095_UPPER_REG_OFFSET 0x00000440
+
+extern const ru_reg_rec UNIMAC_RDP_GR9216_REG;
+#define UNIMAC_RDP_GR9216_REG_OFFSET 0x00000444
+
+extern const ru_reg_rec UNIMAC_RDP_GR9216_UPPER_REG;
+#define UNIMAC_RDP_GR9216_UPPER_REG_OFFSET 0x00000448
+
+extern const ru_reg_rec UNIMAC_RDP_GRPKT_REG;
+#define UNIMAC_RDP_GRPKT_REG_OFFSET 0x0000044c
+
+extern const ru_reg_rec UNIMAC_RDP_GRPKT_UPPER_REG;
+#define UNIMAC_RDP_GRPKT_UPPER_REG_OFFSET 0x00000450
+
+extern const ru_reg_rec UNIMAC_RDP_GRBYT_REG;
+#define UNIMAC_RDP_GRBYT_REG_OFFSET 0x00000454
+
+extern const ru_reg_rec UNIMAC_RDP_GRBYT_UPPER_REG;
+#define UNIMAC_RDP_GRBYT_UPPER_REG_OFFSET 0x00000458
+
+extern const ru_reg_rec UNIMAC_RDP_GRMCA_REG;
+#define UNIMAC_RDP_GRMCA_REG_OFFSET 0x0000045c
+
+extern const ru_reg_rec UNIMAC_RDP_GRMCA_UPPER_REG;
+#define UNIMAC_RDP_GRMCA_UPPER_REG_OFFSET 0x00000460
+
+extern const ru_reg_rec UNIMAC_RDP_GRBCA_REG;
+#define UNIMAC_RDP_GRBCA_REG_OFFSET 0x00000464
+
+extern const ru_reg_rec UNIMAC_RDP_GRBCA_UPPER_REG;
+#define UNIMAC_RDP_GRBCA_UPPER_REG_OFFSET 0x00000468
+
+extern const ru_reg_rec UNIMAC_RDP_GRFCS_REG;
+#define UNIMAC_RDP_GRFCS_REG_OFFSET 0x0000046c
+
+extern const ru_reg_rec UNIMAC_RDP_GRFCS_UPPER_REG;
+#define UNIMAC_RDP_GRFCS_UPPER_REG_OFFSET 0x00000470
+
+extern const ru_reg_rec UNIMAC_RDP_GRXCF_REG;
+#define UNIMAC_RDP_GRXCF_REG_OFFSET 0x00000474
+
+extern const ru_reg_rec UNIMAC_RDP_GRXCF_UPPER_REG;
+#define UNIMAC_RDP_GRXCF_UPPER_REG_OFFSET 0x00000478
+
+extern const ru_reg_rec UNIMAC_RDP_GRXPF_REG;
+#define UNIMAC_RDP_GRXPF_REG_OFFSET 0x0000047c
+
+extern const ru_reg_rec UNIMAC_RDP_GRXPF_UPPER_REG;
+#define UNIMAC_RDP_GRXPF_UPPER_REG_OFFSET 0x00000480
+
+extern const ru_reg_rec UNIMAC_RDP_GRXUO_REG;
+#define UNIMAC_RDP_GRXUO_REG_OFFSET 0x00000484
+
+extern const ru_reg_rec UNIMAC_RDP_GRXUO_UPPER_REG;
+#define UNIMAC_RDP_GRXUO_UPPER_REG_OFFSET 0x00000488
+
+extern const ru_reg_rec UNIMAC_RDP_GRALN_REG;
+#define UNIMAC_RDP_GRALN_REG_OFFSET 0x0000048c
+
+extern const ru_reg_rec UNIMAC_RDP_GRALN_UPPER_REG;
+#define UNIMAC_RDP_GRALN_UPPER_REG_OFFSET 0x00000490
+
+extern const ru_reg_rec UNIMAC_RDP_GRFLR_REG;
+#define UNIMAC_RDP_GRFLR_REG_OFFSET 0x00000494
+
+extern const ru_reg_rec UNIMAC_RDP_GRFLR_UPPER_REG;
+#define UNIMAC_RDP_GRFLR_UPPER_REG_OFFSET 0x00000498
+
+extern const ru_reg_rec UNIMAC_RDP_GRCDE_REG;
+#define UNIMAC_RDP_GRCDE_REG_OFFSET 0x0000049c
+
+extern const ru_reg_rec UNIMAC_RDP_GRCDE_UPPER_REG;
+#define UNIMAC_RDP_GRCDE_UPPER_REG_OFFSET 0x000004a0
+
+extern const ru_reg_rec UNIMAC_RDP_GRFCR_REG;
+#define UNIMAC_RDP_GRFCR_REG_OFFSET 0x000004a4
+
+extern const ru_reg_rec UNIMAC_RDP_GRFCR_UPPER_REG;
+#define UNIMAC_RDP_GRFCR_UPPER_REG_OFFSET 0x000004a8
+
+extern const ru_reg_rec UNIMAC_RDP_GROVR_REG;
+#define UNIMAC_RDP_GROVR_REG_OFFSET 0x000004ac
+
+extern const ru_reg_rec UNIMAC_RDP_GROVR_UPPER_REG;
+#define UNIMAC_RDP_GROVR_UPPER_REG_OFFSET 0x000004b0
+
+extern const ru_reg_rec UNIMAC_RDP_GRJBR_REG;
+#define UNIMAC_RDP_GRJBR_REG_OFFSET 0x000004b4
+
+extern const ru_reg_rec UNIMAC_RDP_GRJBR_UPPER_REG;
+#define UNIMAC_RDP_GRJBR_UPPER_REG_OFFSET 0x000004b8
+
+extern const ru_reg_rec UNIMAC_RDP_GRMTUE_REG;
+#define UNIMAC_RDP_GRMTUE_REG_OFFSET 0x000004bc
+
+extern const ru_reg_rec UNIMAC_RDP_GRMTUE_UPPER_REG;
+#define UNIMAC_RDP_GRMTUE_UPPER_REG_OFFSET 0x000004c0
+
+extern const ru_reg_rec UNIMAC_RDP_GRPOK_REG;
+#define UNIMAC_RDP_GRPOK_REG_OFFSET 0x000004c4
+
+extern const ru_reg_rec UNIMAC_RDP_GRPOK_UPPER_REG;
+#define UNIMAC_RDP_GRPOK_UPPER_REG_OFFSET 0x000004c8
+
+extern const ru_reg_rec UNIMAC_RDP_GRUC_REG;
+#define UNIMAC_RDP_GRUC_REG_OFFSET 0x000004cc
+
+extern const ru_reg_rec UNIMAC_RDP_GRUC_UPPER_REG;
+#define UNIMAC_RDP_GRUC_UPPER_REG_OFFSET 0x000004d0
+
+extern const ru_reg_rec UNIMAC_RDP_GRPPP_REG;
+#define UNIMAC_RDP_GRPPP_REG_OFFSET 0x000004d4
+
+extern const ru_reg_rec UNIMAC_RDP_GRPPP_UPPER_REG;
+#define UNIMAC_RDP_GRPPP_UPPER_REG_OFFSET 0x000004d8
+
+extern const ru_reg_rec UNIMAC_RDP_GRCRC_REG;
+#define UNIMAC_RDP_GRCRC_REG_OFFSET 0x000004dc
+
+extern const ru_reg_rec UNIMAC_RDP_GRCRC_UPPER_REG;
+#define UNIMAC_RDP_GRCRC_UPPER_REG_OFFSET 0x000004e0
+
+extern const ru_reg_rec UNIMAC_RDP_TR64_REG;
+#define UNIMAC_RDP_TR64_REG_OFFSET 0x000004fc
+
+extern const ru_reg_rec UNIMAC_RDP_TR64_UPPER_REG;
+#define UNIMAC_RDP_TR64_UPPER_REG_OFFSET 0x00000500
+
+extern const ru_reg_rec UNIMAC_RDP_TR127_REG;
+#define UNIMAC_RDP_TR127_REG_OFFSET 0x00000504
+
+extern const ru_reg_rec UNIMAC_RDP_TR127_UPPER_REG;
+#define UNIMAC_RDP_TR127_UPPER_REG_OFFSET 0x00000508
+
+extern const ru_reg_rec UNIMAC_RDP_TR255_REG;
+#define UNIMAC_RDP_TR255_REG_OFFSET 0x0000050c
+
+extern const ru_reg_rec UNIMAC_RDP_TR255_UPPER_REG;
+#define UNIMAC_RDP_TR255_UPPER_REG_OFFSET 0x00000510
+
+extern const ru_reg_rec UNIMAC_RDP_TR511_REG;
+#define UNIMAC_RDP_TR511_REG_OFFSET 0x00000514
+
+extern const ru_reg_rec UNIMAC_RDP_TR511_UPPER_REG;
+#define UNIMAC_RDP_TR511_UPPER_REG_OFFSET 0x00000518
+
+extern const ru_reg_rec UNIMAC_RDP_TR1023_REG;
+#define UNIMAC_RDP_TR1023_REG_OFFSET 0x0000051c
+
+extern const ru_reg_rec UNIMAC_RDP_TR1023_UPPER_REG;
+#define UNIMAC_RDP_TR1023_UPPER_REG_OFFSET 0x00000520
+
+extern const ru_reg_rec UNIMAC_RDP_TR1518_REG;
+#define UNIMAC_RDP_TR1518_REG_OFFSET 0x00000524
+
+extern const ru_reg_rec UNIMAC_RDP_TR1518_UPPER_REG;
+#define UNIMAC_RDP_TR1518_UPPER_REG_OFFSET 0x00000528
+
+extern const ru_reg_rec UNIMAC_RDP_TRMGV_REG;
+#define UNIMAC_RDP_TRMGV_REG_OFFSET 0x0000052c
+
+extern const ru_reg_rec UNIMAC_RDP_TRMGV_UPPER_REG;
+#define UNIMAC_RDP_TRMGV_UPPER_REG_OFFSET 0x00000530
+
+extern const ru_reg_rec UNIMAC_RDP_TR2047_REG;
+#define UNIMAC_RDP_TR2047_REG_OFFSET 0x00000534
+
+extern const ru_reg_rec UNIMAC_RDP_TR2047_UPPER_REG;
+#define UNIMAC_RDP_TR2047_UPPER_REG_OFFSET 0x00000538
+
+extern const ru_reg_rec UNIMAC_RDP_TR4095_REG;
+#define UNIMAC_RDP_TR4095_REG_OFFSET 0x0000053c
+
+extern const ru_reg_rec UNIMAC_RDP_TR4095_UPPER_REG;
+#define UNIMAC_RDP_TR4095_UPPER_REG_OFFSET 0x00000540
+
+extern const ru_reg_rec UNIMAC_RDP_TR9216_REG;
+#define UNIMAC_RDP_TR9216_REG_OFFSET 0x00000544
+
+extern const ru_reg_rec UNIMAC_RDP_TR9216_UPPER_REG;
+#define UNIMAC_RDP_TR9216_UPPER_REG_OFFSET 0x00000548
+
+extern const ru_reg_rec UNIMAC_RDP_GTPKT_REG;
+#define UNIMAC_RDP_GTPKT_REG_OFFSET 0x0000054c
+
+extern const ru_reg_rec UNIMAC_RDP_GTPKT_UPPER_REG;
+#define UNIMAC_RDP_GTPKT_UPPER_REG_OFFSET 0x00000550
+
+extern const ru_reg_rec UNIMAC_RDP_GTMCA_REG;
+#define UNIMAC_RDP_GTMCA_REG_OFFSET 0x00000554
+
+extern const ru_reg_rec UNIMAC_RDP_GTMCA_UPPER_REG;
+#define UNIMAC_RDP_GTMCA_UPPER_REG_OFFSET 0x00000558
+
+extern const ru_reg_rec UNIMAC_RDP_GTBCA_REG;
+#define UNIMAC_RDP_GTBCA_REG_OFFSET 0x0000055c
+
+extern const ru_reg_rec UNIMAC_RDP_GTBCA_UPPER_REG;
+#define UNIMAC_RDP_GTBCA_UPPER_REG_OFFSET 0x00000560
+
+extern const ru_reg_rec UNIMAC_RDP_GTXPF_REG;
+#define UNIMAC_RDP_GTXPF_REG_OFFSET 0x00000564
+
+extern const ru_reg_rec UNIMAC_RDP_GTXPF_UPPER_REG;
+#define UNIMAC_RDP_GTXPF_UPPER_REG_OFFSET 0x00000568
+
+extern const ru_reg_rec UNIMAC_RDP_GTXCF_REG;
+#define UNIMAC_RDP_GTXCF_REG_OFFSET 0x0000056c
+
+extern const ru_reg_rec UNIMAC_RDP_GTXCF_UPPER_REG;
+#define UNIMAC_RDP_GTXCF_UPPER_REG_OFFSET 0x00000570
+
+extern const ru_reg_rec UNIMAC_RDP_GTFCS_REG;
+#define UNIMAC_RDP_GTFCS_REG_OFFSET 0x00000574
+
+extern const ru_reg_rec UNIMAC_RDP_GTFCS_UPPER_REG;
+#define UNIMAC_RDP_GTFCS_UPPER_REG_OFFSET 0x00000578
+
+extern const ru_reg_rec UNIMAC_RDP_GTOVR_REG;
+#define UNIMAC_RDP_GTOVR_REG_OFFSET 0x0000057c
+
+extern const ru_reg_rec UNIMAC_RDP_GTOVR_UPPER_REG;
+#define UNIMAC_RDP_GTOVR_UPPER_REG_OFFSET 0x00000580
+
+extern const ru_reg_rec UNIMAC_RDP_GTDRF_REG;
+#define UNIMAC_RDP_GTDRF_REG_OFFSET 0x00000584
+
+extern const ru_reg_rec UNIMAC_RDP_GTDRF_UPPER_REG;
+#define UNIMAC_RDP_GTDRF_UPPER_REG_OFFSET 0x00000588
+
+extern const ru_reg_rec UNIMAC_RDP_GTEDF_REG;
+#define UNIMAC_RDP_GTEDF_REG_OFFSET 0x0000058c
+
+extern const ru_reg_rec UNIMAC_RDP_GTEDF_UPPER_REG;
+#define UNIMAC_RDP_GTEDF_UPPER_REG_OFFSET 0x00000590
+
+extern const ru_reg_rec UNIMAC_RDP_GTSCL_REG;
+#define UNIMAC_RDP_GTSCL_REG_OFFSET 0x00000594
+
+extern const ru_reg_rec UNIMAC_RDP_GTSCL_UPPER_REG;
+#define UNIMAC_RDP_GTSCL_UPPER_REG_OFFSET 0x00000598
+
+extern const ru_reg_rec UNIMAC_RDP_GTMCL_REG;
+#define UNIMAC_RDP_GTMCL_REG_OFFSET 0x0000059c
+
+extern const ru_reg_rec UNIMAC_RDP_GTMCL_UPPER_REG;
+#define UNIMAC_RDP_GTMCL_UPPER_REG_OFFSET 0x000005a0
+
+extern const ru_reg_rec UNIMAC_RDP_GTLCL_REG;
+#define UNIMAC_RDP_GTLCL_REG_OFFSET 0x000005a4
+
+extern const ru_reg_rec UNIMAC_RDP_GTLCL_UPPER_REG;
+#define UNIMAC_RDP_GTLCL_UPPER_REG_OFFSET 0x000005a8
+
+extern const ru_reg_rec UNIMAC_RDP_GTXCL_REG;
+#define UNIMAC_RDP_GTXCL_REG_OFFSET 0x000005ac
+
+extern const ru_reg_rec UNIMAC_RDP_GTXCL_UPPER_REG;
+#define UNIMAC_RDP_GTXCL_UPPER_REG_OFFSET 0x000005b0
+
+extern const ru_reg_rec UNIMAC_RDP_GTFRG_REG;
+#define UNIMAC_RDP_GTFRG_REG_OFFSET 0x000005b4
+
+extern const ru_reg_rec UNIMAC_RDP_GTFRG_UPPER_REG;
+#define UNIMAC_RDP_GTFRG_UPPER_REG_OFFSET 0x000005b8
+
+extern const ru_reg_rec UNIMAC_RDP_GTNCL_REG;
+#define UNIMAC_RDP_GTNCL_REG_OFFSET 0x000005bc
+
+extern const ru_reg_rec UNIMAC_RDP_GTNCL_UPPER_REG;
+#define UNIMAC_RDP_GTNCL_UPPER_REG_OFFSET 0x000005c0
+
+extern const ru_reg_rec UNIMAC_RDP_GTJBR_REG;
+#define UNIMAC_RDP_GTJBR_REG_OFFSET 0x000005c4
+
+extern const ru_reg_rec UNIMAC_RDP_GTJBR_UPPER_REG;
+#define UNIMAC_RDP_GTJBR_UPPER_REG_OFFSET 0x000005c8
+
+extern const ru_reg_rec UNIMAC_RDP_GTBYT_REG;
+#define UNIMAC_RDP_GTBYT_REG_OFFSET 0x000005cc
+
+extern const ru_reg_rec UNIMAC_RDP_GTBYT_UPPER_REG;
+#define UNIMAC_RDP_GTBYT_UPPER_REG_OFFSET 0x000005d0
+
+extern const ru_reg_rec UNIMAC_RDP_GTPOK_REG;
+#define UNIMAC_RDP_GTPOK_REG_OFFSET 0x000005d4
+
+extern const ru_reg_rec UNIMAC_RDP_GTPOK_UPPER_REG;
+#define UNIMAC_RDP_GTPOK_UPPER_REG_OFFSET 0x000005d8
+
+extern const ru_reg_rec UNIMAC_RDP_GTUC_REG;
+#define UNIMAC_RDP_GTUC_REG_OFFSET 0x000005dc
+
+extern const ru_reg_rec UNIMAC_RDP_GTUC_UPPER_REG;
+#define UNIMAC_RDP_GTUC_UPPER_REG_OFFSET 0x000005e0
+
+extern const ru_reg_rec UNIMAC_RDP_RRPKT_REG;
+#define UNIMAC_RDP_RRPKT_REG_OFFSET 0x000005fc
+
+extern const ru_reg_rec UNIMAC_RDP_RRPKT_UPPER_REG;
+#define UNIMAC_RDP_RRPKT_UPPER_REG_OFFSET 0x00000600
+
+extern const ru_reg_rec UNIMAC_RDP_RRUND_REG;
+#define UNIMAC_RDP_RRUND_REG_OFFSET 0x00000604
+
+extern const ru_reg_rec UNIMAC_RDP_RRUND_UPPER_REG;
+#define UNIMAC_RDP_RRUND_UPPER_REG_OFFSET 0x00000608
+
+extern const ru_reg_rec UNIMAC_RDP_RRFRG_REG;
+#define UNIMAC_RDP_RRFRG_REG_OFFSET 0x0000060c
+
+extern const ru_reg_rec UNIMAC_RDP_RRFRG_UPPER_REG;
+#define UNIMAC_RDP_RRFRG_UPPER_REG_OFFSET 0x00000610
+
+extern const ru_reg_rec UNIMAC_RDP_RRBYT_REG;
+#define UNIMAC_RDP_RRBYT_REG_OFFSET 0x00000614
+
+extern const ru_reg_rec UNIMAC_RDP_RRBYT_UPPER_REG;
+#define UNIMAC_RDP_RRBYT_UPPER_REG_OFFSET 0x00000618
+
+extern const ru_reg_rec UNIMAC_RDP_MIB_CNTRL_REG;
+#define UNIMAC_RDP_MIB_CNTRL_REG_OFFSET 0x0000067c
+
+extern const ru_reg_rec UNIMAC_RDP_MIB_READ_DATA_REG;
+#define UNIMAC_RDP_MIB_READ_DATA_REG_OFFSET 0x00000680
+
+extern const ru_reg_rec UNIMAC_RDP_MIB_WRITE_DATA_REG;
+#define UNIMAC_RDP_MIB_WRITE_DATA_REG_OFFSET 0x00000684
+
+extern const ru_reg_rec UNIMAC_RDP_PSW_MS_REG;
+#define UNIMAC_RDP_PSW_MS_REG_OFFSET 0x00000700
+
+extern const ru_reg_rec UNIMAC_RDP_PSW_LS_REG;
+#define UNIMAC_RDP_PSW_LS_REG_OFFSET 0x00000704
+
+extern const ru_reg_rec UNIMAC_RDP_CONTROL_REG;
+#define UNIMAC_RDP_CONTROL_REG_OFFSET 0x0000073c
+
+extern const ru_reg_rec UNIMAC_RDP_EXTENDED_CONTROL_REG;
+#define UNIMAC_RDP_EXTENDED_CONTROL_REG_OFFSET 0x00000740
+
+extern const ru_reg_rec UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_REG;
+#define UNIMAC_RDP_GMII_CLOCK_SWALLOWER_CONTROL_REG_OFFSET 0x00000744
+
+extern const ru_reg_rec UNIMAC_RDP_STATUS_REG;
+#define UNIMAC_RDP_STATUS_REG_OFFSET 0x00000748
+
+extern const ru_reg_rec UNIMAC_RDP_RX_DISCARD_PACKET_COUNTER_REG;
+#define UNIMAC_RDP_RX_DISCARD_PACKET_COUNTER_REG_OFFSET 0x0000074c
+
+extern const ru_reg_rec UNIMAC_RDP_TX_DISCARD_PACKET_COUNTER_REG;
+#define UNIMAC_RDP_TX_DISCARD_PACKET_COUNTER_REG_OFFSET 0x00000750
+
+extern const ru_reg_rec UNIMAC_RDP_REV_REG;
+#define UNIMAC_RDP_REV_REG_OFFSET 0x0000077c
+
+extern const ru_reg_rec UNIMAC_RDP_UMAC_RXERR_MASK_REG;
+#define UNIMAC_RDP_UMAC_RXERR_MASK_REG_OFFSET 0x00000780
+
+extern const ru_reg_rec UNIMAC_RDP_MIB_MAX_PKT_SIZE_REG;
+#define UNIMAC_RDP_MIB_MAX_PKT_SIZE_REG_OFFSET 0x00000784
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_REG_OFFSET 0x00000044
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_REG;
+#define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_REG_OFFSET 0x0000004c
+
+extern const ru_reg_rec TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_REG;
+#define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_REG_OFFSET 0x00000000
+
+#define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_REG_RAM_CNT 0x00000fff
+
+extern const ru_reg_rec TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_REG;
+#define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_REG_OFFSET 0x00004000
+
+extern const ru_reg_rec TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_REG;
+#define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_REG_OFFSET 0x00004010
+
+#define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_REG;
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_REG_OFFSET 0x00004100
+
+extern const ru_reg_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_REG;
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_REG_OFFSET 0x00004104
+
+extern const ru_reg_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_REG;
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_REG_OFFSET 0x00004108
+
+extern const ru_reg_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_REG;
+#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_REG_OFFSET 0x0000410c
+
+extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_REG;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_REG_OFFSET 0x00004200
+
+extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_REG;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_REG_OFFSET 0x00004204
+
+extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_REG;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_REG_OFFSET 0x00004208
+
+extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_REG;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_REG_OFFSET 0x0000420c
+
+extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_REG;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_REG_OFFSET 0x00004214
+
+extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_REG;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_REG_OFFSET 0x00004218
+
+extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_REG;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_REG_OFFSET 0x00004220
+
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_REG;
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_REG_OFFSET 0x00004240
+
+#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_REG;
+#define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_REG_OFFSET 0x00004500
+
+extern const ru_reg_rec HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_REG;
+#define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec HASH_GENERAL_CONFIGURATION_PAD_HIGH_REG;
+#define HASH_GENERAL_CONFIGURATION_PAD_HIGH_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec HASH_GENERAL_CONFIGURATION_PAD_LOW_REG;
+#define HASH_GENERAL_CONFIGURATION_PAD_LOW_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_REG;
+#define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec HASH_GENERAL_CONFIGURATION_UNDO_FIX_REG;
+#define HASH_GENERAL_CONFIGURATION_UNDO_FIX_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec HASH_PM_COUNTERS_HITS_REG;
+#define HASH_PM_COUNTERS_HITS_REG_OFFSET 0x00000100
+
+extern const ru_reg_rec HASH_PM_COUNTERS_SRCHS_REG;
+#define HASH_PM_COUNTERS_SRCHS_REG_OFFSET 0x00000104
+
+extern const ru_reg_rec HASH_PM_COUNTERS_MISS_REG;
+#define HASH_PM_COUNTERS_MISS_REG_OFFSET 0x00000108
+
+extern const ru_reg_rec HASH_PM_COUNTERS_HIT_1ST_ACS_REG;
+#define HASH_PM_COUNTERS_HIT_1ST_ACS_REG_OFFSET 0x0000010c
+
+extern const ru_reg_rec HASH_PM_COUNTERS_HIT_2ND_ACS_REG;
+#define HASH_PM_COUNTERS_HIT_2ND_ACS_REG_OFFSET 0x00000110
+
+extern const ru_reg_rec HASH_PM_COUNTERS_HIT_3RD_ACS_REG;
+#define HASH_PM_COUNTERS_HIT_3RD_ACS_REG_OFFSET 0x00000114
+
+extern const ru_reg_rec HASH_PM_COUNTERS_HIT_4TH_ACS_REG;
+#define HASH_PM_COUNTERS_HIT_4TH_ACS_REG_OFFSET 0x00000118
+
+extern const ru_reg_rec HASH_PM_COUNTERS_FRZ_CNT_REG;
+#define HASH_PM_COUNTERS_FRZ_CNT_REG_OFFSET 0x00000150
+
+extern const ru_reg_rec HASH_LKUP_TBL_CFG_TBL_CFG_REG;
+#define HASH_LKUP_TBL_CFG_TBL_CFG_REG_OFFSET 0x00000200
+
+#define HASH_LKUP_TBL_CFG_TBL_CFG_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_REG;
+#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_REG_OFFSET 0x00000204
+
+#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec HASH_LKUP_TBL_CFG_KEY_MASK_LOW_REG;
+#define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_REG_OFFSET 0x00000208
+
+#define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_REG;
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_REG_OFFSET 0x0000020c
+
+#define HASH_LKUP_TBL_CFG_CNTXT_CFG_REG_RAM_CNT 0x00000006
+
+extern const ru_reg_rec HASH_CAM_CONFIGURATION_CNTXT_CFG_REG;
+#define HASH_CAM_CONFIGURATION_CNTXT_CFG_REG_OFFSET 0x00000400
+
+extern const ru_reg_rec HASH_CAM_INDIRECT_OP_REG;
+#define HASH_CAM_INDIRECT_OP_REG_OFFSET 0x00000800
+
+extern const ru_reg_rec HASH_CAM_INDIRECT_OP_DONE_REG;
+#define HASH_CAM_INDIRECT_OP_DONE_REG_OFFSET 0x00000804
+
+extern const ru_reg_rec HASH_CAM_INDIRECT_ADDR_REG;
+#define HASH_CAM_INDIRECT_ADDR_REG_OFFSET 0x00000808
+
+extern const ru_reg_rec HASH_CAM_INDIRECT_VLID_IN_REG;
+#define HASH_CAM_INDIRECT_VLID_IN_REG_OFFSET 0x0000080c
+
+extern const ru_reg_rec HASH_CAM_INDIRECT_VLID_OUT_REG;
+#define HASH_CAM_INDIRECT_VLID_OUT_REG_OFFSET 0x00000814
+
+extern const ru_reg_rec HASH_CAM_INDIRECT_RSLT_REG;
+#define HASH_CAM_INDIRECT_RSLT_REG_OFFSET 0x00000818
+
+extern const ru_reg_rec HASH_CAM_INDIRECT_KEY_IN_REG;
+#define HASH_CAM_INDIRECT_KEY_IN_REG_OFFSET 0x00000820
+
+#define HASH_CAM_INDIRECT_KEY_IN_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec HASH_CAM_INDIRECT_KEY_OUT_REG;
+#define HASH_CAM_INDIRECT_KEY_OUT_REG_OFFSET 0x00000840
+
+#define HASH_CAM_INDIRECT_KEY_OUT_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_STATUS_REG;
+#define HASH_CAM_BIST_BIST_STATUS_REG_OFFSET 0x00000900
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_DBG_COMPARE_EN_REG;
+#define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_REG_OFFSET 0x00000904
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_DBG_DATA_REG;
+#define HASH_CAM_BIST_BIST_DBG_DATA_REG_OFFSET 0x00000908
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_REG;
+#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_REG_OFFSET 0x0000090c
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_DBG_DATA_VALID_REG;
+#define HASH_CAM_BIST_BIST_DBG_DATA_VALID_REG_OFFSET 0x00000910
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_EN_REG;
+#define HASH_CAM_BIST_BIST_EN_REG_OFFSET 0x00000914
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_MODE_REG;
+#define HASH_CAM_BIST_BIST_MODE_REG_OFFSET 0x00000918
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_RST_L_REG;
+#define HASH_CAM_BIST_BIST_RST_L_REG_OFFSET 0x0000091c
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_REG;
+#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_REG_OFFSET 0x00000920
+
+extern const ru_reg_rec HASH_CAM_BIST_DBG_EN_REG;
+#define HASH_CAM_BIST_DBG_EN_REG_OFFSET 0x00000924
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_CASCADE_SELECT_REG;
+#define HASH_CAM_BIST_BIST_CASCADE_SELECT_REG_OFFSET 0x00000928
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_BLOCK_SELECT_REG;
+#define HASH_CAM_BIST_BIST_BLOCK_SELECT_REG_OFFSET 0x0000092c
+
+extern const ru_reg_rec HASH_CAM_BIST_BIST_REPAIR_ENABLE_REG;
+#define HASH_CAM_BIST_BIST_REPAIR_ENABLE_REG_OFFSET 0x00000930
+
+extern const ru_reg_rec HASH_INTR_CTRL_ISR_REG;
+#define HASH_INTR_CTRL_ISR_REG_OFFSET 0x00000a00
+
+extern const ru_reg_rec HASH_INTR_CTRL_ISM_REG;
+#define HASH_INTR_CTRL_ISM_REG_OFFSET 0x00000a04
+
+extern const ru_reg_rec HASH_INTR_CTRL_IER_REG;
+#define HASH_INTR_CTRL_IER_REG_OFFSET 0x00000a08
+
+extern const ru_reg_rec HASH_INTR_CTRL_ITR_REG;
+#define HASH_INTR_CTRL_ITR_REG_OFFSET 0x00000a0c
+
+extern const ru_reg_rec HASH_DEBUG_DBG0_REG;
+#define HASH_DEBUG_DBG0_REG_OFFSET 0x00000a30
+
+extern const ru_reg_rec HASH_DEBUG_DBG1_REG;
+#define HASH_DEBUG_DBG1_REG_OFFSET 0x00000a34
+
+extern const ru_reg_rec HASH_DEBUG_DBG2_REG;
+#define HASH_DEBUG_DBG2_REG_OFFSET 0x00000a38
+
+extern const ru_reg_rec HASH_DEBUG_DBG3_REG;
+#define HASH_DEBUG_DBG3_REG_OFFSET 0x00000a3c
+
+extern const ru_reg_rec HASH_DEBUG_DBG4_REG;
+#define HASH_DEBUG_DBG4_REG_OFFSET 0x00000a40
+
+extern const ru_reg_rec HASH_DEBUG_DBG5_REG;
+#define HASH_DEBUG_DBG5_REG_OFFSET 0x00000a44
+
+extern const ru_reg_rec HASH_DEBUG_DBG6_REG;
+#define HASH_DEBUG_DBG6_REG_OFFSET 0x00000a48
+
+extern const ru_reg_rec HASH_DEBUG_DBG7_REG;
+#define HASH_DEBUG_DBG7_REG_OFFSET 0x00000a4c
+
+extern const ru_reg_rec HASH_DEBUG_DBG8_REG;
+#define HASH_DEBUG_DBG8_REG_OFFSET 0x00000a50
+
+extern const ru_reg_rec HASH_DEBUG_DBG9_REG;
+#define HASH_DEBUG_DBG9_REG_OFFSET 0x00000a54
+
+extern const ru_reg_rec HASH_DEBUG_DBG10_REG;
+#define HASH_DEBUG_DBG10_REG_OFFSET 0x00000a58
+
+extern const ru_reg_rec HASH_DEBUG_DBG11_REG;
+#define HASH_DEBUG_DBG11_REG_OFFSET 0x00000a5c
+
+extern const ru_reg_rec HASH_DEBUG_DBG12_REG;
+#define HASH_DEBUG_DBG12_REG_OFFSET 0x00000a60
+
+extern const ru_reg_rec HASH_DEBUG_DBG13_REG;
+#define HASH_DEBUG_DBG13_REG_OFFSET 0x00000a64
+
+extern const ru_reg_rec HASH_DEBUG_DBG14_REG;
+#define HASH_DEBUG_DBG14_REG_OFFSET 0x00000a68
+
+extern const ru_reg_rec HASH_DEBUG_DBG15_REG;
+#define HASH_DEBUG_DBG15_REG_OFFSET 0x00000a6c
+
+extern const ru_reg_rec HASH_DEBUG_DBG16_REG;
+#define HASH_DEBUG_DBG16_REG_OFFSET 0x00000a70
+
+extern const ru_reg_rec HASH_DEBUG_DBG17_REG;
+#define HASH_DEBUG_DBG17_REG_OFFSET 0x00000a74
+
+extern const ru_reg_rec HASH_DEBUG_DBG18_REG;
+#define HASH_DEBUG_DBG18_REG_OFFSET 0x00000a78
+
+extern const ru_reg_rec HASH_DEBUG_DBG19_REG;
+#define HASH_DEBUG_DBG19_REG_OFFSET 0x00000a7c
+
+extern const ru_reg_rec HASH_DEBUG_DBG20_REG;
+#define HASH_DEBUG_DBG20_REG_OFFSET 0x00000a80
+
+extern const ru_reg_rec HASH_DEBUG_DBG_SEL_REG;
+#define HASH_DEBUG_DBG_SEL_REG_OFFSET 0x00000a84
+
+extern const ru_reg_rec HASH_AGING_RAM_AGING_REG;
+#define HASH_AGING_RAM_AGING_REG_OFFSET 0x00007000
+
+#define HASH_AGING_RAM_AGING_REG_RAM_CNT 0x00000041
+
+extern const ru_reg_rec HASH_CONTEXT_RAM_CONTEXT_47_24_REG;
+#define HASH_CONTEXT_RAM_CONTEXT_47_24_REG_OFFSET 0x00008000
+
+#define HASH_CONTEXT_RAM_CONTEXT_47_24_REG_RAM_CNT 0x000004bf
+
+extern const ru_reg_rec HASH_CONTEXT_RAM_CONTEXT_23_0_REG;
+#define HASH_CONTEXT_RAM_CONTEXT_23_0_REG_OFFSET 0x00008004
+
+#define HASH_CONTEXT_RAM_CONTEXT_23_0_REG_RAM_CNT 0x000004bf
+
+extern const ru_reg_rec HASH_RAM_ENG_HIGH_REG;
+#define HASH_RAM_ENG_HIGH_REG_OFFSET 0x00010000
+
+#define HASH_RAM_ENG_HIGH_REG_RAM_CNT 0x000007ff
+
+extern const ru_reg_rec HASH_RAM_ENG_LOW_REG;
+#define HASH_RAM_ENG_LOW_REG_OFFSET 0x00010004
+
+#define HASH_RAM_ENG_LOW_REG_RAM_CNT 0x000007ff
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_PRGRM_M_PRM_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_REG_OFFSET 0x00000200
+
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_REG_RAM_CNT 0x0000007f
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_REG_OFFSET 0x00000600
+
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_REG_OFFSET 0x00000700
+
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_REG_RAM_CNT 0x0000001f
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_REG_OFFSET 0x00000800
+
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_REG_OFFSET 0x00000900
+
+#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_REG_OFFSET 0x00000c00
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_REG_OFFSET 0x00000c04
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_REG_OFFSET 0x00000c08
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_REG_OFFSET 0x00000c10
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_REG_OFFSET 0x00000c14
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_REG_OFFSET 0x00000c18
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_REG_OFFSET 0x00000c30
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_REG_OFFSET 0x00000c34
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_REG_OFFSET 0x00000c38
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_REG_OFFSET 0x00000cfc
+
+extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_DEBUG_DBG0_REG;
+#define BAC_IF_BACIF_BLOCK_BACIF_DEBUG_DBG0_REG_OFFSET 0x00000e00
+
+extern const ru_reg_rec CNPL_MEMORY_DATA_REG;
+#define CNPL_MEMORY_DATA_REG_OFFSET 0x00000000
+
+#define CNPL_MEMORY_DATA_REG_RAM_CNT 0x00000bff
+
+extern const ru_reg_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_REG;
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_REG_OFFSET 0x00004000
+
+#define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_REG;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_REG_OFFSET 0x00004100
+
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_REG;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_REG_OFFSET 0x00004110
+
+#define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_REG;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_REG_OFFSET 0x00004120
+
+#define CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_REG_RAM_CNT 0x00000002
+
+extern const ru_reg_rec CNPL_POLICERS_CONFIGURATIONS_PER_UP_REG;
+#define CNPL_POLICERS_CONFIGURATIONS_PER_UP_REG_OFFSET 0x00004130
+
+extern const ru_reg_rec CNPL_POLICERS_CONFIGURATIONS_PL_SIZE_PROF_REG;
+#define CNPL_POLICERS_CONFIGURATIONS_PL_SIZE_PROF_REG_OFFSET 0x00004140
+
+#define CNPL_POLICERS_CONFIGURATIONS_PL_SIZE_PROF_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_ORDR_REG;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_ORDR_REG_OFFSET 0x00004200
+
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_ORDR_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_RSRV_THR_REG;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_RSRV_THR_REG_OFFSET 0x00004240
+
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_RSRV_THR_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HIPRI_THR_REG;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HIPRI_THR_REG_OFFSET 0x00004280
+
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HIPRI_THR_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_MAX_THR_REG;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_MAX_THR_REG_OFFSET 0x000042c0
+
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_MAX_THR_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_REG;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_CFG_REG_OFFSET 0x00004300
+
+extern const ru_reg_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_VAL_REG;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_VAL_REG_OFFSET 0x00004310
+
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_HI_WMRK_VAL_REG_RAM_CNT 0x00000002
+
+extern const ru_reg_rec CNPL_BUF_MNG_COUNTERS_CFG_STAT_CTRS_VAL_REG;
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_CTRS_VAL_REG_OFFSET 0x00004340
+
+#define CNPL_BUF_MNG_COUNTERS_CFG_STAT_CTRS_VAL_REG_RAM_CNT 0x0000000f
+
+extern const ru_reg_rec CNPL_SW_IF_SW_CMD_REG;
+#define CNPL_SW_IF_SW_CMD_REG_OFFSET 0x00004400
+
+extern const ru_reg_rec CNPL_SW_IF_SW_STAT_REG;
+#define CNPL_SW_IF_SW_STAT_REG_OFFSET 0x00004404
+
+extern const ru_reg_rec CNPL_SW_IF_SW_PL_RSLT_REG;
+#define CNPL_SW_IF_SW_PL_RSLT_REG_OFFSET 0x00004410
+
+extern const ru_reg_rec CNPL_SW_IF_SW_PL_RD_REG;
+#define CNPL_SW_IF_SW_PL_RD_REG_OFFSET 0x00004418
+
+#define CNPL_SW_IF_SW_PL_RD_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec CNPL_SW_IF_SW_CNT_RD_REG;
+#define CNPL_SW_IF_SW_CNT_RD_REG_OFFSET 0x00004420
+
+#define CNPL_SW_IF_SW_CNT_RD_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec CNPL_MISC_ARB_PRM_REG;
+#define CNPL_MISC_ARB_PRM_REG_OFFSET 0x00004500
+
+extern const ru_reg_rec CNPL_MISC_COL_AWR_EN_REG;
+#define CNPL_MISC_COL_AWR_EN_REG_OFFSET 0x00004504
+
+extern const ru_reg_rec CNPL_PM_COUNTERS_ENG_CMDS_REG;
+#define CNPL_PM_COUNTERS_ENG_CMDS_REG_OFFSET 0x00004600
+
+#define CNPL_PM_COUNTERS_ENG_CMDS_REG_RAM_CNT 0x0000000b
+
+extern const ru_reg_rec CNPL_PM_COUNTERS_CMD_WAIT_REG;
+#define CNPL_PM_COUNTERS_CMD_WAIT_REG_OFFSET 0x00004640
+
+#define CNPL_PM_COUNTERS_CMD_WAIT_REG_RAM_CNT 0x00000001
+
+extern const ru_reg_rec CNPL_PM_COUNTERS_TOT_CYC_REG;
+#define CNPL_PM_COUNTERS_TOT_CYC_REG_OFFSET 0x00004650
+
+extern const ru_reg_rec CNPL_PM_COUNTERS_GNT_CYC_REG;
+#define CNPL_PM_COUNTERS_GNT_CYC_REG_OFFSET 0x00004654
+
+extern const ru_reg_rec CNPL_PM_COUNTERS_ARB_CYC_REG;
+#define CNPL_PM_COUNTERS_ARB_CYC_REG_OFFSET 0x00004658
+
+extern const ru_reg_rec CNPL_PM_COUNTERS_PL_UP_ERR_REG;
+#define CNPL_PM_COUNTERS_PL_UP_ERR_REG_OFFSET 0x00004660
+
+#define CNPL_PM_COUNTERS_PL_UP_ERR_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec CNPL_PM_COUNTERS_GEN_CFG_REG;
+#define CNPL_PM_COUNTERS_GEN_CFG_REG_OFFSET 0x000046fc
+
+extern const ru_reg_rec CNPL_DEBUG_DBGSEL_REG;
+#define CNPL_DEBUG_DBGSEL_REG_OFFSET 0x00004700
+
+extern const ru_reg_rec CNPL_DEBUG_DBGBUS_REG;
+#define CNPL_DEBUG_DBGBUS_REG_OFFSET 0x00004704
+
+extern const ru_reg_rec CNPL_DEBUG_REQ_VEC_REG;
+#define CNPL_DEBUG_REQ_VEC_REG_OFFSET 0x00004708
+
+extern const ru_reg_rec CNPL_DEBUG_POL_UP_ST_REG;
+#define CNPL_DEBUG_POL_UP_ST_REG_OFFSET 0x00004710
+
+#define CNPL_DEBUG_POL_UP_ST_REG_RAM_CNT 0x00000003
+
+extern const ru_reg_rec NATC_ENG_COMMAND_STATUS_REG;
+#define NATC_ENG_COMMAND_STATUS_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec NATC_ENG_HASH_REG;
+#define NATC_ENG_HASH_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec NATC_ENG_HIT_COUNT_REG;
+#define NATC_ENG_HIT_COUNT_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec NATC_ENG_BYTE_COUNT_REG;
+#define NATC_ENG_BYTE_COUNT_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec NATC_ENG_PKT_LEN_REG;
+#define NATC_ENG_PKT_LEN_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec NATC_ENG_KEY_RESULT_REG;
+#define NATC_ENG_KEY_RESULT_REG_OFFSET 0x00000020
+
+#define NATC_ENG_KEY_RESULT_REG_RAM_CNT 0x00000025
+
+extern const ru_reg_rec NATC_CTRS_CACHE_HIT_COUNT_REG;
+#define NATC_CTRS_CACHE_HIT_COUNT_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec NATC_CTRS_CACHE_MISS_COUNT_REG;
+#define NATC_CTRS_CACHE_MISS_COUNT_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec NATC_CTRS_DDR_REQUEST_COUNT_REG;
+#define NATC_CTRS_DDR_REQUEST_COUNT_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec NATC_CTRS_DDR_EVICT_COUNT_REG;
+#define NATC_CTRS_DDR_EVICT_COUNT_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec NATC_CTRS_DDR_BLOCK_COUNT_REG;
+#define NATC_CTRS_DDR_BLOCK_COUNT_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec NATC_DDR_CFG_SIZE_REG;
+#define NATC_DDR_CFG_SIZE_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec NATC_DDR_CFG_BINS_PER_BUCKET_0_REG;
+#define NATC_DDR_CFG_BINS_PER_BUCKET_0_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec NATC_DDR_CFG_BINS_PER_BUCKET_1_REG;
+#define NATC_DDR_CFG_BINS_PER_BUCKET_1_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec NATC_DDR_CFG_TOTAL_LEN_REG;
+#define NATC_DDR_CFG_TOTAL_LEN_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec NATC_DDR_CFG_SM_STATUS_REG;
+#define NATC_DDR_CFG_SM_STATUS_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec NATC_CONTROL_STATUS_REG;
+#define NATC_CONTROL_STATUS_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec NATC_CONTROL_STATUS2_REG;
+#define NATC_CONTROL_STATUS2_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec NATC_TABLE_CONTROL_REG;
+#define NATC_TABLE_CONTROL_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec NATC_STAT_COUNTER_CONTROL_0_REG;
+#define NATC_STAT_COUNTER_CONTROL_0_REG_OFFSET 0x00000350
+
+extern const ru_reg_rec NATC_STAT_COUNTER_CONTROL_1_REG;
+#define NATC_STAT_COUNTER_CONTROL_1_REG_OFFSET 0x00000354
+
+extern const ru_reg_rec NATC_REGFILE_FIFO_START_ADDR_0_REG;
+#define NATC_REGFILE_FIFO_START_ADDR_0_REG_OFFSET 0x000003a0
+
+extern const ru_reg_rec NATC_REGFILE_FIFO_START_ADDR_1_REG;
+#define NATC_REGFILE_FIFO_START_ADDR_1_REG_OFFSET 0x000003a4
+
+extern const ru_reg_rec NATC_TBL_DDR_KEY_BASE_ADDRESS_LOWER_REG;
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_LOWER_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec NATC_TBL_DDR_KEY_BASE_ADDRESS_UPPER_REG;
+#define NATC_TBL_DDR_KEY_BASE_ADDRESS_UPPER_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec NATC_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_REG;
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec NATC_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_REG;
+#define NATC_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec NATC_KEY_MASK_REG;
+#define NATC_KEY_MASK_REG_OFFSET 0x00000000
+
+#define NATC_KEY_MASK_REG_RAM_CNT 0x00000007
+
+extern const ru_reg_rec NATC_INDIR_C_INDIR_ADDR_REG_REG;
+#define NATC_INDIR_C_INDIR_ADDR_REG_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec NATC_INDIR_C_INDIR_DATA_REG_REG;
+#define NATC_INDIR_C_INDIR_DATA_REG_REG_OFFSET 0x00000010
+
+#define NATC_INDIR_C_INDIR_DATA_REG_REG_RAM_CNT 0x00000028
+
+
+
+/******************************************************************************
+ * XRDP_ Blocks
+ ******************************************************************************/
+extern const ru_block_rec QM_BLOCK;
+extern const ru_block_rec DQM_TOKEN_FIFO_BLOCK;
+extern const ru_block_rec DQM_BLOCK;
+extern const ru_block_rec FPM_BLOCK;
+extern const ru_block_rec RNR_MEM_BLOCK;
+extern const ru_block_rec RNR_INST_BLOCK;
+extern const ru_block_rec RNR_CNTXT_BLOCK;
+extern const ru_block_rec RNR_PRED_BLOCK;
+extern const ru_block_rec RNR_REGS_BLOCK;
+extern const ru_block_rec RNR_QUAD_BLOCK;
+extern const ru_block_rec DSPTCHR_BLOCK;
+extern const ru_block_rec BBH_TX_BLOCK;
+extern const ru_block_rec BBH_RX_BLOCK;
+extern const ru_block_rec UBUS_MSTR_BLOCK;
+extern const ru_block_rec UBUS_SLV_BLOCK;
+extern const ru_block_rec SBPM_BLOCK;
+extern const ru_block_rec DMA_BLOCK;
+extern const ru_block_rec PSRAM_BLOCK;
+extern const ru_block_rec UNIMAC_RDP_BLOCK;
+extern const ru_block_rec UNIMAC_MISC_BLOCK;
+extern const ru_block_rec TCAM_BLOCK;
+extern const ru_block_rec HASH_BLOCK;
+extern const ru_block_rec BAC_IF_BLOCK;
+extern const ru_block_rec CNPL_BLOCK;
+extern const ru_block_rec NATC_ENG_BLOCK;
+extern const ru_block_rec NATC_CTRS_BLOCK;
+extern const ru_block_rec NATC_DDR_CFG_BLOCK;
+extern const ru_block_rec NATC_BLOCK;
+extern const ru_block_rec NATC_TBL_BLOCK;
+extern const ru_block_rec NATC_KEY_BLOCK;
+extern const ru_block_rec NATC_INDIR_BLOCK;
+extern const ru_block_rec *RU_ALL_BLOCKS[];
+
+
+#define RU_BLK_COUNT 31
+#define RU_REG_COUNT 1163
+#define RU_FLD_COUNT 3435
+
+
+#endif /* End of file XRDP_.h */
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_PSRAM_GPL.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_PSRAM_GPL.c
new file mode 100644
index 0000000000..a541b4d0cc
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_PSRAM_GPL.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+/******************************************************************************
+ * Register: PSRAM_MEMORY_DATA
+ ******************************************************************************/
+const ru_reg_rec PSRAM_MEMORY_DATA_REG = 
+{
+    "MEMORY_DATA",
+#if RU_INCLUDE_DESC
+    "PSRAM_MEM_ENTRY %i Register",
+    "psram_mem_entry",
+#endif
+    PSRAM_MEMORY_DATA_REG_OFFSET,
+    PSRAM_MEMORY_DATA_REG_RAM_CNT,
+    4,
+    765,
+};
+
+/******************************************************************************
+ * Block: PSRAM
+ ******************************************************************************/
+static const ru_reg_rec *PSRAM_REGS[] =
+{
+    &PSRAM_MEMORY_DATA_REG,
+};
+
+unsigned long PSRAM_ADDRS[] =
+{
+    0x82000000,
+};
+
+const ru_block_rec PSRAM_BLOCK = 
+{
+    "PSRAM",
+    PSRAM_ADDRS,
+    1,
+    41,
+    PSRAM_REGS
+};
+
+/* End of file XRDP_PSRAM_GPL_AG_trim.c */
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_RNR_REGS_GPL.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_RNR_REGS_GPL.c
new file mode 100644
index 0000000000..6d30c30bb7
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_RNR_REGS_GPL.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+/******************************************************************************
+ * Register: RNR_REGS_CFG_CPU_WAKEUP
+ ******************************************************************************/
+const ru_reg_rec RNR_REGS_CFG_CPU_WAKEUP_REG = 
+{
+    "CFG_CPU_WAKEUP",
+#if RU_INCLUDE_DESC
+    "CPU_WAKEUP Register",
+    "Writing to this register generates a request towards the runner scheduler.",
+#endif
+    RNR_REGS_CFG_CPU_WAKEUP_REG_OFFSET,
+    0,
+    0,
+    239,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+};
+
+/******************************************************************************
+ * Block: RNR_REGS
+ ******************************************************************************/
+static const ru_reg_rec *RNR_REGS_REGS[] =
+{
+    &RNR_REGS_CFG_CPU_WAKEUP_REG,
+};
+
+unsigned long RNR_REGS_ADDRS[] =
+{
+    0x82800000,
+    0x82801000,
+    0x82802000,
+    0x82803000,
+    0x82804000,
+};
+
+const ru_block_rec RNR_REGS_BLOCK = 
+{
+    "RNR_REGS",
+    RNR_REGS_ADDRS,
+    5,
+    29,
+    RNR_REGS_REGS
+};
+
+/* End of file XRDP_RNR_REGS.c */
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_SBPM_GPL.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_SBPM_GPL.c
new file mode 100644
index 0000000000..efe2279edc
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_SBPM_GPL.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+/******************************************************************************
+ * Register: SBPM_REGS_BN_ALLOC
+ ******************************************************************************/
+const ru_reg_rec SBPM_REGS_BN_ALLOC_REG = 
+{
+    "REGS_BN_ALLOC",
+#if RU_INCLUDE_DESC
+    "BN_ALLOC Register",
+    "request for a new buffer",
+#endif
+    SBPM_REGS_BN_ALLOC_REG_OFFSET,
+    0,
+    0,
+    682,
+};
+
+/******************************************************************************
+ * Register: SBPM_REGS_BN_ALLOC_RPLY
+ ******************************************************************************/
+const ru_reg_rec SBPM_REGS_BN_ALLOC_RPLY_REG = 
+{
+    "REGS_BN_ALLOC_RPLY",
+#if RU_INCLUDE_DESC
+    "BN_ALLOC_RPLY Register",
+    "reply for a new buffer alloc",
+#endif
+    SBPM_REGS_BN_ALLOC_RPLY_REG_OFFSET,
+    0,
+    0,
+    683,
+};
+
+/******************************************************************************
+ * Register: SBPM_REGS_BN_CONNECT
+ ******************************************************************************/
+const ru_reg_rec SBPM_REGS_BN_CONNECT_REG = 
+{
+    "REGS_BN_CONNECT",
+#if RU_INCLUDE_DESC
+    "BN_CONNECT Register",
+    "request for connection between two buffers in a linked list. The connection request may be replied with ACK message if the ACK request bit is asserted."
+    "This command is used as write command.",
+#endif
+    SBPM_REGS_BN_CONNECT_REG_OFFSET,
+    0,
+    0,
+    688,
+};
+
+/******************************************************************************
+ * Register: SBPM_REGS_BN_CONNECT_RPLY
+ ******************************************************************************/
+const ru_reg_rec SBPM_REGS_BN_CONNECT_RPLY_REG = 
+{
+    "REGS_BN_CONNECT_RPLY",
+#if RU_INCLUDE_DESC
+    "BN_CONNECT_RPLY Register",
+    "bn_connect_rply",
+#endif
+    SBPM_REGS_BN_CONNECT_RPLY_REG_OFFSET,
+    0,
+    0,
+    689,
+};
+
+/******************************************************************************
+ * Register: SBPM_REGS_GET_NEXT
+ ******************************************************************************/
+const ru_reg_rec SBPM_REGS_GET_NEXT_REG = 
+{
+    "REGS_GET_NEXT",
+#if RU_INCLUDE_DESC
+    "GET_NEXT Register",
+    "a pointer to a buffer in a packet linked list and request for the next buffer in the list"
+    "this command is used as read command.",
+#endif
+    SBPM_REGS_GET_NEXT_REG_OFFSET,
+    0,
+    0,
+    690,
+};
+
+/******************************************************************************
+ * Register: SBPM_REGS_GET_NEXT_RPLY
+ ******************************************************************************/
+const ru_reg_rec SBPM_REGS_GET_NEXT_RPLY_REG = 
+{
+    "REGS_GET_NEXT_RPLY",
+#if RU_INCLUDE_DESC
+    "GET_NEXT_RPLY Register",
+    "get_next_rply",
+#endif
+    SBPM_REGS_GET_NEXT_RPLY_REG_OFFSET,
+    0,
+    0,
+    691,
+};
+
+/******************************************************************************
+ * Register: SBPM_REGS_BN_FREE_WITHOUT_CONTXT
+ ******************************************************************************/
+const ru_reg_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_REG = 
+{
+    "REGS_BN_FREE_WITHOUT_CONTXT",
+#if RU_INCLUDE_DESC
+    "BN_FREE_WITHOUT_CONTXT Register",
+    "bn_free_without_contxt",
+#endif
+    SBPM_REGS_BN_FREE_WITHOUT_CONTXT_REG_OFFSET,
+    0,
+    0,
+    693,
+};
+
+/******************************************************************************
+ * Register: SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY
+ ******************************************************************************/
+const ru_reg_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_REG = 
+{
+    "REGS_BN_FREE_WITHOUT_CONTXT_RPLY",
+#if RU_INCLUDE_DESC
+    "BN_FREE_WITHOUT_CONTXT_RPLY Register",
+    "bn_free_without_contxt_rply",
+#endif
+    SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_REG_OFFSET,
+    0,
+    0,
+    694,
+};
+
+
+/******************************************************************************
+ * Block: SBPM
+ ******************************************************************************/
+static const ru_reg_rec *SBPM_REGS[] =
+{
+    &SBPM_REGS_BN_ALLOC_REG,
+    &SBPM_REGS_BN_ALLOC_RPLY_REG,
+    &SBPM_REGS_BN_CONNECT_REG,
+    &SBPM_REGS_BN_CONNECT_RPLY_REG,
+    &SBPM_REGS_GET_NEXT_REG,
+    &SBPM_REGS_GET_NEXT_RPLY_REG,
+    &SBPM_REGS_BN_FREE_WITHOUT_CONTXT_REG,
+    &SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_REG,
+};
+
+unsigned long SBPM_ADDRS[] =
+{
+    0x828a1000,
+};
+
+const ru_block_rec SBPM_BLOCK = 
+{
+    "SBPM",
+    SBPM_ADDRS,
+    1,
+    53,
+    SBPM_REGS
+};
+
+/* End of file XRDP_SBPM.c */
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_UNIMAC_RDP_GPL.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_UNIMAC_RDP_GPL.c
new file mode 100644
index 0000000000..3ab723cfc6
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/XRDP_UNIMAC_RDP_GPL.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+const ru_reg_rec UNIMAC_RDP_COMMAND_CONFIG_REG = 
+{
+    "COMMAND_CONFIG",
+#if RU_INCLUDE_DESC
+    "Command register. Used by the host processor to control and configure the core",
+    "",
+#endif
+    UNIMAC_RDP_COMMAND_CONFIG_REG_OFFSET,
+    0,
+    0,
+    807,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+};
+
+/******************************************************************************
+ * Block: UNIMAC_RDP
+ ******************************************************************************/
+static const ru_reg_rec *UNIMAC_RDP_REGS[] =
+{
+    &UNIMAC_RDP_COMMAND_CONFIG_REG,
+};
+
+unsigned long UNIMAC_RDP_ADDRS[] =
+{
+    0x828a8004,
+    0x828a9004,
+    0x828aa004,
+    0x828ab004,
+    0x828ac004,
+    0x828ad004,
+    0x828ae004,
+    0x828af004,
+};
+
+const ru_block_rec UNIMAC_RDP_BLOCK = 
+{
+    "UNIMAC_RDP",
+    UNIMAC_RDP_ADDRS,
+    8,
+    177,
+    UNIMAC_RDP_REGS
+};
+
+/* End of file XRDP_UNIMAC_RDP.c */
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/data_path_init_basic_data.h b/arch/arm/mach-bcmbca/xrdp/bcm63146/data_path_init_basic_data.h
new file mode 100644
index 0000000000..30db6b0790
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/data_path_init_basic_data.h
@@ -0,0 +1,794 @@
+{ 0x408a0014 , 0x82a00000 },
+{ 0x408a0018 , 0x82c00000 },
+{ 0x408a001c , 0x82c00000 },
+{ 0x408a0020 , 0x82c80000 },
+{ 0x408a0024 , 0x82c80000 },
+{ 0x408a0028 , 0x82d00000 },
+{ 0x408a0004 , 0x82700000 },
+{ 0x408a0008 , 0x82900000 },
+{ 0x408a000c , 0x82900000 },
+{ 0x408a0010 , 0x82a00000 },
+{ 0x4089c008 , 0x20002 },
+{ 0x4089d008 , 0x20002 },
+{ 0x5700000 , 0x0 },
+{ 0x3000000 , 0x2000 },
+{ 0x82710000 , 0xfc000000 },
+{ 0x41710000 , 0x6008006 },
+{ 0x4171000c , 0x18008006 },
+{ 0x41710018 , 0x8026 },
+{ 0x41710024 , 0x5f80c0a },
+{ 0x41710028 , 0x2100c004 },
+{ 0x4171002c , 0xc4bcac },
+{ 0x41710030 , 0x7401a0b0 },
+{ 0x41710034 , 0x630105cc },
+{ 0x41710038 , 0xb8dcac },
+{ 0x4171003c , 0xf4fff3b0 },
+{ 0x41710040 , 0xe0a10684 },
+{ 0x41710044 , 0x17800006 },
+{ 0x41710048 , 0xe18d6a8 },
+{ 0x4171004c , 0x2100c004 },
+{ 0x41710050 , 0x8403f0b0 },
+{ 0x41710054 , 0x400c0b0 },
+{ 0x41710058 , 0x86a107cc },
+{ 0x4171005c , 0x21000004 },
+{ 0x41710060 , 0x2ec0036 },
+{ 0x41710064 , 0x42ec1036 },
+{ 0x41710068 , 0x83ec2036 },
+{ 0x4171006c , 0x3ed4036 },
+{ 0x41710070 , 0x83ed6036 },
+{ 0x41710074 , 0x3ee8036 },
+{ 0x41710078 , 0x83eea036 },
+{ 0x4171007c , 0x3efc036 },
+{ 0x41710080 , 0x83efe036 },
+{ 0x41710084 , 0x3f00037 },
+{ 0x41710088 , 0x83f02037 },
+{ 0x4171008c , 0x3f14037 },
+{ 0x41710090 , 0x83f16037 },
+{ 0x41710094 , 0x3f28037 },
+{ 0x41710098 , 0x83f2a037 },
+{ 0x4171009c , 0x3f3c037 },
+{ 0x417100a0 , 0x83f3e037 },
+{ 0x417100a4 , 0x820080c6 },
+{ 0x417100a8 , 0x1684ac },
+{ 0x417100ac , 0xc2dd8036 },
+{ 0x417100cc , 0x82 },
+{ 0x417100d0 , 0x82 },
+{ 0x417100d4 , 0x82 },
+{ 0x417100d8 , 0x82 },
+{ 0x417100dc , 0x82 },
+{ 0x417100e0 , 0x82 },
+{ 0x417100e4 , 0x82 },
+{ 0x417100e8 , 0x82 },
+{ 0x417100ec , 0x82 },
+{ 0x417100f0 , 0x82 },
+{ 0x417100f4 , 0xc2 },
+{ 0x417100f8 , 0x82 },
+{ 0x417100fc , 0x82 },
+{ 0x41710100 , 0x82 },
+{ 0x41710104 , 0x82 },
+{ 0x41710108 , 0x82 },
+{ 0x4171010c , 0x82 },
+{ 0x41710110 , 0x82 },
+{ 0x41710114 , 0x82 },
+{ 0x41710118 , 0x82 },
+{ 0x4171011c , 0x82 },
+{ 0x4171013c , 0x2ec0032 },
+{ 0x41710140 , 0x42ec1032 },
+{ 0x41710144 , 0x83ec2032 },
+{ 0x41710148 , 0x3ed4032 },
+{ 0x4171014c , 0x83ed6032 },
+{ 0x41710150 , 0x3ee8032 },
+{ 0x41710154 , 0x83eea032 },
+{ 0x41710158 , 0x3efc032 },
+{ 0x4171015c , 0x83efe032 },
+{ 0x41710160 , 0x3f00033 },
+{ 0x41710164 , 0x83f02033 },
+{ 0x41710168 , 0x3f14033 },
+{ 0x4171016c , 0x83f16033 },
+{ 0x41710170 , 0x3f28033 },
+{ 0x41710174 , 0x83f2a033 },
+{ 0x41710178 , 0x3f3c033 },
+{ 0x4171017c , 0x83f3e033 },
+{ 0x4171018c , 0x1008022 },
+{ 0x4171019c , 0x4400c0b0 },
+{ 0x417101a0 , 0x4d880b0 },
+{ 0x417101a4 , 0x1c69e },
+{ 0x417101a8 , 0x8001c480 },
+{ 0x417101ac , 0x140040b0 },
+{ 0x417101b0 , 0x2008630 },
+{ 0x417101b4 , 0x80008480 },
+{ 0x417101b8 , 0x2008634 },
+{ 0x417101bc , 0x22008638 },
+{ 0x417101c0 , 0x80008482 },
+{ 0x417101c4 , 0x2200863c },
+{ 0x417101c8 , 0x43008839 },
+{ 0x417101cc , 0x3006831 },
+{ 0x417101d0 , 0xc67ccc0a },
+{ 0x417101d4 , 0x6026ccac },
+{ 0x417101d8 , 0xc0aa8bac },
+{ 0x417101dc , 0x2000e696 },
+{ 0x417101e0 , 0x400d0b0 },
+{ 0x417101e4 , 0x4d8c0b0 },
+{ 0x417101e8 , 0x81d69e },
+{ 0x417101ec , 0xa001c680 },
+{ 0x417101f0 , 0x200d630 },
+{ 0x417101f4 , 0x8080d680 },
+{ 0x417101f8 , 0xb83bad },
+{ 0x417101fc , 0x200d634 },
+{ 0x41710200 , 0x2200d638 },
+{ 0x41710204 , 0x6082d680 },
+{ 0x41710208 , 0x8080d682 },
+{ 0x4171020c , 0x2200d63c },
+{ 0x41710210 , 0xc1c1a431 },
+{ 0x41710214 , 0x40060b1 },
+{ 0x41710218 , 0x400f0b0 },
+{ 0x4171021c , 0x80b981 },
+{ 0x41710220 , 0x400c0b0 },
+{ 0x41710224 , 0x400d0b0 },
+{ 0x41710228 , 0x400e0b0 },
+{ 0x4171022c , 0xc1dfc033 },
+{ 0x41710230 , 0x40220e84 },
+{ 0x41710234 , 0xab809006 },
+{ 0x41710238 , 0x41030b1 },
+{ 0x4171023c , 0x4200093c },
+{ 0x41710240 , 0x22983 },
+{ 0x41710244 , 0x68022989 },
+{ 0x41710248 , 0x3004931 },
+{ 0x4171024c , 0x40b85aad },
+{ 0x41710250 , 0xa00a84 },
+{ 0x41710254 , 0xa780c006 },
+{ 0x41710258 , 0x20805a87 },
+{ 0x4171025c , 0xe1805a97 },
+{ 0x41710260 , 0x20805a83 },
+{ 0x41710264 , 0xa0025295 },
+{ 0x41710268 , 0x2080da87 },
+{ 0x4171026c , 0xc2058b1 },
+{ 0x41710270 , 0x5cb1 },
+{ 0x41710274 , 0xa0024a85 },
+{ 0x41710278 , 0xe0145aad },
+{ 0x4171027c , 0xa082de95 },
+{ 0x41710280 , 0x80094aad },
+{ 0x41710284 , 0x4df50b1 },
+{ 0x41710288 , 0x40004a97 },
+{ 0x4171028c , 0x80824a81 },
+{ 0x41710290 , 0x2005a31 },
+{ 0x41710294 , 0xa8835a89 },
+{ 0x41710298 , 0x2005a35 },
+{ 0x4171029c , 0x40220e84 },
+{ 0x417102a0 , 0x9080a006 },
+{ 0x417102a4 , 0x4200093c },
+{ 0x417102a8 , 0x3000934 },
+{ 0x417102ac , 0xa00d84 },
+{ 0x417102b0 , 0x1281d006 },
+{ 0x417102b4 , 0xb84bad },
+{ 0x417102b8 , 0x20003a87 },
+{ 0x417102bc , 0xe1803997 },
+{ 0x417102c0 , 0x20804983 },
+{ 0x417102c4 , 0x4dfe0b1 },
+{ 0x417102c8 , 0x40050b1 },
+{ 0x417102cc , 0x200ff31 },
+{ 0x417102d0 , 0x40030b1 },
+{ 0x417102d4 , 0x6282cfa1 },
+{ 0x417102d8 , 0x6002de85 },
+{ 0x417102dc , 0x80a20e84 },
+{ 0x417102e0 , 0xc4003106 },
+{ 0x417102e4 , 0x20003e83 },
+{ 0x417102e8 , 0xa40986 },
+{ 0x417102ec , 0xb5009106 },
+{ 0x417102f0 , 0x8003c295 },
+{ 0x417102f4 , 0x8883ff89 },
+{ 0x417102f8 , 0x20805a83 },
+{ 0x417102fc , 0xf48b7a17 },
+{ 0x41710300 , 0x8000ef83 },
+{ 0x41710304 , 0xc6228026 },
+{ 0x41710308 , 0x240030b1 },
+{ 0x4171030c , 0x2ae09c2 },
+{ 0x41710310 , 0x8002c294 },
+{ 0x41710314 , 0x2000c686 },
+{ 0x41710318 , 0x200df30 },
+{ 0x4171031c , 0x6002c694 },
+{ 0x41710320 , 0x8081c680 },
+{ 0x41710324 , 0x200cf34 },
+{ 0x41710328 , 0x416e0b0 },
+{ 0x4171032c , 0xc0dcac },
+{ 0x41710330 , 0xb84bad },
+{ 0x41710334 , 0x408c0b0 },
+{ 0x41710338 , 0x4e5f0b0 },
+{ 0x4171033c , 0x400e0b1 },
+{ 0x41710340 , 0xb781 },
+{ 0x41710344 , 0x101cd0a8 },
+{ 0x41710348 , 0xaa81 },
+{ 0x4171034c , 0xc685 },
+{ 0x41710350 , 0x80230d84 },
+{ 0x41710354 , 0xe5802106 },
+{ 0x41710358 , 0x80c3b6d1 },
+{ 0x4171035c , 0xc203c080 },
+{ 0x41710360 , 0x101cd0a8 },
+{ 0x41710364 , 0x68acc7a8 },
+{ 0x41710368 , 0x8003ad85 },
+{ 0x4171036c , 0x8403d0b1 },
+{ 0x41710370 , 0x8083bd81 },
+{ 0x41710374 , 0x2280d68e },
+{ 0x41710378 , 0x1e04c2a8 },
+{ 0x4171037c , 0x86388026 },
+{ 0x41710380 , 0x408c0b1 },
+{ 0x41710384 , 0x80a10ecc },
+{ 0x41710388 , 0xd4008006 },
+{ 0x4171038c , 0x3180c738 },
+{ 0x41710390 , 0x2038d6ac },
+{ 0x41710394 , 0x43c3b6d1 },
+{ 0x417103a0 , 0xe008007 },
+{ 0x417103a4 , 0x2401c0b0 },
+{ 0x417103ac , 0xa080ca96 },
+{ 0x417103b0 , 0x418d0b0 },
+{ 0x417103b4 , 0x6002c680 },
+{ 0x417103b8 , 0xa001d680 },
+{ 0x417103bc , 0x16e0b0 },
+{ 0x417103c0 , 0xfa80 },
+{ 0x417103c4 , 0x408c0b0 },
+{ 0x417103c8 , 0x80a10784 },
+{ 0x417103cc , 0xf9802106 },
+{ 0x417103d0 , 0x80c1e6d4 },
+{ 0x417103d4 , 0xf200c006 },
+{ 0x417103d8 , 0x8081f784 },
+{ 0x417103dc , 0x8001e780 },
+{ 0x417103e0 , 0x2080d682 },
+{ 0x417103e4 , 0xf3c1e6d4 },
+{ 0x417103f0 , 0xc20d8b0 },
+{ 0x417103f4 , 0xe080c996 },
+{ 0x417103f8 , 0xdcb0 },
+{ 0x417103fc , 0xc88caa8 },
+{ 0x41710400 , 0xa0013681 },
+{ 0x41710404 , 0x6026ecac },
+{ 0x41710408 , 0x400c0b0 },
+{ 0x4171040c , 0x2000e796 },
+{ 0x41710410 , 0x400d0b0 },
+{ 0x41710414 , 0xc1c1a431 },
+{ 0x41710418 , 0x400f0b0 },
+{ 0x4171041c , 0x6a0a4a8 },
+{ 0x41710420 , 0x1f04c2a8 },
+{ 0x41710424 , 0x61cc0a8 },
+{ 0x41710428 , 0x1f04d0a8 },
+{ 0x4171042c , 0x7a465a9 },
+{ 0x41710430 , 0x80e980 },
+{ 0x41710434 , 0x2b8fba8 },
+{ 0x41710438 , 0x628a4a8 },
+{ 0x4171043c , 0x7915cda8 },
+{ 0x41710440 , 0x18c0a8 },
+{ 0x41710444 , 0x1d04d0a8 },
+{ 0x41710448 , 0x40a20884 },
+{ 0x4171044c , 0x2b811006 },
+{ 0x41710450 , 0x380e83c },
+{ 0x41710454 , 0x4380c83c },
+{ 0x41710458 , 0x410c0b0 },
+{ 0x4171045c , 0x821883 },
+{ 0x41710460 , 0x1400d0b0 },
+{ 0x41710464 , 0x88811889 },
+{ 0x41710468 , 0x81d69e },
+{ 0x4171046c , 0x4d8c0b0 },
+{ 0x41710470 , 0xa001c680 },
+{ 0x41710474 , 0x200d630 },
+{ 0x41710478 , 0x8080d680 },
+{ 0x4171047c , 0x200d634 },
+{ 0x41710480 , 0x2200d638 },
+{ 0x41710484 , 0x8082d680 },
+{ 0x41710488 , 0x8080d682 },
+{ 0x4171048c , 0x2200d63c },
+{ 0x41710490 , 0x6a0a4a8 },
+{ 0x41710494 , 0x90005cc },
+{ 0x41710498 , 0x1f0482a9 },
+{ 0x4171049c , 0x771d9da9 },
+{ 0x417104a0 , 0xc7198026 },
+{ 0x417104a4 , 0x628a4a8 },
+{ 0x417104a8 , 0xc84285cd },
+{ 0x417104ac , 0x340050b1 },
+{ 0x417104b0 , 0x4d830b1 },
+{ 0x417104b4 , 0x815a9f },
+{ 0x417104b8 , 0xa0823981 },
+{ 0x417104bc , 0x2805931 },
+{ 0x417104c0 , 0x80805a81 },
+{ 0x417104c4 , 0x2805935 },
+{ 0x417104c8 , 0x22805939 },
+{ 0x417104cc , 0x80824a81 },
+{ 0x417104d0 , 0x80004a83 },
+{ 0x417104d4 , 0x2280493d },
+{ 0x417104d8 , 0x240030b1 },
+{ 0x417104dc , 0xc6228026 },
+{ 0x417104e0 , 0x400b0b1 },
+{ 0x417104e4 , 0x2ae09c2 },
+{ 0x417104e8 , 0x2400d0b0 },
+{ 0x417104ec , 0x4d8c0b0 },
+{ 0x417104f0 , 0x81d69e },
+{ 0x417104f4 , 0xa001c680 },
+{ 0x417104f8 , 0x200d630 },
+{ 0x417104fc , 0xc1c1a431 },
+{ 0x41710500 , 0x8080d680 },
+{ 0x41710504 , 0x200d634 },
+{ 0x41710508 , 0x2200d638 },
+{ 0x4171050c , 0x8080d682 },
+{ 0x41710510 , 0xe008007 },
+{ 0x41710514 , 0x2200d63c },
+{ 0x41710518 , 0x2401c0b0 },
+{ 0x4171051c , 0x24010006 },
+{ 0x41710520 , 0x400a0b0 },
+{ 0x41710524 , 0x4e0b0b0 },
+{ 0x41710528 , 0x1a59e },
+{ 0x4171052c , 0x4081a580 },
+{ 0x41710530 , 0x140040b0 },
+{ 0x41710534 , 0x200b530 },
+{ 0x41710538 , 0x8080b580 },
+{ 0x4171053c , 0x200b534 },
+{ 0x41710540 , 0x2200b538 },
+{ 0x41710544 , 0x8080b582 },
+{ 0x41710548 , 0x2200b53c },
+{ 0x4171054c , 0x300a430 },
+{ 0x41710550 , 0x6cc550a },
+{ 0x41710554 , 0x43008439 },
+{ 0x41710558 , 0x280c430 },
+{ 0x4171055c , 0x7528026 },
+{ 0x41710560 , 0x414186cd },
+{ 0x41710564 , 0x2200043c },
+{ 0x41710568 , 0x476c0b0 },
+{ 0x4171056c , 0x41ee0b0 },
+{ 0x41710570 , 0xb8d5ac },
+{ 0x41710574 , 0x408f0b0 },
+{ 0x41710578 , 0xe0a10684 },
+{ 0x4171057c , 0x65812106 },
+{ 0x41710580 , 0xe041c7d0 },
+{ 0x41710584 , 0x5e01c006 },
+{ 0x41710588 , 0xe081d684 },
+{ 0x4171058c , 0xe001c680 },
+{ 0x41710590 , 0x2000e782 },
+{ 0x41710594 , 0xa341c7d0 },
+{ 0x417105a0 , 0x476c0b0 },
+{ 0x417105a4 , 0xb805ad },
+{ 0x417105a8 , 0xf680 },
+{ 0x417105ac , 0x40020b1 },
+{ 0x417105b0 , 0xc880 },
+{ 0x417105b4 , 0x84e5d0b0 },
+{ 0x417105b8 , 0x40030b1 },
+{ 0x417105bc , 0x81024b1 },
+{ 0x417105c0 , 0x40800b1 },
+{ 0x417105c4 , 0x400a8b1 },
+{ 0x417105c8 , 0x400e0b0 },
+{ 0x417105cc , 0x1081 },
+{ 0x417105d0 , 0xe1830a9 },
+{ 0x417105d4 , 0x68ac26a9 },
+{ 0x417105d8 , 0x6885 },
+{ 0x417105dc , 0x2280063c },
+{ 0x417105e0 , 0xc65e8026 },
+{ 0x417105e4 , 0x840300b1 },
+{ 0x417105e8 , 0x412208cc },
+{ 0x417105ec , 0x22800639 },
+{ 0x417105f0 , 0x1900280a },
+{ 0x417105f4 , 0x43c6d0a },
+{ 0x417105f8 , 0x203878ad },
+{ 0x417105fc , 0x87014006 },
+{ 0x41710600 , 0xc0eba8 },
+{ 0x41710604 , 0x40050b1 },
+{ 0x41710608 , 0x40040b1 },
+{ 0x4171060c , 0x840300b1 },
+{ 0x41710610 , 0x385da9 },
+{ 0x41710614 , 0x10b85ba9 },
+{ 0x41710618 , 0x842208cc },
+{ 0x4171061c , 0xc0220684 },
+{ 0x41710620 , 0x91816106 },
+{ 0x41710624 , 0x109c78a9 },
+{ 0x41710628 , 0xc0c2fbd4 },
+{ 0x4171062c , 0xc002c684 },
+{ 0x41710630 , 0xc082f780 },
+{ 0x41710634 , 0x7701c006 },
+{ 0x41710638 , 0x80ab81 },
+{ 0x4171063c , 0x40010b1 },
+{ 0x41710640 , 0x40860b1 },
+{ 0x41710644 , 0x93c1fbd4 },
+{ 0x41710650 , 0x80ab81 },
+{ 0x41710654 , 0x2280c638 },
+{ 0x41710658 , 0x800e60a },
+{ 0x4171065c , 0x1304b0a8 },
+{ 0x41710660 , 0x4097a9 },
+{ 0x41710664 , 0x4c8da9 },
+{ 0x41710668 , 0x280c430 },
+{ 0x4171066c , 0x7528026 },
+{ 0x41710670 , 0x414186cd },
+{ 0x41710674 , 0x2200043c },
+{ 0x41710678 , 0x33c0d0a },
+{ 0x4171067c , 0x9004007 },
+{ 0x41710680 , 0x8403c0b0 },
+{ 0x41710684 , 0x7528026 },
+{ 0x41710688 , 0x2200043c },
+{ 0x4080004c , 0x4 },
+{ 0x40800040 , 0x800000 },
+{ 0x40800044 , 0x820 },
+{ 0x41718000 , 0x9c010000 },
+{ 0x41718024 , 0x10 },
+{ 0x41718028 , 0x12000000 },
+{ 0x4171802c , 0x0 },
+{ 0x41718040 , 0x40010000 },
+{ 0x41718044 , 0x0 },
+{ 0x41718048 , 0xf0000000 },
+{ 0x41718080 , 0x20050000 },
+{ 0x417180a0 , 0x600d0000 },
+{ 0x417180a4 , 0x7c0d0000 },
+{ 0x21700dfc , 0xf000 },
+{ 0x1170123e , 0x0 },
+{ 0x11701242 , 0x8 },
+{ 0x11701246 , 0x10 },
+{ 0x1170124a , 0x18 },
+{ 0x1170124e , 0x20 },
+{ 0x11701252 , 0x28 },
+{ 0x11701256 , 0x30 },
+{ 0x1170125a , 0x38 },
+{ 0x40800000 , 0x1027000 },
+{ 0x40801000 , 0x1027000 },
+{ 0x40808500 , 0x420 },
+{ 0x40808840 , 0x8 },
+{ 0x40808844 , 0x8 },
+{ 0x40808848 , 0x8 },
+{ 0x4080884c , 0x8 },
+{ 0x40898020 , 0x404 },
+{ 0x40898004 , 0x0 },
+{ 0x40898028 , 0x5ee05ee },
+{ 0x40898024 , 0x40404040 },
+{ 0x4089802c , 0x5ee05ee },
+{ 0x40898030 , 0x0 },
+{ 0x40898044 , 0xff },
+{ 0x40898034 , 0x0 },
+{ 0x40898420 , 0x404 },
+{ 0x40898404 , 0x101 },
+{ 0x40898428 , 0x5ee05ee },
+{ 0x40898424 , 0x40404040 },
+{ 0x4089842c , 0x5ee05ee },
+{ 0x40898430 , 0x0 },
+{ 0x40898444 , 0xff },
+{ 0x40898434 , 0x0 },
+{ 0x40898820 , 0x404 },
+{ 0x40898804 , 0x202 },
+{ 0x40898828 , 0x5ee05ee },
+{ 0x40898824 , 0x40404040 },
+{ 0x4089882c , 0x5ee05ee },
+{ 0x40898830 , 0x0 },
+{ 0x40898844 , 0xff },
+{ 0x40898834 , 0x0 },
+{ 0x40898c20 , 0x404 },
+{ 0x40898c04 , 0x303 },
+{ 0x40898c28 , 0x5ee05ee },
+{ 0x40898c24 , 0x40404040 },
+{ 0x40898c2c , 0x5ee05ee },
+{ 0x40898c30 , 0x0 },
+{ 0x40898c44 , 0xff },
+{ 0x40898c34 , 0x0 },
+{ 0x40899020 , 0x404 },
+{ 0x40899004 , 0x404 },
+{ 0x40899028 , 0x5ee05ee },
+{ 0x40899024 , 0x40404040 },
+{ 0x4089902c , 0x5ee05ee },
+{ 0x40899030 , 0x0 },
+{ 0x40899044 , 0xff },
+{ 0x40899034 , 0x0 },
+{ 0x40899420 , 0x404 },
+{ 0x40899404 , 0x505 },
+{ 0x40899428 , 0x5ee05ee },
+{ 0x40899424 , 0x40404040 },
+{ 0x4089942c , 0x5ee05ee },
+{ 0x40899430 , 0x0 },
+{ 0x40899444 , 0xff },
+{ 0x40899434 , 0x0 },
+{ 0x40899820 , 0x404 },
+{ 0x40899804 , 0x606 },
+{ 0x40899828 , 0x5ee05ee },
+{ 0x40899824 , 0x40404040 },
+{ 0x4089982c , 0x5ee05ee },
+{ 0x40899830 , 0x0 },
+{ 0x40899844 , 0xff },
+{ 0x40899834 , 0x0 },
+{ 0x40899c20 , 0x404 },
+{ 0x40899c04 , 0x707 },
+{ 0x40899c28 , 0x5ee05ee },
+{ 0x40899c24 , 0x40404040 },
+{ 0x40899c2c , 0x5ee05ee },
+{ 0x40899c30 , 0x0 },
+{ 0x40899c44 , 0xff },
+{ 0x40899c34 , 0x0 },
+{ 0x40890020 , 0x80400 },
+{ 0x40890024 , 0x80410 },
+{ 0x4089000c , 0x20200000 },
+{ 0x40890018 , 0x101d0 },
+{ 0x40890400 , 0x0 },
+{ 0x40890450 , 0x0 },
+{ 0x408904b0 , 0x0 },
+{ 0x408904a0 , 0x70007 },
+{ 0x408904a4 , 0x0 },
+{ 0x408904a8 , 0x0 },
+{ 0x40890908 , 0x1000000 },
+{ 0x40890920 , 0x1400000 },
+{ 0x40890940 , 0x13f013f },
+{ 0x40890960 , 0x280000 },
+{ 0x40890980 , 0x270027 },
+{ 0x408900bc , 0x3 },
+{ 0x408907a4 , 0x0 },
+{ 0x408907a8 , 0xfff0fff },
+{ 0x40890908 , 0x1000001 },
+{ 0x40890924 , 0x3c00280 },
+{ 0x40890944 , 0x13f013f },
+{ 0x40890964 , 0x780050 },
+{ 0x40890984 , 0x270027 },
+{ 0x40890908 , 0x1000002 },
+{ 0x40890928 , 0x6400500 },
+{ 0x40890948 , 0x13f013f },
+{ 0x40890968 , 0xc800a0 },
+{ 0x40890988 , 0x270027 },
+{ 0x408907b8 , 0x2 },
+{ 0x40890908 , 0x1000003 },
+{ 0x4089094c , 0x13f013f },
+{ 0x4089096c , 0x0 },
+{ 0x4089098c , 0x270027 },
+{ 0x40890600 , 0x0 },
+{ 0x40890604 , 0x1 },
+{ 0x4089090c , 0x3f },
+{ 0x40890020 , 0xc0400 },
+{ 0x40890024 , 0xc0410 },
+{ 0x4089003c , 0x12047c5e },
+{ 0x408a1000 , 0x5fc000 },
+{ 0x408a1050 , 0xa015f },
+{ 0x408a118c , 0x60000001 },
+{ 0x408a1868 , 0x4 },
+{ 0x408a186c , 0x4 },
+{ 0x408a1870 , 0x4 },
+{ 0x408a1874 , 0x4 },
+{ 0x408a1878 , 0x4 },
+{ 0x408a187c , 0x4 },
+{ 0x408a18f4 , 0x30807 },
+{ 0x408a18f4 , 0x807 },
+{ 0x408a1c64 , 0x80 },
+{ 0x408a1c68 , 0x80 },
+{ 0x408a1c6c , 0x80 },
+{ 0x408a1c70 , 0x0 },
+{ 0x408a1c74 , 0x0 },
+{ 0x408a1c78 , 0x0 },
+{ 0x408a1c7c , 0x0 },
+{ 0x408a1cf4 , 0x30807 },
+{ 0x408a1cf4 , 0x807 },
+{ 0x3000000 , 0x20 },
+{ 0x82880080 , 0xfff00f3f },
+{ 0x3000000 , 0x20 },
+{ 0x82880100 , 0xfff00f3f },
+{ 0x40880180 , 0x7f1ff1ff },
+{ 0x40880184 , 0xa0c80a8 },
+{ 0x7000000 , 0x1ff },
+{ 0x82883000 , 0x40004 },
+{ 0x4088270c , 0x1ff },
+{ 0x40882714 , 0x200 },
+{ 0x40882708 , 0x200 },
+{ 0x40880080 , 0x7f1ff1ff },
+{ 0x40880100 , 0x7f1ff1ff },
+{ 0x40880400 , 0x2001f },
+{ 0x40880620 , 0x1 },
+{ 0x40880300 , 0x41c1 },
+{ 0x40880380 , 0x400 },
+{ 0x40882700 , 0x1 },
+{ 0x40882704 , 0x1 },
+{ 0x40880990 , 0x1f },
+{ 0x40880084 , 0x7f1ff1ff },
+{ 0x40880104 , 0x7f1ff1ff },
+{ 0x40880404 , 0x20021 },
+{ 0x40880620 , 0x3 },
+{ 0x40880304 , 0x41c1 },
+{ 0x40880384 , 0x400 },
+{ 0x40882020 , 0x1 },
+{ 0x4088202c , 0x1 },
+{ 0x40882700 , 0x2 },
+{ 0x40882704 , 0x2 },
+{ 0x40880990 , 0x1f },
+{ 0x40880088 , 0x7f1ff1ff },
+{ 0x40880108 , 0x7f1ff1ff },
+{ 0x40880408 , 0x20023 },
+{ 0x40880620 , 0x7 },
+{ 0x40880308 , 0x41c1 },
+{ 0x40880388 , 0x400 },
+{ 0x40882040 , 0x2 },
+{ 0x4088204c , 0x2 },
+{ 0x40882700 , 0x3 },
+{ 0x40882704 , 0x3 },
+{ 0x40880990 , 0x1f },
+{ 0x4088008c , 0x7f1ff1ff },
+{ 0x4088010c , 0x7f1ff1ff },
+{ 0x4088040c , 0x20025 },
+{ 0x40880620 , 0xf },
+{ 0x4088030c , 0x41c1 },
+{ 0x4088038c , 0x400 },
+{ 0x40882060 , 0x3 },
+{ 0x4088206c , 0x3 },
+{ 0x40882700 , 0x4 },
+{ 0x40882704 , 0x4 },
+{ 0x40880990 , 0x1f },
+{ 0x40880090 , 0x7f1ff1ff },
+{ 0x40880110 , 0x7f1ff1ff },
+{ 0x40880410 , 0x20027 },
+{ 0x40880620 , 0x1f },
+{ 0x40880310 , 0x41c1 },
+{ 0x40880390 , 0x400 },
+{ 0x40882080 , 0x4 },
+{ 0x4088208c , 0x4 },
+{ 0x40882700 , 0x5 },
+{ 0x40882704 , 0x5 },
+{ 0x40880990 , 0x1f },
+{ 0x40880094 , 0x7f1ff1ff },
+{ 0x40880114 , 0x7f1ff1ff },
+{ 0x40880414 , 0x20029 },
+{ 0x40880620 , 0x3f },
+{ 0x40880314 , 0x41c1 },
+{ 0x40880394 , 0x400 },
+{ 0x408820a0 , 0x5 },
+{ 0x408820ac , 0x5 },
+{ 0x40882700 , 0x6 },
+{ 0x40882704 , 0x6 },
+{ 0x40880990 , 0x1f },
+{ 0x40880098 , 0x7f1ff1ff },
+{ 0x40880118 , 0x7f1ff1ff },
+{ 0x40880418 , 0x2002b },
+{ 0x40880620 , 0x7f },
+{ 0x40880318 , 0x41c1 },
+{ 0x40880398 , 0x400 },
+{ 0x408820c0 , 0x6 },
+{ 0x408820cc , 0x6 },
+{ 0x40882700 , 0x7 },
+{ 0x40882704 , 0x7 },
+{ 0x40880990 , 0x1f },
+{ 0x4088009c , 0x7f1ff1ff },
+{ 0x4088011c , 0x7f1ff1ff },
+{ 0x4088041c , 0x2002d },
+{ 0x40880620 , 0xff },
+{ 0x4088031c , 0x41c1 },
+{ 0x4088039c , 0x400 },
+{ 0x408820e0 , 0x7 },
+{ 0x408820ec , 0x7 },
+{ 0x40882700 , 0x8 },
+{ 0x40882704 , 0x8 },
+{ 0x40880990 , 0x1f },
+{ 0x408800a0 , 0x7f1ff1ff },
+{ 0x40880120 , 0x7f1ff1ff },
+{ 0x40880420 , 0x20035 },
+{ 0x40880620 , 0x1ff },
+{ 0x40880320 , 0x41c1 },
+{ 0x408803a0 , 0x400 },
+{ 0x40882100 , 0x8 },
+{ 0x4088210c , 0x8 },
+{ 0x40882700 , 0x9 },
+{ 0x40882704 , 0x9 },
+{ 0x40880990 , 0x1f },
+{ 0x408800a4 , 0x7f1ff1ff },
+{ 0x40880124 , 0x7f1ff1ff },
+{ 0x40880424 , 0x3001f },
+{ 0x40880620 , 0x3ff },
+{ 0x40880324 , 0x1c1 },
+{ 0x408803a4 , 0x400 },
+{ 0x40882120 , 0x9 },
+{ 0x4088212c , 0x9 },
+{ 0x40882700 , 0xa },
+{ 0x40882704 , 0xa },
+{ 0x40880990 , 0x1f },
+{ 0x408800a8 , 0x7f1ff1ff },
+{ 0x40880128 , 0x7f1ff1ff },
+{ 0x40880428 , 0x30021 },
+{ 0x40880620 , 0x7ff },
+{ 0x40880328 , 0x1c1 },
+{ 0x408803a8 , 0x400 },
+{ 0x40882140 , 0xa },
+{ 0x4088214c , 0xa },
+{ 0x40882700 , 0xb },
+{ 0x40882704 , 0xb },
+{ 0x40880990 , 0x1f },
+{ 0x408800ac , 0x7f1ff1ff },
+{ 0x4088012c , 0x7f1ff1ff },
+{ 0x4088042c , 0x30023 },
+{ 0x40880620 , 0xfff },
+{ 0x4088032c , 0x1c1 },
+{ 0x408803ac , 0x400 },
+{ 0x40882160 , 0xb },
+{ 0x4088216c , 0xb },
+{ 0x40882700 , 0xc },
+{ 0x40882704 , 0xc },
+{ 0x40880990 , 0x1f },
+{ 0x408800b0 , 0x7f1ff1ff },
+{ 0x40880130 , 0x7f1ff1ff },
+{ 0x40880430 , 0x11ae0000 },
+{ 0x408804c0 , 0x1000 },
+{ 0x40880620 , 0x1fff },
+{ 0x40880330 , 0x41c1 },
+{ 0x40882180 , 0xc },
+{ 0x4088218c , 0xc },
+{ 0x40882700 , 0xd },
+{ 0x40882704 , 0xd },
+{ 0x40880990 , 0x1f },
+{ 0x408800b4 , 0x7f1ff1ff },
+{ 0x40880134 , 0x7f1ff1ff },
+{ 0x40880434 , 0x30027 },
+{ 0x40880620 , 0x3fff },
+{ 0x40880334 , 0x1c1 },
+{ 0x408803b4 , 0x400 },
+{ 0x408821a0 , 0xd },
+{ 0x408821ac , 0xd },
+{ 0x40882700 , 0xe },
+{ 0x40882704 , 0xe },
+{ 0x40880990 , 0x1f },
+{ 0x408800b8 , 0x7f1ff1ff },
+{ 0x40880138 , 0x7f1ff1ff },
+{ 0x40880438 , 0x30029 },
+{ 0x40880620 , 0x7fff },
+{ 0x40880338 , 0x1c1 },
+{ 0x408803b8 , 0x400 },
+{ 0x408821c0 , 0xe },
+{ 0x408821cc , 0xe },
+{ 0x40882700 , 0xf },
+{ 0x40882704 , 0xf },
+{ 0x40880990 , 0x1f },
+{ 0x408800bc , 0x7f1ff1ff },
+{ 0x4088013c , 0x7f1ff1ff },
+{ 0x4088043c , 0x3002b },
+{ 0x40880620 , 0xffff },
+{ 0x4088033c , 0x1c1 },
+{ 0x408803bc , 0x400 },
+{ 0x408821e0 , 0xf },
+{ 0x408821ec , 0xf },
+{ 0x40882700 , 0x10 },
+{ 0x40882704 , 0x10 },
+{ 0x40880990 , 0x1f },
+{ 0x408800c0 , 0x7f1ff1ff },
+{ 0x40880140 , 0x7f1ff1ff },
+{ 0x40880440 , 0x3002d },
+{ 0x40880620 , 0x1ffff },
+{ 0x40880340 , 0x1c1 },
+{ 0x408803c0 , 0x400 },
+{ 0x40882200 , 0x10 },
+{ 0x4088220c , 0x10 },
+{ 0x40882700 , 0x11 },
+{ 0x40882704 , 0x11 },
+{ 0x40880990 , 0x1f },
+{ 0x408800c4 , 0x0 },
+{ 0x40880144 , 0x0 },
+{ 0x40880624 , 0x20000 },
+{ 0x40882220 , 0x11 },
+{ 0x4088222c , 0x11 },
+{ 0x40882700 , 0x12 },
+{ 0x40882704 , 0x12 },
+{ 0x40880990 , 0x1f },
+{ 0x40880520 , 0x1 },
+{ 0x40880604 , 0x3f },
+{ 0x40880900 , 0x1 },
+{ 0x40880480 , 0x28 },
+{ 0x408804d0 , 0x15a },
+{ 0x408804d8 , 0xa6 },
+{ 0x408804d4 , 0x15a },
+{ 0x408804dc , 0xa6 },
+{ 0x40880980 , 0x100 },
+{ 0x40880004 , 0x1feff },
+{ 0x40880850 , 0x201 },
+{ 0x4089803c , 0x3 },
+{ 0x4089843c , 0x3 },
+{ 0x4089883c , 0x3 },
+{ 0x40898c3c , 0x3 },
+{ 0x4089903c , 0x3 },
+{ 0x4089943c , 0x3 },
+{ 0x4089983c , 0x3 },
+{ 0x40899c3c , 0x3 },
+{ 0x40880000 , 0x101 },
+{ 0x40c00000 , 0x307 },
+{ 0x4089c000 , 0x1 },
+{ 0x4089d000 , 0x1 },
+{ 0x40800000 , 0x1027001 },
+{ 0x408a8008 , 0x41c000db },
+{ 0x408a8340 , 0x32 },
+{ 0x408b0044 , 0x1 },
+{ 0x408a9008 , 0x41c000db },
+{ 0x408a9340 , 0x32 },
+{ 0x408b0444 , 0x1 },
+{ 0x408aa008 , 0x41c000db },
+{ 0x408aa340 , 0x32 },
+{ 0x408b0844 , 0x1 },
+{ 0x408ab008 , 0x41c000db },
+{ 0x408ab340 , 0x32 },
+{ 0x408b0c44 , 0x1 },
+{ 0x408ac008 , 0x41c000db },
+{ 0x408ac340 , 0x32 },
+{ 0x408b1044 , 0x1 },
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_data_structures_auto.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_data_structures_auto.c
new file mode 100644
index 0000000000..0d3f2fa184
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_data_structures_auto.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+
+
+/* This is an automated file. Do not edit its contents. */
+
+
+#include "rdd.h"
+#include "ru_types.h"
+
+#include "rdd_data_structures_auto.h"
+
+/* >>>RDD_SRAM_PD_FIFO_ADDRESS_ARR */
+uint32_t RDD_SRAM_PD_FIFO_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0x0,
+};
+/* <<<RDD_SRAM_PD_FIFO_ADDRESS_ARR */
+
+
+/* >>>RDD_US_TM_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS_ARR */
+uint32_t RDD_US_TM_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0x100,
+};
+/* <<<RDD_US_TM_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS_ARR */
+
+
+/* >>>RDD_DIRECT_PROCESSING_PD_TABLE_ADDRESS_ARR */
+uint32_t RDD_DIRECT_PROCESSING_PD_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0x140,
+};
+/* <<<RDD_DIRECT_PROCESSING_PD_TABLE_ADDRESS_ARR */
+
+
+/* >>>RDD_CPU_RX_SCRATCHPAD_ADDRESS_ARR */
+uint32_t RDD_CPU_RX_SCRATCHPAD_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0x160,
+};
+/* <<<RDD_CPU_RX_SCRATCHPAD_ADDRESS_ARR */
+
+
+/* >>>RDD_CPU_TX_SCRATCHPAD_ADDRESS_ARR */
+uint32_t RDD_CPU_TX_SCRATCHPAD_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0x760,
+};
+/* <<<RDD_CPU_TX_SCRATCHPAD_ADDRESS_ARR */
+
+
+/* >>>RDD_BBH_TX_RING_TABLE_ADDRESS_ARR */
+uint32_t RDD_BBH_TX_RING_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xd60,
+};
+/* <<<RDD_BBH_TX_RING_TABLE_ADDRESS_ARR */
+
+
+/* >>>RDD_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS_ARR */
+uint32_t RDD_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xd70,
+};
+/* <<<RDD_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS_ARR */
+
+
+/* >>>RDD_BBH_TX_BB_DESTINATION_TABLE_ADDRESS_ARR */
+uint32_t RDD_BBH_TX_BB_DESTINATION_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xd7c,
+};
+/* <<<RDD_BBH_TX_BB_DESTINATION_TABLE_ADDRESS_ARR */
+
+
+/* >>>RDD_CPU_RX_CFE_SRAM_COUNTERS_ADDRESS_ARR */
+uint32_t RDD_CPU_RX_CFE_SRAM_COUNTERS_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xd80,
+};
+/* <<<RDD_CPU_RX_CFE_SRAM_COUNTERS_ADDRESS_ARR */
+
+
+/* >>>RDD_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS_ARR */
+uint32_t RDD_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xdd0,
+};
+/* <<<RDD_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS_ARR */
+
+
+/* >>>RDD_TASK_IDX_ADDRESS_ARR */
+uint32_t RDD_TASK_IDX_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xddc,
+};
+/* <<<RDD_TASK_IDX_ADDRESS_ARR */
+
+
+/* >>>RDD_CPU_RX_INTERRUPT_SCRATCH_ADDRESS_ARR */
+uint32_t RDD_CPU_RX_INTERRUPT_SCRATCH_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xde0,
+};
+/* <<<RDD_CPU_RX_INTERRUPT_SCRATCH_ADDRESS_ARR */
+
+
+/* >>>RDD_CPU_RX_INTERRUPT_ID_DDR_ADDR_ADDRESS_ARR */
+uint32_t RDD_CPU_RX_INTERRUPT_ID_DDR_ADDR_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xde8,
+};
+/* <<<RDD_CPU_RX_INTERRUPT_ID_DDR_ADDR_ADDRESS_ARR */
+
+
+/* >>>RDD_PKT_BUFFER_ALLOC_MAP_TABLE_ADDRESS_ARR */
+uint32_t RDD_PKT_BUFFER_ALLOC_MAP_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xdf0,
+};
+/* <<<RDD_PKT_BUFFER_ALLOC_MAP_TABLE_ADDRESS_ARR */
+
+
+/* >>>RDD_CPU_RX_LAST_READ_INDEX_ADDRESS_ARR */
+uint32_t RDD_CPU_RX_LAST_READ_INDEX_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xdfc,
+};
+/* <<<RDD_CPU_RX_LAST_READ_INDEX_ADDRESS_ARR */
+
+
+/* >>>RDD_SRAM_DUMMY_STORE_ADDRESS_ARR */
+uint32_t RDD_SRAM_DUMMY_STORE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xdfe,
+};
+/* <<<RDD_SRAM_DUMMY_STORE_ADDRESS_ARR */
+
+
+/* >>>RDD_CPU_TX_CFE_SRAM_COUNTERS_ADDRESS_ARR */
+uint32_t RDD_CPU_TX_CFE_SRAM_COUNTERS_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xe00,
+};
+/* <<<RDD_CPU_TX_CFE_SRAM_COUNTERS_ADDRESS_ARR */
+
+
+/* >>>RDD_CPU_RX_BB_REPLY_ADDR_TABLE_ADDRESS_ARR */
+uint32_t RDD_CPU_RX_BB_REPLY_ADDR_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xe50,
+};
+/* <<<RDD_CPU_RX_BB_REPLY_ADDR_TABLE_ADDRESS_ARR */
+
+
+/* >>>RDD_CPU_TX_BB_REPLY_ADDR_TABLE_ADDRESS_ARR */
+uint32_t RDD_CPU_TX_BB_REPLY_ADDR_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xe58,
+};
+/* <<<RDD_CPU_TX_BB_REPLY_ADDR_TABLE_ADDRESS_ARR */
+
+
+/* >>>RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS_ARR */
+uint32_t RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xe80,
+};
+/* <<<RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS_ARR */
+
+
+/* >>>RDD_REGISTERS_BUFFER_ADDRESS_ARR */
+uint32_t RDD_REGISTERS_BUFFER_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0xec0,
+};
+/* <<<RDD_REGISTERS_BUFFER_ADDRESS_ARR */
+
+
+/* >>>RDD_RX_FLOW_TABLE_ADDRESS_ARR */
+uint32_t RDD_RX_FLOW_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM] = {
+	0x1000,
+};
+/* <<<RDD_RX_FLOW_TABLE_ADDRESS_ARR */
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_data_structures_auto.h b/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_data_structures_auto.h
new file mode 100644
index 0000000000..f0f637d69c
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_data_structures_auto.h
@@ -0,0 +1,6131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+
+
+/* This is an automated file. Do not edit its contents. */
+
+
+#ifndef _RDD_DATA_STRUCTURES_AUTO_H_
+#define _RDD_DATA_STRUCTURES_AUTO_H_
+
+#define GROUPED_EN_SEGMENTS_NUM       1
+#define INVALID_TABLE_ADDRESS         0xFFFFFF
+
+#ifdef __clang__
+#define ALIGNMENT8 __attribute__((align_value(8)))
+#else
+#define ALIGNMENT8
+#endif
+
+
+/* DDR */
+/* PSRAM */
+/* CORE_0 */
+
+/* >>>SRAM_PD_FIFO */
+
+/* >>>RDD_PROCESSING_TX_DESCRIPTOR_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	valid         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	headroom      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	dont_agg      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	mc_copy       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reprocess     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	color         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	force_copy    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	second_level_q	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	first_level_q 	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_valid         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_headroom      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_dont_agg      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_mc_copy       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_reprocess     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_color         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_force_copy    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_second_level_q	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_first_level_q 	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_valid         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_headroom      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_dont_agg      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_mc_copy       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_reprocess     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_color         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_force_copy    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_second_level_q	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_first_level_q 	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_valid         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_headroom      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_dont_agg      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_mc_copy       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reprocess     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_color         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_force_copy    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_second_level_q	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_first_level_q 	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_valid         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_headroom      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_dont_agg      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_mc_copy       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_reprocess     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_color         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_force_copy    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_second_level_q	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_first_level_q 	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 1 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	serial_num    	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	priority      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_serial_num    	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_priority      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_serial_num    	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_priority      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_serial_num    	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_priority      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_serial_num    	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_priority      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 2 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	drop          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	cong_state_stream	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ingress_port  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	union3        	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_drop          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	target_mem_1            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cong_state_stream union */
+			uint32_t	cong_state              	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cong_state_stream union */
+			uint32_t	reserved1_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	flow                    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	bn1_first               	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of union3 union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_drop          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	stream_id               	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cong_state_stream union */
+			uint32_t	reserved2_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	source_port             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved1               	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of union3 union */
+			uint32_t	abs_1                   	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of union3 union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_drop          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_cong_state_stream	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	lag_port                	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	lan_vport               	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved3_union3        	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_drop          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_cong_state_stream	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	is_vport                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	flow_id                 	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved4_union3        	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 3 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	sop_fpm                 	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	bn_fpm                  	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	bn_num                  	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	sop                     	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint16_t	bn0_first               	; /* Member of payload_offset_sop union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	abs_0                   	:29	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+#else
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	first_level_q 	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	second_level_q	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	force_copy    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	color         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reprocess     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	mc_copy       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	dont_agg      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	headroom      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	valid         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_first_level_q 	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_second_level_q	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_force_copy    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_color         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_reprocess     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_mc_copy       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_dont_agg      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_headroom      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_valid         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_first_level_q 	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_second_level_q	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_force_copy    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_color         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_reprocess     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_mc_copy       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_dont_agg      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_headroom      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_valid         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_first_level_q 	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_second_level_q	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_force_copy    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_color         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reprocess     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_mc_copy       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_dont_agg      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_headroom      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_valid         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_first_level_q 	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_second_level_q	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_force_copy    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_color         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_reprocess     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_mc_copy       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_dont_agg      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_headroom      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_valid         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 1 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	priority      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	serial_num    	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_priority      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_serial_num    	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_priority      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_serial_num    	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_priority      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_serial_num    	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_priority      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_serial_num    	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 2 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	union3        	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	ingress_port  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	cong_state_stream	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	drop          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	bn1_first               	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of union3 union */
+			uint32_t	flow                    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved1_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	target_mem_1            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cong_state_stream union */
+			uint32_t	cong_state              	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cong_state_stream union */
+			uint32_t	reserved1_drop          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved1               	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of union3 union */
+			uint32_t	abs_1                   	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of union3 union */
+			uint32_t	source_port             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved2_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	stream_id               	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cong_state_stream union */
+			uint32_t	reserved2_drop          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_union3        	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	lag_port                	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	lan_vport               	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved3_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_cong_state_stream	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_drop          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_union3        	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	is_vport                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	flow_id                 	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved4_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_cong_state_stream	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_drop          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 3 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	sop_fpm                 	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	bn_fpm                  	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	reserved1_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	bn_num                  	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	sop                     	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint16_t	bn0_first               	; /* Member of payload_offset_sop union */
+			uint32_t	reserved2_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	abs_0                   	:29	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	reserved3_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PROCESSING_TX_DESCRIPTOR_DTS;
+
+typedef union
+{
+    uint32_t word_val[4];
+    uint64_t dword_val64[2];
+    RDD_PROCESSING_TX_DESCRIPTOR_DTS fields;
+} PROCESSING_TX_DESCRIPTOR_STRUCT;
+#define RDD_PROCESSING_TX_DESCRIPTOR_VALID_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 7, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_VALID_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 7, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_VALID_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_VALID_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_HEADROOM_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 6, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_HEADROOM_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 6, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_HEADROOM_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p, 6, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_HEADROOM_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p, 6, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_DONT_AGG_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 5, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_DONT_AGG_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 5, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_DONT_AGG_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p, 5, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_DONT_AGG_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p, 5, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_MC_COPY_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 4, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_MC_COPY_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 4, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_MC_COPY_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p, 4, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_MC_COPY_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p, 4, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_REPROCESS_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 3, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_REPROCESS_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 3, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_REPROCESS_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p, 3, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_REPROCESS_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p, 3, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_COLOR_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 2, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_COLOR_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 2, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_COLOR_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p, 2, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_COLOR_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p, 2, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FORCE_COPY_READ_G(r, g, idx)              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 1, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FORCE_COPY_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 1, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FORCE_COPY_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p, 1, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FORCE_COPY_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p, 1, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SECOND_LEVEL_Q_READ_G(r, g, idx)          GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 0, 9, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SECOND_LEVEL_Q_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS), 0, 9, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SECOND_LEVEL_Q_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p, 0, 9, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SECOND_LEVEL_Q_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p, 0, 9, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FIRST_LEVEL_Q_READ_G(r, g, idx)           GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 2, 7, 9, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FIRST_LEVEL_Q_WRITE_G(v, g, idx)          GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 2, 7, 9, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FIRST_LEVEL_Q_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p + 2, 7, 9, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FIRST_LEVEL_Q_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p + 2, 7, 9, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLAG_1588_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 3, 6, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLAG_1588_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 3, 6, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLAG_1588_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 3, 6, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLAG_1588_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 3, 6, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_COHERENT_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 3, 5, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_COHERENT_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 3, 5, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_COHERENT_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 3, 5, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_COHERENT_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 3, 5, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_HN_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 3, 0, 5, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_HN_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 3, 0, 5, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_HN_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 3, 0, 5, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_HN_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 3, 0, 5, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SERIAL_NUM_READ_G(r, g, idx)              GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 4, 6, 10, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SERIAL_NUM_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 4, 6, 10, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SERIAL_NUM_READ(r, p)                     FIELD_MREAD_16((uint8_t *)p + 4, 6, 10, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SERIAL_NUM_WRITE(v, p)                    FIELD_MWRITE_16((uint8_t *)p + 4, 6, 10, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PRIORITY_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 5, 5, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PRIORITY_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 5, 5, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PRIORITY_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 5, 5, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PRIORITY_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 5, 5, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_INGRESS_CONG_READ_G(r, g, idx)            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 5, 4, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_INGRESS_CONG_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 5, 4, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_INGRESS_CONG_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 5, 4, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_INGRESS_CONG_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 5, 4, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 5, 3, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 5, 3, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 5, 3, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 5, 3, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PACKET_LENGTH_READ_G(r, g, idx)           GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 6, 0, 14, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PACKET_LENGTH_WRITE_G(v, g, idx)          GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 6, 0, 14, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_DROP_READ_G(r, g, idx)                    GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 7, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_DROP_WRITE_G(v, g, idx)                   GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 7, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_DROP_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_DROP_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_CONG_STATE_STREAM_READ_G(r, g, idx)       GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 4, 3, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_CONG_STATE_STREAM_WRITE_G(v, g, idx)      GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 4, 3, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_CONG_STATE_STREAM_READ(r, p)              FIELD_MREAD_8((uint8_t *)p + 8, 4, 3, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_CONG_STATE_STREAM_WRITE(v, p)             FIELD_MWRITE_8((uint8_t *)p + 8, 4, 3, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_TARGET_MEM_1_READ_G(r, g, idx)            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 6, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_TARGET_MEM_1_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 6, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_TARGET_MEM_1_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 8, 6, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_TARGET_MEM_1_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_CONG_STATE_READ_G(r, g, idx)              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 4, 2, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_CONG_STATE_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 4, 2, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_CONG_STATE_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 8, 4, 2, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_CONG_STATE_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 8, 4, 2, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_STREAM_ID_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 4, 3, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_STREAM_ID_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 4, 3, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_STREAM_ID_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 8, 4, 3, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_STREAM_ID_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 8, 4, 3, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAN_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAN_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAN_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 8, 3, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAN_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 8, 3, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_INGRESS_PORT_READ_G(r, g, idx)            GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 8, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_INGRESS_PORT_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 8, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_INGRESS_PORT_READ(r, p)                   FIELD_MREAD_16((uint8_t *)p + 8, 3, 8, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_INGRESS_PORT_WRITE(v, p)                  FIELD_MWRITE_16((uint8_t *)p + 8, 3, 8, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLOW_READ_G(r, g, idx)                    GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 8, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLOW_WRITE_G(v, g, idx)                   GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 8, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLOW_READ(r, p)                           FIELD_MREAD_16((uint8_t *)p + 8, 3, 8, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLOW_WRITE(v, p)                          FIELD_MWRITE_16((uint8_t *)p + 8, 3, 8, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOURCE_PORT_READ_G(r, g, idx)             GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 8, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOURCE_PORT_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 8, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOURCE_PORT_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 8, 3, 8, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOURCE_PORT_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 8, 3, 8, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAG_PORT_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 1, 2, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAG_PORT_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 1, 2, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAG_PORT_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 8, 1, 2, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAG_PORT_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 8, 1, 2, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAN_VPORT_READ_G(r, g, idx)               GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 6, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAN_VPORT_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 6, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAN_VPORT_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 8, 3, 6, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_LAN_VPORT_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 8, 3, 6, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_IS_VPORT_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 2, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_IS_VPORT_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 2, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_IS_VPORT_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 8, 2, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_IS_VPORT_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 8, 2, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLOW_ID_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 7, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLOW_ID_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 3, 7, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLOW_ID_READ(r, p)                        FIELD_MREAD_16((uint8_t *)p + 8, 3, 7, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_FLOW_ID_WRITE(v, p)                       FIELD_MWRITE_16((uint8_t *)p + 8, 3, 7, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_UNION3_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 0, 19, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_UNION3_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 0, 19, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_UNION3_READ(r, p)                         FIELD_MREAD_32((uint8_t *)p + 8, 0, 19, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_UNION3_WRITE(v, p)                        FIELD_MWRITE_32((uint8_t *)p + 8, 0, 19, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN1_FIRST_READ_G(r, g, idx)               GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 0, 19, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN1_FIRST_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 8, 0, 19, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN1_FIRST_READ(r, p)                      FIELD_MREAD_32((uint8_t *)p + 8, 0, 19, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN1_FIRST_WRITE(v, p)                     FIELD_MWRITE_32((uint8_t *)p + 8, 0, 19, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_1_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 10, 0, 11, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_1_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 10, 0, 11, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_1_READ(r, p)                          FIELD_MREAD_16((uint8_t *)p + 10, 0, 11, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_1_WRITE(v, p)                         FIELD_MWRITE_16((uint8_t *)p + 10, 0, 11, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_AGG_PD_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 7, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_AGG_PD_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 7, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_AGG_PD_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 12, 7, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_AGG_PD_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_TARGET_MEM_0_READ_G(r, g, idx)            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 6, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_TARGET_MEM_0_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 6, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_TARGET_MEM_0_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 12, 6, 1, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_TARGET_MEM_0_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 12, 6, 1, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_READ_G(r, g, idx)      GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 0, 30, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_WRITE_G(v, g, idx)     GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 0, 30, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_READ(r, p)             FIELD_MREAD_32((uint8_t *)p + 12, 0, 30, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_WRITE(v, p)            FIELD_MWRITE_32((uint8_t *)p + 12, 0, 30, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOP_FPM_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 3, 11, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOP_FPM_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 3, 11, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOP_FPM_READ(r, p)                        FIELD_MREAD_16((uint8_t *)p + 12, 3, 11, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOP_FPM_WRITE(v, p)                       FIELD_MWRITE_16((uint8_t *)p + 12, 3, 11, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN_FPM_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 0, 19, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN_FPM_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 0, 19, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN_FPM_READ(r, p)                         FIELD_MREAD_32((uint8_t *)p + 12, 0, 19, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN_FPM_WRITE(v, p)                        FIELD_MWRITE_32((uint8_t *)p + 12, 0, 19, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN_NUM_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 7, 7, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN_NUM_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 7, 7, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN_NUM_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p + 12, 7, 7, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN_NUM_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p + 12, 7, 7, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOP_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 13, 0, 7, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOP_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 13, 0, 7, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOP_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 13, 0, 7, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_SOP_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 13, 0, 7, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN0_FIRST_READ_G(r, g, idx)               GROUP_MREAD_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 14, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN0_FIRST_WRITE_G(v, g, idx)              GROUP_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 14, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN0_FIRST_READ(r, p)                      MREAD_16((uint8_t *)p + 14, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_BN0_FIRST_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_0_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 0, 29, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_0_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_TX_DESCRIPTOR_DTS) + 12, 0, 29, v)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_0_READ(r, p)                          FIELD_MREAD_32((uint8_t *)p + 12, 0, 29, r)
+#define RDD_PROCESSING_TX_DESCRIPTOR_ABS_0_WRITE(v, p)                         FIELD_MWRITE_32((uint8_t *)p + 12, 0, 29, v)
+/* <<<RDD_PROCESSING_TX_DESCRIPTOR_DTS */
+
+
+#define RDD_SRAM_PD_FIFO_SIZE     16
+typedef struct
+{
+	RDD_PROCESSING_TX_DESCRIPTOR_DTS	entry[ RDD_SRAM_PD_FIFO_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SRAM_PD_FIFO_DTS;
+
+extern uint32_t RDD_SRAM_PD_FIFO_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_SRAM_PD_FIFO_PTR(core_id)	( RDD_SRAM_PD_FIFO_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_SRAM_PD_FIFO_ADDRESS_ARR[core_id] ))
+
+/* <<<SRAM_PD_FIFO */
+
+
+/* >>>US_TM_BBH_TX_EGRESS_COUNTER_TABLE */
+
+/* >>>RDD_BBH_TX_EGRESS_COUNTER_ENTRY_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint8_t	counter   	;
+	uint32_t	reserved0 	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1 	;
+#else
+	uint32_t	reserved0 	:24	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	counter   	;
+	uint32_t	reserved1 	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_TX_EGRESS_COUNTER_ENTRY_DTS;
+
+typedef union
+{
+    uint32_t word_val[2];
+    uint64_t dword_val64[1];
+    RDD_BBH_TX_EGRESS_COUNTER_ENTRY_DTS fields;
+} BBH_TX_EGRESS_COUNTER_ENTRY_STRUCT;
+#define RDD_BBH_TX_EGRESS_COUNTER_ENTRY_COUNTER_READ_G(r, g, idx)            GROUP_MREAD_8(g, idx*sizeof(RDD_BBH_TX_EGRESS_COUNTER_ENTRY_DTS), r)
+#define RDD_BBH_TX_EGRESS_COUNTER_ENTRY_COUNTER_WRITE_G(v, g, idx)           GROUP_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_EGRESS_COUNTER_ENTRY_DTS), v)
+#define RDD_BBH_TX_EGRESS_COUNTER_ENTRY_COUNTER_READ(r, p)                   MREAD_8((uint8_t *)p, r)
+#define RDD_BBH_TX_EGRESS_COUNTER_ENTRY_COUNTER_WRITE(v, p)                  MWRITE_8((uint8_t *)p, v)
+/* <<<RDD_BBH_TX_EGRESS_COUNTER_ENTRY_DTS */
+
+
+#define RDD_US_TM_BBH_TX_EGRESS_COUNTER_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BBH_TX_EGRESS_COUNTER_ENTRY_DTS	entry[ RDD_US_TM_BBH_TX_EGRESS_COUNTER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_US_TM_BBH_TX_EGRESS_COUNTER_TABLE_DTS;
+
+extern uint32_t RDD_US_TM_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_US_TM_BBH_TX_EGRESS_COUNTER_TABLE_PTR(core_id)	( RDD_US_TM_BBH_TX_EGRESS_COUNTER_TABLE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_US_TM_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS_ARR[core_id] ))
+
+/* <<<US_TM_BBH_TX_EGRESS_COUNTER_TABLE */
+
+
+/* >>>DIRECT_PROCESSING_PD_TABLE */
+
+/* >>>RDD_PROCESSING_RX_DESCRIPTOR_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	pd_info           	; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	key_index                   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	fragment_type               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	options                     	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	reserved0                   	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	ctrl_key_index              	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	ctrl_fragment_type          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	sfc                         	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	reserved1                   	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	g9991_tci_sof               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	g9991_tci_eof               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	g9991_tci_const             	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	g9991_tci_sid_1_0           	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint8_t	g9991_tci_sid_9_2           	; /* Member of pd_info union */
+			uint16_t	g9991_length_time           	; /* Member of pd_info union */
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	timestamp                   	; /* Member of pd_info union */
+		};
+	};
+	/* Union WORD 1 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	serial_num        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ploam             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ingress_cong      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs_or_dsl        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	reserved          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	error_type_or_cpu_tx	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_serial_num        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_ploam             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_ingress_cong      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of abs_or_dsl union */
+			uint32_t	reserved1_reserved          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	error_type                  	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of error_type_or_cpu_tx union */
+			uint32_t	reserved1_packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_serial_num        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_ploam             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_ingress_cong      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	xdsl                        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of abs_or_dsl union */
+			uint32_t	reserved2_reserved          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	cpu_tx                      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of error_type_or_cpu_tx union */
+			uint32_t	reserved2                   	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of error_type_or_cpu_tx union */
+			uint32_t	reserved2_packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_serial_num        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ploam             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ingress_cong      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs_or_dsl        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reserved          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs_25_28                   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of error_type_or_cpu_tx union */
+			uint32_t	reserved3_packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_serial_num        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_ploam             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_ingress_cong      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_abs_or_dsl        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_reserved          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_error_type_or_cpu_tx	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 2 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	target_mem_1      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	cong_state        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	lan               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ingress_port      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	bn1_last_or_abs1  	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_target_mem_1      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_cong_state        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_lan               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	flow                        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	bn1_last                    	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_last_or_abs1 union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_target_mem_1      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_cong_state        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_lan               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	source_port                 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	abs1                        	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_last_or_abs1 union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_target_mem_1      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_cong_state        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_lan               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ingress_port      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_bn1_last_or_abs1  	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_target_mem_1      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_cong_state        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_lan               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_ingress_port      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_bn1_last_or_abs1  	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 3 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	agg_pd            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	target_mem_0      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_agg_pd            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_target_mem_0      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	sop_fpm                     	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	bn_fpm                      	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_agg_pd            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_target_mem_0      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	bn_num                      	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	sop                         	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint16_t	bn0_first                   	; /* Member of payload_offset_sop union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_agg_pd            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_target_mem_0      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_agg_pd            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_target_mem_0      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+#else
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	pd_info           	; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	key_index                   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	fragment_type               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	options                     	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	reserved0                   	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	ctrl_key_index              	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	ctrl_fragment_type          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	sfc                         	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	reserved1                   	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	g9991_tci_sof               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	g9991_tci_eof               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	g9991_tci_const             	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint32_t	g9991_tci_sid_1_0           	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of pd_info union */
+			uint8_t	g9991_tci_sid_9_2           	; /* Member of pd_info union */
+			uint16_t	g9991_length_time           	; /* Member of pd_info union */
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	timestamp                   	; /* Member of pd_info union */
+		};
+	};
+	/* Union WORD 1 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	error_type_or_cpu_tx	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	reserved          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs_or_dsl        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	ingress_cong      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ploam             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	serial_num        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	error_type                  	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of error_type_or_cpu_tx union */
+			uint32_t	reserved1_reserved          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of abs_or_dsl union */
+			uint32_t	reserved1_ingress_cong      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_ploam             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_serial_num        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	cpu_tx                      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of error_type_or_cpu_tx union */
+			uint32_t	reserved2                   	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of error_type_or_cpu_tx union */
+			uint32_t	reserved2_reserved          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	xdsl                        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of abs_or_dsl union */
+			uint32_t	reserved2_ingress_cong      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_ploam             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_serial_num        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs_25_28                   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of error_type_or_cpu_tx union */
+			uint32_t	reserved3_reserved          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs_or_dsl        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ingress_cong      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ploam             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_serial_num        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_packet_length     	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_error_type_or_cpu_tx	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_reserved          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_abs_or_dsl        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_ingress_cong      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_ploam             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_serial_num        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 2 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	bn1_last_or_abs1  	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	ingress_port      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	lan               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	cong_state        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	target_mem_1      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	bn1_last                    	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_last_or_abs1 union */
+			uint32_t	flow                        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved1_lan               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_cong_state        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_target_mem_1      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	abs1                        	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_last_or_abs1 union */
+			uint32_t	source_port                 	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved2_lan               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_cong_state        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_target_mem_1      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_bn1_last_or_abs1  	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ingress_port      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_lan               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_cong_state        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_target_mem_1      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_bn1_last_or_abs1  	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_ingress_port      	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_lan               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_cong_state        	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_target_mem_1      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_error             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 3 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	target_mem_0      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	agg_pd            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	sop_fpm                     	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	bn_fpm                      	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	reserved1_target_mem_0      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_agg_pd            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	bn_num                      	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	sop                         	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint16_t	bn0_first                   	; /* Member of payload_offset_sop union */
+			uint32_t	reserved2_target_mem_0      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_agg_pd            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_target_mem_0      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_agg_pd            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 4 */
+		struct{
+			uint32_t	reserved4_payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_target_mem_0      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved4_agg_pd            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PROCESSING_RX_DESCRIPTOR_DTS;
+
+typedef union
+{
+    uint32_t word_val[4];
+    uint64_t dword_val64[2];
+    RDD_PROCESSING_RX_DESCRIPTOR_DTS fields;
+} PROCESSING_RX_DESCRIPTOR_STRUCT;
+#define RDD_PROCESSING_RX_DESCRIPTOR_PD_INFO_READ_G(r, g, idx)                     GROUP_MREAD_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PD_INFO_WRITE_G(v, g, idx)                    GROUP_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PD_INFO_READ(r, p)                            MREAD_32((uint8_t *)p, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PD_INFO_WRITE(v, p)                           MWRITE_32((uint8_t *)p, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_KEY_INDEX_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 6, 2, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_KEY_INDEX_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 6, 2, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_KEY_INDEX_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p, 6, 2, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_KEY_INDEX_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p, 6, 2, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_FRAGMENT_TYPE_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 5, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_FRAGMENT_TYPE_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 5, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_FRAGMENT_TYPE_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p, 5, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_FRAGMENT_TYPE_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p, 5, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_OPTIONS_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 11, 18, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_OPTIONS_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 11, 18, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_OPTIONS_READ(r, p)                            FIELD_MREAD_32((uint8_t *)p, 11, 18, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_OPTIONS_WRITE(v, p)                           FIELD_MWRITE_32((uint8_t *)p, 11, 18, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CTRL_KEY_INDEX_READ_G(r, g, idx)              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 6, 2, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CTRL_KEY_INDEX_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 6, 2, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CTRL_KEY_INDEX_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p, 6, 2, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CTRL_KEY_INDEX_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p, 6, 2, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CTRL_FRAGMENT_TYPE_READ_G(r, g, idx)          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 5, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CTRL_FRAGMENT_TYPE_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 5, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CTRL_FRAGMENT_TYPE_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 5, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CTRL_FRAGMENT_TYPE_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 5, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SFC_READ_G(r, g, idx)                         GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 3, 10, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SFC_WRITE_G(v, g, idx)                        GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 3, 10, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SFC_READ(r, p)                                FIELD_MREAD_16((uint8_t *)p, 3, 10, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SFC_WRITE(v, p)                               FIELD_MWRITE_16((uint8_t *)p, 3, 10, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SOF_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 7, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SOF_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 7, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SOF_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SOF_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_EOF_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 6, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_EOF_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 6, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_EOF_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p, 6, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_EOF_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p, 6, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_CONST_READ_G(r, g, idx)             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 2, 4, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_CONST_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 2, 4, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_CONST_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p, 2, 4, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_CONST_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p, 2, 4, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SID_1_0_READ_G(r, g, idx)           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 0, 2, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SID_1_0_WRITE_G(v, g, idx)          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), 0, 2, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SID_1_0_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p, 0, 2, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SID_1_0_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p, 0, 2, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SID_9_2_READ_G(r, g, idx)           GROUP_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SID_9_2_WRITE_G(v, g, idx)          GROUP_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SID_9_2_READ(r, p)                  MREAD_8((uint8_t *)p + 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_TCI_SID_9_2_WRITE(v, p)                 MWRITE_8((uint8_t *)p + 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_LENGTH_TIME_READ_G(r, g, idx)           GROUP_MREAD_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 2, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_LENGTH_TIME_WRITE_G(v, g, idx)          GROUP_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 2, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_LENGTH_TIME_READ(r, p)                  MREAD_16((uint8_t *)p + 2, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_G9991_LENGTH_TIME_WRITE(v, p)                 MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TIMESTAMP_READ_G(r, g, idx)                   GROUP_MREAD_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TIMESTAMP_WRITE_G(v, g, idx)                  GROUP_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS), v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TIMESTAMP_READ(r, p)                          MREAD_32((uint8_t *)p, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TIMESTAMP_WRITE(v, p)                         MWRITE_32((uint8_t *)p, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SERIAL_NUM_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 4, 6, 10, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SERIAL_NUM_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 4, 6, 10, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SERIAL_NUM_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p + 4, 6, 10, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SERIAL_NUM_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p + 4, 6, 10, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PLOAM_READ_G(r, g, idx)                       GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 5, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PLOAM_WRITE_G(v, g, idx)                      GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 5, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PLOAM_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 5, 5, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PLOAM_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 5, 5, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_INGRESS_CONG_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 4, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_INGRESS_CONG_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 4, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_INGRESS_CONG_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 5, 4, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_INGRESS_CONG_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 5, 4, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_OR_DSL_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 3, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_OR_DSL_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 3, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_OR_DSL_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 5, 3, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_OR_DSL_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 5, 3, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_READ_G(r, g, idx)                         GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 3, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_WRITE_G(v, g, idx)                        GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 3, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 5, 3, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 5, 3, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_XDSL_READ_G(r, g, idx)                        GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 3, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_XDSL_WRITE_G(v, g, idx)                       GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 3, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_XDSL_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 5, 3, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_XDSL_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 5, 3, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_TYPE_OR_CPU_TX_READ_G(r, g, idx)        GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 4, 14, 4, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_TYPE_OR_CPU_TX_WRITE_G(v, g, idx)       GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 4, 14, 4, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_TYPE_OR_CPU_TX_READ(r, p)               FIELD_MREAD_32((uint8_t *)p + 4, 14, 4, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_TYPE_OR_CPU_TX_WRITE(v, p)              FIELD_MWRITE_32((uint8_t *)p + 4, 14, 4, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_TYPE_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 4, 14, 4, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_TYPE_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 4, 14, 4, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_TYPE_READ(r, p)                         FIELD_MREAD_32((uint8_t *)p + 4, 14, 4, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_TYPE_WRITE(v, p)                        FIELD_MWRITE_32((uint8_t *)p + 4, 14, 4, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CPU_TX_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 1, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CPU_TX_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 5, 1, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CPU_TX_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 5, 1, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CPU_TX_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 5, 1, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_25_28_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 4, 14, 4, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_25_28_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 4, 14, 4, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_25_28_READ(r, p)                          FIELD_MREAD_32((uint8_t *)p + 4, 14, 4, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS_25_28_WRITE(v, p)                         FIELD_MWRITE_32((uint8_t *)p + 4, 14, 4, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PACKET_LENGTH_READ_G(r, g, idx)               GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 6, 0, 14, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PACKET_LENGTH_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 6, 0, 14, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_READ_G(r, g, idx)                       GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 7, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_WRITE_G(v, g, idx)                      GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 7, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ERROR_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TARGET_MEM_1_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 6, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TARGET_MEM_1_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 6, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TARGET_MEM_1_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 8, 6, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TARGET_MEM_1_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CONG_STATE_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 4, 2, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CONG_STATE_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 4, 2, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CONG_STATE_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 8, 4, 2, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_CONG_STATE_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 8, 4, 2, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_LAN_READ_G(r, g, idx)                         GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 3, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_LAN_WRITE_G(v, g, idx)                        GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 3, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_LAN_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 8, 3, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_LAN_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 8, 3, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_INGRESS_PORT_READ_G(r, g, idx)                GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 3, 8, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_INGRESS_PORT_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 3, 8, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_INGRESS_PORT_READ(r, p)                       FIELD_MREAD_16((uint8_t *)p + 8, 3, 8, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_INGRESS_PORT_WRITE(v, p)                      FIELD_MWRITE_16((uint8_t *)p + 8, 3, 8, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_FLOW_READ_G(r, g, idx)                        GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 3, 8, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_FLOW_WRITE_G(v, g, idx)                       GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 3, 8, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_FLOW_READ(r, p)                               FIELD_MREAD_16((uint8_t *)p + 8, 3, 8, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_FLOW_WRITE(v, p)                              FIELD_MWRITE_16((uint8_t *)p + 8, 3, 8, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOURCE_PORT_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 3, 8, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOURCE_PORT_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 3, 8, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOURCE_PORT_READ(r, p)                        FIELD_MREAD_16((uint8_t *)p + 8, 3, 8, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOURCE_PORT_WRITE(v, p)                       FIELD_MWRITE_16((uint8_t *)p + 8, 3, 8, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN1_LAST_OR_ABS1_READ_G(r, g, idx)            GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 0, 19, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN1_LAST_OR_ABS1_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 0, 19, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN1_LAST_OR_ABS1_READ(r, p)                   FIELD_MREAD_32((uint8_t *)p + 8, 0, 19, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN1_LAST_OR_ABS1_WRITE(v, p)                  FIELD_MWRITE_32((uint8_t *)p + 8, 0, 19, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN1_LAST_READ_G(r, g, idx)                    GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 0, 19, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN1_LAST_WRITE_G(v, g, idx)                   GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 0, 19, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN1_LAST_READ(r, p)                           FIELD_MREAD_32((uint8_t *)p + 8, 0, 19, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN1_LAST_WRITE(v, p)                          FIELD_MWRITE_32((uint8_t *)p + 8, 0, 19, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS1_READ_G(r, g, idx)                        GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 0, 19, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS1_WRITE_G(v, g, idx)                       GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 8, 0, 19, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS1_READ(r, p)                               FIELD_MREAD_32((uint8_t *)p + 8, 0, 19, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_ABS1_WRITE(v, p)                              FIELD_MWRITE_32((uint8_t *)p + 8, 0, 19, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_AGG_PD_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 7, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_AGG_PD_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 7, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_AGG_PD_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 12, 7, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_AGG_PD_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TARGET_MEM_0_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 6, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TARGET_MEM_0_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 6, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TARGET_MEM_0_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 12, 6, 1, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_TARGET_MEM_0_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 12, 6, 1, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_READ_G(r, g, idx)          GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 0, 30, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 0, 30, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_READ(r, p)                 FIELD_MREAD_32((uint8_t *)p + 12, 0, 30, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_WRITE(v, p)                FIELD_MWRITE_32((uint8_t *)p + 12, 0, 30, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOP_FPM_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 3, 11, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOP_FPM_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 3, 11, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOP_FPM_READ(r, p)                            FIELD_MREAD_16((uint8_t *)p + 12, 3, 11, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOP_FPM_WRITE(v, p)                           FIELD_MWRITE_16((uint8_t *)p + 12, 3, 11, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN_FPM_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 0, 19, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN_FPM_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 0, 19, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN_FPM_READ(r, p)                             FIELD_MREAD_32((uint8_t *)p + 12, 0, 19, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN_FPM_WRITE(v, p)                            FIELD_MWRITE_32((uint8_t *)p + 12, 0, 19, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN_NUM_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 7, 7, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN_NUM_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 12, 7, 7, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN_NUM_READ(r, p)                             FIELD_MREAD_16((uint8_t *)p + 12, 7, 7, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN_NUM_WRITE(v, p)                            FIELD_MWRITE_16((uint8_t *)p + 12, 7, 7, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOP_READ_G(r, g, idx)                         GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 13, 0, 7, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOP_WRITE_G(v, g, idx)                        GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 13, 0, 7, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOP_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 13, 0, 7, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_SOP_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 13, 0, 7, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN0_FIRST_READ_G(r, g, idx)                   GROUP_MREAD_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 14, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN0_FIRST_WRITE_G(v, g, idx)                  GROUP_MWRITE_16(g, idx*sizeof(RDD_PROCESSING_RX_DESCRIPTOR_DTS) + 14, v)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN0_FIRST_READ(r, p)                          MREAD_16((uint8_t *)p + 14, r)
+#define RDD_PROCESSING_RX_DESCRIPTOR_BN0_FIRST_WRITE(v, p)                         MWRITE_16((uint8_t *)p + 14, v)
+/* <<<RDD_PROCESSING_RX_DESCRIPTOR_DTS */
+
+
+#define RDD_DIRECT_PROCESSING_PD_TABLE_SIZE     2
+typedef struct
+{
+	RDD_PROCESSING_RX_DESCRIPTOR_DTS	entry[ RDD_DIRECT_PROCESSING_PD_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DIRECT_PROCESSING_PD_TABLE_DTS;
+
+extern uint32_t RDD_DIRECT_PROCESSING_PD_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_DIRECT_PROCESSING_PD_TABLE_PTR(core_id)	( RDD_DIRECT_PROCESSING_PD_TABLE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_DIRECT_PROCESSING_PD_TABLE_ADDRESS_ARR[core_id] ))
+
+/* <<<DIRECT_PROCESSING_PD_TABLE */
+
+
+/* >>>CPU_RX_SCRATCHPAD */
+
+/* >>>RDD_BYTES_4_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	bits      	;
+#else
+	uint32_t	bits      	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BYTES_4_DTS;
+
+typedef union
+{
+    uint32_t word_val[1];
+    RDD_BYTES_4_DTS fields;
+} BYTES_4_STRUCT;
+#define RDD_BYTES_4_BITS_READ_G(r, g, idx)          GROUP_MREAD_32(g, idx*sizeof(RDD_BYTES_4_DTS), r)
+#define RDD_BYTES_4_BITS_WRITE_G(v, g, idx)         GROUP_MWRITE_32(g, idx*sizeof(RDD_BYTES_4_DTS), v)
+#define RDD_BYTES_4_BITS_READ(r, p)                 MREAD_32((uint8_t *)p, r)
+#define RDD_BYTES_4_BITS_WRITE(v, p)                MWRITE_32((uint8_t *)p, v)
+/* <<<RDD_BYTES_4_DTS */
+
+
+#define RDD_CPU_RX_SCRATCHPAD_SIZE     384
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_CPU_RX_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_SCRATCHPAD_DTS;
+
+extern uint32_t RDD_CPU_RX_SCRATCHPAD_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_CPU_RX_SCRATCHPAD_PTR(core_id)	( RDD_CPU_RX_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_CPU_RX_SCRATCHPAD_ADDRESS_ARR[core_id] ))
+
+/* <<<CPU_RX_SCRATCHPAD */
+
+
+/* >>>CPU_TX_SCRATCHPAD */
+
+#define RDD_CPU_TX_SCRATCHPAD_SIZE     384
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_CPU_TX_SCRATCHPAD_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_SCRATCHPAD_DTS;
+
+extern uint32_t RDD_CPU_TX_SCRATCHPAD_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_CPU_TX_SCRATCHPAD_PTR(core_id)	( RDD_CPU_TX_SCRATCHPAD_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_CPU_TX_SCRATCHPAD_ADDRESS_ARR[core_id] ))
+
+/* <<<CPU_TX_SCRATCHPAD */
+
+
+/* >>>BBH_TX_RING_TABLE */
+
+/* >>>RDD_BBH_TX_DESCRIPTOR_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	sof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	eof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	g9991_const   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	sid_1_0       	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint8_t	sid_9_2       	;
+			uint16_t	frag_length   	;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_sof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_eof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_g9991_const   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_sid_1_0       	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint8_t	reserved1_sid_9_2       	;
+			uint16_t	reserved1_frag_length   	;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_sof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_eof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_g9991_const   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_sid_1_0       	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint8_t	reserved2_sid_9_2       	;
+			uint16_t	reserved2_frag_length   	;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_sof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_eof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_g9991_const   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_sid_1_0       	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint8_t	reserved3_sid_9_2       	;
+			uint16_t	reserved3_frag_length   	;
+		};
+	};
+	/* Union WORD 1 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	last          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	mc_header_size	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	fpm_free_dis  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	g9991_frag    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_last          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_mc_header_size	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_fpm_free_dis  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_g9991_frag    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_last          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_mc_header_size	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_fpm_free_dis  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_g9991_frag    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_last          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_mc_header_size	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_fpm_free_dis  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_g9991_frag    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 2 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	error         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	target_mem_1  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	cong_state    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ingress_port  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	buffer_number_1_or_abs_2	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_error         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_target_mem_1  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_cong_state    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	flow                    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	bn1_first               	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of buffer_number_1_or_abs_2 union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_error         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_target_mem_1  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_cong_state    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	source_port             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved1               	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of buffer_number_1_or_abs_2 union */
+			uint32_t	abs_1                   	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of buffer_number_1_or_abs_2 union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_error         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_target_mem_1  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_cong_state    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ingress_port  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_buffer_number_1_or_abs_2	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 3 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	sop_fpm                 	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	bn_fpm                  	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	bn_num                  	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	sop                     	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint16_t	bn0_first               	; /* Member of payload_offset_sop union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	abs_0                   	:29	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+		};
+	};
+#else
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint16_t	frag_length   	;
+			uint8_t	sid_9_2       	;
+			uint32_t	sid_1_0       	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	g9991_const   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	eof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	sof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint16_t	reserved1_frag_length   	;
+			uint8_t	reserved1_sid_9_2       	;
+			uint32_t	reserved1_sid_1_0       	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_g9991_const   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_eof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_sof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint16_t	reserved2_frag_length   	;
+			uint8_t	reserved2_sid_9_2       	;
+			uint32_t	reserved2_sid_1_0       	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_g9991_const   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_eof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_sof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint16_t	reserved3_frag_length   	;
+			uint8_t	reserved3_sid_9_2       	;
+			uint32_t	reserved3_sid_1_0       	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_g9991_const   	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_eof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_sof           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 1 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	g9991_frag    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	fpm_free_dis  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	mc_header_size	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	last          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_g9991_frag    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_fpm_free_dis  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_mc_header_size	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_last          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_g9991_frag    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_fpm_free_dis  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_mc_header_size	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_last          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_packet_length 	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reserved0     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ingress_cong  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_hn            	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_coherent      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_flag_1588     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_g9991_frag    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_fpm_free_dis  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_mc_header_size	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_last          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 2 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	buffer_number_1_or_abs_2	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	ingress_port  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	cong_state    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	target_mem_1  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	error         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	bn1_first               	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of buffer_number_1_or_abs_2 union */
+			uint32_t	flow                    	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved1_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_cong_state    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_target_mem_1  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_error         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved1               	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of buffer_number_1_or_abs_2 union */
+			uint32_t	abs_1                   	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of buffer_number_1_or_abs_2 union */
+			uint32_t	source_port             	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of ingress_port union */
+			uint32_t	reserved2_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_cong_state    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_target_mem_1  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_error         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_buffer_number_1_or_abs_2	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_ingress_port  	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_lan           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_cong_state    	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_target_mem_1  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_error         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 3 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	payload_offset_sop	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	sop_fpm                 	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	bn_fpm                  	:19	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	reserved1_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	bn_num                  	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	sop                     	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint16_t	bn0_first               	; /* Member of payload_offset_sop union */
+			uint32_t	reserved2_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	abs_0                   	:29	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_sop union */
+			uint32_t	reserved3_target_mem_0  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_agg_pd        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_TX_DESCRIPTOR_DTS;
+
+typedef union
+{
+    uint32_t word_val[4];
+    uint64_t dword_val64[2];
+    RDD_BBH_TX_DESCRIPTOR_DTS fields;
+} BBH_TX_DESCRIPTOR_STRUCT;
+#define RDD_BBH_TX_DESCRIPTOR_SOF_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS), 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOF_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS), 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOF_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOF_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_EOF_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS), 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_EOF_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS), 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_EOF_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p, 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_EOF_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_G9991_CONST_READ_G(r, g, idx)             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS), 2, 4, r)
+#define RDD_BBH_TX_DESCRIPTOR_G9991_CONST_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS), 2, 4, v)
+#define RDD_BBH_TX_DESCRIPTOR_G9991_CONST_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p, 2, 4, r)
+#define RDD_BBH_TX_DESCRIPTOR_G9991_CONST_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p, 2, 4, v)
+#define RDD_BBH_TX_DESCRIPTOR_SID_1_0_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS), 0, 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_SID_1_0_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS), 0, 2, v)
+#define RDD_BBH_TX_DESCRIPTOR_SID_1_0_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p, 0, 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_SID_1_0_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p, 0, 2, v)
+#define RDD_BBH_TX_DESCRIPTOR_SID_9_2_READ_G(r, g, idx)                 GROUP_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_SID_9_2_WRITE_G(v, g, idx)                GROUP_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_SID_9_2_READ(r, p)                        MREAD_8((uint8_t *)p + 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_SID_9_2_WRITE(v, p)                       MWRITE_8((uint8_t *)p + 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_FRAG_LENGTH_READ_G(r, g, idx)             GROUP_MREAD_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_FRAG_LENGTH_WRITE_G(v, g, idx)            GROUP_MWRITE_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 2, v)
+#define RDD_BBH_TX_DESCRIPTOR_FRAG_LENGTH_READ(r, p)                    MREAD_16((uint8_t *)p + 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_FRAG_LENGTH_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_READ_G(r, g, idx)                    GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_WRITE_G(v, g, idx)                   GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 4, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_MC_HEADER_SIZE_READ_G(r, g, idx)          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_MC_HEADER_SIZE_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_MC_HEADER_SIZE_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 4, 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_MC_HEADER_SIZE_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 4, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_FPM_FREE_DIS_READ_G(r, g, idx)            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 5, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_FPM_FREE_DIS_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 5, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_FPM_FREE_DIS_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 4, 5, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_FPM_FREE_DIS_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 4, 5, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_G9991_FRAG_READ_G(r, g, idx)              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 4, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_G9991_FRAG_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 4, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_G9991_FRAG_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 4, 4, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_G9991_FRAG_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 4, 4, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_FLAG_1588_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 3, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_FLAG_1588_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 3, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_FLAG_1588_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 4, 3, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_FLAG_1588_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 4, 3, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_COHERENT_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 2, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_COHERENT_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 2, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_COHERENT_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 4, 2, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_COHERENT_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 4, 2, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_HN_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 5, 5, r)
+#define RDD_BBH_TX_DESCRIPTOR_HN_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 4, 5, 5, v)
+#define RDD_BBH_TX_DESCRIPTOR_HN_READ(r, p)                             FIELD_MREAD_16((uint8_t *)p + 4, 5, 5, r)
+#define RDD_BBH_TX_DESCRIPTOR_HN_WRITE(v, p)                            FIELD_MWRITE_16((uint8_t *)p + 4, 5, 5, v)
+#define RDD_BBH_TX_DESCRIPTOR_INGRESS_CONG_READ_G(r, g, idx)            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 5, 4, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_INGRESS_CONG_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 5, 4, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_INGRESS_CONG_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 5, 4, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_INGRESS_CONG_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 5, 4, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 5, 3, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 5, 3, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 5, 3, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 5, 3, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ_G(r, g, idx)           GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 6, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE_G(v, g, idx)          GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 6, 0, 14, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_BBH_TX_DESCRIPTOR_ERROR_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_ERROR_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_ERROR_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_ERROR_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_1_READ_G(r, g, idx)            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_1_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_1_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 8, 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_1_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_CONG_STATE_READ_G(r, g, idx)              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 4, 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_CONG_STATE_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 4, 2, v)
+#define RDD_BBH_TX_DESCRIPTOR_CONG_STATE_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 8, 4, 2, r)
+#define RDD_BBH_TX_DESCRIPTOR_CONG_STATE_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 8, 4, 2, v)
+#define RDD_BBH_TX_DESCRIPTOR_LAN_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 3, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_LAN_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 3, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_LAN_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 8, 3, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_LAN_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 8, 3, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_INGRESS_PORT_READ_G(r, g, idx)            GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 3, 8, r)
+#define RDD_BBH_TX_DESCRIPTOR_INGRESS_PORT_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 3, 8, v)
+#define RDD_BBH_TX_DESCRIPTOR_INGRESS_PORT_READ(r, p)                   FIELD_MREAD_16((uint8_t *)p + 8, 3, 8, r)
+#define RDD_BBH_TX_DESCRIPTOR_INGRESS_PORT_WRITE(v, p)                  FIELD_MWRITE_16((uint8_t *)p + 8, 3, 8, v)
+#define RDD_BBH_TX_DESCRIPTOR_FLOW_READ_G(r, g, idx)                    GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 3, 8, r)
+#define RDD_BBH_TX_DESCRIPTOR_FLOW_WRITE_G(v, g, idx)                   GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 3, 8, v)
+#define RDD_BBH_TX_DESCRIPTOR_FLOW_READ(r, p)                           FIELD_MREAD_16((uint8_t *)p + 8, 3, 8, r)
+#define RDD_BBH_TX_DESCRIPTOR_FLOW_WRITE(v, p)                          FIELD_MWRITE_16((uint8_t *)p + 8, 3, 8, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_PORT_READ_G(r, g, idx)             GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 3, 8, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_PORT_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 3, 8, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_PORT_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p + 8, 3, 8, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOURCE_PORT_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p + 8, 3, 8, v)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_1_OR_ABS_2_READ_G(r, g, idx)GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 0, 19, r)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_1_OR_ABS_2_WRITE_G(v, g, idx)GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 0, 19, v)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_1_OR_ABS_2_READ(r, p)       FIELD_MREAD_32((uint8_t *)p + 8, 0, 19, r)
+#define RDD_BBH_TX_DESCRIPTOR_BUFFER_NUMBER_1_OR_ABS_2_WRITE(v, p)      FIELD_MWRITE_32((uint8_t *)p + 8, 0, 19, v)
+#define RDD_BBH_TX_DESCRIPTOR_BN1_FIRST_READ_G(r, g, idx)               GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 0, 19, r)
+#define RDD_BBH_TX_DESCRIPTOR_BN1_FIRST_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 8, 0, 19, v)
+#define RDD_BBH_TX_DESCRIPTOR_BN1_FIRST_READ(r, p)                      FIELD_MREAD_32((uint8_t *)p + 8, 0, 19, r)
+#define RDD_BBH_TX_DESCRIPTOR_BN1_FIRST_WRITE(v, p)                     FIELD_MWRITE_32((uint8_t *)p + 8, 0, 19, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_1_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 10, 0, 11, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_1_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 10, 0, 11, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_1_READ(r, p)                          FIELD_MREAD_16((uint8_t *)p + 10, 0, 11, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_1_WRITE(v, p)                         FIELD_MWRITE_16((uint8_t *)p + 10, 0, 11, v)
+#define RDD_BBH_TX_DESCRIPTOR_AGG_PD_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_AGG_PD_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_AGG_PD_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 12, 7, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_AGG_PD_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_0_READ_G(r, g, idx)            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_0_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_0_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 12, 6, 1, r)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_0_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 12, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_READ_G(r, g, idx)      GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 0, 30, r)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_WRITE_G(v, g, idx)     GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 0, 30, v)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_READ(r, p)             FIELD_MREAD_32((uint8_t *)p + 12, 0, 30, r)
+#define RDD_BBH_TX_DESCRIPTOR_PAYLOAD_OFFSET_SOP_WRITE(v, p)            FIELD_MWRITE_32((uint8_t *)p + 12, 0, 30, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOP_FPM_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 3, 11, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOP_FPM_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 3, 11, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOP_FPM_READ(r, p)                        FIELD_MREAD_16((uint8_t *)p + 12, 3, 11, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOP_FPM_WRITE(v, p)                       FIELD_MWRITE_16((uint8_t *)p + 12, 3, 11, v)
+#define RDD_BBH_TX_DESCRIPTOR_BN_FPM_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 0, 19, r)
+#define RDD_BBH_TX_DESCRIPTOR_BN_FPM_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 0, 19, v)
+#define RDD_BBH_TX_DESCRIPTOR_BN_FPM_READ(r, p)                         FIELD_MREAD_32((uint8_t *)p + 12, 0, 19, r)
+#define RDD_BBH_TX_DESCRIPTOR_BN_FPM_WRITE(v, p)                        FIELD_MWRITE_32((uint8_t *)p + 12, 0, 19, v)
+#define RDD_BBH_TX_DESCRIPTOR_BN_NUM_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 7, 7, r)
+#define RDD_BBH_TX_DESCRIPTOR_BN_NUM_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 7, 7, v)
+#define RDD_BBH_TX_DESCRIPTOR_BN_NUM_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p + 12, 7, 7, r)
+#define RDD_BBH_TX_DESCRIPTOR_BN_NUM_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p + 12, 7, 7, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOP_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 13, 0, 7, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOP_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 13, 0, 7, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOP_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 13, 0, 7, r)
+#define RDD_BBH_TX_DESCRIPTOR_SOP_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 13, 0, 7, v)
+#define RDD_BBH_TX_DESCRIPTOR_BN0_FIRST_READ_G(r, g, idx)               GROUP_MREAD_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_BN0_FIRST_WRITE_G(v, g, idx)              GROUP_MWRITE_16(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 14, v)
+#define RDD_BBH_TX_DESCRIPTOR_BN0_FIRST_READ(r, p)                      MREAD_16((uint8_t *)p + 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_BN0_FIRST_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_0_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 0, 29, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_0_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_BBH_TX_DESCRIPTOR_DTS) + 12, 0, 29, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_0_READ(r, p)                          FIELD_MREAD_32((uint8_t *)p + 12, 0, 29, r)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_0_WRITE(v, p)                         FIELD_MWRITE_32((uint8_t *)p + 12, 0, 29, v)
+/* <<<RDD_BBH_TX_DESCRIPTOR_DTS */
+
+typedef struct
+{
+	RDD_BBH_TX_DESCRIPTOR_DTS	entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_TX_RING_TABLE_DTS;
+
+extern uint32_t RDD_BBH_TX_RING_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_BBH_TX_RING_TABLE_PTR(core_id)	( RDD_BBH_TX_RING_TABLE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_BBH_TX_RING_TABLE_ADDRESS_ARR[core_id] ))
+
+/* <<<BBH_TX_RING_TABLE */
+
+
+/* >>>CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE */
+
+#define RDD_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_SIZE     3
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_DTS;
+
+extern uint32_t RDD_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_PTR(core_id)	( RDD_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS_ARR[core_id] ))
+
+/* <<<CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE */
+
+
+/* >>>BBH_TX_BB_DESTINATION_TABLE */
+
+/* >>>RDD_BB_DESTINATION_ENTRY_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	bb_destination	;
+#else
+	uint32_t	bb_destination	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BB_DESTINATION_ENTRY_DTS;
+
+typedef union
+{
+    uint32_t word_val[1];
+    RDD_BB_DESTINATION_ENTRY_DTS fields;
+} BB_DESTINATION_ENTRY_STRUCT;
+#define RDD_BB_DESTINATION_ENTRY_BB_DESTINATION_READ_G(r, g, idx)          GROUP_MREAD_32(g, idx*sizeof(RDD_BB_DESTINATION_ENTRY_DTS), r)
+#define RDD_BB_DESTINATION_ENTRY_BB_DESTINATION_WRITE_G(v, g, idx)         GROUP_MWRITE_32(g, idx*sizeof(RDD_BB_DESTINATION_ENTRY_DTS), v)
+#define RDD_BB_DESTINATION_ENTRY_BB_DESTINATION_READ(r, p)                 MREAD_32((uint8_t *)p, r)
+#define RDD_BB_DESTINATION_ENTRY_BB_DESTINATION_WRITE(v, p)                MWRITE_32((uint8_t *)p, v)
+/* <<<RDD_BB_DESTINATION_ENTRY_DTS */
+
+typedef struct
+{
+	RDD_BB_DESTINATION_ENTRY_DTS	entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBH_TX_BB_DESTINATION_TABLE_DTS;
+
+extern uint32_t RDD_BBH_TX_BB_DESTINATION_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_BBH_TX_BB_DESTINATION_TABLE_PTR(core_id)	( RDD_BBH_TX_BB_DESTINATION_TABLE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_BBH_TX_BB_DESTINATION_TABLE_ADDRESS_ARR[core_id] ))
+
+/* <<<BBH_TX_BB_DESTINATION_TABLE */
+
+
+/* >>>CPU_RX_CFE_SRAM_COUNTERS */
+
+/* >>>RDD_PACKETS_AND_BYTES_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	packets   	;
+	uint32_t	bytes     	;
+#else
+	uint32_t	packets   	;
+	uint32_t	bytes     	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PACKETS_AND_BYTES_DTS;
+
+typedef union
+{
+    uint32_t word_val[2];
+    uint64_t dword_val64[1];
+    RDD_PACKETS_AND_BYTES_DTS fields;
+} PACKETS_AND_BYTES_STRUCT;
+#define RDD_PACKETS_AND_BYTES_PACKETS_READ_G(r, g, idx)          GROUP_MREAD_32(g, idx*sizeof(RDD_PACKETS_AND_BYTES_DTS), r)
+#define RDD_PACKETS_AND_BYTES_PACKETS_WRITE_G(v, g, idx)         GROUP_MWRITE_32(g, idx*sizeof(RDD_PACKETS_AND_BYTES_DTS), v)
+#define RDD_PACKETS_AND_BYTES_PACKETS_READ(r, p)                 MREAD_32((uint8_t *)p, r)
+#define RDD_PACKETS_AND_BYTES_PACKETS_WRITE(v, p)                MWRITE_32((uint8_t *)p, v)
+#define RDD_PACKETS_AND_BYTES_BYTES_READ_G(r, g, idx)            GROUP_MREAD_32(g, idx*sizeof(RDD_PACKETS_AND_BYTES_DTS) + 4, r)
+#define RDD_PACKETS_AND_BYTES_BYTES_WRITE_G(v, g, idx)           GROUP_MWRITE_32(g, idx*sizeof(RDD_PACKETS_AND_BYTES_DTS) + 4, v)
+#define RDD_PACKETS_AND_BYTES_BYTES_READ(r, p)                   MREAD_32((uint8_t *)p + 4, r)
+#define RDD_PACKETS_AND_BYTES_BYTES_WRITE(v, p)                  MWRITE_32((uint8_t *)p + 4, v)
+/* <<<RDD_PACKETS_AND_BYTES_DTS */
+
+
+#define RDD_CPU_RX_CFE_SRAM_COUNTERS_SIZE     10
+typedef struct
+{
+	RDD_PACKETS_AND_BYTES_DTS	entry[ RDD_CPU_RX_CFE_SRAM_COUNTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_CFE_SRAM_COUNTERS_DTS;
+
+extern uint32_t RDD_CPU_RX_CFE_SRAM_COUNTERS_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_CPU_RX_CFE_SRAM_COUNTERS_PTR(core_id)	( RDD_CPU_RX_CFE_SRAM_COUNTERS_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_CPU_RX_CFE_SRAM_COUNTERS_ADDRESS_ARR[core_id] ))
+
+/* <<<CPU_RX_CFE_SRAM_COUNTERS */
+
+
+/* >>>CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE */
+
+#define RDD_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_SIZE     3
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_DTS;
+
+extern uint32_t RDD_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_PTR(core_id)	( RDD_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS_ARR[core_id] ))
+
+/* <<<CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE */
+
+
+/* >>>TASK_IDX */
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TASK_IDX_DTS;
+
+extern uint32_t RDD_TASK_IDX_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_TASK_IDX_PTR(core_id)	( RDD_TASK_IDX_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_TASK_IDX_ADDRESS_ARR[core_id] ))
+
+/* <<<TASK_IDX */
+
+
+/* >>>CPU_RX_INTERRUPT_SCRATCH */
+
+/* >>>RDD_BYTE_1_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint8_t	bits      	;
+#else
+	uint8_t	bits      	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BYTE_1_DTS;
+
+#define RDD_BYTE_1_BITS_READ_G(r, g, idx)          GROUP_MREAD_8(g, idx*sizeof(RDD_BYTE_1_DTS), r)
+#define RDD_BYTE_1_BITS_WRITE_G(v, g, idx)         GROUP_MWRITE_8(g, idx*sizeof(RDD_BYTE_1_DTS), v)
+#define RDD_BYTE_1_BITS_READ(r, p)                 MREAD_8((uint8_t *)p, r)
+#define RDD_BYTE_1_BITS_WRITE(v, p)                MWRITE_8((uint8_t *)p, v)
+/* <<<RDD_BYTE_1_DTS */
+
+
+#define RDD_CPU_RX_INTERRUPT_SCRATCH_SIZE     8
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry[ RDD_CPU_RX_INTERRUPT_SCRATCH_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_INTERRUPT_SCRATCH_DTS;
+
+extern uint32_t RDD_CPU_RX_INTERRUPT_SCRATCH_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_CPU_RX_INTERRUPT_SCRATCH_PTR(core_id)	( RDD_CPU_RX_INTERRUPT_SCRATCH_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_CPU_RX_INTERRUPT_SCRATCH_ADDRESS_ARR[core_id] ))
+
+/* <<<CPU_RX_INTERRUPT_SCRATCH */
+
+
+/* >>>CPU_RX_INTERRUPT_ID_DDR_ADDR */
+
+#define RDD_CPU_RX_INTERRUPT_ID_DDR_ADDR_SIZE     8
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry[ RDD_CPU_RX_INTERRUPT_ID_DDR_ADDR_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_INTERRUPT_ID_DDR_ADDR_DTS;
+
+extern uint32_t RDD_CPU_RX_INTERRUPT_ID_DDR_ADDR_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_CPU_RX_INTERRUPT_ID_DDR_ADDR_PTR(core_id)	( RDD_CPU_RX_INTERRUPT_ID_DDR_ADDR_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_CPU_RX_INTERRUPT_ID_DDR_ADDR_ADDRESS_ARR[core_id] ))
+
+/* <<<CPU_RX_INTERRUPT_ID_DDR_ADDR */
+
+
+/* >>>PKT_BUFFER_ALLOC_MAP_TABLE */
+
+#define RDD_PKT_BUFFER_ALLOC_MAP_TABLE_SIZE     3
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_PKT_BUFFER_ALLOC_MAP_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PKT_BUFFER_ALLOC_MAP_TABLE_DTS;
+
+extern uint32_t RDD_PKT_BUFFER_ALLOC_MAP_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_PKT_BUFFER_ALLOC_MAP_TABLE_PTR(core_id)	( RDD_PKT_BUFFER_ALLOC_MAP_TABLE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_PKT_BUFFER_ALLOC_MAP_TABLE_ADDRESS_ARR[core_id] ))
+
+/* <<<PKT_BUFFER_ALLOC_MAP_TABLE */
+
+
+/* >>>CPU_RX_LAST_READ_INDEX */
+
+/* >>>RDD_BYTES_2_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint16_t	bits      	;
+#else
+	uint16_t	bits      	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BYTES_2_DTS;
+
+#define RDD_BYTES_2_BITS_READ_G(r, g, idx)          GROUP_MREAD_16(g, idx*sizeof(RDD_BYTES_2_DTS), r)
+#define RDD_BYTES_2_BITS_WRITE_G(v, g, idx)         GROUP_MWRITE_16(g, idx*sizeof(RDD_BYTES_2_DTS), v)
+#define RDD_BYTES_2_BITS_READ(r, p)                 MREAD_16((uint8_t *)p, r)
+#define RDD_BYTES_2_BITS_WRITE(v, p)                MWRITE_16((uint8_t *)p, v)
+/* <<<RDD_BYTES_2_DTS */
+
+typedef struct
+{
+	RDD_BYTES_2_DTS	entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_LAST_READ_INDEX_DTS;
+
+extern uint32_t RDD_CPU_RX_LAST_READ_INDEX_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_CPU_RX_LAST_READ_INDEX_PTR(core_id)	( RDD_CPU_RX_LAST_READ_INDEX_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_CPU_RX_LAST_READ_INDEX_ADDRESS_ARR[core_id] ))
+
+/* <<<CPU_RX_LAST_READ_INDEX */
+
+
+/* >>>SRAM_DUMMY_STORE */
+typedef struct
+{
+	RDD_BYTE_1_DTS	entry;
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_SRAM_DUMMY_STORE_DTS;
+
+extern uint32_t RDD_SRAM_DUMMY_STORE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_SRAM_DUMMY_STORE_PTR(core_id)	( RDD_SRAM_DUMMY_STORE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_SRAM_DUMMY_STORE_ADDRESS_ARR[core_id] ))
+
+/* <<<SRAM_DUMMY_STORE */
+
+
+/* >>>CPU_TX_CFE_SRAM_COUNTERS */
+
+#define RDD_CPU_TX_CFE_SRAM_COUNTERS_SIZE     10
+typedef struct
+{
+	RDD_PACKETS_AND_BYTES_DTS	entry[ RDD_CPU_TX_CFE_SRAM_COUNTERS_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_CFE_SRAM_COUNTERS_DTS;
+
+extern uint32_t RDD_CPU_TX_CFE_SRAM_COUNTERS_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_CPU_TX_CFE_SRAM_COUNTERS_PTR(core_id)	( RDD_CPU_TX_CFE_SRAM_COUNTERS_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_CPU_TX_CFE_SRAM_COUNTERS_ADDRESS_ARR[core_id] ))
+
+/* <<<CPU_TX_CFE_SRAM_COUNTERS */
+
+
+/* >>>CPU_RX_BB_REPLY_ADDR_TABLE */
+
+#define RDD_CPU_RX_BB_REPLY_ADDR_TABLE_SIZE     2
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_CPU_RX_BB_REPLY_ADDR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_BB_REPLY_ADDR_TABLE_DTS;
+
+extern uint32_t RDD_CPU_RX_BB_REPLY_ADDR_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_CPU_RX_BB_REPLY_ADDR_TABLE_PTR(core_id)	( RDD_CPU_RX_BB_REPLY_ADDR_TABLE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_CPU_RX_BB_REPLY_ADDR_TABLE_ADDRESS_ARR[core_id] ))
+
+/* <<<CPU_RX_BB_REPLY_ADDR_TABLE */
+
+
+/* >>>CPU_TX_BB_REPLY_ADDR_TABLE */
+
+#define RDD_CPU_TX_BB_REPLY_ADDR_TABLE_SIZE     2
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_CPU_TX_BB_REPLY_ADDR_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_BB_REPLY_ADDR_TABLE_DTS;
+
+extern uint32_t RDD_CPU_TX_BB_REPLY_ADDR_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_CPU_TX_BB_REPLY_ADDR_TABLE_PTR(core_id)	( RDD_CPU_TX_BB_REPLY_ADDR_TABLE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_CPU_TX_BB_REPLY_ADDR_TABLE_ADDRESS_ARR[core_id] ))
+
+/* <<<CPU_TX_BB_REPLY_ADDR_TABLE */
+
+
+/* >>>DS_TM_BBH_TX_EGRESS_COUNTER_TABLE */
+
+#define RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_SIZE     8
+typedef struct
+{
+	RDD_BBH_TX_EGRESS_COUNTER_ENTRY_DTS	entry[ RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_DTS;
+
+extern uint32_t RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_PTR(core_id)	( RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS_ARR[core_id] ))
+
+/* <<<DS_TM_BBH_TX_EGRESS_COUNTER_TABLE */
+
+
+/* >>>REGISTERS_BUFFER */
+
+#define RDD_REGISTERS_BUFFER_SIZE     32
+typedef struct
+{
+	RDD_BYTES_4_DTS	entry[ RDD_REGISTERS_BUFFER_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_REGISTERS_BUFFER_DTS;
+
+extern uint32_t RDD_REGISTERS_BUFFER_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_REGISTERS_BUFFER_PTR(core_id)	( RDD_REGISTERS_BUFFER_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_REGISTERS_BUFFER_ADDRESS_ARR[core_id] ))
+
+/* <<<REGISTERS_BUFFER */
+
+
+/* >>>RX_FLOW_TABLE */
+
+/* >>>RDD_RX_FLOW_ENTRY_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint16_t	virtual_port	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	flow_dest   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	exception   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	reserved    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	cntr_id     	;
+#else
+	uint8_t	cntr_id     	;
+	uint16_t	reserved    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	exception   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	flow_dest   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	virtual_port	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RX_FLOW_ENTRY_DTS;
+
+#define RDD_RX_FLOW_ENTRY_VIRTUAL_PORT_READ_G(r, g, idx)          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_RX_FLOW_ENTRY_DTS), 3, 5, r)
+#define RDD_RX_FLOW_ENTRY_VIRTUAL_PORT_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_RX_FLOW_ENTRY_DTS), 3, 5, v)
+#define RDD_RX_FLOW_ENTRY_VIRTUAL_PORT_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 3, 5, r)
+#define RDD_RX_FLOW_ENTRY_VIRTUAL_PORT_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 3, 5, v)
+#define RDD_RX_FLOW_ENTRY_FLOW_DEST_READ_G(r, g, idx)             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_RX_FLOW_ENTRY_DTS), 2, 1, r)
+#define RDD_RX_FLOW_ENTRY_FLOW_DEST_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_RX_FLOW_ENTRY_DTS), 2, 1, v)
+#define RDD_RX_FLOW_ENTRY_FLOW_DEST_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p, 2, 1, r)
+#define RDD_RX_FLOW_ENTRY_FLOW_DEST_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p, 2, 1, v)
+#define RDD_RX_FLOW_ENTRY_EXCEPTION_READ_G(r, g, idx)             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_RX_FLOW_ENTRY_DTS), 1, 1, r)
+#define RDD_RX_FLOW_ENTRY_EXCEPTION_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_RX_FLOW_ENTRY_DTS), 1, 1, v)
+#define RDD_RX_FLOW_ENTRY_EXCEPTION_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p, 1, 1, r)
+#define RDD_RX_FLOW_ENTRY_EXCEPTION_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p, 1, 1, v)
+#define RDD_RX_FLOW_ENTRY_CNTR_ID_READ_G(r, g, idx)               GROUP_MREAD_8(g, idx*sizeof(RDD_RX_FLOW_ENTRY_DTS) + 1, r)
+#define RDD_RX_FLOW_ENTRY_CNTR_ID_WRITE_G(v, g, idx)              GROUP_MWRITE_8(g, idx*sizeof(RDD_RX_FLOW_ENTRY_DTS) + 1, v)
+#define RDD_RX_FLOW_ENTRY_CNTR_ID_READ(r, p)                      MREAD_8((uint8_t *)p + 1, r)
+#define RDD_RX_FLOW_ENTRY_CNTR_ID_WRITE(v, p)                     MWRITE_8((uint8_t *)p + 1, v)
+/* <<<RDD_RX_FLOW_ENTRY_DTS */
+
+
+#define RDD_RX_FLOW_TABLE_SIZE     320
+typedef struct
+{
+	RDD_RX_FLOW_ENTRY_DTS	entry[ RDD_RX_FLOW_TABLE_SIZE ];
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_RX_FLOW_TABLE_DTS;
+
+extern uint32_t RDD_RX_FLOW_TABLE_ADDRESS_ARR[GROUPED_EN_SEGMENTS_NUM];
+
+#define RDD_RX_FLOW_TABLE_PTR(core_id)	( RDD_RX_FLOW_TABLE_DTS * )(DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + RDD_RX_FLOW_TABLE_ADDRESS_ARR[core_id] ))
+
+/* <<<RX_FLOW_TABLE */
+
+
+/* >>>RDD_DISP_REOR_VIQ */
+typedef enum
+{
+	DISP_REOR_VIQ_FIRST             = 0,
+	DISP_REOR_VIQ_BBH_RX0_NORMAL    = 0,
+	DISP_REOR_VIQ_BBH_RX1_NORMAL    = 1,
+	DISP_REOR_VIQ_BBH_RX2_NORMAL    = 2,
+	DISP_REOR_VIQ_BBH_RX3_NORMAL    = 3,
+	DISP_REOR_VIQ_BBH_RX4_NORMAL    = 4,
+	DISP_REOR_VIQ_BBH_RX5_NORMAL    = 5,
+	DISP_REOR_VIQ_BBH_RX0_EXCL      = 6,
+	DISP_REOR_VIQ_BBH_RX1_EXCL      = 7,
+	DISP_REOR_VIQ_BBH_RX2_EXCL      = 8,
+	DISP_REOR_VIQ_BBH_RX3_EXCL      = 9,
+	DISP_REOR_VIQ_BBH_RX4_EXCL      = 10,
+	DISP_REOR_VIQ_BBH_RX5_EXCL      = 11,
+	DISP_REOR_VIQ_CPU_TX_EGRESS     = 12,
+	DISP_REOR_VIQ_CPU_RX_COPY       = 13,
+	DISP_REOR_VIQ_LAST              = 13
+} rdd_disp_reor_viq;
+/* <<<RDD_DISP_REOR_VIQ */
+
+
+/* >>>RDD_IMAGE_0_CFE_CORE */
+typedef enum
+{
+	IMAGE_0_CFE_CORE_FIRST           = 0,
+	IMAGE_0_CFE_CORE_CPU_RX_THREAD_NUMBER = 0,
+	IMAGE_0_CFE_CORE_CPU_TX_THREAD_NUMBER = 1,
+	IMAGE_0_CFE_CORE_LAST            = 1
+} rdd_cfe_core;
+/* <<<RDD_IMAGE_0_CFE_CORE */
+
+
+/* >>>RDD_CPU_IF_RDD */
+typedef enum
+{
+	CPU_IF_RDD_FIRST      = 0,
+	CPU_IF_RDD_DATA       = 0,
+	CPU_IF_RDD_RECYCLE    = 1,
+	CPU_IF_RDD_FEED       = 2,
+	CPU_IF_RDD_LAST       = 2
+} rdd_cpu_if_rdd;
+/* <<<RDD_CPU_IF_RDD */
+
+
+/* >>>RDD_FLOW_DEST */
+typedef enum
+{
+	FLOW_DEST_FIRST      = 0,
+	FLOW_DEST_ETH_ID     = 0,
+	FLOW_DEST_IPTV_ID    = 1,
+	FLOW_DEST_LAST       = 1
+} rdd_flow_dest;
+/* <<<RDD_FLOW_DEST */
+
+
+/* >>>RDD_PACKET_BUFFER_POOL_TABLE_ADDR */
+typedef enum
+{
+	PACKET_BUFFER_POOL_TABLE_ADDR_FIRST = 2181087232,
+	PACKET_BUFFER_POOL_TABLE_ADDR_RX    = 2181087232,
+	PACKET_BUFFER_POOL_TABLE_ADDR_TX    = 2181099520,
+	PACKET_BUFFER_POOL_TABLE_ADDR_LAST  = 2181099520
+} rdd_packet_buffer_pool_table_addr;
+/* <<<RDD_PACKET_BUFFER_POOL_TABLE_ADDR */
+
+
+/* >>>RDD_PACKET_BUFFER_START_TOKEN */
+typedef enum
+{
+	PACKET_BUFFER_START_TOKEN_FIRST = 384,
+	PACKET_BUFFER_START_TOKEN_RX    = 384,
+	PACKET_BUFFER_START_TOKEN_TX    = 480,
+	PACKET_BUFFER_START_TOKEN_LAST  = 480
+} rdd_packet_buffer_start_token;
+/* <<<RDD_PACKET_BUFFER_START_TOKEN */
+
+
+/* >>>RDD_ACTION */
+typedef enum
+{
+	ACTION_FIRST        = 0,
+	ACTION_FORWARD      = 0,
+	ACTION_TRAP         = 1,
+	ACTION_DROP         = 2,
+	ACTION_MULTICAST    = 3,
+	ACTION_LAST         = 3
+} rdd_action;
+/* <<<RDD_ACTION */
+
+
+/* >>>RDD_LAYER3_IPV6_HEADER */
+typedef enum
+{
+	LAYER3_IPV6_HEADER_FIRST            = 8,
+	LAYER3_IPV6_HEADER_SRC_IP_OFFSET    = 8,
+	LAYER3_IPV6_HEADER_DST_IP_OFFSET    = 24,
+	LAYER3_IPV6_HEADER_LAST             = 24
+} rdd_layer3_ipv6_header;
+/* <<<RDD_LAYER3_IPV6_HEADER */
+
+
+/* >>>RDD_LAYER3_HEADER */
+typedef enum
+{
+	LAYER3_HEADER_FIRST                  = 0,
+	LAYER3_HEADER_TRAFIC_CLASS_OFFSET    = 0,
+	LAYER3_HEADER_TOS_OFFSET             = 1,
+	LAYER3_HEADER_FLAGS_OFFSET           = 6,
+	LAYER3_HEADER_HOP_LIMIT_OFFSET       = 7,
+	LAYER3_HEADER_TTL_OFFSET             = 8,
+	LAYER3_HEADER_PROTOCOL_OFFSET        = 9,
+	LAYER3_HEADER_IP_CHECKSUM_OFFSET     = 10,
+	LAYER3_HEADER_SRC_IP_OFFSET          = 12,
+	LAYER3_HEADER_DST_IP_OFFSET          = 16,
+	LAYER3_HEADER_LAST                   = 16
+} rdd_layer3_header;
+/* <<<RDD_LAYER3_HEADER */
+
+
+/* >>>RDD_LAYER4_HEADER */
+typedef enum
+{
+	LAYER4_HEADER_FIRST                  = 0,
+	LAYER4_HEADER_SRC_PORT_OFFSET        = 0,
+	LAYER4_HEADER_ESP_SPI_OFFSET         = 0,
+	LAYER4_HEADER_DST_PORT_OFFSET        = 2,
+	LAYER4_HEADER_UDP_CHECKSUM_OFFSET    = 6,
+	LAYER4_HEADER_GRE_CALL_ID_OFFSET     = 6,
+	LAYER4_HEADER_TCP_FLAGS_OFFSET       = 13,
+	LAYER4_HEADER_TCP_CHECKSUM_OFFSET    = 16,
+	LAYER4_HEADER_LAST                   = 16
+} rdd_layer4_header;
+/* <<<RDD_LAYER4_HEADER */
+
+
+/* >>>RDD_PARSER_L2_PROTOCOL */
+typedef enum
+{
+	PARSER_L2_PROTOCOL_FIRST             = 1,
+	PARSER_L2_PROTOCOL_PPPOE_D           = 1,
+	PARSER_L2_PROTOCOL_PPPOE_S           = 2,
+	PARSER_L2_PROTOCOL_USER_DEFINED_0    = 8,
+	PARSER_L2_PROTOCOL_USER_DEFINED_1    = 9,
+	PARSER_L2_PROTOCOL_USER_DEFINED_2    = 10,
+	PARSER_L2_PROTOCOL_USER_DEFINED_3    = 11,
+	PARSER_L2_PROTOCOL_ARP               = 12,
+	PARSER_L2_PROTOCOL__1588             = 13,
+	PARSER_L2_PROTOCOL__802_1X           = 14,
+	PARSER_L2_PROTOCOL_MASK              = 15,
+	PARSER_L2_PROTOCOL__802_1AG_CFM      = 15,
+	PARSER_L2_PROTOCOL_LAST              = 15
+} rdd_parser_l2_protocol;
+/* <<<RDD_PARSER_L2_PROTOCOL */
+
+
+/* >>>RDD_PARSER_L3_PROTOCOL */
+typedef enum
+{
+	PARSER_L3_PROTOCOL_FIRST    = 0,
+	PARSER_L3_PROTOCOL_OTHER    = 0,
+	PARSER_L3_PROTOCOL_IPV4     = 1,
+	PARSER_L3_PROTOCOL_IPV6     = 2,
+	PARSER_L3_PROTOCOL_MASK     = 3,
+	PARSER_L3_PROTOCOL_LAST     = 3
+} rdd_parser_l3_protocol;
+/* <<<RDD_PARSER_L3_PROTOCOL */
+
+
+/* >>>RDD_PARSER_L4_PROTOCOL */
+typedef enum
+{
+	PARSER_L4_PROTOCOL_FIRST             = 0,
+	PARSER_L4_PROTOCOL_OTHER             = 0,
+	PARSER_L4_PROTOCOL_TCP               = 1,
+	PARSER_L4_PROTOCOL_UDP               = 2,
+	PARSER_L4_PROTOCOL_IGMP              = 3,
+	PARSER_L4_PROTOCOL_ICMP              = 4,
+	PARSER_L4_PROTOCOL_ICMPV6            = 5,
+	PARSER_L4_PROTOCOL_ESP               = 6,
+	PARSER_L4_PROTOCOL_GRE               = 7,
+	PARSER_L4_PROTOCOL_USER_DEFINED_0    = 8,
+	PARSER_L4_PROTOCOL_USER_DEFINED_1    = 9,
+	PARSER_L4_PROTOCOL_USER_DEFINED_2    = 10,
+	PARSER_L4_PROTOCOL_USER_DEFINED_3    = 11,
+	PARSER_L4_PROTOCOL_RESERVED          = 12,
+	PARSER_L4_PROTOCOL_IPV6              = 13,
+	PARSER_L4_PROTOCOL_AH                = 14,
+	PARSER_L4_PROTOCOL_NOT_PARSED        = 15,
+	PARSER_L4_PROTOCOL_MASK              = 15,
+	PARSER_L4_PROTOCOL_LAST              = 15
+} rdd_parser_l4_protocol;
+/* <<<RDD_PARSER_L4_PROTOCOL */
+
+
+/* >>>RDD_ACTION_ECN */
+typedef enum
+{
+	ACTION_ECN_FIRST               = 0,
+	ACTION_ECN_REMARKING_OFFSET    = 0,
+	ACTION_ECN_REMARKING_WIDTH     = 2,
+	ACTION_ECN_LAST                = 2
+} rdd_action_ecn;
+/* <<<RDD_ACTION_ECN */
+
+
+/* >>>RDD_ACTION_DSCP */
+typedef enum
+{
+	ACTION_DSCP_FIRST                             = 2,
+	ACTION_DSCP_REMARKING_OFFSET                  = 2,
+	ACTION_DSCP_REMARKING_TRAFFIC_CLASS_OFFSET    = 4,
+	ACTION_DSCP_REMARKING_WIDTH                   = 6,
+	ACTION_DSCP_REMARKING_TRAFFIC_CLASS_WIDTH     = 8,
+	ACTION_DSCP_LAST                              = 8
+} rdd_action_dscp;
+/* <<<RDD_ACTION_DSCP */
+
+
+/* >>>RDD_ACTION_OUTER */
+typedef enum
+{
+	ACTION_OUTER_FIRST                         = 14,
+	ACTION_OUTER_PBITS_REMARKING_VID_OFFSET    = 14,
+	ACTION_OUTER_LAST                          = 14
+} rdd_action_outer;
+/* <<<RDD_ACTION_OUTER */
+
+
+/* >>>RDD_ACTION_INNER */
+typedef enum
+{
+	ACTION_INNER_FIRST                         = 18,
+	ACTION_INNER_PBITS_REMARKING_VID_OFFSET    = 18,
+	ACTION_INNER_LAST                          = 18
+} rdd_action_inner;
+/* <<<RDD_ACTION_INNER */
+
+
+/* >>>RDD_ACTION_PBITS */
+typedef enum
+{
+	ACTION_PBITS_FIRST                      = 2,
+	ACTION_PBITS_REMARKING_DSCP_OFFSET      = 2,
+	ACTION_PBITS_REMARKING_PACKET_WIDTH     = 3,
+	ACTION_PBITS_REMARKING_DSCP_WIDTH       = 6,
+	ACTION_PBITS_REMARKING_PACKET_OFFSET    = 13,
+	ACTION_PBITS_LAST                       = 13
+} rdd_action_pbits;
+/* <<<RDD_ACTION_PBITS */
+
+
+/* >>>RDD_ACTION_DS_LITE */
+typedef enum
+{
+	ACTION_DS_LITE_FIRST   = 40,
+	ACTION_DS_LITE_SIZE    = 40,
+	ACTION_DS_LITE_LAST    = 40
+} rdd_action_ds_lite;
+/* <<<RDD_ACTION_DS_LITE */
+
+
+/* >>>RDD_DS_ACTION_ID */
+typedef enum
+{
+	DS_ACTION_ID_FIRST        = 0,
+	DS_ACTION_ID_TRAP         = 0,
+	DS_ACTION_ID_TTL          = 2,
+	DS_ACTION_ID_DSCP         = 4,
+	DS_ACTION_ID_NAT          = 5,
+	DS_ACTION_ID_GRE          = 6,
+	DS_ACTION_ID_OPBITS       = 7,
+	DS_ACTION_ID_IPBITS       = 8,
+	DS_ACTION_ID_DS_LITE      = 9,
+	DS_ACTION_ID_PPPOE        = 10,
+	DS_ACTION_ID_TOTAL_NUM    = 17,
+	DS_ACTION_ID_LAST         = 17
+} rdd_ds_action_id;
+/* <<<RDD_DS_ACTION_ID */
+
+
+/* >>>RDD_US_ACTION_ID */
+typedef enum
+{
+	US_ACTION_ID_FIRST        = 0,
+	US_ACTION_ID_TRAP         = 0,
+	US_ACTION_ID_TTL          = 2,
+	US_ACTION_ID_DSCP         = 4,
+	US_ACTION_ID_NAT          = 5,
+	US_ACTION_ID_GRE          = 6,
+	US_ACTION_ID_OPBITS       = 7,
+	US_ACTION_ID_IPBITS       = 8,
+	US_ACTION_ID_DS_LITE      = 9,
+	US_ACTION_ID_PPPOE        = 10,
+	US_ACTION_ID_TOTAL_NUM    = 17,
+	US_ACTION_ID_LAST         = 17
+} rdd_us_action_id;
+/* <<<RDD_US_ACTION_ID */
+
+
+/* >>>RDD_RDD_VPORT */
+typedef enum
+{
+	RDD_VPORT_FIRST     = 0,
+	RDD_VPORT_ID_0      = 0,
+	RDD_VPORT_ID_1      = 1,
+	RDD_VPORT_ID_2      = 2,
+	RDD_VPORT_ID_3      = 3,
+	RDD_VPORT_ID_4      = 4,
+	RDD_VPORT_ID_5      = 5,
+	RDD_VPORT_ID_6      = 6,
+	RDD_VPORT_ID_7      = 7,
+	RDD_VPORT_ID_8      = 8,
+	RDD_VPORT_ID_9      = 9,
+	RDD_VPORT_ID_10     = 10,
+	RDD_VPORT_ID_11     = 11,
+	RDD_VPORT_ID_12     = 12,
+	RDD_VPORT_ID_13     = 13,
+	RDD_VPORT_ID_14     = 14,
+	RDD_VPORT_ID_15     = 15,
+	RDD_VPORT_ID_16     = 16,
+	RDD_VPORT_ID_17     = 17,
+	RDD_VPORT_ID_18     = 18,
+	RDD_VPORT_ID_19     = 19,
+	RDD_VPORT_ID_20     = 20,
+	RDD_VPORT_ID_21     = 21,
+	RDD_VPORT_ID_22     = 22,
+	RDD_VPORT_ID_23     = 23,
+	RDD_VPORT_ID_24     = 24,
+	RDD_VPORT_ID_25     = 25,
+	RDD_VPORT_ID_26     = 26,
+	RDD_VPORT_ID_27     = 27,
+	RDD_VPORT_ID_28     = 28,
+	RDD_VPORT_ID_29     = 29,
+	RDD_VPORT_ID_30     = 30,
+	RDD_VPORT_ID_31     = 31,
+	RDD_VPORT_ID_32     = 32,
+	RDD_VPORT_ID_33     = 33,
+	RDD_VPORT_ID_34     = 34,
+	RDD_VPORT_ID_35     = 35,
+	RDD_VPORT_ID_36     = 36,
+	RDD_VPORT_ID_37     = 37,
+	RDD_VPORT_ID_38     = 38,
+	RDD_VPORT_ID_39     = 39,
+	RDD_VPORT_ID_ANY    = 40,
+	RDD_VPORT_LAST      = 40
+} rdd_rdd_vport;
+/* <<<RDD_RDD_VPORT */
+
+
+/* >>>RDD_DSCP_TO */
+typedef enum
+{
+	DSCP_TO_FIRST                 = 6,
+	DSCP_TO_PBITS_SHIFT_OFFSET    = 6,
+	DSCP_TO_LAST                  = 6
+} rdd_dscp_to;
+/* <<<RDD_DSCP_TO */
+
+
+/* >>>RDD_RESOLUTION_CONTEXT */
+typedef enum
+{
+	RESOLUTION_CONTEXT_FIRST                          = 0,
+	RESOLUTION_CONTEXT_VIRTUAL_SRC_PORT_OFFSET        = 0,
+	RESOLUTION_CONTEXT_GPE_DMA_OFFSET_WIDTH           = 1,
+	RESOLUTION_CONTEXT_GPE_HEADER_LENGTH_WIDTH        = 1,
+	RESOLUTION_CONTEXT_GPE_HEADER_IH_PTR_WIDTH        = 2,
+	RESOLUTION_CONTEXT_GPE_COMMAND_LIST_PTR_WIDTH     = 2,
+	RESOLUTION_CONTEXT_GPE_PACKET_DRR_PTR_WIDTH       = 4,
+	RESOLUTION_CONTEXT_GPE_HEADER_LENGTH_OFFSET       = 6,
+	RESOLUTION_CONTEXT_GPE_DMA_OFFSET_OFFSET          = 7,
+	RESOLUTION_CONTEXT_GPE_COMMAND_LIST_PTR_OFFSET    = 8,
+	RESOLUTION_CONTEXT_GPE_HEADER_IH_PTR_OFFSET       = 10,
+	RESOLUTION_CONTEXT_GPE_PACKET_DRR_PTR_OFFSET      = 12,
+	RESOLUTION_CONTEXT_LAST                           = 12
+} rdd_resolution_context;
+/* <<<RDD_RESOLUTION_CONTEXT */
+
+
+/* >>>RDD_BBMSG_TYPE */
+typedef enum
+{
+	BBMSG_TYPE_FIRST                                              = 0,
+	BBMSG_TYPE_RUNNER_BBH_RX_FLOW_CONTROL                         = 0,
+	BBMSG_TYPE_QM_PD_FIFO_CREDIT_FREE                             = 0,
+	BBMSG_TYPE_BBH_TX_PACKET_DESCRIPTOR                           = 1,
+	BBMSG_TYPE_RUNNER_SBPM_BUFFER_ALLOC                           = 1,
+	BBMSG_TYPE_QM_UPDATE_FIFO_CREDIT_FREE                         = 1,
+	BBMSG_TYPE_FPM_BUFFER_ALLOC                                   = 1,
+	BBMSG_TYPE_FPM_BUFFER_MCAST_INCREMENT                         = 2,
+	BBMSG_TYPE_RUNNER_SBPM_MCAST_INC_REQUEST                      = 2,
+	BBMSG_TYPE_BBH_TX_NACK                                        = 2,
+	BBMSG_TYPE_BBH_TX_ACK                                         = 3,
+	BBMSG_TYPE_FPM_BUFFER_FREE                                    = 3,
+	BBMSG_TYPE_BBH_SBPM_BUFFER_FREE                               = 3,
+	BBMSG_TYPE_BBH_GHOST_DBR                                      = 4,
+	BBMSG_TYPE_RUNNER_SBPM_CONNECT                                = 4,
+	BBMSG_TYPE_RUNNER_SBPM_GET_NEXT                               = 5,
+	BBMSG_TYPE_BBH_TX_REPORT_ACK                                  = 5,
+	BBMSG_TYPE_BBH_SBPM_BUFFER_FREE_WITHOUT_CONTEXT               = 6,
+	BBMSG_TYPE_RUNNER_SBPM_BUFFER_FREE_WITHOUT_CONTEXT            = 6,
+	BBMSG_TYPE_BBH_TX_REPORT_NACK                                 = 7,
+	BBMSG_TYPE_RUNNER_SBPM_INGRESS_TO_EGRESS                      = 7,
+	BBMSG_TYPE_RUNNER_REORDER_PD_WRITE                            = 8,
+	BBMSG_TYPE_RUNNER_DISPATCHER_PD_ACK                           = 9,
+	BBMSG_TYPE_RUNNER_DISPATCHER_PD_WRITE                         = 10,
+	BBMSG_TYPE_RUNNER_REORDER_TOKEN_REQUEST                       = 11,
+	BBMSG_TYPE_RUNNER_REORDER_BUFFER_CONNECT                      = 12,
+	BBMSG_TYPE_RUNNER_DISPATCHER_WAKEUP_PENDING                   = 13,
+	BBMSG_TYPE_RUNNER_REORDER_CONNECT_REQUEST_BUFFER_CONNECTED    = 14,
+	BBMSG_TYPE_RUNNER_REORDER_BUFFER_MULTICAST_CONNECT_REQUEST    = 15,
+	BBMSG_TYPE_BBH_RX_DISPATCHER_PD_WRITE                         = 24,
+	BBMSG_TYPE_LAST                                               = 24
+} rdd_bbmsg_type;
+/* <<<RDD_BBMSG_TYPE */
+
+
+/* >>>RDD_ERR_RX_PD */
+typedef enum
+{
+	ERR_RX_PD_FIRST                 = 1,
+	ERR_RX_PD_NO_SBPM               = 1,
+	ERR_RX_PD_PACKET_TOO_SHORT      = 2,
+	ERR_RX_PD_PACKET_TOO_LONG       = 3,
+	ERR_RX_PD_CRC                   = 4,
+	ERR_RX_PD_ENCRYPT               = 5,
+	ERR_RX_PD_NO_SDMA_CHUNK         = 6,
+	ERR_RX_PD_SOP_AFTER_SOP         = 7,
+	ERR_RX_PD_THIRD_FLOW_ARRIVAL    = 8,
+	ERR_RX_PD_LAST                  = 8
+} rdd_err_rx_pd;
+/* <<<RDD_ERR_RX_PD */
+
+
+/* >>>RDD_SBPM_OPCODE */
+typedef enum
+{
+	SBPM_OPCODE_FIRST                   = 0,
+	SBPM_OPCODE_MULTI_GET_NEXT          = 0,
+	SBPM_OPCODE_BN_ALLOC                = 1,
+	SBPM_OPCODE_MCST_INC                = 2,
+	SBPM_OPCODE_BN_FREE_WITH_CONTEXT    = 3,
+	SBPM_OPCODE_BN_CONNECT              = 4,
+	SBPM_OPCODE_GET_NEXT                = 5,
+	SBPM_OPCODE_BN_FREE_WO_CONTEXT      = 6,
+	SBPM_OPCODE_INGRESS_TO_EGRESS       = 7,
+	SBPM_OPCODE_LAST                    = 7
+} rdd_sbpm_opcode;
+/* <<<RDD_SBPM_OPCODE */
+
+
+/* >>>RDD_RDD_LAN */
+typedef enum
+{
+	RDD_LAN_FIRST           = 1,
+	RDD_LAN_BRIDGE_PORT0    = 1,
+	RDD_LAN_BRIDGE_PORT1    = 2,
+	RDD_LAN_BRIDGE_PORT2    = 3,
+	RDD_LAN_BRIDGE_PORT3    = 4,
+	RDD_LAN_BRIDGE_PORT4    = 5,
+	RDD_LAN_BRIDGE_PORT5    = 6,
+	RDD_LAN_LAST            = 6
+} rdd_rdd_lan;
+/* <<<RDD_RDD_LAN */
+
+
+/* >>>RDD_MAC_TYPE */
+typedef enum
+{
+	MAC_TYPE_FIRST    = 0,
+	MAC_TYPE_EMAC     = 0,
+	MAC_TYPE_GPON     = 1,
+	MAC_TYPE_XGPON    = 2,
+	MAC_TYPE_EPON     = 3,
+	MAC_TYPE_XEPON    = 4,
+	MAC_TYPE_DSL      = 5,
+	MAC_TYPE_AE10G    = 6,
+	MAC_TYPE_AE2P5    = 7,
+	MAC_TYPE_LAST     = 7
+} rdd_mac_type;
+/* <<<RDD_MAC_TYPE */
+
+
+/* >>>RDD_SBPM */
+typedef enum
+{
+	SBPM_FIRST                    = 16383,
+	SBPM_INVALID_BUFFER_NUMBER    = 16383,
+	SBPM_LAST                     = 16383
+} rdd_sbpm;
+/* <<<RDD_SBPM */
+
+
+/* >>>RDD_FPM_POOL_ID */
+typedef enum
+{
+	FPM_POOL_ID_FIRST            = 0,
+	FPM_POOL_ID_EIGHT_BUFFERS    = 0,
+	FPM_POOL_ID_FOUR_BUFFERS     = 1,
+	FPM_POOL_ID_TWO_BUFFERS      = 2,
+	FPM_POOL_ID_ONE_BUFFER       = 3,
+	FPM_POOL_ID_LAST             = 3
+} rdd_fpm_pool_id;
+/* <<<RDD_FPM_POOL_ID */
+
+
+/* >>>RDD_RNR */
+typedef enum
+{
+	RNR_FIRST       = 0,
+	RNR_CORE0_ID    = 0,
+	RNR_CORE1_ID    = 1,
+	RNR_CORE2_ID    = 2,
+	RNR_CORE3_ID    = 3,
+	RNR_CORE4_ID    = 4,
+	RNR_LAST        = 4
+} rdd_rnr;
+/* <<<RDD_RNR */
+
+
+/* >>>RDD_BB_ID */
+typedef enum
+{
+	BB_ID_FIRST                 = 0,
+	BB_ID_RNR0                  = 0,
+	BB_ID_RNR1                  = 1,
+	BB_ID_RNR2                  = 2,
+	BB_ID_RNR3                  = 3,
+	BB_ID_RNR4                  = 4,
+	BB_ID_BBHLB                 = 16,
+	BB_ID_CNPL_0                = 17,
+	BB_ID_DISPATCHER_REORDER    = 18,
+	BB_ID_SDMA_COPY             = 20,
+	BB_ID_QM_CP_SDMA            = 20,
+	BB_ID_SDMA0                 = 21,
+	BB_ID_SDMA1                 = 22,
+	BB_ID_FPM                   = 23,
+	BB_ID_HASH_0                = 24,
+	BB_ID_NATC_0                = 25,
+	BB_ID_QM_RNR_GRID           = 27,
+	BB_ID_QM_BBHTX              = 28,
+	BB_ID_QM_TOP                = 29,
+	BB_ID_QM_CP_MACHINE         = 30,
+	BB_ID_RX_BBH_0              = 31,
+	BB_ID_TX_LAN                = 32,
+	BB_ID_RX_BBH_1              = 33,
+	BB_ID_RX_BBH_2              = 35,
+	BB_ID_TX_COPY               = 36,
+	BB_ID_RX_BBH_3              = 37,
+	BB_ID_RX_BBH_4              = 39,
+	BB_ID_RX_BBH_5              = 41,
+	BB_ID_RX_BBH_6              = 43,
+	BB_ID_RX_BBH_7              = 45,
+	BB_ID_RX_DSL                = 53,
+	BB_ID_TX_DSL                = 54,
+	BB_ID_TX_DSL_STAT           = 55,
+	BB_ID_SBPM                  = 56,
+	BB_ID_TCAM_0                = 57,
+	BB_ID_TCAM_1                = 58,
+	BB_ID_HASH_1                = 59,
+	BB_ID_NATC_1                = 60,
+	BB_ID_CNPL_1                = 61,
+	BB_ID_LAST                  = 61
+} rdd_bb_id;
+/* <<<RDD_BB_ID */
+
+
+/* Hardware defines */
+
+/* >>>RDD_BB_DESTINATION_ENTRY */
+#define BB_DESTINATION_ENTRY_BB_DESTINATION_F_OFFSET                   0
+#define BB_DESTINATION_ENTRY_BB_DESTINATION_F_WIDTH                    32
+#define BB_DESTINATION_ENTRY_BB_DESTINATION_ENTRY_OFFSET               0
+#define BB_DESTINATION_ENTRY_BB_DESTINATION_OFFSET                     0
+#define BB_DESTINATION_ENTRY_BB_DESTINATION_WORD_OFFSET                0
+/* <<<RDD_BB_DESTINATION_ENTRY */
+
+
+/* >>>RDD_CPU_TX_DESCRIPTOR */
+#define CPU_TX_DESCRIPTOR_VALID_F_OFFSET                            31
+#define CPU_TX_DESCRIPTOR_VALID_F_WIDTH                             1
+#define CPU_TX_DESCRIPTOR_CPU_TX_DESCRIPTOR_OFFSET                  0
+#define CPU_TX_DESCRIPTOR_VALID_OFFSET                              0
+#define CPU_TX_DESCRIPTOR_VALID_WORD_OFFSET                         0
+#define CPU_TX_DESCRIPTOR_VALID_F_OFFSET_MOD8                       7
+#define CPU_TX_DESCRIPTOR_VALID_F_OFFSET_MOD16                      15
+#define CPU_TX_DESCRIPTOR_FIRST_LEVEL_Q_F_OFFSET                    22
+#define CPU_TX_DESCRIPTOR_FIRST_LEVEL_Q_F_WIDTH                     9
+#define CPU_TX_DESCRIPTOR_FIRST_LEVEL_Q_OFFSET                      0
+#define CPU_TX_DESCRIPTOR_FIRST_LEVEL_Q_WORD_OFFSET                 0
+#define CPU_TX_DESCRIPTOR_FIRST_LEVEL_Q_F_OFFSET_MOD16              6
+#define CPU_TX_DESCRIPTOR_ABS_DATA1_F_OFFSET                        0
+#define CPU_TX_DESCRIPTOR_ABS_DATA1_F_WIDTH                         22
+#define CPU_TX_DESCRIPTOR_ABS_DATA1_OFFSET                          0
+#define CPU_TX_DESCRIPTOR_ABS_DATA1_WORD_OFFSET                     0
+#define CPU_TX_DESCRIPTOR_ABS_DATA0_F_OFFSET                        14
+#define CPU_TX_DESCRIPTOR_ABS_DATA0_F_WIDTH                         18
+#define CPU_TX_DESCRIPTOR_ABS_DATA0_OFFSET                          4
+#define CPU_TX_DESCRIPTOR_ABS_DATA0_WORD_OFFSET                     1
+#define CPU_TX_DESCRIPTOR_PACKET_LENGTH_F_OFFSET                    0
+#define CPU_TX_DESCRIPTOR_PACKET_LENGTH_F_WIDTH                     14
+#define CPU_TX_DESCRIPTOR_PACKET_LENGTH_OFFSET                      6
+#define CPU_TX_DESCRIPTOR_PACKET_LENGTH_WORD_OFFSET                 1
+#define CPU_TX_DESCRIPTOR_PACKET_LENGTH_F_OFFSET_MOD16              0
+#define CPU_TX_DESCRIPTOR_DROP_F_OFFSET                             31
+#define CPU_TX_DESCRIPTOR_DROP_F_WIDTH                              1
+#define CPU_TX_DESCRIPTOR_DROP_OFFSET                               8
+#define CPU_TX_DESCRIPTOR_DROP_WORD_OFFSET                          2
+#define CPU_TX_DESCRIPTOR_DROP_F_OFFSET_MOD8                        7
+#define CPU_TX_DESCRIPTOR_DROP_F_OFFSET_MOD16                       15
+#define CPU_TX_DESCRIPTOR_FLAG_1588_F_OFFSET                        30
+#define CPU_TX_DESCRIPTOR_FLAG_1588_F_WIDTH                         1
+#define CPU_TX_DESCRIPTOR_FLAG_1588_OFFSET                          8
+#define CPU_TX_DESCRIPTOR_FLAG_1588_WORD_OFFSET                     2
+#define CPU_TX_DESCRIPTOR_FLAG_1588_F_OFFSET_MOD8                   6
+#define CPU_TX_DESCRIPTOR_FLAG_1588_F_OFFSET_MOD16                  14
+#define CPU_TX_DESCRIPTOR_COLOR_F_OFFSET                            29
+#define CPU_TX_DESCRIPTOR_COLOR_F_WIDTH                             1
+#define CPU_TX_DESCRIPTOR_COLOR_OFFSET                              8
+#define CPU_TX_DESCRIPTOR_COLOR_WORD_OFFSET                         2
+#define CPU_TX_DESCRIPTOR_COLOR_F_OFFSET_MOD8                       5
+#define CPU_TX_DESCRIPTOR_COLOR_F_OFFSET_MOD16                      13
+#define CPU_TX_DESCRIPTOR_DO_NOT_RECYCLE_F_OFFSET                   28
+#define CPU_TX_DESCRIPTOR_DO_NOT_RECYCLE_F_WIDTH                    1
+#define CPU_TX_DESCRIPTOR_DO_NOT_RECYCLE_OFFSET                     8
+#define CPU_TX_DESCRIPTOR_DO_NOT_RECYCLE_WORD_OFFSET                2
+#define CPU_TX_DESCRIPTOR_DO_NOT_RECYCLE_F_OFFSET_MOD8              4
+#define CPU_TX_DESCRIPTOR_DO_NOT_RECYCLE_F_OFFSET_MOD16             12
+#define CPU_TX_DESCRIPTOR_LAN_F_OFFSET                              26
+#define CPU_TX_DESCRIPTOR_LAN_F_WIDTH                               1
+#define CPU_TX_DESCRIPTOR_LAN_OFFSET                                8
+#define CPU_TX_DESCRIPTOR_LAN_WORD_OFFSET                           2
+#define CPU_TX_DESCRIPTOR_LAN_F_OFFSET_MOD8                         2
+#define CPU_TX_DESCRIPTOR_LAN_F_OFFSET_MOD16                        10
+#define CPU_TX_DESCRIPTOR_WAN_FLOW_SOURCE_PORT_F_OFFSET             18
+#define CPU_TX_DESCRIPTOR_WAN_FLOW_SOURCE_PORT_F_WIDTH              8
+#define CPU_TX_DESCRIPTOR_WAN_FLOW_SOURCE_PORT_OFFSET               8
+#define CPU_TX_DESCRIPTOR_WAN_FLOW_SOURCE_PORT_WORD_OFFSET          2
+#define CPU_TX_DESCRIPTOR_WAN_FLOW_SOURCE_PORT_F_OFFSET_MOD16       2
+#define CPU_TX_DESCRIPTOR_BN1_OR_ABS2_OR_1588_F_OFFSET              0
+#define CPU_TX_DESCRIPTOR_BN1_OR_ABS2_OR_1588_F_WIDTH               18
+#define CPU_TX_DESCRIPTOR_BN1_OR_ABS2_OR_1588_OFFSET                8
+#define CPU_TX_DESCRIPTOR_BN1_OR_ABS2_OR_1588_WORD_OFFSET           2
+#define CPU_TX_DESCRIPTOR_AGG_PD_F_OFFSET                           31
+#define CPU_TX_DESCRIPTOR_AGG_PD_F_WIDTH                            1
+#define CPU_TX_DESCRIPTOR_AGG_PD_OFFSET                             12
+#define CPU_TX_DESCRIPTOR_AGG_PD_WORD_OFFSET                        3
+#define CPU_TX_DESCRIPTOR_AGG_PD_F_OFFSET_MOD8                      7
+#define CPU_TX_DESCRIPTOR_AGG_PD_F_OFFSET_MOD16                     15
+#define CPU_TX_DESCRIPTOR_TARGET_MEM_0_F_OFFSET                     30
+#define CPU_TX_DESCRIPTOR_TARGET_MEM_0_F_WIDTH                      1
+#define CPU_TX_DESCRIPTOR_TARGET_MEM_0_OFFSET                       12
+#define CPU_TX_DESCRIPTOR_TARGET_MEM_0_WORD_OFFSET                  3
+#define CPU_TX_DESCRIPTOR_TARGET_MEM_0_F_OFFSET_MOD8                6
+#define CPU_TX_DESCRIPTOR_TARGET_MEM_0_F_OFFSET_MOD16               14
+#define CPU_TX_DESCRIPTOR_ABS_F_OFFSET                              29
+#define CPU_TX_DESCRIPTOR_ABS_F_WIDTH                               1
+#define CPU_TX_DESCRIPTOR_ABS_OFFSET                                12
+#define CPU_TX_DESCRIPTOR_ABS_WORD_OFFSET                           3
+#define CPU_TX_DESCRIPTOR_ABS_F_OFFSET_MOD8                         5
+#define CPU_TX_DESCRIPTOR_ABS_F_OFFSET_MOD16                        13
+#define CPU_TX_DESCRIPTOR_PAYLOAD_OFFSET_OR_ABS_1_F_OFFSET          18
+#define CPU_TX_DESCRIPTOR_PAYLOAD_OFFSET_OR_ABS_1_F_WIDTH           11
+#define CPU_TX_DESCRIPTOR_PAYLOAD_OFFSET_OR_ABS_1_OFFSET            12
+#define CPU_TX_DESCRIPTOR_PAYLOAD_OFFSET_OR_ABS_1_WORD_OFFSET       3
+#define CPU_TX_DESCRIPTOR_PAYLOAD_OFFSET_OR_ABS_1_F_OFFSET_MOD16    2
+#define CPU_TX_DESCRIPTOR_BUFFER_NUMBER_0_OR_ABS_0_F_OFFSET         0
+#define CPU_TX_DESCRIPTOR_BUFFER_NUMBER_0_OR_ABS_0_F_WIDTH          18
+#define CPU_TX_DESCRIPTOR_BUFFER_NUMBER_0_OR_ABS_0_OFFSET           12
+#define CPU_TX_DESCRIPTOR_BUFFER_NUMBER_0_OR_ABS_0_WORD_OFFSET      3
+
+/* >>>RDD_CPU_TX_DESCRIPTOR_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	valid               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	first_level_q       	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs_data1           	:22	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_valid               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_first_level_q       	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_abs_data1           	:22	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_valid               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_first_level_q       	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_abs_data1           	:22	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_valid               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_first_level_q       	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs_data1           	:22	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 1 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	abs_data0           	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	packet_length       	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_abs_data0           	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_packet_length       	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_abs_data0           	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_packet_length       	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_abs_data0           	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_packet_length       	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 2 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	drop                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	flag_1588           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	color               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	do_not_recycle      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	lan                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	wan_flow_source_port	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	bn1_or_abs2_or_1588 	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_drop                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_flag_1588           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_color               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_do_not_recycle      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_reserved1           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_lan                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_wan_flow_source_port	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ssid                          	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	fpm_fallback                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	sbpm_copy                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	bn1_first                     	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_drop                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_flag_1588           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_color               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_do_not_recycle      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_reserved1           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_lan                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_wan_flow_source_port	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	_ssid                         	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	_fpm_fallback                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	_sbpm_copy                    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	abs2                          	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_drop                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_flag_1588           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_color               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_do_not_recycle      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reserved1           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_lan                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_wan_flow_source_port	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	data_1588                     	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+		};
+	};
+	/* Union WORD 3 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	agg_pd              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	target_mem_0        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	payload_offset_or_abs_1	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	buffer_number_0_or_abs_0	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_agg_pd              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_target_mem_0        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_abs                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	sop                           	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_or_abs_1 union */
+			uint32_t	bn0_first                     	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of buffer_number_0_or_abs_0 union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_agg_pd              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_target_mem_0        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_abs                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs1                          	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_or_abs_1 union */
+			uint32_t	abs0                          	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of buffer_number_0_or_abs_0 union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_agg_pd              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_target_mem_0        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_payload_offset_or_abs_1	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_buffer_number_0_or_abs_0	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+#else
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	abs_data1           	:22	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	first_level_q       	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	valid               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_abs_data1           	:22	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_first_level_q       	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_valid               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_abs_data1           	:22	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_first_level_q       	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_valid               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_abs_data1           	:22	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_first_level_q       	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_valid               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 1 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	packet_length       	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs_data0           	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_packet_length       	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_abs_data0           	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_packet_length       	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_abs_data0           	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_packet_length       	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs_data0           	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 2 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	bn1_or_abs2_or_1588 	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	wan_flow_source_port	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	lan                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	do_not_recycle      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	color               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	flag_1588           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	drop                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	ssid                          	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	fpm_fallback                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	sbpm_copy                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	bn1_first                     	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	reserved1_wan_flow_source_port	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_lan                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_reserved1           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_do_not_recycle      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_color               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_flag_1588           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_drop                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	_ssid                         	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	_fpm_fallback                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	_sbpm_copy                    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	abs2                          	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	reserved2_wan_flow_source_port	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_lan                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_reserved1           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_do_not_recycle      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_color               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_flag_1588           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_drop                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	data_1588                     	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of bn1_or_abs2_or_1588 union */
+			uint32_t	reserved3_wan_flow_source_port	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_lan                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reserved1           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_do_not_recycle      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_color               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_flag_1588           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_drop                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 3 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	buffer_number_0_or_abs_0	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	payload_offset_or_abs_1	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	abs                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	target_mem_0        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	agg_pd              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	bn0_first                     	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of buffer_number_0_or_abs_0 union */
+			uint32_t	sop                           	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_or_abs_1 union */
+			uint32_t	reserved1_abs                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_target_mem_0        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_agg_pd              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	abs0                          	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of buffer_number_0_or_abs_0 union */
+			uint32_t	abs1                          	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of payload_offset_or_abs_1 union */
+			uint32_t	reserved2_abs                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_target_mem_0        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_agg_pd              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_buffer_number_0_or_abs_0	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_payload_offset_or_abs_1	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_target_mem_0        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_agg_pd              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_TX_DESCRIPTOR_DTS;
+
+typedef union
+{
+    uint32_t word_val[4];
+    uint64_t dword_val64[2];
+    RDD_CPU_TX_DESCRIPTOR_DTS fields;
+} CPU_TX_DESCRIPTOR_STRUCT;
+#define RDD_CPU_TX_DESCRIPTOR_VALID_READ_G(r, g, idx)                         GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS), 7, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_VALID_WRITE_G(v, g, idx)                        GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS), 7, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_VALID_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_VALID_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_FIRST_LEVEL_Q_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS), 6, 9, r)
+#define RDD_CPU_TX_DESCRIPTOR_FIRST_LEVEL_Q_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS), 6, 9, v)
+#define RDD_CPU_TX_DESCRIPTOR_FIRST_LEVEL_Q_READ(r, p)                        FIELD_MREAD_16((uint8_t *)p, 6, 9, r)
+#define RDD_CPU_TX_DESCRIPTOR_FIRST_LEVEL_Q_WRITE(v, p)                       FIELD_MWRITE_16((uint8_t *)p, 6, 9, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_DATA1_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 0, 0, 22, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_DATA1_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 0, 0, 22, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_DATA1_READ(r, p)                            FIELD_MREAD_32((uint8_t *)p + 0, 0, 22, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_DATA1_WRITE(v, p)                           FIELD_MWRITE_32((uint8_t *)p + 0, 0, 22, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_DATA0_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 4, 14, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_DATA0_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 4, 14, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_DATA0_READ(r, p)                            FIELD_MREAD_32((uint8_t *)p + 4, 14, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_DATA0_WRITE(v, p)                           FIELD_MWRITE_32((uint8_t *)p + 4, 14, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_PACKET_LENGTH_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 6, 0, 14, r)
+#define RDD_CPU_TX_DESCRIPTOR_PACKET_LENGTH_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 6, 0, 14, v)
+#define RDD_CPU_TX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                        FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_CPU_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                       FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_CPU_TX_DESCRIPTOR_DROP_READ_G(r, g, idx)                          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 7, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_DROP_WRITE_G(v, g, idx)                         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 7, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_DROP_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_DROP_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_FLAG_1588_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 6, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_FLAG_1588_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 6, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_FLAG_1588_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 8, 6, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_FLAG_1588_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_COLOR_READ_G(r, g, idx)                         GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 5, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_COLOR_WRITE_G(v, g, idx)                        GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 5, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_COLOR_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 8, 5, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_COLOR_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 8, 5, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_DO_NOT_RECYCLE_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 4, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_DO_NOT_RECYCLE_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 4, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_DO_NOT_RECYCLE_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 8, 4, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_DO_NOT_RECYCLE_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 8, 4, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_LAN_READ_G(r, g, idx)                           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 2, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_LAN_WRITE_G(v, g, idx)                          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 2, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_LAN_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 8, 2, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_LAN_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 8, 2, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_WAN_FLOW_SOURCE_PORT_READ_G(r, g, idx)          GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 2, 8, r)
+#define RDD_CPU_TX_DESCRIPTOR_WAN_FLOW_SOURCE_PORT_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 2, 8, v)
+#define RDD_CPU_TX_DESCRIPTOR_WAN_FLOW_SOURCE_PORT_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 8, 2, 8, r)
+#define RDD_CPU_TX_DESCRIPTOR_WAN_FLOW_SOURCE_PORT_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 8, 2, 8, v)
+#define RDD_CPU_TX_DESCRIPTOR_BN1_OR_ABS2_OR_1588_READ_G(r, g, idx)           GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_BN1_OR_ABS2_OR_1588_WRITE_G(v, g, idx)          GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 0, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_BN1_OR_ABS2_OR_1588_READ(r, p)                  FIELD_MREAD_32((uint8_t *)p + 8, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_BN1_OR_ABS2_OR_1588_WRITE(v, p)                 FIELD_MWRITE_32((uint8_t *)p + 8, 0, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_SSID_READ_G(r, g, idx)                          GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 14, 4, r)
+#define RDD_CPU_TX_DESCRIPTOR_SSID_WRITE_G(v, g, idx)                         GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 14, 4, v)
+#define RDD_CPU_TX_DESCRIPTOR_SSID_READ(r, p)                                 FIELD_MREAD_32((uint8_t *)p + 8, 14, 4, r)
+#define RDD_CPU_TX_DESCRIPTOR_SSID_WRITE(v, p)                                FIELD_MWRITE_32((uint8_t *)p + 8, 14, 4, v)
+#define RDD_CPU_TX_DESCRIPTOR_FPM_FALLBACK_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 5, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_FPM_FALLBACK_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 5, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_FPM_FALLBACK_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 10, 5, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_FPM_FALLBACK_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 10, 5, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_SBPM_COPY_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 4, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_SBPM_COPY_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 4, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_SBPM_COPY_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 10, 4, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_SBPM_COPY_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 10, 4, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_BN1_FIRST_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 0, 12, r)
+#define RDD_CPU_TX_DESCRIPTOR_BN1_FIRST_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 0, 12, v)
+#define RDD_CPU_TX_DESCRIPTOR_BN1_FIRST_READ(r, p)                            FIELD_MREAD_16((uint8_t *)p + 10, 0, 12, r)
+#define RDD_CPU_TX_DESCRIPTOR_BN1_FIRST_WRITE(v, p)                           FIELD_MWRITE_16((uint8_t *)p + 10, 0, 12, v)
+#define RDD_CPU_TX_DESCRIPTOR__SSID_READ_G(r, g, idx)                         GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 14, 4, r)
+#define RDD_CPU_TX_DESCRIPTOR__SSID_WRITE_G(v, g, idx)                        GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 14, 4, v)
+#define RDD_CPU_TX_DESCRIPTOR__SSID_READ(r, p)                                FIELD_MREAD_32((uint8_t *)p + 8, 14, 4, r)
+#define RDD_CPU_TX_DESCRIPTOR__SSID_WRITE(v, p)                               FIELD_MWRITE_32((uint8_t *)p + 8, 14, 4, v)
+#define RDD_CPU_TX_DESCRIPTOR__FPM_FALLBACK_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 5, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR__FPM_FALLBACK_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 5, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR__FPM_FALLBACK_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 10, 5, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR__FPM_FALLBACK_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 10, 5, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR__SBPM_COPY_READ_G(r, g, idx)                    GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 4, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR__SBPM_COPY_WRITE_G(v, g, idx)                   GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 4, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR__SBPM_COPY_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 10, 4, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR__SBPM_COPY_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 10, 4, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS2_READ_G(r, g, idx)                          GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 0, 12, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS2_WRITE_G(v, g, idx)                         GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 10, 0, 12, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS2_READ(r, p)                                 FIELD_MREAD_16((uint8_t *)p + 10, 0, 12, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS2_WRITE(v, p)                                FIELD_MWRITE_16((uint8_t *)p + 10, 0, 12, v)
+#define RDD_CPU_TX_DESCRIPTOR_DATA_1588_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_DATA_1588_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 8, 0, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_DATA_1588_READ(r, p)                            FIELD_MREAD_32((uint8_t *)p + 8, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_DATA_1588_WRITE(v, p)                           FIELD_MWRITE_32((uint8_t *)p + 8, 0, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_AGG_PD_READ_G(r, g, idx)                        GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 7, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_AGG_PD_WRITE_G(v, g, idx)                       GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 7, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_AGG_PD_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 12, 7, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_AGG_PD_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_TARGET_MEM_0_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 6, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_TARGET_MEM_0_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 6, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_TARGET_MEM_0_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 12, 6, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_TARGET_MEM_0_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 12, 6, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_READ_G(r, g, idx)                           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 5, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_WRITE_G(v, g, idx)                          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 5, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 12, 5, 1, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 12, 5, 1, v)
+#define RDD_CPU_TX_DESCRIPTOR_PAYLOAD_OFFSET_OR_ABS_1_READ_G(r, g, idx)       GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 2, 11, r)
+#define RDD_CPU_TX_DESCRIPTOR_PAYLOAD_OFFSET_OR_ABS_1_WRITE_G(v, g, idx)      GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 2, 11, v)
+#define RDD_CPU_TX_DESCRIPTOR_PAYLOAD_OFFSET_OR_ABS_1_READ(r, p)              FIELD_MREAD_16((uint8_t *)p + 12, 2, 11, r)
+#define RDD_CPU_TX_DESCRIPTOR_PAYLOAD_OFFSET_OR_ABS_1_WRITE(v, p)             FIELD_MWRITE_16((uint8_t *)p + 12, 2, 11, v)
+#define RDD_CPU_TX_DESCRIPTOR_SOP_READ_G(r, g, idx)                           GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 2, 11, r)
+#define RDD_CPU_TX_DESCRIPTOR_SOP_WRITE_G(v, g, idx)                          GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 2, 11, v)
+#define RDD_CPU_TX_DESCRIPTOR_SOP_READ(r, p)                                  FIELD_MREAD_16((uint8_t *)p + 12, 2, 11, r)
+#define RDD_CPU_TX_DESCRIPTOR_SOP_WRITE(v, p)                                 FIELD_MWRITE_16((uint8_t *)p + 12, 2, 11, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS1_READ_G(r, g, idx)                          GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 2, 11, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS1_WRITE_G(v, g, idx)                         GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 2, 11, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS1_READ(r, p)                                 FIELD_MREAD_16((uint8_t *)p + 12, 2, 11, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS1_WRITE(v, p)                                FIELD_MWRITE_16((uint8_t *)p + 12, 2, 11, v)
+#define RDD_CPU_TX_DESCRIPTOR_BUFFER_NUMBER_0_OR_ABS_0_READ_G(r, g, idx)      GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_BUFFER_NUMBER_0_OR_ABS_0_WRITE_G(v, g, idx)     GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 0, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_BUFFER_NUMBER_0_OR_ABS_0_READ(r, p)             FIELD_MREAD_32((uint8_t *)p + 12, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_BUFFER_NUMBER_0_OR_ABS_0_WRITE(v, p)            FIELD_MWRITE_32((uint8_t *)p + 12, 0, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_BN0_FIRST_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_BN0_FIRST_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 0, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_BN0_FIRST_READ(r, p)                            FIELD_MREAD_32((uint8_t *)p + 12, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_BN0_FIRST_WRITE(v, p)                           FIELD_MWRITE_32((uint8_t *)p + 12, 0, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS0_READ_G(r, g, idx)                          GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS0_WRITE_G(v, g, idx)                         GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_TX_DESCRIPTOR_DTS) + 12, 0, 18, v)
+#define RDD_CPU_TX_DESCRIPTOR_ABS0_READ(r, p)                                 FIELD_MREAD_32((uint8_t *)p + 12, 0, 18, r)
+#define RDD_CPU_TX_DESCRIPTOR_ABS0_WRITE(v, p)                                FIELD_MWRITE_32((uint8_t *)p + 12, 0, 18, v)
+/* <<<RDD_CPU_TX_DESCRIPTOR_DTS */
+
+/* <<<RDD_CPU_TX_DESCRIPTOR */
+
+
+/* >>>RDD_PARSE */
+#define PARSE_PARSE_OFFSET                              0
+#define PARSE_SUMMARY_OFFSET                            0
+#define PARSE_SUMMARY_WORD_OFFSET                       0
+#define PARSE_SUMMARY_F_OFFSET_MOD16                    0
+#define PARSE_RESULTS_OFFSET                            4
+#define PARSE_RESULTS_WORD_OFFSET                       1
+#define PARSE_RESULTS_F_OFFSET_MOD16                    8
+#define PARSE_L2_LKP_ENTRY_OFFSET                       32
+#define PARSE_L2_LKP_ENTRY_WORD_OFFSET                  8
+#define PARSE_L2_LKP_ENTRY_F_OFFSET_MOD16               8
+#define PARSE_L3_LKP_ENTRY_OFFSET                       48
+#define PARSE_L3_LKP_ENTRY_WORD_OFFSET                  12
+#define PARSE_L3_LKP_ENTRY_F_OFFSET_MOD16               8
+#define PARSE_IC_LKP_ENTRY_OFFSET                       64
+#define PARSE_IC_LKP_ENTRY_WORD_OFFSET                  16
+#define PARSE_IC_LKP_ENTRY_F_OFFSET_MOD16               8
+
+/* >>>RDD_PARSE_DTS */
+#define RDD_PARSE_SUMMARY_NUMBER	4
+#define RDD_PARSE_RESULTS_NUMBER	28
+#define RDD_PARSE_L2_LKP_ENTRY_NUMBER	16
+#define RDD_PARSE_L3_LKP_ENTRY_NUMBER	16
+#define RDD_PARSE_IC_LKP_ENTRY_NUMBER	32
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint8_t	summary[RDD_PARSE_SUMMARY_NUMBER];
+	uint8_t	results[RDD_PARSE_RESULTS_NUMBER];
+	uint8_t	l2_lkp_entry[RDD_PARSE_L2_LKP_ENTRY_NUMBER];
+	uint8_t	l3_lkp_entry[RDD_PARSE_L3_LKP_ENTRY_NUMBER];
+	uint8_t	ic_lkp_entry[RDD_PARSE_IC_LKP_ENTRY_NUMBER];
+#else
+	uint8_t	summary[RDD_PARSE_SUMMARY_NUMBER];
+	uint8_t	results[RDD_PARSE_RESULTS_NUMBER];
+	uint8_t	l2_lkp_entry[RDD_PARSE_L2_LKP_ENTRY_NUMBER];
+	uint8_t	l3_lkp_entry[RDD_PARSE_L3_LKP_ENTRY_NUMBER];
+	uint8_t	ic_lkp_entry[RDD_PARSE_IC_LKP_ENTRY_NUMBER];
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PARSE_DTS;
+
+typedef union
+{
+    uint32_t word_val[24];
+    uint64_t dword_val64[12];
+    RDD_PARSE_DTS fields;
+} PARSE_STRUCT;
+#define RDD_PARSE_SUMMARY_READ_G(r, g, idx, i)            GROUP_MREAD_I_8(g, idx*sizeof(RDD_PARSE_DTS), i, r)
+#define RDD_PARSE_SUMMARY_WRITE_G(v, g, idx, i)           GROUP_MWRITE_I_8(g, idx*sizeof(RDD_PARSE_DTS), i, v)
+#define RDD_PARSE_SUMMARY_READ(r, p, i)                   MREAD_I_8((uint8_t *)p, i, r)
+#define RDD_PARSE_SUMMARY_WRITE(v, p, i)                  MWRITE_I_8((uint8_t *)p, i, v)
+#define RDD_PARSE_RESULTS_READ_G(r, g, idx, i)            GROUP_MREAD_I_8(g, idx*sizeof(RDD_PARSE_DTS) + 4, i, r)
+#define RDD_PARSE_RESULTS_WRITE_G(v, g, idx, i)           GROUP_MWRITE_I_8(g, idx*sizeof(RDD_PARSE_DTS) + 4, i, v)
+#define RDD_PARSE_RESULTS_READ(r, p, i)                   MREAD_I_8((uint8_t *)p + 4, i, r)
+#define RDD_PARSE_RESULTS_WRITE(v, p, i)                  MWRITE_I_8((uint8_t *)p + 4, i, v)
+#define RDD_PARSE_L2_LKP_ENTRY_READ_G(r, g, idx, i)       GROUP_MREAD_I_8(g, idx*sizeof(RDD_PARSE_DTS) + 32, i, r)
+#define RDD_PARSE_L2_LKP_ENTRY_WRITE_G(v, g, idx, i)      GROUP_MWRITE_I_8(g, idx*sizeof(RDD_PARSE_DTS) + 32, i, v)
+#define RDD_PARSE_L2_LKP_ENTRY_READ(r, p, i)              MREAD_I_8((uint8_t *)p + 32, i, r)
+#define RDD_PARSE_L2_LKP_ENTRY_WRITE(v, p, i)             MWRITE_I_8((uint8_t *)p + 32, i, v)
+#define RDD_PARSE_L3_LKP_ENTRY_READ_G(r, g, idx, i)       GROUP_MREAD_I_8(g, idx*sizeof(RDD_PARSE_DTS) + 48, i, r)
+#define RDD_PARSE_L3_LKP_ENTRY_WRITE_G(v, g, idx, i)      GROUP_MWRITE_I_8(g, idx*sizeof(RDD_PARSE_DTS) + 48, i, v)
+#define RDD_PARSE_L3_LKP_ENTRY_READ(r, p, i)              MREAD_I_8((uint8_t *)p + 48, i, r)
+#define RDD_PARSE_L3_LKP_ENTRY_WRITE(v, p, i)             MWRITE_I_8((uint8_t *)p + 48, i, v)
+#define RDD_PARSE_IC_LKP_ENTRY_READ_G(r, g, idx, i)       GROUP_MREAD_I_8(g, idx*sizeof(RDD_PARSE_DTS) + 64, i, r)
+#define RDD_PARSE_IC_LKP_ENTRY_WRITE_G(v, g, idx, i)      GROUP_MWRITE_I_8(g, idx*sizeof(RDD_PARSE_DTS) + 64, i, v)
+#define RDD_PARSE_IC_LKP_ENTRY_READ(r, p, i)              MREAD_I_8((uint8_t *)p + 64, i, r)
+#define RDD_PARSE_IC_LKP_ENTRY_WRITE(v, p, i)             MWRITE_I_8((uint8_t *)p + 64, i, v)
+/* <<<RDD_PARSE_DTS */
+
+/* <<<RDD_PARSE */
+
+
+/* >>>RDD_PARSER_SUMMARY */
+#define PARSER_SUMMARY_DA_FILTER_MATCH_F_OFFSET                  31
+#define PARSER_SUMMARY_DA_FILTER_MATCH_F_WIDTH                   1
+#define PARSER_SUMMARY_PARSER_SUMMARY_OFFSET                     0
+#define PARSER_SUMMARY_DA_FILTER_MATCH_OFFSET                    0
+#define PARSER_SUMMARY_DA_FILTER_MATCH_WORD_OFFSET               0
+#define PARSER_SUMMARY_DA_FILTER_MATCH_F_OFFSET_MOD8             7
+#define PARSER_SUMMARY_DA_FILTER_MATCH_F_OFFSET_MOD16            15
+#define PARSER_SUMMARY_IP_FRAGMENT_F_OFFSET                      30
+#define PARSER_SUMMARY_IP_FRAGMENT_F_WIDTH                       1
+#define PARSER_SUMMARY_IP_FRAGMENT_OFFSET                        0
+#define PARSER_SUMMARY_IP_FRAGMENT_WORD_OFFSET                   0
+#define PARSER_SUMMARY_IP_FRAGMENT_F_OFFSET_MOD8                 6
+#define PARSER_SUMMARY_IP_FRAGMENT_F_OFFSET_MOD16                14
+#define PARSER_SUMMARY_L4_1588_F_OFFSET                          29
+#define PARSER_SUMMARY_L4_1588_F_WIDTH                           1
+#define PARSER_SUMMARY_L4_1588_OFFSET                            0
+#define PARSER_SUMMARY_L4_1588_WORD_OFFSET                       0
+#define PARSER_SUMMARY_L4_1588_F_OFFSET_MOD8                     5
+#define PARSER_SUMMARY_L4_1588_F_OFFSET_MOD16                    13
+#define PARSER_SUMMARY_TCP_UDP_F_OFFSET                          28
+#define PARSER_SUMMARY_TCP_UDP_F_WIDTH                           1
+#define PARSER_SUMMARY_TCP_UDP_OFFSET                            0
+#define PARSER_SUMMARY_TCP_UDP_WORD_OFFSET                       0
+#define PARSER_SUMMARY_TCP_UDP_F_OFFSET_MOD8                     4
+#define PARSER_SUMMARY_TCP_UDP_F_OFFSET_MOD16                    12
+#define PARSER_SUMMARY_DHCP_F_OFFSET                             27
+#define PARSER_SUMMARY_DHCP_F_WIDTH                              1
+#define PARSER_SUMMARY_DHCP_OFFSET                               0
+#define PARSER_SUMMARY_DHCP_WORD_OFFSET                          0
+#define PARSER_SUMMARY_DHCP_F_OFFSET_MOD8                        3
+#define PARSER_SUMMARY_DHCP_F_OFFSET_MOD16                       11
+#define PARSER_SUMMARY_BROADCAST_F_OFFSET                        26
+#define PARSER_SUMMARY_BROADCAST_F_WIDTH                         1
+#define PARSER_SUMMARY_BROADCAST_OFFSET                          0
+#define PARSER_SUMMARY_BROADCAST_WORD_OFFSET                     0
+#define PARSER_SUMMARY_BROADCAST_F_OFFSET_MOD8                   2
+#define PARSER_SUMMARY_BROADCAST_F_OFFSET_MOD16                  10
+#define PARSER_SUMMARY_MULTICAST_F_OFFSET                        25
+#define PARSER_SUMMARY_MULTICAST_F_WIDTH                         1
+#define PARSER_SUMMARY_MULTICAST_OFFSET                          0
+#define PARSER_SUMMARY_MULTICAST_WORD_OFFSET                     0
+#define PARSER_SUMMARY_MULTICAST_F_OFFSET_MOD8                   1
+#define PARSER_SUMMARY_MULTICAST_F_OFFSET_MOD16                  9
+#define PARSER_SUMMARY_DOS_ATTACK_F_OFFSET                       24
+#define PARSER_SUMMARY_DOS_ATTACK_F_WIDTH                        1
+#define PARSER_SUMMARY_DOS_ATTACK_OFFSET                         0
+#define PARSER_SUMMARY_DOS_ATTACK_WORD_OFFSET                    0
+#define PARSER_SUMMARY_DOS_ATTACK_F_OFFSET_MOD8                  0
+#define PARSER_SUMMARY_DOS_ATTACK_F_OFFSET_MOD16                 8
+#define PARSER_SUMMARY_MC_L3_CTL_F_OFFSET                        23
+#define PARSER_SUMMARY_MC_L3_CTL_F_WIDTH                         1
+#define PARSER_SUMMARY_MC_L3_CTL_OFFSET                          1
+#define PARSER_SUMMARY_MC_L3_CTL_WORD_OFFSET                     0
+#define PARSER_SUMMARY_MC_L3_CTL_F_OFFSET_MOD8                   7
+#define PARSER_SUMMARY_MC_L3_CTL_F_OFFSET_MOD16                  7
+#define PARSER_SUMMARY_IP_LENGTH_ERROR_F_OFFSET                  22
+#define PARSER_SUMMARY_IP_LENGTH_ERROR_F_WIDTH                   1
+#define PARSER_SUMMARY_IP_LENGTH_ERROR_OFFSET                    1
+#define PARSER_SUMMARY_IP_LENGTH_ERROR_WORD_OFFSET               0
+#define PARSER_SUMMARY_IP_LENGTH_ERROR_F_OFFSET_MOD8             6
+#define PARSER_SUMMARY_IP_LENGTH_ERROR_F_OFFSET_MOD16            6
+#define PARSER_SUMMARY_ICMPV6_F_OFFSET                           21
+#define PARSER_SUMMARY_ICMPV6_F_WIDTH                            1
+#define PARSER_SUMMARY_ICMPV6_OFFSET                             1
+#define PARSER_SUMMARY_ICMPV6_WORD_OFFSET                        0
+#define PARSER_SUMMARY_ICMPV6_F_OFFSET_MOD8                      5
+#define PARSER_SUMMARY_ICMPV6_F_OFFSET_MOD16                     5
+#define PARSER_SUMMARY_HEADER_LENGTH_ERROR_F_OFFSET              20
+#define PARSER_SUMMARY_HEADER_LENGTH_ERROR_F_WIDTH               1
+#define PARSER_SUMMARY_HEADER_LENGTH_ERROR_OFFSET                1
+#define PARSER_SUMMARY_HEADER_LENGTH_ERROR_WORD_OFFSET           0
+#define PARSER_SUMMARY_HEADER_LENGTH_ERROR_F_OFFSET_MOD8         4
+#define PARSER_SUMMARY_HEADER_LENGTH_ERROR_F_OFFSET_MOD16        4
+#define PARSER_SUMMARY_CHECKSUM_ERROR_F_OFFSET                   19
+#define PARSER_SUMMARY_CHECKSUM_ERROR_F_WIDTH                    1
+#define PARSER_SUMMARY_CHECKSUM_ERROR_OFFSET                     1
+#define PARSER_SUMMARY_CHECKSUM_ERROR_WORD_OFFSET                0
+#define PARSER_SUMMARY_CHECKSUM_ERROR_F_OFFSET_MOD8              3
+#define PARSER_SUMMARY_CHECKSUM_ERROR_F_OFFSET_MOD16             3
+#define PARSER_SUMMARY_VERSION_MISMATCH_F_OFFSET                 18
+#define PARSER_SUMMARY_VERSION_MISMATCH_F_WIDTH                  1
+#define PARSER_SUMMARY_VERSION_MISMATCH_OFFSET                   1
+#define PARSER_SUMMARY_VERSION_MISMATCH_WORD_OFFSET              0
+#define PARSER_SUMMARY_VERSION_MISMATCH_F_OFFSET_MOD8            2
+#define PARSER_SUMMARY_VERSION_MISMATCH_F_OFFSET_MOD16           2
+#define PARSER_SUMMARY_L3_PROTOCOL_F_OFFSET                      16
+#define PARSER_SUMMARY_L3_PROTOCOL_F_WIDTH                       2
+#define PARSER_SUMMARY_L3_PROTOCOL_OFFSET                        1
+#define PARSER_SUMMARY_L3_PROTOCOL_WORD_OFFSET                   0
+#define PARSER_SUMMARY_L3_PROTOCOL_F_OFFSET_MOD8                 0
+#define PARSER_SUMMARY_L3_PROTOCOL_F_OFFSET_MOD16                0
+#define PARSER_SUMMARY_IPV6_EXT_HEADER_FILTER_F_OFFSET           15
+#define PARSER_SUMMARY_IPV6_EXT_HEADER_FILTER_F_WIDTH            1
+#define PARSER_SUMMARY_IPV6_EXT_HEADER_FILTER_OFFSET             2
+#define PARSER_SUMMARY_IPV6_EXT_HEADER_FILTER_WORD_OFFSET        0
+#define PARSER_SUMMARY_IPV6_EXT_HEADER_FILTER_F_OFFSET_MOD8      7
+#define PARSER_SUMMARY_IPV6_EXT_HEADER_FILTER_F_OFFSET_MOD16     15
+#define PARSER_SUMMARY_TCP_FLAG_F_OFFSET                         14
+#define PARSER_SUMMARY_TCP_FLAG_F_WIDTH                          1
+#define PARSER_SUMMARY_TCP_FLAG_OFFSET                           2
+#define PARSER_SUMMARY_TCP_FLAG_WORD_OFFSET                      0
+#define PARSER_SUMMARY_TCP_FLAG_F_OFFSET_MOD8                    6
+#define PARSER_SUMMARY_TCP_FLAG_F_OFFSET_MOD16                   14
+#define PARSER_SUMMARY_EXCEPTION_F_OFFSET                        13
+#define PARSER_SUMMARY_EXCEPTION_F_WIDTH                         1
+#define PARSER_SUMMARY_EXCEPTION_OFFSET                          2
+#define PARSER_SUMMARY_EXCEPTION_WORD_OFFSET                     0
+#define PARSER_SUMMARY_EXCEPTION_F_OFFSET_MOD8                   5
+#define PARSER_SUMMARY_EXCEPTION_F_OFFSET_MOD16                  13
+#define PARSER_SUMMARY_IP_MC_L2_F_OFFSET                         12
+#define PARSER_SUMMARY_IP_MC_L2_F_WIDTH                          1
+#define PARSER_SUMMARY_IP_MC_L2_OFFSET                           2
+#define PARSER_SUMMARY_IP_MC_L2_WORD_OFFSET                      0
+#define PARSER_SUMMARY_IP_MC_L2_F_OFFSET_MOD8                    4
+#define PARSER_SUMMARY_IP_MC_L2_F_OFFSET_MOD16                   12
+#define PARSER_SUMMARY_MC_L3_F_OFFSET                            11
+#define PARSER_SUMMARY_MC_L3_F_WIDTH                             1
+#define PARSER_SUMMARY_MC_L3_OFFSET                              2
+#define PARSER_SUMMARY_MC_L3_WORD_OFFSET                         0
+#define PARSER_SUMMARY_MC_L3_F_OFFSET_MOD8                       3
+#define PARSER_SUMMARY_MC_L3_F_OFFSET_MOD16                      11
+#define PARSER_SUMMARY_ERROR_F_OFFSET                            10
+#define PARSER_SUMMARY_ERROR_F_WIDTH                             1
+#define PARSER_SUMMARY_ERROR_OFFSET                              2
+#define PARSER_SUMMARY_ERROR_WORD_OFFSET                         0
+#define PARSER_SUMMARY_ERROR_F_OFFSET_MOD8                       2
+#define PARSER_SUMMARY_ERROR_F_OFFSET_MOD16                      10
+#define PARSER_SUMMARY_TUNNEL_F_OFFSET                           9
+#define PARSER_SUMMARY_TUNNEL_F_WIDTH                            1
+#define PARSER_SUMMARY_TUNNEL_OFFSET                             2
+#define PARSER_SUMMARY_TUNNEL_WORD_OFFSET                        0
+#define PARSER_SUMMARY_TUNNEL_F_OFFSET_MOD8                      1
+#define PARSER_SUMMARY_TUNNEL_F_OFFSET_MOD16                     9
+#define PARSER_SUMMARY__5_TUP_VALID_F_OFFSET                     8
+#define PARSER_SUMMARY__5_TUP_VALID_F_WIDTH                      1
+#define PARSER_SUMMARY__5_TUP_VALID_OFFSET                       2
+#define PARSER_SUMMARY__5_TUP_VALID_WORD_OFFSET                  0
+#define PARSER_SUMMARY__5_TUP_VALID_F_OFFSET_MOD8                0
+#define PARSER_SUMMARY__5_TUP_VALID_F_OFFSET_MOD16               8
+#define PARSER_SUMMARY_ETHERNET_VERSION_F_OFFSET                 6
+#define PARSER_SUMMARY_ETHERNET_VERSION_F_WIDTH                  2
+#define PARSER_SUMMARY_ETHERNET_VERSION_OFFSET                   3
+#define PARSER_SUMMARY_ETHERNET_VERSION_WORD_OFFSET              0
+#define PARSER_SUMMARY_ETHERNET_VERSION_F_OFFSET_MOD8            6
+#define PARSER_SUMMARY_ETHERNET_VERSION_F_OFFSET_MOD16           6
+#define PARSER_SUMMARY_DNS_F_OFFSET                              5
+#define PARSER_SUMMARY_DNS_F_WIDTH                               1
+#define PARSER_SUMMARY_DNS_OFFSET                                3
+#define PARSER_SUMMARY_DNS_WORD_OFFSET                           0
+#define PARSER_SUMMARY_DNS_F_OFFSET_MOD8                         5
+#define PARSER_SUMMARY_DNS_F_OFFSET_MOD16                        5
+#define PARSER_SUMMARY_FIRST_IP_FRAGMENT_F_OFFSET                4
+#define PARSER_SUMMARY_FIRST_IP_FRAGMENT_F_WIDTH                 1
+#define PARSER_SUMMARY_FIRST_IP_FRAGMENT_OFFSET                  3
+#define PARSER_SUMMARY_FIRST_IP_FRAGMENT_WORD_OFFSET             0
+#define PARSER_SUMMARY_FIRST_IP_FRAGMENT_F_OFFSET_MOD8           4
+#define PARSER_SUMMARY_FIRST_IP_FRAGMENT_F_OFFSET_MOD16          4
+#define PARSER_SUMMARY_L2_PROTOCOL_F_OFFSET                      0
+#define PARSER_SUMMARY_L2_PROTOCOL_F_WIDTH                       4
+#define PARSER_SUMMARY_L2_PROTOCOL_OFFSET                        3
+#define PARSER_SUMMARY_L2_PROTOCOL_WORD_OFFSET                   0
+#define PARSER_SUMMARY_L2_PROTOCOL_F_OFFSET_MOD8                 0
+#define PARSER_SUMMARY_L2_PROTOCOL_F_OFFSET_MOD16                0
+
+/* >>>RDD_PARSER_SUMMARY_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	da_filter_match       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_fragment           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l4_1588               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_udp               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhcp                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	broadcast             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dos_attack            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mc_l3_ctl             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_length_error       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	icmpv6                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	header_length_error   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	checksum_error        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	version_mismatch      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l3_protocol           	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipv6_ext_header_filter	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_flag              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	exception             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_mc_l2              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mc_l3                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tunnel                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	_5_tup_valid          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ethernet_version      	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dns                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	first_ip_fragment     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l2_protocol           	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#else
+	uint32_t	l2_protocol           	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	first_ip_fragment     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dns                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ethernet_version      	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	_5_tup_valid          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tunnel                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	error                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mc_l3                 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_mc_l2              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	exception             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_flag              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipv6_ext_header_filter	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l3_protocol           	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	version_mismatch      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	checksum_error        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	header_length_error   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	icmpv6                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_length_error       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	mc_l3_ctl             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dos_attack            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	multicast             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	broadcast             	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dhcp                  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_udp               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l4_1588               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_fragment           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	da_filter_match       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PARSER_SUMMARY_DTS;
+
+typedef union
+{
+    uint32_t word_val[1];
+    RDD_PARSER_SUMMARY_DTS fields;
+} PARSER_SUMMARY_STRUCT;
+#define RDD_PARSER_SUMMARY_DA_FILTER_MATCH_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 7, 1, r)
+#define RDD_PARSER_SUMMARY_DA_FILTER_MATCH_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 7, 1, v)
+#define RDD_PARSER_SUMMARY_DA_FILTER_MATCH_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_PARSER_SUMMARY_DA_FILTER_MATCH_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_PARSER_SUMMARY_IP_FRAGMENT_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 6, 1, r)
+#define RDD_PARSER_SUMMARY_IP_FRAGMENT_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 6, 1, v)
+#define RDD_PARSER_SUMMARY_IP_FRAGMENT_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p, 6, 1, r)
+#define RDD_PARSER_SUMMARY_IP_FRAGMENT_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p, 6, 1, v)
+#define RDD_PARSER_SUMMARY_L4_1588_READ_G(r, g, idx)                         GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 5, 1, r)
+#define RDD_PARSER_SUMMARY_L4_1588_WRITE_G(v, g, idx)                        GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 5, 1, v)
+#define RDD_PARSER_SUMMARY_L4_1588_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p, 5, 1, r)
+#define RDD_PARSER_SUMMARY_L4_1588_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p, 5, 1, v)
+#define RDD_PARSER_SUMMARY_TCP_UDP_READ_G(r, g, idx)                         GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 4, 1, r)
+#define RDD_PARSER_SUMMARY_TCP_UDP_WRITE_G(v, g, idx)                        GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 4, 1, v)
+#define RDD_PARSER_SUMMARY_TCP_UDP_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p, 4, 1, r)
+#define RDD_PARSER_SUMMARY_TCP_UDP_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p, 4, 1, v)
+#define RDD_PARSER_SUMMARY_DHCP_READ_G(r, g, idx)                            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 3, 1, r)
+#define RDD_PARSER_SUMMARY_DHCP_WRITE_G(v, g, idx)                           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 3, 1, v)
+#define RDD_PARSER_SUMMARY_DHCP_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p, 3, 1, r)
+#define RDD_PARSER_SUMMARY_DHCP_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p, 3, 1, v)
+#define RDD_PARSER_SUMMARY_BROADCAST_READ_G(r, g, idx)                       GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 2, 1, r)
+#define RDD_PARSER_SUMMARY_BROADCAST_WRITE_G(v, g, idx)                      GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 2, 1, v)
+#define RDD_PARSER_SUMMARY_BROADCAST_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p, 2, 1, r)
+#define RDD_PARSER_SUMMARY_BROADCAST_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p, 2, 1, v)
+#define RDD_PARSER_SUMMARY_MULTICAST_READ_G(r, g, idx)                       GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 1, 1, r)
+#define RDD_PARSER_SUMMARY_MULTICAST_WRITE_G(v, g, idx)                      GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 1, 1, v)
+#define RDD_PARSER_SUMMARY_MULTICAST_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p, 1, 1, r)
+#define RDD_PARSER_SUMMARY_MULTICAST_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p, 1, 1, v)
+#define RDD_PARSER_SUMMARY_DOS_ATTACK_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 0, 1, r)
+#define RDD_PARSER_SUMMARY_DOS_ATTACK_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS), 0, 1, v)
+#define RDD_PARSER_SUMMARY_DOS_ATTACK_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p, 0, 1, r)
+#define RDD_PARSER_SUMMARY_DOS_ATTACK_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p, 0, 1, v)
+#define RDD_PARSER_SUMMARY_MC_L3_CTL_READ_G(r, g, idx)                       GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 7, 1, r)
+#define RDD_PARSER_SUMMARY_MC_L3_CTL_WRITE_G(v, g, idx)                      GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 7, 1, v)
+#define RDD_PARSER_SUMMARY_MC_L3_CTL_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 1, 7, 1, r)
+#define RDD_PARSER_SUMMARY_MC_L3_CTL_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 1, 7, 1, v)
+#define RDD_PARSER_SUMMARY_IP_LENGTH_ERROR_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 6, 1, r)
+#define RDD_PARSER_SUMMARY_IP_LENGTH_ERROR_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 6, 1, v)
+#define RDD_PARSER_SUMMARY_IP_LENGTH_ERROR_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 1, 6, 1, r)
+#define RDD_PARSER_SUMMARY_IP_LENGTH_ERROR_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 1, 6, 1, v)
+#define RDD_PARSER_SUMMARY_ICMPV6_READ_G(r, g, idx)                          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 5, 1, r)
+#define RDD_PARSER_SUMMARY_ICMPV6_WRITE_G(v, g, idx)                         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 5, 1, v)
+#define RDD_PARSER_SUMMARY_ICMPV6_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 1, 5, 1, r)
+#define RDD_PARSER_SUMMARY_ICMPV6_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 1, 5, 1, v)
+#define RDD_PARSER_SUMMARY_HEADER_LENGTH_ERROR_READ_G(r, g, idx)             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 4, 1, r)
+#define RDD_PARSER_SUMMARY_HEADER_LENGTH_ERROR_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 4, 1, v)
+#define RDD_PARSER_SUMMARY_HEADER_LENGTH_ERROR_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 1, 4, 1, r)
+#define RDD_PARSER_SUMMARY_HEADER_LENGTH_ERROR_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 1, 4, 1, v)
+#define RDD_PARSER_SUMMARY_CHECKSUM_ERROR_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 3, 1, r)
+#define RDD_PARSER_SUMMARY_CHECKSUM_ERROR_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 3, 1, v)
+#define RDD_PARSER_SUMMARY_CHECKSUM_ERROR_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 1, 3, 1, r)
+#define RDD_PARSER_SUMMARY_CHECKSUM_ERROR_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 1, 3, 1, v)
+#define RDD_PARSER_SUMMARY_VERSION_MISMATCH_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 2, 1, r)
+#define RDD_PARSER_SUMMARY_VERSION_MISMATCH_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 2, 1, v)
+#define RDD_PARSER_SUMMARY_VERSION_MISMATCH_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 1, 2, 1, r)
+#define RDD_PARSER_SUMMARY_VERSION_MISMATCH_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 1, 2, 1, v)
+#define RDD_PARSER_SUMMARY_L3_PROTOCOL_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 0, 2, r)
+#define RDD_PARSER_SUMMARY_L3_PROTOCOL_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 1, 0, 2, v)
+#define RDD_PARSER_SUMMARY_L3_PROTOCOL_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 1, 0, 2, r)
+#define RDD_PARSER_SUMMARY_L3_PROTOCOL_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 1, 0, 2, v)
+#define RDD_PARSER_SUMMARY_IPV6_EXT_HEADER_FILTER_READ_G(r, g, idx)          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 7, 1, r)
+#define RDD_PARSER_SUMMARY_IPV6_EXT_HEADER_FILTER_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 7, 1, v)
+#define RDD_PARSER_SUMMARY_IPV6_EXT_HEADER_FILTER_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 2, 7, 1, r)
+#define RDD_PARSER_SUMMARY_IPV6_EXT_HEADER_FILTER_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 2, 7, 1, v)
+#define RDD_PARSER_SUMMARY_TCP_FLAG_READ_G(r, g, idx)                        GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 6, 1, r)
+#define RDD_PARSER_SUMMARY_TCP_FLAG_WRITE_G(v, g, idx)                       GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 6, 1, v)
+#define RDD_PARSER_SUMMARY_TCP_FLAG_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 2, 6, 1, r)
+#define RDD_PARSER_SUMMARY_TCP_FLAG_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 2, 6, 1, v)
+#define RDD_PARSER_SUMMARY_EXCEPTION_READ_G(r, g, idx)                       GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 5, 1, r)
+#define RDD_PARSER_SUMMARY_EXCEPTION_WRITE_G(v, g, idx)                      GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 5, 1, v)
+#define RDD_PARSER_SUMMARY_EXCEPTION_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 2, 5, 1, r)
+#define RDD_PARSER_SUMMARY_EXCEPTION_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 2, 5, 1, v)
+#define RDD_PARSER_SUMMARY_IP_MC_L2_READ_G(r, g, idx)                        GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 4, 1, r)
+#define RDD_PARSER_SUMMARY_IP_MC_L2_WRITE_G(v, g, idx)                       GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 4, 1, v)
+#define RDD_PARSER_SUMMARY_IP_MC_L2_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 2, 4, 1, r)
+#define RDD_PARSER_SUMMARY_IP_MC_L2_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 2, 4, 1, v)
+#define RDD_PARSER_SUMMARY_MC_L3_READ_G(r, g, idx)                           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 3, 1, r)
+#define RDD_PARSER_SUMMARY_MC_L3_WRITE_G(v, g, idx)                          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 3, 1, v)
+#define RDD_PARSER_SUMMARY_MC_L3_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 2, 3, 1, r)
+#define RDD_PARSER_SUMMARY_MC_L3_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 2, 3, 1, v)
+#define RDD_PARSER_SUMMARY_ERROR_READ_G(r, g, idx)                           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 2, 1, r)
+#define RDD_PARSER_SUMMARY_ERROR_WRITE_G(v, g, idx)                          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 2, 1, v)
+#define RDD_PARSER_SUMMARY_ERROR_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 2, 2, 1, r)
+#define RDD_PARSER_SUMMARY_ERROR_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 2, 2, 1, v)
+#define RDD_PARSER_SUMMARY_TUNNEL_READ_G(r, g, idx)                          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 1, 1, r)
+#define RDD_PARSER_SUMMARY_TUNNEL_WRITE_G(v, g, idx)                         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 1, 1, v)
+#define RDD_PARSER_SUMMARY_TUNNEL_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 2, 1, 1, r)
+#define RDD_PARSER_SUMMARY_TUNNEL_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 2, 1, 1, v)
+#define RDD_PARSER_SUMMARY__5_TUP_VALID_READ_G(r, g, idx)                    GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 0, 1, r)
+#define RDD_PARSER_SUMMARY__5_TUP_VALID_WRITE_G(v, g, idx)                   GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 2, 0, 1, v)
+#define RDD_PARSER_SUMMARY__5_TUP_VALID_READ(r, p)                           FIELD_MREAD_8((uint8_t *)p + 2, 0, 1, r)
+#define RDD_PARSER_SUMMARY__5_TUP_VALID_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 2, 0, 1, v)
+#define RDD_PARSER_SUMMARY_ETHERNET_VERSION_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 3, 6, 2, r)
+#define RDD_PARSER_SUMMARY_ETHERNET_VERSION_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 3, 6, 2, v)
+#define RDD_PARSER_SUMMARY_ETHERNET_VERSION_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 3, 6, 2, r)
+#define RDD_PARSER_SUMMARY_ETHERNET_VERSION_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 3, 6, 2, v)
+#define RDD_PARSER_SUMMARY_DNS_READ_G(r, g, idx)                             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 3, 5, 1, r)
+#define RDD_PARSER_SUMMARY_DNS_WRITE_G(v, g, idx)                            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 3, 5, 1, v)
+#define RDD_PARSER_SUMMARY_DNS_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 3, 5, 1, r)
+#define RDD_PARSER_SUMMARY_DNS_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 3, 5, 1, v)
+#define RDD_PARSER_SUMMARY_FIRST_IP_FRAGMENT_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 3, 4, 1, r)
+#define RDD_PARSER_SUMMARY_FIRST_IP_FRAGMENT_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 3, 4, 1, v)
+#define RDD_PARSER_SUMMARY_FIRST_IP_FRAGMENT_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 3, 4, 1, r)
+#define RDD_PARSER_SUMMARY_FIRST_IP_FRAGMENT_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 3, 4, 1, v)
+#define RDD_PARSER_SUMMARY_L2_PROTOCOL_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 3, 0, 4, r)
+#define RDD_PARSER_SUMMARY_L2_PROTOCOL_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_SUMMARY_DTS) + 3, 0, 4, v)
+#define RDD_PARSER_SUMMARY_L2_PROTOCOL_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 3, 0, 4, r)
+#define RDD_PARSER_SUMMARY_L2_PROTOCOL_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 3, 0, 4, v)
+/* <<<RDD_PARSER_SUMMARY_DTS */
+
+/* <<<RDD_PARSER_SUMMARY */
+
+
+/* >>>RDD_PARSER_RESULTS */
+#define PARSER_RESULTS_L4_PROTOCOL_F_OFFSET                      28
+#define PARSER_RESULTS_L4_PROTOCOL_F_WIDTH                       4
+#define PARSER_RESULTS_PARSER_RESULTS_OFFSET                     0
+#define PARSER_RESULTS_L4_PROTOCOL_OFFSET                        0
+#define PARSER_RESULTS_L4_PROTOCOL_WORD_OFFSET                   0
+#define PARSER_RESULTS_L4_PROTOCOL_F_OFFSET_MOD8                 4
+#define PARSER_RESULTS_L4_PROTOCOL_F_OFFSET_MOD16                12
+#define PARSER_RESULTS_V6_AH_F_OFFSET                            27
+#define PARSER_RESULTS_V6_AH_F_WIDTH                             1
+#define PARSER_RESULTS_V6_AH_OFFSET                              0
+#define PARSER_RESULTS_V6_AH_WORD_OFFSET                         0
+#define PARSER_RESULTS_V6_AH_F_OFFSET_MOD8                       3
+#define PARSER_RESULTS_V6_AH_F_OFFSET_MOD16                      11
+#define PARSER_RESULTS_V6_DEST_OPT_F_OFFSET                      26
+#define PARSER_RESULTS_V6_DEST_OPT_F_WIDTH                       1
+#define PARSER_RESULTS_V6_DEST_OPT_OFFSET                        0
+#define PARSER_RESULTS_V6_DEST_OPT_WORD_OFFSET                   0
+#define PARSER_RESULTS_V6_DEST_OPT_F_OFFSET_MOD8                 2
+#define PARSER_RESULTS_V6_DEST_OPT_F_OFFSET_MOD16                10
+#define PARSER_RESULTS_V6_ROUTE_F_OFFSET                         25
+#define PARSER_RESULTS_V6_ROUTE_F_WIDTH                          1
+#define PARSER_RESULTS_V6_ROUTE_OFFSET                           0
+#define PARSER_RESULTS_V6_ROUTE_WORD_OFFSET                      0
+#define PARSER_RESULTS_V6_ROUTE_F_OFFSET_MOD8                    1
+#define PARSER_RESULTS_V6_ROUTE_F_OFFSET_MOD16                   9
+#define PARSER_RESULTS_V6_HOP_F_OFFSET                           24
+#define PARSER_RESULTS_V6_HOP_F_WIDTH                            1
+#define PARSER_RESULTS_V6_HOP_OFFSET                             0
+#define PARSER_RESULTS_V6_HOP_WORD_OFFSET                        0
+#define PARSER_RESULTS_V6_HOP_F_OFFSET_MOD8                      0
+#define PARSER_RESULTS_V6_HOP_F_OFFSET_MOD16                     8
+#define PARSER_RESULTS_TCP_FLAGS_F_OFFSET                        16
+#define PARSER_RESULTS_TCP_FLAGS_F_WIDTH                         8
+#define PARSER_RESULTS_TCP_FLAGS_OFFSET                          1
+#define PARSER_RESULTS_TCP_FLAGS_WORD_OFFSET                     0
+#define PARSER_RESULTS_TCP_FLAGS_F_OFFSET_MOD16                  0
+#define PARSER_RESULTS_LAYER3_OFFSET_F_OFFSET                    8
+#define PARSER_RESULTS_LAYER3_OFFSET_F_WIDTH                     8
+#define PARSER_RESULTS_LAYER3_OFFSET_OFFSET                      2
+#define PARSER_RESULTS_LAYER3_OFFSET_WORD_OFFSET                 0
+#define PARSER_RESULTS_LAYER3_OFFSET_F_OFFSET_MOD16              8
+#define PARSER_RESULTS_LAYER4_OFFSET_F_OFFSET                    0
+#define PARSER_RESULTS_LAYER4_OFFSET_F_WIDTH                     8
+#define PARSER_RESULTS_LAYER4_OFFSET_OFFSET                      3
+#define PARSER_RESULTS_LAYER4_OFFSET_WORD_OFFSET                 0
+#define PARSER_RESULTS_LAYER4_OFFSET_F_OFFSET_MOD16              0
+#define PARSER_RESULTS_OUTER_VLAN_F_OFFSET                       16
+#define PARSER_RESULTS_OUTER_VLAN_F_WIDTH                        16
+#define PARSER_RESULTS_OUTER_VLAN_OFFSET                         4
+#define PARSER_RESULTS_OUTER_VLAN_WORD_OFFSET                    1
+#define PARSER_RESULTS_MAC_DA1_2_F_OFFSET                        0
+#define PARSER_RESULTS_MAC_DA1_2_F_WIDTH                         16
+#define PARSER_RESULTS_MAC_DA1_2_OFFSET                          6
+#define PARSER_RESULTS_MAC_DA1_2_WORD_OFFSET                     1
+#define PARSER_RESULTS_MAC_DA3_6_F_OFFSET                        0
+#define PARSER_RESULTS_MAC_DA3_6_F_WIDTH                         32
+#define PARSER_RESULTS_MAC_DA3_6_OFFSET                          8
+#define PARSER_RESULTS_MAC_DA3_6_WORD_OFFSET                     2
+#define PARSER_RESULTS_INNER_VLAN_F_OFFSET                       16
+#define PARSER_RESULTS_INNER_VLAN_F_WIDTH                        16
+#define PARSER_RESULTS_INNER_VLAN_OFFSET                         12
+#define PARSER_RESULTS_INNER_VLAN_WORD_OFFSET                    3
+#define PARSER_RESULTS_MAC_SA1_2_F_OFFSET                        0
+#define PARSER_RESULTS_MAC_SA1_2_F_WIDTH                         16
+#define PARSER_RESULTS_MAC_SA1_2_OFFSET                          14
+#define PARSER_RESULTS_MAC_SA1_2_WORD_OFFSET                     3
+#define PARSER_RESULTS_MAC_SA3_6_F_OFFSET                        0
+#define PARSER_RESULTS_MAC_SA3_6_F_WIDTH                         32
+#define PARSER_RESULTS_MAC_SA3_6_OFFSET                          16
+#define PARSER_RESULTS_MAC_SA3_6_WORD_OFFSET                     4
+#define PARSER_RESULTS_ICMPV6_TYPE_F_OFFSET                      24
+#define PARSER_RESULTS_ICMPV6_TYPE_F_WIDTH                       8
+#define PARSER_RESULTS_ICMPV6_TYPE_OFFSET                        20
+#define PARSER_RESULTS_ICMPV6_TYPE_WORD_OFFSET                   5
+#define PARSER_RESULTS_ICMPV6_TYPE_F_OFFSET_MOD16                8
+#define PARSER_RESULTS_IP_TTL_F_OFFSET                           16
+#define PARSER_RESULTS_IP_TTL_F_WIDTH                            8
+#define PARSER_RESULTS_IP_TTL_OFFSET                             21
+#define PARSER_RESULTS_IP_TTL_WORD_OFFSET                        5
+#define PARSER_RESULTS_IP_TTL_F_OFFSET_MOD16                     0
+#define PARSER_RESULTS_IP_LENGTH_F_OFFSET                        0
+#define PARSER_RESULTS_IP_LENGTH_F_WIDTH                         16
+#define PARSER_RESULTS_IP_LENGTH_OFFSET                          22
+#define PARSER_RESULTS_IP_LENGTH_WORD_OFFSET                     5
+#define PARSER_RESULTS_IP_FILTER_MATCH_F_OFFSET                  31
+#define PARSER_RESULTS_IP_FILTER_MATCH_F_WIDTH                   1
+#define PARSER_RESULTS_IP_FILTER_MATCH_OFFSET                    24
+#define PARSER_RESULTS_IP_FILTER_MATCH_WORD_OFFSET               6
+#define PARSER_RESULTS_IP_FILTER_MATCH_F_OFFSET_MOD8             7
+#define PARSER_RESULTS_IP_FILTER_MATCH_F_OFFSET_MOD16            15
+#define PARSER_RESULTS_IP_FILTER_NUM_F_OFFSET                    30
+#define PARSER_RESULTS_IP_FILTER_NUM_F_WIDTH                     1
+#define PARSER_RESULTS_IP_FILTER_NUM_OFFSET                      24
+#define PARSER_RESULTS_IP_FILTER_NUM_WORD_OFFSET                 6
+#define PARSER_RESULTS_IP_FILTER_NUM_F_OFFSET_MOD8               6
+#define PARSER_RESULTS_IP_FILTER_NUM_F_OFFSET_MOD16              14
+#define PARSER_RESULTS_P_TAG_F_OFFSET                            29
+#define PARSER_RESULTS_P_TAG_F_WIDTH                             1
+#define PARSER_RESULTS_P_TAG_OFFSET                              24
+#define PARSER_RESULTS_P_TAG_WORD_OFFSET                         6
+#define PARSER_RESULTS_P_TAG_F_OFFSET_MOD8                       5
+#define PARSER_RESULTS_P_TAG_F_OFFSET_MOD16                      13
+#define PARSER_RESULTS_VID_FILTER_HIT_F_OFFSET                   28
+#define PARSER_RESULTS_VID_FILTER_HIT_F_WIDTH                    1
+#define PARSER_RESULTS_VID_FILTER_HIT_OFFSET                     24
+#define PARSER_RESULTS_VID_FILTER_HIT_WORD_OFFSET                6
+#define PARSER_RESULTS_VID_FILTER_HIT_F_OFFSET_MOD8              4
+#define PARSER_RESULTS_VID_FILTER_HIT_F_OFFSET_MOD16             12
+#define PARSER_RESULTS_DA_FILTER_NUMBER_F_OFFSET                 24
+#define PARSER_RESULTS_DA_FILTER_NUMBER_F_WIDTH                  4
+#define PARSER_RESULTS_DA_FILTER_NUMBER_OFFSET                   24
+#define PARSER_RESULTS_DA_FILTER_NUMBER_WORD_OFFSET              6
+#define PARSER_RESULTS_DA_FILTER_NUMBER_F_OFFSET_MOD8            0
+#define PARSER_RESULTS_DA_FILTER_NUMBER_F_OFFSET_MOD16           8
+#define PARSER_RESULTS_TAG_TYPE_F_OFFSET                         22
+#define PARSER_RESULTS_TAG_TYPE_F_WIDTH                          2
+#define PARSER_RESULTS_TAG_TYPE_OFFSET                           25
+#define PARSER_RESULTS_TAG_TYPE_WORD_OFFSET                      6
+#define PARSER_RESULTS_TAG_TYPE_F_OFFSET_MOD8                    6
+#define PARSER_RESULTS_TAG_TYPE_F_OFFSET_MOD16                   6
+#define PARSER_RESULTS_TPID_VLAN_0_F_OFFSET                      19
+#define PARSER_RESULTS_TPID_VLAN_0_F_WIDTH                       3
+#define PARSER_RESULTS_TPID_VLAN_0_OFFSET                        25
+#define PARSER_RESULTS_TPID_VLAN_0_WORD_OFFSET                   6
+#define PARSER_RESULTS_TPID_VLAN_0_F_OFFSET_MOD8                 3
+#define PARSER_RESULTS_TPID_VLAN_0_F_OFFSET_MOD16                3
+#define PARSER_RESULTS_TPID_VLAN_1_F_OFFSET                      16
+#define PARSER_RESULTS_TPID_VLAN_1_F_WIDTH                       3
+#define PARSER_RESULTS_TPID_VLAN_1_OFFSET                        25
+#define PARSER_RESULTS_TPID_VLAN_1_WORD_OFFSET                   6
+#define PARSER_RESULTS_TPID_VLAN_1_F_OFFSET_MOD8                 0
+#define PARSER_RESULTS_TPID_VLAN_1_F_OFFSET_MOD16                0
+#define PARSER_RESULTS_VID_FILTER_MATCH_F_OFFSET                 12
+#define PARSER_RESULTS_VID_FILTER_MATCH_F_WIDTH                  4
+#define PARSER_RESULTS_VID_FILTER_MATCH_OFFSET                   26
+#define PARSER_RESULTS_VID_FILTER_MATCH_WORD_OFFSET              6
+#define PARSER_RESULTS_VID_FILTER_MATCH_F_OFFSET_MOD8            4
+#define PARSER_RESULTS_VID_FILTER_MATCH_F_OFFSET_MOD16           12
+#define PARSER_RESULTS_DOS_ATTACK_REASON_F_OFFSET                8
+#define PARSER_RESULTS_DOS_ATTACK_REASON_F_WIDTH                 4
+#define PARSER_RESULTS_DOS_ATTACK_REASON_OFFSET                  26
+#define PARSER_RESULTS_DOS_ATTACK_REASON_WORD_OFFSET             6
+#define PARSER_RESULTS_DOS_ATTACK_REASON_F_OFFSET_MOD8           0
+#define PARSER_RESULTS_DOS_ATTACK_REASON_F_OFFSET_MOD16          8
+#define PARSER_RESULTS_LAYER2_ADDRESS_F_OFFSET                   0
+#define PARSER_RESULTS_LAYER2_ADDRESS_F_WIDTH                    8
+#define PARSER_RESULTS_LAYER2_ADDRESS_OFFSET                     27
+#define PARSER_RESULTS_LAYER2_ADDRESS_WORD_OFFSET                6
+#define PARSER_RESULTS_LAYER2_ADDRESS_F_OFFSET_MOD16             0
+
+/* >>>RDD_PARSER_RESULTS_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	l4_protocol      	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /*defined by rdd_parser_l4_protocol enumeration*/
+	uint32_t	v6_ah            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	v6_dest_opt      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	v6_route         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	v6_hop           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	tcp_flags        	;
+	uint8_t	layer3_offset    	;
+	uint8_t	layer4_offset    	;
+	uint16_t	outer_vlan       	;
+	uint16_t	mac_da1_2        	;
+	uint32_t	mac_da3_6        	;
+	uint16_t	inner_vlan       	;
+	uint16_t	mac_sa1_2        	;
+	uint32_t	mac_sa3_6        	;
+	uint8_t	icmpv6_type      	;
+	uint8_t	ip_ttl           	;
+	uint16_t	ip_length        	;
+	uint32_t	ip_filter_match  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_filter_num    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	p_tag            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vid_filter_hit   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	da_filter_number 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tag_type         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tpid_vlan_0      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tpid_vlan_1      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vid_filter_match 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dos_attack_reason	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	layer2_address   	;
+#else
+	uint8_t	layer4_offset    	;
+	uint8_t	layer3_offset    	;
+	uint8_t	tcp_flags        	;
+	uint32_t	v6_hop           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	v6_route         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	v6_dest_opt      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	v6_ah            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	l4_protocol      	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /*defined by rdd_parser_l4_protocol enumeration*/
+	uint16_t	mac_da1_2        	;
+	uint16_t	outer_vlan       	;
+	uint32_t	mac_da3_6        	;
+	uint16_t	mac_sa1_2        	;
+	uint16_t	inner_vlan       	;
+	uint32_t	mac_sa3_6        	;
+	uint16_t	ip_length        	;
+	uint8_t	ip_ttl           	;
+	uint8_t	icmpv6_type      	;
+	uint8_t	layer2_address   	;
+	uint32_t	dos_attack_reason	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vid_filter_match 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tpid_vlan_1      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tpid_vlan_0      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tag_type         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	da_filter_number 	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vid_filter_hit   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	p_tag            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_filter_num    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ip_filter_match  	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PARSER_RESULTS_DTS;
+
+typedef union
+{
+    uint32_t word_val[7];
+    uint64_t dword_val64[3];
+    RDD_PARSER_RESULTS_DTS fields;
+} PARSER_RESULTS_STRUCT;
+#define RDD_PARSER_RESULTS_L4_PROTOCOL_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS), 4, 4, r) /*defined by rdd_parser_l4_protocol enumeration*/
+#define RDD_PARSER_RESULTS_L4_PROTOCOL_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS), 4, 4, v) /*defined by rdd_parser_l4_protocol enumeration*/
+#define RDD_PARSER_RESULTS_L4_PROTOCOL_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p, 4, 4, r) /*defined by rdd_parser_l4_protocol enumeration*/
+#define RDD_PARSER_RESULTS_L4_PROTOCOL_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p, 4, 4, v) /*defined by rdd_parser_l4_protocol enumeration*/
+#define RDD_PARSER_RESULTS_V6_AH_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS), 3, 1, r)
+#define RDD_PARSER_RESULTS_V6_AH_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS), 3, 1, v)
+#define RDD_PARSER_RESULTS_V6_AH_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p, 3, 1, r)
+#define RDD_PARSER_RESULTS_V6_AH_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p, 3, 1, v)
+#define RDD_PARSER_RESULTS_V6_DEST_OPT_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS), 2, 1, r)
+#define RDD_PARSER_RESULTS_V6_DEST_OPT_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS), 2, 1, v)
+#define RDD_PARSER_RESULTS_V6_DEST_OPT_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p, 2, 1, r)
+#define RDD_PARSER_RESULTS_V6_DEST_OPT_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p, 2, 1, v)
+#define RDD_PARSER_RESULTS_V6_ROUTE_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS), 1, 1, r)
+#define RDD_PARSER_RESULTS_V6_ROUTE_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS), 1, 1, v)
+#define RDD_PARSER_RESULTS_V6_ROUTE_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p, 1, 1, r)
+#define RDD_PARSER_RESULTS_V6_ROUTE_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p, 1, 1, v)
+#define RDD_PARSER_RESULTS_V6_HOP_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS), 0, 1, r)
+#define RDD_PARSER_RESULTS_V6_HOP_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS), 0, 1, v)
+#define RDD_PARSER_RESULTS_V6_HOP_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p, 0, 1, r)
+#define RDD_PARSER_RESULTS_V6_HOP_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p, 0, 1, v)
+#define RDD_PARSER_RESULTS_TCP_FLAGS_READ_G(r, g, idx)                  GROUP_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 1, r)
+#define RDD_PARSER_RESULTS_TCP_FLAGS_WRITE_G(v, g, idx)                 GROUP_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 1, v)
+#define RDD_PARSER_RESULTS_TCP_FLAGS_READ(r, p)                         MREAD_8((uint8_t *)p + 1, r)
+#define RDD_PARSER_RESULTS_TCP_FLAGS_WRITE(v, p)                        MWRITE_8((uint8_t *)p + 1, v)
+#define RDD_PARSER_RESULTS_LAYER3_OFFSET_READ_G(r, g, idx)              GROUP_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 2, r)
+#define RDD_PARSER_RESULTS_LAYER3_OFFSET_WRITE_G(v, g, idx)             GROUP_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 2, v)
+#define RDD_PARSER_RESULTS_LAYER3_OFFSET_READ(r, p)                     MREAD_8((uint8_t *)p + 2, r)
+#define RDD_PARSER_RESULTS_LAYER3_OFFSET_WRITE(v, p)                    MWRITE_8((uint8_t *)p + 2, v)
+#define RDD_PARSER_RESULTS_LAYER4_OFFSET_READ_G(r, g, idx)              GROUP_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 3, r)
+#define RDD_PARSER_RESULTS_LAYER4_OFFSET_WRITE_G(v, g, idx)             GROUP_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 3, v)
+#define RDD_PARSER_RESULTS_LAYER4_OFFSET_READ(r, p)                     MREAD_8((uint8_t *)p + 3, r)
+#define RDD_PARSER_RESULTS_LAYER4_OFFSET_WRITE(v, p)                    MWRITE_8((uint8_t *)p + 3, v)
+#define RDD_PARSER_RESULTS_OUTER_VLAN_READ_G(r, g, idx)                 GROUP_MREAD_16(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 4, r)
+#define RDD_PARSER_RESULTS_OUTER_VLAN_WRITE_G(v, g, idx)                GROUP_MWRITE_16(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 4, v)
+#define RDD_PARSER_RESULTS_OUTER_VLAN_READ(r, p)                        MREAD_16((uint8_t *)p + 4, r)
+#define RDD_PARSER_RESULTS_OUTER_VLAN_WRITE(v, p)                       MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_PARSER_RESULTS_MAC_DA1_2_READ_G(r, g, idx)                  GROUP_MREAD_16(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 6, r)
+#define RDD_PARSER_RESULTS_MAC_DA1_2_WRITE_G(v, g, idx)                 GROUP_MWRITE_16(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 6, v)
+#define RDD_PARSER_RESULTS_MAC_DA1_2_READ(r, p)                         MREAD_16((uint8_t *)p + 6, r)
+#define RDD_PARSER_RESULTS_MAC_DA1_2_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_PARSER_RESULTS_MAC_DA3_6_READ_G(r, g, idx)                  GROUP_MREAD_32(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 8, r)
+#define RDD_PARSER_RESULTS_MAC_DA3_6_WRITE_G(v, g, idx)                 GROUP_MWRITE_32(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 8, v)
+#define RDD_PARSER_RESULTS_MAC_DA3_6_READ(r, p)                         MREAD_32((uint8_t *)p + 8, r)
+#define RDD_PARSER_RESULTS_MAC_DA3_6_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_PARSER_RESULTS_INNER_VLAN_READ_G(r, g, idx)                 GROUP_MREAD_16(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 12, r)
+#define RDD_PARSER_RESULTS_INNER_VLAN_WRITE_G(v, g, idx)                GROUP_MWRITE_16(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 12, v)
+#define RDD_PARSER_RESULTS_INNER_VLAN_READ(r, p)                        MREAD_16((uint8_t *)p + 12, r)
+#define RDD_PARSER_RESULTS_INNER_VLAN_WRITE(v, p)                       MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_PARSER_RESULTS_MAC_SA1_2_READ_G(r, g, idx)                  GROUP_MREAD_16(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 14, r)
+#define RDD_PARSER_RESULTS_MAC_SA1_2_WRITE_G(v, g, idx)                 GROUP_MWRITE_16(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 14, v)
+#define RDD_PARSER_RESULTS_MAC_SA1_2_READ(r, p)                         MREAD_16((uint8_t *)p + 14, r)
+#define RDD_PARSER_RESULTS_MAC_SA1_2_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_PARSER_RESULTS_MAC_SA3_6_READ_G(r, g, idx)                  GROUP_MREAD_32(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 16, r)
+#define RDD_PARSER_RESULTS_MAC_SA3_6_WRITE_G(v, g, idx)                 GROUP_MWRITE_32(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 16, v)
+#define RDD_PARSER_RESULTS_MAC_SA3_6_READ(r, p)                         MREAD_32((uint8_t *)p + 16, r)
+#define RDD_PARSER_RESULTS_MAC_SA3_6_WRITE(v, p)                        MWRITE_32((uint8_t *)p + 16, v)
+#define RDD_PARSER_RESULTS_ICMPV6_TYPE_READ_G(r, g, idx)                GROUP_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 20, r)
+#define RDD_PARSER_RESULTS_ICMPV6_TYPE_WRITE_G(v, g, idx)               GROUP_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 20, v)
+#define RDD_PARSER_RESULTS_ICMPV6_TYPE_READ(r, p)                       MREAD_8((uint8_t *)p + 20, r)
+#define RDD_PARSER_RESULTS_ICMPV6_TYPE_WRITE(v, p)                      MWRITE_8((uint8_t *)p + 20, v)
+#define RDD_PARSER_RESULTS_IP_TTL_READ_G(r, g, idx)                     GROUP_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 21, r)
+#define RDD_PARSER_RESULTS_IP_TTL_WRITE_G(v, g, idx)                    GROUP_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 21, v)
+#define RDD_PARSER_RESULTS_IP_TTL_READ(r, p)                            MREAD_8((uint8_t *)p + 21, r)
+#define RDD_PARSER_RESULTS_IP_TTL_WRITE(v, p)                           MWRITE_8((uint8_t *)p + 21, v)
+#define RDD_PARSER_RESULTS_IP_LENGTH_READ_G(r, g, idx)                  GROUP_MREAD_16(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 22, r)
+#define RDD_PARSER_RESULTS_IP_LENGTH_WRITE_G(v, g, idx)                 GROUP_MWRITE_16(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 22, v)
+#define RDD_PARSER_RESULTS_IP_LENGTH_READ(r, p)                         MREAD_16((uint8_t *)p + 22, r)
+#define RDD_PARSER_RESULTS_IP_LENGTH_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 22, v)
+#define RDD_PARSER_RESULTS_IP_FILTER_MATCH_READ_G(r, g, idx)            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 24, 7, 1, r)
+#define RDD_PARSER_RESULTS_IP_FILTER_MATCH_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 24, 7, 1, v)
+#define RDD_PARSER_RESULTS_IP_FILTER_MATCH_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 24, 7, 1, r)
+#define RDD_PARSER_RESULTS_IP_FILTER_MATCH_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 24, 7, 1, v)
+#define RDD_PARSER_RESULTS_IP_FILTER_NUM_READ_G(r, g, idx)              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 24, 6, 1, r)
+#define RDD_PARSER_RESULTS_IP_FILTER_NUM_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 24, 6, 1, v)
+#define RDD_PARSER_RESULTS_IP_FILTER_NUM_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 24, 6, 1, r)
+#define RDD_PARSER_RESULTS_IP_FILTER_NUM_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 24, 6, 1, v)
+#define RDD_PARSER_RESULTS_P_TAG_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 24, 5, 1, r)
+#define RDD_PARSER_RESULTS_P_TAG_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 24, 5, 1, v)
+#define RDD_PARSER_RESULTS_P_TAG_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 24, 5, 1, r)
+#define RDD_PARSER_RESULTS_P_TAG_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 24, 5, 1, v)
+#define RDD_PARSER_RESULTS_VID_FILTER_HIT_READ_G(r, g, idx)             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 24, 4, 1, r)
+#define RDD_PARSER_RESULTS_VID_FILTER_HIT_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 24, 4, 1, v)
+#define RDD_PARSER_RESULTS_VID_FILTER_HIT_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 24, 4, 1, r)
+#define RDD_PARSER_RESULTS_VID_FILTER_HIT_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 24, 4, 1, v)
+#define RDD_PARSER_RESULTS_DA_FILTER_NUMBER_READ_G(r, g, idx)           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 24, 0, 4, r)
+#define RDD_PARSER_RESULTS_DA_FILTER_NUMBER_WRITE_G(v, g, idx)          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 24, 0, 4, v)
+#define RDD_PARSER_RESULTS_DA_FILTER_NUMBER_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 24, 0, 4, r)
+#define RDD_PARSER_RESULTS_DA_FILTER_NUMBER_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 24, 0, 4, v)
+#define RDD_PARSER_RESULTS_TAG_TYPE_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 25, 6, 2, r)
+#define RDD_PARSER_RESULTS_TAG_TYPE_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 25, 6, 2, v)
+#define RDD_PARSER_RESULTS_TAG_TYPE_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 25, 6, 2, r)
+#define RDD_PARSER_RESULTS_TAG_TYPE_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 25, 6, 2, v)
+#define RDD_PARSER_RESULTS_TPID_VLAN_0_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 25, 3, 3, r)
+#define RDD_PARSER_RESULTS_TPID_VLAN_0_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 25, 3, 3, v)
+#define RDD_PARSER_RESULTS_TPID_VLAN_0_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 25, 3, 3, r)
+#define RDD_PARSER_RESULTS_TPID_VLAN_0_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 25, 3, 3, v)
+#define RDD_PARSER_RESULTS_TPID_VLAN_1_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 25, 0, 3, r)
+#define RDD_PARSER_RESULTS_TPID_VLAN_1_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 25, 0, 3, v)
+#define RDD_PARSER_RESULTS_TPID_VLAN_1_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 25, 0, 3, r)
+#define RDD_PARSER_RESULTS_TPID_VLAN_1_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 25, 0, 3, v)
+#define RDD_PARSER_RESULTS_VID_FILTER_MATCH_READ_G(r, g, idx)           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 26, 4, 4, r)
+#define RDD_PARSER_RESULTS_VID_FILTER_MATCH_WRITE_G(v, g, idx)          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 26, 4, 4, v)
+#define RDD_PARSER_RESULTS_VID_FILTER_MATCH_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 26, 4, 4, r)
+#define RDD_PARSER_RESULTS_VID_FILTER_MATCH_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 26, 4, 4, v)
+#define RDD_PARSER_RESULTS_DOS_ATTACK_REASON_READ_G(r, g, idx)          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 26, 0, 4, r)
+#define RDD_PARSER_RESULTS_DOS_ATTACK_REASON_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 26, 0, 4, v)
+#define RDD_PARSER_RESULTS_DOS_ATTACK_REASON_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 26, 0, 4, r)
+#define RDD_PARSER_RESULTS_DOS_ATTACK_REASON_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 26, 0, 4, v)
+#define RDD_PARSER_RESULTS_LAYER2_ADDRESS_READ_G(r, g, idx)             GROUP_MREAD_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 27, r)
+#define RDD_PARSER_RESULTS_LAYER2_ADDRESS_WRITE_G(v, g, idx)            GROUP_MWRITE_8(g, idx*sizeof(RDD_PARSER_RESULTS_DTS) + 27, v)
+#define RDD_PARSER_RESULTS_LAYER2_ADDRESS_READ(r, p)                    MREAD_8((uint8_t *)p + 27, r)
+#define RDD_PARSER_RESULTS_LAYER2_ADDRESS_WRITE(v, p)                   MWRITE_8((uint8_t *)p + 27, v)
+/* <<<RDD_PARSER_RESULTS_DTS */
+
+/* <<<RDD_PARSER_RESULTS */
+
+
+/* >>>RDD_PARSER_L2_LKP_ENTRY */
+#define PARSER_L2_LKP_ENTRY_DA_CRC_F_OFFSET                           0
+#define PARSER_L2_LKP_ENTRY_DA_CRC_F_WIDTH                            32
+#define PARSER_L2_LKP_ENTRY_PARSER_L2_LKP_ENTRY_OFFSET                0
+#define PARSER_L2_LKP_ENTRY_DA_CRC_OFFSET                             0
+#define PARSER_L2_LKP_ENTRY_DA_CRC_WORD_OFFSET                        0
+#define PARSER_L2_LKP_ENTRY_SA_CRC_F_OFFSET                           0
+#define PARSER_L2_LKP_ENTRY_SA_CRC_F_WIDTH                            32
+#define PARSER_L2_LKP_ENTRY_SA_CRC_OFFSET                             4
+#define PARSER_L2_LKP_ENTRY_SA_CRC_WORD_OFFSET                        1
+#define PARSER_L2_LKP_ENTRY_VLAN_ETH_TYPE_CRC_F_OFFSET                0
+#define PARSER_L2_LKP_ENTRY_VLAN_ETH_TYPE_CRC_F_WIDTH                 32
+#define PARSER_L2_LKP_ENTRY_VLAN_ETH_TYPE_CRC_OFFSET                  8
+#define PARSER_L2_LKP_ENTRY_VLAN_ETH_TYPE_CRC_WORD_OFFSET             2
+#define PARSER_L2_LKP_ENTRY_TOS_F_OFFSET                              24
+#define PARSER_L2_LKP_ENTRY_TOS_F_WIDTH                               8
+#define PARSER_L2_LKP_ENTRY_TOS_OFFSET                                12
+#define PARSER_L2_LKP_ENTRY_TOS_WORD_OFFSET                           3
+#define PARSER_L2_LKP_ENTRY_TOS_F_OFFSET_MOD16                        8
+#define PARSER_L2_LKP_ENTRY_LOOKUP_PORT_F_OFFSET                      19
+#define PARSER_L2_LKP_ENTRY_LOOKUP_PORT_F_WIDTH                       5
+#define PARSER_L2_LKP_ENTRY_LOOKUP_PORT_OFFSET                        13
+#define PARSER_L2_LKP_ENTRY_LOOKUP_PORT_WORD_OFFSET                   3
+#define PARSER_L2_LKP_ENTRY_LOOKUP_PORT_F_OFFSET_MOD8                 3
+#define PARSER_L2_LKP_ENTRY_LOOKUP_PORT_F_OFFSET_MOD16                3
+#define PARSER_L2_LKP_ENTRY_VLANS_NUM_F_OFFSET                        16
+#define PARSER_L2_LKP_ENTRY_VLANS_NUM_F_WIDTH                         3
+#define PARSER_L2_LKP_ENTRY_VLANS_NUM_OFFSET                          13
+#define PARSER_L2_LKP_ENTRY_VLANS_NUM_WORD_OFFSET                     3
+#define PARSER_L2_LKP_ENTRY_VLANS_NUM_F_OFFSET_MOD8                   0
+#define PARSER_L2_LKP_ENTRY_VLANS_NUM_F_OFFSET_MOD16                  0
+#define PARSER_L2_LKP_ENTRY_VALID_F_OFFSET                            15
+#define PARSER_L2_LKP_ENTRY_VALID_F_WIDTH                             1
+#define PARSER_L2_LKP_ENTRY_VALID_OFFSET                              14
+#define PARSER_L2_LKP_ENTRY_VALID_WORD_OFFSET                         3
+#define PARSER_L2_LKP_ENTRY_VALID_F_OFFSET_MOD8                       7
+#define PARSER_L2_LKP_ENTRY_VALID_F_OFFSET_MOD16                      15
+#define PARSER_L2_LKP_ENTRY_TCP_PURE_ACK_F_OFFSET                     14
+#define PARSER_L2_LKP_ENTRY_TCP_PURE_ACK_F_WIDTH                      1
+#define PARSER_L2_LKP_ENTRY_TCP_PURE_ACK_OFFSET                       14
+#define PARSER_L2_LKP_ENTRY_TCP_PURE_ACK_WORD_OFFSET                  3
+#define PARSER_L2_LKP_ENTRY_TCP_PURE_ACK_F_OFFSET_MOD8                6
+#define PARSER_L2_LKP_ENTRY_TCP_PURE_ACK_F_OFFSET_MOD16               14
+#define PARSER_L2_LKP_ENTRY_VAR_LEN_CTX_F_OFFSET                      0
+#define PARSER_L2_LKP_ENTRY_VAR_LEN_CTX_F_WIDTH                       4
+#define PARSER_L2_LKP_ENTRY_VAR_LEN_CTX_OFFSET                        15
+#define PARSER_L2_LKP_ENTRY_VAR_LEN_CTX_WORD_OFFSET                   3
+#define PARSER_L2_LKP_ENTRY_VAR_LEN_CTX_F_OFFSET_MOD8                 0
+#define PARSER_L2_LKP_ENTRY_VAR_LEN_CTX_F_OFFSET_MOD16                0
+
+/* >>>RDD_PARSER_L2_LKP_ENTRY_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	da_crc           	;
+	uint32_t	sa_crc           	;
+	uint32_t	vlan_eth_type_crc	;
+	uint8_t	tos              	;
+	uint32_t	lookup_port      	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vlans_num        	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_pure_ack     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	var_len_ctx      	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#else
+	uint32_t	da_crc           	;
+	uint32_t	sa_crc           	;
+	uint32_t	vlan_eth_type_crc	;
+	uint32_t	var_len_ctx      	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1        	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_pure_ack     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vlans_num        	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	lookup_port      	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	tos              	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PARSER_L2_LKP_ENTRY_DTS;
+
+typedef union
+{
+    uint32_t word_val[4];
+    uint64_t dword_val64[2];
+    RDD_PARSER_L2_LKP_ENTRY_DTS fields;
+} PARSER_L2_LKP_ENTRY_STRUCT;
+#define RDD_PARSER_L2_LKP_ENTRY_DA_CRC_READ_G(r, g, idx)                     GROUP_MREAD_32(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS), r)
+#define RDD_PARSER_L2_LKP_ENTRY_DA_CRC_WRITE_G(v, g, idx)                    GROUP_MWRITE_32(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS), v)
+#define RDD_PARSER_L2_LKP_ENTRY_DA_CRC_READ(r, p)                            MREAD_32((uint8_t *)p, r)
+#define RDD_PARSER_L2_LKP_ENTRY_DA_CRC_WRITE(v, p)                           MWRITE_32((uint8_t *)p, v)
+#define RDD_PARSER_L2_LKP_ENTRY_SA_CRC_READ_G(r, g, idx)                     GROUP_MREAD_32(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 4, r)
+#define RDD_PARSER_L2_LKP_ENTRY_SA_CRC_WRITE_G(v, g, idx)                    GROUP_MWRITE_32(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 4, v)
+#define RDD_PARSER_L2_LKP_ENTRY_SA_CRC_READ(r, p)                            MREAD_32((uint8_t *)p + 4, r)
+#define RDD_PARSER_L2_LKP_ENTRY_SA_CRC_WRITE(v, p)                           MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_PARSER_L2_LKP_ENTRY_VLAN_ETH_TYPE_CRC_READ_G(r, g, idx)          GROUP_MREAD_32(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 8, r)
+#define RDD_PARSER_L2_LKP_ENTRY_VLAN_ETH_TYPE_CRC_WRITE_G(v, g, idx)         GROUP_MWRITE_32(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 8, v)
+#define RDD_PARSER_L2_LKP_ENTRY_VLAN_ETH_TYPE_CRC_READ(r, p)                 MREAD_32((uint8_t *)p + 8, r)
+#define RDD_PARSER_L2_LKP_ENTRY_VLAN_ETH_TYPE_CRC_WRITE(v, p)                MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_PARSER_L2_LKP_ENTRY_TOS_READ_G(r, g, idx)                        GROUP_MREAD_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 12, r)
+#define RDD_PARSER_L2_LKP_ENTRY_TOS_WRITE_G(v, g, idx)                       GROUP_MWRITE_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 12, v)
+#define RDD_PARSER_L2_LKP_ENTRY_TOS_READ(r, p)                               MREAD_8((uint8_t *)p + 12, r)
+#define RDD_PARSER_L2_LKP_ENTRY_TOS_WRITE(v, p)                              MWRITE_8((uint8_t *)p + 12, v)
+#define RDD_PARSER_L2_LKP_ENTRY_LOOKUP_PORT_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 13, 3, 5, r)
+#define RDD_PARSER_L2_LKP_ENTRY_LOOKUP_PORT_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 13, 3, 5, v)
+#define RDD_PARSER_L2_LKP_ENTRY_LOOKUP_PORT_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 13, 3, 5, r)
+#define RDD_PARSER_L2_LKP_ENTRY_LOOKUP_PORT_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 13, 3, 5, v)
+#define RDD_PARSER_L2_LKP_ENTRY_VLANS_NUM_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 13, 0, 3, r)
+#define RDD_PARSER_L2_LKP_ENTRY_VLANS_NUM_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 13, 0, 3, v)
+#define RDD_PARSER_L2_LKP_ENTRY_VLANS_NUM_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 13, 0, 3, r)
+#define RDD_PARSER_L2_LKP_ENTRY_VLANS_NUM_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 13, 0, 3, v)
+#define RDD_PARSER_L2_LKP_ENTRY_VALID_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 14, 7, 1, r)
+#define RDD_PARSER_L2_LKP_ENTRY_VALID_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 14, 7, 1, v)
+#define RDD_PARSER_L2_LKP_ENTRY_VALID_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 14, 7, 1, r)
+#define RDD_PARSER_L2_LKP_ENTRY_VALID_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 14, 7, 1, v)
+#define RDD_PARSER_L2_LKP_ENTRY_TCP_PURE_ACK_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 14, 6, 1, r)
+#define RDD_PARSER_L2_LKP_ENTRY_TCP_PURE_ACK_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 14, 6, 1, v)
+#define RDD_PARSER_L2_LKP_ENTRY_TCP_PURE_ACK_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 14, 6, 1, r)
+#define RDD_PARSER_L2_LKP_ENTRY_TCP_PURE_ACK_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 14, 6, 1, v)
+#define RDD_PARSER_L2_LKP_ENTRY_VAR_LEN_CTX_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 15, 0, 4, r)
+#define RDD_PARSER_L2_LKP_ENTRY_VAR_LEN_CTX_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L2_LKP_ENTRY_DTS) + 15, 0, 4, v)
+#define RDD_PARSER_L2_LKP_ENTRY_VAR_LEN_CTX_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 15, 0, 4, r)
+#define RDD_PARSER_L2_LKP_ENTRY_VAR_LEN_CTX_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 15, 0, 4, v)
+/* <<<RDD_PARSER_L2_LKP_ENTRY_DTS */
+
+/* <<<RDD_PARSER_L2_LKP_ENTRY */
+
+
+/* >>>RDD_PARSER_L3_LKP_ENTRY */
+#define PARSER_L3_LKP_ENTRY_SOURCE_IP_F_OFFSET                        0
+#define PARSER_L3_LKP_ENTRY_SOURCE_IP_F_WIDTH                         32
+#define PARSER_L3_LKP_ENTRY_PARSER_L3_LKP_ENTRY_OFFSET                0
+#define PARSER_L3_LKP_ENTRY_SOURCE_IP_OFFSET                          0
+#define PARSER_L3_LKP_ENTRY_SOURCE_IP_WORD_OFFSET                     0
+#define PARSER_L3_LKP_ENTRY_DESTINATION_IP_F_OFFSET                   0
+#define PARSER_L3_LKP_ENTRY_DESTINATION_IP_F_WIDTH                    32
+#define PARSER_L3_LKP_ENTRY_DESTINATION_IP_OFFSET                     4
+#define PARSER_L3_LKP_ENTRY_DESTINATION_IP_WORD_OFFSET                1
+#define PARSER_L3_LKP_ENTRY_SOURCE_PORT_F_OFFSET                      16
+#define PARSER_L3_LKP_ENTRY_SOURCE_PORT_F_WIDTH                       16
+#define PARSER_L3_LKP_ENTRY_SOURCE_PORT_OFFSET                        8
+#define PARSER_L3_LKP_ENTRY_SOURCE_PORT_WORD_OFFSET                   2
+#define PARSER_L3_LKP_ENTRY_DESTINATION_PORT_F_OFFSET                 0
+#define PARSER_L3_LKP_ENTRY_DESTINATION_PORT_F_WIDTH                  16
+#define PARSER_L3_LKP_ENTRY_DESTINATION_PORT_OFFSET                   10
+#define PARSER_L3_LKP_ENTRY_DESTINATION_PORT_WORD_OFFSET              2
+#define PARSER_L3_LKP_ENTRY_TOS_F_OFFSET                              24
+#define PARSER_L3_LKP_ENTRY_TOS_F_WIDTH                               8
+#define PARSER_L3_LKP_ENTRY_TOS_OFFSET                                12
+#define PARSER_L3_LKP_ENTRY_TOS_WORD_OFFSET                           3
+#define PARSER_L3_LKP_ENTRY_TOS_F_OFFSET_MOD16                        8
+#define PARSER_L3_LKP_ENTRY_LOOKUP_PORT_F_OFFSET                      19
+#define PARSER_L3_LKP_ENTRY_LOOKUP_PORT_F_WIDTH                       5
+#define PARSER_L3_LKP_ENTRY_LOOKUP_PORT_OFFSET                        13
+#define PARSER_L3_LKP_ENTRY_LOOKUP_PORT_WORD_OFFSET                   3
+#define PARSER_L3_LKP_ENTRY_LOOKUP_PORT_F_OFFSET_MOD8                 3
+#define PARSER_L3_LKP_ENTRY_LOOKUP_PORT_F_OFFSET_MOD16                3
+#define PARSER_L3_LKP_ENTRY_VLANS_NUM_F_OFFSET                        16
+#define PARSER_L3_LKP_ENTRY_VLANS_NUM_F_WIDTH                         3
+#define PARSER_L3_LKP_ENTRY_VLANS_NUM_OFFSET                          13
+#define PARSER_L3_LKP_ENTRY_VLANS_NUM_WORD_OFFSET                     3
+#define PARSER_L3_LKP_ENTRY_VLANS_NUM_F_OFFSET_MOD8                   0
+#define PARSER_L3_LKP_ENTRY_VLANS_NUM_F_OFFSET_MOD16                  0
+#define PARSER_L3_LKP_ENTRY_VALID_F_OFFSET                            15
+#define PARSER_L3_LKP_ENTRY_VALID_F_WIDTH                             1
+#define PARSER_L3_LKP_ENTRY_VALID_OFFSET                              14
+#define PARSER_L3_LKP_ENTRY_VALID_WORD_OFFSET                         3
+#define PARSER_L3_LKP_ENTRY_VALID_F_OFFSET_MOD8                       7
+#define PARSER_L3_LKP_ENTRY_VALID_F_OFFSET_MOD16                      15
+#define PARSER_L3_LKP_ENTRY_TCP_PURE_ACK_F_OFFSET                     14
+#define PARSER_L3_LKP_ENTRY_TCP_PURE_ACK_F_WIDTH                      1
+#define PARSER_L3_LKP_ENTRY_TCP_PURE_ACK_OFFSET                       14
+#define PARSER_L3_LKP_ENTRY_TCP_PURE_ACK_WORD_OFFSET                  3
+#define PARSER_L3_LKP_ENTRY_TCP_PURE_ACK_F_OFFSET_MOD8                6
+#define PARSER_L3_LKP_ENTRY_TCP_PURE_ACK_F_OFFSET_MOD16               14
+#define PARSER_L3_LKP_ENTRY_IPV6_F_OFFSET                             13
+#define PARSER_L3_LKP_ENTRY_IPV6_F_WIDTH                              1
+#define PARSER_L3_LKP_ENTRY_IPV6_OFFSET                               14
+#define PARSER_L3_LKP_ENTRY_IPV6_WORD_OFFSET                          3
+#define PARSER_L3_LKP_ENTRY_IPV6_F_OFFSET_MOD8                        5
+#define PARSER_L3_LKP_ENTRY_IPV6_F_OFFSET_MOD16                       13
+#define PARSER_L3_LKP_ENTRY_CTX_EXT_F_OFFSET                          12
+#define PARSER_L3_LKP_ENTRY_CTX_EXT_F_WIDTH                           1
+#define PARSER_L3_LKP_ENTRY_CTX_EXT_OFFSET                            14
+#define PARSER_L3_LKP_ENTRY_CTX_EXT_WORD_OFFSET                       3
+#define PARSER_L3_LKP_ENTRY_CTX_EXT_F_OFFSET_MOD8                     4
+#define PARSER_L3_LKP_ENTRY_CTX_EXT_F_OFFSET_MOD16                    12
+#define PARSER_L3_LKP_ENTRY_PROTOCOL_F_OFFSET                         4
+#define PARSER_L3_LKP_ENTRY_PROTOCOL_F_WIDTH                          8
+#define PARSER_L3_LKP_ENTRY_PROTOCOL_OFFSET                           14
+#define PARSER_L3_LKP_ENTRY_PROTOCOL_WORD_OFFSET                      3
+#define PARSER_L3_LKP_ENTRY_PROTOCOL_F_OFFSET_MOD16                   4
+#define PARSER_L3_LKP_ENTRY_VAR_LEN_CTX_F_OFFSET                      0
+#define PARSER_L3_LKP_ENTRY_VAR_LEN_CTX_F_WIDTH                       4
+#define PARSER_L3_LKP_ENTRY_VAR_LEN_CTX_OFFSET                        15
+#define PARSER_L3_LKP_ENTRY_VAR_LEN_CTX_WORD_OFFSET                   3
+#define PARSER_L3_LKP_ENTRY_VAR_LEN_CTX_F_OFFSET_MOD8                 0
+#define PARSER_L3_LKP_ENTRY_VAR_LEN_CTX_F_OFFSET_MOD16                0
+
+/* >>>RDD_PARSER_L3_LKP_ENTRY_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	source_ip       	;
+	uint32_t	destination_ip  	;
+	uint16_t	source_port     	;
+	uint16_t	destination_port	;
+	uint8_t	tos             	;
+	uint32_t	lookup_port     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vlans_num       	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_pure_ack    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipv6            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ctx_ext         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	protocol        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /*defined by rdd_parser_l3_protocol enumeration*/
+	uint32_t	var_len_ctx     	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#else
+	uint32_t	source_ip       	;
+	uint32_t	destination_ip  	;
+	uint16_t	destination_port	;
+	uint16_t	source_port     	;
+	uint32_t	var_len_ctx     	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	protocol        	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /*defined by rdd_parser_l3_protocol enumeration*/
+	uint32_t	ctx_ext         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipv6            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tcp_pure_ack    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	valid           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vlans_num       	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	lookup_port     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	tos             	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PARSER_L3_LKP_ENTRY_DTS;
+
+typedef union
+{
+    uint32_t word_val[4];
+    uint64_t dword_val64[2];
+    RDD_PARSER_L3_LKP_ENTRY_DTS fields;
+} PARSER_L3_LKP_ENTRY_STRUCT;
+#define RDD_PARSER_L3_LKP_ENTRY_SOURCE_IP_READ_G(r, g, idx)                 GROUP_MREAD_32(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS), r)
+#define RDD_PARSER_L3_LKP_ENTRY_SOURCE_IP_WRITE_G(v, g, idx)                GROUP_MWRITE_32(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS), v)
+#define RDD_PARSER_L3_LKP_ENTRY_SOURCE_IP_READ(r, p)                        MREAD_32((uint8_t *)p, r)
+#define RDD_PARSER_L3_LKP_ENTRY_SOURCE_IP_WRITE(v, p)                       MWRITE_32((uint8_t *)p, v)
+#define RDD_PARSER_L3_LKP_ENTRY_DESTINATION_IP_READ_G(r, g, idx)            GROUP_MREAD_32(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 4, r)
+#define RDD_PARSER_L3_LKP_ENTRY_DESTINATION_IP_WRITE_G(v, g, idx)           GROUP_MWRITE_32(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 4, v)
+#define RDD_PARSER_L3_LKP_ENTRY_DESTINATION_IP_READ(r, p)                   MREAD_32((uint8_t *)p + 4, r)
+#define RDD_PARSER_L3_LKP_ENTRY_DESTINATION_IP_WRITE(v, p)                  MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_PARSER_L3_LKP_ENTRY_SOURCE_PORT_READ_G(r, g, idx)               GROUP_MREAD_16(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 8, r)
+#define RDD_PARSER_L3_LKP_ENTRY_SOURCE_PORT_WRITE_G(v, g, idx)              GROUP_MWRITE_16(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 8, v)
+#define RDD_PARSER_L3_LKP_ENTRY_SOURCE_PORT_READ(r, p)                      MREAD_16((uint8_t *)p + 8, r)
+#define RDD_PARSER_L3_LKP_ENTRY_SOURCE_PORT_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 8, v)
+#define RDD_PARSER_L3_LKP_ENTRY_DESTINATION_PORT_READ_G(r, g, idx)          GROUP_MREAD_16(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 10, r)
+#define RDD_PARSER_L3_LKP_ENTRY_DESTINATION_PORT_WRITE_G(v, g, idx)         GROUP_MWRITE_16(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 10, v)
+#define RDD_PARSER_L3_LKP_ENTRY_DESTINATION_PORT_READ(r, p)                 MREAD_16((uint8_t *)p + 10, r)
+#define RDD_PARSER_L3_LKP_ENTRY_DESTINATION_PORT_WRITE(v, p)                MWRITE_16((uint8_t *)p + 10, v)
+#define RDD_PARSER_L3_LKP_ENTRY_TOS_READ_G(r, g, idx)                       GROUP_MREAD_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 12, r)
+#define RDD_PARSER_L3_LKP_ENTRY_TOS_WRITE_G(v, g, idx)                      GROUP_MWRITE_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 12, v)
+#define RDD_PARSER_L3_LKP_ENTRY_TOS_READ(r, p)                              MREAD_8((uint8_t *)p + 12, r)
+#define RDD_PARSER_L3_LKP_ENTRY_TOS_WRITE(v, p)                             MWRITE_8((uint8_t *)p + 12, v)
+#define RDD_PARSER_L3_LKP_ENTRY_LOOKUP_PORT_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 13, 3, 5, r)
+#define RDD_PARSER_L3_LKP_ENTRY_LOOKUP_PORT_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 13, 3, 5, v)
+#define RDD_PARSER_L3_LKP_ENTRY_LOOKUP_PORT_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 13, 3, 5, r)
+#define RDD_PARSER_L3_LKP_ENTRY_LOOKUP_PORT_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 13, 3, 5, v)
+#define RDD_PARSER_L3_LKP_ENTRY_VLANS_NUM_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 13, 0, 3, r)
+#define RDD_PARSER_L3_LKP_ENTRY_VLANS_NUM_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 13, 0, 3, v)
+#define RDD_PARSER_L3_LKP_ENTRY_VLANS_NUM_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 13, 0, 3, r)
+#define RDD_PARSER_L3_LKP_ENTRY_VLANS_NUM_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 13, 0, 3, v)
+#define RDD_PARSER_L3_LKP_ENTRY_VALID_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 14, 7, 1, r)
+#define RDD_PARSER_L3_LKP_ENTRY_VALID_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 14, 7, 1, v)
+#define RDD_PARSER_L3_LKP_ENTRY_VALID_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 14, 7, 1, r)
+#define RDD_PARSER_L3_LKP_ENTRY_VALID_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 14, 7, 1, v)
+#define RDD_PARSER_L3_LKP_ENTRY_TCP_PURE_ACK_READ_G(r, g, idx)              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 14, 6, 1, r)
+#define RDD_PARSER_L3_LKP_ENTRY_TCP_PURE_ACK_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 14, 6, 1, v)
+#define RDD_PARSER_L3_LKP_ENTRY_TCP_PURE_ACK_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 14, 6, 1, r)
+#define RDD_PARSER_L3_LKP_ENTRY_TCP_PURE_ACK_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 14, 6, 1, v)
+#define RDD_PARSER_L3_LKP_ENTRY_IPV6_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 14, 5, 1, r)
+#define RDD_PARSER_L3_LKP_ENTRY_IPV6_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 14, 5, 1, v)
+#define RDD_PARSER_L3_LKP_ENTRY_IPV6_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 14, 5, 1, r)
+#define RDD_PARSER_L3_LKP_ENTRY_IPV6_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 14, 5, 1, v)
+#define RDD_PARSER_L3_LKP_ENTRY_CTX_EXT_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 14, 4, 1, r)
+#define RDD_PARSER_L3_LKP_ENTRY_CTX_EXT_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 14, 4, 1, v)
+#define RDD_PARSER_L3_LKP_ENTRY_CTX_EXT_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 14, 4, 1, r)
+#define RDD_PARSER_L3_LKP_ENTRY_CTX_EXT_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 14, 4, 1, v)
+#define RDD_PARSER_L3_LKP_ENTRY_PROTOCOL_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 14, 4, 8, r) /*defined by rdd_parser_l3_protocol enumeration*/
+#define RDD_PARSER_L3_LKP_ENTRY_PROTOCOL_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 14, 4, 8, v) /*defined by rdd_parser_l3_protocol enumeration*/
+#define RDD_PARSER_L3_LKP_ENTRY_PROTOCOL_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p + 14, 4, 8, r) /*defined by rdd_parser_l3_protocol enumeration*/
+#define RDD_PARSER_L3_LKP_ENTRY_PROTOCOL_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p + 14, 4, 8, v) /*defined by rdd_parser_l3_protocol enumeration*/
+#define RDD_PARSER_L3_LKP_ENTRY_VAR_LEN_CTX_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 15, 0, 4, r)
+#define RDD_PARSER_L3_LKP_ENTRY_VAR_LEN_CTX_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_L3_LKP_ENTRY_DTS) + 15, 0, 4, v)
+#define RDD_PARSER_L3_LKP_ENTRY_VAR_LEN_CTX_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 15, 0, 4, r)
+#define RDD_PARSER_L3_LKP_ENTRY_VAR_LEN_CTX_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 15, 0, 4, v)
+/* <<<RDD_PARSER_L3_LKP_ENTRY_DTS */
+
+/* <<<RDD_PARSER_L3_LKP_ENTRY */
+
+
+/* >>>RDD_PARSER_IC_LKP_ENTRY */
+#define PARSER_IC_LKP_ENTRY_DA_CRC_F_OFFSET                           0
+#define PARSER_IC_LKP_ENTRY_DA_CRC_F_WIDTH                            32
+#define PARSER_IC_LKP_ENTRY_PARSER_IC_LKP_ENTRY_OFFSET                0
+#define PARSER_IC_LKP_ENTRY_DA_CRC_OFFSET                             0
+#define PARSER_IC_LKP_ENTRY_DA_CRC_WORD_OFFSET                        0
+#define PARSER_IC_LKP_ENTRY_SA_CRC_F_OFFSET                           0
+#define PARSER_IC_LKP_ENTRY_SA_CRC_F_WIDTH                            32
+#define PARSER_IC_LKP_ENTRY_SA_CRC_OFFSET                             4
+#define PARSER_IC_LKP_ENTRY_SA_CRC_WORD_OFFSET                        1
+#define PARSER_IC_LKP_ENTRY_SOURCE_IP_F_OFFSET                        0
+#define PARSER_IC_LKP_ENTRY_SOURCE_IP_F_WIDTH                         32
+#define PARSER_IC_LKP_ENTRY_SOURCE_IP_OFFSET                          8
+#define PARSER_IC_LKP_ENTRY_SOURCE_IP_WORD_OFFSET                     2
+#define PARSER_IC_LKP_ENTRY_DESTINATION_IP_F_OFFSET                   0
+#define PARSER_IC_LKP_ENTRY_DESTINATION_IP_F_WIDTH                    32
+#define PARSER_IC_LKP_ENTRY_DESTINATION_IP_OFFSET                     12
+#define PARSER_IC_LKP_ENTRY_DESTINATION_IP_WORD_OFFSET                3
+#define PARSER_IC_LKP_ENTRY_SOURCE_PORT_F_OFFSET                      16
+#define PARSER_IC_LKP_ENTRY_SOURCE_PORT_F_WIDTH                       16
+#define PARSER_IC_LKP_ENTRY_SOURCE_PORT_OFFSET                        16
+#define PARSER_IC_LKP_ENTRY_SOURCE_PORT_WORD_OFFSET                   4
+#define PARSER_IC_LKP_ENTRY_DESTINATION_PORT_F_OFFSET                 0
+#define PARSER_IC_LKP_ENTRY_DESTINATION_PORT_F_WIDTH                  16
+#define PARSER_IC_LKP_ENTRY_DESTINATION_PORT_OFFSET                   18
+#define PARSER_IC_LKP_ENTRY_DESTINATION_PORT_WORD_OFFSET              4
+#define PARSER_IC_LKP_ENTRY_ETHERNET_TYPE_F_OFFSET                    16
+#define PARSER_IC_LKP_ENTRY_ETHERNET_TYPE_F_WIDTH                     16
+#define PARSER_IC_LKP_ENTRY_ETHERNET_TYPE_OFFSET                      20
+#define PARSER_IC_LKP_ENTRY_ETHERNET_TYPE_WORD_OFFSET                 5
+#define PARSER_IC_LKP_ENTRY_PROTOCOL_F_OFFSET                         8
+#define PARSER_IC_LKP_ENTRY_PROTOCOL_F_WIDTH                          8
+#define PARSER_IC_LKP_ENTRY_PROTOCOL_OFFSET                           22
+#define PARSER_IC_LKP_ENTRY_PROTOCOL_WORD_OFFSET                      5
+#define PARSER_IC_LKP_ENTRY_PROTOCOL_F_OFFSET_MOD16                   8
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_0_F_OFFSET                      5
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_0_F_WIDTH                       3
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_0_OFFSET                        23
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_0_WORD_OFFSET                   5
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_0_F_OFFSET_MOD8                 5
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_0_F_OFFSET_MOD16                5
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_1_F_OFFSET                      2
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_1_F_WIDTH                       3
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_1_OFFSET                        23
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_1_WORD_OFFSET                   5
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_1_F_OFFSET_MOD8                 2
+#define PARSER_IC_LKP_ENTRY_TPID_VLAN_1_F_OFFSET_MOD16                2
+#define PARSER_IC_LKP_ENTRY_IPV6_F_OFFSET                             1
+#define PARSER_IC_LKP_ENTRY_IPV6_F_WIDTH                              1
+#define PARSER_IC_LKP_ENTRY_IPV6_OFFSET                               23
+#define PARSER_IC_LKP_ENTRY_IPV6_WORD_OFFSET                          5
+#define PARSER_IC_LKP_ENTRY_IPV6_F_OFFSET_MOD8                        1
+#define PARSER_IC_LKP_ENTRY_IPV6_F_OFFSET_MOD16                       1
+#define PARSER_IC_LKP_ENTRY_IPV4_F_OFFSET                             0
+#define PARSER_IC_LKP_ENTRY_IPV4_F_WIDTH                              1
+#define PARSER_IC_LKP_ENTRY_IPV4_OFFSET                               23
+#define PARSER_IC_LKP_ENTRY_IPV4_WORD_OFFSET                          5
+#define PARSER_IC_LKP_ENTRY_IPV4_F_OFFSET_MOD8                        0
+#define PARSER_IC_LKP_ENTRY_IPV4_F_OFFSET_MOD16                       0
+#define PARSER_IC_LKP_ENTRY_OUTER_PBIT_F_OFFSET                       29
+#define PARSER_IC_LKP_ENTRY_OUTER_PBIT_F_WIDTH                        3
+#define PARSER_IC_LKP_ENTRY_OUTER_PBIT_OFFSET                         24
+#define PARSER_IC_LKP_ENTRY_OUTER_PBIT_WORD_OFFSET                    6
+#define PARSER_IC_LKP_ENTRY_OUTER_PBIT_F_OFFSET_MOD8                  5
+#define PARSER_IC_LKP_ENTRY_OUTER_PBIT_F_OFFSET_MOD16                 13
+#define PARSER_IC_LKP_ENTRY_OUTER_CFI_F_OFFSET                        28
+#define PARSER_IC_LKP_ENTRY_OUTER_CFI_F_WIDTH                         1
+#define PARSER_IC_LKP_ENTRY_OUTER_CFI_OFFSET                          24
+#define PARSER_IC_LKP_ENTRY_OUTER_CFI_WORD_OFFSET                     6
+#define PARSER_IC_LKP_ENTRY_OUTER_CFI_F_OFFSET_MOD8                   4
+#define PARSER_IC_LKP_ENTRY_OUTER_CFI_F_OFFSET_MOD16                  12
+#define PARSER_IC_LKP_ENTRY_OUTER_VID_F_OFFSET                        16
+#define PARSER_IC_LKP_ENTRY_OUTER_VID_F_WIDTH                         12
+#define PARSER_IC_LKP_ENTRY_OUTER_VID_OFFSET                          24
+#define PARSER_IC_LKP_ENTRY_OUTER_VID_WORD_OFFSET                     6
+#define PARSER_IC_LKP_ENTRY_OUTER_VID_F_OFFSET_MOD16                  0
+#define PARSER_IC_LKP_ENTRY_INNER_PBIT_F_OFFSET                       13
+#define PARSER_IC_LKP_ENTRY_INNER_PBIT_F_WIDTH                        3
+#define PARSER_IC_LKP_ENTRY_INNER_PBIT_OFFSET                         26
+#define PARSER_IC_LKP_ENTRY_INNER_PBIT_WORD_OFFSET                    6
+#define PARSER_IC_LKP_ENTRY_INNER_PBIT_F_OFFSET_MOD8                  5
+#define PARSER_IC_LKP_ENTRY_INNER_PBIT_F_OFFSET_MOD16                 13
+#define PARSER_IC_LKP_ENTRY_INNER_CFI_F_OFFSET                        12
+#define PARSER_IC_LKP_ENTRY_INNER_CFI_F_WIDTH                         1
+#define PARSER_IC_LKP_ENTRY_INNER_CFI_OFFSET                          26
+#define PARSER_IC_LKP_ENTRY_INNER_CFI_WORD_OFFSET                     6
+#define PARSER_IC_LKP_ENTRY_INNER_CFI_F_OFFSET_MOD8                   4
+#define PARSER_IC_LKP_ENTRY_INNER_CFI_F_OFFSET_MOD16                  12
+#define PARSER_IC_LKP_ENTRY_INNER_VID_F_OFFSET                        0
+#define PARSER_IC_LKP_ENTRY_INNER_VID_F_WIDTH                         12
+#define PARSER_IC_LKP_ENTRY_INNER_VID_OFFSET                          26
+#define PARSER_IC_LKP_ENTRY_INNER_VID_WORD_OFFSET                     6
+#define PARSER_IC_LKP_ENTRY_INNER_VID_F_OFFSET_MOD16                  0
+#define PARSER_IC_LKP_ENTRY_LOOKUP_PORT_F_OFFSET                      19
+#define PARSER_IC_LKP_ENTRY_LOOKUP_PORT_F_WIDTH                       5
+#define PARSER_IC_LKP_ENTRY_LOOKUP_PORT_OFFSET                        29
+#define PARSER_IC_LKP_ENTRY_LOOKUP_PORT_WORD_OFFSET                   7
+#define PARSER_IC_LKP_ENTRY_LOOKUP_PORT_F_OFFSET_MOD8                 3
+#define PARSER_IC_LKP_ENTRY_LOOKUP_PORT_F_OFFSET_MOD16                3
+#define PARSER_IC_LKP_ENTRY_VLANS_NUM_F_OFFSET                        16
+#define PARSER_IC_LKP_ENTRY_VLANS_NUM_F_WIDTH                         3
+#define PARSER_IC_LKP_ENTRY_VLANS_NUM_OFFSET                          29
+#define PARSER_IC_LKP_ENTRY_VLANS_NUM_WORD_OFFSET                     7
+#define PARSER_IC_LKP_ENTRY_VLANS_NUM_F_OFFSET_MOD8                   0
+#define PARSER_IC_LKP_ENTRY_VLANS_NUM_F_OFFSET_MOD16                  0
+#define PARSER_IC_LKP_ENTRY_TOS_F_OFFSET                              8
+#define PARSER_IC_LKP_ENTRY_TOS_F_WIDTH                               8
+#define PARSER_IC_LKP_ENTRY_TOS_OFFSET                                30
+#define PARSER_IC_LKP_ENTRY_TOS_WORD_OFFSET                           7
+#define PARSER_IC_LKP_ENTRY_TOS_F_OFFSET_MOD16                        8
+
+/* >>>RDD_PARSER_IC_LKP_ENTRY_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	da_crc          	;
+	uint32_t	sa_crc          	;
+	uint32_t	source_ip       	;
+	uint32_t	destination_ip  	;
+	uint16_t	source_port     	;
+	uint16_t	destination_port	;
+	uint16_t	ethernet_type   	;
+	uint8_t	protocol        	;
+	uint32_t	tpid_vlan_0     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tpid_vlan_1     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipv6            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipv4            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_pbit      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_cfi       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_vid       	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inner_pbit      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inner_cfi       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inner_vid       	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	reserved2       	;
+	uint32_t	lookup_port     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	vlans_num       	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	tos             	;
+	uint8_t	reserved3       	;
+#else
+	uint32_t	da_crc          	;
+	uint32_t	sa_crc          	;
+	uint32_t	source_ip       	;
+	uint32_t	destination_ip  	;
+	uint16_t	destination_port	;
+	uint16_t	source_port     	;
+	uint32_t	ipv4            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ipv6            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tpid_vlan_1     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	tpid_vlan_0     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	protocol        	;
+	uint16_t	ethernet_type   	;
+	uint32_t	inner_vid       	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inner_cfi       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	inner_pbit      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_vid       	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_cfi       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	outer_pbit      	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	reserved3       	;
+	uint8_t	tos             	;
+	uint32_t	vlans_num       	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	lookup_port     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	reserved2       	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PARSER_IC_LKP_ENTRY_DTS;
+
+typedef union
+{
+    uint32_t word_val[8];
+    uint64_t dword_val64[4];
+    RDD_PARSER_IC_LKP_ENTRY_DTS fields;
+} PARSER_IC_LKP_ENTRY_STRUCT;
+#define RDD_PARSER_IC_LKP_ENTRY_DA_CRC_READ_G(r, g, idx)                    GROUP_MREAD_32(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS), r)
+#define RDD_PARSER_IC_LKP_ENTRY_DA_CRC_WRITE_G(v, g, idx)                   GROUP_MWRITE_32(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS), v)
+#define RDD_PARSER_IC_LKP_ENTRY_DA_CRC_READ(r, p)                           MREAD_32((uint8_t *)p, r)
+#define RDD_PARSER_IC_LKP_ENTRY_DA_CRC_WRITE(v, p)                          MWRITE_32((uint8_t *)p, v)
+#define RDD_PARSER_IC_LKP_ENTRY_SA_CRC_READ_G(r, g, idx)                    GROUP_MREAD_32(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 4, r)
+#define RDD_PARSER_IC_LKP_ENTRY_SA_CRC_WRITE_G(v, g, idx)                   GROUP_MWRITE_32(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 4, v)
+#define RDD_PARSER_IC_LKP_ENTRY_SA_CRC_READ(r, p)                           MREAD_32((uint8_t *)p + 4, r)
+#define RDD_PARSER_IC_LKP_ENTRY_SA_CRC_WRITE(v, p)                          MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_PARSER_IC_LKP_ENTRY_SOURCE_IP_READ_G(r, g, idx)                 GROUP_MREAD_32(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 8, r)
+#define RDD_PARSER_IC_LKP_ENTRY_SOURCE_IP_WRITE_G(v, g, idx)                GROUP_MWRITE_32(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 8, v)
+#define RDD_PARSER_IC_LKP_ENTRY_SOURCE_IP_READ(r, p)                        MREAD_32((uint8_t *)p + 8, r)
+#define RDD_PARSER_IC_LKP_ENTRY_SOURCE_IP_WRITE(v, p)                       MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_PARSER_IC_LKP_ENTRY_DESTINATION_IP_READ_G(r, g, idx)            GROUP_MREAD_32(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 12, r)
+#define RDD_PARSER_IC_LKP_ENTRY_DESTINATION_IP_WRITE_G(v, g, idx)           GROUP_MWRITE_32(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 12, v)
+#define RDD_PARSER_IC_LKP_ENTRY_DESTINATION_IP_READ(r, p)                   MREAD_32((uint8_t *)p + 12, r)
+#define RDD_PARSER_IC_LKP_ENTRY_DESTINATION_IP_WRITE(v, p)                  MWRITE_32((uint8_t *)p + 12, v)
+#define RDD_PARSER_IC_LKP_ENTRY_SOURCE_PORT_READ_G(r, g, idx)               GROUP_MREAD_16(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 16, r)
+#define RDD_PARSER_IC_LKP_ENTRY_SOURCE_PORT_WRITE_G(v, g, idx)              GROUP_MWRITE_16(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 16, v)
+#define RDD_PARSER_IC_LKP_ENTRY_SOURCE_PORT_READ(r, p)                      MREAD_16((uint8_t *)p + 16, r)
+#define RDD_PARSER_IC_LKP_ENTRY_SOURCE_PORT_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 16, v)
+#define RDD_PARSER_IC_LKP_ENTRY_DESTINATION_PORT_READ_G(r, g, idx)          GROUP_MREAD_16(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 18, r)
+#define RDD_PARSER_IC_LKP_ENTRY_DESTINATION_PORT_WRITE_G(v, g, idx)         GROUP_MWRITE_16(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 18, v)
+#define RDD_PARSER_IC_LKP_ENTRY_DESTINATION_PORT_READ(r, p)                 MREAD_16((uint8_t *)p + 18, r)
+#define RDD_PARSER_IC_LKP_ENTRY_DESTINATION_PORT_WRITE(v, p)                MWRITE_16((uint8_t *)p + 18, v)
+#define RDD_PARSER_IC_LKP_ENTRY_ETHERNET_TYPE_READ_G(r, g, idx)             GROUP_MREAD_16(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 20, r)
+#define RDD_PARSER_IC_LKP_ENTRY_ETHERNET_TYPE_WRITE_G(v, g, idx)            GROUP_MWRITE_16(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 20, v)
+#define RDD_PARSER_IC_LKP_ENTRY_ETHERNET_TYPE_READ(r, p)                    MREAD_16((uint8_t *)p + 20, r)
+#define RDD_PARSER_IC_LKP_ENTRY_ETHERNET_TYPE_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 20, v)
+#define RDD_PARSER_IC_LKP_ENTRY_PROTOCOL_READ_G(r, g, idx)                  GROUP_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 22, r)
+#define RDD_PARSER_IC_LKP_ENTRY_PROTOCOL_WRITE_G(v, g, idx)                 GROUP_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 22, v)
+#define RDD_PARSER_IC_LKP_ENTRY_PROTOCOL_READ(r, p)                         MREAD_8((uint8_t *)p + 22, r)
+#define RDD_PARSER_IC_LKP_ENTRY_PROTOCOL_WRITE(v, p)                        MWRITE_8((uint8_t *)p + 22, v)
+#define RDD_PARSER_IC_LKP_ENTRY_TPID_VLAN_0_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 23, 5, 3, r)
+#define RDD_PARSER_IC_LKP_ENTRY_TPID_VLAN_0_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 23, 5, 3, v)
+#define RDD_PARSER_IC_LKP_ENTRY_TPID_VLAN_0_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 23, 5, 3, r)
+#define RDD_PARSER_IC_LKP_ENTRY_TPID_VLAN_0_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 23, 5, 3, v)
+#define RDD_PARSER_IC_LKP_ENTRY_TPID_VLAN_1_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 23, 2, 3, r)
+#define RDD_PARSER_IC_LKP_ENTRY_TPID_VLAN_1_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 23, 2, 3, v)
+#define RDD_PARSER_IC_LKP_ENTRY_TPID_VLAN_1_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 23, 2, 3, r)
+#define RDD_PARSER_IC_LKP_ENTRY_TPID_VLAN_1_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 23, 2, 3, v)
+#define RDD_PARSER_IC_LKP_ENTRY_IPV6_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 23, 1, 1, r)
+#define RDD_PARSER_IC_LKP_ENTRY_IPV6_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 23, 1, 1, v)
+#define RDD_PARSER_IC_LKP_ENTRY_IPV6_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 23, 1, 1, r)
+#define RDD_PARSER_IC_LKP_ENTRY_IPV6_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 23, 1, 1, v)
+#define RDD_PARSER_IC_LKP_ENTRY_IPV4_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 23, 0, 1, r)
+#define RDD_PARSER_IC_LKP_ENTRY_IPV4_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 23, 0, 1, v)
+#define RDD_PARSER_IC_LKP_ENTRY_IPV4_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 23, 0, 1, r)
+#define RDD_PARSER_IC_LKP_ENTRY_IPV4_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 23, 0, 1, v)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_PBIT_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 24, 5, 3, r)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_PBIT_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 24, 5, 3, v)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_PBIT_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 24, 5, 3, r)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_PBIT_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 24, 5, 3, v)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_CFI_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 24, 4, 1, r)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_CFI_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 24, 4, 1, v)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_CFI_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 24, 4, 1, r)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_CFI_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 24, 4, 1, v)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_VID_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 24, 0, 12, r)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_VID_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 24, 0, 12, v)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_VID_READ(r, p)                        FIELD_MREAD_16((uint8_t *)p + 24, 0, 12, r)
+#define RDD_PARSER_IC_LKP_ENTRY_OUTER_VID_WRITE(v, p)                       FIELD_MWRITE_16((uint8_t *)p + 24, 0, 12, v)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_PBIT_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 26, 5, 3, r)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_PBIT_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 26, 5, 3, v)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_PBIT_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 26, 5, 3, r)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_PBIT_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 26, 5, 3, v)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_CFI_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 26, 4, 1, r)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_CFI_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 26, 4, 1, v)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_CFI_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 26, 4, 1, r)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_CFI_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 26, 4, 1, v)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_VID_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 26, 0, 12, r)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_VID_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 26, 0, 12, v)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_VID_READ(r, p)                        FIELD_MREAD_16((uint8_t *)p + 26, 0, 12, r)
+#define RDD_PARSER_IC_LKP_ENTRY_INNER_VID_WRITE(v, p)                       FIELD_MWRITE_16((uint8_t *)p + 26, 0, 12, v)
+#define RDD_PARSER_IC_LKP_ENTRY_LOOKUP_PORT_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 29, 3, 5, r)
+#define RDD_PARSER_IC_LKP_ENTRY_LOOKUP_PORT_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 29, 3, 5, v)
+#define RDD_PARSER_IC_LKP_ENTRY_LOOKUP_PORT_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 29, 3, 5, r)
+#define RDD_PARSER_IC_LKP_ENTRY_LOOKUP_PORT_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 29, 3, 5, v)
+#define RDD_PARSER_IC_LKP_ENTRY_VLANS_NUM_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 29, 0, 3, r)
+#define RDD_PARSER_IC_LKP_ENTRY_VLANS_NUM_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 29, 0, 3, v)
+#define RDD_PARSER_IC_LKP_ENTRY_VLANS_NUM_READ(r, p)                        FIELD_MREAD_8((uint8_t *)p + 29, 0, 3, r)
+#define RDD_PARSER_IC_LKP_ENTRY_VLANS_NUM_WRITE(v, p)                       FIELD_MWRITE_8((uint8_t *)p + 29, 0, 3, v)
+#define RDD_PARSER_IC_LKP_ENTRY_TOS_READ_G(r, g, idx)                       GROUP_MREAD_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 30, r)
+#define RDD_PARSER_IC_LKP_ENTRY_TOS_WRITE_G(v, g, idx)                      GROUP_MWRITE_8(g, idx*sizeof(RDD_PARSER_IC_LKP_ENTRY_DTS) + 30, v)
+#define RDD_PARSER_IC_LKP_ENTRY_TOS_READ(r, p)                              MREAD_8((uint8_t *)p + 30, r)
+#define RDD_PARSER_IC_LKP_ENTRY_TOS_WRITE(v, p)                             MWRITE_8((uint8_t *)p + 30, v)
+/* <<<RDD_PARSER_IC_LKP_ENTRY_DTS */
+
+/* <<<RDD_PARSER_IC_LKP_ENTRY */
+
+
+/* >>>RDD_NATC_CONTROL_ENTRY */
+#define NATC_CONTROL_ENTRY_DONE_F_OFFSET                             31
+#define NATC_CONTROL_ENTRY_DONE_F_WIDTH                              1
+#define NATC_CONTROL_ENTRY_NATC_CONTROL_ENTRY_OFFSET                 0
+#define NATC_CONTROL_ENTRY_DONE_OFFSET                               0
+#define NATC_CONTROL_ENTRY_DONE_WORD_OFFSET                          0
+#define NATC_CONTROL_ENTRY_DONE_F_OFFSET_MOD8                        7
+#define NATC_CONTROL_ENTRY_DONE_F_OFFSET_MOD16                       15
+#define NATC_CONTROL_ENTRY_NATC_HIT_F_OFFSET                         30
+#define NATC_CONTROL_ENTRY_NATC_HIT_F_WIDTH                          1
+#define NATC_CONTROL_ENTRY_NATC_HIT_OFFSET                           0
+#define NATC_CONTROL_ENTRY_NATC_HIT_WORD_OFFSET                      0
+#define NATC_CONTROL_ENTRY_NATC_HIT_F_OFFSET_MOD8                    6
+#define NATC_CONTROL_ENTRY_NATC_HIT_F_OFFSET_MOD16                   14
+#define NATC_CONTROL_ENTRY_CACHE_HIT_F_OFFSET                        29
+#define NATC_CONTROL_ENTRY_CACHE_HIT_F_WIDTH                         1
+#define NATC_CONTROL_ENTRY_CACHE_HIT_OFFSET                          0
+#define NATC_CONTROL_ENTRY_CACHE_HIT_WORD_OFFSET                     0
+#define NATC_CONTROL_ENTRY_CACHE_HIT_F_OFFSET_MOD8                   5
+#define NATC_CONTROL_ENTRY_CACHE_HIT_F_OFFSET_MOD16                  13
+#define NATC_CONTROL_ENTRY_HW_RESERVED0_F_OFFSET                     24
+#define NATC_CONTROL_ENTRY_HW_RESERVED0_F_WIDTH                      5
+#define NATC_CONTROL_ENTRY_HW_RESERVED0_OFFSET                       0
+#define NATC_CONTROL_ENTRY_HW_RESERVED0_WORD_OFFSET                  0
+#define NATC_CONTROL_ENTRY_HW_RESERVED0_F_OFFSET_MOD8                0
+#define NATC_CONTROL_ENTRY_HW_RESERVED0_F_OFFSET_MOD16               8
+#define NATC_CONTROL_ENTRY_HAS_ITER_F_OFFSET                         20
+#define NATC_CONTROL_ENTRY_HAS_ITER_F_WIDTH                          4
+#define NATC_CONTROL_ENTRY_HAS_ITER_OFFSET                           1
+#define NATC_CONTROL_ENTRY_HAS_ITER_WORD_OFFSET                      0
+#define NATC_CONTROL_ENTRY_HAS_ITER_F_OFFSET_MOD8                    4
+#define NATC_CONTROL_ENTRY_HAS_ITER_F_OFFSET_MOD16                   4
+#define NATC_CONTROL_ENTRY_HW_RESERVED1_F_OFFSET                     18
+#define NATC_CONTROL_ENTRY_HW_RESERVED1_F_WIDTH                      2
+#define NATC_CONTROL_ENTRY_HW_RESERVED1_OFFSET                       1
+#define NATC_CONTROL_ENTRY_HW_RESERVED1_WORD_OFFSET                  0
+#define NATC_CONTROL_ENTRY_HW_RESERVED1_F_OFFSET_MOD8                2
+#define NATC_CONTROL_ENTRY_HW_RESERVED1_F_OFFSET_MOD16               2
+#define NATC_CONTROL_ENTRY_HASH_VAL_F_OFFSET                         0
+#define NATC_CONTROL_ENTRY_HASH_VAL_F_WIDTH                          18
+#define NATC_CONTROL_ENTRY_HASH_VAL_OFFSET                           0
+#define NATC_CONTROL_ENTRY_HASH_VAL_WORD_OFFSET                      0
+#define NATC_CONTROL_ENTRY_HW_RESERVED2_F_OFFSET                     0
+#define NATC_CONTROL_ENTRY_HW_RESERVED2_F_WIDTH                      32
+#define NATC_CONTROL_ENTRY_HW_RESERVED2_OFFSET                       4
+#define NATC_CONTROL_ENTRY_HW_RESERVED2_WORD_OFFSET                  1
+
+/* >>>RDD_NATC_CONTROL_ENTRY_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	done        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	natc_hit    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cache_hit   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	hw_reserved0	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	has_iter    	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	hw_reserved1	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	hash_val    	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	hw_reserved2	;
+#else
+	uint32_t	hash_val    	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	hw_reserved1	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	has_iter    	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	hw_reserved0	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	cache_hit   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	natc_hit    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	done        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	hw_reserved2	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NATC_CONTROL_ENTRY_DTS;
+
+typedef union
+{
+    uint32_t word_val[2];
+    uint64_t dword_val64[1];
+    RDD_NATC_CONTROL_ENTRY_DTS fields;
+} NATC_CONTROL_ENTRY_STRUCT;
+#define RDD_NATC_CONTROL_ENTRY_DONE_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS), 7, 1, r)
+#define RDD_NATC_CONTROL_ENTRY_DONE_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS), 7, 1, v)
+#define RDD_NATC_CONTROL_ENTRY_DONE_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p, 7, 1, r)
+#define RDD_NATC_CONTROL_ENTRY_DONE_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_NATC_CONTROL_ENTRY_NATC_HIT_READ_G(r, g, idx)              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS), 6, 1, r)
+#define RDD_NATC_CONTROL_ENTRY_NATC_HIT_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS), 6, 1, v)
+#define RDD_NATC_CONTROL_ENTRY_NATC_HIT_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p, 6, 1, r)
+#define RDD_NATC_CONTROL_ENTRY_NATC_HIT_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p, 6, 1, v)
+#define RDD_NATC_CONTROL_ENTRY_CACHE_HIT_READ_G(r, g, idx)             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS), 5, 1, r)
+#define RDD_NATC_CONTROL_ENTRY_CACHE_HIT_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS), 5, 1, v)
+#define RDD_NATC_CONTROL_ENTRY_CACHE_HIT_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p, 5, 1, r)
+#define RDD_NATC_CONTROL_ENTRY_CACHE_HIT_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p, 5, 1, v)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED0_READ_G(r, g, idx)          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS), 0, 5, r)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED0_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS), 0, 5, v)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED0_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p, 0, 5, r)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED0_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p, 0, 5, v)
+#define RDD_NATC_CONTROL_ENTRY_HAS_ITER_READ_G(r, g, idx)              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS) + 1, 4, 4, r)
+#define RDD_NATC_CONTROL_ENTRY_HAS_ITER_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS) + 1, 4, 4, v)
+#define RDD_NATC_CONTROL_ENTRY_HAS_ITER_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 1, 4, 4, r)
+#define RDD_NATC_CONTROL_ENTRY_HAS_ITER_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 1, 4, 4, v)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED1_READ_G(r, g, idx)          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS) + 1, 2, 2, r)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED1_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS) + 1, 2, 2, v)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED1_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 1, 2, 2, r)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED1_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 1, 2, 2, v)
+#define RDD_NATC_CONTROL_ENTRY_HASH_VAL_READ_G(r, g, idx)              GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS) + 0, 0, 18, r)
+#define RDD_NATC_CONTROL_ENTRY_HASH_VAL_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS) + 0, 0, 18, v)
+#define RDD_NATC_CONTROL_ENTRY_HASH_VAL_READ(r, p)                     FIELD_MREAD_32((uint8_t *)p + 0, 0, 18, r)
+#define RDD_NATC_CONTROL_ENTRY_HASH_VAL_WRITE(v, p)                    FIELD_MWRITE_32((uint8_t *)p + 0, 0, 18, v)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED2_READ_G(r, g, idx)          GROUP_MREAD_32(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS) + 4, r)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED2_WRITE_G(v, g, idx)         GROUP_MWRITE_32(g, idx*sizeof(RDD_NATC_CONTROL_ENTRY_DTS) + 4, v)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED2_READ(r, p)                 MREAD_32((uint8_t *)p + 4, r)
+#define RDD_NATC_CONTROL_ENTRY_HW_RESERVED2_WRITE(v, p)                MWRITE_32((uint8_t *)p + 4, v)
+/* <<<RDD_NATC_CONTROL_ENTRY_DTS */
+
+/* <<<RDD_NATC_CONTROL_ENTRY */
+
+
+/* >>>RDD_NATC_COUNTERS_ENTRY */
+#define NATC_COUNTERS_ENTRY_HIT_COUNTER_F_OFFSET                      0
+#define NATC_COUNTERS_ENTRY_HIT_COUNTER_F_WIDTH                       32
+#define NATC_COUNTERS_ENTRY_NATC_COUNTERS_ENTRY_OFFSET                0
+#define NATC_COUNTERS_ENTRY_HIT_COUNTER_OFFSET                        0
+#define NATC_COUNTERS_ENTRY_HIT_COUNTER_WORD_OFFSET                   0
+#define NATC_COUNTERS_ENTRY_BYTES_COUNTER_F_OFFSET                    0
+#define NATC_COUNTERS_ENTRY_BYTES_COUNTER_F_WIDTH                     32
+#define NATC_COUNTERS_ENTRY_BYTES_COUNTER_OFFSET                      4
+#define NATC_COUNTERS_ENTRY_BYTES_COUNTER_WORD_OFFSET                 1
+
+/* >>>RDD_NATC_COUNTERS_ENTRY_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	hit_counter  	;
+	uint32_t	bytes_counter	;
+#else
+	uint32_t	hit_counter  	;
+	uint32_t	bytes_counter	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_NATC_COUNTERS_ENTRY_DTS;
+
+typedef union
+{
+    uint32_t word_val[2];
+    uint64_t dword_val64[1];
+    RDD_NATC_COUNTERS_ENTRY_DTS fields;
+} NATC_COUNTERS_ENTRY_STRUCT;
+#define RDD_NATC_COUNTERS_ENTRY_HIT_COUNTER_READ_G(r, g, idx)            GROUP_MREAD_32(g, idx*sizeof(RDD_NATC_COUNTERS_ENTRY_DTS), r)
+#define RDD_NATC_COUNTERS_ENTRY_HIT_COUNTER_WRITE_G(v, g, idx)           GROUP_MWRITE_32(g, idx*sizeof(RDD_NATC_COUNTERS_ENTRY_DTS), v)
+#define RDD_NATC_COUNTERS_ENTRY_HIT_COUNTER_READ(r, p)                   MREAD_32((uint8_t *)p, r)
+#define RDD_NATC_COUNTERS_ENTRY_HIT_COUNTER_WRITE(v, p)                  MWRITE_32((uint8_t *)p, v)
+#define RDD_NATC_COUNTERS_ENTRY_BYTES_COUNTER_READ_G(r, g, idx)          GROUP_MREAD_32(g, idx*sizeof(RDD_NATC_COUNTERS_ENTRY_DTS) + 4, r)
+#define RDD_NATC_COUNTERS_ENTRY_BYTES_COUNTER_WRITE_G(v, g, idx)         GROUP_MWRITE_32(g, idx*sizeof(RDD_NATC_COUNTERS_ENTRY_DTS) + 4, v)
+#define RDD_NATC_COUNTERS_ENTRY_BYTES_COUNTER_READ(r, p)                 MREAD_32((uint8_t *)p + 4, r)
+#define RDD_NATC_COUNTERS_ENTRY_BYTES_COUNTER_WRITE(v, p)                MWRITE_32((uint8_t *)p + 4, v)
+/* <<<RDD_NATC_COUNTERS_ENTRY_DTS */
+
+/* <<<RDD_NATC_COUNTERS_ENTRY */
+
+
+/* >>>RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE */
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL0_F_OFFSET                        0
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL0_F_WIDTH                         2
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL0_OFFSET                          3
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL0_WORD_OFFSET                     0
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL0_F_OFFSET_MOD8                   0
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL0_F_OFFSET_MOD16                  0
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL1_F_OFFSET                        30
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL1_F_WIDTH                         2
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL1_OFFSET                          4
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL1_WORD_OFFSET                     1
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL1_F_OFFSET_MOD8                   6
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL1_F_OFFSET_MOD16                  14
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_BYTES_POPPED_F_OFFSET                     16
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_BYTES_POPPED_F_WIDTH                      14
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_BYTES_POPPED_OFFSET                       4
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_BYTES_POPPED_WORD_OFFSET                  1
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_BYTES_POPPED_F_OFFSET_MOD16               0
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_AGG_F_OFFSET                              15
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_AGG_F_WIDTH                               1
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_AGG_OFFSET                                6
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_AGG_WORD_OFFSET                           1
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_AGG_F_OFFSET_MOD8                         7
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_AGG_F_OFFSET_MOD16                        15
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM0_F_OFFSET                      14
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM0_F_WIDTH                       1
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM0_OFFSET                        6
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM0_WORD_OFFSET                   1
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM0_F_OFFSET_MOD8                 6
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM0_F_OFFSET_MOD16                14
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_ABS_F_OFFSET                              13
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_ABS_F_WIDTH                               1
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_ABS_OFFSET                                6
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_ABS_WORD_OFFSET                           1
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_ABS_F_OFFSET_MOD8                         5
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_ABS_F_OFFSET_MOD16                        13
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM1_F_OFFSET                      12
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM1_F_WIDTH                       1
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM1_OFFSET                        6
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM1_WORD_OFFSET                   1
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM1_F_OFFSET_MOD8                 4
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM1_F_OFFSET_MOD16                12
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_QUEUE_NUMBER_F_OFFSET                     0
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_QUEUE_NUMBER_F_WIDTH                      9
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_QUEUE_NUMBER_OFFSET                       6
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_QUEUE_NUMBER_WORD_OFFSET                  1
+#define BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_QUEUE_NUMBER_F_OFFSET_MOD16               0
+
+/* >>>RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	reserved0   	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	fpm_pool0   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	fpm_pool1   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bytes_popped	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	agg         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_mem0 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	abs         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_mem1 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1   	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	queue_number	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#else
+	uint32_t	fpm_pool0   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0   	:30	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	queue_number	:9	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved1   	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_mem1 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	abs         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	target_mem0 	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	agg         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bytes_popped	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	fpm_pool1   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS;
+
+typedef union
+{
+    uint32_t word_val[2];
+    uint64_t dword_val64[1];
+    RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS fields;
+} BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_STRUCT;
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL0_READ_G(r, g, idx)             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 3, 0, 2, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL0_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 3, 0, 2, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL0_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 3, 0, 2, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL0_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 3, 0, 2, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL1_READ_G(r, g, idx)             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 4, 6, 2, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL1_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 4, 6, 2, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL1_READ(r, p)                    FIELD_MREAD_8((uint8_t *)p + 4, 6, 2, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_FPM_POOL1_WRITE(v, p)                   FIELD_MWRITE_8((uint8_t *)p + 4, 6, 2, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_BYTES_POPPED_READ_G(r, g, idx)          GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 4, 0, 14, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_BYTES_POPPED_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 4, 0, 14, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_BYTES_POPPED_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 4, 0, 14, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_BYTES_POPPED_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 4, 0, 14, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_AGG_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 6, 7, 1, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_AGG_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 6, 7, 1, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_AGG_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 6, 7, 1, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_AGG_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 6, 7, 1, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM0_READ_G(r, g, idx)           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 6, 6, 1, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM0_WRITE_G(v, g, idx)          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 6, 6, 1, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM0_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 6, 6, 1, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM0_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 6, 6, 1, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_ABS_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 6, 5, 1, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_ABS_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 6, 5, 1, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_ABS_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p + 6, 5, 1, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_ABS_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p + 6, 5, 1, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM1_READ_G(r, g, idx)           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 6, 4, 1, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM1_WRITE_G(v, g, idx)          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 6, 4, 1, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM1_READ(r, p)                  FIELD_MREAD_8((uint8_t *)p + 6, 4, 1, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_TARGET_MEM1_WRITE(v, p)                 FIELD_MWRITE_8((uint8_t *)p + 6, 4, 1, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_QUEUE_NUMBER_READ_G(r, g, idx)          GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 6, 0, 9, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_QUEUE_NUMBER_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS) + 6, 0, 9, v)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_QUEUE_NUMBER_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p + 6, 0, 9, r)
+#define RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_QUEUE_NUMBER_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p + 6, 0, 9, v)
+/* <<<RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE_DTS */
+
+/* <<<RDD_BBMSG_RNR_TO_QM_PD_FIFO_CREDIT_FREE */
+
+
+/* >>>RDD_HASH_RESULT */
+#define HASH_RESULT_MATCH_F_OFFSET                            30
+#define HASH_RESULT_MATCH_F_WIDTH                             2
+#define HASH_RESULT_HASH_RESULT_OFFSET                        0
+#define HASH_RESULT_MATCH_OFFSET                              0
+#define HASH_RESULT_MATCH_WORD_OFFSET                         0
+#define HASH_RESULT_MATCH_F_OFFSET_MOD8                       6
+#define HASH_RESULT_MATCH_F_OFFSET_MOD16                      14
+#define HASH_RESULT_MATCH_INDEX_F_OFFSET                      19
+#define HASH_RESULT_MATCH_INDEX_F_WIDTH                       11
+#define HASH_RESULT_MATCH_INDEX_OFFSET                        0
+#define HASH_RESULT_MATCH_INDEX_WORD_OFFSET                   0
+#define HASH_RESULT_MATCH_INDEX_F_OFFSET_MOD16                3
+#define HASH_RESULT_MATCH_ENGINE_F_OFFSET                     17
+#define HASH_RESULT_MATCH_ENGINE_F_WIDTH                      2
+#define HASH_RESULT_MATCH_ENGINE_OFFSET                       1
+#define HASH_RESULT_MATCH_ENGINE_WORD_OFFSET                  0
+#define HASH_RESULT_MATCH_ENGINE_F_OFFSET_MOD8                1
+#define HASH_RESULT_MATCH_ENGINE_F_OFFSET_MOD16               1
+#define HASH_RESULT_CONTEXT0_32_47_F_OFFSET                   0
+#define HASH_RESULT_CONTEXT0_32_47_F_WIDTH                    16
+#define HASH_RESULT_CONTEXT0_32_47_OFFSET                     2
+#define HASH_RESULT_CONTEXT0_32_47_WORD_OFFSET                0
+#define HASH_RESULT_CONTEXT0_0_31_F_OFFSET                    0
+#define HASH_RESULT_CONTEXT0_0_31_F_WIDTH                     32
+#define HASH_RESULT_CONTEXT0_0_31_OFFSET                      4
+#define HASH_RESULT_CONTEXT0_0_31_WORD_OFFSET                 1
+#define HASH_RESULT_CONTEXT1_16_47_F_OFFSET                   0
+#define HASH_RESULT_CONTEXT1_16_47_F_WIDTH                    32
+#define HASH_RESULT_CONTEXT1_16_47_OFFSET                     8
+#define HASH_RESULT_CONTEXT1_16_47_WORD_OFFSET                2
+#define HASH_RESULT_CONTEXT1_0_15_F_OFFSET                    16
+#define HASH_RESULT_CONTEXT1_0_15_F_WIDTH                     16
+#define HASH_RESULT_CONTEXT1_0_15_OFFSET                      12
+#define HASH_RESULT_CONTEXT1_0_15_WORD_OFFSET                 3
+#define HASH_RESULT_CONTEXT2_32_47_F_OFFSET                   0
+#define HASH_RESULT_CONTEXT2_32_47_F_WIDTH                    16
+#define HASH_RESULT_CONTEXT2_32_47_OFFSET                     14
+#define HASH_RESULT_CONTEXT2_32_47_WORD_OFFSET                3
+#define HASH_RESULT_CONTEXT2_0_31_F_OFFSET                    0
+#define HASH_RESULT_CONTEXT2_0_31_F_WIDTH                     32
+#define HASH_RESULT_CONTEXT2_0_31_OFFSET                      16
+#define HASH_RESULT_CONTEXT2_0_31_WORD_OFFSET                 4
+
+/* >>>RDD_HASH_RESULT_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	match         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	match_index   	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	match_engine  	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_0    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	context0_32_47	;
+	uint32_t	context0_0_31 	;
+	uint32_t	context1_16_47	;
+	uint16_t	context1_0_15 	;
+	uint16_t	context2_32_47	;
+	uint32_t	context2_0_31 	;
+	uint32_t	reserved_1    	;
+#else
+	uint16_t	context0_32_47	;
+	uint32_t	reserved_0    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	match_engine  	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	match_index   	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	match         	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	context0_0_31 	;
+	uint32_t	context1_16_47	;
+	uint16_t	context2_32_47	;
+	uint16_t	context1_0_15 	;
+	uint32_t	context2_0_31 	;
+	uint32_t	reserved_1    	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_HASH_RESULT_DTS;
+
+typedef union
+{
+    uint32_t word_val[6];
+    uint64_t dword_val64[3];
+    RDD_HASH_RESULT_DTS fields;
+} HASH_RESULT_STRUCT;
+#define RDD_HASH_RESULT_MATCH_READ_G(r, g, idx)                   GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_HASH_RESULT_DTS), 6, 2, r)
+#define RDD_HASH_RESULT_MATCH_WRITE_G(v, g, idx)                  GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_HASH_RESULT_DTS), 6, 2, v)
+#define RDD_HASH_RESULT_MATCH_READ(r, p)                          FIELD_MREAD_8((uint8_t *)p, 6, 2, r)
+#define RDD_HASH_RESULT_MATCH_WRITE(v, p)                         FIELD_MWRITE_8((uint8_t *)p, 6, 2, v)
+#define RDD_HASH_RESULT_MATCH_INDEX_READ_G(r, g, idx)             GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_HASH_RESULT_DTS), 3, 11, r)
+#define RDD_HASH_RESULT_MATCH_INDEX_WRITE_G(v, g, idx)            GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_HASH_RESULT_DTS), 3, 11, v)
+#define RDD_HASH_RESULT_MATCH_INDEX_READ(r, p)                    FIELD_MREAD_16((uint8_t *)p, 3, 11, r)
+#define RDD_HASH_RESULT_MATCH_INDEX_WRITE(v, p)                   FIELD_MWRITE_16((uint8_t *)p, 3, 11, v)
+#define RDD_HASH_RESULT_MATCH_ENGINE_READ_G(r, g, idx)            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 1, 1, 2, r)
+#define RDD_HASH_RESULT_MATCH_ENGINE_WRITE_G(v, g, idx)           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 1, 1, 2, v)
+#define RDD_HASH_RESULT_MATCH_ENGINE_READ(r, p)                   FIELD_MREAD_8((uint8_t *)p + 1, 1, 2, r)
+#define RDD_HASH_RESULT_MATCH_ENGINE_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 1, 1, 2, v)
+#define RDD_HASH_RESULT_CONTEXT0_32_47_READ_G(r, g, idx)          GROUP_MREAD_16(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 2, r)
+#define RDD_HASH_RESULT_CONTEXT0_32_47_WRITE_G(v, g, idx)         GROUP_MWRITE_16(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 2, v)
+#define RDD_HASH_RESULT_CONTEXT0_32_47_READ(r, p)                 MREAD_16((uint8_t *)p + 2, r)
+#define RDD_HASH_RESULT_CONTEXT0_32_47_WRITE(v, p)                MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_HASH_RESULT_CONTEXT0_0_31_READ_G(r, g, idx)           GROUP_MREAD_32(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 4, r)
+#define RDD_HASH_RESULT_CONTEXT0_0_31_WRITE_G(v, g, idx)          GROUP_MWRITE_32(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 4, v)
+#define RDD_HASH_RESULT_CONTEXT0_0_31_READ(r, p)                  MREAD_32((uint8_t *)p + 4, r)
+#define RDD_HASH_RESULT_CONTEXT0_0_31_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 4, v)
+#define RDD_HASH_RESULT_CONTEXT1_16_47_READ_G(r, g, idx)          GROUP_MREAD_32(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 8, r)
+#define RDD_HASH_RESULT_CONTEXT1_16_47_WRITE_G(v, g, idx)         GROUP_MWRITE_32(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 8, v)
+#define RDD_HASH_RESULT_CONTEXT1_16_47_READ(r, p)                 MREAD_32((uint8_t *)p + 8, r)
+#define RDD_HASH_RESULT_CONTEXT1_16_47_WRITE(v, p)                MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_HASH_RESULT_CONTEXT1_0_15_READ_G(r, g, idx)           GROUP_MREAD_16(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 12, r)
+#define RDD_HASH_RESULT_CONTEXT1_0_15_WRITE_G(v, g, idx)          GROUP_MWRITE_16(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 12, v)
+#define RDD_HASH_RESULT_CONTEXT1_0_15_READ(r, p)                  MREAD_16((uint8_t *)p + 12, r)
+#define RDD_HASH_RESULT_CONTEXT1_0_15_WRITE(v, p)                 MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_HASH_RESULT_CONTEXT2_32_47_READ_G(r, g, idx)          GROUP_MREAD_16(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 14, r)
+#define RDD_HASH_RESULT_CONTEXT2_32_47_WRITE_G(v, g, idx)         GROUP_MWRITE_16(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 14, v)
+#define RDD_HASH_RESULT_CONTEXT2_32_47_READ(r, p)                 MREAD_16((uint8_t *)p + 14, r)
+#define RDD_HASH_RESULT_CONTEXT2_32_47_WRITE(v, p)                MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_HASH_RESULT_CONTEXT2_0_31_READ_G(r, g, idx)           GROUP_MREAD_32(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 16, r)
+#define RDD_HASH_RESULT_CONTEXT2_0_31_WRITE_G(v, g, idx)          GROUP_MWRITE_32(g, idx*sizeof(RDD_HASH_RESULT_DTS) + 16, v)
+#define RDD_HASH_RESULT_CONTEXT2_0_31_READ(r, p)                  MREAD_32((uint8_t *)p + 16, r)
+#define RDD_HASH_RESULT_CONTEXT2_0_31_WRITE(v, p)                 MWRITE_32((uint8_t *)p + 16, v)
+/* <<<RDD_HASH_RESULT_DTS */
+
+/* <<<RDD_HASH_RESULT */
+
+
+/* >>>RDD_TRACE_EVENT */
+#define TRACE_EVENT_TIMESTAMP_F_OFFSET                        20
+#define TRACE_EVENT_TIMESTAMP_F_WIDTH                         12
+#define TRACE_EVENT_TRACE_EVENT_OFFSET                        0
+#define TRACE_EVENT_TIMESTAMP_OFFSET                          0
+#define TRACE_EVENT_TIMESTAMP_WORD_OFFSET                     0
+#define TRACE_EVENT_TIMESTAMP_F_OFFSET_MOD16                  4
+#define TRACE_EVENT_EVENT_ID_F_OFFSET                         18
+#define TRACE_EVENT_EVENT_ID_F_WIDTH                          2
+#define TRACE_EVENT_EVENT_ID_OFFSET                           1
+#define TRACE_EVENT_EVENT_ID_WORD_OFFSET                      0
+#define TRACE_EVENT_EVENT_ID_F_OFFSET_MOD8                    2
+#define TRACE_EVENT_EVENT_ID_F_OFFSET_MOD16                   2
+#define TRACE_EVENT_TRACE_EVENT_INFO_F_OFFSET                 0
+#define TRACE_EVENT_TRACE_EVENT_INFO_F_WIDTH                  18
+#define TRACE_EVENT_TRACE_EVENT_INFO_OFFSET                   0
+#define TRACE_EVENT_TRACE_EVENT_INFO_WORD_OFFSET              0
+
+/* >>>RDD_TRACE_EVENT_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	timestamp              	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	event_id               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	trace_event_info       	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_timestamp              	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_event_id               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	incoming_task_num                	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	reserved                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	task_pc                          	:13	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_timestamp              	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_event_id               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	incoming_bbhrx_src_addr          	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	dma_wr                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	dma_rd                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	dma_wr_reply                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	ramrd                            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	parser                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	bbhtx                            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	bbhrx_async                      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	bbhrx_sync                       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	cpu                              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	fw_self                          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	fw                               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	timer                            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_timestamp              	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_event_id               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2                        	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	acc_type                         	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+		};
+	};
+#else
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	trace_event_info       	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	event_id               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	timestamp              	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	incoming_task_num                	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	reserved                         	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	task_pc                          	:13	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	reserved1_event_id               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_timestamp              	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	incoming_bbhrx_src_addr          	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	dma_wr                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	dma_rd                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	dma_wr_reply                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	ramrd                            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	parser                           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	bbhtx                            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	bbhrx_async                      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	bbhrx_sync                       	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	cpu                              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	fw_self                          	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	fw                               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	timer                            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	reserved2_event_id               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_timestamp              	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved2                        	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	acc_type                         	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of trace_event_info union */
+			uint32_t	reserved3_event_id               	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_timestamp              	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_TRACE_EVENT_DTS;
+
+typedef union
+{
+    uint32_t word_val[1];
+    RDD_TRACE_EVENT_DTS fields;
+} TRACE_EVENT_STRUCT;
+#define RDD_TRACE_EVENT_TIMESTAMP_READ_G(r, g, idx)                        GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_TRACE_EVENT_DTS), 4, 12, r)
+#define RDD_TRACE_EVENT_TIMESTAMP_WRITE_G(v, g, idx)                       GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_TRACE_EVENT_DTS), 4, 12, v)
+#define RDD_TRACE_EVENT_TIMESTAMP_READ(r, p)                               FIELD_MREAD_16((uint8_t *)p, 4, 12, r)
+#define RDD_TRACE_EVENT_TIMESTAMP_WRITE(v, p)                              FIELD_MWRITE_16((uint8_t *)p, 4, 12, v)
+#define RDD_TRACE_EVENT_EVENT_ID_READ_G(r, g, idx)                         GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 1, 2, 2, r)
+#define RDD_TRACE_EVENT_EVENT_ID_WRITE_G(v, g, idx)                        GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 1, 2, 2, v)
+#define RDD_TRACE_EVENT_EVENT_ID_READ(r, p)                                FIELD_MREAD_8((uint8_t *)p + 1, 2, 2, r)
+#define RDD_TRACE_EVENT_EVENT_ID_WRITE(v, p)                               FIELD_MWRITE_8((uint8_t *)p + 1, 2, 2, v)
+#define RDD_TRACE_EVENT_TRACE_EVENT_INFO_READ_G(r, g, idx)                 GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 0, 0, 18, r)
+#define RDD_TRACE_EVENT_TRACE_EVENT_INFO_WRITE_G(v, g, idx)                GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 0, 0, 18, v)
+#define RDD_TRACE_EVENT_TRACE_EVENT_INFO_READ(r, p)                        FIELD_MREAD_32((uint8_t *)p + 0, 0, 18, r)
+#define RDD_TRACE_EVENT_TRACE_EVENT_INFO_WRITE(v, p)                       FIELD_MWRITE_32((uint8_t *)p + 0, 0, 18, v)
+#define RDD_TRACE_EVENT_INCOMING_TASK_NUM_READ_G(r, g, idx)                GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 0, 14, 4, r)
+#define RDD_TRACE_EVENT_INCOMING_TASK_NUM_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 0, 14, 4, v)
+#define RDD_TRACE_EVENT_INCOMING_TASK_NUM_READ(r, p)                       FIELD_MREAD_32((uint8_t *)p + 0, 14, 4, r)
+#define RDD_TRACE_EVENT_INCOMING_TASK_NUM_WRITE(v, p)                      FIELD_MWRITE_32((uint8_t *)p + 0, 14, 4, v)
+#define RDD_TRACE_EVENT_TASK_PC_READ_G(r, g, idx)                          GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 0, 13, r)
+#define RDD_TRACE_EVENT_TASK_PC_WRITE_G(v, g, idx)                         GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 0, 13, v)
+#define RDD_TRACE_EVENT_TASK_PC_READ(r, p)                                 FIELD_MREAD_16((uint8_t *)p + 2, 0, 13, r)
+#define RDD_TRACE_EVENT_TASK_PC_WRITE(v, p)                                FIELD_MWRITE_16((uint8_t *)p + 2, 0, 13, v)
+#define RDD_TRACE_EVENT_INCOMING_BBHRX_SRC_ADDR_READ_G(r, g, idx)          GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 0, 12, 6, r)
+#define RDD_TRACE_EVENT_INCOMING_BBHRX_SRC_ADDR_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 0, 12, 6, v)
+#define RDD_TRACE_EVENT_INCOMING_BBHRX_SRC_ADDR_READ(r, p)                 FIELD_MREAD_32((uint8_t *)p + 0, 12, 6, r)
+#define RDD_TRACE_EVENT_INCOMING_BBHRX_SRC_ADDR_WRITE(v, p)                FIELD_MWRITE_32((uint8_t *)p + 0, 12, 6, v)
+#define RDD_TRACE_EVENT_DMA_WR_READ_G(r, g, idx)                           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 3, 1, r)
+#define RDD_TRACE_EVENT_DMA_WR_WRITE_G(v, g, idx)                          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 3, 1, v)
+#define RDD_TRACE_EVENT_DMA_WR_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 2, 3, 1, r)
+#define RDD_TRACE_EVENT_DMA_WR_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 2, 3, 1, v)
+#define RDD_TRACE_EVENT_DMA_RD_READ_G(r, g, idx)                           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 2, 1, r)
+#define RDD_TRACE_EVENT_DMA_RD_WRITE_G(v, g, idx)                          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 2, 1, v)
+#define RDD_TRACE_EVENT_DMA_RD_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 2, 2, 1, r)
+#define RDD_TRACE_EVENT_DMA_RD_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 2, 2, 1, v)
+#define RDD_TRACE_EVENT_DMA_WR_REPLY_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 1, 1, r)
+#define RDD_TRACE_EVENT_DMA_WR_REPLY_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 1, 1, v)
+#define RDD_TRACE_EVENT_DMA_WR_REPLY_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 2, 1, 1, r)
+#define RDD_TRACE_EVENT_DMA_WR_REPLY_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 2, 1, 1, v)
+#define RDD_TRACE_EVENT_RAMRD_READ_G(r, g, idx)                            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 0, 1, r)
+#define RDD_TRACE_EVENT_RAMRD_WRITE_G(v, g, idx)                           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 0, 1, v)
+#define RDD_TRACE_EVENT_RAMRD_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 2, 0, 1, r)
+#define RDD_TRACE_EVENT_RAMRD_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 2, 0, 1, v)
+#define RDD_TRACE_EVENT_PARSER_READ_G(r, g, idx)                           GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 7, 1, r)
+#define RDD_TRACE_EVENT_PARSER_WRITE_G(v, g, idx)                          GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 7, 1, v)
+#define RDD_TRACE_EVENT_PARSER_READ(r, p)                                  FIELD_MREAD_8((uint8_t *)p + 3, 7, 1, r)
+#define RDD_TRACE_EVENT_PARSER_WRITE(v, p)                                 FIELD_MWRITE_8((uint8_t *)p + 3, 7, 1, v)
+#define RDD_TRACE_EVENT_BBHTX_READ_G(r, g, idx)                            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 6, 1, r)
+#define RDD_TRACE_EVENT_BBHTX_WRITE_G(v, g, idx)                           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 6, 1, v)
+#define RDD_TRACE_EVENT_BBHTX_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 3, 6, 1, r)
+#define RDD_TRACE_EVENT_BBHTX_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 3, 6, 1, v)
+#define RDD_TRACE_EVENT_BBHRX_ASYNC_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 5, 1, r)
+#define RDD_TRACE_EVENT_BBHRX_ASYNC_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 5, 1, v)
+#define RDD_TRACE_EVENT_BBHRX_ASYNC_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 3, 5, 1, r)
+#define RDD_TRACE_EVENT_BBHRX_ASYNC_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 3, 5, 1, v)
+#define RDD_TRACE_EVENT_BBHRX_SYNC_READ_G(r, g, idx)                       GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 4, 1, r)
+#define RDD_TRACE_EVENT_BBHRX_SYNC_WRITE_G(v, g, idx)                      GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 4, 1, v)
+#define RDD_TRACE_EVENT_BBHRX_SYNC_READ(r, p)                              FIELD_MREAD_8((uint8_t *)p + 3, 4, 1, r)
+#define RDD_TRACE_EVENT_BBHRX_SYNC_WRITE(v, p)                             FIELD_MWRITE_8((uint8_t *)p + 3, 4, 1, v)
+#define RDD_TRACE_EVENT_CPU_READ_G(r, g, idx)                              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 3, 1, r)
+#define RDD_TRACE_EVENT_CPU_WRITE_G(v, g, idx)                             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 3, 1, v)
+#define RDD_TRACE_EVENT_CPU_READ(r, p)                                     FIELD_MREAD_8((uint8_t *)p + 3, 3, 1, r)
+#define RDD_TRACE_EVENT_CPU_WRITE(v, p)                                    FIELD_MWRITE_8((uint8_t *)p + 3, 3, 1, v)
+#define RDD_TRACE_EVENT_FW_SELF_READ_G(r, g, idx)                          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 2, 1, r)
+#define RDD_TRACE_EVENT_FW_SELF_WRITE_G(v, g, idx)                         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 2, 1, v)
+#define RDD_TRACE_EVENT_FW_SELF_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 3, 2, 1, r)
+#define RDD_TRACE_EVENT_FW_SELF_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 3, 2, 1, v)
+#define RDD_TRACE_EVENT_FW_READ_G(r, g, idx)                               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 1, 1, r)
+#define RDD_TRACE_EVENT_FW_WRITE_G(v, g, idx)                              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 1, 1, v)
+#define RDD_TRACE_EVENT_FW_READ(r, p)                                      FIELD_MREAD_8((uint8_t *)p + 3, 1, 1, r)
+#define RDD_TRACE_EVENT_FW_WRITE(v, p)                                     FIELD_MWRITE_8((uint8_t *)p + 3, 1, 1, v)
+#define RDD_TRACE_EVENT_TIMER_READ_G(r, g, idx)                            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 0, 1, r)
+#define RDD_TRACE_EVENT_TIMER_WRITE_G(v, g, idx)                           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 3, 0, 1, v)
+#define RDD_TRACE_EVENT_TIMER_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 3, 0, 1, r)
+#define RDD_TRACE_EVENT_TIMER_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 3, 0, 1, v)
+#define RDD_TRACE_EVENT_ACC_TYPE_READ_G(r, g, idx)                         GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 0, 12, r)
+#define RDD_TRACE_EVENT_ACC_TYPE_WRITE_G(v, g, idx)                        GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_TRACE_EVENT_DTS) + 2, 0, 12, v)
+#define RDD_TRACE_EVENT_ACC_TYPE_READ(r, p)                                FIELD_MREAD_16((uint8_t *)p + 2, 0, 12, r)
+#define RDD_TRACE_EVENT_ACC_TYPE_WRITE(v, p)                               FIELD_MWRITE_16((uint8_t *)p + 2, 0, 12, v)
+/* <<<RDD_TRACE_EVENT_DTS */
+
+/* <<<RDD_TRACE_EVENT */
+
+
+/* >>>RDD_CPU_RX_DESCRIPTOR */
+#define CPU_RX_DESCRIPTOR_CPU_RX_DATA_PTR0_UNION_F_OFFSET           0
+#define CPU_RX_DESCRIPTOR_CPU_RX_DATA_PTR0_UNION_F_WIDTH            32
+#define CPU_RX_DESCRIPTOR_CPU_RX_DATA_PTR0_UNION_OFFSET             0
+#define CPU_RX_DESCRIPTOR_CPU_RX_DATA_PTR0_UNION_WORD_OFFSET        0
+#define CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_HI_F_OFFSET          24
+#define CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_HI_F_WIDTH           8
+#define CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_HI_OFFSET            4
+#define CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_HI_WORD_OFFSET       1
+#define CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_HI_F_OFFSET_MOD16    8
+#define CPU_RX_DESCRIPTOR_ABS_F_OFFSET                              16
+#define CPU_RX_DESCRIPTOR_ABS_F_WIDTH                               1
+#define CPU_RX_DESCRIPTOR_ABS_OFFSET                                5
+#define CPU_RX_DESCRIPTOR_ABS_WORD_OFFSET                           1
+#define CPU_RX_DESCRIPTOR_ABS_F_OFFSET_MOD8                         0
+#define CPU_RX_DESCRIPTOR_ABS_F_OFFSET_MOD16                        0
+#define CPU_RX_DESCRIPTOR_PLEN_F_OFFSET                             2
+#define CPU_RX_DESCRIPTOR_PLEN_F_WIDTH                              14
+#define CPU_RX_DESCRIPTOR_PLEN_OFFSET                               6
+#define CPU_RX_DESCRIPTOR_PLEN_WORD_OFFSET                          1
+#define CPU_RX_DESCRIPTOR_PLEN_F_OFFSET_MOD16                       2
+#define CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_F_OFFSET               1
+#define CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_F_WIDTH                1
+#define CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_OFFSET                 7
+#define CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_WORD_OFFSET            1
+#define CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_F_OFFSET_MOD8          1
+#define CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_F_OFFSET_MOD16         1
+#define CPU_RX_DESCRIPTOR_IS_SRC_LAN_F_OFFSET                       31
+#define CPU_RX_DESCRIPTOR_IS_SRC_LAN_F_WIDTH                        1
+#define CPU_RX_DESCRIPTOR_IS_SRC_LAN_OFFSET                         8
+#define CPU_RX_DESCRIPTOR_IS_SRC_LAN_WORD_OFFSET                    2
+#define CPU_RX_DESCRIPTOR_IS_SRC_LAN_F_OFFSET_MOD8                  7
+#define CPU_RX_DESCRIPTOR_IS_SRC_LAN_F_OFFSET_MOD16                 15
+#define CPU_RX_DESCRIPTOR_COLOR_F_OFFSET                            30
+#define CPU_RX_DESCRIPTOR_COLOR_F_WIDTH                             1
+#define CPU_RX_DESCRIPTOR_COLOR_OFFSET                              8
+#define CPU_RX_DESCRIPTOR_COLOR_WORD_OFFSET                         2
+#define CPU_RX_DESCRIPTOR_COLOR_F_OFFSET_MOD8                       6
+#define CPU_RX_DESCRIPTOR_COLOR_F_OFFSET_MOD16                      14
+#define CPU_RX_DESCRIPTOR_VPORT_F_OFFSET                            25
+#define CPU_RX_DESCRIPTOR_VPORT_F_WIDTH                             5
+#define CPU_RX_DESCRIPTOR_VPORT_OFFSET                              8
+#define CPU_RX_DESCRIPTOR_VPORT_WORD_OFFSET                         2
+#define CPU_RX_DESCRIPTOR_VPORT_F_OFFSET_MOD8                       1
+#define CPU_RX_DESCRIPTOR_VPORT_F_OFFSET_MOD16                      9
+#define CPU_RX_DESCRIPTOR_CPU_RX_SRC_UNION_F_OFFSET                 13
+#define CPU_RX_DESCRIPTOR_CPU_RX_SRC_UNION_F_WIDTH                  12
+#define CPU_RX_DESCRIPTOR_CPU_RX_SRC_UNION_OFFSET                   8
+#define CPU_RX_DESCRIPTOR_CPU_RX_SRC_UNION_WORD_OFFSET              2
+#define CPU_RX_DESCRIPTOR_CPU_RX_SRC_UNION_F_OFFSET_MOD16           13
+#define CPU_RX_DESCRIPTOR_DATA_OFFSET_F_OFFSET                      6
+#define CPU_RX_DESCRIPTOR_DATA_OFFSET_F_WIDTH                       7
+#define CPU_RX_DESCRIPTOR_DATA_OFFSET_OFFSET                        10
+#define CPU_RX_DESCRIPTOR_DATA_OFFSET_WORD_OFFSET                   2
+#define CPU_RX_DESCRIPTOR_DATA_OFFSET_F_OFFSET_MOD8                 6
+#define CPU_RX_DESCRIPTOR_DATA_OFFSET_F_OFFSET_MOD16                6
+#define CPU_RX_DESCRIPTOR_REASON_F_OFFSET                           0
+#define CPU_RX_DESCRIPTOR_REASON_F_WIDTH                            6
+#define CPU_RX_DESCRIPTOR_REASON_OFFSET                             11
+#define CPU_RX_DESCRIPTOR_REASON_WORD_OFFSET                        2
+#define CPU_RX_DESCRIPTOR_REASON_F_OFFSET_MOD8                      0
+#define CPU_RX_DESCRIPTOR_REASON_F_OFFSET_MOD16                     0
+#define CPU_RX_DESCRIPTOR_IS_EXCEPTION_F_OFFSET                     31
+#define CPU_RX_DESCRIPTOR_IS_EXCEPTION_F_WIDTH                      1
+#define CPU_RX_DESCRIPTOR_IS_EXCEPTION_OFFSET                       12
+#define CPU_RX_DESCRIPTOR_IS_EXCEPTION_WORD_OFFSET                  3
+#define CPU_RX_DESCRIPTOR_IS_EXCEPTION_F_OFFSET_MOD8                7
+#define CPU_RX_DESCRIPTOR_IS_EXCEPTION_F_OFFSET_MOD16               15
+#define CPU_RX_DESCRIPTOR_IS_RX_OFFLOAD_F_OFFSET                    30
+#define CPU_RX_DESCRIPTOR_IS_RX_OFFLOAD_F_WIDTH                     1
+#define CPU_RX_DESCRIPTOR_IS_RX_OFFLOAD_OFFSET                      12
+#define CPU_RX_DESCRIPTOR_IS_RX_OFFLOAD_WORD_OFFSET                 3
+#define CPU_RX_DESCRIPTOR_IS_RX_OFFLOAD_F_OFFSET_MOD8               6
+#define CPU_RX_DESCRIPTOR_IS_RX_OFFLOAD_F_OFFSET_MOD16              14
+#define CPU_RX_DESCRIPTOR_IS_UCAST_F_OFFSET                         29
+#define CPU_RX_DESCRIPTOR_IS_UCAST_F_WIDTH                          1
+#define CPU_RX_DESCRIPTOR_IS_UCAST_OFFSET                           12
+#define CPU_RX_DESCRIPTOR_IS_UCAST_WORD_OFFSET                      3
+#define CPU_RX_DESCRIPTOR_IS_UCAST_F_OFFSET_MOD8                    5
+#define CPU_RX_DESCRIPTOR_IS_UCAST_F_OFFSET_MOD16                   13
+#define CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_UNION_F_OFFSET              16
+#define CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_UNION_F_WIDTH               13
+#define CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_UNION_OFFSET                12
+#define CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_UNION_WORD_OFFSET           3
+#define CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_UNION_F_OFFSET_MOD16        0
+#define CPU_RX_DESCRIPTOR_CPU_RX_METADATA_UNION_F_OFFSET            0
+#define CPU_RX_DESCRIPTOR_CPU_RX_METADATA_UNION_F_WIDTH             16
+#define CPU_RX_DESCRIPTOR_CPU_RX_METADATA_UNION_OFFSET              14
+#define CPU_RX_DESCRIPTOR_CPU_RX_METADATA_UNION_WORD_OFFSET         3
+
+/* >>>RDD_CPU_RX_DESCRIPTOR_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	cpu_rx_data_ptr0_union  	; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	host_buffer_data_ptr_low          	; /* Member of cpu_rx_data_ptr0_union union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	fpm_idx                           	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_data_ptr0_union union */
+			uint32_t	reserved0                         	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_data_ptr0_union union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	bn0                               	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_data_ptr0_union union */
+			uint32_t	reserved9                         	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_data_ptr0_union union */
+		};
+	};
+	/* Union WORD 1 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint8_t	host_buffer_data_ptr_hi 	;
+			uint32_t	reserved1               	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	plen                    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	is_chksum_verified      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint8_t	reserved1_host_buffer_data_ptr_hi 	;
+			uint32_t	reserved1_reserved1               	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_abs                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_plen                    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_is_chksum_verified      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint8_t	reserved2_host_buffer_data_ptr_hi 	;
+			uint32_t	reserved2_reserved1               	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_abs                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_plen                    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_is_chksum_verified      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint8_t	reserved3_host_buffer_data_ptr_hi 	;
+			uint32_t	reserved3_reserved1               	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_plen                    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_is_chksum_verified      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 2 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	is_src_lan              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	color                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	vport                   	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	cpu_rx_src_union        	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	data_offset             	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reason                  	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_is_src_lan              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_color                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_vport                   	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	wan_flow_id                       	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_src_union union */
+			uint32_t	reserved1_data_offset             	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_reason                  	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_is_src_lan              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_color                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_vport                   	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3                         	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_src_union union */
+			uint32_t	reserved2_data_offset             	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_reason                  	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_is_src_lan              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_color                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_vport                   	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ssid                              	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_src_union union */
+			uint32_t	reserved4                         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_src_union union */
+			uint32_t	reserved3_data_offset             	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reason                  	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 3 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	is_exception            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	is_rx_offload           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	is_ucast                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	mcast_tx_prio_union     	:13	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint16_t	cpu_rx_metadata_union   	; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_is_exception            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_is_rx_offload           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_is_ucast                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	mcast_tx_prio                     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint32_t	reserved5                         	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint16_t	dst_ssid_vector                   	; /* Member of cpu_rx_metadata_union union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_is_exception            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_is_rx_offload           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_is_ucast                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved6                         	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint32_t	metadata_0                        	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint32_t	reserved7                         	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint16_t	metadata_1                        	; /* Member of cpu_rx_metadata_union union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_is_exception            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_is_rx_offload           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_is_ucast                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	omci_enc_key_index                	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint32_t	reserved8                         	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint8_t	egress_queue                      	; /* Member of cpu_rx_metadata_union union */
+			uint8_t	wan_flow                          	; /* Member of cpu_rx_metadata_union union */
+		};
+	};
+#else
+	/* Union WORD 0 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	cpu_rx_data_ptr0_union  	; /* This is a field union */
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	host_buffer_data_ptr_low          	; /* Member of cpu_rx_data_ptr0_union union */
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	fpm_idx                           	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_data_ptr0_union union */
+			uint32_t	reserved0                         	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_data_ptr0_union union */
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	bn0                               	:18	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_data_ptr0_union union */
+			uint32_t	reserved9                         	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_data_ptr0_union union */
+		};
+	};
+	/* Union WORD 1 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	is_chksum_verified      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	plen                    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	abs                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1               	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint8_t	host_buffer_data_ptr_hi 	;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_is_chksum_verified      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_plen                    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_abs                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_reserved1               	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint8_t	reserved1_host_buffer_data_ptr_hi 	;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_is_chksum_verified      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_plen                    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_abs                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_reserved1               	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint8_t	reserved2_host_buffer_data_ptr_hi 	;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_reserved2               	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_is_chksum_verified      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_plen                    	:14	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_abs                     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_reserved1               	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint8_t	reserved3_host_buffer_data_ptr_hi 	;
+		};
+	};
+	/* Union WORD 2 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint32_t	reason                  	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	data_offset             	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	cpu_rx_src_union        	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	vport                   	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	color                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	is_src_lan              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint32_t	reserved1_reason                  	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_data_offset             	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	wan_flow_id                       	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_src_union union */
+			uint32_t	reserved1_vport                   	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_color                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_is_src_lan              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint32_t	reserved2_reason                  	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_data_offset             	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3                         	:12	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_src_union union */
+			uint32_t	reserved2_vport                   	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_color                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_is_src_lan              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint32_t	reserved3_reason                  	:6	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_data_offset             	:7	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	ssid                              	:4	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_src_union union */
+			uint32_t	reserved4                         	:8	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of cpu_rx_src_union union */
+			uint32_t	reserved3_vport                   	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_color                   	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_is_src_lan              	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+	/* Union WORD 3 */
+	union{
+		/* Sub Union 0 */
+		struct{
+			uint16_t	cpu_rx_metadata_union   	; /* This is a field union */
+			uint32_t	mcast_tx_prio_union     	:13	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* This is a field union */
+			uint32_t	is_ucast                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	is_rx_offload           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	is_exception            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 1 */
+		struct{
+			uint16_t	dst_ssid_vector                   	; /* Member of cpu_rx_metadata_union union */
+			uint32_t	mcast_tx_prio                     	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint32_t	reserved5                         	:10	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint32_t	reserved1_is_ucast                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_is_rx_offload           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved1_is_exception            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 2 */
+		struct{
+			uint16_t	metadata_1                        	; /* Member of cpu_rx_metadata_union union */
+			uint32_t	reserved6                         	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint32_t	metadata_0                        	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint32_t	reserved7                         	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint32_t	reserved2_is_ucast                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_is_rx_offload           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved2_is_exception            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+		/* Sub Union 3 */
+		struct{
+			uint8_t	egress_queue                      	; /* Member of cpu_rx_metadata_union union */
+			uint8_t	wan_flow                          	; /* Member of cpu_rx_metadata_union union */
+			uint32_t	omci_enc_key_index                	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint32_t	reserved8                         	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__; /* Member of mcast_tx_prio_union union */
+			uint32_t	reserved3_is_ucast                	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_is_rx_offload           	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+			uint32_t	reserved3_is_exception            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		};
+	};
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RX_DESCRIPTOR_DTS;
+
+typedef union
+{
+    uint32_t word_val[4];
+    uint64_t dword_val64[2];
+    RDD_CPU_RX_DESCRIPTOR_DTS fields;
+} CPU_RX_DESCRIPTOR_STRUCT;
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_DATA_PTR0_UNION_READ_G(r, g, idx)            GROUP_MREAD_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS), r)
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_DATA_PTR0_UNION_WRITE_G(v, g, idx)           GROUP_MWRITE_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS), v)
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_DATA_PTR0_UNION_READ(r, p)                   MREAD_32((uint8_t *)p, r)
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_DATA_PTR0_UNION_WRITE(v, p)                  MWRITE_32((uint8_t *)p, v)
+#define RDD_CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_LOW_READ_G(r, g, idx)          GROUP_MREAD_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS), r)
+#define RDD_CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_LOW_WRITE_G(v, g, idx)         GROUP_MWRITE_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS), v)
+#define RDD_CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_LOW_READ(r, p)                 MREAD_32((uint8_t *)p, r)
+#define RDD_CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_LOW_WRITE(v, p)                MWRITE_32((uint8_t *)p, v)
+#define RDD_CPU_RX_DESCRIPTOR_FPM_IDX_READ_G(r, g, idx)                           GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS), 14, 18, r)
+#define RDD_CPU_RX_DESCRIPTOR_FPM_IDX_WRITE_G(v, g, idx)                          GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS), 14, 18, v)
+#define RDD_CPU_RX_DESCRIPTOR_FPM_IDX_READ(r, p)                                  FIELD_MREAD_32((uint8_t *)p, 14, 18, r)
+#define RDD_CPU_RX_DESCRIPTOR_FPM_IDX_WRITE(v, p)                                 FIELD_MWRITE_32((uint8_t *)p, 14, 18, v)
+#define RDD_CPU_RX_DESCRIPTOR_BN0_READ_G(r, g, idx)                               GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS), 14, 18, r)
+#define RDD_CPU_RX_DESCRIPTOR_BN0_WRITE_G(v, g, idx)                              GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS), 14, 18, v)
+#define RDD_CPU_RX_DESCRIPTOR_BN0_READ(r, p)                                      FIELD_MREAD_32((uint8_t *)p, 14, 18, r)
+#define RDD_CPU_RX_DESCRIPTOR_BN0_WRITE(v, p)                                     FIELD_MWRITE_32((uint8_t *)p, 14, 18, v)
+#define RDD_CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_HI_READ_G(r, g, idx)           GROUP_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 4, r)
+#define RDD_CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_HI_WRITE_G(v, g, idx)          GROUP_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 4, v)
+#define RDD_CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_HI_READ(r, p)                  MREAD_8((uint8_t *)p + 4, r)
+#define RDD_CPU_RX_DESCRIPTOR_HOST_BUFFER_DATA_PTR_HI_WRITE(v, p)                 MWRITE_8((uint8_t *)p + 4, v)
+#define RDD_CPU_RX_DESCRIPTOR_ABS_READ_G(r, g, idx)                               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 5, 0, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_ABS_WRITE_G(v, g, idx)                              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 5, 0, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_ABS_READ(r, p)                                      FIELD_MREAD_8((uint8_t *)p + 5, 0, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_ABS_WRITE(v, p)                                     FIELD_MWRITE_8((uint8_t *)p + 5, 0, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_PLEN_READ_G(r, g, idx)                              GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 6, 2, 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_PLEN_WRITE_G(v, g, idx)                             GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 6, 2, 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_PLEN_READ(r, p)                                     FIELD_MREAD_16((uint8_t *)p + 6, 2, 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_PLEN_WRITE(v, p)                                    FIELD_MWRITE_16((uint8_t *)p + 6, 2, 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 7, 1, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 7, 1, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 7, 1, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_CHKSUM_VERIFIED_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 7, 1, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_SRC_LAN_READ_G(r, g, idx)                        GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 7, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_SRC_LAN_WRITE_G(v, g, idx)                       GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 7, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_SRC_LAN_READ(r, p)                               FIELD_MREAD_8((uint8_t *)p + 8, 7, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_SRC_LAN_WRITE(v, p)                              FIELD_MWRITE_8((uint8_t *)p + 8, 7, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_COLOR_READ_G(r, g, idx)                             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 6, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_COLOR_WRITE_G(v, g, idx)                            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 6, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_COLOR_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 8, 6, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_COLOR_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_VPORT_READ_G(r, g, idx)                             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 1, 5, r)
+#define RDD_CPU_RX_DESCRIPTOR_VPORT_WRITE_G(v, g, idx)                            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 1, 5, v)
+#define RDD_CPU_RX_DESCRIPTOR_VPORT_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 8, 1, 5, r)
+#define RDD_CPU_RX_DESCRIPTOR_VPORT_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 8, 1, 5, v)
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_SRC_UNION_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 13, 12, r)
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_SRC_UNION_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 13, 12, v)
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_SRC_UNION_READ(r, p)                         FIELD_MREAD_32((uint8_t *)p + 8, 13, 12, r)
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_SRC_UNION_WRITE(v, p)                        FIELD_MWRITE_32((uint8_t *)p + 8, 13, 12, v)
+#define RDD_CPU_RX_DESCRIPTOR_WAN_FLOW_ID_READ_G(r, g, idx)                       GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 13, 12, r)
+#define RDD_CPU_RX_DESCRIPTOR_WAN_FLOW_ID_WRITE_G(v, g, idx)                      GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 13, 12, v)
+#define RDD_CPU_RX_DESCRIPTOR_WAN_FLOW_ID_READ(r, p)                              FIELD_MREAD_32((uint8_t *)p + 8, 13, 12, r)
+#define RDD_CPU_RX_DESCRIPTOR_WAN_FLOW_ID_WRITE(v, p)                             FIELD_MWRITE_32((uint8_t *)p + 8, 13, 12, v)
+#define RDD_CPU_RX_DESCRIPTOR_SSID_READ_G(r, g, idx)                              GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 5, 4, r)
+#define RDD_CPU_RX_DESCRIPTOR_SSID_WRITE_G(v, g, idx)                             GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 8, 5, 4, v)
+#define RDD_CPU_RX_DESCRIPTOR_SSID_READ(r, p)                                     FIELD_MREAD_16((uint8_t *)p + 8, 5, 4, r)
+#define RDD_CPU_RX_DESCRIPTOR_SSID_WRITE(v, p)                                    FIELD_MWRITE_16((uint8_t *)p + 8, 5, 4, v)
+#define RDD_CPU_RX_DESCRIPTOR_DATA_OFFSET_READ_G(r, g, idx)                       GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 10, 6, 7, r)
+#define RDD_CPU_RX_DESCRIPTOR_DATA_OFFSET_WRITE_G(v, g, idx)                      GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 10, 6, 7, v)
+#define RDD_CPU_RX_DESCRIPTOR_DATA_OFFSET_READ(r, p)                              FIELD_MREAD_16((uint8_t *)p + 10, 6, 7, r)
+#define RDD_CPU_RX_DESCRIPTOR_DATA_OFFSET_WRITE(v, p)                             FIELD_MWRITE_16((uint8_t *)p + 10, 6, 7, v)
+#define RDD_CPU_RX_DESCRIPTOR_REASON_READ_G(r, g, idx)                            GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 11, 0, 6, r)
+#define RDD_CPU_RX_DESCRIPTOR_REASON_WRITE_G(v, g, idx)                           GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 11, 0, 6, v)
+#define RDD_CPU_RX_DESCRIPTOR_REASON_READ(r, p)                                   FIELD_MREAD_8((uint8_t *)p + 11, 0, 6, r)
+#define RDD_CPU_RX_DESCRIPTOR_REASON_WRITE(v, p)                                  FIELD_MWRITE_8((uint8_t *)p + 11, 0, 6, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_EXCEPTION_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 7, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_EXCEPTION_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 7, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_EXCEPTION_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 12, 7, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_EXCEPTION_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_RX_OFFLOAD_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 6, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_RX_OFFLOAD_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 6, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_RX_OFFLOAD_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 12, 6, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_RX_OFFLOAD_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 12, 6, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_UCAST_READ_G(r, g, idx)                          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 5, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_UCAST_WRITE_G(v, g, idx)                         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 5, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_IS_UCAST_READ(r, p)                                 FIELD_MREAD_8((uint8_t *)p + 12, 5, 1, r)
+#define RDD_CPU_RX_DESCRIPTOR_IS_UCAST_WRITE(v, p)                                FIELD_MWRITE_8((uint8_t *)p + 12, 5, 1, v)
+#define RDD_CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_UNION_READ_G(r, g, idx)               GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 0, 13, r)
+#define RDD_CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_UNION_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 0, 13, v)
+#define RDD_CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_UNION_READ(r, p)                      FIELD_MREAD_16((uint8_t *)p + 12, 0, 13, r)
+#define RDD_CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_UNION_WRITE(v, p)                     FIELD_MWRITE_16((uint8_t *)p + 12, 0, 13, v)
+#define RDD_CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 2, 3, r)
+#define RDD_CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 2, 3, v)
+#define RDD_CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p + 12, 2, 3, r)
+#define RDD_CPU_RX_DESCRIPTOR_MCAST_TX_PRIO_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 12, 2, 3, v)
+#define RDD_CPU_RX_DESCRIPTOR_METADATA_0_READ_G(r, g, idx)                        GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 5, 5, r)
+#define RDD_CPU_RX_DESCRIPTOR_METADATA_0_WRITE_G(v, g, idx)                       GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 5, 5, v)
+#define RDD_CPU_RX_DESCRIPTOR_METADATA_0_READ(r, p)                               FIELD_MREAD_16((uint8_t *)p + 12, 5, 5, r)
+#define RDD_CPU_RX_DESCRIPTOR_METADATA_0_WRITE(v, p)                              FIELD_MWRITE_16((uint8_t *)p + 12, 5, 5, v)
+#define RDD_CPU_RX_DESCRIPTOR_OMCI_ENC_KEY_INDEX_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 3, 2, r)
+#define RDD_CPU_RX_DESCRIPTOR_OMCI_ENC_KEY_INDEX_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 12, 3, 2, v)
+#define RDD_CPU_RX_DESCRIPTOR_OMCI_ENC_KEY_INDEX_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p + 12, 3, 2, r)
+#define RDD_CPU_RX_DESCRIPTOR_OMCI_ENC_KEY_INDEX_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p + 12, 3, 2, v)
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_METADATA_UNION_READ_G(r, g, idx)             GROUP_MREAD_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_METADATA_UNION_WRITE_G(v, g, idx)            GROUP_MWRITE_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_METADATA_UNION_READ(r, p)                    MREAD_16((uint8_t *)p + 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_CPU_RX_METADATA_UNION_WRITE(v, p)                   MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_DST_SSID_VECTOR_READ_G(r, g, idx)                   GROUP_MREAD_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_DST_SSID_VECTOR_WRITE_G(v, g, idx)                  GROUP_MWRITE_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_DST_SSID_VECTOR_READ(r, p)                          MREAD_16((uint8_t *)p + 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_DST_SSID_VECTOR_WRITE(v, p)                         MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_METADATA_1_READ_G(r, g, idx)                        GROUP_MREAD_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_METADATA_1_WRITE_G(v, g, idx)                       GROUP_MWRITE_16(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_METADATA_1_READ(r, p)                               MREAD_16((uint8_t *)p + 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_METADATA_1_WRITE(v, p)                              MWRITE_16((uint8_t *)p + 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_EGRESS_QUEUE_READ_G(r, g, idx)                      GROUP_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_EGRESS_QUEUE_WRITE_G(v, g, idx)                     GROUP_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_EGRESS_QUEUE_READ(r, p)                             MREAD_8((uint8_t *)p + 14, r)
+#define RDD_CPU_RX_DESCRIPTOR_EGRESS_QUEUE_WRITE(v, p)                            MWRITE_8((uint8_t *)p + 14, v)
+#define RDD_CPU_RX_DESCRIPTOR_WAN_FLOW_READ_G(r, g, idx)                          GROUP_MREAD_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 15, r)
+#define RDD_CPU_RX_DESCRIPTOR_WAN_FLOW_WRITE_G(v, g, idx)                         GROUP_MWRITE_8(g, idx*sizeof(RDD_CPU_RX_DESCRIPTOR_DTS) + 15, v)
+#define RDD_CPU_RX_DESCRIPTOR_WAN_FLOW_READ(r, p)                                 MREAD_8((uint8_t *)p + 15, r)
+#define RDD_CPU_RX_DESCRIPTOR_WAN_FLOW_WRITE(v, p)                                MWRITE_8((uint8_t *)p + 15, v)
+/* <<<RDD_CPU_RX_DESCRIPTOR_DTS */
+
+/* <<<RDD_CPU_RX_DESCRIPTOR */
+
+
+/* >>>RDD_CPU_FEED_DESCRIPTOR */
+#define CPU_FEED_DESCRIPTOR_PTR_LOW_F_OFFSET                          0
+#define CPU_FEED_DESCRIPTOR_PTR_LOW_F_WIDTH                           32
+#define CPU_FEED_DESCRIPTOR_CPU_FEED_DESCRIPTOR_OFFSET                0
+#define CPU_FEED_DESCRIPTOR_PTR_LOW_OFFSET                            0
+#define CPU_FEED_DESCRIPTOR_PTR_LOW_WORD_OFFSET                       0
+#define CPU_FEED_DESCRIPTOR_TYPE_F_OFFSET                             8
+#define CPU_FEED_DESCRIPTOR_TYPE_F_WIDTH                              1
+#define CPU_FEED_DESCRIPTOR_TYPE_OFFSET                               6
+#define CPU_FEED_DESCRIPTOR_TYPE_WORD_OFFSET                          1
+#define CPU_FEED_DESCRIPTOR_TYPE_F_OFFSET_MOD8                        0
+#define CPU_FEED_DESCRIPTOR_TYPE_F_OFFSET_MOD16                       8
+#define CPU_FEED_DESCRIPTOR_PTR_HI_F_OFFSET                           0
+#define CPU_FEED_DESCRIPTOR_PTR_HI_F_WIDTH                            8
+#define CPU_FEED_DESCRIPTOR_PTR_HI_OFFSET                             7
+#define CPU_FEED_DESCRIPTOR_PTR_HI_WORD_OFFSET                        1
+#define CPU_FEED_DESCRIPTOR_PTR_HI_F_OFFSET_MOD16                     0
+
+/* >>>RDD_CPU_FEED_DESCRIPTOR_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	ptr_low   	;
+	uint32_t	reserved0 	:23	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	type      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint8_t	ptr_hi    	;
+#else
+	uint32_t	ptr_low   	;
+	uint8_t	ptr_hi    	;
+	uint32_t	type      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved0 	:23	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_FEED_DESCRIPTOR_DTS;
+
+typedef union
+{
+    uint32_t word_val[2];
+    uint64_t dword_val64[1];
+    RDD_CPU_FEED_DESCRIPTOR_DTS fields;
+} CPU_FEED_DESCRIPTOR_STRUCT;
+#define RDD_CPU_FEED_DESCRIPTOR_PTR_LOW_READ_G(r, g, idx)            GROUP_MREAD_32(g, idx*sizeof(RDD_CPU_FEED_DESCRIPTOR_DTS), r)
+#define RDD_CPU_FEED_DESCRIPTOR_PTR_LOW_WRITE_G(v, g, idx)           GROUP_MWRITE_32(g, idx*sizeof(RDD_CPU_FEED_DESCRIPTOR_DTS), v)
+#define RDD_CPU_FEED_DESCRIPTOR_PTR_LOW_READ(r, p)                   MREAD_32((uint8_t *)p, r)
+#define RDD_CPU_FEED_DESCRIPTOR_PTR_LOW_WRITE(v, p)                  MWRITE_32((uint8_t *)p, v)
+#define RDD_CPU_FEED_DESCRIPTOR_TYPE_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_FEED_DESCRIPTOR_DTS) + 6, 0, 1, r)
+#define RDD_CPU_FEED_DESCRIPTOR_TYPE_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_FEED_DESCRIPTOR_DTS) + 6, 0, 1, v)
+#define RDD_CPU_FEED_DESCRIPTOR_TYPE_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 6, 0, 1, r)
+#define RDD_CPU_FEED_DESCRIPTOR_TYPE_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 6, 0, 1, v)
+#define RDD_CPU_FEED_DESCRIPTOR_PTR_HI_READ_G(r, g, idx)             GROUP_MREAD_8(g, idx*sizeof(RDD_CPU_FEED_DESCRIPTOR_DTS) + 7, r)
+#define RDD_CPU_FEED_DESCRIPTOR_PTR_HI_WRITE_G(v, g, idx)            GROUP_MWRITE_8(g, idx*sizeof(RDD_CPU_FEED_DESCRIPTOR_DTS) + 7, v)
+#define RDD_CPU_FEED_DESCRIPTOR_PTR_HI_READ(r, p)                    MREAD_8((uint8_t *)p + 7, r)
+#define RDD_CPU_FEED_DESCRIPTOR_PTR_HI_WRITE(v, p)                   MWRITE_8((uint8_t *)p + 7, v)
+/* <<<RDD_CPU_FEED_DESCRIPTOR_DTS */
+
+/* <<<RDD_CPU_FEED_DESCRIPTOR */
+
+
+/* >>>RDD_CPU_RING_DESCRIPTOR */
+#define CPU_RING_DESCRIPTOR_SIZE_OF_ENTRY_F_OFFSET                    27
+#define CPU_RING_DESCRIPTOR_SIZE_OF_ENTRY_F_WIDTH                     5
+#define CPU_RING_DESCRIPTOR_CPU_RING_DESCRIPTOR_OFFSET                0
+#define CPU_RING_DESCRIPTOR_SIZE_OF_ENTRY_OFFSET                      0
+#define CPU_RING_DESCRIPTOR_SIZE_OF_ENTRY_WORD_OFFSET                 0
+#define CPU_RING_DESCRIPTOR_SIZE_OF_ENTRY_F_OFFSET_MOD8               3
+#define CPU_RING_DESCRIPTOR_SIZE_OF_ENTRY_F_OFFSET_MOD16              11
+#define CPU_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_F_OFFSET                16
+#define CPU_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_F_WIDTH                 11
+#define CPU_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_OFFSET                  0
+#define CPU_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_WORD_OFFSET             0
+#define CPU_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_F_OFFSET_MOD16          0
+#define CPU_RING_DESCRIPTOR_INTERRUPT_ID_F_OFFSET                     0
+#define CPU_RING_DESCRIPTOR_INTERRUPT_ID_F_WIDTH                      16
+#define CPU_RING_DESCRIPTOR_INTERRUPT_ID_OFFSET                       2
+#define CPU_RING_DESCRIPTOR_INTERRUPT_ID_WORD_OFFSET                  0
+#define CPU_RING_DESCRIPTOR_DROP_COUNTER_F_OFFSET                     16
+#define CPU_RING_DESCRIPTOR_DROP_COUNTER_F_WIDTH                      16
+#define CPU_RING_DESCRIPTOR_DROP_COUNTER_OFFSET                       4
+#define CPU_RING_DESCRIPTOR_DROP_COUNTER_WORD_OFFSET                  1
+#define CPU_RING_DESCRIPTOR_WRITE_IDX_F_OFFSET                        0
+#define CPU_RING_DESCRIPTOR_WRITE_IDX_F_WIDTH                         16
+#define CPU_RING_DESCRIPTOR_WRITE_IDX_OFFSET                          6
+#define CPU_RING_DESCRIPTOR_WRITE_IDX_WORD_OFFSET                     1
+#define CPU_RING_DESCRIPTOR_BASE_ADDR_LOW_F_OFFSET                    0
+#define CPU_RING_DESCRIPTOR_BASE_ADDR_LOW_F_WIDTH                     32
+#define CPU_RING_DESCRIPTOR_BASE_ADDR_LOW_OFFSET                      8
+#define CPU_RING_DESCRIPTOR_BASE_ADDR_LOW_WORD_OFFSET                 2
+#define CPU_RING_DESCRIPTOR_READ_IDX_F_OFFSET                         16
+#define CPU_RING_DESCRIPTOR_READ_IDX_F_WIDTH                          16
+#define CPU_RING_DESCRIPTOR_READ_IDX_OFFSET                           12
+#define CPU_RING_DESCRIPTOR_READ_IDX_WORD_OFFSET                      3
+#define CPU_RING_DESCRIPTOR_BASE_ADDR_HIGH_F_OFFSET                   0
+#define CPU_RING_DESCRIPTOR_BASE_ADDR_HIGH_F_WIDTH                    8
+#define CPU_RING_DESCRIPTOR_BASE_ADDR_HIGH_OFFSET                     15
+#define CPU_RING_DESCRIPTOR_BASE_ADDR_HIGH_WORD_OFFSET                3
+#define CPU_RING_DESCRIPTOR_BASE_ADDR_HIGH_F_OFFSET_MOD16             0
+
+/* >>>RDD_CPU_RING_DESCRIPTOR_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	size_of_entry    	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	number_of_entries	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	interrupt_id     	;
+	uint16_t	drop_counter     	;
+	uint16_t	write_idx        	;
+	uint32_t	base_addr_low    	;
+	uint16_t	read_idx         	;
+	uint8_t	reserved0        	;
+	uint8_t	base_addr_high   	;
+#else
+	uint16_t	interrupt_id     	;
+	uint32_t	number_of_entries	:11	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	size_of_entry    	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint16_t	write_idx        	;
+	uint16_t	drop_counter     	;
+	uint32_t	base_addr_low    	;
+	uint8_t	base_addr_high   	;
+	uint8_t	reserved0        	;
+	uint16_t	read_idx         	;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_CPU_RING_DESCRIPTOR_DTS;
+
+typedef union
+{
+    uint32_t word_val[4];
+    uint64_t dword_val64[2];
+    RDD_CPU_RING_DESCRIPTOR_DTS fields;
+} CPU_RING_DESCRIPTOR_STRUCT;
+#define RDD_CPU_RING_DESCRIPTOR_SIZE_OF_ENTRY_READ_G(r, g, idx)              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS), 3, 5, r)
+#define RDD_CPU_RING_DESCRIPTOR_SIZE_OF_ENTRY_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS), 3, 5, v)
+#define RDD_CPU_RING_DESCRIPTOR_SIZE_OF_ENTRY_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p, 3, 5, r)
+#define RDD_CPU_RING_DESCRIPTOR_SIZE_OF_ENTRY_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p, 3, 5, v)
+#define RDD_CPU_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_READ_G(r, g, idx)          GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS), 0, 11, r)
+#define RDD_CPU_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS), 0, 11, v)
+#define RDD_CPU_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_READ(r, p)                 FIELD_MREAD_16((uint8_t *)p, 0, 11, r)
+#define RDD_CPU_RING_DESCRIPTOR_NUMBER_OF_ENTRIES_WRITE(v, p)                FIELD_MWRITE_16((uint8_t *)p, 0, 11, v)
+#define RDD_CPU_RING_DESCRIPTOR_INTERRUPT_ID_READ_G(r, g, idx)               GROUP_MREAD_16(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 2, r)
+#define RDD_CPU_RING_DESCRIPTOR_INTERRUPT_ID_WRITE_G(v, g, idx)              GROUP_MWRITE_16(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 2, v)
+#define RDD_CPU_RING_DESCRIPTOR_INTERRUPT_ID_READ(r, p)                      MREAD_16((uint8_t *)p + 2, r)
+#define RDD_CPU_RING_DESCRIPTOR_INTERRUPT_ID_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 2, v)
+#define RDD_CPU_RING_DESCRIPTOR_DROP_COUNTER_READ_G(r, g, idx)               GROUP_MREAD_16(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 4, r)
+#define RDD_CPU_RING_DESCRIPTOR_DROP_COUNTER_WRITE_G(v, g, idx)              GROUP_MWRITE_16(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 4, v)
+#define RDD_CPU_RING_DESCRIPTOR_DROP_COUNTER_READ(r, p)                      MREAD_16((uint8_t *)p + 4, r)
+#define RDD_CPU_RING_DESCRIPTOR_DROP_COUNTER_WRITE(v, p)                     MWRITE_16((uint8_t *)p + 4, v)
+#define RDD_CPU_RING_DESCRIPTOR_WRITE_IDX_READ_G(r, g, idx)                  GROUP_MREAD_16(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 6, r)
+#define RDD_CPU_RING_DESCRIPTOR_WRITE_IDX_WRITE_G(v, g, idx)                 GROUP_MWRITE_16(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 6, v)
+#define RDD_CPU_RING_DESCRIPTOR_WRITE_IDX_READ(r, p)                         MREAD_16((uint8_t *)p + 6, r)
+#define RDD_CPU_RING_DESCRIPTOR_WRITE_IDX_WRITE(v, p)                        MWRITE_16((uint8_t *)p + 6, v)
+#define RDD_CPU_RING_DESCRIPTOR_BASE_ADDR_LOW_READ_G(r, g, idx)              GROUP_MREAD_32(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 8, r)
+#define RDD_CPU_RING_DESCRIPTOR_BASE_ADDR_LOW_WRITE_G(v, g, idx)             GROUP_MWRITE_32(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 8, v)
+#define RDD_CPU_RING_DESCRIPTOR_BASE_ADDR_LOW_READ(r, p)                     MREAD_32((uint8_t *)p + 8, r)
+#define RDD_CPU_RING_DESCRIPTOR_BASE_ADDR_LOW_WRITE(v, p)                    MWRITE_32((uint8_t *)p + 8, v)
+#define RDD_CPU_RING_DESCRIPTOR_READ_IDX_READ_G(r, g, idx)                   GROUP_MREAD_16(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 12, r)
+#define RDD_CPU_RING_DESCRIPTOR_READ_IDX_WRITE_G(v, g, idx)                  GROUP_MWRITE_16(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 12, v)
+#define RDD_CPU_RING_DESCRIPTOR_READ_IDX_READ(r, p)                          MREAD_16((uint8_t *)p + 12, r)
+#define RDD_CPU_RING_DESCRIPTOR_READ_IDX_WRITE(v, p)                         MWRITE_16((uint8_t *)p + 12, v)
+#define RDD_CPU_RING_DESCRIPTOR_BASE_ADDR_HIGH_READ_G(r, g, idx)             GROUP_MREAD_8(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 15, r)
+#define RDD_CPU_RING_DESCRIPTOR_BASE_ADDR_HIGH_WRITE_G(v, g, idx)            GROUP_MWRITE_8(g, idx*sizeof(RDD_CPU_RING_DESCRIPTOR_DTS) + 15, v)
+#define RDD_CPU_RING_DESCRIPTOR_BASE_ADDR_HIGH_READ(r, p)                    MREAD_8((uint8_t *)p + 15, r)
+#define RDD_CPU_RING_DESCRIPTOR_BASE_ADDR_HIGH_WRITE(v, p)                   MWRITE_8((uint8_t *)p + 15, v)
+/* <<<RDD_CPU_RING_DESCRIPTOR_DTS */
+
+/* <<<RDD_CPU_RING_DESCRIPTOR */
+
+
+/* >>>RDD_PERIPHERALS_STS */
+#define PERIPHERALS_STS_SCHEDULER_DEBUG_F_OFFSET                  27
+#define PERIPHERALS_STS_SCHEDULER_DEBUG_F_WIDTH                   5
+#define PERIPHERALS_STS_PERIPHERALS_STS_OFFSET                    0
+#define PERIPHERALS_STS_SCHEDULER_DEBUG_OFFSET                    0
+#define PERIPHERALS_STS_SCHEDULER_DEBUG_WORD_OFFSET               0
+#define PERIPHERALS_STS_SCHEDULER_DEBUG_F_OFFSET_MOD8             3
+#define PERIPHERALS_STS_SCHEDULER_DEBUG_F_OFFSET_MOD16            11
+#define PERIPHERALS_STS_NEXT_THREAD_IS_READY_F_OFFSET             26
+#define PERIPHERALS_STS_NEXT_THREAD_IS_READY_F_WIDTH              1
+#define PERIPHERALS_STS_NEXT_THREAD_IS_READY_OFFSET               0
+#define PERIPHERALS_STS_NEXT_THREAD_IS_READY_WORD_OFFSET          0
+#define PERIPHERALS_STS_NEXT_THREAD_IS_READY_F_OFFSET_MOD8        2
+#define PERIPHERALS_STS_NEXT_THREAD_IS_READY_F_OFFSET_MOD16       10
+#define PERIPHERALS_STS_NEXT_THREAD_NUMBER_F_OFFSET               21
+#define PERIPHERALS_STS_NEXT_THREAD_NUMBER_F_WIDTH                5
+#define PERIPHERALS_STS_NEXT_THREAD_NUMBER_OFFSET                 0
+#define PERIPHERALS_STS_NEXT_THREAD_NUMBER_WORD_OFFSET            0
+#define PERIPHERALS_STS_NEXT_THREAD_NUMBER_F_OFFSET_MOD8          5
+#define PERIPHERALS_STS_NEXT_THREAD_NUMBER_F_OFFSET_MOD16         5
+#define PERIPHERALS_STS_CURRENT_THREAD_NUMBER_F_OFFSET            16
+#define PERIPHERALS_STS_CURRENT_THREAD_NUMBER_F_WIDTH             5
+#define PERIPHERALS_STS_CURRENT_THREAD_NUMBER_OFFSET              1
+#define PERIPHERALS_STS_CURRENT_THREAD_NUMBER_WORD_OFFSET         0
+#define PERIPHERALS_STS_CURRENT_THREAD_NUMBER_F_OFFSET_MOD8       0
+#define PERIPHERALS_STS_CURRENT_THREAD_NUMBER_F_OFFSET_MOD16      0
+#define PERIPHERALS_STS_TIMER_1_STATUS_F_OFFSET                   12
+#define PERIPHERALS_STS_TIMER_1_STATUS_F_WIDTH                    1
+#define PERIPHERALS_STS_TIMER_1_STATUS_OFFSET                     2
+#define PERIPHERALS_STS_TIMER_1_STATUS_WORD_OFFSET                0
+#define PERIPHERALS_STS_TIMER_1_STATUS_F_OFFSET_MOD8              4
+#define PERIPHERALS_STS_TIMER_1_STATUS_F_OFFSET_MOD16             12
+#define PERIPHERALS_STS_TIMER_0_STATUS_F_OFFSET                   11
+#define PERIPHERALS_STS_TIMER_0_STATUS_F_WIDTH                    1
+#define PERIPHERALS_STS_TIMER_0_STATUS_OFFSET                     2
+#define PERIPHERALS_STS_TIMER_0_STATUS_WORD_OFFSET                0
+#define PERIPHERALS_STS_TIMER_0_STATUS_F_OFFSET_MOD8              3
+#define PERIPHERALS_STS_TIMER_0_STATUS_F_OFFSET_MOD16             11
+#define PERIPHERALS_STS_RAM_READ_COMMAND_FIFO_FULL_F_OFFSET       8
+#define PERIPHERALS_STS_RAM_READ_COMMAND_FIFO_FULL_F_WIDTH        1
+#define PERIPHERALS_STS_RAM_READ_COMMAND_FIFO_FULL_OFFSET         2
+#define PERIPHERALS_STS_RAM_READ_COMMAND_FIFO_FULL_WORD_OFFSET    0
+#define PERIPHERALS_STS_RAM_READ_COMMAND_FIFO_FULL_F_OFFSET_MOD8  0
+#define PERIPHERALS_STS_RAM_READ_COMMAND_FIFO_FULL_F_OFFSET_MOD16 8
+#define PERIPHERALS_STS_QUAD_ID_F_OFFSET                          6
+#define PERIPHERALS_STS_QUAD_ID_F_WIDTH                           2
+#define PERIPHERALS_STS_QUAD_ID_OFFSET                            3
+#define PERIPHERALS_STS_QUAD_ID_WORD_OFFSET                       0
+#define PERIPHERALS_STS_QUAD_ID_F_OFFSET_MOD8                     6
+#define PERIPHERALS_STS_QUAD_ID_F_OFFSET_MOD16                    6
+#define PERIPHERALS_STS_CORE_ID_F_OFFSET                          4
+#define PERIPHERALS_STS_CORE_ID_F_WIDTH                           2
+#define PERIPHERALS_STS_CORE_ID_OFFSET                            3
+#define PERIPHERALS_STS_CORE_ID_WORD_OFFSET                       0
+#define PERIPHERALS_STS_CORE_ID_F_OFFSET_MOD8                     4
+#define PERIPHERALS_STS_CORE_ID_F_OFFSET_MOD16                    4
+#define PERIPHERALS_STS_BB_MESSAGE_PENDING_F_OFFSET               3
+#define PERIPHERALS_STS_BB_MESSAGE_PENDING_F_WIDTH                1
+#define PERIPHERALS_STS_BB_MESSAGE_PENDING_OFFSET                 3
+#define PERIPHERALS_STS_BB_MESSAGE_PENDING_WORD_OFFSET            0
+#define PERIPHERALS_STS_BB_MESSAGE_PENDING_F_OFFSET_MOD8          3
+#define PERIPHERALS_STS_BB_MESSAGE_PENDING_F_OFFSET_MOD16         3
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_IS_EMPTY_F_OFFSET       2
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_IS_EMPTY_F_WIDTH        1
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_IS_EMPTY_OFFSET         3
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_IS_EMPTY_WORD_OFFSET    0
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_IS_EMPTY_F_OFFSET_MOD8  2
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_IS_EMPTY_F_OFFSET_MOD16 2
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_FULL_F_OFFSET           1
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_FULL_F_WIDTH            1
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_FULL_OFFSET             3
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_FULL_WORD_OFFSET        0
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_FULL_F_OFFSET_MOD8      1
+#define PERIPHERALS_STS_BBTX_COMMAND_FIFO_FULL_F_OFFSET_MOD16     1
+#define PERIPHERALS_STS_DMA_COMMAND_FIFO_FULL_F_OFFSET            0
+#define PERIPHERALS_STS_DMA_COMMAND_FIFO_FULL_F_WIDTH             1
+#define PERIPHERALS_STS_DMA_COMMAND_FIFO_FULL_OFFSET              3
+#define PERIPHERALS_STS_DMA_COMMAND_FIFO_FULL_WORD_OFFSET         0
+#define PERIPHERALS_STS_DMA_COMMAND_FIFO_FULL_F_OFFSET_MOD8       0
+#define PERIPHERALS_STS_DMA_COMMAND_FIFO_FULL_F_OFFSET_MOD16      0
+
+/* >>>RDD_PERIPHERALS_STS_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	scheduler_debug           	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	next_thread_is_ready      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	next_thread_number        	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	current_thread_number     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_1                	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	timer_1_status            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	timer_0_status            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_2                	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ram_read_command_fifo_full	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	quad_id                   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	core_id                   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bb_message_pending        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbtx_command_fifo_is_empty	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbtx_command_fifo_full    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	dma_command_fifo_full     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#else
+	uint32_t	dma_command_fifo_full     	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbtx_command_fifo_full    	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bbtx_command_fifo_is_empty	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	bb_message_pending        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	core_id                   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	quad_id                   	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	ram_read_command_fifo_full	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_2                	:2	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	timer_0_status            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	timer_1_status            	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	reserved_1                	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	current_thread_number     	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	next_thread_number        	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	next_thread_is_ready      	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	scheduler_debug           	:5	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_PERIPHERALS_STS_DTS;
+
+typedef union
+{
+    uint32_t word_val[1];
+    RDD_PERIPHERALS_STS_DTS fields;
+} PERIPHERALS_STS_STRUCT;
+#define RDD_PERIPHERALS_STS_SCHEDULER_DEBUG_READ_G(r, g, idx)                     GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS), 3, 5, r)
+#define RDD_PERIPHERALS_STS_SCHEDULER_DEBUG_WRITE_G(v, g, idx)                    GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS), 3, 5, v)
+#define RDD_PERIPHERALS_STS_SCHEDULER_DEBUG_READ(r, p)                            FIELD_MREAD_8((uint8_t *)p, 3, 5, r)
+#define RDD_PERIPHERALS_STS_SCHEDULER_DEBUG_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p, 3, 5, v)
+#define RDD_PERIPHERALS_STS_NEXT_THREAD_IS_READY_READ_G(r, g, idx)                GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS), 2, 1, r)
+#define RDD_PERIPHERALS_STS_NEXT_THREAD_IS_READY_WRITE_G(v, g, idx)               GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS), 2, 1, v)
+#define RDD_PERIPHERALS_STS_NEXT_THREAD_IS_READY_READ(r, p)                       FIELD_MREAD_8((uint8_t *)p, 2, 1, r)
+#define RDD_PERIPHERALS_STS_NEXT_THREAD_IS_READY_WRITE(v, p)                      FIELD_MWRITE_8((uint8_t *)p, 2, 1, v)
+#define RDD_PERIPHERALS_STS_NEXT_THREAD_NUMBER_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_16(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS), 5, 5, r)
+#define RDD_PERIPHERALS_STS_NEXT_THREAD_NUMBER_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_16(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS), 5, 5, v)
+#define RDD_PERIPHERALS_STS_NEXT_THREAD_NUMBER_READ(r, p)                         FIELD_MREAD_16((uint8_t *)p, 5, 5, r)
+#define RDD_PERIPHERALS_STS_NEXT_THREAD_NUMBER_WRITE(v, p)                        FIELD_MWRITE_16((uint8_t *)p, 5, 5, v)
+#define RDD_PERIPHERALS_STS_CURRENT_THREAD_NUMBER_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 1, 0, 5, r)
+#define RDD_PERIPHERALS_STS_CURRENT_THREAD_NUMBER_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 1, 0, 5, v)
+#define RDD_PERIPHERALS_STS_CURRENT_THREAD_NUMBER_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 1, 0, 5, r)
+#define RDD_PERIPHERALS_STS_CURRENT_THREAD_NUMBER_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 1, 0, 5, v)
+#define RDD_PERIPHERALS_STS_TIMER_1_STATUS_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 2, 4, 1, r)
+#define RDD_PERIPHERALS_STS_TIMER_1_STATUS_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 2, 4, 1, v)
+#define RDD_PERIPHERALS_STS_TIMER_1_STATUS_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 2, 4, 1, r)
+#define RDD_PERIPHERALS_STS_TIMER_1_STATUS_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 2, 4, 1, v)
+#define RDD_PERIPHERALS_STS_TIMER_0_STATUS_READ_G(r, g, idx)                      GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 2, 3, 1, r)
+#define RDD_PERIPHERALS_STS_TIMER_0_STATUS_WRITE_G(v, g, idx)                     GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 2, 3, 1, v)
+#define RDD_PERIPHERALS_STS_TIMER_0_STATUS_READ(r, p)                             FIELD_MREAD_8((uint8_t *)p + 2, 3, 1, r)
+#define RDD_PERIPHERALS_STS_TIMER_0_STATUS_WRITE(v, p)                            FIELD_MWRITE_8((uint8_t *)p + 2, 3, 1, v)
+#define RDD_PERIPHERALS_STS_RAM_READ_COMMAND_FIFO_FULL_READ_G(r, g, idx)          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 2, 0, 1, r)
+#define RDD_PERIPHERALS_STS_RAM_READ_COMMAND_FIFO_FULL_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 2, 0, 1, v)
+#define RDD_PERIPHERALS_STS_RAM_READ_COMMAND_FIFO_FULL_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 2, 0, 1, r)
+#define RDD_PERIPHERALS_STS_RAM_READ_COMMAND_FIFO_FULL_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 2, 0, 1, v)
+#define RDD_PERIPHERALS_STS_QUAD_ID_READ_G(r, g, idx)                             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 6, 2, r)
+#define RDD_PERIPHERALS_STS_QUAD_ID_WRITE_G(v, g, idx)                            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 6, 2, v)
+#define RDD_PERIPHERALS_STS_QUAD_ID_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 3, 6, 2, r)
+#define RDD_PERIPHERALS_STS_QUAD_ID_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 3, 6, 2, v)
+#define RDD_PERIPHERALS_STS_CORE_ID_READ_G(r, g, idx)                             GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 4, 2, r)
+#define RDD_PERIPHERALS_STS_CORE_ID_WRITE_G(v, g, idx)                            GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 4, 2, v)
+#define RDD_PERIPHERALS_STS_CORE_ID_READ(r, p)                                    FIELD_MREAD_8((uint8_t *)p + 3, 4, 2, r)
+#define RDD_PERIPHERALS_STS_CORE_ID_WRITE(v, p)                                   FIELD_MWRITE_8((uint8_t *)p + 3, 4, 2, v)
+#define RDD_PERIPHERALS_STS_BB_MESSAGE_PENDING_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 3, 1, r)
+#define RDD_PERIPHERALS_STS_BB_MESSAGE_PENDING_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 3, 1, v)
+#define RDD_PERIPHERALS_STS_BB_MESSAGE_PENDING_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 3, 3, 1, r)
+#define RDD_PERIPHERALS_STS_BB_MESSAGE_PENDING_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 3, 3, 1, v)
+#define RDD_PERIPHERALS_STS_BBTX_COMMAND_FIFO_IS_EMPTY_READ_G(r, g, idx)          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 2, 1, r)
+#define RDD_PERIPHERALS_STS_BBTX_COMMAND_FIFO_IS_EMPTY_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 2, 1, v)
+#define RDD_PERIPHERALS_STS_BBTX_COMMAND_FIFO_IS_EMPTY_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 3, 2, 1, r)
+#define RDD_PERIPHERALS_STS_BBTX_COMMAND_FIFO_IS_EMPTY_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 3, 2, 1, v)
+#define RDD_PERIPHERALS_STS_BBTX_COMMAND_FIFO_FULL_READ_G(r, g, idx)              GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 1, 1, r)
+#define RDD_PERIPHERALS_STS_BBTX_COMMAND_FIFO_FULL_WRITE_G(v, g, idx)             GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 1, 1, v)
+#define RDD_PERIPHERALS_STS_BBTX_COMMAND_FIFO_FULL_READ(r, p)                     FIELD_MREAD_8((uint8_t *)p + 3, 1, 1, r)
+#define RDD_PERIPHERALS_STS_BBTX_COMMAND_FIFO_FULL_WRITE(v, p)                    FIELD_MWRITE_8((uint8_t *)p + 3, 1, 1, v)
+#define RDD_PERIPHERALS_STS_DMA_COMMAND_FIFO_FULL_READ_G(r, g, idx)               GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 0, 1, r)
+#define RDD_PERIPHERALS_STS_DMA_COMMAND_FIFO_FULL_WRITE_G(v, g, idx)              GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_PERIPHERALS_STS_DTS) + 3, 0, 1, v)
+#define RDD_PERIPHERALS_STS_DMA_COMMAND_FIFO_FULL_READ(r, p)                      FIELD_MREAD_8((uint8_t *)p + 3, 0, 1, r)
+#define RDD_PERIPHERALS_STS_DMA_COMMAND_FIFO_FULL_WRITE(v, p)                     FIELD_MWRITE_8((uint8_t *)p + 3, 0, 1, v)
+/* <<<RDD_PERIPHERALS_STS_DTS */
+
+/* <<<RDD_PERIPHERALS_STS */
+
+
+/* >>>RDD_HASH_COMMAND */
+#define HASH_COMMAND_KEY_1_F_OFFSET                            0
+#define HASH_COMMAND_KEY_1_F_WIDTH                             32
+#define HASH_COMMAND_HASH_COMMAND_OFFSET                       0
+#define HASH_COMMAND_KEY_1_OFFSET                              0
+#define HASH_COMMAND_KEY_1_WORD_OFFSET                         0
+#define HASH_COMMAND_KEY_0_F_OFFSET                            4
+#define HASH_COMMAND_KEY_0_F_WIDTH                             28
+#define HASH_COMMAND_KEY_0_OFFSET                              4
+#define HASH_COMMAND_KEY_0_WORD_OFFSET                         1
+#define HASH_COMMAND_CONFIGURATION_F_OFFSET                    1
+#define HASH_COMMAND_CONFIGURATION_F_WIDTH                     3
+#define HASH_COMMAND_CONFIGURATION_OFFSET                      7
+#define HASH_COMMAND_CONFIGURATION_WORD_OFFSET                 1
+#define HASH_COMMAND_CONFIGURATION_F_OFFSET_MOD8               1
+#define HASH_COMMAND_CONFIGURATION_F_OFFSET_MOD16              1
+#define HASH_COMMAND_AGING_F_OFFSET                            0
+#define HASH_COMMAND_AGING_F_WIDTH                             1
+#define HASH_COMMAND_AGING_OFFSET                              7
+#define HASH_COMMAND_AGING_WORD_OFFSET                         1
+#define HASH_COMMAND_AGING_F_OFFSET_MOD8                       0
+#define HASH_COMMAND_AGING_F_OFFSET_MOD16                      0
+
+/* >>>RDD_HASH_COMMAND_DTS */
+
+typedef struct
+{
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	uint32_t	key_1        	;
+	uint32_t	key_0        	:28	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	configuration	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	aging        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#else
+	uint32_t	key_1        	;
+	uint32_t	aging        	:1	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	configuration	:3	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t	key_0        	:28	__PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#endif
+}
+__PACKING_ATTRIBUTE_STRUCT_END__ RDD_HASH_COMMAND_DTS;
+
+typedef union
+{
+    uint32_t word_val[2];
+    uint64_t dword_val64[1];
+    RDD_HASH_COMMAND_DTS fields;
+} HASH_COMMAND_STRUCT;
+#define RDD_HASH_COMMAND_KEY_1_READ_G(r, g, idx)                  GROUP_MREAD_32(g, idx*sizeof(RDD_HASH_COMMAND_DTS), r)
+#define RDD_HASH_COMMAND_KEY_1_WRITE_G(v, g, idx)                 GROUP_MWRITE_32(g, idx*sizeof(RDD_HASH_COMMAND_DTS), v)
+#define RDD_HASH_COMMAND_KEY_1_READ(r, p)                         MREAD_32((uint8_t *)p, r)
+#define RDD_HASH_COMMAND_KEY_1_WRITE(v, p)                        MWRITE_32((uint8_t *)p, v)
+#define RDD_HASH_COMMAND_KEY_0_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_32(g, idx*sizeof(RDD_HASH_COMMAND_DTS) + 4, 4, 28, r)
+#define RDD_HASH_COMMAND_KEY_0_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_32(g, idx*sizeof(RDD_HASH_COMMAND_DTS) + 4, 4, 28, v)
+#define RDD_HASH_COMMAND_KEY_0_READ(r, p)                         FIELD_MREAD_32((uint8_t *)p + 4, 4, 28, r)
+#define RDD_HASH_COMMAND_KEY_0_WRITE(v, p)                        FIELD_MWRITE_32((uint8_t *)p + 4, 4, 28, v)
+#define RDD_HASH_COMMAND_CONFIGURATION_READ_G(r, g, idx)          GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_HASH_COMMAND_DTS) + 7, 1, 3, r)
+#define RDD_HASH_COMMAND_CONFIGURATION_WRITE_G(v, g, idx)         GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_HASH_COMMAND_DTS) + 7, 1, 3, v)
+#define RDD_HASH_COMMAND_CONFIGURATION_READ(r, p)                 FIELD_MREAD_8((uint8_t *)p + 7, 1, 3, r)
+#define RDD_HASH_COMMAND_CONFIGURATION_WRITE(v, p)                FIELD_MWRITE_8((uint8_t *)p + 7, 1, 3, v)
+#define RDD_HASH_COMMAND_AGING_READ_G(r, g, idx)                  GROUP_FIELD_MREAD_8(g, idx*sizeof(RDD_HASH_COMMAND_DTS) + 7, 0, 1, r)
+#define RDD_HASH_COMMAND_AGING_WRITE_G(v, g, idx)                 GROUP_FIELD_MWRITE_8(g, idx*sizeof(RDD_HASH_COMMAND_DTS) + 7, 0, 1, v)
+#define RDD_HASH_COMMAND_AGING_READ(r, p)                         FIELD_MREAD_8((uint8_t *)p + 7, 0, 1, r)
+#define RDD_HASH_COMMAND_AGING_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 7, 0, 1, v)
+/* <<<RDD_HASH_COMMAND_DTS */
+
+/* <<<RDD_HASH_COMMAND */
+
+#endif /* _RDD_DATA_STRUCTURES_AUTO_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_map_auto.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_map_auto.c
new file mode 100644
index 0000000000..4f74f0ec9b
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_map_auto.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+
+
+/* This is an automated file. Do not edit its contents. */
+
+
+#include "rdd_map_auto.h"
+
+
+rdp_runner_image_e rdp_core_to_image_map[] = {
+	image_0_runner_image};
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_map_auto.h b/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_map_auto.h
new file mode 100644
index 0000000000..2a450b6a9b
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_map_auto.h
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+
+
+/* This is an automated file. Do not edit its contents. */
+
+
+#ifndef _RDD_MAP_AUTO_H_
+#define _RDD_MAP_AUTO_H_
+
+typedef enum
+{
+	image_0_runner_image = 0,
+	cfe_core_runner_image = image_0_runner_image,
+	runner_image_last = 0,
+} rdp_runner_image_e;
+
+extern rdp_runner_image_e rdp_core_to_image_map[];
+#endif /* _RDD_MAP_AUTO_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_runner_proj_defs.h b/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_runner_proj_defs.h
new file mode 100644
index 0000000000..d39c5aa9ef
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/rdd_runner_proj_defs.h
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef _RDD_RUNNER_PROJ_DEFS_H
+#define _RDD_RUNNER_PROJ_DEFS_H
+
+#define NUM_OF_GLOBAL_REGS                                      0
+#define NUM_OF_LOCAL_REGS                                       32
+#define NUM_OF_MAIN_RUNNER_THREADS                              16
+#define NUM_OF_RUNNER_CORES                                     3
+
+/* TIMER DEFINES */
+#define FLUSH_TASK_TIMER_INTERVAL_IN_USEC                       15
+#define RATE_LIMITER_TIMER_PERIOD_IN_USEC                       1000
+#define CPU_RX_METER_TIMER_PERIOD                               10000
+#define CPU_RX_METER_TIMER_PERIOD_IN_USEC                       (CPU_RX_METER_TIMER_PERIOD)
+#define FLUSH_TASK_TIMER_INTERVAL                               (FLUSH_TASK_TIMER_INTERVAL_IN_USEC)
+#define RATE_LIMITER_TIMER_PERIOD                               (RATE_LIMITER_TIMER_PERIOD_IN_USEC)
+
+/* NATC */
+#define NATC_16BYTE_KEY_MASK                                    0xc000
+
+#define RDD_WAN0_VPORT       RDD_VPORT_ID_0
+#define RDD_LAN0_VPORT       RDD_VPORT_ID_1
+#define RDD_LAN1_VPORT       RDD_VPORT_ID_2
+#define RDD_LAN2_VPORT       RDD_VPORT_ID_3
+#define RDD_LAN3_VPORT       RDD_VPORT_ID_4
+#define RDD_LAN4_VPORT       RDD_VPORT_ID_5
+#define RDD_LAN5_VPORT       RDD_VPORT_ID_6
+#define RDD_LAN6_VPORT       RDD_VPORT_ID_7
+#define RDD_LAN_VPORT_LAST   RDD_LAN6_VPORT
+
+#define RDD_CPU0_VPORT       (RDD_LAN_VPORT_LAST + 1)
+#define RDD_CPU_VPORT_FIRST  RDD_CPU0_VPORT
+
+#define RDD_CPU_VPORT_FIRST  RDD_CPU0_VPORT
+#define RDD_CPU1_VPORT       (RDD_CPU_VPORT_FIRST + 1)
+#define RDD_CPU2_VPORT       (RDD_CPU_VPORT_FIRST + 2)
+#define RDD_CPU3_VPORT       (RDD_CPU_VPORT_FIRST + 3)
+#define RDD_CPU4_VPORT       (RDD_CPU_VPORT_FIRST + 4)
+#define RDD_WLAN0_VPORT      RDD_CPU4_VPORT
+#define RDD_CPU5_VPORT       (RDD_CPU_VPORT_FIRST + 5)
+#define RDD_WLAN1_VPORT      RDD_CPU5_VPORT
+#define RDD_CPU6_VPORT       (RDD_CPU_VPORT_FIRST + 6)
+#define RDD_WLAN2_VPORT      RDD_CPU6_VPORT
+#define RDD_CPU_VPORT_FLOOD  (RDD_CPU_VPORT_FIRST + 7)
+#define RDD_CPU_VPORT_LAST   RDD_CPU_VPORT_FLOOD
+#define RDD_CPU_VPORT_MASK ((1 << RDD_CPU0_VPORT) | (1 << RDD_CPU1_VPORT) | (1 << RDD_CPU2_VPORT) | \
+    (1 << RDD_CPU3_VPORT) | (1 << RDD_CPU4_VPORT) | (1 << RDD_CPU5_VPORT) | (1 << RDD_CPU6_VPORT) | \
+    (1 << RDD_CPU_VPORT_FLOOD))
+
+
+
+#endif
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/ru_chip.h b/arch/arm/mach-bcmbca/xrdp/bcm63146/ru_chip.h
new file mode 100644
index 0000000000..8c663533a8
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/ru_chip.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _RU_CHIP_H_
+#define _RU_CHIP_H_
+
+#include "XRDP_AG.h"
+
+#endif /* End of file ru_chip.h */
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_drivers_common_ag.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_drivers_common_ag.c
new file mode 100644
index 0000000000..c1e26ae512
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_drivers_common_ag.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#include "xrdp_drv_drivers_common_ag.h"
+
+
+/* get_test_method_value */
+uint32_t gtmv(bdmf_test_method method, uint8_t bits)
+{
+    switch (method)
+    {
+    case bdmf_test_method_mid :
+        return 1 << (bits - 1);
+    case bdmf_test_method_high :
+        /* todo need to fix this, the problem was that ((1<<32)-1)=0 ???, it should be 0xFFFFFFFF */
+        return bits == 32 ? _32BITS_MAX_VAL_ : (1 << bits) - 1;
+    case bdmf_test_method_low :
+    default :
+        return 0;
+    }
+    return 0;
+}
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_drivers_common_ag.h b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_drivers_common_ag.h
new file mode 100644
index 0000000000..c50d92f343
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_drivers_common_ag.h
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _XRDP_DRIVERS_COMMON_AG_H_
+#define _XRDP_DRIVERS_COMMON_AG_H_
+
+
+#include <bdmf_data_types.h>
+#include "bdmf_shell.h"
+#include "bdmf_interface.h"
+#include <bdmf_session.h>
+#include "ru.h"
+
+
+#define _1BITS_MAX_VAL_ (1U<<1)
+#define _2BITS_MAX_VAL_ (1U<<2)
+#define _3BITS_MAX_VAL_ (1U<<3)
+#define _4BITS_MAX_VAL_ (1U<<4)
+#define _5BITS_MAX_VAL_ (1U<<5)
+#define _6BITS_MAX_VAL_ (1U<<6)
+#define _7BITS_MAX_VAL_ (1U<<7)
+#define _9BITS_MAX_VAL_ (1U<<9)
+#define _10BITS_MAX_VAL_ (1U<<10)
+#define _11BITS_MAX_VAL_ (1U<<11)
+#define _12BITS_MAX_VAL_ (1U<<12)
+#define _13BITS_MAX_VAL_ (1U<<13)
+#define _14BITS_MAX_VAL_ (1U<<14)
+#define _15BITS_MAX_VAL_ (1U<<15)
+#define _17BITS_MAX_VAL_ (1U<<17)
+#define _18BITS_MAX_VAL_ (1U<<18)
+#define _19BITS_MAX_VAL_ (1U<<19)
+#define _20BITS_MAX_VAL_ (1U<<20)
+#define _21BITS_MAX_VAL_ (1U<<21)
+#define _22BITS_MAX_VAL_ (1U<<22)
+#define _23BITS_MAX_VAL_ (1U<<23)
+#define _24BITS_MAX_VAL_ (1U<<24)
+#define _25BITS_MAX_VAL_ (1U<<25)
+#define _26BITS_MAX_VAL_ (1U<<26)
+#define _27BITS_MAX_VAL_ (1U<<27)
+#define _28BITS_MAX_VAL_ (1U<<28)
+#define _29BITS_MAX_VAL_ (1U<<29)
+#define _30BITS_MAX_VAL_ (1U<<30)
+#define _31BITS_MAX_VAL_ (1U<<31)
+#define _32BITS_MAX_VAL_ (0xFFFFFFFF)
+
+
+typedef enum
+{
+    bdmf_test_method_low,
+    bdmf_test_method_mid,
+    bdmf_test_method_high,
+}
+bdmf_test_method;
+
+uint32_t gtmv(bdmf_test_method method, uint8_t bits);
+
+
+static inline void ag_ru_block_addr_print(int block_idx)
+{
+	int addr_idx;
+	for (addr_idx = 0; addr_idx < RU_ALL_BLOCKS[block_idx]->addr_count; addr_idx++)
+	{
+		bdmf_trace("block %s[%d] address = 0x%lx\n", RU_ALL_BLOCKS[block_idx]->name, addr_idx,
+			RU_ALL_BLOCKS[block_idx]->addr[addr_idx]);
+	}
+}
+
+static inline void ag_ru_blocks_data_print(void)
+{
+	int block_idx;
+	for (block_idx = 0; block_idx < RU_BLK_COUNT; block_idx++)
+	{
+		ag_ru_block_addr_print(block_idx);
+	}
+}
+#endif
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_psram.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_psram.c
new file mode 100644
index 0000000000..c4697da1da
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_psram.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#include "rdp_common.h"
+#include "xrdp_drv_drivers_common_ag.h"
+#include "xrdp_drv_psram.h"
+
+bdmf_error_t ag_drv_psram_memory_data_set(uint32_t psram_enrty, const psram_memory_data *memory_data)
+{
+    int i;
+#ifdef VALIDATE_PARMS
+    if(!memory_data)
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_PARM), BDMF_ERR_PARM);
+        return BDMF_ERR_PARM;
+    }
+    if((psram_enrty >= 1536))
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_RANGE), BDMF_ERR_RANGE);
+        return BDMF_ERR_RANGE;
+    }
+#endif
+
+    for (i = 0; i < 32; i++)
+        RU_REG_RAM_WRITE(0, psram_enrty *32 + i, PSRAM, MEMORY_DATA, memory_data->memory_data[i]);
+#if 0
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 0, PSRAM, MEMORY_DATA, memory_data->memory_data[0]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 1, PSRAM, MEMORY_DATA, memory_data->memory_data[1]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 2, PSRAM, MEMORY_DATA, memory_data->memory_data[2]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 3, PSRAM, MEMORY_DATA, memory_data->memory_data[3]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 4, PSRAM, MEMORY_DATA, memory_data->memory_data[4]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 5, PSRAM, MEMORY_DATA, memory_data->memory_data[5]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 6, PSRAM, MEMORY_DATA, memory_data->memory_data[6]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 7, PSRAM, MEMORY_DATA, memory_data->memory_data[7]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 8, PSRAM, MEMORY_DATA, memory_data->memory_data[8]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 9, PSRAM, MEMORY_DATA, memory_data->memory_data[9]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 10, PSRAM, MEMORY_DATA, memory_data->memory_data[10]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 11, PSRAM, MEMORY_DATA, memory_data->memory_data[11]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 12, PSRAM, MEMORY_DATA, memory_data->memory_data[12]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 13, PSRAM, MEMORY_DATA, memory_data->memory_data[13]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 14, PSRAM, MEMORY_DATA, memory_data->memory_data[14]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 15, PSRAM, MEMORY_DATA, memory_data->memory_data[15]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 16, PSRAM, MEMORY_DATA, memory_data->memory_data[16]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 17, PSRAM, MEMORY_DATA, memory_data->memory_data[17]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 18, PSRAM, MEMORY_DATA, memory_data->memory_data[18]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 19, PSRAM, MEMORY_DATA, memory_data->memory_data[19]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 20, PSRAM, MEMORY_DATA, memory_data->memory_data[20]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 21, PSRAM, MEMORY_DATA, memory_data->memory_data[21]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 22, PSRAM, MEMORY_DATA, memory_data->memory_data[22]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 23, PSRAM, MEMORY_DATA, memory_data->memory_data[23]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 24, PSRAM, MEMORY_DATA, memory_data->memory_data[24]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 25, PSRAM, MEMORY_DATA, memory_data->memory_data[25]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 26, PSRAM, MEMORY_DATA, memory_data->memory_data[26]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 27, PSRAM, MEMORY_DATA, memory_data->memory_data[27]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 28, PSRAM, MEMORY_DATA, memory_data->memory_data[28]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 29, PSRAM, MEMORY_DATA, memory_data->memory_data[29]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 30, PSRAM, MEMORY_DATA, memory_data->memory_data[30]);
+    RU_REG_RAM_WRITE(0, psram_enrty *32 + 31, PSRAM, MEMORY_DATA, memory_data->memory_data[31]);
+#endif
+
+    return BDMF_ERR_OK;
+}
+
+bdmf_error_t ag_drv_psram_memory_data_get(uint32_t psram_enrty, psram_memory_data *memory_data)
+{
+    int i;
+#ifdef VALIDATE_PARMS
+    if(!memory_data)
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_PARM), BDMF_ERR_PARM);
+        return BDMF_ERR_PARM;
+    }
+    if((psram_enrty >= 1536))
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_RANGE), BDMF_ERR_RANGE);
+        return BDMF_ERR_RANGE;
+    }
+#endif
+
+    for (i = 0; i < 32; i++)
+        RU_REG_RAM_READ(0, psram_enrty *32 + i, PSRAM, MEMORY_DATA, memory_data->memory_data[i]);
+
+#if 0
+    RU_REG_RAM_READ(0, psram_enrty *32 + 0, PSRAM, MEMORY_DATA, memory_data->memory_data[0]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 1, PSRAM, MEMORY_DATA, memory_data->memory_data[1]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 2, PSRAM, MEMORY_DATA, memory_data->memory_data[2]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 3, PSRAM, MEMORY_DATA, memory_data->memory_data[3]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 4, PSRAM, MEMORY_DATA, memory_data->memory_data[4]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 5, PSRAM, MEMORY_DATA, memory_data->memory_data[5]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 6, PSRAM, MEMORY_DATA, memory_data->memory_data[6]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 7, PSRAM, MEMORY_DATA, memory_data->memory_data[7]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 8, PSRAM, MEMORY_DATA, memory_data->memory_data[8]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 9, PSRAM, MEMORY_DATA, memory_data->memory_data[9]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 10, PSRAM, MEMORY_DATA, memory_data->memory_data[10]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 11, PSRAM, MEMORY_DATA, memory_data->memory_data[11]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 12, PSRAM, MEMORY_DATA, memory_data->memory_data[12]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 13, PSRAM, MEMORY_DATA, memory_data->memory_data[13]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 14, PSRAM, MEMORY_DATA, memory_data->memory_data[14]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 15, PSRAM, MEMORY_DATA, memory_data->memory_data[15]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 16, PSRAM, MEMORY_DATA, memory_data->memory_data[16]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 17, PSRAM, MEMORY_DATA, memory_data->memory_data[17]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 18, PSRAM, MEMORY_DATA, memory_data->memory_data[18]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 19, PSRAM, MEMORY_DATA, memory_data->memory_data[19]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 20, PSRAM, MEMORY_DATA, memory_data->memory_data[20]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 21, PSRAM, MEMORY_DATA, memory_data->memory_data[21]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 22, PSRAM, MEMORY_DATA, memory_data->memory_data[22]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 23, PSRAM, MEMORY_DATA, memory_data->memory_data[23]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 24, PSRAM, MEMORY_DATA, memory_data->memory_data[24]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 25, PSRAM, MEMORY_DATA, memory_data->memory_data[25]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 26, PSRAM, MEMORY_DATA, memory_data->memory_data[26]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 27, PSRAM, MEMORY_DATA, memory_data->memory_data[27]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 28, PSRAM, MEMORY_DATA, memory_data->memory_data[28]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 29, PSRAM, MEMORY_DATA, memory_data->memory_data[29]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 30, PSRAM, MEMORY_DATA, memory_data->memory_data[30]);
+    RU_REG_RAM_READ(0, psram_enrty *32 + 31, PSRAM, MEMORY_DATA, memory_data->memory_data[31]);
+#endif
+
+    return BDMF_ERR_OK;
+}
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_psram.h b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_psram.h
new file mode 100644
index 0000000000..9a6dcddcfa
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_psram.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _XRDP_DRV_PSRAM_H_
+#define _XRDP_DRV_PSRAM_H_
+
+#include "access_macros.h"
+#include "bdmf_interface.h"
+#include "rdp_common.h"
+
+
+/**************************************************************************************************/
+/* data: data - data                                                                              */
+/**************************************************************************************************/
+typedef struct
+{
+    uint32_t memory_data[32];
+} psram_memory_data;
+
+
+bdmf_error_t ag_drv_psram_memory_data_set(uint32_t psram_enrty, const psram_memory_data *memory_data);
+bdmf_error_t ag_drv_psram_memory_data_get(uint32_t psram_enrty, psram_memory_data *memory_data);
+#endif
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_rnr_regs.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_rnr_regs.c
new file mode 100644
index 0000000000..8b131fb4c7
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_rnr_regs.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#include "rdp_common.h"
+#include "xrdp_drv_drivers_common_ag.h"
+#include "xrdp_drv_rnr_regs.h"
+
+#define BLOCK_ADDR_COUNT_BITS 3
+#define BLOCK_ADDR_COUNT (1<<BLOCK_ADDR_COUNT_BITS)
+
+bdmf_error_t ag_drv_rnr_regs_cfg_cpu_wakeup_set(uint8_t rnr_id, uint8_t thread_num)
+{
+    uint32_t reg_cfg_cpu_wakeup=0;
+
+#ifdef VALIDATE_PARMS
+    if((rnr_id >= BLOCK_ADDR_COUNT) ||
+       (thread_num >= _4BITS_MAX_VAL_))
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_RANGE), BDMF_ERR_RANGE);
+        return BDMF_ERR_RANGE;
+    }
+#endif
+
+    reg_cfg_cpu_wakeup = RU_FIELD_SET(rnr_id, RNR_REGS, CFG_CPU_WAKEUP, THREAD_NUM, reg_cfg_cpu_wakeup, thread_num);
+
+    RU_REG_WRITE(rnr_id, RNR_REGS, CFG_CPU_WAKEUP, reg_cfg_cpu_wakeup);
+
+    return BDMF_ERR_OK;
+}
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_rnr_regs.h b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_rnr_regs.h
new file mode 100644
index 0000000000..17f9592bd0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_rnr_regs.h
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _XRDP_DRV_RNR_REGS_H_
+#define _XRDP_DRV_RNR_REGS_H_
+
+#include "access_macros.h"
+#include "bdmf_interface.h"
+#include "rdp_common.h"
+
+
+bdmf_error_t ag_drv_rnr_regs_cfg_cpu_wakeup_set(uint8_t rnr_id, uint8_t thread_num);
+
+#endif
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_sbpm.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_sbpm.c
new file mode 100644
index 0000000000..050daa5f99
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_sbpm.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#include "rdp_common.h"
+#include "xrdp_drv_drivers_common_ag.h"
+#include "xrdp_drv_sbpm.h"
+
+bdmf_error_t ag_drv_sbpm_regs_bn_alloc_set(uint8_t sa)
+{
+    uint32_t reg_regs_bn_alloc=0;
+
+#ifdef VALIDATE_PARMS
+    if((sa >= _6BITS_MAX_VAL_))
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_RANGE), BDMF_ERR_RANGE);
+        return BDMF_ERR_RANGE;
+    }
+#endif
+
+    reg_regs_bn_alloc = RU_FIELD_SET(0, SBPM, REGS_BN_ALLOC, SA, reg_regs_bn_alloc, sa);
+
+    RU_REG_WRITE(0, SBPM, REGS_BN_ALLOC, reg_regs_bn_alloc);
+
+    return BDMF_ERR_OK;
+}
+
+bdmf_error_t ag_drv_sbpm_regs_bn_alloc_rply_get(sbpm_regs_bn_alloc_rply *regs_bn_alloc_rply)
+{
+    uint32_t reg_regs_bn_alloc_rply;
+
+#ifdef VALIDATE_PARMS
+    if(!regs_bn_alloc_rply)
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_PARM), BDMF_ERR_PARM);
+        return BDMF_ERR_PARM;
+    }
+#endif
+
+    RU_REG_READ(0, SBPM, REGS_BN_ALLOC_RPLY, reg_regs_bn_alloc_rply);
+
+    regs_bn_alloc_rply->alloc_bn_valid = RU_FIELD_GET(0, SBPM, REGS_BN_ALLOC_RPLY, ALLOC_BN_VALID, reg_regs_bn_alloc_rply);
+    regs_bn_alloc_rply->alloc_bn = RU_FIELD_GET(0, SBPM, REGS_BN_ALLOC_RPLY, ALLOC_BN, reg_regs_bn_alloc_rply);
+    regs_bn_alloc_rply->ack = RU_FIELD_GET(0, SBPM, REGS_BN_ALLOC_RPLY, ACK, reg_regs_bn_alloc_rply);
+    regs_bn_alloc_rply->nack = RU_FIELD_GET(0, SBPM, REGS_BN_ALLOC_RPLY, NACK, reg_regs_bn_alloc_rply);
+    regs_bn_alloc_rply->excl_high = RU_FIELD_GET(0, SBPM, REGS_BN_ALLOC_RPLY, EXCL_HIGH, reg_regs_bn_alloc_rply);
+    regs_bn_alloc_rply->excl_low = RU_FIELD_GET(0, SBPM, REGS_BN_ALLOC_RPLY, EXCL_LOW, reg_regs_bn_alloc_rply);
+    regs_bn_alloc_rply->busy = RU_FIELD_GET(0, SBPM, REGS_BN_ALLOC_RPLY, BUSY, reg_regs_bn_alloc_rply);
+    regs_bn_alloc_rply->rdy = RU_FIELD_GET(0, SBPM, REGS_BN_ALLOC_RPLY, RDY, reg_regs_bn_alloc_rply);
+
+    return BDMF_ERR_OK;
+}
+
+bdmf_error_t ag_drv_sbpm_regs_bn_connect_set(uint16_t bn, bdmf_boolean ack_req, bdmf_boolean wr_req, uint16_t pointed_bn)
+{
+    uint32_t reg_regs_bn_connect=0;
+
+#ifdef VALIDATE_PARMS
+    if((bn >= _14BITS_MAX_VAL_) ||
+       (ack_req >= _1BITS_MAX_VAL_) ||
+       (wr_req >= _1BITS_MAX_VAL_) ||
+       (pointed_bn >= _14BITS_MAX_VAL_))
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_RANGE), BDMF_ERR_RANGE);
+        return BDMF_ERR_RANGE;
+    }
+#endif
+
+    reg_regs_bn_connect = RU_FIELD_SET(0, SBPM, REGS_BN_CONNECT, BN, reg_regs_bn_connect, bn);
+    reg_regs_bn_connect = RU_FIELD_SET(0, SBPM, REGS_BN_CONNECT, ACK_REQ, reg_regs_bn_connect, ack_req);
+    reg_regs_bn_connect = RU_FIELD_SET(0, SBPM, REGS_BN_CONNECT, WR_REQ, reg_regs_bn_connect, wr_req);
+    reg_regs_bn_connect = RU_FIELD_SET(0, SBPM, REGS_BN_CONNECT, POINTED_BN, reg_regs_bn_connect, pointed_bn);
+
+    RU_REG_WRITE(0, SBPM, REGS_BN_CONNECT, reg_regs_bn_connect);
+
+    return BDMF_ERR_OK;
+}
+
+bdmf_error_t ag_drv_sbpm_regs_bn_connect_rply_get(bdmf_boolean *connect_ack, bdmf_boolean *busy, bdmf_boolean *rdy)
+{
+    uint32_t reg_regs_bn_connect_rply;
+
+#ifdef VALIDATE_PARMS
+    if(!connect_ack || !busy || !rdy)
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_PARM), BDMF_ERR_PARM);
+        return BDMF_ERR_PARM;
+    }
+#endif
+
+    RU_REG_READ(0, SBPM, REGS_BN_CONNECT_RPLY, reg_regs_bn_connect_rply);
+
+    *connect_ack = RU_FIELD_GET(0, SBPM, REGS_BN_CONNECT_RPLY, CONNECT_ACK, reg_regs_bn_connect_rply);
+    *busy = RU_FIELD_GET(0, SBPM, REGS_BN_CONNECT_RPLY, BUSY, reg_regs_bn_connect_rply);
+    *rdy = RU_FIELD_GET(0, SBPM, REGS_BN_CONNECT_RPLY, RDY, reg_regs_bn_connect_rply);
+
+    return BDMF_ERR_OK;
+}
+
+bdmf_error_t ag_drv_sbpm_regs_get_next_set(uint16_t bn)
+{
+    uint32_t reg_regs_get_next=0;
+
+#ifdef VALIDATE_PARMS
+    if((bn >= _14BITS_MAX_VAL_))
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_RANGE), BDMF_ERR_RANGE);
+        return BDMF_ERR_RANGE;
+    }
+#endif
+
+    reg_regs_get_next = RU_FIELD_SET(0, SBPM, REGS_GET_NEXT, BN, reg_regs_get_next, bn);
+
+    RU_REG_WRITE(0, SBPM, REGS_GET_NEXT, reg_regs_get_next);
+
+    return BDMF_ERR_OK;
+}
+
+bdmf_error_t ag_drv_sbpm_regs_get_next_rply_get(sbpm_regs_get_next_rply *regs_get_next_rply)
+{
+    uint32_t reg_regs_get_next_rply;
+
+#ifdef VALIDATE_PARMS
+    if(!regs_get_next_rply)
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_PARM), BDMF_ERR_PARM);
+        return BDMF_ERR_PARM;
+    }
+#endif
+
+    RU_REG_READ(0, SBPM, REGS_GET_NEXT_RPLY, reg_regs_get_next_rply);
+
+    regs_get_next_rply->bn_valid = RU_FIELD_GET(0, SBPM, REGS_GET_NEXT_RPLY, BN_VALID, reg_regs_get_next_rply);
+    regs_get_next_rply->next_bn = RU_FIELD_GET(0, SBPM, REGS_GET_NEXT_RPLY, NEXT_BN, reg_regs_get_next_rply);
+    regs_get_next_rply->bn_null = RU_FIELD_GET(0, SBPM, REGS_GET_NEXT_RPLY, BN_NULL, reg_regs_get_next_rply);
+    regs_get_next_rply->mcnt_val = RU_FIELD_GET(0, SBPM, REGS_GET_NEXT_RPLY, MCNT_VAL, reg_regs_get_next_rply);
+    regs_get_next_rply->busy = RU_FIELD_GET(0, SBPM, REGS_GET_NEXT_RPLY, BUSY, reg_regs_get_next_rply);
+    regs_get_next_rply->rdy = RU_FIELD_GET(0, SBPM, REGS_GET_NEXT_RPLY, RDY, reg_regs_get_next_rply);
+
+    return BDMF_ERR_OK;
+}
+
+bdmf_error_t ag_drv_sbpm_regs_bn_free_without_contxt_set(uint16_t head_bn, uint8_t sa, bdmf_boolean ack_req)
+{
+    uint32_t reg_regs_bn_free_without_contxt=0;
+
+#ifdef VALIDATE_PARMS
+    if((head_bn >= _14BITS_MAX_VAL_) ||
+       (sa >= _6BITS_MAX_VAL_) ||
+       (ack_req >= _1BITS_MAX_VAL_))
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_RANGE), BDMF_ERR_RANGE);
+        return BDMF_ERR_RANGE;
+    }
+#endif
+
+    reg_regs_bn_free_without_contxt = RU_FIELD_SET(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT, HEAD_BN, reg_regs_bn_free_without_contxt, head_bn);
+    reg_regs_bn_free_without_contxt = RU_FIELD_SET(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT, SA, reg_regs_bn_free_without_contxt, sa);
+    reg_regs_bn_free_without_contxt = RU_FIELD_SET(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT, ACK_REQ, reg_regs_bn_free_without_contxt, ack_req);
+
+    RU_REG_WRITE(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT, reg_regs_bn_free_without_contxt);
+
+    return BDMF_ERR_OK;
+}
+
+bdmf_error_t ag_drv_sbpm_regs_bn_free_without_contxt_rply_get(sbpm_regs_bn_free_without_contxt_rply *regs_bn_free_without_contxt_rply)
+{
+    uint32_t reg_regs_bn_free_without_contxt_rply;
+
+#ifdef VALIDATE_PARMS
+    if(!regs_bn_free_without_contxt_rply)
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_PARM), BDMF_ERR_PARM);
+        return BDMF_ERR_PARM;
+    }
+#endif
+
+    RU_REG_READ(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT_RPLY, reg_regs_bn_free_without_contxt_rply);
+
+    regs_bn_free_without_contxt_rply->free_ack = RU_FIELD_GET(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT_RPLY, FREE_ACK, reg_regs_bn_free_without_contxt_rply);
+    regs_bn_free_without_contxt_rply->ack_stat = RU_FIELD_GET(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT_RPLY, ACK_STAT, reg_regs_bn_free_without_contxt_rply);
+    regs_bn_free_without_contxt_rply->nack_stat = RU_FIELD_GET(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT_RPLY, NACK_STAT, reg_regs_bn_free_without_contxt_rply);
+    regs_bn_free_without_contxt_rply->excl_high_stat = RU_FIELD_GET(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT_RPLY, EXCL_HIGH_STAT, reg_regs_bn_free_without_contxt_rply);
+    regs_bn_free_without_contxt_rply->excl_low_stat = RU_FIELD_GET(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT_RPLY, EXCL_LOW_STAT, reg_regs_bn_free_without_contxt_rply);
+    regs_bn_free_without_contxt_rply->bsy = RU_FIELD_GET(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT_RPLY, BSY, reg_regs_bn_free_without_contxt_rply);
+    regs_bn_free_without_contxt_rply->rdy = RU_FIELD_GET(0, SBPM, REGS_BN_FREE_WITHOUT_CONTXT_RPLY, RDY, reg_regs_bn_free_without_contxt_rply);
+
+    return BDMF_ERR_OK;
+}
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_sbpm.h b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_sbpm.h
new file mode 100644
index 0000000000..168ab9f320
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_sbpm.h
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _XRDP_DRV_SBPM_H_
+#define _XRDP_DRV_SBPM_H_
+
+#include "access_macros.h"
+#include "bdmf_interface.h"
+#include "rdp_common.h"
+
+
+/**************************************************************************************************/
+/* alloc_bn_valid: alloc_bn_valid - alloc_bn_valid                                                */
+/* alloc_bn: alloc_bn - alloc_bn                                                                  */
+/* ack: ack - ack                                                                                 */
+/* nack: nack - nack                                                                              */
+/* excl_high: excl_high - Exclusive bit is indication of Exclusive_high status of client with rel */
+/*            ated Alloc request                                                                  */
+/* excl_low: excl_low - Exclusive bit is indication of Exclusive_low status of client with relate */
+/*           d Alloc request                                                                      */
+/* busy: busy - busy                                                                              */
+/* rdy: rdy - rdy                                                                                 */
+/**************************************************************************************************/
+typedef struct
+{
+    bdmf_boolean alloc_bn_valid;
+    uint16_t alloc_bn;
+    bdmf_boolean ack;
+    bdmf_boolean nack;
+    bdmf_boolean excl_high;
+    bdmf_boolean excl_low;
+    bdmf_boolean busy;
+    bdmf_boolean rdy;
+} sbpm_regs_bn_alloc_rply;
+
+
+/**************************************************************************************************/
+/* bn_valid: bn_valid - Used for validation of Next BN reply                                      */
+/* next_bn: next_bn - Next BN - reply of Get_next command                                         */
+/* bn_null: bn_null - Next BN is null indication                                                  */
+/* mcnt_val: mcnt_val - mcst cnt val                                                              */
+/* busy: busy - Get Next command is busy                                                          */
+/* rdy: rdy - Get Next command is ready                                                           */
+/**************************************************************************************************/
+typedef struct
+{
+    bdmf_boolean bn_valid;
+    uint16_t next_bn;
+    bdmf_boolean bn_null;
+    uint8_t mcnt_val;
+    bdmf_boolean busy;
+    bdmf_boolean rdy;
+} sbpm_regs_get_next_rply;
+
+
+/**************************************************************************************************/
+/* free_ack: free_ack - Acknowledge on Free command                                               */
+/* ack_stat: ack_stat - ACK status of CPU                                                         */
+/* nack_stat: nack_stat - NACK status of CPU                                                      */
+/* excl_high_stat: excl_high_stat - Exclusive_high status of CPU                                  */
+/* excl_low_stat: excl_low_stat - Exclusive_low status of CPU                                     */
+/* bsy: bsy - Busy bit of command (command is currently in execution)                             */
+/* rdy: rdy - Ready bit of command (ready for new command execution)                              */
+/**************************************************************************************************/
+typedef struct
+{
+    bdmf_boolean free_ack;
+    bdmf_boolean ack_stat;
+    bdmf_boolean nack_stat;
+    bdmf_boolean excl_high_stat;
+    bdmf_boolean excl_low_stat;
+    bdmf_boolean bsy;
+    bdmf_boolean rdy;
+} sbpm_regs_bn_free_without_contxt_rply;
+
+
+bdmf_error_t ag_drv_sbpm_regs_bn_alloc_set(uint8_t sa);
+bdmf_error_t ag_drv_sbpm_regs_bn_alloc_rply_get(
+		sbpm_regs_bn_alloc_rply *regs_bn_alloc_rply);
+bdmf_error_t ag_drv_sbpm_regs_bn_connect_set(uint16_t bn, bdmf_boolean ack_req,
+		bdmf_boolean wr_req, uint16_t pointed_bn);
+bdmf_error_t ag_drv_sbpm_regs_bn_connect_rply_get(bdmf_boolean *connect_ack,
+		bdmf_boolean *busy, bdmf_boolean *rdy);
+bdmf_error_t ag_drv_sbpm_regs_get_next_set(uint16_t bn);
+bdmf_error_t ag_drv_sbpm_regs_get_next_rply_get(
+		sbpm_regs_get_next_rply *regs_get_next_rply);
+bdmf_error_t ag_drv_sbpm_regs_bn_free_without_contxt_set(uint16_t head_bn,
+		uint8_t sa, bdmf_boolean ack_req);
+bdmf_error_t ag_drv_sbpm_regs_bn_free_without_contxt_rply_get(
+		sbpm_regs_bn_free_without_contxt_rply *regs_bn_free_without_contxt_rply);
+
+#endif
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_unimac_rdp.c b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_unimac_rdp.c
new file mode 100644
index 0000000000..a0bbb7c6d3
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_unimac_rdp.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#include "rdp_common.h"
+#include "xrdp_drv_drivers_common_ag.h"
+#include "xrdp_drv_unimac_rdp.h"
+
+#define BLOCK_ADDR_COUNT_BITS 3
+#define BLOCK_ADDR_COUNT (1<<BLOCK_ADDR_COUNT_BITS)
+
+bdmf_error_t ag_drv_unimac_rdp_command_config_set(uint8_t umac_id, const unimac_rdp_command_config *command_config)
+{
+    uint32_t reg_command_config=0;
+
+#ifdef VALIDATE_PARMS
+    if(!command_config)
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_PARM), BDMF_ERR_PARM);
+        return BDMF_ERR_PARM;
+    }
+    if((umac_id >= BLOCK_ADDR_COUNT) ||
+       (command_config->runt_filter_dis >= _1BITS_MAX_VAL_) ||
+       (command_config->oob_efc_disab >= _1BITS_MAX_VAL_) ||
+       (command_config->ignore_tx_pause >= _1BITS_MAX_VAL_) ||
+       (command_config->fd_tx_urun_fix_en >= _1BITS_MAX_VAL_) ||
+       (command_config->line_loopback >= _1BITS_MAX_VAL_) ||
+       (command_config->no_lgth_check >= _1BITS_MAX_VAL_) ||
+       (command_config->cntl_frm_ena >= _1BITS_MAX_VAL_) ||
+       (command_config->ena_ext_config >= _1BITS_MAX_VAL_) ||
+       (command_config->en_internal_tx_crs >= _1BITS_MAX_VAL_) ||
+       (command_config->bypass_oob_efc_synchronizer >= _1BITS_MAX_VAL_) ||
+       (command_config->oob_efc_mode >= _1BITS_MAX_VAL_) ||
+       (command_config->sw_override_rx >= _1BITS_MAX_VAL_) ||
+       (command_config->sw_override_tx >= _1BITS_MAX_VAL_) ||
+       (command_config->mac_loop_con >= _1BITS_MAX_VAL_) ||
+       (command_config->loop_ena >= _1BITS_MAX_VAL_) ||
+       (command_config->fcs_corrupt_urun_en >= _1BITS_MAX_VAL_) ||
+       (command_config->sw_reset >= _1BITS_MAX_VAL_) ||
+       (command_config->overflow_en >= _1BITS_MAX_VAL_) ||
+       (command_config->rx_low_latency_en >= _1BITS_MAX_VAL_) ||
+       (command_config->hd_ena >= _1BITS_MAX_VAL_) ||
+       (command_config->tx_addr_ins >= _1BITS_MAX_VAL_) ||
+       (command_config->pause_ignore >= _1BITS_MAX_VAL_) ||
+       (command_config->pause_fwd >= _1BITS_MAX_VAL_) ||
+       (command_config->crc_fwd >= _1BITS_MAX_VAL_) ||
+       (command_config->pad_en >= _1BITS_MAX_VAL_) ||
+       (command_config->promis_en >= _1BITS_MAX_VAL_) ||
+       (command_config->eth_speed >= _2BITS_MAX_VAL_) ||
+       (command_config->rx_ena >= _1BITS_MAX_VAL_) ||
+       (command_config->tx_ena >= _1BITS_MAX_VAL_))
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_RANGE), BDMF_ERR_RANGE);
+        return BDMF_ERR_RANGE;
+    }
+#endif
+
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, RUNT_FILTER_DIS, reg_command_config, command_config->runt_filter_dis);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, OOB_EFC_DISAB, reg_command_config, command_config->oob_efc_disab);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, IGNORE_TX_PAUSE, reg_command_config, command_config->ignore_tx_pause);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, FD_TX_URUN_FIX_EN, reg_command_config, command_config->fd_tx_urun_fix_en);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, LINE_LOOPBACK, reg_command_config, command_config->line_loopback);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, NO_LGTH_CHECK, reg_command_config, command_config->no_lgth_check);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, CNTL_FRM_ENA, reg_command_config, command_config->cntl_frm_ena);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, ENA_EXT_CONFIG, reg_command_config, command_config->ena_ext_config);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, EN_INTERNAL_TX_CRS, reg_command_config, command_config->en_internal_tx_crs);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, BYPASS_OOB_EFC_SYNCHRONIZER, reg_command_config, command_config->bypass_oob_efc_synchronizer);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, OOB_EFC_MODE, reg_command_config, command_config->oob_efc_mode);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, SW_OVERRIDE_RX, reg_command_config, command_config->sw_override_rx);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, SW_OVERRIDE_TX, reg_command_config, command_config->sw_override_tx);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, MAC_LOOP_CON, reg_command_config, command_config->mac_loop_con);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, LOOP_ENA, reg_command_config, command_config->loop_ena);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, FCS_CORRUPT_URUN_EN, reg_command_config, command_config->fcs_corrupt_urun_en);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, SW_RESET, reg_command_config, command_config->sw_reset);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, OVERFLOW_EN, reg_command_config, command_config->overflow_en);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, RX_LOW_LATENCY_EN, reg_command_config, command_config->rx_low_latency_en);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, HD_ENA, reg_command_config, command_config->hd_ena);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, TX_ADDR_INS, reg_command_config, command_config->tx_addr_ins);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, PAUSE_IGNORE, reg_command_config, command_config->pause_ignore);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, PAUSE_FWD, reg_command_config, command_config->pause_fwd);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, CRC_FWD, reg_command_config, command_config->crc_fwd);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, PAD_EN, reg_command_config, command_config->pad_en);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, PROMIS_EN, reg_command_config, command_config->promis_en);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, ETH_SPEED, reg_command_config, command_config->eth_speed);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, RX_ENA, reg_command_config, command_config->rx_ena);
+    reg_command_config = RU_FIELD_SET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, TX_ENA, reg_command_config, command_config->tx_ena);
+
+    RU_REG_WRITE(umac_id, UNIMAC_RDP, COMMAND_CONFIG, reg_command_config);
+
+    return BDMF_ERR_OK;
+}
+
+bdmf_error_t ag_drv_unimac_rdp_command_config_get(uint8_t umac_id, unimac_rdp_command_config *command_config)
+{
+    uint32_t reg_command_config;
+
+#ifdef VALIDATE_PARMS
+    if(!command_config)
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_PARM), BDMF_ERR_PARM);
+        return BDMF_ERR_PARM;
+    }
+    if((umac_id >= BLOCK_ADDR_COUNT))
+    {
+        bdmf_trace("ERROR driver %s:%u| err=%s (%d)\n", __FILE__, __LINE__, bdmf_strerror(BDMF_ERR_RANGE), BDMF_ERR_RANGE);
+        return BDMF_ERR_RANGE;
+    }
+#endif
+
+    RU_REG_READ(umac_id, UNIMAC_RDP, COMMAND_CONFIG, reg_command_config);
+
+    command_config->runt_filter_dis = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, RUNT_FILTER_DIS, reg_command_config);
+    command_config->oob_efc_disab = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, OOB_EFC_DISAB, reg_command_config);
+    command_config->ignore_tx_pause = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, IGNORE_TX_PAUSE, reg_command_config);
+    command_config->fd_tx_urun_fix_en = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, FD_TX_URUN_FIX_EN, reg_command_config);
+    command_config->line_loopback = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, LINE_LOOPBACK, reg_command_config);
+    command_config->no_lgth_check = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, NO_LGTH_CHECK, reg_command_config);
+    command_config->cntl_frm_ena = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, CNTL_FRM_ENA, reg_command_config);
+    command_config->ena_ext_config = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, ENA_EXT_CONFIG, reg_command_config);
+    command_config->en_internal_tx_crs = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, EN_INTERNAL_TX_CRS, reg_command_config);
+    command_config->bypass_oob_efc_synchronizer = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, BYPASS_OOB_EFC_SYNCHRONIZER, reg_command_config);
+    command_config->oob_efc_mode = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, OOB_EFC_MODE, reg_command_config);
+    command_config->sw_override_rx = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, SW_OVERRIDE_RX, reg_command_config);
+    command_config->sw_override_tx = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, SW_OVERRIDE_TX, reg_command_config);
+    command_config->mac_loop_con = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, MAC_LOOP_CON, reg_command_config);
+    command_config->loop_ena = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, LOOP_ENA, reg_command_config);
+    command_config->fcs_corrupt_urun_en = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, FCS_CORRUPT_URUN_EN, reg_command_config);
+    command_config->sw_reset = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, SW_RESET, reg_command_config);
+    command_config->overflow_en = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, OVERFLOW_EN, reg_command_config);
+    command_config->rx_low_latency_en = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, RX_LOW_LATENCY_EN, reg_command_config);
+    command_config->hd_ena = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, HD_ENA, reg_command_config);
+    command_config->tx_addr_ins = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, TX_ADDR_INS, reg_command_config);
+    command_config->pause_ignore = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, PAUSE_IGNORE, reg_command_config);
+    command_config->pause_fwd = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, PAUSE_FWD, reg_command_config);
+    command_config->crc_fwd = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, CRC_FWD, reg_command_config);
+    command_config->pad_en = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, PAD_EN, reg_command_config);
+    command_config->promis_en = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, PROMIS_EN, reg_command_config);
+    command_config->eth_speed = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, ETH_SPEED, reg_command_config);
+    command_config->rx_ena = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, RX_ENA, reg_command_config);
+    command_config->tx_ena = RU_FIELD_GET(umac_id, UNIMAC_RDP, COMMAND_CONFIG, TX_ENA, reg_command_config);
+
+    return BDMF_ERR_OK;
+}
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_unimac_rdp.h b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_unimac_rdp.h
new file mode 100644
index 0000000000..cb63043224
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bcm63146/xrdp_drv_unimac_rdp.h
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _XRDP_DRV_UNIMAC_RDP_H_
+#define _XRDP_DRV_UNIMAC_RDP_H_
+
+#include "access_macros.h"
+#include "bdmf_interface.h"
+#include "rdp_common.h"
+
+
+/**************************************************************************************************/
+/* runt_filter_dis:  - When set, disable runt filtering.                                          */
+/* oob_efc_disab:  - When this bit is set, out-of-band egress flow control will be disabled. When */
+/*                 this bit is 0 (out-of-band egress flow control enabled) and input pin ext_tx_f */
+/*                low_control is 1, frame transmissions may be stopped - see OOB_EFC_MODE for det */
+/*                ails.
+Out-of-band egress flow control operation is similar to halting the trans */
+/*                mit datapath due to reception of a Pause Frame with a non-zero timer value. Thi */
+/*                s bit however has no effect on regular Rx Pause Frame based egress flow control */
+/*                .                                                                               */
+/* ignore_tx_pause:  - Ignores the back pressure signaling from the system and hence no Tx pause  */
+/*                  generation, when set.                                                         */
+/* fd_tx_urun_fix_en:  - Tx Underflow detection can be improved by accounting for residue bytes i */
+/*                    n 128b to 8b convertor. The fix is valid only for full duplex mode and can  */
+/*                    be enabled by setting this bit.                                             */
+/* line_loopback:  - Enable Line Loopback i.e. MAC FIFO side loopback (RX to TX) when set to '1', */
+/*                 normal operation when set to '0' (Reset value).                                */
+/* no_lgth_check:  - Payload Length Check Disable. When set to '0', the Core checks the frame's p */
+/*                ayload length with the Frame
+Length/Type field, when set to '1'(Reset value), t */
+/*                he payload length check is disabled.                                            */
+/* cntl_frm_ena:  - MAC Control Frame Enable. When set to '1', MAC Control frames with any 
+Opcod */
+/*               e other than 0x0001 are accepted and forward to the Client interface. 
+When set  */
+/*               to '0' (Reset value), MAC Control frames with any Opcode other 
+than 0x0001 are  */
+/*               silently discarded.                                                              */
+/* ena_ext_config:  - Enable Configuration with External Pins. When set to '0' (Reset value) 
+the */
+/*                  Core speed and Mode is programmed with the register bits ETH_SPEED(1:0) 
+and  */
+/*                 HD_ENA. When set to '1', the Core is configured with the pins 
+set_speed(1:0)  */
+/*                 and set_duplex.                                                                */
+/* en_internal_tx_crs:  - If enabled, then CRS input to Unimac is ORed with tds[8] (tx data valid */
+/*                      output). This is helpful when TX CRS is disabled inside PHY.              */
+/* bypass_oob_efc_synchronizer:  - 1=> bypass the OOB external flow control signal synchronizer,  */
+/*                              to e.g. reduce latency. In this case it is assumed/required that  */
+/*                              Unimac input ext_tx_flow_control is already in tx_clk clock domai */
+/*                              n (so there is no need to synchronize it)
+0=> locally synchronize */
+/*                               the OOB egress flow control signal to tx_clk. In this case it is */
+/*                               assumed/required that ext_tx_flow_control is glitchless (e.g. re */
+/*                              gistered in its native clock domain).                             */
+/* oob_efc_mode:  - 0=> strict/full OOB egress backpressure mode:
+- pause frames and PFC frames,  */
+/*               as well as regular packets, are all affected by Unimac input ext_tx_flow_control */
+/*               , as long as OOB_EFC_DISAB is 0
+- in this mode, OOB backpressure will be active  */
+/*               as long as ext_tx_flow_control is asserted and i_oob_efc_disab is 0, regardless  */
+/*               of whether the MAC operates in half duplex mode or full duplex mode
+1=> legacy m */
+/*               ode:
+- ext_tx_flow_control does not affect (does not prevent) transmission of Pa */
+/*               use and PFC frames, i.e. in this mode OOB egress backpressure may only affect tr */
+/*               ansmission of regular packets
+- OOB egress backpressure is fully disabled (ignor */
+/*               ed) when the MAC operates in half duplex mode.                                   */
+/* sw_override_rx:  - If set, enables the SW programmed Rx pause capability config bits to overwr */
+/*                 ite the auto negotiated Rx pause capabilities when ena_ext_config (autoconfig) */
+/*                  is set.
+If cleared, and when ena_ext_config (autoconfig) is set, then SW prog */
+/*                 rammed Rx pause capability config bits has no effect over auto negotiated capa */
+/*                 bilities.                                                                      */
+/* sw_override_tx:  - If set, enables the SW programmed Tx pause capability config bits to overwr */
+/*                 ite the auto negotiated Tx pause capabilities when ena_ext_config (autoconfig) */
+/*                  is set.
+If cleared, and when ena_ext_config (autoconfig) is set, then SW prog */
+/*                 rammed Tx pause capability config bits has no effect over auto negotiated capa */
+/*                 bilities.                                                                      */
+/* mac_loop_con:  - Transmit packets to PHY while in MAC local loopback, when set to '1', otherwi */
+/*               se transmit to PHY is disabled (normal operation),
+when set to '0' (Reset value) */
+/*               .                                                                                */
+/* loop_ena:  - Enable GMII/MII loopback (TX to RX) when set to '1', normal operation when set to */
+/*            '0' (Reset value).                                                                  */
+/* fcs_corrupt_urun_en:  - Corrupt Tx FCS, on underrun, when set to '1', No FCS corruption when s */
+/*                      et to '0' (Reset value).                                                  */
+/* sw_reset:  - Software Reset Command. When asserted, the TX and RX are 
+disabled. Config regist */
+/*           ers are not affected by sw reset. Write a 0 to de-assert the sw reset.               */
+/* overflow_en:  - If set, enables Rx FIFO overflow logic. In this case, the RXFIFO_STAT[1] regis */
+/*              ter bit is not operational (always set to 0).
+If cleared, disables RX FIFO overfl */
+/*              ow logic. In this case, the RXFIFO_STAT[1] register bit is operational (Sticky se */
+/*              t when overrun occurs, clearable only by SW_Reset).                               */
+/* rx_low_latency_en:  - This works only when runt filter is disabled. It reduces the receive lat */
+/*                    ency by 48 MAC clock time.                                                  */
+/* hd_ena:  - Half duplex enable. When set to '1', enables half duplex mode, when set 
+to '0', th */
+/*         e MAC operates in full duplex mode.
+Ignored at ethernet speeds 1G/2.5G or when the reg */
+/*         ister ENA_EXT_CONFIG is set to '1'.                                                    */
+/* tx_addr_ins:  - Set MAC address on transmit. If enabled (Set to '1') the MAC overwrites 
+the s */
+/*              ource MAC address with the programmed MAC address in registers MAC_0 
+and MAC_1.  */
+/*              If disabled (Set to reset value '0'), the source MAC address 
+received from the t */
+/*              ransmit application transmitted is not modified by the MAC.                       */
+/* pause_ignore:  - Ignore Pause Frame Quanta. If enabled (Set to '1') received pause frames 
+are */
+/*                ignored by the MAC. When disabled (Set to reset value '0') the transmit 
+proces */
+/*               s is stopped for the amount of time specified in the pause quanta 
+received with */
+/*               in the pause frame.                                                              */
+/* pause_fwd:  - Terminate/Forward Pause Frames. If enabled (Set to '1') pause frames are 
+forwar */
+/*            ded to the user application.  If disabled (Set to reset value '0'), 
+pause frames a */
+/*            re terminated and discarded in the MAC.                                             */
+/* crc_fwd:  - Terminate/Forward Received CRC. If enabled (1) the CRC field of received 
+frames a */
+/*          re transmitted to the user application.
+If disabled (Set to reset value '0') the CRC  */
+/*          field is stripped from the frame.
+Note: If padding function (bit PAD_EN set to '1') i */
+/*          s enabled. CRC_FWD is 
+ignored and the CRC field is checked and always terminated and */
+/*           removed.                                                                             */
+/* pad_en:  - Enable/Disable Frame Padding. If enabled (Set to '1'), then padding is removed from */
+/*          the received frame before it is transmitted to the user
+application. If disabled (set */
+/*          to reset value '0'), then no padding is removed on receive by the MAC. 
+This bit has  */
+/*         no effect on Tx padding and hence Transmit always pad runts to guarantee a minimum fra */
+/*         me size of 64 octets.                                                                  */
+/* promis_en:  - Enable/Disable MAC promiscuous operation. When asserted (Set to '1'), 
+all frame */
+/*            s are received without Unicast address filtering.                                   */
+/* eth_speed:  - Set MAC speed. Ignored when the register bit ENA_EXT_CONFIG is set to '1'.  When */
+/*             the Register bit ENA_EXT_CONFIG is set to '0', used to set the core mode of operat */
+/*            ion: 00: Enable 10Mbps Ethernet mode 01: Enable 100Mbps Ethernet mode 10: Enable Gi */
+/*            gabit Ethernet mode 11: Enable 2.5Gigabit Ethernet mode                             */
+/* rx_ena:  - Enable/Disable MAC receive path. When set to '0' (Reset value), the MAC 
+receive fu */
+/*         nction is disable.  When set to '1', the MAC receive function is enabled.              */
+/* tx_ena:  - Enable/Disable MAC transmit path for data packets & pause/pfc packets sent in the n */
+/*         ormal data path.
+Pause/pfc packets generated internally are allowed if ignore_tx_pause */
+/*          is not set. When set to '0' (Reset value), the MAC 
+transmit function is disable.  Wh */
+/*         en set to '1', the MAC transmit function is enabled.                                   */
+/**************************************************************************************************/
+typedef struct
+{
+    bdmf_boolean runt_filter_dis;
+    bdmf_boolean oob_efc_disab;
+    bdmf_boolean ignore_tx_pause;
+    bdmf_boolean fd_tx_urun_fix_en;
+    bdmf_boolean line_loopback;
+    bdmf_boolean no_lgth_check;
+    bdmf_boolean cntl_frm_ena;
+    bdmf_boolean ena_ext_config;
+    bdmf_boolean en_internal_tx_crs;
+    bdmf_boolean bypass_oob_efc_synchronizer;
+    bdmf_boolean oob_efc_mode;
+    bdmf_boolean sw_override_rx;
+    bdmf_boolean sw_override_tx;
+    bdmf_boolean mac_loop_con;
+    bdmf_boolean loop_ena;
+    bdmf_boolean fcs_corrupt_urun_en;
+    bdmf_boolean sw_reset;
+    bdmf_boolean overflow_en;
+    bdmf_boolean rx_low_latency_en;
+    bdmf_boolean hd_ena;
+    bdmf_boolean tx_addr_ins;
+    bdmf_boolean pause_ignore;
+    bdmf_boolean pause_fwd;
+    bdmf_boolean crc_fwd;
+    bdmf_boolean pad_en;
+    bdmf_boolean promis_en;
+    uint8_t eth_speed;
+    bdmf_boolean rx_ena;
+    bdmf_boolean tx_ena;
+} unimac_rdp_command_config;
+
+
+bdmf_error_t ag_drv_unimac_rdp_command_config_set(uint8_t umac_id,
+		const unimac_rdp_command_config *command_config);
+bdmf_error_t ag_drv_unimac_rdp_command_config_get(uint8_t umac_id,
+		unimac_rdp_command_config *command_config);
+
+#endif
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bdmf_data_types.h b/arch/arm/mach-bcmbca/xrdp/bdmf_data_types.h
new file mode 100644
index 0000000000..69f5ad6a0e
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bdmf_data_types.h
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ * 
+ */
+
+/********************************************************************
+ * bdmf_types.h
+ *
+ * Broadcom Device Management Framework - built-in attribute types
+ *
+ ********************************************************************/
+ 
+
+#ifndef BDMF_DATA_TYPES_H_
+#define BDMF_DATA_TYPES_H_
+#include <linux/types.h>
+
+/* Signed integer */
+typedef int64_t bdmf_number;
+
+/* Index. Signed to allow special values. Long enough to enable
+ * casting to pointer */
+
+typedef long bdmf_index;
+typedef unsigned long bdmf_ptr;
+
+#define BDMF_INDEX_UNASSIGNED	(-1) /*< "Unassigned" bdmf_index value */
+#define BDMF_INDEX_ANY		(-2) /*< "Any" bdmf_index value */
+
+/* String */
+typedef char *bdmf_string;
+
+/* Ethernet address */
+typedef struct {
+	uint8_t b[6];  /*< Address bytes */
+} bdmf_mac_t;
+
+/* Check if MAC address is zero
+ * param[in]   ip  IP address
+ */
+static inline int bdmf_mac_is_zero(const bdmf_mac_t *mac)
+{
+	return (!mac->b[0] && !mac->b[1] && !mac->b[2] &&
+	        !mac->b[3] && !mac->b[4] && !mac->b[5]);
+}
+
+/* Enumeration value */
+typedef long bdmf_enum;
+
+/* Boolean value */
+typedef char bdmf_boolean;
+
+/* IP address family */
+typedef enum {
+	bdmf_ip_family_ipv4,
+	bdmf_ip_family_ipv6
+} bdmf_ip_family;
+
+/* IPv4 address */
+typedef uint32_t bdmf_ipv4;
+
+/* IPv6 address */
+typedef struct {
+	uint8_t data[16];
+} bdmf_ipv6_t;
+
+/* IPv4 or IPv6 address */
+typedef struct {
+	bdmf_ip_family family;		/*< Address family: IPv4 / IPv6 */
+	union {
+		bdmf_ipv4 ipv4;		/*< IPv4 address */
+		bdmf_ipv6_t ipv6;	/*< IPv6 address */
+	} addr;
+} bdmf_ip_t;
+
+/* Check if IPv6 address is zero
+ * param[in] ip IPv6 address
+ */
+static inline int bdmf_ipv6_is_zero(const bdmf_ipv6_t *ipv6)
+{
+	uint32_t *ipv6_as_int = (uint32_t *)ipv6;
+	return (!ipv6_as_int[0] && !ipv6_as_int[1] &&
+		!ipv6_as_int[2] && !ipv6_as_int[3]);
+}
+
+/* Check if IP address is zero
+ * param[in]   ip  IP address
+ */
+static inline int bdmf_ip_is_zero(const bdmf_ip_t *ip)
+{
+	if (ip->family == bdmf_ip_family_ipv4)
+		return !ip->addr.ipv4;
+	return bdmf_ipv6_is_zero(&ip->addr.ipv6);
+}
+
+/* Compare IP addresses
+ * param[in]   ip  IP address
+ * param[in]   ip2  IP address
+ */
+static inline int bdmf_ip_cmp(const bdmf_ip_t *ip, const bdmf_ip_t *ip2)
+{
+	uint32_t *ipv6_as_int, *ipv6_as_int2;
+
+	if (ip->family != ip2->family)
+		return -1;
+	if (ip->family == bdmf_ip_family_ipv4)
+		return ip->addr.ipv4 != ip2->addr.ipv4;
+
+	ipv6_as_int = (uint32_t *)&ip->addr.ipv6;
+	ipv6_as_int2 = (uint32_t *)&ip2->addr.ipv6;
+	return (!(ipv6_as_int[0] == ipv6_as_int2[0] &&
+		ipv6_as_int[1] == ipv6_as_int2[1] &&
+		ipv6_as_int[2] == ipv6_as_int2[2] &&
+		ipv6_as_int[3] == ipv6_as_int2[3]));
+}
+
+#if defined(CONFIG_PHYS_64BIT)
+typedef uint64_t bdmf_phys_addr_t;
+#else
+typedef uint32_t bdmf_phys_addr_t;
+#endif
+
+#endif /* BDMF_DATA_TYPES_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/bdmf_errno.h b/arch/arm/mach-bcmbca/xrdp/bdmf_errno.h
new file mode 100644
index 0000000000..cc159a96c0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bdmf_errno.h
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ * 
+ */
+
+/*******************************************************************
+ * bdmf_errno.h
+ *
+ * BDMF framework - generic error codes
+ *******************************************************************/
+
+#ifndef BDMF_ERRNO_H
+#define BDMF_ERRNO_H
+
+/* Generic error codes */
+typedef enum {
+	BDMF_ERR_OK		=  0,   /**< OK */
+	BDMF_ERR_PARM		= -1,   /**< Error in parameters */
+	BDMF_ERR_NOMEM		= -2,   /**< No memory */
+	BDMF_ERR_NORES		= -3,   /**< No resources */
+	BDMF_ERR_INTERNAL	= -4,   /**< Internal error */
+	BDMF_ERR_NOENT		= -5,   /**< Entry doesn't exist */
+	BDMF_ERR_NODEV		= -6,   /**< Device doesn't exist */
+	BDMF_ERR_ALREADY	= -7,   /**< Entry already exists */
+	BDMF_ERR_RANGE		= -8,   /**< Out of range */
+	BDMF_ERR_PERM		= -9,   /**< No permission to perform an operation */
+	BDMF_ERR_NOT_SUPPORTED	= -10,  /**< Operation is not supported */
+	BDMF_ERR_PARSE		= -11,  /**< Parsing error */
+	BDMF_ERR_INVALID_OP	= -12,  /**< Invalid operation */
+	BDMF_ERR_IO		= -13,  /**< I/O error */
+	BDMF_ERR_STATE		= -14,  /**< Object is in bad state */
+	BDMF_ERR_DELETED	= -15,  /**< Object is deleted */
+	BDMF_ERR_TOO_MANY	= -16,  /**< Too many objects */
+	BDMF_ERR_NOT_LINKED	= -17,  /**< Objects are not linked */
+	BDMF_ERR_NO_MORE	= -18,  /**< No more entries */
+	BDMF_ERR_OVERFLOW	= -19,  /**< Buffer overflow */
+	BDMF_ERR_COMM_FAIL	= -20,  /**< Communication failure */
+	BDMF_ERR_NOT_CONNECTED	= -21,  /**< No connection with the target system */
+	BDMF_ERR_SYSCALL_ERR	= -22,  /**< System call returned error */
+	BDMF_ERR_MSG_ERROR	= -23,  /**< Received message is insane */
+	BDMF_ERR_TOO_MANY_REQS	= -24,  /**< Too many outstanding requests */
+	BDMF_ERR_NO_MSG_SERVER	= -25,  /**< Remote delivery error. No message server. */
+	BDMF_ERR_NO_LOCAL_SUBS	= -26,  /**< Local subsystem is not set */
+	BDMF_ERR_NO_SUBS	= -27,  /**< Subsystem is not recognised */
+	BDMF_ERR_INTR		= -28,  /**< Operation interrupted */
+	BDMF_ERR_HIST_RES_MISMATCH= -29,  /**< History result mismatch */
+	BDMF_ERR_MORE		= -30,  /**< More work to do */
+	BDMF_ERR_IGNORE		= -31,  /**< Ignore the error */
+	BDMF_ERR_LAST		= -100,	/**< Last generic error */
+} bdmf_error_t;
+
+/* Register error code range
+ * \param[in]	from - From number. Must be negative
+ * \param[in]	to - To number. Must be negative >from
+ * \param[in]	p_strerr - Callback that returns error string
+ *
+ * \returns	BDMF_ERR_OK - OK\n
+ *		BDMF_ERR_PARM - error in parameters\n
+ *		BDMF_ERR_NOMEM - no memory
+ *		BDMF_ERR_ALREADY - (from, to) range overlaps with existing range
+ */
+bdmf_error_t bdmf_error_range_register(int from, int to,
+				       const char *(*p_strerr)(int err));
+
+/* Unregister error code range
+ * \param[in]	from - From number. Must be negative
+ * \param[in]	to - To number. Must be negative >from
+ *
+ * \returns	BDMF_ERR_OK - OK\n
+ *		BDMF_ERR_PARM - error in parameters\n
+ *		BDMF_ERR_NOENT - (from, to) range is not registered
+ */
+bdmf_error_t bdmf_error_range_unregister(int from, int to);
+
+/* Convert error code to error string
+ * \param[in]	err - Error code. One of bdmf_error_t constants or additional
+ *		      codes registered using bdmf_error_register()
+ * \returns	Error string
+ */
+const char *bdmf_strerror(int err);
+
+#endif /* #ifndef BDMF_ERRNO_H */
+
diff --git a/arch/arm/mach-bcmbca/xrdp/bdmf_interface.h b/arch/arm/mach-bcmbca/xrdp/bdmf_interface.h
new file mode 100644
index 0000000000..a0ee9a2e27
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bdmf_interface.h
@@ -0,0 +1,942 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ * 
+ */
+
+#ifndef _BDMF_INTERFACE_H_
+#define _BDMF_INTERFACE_H_
+
+#define BDMF_MAX_MEM_SEGS 4
+
+#include <bdmf_system.h>
+#include <bdmf_data_types.h>
+
+#ifndef MAX
+#define MAX(a, b) ((a) < (b) ? (b) : (a))
+#endif
+#ifndef MIN
+#define MIN(a, b) ((a) >= (b) ? (b) : (a))
+#endif
+#ifndef ARRAY_LENGTH
+#define ARRAY_LENGTH(array) (sizeof(array)/sizeof(array[0]))
+#endif
+
+/* Managed object type handle */
+typedef struct bdmf_type *bdmf_type_handle;
+
+/* Managed object */
+typedef struct bdmf_object *bdmf_object_handle;
+
+/* Inter-object link */
+typedef struct bdmf_link *bdmf_link_handle;
+
+/* Handle that can represent different things */
+typedef void *bdmf_handle;
+
+/* Multi-attribute transaction handle link */
+typedef bdmf_object_handle bdmf_mattr_handle;
+
+/* Object's attribute handle */
+typedef uint16_t bdmf_attr_id;
+
+#define BDMF_MAX_INFO_NAME_LENGTH 32
+#define BDMF_MAX_INFO_HELP_LENGTH 128
+
+#define BDMF_TYPE_MAGIC		(('b'<<24) | ('d'<<16) | ('m'<<8) | 't')
+#define BDMF_OBJECT_MAGIC	(('b'<<24) | ('d'<<16) | ('m'<<8) | 'o')
+#define BDMF_MATTR_MAGIC	(('b'<<24) | ('d'<<16) | ('m'<<8) | 'a')
+#define BDMF_LINK_MAGIC		(('b'<<24) | ('d'<<16) | ('m'<<8) | 'l')
+#define BDMF_INVALID_MAGIC	(('~'<<24) | ('d'<<16) | ('m'<<8) | 'f')
+
+/* Object type information */
+typedef struct bdmf_type_info
+{
+	char name[BDMF_MAX_INFO_NAME_LENGTH];	/**< Object type name */
+	char help[BDMF_MAX_INFO_HELP_LENGTH];	/**< Object type description */
+	int n_objects;				/**< Number of managed objects */
+	int n_attrs;				/**< Number of attributes */
+} bdmf_type_info_t;
+
+
+/* Managed object type iterator.
+ * The function returns the first or the next registered object type handle.
+ *
+ * The handle returned by bdmf_type_get_next function must be
+ * released by passing it as a parameter to bdmf_type_get_next or bdmf_type_put()
+ *
+ * \param[in]	drv - previous type handle. NULL=get first
+ * \return	next type handle or NULL if end of list is reached.
+ */
+bdmf_type_handle bdmf_type_get_next(bdmf_type_handle drv);
+
+
+/** Get managed object type handle given its name
+ * The handle must be released using bdmf_put() function.
+ * 
+ * \param[in]	name - Managed object type name. The name can be followed by
+ * 		       "@subsystem" to identify type located at specific subsystem
+ * \param[out]	pdrv - type handle or NULL if object type with the requested
+ * 		       name is not found. It is guaranteed that *drv contains
+ * 		       valid handle if bdmf_type_find_get function returns 0.
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_type_find_get(const char *name, bdmf_type_handle *pdrv);
+
+
+/* Lock managed object type handle
+ *
+ * The handle must be released using bdmf_put() function.
+ *
+ * \param[in]	drv - Managed object type handle
+ */
+void bdmf_type_get(bdmf_type_handle drv);
+
+
+/* Release managed object type handle.
+ * The function "unlocks" the handle by decrementing usecount in the
+ * underlying structure. Following this call the handle may become invalid.
+ * 
+ * \param[in]	drv - Managed object type handle
+ * \return	void
+ */
+void bdmf_type_put(bdmf_type_handle drv);
+
+
+/* Get managed object type info
+ * 
+ * \param[in]	drv - Managed object type handle
+ * \param[out]	info - Managed object type info
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_type_info(bdmf_type_handle drv, bdmf_type_info_t *info);
+
+
+/* Get number of attributes supported by managed object type
+ *
+ * \param[in]	drv - Managed object type handle
+ * \return	number of attributes
+ */
+int bdmf_type_num_attrs(bdmf_type_handle drv);
+
+typedef struct bdmf_mattr bdmf_mattr_t;
+
+/** Create a new managed object using parameters in attribute descriptor string
+ *
+ * \param[in]	drv - Managed object type handle
+ * \param[in]	owner - Object owner. If NULL, framework tries to identify owner
+ * 			using attributes
+ * \param[in]	attr - An ASCII string of attribute values to be set for the new
+ * 		       object.	The string is comma-delimited list in format
+ * 		       name=value.
+ * \param[out]	pmo - New managed object handle
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_new_and_configure(bdmf_type_handle drv,
+	     bdmf_object_handle owner, const char *attr,
+	     bdmf_object_handle *pmo);
+
+/** Create a new managed object using parameters in attribute set
+ * \param[in]	drv - Managed object type handle
+ * \param[in]	owner - Object owner. If NULL, framework tries to identify owner
+ * 			using attributes
+ * \param[in]	mattr - attribute set in the same format as in bdmf_mattr_set().
+ *			mattr is freed automatically.
+ * \param[out]	pmo - New managed object handle
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_new_and_set(bdmf_type_handle drv,
+	     bdmf_object_handle owner, bdmf_mattr_handle mattr,
+	     bdmf_object_handle *pmo);
+
+
+/** Destroy managed object
+ *
+ * \param[out]	mo - Managed object handle
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_destroy(bdmf_object_handle mo);
+
+
+/** Find managed object
+ *
+ * When no longer needed, the managed object handle must be released by
+ * bdmf_put() function.
+ *
+ * \param[in]	drv - Managed object type handle
+ * \param[in]	owner - Object's owner (parent). If not set, the framework tries
+ * 			to identify the parent using attributes in the discr
+ * 			string.
+ * \param[in]	discr - List of attributes with values in the same format as in
+ * 			bdmf_configure().
+ * 			attrs string is passed transparently to the driver and
+ * 			must be sufficient to uniquely identify the object.
+ *			discr string can contain also attributes necessary to
+ *			identify object's parent, parent's parent, etc.
+ * \param[out]	pmo - Managed object handle
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_find_get(bdmf_type_handle drv,
+		  bdmf_object_handle owner, const char *discr,
+		  bdmf_object_handle *pmo);
+
+
+/** Find managed object
+ *
+ * When no longer needed, the managed object handle must be released by
+ * bdmf_put() function.
+ *
+ * \param[in]	drv - Managed object type handle
+ * \param[in]	owner - Object's owner (parent). If not set, the framework tries
+ * 			to identify the parent using attributes in the discr
+ * 			string.
+ * \param[in]	mattr - Set of attributes with values in the same format as in
+ * 			bdmf_mattr_set()
+ * 			attributes in the set must be sufficient to uniquely
+ * 			identify the object.
+ * \param[out]	pmo - Managed object handle
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_find_get_by_set(bdmf_type_handle drv,
+		  bdmf_object_handle owner, const bdmf_mattr_t *mattr,
+		  bdmf_object_handle *pmo);
+
+
+/** Lock managed object, by increasing its use count.
+ *
+ * An object cannot be destroyed unless its use count is zero.
+ * When no longer needed, the managed object handle must be released by
+ * bdmf_put() function.
+ *
+ * \param[in]	mo - Managed object handle
+ * \return	void
+ */
+void bdmf_get(bdmf_object_handle mo);
+
+
+/** Find managed object given its type name and attributes.
+ *
+ * The function combines bdmf_type_find_get() and bdmf_find_get() .
+ * When no longer needed, the managed object handle must be released by
+ * bdmf_put() function.
+ *
+ * \param[in]	discr - Object discriminator:
+ * 			type name followed by optional "/attribute_string"
+ * 			whereas attr_string is in the same format as in
+ * 			bdmf_new_and_configure()., This string is passed
+ * 			transparently to the driver and must be sufficient to
+ * 			uniquely identify the object. Note that type name can
+ * 			contain "@location" to identify remote subsystem
+ * 			implementing the type. If "@location" is omitted, any
+ * 			location is assumed.
+ * \param[out]	pmo - Managed object handle
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_find_get_by_name(const char *discr, bdmf_object_handle *pmo);
+
+
+/** Release managed object handle locked by one of bdmf_get(),
+ * bdmf_find_get(), bdmf_find_get_by_name(), bdmf_get_next()
+ * 
+ * Following ddmf_put call the object handle can become invalid.
+ *
+ * \param[in]	mo - Managed object handle
+ */
+void bdmf_put(bdmf_object_handle mo);
+
+
+/** Managed object iterator.
+ *
+ * Get next managed object.
+ *
+ * \param[in]	drv - Managed object type handle
+ * \param[in]	mo - Current managed object or NULL
+ * \param[in]	filter - Optional filter string in the same format as in
+ * 			 bdmf_configure. Can be NULL
+ * \return	0 - next object not found, otherwise - next object handle
+ */
+bdmf_object_handle bdmf_get_next(bdmf_type_handle drv,
+				 bdmf_object_handle mo, const char *filter);
+
+
+/** Get object name
+ * \param[in]	mo - Current managed object or NULL
+ * \return	object name
+ */
+const char *bdmf_object_name(bdmf_object_handle mo);
+
+
+/** Child iterator.
+ *
+ * Get next child.
+ *
+ * \param[in]	owner - Owner's handle
+ * \param[in]	type - Optional type name.
+ * 		       If !=NULL, only childs of the given type are iterated.
+ * \param[in]	mo - Current managed object or NULL
+ * \return	0 - next object not found, otherwise - next object handle
+ */
+bdmf_object_handle bdmf_get_next_child(bdmf_object_handle owner,
+				       const char *type, bdmf_object_handle mo);
+
+/** Check if objects are linked.
+ *
+ * One of the objects is a "downstream" object
+ * and the other is "upstream".
+ *
+ * \param[in]	ds - Downstream object handle
+ * \param[in]	us - Upstream object handle
+ * \param[out]	plink - Optional link pointer.
+ *			In case of mux-mux link, link pointer is returned
+ * \return	1 - link found, 0 - link not found.
+ */
+int bdmf_is_linked(bdmf_object_handle ds, bdmf_object_handle us,
+		   bdmf_link_handle *plink);
+
+
+/** Link managed objects together to form a path.
+ *
+ * One of the objects is a "downstream" object
+ * and the other is "upstream".
+ *
+ * \param[in]	ds - Downstream object handle
+ * \param[in]	us - Upstream object handle
+ * \param[in]	attrs - Optional attribute string.
+ *			This string is passed to objects' link_up, link_down
+ *			callbacks
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_link(bdmf_object_handle ds,
+	      bdmf_object_handle us, const char *attrs);
+
+
+/** Unlink managed objects from each other
+ *
+ * \param[in]	ds - Downstream object handle
+ * \param[in]	us - Upstream object handle
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_unlink(bdmf_object_handle ds, bdmf_object_handle us);
+
+
+/** Upstream link iterator
+ *
+ * \param[in]	mo - Managed object
+ * \param[in]	prev - Previous upstream link handle. NULL = get first
+ * \return	next us link handle or NULL
+ */
+bdmf_link_handle bdmf_get_next_us_link(bdmf_object_handle mo,
+				       bdmf_link_handle prev);
+
+
+/** Downstream link iterator
+ *
+ * \param[in]	mo - Managed object
+ * \param[in]	prev - Previous downstream link handle. NULL = get first
+ * \return	next ds link handle or NULL
+ */
+bdmf_link_handle bdmf_get_next_ds_link(bdmf_object_handle mo,
+					bdmf_link_handle prev);
+
+
+
+/** Map DS link to object
+ *
+ * \param[in]	ds_link
+ * \return	object handle
+ */
+bdmf_object_handle bdmf_ds_link_to_object(bdmf_link_handle ds_link);
+
+
+/** Map US link to object
+ *
+ * \param[in]	us_link
+ * \return	object handle
+ */
+bdmf_object_handle bdmf_us_link_to_object(bdmf_link_handle us_link);
+
+/** Get an object help string
+ * 
+ * \param[in]	drv - Managed object type handle
+ * \param[in]	what - Optional string identifying help chapter.
+ * \param[out]	buffer - Buffer where help info should be stored
+ * \param[in]	size - Buffer size
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_help(bdmf_type_handle drv,
+	      const char *what, char *buffer, uint32_t size);
+
+
+
+/** Get object owner.
+ *
+ * \param[in]	mo      Managed object
+ * \param[out]	owner   Object owner
+ */
+void bdmf_get_owner(const bdmf_object_handle mo, bdmf_object_handle *owner);
+
+
+/* Attribute types.
+ * Note that the list can be extended by registered aggregate and custom types.
+ */
+typedef enum {
+	bdmf_attr_number,	/* Numeric attribute */
+	bdmf_attr_string,	/* 0-terminated string */
+	bdmf_attr_buffer,	/* Buffer with binary data */
+	bdmf_attr_pointer,	/* A pointer */
+	bdmf_attr_object,	/* Object reference */
+	bdmf_attr_ether_addr,   /* 6-byte Ethernet h/w address */
+	bdmf_attr_ip_addr,	/* 4-byte IPv4 address or 16-byte IPv6 address */
+	bdmf_attr_ipv4_addr,	/* 4-byte IPv4 address */
+	bdmf_attr_ipv6_addr,	/* 16-byte IPv6 address */
+	bdmf_attr_boolean,	/* boolean. default(first) value = true (1) */
+	bdmf_attr_enum,		/* enumeration with list of values in static table */
+	bdmf_attr_dyn_enum,	/* dynamic enumeration with list of values
+				 * generated by callback */
+	bdmf_attr_enum_mask,	/* Bitmask containg multiple enum values */
+	bdmf_attr_aggregate,	/* aggregate type: "structure" consisting of
+				 * multiple attributes */
+	bdmf_attr_custom,	/* user-defined type */
+	bdmf_attr_last_type
+} bdmf_attr_type_t;
+
+/** Attribute information */
+typedef struct bdmf_attr_info {
+	char name[BDMF_MAX_INFO_NAME_LENGTH];	/* Attribute name */
+	char help[BDMF_MAX_INFO_HELP_LENGTH];	/* Attribute description */
+	bdmf_attr_type_t type;			/* Attribute type */
+	uint16_t size;				/* Attribute size */
+	uint16_t array_size;			/* Attribute array dimension */
+}  bdmf_attr_info_t;
+
+/** Find attribute by its name
+ * \param[in]	drv - Managed object type handle
+ * \param[in]	name - Attribute name
+ * \param[out]	p_attr - Attribute handle
+ * \return	0 - OK
+ *		BDMF_ERR_NOENT - no attribute with such name
+ *		BDMF_ERR_PERM - no permission
+ *		BDMF_ERR_PARM - error in parameters
+ */
+int bdmf_attr_by_name(bdmf_type_handle drv,
+		      const char *name, bdmf_attr_id *p_attr);
+
+
+/** Get attribute info
+ * \param[in]	drv - Managed object type handle
+ * \param[in]	attr - Attribute handle
+ * \param[out]	info - Attribute info
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_attr_info(bdmf_type_handle drv,
+		   bdmf_attr_id attr, bdmf_attr_info_t *info);
+
+
+/** Get attribute array element value as number.
+ * The function can be used for numeric, enum and ipv4 attributes.
+ *
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	attr - Attribute handle
+ * \param[in]	index - Array element index
+ * \param[out]	pva - Attribute value
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_attrelem_get_as_num(bdmf_object_handle mo_or_mattr,
+			     bdmf_attr_id attr, bdmf_index index,
+			     bdmf_number *pval);
+
+
+/** Set attribute array element value as number.
+ * The function can be used for numeric, enum and ipv4 attributes.
+ * 
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	attr - Attribute handle
+ * \param[in]	index - Array element index
+ * \param[in]	val - Attribute value
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_attrelem_set_as_num(bdmf_object_handle mo_or_mattr,
+			     bdmf_attr_id attr, bdmf_index index,
+			     bdmf_number val);
+
+
+/** Get attribute array element value in string (external) format.
+ * 
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	attr - Attribute handle
+ * \param[in]	index - Array element index
+ * \param[out]	buffer - Buffer for output string
+ * \param[in]	size - Buffer size
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_attrelem_get_as_string(bdmf_object_handle mo_or_mattr,
+				bdmf_attr_id attr, bdmf_index index,
+				char *buffer, uint32_t size);
+
+
+/** Set attribute array element using value in string (external) format.
+ * 
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	attr - Attribute handle
+ * \param[in]	index - Array element index
+ * \param[in]	val - Value in external format - 0-terminated string
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_attrelem_set_as_string(bdmf_object_handle mo_or_mattr,
+				bdmf_attr_id attr, bdmf_index index,
+				const char *val);
+
+
+/** Get attribute array element value as binary array.
+ * 
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	attr - Attribute handle
+ * \param[in]	index - Array element index
+ * \param[out]	buffer - Buffer where attribute value is returned
+ * \param[in]	size - Buffer size
+ * \return	>=0 - number of bytes copied, <0 - error code
+ */
+int bdmf_attrelem_get_as_buf(bdmf_object_handle mo_or_mattr,
+			     bdmf_attr_id attr, bdmf_index index,
+			     void *buffer, uint32_t size);
+
+
+/** Set attribute array element value from binary array.
+ * 
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	attr - Attribute handle
+ * \param[in]	index - Array element index
+ * \param[in]	buffer - Buffer containing value
+ * \param[in]	size - Buffer size
+ * \return	>=0 - number of bytes copied, <0 - error code
+ */
+int bdmf_attrelem_set_as_buf(bdmf_object_handle mo_or_mattr,
+			     bdmf_attr_id attr, bdmf_index index,
+			     const void *buffer, uint32_t size);
+
+
+/** Get scalar attribute value as number.
+ *
+ * The function can be used for numeric, enum and ipv4 attributes.
+ * 
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	att - Attribute handle
+ * \param[out]	pval - Attribute value
+ * \return	0 - OK, <0 - error
+ */
+static inline int bdmf_attr_get_as_num(bdmf_object_handle mo_or_mattr,
+				       bdmf_attr_id attr, bdmf_number *pval)
+{
+	return bdmf_attrelem_get_as_num(mo_or_mattr, attr, -1, pval);
+}
+
+/** Set scalar attribute value as number.
+ *
+ * The function can be used for numeric, enum and ipv4 attributes.
+ * 
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	attr - Attribute handle
+ * \param[in]	val - Attribute value
+ * \return	0 - OK, <0 - error
+ */
+static inline int bdmf_attr_set_as_num(bdmf_object_handle mo_or_mattr,
+				       bdmf_attr_id attr, bdmf_number val)
+{
+	return bdmf_attrelem_set_as_num(mo_or_mattr, attr, -1, val);
+}
+
+/** Get scalar attribute value as string (external value).
+ * 
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	attr - Attribute handle
+ * \param[out]	buffer - Buffer for output string
+ * \param[in]	size - Buffer size
+ * \return	0 - OK, <0 - error
+ */
+static inline int bdmf_attr_get_as_string(bdmf_object_handle mo_or_mattr,
+					  bdmf_attr_id attr, char *buffer,
+					  uint32_t size)
+{
+	return bdmf_attrelem_get_as_string(mo_or_mattr, attr, -1, buffer, size);
+}
+
+/** Set attribute value from string (external value).
+ * 
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	attr - Attribute handle
+ * \param[in]	val - Value in external format - 0-terminated string
+ * \return	0 - OK, <0 - error
+ */
+static inline int bdmf_attr_set_as_string(bdmf_object_handle mo_or_mattr,
+					  bdmf_attr_id attr, const char *val)
+{
+	return bdmf_attrelem_set_as_string(mo_or_mattr, attr, -1, val);
+}
+
+/** Get scalar attribute value as binary array
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	attr - Attribute handle
+ * \param[out]	buffer - Buffer where attribute value is returned
+ * \param[in]	size - Buffer size
+ * \return	>=0 - number of bytes copied, <0 - error code
+ */
+static inline int bdmf_attr_get_as_buf(bdmf_object_handle mo_or_mattr,
+				       bdmf_attr_id attr, void *buffer,
+				       uint32_t size)
+{
+	return bdmf_attrelem_get_as_buf(mo_or_mattr, attr, -1, buffer, size);
+}
+
+/** Set scalar attribute value from binary array
+ * \param[in]	mo_or_mattr - Managed object or mattr handle
+ * \param[in]	attr - Attribute handle
+ * \param[in]	buffer - Buffer containing value
+ * \param[in]	size - Buffer size
+ * \return	>=0 - number of bytes copied, <0 - error code
+ */
+static inline int bdmf_attr_set_as_buf(bdmf_object_handle mo_or_mattr,
+				       bdmf_attr_id attr, const void *buffer,
+				       uint32_t size)
+{
+	return bdmf_attrelem_set_as_buf(mo_or_mattr, attr, -1, buffer, size);
+}
+
+
+/** Add attribute array element value as number.
+ *
+ * The function can be used for dynamic arrays of numeric, enum and ipv4
+ * attributes.
+ *
+ * \param[in]		mo - Managed object handle
+ * \param[in]		attr - Attribute handle
+ * \param[in, out]	index - Array element index (handle). On input may
+ * 				contain a hint
+ * \param[in]		val - Attribute value
+ * \return		0 - OK, <0 - error
+ */
+int bdmf_attrelem_add_as_num(bdmf_object_handle mo, bdmf_attr_id attr,
+			     bdmf_index *index, bdmf_number val);
+
+
+/** Add attribute array element value as string.
+ *
+ * \param[in]		mo - Managed object handle
+ * \param[in]		attr - Attribute handle
+ * \param[in, out]	index - Array element index (handle). On input may
+ * 				contain a hint
+ * \param[in]		val - Value in external format - 0-terminated string
+ * \return		0 - OK, <0 - error
+ */
+int bdmf_attrelem_add_as_string(bdmf_object_handle mo, bdmf_attr_id attr,
+				bdmf_index *index, const char *val);
+
+
+/** Add attribute array element value as buffer.
+ *
+ * \param[in]		mo - Managed object handle
+ * \param[in]		attr - Attribute handle
+ * \param[in, out]	index - Array element index (handle). On input may
+ * 				contain a hint
+ * \param[in]		buffer - Buffer containing value
+ * \param[in]		size - Buffer size
+ * \return		>=0 - number of bytes copied, <0 - error code
+ */
+int bdmf_attrelem_add_as_buf(bdmf_object_handle mo, bdmf_attr_id attr,
+			     bdmf_index *index, const void *buffer,
+			     uint32_t size);
+
+
+/** Delete attribute array element
+ *
+ * The function can be used for dynamic arrays.
+ *
+ * \param[in]   mo - Managed object handle
+ * \param[in]   attr - Attribute handle
+ * \param[in]   index - Array element index (handle)
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_attrelem_delete(bdmf_object_handle mo, bdmf_attr_id attr,
+			 bdmf_index index);
+
+
+/** Get next attribute array index
+ *
+ * \param[in]		mo - Managed object handle
+ * \param[in]		attr - Attribute handle
+ * \param[in, out]	index - Array element index (handle). Seed with
+ * 				BDMF_INDEX_UNASSIGNED for get-first
+ * \return		0 - OK, = BDMF_ERR_NOENT - no more entries
+ */
+int bdmf_attrelem_get_next(bdmf_object_handle mo, bdmf_attr_id attr,
+			   bdmf_index *index);
+
+
+/** Find attribute array element index given its value in internal format.
+ *
+ * \param[in]	    	mo - Managed object handle
+ * \param[in]	    	attr - Attribute handle
+ * \param[in, out]	buffer - Buffer containing search value or partial
+ * 				 search value. Can be updated.
+ * \param[in, out]	index - Array element index (handle). On input may
+ * 				contain a hint
+ * \param[in]	   	size - Buffer size
+ * \return		>=0 - number of bytes copied, <0 - error code
+ */
+int bdmf_attrelem_find(bdmf_object_handle mo, bdmf_attr_id attr,
+		       bdmf_index *index, void *buffer, uint32_t size);
+
+
+/** Find attribute array element index given its value as string.
+ *
+ * \param[in]		mo - Managed object handle
+ * \param[in]		attr - Attribute handle
+ * \param[in, out]	index - Array element index (handle). On input may
+ * 				contain a hint
+ * \param[in]		val -  Value in external format - 0-terminated string
+ * \return		0 - OK, <0 - error
+ */
+int bdmf_attrelem_find_by_string(bdmf_object_handle mo, bdmf_attr_id attr,
+				 bdmf_index *index, const char *val);
+
+
+/** Set a number of attributes in a single call.
+ * 
+ * The attributes and values are passed as a comma-delimted
+ * ASCII string of name=value pairs.\n
+ * For enum attrubutes "=value" can be omitted. In this case
+ * the 1st enum value is assumed. For example, if "bool_attr" is
+ * boolean attribute, specifying "bool_attr" in the attribute string without value
+ * means settings its value "=true", because "true" is the 1st value of "boolean"
+ * enumeration.\n
+ * For aggregate attributes the value must be surrounded by "{}" brackets and
+ * has the following format:\n
+ * aggr_attr1={field_name1=value1,field_name2=value2}\n
+ * Nested "{} brackets are allowed to accommodate the case of aggregate attribute's
+ * field itself being an aggregate.\n
+ * 
+ * Example of attribute string:\n
+ * attr1=25,attr2=string1,attr3=enum_value3,attr4="string 4",enum_attr5,aggr_attr1={f1=v1,f2=v2}\n
+ * 
+ * \param[in]	mo - Managed object handle
+ * \param[in]	set - Comma delimited list of name=value pairs
+ * \return		0 - OK, <0 - error
+ */
+int bdmf_configure(bdmf_object_handle mo, const char *set);
+
+
+/** mattr operation */
+typedef enum {
+	bdmf_attr_op_any,	/* Set/Get attribute */
+	bdmf_attr_op_set,	/* Set attribute */
+	bdmf_attr_op_get,	/* Get attribute */
+} bdmf_attr_op_t;
+
+/** Attribute value */
+typedef struct {
+	bdmf_attr_type_t val_type;	/* value type */
+	union {
+		bdmf_number num;	/* number , boolean, enum */
+		const char *s;		/* Value in string format */
+		bdmf_number *pnum;	/* Pointer to value for "get_as_num"
+					 * operation */
+		/* Raw buffer format */
+		struct {
+			void *ptr;
+			uint16_t len;
+		} buf;
+	} x;
+} bdmf_attr_val_t;
+
+/* mattr set entry */
+typedef struct bdmf_mattr_entry {
+	bdmf_attr_id aid;	/* Attribute id */
+	bdmf_index index;	/* Array index */
+	bdmf_attr_val_t val;	/* Value */
+} bdmf_mattr_entry_t;
+
+/** Attribute set.
+ * All fields in this structure are internal and should not be touched
+ * by the drivers;
+ */
+struct bdmf_mattr
+{
+	uint32_t magic;	/* Magic number to distinguish from other entities */
+	bdmf_attr_op_t oper;	/* Mattr operation */
+	bdmf_type_handle drv;   /* Type handle */
+	int max_entries;	/* Max number of entries in entries[] array */
+	int num_entries;	/* Current number of entries in entries[] array */
+	int dynamic;	/* 1=allocated dynamically */
+	bdmf_mattr_entry_t entries[0]; /**< Mattr entries */
+};
+
+
+static inline bdmf_mattr_t *bdmf_mattr_init(bdmf_mattr_t *mattr, bdmf_type_handle drv)
+{
+	mattr->drv = drv;
+	mattr->magic=BDMF_MATTR_MAGIC;
+	mattr->num_entries = 0;
+	mattr->max_entries = bdmf_type_num_attrs(drv);
+	mattr->oper = bdmf_attr_op_any;
+	mattr->dynamic = 0;
+	return mattr;
+}
+
+/** Declare mattr descriptor
+ * \param[in]	name - Variable name to declare of type (bdmf_mattr_t *)
+ * \param[in]	op - Operation
+ * \param[in]	drv - Type for which the set is created (FFU)
+ */
+#define BDMF_MATTR(name, drv)		   \
+	struct { \
+		bdmf_mattr_t hdr; \
+		bdmf_mattr_entry_t entries[bdmf_type_num_attrs(drv)]; \
+	} __ ## name; \
+	bdmf_mattr_handle name = (bdmf_object_handle)bdmf_mattr_init( \
+			(bdmf_mattr_t *)&__ ## name, drv)
+
+
+/** Allocate mattr descriptor.
+ *
+ * This function provides an alternative to BDMF_MATTR macro.
+ * Unlike BDMF_MATTR which allocates mattr descriptor on the stack,
+ * bdmf_mattr_alloc() uses dynamic memory allocation.
+ * Descriptor allocated by bdmf_mattr_alloc() must be released
+ * using bdmf_free()
+ * \param[in]	drv - Object type mattr block will be used for
+ * \return mattr block pointer or NULL if no memory
+ */
+bdmf_mattr_handle bdmf_mattr_alloc(bdmf_type_handle drv);
+
+/** Set a number of object attributes in a single call.
+ *
+ * \param[in]	mo - Managed object handle
+ * \param[in]	mattr - Attribute set.
+ *			The set is released automatically.
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_mattr_set(bdmf_object_handle mo, bdmf_mattr_handle mattr);
+
+/** Get a number of object attributes in a single call.
+ *
+ * \param[in]	mo - Managed object handle
+ * \param[in]	mattr - Attribute set to be fetched
+ * \return	0 - OK, <0 - error
+ */
+int bdmf_mattr_get(bdmf_object_handle mo, bdmf_mattr_handle mattr);
+
+/** Release mattr chain
+ *
+ * \param[in]	mattr - Mattr to be released
+ */
+void bdmf_mattr_free(bdmf_mattr_handle mattr);
+
+/** Trace levels
+ */
+typedef enum
+{
+	bdmf_trace_level_none,	/* Tracing is disabled */
+	bdmf_trace_level_error,	/* Trace errors only */
+	bdmf_trace_level_info,	/* Trace errors and info, including
+				 * configuration changes */
+	bdmf_trace_level_debug,	/* Trace everything */
+} bdmf_trace_level_t;
+
+#ifndef BDMF_NO_TRACE
+
+/** Global trace level (\ref bdmf_trace_level_t) */
+extern int bdmf_global_trace_level;
+
+/* Add trace entry
+ * \param[in]	fmt - printf-like format
+ */
+void bdmf_trace(const char *fmt, ...) __attribute__((format(printf, 1, 2)));
+
+/** Print error trace conditional on global trace level
+ * \param[in]	fmt - printf-like format
+ * \param[in]	args - 0 or more parameters
+ */
+#define BDMF_TRACE_ERR(fmt, args...) \
+	do { \
+		if (bdmf_global_trace_level >= bdmf_trace_level_error) \
+			bdmf_trace("ERR: %s#%d: " fmt, __FUNCTION__, \
+				   __LINE__, ## args); \
+	} while(0)
+
+
+/** Print info trace conditional on global trace level
+ * \param[in]	fmt - printf-like format
+ * \param[in]	args - 0 or more parameters
+ */
+#define BDMF_TRACE_INFO(fmt, args...) \
+	do { \
+		if (bdmf_global_trace_level >= bdmf_trace_level_info) \
+			bdmf_trace("INF: %s#%d: " fmt, __FUNCTION__, \
+				__LINE__, ## args); \
+	} while(0)
+
+
+/** Print info or error trace conditional on global trace level and return
+ * \param[in]	rc - return code. 0=info trace, !=0-error trace
+ * \param[in]	fmt - printf-like format
+ * \param[in]	args - 0 or more parameters
+ */
+#define BDMF_TRACE_RET(rc, fmt, args...) \
+	do { \
+		if (rc) \
+			BDMF_TRACE_ERR("status:%s " fmt, bdmf_strerror(rc), \
+					## args); \
+		else \
+			BDMF_TRACE_INFO("success " fmt, ## args); \
+		return (rc); \
+	} while(0)
+
+
+#ifdef BDMF_DEBUG
+
+/** Print debug trace conditional on global trace level
+ * \param[in]	fmt - printf-like format
+ * \param[in]	args - 0 or more parameters
+ */
+#define BDMF_TRACE_DBG(fmt, args...) \
+	do { \
+		if (bdmf_global_trace_level >= bdmf_trace_level_debug) \
+			bdmf_trace("DBG: %s#%d: " fmt, __FUNCTION__, \
+				__LINE__, ## args); \
+	} while(0)
+
+#else /* #ifdef BDMF_DEBUG */
+
+#define BDMF_TRACE_DBG(fmt, args...)
+
+#endif /* #ifdef BDMF_DEBUG */
+
+#else /* #ifdef BDMF_NO_TRACE  */
+#define BDMF_TRACE_RET(rc, fmt, args...) do { return rc; } while (0)
+#define BDMF_TRACE_INFO(fmt, args...)
+#define BDMF_TRACE_ERR(fmt, args...)
+#define BDMF_TRACE_DBG(fmt, args...)
+#define bdmf_trace printf
+#endif
+
+/** Acquire global lock.
+ * The functions takes ownership of global recursive mutex.
+ * Typically it is used to protect multiple operations in the same transaction.
+ * For example, read-modify-write. \n
+ * There is no need to check return code if calling task doesn't expect signals.
+ * The global lock is recursive. That is,
+ * - a task can take the lock it owns multiple times.
+ * - if task B tries to take the lock held by task A - it blocks
+ * - lock can only be released by the task that owns it
+ * \return  0 - OK \n
+ *	  BDMF_ERR_INTR - interrupted by signal
+ */
+int bdmf_lock(void);
+
+/** Release global lock.
+ * Release global lock acquired by bdmf_lock() call.
+ */
+void bdmf_unlock(void);
+
+#endif /* _BDMF_INTERFACE_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/bdmf_session.h b/arch/arm/mach-bcmbca/xrdp/bdmf_session.h
new file mode 100644
index 0000000000..a039af7876
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bdmf_session.h
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ * 
+ */
+
+/*******************************************************************
+ * bdmf_session.h
+ *
+ * BL framework - management session
+ *
+ *******************************************************************/
+
+#ifndef BDMF_SESSION_H
+
+#define BDMF_SESSION_H
+
+#include <bdmf_system.h>
+#include <stdarg.h>
+
+/** Access rights */
+typedef enum {
+	BDMF_ACCESS_GUEST,	/* Guest. Doesn't have access to commands and
+				 * directories registered with ADMIN rights */
+	BDMF_ACCESS_ADMIN,	/* Administrator: full access */
+	BDMF_ACCESS_DEBUG,	/* Administrator: full access + extended debug
+				 * features */
+} bdmf_access_right_t;
+
+/** Line edit mode */
+typedef enum {
+	BDMF_LINE_EDIT_DEFAULT,	/* Enable line editing and history if
+				 * CONFIG_EDITLINE is defined, disable otherwise */
+	BDMF_LINE_EDIT_ENABLE,	/* Enable line editing. Requires CONFIG_EDITLINE
+				 * define and libedit-dev library */
+	BDMF_LINE_EDIT_DISABLE,	/* Disable line editing and history */
+} bdmf_line_edit_mode_t;
+
+/** Hex dump format */
+typedef enum {
+	BDMF_HEX_DUMP_FORMAT_DEFAULT,	/* Default format of hex dump */
+	BDMF_HEX_DUMP_FORMAT_BYTE,	/* Hex dump format of separate bytes */
+} bdmf_hex_dump_format_t;
+
+/* Management session handle */
+typedef struct bdmf_session bdmf_session;
+
+/* Management session handle */
+typedef struct bdmf_session *bdmf_session_handle;
+
+/** Session parameters structure.
+ * See \ref bdmf_session_open
+ */
+typedef struct bdmf_session_parm {
+	const char *name;	/**< Session name */
+	void *user_priv;	/**< Private user's data */
+
+	/** Session's output function. NULL=use write(stdout)
+	 * returns the number of bytes written or <0 if error
+	 */
+	int (*write)(bdmf_session_handle session, const char *buf, uint32_t size);
+
+	/** Session line input function. NULL=use default(stdin[+line edit) */
+	char *(*gets)(bdmf_session_handle session, char *buf, uint32_t size);
+
+	/** Access rights */
+	bdmf_access_right_t access_right;
+
+	/** Line editing mode */
+	bdmf_line_edit_mode_t line_edit_mode;
+
+	/** Extra data size to be allocated along with session control block.
+	 * The extra data is accessible using bdmf_session_data().
+	 */
+	uint32_t extra_size;
+
+	/** Hex dump format */
+	bdmf_hex_dump_format_t hex_dump_format;
+} bdmf_session_parm_t;
+
+
+/** Open management session
+ *
+ * Monitor supports multiple simultaneous sessions with different
+ * access rights.
+ *
+ * \param[in]   parm - Session parameters. Must not be allocated on the stack.
+ * \param[out]  p_session - Session handle
+ * \return	0 = ok, <0 = error code
+ */
+int bdmf_session_open(const bdmf_session_parm_t *parm,
+		      bdmf_session_handle *p_session);
+
+
+/** Close management session.
+ * \param[in]   session - Session handle
+ */
+void bdmf_session_close(bdmf_session_handle session);
+
+
+/** Write function.
+ * Write buffer to the current session.
+ * \param[in]   session - Session handle. NULL=use stdout
+ * \param[in]   buf - output buffer
+ * \param[in]   size - number of bytes to be written
+ * \return	>=0 - number of bytes written. <0 - output error
+ */
+int bdmf_session_write(bdmf_session_handle session, const char *buf,
+		       uint32_t size);
+
+
+/** Read line
+ * \param[in]		session - Session handle. NULL=use default
+ * \param[in,out]	buf - input buffer
+ * \param[in]		size - buf size
+ * \return		buf if successful, NULL if EOF or error
+ */
+char *bdmf_session_gets(bdmf_session_handle session, char *buf, uint32_t size);
+
+
+/** Print function.
+ * Prints in the context of current session.
+ * \param[in]	session - Session handle. NULL=use stdout
+ * \param[in]	format - print format - as in printf
+ */
+void bdmf_session_print(bdmf_session_handle session, const char *format, ...)
+#ifndef BDMF_SESSION_DISABLE_FORMAT_CHECK
+__attribute__((format(printf, 2, 3)))
+#endif
+;
+
+
+/** Print function.
+ * Prints in the context of current session.
+ * \param[in]	session - Session handle. NULL=use stdout
+ * \param[in]	format - print format - as in printf
+ * \param[in]	ap - parameters list. Undefined after the call
+ */
+void bdmf_session_vprint(bdmf_session_handle session, const char *format,
+			 va_list ap);
+
+/** Print buffer in hexadecimal format
+ * \param[in]	session - Session handle. NULL=use stdout
+ * \param[in]	buffer - Buffer address
+ * \param[in]	offset - Start offset in the buffer
+ * \param[in]	count - Number of bytes to dump
+ */
+void bdmf_session_hexdump(bdmf_session_handle session, void *buffer,
+			  uint32_t offset, uint32_t count);
+
+/** Get extra data associated with the session
+ * \param[in]	session - Session handle. NULL=default session
+ * \return extra_data pointer or NULL if there is no extra data
+ */
+void *bdmf_session_data(bdmf_session_handle session);
+
+
+/** Get user_priv provided in session parameters when it was registered
+ * \param[in]	session - Session handle. NULL=default session
+ * \return usr_priv value
+ */
+void *bdmf_session_user_priv(bdmf_session_handle session);
+
+
+/** Set user_priv provided in session parameters when it was registered
+ * \param[in]	session - Session handle. NULL=default session
+ * \param[in]	usr_priv - user_priv value
+ * \return old usr_priv value
+ */
+void *bdmf_session_user_priv_set(bdmf_session_handle session, void *user_priv);
+
+
+/** Get session name
+ * \param[in]	session - Session handle. NULL=use stdin
+ * \return session name
+ */
+const char *bdmf_session_name(bdmf_session_handle session);
+
+
+/** Get session access rights
+ * \param[in]	session - Session handle. NULL=default debug session
+ * \return session access right
+ */
+bdmf_access_right_t bdmf_session_access_right(bdmf_session_handle session);
+
+
+/** Context extension
+ *
+ * - if no command - display list of command or extend command
+ * - if prev char is " "
+ *      - if positional and next parm is enum - show/extends list of matching values
+ *      - else - show/extend list of unused parameters
+ *   else
+ *      - if entering value and enum - show/extends list of matching values
+ *      - else - show/extend list of matching unused parameters
+ *
+ * \param[in]	session - Session handle
+ * \param[in]	input_string - String to be parsed
+ * \param[out]	insert_str - String to insert at cursor position
+ * \param[in]	insert_size - Insert buffer size
+ * \return	=0  - OK; -EINVAL - parsing error
+ */
+int bdmf_extend(bdmf_session_handle session, char *input_string,
+		char *insert_str, uint32_t insert_size);
+
+
+#ifdef BDMF_INTERNAL
+
+#define BDMF_SESSION_OUTBUF_LEN   2048
+
+/* editline functionality */
+/* If libedit is included - it takes precedence */
+#ifdef CONFIG_LIBEDIT
+#include <histedit.h>
+#undef CONFIG_LINENOISE
+#endif /* #ifdef CONFIG_LIBEDIT */
+
+#ifdef CONFIG_LINENOISE
+#include <linenoise.h>
+#endif
+
+/* Management session structure */
+struct bdmf_session {
+	bdmf_session *next;
+	bdmf_session_parm_t parms;
+	uint32_t magic;
+#define BDMF_SESSION_MAGIC	(('s'<<24)|('e'<<16)|('s'<<8)|'s')
+#define BDMF_SESSION_MAGIC_DEL	(('s'<<24)|('e'<<16)|('s'<<8)|'~')
+
+	/* Line editing and history support */
+#ifdef CONFIG_LIBEDIT
+	EditLine *el;
+	History *history;
+	HistEvent histevent;
+#endif
+#ifdef CONFIG_LINENOISE
+	linenoiseSession *ln_session;
+#endif
+	char outbuf[BDMF_SESSION_OUTBUF_LEN];
+
+	/* Followed by session data */
+};
+#endif
+
+#endif /* #ifndef BDMF_SESSION_H */
diff --git a/arch/arm/mach-bcmbca/xrdp/bdmf_shell.h b/arch/arm/mach-bcmbca/xrdp/bdmf_shell.h
new file mode 100644
index 0000000000..5a422b3e16
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bdmf_shell.h
@@ -0,0 +1,597 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ * 
+ */
+
+/*******************************************************************
+ * bdmf_shell.h
+ *
+ * BL framework - shell API
+ *
+ *******************************************************************/
+
+#ifndef BDMF_MON_H
+
+#define BDMF_MON_H
+
+#include <bdmf_system.h>
+#include <bdmf_session.h>
+
+/** \defgroup bdmf_mon Broadlight Monitor Module (CLI)
+ * Broadlight Monitor is used for all configuration and status monitoring.\n
+ * It doesn't have built-in scripting capabilities (logical expressions, loops),
+ * but can be used in combination with any available scripting language.\n
+ * Broadlight Monitor replaces Broadlight Shell and supports the following features:\n
+ * - parameter number and type validation (simplifies command handlers development)
+ * - parameter value range checking
+ * - mandatory and optional parameters
+ * - positional and named parameters
+ * - parameters with default values
+ * - enum parameters can have arbitrary values
+ * - automatic command help generation
+ * - automatic or user-defined command shortcuts
+ * - command handlers return completion status to enable scripting
+ * - multiple sessions
+ * - session access rights
+ * - extendible. Supports user-defined parameter types
+ * - relatively low stack usage
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define BDMFMON_MAX_SEARCH_SUBSTR_LENGTH 80
+
+/** Monitor entry handle
+ */
+typedef struct bdmfmon_entry *bdmfmon_handle_t;
+
+/* if BDMFMON_PARM_USERIO flag is set:
+   low_val: t_userscanf_f function
+   high_val: t_userprintf_f function
+*/
+
+/** Function parameter structure */
+typedef struct bdmfmon_cmd_parm bdmfmon_cmd_parm_t;
+
+/** Parameter type */
+typedef enum
+{
+    BDMFMON_PARM_NONE,
+    BDMFMON_PARM_DECIMAL,         /**< Decimal number */
+    BDMFMON_PARM_DECIMAL64,       /**< Signed 64-bit decimal */
+    BDMFMON_PARM_UDECIMAL,        /**< Unsigned decimal number */
+    BDMFMON_PARM_UDECIMAL64,      /**< Unsigned 64-bit decimal number */
+    BDMFMON_PARM_HEX,             /**< Hexadecimal number */
+    BDMFMON_PARM_HEX64,           /**< 64-bit hexadecimal number */
+    BDMFMON_PARM_NUMBER,          /**< Decimal number or hex number prefixed by 0x */
+    BDMFMON_PARM_NUMBER64,        /**< 64bit decimal number or hex number prefixed by 0x */
+    BDMFMON_PARM_UNUMBER,         /**< Unsigned decimal number or hex number prefixed by 0x */
+    BDMFMON_PARM_UNUMBER64,       /**< Unsigned 64bit decimal number or hex number prefixed by 0x */
+    BDMFMON_PARM_STRING,          /**< String */
+    BDMFMON_PARM_ENUM,            /**< Enumeration */
+    BDMFMON_PARM_IP,              /**< IP address n.n.n.n */
+    BDMFMON_PARM_IPV6,            /**< IPv6 address */
+    BDMFMON_PARM_MAC,             /**< MAC address xx:xx:xx:xx:xx:xx */
+    BDMFMON_PARM_BUFFER,          /**< Byte array */
+
+    BDMFMON_PARM_USERDEF          /**< User-defined parameter. User must provide scan_cb */
+} bdmfmon_parm_type_t;
+
+/** Enum attribute value.
+ *
+ *  Enum values is an array of bdmfmon_enum_val_t terminated by element with name==NULL
+ *
+ */
+typedef struct bdmfmon_enum_val
+{
+    const char *name;           /**< Enum symbolic name */
+    long val;                   /**< Enum internal value */
+    bdmfmon_cmd_parm_t *parms;  /**< Extension parameter table for enum-selector */
+} bdmfmon_enum_val_t;
+#define BDMFMON_MAX_ENUM_VALUES   128     /**< Max number of enum values */
+#define BDMFMON_ENUM_LAST     { NULL, 0}  /**< Last entry in enum table */
+
+/** Boolean values (true/false, yes/no, on/off)
+ *
+ */
+extern bdmfmon_enum_val_t bdmfmon_enum_bool_table[];
+
+/* Monitor data types */
+typedef long bdmfmon_number;      /**< Type underlying BDMFMON_PARM_NUMBER, BDMFMON_PARM_DECIMAL */
+typedef long bdmfmon_unumber;     /**< Type underlying BDMFMON_PARM_HEX, BDMFMON_PARM_UDECIMAL */
+typedef long bdmfmon_number64;    /**< Type underlying BDMFMON_PARM_NUMBER64, BDMFMON_PARM_DECIMAL64 */
+typedef long bdmfmon_unumber64;   /**< Type underlying BDMFMON_PARM_HEX64, BDMFMON_PARM_UDECIMAL64 */
+
+/** Parameter value */
+typedef union bdmfmon_parm_value
+{
+    long number;                    /**< Signed number */
+    unsigned long unumber;          /**< Unsigned number */
+    long long number64;             /**< Signed 64-bit number */
+    unsigned long long unumber64;   /**< Unsigned 64-bit number */
+    char *string;                   /**< 0-terminated string */
+    double d;                       /**< Double-precision floating point number */
+    char mac[6];                    /**< MAC address */
+}  bdmfmon_parm_value_t;
+
+/** User-defined scan function.
+ * The function is used for parsing user-defined parameter types
+ * Returns: 0-ok, <=error
+ *
+ */
+typedef int (*bdmfmon_scan_cb_t)(const bdmfmon_cmd_parm_t *parm, bdmfmon_parm_value_t *value,
+    const char *string_val);
+
+/** User-defined print function.
+ * The function is used for printing user-defined parameter types
+ *
+ */
+typedef void (*bdmfmon_format_cb_t)(const bdmfmon_cmd_parm_t *parm, bdmfmon_parm_value_t value,
+    char *buffer, int size);
+
+
+/** Function parameter structure */
+struct bdmfmon_cmd_parm
+{
+   const char *name;            /**< Parameter name. Shouldn't be allocated on stack! */
+   const char *description;     /**< Parameter description. Shouldn't be allocated on stack! */
+   bdmfmon_parm_type_t type;       /**< Parameter type */
+   uint8_t flags;               /**< Combination of BDMFMON_PARM_xx flags */
+#define BDMFMON_PARM_FLAG_OPTIONAL   0x01 /**< Parameter is optional */
+#define BDMFMON_PARM_FLAG_DEFVAL     0x02 /**< Default value is set */
+#define BDMFMON_PARM_FLAG_RANGE      0x04 /**< Range is set */
+#define BDMFMON_PARM_FLAG_ENUM_EOL_SEPARATOR 0x08 /**< Use new line as enum separator */
+#define BDMFMON_PARM_FLAG_EOL        0x20 /**< String from the current parser position till EOL */
+#define BDMFMON_PARM_FLAG_SELECTOR   0x40 /**< Parameter selects other parameters */
+#define BDMFMON_PARM_FLAG_ASSIGNED   0x80 /**< Internal flag: parameter is assigned */
+
+   bdmfmon_number low_val;       /**< Low val for range checking */
+   bdmfmon_number hi_val;        /**< Hi val for range checking */
+   bdmfmon_parm_value_t value;     /**< Value */
+   bdmfmon_enum_val_t *enum_table; /**< Table containing { enum_name, enum_value } pairs */
+   bdmfmon_scan_cb_t scan_cb;      /**< User-defined scan function for BDMFMON_PARM_USERDEF parameter type */
+   bdmfmon_format_cb_t format_cb;  /**< User-defined format function for BDMFMON_PARM_USERDEF parameter type */
+   uint32_t max_array_size;     /**< Max array size for array-parameter */
+   uint32_t array_size;         /**< Actual array size for array-parameter */
+   bdmfmon_parm_value_t *values;   /**< Array values */
+   void *user_data;             /**< User data - passed transparently to command handler */
+};
+
+/** Command parameter list terminator */
+#define BDMFMON_PARM_LIST_TERMINATOR  { .name=NULL, .type=BDMFMON_PARM_NONE }
+
+/** Helper macro: make simple parameter
+ * \param[in] _name     Parameter name
+ * \param[in] _descr    Parameter description
+ * \param[in] _type     Parameter type
+ * \param[in] _flags    Parameter flags
+ */
+#define BDMFMON_MAKE_PARM(_name, _descr, _type, _flags) \
+    { .name=(_name), .description=(_descr), .type=(_type), .flags=(_flags) }
+
+/** Helper macro: make simple parameter
+ * \param[in] _name     Parameter name
+ * \param[in] _descr    Parameter description
+ * \param[in] _type     Parameter type
+ * \param[in] _flags    Parameter flags
+ * \param[in] _size     Max array size
+ * \param[in] _values   Array values buffer
+ */
+#define BDMFMON_MAKE_PARM_ARRAY(_name, _descr, _type, _flags, _size, _values) \
+    { .name=(_name), .description=(_descr), .type=(_type), .flags=(_flags),\
+        .max_array_size=(_size), .values=(_values) }
+
+/** Helper macro: make range parameter
+ * \param[in] _name     Parameter name
+ * \param[in] _descr    Parameter description
+ * \param[in] _type     Parameter type
+ * \param[in] _flags    Parameter flags
+ * \param[in] _min      Min value
+ * \param[in] _max      Max value
+ */
+#define BDMFMON_MAKE_PARM_RANGE(_name, _descr, _type, _flags, _min, _max) \
+    { .name=(_name), .description=(_descr), .type=(_type), .flags=(_flags) | BDMFMON_PARM_FLAG_RANGE, \
+        .low_val=(_min), .hi_val=(_max) }
+
+/** Helper macro: make parameter with default value
+ * \param[in] _name     Parameter name
+ * \param[in] _descr    Parameter description
+ * \param[in] _type     Parameter type
+ * \param[in] _flags    Parameter flags
+ * \param[in] _dft      Default value
+ */
+#define BDMFMON_MAKE_PARM_DEFVAL(_name, _descr, _type, _flags, _dft) \
+    { .name=(_name), .description=(_descr), .type=(_type), .flags=(_flags) | BDMFMON_PARM_FLAG_DEFVAL, \
+        .value = {_dft} }
+
+/** Helper macro: make range parameter with default value
+ * \param[in] _name     Parameter name
+ * \param[in] _descr    Parameter description
+ * \param[in] _type     Parameter type
+ * \param[in] _flags    Parameter flags
+ * \param[in] _min      Min value
+ * \param[in] _max      Max value
+ * \param[in] _dft      Default value
+ */
+#define BDMFMON_MAKE_PARM_RANGE_DEFVAL(_name, _descr, _type, _flags, _min, _max, _dft) \
+    { .name=(_name), .description=(_descr), .type=(_type), \
+        .flags=(_flags) | BDMFMON_PARM_FLAG_RANGE | BDMFMON_PARM_FLAG_DEFVAL, \
+        .low_val=(_min), .hi_val=(_max), .value = {_dft} }
+
+/** Helper macro: make enum parameter
+ * \param[in] _name     Parameter name
+ * \param[in] _descr    Parameter description
+ * \param[in] _values   Enum values table
+ * \param[in] _flags    Parameter flags
+ */
+#define BDMFMON_MAKE_PARM_ENUM(_name, _descr, _values, _flags) \
+    { .name=(_name), .description=(_descr), .type=BDMFMON_PARM_ENUM, .flags=(_flags), .enum_table=(_values)}
+
+/** Helper macro: make enum parameter with default value
+ * \param[in] _name     Parameter name
+ * \param[in] _descr    Parameter description
+ * \param[in] _values   Enum values table
+ * \param[in] _flags    Parameter flags
+ * \param[in] _dft      Default value
+ */
+#define BDMFMON_MAKE_PARM_ENUM_DEFVAL(_name, _descr, _values, _flags, _dft) \
+    { .name=(_name), .description=(_descr), .type=BDMFMON_PARM_ENUM, .flags=(_flags) | BDMFMON_PARM_FLAG_DEFVAL,\
+        .enum_table=(_values), .value={.string=_dft} }
+
+/** Helper macro: make enum-selector parameter
+ * \param[in] _name     Parameter name
+ * \param[in] _descr    Parameter description
+ * \param[in] _values   Selector values table
+ * \param[in] _flags    Parameter flags
+ */
+#define BDMFMON_MAKE_PARM_SELECTOR(_name, _descr, _values, _flags) \
+    { .name=(_name), .description=(_descr), .type=BDMFMON_PARM_ENUM, \
+        .flags=(_flags) | BDMFMON_PARM_FLAG_SELECTOR | BDMFMON_PARM_FLAG_ENUM_EOL_SEPARATOR, \
+        .enum_table=(_values) }
+
+/** Helper macro: make buffer parameter
+ * \param[in] _name     Parameter name
+ * \param[in] _descr    Parameter description
+ * \param[in] _flags    Parameter flags
+ * \param[in] _buf      Memory buffer associated with the parameter
+ * \param[in] _size     Buffer size
+ */
+#define BDMFMON_MAKE_PARM_BUFFER(_name, _descr, _flags, _buf, _size) \
+    { .name=(_name), .description=(_descr), .type=BDMFMON_PARM_BUFFER, \
+        .flags=(_flags), .value.buffer = {.start = _buf, .curr = _buf, .len = _size} }
+
+/** Register command without parameters helper */
+#define BDMFMON_MAKE_CMD_NOPARM(dir, cmd, help, cb) \
+    bdmfmon_cmd_add(dir, cmd, cb, help, BDMF_ACCESS_ADMIN, NULL, NULL)
+
+/** Register command helper */
+#define BDMFMON_MAKE_CMD(dir, cmd, help, cb, parms...)                          \
+{                                                                               \
+    static bdmfmon_cmd_parm_t cmd_parms[]={                                     \
+        parms,                                                                  \
+        BDMFMON_PARM_LIST_TERMINATOR                                            \
+    };                                                                          \
+    bdmfmon_cmd_add(dir, cmd, cb, help, BDMF_ACCESS_ADMIN, NULL, cmd_parms); \
+}
+
+/** Optional custom directory handlers */
+typedef void (*bdmfmon_dir_enter_leave_cb)(bdmf_session_handle session, bdmfmon_handle_t dir, int is_enter);
+
+/** Optional command or directory help callback
+ * \param[in]   session     Session handle
+ * \param[in]   h           Command or directory handle
+ * \param[in]   parms       Parameter(s) - the rest of the command string.
+ *                          Can be used for example to get help on individual parameters
+ */
+typedef void (*bdmfmon_help_cb_t)(bdmf_session_handle session, bdmfmon_handle_t h, const char *parms);
+
+/** Optional parameter extend callback
+ * \param[in]   session         Session handle
+ * \param[in]   parm            CLI parameter
+ * \param[in]   partial_value   Parameter value entered so far
+ * \param[out]  insert_str      String to be inserted in input string
+ * \param[in]   insert_size     insert_str buffer size
+ * \returns  0=OK or error code
+ */
+typedef int (*bdmfmon_parm_extend_cb_t)(bdmf_session_handle session, bdmfmon_cmd_parm_t *parm,
+    const char *partial_value, char *insert_str, uint32_t insert_size);
+
+/** Extra parameters of monitor directory.
+ * See \ref bdmfmon_dir_add
+ *
+ */
+typedef struct bdmfmon_dir_extra_parm
+{
+    void *user_priv;            /**< private data passed to enter_leave_cb */
+    bdmfmon_dir_enter_leave_cb enter_leave_cb; /**< callback function to be called when session enters/leavs the directory */
+    bdmfmon_help_cb_t help_cb;     /**< Help function called to print directory help instead of the automatic help */
+} bdmfmon_dir_extra_parm_t;
+
+
+/** Extra parameters of monitor command.
+ * See \ref bdmfmon_cmd_add
+ *
+ */
+typedef struct bdmfmon_cmd_extra_parm
+{
+    bdmfmon_help_cb_t help_cb;                          /**< Optional help callback. Can be used for more sophisticated help, e.g., help for specific parameters */
+    uint32_t flags;                                     /**< Command flags */
+#define BDMFMON_CMD_FLAG_NO_NAME_PARMS   0x00000001     /**< No named parms. Positional only. Can be useful if parameter value can contain ',' */
+    void (*free_parms)(bdmfmon_cmd_parm_t *parms);      /**< Optional user-defined free */
+    uint32_t num_parm_extend;                           /**< Number of entries in parm_extend[] array */
+    bdmfmon_parm_extend_cb_t parm_extend[];             /**< Optional parameter extend callbacks */
+} bdmfmon_cmd_extra_parm_t;
+
+
+/** Monitor command handler prototype */
+typedef int (*bdmfmon_cmd_cb_t)(bdmf_session_handle session, const bdmfmon_cmd_parm_t parm[], uint16_t n_parms);
+
+
+/** Add subdirectory to the parent directory
+ *
+ * \param[in]   parent          Parent directory handle. NULL=root
+ * \param[in]   name            Directory name
+ * \param[in]   help            Help string
+ * \param[in]   access_right    Access rights
+ * \param[in]   extras          Optional directory descriptor. Mustn't be allocated on the stack.
+ * \return      new directory handle or NULL in case of failure
+ */
+bdmfmon_handle_t bdmfmon_dir_add(bdmfmon_handle_t parent, const char *name,
+                             const char *help, bdmf_access_right_t access_right,
+                             const bdmfmon_dir_extra_parm_t *extras);
+
+
+/** Scan directory tree and look for directory named "name".
+ * 
+ * \param[in]   parent          Directory sub-tree root. NULL=root
+ * \param[in]   name            Name of directory to be found
+ * \return      directory handle if found or NULL if not found
+ */
+bdmfmon_handle_t bdmfmon_dir_find(bdmfmon_handle_t parent, const char *name );
+
+
+/** Scan directory tree and look for command named "name".
+ *
+ * \param[in]   parent          Directory sub-tree root. NULL=root
+ * \param[in]   name            Name of command to be found
+ * \return      command handle if found or NULL if not found
+ */
+bdmfmon_handle_t bdmfmon_cmd_find(bdmfmon_handle_t parent, const char *name );
+
+
+/** Get token name
+ * \param[in]   token           Directory or command token
+ * \return      directory token name
+ */
+const char *bdmfmon_token_name(bdmfmon_handle_t token);
+
+/** Find the CLI parameter with the specified name (case insensitive).
+ * \param[in]   session  CLI session
+ * \param[in]   name     Parameter name
+ * \return      The CLI parameter that was found, or NULL if not found
+ */
+bdmfmon_cmd_parm_t *bdmfmon_find_named_parm(bdmf_session_handle session, const char *name);
+
+/** Find the first CLI parameter whose name starts with the specified string (case insensitive).
+ * \param[in]   session  CLI session
+ * \param[in]   prefix   Parameter name prefix
+ * \return      The CLI parameter that was found, or NULL if not found
+ */
+bdmfmon_cmd_parm_t *bdmfmon_find_parm_by_prefix(bdmf_session_handle session, const char *prefix);
+
+/** Open monitor session
+ *
+ * Monitor supports multiple simultaneous sessions with different
+ * access rights.
+ * Note that there already is a default session with full administrative rights,
+ * that takes input from stdin and outputs to stdout.
+ * \param[in]   parm        Session parameters. Must not be allocated on the stack.
+ * \param[out]  p_session   Session handle
+ * \return
+ *      0   =OK\n
+ *      <0  =error code
+ */
+int bdmfmon_session_open(const bdmf_session_parm_t *parm, bdmf_session_handle *p_session);
+
+/** Close monitor session.
+ * \param[in]   session         Session handle
+ */
+void bdmfmon_session_close(bdmf_session_handle session );
+
+/** Add CLI command
+ *
+ * \param[in]   dir             Handle of directory to add command to. NULL=root
+ * \param[in]   name            Command name
+ * \param[in]   cmd_cb          Command handler
+ * \param[in]   help            Help string
+ * \param[in]   access_right    Access rights
+ * \param[in]   extras          Optional extras
+ * \param[in]   parms           Optional parameters array. Must not be allocated on the stack!
+ *                              If parms!=NULL, the last parameter in the array must have name==NULL.
+ * \return
+ *      0   =OK\n
+ *      <0  =error code
+ */
+int bdmfmon_cmd_add(bdmfmon_handle_t dir, const char *name, bdmfmon_cmd_cb_t cmd_cb,
+                  const char *help, bdmf_access_right_t access_right,
+                  const bdmfmon_cmd_extra_parm_t *extras, bdmfmon_cmd_parm_t parms[]);
+
+
+/** Destroy token (command or directory)
+ * \param[in]   token           Directory or command token. NULL=root
+ */
+void bdmfmon_token_destroy(bdmfmon_handle_t token);
+
+/** Parse and execute input string.
+ * input_string can contain multiple commands delimited by ';'
+ * 
+ * \param[in]   session         Session handle
+ * \param[in]   input_string    String to be parsed
+ * \return
+ *      =0  - OK \n
+ *      -EINVAL - parsing error\n
+ *      other - return code - as returned from command handler.
+ *            It is recommended to return -EINTR to interrupt monitor loop.
+ */
+int bdmfmon_parse(bdmf_session_handle session, char *input_string);
+
+/** Read input and parse iteratively until EOF or bdmfmon_is_stopped()
+ *
+ * \param[in]   session         Session handle
+ * \return
+ *      =0  - OK \n
+ */
+int bdmfmon_driver(bdmf_session_handle session);
+
+/** Stop monitor driver.
+ * The function stops \ref bdmfmon_driver
+ * \param[in]   session         Session handle
+ */
+void bdmfmon_stop(bdmf_session_handle session);
+
+/** Returns 1 if monitor session is stopped
+ * \param[in]   session         Session handle
+ * \returns 1 if monitor session stopped by bdmfmon_stop()\n
+ * 0 otherwise
+ */
+int bdmfmon_is_stopped(bdmf_session_handle session);
+
+/** Get current directory for the session,
+ * \param[in]   session         Session handle
+ * \return      The current directory handle
+ */
+bdmfmon_handle_t bdmfmon_dir_get(bdmf_session_handle session );
+
+/** Set current directory for the session.
+ * \param[in]   session         Session handle
+ * \param[in]   dir             Directory that should become current
+ * \return
+ *      =0  - OK
+ *      <0  - error
+ */
+int bdmfmon_dir_set(bdmf_session_handle session, bdmfmon_handle_t dir);
+
+/** Get parameter number given its name.
+ * The function is intended for use by command handlers
+ * \param[in]       session         Session handle
+ * \param[in]       parm_name       Parameter name
+ * \return
+ *  >=0 - parameter number\n
+ *  <0  - parameter with this name doesn't exist
+ */
+int bdmfmon_parm_number(bdmf_session_handle session, const char *parm_name);
+
+/** Get parameter by name
+ * The function is intended for use by command handlers
+ * \param[in]       session         Session handle
+ * \param[in]       parm_name       Parameter name
+ * \return
+ * parameter pointer or NULL if not found
+ */
+bdmfmon_cmd_parm_t *bdmfmon_parm_get(bdmf_session_handle session, const char *parm_name);
+
+/** Check if parameter is set
+ * The function is intended for use by command handlers
+ * \param[in]       session         Session handle
+ * \param[in]       parm_number     Parameter number
+ * \return
+ * TRUE if parameter is set, FALSE otherwise
+ */
+int bdmfmon_parm_is_set(bdmf_session_handle session, int parm_number);
+
+/** Check if parameter is set
+ * \param[in]       session         Session handle
+ * \param[in]       parm_number     Parameter number
+ * \return
+ *  0 if parameter is set\n
+ *  BCM_ERR_NOENT if parameter is not set
+ *  BCM_ERR_PARM if parm_number is invalid
+ */
+int bdmfmon_parm_check(bdmf_session_handle session, int parm_number);
+
+
+/** Get enum's string value given its internal value
+ * \param[in]       table           Enum table
+ * \param[in]       value           Internal value
+ * \return
+ *      enum string value or NULL if internal value is invalid
+ */
+static inline const char *bdmfmon_enum_stringval(const bdmfmon_enum_val_t table[], long value)
+{
+    while(table->name)
+    {
+        if (table->val==value)
+            return table->name;
+        ++table;
+    }
+    return NULL;
+}
+
+
+/** Get enum's parameter string value given its internal value
+ * \param[in]       session         Session handle
+ * \param[in]       parm_number     Parameter number
+ * \param[in]       value           Internal value
+ * \return
+ *      enum string value or NULL if parameter is not enum or
+ *      internal value is invalid
+ */
+const char *bdmfmon_enum_parm_stringval(bdmf_session_handle session, int parm_number, long value);
+
+
+/** Print CLI parameter value
+ * \param[in]       session         Session handle
+ * \param[in]       parm            Parameter
+ */
+void bdmfmon_parm_print(bdmf_session_handle session, const bdmfmon_cmd_parm_t *parm);
+
+
+/** strncpy flavour that always add 0 terminator
+ * \param[in]       dst             Destination string
+ * \param[in]       src             Source string
+ * \param[in]       dst_size        Destination buffer size
+ * \return dst
+ */
+static inline char *bdmfmon_strncpy(char *dst, const char *src, uint32_t dst_size)
+{
+    strncpy(dst, src, dst_size-1);
+    dst[dst_size-1] = 0;
+    return dst;
+}
+
+
+/** strncat flavour that limits size of destination buffer
+ * \param[in]       dst             Destination string
+ * \param[in]       src             Source string
+ * \param[in]       dst_size        Destination buffer size
+ * \return dst
+ */
+static inline char *bdmfmon_strncat(char *dst, const char *src, uint32_t dst_size)
+{
+    uint32_t dst_len = strlen(dst);
+    return strncat(dst, src, dst_size-dst_len-1);
+}
+
+
+/** strdup
+ * \param[in]       str             Destination string
+ * \return dynamically allocated string replica. Caller must release
+ */
+char *bdmfmon_strdup(const char *str);
+
+/* Redefine bdmfmon_session_print --> bdmfmon_print */
+#define bdmfmon_print bdmf_session_print
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} end bcm_cli group */
+
+#endif /* #ifndef BDMF_MON_H */
diff --git a/arch/arm/mach-bcmbca/xrdp/bdmf_system.h b/arch/arm/mach-bcmbca/xrdp/bdmf_system.h
new file mode 100644
index 0000000000..f3c19a17f3
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/bdmf_system.h
@@ -0,0 +1,307 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ * 
+ */
+
+#ifndef _BDMF_SYSTEM_H_
+#define _BDMF_SYSTEM_H_
+
+#include <linux/compat.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#define BDMFSYS_STDIO
+#include <stdint.h>
+#include <errno.h>
+
+#include <bdmf_errno.h>
+#include <bdmf_data_types.h>
+
+#define bdmf_sort(base, num, size, cmp_func, swap_func) \
+		qsort(base, num, size, cmp_func)
+
+#ifndef __PACKING_ATTRIBUTE_STRUCT_END__
+#define __PACKING_ATTRIBUTE_STRUCT_END__ __attribute__ ((packed))
+#endif
+#ifndef __PACKING_ATTRIBUTE_FIELD_LEVEL__
+#define __PACKING_ATTRIBUTE_FIELD_LEVEL__
+#endif
+
+#define BDMF_RX_CSUM_VERIFIED_MASK   0x01
+#define BDMF_RX_CSUM_VERIFIED_SHIFT  0
+#define SECONDS_TO_USEC 1000000
+
+extern uint32_t jiffies;
+
+/* runner reserved ddr tables */
+#define __exit_refok
+#define __init
+
+/* Allocate/release memory */
+bdmf_phys_addr_t rsv_virt_to_phys(volatile void *vir_addr);
+void *rsv_phys_to_virt(bdmf_phys_addr_t phys_addr);
+void *bdmf_alloc_rsv(int size, bdmf_phys_addr_t *phys_addr);
+void *bdmf_rsv_mem_init(void);
+void bdmf_rsv_mem_destroy(void);
+void bdmf_rsv_mem_stats(void);
+
+static inline void *bdmf_alloc(size_t size)
+{
+	return malloc(size);
+}
+
+static inline void *bdmf_calloc(size_t size)
+{
+	void *p = bdmf_alloc(size);
+	if (p)
+		memset(p, 0, size);
+	return p;
+}
+
+static inline void bdmf_free(void *p)
+{
+	free(p);
+}
+
+#define bdmf_alloc_uncached(size, phys_addr_p) bdmf_alloc_rsv(size, phys_addr_p)
+#define bdmf_free_uncached(_virt_p, _phys_addr, _size) do { } while(0)
+
+/* Input/Output */
+#define bdmf_print(format,args...) printf(format, ## args)
+#define bdmf_vprint(format,ap) vprintf(format, ap)
+#define bdmf_print_error(format,args...) \
+	bdmf_print("***Error in %s:%d>"format, __FUNCTION__, __LINE__, ## args)
+
+
+/* Task-aware (recursive) mutex
+ * The same task can take the same mutex multiple times.
+ * However, if task B attempts to take mutex that is already taken by task A,
+ * it will block
+ */
+typedef struct { int initialized; char b[128]; } bdmf_ta_mutex;
+void bdmf_ta_mutex_init(bdmf_ta_mutex *pmutex);
+int  bdmf_ta_mutex_lock(bdmf_ta_mutex *pmutex);
+void bdmf_ta_mutex_unlock(bdmf_ta_mutex *pmutex);
+void bdmf_ta_mutex_delete(bdmf_ta_mutex *pmutex);
+
+#define __BDMF_TA_MUTEX_INITIALIZER(lock) {.initialized = 0}
+
+typedef bdmf_ta_mutex bdmf_reent_fastlock;
+#define bdmf_reent_fastlock_init(plock)  bdmf_ta_mutex_init(plock)
+#define bdmf_reent_fastlock_lock(plock)  bdmf_ta_mutex_lock(plock)
+#define bdmf_reent_fastlock_unlock(plock) bdmf_ta_mutex_unlock(plock)
+
+typedef struct { int initialized; int locked; } bdmf_simple_mutex;
+static inline void bdmf_simple_mutex_init(bdmf_simple_mutex *pmutex)
+{
+	pmutex->locked = 0;
+	pmutex->initialized = 1;
+}
+
+static inline int bdmf_simple_mutex_lock(const char *func, int line,
+					 bdmf_simple_mutex *pmutex)
+{
+	if (!pmutex->initialized)
+		bdmf_simple_mutex_init(pmutex);
+	if (pmutex->locked)
+		bdmf_print("%s:%d> LOCK APPLIED WHEN INTERRUPTS LOCKED (expect "
+			   "re-entrant?)!!!\n", func, line);
+
+	pmutex->locked = 1;
+
+	return 0;
+}
+
+static inline void bdmf_simple_mutex_unlock(const char *func, int line, bdmf_simple_mutex *pmutex)
+{
+	if (!pmutex->initialized)
+		bdmf_simple_mutex_init(pmutex);
+
+	if (!pmutex->locked)
+		bdmf_print("%s:%d> UNLOCK APPLIED WHEN INTERRUPTS "
+			   "UNLOCKED!!!\n", func, line);
+
+	pmutex->locked = 0;
+}
+
+static inline void bdmf_simple_mutex_delete(bdmf_simple_mutex *pmutex)
+{
+	pmutex->locked = 0;
+	pmutex->initialized = 0; 
+}
+
+#define __BDMF_SIMPLE_MUTEX_INITIALIZER(lock) {.initialized = 0}
+
+/* Fast lock/unlock */
+typedef bdmf_simple_mutex bdmf_fastlock;
+#define DEFINE_BDMF_FASTLOCK(lock) \
+	bdmf_fastlock lock = __BDMF_SIMPLE_MUTEX_INITIALIZER(lock)
+#define bdmf_fastlock_init(plock) bdmf_simple_mutex_init(plock)
+#define bdmf_fastlock_lock(plock) \
+	bdmf_simple_mutex_lock(__FUNCTION__, __LINE__, plock)
+#define bdmf_fastlock_unlock(plock) \
+	bdmf_simple_mutex_unlock(__FUNCTION__, __LINE__, plock)
+#define bdmf_fastlock_lock_irq(plock, flags) \
+	do { \
+		bdmf_simple_mutex_lock(__FUNCTION__, __LINE__, plock); \
+		flags = 0; \
+	} while (flags)
+#define bdmf_fastlock_unlock_irq(plock, flags) \
+	bdmf_simple_mutex_unlock(__FUNCTION__, __LINE__, plock)
+
+/* mmap shared area */
+void *bdmf_mmap(const char *fname, uint32_t size);
+
+/* IRQ handling */
+typedef int (*f_bdmf_irq_cb)(int irq, void *data);
+#define BDMFSYS_IRQ__NUM_OF   64
+int bdmf_irq_connect(int irq, f_bdmf_irq_cb cb, void *data);
+int bdmf_irq_free(int irq, f_bdmf_irq_cb cb, void *data);
+void bdmf_irq_raise(int irq);
+
+/*
+ * dcache
+ */
+#define BCM_MAX_PKT_LEN 2048 /* For simulation only */
+
+static inline void bdmf_dcache_flush(unsigned long addr __attribute__((unused)),
+				     unsigned long size __attribute__((unused)))
+{
+}
+
+static inline void bdmf_dcache_inv(unsigned long addr __attribute__((unused)),
+				   unsigned long size __attribute__((unused)))
+{
+}
+
+/*-----------------------------------------------------------------------
+ * Timers
+ * todo: add "real" timer mapping
+ *----------------------------------------------------------------------*/
+
+/** timer handle */
+typedef struct bdmf_timer bdmf_timer_t;
+
+/** timer callback function
+ * \param[in]	timer - timer that has expired
+ * \param[in]	priv - private cookie passed in bdmf_timer_init()
+ */
+typedef void (*bdmf_timer_cb_t)(bdmf_timer_t *timer, unsigned long priv);
+
+struct bdmf_timer {
+	unsigned long priv;
+	bdmf_timer_cb_t cb;
+};
+
+/** Initialize timer
+ * \param[in]	timer - timer handle
+ * \param[in]	cb - callback to be called upon expiration
+ * \param[in]	priv - private cooke to be passed to cb()
+ */
+void bdmf_timer_init(bdmf_timer_t *timer, bdmf_timer_cb_t cb,
+		     unsigned long priv);
+
+/** Start timer
+ * \param[in]	timer - timer handle that has been initialized using
+ * 			bdmf_timer_init()
+ * \param[in]	ticks - number of ticks from now to expiration
+ * \returns	0=OK or error code <0
+ */
+int bdmf_timer_start(bdmf_timer_t *timer, uint32_t ticks);
+
+/** stop timer
+ * \param[in]	timer - timer to be stopped
+ * The function is safe to call even if timer is not running
+ */
+void bdmf_timer_stop(bdmf_timer_t *timer);
+
+/** Delete timer
+ * \param[in]	timer - timer to be deleted
+ * The timer is stopped if running
+ */
+void bdmf_timer_delete(bdmf_timer_t *timer);
+
+/** Convert ms to ticks
+ * \param[in]	ms - ms
+ * \returns timer ticks
+ */
+uint32_t bdmf_ms_to_ticks(uint32_t ms);
+
+
+
+#define BDMF_IRQ_NONE 0		/* IRQ is not from this device */
+#define BDMF_IRQ_HANDLED 1	/* IRQ has been handled */
+
+#define BDMF_IRQF_DISABLED 1	/* Interrupt is disabled after connect */
+
+#ifdef XRDP
+typedef int (*int_cb_t)(int irq, void *priv);
+typedef struct {
+	int irq;
+	int_cb_t int_cb;
+	void *priv;
+} bdmf_int_parm_t;
+#endif
+
+#define MAX_INT_NUM 32
+
+/** Connect system interrupt
+ * \param[in]	irq - IRQ number
+ * \param[in]	cpu - CPU number (for SMP)
+ * \param[in]	flags - IRQ flags
+ * \param[in]	isr - ISR
+ * \param[in]	name - device name
+ * \param[in]	priv - Private cookie
+ * \returns	0=OK, <0- error
+ */
+int bdmf_int_connect(int irq, int cpu, int flags,
+		     int (*isr)(int irq, void *priv), const char *name,
+		     void *priv);
+
+/** Disconnect system interrupt
+ * \param[in]	irq - IRQ number
+ * \param[in]	priv - Private cookie passed in bdmf_int_connect()
+ * \returns	0=OK, <0- error
+ */
+void bdmf_int_disconnect(int irq, void *priv);
+
+/** Unmask IRQ
+ * \param[in]	irq - IRQ
+ */
+static inline void bdmf_int_enable(int irq __attribute__((unused)))
+{
+}
+
+/** Mask IRQ
+ * \param[in]	irq - IRQ
+ */
+static inline void bdmf_int_disable(int irq __attribute__((unused)))
+{
+}
+
+/*-----------------------------------------------------------------------
+ * Endian-related macros and constants.
+ *
+ *  __BYTE_ORDER define is set by GCC compilation environment.
+ *  No need to do anything here.
+ *  The following must be defined:
+ *  __BYTE_ORDER
+ *  __LITTLE_ENDIAN
+ *  __BIG_ENDIAN
+ *  __bswap_16(x)
+ *  __bswap_32(x)
+ *
+ *----------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------
+ * A few defines to make porting of linux drivers into BDMF smoother
+ *----------------------------------------------------------------------*/
+struct module;
+#define __user
+#define __init
+#define __exit
+
+#endif /* _BDMF_SYSTEM_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/data_path_init_basic.c b/arch/arm/mach-bcmbca/xrdp/data_path_init_basic.c
new file mode 100644
index 0000000000..738138c166
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/data_path_init_basic.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+   
+ */
+
+
+#include "rdd.h"
+
+#include "data_path_init_basic.h"
+
+dpi_params_t *p_dpi_cfg;
+
+uintptr_t rdp_runner_core_addr[GROUPED_EN_SEGMENTS_NUM];
+
+static const access_log_tuple_t init_data[] = {
+	#include "data_path_init_basic_data.h"
+	{ (ACCESS_LOG_OP_STOP << 24), 0 }
+};
+
+int data_path_init_basic(dpi_params_t *dpi_params)
+{
+	 int rc = 0;
+
+	p_dpi_cfg = dpi_params;
+
+	printf("%s: Restore HW configuration\n", __func__);
+	rc = access_log_restore(init_data);
+	printf("%s: Restore HW configuration done. rc=%d\n", __func__, rc);
+
+	return rc;
+}
+
diff --git a/arch/arm/mach-bcmbca/xrdp/data_path_init_basic.h b/arch/arm/mach-bcmbca/xrdp/data_path_init_basic.h
new file mode 100644
index 0000000000..4876ec001d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/data_path_init_basic.h
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+   
+ */
+
+#ifndef _DATA_PATH_INIT_BASIC_
+#define _DATA_PATH_INIT_BASIC_
+
+#ifndef XRDP
+#define XRDP
+#endif
+
+/* includes */
+#include "bdmf_data_types.h"
+#include "rdp_common.h"
+
+/* functions */
+int data_path_init(dpi_params_t *dpi_params);
+int data_path_init_basic(dpi_params_t *dpi_params);
+#endif
+
diff --git a/arch/arm/mach-bcmbca/xrdp/packing.h b/arch/arm/mach-bcmbca/xrdp/packing.h
new file mode 100644
index 0000000000..deaa86e5c4
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/packing.h
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2012 Broadcom
+ */
+/*
+*  
+*/
+
+#ifndef __PACKING_H_
+#define __PACKING_H_
+
+#define __PACKING_ATTRIBUTE_STRUCT_END__  __attribute__ ((packed))
+#define __PACKING_ATTRIBUTE_FIELD_LEVEL__ 
+
+#endif
+
diff --git a/arch/arm/mach-bcmbca/xrdp/rdd.h b/arch/arm/mach-bcmbca/xrdp/rdd.h
new file mode 100644
index 0000000000..4a2e848cf1
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdd.h
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef _RDD_H_
+#define _RDD_H_
+
+#include <common.h>
+
+#ifndef __PACKING_ATTRIBUTE_STRUCT_END__
+#include "packing.h"
+#endif
+#include "rdpa_types.h"
+#include "rdpa_cpu_basic.h"
+
+#include "access_macros.h"
+
+#include "rdd_data_structures_auto.h"
+#include "rdd_platform.h"
+
+/* task addresses labels from fw compilation */
+#ifndef CONFIG_BCMBCA_XRDP_GPL
+#include "rdd_runner_labels.h"
+#include "rdd_runner_defs_auto.h"
+#endif
+
+
+#endif /* _RDD_H_ */
+
diff --git a/arch/arm/mach-bcmbca/xrdp/rdd_common.c b/arch/arm/mach-bcmbca/xrdp/rdd_common.c
new file mode 100644
index 0000000000..cd37d0a8c9
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdd_common.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+#include "rdd.h"
+#include "rdd_runner_proj_defs.h"
+
+#define LAYER2_HEADER_COPY_DST_OFFSET_ARRAY(var, offset) \
+	uint16_t var[] = { \
+		[0] = offset - 2,   \
+		[1] = offset - 10,  \
+		[2] = offset - 10,  \
+		[3] = offset - 18,  \
+		[4] = offset - 18,  \
+		[5] = offset - 2,   \
+		[6] = offset - 2,   \
+		[7] = offset - 10,  \
+		[8] = offset - 10,  \
+		[9] = offset - 18,  \
+		[10] = offset + 6,  \
+		[11] = offset - 2,  \
+		[12] = offset - 2,  \
+		[13] = offset - 10, \
+		[14] = offset - 10, \
+		[15] = offset + 6,  \
+		[16] = offset + 6,  \
+		[17] = offset - 2,  \
+		[18] = offset - 2,  \
+		[19] = offset - 10, \
+		[20] = offset + 14, \
+		[21] = offset + 6,  \
+		[22] = offset + 6,  \
+		[23] = offset - 2,  \
+		[24] = offset - 2,  \
+		[25] = offset + 14, \
+		[26] = offset + 14, \
+		[27] = offset + 6,  \
+		[28] = offset + 6,  \
+		[29] = offset - 2,  \
+	}
+
+
+static void __rdd_rx_flow_cfg(uint32_t flow_index, rdd_flow_dest destination,
+			      rdd_rdd_vport vport, uint32_t counter_id)
+{
+	RDD_RX_FLOW_ENTRY_VIRTUAL_PORT_WRITE_G(vport,
+				RDD_RX_FLOW_TABLE_ADDRESS_ARR, flow_index);
+}
+
+void rdd_rx_flow_cfg(uint32_t flow_index, rdd_flow_dest destination,
+		     rdd_rdd_vport vport, uint32_t counter_id)
+{
+
+	RDD_BTRACE("flow_index = %d, destination = %d, vport = %d, counter_id "
+		   "= %d, first_time %d\n", flow_index,	destination, vport,
+		   counter_id, first_time);
+
+	__rdd_rx_flow_cfg(flow_index, destination, vport, counter_id);
+}
+
diff --git a/arch/arm/mach-bcmbca/xrdp/rdd_common.h b/arch/arm/mach-bcmbca/xrdp/rdd_common.h
new file mode 100644
index 0000000000..c665fe2995
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdd_common.h
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2014 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef _RDD_COMMON_H
+#define _RDD_COMMON_H
+
+#include "rdp_platform.h"
+#include "rdd_defs.h"
+
+typedef enum
+{
+	WANBIT,
+	LANBIT,
+	ERRORBIT
+} wan_or_lan_pd_bit_t;
+
+#if defined(CONFIG_PHYS_64BIT)
+/* 64 bit*/
+#define GET_ADDR_HIGH_LOW(msb_addr, lsb_addr, phys_ring_address) \
+	lsb_addr = phys_ring_address & 0xFFFFFFFF; \
+	msb_addr = phys_ring_address >> 32;
+#else
+/* 32 bit */
+#define GET_ADDR_HIGH_LOW(msb_addr, lsb_addr, phys_ring_address) \
+	lsb_addr = ((uint32_t)phys_ring_address & 0xFFFFFFFF); \
+	msb_addr = 0;
+#endif
+
+#define PORT_OR_WAN_FLOW_TO_TX_FLOW(port , dir) (dir == rdpa_dir_us \
+	? WANBIT << RDD_LOG2_NUM_OF_WAN_FLOWS | port \
+	: LANBIT << RDD_LOG2_NUM_OF_WAN_FLOWS | port)
+
+#define RUNNER_CORE_CONTEXT_ADDRESS(rnr_idx)	DEVICE_ADDRESS(RU_BLK(RNR_CNTXT).addr[rnr_idx] + RU_REG_OFFSET(RNR_CNTXT, MEM_ENTRY))
+#define PACKET_BUFFER_PD_PTR(base_addr, task_number) (base_addr + (task_number * sizeof(RDD_PACKET_BUFFER_DTS)))
+
+#define LAYER2_HEADER_COPY_ROUTINE_ARRAY(var, image, prefix) \
+	uint16_t var[] = { \
+		[0] = ADDRESS_OF(image, prefix##_14_bytes_8_bytes_align),  \
+		[1] = ADDRESS_OF(image, prefix##_18_bytes_8_bytes_align),  \
+		[2] = ADDRESS_OF(image, prefix##_22_bytes_8_bytes_align),  \
+		[3] = ADDRESS_OF(image, prefix##_26_bytes_8_bytes_align),  \
+		[4] = ADDRESS_OF(image, prefix##_30_bytes_8_bytes_align),  \
+		[5] = ADDRESS_OF(image, prefix##_14_bytes_4_bytes_align),  \
+		[6] = ADDRESS_OF(image, prefix##_18_bytes_4_bytes_align),  \
+		[7] = ADDRESS_OF(image, prefix##_22_bytes_4_bytes_align),  \
+		[8] = ADDRESS_OF(image, prefix##_26_bytes_4_bytes_align),  \
+		[9] = ADDRESS_OF(image, prefix##_30_bytes_4_bytes_align),  \
+		[10] = ADDRESS_OF(image, prefix##_14_bytes_8_bytes_align), \
+		[11] = ADDRESS_OF(image, prefix##_18_bytes_8_bytes_align), \
+		[12] = ADDRESS_OF(image, prefix##_22_bytes_8_bytes_align), \
+		[13] = ADDRESS_OF(image, prefix##_26_bytes_8_bytes_align), \
+		[14] = ADDRESS_OF(image, prefix##_30_bytes_8_bytes_align), \
+		[15] = ADDRESS_OF(image, prefix##_14_bytes_4_bytes_align), \
+		[16] = ADDRESS_OF(image, prefix##_18_bytes_4_bytes_align), \
+		[17] = ADDRESS_OF(image, prefix##_22_bytes_4_bytes_align), \
+		[18] = ADDRESS_OF(image, prefix##_26_bytes_4_bytes_align), \
+		[19] = ADDRESS_OF(image, prefix##_30_bytes_4_bytes_align), \
+		[20] = ADDRESS_OF(image, prefix##_14_bytes_8_bytes_align), \
+		[21] = ADDRESS_OF(image, prefix##_18_bytes_8_bytes_align), \
+		[22] = ADDRESS_OF(image, prefix##_22_bytes_8_bytes_align), \
+		[23] = ADDRESS_OF(image, prefix##_26_bytes_8_bytes_align), \
+		[24] = ADDRESS_OF(image, prefix##_30_bytes_8_bytes_align), \
+		[25] = ADDRESS_OF(image, prefix##_14_bytes_4_bytes_align), \
+		[26] = ADDRESS_OF(image, prefix##_18_bytes_4_bytes_align), \
+		[27] = ADDRESS_OF(image, prefix##_22_bytes_4_bytes_align), \
+		[28] = ADDRESS_OF(image, prefix##_26_bytes_4_bytes_align), \
+		[29] = ADDRESS_OF(image, prefix##_30_bytes_4_bytes_align), \
+	}
+
+#define ANY_VID 0xFFFF
+
+/* RX APIs*/
+void rdd_rx_flow_cfg(uint32_t flow_index, rdd_flow_dest destination,
+		     rdd_rdd_vport vport, uint32_t cntr_id);
+void rdd_mac_type_cfg(rdd_mac_type wan_mac_type);
+
+/* TX APIs*/
+void rdd_tx_flow_enable(uint16_t port_or_wan_flow, rdpa_traffic_dir dir,
+			bdmf_boolean enable);
+
+#endif /* _RDD_COMMON_H */
diff --git a/arch/arm/mach-bcmbca/xrdp/rdd_cpu_rx.c b/arch/arm/mach-bcmbca/xrdp/rdd_cpu_rx.c
new file mode 100644
index 0000000000..3aa129a476
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdd_cpu_rx.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "rdd_cpu_rx.h"
+
+
+
+
diff --git a/arch/arm/mach-bcmbca/xrdp/rdd_cpu_rx.h b/arch/arm/mach-bcmbca/xrdp/rdd_cpu_rx.h
new file mode 100644
index 0000000000..ab2e579a07
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdd_cpu_rx.h
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _RDD_CPU_RX_H_
+#define _RDD_CPU_RX_H_
+
+#include "bdmf_errno.h"
+#include "rdd.h"
+
+#define HOST_BUFFER_SIZE                    2048
+#define RING_INTERRUPT_THRESHOLD_MAX   ((1 << 16) - 1)
+#define CPU_RING_SIZE_32_RESOLUTION 5
+#define CPU_RING_SIZE_64_RESOLUTION 6
+
+#endif /* _RDD_CPU_RX_H_ */
+
diff --git a/arch/arm/mach-bcmbca/xrdp/rdd_cpu_tx.h b/arch/arm/mach-bcmbca/xrdp/rdd_cpu_tx.h
new file mode 100644
index 0000000000..4b3cebf4a1
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdd_cpu_tx.h
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _RDD_CPU_TX_H_
+#define _RDD_CPU_TX_H_
+
+
+typedef struct {
+	void *sysb;		/* Buffer pointer */
+	void *data;		/* Buffer pointer */
+	uint32_t fpm_bn;	/* Buffer number */
+	uint16_t offset;	/* Buffer offset */
+	uint16_t length;	/* Buffer length */
+	uint8_t abs_flag:1;	/* ABS/FPM */
+	uint8_t sbpm_copy:1;	/* copy to SBPM/FPM */
+	uint8_t fpm_fallback:1;	/* if no SBPM copy to FPM */
+	uint8_t reserve:5;
+} pbuf_t;
+
+
+typedef union {
+	uint32_t bn1_or_abs2_or_1588	:18 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	uint32_t data_1588		:18 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	struct {
+		uint32_t ssid		:4  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		uint32_t fpm_fallback	:1  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		uint32_t sbpm_copy	:1  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		uint32_t bn1_or_abs2	:12 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	};
+#else
+	struct {
+		uint32_t bn1_or_abs2	:12 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		uint32_t sbpm_copy	:1  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		uint32_t fpm_fallback	:1  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		uint32_t ssid		:4  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	};
+#endif
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	struct {
+		uint32_t lag_index	:2  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		uint32_t reserved2	:16 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	};
+#else
+	struct {
+		uint32_t reserved2	:16 __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		uint32_t lag_index	:2  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	};
+#endif
+} cpu_tx_bn1_or_abs2_or_1588;
+
+
+typedef union {
+	uint8_t wan_flow_source_port	:8  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	struct {
+		uint8_t is_vport	:1  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		uint8_t flow_or_port_id	:7  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	};
+#else
+	struct {
+		uint8_t flow_or_port_id	:7  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+		uint8_t is_vport	:1  __PACKING_ATTRIBUTE_FIELD_LEVEL__;
+	};
+#endif
+} cpu_tx_wan_flow_source_port;
+
+typedef union {
+	uint32_t pkt_buf_ptr_low	:32; /* 32 lsb of pointer to abs buffer */
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	struct {
+		uint32_t fpm_bn0	:18; /* fpm number */
+		uint32_t fpm_sop	:11; /* start of packet offset */
+		uint32_t reserved0	:3;
+	};
+#else
+	struct {
+		uint32_t reserved0	:3;
+		uint32_t fpm_sop	:11; /* start of packet offset */
+		uint32_t fpm_bn0	:18; /* fpm number */
+	};
+#endif
+} pkt_buf_ptr_low_or_fpm_t;
+
+typedef union {
+	uint32_t sk_buf_ptr_low		:32;
+#ifndef FIRMWARE_LITTLE_ENDIAN
+	struct {
+		uint32_t data_1558	:18; /* reserved for 1558 data */
+		uint32_t reserved1	:14;
+	};
+#else
+	struct {
+		uint32_t data_1558	:18; /* reserved for 1558 data */
+		uint32_t reserved1	:14;
+	};
+#endif
+} sk_buf_ptr_low_or_data_1588_t;
+
+#endif /* _RDD_CPU_TX_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/rdd_cpu_tx_ring.c b/arch/arm/mach-bcmbca/xrdp/rdd_cpu_tx_ring.c
new file mode 100644
index 0000000000..1b88f38184
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdd_cpu_tx_ring.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+	
+*/
+
+/*
+ * cpu_tx_ring.c
+ */
+
+#include "rdd.h"
+#include "rdd_cpu_tx_ring.h"
+#include "bdmf_errno.h"
+#include "bdmf_session.h"
+#include "rdp_mm.h"
+#if defined(CONFIG_BCMBCA_XRDP_GPL)
+#include "xrdp_drv_rnr_regs.h"
+#else
+#include "xrdp_drv_rnr_regs_ag.h"
+#endif
+
+#define XRDP_USLEEP(_a)		udelay(_a)
+#define XRDP_ERR_MSG(args...)	printf(args)
+
+static RDD_BBH_TX_RING_TABLE_DTS *bbh_pd_table = NULL;
+static RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_DTS *counters_table = NULL;
+static RDD_BBH_TX_BB_DESTINATION_TABLE_DTS *bb_dest_table = NULL;
+static int tx_pd_idx;
+static uint8_t bbh_ingress_counter[8];
+
+#define RDD_CPU_TX_MAX_ITERS	2
+#define RDD_CPU_TX_ITER_DELAY	1000
+#define QM_QUEUE_INDEX_DS_FIRST QM_QUEUE_DS_START
+
+#define RDD_CPU_TX_MAX_BUF_SIZE 2048
+
+static int __rdd_cpu_tx_poll(uint8_t tx_port)
+{
+	volatile RDD_CPU_TX_DESCRIPTOR_DTS *tx_pd;
+	volatile RDD_BBH_TX_EGRESS_COUNTER_ENTRY_DTS *counters_id;
+	int old_packet_size, iter, egress_counter_val;
+	uint8_t *p;
+
+	if (!bbh_pd_table) { /* First call ? */
+		bbh_pd_table = RDD_BBH_TX_RING_TABLE_PTR(
+					get_runner_idx(cfe_core_runner_image));
+		counters_table = RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_PTR(
+					get_runner_idx(cfe_core_runner_image));
+		bb_dest_table = RDD_BBH_TX_BB_DESTINATION_TABLE_PTR(
+					get_runner_idx(cfe_core_runner_image));
+	}
+
+	tx_pd = (volatile RDD_CPU_TX_DESCRIPTOR_DTS *)&bbh_pd_table->entry;
+
+	counters_id = (volatile RDD_BBH_TX_EGRESS_COUNTER_ENTRY_DTS *)&counters_table->entry[0];
+
+	/* Wait until TX_PD becomes available */
+	RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ(old_packet_size, tx_pd);
+
+	/* Wait until BBH is available*/
+	p = (uint8_t *)counters_id;
+
+	/* in 6858 (XRDP_BBH_PER_LAN_PORT)egress counters are in 64 bit alignment),
+	 * in other 1 byte */
+#if defined(XRDP_BBH_PER_LAN_PORT)
+	p = p + (tx_port * EGRESS_COUNTER_SIZE);
+#else
+	p = p + tx_port;
+#endif
+
+	RDD_BBH_TX_EGRESS_COUNTER_ENTRY_COUNTER_READ(egress_counter_val, p);
+
+	for (iter = 0; ((old_packet_size!=0) ||
+			((bbh_ingress_counter[tx_port] - egress_counter_val) >= 8)) &&
+		       (iter < RDD_CPU_TX_MAX_ITERS); iter++) {
+		XRDP_USLEEP(RDD_CPU_TX_ITER_DELAY);
+		RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ(old_packet_size, tx_pd);
+		RDD_BBH_TX_EGRESS_COUNTER_ENTRY_COUNTER_READ(egress_counter_val, p);
+	}
+	if (iter == RDD_CPU_TX_MAX_ITERS) {
+		printf("non empty at index %d or bbh full(ingress=%d, "
+		       "egress=%d,diff=%d)\n", tx_pd_idx,
+		       bbh_ingress_counter[tx_port], egress_counter_val,
+                       bbh_ingress_counter[tx_port] - egress_counter_val);
+		return BDMF_ERR_INTERNAL;
+	}
+
+	return BDMF_ERR_OK;
+}
+
+static uint32_t __rdd_cpu_tx_get_bb_id(uint8_t tx_port)
+{
+#ifdef CONFIG_BCM96858
+	switch (tx_port)
+	{
+	case 0:
+		return BB_ID_TX_BBH_4;
+	case 1:
+		return BB_ID_TX_BBH_1;
+	case 2:
+		return BB_ID_TX_BBH_2;
+	case 3:
+		return BB_ID_TX_BBH_3;
+	case 4:
+		return BB_ID_TX_BBH_0;
+	case 5:
+		return BB_ID_TX_BBH_5;
+	case 6:
+		return BB_ID_TX_BBH_6;
+	case 7:
+		return BB_ID_TX_BBH_7;
+	default:
+		return BB_ID_TX_BBH_0;
+	}
+#else
+	return (BB_ID_TX_LAN + (tx_port << 6));
+#endif
+}
+
+#define MIN_PACKET_LENGTH_WITHOUT_CRC 60
+
+#if defined(CONFIG_BCM63146)
+int rdd_cpu_tx_new(uint8_t *buffer, uint32_t length, uint8_t tx_port)
+{
+	volatile RDD_CPU_TX_DESCRIPTOR_DTS *tx_pd;
+	volatile RDD_BB_DESTINATION_ENTRY_DTS *bb_dest;
+	uint32_t bb_id;
+	uint32_t *tx_buffer_ptr = (uint32_t *)PACKET_BUFFER_POOL_TABLE_ADDR_TX;
+	int rc;
+
+	if (length >= RDD_CPU_TX_MAX_BUF_SIZE) {
+		printf("ERR: can't transmit buffer with length %u longer "
+		       "than %d\n", length, RDD_CPU_TX_MAX_BUF_SIZE);
+		return BDMF_ERR_PARM;
+	}
+
+	rc = __rdd_cpu_tx_poll(tx_port);
+	if (rc)
+		return rc;
+
+	tx_pd = (volatile RDD_CPU_TX_DESCRIPTOR_DTS *)&bbh_pd_table->entry;
+	bb_dest = (volatile RDD_BB_DESTINATION_ENTRY_DTS *)&bb_dest_table->entry;
+
+	/* copy buffer to the fix location */
+	memcpy(tx_buffer_ptr, buffer, length);
+	FLUSH_RANGE(tx_buffer_ptr, length);
+
+	/* complete TX descriptor */
+	RDD_BBH_TX_DESCRIPTOR_LAST_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_ABS_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_0_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_1_WRITE(1, tx_pd);
+
+	bb_id = __rdd_cpu_tx_get_bb_id(tx_port);
+	RDD_BB_DESTINATION_ENTRY_BB_DESTINATION_WRITE(bb_id, bb_dest);
+
+	/*  must be latest write */
+	if (unlikely(length < MIN_PACKET_LENGTH_WITHOUT_CRC))
+		length = MIN_PACKET_LENGTH_WITHOUT_CRC;
+	RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(length, tx_pd);
+
+	WMB();
+
+	/* update ingress counter */
+	bbh_ingress_counter[tx_port] += 1;
+	ag_drv_rnr_regs_cfg_cpu_wakeup_set(
+			get_runner_idx(cfe_core_runner_image),
+			IMAGE_0_CFE_CORE_CPU_TX_THREAD_NUMBER);
+
+	return BDMF_ERR_OK;
+}
+#endif
+
+int rdd_cpu_tx(uint32_t length, uint16_t bn0, uint16_t bn1, uint8_t bns_num,
+	       uint8_t tx_port)
+{
+	volatile RDD_CPU_TX_DESCRIPTOR_DTS *tx_pd;
+	volatile RDD_BB_DESTINATION_ENTRY_DTS *bb_dest;
+	uint32_t bb_id;
+	int rc;
+
+	if (length >= RDD_CPU_TX_MAX_BUF_SIZE) {
+		printf("ERR: can't transmit buffer with length %u longer "
+		       "than %d\n", length, RDD_CPU_TX_MAX_BUF_SIZE);
+		return BDMF_ERR_PARM;
+	}
+
+	rc = __rdd_cpu_tx_poll(tx_port);
+	if (rc)
+		return rc;
+
+	tx_pd = (volatile RDD_CPU_TX_DESCRIPTOR_DTS *)&bbh_pd_table->entry;
+	bb_dest = (volatile RDD_BB_DESTINATION_ENTRY_DTS *)&bb_dest_table->entry;
+
+	/* transmit */
+	memset((void *)tx_pd, 0, sizeof(*tx_pd));
+	RDD_BBH_TX_DESCRIPTOR_SOF_WRITE(0, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_LAST_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_AGG_PD_WRITE(0, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_ABS_WRITE(0, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_SOP_WRITE(0, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_BN0_FIRST_WRITE(bn0, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_BN1_FIRST_WRITE(bn1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_0_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_1_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_BN_NUM_WRITE(bns_num, tx_pd);
+
+	bb_id = __rdd_cpu_tx_get_bb_id(tx_port);
+	RDD_BB_DESTINATION_ENTRY_BB_DESTINATION_WRITE(bb_id, bb_dest);
+
+	/*  must be latest write */
+	if (unlikely(length < MIN_PACKET_LENGTH_WITHOUT_CRC))
+		length = MIN_PACKET_LENGTH_WITHOUT_CRC;
+	RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(length, tx_pd);
+
+	/* update ingress counter */
+	bbh_ingress_counter[tx_port] += 1;
+	ag_drv_rnr_regs_cfg_cpu_wakeup_set(
+			get_runner_idx(cfe_core_runner_image),
+			IMAGE_0_CFE_CORE_CPU_TX_THREAD_NUMBER);
+
+	return BDMF_ERR_OK;
+}
+
diff --git a/arch/arm/mach-bcmbca/xrdp/rdd_cpu_tx_ring.h b/arch/arm/mach-bcmbca/xrdp/rdd_cpu_tx_ring.h
new file mode 100644
index 0000000000..d3848051dd
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdd_cpu_tx_ring.h
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+    
+*/
+
+/*
+ * cpu_tx_ring.h
+ */
+
+#ifndef _CPU_TX_RING_H_
+#define _CPU_TX_RING_H_
+
+
+#if defined(CONFIG_BCM63146)
+int rdd_cpu_tx_new(uint8_t *buffer, uint32_t length, uint8_t tx_port);
+#endif
+int rdd_cpu_tx(uint32_t length, uint16_t bn0, uint16_t bn1, uint8_t bns_num, uint8_t tx_port);
+
+
+#endif /* _CPU_TX_RING_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/rdd_defs.h b/arch/arm/mach-bcmbca/xrdp/rdd_defs.h
new file mode 100644
index 0000000000..bbb85a5787
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdd_defs.h
@@ -0,0 +1,263 @@
+/*
+    <:copyright-BRCM:2014-2016:DUAL/GPL:standard
+    
+       Copyright (c) 2014-2016 Broadcom 
+       All Rights Reserved
+    
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License, version 2, as published by
+    the Free Software Foundation (the "GPL").
+    
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+    
+    
+    A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+    writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+    Boston, MA 02111-1307, USA.
+    
+:>
+*/
+
+#ifndef _RDD_DEFS_H
+#define _RDD_DEFS_H
+
+#include "rdpa_types.h"
+#include "rdpa_cpu_basic.h"
+#include "rdd_runner_proj_defs.h"
+#include "rdd_map_auto.h"
+
+#define ADDRESS_OF(image, task_name) image##_##task_name
+
+#define RDD_LAYER2_HEADER_MINIMUM_LENGTH	14
+#define RDD_MAX_WAN_FLOW			255
+#define RDD_NUM_OF_WAN_FLOWS			256
+#define RDD_LOG2_NUM_OF_WAN_FLOWS		8
+#define RX_FLOW_CONTEXTS_NUMBER			(256 + 64)
+#define TX_FLOW_CONTEXTS_NUMBER			RX_FLOW_CONTEXTS_NUMBER
+#define IPTV_CTX_ENTRY_IDX_NULL			0x0
+#define RDD_PACKET_HEADROOM_OFFSET		18
+#define RDD_CONTEXT_TABLE_SIZE			(64 * 1024)
+
+#define THREAD_WAKEUP_REQUEST(x)		(((x) << 4) + 1)
+
+#define RDD_PHYS_PORT_WAN_PON rdpa_emac__num_of
+
+typedef uint32_t rdd_vport_id_t;
+typedef uint32_t rdd_emac_id_vector_t;
+typedef unsigned long long rdd_vport_vector_t;
+typedef uint32_t rdd_wan_channel_id_t;
+
+typedef enum {
+	rdd_wan_gpon = 0,
+	rdd_wan_epon = 1,
+	rdd_wan_ae = 2,
+}
+rdd_wan_mode_t;
+
+typedef enum {
+	RDD_TX_QUEUE_0 = 0,
+	RDD_TX_QUEUE_1 = 1,
+	RDD_TX_QUEUE_2 = 2,
+	RDD_TX_QUEUE_3 = 3,
+	RDD_TX_QUEUE_4 = 4,
+	RDD_TX_QUEUE_5 = 5,
+	RDD_TX_QUEUE_6 = 6,
+	RDD_TX_QUEUE_7 = 7,
+	RDD_TX_QUEUE_LAST = 7,
+	RDD_TX_QUEUE_NUMBER = RDD_TX_QUEUE_LAST + 1,
+} rdd_tx_queue_id_t;
+
+typedef struct {
+	uint32_t rate;
+	uint32_t limit;
+} rdd_rate_limit_params_t;
+
+typedef struct {
+	uint32_t sustain_budget;
+	rdd_rate_limit_params_t peak_budget;
+	uint32_t peak_weight;
+} rdd_rate_cntrl_params_t;
+
+typedef enum {
+	RDD_RATE_LIMITER_PORT_0 = 0,
+	RDD_RATE_LIMITER_PORT_1 = 1,
+	RDD_RATE_LIMITER_PORT_2 = 2,
+	RDD_RATE_LIMITER_PORT_3 = 3,
+	RDD_RATE_LIMITER_PORT_4 = 4,
+	RDD_RATE_LIMITER_PORT_5 = 5,
+	RDD_RATE_LIMITER_PORT_6 = 6,
+	RDD_RATE_LIMITER_SERVICE_QUEUE_0 = 6,
+	RDD_RATE_LIMITER_PORT_7 = 7,
+	RDD_RATE_LIMITER_PORT_8 = 8,
+	RDD_RATE_LIMITER_PORT_9 = 9,
+	RDD_RATE_LIMITER_PORT_10 = 10,
+	RDD_RATE_LIMITER_PORT_11 = 11,
+	RDD_RATE_LIMITER_PORT_12 = 12,
+	RDD_RATE_LIMITER_PORT_13 = 13,
+	RDD_RATE_LIMITER_SERVICE_QUEUE_7 = 13,
+	RDD_RATE_LIMITER_PORT_14 = 14,
+	RDD_RATE_LIMITER_SERVICE_QUEUE_OVERALL = 14,
+	RDD_RATE_LIMITER_PORT_15 = 15,
+	RDD_RATE_LIMITER_PORT_LAST = 15,
+	RDD_RATE_LIMITER_DISABLED = 16,
+} rdd_rate_limiter_t;
+
+typedef enum {
+	RDD_QUEUE_PROFILE_0 = 0,
+	RDD_QUEUE_PROFILE_1,
+	RDD_QUEUE_PROFILE_2,
+	RDD_QUEUE_PROFILE_3,
+	RDD_QUEUE_PROFILE_4,
+	RDD_QUEUE_PROFILE_5,
+	RDD_QUEUE_PROFILE_6,
+	RDD_QUEUE_PROFILE_7,
+	RDD_QUEUE_PROFILE_DISABLED = 8,
+} rdd_queue_profile_id_t;
+
+typedef enum {
+	RDD_TPID_ID_0 = 0,
+	RDD_TPID_ID_1,
+	RDD_TPID_ID_2,
+	RDD_TPID_ID_3,
+	RDD_TPID_ID_4,
+	RDD_TPID_ID_5,
+	RDD_TPID_ID_6,
+	RDD_TPID_ID_7,
+} rdd_tpid_id_t;
+
+/* alias for backward compatibility */
+typedef rdd_tpid_id_t rdd_tpid_id;
+
+typedef struct {
+	uint32_t min_threshold;
+	uint32_t max_threshold;
+	uint32_t max_drop_probability;
+} rdd_prio_class_thresholds_t;
+
+typedef struct {
+	rdd_prio_class_thresholds_t high_priority_class;
+	rdd_prio_class_thresholds_t low_priority_class;
+	bdmf_boolean us_flow_control_mode; /* 0 for disabled, 1 for enabled */
+} rdd_queue_profile_t;
+
+/* tm - common definitions */
+#define EXPONENT_LIST_LEN	4
+#define MANTISSA_LEN		14
+#define EXPONENT_LEN		2
+#define RL_MAX_BUCKET_SIZE \
+	(((1 << MANTISSA_LEN) - 1) << exponent_list[EXPONENT_LIST_LEN - 1])
+
+typedef uint8_t quantum_number_t;
+
+typedef enum {
+	RDD_SCHED_TYPE_BASIC,
+	RDD_SCHED_TYPE_COMPLEX,
+} rdpa_rdd_sched_type_t;
+
+typedef enum {
+	RDD_RL_TYPE_BASIC,
+	RDD_RL_TYPE_COMPLEX,
+} rdpa_rdd_rl_type_t;
+
+typedef struct {
+	uint8_t exponent;
+	uint16_t mantissa;
+} rdd_rl_float_t;
+
+/* find the first core of module_idx */
+static inline int get_runner_idx(rdp_runner_image_e module_idx)
+{
+	int i;
+
+	for (i = 0; i < NUM_OF_RUNNER_CORES; ++i)
+		if (rdp_core_to_image_map[i] == module_idx)
+			return i;
+
+	return NUM_OF_RUNNER_CORES;
+}
+
+/* returns the i'th bit in a vector */
+static inline int get_location_of_bit_in_mask(uint8_t idx, uint32_t mask)
+{
+	uint8_t i, count = 0;
+
+	for (i = 0; i < 32; ++i) {
+		if (mask & 1)
+			count++;
+		if (idx == count)
+			return i;
+		mask = mask >> 1;
+	}
+	return (-1);
+}
+
+/* count the number of bits in a vector */
+static inline uint8_t asserted_bits_count_get(uint32_t mask)
+{
+	uint8_t i, count = 0;
+
+	for (i = 0; i < 32; ++i) {
+		if (mask & 1)
+			count++;
+		mask = mask >> 1;
+	}
+	return count;
+}
+
+static inline rdd_rl_float_t rdd_rate_limiter_get_floating_point_rep(
+		uint32_t fixed_point, uint32_t *exponent_list)
+{
+	rdd_rl_float_t floating_point = {};
+	uint32_t i;
+
+	for (i = EXPONENT_LIST_LEN - 1; i > 0; i--) {
+		if (fixed_point > (((1 << MANTISSA_LEN) - 1) <<
+				exponent_list[i - 1])) {
+			floating_point.exponent = i;
+			break;
+		}
+	}
+	floating_point.mantissa = fixed_point >>
+			exponent_list[floating_point.exponent];
+	if ((exponent_list[floating_point.exponent] > 0) &&
+	   ((fixed_point >> (exponent_list[floating_point.exponent] - 1)) & 1))
+		floating_point.mantissa++;
+
+	return floating_point;
+}
+
+static inline uint32_t rdd_rate_to_alloc_unit(uint32_t rate, uint32_t period)
+{
+	return ((rate + ((1000000 / period) / 2)) / (1000000 / period));
+}
+
+typedef struct {
+	uint32_t good_tx_packet;
+	uint16_t error_tx_packets_discard;
+} rdd_service_queue_pm_counters_t;
+
+typedef struct {
+	uint32_t rx_packets;
+	uint32_t tx_packets;
+	uint32_t rx_bytes;
+	uint32_t tx_bytes;
+	uint32_t crc_err;
+	uint32_t rx_drop_pkt;
+} rdd_vport_pm_counters_t;
+
+typedef struct {
+	uint8_t to_lan;
+	uint8_t tx_flow;	/**< US: Gem Flow or LLID ; DS : VPORT */
+	rdd_vport_id_t egress_port;
+	rdpa_qos_method qos_method;
+	uint8_t priority;
+	rdpa_forward_action action;	/**< forward/drop/cpu */
+} rdd_ic_context_t;
+
+#define RDD_TRACE(fmt, args...) do { } while (0)
+#define RDD_BTRACE(fmt, args...) do { } while (0)
+
+#endif /* _RDD_DEFS_H */
diff --git a/arch/arm/mach-bcmbca/xrdp/rdd_init.h b/arch/arm/mach-bcmbca/xrdp/rdd_init.h
new file mode 100644
index 0000000000..a039b15488
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdd_init.h
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef _RDD_INIT_H
+#define _RDD_INIT_H
+
+typedef struct
+{
+	uint8_t *ddr0_runner_base_ptr;
+	int is_basic;
+} rdd_init_params_t;
+
+int rdd_init(void);
+void rdd_exit(void);
+
+int rdd_data_structures_init(rdd_init_params_t *init_params);
+
+
+#endif /* _RDD_INIT_H */
diff --git a/arch/arm/mach-bcmbca/xrdp/rdd_platform.h b/arch/arm/mach-bcmbca/xrdp/rdd_platform.h
new file mode 100644
index 0000000000..33de52251d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdd_platform.h
@@ -0,0 +1,172 @@
+/*
+   <:copyright-BRCM:2013-2016:DUAL/GPL:standard
+   
+      Copyright (c) 2013-2016 Broadcom 
+      All Rights Reserved
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License, version 2, as published by
+   the Free Software Foundation (the "GPL").
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   
+   A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+   writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.
+   
+   :>
+ */
+
+#ifndef _RDD_PLATFORM_H
+#define _RDD_PLATFORM_H
+
+#include "rdd_map_auto.h"
+#include "rdd_common.h"
+
+#if defined(XRDP_BBH_PER_LAN_PORT)
+#define EGRESS_COUNTER_SIZE 8
+#else
+#define EGRESS_COUNTER_SIZE 1
+#endif
+
+extern uintptr_t rdp_runner_core_addr[];
+
+#define RDD_VIRT_TO_PHYS(_addr) \
+	virt_to_phys((const volatile void *)(uintptr_t)_addr)
+#define RDD_PHYS_TO_VIRT(_addr) phys_to_virt(_addr)
+#define RDD_RSV_VIRT_TO_PHYS(_addr) \
+	RDD_VIRT_TO_PHYS((volatile void *)(uintptr_t)_addr)
+#define RDD_RSV_PHYS_TO_VIRT(_addr) RDD_PHYS_TO_VIRT(_addr)
+
+typedef enum {
+	rdd_size_8,
+	rdd_size_16,
+	rdd_size_32,
+} rdd_entry_size_t;
+
+typedef struct rdd_module {
+	int (*init)(const struct rdd_module *);
+	uint32_t context_offset;
+	uint32_t context_size;
+	uint32_t res_offset;
+	uint32_t *cfg_ptr;
+	void *params;
+} rdd_module_t;
+
+static inline void _rdd_module_init(rdd_module_t *module)
+{
+	if (module->init)
+		module->init(module);
+}
+
+static inline void _rdd_i_write(uint32_t *addr_arr, uint32_t addr, uint32_t val,
+				uint32_t i, rdd_entry_size_t size)
+{
+	uint32_t *entry;
+	int mem_id;
+
+	for (mem_id = 0; mem_id < GROUPED_EN_SEGMENTS_NUM; mem_id++) {
+		if (addr_arr[mem_id] == INVALID_TABLE_ADDRESS)
+			continue;
+
+		entry = (uint32_t *)(DEVICE_ADDRESS((
+				rdp_runner_core_addr[mem_id] +
+				addr_arr[mem_id]) + addr));
+		switch (size) {
+		case rdd_size_32:
+			MWRITE_I_32(entry, i, val);
+			break;
+		case rdd_size_16:
+			MWRITE_I_16(entry, i, val);
+			break;
+		default:
+			MWRITE_I_8(entry, i, val);
+			break;
+		}
+	}
+}
+
+static inline uint32_t _rdd_i_read(uint32_t *addr_arr, uint32_t addr,
+				   uint32_t i, rdd_entry_size_t size)
+{
+	uint32_t *entry;
+	int mem_id;
+
+	for (mem_id = 0; mem_id < GROUPED_EN_SEGMENTS_NUM; mem_id++) {
+		if (addr_arr[mem_id] == INVALID_TABLE_ADDRESS)
+			continue;
+
+		entry = (uint32_t *)(DEVICE_ADDRESS((
+				rdp_runner_core_addr[mem_id] +
+				addr_arr[mem_id]) + addr));
+		switch (size) {
+		case rdd_size_32:
+			return MGET_I_32(entry, i);
+		case rdd_size_16:
+			return MGET_I_16(entry, i);
+		default:
+			return MGET_I_8(entry, i);
+		}
+	}
+	return 0;
+}
+
+static inline void _rdd_field_write(uint32_t *addr_arr, uint32_t addr,
+				    uint32_t val, uint32_t lsb, uint32_t width,
+				    rdd_entry_size_t size)
+{
+	uint32_t *entry;
+	int mem_id;
+
+	for (mem_id = 0; mem_id < GROUPED_EN_SEGMENTS_NUM; mem_id++) {
+		if (addr_arr[mem_id] == INVALID_TABLE_ADDRESS)
+			continue;
+
+		entry = (uint32_t *)(DEVICE_ADDRESS((
+				rdp_runner_core_addr[mem_id] +
+				addr_arr[mem_id]) + addr));
+		switch (size) {
+		case rdd_size_32:
+			FIELD_MWRITE_32(entry, lsb, width, val);
+			break;
+		case rdd_size_16:
+			FIELD_MWRITE_16(entry, lsb, width, val);
+			break;
+		default:
+			FIELD_MWRITE_8(entry, lsb, width, val);
+			break;
+		}
+	}
+}
+
+static inline uint32_t _rdd_field_read(uint32_t *addr_arr, uint32_t addr,
+				       uint32_t lsb, uint32_t width,
+				       rdd_entry_size_t size)
+{
+	uint32_t *entry;
+	int mem_id;
+
+	for (mem_id = 0; mem_id < GROUPED_EN_SEGMENTS_NUM; mem_id++) {
+		if (addr_arr[mem_id] == INVALID_TABLE_ADDRESS)
+			continue;
+
+		entry = (uint32_t *)(DEVICE_ADDRESS((
+				rdp_runner_core_addr[mem_id] +
+				addr_arr[mem_id]) + addr));
+		switch (size) {
+		case rdd_size_32:
+			return FIELD_MGET_32(entry, lsb, width);
+		case rdd_size_16:
+			return FIELD_MGET_16(entry, lsb, width);
+		default:
+			return FIELD_MGET_8(entry, lsb, width);
+		}
+	}
+	return 0;
+}
+#endif
+
diff --git a/arch/arm/mach-bcmbca/xrdp/rdp_common.h b/arch/arm/mach-bcmbca/xrdp/rdp_common.h
new file mode 100644
index 0000000000..2edfec263f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdp_common.h
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef RDP_COMMON_H_INCLUDED
+#define RDP_COMMON_H_INCLUDED
+
+#include "rdp_platform.h"
+#include "rdd.h"
+#include "access_macros.h"
+
+/* default values for PARSER */
+#define PARSER_TCP_CTL_FLAGS		0x07
+#define PARSER_EXCP_IP_HDR_LEN_ERR	(1 << 0)
+#define PARSER_EXCP_CHKSUM_ERR		(1 << 1)
+#define PARSER_EXCP_ETH_MULCST		(1 << 2)
+#define PARSER_EXCP_IP_MULCST		(1 << 3)
+#define PARSER_EXCP_DISABLE_IP_LEN_ERR	(1 << 4)
+#define PARSER_EXCP_DISABLE_IP_VER_TEST	(1 << 5)
+/* defines the protocol of ppp_code_1 (1 - IPv6, 0 - IPv4) in
+ * register PPP_IP_Protocol_Code */
+#define PARSER_EXCP_PPP_CODE_1_PROTOCOL	(1 << 7) 
+#define PARSER_EXCP_IP_L2_MULCST	(1 << 10)
+#define PARSER_EXCP_L4_INV_5_TUPPLE	(1 << 11)
+#define PARSER_EXCP_UDP_1588		(1 << 12)
+#define PARSER_EXCP_DHCP		(1 << 13)
+/* MAC_SPOF bit is located in bit [3] on the eng_conf register (ENG) */
+#define PARSER_EXCP_MAC_SPOOF		(1 << 3)
+#define PARSER_EXCP_STATUS_BITS	\
+	(PARSER_EXCP_IP_HDR_LEN_ERR | PARSER_EXCP_CHKSUM_ERR | \
+	 PARSER_EXCP_ETH_MULCST | PARSER_EXCP_IP_MULCST | \
+	 PARSER_EXCP_PPP_CODE_1_PROTOCOL | PARSER_EXCP_IP_L2_MULCST | \
+	 PARSER_EXCP_L4_INV_5_TUPPLE | PARSER_EXCP_UDP_1588 | PARSER_EXCP_DHCP)
+/* eng_conf register default configuration*/
+#define PARSER_AH_DETECTION		0x18000 | PARSER_EXCP_MAC_SPOOF
+#define PARSER_PPP_PROTOCOL_CODE_0_IPV4	0x21
+#define PARSER_PPP_PROTOCOL_CODE_1_IPV6	0x57
+#define PARSER_IP_PROTOCOL_IPIP		4
+/* Profile 0 for DS, profile 1 for US */
+#define PARSER_PROFILE_US		0x02
+
+typedef enum {
+	DMA_BUFSIZE_128  = 0,
+	DMA_BUFSIZE_256  = 1,
+	DMA_BUFSIZE_512  = 2,
+	DMA_BUFSIZE_1024 = 3,
+	DMA_BUFSIZE_2048 = 4,
+} drv_rnr_dma_bufsize_t;
+
+typedef enum  ddr_buf_size_e {
+	BUF_256 = 0,
+	BUF_512,
+	BUF_1K,
+	BUF_2K,
+	BUF_4K
+} ddr_buf_size_e;
+
+void lookup_bbh_tx_bufsz_by_fpm_bufsz(uint32_t *fpm_bufsize,
+				      uint8_t *bbh_tx_bufsize);
+void lookup_dma_bufsz_by_fpm_bufsz(uint32_t *fpm_bufsz, uint8_t *dma_bufsz);
+
+typedef struct {
+	uint32_t low;
+	uint8_t high;
+} ddr_addr;
+
+typedef enum {
+	bcm_tag_opcode0,
+	bcm_tag_opcode1
+} bcm_tag_t;
+
+typedef enum {
+	hash_max_16_entries_per_engine,
+	hash_max_32_entries_per_engine,
+	hash_max_64_entries_per_engine,
+	hash_max_128_entries_per_engine,
+	hash_max_256_entries_per_engine,
+	hash_max_512_entries_per_engine,
+	hash_max_1k_entries_per_engine,
+	hash_max_1_5k_entries_per_engine,
+} tbl_size_e;
+
+typedef struct {
+	uint32_t mtu_size;
+	uint32_t headroom_size;
+	bcm_tag_t bcmsw_tag;
+	/* runner tables DDR base address */
+	ddr_addr rdp_phy_ddr_rnr_tables_base;
+	/* runner tables DDR0 virtual base address */
+	void *rdp_ddr_rnr_tables_base_virt;
+	/* fpm pool DDR0 virtual base address for unicast packets */
+	void *rdp_ddr_pkt_base_virt;
+	uint32_t enabled_port_map;
+	uint32_t runner_freq; /* rdp block clock */
+	uint32_t fpm_buf_size;
+	int xfi_port;
+	uint32_t bbh_id_gbe_wan; /* bbh_id for gbe port */
+	/* define the number of queue for DS queues */
+	uint16_t number_of_ds_queues;
+	/* define the number of queue for US queues */
+	uint16_t number_of_us_queues;
+	/* define the number of queue for SERVICE queues */
+	uint16_t number_of_service_queues;
+#ifdef G9991
+	rdpa_emac system_port;
+	uint32_t g9991_port_vec;
+	uint32_t g9991_bbh_vec;
+#endif
+	bdmf_boolean dpu_split_scheduling_mode;
+	tbl_size_e iptv_table_size;
+	tbl_size_e arl_table_size;
+} dpi_params_t;
+
+typedef struct bbh_to_dma_x {
+	bbh_id_e bbh_id;
+	dma_id_e dma_id;
+} bbh_to_dma_x_t;
+
+/* QM queue index */
+typedef uint16_t  rdp_qm_queue_idx_t;
+
+/* FPM pool id */
+typedef enum {
+	FPM_POOL_ID_0 = 0,
+	FPM_POOL_ID_1 = 1,
+	FPM_POOL_ID_2 = 2,
+	FPM_POOL_ID_3 = 3,
+} fpm_pool_id_e;
+
+/* FPM user group */
+typedef enum {
+	FPM_DS_UG = 0,
+	FPM_US_UG = 1,
+	FPM_WLAN_UG = 2,
+	FPM_ALL_PASS_UG = 3,	
+} fpm_ug_id_e;
+
+/* Peripheral */
+typedef enum {
+	QM_PERIPH_ID_ETH0 = 0,
+	QM_PERIPH_ID_ETH1 = 1,
+	QM_PERIPH_ID_ETH2 = 2,
+	QM_PERIPH_ID_ETH3 = 3,
+	QM_PERIPH_ID_GPON = 4,
+	QM_PERIPH_ID_EPON = 5,
+
+	QM_PERIPH_ID__NUM_OF = 6
+} qm_periph_id_e;
+
+typedef enum ddr_byte_res_e {
+	RES_1B = 0,
+	RES_2B
+} ddr_byte_res_e;
+
+typedef enum natc_tbl_id_e {
+	NATC_TBL0_ID = 0,
+	NATC_TBL1_ID,
+	NATC_TBL2_ID,
+	NATC_TBL3_ID,
+	NATC_TBL4_ID,
+	NATC_TBL5_ID,
+	NATC_TBL6_ID,
+	NATC_TBL7_ID,
+	NATC_TBL_ID_LAST = NATC_TBL7_ID,
+} natc_tbl_id_e;
+
+typedef enum natc_eng_id_e {
+	NATC_ENG0_ID = 0,
+	NATC_ENG1_ID,
+	NATC_ENG2_ID,
+	NATC_ENG3_ID,
+	NATC_ENG_ID_LAST = NATC_ENG3_ID,
+} natc_eng_id_e;
+
+typedef enum ubus_mstr_id_e {
+	UBUS_MSTR0_ID = 0,
+	UBUS_MSTR1_ID,
+	UBUS_MSTR_ID_LAST = UBUS_MSTR1_ID,
+} ubus_mstr_id_e;
+
+typedef enum xlif_channel_id_e {
+	CHANNEL0_ID = 0,
+	CHANNEL1_ID,
+	CHANNEL2_ID,
+	CHANNEL3_ID,
+	CHANNEL4_ID,
+	CHANNEL5_ID,
+	CHANNEL6_ID,
+	CHANNEL7_ID,
+	CHANNEL_ID_LAST = CHANNEL7_ID,
+} xlif_channel_id_e;
+
+#define BB_ID_CPU0 (BB_ID_LAST + 1)
+#define BB_ID_CPU1 (BB_ID_LAST + 2)
+#define BB_ID_CPU2 (BB_ID_LAST + 3)
+
+/* HASH key masks */
+/* IPTV */
+#define HASH_TABLE_IPTV_KEY_MASK_LO 0xFFFFFFFF /* 32bit key */
+/* Only 12 bits of internal context are used */
+#define HASH_TABLE_IPTV_KEY_MASK_HI 0x0000FFFF
+
+/* ARL */
+#define HASH_TABLE_ARL_KEY_MASK_LO 0xFFFFFFFF /* 60bit key */
+#define HASH_TABLE_ARL_KEY_MASK_HI 0xFFFFFFF
+
+/* Bridge and VLAN */
+#define HASH_TABLE_BRIDGE_AND_VLAN_LKP_MASK_LO 0x000FFFFF /* 20bit key */
+#define HASH_TABLE_BRIDGE_AND_VLAN_LKP_MASK_HI 0x0
+
+#endif /* RDP_COMMON_H_INCLUDED */
+
diff --git a/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring.c b/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring.c
new file mode 100644
index 0000000000..751c08eb6c
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring.c
@@ -0,0 +1,198 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+   
+ */
+
+/* This file contains the implementation of the Runner CPU ring interface */
+
+#include "rdp_cpu_ring.h"
+#include "rdd_cpu_rx.h"
+#include "rdp_cpu_ring_inline.h"
+#include "rdp_mm.h"
+#include "bdmf_system.h"
+
+/* reason statistics for US/DS */
+int stats_reason[2][rdpa_cpu_reason__num_of] = {};
+EXPORT_SYMBOL(stats_reason);
+
+#define RW_INDEX_SIZE (sizeof(uint16_t))
+
+#ifndef CONFIG_BCMBCA_XRDP_GPL
+#include "rdd_ag_cpu_rx.h"
+#include "rdp_drv_sbpm.h"
+#else
+#include "rdpa_gpl_sbpm.h"
+#endif
+
+static int GetPdFromRamFifo(uint32_t *word0, uint32_t *word1, uint32_t *word2,
+			    uint32_t *word3)
+{
+	static int idx = 0;
+#if defined(CONFIG_BCM63146)
+	static int prev_idx = 0;
+	volatile uint32_t *desc_addr = (uint32_t *)RDD_SRAM_PD_FIFO_PTR(0);
+	volatile uint32_t *prev_desc_addr = (uint32_t *)RDD_SRAM_PD_FIFO_PTR(0);
+	RDD_CPU_RX_LAST_READ_INDEX_DTS *last_read_idx_ptr = RDD_CPU_RX_LAST_READ_INDEX_PTR(0);
+	CPU_RX_DESCRIPTOR prev_rx_desc;
+
+	desc_addr += idx;
+	*word2 = swap4bytes(*(desc_addr + 2));
+	*word3 = swap4bytes(*(desc_addr + 3));
+	*word1 = swap4bytes(*(desc_addr + 1));
+	*word0 = swap4bytes(*(desc_addr));
+
+	if ((*word2 == 0) || (*word1 == 0))
+		return BDMF_ERR_NO_MORE;
+
+	/* need to invalidate cache for the previous buffer, or else
+	 * HW cache eviction might corrupt the next RX packet that uses
+	 * the same buffer */
+	if (likely(prev_idx != idx)) {
+		prev_desc_addr += prev_idx;
+		prev_rx_desc.word0 = swap4bytes(*(prev_desc_addr));
+		prev_rx_desc.word1 = swap4bytes(*(prev_desc_addr + 1));
+		INV_RANGE(prev_rx_desc.word0, prev_rx_desc.fpm.packet_length);
+	}
+	prev_idx = idx;
+
+	MWRITE_16(last_read_idx_ptr, ((uintptr_t)desc_addr & 0xffff));
+	idx = (idx + 4) % (RDD_SRAM_PD_FIFO_SIZE * 4);
+#else
+	static int total_rx_packets = 0;
+
+	INV_RANGE((uintptr_t)RDD_SRAM_PD_FIFO_ADDRESS_ARR[0] , (64 * 16));
+
+	GROUP_MREAD_32(RDD_SRAM_PD_FIFO_ADDRESS_ARR, (idx + 0)*sizeof(uint32_t),
+			(*word0));
+	GROUP_MREAD_32(RDD_SRAM_PD_FIFO_ADDRESS_ARR, (idx + 1)*sizeof(uint32_t),
+			(*word1));
+	GROUP_MREAD_32(RDD_SRAM_PD_FIFO_ADDRESS_ARR, (idx + 2)*sizeof(uint32_t),
+			(*word2));
+	GROUP_MREAD_32(RDD_SRAM_PD_FIFO_ADDRESS_ARR, (idx + 3)*sizeof(uint32_t),
+			(*word3));
+
+	if (*word1 == 0)
+		return BDMF_ERR_NO_MORE;
+
+	total_rx_packets++;
+	GROUP_MWRITE_32(RDD_SRAM_PD_FIFO_ADDRESS_ARR,
+			(idx + 3)*sizeof(uint32_t), 0);
+	GROUP_MWRITE_32(RDD_SRAM_PD_FIFO_ADDRESS_ARR,
+			(idx + 2)*sizeof(uint32_t), 0);
+	/* for 63146, we need first 2 PDs to free buffer back */
+	GROUP_MWRITE_32(RDD_SRAM_PD_FIFO_ADDRESS_ARR,
+			(idx + 1)*sizeof(uint32_t), 0);
+	GROUP_MWRITE_32(RDD_SRAM_PD_FIFO_ADDRESS_ARR,
+			(idx + 0)*sizeof(uint32_t), 0);
+
+	idx = (idx + 4) % (64 * 4);
+#endif
+	return 0;
+}
+
+static inline int ReadPacketFromFpmFwDirect(CPU_RX_PARAMS *rx_params)
+{
+	CPU_RX_DESCRIPTOR rx_desc;
+	int ret;
+#if !defined(CONFIG_BCM63146)
+	uint32_t bn0;
+#endif
+
+#ifdef CONFIG_BCM_CACHE_COHERENCY
+	/* Before accessing the descriptors must do barrier */
+	dma_rmb();
+#endif
+
+	ret = GetPdFromRamFifo(&rx_desc.word0, &rx_desc.word1, &rx_desc.word2,
+			       &rx_desc.word3);
+	if (ret == BDMF_ERR_NO_MORE)
+		return BDMF_ERR_NO_MORE;
+
+	rx_params->packet_size = rx_desc.fpm.packet_length;
+
+#if defined(CONFIG_BCM63146)
+	rx_params->data_ptr = (uint8_t *)((uintptr_t)rx_desc.word0);
+#else
+	bn0 = rx_desc.sbpm.bn0;
+
+	ret = drv_sbpm_copy_list(bn0, &rx_params->data_ptr[0]);
+	if (ret != 0) {
+		printf("copy sbpm failed\n");
+		return BDMF_ERR_NO_MORE;
+	}
+	ret = drv_sbpm_free_list(bn0);
+	if (ret != 0) {
+		printf("free sbpm failed\n");
+		return BDMF_ERR_NO_MORE;
+	}
+#endif
+
+	/* The place of data_ofset is the same in all structures in this union
+	 * we could use any.*/
+	rx_params->data_offset = rx_desc.wan.data_offset;
+	rx_params->src_bridge_port = rx_desc.wan.source_port;
+
+	if (rx_desc.cpu_vport.vport >= RDD_CPU_VPORT_FIRST &&
+	    rx_desc.cpu_vport.vport <= RDD_CPU_VPORT_LAST)
+		rx_params->dst_ssid = rx_desc.cpu_vport.ssid;
+	else if (!rx_desc.wan.is_src_lan)
+		rx_params->flow_id = rx_desc.wan.wan_flow_id;
+	rx_params->reason = (rdpa_cpu_reason)rx_desc.wan.reason;
+#ifdef CONFIG_CPU_REDIRECT_MODE_SUPPORT
+	if (rx_params->reason == rdpa_cpu_rx_reason_cpu_redirect) {
+		rx_params->cpu_redirect_egress_queue = rx_desc.cpu_redirect.egress_queue;
+		rx_params->cpu_redirect_wan_flow = rx_desc.cpu_redirect.wan_flow;
+	}
+#endif
+	rx_params->is_ucast = rx_desc.is_ucast;
+	rx_params->is_exception = rx_desc.is_exception;
+	rx_params->is_rx_offload = rx_desc.is_rx_offload;
+	rx_params->mcast_tx_prio = rx_desc.mcast_tx_prio;
+
+	if (rx_desc.wl_nic.is_chain) {
+		/* Re-construct metadata to comply rdd_fc_context_t for wl_nic. */
+		uint16_t metadata_1 = rx_desc.wl_nic.iq_prio << 8 | rx_desc.wl_nic.chain_id;
+		uint8_t metadata_0 = (1 << 3) | rx_desc.wl_nic.tx_prio;
+
+		rx_params->wl_metadata = metadata_0 << 10 | metadata_1;
+	} else
+		rx_params->wl_metadata = rx_desc.wl_metadata;
+
+	return 0;
+}
+
+/* this API copies the next available packet from ring to given pointer */
+int rdp_cpu_ring_read_packet_copy(uint32_t ring_id, CPU_RX_PARAMS *rxParams)
+{
+#if !defined(CONFIG_BCM63146)
+	void *client_pdata;
+#endif
+	uint32_t ret = 0;
+
+	/* Data offset field is field ONLY in CFE driver on BCM6858
+	 * To ensure correct work of another platforms the data offset field
+	 * should be zeroed */
+	rxParams->data_offset = 0;
+
+#if !defined(CONFIG_BCM63146)
+	client_pdata = (void*)rxParams->data_ptr;
+#endif
+
+	ret = ReadPacketFromFpmFwDirect(rxParams);
+	if (ret)
+		goto exit;
+
+	/* Assign the data buffer back to ring */
+	INV_RANGE((rxParams->data_ptr + rxParams->data_offset), rxParams->packet_size);
+
+exit:
+
+#if !defined(CONFIG_BCM63146)
+	rxParams->data_ptr = client_pdata;
+#endif
+	return ret;
+}
+
diff --git a/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring.h b/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring.h
new file mode 100644
index 0000000000..e6e94e40df
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring.h
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+    
+*/
+
+/**************************************************************************/
+/*									  */
+/* File Description:							  */
+/*									  */
+/* This file contains the implementation of the Runner CPU ring interface */
+/*									  */
+/******************************************************************************/
+
+#ifndef _RDP_CPU_RING_H_
+#define _RDP_CPU_RING_H_
+
+#include "rdp_subsystem_common.h"
+
+#include "rdpa_types.h"
+#include "rdd.h"
+#include "rdp_cpu_ring_defs.h"
+
+
+typedef struct {
+	uint8_t *data_ptr;
+	uint8_t data_offset;
+	uint16_t packet_size;
+	uint16_t flow_id;
+	uint16_t reason;
+	uint16_t src_bridge_port;
+	uint16_t dst_ssid;
+	uint32_t wl_metadata;
+	uint16_t ptp_index;
+	uint16_t free_index;
+	uint8_t is_rx_offload;
+	uint8_t is_ipsec_upstream;
+	uint8_t is_ucast;
+	uint8_t is_exception;
+	uint8_t is_csum_verified;
+	uint8_t mcast_tx_prio;
+} CPU_RX_PARAMS;
+
+int rdp_cpu_ring_read_packet_copy(uint32_t ringId, CPU_RX_PARAMS *rxParams);
+
+#endif /* _RDP_CPU_RING_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring_defs.h b/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring_defs.h
new file mode 100644
index 0000000000..e7493b6a1f
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring_defs.h
@@ -0,0 +1,301 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ *  
+ */
+
+
+#ifndef _RDP_CPU_RING_DEFS_H
+#define _RDP_CPU_RING_DEFS_H
+
+#include "access_macros.h"
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+    union {
+        struct {
+            uint32_t word0;
+            uint32_t word1;
+        };
+        struct {
+            uint32_t host_buffer_data_ptr_low; /* total 40 bits for address */
+            uint32_t host_buffer_data_ptr_hi:8;
+            uint32_t reserved0:7;
+            uint32_t abs:1;
+            uint32_t packet_length:14;
+            uint32_t is_chksum_verified:1;
+            uint32_t reserved2:1;
+        } abs;
+        struct {
+            uint32_t fpm_idx:18;
+            uint32_t reserved0:14;
+            uint32_t reserved1:15;
+            uint32_t abs:1;
+            uint32_t packet_length:14;
+            uint32_t is_chksum_verified:1;
+            uint32_t reserved2:1;
+        } fpm;
+        struct {
+            uint32_t bn0:18;
+            uint32_t reserved0:14;
+            uint32_t reserved1:15;
+            uint32_t abs:1;
+            uint32_t packet_length:14;
+            uint32_t is_chksum_verified:1;
+            uint32_t reserved2:1;
+        } sbpm;
+    };
+
+    union {
+        uint32_t word2;
+        struct {
+            uint32_t is_src_lan:1;
+            uint32_t reserved7:1;
+            uint32_t source_port:5;
+            uint32_t wan_flow_id:12; /* WAN Flow / DSL flags */
+            uint32_t data_offset:7;
+            uint32_t reason:6;
+        } wan;
+        struct {
+            uint32_t is_src_lan:1;
+            uint32_t reserved7:1;
+            uint32_t source_port:5; /* LAN */
+            uint32_t reserved3:12;
+            uint32_t data_offset:7;
+            uint32_t reason:6;
+        } lan;
+        struct {
+            uint32_t is_src_lan:1;
+            uint32_t reserved7:1;
+            uint32_t vport:5;
+            uint32_t ssid:4;
+            uint32_t reserved4:8;
+            uint32_t data_offset:7;
+            uint32_t reason:6;
+        } cpu_vport; /* (e.g. WLAN) */
+    };
+
+    union {
+        uint32_t word3;
+        struct {
+            uint16_t    is_exception:1;
+            uint16_t    is_rx_offload:1;
+            uint16_t    is_ucast:1;
+            uint16_t    mcast_tx_prio:3;
+            uint16_t    reserved5:10;
+            union {
+                uint16_t dst_ssid_vector; /* For WLAN multicast */
+                uint16_t wl_metadata; /* For WLAN multicast */
+                struct {
+                    uint16_t reserved8:2;
+                    uint16_t is_chain:1;
+                    uint16_t tx_prio:3;
+                    uint16_t reserved9:1;
+                    uint16_t iq_prio:1;
+                    uint16_t chain_id:8;
+                } wl_nic;
+                struct {
+                    uint16_t reserved10:2;
+                    uint16_t is_chain:1;
+                    uint16_t tx_prio:3;
+                    uint16_t flow_ring_idx:10;
+                } wl_dongle;
+                struct {
+                    uint16_t reserved11:2;
+                    uint16_t metadata_0:4; /* For WLAN: is_chain:1, tx_prio:3 */
+                    uint16_t metadata_1:10; /* For WLAN NIC: rsv:1, iq_prio:1, chain_id:1; Dongle: flow_ring_idx:10 */
+                } metadata;
+#ifdef CONFIG_CPU_REDIRECT_MODE_SUPPORT
+                struct {
+                    uint16_t egress_queue:8;
+                    uint16_t wan_flow:8;
+                } cpu_redirect;
+#endif
+            };
+        };
+    };
+}
+CPU_RX_DESCRIPTOR;
+
+typedef struct
+{
+    union {
+        struct {
+            uint32_t word0;
+            uint32_t word1;
+        };
+        struct {
+            uint32_t host_buffer_data_ptr_low; /* total 40 bits for address */
+            uint32_t reserved:23;
+            uint32_t abs:1;
+            uint32_t host_buffer_data_ptr_hi:8;
+        } abs;
+    };
+}
+CPU_FEED_DESCRIPTOR;
+
+typedef struct
+{
+    union {
+        struct {
+            uint32_t word0;
+            uint32_t word1;
+        };
+        struct {
+            uint32_t host_buffer_data_ptr_low; /* total 40 bits for address */
+            uint32_t reserved:22;
+            uint32_t from_feed_ring:1;
+            uint32_t abs:1;
+            uint32_t host_buffer_data_ptr_hi:8;
+        } abs;
+    };
+}
+CPU_RECYCLE_DESCRIPTOR;
+#else
+typedef struct
+{
+    union {
+        struct {
+            uint32_t word0;
+            uint32_t word1;
+        };
+        struct {
+            uint32_t host_buffer_data_ptr_low; /* total 40 bits for address */
+            uint32_t reserved2:1;
+            uint32_t is_chksum_verified:1;
+            uint32_t packet_length:14;
+            uint32_t abs:1;
+            uint32_t reserved0:7;
+            uint32_t host_buffer_data_ptr_hi:8;
+        } abs;
+        struct {
+            uint32_t reserved0:14;
+            uint32_t fpm_idx:18;
+            uint32_t reserved2:1;
+            uint32_t is_chksum_verified:1;
+            uint32_t packet_length:14;
+            uint32_t abs:1;
+            uint32_t reserved1:15;
+        } fpm;
+        struct {
+            uint32_t reserved0:14;
+            uint32_t bn0:18;
+            uint32_t reserved2:1;
+            uint32_t is_chksum_verified:1;
+            uint32_t packet_length:14;
+            uint32_t abs:1;
+            uint32_t reserved1:15;
+        } sbpm;
+    };
+    union {
+        uint32_t word2;
+        struct {
+            uint32_t reason:6;
+            uint32_t data_offset:7;
+            uint32_t wan_flow_id:12; /* WAN Flow / DSL flags */
+            uint32_t source_port:5;
+            uint32_t reserved7:1;
+            uint32_t is_src_lan:1;
+        } wan;
+        struct {
+            uint32_t reason:6;
+            uint32_t data_offset:7;
+            uint32_t reserved3:12;
+            uint32_t source_port:5; /* LAN */
+            uint32_t reserved7:1;
+            uint32_t is_src_lan:1;
+        } lan;
+        struct {
+            uint32_t reason:6;
+            uint32_t data_offset:7;
+            uint32_t reserved4:8;
+            uint32_t ssid:4;
+            uint32_t vport:5;
+            uint32_t reserved7:1;
+            uint32_t is_src_lan:1;
+        } cpu_vport;
+    };
+
+    union {
+        uint32_t word3;
+        struct {
+            union {
+                uint16_t dst_ssid_vector; /* For WLAN multicast */
+                uint16_t wl_metadata; /* For WLAN multicast */
+                struct {
+                    uint16_t metadata_1:10; /* For WLAN NIC: rsv:1, iq_prio:1, chain_id:1; Dongle: flow_ring_idx:10 */
+                    uint16_t metadata_0:4; /* For WLAN: is_chain:1, tx_prio:3 */
+                    uint16_t reserved11:2;
+                } metadata;
+                struct {
+                    uint16_t flow_ring_idx:10;
+                    uint16_t tx_prio:3;
+                    uint16_t is_chain:1;
+                    uint16_t reserved10:2;
+                } wl_dongle;
+                struct {
+                    uint16_t chain_id:8;
+                    uint16_t iq_prio:1;
+                    uint16_t reserved9:1;
+                    uint16_t tx_prio:3;
+                    uint16_t is_chain:1;
+                    uint16_t reserved8:2;
+                } wl_nic;
+#ifdef CONFIG_CPU_REDIRECT_MODE_SUPPORT
+                struct {
+                    uint16_t wan_flow:8;
+                    uint16_t egress_queue:8;
+                } cpu_redirect;
+#endif
+            };
+            uint16_t    reserved5:10;
+            uint16_t    mcast_tx_prio:3;
+            uint16_t    is_ucast:1;
+            uint16_t    is_rx_offload:1;
+            uint16_t    is_exception:1;
+        };
+    };
+}
+CPU_RX_DESCRIPTOR;
+
+typedef struct
+{
+    union {
+        struct {
+            uint32_t word0;
+            uint32_t word1;
+        };
+        struct {
+            uint32_t host_buffer_data_ptr_low; /* total 40 bits for address */
+            uint32_t host_buffer_data_ptr_hi:8;
+            uint32_t abs:1;
+            uint32_t reserved:23;
+        } abs;
+    };
+}
+CPU_FEED_DESCRIPTOR;
+
+typedef struct
+{
+    union {
+        struct {
+            uint32_t word0;
+            uint32_t word1;
+        };
+        struct {
+            uint32_t host_buffer_data_ptr_low; /* total 40 bits for address */
+            uint32_t host_buffer_data_ptr_hi:8;
+            uint32_t abs:1;
+            uint32_t from_feed_ring:1;
+            uint32_t reserved:22;
+        } abs;
+    };
+}
+CPU_RECYCLE_DESCRIPTOR;
+
+#endif
+
+#endif /*_RDP_CPU_RING_DEFS_H */
diff --git a/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring_inline.h b/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring_inline.h
new file mode 100644
index 0000000000..08495b10ff
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdp_cpu_ring_inline.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+   
+ */
+
+#ifndef _RDP_CPU_RING_INLINE_H_
+#define _RDP_CPU_RING_INLINE_H_
+
+
+
+#endif /* _RDP_CPU_RING_INLINE_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/rdp_mm.h b/arch/arm/mach-bcmbca/xrdp/rdp_mm.h
new file mode 100644
index 0000000000..ec188ebdea
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdp_mm.h
@@ -0,0 +1,142 @@
+/*
+    <:copyright-BRCM:2014-2016:DUAL/GPL:standard
+    
+       Copyright (c) 2014-2016 Broadcom 
+       All Rights Reserved
+    
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License, version 2, as published by
+    the Free Software Foundation (the "GPL").
+    
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+    
+    
+    A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
+    writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+    Boston, MA 02111-1307, USA.
+    
+    :>
+*/
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains inline functions for runner host memory management      */
+/*                                                                            */
+/******************************************************************************/
+#ifndef _RDP_MM_H_
+#define _RDP_MM_H_
+#include <common.h>
+#include "bdmf_data_types.h"
+
+#define VIRT_TO_PHYS(_addr)		((uintptr_t)_addr)
+#define PHYS_TO_CACHED(_addr)		((void *)((uintptr_t)_addr))
+#define PHYS_TO_UNCACHED(_addr)		((void *)((uintptr_t)_addr))
+
+#define CACHED_FREE(_ptr)		free(_ptr)
+
+#define KMALLOC(_size, _align)		memalign(_align, _size)
+#define KFREE(_ptr)			free(_ptr)
+
+#if defined(CONFIG_BCM6858) || defined(CONFIG_BCM63146) || \
+    defined(CONFIG_BCM6846) || defined(CONFIG_BCM6856) || \
+    defined(CONFIG_BCM6878)
+#define DMA_CACHE_LINE 64
+#else
+#define DMA_CACHE_LINE 32
+#endif
+
+#define FLUSH_RANGE(s,l) ({ \
+	unsigned long start, end;	\
+	start = ((unsigned long)(s))&~(DMA_CACHE_LINE-1); \
+	end = (((unsigned long)(s)+(l)) + \
+		DMA_CACHE_LINE - 1)&~(DMA_CACHE_LINE-1); \
+	flush_dcache_range(start, end);	})
+
+#define INV_RANGE(s,l) ({ \
+	unsigned long start, end;	\
+	start = ((unsigned long)(s))&~(DMA_CACHE_LINE-1); \
+	end = (((unsigned long)(s)+(l)) + \
+		DMA_CACHE_LINE - 1)&~(DMA_CACHE_LINE-1); \
+	invalidate_dcache_range(start, end);	})
+
+#define BCM_PKTBUF_SIZE 2048
+
+#define rdp_mm_aligned_alloc(_size, _phy_addr_p) \
+	__rdp_mm_aligned_alloc((_size), (_phy_addr_p), GFP_DMA)
+#define rdp_mm_aligned_alloc_atomic(_size, _phy_addr_p) \
+	__rdp_mm_aligned_alloc((_size), (_phy_addr_p), GFP_ATOMIC)
+
+static inline void *__rdp_mm_aligned_alloc(uint32_t size,
+					   bdmf_phys_addr_t *phy_addr_p,
+					   gfp_t gfp)
+{
+	dma_addr_t phy_addr;
+	uint32_t size_padded_aligned;
+	dma_addr_t *mem;
+
+	/* must be multiple of pointer size */
+	size_padded_aligned = (size + (sizeof(dma_addr_t) << 1) - 1) &
+			~(sizeof(dma_addr_t) - 1);
+	mem = (dma_addr_t *)consistent_alloc(gfp, size_padded_aligned, &phy_addr);
+	if (unlikely(mem == NULL))
+		return NULL;
+
+	mem[(size_padded_aligned / sizeof(dma_addr_t)) - 1] = phy_addr;
+	*phy_addr_p = (bdmf_phys_addr_t)phy_addr;
+	return (void *)mem;
+}
+
+static inline void rdp_mm_aligned_free(void *ptr, uint32_t size)
+{
+	uint32_t size_padded_aligned;
+	dma_addr_t *mem = ptr, phy_addr;
+
+	size_padded_aligned = (size + (sizeof(dma_addr_t) << 1) - 1) &
+			~(sizeof(dma_addr_t) - 1);
+	phy_addr = mem[(size_padded_aligned / sizeof(dma_addr_t)) - 1];
+	consistent_free(ptr, size_padded_aligned, phy_addr);
+}
+
+static inline void rdp_mm_setl_context(void *__to, unsigned int __val,
+				       unsigned int __n)
+{
+	volatile unsigned int *dst = (volatile unsigned int *)__to;
+	int i;
+
+	for (i = 0; i < (__n / 4); i++, dst++) {
+		if ((i & 0x3) == 3)
+			continue;
+		*dst = __val; /* DSL */
+	}
+}
+
+static inline void rdp_mm_setl(void *__to, unsigned int __val, unsigned int __n)
+{
+	volatile unsigned int *dst = (volatile unsigned int *)__to;
+	int i;
+
+	for (i = 0; i < (__n / 4); i++, dst++)
+		*dst = __val; /* DSL */
+}
+
+static inline void rdp_mm_cpyl_context(void *__to, void *__from,
+				       unsigned int __n)
+{
+	volatile unsigned int * src = (unsigned int *)__from;
+	volatile unsigned int * dst = (unsigned int *)__to;
+	int i, n = __n / 4;
+
+	for (i = 0; i < n; i++, src++, dst++) {
+		if ((i & 0x3) == 3)
+			continue;
+
+		*dst = swap4bytes(*src);
+	}
+}
+
+#endif
diff --git a/arch/arm/mach-bcmbca/xrdp/rdp_platform.c b/arch/arm/mach-bcmbca/xrdp/rdp_platform.c
new file mode 100644
index 0000000000..f3ed4497b8
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdp_platform.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+    
+*/
+
+#include "rdp_common.h"
+#ifndef __PACKING_ATTRIBUTE_STRUCT_END__
+#include "packing.h"
+#endif
+#include "rdd_data_structures_auto.h"
+
+#ifdef CONFIG_BCM6858
+
+int reg_id[32] = {[8] = 0, [9] = 1, [10] = 2, [11] = 4, [12] = 5, [13] = 6, [14] = 8, [15] = 9, [16] = 10, [17] = 12, [18] = 13, [19] = 14, [20] = 16, [21] = 17, [22] = 18,
+    [23] = 20, [24] = 21, [25] = 22, [26] = 24, [27] = 25, [28] = 26, [29] = 28, [30] = 29, [31] = 30};
+#else
+#if !defined(CONFIG_BCM63146) && !defined(CONFIG_BCM6878)
+int reg_id[32]={[8]=0, [9]=1, [10]=2, [11]=3, [12]=4, [13]=5, [14]=6, [15]=7, [16]=8, [17]=9, [18]=10, [19]=11, [20]=12, [21]=13, [22]=14,
+    [23]=15, [24]=16, [25]=17, [26]=18, [27]=19, [28]=20, [29]=21, [30]=22, [31]=23};
+#else
+int reg_id[32]={0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};
+#endif //DUAL_ISSUE
+#endif
+
diff --git a/arch/arm/mach-bcmbca/xrdp/rdp_platform.h b/arch/arm/mach-bcmbca/xrdp/rdp_platform.h
new file mode 100644
index 0000000000..6686d3a964
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdp_platform.h
@@ -0,0 +1,502 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+    
+*/
+
+#ifndef RDP_PLATFORM_H_INCLUDED
+#define RDP_PLATFORM_H_INCLUDED
+
+
+#define MAX_NUM_OF_QUEUES_IN_SCHED 32
+
+/* SBPM */
+#define SBPM_BASE_ADDRESS	0
+#define SBPM_INIT_OFFSET	(SBPM_MAX_BUFFER_NUMBER)
+#define SBPM_MAX_NUM_OF_BNS	(SBPM_MAX_BUFFER_NUMBER + 1)
+
+
+typedef enum rnr_quad_id_e {
+	RNR_QUAD0_ID = 0,
+	RNR_QUAD_ID_LAST = RNR_QUAD0_ID,
+	NUM_OF_RNR_QUADS = RNR_QUAD_ID_LAST + 1,
+} rnr_quad_id_e;
+
+#if defined(CONFIG_BCM6858)
+
+#define RNR_FREQ_IN_MHZ 1000
+#define UBUS_SLV_FREQ_IN_MHZ 500
+#define NUM_OF_CORES_IN_QUAD 4
+#define DRV_PARSER_MASKED_DA_FILTER_NUM 2
+#define DRV_PARSER_DA_FILTER_NUM 9
+#define NUM_OF_RNR_WITH_PROFILING 16
+
+/* DISP CONGESTION */
+#define DIS_REOR_CONGESTION_THRESHOLD	450
+#define DIS_REOR_LINKED_LIST_BUFFER_NUM  1024
+#define NUM_OF_PROCESSING_TASKS		  96
+
+/* BBH_RX */
+#define DRV_BBH_RX_MAXIMAL_PACKET_HEADER_OFFSET 127
+
+/* BBH_TX */
+#define BBH_TX_DS_PD_FIFO_SIZE_0 8
+#define BBH_TX_DS_PD_FIFO_SIZE_1 8
+
+/* HASH */
+#define HASH_NUM_OF_ENGINES		   2
+#define HASH_NUM_OF_ENGINES_LOG2	  1
+#define HASH_NUM_OF_EFFECTIVE_ENGINES 2
+#define HASH_NUM_OF_ENTRIES_IN_RAM	2048
+
+#define IS_WAN_TX_PORT(bbh_id) (bbh_id == BBH_ID_PON)
+#define IS_SDMA(dma_id) (dma_id > DMA1_ID)
+#define IS_DMA(dma_id) (dma_id <= DMA1_ID)
+#define IS_PROCESSING_RUNNER_IMAGE(i)  (rdp_core_to_image_map[i] == processing_runner_image)
+#define IS_DS_TM_RUNNER_IMAGE(i)  (rdp_core_to_image_map[i] == ds_tm_runner_image)
+
+/* NATC */
+#define NATC_CACHE_ENTRIES_NUM   512
+
+/* TCAM table size (entries) */
+#define RDP_TCAM_TABLE_SIZE	 512
+/* Number of TCAM engines */
+#define RDP_TCAM_NUM_ENGINES	2
+
+/* Max number of queues supported by QM */
+#define QM_NUM_QUEUES		   288
+
+typedef enum dma_id_e
+{
+	DMA0_ID = 0,
+	DMA1_ID,
+	SDMA0_ID,
+	SDMA1_ID,
+	DMA_NUM,
+	DMA_ID_FIRST = DMA0_ID,
+} dma_id_e;
+
+typedef enum bbh_id_e
+{
+	BBH_ID_0 = 0,  /* XLMAC1_0_RGMII */
+	BBH_ID_1,	  /* XLMAC0_1_2p5G  */
+	BBH_ID_2,	  /* XLMAC0_2_1G	*/
+	BBH_ID_3,	  /* XLMAC0_3_1G	*/
+	BBH_ID_4,	  /* XLMAC0_0_10G   */
+	BBH_ID_5,	  /* XLMAC1_1_RGMII */
+	BBH_ID_6,	  /* XLMAC1_2_RGMII */
+	BBH_ID_7,	  /* XLMAC1_3_RGMII */
+	BBH_ID_PON,
+	BBH_ID_NUM,
+	BBH_ID_FIRST = BBH_ID_0,
+	BBH_ID_LAST = BBH_ID_PON,
+	BBH_ID_LAST_XLMAC = BBH_ID_7,
+	BBH_ID_NULL = BBH_ID_NUM
+} bbh_id_e;
+
+
+/* SBPM */
+
+#define SBPM_MAX_BUFFER_NUMBER			  0xFFF
+
+
+/**********************************************************************************************************/
+#elif  defined(CONFIG_BCM6846)
+
+#define RNR_FREQ_IN_MHZ 1400
+#define UBUS_SLV_FREQ_IN_MHZ 466
+#define NUM_OF_CORES_IN_QUAD 3
+#define DRV_PARSER_MASKED_DA_FILTER_NUM 2
+#define DRV_PARSER_DA_FILTER_NUM 9
+#define NUM_OF_RNR_WITH_PROFILING 3
+
+#define IS_WAN_TX_PORT(bbh_id) (bbh_id == BBH_TX_WAN_ID)
+#define IS_WAN_RX_PORT(bbh_id) (bbh_id == BBH_ID_PON)
+#define IS_SDMA(dma_id)  (dma_id > DMA0_ID)
+#define IS_DMA(dma_id)   (dma_id <= DMA0_ID)
+#define IS_PROCESSING_RUNNER_IMAGE(i)  ((rdp_core_to_image_map[i] == processing0_runner_image) || (rdp_core_to_image_map[i] == processing1_runner_image))
+#define IS_DS_TM_RUNNER_IMAGE(i)  (rdp_core_to_image_map[i] == ds_tm_runner_image)
+
+/* NATC */
+#define NATC_CACHE_ENTRIES_NUM   512
+
+/* DISP CONGESTION */
+#define DIS_REOR_CONGESTION_THRESHOLD	200
+#define DIS_REOR_LINKED_LIST_BUFFER_NUM  512
+#define NUM_OF_PROCESSING_TASKS		  12
+
+/* SBPM */
+
+#define SBPM_MAX_BUFFER_NUMBER			  0x5FF
+
+
+/* BBH_RX */
+#define DRV_BBH_RX_MAXIMAL_PACKET_HEADER_OFFSET 63
+#define BBH_FREQUENCY (466770000) /* 466.77 MHz */
+
+/* BBH_TX */
+#define BBH_TX_DS_PD_FIFO_SIZE_0 7
+#define BBH_TX_DS_PD_FIFO_SIZE_1 7
+
+/* HASH */
+#define HASH_NUM_OF_ENGINES		   2
+#define HASH_NUM_OF_ENGINES_LOG2	  1
+#define HASH_NUM_OF_EFFECTIVE_ENGINES 2
+
+/* TCAM table size (entries) */
+#define RDP_TCAM_TABLE_SIZE	 256
+/* Number of TCAM engines */
+#define RDP_TCAM_NUM_ENGINES	1
+
+/* Max number of queues supported by QM */
+#define QM_NUM_QUEUES		   96
+/* Max number of EPON queues supported by QM */
+#define QM_NUM_EPON_QUEUES	  8
+/* Max number of reported queues supported by QM */
+#define QM_NUM_REPORTED_QUEUES  32
+
+typedef enum bbh_id_e
+{
+	BBH_ID_0 = 0,
+	BBH_ID_1,
+	BBH_ID_2,
+	BBH_ID_3,
+	BBH_ID_4,
+	BBH_ID_PON,
+	BBH_ID_NUM,
+	BBH_ID_FIRST = BBH_ID_0,
+	BBH_ID_LAST = BBH_ID_PON,
+	BBH_ID_NULL = BBH_ID_NUM
+} bbh_id_e;
+
+typedef enum dma_id_e
+{
+	DMA0_ID = 0,
+	SDMA0_ID,
+	DMA_NUM,
+	DMA_ID_FIRST = DMA0_ID,
+} dma_id_e;
+
+/**********************************************************************************************************/
+
+#elif  defined(CONFIG_BCM6878)
+#define RNR_FREQ_IN_MHZ 1000
+#define UBUS_SLV_FREQ_IN_MHZ 466
+#define NUM_OF_CORES_IN_QUAD 3
+#define DRV_PARSER_MASKED_DA_FILTER_NUM 2
+#define DRV_PARSER_DA_FILTER_NUM 9
+#define NUM_OF_RNR_WITH_PROFILING 3
+
+#define IS_WAN_TX_PORT(bbh_id) (bbh_id == BBH_TX_WAN_ID)
+#define IS_WAN_RX_PORT(bbh_id) (bbh_id == BBH_ID_PON)
+#define IS_SDMA(dma_id)  (dma_id > DMA0_ID)
+#define IS_DMA(dma_id)   (dma_id <= DMA0_ID)
+#define IS_PROCESSING_RUNNER_IMAGE(i)  ((rdp_core_to_image_map[i] == processing0_runner_image) || (rdp_core_to_image_map[i] == processing1_runner_image))
+#define IS_DS_TM_RUNNER_IMAGE(i)  (rdp_core_to_image_map[i] == ds_tm_runner_image)
+
+
+/* NATC */
+#define NATC_CACHE_ENTRIES_NUM   512
+
+/* DISP CONGESTION */
+#define DIS_REOR_CONGESTION_THRESHOLD	100
+#define DIS_REOR_LINKED_LIST_BUFFER_NUM  256
+#define NUM_OF_PROCESSING_TASKS		  12
+
+/* BBH_RX */
+#define DRV_BBH_RX_MAXIMAL_PACKET_HEADER_OFFSET 63
+#define BBH_FREQUENCY (466770000) /* 466.77 MHz */
+
+/* BBH_TX */
+#define BBH_TX_DS_PD_FIFO_SIZE_0 7
+#define BBH_TX_DS_PD_FIFO_SIZE_1 7
+
+/* HASH */
+#define HASH_NUM_OF_ENGINES		   2
+#define HASH_NUM_OF_ENGINES_LOG2	  1
+#define HASH_NUM_OF_EFFECTIVE_ENGINES 2
+
+/* TCAM table size (entries) */
+#define RDP_TCAM_TABLE_SIZE	 256
+/* Number of TCAM engines */
+#define RDP_TCAM_NUM_ENGINES	1
+
+/* Max number of queues supported by QM */
+#define QM_NUM_QUEUES		   128
+/* Max number of EPON queues supported by QM */
+#define QM_NUM_EPON_QUEUES	  8
+/* Max number of reported queues supported by QM */
+#define QM_NUM_REPORTED_QUEUES  32
+
+typedef enum bbh_id_e
+{
+	BBH_ID_0 = 0,
+	BBH_ID_1,
+	BBH_ID_2,
+	BBH_ID_3,
+	BBH_ID_4,
+	BBH_ID_PON,
+	BBH_ID_NUM,
+	BBH_ID_FIRST = BBH_ID_0,
+	BBH_ID_LAST = BBH_ID_PON,
+	BBH_ID_NULL = BBH_ID_NUM
+} bbh_id_e;
+
+typedef enum dma_id_e
+{
+	DMA0_ID = 0,
+	DMA_NUM,
+	DMA_ID_FIRST = DMA0_ID,
+} dma_id_e;
+
+typedef enum bbh_tx_id_e
+{
+	BBH_TX_ID_LAN = 0,
+	BBH_TX_ID_PON,
+	BBH_TX_ID_NUM,
+	BBH_TX_ID_FIRST = BBH_TX_ID_LAN,
+	BBH_TX_ID_LAST = BBH_TX_ID_PON,
+	BBH_TX_ID_NULL = BBH_TX_ID_NUM
+} bbh_tx_id_e;
+
+/* SBPM */
+#define SBPM_MAX_BUFFER_NUMBER			  0x3FF
+
+
+
+#elif defined(CONFIG_BCM6856) 
+
+#define RNR_FREQ_IN_MHZ 1400
+#define UBUS_SLV_FREQ_IN_MHZ 500
+#define NUM_OF_CORES_IN_QUAD 4
+#define DRV_PARSER_MASKED_DA_FILTER_NUM 2
+#define DRV_PARSER_DA_FILTER_NUM 9
+#define NUM_OF_RNR_WITH_PROFILING 8
+
+#define IS_WAN_TX_PORT(bbh_id) (bbh_id == BBH_TX_WAN_ID)
+#define IS_SDMA(dma_id)  (dma_id > DMA0_ID)
+#define IS_DMA(dma_id)   (dma_id <= DMA0_ID)
+#define IS_PROCESSING_RUNNER_IMAGE(i)  ((rdp_core_to_image_map[i] == processing0_runner_image) || (rdp_core_to_image_map[i] == processing1_runner_image) || (rdp_core_to_image_map[i] == processing2_runner_image) || (rdp_core_to_image_map[i] == processing3_runner_image))
+#define IS_DS_TM_RUNNER_IMAGE(i)  (rdp_core_to_image_map[i] == ds_tm_runner_image)
+
+/* NATC */
+#define NATC_CACHE_ENTRIES_NUM   512
+
+/* DISP CONGESTION */
+#define DIS_REOR_CONGESTION_THRESHOLD	200
+#define DIS_REOR_LINKED_LIST_BUFFER_NUM  1024
+#define NUM_OF_PROCESSING_TASKS		  32
+
+/* SBPM */
+#define SBPM_UG0_BN_THRESHOLD			   0x3FF
+
+/* BBH_RX */
+#define DRV_BBH_RX_MAXIMAL_PACKET_HEADER_OFFSET 63
+#define BBH_FREQUENCY (500*1000000) /* 500 MHz */
+
+/* BBH_TX */
+#define BBH_TX_DS_PD_FIFO_SIZE_0 7
+#define BBH_TX_DS_PD_FIFO_SIZE_1 7
+
+/* HASH */
+#define HASH_NUM_OF_ENGINES		   4
+#define HASH_NUM_OF_ENGINES_LOG2	  2
+#define HASH_NUM_OF_EFFECTIVE_ENGINES 4
+#define HASH_NUM_OF_ENTRIES_IN_RAM	6144
+
+/* TCAM table size (entries) */
+#define RDP_TCAM_TABLE_SIZE	 256
+/* Number of TCAM engines */
+#define RDP_TCAM_NUM_ENGINES	2
+
+/* Max number of queues supported by QM */
+#define QM_NUM_QUEUES		   160
+/* Max number of reported queues supported by QM */
+#define QM_NUM_REPORTED_QUEUES  128
+
+typedef enum dma_id_e
+{
+	DMA0_ID = 0,
+	DMA1_ID,
+	SDMA0_ID,
+	SDMA1_ID,
+	DMA_NUM,
+	DMA_ID_FIRST = DMA0_ID,
+} dma_id_e;
+
+typedef enum bbh_id_e
+{
+	BBH_ID_0 = 0,
+	BBH_ID_1,
+	BBH_ID_2,
+	BBH_ID_3,
+	BBH_ID_4,
+	BBH_ID_5,
+	BBH_ID_PON,
+	BBH_ID_NUM,
+	BBH_ID_FIRST = BBH_ID_0,
+	BBH_ID_LAST = BBH_ID_PON,
+	BBH_ID_NULL = BBH_ID_NUM
+} bbh_id_e;
+
+typedef enum bbh_tx_id_e
+{
+	BBH_TX_ID_LAN = 0,
+	BBH_TX_ID_PON,
+	BBH_TX_ID_NUM,
+	BBH_TX_ID_FIRST = BBH_TX_ID_LAN,
+	BBH_TX_ID_LAST = BBH_TX_ID_PON,
+	BBH_TX_ID_NULL = BBH_TX_ID_NUM
+} bbh_tx_id_e;
+
+#elif  defined(CONFIG_BCM63146)
+
+#define RNR_FREQ_IN_MHZ 1250
+/* TBD63146. Need for CONFIG_BCM63146 */
+#define UBUS_SLV_FREQ_IN_MHZ 560
+/* TBD below */
+#define NUM_OF_CORES_IN_QUAD 3
+#define DRV_PARSER_MASKED_DA_FILTER_NUM 2
+#define DRV_PARSER_DA_FILTER_NUM 9
+#define NUM_OF_RNR_WITH_PROFILING 3
+
+/* IS_WAN_TX_PORT and IS_WAN_RX_PORT identify TX WAN ports for DSL only (NOT Ethernet) */
+#define IS_WAN_TX_PORT(bbh_id) (bbh_id == BBH_TX_ID_DSL)
+#define IS_WAN_RX_PORT(bbh_id) (bbh_id == BBH_ID_DSL)
+/* IS_DS_WAN_PORT and IS_US_WAN_PORT identify ALL (DS/US respectively) WAN ports */
+/* TBD63146. Identify Ethernet WAN */
+#define IS_DS_WAN_PORT(bbh_id)  (bbh_id == BBH_ID_DSL)
+#define IS_US_WAN_PORT(bbh_id) (bbh_id == BBH_TX_ID_DSL)
+#define IS_PROCESSING_RUNNER_IMAGE(i) \
+	((rdp_core_to_image_map[i] == processing0_runner_image) || \
+	(rdp_core_to_image_map[i] == processing1_runner_image) || \
+	(rdp_core_to_image_map[i] == processing2_runner_image))
+#define IS_DS_TM_RUNNER_IMAGE(i) (rdp_core_to_image_map[i] == ds_tm_runner_image)
+#define IS_US_TM_RUNNER_IMAGE(i) (rdp_core_to_image_map[i] == us_tm_runner_image)
+
+/* NATC */
+#define NATC_CACHE_ENTRIES_NUM 1024
+
+/* DISP CONGESTION */
+#define DIS_REOR_CONGESTION_THRESHOLD	200
+#define DIS_REOR_LINKED_LIST_BUFFER_NUM	512
+#define NUM_OF_PROCESSING_TASKS	 	32
+
+/* SBPM */
+/* the real physical limit is 0x5FF */
+#define SBPM_MAX_BUFFER_NUMBER	0x17F
+#define SBPM_UG0_BN_THRESHOLD	0x15F
+#define SBPM_UG1_BN_THRESHOLD	0x23
+
+/* BBH_RX */
+#define DRV_BBH_RX_MAXIMAL_PACKET_HEADER_OFFSET 127
+/* TBD63146. Need for BCM63146 */
+#define BBH_FREQUENCY (560*1000000) /* 560 MHz */
+
+/* BBH_TX */
+#define BBH_TX_DS_PD_FIFO_SIZE_0 7
+#define BBH_TX_DS_PD_FIFO_SIZE_1 7
+
+/* HASH */
+#define HASH_NUM_OF_ENGINES		2
+#define HASH_NUM_OF_ENGINES_LOG2	1
+#define HASH_NUM_OF_EFFECTIVE_ENGINES	2
+
+/* TCAM table size (entries) */
+#define RDP_TCAM_TABLE_SIZE	256
+/* Number of TCAM engines */
+#define RDP_TCAM_NUM_ENGINES	2
+
+/* Max number of queues supported by QM */
+#define QM_NUM_QUEUES		128
+
+typedef enum dma_id_e {
+	DMA0_ID = 0,
+	DMA1_ID,
+	DMA_NUM,
+	DMA_ID_FIRST = DMA0_ID,
+} dma_id_e;
+
+typedef enum bbh_id_e {
+	/* RX */
+	/* RX BBH_ID needs to be the same as DISP_REOR_VIQ defined in
+	 * project_data_structures.xml or else bbh_rx configuration will break */
+	BBH_ID_0 = 0,
+	BBH_ID_1,
+	BBH_ID_2,
+	BBH_ID_3,
+	BBH_ID_4,
+	BBH_ID_5,
+	BBH_ID_6_2P5G,
+	BBH_ID_7_5G,
+	BBH_ID_DSL,
+	BBH_ID_NUM,
+	BBH_ID_FIRST = BBH_ID_0,
+	BBH_ID_NUM_LAN = BBH_ID_7_5G,
+	BBH_ID_LAST = BBH_ID_DSL,
+	BBH_ID_NULL = BBH_ID_NUM,
+} bbh_id_e;
+
+typedef enum bbh_tx_id_e {
+	BBH_TX_ID_LAN = 0,
+	BBH_ID_QM_COPY,
+	BBH_TX_ID_DSL,
+	BBH_TX_ID_NUM,
+	BBH_TX_ID_FIRST = BBH_TX_ID_LAN,
+	BBH_TX_ID_LAST = BBH_TX_ID_DSL,
+	BBH_TX_ID_NULL = BBH_ID_NULL,
+} bbh_tx_id_e;
+
+typedef enum dma_target_e {
+	DMA_TARGET_DMA = 0,
+	DMA_TARGET_SDMA,
+	DMA_TARGET_NUM,
+	DMA_TARGET_FIRST = DMA_TARGET_DMA,
+} dma_target_e;
+
+/* some change of definition for easy to compilation */
+#define BBH_ID_PON BBH_ID_DSL
+#define BB_ID_RX_PON BB_ID_RX_DSL
+#define BB_ID_TX_PON_ETH_PD BB_ID_TX_DSL
+#define BB_ID_TX_PON_ETH_STAT BB_ID_TX_DSL_STAT
+
+#define SDMA_U_THRESH_IN_BBH_LAN_VALUE (0x2)
+#define SDMA_U_THRESH_OUT_BBH_LAN_VALUE	(0x1)
+
+#define SDMA_U_THRESH_IN_BBH_5G_VALUE (0x3)
+#define SDMA_U_THRESH_OUT_BBH_5G_VALUE (0x2)
+
+#define SDMA_U_THRESH_IN_BBH_2P5G_VALUE (0x3)
+#define SDMA_U_THRESH_OUT_BBH_2P5G_VALUE (0x2)
+
+#define SDMA_U_THRESH_IN_BBH_DSL_VALUE (0x6)
+#define SDMA_U_THRESH_OUT_BBH_DSL_VALUE (0x4)
+
+#define SDMA_STRICT_PRI_RX_BBH_LAN_VALUE (0x4)
+#define SDMA_STRICT_PRI_RX_BBH_5G_VALUE (0x04)
+#define SDMA_STRICT_PRI_RX_BBH_2P5G_VALUE (0x04)
+#define SDMA_STRICT_PRI_RX_BBH_DSL_VALUE (0x4)
+
+#define SDMA_STRICT_PRI_TX_BBH_LAN_VALUE (0x04)
+#define DMA_STRICT_PRI_TX_BBH_LAN_VALUE (0x08)
+#define SDMA_STRICT_PRI_TX_BBH_COPY_VALUE (0x04)
+#define DMA_STRICT_PRI_TX_BBH_COPY_VALUE (0x08)
+#define SDMA_STRICT_PRI_TX_BBH_DSL_VALUE (0x04)
+#define DMA_STRICT_PRI_TX_BBH_DSL_VALUE (0x08)
+
+#define SDMA_RR_WEIGHT_RX_BBH_LAN_VALUE (0x00)
+#define SDMA_RR_WEIGHT_RX_BBH_5G_VALUE (0x00)
+#define SDMA_RR_WEIGHT_RX_BBH_2P5G_VALUE (0x00)
+#define SDMA_RR_WEIGHT_RX_BBH_DSL_VALUE (0x00)
+
+#define SDMA_RR_WEIGHT_TX_BBH_LAN_VALUE (0x00)
+#define DMA_RR_WEIGHT_TX_BBH_LAN_VALUE (0x00)
+#define SDMA_RR_WEIGHT_TX_BBH_COPY_VALUE (0x00)
+#define DMA_RR_WEIGHT_TX_BBH_COPY_VALUE (0x00)
+#define SDMA_RR_WEIGHT_TX_BBH_DSL_VALUE (0x00)
+#define DMA_RR_WEIGHT_TX_BBH_DSL_VALUE (0x00)
+#endif
+
+#endif
diff --git a/arch/arm/mach-bcmbca/xrdp/rdp_subsystem_common.h b/arch/arm/mach-bcmbca/xrdp/rdp_subsystem_common.h
new file mode 100644
index 0000000000..c2c93ec85b
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdp_subsystem_common.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2012 Broadcom
+ */
+/*
+* 
+*/
+
+#ifndef __RDP_SUBSYSTEM_COMMON__
+#define __RDP_SUBSYSTEM_COMMON__
+
+/* #include "bcm_hwdefs.h" */
+
+#endif
diff --git a/arch/arm/mach-bcmbca/xrdp/rdpa_cpu_basic.h b/arch/arm/mach-bcmbca/xrdp/rdpa_cpu_basic.h
new file mode 100644
index 0000000000..c72924e1fc
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdpa_cpu_basic.h
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+*  
+*/
+
+
+#ifndef RDPA_CPU_BASIC_H_
+#define RDPA_CPU_BASIC_H_
+
+/** CPU trap reasons */
+typedef enum {
+	rdpa_cpu_reason_min = 0,
+	rdpa_cpu_rx_reason_oam			= 0, /**< OAM packet */
+	rdpa_cpu_rx_reason_omci			= 1, /**< OMCI packet */
+	rdpa_cpu_rx_reason_flow			= 2,
+	rdpa_cpu_rx_reason_mcast		= 3, /**< Multicat packet */
+	rdpa_cpu_rx_reason_bcast		= 4, /**< Broadcast packet */
+	rdpa_cpu_rx_reason_igmp			= 5, /**< Igmp packet */
+	rdpa_cpu_rx_reason_icmpv6		= 6, /**< Icmpv6 packet */
+	rdpa_cpu_rx_reason_mac_trap_0		= 7,
+	rdpa_cpu_rx_reason_mac_trap_1		= 8,
+	rdpa_cpu_rx_reason_mac_trap_2		= 9,
+	rdpa_cpu_rx_reason_mac_trap_3		= 10,
+	rdpa_cpu_rx_reason_dhcp			= 11, /**< DHCP packet */
+	rdpa_cpu_rx_reason_non_tcp_udp		= 12, /**< Packet is non TCP or UDP */
+	rdpa_cpu_rx_reason_local_ip		= 13, /**< CPU ingress packet copy */
+	rdpa_cpu_rx_reason_hdr_err		= 14, /**< Packet with IP header error */
+	rdpa_cpu_rx_reason_sa_moved		= 15, /**< SA move indication*/
+	rdpa_cpu_rx_reason_unknown_sa		= 16, /**< Unknown SA indication */
+	rdpa_cpu_rx_reason_unknown_da		= 17, /**< Unknown DA indication */
+	rdpa_cpu_rx_reason_ip_frag		= 18, /**< Packet is fragmented */
+	rdpa_cpu_rx_reason_mac_spoofing		= 19, /**< Mac spoofing \XRDP_LIMITED */
+	rdpa_cpu_rx_reason_direct_flow		= 20, /**< Direct flow */
+	rdpa_cpu_rx_reason_mcast_miss		= 21, /**< Multicast flow lookup miss */
+	rdpa_cpu_rx_reason_ipsec		= 22, /**< IPSec RX offload */
+	rdpa_cpu_rx_reason_reserved_0		= 23, /* */
+	rdpa_cpu_rx_reason_reserved_1		= 24, /* */
+	rdpa_cpu_rx_reason_reserved_2		= 25, /* */
+	rdpa_cpu_rx_reason_l2cp			= 26, /* \XRDP_LIMITED */
+	rdpa_cpu_rx_reason_cpu_mirroring	= 27, /* */
+	rdpa_cpu_rx_reason_etype_udef_0		= 28, /**< User defined ethertype 1 */
+	rdpa_cpu_rx_reason_etype_udef_1		= 29, /**< User defined ethertype 2 */
+	rdpa_cpu_rx_reason_etype_udef_2		= 30, /**< User defined ethertype 3 */
+	rdpa_cpu_rx_reason_etype_udef_3		= 31, /**< User defined ethertype 4 */
+	rdpa_cpu_rx_reason_etype_pppoe_d	= 32, /**< PPPoE Discovery */
+	rdpa_cpu_rx_reason_etype_pppoe_s	= 33, /**< PPPoE Source */
+	rdpa_cpu_rx_reason_etype_arp		= 34, /**< Packet with ethertype Arp */
+	rdpa_cpu_rx_reason_etype_ptp_1588	= 35, /**< Packet with ethertype 1588 */
+	rdpa_cpu_rx_reason_etype_802_1x		= 36, /**< Packet with ethertype 802_1x */
+	rdpa_cpu_rx_reason_etype_802_1ag_cfm	= 37, /**< Packet with ethertype v801 Lag CFG*/
+	rdpa_cpu_rx_reason_pci_ip_flow_miss_1	= 38, /**< DHD PCI flow miss radio 1 */
+	rdpa_cpu_rx_reason_pci_ip_flow_miss_2	= 39, /**< DHD PCI flow miss radio 2 */
+	rdpa_cpu_rx_reason_pci_ip_flow_miss_3	= 40, /**< DHD PCI flow miss radio 3 */
+	rdpa_cpu_rx_reason_ip_flow_miss		= 41, /**< Flow miss indication */
+	rdpa_cpu_rx_reason_tcp_flags		= 42, /**< TCP flag indication */
+	rdpa_cpu_rx_reason_ttl_expired		= 43, /**< TTL expired indication */
+	rdpa_cpu_rx_reason_mtu_exceeded		= 44, /**< MTU exceeded indication */
+	rdpa_cpu_rx_reason_l4_icmp		= 45, /**< layer-4 ICMP protocol */
+	rdpa_cpu_rx_reason_l4_esp		= 46, /**< layer-4 ESP protocol */
+	rdpa_cpu_rx_reason_l4_gre		= 47, /**< layer-4 GRE protocol */
+	rdpa_cpu_rx_reason_l4_ah		= 48, /**< layer-4 AH protocol */
+	rdpa_cpu_rx_reason_parser_error		= 49, /**< Error when parsing packet \XRDP_LIMITED */
+	rdpa_cpu_rx_reason_l4_ipv6		= 50, /**< layer-4 IPV6 protocol */
+	rdpa_cpu_rx_reason_l4_udef_0		= 51, /**< User defined layer-4 1 */
+	rdpa_cpu_rx_reason_l4_udef_1		= 52, /**< User defined layer-4 2 */
+	rdpa_cpu_rx_reason_l4_udef_2		= 53, /**< User defined layer-4 3 */
+	rdpa_cpu_rx_reason_l4_udef_3		= 54, /**< User defined layer-4 4 */
+	rdpa_cpu_rx_reason_cpu_redirect		= 55, /**< CPU redirect */
+	rdpa_cpu_rx_reason_udef_0		= 56, /**< User defined 1 */
+	rdpa_cpu_rx_reason_udef_1		= 57, /**< User defined 2 */
+	rdpa_cpu_rx_reason_udef_2		= 58, /**< User defined 3 */
+	rdpa_cpu_rx_reason_udef_3		= 59, /**< User defined 4 */
+	rdpa_cpu_rx_reason_udef_4		= 60, /**< User defined 5 */
+	rdpa_cpu_rx_reason_udef_5		= 61, /**< User defined 6 */
+	rdpa_cpu_rx_reason_udef_6		= 62, /**< User defined 7 */
+	rdpa_cpu_rx_reason_udef_7		= 63, /**< User defined 8 */
+	rdpa_cpu_reason__num_of
+} rdpa_cpu_reason;
+
+#if defined(CONFIG_BCM_REASON_TO_SKB_MARK) || defined(BCM_REASON_TO_SKB_MARK)
+#define WEB_ACCESS_IC_TRAP_REASON rdpa_cpu_rx_reason_udef_6
+#define WEB_ACCESS_SKB_MARK_PORT 0x5A
+#endif
+
+#if defined(CONFIG_BCM_DSL_XRDP) || defined(CONFIG_BCM_DSL_RDP)
+#define rdpa_cpu_rx_reason_hit_trap_high rdpa_cpu_rx_reason_udef_4
+#define rdpa_cpu_rx_reason_hit_trap_low	rdpa_cpu_rx_reason_udef_5
+#define rdpa_cpu_rx_reason_ingqos rdpa_cpu_rx_reason_udef_6
+#define RDPACTL_IC_TRAP_REASON_HIGH \
+	(rdpa_cpu_rx_reason_ingqos - rdpa_cpu_rx_reason_udef_0)
+#define rdpa_cpu_rx_reason_tcpspdtst rdpa_cpu_rx_reason_udef_7
+#else
+#define rdpa_cpu_rx_reason_tcpspdtst rdpa_cpu_rx_reason_udef_7
+#endif
+
+/** CPU port */
+typedef enum {
+	rdpa_cpu_port_first = 0,
+	rdpa_cpu0 = rdpa_cpu_port_first,
+	rdpa_cpu_host = rdpa_cpu0, /**< Host RX */
+	rdpa_cpu1,
+	rdpa_cpu_xtm = rdpa_cpu1, /**< XTM RX */
+	rdpa_cpu2,
+	rdpa_cpu3,
+	rdpa_cpu4,
+	rdpa_cpu_wlan0 = rdpa_cpu4, /**< WLAN 0 TX */
+	rdpa_cpu5,
+	rdpa_cpu_wlan1 = rdpa_cpu5,
+	rdpa_cpu6,
+	rdpa_cpu_wlan2 = rdpa_cpu6,
+	rdpa_cpu_port__num_of,
+	rdpa_cpu_none
+} rdpa_cpu_port;
+
+#define RDPA_CPU_MAX_QUEUES 8 /* Max number of queues on host port */
+
+/** TC */
+#define RDPA_CPU_TC_DEFAULT 0
+#define RDPA_CPU_TC_NUM 8
+
+/** CPU reason table indicies */
+#define CPU_REASON_LAN_TABLE_INDEX  0
+#define CPU_REASON_WAN0_TABLE_INDEX 0
+#define CPU_REASON_WAN1_TABLE_INDEX 1
+
+/** @} end of cpu Doxygen group */
+
+/** TC definition */
+typedef enum {
+	rdpa_cpu_tc0	= 0, 
+	rdpa_cpu_tc1	= 1, 
+	rdpa_cpu_tc2	= 2,
+	rdpa_cpu_tc3	= 3, 
+	rdpa_cpu_tc4	= 4, 
+	rdpa_cpu_tc5	= 5,
+	rdpa_cpu_tc6	= 6, 
+	rdpa_cpu_tc7	= 7,
+	rdpa_cpu_tc__num_of,
+} rdpa_cpu_tc;
+
+/** CPU tx packet insertion point */
+typedef enum {
+	/* Egress port and priority are specified explicitly. This is the
+	 * most common mode */
+	rdpa_cpu_tx_port = 0,
+	/* Egress port and priority are specified explicitly. This is the most
+	 * common mode same as rdpa_cpu_tx_egress*/
+	rdpa_cpu_tx_egress = 0,
+	/* Before bridge forwarding decision, before classification */
+	rdpa_cpu_tx_bridge = 1,
+	/* Before bridge forwarding decision, before classification same as
+	 * rdpa_cpu_tx_bridge*/
+	rdpa_cpu_tx_ingress = 1,
+
+	rdpa_cpu_tx_entry__num_of   /**< Number of CPU TX entries */
+} rdpa_cpu_tx_method;
+
+/** Extra data that can be passed along with the packet to be transmitted */
+typedef struct {
+	rdpa_cpu_tx_method method; /* Packet transmit method */
+	/* Destination port for method=port, source port for method=bridge */
+	rdpa_if port;
+	rdpa_cpu_port cpu_port; /* CPU object index */
+	uint8_t ssid; /* SSID, in use when port is wlan */
+	uint8_t lag_index; /* lag_index, in use when port is an SF2 port */
+
+	union {
+		/* queue_id in the following substructures must overlap */
+		struct {
+			uint32_t queue_id; /* Egress queue id */
+		} lan;
+
+		struct {
+			uint32_t queue_id; /* Egress queue id. method=port only */
+			/* Destination flow for method=port, Source flow for
+			 * method=bridge,port=wan */
+			rdpa_flow flow;
+		} wan;
+
+		uint32_t oam_data; /* Extra data entry-specific */
+	} x;
+	uint32_t data; /* data pointer or FPM/BPM hw token */
+	uint16_t data_offset; /* data offset inside pointer */
+	uint16_t data_size; /* size of actuall data */
+
+	union {
+		struct {
+			/* when set, indicates that a Speed Service Setup packet
+			 * is being transmitted */
+			uint8_t is_spdsvc_setup_packet:1;
+			/* BOOL flag, TRUE=never lock QM access, only for send
+			 * dying gasp. Default should be FALSE!! */
+			uint8_t no_lock:1;
+			uint8_t reserved:6;
+		} bits;
+		uint8_t flags; 
+	};
+	rdpa_discard_prty drop_precedence; /* Indicates drop precedence */
+	uint32_t spdt_so_mark; /* Socket mark for Speed Test */
+#ifdef CONFIG_BCM_PTP_1588
+	uint32_t ptp_info;
+#endif
+} rdpa_cpu_tx_info_t;
+
+#endif /* RDPA_CPU_BASIC_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/rdpa_gpl_sbpm.c b/arch/arm/mach-bcmbca/xrdp/rdpa_gpl_sbpm.c
new file mode 100644
index 0000000000..df65e25aaa
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdpa_gpl_sbpm.c
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+	
+*/
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+
+#include "rdpa_gpl_sbpm.h"
+#include "rdp_common.h"
+#include "rdp_subsystem_common.h"
+#include "XRDP_AG.h"
+#if defined(CONFIG_BCM63146)
+#if defined(CONFIG_BCMBCA_XRDP_GPL)
+#include "xrdp_drv_psram.h"
+#include "xrdp_drv_sbpm.h"
+#else
+#include "xrdp_drv_psram_ag.h"
+#include "xrdp_drv_sbpm_ag.h"
+#endif
+#else
+#include "xrdp_drv_psram_mem_ag.h"
+#endif
+
+#define SBPM_MAX_NUM_OF_ITERS 1000
+
+#ifndef MIN
+#define MIN(a, b) ((a) >= (b) ? (b) : (a))
+#endif
+
+static int drv_sbpm_connect_single(uint16_t bn, uint16_t next_bn)
+{
+	int rc, num_of_iters;
+	bdmf_boolean connect_ack, busy, rdy;
+
+	rc = ag_drv_sbpm_regs_bn_connect_set(bn, 1, 0, next_bn);
+	if (rc)
+		return rc;
+	for (num_of_iters = 0; num_of_iters < SBPM_MAX_NUM_OF_ITERS;
+			num_of_iters++) {
+		rc = ag_drv_sbpm_regs_bn_connect_rply_get(&connect_ack, &busy,
+							  &rdy);
+		if (rc)
+			return rc;
+		if (rdy && connect_ack)
+			break;
+	}
+	if (num_of_iters == SBPM_MAX_NUM_OF_ITERS)
+		return BDMF_ERR_INTERNAL;
+	return 0;
+}
+
+static bdmf_error_t drv_sbpm_copy_buf_to_bn(uint16_t bn, uint32_t headroom,
+					    uint8_t *data, uint32_t size)
+{
+#ifdef CONFIG_BCM_PON_XRDP
+	psram_mem_memory_data _data = {};
+
+	memcpy((uint8_t *)(&_data) + headroom, data,
+	       MIN(size, SBPM_BUF_SIZE - headroom));
+	return ag_drv_psram_mem_memory_data_set(bn, &_data);
+#else
+	psram_memory_data _data = {};
+
+	memcpy((uint8_t *)(&_data) + headroom, data,
+	       MIN(size, SBPM_BUF_SIZE - headroom));
+	return ag_drv_psram_memory_data_set(bn, &_data);
+#endif
+}
+
+static bdmf_error_t drv_sbpm_alloc_single(uint32_t size, uint32_t headroom,
+					  uint8_t *data, uint16_t *bn)
+{
+	int rc, num_of_iters;
+	sbpm_regs_bn_alloc_rply reply;
+
+	rc = ag_drv_sbpm_regs_bn_alloc_set(30);
+	if (rc)
+		goto error;
+	for (num_of_iters = 0; num_of_iters < SBPM_MAX_NUM_OF_ITERS;
+			num_of_iters++) {
+		rc = ag_drv_sbpm_regs_bn_alloc_rply_get(&reply);
+		if (rc)
+			goto error;
+		if (reply.rdy && reply.alloc_bn_valid)
+			break;
+	}
+	if (num_of_iters == SBPM_MAX_NUM_OF_ITERS) {
+		printf("%s: alloc single 5 (%d)\n", __FUNCTION__, rc);
+		rc = BDMF_ERR_INTERNAL;
+		goto error;
+	}
+
+	drv_sbpm_copy_buf_to_bn(reply.alloc_bn, headroom, data, size);
+	*bn = reply.alloc_bn;
+	return 0;
+
+error:
+	*bn = SBPM_INVALID_BUFFER_NUMBER;
+	return rc;
+}
+
+bdmf_error_t drv_sbpm_alloc_list(uint32_t size, uint32_t headroom, uint8_t *data,
+				 uint16_t *bn0, uint16_t *bn1, uint8_t *bns_num)
+{
+
+	uint16_t head_bn = SBPM_INVALID_BUFFER_NUMBER, new_bn, curr_bn;
+	int rc = 0, _size, sbpm_buf_size_wo_headroom;
+	uint8_t _bns_num = 1;
+
+	_size = (int)size;
+	sbpm_buf_size_wo_headroom = SBPM_BUF_SIZE - headroom;
+
+	/* Allocate first; then in loop, copy and allocate next as long
+	 * as needed. */
+	rc = drv_sbpm_alloc_single(_size, headroom, data, &head_bn);
+	if (rc)
+		goto error;
+	if (_size <= sbpm_buf_size_wo_headroom) {
+		/* We are done, short packet */
+		new_bn = head_bn; /* Last BN = head BN */
+		goto exit;
+	}
+
+	for (_size -= sbpm_buf_size_wo_headroom,
+			data += sbpm_buf_size_wo_headroom, curr_bn = head_bn;
+	     _size > 0;
+	     _size -= SBPM_BUF_SIZE, data += SBPM_BUF_SIZE, curr_bn = new_bn) {
+		rc = drv_sbpm_alloc_single(_size, 0, data, &new_bn);
+		if (rc)
+			goto error;
+		rc = drv_sbpm_connect_single(curr_bn, new_bn);
+		if (rc) {
+			drv_sbpm_free_list(new_bn);
+			goto error;
+		}
+		_bns_num++;
+	}
+
+exit:
+
+	if (bn0)
+		*bn0 = head_bn;
+	if (bn1)
+		*bn1 = new_bn;
+	if (bns_num)
+		*bns_num = _bns_num;
+	return 0;
+
+error:
+	if (head_bn != SBPM_INVALID_BUFFER_NUMBER)
+		drv_sbpm_free_list(head_bn);
+
+	if (bn0)
+		*bn0 = SBPM_INVALID_BUFFER_NUMBER;
+	if (bn1)
+		*bn1 = SBPM_INVALID_BUFFER_NUMBER;
+	if (bns_num)
+		*bns_num = 0;
+	return rc;
+}
+
+bdmf_error_t drv_sbpm_free_list(uint16_t head_bn)
+{
+	int rc, num_of_iters;
+	sbpm_regs_bn_free_without_contxt_rply reply;
+
+	rc = ag_drv_sbpm_regs_bn_free_without_contxt_set(head_bn, 18, 1);
+	if (rc)
+		return rc;
+	for (num_of_iters = 0; num_of_iters < SBPM_MAX_NUM_OF_ITERS;
+	     num_of_iters++) {
+		rc = ag_drv_sbpm_regs_bn_free_without_contxt_rply_get(&reply);
+		if (rc)
+			return rc;
+		if (reply.rdy)
+			break;
+	}
+	if (reply.free_ack == 0) {
+		bdmf_trace("coudlnt release bn =%d free_ack=0\n", head_bn);
+		return BDMF_ERR_INTERNAL;
+	}
+
+	if (num_of_iters == SBPM_MAX_NUM_OF_ITERS) {
+		bdmf_trace("coudlnt release bn=%d max_iter\n", head_bn);
+		return BDMF_ERR_INTERNAL;
+	}
+
+	return 0;
+}
+
+uint16_t drv_sbpm_get_next_bn(int16_t bn)
+{
+	int rc;
+	sbpm_regs_get_next_rply next_rply = {};
+	uint32_t next_bn = SBPM_INVALID_BUFFER_NUMBER;
+
+	rc = ag_drv_sbpm_regs_get_next_set(bn);
+	while (!rc) {
+		rc = ag_drv_sbpm_regs_get_next_rply_get(&next_rply);
+		if (!next_rply.busy)
+			break;
+	}
+	if (rc)
+		return SBPM_INVALID_BUFFER_NUMBER;
+
+	if (next_rply.bn_valid) {
+		if (!next_rply.bn_null)
+			next_bn = next_rply.next_bn;
+	}
+	else
+		bdmf_trace(" ### BN_NULL (0x%x)\n", next_rply.next_bn);
+
+	if (next_rply.mcnt_val != 0)
+		bdmf_trace("bn: %d, mcast value: %d\n", bn, next_rply.mcnt_val);
+
+	return next_bn;
+}
+
+/* this funnction copy single sbpm to buffer */
+#ifdef CONFIG_BCM_PON_XRDP
+void drv_sbpm_copy_single(psram_mem_memory_data *memory_data, int first,
+			  uint8_t *dest_buffer, uint32_t *dest_index)
+#else
+void drv_sbpm_copy_single(psram_memory_data *memory_data, int first,
+			  uint8_t *dest_buffer, uint32_t *dest_index)
+#endif
+{
+	int i = 0;
+	uint32_t swapped;
+
+	if (first) {
+		/* this is a case to skip headroom in first sbpm header */
+		i = 5;
+		swapped = ((memory_data->memory_data[4] >> 24) & 0xff) |
+			  ((memory_data->memory_data[4] >> 8) & 0xff00) |
+			  ((memory_data->memory_data[4] << 8) & 0xff0000) |
+			  ((memory_data->memory_data[4] << 24) & 0xff000000);
+		dest_buffer[*dest_index + 1] = swapped & 0xff;
+		dest_buffer[*dest_index] = (swapped >> 8) & 0xff;
+		*dest_index +=2;
+	}
+
+
+	for (; i < 32;i++) {
+		swapped = ((memory_data->memory_data[i] >> 24) & 0xff) |
+			  ((memory_data->memory_data[i] >> 8) & 0xff00) |
+			  ((memory_data->memory_data[i] << 8) & 0xff0000) |
+			  ((memory_data->memory_data[i] << 24) & 0xff000000);
+
+		dest_buffer[*dest_index + 3] = swapped& 0xff;
+		dest_buffer[*dest_index + 2] = (swapped >> 8) & 0xff;
+		dest_buffer[*dest_index + 1] = (swapped >> 16) & 0xff;
+		dest_buffer[*dest_index + 0] = (swapped >> 24) & 0xff;
+		*dest_index +=4;
+	}
+}
+
+/* this funnction copy list of sbpm to buffer */
+bdmf_error_t drv_sbpm_copy_list(uint16_t bn, uint8_t *dest_buffer)
+{
+	uint16_t next_bn;
+	int i;
+	uint32_t dest_index = 0;
+#ifdef CONFIG_BCM_PON_XRDP
+	psram_mem_memory_data memory_data;
+#else
+	psram_memory_data memory_data;
+#endif
+
+#ifdef CONFIG_BCM_PON_XRDP
+	ag_drv_psram_mem_memory_data_get(bn, &memory_data);
+#else
+	ag_drv_psram_memory_data_get(bn, &memory_data);
+#endif
+	drv_sbpm_copy_single(&memory_data, 1, &dest_buffer[0], &dest_index);
+
+
+	for (i = 0; i < SBPM_MAX_NUM_OF_BNS; i++) {
+		next_bn = drv_sbpm_get_next_bn(bn);
+		if (next_bn == SBPM_INVALID_BUFFER_NUMBER)
+			break;
+
+		bn = next_bn;
+#ifdef CONFIG_BCM_PON_XRDP
+		ag_drv_psram_mem_memory_data_get(bn, &memory_data);
+#else
+		ag_drv_psram_memory_data_get(bn, &memory_data);
+#endif
+		drv_sbpm_copy_single(&memory_data, 0, &dest_buffer[0],
+				     &dest_index);
+	}
+	if (i == SBPM_MAX_NUM_OF_BNS) {
+		bdmf_trace("===== BAD LIST ALLOCATED, STOP SCANNING...., "
+			   "original bn is %d\n", bn);
+		return BDMF_ERR_INTERNAL;
+	}
+	return 0;
+}
+
diff --git a/arch/arm/mach-bcmbca/xrdp/rdpa_gpl_sbpm.h b/arch/arm/mach-bcmbca/xrdp/rdpa_gpl_sbpm.h
new file mode 100644
index 0000000000..025385aa09
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdpa_gpl_sbpm.h
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+	
+*/
+
+#ifndef _RDP_DRV_SBPM_H_
+#define _RDP_DRV_SBPM_H_
+
+#include <linux/types.h>
+#include <bdmf_errno.h>
+
+#define SBPM_BUF_SIZE 128
+
+bdmf_error_t drv_sbpm_copy_list(uint16_t bn, uint8_t *dest_buffer);
+bdmf_error_t drv_sbpm_alloc_list(uint32_t size, uint32_t headroom,
+				 uint8_t *data, uint16_t *bn0, uint16_t *bn1,
+				 uint8_t *bns_num);
+bdmf_error_t drv_sbpm_free_list(uint16_t head_bn);
+
+#endif
diff --git a/arch/arm/mach-bcmbca/xrdp/rdpa_types.h b/arch/arm/mach-bcmbca/xrdp/rdpa_types.h
new file mode 100644
index 0000000000..62f775ee91
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/rdpa_types.h
@@ -0,0 +1,899 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ *  
+ */
+
+
+#ifndef _RDPA_TYPES_H_
+#define _RDPA_TYPES_H_
+
+#include <bdmf_data_types.h>
+
+/** Traffic direction */
+typedef enum {
+	rdpa_dir_ds, /* Downstream */
+	rdpa_dir_us  /* Upstream */
+} rdpa_traffic_dir;
+
+/* Direction + index, Underlying structure for rdpa_dir_index aggregate */
+typedef struct {
+	rdpa_traffic_dir dir; /* Traffic direction */
+	bdmf_index index; /* Index */
+} rdpa_dir_index_t;
+
+/* PPPoE header */
+typedef struct {
+	uint32_t session; /* PPPoE session ID */
+} rdpa_pppoe_t;
+
+/* PBIT */
+typedef uint8_t rdpa_pbit;
+
+/* DSCP */
+typedef uint8_t rdpa_dscp;
+
+/* DSCP pbit dei */
+typedef struct {
+	uint8_t pbit; /* pbit */
+	uint8_t dei; /* pbit */
+} rdpa_pbit_dei_t;
+
+/* Priority */
+typedef uint8_t rdpa_prty;
+
+/** TCONT index */
+typedef uint8_t rdpa_tcont;
+
+/* Dual Stack lite tunnel ID */
+/* this enum is the only modification needed in order to add more than
+ * one tunnel */
+typedef enum {
+	rdpa_ds_lite_tunnel_0, 
+	rdpa_ds_lite_max_tunnel_id = rdpa_ds_lite_tunnel_0
+} rdpa_ds_lite_tunnel_id;
+
+/* GEM flow ID (internal index) */
+typedef uint16_t rdpa_gem;
+
+/* Ethernet/GEM flow ID */
+typedef uint16_t rdpa_flow;
+
+/* not used by xDSL WAN Mode. flows 1-15 are used by DSL WAN modes for 16
+ * channels in multiples upto 255.
+ * Any other values would collide with the DSL WAN flows. 
+ * values 0x0, 0x10, 0x20... are unused. */
+#define GBE_WAN_FLOW_ID 0
+
+
+/* UNASSIGNED value */
+#define RDPA_VALUE_UNASSIGNED ((unsigned)-1)
+#define RDPA_VALUE_UNMATCHED RDPA_VALUE_UNASSIGNED
+
+/* ANY value */
+#define RDPA_VALUE_ANY ((unsigned)-2)
+
+/* VID/PBIT/DEI */
+#define RDPA_VID_UNTAGGED ((unsigned)-3)
+#define RDPA_MAX_VID 4095
+#define RDPA_MAX_PBIT 7
+#define RDPA_MAX_DEI 1
+
+/* Layer-4 PROTOCOL definitions */
+#define RDPA_INVALID_PROTOCOL (0xFF)
+
+/* TPID Detect.
+ *  A set of TPID values, both pre- and user-defined,
+ *  used to apply tagging classification rules on incoming
+ *  traffic. Accordingly, every packet is classified as Single
+ *  or Double tagged. */
+typedef enum {
+	rdpa_tpid_detect_0x8100, /* Pre-Defined, 0x8100 */
+	rdpa_tpid_detect_0x88A8, /* Pre-Defined, 0x88A8 */
+	rdpa_tpid_detect_0x9100, /* Pre-Defined, 0x9100 */
+	rdpa_tpid_detect_0x9200, /* Pre-Defined, 0x9200 */
+
+	rdpa_tpid_detect_udef_1, /* User-Defined, #1	*/
+	rdpa_tpid_detect_udef_2, /* User-Defined, #2	*/
+
+	rdpa_tpid_detect__num_of
+} rdpa_tpid_detect_t;
+
+
+/* Forwarding action */
+typedef enum {
+	rdpa_forward_action_none	= 0, /* ACL */
+	rdpa_forward_action_forward	= 1, /* Forward */
+	rdpa_forward_action_host	= 2, /* Trap to the host */
+	rdpa_forward_action_drop	= 4, /* Discard */
+	rdpa_forward_action_flood	= 8, /* Flood, for DA lookup only */
+	/* Skip - used for generic filter for increment counter action only */
+	rdpa_forward_action_skip	= 16
+} rdpa_forward_action;
+
+/** Filtering action */
+typedef enum {
+	rdpa_filter_action_allow, /* Allow through */
+	rdpa_filter_action_deny	/* Block packet */
+} rdpa_filter_action;
+
+/** QoS mapping method */
+typedef enum {
+	rdpa_qos_method_flow, /**< Flow-based QoS mapping */
+	rdpa_qos_method_pbit /**< Pbit-based QoS mapping */
+} rdpa_qos_method;
+
+/** Allow frame types */
+typedef enum
+{
+	rdpa_port_allow_any,		/**< Allow tagged and untagged frames */
+	rdpa_port_allow_tagged,	 /**< Allow tagged frames only */
+	rdpa_port_allow_untagged,   /**< Allow untagged frames only */
+} rdpa_port_frame_allow;
+
+/** Forwarding mode */
+typedef enum
+{
+	rdpa_forwarding_mode_pkt,   /**< Packet-based forwarding */
+	rdpa_forwarding_mode_flow,  /**< Flow-based forwarding */
+} rdpa_forwarding_mode;
+
+/** DS Ethernet flow classification mode */
+typedef enum
+{
+	rdpa_classify_mode_pkt,	 /**< Packet-based classification */
+	rdpa_classify_mode_flow,	/**< Flow-based classification */
+} rdpa_classify_mode;
+
+/** Discard priority */
+typedef enum
+{
+	rdpa_discard_prty_low,	  /**< Low priority for Ingress QoS: traffic dropped under high ingress congestion */
+	rdpa_discard_prty_high	  /**< High priority for Ingress QoS: traffic passed under high ingress congresion */
+} rdpa_discard_prty;
+
+/** Flow destination */
+typedef enum
+{
+	rdpa_flow_dest_none,		/**< Not set */
+
+	rdpa_flow_dest_iptv,		/**< IPTV */
+	rdpa_flow_dest_eth,		 /**< Flow */
+	rdpa_flow_dest_omci,		/**< OMCI */
+
+	rdpa_flow_dest__num_of,	 /* Number of values in rdpa_flow_destination enum */
+} rdpa_flow_destination;
+
+/** WAN technology */
+typedef enum
+{
+	rdpa_wan_none,			  /**< Not configured */
+	rdpa_wan_gpon,			  /**< GPON */
+	rdpa_wan_xgpon,			 /**< XGPON */
+	rdpa_wan_epon,			  /**< EPON */
+	rdpa_wan_xepon,			 /**< XEPON */
+	rdpa_wan_gbe,			   /**< GbE */
+	rdpa_wan_dsl,			   /**< xDSL */
+	rdpa_wan_type__num_of
+} rdpa_wan_type;
+
+/** Link speed */
+typedef enum
+{
+	rdpa_speed_none,			/**< Not configured */
+	rdpa_speed_100m,			/**< Speed of 100 Mega */
+	rdpa_speed_1g,			  /**< Speed of 1 Giga */
+	rdpa_speed_2_5g,			/**< Speed of 2.5 Giga */
+	rdpa_speed_5g,			  /**< Speed of 5 Giga */
+	rdpa_speed_10g,			 /**< Speed of 10 Giga */
+} rdpa_speed_type;
+
+/** Simple statistics */
+typedef struct
+{
+	uint32_t packets;		   /**< Packets */
+	uint32_t bytes;			 /**< Bytes */
+} rdpa_stat_t;
+
+/** Generic 1-way statistics */
+typedef struct
+{
+	rdpa_stat_t passed;		 /**< Passed statistics */
+	rdpa_stat_t discarded;	  /**< Discarded statistics */
+} rdpa_stat_1way_t;
+
+/** Tx+Rx statistics */
+typedef struct
+{
+	rdpa_stat_1way_t tx;		/**< Transmit statistics */
+	rdpa_stat_1way_t rx;		/**< Receive statistics */
+} rdpa_stat_tx_rx_t;
+
+/** Tx+Rx statistics for passed packets + bytes  */
+typedef struct
+{
+	rdpa_stat_t tx;			 /**< Transmit statistics */
+	rdpa_stat_t rx;			 /**< Receive statistics */
+} rdpa_stat_tx_rx_valid_t;
+
+/** RDPA interface (port).
+ * The enum includes physical and virtual ports that
+ * can appear in bridging / routing rules as ingress or egress interface.
+ * The port list does not include VLAN-based virtual interfaces and tunnels.
+ * Aggregation ports, such as PCI and SWITCH, can be used in 2-level scheduling.
+ */
+typedef enum
+{
+	rdpa_if_first,		  /*< First interface */
+
+	/** WAN ports */
+	rdpa_if_wan0 = rdpa_if_first, /**< WAN0 port */
+	rdpa_if_wan1,		   /**< WAN1 port */
+	rdpa_if_wan2,		   /**< WAN2 port */
+	rdpa_if_wan_max = rdpa_if_wan2,
+	/** LAN ports */
+	rdpa_if_lan0,		   /**< LAN0 port */
+	rdpa_if_lan1,		   /**< LAN1 port */
+	rdpa_if_lan2,		   /**< LAN2 port */
+	rdpa_if_lan3,		   /**< LAN3 port */
+	rdpa_if_lan4,		   /**< LAN4 port */
+	rdpa_if_lan5,		   /**< LAN5 port */
+	rdpa_if_lan6,		   /**< LAN6 port */
+	rdpa_if_lan7,		   /**< LAN7 port */
+#if defined(BCM_DSL_RDP) || defined(BCM_DSL_XRDP)
+	rdpa_if_lan_max = rdpa_if_lan7,
+#else /* DSL Platforms */
+	rdpa_if_lan8,		   /**< LAN8 port */
+	rdpa_if_lan9,		   /**< LAN9 port */
+	rdpa_if_lan10,		   /**< LAN10 port */
+	rdpa_if_lan11,		   /**< LAN11 port */
+	rdpa_if_lan12,		   /**< LAN12 port */
+	rdpa_if_lan13,		   /**< LAN13 port */
+	rdpa_if_lan14,		   /**< LAN14 port */
+	rdpa_if_lan15,		   /**< LAN15 port */
+	rdpa_if_lan16,		   /**< LAN16 port */
+	rdpa_if_lan17,		   /**< LAN17 port */
+	rdpa_if_lan18,		   /**< LAN18 port */
+	rdpa_if_lan19,		   /**< LAN19 port */
+	rdpa_if_lan20,		   /**< LAN20 port */
+	rdpa_if_lan21,		   /**< LAN21 port */
+#ifdef G9991
+	rdpa_if_lan22,		   /**< LAN22 port */
+	rdpa_if_lan23,		   /**< LAN23 port */
+	rdpa_if_lan24,		   /**< LAN24 port */
+	rdpa_if_lan25,		   /**< LAN25 port */
+	rdpa_if_lan26,		   /**< LAN26 port */
+	rdpa_if_lan27,		   /**< LAN27 port */
+	rdpa_if_lan28,		   /**< LAN28 port */
+	rdpa_if_lan29,		   /**< LAN29 port */
+	rdpa_if_lan_max = rdpa_if_lan29,
+#else
+	rdpa_if_lan_max = rdpa_if_lan21,
+#endif
+#endif /* PON Platforms */
+	/** Special ports */
+	rdpa_if_lag0,		   /**< Physical emac0 port */
+	rdpa_if_lag1,		   /**< Physical emac1 port */
+	rdpa_if_lag2,		   /**< Physical emac2 port */
+	rdpa_if_lag3,		   /**< Physical emac3 port */
+	rdpa_if_lag4,		   /**< Physical emac4 port */
+	rdpa_if_lag_max = rdpa_if_lag4,
+
+	/** Switch aggregate port */
+	rdpa_if_switch,		 /**< LAN switch port */
+
+#ifndef XRDP
+	/** CPU ports for WLAN usage (local termination) */
+	rdpa_if_wlan0,
+	rdpa_if_cpu_first = rdpa_if_wlan0,
+	rdpa_if_wlan1,
+	rdpa_if_wlan_last = rdpa_if_wlan1,
+	/** CPU (local termination) */
+	rdpa_if_cpu,				/**< CPU port (local termination) */
+
+	rdpa_if_max_mcast_port = rdpa_if_cpu, /* only above ports could be part of mcast egress port mask */
+
+	/** Wi-Fi logical ports (SSIDs) */
+	rdpa_if_ssid0,		  /**< Wi-Fi: SSID0 */
+	rdpa_if_ssid1,		  /**< Wi-Fi: SSID1 */
+	rdpa_if_ssid2,		  /**< Wi-Fi: SSID2 */
+	rdpa_if_ssid3,		  /**< Wi-Fi: SSID3 */
+	rdpa_if_ssid4,		  /**< Wi-Fi: SSID4 */
+	rdpa_if_ssid5,		  /**< Wi-Fi: SSID5 */
+	rdpa_if_ssid6,		  /**< Wi-Fi: SSID6 */
+	rdpa_if_ssid7,		  /**< Wi-Fi: SSID7 */
+	rdpa_if_ssid8,		  /**< Wi-Fi: SSID8 */
+	rdpa_if_ssid9,		  /**< Wi-Fi: SSID9 */
+	rdpa_if_ssid10,		 /**< Wi-Fi: SSID10 */
+	rdpa_if_ssid11,		 /**< Wi-Fi: SSID11 */
+	rdpa_if_ssid12,		 /**< Wi-Fi: SSID12 */
+	rdpa_if_ssid13,		 /**< Wi-Fi: SSID13 */
+	rdpa_if_ssid14,		 /**< Wi-Fi: SSID14 */
+	rdpa_if_ssid15,		 /**< Wi-Fi: SSID15 */
+	rdpa_if_cpu_last = rdpa_if_ssid15,
+#else
+	/** CPU ports (local termination) */
+	rdpa_if_cpu0, /**< CPU0 port (local termination) */
+	rdpa_if_cpu_first = rdpa_if_cpu0,
+	rdpa_if_cpu = rdpa_if_cpu0,
+	rdpa_if_max_mcast_port = rdpa_if_cpu, /* only above ports could be part of mcast egress port mask */
+	rdpa_if_cpu1,		   /**< CPU1 port (local termination) */
+	rdpa_if_cpu2,		   /**< CPU2 port (local termination) */
+	rdpa_if_cpu3,		   /**< CPU3 port (local termination) */
+	rdpa_if_wlan0,		   /**< CPU port (local termination) reserved for WLAN0 */
+	rdpa_if_wlan1,		   /**< CPU port (local termination) reserved for WLAN1 */
+	rdpa_if_wlan2,		   /**< CPU port (local termination) reserved for WLAN2 */
+	rdpa_if_wlan_last = rdpa_if_wlan2,
+	rdpa_if_cpu_last = rdpa_if_wlan2,
+#endif
+
+	rdpa_if_bond0,		  /**< Virtual Port bonding interface 0 */
+	rdpa_if_bond1,		  /**< Virtual Port bonding interface 1 */
+	rdpa_if_bond2,		  /**< Virtual Port bonding interface 2 */
+	rdpa_if_bond_max = rdpa_if_bond2,
+	rdpa_if_any,			/**< Any Port */
+
+
+	rdpa_if__number_of,
+
+	rdpa_if_none			/**< No port */
+
+} rdpa_if;
+
+typedef enum 
+{
+	rdpa_wlan_ssid0,
+	rdpa_wlan_ssid1,
+	rdpa_wlan_ssid2,
+	rdpa_wlan_ssid3,
+	rdpa_wlan_ssid4,
+	rdpa_wlan_ssid5,
+	rdpa_wlan_ssid6,
+	rdpa_wlan_ssid7,
+	rdpa_wlan_ssid8,
+	rdpa_wlan_ssid9,
+	rdpa_wlan_ssid10,
+	rdpa_wlan_ssid11,
+	rdpa_wlan_ssid12,
+	rdpa_wlan_ssid13,
+	rdpa_wlan_ssid14,
+	rdpa_wlan_ssid15,
+} rdpa_wlan_ssid;
+
+/** EMAC id */
+typedef enum
+{
+	rdpa_emac0,			 /**< EMAC0 */
+	rdpa_emac1,			 /**< EMAC1 */
+	rdpa_emac2,			 /**< EMAC2 */
+	rdpa_emac3,			 /**< EMAC3 */
+	rdpa_emac4,			 /**< EMAC4 */
+	rdpa_emac5,			 /**< EMAC5 */
+	rdpa_emac6,			 /**< EMAC6 */
+	rdpa_emac7,			 /**< EMAC7 */
+	rdpa_emac__num_of,	  /* Max number of EMACs */
+	rdpa_emac_none,	  /**< Indicates virtual port */
+} rdpa_emac;
+
+/** EMAC mode */
+typedef enum
+{
+	rdpa_emac_mode_sgmii,   /**< SGMII */
+	rdpa_emac_mode_hisgmii, /**< HISGMII */
+	rdpa_emac_mode_qsgmii,  /**< QSGMII */
+	rdpa_emac_mode_ss_smii, /**< SS SMII */
+	rdpa_emac_mode_rgmii,   /**< RGMII */
+	rdpa_emac_mode_mii,	 /**< MII */
+	rdpa_emac_mode_tmii,	/**< TMII */
+
+	rdpa_emac_mode__num_of, /* Number of EMAC modes */
+} rdpa_emac_mode;
+
+
+/** EMAC rates */
+typedef enum
+{
+	rdpa_emac_rate_10m,	 /**< 10 Mbps */
+	rdpa_emac_rate_100m,	/**< 100 Mbps */
+	rdpa_emac_rate_1g,	  /**< 1 Gbps */
+	rdpa_emac_rate_2_5g,	/**< 2.5 Gbps */
+
+	rdpa_emac_rate__num_of, /* Number of rates */
+} rdpa_emac_rate;
+
+/** EMAC configuration */
+typedef struct
+{
+	char loopback;	  /**< 1 = line loopback */
+	rdpa_emac_rate rate;	   /**< EMAC rate */
+	char generate_crc;  /**< 1 = generate CRC */
+	char full_duplex;   /**< 1 = full duplex */
+	char pad_short;	 /**< 1 = pad short frames */
+	char allow_too_long;/**< 1 = allow long frames */
+	char check_length;  /**< 1 = check frame length */
+	uint32_t preamble_length;   /**< Preamble length */
+	uint32_t back2back_gap;	 /**< Back2Back inter-packet gap */
+	uint32_t non_back2back_gap; /**< Non Back2Back inter-packet gap */
+	uint32_t min_interframe_gap; /**< Min inter-frame gap */
+	char rx_flow_control;/**< 1 = enable RX flow control */
+	char tx_flow_control;/**< 1 = enable TX flow control */
+} rdpa_emac_cfg_t;
+
+/** RX RMON counters.
+ * Underlying type for emac_rx_stat aggregate type.
+ */
+typedef struct
+{
+	uint32_t byte;			  /**< Receive Byte Counter */
+	uint32_t packet;			/**< Receive Packet Counter */
+	uint32_t frame_64;		  /**< Receive 64 Byte Frame Counter */
+	uint32_t frame_65_127;	  /**< Receive 65 to 127 Byte Frame Counter */
+	uint32_t frame_128_255;	 /**< Receive 128 to 255 Byte Frame Counter */
+	uint32_t frame_256_511;	 /**< Receive 256 to 511 Byte Frame Counter */
+	uint32_t frame_512_1023;	/**< Receive 512 to 1023 Byte Frame Counter */
+	uint32_t frame_1024_1518;   /**< Receive 1024 to 1518 Byte Frame Counter */
+	uint32_t frame_1519_mtu;	/**< Receive 1519 to MTU Frame Counter */
+	uint32_t multicast_packet;  /**< Receive Multicast Packet */
+	uint32_t broadcast_packet;  /**< Receive Broadcast Packet */
+	uint32_t unicast_packet;	/**< Receive Unicast Packet */
+	uint32_t alignment_error;   /**< Receive Alignment error */
+	uint32_t frame_length_error;/**< Receive Frame Length Error Counter */
+	uint32_t code_error;		/**< Receive Code Error Counter */
+	uint32_t carrier_sense_error;/**< Receive Carrier sense error */
+	uint32_t fcs_error;		 /**< Receive FCS Error Counter */
+	uint32_t control_frame;	 /**< Receive Control Frame Counter */
+	uint32_t pause_control_frame;/**< Receive Pause Control Frame */
+	uint32_t unknown_opcode;	/**< Receive Unknown opcode */
+	uint32_t undersize_packet;  /**< Receive Undersize Packet */
+	uint32_t oversize_packet;   /**< Receive Oversize Packet */
+	uint32_t fragments;		 /**< Receive Fragments */
+	uint32_t jabber;			/**< Receive Jabber counter */
+	uint32_t overflow;		  /**< Receive Overflow counter */
+} rdpa_emac_rx_stat_t;
+
+/** Tx RMON counters.
+ * Underlying type for emac_tx_stat aggregate type.
+ */
+typedef struct
+{
+	uint32_t byte;			  /**< Transmit Byte Counter */
+	uint32_t packet;			/**< Transmit Packet Counter */
+	uint32_t frame_64;		  /**< Transmit 64 Byte Frame Counter */
+	uint32_t frame_65_127;	  /**< Transmit 65 to 127 Byte Frame Counter */
+	uint32_t frame_128_255;	 /**< Transmit 128 to 255 Byte Frame Counter */
+	uint32_t frame_256_511;	 /**< Transmit 256 to 511 Byte Frame Counter */
+	uint32_t frame_512_1023;	/**< Transmit 512 to 1023 Byte Frame Counter */
+	uint32_t frame_1024_1518;   /**< Transmit 1024 to 1518 Byte Frame Counter */
+	uint32_t frame_1519_mtu;	/**< Transmit 1519 to MTU Frame Counter */
+	uint32_t fcs_error;		 /**< Transmit FCS Error */
+	uint32_t multicast_packet;  /**< Transmit Multicast Packet */
+	uint32_t broadcast_packet;  /**< Transmit Broadcast Packet */
+	uint32_t unicast_packet;	/**< Transmit Unicast Packet */
+	uint32_t excessive_collision; /**< Transmit Excessive collision counter */
+	uint32_t late_collision;	/**< Transmit Late collision counter */
+	uint32_t single_collision;  /**< Transmit Single collision frame counter */
+	uint32_t multiple_collision;/**< Transmit Multiple collision frame counter */
+	uint32_t total_collision;   /**< Transmit Total Collision Counter */
+	uint32_t pause_control_frame; /**< Transmit PAUSE Control Frame */
+	uint32_t deferral_packet;   /**< Transmit Deferral Packet */
+	uint32_t excessive_deferral_packet; /**< Transmit Excessive Deferral Packet */
+	uint32_t jabber_frame;	  /**< Transmit Jabber Frame */
+	uint32_t control_frame;	 /**< Transmit Control Frame */
+	uint32_t oversize_frame;	/**< Transmit Oversize Frame counter */
+	uint32_t undersize_frame;   /**< Transmit Undersize Frame */
+	uint32_t fragments_frame;   /**< Transmit Fragments Frame counter */
+	uint32_t error;			 /**< Transmission errors*/
+	uint32_t underrun;		  /**< Transmission underrun */
+} rdpa_emac_tx_stat_t;
+
+/** Emac statistics */
+typedef struct
+{
+	rdpa_emac_rx_stat_t rx; /**< Emac Receive Statistics */
+	rdpa_emac_tx_stat_t tx; /**< Emac Transmit Statistics */
+} rdpa_emac_stat_t;
+
+/** RDPA EMAC mask
+ * A combination of \ref rdpa_emac_id constants.
+ */
+typedef unsigned int rdpa_emacs;
+
+/** RDPA emac mask.
+ * \param[in] __emac EMAC
+ * \return EMAC - Mask representation
+ */
+static inline rdpa_emacs rdpa_emac_id(rdpa_emac __emac)
+{
+	return 1 << (__emac);
+}
+
+/** RDPA port mask
+ * A combination of \ref rdpa_if_id constants.
+ */
+typedef uint64_t rdpa_ports __attribute__((aligned(8)));
+
+/** RDPA interface (port) mask.
+ * Can be combined in rdpa_ports mask to specify multiple ports in the same operation.
+ * \param[in] __if Interface
+ * \return Interface - Mask representation
+ */
+static inline rdpa_ports rdpa_if_id(rdpa_if __if)
+{
+	return 1LL << (__if);
+}
+
+/** All WAN ports */
+#define RDPA_PORT_ALL_WAN   (rdpa_if_id(rdpa_if_wan0) | rdpa_if_id(rdpa_if_wan1) | rdpa_if_id(rdpa_if_wan2))
+
+/** Check if interface is WAN interface
+ * \param[in]   __if	 Interface
+ * \return 1 WAN, 0 otherwise
+ */
+static inline int rdpa_if_is_wan(rdpa_if __if)
+{
+	return (RDPA_PORT_ALL_WAN & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+/** Map a given WAN type to the corresponding WAN interface per the platform support.
+ * \param[in]   __wan	WAN type 
+ * \return Interface (rdpa_if_wan0/1/2) or rdpa_if_none if wan_type is not supported on the platform
+ */
+static inline rdpa_if rdpa_wan_type_to_if(rdpa_wan_type __wan)
+{
+#if defined(CONFIG_BCM63146)
+   switch (__wan) {
+	  case rdpa_wan_gbe	   :
+		 return (rdpa_if_wan0);
+	  case rdpa_wan_dsl	   :
+		 return (rdpa_if_wan1);
+	  default				 :
+		 return (rdpa_if_none);
+   }
+#else /* PON Platforms */
+   switch (__wan) {
+	  case rdpa_wan_gpon	  :
+	  case rdpa_wan_xgpon	 :
+	  case rdpa_wan_epon	  :
+	  case rdpa_wan_xepon	 :
+		 return (rdpa_if_wan0);
+	  case rdpa_wan_gbe	   :
+#ifdef CONFIG_MULTI_WAN_SUPPORT
+		 return (rdpa_if_wan1);
+#else
+		 return (rdpa_if_wan0);
+#endif
+	  default				 :
+		 return (rdpa_if_none);
+   }
+#endif /* PON Platforms */
+}
+
+/** All LAN MACs */
+#ifndef XRDP
+#define RDPA_PORT_ALL_LOOKUP_PORTS \
+	(rdpa_if_id(rdpa_if_wan0) | rdpa_if_id(rdpa_if_lan0) | rdpa_if_id(rdpa_if_lan1) | rdpa_if_id(rdpa_if_lan2) | \
+		rdpa_if_id(rdpa_if_lan3) | rdpa_if_id(rdpa_if_lan4))
+#endif
+/** All LAN MACs */
+#ifdef G9991
+#define RDPA_PORT_ALL_LAN_MACS \
+	(rdpa_if_id(rdpa_if_lan0) | rdpa_if_id(rdpa_if_lan1) | rdpa_if_id(rdpa_if_lan2) | \
+	 rdpa_if_id(rdpa_if_lan3) | rdpa_if_id(rdpa_if_lan4) | rdpa_if_id(rdpa_if_lan5) | \
+	 rdpa_if_id(rdpa_if_lan6) | rdpa_if_id(rdpa_if_lan7) | rdpa_if_id(rdpa_if_lan8) | \
+	 rdpa_if_id(rdpa_if_lan9) | rdpa_if_id(rdpa_if_lan10) | rdpa_if_id(rdpa_if_lan11) | \
+	 rdpa_if_id(rdpa_if_lan12) | rdpa_if_id(rdpa_if_lan13) | rdpa_if_id(rdpa_if_lan14) | \
+	 rdpa_if_id(rdpa_if_lan15) | rdpa_if_id(rdpa_if_lan16) | rdpa_if_id(rdpa_if_lan17) | \
+	 rdpa_if_id(rdpa_if_lan18) | rdpa_if_id(rdpa_if_lan19) | rdpa_if_id(rdpa_if_lan20) | \
+	 rdpa_if_id(rdpa_if_lan21) | rdpa_if_id(rdpa_if_lan22) | rdpa_if_id(rdpa_if_lan23) | \
+	 rdpa_if_id(rdpa_if_lan24) | rdpa_if_id(rdpa_if_lan25) | rdpa_if_id(rdpa_if_lan26) | \
+	 rdpa_if_id(rdpa_if_lan27) | rdpa_if_id(rdpa_if_lan28) | rdpa_if_id(rdpa_if_lan29))
+#elif defined(BCM_DSL_RDP) || defined(BCM_DSL_XRDP)
+#define RDPA_PORT_ALL_LAN_MACS \
+	(rdpa_if_id(rdpa_if_lan0) | rdpa_if_id(rdpa_if_lan1) | rdpa_if_id(rdpa_if_lan2) | \
+	 rdpa_if_id(rdpa_if_lan3) | rdpa_if_id(rdpa_if_lan4) | rdpa_if_id(rdpa_if_lan5) | \
+	 rdpa_if_id(rdpa_if_lan6) | rdpa_if_id(rdpa_if_lan7))
+#else
+#define RDPA_PORT_ALL_LAN_MACS \
+	(rdpa_if_id(rdpa_if_lan0) | rdpa_if_id(rdpa_if_lan1) | rdpa_if_id(rdpa_if_lan2) | \
+	 rdpa_if_id(rdpa_if_lan3) | rdpa_if_id(rdpa_if_lan4) | rdpa_if_id(rdpa_if_lan5) | \
+	 rdpa_if_id(rdpa_if_lan6) | rdpa_if_id(rdpa_if_lan7) | rdpa_if_id(rdpa_if_lan8) | \
+	 rdpa_if_id(rdpa_if_lan9) | rdpa_if_id(rdpa_if_lan10) | rdpa_if_id(rdpa_if_lan11) | \
+	 rdpa_if_id(rdpa_if_lan12) | rdpa_if_id(rdpa_if_lan13) | rdpa_if_id(rdpa_if_lan14) | \
+	 rdpa_if_id(rdpa_if_lan15) | rdpa_if_id(rdpa_if_lan16) | rdpa_if_id(rdpa_if_lan17) | \
+	 rdpa_if_id(rdpa_if_lan18) | rdpa_if_id(rdpa_if_lan19) | rdpa_if_id(rdpa_if_lan20) | \
+	 rdpa_if_id(rdpa_if_lan21))
+#endif
+
+/** All physical ports */
+#define RDPA_PORT_LAG_AND_SWITCH_PORTS \
+	(rdpa_if_id(rdpa_if_lag0) | rdpa_if_id(rdpa_if_lag1) | rdpa_if_id(rdpa_if_lag2) | \
+		rdpa_if_id(rdpa_if_lag3) | rdpa_if_id(rdpa_if_lag4) | rdpa_if_id(rdpa_if_switch))
+
+/** All EMACs */
+#ifndef XRDP
+#define RDPA_PORT_ALL_EMACS \
+	(rdpa_emac_id(rdpa_emac0) | rdpa_emac_id(rdpa_emac1) | rdpa_emac_id(rdpa_emac2) | \
+		rdpa_emac_id(rdpa_emac3) | rdpa_emac_id(rdpa_emac4) | rdpa_emac_id(rdpa_emac5))
+#else
+#define RDPA_PORT_ALL_EMACS \
+	(rdpa_emac_id(rdpa_emac0) | rdpa_emac_id(rdpa_emac1) | rdpa_emac_id(rdpa_emac2) | \
+		rdpa_emac_id(rdpa_emac3) | rdpa_emac_id(rdpa_emac4) | rdpa_emac_id(rdpa_emac5) |\
+		rdpa_emac_id(rdpa_emac6))
+#endif
+
+/** All LAN ports */
+#define RDPA_PORT_ALL_LAN (RDPA_PORT_ALL_LAN_MACS)
+/** All LAN ports and physical */
+#define RDPA_PORT_ALL_LAN_AND_LAG (RDPA_PORT_ALL_LAN_MACS | RDPA_PORT_LAG_AND_SWITCH_PORTS)
+
+/** Check if interface is LAN interface (LAN EMAC port or LAN switch port, not including Wi-Fi ports)
+ * \param[in]   __if	 Interface
+ * \return 1 LAN (port or switch), 0 otherwise
+ */
+static inline int rdpa_if_is_lan(rdpa_if __if)
+{
+	return (RDPA_PORT_ALL_LAN & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+/** Check if interface is LAN interface (LAN EMAC port, not including WiFi ports)
+ * \param[in]   __if	 Interface
+ * \return 1 LAN , 0 otherwise
+ */
+static inline int rdpa_if_is_lan_mac(rdpa_if __if)
+{
+	return (RDPA_PORT_ALL_LAN_MACS & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+/** Check if interface is LAN interface (LAN EMAC port or physical port)
+ * \param[in]   __if	 Interface
+ * \return 1 LAN (port or phisical), 0 otherwise
+ */
+static inline int rdpa_if_is_lan_lag_and_switch(rdpa_if __if)
+{
+	return (RDPA_PORT_ALL_LAN_AND_LAG & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+
+/** Check if interface is LAG interface (physical port)
+ * \param[in]   __if	 Interface
+ * \return 1 LAN (port or phisical), 0 otherwise
+ */
+static inline int rdpa_if_is_lag_and_switch(rdpa_if __if)
+{
+	return (RDPA_PORT_LAG_AND_SWITCH_PORTS & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+/** All WLAN ports */
+#ifdef XRDP
+#define RDPA_PORT_ALL_WLAN \
+	(rdpa_if_id(rdpa_if_wlan0) | rdpa_if_id(rdpa_if_wlan1) | rdpa_if_id(rdpa_if_wlan2))
+#else
+#define RDPA_PORT_ALL_WLAN \
+	(rdpa_if_id(rdpa_if_wlan0) | rdpa_if_id(rdpa_if_wlan1))
+#endif
+
+/** Check if interface is WLAN (PCI port)
+ * \param[in]   __if	 Interface
+ * \return 1 if WLAN port, 0 otherwise
+ */
+static inline int rdpa_if_is_wlan(rdpa_if __if)
+{
+	return (RDPA_PORT_ALL_WLAN & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+#if defined(CONFIG_BCM_PON_XRDP) || defined(BCM_DSL_XRDP)
+#define WL_NUM_OF_SSID_PER_UNIT		16
+#else
+#define WL_NUM_OF_SSID_PER_UNIT		8
+#endif /* CONFIG_BCM_PON */
+
+/** All Bond ports */
+#define RDPA_PORT_ALL_BOND \
+	(rdpa_if_id(rdpa_if_bond0) | rdpa_if_id(rdpa_if_bond1) | rdpa_if_id(rdpa_if_bond2))
+
+/** Check if interface is Bonded
+ * \param[in]   __if	 Interface
+ * \return 1 if Bond port, 0 otherwise
+ */
+static inline int rdpa_if_is_bond(rdpa_if __if)
+{
+	return (RDPA_PORT_ALL_BOND & rdpa_if_id(__if)) ? 1 : 0;
+}
+
+
+#ifndef XRDP
+/** All WiFi virtual interfaces */
+#define RDPA_PORT_ALL_SSIDS \
+	(rdpa_if_id(rdpa_if_ssid0) | rdpa_if_id(rdpa_if_ssid1) | rdpa_if_id(rdpa_if_ssid2) | rdpa_if_id(rdpa_if_ssid3) | \
+		rdpa_if_id(rdpa_if_ssid4) | rdpa_if_id(rdpa_if_ssid5) | rdpa_if_id(rdpa_if_ssid6) | rdpa_if_id(rdpa_if_ssid7) | \
+		rdpa_if_id(rdpa_if_ssid8) | rdpa_if_id(rdpa_if_ssid9) | rdpa_if_id(rdpa_if_ssid10) | rdpa_if_id(rdpa_if_ssid11) | \
+		rdpa_if_id(rdpa_if_ssid12) | rdpa_if_id(rdpa_if_ssid13) | rdpa_if_id(rdpa_if_ssid14) | rdpa_if_id(rdpa_if_ssid15))
+
+/** Check if interface is Wi-Fi SSID
+ * \param[in]   __if	 Interface
+ * \return 1 Wi-Fi SSID, 0 otherwise
+ */
+static inline int rdpa_if_is_wifi(rdpa_if __if)
+{
+	return (RDPA_PORT_ALL_SSIDS & rdpa_if_id(__if)) ? 1 : 0;
+}
+#else
+static inline int rdpa_if_is_wifi(rdpa_if __if)
+{
+	return rdpa_if_is_wlan(__if);
+}
+#endif
+
+static inline int rdpa_if_is_cpu_port(rdpa_if __if)
+{
+	return __if >= rdpa_if_cpu_first && __if <= rdpa_if_cpu_last;
+}
+
+/** Check if interface is either LAN interface (LAN EMAC port or LAN switch port) or Wi-Fi SSID
+ * \param[in] __if Interface
+ * \return 1 LAN interface or Wi-Fi SSID, 0 otherwise
+ */
+static inline int rdpa_if_is_lan_or_wifi(rdpa_if __if)
+{
+	return rdpa_if_is_lan(__if) || rdpa_if_is_wifi(__if);
+}
+
+/** Check if interface is either LAN interface (LAN EMAC port or LAN switch port) or WLAN (PCI port)
+ * \param[in] __if Interface
+ * \return 1 LAN interface or WLAN, 0 otherwise
+ */
+static inline int rdpa_if_is_lan_or_cpu(rdpa_if __if)
+{
+	return rdpa_if_is_lan(__if) || rdpa_if_is_cpu_port(__if);
+}
+
+/** Check if interface is CPU and not WLAN (PCI port)
+ * \param[in] __if Interface
+ * \return 1 if pure CPU, 0 otherwise
+ */
+static inline int rdpa_if_is_cpu_not_wlan(rdpa_if __if)
+{
+	return rdpa_if_is_cpu_port(__if) && (!rdpa_if_is_wlan(__if));
+}
+
+
+/** All MACs */
+#define RDPA_PORT_ALL_MACS (RDPA_PORT_ALL_LAN_MACS | RDPA_PORT_ALL_WAN)
+
+/** Check if port mask contains single port
+ * \param[in] ports Port Mask
+ * \return 1 if mask contains a single port , 0 otherwise
+ */
+static inline int rdpa_port_is_single(rdpa_ports ports)
+{
+	return (ports & (ports - 1)) == 0;
+}
+
+/** Check if port mask contains wan0 port
+ * \param[in] ports Port Mask
+ * \return 1 if mask contains a wan0 port , 0 otherwise
+ */
+static inline int rdpa_ports_contains_wan0_if(rdpa_ports ports)
+{
+	return ports & rdpa_if_id(rdpa_if_wan0); /* FIXME - MULTI-WAN XPON */
+}
+
+/** System operation mode */
+typedef enum
+{
+	rdpa_method_prv,		  /**< Used to configure system in Provision mode */
+	rdpa_method_fc,		   /**< Used to configure system in Flow Cache mode */
+} rdpa_operation_mode;
+
+/** IPTV entries lookup method */
+typedef enum
+{
+	iptv_lookup_method_mac, /**< Perform IPTV entry lookup by MAC address (L2) */
+	iptv_lookup_method_mac_vid, /**< Perform IPTV entry lookup by MAC address and VID (L2) */
+	iptv_lookup_method_group_ip, /**< Perform IPTV entry lookup by Multicast Group IP address (IGMPv2/MLDv1) */
+	iptv_lookup_method_group_ip_src_ip, /**< Perform IPTV entry lookup by Multicast Group IP and Source IP
+											 addresses (IGMPv3/MLDv2). Source IP address is optional. */
+	iptv_lookup_method_group_ip_src_ip_vid /**< Perform IPTV entry lookup by Multicast Group IP and Source IP
+												addresses and VID. Source IP address is optional. */
+} rdpa_iptv_lookup_method;
+
+/** EPON mode */
+typedef enum
+{
+	rdpa_epon_none,			/**< not EPON mode */ 
+	rdpa_epon_ctc,			 /**< CTC OAM mode */
+	rdpa_epon_cuc,			 /**< CUC OAM mode */
+	rdpa_epon_dpoe,			/**< DPOE OAM mode */
+	rdpa_epon_bcm,			 /**< BCM OAM mode */
+	rdpa_epon_ctc_dyn,		 /**< CTC OAM dynamic mode  */
+	rdpa_epon_cuc_dyn,		 /**< CUC OAM dynamic mode  */
+	rdpa_epon_last,
+} rdpa_epon_mode;
+
+/** Packet offset type */
+typedef enum
+{
+	RDPA_OFFSET_L2, /**< Offset of L2 header */
+	RDPA_OFFSET_L3, /**< Offset of L3 header */
+	RDPA_OFFSET_L4, /**< Offset of L4 header */
+} rdpa_offset_t;
+
+/* BPM buffer size */
+typedef enum
+{
+	RDPA_BPM_BUFFER_2K = 2048,
+	RDPA_BPM_BUFFER_2_5K = 2560,
+	RDPA_BPM_BUFFER_4K = 4096,
+	RDPA_BPM_BUFFER_16K = 16384,
+} rdpa_bpm_buffer_size_t;
+
+/** WiFi Acceleration type */
+typedef enum
+{
+	RDPA_WL_ACCEL_NONE = 0,	 /**< Acceleration disabled */
+	RDPA_WL_ACCEL_WFD,		  /**< WFD Acceleration type */
+	RDPA_WL_ACCEL_DHD_OFFLOAD   /**< DHD Offload Acceleration type */
+} rdpa_wl_accel_t;
+
+/** CPU ring type */
+typedef enum {
+	rdpa_ring_data = 0,		 /**< Data ring */
+	rdpa_ring_recycle = 1,	  /**< Recycle ring */
+	rdpa_ring_feed = 2,		 /**< Feed ring */
+	rdpa_ring_cpu_tx = 3,	   /**< Cpu tx PD ring */
+} rdpa_ring_type_t;
+
+typedef enum {
+	rdpa_proto_filter_ipv4,
+	rdpa_proto_filter_ipv6,
+	rdpa_proto_filter_pppoe,
+	rdpa_proto_filter_non_ip,
+	rdpa_proto_filter_any,
+	rdpa_proto_filter_last = rdpa_proto_filter_any,
+} rdpa_proto_filter_t;
+
+/** Protocol Filters mask, defines allowed protocols */
+typedef enum {
+	rdpa_proto_filter_ipv4_mask = (1 << rdpa_proto_filter_ipv4),	 /**< Allow IPv4 traffic */
+	rdpa_proto_filter_ipv6_mask = (1 << rdpa_proto_filter_ipv6),	 /**< Allow IPv6 traffic */
+	rdpa_proto_filter_pppoe_mask = (1 << rdpa_proto_filter_pppoe),   /**< Allow PPPoE traffic */ 
+	rdpa_proto_filter_non_ip_mask = (1 << rdpa_proto_filter_non_ip), /**< Allow Non-IP traffic */
+	rdpa_proto_filter_any_mask = (1 << rdpa_proto_filter_any),	   /**< Allow any traffic */
+} rdpa_proto_filter_fields;
+
+typedef uint32_t rdpa_proto_filters_mask_t; /**< Mask of \ref rdpa_proto_filter_fields (enabled protocols) */
+
+/** @} end of types Doxygen group */
+
+typedef struct
+{
+	int src;
+	int dest;
+} int2int_map_t;
+
+static inline int int2int_map(int2int_map_t *map, int src, int last)
+{
+	for (; map->src != last && map->src != src; map++)
+		;
+	return map->dest;
+}
+
+static inline int int2int_map_r(int2int_map_t *map, int src, int last)
+{
+	for (; map->src != last && map->dest != src; map++)
+		;
+	return map->src;
+}
+
+typedef enum
+{
+	RDPA_FLOW_UNKNOWN,
+	RDPA_FLOW_TUPLE_L3,
+	RDPA_FLOW_TUPLE_L2,
+	RDPA_FLOW_MC,
+} rdpa_flow_t;
+
+#endif /* _RDPA_TYPES_H_ */
+
diff --git a/arch/arm/mach-bcmbca/xrdp/ru.c b/arch/arm/mach-bcmbca/xrdp/ru.c
new file mode 100644
index 0000000000..11dfb6fc27
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/ru.c
@@ -0,0 +1,394 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2014 Broadcom
+   All Rights Reserved
+
+    
+*/
+/**
+ * \brief Register Utilities functional implementation
+ */
+#include <common.h>
+#include "ru.h"
+#include "ru_config.h"
+
+
+void *memset_write32(void *block, int c, uint32_t size)
+{
+	return memset(block, c, size);
+}
+
+extern const ru_block_rec *RU_ALL_BLOCKS[];
+
+/******************************************************************************
+ * Find by name utilities
+ ******************************************************************************/
+const ru_block_rec *ru_block_name_find(const char *name)
+{
+	int blk_idx = 0;
+	const ru_block_rec *blk = RU_ALL_BLOCKS[blk_idx];
+
+	while (blk) {
+		if (strcmp(blk->name, name) == 0)
+			break;
+		blk = RU_ALL_BLOCKS[++blk_idx];
+	}
+	return blk;
+}
+
+
+const ru_reg_rec *ru_reg_name_find(ru_block_inst blk_inst,
+				   const ru_block_rec *block,
+				   const char *name)
+{
+	int i;
+	const ru_reg_rec *reg = NULL;
+
+	for (i = 0; i < block->reg_count; i++) {
+		if (strcmp(block->regs[i]->name, name) == 0) {
+			reg = block->regs[i];
+			break;
+		}
+	}
+	return reg;
+}
+
+#if RU_INCLUDE_FIELD_DB
+const ru_field_rec *ru_field_name_find(const ru_reg_rec *reg, const char *name)
+{
+	int i;
+	const ru_field_rec *fld = NULL;
+
+	for (i = 0; i < reg->field_count; i++) {
+		if (strcmp(reg->fields[i]->name, name) == 0) {
+			fld = reg->fields[i];
+			break;
+		}
+	}
+	return fld;
+}
+#endif
+
+
+/******************************************************************************
+ * Find by register address
+ ******************************************************************************/
+int ru_block_addr_find(uint32_t addr,
+	 	       ru_block_inst *blk_inst,
+		       const ru_block_rec **block)
+{
+	int rc = -1;
+	ru_block_inst blk_idx = 0;
+	const ru_block_rec *blk = RU_ALL_BLOCKS[blk_idx];
+	uint32_t reg_idx;
+
+	while (blk) {
+		for (*blk_inst = 0; *blk_inst < blk->addr_count; (*blk_inst)++) {
+			for (reg_idx = 0; reg_idx < blk->reg_count; reg_idx++) {
+				if ((blk->regs[reg_idx]->addr +
+				     blk->addr[*blk_inst]) == addr) {
+					*block = blk;
+					return 0;
+				}
+			}
+		}
+		blk = RU_ALL_BLOCKS[++blk_idx];
+	}
+
+	return rc;
+}
+
+
+int ru_reg_addr_find(uint32_t addr, ru_block_inst *blk_inst,
+		     const ru_block_rec **block,
+		     const ru_reg_rec **reg)
+{
+	int rc = -1;
+	ru_block_inst blk_idx = 0;
+	const ru_block_rec *blk = RU_ALL_BLOCKS[blk_idx];
+	uint32_t reg_idx;
+
+	while (blk) {
+		for (*blk_inst = 0; *blk_inst < blk->addr_count; (*blk_inst)++) {
+			for (reg_idx = 0; reg_idx < blk->reg_count; reg_idx++) {
+				if ((blk->regs[reg_idx]->addr +
+				     blk->addr[*blk_inst]) == addr) {
+					*block = blk;
+					*reg = blk->regs[reg_idx];
+					return 0;
+				}
+			}
+		}
+		blk = RU_ALL_BLOCKS[++blk_idx];
+	}
+
+	return rc;
+}
+
+
+/******************************************************************************
+ * Print parsed register value
+ ******************************************************************************/
+int ru_reg_print(ru_block_inst blk_inst,
+				 const ru_block_rec *block,
+				 const ru_reg_rec *reg,
+				 uint32_t value)
+{
+#if RU_INCLUDE_FIELD_DB
+	int i;
+#endif
+
+	RU_PRINT("%s.%s[%d]@0x%lX+%lX: 0x%08X\n", block->name, reg->name,
+		 blk_inst, block->addr[blk_inst], reg->addr, value);
+
+#if RU_INCLUDE_FIELD_DB
+	for (i = 0; i < reg->field_count; i++) {
+		RU_PRINT("\t%s[%d:%d]: 0x%X\n", reg->fields[i]->name,
+			 reg->fields[i]->shift + reg->fields[i]->bits - 1,
+			 reg->fields[i]->shift,
+			 ru_field_get(blk_inst, block, reg, reg->fields[i],
+				      value));
+	}
+#endif
+	return 0;
+}
+
+
+int ru_reg_addr_print(uint32_t addr, uint32_t value)
+{
+	ru_block_inst blk_inst;
+	const ru_block_rec *block;
+	const ru_reg_rec *reg;
+	int rc;
+
+	if (!(rc = ru_reg_addr_find(addr, &blk_inst, &block, &reg)))
+		ru_reg_print(blk_inst, block, reg, value);
+
+	return rc;
+}
+
+
+int ru_reg_name_print(ru_block_inst blk_inst, const char *bname,
+		      const char *rname, uint32_t value)
+{
+	const ru_block_rec *block;
+	const ru_reg_rec *reg;
+	int rc = -1;
+
+	block = ru_block_name_find(bname);
+	if (block) {
+		reg = ru_reg_name_find(blk_inst, block, rname);
+		if (reg)
+			rc = ru_reg_print(blk_inst, block, reg, value);
+	}
+
+	return rc;
+}
+
+#if RU_FIELD_CHECK_ENABLE
+static uint8_t ru_field_check_enable;
+#endif
+
+#if RU_OFFLINE_TEST
+static uint32_t ru_reg_space[RU_REG_COUNT];
+static uint32_t **ru_mem_reg_space[RU_BLK_COUNT];
+#endif
+
+void ru_field_bounds_check_enable(int enable)
+{
+#if RU_FIELD_CHECK_ENABLE
+	ru_field_check_enable = enable;
+#endif /* RU_FIELD_CHECK_ENABLE */
+}
+
+
+/******************************************************************************
+ * Register access functions
+ ******************************************************************************/
+
+
+#if !RU_EXTERNAL_REGISTER_ADDRESSING
+int __ru_reg_write(const char *func, const int line, ru_block_inst blk_inst,
+		   const ru_block_rec *blk, const ru_reg_rec *reg, uint32_t val)
+{
+	RU_DBG("RU_REG_WRITE from %s:%d, block:%s, reg:%s, val:%x\n", func,
+	       line, blk->name, reg->name, val);
+#if RU_OFFLINE_TEST
+	ru_reg_space[reg->log_idx] = val;
+#else
+	WRITE_32(blk->addr[blk_inst] + reg->addr, val);
+#endif /* RU_OFFLINE_TEST */
+	return 0;
+}
+#endif /* !RU_EXTERNAL_REGISTER_ADDRESSING */
+
+
+#if !RU_EXTERNAL_REGISTER_ADDRESSING
+uint32_t __ru_reg_read(const char *func, const int line, ru_block_inst blk_inst,
+		       const ru_block_rec *blk, const ru_reg_rec *reg)
+{
+#if RU_OFFLINE_TEST
+	return ru_reg_space[reg->log_idx];
+#else
+	uint32_t rv;
+	
+	READ_32(blk->addr[blk_inst] + reg->addr, rv);
+
+	RU_DBG("RU_REG_READ from %s:%d, block:%s\n", func, line, blk->name);
+	return rv;
+#endif /* RU_OFFLINE_TEST */
+}
+#endif /* !RU_EXTERNAL_REGISTER_ADDRESSING */
+
+#if RU_OFFLINE_TEST
+int ru_block_idx_find(const char *name)
+{
+	int blk_idx = 0;
+	const ru_block_rec *blk = RU_ALL_BLOCKS[blk_idx];
+
+	while (blk) {
+		if (strcmp(blk->name, name) == 0)
+			break;
+		blk = RU_ALL_BLOCKS[++blk_idx];
+	}
+	return blk_idx;
+}
+
+int ru_reg_idx_find(const ru_block_rec *blk, const char *name)
+{
+	int i;
+
+	for (i = 0; i < blk->reg_count; i++) {
+		if (strcmp(blk->regs[i]->name, name) == 0)
+			break;
+	}
+	return i;
+}
+
+uint32_t *ru_reg_mem_area(const ru_block_rec *blk, const ru_reg_rec *reg)
+{
+	int blk_idx = ru_block_idx_find(blk->name);
+	int reg_idx = ru_reg_idx_find(blk, reg->name);
+	/* Per-register pointer array */
+	uint32_t **blk_reg_areas = ru_mem_reg_space[blk_idx];
+
+	if (!blk_reg_areas[reg_idx]) {
+		printf("%s: %s.%s No ram. blk_idx=%d reg_idx=%d\n",
+			__FUNCTION__, blk->name, reg->name, blk_idx, reg_idx);
+	}
+	return blk_reg_areas[reg_idx];
+}
+#endif
+
+#if !RU_EXTERNAL_REGISTER_ADDRESSING
+int __ru_reg_ram_write(const char *func, const int line, ru_block_inst blk_inst,
+		       ru_ram_addr ram_addr, const ru_block_rec *blk,
+		       const ru_reg_rec *reg, uint32_t val)
+{
+#if RU_OFFLINE_TEST
+	uint32_t *mem_area = ru_reg_mem_area(blk, reg);
+#endif
+
+	RU_DBG("RU_REG_RAM_WRITE from %s:%d, block:%s\n", func, line, blk->name);
+	printf("RU_REG_RAM_WRITE from %s:%d, block:%s\n", func, line, blk->name);
+
+#if RU_OFFLINE_TEST
+	if (mem_area)
+		mem_area[reg->ram_count*blk_inst + ram_addr] = val;
+	else
+		printf("%s->%s: can't write %s.%s. No ram\n", func,
+		       __FUNCTION__, blk->name, reg->name);
+#else
+	WRITE_32(blk->addr[blk_inst] + reg->addr + (reg->offset * ram_addr), val);
+			
+	printf("%s:%d:writing to addr 0x%08x\n", __func__, __LINE__,
+	       reg->addr + (reg->offset * ram_addr));
+#endif /* RU_OFFLINE_TEST */
+	return 0;
+}
+#endif /* !RU_EXTERNAL_REGISTER_ADDRESSING */
+
+
+#if !RU_EXTERNAL_REGISTER_ADDRESSING
+uint32_t __ru_reg_ram_read(const char *func, const int line,
+			   ru_block_inst blk_inst, ru_ram_addr ram_addr,
+			   const ru_block_rec *blk, const ru_reg_rec *reg)
+{
+	uint32_t rv;
+#if RU_OFFLINE_TEST
+	uint32_t *mem_area = ru_reg_mem_area(blk, reg);
+	if (mem_area)
+		rv = mem_area[reg->ram_count*blk_inst + ram_addr];
+	else {
+		printf("%s->%s: can't read %s.%s. No ram\n", func, __func__,
+		       blk->name, reg->name);
+		rv = 0;
+	}
+#else
+	READ_32(blk->addr[blk_inst] + reg->addr + (reg->offset * ram_addr), rv);
+
+	RU_DBG("RU_REG_RAM_READ from %s:%d, block:%s\n", func, line, blk->name);
+#endif /* RU_OFFLINE_TEST */
+	return rv;
+}
+#endif /* !RU_EXTERNAL_REGISTER_ADDRESSING */
+
+
+uint32_t __ru_field_set(const char *func, const int line,
+			ru_block_inst blk_inst, const ru_block_rec *blk,
+			const ru_reg_rec *reg, const ru_field_rec *fld,
+			uint32_t reg_val, uint32_t fld_val)
+{
+#if RU_FIELD_CHECK_ENABLE
+	if (ru_field_check_enable) {
+		if (fld_val > (fld->mask >> fld->shift)) {
+			RU_ASSERT();
+			RU_PRINT("ASSERT: Field value out of range. Max %u, "
+				 "attempted %u\n", (fld->mask >> fld->shift),
+				 fld_val);
+			RU_PRINT("  In field: %s.%s.%s\n", blk->name, reg->name,
+				 fld->name);
+			return reg_val;
+		}
+	}
+#endif /* RU_FIELD_CHECK_ENABLE */
+	RU_DBG("RU_FIELD_SET from %s:%d, field:%s, reg_val:%x, field_val:%x\n",
+	       func, line, fld->name, reg_val, fld_val);
+
+	return FIELD_SET_(reg_val, fld->mask, fld->shift, fld_val);
+}
+
+
+uint32_t __ru_field_get(const char *func, const int line,
+			ru_block_inst blk_inst, const ru_block_rec *blk,
+			const ru_reg_rec *reg, const ru_field_rec *fld,
+			uint32_t reg_val)
+{
+	RU_DBG("RU_FIELD_GET from %s:%d, field:%s\n", func, line, fld->name);
+	return FIELD_GET_(reg_val, fld->mask, fld->shift);
+}
+
+
+void __ru_field_write(const char *func, const int line,	ru_block_inst blk_inst,
+		      const ru_block_rec *blk, const ru_reg_rec *reg,
+		      const ru_field_rec *fld, uint32_t fld_val)
+{
+	uint32_t rv;
+
+	rv = __ru_reg_read(func, line, blk_inst, blk, reg);
+	rv = __ru_field_set(func, line, blk_inst, blk, reg, fld, rv, fld_val);
+	__ru_reg_write(func, line, blk_inst, blk, reg, rv);
+}
+
+
+uint32_t __ru_field_read(const char *func, const int line,
+			 ru_block_inst blk_inst, const ru_block_rec *blk,
+			 const ru_reg_rec *reg, const ru_field_rec *fld)
+{
+	uint32_t rv;
+
+	rv = __ru_reg_read(func, line, blk_inst, blk, reg);
+	return __ru_field_get(func, line, blk_inst, blk, reg, fld, rv);
+}
+
+/* End of file ru.c */
diff --git a/arch/arm/mach-bcmbca/xrdp/ru.h b/arch/arm/mach-bcmbca/xrdp/ru.h
new file mode 100644
index 0000000000..bdab67e84a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/ru.h
@@ -0,0 +1,496 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+
+*/
+#ifndef _RU_H_
+#define _RU_H_
+/**
+ * \brief Register tracking utilities
+ *
+ * The register track module provides functionality to comprehensively debug
+ * register level transactions.  It is a slow interface that should be used in
+ * parallel to standard direct read/write transactions.  The module can parse
+ * registers into easy read field format.  Registers may be looked up by name
+ * or address.
+ *
+ */
+
+#include <linux/types.h>
+#include "ru_config.h"
+#include "ru_types.h"
+#include "ru_chip.h"
+
+#include "access_macros.h"
+void *memset_write32 (void *block, int c, uint32_t size);
+
+/******************************************************************************
+ * Find by name utilities
+ ******************************************************************************/
+
+#define FIELD_SET_(reg,mask,shift,fld) (((reg) & ~(mask)) | ((fld) << (shift)))
+#define FIELD_GET_(reg,mask,shift) (((reg) & (mask)) >> (shift))
+
+
+/**
+ * \brief Get block info by name
+ *
+ * This function fetches a block info structure by the name of the block.  The
+ * block name should be in the exact format of the register specification.  If
+ * no block is found matching the given name NULL is returned.
+ *
+ * \param name Block to look up
+ *
+ * \return
+ * Block info structure if found, NULL if block does not exist
+ */
+extern
+const ru_block_rec *ru_block_name_find(const char *name);
+
+
+/**
+ * \brief Get register info by name
+ *
+ * This function fetches a register info structure given the info of the block
+ * and the register name.  Names must exactly match the register specification,
+ * the register name should not have the block name prepended.  If no matching
+ * register is found for the supplied block NULL is returned.
+ *
+ * \param blk_inst Block instance
+ * \param block Block to search
+ * \param name Register name to lookup
+ *
+ * \return
+ * Register info structure if found, NULL if register does not exist
+ */
+extern
+const ru_reg_rec *ru_reg_name_find(ru_block_inst blk_inst,
+				   const ru_block_rec *block,
+				   const char *name);
+
+
+/**
+ * \brief Get field info by name
+ *
+ * This function fetches a field info structure given the info of the register
+ * and the name of the field.  The name should exactly match the register
+ * specification, without block or register name prepended.  If no matching
+ * field is found for the supplied register NULL is returned.
+ *
+ * \param reg Register to search
+ * \param name Field name to lookup
+ *
+ * \return
+ * Field info structure if found, NULL if field does not exist
+ */
+extern
+const ru_field_rec *ru_field_name_find(const ru_reg_rec *reg, const char *name);
+
+
+/******************************************************************************
+ * Find by register address
+ ******************************************************************************/
+
+/**
+ * \brief Get a block info by address
+ *
+ * This function fetches a block record by address.  The address may be anywhere
+ * within the register space of the block.  If found the block record is
+ * assigned to the supplied container.
+ *
+ * \param[in] addr Address to lookup
+ * \param[out] blk_inst Container for found instance number
+ * \param[out] block Container for found block
+ *
+ * \return
+ * 0 if successful, -1 if failed
+ */
+extern
+int ru_block_addr_find(uint32_t addr,
+		       ru_block_inst *blk_inst,
+		       const ru_block_rec **block);
+
+
+/**
+ * \brief Get block and register info by address
+ *
+ * This function fetches a block and register record by address.  The found
+ * records are assigned to the supplied container.
+ *
+ * \param[in] addr Address to lookup
+ * \param[out] blk_inst Container for found instance number
+ * \param[out] block Container for found block
+ * \param[out] reg Container for foudn register
+ *
+ * \return
+ * 0 if successful, -1 if failed
+ */
+extern
+int ru_reg_addr_find(uint32_t addr,
+		     ru_block_inst *blk_inst,
+		     const ru_block_rec **block,
+		     const ru_reg_rec **reg);
+
+
+/******************************************************************************
+ * Print parsed register value
+ ******************************************************************************/
+
+/**
+ * \brief Parse and print a register from records
+ *
+ * This function parses a register into its individual fields and prints the
+ * formatted output to stdout.  The function is supplied the block and register
+ * info records for the register to print.
+ *
+ * \param blk_inst Block instance number
+ * \param block Block for regsiter
+ * \param reg Register to print
+ * \param value Register value
+ *
+ * \return
+ * 0 if successful, -1 if failed
+ */
+extern
+int ru_reg_print(ru_block_inst blk_inst,
+		 const ru_block_rec *block,
+		 const ru_reg_rec *reg,
+		 uint32_t value);
+
+
+/**
+ * \brief Parse and print a register from address
+ *
+ * This function parses a register into its individual fields and prints the
+ * formatted output to stdout.  The function is supplied the address of the
+ * register to print.
+ *
+ * \param addr Register address
+ * \param value Register value
+ *
+ * \return
+ * 0 if successful, -1 if failed
+ */
+extern
+int ru_reg_addr_print(uint32_t addr, uint32_t value);
+
+
+/**
+ * \brief Parse and print a register from names
+ *
+ * This function parses a register into its individual fields and prints the
+ * formatted output to stdout.  The function is supplied the names of the block
+ * and register to print.
+ *
+ * \param blk_inst Block instance number
+ * \param bname Name of block
+ * \param rname Name of register
+ * \param value Register value
+ *
+ * \return
+ * 0 if successful, -1 if failed
+ */
+extern
+int ru_reg_name_print(ru_block_inst blk_inst,
+		      const char *bname,
+		      const char *rname,
+		      uint32_t value);
+
+
+/******************************************************************************
+ * Register logging and debugging functions
+ ******************************************************************************/
+/**
+ * \brief Enable or disable field bounds checking
+ *
+ * This function enables or disables the field bounds check down when a register
+ * field is set.  The checking will still be compiled in but simply bypassed.
+ * To fully bypass bounds checking disable RU_FIELD_CHECK_ENABLE.
+ *
+ * \param enable Enable or disable bounds checking
+ *
+ * \return
+ * None
+ */
+extern
+void ru_field_bounds_check_enable(int enable);
+
+
+/******************************************************************************
+ * Register access functions
+ ******************************************************************************/
+
+/**
+ * \brief Write a register
+ *
+ * This function writes a value to a register.  If debugging is enabled the
+ * written value may be logged.
+ *
+ * \param blk_inst Block instance number
+ * \param blk Register block record
+ * \param reg Register record
+ * \param val Value to write
+ *
+ * \return
+ * 0 if successful
+ */
+extern
+int __ru_reg_write(const char *func, const int line,
+		   ru_block_inst blk_inst,
+		   const ru_block_rec *blk,
+		   const ru_reg_rec *reg,
+		   uint32_t val);
+#define ru_reg_write(blk_inst, blk, reg, val) \
+	__ru_reg_write(__FUNCTION__, __LINE__, blk_inst, blk, reg, val)
+#if !RU_FUNCTION_REG_ACCESS
+#define RU_REG_WRITE(i, b, r, v) \
+	WRITE_32(RU_BLK(b).addr[i] + RU_REG_OFFSET(b, r), v)
+#else
+#define RU_REG_WRITE(i, b, r, v) ru_reg_write(i, &RU_BLK(b), &RU_REG(b, r), v)
+#endif
+
+
+/**
+ * \brief Read a register
+ *
+ * This function reads a register.  If debugging is enabled the value read may
+ * be logged.
+ *
+ * \param blk_inst Block instance number
+ * \param blk Register block record
+ * \param reg Register record
+ * \param val Read back register value
+ *
+ * \return
+ * 0 if successful
+ */
+extern
+uint32_t __ru_reg_read(const char *func, const int line,
+		       ru_block_inst blk_inst,
+		       const ru_block_rec *blk,
+		       const ru_reg_rec *reg);
+#define ru_reg_read(blk_inst, blk, reg) \
+	__ru_reg_read(__FUNCTION__, __LINE__, blk_inst, blk, reg)
+#if !RU_FUNCTION_REG_ACCESS
+#define RU_REG_READ(i, b, r, reg) \
+	READ_32(RU_BLK(b).addr[i] + RU_REG_OFFSET(b, r), reg)
+#else
+#define RU_REG_READ(i, b, r, reg) \
+	((reg) = ru_reg_read(i, &RU_BLK(b), &RU_REG(b, r)))
+#endif
+
+
+/**
+ * \brief Write a RAM mapped register
+ *
+ * This function writes a instace of a RAM mapped register (i.e. a RAM that is
+ * an indexable table of identical registers).  If debugging is enabled the
+ * value written value may be logged.
+ *
+ * \param blk_inst Block instance number
+ * \param ram_addr RAM address, aligned to the size of the register
+ * \param blk Register block record
+ * \param reg Register record
+ * \param val Value to write
+ *
+ * \return
+ * 0 if successful
+ */
+extern
+int __ru_reg_ram_write(const char *func, const int line,
+		       ru_block_inst blk_inst,
+		       ru_ram_addr ram_addr,
+		       const ru_block_rec *blk,
+		       const ru_reg_rec *reg,
+		       uint32_t val);
+#define ru_reg_ram_write(blk_inst, ram_addr, blk, reg, val) \
+	__ru_reg_ram_write(__func__, __LINE__, blk_inst, ram_addr, blk, reg, val)
+#if !RU_FUNCTION_REG_ACCESS
+#define RU_REG_RAM_WRITE(i, a, b, r, v) \
+	WRITE_32(RU_BLK(b).addr[i] + RU_REG_OFFSET(b,r) + \
+		 (RU_REG(b, r).offset*(a)), v)
+#else
+#define RU_REG_RAM_WRITE(i, a, b, r, v) \
+	ru_reg_ram_write(i, a, &RU_BLK(b), &RU_REG(b, r), v)
+#endif
+
+
+/**
+ * \brief Read a RAM mapped register
+ *
+ * This function reads a instace of a RAM mapped register (i.e. a RAM that is an
+ * indexable table of identical registers).  If debugging is enabled the value
+ * read may be logged.
+ *
+ * \param blk_inst Block instance number
+ * \param ram_addr RAM address, aligned to the size of the register
+ * \param blk Register block record
+ * \param reg Register record
+ * \param val Read back register value
+ *
+ * \return
+ * 0 if successful
+ */
+extern
+uint32_t __ru_reg_ram_read(const char *func, const int line,
+			   ru_block_inst blk_inst,
+			   ru_ram_addr ram_addr,
+			   const ru_block_rec *blk,
+			   const ru_reg_rec *reg);
+#define ru_reg_ram_read(blk_inst, ram_addr, blk, reg) \
+	__ru_reg_ram_read(__FUNCTION__, __LINE__, blk_inst, ram_addr, blk, reg)
+#if !RU_FUNCTION_REG_ACCESS
+#define RU_REG_RAM_READ(i, a, b, r, var) \
+	READ_32(RU_BLK(b).addr[i] + RU_REG_OFFSET(b,r) + \
+		(RU_REG(b, r).offset*(a)), var)
+#else
+#define RU_REG_RAM_READ(i, a, b, r, var) \
+	((var) = ru_reg_ram_read(i, a, &RU_BLK(b), &RU_REG(b, r)))
+#endif
+
+
+/**
+ * \brief Set a register field
+ *
+ * This function sets a field in a register.  The value if applied to the
+ * supplied old register value and returned.  If debbuging is enabled an
+ * assertion will be raised if the field is out of range with range being
+ * determined by the width of the field. If the field is out of range it will
+ * not be set and the original old value will be returned.
+ *
+ * \param blk_inst Block instance number
+ * \param blk Register block record
+ * \param reg Register record
+ * \param fld Register field record
+ * \param reg_val Old register value to write in to
+ * \param fld_val Field value to write
+ *
+ * \return
+ * val with new field value applied
+ */
+extern
+uint32_t __ru_field_set(const char *func, const int line,
+			ru_block_inst blk_inst,
+			const ru_block_rec *blk,
+			const ru_reg_rec *reg,
+			const ru_field_rec *fld,
+			uint32_t reg_val,
+			uint32_t fld_val);
+#define ru_field_set(blk_inst, blk, reg, fld, reg_val, fld_val) \
+	__ru_field_set(__func__, __LINE__, blk_inst, blk, reg, \
+		       fld, reg_val, fld_val)
+#if !RU_FUNCTION_REG_ACCESS
+#define RU_FIELD_SET(i, b, r, f, rv, fv) \
+	(((rv) & ~RU_FLD_MASK(b, r, f)) | (fv << RU_FLD_SHIFT(b, r, f)))
+#else
+#define RU_FIELD_SET(i, b, r, f, rv, fv) \
+	ru_field_set(i, &RU_BLK(b), &RU_REG(b, r), &RU_FLD(b, r, f), rv, fv)
+#endif
+
+
+/**
+ * \brief Get a register field
+ *
+ * This function gets a field in a register.  The value returned is justified to
+ * bit [0]. This function does not support any debug features.
+ *
+ * \param blk_inst Block instance number
+ * \param blk Register block record
+ * \param reg Register record
+ * \param fld Register field record
+ * \param reg_val Old register value to read from
+ *
+ * \return
+ * Bit [0] justified field value
+ */
+extern
+uint32_t __ru_field_get(const char *func, const int line,
+			ru_block_inst blk_inst,
+			const ru_block_rec *blk,
+			const ru_reg_rec *reg,
+			const ru_field_rec *fld,
+			uint32_t reg_val);
+#define ru_field_get(blk_inst, blk, reg, fld, reg_val) \
+	__ru_field_get(__FUNCTION__, __LINE__, blk_inst, blk, reg, fld, reg_val)
+#if !RU_FUNCTION_REG_ACCESS
+#define RU_FIELD_GET(i, b, r, f, rv) \
+	(((rv) & RU_FLD_MASK(b, r, f)) >> RU_FLD_SHIFT(b, r, f))
+#else
+#define RU_FIELD_GET(i, b, r, f, rv) \
+		ru_field_get(i, &RU_BLK(b), &RU_REG(b, r), &RU_FLD(b, r, f), rv)
+#endif
+
+
+/**
+ * \brief Write a field in a register
+ *
+ * This function performs a read modify write action on a given register setting
+ * the desired field in the process. The same logging and field checking applies
+ * as ru_reg_write, ru_reg_read, and ru_field_set.  This function should be used
+ * when it is desirable to only write a single field in a register.
+ *
+ * \param blk_inst Block instance number
+ * \param blk Register block record
+ * \param reg Register record
+ * \param fld Register field record
+ * \param fld_val Field value to write
+ *
+ * \return
+ * None
+ */
+extern
+void __ru_field_write(const char *func, const int line,
+		      ru_block_inst blk_inst,
+		      const ru_block_rec *blk,
+		      const ru_reg_rec *reg,
+		      const ru_field_rec *fld,
+		      uint32_t fld_val);
+#define ru_field_write(blk_inst, blk, reg, fld, fld_val) \
+	__ru_field_write(__func__, __LINE__, blk_inst, blk, reg, fld, fld_val)
+#if !RU_FUNCTION_REG_ACCESS
+#define RU_FIELD_WRITE(i, b, r, f, fv) \
+	do { \
+		uint32_t rv; \
+		rv = RU_REG_READ(i, b, r); \
+		rv = RU_FIELD_SET(i, b, r, f, rv, fv); \
+		RU_REG_WRITE(i, b, r, v); \
+	} while (0)
+#else
+#define RU_FIELD_WRITE(i, b, r, f,fv) \
+	ru_field_write(i, &RU_BLK(b), &RU_REG(b, r), &RU_FLD(b, r, f), fv)
+#endif
+
+
+/**
+ * \brief Read a field from a register
+ *
+ * This function reads a register and returns a given field.  The same logging
+ * as ru_reg_read applies.  This function should be called when on a single
+ * field is required from a register.
+ *
+ * \param blk_inst Block instance number
+ * \param blk Register block record
+ * \param reg Register record
+ * \param fld Register field record
+ *
+ * \return
+ * Bit [0] justified field value
+ */
+extern
+uint32_t __ru_field_read(const char *func, const int line,
+			 ru_block_inst blk_inst,
+			 const ru_block_rec *blk,
+			 const ru_reg_rec *reg,
+			 const ru_field_rec *fld);
+#define ru_field_read(blk_inst, blk, reg, fld) \
+	__ru_field_read(__FUNCTION__, __LINE__, blk_inst, blk, reg, fld)
+#if !RU_FUNCTION_REG_ACCESS
+#define RU_FIELD_READ(i, b, r, f) RU_FIELD_GET(i, b, r, f, RU_REG_READ(i, b, r))
+#else
+#define RU_FIELD_READ(i, b, r, f) \
+	ru_field_read(i, &RU_BLK(b), &RU_REG(b, r), &RU_FLD(b, r, f))
+#endif
+
+#endif /* End of file _RU_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/ru_config.h b/arch/arm/mach-bcmbca/xrdp/ru_config.h
new file mode 100644
index 0000000000..aa0549c63d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/ru_config.h
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+
+*/
+/**
+ * \brief Register Utility configuration and common includes
+ */
+#ifndef _RU_CONFIG_H_
+#define _RU_CONFIG_H_
+
+#ifndef RU_USE_STDC
+#define RU_USE_STDC 0
+#endif
+
+#if RU_USE_STDC
+/* These include files are required by the library */
+#include <stdlib.h>
+#include <linux/types.h>
+#include <string.h>
+#endif
+
+/******************************************************************************
+ * Optimizations
+ ******************************************************************************/
+
+/* Register access bypasses function interface and error checking instead
+   generating register accesses as inline memory dereference. This must be used 
+   with RU_EXTERNAL_REGISTER_ADDRESSING and RU_OFFLINE_TEST disabled. */
+#ifndef RU_FUNCTION_REG_ACCESS
+#define RU_FUNCTION_REG_ACCESS 0
+#endif
+
+#ifndef RU_FUNCTION_REG_ACCESS_DBG
+#define RU_FUNCTION_REG_ACCESS_DBG 0
+#endif
+
+/* Remove field bounds checking from RU_FIELD_SET.  This may be disabled once
+   software has stabilized and bounds checking begins to hurt performance. */
+#ifndef RU_FIELD_CHECK_ENABLE
+#define RU_FIELD_CHECK_ENABLE 1
+#endif
+
+/* Include title and description strings from RBD.  Note, this will take up a
+   very large amount of RAM on bigger systems. */ 
+#ifndef RU_INCLUDE_DESC
+#define RU_INCLUDE_DESC RU_FUNCTION_REG_ACCESS
+#endif
+
+/* Include field defitions in the register database */
+#ifndef RU_INCLUDE_FIELD_DB
+#define RU_INCLUDE_FIELD_DB RU_FUNCTION_REG_ACCESS
+#endif
+
+/* Include read/write access field in database */
+#ifndef RU_INCLUDE_ACCESS
+#define RU_INCLUDE_ACCESS RU_FUNCTION_REG_ACCESS
+#endif
+
+/******************************************************************************
+ * Logging
+ ******************************************************************************/
+
+/* Number of register accesses in the register logging ring buffer */
+#ifndef RU_LOG_SIZE
+#define RU_LOG_SIZE 65536
+#endif
+
+/* Number of unique logging rules that may be used at any time */
+#ifndef RU_RULE_POOL_SIZE
+#define RU_RULE_POOL_SIZE 256
+#endif
+
+/******************************************************************************
+ * Print and error
+ ******************************************************************************/
+
+/* Optional assert function to call when field bounds checking fails or logging
+   rule allocation fails.  Print function will also be called when this 
+   occurs. */
+#define RU_ASSERT()
+
+/* Print function to use for register logging output. */
+#if RU_USE_STDC
+#define RU_PRINT(...) printf(__VA_ARGS__)
+#elif !defined(NO_BDMF_HANDLE)
+#define RU_PRINT(...) do { } while (0)
+#endif
+
+#if RU_FUNCTION_REG_ACCESS_DBG
+#define RU_DBG RU_PRINT
+#else
+#define RU_DBG(...) do { } while (0)
+#endif
+
+/******************************************************************************
+ * Test and miscellaneous
+ ******************************************************************************/
+
+/* Registers are directly accessed as pointers to RAM using base and offset
+   calculations from the block and register records.  If register access is 
+   redirected over another bus set this to 0 and implement new versions of
+   ru_reg_write and ru_reg_read. */
+#ifndef RU_EXTERNAL_REGISTER_ADDRESSING
+#define RU_EXTERNAL_REGISTER_ADDRESSING 0
+#endif
+
+/* Register access is redirected to an internal buffer for testing functions
+   when hardware access is not available. It is only meaningful if 
+   RU_DIRECT_REGISTER_ADDRESSING is enabled. */
+#ifndef RU_OFFLINE_TEST
+#define RU_OFFLINE_TEST 0
+#endif
+
+/* Set this to 1 to include a stub main function for simple compile checks */
+#ifndef RU_TEST_COMPILE_STUB
+#define RU_TEST_COMPILE_STUB 0
+#endif
+
+#endif /* End of file _RU_CONFIG_H_ */
+
diff --git a/arch/arm/mach-bcmbca/xrdp/ru_types.h b/arch/arm/mach-bcmbca/xrdp/ru_types.h
new file mode 100644
index 0000000000..9b63ab01c2
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/ru_types.h
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2015 Broadcom
+ */
+/*
+
+*/
+
+#ifndef _RU_TYPES_H_
+#define _RU_TYPES_H_
+/**
+ * \brief Register tracking type definitions
+ *
+ * The register track module provides functionality to comprehensively debug
+ * register level transactions.  It is a slow interface that should be used in
+ * parallel to standard direct read/write transactions.  The module can parse
+ * registers into easy read field format.  Registers may be looked up by name
+ * or address.
+ *
+ */
+#include <linux/types.h>
+#include "ru_config.h"
+
+typedef enum {
+	ru_access_read	= 0x01, /*< Read only */
+	ru_access_write	= 0x02, /*< Write only */
+	ru_access_rw	= 0x03  /*< Read/write */
+} ru_access;
+
+typedef struct {
+	const char *name;	/*< Name of field from reg spec */
+#if RU_INCLUDE_DESC
+	const char *title;	/*< Short title of the field */
+	const char *desc;	/*< Detail description */
+#endif
+	uint32_t mask;		/*< Field bit mask */
+	uint32_t align;		/*< Unknown, used by register macro */
+	uint32_t bits;		/*< Field bit width */
+	uint32_t shift;		/*< Field bit offset */
+#if RU_INCLUDE_ACCESS
+	ru_access access;	/*< Field read/write access */
+#endif
+} ru_field_rec;			/*< Field info record */
+
+typedef struct {
+	const char *name;	/*< Name of register from reg spec */
+#if RU_INCLUDE_DESC
+	const char *title;	/*< Short title of the register */
+	const char *desc;	/*< Detail description */
+#endif
+	unsigned long addr;	/*< Block relative register address */
+	uint32_t ram_count;	/*< RAM addresses, 0 for std register */
+	uint32_t offset;	/*< Offset of next index in RAM types */
+	uint32_t log_idx;	/*< Register ID for debug logging */
+#if RU_INCLUDE_ACCESS
+	ru_access access;	/*< Register read/write access */
+#endif
+#if RU_INCLUDE_FIELD_DB
+	uint32_t field_count;	/*< Number of fields, private */
+	const ru_field_rec **fields;	/*< All fields for register, private */
+#endif
+} ru_reg_rec;			/*< Register info record */
+
+typedef struct {
+	const char *name;	/*< Name of the block */
+	unsigned long *addr;	/*< Block base addresses */
+	uint8_t addr_count;	/*< Number of block instances */
+	uint32_t reg_count;	/*< Number of registers, private */
+	const ru_reg_rec **regs;	/*< All registers for block, private */
+} ru_block_rec;			/*< Info for a block instance */
+
+typedef enum
+{
+	ru_log_none	= 0x00, /*< Do not log */
+	ru_log_read	= 0x01, /*< Log read access only */
+	ru_log_write	= 0x02, /*< Log write access only */
+	ru_log_both	= 0x03  /*< Log both read and write */
+} ru_log_type;			/*< Access logging type */
+
+typedef enum {
+	ru_op_equal,		/*< (Register & Mask) == Value */
+	ru_op_not_equal,	/*< (Register & Mask) != Value */
+	ru_op_greater_than,	/*< (Register & Mask) > Value */
+	ru_op_less_than		/*< (Register & Mask) < Value */
+} ru_log_op;			/*< Logging comparator operation */
+
+#define RU_BLK(b) b##_BLOCK
+#define RU_REG(b, r) b##_##r##_REG
+#define RU_REG_OFFSET(b, r) b##_##r##_REG_OFFSET
+#define RU_REG_RAM_CNT(b, r) b##_##r##_REG_RAM_CNT
+#define RU_FLD(b, r, f) b##_##r##_##f##_FIELD
+#define RU_FLD_MASK(b, r, f) b##_##r##_##f##_FIELD_MASK
+#define RU_FLD_SHIFT(b,r,f) b##_##r##_##f##_FIELD_SHIFT
+
+typedef uint8_t ru_block_inst;	/*< Multiple block instance index */
+typedef uint32_t ru_ram_addr;	/*< Index for RAM mapped registers */
+
+#endif /* End of file _RU_TYPES_H_ */
diff --git a/arch/arm/mach-bcmbca/xrdp/xrdp_full/Makefile b/arch/arm/mach-bcmbca/xrdp/xrdp_full/Makefile
new file mode 100755
index 0000000000..914c2aed9a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/xrdp/xrdp_full/Makefile
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+CUR_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
+BLD_DIR = $(shell pwd)
+BLD_DIR :=$(subst /bootloaders/, /bootloaders/,$(BLD_DIR))$
+BLD_DIR :=$(word 1,$(BLD_DIR))
+TOP_DIR :=$(BLD_DIR)/rdp
+PROJECT_DIR := $(TOP_DIR)/projects/XRDP_CFE2
+CHIP_ID := $(patsubst "bcm%",%,$(CONFIG_SYS_SOC))
+
+KBUILD_CPPFLAGS += -DBCM$(CHIP_ID) -DXRDP_CFE -D_CFE_REDUCED_XRDP_
+KBUILD_CPPFLAGS += -include common.h -I$(BLD_DIR)/shared/opensource/include/bcm963xx
+PROJ_DRV_SRC_LIST := $(PROJECT_DIR)/BCM$(CHIP_ID)_A0_UBOOT_sources.list
+PROJ_FW_SRC_LIST := $(PROJECT_DIR)/BCM$(CHIP_ID)_A0_fw_sources.list
+
+LN = ln -sf
+RM = rm -f
+
+ifneq ($(findstring _$(strip $(CHIP_ID))_,_63146_),)
+KBUILD_CPPFLAGS += -DBCM_DSL_XRDP
+else
+KBUILD_CPPFLAGS += -DBCM_PON_XRDP
+endif
+
+ifneq ($(findstring _$(strip $(CHIP_ID))_,_6878_63146_),)
+KBUILD_CPPFLAGS += -DDUAL_ISSUE
+endif
+
+ifneq ($(findstring _$(strip $(CHIP_ID))_,_63146_),)
+KBUILD_CPPFLAGS += -DXRDP_RGEN6
+
+# temporary
+KBUILD_CPPFLAGS += -DCONFIG_BRCM_IKOS
+endif
+
+obj-y += xrdp_full.o
+
+xrdp_full-objs := XRDP_BAC_IF_AG.o XRDP_BBH_RX_AG.o
+xrdp_full-objs += XRDP_BBH_TX_AG.o XRDP_CNPL_AG.o XRDP_DMA_AG.o
+xrdp_full-objs += XRDP_DQM_AG.o XRDP_DSPTCHR_AG.o XRDP_FPM_AG.o
+xrdp_full-objs += XRDP_HASH_AG.o XRDP_NATC_AG.o XRDP_NATC_CFG_AG.o
+xrdp_full-objs += XRDP_NATC_CTRS_AG.o XRDP_NATC_DDR_CFG_AG.o XRDP_NATC_ENG_AG.o
+xrdp_full-objs += XRDP_NATC_INDIR_AG.o XRDP_QM_AG.o XRDP_RNR_CNTXT_AG.o
+xrdp_full-objs += XRDP_RNR_INST_AG.o XRDP_RNR_MEM_AG.o XRDP_RNR_PRED_AG.o
+xrdp_full-objs += XRDP_RNR_REGS_AG.o XRDP_RNR_QUAD_AG.o XRDP_TCAM_AG.o
+xrdp_full-objs += XRDP_UBUS_MSTR_AG.o XRDP_UBUS_SLV_AG.o XRDP_UNIMAC_MISC_AG.o
+xrdp_full-objs += XRDP_PSRAM_AG.o XRDP_SBPM_AG.o XRDP_UNIMAC_RDP_AG.o
+
+xrdp_full-objs += rdd_init.o rdd_runner_tasks_auto.o rdp_common.o
+xrdp_full-objs += rdd_ag_cpu_rx.o
+xrdp_full-objs += rdp_drv_bbh_rx.o rdp_drv_bbh_tx.o rdp_drv_dis_reor.o
+xrdp_full-objs += rdp_drv_dma.o rdp_drv_rnr.o rdp_drv_sbpm.o
+
+xrdp_full-objs += xrdp_drv_bac_if_ag.o xrdp_drv_bbh_rx_ag.o xrdp_drv_bbh_tx_ag.o
+xrdp_full-objs += xrdp_drv_cnpl_ag.o xrdp_drv_dma_ag.o xrdp_drv_dqm_ag.o
+xrdp_full-objs += xrdp_drv_dsptchr_ag.o xrdp_drv_unimac_misc_ag.o
+xrdp_full-objs += xrdp_drv_fpm_ag.o xrdp_drv_hash_ag.o xrdp_drv_natc_ag.o
+xrdp_full-objs += xrdp_drv_natc_ctrs_ag.o xrdp_drv_natc_ddr_cfg_ag.o
+xrdp_full-objs += xrdp_drv_natc_eng_ag.o xrdp_drv_natc_indir_ag.o
+xrdp_full-objs += xrdp_drv_qm_ag.o xrdp_drv_rnr_cntxt_ag.o
+xrdp_full-objs += xrdp_drv_rnr_inst_ag.o xrdp_drv_rnr_mem_ag.o
+xrdp_full-objs += xrdp_drv_rnr_pred_ag.o xrdp_drv_rnr_quad_ag.o
+xrdp_full-objs += xrdp_drv_rnr_regs_ag.o xrdp_drv_tcam_ag.o
+xrdp_full-objs += xrdp_drv_ubus_mstr_ag.o xrdp_drv_ubus_slv_ag.o
+xrdp_full-objs += xrdp_drv_psram_ag.o xrdp_drv_sbpm_ag.o
+xrdp_full-objs += xrdp_drv_unimac_rdp_ag.o
+
+xrdp_full-objs += fw_binary_auto.o predict_runner_fw_0.o runner_fw_0.o
+
+xrdp_full-objs += data_path_init.o
+
+
+prepare_xrdp_links:
+	@echo "got here!! prepare_xrdp_links"
+	$(foreach src,$(shell grep "\.h" $(PROJ_FW_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(src) $(CUR_DIR)))
+	$(foreach src,$(shell grep "drivers/rdd" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(src) $(CUR_DIR)))
+	$(foreach src,$(shell grep "firmware/.*\.h" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(src) $(CUR_DIR)))
+	$(foreach src,$(shell grep "firmware/.*rdd_.*\.c" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(src) $(CUR_DIR)))
+	$(foreach src,$(shell grep "drivers/rdp_subsystem" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(src) $(CUR_DIR)))
+	$(foreach src,$(shell grep "firmware_bin/" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(src) $(CUR_DIR)))
+	$(foreach src,$(shell grep "rdp_drv" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(src) $(CUR_DIR)))
+	$(foreach src,$(shell grep "drivers/bdmf" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile" | grep -v "*.c"),$(shell $(LN) $(TOP_DIR)/$(src) $(CUR_DIR)))
+	$(foreach src,$(shell grep "drivers/rdpa_gpl/include" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(src) $(CUR_DIR)))
+#	$(foreach src,$(shell ls *.[c,h]),$(shell if [[ ! -f $(src) ]]; then $(RM) $(src); fi))
+
+
+$(obj)/xrdp_full.o: prepare_xrdp_links
+
+
+# FIXME!! how to add clean. we can simply delete all the .c/.h
+clean-files += $(CUR_DIR)/*.c $(CUR_DIR)/*.h
+
diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig
new file mode 100644
index 0000000000..3beae8b4d8
--- /dev/null
+++ b/board/broadcom/bcmbca/Kconfig
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_BOARD
+	default "bcmbca"
+
+if TARGET_BCM963158
+config SYS_CONFIG_NAME
+	default "bcm963158"
+endif
+
+if TARGET_BCM96858
+config SYS_CONFIG_NAME
+	default "bcm96858"
+endif
+
+if TARGET_BCM96856
+config SYS_CONFIG_NAME
+	default "bcm96856"
+endif
+
+if TARGET_BCM963178
+config SYS_CONFIG_NAME
+	default "bcm963178"
+endif
+
+if TARGET_BCM947622
+config SYS_CONFIG_NAME
+	default "bcm947622"
+endif
+
+if TARGET_BCM96756
+config SYS_CONFIG_NAME
+	default "bcm96756"
+endif
+
+if TARGET_BCM96846
+config SYS_CONFIG_NAME
+    default "bcm96846"
+endif
+
+if TARGET_BCM96878
+config SYS_CONFIG_NAME
+    default "bcm96878"
+endif
+
+if TARGET_BCM96855
+config SYS_CONFIG_NAME
+    default "bcm96855"
+endif
+
+if TARGET_BCM94908
+config SYS_CONFIG_NAME
+	default "bcm94908"
+endif
+
+if TARGET_BCM94912
+config SYS_CONFIG_NAME
+	default "bcm94912"
+endif
+
+if TARGET_BCM963146
+config SYS_CONFIG_NAME
+	default "bcm963146"
+endif
+
+if TARGET_BCM963138
+config SYS_CONFIG_NAME
+	default "bcm963138"
+endif
+
+if TARGET_BCM963148
+config SYS_CONFIG_NAME
+	default "bcm963148"
+endif
+
+config BCMBCA_HTTPD
+	bool "Support HTTPD server"
+	depends on NET
+
+config BCMBCA_IKOS
+	bool "IKOS"
+	depends on !CONFIG_SYS_ARCH_TIMER
+	help
+	  Enable IKOS build 
+
+config BCMBCA_BOARD_SPECIFIC_DT
+	bool "Load board specific device tree for uboot"
+
+config BCMBCA_UPDATE_MCB_IN_ENV
+	bool "Auto update MCB selector in environment"
+	depends on BCMBCA_BOARD_SPECIFIC_DT
+	default y
+
+config BCMBCA_BOARD_SDK
+	bool "Support board sdk"
+	default y
+
+config BCMBCA_EARLY_ABORT_JTAG_UNLOCK
+	bool "Unlocks JTAG in early abort. Hazardous: Use in debug/development mode only"
+	help
+          JTAG unlock is a debug feature helping to unbrick board if booted to BOOTROM secure mode
+		
+#Hopefully temporary home for this driver
+#since we need this in tpl, we can't have it under misc 
+config BCM_BOOTSTATE
+	bool "Enable support for Broadcom Bootstate Driver"
+	help
+	  If you say Y here, you will get support broadcom bootstate
+	  mechanism
+
+config BCMBCA_EXTRA_BOARD_OBJECTS
+	string "Space Seperated List of Extra board/broadcom/bcmbca  objects to build"
+	help
+	  To add additional files to the uboot proper in the board/broadcom/bcmbca directory
+	  add the names of the .o files in a space-separated list
+
+config BCMBCA_BOARD_TK_PROG
+	bool "Build Turnkey Programming SPL Version"
+	default n
+
+config BCMBCA_BUTTON
+	bool "button support for broadcom board"
+	depends on DM
+	default y
diff --git a/board/broadcom/bcmbca/Makefile b/board/broadcom/bcmbca/Makefile
new file mode 100644
index 0000000000..378dfb999a
--- /dev/null
+++ b/board/broadcom/bcmbca/Makefile
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+
+# ccflags-y += -save-temps
+
+ifndef CONFIG_SPL_BUILD
+# u-boot proper
+CFLAGS_board.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"')
+obj-y += board.o
+obj-y += spl_env.o
+obj-$(CONFIG_BCMBCA_BOARD_SDK) += board_sdk.o
+obj-y += bca_common.o
+obj-$(CONFIG_BCMBCA_BOARD_SDK) += sdk_test_commands.o
+obj-$(CONFIG_BCMBCA_PMC) += pmc_commands.o
+obj-$(CONFIG_BCMBCA_HTTPD) += httpd/
+obj-$(CONFIG_BCM_BOOTSTATE) += bcm_bootstate.o 
+obj-$(CONFIG_BCMBCA_BOARD_SDK) += board_secure.o
+obj-$(CONFIG_BCMBCA_BOARD_SDK) += board_secure_sdk.o
+obj-$(CONFIG_BCMBCA_BOARD_SDK) += board_secure_utils.o
+obj-$(CONFIG_BCMBCA_BOARD_SDK) += board_secure_fit.o
+obj-$(CONFIG_BCMBCA_BOARD_SDK) += mini-gmp/
+obj-$(CONFIG_BCMBCA_BUTTON) += bcmbca_button.o reset_button.o
+obj-y += $(subst ",,$(CONFIG_BCMBCA_EXTRA_BOARD_OBJECTS))
+endif
+
+ifndef CONFIG_TPL_BUILD
+# SPL
+ifndef CONFIG_BCMBCA_BOARD_TK_PROG
+# Standard SPL
+obj-$(CONFIG_SPL_BUILD)	+= boot_blob.o
+obj-$(CONFIG_SPL_BUILD)	+= boot_flash.o
+obj-$(CONFIG_SPL_BUILD)	+= board_spl.o
+CFLAGS_board_spl.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"')
+obj-$(CONFIG_SPL_BUILD)	+= spl_env.o
+obj-$(CONFIG_SPL_BUILD)	+= early_abort.o
+obj-$(CONFIG_SPL_BUILD) += board_secure.o
+obj-$(CONFIG_SPL_BUILD) += board_secure_spl.o
+else
+# TK SPL
+ifdef CONFIG_BCMBCA_BOARD_TK_PROG
+obj-$(CONFIG_SPL_BUILD)	+= board_tk_prog.o
+obj-$(CONFIG_SPL_BUILD) += board_secure.o
+obj-$(CONFIG_SPL_BUILD) += board_secure_utils.o
+obj-$(CONFIG_SPL_BUILD) += board_secure_spl.o
+obj-$(CONFIG_SPL_BUILD) += mini-gmp/
+endif
+endif
+endif
+
+# TPL
+obj-$(CONFIG_TPL_BUILD)	+= board_tpl.o
+CFLAGS_board_tpl.o := $(if $(BUILD_TAG),-DBUILD_TAG='"$(BUILD_TAG)"')
+obj-$(CONFIG_TPL_BUILD)	+= bca_common.o
+obj-$(CONFIG_TPL_BUILD)	+= spl_env.o
+bootstate-$(CONFIG_BCM_BOOTSTATE) += bcm_bootstate.o
+obj-$(CONFIG_TPL_BUILD)	+= $(bootstate-y)
+obj-$(CONFIG_BCMBCA_IKOS) += board_ikos.o
+obj-$(CONFIG_TPL_BUILD) += board_secure.o
+obj-$(CONFIG_TPL_BUILD) += board_secure_tpl.o
+obj-$(CONFIG_TPL_BUILD) += board_secure_fit.o
+obj-$(CONFIG_TPL_BUILD) += board_secure_utils.o
+obj-$(CONFIG_TPL_BUILD) += mini-gmp/
diff --git a/board/broadcom/bcmbca/bca_common.c b/board/broadcom/bcmbca/bca_common.c
new file mode 100644
index 0000000000..d5584453a2
--- /dev/null
+++ b/board/broadcom/bcmbca/bca_common.c
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <linux/ctype.h>
+#include <stdlib.h>
+#include <string.h>
+#include "bca_common.h"
+
+#define CLI_CB_NUM 8
+
+struct cli_job_cb
+{
+    unsigned long last_time;
+    unsigned long time_period;
+    void (*job_cb)(void);
+};
+
+static unsigned long        registred_cb_count = 0;
+static struct cli_job_cb    cli_job_cb_arr[CLI_CB_NUM];
+
+void init_cli_cb_arr(void)
+{
+    memset(cli_job_cb_arr, 0, sizeof(struct cli_job_cb)*CLI_CB_NUM);
+}
+
+void register_cli_job_cb(unsigned long time_period, void (*job_cb)(void))
+{
+    int i;
+    for(i=0; i<CLI_CB_NUM; i++) 
+    {
+        if (!cli_job_cb_arr[i].job_cb)
+        {
+            cli_job_cb_arr[i].job_cb = job_cb;
+            cli_job_cb_arr[i].time_period = time_period;
+            cli_job_cb_arr[i].last_time = get_timer(0);
+            registred_cb_count++;
+            break;
+        }
+    }
+}
+
+void unregister_cli_job_cb(void (*job_cb)(void))
+{
+    int i,j;
+    for(i=0; i<registred_cb_count; i++) 
+    {
+        if (cli_job_cb_arr[i].job_cb == job_cb)
+        {
+            for(j=i; j<registred_cb_count; j++)
+            {
+                if(j+1 == registred_cb_count)
+                {
+                    memset(&cli_job_cb_arr[j], 0, sizeof(struct cli_job_cb));
+                    break;
+                }
+                memcpy(&cli_job_cb_arr[j], &cli_job_cb_arr[j+1], sizeof(struct cli_job_cb));
+            }
+            registred_cb_count--;
+            break;
+        }
+    }
+}
+
+void run_cli_jobs(void)
+{
+    int i;
+    for(i=0; i<registred_cb_count; i++) 
+    {
+        if(cli_job_cb_arr[i].job_cb)
+        {
+            if(!cli_job_cb_arr[i].time_period)
+            {
+                cli_job_cb_arr[i].job_cb();
+            }
+            else
+            {
+                if(get_timer(cli_job_cb_arr[i].last_time) >= cli_job_cb_arr[i].time_period)
+                {
+                    cli_job_cb_arr[i].job_cb();
+                    cli_job_cb_arr[i].last_time = get_timer(0);
+                }
+            }
+        }
+    }
+}
+
+int suffix2shift(char suffix)
+{
+	if (suffix == 'K')
+	{
+		return(10);
+	} else if (suffix == 'M')
+	{
+		return(20);
+	} else if (suffix == 'G')
+	{
+		return(30);
+	}
+	return(0);
+}
+
+/**
+ * parse_env_nums - get named environment value of format FIELD=n1,n2,n3....
+ * @buffer: pointer environment variable to parse
+ * @maxargs: max number of arguments to parse
+ * @args: pointer to array of unsigned longs for numeric arguments
+ * @suffixes: pointer to array of chars for suffix characters
+ *
+ * returns:
+ *     number of arguments total if successful
+ *     0 if not found
+ */
+int parse_env_nums(const char *buffer, const int maxargs, unsigned long *args, char *suffixes)
+{
+	int ret = 0;
+	char *b = NULL;
+	char *p;
+	int i;
+	int l;
+	char *tok;
+	if (NULL != buffer)
+	{
+		l = strlen(buffer);
+		b = malloc(l+1); 
+		strncpy(b, buffer, l+1);
+		p = b;
+		for (i = 0 ; i < maxargs ; i++)
+		{
+			tok = strtok(p,",");
+			p = NULL;
+			if (NULL != tok)
+			{
+				char *cp = NULL;
+				args[i] = simple_strtoul(tok, &cp, 0);
+				suffixes[i] = '\0';
+				if (NULL != cp)
+				{
+					if (isalpha(*cp) && (NULL != suffixes))
+					{
+						suffixes[i] = toupper(*cp);
+					} 
+				}
+				ret++;
+			}
+			else
+			{
+				break;
+			}
+		
+		}
+	}
+	if (b) free(b);
+	return(ret); 
+}
+
+
+/**
+ * parse_env_string_plus_nums - get named environment value of format FIELD=name:n1,n2,n3....
+ * @buffer: pointer environment variable to parse
+ * @name: pointer to buffer to which name will be copied [ caller is required to free this pointer ]
+ * @maxargs: max number of arguments to parse
+ * @args: pointer to array of unsigned longs for numeric arguments
+ * @suffixes: pointer to array of chars for suffix characters
+ *
+ * returns:
+ *     number of arguments total  (name + args) if successful
+ *     0 if not found
+ */
+int parse_env_string_plus_nums(const char *buffer, char **name, const int maxargs, unsigned long *args, char *suffixes)
+{
+	int ret = 0;
+	char *b;
+	int i;
+	int l;
+	char *tok;
+	if (NULL != buffer)
+	{
+		l = strlen(buffer);
+		b = malloc(l+1); 
+		strncpy(b, buffer, l+1);
+		tok = strtok(b,":");
+		*name = tok; 
+		ret++;
+		for (i = 0 ; i < maxargs ; i++)
+		{
+			tok = strtok(NULL,",");
+			if (NULL != tok)
+			{
+				char *cp = NULL;
+				args[i] = simple_strtoul(tok, &cp, 0);
+				suffixes[i] = '\0';
+				if (NULL != cp)
+				{
+					if (isalpha(*cp) && (NULL != suffixes))
+					{
+						suffixes[i] = toupper(*cp);
+					} 
+				}
+				ret++;
+			}
+			else
+			{
+				break;
+			}
+		
+		}
+	}
+	return(ret); 
+}
+
diff --git a/board/broadcom/bcmbca/bcm_bootstate.c b/board/broadcom/bcmbca/bcm_bootstate.c
new file mode 100644
index 0000000000..aa8fb46290
--- /dev/null
+++ b/board/broadcom/bcmbca/bcm_bootstate.c
@@ -0,0 +1,251 @@
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/global_data.h>
+#include <linux/libfdt.h>
+#include <asm/arch/cpu.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <dm.h>
+
+
+#include "bcm_bootstate.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CHECK_NULL(ptr) ptr != NULL //|| init_regs()
+
+typedef void (*set_boot_reason_p)(uint32_t value);
+typedef void (*clear_boot_reason_p)(void);
+typedef uint32_t (*get_boot_reason_p)(void);
+
+struct spi_reset_reason
+{
+	uint32_t *glb_cntrl;
+	uint32_t *flash_cntrl;
+	uint32_t *profile;
+
+};
+typedef struct boot_state_data
+{
+	uint32_t *reset_status;
+	union
+	{
+		volatile uint32_t *reset_reason;
+		struct spi_reset_reason srr;
+	};
+	set_boot_reason_p set_boot_reason;
+	get_boot_reason_p get_boot_reason;
+	clear_boot_reason_p clear_boot_reason;
+
+}boot_state_data;
+
+boot_state_data __attribute__((section(".data"))) b_state_data;
+
+int bcmbca_get_reset_status(void)
+{
+	int resetStatus = -1;
+	if(CHECK_NULL((b_state_data.reset_status)))
+	{
+		resetStatus = *b_state_data.reset_status & RESET_STATUS_MASK;
+	}
+	return resetStatus;
+}
+unsigned long i=0;
+static void bcmbca_set_boot_reason_v1(uint32_t value)
+{
+
+	if(CHECK_NULL((b_state_data.srr.glb_cntrl)))
+	{
+		*b_state_data.srr.glb_cntrl |= DO_NOT_RESET_ON_WATCHDOG;
+		if(CHECK_NULL((b_state_data.srr.profile)))
+		{
+			*b_state_data.srr.profile = value;
+		}
+	}
+
+}
+static void bcmbca_set_boot_reason_v2(uint32_t value)
+{
+	uint32_t tmp_val;
+	int retries=0;
+
+	if(CHECK_NULL((b_state_data.reset_reason)))
+	{
+		while(retries++ < 255) 
+		{
+			tmp_val=*b_state_data.reset_reason;
+			dsb();
+			*b_state_data.reset_reason=value;
+			dsb();
+			tmp_val=*b_state_data.reset_reason;
+			if(tmp_val == value)
+				break;
+		}
+		if(retries > 1)
+			printf("current value %d value to write %d retried [%d] times to write the reset_reason %s\n", tmp_val, value, retries, (tmp_val == value) ? "success":"fail");
+	}
+}
+
+void bcmbca_set_boot_reason(uint32_t value)
+{
+	if(CHECK_NULL(b_state_data.set_boot_reason))
+	{
+		b_state_data.set_boot_reason(value);
+	}
+} 
+
+
+static void bcmbca_clear_boot_reason_v1(void)
+{
+	if(CHECK_NULL((b_state_data.srr.glb_cntrl)))
+	{
+		*b_state_data.srr.glb_cntrl &= ~DO_NOT_RESET_ON_WATCHDOG;
+		if(CHECK_NULL((b_state_data.srr.flash_cntrl)))
+		{
+			*b_state_data.srr.flash_cntrl = FLASH_CNTRL_RESET_VAL;
+		}
+		if(CHECK_NULL((b_state_data.srr.profile)))
+		{
+			*b_state_data.srr.profile = 0;
+		}
+	}
+}
+static void bcmbca_clear_boot_reason_v2(void)
+{
+	uint32_t tmp_val;
+	int retries=0;
+	if(CHECK_NULL((b_state_data.reset_reason)))
+	{
+		while(retries++ < 255)
+		{
+			tmp_val=*b_state_data.reset_reason;
+			dsb();
+			*b_state_data.reset_reason &= ~(0x1ffff);
+			dsb();
+			tmp_val=*b_state_data.reset_reason;
+			if((tmp_val & (0x1ffff)) == 0)
+				break;
+		}
+		if(retries > 1)
+			printf("retried [%d] times to clear the reset_reason %s\n", retries, ((tmp_val & (0x1ffff)) == 0) ? "success":"fail");
+	}
+}
+
+void bcmbca_clear_boot_reason(void)
+{
+	if(CHECK_NULL((b_state_data.clear_boot_reason)))
+	{
+		b_state_data.clear_boot_reason();
+	}
+}
+
+static uint32_t bcmbca_get_boot_reason_v1(void)
+{
+uint32_t rc=-1;
+
+	if(CHECK_NULL((b_state_data.srr.profile)))
+	{
+		rc=(*b_state_data.reset_status & SW_RESET_STATUS) != 0 ? *b_state_data.srr.profile & 0x1ffff:-1;
+	}
+return rc;
+}
+static uint32_t bcmbca_get_boot_reason_v2(void)
+{
+uint32_t rc=-1;
+
+	//boot reason is only good in case of sw reset
+	if((b_state_data.reset_reason != NULL && b_state_data.reset_status != NULL))
+	{
+		rc=(*b_state_data.reset_status & SW_RESET_STATUS) != 0 ? *b_state_data.reset_reason & 0x1ffff:-1;
+	}
+return rc;
+}
+
+uint32_t bcmbca_get_boot_reason(void)
+{
+int rc=-1;
+	if(CHECK_NULL((b_state_data.get_boot_reason)))
+	{
+		rc = b_state_data.get_boot_reason();
+	}
+return rc;
+}
+
+
+static int bootstate_v1_probe(struct udevice *dev)
+{
+	struct resource res;
+	int ret=0;
+	b_state_data.clear_boot_reason = bcmbca_clear_boot_reason_v1;
+	b_state_data.set_boot_reason = bcmbca_set_boot_reason_v1;
+	b_state_data.get_boot_reason = bcmbca_get_boot_reason_v1;
+	ret = dev_read_resource_byname(dev, "reset_status", &res);
+        if (!ret) {
+		b_state_data.reset_status=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	ret = dev_read_resource_byname(dev, "global_control", &res);
+        if (!ret) {
+		b_state_data.srr.glb_cntrl=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	ret = dev_read_resource_byname(dev, "flash_control", &res);
+        if (!ret) {
+		b_state_data.srr.flash_cntrl=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	ret = dev_read_resource_byname(dev, "mode_control", &res);
+        if (!ret) {
+		b_state_data.srr.profile=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+return 0;
+}
+static int bootstate_v2_probe(struct udevice *dev)
+{
+	struct resource res;
+	int ret=0;
+	b_state_data.clear_boot_reason = bcmbca_clear_boot_reason_v2;
+	b_state_data.set_boot_reason = bcmbca_set_boot_reason_v2;
+	b_state_data.get_boot_reason = bcmbca_get_boot_reason_v2;
+
+	ret = dev_read_resource_byname(dev, "reset_status", &res);
+        if (!ret) {
+		b_state_data.reset_status=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	ret = dev_read_resource_byname(dev, "reset_reason", &res);
+        if (!ret) {
+		b_state_data.reset_reason=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+return 0;
+}
+
+static const struct udevice_id bootstate_v1_ids[] = {
+        { .compatible = "brcm,bcmbca-bootstate-v1" },
+        { }
+};
+static const struct udevice_id bootstate_v2_ids[] = {
+        { .compatible = "brcm,bcmbca-bootstate-v2" },
+        { }
+};
+
+U_BOOT_DRIVER(bootstate_v1_drv) = {
+        .name = "bcm_bootsate_v1",
+        .id = UCLASS_NOP,
+        .of_match = bootstate_v1_ids,
+        .probe = bootstate_v1_probe,
+};
+U_BOOT_DRIVER(bootstate_v2_drv) = {
+        .name = "bcm_bootsate_v2",
+        .id = UCLASS_NOP,
+        .of_match = bootstate_v2_ids,
+        .probe = bootstate_v2_probe,
+};
+
+void bca_bootstate_probe(void)
+{
+	struct udevice *dev;
+
+	memset(&b_state_data, '\0', sizeof(b_state_data));
+
+	//for (uclass_first_device_check(UCLASS_MISC, &dev); dev; uclass_next_device_check(&dev));
+
+	uclass_get_device_by_driver(UCLASS_NOP, DM_GET_DRIVER(bootstate_v2_drv), &dev);
+	uclass_get_device_by_driver(UCLASS_NOP, DM_GET_DRIVER(bootstate_v1_drv), &dev);
+}
diff --git a/board/broadcom/bcmbca/bcm_bootstate.h b/board/broadcom/bcmbca/bcm_bootstate.h
new file mode 100644
index 0000000000..a42c46ae80
--- /dev/null
+++ b/board/broadcom/bcmbca/bcm_bootstate.h
@@ -0,0 +1,30 @@
+#include <common.h>
+
+#define BOOT_STATE_VERSION_1 0x01
+#define BOOT_STATE_VERSION_2 0x02
+
+#define DO_NOT_RESET_ON_WATCHDOG (1<<22)
+#define FLASH_CNTRL_RESET_VAL 0x050b
+
+#define PCIE_RESET_STATUS       0x10000000
+#define SW_RESET_STATUS         0x20000000
+#define HW_RESET_STATUS         0x40000000
+#define POR_RESET_STATUS        0x80000000
+#define RESET_STATUS_MASK       0xF0000000
+
+#define BCM_BOOT_REASON_REBOOT 		(0x00000000)
+#define BCM_BOOT_REASON_ACTIVATE 	(0x00000001)
+#define BCM_BOOT_REASON_PANIC 		(0x00000002)
+#define BCM_BOOT_REASON_WATCHDOG	(0x00000004)
+
+#define BCM_BOOT_PHASE_MASK		(0x000000F0)
+#define BCM_BOOT_PHASE_UBOOT		(0x00000010)
+#define BCM_BOOT_PHASE_LINUX_START	(0x00000020)
+#define BCM_BOOT_PHASE_LINUX_RUN	(0x00000030)
+
+int bcmbca_get_reset_status(void);
+void bcmbca_set_boot_reason(uint32_t value);
+void bcmbca_clear_boot_reason(void);
+uint32_t bcmbca_get_boot_reason(void);
+void bca_bootstate_probe(void);
+
diff --git a/board/broadcom/bcmbca/bcm_uboot_lockdown.c b/board/broadcom/bcmbca/bcm_uboot_lockdown.c
new file mode 100644
index 0000000000..1ea6be7137
--- /dev/null
+++ b/board/broadcom/bcmbca/bcm_uboot_lockdown.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Broadcom Corporation
+ * Joel Peshkin, Broadcom Corporation, joel.peshkin@broadcom.com
+ */
+
+#define DEBUG
+#define USE_FIXED_PASSWORD 1
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <hexdump.h>
+#include <linux/ctype.h>
+#include <linux/stddef.h>
+#include <u-boot/sha256.h>
+#include <errno.h>
+#include <bca_sdk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *null_env = "\0\0\0\0";
+
+#define BCM_LOCKDOWN_MAX_ENV_NAME 64
+#define BCM_LOCKDOWN_MAX_ENV_VALUE 520
+/* also limit with CONFIG_ENV_SIZE */
+
+static void lock_env_add_safe(char *name, char *val, char *safe, int max);
+
+/* 
+ * lock_env_add_safe:  Add environment variable only if its value is strictly alphanumeric or
+ *                     alphanumeric plus a specific set of characters
+ */
+static void lock_env_add_safe(char *name, char *val, char *safe, int max)
+{
+	int l;
+	int i;
+	char v[2];
+	v[1] = '\0';
+	l = strlen(val);
+	if (l > max) {
+		return;
+	}
+	for (i = 0; i < l; i++) {
+		v[0] = val[i];
+		if (!(isalnum(val[i]) || (NULL != strstr(safe, v)))) {
+			/* printf("rejected '%s'='%s'\n",name,val); */
+			return;
+		}
+	}
+	env_set(name, val);
+}
+
+int env_override_import(void *ep)
+{
+	char sha_env_str[SHA256_SUM_LEN * 4 + 1]; /* enough room for salt */
+	char password[32];
+	char salt[32] = {0};
+	char dnum[16] = {0};
+	u8 sha_env[SHA256_SUM_LEN];
+	char *cp = ((char *)ep) + 4;	/* skip length field */
+	char *delim;
+	int once = 0;
+	int size = 0;
+	int i,j;
+	int node,len;
+	env_import((void *)null_env, 0);
+	env_set("overridden", "true");
+	/* Iterate over stored environment variables and only import them if they are trusted */
+	while (*cp != '\0') {
+		delim = strstr(cp, "=");
+		if (delim && (delim <= cp + BCM_LOCKDOWN_MAX_ENV_NAME)
+		    && (delim <= ep + CONFIG_ENV_SIZE)) {
+			*delim = '\0';
+			delim++;
+			if (strlen(delim) > BCM_LOCKDOWN_MAX_ENV_VALUE) {
+				break;
+			}
+			/* if we made it this far, *cp and *delim point to name and value */
+
+			if ((strcmp(cp, "IMAGE") == 0)
+			    || (strcmp(cp, "MCB") == 0)
+			    || (strcmp(cp, "ethaddr") == 0)) {
+				/* These are OK as long as they contain only alphanumeric plus : */
+				lock_env_add_safe(cp, delim, ":,", 32);
+			} else if (strcmp(cp, "env_boot_magic") == 0) {
+				/* env_boot_magic is safe but can have '@' */
+				lock_env_add_safe(cp, delim, "@,", 32);
+			} else if (strcmp(cp, "once") == 0) {
+				/* "once" can be stores as "once=true" 
+				 * otherwise, we will need to set it to a fixed script later
+				 */
+				if (strcmp(delim, "true") == 0) {
+					once = 1;
+					env_set(cp, delim);
+				}
+			} else if (strncmp(cp, "rdp", 3) == 0) {
+				lock_env_add_safe(cp, delim, "", 6);
+			} else if (strcmp(cp, "nummacaddrs") == 0) {
+				lock_env_add_safe(cp, delim, "_", 32);
+			} else if (strcmp(cp, "boardid") == 0) {
+				lock_env_add_safe(cp, delim, "_", 32);
+			} else {
+				/* printf("skipped '%s'='%s'\n",cp,delim); */
+			}
+
+			/* done with conditional import */
+			cp = delim + strlen(delim) + 1;
+		} else {
+			break;
+		}
+	}
+
+	/* Boot command can only be set from this (signed) code and will not accept arbitrary values */
+	env_set("bootdelay", "5");
+	env_set("bootcmd", "printenv; run once ; sdk boot_img");
+
+	/* If we haven't stored the value of "once" as "true" yet, we want it to be a script of commands
+	 * to be executed once.  At a minimum, after an image is programmed, we need to save the environment
+	 * including the env_boot_magic variable one time to reflect the physical flash offset of the environment
+	 * redundant copies
+	 */
+	if (once == 0) {
+		env_set("once", "setenv once true; saveenv");
+	}
+	// gd->flags |= GD_FLG_DISABLE_CONSOLE; 
+
+	node = fdt_path_offset(gd->fdt_blob, "/trust/serial_num");
+	if (node < 0) {
+		printf("no serial number node in uboot DTB\n");
+	} else {
+		unsigned long sn = 0;
+		len = 0;
+		cp = NULL;
+		cp = (char *)fdt_getprop(gd->fdt_blob, node, "value", &len);
+		printf("full serial number: ");
+		for (i = 0; i < len ; i++) {
+			printf("%02x",cp[i]);
+		}
+		printf("\n");
+		if (len) {
+			for (i = 0 ; i < 6 ; i++) {
+				sn = (sn << 8) | (long)(cp[len-6+i]);
+			}
+			printf("decimal serial number: %ld\n",sn);
+			sprintf(dnum,"%ld",sn);
+			env_set("decimal_serial_num", dnum);
+		}
+	}
+
+	/* Now set bootstopkeysha256 */
+
+	/* In this example, password is being set to a fixed value.   More likely, you will want to set it to
+	 * something like the base64 of the last 6 bytes of the sha256 of a secret concatenated with the serial 
+	 * number 
+	 */
+
+	size = SHA256_SUM_LEN;
+	j = 0;
+
+	node = fdt_path_offset(gd->fdt_blob, "/trust/key_cli_seed");
+
+#ifndef USE_FIXED_PASSWORD
+	if (node < 0) {
+		printf("no cli seed node in uboot DTB\n");
+	} else {
+		char combined[256];
+		long long pass;
+		char cset[] = "abcdefghijk#mnopqrstuvwxyzABCDEFGHIJKLMN-PQRSTUVWXYZ@!23456789_*";
+		len = 0;
+		cp = NULL;
+		cp = (char *)fdt_getprop(gd->fdt_blob, node, "value", &len);
+		strncpy(combined,cp,256);
+		strncat(combined,dnum,256);
+		hash_block("sha256", (const void *)combined,
+		   strlen(combined), sha_env, &size);
+		memcpy(&pass, sha_env, sizeof(pass));
+		for (i = 0 ; i < 8 ; i++) {
+			password[i] = cset[ (pass >> (6 * i) ) & 0x3f ];
+		}
+		password[8] = 0;
+		printf("OBVIOUSLY -- REMOVE THIS PRINT\npassword set to %s\n",password);
+	}
+#endif
+		
+
+#ifdef USE_FIXED_PASSWORD
+	strcpy(salt, "S4lt3d@");
+	strcpy(password, salt);
+	strcat(password, "test54321");
+#endif
+
+	hash_block("sha256", (const void *)password,
+		   strlen(password), sha_env, &size);
+	j = sprintf(sha_env_str,"%s:",salt);
+	for (i = 0; i < SHA256_SUM_LEN; i++) {
+		j += sprintf(&sha_env_str[j], "%02x", sha_env[i]);
+	}
+
+	env_set("bootstopkeysha256", sha_env_str);
+	return 1;
+}
diff --git a/board/broadcom/bcmbca/bcmbca_button.c b/board/broadcom/bcmbca/bcmbca_button.c
new file mode 100644
index 0000000000..76f6817fd0
--- /dev/null
+++ b/board/broadcom/bcmbca/bcmbca_button.c
@@ -0,0 +1,708 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <linux/compat.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "bcmbca_button.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BCA_GPIO_ACTIVE_HIGH    (0x0 << 1)
+#define BCA_GPIO_ACTIVE_LOW     (0x1 << 1)
+
+#define CONSUMER_NAME           "ext_irq"
+#define BTN_EVENT_NUM           3
+
+#define PRINT_ACT_NAME          "print"
+#define PRINT_ACT_NAME_UBOOT    "print_uboot"
+
+#define PRESS_EVENT             "press"
+#define HOLD_EVENT              "hold"
+#define RELEASE_EVENT           "release"
+
+#define MAX_BTN_HOOKS_PER_TRIG  5
+#define MAX_BTN_HOOKS_PER_BTN   (MAX_BTN_HOOKS_PER_TRIG * 3)
+
+typedef enum {
+	PB_BUTTON_0,
+	PB_BUTTON_1,
+	PB_BUTTON_2,
+	PB_BUTTON_MAX
+} PB_BUTTON_ID;
+
+#define BTN_EV_PRESSED      0x1
+#define BTN_EV_HOLD         0x2
+#define BTN_EV_RELEASED     0x4
+#define BTN_POLLFREQ        100 /* in ms */
+
+// Main button structure:
+typedef struct _BtnInfo {
+	PB_BUTTON_ID btnId;
+	struct gpio_desc gd;
+	int active;
+	u32 lastPressTime;
+	u32 lastHoldTime;
+	u32 lastReleaseTime;
+	spinlock_t lock;
+	u32 events;
+	u32 act_registered;
+	u32 longest_holdevt;
+	void *poll;
+	char name[32];
+	bool (*isDown)(struct _BtnInfo *btnInfo);
+} BtnInfo;
+
+typedef struct {
+	buttonNotifyHook_t hook;
+	unsigned long timeout; // in ms;
+	void *param;
+	int done;
+} pushButtonHookInfo_t;
+
+typedef int (*registerBtnHook)(PB_BUTTON_ID btn,
+				buttonNotifyHook_t hook,
+				unsigned long timeInMs,
+				void *param);
+
+struct button_action {
+	char *action_name;
+	buttonNotifyHook_t btn_hook;
+};
+
+struct button_events {
+	char *btn_event;
+	registerBtnHook reg_hook;
+};
+
+static pushButtonHookInfo_t btnPressedInfo[PB_BUTTON_MAX][MAX_BTN_HOOKS_PER_TRIG] = {};
+static pushButtonHookInfo_t btnHeldInfo[PB_BUTTON_MAX][MAX_BTN_HOOKS_PER_TRIG] = {};
+static pushButtonHookInfo_t btnReleasedInfo[PB_BUTTON_MAX][MAX_BTN_HOOKS_PER_TRIG] = {};
+static int btnPressTime[PB_BUTTON_MAX] = {};
+
+static BtnInfo btnInfo[PB_BUTTON_MAX] = {};
+
+static void reset_hooks_array(PB_BUTTON_ID btn)
+{
+	int j;
+
+	for (j = 0; j < MAX_BTN_HOOKS_PER_TRIG; j++) {
+		btnPressedInfo[btn][j].done = 0;
+		btnHeldInfo[btn][j].done = 0;
+		btnReleasedInfo[btn][j].done = 0;
+	}
+}
+
+static BtnInfo *find_btn_info(const char *name)
+{
+	int i;
+
+	for (i = 0 ; i < PB_BUTTON_MAX; i++) {
+		if (!strcmp(name, btnInfo[i].name))
+			return &btnInfo[i];
+	}
+	return NULL;
+}
+
+static BtnInfo *find_btn_info_by_id(PB_BUTTON_ID btn)
+{
+	int i;
+
+	for (i = 0; i < PB_BUTTON_MAX; i++) {
+		if (btnInfo[i].btnId == btn)
+			return &btnInfo[i];
+	}
+	return NULL;
+}
+
+static void do_button(PB_BUTTON_ID btn,
+				unsigned long currentTime,
+				pushButtonHookInfo_t (*actions_arr)[MAX_BTN_HOOKS_PER_TRIG])
+{
+	unsigned long timeInMs;
+	pushButtonHookInfo_t *pInfo;
+	int callIdx;
+	int callInfoIdx = 0;
+	pushButtonHookInfo_t callInfo[MAX_BTN_HOOKS_PER_TRIG] = {};
+	unsigned long flags;
+	int idx;
+
+	if (unlikely(btn >= PB_BUTTON_MAX)) {
+		printk(KERN_ERR "%s: unrecognized button id (%d)\n",
+			__func__, btn);
+		return;
+	}
+
+	timeInMs = currentTime - btnPressTime[btn];
+
+	spin_lock_irqsave(&lock, flags);
+	for (idx = 0; idx < MAX_BTN_HOOKS_PER_TRIG; idx++) {
+		pInfo = &actions_arr[btn][idx];
+		if (pInfo->done)
+			continue;
+
+		if (pInfo->hook) {
+			if (pInfo->timeout) {
+				if (pInfo->timeout > timeInMs)
+					continue;
+			}
+			callInfo[callInfoIdx] = *pInfo;
+			pInfo->done = 1;
+			callInfoIdx++;
+		}
+	}
+	spin_unlock_irqrestore(&lock, flags);
+
+	for (callIdx = 0; callIdx < callInfoIdx; callIdx++)
+		callInfo[callIdx].hook(timeInMs, callInfo[callIdx].param);
+
+}
+
+void do_button_release(PB_BUTTON_ID btn, unsigned long currentTime)
+{
+	int idx;
+	unsigned long timeInMs;
+	unsigned long flags;
+	int callIdx;
+	int callInfoIdx = 0;
+	pushButtonHookInfo_t callInfo[MAX_BTN_HOOKS_PER_TRIG] = {};
+
+	if (unlikely(btn >= PB_BUTTON_MAX)) {
+		printk(KERN_ERR "%s: unrecognized button id (%d)\n", __func__, btn);
+		return;
+	}
+
+	timeInMs = currentTime - btnPressTime[btn];
+
+	spin_lock_irqsave(&lock, flags);
+	for (idx = 0; idx < MAX_BTN_HOOKS_PER_TRIG; idx++) {
+		pushButtonHookInfo_t *pNewInfo = &btnReleasedInfo[btn][idx];
+
+		if (!pNewInfo->hook || pNewInfo->timeout > timeInMs)
+			continue;
+		if (callInfoIdx == 0 || pNewInfo->timeout == callInfo[0].timeout) {
+			callInfo[callInfoIdx] = *pNewInfo;
+			callInfoIdx++;
+		} else if (pNewInfo->timeout > callInfo[0].timeout) {
+			callInfo[0] = *pNewInfo;
+			callInfoIdx = 1;
+		}
+	}
+	spin_unlock_irqrestore(&lock, flags);
+
+	for (callIdx = 0; callIdx < callInfoIdx; callIdx++)
+		callInfo[callIdx].hook(timeInMs, callInfo[callIdx].param);
+}
+
+static int insert_to_array(buttonNotifyHook_t hook,
+			unsigned long timeInMs,
+			void *param,
+			pushButtonHookInfo_t *pHookArray)
+{
+	int idx;
+	pushButtonHookInfo_t *pInfo;
+
+	if (pHookArray[MAX_BTN_HOOKS_PER_TRIG - 1].hook) {
+		printk(KERN_ERR "%s: to many entries\n", __func__);
+		return -1;
+	}
+	for (idx = 0; idx < MAX_BTN_HOOKS_PER_TRIG; idx++) {
+		pInfo = &pHookArray[idx];
+		if (!pInfo->hook) {  // inserting at end
+			pInfo->hook = hook;
+			pInfo->timeout = timeInMs;
+			pInfo->param = param;
+			return idx;
+		}
+	}
+	return -1;
+}
+
+static int register_button_press_notify_hook(PB_BUTTON_ID btn,
+				buttonNotifyHook_t hook,
+				unsigned long timeInMs,
+				void *param)
+{
+	unsigned long flags;
+	int idx;
+
+	if (unlikely(btn >= PB_BUTTON_MAX)) {
+		printk(KERN_ERR "%s: unrecognized button id (%d)\n", __func__, btn);
+		return -1;
+	}
+	if (unlikely(!hook)) {
+		printk(KERN_ERR "%s: cannot register NULL hook\n", __func__);
+		return -1;
+	}
+
+	spin_lock_irqsave(&lock, flags);
+	idx = insert_to_array(hook, timeInMs, param, btnPressedInfo[btn]);
+	spin_unlock_irqrestore(&lock, flags);
+	if (unlikely(idx < 0)) {
+		printk(KERN_ERR "%s: Could not insert notify hook %pF (out of room)\n",
+			__func__, hook);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int register_button_hold_notify_hook(PB_BUTTON_ID btn,
+				buttonNotifyHook_t hook,
+				unsigned long timeInMs,
+				void *param)
+{
+	int idx;
+	unsigned long flags;
+	BtnInfo *button = NULL;
+  
+	if (unlikely(btn >= PB_BUTTON_MAX)) {
+		printk(KERN_ERR "%s: unrecognized button id (%d)\n", __func__, btn);
+		return -1;
+	}
+	if (unlikely(!hook)) {
+		printk(KERN_ERR "%s: cannot register NULL hook\n", __func__);
+		return -1;
+	}
+	button = find_btn_info_by_id(btn);
+	if (unlikely(!button)) {
+		printk(KERN_ERR "%s: cannot find the button info for id %d\n", __func__, btn);
+		return -1;
+	}
+
+	spin_lock_irqsave(&lock, flags);
+	idx = insert_to_array(hook, timeInMs, param, btnHeldInfo[btn]);
+	if (timeInMs > button->longest_holdevt)
+		button->longest_holdevt = timeInMs;
+	spin_unlock_irqrestore(&lock, flags);
+	if (unlikely(idx < 0)) {
+		printk(KERN_ERR "%s: Could not insert notify hook %pF (out of room)\n", __func__, hook);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int register_button_release_notify_hook(PB_BUTTON_ID btn,
+				buttonNotifyHook_t hook,
+				unsigned long timeInMs,
+				void *param)
+{
+	int idx;
+	unsigned long flags;
+	BtnInfo *button = NULL;
+
+	if (unlikely(btn >= PB_BUTTON_MAX)) {
+		printk(KERN_ERR "%s: unrecognized button id (%d)\n", __func__, btn);
+		return -1;
+	}
+	if (unlikely(!hook)) {
+		printk(KERN_ERR "%s: cannot register NULL hook\n", __func__);
+		return -1;
+	}
+	button = find_btn_info_by_id(btn);
+	if (unlikely(!button)) {
+		printk(KERN_ERR "%s: cannot find the button info for id %d\n", __func__, btn);
+		return -1;
+	}
+	
+	spin_lock_irqsave(&lock, flags);
+	idx = insert_to_array(hook, timeInMs, param, btnReleasedInfo[btn]);
+	if (timeInMs > button->longest_holdevt)
+		button->longest_holdevt = timeInMs;
+	spin_unlock_irqrestore(&lock, flags);
+	if (unlikely(idx < 0)) {
+		printk(KERN_ERR "%s: Could not insert notify hook %pF (out of room)\n", __func__, hook);
+		return -1;
+	}
+
+	return 0;
+}
+
+/***************************************************************************/
+// BP_BTN_ACTION_PRINT
+static void btn_hook_print(unsigned long timeInMs, void *param)
+{
+	printk("%s\n", (char *)param);
+}
+
+/***************************************************************************
+ * Function Name: btn_do_press
+ * Description  : This is called when a press has been detected.
+ * Parameters   : arg: a pointer to a BtnInfo structure
+ ***************************************************************************/
+static void btn_do_press(BtnInfo *btn, unsigned long currentTime)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&lock, flags);
+
+	reset_hooks_array(btn->btnId);
+	btnPressTime[btn->btnId] = currentTime;
+	btn->events &= ~BTN_EV_PRESSED;
+
+	spin_unlock_irqrestore(&lock, flags);
+
+	do_button(btn->btnId, currentTime, btnPressedInfo);
+}
+
+/***************************************************************************
+ * Function Name: btn_do_release
+ * Description  : This is called when a release has been detected
+ * Parameters   : arg: a pointer to a BtnInfo structure
+ ***************************************************************************/
+static void btn_do_release(BtnInfo *btn, unsigned long currentTime)
+{
+	btn->events &= ~(BTN_EV_RELEASED | BTN_EV_HOLD);
+	do_button_release(btn->btnId, currentTime);
+}
+
+/***************************************************************************
+ * Function Name: btn_do_hold
+ * Description  : This is called when a button hold is detected
+ * Parameters   : arg: a pointer to a BtnInfo structure
+ ***************************************************************************/
+static void btn_do_hold(BtnInfo *btn, unsigned long currentTime)
+{
+	btn->events &= ~BTN_EV_HOLD;
+	do_button(btn->btnId, currentTime, btnHeldInfo);
+}
+
+static int __btn_poll(BtnInfo *btn)
+{
+	unsigned long currentTime = get_timer(0);
+	unsigned long flags;
+
+	spin_lock_irqsave(&btn->lock, flags);
+	if (btn->active) {
+		if (btn->isDown(btn)) {
+			btn->lastHoldTime = currentTime;
+			btn->events |= BTN_EV_HOLD;
+			btn_do_hold(btn, btn->lastHoldTime);
+		} else {
+			btn->lastReleaseTime = currentTime;
+			btn->active = 0;
+			btn->events |= BTN_EV_RELEASED;
+			btn_do_release(btn, btn->lastReleaseTime);
+		}
+	} else {
+		if (btn->isDown(btn)) {
+			btn->active = 1;
+			btn->lastPressTime = currentTime;
+			btn->events |= BTN_EV_PRESSED;
+			btn_do_press(btn, btn->lastPressTime);
+		}
+	}
+
+	spin_unlock_irqrestore(&btn->lock, flags);
+
+	return btn->active;
+}
+
+/***************************************************************************
+ * Function Name: btn_poll
+ * Description  : This is the polling function. It checks each button
+		  and act on if event timeout occurs. It should be called by
+		  u-boot periodic function such as cli_loop
+ * Return       : positive if any button is active
+ ***************************************************************************/
+int btn_poll(void)
+{
+	BtnInfo *btn;
+	int i, rc = 0;
+
+	for (i = PB_BUTTON_0; i < PB_BUTTON_MAX; i++) {
+		btn = &btnInfo[i];
+		if (btn->poll && btn->act_registered)
+			rc |= __btn_poll(btn);
+	}
+
+	return rc;
+}
+
+/***************************************************************************
+ * Function Name: btn_poll_block
+ * Description  : This function keep polling the button until all button is
+		  released. It can be called during the boot to any special
+		  button event before entering the cli
+ ***************************************************************************/
+void btn_poll_block(void)
+{
+	int rc = 1;
+
+	while (rc)
+		rc = btn_poll();
+}
+
+/***************************************************************************
+ * Function Name: btn_is_gpio_btn_down
+ * Description  : This a the check to see if a gpio-based button is down
+		  based on the gpio level
+ * Parameters   : arg: a pointer to a BtnInfo structure
+ * Returns      : 1 if the button is down
+ ***************************************************************************/
+static bool btn_is_gpio_btn_down(BtnInfo *btn)
+{
+	return dm_gpio_get_value(&btn->gd);
+}
+
+static struct button_events btn_events[BTN_EVENT_NUM] = {
+	{PRESS_EVENT,   register_button_press_notify_hook},
+	{HOLD_EVENT,    register_button_hold_notify_hook},
+	{RELEASE_EVENT, register_button_release_notify_hook}
+};
+
+static registerBtnHook get_register_hook_fnc(const char *event_name)
+{
+	int i;
+
+	for (i = 0; i < BTN_EVENT_NUM; i++) {
+		if (!strcmp(event_name, btn_events[i].btn_event))
+			return btn_events[i].reg_hook;
+	}
+	return NULL;
+}
+
+static int read_button_event_action_params(ofnode btn_event_np, const char *action_name,
+	u32 *ptimeout, void** pparam)
+{
+	const char *print_string = NULL, *cmd_string = NULL;
+	char *action_name_cmd;
+	
+	if (!strcmp(action_name, PRINT_ACT_NAME)
+		|| !strcmp(action_name, PRINT_ACT_NAME_UBOOT)) {
+			print_string = ofnode_read_string(btn_event_np, action_name);
+			if (print_string == NULL)
+				return -1;
+			*pparam = strndup(print_string, strlen(print_string));
+	} else {
+		if (ofnode_read_u32(btn_event_np, action_name, ptimeout))
+			return -1;
+		*ptimeout *= 1000;
+
+		/* check if <action_name>_cmd command string is defined */
+		action_name_cmd = malloc(sizeof(action_name) + 8);
+		sprintf(action_name_cmd, "%s_cmd", action_name);
+		cmd_string = ofnode_read_string(btn_event_np, action_name_cmd);
+		if (cmd_string)
+			*pparam = strndup(cmd_string, strlen(cmd_string));
+		free(action_name_cmd);
+	}
+
+	return 0;
+}
+
+static int register_button_event_action(const char *button_name, ofnode event_np,
+	buttonNotifyHook_t hook, u32 timeout, void* param)
+{
+	registerBtnHook btn_hook_register = NULL;
+	BtnInfo *btn_info = NULL;
+
+	btn_hook_register =
+		get_register_hook_fnc(ofnode_get_name(event_np));
+	if (!btn_hook_register)
+		return -1;
+	
+	btn_info = find_btn_info(button_name);
+	if (!btn_info)
+		return -1;
+	
+	if (btn_hook_register(btn_info->btnId, hook, timeout, param))
+		return -1;
+	else 
+		btn_info->act_registered =1;
+
+	return 0;
+}
+  
+
+int register_button_action(const char *button_name, const char *action_name,
+	buttonNotifyHook_t hook)
+{
+	ofnode btn_np, btn_event_np;
+	u32 timeout = 0;
+	void *param = NULL;
+
+	btn_np = ofnode_by_compatible(ofnode_null(), "brcm,buttons");
+	if (!ofnode_valid(btn_np))
+		return -ENODEV;
+
+	btn_np = ofnode_find_subnode(btn_np, button_name);
+	if (!ofnode_valid(btn_np))
+		return -ENODEV;
+
+	ofnode_for_each_subnode(btn_event_np, btn_np) {
+		if (read_button_event_action_params(btn_event_np, action_name,
+			&timeout, &param))
+			continue;
+
+		if (register_button_event_action(button_name, btn_event_np, hook,
+				timeout, param))
+			return -ENOENT;
+	}
+
+	return 0;
+}
+
+int register_button_action_for_event(const char *button_name, const char* event_name,
+	const char *action_name, buttonNotifyHook_t hook)
+{
+	ofnode btn_np, btn_event_np;
+	u32 timeout = 0;
+	void *param = NULL;
+	const void *fdt = gd->fdt_blob;
+	int node_offset, prop_offset;
+	const void *value;
+	const char *propname;	
+	int len, num_action = 0;
+
+	btn_np = ofnode_by_compatible(ofnode_null(), "brcm,buttons");
+	if (!ofnode_valid(btn_np))
+		return -ENODEV;
+
+	btn_np = ofnode_find_subnode(btn_np, button_name);
+	if (!ofnode_valid(btn_np))
+		return -ENODEV;
+
+	btn_event_np = ofnode_find_subnode(btn_np, event_name);
+	if (!ofnode_valid(btn_np))
+		return -ENODEV;
+
+	if (action_name) {
+		if (!read_button_event_action_params(btn_event_np, action_name,
+			&timeout, &param)) {
+			if (register_button_event_action(button_name, btn_event_np, hook,
+				timeout, param))
+				return -ENOENT;
+			else
+				num_action++;
+		}
+	} else {
+		/* no action_name specified, enumerate all the actions properties */
+		node_offset = ofnode_to_offset(btn_event_np);
+		for (prop_offset = fdt_first_property_offset(fdt, node_offset);
+	    	prop_offset > 0;
+			prop_offset = fdt_next_property_offset(fdt, prop_offset)) {
+				value = fdt_getprop_by_offset(fdt, prop_offset,
+					      &propname, &len);			
+				if (!value)
+					continue;
+				/* skip if the property is the action cmd string */
+				len = strlen(propname);
+				if (strncmp(&propname[len-4], "_cmd", 4) == 0)
+					continue;
+
+			if (read_button_event_action_params(btn_event_np, propname,
+				&timeout, &param))
+				continue;
+
+			if (register_button_event_action(button_name, btn_event_np, hook,
+				timeout, param))
+				return -ENOENT;
+			else
+				num_action++;
+		}
+	}
+
+	return num_action;
+}
+
+static int bcmbca_button_probe(struct udevice *dev)
+{
+	ofnode btn_np;
+	int ret;
+	int i = 0;
+	struct ofnode_phandle_args params;
+
+	dev_for_each_subnode(btn_np, dev) {
+		memset(&btnInfo[i], 0x0, sizeof(BtnInfo));
+
+		spin_lock_init(&btnInfo[i].lock);
+		strncpy(btnInfo[i].name, ofnode_get_name(btn_np), 32);
+
+		btnInfo[i].btnId = i;
+		btnInfo[i].active = 0;
+		btnInfo[i].events = 0;
+
+		btnInfo[i].poll = btn_poll;
+		btnInfo[i].isDown = btn_is_gpio_btn_down;
+
+		ret = ofnode_parse_phandle_with_args(btn_np, CONSUMER_NAME, NULL, 3, 0,
+									&params);
+		if (ret) {
+			dev_err(dev, "%s property not found ret %d\n", CONSUMER_NAME, ret);
+			continue;
+		}
+
+		ret = uclass_first_device(UCLASS_GPIO, &btnInfo[i].gd.dev);
+		if (ret) {
+			dev_err(dev, "Failed to get GPIO device ret %d\n", ret);
+			return ret;
+		}
+
+		if (params.args[1] & BCA_GPIO_ACTIVE_LOW) {
+			params.args[1] &= ~BCA_GPIO_ACTIVE_LOW;
+			params.args[1] |= GPIO_ACTIVE_LOW;
+		}
+		ret = gpio_xlate_offs_flags(btnInfo[i].gd.dev, &btnInfo[i].gd,
+			&params);
+		if (ret) {
+			dev_err(dev, "gpio_xlate_offs_flags returned failure %d\n", ret);
+			continue;
+		}
+		btnInfo[i].gd.flags |= GPIOD_IS_IN;
+
+		ret = dm_gpio_request(&btnInfo[i].gd, CONSUMER_NAME);
+		if (ret) {
+			dev_err(dev, "Failed to request GPIO %d ret %d\n",
+				btnInfo[i].gd.offset, ret);
+			continue;
+		}
+
+		dm_gpio_set_dir(&btnInfo[i].gd);
+		if (ret) {
+			dev_err(dev, "Failed to set GPIO %d direction ret %d\n",
+				btnInfo[i].gd.offset, ret);
+			continue;
+		}
+
+		ret = register_button_action(ofnode_get_name(btn_np), PRINT_ACT_NAME_UBOOT,
+			btn_hook_print);
+		if (ret < 0) {
+			register_button_action(ofnode_get_name(btn_np), PRINT_ACT_NAME,
+				btn_hook_print);
+		}
+
+		i++;
+		if (i == PB_BUTTON_MAX) {
+			dev_err(dev, "max number %d of button reached!\n", i);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static struct udevice_id const bcmbca_button_of_match[] = {
+	{ .compatible = "brcm,buttons" },
+	{}
+};
+
+U_BOOT_DRIVER(bcmbca_button) = {
+	.name = "bcm-bca-button",
+	.id = UCLASS_NOP,
+	.of_match = bcmbca_button_of_match,
+	.probe = bcmbca_button_probe,
+};
+
+void bcmbca_button_init(void)
+{
+	struct udevice *dev;
+
+	uclass_get_device_by_driver(UCLASS_NOP, DM_GET_DRIVER(bcmbca_button),
+						&dev);
+}
diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c
new file mode 100644
index 0000000000..66da9b63fe
--- /dev/null
+++ b/board/broadcom/bcmbca/board.c
@@ -0,0 +1,256 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include <fdtdec.h>
+#include <dm.h>
+#include <mtd.h>
+#include <cli.h>
+
+#include <asm/sections.h>
+#include <linux/ctype.h>
+#include <stdlib.h>
+#include <string.h>
+#include <environment.h>
+#if defined(CONFIG_ARM64)
+#include <asm/armv8/mmu.h>
+#else
+#include <asm/armv7.h>
+#include <asm/arch/misc.h>
+#endif
+#include "bca_common.h"
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#endif
+#if defined(CONFIG_BCMBCA_BUTTON)
+#include "bcmbca_button.h"
+#endif
+#include <linux/io.h>
+
+#if defined(CONFIG_BCM_BCA_LED)
+void bca_led_probe(void);
+#endif
+
+void bcmbca_xrdp_eth_init(void);
+
+
+#if defined(CONFIG_BCM_BOOTSTATE)
+void bca_bootstate_probe(void);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak void boot_secondary_cpu(unsigned long vector)
+{
+}
+
+__weak int set_cpu_freq(int freqMHz)
+{
+	return 0;
+}
+/* overrideable callback to insert within board _init */
+__weak int board_sdk_init_e(void)
+{
+	return 0;
+}
+
+#if !defined(CONFIG_TPL_ATF) && !defined(CONFIG_ARM64)
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+}
+
+static void __waitloop(void)
+{
+	while(!GPIO->GeneralPurpose)
+		wfi();
+	/* do nonsecure entry */
+	__asm__(".arch_extension sec");
+	__asm__("mov ip, %0" : : "r" (GPIO->GeneralPurpose));
+	__asm__("smc #0");
+}
+
+void(*__waitloop_rel)(void) = (void(*)(void))CONFIG_SMP_PEN_ADDR;
+
+void smp_waitloop(unsigned previous_address)
+{
+#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715
+	u32 acr;
+
+	/* Enable invalidates of BTB for secondary cpu */
+	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+	acr |= 0x1;
+	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
+#endif
+	__waitloop_rel();
+}
+#endif
+
+#if defined(CONFIG_SPI_FLASH) && defined(CONFIG_DM_SPI_FLASH)
+void board_spinor_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	debug("SPI NOR  enabled in configuration, checking for device\n");
+	ret = uclass_get_device_by_driver(UCLASS_SPI_FLASH, DM_GET_DRIVER(spi_flash_std), &dev);
+	if (ret)
+		debug("SPI NOR failed to initialize. (error %d)\n", ret);
+	else
+		mtd_probe_devices();
+}
+#endif
+
+int board_init(void)
+{
+#if !defined(CONFIG_TPL_ATF)
+	unsigned long vector;
+#endif
+	board_sdk_init_e();
+
+#if defined(CONFIG_BCM_BCA_LED)
+	bca_led_probe();
+#endif
+
+#if defined(CONFIG_BCMBCA_PMC)
+	pmc_init();
+#endif
+
+	print_chipinfo();
+#if defined(BUILD_TAG)
+	printf("$Uboot: "BUILD_TAG" $\n");
+#endif
+
+#if !defined(CONFIG_TPL_ATF)
+#if defined(CONFIG_ARM64)
+	vector  = (unsigned long)&_start;
+#else
+	vector  = (unsigned long)_smp_pen;
+	GPIO->GeneralPurpose = 0;
+	memcpy(__waitloop_rel, __waitloop, 0x1000);
+	flush_dcache_range((unsigned long)__waitloop_rel, (unsigned long)__waitloop_rel + 0x1000);	
+#endif
+	boot_secondary_cpu(vector);
+#endif
+#if defined(CONFIG_BCM_BOOTSTATE)
+	bca_bootstate_probe();
+#endif
+#if defined(CONFIG_BCMBCA_BUTTON)
+	bcmbca_button_init();
+	reset_button_init();
+#endif
+#if defined(CONFIG_SPI_FLASH) && defined(CONFIG_DM_SPI_FLASH)
+	board_spinor_init();
+#endif
+	return 0;
+}
+
+int board_fix_fdt(void * fdt_addr)
+{
+	return 0;
+}
+
+void board_nand_init(void)
+{
+	struct udevice *dev;
+	int ret;
+	int device = 0;
+
+#if defined(CONFIG_NAND_BRCMNAND)
+	debug("parallel NAND enabled in configuration, checking for device\n");
+	ret = uclass_get_device_by_driver(UCLASS_MTD, DM_GET_DRIVER(brcm_nand), &dev);
+	if (ret < 0)
+		debug("parallel NAND failed to initialize. (error %d)\n", ret);
+	else
+		device++;
+#endif
+
+#if defined(CONFIG_MTD_SPI_NAND)
+	debug("SPI NAND enabled in configuration, checking for device\n");
+	ret = uclass_get_device_by_driver(UCLASS_MTD, DM_GET_DRIVER(spinand), &dev);
+	if (ret < 0)
+		debug("SPI NAND failed to initialize. (error %d)\n", ret);
+	else
+	{
+		struct mtd_info *mtd = dev_get_uclass_priv(dev);
+		nand_register(device, mtd);
+	}
+#endif
+
+}
+__weak int ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+
+__weak int board_sdk_late_init_e(void)
+{
+	return 0;
+}
+
+__weak int board_sdk_late_init_l(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	board_sdk_late_init_e();
+
+	init_cli_cb_arr();
+	cli_jobs_cb = run_cli_jobs;
+	
+#ifdef CONFIG_BCMBCA_XRDP_ETH
+	register_cli_job_cb(0, bcmbca_xrdp_eth_init);
+#endif
+
+#if defined(CONFIG_BCMBCA_BUTTON)
+	register_cli_job_cb(100, btn_poll);
+#endif
+	board_sdk_late_init_l();
+	return 0;
+}
+
+
+/* FIXME FIXME FIXME 
+ * This file has a few things that are common to spl and tpl ( move to board_spltpl.c )
+ * and a few things that are universal to uboot on bcmbca devices (keep here)
+ * and a few things that are specific to the reference SDK's conventions for environment, flash layout, etc..  (move to bcmbca_uboot.c)
+ */
+
+__weak hook_dram_init(void)
+{
+}
+
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		printf("fdtdec_setup_mem_size_base() has failed\n");
+	else {
+	hook_dram_init();
+#if defined(CONFIG_ARM64)
+		/* update memory size in mmu table*/
+		mem_map[0].virt = mem_map[0].phys = gd->ram_base;
+		mem_map[0].size = gd->ram_size;
+#endif
+	}
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	hook_dram_init();
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	return 0;
+}
+
+__weak void board_mtdparts_default(const char **mtdids, const char **mtdparts)
+{
+}
diff --git a/board/broadcom/bcmbca/board_ikos.c b/board/broadcom/bcmbca/board_ikos.c
new file mode 100644
index 0000000000..798754fabf
--- /dev/null
+++ b/board/broadcom/bcmbca/board_ikos.c
@@ -0,0 +1,150 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <common.h>
+#include <image.h>
+#include <spl.h>
+#include "tpl_params.h"
+#include "bcm_secure.h"
+#include "boot_blob.h"
+#include "otp_map_cmn.h"
+#ifdef CONFIG_ARMV7_NONSEC
+#include <asm/armv7.h>
+#include <asm/secure.h>
+#endif
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+typedef void __noreturn(*image_entry_t) (void *);
+
+/* Override function for ikos implementation */
+
+#if defined(CONFIG_SPL_BUILD)
+
+#if defined(CONFIG_TPL_BUILD)
+int tpl_ram_load_image(struct spl_image_info *spl_image,
+			  struct spl_boot_device *bootdev)
+{
+	printf("ikos set tpl image entry to u-boot directly\n");
+
+	spl_image->os = IH_OS_U_BOOT;
+	spl_image->entry_point = (image_entry_t)CONFIG_SYS_TEXT_BASE;
+
+	return 0;
+}
+
+int get_raw_metadata(void *buffer, struct ubispl_info *info, int n)
+{
+	return 0;
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_RAM;
+}
+
+SPL_LOAD_IMAGE_METHOD("RAM", 0, BOOT_DEVICE_RAM, tpl_ram_load_image);
+#else
+void start_tpl(tpl_params *parms)
+{ 
+	typedef void __noreturn(*image_entry_t) (void *);
+	image_entry_t image_entry =
+		(image_entry_t) CONFIG_TPL_TEXT_BASE;
+	void *new_params = (void*)TPL_PARAMS_ADDR;
+
+	memcpy(new_params, parms, sizeof(tpl_params));
+
+	cleanup_before_linux();
+	image_entry((void *)new_params);
+}
+
+void * load_spl_env(void *buffer)
+{
+}
+#endif
+
+int nand_is_bad_block(unsigned int blk)
+{
+	/* simulatioin/ikos enironment does not support spare area */
+	return 0;
+}
+
+void early_abort(void)
+{
+
+}
+#else
+
+int last_stage_init(void)
+{
+#ifdef CONFIG_ARM64
+
+#else
+	unsigned long machid = 0xffffffff;
+#ifdef CONFIG_MACH_TYPE
+	machid = CONFIG_MACH_TYPE;
+#endif
+	printf("Booting Linux...\n");
+
+	armv7_init_nonsec();
+	cleanup_before_linux();
+	secure_ram_addr(_do_nonsec_entry)((void*)0x00108000,
+					0, machid, 0x03000000);
+#endif
+
+    return 0;
+}
+
+void *board_fdt_blob_setup(void)
+{
+	/* DTB is backdoor loaded */
+	return (void *)0x03000000;
+}
+
+uint32_t env_boot_magic_search_size(void)
+{
+	return 256*1024;
+}
+
+static int do_linux_ikos(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	run_command("env set -f fdt_high 0xFFFFFFFFFFFFFFFF", 0);
+	/* back door load fit image at 0x3000000 in IKOS*/
+	run_command("bootm 0x3000000#conf_linux", 0);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	boot_linux_ikos,	1,	1,	do_linux_ikos,
+	"IKOS boot linux from backdoor loaded fit image ",
+	""
+);
+
+#endif
+
+otp_hw_cmn_err_t  otp_hw_read(otp_hw_cmn_t *dev, 
+				u32 addr,
+				otp_hw_cmn_row_conf_t* row_conf,
+				u32* data,
+				u32 size)
+{
+	*data = 0;
+	return 0;
+}
+
+void bcm_sec_init(void)
+{
+}
+
+int bcm_sec_do(bcm_sec_ctx_t ctx, bcm_sec_cb_arg_t arg[SEC_CTRL_ARG_MAX])
+{
+	return 0;
+}
+
+#if !defined(CONFIG_SYS_ARCH_TIMER)
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
+#endif
diff --git a/board/broadcom/bcmbca/board_sdk.c b/board/broadcom/bcmbca/board_sdk.c
new file mode 100644
index 0000000000..88756b9560
--- /dev/null
+++ b/board/broadcom/bcmbca/board_sdk.c
@@ -0,0 +1,462 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+
+
+#include <linux/ctype.h>
+#include <mtd.h>
+#include <stdlib.h>
+#include <string.h>
+#include <environment.h>
+#include <cli.h>
+#include "bca_common.h"
+#include "bcm_bootstate.h"
+#include "httpd/bcmbca_net.h"
+#include <bca_sdk.h>
+#include "bcm_secure.h"
+#include "bcm_otp.h"
+
+void bcmbca_xrdp_eth_init(void);
+int board_init_flash_parts(int erase_img_part);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+
+typedef struct _bcm_board_fixup_fdt_data_ {
+	char node[512];
+	char prop[512];
+	size_t size;
+	char val[1];
+} bcm_board_fixup_fdt_data_t;
+
+
+
+static bcm_board_fixup_fdt_data_t**  __fdt_fixup_tbl; 
+static bcm_board_fixup_fdt_data_t**  __fdt_fixup_tbl_end; 
+
+static void bcm_board_fdt_fixup_release(void)
+{
+	bcm_board_fixup_fdt_data_t **tbl = __fdt_fixup_tbl;
+	assert(__fdt_fixup_tbl_end || __fdt_fixup_tbl_end);
+	while((unsigned long)tbl < (unsigned long)__fdt_fixup_tbl_end) {
+		if (*tbl) {
+			free(*tbl);
+		}
+		tbl++;
+	}
+	free(__fdt_fixup_tbl);
+	__fdt_fixup_tbl = NULL;
+	__fdt_fixup_tbl_end = NULL;
+}
+
+static int bcm_board_fdt_fixup_set(const char* node, 
+		const char* prop,
+		void* val,
+		unsigned int	size)
+{
+	int rc = -1;
+	void * new_ptr;
+	unsigned int tbl_len;
+	bcm_board_fixup_fdt_data_t * fdt_dat; 
+	assert (strlen(node) < 512 && strlen(prop) < 512);
+	tbl_len = (!__fdt_fixup_tbl)? 0 : 
+				(__fdt_fixup_tbl_end -__fdt_fixup_tbl);
+	new_ptr = realloc(__fdt_fixup_tbl, 
+			sizeof(bcm_board_fixup_fdt_data_t*) * (tbl_len + 1));
+	if (!new_ptr) {
+		goto __out_of_mem;
+	}
+	__fdt_fixup_tbl = new_ptr;
+	__fdt_fixup_tbl_end = __fdt_fixup_tbl + tbl_len;
+
+	fdt_dat = (bcm_board_fixup_fdt_data_t*)malloc(
+					sizeof(bcm_board_fixup_fdt_data_t)+size);
+	if (!fdt_dat) {
+		goto __out_of_mem;
+	}
+	memset(fdt_dat, 0, sizeof(bcm_board_fixup_fdt_data_t) + size);
+	memcpy(fdt_dat->val, val, size);
+	strncpy(fdt_dat->node, node, 512);
+	strncpy(fdt_dat->prop, prop, 512);
+	fdt_dat->size = size;
+	*__fdt_fixup_tbl_end++ = fdt_dat;
+	rc = 0;
+__out_of_mem:
+	return rc;
+}
+
+int bcm_board_boot_fit_fdt_fixup(void* fdt)
+{
+	int rc = -1, off = 0, len = 0;
+	const char* val;
+	uint32_t  ui_val;
+	if (!fdt) {
+		goto err;
+	}
+	off = fdt_path_offset(fdt, "/brcm_sec_hashes/rootfs/hash-1");
+	if (off < 0) {
+		if(bcm_sec_state() == SEC_STATE_UNSEC) {
+			return 0; 
+		}
+		goto err;
+	}
+	val = fdt_getprop(fdt, off, "value", &len);
+	if (bcm_board_fdt_fixup_set("/", BRCM_ROOTFS_SHA256_PROP, val, len)) {
+		goto err;
+	}
+	off = fdt_path_offset(fdt, "/brcm_sec_hashes/rootfs");
+	if (off < 0) {
+		goto err;
+	}
+	val = fdt_getprop(fdt, off, "size", &len);
+	/*the value returned as be  BE. Must turn to cpu */
+	ui_val = fdt32_to_cpu(*(uint32_t*)val);
+	if (bcm_board_fdt_fixup_set("/", BRCM_ROOTFS_IMGLEN_PROP, &ui_val, len)) {
+		goto err;
+	}
+	rc = 0;
+err:
+	if (rc) {	
+		printf("ERROR:Unable to add a fixup to FDT\n");
+		bcm_board_fdt_fixup_release();
+	}
+	return rc;
+}
+
+int bcm_board_boot_bootstate_fdt_fixup(void* fdt)
+{
+	int rc = -1, node = 0, len = 0;
+	int *val = NULL;
+
+	if (!gd->fdt_blob)
+	{
+		goto error;
+	}
+
+	node = fdt_path_offset(gd->fdt_blob, "/chosen");
+	if (node < 0)
+	{
+		goto error;
+	}
+
+	val = (int *)fdt_getprop(gd->fdt_blob, node, "active_image", &len);
+	if (!val || !*val)
+	{
+		goto error;
+	}
+
+	if (bcm_board_fdt_fixup_set("/chosen", "active_image", val, len))
+	{
+		goto error;
+	}
+
+	rc = 0;
+error:
+	if (rc)
+	{
+		printf("ERROR:Unable to add bootstate fixup to FDT\n");
+		bcm_board_fdt_fixup_release();
+	}
+	return rc;
+}
+
+// add to this function all fixups we need before booting 
+// to linux (for now).
+// FIT is an input fdt if ignored then it is ommitted 
+int bcm_board_boot_fdt_fixup(void* fdt)
+{
+	int rc = bcm_board_boot_fit_fdt_fixup(fdt) | bcm_board_boot_bootstate_fdt_fixup(fdt);
+	return rc;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+//uboot callback  
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc = 0;
+	bcm_board_fixup_fdt_data_t *fdt_data;
+	bcm_board_fixup_fdt_data_t **tbl = __fdt_fixup_tbl;
+	assert(__fdt_fixup_tbl || __fdt_fixup_tbl_end);
+	while((unsigned long)tbl < (unsigned long)__fdt_fixup_tbl_end) {
+		if (*tbl) {
+			fdt_data = *tbl;
+			rc |= fdt_find_and_setprop(blob, fdt_data->node, fdt_data->prop,
+				fdt_data->val, fdt_data->size, 1);
+		}
+		tbl++;
+	}
+	return rc; 
+}
+#endif
+#if defined(CONFIG_BCM_BOOTSTATE)
+static void bcmbca_bootstate_reached_uboot(void)
+{
+    bcmbca_clear_boot_reason();
+    unregister_cli_job_cb(bcmbca_bootstate_reached_uboot);
+}
+#endif
+
+#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
+
+#define LINUX_NAND_MTD_ID		"brcmnand.0"
+#define LINUX_SPINAND_MTD_ID		"spi1.0"
+#define UBOOT_NAND_MTD_ID		"nand0"
+#define LINUX_SPINOR_MTD_ID "spi-nor.0"
+
+static char bcmbca_def_mtd_ids[128] = {0};
+static char bcmbca_def_mtd_parts[512] = {0};
+static char bcmbca_linux_mtd_ids[128] = {0};
+
+void board_mtdparts_default(const char **mtdids, const char **mtdparts)
+{
+	/* use first mtd device as default.  For nand and spi nand driver,
+	 * u-boot uses nand0, nand1 and etc as its mtd id
+	 */
+	struct mtd_info *mtd = get_mtd_device_nm(UBOOT_NAND_MTD_ID);
+	if (!IS_ERR_OR_NULL(mtd)) {
+		/* check driver name to see if it is spi nand or parallel nand */
+		if (strcmp(mtd->dev->driver->name, "spi_nand") == 0) {
+   			sprintf(bcmbca_def_mtd_ids, "nand0=%s", LINUX_SPINAND_MTD_ID);
+			sprintf(bcmbca_def_mtd_parts, "%s:%lld(loader)", 
+				LINUX_SPINAND_MTD_ID, (long long)env_boot_magic_search_size());
+			sprintf(bcmbca_linux_mtd_ids, "%s", LINUX_SPINAND_MTD_ID);
+		} else if (strcmp(mtd->dev->driver->name, "brcm-nand") == 0) {
+   			sprintf(bcmbca_def_mtd_ids, "nand0=%s", LINUX_NAND_MTD_ID);
+			sprintf(bcmbca_def_mtd_parts, "%s:%lld(loader)", 
+				LINUX_NAND_MTD_ID, (long long)env_boot_magic_search_size());
+			sprintf(bcmbca_linux_mtd_ids, "%s", LINUX_NAND_MTD_ID);
+		} else {
+			printf("Unsupported driver %s!\n", mtd->dev->driver->name);
+			return;
+		}
+	} else {
+		mtd = get_mtd_device_nm(SPIFLASH_MTDNAME);
+		if (!IS_ERR_OR_NULL(mtd)) {
+  			sprintf(bcmbca_def_mtd_ids, "nor0=%s", LINUX_SPINOR_MTD_ID);
+			sprintf(bcmbca_def_mtd_parts, "%s:%lld(loader)", 
+				LINUX_SPINOR_MTD_ID, (long long)env_boot_magic_search_size());
+			put_mtd_device(mtd);
+		}
+	}
+	*mtdids = bcmbca_def_mtd_ids;
+	*mtdparts = bcmbca_def_mtd_parts;
+}
+#endif
+
+#ifdef CONFIG_BCMBCA_UPDATE_MCB_IN_ENV
+#include "spl_ddrinit.h"
+
+static int update_memcfg(void)
+{
+
+	if (env_get("boardid") == NULL)
+		printf("ERROR: boardid is not defined in uboot environment \nPlease use uboot command \'setenv boardid [board name]\' to set boardid\n");
+	else
+	{
+		const uint32_t* memcfg;
+		uint32_t fdt_mcb, env_mcb;
+		int offset = fdt_path_offset(gd->fdt_blob, "/memory_controller");
+		if (offset < 0)
+		{
+			printf("Can't find /memory_controller node in board Device Tree\n");
+			return -1;
+		}
+		memcfg = fdt_getprop(gd->fdt_blob, offset, "memcfg", NULL);
+		if (memcfg == NULL)
+		{
+			printf("Can't find memcfg parameter in Device Tree\n");
+			return -1;
+		}
+		fdt_mcb = be32_to_cpu(*memcfg);
+		env_mcb = env_get_hex("MCB", 0);
+
+		if (!env_mcb || ((fdt_mcb!=env_mcb) && !(env_mcb&BP_DDR_CONFIG_OVERRIDE)))
+		{
+			printf("Updating MCB environment from 0x%x to 0x%x\n", env_mcb, fdt_mcb);
+			env_set_hex("MCB", fdt_mcb);
+			env_save();
+			printf("Memory Configuration Changed -- REBOOT NEEDED\n");
+		}
+	}
+
+	return 0;
+}
+#endif
+
+int board_sdk_late_init_e(void)
+{
+	bcm_sec_init();
+	bcm_sec_cb_arg_t cb_args[SEC_CTRL_ARG_MAX] = {0};
+	cb_args[SEC_CTRL_ARG_KEY].arg[0].ctrl = SEC_CTRL_KEY_GET;
+	cb_args[SEC_CTRL_ARG_KEY].arg[1].ctrl = SEC_CTRL_KEY_CHAIN_RSA;
+	cb_args[SEC_CTRL_ARG_KEY].arg[1].ctrl_arg = (void*)gd->fdt_blob;
+	cb_args[SEC_CTRL_ARG_KEY].arg[2].ctrl = SEC_CTRL_KEY_CHAIN_AES;
+	cb_args[SEC_CTRL_ARG_KEY].arg[2].ctrl_arg = (void*)gd->fdt_blob;
+	bcm_sec_do(SEC_SET, cb_args);
+#if 0 
+	bcm_sec_key_arg_t* _keys;
+	bcm_sec_get_active_aes_key(&_keys);
+	if (_keys) {
+		int i;
+		for (i = 0; i < _keys->len; i++ ) {
+			printf("Got key %s %llx %llx %llx %llx \n",_keys->aes[i].id, 
+						((u64*)_keys->aes[i].key)[0],
+						((u64*)_keys->aes[i].key)[1],
+						((u64*)_keys->aes[i].key)[2],
+						((u64*)_keys->aes[i].key)[3]);
+		}
+
+	}
+#endif
+	printf("Now we are in UBOOT proper\n");
+
+	return 0;
+}
+
+int board_sdk_init_e(void)
+{
+	if (bcm_otp_init()) {
+		hang();
+	}
+}
+
+int board_sdk_late_init_l(void)
+{
+	char *cp;
+	int node, len;
+
+#ifdef CONFIG_BCMBCA_UPDATE_MCB_IN_ENV
+	update_memcfg();
+#endif
+
+#ifdef CONFIG_BCMBCA_HTTPD
+	if(!httpd_check_net_env())
+		register_cli_job_cb(0, http_poll);
+#endif
+
+#if defined(CONFIG_BCM_BOOTSTATE)
+	register_cli_job_cb(0, bcmbca_bootstate_reached_uboot);
+#endif
+
+	node = fdt_path_offset(gd->fdt_blob, "/chosen");
+	if (node < 0) {
+		printf("Can't find /chosen node in cboot DTB\n");
+		return node;
+	}
+	cp = (char *)fdt_getprop(gd->fdt_blob, node, "boot_device", &len);
+	if (cp) { 
+		printf("boot_device is %s\n",cp);
+	}
+
+	board_init_flash_parts(0);
+
+	return(0);
+}
+
+int board_init_flash_parts(int erase_img_part)
+{
+	char *cp;
+	char *media = NULL;
+	int n = 0;
+	int ret = -1;
+#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_GPT)
+	cp = env_get("IMAGE");
+	if (NULL != cp)
+	{
+		unsigned long iargs[4];
+		char units[4];
+		n =  parse_env_string_plus_nums(cp, &media, 4, iargs, units);
+#ifdef CONFIG_CMD_MTDPARTS
+		if( strcasecmp(media, FLASH_DEV_STR_NAND) == 0 ) {
+			char *mparts;
+			int ncommas = 0;
+			mparts = env_get("mtdparts");
+			while (mparts && (*mparts != '\0')) {
+				/* count the commas in mtdparts */
+				if (*mparts == ',') {
+					ncommas++;
+				}
+				mparts++;
+			}
+			/* only update mtdparts from IMAGE if IMAGE is specified and mtdparts has 0 or 1  
+			 * commas -- either 1 or 2 devices defined */
+			if ((ncommas < 2 ) && ((n == 3) || (n == 2))) {
+				char cmd[64];
+				struct mtd_info *mtd;
+				long long image_start;
+				long long image_max;
+				long long image_end = 0;
+				image_start = ((long long)iargs[0]) << suffix2shift(units[0])  ;
+				if ( n == 3) {
+					image_end = ((long long)iargs[1]) << suffix2shift(units[1])  ;
+				}
+				mtd_probe_devices();
+				mtd = get_mtd_device_nm("nand0");
+				if (IS_ERR_OR_NULL(mtd))
+				{
+					printf("cant get mtd nand0\n");
+				}
+				image_max = mtd->size - 8 * mtd->erasesize;
+				put_mtd_device(mtd);
+				if ((n == 2)  || (image_end < 1) || (image_end > image_max)) {
+					image_end = image_max;
+					printf("adjusted to skip last 8 blocks\n");
+				}
+
+				/* Initialize mtd parts */
+				printf("image in %s from %lld to %lld\n",media,image_start,image_end);
+				run_command("mtdparts delall",0);
+
+				/* Set key mtd env variables */
+				env_set("mtdids", bcmbca_def_mtd_ids);
+				sprintf(cmd, "%s:%lld(loader),%lld@%lld(image)",
+					bcmbca_linux_mtd_ids,
+					image_start,
+					image_end-image_start,
+					image_start);
+				env_set("mtdparts", cmd);
+				run_command("mtdparts",0);
+
+				/* erase image partition if required */
+				if (erase_img_part) {
+					printf("WARNING: Erasing image partition!\n");
+					sprintf(cmd,"mtd erase image");
+					run_command(cmd,0);
+				}
+				ret = 0;
+			}
+		}
+#endif /* CONFIG_CMD_MTDPARTS */		
+
+#ifdef CONFIG_CMD_GPT
+		if( strcasecmp(media, FLASH_DEV_STR_EMMC) == 0 ) {
+			/* Setup default partitions */
+			char * partitions = NULL;
+			if( run_command("env exists default_partitions",0) == 0 ) {
+				run_command("part list mmc 0 curr_parts",0);
+				partitions=env_get("curr_parts");
+				if( (strlen(partitions) <= 1) || erase_img_part) {
+					if( erase_img_part )
+						printf("WARNING: Reformatting eMMC image partitions!\n");
+					else						
+						printf("Bootstrap Image Detected!, Setting default eMMC partitions!\n");
+
+					run_command("gpt write mmc 0 $default_partitions", 0);
+					run_command("gpt verify mmc 0 $default_partitions", 0);
+				}
+				ret = 0;
+			}
+		}
+#endif /* CONFIG_CMD_GPT */		
+		free(media);
+	}
+#endif
+	return ret;
+}
+
diff --git a/board/broadcom/bcmbca/board_secure.c b/board/broadcom/bcmbca/board_secure.c
new file mode 100644
index 0000000000..1a9eea15ff
--- /dev/null
+++ b/board/broadcom/bcmbca/board_secure.c
@@ -0,0 +1,499 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+#include <common.h>
+#include <wdt.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <linux/errno.h>
+#include <asm/unaligned.h>
+#include <malloc.h>
+#include "u-boot/rsa.h"
+#include "u-boot/rsa-mod-exp.h"
+#include <u-boot/sha256.h>
+#include <uboot_aes.h>
+#include "bcm_secure.h"
+#include "bcm_otp.h"
+#include <watchdog.h>
+
+
+/* callback can be called early in before relocation and 
+ * before bss zero loop */
+static bcm_sec_t s_bcm_sec __attribute__((section(".data"))) = {0};
+
+
+static inline void copy_append(bcm_sec_ctrl_arg_t* d, bcm_sec_ctrl_arg_t* s, u32 len)
+{
+		int i,j;
+		for(i = 0; i < len; i++) {
+			if (!s[i].ctrl) {
+				continue;	
+			}
+			for(j = 0; j < len; j++) {
+				if ( (u32)d[j].ctrl == (u32)s[i].ctrl ||
+						!((u32)d[j].ctrl) ) {
+					d[j].ctrl = s[i].ctrl;
+					d[j].ctrl_arg = s[i].ctrl_arg;
+					break;
+				}
+			} 
+		}
+}
+ 
+
+static void bcm_sec_set_args(bcm_sec_t *sec, bcm_sec_cb_arg_t args[SEC_CTRL_ARG_MAX])
+{
+	int i;
+	for (i = 0; i < SEC_CTRL_ARG_MAX; i++) {
+ 		copy_append(sec->cb[i].arg, 
+			args[i].arg, SEC_CTRL_RUN_ORDER_MAX);
+	}
+}
+
+
+
+static bcm_sec_ctrl_arg_t* bcm_sec_get_ctrl_arg(bcm_sec_t* sec, 
+			bcm_sec_ctrl_arg_t* ctrl,
+			bcm_sec_ctrl_arg_num_t ctrl_id)
+{
+	int i;
+	bcm_sec_ctrl_arg_t *c; 
+	bcm_sec_ctrl_arg_t *res = NULL;
+	c = sec->cb[ctrl_id].arg;
+	for(i = 0; i < SEC_CTRL_RUN_ORDER_MAX; i++) {
+		if (!c[i].ctrl) {
+			continue;	
+		}
+		if ( (u32)c[i].ctrl == (u32)ctrl->ctrl) {
+			res = &c[i];
+			break;
+		}
+	}
+	return res;
+}
+
+int	bcm_sec_update_ctrl_arg(bcm_sec_ctrl_arg_t* arg,
+			bcm_sec_ctrl_arg_num_t ctrl)
+{
+	bcm_sec_ctrl_arg_t *_arg = bcm_sec_get_ctrl_arg(bcm_sec(), arg, ctrl);
+	if (!_arg) {
+		return -1; 
+	}
+	if (ctrl == SEC_CTRL_ARG_KEY && ( 
+		(_arg->ctrl == SEC_CTRL_KEY_CHAIN_AES) || (_arg->ctrl == SEC_CTRL_KEY_CHAIN_ENCKEY) || (_arg->ctrl == SEC_CTRL_KEY_EXPORT_ITEM)) ) {
+		((bcm_sec_key_arg_t*)_arg->ctrl_arg)->arg = arg->ctrl_arg;
+	} else { 
+		_arg->ctrl_arg = arg->ctrl_arg;
+	}  
+	return 0;
+}
+
+/* based on the content of theotp field returns state - unsec, mfg or fld*/
+static int bcm_sec_boot_state(bcm_sec_state_t* sec_state)
+{
+	otp_hw_ctl_data_t ctl_data = { 
+		.addr = SOTP_MAP_FLD_ROE,
+		.status = OTP_HW_CMN_STATUS_ROW_DATA_VALID
+	};
+	otp_hw_cmn_ctl_cmd_t cmd = {
+		.ctl = OTP_HW_CMN_CTL_STATUS ,
+		.data = (uintptr_t)&ctl_data, 
+		.size = sizeof(ctl_data)
+	};
+	int rc = -1;
+	u32 *btrm_en = NULL,
+		*btrm_cust_en = NULL,
+		*cust_mid = NULL, size = 0, res = 0;
+	*sec_state = SEC_STATE_UNSEC;
+	if (bcm_otp_read(OTP_MAP_CUST_BTRM_BOOT_ENABLE, &btrm_cust_en, &size) ||
+		bcm_otp_read(OTP_MAP_BRCM_BTRM_BOOT_ENABLE, &btrm_en, &size) ||
+		bcm_otp_read(OTP_MAP_CUST_MFG_MRKTID, &cust_mid, &size)) {
+		goto err;	
+	}
+	if ( !(*btrm_en) ||  !(*btrm_cust_en)) {
+		goto done;	
+	}
+	*sec_state = SEC_STATE_GEN3_MFG;
+	if ( !(*cust_mid) ) {
+		goto done;
+	}
+
+	if (bcm_otp_ctl(BCM_SOTP_MAP, &cmd, &res)) {
+		goto err;	
+	}
+	if (!(res&OTP_HW_CMN_STATUS_ROW_DATA_VALID) ) {
+		/*printf("%s ek: 0x%x \n",__FUNCTION__,*(u32*)BCM_SECBT_CRED_AES);*/
+		if (!*((u32*)BCM_SECBT_CRED_AES)) {
+			goto done;
+		}
+	}
+	res = 0;
+	ctl_data.addr = SOTP_MAP_FLD_HMID;
+	if (bcm_otp_ctl(BCM_SOTP_MAP, &cmd, &res)) {
+		goto err;	
+	}
+	if (!(res&OTP_HW_CMN_STATUS_ROW_DATA_VALID)) {
+		/*printf("%s pub: 0x%x \n",__FUNCTION__,*(u32*)BCM_SECBT_CRED_MOD);*/
+		if (! *((u32*)BCM_SECBT_CRED_MOD)) { 
+			goto done;
+		}
+	}
+	*sec_state = SEC_STATE_GEN3_FLD;
+done:
+	rc = 0;
+err:
+	return rc;	
+}
+
+int bcm_sec_set_sec_ser_num( char * ser_num, u32 ser_num_size)
+{
+	int rc = -1;
+
+	/* Commit the new secure serial number to S/OTP */
+	rc = bcm_otp_write(SOTP_MAP_SER_NUM, ser_num, ser_num_size);
+	if(rc) {
+		printf("%s: ERROR! Failed to commit secure serial number! rc:%d\n", __FUNCTION__, rc);
+	}
+	return rc;
+}
+
+int bcm_sec_get_sec_ser_num( char * ser_num, u32 ser_num_size)
+{
+	int rc = -1;
+	u32 * pdata = NULL;
+	u32 size = 0;
+	u32 num_words = 0;
+
+	/* Get secure serial number fields from S/OTP */
+	rc = bcm_otp_read(SOTP_MAP_SER_NUM, &pdata, &size);
+
+	if( rc == OTP_HW_CMN_ERR_KEY_EMPTY )
+	{
+		memset(ser_num, 0x0, ser_num_size);
+		return OTP_HW_CMN_OK;
+	}
+
+	/* If retrieval fails, check dtb for exported value */
+	if( rc ) {
+		int node;
+		node = fdt_path_offset(gd->fdt_blob, "/trust/serial_num");
+		if (node >= 0) {
+			char * cp = NULL;
+			cp = (char *)fdt_getprop(gd->fdt_blob, node, "value", &size);
+			if (cp) {
+				memcpy(ser_num, cp, (size>ser_num_size?ser_num_size:size));
+				rc = 0;
+			}
+		}
+		if(rc) {
+			printf("%s: ERROR! Failed to retrieve secure serial number! rc:%d\n", __FUNCTION__, rc);
+		} 
+	} else {
+		memcpy(ser_num, pdata, (size>ser_num_size?ser_num_size:size));
+	}
+	return rc;
+}
+
+int bcm_sec_set_dev_spec_key( char * dev_spec_key, u32 dev_spec_key_size)
+{
+	int rc = -1;
+
+	/* Commit the new device specific key to S/OTP */
+	rc = bcm_otp_write(SOTP_MAP_KEY_DEV_SPECIFIC, dev_spec_key, dev_spec_key_size);
+	if(rc) {
+		printf("%s: ERROR! Failed to commit secure serial number! rc:%d\n", __FUNCTION__, rc);
+	}
+	return rc;
+}
+
+int bcm_sec_get_dev_spec_key( char * dev_spec_key, u32 dev_spec_key_size)
+{
+	int rc = -1;
+	u32 * pdata = NULL;
+	u32 size = 0;
+	u32 num_words = 0;
+
+	/* Get device specific from S/OTP */
+	rc = bcm_otp_read(SOTP_MAP_KEY_DEV_SPECIFIC, &pdata, &size);
+
+	if( rc == OTP_HW_CMN_ERR_KEY_EMPTY )
+	{
+		memset(dev_spec_key, 0x0, dev_spec_key_size);
+		return OTP_HW_CMN_OK;
+	}
+
+	if(rc) {
+		printf("%s: ERROR! Failed to retrieve secure serial number! rc:%d\n", __FUNCTION__, rc);
+	} else {
+		memcpy(dev_spec_key, pdata, (size>dev_spec_key_size?dev_spec_key_size:size));
+	}
+	return rc;
+}
+
+#define ANTI_ROLLBACK_LVL_NUMBITS	2
+#define ANTI_ROLLBACK_LVL_MASK		((1 << ANTI_ROLLBACK_LVL_NUMBITS)-1)
+#define ANTI_ROLLBACK_LVL_SHIFT		ANTI_ROLLBACK_LVL_NUMBITS
+static int bcm_sec_antirollback_lvl_ctl( u32 * lvl, int write )
+{
+	int rc = -1;
+	u32 * pdata = NULL;
+	u32 size = 0;
+	u32 current_lvl = 0;
+	u32 num_lvls_word = sizeof(u32)*8/ANTI_ROLLBACK_LVL_NUMBITS;
+	u32 num_words = 0;
+	u32 i,j,tmp_lvl;
+
+	/* Get anti_rollback fields from S/OTP */
+	rc = bcm_otp_read(SOTP_MAP_ANTI_ROLLBACK, &pdata, &size);
+	if (rc) {
+		printf("%s: ERROR! Failed to retrieve anti-rollback level data! rc:%d\n", 
+			__FUNCTION__, rc);
+		goto finish_read;	
+	}
+
+	/* Calculate level */
+	num_words = size/sizeof(u32);
+	for( i=0; i<num_words; i++ ){
+		for( j=0; j<num_lvls_word; j++) {
+			if( pdata[i] & (ANTI_ROLLBACK_LVL_MASK << (j*ANTI_ROLLBACK_LVL_SHIFT))) {
+				current_lvl++;
+			} else {
+				goto finish_read;
+			}
+		}
+	}
+
+finish_read:
+	if( write ) {
+		tmp_lvl = *lvl;
+		/* Do boundary checks on requested level */
+		if( tmp_lvl <= current_lvl ) {
+			printf("%s: ERROR! Requested anti-rollback level %d is lower than current %d\n", __FUNCTION__, tmp_lvl, current_lvl);
+			rc = -1;
+			goto finish;
+		}
+		if( tmp_lvl > num_words * num_lvls_word ) { //FIXME BOUNDARY
+			printf("%s: ERROR! Requested anti-rollback level %d is higher than maximum %d\n", __FUNCTION__, tmp_lvl, num_words * num_lvls_word );
+			rc = -1;
+			goto finish;
+		}
+
+		/* Encode new rollback level */
+		for( i=0; i<num_words; i++ ){
+			/* Batch fill the row if level exceeds it */
+			if( tmp_lvl >= num_lvls_word )
+			{
+				/* adjust level */
+				tmp_lvl -= num_lvls_word;
+
+				/* If current word is filled continue to next word */
+				if( pdata[i] == 0xFFFFFFFF )
+					continue;
+				else
+					pdata[i] = 0xFFFFFFFF;
+			}
+			else
+			{
+				/* Selectively fill the row according to level */
+				while( tmp_lvl )
+				{
+					pdata[i] |= ANTI_ROLLBACK_LVL_MASK << ((tmp_lvl-1)*ANTI_ROLLBACK_LVL_SHIFT);
+					tmp_lvl--;
+				}
+			}
+			if( tmp_lvl == 0 )
+				break;
+		}
+
+		/* Commit the new anti-rollback level to S/OTP */
+		rc = bcm_otp_write(SOTP_MAP_ANTI_ROLLBACK, pdata, size);
+		if(rc) {
+			printf("%s: ERROR! Failed to commit anti-rollback level data! rc:%d\n", __FUNCTION__, rc);
+			goto finish;	
+		}
+	} else {
+		*lvl = current_lvl;
+	}
+finish:
+	return rc;
+}
+
+int bcm_sec_get_antirollback_lvl( u32 * lvl)
+{
+	return(bcm_sec_antirollback_lvl_ctl( lvl, 0 ));
+}
+int bcm_sec_set_antirollback_lvl( u32 lvl)
+{
+	return(bcm_sec_antirollback_lvl_ctl( &lvl, 1 ));
+}
+/* assigns a number to a callback to be run ascending order in bcm_sec_do*/
+static void bcm_set_cb_order(bcm_sec_ctrl_arg_num_t ord_arg[SEC_CTRL_ARG_MAX])
+{
+	bcm_sec_ctrl_arg_num_t *ord = bcm_sec()->ord;
+	if (ord_arg) {
+		memcpy(ord, ord_arg, 
+				SEC_CTRL_ARG_MAX*sizeof(bcm_sec_ctrl_arg_num_t));
+	} else {
+		int i;
+		for (i = 0; i < SEC_CTRL_ARG_MAX; i++) {
+			ord[i] = i;
+		}
+	}
+}
+
+bcm_sec_t* bcm_sec(void)
+{
+	return &s_bcm_sec;
+}
+
+
+bcm_sec_state_t bcm_sec_state(void)
+{
+	return bcm_sec()->state;
+}
+
+void bcm_sec_get_active_aes_key(u8** key)
+{
+	*key = bcm_sec()->key.ek;
+}
+
+void bcm_sec_set_active_aes_key(u8* key)
+{
+	bcm_sec()->key.ek = key;
+}
+
+u8* bcm_sec_get_active_pub_key(void)
+{
+	return bcm_sec()->key.pub;
+}
+
+u8* bcm_sec_set_active_pub_key(u8 * key)
+{
+	bcm_sec()->key.pub = key;
+}
+
+__weak void bcm_sec_clean_secmem(bcm_sec_t* sec)
+{
+
+}
+
+__weak int bcm_sec_btrm_key_info(bcm_sec_t* sec)
+{
+	/* Set root keys */
+	memcpy(sec->key.rsa_pub, (void*)BCM_SECBT_CRED_MOD, 
+			RSA2048_BYTES);
+	memcpy(sec->key.aes_ek, (void*)BCM_SECBT_CRED_AES, 
+			BCM_SECBT_AES_CBC128_EK_LEN); 
+	memcpy(sec->key.aes_ek + BCM_SECBT_AES_CBC128_EK_LEN,  
+		(void*)BCM_SECBT_CRED_AES_IV, BCM_SECBT_AES_CBC128_EK_LEN);
+
+	/* Set active keys */
+	sec->key.pub = sec->key.rsa_pub;
+	sec->key.ek = sec->key.aes_ek;
+
+	/* Clear delegation config */
+	sec->delg_cfg_obj = NULL;
+
+	return 0;	
+}
+
+void bcm_sec_clean_keys(bcm_sec_t* sec)
+{
+	if (sec->key.ek) {
+		memset(sec->key.ek, 0, BCM_SECBT_AES_CBC128_EK_LEN*2);
+	}
+	memset(&sec->key, 0, sizeof(bcm_sec_key_t));
+}
+
+/* should be overridden by the implementation */
+__weak void bcm_sec_cb_init(bcm_sec_t* obj)
+{
+	
+}
+ 
+__weak void bcm_sec_init(void)
+{
+	bcm_sec_t* sec = bcm_sec();
+	bcm_sec_cb_init(sec);
+	bcm_set_cb_order(NULL);	
+	bcm_sec_boot_state(&sec->state);
+	switch (sec->state) {
+		case SEC_STATE_GEN3_MFG:
+			printf("Board is MFG secure\n");
+			break;
+		case SEC_STATE_GEN3_FLD:
+			printf("Board is FLD secure\n");
+			break;
+		default:
+			printf("Board is non secure\n");
+	}
+}
+
+__weak int bcm_sec_do(bcm_sec_ctx_t ctx, bcm_sec_cb_arg_t arg[SEC_CTRL_ARG_MAX])
+{
+	int rc = -1, i, j;
+	bcm_sec_t *sec = bcm_sec();
+	bcm_sec_ctrl_cb_t *__cb; 
+	bcm_sec_ctrl_arg_t *cb_arg;
+	if (arg) {
+		bcm_sec_set_args(sec, arg);
+	}
+	/* This is a 2 step function.  eg SEC_LEVEL_NONE->SEC_LEVEL_INIT->FINAL LEVEL(see below) .
+ 	 */
+	if (ctx & SEC_SCHED_CLR) {
+		sec->sched_ctx =  SEC_NONE;
+		return rc;
+	}
+
+	if (sec->sched_ctx & SEC_SET_SCHED) {
+		/* continuing with schedule level*/
+		ctx = (sec->sched_ctx & (~SEC_SET_SCHED));
+	} else if (ctx & SEC_SET_SCHED) {
+		sec->sched_ctx =  ctx;
+		//debug("SEC *** SCHEDULED \n");
+		return rc;
+	}
+	for (j = 0; j < SEC_CTRL_ARG_MAX; j++) {
+		__cb = &sec->cb[sec->ord[j]];
+		if (!__cb->cb) {
+			continue;
+		}
+		cb_arg = __cb->arg;
+		for (i = 0;  i < SEC_CTRL_RUN_ORDER_MAX; i++) {
+#if DEBUG 
+			if (cb_arg[i].ctrl) {
+				printf("SEC *** DO %d CTRL %d  parm 0x%x\n", j, 
+							cb_arg[i].ctrl,
+							cb_arg[i].ctrl_arg);
+			}
+#endif 
+			if (__cb->cb(sec, cb_arg[i].ctrl, cb_arg[i].ctrl_arg)) {
+				cb_arg[i].ctrl = 0;
+				cb_arg[i].ctrl_arg = NULL;
+				goto err;
+			}
+			cb_arg[i].ctrl = 0;
+			cb_arg[i].ctrl_arg = NULL;
+		} 
+	}
+	sec->curr_ctx = ctx;
+	rc = 0;
+err:
+	return rc;
+}
+
+void bcm_sec_deinit(void)
+{
+	bcm_sec_clean_secmem(&s_bcm_sec);
+	bcm_sec_clean_keys(&s_bcm_sec);
+	memset(&s_bcm_sec, 0, sizeof(bcm_sec_t));
+}
+
+void bcm_sec_abort(void)
+{
+	bcm_sec_deinit();
+	WATCHDOG_RESET();
+	/* we never return if watchdog wasn't enabled */
+	hang();
+}
diff --git a/board/broadcom/bcmbca/board_secure_fit.c b/board/broadcom/bcmbca/board_secure_fit.c
new file mode 100644
index 0000000000..ce4cd46ee8
--- /dev/null
+++ b/board/broadcom/bcmbca/board_secure_fit.c
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <linux/errno.h>
+#include <asm/unaligned.h>
+#include <malloc.h>
+#include "tpl_params.h"
+#include "spl_env.h"
+#include "u-boot/rsa.h"
+#include "u-boot/rsa-mod-exp.h"
+#include <u-boot/sha256.h>
+#include <uboot_aes.h>
+#include <watchdog.h>
+#include "bcm_secure.h"
+
+#define FIT_PAD_MAX_SIZE 0x1000
+#define BCM_TAG_FIT_HDR_SEC_DELG_REC    0x44454c47 // DELG
+#define BCM_TAG_FIT_HDR_SEC_SIGNATURE	0x46495453 // FITS
+#define BCM_TAG_FIT_HDR_SEC_PUBKEY	0x46495450 // FITP
+#define BCM_FIT_HDR_MAX_RECORDS		4	
+#define BCM_FIT_HDR_MIN_HDR_SIZE	(RSA2048_BYTES+sizeof(u32))
+
+ 
+int bcm_tag_fit_hdr_validate(const u8 *fit, u32 size, 
+		u32 hdr_size, u8* master_pub)
+{
+	int rc = -1;
+	u32 tag = 0, cnt = 0;
+	u8 sig[RSA2048_BYTES];
+	u8 *p = (u8*)fit + size;
+	u8 *pmax = p; 
+	u8 key_buf[RSA2048_BYTES];
+	const u8 *key = master_pub;
+	struct image_sign_info im;
+
+#if defined (CONFIG_TPL_BUILD)
+	u32 sdr_plus_sig_size = 0;
+	int sdr_verified = 0;
+#endif 	
+
+	if (hdr_size < BCM_FIT_HDR_MIN_HDR_SIZE) {
+		goto err;
+	}	
+	
+	im.checksum = image_get_checksum_algo("sha256,");
+	if (!im.checksum) {
+		printf("ERROR: couldn't get checksum algo\n"); 
+		goto err;
+	}
+	while (cnt < BCM_FIT_HDR_MAX_RECORDS && (p - pmax) < hdr_size) {
+		memcpy(&tag, p, sizeof(u32));
+		switch ( tag ) {
+#if defined (CONFIG_TPL_BUILD)
+			case BCM_TAG_FIT_HDR_SEC_DELG_REC:
+				rc = bcm_sec_delg_process_sdr(p, pmax+hdr_size-1, &sdr_plus_sig_size);
+				if( rc ) {
+					printf("ERROR: SDR verification failed!\n");
+					return rc;
+				} else {
+					/* SDR valid, swap in new pub key */
+					key = bcm_sec_get_active_pub_key();
+					p += sdr_plus_sig_size; 
+					sdr_verified = 1;
+				}
+			break;
+#endif /* defined (CONFIG_TPL_BUILD) */
+			case BCM_TAG_FIT_HDR_SEC_SIGNATURE:
+				memcpy(sig, p + sizeof(u32), RSA2048_BYTES);
+				debug("\nVerifying Signature; 4 leading bytes 0x%x verifying with key 0x%x\n",*(u32*)sig, *(u32*)key);
+				if (!bcm_sec_rsa_verify(fit, size, sig,  RSA2048_BYTES, key, &im )) {
+					rc = 0;
+#if defined (CONFIG_TPL_BUILD)
+					/* Upon FIT hdr & sdr authentication success, check sec node */
+					if( sdr_verified ) {
+						rc = bcm_sec_delg_process_sec_node(fit);
+						if( rc ) {
+							printf("ERROR: Security Node verification failed!\n");
+						}
+					}
+#endif /* defined (CONFIG_TPL_BUILD) */
+					return rc;
+				}
+				p += sizeof(u32) + RSA2048_BYTES; 
+			break;
+			case BCM_TAG_FIT_HDR_SEC_PUBKEY:
+#if defined (CONFIG_TPL_BUILD)
+				if( !sdr_verified ) 
+#endif					
+				{
+					memcpy(key_buf, p + sizeof(u32), RSA2048_BYTES);
+					memcpy(sig, p + sizeof(u32) + RSA2048_BYTES , RSA2048_BYTES);
+					debug("\nGot Key and Signature, 4 leading bytes: key 0x%x sig 0x%x\n", 
+							*(u32*)key_buf, *(u32*)sig);
+					if (!bcm_sec_rsa_verify(key_buf, RSA2048_BYTES, sig,  RSA2048_BYTES, master_pub, &im )) {
+						key = key_buf; 
+					} else {
+						printf("The key 0x%x can't be verified\n", *(u32*)key_buf);
+					} 
+
+					p += sizeof(u32) + RSA2048_BYTES*2;
+					cnt++; 
+				}
+			break;
+			default:
+				p++;
+		}
+	} 
+err:
+	return rc;
+}
+
+ulong bcm_sec_get_reqd_load_size( void * fit )
+{
+	return( fdt_totalsize(fit) + FIT_PAD_MAX_SIZE );
+}
+
+int bcm_sec_validate_fit(void* fit, u32 max_image_size)
+{
+	int rc = -1;
+	ulong size = fdt_totalsize(fit);
+	bcm_sec_state_t st = bcm_sec_state();
+
+	if (FIT_PAD_MAX_SIZE > max_image_size) {
+		printf("ERROR: FIT image is too short to process\n");
+		goto _die;
+	}
+
+	u8* key = bcm_sec_get_active_pub_key();
+	if (!key) {
+		if((st == SEC_STATE_UNSEC)) {
+			rc = 0;
+		}
+		goto _die;
+	}
+
+	rc = bcm_tag_fit_hdr_validate(fit, size, FIT_PAD_MAX_SIZE, (u8*)key);
+	if (rc) {
+		goto _die;
+	}
+	rc = 0;
+	printf("FIT Header Authentication Successfull!\n");
+_die:
+	if(rc ) {
+		printf("FAILED to authenticate FIT header!!! \n");
+		if(st & SEC_STATE_SECURE) {
+			bcm_sec_abort();
+		} 
+	}
+	return rc; 
+}
+
+u8* bcm_util_get_fdt_prop_data(void* fdt, char* path, char *prop, int* len)
+{
+	u8* d = NULL; 
+	int node = fdt_path_offset (fdt, path);
+	if(node < 0) {
+		debug("ERROR: unable to find path fdt %s \n", path);
+		goto err;
+	} 
+	d = (u8*)fdt_getprop(fdt, node, prop, len);
+	if (!d) {
+		debug("ERROR: unable to get %s\n", prop);
+		goto err;
+	}
+err :
+	return d;
+}
diff --git a/board/broadcom/bcmbca/board_secure_sdk.c b/board/broadcom/bcmbca/board_secure_sdk.c
new file mode 100644
index 0000000000..bf3e3f8c75
--- /dev/null
+++ b/board/broadcom/bcmbca/board_secure_sdk.c
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+#include <common.h>
+#include <wdt.h>
+#include <fdtdec.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <linux/errno.h>
+#include <asm/unaligned.h>
+#include <malloc.h>
+#include "tpl_params.h"
+#include "spl_env.h"
+#include "bcm_secure.h"
+#include "bcm_otp.h"
+#include "u-boot/rsa.h"
+#include "u-boot/rsa-mod-exp.h"
+#include <u-boot/sha256.h>
+#include <uboot_aes.h>
+#include <watchdog.h>
+
+#define NODE_NAME_LEN	128
+
+static int sec_key_ctrl(bcm_sec_t *sec, bcm_sec_ctrl_t ctrl, void* arg)
+{
+	int rc = 0;
+	switch(ctrl) {
+	case SEC_CTRL_KEY_GET:
+		{
+			if ( !(sec->state & SEC_STATE_SECURE)) {
+				u8* env_key = bcm_util_env_var2bin("brcm_pub_testkey", RSA2048_BYTES);
+				/* We've got test key; try to authenticate with it
+ 				* Only works in non-secure mode
+ 				* */
+				if (!env_key) {
+					debug("No Key in environment \n");
+				} else {
+					memcpy(sec->key.rsa_pub, env_key, RSA2048_BYTES);
+					sec->key.pub = sec->key.rsa_pub;
+				} 
+			}
+		}
+		break;
+        case SEC_CTRL_KEY_CHAIN_RSA:
+		if(sec->state & SEC_STATE_SECURE) {
+			int  len = 0;	
+			u8 * k;
+			int off;
+			off = fdt_path_offset(arg, "/trust/brcm_pub_key");
+			if (off < 0) {
+				printf("ERROR: Can't find /trust/brcm_pub_key node in boot DTB!\n");
+			}
+			k = (char*)(fdt_getprop(arg, off, "value", &len));
+			if (!k || len != RSA2048_BYTES) {
+				rc = -1;
+				printf("ERROR: length  %d \n", len);
+				break ;
+			} else {
+				memcpy(sec->key.rsa_pub, k, RSA2048_BYTES);
+				sec->key.pub = sec->key.rsa_pub;
+			}
+
+		} 
+		break;
+       	case SEC_CTRL_KEY_CHAIN_AES:
+		if(sec->state & SEC_STATE_SECURE) {
+			int  len = 0, alloc_len = 0;
+			char *_keys_prop[2] = {FIT_AES1, FIT_AES2};
+			bcm_sec_key_arg_t *aes_arg;
+			int off;
+			u8* aes1,aes2;
+			char key_node[NODE_NAME_LEN];
+
+			/* Get aes1 */
+			snprintf(key_node,NODE_NAME_LEN, "/trust/%s", _keys_prop[0]);
+			off = fdt_path_offset(arg, key_node);
+			if (off < 0) {
+				printf("INFO: Can't find %s node in boot DTB!\n", key_node);
+				break;
+			}
+			aes1 = (char*)(fdt_getprop(arg, off, "value", &len));
+			if (aes1 && len != BCM_SECBT_AES_CBC128_EK_LEN*2) {
+				break;
+			}
+
+			/* Get aes2 */
+			snprintf(key_node,NODE_NAME_LEN, "/trust/%s", _keys_prop[1]);
+			off = fdt_path_offset(arg, key_node);
+			if (off < 0) {
+				printf("INFO: Can't find %s node in boot DTB!\n", key_node);
+				break;
+			}
+			aes2 = (char*)(fdt_getprop(arg, off, "value", &len));
+			if (aes2 && len != BCM_SECBT_AES_CBC128_EK_LEN*2) {
+				break;
+			}
+
+			alloc_len = sizeof(bcm_sec_key_arg_t) + 
+				(aes1 && aes2) ? sizeof(bcm_sec_key_aes_arg_t)*2 : sizeof(bcm_sec_key_aes_arg_t);
+			aes_arg = malloc(alloc_len);
+			if (!aes_arg) {
+		 		break;
+			}
+			memset(aes_arg, 0, alloc_len);
+			if (aes1) {
+				//printf("Got %s 0x%x\n" , _keys_prop[0], *(u32*)aes1);
+				strcpy(aes_arg->aes[aes_arg->len].id,_keys_prop[0]);
+				memcpy(aes_arg->aes[aes_arg->len].key, aes1, BCM_SECBT_AES_CBC128_EK_LEN*2);
+				aes_arg->len++;
+			}
+			if (aes2) {
+				strcpy(aes_arg->aes[aes_arg->len].id, _keys_prop[1]);
+				memcpy(aes_arg->aes[aes_arg->len].key, aes2, BCM_SECBT_AES_CBC128_EK_LEN*2);
+				//printf("Got %s 0x%x\n" , _keys_prop[1], *(u32*)aes2);	
+				aes_arg->len++;
+			}
+			sec->key.ch_ek = aes_arg;
+		}
+		break;
+        case SEC_CTRL_KEY_CLEAN_ALL:
+		bcm_sec_clean_keys(sec);
+		break;
+	default:
+		break;
+	}
+	return rc;
+}
+
+void bcm_sec_cb_init(bcm_sec_t* sec)
+{
+	sec->cb[SEC_CTRL_ARG_KEY].cb = sec_key_ctrl;
+}
diff --git a/board/broadcom/bcmbca/board_secure_spl.c b/board/broadcom/bcmbca/board_secure_spl.c
new file mode 100644
index 0000000000..a67718c2f0
--- /dev/null
+++ b/board/broadcom/bcmbca/board_secure_spl.c
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+#include <common.h>
+#include <wdt.h>
+#include <fdtdec.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <linux/errno.h>
+#include <asm/unaligned.h>
+#include <malloc.h>
+#include "tpl_params.h"
+#include "bcm_secure.h"
+#include "bcm_otp.h"
+#include <asm/arch/rng.h>
+#include "u-boot/rsa.h"
+#include "u-boot/rsa-mod-exp.h"
+#include <u-boot/sha256.h>
+#include <uboot_aes.h>
+
+void bcm_sec_clean_secmem(bcm_sec_t* sec)
+{
+	if ( sec->state & SEC_STATE_SECURE) {
+		memset((void*)bcm_secbt_args(), 0, sizeof(bcm_secbt_args_t));
+	}
+}
+
+/* prevent zerofying by bss loop since we are called early in before relocation*/
+
+static int sec_otp_ctrl(bcm_sec_t* sec, bcm_sec_ctrl_t ctrl, void* arg)
+{
+	switch(ctrl) {
+        case SEC_CTRL_SOTP_LOCK_ALL: 
+/*  
+ * disable sensitive blocks for sec slave 
+ * and non-sec master*/
+		{	
+			if (bcm_sotp_ctl_perm(OTP_HW_CMN_CTL_LOCK,
+				OTP_HW_CMN_CTL_LOCK_ALL, NULL) == OTP_MAP_CMN_ERR_UNSP) {
+				printf("WARNING: lock is not supported\n");
+			}
+		}
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int sec_key_ctrl(bcm_sec_t *sec, bcm_sec_ctrl_t ctrl, void* arg) 
+{
+	switch(ctrl) {
+		case SEC_CTRL_KEY_GET:	
+			if ( sec->state & SEC_STATE_SECURE) {
+				bcm_sec_btrm_key_info(sec);
+			}
+			break;
+        	case SEC_CTRL_KEY_CLEAN_ALL:
+			bcm_sec_clean_secmem(sec);
+			bcm_sec_clean_keys(sec);
+			break;
+		default:
+			break;
+	}
+	return 0;
+}
+
+void bcm_sec_cb_init(bcm_sec_t* sec)
+{
+	sec->cb[SEC_CTRL_ARG_KEY].cb = sec_key_ctrl;
+	sec->cb[SEC_CTRL_ARG_SOTP].cb = sec_otp_ctrl;
+}
diff --git a/board/broadcom/bcmbca/board_secure_tpl.c b/board/broadcom/bcmbca/board_secure_tpl.c
new file mode 100644
index 0000000000..82a7cc7aa4
--- /dev/null
+++ b/board/broadcom/bcmbca/board_secure_tpl.c
@@ -0,0 +1,1410 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+#include <common.h>
+#include <wdt.h>
+#include <fdtdec.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <linux/errno.h>
+#include <asm/unaligned.h>
+#include <malloc.h>
+#include "tpl_params.h"
+#include "spl_env.h"
+#include "bcm_secure.h"
+#include "bcm_otp.h"
+#include "bcm_rng.h"
+#include <asm/arch/rng.h>
+#include "u-boot/rsa.h"
+#include "u-boot/rsa-mod-exp.h"
+#include <u-boot/sha256.h>
+#include <uboot_aes.h>
+#include <watchdog.h>
+#include "mini-gmp/mini-gmp.h"
+#include "mini-gmp/mini-mpq.h"
+
+#define NODE_NAME_LEN			128
+#define BCM_SEC_MAX_ENCODED_KEYS	10
+#define BCM_SEC_MAX_EXPORTED_ITEMS	5
+#define DELG_SEC_FIT_NODE_PATH 		"/security"
+#define DELG_SEC_FIT_NODE_SIG		"signature"
+#define DELG_SEC_POL_PATH		"/security_policy"
+#define DELG_SEC_POL_DELGID		"delegate_id"
+#define DELG_SEC_POL_MINTPLV		"min_tpl_compatibility"
+#define DELG_SEC_POL_AES_KEY_PATH	"/security_policy/key-aes"
+#define DELG_SEC_POL_AES_KEY_ENC_ALGO	"algo"
+#define DELG_SEC_POL_AES_KEY_DATA	"data"
+#define DELG_SEC_POL_ANTI_ROLLBACK_PATH "/security_policy/anti-rollback"
+#define DELG_SEC_POL_SEC_RESTRICT_PATH  "/security_policy/sec_restriction"
+#define DELG_SEC_POL_STATUS		"status"
+#define DELG_SEC_POL_STATUS_DISABLED	"disabled"
+#define DELG_SEC_POL_NEW_ANTIROLLBCK	"new_antirollback"
+#define DELG_SEC_POL_ANTIROLLBCK_LIM	"antirollback_limit"
+#define DELG_SEC_POL_HW_STATE_PATH	"/security_policy/sec_restriction/hw_state"
+#define DELG_HW_STATE_PATH		"/trust/hw_state"
+#define DELG_ANTI_ROLLBACK_PATH 	"/trust/anti-rollback"
+#define DELG_ENC_KEYS_PATH		"/trust/encoded_keys"
+#define DELG_ENC_KEYS_NAME		"key_name"
+#define DELG_ENC_KEYS_PERM		"permission"
+#define DELG_ENC_KEYS_SIZE		"size"
+#define DELG_ENC_KEYS_DATA		DELG_SEC_POL_AES_KEY_DATA
+#define DELG_ENC_KEYS_LDADDR		"load_addr"
+#define DELG_ENC_KEYS_ALGO		DELG_SEC_POL_AES_KEY_ENC_ALGO
+#define DELG_ENC_KEYS_PERMSEC		"secure"
+#define DELG_ENC_KEYS_PERMNONSEC	"nonsecure"
+#define DELG_TRUST_NODE_PATH		"/trust"
+#define DELG_TRUST_NODE			"trust"
+#define DELG_SEC_POL_SEC_EXPORT_PATH	"/security_policy/sec_restriction/sec_exports"
+#define DELG_SEC_ALLOWED_EXPORTS        "allowed_exports"
+#define DELG_SEC_EXPORT_PATH            "/trust/sec_exports"
+#define DELG_EXP_ITEM_NAME		"item_name"
+#define DELG_EXP_ITEM_ID		"item_sec_id"
+#define DELG_EXP_ITEM_LENGTH		"length"
+#define DELG_EXP_ITEM_SALT		"salt"
+#define DELG_EXP_ITEM_ALGO		DELG_SEC_POL_AES_KEY_ENC_ALGO
+
+static int sec_add_export_item_fdt( u8 * fdt, bcm_sec_export_item_t* item );
+static int bcm_sec_set_sotp_hw_state(u8* fit, int node, bcm_sec_cb_arg_t* sotp_st_arg);
+static int bcm_sec_set_rng_hw_state(u8* fit, int node, bcm_sec_cb_arg_t* rng_st_arg);
+
+typedef struct sec_exp_item_otp_map {
+	char item_id[NODE_NAME_LEN];
+	otp_map_feat_t otp_feat;
+} sec_exp_item_otp_map_t;
+
+sec_exp_item_otp_map_t exp_item_otp_map[] = { 
+	{ "SEC_ITEM_KEY_DEV_SPECIFIC"	, SOTP_MAP_KEY_DEV_SPECIFIC},
+	{ "SEC_ITEM_SER_NUM"		, SOTP_MAP_SER_NUM},
+	{ ""				, OTP_MAP_MAX}
+};
+
+void bcm_sec_clean_secmem(bcm_sec_t* sec)
+{
+	if ( sec->state & SEC_STATE_SECURE) {
+		memset((void*)bcm_secbt_args(), 0, sizeof(bcm_secbt_args_t));
+	}
+}
+
+static int sec_otp_ctrl(bcm_sec_t* sec, bcm_sec_ctrl_t ctrl, void* arg)
+{
+	switch(ctrl) {
+        case SEC_CTRL_SOTP_LOCK_ALL: 
+		/* Lock access to all otp keycontent including register access to the controller for both secure/non-secure masters*/
+		{
+			if (bcm_sotp_ctl_perm(OTP_HW_CMN_CTL_LOCK,
+				OTP_HW_CMN_CTL_LOCK_ALL, NULL) == OTP_MAP_CMN_ERR_UNSP) {
+				printf("WARNING: lock is not supported\n");
+			}
+		}
+		break;
+	
+        case SEC_CTRL_SOTP_UNLOCK_SOTP_UNSEC_PROV: {
+		/*  
+ 		* unlock non secure masters in provisioning mode --> readlock all nonzero rows
+		*/
+			if (bcm_sotp_ctl_perm(OTP_HW_CMN_CTL_UNLOCK,
+				OTP_HW_CMN_CTL_LOCK_NS_PROV, NULL) == OTP_MAP_CMN_ERR_UNSP) {
+				printf("WARNING: unlock is not supported\n");
+			}
+			break;
+		}
+		break;
+
+        case SEC_CTRL_SOTP_UNLOCK_SOTP_UNSEC: {
+		/*  
+ 		* unlock non secure masters
+		*/
+			if (bcm_sotp_ctl_perm(OTP_HW_CMN_CTL_UNLOCK,
+				OTP_HW_CMN_CTL_LOCK_NS, NULL) == OTP_MAP_CMN_ERR_UNSP) {
+				printf("WARNING: unlock is not supported\n");
+			}
+			break;
+		}
+		break;
+        case SEC_CTRL_SOTP_UNLOCK_SOTP_SEC: {
+ 		/* unlock secure masters*/
+			if (bcm_sotp_ctl_perm(OTP_HW_CMN_CTL_UNLOCK,
+				OTP_HW_CMN_CTL_LOCK_S, NULL) == OTP_MAP_CMN_ERR_UNSP) {
+				printf("WARNING: unlock is not supported\n");
+			}
+		}
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int sec_rng_ctrl(bcm_sec_t* sec, bcm_sec_ctrl_t ctrl, void* arg)
+{
+	switch(ctrl) {
+	
+        case SEC_CTRL_RNG_LOCK_ALL: 
+		rng_pac_lock(RNG_PERM_DISABLE_ALL);
+		break;
+	
+        case SEC_CTRL_RNG_UNLOCK_RNG_UNSEC: 
+		rng_pac_lock(RNG_PERM_NSEC_ENABLE);
+		break;
+        case SEC_CTRL_RNG_UNLOCK_RNG_SEC: 
+		rng_pac_lock(RNG_PERM_SEC_ENABLE);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int sec_add_fdt_node( u8 * fdt, char * path, char * nodename)
+{
+	int node = -1;
+	printf("INFO: Creating %s/%s\n", path, nodename);
+        /*
+         * Parameters: Node path, new node to be appended to the path.
+         */
+        node = fdt_path_offset (fdt, path);
+        if (node < 0) {
+                /*
+                 * Not found or something else bad happened.
+                 */
+                printf ("libfdt fdt_path_offset() returned %s\n",
+                        fdt_strerror(node));
+                return -1;
+        }
+        node = fdt_add_subnode(fdt, node, nodename);
+        if (node < 0) {
+                printf ("libfdt fdt_add_subnode(): %s\n",
+                        fdt_strerror(node));
+                return -1;
+        }
+	return node;
+}
+
+static int sec_get_export_item( char * item_id, u8 ** data, u32 * size )
+{
+	int i = 0;
+	int rc = -1;
+
+	while( exp_item_otp_map[i].item_id ) {
+		if( (strncasecmp(exp_item_otp_map[i].item_id, item_id, NODE_NAME_LEN) == 0)) 
+		{
+			printf("INFO: Found matching item for %s = %d\n", item_id, 
+				exp_item_otp_map[i].otp_feat);
+			break;
+		}
+		i++;
+	}
+	if( exp_item_otp_map[i].otp_feat != OTP_MAP_MAX )
+		rc = bcm_otp_read(exp_item_otp_map[i].otp_feat, (u32**)data, size);
+
+	return rc;
+}
+
+static int sec_salt_hash_item( u8 * item_src, int size_src, 
+		u8* item_dest, int size_dst,
+		char * algo, int salt)
+{
+	char * temp_buff;
+	char * buf_ptr;
+	char * dst_ptr;
+
+	/* Allocate temp mem of src size + size of 32-bit salt */
+	temp_buff = malloc(size_src + sizeof(int));
+	if (!temp_buff) {
+		printf("ERROR: Cannot allocate memory tempbuff\n");
+		return -1;
+	} 
+
+	/* Init buffer pointers */
+	buf_ptr = (char*)temp_buff;
+	dst_ptr = (char*)item_dest;
+
+	//TODO: Support other algorithms rather than just sha256
+	if( (size_dst % SHA256_SUM_LEN) || size_dst > 2*SHA256_SUM_LEN ) {
+		printf("ERROR: Unsupported final item size %d for hashing!\n", size_dst);
+		return -1;
+	}
+	
+	/* First pass, get first 256bits of obfuscated item data */
+	if( salt ) {
+		memcpy(buf_ptr, &salt, sizeof(int));
+		buf_ptr += sizeof(int);
+	}
+	memcpy(buf_ptr, item_src, size_src);
+
+	//TODO: Handle other algorigthms, hardcoding to sha256
+	bcm_sec_digest( temp_buff, size_src + sizeof(int), dst_ptr, "sha256");
+	dst_ptr += SHA256_SUM_LEN;
+
+	/* 2nd pass, get 2nd 256bits of obfuscated item data, reverse order of salting */
+	if( size_dst > SHA256_SUM_LEN ) {
+		buf_ptr = temp_buff;
+		memcpy(buf_ptr, item_src, size_src);
+		buf_ptr += size_src;
+		if( salt ) {
+			memcpy(buf_ptr, &salt, sizeof(int));
+			buf_ptr += sizeof(u32);
+		}
+		//TODO: Handle other algorigthms, hardcoding to sha256
+		bcm_sec_digest(temp_buff, size_src + sizeof(int), dst_ptr, "sha256");
+	}
+	free(temp_buff);
+	return 0;
+}
+
+static int sec_add_export_item_fdt( u8 * fdt, bcm_sec_export_item_t* item )
+{
+	int node = -1;
+	char node_name[NODE_NAME_LEN];
+	int ret = -1;
+	u8 * temp_buff = NULL;
+	u8 * pdata = NULL;
+	u32 data_size = 0;
+
+	/* Get the exported item */
+	if( !item->value ) {
+		/* Get items */
+		if( !item->id || !item->len ) {
+			printf("INFO: Skipping exported item %s %s %d\n", item->name, item->id, item->len);
+			ret = 0;
+			goto err;
+		}
+
+		/* Get the item */
+		ret = sec_get_export_item( item->id, &pdata, &data_size );
+		if( ret ) {
+			printf("INFO: Cannot retrieve export item %s! Skipping!\n", item->name);
+			ret = 0;
+			goto err;
+		}
+		
+		/* Allocate memory for value */
+		temp_buff = malloc(item->len);
+		if (!temp_buff) {
+			printf("ERROR: Cannot allocate memory for export item\n");
+			ret = -1;
+			goto err;
+		} 
+		memset(temp_buff,0,item->len);
+
+		/* Salt and/or hash the item */
+		if( item->algo ) {
+			ret = sec_salt_hash_item( (u8*) pdata, data_size, temp_buff, item->len, item->algo, item->salt );
+			if( ret ) {
+				printf("INFO: Cannot salt/hash item %s! Skipping!\n", item->name);
+				ret = 0;
+				goto err;
+			}
+		} else {
+			memcpy(temp_buff, pdata, (data_size>item->len?item->len:data_size));
+		}
+
+		/* Set value */
+		item->value = temp_buff;
+	}
+
+	/* Create /trust node if it doesnt exits */	
+	node = fdt_path_offset (fdt, DELG_TRUST_NODE_PATH);
+	if(node < 0) {
+		node = sec_add_fdt_node( fdt, "/", DELG_TRUST_NODE);
+		if( node < 0) {
+			printf("ERROR: Could not create %s node!\n", DELG_TRUST_NODE_PATH);
+			ret = -1;
+			goto err;
+		}
+	} 
+
+	/* Add item node */
+	snprintf(node_name,NODE_NAME_LEN,item->name);
+	node = sec_add_fdt_node( fdt, DELG_TRUST_NODE_PATH, node_name);
+	if( node < 0 ) {
+		printf("ERROR: Could not add %s node to %s!\n",
+			node_name, DELG_TRUST_NODE_PATH);
+		ret = -1;
+		goto err;
+	}
+	printf("INFO: Adding exported item node %s to dtb, size:%d\n", node_name, item->len);
+
+	/* Add the item value */
+	ret = fdt_setprop(fdt, node, "value", item->value, item->len);
+	if( ret ) {
+		printf("ERROR: Could net set value for %s/%s\n",DELG_TRUST_NODE_PATH,node_name);
+		goto err;
+	}
+	
+	/* Set the export flag */
+	if( !ret && item->exp_flag ) {
+		ret = fdt_setprop(fdt, node, "export", "yes", strlen("yes")+1); 
+		if( ret ) {
+			printf("ERROR: Could not set %s/%s/export\n",DELG_TRUST_NODE_PATH,node_name);
+			goto err;
+		}
+	}
+err:
+	if( temp_buff )
+		free(temp_buff);
+	
+	return ret;
+}
+
+static int sec_add_decoded_key_fdt( u8 * fdt, char* key_name, u8 * key_val, int key_len)
+{
+	int node = -1;
+	char key_node_name[NODE_NAME_LEN];
+	int ret = -1;
+
+	node = fdt_path_offset (fdt, DELG_TRUST_NODE_PATH);
+	/* Create /trust node if it doesnt exits */	
+	if(node < 0) {
+		node = sec_add_fdt_node( fdt, "/", DELG_TRUST_NODE);
+		if( node < 0) {
+			printf("ERROR: Could not create %s node!\n", DELG_TRUST_NODE_PATH);
+			return -1;
+		}
+	} 
+
+	/* Add key node */
+	snprintf(key_node_name,NODE_NAME_LEN,"key_%s", key_name);
+	node = sec_add_fdt_node( fdt, DELG_TRUST_NODE_PATH, key_node_name);
+	if( node < 0 ) {
+		printf("ERROR: Could not add %s node to %s!\n",
+			key_node_name, DELG_TRUST_NODE_PATH);
+		return -1;
+	}
+
+	ret = fdt_setprop(fdt, node, "value", key_val, key_len); 
+	if( ret )
+		printf("ERROR: Could net set value for %s/%s\n",DELG_TRUST_NODE_PATH,key_node_name);
+
+	return ret;
+}
+
+static int sec_key_ctrl(bcm_sec_t *sec, bcm_sec_ctrl_t ctrl, void * arg)
+{
+	int rc = 0;
+	u8* ek_iv = NULL;
+	u8* key_data = NULL;
+	switch(ctrl) {
+	case SEC_CTRL_KEY_GET:
+		{
+			if ( sec->state & SEC_STATE_SECURE) {
+				bcm_sec_btrm_key_info(sec);
+			} else {
+				u8* env_key = bcm_util_env_var2bin("brcm_pub_testkey", RSA2048_BYTES);
+				/* We've got test key; try to authenticate with it
+ 				* Only works in non-secure mode
+ 				* */
+				if (!env_key) {
+					debug("No Key in environment \n");
+				} else {
+					memcpy(sec->key.rsa_pub, env_key, RSA2048_BYTES);
+					sec->key.pub = sec->key.rsa_pub;
+				} 
+			}
+		}
+		break;
+        case SEC_CTRL_KEY_CHAIN_RSA:
+		if (sec->state&SEC_STATE_SECURE) {
+			bcm_sec_export_item_t item;
+			u32 lvl = 0;
+			item.salt = 0;
+			item.algo = NULL;
+			item.exp_flag = 1;
+
+			bcm_sec_get_antirollback_lvl(&lvl);
+			lvl = cpu_to_be32(lvl);
+			item.name = "antirollback_lvl";
+			item.len = sizeof(u32);
+			item.value = (u8*)&lvl;
+			rc = sec_add_export_item_fdt(arg, &item);
+
+			if( rc == 0 ) {
+				item.name = "brcm_pub_key";
+				item.len = RSA2048_BYTES;
+				item.value = sec->key.pub;
+				rc = sec_add_export_item_fdt(arg, &item);
+				if (!sec->key.pub || rc ) {
+					rc = -1;
+					printf("ERROR: unable to chain pub_key\n");
+				}
+			}
+		} 
+		break;
+	case SEC_CTRL_KEY_EXPORT_ITEM: 
+		if (sec->state&SEC_STATE_SECURE) {
+			int i;
+			bcm_sec_key_arg_t* sec_arg = arg;
+			for (i = 0; i<sec_arg->len; i++) { 
+				sec_add_export_item_fdt(sec_arg->arg, 
+					&sec_arg->item[i]);
+			}
+		}
+		break;
+
+       	case SEC_CTRL_KEY_CHAIN_ENCKEY:
+		if (sec->state&SEC_STATE_SECURE) {
+			int i;
+			bcm_sec_key_arg_t* sec_arg = arg;
+			for (i = 0; i<sec_arg->len; i++) { 
+				/* Decrypt encoded key */
+				bcm_sec_get_active_aes_key(&ek_iv);
+				/* FIXME: Compare un-enc and enc sizes to figure out malloc length ( we are assuming enc > un-enc ) */
+				key_data = malloc(sec_arg->enc_key[i].size_enc);
+				if (!key_data) {
+					printf("ERROR: Cannot allocate memory for decoded key size %d!\n", sec_arg->enc_key[i].size_enc);
+					return -1;
+				}
+				memcpy(key_data, sec_arg->enc_key[i].data, sec_arg->enc_key[i].size_enc);
+				bcm_sec_aes_cbc128((u8*)ek_iv, (u8*)ek_iv + AES128_KEY_LENGTH, key_data, sec_arg->enc_key[i].size_enc,0);
+				debug("KEYDECRYPT: encr:0x%08x key:0x%08x decr:0x%08x\n", *(u32*)sec_arg->enc_key[i].data, *(u32*)ek_iv, *(u32*)key_data);
+
+				/* If no permissions are set, assume secure key */
+				if( !sec_arg->enc_key[i].perm ||
+					(strcasecmp(sec_arg->enc_key[i].perm, DELG_ENC_KEYS_PERMSEC) == 0) ) {
+					/* For secure keys see if there is a load address */
+					if( sec_arg->enc_key[i].load_addr ) {
+						printf("INFO: copying key %s to %p\n", 
+							sec_arg->enc_key[i].name,(void*)sec_arg->enc_key[i].load_addr); 
+						printf("INFO: copying to load addr disabled for now!\n");
+						//memcpy((void*)sec_arg->enc_key[i].load_addr,	key_data, sec_arg->enc_key[i].size);
+					} else {
+						printf("INFO: No load address specified for secure key %s! Ignoring\n", sec_arg->enc_key[i].name);
+					}
+				} else {
+					/* For non-secure keys add them to dtb */
+					sec_add_decoded_key_fdt(sec_arg->arg, 
+						sec_arg->enc_key[i].name, 
+						key_data,
+						sec_arg->enc_key[i].size);
+				}
+				free(key_data);
+				key_data = NULL;
+			}
+		}
+		break;
+       	case SEC_CTRL_KEY_CHAIN_AES:
+		if (sec->state&SEC_STATE_SECURE) {
+			int i;
+			bcm_sec_export_item_t item;
+			bcm_sec_key_arg_t* sec_arg = arg;
+			item.salt = 0;
+			item.algo = NULL;
+			item.exp_flag = 0;
+			for (i = 0; i< sec_arg->len; i++) {
+				item.name =  sec_arg->aes[i].id;
+				item.len = BCM_SECBT_AES_CBC128_EK_LEN*2;
+				item.value = sec_arg->aes[i].key;
+				if (sec_add_export_item_fdt(sec_arg->arg, &item)) {
+					rc = -1;
+					printf("ERROR: unable to chain aes_key\n");
+				}
+			}
+		}
+		break;
+        case SEC_CTRL_KEY_CLEAN_SEC_MEM:
+		memset((void*)bcm_secbt_args(),0, sizeof(bcm_secbt_args_t));
+		break;
+        case SEC_CTRL_KEY_CLEAN_ALL:
+		bcm_sec_clean_secmem(sec);
+		bcm_sec_clean_keys(sec);
+		break;
+	default:
+		break;
+	}
+	return rc;
+}
+
+void bcm_sec_cb_init(bcm_sec_t* sec)
+{
+	sec->cb[SEC_CTRL_ARG_KEY].cb = sec_key_ctrl;
+	sec->cb[SEC_CTRL_ARG_SOTP].cb = sec_otp_ctrl;
+	sec->cb[SEC_CTRL_ARG_RNG].cb = sec_rng_ctrl;
+}
+
+void bcm_sec_get_root_aes_key(u8** key)
+{
+	*key = bcm_sec()->key.aes_ek;
+}
+
+u8* bcm_sec_get_root_pub_key(void)
+{
+	return bcm_sec()->key.rsa_pub;
+}
+
+static void bcm_sec_set_delg_cfg( bcm_sec_delg_cfg * cfg )
+{
+	bcm_sec()->delg_cfg_obj = cfg;
+}
+
+bcm_sec_delg_cfg * bcm_sec_get_delg_cfg(void)
+{
+	return bcm_sec()->delg_cfg_obj;
+}
+
+bcm_sec_export_item_t bcm_sec_exported_items[BCM_SEC_MAX_EXPORTED_ITEMS];
+static int bcm_sec_process_exports(u8 * fit_hdr, bcm_sec_cb_arg_t* key_args)
+{
+	u8 * fit_ptr = NULL;
+	bcm_sec_delg_cfg* delg_cfg = bcm_sec_get_delg_cfg();
+	char * allowed_exports = NULL;
+	bcm_sec_key_arg_t * item_list;
+	int sec_export_offset = -1;
+	int exp_item_offset = -1;
+	int count = 0;
+	int ndepth = 0;
+	int * value = NULL;
+
+	/* IF delegations are active then sec_exports in security 
+	 * policy control delegate requested exports */
+	if( delg_cfg && delg_cfg->delg_id ) 
+	{
+		fit_ptr = delg_cfg->sec_policy_fit;
+		sec_export_offset =  fdt_path_offset (fit_ptr, DELG_SEC_POL_SEC_EXPORT_PATH);
+		if (sec_export_offset < 0) {
+			debug("INFO: Could not find %s in security policy\n", DELG_SEC_POL_SEC_EXPORT_PATH);
+		} else {
+			/* Check if sec_export_offset is disabled */
+			value = (int*)fdt_getprop((void *)fit_ptr, sec_export_offset, DELG_SEC_POL_STATUS, NULL);
+			if (value && (strcasecmp((const char*)value, DELG_SEC_POL_STATUS_DISABLED) == 0)){
+				printf("INFO: Found DISABLED  %s  in security policy\n", DELG_SEC_POL_SEC_EXPORT_PATH);
+				sec_export_offset = -1;	
+			} else {
+				printf("INFO: Found %s  in security policy\n", DELG_SEC_POL_SEC_EXPORT_PATH);
+			}
+			allowed_exports = (char*)fdt_getprop((void *)fit_ptr, sec_export_offset, DELG_SEC_ALLOWED_EXPORTS, NULL);
+			if( !allowed_exports || strlen((const char*)allowed_exports) == 0 ) {
+				/* No exports allowed */
+				sec_export_offset = -1;
+			}
+		}
+	}
+	/* If no policy export node  or if policy export  is disabled, simply return */
+	if( sec_export_offset < 0 ) {
+		return 0;
+	}
+
+	/* Check delegate's requested exports */
+	if( fit_hdr ) {
+		delg_cfg = NULL;
+		fit_ptr = fit_hdr;
+		sec_export_offset =  fdt_path_offset (fit_ptr, DELG_SEC_EXPORT_PATH);
+		if (sec_export_offset < 0) {
+			debug("INFO: Could not find %s  in fit\n", DELG_SEC_EXPORT_PATH);
+			return 0;
+		} else {
+			/* Check if sec_export_offset is disabled */
+			value = (int*)fdt_getprop((void *)fit_ptr, sec_export_offset, DELG_SEC_POL_STATUS, NULL);
+			if (value && (strcasecmp((const char*)value, DELG_SEC_POL_STATUS_DISABLED) == 0)){
+				printf("INFO: Found DISABLED  %s  in fit\n", DELG_SEC_EXPORT_PATH);
+				sec_export_offset = -1;
+			} else {
+				printf("INFO: Found %s  in fit\n", DELG_SEC_EXPORT_PATH);
+			}
+		}
+	}
+
+	if (sec_export_offset) {
+		/* Process all image subnodes */
+		for (ndepth = 0, count = 0,
+		     exp_item_offset = fdt_next_node(fit_hdr, sec_export_offset, &ndepth);
+				(exp_item_offset >= 0) && (ndepth > 0);
+				exp_item_offset = fdt_next_node(fit_hdr, exp_item_offset, &ndepth)) {
+			if (ndepth == 1) {
+				/*
+				 * Direct child node of the sec_export parent node,
+				 * i.e. item node.
+				 */
+
+				/* Get key name */
+				bcm_sec_exported_items[count].value = NULL;
+				bcm_sec_exported_items[count].name = (char*)fdt_getprop((void *)fit_hdr, exp_item_offset, DELG_EXP_ITEM_NAME, NULL);
+				bcm_sec_exported_items[count].id = (char*)fdt_getprop((void *)fit_hdr, exp_item_offset, DELG_EXP_ITEM_ID, NULL);
+				value = (int*)fdt_getprop((void *)fit_hdr, exp_item_offset, DELG_EXP_ITEM_LENGTH, NULL);
+
+				if( !bcm_sec_exported_items[count].name || !bcm_sec_exported_items[count].id || !value )
+					continue;
+
+				printf("INFO: Found item:%s id:%s in fit\n", bcm_sec_exported_items[count].name,  bcm_sec_exported_items[count].id);
+				/* Check if requested item is allowed to be exported */
+				if( !strstr(allowed_exports, bcm_sec_exported_items[count].id))
+					continue;
+
+				bcm_sec_exported_items[count].len = be32_to_cpu(*value);
+				if( !bcm_sec_exported_items[count].len)
+					continue;
+
+				/* Get optional 32-bit salt */
+				value = (int*)fdt_getprop((void *)fit_hdr, exp_item_offset, DELG_EXP_ITEM_SALT, NULL);
+				if( value )
+					bcm_sec_exported_items[count].salt = be32_to_cpu(*value);
+
+				/* Get optional hashing algorithm */
+				bcm_sec_exported_items[count].algo = (char*)fdt_getprop((void *)fit_hdr, exp_item_offset, DELG_EXP_ITEM_ALGO, NULL);
+				bcm_sec_exported_items[count].exp_flag = 1;
+
+				count++;
+
+				if( count >= BCM_SEC_MAX_EXPORTED_ITEMS ) {
+					printf("INFO: Max secure export item limit of %d items reached! Ignoring other items!\n", BCM_SEC_MAX_EXPORTED_ITEMS);
+					break;
+				}
+			}
+		}
+	}
+
+	if( count ) {
+		item_list = malloc(sizeof(bcm_sec_key_arg_t));
+		if (!item_list) {
+			printf("ERROR: Cannot allocate memory for exported item list!\n");
+			return -1;
+		}
+		item_list->len = count;
+		item_list->item = &bcm_sec_exported_items[0];
+		key_args->arg[2].ctrl = SEC_CTRL_KEY_EXPORT_ITEM;
+		key_args->arg[2].ctrl_arg = item_list;
+	}
+	return 0;
+}
+
+static int bcm_sec_get_antirollback_node( u8 * fit, char * path, int * req_antirollback, int * antirollback_limit)
+{
+	/* Get key-owners antirollback update node from policy */
+	int * value = NULL;
+	int nodeoffset = fdt_path_offset((void *)fit, path);
+	if( nodeoffset < 0 ) {
+		printf("INFO: %s node NOT found!\n", path);
+	} else  {
+		/* Check if node is disabled */
+		value = (int*)fdt_getprop((void *)fit, nodeoffset, DELG_SEC_POL_STATUS, NULL);
+		if (value && (strcasecmp((const char*)value, DELG_SEC_POL_STATUS_DISABLED) == 0)) {
+			nodeoffset = -1;
+			printf("INFO: Disabled %s node found!\n", path);
+		} else {
+			printf("INFO: %s node found !\n", path);
+			/* retrieve anti=rollback settings */
+			value = (int*)fdt_getprop((void *)fit, nodeoffset, DELG_SEC_POL_NEW_ANTIROLLBCK, NULL);
+			if (value && req_antirollback )
+				*req_antirollback =  be32_to_cpu(*value); 
+
+			value = (int*)fdt_getprop((void *)fit, nodeoffset, DELG_SEC_POL_ANTIROLLBCK_LIM, NULL);
+			if (value && antirollback_limit )
+				*antirollback_limit =  be32_to_cpu(*value); 
+		}
+	}
+	return nodeoffset;
+}
+
+static int bcm_sec_process_antirollback( u8 * fit_hdr)
+{
+	/* Process rollback update node for both key-owner and delegate.
+	 * key-owner's rollback update node can limit the rollback levels that 
+	 * can be updated by delegate */
+	u32 pol_req_antirollback = 0;
+	u32 pol_antirollback_limit = 0;
+	u32 delg_req_antirollback = 0;
+	u32 commit_antirollback = 0;
+	u32 current_antirollback = 0;
+	u32 delg_maximum_antirollback = 0;
+	int nodeoffset_pol = -1;
+	int nodeoffset_fit = -1;
+	bcm_sec_delg_cfg * delg_cfg = NULL;
+	int ret = -1;
+
+	/* Get current anti-rollback level */
+	bcm_sec_get_antirollback_lvl(&current_antirollback);
+
+	/* Check if delegations are active, get key-owners antirollback settings */
+	delg_cfg = bcm_sec_get_delg_cfg();
+	if( delg_cfg && delg_cfg->delg_id ) {
+		/* Get maximum rollback valid for this delegation */
+		delg_maximum_antirollback = delg_cfg->max_antirollback;
+
+		/* Get key-owners antirollback update node from policy */
+		nodeoffset_pol = bcm_sec_get_antirollback_node((void *)delg_cfg->sec_policy_fit, DELG_SEC_POL_ANTI_ROLLBACK_PATH,
+								(int*)&pol_req_antirollback, (int*)&pol_antirollback_limit);
+	}
+
+	/* Get delegates antirollback update node from main FIT hdr */
+	if( fit_hdr ) {
+		nodeoffset_pol = bcm_sec_get_antirollback_node((void *)fit_hdr, DELG_ANTI_ROLLBACK_PATH,
+								(int*)&delg_req_antirollback, NULL);
+	}
+
+	/* Early return if no node found */
+	if ((nodeoffset_pol < 0) && (nodeoffset_fit < 0)) {
+		return 0;
+	}
+
+	printf("INFO: ko_rb:%d kp_lim:%d delg_rb:%d max:%d curr:%d\n",
+		pol_req_antirollback, pol_antirollback_limit, delg_req_antirollback, 
+		delg_maximum_antirollback, current_antirollback);
+
+	/* Verify key-owners requested antirollback */
+	if( pol_req_antirollback ) {
+		if( pol_req_antirollback > delg_maximum_antirollback ) {
+			printf("ERROR: Invalid security policy requested antirollback:%d, Max:%d\n",
+				pol_req_antirollback, delg_maximum_antirollback);
+			return ret;
+		}
+	} 
+	
+	/* Ensure that key-owner's anti-rollback limit for delegate's falls within the max allowable */
+	if( !pol_antirollback_limit || (pol_antirollback_limit > delg_maximum_antirollback) )
+		pol_antirollback_limit = delg_maximum_antirollback;
+
+	
+	/* Verify delegates requested antirollback */
+	if( delg_req_antirollback && pol_antirollback_limit ) {
+		if( delg_req_antirollback > pol_antirollback_limit) {
+			printf("INFO: Invalid FIT requested antirollback:%d, Max:%d\n",
+				delg_req_antirollback, pol_antirollback_limit);
+			delg_req_antirollback = 0;
+		}
+	} 
+	
+	/* Figure out the antirollback level to commit */
+	if (delg_req_antirollback > pol_req_antirollback)
+		commit_antirollback = delg_req_antirollback;
+	else
+		commit_antirollback = pol_req_antirollback;
+
+	/* Do boundary checks */
+	if( !commit_antirollback || (commit_antirollback <= current_antirollback) ) {
+		printf("INFO: Not committing requested anti_rollback level %d! Min:%d\n", 
+			commit_antirollback,current_antirollback);
+		ret = 0;
+	} else {
+		/* commit the antirollback */
+		printf("INFO: Committing antirollback level:%d\n", commit_antirollback);
+		ret = bcm_sec_set_antirollback_lvl(commit_antirollback);
+	}
+
+	return ret;
+}
+
+static int bcm_sec_process_hw_state(u8 * fit_hdr, bcm_sec_cb_arg_t* sotp_st_arg, bcm_sec_cb_arg_t* rng_st_arg)
+{
+	int * value = 0;
+	u8 * fit_ptr = NULL;
+	bcm_sec_state_t st = bcm_sec_state();
+	bcm_sec_delg_cfg* delg_cfg = bcm_sec_get_delg_cfg();
+	int node = -1;
+
+	/* IF delegations are active then hw_state in security 
+	 * policy overrides delegate specified state */
+	if( delg_cfg && delg_cfg->delg_id ) 
+	{
+		fit_ptr = delg_cfg->sec_policy_fit;
+		node =  fdt_path_offset (fit_ptr, DELG_SEC_POL_HW_STATE_PATH);
+		if (node < 0) {
+			debug("INFO: Could not find %s node in security policy\n", DELG_SEC_POL_HW_STATE_PATH);
+		} else {
+			/* Check if node is disabled */
+			value = (int*)fdt_getprop((void *)fit_ptr, node, DELG_SEC_POL_STATUS, NULL);
+			if (value && (strcasecmp((const char*)value, DELG_SEC_POL_STATUS_DISABLED) == 0)){
+				printf("INFO: Found DISABLED  %s node in security policy\n", DELG_SEC_POL_HW_STATE_PATH);
+				node = -1;	
+			} else {
+				printf("INFO: Found %s node in security policy\n", DELG_SEC_POL_HW_STATE_PATH);
+			}
+		}
+	}
+
+	/* Check delegate's specified hw_state */
+	if( (node < 0) && fit_hdr ) {
+		delg_cfg = NULL;
+		fit_ptr = fit_hdr;
+		node =  fdt_path_offset (fit_ptr, DELG_HW_STATE_PATH);
+		if (node < 0) {
+			debug("INFO: Could not find %s node in fit\n", DELG_HW_STATE_PATH);
+			node = -1;
+		} else {
+			/* Check if node is disabled */
+			value = (int*)fdt_getprop((void *)fit_ptr, node, DELG_SEC_POL_STATUS, NULL);
+			if (value && (strcasecmp((const char*)value, DELG_SEC_POL_STATUS_DISABLED) == 0)){
+				printf("INFO: Found DISABLED  %s node in fit\n", DELG_HW_STATE_PATH);
+				node = -1;
+			} else {
+				printf("INFO: Found %s node in fit\n", DELG_HW_STATE_PATH);
+			}
+		}
+	}
+
+	/* Set the default hw state */
+	/* If in secure mode and sotp-lock not specified     --> LOCK by default 
+	 * If in NON-secure mode and sotp-lock not specified --> UNLOCK by default */
+	/* If in secure mode and rng-lock not specified     --> LOCK by default 
+	 * If in NON-secure mode and rng-lock not specified --> UNLOCK by default */
+	if(st == SEC_STATE_SECURE) {
+		sotp_st_arg->arg[0].ctrl = SEC_CTRL_SOTP_LOCK_ALL;
+		rng_st_arg->arg[0].ctrl = SEC_CTRL_RNG_LOCK_ALL;
+	} else {
+		sotp_st_arg->arg[0].ctrl = SEC_CTRL_SOTP_UNLOCK_SOTP_UNSEC;
+		rng_st_arg->arg[0].ctrl = SEC_CTRL_RNG_UNLOCK_RNG_UNSEC;
+	}
+
+	if( node >= 0 ) {
+		/* set hw state from node */
+		bcm_sec_set_sotp_hw_state(fit_ptr, node, sotp_st_arg); 
+		bcm_sec_set_rng_hw_state(fit_ptr, node, rng_st_arg); 
+	}
+	return 0;
+}
+
+static int bcm_sec_delg_pre_process_restrictions(u8 * policy_fdt, u8 * fit_hdr)
+{
+	/* TODO: Pre Process s/w restrictions here */
+	return 0;
+}
+
+bcm_sec_enc_key_arg_t bcm_sec_encoded_keys[BCM_SEC_MAX_ENCODED_KEYS];
+
+static int bcm_sec_process_encoded_keys(u8 * fit_hdr, bcm_sec_cb_arg_t* key_args)
+{
+	/* TODO: Encoded keys could be present in security node or outside security node.
+	 * Keys inside security node will be encrypted via the root aes key. Keys outside
+	 * the security node will be encrypted via the active (delegated) aes key.
+	 * These keys will have  security permissions. These keys need to be added to the 
+	 * key_chain so that they can be exported to the next level of software in 
+	 * spl_perform_fixups */
+	int enc_keys_offset = -1;
+	int key_offset = -1;
+	int count = 0;
+	int ndepth = 0;
+	int * value = NULL;
+	bcm_sec_key_arg_t *enc_keys;
+	bcm_sec_delg_cfg* delg_cfg = bcm_sec_get_delg_cfg();
+
+	/* Process key-owners encoded keys in security node if present
+	 * These keys are encrypted using ROE */
+	if( delg_cfg && delg_cfg->delg_id ) 
+	{
+		/* TODO: Handle key-owners encoded keys */
+	}
+
+	/* Process delegates encoded keys in FIT header
+	 * These keys are encrypted using the active AES key */
+	enc_keys_offset =  fdt_path_offset (fit_hdr, DELG_ENC_KEYS_PATH);
+	if (enc_keys_offset < 0) {
+		debug("INFO: Could not find %s node in fit\n", DELG_ENC_KEYS_PATH);
+		return 0;
+	} else {
+		/* Process all image subnodes */
+		for (ndepth = 0, count = 0,
+		     key_offset = fdt_next_node(fit_hdr, enc_keys_offset, &ndepth);
+				(key_offset >= 0) && (ndepth > 0);
+				key_offset = fdt_next_node(fit_hdr, key_offset, &ndepth)) {
+			if (ndepth == 1) {
+				/*
+				 * Direct child node of the encoded_keys parent node,
+				 * i.e. key node.
+				 */
+
+				/* Get key name */
+				bcm_sec_encoded_keys[count].name = (char*)fdt_getprop((void *)fit_hdr, key_offset, DELG_ENC_KEYS_NAME, NULL);
+				if (bcm_sec_encoded_keys[count].name == NULL)
+				{
+					printf("INFO: Can't find %s parameter in key node under %s \n", DELG_ENC_KEYS_NAME,
+						DELG_ENC_KEYS_PATH);
+					continue;
+				}
+				printf("INFO: Found key %s in under %s\n", bcm_sec_encoded_keys[count].name, DELG_ENC_KEYS_PATH);
+
+				/* Get unencrypted size */
+				value = (int*)fdt_getprop((void *)fit_hdr, key_offset, DELG_ENC_KEYS_SIZE, NULL);
+				if( value ) {
+					bcm_sec_encoded_keys[count].size  =  be32_to_cpu(*value); 
+				} else {
+					printf("INFO: Unencrypted size for key %s is not specified! Skipping Key!\n", 
+						bcm_sec_encoded_keys[count].name);
+					continue;
+				}
+				
+				/* Get keydata */
+				value = (int*)fdt_getprop((void *)fit_hdr, key_offset, DELG_ENC_KEYS_DATA, (int*)&bcm_sec_encoded_keys[count].size_enc);
+				if( value && bcm_sec_encoded_keys[count].size_enc ) {
+					bcm_sec_encoded_keys[count].data = (u8*)value;
+				} else {
+					printf("INFO: Key data for key %s not found! Skipping Key!\n", 
+						bcm_sec_encoded_keys[count].name);
+					continue;
+				}
+
+				/* Get load address (optional) */
+				value = (int*)fdt_getprop((void *)fit_hdr, key_offset, DELG_ENC_KEYS_LDADDR, NULL);
+				if( value )
+					bcm_sec_encoded_keys[count].load_addr  =  be64_to_cpu(*value); 
+
+				/* Get load permissions and enc algorithm (optional) */
+				bcm_sec_encoded_keys[count].perm = (char*)fdt_getprop((void *)fit_hdr, key_offset, DELG_ENC_KEYS_PERM, NULL);
+				bcm_sec_encoded_keys[count].algo = (char*)fdt_getprop((void *)fit_hdr, key_offset, DELG_ENC_KEYS_ALGO, NULL);
+				count++;
+
+				if( count >= BCM_SEC_MAX_ENCODED_KEYS ) {
+					printf("INFO: Max encoded key limit of %d keys reached! Ignoring other keys!\n", BCM_SEC_MAX_ENCODED_KEYS);
+					break;
+				}
+			}
+		}
+	}
+
+	/* Add detected keys */
+	if( count ) {
+		enc_keys = malloc(sizeof(bcm_sec_key_arg_t));
+		if (!enc_keys) {
+			printf("ERROR: Cannot allocate memory for encoded key ring!\n");
+			return -1;
+		}
+		enc_keys->len = count;
+		enc_keys->enc_key = &bcm_sec_encoded_keys[0];
+		key_args->arg[1].ctrl = SEC_CTRL_KEY_CHAIN_ENCKEY;
+		key_args->arg[1].ctrl_arg = enc_keys;
+	}
+	return 0;
+}
+
+static int bcm_sec_delg_process_policy(u8 * policy_fdt, u8 * fit_hdr )
+{
+	u32 * value;
+	u32 pol_delg_id;
+	u32 min_tpl_version;
+	char * key_enc_alg;
+	u8 * key_data;
+	int key_len;
+	int nodeoffset = 0;
+	bcm_sec_delg_cfg * delg_cfg = NULL;
+	int ret = -1;
+
+	/* Get delegation config */ 
+	delg_cfg = bcm_sec_get_delg_cfg();
+	if( !delg_cfg ) {
+		printf("ERROR: Delegation configuration not found!\n");
+		return ret;
+	}
+
+	/* Get security policy node */
+	nodeoffset = fdt_path_offset((void *)policy_fdt, DELG_SEC_POL_PATH);
+	if( nodeoffset < 0 ) {
+		printf("ERROR: %s node not found in security policy!\n", DELG_SEC_POL_PATH);
+		return ret;
+	}
+
+	/* Get delegate id */
+	value = (u32*)fdt_getprop((void *)policy_fdt, nodeoffset, DELG_SEC_POL_DELGID, NULL);
+	if (value == NULL)
+	{
+		printf("Can't find %s parameter in %s\n", DELG_SEC_POL_DELGID,
+			DELG_SEC_POL_PATH);
+		return ret;
+	}
+	pol_delg_id =  be32_to_cpu(*value); 
+	if( pol_delg_id != delg_cfg->delg_id ) {
+		printf("ERROR: delegate ID mismatch! %d != %d !\n", delg_cfg->delg_id, pol_delg_id);
+		return ret;
+	}
+	
+	/* get min tpl version */
+	value = (u32*)fdt_getprop((void *)policy_fdt, nodeoffset, DELG_SEC_POL_MINTPLV, NULL);
+	if (value == NULL)
+	{
+		printf("Can't find %s parameter in %s\n", DELG_SEC_POL_MINTPLV,
+			DELG_SEC_POL_PATH);
+		return 0;
+	}
+
+	//TODO: Compare TPL version to something
+	min_tpl_version =  be32_to_cpu(*value); 
+
+
+	/* 1 - Get delegated AES key (MANDATORY) */
+	nodeoffset = fdt_path_offset((void *)policy_fdt, DELG_SEC_POL_AES_KEY_PATH);
+	if( nodeoffset < 0 ) {
+		printf("ERROR: %s node not found in bundle!\n", DELG_SEC_POL_AES_KEY_PATH);
+		return ret;
+	}
+
+	/* Get encryption algorithm */
+	value = (u32*)fdt_getprop((void *)policy_fdt, nodeoffset, DELG_SEC_POL_AES_KEY_ENC_ALGO, NULL);
+	if (value == NULL)
+	{
+		printf("Can't find %s parameter in %s\n", DELG_SEC_POL_AES_KEY_ENC_ALGO,
+			DELG_SEC_POL_AES_KEY_PATH);
+		return ret;
+	}
+
+	// TODO: Support other encryption algorithms
+	key_enc_alg = (char*)value;
+
+	/* Get key data */
+	value = (u32*)fdt_getprop((void *)policy_fdt, nodeoffset, DELG_SEC_POL_AES_KEY_DATA, &key_len);
+	if (value == NULL)
+	{
+		printf("Can't find %s parameter in %s\n", DELG_SEC_POL_AES_KEY_DATA,
+			DELG_SEC_POL_AES_KEY_PATH);
+		return ret;
+	}
+	printf("Found potential Encrypted AES Key: KAES:0x%08x len:%d\n",
+		*(u32*)value, key_len); 
+
+	/* Decypt delegates aes key using ROE */
+	u8* ek_iv = NULL;
+	bcm_sec_get_root_aes_key(&ek_iv);
+	key_data = malloc(key_len);
+	if (!key_data) {
+		printf("ERROR: Cannot allocate memory for decoded delegated key!\n");
+		return -1;
+	}
+	memcpy(key_data, (u8*)value, key_len); 
+	debug("Decrypting del_enc_key: ROE:0x%08x, KAES:0x%08x len:%d\n",
+	                *(u32*)ek_iv, *(u32*)value, key_len);
+	bcm_sec_aes_cbc128((u8*)ek_iv, (u8*)ek_iv + AES128_KEY_LENGTH, key_data, key_len,0);
+
+	/* Copy key to our delg config */
+	memcpy(delg_cfg->aes_ek, (void*)key_data, 
+			BCM_SECBT_AES_CBC128_EK_LEN); 
+	memcpy(delg_cfg->aes_ek + BCM_SECBT_AES_CBC128_EK_LEN,  
+		(void*)(key_data+BCM_SECBT_AES_CBC128_EK_LEN), BCM_SECBT_AES_CBC128_EK_LEN);
+	free(key_data);
+	key_data = NULL;
+
+	debug("Decrypted AES_EK: 0x%08x AES_IV: 0x%08x\n",
+		*(u32*)delg_cfg->aes_ek, 
+		*(u32*)(delg_cfg->aes_ek + BCM_SECBT_AES_CBC128_EK_LEN));
+
+	bcm_sec_set_active_aes_key(delg_cfg->aes_ek);
+
+	/* Save our pointer to our policy for later use */
+	delg_cfg->sec_policy_fit = policy_fdt;
+
+	/* TODO:Handle sec restrictions */
+	bcm_sec_delg_pre_process_restrictions(policy_fdt, fit_hdr);
+
+	ret = 0;
+
+	return ret;
+
+}
+
+int bcm_sec_delg_process_sec_node(u8 * fit)
+{
+	size_t  size = 0;
+	int nodeoffset = 0;
+	ulong * sec_policy_ptr = NULL;
+	u8 * sig_sec_fit_delg = NULL;
+	int sig_len = 0;
+	int ret = -1;
+	u8* krot_pub = bcm_sec_get_root_pub_key();
+	struct image_sign_info im;
+	
+	/* Setup signing structures */
+	im.checksum = image_get_checksum_algo("sha256,");
+	if (!im.checksum) {
+		printf("ERROR: couldn't get checksum algo\n"); 
+		return ret;
+	}
+
+	nodeoffset = fdt_path_offset((void *)fit, DELG_SEC_FIT_NODE_PATH);
+	if( nodeoffset < 0 ) {
+		printf("ERROR: %s node not found in FIT!\n", DELG_SEC_FIT_NODE_PATH);
+		return ret;
+	}
+	
+	/* Get security policy dtb */
+	fit_image_get_data_and_size((void *)fit, nodeoffset, (const void**)&sec_policy_ptr, &size);
+	if( !size ) {
+		printf("ERROR: sec policy data not found!\n");
+		return ret;
+	}
+
+	/* Get signature */
+	sig_sec_fit_delg = (u8*)fdt_getprop( (void *)fit, nodeoffset, DELG_SEC_FIT_NODE_SIG, &sig_len);
+	if( !sig_sec_fit_delg) {
+		printf("ERROR: %s not found in %s !\n", DELG_SEC_FIT_NODE_SIG,
+			 DELG_SEC_FIT_NODE_PATH);
+		return ret;
+	}
+
+	/* Verify signature */
+	printf("Found potential Security Node: Policy:0x%08x Sig:0x%08x Size:%d\n",
+		*(u32*)sec_policy_ptr, *(u32*)sig_sec_fit_delg, (u32)size);
+
+	ret = bcm_sec_rsa_verify((u8*)sec_policy_ptr, 
+				size, 
+				sig_sec_fit_delg,  
+				RSA2048_BYTES, krot_pub, &im );
+
+	if( ret == 0 ) {
+		printf("Security Node Authentication Successfull!\n");
+		/* Process policy */
+		ret = bcm_sec_delg_process_policy((u8*)sec_policy_ptr, fit);
+	} else {
+		printf("ERROR: Security Node Authentication FAILS!");
+		ret = -1;
+	}
+	return ret;
+
+}
+
+int bcm_sec_delg_process_sdr( u8 * psdr, u8 * hdr_end, u32 * sdr_plus_sig_size)
+{
+	int rc = -1;
+	u32 lvl = 0;
+	u32 delegateId = 0;
+	u32 max_anti_rollback_lvl = 0;
+	u8* sdr_start = psdr;
+	unsigned long long sdr_size = 0;
+	u8* sig_sec_rec_delg = NULL;
+	u8* krsa_delg_pub = NULL;
+	u8* krot_pub = bcm_sec_get_root_pub_key();
+	struct image_sign_info im;
+	bcm_sec_delg_cfg * delg_cfg = NULL;
+	
+	/* Setup signing structures */
+	im.checksum = image_get_checksum_algo("sha256,");
+	if (!im.checksum) {
+		printf("ERROR: couldn't get checksum algo\n"); 
+		goto err;
+	}
+
+	/* parse sdr fields */
+	psdr += sizeof(u32);
+	delegateId = *(u32*)psdr;
+	psdr += sizeof(u32);
+	max_anti_rollback_lvl = *(u32*)psdr;
+	psdr += sizeof(u32);
+	krsa_delg_pub = psdr;
+	psdr += RSA2048_BYTES;
+	sig_sec_rec_delg = psdr;
+	sdr_size = (unsigned long long )(psdr - sdr_start); // Check this
+	*sdr_plus_sig_size = sdr_size + RSA2048_BYTES;
+
+	printf("Found potential SDR: delg_id:%d maxrollbck:%d size:%llu\n", 
+		delegateId, max_anti_rollback_lvl, sdr_size);
+
+	printf("Found potential SDR: PubKey:0x%08x Sig:0x%08x\n",
+		*(u32*)krsa_delg_pub, *(u32*)sig_sec_rec_delg);
+	
+	/* Check if SDR + signature have crossed our search boundary */
+	if ( ((u8*)psdr + *sdr_plus_sig_size-1) > hdr_end ) {
+		printf("ERROR: Corrupted SDR, search exceeds boundary 0x%p > 0x%p\n",
+			(u8*)psdr + RSA2048_BYTES-1, hdr_end);
+		goto err;
+	}
+	
+	/* Check if delegateID is valid */
+	if( !delegateId ) {
+		printf("ERROR: Invalid Delegate ID %d\n", delegateId);
+		goto err;
+	}
+
+	/* Check if anti-rollback is valid */
+	rc = bcm_sec_get_antirollback_lvl(&lvl);
+	if(  (lvl > max_anti_rollback_lvl) || rc ) {
+		printf("ERROR: Expired delegated credentials detected curr(%d) > max(%d) rc:%d\n", 
+			lvl, max_anti_rollback_lvl, rc);
+		rc = -1;
+		goto err;
+	}
+	
+	
+	/* Authenticate sdr signature */
+	rc = bcm_sec_rsa_verify(sdr_start, 
+				sdr_size, 
+				sig_sec_rec_delg,  
+				RSA2048_BYTES, krot_pub, &im );
+	if( rc == 0 ) {
+		printf("SDR Authentication Successfull!\n");
+		/* Commit all fields to our structures */
+		delg_cfg = malloc(sizeof(bcm_sec_delg_cfg)); //TODO: Where to free this?
+		if (!delg_cfg) {
+			printf("ERROR: Cannot allocate memory for delegation config!\n");
+			rc = -1;
+			goto err;
+		}
+		delg_cfg->delg_id = delegateId;
+		delg_cfg->max_antirollback = max_anti_rollback_lvl;
+		memcpy(delg_cfg->rsa_pub, krsa_delg_pub, BCM_SECBT_RSA2048_MOD_LEN);
+
+		/* Commit delegation config */
+		bcm_sec_set_delg_cfg( delg_cfg );
+
+		/* Set active public key */
+		bcm_sec_set_active_pub_key( (u8*)delg_cfg->rsa_pub );
+
+	} else {
+		printf("ERROR: SDR Authentication FAILS!\n");
+		rc = -1;
+	}
+
+err:
+	return rc;
+}
+
+/* returns heap allocated key*/
+static int fdt_key_decrypt(void* fit, int node, const char* prop, 
+			const u8* ek_iv,  u8* aes)
+{
+	int rc = -1, len = 0;
+	assert(BCM_SECBT_AES_CBC128_EK_LEN == AES128_KEY_LENGTH);
+	const u8* key = fdt_getprop(fit, node, prop, &len);
+	if (!key || ((len-1)%(AES128_KEY_LENGTH*2))) {
+		if (key) {
+			printf("Error: Invalid size for %s must be at least %d including iv \n",prop ,AES128_KEY_LENGTH*2);
+		}
+		goto err;
+	}
+	if (bcm_util_hex2u32((const char*)key, aes) < 0) {
+		goto err;
+	}
+	bcm_sec_aes_cbc128((u8*)ek_iv, (u8*)ek_iv + AES128_KEY_LENGTH, aes, (len-1)/2, 0);
+	rc  = 0;
+err: 
+	return rc;
+}
+
+static int bcm_sec_fit_key_chain(void* fit, int node, bcm_sec_key_arg_t** aes )
+{
+	int rc = -1, len = 0;
+	u8* ek_iv = NULL;
+	bcm_sec_key_aes_arg_t* _aes = NULL;
+	bcm_sec_key_arg_t* aes_arg = NULL;
+	char *_keys_prop[2] = {FIT_AES1, FIT_AES2};
+	bcm_sec_get_active_aes_key(&ek_iv);
+	if (!ek_iv)   {
+		goto err;
+	}
+	aes_arg = malloc(sizeof(bcm_sec_key_arg_t));
+	_aes    = malloc(sizeof(bcm_sec_key_aes_arg_t)*2);
+	if (!aes_arg || !_aes) {
+		goto err;
+	}
+	memset(aes_arg, 0, sizeof(bcm_sec_key_arg_t));
+	memset(_aes,    0, sizeof(bcm_sec_key_arg_t)*2);
+	aes_arg->aes = _aes;
+
+	if (fdt_key_decrypt(fit, node, _keys_prop[0], ek_iv,  _aes[0].key)) {
+		free(_aes);
+		free(aes_arg);
+		goto err;
+	}
+	strcpy(_aes[0].id, _keys_prop[0]);
+	aes_arg->len++;
+	if (!fdt_key_decrypt(fit, node, _keys_prop[1], _aes[0].key,  _aes[1].key)) {
+		if (fdt_getprop(fit, node, "dont-flush-aes1", &len)) {
+		/* will chain aes1-key along with dev key */
+			strcpy(_aes[1].id, _keys_prop[1]);
+			aes_arg->len++;
+		} else {
+			strcpy(_aes[0].id, _keys_prop[1]);
+			memcpy(_aes[0].key, _aes[1].key, AES128_KEY_LENGTH*2);	
+			memset(_aes[1].key,  AES128_KEY_LENGTH*2, 0);
+		}
+	}
+	*aes = aes_arg;
+	rc  = 0;
+err:
+	return rc;
+}
+
+static int bcm_sec_set_sotp_hw_state(u8* fit, int node, bcm_sec_cb_arg_t* sotp_st_arg) {
+
+	int * value = NULL;
+	int len;
+
+	/* Set sotp hardware state */
+	value = (int*)fdt_getprop(fit, node, "sotp-lock", &len);
+	if( value ) {
+		if (strncmp((const char*)value, "all", 3) == 0) {
+			/* Lock access for all masters */
+			sotp_st_arg->arg[0].ctrl = SEC_CTRL_SOTP_LOCK_ALL;
+		} else if( strncmp((const char*)value, "none", 4) == 0 ) {
+			/* Lock access for none ( unlocked for all masters ) */
+			sotp_st_arg->arg[0].ctrl = SEC_CTRL_SOTP_UNLOCK_SOTP_UNSEC;
+		} else if( strncmp((const char*)value, "prov", 4) == 0 ) {
+			/* Provisioning mode, Lock access for none, lock non-zero rows */
+			sotp_st_arg->arg[0].ctrl = SEC_CTRL_SOTP_UNLOCK_SOTP_UNSEC_PROV;
+		} else {
+			/* Lock access for non secure masters only ( unlocked for secure masters only )*/
+			sotp_st_arg->arg[0].ctrl = SEC_CTRL_SOTP_UNLOCK_SOTP_SEC;
+		}
+	}
+	return 0;
+}
+
+static int bcm_sec_set_rng_hw_state(u8* fit, int node, bcm_sec_cb_arg_t* rng_st_arg) {
+
+	int * value = NULL;
+	int len;
+
+	/* Set rng hardware state */
+	value = (int*)fdt_getprop(fit, node, "rng-lock", &len);
+	if( value ) {
+		if(strncmp((const char*)value, "all", 3) == 0) {
+			/* Lock access for all masters */
+			rng_st_arg->arg[0].ctrl = SEC_CTRL_RNG_LOCK_ALL;
+		} else if( strncmp((const char*)value, "none", 4) == 0 ) {
+			/* Lock access for none ( unlocked for all masters ) */
+			rng_st_arg->arg[0].ctrl = SEC_CTRL_RNG_UNLOCK_RNG_UNSEC;
+		} else {
+			/* Lock access for non secure masters only ( unlocked for secure masters only )*/
+			rng_st_arg->arg[0].ctrl = SEC_CTRL_RNG_UNLOCK_RNG_SEC;
+		}
+	}
+	return 0;
+}
+
+int bcm_sec_fit(void* fit)
+{
+	bcm_sec_key_arg_t *aes;
+	int node = -1;
+/*trust/dont-lock-sotp ==>  otherwise, lock SOTP before passing control
+
+trust/dont-flush-aes1 ==> otherwise, wipe out the aes key before passing control
+trust/aes1-key = hex-string ==> use original AES key to decrypt this string, wipe the original key,*/ 
+	bcm_sec_cb_arg_t cb_args[SEC_CTRL_ARG_MAX] = {0}; 
+	bcm_sec_cb_arg_t* karg = &cb_args[SEC_CTRL_ARG_KEY];
+	bcm_sec_cb_arg_t* sarg = &cb_args[SEC_CTRL_ARG_SOTP];
+	bcm_sec_cb_arg_t* rarg = &cb_args[SEC_CTRL_ARG_RNG];
+	bcm_sec_delg_cfg* delg_cfg = bcm_sec_get_delg_cfg();
+
+	/* Chain keys if required */
+	/* when enumerated later 0 - will be run first
+ 	* 1- second and so on.for both s_ctrl and k_ctrl 		
+ 	*/
+	karg->arg[0].ctrl = SEC_CTRL_KEY_CHAIN_RSA;
+	karg->arg[3].ctrl = SEC_CTRL_KEY_CLEAN_ALL;
+	
+	if( delg_cfg && delg_cfg->delg_id ) {
+		/* If delegated credentials are in play then do not pass aes1/aes2 
+		 * and instead process encoded keys in FIT and security node */
+		bcm_sec_process_encoded_keys(fit, karg);
+	} else  {
+		node =  fdt_path_offset (fit, "/trust");
+		if (node < 0) {
+			/* No trust node */
+			goto done;
+		}
+		/* aes1  aka aes1 
+		*  aes2 gets decrypted by aes1, aes1 gets decrypted by ROE aka truste bootrom key 
+		* 	*/ 
+		if (!bcm_sec_fit_key_chain(fit, node, &aes)) {
+			karg->arg[1].ctrl = SEC_CTRL_KEY_CHAIN_AES;
+			karg->arg[1].ctrl_arg = aes;
+		}
+	}
+
+	/* Configure anti-rollback levels */
+	bcm_sec_process_antirollback(fit);
+
+	/* Export secure items */
+	bcm_sec_process_exports(fit, karg);
+
+done:
+	/* Set hw states */
+	bcm_sec_process_hw_state(fit, sarg, rarg);
+
+	bcm_sec_do(SEC_SET_SCHED, cb_args);
+	return 0;
+
+}
diff --git a/board/broadcom/bcmbca/board_secure_utils.c b/board/broadcom/bcmbca/board_secure_utils.c
new file mode 100644
index 0000000000..bfef25f74f
--- /dev/null
+++ b/board/broadcom/bcmbca/board_secure_utils.c
@@ -0,0 +1,299 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <linux/errno.h>
+#include <asm/unaligned.h>
+#include <malloc.h>
+#include "tpl_params.h"
+#include "spl_env.h"
+#include "bcm_secure.h"
+#include "u-boot/rsa.h"
+#include "u-boot/rsa-mod-exp.h"
+#include <u-boot/sha256.h>
+#include <uboot_aes.h>
+#include <watchdog.h>
+#include "mini-gmp/mini-gmp.h"
+#include "mini-gmp/mini-mpq.h"
+
+#ifdef BCM_SEC_KEY_OBFUSCATION
+
+static int sec_gen_key(u8* key)
+{
+	// setup bootlut 
+	// A sketch
+	int i, rc = -1;
+	/* secure mailbox */
+	volatile u32 *rng = 0xff800b00;
+	/* enable an RNG default was 0x11 <<*/
+	rng[(0x80>>2)] = (0x1|(0x11<<13));
+	/* if count not 0 and not empty */	
+	while((rng[(0xa4>>2)]>>31) > 0 || rng[(0xa4>>2)] < 8 );
+	if ((rng[(0xa4>>2)]&0xff)) {
+		u32 key[8];	
+		/* Collect words*/
+		for (i = 0; i < 8; i++ ) {
+			key[i] =  rng[(0xa0>>2)];
+		}
+		rc = 0;
+	}
+	return rc;
+}
+
+int sec_mbox_set(u8* key)
+{
+	// setup bootlut 
+	// A sketch
+	int i;
+	/* secure mailbox */
+	volatile u32 *bootlut = 0xffff0000;
+	/* Collect words*/
+	for (i = 0; i < 8; i++ ) {
+		bootlut[i] =  key[i];
+	}
+	bootlut[(0x40>>2)] = 0xdd;
+}
+
+
+int sec_mbox_get(u8* key)
+{
+	// setup bootlut 
+	// A sketch
+	int i;
+	/* secure mailbox */
+	volatile u32 *bootlut = 0xffff0000;
+	/* Collect words*/
+	for (i = 0; i < 8; i++ ) {
+		key[i] = bootlut[i];
+	}
+}
+u8* obfuscate(const u8* s,
+	u32 len)
+{
+	u8 ses_key[AES128_KEY_LENGTH*2];
+	/*Get aes */
+	/* After this line only secure master could write to the mailbox register*/
+	u8* dat = malloc(len);
+	if (dat && !sec_gen_key(ses_key)) {
+		memcpy(dat, s, len);
+		bcm_sec_aes_cbc128(ses_key, ses_key+AES128_KEY_LENGTH, dat, len, 1);
+		sec_set_mbox(ses_key);		
+		return dat;
+	} 
+	if (dat) {
+		free(dat);
+	} 
+	return NULL; 
+}
+
+u8* deobfuscate(u8* s,
+	u32 len)
+{
+	u8 ses_key[AES128_KEY_LENGTH*2];
+	/*Get aes */
+	/* After this line only secure master could write to the mailbox register*/
+	sec_get_mbox(ses_key);
+	bcm_sec_aes_cbc128(ses_key, ses_key+AES128_KEY_LENGTH, s, len, 0);
+	return s;
+}
+#endif
+
+
+#if defined (CONFIG_TPL_BUILD)
+extern tpl_params * tplparams;
+
+static inline char* __get_ev(const char* nm)
+{
+        char* k = NULL;
+        if (!tplparams) {
+                return NULL;
+        }
+        k = find_spl_env_val(tplparams->environment, nm);
+        if (!k) {
+                return NULL;
+        }
+        return k;
+}
+
+#else
+
+static inline char* __get_ev(const char* nm)
+{
+        return env_get(nm);
+}
+
+#endif
+int bcm_util_hex2u32(const char* s, u8*  d)
+{
+	int len;
+	u32* u = (u32*)d ;
+        char buf[sizeof(u32)*2 + sizeof(u8)] = {0};
+	char* pmax, *p = (char*)s;
+	if (!p || !d) {
+		return -1;
+	}
+
+	len = strlen(p);
+	len -= (len%sizeof(u32));
+	pmax = (char*)s + len; 
+        while(p < pmax )        {
+                memcpy(buf, p, sizeof(u32)*2);
+                *u++ = ntohl(simple_strtoul((const char*)buf, NULL, 16));
+                //printf("\n %x %s \n",new_key[j-1],buf);
+                p += sizeof(u32)*2;
+        }
+	return len/2; 
+}
+
+u8* bcm_util_env_var2bin(const char* id, u32 len )
+{
+        char* p = NULL, *pmax;
+        u8 *data = NULL;
+        char buf[sizeof(u32)*2+sizeof(u8)] = {0};
+        int j = 0 ;
+        p = __get_ev(id);
+        if (!p) {
+                debug("No key\n");
+                return NULL;
+        }
+        pmax = p + strlen((const char*)p);
+        if (pmax-p != len*2) {
+                printf("ERROR: invalid length for %s;must be %d got only %d\n",
+                id, len*2, (u32)(pmax - p));
+                return NULL;
+        }
+        data = malloc(len);
+        if (!data) {
+                return NULL;
+        }
+        while(p < pmax )        {
+                memcpy(buf, p, sizeof(u32)*2);
+                ((u32*)data)[j++] = ntohl(simple_strtoul((const char*)buf, NULL, 16));
+                //printf("\n %x %s \n",new_key[j-1],buf);
+                p += sizeof(u32)*2;
+        }
+        return data;
+}
+
+void bcm_sec_aes_cbc128(u8 *key, u8 *iv, u8* txt, 
+			u32 length, u32 flag)
+{ 
+	u32 num_aes_blocks;
+	u8 key_schedule[AES128_EXPAND_KEY_LENGTH];
+	aes_expand_key(key, AES128_KEY_LENGTH, key_schedule);
+	num_aes_blocks = (length + AES128_KEY_LENGTH - 1) / AES128_KEY_LENGTH;
+	flag? aes_cbc_encrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, txt, txt, num_aes_blocks) :
+			aes_cbc_decrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, txt, txt, num_aes_blocks);
+}
+
+static inline void checksum_sha256(const u8 *obj, 
+				u32 len, u8* hash)
+{
+	sha256_context ctx;
+	sha256_starts(&ctx);
+	sha256_update(&ctx, obj, len);
+	sha256_finish(&ctx, hash);
+}
+
+static int rsa_get_params(const u8* modulus,
+			u32 modulus_size,	
+			unsigned long *n0inv, 
+			u8 *rr)
+{
+	size_t wcnt; 
+	int rc = 0; 
+	mpz_t	 _inv, _n0inv, 
+		_r_sqrd, _key, _2_32, _2, _2_x;
+
+	mpz_init (_n0inv);
+	mpz_init (_inv);
+	mpz_init (_r_sqrd);
+	mpz_init (_key);
+	mpz_init (_2);
+	mpz_init (_2_32);
+	mpz_init (_2_x);
+	mpz_set_ui (_2, 2);
+	mpz_import(_key , modulus_size, 1, sizeof(u8), 0, 0, modulus);
+	mpz_pow_ui(_2_32, _2, 32);
+	/* Calculate an inverse for _key and 2^32 */
+	if ( mpz_invert(_inv, _key, _2_32) == 0) {
+		rc = -1;
+		goto err;
+	}
+	/*subtract to get negative of _inv*/
+	mpz_sub(_n0inv, _2_32, _inv);
+	
+	mpz_export(n0inv, &wcnt, 1, sizeof(unsigned long), -1, 0, _n0inv);
+	
+	/*printf(" wcnt;--- n0inv:  %lu \n \t 0x%u\n", wcnt, *n0inv);*/
+	/* RSA2048_BYTES converted to bits then multipled by 2 
+  		to square [2^(RSA2048_BYTES*8)]^2
+	*/
+	mpz_pow_ui(_2_x, _2, modulus_size*8*2);
+	/* modulo division to get an r-squared */
+	mpz_mod(_r_sqrd, _2_x, _key);
+
+	mpz_export(rr, &wcnt, 1, modulus_size, 1, 0, _r_sqrd);
+	//dbg_hex(rr, RSA2048_BYTES, "R squared:");
+err:
+	mpz_clear (_n0inv);
+	mpz_clear (_inv);
+	mpz_clear (_r_sqrd);
+	mpz_clear (_key);
+	mpz_clear (_2);
+	mpz_clear (_2_32);
+	mpz_clear (_2_x);
+	return rc;
+
+}
+
+
+void bcm_sec_digest(const u8 *data, u32 len, u8* digest, char* algo)
+{
+	//TODO: Support other algo, currently Ignoring algo and defaulting to sha256
+	checksum_sha256(data, len, digest);
+}
+
+int bcm_sec_rsa_verify(const u8 *obj, 
+		u32 obj_len, const u8* sig, 
+		u32 sig_len, const u8 *pub, 
+		struct image_sign_info *im )
+{
+	int rc = -1;
+	struct key_prop rsa_prop ;
+	u8 hash[SHA256_SUM_LEN] = {0};
+	u8 rr[RSA2048_BYTES*2] = {0};
+        u8	sig_dec[RSA2048_BYTES] = {0};
+	unsigned long n0inv = 0;
+	checksum_sha256(obj, obj_len, hash);
+	rc = rsa_get_params(pub, RSA2048_BYTES, &n0inv, rr); 
+	if (rc) {
+		printf("ERROR: rsa arguments\n");	
+		goto err;
+	}
+
+	rsa_prop.modulus = pub;
+	rsa_prop.n0inv = n0inv;
+	rsa_prop.rr = rr;
+	rsa_prop.num_bits = RSA2048_BYTES*8;
+	rsa_prop.exp_len = 4;
+	rsa_prop.public_exponent = NULL;
+	rc = rsa_mod_exp_sw(sig, sig_len, &rsa_prop, sig_dec);
+	if (rc) {
+		printf("ERROR: rsa decryption\n");	
+		goto err; 
+	}
+	//dbg_hex(sig_dec, RSA2048_BYTES, " Sig Decrypted :");
+	//dbg_hex(hash, SHA256_SUM_LEN, " hash :");
+	rc = padding_pss_verify(im, sig_dec, RSA2048_BYTES, hash, SHA256_SUM_LEN);
+err:
+	memset(sig_dec, 0, RSA2048_BYTES);
+	memset(hash, 0, SHA256_SUM_LEN);
+	memset(rr, 0, RSA2048_BYTES*2);
+	memset(&rsa_prop, 0, sizeof(struct key_prop));
+	return rc;
+}
diff --git a/board/broadcom/bcmbca/board_spl.c b/board/broadcom/bcmbca/board_spl.c
new file mode 100644
index 0000000000..9b9deaef8e
--- /dev/null
+++ b/board/broadcom/bcmbca/board_spl.c
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include <spl.h>
+#include <nand.h>
+#include "spl_ddrinit.h"
+#include <asm/arch/misc.h>
+#if defined(CONFIG_BCMBCA_DDRC)
+#include "asm/arch/ddr.h"
+#endif
+#include "boot_blob.h"
+#include "boot_flash.h"
+#include "tpl_params.h"
+#include "spl_env.h"
+#include "early_abort.h"
+#include "bcm_secure.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+tpl_params tplparams;
+
+void spl_board_deinit(void);
+
+static void setup_tpl_parms(tpl_params *parms)
+{
+	tplparams.environment = NULL;
+	/* tplparams.early_flags = boot_params; */
+#if defined(CONFIG_BCMBCA_DDRC)
+	tplparams.ddr_size = get_ddr_size();
+#else
+	tplparams.ddr_size = 64*1024*1024;
+#endif
+	tplparams.boot_device = bcmbca_get_boot_device();
+	parms->environment = load_spl_env((void*)TPL_ENV_ADDR);
+}
+
+/* spl load and start tpl. never return */
+__weak void start_tpl(tpl_params *parms)
+{
+	typedef void __noreturn(*image_entry_t) (void *);
+	image_entry_t image_entry =
+		(image_entry_t) CONFIG_TPL_TEXT_BASE;
+	void *new_params = (void*)TPL_PARAMS_ADDR;
+	int size = CONFIG_TPL_MAX_SIZE;
+
+	memcpy(new_params, parms, sizeof(tpl_params));
+
+	if (load_boot_blob(TPL_TABLE_MAGIC, 0x0, (void *)CONFIG_TPL_TEXT_BASE,
+		&size) == 0) {
+		spl_board_deinit();
+		image_entry((void *)new_params);
+	}
+
+	/* disable mmu/dcache to enable loading of uboot to memory by jtag if needed */
+	dcache_disable();
+	hang();
+}
+
+__weak void arch_cpu_deinit()
+{
+
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NONE;
+}
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+int reserve_mmu(void)
+{
+#if defined(CONFIG_BRCM_SPL_MEMC_SRAM)
+	/* enable 64KB sram in MEMC controller for MMU table */
+	MEMC->SRAM_REMAP_CTRL = (CONFIG_SYS_PAGETBL_BASE | 0x00000040);
+	MEMC->SRAM_REMAP_CTRL |= 0x2;
+	MEMC->SRAM_REMAP_CTRL;
+#endif
+
+	gd->arch.tlb_addr = CONFIG_SYS_PAGETBL_BASE;
+	gd->arch.tlb_size = CONFIG_SYS_PAGETBL_SIZE;
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BCMBCA_LDO_TRIM
+static void bcmbca_set_ldo_trim(void)
+{
+	u32 trim = 0;
+
+	bcm_otp_get_ldo_trim(&trim);
+	if (trim) {
+		printf("Apply trim code 0x%x reg 0x%x from otp to LDO controller...\n", 
+			trim, (trim<<LDO_VREG_CTRL_TRIM_SHIFT)&LDO_VREG_CTRL_TRIM_MASK );
+		TOPCTRL->LdoCtl =
+			(trim<<LDO_VREG_CTRL_TRIM_SHIFT) & LDO_VREG_CTRL_TRIM_MASK;
+	}
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init();
+#endif
+#if defined(CONFIG_SYS_ARCH_TIMER)
+	timer_init();
+#endif
+	if (spl_early_init())
+		hang();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+	printf("Strap register: 0x%x\n", MISC->miscStrapBus);
+	if (bcm_otp_init()) {
+		hang();
+	}
+
+	bcm_sec_init();
+#if defined(BUILD_TAG)
+	printf("$SPL: "BUILD_TAG" $\n");
+#endif
+	early_abort();
+
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+	reserve_mmu();
+	enable_caches();
+#endif
+}
+
+void spl_board_deinit(void)
+{
+	/* 
+	 * even thought the name says linux but it does everything needed for
+	 * boot to the next image: flush and disable cache, disable mmu
+	 */
+	cleanup_before_linux();
+
+	arch_cpu_deinit();
+
+#if defined(CONFIG_BRCM_SPL_MEMC_SRAM)
+	/* disable 64KB sram in MEMC controller for MMU table */
+	MEMC->SRAM_REMAP_CTRL = 0;
+	MEMC->SRAM_REMAP_CTRL;
+#endif	
+}
+
+void spl_board_init(void)
+{
+	early_abort_t* ea_info;
+
+#ifdef CONFIG_BCMBCA_LDO_TRIM
+	bcmbca_set_ldo_trim();
+#endif
+	boot_flash_init();
+
+	ea_info = early_abort_info();
+
+#ifdef CONFIG_BCMBCA_EARLY_ABORT_JTAG_UNLOCK
+	printf("WARNING -- JTAG UNLOCK IS ENABLED\n");
+#endif
+#if defined(CONFIG_BCMBCA_DDRC)
+	{
+		uint32_t mcb_sel = 0,
+			mcb_mode = 0;
+		if ((ea_info->status&SPL_EA_DDR_MCB_SEL)) {
+			mcb_mode = (SPL_DDR_INIT_MCB_OVRD|SPL_DDR_INIT_MCB_SEL);
+			mcb_sel = ea_info->data;
+		} else if ((ea_info->status&(SPL_EA_DDR3_SAFE_MODE))) {
+			mcb_mode = (SPL_DDR_INIT_MCB_OVRD|SPL_DDR_INIT_DDR3_SAFE_MODE);
+		} else if ((ea_info->status&SPL_EA_DDR4_SAFE_MODE)) {
+			mcb_mode = (SPL_DDR_INIT_MCB_OVRD|SPL_DDR_INIT_DDR4_SAFE_MODE);
+		}
+		/*printf("\nGot mcb_mode 0x%x\n",mcb_mode);*/
+		spl_ddrinit(mcb_mode, mcb_sel);
+	}
+#endif
+
+	if ((ea_info->status&(SPL_EA_IMAGE_FB))) {
+		tplparams.early_flags = SPL_EA_IMAGE_FB;
+	}else if ((ea_info->status&SPL_EA_IMAGE_RECOV)) {
+		tplparams.early_flags = SPL_EA_IMAGE_RECOV;
+	}
+	if ((ea_info->status&SPL_EA_IGNORE_BOARDID)) {
+		tplparams.early_flags |= SPL_EA_IGNORE_BOARDID;
+	}
+	/* printf("\nGot TPL flags 0x%x\n",tplparams.early_flags); */
+	setup_tpl_parms(&tplparams);
+
+	start_tpl(&tplparams);
+}
diff --git a/board/broadcom/bcmbca/board_tk_prog.c b/board/broadcom/bcmbca/board_tk_prog.c
new file mode 100644
index 0000000000..46548bcc5f
--- /dev/null
+++ b/board/broadcom/bcmbca/board_tk_prog.c
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include <spl.h>
+#include <asm/arch/misc.h>
+#include "asm/arch/ddr.h"
+#include "bcm_secure.h"
+#include "bcm_otp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+void spl_board_deinit(void);
+
+__weak void arch_cpu_deinit()
+{
+
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NONE;
+}
+__weak void spl_ddrinit_prepare(void)
+{
+}
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+int reserve_mmu(void)
+{
+#if defined(CONFIG_BRCM_SPL_MEMC_SRAM)
+	/* enable 64KB sram in MEMC controller for MMU table */
+	MEMC->SRAM_REMAP_CTRL = (CONFIG_SYS_PAGETBL_BASE | 0x00000040);
+	MEMC->SRAM_REMAP_CTRL |= 0x2;
+	MEMC->SRAM_REMAP_CTRL;
+#endif
+	gd->arch.tlb_addr = CONFIG_SYS_PAGETBL_BASE;
+	gd->arch.tlb_size = CONFIG_SYS_PAGETBL_SIZE;
+
+	return 0;
+}
+#endif
+
+extern int sec_tk();
+extern void sec_tk_find_keystore();
+void board_init_f(ulong dummy)
+{
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init();
+#endif
+#if defined(CONFIG_SYS_ARCH_TIMER)
+	timer_init();
+#endif
+       if (spl_early_init())
+                hang();
+
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+	printf(" TK OTP/SOTP \n");
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+	reserve_mmu();
+	enable_caches();
+#endif
+	sec_tk_find_keystore();
+}
+
+void spl_board_deinit(void)
+{
+	/* 
+	 * even thought the name says linux but it does everything needed for
+	 * boot to the next image: flush and disable cache, disable mmu
+	 */
+	cleanup_before_linux();
+
+	arch_cpu_deinit();
+
+#if defined(CONFIG_BRCM_SPL_MEMC_SRAM)
+	/* disable 64KB sram in MEMC controller for MMU table */
+	MEMC->SRAM_REMAP_CTRL = 0;
+	MEMC->SRAM_REMAP_CTRL;
+#endif	
+}
+
+void spl_board_init(void)
+{
+	bcm_otp_init();
+	bcm_sec_init();
+	bcm_sec_cb_arg_t cb_args[SEC_CTRL_ARG_MAX] = {0};
+	cb_args[SEC_CTRL_ARG_KEY].arg[0].ctrl = SEC_CTRL_KEY_GET;
+	bcm_sec_do(SEC_SET, cb_args);
+	sec_tk();
+	bcm_sec_deinit();
+	while(1);
+}
diff --git a/board/broadcom/bcmbca/board_tpl.c b/board/broadcom/bcmbca/board_tpl.c
new file mode 100644
index 0000000000..6c219ba6da
--- /dev/null
+++ b/board/broadcom/bcmbca/board_tpl.c
@@ -0,0 +1,644 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+#define DEBUG
+#include <common.h>
+#include <mmc.h>
+#include <spl.h>
+#include <nand.h>
+#if defined(CONFIG_ARM64)
+#include <asm/armv8/mmu.h>
+#endif
+
+#include "spl_ddrinit.h"
+#include "bcmbca_nand_spl.h"
+#include "bca_common.h"
+#include "bca_sdk.h"
+#include "bcm_bootstate.h"
+#include <time.h>
+#include <ubispl.h>
+#include "early_abort.h"
+#include "tpl_params.h"
+#include "spl_env.h"
+#include <environment.h>
+#include <hexdump.h>
+#include "bcmbca-dtsetup.h"
+#include "bcm_secure.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+tpl_params __attribute__((section(".data"))) * tplparams = NULL;
+
+static struct bcasdk_ctx sdk_ctx = {};
+
+static void update_uboot_fdt_sdk(void *fdt_addr);
+void save_boot_params_ret(void);
+static int get_fit_load_vol_id(void *info);
+static void update_uboot_fdt_sdk(void *fdt_addr)
+{
+ 	int offset;
+	
+	offset=fdt_path_offset (fdt_addr, "/chosen");
+	if(offset >= 0)
+	{
+		if (sdk_ctx.last_reset_reason >= 0) {
+			if(fdt_setprop_u32(fdt_addr, offset, "reset_reason", sdk_ctx.last_reset_reason))
+			{
+				printf("Could not set reset reason node in the fdt, device may not boot properly\n");
+			}
+		}
+		if(fdt_setprop_u32(fdt_addr, offset, "active_image", sdk_ctx.active_image))
+		{
+			printf("Could not set image node in the fdt, device may not boot properly\n");
+		}
+	}
+}
+
+__weak void boost_cpu_clock(void)
+{
+
+}
+
+/* called from start.S. No stack use. */
+void save_boot_params(void* params)
+{
+	tplparams = (tpl_params*)params;
+	save_boot_params_ret();
+}
+
+#if !defined(CONFIG_BCMBCA_IKOS)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	bcm_sec_delg_cfg * delg_cfg = NULL;
+
+	update_uboot_fdt(spl_image->fdt_addr, tplparams);
+	update_uboot_fdt_sdk(spl_image->fdt_addr);
+	bcm_sec_ctrl_arg_t arg = {.ctrl = SEC_CTRL_KEY_CHAIN_RSA, 
+				.ctrl_arg = spl_image->fdt_addr} ;
+	bcm_sec_update_ctrl_arg(&arg, SEC_CTRL_ARG_KEY);
+
+	/* Check if delegation is active inorder to pass encoded keys */
+	delg_cfg = bcm_sec_get_delg_cfg();
+	if( delg_cfg && delg_cfg->delg_id ) {
+		arg.ctrl = SEC_CTRL_KEY_CHAIN_ENCKEY;
+	} else {
+		arg.ctrl = SEC_CTRL_KEY_CHAIN_AES;
+	}
+	bcm_sec_update_ctrl_arg(&arg, SEC_CTRL_ARG_KEY);
+
+	/* Check if delegation is active to pass export items */
+	if( delg_cfg && delg_cfg->delg_id ) {
+		arg.ctrl = SEC_CTRL_KEY_EXPORT_ITEM;
+		bcm_sec_update_ctrl_arg(&arg, SEC_CTRL_ARG_KEY);
+	}
+	bcm_sec_do(SEC_SET, NULL);
+}
+#endif
+
+#if defined(CONFIG_MMC)
+#define MMC_DEV_NUM 	0
+#if defined(CONFIG_SUPPORT_EMMC_BOOT)
+u32 spl_boot_mode(const u32 boot_device)
+{
+	return MMCSD_MODE_RAW;
+}
+#endif	
+
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
+static int board_tpl_load_mmc_part(struct blk_desc *bd, disk_partition_t * info, void * buffer)
+{
+	int ret = 0;
+	unsigned long count;
+	unsigned long sector = info->start;
+	unsigned long num_blocks = info->size;
+
+	/* read image header to find the image size & load address */
+	count = blk_dread(bd, sector, num_blocks, buffer);
+	printf("%s: read sector %lx, count=%lu\n", __FUNCTION__, sector, count);
+	if (count == 0) {
+		ret = -EIO;
+	}
+	return ret;
+}
+
+int spl_boot_partition(const u32 boot_device)
+{
+	int fit_part_id = 0;
+	disk_partition_t info;
+	
+	fit_part_id = get_fit_load_vol_id((void*)&info);
+
+	return fit_part_id;
+}
+#endif
+#endif /* CONFIG_MMC */
+
+char *imgdev_name = NULL;
+#if !defined(CONFIG_BCMBCA_IKOS)
+void board_boot_order(u32 *spl_boot_list)
+{
+	int i=0;
+
+	unsigned long iargs[4];
+	char units[4];
+	int n;
+	n = parse_env_string_plus_nums(find_spl_env_val
+				       (tplparams->environment, "IMAGE"), &imgdev_name,
+				       4, iargs, units);
+	if (n > 0) {
+		printf("IMAGE is %s\n", imgdev_name);
+
+#if defined(CONFIG_NAND_BRCMNAND) || defined(CONFIG_MTD_SPI_NAND)	
+		if (strcmp(imgdev_name,"NAND") == 0) {
+			spl_boot_list[i++] = BOOT_DEVICE_BOARD;
+		}
+#endif
+
+#if defined(CONFIG_MMC)		
+		if (strcmp(imgdev_name,"EMMC") == 0) {
+			spl_boot_list[i++] = BOOT_DEVICE_MMC1;
+		}
+#endif	
+
+#if defined(CONFIG_TPL_SPI_FLASH_SUPPORT)
+		if (strcmp(imgdev_name,"SPINOR") == 0) {
+			spl_boot_list[i++] = BOOT_DEVICE_NOR;
+		}
+#endif		
+
+	} else {
+		printf("IMAGE environment variable not found in env at %p!\n", tplparams->environment);
+	}
+
+
+	spl_boot_list[i++] = BOOT_DEVICE_NONE;
+}
+#endif
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+int reserve_mmu(void)
+{
+	gd->arch.tlb_addr = CONFIG_SYS_PAGETBL_BASE;
+	gd->arch.tlb_size = CONFIG_SYS_PAGETBL_SIZE;
+
+	return 0;
+}
+
+/* 
+ * flush and invalid cache before launch u-boot.
+ * this function is called by board_init_r after u-boot image loaded.
+ */
+void spl_board_prepare_for_boot(void)
+{
+	cleanup_before_linux();
+}
+#endif
+void board_init_f(ulong dummy)
+{
+#if defined(CONFIG_ARCH_CPU_INIT)
+	arch_cpu_init();
+#endif
+
+#if defined(CONFIG_SYS_ARCH_TIMER)
+	timer_init();
+#endif
+
+#if !defined(CONFIG_ARM64)
+	spl_set_bd();
+#endif
+
+	if (spl_early_init())
+		hang();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	dram_init();
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+	reserve_mmu();
+	enable_caches();
+#endif
+
+	if (tplparams->environment != (void*)(TPL_ENV_ADDR)) {
+		printf("Invalid environment address 0x%p! Should be 0x%x.\n",
+			tplparams->environment, TPL_ENV_ADDR);
+		hang();
+	}
+
+	if (bcm_otp_init()) {
+		hang();
+	}
+	bcm_sec_init();
+	bcm_sec_cb_arg_t cb_args[SEC_CTRL_ARG_MAX] = {0};
+	cb_args[SEC_CTRL_ARG_KEY].arg[0].ctrl = SEC_CTRL_KEY_GET;
+	bcm_sec_do(SEC_SET, cb_args);
+#if defined(BUILD_TAG)
+	printf("$TPL: "BUILD_TAG" $\n");
+#endif
+
+#if defined(CONFIG_BCM_BOOTSTATE)
+	bca_bootstate_probe();
+#endif
+}
+
+int dram_init(void)
+{
+	gd->ram_base = 0x0;
+	gd->ram_size = min(PHYS_SDRAM_1_SIZE, ((u64) tplparams->ddr_size << 20));
+	gd->bd->bi_dram[0].start = 0x00;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+#if defined(CONFIG_ARM64)
+	/* update memory size in mmu table*/
+	mem_map[0].virt = mem_map[0].phys = gd->ram_base;
+	mem_map[0].size = gd->ram_size;
+#endif
+        return 0;
+}
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_BCMBCA_PMC)
+	pmc_initmode();
+#endif
+#if !defined(CONFIG_BCMBCA_IKOS)
+	boost_cpu_clock();
+#endif
+}
+
+int board_fit_config_name_match(const char *name)
+{
+#ifdef CONFIG_BCMBCA_BOARD_SPECIFIC_DT
+	static char *boardid = NULL;
+	
+	if(!boardid && !(tplparams->early_flags & SPL_EA_IGNORE_BOARDID))
+		boardid = find_spl_env_val(tplparams->environment, "boardid");
+	
+	return strcasecmp(boardid, name);
+#else
+	return 0;
+#endif //#ifdef CONFIG_BCMBCA_BOARD_SPECIFIC_DT
+}
+
+struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
+{
+	return (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS;
+}
+
+#ifdef CONFIG_NAND
+static ulong tpl_load_read(struct spl_load_info *load, ulong sector,
+			       ulong count, void *buf)
+{
+	debug("%s: sector %lx, count %lx, buf %p\n", __func__, sector, count,
+	      buf);
+	if(buf != (void *)sector)
+		memcpy(buf, (void *)sector, count);
+
+	return count;
+}
+
+// TBD
+struct metadata_s {
+};
+
+__weak int get_raw_metadata(void *buffer, struct ubispl_info *info, int n)
+{
+	int r = 0;
+	int v;
+#if defined(CONFIG_MMC)
+	struct mmc *mmc; 
+	struct blk_desc *bd;
+#endif	
+	struct ubispl_load volume;
+	int volmap[] = { METADATA_VOL_ID_1, METADATA_VOL_ID_2, -1 };
+	v = volmap[n];
+	if (v >= 0) {
+		if (strcmp(imgdev_name,"NAND") == 0) {  
+			volume.vol_id = v;
+			volume.load_addr = buffer;
+			if (0 > ubispl_load_volumes((struct ubispl_info *)info, &volume, 1)) {
+				return (-1);
+			}
+#if defined(CONFIG_MMC)
+		} else if (strcmp(imgdev_name,"EMMC") == 0) {
+			mmc = find_mmc_device(0);
+			bd = mmc_get_blk_desc(mmc);
+			memset(info, 0, sizeof(disk_partition_t));
+			if( part_get_info(bd, v, (disk_partition_t *)info) ) {
+				printf("Error: Invalid gpt partition %d\n", v);
+				return (-1);
+			} else {
+#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION)
+				if( board_tpl_load_mmc_part(bd, info, buffer) < 0) {
+					printf("Error: Read from gpt partition %d failed!\n", v); 
+					return (-1);
+				}
+#endif
+			}
+#endif			
+		}
+		r = 1;
+	}
+	return (r);
+}
+
+/* FIXME -- break into 
+ *   get_raw_metatdata()  just fetch metadata copy N into a buffer 
+ *   validate_metadata()  given buffer, return committed and valid
+ *   get_reboot_volatile_flags()
+ *   set_reboot_volatile_flags()
+ *   get_fit_load_id() -- combine above to return volid or partid
+ */
+static int get_fit_load_vol_id(void *info)
+//static int get_fit_load_vol_id(struct ubispl_info *info)
+{
+	int fit_vol_id = IMAGE_VOL_ID_1;
+	int selected_img_idx = 1;
+	char *cp;
+	int valid[2] = { 0, 0 };
+	int seq[2] = { -1, -1 };
+	int committed = 1;
+	int r;
+	int v = 0;
+	int boot_strap_detected = 0;
+	volatile int imgmap[ACTIVE_IMGIDX_MAX+1] = { -1, IMAGE_VOL_ID_1, IMAGE_VOL_ID_2 };
+	while (1 == 1) {
+		cp = (char *)spl_get_load_buffer(0, 0);
+		r = get_raw_metadata(cp, info, v);
+		if (0 == r) {
+			/* no more copies */
+			printf("no metadata -- using defaults\n");
+			boot_strap_detected = 1;
+			break;
+		} else if (r < 0) {
+			/* read error on copy */
+			v++;
+			continue;
+		}
+		if (0 == validate_metadata(cp, valid, &committed, seq)) {
+			break;
+		}
+		printf("metadata copy %d crc bad\n", v);
+		v++;
+	}
+	
+	if ((valid[0] == 0) && (valid[1] == 1)) {
+		selected_img_idx = 2;
+	} else if ((valid[0] == 1) && (valid[1] == 0)) {
+		selected_img_idx = 1;
+	} else {
+		if( committed )
+			selected_img_idx = committed;
+	}
+
+	sdk_ctx.last_reset_reason = 0;
+#if defined(CONFIG_BCM_BOOTSTATE)
+	r = bcmbca_get_reset_status();
+	printf("RESET STATUS is 0x%x\n",r);
+	if (r & SW_RESET_STATUS) {
+#if defined(CONFIG_BCM63138)
+		/* there's a hardware bug in the 63138 where a power-up boot reports a software reset,
+			check for power-up value in register and if so set to zero */
+		if ((bcmbca_get_boot_reason() & 0xFFFF) == 0x22ff)
+		{
+			bcmbca_set_boot_reason(0);
+		}
+#endif
+		sdk_ctx.last_reset_reason = bcmbca_get_boot_reason();
+		printf("BOOT REASON is 0x%x\n",sdk_ctx.last_reset_reason);
+	}
+	bcmbca_set_boot_reason((sdk_ctx.last_reset_reason << 16) | BCM_BOOT_REASON_WATCHDOG | BCM_BOOT_PHASE_UBOOT);
+#endif
+
+	/* TODO -- if boot_once is set AND nonselected image is valid, switch selected image AND clear boot once */
+	if (valid[0] && valid[1] && ((sdk_ctx.last_reset_reason & BCM_BOOT_REASON_ACTIVATE) ||  (tplparams->early_flags & SPL_EA_IMAGE_FB)))
+	{
+		selected_img_idx = 3 - committed;
+	}
+
+	/* now look up volume ID for the selected image */
+	fit_vol_id = imgmap[selected_img_idx];
+	if( boot_strap_detected ) {
+		printf("SELECTED BOOTSTRAP Image FIT_VOL_ID is %d\n", fit_vol_id);
+		sdk_ctx.active_image = ACTIVE_IMGIDX_BOOTSTRAP;
+	} else {
+		printf("SELECTED Image %d FIT_VOL_ID is %d\n",selected_img_idx, fit_vol_id);
+		sdk_ctx.active_image = selected_img_idx;
+	}
+	return fit_vol_id;
+}
+
+static int log2exact(uint32_t num)
+{
+	int r = 0;
+	while (num > 1) {
+		r++;
+		num = num >> 1;
+	}
+	return(r);
+}
+
+#if !defined(CONFIG_BCMBCA_IKOS)
+/* This function is called after entire FIT header has been read into memory */
+void board_spl_fit_pre_load(struct spl_image_info * image_info, 
+	struct spl_load_info *load_info, void * fit, ulong start_sector, ulong sector_count)
+{
+ 	uint64_t loaded_size = sector_count * load_info->bl_len;
+	uint64_t required_size = bcm_sec_get_reqd_load_size(fit);
+
+	/* In the case where entire FIT image may not have been loaded to memory
+	 * at once, we may have a case where we havent loaded enough blocks to get 
+	 * the FIT signature */
+	if( loaded_size  < required_size ) {
+		/* Read required size */
+		sector_count = load_info->read(load_info, start_sector, 
+			(required_size/load_info->bl_len) + (required_size%load_info->bl_len?1:0), fit);
+		debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n",
+	      		start_sector, 
+			(required_size/load_info->bl_len) + (required_size%load_info->bl_len?1:0),
+			fit, sector_count, required_size);
+		loaded_size = sector_count * load_info->bl_len;
+	}
+
+	/* Authenticate FIT header and set security settings */
+	bcm_sec_validate_fit(fit, loaded_size);
+	bcm_sec_fit(fit);
+}
+#endif
+
+__weak int tpl_load_image(struct spl_image_info *spl_image,
+			  struct spl_boot_device *bootdev)
+{
+	int ret = -1;
+	struct ubispl_info info;
+	struct ubispl_load volume;
+	int page_size; 
+	void *fit = spl_get_load_buffer(0, 0);
+	uint64_t image_start = 1024 * 1024;
+	uint64_t image_end = (uint64_t)(-1);
+	uint64_t totalsize;
+	int log2_pebsize;
+	char *name;
+	unsigned long iargs[4];
+	char units[4];
+	int n;
+
+	/* For NAND devices, determine image_start and image_end */
+	n = parse_env_string_plus_nums(find_spl_env_val
+				       (tplparams->environment, "IMAGE"), &name,
+				       4, iargs, units);
+	if (n > 0) {
+		if (n > 1) {
+			image_start =
+			    ((uint64_t) iargs[0]) << suffix2shift(units[0]);
+			
+		}
+		if (n > 2) {
+			image_end =
+			    (uint64_t) iargs[1] << suffix2shift(units[1]);
+		}
+	}
+	free(name);
+
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	nand_init();
+#endif
+
+	info.read = nand_spl_read_block;
+	info.peb_size = nand_spl_get_blk_size();
+	log2_pebsize = log2exact(info.peb_size);
+	page_size = nand_spl_get_page_size();
+
+	info.ubi = (struct ubi_scan_info *)CONFIG_SPL_UBI_INFO_ADDR;
+	info.fastmap = IS_ENABLED(CONFIG_MTD_UBI_FASTMAP);
+
+	info.peb_offset = image_start >> log2_pebsize;
+	/* vid_offset and leb_start of page_size and 2*page_size respectively are dictated by ubinize with no subpage writes required */
+	info.vid_offset = page_size;
+	info.leb_start = 2 * page_size ;
+	totalsize = nand_spl_get_total_size();
+	if (image_end == (uint64_t) (-1)) {
+		image_end = totalsize;
+	} else if (image_end > totalsize) {
+		image_end = totalsize - 8 * info.peb_size;
+		printf("INFO: IMAGE specified beyond flash size... using flash up to the end for image\n");
+	}
+	info.peb_count = (image_end >> log2_pebsize) - info.peb_offset;
+	debug("image from %lld to %lld\n",image_start, image_end); 
+	
+	volume.vol_id = get_fit_load_vol_id(&info);
+	volume.load_addr = fit;
+
+	ret = ubispl_load_volumes(&info, &volume, 1);
+	  
+	if (!ret && (image_get_magic(fit) == FDT_MAGIC)) {
+		struct spl_load_info load;
+		debug("Found FIT format U-Boot\n");
+
+		load.bl_len = 1;
+		load.read = tpl_load_read;
+		ret = spl_load_simple_fit(spl_image, &load, (long)fit, fit);
+	}
+
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	nand_deselect();
+#endif
+
+	return ret;
+}
+
+SPL_LOAD_IMAGE_METHOD("NAND", 0, BOOT_DEVICE_BOARD, tpl_load_image);
+#endif /* CONFIG_NAND */
+#if defined(CONFIG_TPL_SPI_FLASH_SUPPORT)
+static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector,
+			      ulong count, void *buf)
+{
+	ulong ret;
+	size_t retlen;
+	struct mtd_info *mtd = load->dev;
+
+	ret = mtd_read(mtd, sector, count, &retlen, buf);
+	if (!ret)
+		return retlen;
+	else
+		return 0;
+}
+
+static int tpl_spinor_load_image(struct spl_image_info *spl_image,
+			  struct spl_boot_device *bootdev)
+{
+	int ret = -1;
+	char *name;
+	int n;
+	unsigned long iargs[4];
+	unsigned long image_start;
+	int use_spinor = 0;
+	char units[4];
+	struct udevice *dev;
+	struct mtd_info *mtd;
+	size_t retlen;	
+	void *fit = spl_get_load_buffer(0, 0);
+
+	n = parse_env_string_plus_nums(find_spl_env_val
+				       (tplparams->environment, "IMAGE"), &name,
+				       4, iargs, units);
+	if (n > 0) {
+		debug("IMAGE is %s\n",name);
+		if (strcmp(name,"SPINOR") == 0) {
+			use_spinor = 1;
+			if (n > 1) {
+				image_start = iargs[0]<< suffix2shift(units[0]);
+				
+			}
+		}
+	}
+	free(name);
+	if (!use_spinor){
+		debug("Lack of SPINOR image env setting.\n");
+		goto done;
+	}
+
+	ret = uclass_get_device_by_driver(UCLASS_SPI_FLASH, DM_GET_DRIVER(spi_flash_std), &dev);
+	if (ret){
+		debug("SPI NOR failed to initialize. (error %d)\n", ret);
+		goto done;
+	}
+	mtd = get_mtd_device_nm(SPIFLASH_MTDNAME);
+	if (IS_ERR_OR_NULL(mtd)){
+		debug("%s:MTD device %s not found, ret %ld\n",__func__, SPIFLASH_MTDNAME,
+		   PTR_ERR(mtd));
+		ret = -1;
+		goto done;
+	}
+
+	/* Load u-boot, mkimage header is 64 bytes. */
+	ret = mtd_read(mtd, image_start, sizeof(struct image_header), &retlen,fit);
+	if (ret) {
+		debug("%s: Failed to read from SPI flash (err=%d)\n", __func__, ret);
+		goto done;
+	}
+	if (image_get_magic(fit) == FDT_MAGIC) {
+		struct spl_load_info load;
+
+		debug("Found FIT format U-Boot\n");
+		load.dev = mtd;
+		load.priv = NULL;
+		load.filename = NULL;
+		load.bl_len = 1;
+		load.read = spl_spi_fit_read;
+		debug("spl_load_simple_fit from %d\n",image_start);
+		ret = spl_load_simple_fit(spl_image, &load, image_start, fit);
+
+		//spi nor, hard code active_image  to 1		
+		sdk_ctx.active_image = 1;
+	}
+done:
+	put_mtd_device(mtd);
+	return ret;
+}
+
+SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_NOR, tpl_spinor_load_image);
+#endif
+
diff --git a/board/broadcom/bcmbca/boot_blob.c b/board/broadcom/bcmbca/boot_blob.c
new file mode 100644
index 0000000000..80ceb318dc
--- /dev/null
+++ b/board/broadcom/bcmbca/boot_blob.c
@@ -0,0 +1,237 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/* define DEBUG before common.h to enable debug macro */
+#define DEBUG
+#include <common.h>
+#include <environment.h>
+#include <nand.h>
+#include <u-boot/sha256.h>
+#include "boot_blob.h"
+#include "boot_flash.h"
+#include "spl_env.h"
+
+/* overlay entry table */
+#include "generated/hashtable.h"
+
+static int search_blob_in_hash(uint32_t magic, uint32_t sel, int *len,
+			       uint8_t * sha256)
+{
+	struct overlays entry;
+	int i = 0, offset = -1;
+
+	do {
+		entry = ovl[i];
+		if (entry.ovltype == 0)
+			break;
+
+		if (entry.ovltype == magic && entry.selector == sel) {
+			offset = entry.offset;
+			memcpy(sha256, entry.sha, 32);
+			*len = entry.size;
+			break;
+		}
+		i++;
+
+	} while (1);
+
+	if (offset == -1)
+		printf("blob not found for magic 0x%x sel 0x%x!\n", magic, sel);
+
+	return offset;
+}
+
+static int validate_blob_sha256_digest(void *buf, int size, void *pdigest)
+{
+	uint8_t out[32];
+	sha256_context ctx;
+	sha256_starts(&ctx);
+	sha256_update(&ctx, buf, size);
+	sha256_finish(&ctx, out);
+	return memcmp(pdigest, out, 32);
+}
+
+static struct magic_search_s {
+	uint32_t index;
+	uint32_t last;
+	uint32_t length;
+	uint32_t dpfe_fs; /* dpfe blob fast search */  
+	uint32_t magics[BOOT_BLOB_MAX_MAGIC_NUMS][BOOT_BLOB_MAX_MAGIC_SEARCH + 1];
+} magic_search;
+
+static void init_find_magic(void)
+{
+	int col, i;
+	uint32_t e;
+	printf("FFinit ");
+	if (magic_search.last != 0) {
+		return;
+	}
+	i = 0;
+	while ((e = ovl[i].ovltype) != 0) {
+		for (col = 0; col < BOOT_BLOB_MAX_MAGIC_NUMS; col++) {
+			if (magic_search.magics[col][0] == e) {
+				break;
+			} else if (magic_search.magics[col][0] == 0) {
+				magic_search.magics[col][0] = e;
+				break;
+			}
+		}
+		i++;
+	}
+	printf("done\n");
+
+}
+
+static int is_magic_match(uint32_t magic)
+{
+	/* DPFE blob maigc last nibble is the segment id. Ignore it */
+	if ( IS_DPFE_MAGIC(magic_search.last))
+		return ((magic_search.last&DPFE_MAGIC_MASK)
+			== (magic&DPFE_MAGIC_MASK));
+	else
+		return (magic_search.last == magic);
+}
+
+static uint32_t find_magic(uint32_t magic)
+{
+	boot_blob_hdr hdr;
+	uint32_t found;
+	uint32_t end_addr = BOOT_BLOB_SEARCH_END_ADDR;
+
+	if (!is_magic_match(magic)) {
+		init_find_magic();
+		magic_search.index = BOOT_BLOB_SEARCH_START_ADDR;
+	}
+
+	/* TODO start with cached offsets if already located ... */
+	/* debug("look for magic number 0x%x starting at address 0x%x\n", */
+	/*			   magic, magic_search.index); */
+	while (magic_search.index < end_addr) {
+		/* For DPFE segment blobs, all the segments are concontinous 
+		 * in the flash. So the subsequent segment will be at least 
+		 * at current addr + segment size. so we skip the search for 
+		 * current segment to redcue read on boot blocks
+		 */ 
+		if (IS_DPFE_MAGIC(magic_search.last) && magic == (magic_search.last+1)
+		    && magic_search.dpfe_fs) {
+			magic_search.index += ROUND(magic_search.length + sizeof(hdr),
+			    BOOT_BLOB_SEARCH_BOUNDARY);
+			/* printf("magic 0x%x skip current dpfe blob, quick search at 0x%x\n", 
+			      magic, magic_search.index);*/
+		}
+		
+		hdr.length = hdr.magic = 0;
+		/* if read fail, we hit bad block and revert back to 4k search */
+		if (read_boot_device(magic_search.index, &hdr, sizeof(hdr)) < 0)
+			magic_search.dpfe_fs = 0;
+
+		/* TODO cache other magic numbers location while searching ... */
+		found = magic_search.index;
+
+		/* Return magic if we found it */
+		if (hdr.magic == magic) {
+			debug("find magic number 0x%x at address 0x%x\n",
+				   magic, found);
+			magic_search.last = hdr.magic;
+			magic_search.length = hdr.length;
+			if (IS_DPFE_MAGIC(magic_search.last))
+				magic_search.dpfe_fs = 1;
+			return found;
+		} else {
+			magic_search.dpfe_fs = 0;
+		}
+
+		/* Update search index to point to next entry */
+		magic_search.index += BOOT_BLOB_SEARCH_BOUNDARY;
+	}
+	return ~0;
+}
+
+static int read_blob_from_flash(uint32_t magic, uint32_t offset, void *data,
+				int len, uint8_t * digest)
+{
+	uint32_t entry;
+	int ret = -1;
+
+	while ((entry = find_magic(magic)) < BOOT_BLOB_SEARCH_END_ADDR) {
+		printf("reading blob from 0x%x offset 0x%x len %d\n", entry, offset, len);
+		read_boot_device(entry + offset, data, len);
+		ret = validate_blob_sha256_digest(data, len, digest);
+		if (ret == 0) {
+			debug("digest sha256 OK\n");
+			return BOOT_BLOB_SUCCESS;
+		} else {
+			debug("digest sha256 mismatch\n");
+			magic_search.index += BOOT_BLOB_SEARCH_BOUNDARY;
+			magic_search.dpfe_fs = 0;
+		}
+	}
+
+	return BOOT_BLOB_MAGIC_NOT_FOUND;
+}
+
+int load_boot_blob(uint32_t magic, uint32_t sel, void *data, int* len)
+{
+	int offset;
+	int size;
+	unsigned char digest[32];
+
+	/* find out the offset of the blob from the hash table first */
+	if ((offset = search_blob_in_hash(magic, sel, &size, digest)) < 0)
+		return BOOT_BLOB_NOT_IN_HASTTBL;
+
+	if (size > *len) {
+		printf("buffer too small\n");
+		return BOOT_BLOB_INVALID_PARAM;
+	}
+
+	*len = size;
+	/* find out the first the blob with the magic number from flash */
+	return read_blob_from_flash(magic, offset, data, size, digest);
+}
+
+__weak void * load_spl_env(void *buffer)
+{
+	uint32_t entry;
+	uint32_t len;
+	uint32_t crc;
+	uint32_t got;
+	env_t *ep;
+	while ((entry =
+		find_magic(UBOOT_ENV_MAGIC)) < BOOT_BLOB_SEARCH_END_ADDR) {
+		uint32_t *d = (uint32_t *) buffer;
+		read_boot_device(entry, d, 8);
+		len = d[1];
+		if (len > BOOT_BLOB_MAX_ENV_SIZE) {
+			continue;
+		}
+		read_boot_device(entry, d, len + 12);
+		ep = (env_t *)(d+2);
+		memcpy(&crc, &ep->crc, sizeof(crc));
+
+		got = crc32(0, ep->data, len-4);
+
+		if (got != crc) {
+			debug("CRC mismatch len = %d\n",len);
+			debug("computed %x \n",got);
+			debug("expected %x \n",crc);
+			magic_search.index += BOOT_BLOB_SEARCH_BOUNDARY;
+		} else {
+			return(buffer);
+		}
+	}
+	return(NULL);
+}
+
+
+struct overlays* get_boot_blob_hash_entry(int i)
+{
+
+	if (i >= sizeof(ovl)/sizeof(struct overlays))
+		return NULL;
+	else
+		return &ovl[i];
+}
diff --git a/board/broadcom/bcmbca/boot_flash.c b/board/broadcom/bcmbca/boot_flash.c
new file mode 100644
index 0000000000..c00b82ff73
--- /dev/null
+++ b/board/broadcom/bcmbca/boot_flash.c
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+#include <common.h>
+#include <nand.h>
+#include <mmc.h>
+#include "boot_flash.h"
+
+#ifdef CONFIG_MMC
+#define MMC_DEV_NUM 0
+#define MMC_BOOT_HWPART 1
+#define MMC_USERDATA_PART 0
+#endif
+
+/* for emmc and spi flash*/
+void* flash_dev;
+
+int boot_flash_init(void)
+{
+	flash_dev = NULL;
+#ifdef CONFIG_NAND
+	nand_init();
+#endif
+
+#if defined(CONFIG_MMC) && defined(CONFIG_SUPPORT_EMMC_BOOT)
+	struct mmc *mmc;
+	int ret;
+	ret = mmc_initialize(NULL);
+	if(ret)	{
+		printf("MMC Initialization Failed!!\n");
+		hang();
+	}
+
+	mmc = find_mmc_device(MMC_DEV_NUM);
+	mmc_init(mmc);
+#endif
+
+#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
+	struct udevice *dev;
+	struct mtd_info *mtd;
+	int ret = -1;
+
+	ret = uclass_get_device_by_driver(UCLASS_SPI_FLASH, DM_GET_DRIVER(spi_flash_std), &dev);
+	if (ret){
+		debug("SPI NOR failed to initialize. (error %d)\n", ret);
+		hang();
+	}
+	mtd = get_mtd_device_nm(SPIFLASH_MTDNAME);
+	if (IS_ERR_OR_NULL(mtd)){
+		printf("%s:MTD device %s not found, ret %ld\n",__func__, SPIFLASH_MTDNAME,
+		   PTR_ERR(mtd));
+		hang();
+	}
+	else
+		flash_dev = mtd;
+#endif
+	return 0;
+}
+/* return number of bytes read if success, negative value if fail */
+int read_boot_device(uint32_t address, void *data, int len)
+{
+	int ret;
+#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
+	size_t retlen;	
+	debug("read_boot_device:address=%d,len=%d\n",address,len);
+	if ( flash_dev != NULL){
+		ret = mtd_read(flash_dev, address, len, &retlen, data);
+		if ( ret == 0)
+			ret = retlen;
+		else{
+			debug("%s: Failed to read from SPI flash (err=%d)\n", __func__, ret);
+			ret = -1;
+		}
+	}
+	else
+		ret = -1;
+#endif
+	
+#ifdef CONFIG_NAND
+	/* unfortunately nand spl api does not return the length.. */
+	ret = nand_spl_load_image(address, len, data);
+	if (ret == 0)
+		ret = len;
+	else
+		ret = -1;
+#endif
+
+#if defined(CONFIG_MMC) && defined(CONFIG_SUPPORT_EMMC_BOOT)
+	blk_select_hwpart_devnum(IF_TYPE_MMC, MMC_DEV_NUM, MMC_BOOT_HWPART);
+	/* Unfortunately mmc_spl_load_image has no return code */
+	mmc_spl_load_image(address, len, data);
+	ret = len;
+	blk_select_hwpart_devnum(IF_TYPE_MMC, MMC_DEV_NUM, MMC_USERDATA_PART);
+#endif
+
+#if defined(CONFIG_SPL_XIP_SUPPORT)
+	memcpy((uint8_t*)data, (uint8_t*)(address+NOR_XIP_BASE_ADDR), len);
+#endif
+	return ret;
+}
diff --git a/board/broadcom/bcmbca/early_abort.c b/board/broadcom/bcmbca/early_abort.c
new file mode 100644
index 0000000000..74bc65d770
--- /dev/null
+++ b/board/broadcom/bcmbca/early_abort.c
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+#include <spl.h>
+#include "early_abort.h"
+#include "bcm_secure.h"
+#include "spl_ddrinit.h"
+
+static  early_abort_t ea __attribute__((section(".data")));
+
+static char _get_char(void)
+{
+	return tstc() ? getc():'\0';
+}
+
+static void _flush_chars(void)
+{
+	mdelay(1500);
+	while(_get_char() != '\0');
+}
+
+static int catch_early_abort(void)
+{
+	/* listen for .5 s to catch */ 
+	uint32_t tm = SPL_EA_CATCH_TM_MS;
+	do {
+		if( _get_char() == 'a') {
+			return 0;
+		}
+		mdelay(1);
+	} while(--tm);
+	return 1;
+}
+
+static void early_abort_menu(void)
+{
+	const char *menu = "Use enter to confirm input menu selection\r\n"
+		"go - continue\r\n"
+		"ddr - mcb override(hex) or DDR safe mode.\r\n"
+		"\tddr (3|4) safe modes;\r\n" 
+		"\tddr <hex num>  passes selector value \r\n"
+		"r - Boot Fallback; 1 - recovery\r\n"
+		"bid - Ignore boardid while booting\r\n";
+	const char *menu_cont =
+		"mcb - List all the mcb selectors\r\n"
+#ifdef CONFIG_BCMBCA_EARLY_ABORT_JTAG_UNLOCK
+		"jtag - Unlock JTAG\r\n"
+#endif
+		"h - halt\r\n";
+
+	printf("%s", menu);
+	printf("%s", menu_cont);
+}
+
+static int _get_chars(char brk, char b[128])
+{
+	char *s =  b;
+	do {
+		char c = _get_char();
+		if (c == '\0' || (!isalpha(c) && !isdigit(c) && c != brk && !isspace(c))) {
+			continue;
+		}
+		if (c == brk) {
+			break;
+		}
+		putc(c);
+		*s++ = c;
+	} while(s - b < 127);
+	*s = '\0';
+	return s-b;
+}
+
+
+static inline char* _skpchr(const char* s, char c)
+{
+	char* p = (char*)s;
+	while(*p == c ) { p++; }
+	return p;
+}
+/* given the char c and tok - search for the pattern:
+ *  <tok|$>c<(tok)|\0*>
+ *
+ * */
+static char* _strchr_not_tok(const char* s, char c, char tok) 
+{
+	char *p = (char*)s;
+	if (*p == c) {
+		goto done ;
+	}
+	p = _skpchr(p, tok);
+	if (p == s) {	
+		return  NULL;
+	}
+done:
+	return (*p == c && (*(p+1) =='\0' || isspace(*(p+1))))? p : NULL;
+}
+
+__weak void early_abort(void)
+{
+	unsigned long tm = SPL_EA_TM_MS; 
+	spl_ea_status_t ddr_flags = SPL_EA_NONE,
+			ignore_boardid = SPL_EA_NONE,
+			image_flags = SPL_EA_NONE;
+	int chno = 0;
+	/* This function called early so avoiding usage of BS as much as possible.
+ 	* Stack MUST BE available  
+ 	* Using global pointer to convei
+ 	* early abort status
+ 	* */
+	if (catch_early_abort()) {
+		return;
+	}
+	/* print menu */
+	memset(&ea, 0, sizeof(ea));
+	early_abort_menu();
+	_flush_chars();
+	do {
+		char cbuf[128];
+		char* sel = cbuf;
+		mdelay(1);
+		if (!serial_tstc()) {
+			continue;
+		}
+		chno =  _get_chars('\r', sel);
+		sel = _skpchr(sel, ' ');
+		if (!strncmp(sel, "ddr", 3)) {
+			/* grab hex for selector */
+			char * p = _strchr_not_tok(sel + 3, '3', ' ');
+			if (p) {
+				ddr_flags =  SPL_EA_DDR3_SAFE_MODE;
+						printf("\r\nSafe Mode - DDR%c\n",*p);
+			} else {
+				p = _strchr_not_tok(sel + 3, '4', ' ');
+				if (p) {
+					ddr_flags =  SPL_EA_DDR4_SAFE_MODE;
+					printf("\r\nSafe Mode - DDR%c\n",*p);
+				} else {
+					char * p = sel + 3;
+					unsigned long val;
+					p = _skpchr(p, ' ');
+					val = simple_strtoul(p, NULL, 16);
+					if (val != -EINVAL) {
+						ddr_flags = SPL_EA_DDR_MCB_SEL;
+						ea.data = val;
+						printf("\r\nMCB selector 0x%lx\r\n", val);
+					} else {
+						ddr_flags =  SPL_EA_DDR3_SAFE_MODE;
+						printf("\r\nSafe Mode - DDR3\r\n");
+					}
+				}
+			}
+		} else if (!strncmp(sel,"go", 2)) {
+			/*done get out*/
+			break;
+		} else if (*sel == 'r') {
+			char * p = _strchr_not_tok(sel + 1 , '1', ' '); 
+			image_flags = p && *p=='1'?
+				SPL_EA_IMAGE_RECOV : SPL_EA_IMAGE_FB;
+			printf("\r\nBoot Image: %s \r\n",
+				(image_flags&SPL_EA_IMAGE_RECOV)?"Recovery":"Fallback");
+		} else if (*sel == 'h') {
+			/*resetting timeout; 
+ * 				started polling almost infinitely*/
+			tm = -1;
+			printf("\r\nHalted\r\n");
+#ifdef CONFIG_BCMBCA_EARLY_ABORT_JTAG_UNLOCK
+		} else if (*sel == 'j'|| !strncmp(sel,"jtag", 4)) {
+			bcm_sec_cb_arg_t cb_args[SEC_CTRL_ARG_MAX] = {0}; 
+			cb_args[SEC_CTRL_ARG_SOTP].arg[0].ctrl = SEC_CTRL_SOTP_LOCK_ALL;
+			cb_args[SEC_CTRL_ARG_KEY].arg[0].ctrl = SEC_CTRL_KEY_CLEAN_ALL;
+			bcm_sec_do(SEC_SET, cb_args);
+			BCM_SEC_UNLOCK_JTAG;
+			ea.status |= SPL_EA_JTAG_UNLOCK;
+			printf("\r\nUnlocked\r\n");
+#endif
+		} else if (!strncmp(sel, "bid", 3)) {
+			ignore_boardid = SPL_EA_IGNORE_BOARDID;
+			printf("\r\nIgnore boardid while booting\r\n");
+		} else if (!strncmp(sel, "mcb", 3)) {
+#ifdef CONFIG_BCMBCA_DDRC
+			spl_list_mcb_sel();
+#endif
+		} else if (chno){
+			 
+			putc('\r');
+			do {
+				putc(' ');
+			} while(--chno);
+			putc('\r');
+		} 
+
+	} while(--tm);
+	if (ddr_flags || image_flags || ignore_boardid) {
+		ea.status |= (ddr_flags|image_flags|ignore_boardid);
+	}
+	/*printf("Time out counter at %lu\n",tm);*/
+}
+
+early_abort_t* early_abort_info()
+{
+	return &ea;
+}
diff --git a/board/broadcom/bcmbca/flashback.c b/board/broadcom/bcmbca/flashback.c
new file mode 100644
index 0000000000..40cc0791a9
--- /dev/null
+++ b/board/broadcom/bcmbca/flashback.c
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+
+#include <asm/arch/ddr.h>
+#include <linux/ctype.h>
+#include <mtd.h>
+#include <nand.h>
+#include <stdlib.h>
+#include <string.h>
+#include <environment.h>
+#include <cli.h>
+#include <linux/bitops.h>
+#include <linux/crc32.h>
+#include <ubi_uboot.h>
+#include "bca_common.h"
+#include "bca_sdk.h"
+#include "spl_env.h"
+
+struct recovery_chunks {
+	int flashpage;		// page in flash
+	int size;		// number of bytes before fill
+	int type;		// 0x0= fill with 0xff, 0x1 = fill with 0x00, 0x7fffffff = END
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int erase(struct mtd_info *mtd, int first, int blocks);
+
+static int erase(struct mtd_info *mtd, int first, int blocks)
+{
+	struct erase_info erase_op = { };
+	int ret;
+
+	erase_op.mtd = mtd;
+	erase_op.addr = first * mtd->erasesize;
+	erase_op.len = blocks * mtd->erasesize;
+	erase_op.scrub = 0;
+	printf("Erasing %d blocks from block %d\n", blocks, first);
+
+	while (erase_op.len) {
+		ret = mtd_erase(mtd, &erase_op);
+
+		/* Abort if its not a bad block error */
+		if (ret != -EIO)
+			break;
+
+		printf("Skipping bad block at 0x%08llx\n", erase_op.fail_addr);
+
+		/* Skip bad block and continue behind it */
+		erase_op.len -= erase_op.fail_addr - erase_op.addr;
+		erase_op.len -= mtd->erasesize;
+		erase_op.addr = erase_op.fail_addr + mtd->erasesize;
+	}
+
+	if (ret && ret != -EIO)
+		ret = -1;
+	else
+		ret = 0;
+	return (ret);
+};
+
+
+static int do_flashback(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[]);
+static int do_flashback(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	struct mtd_info *mtd = NULL;
+	struct recovery_chunks *recovery_chunks_list = CONFIG_SYS_LOAD_ADDR;
+	long offset;
+	int i;
+	size_t sz = 0;
+	int blocks, pages;
+	int ret = 0;
+	char *bp;
+	int chunk;
+	mtd = get_mtd_device_nm("nand0");
+	blocks = (mtd->size / mtd->erasesize);
+	pages = (mtd->erasesize / mtd->writesize);
+	erase(mtd, 0, blocks);
+	chunk = 0;
+	bp = &recovery_chunks_list[blocks * pages + 1];
+	while (recovery_chunks_list[chunk].type < 0x1000) {
+		i = mtd_write(mtd,
+			      recovery_chunks_list[chunk].flashpage *
+			      mtd->writesize, mtd->writesize, &sz, bp);
+		bp += recovery_chunks_list[chunk].size;
+		chunk++;
+		printf("%d ", chunk);
+	}
+	put_mtd_device(mtd);
+	return(0);
+}
+
+static char usage[] = "line 1...\n" "line 2...\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(flashback_ops, "flashback commands", usage,
+			U_BOOT_SUBCMD_MKENT(go_flashback, 1, 0, do_flashback)
+					    );
+
+
diff --git a/board/broadcom/bcmbca/httpd/Makefile b/board/broadcom/bcmbca/httpd/Makefile
new file mode 100644
index 0000000000..d5edf9d929
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+
+# ccflags-y += -save-temps
+
+obj-$(CONFIG_BCMBCA_HTTPD) += bcmbca_net.o
+obj-$(CONFIG_BCMBCA_HTTPD) += httpd.o
+obj-$(CONFIG_BCMBCA_HTTPD) += uip.o
+obj-$(CONFIG_BCMBCA_HTTPD) += uip_arch.o
+obj-$(CONFIG_BCMBCA_HTTPD) += uip_arp.o
+
+
diff --git a/board/broadcom/bcmbca/httpd/bcmbca_net.c b/board/broadcom/bcmbca/httpd/bcmbca_net.c
new file mode 100644
index 0000000000..6fe242c80e
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/bcmbca_net.c
@@ -0,0 +1,296 @@
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <errno.h>
+#include <net.h>
+
+#include "uipopt.h"
+#include "uip.h" 
+#include "uip_arp.h"
+#include "httpd.h"
+#include "bca_sdk.h"
+#include "bca_common.h"
+
+typedef enum
+{
+	HTTP_IMG_UPGRADE_IDLE,
+	HTTP_IMG_UPGRADE_INPROGRESS,
+	HTTP_IMG_UPGRADE_OK,
+	HTTP_IMG_UPGRADE_WAIT_RESET,
+	HTTP_IMG_UPGRADE_FAIL,
+} HTTP_IMG_UPGRADE_STATE;
+
+static HTTP_IMG_UPGRADE_STATE http_upgrade_state = HTTP_IMG_UPGRADE_IDLE;
+static uint64_t httpd_reset_wait_start_ticks = 0;
+static uint64_t httpd_reset_wait_timeout_sec = 0;
+
+extern int (*ip_tap)(uchar *in_packet, int len, struct ip_udp_hdr *ip);
+
+#define HTTPD_RESET_WAIT_SEC	3	/* Amount of seconds to wait before triggering device reset */
+#define IPPROTO_TCP		6	/* Trasmission Control Protocol	*/
+
+extern void (*jobs_func)(void);
+
+void send_httpd(void)
+{
+	volatile uchar *tmpbuf;
+	uchar *tx_packet;
+	int i;
+	
+	tx_packet = net_get_async_tx_pkt_buf();
+	tmpbuf = tx_packet;
+
+	for(i = 0; i < 40 + UIP_LLH_LEN; i++)
+		tmpbuf[i] = uip_buf[i];
+
+	for(; i < uip_len; i++)
+		tmpbuf[i] = uip_appdata[i - 40 - UIP_LLH_LEN];
+
+	net_send_packet(tx_packet, uip_len);
+}
+
+int httpd_check_net_env(void)
+{
+	char eth_addr[6];
+	
+	if(!env_get("ipaddr"))
+	{
+		printf("HTTPD: ipaddr not defined\n");
+		return -1;
+	}
+
+	if(!env_get("netmask"))
+	{
+		printf("HTTPD: netmask not defined\n");
+		return -1;
+	}
+	
+	if(!eth_env_get_enetaddr("ethaddr",eth_addr))
+	{
+		printf("HTTPD: ethaddr not defined\n");
+		return -1;
+	}
+	printf("HTTPD: ready for starting\n");
+	return 0;
+}
+
+void httpd_start(void)
+{
+	struct uip_eth_addr eaddr;
+	unsigned short ip[2];
+	char eth_addr[6];
+	char *ip_addr = NULL, *net_mask = NULL;
+
+	uip_init();
+
+	ip_addr = env_get("ipaddr");
+	if(ip_addr)
+	{
+		net_ip = string_to_ip(ip_addr);
+	}
+	else
+	{
+		printf("httpd_start: ipaddr not defined\n");
+		return;
+	}
+	net_mask = env_get("netmask");
+	if(net_mask)
+	{
+		net_netmask = string_to_ip(net_mask);
+	}
+	else
+	{
+		printf("httpd_start: netmask not defined\n");
+		return;
+	}
+
+	ip[0] = net_ip.s_addr & 0x0000FFFF;
+	ip[1] = (net_ip.s_addr & 0xFFFF0000) >> 16;
+	uip_sethostaddr(ip);
+
+	ip[0] = net_netmask.s_addr & 0x0000FFFF;
+	ip[1] = (net_netmask.s_addr & 0xFFFF0000) >> 16;
+	
+	uip_setnetmask(ip);	
+	
+	if(eth_env_get_enetaddr("ethaddr",eth_addr))
+	{
+		memcpy(net_ethaddr, eth_addr, 6);
+	}
+	else
+	{
+		printf("httpd_start: ethaddr not defined\n");
+		return;
+	}
+	memcpy(eaddr.addr, net_ethaddr, 6);
+	uip_setethaddr(eaddr);
+
+	uip_listen(HTONS(80));
+}
+
+int httpd_poll_post_process(void)
+{
+	/* Handle device reset after succesfull image upgrade */
+	if( http_upgrade_state == HTTP_IMG_UPGRADE_WAIT_RESET )
+	{
+		if( get_ticks() - httpd_reset_wait_start_ticks > httpd_reset_wait_timeout_sec * get_tbclk())
+			do_reset(NULL, 0, 0, NULL);
+	}
+}
+
+int http_rcv(uchar *in_packet, int len, struct ip_udp_hdr *ip)
+{
+	if(ip->ip_p == IPPROTO_TCP)
+	{
+		if(len > sizeof(uip_buf))
+		{
+			printf("TCP/IP packet len %d > uip buffer %d\n", len, sizeof(uip_buf));
+			return 1;
+		}
+		memcpy(uip_buf, in_packet, len);
+		uip_arp_ipin();
+		uip_input();
+		if(uip_len > 0)
+		{
+			uip_arp_out();
+			send_httpd();
+		}
+
+		if( uip_aborted() && (http_upgrade_state != HTTP_IMG_UPGRADE_WAIT_RESET) )
+			http_upgrade_state = HTTP_IMG_UPGRADE_IDLE;
+
+		/* If upgrade succeeded, reset after sending confirmation page */
+		if( http_upgrade_state > HTTP_IMG_UPGRADE_INPROGRESS )
+		{
+			/* Issue reset after sending update page if upgrade was good */
+			switch(http_upgrade_state) 
+			{
+				case HTTP_IMG_UPGRADE_OK:
+					/* Prepare to close TCP connection */
+					uip_close();
+					/* Set state to waiting for reset */
+					http_upgrade_state = HTTP_IMG_UPGRADE_WAIT_RESET;
+					/* Arm the reset counter */
+					httpd_reset_wait_start_ticks = get_ticks();
+					httpd_reset_wait_timeout_sec = HTTPD_RESET_WAIT_SEC;
+					printk("Resetting in %d seconds....\n", httpd_reset_wait_timeout_sec);
+				break;
+
+				case HTTP_IMG_UPGRADE_WAIT_RESET:
+					/* Do nothing */
+				break;
+
+				default:
+					http_upgrade_state = HTTP_IMG_UPGRADE_IDLE;
+				break;
+			}
+		}
+
+		return 1;
+	}
+	return 0;
+}
+
+STREAM_UPGRADE_STATUS http_get_upgrade_status(void)
+{
+	if( http_upgrade_state == HTTP_IMG_UPGRADE_FAIL )
+		return STREAM_UPGRADE_ERR;
+	else
+		return STREAM_UPGRADE_OK;
+
+}
+
+STREAM_TRANSFER_STATUS http_update_image(char *data, unsigned int len, STREAM_TRANSFER_STATE state)
+{
+	static char* upload_addr = NULL;
+	static char* orig_upload_addr = NULL;
+	char * s = NULL;
+	int ret = -1;
+
+	if( state == TRANSFER_START ) {
+		if( http_upgrade_state == HTTP_IMG_UPGRADE_IDLE ) {
+			/* pre-set load_addr */
+			s = env_get("loadaddr");
+			if (s != NULL)
+				upload_addr = simple_strtoul(s, NULL, 16);
+			else
+				upload_addr = load_addr;
+
+			orig_upload_addr = upload_addr;
+			http_upgrade_state = HTTP_IMG_UPGRADE_INPROGRESS;
+			printf("%s: downloading image to 0x%p\n         ", __FUNCTION__, orig_upload_addr);
+		} else {
+			printf("%s: ERROR: Image Upgrade already in progress! Ignoring Upgrade request!p\n", __FUNCTION__);
+			return STOP_STREAM_DATA;
+		}
+	}
+	
+	if( upload_addr ) {
+		memcpy(upload_addr, data, len);
+		upload_addr += len;
+	}
+
+	if( state == TRANSFER_END )
+	{
+		int img_index = get_img_index_for_upgrade(0);
+		ret = flash_upgrade_img_bundle(orig_upload_addr, img_index, NULL);
+		upload_addr = NULL;
+		orig_upload_addr = NULL;
+
+		if( ret ) {
+			printf("ERROR: HTTP Image upgrade failed!!\n");
+			http_upgrade_state = HTTP_IMG_UPGRADE_FAIL;
+		} else {
+			printf("INFO: HTTP Image upgrade successfull!!\n");		
+			//FIXME: Check boot once flag before committing?
+			commit_image( img_index );
+			http_upgrade_state = HTTP_IMG_UPGRADE_OK;
+		}
+	}
+
+	return NEXT_STREAM_DATA;
+}
+
+void http_poll(void)
+{
+	int ret;
+	struct udevice *current;
+	static int uip_initalized = 0;
+
+	current = eth_get_dev();
+
+	if(!current || !eth_is_active(current))
+	{	
+		net_init();
+		if (eth_is_on_demand_init()) 
+		{
+			eth_halt();
+			eth_set_current();
+			ret = eth_init();
+			if (ret < 0) {
+				eth_halt();
+				unregister_cli_job_cb(http_poll);
+				printf("HTTPD: no network interface found, failed to init network\n");
+				return;
+			}
+		} 
+		else 
+		{
+			eth_init_state_only();
+		}
+	}
+
+	if(!uip_initalized)
+	{
+		httpd_start();
+		handle_data_stream = http_update_image;
+		get_stream_upgrade_status = http_get_upgrade_status;
+		ip_tap = http_rcv;
+		uip_initalized = 1;
+	}
+
+	eth_rx();
+	httpd_poll_post_process();
+}
+
+
diff --git a/board/broadcom/bcmbca/httpd/bcmbca_net.h b/board/broadcom/bcmbca/httpd/bcmbca_net.h
new file mode 100644
index 0000000000..4788ac9558
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/bcmbca_net.h
@@ -0,0 +1,7 @@
+#ifndef __BCMBCA_NET_H__
+#define __BCMBCA_NET_H__
+
+void http_poll(void);
+int httpd_check_net_env(void);
+
+#endif /* __BCMBCA_NET_H__ */
diff --git a/board/broadcom/bcmbca/httpd/fs.h b/board/broadcom/bcmbca/httpd/fs.h
new file mode 100644
index 0000000000..2d9693bff0
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/fs.h
@@ -0,0 +1,80 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP server read-only file system header file.
+ * \author Adam Dunkels <adam@dunkels.com>
+ */
+ 
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ * $Id: fs.h,v 1.6.2.3 2003/10/07 13:22:27 adam Exp $
+ */
+#ifndef __FS_H__
+#define __FS_H__
+
+#include "uip.h"
+
+/**
+ * An open file in the read-only file system.
+ */
+struct fs_file {
+  char *data;  /**< The actual file data. */
+  int len;     /**< The length of the file data. */
+};
+
+/**
+ * Open a file in the read-only file system.
+ *
+ * \param name The name of the file.
+ *
+ * \param file The file pointer, which must be allocated by caller and
+ * will be filled in by the function.
+ */
+int fs_open(const char *name, struct fs_file *file);
+
+#ifdef FS_STATISTICS
+#if FS_STATISTICS == 1  
+u16_t fs_count(char *name);
+#endif /* FS_STATISTICS */
+#endif /* FS_STATISTICS */
+
+/**
+ * Initialize the read-only file system.
+ */
+void fs_init(void);
+
+#endif /* __FS_H__ */
diff --git a/board/broadcom/bcmbca/httpd/html/404.html b/board/broadcom/bcmbca/httpd/html/404.html
new file mode 100644
index 0000000000..3b79efd535
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/html/404.html
@@ -0,0 +1,14 @@
+<!DOCTYPE HTML>
+<html>
+	<head>
+		<meta charset="utf-8">
+		<title>Page not found</title>
+		<link rel="icon" href="data:,">
+	</head>
+	<body>
+		<div id="m">
+			<h1 class="red">Page not found</h1>
+			<p>The page you were looking for doesn't exist!</p>
+		</div>
+	</body>
+</html>
diff --git a/board/broadcom/bcmbca/httpd/html/fail.html b/board/broadcom/bcmbca/httpd/html/fail.html
new file mode 100644
index 0000000000..0cd83559d3
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/html/fail.html
@@ -0,0 +1,26 @@
+<!DOCTYPE HTML>
+<html>
+	<head>
+		<meta charset="utf-8">
+		<title>Update failed</title>
+		<link rel="icon" href="data:,">
+	</head>
+	<body>
+		<div id="m">
+			<h1 class="red">Update failed</h1>
+			<p>Please click on refresh button of your browser to go back to the upload page.<br>Check U-Boot console for any errors.</p>
+		</div>
+		<script>
+			if ( window.history.replaceState ) {
+				window.history.replaceState( null, null, window.location.href );
+			}
+			function checkEvt(){
+				var evTypep=window.performance.getEntriesByType("navigation")[0].type;
+				if (evTypep=='reload'){
+					window.location.replace("index.html");
+				}
+			}
+			checkEvt();
+		</script>
+	</body>
+</html>
diff --git a/board/broadcom/bcmbca/httpd/html/flashing.html b/board/broadcom/bcmbca/httpd/html/flashing.html
new file mode 100644
index 0000000000..4b86066328
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/html/flashing.html
@@ -0,0 +1,18 @@
+<!DOCTYPE HTML>
+<html>
+	<head>
+		<meta charset="utf-8">
+		<title>Update in progress</title>
+		<link rel="icon" href="data:,">
+		<style>
+			h1,p,body{margin:0;padding:0}html,body{font:13px/20px Tahoma,sans-serif;background:#135B72;color:#FFF;text-align:center;height:100%}#m{padding:30px 0}#m>*{padding:20px}#f{font-size:11px;position:absolute;bottom:0;width:100%;padding:15px 0}a{color:#FEDD12;text-decoration:none}h1{font:bold 40px/40px Arial}#l{height:30px;width:30px;margin:30px auto;-webkit-animation:r 1s infinite linear;-moz-animation:r 1s infinite linear;-o-animation:r 1s infinite linear;animation:r 1s infinite linear;border-left:5px solid #FEDD12;border-right:5px solid #FEDD12;border-bottom:5px solid #135B72;border-top:5px solid #135B72;border-radius:100%}@-webkit-keyframes r{from{-webkit-transform:rotate(0deg)}to{-webkit-transform:rotate(359deg)}}@-moz-keyframes r{from{-moz-transform:rotate(0deg)}to{-moz-transform:rotate(359deg)}}@-o-keyframes r{from{-o-transform:rotate(0deg)}to{-o-transform:rotate(359deg)}}@keyframes r{from{transform:rotate(0deg)}to{transform:rotate(359deg)}}
+		</style>
+	</head>
+	<body>
+		<div id="m">
+			<h1>Update in progress</h1>
+			<p>Your file was successfully uploaded! Update is in progress and you should wait for automatic reset of the device.<br>Update time depends on image size and may take up to a few minutes. You can close this page.</p>
+			<div id="l"></div>
+		</div>
+	</body>
+</html>
diff --git a/board/broadcom/bcmbca/httpd/html/index.html b/board/broadcom/bcmbca/httpd/html/index.html
new file mode 100644
index 0000000000..4869107c8c
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/html/index.html
@@ -0,0 +1,15 @@
+<!DOCTYPE HTML>
+<html>
+	<head>
+		<meta charset="utf-8">
+		<title>Software update</title>
+		<link rel="icon" href="data:,">
+	</head>
+	<body>
+		<div id="m">
+			<h1>Software update</h1>
+			<p>You are going to upload new software to the device.<br>Choose a proper file from your local hard drive and click <strong>"Update software"</strong> button.<br>Please, do not power off the device during update, if everything goes well, the device will restart.</p>
+			<form method="post" enctype="multipart/form-data"><input type="file" name="firmware"><input type="submit" value="Update software"></form>
+		</div>
+	</body>
+</html>
diff --git a/board/broadcom/bcmbca/httpd/httpd.c b/board/broadcom/bcmbca/httpd/httpd.c
new file mode 100644
index 0000000000..bf07e10118
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/httpd.c
@@ -0,0 +1,527 @@
+#include "uip.h"
+#include "httpd.h"
+#include "fs.h"
+
+#include "generated/index.h" 
+#include "generated/flashing.h"
+#include "generated/fail.h"
+#include "generated/404.h"
+
+#define STATE_NONE		0		// empty state (waiting for request...)
+#define STATE_FILE_REQUEST	1		// remote host sent GET request
+#define STATE_UPLOAD_REQUEST	2		// remote host sent POST request
+
+#define HTTPD_USE_STATIC_MEM	1		// Do not use dynamic memory allocation for interim values
+
+// ASCII characters
+#define ISO_G					0x47	// GET
+#define ISO_E					0x45
+#define ISO_T					0x54
+#define ISO_P					0x50	// POST
+#define ISO_O					0x4f
+#define ISO_S					0x53
+#define ISO_T					0x54
+#define ISO_slash				0x2f	// control and other characters
+#define ISO_space				0x20
+#define ISO_nl					0x0a
+#define ISO_cr					0x0d
+#define ISO_tab					0x09
+
+// we use this so that we can do without the ctype library
+#define is_digit(c)				((c) >= '0' && (c) <= '9')
+
+// debug
+//#define DEBUG_UIP
+
+
+// http app state
+struct httpd_state *hs;
+
+static int webfailsafe_post_done = 0;
+static int webfailsafe_upload_failed = 0;
+static int data_start_found = 0;
+
+int	webfailsafe_is_running = 0;
+int	webfailsafe_ready_for_upgrade = 0;
+
+STREAM_TRANSFER_STATUS (*handle_data_stream)(char *data_stream_ptr, unsigned int len, STREAM_TRANSFER_STATE state) = NULL;
+STREAM_UPGRADE_STATUS (*get_stream_upgrade_status)(void) = NULL;
+
+static unsigned char post_packet_counter = 0;
+static unsigned char packets_per_hash = 0;
+
+// 0x0D -> CR 0x0A -> LF
+static char eol[3] = { 0x0d, 0x0a, 0x00 };
+static char eol2[5] = { 0x0d, 0x0a, 0x0d, 0x0a, 0x00 };
+
+#if HTTPD_USE_STATIC_MEM
+#define HTTPD_STATIC_MEM_SZ	200
+static char boundary_value[HTTPD_STATIC_MEM_SZ];
+#else
+static char *boundary_value;
+#endif
+
+// str to int
+static int atoi(const char *s){
+	int i = 0;
+
+	while(is_digit(*s)){
+		i = i * 10 + *(s++) - '0';
+	}
+
+	return(i);
+}
+
+// print downloading progress
+static void httpd_download_progress(void){
+
+	if (packets_per_hash++ == 100)
+	{
+		putc('#');
+		packets_per_hash = 0;
+		post_packet_counter++;
+	}
+
+	if(post_packet_counter == 39){
+		puts("\n         ");
+		post_packet_counter = 0;
+	}
+}
+
+// reset app state
+static void httpd_state_reset(void){
+	hs->state = STATE_NONE;
+	hs->count = 0;
+	hs->dataptr = 0;
+	hs->upload = 0;
+	hs->upload_total = 0;
+
+	data_start_found = 0;
+	post_packet_counter = 0;
+
+#if HTTPD_USE_STATIC_MEM
+	memset(boundary_value, 0, HTTPD_STATIC_MEM_SZ);
+#else
+	if(boundary_value){
+		free(boundary_value);
+	}
+#endif	
+
+}
+
+// find and get first chunk of data
+static int httpd_findandstore_firstchunk(void){
+	char *start = NULL;
+	char *end = NULL;
+	
+#if !HTTPD_USE_STATIC_MEM
+	if(!boundary_value){
+		return(0);
+	}
+#endif	
+
+	// chek if we have data in packet
+	start = (char *)strstr((char *)uip_appdata, (char *)boundary_value);
+
+	if(start){
+		// ok, we have data in this packet!
+		// find upgrade type
+
+		end = (char *)strstr((char *)start, "name=\"firmware\"");
+
+		if(end){
+			printf("Starting update software\n");
+		} else {
+			printf("input name not found!\n");
+			return(0);
+		}
+
+		end = NULL;
+
+		// find start position of the data!
+		end = (char *)strstr((char *)start, eol2);
+
+		if(end){
+			if((end - (char *)uip_appdata) < uip_len){
+				// move pointer over CR LF CR LF
+				end += 4;
+
+				// how much data we expect?
+				// last part (magic value 6): [CR][LF](boundary length)[-][-][CR][LF]
+				hs->upload_total = hs->upload_total - (int)(end - start) - strlen(boundary_value) - 6;
+
+				printf("Upload file size: %d bytes\n", hs->upload_total);
+
+				// We need to check if file which we are going to download
+				// has correct size (for every type of upgrade)
+
+				printf("Loading: ");
+
+				// how much data we are storing now?
+				hs->upload = (unsigned int)(uip_len - (end - (char *)uip_appdata));
+
+				if(handle_data_stream(end, hs->upload, TRANSFER_START) == STOP_STREAM_DATA)
+				{
+					httpd_state_reset();
+					uip_abort();
+					return 0;
+				}
+
+				httpd_download_progress();
+
+				return(1);
+
+			}
+		} else {
+			printf("couldn't find start of data!\n");
+		}
+
+	}
+
+	return(0);
+}
+
+// called for http server app
+void httpd_appcall(void){
+	struct fs_file fsfile;
+	unsigned int i;
+
+	switch(uip_conn->lport){
+		case HTONS(80):
+			// app state
+			hs = (struct httpd_state *)(uip_conn->appstate);
+
+			// closed connection
+			if(uip_closed()){
+				httpd_state_reset();
+				uip_close();
+				return;
+			}
+
+			// aborted connection or time out occured
+			if(uip_aborted() || uip_timedout()){
+				httpd_state_reset();
+				uip_abort();
+				return;
+			}
+
+			// if we are pooled
+			if(uip_poll()){
+				if(hs->count++ >= 100){
+					httpd_state_reset();
+					uip_abort();
+				}
+				return;
+			}
+
+			// new connection
+			if(uip_connected()){
+				httpd_state_reset();
+				return;
+			}
+
+			// new data in STATE_NONE
+			if(uip_newdata() && hs->state == STATE_NONE){
+				// GET or POST request?
+				if(uip_appdata[0] == ISO_G && uip_appdata[1] == ISO_E && uip_appdata[2] == ISO_T && (uip_appdata[3] == ISO_space || uip_appdata[3] == ISO_tab)){
+					hs->state = STATE_FILE_REQUEST;
+				} else if(uip_appdata[0] == ISO_P && uip_appdata[1] == ISO_O && uip_appdata[2] == ISO_S && uip_appdata[3] == ISO_T && (uip_appdata[4] == ISO_space || uip_appdata[4] == ISO_tab)){
+					hs->state = STATE_UPLOAD_REQUEST;
+				}
+
+				// anything else -> abort the connection!
+				if(hs->state == STATE_NONE){
+					httpd_state_reset();
+					uip_abort();
+					return;
+				}
+
+				// get file or firmware upload?
+				if(hs->state == STATE_FILE_REQUEST){
+
+					// we are looking for GET file name
+					for(i = 4; i < 30; i++){
+						if(uip_appdata[i] == ISO_space || uip_appdata[i] == ISO_cr || uip_appdata[i] == ISO_nl || uip_appdata[i] == ISO_tab){
+							uip_appdata[i] = 0;
+							i = 0;
+							break;
+						}
+					}
+
+					if(i != 0){
+						printf("request file name too long!\n");
+						httpd_state_reset();
+						uip_abort();
+						return;
+					}
+
+					printf("Request for: ");
+					printf("%s\n", &uip_appdata[4]);
+
+					// request for /
+					if((uip_appdata[4] == ISO_slash && uip_appdata[5] == 0) || !strcmp(&uip_appdata[4], "/index.html")){
+						fsfile.data = (char*)index_html;
+						fsfile.len = sizeof(index_html);
+					} else { 
+						// check if we have requested file
+						fsfile.data = (char*)__404_html;
+						fsfile.len = sizeof(__404_html);
+					}
+
+					hs->state = STATE_FILE_REQUEST;
+					hs->dataptr = (u8_t *)fsfile.data;
+					hs->upload = fsfile.len;
+
+					// send first (and maybe the last) chunk of data
+					uip_send(hs->dataptr, (hs->upload > uip_mss() ? uip_mss() : hs->upload));
+					return;
+
+				} else if(hs->state == STATE_UPLOAD_REQUEST){
+					char *start = NULL;
+					char *end = NULL;
+
+					// end bufor data with NULL
+					uip_appdata[uip_len] = '\0';
+
+					/*
+					 * We got first packet with POST request
+					 *
+					 * Some browsers don't include first chunk of data in the first
+					 * POST request packet (like Google Chrome, IE and Safari)!
+					 * So we must now find two values:
+					 * - Content-Length
+					 * - boundary
+					 * Headers with these values can be in any order!
+					 * If we don't find these values in first packet, connection will be aborted!
+					 *
+					 */
+
+					// Content-Length pos
+					start = (char *)strstr((char*)uip_appdata, "Content-Length:");
+
+					if(start){
+						start += sizeof("Content-Length:");
+
+						// find end of the line with "Content-Length:"
+						end = (char *)strstr(start, eol);
+
+						if(end){
+
+							hs->upload_total = atoi(start);
+#ifdef DEBUG_UIP
+							printf("Expecting %d bytes in body request message\n", hs->upload_total);
+#endif
+
+						} else {
+							printf("couldn't find 'Content-Length'!\n");
+							httpd_state_reset();
+							uip_abort();
+							return;
+						}
+
+					} else {
+						printf("couldn't find 'Content-Length'!\n");
+						httpd_state_reset();
+						uip_abort();
+						return;
+					}
+
+					// we don't support very small files (< 10 KB)
+					if(hs->upload_total < 10240){
+						printf("request for upload < 10 KB data!\n");
+						httpd_state_reset();
+						uip_abort();
+						return;
+					}
+
+					// boundary value
+					start = NULL;
+					end = NULL;
+
+					start = (char *)strstr((char *)uip_appdata, "boundary=");
+
+					if(start){
+						// move pointer over "boundary="
+						start += 9;
+
+						// find end of line with boundary value
+						end = (char *)strstr((char *)start, eol);
+
+						if(end){
+
+#if !HTTPD_USE_STATIC_MEM
+							// malloc space for boundary value + '--' and '\0'
+							boundary_value = (char*)malloc(end - start + 3);
+#endif							
+							if(boundary_value){
+
+								memcpy(&boundary_value[2], start, end - start);
+
+								// add -- at the begin and 0 at the end
+								boundary_value[0] = '-';
+								boundary_value[1] = '-';
+								boundary_value[end - start + 2] = 0;
+
+#ifdef DEBUG_UIP
+								printf("Found boundary value: \"%s\"\n", boundary_value);
+#endif
+
+							} else {
+								printf("couldn't allocate memory for boundary!\n");
+								httpd_state_reset();
+								uip_abort();
+								return;
+							}
+
+						} else {
+							printf("couldn't find boundary!\n");
+							httpd_state_reset();
+							uip_abort();
+							return;
+						}
+					} else {
+						printf("couldn't find boundary!\n");
+						httpd_state_reset();
+						uip_abort();
+						return;
+					}
+
+					/*
+					 * OK, if we are here, it means that we found
+					 * Content-Length and boundary values in headers
+					 *
+					 * We can now try to 'allocate memory' and
+					 * find beginning of the data in first packet
+					 */
+
+					if(httpd_findandstore_firstchunk()){
+						data_start_found = 1;
+					} else {
+						data_start_found = 0;
+					}
+
+					return;
+
+				} /* else if(hs->state == STATE_UPLOAD_REQUEST) */
+
+			} /* uip_newdata() && hs->state == STATE_NONE */
+
+			// if we got ACK from remote host
+			if(uip_acked()){
+				// if we are in STATE_FILE_REQUEST state
+				if(hs->state == STATE_FILE_REQUEST){
+					// data which we send last time was received (we got ACK)
+					// if we send everything last time -> gently close the connection
+					if(hs->upload <= uip_mss()){
+						// post upload completed?
+						if(webfailsafe_post_done){
+							if(!webfailsafe_upload_failed){
+								webfailsafe_ready_for_upgrade = 1;
+							}
+
+							webfailsafe_post_done = 0;
+							webfailsafe_upload_failed = 0;
+						}
+
+						httpd_state_reset();
+						uip_close();
+						return;
+					}
+
+					// otherwise, send another chunk of data
+					// last time we sent uip_conn->len size of data
+					hs->dataptr += uip_conn->len;
+					hs->upload -= uip_conn->len;
+
+					uip_send(hs->dataptr, (hs->upload > uip_mss() ? uip_mss() : hs->upload));
+				}
+
+				return;
+
+			}
+
+			// if we need to retransmit
+			if(uip_rexmit()){
+				// if we are in STATE_FILE_REQUEST state
+				if(hs->state == STATE_FILE_REQUEST){
+					// send again chunk of data without changing pointer and length of data left to send
+					uip_send(hs->dataptr, (hs->upload > uip_mss() ? uip_mss() : hs->upload));
+				}
+
+				return;
+
+			}
+
+			// if we got new data frome remote host
+			if(uip_newdata()){
+				// if we are in STATE_UPLOAD_REQUEST state
+				if(hs->state == STATE_UPLOAD_REQUEST){
+					// end bufor data with NULL
+					uip_appdata[uip_len] = '\0';
+
+					// do we have to find start of data?
+					if(!data_start_found){
+
+						if(!httpd_findandstore_firstchunk()){
+							printf("couldn't find start of data in next packet!\n");
+							httpd_state_reset();
+							uip_abort();
+							return;
+						} else {
+							data_start_found = 1;
+						}
+						return;
+					}
+
+					hs->upload += (unsigned int)uip_len;
+
+					if(!webfailsafe_upload_failed){
+						if(handle_data_stream((char*)uip_appdata, uip_len, (hs->upload >= hs->upload_total) ? TRANSFER_END : TRANSFER_CONTINUE) == STOP_STREAM_DATA)
+						{
+							httpd_state_reset();
+							uip_abort();
+							return;
+						}
+					}
+
+					httpd_download_progress();
+
+					// if we have collected all data
+					if(hs->upload >= hs->upload_total){
+						// end of post upload
+						webfailsafe_post_done = 1;
+
+						// Check if upgrade failed
+						if( get_stream_upgrade_status() == STREAM_UPGRADE_ERR )
+							webfailsafe_upload_failed = 1;
+						else
+							webfailsafe_upload_failed = 0;
+
+						// which website will be returned
+						if(!webfailsafe_upload_failed){
+							fsfile.data = (char*)flashing_html;
+							fsfile.len = sizeof(flashing_html);
+						} else {
+							fsfile.data = (char*)fail_html;
+							fsfile.len = sizeof(fail_html);
+						}
+						httpd_state_reset();
+						hs->state = STATE_FILE_REQUEST;
+						hs->dataptr = (u8_t *)fsfile.data;
+						hs->upload = fsfile.len;
+
+						uip_send(hs->dataptr, (hs->upload > uip_mss() ? uip_mss() : hs->upload));
+					}
+				}
+				return;
+			}
+			break;
+
+		default:
+			// we shouldn't get here... we are listening only on port 80
+			uip_abort();
+			break;
+	}
+}
+
+
diff --git a/board/broadcom/bcmbca/httpd/httpd.h b/board/broadcom/bcmbca/httpd/httpd.h
new file mode 100644
index 0000000000..6063f7f127
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/httpd.h
@@ -0,0 +1,98 @@
+/**
+ * \addtogroup httpd
+ * @{
+ */
+
+/**
+ * \file
+ * HTTP server header file.
+ * \author Adam Dunkels <adam@dunkels.com>
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: httpd.h,v 1.4.2.3 2003/10/06 22:56:44 adam Exp $
+ *
+ */
+
+#ifndef __HTTPD_H__
+#define __HTTPD_H__
+
+typedef enum
+{
+	TRANSFER_START,
+	TRANSFER_CONTINUE,
+	TRANSFER_END
+} STREAM_TRANSFER_STATE;
+
+typedef enum
+{
+	NEXT_STREAM_DATA,
+	STOP_STREAM_DATA
+} STREAM_TRANSFER_STATUS;
+
+typedef enum
+{
+	STREAM_UPGRADE_OK,
+	STREAM_UPGRADE_ERR
+} STREAM_UPGRADE_STATUS;
+
+void httpd_appcall(void);
+
+/* UIP_APPCALL: the name of the application function. This function
+ must return void and take no arguments (i.e., C type "void
+ appfunc(void)"). */
+#ifndef UIP_APPCALL
+#define UIP_APPCALL		httpd_appcall
+#endif
+
+struct httpd_state {
+	unsigned long state;
+	unsigned long count;
+	u8_t *dataptr;
+	unsigned long upload;
+	unsigned long upload_total;
+};
+
+/* UIP_APPSTATE_SIZE: The size of the application-specific state
+ stored in the uip_conn structure. */
+#ifndef UIP_APPSTATE_SIZE
+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state))
+#endif
+
+//#define FS_STATISTICS 1
+
+extern struct httpd_state *hs;
+
+extern STREAM_TRANSFER_STATUS (*handle_data_stream)(char *data_stream_ptr, unsigned int len, STREAM_TRANSFER_STATE state);
+extern STREAM_UPGRADE_STATUS (*get_stream_upgrade_status)(void);
+
+#endif /* __HTTPD_H__ */
diff --git a/board/broadcom/bcmbca/httpd/uip.c b/board/broadcom/bcmbca/httpd/uip.c
new file mode 100644
index 0000000000..5eae70dbae
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/uip.c
@@ -0,0 +1,1508 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \file
+ * The uIP TCP/IP stack code.
+ * \author Adam Dunkels <adam@dunkels.com>
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.c,v 1.62.2.10 2003/10/07 13:23:01 adam Exp $
+ *
+ */
+
+/*
+This is a small implementation of the IP and TCP protocols (as well as
+some basic ICMP stuff). The implementation couples the IP, TCP and the
+application layers very tightly. To keep the size of the compiled code
+down, this code also features heavy usage of the goto statement.
+
+The principle is that we have a small buffer, called the uip_buf, in
+which the device driver puts an incoming packet. The TCP/IP stack
+parses the headers in the packet, and calls upon the application. If
+the remote host has sent data to the application, this data is present
+in the uip_buf and the application read the data from there. It is up
+to the application to put this data into a byte stream if needed. The
+application will not be fed with data that is out of sequence.
+
+If the application whishes to send data to the peer, it should put its
+data into the uip_buf, 40 bytes from the start of the buffer. The
+TCP/IP stack will calculate the checksums, and fill in the necessary
+header fields and finally send the packet back to the peer.
+*/
+
+#include "uip.h"
+#include "uipopt.h"
+#include "uip_arch.h"
+#include "uip_arp.h"
+/*-----------------------------------------------------------------------------------*/
+/* Variable definitions. */
+
+
+/* The IP address of this host. If it is defined to be fixed (by setting UIP_FIXEDADDR to 1 in uipopt.h), the address is set here. Otherwise, the address */
+#if UIP_FIXEDADDR > 0
+const unsigned short int uip_hostaddr[2] =
+  {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1),
+   HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)};
+const unsigned short int uip_arp_draddr[2] =
+  {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1),
+   HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)};
+const unsigned short int uip_arp_netmask[2] =
+  {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1),
+   HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)};
+#else
+unsigned short int uip_hostaddr[2];       
+unsigned short int uip_arp_draddr[2], uip_arp_netmask[2];
+#endif /* UIP_FIXEDADDR */
+
+struct uip_eth_addr uip_ethaddr = {{UIP_ETHADDR0,
+				    UIP_ETHADDR1,
+				    UIP_ETHADDR2,
+				    UIP_ETHADDR3,
+				    UIP_ETHADDR4,
+				    UIP_ETHADDR5}};
+
+
+u8_t uip_buf[UIP_BUFSIZE+4];   /* The packet buffer that contains
+				incoming packets. */
+volatile u8_t *uip_appdata;  /* The uip_appdata pointer points to
+				application data. */
+volatile u8_t *uip_sappdata;  /* The uip_appdata pointer points to the
+				 application data which is to be sent. */
+#if UIP_URGDATA > 0
+volatile u8_t *uip_urgdata;  /* The uip_urgdata pointer points to
+				urgent data (out-of-band data), if
+				present. */
+volatile u8_t uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+volatile unsigned short int uip_len, uip_slen;
+                             /* The uip_len is either 8 or 16 bits,
+				depending on the maximum packet
+				size. */
+
+volatile u8_t uip_flags;     /* The uip_flags variable is used for
+				communication between the TCP/IP stack
+				and the application program. */
+struct uip_conn *uip_conn;   /* uip_conn always points to the current
+				connection. */
+
+struct uip_conn uip_conns[UIP_CONNS];
+                             /* The uip_conns array holds all TCP
+				connections. */
+unsigned short int uip_listenports[UIP_LISTENPORTS];
+                             /* The uip_listenports list all currently
+				listning ports. */
+#if UIP_UDP
+struct uip_udp_conn *uip_udp_conn;
+struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+
+static unsigned short int ipid;           /* Ths ipid variable is an increasing
+				number that is used for the IP ID
+				field. */
+
+static u8_t iss[4];          /* The iss variable is used for the TCP
+				initial sequence number. */
+
+#if UIP_ACTIVE_OPEN
+static unsigned short int lastport;       /* Keeps track of the last port used for
+				a new connection. */
+#endif /* UIP_ACTIVE_OPEN */
+
+/* Temporary variables. */
+volatile u8_t uip_acc32[4];
+static u8_t c, opt;
+static unsigned short int tmp16;
+
+/* Structures and definitions. */
+#define TCP_FIN 0x01
+#define TCP_SYN 0x02
+#define TCP_RST 0x04
+#define TCP_PSH 0x08
+#define TCP_ACK 0x10
+#define TCP_URG 0x20
+#define TCP_CTL 0x3f
+
+#define ICMP_ECHO_REPLY 0
+#define ICMP_ECHO       8     
+
+/* Macros. */
+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])
+#define FBUF ((uip_tcpip_hdr *)&uip_reassbuf[0])
+#define ICMPBUF ((uip_icmpip_hdr *)&uip_buf[UIP_LLH_LEN])
+#define UDPBUF ((uip_udpip_hdr *)&uip_buf[UIP_LLH_LEN])
+
+#if UIP_STATISTICS == 1
+struct uip_stats uip_stat;
+#define UIP_STAT(s) s
+#else
+#define UIP_STAT(s)
+#endif /* UIP_STATISTICS == 1 */
+
+#if UIP_LOGGING == 1
+extern void puts(const char *s);
+#define UIP_LOG(m) puts(m)
+#else
+#define UIP_LOG(m)
+#endif /* UIP_LOGGING == 1 */
+
+/*-----------------------------------------------------------------------------------*/
+void
+uip_init(void)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    uip_listenports[c] = 0;
+  }
+  for(c = 0; c < UIP_CONNS; ++c) {
+    uip_conns[c].tcpstateflags = CLOSED;
+  }
+#if UIP_ACTIVE_OPEN
+  lastport = 1024;
+#endif /* UIP_ACTIVE_OPEN */
+
+#if UIP_UDP
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    uip_udp_conns[c].lport = 0;
+  }
+#endif /* UIP_UDP */
+  
+
+  /* IPv4 initialization. */
+#if UIP_FIXEDADDR == 0
+  uip_hostaddr[0] = uip_hostaddr[1] = 0;
+#endif /* UIP_FIXEDADDR */
+
+}
+/*-----------------------------------------------------------------------------------*/
+#if UIP_ACTIVE_OPEN
+struct uip_conn *
+uip_connect(unsigned short int *ripaddr, unsigned short int rport)
+{
+  register struct uip_conn *conn, *cconn;
+  
+  /* Find an unused local port. */
+ again:
+  ++lastport;
+
+  if(lastport >= 32000) {
+    lastport = 4096;
+  }
+
+  /* Check if this port is already in use, and if so try to find
+     another one. */
+  for(c = 0; c < UIP_CONNS; ++c) {
+    conn = &uip_conns[c];
+    if(conn->tcpstateflags != CLOSED &&
+       conn->lport == htons(lastport)) {
+      goto again;
+    }
+  }
+
+
+  conn = 0;
+  for(c = 0; c < UIP_CONNS; ++c) {
+    cconn = &uip_conns[c]; 
+    if(cconn->tcpstateflags == CLOSED) {
+      conn = cconn;
+      break;
+    }
+    if(cconn->tcpstateflags == TIME_WAIT) {
+      if(conn == 0 ||
+	 cconn->timer > uip_conn->timer) {
+	conn = cconn;
+      }
+    }
+  }
+
+  if(conn == 0) {
+    return 0;
+  }
+  
+  conn->tcpstateflags = SYN_SENT;
+
+  conn->snd_nxt[0] = iss[0];
+  conn->snd_nxt[1] = iss[1];
+  conn->snd_nxt[2] = iss[2];
+  conn->snd_nxt[3] = iss[3];
+
+  conn->initialmss = conn->mss = UIP_TCP_MSS;
+  
+  conn->len = 1;   /* TCP length of the SYN is one. */
+  conn->nrtx = 0;
+  conn->timer = 1; /* Send the SYN next time around. */
+  conn->rto = UIP_RTO;
+  conn->sa = 0;
+  conn->sv = 16;
+  conn->lport = htons(lastport);
+  conn->rport = rport;
+  conn->ripaddr[0] = ripaddr[0];
+  conn->ripaddr[1] = ripaddr[1];
+  
+  return conn;
+}
+#endif /* UIP_ACTIVE_OPEN */
+/*-----------------------------------------------------------------------------------*/
+#if UIP_UDP
+struct uip_udp_conn *
+uip_udp_new(unsigned short int *ripaddr, unsigned short int rport)
+{
+  register struct uip_udp_conn *conn;
+  
+  /* Find an unused local port. */
+ again:
+  ++lastport;
+
+  if(lastport >= 32000) {
+    lastport = 4096;
+  }
+  
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    if(uip_udp_conns[c].lport == lastport) {
+      goto again;
+    }
+  }
+
+
+  conn = 0;
+  for(c = 0; c < UIP_UDP_CONNS; ++c) {
+    if(uip_udp_conns[c].lport == 0) {
+      conn = &uip_udp_conns[c]; 
+      break;
+    }
+  }
+
+  if(conn == 0) {
+    return 0;
+  }
+  
+  conn->lport = HTONS(lastport);
+  conn->rport = HTONS(rport);
+  conn->ripaddr[0] = ripaddr[0];
+  conn->ripaddr[1] = ripaddr[1];
+  
+  return conn;
+}
+#endif /* UIP_UDP */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_unlisten(unsigned short int port)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(uip_listenports[c] == port) {
+      uip_listenports[c] = 0;
+      return;
+    }
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+void
+uip_listen(unsigned short int port)
+{
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(uip_listenports[c] == 0) {
+      uip_listenports[c] = port;
+      return;
+    }
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/* XXX: IP fragment reassembly: not well-tested. */
+
+#if UIP_REASSEMBLY
+#define UIP_REASS_BUFSIZE (UIP_BUFSIZE - UIP_LLH_LEN)
+static u8_t uip_reassbuf[UIP_REASS_BUFSIZE];
+static u8_t uip_reassbitmap[UIP_REASS_BUFSIZE / (8 * 8)];
+static const u8_t bitmap_bits[8] = {0xff, 0x7f, 0x3f, 0x1f,
+				    0x0f, 0x07, 0x03, 0x01};
+static unsigned short int uip_reasslen;
+static u8_t uip_reassflags;
+#define UIP_REASS_FLAG_LASTFRAG 0x01
+static u8_t uip_reasstmr;
+
+#define IP_HLEN 20
+#define IP_MF   0x20
+
+static u8_t
+uip_reass(void)
+{
+  unsigned short int offset, len;
+  unsigned short int i;
+
+  /* If ip_reasstmr is zero, no packet is present in the buffer, so we
+     write the IP header of the fragment into the reassembly
+     buffer. The timer is updated with the maximum age. */
+  if(uip_reasstmr == 0) {
+    memcpy(uip_reassbuf, &BUF->vhl, IP_HLEN);
+    uip_reasstmr = UIP_REASS_MAXAGE;
+    uip_reassflags = 0;
+    /* Clear the bitmap. */
+    memset(uip_reassbitmap, sizeof(uip_reassbitmap), 0);
+  }
+
+  /* Check if the incoming fragment matches the one currently present
+     in the reasembly buffer. If so, we proceed with copying the
+     fragment into the buffer. */
+  if(BUF->srcipaddr[0] == FBUF->srcipaddr[0] &&
+     BUF->srcipaddr[1] == FBUF->srcipaddr[1] &&
+     BUF->destipaddr[0] == FBUF->destipaddr[0] &&
+     BUF->destipaddr[1] == FBUF->destipaddr[1] &&
+     BUF->ipid[0] == FBUF->ipid[0] &&
+     BUF->ipid[1] == FBUF->ipid[1]) {
+
+    len = (BUF->len[0] << 8) + BUF->len[1] - (BUF->vhl & 0x0f) * 4;
+    offset = (((BUF->ipoffset[0] & 0x3f) << 8) + BUF->ipoffset[1]) * 8;
+
+    /* If the offset or the offset + fragment length overflows the
+       reassembly buffer, we discard the entire packet. */
+    if(offset > UIP_REASS_BUFSIZE ||
+       offset + len > UIP_REASS_BUFSIZE) {
+      uip_reasstmr = 0;
+      goto nullreturn;
+    }
+
+    /* Copy the fragment into the reassembly buffer, at the right
+       offset. */
+    memcpy(&uip_reassbuf[IP_HLEN + offset],
+	   (char *)BUF + (int)((BUF->vhl & 0x0f) * 4),
+	   len);
+      
+    /* Update the bitmap. */
+    if(offset / (8 * 8) == (offset + len) / (8 * 8)) {
+      /* If the two endpoints are in the same byte, we only update
+	 that byte. */
+	     
+      uip_reassbitmap[offset / (8 * 8)] |=
+	     bitmap_bits[(offset / 8 ) & 7] &
+	     ~bitmap_bits[((offset + len) / 8 ) & 7];
+    } else {
+      /* If the two endpoints are in different bytes, we update the
+	 bytes in the endpoints and fill the stuff inbetween with
+	 0xff. */
+      uip_reassbitmap[offset / (8 * 8)] |=
+	bitmap_bits[(offset / 8 ) & 7];
+      for(i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) {
+	uip_reassbitmap[i] = 0xff;
+      }      
+      uip_reassbitmap[(offset + len) / (8 * 8)] |=
+	~bitmap_bits[((offset + len) / 8 ) & 7];
+    }
+    
+    /* If this fragment has the More Fragments flag set to zero, we
+       know that this is the last fragment, so we can calculate the
+       size of the entire packet. We also set the
+       IP_REASS_FLAG_LASTFRAG flag to indicate that we have received
+       the final fragment. */
+
+    if((BUF->ipoffset[0] & IP_MF) == 0) {
+      uip_reassflags |= UIP_REASS_FLAG_LASTFRAG;
+      uip_reasslen = offset + len;
+    }
+    
+    /* Finally, we check if we have a full packet in the buffer. We do
+       this by checking if we have the last fragment and if all bits
+       in the bitmap are set. */
+    if(uip_reassflags & UIP_REASS_FLAG_LASTFRAG) {
+      /* Check all bytes up to and including all but the last byte in
+	 the bitmap. */
+      for(i = 0; i < uip_reasslen / (8 * 8) - 1; ++i) {
+	if(uip_reassbitmap[i] != 0xff) {
+	  goto nullreturn;
+	}
+      }
+      /* Check the last byte in the bitmap. It should contain just the
+	 right amount of bits. */
+      if(uip_reassbitmap[uip_reasslen / (8 * 8)] !=
+	 (u8_t)~bitmap_bits[uip_reasslen / 8 & 7]) {
+	goto nullreturn;
+      }
+
+      /* If we have come this far, we have a full packet in the
+	 buffer, so we allocate a pbuf and copy the packet into it. We
+	 also reset the timer. */
+      uip_reasstmr = 0;
+      memcpy(BUF, FBUF, uip_reasslen);
+
+      /* Pretend to be a "normal" (i.e., not fragmented) IP packet
+	 from now on. */
+      BUF->ipoffset[0] = BUF->ipoffset[1] = 0;
+      BUF->len[0] = uip_reasslen >> 8;
+      BUF->len[1] = uip_reasslen & 0xff;
+      BUF->ipchksum = 0;
+      BUF->ipchksum = ~(uip_ipchksum());
+
+      return uip_reasslen;
+    }
+  }
+
+ nullreturn:
+  return 0;
+}
+#endif /* UIP_REASSEMBL */
+/*-----------------------------------------------------------------------------------*/
+static void
+uip_add_rcv_nxt(unsigned short int n)
+{
+  uip_add32(uip_conn->rcv_nxt, n);
+  uip_conn->rcv_nxt[0] = uip_acc32[0];
+  uip_conn->rcv_nxt[1] = uip_acc32[1];
+  uip_conn->rcv_nxt[2] = uip_acc32[2];
+  uip_conn->rcv_nxt[3] = uip_acc32[3];
+}
+/*-----------------------------------------------------------------------------------*/
+void
+uip_process(u8_t flag)
+{
+  register struct uip_conn *uip_connr = uip_conn;
+  
+  uip_appdata = &uip_buf[40 + UIP_LLH_LEN];
+
+  /* Check if we were invoked because of the perodic timer fireing. */
+  if(flag == UIP_TIMER) {
+#if UIP_REASSEMBLY
+    if(uip_reasstmr != 0) {
+      --uip_reasstmr;
+    }
+#endif /* UIP_REASSEMBLY */
+    /* Increase the initial sequence number. */
+    if(++iss[3] == 0) {
+      if(++iss[2] == 0) {
+	if(++iss[1] == 0) {
+	  ++iss[0];
+	}
+      }
+    }    
+    uip_len = 0;
+    if(uip_connr->tcpstateflags == TIME_WAIT ||
+       uip_connr->tcpstateflags == FIN_WAIT_2) {
+      ++(uip_connr->timer);
+      if(uip_connr->timer == UIP_TIME_WAIT_TIMEOUT) {
+	uip_connr->tcpstateflags = CLOSED;
+      }
+    } else if(uip_connr->tcpstateflags != CLOSED) {
+      /* If the connection has outstanding data, we increase the
+	 connection's timer and see if it has reached the RTO value
+	 in which case we retransmit. */
+      if(uip_outstanding(uip_connr)) {
+	if(uip_connr->timer-- == 0) {
+	  if(uip_connr->nrtx == UIP_MAXRTX ||
+	     ((uip_connr->tcpstateflags == SYN_SENT ||
+	       uip_connr->tcpstateflags == SYN_RCVD) &&
+	      uip_connr->nrtx == UIP_MAXSYNRTX)) {
+	    uip_connr->tcpstateflags = CLOSED;
+
+	    /* We call UIP_APPCALL() with uip_flags set to
+	       UIP_TIMEDOUT to inform the application that the
+	       connection has timed out. */
+	    uip_flags = UIP_TIMEDOUT;
+	    UIP_APPCALL();
+
+	    /* We also send a reset packet to the remote host. */
+	    BUF->flags = TCP_RST | TCP_ACK;
+	    goto tcp_send_nodata;
+	  }
+
+	  /* Exponential backoff. */
+	  uip_connr->timer = UIP_RTO << (uip_connr->nrtx > 4?
+					 4:
+					 uip_connr->nrtx);
+	  ++(uip_connr->nrtx);
+	  
+	  /* Ok, so we need to retransmit. We do this differently
+	     depending on which state we are in. In ESTABLISHED, we
+	     call upon the application so that it may prepare the
+	     data for the retransmit. In SYN_RCVD, we resend the
+	     SYNACK that we sent earlier and in LAST_ACK we have to
+	     retransmit our FINACK. */
+	  UIP_STAT(++uip_stat.tcp.rexmit);
+	  switch(uip_connr->tcpstateflags & TS_MASK) {
+	  case SYN_RCVD:
+	    /* In the SYN_RCVD state, we should retransmit our
+               SYNACK. */
+	    goto tcp_send_synack;
+	    
+#if UIP_ACTIVE_OPEN
+	  case SYN_SENT:
+	    /* In the SYN_SENT state, we retransmit out SYN. */
+	    BUF->flags = 0;
+	    goto tcp_send_syn;
+#endif /* UIP_ACTIVE_OPEN */
+	    
+	  case ESTABLISHED:
+	    /* In the ESTABLISHED state, we call upon the application
+               to do the actual retransmit after which we jump into
+               the code for sending out the packet (the apprexmit
+               label). */
+	    uip_len = 0;
+	    uip_slen = 0;
+	    uip_flags = UIP_REXMIT;
+	    UIP_APPCALL();
+	    goto apprexmit;
+	    
+	  case FIN_WAIT_1:
+	  case CLOSING:
+	  case LAST_ACK:
+	    /* In all these states we should retransmit a FINACK. */
+	    goto tcp_send_finack;
+	    
+	  }
+	}
+      } else if((uip_connr->tcpstateflags & TS_MASK) == ESTABLISHED) {
+	/* If there was no need for a retransmission, we poll the
+           application for new data. */
+	uip_len = 0;
+	uip_slen = 0;
+	uip_flags = UIP_POLL;
+	UIP_APPCALL();
+	goto appsend;
+      }
+    }
+    goto drop;
+  }
+#if UIP_UDP 
+  if(flag == UIP_UDP_TIMER) {
+    if(uip_udp_conn->lport != 0) {
+      uip_appdata = &uip_buf[UIP_LLH_LEN + 28];
+      uip_len = uip_slen = 0;
+      uip_flags = UIP_POLL;
+      UIP_UDP_APPCALL();
+      goto udp_send;
+    } else {
+      goto drop;
+    }
+  }
+#endif
+
+  /* This is where the input processing starts. */
+  UIP_STAT(++uip_stat.ip.recv);
+
+
+  /* Start of IPv4 input header processing code. */
+  
+  /* Check validity of the IP header. */  
+  if(BUF->vhl != 0x45)  { /* IP version and header length. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.vhlerr);
+    UIP_LOG("ip: invalid version or header length.");
+    goto drop;
+  }
+  
+  /* Check the size of the packet. If the size reported to us in
+     uip_len doesn't match the size reported in the IP header, there
+     has been a transmission error and we drop the packet. */
+  
+  if(BUF->len[0] != (uip_len >> 8)) { /* IP length, high byte. */
+    uip_len = (uip_len & 0xff) | (BUF->len[0] << 8);
+  }
+  if(BUF->len[1] != (uip_len & 0xff)) { /* IP length, low byte. */
+    uip_len = (uip_len & 0xff00) | BUF->len[1];
+  }
+
+  /* Check the fragment flag. */
+  if((BUF->ipoffset[0] & 0x3f) != 0 ||
+     BUF->ipoffset[1] != 0) { 
+#if UIP_REASSEMBLY
+    uip_len = uip_reass();
+    if(uip_len == 0) {
+      goto drop;
+    }
+#else
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.fragerr);
+    UIP_LOG("ip: fragment dropped.");    
+    goto drop;
+#endif /* UIP_REASSEMBLY */
+  }
+
+  /* If we are configured to use ping IP address configuration and
+     hasn't been assigned an IP address yet, we accept all ICMP
+     packets. */
+#if UIP_PINGADDRCONF
+  if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) {
+    if(BUF->proto == UIP_PROTO_ICMP) {
+      UIP_LOG("ip: possible ping config packet received.");
+      goto icmp_input;
+    } else {
+      UIP_LOG("ip: packet dropped since no address assigned.");
+      goto drop;
+    }
+  }
+#endif /* UIP_PINGADDRCONF */
+  
+  /* Check if the packet is destined for our IP address. */  
+  if(BUF->destipaddr[0] != uip_hostaddr[0]) {
+    UIP_STAT(++uip_stat.ip.drop);
+    //UIP_LOG("ip: packet not for us."); 
+    goto drop;
+  }
+  if(BUF->destipaddr[1] != uip_hostaddr[1]) {
+    UIP_STAT(++uip_stat.ip.drop);
+    //UIP_LOG("ip: packet not for us.");        
+    goto drop;
+  }
+
+  if(uip_ipchksum() != 0xffff) { /* Compute and check the IP header
+				    checksum. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.chkerr);
+    UIP_LOG("ip: bad checksum.");    
+    goto drop;
+  }
+
+  if(BUF->proto == UIP_PROTO_TCP)  /* Check for TCP packet. If so, jump
+                                     to the tcp_input label. */
+    goto tcp_input;
+
+#if UIP_UDP
+  if(BUF->proto == UIP_PROTO_UDP)
+    goto udp_input;
+#endif /* UIP_UDP */
+
+  if(BUF->proto != UIP_PROTO_ICMP) { /* We only allow ICMP packets from
+					here. */
+    UIP_STAT(++uip_stat.ip.drop);
+    UIP_STAT(++uip_stat.ip.protoerr);
+    UIP_LOG("ip: neither tcp nor icmp.");        
+    goto drop;
+  }
+  
+ //icmp_input:
+  UIP_STAT(++uip_stat.icmp.recv);
+  
+  /* ICMP echo (i.e., ping) processing. This is simple, we only change
+     the ICMP type from ECHO to ECHO_REPLY and adjust the ICMP
+     checksum before we return the packet. */
+  if(ICMPBUF->type != ICMP_ECHO) {
+    UIP_STAT(++uip_stat.icmp.drop);
+    UIP_STAT(++uip_stat.icmp.typeerr);
+    UIP_LOG("icmp: not icmp echo.");
+    goto drop;
+  }
+
+  /* If we are configured to use ping IP address assignment, we use
+     the destination IP address of this ping packet and assign it to
+     ourself. */
+#if UIP_PINGADDRCONF
+  if((uip_hostaddr[0] | uip_hostaddr[1]) == 0) {
+    uip_hostaddr[0] = BUF->destipaddr[0];
+    uip_hostaddr[1] = BUF->destipaddr[1];
+  }
+#endif /* UIP_PINGADDRCONF */  
+  
+  ICMPBUF->type = ICMP_ECHO_REPLY;
+  
+  if(ICMPBUF->icmpchksum >= HTONS(0xffff - (ICMP_ECHO << 8))) {
+    ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8) + 1;
+  } else {
+    ICMPBUF->icmpchksum += HTONS(ICMP_ECHO << 8);
+  }
+  
+  /* Swap IP addresses. */
+  tmp16 = BUF->destipaddr[0];
+  BUF->destipaddr[0] = BUF->srcipaddr[0];
+  BUF->srcipaddr[0] = tmp16;
+  tmp16 = BUF->destipaddr[1];
+  BUF->destipaddr[1] = BUF->srcipaddr[1];
+  BUF->srcipaddr[1] = tmp16;
+
+  UIP_STAT(++uip_stat.icmp.sent);
+  goto send;
+
+  /* End of IPv4 input header processing code. */
+  
+
+#if UIP_UDP
+  /* UDP input processing. */
+ udp_input:
+  /* UDP processing is really just a hack. We don't do anything to the
+     UDP/IP headers, but let the UDP application do all the hard
+     work. If the application sets uip_slen, it has a packet to
+     send. */
+#if UIP_UDP_CHECKSUMS
+  if(uip_udpchksum() != 0xffff) { 
+    UIP_STAT(++uip_stat.udp.drop);
+    UIP_STAT(++uip_stat.udp.chkerr);
+    UIP_LOG("udp: bad checksum.");    
+    goto drop;
+  }  
+#endif /* UIP_UDP_CHECKSUMS */
+
+  /* Demultiplex this UDP packet between the UDP "connections". */
+  for(uip_udp_conn = &uip_udp_conns[0];
+      uip_udp_conn < &uip_udp_conns[UIP_UDP_CONNS];
+      ++uip_udp_conn) {
+    if(uip_udp_conn->lport != 0 &&
+       UDPBUF->destport == uip_udp_conn->lport &&
+       (uip_udp_conn->rport == 0 ||
+        UDPBUF->srcport == uip_udp_conn->rport) &&
+       BUF->srcipaddr[0] == uip_udp_conn->ripaddr[0] &&
+       BUF->srcipaddr[1] == uip_udp_conn->ripaddr[1]) {
+      goto udp_found; 
+    }
+  }
+  goto drop;
+  
+ udp_found:
+  uip_len = uip_len - 28;
+  uip_appdata = &uip_buf[UIP_LLH_LEN + 28];
+  uip_flags = UIP_NEWDATA;
+  uip_slen = 0;
+  UIP_UDP_APPCALL();
+ udp_send:
+  if(uip_slen == 0) {
+    goto drop;      
+  }
+  uip_len = uip_slen + 28;
+
+  BUF->len[0] = (uip_len >> 8);
+  BUF->len[1] = (uip_len & 0xff);
+  
+  BUF->proto = UIP_PROTO_UDP;
+
+  UDPBUF->udplen = HTONS(uip_slen + 8);
+  UDPBUF->udpchksum = 0;
+#if UIP_UDP_CHECKSUMS 
+  /* Calculate UDP checksum. */
+  UDPBUF->udpchksum = ~(uip_udpchksum());
+  if(UDPBUF->udpchksum == 0) {
+    UDPBUF->udpchksum = 0xffff;
+  }
+#endif /* UIP_UDP_CHECKSUMS */
+
+  BUF->srcport  = uip_udp_conn->lport;
+  BUF->destport = uip_udp_conn->rport;
+
+  BUF->srcipaddr[0] = uip_hostaddr[0];
+  BUF->srcipaddr[1] = uip_hostaddr[1];
+  BUF->destipaddr[0] = uip_udp_conn->ripaddr[0];
+  BUF->destipaddr[1] = uip_udp_conn->ripaddr[1];
+ 
+  uip_appdata = &uip_buf[UIP_LLH_LEN + 40];
+  goto ip_send_nolen;
+#endif /* UIP_UDP */
+  
+  /* TCP input processing. */  
+ tcp_input:
+  UIP_STAT(++uip_stat.tcp.recv);
+
+  /* Start of TCP input header processing code. */
+  if(uip_tcpchksum() != 0xffff) {   /* Compute and check the TCP
+				       checksum. */
+    UIP_STAT(++uip_stat.tcp.drop);
+    UIP_STAT(++uip_stat.tcp.chkerr);
+    UIP_LOG("tcp: bad checksum.");    
+    goto drop;
+  }
+  /* Demultiplex this segment. */
+  /* First check any active connections. */
+  for(uip_connr = &uip_conns[0]; uip_connr < &uip_conns[UIP_CONNS]; ++uip_connr) {
+    if(uip_connr->tcpstateflags != CLOSED &&
+       BUF->destport == uip_connr->lport &&
+       BUF->srcport == uip_connr->rport &&
+       BUF->srcipaddr[0] == uip_connr->ripaddr[0] &&
+       BUF->srcipaddr[1] == uip_connr->ripaddr[1]) {
+      goto found;    
+    }
+  }
+
+  /* If we didn't find and active connection that expected the packet,
+     either this packet is an old duplicate, or this is a SYN packet
+     destined for a connection in LISTEN. If the SYN flag isn't set,
+     it is an old packet and we send a RST. */
+  if((BUF->flags & TCP_CTL) != TCP_SYN)
+    goto reset;
+  
+  tmp16 = BUF->destport;
+  /* Next, check listening connections. */  
+  for(c = 0; c < UIP_LISTENPORTS; ++c) {
+    if(tmp16 == uip_listenports[c])
+      goto found_listen;
+  }
+  
+  /* No matching connection found, so we send a RST packet. */
+  UIP_STAT(++uip_stat.tcp.synrst);
+ reset:
+
+  /* We do not send resets in response to resets. */
+  if(BUF->flags & TCP_RST) 
+    goto drop;
+
+  UIP_STAT(++uip_stat.tcp.rst);
+  
+  BUF->flags = TCP_RST | TCP_ACK;
+  uip_len = 40;
+  BUF->tcpoffset = 5 << 4;
+
+  /* Flip the seqno and ackno fields in the TCP header. */
+  c = BUF->seqno[3];
+  BUF->seqno[3] = BUF->ackno[3];  
+  BUF->ackno[3] = c;
+  
+  c = BUF->seqno[2];
+  BUF->seqno[2] = BUF->ackno[2];  
+  BUF->ackno[2] = c;
+  
+  c = BUF->seqno[1];
+  BUF->seqno[1] = BUF->ackno[1];
+  BUF->ackno[1] = c;
+  
+  c = BUF->seqno[0];
+  BUF->seqno[0] = BUF->ackno[0];  
+  BUF->ackno[0] = c;
+
+  /* We also have to increase the sequence number we are
+     acknowledging. If the least significant byte overflowed, we need
+     to propagate the carry to the other bytes as well. */
+  if(++BUF->ackno[3] == 0) {
+    if(++BUF->ackno[2] == 0) {
+      if(++BUF->ackno[1] == 0) {
+	++BUF->ackno[0];
+      }
+    }
+  }
+ 
+  /* Swap port numbers. */
+  tmp16 = BUF->srcport;
+  BUF->srcport = BUF->destport;
+  BUF->destport = tmp16;
+  
+  /* Swap IP addresses. */
+  tmp16 = BUF->destipaddr[0];
+  BUF->destipaddr[0] = BUF->srcipaddr[0];
+  BUF->srcipaddr[0] = tmp16;
+  tmp16 = BUF->destipaddr[1];
+  BUF->destipaddr[1] = BUF->srcipaddr[1];
+  BUF->srcipaddr[1] = tmp16;
+
+  
+  /* And send out the RST packet! */
+  goto tcp_send_noconn;
+
+  /* This label will be jumped to if we matched the incoming packet
+     with a connection in LISTEN. In that case, we should create a new
+     connection and send a SYNACK in return. */
+ found_listen:
+  /* First we check if there are any connections avaliable. Unused
+     connections are kept in the same table as used connections, but
+     unused ones have the tcpstate set to CLOSED. Also, connections in
+     TIME_WAIT are kept track of and we'll use the oldest one if no
+     CLOSED connections are found. Thanks to Eddie C. Dost for a very
+     nice algorithm for the TIME_WAIT search. */
+  uip_connr = 0;
+  for(c = 0; c < UIP_CONNS; ++c) {
+    if(uip_conns[c].tcpstateflags == CLOSED) {
+      uip_connr = &uip_conns[c];
+      break;
+    }
+    if(uip_conns[c].tcpstateflags == TIME_WAIT) {
+      if(uip_connr == 0 ||
+	 uip_conns[c].timer > uip_connr->timer) {
+	uip_connr = &uip_conns[c];
+      }
+    }
+  }
+
+  if(uip_connr == 0) {
+    /* All connections are used already, we drop packet and hope that
+       the remote end will retransmit the packet at a time when we
+       have more spare connections. */
+    UIP_STAT(++uip_stat.tcp.syndrop);
+    UIP_LOG("tcp: found no unused connections.");
+    goto drop;
+  }
+  uip_conn = uip_connr;
+  
+  /* Fill in the necessary fields for the new connection. */
+  uip_connr->rto = uip_connr->timer = UIP_RTO;
+  uip_connr->sa = 0;
+  uip_connr->sv = 4;  
+  uip_connr->nrtx = 0;
+  uip_connr->lport = BUF->destport;
+  uip_connr->rport = BUF->srcport;
+  uip_connr->ripaddr[0] = BUF->srcipaddr[0];
+  uip_connr->ripaddr[1] = BUF->srcipaddr[1];
+  uip_connr->tcpstateflags = SYN_RCVD;
+
+  uip_connr->snd_nxt[0] = iss[0];
+  uip_connr->snd_nxt[1] = iss[1];
+  uip_connr->snd_nxt[2] = iss[2];
+  uip_connr->snd_nxt[3] = iss[3];
+  uip_connr->len = 1;
+
+  /* rcv_nxt should be the seqno from the incoming packet + 1. */
+  uip_connr->rcv_nxt[3] = BUF->seqno[3];
+  uip_connr->rcv_nxt[2] = BUF->seqno[2];
+  uip_connr->rcv_nxt[1] = BUF->seqno[1];
+  uip_connr->rcv_nxt[0] = BUF->seqno[0];
+  uip_add_rcv_nxt(1);
+
+  /* Parse the TCP MSS option, if present. */
+  if((BUF->tcpoffset & 0xf0) > 0x50) {
+    for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {
+      opt = uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + c];
+      if(opt == 0x00) {
+	/* End of options. */	
+	break;
+      } else if(opt == 0x01) {
+	++c;
+	/* NOP option. */
+      } else if(opt == 0x02 &&
+		uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) {
+	/* An MSS option with the right option length. */	
+	tmp16 = ((unsigned short int)uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
+	  (unsigned short int)uip_buf[40 + UIP_LLH_LEN + 3 + c];
+	uip_connr->initialmss = uip_connr->mss =
+	  tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
+	
+	/* And we are done processing options. */
+	break;
+      } else {
+	/* All other options have a length field, so that we easily
+	   can skip past them. */
+	if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
+	  /* If the length field is zero, the options are malformed
+	     and we don't process them further. */
+	  break;
+	}
+	c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+      }      
+    }
+  }
+  
+  /* Our response will be a SYNACK. */
+#if UIP_ACTIVE_OPEN
+ tcp_send_synack:
+  BUF->flags = TCP_ACK;    
+  
+ tcp_send_syn:
+  BUF->flags |= TCP_SYN;    
+#else /* UIP_ACTIVE_OPEN */
+ tcp_send_synack:
+  BUF->flags = TCP_SYN | TCP_ACK;    
+#endif /* UIP_ACTIVE_OPEN */
+  
+  /* We send out the TCP Maximum Segment Size option with our
+     SYNACK. */
+  BUF->optdata[0] = 2;
+  BUF->optdata[1] = 4;
+  BUF->optdata[2] = (UIP_TCP_MSS) / 256;
+  BUF->optdata[3] = (UIP_TCP_MSS) & 255;
+  uip_len = 44;
+  BUF->tcpoffset = 6 << 4;
+  goto tcp_send;
+
+  /* This label will be jumped to if we found an active connection. */
+ found:
+  uip_conn = uip_connr;
+  uip_flags = 0;
+
+  /* We do a very naive form of TCP reset processing; we just accept
+     any RST and kill our connection. We should in fact check if the
+     sequence number of this reset is wihtin our advertised window
+     before we accept the reset. */
+  if(BUF->flags & TCP_RST) {
+    uip_connr->tcpstateflags = CLOSED;
+    UIP_LOG("tcp: got reset, aborting connection.");
+    uip_flags = UIP_ABORT;
+    UIP_APPCALL();
+    goto drop;
+  }      
+  /* Calculated the length of the data, if the application has sent
+     any data to us. */
+  c = (BUF->tcpoffset >> 4) << 2;
+  /* uip_len will contain the length of the actual TCP data. This is
+     calculated by subtracing the length of the TCP header (in
+     c) and the length of the IP header (20 bytes). */
+  uip_len = uip_len - c - 20;
+
+  /* First, check if the sequence number of the incoming packet is
+     what we're expecting next. If not, we send out an ACK with the
+     correct numbers in. */
+  if(uip_len > 0 &&
+     (BUF->seqno[0] != uip_connr->rcv_nxt[0] ||
+      BUF->seqno[1] != uip_connr->rcv_nxt[1] ||
+      BUF->seqno[2] != uip_connr->rcv_nxt[2] ||
+      BUF->seqno[3] != uip_connr->rcv_nxt[3])) {
+    goto tcp_send_ack;
+  }
+
+  /* Next, check if the incoming segment acknowledges any outstanding
+     data. If so, we update the sequence number, reset the length of
+     the outstanding data, calculate RTT estimations, and reset the
+     retransmission timer. */
+  if((BUF->flags & TCP_ACK) && uip_outstanding(uip_connr)) {
+    uip_add32(uip_connr->snd_nxt, uip_connr->len);
+    if(BUF->ackno[0] == uip_acc32[0] &&
+       BUF->ackno[1] == uip_acc32[1] &&
+       BUF->ackno[2] == uip_acc32[2] &&
+       BUF->ackno[3] == uip_acc32[3]) {
+      /* Update sequence number. */
+      uip_connr->snd_nxt[0] = uip_acc32[0];
+      uip_connr->snd_nxt[1] = uip_acc32[1];
+      uip_connr->snd_nxt[2] = uip_acc32[2];
+      uip_connr->snd_nxt[3] = uip_acc32[3];
+	
+
+      /* Do RTT estimation, unless we have done retransmissions. */
+      if(uip_connr->nrtx == 0) {
+	signed char m;
+	m = uip_connr->rto - uip_connr->timer;
+	/* This is taken directly from VJs original code in his paper */
+	m = m - (uip_connr->sa >> 3);
+	uip_connr->sa += m;
+	if(m < 0) {
+	  m = -m;
+	}
+	m = m - (uip_connr->sv >> 2);
+	uip_connr->sv += m;
+	uip_connr->rto = (uip_connr->sa >> 3) + uip_connr->sv;
+
+      }
+      /* Set the acknowledged flag. */
+      uip_flags = UIP_ACKDATA;
+      /* Reset the retransmission timer. */
+      uip_connr->timer = uip_connr->rto;
+    }
+    
+  }
+
+  /* Do different things depending on in what state the connection is. */
+  switch(uip_connr->tcpstateflags & TS_MASK) {
+    /* CLOSED and LISTEN are not handled here. CLOSE_WAIT is not
+	implemented, since we force the application to close when the
+	peer sends a FIN (hence the application goes directly from
+	ESTABLISHED to LAST_ACK). */
+  case SYN_RCVD:
+    /* In SYN_RCVD we have sent out a SYNACK in response to a SYN, and
+       we are waiting for an ACK that acknowledges the data we sent
+       out the last time. Therefore, we want to have the UIP_ACKDATA
+       flag set. If so, we enter the ESTABLISHED state. */
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = ESTABLISHED;
+      uip_flags = UIP_CONNECTED;
+      uip_connr->len = 0;
+      if(uip_len > 0) {
+        uip_flags |= UIP_NEWDATA;
+        uip_add_rcv_nxt(uip_len);
+      }
+      uip_slen = 0;
+      UIP_APPCALL();
+      goto appsend;
+    }
+    goto drop;
+#if UIP_ACTIVE_OPEN
+  case SYN_SENT:
+    /* In SYN_SENT, we wait for a SYNACK that is sent in response to
+       our SYN. The rcv_nxt is set to sequence number in the SYNACK
+       plus one, and we send an ACK. We move into the ESTABLISHED
+       state. */
+    if((uip_flags & UIP_ACKDATA) &&
+       BUF->flags == (TCP_SYN | TCP_ACK)) {
+
+      /* Parse the TCP MSS option, if present. */
+      if((BUF->tcpoffset & 0xf0) > 0x50) {
+	for(c = 0; c < ((BUF->tcpoffset >> 4) - 5) << 2 ;) {
+	  opt = uip_buf[40 + UIP_LLH_LEN + c];
+	  if(opt == 0x00) {
+	    /* End of options. */	
+	    break;
+	  } else if(opt == 0x01) {
+	    ++c;
+	    /* NOP option. */
+	  } else if(opt == 0x02 &&
+		    uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0x04) {
+	    /* An MSS option with the right option length. */
+	    tmp16 = (uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 2 + c] << 8) |
+	      uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 3 + c];
+	    uip_connr->initialmss =
+	      uip_connr->mss = tmp16 > UIP_TCP_MSS? UIP_TCP_MSS: tmp16;
+
+	    /* And we are done processing options. */
+	    break;
+	  } else {
+	    /* All other options have a length field, so that we easily
+	       can skip past them. */
+	    if(uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c] == 0) {
+	      /* If the length field is zero, the options are malformed
+		 and we don't process them further. */
+	      break;
+	    }
+	    c += uip_buf[UIP_TCPIP_HLEN + UIP_LLH_LEN + 1 + c];
+	  }      
+	}
+      }
+      uip_connr->tcpstateflags = ESTABLISHED;      
+      uip_connr->rcv_nxt[0] = BUF->seqno[0];
+      uip_connr->rcv_nxt[1] = BUF->seqno[1];
+      uip_connr->rcv_nxt[2] = BUF->seqno[2];
+      uip_connr->rcv_nxt[3] = BUF->seqno[3];
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CONNECTED | UIP_NEWDATA;
+      uip_connr->len = 0;
+      uip_len = 0;
+      uip_slen = 0;
+      UIP_APPCALL();
+      goto appsend;
+    }
+    goto reset;
+#endif /* UIP_ACTIVE_OPEN */
+    
+  case ESTABLISHED:
+    /* In the ESTABLISHED state, we call upon the application to feed
+    data into the uip_buf. If the UIP_ACKDATA flag is set, the
+    application should put new data into the buffer, otherwise we are
+    retransmitting an old segment, and the application should put that
+    data into the buffer.
+
+    If the incoming packet is a FIN, we should close the connection on
+    this side as well, and we send out a FIN and enter the LAST_ACK
+    state. We require that there is no outstanding data; otherwise the
+    sequence numbers will be screwed up. */
+
+    if(BUF->flags & TCP_FIN) {
+      if(uip_outstanding(uip_connr)) {
+	goto drop;
+      }
+      uip_add_rcv_nxt(1 + uip_len);      
+      uip_flags = UIP_CLOSE;
+      if(uip_len > 0) {
+	uip_flags |= UIP_NEWDATA;
+      }
+      UIP_APPCALL();
+      uip_connr->len = 1;
+      uip_connr->tcpstateflags = LAST_ACK;
+      uip_connr->nrtx = 0;
+    tcp_send_finack:
+      BUF->flags = TCP_FIN | TCP_ACK;      
+      goto tcp_send_nodata;
+    }
+
+    /* Check the URG flag. If this is set, the segment carries urgent
+       data that we must pass to the application. */
+    if(BUF->flags & TCP_URG) {
+#if UIP_URGDATA > 0
+      uip_urglen = (BUF->urgp[0] << 8) | BUF->urgp[1];
+      if(uip_urglen > uip_len) {
+	/* There is more urgent data in the next segment to come. */
+	uip_urglen = uip_len;
+      }
+      uip_add_rcv_nxt(uip_urglen);
+      uip_len -= uip_urglen;
+      uip_urgdata = uip_appdata;
+      uip_appdata += uip_urglen;
+    } else {
+      uip_urglen = 0;
+#endif /* UIP_URGDATA > 0 */
+      uip_appdata += (BUF->urgp[0] << 8) | BUF->urgp[1];
+      uip_len -= (BUF->urgp[0] << 8) | BUF->urgp[1];
+    }
+    
+    
+    /* If uip_len > 0 we have TCP data in the packet, and we flag this
+       by setting the UIP_NEWDATA flag and update the sequence number
+       we acknowledge. If the application has stopped the dataflow
+       using uip_stop(), we must not accept any data packets from the
+       remote host. */
+    if(uip_len > 0 && !(uip_connr->tcpstateflags & UIP_STOPPED)) {
+      uip_flags |= UIP_NEWDATA;
+      uip_add_rcv_nxt(uip_len);
+    }
+
+    /* Check if the available buffer space advertised by the other end
+       is smaller than the initial MSS for this connection. If so, we
+       set the current MSS to the window size to ensure that the
+       application does not send more data than the other end can
+       handle.
+
+       If the remote host advertises a zero window, we set the MSS to
+       the initial MSS so that the application will send an entire MSS
+       of data. This data will not be acknowledged by the receiver,
+       and the application will retransmit it. This is called the
+       "persistent timer" and uses the retransmission mechanim.
+    */
+    tmp16 = ((unsigned short int)BUF->wnd[0] << 8) + (unsigned short int)BUF->wnd[1];
+    if(tmp16 > uip_connr->initialmss ||
+       tmp16 == 0) {
+      tmp16 = uip_connr->initialmss;
+    }
+    uip_connr->mss = tmp16;
+
+    /* If this packet constitutes an ACK for outstanding data (flagged
+       by the UIP_ACKDATA flag, we should call the application since it
+       might want to send more data. If the incoming packet had data
+       from the peer (as flagged by the UIP_NEWDATA flag), the
+       application must also be notified.
+
+       When the application is called, the global variable uip_len
+       contains the length of the incoming data. The application can
+       access the incoming data through the global pointer
+       uip_appdata, which usually points 40 bytes into the uip_buf
+       array.
+
+       If the application wishes to send any data, this data should be
+       put into the uip_appdata and the length of the data should be
+       put into uip_len. If the application don't have any data to
+       send, uip_len must be set to 0. */
+	if(uip_flags & (UIP_NEWDATA | UIP_ACKDATA)) {
+      uip_slen = 0;
+      UIP_APPCALL();
+
+    appsend:
+      
+	  if(uip_flags & UIP_ABORT) {
+	uip_slen = 0;
+	uip_connr->tcpstateflags = CLOSED;
+	BUF->flags = TCP_RST | TCP_ACK;
+	goto tcp_send_nodata;
+      }
+
+      if(uip_flags & UIP_CLOSE) {
+	uip_slen = 0;
+	uip_connr->len = 1;
+	uip_connr->tcpstateflags = FIN_WAIT_1;
+	uip_connr->nrtx = 0;
+	BUF->flags = TCP_FIN | TCP_ACK;
+	goto tcp_send_nodata;	
+      }
+
+	  /* If uip_slen > 0, the application has data to be sent. */
+      if(uip_slen > 0) {
+
+	/* If the connection has acknowledged data, the contents of
+	   the ->len variable should be discarded. */ 
+	if((uip_flags & UIP_ACKDATA) != 0) {
+	  uip_connr->len = 0;
+	}
+
+	/* If the ->len variable is non-zero the connection has
+	   already data in transit and cannot send anymore right
+	   now. */
+	if(uip_connr->len == 0) {
+
+	  /* The application cannot send more than what is allowed by
+	     the mss (the minumum of the MSS and the available
+	     window). */
+	  if(uip_slen > uip_connr->mss) {
+		uip_slen = uip_connr->mss;
+	  }
+
+	  /* Remember how much data we send out now so that we know
+	     when everything has been acknowledged. */
+	  uip_connr->len = uip_slen;
+	} else {
+
+	  /* If the application already had unacknowledged data, we
+	     make sure that the application does not send (i.e.,
+	     retransmit) out more than it previously sent out. */
+	  uip_slen = uip_connr->len;
+	}
+      } else {
+	uip_connr->len = 0;
+      }
+      uip_connr->nrtx = 0;
+    apprexmit:
+      uip_appdata = uip_sappdata;
+
+      /* If the application has data to be sent, or if the incoming
+         packet had new data in it, we must send out a packet. */
+      if(uip_slen > 0 && uip_connr->len > 0) {
+	/* Add the length of the IP and TCP headers. */
+	uip_len = uip_connr->len + UIP_TCPIP_HLEN;
+	/* We always set the ACK flag in response packets. */
+	BUF->flags = TCP_ACK | TCP_PSH;
+	/* Send the packet. */
+	goto tcp_send_noopts;
+      }
+      /* If there is no data to send, just send out a pure ACK if
+	 there is newdata. */
+      if(uip_flags & UIP_NEWDATA) {
+	uip_len = UIP_TCPIP_HLEN;
+	BUF->flags = TCP_ACK;
+	goto tcp_send_noopts;
+      }
+    }
+	goto drop;
+  case LAST_ACK:
+    /* We can close this connection if the peer has acknowledged our
+       FIN. This is indicated by the UIP_ACKDATA flag. */     
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = CLOSED;
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+    }
+    break;
+    
+  case FIN_WAIT_1:
+    /* The application has closed the connection, but the remote host
+       hasn't closed its end yet. Thus we do nothing but wait for a
+       FIN from the other side. */
+    if(uip_len > 0) {
+      uip_add_rcv_nxt(uip_len);
+    }
+    if(BUF->flags & TCP_FIN) {
+      if(uip_flags & UIP_ACKDATA) {
+	uip_connr->tcpstateflags = TIME_WAIT;
+	uip_connr->timer = 0;
+	uip_connr->len = 0;
+      } else {
+	uip_connr->tcpstateflags = CLOSING;
+      }
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+      goto tcp_send_ack;
+    } else if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = FIN_WAIT_2;
+      uip_connr->len = 0;
+      goto drop;
+    }
+    if(uip_len > 0) {
+      goto tcp_send_ack;
+    }
+    goto drop;
+      
+  case FIN_WAIT_2:
+    if(uip_len > 0) {
+      uip_add_rcv_nxt(uip_len);
+    }
+    if(BUF->flags & TCP_FIN) {
+      uip_connr->tcpstateflags = TIME_WAIT;
+      uip_connr->timer = 0;
+      uip_add_rcv_nxt(1);
+      uip_flags = UIP_CLOSE;
+      UIP_APPCALL();
+      goto tcp_send_ack;
+    }
+    if(uip_len > 0) {
+      goto tcp_send_ack;
+    }
+    goto drop;
+
+  case TIME_WAIT:
+    goto tcp_send_ack;
+    
+  case CLOSING:
+    if(uip_flags & UIP_ACKDATA) {
+      uip_connr->tcpstateflags = TIME_WAIT;
+      uip_connr->timer = 0;
+    }
+  }  
+  goto drop;
+  
+
+  /* We jump here when we are ready to send the packet, and just want
+     to set the appropriate TCP sequence numbers in the TCP header. */
+ tcp_send_ack:
+  BUF->flags = TCP_ACK;
+ tcp_send_nodata:
+  uip_len = 40;
+ tcp_send_noopts:
+  BUF->tcpoffset = 5 << 4;
+ tcp_send:
+  /* We're done with the input processing. We are now ready to send a
+     reply. Our job is to fill in all the fields of the TCP and IP
+     headers before calculating the checksum and finally send the
+     packet. */
+  BUF->ackno[0] = uip_connr->rcv_nxt[0];
+  BUF->ackno[1] = uip_connr->rcv_nxt[1];
+  BUF->ackno[2] = uip_connr->rcv_nxt[2];
+  BUF->ackno[3] = uip_connr->rcv_nxt[3];
+  
+  BUF->seqno[0] = uip_connr->snd_nxt[0];
+  BUF->seqno[1] = uip_connr->snd_nxt[1];
+  BUF->seqno[2] = uip_connr->snd_nxt[2];
+  BUF->seqno[3] = uip_connr->snd_nxt[3];
+
+  BUF->proto = UIP_PROTO_TCP;
+  
+  BUF->srcport  = uip_connr->lport;
+  BUF->destport = uip_connr->rport;
+
+  BUF->srcipaddr[0] = uip_hostaddr[0];
+  BUF->srcipaddr[1] = uip_hostaddr[1];
+  BUF->destipaddr[0] = uip_connr->ripaddr[0];
+  BUF->destipaddr[1] = uip_connr->ripaddr[1];
+ 
+
+  if(uip_connr->tcpstateflags & UIP_STOPPED) {
+    /* If the connection has issued uip_stop(), we advertise a zero
+       window so that the remote host will stop sending data. */
+    BUF->wnd[0] = BUF->wnd[1] = 0;
+  } else {
+    BUF->wnd[0] = ((UIP_RECEIVE_WINDOW) >> 8);
+    BUF->wnd[1] = ((UIP_RECEIVE_WINDOW) & 0xff); 
+  }
+
+ tcp_send_noconn:
+
+  BUF->len[0] = (uip_len >> 8);
+  BUF->len[1] = (uip_len & 0xff);
+
+  /* Calculate TCP checksum. */
+  BUF->tcpchksum = 0;
+  BUF->tcpchksum = ~(uip_tcpchksum());
+  
+ //ip_send_nolen:
+
+  BUF->vhl = 0x45;
+  BUF->tos = 0;
+  BUF->ipoffset[0] = BUF->ipoffset[1] = 0;
+  BUF->ttl  = UIP_TTL;
+  ++ipid;
+  BUF->ipid[0] = ipid >> 8;
+  BUF->ipid[1] = ipid & 0xff;
+  
+  /* Calculate IP checksum. */
+  BUF->ipchksum = 0;
+  BUF->ipchksum = ~(uip_ipchksum());
+
+  UIP_STAT(++uip_stat.tcp.sent);
+ send:
+  UIP_STAT(++uip_stat.ip.sent);
+  /* Return and let the caller do the actual transmission. */
+  return;
+ drop:
+  uip_len = 0;
+  return;
+}
+/*-----------------------------------------------------------------------------------*/
+/*unsigned short int
+htons(unsigned short int val)
+{
+  return HTONS(val);
+}*/
+/*-----------------------------------------------------------------------------------*/
+/** @} */
diff --git a/board/broadcom/bcmbca/httpd/uip.h b/board/broadcom/bcmbca/httpd/uip.h
new file mode 100644
index 0000000000..6012de7be0
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/uip.h
@@ -0,0 +1,1066 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \file
+ * Header file for the uIP TCP/IP stack.
+ * \author Adam Dunkels <adam@dunkels.com>
+ *
+ * The uIP TCP/IP stack header file contains definitions for a number
+ * of C macros that are used by uIP programs as well as internal uIP
+ * structures, TCP/IP header structures and function declarations.
+ *
+ */
+
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip.h,v 1.36.2.7 2003/10/07 13:47:51 adam Exp $
+ *
+ */
+
+#ifndef __UIP_H__
+#define __UIP_H__
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <malloc.h>
+#include <common.h>
+
+
+#include "uipopt.h"
+
+/*-----------------------------------------------------------------------------------*/
+/* First, the functions that should be called from the
+ * system. Initialization, the periodic timer and incoming packets are
+ * handled by the following three functions.
+ */
+
+/**
+ * \defgroup uipconffunc uIP configuration functions
+ * @{
+ *
+ * The uIP configuration functions are used for setting run-time
+ * parameters in uIP such as IP addresses. 
+ */
+
+/**
+ * Set the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * \param addr A pointer to a 4-byte representation of the IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_sethostaddr(addr) do { uip_hostaddr[0] = addr[0]; \
+                              uip_hostaddr[1] = addr[1]; } while(0)
+
+/**
+ * Get the IP address of this host.
+ *
+ * The IP address is represented as a 4-byte array where the first
+ * octet of the IP address is put in the first member of the 4-byte
+ * array.
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the currently configured IP address.
+ *
+ * \hideinitializer
+ */
+#define uip_gethostaddr(addr) do { addr[0] = uip_hostaddr[0]; \
+                              addr[1] = uip_hostaddr[1]; } while(0)
+
+/** @} */
+
+/**
+ * \defgroup uipinit uIP initialization functions
+ * @{
+ *
+ * The uIP initialization functions are used for booting uIP.
+ */
+
+/**
+ * uIP initialization function.
+ *
+ * This function should be called at boot up to initilize the uIP
+ * TCP/IP stack.
+ */
+void uip_init(void);
+
+/** @} */
+
+/**
+ * \defgroup uipdevfunc uIP device driver functions
+ * @{
+ *
+ * These functions are used by a network device driver for interacting
+ * with uIP.
+ */
+
+/**
+ * Process an incoming packet.
+ *
+ * This function should be called when the device driver has received
+ * a packet from the network. The packet from the device driver must
+ * be present in the uip_buf buffer, and the length of the packet
+ * should be placed in the uip_len variable.
+ *
+ * When the function returns, there may be an outbound packet placed
+ * in the uip_buf packet buffer. If so, the uip_len variable is set to
+ * the length of the packet. If no packet is to be sent out, the
+ * uip_len variable is set to 0.
+ *
+ * The usual way of calling the function is presented by the source
+ * code below.
+ \code
+  uip_len = devicedriver_poll();
+  if(uip_len > 0) {
+    uip_input();
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uIP ARP code before calling
+ * this function:
+ \code
+  #define BUF ((struct uip_eth_hdr *)&uip_buf[0])
+  uip_len = ethernet_devicedrver_poll();
+  if(uip_len > 0) {
+    if(BUF->type == HTONS(UIP_ETHTYPE_IP)) {
+      uip_arp_ipin();
+      uip_input();
+      if(uip_len > 0) {
+        uip_arp_out();
+	ethernet_devicedriver_send();
+      }
+    } else if(BUF->type == HTONS(UIP_ETHTYPE_ARP)) {
+      uip_arp_arpin();
+      if(uip_len > 0) {
+	ethernet_devicedriver_send();
+      }
+    }
+ \endcode
+ *
+ * \hideinitializer
+ */
+#define uip_input()        uip_process(UIP_DATA)
+
+/**
+ * Periodic processing for a connection identified by its number.
+ * 
+ * This function does the necessary periodic processing (timers,
+ * polling) for a uIP TCP conneciton, and should be called when the
+ * periodic uIP timer goes off. It should be called for every
+ * connection, regardless of whether they are open of closed.
+ *
+ * When the function returns, it may have an outbound packet waiting
+ * for service in the uIP packet buffer, and if so the uip_len
+ * variable is set to a value larger than zero. The device driver
+ * should be called to send out the packet.
+ *
+ * The ususal way of calling the function is through a for() loop like
+ * this:
+ \code
+  for(i = 0; i < UIP_CONNS; ++i) {
+    uip_periodic(i);
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }
+ \endcode
+ *
+ * \note If you are writing a uIP device driver that needs ARP
+ * (Address Resolution Protocol), e.g., when running uIP over
+ * Ethernet, you will need to call the uip_arp_out() function before
+ * calling the device driver:
+ \code
+  for(i = 0; i < UIP_CONNS; ++i) {
+    uip_periodic(i);
+    if(uip_len > 0) {
+      uip_arp_out();
+      ethernet_devicedriver_send();
+    }
+  }
+ \endcode 
+ *
+ * \param conn The number of the connection which is to be periodically polled.
+ *
+ * \hideinitializer
+ */
+#define uip_periodic(conn) do { uip_conn = &uip_conns[conn]; \
+                                uip_process(UIP_TIMER); } while (0)
+
+/**
+ * Periodic processing for a connection identified by a pointer to its structure.
+ *
+ * Same as uip_periodic() but takes a pointer to the actual uip_conn
+ * struct instead of an integer as its argument. This function can be
+ * used to force periodic processing of a specific connection.
+ *
+ * \param conn A pointer to the uip_conn struct for the connection to
+ * be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_periodic_conn(conn) do { uip_conn = conn; \
+                                     uip_process(UIP_TIMER); } while (0)
+
+#if UIP_UDP
+/**
+ * Periodic processing for a UDP connection identified by its number.
+ *
+ * This function is essentially the same as uip_prerioic(), but for
+ * UDP connections. It is called in a similar fashion as the
+ * uip_periodic() function:
+ \code
+  for(i = 0; i < UIP_UDP_CONNS; i++) {
+    uip_udp_periodic(i);
+    if(uip_len > 0) {
+      devicedriver_send();
+    }
+  }   
+ \endcode
+ *
+ * \note As for the uip_periodic() function, special care has to be
+ * taken when using uIP together with ARP and Ethernet:
+ \code
+  for(i = 0; i < UIP_UDP_CONNS; i++) {
+    uip_udp_periodic(i);
+    if(uip_len > 0) {
+      uip_arp_out();
+      ethernet_devicedriver_send();
+    }
+  }   
+ \endcode
+ *
+ * \param conn The number of the UDP connection to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic(conn) do { uip_udp_conn = &uip_udp_conns[conn]; \
+                                uip_process(UIP_UDP_TIMER); } while (0)
+
+/**
+ * Periodic processing for a UDP connection identified by a pointer to
+ * its structure.
+ *
+ * Same as uip_udp_periodic() but takes a pointer to the actual
+ * uip_conn struct instead of an integer as its argument. This
+ * function can be used to force periodic processing of a specific
+ * connection.
+ *
+ * \param conn A pointer to the uip_udp_conn struct for the connection
+ * to be processed.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_periodic_conn(conn) do { uip_udp_conn = conn; \
+                                         uip_process(UIP_UDP_TIMER); } while (0)
+
+
+#endif /* UIP_UDP */
+
+/**
+ * The uIP packet buffer.
+ *
+ * The uip_buf array is used to hold incoming and outgoing
+ * packets. The device driver should place incoming data into this
+ * buffer. When sending data, the device driver should read the link
+ * level headers and the TCP/IP headers from this buffer. The size of
+ * the link level headers is configured by the UIP_LLH_LEN define.
+ *
+ * \note The application data need not be placed in this buffer, so
+ * the device driver must read it from the place pointed to by the
+ * uip_appdata pointer as illustrated by the following example:
+ \code
+ void
+ devicedriver_send(void)
+ {
+    hwsend(&uip_buf[0], UIP_LLH_LEN);
+    hwsend(&uip_buf[UIP_LLH_LEN], 40);
+    hwsend(uip_appdata, uip_len - 40 - UIP_LLH_LEN);
+ }
+ \endcode
+ */
+extern u8_t uip_buf[UIP_BUFSIZE+4];
+
+/** @} */
+
+/*-----------------------------------------------------------------------------------*/
+/* Functions that are used by the uIP application program. Opening and
+ * closing connections, sending and receiving data, etc. is all
+ * handled by the functions below.
+*/
+/**
+ * \defgroup uipappfunc uIP application functions
+ * @{
+ *
+ * Functions used by an application running of top of uIP.
+ */
+
+/**
+ * Start listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_listen(HTONS(80)); 
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void uip_listen(u16_t port);
+
+/**
+ * Stop listening to the specified port.
+ *
+ * \note Since this function expects the port number in network byte
+ * order, a conversion using HTONS() or htons() is necessary.
+ *
+ \code
+ uip_unlisten(HTONS(80)); 
+ \endcode
+ *
+ * \param port A 16-bit port number in network byte order.
+ */
+void uip_unlisten(u16_t port);
+
+/**
+ * Connect to a remote host using TCP.
+ *
+ * This function is used to start a new connection to the specified
+ * port on the specied host. It allocates a new connection identifier,
+ * sets the connection to the SYN_SENT state and sets the
+ * retransmission timer to 0. This will cause a TCP SYN segment to be
+ * sent out the next time this connection is periodically processed,
+ * which usually is done within 0.5 seconds after the call to
+ * uip_connect().
+ *
+ * \note This function is avaliable only if support for active open
+ * has been configured by defining UIP_ACTIVE_OPEN to 1 in uipopt.h.
+ *
+ * \note Since this function requires the port number to be in network
+ * byte order, a convertion using HTONS() or htons() is necessary.
+ *
+ \code
+ u16_t ipaddr[2];
+
+ uip_ipaddr(ipaddr, 192,168,1,2);
+ uip_connect(ipaddr, HTONS(80)); 
+ \endcode
+ * 
+ * \param ripaddr A pointer to a 4-byte array representing the IP
+ * address of the remote hot.
+ *
+ * \param port A 16-bit port number in network byte order.
+ *
+ * \return A pointer to the uIP connection identifier for the new connection,
+ * or NULL if no connection could be allocated.   
+ *
+ */
+struct uip_conn *uip_connect(u16_t *ripaddr, u16_t port);
+
+
+
+/**
+ * \internal
+ *
+ * Check if a connection has outstanding (i.e., unacknowledged) data.
+ *
+ * \param conn A pointer to the uip_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_outstanding(conn) ((conn)->len)
+
+/**
+ * Send data on the current connection.
+ *
+ * This function is used to send out a single segment of TCP
+ * data. Only applications that have been invoked by uIP for event
+ * processing can send data. 
+ *
+ * The amount of data that actually is sent out after a call to this
+ * funcion is determined by the maximum amount of data TCP allows. uIP
+ * will automatically crop the data so that only the appropriate
+ * amount of data is sent. The function uip_mss() can be used to query
+ * uIP for the amount of data that actually will be sent.
+ * 
+ * \note This function does not guarantee that the sent data will
+ * arrive at the destination. If the data is lost in the network, the
+ * application will be invoked with the uip_rexmit() event being
+ * set. The application will then have to resend the data using this
+ * function.
+ * 
+ * \param data A pointer to the data which is to be sent.
+ *
+ * \param len The maximum amount of data bytes to be sent.
+ *
+ * \hideinitializer
+ */
+#define uip_send(data, len) do { uip_sappdata = (data); uip_slen = (len);} while(0)   
+
+/**
+ * The length of any incoming data that is currently avaliable (if avaliable)
+ * in the uip_appdata buffer.
+ *
+ * The test function uip_data() must first be used to check if there
+ * is any data available at all.
+ *
+ * \hideinitializer
+ */
+#define uip_datalen()       uip_len
+
+/**
+ * The length of any out-of-band data (urgent data) that has arrived
+ * on the connection.
+ *
+ * \note The configuration parameter UIP_URGDATA must be set for this
+ * function to be enabled.
+ *
+ * \hideinitializer
+ */
+#define uip_urgdatalen()    uip_urglen
+
+/**
+ * Close the current connection.
+ *
+ * This function will close the current connection in a nice way.
+ *
+ * \hideinitializer
+ */
+#define uip_close()         (uip_flags = UIP_CLOSE)
+
+/**
+ * Abort the current connection.
+ *
+ * This function will abort (reset) the current connection, and is
+ * usually used when an error has occured that prevents using the
+ * uip_close() function.
+ *
+ * \hideinitializer
+ */
+#define uip_abort()         (uip_flags = UIP_ABORT)
+
+/**
+ * Tell the sending host to stop sending data.
+ *
+ * This function will close our receiver's window so that we stop
+ * receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_stop()          (uip_conn->tcpstateflags |= UIP_STOPPED)
+
+/**
+ * Find out if the current connection has been previously stopped with
+ * uip_stop().
+ *
+ * \hideinitializer
+ */
+#define uip_stopped(conn)   ((conn)->tcpstateflags & UIP_STOPPED)
+
+/**
+ * Restart the current connection, if is has previously been stopped
+ * with uip_stop().
+ *
+ * This function will open the receiver's window again so that we
+ * start receiving data for the current connection.
+ *
+ * \hideinitializer
+ */
+#define uip_restart()         do { uip_flags |= UIP_NEWDATA; \
+                                   uip_conn->tcpstateflags &= ~UIP_STOPPED; \
+                              } while(0)
+
+
+/* uIP tests that can be made to determine in what state the current
+   connection is, and what the application function should do. */
+
+/**
+ * Is new incoming data available?
+ *
+ * Will reduce to non-zero if there is new data for the application
+ * present at the uip_appdata pointer. The size of the data is
+ * avaliable through the uip_len variable.
+ *
+ * \hideinitializer
+ */
+#define uip_newdata()   (uip_flags & UIP_NEWDATA)
+
+/**
+ * Has previously sent data been acknowledged?
+ *
+ * Will reduce to non-zero if the previously sent data has been
+ * acknowledged by the remote host. This means that the application
+ * can send new data. 
+ *
+ * \hideinitializer
+ */
+#define uip_acked()   (uip_flags & UIP_ACKDATA)
+
+/**
+ * Has the connection just been connected?  
+ *
+ * Reduces to non-zero if the current connection has been connected to
+ * a remote host. This will happen both if the connection has been
+ * actively opened (with uip_connect()) or passively opened (with
+ * uip_listen()).
+ *
+ * \hideinitializer
+ */
+#define uip_connected() (uip_flags & UIP_CONNECTED)
+
+/**
+ * Has the connection been closed by the other end?
+ *
+ * Is non-zero if the connection has been closed by the remote
+ * host. The application may then do the necessary clean-ups.
+ *
+ * \hideinitializer
+ */
+#define uip_closed()    (uip_flags & UIP_CLOSE)
+
+/**
+ * Has the connection been aborted by the other end?
+ *
+ * Non-zero if the current connection has been aborted (reset) by the
+ * remote host.
+ *
+ * \hideinitializer
+ */
+#define uip_aborted()    (uip_flags & UIP_ABORT)
+
+/**
+ * Has the connection timed out?
+ *
+ * Non-zero if the current connection has been aborted due to too many
+ * retransmissions.
+ *
+ * \hideinitializer
+ */
+#define uip_timedout()    (uip_flags & UIP_TIMEDOUT)
+
+/**
+ * Do we need to retransmit previously data?
+ *
+ * Reduces to non-zero if the previously sent data has been lost in
+ * the network, and the application should retransmit it. The
+ * application should send the exact same data as it did the last
+ * time, using the uip_send() function.
+ *
+ * \hideinitializer
+ */
+#define uip_rexmit()     (uip_flags & UIP_REXMIT)
+
+/**
+ * Is the connection being polled by uIP?
+ *
+ * Is non-zero if the reason the application is invoked is that the
+ * current connection has been idle for a while and should be
+ * polled.
+ *
+ * The polling event can be used for sending data without having to
+ * wait for the remote host to send data.
+ *
+ * \hideinitializer
+ */ 
+#define uip_poll()       (uip_flags & UIP_POLL)
+
+/**
+ * Get the initial maxium segment size (MSS) of the current
+ * connection.
+ *
+ * \hideinitializer
+ */
+#define uip_initialmss()             (uip_conn->initialmss)
+
+/**
+ * Get the current maxium segment size that can be sent on the current
+ * connection.
+ *
+ * The current maxiumum segment size that can be sent on the
+ * connection is computed from the receiver's window and the MSS of
+ * the connection (which also is available by calling
+ * uip_initialmss()).
+ *
+ * \hideinitializer
+ */
+#define uip_mss()             (uip_conn->mss)
+
+/**
+ * Set up a new UDP connection.
+ *
+ * \param ripaddr A pointer to a 4-byte structure representing the IP
+ * address of the remote host.
+ *
+ * \param rport The remote port number in network byte order.
+ *
+ * \return The uip_udp_conn structure for the new connection or NULL
+ * if no connection could be allocated.
+ */
+struct uip_udp_conn *uip_udp_new(u16_t *ripaddr, u16_t rport);
+
+/**
+ * Removed a UDP connection.
+ *
+ * \param conn A pointer to the uip_udp_conn structure for the connection.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_remove(conn) (conn)->lport = 0
+
+/**
+ * Send a UDP datagram of length len on the current connection.
+ *
+ * This function can only be called in response to a UDP event (poll
+ * or newdata). The data must be present in the uip_buf buffer, at the
+ * place pointed to by the uip_appdata pointer.
+ *
+ * \param len The length of the data in the uip_buf buffer.
+ *
+ * \hideinitializer
+ */
+#define uip_udp_send(len) uip_slen = (len)
+
+/** @} */
+
+/* uIP convenience and converting functions. */
+
+/**
+ * \defgroup uipconvfunc uIP conversion functions
+ * @{
+ *
+ * These functions can be used for converting between different data
+ * formats used by uIP.
+ */
+ 
+/**
+ * Pack an IP address into a 4-byte array which is used by uIP to
+ * represent IP addresses.
+ *
+ * Example:
+ \code
+ u16_t ipaddr[2];
+
+ uip_ipaddr(&ipaddr, 192,168,1,2); 
+ \endcode
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the IP addres.
+ * \param addr0 The first octet of the IP address.
+ * \param addr1 The second octet of the IP address.
+ * \param addr2 The third octet of the IP address.
+ * \param addr3 The forth octet of the IP address. 
+ *
+ * \hideinitializer
+ */
+#define uip_ipaddr(addr, addr0,addr1,addr2,addr3) do { \
+                     (addr)[0] = HTONS(((addr0) << 8) | (addr1)); \
+                     (addr)[1] = HTONS(((addr2) << 8) | (addr3)); \
+                  } while(0)
+
+/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This macro is primarily used for converting constants from host
+ * byte order to network byte order. For converting variables to
+ * network byte order, use the htons() function instead.
+ *
+ * \hideinitializer
+ */
+#ifndef HTONS
+#   if BYTE_ORDER == BIG_ENDIAN
+#      define HTONS(n) (n)
+#   else /* BYTE_ORDER == BIG_ENDIAN */
+#      define HTONS(n) ((((u16_t)((n) & 0xff)) << 8) | (((n) & 0xff00) >> 8))
+#   endif /* BYTE_ORDER == BIG_ENDIAN */
+#endif /* HTONS */
+
+/**
+ * Convert 16-bit quantity from host byte order to network byte order.
+ *
+ * This function is primarily used for converting variables from host
+ * byte order to network byte order. For converting constants to
+ * network byte order, use the HTONS() macro instead.
+ */
+#ifndef htons
+u16_t htons(u16_t val);
+#endif /* htons */
+
+/** @} */
+
+/**
+ * Pointer to the application data in the packet buffer.
+ *
+ * This pointer points to the application data when the application is
+ * called. If the application wishes to send data, the application may
+ * use this space to write the data into before calling uip_send().
+ */
+extern volatile u8_t *uip_appdata;
+extern volatile u8_t *uip_sappdata; 
+
+#if UIP_URGDATA > 0 
+/* u8_t *uip_urgdata:
+ *
+ * This pointer points to any urgent data that has been received. Only
+ * present if compiled with support for urgent data (UIP_URGDATA).
+ */
+extern volatile u8_t *uip_urgdata; 
+#endif /* UIP_URGDATA > 0 */
+
+
+/* u[8|16]_t uip_len:
+ *
+ * When the application is called, uip_len contains the length of any
+ * new data that has been received from the remote host. The
+ * application should set this variable to the size of any data that
+ * the application wishes to send. When the network device driver
+ * output function is called, uip_len should contain the length of the
+ * outgoing packet.
+ */
+extern volatile u16_t uip_len, uip_slen;
+
+#if UIP_URGDATA > 0 
+extern volatile u8_t uip_urglen, uip_surglen;
+#endif /* UIP_URGDATA > 0 */
+
+
+/**
+ * Representation of a uIP TCP connection.
+ *
+ * The uip_conn structure is used for identifying a connection. All
+ * but one field in the structure are to be considered read-only by an
+ * application. The only exception is the appstate field whos purpose
+ * is to let the application store application-specific state (e.g.,
+ * file pointers) for the connection. The size of this field is
+ * configured in the "uipopt.h" header file.
+ */
+struct uip_conn {
+  u16_t ripaddr[2];   /**< The IP address of the remote host. */
+  
+  u16_t lport;        /**< The local TCP port, in network byte order. */
+  u16_t rport;        /**< The local remote TCP port, in network byte
+			 order. */  
+  
+  u8_t rcv_nxt[4];    /**< The sequence number that we expect to
+			 receive next. */
+  u8_t snd_nxt[4];    /**< The sequence number that was last sent by
+                         us. */
+  u16_t len;          /**< Length of the data that was previously sent. */
+  u16_t mss;          /**< Current maximum segment size for the
+			 connection. */
+  u16_t initialmss;   /**< Initial maximum segment size for the
+			 connection. */  
+  u8_t sa;            /**< Retransmission time-out calculation state
+			 variable. */
+  u8_t sv;            /**< Retransmission time-out calculation state
+			 variable. */
+  u16_t rto;           /**< Retransmission time-out. */
+  u16_t tcpstateflags; /**< TCP state and flags. */
+  u16_t timer;         /**< The retransmission timer. */
+  u16_t nrtx;          /**< The number of retransmissions for the last
+			 segment sent. */
+
+  /** The application state. */
+  u8_t appstate[UIP_APPSTATE_SIZE];  
+};
+
+
+/* Pointer to the current connection. */
+extern struct uip_conn *uip_conn;
+/* The array containing all uIP connections. */
+extern struct uip_conn uip_conns[UIP_CONNS];
+/**
+ * \addtogroup uiparch
+ * @{
+ */
+
+/**
+ * 4-byte array used for the 32-bit sequence number calculations.
+ */
+extern volatile u8_t uip_acc32[4];
+
+/** @} */
+
+
+#if UIP_UDP
+/**
+ * Representation of a uIP UDP connection.
+ */
+struct uip_udp_conn {
+  u16_t ripaddr[2];   /**< The IP address of the remote peer. */
+  u16_t lport;        /**< The local port number in network byte order. */
+  u16_t rport;        /**< The remote port number in network byte order. */
+};
+
+extern struct uip_udp_conn *uip_udp_conn;
+extern struct uip_udp_conn uip_udp_conns[UIP_UDP_CONNS];
+#endif /* UIP_UDP */
+
+/**
+ * The structure holding the TCP/IP statistics that are gathered if
+ * UIP_STATISTICS is set to 1.
+ *
+ */
+struct uip_stats {
+  struct {
+    uip_stats_t drop;     /**< Number of dropped packets at the IP
+			     layer. */
+    uip_stats_t recv;     /**< Number of received packets at the IP
+			     layer. */
+    uip_stats_t sent;     /**< Number of sent packets at the IP
+			     layer. */
+    uip_stats_t vhlerr;   /**< Number of packets dropped due to wrong
+			     IP version or header length. */
+    uip_stats_t hblenerr; /**< Number of packets dropped due to wrong
+			     IP length, high byte. */
+    uip_stats_t lblenerr; /**< Number of packets dropped due to wrong
+			     IP length, low byte. */
+    uip_stats_t fragerr;  /**< Number of packets dropped since they
+			     were IP fragments. */
+    uip_stats_t chkerr;   /**< Number of packets dropped due to IP
+			     checksum errors. */
+    uip_stats_t protoerr; /**< Number of packets dropped since they
+			     were neither ICMP, UDP nor TCP. */
+  } ip;                   /**< IP statistics. */
+  struct {
+    uip_stats_t drop;     /**< Number of dropped ICMP packets. */
+    uip_stats_t recv;     /**< Number of received ICMP packets. */
+    uip_stats_t sent;     /**< Number of sent ICMP packets. */
+    uip_stats_t typeerr;  /**< Number of ICMP packets with a wrong
+			     type. */
+  } icmp;                 /**< ICMP statistics. */
+  struct {
+    uip_stats_t drop;     /**< Number of dropped TCP segments. */
+    uip_stats_t recv;     /**< Number of recived TCP segments. */
+    uip_stats_t sent;     /**< Number of sent TCP segments. */
+    uip_stats_t chkerr;   /**< Number of TCP segments with a bad
+			     checksum. */
+    uip_stats_t ackerr;   /**< Number of TCP segments with a bad ACK
+			     number. */
+    uip_stats_t rst;      /**< Number of recevied TCP RST (reset) segments. */
+    uip_stats_t rexmit;   /**< Number of retransmitted TCP segments. */
+    uip_stats_t syndrop;  /**< Number of dropped SYNs due to too few
+			     connections was avaliable. */
+    uip_stats_t synrst;   /**< Number of SYNs for closed ports,
+			     triggering a RST. */
+  } tcp;                  /**< TCP statistics. */
+};
+
+/**
+ * The uIP TCP/IP statistics.
+ *
+ * This is the variable in which the uIP TCP/IP statistics are gathered.
+ */
+extern struct uip_stats uip_stat;
+
+
+/*-----------------------------------------------------------------------------------*/
+/* All the stuff below this point is internal to uIP and should not be
+ * used directly by an application or by a device driver.
+ */
+/*-----------------------------------------------------------------------------------*/
+/* u8_t uip_flags:
+ *
+ * When the application is called, uip_flags will contain the flags
+ * that are defined in this file. Please read below for more
+ * infomation.
+ */
+extern volatile u8_t uip_flags;
+
+/* The following flags may be set in the global variable uip_flags
+   before calling the application callback. The UIP_ACKDATA and
+   UIP_NEWDATA flags may both be set at the same time, whereas the
+   others are mutualy exclusive. Note that these flags should *NOT* be
+   accessed directly, but through the uIP functions/macros. */
+
+#define UIP_ACKDATA   1     /* Signifies that the outstanding data was
+			       acked and the application should send
+			       out new data instead of retransmitting
+			       the last data. */
+#define UIP_NEWDATA   2     /* Flags the fact that the peer has sent
+			       us new data. */
+#define UIP_REXMIT    4     /* Tells the application to retransmit the
+			       data that was last sent. */
+#define UIP_POLL      8     /* Used for polling the application, to
+			       check if the application has data that
+			       it wants to send. */
+#define UIP_CLOSE     16    /* The remote host has closed the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to close the
+			       connection. */
+#define UIP_ABORT     32    /* The remote host has aborted the
+			       connection, thus the connection has
+			       gone away. Or the application signals
+			       that it wants to abort the
+			       connection. */
+#define UIP_CONNECTED 64    /* We have got a connection from a remote
+                               host and have set up a new connection
+                               for it, or an active connection has
+                               been successfully established. */
+
+#define UIP_TIMEDOUT  128   /* The connection has been aborted due to
+			       too many retransmissions. */
+
+
+/* uip_process(flag):
+ *
+ * The actual uIP function which does all the work.
+ */
+void uip_process(u8_t flag);
+
+/* The following flags are passed as an argument to the uip_process()
+   function. They are used to distinguish between the two cases where
+   uip_process() is called. It can be called either because we have
+   incoming data that should be processed, or because the periodic
+   timer has fired. */
+
+#define UIP_DATA    1     /* Tells uIP that there is incoming data in
+                             the uip_buf buffer. The length of the
+                             data is stored in the global variable
+                             uip_len. */
+#define UIP_TIMER   2     /* Tells uIP that the periodic timer has
+                             fired. */
+#if UIP_UDP
+#define UIP_UDP_TIMER 3
+#endif /* UIP_UDP */
+
+/* The TCP states used in the uip_conn->tcpstateflags. */
+#define CLOSED      0
+#define SYN_RCVD    1
+#define SYN_SENT    2
+#define ESTABLISHED 3
+#define FIN_WAIT_1  4
+#define FIN_WAIT_2  5
+#define CLOSING     6
+#define TIME_WAIT   7
+#define LAST_ACK    8
+#define TS_MASK     15
+  
+#define UIP_STOPPED      16
+
+#define UIP_TCPIP_HLEN 40
+
+/* The TCP and IP headers. */
+typedef struct {
+  /* IP header. */
+  u8_t vhl,
+    tos,          
+    len[2],       
+    ipid[2],        
+    ipoffset[2],  
+    ttl,          
+    proto;     
+  u16_t ipchksum;
+  u16_t srcipaddr[2], 
+    destipaddr[2];
+  
+  /* TCP header. */
+  u16_t srcport,
+    destport;
+  u8_t seqno[4],  
+    ackno[4],
+    tcpoffset,
+    flags,
+    wnd[2];     
+  u16_t tcpchksum;
+  u8_t urgp[2];
+  u8_t optdata[4];
+} uip_tcpip_hdr;
+
+/* The ICMP and IP headers. */
+typedef struct {
+  /* IP header. */
+  u8_t vhl,
+    tos,          
+    len[2],       
+    ipid[2],        
+    ipoffset[2],  
+    ttl,          
+    proto;     
+  u16_t ipchksum;
+  u16_t srcipaddr[2], 
+    destipaddr[2];
+  /* ICMP (echo) header. */
+  u8_t type, icode;
+  u16_t icmpchksum;
+  u16_t id, seqno;  
+} uip_icmpip_hdr;
+
+
+/* The UDP and IP headers. */
+typedef struct {
+  /* IP header. */
+  u8_t vhl,
+    tos,          
+    len[2],       
+    ipid[2],        
+    ipoffset[2],  
+    ttl,          
+    proto;     
+  u16_t ipchksum;
+  u16_t srcipaddr[2], 
+    destipaddr[2];
+  
+  /* UDP header. */
+  u16_t srcport,
+    destport;
+  u16_t udplen;
+  u16_t udpchksum;
+} uip_udpip_hdr;
+
+#define UIP_PROTO_ICMP  1
+#define UIP_PROTO_TCP   6
+#define UIP_PROTO_UDP   17
+
+#if UIP_FIXEDADDR
+extern const u16_t uip_hostaddr[2];
+#else /* UIP_FIXEDADDR */
+extern u16_t uip_hostaddr[2];
+#endif /* UIP_FIXEDADDR */
+
+#endif /* __UIP_H__ */
+
+
+/** @} */
+
diff --git a/board/broadcom/bcmbca/httpd/uip_arch.c b/board/broadcom/bcmbca/httpd/uip_arch.c
new file mode 100644
index 0000000000..cb3952bf73
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/uip_arch.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arch.c,v 1.2.2.1 2003/10/04 22:54:17 adam Exp $
+ *
+ */
+
+
+#include "uip.h"
+#include "uip_arch.h"
+
+#define BUF ((uip_tcpip_hdr *)&uip_buf[UIP_LLH_LEN])
+#define IP_PROTO_TCP    6
+
+/*-----------------------------------------------------------------------------------*/
+void
+uip_add32(u8_t *op32, u16_t op16)
+{
+  
+  uip_acc32[3] = op32[3] + (op16 & 0xff);
+  uip_acc32[2] = op32[2] + (op16 >> 8);
+  uip_acc32[1] = op32[1];
+  uip_acc32[0] = op32[0];
+  
+  if(uip_acc32[2] < (op16 >> 8)) {
+    ++uip_acc32[1];    
+    if(uip_acc32[1] == 0) {
+      ++uip_acc32[0];
+    }
+  }
+  
+  
+  if(uip_acc32[3] < (op16 & 0xff)) {
+    ++uip_acc32[2];  
+    if(uip_acc32[2] == 0) {
+      ++uip_acc32[1];    
+      if(uip_acc32[1] == 0) {
+	++uip_acc32[0];
+      }
+    }
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+u16_t
+uip_chksum(u16_t *sdata, u16_t len)
+{
+  u16_t acc;
+  
+  for(acc = 0; len > 1; len -= 2) {
+    acc += *sdata;
+    if(acc < *sdata) {
+      /* Overflow, so we add the carry to acc (i.e., increase by
+         one). */
+      ++acc;
+    }
+    ++sdata;
+  }
+
+  /* add up any odd byte */
+  if(len == 1) {
+    acc += htons(((u16_t)(*(u8_t *)sdata)) << 8);
+    if(acc < htons(((u16_t)(*(u8_t *)sdata)) << 8)) {
+      ++acc;
+    }
+  }
+
+  return acc;
+}
+/*-----------------------------------------------------------------------------------*/
+u16_t
+uip_ipchksum(void)
+{
+  return uip_chksum((u16_t *)&uip_buf[UIP_LLH_LEN], 20);
+}
+/*-----------------------------------------------------------------------------------*/
+u16_t
+uip_tcpchksum(void)
+{
+  u16_t hsum, sum;
+
+  
+  /* Compute the checksum of the TCP header. */
+  hsum = uip_chksum((u16_t *)&uip_buf[20 + UIP_LLH_LEN], 20);
+
+  /* Compute the checksum of the data in the TCP packet and add it to
+     the TCP header checksum. */
+  sum = uip_chksum((u16_t *)uip_appdata,
+		   (u16_t)(((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 40)));
+
+  if((sum += hsum) < hsum) {
+    ++sum;
+  }
+  
+  if((sum += BUF->srcipaddr[0]) < BUF->srcipaddr[0]) {
+    ++sum;
+  }
+  if((sum += BUF->srcipaddr[1]) < BUF->srcipaddr[1]) {
+    ++sum;
+  }
+  if((sum += BUF->destipaddr[0]) < BUF->destipaddr[0]) {
+    ++sum;
+  }
+  if((sum += BUF->destipaddr[1]) < BUF->destipaddr[1]) {
+    ++sum;
+  }
+  if((sum += (u16_t)htons((u16_t)IP_PROTO_TCP)) < (u16_t)htons((u16_t)IP_PROTO_TCP)) {
+    ++sum;
+  }
+
+  hsum = (u16_t)htons((((u16_t)(BUF->len[0]) << 8) + BUF->len[1]) - 20);
+  
+  if((sum += hsum) < hsum) {
+    ++sum;
+  }
+  
+  return sum;
+}
+/*-----------------------------------------------------------------------------------*/
diff --git a/board/broadcom/bcmbca/httpd/uip_arch.h b/board/broadcom/bcmbca/httpd/uip_arch.h
new file mode 100644
index 0000000000..947d84cf17
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/uip_arch.h
@@ -0,0 +1,130 @@
+/**
+ * \defgroup uiparch Architecture specific uIP functions
+ * @{
+ *
+ * The functions in the architecture specific module implement the IP
+ * check sum and 32-bit additions.
+ *
+ * The IP checksum calculation is the most computationally expensive
+ * operation in the TCP/IP stack and it therefore pays off to
+ * implement this in efficient assembler. The purpose of the uip-arch
+ * module is to let the checksum functions to be implemented in
+ * architecture specific assembler.
+ *
+ */
+
+/**
+ * \file
+ * Declarations of architecture specific functions.
+ * \author Adam Dunkels <adam@dunkels.com>
+ */
+
+/*
+ * Copyright (c) 2001, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arch.h,v 1.1.2.2 2003/10/06 15:10:22 adam Exp $
+ *
+ */
+
+#ifndef __UIP_ARCH_H__
+#define __UIP_ARCH_H__
+
+#include "uip.h"
+
+/**
+ * Carry out a 32-bit addition.
+ *
+ * Because not all architectures for which uIP is intended has native
+ * 32-bit arithmetic, uIP uses an external C function for doing the
+ * required 32-bit additions in the TCP protocol processing. This
+ * function should add the two arguments and place the result in the
+ * global variable uip_acc32.
+ *
+ * \note The 32-bit integer pointed to by the op32 parameter and the
+ * result in the uip_acc32 variable are in network byte order (big
+ * endian).
+ *
+ * \param op32 A pointer to a 4-byte array representing a 32-bit
+ * integer in network byte order (big endian).
+ *
+ * \param op16 A 16-bit integer in host byte order.
+ */
+void uip_add32(u8_t *op32, u16_t op16);
+
+/**
+ * Calculate the Internet checksum over a buffer.
+ *
+ * The Internet checksum is the one's complement of the one's
+ * complement sum of all 16-bit words in the buffer.
+ *
+ * See RFC1071.
+ *
+ * \note This function is not called in the current version of uIP,
+ * but future versions might make use of it.
+ *
+ * \param buf A pointer to the buffer over which the checksum is to be
+ * computed.
+ *
+ * \param len The length of the buffer over which the checksum is to
+ * be computed.
+ *
+ * \return The Internet checksum of the buffer.
+ */
+u16_t uip_chksum(u16_t *buf, u16_t len);
+
+/**
+ * Calculate the IP header checksum of the packet header in uip_buf.
+ *
+ * The IP header checksum is the Internet checksum of the 20 bytes of
+ * the IP header.
+ *
+ * \return The IP header checksum of the IP header in the uip_buf
+ * buffer.
+ */
+u16_t uip_ipchksum(void);
+
+/**
+ * Calculate the TCP checksum of the packet in uip_buf and uip_appdata.
+ *
+ * The TCP checksum is the Internet checksum of data contents of the
+ * TCP segment, and a pseudo-header as defined in RFC793.
+ *
+ * \note The uip_appdata pointer that points to the packet data may
+ * point anywhere in memory, so it is not possible to simply calculate
+ * the Internet checksum of the contents of the uip_buf buffer.
+ *
+ * \return The TCP checksum of the TCP segment in uip_buf and pointed
+ * to by uip_appdata.
+ */
+u16_t uip_tcpchksum(void);
+
+/** @} */
+
+#endif /* __UIP_ARCH_H__ */
diff --git a/board/broadcom/bcmbca/httpd/uip_arp.c b/board/broadcom/bcmbca/httpd/uip_arp.c
new file mode 100644
index 0000000000..9226b667e4
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/uip_arp.c
@@ -0,0 +1,393 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \defgroup uiparp uIP Address Resolution Protocol
+ * @{
+ * 
+ * The Address Resolution Protocol ARP is used for mapping between IP
+ * addresses and link level addresses such as the Ethernet MAC
+ * addresses. ARP uses broadcast queries to ask for the link level
+ * address of a known IP address and the host which is configured with
+ * the IP address for which the query was meant, will respond with its
+ * link level address.
+ *
+ * \note This ARP implementation only supports Ethernet.
+ */
+ 
+/**
+ * \file
+ * Implementation of the ARP Address Resolution Protocol.
+ * \author Adam Dunkels <adam@dunkels.com>
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.c,v 1.7.2.3 2003/10/06 22:42:30 adam Exp $
+ *
+ */
+
+
+#include "uip_arp.h"
+
+struct arp_header {
+  struct uip_eth_hdr ethhdr;
+  u16_t hwtype;
+  u16_t protocol;
+  u8_t hwlen;
+  u8_t protolen;
+  u16_t opcode;
+  struct uip_eth_addr shwaddr;
+  u16_t sipaddr[2];
+  struct uip_eth_addr dhwaddr;
+  u16_t dipaddr[2]; 
+};
+
+struct ethip_hdr {
+  struct uip_eth_hdr ethhdr;
+  /* IP header. */
+  u8_t vhl,
+    tos,          
+    len[2],       
+    ipid[2],        
+    ipoffset[2],  
+    ttl,          
+    proto;     
+  u16_t ipchksum;
+  u16_t srcipaddr[2], 
+    destipaddr[2];
+};
+
+#define ARP_REQUEST 1
+#define ARP_REPLY   2
+
+#define ARP_HWTYPE_ETH 1
+
+struct arp_entry {
+  u16_t ipaddr[2];
+  struct uip_eth_addr ethaddr;
+  u8_t time;
+};
+
+extern struct uip_eth_addr uip_ethadd;
+
+static struct arp_entry arp_table[UIP_ARPTAB_SIZE];
+static u16_t ipaddr[2];
+static u8_t i, c;
+
+static u8_t arptime;
+static u8_t tmpage;
+
+#define BUF   ((struct arp_header *)&uip_buf[0])
+#define IPBUF ((struct ethip_hdr *)&uip_buf[0])
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Initialize the ARP module.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_init(void)
+{
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    memset(arp_table[i].ipaddr, 0, 4);
+  }
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Periodic ARP processing function.
+ *
+ * This function performs periodic timer processing in the ARP module
+ * and should be called at regular intervals. The recommended interval
+ * is 10 seconds between the calls.
+ *
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_timer(void)
+{
+  struct arp_entry *tabptr;
+  
+  ++arptime;
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    tabptr = &arp_table[i];
+    if((tabptr->ipaddr[0] | tabptr->ipaddr[1]) != 0 &&
+       arptime - tabptr->time >= UIP_ARP_MAXAGE) {
+      memset(tabptr->ipaddr, 0, 4);
+    }
+  }
+
+}
+/*-----------------------------------------------------------------------------------*/
+static void
+uip_arp_update(u16_t *ipaddr, struct uip_eth_addr *ethaddr)
+{
+  register struct arp_entry *tabptr = 0;
+  /* Walk through the ARP mapping table and try to find an entry to
+     update. If none is found, the IP -> MAC address mapping is
+     inserted in the ARP table. */
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+
+    tabptr = &arp_table[i];
+    /* Only check those entries that are actually in use. */
+    if(tabptr->ipaddr[0] != 0 &&
+       tabptr->ipaddr[1] != 0) {
+
+      /* Check if the source IP address of the incoming packet matches
+         the IP address in this ARP table entry. */
+      if(ipaddr[0] == tabptr->ipaddr[0] &&
+	 ipaddr[1] == tabptr->ipaddr[1]) {
+	 
+	/* An old entry found, update this and return. */
+	memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);
+	tabptr->time = arptime;
+
+	return;
+      }
+    }
+  }
+
+  /* If we get here, no existing ARP table entry was found, so we
+     create one. */
+
+  /* First, we try to find an unused entry in the ARP table. */
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    tabptr = &arp_table[i];
+    if(tabptr->ipaddr[0] == 0 &&
+       tabptr->ipaddr[1] == 0) {
+      break;
+    }
+  }
+
+  /* If no unused entry is found, we try to find the oldest entry and
+     throw it away. */
+  if(i == UIP_ARPTAB_SIZE) {
+    tmpage = 0;
+    c = 0;
+    for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+      tabptr = &arp_table[i];
+      if(arptime - tabptr->time > tmpage) {
+	tmpage = arptime - tabptr->time;
+	c = i;
+      }
+    }
+    i = c;
+  }
+
+  /* Now, i is the ARP table entry which we will fill with the new
+     information. */
+  memcpy(tabptr->ipaddr, ipaddr, 4);
+  memcpy(tabptr->ethaddr.addr, ethaddr->addr, 6);
+  tabptr->time = arptime;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * ARP processing for incoming IP packets
+ *
+ * This function should be called by the device driver when an IP
+ * packet has been received. The function will check if the address is
+ * in the ARP cache, and if so the ARP cache entry will be
+ * refreshed. If no ARP cache entry was found, a new one is created.
+ * If IP address is not from local network it comes with MAC of default
+ * gatway we save both in ARP cache. 
+ *
+ * This function expects an IP packet with a prepended Ethernet header
+ * in the uip_buf[] buffer, and the length of the packet in the global
+ * variable uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_ipin(void)
+{
+  uip_len -= sizeof(struct uip_eth_hdr);
+  uip_arp_update(IPBUF->srcipaddr, &(IPBUF->ethhdr.src));
+  return;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * ARP processing for incoming ARP packets.
+ *
+ * This function should be called by the device driver when an ARP
+ * packet has been received. The function will act differently
+ * depending on the ARP packet type: if it is a reply for a request
+ * that we previously sent out, the ARP cache will be filled in with
+ * the values from the ARP reply. If the incoming ARP packet is an ARP
+ * request for our IP address, an ARP reply packet is created and put
+ * into the uip_buf[] buffer.
+ *
+ * When the function returns, the value of the global variable uip_len
+ * indicates whether the device driver should send out a packet or
+ * not. If uip_len is zero, no packet should be sent. If uip_len is
+ * non-zero, it contains the length of the outbound packet that is
+ * present in the uip_buf[] buffer.
+ *
+ * This function expects an ARP packet with a prepended Ethernet
+ * header in the uip_buf[] buffer, and the length of the packet in the
+ * global variable uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_arpin(void)
+{
+
+  if(uip_len < sizeof(struct arp_header)) {
+    uip_len = 0;
+    return;
+  }
+
+  uip_len = 0;
+
+  switch(BUF->opcode) {
+  case HTONS(ARP_REQUEST):
+    /* ARP request. If it asked for our address, we send out a
+       reply. */
+    if(BUF->dipaddr[0] == uip_hostaddr[0] &&
+       BUF->dipaddr[1] == uip_hostaddr[1]) {
+      /* The reply opcode is 2. */
+      BUF->opcode = HTONS(2);
+
+      memcpy(BUF->dhwaddr.addr, BUF->shwaddr.addr, 6);
+      memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);
+      memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+      memcpy(BUF->ethhdr.dest.addr, BUF->dhwaddr.addr, 6);
+      
+      BUF->dipaddr[0] = BUF->sipaddr[0];
+      BUF->dipaddr[1] = BUF->sipaddr[1];
+      BUF->sipaddr[0] = uip_hostaddr[0];
+      BUF->sipaddr[1] = uip_hostaddr[1];
+
+      BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP);      
+      uip_len = sizeof(struct arp_header);
+    }      
+    break;
+  case HTONS(ARP_REPLY):
+    /* ARP reply. We insert or update the ARP table if it was meant
+       for us. */
+    if(BUF->dipaddr[0] == uip_hostaddr[0] &&
+       BUF->dipaddr[1] == uip_hostaddr[1]) {
+
+      uip_arp_update(BUF->sipaddr, &BUF->shwaddr);
+    }
+    break;
+  }
+
+  return;
+}
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Prepend Ethernet header to an outbound IP packet and see if we need
+ * to send out an ARP request.
+ *
+ * This function should be called before sending out an IP packet. The
+ * function checks the destination IP address of the IP packet to see
+ * what Ethernet MAC address that should be used as a destination MAC
+ * address on the Ethernet.
+ *
+ * If the destination IP address is in the local network (determined
+ * by logical ANDing of netmask and our IP address), the function
+ * checks the ARP cache to see if an entry for the destination IP
+ * address is found. If so, an Ethernet header is prepended and the
+ * function returns. If no ARP cache entry is found for the
+ * destination IP address, the packet in the uip_buf[] is replaced by
+ * an ARP request packet for the IP address. The IP packet is dropped
+ * and it is assumed that they higher level protocols (e.g., TCP)
+ * eventually will retransmit the dropped packet.
+ *
+ * If the destination IP address is not on the local network, the IP
+ * address of the default router is used instead.
+ *
+ * When the function returns, a packet is present in the uip_buf[]
+ * buffer, and the length of the packet is in the global variable
+ * uip_len.
+ */
+/*-----------------------------------------------------------------------------------*/
+void
+uip_arp_out(void)
+{
+  struct arp_entry *tabptr = 0;
+
+  /* Find the destination IP address in the ARP table and construct
+     the Ethernet header. If the destination IP address isn't on the
+     local network host IP address and default gatway MAC already learned
+     from previous incoming TCP/IP packet.
+  */   
+
+  ipaddr[0] = IPBUF->destipaddr[0];
+  ipaddr[1] = IPBUF->destipaddr[1];
+      
+  for(i = 0; i < UIP_ARPTAB_SIZE; ++i) {
+    tabptr = &arp_table[i];
+    if(ipaddr[0] == tabptr->ipaddr[0] &&
+       ipaddr[1] == tabptr->ipaddr[1])
+      break;
+  }
+
+  if(i == UIP_ARPTAB_SIZE) {
+    /* The destination address was not in our ARP table, so we
+       overwrite the IP packet with an ARP request. */
+
+    memset(BUF->ethhdr.dest.addr, 0xff, 6);
+    memset(BUF->dhwaddr.addr, 0x00, 6);
+    memcpy(BUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+    memcpy(BUF->shwaddr.addr, uip_ethaddr.addr, 6);
+    
+    BUF->dipaddr[0] = ipaddr[0];
+    BUF->dipaddr[1] = ipaddr[1];
+    BUF->sipaddr[0] = uip_hostaddr[0];
+    BUF->sipaddr[1] = uip_hostaddr[1];
+    BUF->opcode = HTONS(ARP_REQUEST); /* ARP request. */
+    BUF->hwtype = HTONS(ARP_HWTYPE_ETH);
+    BUF->protocol = HTONS(UIP_ETHTYPE_IP);
+    BUF->hwlen = 6;
+    BUF->protolen = 4;
+    BUF->ethhdr.type = HTONS(UIP_ETHTYPE_ARP);
+
+    uip_appdata = &uip_buf[40 + UIP_LLH_LEN];
+    
+    uip_len = sizeof(struct arp_header);
+    return;
+  }
+
+  /* Build an ethernet header. */
+  memcpy(IPBUF->ethhdr.dest.addr, tabptr->ethaddr.addr, 6);
+  memcpy(IPBUF->ethhdr.src.addr, uip_ethaddr.addr, 6);
+  
+  IPBUF->ethhdr.type = HTONS(UIP_ETHTYPE_IP);
+  
+  uip_len += sizeof(struct uip_eth_hdr);
+}
+/*-----------------------------------------------------------------------------------*/
+
+/** @} */
+/** @} */
diff --git a/board/broadcom/bcmbca/httpd/uip_arp.h b/board/broadcom/bcmbca/httpd/uip_arp.h
new file mode 100644
index 0000000000..0371cd6731
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/uip_arp.h
@@ -0,0 +1,201 @@
+/**
+ * \addtogroup uip
+ * @{
+ */
+
+/**
+ * \addtogroup uiparp 
+ * @{
+ */
+ 
+/**
+ * \file
+ * Macros and definitions for the ARP module.
+ * \author Adam Dunkels <adam@dunkels.com>
+ */
+  
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uip_arp.h,v 1.3.2.2 2003/10/06 15:10:22 adam Exp $
+ *
+ */
+
+#ifndef __UIP_ARP_H__
+#define __UIP_ARP_H__
+
+#include "uip.h"
+
+
+/**
+ * Representation of a 48-bit Ethernet address.
+ */
+struct uip_eth_addr {
+  u8_t addr[6];
+};
+
+extern struct uip_eth_addr uip_ethaddr;
+
+/**
+ * The Ethernet header. 
+ */
+struct uip_eth_hdr {
+  struct uip_eth_addr dest;
+  struct uip_eth_addr src;
+  u16_t type;
+};
+
+#define UIP_ETHTYPE_ARP 0x0806
+#define UIP_ETHTYPE_IP  0x0800
+#define UIP_ETHTYPE_IP6 0x86dd 
+
+
+/* The uip_arp_init() function must be called before any of the other
+   ARP functions. */
+void uip_arp_init(void);
+
+/* The uip_arp_ipin() function should be called whenever an IP packet
+   arrives from the Ethernet. This function refreshes the ARP table or
+   inserts a new mapping if none exists. The function assumes that an
+   IP packet with an Ethernet header is present in the uip_buf buffer
+   and that the length of the packet is in the uip_len variable. */
+void uip_arp_ipin(void);
+
+/* The uip_arp_arpin() should be called when an ARP packet is received
+   by the Ethernet driver. This function also assumes that the
+   Ethernet frame is present in the uip_buf buffer. When the
+   uip_arp_arpin() function returns, the contents of the uip_buf
+   buffer should be sent out on the Ethernet if the uip_len variable
+   is > 0. */
+void uip_arp_arpin(void);
+
+/* The uip_arp_out() function should be called when an IP packet
+   should be sent out on the Ethernet. This function creates an
+   Ethernet header before the IP header in the uip_buf buffer. The
+   Ethernet header will have the correct Ethernet MAC destination
+   address filled in if an ARP table entry for the destination IP
+   address (or the IP address of the default router) is present. If no
+   such table entry is found, the IP packet is overwritten with an ARP
+   request and we rely on TCP to retransmit the packet that was
+   overwritten. In any case, the uip_len variable holds the length of
+   the Ethernet frame that should be transmitted. */
+void uip_arp_out(void);
+
+/* The uip_arp_timer() function should be called every ten seconds. It
+   is responsible for flushing old entries in the ARP table. */
+void uip_arp_timer(void);
+
+/** @} */
+
+/**
+ * \addtogroup uipconffunc
+ * @{
+ */
+
+/**
+ * Set the default router's IP address.
+ *
+ * \param addr A pointer to a 4-byte array containing the IP address
+ * of the default router.
+ *
+ * \hideinitializer
+ */
+#define uip_setdraddr(addr) do { uip_arp_draddr[0] = addr[0]; \
+                                 uip_arp_draddr[1] = addr[1]; } while(0)
+
+/**
+ * Set the netmask.
+ *
+ * \param addr A pointer to a 4-byte array containing the IP address
+ * of the netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_setnetmask(addr) do { uip_arp_netmask[0] = addr[0]; \
+                                  uip_arp_netmask[1] = addr[1]; } while(0)
+
+
+/**
+ * Get the default router's IP address.
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the IP address of the default router.
+ *
+ * \hideinitializer
+ */
+#define uip_getdraddr(addr) do { addr[0] = uip_arp_draddr[0]; \
+                                 addr[1] = uip_arp_draddr[1]; } while(0)
+
+/**
+ * Get the netmask.
+ *
+ * \param addr A pointer to a 4-byte array that will be filled in with
+ * the value of the netmask.
+ *
+ * \hideinitializer
+ */
+#define uip_getnetmask(addr) do { addr[0] = uip_arp_netmask[0]; \
+                                  addr[1] = uip_arp_netmask[1]; } while(0)
+
+
+/**
+ * Specifiy the Ethernet MAC address.
+ *
+ * The ARP code needs to know the MAC address of the Ethernet card in
+ * order to be able to respond to ARP queries and to generate working
+ * Ethernet headers.
+ *
+ * \note This macro only specifies the Ethernet MAC address to the ARP
+ * code. It cannot be used to change the MAC address of the Ethernet
+ * card.
+ *
+ * \param eaddr A pointer to a struct uip_eth_addr containing the
+ * Ethernet MAC address of the Ethernet card.
+ *
+ * \hideinitializer
+ */
+#define uip_setethaddr(eaddr) do {uip_ethaddr.addr[0] = eaddr.addr[0]; \
+                              uip_ethaddr.addr[1] = eaddr.addr[1];\
+                              uip_ethaddr.addr[2] = eaddr.addr[2];\
+                              uip_ethaddr.addr[3] = eaddr.addr[3];\
+                              uip_ethaddr.addr[4] = eaddr.addr[4];\
+                              uip_ethaddr.addr[5] = eaddr.addr[5];} while(0)
+
+/** @} */
+
+/**
+ * \internal Internal variables that are set using the macros
+ * uip_setdraddr and uip_setnetmask.
+ */
+extern u16_t uip_arp_draddr[2], uip_arp_netmask[2];
+#endif /* __UIP_ARP_H__ */
+
+
diff --git a/board/broadcom/bcmbca/httpd/uipopt.h b/board/broadcom/bcmbca/httpd/uipopt.h
new file mode 100644
index 0000000000..57984cbbec
--- /dev/null
+++ b/board/broadcom/bcmbca/httpd/uipopt.h
@@ -0,0 +1,559 @@
+/**
+ * \defgroup uipopt Configuration options for uIP
+ * @{
+ *
+ * uIP is configured using the per-project configuration file
+ * "uipopt.h". This file contains all compile-time options for uIP and
+ * should be tweaked to match each specific project. The uIP
+ * distribution contains a documented example "uipopt.h" that can be
+ * copied and modified for each project.
+ */
+
+/**
+ * \file
+ * Configuration options for uIP.
+ * \author Adam Dunkels <adam@dunkels.com>
+ *
+ * This file is used for tweaking various configuration options for
+ * uIP. You should make a copy of this file into one of your project's
+ * directories instead of editing this example "uipopt.h" file that
+ * comes with the uIP distribution.
+ */
+
+/*
+ * Copyright (c) 2001-2003, Adam Dunkels.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+ *
+ * This file is part of the uIP TCP/IP stack.
+ *
+ * $Id: uipopt.h,v 1.16.2.5 2003/10/07 13:22:51 adam Exp $
+ *
+ */
+
+#ifndef __UIPOPT_H__
+#define __UIPOPT_H__
+
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipopttypedef uIP type definitions
+ * @{
+ */
+
+/**
+ * The 8-bit unsigned data type.
+ *
+ * This may have to be tweaked for your particular compiler. "unsigned
+ * char" works for most compilers.
+ */
+typedef unsigned char u8_t;
+
+/**
+ * The 16-bit unsigned data type.
+ *
+ * This may have to be tweaked for your particular compiler. "unsigned
+ * short" works for most compilers.
+ */
+typedef unsigned short u16_t;
+
+/**
+ * The statistics data type.
+ *
+ * This datatype determines how high the statistics counters are able
+ * to count.
+ */
+typedef unsigned short uip_stats_t;
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptstaticconf Static configuration options
+ * @{
+ *
+ * These configuration options can be used for setting the IP address
+ * settings statically, but only if UIP_FIXEDADDR is set to 1. The
+ * configuration options for a specific node includes IP address,
+ * netmask and default router as well as the Ethernet address. The
+ * netmask, default router and Ethernet address are appliciable only
+ * if uIP should be run over Ethernet.
+ *
+ * All of these should be changed to suit your project.
+*/
+
+/**
+ * Determines if uIP should use a fixed IP address or not.
+ *
+ * If uIP should use a fixed IP address, the settings are set in the
+ * uipopt.h file. If not, the macros uip_sethostaddr(),
+ * uip_setdraddr() and uip_setnetmask() should be used instead.
+ *
+ * \hideinitializer
+ */
+#define UIP_FIXEDADDR    0
+
+/**
+ * Ping IP address asignment.
+ *
+ * uIP uses a "ping" packets for setting its own IP address if this
+ * option is set. If so, uIP will start with an empty IP address and
+ * the destination IP address of the first incoming "ping" (ICMP echo)
+ * packet will be used for setting the hosts IP address.
+ *
+ * \note This works only if UIP_FIXEDADDR is 0.
+ *
+ * \hideinitializer
+ */
+#define UIP_PINGADDRCONF 0
+
+#define UIP_IPADDR0     192 /**< The first octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR1     168 /**< The second octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR2     0   /**< The third octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_IPADDR3     250   /**< The fourth octet of the IP address of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+#define UIP_NETMASK0    255 /**< The first octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK1    255 /**< The second octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK2    255 /**< The third octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_NETMASK3    0   /**< The fourth octet of the netmask of
+			       this uIP node, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+#define UIP_DRIPADDR0   192 /**< The first octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR1   168 /**< The second octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR2   0   /**< The third octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+#define UIP_DRIPADDR3   1   /**< The fourth octet of the IP address of
+			       the default router, if UIP_FIXEDADDR is
+			       1. \hideinitializer */
+
+/**
+ * Specifies if the uIP ARP module should be compiled with a fixed
+ * Ethernet MAC address or not.
+ *
+ * If this configuration option is 0, the macro uip_setethaddr() can
+ * be used to specify the Ethernet address at run-time.
+ *
+ * \hideinitializer
+ */
+#define UIP_FIXEDETHADDR 0
+
+#define UIP_ETHADDR0    0x00  /**< The first octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR1    0xbd  /**< The second octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR2    0x3b  /**< The third octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR3    0x33  /**< The fourth octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR4    0x05  /**< The fifth octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+#define UIP_ETHADDR5    0x71  /**< The sixth octet of the Ethernet
+				 address if UIP_FIXEDETHADDR is
+				 1. \hideinitializer */
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptip IP configuration options
+ * @{
+ *
+ */
+/**
+ * The IP TTL (time to live) of IP packets sent by uIP.
+ *
+ * This should normally not be changed.
+ */
+#define UIP_TTL         255
+
+/**
+ * Turn on support for IP packet reassembly.
+ *
+ * uIP supports reassembly of fragmented IP packets. This features
+ * requires an additonal amount of RAM to hold the reassembly buffer
+ * and the reassembly code size is approximately 700 bytes.  The
+ * reassembly buffer is of the same size as the uip_buf buffer
+ * (configured by UIP_BUFSIZE).
+ *
+ * \note IP packet reassembly is not heavily tested.
+ *
+ * \hideinitializer
+ */
+#define UIP_REASSEMBLY 0
+
+/**
+ * The maximum time an IP fragment should wait in the reassembly
+ * buffer before it is dropped.
+ *
+ */
+#define UIP_REASS_MAXAGE 40
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptudp UDP configuration options
+ * @{
+ *
+ * \note The UDP support in uIP is still not entirely complete; there
+ * is no support for sending or receiving broadcast or multicast
+ * packets, but it works well enough to support a number of vital
+ * applications such as DNS queries, though
+ */
+
+/**
+ * Toggles wether UDP support should be compiled in or not.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP           0
+
+/**
+ * Toggles if UDP checksums should be used or not.
+ *
+ * \note Support for UDP checksums is currently not included in uIP,
+ * so this option has no function.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP_CHECKSUMS 0
+
+/**
+ * The maximum amount of concurrent UDP connections.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP_CONNS    10
+
+/**
+ * The name of the function that should be called when UDP datagrams arrive.
+ *
+ * \hideinitializer
+ */
+#define UIP_UDP_APPCALL  udp_appcall
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipopttcp TCP configuration options
+ * @{
+ */
+
+/**
+ * Determines if support for opening connections from uIP should be
+ * compiled in.
+ *
+ * If the applications that are running on top of uIP for this project
+ * do not need to open outgoing TCP connections, this configration
+ * option can be turned off to reduce the code size of uIP.
+ *
+ * \hideinitializer
+ */
+#define UIP_ACTIVE_OPEN 0
+
+/**
+ * The maximum number of simultaneously open TCP connections.
+ *
+ * Since the TCP connections are statically allocated, turning this
+ * configuration knob down results in less RAM used. Each TCP
+ * connection requires approximatly 30 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#define UIP_CONNS       2
+
+/**
+ * The maximum number of simultaneously listening TCP ports.
+ *
+ * Each listening TCP port requires 2 bytes of memory.
+ *
+ * \hideinitializer
+ */
+#define UIP_LISTENPORTS 1
+
+/**
+ * The size of the advertised receiver's window.
+ *
+ * Should be set low (i.e., to the size of the uip_buf buffer) is the
+ * application is slow to process incoming data, or high (32768 bytes)
+ * if the application processes data quickly.
+ *
+ * \hideinitializer
+ */
+//#define UIP_RECEIVE_WINDOW   32768
+#define UIP_RECEIVE_WINDOW   3000
+
+/**
+ * Determines if support for TCP urgent data notification should be
+ * compiled in.
+ *
+ * Urgent data (out-of-band data) is a rarely used TCP feature that
+ * very seldom would be required.
+ *
+ * \hideinitializer
+ */
+//#define UIP_URGDATA      0
+#define UIP_URGDATA      1
+
+/**
+ * The initial retransmission timeout counted in timer pulses.
+ *
+ * This should not be changed.
+ */
+#define UIP_RTO         3
+
+/**
+ * The maximum number of times a segment should be retransmitted
+ * before the connection should be aborted.
+ *
+ * This should not be changed.
+ */
+#define UIP_MAXRTX      8
+
+/**
+ * The maximum number of times a SYN segment should be retransmitted
+ * before a connection request should be deemed to have been
+ * unsuccessful.
+ *
+ * This should not need to be changed.
+ */
+#define UIP_MAXSYNRTX      3
+
+/**
+ * The TCP maximum segment size.
+ *
+ * This is should not be to set to more than UIP_BUFSIZE - UIP_LLH_LEN - 40.
+ */
+#define UIP_TCP_MSS     (UIP_BUFSIZE - UIP_LLH_LEN - 40)
+
+/**
+ * How long a connection should stay in the TIME_WAIT state.
+ *
+ * This configiration option has no real implication, and it should be
+ * left untouched.
+ */ 
+#define UIP_TIME_WAIT_TIMEOUT 120
+
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptarp ARP configuration options
+ * @{
+ */
+
+/**
+ * The size of the ARP table.
+ *
+ * This option should be set to a larger value if this uIP node will
+ * have many connections from the local network.
+ *
+ * \hideinitializer
+ */
+#define UIP_ARPTAB_SIZE 2
+
+/**
+ * The maxium age of ARP table entries measured in 10ths of seconds.
+ *
+ * An UIP_ARP_MAXAGE of 120 corresponds to 20 minutes (BSD
+ * default).
+ */
+#define UIP_ARP_MAXAGE 120
+
+/** @} */
+
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptgeneral General configuration options
+ * @{
+ */
+
+/**
+ * The size of the uIP packet buffer.
+ *
+ * The uIP packet buffer should not be smaller than 60 bytes, and does
+ * not need to be larger than 1500 bytes. Lower size results in lower
+ * TCP throughput, larger size results in higher TCP throughput.
+ *
+ * \hideinitializer
+ */
+#define UIP_BUFSIZE     1500
+
+
+/**
+ * Determines if statistics support should be compiled in.
+ *
+ * The statistics is useful for debugging and to show the user.
+ *
+ * \hideinitializer
+ */
+#define UIP_STATISTICS  0
+
+/**
+ * Determines if logging of certain events should be compiled in.
+ *
+ * This is useful mostly for debugging. The function uip_log()
+ * must be implemented to suit the architecture of the project, if
+ * logging is turned on.
+ *
+ * \hideinitializer
+ */
+#define UIP_LOGGING     1
+
+/**
+ * Print out a uIP log message.
+ *
+ * This function must be implemented by the module that uses uIP, and
+ * is called by uIP whenever a log message is generated.
+ */
+void uip_log(char *msg);
+
+/**
+ * The link level header length.
+ *
+ * This is the offset into the uip_buf where the IP header can be
+ * found. For Ethernet, this should be set to 14. For SLIP, this
+ * should be set to 0.
+ *
+ * \hideinitializer
+ */
+#define UIP_LLH_LEN     14
+
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+/**
+ * \defgroup uipoptcpu CPU architecture configuration
+ * @{
+ *
+ * The CPU architecture configuration is where the endianess of the
+ * CPU on which uIP is to be run is specified. Most CPUs today are
+ * little endian, and the most notable exception are the Motorolas
+ * which are big endian. The BYTE_ORDER macro should be changed to
+ * reflect the CPU architecture on which uIP is to be run.
+ */
+#ifndef LITTLE_ENDIAN
+#define LITTLE_ENDIAN  3412
+#endif /* LITTLE_ENDIAN */
+#ifndef BIG_ENDIAN
+#define BIG_ENDIAN     1234
+#endif /* BIGE_ENDIAN */
+
+/**
+ * The byte order of the CPU architecture on which uIP is to be run.
+ *
+ * This option can be either BIG_ENDIAN (Motorola byte order) or
+ * LITTLE_ENDIAN (Intel byte order).
+ *
+ * \hideinitializer
+ */
+/*#ifndef BYTE_ORDER*/
+#define BYTE_ORDER     LITTLE_ENDIAN
+/*#endif*/ /* BYTE_ORDER */
+
+/** @} */
+/*------------------------------------------------------------------------------*/
+
+/**
+ * \defgroup uipoptapp Appication specific configurations
+ * @{
+ *
+ * An uIP application is implemented using a single application
+ * function that is called by uIP whenever a TCP/IP event occurs. The
+ * name of this function must be registered with uIP at compile time
+ * using the UIP_APPCALL definition.
+ *
+ * uIP applications can store the application state within the
+ * uip_conn structure by specifying the size of the application
+ * structure with the UIP_APPSTATE_SIZE macro.
+ *
+ * The file containing the definitions must be included in the
+ * uipopt.h file.
+ *
+ * The following example illustrates how this can look.
+ \code
+
+void httpd_appcall(void);
+#define UIP_APPCALL     httpd_appcall
+
+struct httpd_state {
+  u8_t state; 
+  u16_t count;
+  char *dataptr;
+  char *script;
+};
+#define UIP_APPSTATE_SIZE (sizeof(struct httpd_state))
+ \endcode
+ */
+
+/**
+ * \var #define UIP_APPCALL
+ *
+ * The name of the application function that uIP should call in
+ * response to TCP/IP events.
+ *
+ */
+
+/**
+ * \var #define UIP_APPSTATE_SIZE
+ *
+ * The size of the application state that is to be stored in the
+ * uip_conn structure.
+ */
+/** @} */
+
+/* Include the header file for the application program that should be
+   used. If you don't use the example web server, you should change
+   this. */
+#include "httpd.h"
+
+
+#endif /* __UIPOPT_H__ */
diff --git a/board/broadcom/bcmbca/mini-gmp/Makefile b/board/broadcom/bcmbca/mini-gmp/Makefile
new file mode 100644
index 0000000000..d3c61139bd
--- /dev/null
+++ b/board/broadcom/bcmbca/mini-gmp/Makefile
@@ -0,0 +1,2 @@
+ccflags-y += -DMINI_GMP_DONT_USE_FLOAT_H
+obj-y += mini-gmp.o mini-mpq.o
diff --git a/board/broadcom/bcmbca/mini-gmp/mini-gmp.c b/board/broadcom/bcmbca/mini-gmp/mini-gmp.c
new file mode 100644
index 0000000000..2755705d62
--- /dev/null
+++ b/board/broadcom/bcmbca/mini-gmp/mini-gmp.c
@@ -0,0 +1,4597 @@
+/* mini-gmp, a minimalistic implementation of a GNU GMP subset.
+
+   Contributed to the GNU project by Niels Möller
+
+Copyright 1991-1997, 1999-2019 Free Software Foundation, Inc.
+
+This file is part of the GNU MP Library.
+
+The GNU MP Library is free software; you can redistribute it and/or modify
+it under the terms of either:
+
+  * the GNU Lesser General Public License as published by the Free
+    Software Foundation; either version 3 of the License, or (at your
+    option) any later version.
+
+or
+
+  * the GNU General Public License as published by the Free Software
+    Foundation; either version 2 of the License, or (at your option) any
+    later version.
+
+or both in parallel, as here.
+
+The GNU MP Library is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received copies of the GNU General Public License and the
+GNU Lesser General Public License along with the GNU MP Library.  If not,
+see https://www.gnu.org/licenses/.  */
+
+/* NOTE: All functions in this file which are not declared in
+   mini-gmp.h are internal, and are not intended to be compatible
+   neither with GMP nor with future versions of mini-gmp. */
+
+/* Much of the material copied from GMP files, including: gmp-impl.h,
+   longlong.h, mpn/generic/add_n.c, mpn/generic/addmul_1.c,
+   mpn/generic/lshift.c, mpn/generic/mul_1.c,
+   mpn/generic/mul_basecase.c, mpn/generic/rshift.c,
+   mpn/generic/sbpi1_div_qr.c, mpn/generic/sub_n.c,
+   mpn/generic/submul_1.c. */
+#if defined (CONFIG_ARM64) || defined (CONFIG_ARM) 
+#include <common.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <linux/errno.h>
+#include <asm/types.h>
+#include <asm/unaligned.h>
+#include <malloc.h>
+#define CHAR_BIT	8
+extern void bcm_sec_abort(void);
+#define abort	bcm_sec_abort
+
+#if defined (CONFIG_ARM64)
+
+typedef unsigned long long addr_t;
+#else 
+typedef unsigned long addr_t;
+#endif
+
+#else
+#include <assert.h>
+#include <ctype.h>
+#include <limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#endif
+
+#include "mini-gmp.h"
+
+#if !defined(MINI_GMP_DONT_USE_FLOAT_H)
+#include <float.h>
+#endif
+
+
+/* Macros */
+#define GMP_LIMB_BITS (sizeof(mp_limb_t) * CHAR_BIT)
+
+#define GMP_LIMB_MAX ((mp_limb_t) ~ (mp_limb_t) 0)
+#define GMP_LIMB_HIGHBIT ((mp_limb_t) 1 << (GMP_LIMB_BITS - 1))
+
+#define GMP_HLIMB_BIT ((mp_limb_t) 1 << (GMP_LIMB_BITS / 2))
+#define GMP_LLIMB_MASK (GMP_HLIMB_BIT - 1)
+
+#define GMP_ULONG_BITS (sizeof(unsigned long) * CHAR_BIT)
+#define GMP_ULONG_HIGHBIT ((unsigned long) 1 << (GMP_ULONG_BITS - 1))
+
+#define GMP_ABS(x) ((x) >= 0 ? (x) : -(x))
+#define GMP_NEG_CAST(T,x) (-((T)((x) + 1) - 1))
+
+#define GMP_MIN(a, b) ((a) < (b) ? (a) : (b))
+#define GMP_MAX(a, b) ((a) > (b) ? (a) : (b))
+
+#define GMP_CMP(a,b) (((a) > (b)) - ((a) < (b)))
+
+#if defined(DBL_MANT_DIG) && FLT_RADIX == 2
+#define GMP_DBL_MANT_BITS DBL_MANT_DIG
+#else
+#define GMP_DBL_MANT_BITS (53)
+#endif
+
+/* Return non-zero if xp,xsize and yp,ysize overlap.
+   If xp+xsize<=yp there's no overlap, or if yp+ysize<=xp there's no
+   overlap.  If both these are false, there's an overlap. */
+#define GMP_MPN_OVERLAP_P(xp, xsize, yp, ysize)				\
+  ((xp) + (xsize) > (yp) && (yp) + (ysize) > (xp))
+
+#define gmp_assert_nocarry(x) do { \
+    mp_limb_t __cy = (x);	   \
+    assert (__cy == 0);		   \
+  } while (0)
+
+#define gmp_clz(count, x) do {						\
+    mp_limb_t __clz_x = (x);						\
+    unsigned __clz_c = 0;						\
+    int LOCAL_SHIFT_BITS = 8;						\
+    if (GMP_LIMB_BITS > LOCAL_SHIFT_BITS)				\
+      for (;								\
+	   (__clz_x & ((mp_limb_t) 0xff << (GMP_LIMB_BITS - 8))) == 0;	\
+	   __clz_c += 8)						\
+	{ __clz_x <<= LOCAL_SHIFT_BITS;	}				\
+    for (; (__clz_x & GMP_LIMB_HIGHBIT) == 0; __clz_c++)		\
+      __clz_x <<= 1;							\
+    (count) = __clz_c;							\
+  } while (0)
+
+#define gmp_ctz(count, x) do {						\
+    mp_limb_t __ctz_x = (x);						\
+    unsigned __ctz_c = 0;						\
+    gmp_clz (__ctz_c, __ctz_x & - __ctz_x);				\
+    (count) = GMP_LIMB_BITS - 1 - __ctz_c;				\
+  } while (0)
+
+#define gmp_add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    mp_limb_t __x;							\
+    __x = (al) + (bl);							\
+    (sh) = (ah) + (bh) + (__x < (al));					\
+    (sl) = __x;								\
+  } while (0)
+
+#define gmp_sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    mp_limb_t __x;							\
+    __x = (al) - (bl);							\
+    (sh) = (ah) - (bh) - ((al) < (bl));					\
+    (sl) = __x;								\
+  } while (0)
+
+#define gmp_umul_ppmm(w1, w0, u, v)					\
+  do {									\
+    int LOCAL_GMP_LIMB_BITS = GMP_LIMB_BITS;				\
+    if (sizeof(unsigned int) * CHAR_BIT >= 2 * GMP_LIMB_BITS)		\
+      {									\
+	unsigned int __ww = (unsigned int) (u) * (v);			\
+	w0 = (mp_limb_t) __ww;						\
+	w1 = (mp_limb_t) (__ww >> LOCAL_GMP_LIMB_BITS);			\
+      }									\
+    else if (GMP_ULONG_BITS >= 2 * GMP_LIMB_BITS)			\
+      {									\
+	unsigned long int __ww = (unsigned long int) (u) * (v);		\
+	w0 = (mp_limb_t) __ww;						\
+	w1 = (mp_limb_t) (__ww >> LOCAL_GMP_LIMB_BITS);			\
+      }									\
+    else {								\
+      mp_limb_t __x0, __x1, __x2, __x3;					\
+      unsigned __ul, __vl, __uh, __vh;					\
+      mp_limb_t __u = (u), __v = (v);					\
+									\
+      __ul = __u & GMP_LLIMB_MASK;					\
+      __uh = __u >> (GMP_LIMB_BITS / 2);				\
+      __vl = __v & GMP_LLIMB_MASK;					\
+      __vh = __v >> (GMP_LIMB_BITS / 2);				\
+									\
+      __x0 = (mp_limb_t) __ul * __vl;					\
+      __x1 = (mp_limb_t) __ul * __vh;					\
+      __x2 = (mp_limb_t) __uh * __vl;					\
+      __x3 = (mp_limb_t) __uh * __vh;					\
+									\
+      __x1 += __x0 >> (GMP_LIMB_BITS / 2);/* this can't give carry */	\
+      __x1 += __x2;		/* but this indeed can */		\
+      if (__x1 < __x2)		/* did we get it? */			\
+	__x3 += GMP_HLIMB_BIT;	/* yes, add it in the proper pos. */	\
+									\
+      (w1) = __x3 + (__x1 >> (GMP_LIMB_BITS / 2));			\
+      (w0) = (__x1 << (GMP_LIMB_BITS / 2)) + (__x0 & GMP_LLIMB_MASK);	\
+    }									\
+  } while (0)
+
+#define gmp_udiv_qrnnd_preinv(q, r, nh, nl, d, di)			\
+  do {									\
+    mp_limb_t _qh, _ql, _r, _mask;					\
+    gmp_umul_ppmm (_qh, _ql, (nh), (di));				\
+    gmp_add_ssaaaa (_qh, _ql, _qh, _ql, (nh) + 1, (nl));		\
+    _r = (nl) - _qh * (d);						\
+    _mask = -(mp_limb_t) (_r > _ql); /* both > and >= are OK */		\
+    _qh += _mask;							\
+    _r += _mask & (d);							\
+    if (_r >= (d))							\
+      {									\
+	_r -= (d);							\
+	_qh++;								\
+      }									\
+									\
+    (r) = _r;								\
+    (q) = _qh;								\
+  } while (0)
+
+#define gmp_udiv_qr_3by2(q, r1, r0, n2, n1, n0, d1, d0, dinv)		\
+  do {									\
+    mp_limb_t _q0, _t1, _t0, _mask;					\
+    gmp_umul_ppmm ((q), _q0, (n2), (dinv));				\
+    gmp_add_ssaaaa ((q), _q0, (q), _q0, (n2), (n1));			\
+									\
+    /* Compute the two most significant limbs of n - q'd */		\
+    (r1) = (n1) - (d1) * (q);						\
+    gmp_sub_ddmmss ((r1), (r0), (r1), (n0), (d1), (d0));		\
+    gmp_umul_ppmm (_t1, _t0, (d0), (q));				\
+    gmp_sub_ddmmss ((r1), (r0), (r1), (r0), _t1, _t0);			\
+    (q)++;								\
+									\
+    /* Conditionally adjust q and the remainders */			\
+    _mask = - (mp_limb_t) ((r1) >= _q0);				\
+    (q) += _mask;							\
+    gmp_add_ssaaaa ((r1), (r0), (r1), (r0), _mask & (d1), _mask & (d0)); \
+    if ((r1) >= (d1))							\
+      {									\
+	if ((r1) > (d1) || (r0) >= (d0))				\
+	  {								\
+	    (q)++;							\
+	    gmp_sub_ddmmss ((r1), (r0), (r1), (r0), (d1), (d0));	\
+	  }								\
+      }									\
+  } while (0)
+
+/* Swap macros. */
+#define MP_LIMB_T_SWAP(x, y)						\
+  do {									\
+    mp_limb_t __mp_limb_t_swap__tmp = (x);				\
+    (x) = (y);								\
+    (y) = __mp_limb_t_swap__tmp;					\
+  } while (0)
+#define MP_SIZE_T_SWAP(x, y)						\
+  do {									\
+    mp_size_t __mp_size_t_swap__tmp = (x);				\
+    (x) = (y);								\
+    (y) = __mp_size_t_swap__tmp;					\
+  } while (0)
+#define MP_BITCNT_T_SWAP(x,y)			\
+  do {						\
+    mp_bitcnt_t __mp_bitcnt_t_swap__tmp = (x);	\
+    (x) = (y);					\
+    (y) = __mp_bitcnt_t_swap__tmp;		\
+  } while (0)
+#define MP_PTR_SWAP(x, y)						\
+  do {									\
+    mp_ptr __mp_ptr_swap__tmp = (x);					\
+    (x) = (y);								\
+    (y) = __mp_ptr_swap__tmp;						\
+  } while (0)
+#define MP_SRCPTR_SWAP(x, y)						\
+  do {									\
+    mp_srcptr __mp_srcptr_swap__tmp = (x);				\
+    (x) = (y);								\
+    (y) = __mp_srcptr_swap__tmp;					\
+  } while (0)
+
+#define MPN_PTR_SWAP(xp,xs, yp,ys)					\
+  do {									\
+    MP_PTR_SWAP (xp, yp);						\
+    MP_SIZE_T_SWAP (xs, ys);						\
+  } while(0)
+#define MPN_SRCPTR_SWAP(xp,xs, yp,ys)					\
+  do {									\
+    MP_SRCPTR_SWAP (xp, yp);						\
+    MP_SIZE_T_SWAP (xs, ys);						\
+  } while(0)
+
+#define MPZ_PTR_SWAP(x, y)						\
+  do {									\
+    mpz_ptr __mpz_ptr_swap__tmp = (x);					\
+    (x) = (y);								\
+    (y) = __mpz_ptr_swap__tmp;						\
+  } while (0)
+#define MPZ_SRCPTR_SWAP(x, y)						\
+  do {									\
+    mpz_srcptr __mpz_srcptr_swap__tmp = (x);				\
+    (x) = (y);								\
+    (y) = __mpz_srcptr_swap__tmp;					\
+  } while (0)
+
+const int mp_bits_per_limb = GMP_LIMB_BITS;
+
+
+/* Memory allocation and other helper functions. */
+static void
+gmp_die (const char *msg)
+{
+  printf ("%s\n", msg);
+  abort(); 
+}
+
+static void
+gmp_default_free (void *p, size_t unused_size)
+{
+	free ((void*)((addr_t*)p-1));
+}
+
+static void *
+gmp_default_alloc (size_t size)
+{
+  void *p;
+
+  assert (size > 0);
+
+  p = malloc (size+sizeof(void*));
+  if (!p)
+    gmp_die("gmp_default_alloc: Virtual memory exhausted.");
+  *(addr_t *)p = (addr_t)p+size;
+  return (void*)((addr_t *)p + 1);
+}
+
+static void *
+gmp_default_realloc (void *old, size_t unused_old_size, size_t new_size)
+{
+  void * p;
+  addr_t *_blk = (addr_t*)old - 1;
+   
+  p = gmp_default_alloc (new_size);
+
+  if (!p)
+    gmp_die("gmp_default_realloc: Virtual memory exhausted.");
+  /*debug("reallocating old size 0x%x new size 0x%x\n", (*_blk - (addr_t)_blk), new_size);*/
+  memcpy(p, old, *_blk - (addr_t)_blk);
+
+  gmp_default_free(old, 0);	
+
+  return p;
+}
+
+
+static void * (*gmp_allocate_func) (size_t) = gmp_default_alloc;
+static void * (*gmp_reallocate_func) (void *, size_t, size_t) = gmp_default_realloc;
+static void (*gmp_free_func) (void *, size_t) = gmp_default_free;
+
+void
+mp_get_memory_functions (void *(**alloc_func) (size_t),
+			 void *(**realloc_func) (void *, size_t, size_t),
+			 void (**free_func) (void *, size_t))
+{
+  if (alloc_func)
+    *alloc_func = gmp_allocate_func;
+
+  if (realloc_func)
+    *realloc_func = gmp_reallocate_func;
+
+  if (free_func)
+    *free_func = gmp_free_func;
+}
+
+void
+mp_set_memory_functions (void *(*alloc_func) (size_t),
+			 void *(*realloc_func) (void *, size_t, size_t),
+			 void (*free_func) (void *, size_t))
+{
+  if (!alloc_func)
+    alloc_func = gmp_default_alloc;
+  if (!realloc_func)
+    realloc_func = gmp_default_realloc;
+  if (!free_func)
+    free_func = gmp_default_free;
+
+  gmp_allocate_func = alloc_func;
+  gmp_reallocate_func = realloc_func;
+  gmp_free_func = free_func;
+}
+
+#define gmp_xalloc(size) ((*gmp_allocate_func)((size)))
+#define gmp_free(p) ((*gmp_free_func) ((p), 0))
+
+static mp_ptr
+gmp_xalloc_limbs (mp_size_t size)
+{
+  return (mp_ptr) gmp_xalloc (size * sizeof (mp_limb_t));
+}
+
+static mp_ptr
+gmp_xrealloc_limbs (mp_ptr old, mp_size_t size)
+{
+  assert (size > 0);
+  return (mp_ptr) (*gmp_reallocate_func) (old, 0, size * sizeof (mp_limb_t));
+}
+
+
+/* MPN interface */
+
+void
+mpn_copyi (mp_ptr d, mp_srcptr s, mp_size_t n)
+{
+  mp_size_t i;
+  for (i = 0; i < n; i++)
+    d[i] = s[i];
+}
+
+void
+mpn_copyd (mp_ptr d, mp_srcptr s, mp_size_t n)
+{
+  while (--n >= 0)
+    d[n] = s[n];
+}
+
+int
+mpn_cmp (mp_srcptr ap, mp_srcptr bp, mp_size_t n)
+{
+  while (--n >= 0)
+    {
+      if (ap[n] != bp[n])
+	return ap[n] > bp[n] ? 1 : -1;
+    }
+  return 0;
+}
+
+static int
+mpn_cmp4 (mp_srcptr ap, mp_size_t an, mp_srcptr bp, mp_size_t bn)
+{
+  if (an != bn)
+    return an < bn ? -1 : 1;
+  else
+    return mpn_cmp (ap, bp, an);
+}
+
+static mp_size_t
+mpn_normalized_size (mp_srcptr xp, mp_size_t n)
+{
+  while (n > 0 && xp[n-1] == 0)
+    --n;
+  return n;
+}
+
+int
+mpn_zero_p(mp_srcptr rp, mp_size_t n)
+{
+  return mpn_normalized_size (rp, n) == 0;
+}
+
+void
+mpn_zero (mp_ptr rp, mp_size_t n)
+{
+  while (--n >= 0)
+    rp[n] = 0;
+}
+
+mp_limb_t
+mpn_add_1 (mp_ptr rp, mp_srcptr ap, mp_size_t n, mp_limb_t b)
+{
+  mp_size_t i;
+
+  assert (n > 0);
+  i = 0;
+  do
+    {
+      mp_limb_t r = ap[i] + b;
+      /* Carry out */
+      b = (r < b);
+      rp[i] = r;
+    }
+  while (++i < n);
+
+  return b;
+}
+
+mp_limb_t
+mpn_add_n (mp_ptr rp, mp_srcptr ap, mp_srcptr bp, mp_size_t n)
+{
+  mp_size_t i;
+  mp_limb_t cy;
+
+  for (i = 0, cy = 0; i < n; i++)
+    {
+      mp_limb_t a, b, r;
+      a = ap[i]; b = bp[i];
+      r = a + cy;
+      cy = (r < cy);
+      r += b;
+      cy += (r < b);
+      rp[i] = r;
+    }
+  return cy;
+}
+
+mp_limb_t
+mpn_add (mp_ptr rp, mp_srcptr ap, mp_size_t an, mp_srcptr bp, mp_size_t bn)
+{
+  mp_limb_t cy;
+
+  assert (an >= bn);
+
+  cy = mpn_add_n (rp, ap, bp, bn);
+  if (an > bn)
+    cy = mpn_add_1 (rp + bn, ap + bn, an - bn, cy);
+  return cy;
+}
+
+mp_limb_t
+mpn_sub_1 (mp_ptr rp, mp_srcptr ap, mp_size_t n, mp_limb_t b)
+{
+  mp_size_t i;
+
+  assert (n > 0);
+
+  i = 0;
+  do
+    {
+      mp_limb_t a = ap[i];
+      /* Carry out */
+      mp_limb_t cy = a < b;
+      rp[i] = a - b;
+      b = cy;
+    }
+  while (++i < n);
+
+  return b;
+}
+
+mp_limb_t
+mpn_sub_n (mp_ptr rp, mp_srcptr ap, mp_srcptr bp, mp_size_t n)
+{
+  mp_size_t i;
+  mp_limb_t cy;
+
+  for (i = 0, cy = 0; i < n; i++)
+    {
+      mp_limb_t a, b;
+      a = ap[i]; b = bp[i];
+      b += cy;
+      cy = (b < cy);
+      cy += (a < b);
+      rp[i] = a - b;
+    }
+  return cy;
+}
+
+mp_limb_t
+mpn_sub (mp_ptr rp, mp_srcptr ap, mp_size_t an, mp_srcptr bp, mp_size_t bn)
+{
+  mp_limb_t cy;
+
+  assert (an >= bn);
+
+  cy = mpn_sub_n (rp, ap, bp, bn);
+  if (an > bn)
+    cy = mpn_sub_1 (rp + bn, ap + bn, an - bn, cy);
+  return cy;
+}
+
+mp_limb_t
+mpn_mul_1 (mp_ptr rp, mp_srcptr up, mp_size_t n, mp_limb_t vl)
+{
+  mp_limb_t ul, cl, hpl, lpl;
+
+  assert (n >= 1);
+
+  cl = 0;
+  do
+    {
+      ul = *up++;
+      gmp_umul_ppmm (hpl, lpl, ul, vl);
+
+      lpl += cl;
+      cl = (lpl < cl) + hpl;
+
+      *rp++ = lpl;
+    }
+  while (--n != 0);
+
+  return cl;
+}
+
+mp_limb_t
+mpn_addmul_1 (mp_ptr rp, mp_srcptr up, mp_size_t n, mp_limb_t vl)
+{
+  mp_limb_t ul, cl, hpl, lpl, rl;
+
+  assert (n >= 1);
+
+  cl = 0;
+  do
+    {
+      ul = *up++;
+      gmp_umul_ppmm (hpl, lpl, ul, vl);
+
+      lpl += cl;
+      cl = (lpl < cl) + hpl;
+
+      rl = *rp;
+      lpl = rl + lpl;
+      cl += lpl < rl;
+      *rp++ = lpl;
+    }
+  while (--n != 0);
+
+  return cl;
+}
+
+mp_limb_t
+mpn_submul_1 (mp_ptr rp, mp_srcptr up, mp_size_t n, mp_limb_t vl)
+{
+  mp_limb_t ul, cl, hpl, lpl, rl;
+
+  assert (n >= 1);
+
+  cl = 0;
+  do
+    {
+      ul = *up++;
+      gmp_umul_ppmm (hpl, lpl, ul, vl);
+
+      lpl += cl;
+      cl = (lpl < cl) + hpl;
+
+      rl = *rp;
+      lpl = rl - lpl;
+      cl += lpl > rl;
+      *rp++ = lpl;
+    }
+  while (--n != 0);
+
+  return cl;
+}
+
+mp_limb_t
+mpn_mul (mp_ptr rp, mp_srcptr up, mp_size_t un, mp_srcptr vp, mp_size_t vn)
+{
+  assert (un >= vn);
+  assert (vn >= 1);
+  assert (!GMP_MPN_OVERLAP_P(rp, un + vn, up, un));
+  assert (!GMP_MPN_OVERLAP_P(rp, un + vn, vp, vn));
+
+  /* We first multiply by the low order limb. This result can be
+     stored, not added, to rp. We also avoid a loop for zeroing this
+     way. */
+
+  rp[un] = mpn_mul_1 (rp, up, un, vp[0]);
+
+  /* Now accumulate the product of up[] and the next higher limb from
+     vp[]. */
+
+  while (--vn >= 1)
+    {
+      rp += 1, vp += 1;
+      rp[un] = mpn_addmul_1 (rp, up, un, vp[0]);
+    }
+  return rp[un];
+}
+
+void
+mpn_mul_n (mp_ptr rp, mp_srcptr ap, mp_srcptr bp, mp_size_t n)
+{
+  mpn_mul (rp, ap, n, bp, n);
+}
+
+void
+mpn_sqr (mp_ptr rp, mp_srcptr ap, mp_size_t n)
+{
+  mpn_mul (rp, ap, n, ap, n);
+}
+
+mp_limb_t
+mpn_lshift (mp_ptr rp, mp_srcptr up, mp_size_t n, unsigned int cnt)
+{
+  mp_limb_t high_limb, low_limb;
+  unsigned int tnc;
+  mp_limb_t retval;
+
+  assert (n >= 1);
+  assert (cnt >= 1);
+  assert (cnt < GMP_LIMB_BITS);
+
+  up += n;
+  rp += n;
+
+  tnc = GMP_LIMB_BITS - cnt;
+  low_limb = *--up;
+  retval = low_limb >> tnc;
+  high_limb = (low_limb << cnt);
+
+  while (--n != 0)
+    {
+      low_limb = *--up;
+      *--rp = high_limb | (low_limb >> tnc);
+      high_limb = (low_limb << cnt);
+    }
+  *--rp = high_limb;
+
+  return retval;
+}
+
+mp_limb_t
+mpn_rshift (mp_ptr rp, mp_srcptr up, mp_size_t n, unsigned int cnt)
+{
+  mp_limb_t high_limb, low_limb;
+  unsigned int tnc;
+  mp_limb_t retval;
+
+  assert (n >= 1);
+  assert (cnt >= 1);
+  assert (cnt < GMP_LIMB_BITS);
+
+  tnc = GMP_LIMB_BITS - cnt;
+  high_limb = *up++;
+  retval = (high_limb << tnc);
+  low_limb = high_limb >> cnt;
+
+  while (--n != 0)
+    {
+      high_limb = *up++;
+      *rp++ = low_limb | (high_limb << tnc);
+      low_limb = high_limb >> cnt;
+    }
+  *rp = low_limb;
+
+  return retval;
+}
+
+static mp_bitcnt_t
+mpn_common_scan (mp_limb_t limb, mp_size_t i, mp_srcptr up, mp_size_t un,
+		 mp_limb_t ux)
+{
+  unsigned cnt;
+
+  assert (ux == 0 || ux == GMP_LIMB_MAX);
+  assert (0 <= i && i <= un );
+
+  while (limb == 0)
+    {
+      i++;
+      if (i == un)
+	return (ux == 0 ? ~(mp_bitcnt_t) 0 : un * GMP_LIMB_BITS);
+      limb = ux ^ up[i];
+    }
+  gmp_ctz (cnt, limb);
+  return (mp_bitcnt_t) i * GMP_LIMB_BITS + cnt;
+}
+
+mp_bitcnt_t
+mpn_scan1 (mp_srcptr ptr, mp_bitcnt_t bit)
+{
+  mp_size_t i;
+  i = bit / GMP_LIMB_BITS;
+
+  return mpn_common_scan ( ptr[i] & (GMP_LIMB_MAX << (bit % GMP_LIMB_BITS)),
+			  i, ptr, i, 0);
+}
+
+mp_bitcnt_t
+mpn_scan0 (mp_srcptr ptr, mp_bitcnt_t bit)
+{
+  mp_size_t i;
+  i = bit / GMP_LIMB_BITS;
+
+  return mpn_common_scan (~ptr[i] & (GMP_LIMB_MAX << (bit % GMP_LIMB_BITS)),
+			  i, ptr, i, GMP_LIMB_MAX);
+}
+
+void
+mpn_com (mp_ptr rp, mp_srcptr up, mp_size_t n)
+{
+  while (--n >= 0)
+    *rp++ = ~ *up++;
+}
+
+mp_limb_t
+mpn_neg (mp_ptr rp, mp_srcptr up, mp_size_t n)
+{
+  while (*up == 0)
+    {
+      *rp = 0;
+      if (!--n)
+	return 0;
+      ++up; ++rp;
+    }
+  *rp = - *up;
+  mpn_com (++rp, ++up, --n);
+  return 1;
+}
+
+
+/* MPN division interface. */
+
+/* The 3/2 inverse is defined as
+
+     m = floor( (B^3-1) / (B u1 + u0)) - B
+*/
+mp_limb_t
+mpn_invert_3by2 (mp_limb_t u1, mp_limb_t u0)
+{
+  mp_limb_t r, m;
+
+  {
+    mp_limb_t p, ql;
+    unsigned ul, uh, qh;
+
+    /* For notation, let b denote the half-limb base, so that B = b^2.
+       Split u1 = b uh + ul. */
+    ul = u1 & GMP_LLIMB_MASK;
+    uh = u1 >> (GMP_LIMB_BITS / 2);
+
+    /* Approximation of the high half of quotient. Differs from the 2/1
+       inverse of the half limb uh, since we have already subtracted
+       u0. */
+    qh = (u1 ^ GMP_LIMB_MAX) / uh;
+
+    /* Adjust to get a half-limb 3/2 inverse, i.e., we want
+
+       qh' = floor( (b^3 - 1) / u) - b = floor ((b^3 - b u - 1) / u
+	   = floor( (b (~u) + b-1) / u),
+	   
+       and the remainder
+
+       r = b (~u) + b-1 - qh (b uh + ul)
+       = b (~u - qh uh) + b-1 - qh ul
+
+       Subtraction of qh ul may underflow, which implies adjustments.
+       But by normalization, 2 u >= B > qh ul, so we need to adjust by
+       at most 2.
+    */
+
+    r = ((~u1 - (mp_limb_t) qh * uh) << (GMP_LIMB_BITS / 2)) | GMP_LLIMB_MASK;
+
+    p = (mp_limb_t) qh * ul;
+    /* Adjustment steps taken from udiv_qrnnd_c */
+    if (r < p)
+      {
+	qh--;
+	r += u1;
+	if (r >= u1) /* i.e. we didn't get carry when adding to r */
+	  if (r < p)
+	    {
+	      qh--;
+	      r += u1;
+	    }
+      }
+    r -= p;
+
+    /* Low half of the quotient is
+
+       ql = floor ( (b r + b-1) / u1).
+
+       This is a 3/2 division (on half-limbs), for which qh is a
+       suitable inverse. */
+
+    p = (r >> (GMP_LIMB_BITS / 2)) * qh + r;
+    /* Unlike full-limb 3/2, we can add 1 without overflow. For this to
+       work, it is essential that ql is a full mp_limb_t. */
+    ql = (p >> (GMP_LIMB_BITS / 2)) + 1;
+
+    /* By the 3/2 trick, we don't need the high half limb. */
+    r = (r << (GMP_LIMB_BITS / 2)) + GMP_LLIMB_MASK - ql * u1;
+
+    if (r >= (GMP_LIMB_MAX & (p << (GMP_LIMB_BITS / 2))))
+      {
+	ql--;
+	r += u1;
+      }
+    m = ((mp_limb_t) qh << (GMP_LIMB_BITS / 2)) + ql;
+    if (r >= u1)
+      {
+	m++;
+	r -= u1;
+      }
+  }
+
+  /* Now m is the 2/1 inverse of u1. If u0 > 0, adjust it to become a
+     3/2 inverse. */
+  if (u0 > 0)
+    {
+      mp_limb_t th, tl;
+      r = ~r;
+      r += u0;
+      if (r < u0)
+	{
+	  m--;
+	  if (r >= u1)
+	    {
+	      m--;
+	      r -= u1;
+	    }
+	  r -= u1;
+	}
+      gmp_umul_ppmm (th, tl, u0, m);
+      r += th;
+      if (r < th)
+	{
+	  m--;
+	  m -= ((r > u1) | ((r == u1) & (tl > u0)));
+	}
+    }
+
+  return m;
+}
+
+struct gmp_div_inverse
+{
+  /* Normalization shift count. */
+  unsigned shift;
+  /* Normalized divisor (d0 unused for mpn_div_qr_1) */
+  mp_limb_t d1, d0;
+  /* Inverse, for 2/1 or 3/2. */
+  mp_limb_t di;
+};
+
+static void
+mpn_div_qr_1_invert (struct gmp_div_inverse *inv, mp_limb_t d)
+{
+  unsigned shift;
+
+  assert (d > 0);
+  gmp_clz (shift, d);
+  inv->shift = shift;
+  inv->d1 = d << shift;
+  inv->di = mpn_invert_limb (inv->d1);
+}
+
+static void
+mpn_div_qr_2_invert (struct gmp_div_inverse *inv,
+		     mp_limb_t d1, mp_limb_t d0)
+{
+  unsigned shift;
+
+  assert (d1 > 0);
+  gmp_clz (shift, d1);
+  inv->shift = shift;
+  if (shift > 0)
+    {
+      d1 = (d1 << shift) | (d0 >> (GMP_LIMB_BITS - shift));
+      d0 <<= shift;
+    }
+  inv->d1 = d1;
+  inv->d0 = d0;
+  inv->di = mpn_invert_3by2 (d1, d0);
+}
+
+static void
+mpn_div_qr_invert (struct gmp_div_inverse *inv,
+		   mp_srcptr dp, mp_size_t dn)
+{
+  assert (dn > 0);
+
+  if (dn == 1)
+    mpn_div_qr_1_invert (inv, dp[0]);
+  else if (dn == 2)
+    mpn_div_qr_2_invert (inv, dp[1], dp[0]);
+  else
+    {
+      unsigned shift;
+      mp_limb_t d1, d0;
+
+      d1 = dp[dn-1];
+      d0 = dp[dn-2];
+      assert (d1 > 0);
+      gmp_clz (shift, d1);
+      inv->shift = shift;
+      if (shift > 0)
+	{
+	  d1 = (d1 << shift) | (d0 >> (GMP_LIMB_BITS - shift));
+	  d0 = (d0 << shift) | (dp[dn-3] >> (GMP_LIMB_BITS - shift));
+	}
+      inv->d1 = d1;
+      inv->d0 = d0;
+      inv->di = mpn_invert_3by2 (d1, d0);
+    }
+}
+
+/* Not matching current public gmp interface, rather corresponding to
+   the sbpi1_div_* functions. */
+static mp_limb_t
+mpn_div_qr_1_preinv (mp_ptr qp, mp_srcptr np, mp_size_t nn,
+		     const struct gmp_div_inverse *inv)
+{
+  mp_limb_t d, di;
+  mp_limb_t r;
+  mp_ptr tp = NULL;
+
+  if (inv->shift > 0)
+    {
+      /* Shift, reusing qp area if possible. In-place shift if qp == np. */
+      tp = qp ? qp : gmp_xalloc_limbs (nn);
+      r = mpn_lshift (tp, np, nn, inv->shift);
+      np = tp;
+    }
+  else
+    r = 0;
+
+  d = inv->d1;
+  di = inv->di;
+  while (--nn >= 0)
+    {
+      mp_limb_t q;
+
+      gmp_udiv_qrnnd_preinv (q, r, r, np[nn], d, di);
+      if (qp)
+	qp[nn] = q;
+    }
+  if ((inv->shift > 0) && (tp != qp))
+    gmp_free (tp);
+
+  return r >> inv->shift;
+}
+
+static void
+mpn_div_qr_2_preinv (mp_ptr qp, mp_ptr np, mp_size_t nn,
+		     const struct gmp_div_inverse *inv)
+{
+  unsigned shift;
+  mp_size_t i;
+  mp_limb_t d1, d0, di, r1, r0;
+
+  assert (nn >= 2);
+  shift = inv->shift;
+  d1 = inv->d1;
+  d0 = inv->d0;
+  di = inv->di;
+
+  if (shift > 0)
+    r1 = mpn_lshift (np, np, nn, shift);
+  else
+    r1 = 0;
+
+  r0 = np[nn - 1];
+
+  i = nn - 2;
+  do
+    {
+      mp_limb_t n0, q;
+      n0 = np[i];
+      gmp_udiv_qr_3by2 (q, r1, r0, r1, r0, n0, d1, d0, di);
+
+      if (qp)
+	qp[i] = q;
+    }
+  while (--i >= 0);
+
+  if (shift > 0)
+    {
+      assert ((r0 & (GMP_LIMB_MAX >> (GMP_LIMB_BITS - shift))) == 0);
+      r0 = (r0 >> shift) | (r1 << (GMP_LIMB_BITS - shift));
+      r1 >>= shift;
+    }
+
+  np[1] = r1;
+  np[0] = r0;
+}
+
+static void
+mpn_div_qr_pi1 (mp_ptr qp,
+		mp_ptr np, mp_size_t nn, mp_limb_t n1,
+		mp_srcptr dp, mp_size_t dn,
+		mp_limb_t dinv)
+{
+  mp_size_t i;
+
+  mp_limb_t d1, d0;
+  mp_limb_t cy, cy1;
+  mp_limb_t q;
+
+  assert (dn > 2);
+  assert (nn >= dn);
+
+  d1 = dp[dn - 1];
+  d0 = dp[dn - 2];
+
+  assert ((d1 & GMP_LIMB_HIGHBIT) != 0);
+  /* Iteration variable is the index of the q limb.
+   *
+   * We divide <n1, np[dn-1+i], np[dn-2+i], np[dn-3+i],..., np[i]>
+   * by            <d1,          d0,        dp[dn-3],  ..., dp[0] >
+   */
+
+  i = nn - dn;
+  do
+    {
+      mp_limb_t n0 = np[dn-1+i];
+
+      if (n1 == d1 && n0 == d0)
+	{
+	  q = GMP_LIMB_MAX;
+	  mpn_submul_1 (np+i, dp, dn, q);
+	  n1 = np[dn-1+i];	/* update n1, last loop's value will now be invalid */
+	}
+      else
+	{
+	  gmp_udiv_qr_3by2 (q, n1, n0, n1, n0, np[dn-2+i], d1, d0, dinv);
+
+	  cy = mpn_submul_1 (np + i, dp, dn-2, q);
+
+	  cy1 = n0 < cy;
+	  n0 = n0 - cy;
+	  cy = n1 < cy1;
+	  n1 = n1 - cy1;
+	  np[dn-2+i] = n0;
+
+	  if (cy != 0)
+	    {
+	      n1 += d1 + mpn_add_n (np + i, np + i, dp, dn - 1);
+	      q--;
+	    }
+	}
+
+      if (qp)
+	qp[i] = q;
+    }
+  while (--i >= 0);
+
+  np[dn - 1] = n1;
+}
+
+static void
+mpn_div_qr_preinv (mp_ptr qp, mp_ptr np, mp_size_t nn,
+		   mp_srcptr dp, mp_size_t dn,
+		   const struct gmp_div_inverse *inv)
+{
+  assert (dn > 0);
+  assert (nn >= dn);
+
+  if (dn == 1)
+    np[0] = mpn_div_qr_1_preinv (qp, np, nn, inv);
+  else if (dn == 2)
+    mpn_div_qr_2_preinv (qp, np, nn, inv);
+  else
+    {
+      mp_limb_t nh;
+      unsigned shift;
+
+      assert (inv->d1 == dp[dn-1]);
+      assert (inv->d0 == dp[dn-2]);
+      assert ((inv->d1 & GMP_LIMB_HIGHBIT) != 0);
+
+      shift = inv->shift;
+      if (shift > 0)
+	nh = mpn_lshift (np, np, nn, shift);
+      else
+	nh = 0;
+
+      mpn_div_qr_pi1 (qp, np, nn, nh, dp, dn, inv->di);
+
+      if (shift > 0)
+	gmp_assert_nocarry (mpn_rshift (np, np, dn, shift));
+    }
+}
+
+static void
+mpn_div_qr (mp_ptr qp, mp_ptr np, mp_size_t nn, mp_srcptr dp, mp_size_t dn)
+{
+  struct gmp_div_inverse inv;
+  mp_ptr tp = NULL;
+
+  assert (dn > 0);
+  assert (nn >= dn);
+
+  mpn_div_qr_invert (&inv, dp, dn);
+  if (dn > 2 && inv.shift > 0)
+    {
+      tp = gmp_xalloc_limbs (dn);
+      gmp_assert_nocarry (mpn_lshift (tp, dp, dn, inv.shift));
+      dp = tp;
+    }
+  mpn_div_qr_preinv (qp, np, nn, dp, dn, &inv);
+  if (tp)
+    gmp_free (tp);
+}
+
+
+/* MPN base conversion. */
+static unsigned
+mpn_base_power_of_two_p (unsigned b)
+{
+  switch (b)
+    {
+    case 2: return 1;
+    case 4: return 2;
+    case 8: return 3;
+    case 16: return 4;
+    case 32: return 5;
+    case 64: return 6;
+    case 128: return 7;
+    case 256: return 8;
+    default: return 0;
+    }
+}
+
+struct mpn_base_info
+{
+  /* bb is the largest power of the base which fits in one limb, and
+     exp is the corresponding exponent. */
+  unsigned exp;
+  mp_limb_t bb;
+};
+
+static void
+mpn_get_base_info (struct mpn_base_info *info, mp_limb_t b)
+{
+  mp_limb_t m;
+  mp_limb_t p;
+  unsigned exp;
+
+  m = GMP_LIMB_MAX / b;
+  for (exp = 1, p = b; p <= m; exp++)
+    p *= b;
+
+  info->exp = exp;
+  info->bb = p;
+}
+
+static mp_bitcnt_t
+mpn_limb_size_in_base_2 (mp_limb_t u)
+{
+  unsigned shift;
+
+  assert (u > 0);
+  gmp_clz (shift, u);
+  return GMP_LIMB_BITS - shift;
+}
+
+static size_t
+mpn_get_str_bits (unsigned char *sp, unsigned bits, mp_srcptr up, mp_size_t un)
+{
+  unsigned char mask;
+  size_t sn, j;
+  mp_size_t i;
+  unsigned shift;
+
+  sn = ((un - 1) * GMP_LIMB_BITS + mpn_limb_size_in_base_2 (up[un-1])
+	+ bits - 1) / bits;
+
+  mask = (1U << bits) - 1;
+
+  for (i = 0, j = sn, shift = 0; j-- > 0;)
+    {
+      unsigned char digit = up[i] >> shift;
+
+      shift += bits;
+
+      if (shift >= GMP_LIMB_BITS && ++i < un)
+	{
+	  shift -= GMP_LIMB_BITS;
+	  digit |= up[i] << (bits - shift);
+	}
+      sp[j] = digit & mask;
+    }
+  return sn;
+}
+
+/* We generate digits from the least significant end, and reverse at
+   the end. */
+static size_t
+mpn_limb_get_str (unsigned char *sp, mp_limb_t w,
+		  const struct gmp_div_inverse *binv)
+{
+  mp_size_t i;
+  for (i = 0; w > 0; i++)
+    {
+      mp_limb_t h, l, r;
+
+      h = w >> (GMP_LIMB_BITS - binv->shift);
+      l = w << binv->shift;
+
+      gmp_udiv_qrnnd_preinv (w, r, h, l, binv->d1, binv->di);
+      assert ((r & (GMP_LIMB_MAX >> (GMP_LIMB_BITS - binv->shift))) == 0);
+      r >>= binv->shift;
+
+      sp[i] = r;
+    }
+  return i;
+}
+
+static size_t
+mpn_get_str_other (unsigned char *sp,
+		   int base, const struct mpn_base_info *info,
+		   mp_ptr up, mp_size_t un)
+{
+  struct gmp_div_inverse binv;
+  size_t sn;
+  size_t i;
+
+  mpn_div_qr_1_invert (&binv, base);
+
+  sn = 0;
+
+  if (un > 1)
+    {
+      struct gmp_div_inverse bbinv;
+      mpn_div_qr_1_invert (&bbinv, info->bb);
+
+      do
+	{
+	  mp_limb_t w;
+	  size_t done;
+	  w = mpn_div_qr_1_preinv (up, up, un, &bbinv);
+	  un -= (up[un-1] == 0);
+	  done = mpn_limb_get_str (sp + sn, w, &binv);
+
+	  for (sn += done; done < info->exp; done++)
+	    sp[sn++] = 0;
+	}
+      while (un > 1);
+    }
+  sn += mpn_limb_get_str (sp + sn, up[0], &binv);
+
+  /* Reverse order */
+  for (i = 0; 2*i + 1 < sn; i++)
+    {
+      unsigned char t = sp[i];
+      sp[i] = sp[sn - i - 1];
+      sp[sn - i - 1] = t;
+    }
+
+  return sn;
+}
+
+size_t
+mpn_get_str (unsigned char *sp, int base, mp_ptr up, mp_size_t un)
+{
+  unsigned bits;
+
+  assert (un > 0);
+  assert (up[un-1] > 0);
+
+  bits = mpn_base_power_of_two_p (base);
+  if (bits)
+    return mpn_get_str_bits (sp, bits, up, un);
+  else
+    {
+      struct mpn_base_info info;
+
+      mpn_get_base_info (&info, base);
+      return mpn_get_str_other (sp, base, &info, up, un);
+    }
+}
+
+static mp_size_t
+mpn_set_str_bits (mp_ptr rp, const unsigned char *sp, size_t sn,
+		  unsigned bits)
+{
+  mp_size_t rn;
+  size_t j;
+  unsigned shift;
+
+  for (j = sn, rn = 0, shift = 0; j-- > 0; )
+    {
+      if (shift == 0)
+	{
+	  rp[rn++] = sp[j];
+	  shift += bits;
+	}
+      else
+	{
+	  rp[rn-1] |= (mp_limb_t) sp[j] << shift;
+	  shift += bits;
+	  if (shift >= GMP_LIMB_BITS)
+	    {
+	      shift -= GMP_LIMB_BITS;
+	      if (shift > 0)
+		rp[rn++] = (mp_limb_t) sp[j] >> (bits - shift);
+	    }
+	}
+    }
+  rn = mpn_normalized_size (rp, rn);
+  return rn;
+}
+
+/* Result is usually normalized, except for all-zero input, in which
+   case a single zero limb is written at *RP, and 1 is returned. */
+static mp_size_t
+mpn_set_str_other (mp_ptr rp, const unsigned char *sp, size_t sn,
+		   mp_limb_t b, const struct mpn_base_info *info)
+{
+  mp_size_t rn;
+  mp_limb_t w;
+  unsigned k;
+  size_t j;
+
+  assert (sn > 0);
+
+  k = 1 + (sn - 1) % info->exp;
+
+  j = 0;
+  w = sp[j++];
+  while (--k != 0)
+    w = w * b + sp[j++];
+
+  rp[0] = w;
+
+  for (rn = 1; j < sn;)
+    {
+      mp_limb_t cy;
+
+      w = sp[j++];
+      for (k = 1; k < info->exp; k++)
+	w = w * b + sp[j++];
+
+      cy = mpn_mul_1 (rp, rp, rn, info->bb);
+      cy += mpn_add_1 (rp, rp, rn, w);
+      if (cy > 0)
+	rp[rn++] = cy;
+    }
+  assert (j == sn);
+
+  return rn;
+}
+
+mp_size_t
+mpn_set_str (mp_ptr rp, const unsigned char *sp, size_t sn, int base)
+{
+  unsigned bits;
+
+  if (sn == 0)
+    return 0;
+
+  bits = mpn_base_power_of_two_p (base);
+  if (bits)
+    return mpn_set_str_bits (rp, sp, sn, bits);
+  else
+    {
+      struct mpn_base_info info;
+
+      mpn_get_base_info (&info, base);
+      return mpn_set_str_other (rp, sp, sn, base, &info);
+    }
+}
+
+
+/* MPZ interface */
+void
+mpz_init (mpz_t r)
+{
+  static const mp_limb_t dummy_limb = GMP_LIMB_MAX & 0xc1a0;
+
+  r->_mp_alloc = 0;
+  r->_mp_size = 0;
+  r->_mp_d = (mp_ptr) &dummy_limb;
+}
+
+/* The utility of this function is a bit limited, since many functions
+   assigns the result variable using mpz_swap. */
+void
+mpz_init2 (mpz_t r, mp_bitcnt_t bits)
+{
+  mp_size_t rn;
+
+  bits -= (bits != 0);		/* Round down, except if 0 */
+  rn = 1 + bits / GMP_LIMB_BITS;
+
+  r->_mp_alloc = rn;
+  r->_mp_size = 0;
+  r->_mp_d = gmp_xalloc_limbs (rn);
+}
+
+void
+mpz_clear (mpz_t r)
+{
+  if (r->_mp_alloc)
+    gmp_free (r->_mp_d);
+}
+
+static mp_ptr
+mpz_realloc (mpz_t r, mp_size_t size)
+{
+  size = GMP_MAX (size, 1);
+
+  if (r->_mp_alloc)
+    r->_mp_d = gmp_xrealloc_limbs (r->_mp_d, size);
+  else
+    r->_mp_d = gmp_xalloc_limbs (size);
+  r->_mp_alloc = size;
+
+  if (GMP_ABS (r->_mp_size) > size)
+    r->_mp_size = 0;
+
+  return r->_mp_d;
+}
+
+/* Realloc for an mpz_t WHAT if it has less than NEEDED limbs.  */
+#define MPZ_REALLOC(z,n) ((n) > (z)->_mp_alloc			\
+			  ? mpz_realloc(z,n)			\
+			  : (z)->_mp_d)
+
+/* MPZ assignment and basic conversions. */
+void
+mpz_set_si (mpz_t r, signed long int x)
+{
+  if (x >= 0)
+    mpz_set_ui (r, x);
+  else /* (x < 0) */
+    if (GMP_LIMB_BITS < GMP_ULONG_BITS)
+      {
+	mpz_set_ui (r, GMP_NEG_CAST (unsigned long int, x));
+	mpz_neg (r, r);
+      }
+  else
+    {
+      r->_mp_size = -1;
+      MPZ_REALLOC (r, 1)[0] = GMP_NEG_CAST (unsigned long int, x);
+    }
+}
+
+void
+mpz_set_ui (mpz_t r, unsigned long int x)
+{
+  if (x > 0)
+    {
+      r->_mp_size = 1;
+      MPZ_REALLOC (r, 1)[0] = x;
+      if (GMP_LIMB_BITS < GMP_ULONG_BITS)
+	{
+	  int LOCAL_GMP_LIMB_BITS = GMP_LIMB_BITS;
+	  while (x >>= LOCAL_GMP_LIMB_BITS)
+	    {
+	      ++ r->_mp_size;
+	      MPZ_REALLOC (r, r->_mp_size)[r->_mp_size - 1] = x;
+	    }
+	}
+    }
+  else
+    r->_mp_size = 0;
+}
+
+void
+mpz_set (mpz_t r, const mpz_t x)
+{
+  /* Allow the NOP r == x */
+  if (r != x)
+    {
+      mp_size_t n;
+      mp_ptr rp;
+
+      n = GMP_ABS (x->_mp_size);
+      rp = MPZ_REALLOC (r, n);
+
+      mpn_copyi (rp, x->_mp_d, n);
+      r->_mp_size = x->_mp_size;
+    }
+}
+
+void
+mpz_init_set_si (mpz_t r, signed long int x)
+{
+  mpz_init (r);
+  mpz_set_si (r, x);
+}
+
+void
+mpz_init_set_ui (mpz_t r, unsigned long int x)
+{
+  mpz_init (r);
+  mpz_set_ui (r, x);
+}
+
+void
+mpz_init_set (mpz_t r, const mpz_t x)
+{
+  mpz_init (r);
+  mpz_set (r, x);
+}
+
+int
+mpz_fits_slong_p (const mpz_t u)
+{
+  return (LONG_MAX + LONG_MIN == 0 || mpz_cmp_ui (u, LONG_MAX) <= 0) &&
+    mpz_cmpabs_ui (u, GMP_NEG_CAST (unsigned long int, LONG_MIN)) <= 0;
+}
+
+static int
+mpn_absfits_ulong_p (mp_srcptr up, mp_size_t un)
+{
+  int ulongsize = GMP_ULONG_BITS / GMP_LIMB_BITS;
+  mp_limb_t ulongrem = 0;
+
+  if (GMP_ULONG_BITS % GMP_LIMB_BITS != 0)
+    ulongrem = (mp_limb_t) (ULONG_MAX >> GMP_LIMB_BITS * ulongsize) + 1;
+
+  return un <= ulongsize || (up[ulongsize] < ulongrem && un == ulongsize + 1);
+}
+
+int
+mpz_fits_ulong_p (const mpz_t u)
+{
+  mp_size_t us = u->_mp_size;
+
+  return us >= 0 && mpn_absfits_ulong_p (u->_mp_d, us);
+}
+
+long int
+mpz_get_si (const mpz_t u)
+{
+  unsigned long r = mpz_get_ui (u);
+  unsigned long c = -LONG_MAX - LONG_MIN;
+
+  if (u->_mp_size < 0)
+    /* This expression is necessary to properly handle -LONG_MIN */
+    return -(long) c - (long) ((r - c) & LONG_MAX);
+  else
+    return (long) (r & LONG_MAX);
+}
+
+unsigned long int
+mpz_get_ui (const mpz_t u)
+{
+  if (GMP_LIMB_BITS < GMP_ULONG_BITS)
+    {
+      int LOCAL_GMP_LIMB_BITS = GMP_LIMB_BITS;
+      unsigned long r = 0;
+      mp_size_t n = GMP_ABS (u->_mp_size);
+      n = GMP_MIN (n, 1 + (mp_size_t) (GMP_ULONG_BITS - 1) / GMP_LIMB_BITS);
+      while (--n >= 0)
+	r = (r << LOCAL_GMP_LIMB_BITS) + u->_mp_d[n];
+      return r;
+    }
+
+  return u->_mp_size == 0 ? 0 : u->_mp_d[0];
+}
+
+size_t
+mpz_size (const mpz_t u)
+{
+  return GMP_ABS (u->_mp_size);
+}
+
+mp_limb_t
+mpz_getlimbn (const mpz_t u, mp_size_t n)
+{
+  if (n >= 0 && n < GMP_ABS (u->_mp_size))
+    return u->_mp_d[n];
+  else
+    return 0;
+}
+
+void
+mpz_realloc2 (mpz_t x, mp_bitcnt_t n)
+{
+  mpz_realloc (x, 1 + (n - (n != 0)) / GMP_LIMB_BITS);
+}
+
+mp_srcptr
+mpz_limbs_read (mpz_srcptr x)
+{
+  return x->_mp_d;
+}
+
+mp_ptr
+mpz_limbs_modify (mpz_t x, mp_size_t n)
+{
+  assert (n > 0);
+  return MPZ_REALLOC (x, n);
+}
+
+mp_ptr
+mpz_limbs_write (mpz_t x, mp_size_t n)
+{
+  return mpz_limbs_modify (x, n);
+}
+
+void
+mpz_limbs_finish (mpz_t x, mp_size_t xs)
+{
+  mp_size_t xn;
+  xn = mpn_normalized_size (x->_mp_d, GMP_ABS (xs));
+  x->_mp_size = xs < 0 ? -xn : xn;
+}
+
+static mpz_srcptr
+mpz_roinit_normal_n (mpz_t x, mp_srcptr xp, mp_size_t xs)
+{
+  x->_mp_alloc = 0;
+  x->_mp_d = (mp_ptr) xp;
+  x->_mp_size = xs;
+  return x;
+}
+
+mpz_srcptr
+mpz_roinit_n (mpz_t x, mp_srcptr xp, mp_size_t xs)
+{
+  mpz_roinit_normal_n (x, xp, xs);
+  mpz_limbs_finish (x, xs);
+  return x;
+}
+
+
+/* Conversions and comparison to double. */
+void
+mpz_set_d (mpz_t r, double x)
+{
+  int sign;
+  mp_ptr rp;
+  mp_size_t rn, i;
+  double B;
+  double Bi;
+  mp_limb_t f;
+
+  /* x != x is true when x is a NaN, and x == x * 0.5 is true when x is
+     zero or infinity. */
+  if (x != x || x == x * 0.5)
+    {
+      r->_mp_size = 0;
+      return;
+    }
+
+  sign = x < 0.0 ;
+  if (sign)
+    x = - x;
+
+  if (x < 1.0)
+    {
+      r->_mp_size = 0;
+      return;
+    }
+  B = 4.0 * (double) (GMP_LIMB_HIGHBIT >> 1);
+  Bi = 1.0 / B;
+  for (rn = 1; x >= B; rn++)
+    x *= Bi;
+
+  rp = MPZ_REALLOC (r, rn);
+
+  f = (mp_limb_t) x;
+  x -= f;
+  assert (x < 1.0);
+  i = rn-1;
+  rp[i] = f;
+  while (--i >= 0)
+    {
+      x = B * x;
+      f = (mp_limb_t) x;
+      x -= f;
+      assert (x < 1.0);
+      rp[i] = f;
+    }
+
+  r->_mp_size = sign ? - rn : rn;
+}
+
+void
+mpz_init_set_d (mpz_t r, double x)
+{
+  mpz_init (r);
+  mpz_set_d (r, x);
+}
+
+double
+mpz_get_d (const mpz_t u)
+{
+  int m;
+  mp_limb_t l;
+  mp_size_t un;
+  double x;
+  double B = 4.0 * (double) (GMP_LIMB_HIGHBIT >> 1);
+
+  un = GMP_ABS (u->_mp_size);
+
+  if (un == 0)
+    return 0.0;
+
+  l = u->_mp_d[--un];
+  gmp_clz (m, l);
+  m = m + GMP_DBL_MANT_BITS - GMP_LIMB_BITS;
+  if (m < 0)
+    l &= GMP_LIMB_MAX << -m;
+
+  for (x = l; --un >= 0;)
+    {
+      x = B*x;
+      if (m > 0) {
+	l = u->_mp_d[un];
+	m -= GMP_LIMB_BITS;
+	if (m < 0)
+	  l &= GMP_LIMB_MAX << -m;
+	x += l;
+      }
+    }
+
+  if (u->_mp_size < 0)
+    x = -x;
+
+  return x;
+}
+
+int
+mpz_cmpabs_d (const mpz_t x, double d)
+{
+  mp_size_t xn;
+  double B, Bi;
+  mp_size_t i;
+
+  xn = x->_mp_size;
+  d = GMP_ABS (d);
+
+  if (xn != 0)
+    {
+      xn = GMP_ABS (xn);
+
+      B = 4.0 * (double) (GMP_LIMB_HIGHBIT >> 1);
+      Bi = 1.0 / B;
+
+      /* Scale d so it can be compared with the top limb. */
+      for (i = 1; i < xn; i++)
+	d *= Bi;
+
+      if (d >= B)
+	return -1;
+
+      /* Compare floor(d) to top limb, subtract and cancel when equal. */
+      for (i = xn; i-- > 0;)
+	{
+	  mp_limb_t f, xl;
+
+	  f = (mp_limb_t) d;
+	  xl = x->_mp_d[i];
+	  if (xl > f)
+	    return 1;
+	  else if (xl < f)
+	    return -1;
+	  d = B * (d - f);
+	}
+    }
+  return - (d > 0.0);
+}
+
+int
+mpz_cmp_d (const mpz_t x, double d)
+{
+  if (x->_mp_size < 0)
+    {
+      if (d >= 0.0)
+	return -1;
+      else
+	return -mpz_cmpabs_d (x, d);
+    }
+  else
+    {
+      if (d < 0.0)
+	return 1;
+      else
+	return mpz_cmpabs_d (x, d);
+    }
+}
+
+
+/* MPZ comparisons and the like. */
+int
+mpz_sgn (const mpz_t u)
+{
+  return GMP_CMP (u->_mp_size, 0);
+}
+
+int
+mpz_cmp_si (const mpz_t u, long v)
+{
+  mp_size_t usize = u->_mp_size;
+
+  if (v >= 0)
+    return mpz_cmp_ui (u, v);
+  else if (usize >= 0)
+    return 1;
+  else
+    return - mpz_cmpabs_ui (u, GMP_NEG_CAST (unsigned long int, v));
+}
+
+int
+mpz_cmp_ui (const mpz_t u, unsigned long v)
+{
+  mp_size_t usize = u->_mp_size;
+
+  if (usize < 0)
+    return -1;
+  else
+    return mpz_cmpabs_ui (u, v);
+}
+
+int
+mpz_cmp (const mpz_t a, const mpz_t b)
+{
+  mp_size_t asize = a->_mp_size;
+  mp_size_t bsize = b->_mp_size;
+
+  if (asize != bsize)
+    return (asize < bsize) ? -1 : 1;
+  else if (asize >= 0)
+    return mpn_cmp (a->_mp_d, b->_mp_d, asize);
+  else
+    return mpn_cmp (b->_mp_d, a->_mp_d, -asize);
+}
+
+int
+mpz_cmpabs_ui (const mpz_t u, unsigned long v)
+{
+  mp_size_t un = GMP_ABS (u->_mp_size);
+
+  if (! mpn_absfits_ulong_p (u->_mp_d, un))
+    return 1;
+  else
+    {
+      unsigned long uu = mpz_get_ui (u);
+      return GMP_CMP(uu, v);
+    }
+}
+
+int
+mpz_cmpabs (const mpz_t u, const mpz_t v)
+{
+  return mpn_cmp4 (u->_mp_d, GMP_ABS (u->_mp_size),
+		   v->_mp_d, GMP_ABS (v->_mp_size));
+}
+
+void
+mpz_abs (mpz_t r, const mpz_t u)
+{
+  mpz_set (r, u);
+  r->_mp_size = GMP_ABS (r->_mp_size);
+}
+
+void
+mpz_neg (mpz_t r, const mpz_t u)
+{
+  mpz_set (r, u);
+  r->_mp_size = -r->_mp_size;
+}
+
+void
+mpz_swap (mpz_t u, mpz_t v)
+{
+  MP_SIZE_T_SWAP (u->_mp_size, v->_mp_size);
+  MP_SIZE_T_SWAP (u->_mp_alloc, v->_mp_alloc);
+  MP_PTR_SWAP (u->_mp_d, v->_mp_d);
+}
+
+
+/* MPZ addition and subtraction */
+
+
+void
+mpz_add_ui (mpz_t r, const mpz_t a, unsigned long b)
+{
+  mpz_t bb;
+  mpz_init_set_ui (bb, b);
+  mpz_add (r, a, bb);
+  mpz_clear (bb);
+}
+
+void
+mpz_sub_ui (mpz_t r, const mpz_t a, unsigned long b)
+{
+  mpz_ui_sub (r, b, a);
+  mpz_neg (r, r);
+}
+
+void
+mpz_ui_sub (mpz_t r, unsigned long a, const mpz_t b)
+{
+  mpz_neg (r, b);
+  mpz_add_ui (r, r, a);
+}
+
+static mp_size_t
+mpz_abs_add (mpz_t r, const mpz_t a, const mpz_t b)
+{
+  mp_size_t an = GMP_ABS (a->_mp_size);
+  mp_size_t bn = GMP_ABS (b->_mp_size);
+  mp_ptr rp;
+  mp_limb_t cy;
+
+  if (an < bn)
+    {
+      MPZ_SRCPTR_SWAP (a, b);
+      MP_SIZE_T_SWAP (an, bn);
+    }
+
+  rp = MPZ_REALLOC (r, an + 1);
+  cy = mpn_add (rp, a->_mp_d, an, b->_mp_d, bn);
+
+  rp[an] = cy;
+
+  return an + cy;
+}
+
+static mp_size_t
+mpz_abs_sub (mpz_t r, const mpz_t a, const mpz_t b)
+{
+  mp_size_t an = GMP_ABS (a->_mp_size);
+  mp_size_t bn = GMP_ABS (b->_mp_size);
+  int cmp;
+  mp_ptr rp;
+
+  cmp = mpn_cmp4 (a->_mp_d, an, b->_mp_d, bn);
+  if (cmp > 0)
+    {
+      rp = MPZ_REALLOC (r, an);
+      gmp_assert_nocarry (mpn_sub (rp, a->_mp_d, an, b->_mp_d, bn));
+      return mpn_normalized_size (rp, an);
+    }
+  else if (cmp < 0)
+    {
+      rp = MPZ_REALLOC (r, bn);
+      gmp_assert_nocarry (mpn_sub (rp, b->_mp_d, bn, a->_mp_d, an));
+      return -mpn_normalized_size (rp, bn);
+    }
+  else
+    return 0;
+}
+
+void
+mpz_add (mpz_t r, const mpz_t a, const mpz_t b)
+{
+  mp_size_t rn;
+
+  if ( (a->_mp_size ^ b->_mp_size) >= 0)
+    rn = mpz_abs_add (r, a, b);
+  else
+    rn = mpz_abs_sub (r, a, b);
+
+  r->_mp_size = a->_mp_size >= 0 ? rn : - rn;
+}
+
+void
+mpz_sub (mpz_t r, const mpz_t a, const mpz_t b)
+{
+  mp_size_t rn;
+
+  if ( (a->_mp_size ^ b->_mp_size) >= 0)
+    rn = mpz_abs_sub (r, a, b);
+  else
+    rn = mpz_abs_add (r, a, b);
+
+  r->_mp_size = a->_mp_size >= 0 ? rn : - rn;
+}
+
+
+/* MPZ multiplication */
+void
+mpz_mul_si (mpz_t r, const mpz_t u, long int v)
+{
+  if (v < 0)
+    {
+      mpz_mul_ui (r, u, GMP_NEG_CAST (unsigned long int, v));
+      mpz_neg (r, r);
+    }
+  else
+    mpz_mul_ui (r, u, v);
+}
+
+void
+mpz_mul_ui (mpz_t r, const mpz_t u, unsigned long int v)
+{
+  mpz_t vv;
+  mpz_init_set_ui (vv, v);
+  mpz_mul (r, u, vv);
+  mpz_clear (vv);
+  return;
+}
+
+void
+mpz_mul (mpz_t r, const mpz_t u, const mpz_t v)
+{
+  int sign;
+  mp_size_t un, vn, rn;
+  mpz_t t;
+  mp_ptr tp;
+
+  un = u->_mp_size;
+  vn = v->_mp_size;
+
+  if (un == 0 || vn == 0)
+    {
+      r->_mp_size = 0;
+      return;
+    }
+
+  sign = (un ^ vn) < 0;
+
+  un = GMP_ABS (un);
+  vn = GMP_ABS (vn);
+
+  mpz_init2 (t, (un + vn) * GMP_LIMB_BITS);
+
+  tp = t->_mp_d;
+  if (un >= vn)
+    mpn_mul (tp, u->_mp_d, un, v->_mp_d, vn);
+  else
+    mpn_mul (tp, v->_mp_d, vn, u->_mp_d, un);
+
+  rn = un + vn;
+  rn -= tp[rn-1] == 0;
+
+  t->_mp_size = sign ? - rn : rn;
+  mpz_swap (r, t);
+  mpz_clear (t);
+}
+
+void
+mpz_mul_2exp (mpz_t r, const mpz_t u, mp_bitcnt_t bits)
+{
+  mp_size_t un, rn;
+  mp_size_t limbs;
+  unsigned shift;
+  mp_ptr rp;
+
+  un = GMP_ABS (u->_mp_size);
+  if (un == 0)
+    {
+      r->_mp_size = 0;
+      return;
+    }
+
+  limbs = bits / GMP_LIMB_BITS;
+  shift = bits % GMP_LIMB_BITS;
+
+  rn = un + limbs + (shift > 0);
+  rp = MPZ_REALLOC (r, rn);
+  if (shift > 0)
+    {
+      mp_limb_t cy = mpn_lshift (rp + limbs, u->_mp_d, un, shift);
+      rp[rn-1] = cy;
+      rn -= (cy == 0);
+    }
+  else
+    mpn_copyd (rp + limbs, u->_mp_d, un);
+
+  mpn_zero (rp, limbs);
+
+  r->_mp_size = (u->_mp_size < 0) ? - rn : rn;
+}
+
+void
+mpz_addmul_ui (mpz_t r, const mpz_t u, unsigned long int v)
+{
+  mpz_t t;
+  mpz_init_set_ui (t, v);
+  mpz_mul (t, u, t);
+  mpz_add (r, r, t);
+  mpz_clear (t);
+}
+
+void
+mpz_submul_ui (mpz_t r, const mpz_t u, unsigned long int v)
+{
+  mpz_t t;
+  mpz_init_set_ui (t, v);
+  mpz_mul (t, u, t);
+  mpz_sub (r, r, t);
+  mpz_clear (t);
+}
+
+void
+mpz_addmul (mpz_t r, const mpz_t u, const mpz_t v)
+{
+  mpz_t t;
+  mpz_init (t);
+  mpz_mul (t, u, v);
+  mpz_add (r, r, t);
+  mpz_clear (t);
+}
+
+void
+mpz_submul (mpz_t r, const mpz_t u, const mpz_t v)
+{
+  mpz_t t;
+  mpz_init (t);
+  mpz_mul (t, u, v);
+  mpz_sub (r, r, t);
+  mpz_clear (t);
+}
+
+
+/* MPZ division */
+enum mpz_div_round_mode { GMP_DIV_FLOOR, GMP_DIV_CEIL, GMP_DIV_TRUNC };
+
+/* Allows q or r to be zero. Returns 1 iff remainder is non-zero. */
+static int
+mpz_div_qr (mpz_t q, mpz_t r,
+	    const mpz_t n, const mpz_t d, enum mpz_div_round_mode mode)
+{
+  mp_size_t ns, ds, nn, dn, qs;
+  ns = n->_mp_size;
+  ds = d->_mp_size;
+
+  if (ds == 0)
+    gmp_die("mpz_div_qr: Divide by zero.");
+
+  if (ns == 0)
+    {
+      if (q)
+	q->_mp_size = 0;
+      if (r)
+	r->_mp_size = 0;
+      return 0;
+    }
+
+  nn = GMP_ABS (ns);
+  dn = GMP_ABS (ds);
+
+  qs = ds ^ ns;
+
+  if (nn < dn)
+    {
+      if (mode == GMP_DIV_CEIL && qs >= 0)
+	{
+	  /* q = 1, r = n - d */
+	  if (r)
+	    mpz_sub (r, n, d);
+	  if (q)
+	    mpz_set_ui (q, 1);
+	}
+      else if (mode == GMP_DIV_FLOOR && qs < 0)
+	{
+	  /* q = -1, r = n + d */
+	  if (r)
+	    mpz_add (r, n, d);
+	  if (q)
+	    mpz_set_si (q, -1);
+	}
+      else
+	{
+	  /* q = 0, r = d */
+	  if (r)
+	    mpz_set (r, n);
+	  if (q)
+	    q->_mp_size = 0;
+	}
+      return 1;
+    }
+  else
+    {
+      mp_ptr np, qp;
+      mp_size_t qn, rn;
+      mpz_t tq, tr;
+
+      mpz_init_set (tr, n);
+      np = tr->_mp_d;
+
+      qn = nn - dn + 1;
+
+      if (q)
+	{
+	  mpz_init2 (tq, qn * GMP_LIMB_BITS);
+	  qp = tq->_mp_d;
+	}
+      else
+	qp = NULL;
+
+      mpn_div_qr (qp, np, nn, d->_mp_d, dn);
+
+      if (qp)
+	{
+	  qn -= (qp[qn-1] == 0);
+
+	  tq->_mp_size = qs < 0 ? -qn : qn;
+	}
+      rn = mpn_normalized_size (np, dn);
+      tr->_mp_size = ns < 0 ? - rn : rn;
+
+      if (mode == GMP_DIV_FLOOR && qs < 0 && rn != 0)
+	{
+	  if (q)
+	    mpz_sub_ui (tq, tq, 1);
+	  if (r)
+	    mpz_add (tr, tr, d);
+	}
+      else if (mode == GMP_DIV_CEIL && qs >= 0 && rn != 0)
+	{
+	  if (q)
+	    mpz_add_ui (tq, tq, 1);
+	  if (r)
+	    mpz_sub (tr, tr, d);
+	}
+
+      if (q)
+	{
+	  mpz_swap (tq, q);
+	  mpz_clear (tq);
+	}
+      if (r)
+	mpz_swap (tr, r);
+
+      mpz_clear (tr);
+
+      return rn != 0;
+    }
+}
+
+void
+mpz_cdiv_qr (mpz_t q, mpz_t r, const mpz_t n, const mpz_t d)
+{
+  mpz_div_qr (q, r, n, d, GMP_DIV_CEIL);
+}
+
+void
+mpz_fdiv_qr (mpz_t q, mpz_t r, const mpz_t n, const mpz_t d)
+{
+  mpz_div_qr (q, r, n, d, GMP_DIV_FLOOR);
+}
+
+void
+mpz_tdiv_qr (mpz_t q, mpz_t r, const mpz_t n, const mpz_t d)
+{
+  mpz_div_qr (q, r, n, d, GMP_DIV_TRUNC);
+}
+
+void
+mpz_cdiv_q (mpz_t q, const mpz_t n, const mpz_t d)
+{
+  mpz_div_qr (q, NULL, n, d, GMP_DIV_CEIL);
+}
+
+void
+mpz_fdiv_q (mpz_t q, const mpz_t n, const mpz_t d)
+{
+  mpz_div_qr (q, NULL, n, d, GMP_DIV_FLOOR);
+}
+
+void
+mpz_tdiv_q (mpz_t q, const mpz_t n, const mpz_t d)
+{
+  mpz_div_qr (q, NULL, n, d, GMP_DIV_TRUNC);
+}
+
+void
+mpz_cdiv_r (mpz_t r, const mpz_t n, const mpz_t d)
+{
+  mpz_div_qr (NULL, r, n, d, GMP_DIV_CEIL);
+}
+
+void
+mpz_fdiv_r (mpz_t r, const mpz_t n, const mpz_t d)
+{
+  mpz_div_qr (NULL, r, n, d, GMP_DIV_FLOOR);
+}
+
+void
+mpz_tdiv_r (mpz_t r, const mpz_t n, const mpz_t d)
+{
+  mpz_div_qr (NULL, r, n, d, GMP_DIV_TRUNC);
+}
+
+void
+mpz_mod (mpz_t r, const mpz_t n, const mpz_t d)
+{
+  mpz_div_qr (NULL, r, n, d, d->_mp_size >= 0 ? GMP_DIV_FLOOR : GMP_DIV_CEIL);
+}
+
+static void
+mpz_div_q_2exp (mpz_t q, const mpz_t u, mp_bitcnt_t bit_index,
+		enum mpz_div_round_mode mode)
+{
+  mp_size_t un, qn;
+  mp_size_t limb_cnt;
+  mp_ptr qp;
+  int adjust;
+
+  un = u->_mp_size;
+  if (un == 0)
+    {
+      q->_mp_size = 0;
+      return;
+    }
+  limb_cnt = bit_index / GMP_LIMB_BITS;
+  qn = GMP_ABS (un) - limb_cnt;
+  bit_index %= GMP_LIMB_BITS;
+
+  if (mode == ((un > 0) ? GMP_DIV_CEIL : GMP_DIV_FLOOR)) /* un != 0 here. */
+    /* Note: Below, the final indexing at limb_cnt is valid because at
+       that point we have qn > 0. */
+    adjust = (qn <= 0
+	      || !mpn_zero_p (u->_mp_d, limb_cnt)
+	      || (u->_mp_d[limb_cnt]
+		  & (((mp_limb_t) 1 << bit_index) - 1)));
+  else
+    adjust = 0;
+
+  if (qn <= 0)
+    qn = 0;
+  else
+    {
+      qp = MPZ_REALLOC (q, qn);
+
+      if (bit_index != 0)
+	{
+	  mpn_rshift (qp, u->_mp_d + limb_cnt, qn, bit_index);
+	  qn -= qp[qn - 1] == 0;
+	}
+      else
+	{
+	  mpn_copyi (qp, u->_mp_d + limb_cnt, qn);
+	}
+    }
+
+  q->_mp_size = qn;
+
+  if (adjust)
+    mpz_add_ui (q, q, 1);
+  if (un < 0)
+    mpz_neg (q, q);
+}
+
+static void
+mpz_div_r_2exp (mpz_t r, const mpz_t u, mp_bitcnt_t bit_index,
+		enum mpz_div_round_mode mode)
+{
+  mp_size_t us, un, rn;
+  mp_ptr rp;
+  mp_limb_t mask;
+
+  us = u->_mp_size;
+  if (us == 0 || bit_index == 0)
+    {
+      r->_mp_size = 0;
+      return;
+    }
+  rn = (bit_index + GMP_LIMB_BITS - 1) / GMP_LIMB_BITS;
+  assert (rn > 0);
+
+  rp = MPZ_REALLOC (r, rn);
+  un = GMP_ABS (us);
+
+  mask = GMP_LIMB_MAX >> (rn * GMP_LIMB_BITS - bit_index);
+
+  if (rn > un)
+    {
+      /* Quotient (with truncation) is zero, and remainder is
+	 non-zero */
+      if (mode == ((us > 0) ? GMP_DIV_CEIL : GMP_DIV_FLOOR)) /* us != 0 here. */
+	{
+	  /* Have to negate and sign extend. */
+	  mp_size_t i;
+
+	  gmp_assert_nocarry (! mpn_neg (rp, u->_mp_d, un));
+	  for (i = un; i < rn - 1; i++)
+	    rp[i] = GMP_LIMB_MAX;
+
+	  rp[rn-1] = mask;
+	  us = -us;
+	}
+      else
+	{
+	  /* Just copy */
+	  if (r != u)
+	    mpn_copyi (rp, u->_mp_d, un);
+
+	  rn = un;
+	}
+    }
+  else
+    {
+      if (r != u)
+	mpn_copyi (rp, u->_mp_d, rn - 1);
+
+      rp[rn-1] = u->_mp_d[rn-1] & mask;
+
+      if (mode == ((us > 0) ? GMP_DIV_CEIL : GMP_DIV_FLOOR)) /* us != 0 here. */
+	{
+	  /* If r != 0, compute 2^{bit_count} - r. */
+	  mpn_neg (rp, rp, rn);
+
+	  rp[rn-1] &= mask;
+
+	  /* us is not used for anything else, so we can modify it
+	     here to indicate flipped sign. */
+	  us = -us;
+	}
+    }
+  rn = mpn_normalized_size (rp, rn);
+  r->_mp_size = us < 0 ? -rn : rn;
+}
+
+void
+mpz_cdiv_q_2exp (mpz_t r, const mpz_t u, mp_bitcnt_t cnt)
+{
+  mpz_div_q_2exp (r, u, cnt, GMP_DIV_CEIL);
+}
+
+void
+mpz_fdiv_q_2exp (mpz_t r, const mpz_t u, mp_bitcnt_t cnt)
+{
+  mpz_div_q_2exp (r, u, cnt, GMP_DIV_FLOOR);
+}
+
+void
+mpz_tdiv_q_2exp (mpz_t r, const mpz_t u, mp_bitcnt_t cnt)
+{
+  mpz_div_q_2exp (r, u, cnt, GMP_DIV_TRUNC);
+}
+
+void
+mpz_cdiv_r_2exp (mpz_t r, const mpz_t u, mp_bitcnt_t cnt)
+{
+  mpz_div_r_2exp (r, u, cnt, GMP_DIV_CEIL);
+}
+
+void
+mpz_fdiv_r_2exp (mpz_t r, const mpz_t u, mp_bitcnt_t cnt)
+{
+  mpz_div_r_2exp (r, u, cnt, GMP_DIV_FLOOR);
+}
+
+void
+mpz_tdiv_r_2exp (mpz_t r, const mpz_t u, mp_bitcnt_t cnt)
+{
+  mpz_div_r_2exp (r, u, cnt, GMP_DIV_TRUNC);
+}
+
+void
+mpz_divexact (mpz_t q, const mpz_t n, const mpz_t d)
+{
+  gmp_assert_nocarry (mpz_div_qr (q, NULL, n, d, GMP_DIV_TRUNC));
+}
+
+int
+mpz_divisible_p (const mpz_t n, const mpz_t d)
+{
+  return mpz_div_qr (NULL, NULL, n, d, GMP_DIV_TRUNC) == 0;
+}
+
+int
+mpz_congruent_p (const mpz_t a, const mpz_t b, const mpz_t m)
+{
+  mpz_t t;
+  int res;
+
+  /* a == b (mod 0) iff a == b */
+  if (mpz_sgn (m) == 0)
+    return (mpz_cmp (a, b) == 0);
+
+  mpz_init (t);
+  mpz_sub (t, a, b);
+  res = mpz_divisible_p (t, m);
+  mpz_clear (t);
+
+  return res;
+}
+
+static unsigned long
+mpz_div_qr_ui (mpz_t q, mpz_t r,
+	       const mpz_t n, unsigned long d, enum mpz_div_round_mode mode)
+{
+  unsigned long ret;
+  mpz_t rr, dd;
+
+  mpz_init (rr);
+  mpz_init_set_ui (dd, d);
+  mpz_div_qr (q, rr, n, dd, mode);
+  mpz_clear (dd);
+  ret = mpz_get_ui (rr);
+
+  if (r)
+    mpz_swap (r, rr);
+  mpz_clear (rr);
+
+  return ret;
+}
+
+unsigned long
+mpz_cdiv_qr_ui (mpz_t q, mpz_t r, const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (q, r, n, d, GMP_DIV_CEIL);
+}
+
+unsigned long
+mpz_fdiv_qr_ui (mpz_t q, mpz_t r, const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (q, r, n, d, GMP_DIV_FLOOR);
+}
+
+unsigned long
+mpz_tdiv_qr_ui (mpz_t q, mpz_t r, const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (q, r, n, d, GMP_DIV_TRUNC);
+}
+
+unsigned long
+mpz_cdiv_q_ui (mpz_t q, const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (q, NULL, n, d, GMP_DIV_CEIL);
+}
+
+unsigned long
+mpz_fdiv_q_ui (mpz_t q, const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (q, NULL, n, d, GMP_DIV_FLOOR);
+}
+
+unsigned long
+mpz_tdiv_q_ui (mpz_t q, const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (q, NULL, n, d, GMP_DIV_TRUNC);
+}
+
+unsigned long
+mpz_cdiv_r_ui (mpz_t r, const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (NULL, r, n, d, GMP_DIV_CEIL);
+}
+unsigned long
+mpz_fdiv_r_ui (mpz_t r, const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (NULL, r, n, d, GMP_DIV_FLOOR);
+}
+unsigned long
+mpz_tdiv_r_ui (mpz_t r, const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (NULL, r, n, d, GMP_DIV_TRUNC);
+}
+
+unsigned long
+mpz_cdiv_ui (const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (NULL, NULL, n, d, GMP_DIV_CEIL);
+}
+
+unsigned long
+mpz_fdiv_ui (const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (NULL, NULL, n, d, GMP_DIV_FLOOR);
+}
+
+unsigned long
+mpz_tdiv_ui (const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (NULL, NULL, n, d, GMP_DIV_TRUNC);
+}
+
+unsigned long
+mpz_mod_ui (mpz_t r, const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (NULL, r, n, d, GMP_DIV_FLOOR);
+}
+
+void
+mpz_divexact_ui (mpz_t q, const mpz_t n, unsigned long d)
+{
+  gmp_assert_nocarry (mpz_div_qr_ui (q, NULL, n, d, GMP_DIV_TRUNC));
+}
+
+int
+mpz_divisible_ui_p (const mpz_t n, unsigned long d)
+{
+  return mpz_div_qr_ui (NULL, NULL, n, d, GMP_DIV_TRUNC) == 0;
+}
+
+
+/* GCD */
+static mp_limb_t
+mpn_gcd_11 (mp_limb_t u, mp_limb_t v)
+{
+  unsigned shift;
+
+  assert ( (u | v) > 0);
+
+  if (u == 0)
+    return v;
+  else if (v == 0)
+    return u;
+
+  gmp_ctz (shift, u | v);
+
+  u >>= shift;
+  v >>= shift;
+
+  if ( (u & 1) == 0)
+    MP_LIMB_T_SWAP (u, v);
+
+  while ( (v & 1) == 0)
+    v >>= 1;
+
+  while (u != v)
+    {
+      if (u > v)
+	{
+	  u -= v;
+	  do
+	    u >>= 1;
+	  while ( (u & 1) == 0);
+	}
+      else
+	{
+	  v -= u;
+	  do
+	    v >>= 1;
+	  while ( (v & 1) == 0);
+	}
+    }
+  return u << shift;
+}
+
+unsigned long
+mpz_gcd_ui (mpz_t g, const mpz_t u, unsigned long v)
+{
+  mpz_t t;
+  mpz_init_set_ui(t, v);
+  mpz_gcd (t, u, t);
+  if (v > 0)
+    v = mpz_get_ui (t);
+
+  if (g)
+    mpz_swap (t, g);
+
+  mpz_clear (t);
+
+  return v;
+}
+
+static mp_bitcnt_t
+mpz_make_odd (mpz_t r)
+{
+  mp_bitcnt_t shift;
+
+  assert (r->_mp_size > 0);
+  /* Count trailing zeros, equivalent to mpn_scan1, because we know that there is a 1 */
+  shift = mpn_common_scan (r->_mp_d[0], 0, r->_mp_d, 0, 0);
+  mpz_tdiv_q_2exp (r, r, shift);
+
+  return shift;
+}
+
+void
+mpz_gcd (mpz_t g, const mpz_t u, const mpz_t v)
+{
+  mpz_t tu, tv;
+  mp_bitcnt_t uz, vz, gz;
+
+  if (u->_mp_size == 0)
+    {
+      mpz_abs (g, v);
+      return;
+    }
+  if (v->_mp_size == 0)
+    {
+      mpz_abs (g, u);
+      return;
+    }
+
+  mpz_init (tu);
+  mpz_init (tv);
+
+  mpz_abs (tu, u);
+  uz = mpz_make_odd (tu);
+  mpz_abs (tv, v);
+  vz = mpz_make_odd (tv);
+  gz = GMP_MIN (uz, vz);
+
+  if (tu->_mp_size < tv->_mp_size)
+    mpz_swap (tu, tv);
+
+  mpz_tdiv_r (tu, tu, tv);
+  if (tu->_mp_size == 0)
+    {
+      mpz_swap (g, tv);
+    }
+  else
+    for (;;)
+      {
+	int c;
+
+	mpz_make_odd (tu);
+	c = mpz_cmp (tu, tv);
+	if (c == 0)
+	  {
+	    mpz_swap (g, tu);
+	    break;
+	  }
+	if (c < 0)
+	  mpz_swap (tu, tv);
+
+	if (tv->_mp_size == 1)
+	  {
+	    mp_limb_t vl = tv->_mp_d[0];
+	    mp_limb_t ul = mpz_tdiv_ui (tu, vl);
+	    mpz_set_ui (g, mpn_gcd_11 (ul, vl));
+	    break;
+	  }
+	mpz_sub (tu, tu, tv);
+      }
+  mpz_clear (tu);
+  mpz_clear (tv);
+  mpz_mul_2exp (g, g, gz);
+}
+
+void
+mpz_gcdext (mpz_t g, mpz_t s, mpz_t t, const mpz_t u, const mpz_t v)
+{
+  mpz_t tu, tv, s0, s1, t0, t1;
+  mp_bitcnt_t uz, vz, gz;
+  mp_bitcnt_t power;
+
+  if (u->_mp_size == 0)
+    {
+      /* g = 0 u + sgn(v) v */
+      signed long sign = mpz_sgn (v);
+      mpz_abs (g, v);
+      if (s)
+	s->_mp_size = 0;
+      if (t)
+	mpz_set_si (t, sign);
+      return;
+    }
+
+  if (v->_mp_size == 0)
+    {
+      /* g = sgn(u) u + 0 v */
+      signed long sign = mpz_sgn (u);
+      mpz_abs (g, u);
+      if (s)
+	mpz_set_si (s, sign);
+      if (t)
+	t->_mp_size = 0;
+      return;
+    }
+
+  mpz_init (tu);
+  mpz_init (tv);
+  mpz_init (s0);
+  mpz_init (s1);
+  mpz_init (t0);
+  mpz_init (t1);
+
+  mpz_abs (tu, u);
+  uz = mpz_make_odd (tu);
+  mpz_abs (tv, v);
+  vz = mpz_make_odd (tv);
+  gz = GMP_MIN (uz, vz);
+
+  uz -= gz;
+  vz -= gz;
+
+  /* Cofactors corresponding to odd gcd. gz handled later. */
+  if (tu->_mp_size < tv->_mp_size)
+    {
+      mpz_swap (tu, tv);
+      MPZ_SRCPTR_SWAP (u, v);
+      MPZ_PTR_SWAP (s, t);
+      MP_BITCNT_T_SWAP (uz, vz);
+    }
+
+  /* Maintain
+   *
+   * u = t0 tu + t1 tv
+   * v = s0 tu + s1 tv
+   *
+   * where u and v denote the inputs with common factors of two
+   * eliminated, and det (s0, t0; s1, t1) = 2^p. Then
+   *
+   * 2^p tu =  s1 u - t1 v
+   * 2^p tv = -s0 u + t0 v
+   */
+
+  /* After initial division, tu = q tv + tu', we have
+   *
+   * u = 2^uz (tu' + q tv)
+   * v = 2^vz tv
+   *
+   * or
+   *
+   * t0 = 2^uz, t1 = 2^uz q
+   * s0 = 0,    s1 = 2^vz
+   */
+
+  mpz_setbit (t0, uz);
+  mpz_tdiv_qr (t1, tu, tu, tv);
+  mpz_mul_2exp (t1, t1, uz);
+
+  mpz_setbit (s1, vz);
+  power = uz + vz;
+
+  if (tu->_mp_size > 0)
+    {
+      mp_bitcnt_t shift;
+      shift = mpz_make_odd (tu);
+      mpz_mul_2exp (t0, t0, shift);
+      mpz_mul_2exp (s0, s0, shift);
+      power += shift;
+
+      for (;;)
+	{
+	  int c;
+	  c = mpz_cmp (tu, tv);
+	  if (c == 0)
+	    break;
+
+	  if (c < 0)
+	    {
+	      /* tv = tv' + tu
+	       *
+	       * u = t0 tu + t1 (tv' + tu) = (t0 + t1) tu + t1 tv'
+	       * v = s0 tu + s1 (tv' + tu) = (s0 + s1) tu + s1 tv' */
+
+	      mpz_sub (tv, tv, tu);
+	      mpz_add (t0, t0, t1);
+	      mpz_add (s0, s0, s1);
+
+	      shift = mpz_make_odd (tv);
+	      mpz_mul_2exp (t1, t1, shift);
+	      mpz_mul_2exp (s1, s1, shift);
+	    }
+	  else
+	    {
+	      mpz_sub (tu, tu, tv);
+	      mpz_add (t1, t0, t1);
+	      mpz_add (s1, s0, s1);
+
+	      shift = mpz_make_odd (tu);
+	      mpz_mul_2exp (t0, t0, shift);
+	      mpz_mul_2exp (s0, s0, shift);
+	    }
+	  power += shift;
+	}
+    }
+
+  /* Now tv = odd part of gcd, and -s0 and t0 are corresponding
+     cofactors. */
+
+  mpz_mul_2exp (tv, tv, gz);
+  mpz_neg (s0, s0);
+
+  /* 2^p g = s0 u + t0 v. Eliminate one factor of two at a time. To
+     adjust cofactors, we need u / g and v / g */
+
+  mpz_divexact (s1, v, tv);
+  mpz_abs (s1, s1);
+  mpz_divexact (t1, u, tv);
+  mpz_abs (t1, t1);
+
+  while (power-- > 0)
+    {
+      /* s0 u + t0 v = (s0 - v/g) u - (t0 + u/g) v */
+      if (mpz_odd_p (s0) || mpz_odd_p (t0))
+	{
+	  mpz_sub (s0, s0, s1);
+	  mpz_add (t0, t0, t1);
+	}
+      assert (mpz_even_p (t0) && mpz_even_p (s0));
+      mpz_tdiv_q_2exp (s0, s0, 1);
+      mpz_tdiv_q_2exp (t0, t0, 1);
+    }
+
+  /* Arrange so that |s| < |u| / 2g */
+  mpz_add (s1, s0, s1);
+  if (mpz_cmpabs (s0, s1) > 0)
+    {
+      mpz_swap (s0, s1);
+      mpz_sub (t0, t0, t1);
+    }
+  if (u->_mp_size < 0)
+    mpz_neg (s0, s0);
+  if (v->_mp_size < 0)
+    mpz_neg (t0, t0);
+
+  mpz_swap (g, tv);
+  if (s)
+    mpz_swap (s, s0);
+  if (t)
+    mpz_swap (t, t0);
+
+  mpz_clear (tu);
+  mpz_clear (tv);
+  mpz_clear (s0);
+  mpz_clear (s1);
+  mpz_clear (t0);
+  mpz_clear (t1);
+}
+
+void
+mpz_lcm (mpz_t r, const mpz_t u, const mpz_t v)
+{
+  mpz_t g;
+
+  if (u->_mp_size == 0 || v->_mp_size == 0)
+    {
+      r->_mp_size = 0;
+      return;
+    }
+
+  mpz_init (g);
+
+  mpz_gcd (g, u, v);
+  mpz_divexact (g, u, g);
+  mpz_mul (r, g, v);
+
+  mpz_clear (g);
+  mpz_abs (r, r);
+}
+
+void
+mpz_lcm_ui (mpz_t r, const mpz_t u, unsigned long v)
+{
+  if (v == 0 || u->_mp_size == 0)
+    {
+      r->_mp_size = 0;
+      return;
+    }
+
+  v /= mpz_gcd_ui (NULL, u, v);
+  mpz_mul_ui (r, u, v);
+
+  mpz_abs (r, r);
+}
+
+int
+mpz_invert (mpz_t r, const mpz_t u, const mpz_t m)
+{
+  mpz_t g, tr;
+  int invertible;
+
+  if (u->_mp_size == 0 || mpz_cmpabs_ui (m, 1) <= 0)
+    return 0;
+
+  mpz_init (g);
+  mpz_init (tr);
+
+  mpz_gcdext (g, tr, NULL, u, m);
+  invertible = (mpz_cmp_ui (g, 1) == 0);
+
+  if (invertible)
+    {
+      if (tr->_mp_size < 0)
+	{
+	  if (m->_mp_size >= 0)
+	    mpz_add (tr, tr, m);
+	  else
+	    mpz_sub (tr, tr, m);
+	}
+      mpz_swap (r, tr);
+    }
+
+  mpz_clear (g);
+  mpz_clear (tr);
+  return invertible;
+}
+
+
+/* Higher level operations (sqrt, pow and root) */
+
+void
+mpz_pow_ui (mpz_t r, const mpz_t b, unsigned long e)
+{
+  unsigned long bit;
+  mpz_t tr;
+  mpz_init_set_ui (tr, 1);
+
+  bit = GMP_ULONG_HIGHBIT;
+  do
+    {
+      mpz_mul (tr, tr, tr);
+      if (e & bit)
+	mpz_mul (tr, tr, b);
+      bit >>= 1;
+    }
+  while (bit > 0);
+
+  mpz_swap (r, tr);
+  mpz_clear (tr);
+}
+
+void
+mpz_ui_pow_ui (mpz_t r, unsigned long blimb, unsigned long e)
+{
+  mpz_t b;
+
+  mpz_init_set_ui (b, blimb);
+  mpz_pow_ui (r, b, e);
+  mpz_clear (b);
+}
+
+void
+mpz_powm (mpz_t r, const mpz_t b, const mpz_t e, const mpz_t m)
+{
+  mpz_t tr;
+  mpz_t base;
+  mp_size_t en, mn;
+  mp_srcptr mp;
+  struct gmp_div_inverse minv;
+  unsigned shift;
+  mp_ptr tp = NULL;
+
+  en = GMP_ABS (e->_mp_size);
+  mn = GMP_ABS (m->_mp_size);
+  if (mn == 0)
+    gmp_die ("mpz_powm: Zero modulo.");
+
+  if (en == 0)
+    {
+      mpz_set_ui (r, 1);
+      return;
+    }
+
+  mp = m->_mp_d;
+  mpn_div_qr_invert (&minv, mp, mn);
+  shift = minv.shift;
+
+  if (shift > 0)
+    {
+      /* To avoid shifts, we do all our reductions, except the final
+	 one, using a *normalized* m. */
+      minv.shift = 0;
+
+      tp = gmp_xalloc_limbs (mn);
+      gmp_assert_nocarry (mpn_lshift (tp, mp, mn, shift));
+      mp = tp;
+    }
+
+  mpz_init (base);
+
+  if (e->_mp_size < 0)
+    {
+      if (!mpz_invert (base, b, m))
+	gmp_die ("mpz_powm: Negative exponent and non-invertible base.");
+    }
+  else
+    {
+      mp_size_t bn;
+      mpz_abs (base, b);
+
+      bn = base->_mp_size;
+      if (bn >= mn)
+	{
+	  mpn_div_qr_preinv (NULL, base->_mp_d, base->_mp_size, mp, mn, &minv);
+	  bn = mn;
+	}
+
+      /* We have reduced the absolute value. Now take care of the
+	 sign. Note that we get zero represented non-canonically as
+	 m. */
+      if (b->_mp_size < 0)
+	{
+	  mp_ptr bp = MPZ_REALLOC (base, mn);
+	  gmp_assert_nocarry (mpn_sub (bp, mp, mn, bp, bn));
+	  bn = mn;
+	}
+      base->_mp_size = mpn_normalized_size (base->_mp_d, bn);
+    }
+  mpz_init_set_ui (tr, 1);
+
+  while (--en >= 0)
+    {
+      mp_limb_t w = e->_mp_d[en];
+      mp_limb_t bit;
+
+      bit = GMP_LIMB_HIGHBIT;
+      do
+	{
+	  mpz_mul (tr, tr, tr);
+	  if (w & bit)
+	    mpz_mul (tr, tr, base);
+	  if (tr->_mp_size > mn)
+	    {
+	      mpn_div_qr_preinv (NULL, tr->_mp_d, tr->_mp_size, mp, mn, &minv);
+	      tr->_mp_size = mpn_normalized_size (tr->_mp_d, mn);
+	    }
+	  bit >>= 1;
+	}
+      while (bit > 0);
+    }
+
+  /* Final reduction */
+  if (tr->_mp_size >= mn)
+    {
+      minv.shift = shift;
+      mpn_div_qr_preinv (NULL, tr->_mp_d, tr->_mp_size, mp, mn, &minv);
+      tr->_mp_size = mpn_normalized_size (tr->_mp_d, mn);
+    }
+  if (tp)
+    gmp_free (tp);
+
+  mpz_swap (r, tr);
+  mpz_clear (tr);
+  mpz_clear (base);
+}
+
+void
+mpz_powm_ui (mpz_t r, const mpz_t b, unsigned long elimb, const mpz_t m)
+{
+  mpz_t e;
+
+  mpz_init_set_ui (e, elimb);
+  mpz_powm (r, b, e, m);
+  mpz_clear (e);
+}
+
+/* x=trunc(y^(1/z)), r=y-x^z */
+void
+mpz_rootrem (mpz_t x, mpz_t r, const mpz_t y, unsigned long z)
+{
+  int sgn;
+  mpz_t t, u;
+
+  sgn = y->_mp_size < 0;
+  if ((~z & sgn) != 0)
+    gmp_die ("mpz_rootrem: Negative argument, with even root.");
+  if (z == 0)
+    gmp_die ("mpz_rootrem: Zeroth root.");
+
+  if (mpz_cmpabs_ui (y, 1) <= 0) {
+    if (x)
+      mpz_set (x, y);
+    if (r)
+      r->_mp_size = 0;
+    return;
+  }
+
+  mpz_init (u);
+  mpz_init (t);
+  mpz_setbit (t, mpz_sizeinbase (y, 2) / z + 1);
+
+  if (z == 2) /* simplify sqrt loop: z-1 == 1 */
+    do {
+      mpz_swap (u, t);			/* u = x */
+      mpz_tdiv_q (t, y, u);		/* t = y/x */
+      mpz_add (t, t, u);		/* t = y/x + x */
+      mpz_tdiv_q_2exp (t, t, 1);	/* x'= (y/x + x)/2 */
+    } while (mpz_cmpabs (t, u) < 0);	/* |x'| < |x| */
+  else /* z != 2 */ {
+    mpz_t v;
+
+    mpz_init (v);
+    if (sgn)
+      mpz_neg (t, t);
+
+    do {
+      mpz_swap (u, t);			/* u = x */
+      mpz_pow_ui (t, u, z - 1);		/* t = x^(z-1) */
+      mpz_tdiv_q (t, y, t);		/* t = y/x^(z-1) */
+      mpz_mul_ui (v, u, z - 1);		/* v = x*(z-1) */
+      mpz_add (t, t, v);		/* t = y/x^(z-1) + x*(z-1) */
+      mpz_tdiv_q_ui (t, t, z);		/* x'=(y/x^(z-1) + x*(z-1))/z */
+    } while (mpz_cmpabs (t, u) < 0);	/* |x'| < |x| */
+
+    mpz_clear (v);
+  }
+
+  if (r) {
+    mpz_pow_ui (t, u, z);
+    mpz_sub (r, y, t);
+  }
+  if (x)
+    mpz_swap (x, u);
+  mpz_clear (u);
+  mpz_clear (t);
+}
+
+int
+mpz_root (mpz_t x, const mpz_t y, unsigned long z)
+{
+  int res;
+  mpz_t r;
+
+  mpz_init (r);
+  mpz_rootrem (x, r, y, z);
+  res = r->_mp_size == 0;
+  mpz_clear (r);
+
+  return res;
+}
+
+/* Compute s = floor(sqrt(u)) and r = u - s^2. Allows r == NULL */
+void
+mpz_sqrtrem (mpz_t s, mpz_t r, const mpz_t u)
+{
+  mpz_rootrem (s, r, u, 2);
+}
+
+void
+mpz_sqrt (mpz_t s, const mpz_t u)
+{
+  mpz_rootrem (s, NULL, u, 2);
+}
+
+int
+mpz_perfect_square_p (const mpz_t u)
+{
+  if (u->_mp_size <= 0)
+    return (u->_mp_size == 0);
+  else
+    return mpz_root (NULL, u, 2);
+}
+
+int
+mpn_perfect_square_p (mp_srcptr p, mp_size_t n)
+{
+  mpz_t t;
+
+  assert (n > 0);
+  assert (p [n-1] != 0);
+  return mpz_root (NULL, mpz_roinit_normal_n (t, p, n), 2);
+}
+
+mp_size_t
+mpn_sqrtrem (mp_ptr sp, mp_ptr rp, mp_srcptr p, mp_size_t n)
+{
+  mpz_t s, r, u;
+  mp_size_t res;
+
+  assert (n > 0);
+  assert (p [n-1] != 0);
+
+  mpz_init (r);
+  mpz_init (s);
+  mpz_rootrem (s, r, mpz_roinit_normal_n (u, p, n), 2);
+
+  assert (s->_mp_size == (n+1)/2);
+  mpn_copyd (sp, s->_mp_d, s->_mp_size);
+  mpz_clear (s);
+  res = r->_mp_size;
+  if (rp)
+    mpn_copyd (rp, r->_mp_d, res);
+  mpz_clear (r);
+  return res;
+}
+
+/* Combinatorics */
+
+void
+mpz_mfac_uiui (mpz_t x, unsigned long n, unsigned long m)
+{
+  mpz_set_ui (x, n + (n == 0));
+  if (m + 1 < 2) return;
+  while (n > m + 1)
+    mpz_mul_ui (x, x, n -= m);
+}
+
+void
+mpz_2fac_ui (mpz_t x, unsigned long n)
+{
+  mpz_mfac_uiui (x, n, 2);
+}
+
+void
+mpz_fac_ui (mpz_t x, unsigned long n)
+{
+  mpz_mfac_uiui (x, n, 1);
+}
+
+void
+mpz_bin_uiui (mpz_t r, unsigned long n, unsigned long k)
+{
+  mpz_t t;
+
+  mpz_set_ui (r, k <= n);
+
+  if (k > (n >> 1))
+    k = (k <= n) ? n - k : 0;
+
+  mpz_init (t);
+  mpz_fac_ui (t, k);
+
+  for (; k > 0; --k)
+    mpz_mul_ui (r, r, n--);
+
+  mpz_divexact (r, r, t);
+  mpz_clear (t);
+}
+
+
+/* Primality testing */
+
+/* Computes Kronecker (a/b) with odd b, a!=0 and GCD(a,b) = 1 */
+/* Adapted from JACOBI_BASE_METHOD==4 in mpn/generic/jacbase.c */
+static int
+gmp_jacobi_coprime (mp_limb_t a, mp_limb_t b)
+{
+  int c, bit = 0;
+
+  assert (b & 1);
+  assert (a != 0);
+  /* assert (mpn_gcd_11 (a, b) == 1); */
+
+  /* Below, we represent a and b shifted right so that the least
+     significant one bit is implicit. */
+  b >>= 1;
+
+  gmp_ctz(c, a);
+  a >>= 1;
+
+  do
+    {
+      a >>= c;
+      /* (2/b) = -1 if b = 3 or 5 mod 8 */
+      bit ^= c & (b ^ (b >> 1));
+      if (a < b)
+	{
+	  bit ^= a & b;
+	  a = b - a;
+	  b -= a;
+	}
+      else
+	{
+	  a -= b;
+	  assert (a != 0);
+	}
+
+      gmp_ctz(c, a);
+      ++c;
+    }
+  while (b > 0);
+
+  return bit & 1 ? -1 : 1;
+}
+
+static void
+gmp_lucas_step_k_2k (mpz_t V, mpz_t Qk, const mpz_t n)
+{
+  mpz_mod (Qk, Qk, n);
+  /* V_{2k} <- V_k ^ 2 - 2Q^k */
+  mpz_mul (V, V, V);
+  mpz_submul_ui (V, Qk, 2);
+  mpz_tdiv_r (V, V, n);
+  /* Q^{2k} = (Q^k)^2 */
+  mpz_mul (Qk, Qk, Qk);
+}
+
+/* Computes V_k, Q^k (mod n) for the Lucas' sequence */
+/* with P=1, Q=Q; k = (n>>b0)|1. */
+/* Requires an odd n > 4; b0 > 0; -2*Q must not overflow a long */
+/* Returns (U_k == 0) and sets V=V_k and Qk=Q^k. */
+static int
+gmp_lucas_mod (mpz_t V, mpz_t Qk, long Q,
+	       mp_bitcnt_t b0, const mpz_t n)
+{
+  mp_bitcnt_t bs;
+  mpz_t U;
+  int res;
+
+  assert (b0 > 0);
+  assert (Q <= - (LONG_MIN / 2));
+  assert (Q >= - (LONG_MAX / 2));
+  assert (mpz_cmp_ui (n, 4) > 0);
+  assert (mpz_odd_p (n));
+
+  mpz_init_set_ui (U, 1); /* U1 = 1 */
+  mpz_set_ui (V, 1); /* V1 = 1 */
+  mpz_set_si (Qk, Q);
+
+  for (bs = mpz_sizeinbase (n, 2) - 1; --bs >= b0;)
+    {
+      /* U_{2k} <- U_k * V_k */
+      mpz_mul (U, U, V);
+      /* V_{2k} <- V_k ^ 2 - 2Q^k */
+      /* Q^{2k} = (Q^k)^2 */
+      gmp_lucas_step_k_2k (V, Qk, n);
+
+      /* A step k->k+1 is performed if the bit in $n$ is 1	*/
+      /* mpz_tstbit(n,bs) or the the bit is 0 in $n$ but	*/
+      /* should be 1 in $n+1$ (bs == b0)			*/
+      if (b0 == bs || mpz_tstbit (n, bs))
+	{
+	  /* Q^{k+1} <- Q^k * Q */
+	  mpz_mul_si (Qk, Qk, Q);
+	  /* U_{k+1} <- (U_k + V_k) / 2 */
+	  mpz_swap (U, V); /* Keep in V the old value of U_k */
+	  mpz_add (U, U, V);
+	  /* We have to compute U/2, so we need an even value, */
+	  /* equivalent (mod n) */
+	  if (mpz_odd_p (U))
+	    mpz_add (U, U, n);
+	  mpz_tdiv_q_2exp (U, U, 1);
+	  /* V_{k+1} <-(D*U_k + V_k) / 2 =
+			U_{k+1} + (D-1)/2*U_k = U_{k+1} - 2Q*U_k */
+	  mpz_mul_si (V, V, -2*Q);
+	  mpz_add (V, U, V);
+	  mpz_tdiv_r (V, V, n);
+	}
+      mpz_tdiv_r (U, U, n);
+    }
+
+  res = U->_mp_size == 0;
+  mpz_clear (U);
+  return res;
+}
+
+/* Performs strong Lucas' test on x, with parameters suggested */
+/* for the BPSW test. Qk is only passed to recycle a variable. */
+/* Requires GCD (x,6) = 1.*/
+static int
+gmp_stronglucas (const mpz_t x, mpz_t Qk)
+{
+  mp_bitcnt_t b0;
+  mpz_t V, n;
+  mp_limb_t maxD, D; /* The absolute value is stored. */
+  long Q;
+  mp_limb_t tl;
+
+  /* Test on the absolute value. */
+  mpz_roinit_normal_n (n, x->_mp_d, GMP_ABS (x->_mp_size));
+
+  assert (mpz_odd_p (n));
+  /* assert (mpz_gcd_ui (NULL, n, 6) == 1); */
+  if (mpz_root (Qk, n, 2))
+    return 0; /* A square is composite. */
+
+  /* Check Ds up to square root (in case, n is prime)
+     or avoid overflows */
+  maxD = (Qk->_mp_size == 1) ? Qk->_mp_d [0] - 1 : GMP_LIMB_MAX;
+
+  D = 3;
+  /* Search a D such that (D/n) = -1 in the sequence 5,-7,9,-11,.. */
+  /* For those Ds we have (D/n) = (n/|D|) */
+  do
+    {
+      if (D >= maxD)
+	return 1 + (D != GMP_LIMB_MAX); /* (1 + ! ~ D) */
+      D += 2;
+      tl = mpz_tdiv_ui (n, D);
+      if (tl == 0)
+	return 0;
+    }
+  while (gmp_jacobi_coprime (tl, D) == 1);
+
+  mpz_init (V);
+
+  /* n-(D/n) = n+1 = d*2^{b0}, with d = (n>>b0) | 1 */
+  b0 = mpz_scan0 (n, 0);
+
+  /* D= P^2 - 4Q; P = 1; Q = (1-D)/4 */
+  Q = (D & 2) ? (long) (D >> 2) + 1 : -(long) (D >> 2);
+
+  if (! gmp_lucas_mod (V, Qk, Q, b0, n))	/* If Ud != 0 */
+    while (V->_mp_size != 0 && --b0 != 0)	/* while Vk != 0 */
+      /* V <- V ^ 2 - 2Q^k */
+      /* Q^{2k} = (Q^k)^2 */
+      gmp_lucas_step_k_2k (V, Qk, n);
+
+  mpz_clear (V);
+  return (b0 != 0);
+}
+
+static int
+gmp_millerrabin (const mpz_t n, const mpz_t nm1, mpz_t y,
+		 const mpz_t q, mp_bitcnt_t k)
+{
+  assert (k > 0);
+
+  /* Caller must initialize y to the base. */
+  mpz_powm (y, y, q, n);
+
+  if (mpz_cmp_ui (y, 1) == 0 || mpz_cmp (y, nm1) == 0)
+    return 1;
+
+  while (--k > 0)
+    {
+      mpz_powm_ui (y, y, 2, n);
+      if (mpz_cmp (y, nm1) == 0)
+	return 1;
+      /* y == 1 means that the previous y was a non-trivial square root
+	 of 1 (mod n). y == 0 means that n is a power of the base.
+	 In either case, n is not prime. */
+      if (mpz_cmp_ui (y, 1) <= 0)
+	return 0;
+    }
+  return 0;
+}
+
+/* This product is 0xc0cfd797, and fits in 32 bits. */
+#define GMP_PRIME_PRODUCT \
+  (3UL*5UL*7UL*11UL*13UL*17UL*19UL*23UL*29UL)
+
+/* Bit (p+1)/2 is set, for each odd prime <= 61 */
+#define GMP_PRIME_MASK 0xc96996dcUL
+
+int
+mpz_probab_prime_p (const mpz_t n, int reps)
+{
+  mpz_t nm1;
+  mpz_t q;
+  mpz_t y;
+  mp_bitcnt_t k;
+  int is_prime;
+  int j;
+
+  /* Note that we use the absolute value of n only, for compatibility
+     with the real GMP. */
+  if (mpz_even_p (n))
+    return (mpz_cmpabs_ui (n, 2) == 0) ? 2 : 0;
+
+  /* Above test excludes n == 0 */
+  assert (n->_mp_size != 0);
+
+  if (mpz_cmpabs_ui (n, 64) < 0)
+    return (GMP_PRIME_MASK >> (n->_mp_d[0] >> 1)) & 2;
+
+  if (mpz_gcd_ui (NULL, n, GMP_PRIME_PRODUCT) != 1)
+    return 0;
+
+  /* All prime factors are >= 31. */
+  if (mpz_cmpabs_ui (n, 31*31) < 0)
+    return 2;
+
+  mpz_init (nm1);
+  mpz_init (q);
+
+  /* Find q and k, where q is odd and n = 1 + 2**k * q.  */
+  mpz_abs (nm1, n);
+  nm1->_mp_d[0] -= 1;
+  k = mpz_scan1 (nm1, 0);
+  mpz_tdiv_q_2exp (q, nm1, k);
+
+  /* BPSW test */
+  mpz_init_set_ui (y, 2);
+  is_prime = gmp_millerrabin (n, nm1, y, q, k) && gmp_stronglucas (n, y);
+  reps -= 24; /* skip the first 24 repetitions */
+
+  /* Use Miller-Rabin, with a deterministic sequence of bases, a[j] =
+     j^2 + j + 41 using Euler's polynomial. We potentially stop early,
+     if a[j] >= n - 1. Since n >= 31*31, this can happen only if reps >
+     30 (a[30] == 971 > 31*31 == 961). */
+
+  for (j = 0; is_prime & (j < reps); j++)
+    {
+      mpz_set_ui (y, (unsigned long) j*j+j+41);
+      if (mpz_cmp (y, nm1) >= 0)
+	{
+	  /* Don't try any further bases. This "early" break does not affect
+	     the result for any reasonable reps value (<=5000 was tested) */
+	  assert (j >= 30);
+	  break;
+	}
+      is_prime = gmp_millerrabin (n, nm1, y, q, k);
+    }
+  mpz_clear (nm1);
+  mpz_clear (q);
+  mpz_clear (y);
+
+  return is_prime;
+}
+
+
+/* Logical operations and bit manipulation. */
+
+/* Numbers are treated as if represented in two's complement (and
+   infinitely sign extended). For a negative values we get the two's
+   complement from -x = ~x + 1, where ~ is bitwise complement.
+   Negation transforms
+
+     xxxx10...0
+
+   into
+
+     yyyy10...0
+
+   where yyyy is the bitwise complement of xxxx. So least significant
+   bits, up to and including the first one bit, are unchanged, and
+   the more significant bits are all complemented.
+
+   To change a bit from zero to one in a negative number, subtract the
+   corresponding power of two from the absolute value. This can never
+   underflow. To change a bit from one to zero, add the corresponding
+   power of two, and this might overflow. E.g., if x = -001111, the
+   two's complement is 110001. Clearing the least significant bit, we
+   get two's complement 110000, and -010000. */
+
+int
+mpz_tstbit (const mpz_t d, mp_bitcnt_t bit_index)
+{
+  mp_size_t limb_index;
+  unsigned shift;
+  mp_size_t ds;
+  mp_size_t dn;
+  mp_limb_t w;
+  int bit;
+
+  ds = d->_mp_size;
+  dn = GMP_ABS (ds);
+  limb_index = bit_index / GMP_LIMB_BITS;
+  if (limb_index >= dn)
+    return ds < 0;
+
+  shift = bit_index % GMP_LIMB_BITS;
+  w = d->_mp_d[limb_index];
+  bit = (w >> shift) & 1;
+
+  if (ds < 0)
+    {
+      /* d < 0. Check if any of the bits below is set: If so, our bit
+	 must be complemented. */
+      if (shift > 0 && (mp_limb_t) (w << (GMP_LIMB_BITS - shift)) > 0)
+	return bit ^ 1;
+      while (--limb_index >= 0)
+	if (d->_mp_d[limb_index] > 0)
+	  return bit ^ 1;
+    }
+  return bit;
+}
+
+static void
+mpz_abs_add_bit (mpz_t d, mp_bitcnt_t bit_index)
+{
+  mp_size_t dn, limb_index;
+  mp_limb_t bit;
+  mp_ptr dp;
+
+  dn = GMP_ABS (d->_mp_size);
+
+  limb_index = bit_index / GMP_LIMB_BITS;
+  bit = (mp_limb_t) 1 << (bit_index % GMP_LIMB_BITS);
+
+  if (limb_index >= dn)
+    {
+      mp_size_t i;
+      /* The bit should be set outside of the end of the number.
+	 We have to increase the size of the number. */
+      dp = MPZ_REALLOC (d, limb_index + 1);
+
+      dp[limb_index] = bit;
+      for (i = dn; i < limb_index; i++)
+	dp[i] = 0;
+      dn = limb_index + 1;
+    }
+  else
+    {
+      mp_limb_t cy;
+
+      dp = d->_mp_d;
+
+      cy = mpn_add_1 (dp + limb_index, dp + limb_index, dn - limb_index, bit);
+      if (cy > 0)
+	{
+	  dp = MPZ_REALLOC (d, dn + 1);
+	  dp[dn++] = cy;
+	}
+    }
+
+  d->_mp_size = (d->_mp_size < 0) ? - dn : dn;
+}
+
+static void
+mpz_abs_sub_bit (mpz_t d, mp_bitcnt_t bit_index)
+{
+  mp_size_t dn, limb_index;
+  mp_ptr dp;
+  mp_limb_t bit;
+
+  dn = GMP_ABS (d->_mp_size);
+  dp = d->_mp_d;
+
+  limb_index = bit_index / GMP_LIMB_BITS;
+  bit = (mp_limb_t) 1 << (bit_index % GMP_LIMB_BITS);
+
+  assert (limb_index < dn);
+
+  gmp_assert_nocarry (mpn_sub_1 (dp + limb_index, dp + limb_index,
+				 dn - limb_index, bit));
+  dn = mpn_normalized_size (dp, dn);
+  d->_mp_size = (d->_mp_size < 0) ? - dn : dn;
+}
+
+void
+mpz_setbit (mpz_t d, mp_bitcnt_t bit_index)
+{
+  if (!mpz_tstbit (d, bit_index))
+    {
+      if (d->_mp_size >= 0)
+	mpz_abs_add_bit (d, bit_index);
+      else
+	mpz_abs_sub_bit (d, bit_index);
+    }
+}
+
+void
+mpz_clrbit (mpz_t d, mp_bitcnt_t bit_index)
+{
+  if (mpz_tstbit (d, bit_index))
+    {
+      if (d->_mp_size >= 0)
+	mpz_abs_sub_bit (d, bit_index);
+      else
+	mpz_abs_add_bit (d, bit_index);
+    }
+}
+
+void
+mpz_combit (mpz_t d, mp_bitcnt_t bit_index)
+{
+  if (mpz_tstbit (d, bit_index) ^ (d->_mp_size < 0))
+    mpz_abs_sub_bit (d, bit_index);
+  else
+    mpz_abs_add_bit (d, bit_index);
+}
+
+void
+mpz_com (mpz_t r, const mpz_t u)
+{
+  mpz_add_ui (r, u, 1);
+  mpz_neg (r, r);
+}
+
+void
+mpz_and (mpz_t r, const mpz_t u, const mpz_t v)
+{
+  mp_size_t un, vn, rn, i;
+  mp_ptr up, vp, rp;
+
+  mp_limb_t ux, vx, rx;
+  mp_limb_t uc, vc, rc;
+  mp_limb_t ul, vl, rl;
+
+  un = GMP_ABS (u->_mp_size);
+  vn = GMP_ABS (v->_mp_size);
+  if (un < vn)
+    {
+      MPZ_SRCPTR_SWAP (u, v);
+      MP_SIZE_T_SWAP (un, vn);
+    }
+  if (vn == 0)
+    {
+      r->_mp_size = 0;
+      return;
+    }
+
+  uc = u->_mp_size < 0;
+  vc = v->_mp_size < 0;
+  rc = uc & vc;
+
+  ux = -uc;
+  vx = -vc;
+  rx = -rc;
+
+  /* If the smaller input is positive, higher limbs don't matter. */
+  rn = vx ? un : vn;
+
+  rp = MPZ_REALLOC (r, rn + (mp_size_t) rc);
+
+  up = u->_mp_d;
+  vp = v->_mp_d;
+
+  i = 0;
+  do
+    {
+      ul = (up[i] ^ ux) + uc;
+      uc = ul < uc;
+
+      vl = (vp[i] ^ vx) + vc;
+      vc = vl < vc;
+
+      rl = ( (ul & vl) ^ rx) + rc;
+      rc = rl < rc;
+      rp[i] = rl;
+    }
+  while (++i < vn);
+  assert (vc == 0);
+
+  for (; i < rn; i++)
+    {
+      ul = (up[i] ^ ux) + uc;
+      uc = ul < uc;
+
+      rl = ( (ul & vx) ^ rx) + rc;
+      rc = rl < rc;
+      rp[i] = rl;
+    }
+  if (rc)
+    rp[rn++] = rc;
+  else
+    rn = mpn_normalized_size (rp, rn);
+
+  r->_mp_size = rx ? -rn : rn;
+}
+
+void
+mpz_ior (mpz_t r, const mpz_t u, const mpz_t v)
+{
+  mp_size_t un, vn, rn, i;
+  mp_ptr up, vp, rp;
+
+  mp_limb_t ux, vx, rx;
+  mp_limb_t uc, vc, rc;
+  mp_limb_t ul, vl, rl;
+
+  un = GMP_ABS (u->_mp_size);
+  vn = GMP_ABS (v->_mp_size);
+  if (un < vn)
+    {
+      MPZ_SRCPTR_SWAP (u, v);
+      MP_SIZE_T_SWAP (un, vn);
+    }
+  if (vn == 0)
+    {
+      mpz_set (r, u);
+      return;
+    }
+
+  uc = u->_mp_size < 0;
+  vc = v->_mp_size < 0;
+  rc = uc | vc;
+
+  ux = -uc;
+  vx = -vc;
+  rx = -rc;
+
+  /* If the smaller input is negative, by sign extension higher limbs
+     don't matter. */
+  rn = vx ? vn : un;
+
+  rp = MPZ_REALLOC (r, rn + (mp_size_t) rc);
+
+  up = u->_mp_d;
+  vp = v->_mp_d;
+
+  i = 0;
+  do
+    {
+      ul = (up[i] ^ ux) + uc;
+      uc = ul < uc;
+
+      vl = (vp[i] ^ vx) + vc;
+      vc = vl < vc;
+
+      rl = ( (ul | vl) ^ rx) + rc;
+      rc = rl < rc;
+      rp[i] = rl;
+    }
+  while (++i < vn);
+  assert (vc == 0);
+
+  for (; i < rn; i++)
+    {
+      ul = (up[i] ^ ux) + uc;
+      uc = ul < uc;
+
+      rl = ( (ul | vx) ^ rx) + rc;
+      rc = rl < rc;
+      rp[i] = rl;
+    }
+  if (rc)
+    rp[rn++] = rc;
+  else
+    rn = mpn_normalized_size (rp, rn);
+
+  r->_mp_size = rx ? -rn : rn;
+}
+
+void
+mpz_xor (mpz_t r, const mpz_t u, const mpz_t v)
+{
+  mp_size_t un, vn, i;
+  mp_ptr up, vp, rp;
+
+  mp_limb_t ux, vx, rx;
+  mp_limb_t uc, vc, rc;
+  mp_limb_t ul, vl, rl;
+
+  un = GMP_ABS (u->_mp_size);
+  vn = GMP_ABS (v->_mp_size);
+  if (un < vn)
+    {
+      MPZ_SRCPTR_SWAP (u, v);
+      MP_SIZE_T_SWAP (un, vn);
+    }
+  if (vn == 0)
+    {
+      mpz_set (r, u);
+      return;
+    }
+
+  uc = u->_mp_size < 0;
+  vc = v->_mp_size < 0;
+  rc = uc ^ vc;
+
+  ux = -uc;
+  vx = -vc;
+  rx = -rc;
+
+  rp = MPZ_REALLOC (r, un + (mp_size_t) rc);
+
+  up = u->_mp_d;
+  vp = v->_mp_d;
+
+  i = 0;
+  do
+    {
+      ul = (up[i] ^ ux) + uc;
+      uc = ul < uc;
+
+      vl = (vp[i] ^ vx) + vc;
+      vc = vl < vc;
+
+      rl = (ul ^ vl ^ rx) + rc;
+      rc = rl < rc;
+      rp[i] = rl;
+    }
+  while (++i < vn);
+  assert (vc == 0);
+
+  for (; i < un; i++)
+    {
+      ul = (up[i] ^ ux) + uc;
+      uc = ul < uc;
+
+      rl = (ul ^ ux) + rc;
+      rc = rl < rc;
+      rp[i] = rl;
+    }
+  if (rc)
+    rp[un++] = rc;
+  else
+    un = mpn_normalized_size (rp, un);
+
+  r->_mp_size = rx ? -un : un;
+}
+
+static unsigned
+gmp_popcount_limb (mp_limb_t x)
+{
+  unsigned c;
+
+  /* Do 16 bits at a time, to avoid limb-sized constants. */
+  int LOCAL_SHIFT_BITS = 16;
+  for (c = 0; x > 0;)
+    {
+      unsigned w = x - ((x >> 1) & 0x5555);
+      w = ((w >> 2) & 0x3333) + (w & 0x3333);
+      w =  (w >> 4) + w;
+      w = ((w >> 8) & 0x000f) + (w & 0x000f);
+      c += w;
+      if (GMP_LIMB_BITS > LOCAL_SHIFT_BITS)
+	x >>= LOCAL_SHIFT_BITS;
+      else
+	x = 0;
+    }
+  return c;
+}
+
+mp_bitcnt_t
+mpn_popcount (mp_srcptr p, mp_size_t n)
+{
+  mp_size_t i;
+  mp_bitcnt_t c;
+
+  for (c = 0, i = 0; i < n; i++)
+    c += gmp_popcount_limb (p[i]);
+
+  return c;
+}
+
+mp_bitcnt_t
+mpz_popcount (const mpz_t u)
+{
+  mp_size_t un;
+
+  un = u->_mp_size;
+
+  if (un < 0)
+    return ~(mp_bitcnt_t) 0;
+
+  return mpn_popcount (u->_mp_d, un);
+}
+
+mp_bitcnt_t
+mpz_hamdist (const mpz_t u, const mpz_t v)
+{
+  mp_size_t un, vn, i;
+  mp_limb_t uc, vc, ul, vl, comp;
+  mp_srcptr up, vp;
+  mp_bitcnt_t c;
+
+  un = u->_mp_size;
+  vn = v->_mp_size;
+
+  if ( (un ^ vn) < 0)
+    return ~(mp_bitcnt_t) 0;
+
+  comp = - (uc = vc = (un < 0));
+  if (uc)
+    {
+      assert (vn < 0);
+      un = -un;
+      vn = -vn;
+    }
+
+  up = u->_mp_d;
+  vp = v->_mp_d;
+
+  if (un < vn)
+    MPN_SRCPTR_SWAP (up, un, vp, vn);
+
+  for (i = 0, c = 0; i < vn; i++)
+    {
+      ul = (up[i] ^ comp) + uc;
+      uc = ul < uc;
+
+      vl = (vp[i] ^ comp) + vc;
+      vc = vl < vc;
+
+      c += gmp_popcount_limb (ul ^ vl);
+    }
+  assert (vc == 0);
+
+  for (; i < un; i++)
+    {
+      ul = (up[i] ^ comp) + uc;
+      uc = ul < uc;
+
+      c += gmp_popcount_limb (ul ^ comp);
+    }
+
+  return c;
+}
+
+mp_bitcnt_t
+mpz_scan1 (const mpz_t u, mp_bitcnt_t starting_bit)
+{
+  mp_ptr up;
+  mp_size_t us, un, i;
+  mp_limb_t limb, ux;
+
+  us = u->_mp_size;
+  un = GMP_ABS (us);
+  i = starting_bit / GMP_LIMB_BITS;
+
+  /* Past the end there's no 1 bits for u>=0, or an immediate 1 bit
+     for u<0. Notice this test picks up any u==0 too. */
+  if (i >= un)
+    return (us >= 0 ? ~(mp_bitcnt_t) 0 : starting_bit);
+
+  up = u->_mp_d;
+  ux = 0;
+  limb = up[i];
+
+  if (starting_bit != 0)
+    {
+      if (us < 0)
+	{
+	  ux = mpn_zero_p (up, i);
+	  limb = ~ limb + ux;
+	  ux = - (mp_limb_t) (limb >= ux);
+	}
+
+      /* Mask to 0 all bits before starting_bit, thus ignoring them. */
+      limb &= GMP_LIMB_MAX << (starting_bit % GMP_LIMB_BITS);
+    }
+
+  return mpn_common_scan (limb, i, up, un, ux);
+}
+
+mp_bitcnt_t
+mpz_scan0 (const mpz_t u, mp_bitcnt_t starting_bit)
+{
+  mp_ptr up;
+  mp_size_t us, un, i;
+  mp_limb_t limb, ux;
+
+  us = u->_mp_size;
+  ux = - (mp_limb_t) (us >= 0);
+  un = GMP_ABS (us);
+  i = starting_bit / GMP_LIMB_BITS;
+
+  /* When past end, there's an immediate 0 bit for u>=0, or no 0 bits for
+     u<0.  Notice this test picks up all cases of u==0 too. */
+  if (i >= un)
+    return (ux ? starting_bit : ~(mp_bitcnt_t) 0);
+
+  up = u->_mp_d;
+  limb = up[i] ^ ux;
+
+  if (ux == 0)
+    limb -= mpn_zero_p (up, i); /* limb = ~(~limb + zero_p) */
+
+  /* Mask all bits before starting_bit, thus ignoring them. */
+  limb &= GMP_LIMB_MAX << (starting_bit % GMP_LIMB_BITS);
+
+  return mpn_common_scan (limb, i, up, un, ux);
+}
+
+
+/* MPZ base conversion. */
+
+size_t
+mpz_sizeinbase (const mpz_t u, int base)
+{
+  mp_size_t un;
+  mp_srcptr up;
+  mp_ptr tp;
+  mp_bitcnt_t bits;
+  struct gmp_div_inverse bi;
+  size_t ndigits;
+
+  assert (base >= 2);
+  assert (base <= 62);
+
+  un = GMP_ABS (u->_mp_size);
+  if (un == 0)
+    return 1;
+
+  up = u->_mp_d;
+
+  bits = (un - 1) * GMP_LIMB_BITS + mpn_limb_size_in_base_2 (up[un-1]);
+  switch (base)
+    {
+    case 2:
+      return bits;
+    case 4:
+      return (bits + 1) / 2;
+    case 8:
+      return (bits + 2) / 3;
+    case 16:
+      return (bits + 3) / 4;
+    case 32:
+      return (bits + 4) / 5;
+      /* FIXME: Do something more clever for the common case of base
+	 10. */
+    }
+
+  tp = gmp_xalloc_limbs (un);
+  mpn_copyi (tp, up, un);
+  mpn_div_qr_1_invert (&bi, base);
+
+  ndigits = 0;
+  do
+    {
+      ndigits++;
+      mpn_div_qr_1_preinv (tp, tp, un, &bi);
+      un -= (tp[un-1] == 0);
+    }
+  while (un > 0);
+
+  gmp_free (tp);
+  return ndigits;
+}
+
+char *
+mpz_get_str (char *sp, int base, const mpz_t u)
+{
+  unsigned bits;
+  const char *digits;
+  mp_size_t un;
+  size_t i, sn;
+
+  digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz";
+  if (base > 1)
+    {
+      if (base <= 36)
+	digits = "0123456789abcdefghijklmnopqrstuvwxyz";
+      else if (base > 62)
+	return NULL;
+    }
+  else if (base >= -1)
+    base = 10;
+  else
+    {
+      base = -base;
+      if (base > 36)
+	return NULL;
+    }
+
+  sn = 1 + mpz_sizeinbase (u, base);
+  if (!sp)
+    sp = (char *) gmp_xalloc (1 + sn);
+
+  un = GMP_ABS (u->_mp_size);
+
+  if (un == 0)
+    {
+      sp[0] = '0';
+      sp[1] = '\0';
+      return sp;
+    }
+
+  i = 0;
+
+  if (u->_mp_size < 0)
+    sp[i++] = '-';
+
+  bits = mpn_base_power_of_two_p (base);
+
+  if (bits)
+    /* Not modified in this case. */
+    sn = i + mpn_get_str_bits ((unsigned char *) sp + i, bits, u->_mp_d, un);
+  else
+    {
+      struct mpn_base_info info;
+      mp_ptr tp;
+
+      mpn_get_base_info (&info, base);
+      tp = gmp_xalloc_limbs (un);
+      mpn_copyi (tp, u->_mp_d, un);
+
+      sn = i + mpn_get_str_other ((unsigned char *) sp + i, base, &info, tp, un);
+      gmp_free (tp);
+    }
+
+  for (; i < sn; i++)
+    sp[i] = digits[(unsigned char) sp[i]];
+
+  sp[sn] = '\0';
+  return sp;
+}
+
+int
+mpz_set_str (mpz_t r, const char *sp, int base)
+{
+  unsigned bits, value_of_a;
+  mp_size_t rn, alloc;
+  mp_ptr rp;
+  size_t dn;
+  int sign;
+  unsigned char *dp;
+
+  assert (base == 0 || (base >= 2 && base <= 62));
+
+  while (isspace( (unsigned char) *sp))
+    sp++;
+
+  sign = (*sp == '-');
+  sp += sign;
+
+  if (base == 0)
+    {
+      if (sp[0] == '0')
+	{
+	  if (sp[1] == 'x' || sp[1] == 'X')
+	    {
+	      base = 16;
+	      sp += 2;
+	    }
+	  else if (sp[1] == 'b' || sp[1] == 'B')
+	    {
+	      base = 2;
+	      sp += 2;
+	    }
+	  else
+	    base = 8;
+	}
+      else
+	base = 10;
+    }
+
+  if (!*sp)
+    {
+      r->_mp_size = 0;
+      return -1;
+    }
+  dp = (unsigned char *) gmp_xalloc (strlen (sp));
+
+  value_of_a = (base > 36) ? 36 : 10;
+  for (dn = 0; *sp; sp++)
+    {
+      unsigned digit;
+
+      if (isspace ((unsigned char) *sp))
+	continue;
+      else if (*sp >= '0' && *sp <= '9')
+	digit = *sp - '0';
+      else if (*sp >= 'a' && *sp <= 'z')
+	digit = *sp - 'a' + value_of_a;
+      else if (*sp >= 'A' && *sp <= 'Z')
+	digit = *sp - 'A' + 10;
+      else
+	digit = base; /* fail */
+
+      if (digit >= (unsigned) base)
+	{
+	  gmp_free (dp);
+	  r->_mp_size = 0;
+	  return -1;
+	}
+
+      dp[dn++] = digit;
+    }
+
+  if (!dn)
+    {
+      gmp_free (dp);
+      r->_mp_size = 0;
+      return -1;
+    }
+  bits = mpn_base_power_of_two_p (base);
+
+  if (bits > 0)
+    {
+      alloc = (dn * bits + GMP_LIMB_BITS - 1) / GMP_LIMB_BITS;
+      rp = MPZ_REALLOC (r, alloc);
+      rn = mpn_set_str_bits (rp, dp, dn, bits);
+    }
+  else
+    {
+      struct mpn_base_info info;
+      mpn_get_base_info (&info, base);
+      alloc = (dn + info.exp - 1) / info.exp;
+      rp = MPZ_REALLOC (r, alloc);
+      rn = mpn_set_str_other (rp, dp, dn, base, &info);
+      /* Normalization, needed for all-zero input. */
+      assert (rn > 0);
+      rn -= rp[rn-1] == 0;
+    }
+  assert (rn <= alloc);
+  gmp_free (dp);
+
+  r->_mp_size = sign ? - rn : rn;
+
+  return 0;
+}
+
+int
+mpz_init_set_str (mpz_t r, const char *sp, int base)
+{
+  mpz_init (r);
+  return mpz_set_str (r, sp, base);
+}
+#if 0
+size_t
+mpz_out_str (FILE *stream, int base, const mpz_t x)
+{
+  char *str;
+  size_t len;
+
+  str = mpz_get_str (NULL, base, x);
+  len = strlen (str);
+  len = fwrite (str, 1, len, stream);
+  gmp_free (str);
+  return len;
+}
+#endif
+
+static int
+gmp_detect_endian (void)
+{
+  static const int i = 2;
+  const unsigned char *p = (const unsigned char *) &i;
+  return 1 - *p;
+}
+
+/* Import and export. Does not support nails. */
+void
+mpz_import (mpz_t r, size_t count, int order, size_t size, int endian,
+	    size_t nails, const void *src)
+{
+  const unsigned char *p;
+  ptrdiff_t word_step;
+  mp_ptr rp;
+  mp_size_t rn;
+
+  /* The current (partial) limb. */
+  mp_limb_t limb;
+  /* The number of bytes already copied to this limb (starting from
+     the low end). */
+  size_t bytes;
+  /* The index where the limb should be stored, when completed. */
+  mp_size_t i;
+
+  if (nails != 0)
+    gmp_die ("mpz_import: Nails not supported.");
+
+  assert (order == 1 || order == -1);
+  assert (endian >= -1 && endian <= 1);
+
+  if (endian == 0)
+    endian = gmp_detect_endian ();
+
+  p = (unsigned char *) src;
+
+  word_step = (order != endian) ? 2 * size : 0;
+
+  /* Process bytes from the least significant end, so point p at the
+     least significant word. */
+  if (order == 1)
+    {
+      p += size * (count - 1);
+      word_step = - word_step;
+    }
+
+  /* And at least significant byte of that word. */
+  if (endian == 1)
+    p += (size - 1);
+
+  rn = (size * count + sizeof(mp_limb_t) - 1) / sizeof(mp_limb_t);
+  rp = MPZ_REALLOC (r, rn);
+
+  for (limb = 0, bytes = 0, i = 0; count > 0; count--, p += word_step)
+    {
+      size_t j;
+      for (j = 0; j < size; j++, p -= (ptrdiff_t) endian)
+	{
+	  limb |= (mp_limb_t) *p << (bytes++ * CHAR_BIT);
+	  if (bytes == sizeof(mp_limb_t))
+	    {
+	      rp[i++] = limb;
+	      bytes = 0;
+	      limb = 0;
+	    }
+	}
+    }
+  assert (i + (bytes > 0) == rn);
+  if (limb != 0)
+    rp[i++] = limb;
+  else
+    i = mpn_normalized_size (rp, i);
+
+  r->_mp_size = i;
+}
+
+void *
+mpz_export (void *r, size_t *countp, int order, size_t size, int endian,
+	    size_t nails, const mpz_t u)
+{
+  size_t count;
+  mp_size_t un;
+
+  if (nails != 0)
+    gmp_die ("mpz_import: Nails not supported.");
+
+  assert (order == 1 || order == -1);
+  assert (endian >= -1 && endian <= 1);
+  assert (size > 0 || u->_mp_size == 0);
+
+  un = u->_mp_size;
+  count = 0;
+  if (un != 0)
+    {
+      size_t k;
+      unsigned char *p;
+      ptrdiff_t word_step;
+      /* The current (partial) limb. */
+      mp_limb_t limb;
+      /* The number of bytes left to to in this limb. */
+      size_t bytes;
+      /* The index where the limb was read. */
+      mp_size_t i;
+
+      un = GMP_ABS (un);
+
+      /* Count bytes in top limb. */
+      limb = u->_mp_d[un-1];
+      assert (limb != 0);
+
+      k = (GMP_LIMB_BITS <= CHAR_BIT);
+      if (!k)
+	{
+	  do {
+	    int LOCAL_CHAR_BIT = CHAR_BIT;
+	    k++; limb >>= LOCAL_CHAR_BIT;
+	  } while (limb != 0);
+	}
+      /* else limb = 0; */
+
+      count = (k + (un-1) * sizeof (mp_limb_t) + size - 1) / size;
+
+      if (!r)
+	r = gmp_xalloc (count * size);
+
+      if (endian == 0)
+	endian = gmp_detect_endian ();
+
+      p = (unsigned char *) r;
+
+      word_step = (order != endian) ? 2 * size : 0;
+
+      /* Process bytes from the least significant end, so point p at the
+	 least significant word. */
+      if (order == 1)
+	{
+	  p += size * (count - 1);
+	  word_step = - word_step;
+	}
+
+      /* And at least significant byte of that word. */
+      if (endian == 1)
+	p += (size - 1);
+
+      for (bytes = 0, i = 0, k = 0; k < count; k++, p += word_step)
+	{
+	  size_t j;
+	  for (j = 0; j < size; ++j, p -= (ptrdiff_t) endian)
+	    {
+	      if (sizeof (mp_limb_t) == 1)
+		{
+		  if (i < un)
+		    *p = u->_mp_d[i++];
+		  else
+		    *p = 0;
+		}
+	      else
+		{
+		  int LOCAL_CHAR_BIT = CHAR_BIT;
+		  if (bytes == 0)
+		    {
+		      if (i < un)
+			limb = u->_mp_d[i++];
+		      bytes = sizeof (mp_limb_t);
+		    }
+		  *p = limb;
+		  limb >>= LOCAL_CHAR_BIT;
+		  bytes--;
+		}
+	    }
+	}
+      assert (i == un);
+      assert (k == count);
+    }
+
+  if (countp)
+    *countp = count;
+
+  return r;
+}
diff --git a/board/broadcom/bcmbca/mini-gmp/mini-gmp.h b/board/broadcom/bcmbca/mini-gmp/mini-gmp.h
new file mode 100644
index 0000000000..360d3e7d59
--- /dev/null
+++ b/board/broadcom/bcmbca/mini-gmp/mini-gmp.h
@@ -0,0 +1,304 @@
+/* mini-gmp, a minimalistic implementation of a GNU GMP subset.
+
+Copyright 2011-2015, 2017, 2019 Free Software Foundation, Inc.
+
+This file is part of the GNU MP Library.
+
+The GNU MP Library is free software; you can redistribute it and/or modify
+it under the terms of either:
+
+  * the GNU Lesser General Public License as published by the Free
+    Software Foundation; either version 3 of the License, or (at your
+    option) any later version.
+
+or
+
+  * the GNU General Public License as published by the Free Software
+    Foundation; either version 2 of the License, or (at your option) any
+    later version.
+
+or both in parallel, as here.
+
+The GNU MP Library is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received copies of the GNU General Public License and the
+GNU Lesser General Public License along with the GNU MP Library.  If not,
+see https://www.gnu.org/licenses/.  */
+
+/* About mini-gmp: This is a minimal implementation of a subset of the
+   GMP interface. It is intended for inclusion into applications which
+   have modest bignums needs, as a fallback when the real GMP library
+   is not installed.
+
+   This file defines the public interface. */
+
+#ifndef __MINI_GMP_H__
+#define __MINI_GMP_H__
+
+/* For size_t */
+#include <stddef.h>
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+void mp_set_memory_functions (void *(*) (size_t),
+			      void *(*) (void *, size_t, size_t),
+			      void (*) (void *, size_t));
+
+void mp_get_memory_functions (void *(**) (size_t),
+			      void *(**) (void *, size_t, size_t),
+			      void (**) (void *, size_t));
+
+#ifndef MINI_GMP_LIMB_TYPE
+#define MINI_GMP_LIMB_TYPE long
+#endif
+
+typedef unsigned MINI_GMP_LIMB_TYPE mp_limb_t;
+typedef long mp_size_t;
+typedef unsigned long mp_bitcnt_t;
+
+typedef mp_limb_t *mp_ptr;
+typedef const mp_limb_t *mp_srcptr;
+
+typedef struct
+{
+  int _mp_alloc;		/* Number of *limbs* allocated and pointed
+				   to by the _mp_d field.  */
+  int _mp_size;			/* abs(_mp_size) is the number of limbs the
+				   last field points to.  If _mp_size is
+				   negative this is a negative number.  */
+  mp_limb_t *_mp_d;		/* Pointer to the limbs.  */
+} __mpz_struct;
+
+typedef __mpz_struct mpz_t[1];
+
+typedef __mpz_struct *mpz_ptr;
+typedef const __mpz_struct *mpz_srcptr;
+
+extern const int mp_bits_per_limb;
+
+void mpn_copyi (mp_ptr, mp_srcptr, mp_size_t);
+void mpn_copyd (mp_ptr, mp_srcptr, mp_size_t);
+void mpn_zero (mp_ptr, mp_size_t);
+
+int mpn_cmp (mp_srcptr, mp_srcptr, mp_size_t);
+int mpn_zero_p (mp_srcptr, mp_size_t);
+
+mp_limb_t mpn_add_1 (mp_ptr, mp_srcptr, mp_size_t, mp_limb_t);
+mp_limb_t mpn_add_n (mp_ptr, mp_srcptr, mp_srcptr, mp_size_t);
+mp_limb_t mpn_add (mp_ptr, mp_srcptr, mp_size_t, mp_srcptr, mp_size_t);
+
+mp_limb_t mpn_sub_1 (mp_ptr, mp_srcptr, mp_size_t, mp_limb_t);
+mp_limb_t mpn_sub_n (mp_ptr, mp_srcptr, mp_srcptr, mp_size_t);
+mp_limb_t mpn_sub (mp_ptr, mp_srcptr, mp_size_t, mp_srcptr, mp_size_t);
+
+mp_limb_t mpn_mul_1 (mp_ptr, mp_srcptr, mp_size_t, mp_limb_t);
+mp_limb_t mpn_addmul_1 (mp_ptr, mp_srcptr, mp_size_t, mp_limb_t);
+mp_limb_t mpn_submul_1 (mp_ptr, mp_srcptr, mp_size_t, mp_limb_t);
+
+mp_limb_t mpn_mul (mp_ptr, mp_srcptr, mp_size_t, mp_srcptr, mp_size_t);
+void mpn_mul_n (mp_ptr, mp_srcptr, mp_srcptr, mp_size_t);
+void mpn_sqr (mp_ptr, mp_srcptr, mp_size_t);
+int mpn_perfect_square_p (mp_srcptr, mp_size_t);
+mp_size_t mpn_sqrtrem (mp_ptr, mp_ptr, mp_srcptr, mp_size_t);
+
+mp_limb_t mpn_lshift (mp_ptr, mp_srcptr, mp_size_t, unsigned int);
+mp_limb_t mpn_rshift (mp_ptr, mp_srcptr, mp_size_t, unsigned int);
+
+mp_bitcnt_t mpn_scan0 (mp_srcptr, mp_bitcnt_t);
+mp_bitcnt_t mpn_scan1 (mp_srcptr, mp_bitcnt_t);
+
+void mpn_com (mp_ptr, mp_srcptr, mp_size_t);
+mp_limb_t mpn_neg (mp_ptr, mp_srcptr, mp_size_t);
+
+mp_bitcnt_t mpn_popcount (mp_srcptr, mp_size_t);
+
+mp_limb_t mpn_invert_3by2 (mp_limb_t, mp_limb_t);
+#define mpn_invert_limb(x) mpn_invert_3by2 ((x), 0)
+
+size_t mpn_get_str (unsigned char *, int, mp_ptr, mp_size_t);
+mp_size_t mpn_set_str (mp_ptr, const unsigned char *, size_t, int);
+
+void mpz_init (mpz_t);
+void mpz_init2 (mpz_t, mp_bitcnt_t);
+void mpz_clear (mpz_t);
+
+#define mpz_odd_p(z)   (((z)->_mp_size != 0) & (int) (z)->_mp_d[0])
+#define mpz_even_p(z)  (! mpz_odd_p (z))
+
+int mpz_sgn (const mpz_t);
+int mpz_cmp_si (const mpz_t, long);
+int mpz_cmp_ui (const mpz_t, unsigned long);
+int mpz_cmp (const mpz_t, const mpz_t);
+int mpz_cmpabs_ui (const mpz_t, unsigned long);
+int mpz_cmpabs (const mpz_t, const mpz_t);
+int mpz_cmp_d (const mpz_t, double);
+int mpz_cmpabs_d (const mpz_t, double);
+
+void mpz_abs (mpz_t, const mpz_t);
+void mpz_neg (mpz_t, const mpz_t);
+void mpz_swap (mpz_t, mpz_t);
+
+void mpz_add_ui (mpz_t, const mpz_t, unsigned long);
+void mpz_add (mpz_t, const mpz_t, const mpz_t);
+void mpz_sub_ui (mpz_t, const mpz_t, unsigned long);
+void mpz_ui_sub (mpz_t, unsigned long, const mpz_t);
+void mpz_sub (mpz_t, const mpz_t, const mpz_t);
+
+void mpz_mul_si (mpz_t, const mpz_t, long int);
+void mpz_mul_ui (mpz_t, const mpz_t, unsigned long int);
+void mpz_mul (mpz_t, const mpz_t, const mpz_t);
+void mpz_mul_2exp (mpz_t, const mpz_t, mp_bitcnt_t);
+void mpz_addmul_ui (mpz_t, const mpz_t, unsigned long int);
+void mpz_addmul (mpz_t, const mpz_t, const mpz_t);
+void mpz_submul_ui (mpz_t, const mpz_t, unsigned long int);
+void mpz_submul (mpz_t, const mpz_t, const mpz_t);
+
+void mpz_cdiv_qr (mpz_t, mpz_t, const mpz_t, const mpz_t);
+void mpz_fdiv_qr (mpz_t, mpz_t, const mpz_t, const mpz_t);
+void mpz_tdiv_qr (mpz_t, mpz_t, const mpz_t, const mpz_t);
+void mpz_cdiv_q (mpz_t, const mpz_t, const mpz_t);
+void mpz_fdiv_q (mpz_t, const mpz_t, const mpz_t);
+void mpz_tdiv_q (mpz_t, const mpz_t, const mpz_t);
+void mpz_cdiv_r (mpz_t, const mpz_t, const mpz_t);
+void mpz_fdiv_r (mpz_t, const mpz_t, const mpz_t);
+void mpz_tdiv_r (mpz_t, const mpz_t, const mpz_t);
+
+void mpz_cdiv_q_2exp (mpz_t, const mpz_t, mp_bitcnt_t);
+void mpz_fdiv_q_2exp (mpz_t, const mpz_t, mp_bitcnt_t);
+void mpz_tdiv_q_2exp (mpz_t, const mpz_t, mp_bitcnt_t);
+void mpz_cdiv_r_2exp (mpz_t, const mpz_t, mp_bitcnt_t);
+void mpz_fdiv_r_2exp (mpz_t, const mpz_t, mp_bitcnt_t);
+void mpz_tdiv_r_2exp (mpz_t, const mpz_t, mp_bitcnt_t);
+
+void mpz_mod (mpz_t, const mpz_t, const mpz_t);
+
+void mpz_divexact (mpz_t, const mpz_t, const mpz_t);
+
+int mpz_divisible_p (const mpz_t, const mpz_t);
+int mpz_congruent_p (const mpz_t, const mpz_t, const mpz_t);
+
+unsigned long mpz_cdiv_qr_ui (mpz_t, mpz_t, const mpz_t, unsigned long);
+unsigned long mpz_fdiv_qr_ui (mpz_t, mpz_t, const mpz_t, unsigned long);
+unsigned long mpz_tdiv_qr_ui (mpz_t, mpz_t, const mpz_t, unsigned long);
+unsigned long mpz_cdiv_q_ui (mpz_t, const mpz_t, unsigned long);
+unsigned long mpz_fdiv_q_ui (mpz_t, const mpz_t, unsigned long);
+unsigned long mpz_tdiv_q_ui (mpz_t, const mpz_t, unsigned long);
+unsigned long mpz_cdiv_r_ui (mpz_t, const mpz_t, unsigned long);
+unsigned long mpz_fdiv_r_ui (mpz_t, const mpz_t, unsigned long);
+unsigned long mpz_tdiv_r_ui (mpz_t, const mpz_t, unsigned long);
+unsigned long mpz_cdiv_ui (const mpz_t, unsigned long);
+unsigned long mpz_fdiv_ui (const mpz_t, unsigned long);
+unsigned long mpz_tdiv_ui (const mpz_t, unsigned long);
+
+unsigned long mpz_mod_ui (mpz_t, const mpz_t, unsigned long);
+
+void mpz_divexact_ui (mpz_t, const mpz_t, unsigned long);
+
+int mpz_divisible_ui_p (const mpz_t, unsigned long);
+
+unsigned long mpz_gcd_ui (mpz_t, const mpz_t, unsigned long);
+void mpz_gcd (mpz_t, const mpz_t, const mpz_t);
+void mpz_gcdext (mpz_t, mpz_t, mpz_t, const mpz_t, const mpz_t);
+void mpz_lcm_ui (mpz_t, const mpz_t, unsigned long);
+void mpz_lcm (mpz_t, const mpz_t, const mpz_t);
+int mpz_invert (mpz_t, const mpz_t, const mpz_t);
+
+void mpz_sqrtrem (mpz_t, mpz_t, const mpz_t);
+void mpz_sqrt (mpz_t, const mpz_t);
+int mpz_perfect_square_p (const mpz_t);
+
+void mpz_pow_ui (mpz_t, const mpz_t, unsigned long);
+void mpz_ui_pow_ui (mpz_t, unsigned long, unsigned long);
+void mpz_powm (mpz_t, const mpz_t, const mpz_t, const mpz_t);
+void mpz_powm_ui (mpz_t, const mpz_t, unsigned long, const mpz_t);
+
+void mpz_rootrem (mpz_t, mpz_t, const mpz_t, unsigned long);
+int mpz_root (mpz_t, const mpz_t, unsigned long);
+
+void mpz_fac_ui (mpz_t, unsigned long);
+void mpz_2fac_ui (mpz_t, unsigned long);
+void mpz_mfac_uiui (mpz_t, unsigned long, unsigned long);
+void mpz_bin_uiui (mpz_t, unsigned long, unsigned long);
+
+int mpz_probab_prime_p (const mpz_t, int);
+
+int mpz_tstbit (const mpz_t, mp_bitcnt_t);
+void mpz_setbit (mpz_t, mp_bitcnt_t);
+void mpz_clrbit (mpz_t, mp_bitcnt_t);
+void mpz_combit (mpz_t, mp_bitcnt_t);
+
+void mpz_com (mpz_t, const mpz_t);
+void mpz_and (mpz_t, const mpz_t, const mpz_t);
+void mpz_ior (mpz_t, const mpz_t, const mpz_t);
+void mpz_xor (mpz_t, const mpz_t, const mpz_t);
+
+mp_bitcnt_t mpz_popcount (const mpz_t);
+mp_bitcnt_t mpz_hamdist (const mpz_t, const mpz_t);
+mp_bitcnt_t mpz_scan0 (const mpz_t, mp_bitcnt_t);
+mp_bitcnt_t mpz_scan1 (const mpz_t, mp_bitcnt_t);
+
+int mpz_fits_slong_p (const mpz_t);
+int mpz_fits_ulong_p (const mpz_t);
+long int mpz_get_si (const mpz_t);
+unsigned long int mpz_get_ui (const mpz_t);
+double mpz_get_d (const mpz_t);
+size_t mpz_size (const mpz_t);
+mp_limb_t mpz_getlimbn (const mpz_t, mp_size_t);
+
+void mpz_realloc2 (mpz_t, mp_bitcnt_t);
+mp_srcptr mpz_limbs_read (mpz_srcptr);
+mp_ptr mpz_limbs_modify (mpz_t, mp_size_t);
+mp_ptr mpz_limbs_write (mpz_t, mp_size_t);
+void mpz_limbs_finish (mpz_t, mp_size_t);
+mpz_srcptr mpz_roinit_n (mpz_t, mp_srcptr, mp_size_t);
+
+#define MPZ_ROINIT_N(xp, xs) {{0, (xs),(xp) }}
+
+void mpz_set_si (mpz_t, signed long int);
+void mpz_set_ui (mpz_t, unsigned long int);
+void mpz_set (mpz_t, const mpz_t);
+void mpz_set_d (mpz_t, double);
+
+void mpz_init_set_si (mpz_t, signed long int);
+void mpz_init_set_ui (mpz_t, unsigned long int);
+void mpz_init_set (mpz_t, const mpz_t);
+void mpz_init_set_d (mpz_t, double);
+
+size_t mpz_sizeinbase (const mpz_t, int);
+char *mpz_get_str (char *, int, const mpz_t);
+int mpz_set_str (mpz_t, const char *, int);
+int mpz_init_set_str (mpz_t, const char *, int);
+#if 0
+/* This long list taken from gmp.h. */
+/* For reference, "defined(EOF)" cannot be used here.  In g++ 2.95.4,
+   <iostream> defines EOF but not FILE.  */
+#if defined (FILE)                                              \
+  || defined (H_STDIO)                                          \
+  || defined (_H_STDIO)               /* AIX */                 \
+  || defined (_STDIO_H)               /* glibc, Sun, SCO */     \
+  || defined (_STDIO_H_)              /* BSD, OSF */            \
+  || defined (__STDIO_H)              /* Borland */             \
+  || defined (__STDIO_H__)            /* IRIX */                \
+  || defined (_STDIO_INCLUDED)        /* HPUX */                \
+  || defined (__dj_include_stdio_h_)  /* DJGPP */               \
+  || defined (_FILE_DEFINED)          /* Microsoft */           \
+  || defined (__STDIO__)              /* Apple MPW MrC */       \
+  || defined (_MSL_STDIO_H)           /* Metrowerks */          \
+  || defined (_STDIO_H_INCLUDED)      /* QNX4 */		\
+  || defined (_ISO_STDIO_ISO_H)       /* Sun C++ */		\
+  || defined (__STDIO_LOADED)         /* VMS */
+size_t mpz_out_str (FILE *, int, const mpz_t);
+#endif
+#endif
+void mpz_import (mpz_t, size_t, int, size_t, int, size_t, const void *);
+void *mpz_export (void *, size_t *, int, size_t, int, size_t, const mpz_t);
+
+#if defined (__cplusplus)
+}
+#endif
+#endif /* __MINI_GMP_H__ */
diff --git a/board/broadcom/bcmbca/mini-gmp/mini-mpq.c b/board/broadcom/bcmbca/mini-gmp/mini-mpq.c
new file mode 100644
index 0000000000..c303c20111
--- /dev/null
+++ b/board/broadcom/bcmbca/mini-gmp/mini-mpq.c
@@ -0,0 +1,568 @@
+/* mini-mpq, a minimalistic implementation of a GNU GMP subset.
+
+   Contributed to the GNU project by Marco Bodrato
+
+   Acknowledgment: special thanks to Bradley Lucier for his comments
+   to the preliminary version of this code.
+
+Copyright 2018, 2019 Free Software Foundation, Inc.
+
+This file is part of the GNU MP Library.
+
+The GNU MP Library is free software; you can redistribute it and/or modify
+it under the terms of either:
+
+  * the GNU Lesser General Public License as published by the Free
+    Software Foundation; either version 3 of the License, or (at your
+    option) any later version.
+
+or
+
+  * the GNU General Public License as published by the Free Software
+    Foundation; either version 2 of the License, or (at your option) any
+    later version.
+
+or both in parallel, as here.
+
+The GNU MP Library is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received copies of the GNU General Public License and the
+GNU Lesser General Public License along with the GNU MP Library.  If not,
+see https://www.gnu.org/licenses/.  */
+#if defined (CONFIG_ARM64) || defined (CONFIG_ARM) 
+#include <common.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <linux/errno.h>
+#include <asm/types.h>
+#include <asm/unaligned.h>
+#include <malloc.h>
+#define CHAR_BIT	8
+extern void bcm_sec_abort(void);
+#define abort	bcm_sec_abort
+#else 
+#include <assert.h>
+#include <limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#endif
+
+#include "mini-mpq.h"
+#ifndef GMP_LIMB_HIGHBIT
+#define GMP_LIMB_MAX ((mp_limb_t) ~ (mp_limb_t) 0)
+/* Define macros and static functions already defined by mini-gmp.c */
+#define GMP_LIMB_BITS (sizeof(mp_limb_t) * CHAR_BIT)
+#define GMP_LIMB_HIGHBIT ((mp_limb_t) 1 << (GMP_LIMB_BITS - 1))
+#define GMP_NEG_CAST(T,x) (-((T)((x) + 1) - 1))
+#define GMP_MIN(a, b) ((a) < (b) ? (a) : (b))
+
+extern void sec_abort(void);
+
+static mpz_srcptr
+mpz_roinit_normal_n (mpz_t x, mp_srcptr xp, mp_size_t xs)
+{
+  x->_mp_alloc = 0;
+  x->_mp_d = (mp_ptr) xp;
+  x->_mp_size = xs;
+  return x;
+}
+
+static void
+gmp_die (const char *msg)
+{
+  printf ( "%s\n", msg);
+  abort();
+}
+#endif
+
+
+/* MPQ helper functions */
+static mpq_srcptr
+mpq_roinit_normal_nn (mpq_t x, mp_srcptr np, mp_size_t ns,
+		     mp_srcptr dp, mp_size_t ds)
+{
+  mpz_roinit_normal_n (mpq_numref(x), np, ns);
+  mpz_roinit_normal_n (mpq_denref(x), dp, ds);
+  return x;
+}
+
+static mpq_srcptr
+mpq_roinit_zz (mpq_t x, mpz_srcptr n, mpz_srcptr d)
+{
+  return mpq_roinit_normal_nn (x, n->_mp_d, n->_mp_size,
+			       d->_mp_d, d->_mp_size);
+}
+
+static void
+mpq_nan_init (mpq_t x)
+{
+  mpz_init (mpq_numref (x));
+  mpz_init (mpq_denref (x));
+}
+
+void
+mpq_init (mpq_t x)
+{
+  mpz_init (mpq_numref (x));
+  mpz_init_set_ui (mpq_denref (x), 1);
+}
+
+void
+mpq_clear (mpq_t x)
+{
+  mpz_clear (mpq_numref (x));
+  mpz_clear (mpq_denref (x));
+}
+
+static void
+mpq_canonical_sign (mpq_t r)
+{
+  int cmp = mpq_denref (r)->_mp_size;
+  if (cmp <= 0)
+    {
+      if (cmp == 0)
+	gmp_die("mpq: Fraction with zero denominator.");
+      mpz_neg (mpq_denref (r), mpq_denref (r));
+      mpz_neg (mpq_numref (r), mpq_numref (r));
+    }
+}
+
+static void
+mpq_helper_canonicalize (mpq_t r, const mpz_t num, const mpz_t den, mpz_t g)
+{
+  if (num->_mp_size == 0)
+    mpq_set_ui (r, 0, 1);
+  else
+    {
+      mpz_gcd (g, num, den);
+      mpz_tdiv_q (mpq_numref (r), num, g);
+      mpz_tdiv_q (mpq_denref (r), den, g);
+      mpq_canonical_sign (r);
+    }
+}
+
+void
+mpq_canonicalize (mpq_t r)
+{
+  mpz_t t;
+
+  mpz_init (t);
+  mpq_helper_canonicalize (r, mpq_numref (r), mpq_denref (r), t);
+  mpz_clear (t);
+}
+
+void
+mpq_swap (mpq_t a, mpq_t b)
+{
+  mpz_swap (mpq_numref (a), mpq_numref (b));
+  mpz_swap (mpq_denref (a), mpq_denref (b));
+}
+
+
+/* MPQ assignment and conversions. */
+void
+mpz_set_q (mpz_t r, const mpq_t q)
+{
+  mpz_tdiv_q (r, mpq_numref (q), mpq_denref (q));
+}
+
+void
+mpq_set (mpq_t r, const mpq_t q)
+{
+  mpz_set (mpq_numref (r), mpq_numref (q));
+  mpz_set (mpq_denref (r), mpq_denref (q));
+}
+
+void
+mpq_set_ui (mpq_t r, unsigned long n, unsigned long d)
+{
+  mpz_set_ui (mpq_numref (r), n);
+  mpz_set_ui (mpq_denref (r), d);
+}
+
+void
+mpq_set_si (mpq_t r, signed long n, unsigned long d)
+{
+  mpz_set_si (mpq_numref (r), n);
+  mpz_set_ui (mpq_denref (r), d);
+}
+
+void
+mpq_set_z (mpq_t r, const mpz_t n)
+{
+  mpz_set_ui (mpq_denref (r), 1);
+  mpz_set (mpq_numref (r), n);
+}
+
+void
+mpq_set_num (mpq_t r, const mpz_t z)
+{
+  mpz_set (mpq_numref (r), z);
+}
+
+void
+mpq_set_den (mpq_t r, const mpz_t z)
+{
+  mpz_set (mpq_denref (r), z);
+}
+
+void
+mpq_get_num (mpz_t r, const mpq_t q)
+{
+  mpz_set (r, mpq_numref (q));
+}
+
+void
+mpq_get_den (mpz_t r, const mpq_t q)
+{
+  mpz_set (r, mpq_denref (q));
+}
+
+
+/* MPQ comparisons and the like. */
+int
+mpq_cmp (const mpq_t a, const mpq_t b)
+{
+  mpz_t t1, t2;
+  int res;
+
+  mpz_init (t1);
+  mpz_init (t2);
+  mpz_mul (t1, mpq_numref (a), mpq_denref (b));
+  mpz_mul (t2, mpq_numref (b), mpq_denref (a));
+  res = mpz_cmp (t1, t2);
+  mpz_clear (t1);
+  mpz_clear (t2);
+
+  return res;
+}
+
+int
+mpq_cmp_z (const mpq_t a, const mpz_t b)
+{
+  mpz_t t;
+  int res;
+
+  mpz_init (t);
+  mpz_mul (t, b, mpq_denref (a));
+  res = mpz_cmp (mpq_numref (a), t);
+  mpz_clear (t);
+
+  return res;
+}
+
+int
+mpq_equal (const mpq_t a, const mpq_t b)
+{
+  return (mpz_cmp (mpq_numref (a), mpq_numref (b)) == 0) &&
+    (mpz_cmp (mpq_denref (a), mpq_denref (b)) == 0);
+}
+
+int
+mpq_cmp_ui (const mpq_t q, unsigned long n, unsigned long d)
+{
+  mpq_t t;
+  assert (d != 0);
+  if (ULONG_MAX <= GMP_LIMB_MAX) {
+    mp_limb_t nl = n, dl = d;
+    return mpq_cmp (q, mpq_roinit_normal_nn (t, &nl, n != 0, &dl, 1));
+  } else {
+    int ret;
+
+    mpq_init (t);
+    mpq_set_ui (t, n, d);
+    ret = mpq_cmp (q, t);
+    mpq_clear (t);
+
+    return ret;
+  }
+}
+
+int
+mpq_cmp_si (const mpq_t q, signed long n, unsigned long d)
+{
+  assert (d != 0);
+
+  if (n >= 0)
+    return mpq_cmp_ui (q, n, d);
+  else
+    {
+      mpq_t t;
+
+      if (ULONG_MAX <= GMP_LIMB_MAX)
+	{
+	  mp_limb_t nl = GMP_NEG_CAST (unsigned long, n), dl = d;
+	  return mpq_cmp (q, mpq_roinit_normal_nn (t, &nl, -1, &dl, 1));
+	}
+      else
+	{
+	  unsigned long l_n = GMP_NEG_CAST (unsigned long, n);
+
+	  mpq_roinit_normal_nn (t, mpq_numref (q)->_mp_d, - mpq_numref (q)->_mp_size,
+				mpq_denref (q)->_mp_d, mpq_denref (q)->_mp_size);
+	  return - mpq_cmp_ui (t, l_n, d);
+	}
+    }
+}
+
+int
+mpq_sgn (const mpq_t a)
+{
+  return mpz_sgn (mpq_numref (a));
+}
+
+
+/* MPQ arithmetic. */
+void
+mpq_abs (mpq_t r, const mpq_t q)
+{
+  mpz_abs (mpq_numref (r), mpq_numref (q));
+  mpz_set (mpq_denref (r), mpq_denref (q));
+}
+
+void
+mpq_neg (mpq_t r, const mpq_t q)
+{
+  mpz_neg (mpq_numref (r), mpq_numref (q));
+  mpz_set (mpq_denref (r), mpq_denref (q));
+}
+
+void
+mpq_add (mpq_t r, const mpq_t a, const mpq_t b)
+{
+  mpz_t t;
+
+  mpz_init (t);
+  mpz_gcd (t, mpq_denref (a), mpq_denref (b));
+  if (mpz_cmp_ui (t, 1) == 0)
+    {
+      mpz_mul (t, mpq_numref (a), mpq_denref (b));
+      mpz_addmul (t, mpq_numref (b), mpq_denref (a));
+      mpz_mul (mpq_denref (r), mpq_denref (a), mpq_denref (b));
+      mpz_swap (mpq_numref (r), t);
+    }
+  else
+    {
+      mpz_t x, y;
+      mpz_init (x);
+      mpz_init (y);
+
+      mpz_tdiv_q (x, mpq_denref (b), t);
+      mpz_tdiv_q (y, mpq_denref (a), t);
+      mpz_mul (x, mpq_numref (a), x);
+      mpz_addmul (x, mpq_numref (b), y);
+
+      mpz_gcd (t, x, t);
+      mpz_tdiv_q (mpq_numref (r), x, t);
+      mpz_tdiv_q (x, mpq_denref (b), t);
+      mpz_mul (mpq_denref (r), x, y);
+
+      mpz_clear (x);
+      mpz_clear (y);
+    }
+  mpz_clear (t);
+}
+
+void
+mpq_sub (mpq_t r, const mpq_t a, const mpq_t b)
+{
+  mpq_t t;
+
+  mpq_roinit_normal_nn (t, mpq_numref (b)->_mp_d, - mpq_numref (b)->_mp_size,
+			mpq_denref (b)->_mp_d, mpq_denref (b)->_mp_size);
+  mpq_add (r, a, t);
+}
+
+void
+mpq_div (mpq_t r, const mpq_t a, const mpq_t b)
+{
+  mpq_t t;
+  mpq_mul (r, a, mpq_roinit_zz (t, mpq_denref (b), mpq_numref (b)));
+}
+
+void
+mpq_mul (mpq_t r, const mpq_t a, const mpq_t b)
+{
+  mpq_t t;
+  mpq_nan_init (t);
+
+  if (a != b) {
+    mpz_t g;
+
+    mpz_init (g);
+    mpq_helper_canonicalize (t, mpq_numref (a), mpq_denref (b), g);
+    mpq_helper_canonicalize (r, mpq_numref (b), mpq_denref (a), g);
+    mpz_clear (g);
+
+    a = r;
+    b = t;
+  }
+
+  mpz_mul (mpq_numref (r), mpq_numref (a), mpq_numref (b));
+  mpz_mul (mpq_denref (r), mpq_denref (a), mpq_denref (b));
+  mpq_clear (t);
+}
+
+void
+mpq_div_2exp (mpq_t r, const mpq_t q, mp_bitcnt_t e)
+{
+  mp_bitcnt_t z = mpz_scan1 (mpq_numref (q), 0);
+  z = GMP_MIN (z, e);
+  mpz_mul_2exp (mpq_denref (r), mpq_denref (q), e - z);
+  mpz_tdiv_q_2exp (mpq_numref (r), mpq_numref (q), z);
+}
+
+void
+mpq_mul_2exp (mpq_t r, const mpq_t q, mp_bitcnt_t e)
+{
+  mp_bitcnt_t z = mpz_scan1 (mpq_denref (q), 0);
+  z = GMP_MIN (z, e);
+  mpz_mul_2exp (mpq_numref (r), mpq_numref (q), e - z);
+  mpz_tdiv_q_2exp (mpq_denref (r), mpq_denref (q), z);
+}
+
+void
+mpq_inv (mpq_t r, const mpq_t q)
+{
+  mpq_set (r, q);
+  mpz_swap (mpq_denref (r), mpq_numref (r));
+  mpq_canonical_sign (r);
+}
+
+
+/* MPQ to/from double. */
+void
+mpq_set_d (mpq_t r, double x)
+{
+  mpz_set_ui (mpq_denref (r), 1);
+
+  /* x != x is true when x is a NaN, and x == x * 0.5 is true when x is
+     zero or infinity. */
+  if (x == x * 0.5 || x != x)
+    mpq_numref (r)->_mp_size = 0;
+  else
+    {
+      double B;
+      mp_bitcnt_t e;
+
+      B = 4.0 * (double) (GMP_LIMB_HIGHBIT >> 1);
+      for (e = 0; x != x + 0.5; e += GMP_LIMB_BITS)
+	x *= B;
+
+      mpz_set_d (mpq_numref (r), x);
+      mpq_div_2exp (r, r, e);
+    }
+}
+
+double
+mpq_get_d (const mpq_t u)
+{
+  mp_bitcnt_t ne, de, ee;
+  mpz_t z;
+  double B, ret;
+
+  ne = mpz_sizeinbase (mpq_numref (u), 2);
+  de = mpz_sizeinbase (mpq_denref (u), 2);
+
+  ee = CHAR_BIT * sizeof (double);
+  if (de == 1 || ne > de + ee)
+    ee = 0;
+  else
+    ee = (ee + de - ne) / GMP_LIMB_BITS + 1;
+
+  mpz_init (z);
+  mpz_mul_2exp (z, mpq_numref (u), ee * GMP_LIMB_BITS);
+  mpz_tdiv_q (z, z, mpq_denref (u));
+  ret = mpz_get_d (z);
+  mpz_clear (z);
+
+  B = 4.0 * (double) (GMP_LIMB_HIGHBIT >> 1);
+  for (B = 1 / B; ee != 0; --ee)
+    ret *= B;
+
+  return ret;
+}
+
+
+/* MPQ and strings/streams. */
+char *
+mpq_get_str (char *sp, int base, const mpq_t q)
+{
+  char *res;
+  char *rden;
+  size_t len;
+
+  res = mpz_get_str (sp, base, mpq_numref (q));
+  if (res == NULL || mpz_cmp_ui (mpq_denref (q), 1) == 0)
+    return res;
+
+  len = strlen (res) + 1;
+  rden = sp ? sp + len : NULL;
+  rden = mpz_get_str (rden, base, mpq_denref (q));
+  assert (rden != NULL);
+
+  if (sp == NULL) {
+    void * (*gmp_reallocate_func) (void *, size_t, size_t);
+    void (*gmp_free_func) (void *, size_t);
+    size_t lden;
+
+    mp_get_memory_functions (NULL, &gmp_reallocate_func, &gmp_free_func);
+    lden = strlen (rden) + 1;
+    res = (char *) gmp_reallocate_func (res, 0, (lden + len) * sizeof (char));
+    memcpy (res + len, rden, lden);
+    gmp_free_func (rden, 0);
+  }
+
+  res [len - 1] = '/';
+  return res;
+}
+#if 0
+size_t
+mpq_out_str (FILE *stream, int base, const mpq_t x)
+{
+  char * str;
+  size_t len;
+  void (*gmp_free_func) (void *, size_t);
+
+  str = mpq_get_str (NULL, base, x);
+  len = strlen (str);
+  len = fwrite (str, 1, len, stream);
+  mp_get_memory_functions (NULL, NULL, &gmp_free_func);
+  gmp_free_func (str, 0);
+  return len;
+}
+#endif
+int
+mpq_set_str (mpq_t r, const char *sp, int base)
+{
+  const char *slash;
+
+  slash = strchr (sp, '/');
+  if (slash == NULL) {
+    mpz_set_ui (mpq_denref(r), 1);
+    return mpz_set_str (mpq_numref(r), sp, base);
+  } else {
+    char *num;
+    size_t numlen;
+    int ret;
+    void * (*gmp_allocate_func) (size_t);
+    void (*gmp_free_func) (void *, size_t);
+
+    mp_get_memory_functions (&gmp_allocate_func, NULL, &gmp_free_func);
+    numlen = slash - sp;
+    num = (char *) gmp_allocate_func ((numlen + 1) * sizeof (char));
+    memcpy (num, sp, numlen);
+    num[numlen] = '\0';
+    ret = mpz_set_str (mpq_numref(r), num, base);
+    gmp_free_func (num, 0);
+
+    if (ret != 0)
+      return ret;
+
+    return mpz_set_str (mpq_denref(r), slash + 1, base);
+  }
+}
diff --git a/board/broadcom/bcmbca/mini-gmp/mini-mpq.h b/board/broadcom/bcmbca/mini-gmp/mini-mpq.h
new file mode 100644
index 0000000000..2a7a2c6122
--- /dev/null
+++ b/board/broadcom/bcmbca/mini-gmp/mini-mpq.h
@@ -0,0 +1,114 @@
+/* mini-mpq, a minimalistic implementation of a GNU GMP subset.
+
+Copyright 2018, 2019 Free Software Foundation, Inc.
+
+This file is part of the GNU MP Library.
+
+The GNU MP Library is free software; you can redistribute it and/or modify
+it under the terms of either:
+
+  * the GNU Lesser General Public License as published by the Free
+    Software Foundation; either version 3 of the License, or (at your
+    option) any later version.
+
+or
+
+  * the GNU General Public License as published by the Free Software
+    Foundation; either version 2 of the License, or (at your option) any
+    later version.
+
+or both in parallel, as here.
+
+The GNU MP Library is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received copies of the GNU General Public License and the
+GNU Lesser General Public License along with the GNU MP Library.  If not,
+see https://www.gnu.org/licenses/.  */
+
+/* Header */
+
+#ifndef __MINI_MPQ_H__
+#define __MINI_MPQ_H__
+
+#include "mini-gmp.h"
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+typedef struct
+{
+  __mpz_struct _mp_num;
+  __mpz_struct _mp_den;
+} __mpq_struct;
+
+typedef __mpq_struct mpq_t[1];
+
+typedef const __mpq_struct *mpq_srcptr;
+typedef __mpq_struct *mpq_ptr;
+
+#define mpq_numref(Q) (&((Q)->_mp_num))
+#define mpq_denref(Q) (&((Q)->_mp_den))
+
+void mpq_abs (mpq_t, const mpq_t);
+void mpq_add (mpq_t, const mpq_t, const mpq_t);
+void mpq_canonicalize (mpq_t);
+void mpq_clear (mpq_t);
+int mpq_cmp (const mpq_t, const mpq_t);
+int mpq_cmp_si (const mpq_t, signed long, unsigned long);
+int mpq_cmp_ui (const mpq_t, unsigned long, unsigned long);
+int mpq_cmp_z (const mpq_t, const mpz_t);
+void mpq_div (mpq_t, const mpq_t, const mpq_t);
+void mpq_div_2exp (mpq_t, const mpq_t, mp_bitcnt_t);
+int mpq_equal (const mpq_t, const mpq_t);
+double mpq_get_d (const mpq_t);
+void mpq_get_den (mpz_t, const mpq_t);
+void mpq_get_num (mpz_t, const mpq_t);
+char * mpq_get_str (char *, int, const mpq_t q);
+void mpq_init (mpq_t);
+void mpq_inv (mpq_t, const mpq_t);
+void mpq_mul (mpq_t, const mpq_t, const mpq_t);
+void mpq_mul_2exp (mpq_t, const mpq_t, mp_bitcnt_t);
+void mpq_neg (mpq_t, const mpq_t);
+void mpq_set (mpq_t, const mpq_t);
+void mpq_set_d (mpq_t, double);
+void mpq_set_den (mpq_t, const mpz_t);
+void mpq_set_num (mpq_t, const mpz_t);
+void mpq_set_si (mpq_t, signed long, unsigned long);
+int mpq_set_str (mpq_t, const char *, int);
+void mpq_set_ui (mpq_t, unsigned long, unsigned long);
+void mpq_set_z (mpq_t, const mpz_t);
+int mpq_sgn (const mpq_t);
+void mpq_sub (mpq_t, const mpq_t, const mpq_t);
+void mpq_swap (mpq_t, mpq_t);
+#if 0
+/* This long list taken from gmp.h. */
+/* For reference, "defined(EOF)" cannot be used here.  In g++ 2.95.4,
+   <iostream> defines EOF but not FILE.  */
+#if defined (FILE)                                              \
+  || defined (H_STDIO)                                          \
+  || defined (_H_STDIO)               /* AIX */                 \
+  || defined (_STDIO_H)               /* glibc, Sun, SCO */     \
+  || defined (_STDIO_H_)              /* BSD, OSF */            \
+  || defined (__STDIO_H)              /* Borland */             \
+  || defined (__STDIO_H__)            /* IRIX */                \
+  || defined (_STDIO_INCLUDED)        /* HPUX */                \
+  || defined (__dj_include_stdio_h_)  /* DJGPP */               \
+  || defined (_FILE_DEFINED)          /* Microsoft */           \
+  || defined (__STDIO__)              /* Apple MPW MrC */       \
+  || defined (_MSL_STDIO_H)           /* Metrowerks */          \
+  || defined (_STDIO_H_INCLUDED)      /* QNX4 */                \
+  || defined (_ISO_STDIO_ISO_H)       /* Sun C++ */             \
+  || defined (__STDIO_LOADED)         /* VMS */
+size_t mpq_out_str (FILE *, int, const mpq_t);
+#endif
+#endif
+void mpz_set_q (mpz_t, const mpq_t);
+
+#if defined (__cplusplus)
+}
+#endif
+#endif /* __MINI_MPQ_H__ */
diff --git a/board/broadcom/bcmbca/pmc_commands.c b/board/broadcom/bcmbca/pmc_commands.c
new file mode 100644
index 0000000000..dd7f3fad91
--- /dev/null
+++ b/board/broadcom/bcmbca/pmc_commands.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019
+ * Broadcom Corp
+ */
+
+#include <command.h>
+#include <common.h>
+#include <environment.h>
+#include "spl_env.h"
+#include "pmc_drv.h"
+
+#ifdef PMC_ON_HOSTCPU
+#define PMCcmd(...) -1
+#else
+extern int PMCcmd(int arg[4]);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	PMCFW_CODE,
+	PMCFW_DATA,
+	PMCFW_TYPES
+};
+
+static int is_pmcfw_loaded(int type)
+{
+	const char *path[PMCFW_TYPES] = {
+		"/fit-images/pmcfw_code",
+		"/fit-images/pmcfw_data"
+	};
+	int offset = fdt_path_offset(gd->fdt_blob, path[type]);
+	const uint32_t *load_addr, *size;
+
+	if (offset < 0) return 0;
+	load_addr = fdt_getprop(gd->fdt_blob, offset, "load-addr", NULL);
+	if (!load_addr) return 0;
+	size = fdt_getprop(gd->fdt_blob, offset, "size", NULL);
+	if (!size) return 0;
+	printf("pmc firmware %s has been loaded to 0x%x, size=%uB\n",
+			(type ? "data" : "code"),
+			be32_to_cpu(*load_addr), be32_to_cpu(*size));
+
+	return 1;
+}
+
+int is_pmcfw_code_loaded(void)
+{
+	return is_pmcfw_loaded(PMCFW_CODE);
+}
+
+int is_pmcfw_data_loaded(void)
+{
+	return is_pmcfw_loaded(PMCFW_DATA);
+}
+
+// return 1 if the environment variable avs_disable=1
+int getAVSConfig(void)
+{
+	char *disable = NULL;
+	int offset = fdt_path_offset(gd->fdt_blob, "/chosen");
+
+	if (offset < 0) return 0;
+	disable = fdt_getprop(gd->fdt_blob, offset, ENV_AVS_DISABLE, NULL);
+	if (!disable) return 0;
+
+	return *disable == '1';
+}
+
+static void setAVSConfig(int new)
+{
+	int old = getAVSConfig();
+
+	if (old == new) return;
+
+	if (!env_set(ENV_AVS_DISABLE, new ? "1" : NULL) && !env_save())
+		printf("Reboot to use new " ENV_AVS_DISABLE "=%d\n", new);
+}
+
+static int
+do_pmc_sc_avs(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+#if IS_BCMCHIP(4908) || IS_BCMCHIP(63158) || IS_BCMCHIP(63178) || \
+	IS_BCMCHIP(47622) || IS_BCMCHIP(63146) || IS_BCMCHIP(4912) || \
+	IS_BCMCHIP(6756)
+	int pmc[4];
+	static const char *disables[] = {"0", "disable", "false", "off"};
+	int res, i;
+
+	if (argc < 2) {
+		res = getAVSConfig();
+		printf("AVS %sdisabled by environment\n", res ? "" : "not ");
+		return CMD_RET_SUCCESS;
+	}
+
+	if (!strcmp(argv[1], "show")) {
+		memset((void*)pmc, 0, sizeof(pmc));
+		/* Try to know the AVS disable state */
+		pmc[0] = 20; // cmdGetAvsDisableState defined in pmc/command.h
+		res = PMCcmd(pmc);
+		if (!res)
+			printf("AVS %s\n", pmc[2] ? "Disabled" : "Enabled");
+		else
+			printf("failed to get AVS state, res=%d\n", res);
+		return CMD_RET_SUCCESS;
+	}
+
+	res = 0;
+	for (i = 0; i < sizeof disables / sizeof disables[0]; i++)
+		if (!strcmp(argv[1], disables[i])) {
+			res = 1;
+			break;
+		}
+
+	setAVSConfig(res);
+#else
+	printf("not supported\n");
+#endif
+	return CMD_RET_SUCCESS;
+}
+
+static int
+do_pmc_sc_closeavs(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+#if IS_BCMCHIP(63138) || IS_BCMCHIP(63148) || IS_BCMCHIP(4908) || \
+			IS_BCMCHIP(63158) || defined(PMC_IMPL_3_X)
+	int res;
+	uint32_t island = 0;
+	uint16_t margin_mv_slow;
+	uint16_t margin_mv_fast;
+	uint16_t maximum_mv = 0;
+	uint16_t minimum_mv = 0;
+
+	if (!(argc == 4 || argc == 3
+#if IS_BCMCHIP(63158) || defined(PMC_IMPL_3_X)
+		|| argc == 6 || argc == 5
+#endif
+		)) {
+		printf("invalid number of parameters\n");
+		return CMD_RET_SUCCESS;
+	}
+
+	switch (argc) {
+	case 3:
+	case 5:
+		margin_mv_slow = (uint16_t)simple_strtol(argv[1], NULL, 0);
+		margin_mv_fast = (uint16_t)simple_strtol(argv[2], NULL, 0);
+		if (argc == 3)
+			break;
+		maximum_mv = (uint16_t)simple_strtol(argv[3], NULL, 0);
+		minimum_mv = (uint16_t)simple_strtol(argv[4], NULL, 0);
+		break;
+	case 4:
+	case 6:
+		island = (uint32_t)simple_strtol(argv[1], NULL, 0);
+		margin_mv_slow = (uint16_t)simple_strtol(argv[2], NULL, 0);
+		margin_mv_fast = (uint16_t)simple_strtol(argv[3], NULL, 0);
+		if (argc == 4)
+			break;
+		maximum_mv = (uint16_t)simple_strtol(argv[4], NULL, 0);
+		minimum_mv = (uint16_t)simple_strtol(argv[5], NULL, 0);
+		break;
+	}
+
+	if (minimum_mv && maximum_mv && (minimum_mv > maximum_mv)) {
+		printf("invalid parameters: min %d > max %d "
+				"and not firmware default\n",
+				minimum_mv, maximum_mv);
+		return CMD_RET_SUCCESS;
+	}
+
+	printf("closeavs with [island %d] margin_mv slow %d fast %d"
+#if IS_BCMCHIP(63158) || defined(PMC_IMPL_3_X)
+		"\n  [max_mv %d min_mv %d (0 means using firmware default)]"
+#endif
+		" ...\n", island, (short) margin_mv_slow, (short) margin_mv_fast
+#if IS_BCMCHIP(63158) || defined(PMC_IMPL_3_X)
+		, maximum_mv, minimum_mv
+#endif
+		);
+
+	res = CloseAVS(island, margin_mv_slow, margin_mv_fast, maximum_mv, minimum_mv);
+	printf("%sed, res=%d\n", res ? "fail" : "succeed", res);
+#else
+	printf("not supported\n");
+#endif
+	return CMD_RET_SUCCESS;
+}
+
+static int
+do_pmc_sc_cmd(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	int i, res, cmd[4] = { 0 };
+
+	for (i = 0; (i < sizeof(cmd)/sizeof(cmd[0])) && (i+1 < argc); i++)
+		cmd[i] = simple_strtol(argv[i+1], NULL, 0);
+	
+	res = PMCcmd(cmd);
+	printf("res=%d rsp=[%08x %08x %08x %08x]\n",
+			res, cmd[0], cmd[1], cmd[2], cmd[3]);
+
+	return CMD_RET_SUCCESS;
+}
+
+static int
+do_pmc_sc_log(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+#if defined(PMC_RAM_BOOT) && (defined(PMC_SHARED_MEMORY) || defined(PMC_IMPL_3_X))
+	int log_type = 0;
+
+	if (argc > 1)
+		log_type = simple_strtol(argv[1], NULL, 0);
+	pmc_log(log_type);
+#endif
+	return CMD_RET_SUCCESS;
+}
+
+static int get_pvtmon_result(int select, int island, int * val)
+{
+	int res, adc = -1;
+
+	res = GetPVT(select, island, &adc);
+	if (!res)
+		*val = pmc_convert_pvtmon(select, adc);
+	return res;
+}
+
+static int
+do_pmc_sc_pvtmon(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	int select = 0;
+	int island = 0;
+	int res, val;
+
+	if (argc > 1)
+		select = simple_strtol(argv[1], NULL, 0);
+
+	if (select < 0 || select > 7) {
+		printf("invalid value for select, must be in 0 ~ 7\n");
+		return CMD_RET_SUCCESS;
+	}
+
+	if (argc > 2)
+		island = simple_strtol(argv[2], NULL, 0);
+
+	printf("get pvtmon select %d island %d ... ", select, island);
+	res = get_pvtmon_result(select, island, &val);
+	if (res)
+		printf("failed, res=%d\n", res);
+	else
+		printf("value %d.%03d %c\n",
+			val/1000, (val > 0 ? val : -val)%1000,
+			select ? 'V' : 'C');
+	return CMD_RET_SUCCESS;
+}
+
+static int
+do_pmc_sc_tracktemp(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	char *p = argc > 1 ? argv[1] : NULL;
+	int res, status = 1;
+
+	if (!p || !strcmp(p, "status")) {
+		res = pmc_get_tracktemp(&status);
+		
+		if (res)
+			printf("failed to get tracktemp status, res=%d\n", res);
+		else
+			printf("tracktemp is %s\n", status ? "on" : "off");
+
+		return CMD_RET_SUCCESS;
+	}
+	
+	if (!strcmp(p, "off")) status = 0;
+
+	res = pmc_set_tracktemp(status);
+	if (res)
+		printf("failed to set tracktemp %s, res=%d\n",
+				status ? "on" : "off", res);
+	return CMD_RET_SUCCESS;
+}
+
+static char pmc_usage[] =
+"{avs | closeavs | cmd | log | pvtmon | tracktemp}\n"
+"    - avs [enable | disable | show]\n"
+"    - closeavs [<island>] <margin_mv_slow> <margin_mv_fast>"
+#if IS_BCMCHIP(63158) || defined(PMC_IMPL_3_X)
+				" [<maximum_mv> <minimum_mv>]"
+#endif
+				"\n"
+"    - cmd <cmdnum> [<param1> [<param2> [<param3>]]]\n"
+"    - log [<logtype>]\n"
+"    - pvtmon [<select> [<island>]]\n"
+"    - tracktemp [status | on | off]\n"
+;
+
+U_BOOT_CMD_WITH_SUBCMDS(pmc, "Broadcom pmc commands", pmc_usage,
+	U_BOOT_SUBCMD_MKENT(avs, 2, 0, do_pmc_sc_avs),
+	U_BOOT_SUBCMD_MKENT(closeavs, 6, 0, do_pmc_sc_closeavs),
+	U_BOOT_SUBCMD_MKENT(cmd, 5, 0, do_pmc_sc_cmd),
+	U_BOOT_SUBCMD_MKENT(log, 2, 0, do_pmc_sc_log),
+	U_BOOT_SUBCMD_MKENT(pvtmon, 3, 0, do_pmc_sc_pvtmon),
+	U_BOOT_SUBCMD_MKENT(tracktemp, 2, 0, do_pmc_sc_tracktemp));
diff --git a/board/broadcom/bcmbca/reimage.c b/board/broadcom/bcmbca/reimage.c
new file mode 100644
index 0000000000..5b76d65b21
--- /dev/null
+++ b/board/broadcom/bcmbca/reimage.c
@@ -0,0 +1,1166 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+
+#include <asm/arch/ddr.h>
+#include <linux/ctype.h>
+#include <mtd.h>
+#include <nand.h>
+#include <stdlib.h>
+#include <string.h>
+#include <environment.h>
+#include <cli.h>
+#include <linux/bitops.h>
+#include <linux/crc32.h>
+#include <ubi_uboot.h>
+#include "bca_common.h"
+#include "bca_sdk.h"
+#include "reimage.h"
+#include "spl_env.h"
+
+static struct reimager rei = { 0 };
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak void boost_cpu_clock(void)
+{
+}
+
+int board_sdk_late_init_e(void)
+{
+	boost_cpu_clock();
+
+	/* CUSTOMIZE -- set default behavior here */
+	env_set("bootdelay", "5");
+	env_set("bootcmd", "reimage auto");
+	return 0;
+}
+
+void hook_dram_init(void)
+{
+	int shift;
+	u64 size;
+#if defined(CONFIG_BCM63138) || defined(CONFIG_BCM63148) || defined(CONFIG_BCM4908) || defined(CONFIG_BCM6858)
+	shift =
+	    (MEMC->GLB_GCFG & MEMC_GLB_GCFG_SIZE1_MASK) >>
+	    MEMC_GLB_GCFG_SIZE1_SHIFT;
+#else
+	shift =
+	    (MEMC->GLB_FSBL_STATE & MEMC_GLB_FSBL_DRAM_SIZE_MASK) >>
+	    MEMC_GLB_FSBL_DRAM_SIZE_SHIFT;
+#endif
+	size = 1 << shift;	// in MB
+	printf("DDR size from controller %dMB\n", size);
+	gd->ram_size = (phys_size_t) (size << 20);
+	gd->ram_base = 0;
+	gd->bd->bi_dram[0].start = 0;
+	gd->bd->bi_dram[0].size = (phys_size_t) gd->ram_size;
+}
+
+static int check_nv_crc(struct nvram_s *nv);
+
+static int check_nv_crc(struct nvram_s *nv)
+{
+	int orig, new;
+	printf("original CRC 0x%x\n", nv->ulCheckSum);
+	orig = nv->ulCheckSum;
+	nv->ulCheckSum = 0;
+	/* use crc32_le to get standard CRC rather than the unusual one 
+	 * used for uboot environment files */
+	new = crc32_le(0xffffffff, nv, 1024);
+	printf("computed CRC 0x%x\n", new);
+	nv->ulCheckSum = orig;
+	return (new == orig);
+}
+
+static int ubi_dev_scan(struct mtd_info *info, const char *vid_header_offset);
+
+static int ubi_dev_scan(struct mtd_info *info, const char *vid_header_offset)
+{
+	char ubi_mtd_param_buffer[80];
+	int err;
+
+	if (!vid_header_offset)
+		sprintf(ubi_mtd_param_buffer, "%s", info->name);
+	else
+		sprintf(ubi_mtd_param_buffer, "%s,%s", info->name,
+			vid_header_offset);
+
+	err = ubi_mtd_param_parse(ubi_mtd_param_buffer, NULL);
+	if (err)
+		return -err;
+
+	err = ubi_init();
+	if (err)
+		return -err;
+
+	return 0;
+}
+
+static int erase(struct mtd_info *mtd, int first, int blocks);
+
+static int erase(struct mtd_info *mtd, int first, int blocks)
+{
+	struct erase_info erase_op = { };
+	int ret;
+
+	erase_op.mtd = mtd;
+	erase_op.addr = first * mtd->erasesize;
+	erase_op.len = blocks * mtd->erasesize;
+	erase_op.scrub = 0;
+	printf("Erasing %d blocks from block %d\n", blocks, first);
+
+	while (erase_op.len) {
+		ret = mtd_erase(mtd, &erase_op);
+
+		/* Abort if its not a bad block error */
+		if (ret != -EIO)
+			break;
+
+		printf("Skipping bad block at 0x%08llx\n", erase_op.fail_addr);
+
+		/* Skip bad block and continue behind it */
+		erase_op.len -= erase_op.fail_addr - erase_op.addr;
+		erase_op.len -= mtd->erasesize;
+		erase_op.addr = erase_op.fail_addr + mtd->erasesize;
+	}
+
+	if (ret && ret != -EIO)
+		ret = -1;
+	else
+		ret = 0;
+	return (ret);
+};
+
+static int do_nvram_parse(cmd_tbl_t * cmdtp, int flag, int argc,
+			  char *const argv[]);
+static int do_prepare(cmd_tbl_t * cmdtp, int flag, int argc,
+		      char *const argv[]);
+static int do_finish(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+
+static int do_prepare(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	struct erase_info erase_op = { };
+	char more_env[1024];
+	int more_env_size;
+	int i, ret;
+	size_t sz = 0;
+	int rblk, wblk;
+	char *bp;
+	char *cp;
+	int block;
+	int err;
+	long offset;
+	if (!rei.payload_blocks) {
+		printf("parse first\n");
+		return (-1);
+	}
+	struct mtd_info *mtd = NULL;
+	wblk = rei.burn_first_start;
+	bp = rei.loader_payload =
+	    malloc(rei.blocksizeK * 1024 * rei.loader_blocks);
+	if (!bp) {
+		printf("loader payload malloc failed\n");
+		return (-1);
+	}
+	mtd_probe_devices();
+	if (rei.pure_payload_image) {
+		int count = 0;
+		int leb = 0;
+		int offset = 0;
+		int m, s;
+		m = rei.pure_payload_volume_index;
+		s = rei.ubi->volumes[m]->usable_leb_size;
+		cp = CONFIG_SYS_LOAD_ADDR;
+		for (leb = 0;
+		     leb * s < 2048 + rei.blocksizeK * 1024 * rei.loader_blocks;
+		     leb++) {
+			err =
+			    ubi_eba_read_leb(rei.ubi, rei.ubi->volumes[m], leb,
+					     cp + leb * s, 0, s, 0);
+		}
+		memcpy(rei.loader_payload, cp + 2048,
+		       rei.blocksizeK * 1024 * rei.loader_blocks);
+		printf("start of image device = 0x%x\n",
+		       2048 + rei.blocksizeK * 1024 * rei.loader_blocks);
+		leb = (2048 + rei.blocksizeK * 1024 * rei.loader_blocks) / s;
+		offset = (2048 + rei.blocksizeK * 1024 * rei.loader_blocks) % s;
+		count = 0;
+		mtd = get_mtd_device_nm("nand0");
+		if (IS_ERR_OR_NULL(mtd)) {
+			printf("failed to get mtd\n");
+			return (-1);
+		}
+		erase(mtd, rei.erase_first_start, rei.erase_first_blocks);
+		put_mtd_device(mtd);
+		while (count < rei.payload_blocks * rei.blocksizeK * 1024) {
+			cp = CONFIG_SYS_LOAD_ADDR;
+			while (((int)cp < CONFIG_SYS_LOAD_ADDR + SZ_16M)
+			       && (count <
+				   rei.payload_blocks * rei.blocksizeK *
+				   1024)) {
+				err =
+				    ubi_eba_read_leb(rei.ubi,
+						     rei.ubi->volumes[m], leb,
+						     cp, offset, s - offset, 0);
+				printf("R");
+				// printf
+				// (" leb %d off 0x%x new 0x%x count %x --> %p\n",
+				// leb, offset, s - offset, count, cp);
+				count = count + s - offset;
+				cp = cp + s - offset;
+				offset = 0;
+				leb++;
+			}
+			// printf("final cp is %p next leb %d\n", cp, leb);
+			if ((int)cp > CONFIG_SYS_LOAD_ADDR + SZ_16M) {
+				offset =
+				    s - ((int)cp -
+					 (CONFIG_SYS_LOAD_ADDR + SZ_16M));
+				leb--;
+				// printf
+				// ("adjusted offset to 0x%x and next leb to %d\n",
+				// offset, leb);
+			}
+			mtd = get_mtd_device_nm("nand0");
+			if (IS_ERR_OR_NULL(mtd)) {
+				printf("failed to get mtd\n");
+				return (-1);
+			}
+			cp = CONFIG_SYS_LOAD_ADDR;
+			while (((int)cp + mtd->erasesize) <=
+			       CONFIG_SYS_LOAD_ADDR + SZ_16M) {
+				if (wblk <
+				    (rei.burn_first_start +
+				     rei.burn_first_blocks)) {
+					if (!mtd_block_isbad
+					    (mtd, wblk * mtd->erasesize)) {
+						i = mtd_write(mtd,
+							      wblk *
+							      mtd->erasesize,
+							      mtd->erasesize,
+							      &sz, cp);
+						printf("W");
+						// printf
+						// (" 0x%x bytes at %p -> blk %d\n",
+						// sz, cp, wblk);
+						cp += sz;
+					} else {
+						printf("bad");
+					}
+					wblk++;
+				} else {
+					printf
+					    ("\nFIXME -- remainder not implemented\n");
+				}
+			}
+			put_mtd_device(mtd);
+		}
+	}
+
+	else {
+		mtd = get_mtd_device_nm("nand0");
+		if (IS_ERR_OR_NULL(mtd)) {
+			printf("failed to get mtd\n");
+			return (-1);
+		}
+		// FIXME -- loop on payload until we have enough data
+		//  first --> loader (DDR)
+		//  next --> burn_first (until exhausted)
+		//  finally --> allocate remainder and copy to DDR
+		rblk = rei.payload_start;
+		while (bp <
+		       (rei.loader_payload +
+			mtd->erasesize * rei.loader_blocks)) {
+			i = mtd_read(mtd, rblk * mtd->erasesize, mtd->erasesize,
+				     &sz,
+				     rei.loader_payload +
+				     mtd->erasesize * (rblk -
+						       rei.payload_start));
+			printf("read loader -> mem %d bytes ret %d\n", sz, i);
+			rblk++;
+			bp += sz;
+		}
+		printf("loader in memory buffer at 0x%x and size 0x%x\n",
+		       rei.loader_payload, mtd->erasesize * rei.loader_blocks);
+		erase(mtd, rei.erase_first_start, rei.erase_first_blocks);
+		// rblk = rei.payload_start + rei.loader_blocks;
+		block = rei.loader_blocks;
+		while (block < (rei.loader_blocks + rei.payload_blocks)) {
+			i = mtd_read(mtd, rblk * mtd->erasesize, mtd->erasesize,
+				     &sz, (char *)CONFIG_SYS_LOAD_ADDR);
+			printf("R");
+			if (sz) {
+				block++;
+				i = 1;
+				while (i) {
+					if (wblk <
+					    (rei.burn_first_start +
+					     rei.burn_first_blocks)) {
+						if (!mtd_block_isbad
+						    (mtd,
+						     wblk * mtd->erasesize)) {
+							i = mtd_write(mtd,
+								      wblk *
+								      mtd->
+								      erasesize,
+								      mtd->
+								      erasesize,
+								      &sz,
+								      (char *)
+								      CONFIG_SYS_LOAD_ADDR);
+							printf("W", sz, i);
+						} else {
+							printf("bad");
+						}
+						wblk++;
+					} else {
+						if (!rei.remaining_payload) {
+							rei.remaining_payload =
+							    malloc
+							    (mtd->erasesize *
+							     (rei.loader_blocks
+							      +
+							      rei.payload_blocks
+							      - block + 1));
+							rei.remaining_payload_len = 0;
+							if (!rei.
+							    remaining_payload) {
+								printf
+								    ("malloc for remaining failed\n");
+								return (1);
+							}
+						}
+						memcpy(rei.remaining_payload +
+						       rei.
+						       remaining_payload_len,
+						       (char *)
+						       CONFIG_SYS_LOAD_ADDR,
+						       mtd->erasesize);
+						rei.remaining_payload_len +=
+						    mtd->erasesize;
+						printf("M");
+						i = 0;
+					}
+				}
+			}
+			rblk++;
+
+		}
+		printf("\n");
+		put_mtd_device(mtd);
+
+	}
+
+	cp = more_env;
+
+	cp += sprintf(cp, "ethaddr=%x:%x:%x:%x:%x:%x",
+		      rei.nvram.ucaBaseMacAddr[0],
+		      rei.nvram.ucaBaseMacAddr[1],
+		      rei.nvram.ucaBaseMacAddr[2],
+		      rei.nvram.ucaBaseMacAddr[3],
+		      rei.nvram.ucaBaseMacAddr[4], rei.nvram.ucaBaseMacAddr[5]);
+	*(cp++) = '\0';
+
+	cp +=
+	    sprintf(cp,
+		    "bootcmd=printenv;run once;run check_flashback;printenv;sdk boot_img");
+	*(cp++) = '\0';
+
+	cp += sprintf(cp, "tries=3");
+	*(cp++) = '\0';
+
+	cp +=
+	    sprintf(cp,
+		    "check_flashback=test $tries -eq 0 || echo $tries ;  setexpr tries $tries - 1 ; saveenv ; test $tries -eq 0 && run do_flashback");
+	*(cp++) = '\0';
+
+	cp +=
+	    sprintf(cp,
+		    "do_flashback=echo here is where I would have run flashback");
+	*(cp++) = '\0';
+
+	cp += sprintf(cp, "once=sdk metadata 1 1;setenv once true;saveenv");
+	*(cp++) = '\0';
+
+	*(cp++) = '\0';
+	more_env_size = cp - more_env + 1;
+
+	for (bp = rei.loader_payload;
+	     bp < rei.loader_payload + mtd->erasesize * rei.loader_blocks;
+	     bp += 4096) {
+		int *tenv;
+		env_t *ep;
+		uint32_t new, crc;
+		tenv = (int *)bp;
+		printf("env check at %x\r", bp - rei.loader_payload);
+		if (tenv[0] == BOOT_MAGIC_MAGIC) {
+			printf("\nGOT IT\n");
+			ep = (env_t *) & tenv[2];
+			memcpy(&crc, &ep->crc, sizeof(crc));
+			/* specifically use uboot's env crc function
+			 * even though we have included the standard
+			 * linux crc32 */
+			new = the_env_crc32(0, ep->data, tenv[1] - 4);
+			if (new != crc) {
+				printf("bad\n");
+			} else {
+				printf("good\n");
+
+				for (i = 0; i < tenv[1] - 4; i++) {
+					if ((ep->data[i] == '\0')
+					    && (ep->data[i + 1] == '\0')) {
+						memcpy(&ep->data[i + 1],
+						       more_env, more_env_size);
+						break;
+					}
+				}
+				new = the_env_crc32(0, ep->data, tenv[1] - 4);
+				memcpy(&ep->crc, &new, sizeof(new));
+			}
+		}
+	}
+
+	printf("\n");
+	return (0);
+}
+
+static int do_finish(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	int i, ret;
+	unsigned long time_start, time_mid, time_end;
+	size_t sz = 0;
+	int rblk, wblk;
+	char *bp;
+	char cmd[256];
+	int block;
+	long offset;
+	if (!rei.payload_blocks) {
+		printf("parse first\n");
+		return (-1);
+	}
+	run_command("ubifsumount", 0);
+	run_command("ubi detach", 0);
+	struct mtd_info *mtd = NULL;
+	mtd_probe_devices();
+	mtd = get_mtd_device_nm("nand0");
+	if (IS_ERR_OR_NULL(mtd)) {
+		printf("failed to get mtd\n");
+		return (-1);
+	}
+	if (!rei.loader_payload) {
+		printf("loader payload isn't set\n");
+		return (-1);
+	}
+	time_start = get_timer(0);
+	erase(mtd, 0, rei.loader_blocks);
+	for (i = 0; i < rei.loader_blocks; i++) {
+		offset = i * mtd->erasesize;
+		ret = mtd_write(mtd,
+				i * mtd->erasesize,
+				mtd->erasesize, &sz,
+				&rei.loader_payload[i * mtd->erasesize]);
+		printf("w mem->ldr %d b ret %d\n", sz, ret);
+	}
+	erase(mtd, rei.burn_remaining_start, rei.burn_remaining_blocks);
+	wblk = rei.burn_remaining_start;
+	i = 0;
+	while (i < rei.remaining_payload_len) {
+		printf("rp %x => %d\n", i, wblk);
+		ret = mtd_write(mtd,
+				wblk * mtd->erasesize,
+				mtd->erasesize, &sz, &rei.remaining_payload[i]);
+		i += sz;
+		wblk++;
+	}
+
+	erase(mtd, rei.erase_last_start, rei.erase_last_blocks);
+	put_mtd_device(mtd);
+	time_mid = get_timer(0);
+	sprintf(cmd, "%s:%lld(loader),%lld@%lld(image)",
+		"brcmnand.0",
+		(long long)(rei.loader_blocks * (long long)mtd->erasesize),
+		(long long)(mtd->size -
+			    (rei.loader_blocks + 8) * mtd->erasesize),
+		(long long)(rei.loader_blocks * mtd->erasesize));
+	run_command("mtdparts delall", 0);
+	env_set("mtdparts", cmd);
+	run_command("mtdparts", 0);
+	if (rei.preserved_data_max_len) {
+		run_command("ubi part image", 0);
+
+		sprintf(cmd, "ubi create transition 0x%x dynamic 33",
+			rei.preserved_data_max_len);
+		run_command(cmd, 0);
+		sprintf(cmd, "ubi write 0x%x transition 0x%x",
+			rei.preserved_data, rei.preserved_data_max_len);
+		run_command(cmd, 0);
+	}
+
+	time_end = get_timer(0);
+	run_command("ubi detach", 0);
+	printf("start %ld\nsafe  %ld\ndone  %\ld\nHZ %d\n", time_start,
+	       time_mid, time_end, CONFIG_SYS_HZ);
+	return (0);
+
+}
+
+static void set_rei_ranges(int i);
+
+static void set_rei_ranges(int i)
+{
+	char *cp;
+	struct nvram_s *nv;
+	nv = &rei.nvram;
+	printf("ranges for image %d\n", i);
+	rei.erase_first_start = nv->ulNandPartOfsKb[3 - i] / rei.blocksizeK;
+	rei.erase_first_blocks = nv->ulNandPartSizeKb[3 - i] / rei.blocksizeK;
+	if (rei.erase_first_start < rei.loader_blocks) {
+		rei.burn_first_start = rei.loader_blocks;
+		rei.burn_first_blocks =
+		    rei.erase_first_blocks -
+		    (rei.loader_blocks - rei.erase_first_start);
+	} else {
+		rei.burn_first_start = rei.erase_first_start;
+		rei.burn_first_blocks = rei.erase_first_blocks;
+	}
+	if (cp = env_get("burn_first_blocks")) {
+		rei.burn_first_blocks = simple_strtoul(cp, NULL, 0);
+	}
+	printf("rei.erase_first_start=%d\n", rei.erase_first_start);
+	printf("rei.erase_first_blocks=%d\n", rei.erase_first_blocks);
+	printf("rei.burn_first_start=%d\n", rei.burn_first_start);
+	printf("rei.burn_first_blocks=%d\n", rei.burn_first_blocks);
+	rei.burn_remaining_start = nv->ulNandPartOfsKb[i] / rei.blocksizeK;
+	rei.burn_remaining_blocks = nv->ulNandPartSizeKb[i] / rei.blocksizeK;
+	if (rei.burn_remaining_start < rei.loader_blocks) {
+		rei.burn_remaining_start = rei.loader_blocks;
+		rei.burn_remaining_blocks =
+		    rei.burn_remaining_blocks -
+		    (rei.loader_blocks - rei.burn_remaining_start);
+	}
+}
+
+static int do_nvram_parse(cmd_tbl_t * cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	// int *haystack = (int *)0x1000000;
+	int i, j, k, m;
+	int ret = 0;
+	u_char *cp;
+	int blocksize;
+	int err;
+	long int needle;
+	char split[128];
+	int payload_loader_size = 0;
+	int payload_size = 0;
+	struct nvram_s *nv;
+	u_char tmp[2048];
+	// char cmd[256];
+	long int *ip;
+	struct mtd_info *mtd;
+	size_t sz = 0;
+	int crc;
+
+	memcpy(&needle, NVRAM_MAGIC, 8);
+	mtd_probe_devices();
+	mtd = get_mtd_device_nm("nand0");
+	if (IS_ERR_OR_NULL(mtd)) {
+		printf("failed to get mtd\n");
+		return (-1);
+	}
+	i = mtd_read(mtd, 0, 2 << 20, &sz, (u_char *) CONFIG_SYS_LOAD_ADDR);
+	nv = 0x1010580;
+	if (!check_nv_crc(nv)) {
+		nv = NULL;
+		for (ip = (long int *)CONFIG_SYS_LOAD_ADDR;
+		     ip < (long int *)(CONFIG_SYS_LOAD_ADDR + SZ_2M);
+		     ip = ip + (2048 / sizeof(long int))) {
+			if (*ip == needle) {
+				printf("got it %p\n", ip);
+				nv = &ip[1];
+				if (check_nv_crc(nv)) {
+					printf("nvram CRC OK\n");
+				} else {
+					printf("nvram CRC failed\n");
+				}
+			}
+		}
+	}
+	if (!nv) {
+		printf("failed\n");
+		return (1);
+	}
+	memcpy(&rei.nvram, nv, sizeof(rei.nvram));
+	printf("version %d\n", nv->version);
+	memset(tmp, 0, 24);
+	strncpy(tmp, nv->boardid, 16);
+	printf("boardid %s\n", tmp);
+	printf("bootline %s\n", nv->bootline);
+	printf("afeids %x,%x\n", nv->afeId[0], nv->afeId[1]);
+	printf("MCB %x\n", nv->ulMemoryConfig);
+	for (i = 0; i < NP_TOTAL; i++) {
+		printf("part %d offset %dK size %dK\n", i,
+		       nv->ulNandPartOfsKb[i], nv->ulNandPartSizeKb[i]);
+	}
+	memset(tmp, 0, 24);
+	strncpy(tmp, nv->szVoiceBoardId, 16);
+	printf("voiceboardid %s\n", tmp);
+
+	blocksize = mtd->erasesize;
+	rei.blocksizeK = mtd->erasesize >> 10;
+	put_mtd_device(mtd);
+	env_set("mtdids", "nand0=brcmnand.0");
+	sprintf(tmp, "%s:%dK@%dK(nvram)ro,%dK@%dK(image1)ro,%dK@%dK(image2)ro,",
+		"brcmnand.0",
+		nv->ulNandPartSizeKb[0], nv->ulNandPartOfsKb[0],
+		nv->ulNandPartSizeKb[1], nv->ulNandPartOfsKb[1],
+		nv->ulNandPartSizeKb[2], nv->ulNandPartOfsKb[2]
+	    );
+	k = nv->ulNandPartSizeKb[2] + nv->ulNandPartOfsKb[2];
+	for (i = 0; i < 3; i++) {
+		j = nv->part_info[i].size;
+		j = (j & 0xc000 == 0xc000) ? 0 : j;
+		printf("misc%d size is %d\n", i + 1, j);
+		if (j) {
+			sprintf(tmp + strlen(tmp), "%dK@%dK(misc%d),",
+				j * 1024, k, i + 1);
+			k = k + j * 1024;
+		}
+	}
+	sprintf(tmp + strlen(tmp), "%dK@%dK(data)",
+		nv->ulNandPartSizeKb[3], nv->ulNandPartOfsKb[3]
+	    );
+	printf("setting mtdparts to %s\n", tmp);
+	env_set("mtdparts", tmp);
+	run_command("mtdparts", 0);
+	sprintf(tmp, "0x%x", nv->ulNandPartSizeKb[0] * 1024);
+	env_set("nvram_size", tmp);
+	run_command("nand info", 0);
+	printf("erase block %d\n", blocksize);
+	strcpy(split, MASQ_SPLIT_A);
+	strcat(split, MASQ_SPLIT_B);
+	mtd_probe_devices();
+	for (i = 1; i < 3; i++) {
+		sprintf(tmp, "image%d", i);
+		mtd = get_mtd_device_nm(tmp);
+		if (IS_ERR_OR_NULL(mtd)) {
+			printf("failed to get mtd\n");
+			return (-1);
+		}
+		for (j = 0; j < 20; j++) {
+			// printf("read i=%d j=%d\n",i,j);
+			ret = mtd_read(mtd, j * blocksize, 2048, &sz, tmp);
+			// printf("ret %d read %d\n",ret,sz);
+			if (0 == strncmp(split, tmp, strlen(split) + 1)) {
+				printf("found image%d block %d\n", i, j);
+				cp = &tmp[strlen(split) + 1];
+				payload_loader_size =
+				    simple_strtoul(cp, NULL, 0);
+				cp = cp + strlen(cp) + 1;
+				payload_size = simple_strtoul(cp, NULL, 0);
+				printf("loader size %d payload size %d\n",
+				       payload_loader_size, payload_size);
+				rei.loader_blocks =
+				    payload_loader_size / blocksize;
+				rei.payload_blocks = payload_size / blocksize;
+				rei.split_image_start =
+				    (nv->ulNandPartOfsKb[i] / rei.blocksizeK);
+				rei.split_image_end =
+				    (nv->ulNandPartOfsKb[i] +
+				     nv->ulNandPartSizeKb[i]) / rei.blocksizeK -
+				    1;
+				rei.payload_start =
+				    (nv->ulNandPartOfsKb[i] / rei.blocksizeK) +
+				    j + 1;
+/////
+				set_rei_ranges(i);
+				i = j = 30;
+				break;
+			}
+
+		}
+		put_mtd_device(mtd);
+		/* the following will probably be removed ...  reimage will always be packaged as a split image */
+		/* if we do keep it, after attaching, it needs to check for volumes other than the rootfs */
+		/* or the number of volumes */
+		if ((0 == 1) && (i < 3)) {
+			if (rei.ubi)
+				ubi_exit();
+
+			rei.ubi = NULL;
+			/* didn't find marker yet */
+			err = ubi_dev_scan(mtd, NULL);
+			if (err) {
+				printf("UBI init error %d\n", err);
+				printf
+				    ("Please check, if the correct MTD partition is used (size big enough?)\n");
+			}
+
+			rei.ubi = ubi_devices[0];
+
+			sprintf(tmp, "image%d", i);
+			if (rei.ubi) {
+				printf("part %s attaches as ubi\n", tmp);
+				for (m = 0; m < (rei.ubi->vtbl_slots + 1); m++) {
+					if (!rei.ubi->volumes[m])
+						continue;	/* Empty record */
+					printf("name %s\n",
+					       rei.ubi->volumes[m]->name);
+					if (0 ==
+					    strcmp("payload",
+						   rei.ubi->volumes[m]->name)) {
+						/* found payload volume */
+						rei.pure_payload_image = i;
+						rei.pure_payload_volume_index =
+						    m;
+						i = 30;
+					}
+				}
+			}
+		}
+		if (rei.pure_payload_image) {
+			int m, s, t;
+			m = rei.pure_payload_volume_index;
+			s = rei.ubi->volumes[m]->usable_leb_size;
+			err =
+			    ubi_eba_read_leb(rei.ubi, rei.ubi->volumes[m],
+					     0, CONFIG_SYS_LOAD_ADDR, 0, s, 0);
+			cp = CONFIG_SYS_LOAD_ADDR;
+			t = simple_strtoul(cp, &cp, 0);
+			rei.loader_blocks = t / blocksize;
+			printf("loader size %d is %d blocks\n", t, blocksize);
+			cp++;
+			t = simple_strtoul(cp, &cp, 0);
+			rei.payload_blocks = t / blocksize;
+			printf("payload size %d is %d blocks\n", t, blocksize);
+			set_rei_ranges(rei.pure_payload_image);
+
+		}
+
+	}
+
+	nv = &rei.nvram;
+	rei.erase_last_start =
+	    (nv->ulNandPartOfsKb[2] + nv->ulNandPartSizeKb[2]) / rei.blocksizeK;
+	rei.erase_last_blocks =
+	    ((nv->ulNandPartOfsKb[3] +
+	      nv->ulNandPartSizeKb[3]) / rei.blocksizeK) - rei.erase_last_start;
+	return (ret);
+}
+
+static int do_preserve_allocate(cmd_tbl_t * cmdtp, int flag, int argc,
+				char *const argv[]);
+
+static int do_preserve_save(cmd_tbl_t * cmdtp, int flag, int argc,
+			    char *const argv[]);
+static int do_preserve_allocate(cmd_tbl_t * cmdtp, int flag, int argc,
+				char *const argv[])
+{
+	int len;
+	char *cp;
+	len = simple_strtoul(argv[1], NULL, 0);
+	cp = malloc(len);
+	if (!cp) {
+		printf("malloc failed\n");
+		return (1);
+	}
+	cp[0] = '\0';
+	rei.preserved_data = cp;
+	rei.preserved_data_len = 0;
+	rei.preserved_data_max_len = len;
+	printf("allocated 0x%x bytes at %x\n", len, cp);
+	return (0);
+}
+
+static int do_preserve_save(cmd_tbl_t * cmdtp, int flag, int argc,
+			    char *const argv[])
+{
+	char *cp;
+	int len;
+	if (argc != 2) {
+		printf("filename required\n");
+		return (-1);
+	}
+	if (cp = env_get("filesize")) {
+		len = simple_strtoul(cp, NULL, 16);
+	} else {
+		printf("filesize in env is not set\n");
+		return (1);
+	}
+	if (rei.preserved_data_len + strlen(argv[1]) + 16 + len >
+	    rei.preserved_data_max_len) {
+		printf("allocated space exhausted\n");
+		return (1);
+	}
+	rei.preserved_data_len +=
+	    sprintf(rei.preserved_data + rei.preserved_data_len, "%s\n%d\n",
+		    argv[1], len);
+	memcpy(rei.preserved_data + rei.preserved_data_len,
+	       CONFIG_SYS_LOAD_ADDR, len);
+	rei.preserved_data_len += len;
+	*((char *)(rei.preserved_data + rei.preserved_data_len)) = '\n';
+	printf("preserved %d bytes as %s\n", len, argv[1]);
+	return (0);
+}
+
+static int do_commit(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+static int do_commit(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	struct mtd_info *mtd = NULL;
+	long offset;
+	int i;
+	size_t sz = 0;
+	int ret = 0;
+	int rblk;
+	if (!rei.loader_payload) {
+		printf("prepare revertable first\n");
+		return (-1);
+	}
+	mtd_probe_devices();
+	mtd = get_mtd_device_nm("nand0");
+	erase(mtd, rei.erase_first_start, rei.erase_first_blocks);
+	erase(mtd, rei.erase_last_start, rei.erase_last_blocks);
+	erase(mtd, 0, rei.loader_blocks);
+	rblk = 0;
+	for (i = 0; i < rei.loader_blocks; i++) {
+		if (mtd_block_isbad(mtd, (uint64_t) i * mtd->erasesize)) {
+			printf("skip bad block %d\n", i);
+		} else {
+			offset = i * mtd->erasesize;
+			ret = mtd_write(mtd,
+				i * mtd->erasesize,
+				mtd->erasesize, &sz,
+				&rei.loader_payload[rblk * mtd->erasesize]);
+				printf("w mem->ldr %d b ret %d\n", sz, ret);
+			if (ret == 0) {
+				rblk++;
+			}
+		}
+	}
+	put_mtd_device(mtd);
+	return (ret);
+}
+
+static int do_revertable(cmd_tbl_t * cmdtp, int flag, int argc,
+			 char *const argv[]);
+static int do_revertable(cmd_tbl_t * cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	struct mtd_info *mtd = NULL;
+	char *bp;
+	int rblk;
+	int i, ret = 0;
+	size_t sz = 0;
+	char more_env[1024];
+	int more_env_size;
+	// parse nvram
+	if (!rei.payload_blocks) {
+		printf("parse first\n");
+		return (-1);
+	}
+	mtd_probe_devices();
+	mtd = get_mtd_device_nm("nand0");
+	if (IS_ERR_OR_NULL(mtd)) {
+		printf("failed to get mtd\n");
+		return (-1);
+	}
+	erase(mtd, rei.split_image_start,
+	      rei.payload_start - rei.split_image_start);
+	// read loader to ddr
+	bp = rei.loader_payload =
+	    malloc(rei.blocksizeK * 1024 * rei.loader_blocks);
+	if (!bp) {
+		printf("loader payload malloc failed\n");
+		return (-1);
+	}
+	rblk = rei.payload_start;
+	while (bp < (rei.loader_payload + mtd->erasesize * rei.loader_blocks)) {
+		i = mtd_read(mtd, rblk * mtd->erasesize, mtd->erasesize,
+			     &sz,
+			     rei.loader_payload +
+			     mtd->erasesize * (rblk - rei.payload_start));
+		printf("read loader -> mem %d bytes ret %d\n", (int)sz, i);
+		rblk++;
+		bp += sz;
+	}
+	// erase start of reimage image to end of loader
+	erase(mtd, rei.payload_start, rei.loader_blocks);
+	// preserve files
+	// update loader in ddr (env)
+	reimage_env_append(&rei);
+	put_mtd_device(mtd);
+	return (ret);
+}
+
+static int do_read_recovery(cmd_tbl_t * cmdtp, int flag, int argc,
+			    char *const argv[]);
+static int do_read_recovery(cmd_tbl_t * cmdtp, int flag, int argc,
+			    char *const argv[])
+{
+	struct mtd_info *mtd = NULL;
+	char *bp;
+	int rblk;
+	int blocks;
+	int pages;
+	int chunk = 0;
+	size_t sz = 0;
+	loff_t off;
+	int i, j, n, z, ret = 0;
+	u32 *up32;
+	int block = 0;
+	int page = 0;
+	struct mtd_oob_ops oob_ops;
+	u32 spare[200];
+	mtd = get_mtd_device_nm("nand0");
+	blocks = (mtd->size / mtd->erasesize);
+	pages = (mtd->erasesize / mtd->writesize);
+	rei.recovery_chunks_list = CONFIG_SYS_LOAD_ADDR;
+	rei.recovery_data_buf =
+	    CONFIG_SYS_LOAD_ADDR + (blocks * pages +
+				    1) * sizeof(struct recovery_chunks);
+	rei.recovery_data_len = 0;
+	if (!rei.recovery_chunks_list) {
+		printf("recovery chunks  malloc failed\n");
+		return (-1);
+	}
+	printf("Flash device is %d blocks of %d pages of %d bytes\n", blocks,
+	       pages, mtd->writesize);
+	while (block < blocks) {
+		if ((block >= rei.split_image_start)
+		    && (block <= rei.split_image_end)) {
+			// printf("block %d is part of reimage\n", block);
+			block++;
+			continue;
+		}
+		off =
+		    (uint64_t) page *mtd->writesize +
+		    (uint64_t) block *mtd->erasesize;
+		if (page == 0) {
+			if (mtd_block_isbad
+			    (mtd, (uint64_t) block * mtd->erasesize)) {
+				/* check for bad block */
+				printf("block %d is bad\n", block);
+				block++;
+				continue;
+			}
+		}
+		sz = 0;
+		/* read to buffer ... may not keep it */
+		bp = rei.recovery_data_buf + rei.recovery_data_len;
+		oob_ops.mode = MTD_OPS_PLACE_OOB;
+		oob_ops.len = mtd->writesize;
+		oob_ops.retlen = 0;
+		oob_ops.ooblen = mtd->oobsize;
+		oob_ops.oobretlen = 0;
+		oob_ops.ooboffs = 0;
+		oob_ops.datbuf = bp;
+		oob_ops.oobbuf = spare;
+		i = mtd_read_oob(mtd, off, &oob_ops);
+		sz = oob_ops.retlen;
+
+		n = 0;
+		j = 0;
+		if (i != 0) {
+			printf("%d/%d return %d sz %d\n", block, page, i, sz);
+		}
+		if (page == 0) {
+			//printf("%d/%d  ", block, page, i, sz);
+			printf(".");
+			// printf("%d/%d r %d sz %d", block, page, i, sz);
+		}
+		while ((n < 2) && (j < sz)) {
+			up32 = bp + j;
+			n = n + 32 - generic_hweight32(*up32);
+			j = j + 4;
+			/* check if not blank ... otherwise read oob too */
+		}
+		if (page == 0) {
+			// printf(" zeros %d", n);
+		}
+		z = 0;
+		if (n < 2) {
+			/* check for zeros in oob */
+			for (j = 0; j < oob_ops.oobretlen >> 2; j++) {
+				z = z + 32 - generic_hweight32(spare[j]);
+			}
+			if (page == 0) {
+				// printf(" spare zeros %d\n", z);
+			}
+		} else {
+			if (page == 0) {
+				// printf("\n");
+			}
+		}
+		/* deal with this page */
+		// if (n + z > 2) {
+		if ((i == 0) && (n != 0)) {
+			// not blank
+			rei.recovery_chunks_list[chunk].flashpage =
+			    block * pages + page;
+			rei.recovery_chunks_list[chunk].size = mtd->writesize;
+			rei.recovery_chunks_list[chunk].type = 0x00;
+			chunk++;
+			rei.recovery_data_len += mtd->writesize;
+		}
+		page = (page + 1) % pages;
+		if (page == 0) {
+			block++;
+		}
+	}
+	rei.recovery_chunks_list[chunk].type = 0x7fffffff;
+	printf("chunks %d len 0x%x\n", chunk, rei.recovery_data_len);
+	// load old blocks (everything but reimage image) to ddr
+	put_mtd_device(mtd);
+	return (ret);
+}
+
+	// erase everything except the reimage payload (after loader)
+	// burn loader
+	// attach image
+	// store preserved files
+	// store old blocks
+
+static int do_flashback(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[]);
+static int do_flashback(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	struct mtd_info *mtd = NULL;
+	long offset;
+	int i;
+	size_t sz = 0;
+	int blocks, pages;
+	int ret = 0;
+	char *bp;
+	int chunk;
+	if (rei.recovery_data_len == 0) {
+		printf("read recovery chunks first\n");
+		return (2);
+	}
+	mtd = get_mtd_device_nm("nand0");
+	blocks = (mtd->size / mtd->erasesize);
+	pages = (mtd->erasesize / mtd->writesize);
+	erase(mtd, 0, blocks);
+	chunk = 0;
+	bp = rei.recovery_data_buf;
+	while (rei.recovery_chunks_list[chunk].type < 0x1000) {
+		i = mtd_write(mtd,
+			      rei.recovery_chunks_list[chunk].flashpage *
+			      mtd->writesize, mtd->writesize, &sz, bp);
+		bp += rei.recovery_chunks_list[chunk].size;
+		chunk++;
+		printf("%d ", chunk);
+	}
+	put_mtd_device(mtd);
+}
+
+static int do_store_preserved(cmd_tbl_t * cmdtp, int flag, int argc,
+			      char *const argv[]);
+static int do_store_preserved(cmd_tbl_t * cmdtp, int flag, int argc,
+			      char *const argv[])
+{
+	char cmd[256];
+	struct mtd_info *mtd = NULL;
+	mtd = get_mtd_device_nm("nand0");
+	if (IS_ERR_OR_NULL(mtd)) {
+		printf("failed to get mtd\n");
+		return (-1);
+	}
+	sprintf(cmd, "%s:%lld(loader),%lld@%lld(image)",
+		"brcmnand.0",
+		(long long)(rei.loader_blocks * (long long)mtd->erasesize),
+		(long long)(mtd->size -
+			    (rei.loader_blocks + 8) * mtd->erasesize),
+		(long long)(rei.loader_blocks * mtd->erasesize));
+	run_command("mtdparts delall", 0);
+	env_set("mtdparts", cmd);
+	run_command("mtdparts", 0);
+	run_command("ubi part image", 0);
+	if (rei.preserved_data_max_len) {
+		sprintf(cmd, "ubi create transition 0x%x dynamic 33",
+			rei.preserved_data_max_len);
+		run_command(cmd, 0);
+		sprintf(cmd, "ubi write 0x%x transition 0x%x",
+			rei.preserved_data, rei.preserved_data_max_len);
+		run_command(cmd, 0);
+	}
+	if (rei.recovery_data_len) {
+		sprintf(cmd, "ubi create recovery 0x%x dynamic 34",
+			rei.recovery_data_len + (void *)rei.recovery_data_buf -
+			(void *)rei.recovery_chunks_list);
+		run_command(cmd, 0);
+		sprintf(cmd, "ubi write 0x%x recovery 0x%x",
+			rei.recovery_chunks_list,
+			rei.recovery_data_len + (void *)rei.recovery_data_buf -
+			(void *)rei.recovery_chunks_list);
+		run_command(cmd, 0);
+	}
+}
+
+void reimage_splice_env(struct reimager *r, char *more_env, int more_env_size)
+{
+	char *bp;
+	int i;
+	for (bp = r->loader_payload;
+	     bp <
+	     r->loader_payload + r->blocksizeK * 1024 * r->loader_blocks;
+	     bp += 4096) {
+		int *tenv;
+		env_t *ep;
+		uint32_t new, crc;
+		tenv = (int *)bp;
+		printf("env check at %x\r", bp - r->loader_payload);
+		if (tenv[0] == BOOT_MAGIC_MAGIC) {
+			printf("\nGOT IT\n");
+			ep = (env_t *) & tenv[2];
+			memcpy(&crc, &ep->crc, sizeof(crc));
+			/* specifically use uboot's env crc function
+			 * even though we have included the standard
+			 * linux crc32 */
+			new = the_env_crc32(0, ep->data, tenv[1] - 4);
+			if (new != crc) {
+				printf("bad\n");
+			} else {
+				printf("good\n");
+
+				for (i = 0; i < tenv[1] - 4; i++) {
+					if ((ep->data[i] == '\0')
+					    && (ep->data[i + 1] == '\0')) {
+						memcpy(&ep->data[i + 1],
+						       more_env, more_env_size);
+						break;
+					}
+				}
+				new = the_env_crc32(0, ep->data, tenv[1] - 4);
+				memcpy(&ep->crc, &new, sizeof(new));
+			}
+		}
+	}
+}
+
+static char usage[] = "line 1...\n" "line 2...\n";
+
+U_BOOT_CMD_WITH_SUBCMDS(safeimage, "safe reimage commands", usage,
+			U_BOOT_SUBCMD_MKENT(commit, 5, 0, do_commit),
+			U_BOOT_SUBCMD_MKENT(flashback, 5, 0, do_flashback),
+			U_BOOT_SUBCMD_MKENT(read_recovery, 5, 0,
+					    do_read_recovery),
+			U_BOOT_SUBCMD_MKENT(revertable, 5, 0, do_revertable),
+			U_BOOT_SUBCMD_MKENT(nvram, 1, 0, do_nvram_parse),
+			U_BOOT_SUBCMD_MKENT(store_preserved, 1, 0,
+					    do_store_preserved));
+
+U_BOOT_CMD_WITH_SUBCMDS(reimage, "reimage commands", usage,
+			U_BOOT_SUBCMD_MKENT(auto, 1, 0, do_reimage_auto),
+			U_BOOT_SUBCMD_MKENT(finish, 5, 0, do_finish),
+			U_BOOT_SUBCMD_MKENT(prepare, 5, 0, do_prepare),
+			U_BOOT_SUBCMD_MKENT(nvram, 1, 0, do_nvram_parse));
+
+U_BOOT_CMD_WITH_SUBCMDS(preserve, "preserve data commands", usage,
+			U_BOOT_SUBCMD_MKENT(allocate, 5, 0,
+					    do_preserve_allocate),
+			U_BOOT_SUBCMD_MKENT(save, 5, 0, do_preserve_save));
diff --git a/board/broadcom/bcmbca/reimage.h b/board/broadcom/bcmbca/reimage.h
new file mode 100644
index 0000000000..f45e652493
--- /dev/null
+++ b/board/broadcom/bcmbca/reimage.h
@@ -0,0 +1,103 @@
+
+#include <cli.h>
+
+#define NVRAM_MAGIC "nVrAmDaT"
+#define MASQ_SPLIT_A "ImageFollows - e62b6965f01ec7e98fcde8ee1de"
+#define MASQ_SPLIT_B "57bfa9bc4e2e4eb5cee95406d5337ed9355da"
+
+#define NP_TOTAL 5
+
+struct allocs_dhd {
+	unsigned char dhd_size[3];
+	unsigned char reserved;
+};
+
+struct nvram_s {
+	unsigned int version;
+	char bootline[256];
+	char boardid[16];
+	unsigned int ulMainTpNum;
+	unsigned int ulPsiSize;
+	unsigned int ulNumMacAddrs;
+	unsigned char ucaBaseMacAddr[6];
+	char pad;
+	char backupPsi;	 /**< if 0x01, allocate space for a backup PSI */
+	unsigned int ulCheckSumV4;
+	char dummy1[292];
+	unsigned int ulNandPartOfsKb[NP_TOTAL];
+	unsigned int ulNandPartSizeKb[NP_TOTAL];
+	char szVoiceBoardId[16];
+	unsigned int afeId[2];
+	unsigned short opticRxPwrReading;	// optical initial rx power reading
+	unsigned short opticRxPwrOffset;	// optical rx power offset
+	unsigned short opticTxPwrReading;	// optical initial tx power reading
+	unsigned char ucUnused2[58];
+	unsigned char ucFlashBlkSize;
+	unsigned char ucAuxFSPercent;
+	unsigned char ucUnused3[2];
+	unsigned int ulBoardStuffOption;	// board options. bit0-3 is for DECT
+	unsigned int reserved2;
+	unsigned int ulMemoryConfig;
+	struct partition_info {
+		/*
+		   2MSB represent the
+		   00 = MB
+		   01 = GB
+		   10 = reserved
+		   11 = reserved
+		   14LSB represent multiple of 2MSB
+		 */
+
+		unsigned short size;
+	} part_info[4];
+	struct allocs_dhd alloc_dhd;
+
+	/* Add any new non-secure related elements here */
+	unsigned int ulFeatures;	// feature bitmask
+	char chUnused[268];	/* Adjust chUnused such that everything above + chUnused[] + ulCheckSum = 1k */
+	unsigned int ulCheckSum;
+};
+
+struct recovery_chunks {
+	int flashpage;		// page in flash
+	int size;		// number of bytes before fill
+	int type;		// 0x0= fill with 0xff, 0x1 = fill with 0x00, 0x7fffffff = END
+};
+
+static struct reimager {
+	// layout items
+	int loader_blocks;	// number of erase blocks in loader IMAGE
+	int split_image_start;	// start of image partition in blocks
+	int split_image_end;	// end of image partition in blocks
+	int payload_start;	// actual block number where payload starts in flash
+	int payload_blocks;	// this will be after decompression if stored compressed
+	int erase_first_start;	// the old linux image erase block start
+	int erase_first_blocks;	// old linux image erase block size 
+	int burn_first_start;	// the old linux image, but after loader (erase block number)
+	int burn_first_blocks;	// number of erase blocks usable once erase_first is erased
+	int burn_remaining_start;	// starting erase block where we can write once we have erased all
+	int burn_remaining_blocks;	// number of blocks available where we can write once we have erased
+	int erase_last_start;	// starting EB to be erased after everything is written
+	int erase_last_blocks;	// number of EBs to erase last
+	// bookkeeping
+	int blocksizeK;
+	char *remaining_payload;	// buffer for EBs that are part of payload and didn't fit in burn_first
+	int remaining_payload_len;	// length of payload held in remaining_payload[]
+	char *loader_payload;	// in-memory copy of loader
+	char *preserved_data;	// buffer for preserved data (filename\0hexlength\0data)...
+	int preserved_data_len;	// number of bytes of buffered preserved data
+	int preserved_data_max_len;	// allocated max preserved data
+	struct recovery_chunks *recovery_chunks_list;
+	char *recovery_data_buf;
+	int recovery_data_len;
+	struct nvram_s nvram;	// in-memory copy of nvram
+	struct ubi_device *ubi;
+	int pure_payload_image;	// if using pureubi, select payload image
+	int pure_payload_volume_index;	// if using pureubi payload volume index
+
+};
+
+int do_reimage_auto(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+
+void reimage_splice_env(struct reimager *r, char *more_env, int more_env_size);
+void reimage_env_append(struct reimager *r);
diff --git a/board/broadcom/bcmbca/reimage_bcmref.c b/board/broadcom/bcmbca/reimage_bcmref.c
new file mode 100644
index 0000000000..e14050d40b
--- /dev/null
+++ b/board/broadcom/bcmbca/reimage_bcmref.c
@@ -0,0 +1,78 @@
+
+#include <common.h>
+#include <cli.h>
+#include <string.h>
+#include "reimage.h"
+
+int do_reimage_auto(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	/* CUSTOMIZE -- Sequence of commands to run automatically */
+	run_command("safeimage nvram", 0);
+	run_command("safeimage revertable", 0);
+	run_command("preserve allocate 0x80000", 0);
+	run_command("setenv partition data", 0);
+	run_command("fsload newkey.key && preserve save /data/newkey.key", 0);
+	run_command("fsload newkey && preserve save /data/newkey", 0);
+	run_command("fsload newkey.cert && preserve save /data/newkey.cert", 0);
+	run_command("fsload psi && preserve save /data/psi", 0);
+	run_command("fsload scratchpad && preserve save /data/scratchpad", 0);
+	run_command
+	    ("fsload .kernel_nvram.setting && preserve save /data/.kernel_nvram.setting",
+	     0);
+	run_command("nand read 0x1000000 nvram", 0);	/* must be last before commit */
+	run_command("safeimage commit", 0);
+	run_command("safeimage store_preserved", 0);
+	run_command("ubi create cfe_nvram $nvram_size static 52", 0);
+	run_command("ubi write 0x1000000  cfe_nvram $nvram_size", 0);
+	run_command("reset", 0);
+	return (0);
+}
+
+void reimage_env_append(struct reimager *r)
+{
+	char more_env[1024];
+	char tmp1[128];
+	char tmp2[128];
+	char *bp;
+	char *cp;
+	int more_env_size;
+	int i;
+	cp = more_env;
+
+	/* CUSTOMIZE THIS-- whatever needs to be transferred from NVRAM to the uboot environment, put it here */
+	/* START */
+	printf("cfe_bootline=%s\n", r->nvram.bootline);
+	tmp2[0] = '\0';
+	bp = strtok(r->nvram.bootline, "= ");	/* skip to e= */
+	bp = strtok(NULL, "= ");	/* find the address after e= to space */
+	strcpy(tmp1, bp);
+	bp = strtok(NULL, "= ");	/* skip to h= */
+	bp = strtok(NULL, "= ");	/* find the address after h= to space */
+	strcpy(tmp2, bp);
+	bp = strtok(NULL, "^");
+	cp += sprintf(cp, "ipaddr=%s", tmp1);
+	*(cp++) = '\0';
+	cp += sprintf(cp, "serverip=%s", tmp2);
+	*(cp++) = '\0';
+	cp += sprintf(cp, "MCB=0x%x", r->nvram.ulMemoryConfig);
+	*(cp++) = '\0';
+	cp += sprintf(cp, "ethaddr=%x:%x:%x:%x:%x:%x",
+		      r->nvram.ucaBaseMacAddr[0],
+		      r->nvram.ucaBaseMacAddr[1],
+		      r->nvram.ucaBaseMacAddr[2],
+		      r->nvram.ucaBaseMacAddr[3],
+		      r->nvram.ucaBaseMacAddr[4], r->nvram.ucaBaseMacAddr[5]);
+	*(cp++) = '\0';
+
+	cp += sprintf(cp, "bootcmd=printenv;run once;sdk boot_img");
+	*(cp++) = '\0';
+
+	cp += sprintf(cp, "once=sdk metadata 1 1;setenv once true;saveenv");
+	*(cp++) = '\0';
+
+	*(cp++) = '\0';
+	/* END */
+
+	more_env_size = cp - more_env + 1;
+	reimage_splice_env(r, more_env, more_env_size);
+}
diff --git a/board/broadcom/bcmbca/reimage_flashback.c b/board/broadcom/bcmbca/reimage_flashback.c
new file mode 100644
index 0000000000..1461c71290
--- /dev/null
+++ b/board/broadcom/bcmbca/reimage_flashback.c
@@ -0,0 +1,85 @@
+
+#include <common.h>
+#include <cli.h>
+#include <string.h>
+#include "reimage.h"
+
+int do_reimage_auto(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	/* CUSTOMIZE -- Sequence of commands to run automatically */
+	run_command("safeimage nvram", 0);
+	run_command("safeimage revertable", 0);
+	run_command("preserve allocate 0x80000", 0);
+	run_command("setenv partition data", 0);
+	run_command("fsload newkey.key && preserve save /data/newkey.key", 0);
+	run_command("fsload newkey && preserve save /data/newkey", 0);
+	run_command("fsload newkey.cert && preserve save /data/newkey.cert", 0);
+	run_command("fsload psi && preserve save /data/psi", 0);
+	run_command("fsload scratchpad && preserve save /data/scratchpad", 0);
+	run_command
+	    ("fsload .kernel_nvram.setting && preserve save /data/.kernel_nvram.setting",
+	     0);
+	run_command("safeimage read_recovery nvram", 0);	/* must be last before commit */
+	run_command("safeimage commit", 0);
+	run_command("safeimage store_preserved", 0);
+	run_command("reset", 0);
+	return (0);
+}
+
+void reimage_env_append(struct reimager *r)
+{
+	char more_env[1024];
+	char tmp1[128];
+	char tmp2[128];
+	char *bp;
+	char *cp;
+	int more_env_size;
+	int i;
+	cp = more_env;
+
+	/* CUSTOMIZE THIS-- whatever needs to be transferred from NVRAM to the uboot environment, put it here */
+	/* START */
+	printf("cfe_bootline=%s\n", r->nvram.bootline);
+	tmp2[0] = '\0';
+	bp = strtok(r->nvram.bootline, "= ");	/* skip to e= */
+	bp = strtok(NULL, "= ");	/* find the address after e= to space */
+	strcpy(tmp1, bp);
+	bp = strtok(NULL, "= ");	/* skip to h= */
+	bp = strtok(NULL, "= ");	/* find the address after h= to space */
+	strcpy(tmp2, bp);
+	bp = strtok(NULL, "^");
+	cp += sprintf(cp, "ipaddr=%s", tmp1);
+	*(cp++) = '\0';
+	cp += sprintf(cp, "serverip=%s", tmp2);
+	*(cp++) = '\0';
+	cp += sprintf(cp, "MCB=0x%x", r->nvram.ulMemoryConfig);
+	*(cp++) = '\0';
+	cp += sprintf(cp, "ethaddr=%x:%x:%x:%x:%x:%x",
+		      r->nvram.ucaBaseMacAddr[0],
+		      r->nvram.ucaBaseMacAddr[1],
+		      r->nvram.ucaBaseMacAddr[2],
+		      r->nvram.ucaBaseMacAddr[3],
+		      r->nvram.ucaBaseMacAddr[4], r->nvram.ucaBaseMacAddr[5]);
+	*(cp++) = '\0';
+
+	cp += sprintf(cp, "bootcmd=printenv;run once;run check_flashback;sdk boot_img");
+	*(cp++) = '\0';
+
+	cp += sprintf(cp, "tries=3");
+	*(cp++) = '\0';
+
+	cp += sprintf(cp, "check_flashback=test $tries -eq 0 || echo $tries ;  setexpr tries $tries - 1 ; saveenv ; test $tries -eq 0 && run do_flashback");
+	*(cp++) = '\0';
+
+	cp += sprintf(cp, "do_flashback=ubi part image && ubi read 0x1000000 recovery && flashback_ops go_flashback && reset");
+	*(cp++) = '\0';
+
+	cp += sprintf(cp, "once=sdk metadata 1 1;setenv once true;saveenv");
+	*(cp++) = '\0';
+
+	*(cp++) = '\0';
+	/* END */
+
+	more_env_size = cp - more_env + 1;
+	reimage_splice_env(r, more_env, more_env_size);
+}
diff --git a/board/broadcom/bcmbca/reset_button.c b/board/broadcom/bcmbca/reset_button.c
new file mode 100644
index 0000000000..ed2618e32d
--- /dev/null
+++ b/board/broadcom/bcmbca/reset_button.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include "bcmbca_button.h"
+
+#define DEFAULT_RESET_CMD	"sdk restoredefault;reset"
+
+static void btn_hook_rst_to_dflt(unsigned long time, void *param)
+{
+	if (param) {
+		run_command((char *)param, 0);
+	} else {
+		/* stop the auto boot as the default rst button behavior */
+		run_command(DEFAULT_RESET_CMD, 0);
+	}
+}
+
+static void btn_hook_reset_release(unsigned long time, void *param)
+{
+ 	if (param) {
+		run_command((char *)param, 0);
+	}
+}
+
+
+/* 
+ * u-boot button drv uses release event to support multiple press action with
+ * different length of press time. Using the example below, if user press and
+ * hold reset button for more than 5s but less 10s, the default_cmd action
+ * will be taken.  If user press and hold longer than 10s then release, the
+ * recovery action will be taken.  If user press and never release the button,
+ * u-boot boot will stuck and wait for user to release the botton
+ *
+ * User can add more action items with different wait length. Button drv 
+ * enumerate all of them when registering action for release event.
+ *
+ * If release action is not specified, it fallbacks to hold rst_to_dflt action
+ * 
+ *		reset_button {
+ *			press {
+ *				print = "Button Press -- Hold for 5s to do restore to default";
+ *			};
+ *			hold {
+ *				rst_to_dflt = <5>;
+ *			};
+ *			release {
+ *				reset = <0>;
+ *				default = < 5>;
+ *				default_cmd= "sdk restoredfaults ; sdk boot_image";
+ *				recovery = <10>;
+ *				recovery_cmd = "setenv ipaddr 192.168.1.1; setenv netmask 255.0.0.0 ; sdk httpd_start ; sdk poll_bg";
+ *			};	
+ *		};
+ */
+
+int reset_button_init(void)
+{
+	int ret;
+
+	ret = register_button_action_for_event("reset_button", "release", NULL,
+			btn_hook_reset_release);
+	/* if board does not use release event for the reset button, fallback
+	   default hold event */
+	if (ret <= 1) {
+		ret = register_button_action("reset_button", "rst_to_dflt",
+			btn_hook_rst_to_dflt);
+		if (ret < 0) {
+			printk("Failed to register rst_to_dflt action rc %d\n", ret);
+			return -1;
+		}
+	}
+
+	return 0;
+}
diff --git a/board/broadcom/bcmbca/sdk_test_commands.c b/board/broadcom/bcmbca/sdk_test_commands.c
new file mode 100644
index 0000000000..3724f5e1f9
--- /dev/null
+++ b/board/broadcom/bcmbca/sdk_test_commands.c
@@ -0,0 +1,3010 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019
+ * Broadcom Corp
+ */
+
+#include <stdlib.h>
+#include <command.h>
+#include <common.h>
+#include <environment.h>
+#include <hexdump.h>
+#include <ubi_uboot.h>
+#include <cli.h>
+#include <console.h>
+#include "bca_common.h"
+#include "bcm_bootstate.h"
+#include "spl_env.h"
+#include "bca_sdk.h"
+#include "bcm_secure.h"
+#include "httpd/bcmbca_net.h"
+#include <nand.h>
+#include <mmc.h>
+#if defined(CONFIG_WDT)
+#include <wdt.h>
+#endif
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#endif
+
+#define SIZE_OVERHEAD		0x100000UL	//1M
+#define BOOTFS_SIZE_BYTES	0x00A00000UL	//10M
+#define ROOTFS_SIZE_BYTES	0x02800000UL	//40M
+#define SQUASHFS_MAGIC		0x73717368
+#define UBIFS_MAGIC		0x06101831
+#define MIN_IMG_INDEX		1
+#define MAX_IMG_INDEX		2
+
+#define atoi(s) simple_strtol(s, NULL, 0)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Flag indicating whether we want to force an update and disregard any compatibility checks */
+static int forced_updates = 0;
+static char forced_image_media[256] = {0};
+static char forced_boot_media[256] = {0};
+/* Flag to prevent synching of runtime env to loader bin when flashing a new loader */
+static int disable_runtime_env_sync = 0;
+
+typedef int (*flash_fn)( ulong addr, ulong size , int img_index);
+
+typedef struct {
+	char name[20]; /* Name of upgrade bundle component */
+	flash_fn func; /* Function to flash this upgrade bundle component */
+} flashfn_table_entry;
+
+/* Enable CLI commands based on included CMD modules */
+#if defined(CONFIG_CMD_GPT) && defined(CONFIG_CMD_PART) && defined(CONFIG_CMD_MMC) && defined(CONFIG_MMC)
+#define BCA_SDK_EMMC_CMD	1
+#endif
+
+#if defined(CONFIG_CMD_UBI) && defined(CONFIG_CMD_MTD) && defined(CONFIG_NAND)
+#define BCA_SDK_NAND_CMD	1
+#endif
+
+#if defined(CONFIG_CMD_SF) && defined(CONFIG_SPI_FLASH) && defined(CONFIG_DM_SPI_FLASH) && defined(CONFIG_CMD_MTD)
+#define BCA_SDK_SPINOR_CMD	1
+#endif
+
+#if defined(BCA_SDK_SPINOR_CMD)
+static int spinor_load_bootfs(uint32_t bootfs_load_addr ); 
+static int spinor_restoredefault(void);
+static int write_spinor_partition( char *const partitionname, ulong addr, ulong size );
+static int do_flash_spinor_binary(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+static int do_flash_spinor_bootfs_rootfs(cmd_tbl_t * cmdtp, int flag, int argc,	char *const argv[]);
+static int flash_loader_spinor( ulong addr, ulong size);
+#endif
+#ifdef BCA_SDK_EMMC_CMD
+/* EMMC specific routines */
+static int flash_rootfs_emmc( ulong addr, ulong size, int img_index );
+static int flash_bootfs_emmc( ulong addr, ulong size, int img_index );
+static int flash_loader_emmc( ulong addr, ulong size, int img_index );
+static int set_emmc_metadata( char* metadata, int size );
+static int get_emmc_metadata( char* metadata, int size );
+static int emmc_load_bootfs( int img_index, uint32_t bootfs_load_addr ); 
+static int emmc_rdwr_userdata_part( char * part_name, ulong addr, ulong size, int write );
+static int emmc_rdwr_boot_part( ulong addr, ulong size, int img_index, int write );
+static int emmc_restoredefault(void);
+static int emmc_do_gpt_fixup(void);
+#endif /* BCA_SDK_EMMC_CMD */
+
+#ifdef BCA_SDK_NAND_CMD
+/* NAND Specific routines */
+static int flash_rootfs_nand( ulong addr, ulong size, int img_index );
+static int flash_bootfs_nand( ulong addr, ulong size, int img_index );
+static int flash_loader_nand( ulong addr, ulong size, int img_index );
+static int set_nand_metadata( char* metadata, int size );
+static int get_nand_metadata( char* metadata, int size );
+static int nand_load_fit( int img_index, uint32_t fit_load_addr );
+static int nand_load_bootfs( int img_index, uint32_t bootfs_load_addr );
+static int nand_restoredefault(void);
+#endif /* BCA_SDK_NAND_CMD */
+
+/* Generic routines */
+static unsigned int bcm_handle_mapper(void* fit, char *flash_device, char *flash_opts);
+static int update_flash_parts_from_loader_bin( ulong loader_addr, ulong loader_size );
+static int get_binary_from_bundle( ulong bundle_addr, char * conf_name, char * name, 
+	char ** bin_name, ulong * addr, ulong * size );
+static int sync_update_loader_bin_env(ulong loader_addr);
+static int verify_compat_string( const char * compat_str );
+static int do_flash_bins(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+static int do_boot(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+static int do_load(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+static int load_linux_img(int flag, int argc, char *const argv[]);
+static int do_restoredefault(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+static int do_metadata(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+static int do_force(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+static int flash_rootfs( ulong addr, ulong size , int img_index);
+static int flash_bootfs( ulong addr, ulong size , int img_index);
+static int flash_loader( ulong addr, ulong size , int img_index);
+static int do_flash_loader(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+static int do_flash_bootfs_rootfs( char * bootfs_filename, char * rootfs_filename, int image_index );
+static int do_flash_upgrade_img (cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+static int set_metadata_val( int * committed, int * valid, int * seq );
+static int get_metadata_val( int * committed, int * valid, int * seq );
+static int do_activate(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+char * get_loader_media(void);
+static char * get_image_media(void);
+static int get_active_img_idx(void);
+static int set_active_img_idx( int img_idx);
+#ifdef CONFIG_BCMBCA_HTTPD
+static int do_httpd_start(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+#endif
+#ifdef CONFIG_BCMBCA_XRDP_ETH
+static int do_eth_active_port(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+#endif
+
+/* Local Variables */
+static flashfn_table_entry fn_table[] =  {
+	{ "bootfs", flash_bootfs },
+	{ "rootfs", flash_rootfs },
+	{ "loader", flash_loader }
+};
+
+#ifdef CONFIG_BCMBCA_BOARD_SPECIFIC_DT
+#define BCMBCA_BOARDID_MAXSIZE	28
+#define BCMBCA_VOICEBOARDID_MAXSIZE	BCMBCA_BOARDID_MAXSIZE
+#include "spl_ddrinit.h"
+static int on_boardid(const char *name, const char *value, enum env_op op, int flags)
+{
+	char boardid[BCMBCA_BOARDID_MAXSIZE+4];
+	int ret = 0;
+	int img_index = 0;
+	long conf, node, offset;
+	uint32_t env_mcb;
+
+	if (forced_updates || ((flags & H_INTERACTIVE) == 0))
+		return 0;
+
+	switch (op) {
+	case env_op_create:
+	case env_op_overwrite:
+		img_index = get_active_img_idx();
+		if((img_index < MIN_IMG_INDEX) || (img_index > MAX_IMG_INDEX)) 
+			img_index = MIN_IMG_INDEX;
+		/* Load bootfs to load address */
+		if(  strcasecmp(get_image_media(), FLASH_DEV_STR_NAND) == 0 )  {
+#ifdef BCA_SDK_NAND_CMD
+			if (nand_load_fit(img_index, load_addr))
+			{
+				printf("Failed to load bootfs\n");
+				return 0;
+			}
+#endif
+		}
+
+		if( ( strcasecmp(get_image_media(), FLASH_DEV_STR_EMMC) == 0 ) ) {
+#ifdef BCA_SDK_EMMC_CMD
+			ret = emmc_load_bootfs(img_index, load_addr);
+			if (ret)
+			{
+				printf("Failed to load bootfs\n");
+				return 0;
+			}
+#endif
+		}
+    
+		conf = fdt_path_offset((void*)load_addr, FIT_IMAGES_PATH);
+		if (conf < 0) {
+			printf("Cannot find /images node: %ld\n", conf);
+			return 0;
+		}
+
+		if (strlen(value) > BCMBCA_BOARDID_MAXSIZE)
+		{
+			printf("boardid is too long, max size is %d\n", BCMBCA_BOARDID_MAXSIZE);
+			return 1;
+		}
+		sprintf(boardid,"fdt_%s", value);
+		for (node = fdt_first_subnode((const void*)load_addr, conf); node >= 0; node = fdt_next_subnode((const void*)load_addr, node))
+		{
+			const char* image_name = fit_get_name((const char*)load_addr, node, NULL);
+     
+			if (strcmp(image_name, boardid) == 0)
+			{  
+				const uint32_t* memcfg;
+				uint32_t fdt_mcb;
+				const void* fdt;
+				size_t size;
+  
+				ret = fit_image_get_data_and_size((const void*)load_addr, node, &fdt, &size);
+				if (ret)
+				{
+					printf("Failed to get FDT\n");
+					return 0;
+				}
+             
+				offset = fdt_path_offset(fdt, "/memory_controller");
+				if (offset < 0) {
+					printf("Not found memory_controller node in FDT\n");
+					return 0;
+				}                
+
+				memcfg = fdt_getprop(fdt, offset, "memcfg", NULL);
+				if (memcfg == NULL)
+				{
+					printf("Can't find memcfg parameter in DTB\n");
+					return 0;
+				}
+				fdt_mcb = be32_to_cpu(*memcfg);
+				env_mcb = env_get_hex("MCB", 0);
+				if (env_mcb & BP_DDR_CONFIG_OVERRIDE)
+				{
+					printf("MCB sticky bit is set, MCB is not updated\n Current MCB 0x%x, FDT MCB 0x%x\n", env_mcb, fdt_mcb);
+					return 0;
+				}
+				printf("Updating MCB environment from 0x%x to 0x%x\n", env_mcb, fdt_mcb);
+				env_set_hex("MCB", fdt_mcb);
+				env_set("boardid", value);
+				printf("Memory Configuration Changed -- SAVING ENV AND REBOOT NEEDED\n");				
+				return 0;
+			}
+		}
+		printf("Error: boardid %s not supported.\nList of supported boards:\n", value);
+		for (node = fdt_first_subnode((const void*)load_addr, conf); node >= 0; node = fdt_next_subnode((const void*)load_addr, node))
+		{
+			char* name = fit_get_name((const char*)load_addr, node, NULL);
+			if ((strncmp("fdt_", name, 4) == 0) && (strcmp("fdt_uboot", name)))
+				printf("%s\n", (name+4));
+		}
+		return 1;
+	case env_op_delete:
+		if (flags & H_FORCE)
+			return 0;
+
+		printf("## boardid may not be deleted\n");
+		return 1;
+	default:
+		return 0;
+	}
+}
+U_BOOT_ENV_CALLBACK(boardid, on_boardid);
+
+static int on_voiceBoardid(const char *name, const char *value, enum env_op op, int flags)
+{
+	char boardid[BCMBCA_BOARDID_MAXSIZE+4];
+	int ret = 0;
+	int img_index = 0;
+	long conf, node, offset;
+	char *pboardid;
+
+	if (forced_updates || ((flags & H_INTERACTIVE) == 0))
+		return 0;
+
+	pboardid = env_get("boardid");
+	if (!pboardid)
+	{
+		printf("boardId must be set first.\n");
+		return 1;
+	}
+
+	switch (op) {
+	case env_op_create:
+	case env_op_overwrite:
+		img_index = get_active_img_idx();
+		if((img_index < MIN_IMG_INDEX) || (img_index > MAX_IMG_INDEX)) 
+			img_index = MIN_IMG_INDEX;
+		/* Load bootfs to load address */
+		if(  strcasecmp(get_image_media(), FLASH_DEV_STR_NAND) == 0 )  {
+#ifdef BCA_SDK_NAND_CMD
+			if (nand_load_fit(img_index, load_addr))
+			{
+				printf("Failed to load bootfs\n");
+				return 0;
+			}
+#endif
+		}
+
+		if( ( strcasecmp(get_image_media(), FLASH_DEV_STR_EMMC) == 0 ) ) {
+#ifdef BCA_SDK_EMMC_CMD
+			ret = emmc_load_bootfs(img_index, load_addr);
+			if (ret)
+			{
+				printf("Failed to load bootfs\n");
+				return 0;
+			}
+#endif
+		}
+
+		conf = fdt_path_offset((void*)load_addr, FIT_IMAGES_PATH);
+		if (conf < 0) {
+			printf("Cannot find /images node: %ld\n", conf);
+			return 0;
+		}
+
+		if (strlen(value) > BCMBCA_VOICEBOARDID_MAXSIZE)
+		{
+			printf("voiceboardid is too long, max size is %d\n", BCMBCA_VOICEBOARDID_MAXSIZE);
+			return 1;
+		}
+		sprintf(boardid,"fdt_%s", pboardid);
+		for (node = fdt_first_subnode((const void*)load_addr, conf); node >= 0; node = fdt_next_subnode((const void*)load_addr, node))
+		{
+			const char* image_name = fit_get_name((const char*)load_addr, node, NULL);
+
+			if (strcmp(image_name, boardid) == 0)
+			{
+				size_t size;
+				const void* fdt;
+				int i, len, idx, slicCount;
+				const char *sliclist;
+
+				ret = fit_image_get_data_and_size((const void*)load_addr, node, &fdt, &size);
+				if (ret)
+				{
+					printf("Failed to get FDT\n");
+					return 0;
+				}
+
+				offset = fdt_path_offset(fdt, "/bcm_voice");
+				if (offset < 0) {
+					printf("Not found voice node in FDT\n");
+					return 0;
+				}                
+				idx = fdt_stringlist_search(fdt, offset, "sliclist", value);
+				/* is the string is found, save it and exit */
+				if (0 <= idx)
+				{
+					env_set("voiceboardid", value);
+					printf("-- saving env and reboot needeD\n");				
+					return 0;
+				}
+				printf("%d: %s is not found. idx=%d\n", __LINE__, value, idx);
+				slicCount = fdt_stringlist_count(fdt, offset, "sliclist");
+				printf("slicCount=%d. List of supported daughter cards:\n", slicCount);
+				for (i=0; i < slicCount; i++)
+				{
+					sliclist = fdt_stringlist_get(fdt, offset, "sliclist", i, &len);
+					if (sliclist)
+					   printf("%s\n", sliclist);
+					else
+					   printf("%d: fdt_stringlist_get failed. len=%d\n", __LINE__, len);
+				}
+				return 1;
+			}
+		}
+		return 1;
+	case env_op_delete:
+		env_set("voiceboardid", "");
+		printf("-- Saving env and reboot needed\n");				
+		return 0;
+	default:
+		return 0;
+	}
+}
+U_BOOT_ENV_CALLBACK( voiceboardid, on_voiceBoardid);
+#endif
+
+static int get_active_img_idx( void )
+{
+	int node,len;
+	unsigned int active_img_idx = 0;
+	fdt32_t * nodep = NULL;
+	node = fdt_path_offset(gd->fdt_blob, "/chosen");
+	if (node < 0) {
+		printf("Can't find /chosen node in uboot DTB\n");
+		return node;
+	}
+	nodep = (fdt32_t *)fdt_getprop(gd->fdt_blob, node, "active_image", &len);
+	active_img_idx = fdt32_to_cpu(*(fdt32_t *)nodep);
+	
+	return active_img_idx;
+}
+
+static int set_active_img_idx( int img_idx )
+{
+	int node,len;
+	fdt32_t * nodep = NULL;
+	node = fdt_path_offset(gd->fdt_blob, "/chosen");
+	int ret = -1;
+	if (node < 0) {
+		printf("Can't find /chosen node in uboot DTB, device may not boot properly!\n");
+	} else {
+		ret = fdt_setprop_u32(gd->fdt_blob, node, "active_image", img_idx);
+		if(ret)
+		{
+			printf("Could not set active image node in the fdt, device may not boot properly!\n");
+		}
+	}
+	return ret;
+}
+
+/************************************************************
+ *                Flash Specific Functions                  *
+ ************************************************************/
+#ifdef BCA_SDK_EMMC_CMD
+static int emmc_restoredefault(void)
+{
+	ulong part_size_blk, part_start_blk;
+	char cmd[128];
+	int ret = -1;
+
+	/* Switch to user data partition */
+	if ( run_command("mmc dev 0 0", 0) == 0 ) {
+		env_set("part_start_blk", NULL);
+		env_set("part_size_blk", NULL);
+		run_command("part start mmc 0 data part_start_blk", 0); 
+		run_command("part  size mmc 0 data part_size_blk", 0); 
+		part_start_blk = env_get_hex("part_start_blk", 0);
+		part_size_blk  = env_get_hex("part_size_blk", 0);
+
+		/* If data exists, delete it */
+		if( part_size_blk ) {
+			sprintf(cmd, "mmc erase 0x%lx 0x%lx", part_start_blk, part_size_blk);
+			ret = run_command(cmd, 0);
+		} else {
+			ret = 0;
+		}
+	} else {
+		printf("Error: Cannot switch to userdata partition!\n");
+	}
+
+	return ret;
+}
+
+static int emmc_rdwr_boot_part( ulong addr, ulong size, int img_index, int write )
+{
+	char cmd[128];
+	ulong num_blocks = 0;
+	ulong block_addr = 0;
+	ulong part_size_blk = 0;
+	int boot_part_num = 1;
+	int ret = -1;
+	struct mmc *mmc = NULL;
+
+	mmc = find_mmc_device(0);
+	if( !mmc ) {
+		printf("Error: Cannot access mmc device!\n");
+		goto emmc_rdwr_boot_part_exit;
+	}
+
+	/* Calculate number of blocks */
+        num_blocks = size/mmc->read_bl_len + (size%mmc->read_bl_len?1:0);
+
+	/* Determine size of raw boot partition */
+	part_size_blk = mmc->capacity_boot/mmc->read_bl_len;
+	if( num_blocks > part_size_blk ) {
+		printf("Error: Insufficient space in boot partition %d for 0x%lx blocks. Partition size is 0x%lx\n", boot_part_num, num_blocks, part_size_blk);
+		goto emmc_rdwr_boot_part_exit;
+	}
+
+	/* Switch to boot partition */
+	sprintf(cmd, "mmc dev 0 %d", boot_part_num);
+	if ( run_command(cmd, 0) ) {
+		printf("Error: Cannot switch to bootpartition %d!\n", boot_part_num);
+		goto emmc_rdwr_boot_part_exit;
+	}
+
+	/* Write to raw boot partition */
+	sprintf(cmd, "mmc %s 0x%lx 0x%lx 0x%lx", (write?"write":"read"), addr, block_addr, num_blocks);
+	ret = run_command(cmd, 0);
+	printf("%s: %s (bootp%d)\n", __FUNCTION__, cmd, boot_part_num);
+
+	/* Switch back to userdata partition */
+	run_command("mmc dev 0 0", 0); 
+
+emmc_rdwr_boot_part_exit:
+	if( ret )
+		printf("Error: Failed %s 0x%lx blocks from/to boot partition %d!\n", (write?"writing":"reading"), num_blocks, boot_part_num);
+
+	return ret;
+}
+
+static int emmc_rdwr_userdata_part( char * part_name, ulong addr, ulong size, int write )
+{
+	char cmd[128];
+	ulong num_blocks = 0;
+	ulong block_addr = 0;
+	ulong part_size_blk = 0;
+	int ret = -1;
+	struct mmc *mmc = NULL;
+
+	mmc = find_mmc_device(0);
+	if( !mmc ) {
+		printf("Error: Cannot access mmc device!\n");
+		goto emmc_rdwr_usrdata_part_exit;
+	}
+
+	/* Calculate number of blocks */
+        num_blocks = size/mmc->read_bl_len + (size%mmc->read_bl_len?1:0);
+
+	/* Switch to user data partition */
+	if ( run_command("mmc dev 0 0", 0) ) {
+		printf("Error: Cannot switch to userdata partition!\n");
+		goto emmc_rdwr_usrdata_part_exit;
+	}
+
+	/* Get GPT partition size in blocks */
+	env_set("part_size_blk", NULL);
+	sprintf(cmd, "part size mmc 0 %s part_size_blk", part_name);
+	if(run_command(cmd, 0) == 0) {
+		part_size_blk = env_get_hex("part_size_blk", 0);
+		if( num_blocks > part_size_blk ) {
+			printf("Error: Insufficient space in partition %s for 0x%lx blocks. Partition size is 0x%lx\n", part_name, num_blocks, part_size_blk);
+			goto emmc_rdwr_usrdata_part_exit;
+		}
+	} else {
+		printf("Error: Cannot determine size of GPT partition %s\n", part_name);
+		goto emmc_rdwr_usrdata_part_exit;
+	}
+
+	/* Get start block address of partition */
+	sprintf(cmd, "part start mmc 0 %s part_start_blk", part_name);
+	env_set("part_start_blk", NULL);
+	if(run_command(cmd, 0) == 0) {
+		block_addr = env_get_hex("part_start_blk", 0);
+		sprintf(cmd, "mmc %s 0x%lx 0x%lx 0x%lx", (write?"write":"read"), addr, block_addr, num_blocks);
+		ret = run_command(cmd, 0);
+		printf("%s: %s (%s)\n", __FUNCTION__, cmd, part_name);
+	} else {
+		printf("Error: Cannot determine start block of GPT partition %s\n", part_name);
+		goto emmc_rdwr_usrdata_part_exit;
+	}
+
+emmc_rdwr_usrdata_part_exit:
+	if( ret )
+		printf("Error: Failed %s 0x%lx blocks from/to GPT partition %s!\n", (write?"writing":"reading"), num_blocks, part_name);
+	return ret;
+}
+
+static int flash_rootfs_emmc( ulong addr, ulong size, int img_index )
+{
+	char part_name[128];
+	int ret = CMD_RET_FAILURE;
+
+	if( !addr || !size || img_index < MIN_IMG_INDEX || img_index > MAX_IMG_INDEX )
+		return CMD_RET_USAGE;
+
+	sprintf(part_name, "rootfs%d", img_index);
+	ret = emmc_rdwr_userdata_part( part_name, (ulong)addr, size, 1 );
+
+	return ret;
+}
+
+static int flash_bootfs_emmc( ulong addr, ulong size, int img_index )
+{
+	char part_name[128];
+	int ret = CMD_RET_FAILURE;
+
+	if( !addr || !size || img_index < MIN_IMG_INDEX || img_index > MAX_IMG_INDEX )
+		return CMD_RET_USAGE;
+
+	sprintf(part_name, "bootfs%d", img_index);
+	ret = emmc_rdwr_userdata_part( part_name, (ulong)addr, size, 1 );
+	return ret;
+}
+
+static int flash_loader_emmc( ulong addr, ulong size, int img_index )
+{
+	int ret = -1;
+
+	if( !addr || !size )
+		return CMD_RET_USAGE;
+
+	ret = emmc_rdwr_boot_part( addr, size, img_index, 1);
+
+	return ret;
+}
+
+static int set_emmc_metadata( char* metadata, int size )
+{
+	char part_name[128];
+	int ret;
+	int i;
+
+	for (i = 1; i < 3; i++) {
+		sprintf(part_name, "metadata%d", i);
+		ret = emmc_rdwr_userdata_part( part_name, (ulong)metadata, size, 1 );
+	}
+	return ret;
+}
+
+static int get_emmc_metadata( char* metadata, int size )
+{
+	int ret;
+	int committed = 0;
+	int valid[2] = {0,0};
+	int seq[2] = {-1,-1};
+	int i;
+	char part_name[128];
+
+	for (i = 1; i < 3; i++) {
+		sprintf(part_name, "metadata%d", i);
+		ret = emmc_rdwr_userdata_part( part_name, (ulong)metadata, size, 0 );
+		if (0 == validate_metadata(metadata, valid, &committed, seq)) {
+			break;
+		} else {
+			printf("metadata parse error\n");
+			ret = CMD_RET_FAILURE;
+		}
+	}
+	return ret;
+}
+
+static ulong emmc_get_bootfs_size( char * fit )
+{
+	int images_noffset;
+	int noffset;
+	int ndepth;
+	int count;
+	size_t size;
+	ulong bootfs_size = 0;
+	const void *data;
+
+	/* Find images parent node offset */
+	images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
+	if (images_noffset < 0) {
+		printf("Can't find images parent node '%s' (%s)\n",
+		       FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+		return 0;
+	}
+
+	/* Process all image subnodes */
+	for (ndepth = 0, count = 0,
+	     noffset = fdt_next_node(fit, images_noffset, &ndepth);
+			(noffset >= 0) && (ndepth > 0);
+			noffset = fdt_next_node(fit, noffset, &ndepth)) {
+		if (ndepth == 1) {
+			/*
+			 * Direct child node of the images parent node,
+			 * i.e. component image node.
+			 */
+			count++;
+
+			if (fit_image_get_data_and_size(fit, noffset, &data, &size) == 0) {
+				bootfs_size = ((ulong)data+(ulong)size) - (ulong)fit;
+			}
+		}
+	}
+	printf("Bootfs size is %lu bytes\n", bootfs_size);
+	return bootfs_size;
+}
+
+static int emmc_add_gpt_part( char * name, ulong size )
+{
+	char * current_parts = NULL;
+	char * new_parts = NULL;
+	int ret = -1;
+
+	/* Read partitions into variable */
+	env_set("current_parts", NULL);
+	run_command("gpt read mmc 0 current_parts", 0);
+	current_parts = env_get("current_parts");
+
+	if( strstr(current_parts, name) ) {
+		printf("%s: GPT partition:%s of size:%luMiB exists!\n", __FUNCTION__, name, size);
+		return 0;	
+	} else {
+		printf("%s: Adding GPT partition %s of size %luMiB\n", __FUNCTION__, name, size);
+	}
+	
+	/* Update partitions */
+	new_parts = malloc(strlen(current_parts) + 1024 );
+	if( new_parts )	{
+		sprintf(new_parts, "%sname=%s,size=%luMiB;", current_parts, name, size);
+		ret = env_set("current_parts", new_parts);
+		free(new_parts);
+		ret = run_command("gpt write mmc 0 $current_parts", 0);
+		ret = run_command("gpt verify mmc 0 $current_parts", 0);
+	} else {
+		printf("%s: Error allocating memory for partition string!\n", __FUNCTION__);
+	}
+
+	//env_set("current_parts", NULL);
+	return ret;
+
+}
+
+/* This function will create GPT partitions if it detects partition sizes specfied via
+ * uboot environment variables. The env variable name has to be in the format:
+ * 	<partition_name>_vol_size=<size in MiB>
+ * The function will then create GPT partition with name <partition_name> of size <size>
+ *
+ * NOTE: For NAND, equivalent ubi volumes are also created dynamically based on the same 
+ * uboot env variables. However, for NAND the volumes are created in the mount-fs.sh linux 
+ * startup script instead of in uboot proper.
+ */
+#define VOL_SIZE_STR "_vol_size="
+static int emmc_do_gpt_fixup(void)
+{
+	env_t *ep;
+	char *envbuf = NULL;
+	int ret = -2;
+	int elen;
+	char *config;
+	char * token = NULL;
+        char * token2 = NULL;
+        char * name;
+        int value;
+	ulong token_len = 0;
+
+	config = env_get("env_boot_magic");
+	if (NULL == config)
+	{
+		printf("env_boot_magic missing in the env\n");
+		return -1;
+	}
+	elen = simple_strtoul(config, NULL, 0);
+	elen = max(elen, CONFIG_ENV_SIZE);
+	envbuf = malloc(elen);
+	memset(envbuf, 0, elen);
+	
+	if (!envbuf)
+	{
+		printf("memory allocation failed\n");
+		return -2;
+	}
+	ep = (env_t *) (envbuf + 8);
+	ret = env_export(ep);
+
+	/* Search environment for variable names matching <part>_vol_size */
+	token = (char*)(ep->data);
+        while(strlen(token) && (ret == 0) && ((ulong)token < ((ulong)envbuf+elen)))
+        {
+		token_len = strlen(token);
+                if( (token2 = strstr(token, VOL_SIZE_STR)) )
+                {
+                        *token2 = '\0';
+                        name = token;
+                        value = atoi( (char*)((ulong)token2 + strlen(VOL_SIZE_STR)) );
+                        printf("%s: Detected env defined partition:%s, of size:%dM\n", __FUNCTION__, name, value);
+			ret = emmc_add_gpt_part(name, value);
+			ret = 0;
+                }
+                token = (char*)((ulong)token + token_len + 1);
+        }
+	free(envbuf);
+	return(ret);
+}
+
+static int do_gpt_fixup(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	return emmc_do_gpt_fixup();
+}
+
+static int emmc_load_bootfs( int img_index, uint32_t bootfs_load_addr ) 
+{
+	char cmd[128];
+	ulong size;
+	int ret = CMD_RET_FAILURE;
+	int fit_auth= -1;
+
+	/* Set rootfs volume id */
+	int rootfs_partid = (img_index == 1?IMAGE_PART_ID_1:IMAGE_PART_ID_2)+1;
+
+	/* Switch to userdata partition */
+	if( run_command("mmc dev 0 0", 0) == 0 ) {
+		//FIXME: OR skip loading if FIT is already in memory
+		//FIXME: IF FIT is loaded from flash, reverify RSA of header
+		sprintf(cmd, "bootfs%d", img_index);
+
+		/* Get FDT header */
+		size = sizeof(struct fdt_header);
+                ret = emmc_rdwr_userdata_part( cmd, (ulong)bootfs_load_addr, size, 0 );
+
+		/* Retrieve entire FIT header */
+                ret = emmc_rdwr_userdata_part( cmd, (ulong)bootfs_load_addr, 
+			bcm_sec_get_reqd_load_size((ulong)bootfs_load_addr), 0 );
+
+		if (!ret) {
+			fit_auth = bcm_sec_validate_fit((void*)bootfs_load_addr, 0x10000);
+		}
+
+		/* Determine size of bootfs from fdt_header and load it */
+		size = emmc_get_bootfs_size((void *)bootfs_load_addr);
+                ret = emmc_rdwr_userdata_part( cmd, (ulong)bootfs_load_addr, size, 0 );
+
+		/* generate mapper parameters */
+		sprintf(cmd,"/dev/mmcblk0p%d", rootfs_partid);
+
+		/* If device mapper not being used, set rootfs_opts manually */
+		if ( (bcm_handle_mapper((void*)(ulong)bootfs_load_addr, cmd, "")) != 0)
+		{
+			/* Set default bootargs */
+			sprintf(cmd, "env set -f rootfs_opts root=/dev/mmcblk0p%d", rootfs_partid);
+			run_command(cmd, 0);
+		}
+
+		if (!fit_auth) {
+			bcm_board_boot_fdt_fixup((void*)bootfs_load_addr);
+		}
+	}
+	return ret;
+}
+
+#endif /* BCA_SDK_EMMC_CMD */
+
+#ifdef BCA_SDK_NAND_CMD 
+#define EXTRA_SPC_SUFFIX_STR "_extra_space"
+static uint64_t nand_get_part_extra_bytes(char* partition_prefix)
+{
+	char var_name[128];
+	char * extra_space_str = NULL;
+	uint64_t extra_bytes = 0;
+	unsigned long iargs[4] = {0};
+	char units[4]= {0};
+	sprintf(var_name, "%s%s", partition_prefix, EXTRA_SPC_SUFFIX_STR);
+	extra_space_str = env_get(var_name);
+	if( extra_space_str ) {
+		parse_env_nums(extra_space_str, 1, iargs, units);
+		extra_bytes = ((long long)iargs[0]) << suffix2shift(units[0]);
+	}
+	if( extra_bytes < SIZE_OVERHEAD )
+		extra_bytes = SIZE_OVERHEAD;
+
+	return extra_bytes;
+}
+
+static uint64_t nand_get_avail_space(char * update_vol_name)
+{
+	int i;
+	static struct ubi_device *ubi;
+	static struct ubi_volume *vol;
+	uint64_t vol_size = 0;
+	uint64_t avail_space = 0;
+	int ret = -1;
+
+	ret = run_command("ubi part image", 0);
+	if( ret == 0 ) {
+		ubi = ubi_devices[0];
+		for (i = 0; i < (ubi->vtbl_slots + 1); i++) {
+			if (!ubi->volumes[i])
+				continue;	/* Empty record */
+			vol = ubi->volumes[i];
+			if( strcmp(vol->name,update_vol_name) == 0 ) {
+				vol_size = vol->reserved_pebs * vol->usable_leb_size;
+				break;
+			}
+		}
+		avail_space = ubi->avail_pebs * ubi->leb_size + vol_size;
+	}
+	return avail_space;
+}
+
+static int nand_restoredefault(void)
+{
+	int ret = -1;
+	if(run_command("ubi part image", 0) == 0) {
+
+		/* If data exists, delete it */
+		if(run_command("ubi check data", 0) == 0 ) {
+			ret = run_command("ubi remove data", 0);
+		} else {
+			ret = 0;
+		}
+	} else {
+		printf("Error: Cannot attach ubi!\n");
+	}
+	return ret;
+}
+
+static int flash_rootfs_nand( ulong addr, ulong size, int img_index )
+{
+	char cmd[128];
+	int ret = CMD_RET_FAILURE;
+	int rootfs_volid = (img_index == 1? IMAGE_VOL_ID_1:IMAGE_VOL_ID_2) + 1;
+	uint64_t avail_bytes = 0;
+	uint64_t extra_space_bytes = nand_get_part_extra_bytes("rootfs");
+
+	if( !addr || !size || img_index < MIN_IMG_INDEX || img_index > MAX_IMG_INDEX )
+		return CMD_RET_USAGE;
+
+	if(run_command("ubi part image", 0) == 0) {
+
+		/* check if new rootfs will fit in flash */
+		sprintf(cmd, "rootfs%d", img_index); 
+		avail_bytes =  nand_get_avail_space(cmd);
+		if( avail_bytes < size+extra_space_bytes ) {
+			printf("Error: Insufficient space in NAND for 0x%lx Bytes . Available size is 0x%llx\n", size+extra_space_bytes, avail_bytes);
+			return -1;
+		}
+
+		/* If rootfs1 exists, delete it */
+		sprintf(cmd, "ubi check rootfs%d", img_index);
+		if(run_command(cmd, 0) == 0) {
+			sprintf(cmd, "ubi remove rootfs%d", img_index);
+			run_command(cmd, 0);
+		}	
+
+		/* Create rootfs volume */
+		sprintf(cmd, "ubi create rootfs%d %llx  dynamic %d", img_index, size+extra_space_bytes,
+								rootfs_volid);
+		ret = run_command(cmd, 0);
+
+		/* Write rootfs data volume */
+		if( ret == 0 ) {
+			sprintf(cmd, "ubi write %lx rootfs%d %lx\n", addr, img_index, size);
+			ret = run_command(cmd, 0);
+		}
+
+		run_command("ubi detach", 0);
+	}
+	return ret;
+}
+
+static int flash_bootfs_nand( ulong addr, ulong size, int img_index )
+{
+	char cmd[128];
+	int ret = CMD_RET_FAILURE;
+	int bootfs_volid = (img_index == 1? IMAGE_VOL_ID_1:IMAGE_VOL_ID_2);
+	int active_img_idx;
+	uint64_t avail_bytes = 0;
+	uint64_t extra_space_bytes = nand_get_part_extra_bytes("bootfs");
+
+	if( !addr || !size || img_index < MIN_IMG_INDEX || img_index > MAX_IMG_INDEX )
+		return CMD_RET_USAGE;
+
+	ret = run_command("ubi part image", 0);
+	if( ret ) {
+		/* Attach failed, check if we are running bootstrap code */
+		active_img_idx = get_active_img_idx();
+		if( active_img_idx == ACTIVE_IMGIDX_BOOTSTRAP ) {
+			/* We are running bootstrap image, wipe Image partition and retry */
+			printf("UBI attach fails for bootstrap image --> erasing IMAGE MTD partition\n");
+			run_command("mtd erase image", 0);
+			ret = run_command("ubi part image", 0);
+		}
+	}
+
+	if(ret == 0) {
+		/* If fit1 exists, delete it */
+		if(run_command("ubi check fit1", 0) == 0) 
+			run_command("ubi remove fit1", 0);
+
+		/* check if new bootfs will fit in flash */
+		sprintf(cmd, "bootfs%d", img_index); 
+		avail_bytes =  nand_get_avail_space(cmd);
+		if( avail_bytes < size+extra_space_bytes ) {
+			printf("Error: Insufficient space in NAND for 0x%lx Bytes . Available size is 0x%llx\n", size+extra_space_bytes, avail_bytes);
+			return -1;
+		}
+
+		/* If bootfs exists, delete it */
+		sprintf(cmd, "ubi check bootfs%d", img_index); 
+		if(run_command(cmd, 0) == 0) {
+			sprintf(cmd, "ubi remove bootfs%d", img_index);
+			run_command(cmd, 0);
+		}
+
+		/* Create bootfs volume */
+		sprintf(cmd, "ubi create bootfs%d %llx  static %d", img_index, size+extra_space_bytes,
+								bootfs_volid);
+		ret = run_command(cmd, 0);
+
+		/* Write img data */
+		if( ret == 0 ) {
+			sprintf(cmd, "ubi write %lx bootfs%d %lx\n", addr, img_index, size);
+			ret = run_command(cmd, 0);
+		}
+
+		run_command("ubi detach", 0);
+	} else {
+		printf("Error! UBI attach failed!\n");
+	}
+
+	return ret;
+}
+
+
+static int flash_loader_nand( ulong addr, ulong size, int img_index )
+{
+	struct mtd_info * mtd;
+	struct erase_info erase_op = {};
+	loff_t off;
+	int ret;
+	size_t retlen;
+	ulong remaining_bytes = size;
+	mtd = get_mtd_device_nm("loader");
+
+	if( !addr || !size )
+		return CMD_RET_USAGE;
+
+	if( !mtd ) {
+		printf("ERROR: Failed to retrieve MTD device for NAND loader!\n");
+		return -1;
+	}
+
+	if( size > mtd->size ) {
+		printf("ERROR: loader size 0x%08llx is greater than mtd partition size 0x%08llx!\n", size, mtd->size);
+		put_mtd_device(mtd);
+		return -1;
+	}
+
+	(void)img_index;
+
+	/* Block by block write of loader */
+	for( off=0; off < mtd->size; off += mtd->erasesize )
+	{
+		if( remaining_bytes ) {
+			/* Erase block */
+			erase_op.mtd = mtd;
+			erase_op.addr = off;
+			erase_op.len = mtd->erasesize;
+			erase_op.scrub = 0;
+			printf("Erasing next block at 0x%08llx\n", off);
+			ret = mtd_erase(mtd, &erase_op);
+
+			/* Abort if its not a bad block error */
+			if ((ret == -EIO) && erase_op.fail_addr) {
+				printf("Skipping bad block at 0x%08llx\n", erase_op.fail_addr);
+
+				/* Truncate image size if we cant fit due to bad block skip */
+				if( remaining_bytes > (mtd->size - off - mtd->erasesize) )
+					remaining_bytes -= (remaining_bytes < mtd->erasesize?remaining_bytes:mtd->erasesize);
+
+				continue;
+			} else if ( ret ) {
+				printf("ERROR: Failed to erase NAND block 0x%08llx\n", off);
+				break;
+			}
+
+			/* write block */
+			printf("Writing next block at 0x%08llx\n", off);
+			ret = mtd_write(mtd, off, 
+				(remaining_bytes < mtd->erasesize?remaining_bytes:mtd->erasesize), 
+				&retlen, (const uchar*)(addr));
+
+			if( ret ) {
+				printf("ERROR: Failed to write NAND block 0x%08llx\n", off);
+				break;
+			}
+
+			addr += (remaining_bytes < mtd->erasesize?remaining_bytes:mtd->erasesize);
+			remaining_bytes -= (remaining_bytes < mtd->erasesize?remaining_bytes:mtd->erasesize);
+		}
+		else
+			break;
+	}
+
+	if( ret ) {
+		/* Loader upgrade failed for some reason */
+		printf("ERROR: Failed to flash NAND loader! re=%d\n", ret);
+	} else {
+		/* Loader upgrade worked */
+		printf("NAND loader flashed successfully!\n");
+	}
+
+	put_mtd_device(mtd);
+	return ret;
+}
+
+static int set_nand_metadata( char* metadata, int size )
+{
+	char cmd[128];
+	int ret;
+	int i;
+	int volmap[] = {-1,METADATA_VOL_ID_1,METADATA_VOL_ID_2};
+
+	ret = ubi_part("image", NULL);
+	if (ret != 0) {
+		return (ret);
+	}
+	for (i = 1; i < 3; i++) {
+		sprintf(cmd, "ubi remove metadata%d", i);
+		run_command(cmd, 0);
+		sprintf(cmd,
+			"ubi create metadata%d %d static %d", i,
+			METADATA_SIZE + 1024, volmap[i]);
+		run_command(cmd, 0);
+		sprintf(cmd, "metadata%d", i);
+		ubi_volume_write(cmd, metadata, size);
+	}
+	run_command("ubi detach", 0);
+	return ret;
+}
+
+static int get_nand_metadata( char* metadata, int size )
+{
+	int ret;
+	int committed = 0;
+	int valid[2] = {0,0};
+	int seq[2] = {-1,-1};
+	int i;
+	char name[128];
+
+	ret = ubi_part("image", NULL);
+	if (ret != 0) {
+		return (ret);
+	}
+	for (i = 1; i < 3; i++) {
+		sprintf(name, "metadata%d", i);
+		ret = ubi_volume_read(name, metadata, size);
+		printf("read from %s returned %d\n", name, ret);
+		if (0 == validate_metadata(metadata, valid, &committed, seq)) {
+			break;
+		} else {
+			printf("metadata parse error\n");
+			ret = CMD_RET_FAILURE;
+		}
+	}
+	run_command("ubi detach", 0);
+	return ret;
+}
+
+static int nand_load_fit( int img_index, uint32_t fit_load_addr ) 
+{
+	char cmd[128];
+	int ret = CMD_RET_FAILURE;
+	int fit_auth= -1;
+
+	if(run_command("ubi part image", 0) == 0) {
+		//FIXME: OR skip loading if FIT is already in memory
+		//FIXME: IF FIT is loaded from flash, reverify RSA of header
+		sprintf(cmd, "ubi read %lx bootfs%d", fit_load_addr, img_index);
+		ret = run_command(cmd, 0); 
+		/* may be it is just bootstrap image */
+		if (ret) {
+			sprintf(cmd, "ubi read %lx fit1", fit_load_addr);
+			ret = run_command(cmd, 0); 
+		}
+	}
+	return ret;
+}
+
+
+static unsigned int bcm_handle_mapper(void* fit, char *flash_device, char *flash_opts)
+{
+	const char *val;
+	char cmd[768];
+	char work[768];
+	char *cp;
+	int off, len;
+	char dmdev[32];
+	unsigned int magic;
+
+ 	off = fdt_path_offset(fit, "/brcm_rootfs_encrypt");
+	if (off < 0) {
+		return(1);
+	}
+	strcpy(dmdev,"/dev/dm-0");
+	if (val = fdt_getprop(fit, off, "dev", &len)) {
+		strncpy(dmdev, val, len);
+		dmdev[len] = 0;
+	}
+	val = fdt_getprop(fit, off, "type", &len);
+	if (val == NULL) {
+		return(1);
+	}
+	val = fdt_getprop(fit, off, "mapper", &len);
+	if (val == NULL) {
+		return(1);
+	}
+	strncpy(work, val, len);
+	work[len] = 0;
+
+	while (cp = strstr(work,"%DEVICE%")) {
+		strncpy(cmd, work, cp-work);
+		sprintf(&cmd[cp-work], "%s %s", \
+			flash_device, cp+8);
+		strcpy(work,cmd);
+	}
+	if (cp = strstr(work,"%IMAGE_KEY%")) {
+		int i;
+		val = NULL;
+		len = 0;
+		off = fdt_path_offset(gd->fdt_blob, "/trust/key_image_aes");
+		if (off < 0) {
+			printf("ERROR: Can't find /trust/key_image_aes node in boot DTB!\n");
+		}
+		val = (char*)(fdt_getprop(gd->fdt_blob, off, "value", &len));
+		strncpy(cmd, work, cp-work);
+		for (i = 0 ; i < len ; i++) { 
+		   sprintf(&cmd[cp-work+2*i], "%02x", val[i]);
+                }
+		sprintf(&cmd[cp-work+2*i], "%s", cp+11);
+		strcpy(work,cmd);
+	}
+	sprintf(cmd, "root=%s %s dm-mod.create=\"%s\"", dmdev, flash_opts, work);
+	env_set("rootfs_opts", cmd);
+	return(0);
+}
+ 
+static int nand_load_bootfs( int img_index, uint32_t bootfs_load_addr ) 
+{
+	char cmd[128];
+	char device[32];
+	unsigned int magic = 0;
+	int ret = CMD_RET_FAILURE;
+	int fit_auth= -1;
+
+	/* Set rootfs volume id */
+	int rootfs_volid = (img_index == 1?IMAGE_VOL_ID_1:IMAGE_VOL_ID_2)+1;
+
+	if(run_command("ubi part image", 0) == 0) {
+		/* Set default bootargs */
+		/* Determine rootfs type */
+		sprintf(cmd, "ubi read %lx bootfs%d", bootfs_load_addr, img_index);
+		ret = run_command(cmd, 0); 
+		if (!ret) {
+			fit_auth = bcm_sec_validate_fit((void*)bootfs_load_addr, 0x10000);
+		}
+
+		sprintf(device,"/dev/ubiblock0_%d", rootfs_volid); 
+		sprintf(cmd,"ubi.mtd=1 ubi.block=0,%d rootfstype=squashfs", rootfs_volid); 
+		if (bcm_handle_mapper((void*)(ulong)bootfs_load_addr, device, cmd) == 0)
+		{
+			/* mapper has set up the whole thing */
+			if (!fit_auth) {
+				bcm_board_boot_fdt_fixup((void*)bootfs_load_addr);
+			}
+			return(0);
+		}
+
+		sprintf(cmd, "ubi read %lx rootfs%d %d", &magic, img_index, (int)sizeof(unsigned int));
+		if (run_command(cmd, 0) == 0) {
+			if( magic == UBIFS_MAGIC ) {
+				sprintf(cmd, "env set -f rootfs_opts root=ubi:rootfs%d ubi.mtd=1 rootfstype=ubifs", img_index);
+				run_command(cmd, 0);
+			}
+			else if ( magic == SQUASHFS_MAGIC ) {
+				sprintf(cmd, "env set -f rootfs_opts root=/dev/ubiblock0_%d ubi.mtd=1 ubi.block=0,%d rootfstype=squashfs", rootfs_volid, rootfs_volid);
+				run_command(cmd, 0);
+			} else {
+				printf("ERROR: Invalid rootfs detected in volume rootfs1! Boot aborted!\n");
+				return ret;
+			}
+		} else {
+			printf("ERROR: Cannot determine rootfs type! Boot aborted!\n");
+			return ret;
+		}
+
+		if (!fit_auth &&  magic == SQUASHFS_MAGIC ) {
+			bcm_board_boot_fdt_fixup((void*)bootfs_load_addr);
+		}
+	}
+	return ret;
+}
+#endif /* BCA_SDK_NAND_CMD */
+#if defined(BCA_SDK_SPINOR_CMD)
+static int spinor_load_bootfs(uint32_t bootfs_load_addr) 
+{
+	int ret= -1;
+	struct mtd_info *mtd;
+	size_t retlen;	
+	int fit_auth;
+	
+	mtd_probe_devices();
+	mtd = get_mtd_device_nm(BOOTFS_PART);
+	if (IS_ERR_OR_NULL(mtd)){
+		debug("%s:MTD device %s not found, ret %ld\n",__func__, BOOTFS_PART,
+		   PTR_ERR(mtd));
+		return ret;
+	}
+	
+	ret = mtd_read(mtd,0,mtd->size,&retlen,(u_char*)bootfs_load_addr );
+
+	if (!ret) {
+		fit_auth = bcm_sec_validate_fit((void*)bootfs_load_addr, 0x10000);
+	}
+
+	/* If device mapper not being used, set the rootfs_opts manually */
+	if (bcm_handle_mapper((void*)(ulong)bootfs_load_addr, "/dev/mtdblock3", "rootfstype=squashfs") != 0) {
+		env_set("rootfs_opts","root=/dev/mtdblock3 rootfstype=squashfs");
+	}
+
+	if (!fit_auth) {
+		bcm_board_boot_fdt_fixup((void*)bootfs_load_addr);
+	}
+
+	put_mtd_device(mtd);
+	return ret;
+}
+static int spinor_restoredefault(void)
+{
+	struct mtd_info *mtd;
+	struct erase_info ei;
+	int ret;
+
+	mtd_probe_devices();
+	mtd = get_mtd_device_nm(DATA_PART);
+	if (IS_ERR_OR_NULL(mtd)){
+		printf("ERROR!!:failed to get data partition!!\n");
+		return CMD_RET_FAILURE;
+	}
+	
+	memset(&ei, 0, sizeof(ei));
+	ei.mtd = mtd;
+	ei.addr = 0;
+	ei.len = mtd->size;
+	ret = mtd_erase(mtd, &ei);
+	if (ret){
+		printf("ERROR!!: failed to restore to default!!\n");
+		ret = CMD_RET_FAILURE;
+	}
+	else
+		printf("Restore to default done.\n");
+
+	put_mtd_device(mtd);
+	return ret;
+}
+
+static int flash_loader_spinor( ulong addr, ulong size)
+{
+	int ret= -1;
+	struct mtd_info *mtd;
+	struct erase_info ei;
+	size_t retlen;	
+	char *config;
+	u_char *envbuf = NULL;
+	char *found = NULL;
+	int elen;
+	int i;
+	size_t wr_len;
+	char *c;
+
+	if( !addr || !size )
+		return CMD_RET_USAGE;
+	mtd_probe_devices();
+	mtd = get_mtd_device_nm(LOADER_PART);
+	if (IS_ERR_OR_NULL(mtd)){
+		printf("%s:MTD device %s not found, ret %ld\n",__func__, LOADER_PART,
+		   PTR_ERR(mtd));
+		return ret;
+	}
+
+	config = env_get("env_boot_magic");
+	if (NULL != config){
+		elen = simple_strtoul(config, NULL, 0);
+		found = malloc(strlen(config) + 1);
+		if (found){
+			strcpy(found, config);
+			envbuf = malloc(elen + 12);
+			if(envbuf){
+				strtok(found, "@");
+				while ((c = strtok(NULL, ","))) {
+					i = simple_strtoul(c, NULL, 0);
+					debug("read from %x\n", i);
+					wr_len = elen+12;
+					debug("read len %x\n", wr_len);
+					if( mtd_read(mtd,i,wr_len,&retlen, envbuf)){
+						debug("%s:MTD device %s read fail\n",__func__, LOADER_PART);
+						continue;
+					}
+					/*assume addr + i  will  not cause any issue*/
+					memcpy(addr+i, envbuf, wr_len);
+					/*need this?*/
+					if( size < (i + wr_len)){
+						debug("%s:Change original size from %ld to %d \n",__func__,size, i + wr_len);
+						size = i + wr_len;
+					}
+				}
+				free(envbuf);
+			}
+			free(found);
+		}
+	}
+
+	printf("\nErasing MTD partition %s...\n",LOADER_PART);
+	memset(&ei, 0, sizeof(ei));
+	ei.mtd = mtd;
+	ei.addr = 0;
+	ei.len = mtd->size;
+	ret = mtd_erase(mtd, &ei);
+	if (ret){
+		debug("%s:erase MTD device %s fail, ret %d\n",__func__, LOADER_PART,
+	   		ret);
+		goto done;
+	}
+	
+	printf("Writing MTD partition %s...\n",LOADER_PART);
+	ret = mtd_write(mtd, 0, size, &retlen, addr);
+	if (ret){
+		debug("%s:write MTD device %s fail, ret %d\n",__func__, LOADER_PART,
+	   		ret);
+	}
+	debug("%s:Erase/write MTD device %s done, ret %d\n",__func__, LOADER_PART,
+		ret);
+done:	
+	put_mtd_device(mtd);
+	return ret;
+
+}
+
+static int write_spinor_partition( char *const partitionname, ulong addr, ulong size )
+{
+	int ret= -1;
+	struct mtd_info *mtd;
+	struct erase_info ei;
+	size_t retlen;	
+
+	if( !addr || !size )
+		return CMD_RET_USAGE;
+
+	mtd_probe_devices();
+	mtd = get_mtd_device_nm(partitionname);
+	if (IS_ERR_OR_NULL(mtd)){
+		debug("%s:MTD device %s not found, ret %d\n",__func__, partitionname,
+		   PTR_ERR(mtd));
+		return ret;
+	}
+	printf("\nErasing MTD partition %s...\n",partitionname);
+	memset(&ei, 0, sizeof(ei));
+	ei.mtd = mtd;
+	ei.addr = 0;
+	ei.len = mtd->size;
+	ret = mtd_erase(mtd, &ei);
+	if (ret){
+		debug("%s:erase MTD device %s fail, ret %d\n",__func__, partitionname,
+	   		ret);
+		goto done;
+	}
+	
+	printf("Writing MTD partition %s...\n",partitionname);
+	ret = mtd_write(mtd, 0, size, &retlen, (u_char*)addr);
+	if (ret){
+		debug("%s:write MTD device %s fail, ret %d\n",__func__, partitionname,
+	   		ret);
+	}
+done:	
+	put_mtd_device(mtd);
+	return ret;
+}
+
+static int do_flash_spinor_binary(cmd_tbl_t * cmdtp, int flag, int argc, 
+			char *const argv[])
+{
+	char cmd[128];
+	ulong size; 
+	ulong addr; 
+
+	/* Download binary image */
+	sprintf(cmd, "tftp %lx %s", load_addr, argv[1]);
+	if( run_command(cmd, 0) == 0 ) {
+		addr = env_get_hex("fileaddr", 0);
+		size = env_get_hex("filesize", 0);
+		write_spinor_partition(SPIFLASH_MTDNAME, addr, size);
+	} else 
+		printf("ERROR!!: Failed to tftp spinor binary!!\n");
+
+	return 0;
+}
+
+static int do_flash_spinor_bootfs_rootfs(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	char filename[30];
+	int flash_fit=0;
+	int ret = CMD_RET_FAILURE;
+	char cmd[128];
+	ulong size; 
+	ulong addr; 
+	
+
+	/* Parse arguments */
+	if ( strcmp(argv[0], "flash_spinor_fit") == 0) {
+		flash_fit=1;
+		sprintf(filename, "brcm_full_linux.itb");
+	} else {
+		sprintf(filename, "rootfs.squashfs");
+	}
+
+	sprintf(cmd, "tftp %lx %s\n", load_addr, filename);
+	if( run_command(cmd, 0) == 0 ) {
+		size = env_get_hex("filesize", 0);
+		addr = env_get_hex("fileaddr", 0);
+		if(flash_fit){
+			ret = write_spinor_partition(BOOTFS_PART, addr, size);
+		}
+		else{
+			ret = write_spinor_partition(ROOTFS_PART, addr, size);
+		}
+	}
+	else
+		printf("ERROR!!: Failed to tftp rootfs binary!!\n");
+
+	return ret;
+}
+#endif /*BCA_SDK_SPINOR_CMD*/
+
+/************************************************************
+ *                    Generic Functions                     *
+ ************************************************************/
+static int sync_update_loader_bin_env(ulong loader_addr)
+{
+	env_t *ep;
+	uint32_t calc_crc;
+	char *envbuf = NULL;
+	uint32_t *envintp;
+	int ret = -2;
+	int i;
+	loff_t off;
+	size_t rdlen;
+	uint32_t magichdr[3];
+	int num_env_found = 0;
+	char * config;
+
+	/* Search loader in memory for env headers */
+	for (off = 0; off < (loff_t)env_boot_magic_search_size(); off += 4096) {
+		rdlen = 12;
+		memcpy((char*)magichdr, (char*)loader_addr + off, rdlen);
+		if (magichdr[0] != BOOT_MAGIC_MAGIC) {
+			continue;
+		} else {
+			/* Verify CRC */
+			rdlen = magichdr[1];
+			ep = (env_t *) ((char*)loader_addr + off + 8);
+			calc_crc = the_env_crc32(0, ep->data, rdlen - 4);
+			if( ep->crc == calc_crc ) {
+				num_env_found++;
+			} else {
+				continue;
+			}
+		}
+
+		/* Create synced env blob */
+		if(num_env_found == 1)
+		{
+			/* Export environment to embed in new loader */
+			envbuf = malloc(max(rdlen + 12, CONFIG_ENV_SIZE + 12));
+			if( !envbuf ) {
+				printf("ERROR: Failed to allocate mem for env!\n");
+				ret = -1;
+				break;
+			}	
+			ep = (env_t *) (envbuf + 8);
+			envintp = (uint32_t *) envbuf;
+
+			/* Delete boot magic string before exporting env */
+			config = env_get("env_boot_magic");
+			env_set("env_boot_magic", NULL);
+			ret = env_export(ep);
+			if( ret ) {
+				printf("ERROR: Failed to export env!\n");
+				env_set("env_boot_magic", config);
+				break;
+			}
+
+			for (i = CONFIG_ENV_SIZE; i < rdlen; i++) {
+				envbuf[12 + i] = 0xff;
+			}
+			calc_crc = the_env_crc32(0, ep->data, rdlen - 4);
+			memcpy(&ep->crc, &calc_crc, sizeof(calc_crc));
+			envintp[0] = BOOT_MAGIC_MAGIC;
+			envintp[1] = rdlen;
+		}
+
+		/* Write synched env back to loader binary */
+		printf("Updating env in loader bin at 0x%lx\n", (long)off);
+		memcpy((char*)loader_addr + off, envbuf, rdlen+12);
+	}
+
+	if(envbuf)
+		free(envbuf);
+
+	if(!num_env_found)
+		ret = -1;
+
+	return ret;
+}
+
+char * get_loader_media(void)
+{
+	int node,len;
+	char *media = NULL;
+
+	if(forced_updates && strlen(forced_boot_media)) {
+		media = forced_boot_media;
+		printf("WARNING: forced_updates == 1, forcing boot media to %s!\n", media);
+	} else {
+		node = fdt_path_offset(gd->fdt_blob, "/chosen");
+		if (node < 0) {
+			printf("ERROR: Can't find /chosen node in cboot DTB! Cannot determine boot media!\n");
+			return media;
+		}
+		media = (char*)(fdt_getprop(gd->fdt_blob, node, "boot_device", &len));
+	}
+	return media;
+}
+
+static char * get_image_media(void)
+{
+	char *cp = NULL;
+	char *media = NULL;
+
+	if(forced_updates && strlen(forced_image_media)) {
+		media = forced_image_media;
+		printf("WARNING: forced_updates == 1, forcing image media to %s!\n", media);
+	} else {
+		cp = env_get("IMAGE");
+		if (NULL != cp)
+		{
+			unsigned long iargs[4];
+			char units[4];
+			parse_env_string_plus_nums(cp, &media, 4, iargs, units);
+		}
+		else
+			printf("ERROR: Can't find IMAGE env parameter! Cannot determine image media!\n");
+	}
+
+	return media;
+}
+
+static int flash_rootfs( ulong addr, ulong size , int img_index)
+{
+	int ret = -1;
+	if( strcasecmp(get_image_media(), FLASH_DEV_STR_NAND) == 0 ) {
+#ifdef BCA_SDK_NAND_CMD
+		ret = flash_rootfs_nand(addr, size, img_index);
+#endif
+	}
+
+	if( ret && ( strcasecmp(get_image_media(), FLASH_DEV_STR_EMMC) == 0 ) ) {
+#ifdef BCA_SDK_EMMC_CMD
+		ret = flash_rootfs_emmc(addr, size, img_index);
+#endif
+	}
+
+	if( ret && ( strcasecmp(get_image_media(), FLASH_DEV_STR_SPINOR) == 0 ) ) {
+#ifdef BCA_SDK_SPINOR_CMD
+	ret = write_spinor_partition(ROOTFS_PART, addr, size);
+#endif
+	}
+
+	if( ret )
+		printf("ERROR: Failed to flash bootfs binary!\n");
+
+	return ret;
+
+}
+static int flash_bootfs( ulong addr, ulong size , int img_index)
+{
+	int ret = -1;
+	if( strcasecmp(get_image_media(), FLASH_DEV_STR_NAND) == 0 ) {
+#ifdef BCA_SDK_NAND_CMD
+		ret = flash_bootfs_nand(addr, size, img_index);
+#endif
+	}
+
+	if( ret && ( strcasecmp(get_image_media(), FLASH_DEV_STR_EMMC) == 0 ) ) {
+#ifdef BCA_SDK_EMMC_CMD
+		ret = flash_bootfs_emmc(addr, size, img_index);
+#endif
+	}
+
+	if( ret && ( strcasecmp(get_image_media(), FLASH_DEV_STR_SPINOR) == 0 ) ) {
+#ifdef BCA_SDK_SPINOR_CMD
+		ret = write_spinor_partition(BOOTFS_PART, addr, size);
+#endif
+	}
+	if( ret )
+		printf("ERROR: Failed to flash bootfs binary!\n");
+
+	return ret;
+}
+static int flash_loader( ulong addr, ulong size , int img_index)
+{
+	int ret = -1;
+	char * config;
+
+	/* Synch uboot env to loader binary */
+	if( disable_runtime_env_sync ) {
+		printf("WARNING: Not synching runtime env to loader board_spl_fit_pre_load!\n");
+	} else {
+		if( sync_update_loader_bin_env(addr) ) {
+			printf("ERROR: Could not sync runtime env to loader bin!\n");
+			return ret;
+		}
+	}
+
+	if( strcasecmp(get_loader_media(), FLASH_DEV_STR_NAND) == 0 ) {
+#ifdef BCA_SDK_NAND_CMD
+		ret = flash_loader_nand(addr, size, img_index);
+#endif 
+	}
+
+	if( ret && ( strcasecmp(get_loader_media(), FLASH_DEV_STR_EMMC) == 0 ) ) {
+#ifdef BCA_SDK_EMMC_CMD
+		ret = flash_loader_emmc(addr, size, img_index);
+#endif
+	}
+
+	if( ret && ( strcasecmp(get_loader_media(), FLASH_DEV_STR_SPINOR) == 0 ) ) {
+#ifdef BCA_SDK_SPINOR_CMD
+		ret = flash_loader_spinor(addr, size);
+#endif
+	}
+	if( disable_runtime_env_sync ) {
+		printf("WARNING: Not updating runtime env from flashed loader!\n");
+		disable_runtime_env_sync = 0;
+	} else {
+		/* Since sync was successful, we need to scan loader
+		 * for boot magic and update runtime env */
+		env_relocate();
+		env_set("fileaddr", NULL);
+		env_save();
+	}
+
+	if( ret ) 
+		printf("ERROR: Failed to flash loader binary!\n");
+
+	return ret;
+}
+
+static int set_metadata_val( int * committed, int * valid, int * seq )
+{
+	char* b;
+	uint32_t *d, crc;
+	env_t * ep;
+	int i;
+	int ret = -1;
+
+	b = malloc(METADATA_SIZE + 2048);
+	d = (uint32_t *) b;
+	ep = (env_t *) & d[2];
+	d[0] = METADATA_SIZE;
+	d[1] = METADATA_SIZE;
+	i =     sprintf((char*)ep->data,     "COMMITTED=%d",*committed) + 1;
+	i = i + sprintf((char*)&ep->data[i], "VALID=%d,%d",valid[0],valid[1]) + 1;
+	i = i + sprintf((char*)&ep->data[i], "SEQ=%d,%d",seq[0],seq[1]) + 1;
+	ep->data[i] = '\0';
+	crc = the_env_crc32(0, ep->data, (d[0] - 4) & 0xffff);
+	/* 
+	 * We can't use plain crc32 because someone redefines it??
+	 * crc = crc32(0, ep->data, (d[0] - 4) & 0xffff);
+	 */
+	memcpy(&ep->crc, &crc, sizeof(crc));
+
+	/* Flash metadata */
+	if( strcasecmp(get_image_media(), FLASH_DEV_STR_NAND) == 0 ) {
+#ifdef BCA_SDK_NAND_CMD
+		ret = set_nand_metadata(b, METADATA_SIZE + 16);
+#endif
+	}
+
+	if( ret && ( strcasecmp(get_image_media(), FLASH_DEV_STR_EMMC) == 0 ) ) {
+#ifdef BCA_SDK_EMMC_CMD
+		ret = set_emmc_metadata(b, METADATA_SIZE + 16);
+#endif
+	}
+
+	printf("Setting committed %d valid %d,%d seq %d,%d\n", *committed, valid[0], valid[1], seq[0], seq[1]);
+	free(b);
+	return ret;
+}
+
+static int get_metadata_val( int * committed, int * valid, int * seq )
+{
+	char *b = malloc(MAX_METADATA_SIZE);
+	int ret = -1;
+
+	/* Read metadata from flash */
+	if( strcasecmp(get_image_media(), FLASH_DEV_STR_NAND) == 0 ) {
+#ifdef BCA_SDK_NAND_CMD
+		ret = get_nand_metadata( b, MAX_METADATA_SIZE);
+#endif
+	}
+
+	if( ret && ( strcasecmp(get_image_media(), FLASH_DEV_STR_EMMC) == 0 ) ) {
+#ifdef BCA_SDK_EMMC_CMD
+		ret = get_emmc_metadata(b, MAX_METADATA_SIZE);
+#endif
+	}
+	
+	/* Validate metadata */
+	ret = validate_metadata(b, valid, committed, seq);
+	free(b);
+	printf("Getting committed %d valid %d,%d seq %d,%d\n", *committed, valid[0], valid[1], seq[0], seq[1]);
+	return ret;
+}
+
+int commit_image( int img_index )
+{
+	int committed = 0;
+	int valid[2] = {0,0};
+	int seq[2] = {-1,-1};
+
+	/*Return directly for SPI Nor*/
+	if( strcmp(get_image_media(), FLASH_DEV_STR_SPINOR) == 0)
+		return 0;
+	
+	/* Get committed image */
+	get_metadata_val(&committed, valid, seq);
+
+	/* update committed image */
+	committed = img_index;
+	valid[img_index-1] = img_index;
+	seq[img_index-1] = (seq[(img_index == 1) ? 1 : 0] + 1) % 1000; // set newly written image sequence number one greater than other image
+
+	/* Set committed image */
+	set_metadata_val(&committed, valid, seq);
+
+	return 0;
+}
+
+int get_img_index_for_upgrade(int flag)
+{
+	int committed = 0;
+	int valid[2] = {0,0};
+	int seq[2] = {-1,-1};
+	(void) flag;
+	int img_index = get_active_img_idx();
+
+	/*Return 1 for SPI Nor*/
+	if( strcmp(get_image_media(), FLASH_DEV_STR_SPINOR) == 0 )	
+		return 1;
+	
+	/* If we know the active image, always write to the inactive image */
+	if( img_index ) {
+		return( (img_index==1)?2:1 );
+	}
+
+	/* If we cannot determine active image, then get non committed image */
+	get_metadata_val(&committed, valid, seq);
+	if( !committed ) {
+		/* If no commited images then we will flash to the 1st img index */
+		return 1;
+	} else {
+		/* If we have a committed image, then we will upgrade the uncommitted one */
+		return (committed == 1? 2: 1);
+	}
+}
+
+#ifndef CONFIG_LOAD_FIT_OFFSET
+#define CONFIG_LOAD_FIT_OFFSET	SZ_16M
+#endif
+
+static int load_linux_img( int flag, int argc, char *const argv[])
+{
+	char cmd[128];
+	char * board_id  = NULL;
+	int img_index = 0; 
+	uint32_t bootfs_load_addr = load_addr + CONFIG_LOAD_FIT_OFFSET;
+	int ret = -1;
+
+	if( argc == 1 ) {
+		img_index = get_active_img_idx();
+	} else if( argc > 1 ) {
+		if( strlen(argv[1]) == 1 )
+			img_index = *argv[1] - '0';
+		else {
+			board_id = argv[1];
+			img_index = get_active_img_idx();
+		}
+
+		if( argc > 2 ) {
+			board_id = argv[2];
+		}
+	}
+
+	if( img_index < MIN_IMG_INDEX || img_index > MAX_IMG_INDEX ) {
+		printf("ERROR: Invalid Image Index specified!\n");
+		return CMD_RET_FAILURE;
+	}	
+
+#if defined(CONFIG_BCM_BOOTSTATE)
+	/* bcmbca_set_boot_reason(BCM_BOOT_REASON_WATCHDOG | BCM_BOOT_PHASE_LINUX_START | (bcmbca_get_boot_reason() & 0xffff0000) ); */
+#endif
+	/* Load bootfs to load address */
+	if( strcasecmp(get_image_media(), FLASH_DEV_STR_NAND) == 0 ) {
+#ifdef BCA_SDK_NAND_CMD
+		ret = nand_load_bootfs(img_index, bootfs_load_addr);
+#endif
+	}
+
+	if( ret && ( strcasecmp(get_image_media(), FLASH_DEV_STR_EMMC) == 0 ) ) {
+#ifdef BCA_SDK_EMMC_CMD
+		ret = emmc_load_bootfs(img_index, bootfs_load_addr);
+		ret = emmc_do_gpt_fixup();
+#endif
+	}
+
+	if( ret && ( strcasecmp(get_image_media(), FLASH_DEV_STR_SPINOR) == 0 ) ) {
+#ifdef BCA_SDK_SPINOR_CMD
+		ret = spinor_load_bootfs(bootfs_load_addr);
+#endif
+	}
+	
+	if( ret == 0 ) {
+#if defined(CONFIG_WDT)
+		if (gd->watchdog_dev)
+			wdt_stop(gd->watchdog_dev);
+#endif
+		if(!board_id)
+			board_id = env_get("boardid");
+		
+		/* Load binaries */
+		sprintf(cmd, "/configurations/conf_lx_%s", board_id);
+		if(board_id && (fdt_path_offset((void *)bootfs_load_addr, cmd) >= 0))
+			sprintf(cmd, "bootm start %lx#conf_lx_%s; bootm loados; bootm prep;", bootfs_load_addr, board_id);
+		else
+			sprintf(cmd, "bootm start %lx#conf_linux; bootm loados; bootm prep;", bootfs_load_addr);
+
+      		run_command(cmd, 0);
+	} else {
+		printf("ERROR: Failed to load bootfs%d!\n", img_index);
+	}
+
+	return ret;
+}
+
+static int do_load(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	if( load_linux_img( flag, argc, argv ) == 0 ) {
+		printf("\nAll Image components have been loaded to DDR:\n");
+		printf(" - To edit FDT: 'fdt <fdt cmds> ..'\n");
+		printf(" - To launch Linux: 'bootm go'\n");
+	} else
+		printf("Linux image loading Failed!\n");
+
+	return 0;
+}
+
+static int do_boot(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	if( load_linux_img( flag, argc, argv ) == 0 ) 
+		run_command("bootm go\n", 0);
+	else
+		printf("Linux image booting Failed!\n");
+
+	return 0;
+}
+
+static int do_flash_loader(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	char cmd[128];
+	const char *chip_num;
+	ulong size; 
+	ulong addr; 
+
+	/* Determine chip number */
+	chip_num = strstr(CONFIG_SYS_SOC, "bcm");	
+	chip_num += strlen("bcm");
+
+	if( strcasecmp(get_loader_media(), FLASH_DEV_STR_NAND) == 0 ) {
+		sprintf(cmd, "tftp %lx loader_test_nand_%s.bin\n", load_addr, chip_num);
+	}
+
+	if( ( strcasecmp(get_loader_media(), FLASH_DEV_STR_EMMC) == 0 ) ) {
+		sprintf(cmd, "tftp %lx loader_test_emmc_%s.bin\n", load_addr, chip_num);
+	}
+
+	if( ( strcasecmp(get_loader_media(), FLASH_DEV_STR_SPINOR) == 0 ) ) {
+		sprintf(cmd, "tftp %lx loader_test_spinor_%s.bin\n", load_addr, chip_num);
+	}
+
+	if( run_command(cmd, 0) == 0 ) {
+		size = env_get_hex("filesize", 0);
+		addr = env_get_hex("fileaddr", 0);
+		flash_loader(addr, size, 0);
+	} else
+		printf("ERROR!!: Failed to tftp loader binary!!\n");
+
+	return 0;
+}
+
+static int do_flash_bootfs_rootfs( char * bootfs_filename, char * rootfs_filename, int img_index )
+{
+	char cmd[128];
+	ulong size;
+	ulong addr;
+	int ret = CMD_RET_FAILURE;
+
+	/* Write bootfs */
+	if(bootfs_filename) {
+		sprintf(cmd, "tftp %lx %s", load_addr, bootfs_filename);
+		if( run_command(cmd, 0) == 0 ) {
+			size = env_get_hex("filesize", 0);
+			addr = env_get_hex("fileaddr", 0);
+			ret = flash_bootfs(addr, size, img_index);
+		} else
+			printf("ERROR!!: Failed to tftp FIT image!!\n");
+	}
+	
+	/* Write rootfs */
+	if(rootfs_filename) {
+		sprintf(cmd, "tftp %lx %s\n", load_addr, rootfs_filename);
+		
+		if( run_command(cmd, 0) == 0 ) {
+			size = env_get_hex("filesize", 0);
+			addr = env_get_hex("fileaddr", 0);
+			ret = flash_rootfs(addr, size, img_index);
+		} else
+			printf("ERROR!!: Failed to tftp rootfs binary!!\n");
+	}
+
+	return ret;
+}
+
+static int do_flash_bins(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	char * rootfs_fname = NULL;
+	char * bootfs_fname = NULL;
+	int img_index = 0;
+	int ret = CMD_RET_FAILURE;
+
+	/* Parse arguments */
+	if ( (strcmp(argv[0], "flash_bootfs_raw") == 0) ) {
+		bootfs_fname = argv[1];
+	}
+	if( (strcmp(argv[0], "flash_rootfs_raw") == 0) ) { 
+		rootfs_fname = argv[1];
+	}
+
+	if( argc >= 2 ) {
+		if( (argc == 3) && (strlen(argv[2]) == 1) ) 
+			img_index = *argv[2] - '0';
+		else
+			img_index = get_img_index_for_upgrade(0);
+	} else {
+		return CMD_RET_USAGE;
+	}
+
+	ret = do_flash_bootfs_rootfs(bootfs_fname, rootfs_fname, img_index);
+
+	return ret;
+}
+
+static int verify_compat_string( const char * compat_str )
+{
+	const char *chip_num;
+	char * flash_type;
+	char * token = NULL;
+#ifdef BCA_SDK_NAND_CMD
+	char flash_type_full[20];
+ 	struct mtd_info *mtd = NULL;
+#endif	
+
+	/* Early return if forced updates are enabled */
+	if( forced_updates ) {
+		printf("WARNING: Skipping all compatibility checks due to forced updates being enabled!\n");
+		return 0;
+	}
+
+	/* Determine chip number */
+	chip_num = strstr(CONFIG_SYS_SOC, "bcm");	
+	chip_num += strlen("bcm");
+
+	/* Determine flash type matches*/
+	flash_type = get_image_media();
+
+	if( strcmp(flash_type, FLASH_DEV_STR_NAND) == 0 ) {
+#ifdef BCA_SDK_NAND_CMD
+		mtd = get_nand_dev_by_index(0);
+		if (!mtd) {
+			printf("ERROR: Cannot determine NAND erase block size!\n");
+			return CMD_RET_FAILURE;
+		}
+		sprintf(flash_type_full, "%s%d", flash_type, mtd->erasesize >> 10 );
+#endif
+	}
+
+	/* Check compat string */
+	token = strtok((char *)compat_str,";");
+	while( token ) {
+		if( strstr(token, "chip=")) {
+			token += strlen("chip=");
+			if( strcasecmp(token, chip_num) ) {
+				printf("ERROR: Img bundle is for %s, current chip is %s\n", token, chip_num);
+				return -1;
+			}
+		} else if( strstr(token, "flash=")) {
+			token += strlen("flash=");
+			if( strcasecmp(token, flash_type) ) {
+				if( strcmp(flash_type, FLASH_DEV_STR_NAND) == 0 ) {
+#ifdef BCA_SDK_NAND_CMD
+					if( strcasecmp(token, flash_type_full) ) 
+					{	
+						printf("ERROR: Img bundle is for %s, current flash is %s\n", token, flash_type_full);
+						return -1;
+					}
+#endif					
+				} else {
+					printf("ERROR: Img bundle is for %s, current flash is %s\n", token, flash_type);
+					return -1;
+				}
+			}
+		}
+		token = strtok(NULL,";");
+	}
+	return 0;
+}
+
+static int get_binary_from_bundle( ulong bundle_addr, char * conf_name, char * name, 
+	char ** bin_name, ulong * addr, ulong * size )
+{
+	char path[128];
+	int conf_nodeoffset = 0;
+	int nodeoffset = 0;
+	int len;
+	int ret = -1;
+
+	if ( !conf_name || !name || !bin_name ) {
+		printf("ERROR: Invalid conf_name %p, bin_name %p, name %p\n",
+			conf_name, bin_name, name);
+		return ret;
+	}
+
+	/* retrieve configuration node */
+	sprintf(path, "/configurations");
+	sprintf(path, "%s/%s", path, conf_name);
+	conf_nodeoffset = fdt_path_offset((void *)bundle_addr, path);
+	if( conf_nodeoffset < 0 ) {
+		printf("ERROR: %s node not found in bundle!\n", conf_name);
+		return ret;
+	}
+
+	/* Get actual name of fit node for bundle component */
+	*bin_name = fdt_getprop( (void *)bundle_addr, conf_nodeoffset, name, &len);
+	if( !*bin_name ) {
+		printf("INFO: %s not found in configuration %s ...skipping!\n", name, conf_name);
+		return ret;
+	}
+	
+	/* Retrieve node offset for bundle component */
+	sprintf(path, "/images/%s", *bin_name);
+	nodeoffset = fdt_path_offset((void *)bundle_addr, path);
+	if( nodeoffset < 0 ) {
+		printf("ERROR: %s node not found in bundle!\n", path);
+		return ret;
+	}
+	
+	/* Get location and size of binary's data */
+	fit_image_get_data_and_size((void *)bundle_addr, nodeoffset, (const void**)addr, size);
+	if( !*size ) {
+		printf("ERROR: %s data not found in bundle!\n", *bin_name);
+		return ret;
+	}
+	return 0;
+}
+
+static int update_flash_parts_from_loader_bin( ulong loader_addr, ulong loader_size ) {
+	env_t *ep;
+	uint32_t calc_crc;
+	char *envbuf = NULL;
+	uint32_t *envintp;
+	int ret = -2;
+	int i;
+	loff_t off;
+	size_t rdlen;
+	uint32_t magichdr[3];
+	char cmd[128];
+
+	/* Search loader in memory for env headers */
+	for (off = 0; off < (loff_t)env_boot_magic_search_size(); off += 4096) {
+		/* Search loader bin for environment */
+		rdlen = 12;
+		memcpy((char*)magichdr, (char*)loader_addr + off, rdlen);
+		if (magichdr[0] != BOOT_MAGIC_MAGIC) {
+			continue;
+		} else {
+			/* Verify CRC */
+			rdlen = magichdr[1];
+			ep = (env_t *) ((char*)loader_addr + off + 8);
+			calc_crc = the_env_crc32(0, ep->data, rdlen - 4);
+			if( ep->crc == calc_crc ) {
+				break;
+			} else {
+				continue;
+			}
+		}
+	}
+
+	/* Set runtime env variables based on loader's env */
+	if( off < (loff_t)env_boot_magic_search_size() ) {
+
+		/* read IMAGE variable */
+		sprintf(cmd, "env import %lx - IMAGE", (char*)ep);
+		run_command(cmd, 0);
+
+		/* Verify */
+		if( env_get("IMAGE") == NULL ) {
+			printf("ERROR! Failed to import IMAGE parameter from loader!\n");
+			return ret;
+		}
+
+		/* read default_partitions */
+		if( ( strcasecmp(get_image_media(), FLASH_DEV_STR_EMMC) == 0 ) ) {
+			sprintf(cmd, "env import %lx - default_partitions", (char*)ep);
+			run_command(cmd, 0);
+
+			/* Verify */
+			if( env_get("default_partitions") == NULL ) {
+				printf("ERROR! Failed to import default_partitions parameter from loader!\n");
+				return ret;
+			}
+		}
+
+		/* Call partition init code */
+		printf("INFO: flash partition config updated. Repartitioning flash!\n");
+		ret = board_init_flash_parts(1);
+	} else {
+		printf("ERROR!: No environment found in loader binary!\n");
+	}
+	return ret;
+}
+
+int flash_upgrade_img_bundle( ulong bundle_addr , int img_index, const char * conf_name)
+{
+	char path[128];
+	ulong addr=0;
+	ulong size=0;
+	ulong loader_addr=0;
+	ulong loader_size=0;
+	int i=0;
+	int err = 0;
+	const char * bin_name;
+	const char * loader_bin_name;
+	const char * compat_str;
+	char *compat_copy;
+	int nodeoffset = 0;
+	int conf_nodeoffset = 0;
+	int max_entries = sizeof(fn_table)/sizeof(flashfn_table_entry);
+	int len;
+
+	/* verify hashes of all upgrade bundle contents */
+	if( fit_all_image_verify((void *)bundle_addr) ) {
+
+		/* Get offset of config node */
+		sprintf(path, "/configurations");
+		nodeoffset = fdt_path_offset((void *)bundle_addr, path);
+		if( nodeoffset < 0 ) {
+			printf("ERROR: %s node not found in bundle!\n", path);
+			return CMD_RET_FAILURE;
+		}
+
+		/* If configuration is specifed then use it */
+		if( !conf_name ) {
+			/* Get name of the default configuration */
+			conf_name = fdt_getprop((void *)bundle_addr, nodeoffset, "default", &len);
+			if( !conf_name ) {
+				printf("ERROR: Default configuration not found in bundle!\n");
+				return CMD_RET_FAILURE;
+			}
+		}
+
+		/* Get offset of selected configurations fit node */
+		sprintf(path, "%s/%s", path, conf_name);
+		conf_nodeoffset = fdt_path_offset((void *)bundle_addr, path);
+		if( conf_nodeoffset < 0 ) {
+			printf("ERROR: %s node not found in bundle!\n", conf_name);
+			return CMD_RET_FAILURE;
+		}
+
+		/* Verify compatibility */
+		compat_str = fdt_getprop( (void *)bundle_addr, conf_nodeoffset, "compatible", &len);
+		if( !compat_str ) {
+			printf("Error: 'compatible' node not found in bundle!\n");
+			return CMD_RET_FAILURE;
+		}
+		
+		compat_copy = malloc(strlen(compat_str)+1);
+		if(!compat_copy)
+		{
+			printf("Error allocating memory for compatibility string!\n");
+			return CMD_RET_FAILURE;
+		}
+		strcpy(compat_copy, compat_str);
+		
+		if( verify_compat_string(compat_copy) ) {
+			printf("Error: Bundle is not compatible with platform!\n");
+			free(compat_copy);
+			return CMD_RET_FAILURE;
+		}
+		free(compat_copy);
+		
+		/* Decide whether we want to reformat partitions based on loader
+		 * binaries partition configuration configuration */
+		if( NULL == env_get("IMAGE") ) {
+			printf("WARNING: IMAGE env variable missing! Using IMAGE from loader binary!\n");
+			if( get_binary_from_bundle(bundle_addr, conf_name, "loader", 
+			   &loader_bin_name, &loader_addr, &loader_size) == 0 ) {
+				printf("INFO: Reformatting flash media based on new loader binary\n");
+				if( update_flash_parts_from_loader_bin( loader_addr, loader_size ) ) {
+					printf("ERROR: Failed to reformat flash based loader binary!\n");
+					return CMD_RET_FAILURE;
+				}
+
+				/* Set flag to prevent sync of run-time env to loader bin */
+				disable_runtime_env_sync = 1;
+			} else {
+				printf("ERROR! No loader binary AND IMAGE parameter not set!\n");
+				return CMD_RET_FAILURE;
+			}
+		} else if (env_get_hex("reformatOnUpgrade", 0)) {
+			printf("INFO: Reformatting partitions because reformatOnUpgrade == 1!\n");
+			err = board_init_flash_parts(1);
+			env_set("reformatOnUpgrade", NULL);
+		}
+
+		for( i=0; i<max_entries && !err; i++ ) {
+			/* Parse loader only if it has not been parsed before */
+			if( (strcmp(fn_table[i].name,"loader") == 0 ) && loader_addr && loader_size ) {
+				bin_name = loader_bin_name;
+				size = loader_size;
+				addr = loader_addr;
+			} else {
+				if (get_binary_from_bundle( bundle_addr, conf_name, fn_table[i].name, 
+				   &bin_name, &addr, &size ) ) {
+					continue;
+				}
+			}
+		
+			/* Calling flashing function */
+			printf("Flashing %s (%s: 0x%lx bytes from 0x%lx) to %s%d.....\n", 
+			   fn_table[i].name, bin_name, size, addr, fn_table[i].name, 
+			   (strcmp(fn_table[i].name,"loader")?img_index:0));
+			err = fn_table[i].func(addr, size, img_index);
+		}
+
+		/* Reset flag */
+		disable_runtime_env_sync = 0;
+	} else {
+		err = CMD_RET_FAILURE;
+	}
+
+	return err;
+}
+
+static int do_flash_upgrade_img (cmd_tbl_t * cmdtp, int flag, int argc, 
+			char *const argv[])
+{
+	char cmd[128];
+	ulong bundle_addr=0;
+	int err = CMD_RET_FAILURE;
+	const char * conf_name = NULL;
+	int img_index = 0;
+	bool download = true;
+	bool commit = true;
+	int active_img_idx = get_active_img_idx();
+
+	/* Parse and remove the optional skip argument */
+	if ( argc > 1) {
+		if ( !strcmp(argv[1], "-s")) {
+			download = false;
+			argc--;
+			argv++;
+		} else if ( !strcmp(argv[1], "-i")) {
+			commit = false;
+			argc--;
+			argv++;
+		}
+	}
+
+	if( argc == 2 ) {
+		img_index = get_img_index_for_upgrade(0);
+	} else if( argc > 2 ) {
+		if( strlen(argv[2]) == 1 )
+			img_index = *argv[2] - '0';
+		else {
+			conf_name = argv[2];
+			img_index = get_img_index_for_upgrade(0);
+		}
+
+		if( argc > 3 ) {
+			conf_name = argv[3];
+		}
+	}
+
+	if( img_index < MIN_IMG_INDEX || img_index > MAX_IMG_INDEX ) {
+		printf("ERROR: Invalid Image Index specified!\n");
+		return CMD_RET_USAGE;
+	}	
+
+	if (download)
+		sprintf(cmd, "tftp %lx %s", load_addr, argv[1]);
+
+	if( !download || run_command(cmd, 0) == 0 ) {
+		bundle_addr = env_get_hex("fileaddr", 0);
+
+		if (bundle_addr)
+			/* Call main img flashing function */
+			err = flash_upgrade_img_bundle(bundle_addr, img_index, conf_name);
+	}
+
+	if(err) {
+		printf("ERROR: Image upgrade failed!!\n");
+	} else {
+		printf("INFO: Image upgrade successfull!!\n");		
+		if( commit ) {
+			printf("INFO: Committing Image!!\n");		
+			commit_image( img_index );
+
+			/* Handle bootstrap condition */
+			if( active_img_idx == ACTIVE_IMGIDX_BOOTSTRAP ) {
+				/* Now that we have a valid image flashed, change active image index */
+				set_active_img_idx(img_index);
+			}
+		} else {
+			printf("INFO: Not Committing Image!!\n");		
+		}
+	}
+
+	return err;
+}
+
+static int do_restoredefault(cmd_tbl_t * cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	int ret = -1;
+	if( strcmp(get_image_media(), FLASH_DEV_STR_NAND) == 0 ) {
+#ifdef BCA_SDK_NAND_CMD
+		ret = nand_restoredefault();
+#endif
+	}
+
+	if( ret && ( strcmp(get_image_media(), FLASH_DEV_STR_EMMC) == 0 ) ) {
+#ifdef BCA_SDK_EMMC_CMD
+		ret = emmc_restoredefault();
+#endif
+	}
+	
+	if( ret && ( strcmp(get_image_media(), FLASH_DEV_STR_SPINOR) == 0 ) ) {
+#ifdef BCA_SDK_SPINOR_CMD
+		ret = spinor_restoredefault();
+#endif
+	}
+
+	return ret;
+}
+
+static int do_metadata(cmd_tbl_t * cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	int ret = -1;
+	int committed = 0;
+	int valid[2] = {0,0};
+	int seq[2] = {-1,-1};
+	int status = get_metadata_val(&committed, valid, seq);
+
+	if (argc == 1) {
+		if (0 == status) {
+			printf("committed-img: %d valid-imgs: ", committed);
+			if( valid[0] )
+				printf("%d", valid[0]);
+			if( valid[1] )
+				printf("%d", valid[1]);
+			printf(", seq# img 1: %d, img2: %d\n\n", seq[0], seq[1]);
+			ret = 0;
+		} else {
+			printf("metadata parse error\n");
+		}
+	} else if (argc == 3) {
+		committed = atoi(argv[1]);
+		valid[0] = atoi(strtok(argv[2],","));
+		valid[1] = atoi(strtok(NULL,","));
+		
+		if (0 != set_metadata_val(&committed, valid, seq)) {
+			printf("metadata parse error\n");
+		} else {
+			ret = 0;
+		}
+	}
+	return ret;
+}
+
+#if defined(CONFIG_BCM_BOOTSTATE)
+static int do_activate(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	bcmbca_set_boot_reason(BCM_BOOT_REASON_ACTIVATE);
+	run_command("reset", 0); 
+	return 0;
+}
+#endif
+
+static int do_force(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	int ret = 0;
+	if( argc > 1 ) {
+		if( atoi(argv[1]) == 1 ) {
+			if( (argc == 4) 
+				&& ( ( strcasecmp(argv[2], FLASH_DEV_STR_NAND) == 0 )
+				|| (   strcasecmp(argv[2], FLASH_DEV_STR_SPINOR) == 0 )
+				|| (   strcasecmp(argv[2], FLASH_DEV_STR_EMMC) == 0 ) ) 
+				&& ( ( strcasecmp(argv[3], FLASH_DEV_STR_NAND) == 0 )
+				|| (   strcasecmp(argv[3], FLASH_DEV_STR_SPINOR) == 0 )
+				|| (   strcasecmp(argv[3], FLASH_DEV_STR_EMMC) == 0 ) )	) {
+				forced_updates = 1;
+				strcpy(forced_boot_media,argv[2]);
+				strcpy(forced_image_media,argv[3]);
+			} else if(argc == 2) {
+				forced_updates = 1;
+			} else {
+				ret = CMD_RET_USAGE;
+				printf("Cannot determine boot/image flash type, please specify flash types!\n");
+			}
+		} else {
+			forced_updates = 0;
+			forced_boot_media[0] = '\0';
+			forced_image_media[0] = '\0';
+		}
+	}
+
+	printf("Forced Image Updates: %s, Forced flash types: Boot=%s, Image=%s\n", 
+		(forced_updates?"Enabled":"Disabled"), 
+		(forced_updates?forced_boot_media:"NOT SPECIFIED"),
+		(forced_updates?forced_image_media:"NOT SPECIFIED"));
+
+	return ret;
+}
+
+#ifdef CONFIG_BCMBCA_HTTPD
+static int do_httpd_start(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+    if(!httpd_check_net_env())
+        register_cli_job_cb(0, http_poll);
+    return 0;
+}
+#endif
+
+#ifdef CONFIG_BCMBCA_PMC
+static int do_bpcm_cmd(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	int err = CMD_RET_USAGE;
+	int read = 0;
+        u32 addr, off, data;
+	
+	if ((argc != 5) && (argc != 4))
+		return err;  
+  
+	if (!strcmp(argv[1], "r"))
+		read = 1;
+	else if (!strcmp(argv[1], "w"))
+		read = 0;
+	else
+		return err;
+
+	addr = atoi(argv[2]);
+	off = atoi(argv[3]);
+	if (!read) {
+		data = atoi(argv[4]);
+		err = WriteBPCMRegister(addr, off>>2, data);
+		printf("bpcm write data 0x%x to addr 0x%x offset 0x%x ret %d\n",
+		       data, addr, off, err);
+	} else {
+		err = ReadBPCMRegister(addr, off>>2, &data);
+		printf("bpcm read data 0x%x from addr 0x%x offset 0x%x ret %d\n",
+		       data, addr, off, err);
+	}
+	
+
+	return err;
+}
+
+static int do_cpufreq(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	int err = CMD_RET_USAGE, freqMHz;
+
+	if (argc != 2)
+		return err;
+
+	err = CMD_RET_SUCCESS;
+	freqMHz = atoi(argv[1]);
+	freqMHz = set_cpu_freq(freqMHz);
+	if (freqMHz > 0)
+		printf("cpu freq set to %dMHz\n", freqMHz);
+	else
+		err = CMD_RET_FAILURE;
+
+	return err;
+}
+#endif
+
+static int do_dev_spec_key(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	int err = CMD_RET_USAGE;
+	int rc, len;
+	u32 dev_spec_key[8];
+	int i;
+	bool force = false;                                 
+							    
+	if ( (argc == 2) && (strcmp(argv[1], "get") == 0)) {
+		rc = bcm_sec_get_dev_spec_key((char*)dev_spec_key, sizeof(u32)*8);
+	} else if ( (argc >= 10) && (strcmp(argv[1], "set") == 0)) {
+		/* Parse and remove the optional FORCE argument */  
+		if( argc > 10 ) {
+			if ( !strcasecmp(argv[2], "-f")) {              
+				force = true;                       
+				argc--;                             
+				argv++;                             
+			}
+		}
+
+		for(i=0; i<8; i++) {
+			dev_spec_key[i] = simple_strtoul(argv[i+2],NULL, 0);
+		}
+		if ( !force ) {
+			printf("WARNING: You are attempting to set a new device specific key.\n");
+			len = cli_readline("This operation cannot be undone, enter 'Y' to continue: ");	
+			if( !len || console_buffer[0] != 'Y' ) {
+				printf("Device specific key setting aborted.\n");
+				return CMD_RET_SUCCESS;
+			}
+		}
+		rc = bcm_sec_set_dev_spec_key((char*)dev_spec_key, sizeof(u32)*8);
+	} else {
+		return err;
+	}
+
+	if (rc == 0) {
+		printf("Current Device Specific Key:\n");
+		for( i=0; i<8; i++ ) {
+			printf(" [%d]0x%08x\n", i, dev_spec_key[i]);
+		}
+		printf("\n\n");
+		err = CMD_RET_SUCCESS;
+	} else {
+		err = CMD_RET_FAILURE;
+	}
+
+	return err;
+}
+
+static int do_sec_ser_num(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	int err = CMD_RET_USAGE;
+	int rc, len;
+	u32 sec_ser_num[8] = {0};
+	char * sec_ser_num_ptr = (char*)&sec_ser_num[0];
+	char * sec_ser_num_char_array;
+	char byte_buf[3] = {0};
+	int i,j;
+	bool force = false;                                 
+	bool is_set = false;
+	bool is_odd = false;
+							    
+	if ( (argc == 2) && (strcmp(argv[1], "get") == 0)) {
+		rc = bcm_sec_get_sec_ser_num((char*)sec_ser_num, sizeof(u32)*8);
+	} else if ( (argc >= 3) && (strcmp(argv[1], "set") == 0)) {
+		is_set = true;
+		/* Parse and remove the optional FORCE argument */  
+		if( argc == 4 ) {
+			if ( !strcasecmp(argv[2], "-f")) {              
+				force = true;                       
+				argc--;                             
+				argv++;                             
+			}
+		}
+
+		/* Check if byte array exceeds 32 bytes OR contains an ODD number of characters */
+		sec_ser_num_char_array = argv[2];
+
+		/* Skip leading 0x if present */
+		if( sec_ser_num_char_array[1] == 'x' || sec_ser_num_char_array[1] == 'X' )
+			sec_ser_num_char_array += 2;
+
+		debug("sernum:%s len:%d\n", sec_ser_num_char_array, (int)strlen(sec_ser_num_char_array));
+		if( ((strlen(sec_ser_num_char_array)/2) > sizeof(sec_ser_num)) || (strlen(sec_ser_num_char_array) % 2)){
+			return CMD_RET_USAGE;
+		}
+
+		/* Check if there is an odd number of digits so that we can insert an extra zero */
+		if( strlen(sec_ser_num_char_array) % 2 )
+			is_odd = 1;
+
+		for(i=0,j=sizeof(sec_ser_num)-strlen(sec_ser_num_char_array)/2; 
+		   i<strlen(sec_ser_num_char_array),j<sizeof(sec_ser_num); j++){
+			if( is_odd && (i == 0) ) {
+				byte_buf[1] = sec_ser_num_char_array[i];
+				is_odd = false;
+				i++;
+			} else {
+				memcpy(byte_buf,&sec_ser_num_char_array[i], 2);
+				i += 2;
+			}
+
+			sec_ser_num_ptr[j] = simple_strtoul(byte_buf,NULL,16);
+			debug("byte_buf: %s 0x%02x\n", byte_buf, sec_ser_num_ptr[j]);
+		}
+
+		if ( !force ) {
+			printf("WARNING: You are attempting to set a new secure serial number.\n");
+			len = cli_readline("This operation cannot be undone, enter 'Y' to continue: ");	
+			if( !len || console_buffer[0] != 'Y' ) {
+				printf("secure serial number setting aborted.\n");
+				return CMD_RET_SUCCESS;
+			}
+		}
+		rc = bcm_sec_set_sec_ser_num((char*)sec_ser_num, sizeof(u32)*8);
+	} else {
+		return err;
+	}
+
+	if (rc == 0) {
+		if( is_set ) 
+			printf("Set Secure Serial Number as:\n");
+		else
+			printf("Current Secure Serial Number:\n");
+
+		printf(" [");
+		for( i=0; i<sizeof(sec_ser_num); i++ ) {
+			printf("%02x", sec_ser_num_ptr[i]);
+		}
+		printf("]\n");
+
+		printf("In memory represenation:\n");
+		for( i=0; i<8; i++ ) {
+			printf(" [%d]0x%08x\n", i, sec_ser_num[i]);
+		}
+		printf("\n\n");
+		err = CMD_RET_SUCCESS;
+	} else {
+		err = CMD_RET_FAILURE;
+	}
+
+	return err;
+}
+static int do_antirollback(cmd_tbl_t * cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	int err = CMD_RET_USAGE;
+	int rc, len;
+	u32 lvl;
+	bool force = false;                                 
+							    
+
+	if ( (argc == 2) && (strcmp(argv[1], "get") == 0)) {
+		rc = bcm_sec_get_antirollback_lvl(&lvl);
+	} else if ( (argc >= 3) && (strcmp(argv[1], "set") == 0)) {
+		/* Parse and remove the optional FORCE argument */  
+		if( argc > 3 ) {
+			if ( !strcasecmp(argv[2], "-f")) {              
+				force = true;                       
+				argc--;                             
+				argv++;                             
+			}
+		}
+
+		/* get level */
+		lvl = atoi(argv[2]);
+		if ( !force ) {
+			printf("WARNING: You are attempting to set a new anti-rollback level.\n");
+			len = cli_readline("This operation cannot be undone, enter 'Y' to continue: ");	
+			if( !len || console_buffer[0] != 'Y' ) {
+				printf("Anti-rollback level setting aborted.\n");
+				return CMD_RET_SUCCESS;
+			}
+		}
+		rc = bcm_sec_set_antirollback_lvl(lvl);
+	} else {
+		return err;
+	}
+
+	if (rc == 0) {
+		printf("Current anti-rollback level set to: %d\n", lvl);
+		err = CMD_RET_SUCCESS;
+	} else {
+		err = CMD_RET_FAILURE;
+	}
+
+	return err;
+}
+
+#ifdef CONFIG_BCMBCA_XRDP_ETH
+extern int bcmbca_xrdp_eth_phy_status(void);
+extern int bcmbca_xrdp_eth_mac_status(void);
+extern int bcmbca_xrdp_eth_active_port_get(void);
+extern int bcmbca_xrdp_eth_active_port_set(int port);
+extern int bcmbca_xrdp_eth_env_active_port_set(int port);
+
+static int do_eth_active_port(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+    int port;
+
+	if (argc == 2)
+    {
+        port = (atoi(argv[1]));
+        bcmbca_xrdp_eth_active_port_set(port);
+    }
+
+    port = bcmbca_xrdp_eth_active_port_get();
+    printf("XRDP Ethernet active port is set to %d\n" ,port);
+
+	return 0;
+}
+
+static int on_active_port(const char *name, const char *value, enum env_op op, int flags)
+{
+    int active_port = -1;
+
+	if ((flags & H_INTERACTIVE) == 0)
+		return 0;
+
+	switch (op) {
+	case env_op_create:
+	case env_op_overwrite:
+        active_port = simple_strtoul(value, NULL, 10);
+        break;
+    case env_op_delete:
+        break;
+    default:
+        break;
+    }
+
+    return bcmbca_xrdp_eth_env_active_port_set(active_port);
+}
+U_BOOT_ENV_CALLBACK(active_port, on_active_port);
+#endif
+
+static char usage[] = 
+#ifdef BCA_SDK_EMMC_CMD
+    "\n## eMMC Specific Test Commands ##\n"
+    "gpt_fixup\n"
+    " - Create GPT partitions if partition sizes are specfied via special uboot\n"
+    " - environment variables. The env variable name has to be in the format:\n"
+    " - 	<partition_name>_vol_size=<size in MiB>\n"
+#endif /* BCA_SDK_EMMC_CMD */
+#ifdef BCA_SDK_SPINOR_CMD
+    "\n## SPINOR Specific Test Commands ##\n"
+    "flash_spinor_fit\n"
+    " - Download and flash atf+uboot+vmlinux+dtb in brcm_full.itb to SPI NOR flash \n"
+    "flash_spinor_rootfs\n"
+    " - Download and flash rootfs in rootfs.squashfs to SPI NOR flash\n"
+    "flash_spinor_upgrade [-s] <filename> [conf]\n"
+    "flash_spinor_upgrade <filename> [<img> [<conf>]]\n" 
+    " - Download and flash an image upgrade bundle to SPI NOR flash\n"
+    "flash_spinor_binary <filename> \n" 
+    " - Erase whole flash,download and flash a binary image to SPI NOR flash start from 0\n"
+    "boot_spinor [boardid]\n"
+    " - Boot linux from image in SPI NOR flash.\n" 
+#endif
+    "\n## Generic Test Commands ##\n"
+    "force \n"
+    " - Without arguments, display if forced image updates are enabled\n"
+    "force [force value] <[Boot Flash Type] [Image Flash Type]>\n"
+    " - Enable(value=1)/Disable(value=0) forced image updates. All compatibility checks are ignored if enabled\n"
+    " - If boot and image flash types are not detected, then they need to be specified as 2nd and 3rd args\n"
+    " - Valid flash type values = [NAND|SPINAND|EMMC|NOR]\n"
+    "restoredefault\n"
+    " - Delete contents of /data so that it gets populated with default values\n"
+    "flash_loader\n"                        
+    " - Download and flash SPL+TPL in loader_test_<flash>_<chip>.bin to boot flash\n"
+#if defined(BCA_SDK_NAND_CMD) || defined(BCA_SDK_EMMC_CMD)
+    "flash_bootfs_raw <bootfs binary> [img]\n"                      
+    "flash_rootfs_raw <rootfs binary> [img]\n"   
+    " - Download and flash raw bootfs/rootfs binary to flash \n"
+    " - WARNING: These are raw writes with no content, security or compatibility checks. Metadata is NOT updated \n"
+    "metadata \n"
+    "metadata [committed] [valid],[valid]\n"    
+    " - without arguments, parse and display metadata\n"
+    " - set metadata values (example \"metadata 1 1,2\" for both images valid and #1 committed)\n" 
+    " - NOTE: Must do a sw reset for metadata changes to take affect\n"
+#endif
+    "flash_img_upgrade [-s] <filename> [conf]\n"
+    "flash_img_upgrade [-i] <filename> [<img> [<conf>]]\n" 
+    " - Download and flash an image upgrade bundle via TFTP\n"
+    " - NOTE: Must do a sw reset to use the new image\n"
+    "load_img [boardid]\n"                  
+    "load_img [<img> [<boardid>]]\n"                  
+    " - Load image from flash into DDR.\n" 
+    "boot_img [boardid]\n"                  
+    "boot_img [<img> [<boardid>]]\n"                  
+    " - Boot linux from image in flash.\n" 
+    "[Legend - Optional Parameters]\n"
+    " -s:      Skip downloading the image via tftp. Assume it is already at ${fileaddr}\n"
+    " -i:      Inactive. Do not change activation state of new image i.e do not commit image\n"
+    " img:     Image index for flashing/booting. Valid values: [1|2]. Default index is determined from metadata\n"
+    " fstype:  Filesystem type for flashing. Valid values: [squashfs|ubifs|ext4]. Default is squashfs\n"
+    " boardid: Boardid to determine boot configuration. If omitted default configuration node is used\n"
+    " conf:    Configuration name used for flashing img bundle. If omitted default configuration node is used\n\n"
+#ifdef CONFIG_BCMBCA_HTTPD
+    "httpd_start \n"
+    " - without arguments, start httpd server\n"
+#endif
+#ifdef CONFIG_BCMBCA_PMC
+    "bpcm_cmd <r|w> <addr> <offset> [<data>]\n"                  
+    " - read/write bpcm register\n"
+    "cpufreq <freq in MHz>\n"                  
+    " - set cpu frequency\n" 
+#endif	  
+    "antirollback get\n"                  
+    " - get current anti-rollback level\n" 
+    "antirollback set [-f] <new anti-rollback level to set>\n"                  
+    " - set new anti-rollback level. [-f] will force the commit and skip warnings\n" 
+    "sec_ser_num get \n"                  
+    " - get current secure serial number level ( 64 digits )\n" 
+    "sec_ser_num set [-f] < Hex secure serial number ( Max 64 digits )>\n"
+    " - set new secure serial number . [-f] will force the commit and skip warnings\n" 
+    "dev_spec_key get \n"                  
+    " - get current device specific key ( 32 bytes )\n" 
+    "dev_spec_key set [-f] <32-bit hex word 0>...<32-bit hex word 7> \n"                  
+    " - set new device specific key. [-f] will force the commit and skip warnings\n" 
+    ;
+
+static char sdk_usage[] = 
+    "\nforce\n"
+    " - Without arguments, display if forced image updates are enabled\n"
+    "force [force value] <[Boot Flash Type] [Image Flash Type]>\n"
+    " - Enable(value=1)/Disable(value=0) forced image updates. All compatibility checks are ignored if enabled\n"
+    " - If boot and image flash types are not detected, then they need to be specified as 2nd and 3rd args\n"
+    " - Valid flash type values = [NAND|SPINAND|EMMC|NOR]\n"
+    "restoredefault\n"
+    " - Delete contents of /data so that it gets populated with default values\n"
+#if defined(BCA_SDK_NAND_CMD) || defined(BCA_SDK_EMMC_CMD)
+    "metadata \n"
+    "metadata [committed] [valid],[valid]\n"    
+    " - without arguments, parse and display metadata\n"
+    " - set metadata values (example \"metadata 1 1,2\" for both images valid and #1 committed)\n" 
+    " - NOTE: Must do a sw reset for metadata changes to take affect\n"
+#endif
+    "flash_img_upgrade [-s] <filename> [conf]\n"
+    "flash_img_upgrade [-i] <filename> [<img> [<conf>]]\n" 
+    " - Download and flash an image upgrade bundle via TFTP\n"
+    " - NOTE: Must do a sw reset to use the new image\n"
+    "load_img [boardid]\n"                  
+    "load_img [<img> [<boardid>]]\n"                  
+    " - Load image from flash into DDR.\n" 
+    "boot_img [boardid]\n"                  
+    "boot_img [<img> [<boardid>]]\n"                  
+    " - Boot linux from image in flash.\n" 
+    "[Legend - Optional Parameters]\n"
+    " -s:      Skip downloading the image via tftp. Assume it is already at ${fileaddr}\n"
+    " -i:      Inactive. Mark new image as inactive i.e do not commit image\n"
+    " img:     Image index for flashing/booting. Valid values: [1|2]. Default index is determined from metadata\n"
+    " boardid: Boardid to determine boot configuration. If omitted default configuration node is used\n"
+    " conf:    Configuration name used for flashing img bundle. If omitted default configuration node is used\n\n"
+#ifdef CONFIG_BCMBCA_HTTPD
+    "httpd_start \n"
+    " - without arguments, start httpd server\n"
+#endif
+#ifdef CONFIG_BCMBCA_XRDP_ETH
+    "active_port [port]\n"
+    " - Set the active network driver's port to send packets from\n"
+    " - without arguments, display the current active port\n"
+    "eth_status [type]\n"
+    " - Print the XRDP Ethernet network driver status tables\n"
+    " - Argument can be phy or mac. If no argument provided, both tables will be printed\n"
+#endif
+    ;
+
+U_BOOT_CMD_WITH_SUBCMDS(bca_test, "Broadcom test commands", usage,
+			U_BOOT_SUBCMD_MKENT(flash_loader, 1, 0, do_flash_loader),
+#ifdef BCA_SDK_EMMC_CMD
+			U_BOOT_SUBCMD_MKENT(gpt_fixup, 1, 0, do_gpt_fixup),
+#endif /* BCA_SDK_EMMC_CMD */
+#ifdef BCA_SDK_SPINOR_CMD
+			U_BOOT_SUBCMD_MKENT(flash_spinor_fit, 1, 0, do_flash_spinor_bootfs_rootfs),
+			U_BOOT_SUBCMD_MKENT(flash_spinor_rootfs, 1, 0, do_flash_spinor_bootfs_rootfs),
+			U_BOOT_SUBCMD_MKENT(flash_spinor_upgrade, 5, 0, do_flash_upgrade_img),
+			U_BOOT_SUBCMD_MKENT(flash_spinor_binary, 2, 0, do_flash_spinor_binary),
+			U_BOOT_SUBCMD_MKENT(boot_spinor, 3, 0, do_boot),
+#endif			
+#if defined(CONFIG_BCM_BOOTSTATE)
+			U_BOOT_SUBCMD_MKENT(activate, 1, 0, do_activate),
+#endif /* CONFIG_BCM_BOOTSTATE */
+			U_BOOT_SUBCMD_MKENT(force, 4, 0, do_force),
+			U_BOOT_SUBCMD_MKENT(restoredefault, 1, 0, do_restoredefault),
+#if defined(BCA_SDK_NAND_CMD) || defined(BCA_SDK_EMMC_CMD) 
+			U_BOOT_SUBCMD_MKENT(flash_bootfs_raw, 3, 0, do_flash_bins),
+			U_BOOT_SUBCMD_MKENT(flash_rootfs_raw, 3, 0, do_flash_bins),
+			U_BOOT_SUBCMD_MKENT(metadata, 5, 0, do_metadata),
+#endif			
+			U_BOOT_SUBCMD_MKENT(flash_img_upgrade, 5, 0, do_flash_upgrade_img),
+			U_BOOT_SUBCMD_MKENT(boot_img, 3, 0, do_boot)
+#ifdef CONFIG_BCMBCA_HTTPD
+			,U_BOOT_SUBCMD_MKENT(httpd_start, 1, 0, do_httpd_start)
+#endif
+#ifdef CONFIG_BCMBCA_PMC
+			,U_BOOT_SUBCMD_MKENT(bpcm_cmd, 5, 0, do_bpcm_cmd)
+			,U_BOOT_SUBCMD_MKENT(cpufreq, 2, 0, do_cpufreq)			
+#endif			
+			,U_BOOT_SUBCMD_MKENT(antirollback, 4, 0, do_antirollback)			
+			,U_BOOT_SUBCMD_MKENT(sec_ser_num, 12, 0, do_sec_ser_num)			
+			,U_BOOT_SUBCMD_MKENT(dev_spec_key, 12, 0, do_dev_spec_key)			
+    );
+
+U_BOOT_CMD_WITH_SUBCMDS(sdk, "Broadcom SDK support commands", sdk_usage,
+			U_BOOT_SUBCMD_MKENT(force, 4, 0, do_force),
+			U_BOOT_SUBCMD_MKENT(restoredefault, 1, 0, do_restoredefault),
+#if defined(BCA_SDK_NAND_CMD) || defined(BCA_SDK_EMMC_CMD) 
+			U_BOOT_SUBCMD_MKENT(metadata, 5, 0, do_metadata),
+#endif			
+			U_BOOT_SUBCMD_MKENT(flash_img_upgrade, 5, 0, do_flash_upgrade_img),
+			U_BOOT_SUBCMD_MKENT(boot_img, 3, 0, do_boot),
+			U_BOOT_SUBCMD_MKENT(load_img, 3, 0, do_load)
+#ifdef CONFIG_BCMBCA_HTTPD
+			,U_BOOT_SUBCMD_MKENT(httpd_start, 1, 0, do_httpd_start)
+#endif
+#ifdef CONFIG_BCMBCA_XRDP_ETH
+			,U_BOOT_SUBCMD_MKENT(active_port, 2, 0, do_eth_active_port)
+#endif
+    );
+
diff --git a/board/broadcom/bcmbca/spl_env.c b/board/broadcom/bcmbca/spl_env.c
new file mode 100644
index 0000000000..0e73d86fc9
--- /dev/null
+++ b/board/broadcom/bcmbca/spl_env.c
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <linux/ctype.h>
+#include <environment.h>
+#include <hexdump.h>
+#include <stdlib.h>
+#include <string.h>
+#include "bca_common.h"
+#include "spl_env.h"
+
+/**
+ * find_spl_env_val - get pointer to named environment value 
+ * @buffer: pointer to the magic number of the, already loaded and validated, environment buffer
+ * @name: name of the environment variable to find
+ *
+ * returns:
+ *     pointer to the first character after the NAME= string in the environment if found
+ *     NULL if not found
+ */
+char *find_spl_env_val(const char *buffer, const char *name)
+{
+	uint32_t len;
+	env_t *ep;
+	int nmlen;
+	uint32_t *d = (uint32_t *) buffer;
+	if (buffer == NULL) {
+		return NULL;
+	}
+	len = d[1];
+
+	nmlen = strlen(name);
+#if BCM_DEBUG_SPLENV
+	printf("look for env %s\n", name);
+#endif /* BCM_DEBUG_SPLENV */
+	ep = (env_t *) (buffer + 8);
+	char *c;
+	char previous = '\0';
+	c = (char *)&ep->data[0];
+	while ((c < (char *)&ep->data[len - 4])
+	       && ((c[0] != '\0') || (c[1] != '\0'))) {
+		if ((previous == '\0')
+		    && (0 == strncmp(name, (char *)c, nmlen))
+		    && (c[nmlen] == '=')) {
+			c = c + nmlen + 1;
+#if BCM_DEBUG_SPLENV
+			{
+				int i;
+				i = strlen(c);
+				if (i > 80) {
+					printf("found %d byte value\n",i);
+				} else {
+					printf("found %s\n", c);
+				}
+			}
+#endif /* BCM_DEBUG_SPLENV */
+			return c;
+		}
+		previous = c[0];
+		c++;
+	}
+	return NULL;
+}
+
+/**
+ * get_spl_env_val - get named environment value 
+ * @buffer: pointer to the magic number of the, already loaded and validated, environment buffer
+ * @name: name of the environment variable to find
+ * @out: pointer to buffer to which data will be copied
+ * @maxlen: max bytes to copy to the output buffer
+ *
+ * returns:
+ *     0 if successful
+ *     1 if not found
+ */
+int get_spl_env_val(const char *buffer, const char *name, char *out, int maxlen)
+{
+	char *c;
+	c = find_spl_env_val(buffer, name);
+	if (NULL != c) {
+		strncpy(out, c, maxlen);
+		return (0);
+	}
+	return 1;
+}
+
+int validate_metadata(char *cp, int *valid, int *committed, int *seq)
+{
+	uint32_t *d, crc, got;
+	env_t *ep;
+	char buf[16];
+	d = (uint32_t *) cp;
+	ep = (env_t *) & d[2];
+	memcpy(&crc, &ep->crc, sizeof(crc));
+	got = crc32(0, ep->data, (d[1] - 4) & 0xffff);
+	if (got == crc) {
+		unsigned long iargs[3];
+		int n, i;
+		n = parse_env_nums(find_spl_env_val
+				   (cp, "VALID"), 3, iargs, NULL);
+		for (i = 0; i < n; i++) {
+			if ((iargs[i] >= 1) && (iargs[i] <= 2)) {
+				valid[iargs[i] - 1] = iargs[i];
+			}
+		}
+		if (0 == get_spl_env_val(cp, "COMMITTED", buf, 10)) {
+			*committed = (buf[0] == '1') ? 1 : 2;
+		}
+
+		// preset the sequence numbers incase the field doesn't exist
+		if ((*committed == 1) && valid[0])
+		{
+			seq[0] = 1;
+			if (valid[1])
+				seq[1] = 0;
+		}
+		else if ((*committed == 2) && valid[1])
+		{
+			seq[1] = 1;
+			if (valid[0])
+				seq[0] = 0;
+		}
+
+		n = parse_env_nums(find_spl_env_val
+				   (cp, "SEQ"), 3, iargs, NULL);
+		for (i = 0; i < n; i++) {
+			seq[i] = iargs[i];
+		}
+
+		return (0);
+	}
+#if 0
+	printf("at %p for %d bytes expected %x got %x\n",&ep->data, d[0]-4, crc,got);
+        print_hex_dump_bytes("vdate: ", DUMP_PREFIX_ADDRESS, cp, 256+32);
+	got = crc32(0, ep->data, (d[0] - 4) & 0xffff);
+	printf("just for grins %x\n",got);
+#endif
+	/* Error out all fields to indicate no committed and valid images */
+	valid[0] = 0;
+	valid[1] = 0;
+	*committed = 0;
+	seq[0] = -1;
+	seq[1] = -1;
+	return (1);
+}
+
+/* UBOOT has multiple conflicting CRC32 implementations, so share the one that works */
+uint32_t the_env_crc32(int a, void *b, int len) {
+	return(crc32(a,b,len));
+}
+
diff --git a/board/broadcom/bcmbca/uboot_lockdown.c b/board/broadcom/bcmbca/uboot_lockdown.c
new file mode 100644
index 0000000000..760a31c79c
--- /dev/null
+++ b/board/broadcom/bcmbca/uboot_lockdown.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Broadcom Corporation
+ * Joel Peshkin, Broadcom Corporation, joel.peshkin@broadcom.com
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <hexdump.h>
+#include <linux/ctype.h>
+#include <linux/stddef.h>
+#include <errno.h>
+#include <bca_sdk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char *null_env = "\0\0\0\0";
+
+#define BCM_LOCKDOWN_MAX_ENV_NAME 64
+#define BCM_LOCKDOWN_MAX_ENV_VALUE 520
+/* also limit with CONFIG_ENV_SIZE */
+
+static void lock_env_add_safe(char *name, char *val, char * safe, int max);
+
+static void lock_env_add_safe(char *name, char *val, char *safe, int max)
+{
+	int l;
+	int i;
+	char v[2];
+	v[1] = '\0';
+	l = strlen(val);
+	if (l > max) {
+		return;
+	}
+	for (i = 0 ; i < l ; i++) {
+		v[0] = val[i];
+		if (!(isalnum(val[i]) || (NULL != strstr(safe,v)))) {
+			/* printf("rejected '%s'='%s'\n",name,val); */
+			return;
+		}
+	}
+	env_set(name, val);
+}
+
+int env_override_import(void *ep)
+{
+	char *cp = ((char *)ep) + 4; /* skip length field */
+	char *delim;
+	env_import ((void *) null_env, 0);
+	env_set("overridden", "true");
+	while (*cp != '\0') {
+		delim = strstr(cp,"=");
+		if (delim && (delim <= cp + BCM_LOCKDOWN_MAX_ENV_NAME) && (delim <= ep + CONFIG_ENV_SIZE)) {
+			*delim = '\0';
+			delim++;
+			if (strlen(delim) > BCM_LOCKDOWN_MAX_ENV_VALUE) {
+				break;
+			}
+			/* if we made it this far, *cp and *delim point to name and value */
+
+			if ((strcmp(cp,"IMAGE") == 0) || (strcmp(cp,"MCB") == 0) || (strcmp(cp,"ethaddr") == 0)) {
+				lock_env_add_safe(cp,delim,":,",32);
+			} else if (strncmp(cp,"demo_",5) == 0) {
+				env_set(cp,delim);
+			} else if (strcmp(cp,"env_boot_magic") == 0) {
+				lock_env_add_safe(cp,delim,"@,",32);
+			} else if (strncmp(cp,"rdp",3) == 0) {
+				lock_env_add_safe(cp,delim,"",6);
+			} else if (strcmp(cp,"nummacaddrs") == 0) {
+				lock_env_add_safe(cp,delim,"_",32);
+			} else if (strcmp(cp,"boardid") == 0) {
+				lock_env_add_safe(cp,delim,"_",32);
+			} else {
+				/* printf("skipped '%s'='%s'\n",cp,delim); */
+			}
+
+
+			/* done with conditional import */
+			cp = delim + strlen(delim) + 1;
+		} else {
+			break;
+		}
+	}
+	env_set("bootdelay", "1");
+	env_set("bootcmd", "printenv;sdk boot_img");
+	/* gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; */
+	gd->flags |= GD_FLG_DISABLE_CONSOLE; 
+	return 1;
+}
+
diff --git a/cmd/gpt.c b/cmd/gpt.c
index 33cda51396..01137c8761 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -342,17 +342,43 @@ static int get_gpt_info(struct blk_desc *dev_desc)
 }
 
 /* a wrapper to test get_gpt_info */
-static int do_get_gpt_info(struct blk_desc *dev_desc)
+static int do_get_gpt_info(struct blk_desc *dev_desc, char * const namestr)
 {
-	int ret;
+	int numparts;
+	numparts = get_gpt_info(dev_desc);
+
+	if (numparts > 0) {
+		if (namestr) {
+			char disk_guid[UUID_STR_LEN + 1];
+			char *partitions_list; 
+			int partlistlen;
+			int ret = -1;
+			ret = get_disk_guid(dev_desc, disk_guid);
+			if (ret < 0)
+				return ret;
+
+			partlistlen = calc_parts_list_len(numparts);
+			partitions_list = malloc(partlistlen);
+			if (!partitions_list) {
+				del_gpt_info();
+				return -ENOMEM;
+			}
+			memset(partitions_list, '\0', partlistlen);
 
-	ret = get_gpt_info(dev_desc);
-	if (ret > 0) {
-		print_gpt_info();
+			ret = create_gpt_partitions_list(numparts, disk_guid, partitions_list);
+			if (ret < 0) {
+				printf("Error: Could not create partition list string!\n");
+			} else {
+				env_set(namestr, partitions_list);
+			}
+			free(partitions_list);
+		} else {
+			print_gpt_info();
+		}
 		del_gpt_info();
 		return 0;
 	}
-	return ret;
+	return numparts;
 }
 #endif
 
@@ -849,7 +875,7 @@ static int do_gpt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		ret = do_disk_guid(blk_dev_desc, argv[4]);
 #ifdef CONFIG_CMD_GPT_RENAME
 	} else if (strcmp(argv[1], "read") == 0) {
-		ret = do_get_gpt_info(blk_dev_desc);
+		ret = do_get_gpt_info(blk_dev_desc, argv[4]);
 	} else if ((strcmp(argv[1], "swap") == 0) ||
 		   (strcmp(argv[1], "rename") == 0)) {
 		ret = do_rename_gpt_parts(blk_dev_desc, argv[1], argv[4], argv[5]);
@@ -885,8 +911,9 @@ U_BOOT_CMD(gpt, CONFIG_SYS_MAXARGS, 1, do_gpt,
 	" gpt guid mmc 0 varname\n"
 #ifdef CONFIG_CMD_GPT_RENAME
 	"gpt partition renaming commands:\n"
-	" gpt read <interface> <dev>\n"
+	" gpt read <interface> <dev> <varname>\n"
 	"    - read GPT into a data structure for manipulation\n"
+	"    - read GPT partitions into environment variable\n"
 	" gpt swap <interface> <dev> <name1> <name2>\n"
 	"    - change all partitions named name1 to name2\n"
 	"      and vice-versa\n"
@@ -895,5 +922,7 @@ U_BOOT_CMD(gpt, CONFIG_SYS_MAXARGS, 1, do_gpt,
 	" Example usage:\n"
 	" gpt swap mmc 0 foo bar\n"
 	" gpt rename mmc 0 3 foo\n"
+	" gpt read mmc 0 3 \n"
+	" gpt read mmc 0 3 varname\n"
 #endif
 );
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 49d3b5bdf4..1b5e2f2cf9 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -50,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
 	defined(CONFIG_ENV_IS_IN_SATA)		|| \
 	defined(CONFIG_ENV_IS_IN_SPI_FLASH)	|| \
 	defined(CONFIG_ENV_IS_IN_REMOTE)	|| \
+	defined(CONFIG_ENV_IS_IN_BOOT_MAGIC)	|| \
 	defined(CONFIG_ENV_IS_IN_UBI)
 
 #define ENV_IS_IN_DEVICE
@@ -59,7 +60,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #if	!defined(ENV_IS_IN_DEVICE)		&& \
 	!defined(CONFIG_ENV_IS_NOWHERE)
 # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|\
-NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
+NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|BOOT_MAGIC|UBI} or CONFIG_ENV_IS_NOWHERE
 #endif
 
 /*
diff --git a/cmd/ubi.c b/cmd/ubi.c
index c511a2fb76..c0d011dd45 100644
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -171,6 +171,11 @@ static int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id)
 	}
 	printf("Creating %s volume %s of size %lld\n",
 		dynamic ? "dynamic" : "static", volume, size);
+
+#ifdef CONFIG_SYS_NMRP
+    if (!strncmp("rootfs", volume, 6))
+        SendNmrpAlive();
+#endif
 	/* Call real ubi create volume */
 	return ubi_create_volume(ubi, &req);
 }
diff --git a/common/Makefile b/common/Makefile
index c7e41ef307..63015ecc64 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -70,7 +70,7 @@ endif
 obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o
 obj-$(CONFIG_TPL_HASH_SUPPORT) += hash.o
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
-obj-$(CONFIG_SPL_LOAD_FIT) += common_fit.o
+obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += common_fit.o
 obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
 
@@ -81,6 +81,7 @@ obj-$(CONFIG_SPL_USB_STORAGE) += usb_storage.o
 else
 obj-$(CONFIG_USB_MUSB_HOST) += usb.o
 endif
+obj-$(CONFIG_SPL_STANDALONE) += exports.o
 endif # CONFIG_SPL_BUILD
 
 #others
diff --git a/common/autoboot.c b/common/autoboot.c
index 94133eaeda..7a449e575e 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -17,7 +17,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define MAX_DELAY_STOP_STR 32
+#define MAX_DELAY_STOP_STR 64
 
 #ifndef DEBUG_BOOTKEYS
 #define DEBUG_BOOTKEYS 0
@@ -37,7 +37,7 @@ static int stored_bootdelay;
  *
  * https://crackstation.net/hashing-security.htm
  */
-static int slow_equals(u8 *a, u8 *b, int len)
+static int slow_equals(u8 * a, u8 * b, int len)
 {
 	int diff = 0;
 	int i;
@@ -54,6 +54,7 @@ static int passwd_abort(uint64_t etime)
 	u8 sha_env[SHA256_SUM_LEN];
 	u8 sha[SHA256_SUM_LEN];
 	char presskey[MAX_DELAY_STOP_STR];
+	char *c;
 	const char *algo_name = "sha256";
 	u_int presskey_len = 0;
 	int abort = 0;
@@ -63,6 +64,13 @@ static int passwd_abort(uint64_t etime)
 	if (sha_env_str == NULL)
 		sha_env_str = CONFIG_AUTOBOOT_STOP_STR_SHA256;
 
+	c = strstr(sha_env_str, ":");
+	if (c && (c - sha_env_str < MAX_DELAY_STOP_STR)) {
+		/* preload presskey with salt */
+		memcpy(presskey, sha_env_str, c - sha_env_str);
+		presskey_len = c - sha_env_str;
+		sha_env_str = c + 1;
+	}
 	/*
 	 * Generate the binary value from the environment hash value
 	 * so that we can compare this value with the computed hash
@@ -73,6 +81,9 @@ static int passwd_abort(uint64_t etime)
 		printf("Hash %s not supported!\n", algo_name);
 		return 0;
 	}
+	while (tstc()) {
+		getc();
+	}
 
 	/*
 	 * We don't know how long the stop-string is, so we need to
@@ -94,6 +105,8 @@ static int passwd_abort(uint64_t etime)
 			/* And check if sha matches saved value in env */
 			if (slow_equals(sha, sha_env, SHA256_SUM_LEN))
 				abort = 1;
+			/* add 1 second per character typed */
+			etime += (uint64_t) (1) * get_tbclk();
 		}
 	} while (!abort && get_ticks() <= etime);
 
@@ -107,34 +120,33 @@ static int passwd_abort(uint64_t etime)
 		char *str;
 		u_int len;
 		int retry;
-	}
-	delaykey[] = {
-		{ .str = env_get("bootdelaykey"),  .retry = 1 },
-		{ .str = env_get("bootstopkey"),   .retry = 0 },
-	};
+	} delaykey[] = {
+		{
+		.str = env_get("bootdelaykey"),.retry = 1}, {
+	.str = env_get("bootstopkey"),.retry = 0},};
 
 	char presskey[MAX_DELAY_STOP_STR];
 	u_int presskey_len = 0;
 	u_int presskey_max = 0;
 	u_int i;
 
-#  ifdef CONFIG_AUTOBOOT_DELAY_STR
+#ifdef CONFIG_AUTOBOOT_DELAY_STR
 	if (delaykey[0].str == NULL)
 		delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR;
-#  endif
-#  ifdef CONFIG_AUTOBOOT_STOP_STR
+#endif
+#ifdef CONFIG_AUTOBOOT_STOP_STR
 	if (delaykey[1].str == NULL)
 		delaykey[1].str = CONFIG_AUTOBOOT_STOP_STR;
-#  endif
+#endif
 
 	for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i++) {
 		delaykey[i].len = delaykey[i].str == NULL ?
-				    0 : strlen(delaykey[i].str);
+		    0 : strlen(delaykey[i].str);
 		delaykey[i].len = delaykey[i].len > MAX_DELAY_STOP_STR ?
-				    MAX_DELAY_STOP_STR : delaykey[i].len;
+		    MAX_DELAY_STOP_STR : delaykey[i].len;
 
 		presskey_max = presskey_max > delaykey[i].len ?
-				    presskey_max : delaykey[i].len;
+		    presskey_max : delaykey[i].len;
 
 		debug_bootkeys("%s key:<%s>\n",
 			       delaykey[i].retry ? "delay" : "stop",
@@ -159,12 +171,12 @@ static int passwd_abort(uint64_t etime)
 		for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i++) {
 			if (delaykey[i].len > 0 &&
 			    presskey_len >= delaykey[i].len &&
-				memcmp(presskey + presskey_len -
-					delaykey[i].len, delaykey[i].str,
-					delaykey[i].len) == 0) {
-					debug_bootkeys("got %skey\n",
-						delaykey[i].retry ? "delay" :
-						"stop");
+			    memcmp(presskey + presskey_len -
+				   delaykey[i].len, delaykey[i].str,
+				   delaykey[i].len) == 0) {
+				debug_bootkeys("got %skey\n",
+					       delaykey[i].retry ? "delay" :
+					       "stop");
 
 				/* don't retry auto boot */
 				if (!delaykey[i].retry)
@@ -187,13 +199,13 @@ static int __abortboot(int bootdelay)
 	int abort;
 	uint64_t etime = endtick(bootdelay);
 
-#  ifdef CONFIG_AUTOBOOT_PROMPT
+#ifdef CONFIG_AUTOBOOT_PROMPT
 	/*
 	 * CONFIG_AUTOBOOT_PROMPT includes the %d for all boards.
 	 * To print the bootdelay value upon bootup.
 	 */
 	printf(CONFIG_AUTOBOOT_PROMPT, bootdelay);
-#  endif
+#endif
 
 	abort = passwd_abort(etime);
 	if (!abort)
@@ -202,7 +214,7 @@ static int __abortboot(int bootdelay)
 	return abort;
 }
 
-# else	/* !defined(CONFIG_AUTOBOOT_KEYED) */
+#else /* !defined(CONFIG_AUTOBOOT_KEYED) */
 
 #ifdef CONFIG_MENUKEY
 static int menukey;
@@ -222,10 +234,10 @@ static int __abortboot(int bootdelay)
 	/*
 	 * Check if key already pressed
 	 */
-	if (tstc()) {	/* we got a key press	*/
-		(void) getc();  /* consume input	*/
+	if (tstc()) {		/* we got a key press   */
+		(void)getc();	/* consume input        */
 		puts("\b\b\b 0");
-		abort = 1;	/* don't auto boot	*/
+		abort = 1;	/* don't auto boot      */
 	}
 
 	while ((bootdelay > 0) && (!abort)) {
@@ -233,14 +245,14 @@ static int __abortboot(int bootdelay)
 		/* delay 1000 ms */
 		ts = get_timer(0);
 		do {
-			if (tstc()) {	/* we got a key press	*/
-				abort  = 1;	/* don't auto boot	*/
-				bootdelay = 0;	/* no more delay	*/
-# ifdef CONFIG_MENUKEY
+			if (tstc()) {	/* we got a key press   */
+				abort = 1;	/* don't auto boot      */
+				bootdelay = 0;	/* no more delay        */
+#ifdef CONFIG_MENUKEY
 				menukey = getc();
-# else
-				(void) getc();  /* consume input	*/
-# endif
+#else
+				(void)getc();	/* consume input        */
+#endif
 				break;
 			}
 			udelay(10000);
@@ -253,7 +265,7 @@ static int __abortboot(int bootdelay)
 
 	return abort;
 }
-# endif	/* CONFIG_AUTOBOOT_KEYED */
+#endif /* CONFIG_AUTOBOOT_KEYED */
 
 static int abortboot(int bootdelay)
 {
@@ -298,8 +310,7 @@ const char *bootdelay_process(void)
 	bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
 
 #ifdef CONFIG_OF_CONTROL
-	bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay",
-			bootdelay);
+	bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay", bootdelay);
 #endif
 
 	debug("### main_loop entered: bootdelay=%d\n\n", bootdelay);
@@ -339,8 +350,16 @@ void autoboot_command(const char *s)
 #if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC)
 		disable_ctrlc(prev);	/* restore Control C checking */
 #endif
+#if defined(CONFIG_AUTOBOOT_KEYED)
+		printf("bootcommand failed .. last chance\n");
+		if (!abortboot(20)) {
+			printf("RESET THE BOARD\n");
+			while (1) {
+			};
+		}
+		printf("drop to cli ok\n");
+#endif /* CONFIG_AUTOBOOT_KEYED */
 	}
-
 #ifdef CONFIG_MENUKEY
 	if (menukey == CONFIG_MENUKEY) {
 		s = env_get("menucmd");
diff --git a/common/board_f.c b/common/board_f.c
index c25eb188fb..194d5605ca 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -472,12 +472,38 @@ static int reserve_uboot(void)
 	return 0;
 }
 
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+static int reserve_noncached(void)
+{
+	/*
+	 * The value of gd->start_addr_sp must match the value of malloc_start
+	 * calculated in boatrd_f.c:initr_malloc(), which is passed to
+	 * board_r.c:mem_malloc_init() and then used by
+	 * cache.c:noncached_init()
+	 *
+	 * These calculations must match the code in cache.c:noncached_init()
+	 */
+	gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
+		MMU_SECTION_SIZE;
+	gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
+				   MMU_SECTION_SIZE);
+	debug("Reserving %dM for noncached_alloc() at: %08lx\n",
+	      CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
+
+	return 0;
+}
+#endif
+
 /* reserve memory for malloc() area */
 static int reserve_malloc(void)
 {
 	gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
 	debug("Reserving %dk for malloc() at: %08lx\n",
 	      TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+	reserve_noncached();
+#endif
+
 	return 0;
 }
 
diff --git a/common/board_r.c b/common/board_r.c
index df24021f2c..c54605ab63 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -243,6 +243,10 @@ static int initr_malloc(void)
 	      gd->malloc_ptr / 1024);
 #endif
 	/* The malloc area is immediately below the monitor copy in DRAM */
+	/*
+	 * This value MUST match the value of gd->start_addr_sp in board_f.c:
+	 * reserve_noncached().
+	 */
 	malloc_start = gd->relocaddr - TOTAL_MALLOC_LEN;
 	mem_malloc_init((ulong)map_sysmem(malloc_start, TOTAL_MALLOC_LEN),
 			TOTAL_MALLOC_LEN);
diff --git a/common/cli_readline.c b/common/cli_readline.c
index 99b631720e..c678b73ed1 100644
--- a/common/cli_readline.c
+++ b/common/cli_readline.c
@@ -20,6 +20,8 @@ static const char   tab_seq[] = "        ";	/* used to expand TABs */
 
 char console_buffer[CONFIG_SYS_CBSIZE + 1];	/* console I/O buffer	*/
 
+void (*cli_jobs_cb)(void) = NULL;
+
 static char *delete_char (char *buffer, char *p, int *colp, int *np, int plen)
 {
 	char *s;
@@ -269,6 +271,15 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len,
 				WATCHDOG_RESET();
 			}
 			first = 0;
+		}       
+
+		if(cli_jobs_cb)
+		{
+			while(!tstc())
+			{	
+				cli_jobs_cb();
+				WATCHDOG_RESET();
+			}
 		}
 
 		ichar = getcmd_getch();
diff --git a/common/exports.c b/common/exports.c
index b4f1f7af15..719123fa1d 100644
--- a/common/exports.c
+++ b/common/exports.c
@@ -1,4 +1,5 @@
 #include <common.h>
+#include <malloc.h>
 #include <exports.h>
 #include <spi.h>
 #include <i2c.h>
diff --git a/common/image-fit.c b/common/image-fit.c
index a74b44f298..3381995e1d 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -142,7 +142,7 @@ int fit_get_subimage_count(const void *fit, int images_noffset)
 	return count;
 }
 
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FIT_PRINT)
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FIT_PRINT) || defined(CONFIG_TPL_FIT_PRINT)
 /**
  * fit_image_print_data() - prints out the hash node details
  * @fit: pointer to the FIT format image header
@@ -550,7 +550,7 @@ void fit_image_print(const void *fit, int image_noffset, const char *p)
 #else
 void fit_print_contents(const void *fit) { }
 void fit_image_print(const void *fit, int image_noffset, const char *p) { }
-#endif /* !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FIT_PRINT) */
+#endif /* !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FIT_PRINT) || defined(CONFIG_TPL_FIT_PRINT) */
 
 /**
  * fit_get_desc - get node description property
diff --git a/common/main.c b/common/main.c
index 07b34bf2b0..46dac40cf5 100644
--- a/common/main.c
+++ b/common/main.c
@@ -11,6 +11,9 @@
 #include <cli.h>
 #include <console.h>
 #include <version.h>
+#if defined(CONFIG_BCMBCA_BUTTON)
+#include "bcmbca_button.h"
+#endif
 
 /*
  * Board-specific Platform code can reimplement show_boot_progress () if needed
@@ -37,6 +40,53 @@ static void run_preboot_environment_command(void)
 #endif /* CONFIG_PREBOOT */
 }
 
+int g_restore_default;
+
+void check_restore_default(void)
+{
+#define Button_Reg 0xff800528	
+#define Reset_GPIO_Mask 0x00200000	
+	unsigned int *addr_button = (unsigned int*)Button_Reg;
+	int i;
+	
+	g_restore_default=1;
+	for( i=0; i<50; i++ )
+	{
+		  if( ((*addr_button) & Reset_GPIO_Mask) != 0 )  // Reset button not pressed
+		  {
+			    g_restore_default=0;
+			    break;
+		  }
+			
+      udelay(100000); //delay 100ms
+	}
+	
+	if( g_restore_default==1 )
+	{	
+		  printf("===== Restore default =====\n");
+		  run_command("sdk restoredefault", 0);
+
+    	for( i=0; i<20; i++ )
+    	{
+		      if ((i % 2) == 0) {
+			        board_test_led(0);
+		       } else {
+			        board_test_led(1);
+		       }
+			     udelay(250000);
+       }
+       board_test_led(0);
+	  }
+	  return;
+}
+
+void bootup_turn_on_power_led(void)
+{
+	//power up, turn on power led
+	printf("===== POWER ON TURN ON POWER LED =====\n");
+	board_test_led(0);
+}
+
 /* We come here after U-Boot is initialised and ready to process commands */
 void main_loop(void)
 {
@@ -48,12 +98,23 @@ void main_loop(void)
 		env_set("ver", version_string);  /* set version variable */
 
 	cli_init();
-
+	/*Foxconn add start*/
+	bootup_turn_on_power_led();
+	/*Foxconn add end*/
 	run_preboot_environment_command();
 
+  check_restore_default();
+  
+#ifdef CONFIG_SYS_NMRP
+    StartNmrpClient();
+#endif
+
 	if (IS_ENABLED(CONFIG_UPDATE_TFTP))
 		update_tftp(0UL, NULL, NULL);
 
+#if defined(CONFIG_BCMBCA_BUTTON)
+        btn_poll_block();
+#endif	
 	s = bootdelay_process();
 	if (cli_process_fdt(&s))
 		cli_secure_boot_cmd(s);
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 142753f9e7..d3d4d27c40 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -956,6 +956,13 @@ config SPL_ATF
 	  is loaded by SPL (which is considered as BL2 in ATF terminology).
 	  More detail at: https://github.com/ARM-software/arm-trusted-firmware
 
+config TPL_ATF
+	bool "Support ARM Trusted Firmware"
+	help
+	  ATF(ARM Trusted Firmware) is a component for ARM AArch64/32 which
+	  is loaded by TPL (which is considered as BL2 in ATF terminology).
+	  More detail at: https://github.com/ARM-software/arm-trusted-firmware
+
 config SPL_ATF_NO_PLATFORM_PARAM
         bool "Pass no platform parameter"
 	depends on SPL_ATF
@@ -1120,6 +1127,11 @@ config TPL_MPC8XXX_INIT_DDR_SUPPORT
 	  Enable support for DDR-SDRAM on the MPC8XXX family within TPL. See
 	  SPL_MPC8XXX_INIT_DDR_SUPPORT for details.
 
+config TPL_MTD_SUPPORT
+	bool "Support MTD drivers"
+	help
+	  Enable support for MTD (Memory Technology Device) within TPL.
+ 
 config TPL_MMC_SUPPORT
 	bool "Support MMC"
 	depends on MMC
@@ -1206,6 +1218,59 @@ config TPL_YMODEM_SUPPORT
 	  means of transmitting U-Boot over a serial line for using in TPL,
 	  with a checksum to ensure correctness.
 
+config TPL_FIT
+	bool "Support Flattened Image Tree within SPL"
+	depends on SPL
+	select TPL_OF_LIBFDT
+
+config TPL_FIT_PRINT
+	bool "Support FIT printing within TPL"
+	depends on TPL_FIT
+	help
+	  Support printing the content of the fitImage in a verbose manner in TPL.
+
+config TPL_LOAD_FIT
+	bool "Enable TPL loading U-Boot as a FIT (basic fitImage features)"
+	select TPL_FIT
+	help
+	  Normally with the TPL framework a legacy image is generated as part
+	  of the build. This contains U-Boot along with information as to
+	  where it should be loaded. This option instead enables generation
+	  of a FIT (Flat Image Tree) which provides more flexibility. In
+	  particular it can handle selecting from multiple device tree
+	  and passing the correct one to U-Boot.
+
+config TPL_RSA
+	bool "Use RSA Library within TPL"
+
+config TPL_FIT_SIGNATURE
+	bool "Enable signature verification of FIT firmware within TPL"
+	depends on SPL_DM
+	select TPL_FIT
+	select TPL_RSA
+
+config TPL_SHA256_SUPPORT
+	bool "Support SHA256"
+	depends on TPL_FIT
+	select SHA256
+	help
+	  Enable this to support SHA256 in FIT images within TPL. A SHA256
+	  checksum is a 256-bit (32-byte) hash value used to check that the
+	  image contents have not been corrupted. SHA256 is recommended for
+	  use in secure applications since (as at 2016) there is no known
+	  feasible attack that could produce a 'collision' with differing
+	  input data. Use this for the highest security. Note that only the
+	  SHA256 variant is supported: SHA512 and others are not currently
+	  supported in U-Boot.
+
+config TPL_CRYPTO_SUPPORT
+	bool "Support crypto drivers"
+	help
+	  Enable crypto drivers in TPL. These drivers can be used to
+	  accelerate secure boot processing in secure applications. Enable
+	  this option to build the drivers in drivers/crypto as part of an
+	  SPL build.
+
 endif # TPL
 
 config SPL_AT91_MCK_BYPASS
@@ -1220,5 +1285,14 @@ config SPL_AT91_MCK_BYPASS
 	  If this option is disabled, the SoC expects a crystal oscillator
 	  that needs driving on both XIN and XOUT lines.
 
+config SPL_STANDALONE
+	bool "Support standalone application in SPL"
+	default n
+	help
+	  This option enables standalone application build for SPL.
+	  Unlike u_boot proper loading application from the shell manually, SPL
+	  need to load the app binary from somewhere during the SPL execution,
+	  typically in the SPL board init routine.
+
 endif # SPL
 endmenu
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 4ddeff9b51..41c38fc630 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -599,6 +599,10 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	timer_init();
 #endif
 
+#ifdef CONFIG_SPL_STANDALONE
+	jumptable_init();
+#endif
+
 #if CONFIG_IS_ENABLED(BOARD_INIT)
 	spl_board_init();
 #endif
diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c
index 4715f9d371..3b13363874 100644
--- a/common/spl/spl_atf.c
+++ b/common/spl/spl_atf.c
@@ -79,10 +79,17 @@ static struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl33_entry)
 	return bl2_to_bl31_params;
 }
 
+#if __LINUX_ARM_ARCH__==8
 static inline void raw_write_daif(unsigned int daif)
 {
 	__asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory");
 }
+#else
+static inline void raw_write_daif(unsigned int daif)
+{
+
+}
+#endif
 
 typedef void (*atf_entry_t)(struct bl31_params *params, void *plat_params);
 
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 163e540622..f51d703a0d 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -80,7 +80,7 @@ int spl_load_image_fat(struct spl_image_info *spl_image,
 			return err;
 		if (err == 0)
 			err = 1;
-	} else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	} else if (CONFIG_IS_ENABLED(LOAD_FIT) &&
 	    image_get_magic(header) == FDT_MAGIC) {
 		struct spl_load_info load;
 
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 87ecf0bb9e..c00f0ac67b 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -24,6 +24,11 @@ __weak ulong board_spl_fit_size_align(ulong size)
 	return size;
 }
 
+__weak void board_spl_fit_pre_load(struct spl_image_info * image_info, 
+	struct spl_load_info *load_info, void * fit, ulong start_sector, ulong sector_count)
+{
+}
+
 /**
  * spl_fit_get_image_name(): By using the matching configuration subnode,
  * retrieve the name of an image, specified by a property name and an index
@@ -239,7 +244,7 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
 		src = (void *)data;
 	}
 
-#ifdef CONFIG_SPL_FIT_SIGNATURE
+#if CONFIG_IS_ENABLED(FIT_SIGNATURE)
 	printf("## Checking hash(es) for Image %s ... ",
 	       fit_get_name(fit, node, NULL));
 	if (!fit_image_verify_with_data(fit, node,
@@ -389,6 +394,9 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 	if (count == 0)
 		return -EIO;
 
+	/* Do any preprocessing */
+	board_spl_fit_pre_load(spl_image, info, fit, sector, sectors);
+
 	/* find the node holding the images information */
 	images = fdt_path_offset(fit, FIT_IMAGES_PATH);
 	if (images < 0) {
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 324d91c884..75d559d5b6 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -68,7 +68,7 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image,
 		goto end;
 	}
 
-	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	if (CONFIG_IS_ENABLED(LOAD_FIT) &&
 	    image_get_magic(header) == FDT_MAGIC) {
 		struct spl_load_info load;
 
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index e2bcefb111..b447595467 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -52,7 +52,7 @@ static int spl_nand_load_element(struct spl_image_info *spl_image,
 	if (err)
 		return err;
 
-	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	if (CONFIG_IS_ENABLED(LOAD_FIT) &&
 	    image_get_magic(header) == FDT_MAGIC) {
 		struct spl_load_info load;
 
diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c
index c91ad2b6dd..af176cc284 100644
--- a/common/spl/spl_net.c
+++ b/common/spl/spl_net.c
@@ -44,7 +44,7 @@ static int spl_net_load_image(struct spl_image_info *spl_image,
 		return rv;
 	}
 
-	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	if (CONFIG_IS_ENABLED(LOAD_FIT) &&
 	    image_get_magic(header) == FDT_MAGIC) {
 		struct spl_load_info load;
 
diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c
index 969e319de0..78cdbc30ea 100644
--- a/common/spl/spl_nor.c
+++ b/common/spl/spl_nor.c
@@ -38,7 +38,7 @@ static int spl_nor_load_image(struct spl_image_info *spl_image,
 		 * location in SDRAM
 		 */
 		header = (const struct image_header *)CONFIG_SYS_OS_BASE;
-#ifdef CONFIG_SPL_LOAD_FIT
+#if CONFIG_IS_ENABLED(LOAD_FIT)
 		if (image_get_magic(header) == FDT_MAGIC) {
 			debug("Found FIT\n");
 			load.bl_len = 1;
diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c
index 954e91a004..7527c49434 100644
--- a/common/spl/spl_ram.c
+++ b/common/spl/spl_ram.c
@@ -40,7 +40,7 @@ static int spl_ram_load_image(struct spl_image_info *spl_image,
 		spl_dfu_cmd(0, "dfu_alt_info_ram", "ram", "0");
 #endif
 
-	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	if (CONFIG_IS_ENABLED(LOAD_FIT) &&
 	    image_get_magic(header) == FDT_MAGIC) {
 		struct spl_load_info load;
 
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index 9b74473377..68f4af7973 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -120,7 +120,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image,
 				return err;
 			err = spl_parse_image_header(spl_image,
 					(struct image_header *)CONFIG_SYS_LOAD_ADDR);
-		} else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+		} else if (CONFIG_IS_ENABLED(LOAD_FIT) &&
 			   image_get_magic(header) == FDT_MAGIC) {
 			struct spl_load_info load;
 
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index fa539ecd7a..fbd3f7e987 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -107,7 +107,7 @@ static int spl_ymodem_load_image(struct spl_image_info *spl_image,
 		ret = spl_parse_image_header(spl_image, ih);
 		if (ret)
 			return ret;
-	} else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	} else if (CONFIG_IS_ENABLED(LOAD_FIT) &&
 	    image_get_magic((struct image_header *)buf) == FDT_MAGIC) {
 		struct spl_load_info load;
 		struct ymodem_fit_info info;
diff --git a/config.mk b/config.mk
index caf0dd9b81..46eca2d7dc 100644
--- a/config.mk
+++ b/config.mk
@@ -73,6 +73,8 @@ PLATFORM_CPPFLAGS += -pipe
 LDFLAGS += $(PLATFORM_LDFLAGS)
 LDFLAGS_FINAL += -Bstatic
 
+PLATFORM_CPPFLAGS += -DFIRMWARE_RECOVER_FROM_TFTP_SERVER -DCONFIG_SYS_NMRP -DDNI_NAND -DCONFIG_SYS_SINGLE_FIRMWARE
+
 export PLATFORM_CPPFLAGS
 export RELFLAGS
 export LDFLAGS_FINAL
diff --git a/configs/bcm947622_defconfig b/configs/bcm947622_defconfig
new file mode 100644
index 0000000000..7eba3fb2fe
--- /dev/null
+++ b/configs/bcm947622_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM47622=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x8523C000
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x10000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM947622=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv7/u-boot.lds"
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x10000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x8520c000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_MMC_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm947622"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCMBCA=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_BCMBCA=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_BCMBCA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm94908_defconfig b/configs/bcm94908_defconfig
new file mode 100644
index 0000000000..91e2f5acb7
--- /dev/null
+++ b/configs/bcm94908_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM4908=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x822cb810
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x10000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM94908=y
+CONFIG_TPL_MAX_SIZE=1048576
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds"
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x11000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x822a0000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_MMC_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm94908"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCMBCA=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_BCMBCA=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_BCMBCA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm94908_ram_defconfig b/configs/bcm94908_ram_defconfig
new file mode 100644
index 0000000000..59ee75023c
--- /dev/null
+++ b/configs/bcm94908_ram_defconfig
@@ -0,0 +1,52 @@
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCM4908=y
+CONFIG_SYS_TEXT_BASE=0x10000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_BCM94908=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_CACHE=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm94908"
+# CONFIG_NET is not set
+CONFIG_BLK=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_BCM6345_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_BCM6858=y
+CONFIG_LED_BLINK=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_NAND_BRCMNAND_4908=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+# CONFIG_SPL_SERIAL_PRESENT is not set
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_BCM6345=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm94912_defconfig b/configs/bcm94912_defconfig
new file mode 100644
index 0000000000..e46c5cc131
--- /dev/null
+++ b/configs/bcm94912_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM4912=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x82000000
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x5000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM94912=y
+CONFIG_TPL_MAX_SIZE=1048576
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds"
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x10000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x82010000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_MMC_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm94912"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCMBCA=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm94912_ikos_defconfig b/configs/bcm94912_ikos_defconfig
new file mode 100644
index 0000000000..1aef785033
--- /dev/null
+++ b/configs/bcm94912_ikos_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM4912=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_REGINIT=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x82000000
+CONFIG_BCMBCA_IKOS=y
+CONFIG_TARGET_BCM94912=y
+CONFIG_TPL_MAX_SIZE=1048576
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x82010000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm94912"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_BAUDRATE=1500000
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm94912_nor_xip_ikos_defconfig b/configs/bcm94912_nor_xip_ikos_defconfig
new file mode 100644
index 0000000000..ced3cc23d7
--- /dev/null
+++ b/configs/bcm94912_nor_xip_ikos_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM4912=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_REGINIT=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x82000000
+CONFIG_BCMBCA_IKOS=y
+CONFIG_TARGET_BCM94912=y
+CONFIG_TPL_MAX_SIZE=1048576
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x82010000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_XIP_SUPPORT=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_DEFAULT_DEVICE_TREE="bcm94912"
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_BAUDRATE=1500000
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm963138_defconfig b/configs/bcm963138_defconfig
new file mode 100644
index 0000000000..1d360035cf
--- /dev/null
+++ b/configs/bcm963138_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM63138=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x80750000
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x10000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM963138=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv7/u-boot.lds"
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x10000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x80700000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_MMC_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm963138"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCMBCA=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_BCMBCA=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_BCMBCA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm963146_defconfig b/configs/bcm963146_defconfig
new file mode 100644
index 0000000000..45a47a9d33
--- /dev/null
+++ b/configs/bcm963146_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM63146=y
+# CONFIG_BCMBCA_PMC_XRDP is not set
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x82000000
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x5000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TPL_MAX_SIZE=1048576
+CONFIG_TARGET_BCM963146=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds"
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x10000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x82010000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_MMC_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm963146"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCMBCA=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm963146_ikos_defconfig b/configs/bcm963146_ikos_defconfig
new file mode 100644
index 0000000000..18f83eda52
--- /dev/null
+++ b/configs/bcm963146_ikos_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM63146=y
+# CONFIG_BCMBCA_PMC_XRDP is not set
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x82000000
+CONFIG_BCMBCA_IKOS=y
+CONFIG_TPL_MAX_SIZE=1048576
+CONFIG_TARGET_BCM963146=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x82010000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm963146"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_BAUDRATE=1500000
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm963146_nor_xip_defconfig b/configs/bcm963146_nor_xip_defconfig
new file mode 100755
index 0000000000..f7ebfb08c7
--- /dev/null
+++ b/configs/bcm963146_nor_xip_defconfig
@@ -0,0 +1,80 @@
+CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM63146=y
+# CONFIG_BCMBCA_PMC_XRDP is not set
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x82000000
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x5000
+CONFIG_TPL_MAX_SIZE=1048576
+CONFIG_TARGET_BCM963146=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x82010000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_XIP_SUPPORT=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm963146"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm963146_nor_xip_ikos_defconfig b/configs/bcm963146_nor_xip_ikos_defconfig
new file mode 100755
index 0000000000..b60d57815a
--- /dev/null
+++ b/configs/bcm963146_nor_xip_ikos_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM63146=y
+# CONFIG_BCMBCA_PMC_XRDP is not set
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_REGINIT=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x82000000
+CONFIG_BCMBCA_IKOS=y
+CONFIG_TPL_MAX_SIZE=1048576
+CONFIG_TARGET_BCM963146=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x82010000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_XIP_SUPPORT=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_DEFAULT_DEVICE_TREE="bcm963146"
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_BAUDRATE=1500000
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm963148_defconfig b/configs/bcm963148_defconfig
new file mode 100644
index 0000000000..6ea5872a2d
--- /dev/null
+++ b/configs/bcm963148_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM63148=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x80750000
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x10000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM963148=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv7/u-boot.lds"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x80700000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm963148"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_BCMBCA=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_BCMBCA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm963158_defconfig b/configs/bcm963158_defconfig
new file mode 100644
index 0000000000..1476156823
--- /dev/null
+++ b/configs/bcm963158_defconfig
@@ -0,0 +1,112 @@
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM63158=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x80850000
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x10000
+CONFIG_TARGET_BCM963158=y
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TPL_MAX_SIZE=1048576
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds"
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x10000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DISABLE_CONSOLE=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x80820000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_MMC_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm963158"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCMBCA=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_BCMBCA=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_BCMBCA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm963178_defconfig b/configs/bcm963178_defconfig
new file mode 100644
index 0000000000..22410f9162
--- /dev/null
+++ b/configs/bcm963178_defconfig
@@ -0,0 +1,92 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM63178=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x8423C000
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x10000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM963178=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv7/u-boot.lds"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x8420C000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm963178"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_BCMBCA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm96756_defconfig b/configs/bcm96756_defconfig
new file mode 100644
index 0000000000..7a7b8b815b
--- /dev/null
+++ b/configs/bcm96756_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM6756=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x8523C000
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x10000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM96756=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv7/u-boot.lds"
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x10000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x85200000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_MMC_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm96756"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCMBCA=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_BCMBCA=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_BCMBCA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm96846_defconfig b/configs/bcm96846_defconfig
new file mode 100644
index 0000000000..41dba36cee
--- /dev/null
+++ b/configs/bcm96846_defconfig
@@ -0,0 +1,102 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM6846=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x82600400
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x8000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM96846=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv7/u-boot.lds"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x8260c100
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm96846"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_BCMBCA=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_BCMBCA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm96855_defconfig b/configs/bcm96855_defconfig
new file mode 100644
index 0000000000..3c5a59fe3f
--- /dev/null
+++ b/configs/bcm96855_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM6855=y
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM96855=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv7/u-boot.lds"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x82000000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm96855"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm96855_nand_xip_ikos_defconfig b/configs/bcm96855_nand_xip_ikos_defconfig
new file mode 100755
index 0000000000..48539dd26c
--- /dev/null
+++ b/configs/bcm96855_nand_xip_ikos_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM6855=y
+CONFIG_BCMBCA_IKOS=y
+CONFIG_TARGET_BCM96855=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv7/u-boot.lds"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_SPL_TEXT_BASE=0x82000000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_MMC_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm96855"
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_BAUDRATE=1562500
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
diff --git a/configs/bcm96856_defconfig b/configs/bcm96856_defconfig
new file mode 100644
index 0000000000..899cb158fd
--- /dev/null
+++ b/configs/bcm96856_defconfig
@@ -0,0 +1,117 @@
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM6856=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x82600400
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x10000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM96856=y
+CONFIG_TPL_MAX_SIZE=1048576
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds"
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x10000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_TEXT_BASE=0x82612000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_MMC_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm96856"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCMBCA=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_BCMBCA=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_BCMBCA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig
index d331e4e807..78af81eac3 100644
--- a/configs/bcm968580xref_ram_defconfig
+++ b/configs/bcm968580xref_ram_defconfig
@@ -18,6 +18,8 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
@@ -35,12 +37,19 @@ CONFIG_MTD=y
 CONFIG_NAND=y
 CONFIG_NAND_BRCMNAND=y
 CONFIG_NAND_BRCMNAND_6858=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 CONFIG_CONS_INDEX=0
 CONFIG_DM_SERIAL=y
 CONFIG_SERIAL_SEARCH_ALL=y
 CONFIG_BCM6345_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_BCM63XX_HSSPI=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_WDT_BCM6345=y
diff --git a/configs/bcm96858_defconfig b/configs/bcm96858_defconfig
new file mode 100644
index 0000000000..df07293f5c
--- /dev/null
+++ b/configs/bcm96858_defconfig
@@ -0,0 +1,117 @@
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM6858=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x82600400
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x10000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM96858=y
+CONFIG_TPL_MAX_SIZE=1048576
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv8/u-boot.lds"
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x10000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_TEXT_BASE=0x82620000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_MMC_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm96858"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_BCMBCA=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_BCM6345_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_BCMBCA=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_BCMBCA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/configs/bcm96878_defconfig b/configs/bcm96878_defconfig
new file mode 100644
index 0000000000..f7ae2a98db
--- /dev/null
+++ b/configs/bcm96878_defconfig
@@ -0,0 +1,101 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_BCM6878=y
+CONFIG_BCMBCA_DDRC=y
+CONFIG_BCMBCA_DDR_LOADADDR=0x82610000
+CONFIG_BOOT_BLOB_JTAG_LOAD_MAX_DDR_SIZE=0x8000
+CONFIG_BCMBCA_HTTPD=y
+CONFIG_BCMBCA_BOARD_SPECIFIC_DT=y
+CONFIG_BCM_BOOTSTATE=y
+CONFIG_TARGET_BCM96878=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TPL_TEXT_BASE=0x05000000
+CONFIG_TPL_LDSCRIPT="arch/arm/cpu/armv7/u-boot.lds"
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_IMAGE_FORMAT_LEGACY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_LOG=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_TEXT_BASE=0x82600000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_TPL_ATF=y
+CONFIG_TPL=y
+CONFIG_TPL_NEEDS_SEPARATE_TEXT_BASE=y
+CONFIG_TPL_ENV_SUPPORT=y
+CONFIG_TPL_NAND_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_STANDALONE=y
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_DEFAULT_DEVICE_TREE="bcm96878"
+CONFIG_ENV_IS_IN_BOOT_MAGIC=y
+CONFIG_TFTP_BLOCKSIZE=1024
+CONFIG_TPL_DM=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_LED_BLINK=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_BCMBCA=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=0
+CONFIG_DM_SERIAL=y
+CONFIG_SERIAL_SEARCH_ALL=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_BCMBCA=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_BCMBCA=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_WDT_BCM6345=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZMA=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/disk/Kconfig b/disk/Kconfig
index 28fb81c2ee..10036fdbed 100644
--- a/disk/Kconfig
+++ b/disk/Kconfig
@@ -114,6 +114,12 @@ config SPL_EFI_PARTITION
 	depends on  SPL && PARTITIONS
 	default y if EFI_PARTITION
 
+
+config TPL_EFI_PARTITION
+	bool "Enable EFI GPT partition table for TPL"
+	depends on  SPL && PARTITIONS
+	default y if EFI_PARTITION
+
 config PARTITION_UUIDS
 	bool "Enable support of UUID for partition"
 	depends on PARTITIONS
@@ -128,6 +134,12 @@ config SPL_PARTITION_UUIDS
 	depends on SPL && PARTITIONS
 	default y if SPL_EFI_PARTITION
 
+
+config TPL_PARTITION_UUIDS
+	bool "Enable support of UUID for partition in TPL"
+	depends on SPL && PARTITIONS
+	default y if SPL_EFI_PARTITION
+
 config PARTITION_TYPE_GUID
 	bool "Enable support of GUID for partition type"
 	depends on PARTITIONS
diff --git a/disk/Makefile b/disk/Makefile
index ccd0335959..6018b87f81 100644
--- a/disk/Makefile
+++ b/disk/Makefile
@@ -6,8 +6,8 @@
 #ccflags-y += -DET_DEBUG -DDEBUG
 
 obj-$(CONFIG_PARTITIONS) 	+= part.o
-obj-$(CONFIG_$(SPL_)MAC_PARTITION)   += part_mac.o
-obj-$(CONFIG_$(SPL_)DOS_PARTITION)   += part_dos.o
-obj-$(CONFIG_$(SPL_)ISO_PARTITION)   += part_iso.o
-obj-$(CONFIG_$(SPL_)AMIGA_PARTITION) += part_amiga.o
-obj-$(CONFIG_$(SPL_)EFI_PARTITION)   += part_efi.o
+obj-$(CONFIG_$(SPL_TPL_)MAC_PARTITION)   += part_mac.o
+obj-$(CONFIG_$(SPL_TPL_)DOS_PARTITION)   += part_dos.o
+obj-$(CONFIG_$(SPL_TPL_)ISO_PARTITION)   += part_iso.o
+obj-$(CONFIG_$(SPL_TPL_)AMIGA_PARTITION) += part_amiga.o
+obj-$(CONFIG_$(SPL_TPL_)EFI_PARTITION)   += part_efi.o
diff --git a/drivers/Makefile b/drivers/Makefile
index 6635dabd2c..f67a5b816b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -24,13 +24,14 @@ obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/
 obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/
 obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/
 obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
+obj-$(CONFIG_$(SPL_TPL_)UBI) += mtd/ubispl/
+obj-$(CONFIG_$(SPL_TPL_)CRYPTO_SUPPORT) += crypto/
 
 ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_BUILD
 
 obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/
 obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
-obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
 obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
 obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
@@ -42,7 +43,6 @@ obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/
 obj-$(CONFIG_SPL_DM_RESET) += reset/
 obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
 obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
-obj-$(CONFIG_SPL_UBI) += mtd/ubispl/
 obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
@@ -60,10 +60,12 @@ obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 obj-$(CONFIG_SPL_THERMAL) += thermal/
 
 endif
+else
+obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/
 endif
 
 ifdef CONFIG_TPL_BUILD
-
+obj-$(CONFIG_TPL_MTD_SUPPORT) += mtd/
 obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
 
 endif
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 3feb0aa997..caaf10ed2b 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -3,7 +3,7 @@
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
-obj-$(CONFIG_$(SPL_)BLK) += blk-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)BLK) += blk-uclass.o
 
 ifndef CONFIG_$(SPL_)BLK
 obj-y += blk_legacy.o
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 2d195ae35e..419738cae9 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -99,6 +99,15 @@ config SPL_DM_SEQ_ALIAS
 	  numbered devices (e.g. serial0 = &serial0). This feature can be
 	  disabled if it is not required, to save code space in SPL.
 
+config TPL_DM_SEQ_ALIAS
+	bool "Support numbered aliases in device tree in SPL"
+	depends on DM
+	default n
+	help
+	  Most boards will have a '/aliases' node containing the path to
+	  numbered devices (e.g. serial0 = &serial0). This feature can be
+	  disabled if it is not required, to save code space in TPL.
+
 config REGMAP
 	bool "Support register maps"
 	depends on DM
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e36a8abc42..f2c419085d 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -362,4 +362,10 @@ config MT7621_GPIO
 	help
 	  Say yes here to support MediaTek MT7621 compatible GPIOs.
 
+config BCMBCA_GPIO
+	bool "BCMBCA GPIO driver"
+	depends on DM_GPIO && ARCH_BCMBCA && PINCTRL_BCMBCA 
+	help
+	  This driver supports the GPIO on BCMBCA SoC's.
+
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 7337153e0e..4c4f724161 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -61,3 +61,4 @@ obj-$(CONFIG_$(SPL_)PCF8575_GPIO)	+= pcf8575_gpio.o
 obj-$(CONFIG_PM8916_GPIO)	+= pm8916_gpio.o
 obj-$(CONFIG_MT7621_GPIO)	+= mt7621_gpio.o
 obj-$(CONFIG_MSCC_SGPIO)	+= mscc_sgpio.o
+obj-$(CONFIG_BCMBCA_GPIO)   += gpio-bcm-bca.o 
diff --git a/drivers/gpio/gpio-bcm-bca.c b/drivers/gpio/gpio-bcm-bca.c
new file mode 100644
index 0000000000..fd992fa094
--- /dev/null
+++ b/drivers/gpio/gpio-bcm-bca.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ *  
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#define GPIO_TO_IDX(gpio)   ((gpio) >> 5)
+#define GPIO_TO_MASK(gpio)  (1<<((gpio) & 0x1f))
+#define GPIO_TO_SHIFT(gpio) ((gpio) & 0x1f)
+
+struct bcmbca_gpio {
+    void __iomem *gpio_dir_base;
+    void __iomem *gpio_data_base;
+};
+
+static inline struct bcmbca_gpio *to_bca_gpio(struct udevice *dev)
+{
+    return dev_get_priv(dev);
+}
+
+static int bcmbca_gpio_direction_input(struct udevice *dev, unsigned gpio)
+{
+    struct bcmbca_gpio *bca_gpio;
+    volatile uint32_t *gpio_dir;
+
+    bca_gpio = to_bca_gpio(dev);
+    gpio_dir = (volatile uint32_t *)bca_gpio->gpio_dir_base;
+
+    gpio_dir[GPIO_TO_IDX(gpio)] &= ~GPIO_TO_MASK(gpio);
+
+
+    return 0;
+}
+
+static int bcmbca_gpio_direction_output(struct udevice *dev, unsigned gpio, int value)
+{
+    struct bcmbca_gpio *bca_gpio;
+    volatile uint32_t *gpio_dir;
+    volatile uint32_t *gpio_data;
+
+    bca_gpio = to_bca_gpio(dev);
+    gpio_dir = (volatile uint32_t *)bca_gpio->gpio_dir_base;
+    gpio_data = (volatile uint32_t *)bca_gpio->gpio_data_base;
+
+    gpio_dir[GPIO_TO_IDX(gpio)] |= GPIO_TO_MASK(gpio);
+
+    if (value)
+        gpio_data[GPIO_TO_IDX(gpio)] |= GPIO_TO_MASK(gpio);
+    else
+        gpio_data[GPIO_TO_IDX(gpio)] &= ~GPIO_TO_MASK(gpio);
+
+
+    return 0;
+}
+
+static int bcmbca_gpio_get_direction(struct udevice *dev, unsigned gpio)
+{
+    struct bcmbca_gpio *bca_gpio;
+    volatile uint32_t *gpio_dir;
+    u32 val;
+
+    bca_gpio = to_bca_gpio(dev);
+    gpio_dir = (volatile uint32_t *)bca_gpio->gpio_dir_base;
+
+    val = (gpio_dir[GPIO_TO_IDX(gpio)] & GPIO_TO_MASK(gpio)) >> GPIO_TO_SHIFT(gpio);
+
+    return val ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static int bcmbca_gpio_get(struct udevice *dev, unsigned gpio)
+{
+    struct bcmbca_gpio *bca_gpio;
+    volatile uint32_t *gpio_data;
+    u32 val;
+
+    bca_gpio = to_bca_gpio(dev);
+    gpio_data = (volatile uint32_t *)bca_gpio->gpio_data_base;
+
+    val = (gpio_data[GPIO_TO_IDX(gpio)] & GPIO_TO_MASK(gpio)) >> GPIO_TO_SHIFT(gpio);
+
+    return (int)val;
+}
+
+static int bcmbca_gpio_set(struct udevice *dev, unsigned gpio, int value)
+{
+    struct bcmbca_gpio *bca_gpio;
+    volatile uint32_t *gpio_data;
+
+    bca_gpio = to_bca_gpio(dev);
+    gpio_data = (volatile uint32_t *)bca_gpio->gpio_data_base;
+
+    if (value)
+        gpio_data[GPIO_TO_IDX(gpio)] |= GPIO_TO_MASK(gpio);
+    else
+        gpio_data[GPIO_TO_IDX(gpio)] &= ~GPIO_TO_MASK(gpio);
+
+    return 0;
+}
+
+static int bcmbca_gpio_request(struct udevice *dev, unsigned offset, const char *label)
+{
+    return pinctrl_gpio_request(dev, offset);
+}
+
+static const struct dm_gpio_ops bcmbca_gpio_ops = {
+    .request = bcmbca_gpio_request,
+    .get_function = bcmbca_gpio_get_direction,
+    .direction_input = bcmbca_gpio_direction_input,
+    .direction_output = bcmbca_gpio_direction_output,
+    .get_value = bcmbca_gpio_get,
+    .set_value = bcmbca_gpio_set,
+};
+
+static struct udevice_id const bcmbca_gpio_of_match[] = {
+    { .compatible = "brcm,bca-gpio" },
+    {}
+};
+
+static int bcmbca_gpio_probe(struct udevice *dev)
+{
+    struct gpio_dev_priv *chip = dev_get_uclass_priv(dev);
+    struct bcmbca_gpio *bca_gpio = dev_get_priv(dev); 
+    int ret;
+    unsigned int ngpio = 0;
+
+    if (dev_read_u32u(dev, "ngpios", &ngpio)) 
+    {
+        printf("Missing ngpios OF property\n");
+        ret = -EINVAL;
+        goto error;
+    }
+
+    bca_gpio->gpio_dir_base = dev_remap_addr_name(dev, "gpio-dir");
+    if (!bca_gpio->gpio_dir_base) 
+    {
+        printf("Failed to find/map the gpio-dir resource\n");
+        ret = -ENXIO;
+        goto error;
+    }
+
+    bca_gpio->gpio_data_base = dev_remap_addr_name(dev, "gpio-data");
+    if (!bca_gpio->gpio_data_base) 
+    {
+        printf("Failed to find/map the gpio-data resource\n");
+        ret = -ENXIO;
+        goto error;
+    }
+
+    chip->gpio_count = ngpio;
+    chip->bank_name = dev->name;
+    chip->gpio_base = 0;
+
+    return 0;
+
+error:
+    bca_gpio->gpio_data_base = NULL;
+    bca_gpio->gpio_dir_base = NULL;
+
+    return ret;
+}
+
+U_BOOT_DRIVER(bcmbca_gpio) = {
+    .name = "bcm-bca-gpio",
+    .id = UCLASS_GPIO,
+    .of_match = bcmbca_gpio_of_match,
+    .ops = &bcmbca_gpio_ops,
+    .priv_auto_alloc_size = sizeof(struct bcmbca_gpio),
+    .probe = bcmbca_gpio_probe,
+};
+
diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
index 5643939348..f10fdffcbf 100644
--- a/drivers/led/Kconfig
+++ b/drivers/led/Kconfig
@@ -69,6 +69,13 @@ config SPL_LED_GPIO
 	  This option is an SPL-variant of the LED_GPIO option.
 	  See the help of LED_GPIO for details.
 
+config BCM_BCA_LED
+	bool "LED Support for BCMBCA devices"
+	depends on LED && ARCH_BCMBCA
+	help
+	  This option enables support for LEDs connected to the all BCMBCA based devices
+	  HW has blinking capabilities and up to 32 LEDs can be controlled.
+
 config LED_STATUS
 	bool "Enable status LED API"
 	help
diff --git a/drivers/led/Makefile b/drivers/led/Makefile
index 3654dd3c04..71bc94e9f8 100644
--- a/drivers/led/Makefile
+++ b/drivers/led/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_LED_BCM6328) += led_bcm6328.o
 obj-$(CONFIG_LED_BCM6358) += led_bcm6358.o
 obj-$(CONFIG_LED_BCM6858) += led_bcm6858.o
 obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o
+obj-$(CONFIG_BCM_BCA_LED) += bcm_bca_led_ctrl.o bcm_bca_cled_ctrl.o bcm_bca_leds.o
diff --git a/drivers/led/bcm_bca_cled_ctrl.c b/drivers/led/bcm_bca_cled_ctrl.c
new file mode 100644
index 0000000000..cc4bdde2b7
--- /dev/null
+++ b/drivers/led/bcm_bca_cled_ctrl.c
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ *  
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/ofnode.h>
+#include <errno.h>
+#include <led.h>
+#include <asm/io.h>
+
+enum LP_CLED_REGS {
+    CLED_CTRL = 0,
+    CLED_HW_EN,
+    CLED_SERIAL_SHIFT_SEL,
+    CLED_HW_POLARITY,
+    CLED_SW_SET,
+    CLED_SW_POLARITY,
+    CLED_CH_ACT,
+    CLED_XX_CONFIG,
+    CLED_SW_CLEAR,
+    CLED_SW_STATUS,
+    CLED_MUX,
+    CLED_SERIAL_POLARITY,
+    CLED_PARALLEL_POLARITY,
+    CLED_MAX_REG,
+};
+
+struct bcm_bca_cled_ctrl {
+    void __iomem *led_regs[CLED_MAX_REG];
+    uint8_t max_supported_leds;
+    uint8_t serial_shifters_num;
+    uint32_t serial_led_map;
+    uint8_t active_serial_led_count;
+    uint32_t mux_maped;
+};
+
+static struct bcm_bca_cled_ctrl *bca_cled = NULL;
+
+static const struct udevice_id bca_cled_ctrl_of_match[] = {
+	{ .compatible = "brcm,bca-cleds-ctrl", },
+	{ },
+};
+
+static const ofnode of_parse_phandle(const ofnode handle, const char *phandle_name, int index)
+{
+    ofnode node = ofnode_null();
+    struct ofnode_phandle_args out_args;
+
+    if (ofnode_parse_phandle_with_args(handle, phandle_name, NULL, 0, index, &out_args) == 0)
+    {
+        node = out_args.node;
+    }
+    return node;
+}
+
+static int bca_cled_ctrl_probe(struct udevice *dev)
+{
+    unsigned int val = 0;
+	int ret;
+    int i;
+    bool serial_msb_first = 0;
+    bool serial_data_polarity_low = 0;
+    uint32_t reg_val;
+    ofnode serial_pinctrl;
+
+    char *reg_names[CLED_MAX_REG] = { "glbl_ctrl", "hw_en", "ser_shift", "hw_polarity", 
+    "sw_set", "sw_polarity", "ch_activate", "ch_config", "sw_clear", "sw_status",
+    "out_mux","ser_polarity", "par_polarity" }; 
+
+	bca_cled = dev_get_priv(dev);
+
+    if(dev_read_u32u(dev, "nleds", &val))
+    {
+        printf("nleds property not present\n");
+        ret = -EINVAL;
+        goto error;
+    }
+
+    bca_cled->max_supported_leds = (uint8_t)val;
+    printf("max supported leds %d[%d]\n", bca_cled->max_supported_leds, val);
+
+    serial_pinctrl = of_parse_phandle(dev_ofnode(dev), "pinctrl-0", 0);
+
+    if (serial_pinctrl.of_offset != -1)
+    {
+
+        if (dev_read_u32u(dev, "serial-shifters-installed", &val)) 
+        {
+            printf("The serial-shifters-installed property not present while Serial LED controller interface is configured\n");
+            ret = -EINVAL;
+            goto error;
+        }
+
+        bca_cled->serial_shifters_num = (uint8_t)val;
+
+        serial_msb_first = dev_read_bool(dev, "serial-order-msb-first");
+        serial_data_polarity_low =  dev_read_bool(dev, "serial-data-polarity-low");
+        printf("Serial CLED interface found num shifters %d serial data polarity low %d\n",
+            bca_cled->serial_shifters_num, serial_data_polarity_low);
+    }
+    else
+    {
+        printf(" Parallel CLED interface found\n");
+    }
+
+    for (i = 0; i < CLED_MAX_REG; i++)
+    {
+        bca_cled->led_regs[i] = dev_remap_addr_name(dev, reg_names[i]);
+        if (bca_cled->led_regs[i] == NULL)
+        {
+            printf("Failed to find %s resource\n", reg_names[i]);
+            ret = -EINVAL;
+            goto error;
+        }
+    }
+
+    if (!dev_read_u32u(dev, "hw-polarity-quirk", &val)) 
+    {
+        *(volatile uint32_t *)(bca_cled->led_regs[CLED_HW_POLARITY]) = (uint32_t)val;
+    }
+
+    if (!dev_read_u32u(dev, "sw-polarity-quirk", &val)) 
+    {
+        *(volatile uint32_t *)(bca_cled->led_regs[CLED_SW_POLARITY]) = (uint32_t)val;
+    }
+
+
+    *(volatile uint32_t *)(bca_cled->led_regs[CLED_CTRL]) &= ~(0xa);
+    if (serial_data_polarity_low)
+        reg_val = 0x8;
+    else
+        reg_val = 0xa;
+
+    if (serial_msb_first)
+        reg_val |= 0x10;
+    else
+        *(volatile uint32_t *)(bca_cled->led_regs[CLED_CTRL]) &= ~(0x10);
+
+    *(volatile uint32_t *)(bca_cled->led_regs[CLED_CTRL]) |= reg_val;
+    *(volatile uint32_t *)(bca_cled->led_regs[CLED_HW_EN]) = 0;
+    *(volatile uint32_t *)(bca_cled->led_regs[CLED_SERIAL_POLARITY]) = 0;
+    *(volatile uint32_t *)(bca_cled->led_regs[CLED_PARALLEL_POLARITY]) = 0;
+
+    printf("BCA CLED Controller initialized\n");
+    
+    return 0;
+
+error:
+    return ret;
+}
+
+static int bca_cled_ctrl_bind(struct udevice *parent)
+{
+	ofnode node;
+
+	dev_for_each_subnode(node, parent) {
+		struct led_uc_plat *uc_plat;
+		struct udevice *dev;
+		const char *label;
+		int ret;
+
+		ret = device_bind_driver_to_node(parent, "bcm-bca-leds", ofnode_get_name(node),
+            node, &dev);
+		if (ret)
+        {
+            if (ret != -ENODEV)
+                printf("failed to bind node %s ret %d\n", ofnode_get_name(node), ret);
+            continue;
+        }
+
+		label = ofnode_read_string(node, "label");
+        if (label)
+        {
+            uc_plat = dev_get_uclass_platdata(dev);
+            uc_plat->label = label;
+        }
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(bcm_bca_cled_ctrl_driver) = {
+    .name = "bcm-bca-cled-ctrl",
+	.id = UCLASS_LED,
+	.probe = bca_cled_ctrl_probe,
+    .bind = bca_cled_ctrl_bind,
+    .of_match = bca_cled_ctrl_of_match,
+	.priv_auto_alloc_size = sizeof(struct bcm_bca_cled_ctrl),
+};
+
+struct cled_cfg {
+    union {
+        struct {
+            unsigned int mode:2;            /* [01]-[00] */
+            unsigned int reserved1:1;       /* [02]-[02] */
+            unsigned int flash_ctrl:3;      /* [05]-[03] */
+            unsigned int bright_ctrl:8;     /* [13]-[06] */
+            unsigned int repeat_cycle:1;    /* [14]-[14] */
+            unsigned int change_dir:1;      /* [15]-[15] */
+            unsigned int phas_1_bright:1;   /* [16]-[16] */
+            unsigned int phas_2_bright:1;   /* [17]-[17] */
+            unsigned int reserved2:2;       /* [19]-[18] */
+            unsigned int init_delay:4;      /* [23]-[20] */
+            unsigned int final_delay:4;     /* [27]-[24] */
+            unsigned int color_blend_c:4;   /* [31]-[28] */
+        } Bits;
+        uint32_t Reg;
+    }cfg0;
+    union {
+        struct {
+            unsigned int b_step_1:4;        /* [03]-[00] */
+            unsigned int t_step_1:4;        /* [07]-[04] */
+            unsigned int n_step_1:4;        /* [11]-[08] */
+            unsigned int b_step_2:4;        /* [15]-[12] */
+            unsigned int t_step_2:4;        /* [19]-[16] */
+            unsigned int n_step_2:4;        /* [23]-[20] */
+            unsigned int reserved:8;        /* [31]-[24] */
+        } Bits;
+        uint32_t Reg;
+    }cfg1;
+    union {
+        struct {
+            unsigned int b_step_3:4;        /* [03]-[00] */
+            unsigned int t_step_3:4;        /* [07]-[04] */
+            unsigned int n_step_3:4;        /* [11]-[08] */
+            unsigned int final_step:4;      /* [15]-[12] */
+            unsigned int reserved:16;       /* [31]-[16] */
+        } Bits;
+        uint32_t Reg;
+    }cfg2;
+    union {
+        struct {
+            unsigned int phase_delay_1:16;  /* [15]-[00] */
+            unsigned int phase_delay_2:16;  /* [31]-[16] */
+        } Bits;
+        uint32_t Reg;
+    }cfg3;
+};
+
+static int setup_crossbar(ofnode np, unsigned int led_num)
+{
+    uint32_t crossbar_output;
+    uint8_t mux_idx = 0;
+    uint32_t mux_mask = 0;
+    uint32_t mux_val = 0;
+    volatile uint32_t *mux_output;
+
+    if(ofnode_read_u32(np, "crossbar-output", &crossbar_output))
+    {
+        printf( "crossbar-output property not present\n");
+        return -EINVAL;
+    }
+
+    if (bca_cled->mux_maped & (1 << crossbar_output))
+    {
+        printf( "crossbar-output is already used\n");
+        return -EINVAL;
+    }
+
+    mux_idx = (crossbar_output >> 2);
+    mux_mask = 0x1f <<((crossbar_output & 0x3) << 3);
+    mux_val = led_num<<((crossbar_output &0x3)<<3);
+
+    mux_output = (volatile uint32_t *)bca_cled->led_regs[CLED_MUX];
+    mux_output[mux_idx] &= ~mux_mask;
+    mux_output[mux_idx] |= mux_val;
+    bca_cled->mux_maped |= (1 << crossbar_output);
+
+    return 0;
+}
+
+int bca_cled_setup_serial(unsigned int led_num, unsigned int polarity, unsigned int is_hw, 
+    const struct udevice *dev, bool is_crossbar)
+{
+    uint32_t led_mask = 1 << led_num;
+    volatile uint32_t *polarity_reg;
+    uint32_t led_map = 0;
+    uint8_t missed_pins;
+    int i;
+
+    if(!bca_cled)
+        return -ENODEV;
+
+    if (led_num > bca_cled->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num,
+            bca_cled->max_supported_leds);
+        return -EINVAL;
+    }
+
+    if (bca_cled->serial_shifters_num == 0)
+    {
+        printf("Serial LED%d is requested, but no serial LED interface defined\n", led_num);
+        return -EINVAL;
+    }
+
+    if (is_crossbar)
+    {
+        if (setup_crossbar(dev_ofnode(dev), led_num))
+            return -EINVAL;
+    }
+
+    polarity_reg = (volatile uint32_t *)bca_cled->led_regs[CLED_SERIAL_POLARITY];
+
+    bca_cled->active_serial_led_count++;
+    if (bca_cled->active_serial_led_count > (bca_cled->serial_shifters_num * 8))
+    {
+        bca_cled->active_serial_led_count--;
+        printf("The number of registered serial LEDs is bigger than supported by this configuration\n" );
+        return -EINVAL;
+    }
+
+    if (is_hw)
+        *(volatile uint32_t *)(bca_cled->led_regs[CLED_HW_EN]) |= led_mask;
+
+    if (polarity)
+        *polarity_reg |= led_mask;
+    else
+        *polarity_reg &= ~(led_mask);
+
+    bca_cled->serial_led_map |= led_mask;
+
+    missed_pins = (bca_cled->serial_shifters_num * 8) - bca_cled->active_serial_led_count;
+
+    led_map = bca_cled->serial_led_map;
+
+    for (i = 31; i>=0 && missed_pins; i--)
+    {
+        if (bca_cled->serial_led_map & (1 << i))
+            break;
+        led_map |= (1 << i);
+        missed_pins--;
+    }
+
+    *(volatile uint32_t *)(bca_cled->led_regs[CLED_SERIAL_SHIFT_SEL]) = led_map;
+    return 0;
+}
+
+int bca_cled_setup_parallel(unsigned int led_num, int polarity, int is_hw, struct udevice *dev, bool is_crossbar)
+{
+    uint32_t led_mask = 1 << led_num;
+    volatile uint32_t *polarity_reg;
+    ofnode led_pinctrl;
+  
+    if(!bca_cled)
+        return -ENODEV;
+
+    if (led_num > bca_cled->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num,
+            bca_cled->max_supported_leds);
+        return -EINVAL;
+    }
+    if(is_crossbar)
+    {
+
+        led_pinctrl = of_parse_phandle(dev_ofnode(dev), "pinctrl-0", 0);
+        if (led_pinctrl.of_offset == -1)
+        {
+            printf("requested parallel LED %d does not define proper pinctrl-0\n", 
+                led_num);
+            return -EINVAL;
+        }
+
+    }
+
+    polarity_reg = (volatile uint32_t *)bca_cled->led_regs[CLED_PARALLEL_POLARITY];
+
+
+    if (is_hw)
+        *(volatile uint32_t *)(bca_cled->led_regs[CLED_HW_EN]) |= led_mask;
+
+    if (polarity)
+        *polarity_reg |= led_mask;
+    else
+        *polarity_reg &= ~(led_mask);
+
+    return 0;
+}
+
+int bca_cled_get_value(unsigned int led_num)
+{
+    uint32_t led_mask = 1 << led_num;
+    
+    if(!bca_cled)
+        return -ENODEV;
+
+    if (led_num > bca_cled->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num,
+            bca_cled->max_supported_leds);
+        return -EINVAL;
+    }
+    
+    return *(volatile uint32_t *)(bca_cled->led_regs[CLED_SW_STATUS]) & led_mask;
+}
+
+int bca_cled_set_value(unsigned int led_num, unsigned int value)
+{
+    uint32_t led_mask = 1 << led_num;
+    
+    if(!bca_cled)
+        return -ENODEV;
+
+    if (led_num > bca_cled->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num,
+            bca_cled->max_supported_leds);
+        return -EINVAL;
+    }
+    if (value)
+        *(volatile uint32_t *)(bca_cled->led_regs[CLED_SW_SET]) = led_mask;
+    else
+        *(volatile uint32_t *)(bca_cled->led_regs[CLED_SW_CLEAR]) = led_mask;
+    
+    return 0;
+}
+
+int bca_cled_set_brightness(unsigned int led_num, unsigned int value)
+{
+    uint32_t led_mask = 1 << led_num;
+    volatile struct cled_cfg *led_config;
+
+    if(!bca_cled)
+        return -ENODEV;
+
+    if (led_num > bca_cled->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num,
+            bca_cled->max_supported_leds);
+        return -EINVAL;
+    }
+
+    led_config = (volatile struct cled_cfg *)(bca_cled->led_regs[CLED_XX_CONFIG]);
+
+    led_config[led_num].cfg0.Bits.bright_ctrl = value;
+    *(volatile uint32_t *)(bca_cled->led_regs[CLED_CH_ACT]) = led_mask;
+    
+    return 0;
+}
+
+int bca_cled_set_flash_rate(unsigned int led_num, unsigned int value)
+{
+    uint32_t led_mask = 1 << led_num;
+    volatile struct cled_cfg *led_config;
+
+    if(!bca_cled)
+        return -ENODEV;
+
+    if (led_num > bca_cled->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num,
+            bca_cled->max_supported_leds);
+        return -EINVAL;
+    }
+
+    led_config = (volatile struct cled_cfg *)(bca_cled->led_regs[CLED_XX_CONFIG]);
+
+    led_config[led_num].cfg0.Bits.flash_ctrl = value;
+    *(volatile uint32_t *)(bca_cled->led_regs[CLED_CH_ACT]) = led_mask;
+    
+    return 0;
+}
+
diff --git a/drivers/led/bcm_bca_led_ctrl.c b/drivers/led/bcm_bca_led_ctrl.c
new file mode 100644
index 0000000000..c08e2dce51
--- /dev/null
+++ b/drivers/led/bcm_bca_led_ctrl.c
@@ -0,0 +1,372 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ *  
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/ofnode.h>
+#include <errno.h>
+#include <led.h>
+#include <asm/io.h>
+
+enum LP_LED_REGS {
+    LED_CTRL = 0,
+    LED_HW_EN,
+    LED_SERIAL_SHIFT_SEL,
+    LED_FLASH_RATE,
+    LED_BRIGHTNESS,
+    LED_POWER_LED_CFG,
+    LED_POWER_LUT,
+    LED_HW_POLARITY,
+    LED_SW_DATA,
+    LED_SW_POLARITY,
+    LED_PARALLEL_POLARITY,
+    LED_SERIAL_POLARITY,
+    LED_LAST_MANDATORY,
+    LED_MASK = LED_LAST_MANDATORY,
+    LED_MAX_REG,
+};
+
+struct bcm_bca_led_ctrl {
+    void __iomem *led_regs[LED_MAX_REG];
+    uint8_t max_supported_leds;
+    uint8_t serial_shifters_num;
+    uint32_t serial_led_map;
+    uint8_t active_serial_led_count;
+};
+
+static struct bcm_bca_led_ctrl *bca_led = NULL;
+
+static const struct udevice_id bca_led_ctrl_of_match[] = {
+	{ .compatible = "brcm,bca-leds-ctrl", },
+	{ },
+};
+
+static const ofnode of_parse_phandle(const ofnode handle, const char *phandle_name, int index)
+{
+    ofnode node = ofnode_null();
+    struct ofnode_phandle_args out_args;
+
+    if (ofnode_parse_phandle_with_args(handle, phandle_name, NULL, 0, index, &out_args) == 0)
+    {
+        node = out_args.node;
+    }
+    return node;
+}
+
+static int bca_led_ctrl_probe(struct udevice *dev)
+{
+    unsigned int val = 0;
+	int ret;
+    int i;
+    bool serial_msb_first = 0;
+    bool serial_data_polarity_low = 0;
+    uint32_t reg_val;
+    volatile uint32_t *led_bright;
+    ofnode serial_pinctrl;
+
+    char *reg_names[LED_MAX_REG] = {"glbl_ctrl", "hw_en", "ser_shift", "flash_rate", "brightness",
+                                    "power_led_cfg", "power_lut", "hw_polarity", "sw_data", "sw_polarity",
+                                    "par_polarity", "ser_polarity", "mask"}; 
+
+	bca_led = dev_get_priv(dev);
+
+    if(dev_read_u32u(dev, "nleds", &val))
+    {
+        printf("nleds property not present\n");
+        ret = -EINVAL;
+        goto error;
+    }
+
+    bca_led->max_supported_leds = (uint8_t)val;
+    printf("max supported leds %d[%d]\n", bca_led->max_supported_leds, val);
+
+    serial_pinctrl = of_parse_phandle(dev_ofnode(dev), "pinctrl-0", 0);
+
+    if (serial_pinctrl.of_offset != -1)
+    {
+
+        if (dev_read_u32u(dev, "serial-shifters-installed", &val)) 
+        {
+            printf("The serial-shifters-installed property not present while Serial LED controller interface is configured\n");
+            ret = -EINVAL;
+            goto error;
+        }
+
+        bca_led->serial_shifters_num = (uint8_t)val;
+
+        serial_msb_first = dev_read_bool(dev, "serial-order-msb-first");
+        serial_data_polarity_low =  dev_read_bool(dev, "serial-data-polarity-low");
+        printf("Serial LED interface found num shifters %d [%d] serial data polarity low %d\n",
+            bca_led->serial_shifters_num, val, serial_data_polarity_low);
+    }
+    else
+    {
+        printf(" Parallel LED interface found\n");
+    }
+
+    for (i = 0; i < LED_MAX_REG; i++)
+    {
+        bca_led->led_regs[i] = dev_remap_addr_name(dev, reg_names[i]);
+        if ((bca_led->led_regs[i] == NULL) && (i < LED_LAST_MANDATORY))
+        {
+            printf("Failed to find %s resource\n", reg_names[i]);
+            ret = -EINVAL;
+            goto error;
+        }
+    }
+
+    if (!dev_read_u32u(dev, "hw-polarity-quirk", &val)) 
+    {
+        *(volatile uint32_t *)(bca_led->led_regs[LED_HW_POLARITY]) = (uint32_t)val;
+    }
+
+    if (!dev_read_u32(dev, "sw-polarity-quirk", &val)) 
+    {
+        *(volatile uint32_t *)(bca_led->led_regs[LED_SW_POLARITY]) = (uint32_t)val;
+    }
+
+    if (serial_data_polarity_low)
+        reg_val = 0x8;
+    else
+        reg_val = 0xa;
+
+    if (serial_msb_first)
+        reg_val |= 0x10;
+
+    *(volatile uint32_t *)(bca_led->led_regs[LED_CTRL]) = reg_val;
+
+    led_bright = (volatile uint32_t *)(bca_led->led_regs[LED_BRIGHTNESS]);
+    for (i = 0; i < bca_led->max_supported_leds/8; i++)
+            led_bright[i] = 0x88888888;
+
+    *(volatile uint32_t *)(bca_led->led_regs[LED_HW_EN]) = 0;
+    *(volatile uint32_t *)(bca_led->led_regs[LED_SERIAL_POLARITY]) = 0;
+    *(volatile uint32_t *)(bca_led->led_regs[LED_PARALLEL_POLARITY]) = 0;
+
+    printf("BCA LED Controller initialized\n");
+
+    return 0;
+
+error:
+    return ret;
+}
+
+static int bca_led_ctrl_bind(struct udevice *parent)
+{
+	ofnode node;
+
+	dev_for_each_subnode(node, parent) {
+		struct led_uc_plat *uc_plat;
+		struct udevice *dev;
+		const char *label;
+		int ret;
+
+		ret = device_bind_driver_to_node(parent, "bcm-bca-leds", ofnode_get_name(node),
+            node, &dev);
+		if (ret)
+        {
+            if (ret != -ENODEV)
+                printf("failed to bind node %s ret %d\n", ofnode_get_name(node), ret);
+            continue;
+        }
+
+		label = ofnode_read_string(node, "label");
+        if (label)
+        {
+            uc_plat = dev_get_uclass_platdata(dev);
+            uc_plat->label = label;
+        }
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(bcm_bca_led_ctrl_driver) = {
+    .name = "bcm-bca-led-ctrl",
+	.id = UCLASS_LED,
+	.probe = bca_led_ctrl_probe,
+    .bind = bca_led_ctrl_bind,
+    .of_match = bca_led_ctrl_of_match,
+	.priv_auto_alloc_size = sizeof(struct bcm_bca_led_ctrl),
+};
+
+int bca_led_setup_serial(unsigned int led_num, unsigned int polarity, unsigned int is_hw)
+{
+    uint32_t led_mask = 1 << led_num;
+    volatile uint32_t *polarity_reg;
+    uint32_t led_map = 0;
+    uint8_t missed_pins;
+    int i;
+
+    if(!bca_led)
+        return -ENODEV;
+
+    if (led_num > bca_led->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num,
+            bca_led->max_supported_leds);
+        return -EINVAL;
+    }
+
+    if (bca_led->serial_shifters_num == 0)
+    {
+        printf("Serial LED%d is requested, but no serial LED interface defined\n", led_num);
+        return -EINVAL;
+    }
+
+    polarity_reg = (volatile uint32_t *)bca_led->led_regs[LED_SERIAL_POLARITY];
+
+    bca_led->active_serial_led_count++;
+    if (bca_led->active_serial_led_count > (bca_led->serial_shifters_num * 8))
+    {
+        bca_led->active_serial_led_count--;
+        printf("The number of registered serial LEDs is bigger than supported by this configuration\n" );
+        return -EINVAL;
+    }
+
+    if (is_hw)
+        *(volatile uint32_t *)(bca_led->led_regs[LED_HW_EN]) |= led_mask;
+
+    if (polarity)
+        *polarity_reg |= led_mask;
+    else
+        *polarity_reg &= ~(led_mask);
+
+    bca_led->serial_led_map |= led_mask;
+
+    missed_pins = (bca_led->serial_shifters_num * 8) - bca_led->active_serial_led_count;
+
+    led_map = bca_led->serial_led_map;
+
+    for (i = 31; i>=0 && missed_pins; i--)
+    {
+        if (bca_led->serial_led_map & (1 << i))
+            break;
+        led_map |= (1 << i);
+        missed_pins--;
+    }
+
+    *(volatile uint32_t *)(bca_led->led_regs[LED_SERIAL_SHIFT_SEL]) = led_map; 
+
+    return 0;
+}
+
+int bca_led_setup_parallel(unsigned int led_num, int polarity, int is_hw)
+{
+    uint32_t led_mask = 1 << led_num;
+    volatile uint32_t *polarity_reg;
+   
+    if(!bca_led)
+        return -ENODEV;
+
+    if (led_num > bca_led->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num, bca_led->max_supported_leds);
+        return -EINVAL;
+    }
+
+    polarity_reg = (volatile uint32_t *)bca_led->led_regs[LED_PARALLEL_POLARITY];
+
+    if (is_hw)
+        *(volatile uint32_t *)(bca_led->led_regs[LED_HW_EN]) |= led_mask;
+
+    if (polarity)
+        *polarity_reg |= led_mask;
+    else
+        *polarity_reg &= ~(led_mask);
+
+    return 0;
+}
+
+int bca_led_get_value(unsigned int led_num)
+{
+    uint32_t led_mask = 1 << led_num;
+    
+    if(!bca_led)
+        return -ENODEV;
+
+    if (led_num > bca_led->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num, bca_led->max_supported_leds);
+        return -EINVAL;
+    }
+
+    return *(volatile uint32_t *)(bca_led->led_regs[LED_SW_DATA]) & led_mask;
+}
+
+int bca_led_set_value(unsigned int led_num, unsigned int value)
+{
+    uint32_t led_mask = 1 << led_num;
+    
+    if(!bca_led)
+        return -ENODEV;
+
+    if (led_num > bca_led->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num, bca_led->max_supported_leds);
+        return -EINVAL;
+    }
+    if (value)
+        *(volatile uint32_t *)(bca_led->led_regs[LED_SW_DATA]) |= led_mask;
+    else
+        *(volatile uint32_t *)(bca_led->led_regs[LED_SW_DATA]) &= ~led_mask;
+    
+    return 0;
+}
+
+int bca_led_set_brightness(unsigned int led_num, unsigned int value)
+{
+    uint8_t reg_idx = (led_num >> 3);
+    uint32_t led_mask = 0xf << ((led_num & 0x7) << 2);
+    uint32_t mapped_val = value << ((led_num & 0x7) << 2);
+    volatile uint32_t *led_bright;
+    
+    if(!bca_led)
+        return -ENODEV;
+
+    if (led_num > bca_led->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num, bca_led->max_supported_leds);
+        return -EINVAL;
+    }
+
+    led_bright = (volatile uint32_t *)(bca_led->led_regs[LED_BRIGHTNESS]);
+
+    led_bright[reg_idx] &= ~led_mask;
+    led_bright[reg_idx] |= mapped_val;
+    return 0;
+}
+
+int bca_led_set_flash_rate(unsigned int led_num, unsigned int value)
+{
+    uint8_t reg_idx = (led_num >> 3);
+    uint32_t led_mask = 0xf << ((led_num & 0x7) << 2);
+    uint32_t mapped_val = value << ((led_num & 0x7) << 2);
+    volatile uint32_t *led_flash;
+
+    if(!bca_led)
+        return -ENODEV;
+
+    if (led_num > bca_led->max_supported_leds)
+    {
+        printf("requested LED %d is out of supported range(%d)\n", led_num, bca_led->max_supported_leds);
+        return -EINVAL;
+    }
+
+    led_flash = (volatile uint32_t *)(bca_led->led_regs[LED_FLASH_RATE]);
+
+    led_flash[reg_idx] &= ~led_mask;
+    led_flash[reg_idx] |= mapped_val;
+    return 0;
+}
+
+void bca_led_probe(void)
+{
+    struct udevice *dev;
+
+    for (uclass_first_device_check(UCLASS_LED, &dev); dev; uclass_next_device_check(&dev));
+}
diff --git a/drivers/led/bcm_bca_leds.c b/drivers/led/bcm_bca_leds.c
new file mode 100644
index 0000000000..ae43d3e336
--- /dev/null
+++ b/drivers/led/bcm_bca_leds.c
@@ -0,0 +1,753 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+ *  
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/ofnode.h>
+#include <led.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#include "bcm_bca_leds.h"
+struct bca_led {
+    struct led_ops ops;
+    uint32_t pin;
+    struct udevice *dev;
+	struct gpio_desc desc;
+    struct list_head node;
+};
+
+extern int bca_led_set_value(unsigned int led_num, unsigned int value);
+extern int bca_led_get_value(unsigned int led_num);
+extern int bca_led_set_brightness(unsigned int led_num, unsigned int value);
+extern int bca_led_set_flash_rate(unsigned int led_num, unsigned int value);
+extern int bca_led_setup_serial(unsigned int led_num, unsigned int polarity, unsigned int is_hw);
+extern int bca_led_setup_parallel(unsigned int led_num, unsigned int polarity, unsigned int is_hw);
+/*CLED controller APIs*/
+extern int bca_cled_set_value(unsigned int led_num, unsigned int value);
+extern int bca_cled_get_value(unsigned int led_num);
+extern int bca_cled_set_brightness(unsigned int led_num, unsigned int value);
+extern int bca_cled_set_flash_rate(unsigned int led_num, unsigned int value);
+extern int bca_cled_setup_serial(unsigned int led_num, unsigned int polarity, unsigned int is_hw,
+    struct udevice *dev, bool is_crossbar);
+extern int bca_cled_setup_parallel(unsigned int led_num, unsigned int polarity, unsigned int is_hw,
+    struct udevice *dev, bool is_crossbar);
+
+LIST_HEAD(leds_list);
+
+struct udevice* find_led_device_by_pin(uint32_t pin)
+{
+    struct  bca_led *led;
+    list_for_each_entry(led, &leds_list, node)
+    {
+        if (pin == led->pin)
+            return led->dev;
+    }
+    return NULL;
+}
+
+static int bca_gpio_led_set(struct udevice *dev, enum led_state_t value)
+{
+    struct bca_led *led = dev_get_priv(dev);
+
+    if (value == LEDST_OFF || value == LEDST_ON)
+        dm_gpio_set_value(&led->desc, value == LEDST_OFF ? 0 : 1);
+    else
+    {
+        int state;
+        state  = dm_gpio_get_value(&led->desc);
+        dm_gpio_set_value(&led->desc, state == 0 ? 1 : 0);
+    }
+    return 0;
+}
+
+static enum led_state_t bca_gpio_led_get(struct udevice *dev)
+{
+    struct bca_led *led = dev_get_priv(dev);
+
+    int state;
+    state  = dm_gpio_get_value(&led->desc);
+    return state == 0 ? LEDST_OFF : LEDST_ON;
+}
+
+static int gpio_led_parse(struct udevice *dev, struct bca_led *led)
+{
+    uint32_t gpio;
+    int ret;
+    unsigned long gflags = GPIOD_IS_OUT;
+    struct led_uc_plat *uc_plat;
+    char name[5];
+
+    if (!dev_read_bool(dev, "software_led"))
+    {
+        printf("Hardware LEDs over GPIO inerface is not supported\n");
+        return -EINVAL;
+    }
+
+    if (dev_read_u32u(dev, "pin", &gpio))
+    {
+        printf("GPIO pin is not specified\n");
+        return -EINVAL;
+    }
+
+    if (dev_read_bool(dev, "active_low"))
+        gflags |= GPIOD_ACTIVE_LOW;
+    uc_plat = dev_get_uclass_platdata(dev);
+    uc_plat->label = dev_read_prop(dev, "label", NULL) ? : dev_read_name(dev);
+
+    snprintf(name, 5, "%d", gpio);
+    ret = dm_gpio_lookup_name(name, &led->desc);
+    if (ret)
+    {
+        printf("Failed to find GPIO %d(%s)\n", gpio, name);
+        return ret;
+    }
+
+    ret = dm_gpio_request(&led->desc, uc_plat->label); 
+    if (ret)
+    {
+        printf("Failed to request GPIO %d\n", gpio);
+        return ret;
+    }
+
+    led->pin = gpio;
+
+    dm_gpio_set_dir_flags(&led->desc, gflags);
+
+    led->ops.set_state = bca_gpio_led_set;
+    led->ops.get_state = bca_gpio_led_get;
+#ifdef CONFIG_LED_BLINK    
+    led->ops.set_period = NULL;
+#endif
+    return 0;
+}
+
+static enum led_state_t common_bca_led_get(struct udevice *dev, int is_cled)
+{
+    struct bca_led *led = dev_get_priv(dev);
+    int curr_value; 
+    if (is_cled)
+        curr_value = bca_cled_get_value(led->pin);
+    else
+        curr_value = bca_led_get_value(led->pin);
+    return curr_value == 0 ? LEDST_OFF : LEDST_ON; 
+}
+
+static enum led_state_t bca_cled_get(struct udevice *dev)
+{
+    return common_bca_led_get(dev, 1);
+}
+
+static enum led_state_t bca_led_get(struct udevice *dev)
+{
+    return common_bca_led_get(dev, 0);
+}
+
+static int common_bca_led_set(struct udevice *dev, enum led_state_t value, int is_cled)
+{
+    int (* led_set_value)(unsigned int led_num, unsigned int value) = NULL;
+    int (* led_set_flash_rate)(unsigned int led_num, unsigned int value) = NULL;
+    int (* led_get_value)(unsigned int led_num) = NULL;
+
+    struct bca_led *led = dev_get_priv(dev);
+    int curr_value; 
+
+    if (is_cled)
+    {
+        led_set_value = bca_cled_set_value;
+        led_get_value = bca_cled_get_value;
+        led_set_flash_rate = bca_cled_set_flash_rate;
+    }
+    else
+    {
+        led_set_value = bca_led_set_value;
+        led_get_value = bca_led_get_value;
+        led_set_flash_rate = bca_led_set_flash_rate;
+    }
+
+    switch (value)
+    {
+    case LEDST_OFF:
+        led_set_value(led->pin, 0);
+        led_set_flash_rate(led->pin, 0);
+        break;
+#ifdef CONFIG_LED_BLINK
+    case LEDST_BLINK:
+#endif
+    case LEDST_ON:
+        led_set_value(led->pin, 1);
+        break;
+    case LEDST_TOGGLE:
+        curr_value = led_get_value(led->pin);
+        if (curr_value > 0)
+            led_set_value(led->pin, 0);
+        else if (curr_value == 0)
+            led_set_value(led->pin, 1);
+
+    default:
+        break;
+    }
+    return 0;
+}
+
+static int bca_cled_set(struct udevice *dev, enum led_state_t value)
+{
+    return common_bca_led_set(dev, value, 1);
+}
+
+static int bca_led_set(struct udevice *dev, enum led_state_t value)
+{
+    return common_bca_led_set(dev, value, 0);
+}
+
+static unsigned int convert_ms_to_hz(unsigned int ms)
+{
+    if (ms <= 60)
+        return 1;
+    if (ms <= 120)
+        return 2;
+    if (ms <= 240)
+        return 3;
+    if (ms <= 480)
+        return 4;
+    if (ms <= 960)
+        return 5;
+    if (ms <= 1920)
+        return 6;
+    return 7;
+}
+
+#ifdef CONFIG_LED_BLINK
+static int common_bca_blink_set(struct udevice *dev, int delay_on, int is_cled)
+{
+    struct bca_led *led = dev_get_priv(dev);
+    unsigned int delay;
+
+    delay = convert_ms_to_hz(delay_on);
+
+    if (is_cled)
+        bca_cled_set_flash_rate(led->pin, delay);
+    else
+        bca_led_set_flash_rate(led->pin, delay);
+
+    return 0;
+}
+
+static int bca_blink_set(struct udevice *dev, int delay_on)
+{
+    return common_bca_blink_set(dev, delay_on, 0);
+}
+
+static int bca_c_blink_set(struct udevice *dev, int delay_on)
+{
+    return common_bca_blink_set(dev, delay_on, 1);
+}
+#endif
+
+static int serial_led_parse(struct udevice *dev, struct bca_led *led)
+{
+    bool active_high;
+    bool is_hw;
+    uint32_t led_num;
+    uint32_t init_brightness = 255;
+    uint32_t init_flash_rate = 0;
+    uint32_t default_state;
+    struct led_uc_plat *uc_plat;
+    int ret;
+
+    if (dev_read_u32u(dev, "bit", &led_num))
+    {
+        printf("bit property is not specified\n");
+        return -EINVAL;
+    }
+
+    is_hw = dev_read_bool(dev, "hardware_led");
+    active_high = dev_read_bool(dev, "active_high");
+
+    ret = bca_led_setup_serial(led_num, active_high, is_hw);
+    if (ret)
+    {
+        if (ret != -ENODEV)
+            printf("Failed to setup serial led %d\n", led_num);
+        return ret;
+    }
+
+    ret = dev_read_u32u(dev, "brightness", &init_brightness);
+    ret = dev_read_u32u(dev, "flash_rate", &init_flash_rate);
+
+    bca_led_set_brightness(led_num, init_brightness == 0 ? 0 : init_brightness < 31 ?
+        1 : init_brightness/31);
+    bca_led_set_flash_rate(led_num, init_flash_rate & 0x7);
+
+    ret = dev_read_u32u(dev, "default_state", &default_state);
+    if (!ret)
+    {
+        bca_led_set_value(led_num, default_state);
+    }
+
+    led->pin = led_num;
+    if (is_hw)
+    {
+        led->ops.set_state = NULL;
+        led->ops.get_state = NULL;
+#ifdef CONFIG_LED_BLINK
+        led->ops.set_period = NULL;
+#endif
+    }
+    else
+    {
+        led->ops.set_state = bca_led_set;
+        led->ops.get_state = bca_led_get;
+#ifdef CONFIG_LED_BLINK
+        led->ops.set_period = bca_blink_set;
+#endif
+    }
+    uc_plat = dev_get_uclass_platdata(dev);
+    uc_plat->label = dev_read_prop(dev, "label", NULL) ? : dev_read_name(dev);
+
+    return 0;
+}
+
+static int serial_cled_parse(struct udevice *dev, struct bca_led *led)
+{
+    bool active_high;
+    bool is_hw;
+    uint32_t led_num;
+    uint32_t init_brightness = 255;
+    uint32_t init_flash_rate = 0;
+    uint32_t default_state;
+    struct led_uc_plat *uc_plat;
+    int ret;
+    bool is_crossbar;
+
+    if (dev_read_u32u(dev, "bit", &led_num))
+    {
+        printf("bit property is not specified\n");
+        return -EINVAL;
+    }
+
+    is_hw = dev_read_bool(dev, "hardware_led");
+    active_high = dev_read_bool(dev, "active_high");
+    is_crossbar = dev_read_bool(dev, "crossbar");
+
+    ret = bca_cled_setup_serial(led_num, active_high, is_hw, dev, is_crossbar);
+
+    if (ret)
+    {
+        if (ret != -ENODEV)
+            printf("Failed to setup serial led %d\n", led_num);
+        return ret;
+    }
+
+    ret = dev_read_u32u(dev, "brightness", &init_brightness);
+    ret = dev_read_u32u(dev, "flash_rate", &init_flash_rate);
+
+    bca_cled_set_brightness(led_num, init_brightness);
+    bca_cled_set_flash_rate(led_num, init_flash_rate & 0x7);
+
+    ret = dev_read_u32u(dev, "default_state", &default_state);
+    if (!ret)
+    {
+        bca_cled_set_value(led_num, default_state);
+    }
+
+    led->pin = led_num;
+    if (is_hw)
+    {
+        led->ops.set_state = NULL;
+        led->ops.get_state = NULL;
+#ifdef CONFIG_LED_BLINK
+        led->ops.set_period = NULL;
+#endif
+    }
+    else
+    {
+        led->ops.set_state = bca_cled_set;
+        led->ops.get_state = bca_cled_get;
+#ifdef CONFIG_LED_BLINK
+        led->ops.set_period = bca_c_blink_set;
+#endif
+    }
+    uc_plat = dev_get_uclass_platdata(dev);
+    uc_plat->label = dev_read_prop(dev, "label", NULL) ? : dev_read_name(dev);
+
+    return 0;
+}
+
+static int parallel_led_parse(struct udevice *dev, struct bca_led *led)
+{
+    bool active_high;
+    bool is_hw;
+    uint32_t led_num;
+    uint32_t init_brightness = 255;
+    uint32_t init_flash_rate = 0;
+    uint32_t default_state;
+    struct led_uc_plat *uc_plat;
+    int ret;
+
+    if (dev_read_u32u(dev, "bit", &led_num))
+    {
+        printf("bit property is not specified\n");
+        return -EINVAL;
+    }
+
+    is_hw = dev_read_bool(dev, "hardware_led");
+    active_high = dev_read_bool(dev, "active_high");
+
+    ret = bca_led_setup_parallel(led_num, active_high, is_hw);
+
+    if (ret)
+    {
+        if (ret != -ENODEV)
+            printf("Failed to setup parallel led %d\n", led_num);
+        return ret;
+    }
+
+    ret = dev_read_u32u(dev, "brightness", &init_brightness);
+    ret = dev_read_u32u(dev, "flash_rate", &init_flash_rate);
+
+    bca_led_set_brightness(led_num, init_brightness == 0 ? 0 : init_brightness < 31 ?
+        1 : init_brightness/31);
+    bca_led_set_flash_rate(led_num, init_flash_rate & 0x7);
+
+    ret = dev_read_u32u(dev, "default_state", &default_state);
+    if (!ret)
+    {
+        bca_led_set_value(led_num, default_state);
+    }
+
+    led->pin = led_num;
+    if (is_hw)
+    {
+        led->ops.set_state = NULL;
+        led->ops.get_state = NULL;
+#ifdef CONFIG_LED_BLINK
+        led->ops.set_period = NULL;
+#endif
+    }
+    else
+    {
+        led->ops.set_state = bca_led_set;
+        led->ops.get_state = bca_led_get;
+#ifdef CONFIG_LED_BLINK
+        led->ops.set_period = bca_blink_set;
+#endif
+    }
+    uc_plat = dev_get_uclass_platdata(dev);
+    uc_plat->label = dev_read_prop(dev, "label", NULL) ? : dev_read_name(dev);
+
+    return 0;
+}
+
+static int parallel_cled_parse(struct udevice *dev, struct bca_led *led)
+{
+    bool active_high;
+    bool is_hw;
+    uint32_t led_num;
+    uint32_t init_brightness = 255;
+    uint32_t init_flash_rate = 0;
+    uint32_t default_state;
+    struct led_uc_plat *uc_plat;
+    int ret;
+    bool is_crossbar;
+
+    if (dev_read_u32u(dev, "bit", &led_num))
+    {
+        printf("bit property is not specified\n");
+        return -EINVAL;
+    }
+
+    is_hw = dev_read_bool(dev, "hardware_led");
+    active_high = dev_read_bool(dev, "active_high");
+    is_crossbar = dev_read_bool(dev, "crossbar");
+
+    ret = bca_cled_setup_parallel(led_num, active_high, is_hw, dev, is_crossbar);
+
+    if (ret)
+    {
+        if (ret != -ENODEV)
+            printf("Failed to setup parallel led %d\n", led_num);
+        return ret;
+    }
+
+    ret = dev_read_u32u(dev, "brightness", &init_brightness);
+    ret = dev_read_u32u(dev, "flash_rate", &init_flash_rate);
+
+    bca_cled_set_brightness(led_num, init_brightness);
+    bca_cled_set_flash_rate(led_num, init_flash_rate & 0x7);
+
+    ret = dev_read_u32u(dev, "default_state", &default_state);
+    if (!ret)
+    {
+        bca_cled_set_value(led_num, default_state);
+    }
+
+    led->pin = led_num;
+    if (is_hw)
+    {
+        led->ops.set_state = NULL;
+        led->ops.get_state = NULL;
+#ifdef CONFIG_LED_BLINK
+        led->ops.set_period = NULL;
+#endif
+    }
+    else
+    {
+        led->ops.set_state = bca_cled_set;
+        led->ops.get_state = bca_cled_get;
+#ifdef CONFIG_LED_BLINK
+        led->ops.set_period = bca_c_blink_set;
+#endif
+    }
+    uc_plat = dev_get_uclass_platdata(dev);
+    uc_plat->label = dev_read_prop(dev, "label", NULL) ? : dev_read_name(dev);
+
+    return 0;
+}
+
+static enum led_state_t bcm_led_get_state(struct udevice *dev)
+{
+    struct bca_led *led;
+    led = dev_get_priv(dev);
+
+    if (led->ops.get_state)
+        return led->ops.get_state(dev);
+    else
+        return LEDST_OFF;
+}
+
+static int bcm_led_set_state(struct udevice *dev, enum led_state_t state)
+{
+    struct bca_led *led;
+    led = dev_get_priv(dev);
+
+    if (led->ops.set_state)
+        return led->ops.set_state(dev, state);
+    else
+        return -EINVAL;
+};
+
+#ifdef CONFIG_LED_BLINK
+static int bcm_led_set_period(struct udevice *dev, int period_ms)
+{
+    struct bca_led *led;
+    led = dev_get_priv(dev);
+    if (led->ops.set_period)
+        return led->ops.set_period(dev, period_ms);
+    else
+        return -EINVAL;
+}
+#endif
+
+static const struct led_ops bcm_bca_led_ops = {
+	.get_state = bcm_led_get_state,
+	.set_state = bcm_led_set_state,
+#ifdef CONFIG_LED_BLINK
+	.set_period = bcm_led_set_period,
+#endif
+};
+
+static const struct udevice_id bca_leds_of_match[] = {
+    { .compatible = "brcm,serial-led", .data = (long unsigned int )serial_led_parse, },
+    { .compatible = "brcm,serial-cled", .data = (long unsigned int )serial_cled_parse, },
+	{ .compatible = "brcm,gpio-led", .data = (long unsigned int)gpio_led_parse, },
+    { .compatible = "brcm,parallel-led", .data = (long unsigned int)parallel_led_parse, },
+    { .compatible = "brcm,parallel-cled", .data = (long unsigned int)parallel_cled_parse, },
+	{ },
+};
+
+static int driver_check_compatible(const struct udevice_id *of_match,
+				   const struct udevice_id **of_idp,
+				   const char *compat)
+{
+	if (!of_match)
+		return -ENOENT;
+
+	while (of_match->compatible) {
+		if (!strcmp(of_match->compatible, compat)) {
+			*of_idp = of_match;
+			return 0;
+		}
+		of_match++;
+	}
+
+	return -ENOENT;
+}
+
+static int bca_leds_bind(struct udevice *dev)
+{
+    const char *compat, *status;
+    const struct udevice_id *id;
+    int ret;
+
+    compat = dev_read_prop(dev, "compatible", NULL);
+    ret = driver_check_compatible(bca_leds_of_match, &id, compat);
+    if (!ret)
+    {
+        status = dev_read_prop(dev, "status", NULL);
+        if (!strcmp("ok", status) || !strcmp("okay", status))
+            dev->driver_data = id->data;
+        else
+            ret = -ENODEV;
+    }
+
+    return ret;
+}
+
+static int bca_leds_probe(struct udevice *dev)
+{
+    struct bca_led *led;
+    int ret = 0;
+    int(*parse_func)(struct udevice *dev, struct bca_led *led);
+    ulong data = 0;
+
+    data = dev_get_driver_data(dev);
+    if (!data)
+        return -ENODEV;
+
+    led = dev_get_priv(dev);
+
+    parse_func = (int(*)(struct udevice *, struct bca_led *))data;
+    ret = parse_func(dev, led);
+    if (ret)
+        goto error; 
+    
+    if (led->ops.set_state) /* Software leds will be registered in Linux framework */
+    {
+        list_add_tail(&led->node, &leds_list);
+        printf("SW led %d registered\n", led->pin);
+    }
+    else
+    {
+        printf("HW led %d registered\n", led->pin);
+    }
+
+    return 0;
+error:
+    return ret;
+}
+
+U_BOOT_DRIVER(bcm_bca_leds_driver) = {
+    .name = "bcm-bca-leds",
+	.id = UCLASS_LED,
+    .of_match = bca_leds_of_match,
+	.probe = bca_leds_probe,
+    .bind = bca_leds_bind,
+	.priv_auto_alloc_size = sizeof(struct bca_led),
+    .ops = &bcm_bca_led_ops,
+};
+
+#define led_err(fmt, ...) \
+    printf("%s:L%d "fmt, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+#define led_info(fmt, ...) \
+    printf("%s:L%d "fmt, __FUNCTION__, __LINE__, ##__VA_ARGS__)
+
+static const ofnode of_parse_phandle(const ofnode handle, const char *phandle_name, int index)
+{
+    ofnode node = ofnode_null();
+    struct ofnode_phandle_args out_args;
+
+    if (ofnode_parse_phandle_with_args(handle, phandle_name, NULL, 0, index, &out_args) == 0)
+    {
+        node = out_args.node;
+    }
+    return node;
+}
+
+struct udevice * bca_led_request_sw_led(ofnode dn, const char *consumer_led_name)
+{
+    ofnode led_node;
+    uint32_t led;
+
+    led_node = of_parse_phandle(dn, consumer_led_name, 0);
+    if (led_node.of_offset == -1)
+    {
+        led_info("%s led not found\n", consumer_led_name);
+        return NULL;
+    }
+
+    if (ofnode_read_u32(led_node, "bit", &led))
+    {
+        if (ofnode_read_u32(led_node, "pin", &led))
+        {
+            led_err("LED structure referenced by %s is in wrong format\n", consumer_led_name);
+            return NULL;
+        }
+    }
+
+    return find_led_device_by_pin(led); 
+}
+
+void bca_led_request_network_leds(ofnode dn, bca_leds_info_t *led_info)
+{
+    int i;
+    ofnode led_node;
+    uint32_t port, led;
+    uint32_t link;
+    uint32_t activity;
+    int ret;
+
+    led_info->port_id = 0xff;
+    for(i = 0; i < 4; i++)
+    {
+        led_info->link[i] = 0;
+        led_info->activity[i] = 0;
+    }
+
+    for(i = 0; i < 4; i++)
+    {
+        led_node = of_parse_phandle(dn, "network-leds", i);
+        if (led_node.of_offset == -1)
+            return;
+
+        if (!ofnode_read_bool(led_node, "hardware_led"))
+        {
+            led_err("Only Hardware LEDs could be used as Network Leds node\n");
+            continue;
+        }
+
+        ret = ofnode_read_u32(led_node, "port", &port);
+        if (ret)
+        {
+            led_err("LED structure referenced by is in wrong format\n");
+            continue;
+        }
+        
+        if (led_info->port_id != 0xff && led_info->port_id != port)
+        {
+            led_err("HW LED assigned to port %d referenced from port %d\n", port, led_info->port_id);
+            continue;
+        }
+
+        ret = ofnode_read_u32(led_node, "led", &led);
+        if (ret)
+        {
+            led_err("LED structure referenced is in wrong format\n");
+            continue;
+        }
+
+        link = 0;
+        activity = 0;
+        ofnode_read_u32(led_node, "link", &link);
+        ofnode_read_u32(led_node, "activity", &activity);
+
+        led_info("network led %d for port %d link 0x%x activity 0x%x\n", led, port, link, activity);
+
+        if (link == 0 && activity == 0)
+        {
+            led_err("At least one of the activity/link LED functionality must be specified for port %d led %d\n",
+                port, led);
+            continue;
+        }
+        led_info->port_id = port;
+        led_info->link[led] = link;
+        led_info->activity[led] = activity;
+    }
+}
+
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c23299ea96..9a049564d4 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -44,6 +44,17 @@ config SPL_DM_MMC
 	  appear as block devices in U-Boot and can support filesystems such
 	  as EXT4 and FAT.
 
+config TPL_DM_MMC
+	bool "Enable MMC controllers using Driver Model in TPL"
+	depends on SPL_DM && DM_MMC
+	default y
+	help
+	  This enables the MultiMediaCard (MMC) uclass which supports MMC and
+	  Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
+	  and non-removable (e.g. eMMC chip) devices are supported. These
+	  appear as block devices in U-Boot and can support filesystems such
+	  as EXT4 and FAT.
+
 if MMC
 
 config ARM_PL180_MMCI
@@ -441,6 +452,17 @@ config MMC_SDHCI_BCMSTB
 
 	  If unsure, say N.
 
+config MMC_SDHCI_BCMBCA
+	tristate "SDHCI support for the BCMBCA SD/MMC Controller"
+	depends on MMC_SDHCI
+	help
+	  This selects the Broadcom set-top box SD/MMC controller.
+
+	  If you have a BCMBCA platform with SD or MMC devices,
+	  say Y here.
+
+	  If unsure, say N.
+
 config MMC_SDHCI_CADENCE
 	bool "SDHCI support for the Cadence SD/SDIO/eMMC controller"
 	depends on BLK && DM_MMC
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 0076fc393b..f02c2639d0 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -17,6 +17,10 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
 endif
 
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_MMC_SDHCI_BCMBCA) += bcmbca_sdhci_spl.o
+endif
+
 obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
 obj-$(CONFIG_MMC_DAVINCI)		+= davinci_mmc.o
 obj-$(CONFIG_MMC_DW)			+= dw_mmc.o
@@ -48,6 +52,7 @@ obj-$(CONFIG_MMC_SDHCI)			+= sdhci.o
 obj-$(CONFIG_MMC_SDHCI_ATMEL)		+= atmel_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= bcm2835_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_BCMSTB)		+= bcmstb_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_BCMBCA)		+= bcmbca_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_CADENCE)		+= sdhci-cadence.o
 obj-$(CONFIG_MMC_SDHCI_K3_ARASAN)	+= k3_arsan_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_KONA)		+= kona_sdhci.o
diff --git a/drivers/mmc/bcmbca_sdhci.c b/drivers/mmc/bcmbca_sdhci.c
new file mode 100644
index 0000000000..b3fe6ab8ec
--- /dev/null
+++ b/drivers/mmc/bcmbca_sdhci.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018  Cisco Systems, Inc.
+ * (C) Copyright 2019  Synamedia
+ * (C) Copyright 2019  Broadcom Ltd
+ *
+ * Author: Farhan Ali <farhan.ali@broadcom.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+/* 400KHz is max freq for card ID etc. Use that as min */
+#define MIN_FREQ 400000
+#define BCMBCA_MMC_BOOT_MAIN_CTL	0
+#define BCMBCA_MMC_BOOT_STATUS		0x4
+#define BCMBCA_MMC_BOOT_MODE_MASK	1
+
+struct sdhci_bcmbca_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
+static int sdhci_bcmbca_bind(struct udevice *dev)
+{
+	struct sdhci_bcmbca_plat *plat = dev_get_platdata(dev);
+
+	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static int sdhci_bcmbca_probe(struct udevice *dev)
+{
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct sdhci_bcmbca_plat *plat = dev_get_platdata(dev);
+	struct sdhci_host *host = dev_get_priv(dev);
+	struct resource res;
+	void * boot_regs;
+	int ret;
+
+	host->name = dev->name;
+
+	/* Get sdhci controller base address */
+	ret = dev_read_resource_byname(dev, "sdhci-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs sdhci-base address(ret = %d)!\n", ret);
+		return ret;
+	}
+							
+	host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
+	host->ioaddr = devm_ioremap(dev, res.start, resource_size(&res));
+	if (IS_ERR(host->ioaddr))
+		return PTR_ERR(host->ioaddr);
+
+	/* Get sdhci boot controller base address */
+	ret = dev_read_resource_byname(dev, "sdhci-boot", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs sdhci-boot address(ret = %d)!\n", ret);
+		return ret;
+	}
+
+	boot_regs = devm_ioremap(dev, res.start, resource_size(&res));
+	if (IS_ERR(boot_regs))
+		return PTR_ERR(boot_regs);
+
+	/* Get us out of boot mode */
+	while(readl(boot_regs + BCMBCA_MMC_BOOT_STATUS) & BCMBCA_MMC_BOOT_MODE_MASK)
+	{
+		writel(0, boot_regs + BCMBCA_MMC_BOOT_MAIN_CTL);
+	}
+
+	ret = mmc_of_parse(dev, &plat->cfg);
+	if (ret)
+		return ret;
+
+	/* Use default max frequency from caps register */
+	ret = sdhci_setup_cfg(&plat->cfg, host,
+			      0,
+			      MIN_FREQ);
+	if (ret)
+		return ret;
+
+	upriv->mmc = &plat->mmc;
+	host->mmc = &plat->mmc;
+	host->mmc->priv = host;
+
+	return sdhci_probe(dev);
+}
+
+static const struct udevice_id sdhci_bcmbca_match[] = {
+	{ .compatible = "brcm,bcm63xx-sdhci" },
+	{ .compatible = "brcm,sdhci-brcmbca" },
+	{ }
+};
+
+U_BOOT_DRIVER(sdhci_bcmbca) = {
+	.name = "sdhci-bcmbca",
+	.id = UCLASS_MMC,
+	.of_match = sdhci_bcmbca_match,
+	.ops = &sdhci_ops,
+	.bind = sdhci_bcmbca_bind,
+	.probe = sdhci_bcmbca_probe,
+	.priv_auto_alloc_size = sizeof(struct sdhci_host),
+	.platdata_auto_alloc_size = sizeof(struct sdhci_bcmbca_plat),
+};
diff --git a/drivers/mmc/bcmbca_sdhci_spl.c b/drivers/mmc/bcmbca_sdhci_spl.c
new file mode 100644
index 0000000000..191b4afa61
--- /dev/null
+++ b/drivers/mmc/bcmbca_sdhci_spl.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019  Broadcom Ltd
+ *
+ * Author: Farhan Ali <farhan.ali@broadcom.com>
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <malloc.h>
+
+char temp_buff[512];
+
+/* Copy over data from a specified offset */
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst)
+{
+	uint blk_start, blk_cnt, err;
+	char * datap = vdst;
+	int i=0;
+	uint init_offset = 0;
+	uint orig_size = size;
+
+	struct mmc *mmc = find_mmc_device(0);
+	struct blk_desc * block_dev = mmc_get_blk_desc(mmc);
+	if (!mmc) {
+		puts("spl: mmc device not found!!\n");
+		hang();
+	}
+
+	if (mmc_init(mmc)) {
+		puts("MMC init failed\n");
+		return;
+	}
+	
+	if( mmc->read_bl_len > sizeof(temp_buff) )
+	{
+		puts("MMC temp buffer is smaller than read_bl_len\n");
+		hang();
+	}
+
+	blk_start = offs/mmc->read_bl_len;
+	init_offset = offs % mmc->read_bl_len;
+	blk_cnt = (init_offset+size)/mmc->read_bl_len + ((init_offset+size)%mmc->read_bl_len?1:0);
+
+	debug("Addr:0x%08x Len:0x%08x Startb:0x%08x Numb:0x%08x Endb:0x%08x\n"
+		, offs, size, blk_start, blk_cnt			
+		,((offs+size)/mmc->read_bl_len + ((offs+size)%mmc->read_bl_len?1:0)));
+
+	for( i=0; i<blk_cnt; i++ )
+	{
+		err = blk_dread(block_dev, blk_start, 1,
+				temp_buff);
+		if (err != 1) 
+		{
+			puts("spl: mmc read failed!!\n");
+			hang();
+		} 
+		else
+		{
+			/* All data in current block, copy it over */
+			if( (init_offset + size) < mmc->read_bl_len )
+			{
+				memcpy(datap, temp_buff+init_offset, size);
+				size = 0;
+				init_offset = 0;
+			}
+			else
+			{
+				/* Data spans blocks, copy all data in this block */
+				memcpy(datap, temp_buff+init_offset, mmc->read_bl_len-init_offset);
+				size -= mmc->read_bl_len-init_offset;
+				datap += mmc->read_bl_len-init_offset;
+				init_offset = 0;
+			}
+
+			blk_start++;
+		}
+	}
+}
+
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
index 0b793695cc..e9ed095265 100644
--- a/drivers/mtd/nand/core.c
+++ b/drivers/mtd/nand/core.c
@@ -161,7 +161,11 @@ int nanddev_mtd_erase(struct mtd_info *mtd, struct erase_info *einfo)
 	nanddev_offs_to_pos(nand, einfo->addr, &pos);
 	nanddev_offs_to_pos(nand, einfo->addr + einfo->len - 1, &last);
 	while (nanddev_pos_cmp(&pos, &last) <= 0) {
-		ret = nanddev_erase(nand, &pos);
+		if (einfo->scrub)
+			ret = nand->ops->erase(nand, &pos);
+		else
+			ret = nanddev_erase(nand, &pos);
+
 		if (ret) {
 			einfo->fail_addr = nanddev_pos_to_offs(nand, &pos);
 
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index f86035bcce..cea6212388 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -73,18 +73,6 @@ config NAND_BRCMNAND_6838
        help
          Enable support for broadcom nand driver on bcm6838.
 
-config NAND_BRCMNAND_6858
-       bool "Support Broadcom NAND controller on bcm6858"
-       depends on NAND_BRCMNAND && ARCH_BCM6858
-       help
-         Enable support for broadcom nand driver on bcm6858.
-
-config NAND_BRCMNAND_63158
-       bool "Support Broadcom NAND controller on bcm63158"
-       depends on NAND_BRCMNAND && ARCH_BCM63158
-       help
-         Enable support for broadcom nand driver on bcm63158.
-
 config NAND_DAVINCI
 	bool "Support TI Davinci NAND controller"
 	help
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 9337f6482e..2376207bab 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -75,5 +75,6 @@ obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
 obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
 obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o
+obj-$(CONFIG_NAND_BRCMNAND) += brcmnand/
 
 endif # drivers
diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile
index a2363cc80e..17550e171c 100644
--- a/drivers/mtd/nand/raw/brcmnand/Makefile
+++ b/drivers/mtd/nand/raw/brcmnand/Makefile
@@ -1,7 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_NAND_BRCMNAND) += brcmnand_spl.o
+else
 obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o
 obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o
-obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o
 obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o
 obj-$(CONFIG_NAND_BRCMNAND) += brcmnand_compat.o
+obj-$(CONFIG_NAND_BRCMNAND) += bcmbca_nand.o
+endif
diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c
deleted file mode 100644
index 3586baa4fa..0000000000
--- a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include <common.h>
-#include <asm/io.h>
-#include <memalign.h>
-#include <nand.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <dm.h>
-
-#include "brcmnand.h"
-
-struct bcm6858_nand_soc {
-	struct brcmnand_soc soc;
-	void __iomem *base;
-};
-
-#define BCM6858_NAND_INT		0x00
-#define BCM6858_NAND_STATUS_SHIFT	0
-#define BCM6858_NAND_STATUS_MASK	(0xfff << BCM6858_NAND_STATUS_SHIFT)
-
-#define BCM6858_NAND_INT_EN		0x04
-#define BCM6858_NAND_ENABLE_SHIFT	0
-#define BCM6858_NAND_ENABLE_MASK	(0xffff << BCM6858_NAND_ENABLE_SHIFT)
-
-enum {
-	BCM6858_NP_READ		= BIT(0),
-	BCM6858_BLOCK_ERASE	= BIT(1),
-	BCM6858_COPY_BACK	= BIT(2),
-	BCM6858_PAGE_PGM	= BIT(3),
-	BCM6858_CTRL_READY	= BIT(4),
-	BCM6858_DEV_RBPIN	= BIT(5),
-	BCM6858_ECC_ERR_UNC	= BIT(6),
-	BCM6858_ECC_ERR_CORR	= BIT(7),
-};
-
-static bool bcm6858_nand_intc_ack(struct brcmnand_soc *soc)
-{
-	struct bcm6858_nand_soc *priv =
-			container_of(soc, struct bcm6858_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM6858_NAND_INT;
-	u32 val = brcmnand_readl(mmio);
-
-	if (val & (BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT)) {
-		/* Ack interrupt */
-		val &= ~BCM6858_NAND_STATUS_MASK;
-		val |= BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT;
-		brcmnand_writel(val, mmio);
-		return true;
-	}
-
-	return false;
-}
-
-static void bcm6858_nand_intc_set(struct brcmnand_soc *soc, bool en)
-{
-	struct bcm6858_nand_soc *priv =
-			container_of(soc, struct bcm6858_nand_soc, soc);
-	void __iomem *mmio = priv->base + BCM6858_NAND_INT_EN;
-	u32 val = brcmnand_readl(mmio);
-
-	/* Don't ack any interrupts */
-	val &= ~BCM6858_NAND_STATUS_MASK;
-
-	if (en)
-		val |= BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT;
-	else
-		val &= ~(BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT);
-
-	brcmnand_writel(val, mmio);
-}
-
-static int bcm6858_nand_probe(struct udevice *dev)
-{
-	struct udevice *pdev = dev;
-	struct bcm6858_nand_soc *priv = dev_get_priv(dev);
-	struct brcmnand_soc *soc;
-	struct resource res;
-
-	soc = &priv->soc;
-
-	dev_read_resource_byname(pdev, "nand-int-base", &res);
-	priv->base = devm_ioremap(dev, res.start, resource_size(&res));
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
-
-	soc->ctlrdy_ack = bcm6858_nand_intc_ack;
-	soc->ctlrdy_set_enabled = bcm6858_nand_intc_set;
-
-	/* Disable and ack all interrupts  */
-	brcmnand_writel(0, priv->base + BCM6858_NAND_INT_EN);
-	brcmnand_writel(0, priv->base + BCM6858_NAND_INT);
-
-	return brcmnand_probe(pdev, soc);
-}
-
-static const struct udevice_id bcm6858_nand_dt_ids[] = {
-	{
-		.compatible = "brcm,nand-bcm6858",
-	},
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(bcm6858_nand) = {
-	.name = "bcm6858-nand",
-	.id = UCLASS_MTD,
-	.of_match = bcm6858_nand_dt_ids,
-	.probe = bcm6858_nand_probe,
-	.priv_auto_alloc_size = sizeof(struct bcm6858_nand_soc),
-};
-
-void board_nand_init(void)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device_by_driver(UCLASS_MTD,
-					  DM_GET_DRIVER(bcm6858_nand), &dev);
-	if (ret && ret != -ENODEV)
-		pr_err("Failed to initialize %s. (error %d)\n", dev->name,
-		       ret);
-}
diff --git a/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c b/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c
new file mode 100644
index 0000000000..c7138bbb63
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright © 2010-2019 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <memalign.h>
+#include <nand.h>
+#include <clk.h>
+#include <linux/ioport.h>
+#include <linux/completion.h>
+#include <linux/errno.h>
+#include <linux/log2.h>
+#include <asm/processor.h>
+#include <dm.h>
+
+#include "brcmnand.h"
+#include "brcmnand_compat.h"
+
+
+struct bcmbca_nand_soc {
+	struct brcmnand_soc soc;
+	void __iomem *base;
+};
+
+#define BCMBCA_NAND_INT		0x00
+#define BCMBCA_NAND_STATUS_SHIFT	0
+#define BCMBCA_NAND_STATUS_MASK	(0xfff << BCMBCA_NAND_STATUS_SHIFT)
+
+#define BCMBCA_NAND_INT_EN		0x04
+#define BCMBCA_NAND_ENABLE_SHIFT	0
+#define BCMBCA_NAND_ENABLE_MASK	(0xffff << BCMBCA_NAND_ENABLE_SHIFT)
+
+enum {
+	BCMBCA_NP_READ		= BIT(0),
+	BCMBCA_BLOCK_ERASE		= BIT(1),
+	BCMBCA_COPY_BACK		= BIT(2),
+	BCMBCA_PAGE_PGM		= BIT(3),
+	BCMBCA_CTRL_READY		= BIT(4),
+	BCMBCA_DEV_RBPIN		= BIT(5),
+	BCMBCA_ECC_ERR_UNC		= BIT(6),
+	BCMBCA_ECC_ERR_CORR	= BIT(7),
+};
+
+static bool bcmbca_nand_intc_ack(struct brcmnand_soc *soc)
+{
+	struct bcmbca_nand_soc *priv =
+			container_of(soc, struct bcmbca_nand_soc, soc);
+	void __iomem *mmio = priv->base + BCMBCA_NAND_INT;
+	u32 val = brcmnand_readl(mmio);
+
+	if (val & (BCMBCA_CTRL_READY << BCMBCA_NAND_STATUS_SHIFT)) {
+		/* Ack interrupt */
+		val &= ~BCMBCA_NAND_STATUS_MASK;
+		val |= BCMBCA_CTRL_READY << BCMBCA_NAND_STATUS_SHIFT;
+		brcmnand_writel(val, mmio);
+		return true;
+	}
+
+	return false;
+}
+
+static void bcmbca_nand_intc_set(struct brcmnand_soc *soc, bool en)
+{
+	struct bcmbca_nand_soc *priv =
+			container_of(soc, struct bcmbca_nand_soc, soc);
+	void __iomem *mmio = priv->base + BCMBCA_NAND_INT_EN;
+	u32 val = brcmnand_readl(mmio);
+
+	/* Don't ack any interrupts */
+	val &= ~BCMBCA_NAND_STATUS_MASK;
+
+	if (en)
+		val |= BCMBCA_CTRL_READY << BCMBCA_NAND_ENABLE_SHIFT;
+	else
+		val &= ~(BCMBCA_CTRL_READY << BCMBCA_NAND_ENABLE_SHIFT);
+
+	brcmnand_writel(val, mmio);
+}
+
+static int bcmbca_nand_probe(struct udevice *dev)
+{
+	struct udevice *pdev = dev;
+	struct bcmbca_nand_soc *priv = dev_get_priv(dev);
+	struct brcmnand_soc *soc;
+	struct resource res;
+
+	soc = &priv->soc;
+
+	dev_read_resource_byname(pdev, "nand-int-base", &res);
+	priv->base = devm_ioremap(dev, res.start, resource_size(&res));
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	soc->ctlrdy_ack = bcmbca_nand_intc_ack;
+	soc->ctlrdy_set_enabled = bcmbca_nand_intc_set;
+
+	/* Disable and ack all interrupts  */
+	brcmnand_writel(0, priv->base + BCMBCA_NAND_INT_EN);
+	brcmnand_writel(0, priv->base + BCMBCA_NAND_INT);
+
+	return brcmnand_probe(pdev, soc);
+}
+
+static const struct udevice_id bcmbca_nand_dt_ids[] = {
+	{
+		.compatible = "brcm,nand-bcmbca",
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(brcm_nand) = {
+	.name = "brcm-nand",
+	.id = UCLASS_MTD,
+	.of_match = bcmbca_nand_dt_ids,
+	.probe = bcmbca_nand_probe,
+	.priv_auto_alloc_size = sizeof(struct bcmbca_nand_soc),
+};
+
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("David Regan");
+MODULE_DESCRIPTION("NAND driver for Broadcom chips");
+MODULE_ALIAS("platform:brcmnand");
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
index faa6da42d5..bc79166cc1 100644
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
@@ -699,6 +699,14 @@ static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
 	return mask;
 }
 
+static inline int brcmnand_ecc_level_shift(struct brcmnand_controller *ctrl)
+{
+	if (ctrl->nand_version >= 0x0702)
+		return NAND_ACC_CONTROL_ECC_EXT_SHIFT;
+	else
+		return NAND_ACC_CONTROL_ECC_SHIFT;
+}
+
 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
 {
 	struct brcmnand_controller *ctrl = host->ctrl;
@@ -760,6 +768,38 @@ static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
 	nand_writereg(ctrl, acc_control_offs, tmp);
 }
 
+static int brcmnand_get_spare_size(struct brcmnand_host *host)
+{
+	struct brcmnand_controller *ctrl = host->ctrl;
+	u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
+						  BRCMNAND_CS_ACC_CONTROL);
+	u32 acc = nand_readreg(ctrl, acc_control_offs);
+
+	return (acc&brcmnand_spare_area_mask(ctrl));
+}
+
+static int brcmnand_get_ecc_strength(struct brcmnand_host *host)
+{
+	struct brcmnand_controller *ctrl = host->ctrl;
+	u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
+						  BRCMNAND_CS_ACC_CONTROL);
+	int sector_size_1k = brcmnand_get_sector_size_1k(host);
+	u32 acc;
+	int spare_area_size, ecc_level, ecc_strength;
+
+	spare_area_size = brcmnand_get_spare_size(host);
+	acc = nand_readreg(ctrl, acc_control_offs);
+	ecc_level = (acc & brcmnand_ecc_level_mask(ctrl)) >> brcmnand_ecc_level_shift(ctrl);
+	if (sector_size_1k)
+		ecc_strength = ecc_level<<1;
+	else if(spare_area_size == 16 && ecc_level == 15 )
+		ecc_strength = 1; /* hamming */
+	else
+		ecc_strength = ecc_level;
+
+	return ecc_strength;
+}
+
 /***********************************************************************
  * CS_NAND_SELECT
  ***********************************************************************/
@@ -888,185 +928,134 @@ static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,
 }
 
 /*
- * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
- * the layout/configuration.
- * Returns -ERRCODE on failure.
+ * Returns a nand_ecclayout strucutre for the given layout/configuration.
+ * Returns NULL on failure.
  */
-static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section,
-					  struct mtd_oob_region *oobregion)
-{
-	struct nand_chip *chip = mtd_to_nand(mtd);
-	struct brcmnand_host *host = nand_get_controller_data(chip);
-	struct brcmnand_cfg *cfg = &host->hwcfg;
-	int sas = cfg->spare_area_size << cfg->sector_size_1k;
-	int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
-
-	if (section >= sectors)
-		return -ERANGE;
-
-	oobregion->offset = (section * sas) + 6;
-	oobregion->length = 3;
-
-	return 0;
-}
-
-static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section,
-					   struct mtd_oob_region *oobregion)
+static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
+						     struct brcmnand_host *host)
 {
-	struct nand_chip *chip = mtd_to_nand(mtd);
-	struct brcmnand_host *host = nand_get_controller_data(chip);
 	struct brcmnand_cfg *cfg = &host->hwcfg;
-	int sas = cfg->spare_area_size << cfg->sector_size_1k;
-	int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
-
-	if (section >= sectors * 2)
-		return -ERANGE;
-
-	oobregion->offset = (section / 2) * sas;
+	int i, j;
+	struct nand_ecclayout *layout;
+	int req;
+	int sectors;
+	int sas;
+	int idx1, idx2;
 
-	if (section & 1) {
-		oobregion->offset += 9;
-		oobregion->length = 7;
-	} else {
-		oobregion->length = 6;
-
-		/* First sector of each page may have BBI */
-		if (!section) {
-			/*
-			 * Small-page NAND use byte 6 for BBI while large-page
-			 * NAND use byte 0.
-			 */
-			if (cfg->page_size > 512)
-				oobregion->offset++;
-			oobregion->length--;
+#ifndef __UBOOT__
+	layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
+#else
+	layout = devm_kzalloc(host->pdev, sizeof(*layout), GFP_KERNEL);
+#endif
+	if (!layout)
+		return NULL;
+
+	sectors = cfg->page_size / (512 << cfg->sector_size_1k);
+	sas = cfg->spare_area_size << cfg->sector_size_1k;
+
+	/* Hamming */
+	if (is_hamming_ecc(host->ctrl, cfg)) {
+		for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
+			/* First sector of each page may have BBI */
+			if (i == 0) {
+				layout->oobfree[idx2].offset = i * sas + 1;
+				/* Small-page NAND use byte 6 for BBI */
+				if (cfg->page_size == 512)
+					layout->oobfree[idx2].offset--;
+				layout->oobfree[idx2].length = 5;
+			} else {
+				layout->oobfree[idx2].offset = i * sas;
+				layout->oobfree[idx2].length = 6;
+			}
+			idx2++;
+			layout->eccpos[idx1++] = i * sas + 6;
+			layout->eccpos[idx1++] = i * sas + 7;
+			layout->eccpos[idx1++] = i * sas + 8;
+			layout->oobfree[idx2].offset = i * sas + 9;
+			layout->oobfree[idx2].length = 7;
+			idx2++;
+			/* Leave zero-terminated entry for OOBFREE */
+			if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
+				    idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
+				break;
 		}
-	}
-
-	return 0;
-}
-
-static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = {
-	.ecc = brcmnand_hamming_ooblayout_ecc,
-	.free = brcmnand_hamming_ooblayout_free,
-};
-
-static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section,
-				      struct mtd_oob_region *oobregion)
-{
-	struct nand_chip *chip = mtd_to_nand(mtd);
-	struct brcmnand_host *host = nand_get_controller_data(chip);
-	struct brcmnand_cfg *cfg = &host->hwcfg;
-	int sas = cfg->spare_area_size << cfg->sector_size_1k;
-	int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
-
-	if (section >= sectors)
-		return -ERANGE;
-
-	oobregion->offset = (section * (sas + 1)) - chip->ecc.bytes;
-	oobregion->length = chip->ecc.bytes;
-
-	return 0;
-}
-
-static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section,
-					  struct mtd_oob_region *oobregion)
-{
-	struct nand_chip *chip = mtd_to_nand(mtd);
-	struct brcmnand_host *host = nand_get_controller_data(chip);
-	struct brcmnand_cfg *cfg = &host->hwcfg;
-	int sas = cfg->spare_area_size << cfg->sector_size_1k;
-	int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
-
-	if (section >= sectors)
-		return -ERANGE;
-
-	if (sas <= chip->ecc.bytes)
-		return 0;
-
-	oobregion->offset = section * sas;
-	oobregion->length = sas - chip->ecc.bytes;
 
-	if (!section) {
-		oobregion->offset++;
-		oobregion->length--;
+		return layout;
 	}
 
-	return 0;
-}
-
-static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section,
-					  struct mtd_oob_region *oobregion)
-{
-	struct nand_chip *chip = mtd_to_nand(mtd);
-	struct brcmnand_host *host = nand_get_controller_data(chip);
-	struct brcmnand_cfg *cfg = &host->hwcfg;
-	int sas = cfg->spare_area_size << cfg->sector_size_1k;
+	/*
+	 * CONTROLLER_VERSION:
+	 *   < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
+	 *  >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
+	 * But we will just be conservative.
+	 */
+	req = DIV_ROUND_UP(ecc_level * 14, 8);
+	if (req >= sas) {
+		dev_err(&host->pdev->dev,
+			"error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
+			req, sas);
+		return NULL;
+	}
 
-	if (section > 1 || sas - chip->ecc.bytes < 6 ||
-	    (section && sas - chip->ecc.bytes == 6))
-		return -ERANGE;
+	layout->eccbytes = req * sectors;
+	for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
+		for (j = sas - req; j < sas && idx1 <
+				MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
+			layout->eccpos[idx1] = i * sas + j;
 
-	if (!section) {
-		oobregion->offset = 0;
-		oobregion->length = 5;
-	} else {
-		oobregion->offset = 6;
-		oobregion->length = sas - chip->ecc.bytes - 6;
+		/* First sector of each page may have BBI */
+		if (i == 0) {
+			if (cfg->page_size == 512 && (sas - req >= 6)) {
+				/* Small-page NAND use byte 6 for BBI */
+				layout->oobfree[idx2].offset = 0;
+				layout->oobfree[idx2].length = 5;
+				idx2++;
+				if (sas - req > 6) {
+					layout->oobfree[idx2].offset = 6;
+					layout->oobfree[idx2].length =
+						sas - req - 6;
+					idx2++;
+				}
+			} else if (sas > req + 1) {
+				layout->oobfree[idx2].offset = i * sas + 1;
+				layout->oobfree[idx2].length = sas - req - 1;
+				idx2++;
+			}
+		} else if (sas > req) {
+			layout->oobfree[idx2].offset = i * sas;
+			layout->oobfree[idx2].length = sas - req;
+			idx2++;
+		}
+		/* Leave zero-terminated entry for OOBFREE */
+		if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
+				idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
+			break;
 	}
 
-	return 0;
+	return layout;
 }
 
-static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = {
-	.ecc = brcmnand_bch_ooblayout_ecc,
-	.free = brcmnand_bch_ooblayout_free_lp,
-};
-
-static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = {
-	.ecc = brcmnand_bch_ooblayout_ecc,
-	.free = brcmnand_bch_ooblayout_free_sp,
-};
-
-static int brcmstb_choose_ecc_layout(struct brcmnand_host *host)
+static struct nand_ecclayout *brcmstb_choose_ecc_layout(
+		struct brcmnand_host *host)
 {
+	struct nand_ecclayout *layout;
 	struct brcmnand_cfg *p = &host->hwcfg;
-	struct mtd_info *mtd = nand_to_mtd(&host->chip);
-	struct nand_ecc_ctrl *ecc = &host->chip.ecc;
 	unsigned int ecc_level = p->ecc_level;
-	int sas = p->spare_area_size << p->sector_size_1k;
-	int sectors = p->page_size / (512 << p->sector_size_1k);
 
 	if (p->sector_size_1k)
 		ecc_level <<= 1;
 
-	if (is_hamming_ecc(host->ctrl, p)) {
-		ecc->bytes = 3 * sectors;
-		mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops);
-		return 0;
-	}
-
-	/*
-	 * CONTROLLER_VERSION:
-	 *   < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
-	 *  >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
-	 * But we will just be conservative.
-	 */
-	ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);
-	if (p->page_size == 512)
-		mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops);
-	else
-		mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops);
-
-	if (ecc->bytes >= sas) {
+	layout = brcmnand_create_layout(ecc_level, host);
+	if (!layout) {
 		dev_err(&host->pdev->dev,
-			"error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
-			ecc->bytes, sas);
-		return -EINVAL;
+				"no proper ecc_layout for this NAND cfg\n");
+		return NULL;
 	}
 
-	return 0;
+	return layout;
 }
 
+
 static void brcmnand_wp(struct mtd_info *mtd, int wp)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
@@ -1727,11 +1716,13 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
 static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
 		  struct nand_chip *chip, void *buf, u64 addr)
 {
-	int i, sas;
-	void *oob = chip->oob_poi;
+	struct mtd_oob_region ecc;  
+	int i;
 	int bitflips = 0;
 	int page = addr >> chip->page_shift;
 	int ret;
+	void *ecc_bytes;
+	void *ecc_chunk;	
 
 	if (!buf) {
 #ifndef __UBOOT__
@@ -1743,16 +1734,20 @@ static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
 		chip->pagebuf = -1;
 	}
 
-	sas = mtd->oobsize / chip->ecc.steps;
-
 	/* read without ecc for verification */
 	ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
 	if (ret)
 		return ret;
 
-	for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
-		ret = nand_check_erased_ecc_chunk(buf, chip->ecc.size,
-						  oob, sas, NULL, 0,
+	for (i = 0; i < chip->ecc.steps; i++) {
+		ecc_chunk = buf + chip->ecc.size * i;
+
+		mtd_ooblayout_ecc(mtd, i, &ecc);
+		ecc_bytes = chip->oob_poi + ecc.offset;
+
+		ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
+						  ecc_bytes, ecc.length,						  
+						  NULL, 0,
 						  chip->ecc.strength);
 		if (ret < 0)
 			return ret;
@@ -2164,9 +2159,23 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
 	char msg[128];
 	u32 offs, tmp, oob_sector;
 	int ret;
+	int sector_size_1k = 0;
 
 	memset(cfg, 0, sizeof(*cfg));
 
+	/* set ECC size and strength based on hw configuration from strap 
+	 * if dtb does not specify them 
+	 */
+	sector_size_1k = brcmnand_get_sector_size_1k(host);
+	if (chip->ecc.size == 0) {
+		if (sector_size_1k< 0)
+			chip->ecc.size = 512;
+		else
+			chip->ecc.size = 512<<sector_size_1k;
+	}
+	
+	if (chip->ecc.strength == 0)
+		chip->ecc.strength = brcmnand_get_ecc_strength(host);
 #ifndef __UBOOT__
 	ret = of_property_read_u32(nand_get_flash_node(chip),
 				   "brcm,nand-oob-sector-size",
@@ -2177,9 +2186,10 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
 			      &oob_sector);
 #endif /* __UBOOT__ */
 	if (ret) {
-		/* Use detected size */
-		cfg->spare_area_size = mtd->oobsize /
-					(mtd->writesize >> FC_SHIFT);
+		/* set spare area based on hw configuration from strap 
+		 * if dtb does not specify them 
+		 */
+		cfg->spare_area_size = brcmnand_get_spare_size(host);
 	} else {
 		cfg->spare_area_size = oob_sector;
 	}
@@ -2327,7 +2337,7 @@ static int brcmnand_init_cs(struct brcmnand_host *host, ofnode dn)
 #ifndef __UBOOT__
 	mtd->dev.parent = &pdev->dev;
 #else
-	mtd->dev->parent = pdev;
+	mtd->dev = pdev;
 #endif /* __UBOOT__ */
 
 	chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
@@ -2383,9 +2393,9 @@ static int brcmnand_init_cs(struct brcmnand_host *host, ofnode dn)
 	/* only use our internal HW threshold */
 	mtd->bitflip_threshold = 1;
 
-	ret = brcmstb_choose_ecc_layout(host);
-	if (ret)
-		return ret;
+	chip->ecc.layout = brcmstb_choose_ecc_layout(host);
+	if (!chip->ecc.layout)
+		return -ENXIO;
 
 	ret = nand_scan_tail(mtd);
 	if (ret)
diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand_spl.c b/drivers/mtd/nand/raw/brcmnand/brcmnand_spl.c
new file mode 100644
index 0000000000..d054bf4ac9
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand_spl.c
@@ -0,0 +1,934 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+//#define DEBUG
+
+#include <common.h>
+#include <nand.h>
+#include "brcmnand.h"
+#include "brcmnand_spl.h"
+
+#define SPARE_MAX_SIZE          (27 * 16)
+#define CTRLR_CACHE_SIZE        512
+#define FC_WORDS		(CTRLR_CACHE_SIZE  >> 2)
+
+#define NAND_CHIPID(chip)       ((chip)->chip_device_id >> 16)
+
+/* Flash manufacturers. */
+#define FLASHTYPE_SAMSUNG       0xec
+#define FLASHTYPE_ST            0x20
+#define FLASHTYPE_MICRON        0x2c
+#define FLASHTYPE_HYNIX         0xad
+#define FLASHTYPE_TOSHIBA       0x98
+#define FLASHTYPE_MXIC          0xc2
+#define FLASHTYPE_SPANSION      0x01
+
+/* Samsung flash parts. */
+#define SAMSUNG_K9F5608U0A      0x55
+#define SAMSUNG_K9F1208U0       0x76
+#define SAMSUNG_K9F1G08U0       0xf1
+
+/* ST flash parts. */
+#define ST_NAND512W3A2CN6       0x76
+#define ST_NAND01GW3B2CN6       0xf1
+
+/* Micron flash parts. */
+#define MICRON_MT29F1G08AAC     0xf1
+#define MICRON_MT29F2G08ABA     0xda
+#define MICRON_MT29F4G08ABA     0xdc
+#define MICRON_MT29F8G08ABA     0x38
+#define MICRON_MT29F8G16ABA     0xd3
+
+/* Hynix flash parts. */
+#define HYNIX_H27U1G8F2B        0xf1
+#define HYNIX_H27U518S2C        0x76
+
+/* MXIC flash parts */
+#define MXIC_MX30LF1208AA       0xf0
+#define MXIC_MX30LF1G08AA       0xf1
+
+/* SPANSION flash parts */
+#define SPANSION_S34ML01G1      0xf1
+#define SPANSION_S34ML02G1      0xda
+#define SPANSION_S34ML04G1      0xdc
+
+/* Flash id to name mapping. */
+#define NAND_MAKE_ID(A,B)    \
+    (((unsigned short) (A) << 8) | ((unsigned short) B & 0xff))
+
+#define NAND_FLASH_DEVICES                                                    \
+  {{NAND_MAKE_ID(FLASHTYPE_SAMSUNG,SAMSUNG_K9F5608U0A),"Samsung K9F5608U0"},  \
+   {NAND_MAKE_ID(FLASHTYPE_SAMSUNG,SAMSUNG_K9F1208U0),"Samsung K9F1208U0"},   \
+   {NAND_MAKE_ID(FLASHTYPE_SAMSUNG,SAMSUNG_K9F1G08U0),"Samsung K9F1G08U0"},   \
+   {NAND_MAKE_ID(FLASHTYPE_ST,ST_NAND512W3A2CN6),"ST NAND512W3A2CN6"},        \
+   {NAND_MAKE_ID(FLASHTYPE_ST,ST_NAND01GW3B2CN6),"ST NAND01GW3B2CN6"},        \
+   {NAND_MAKE_ID(FLASHTYPE_MICRON,MICRON_MT29F1G08AAC),"Micron MT29F1G08AAC"},\
+   {NAND_MAKE_ID(FLASHTYPE_MICRON,MICRON_MT29F2G08ABA),"Micron MT29F2G08ABA"},\
+   {NAND_MAKE_ID(FLASHTYPE_MICRON,MICRON_MT29F4G08ABA),"Micron MT29F4G08ABA"},\
+   {NAND_MAKE_ID(FLASHTYPE_MICRON,MICRON_MT29F8G08ABA),"Micron MT29F8G08ABA"},\
+   {NAND_MAKE_ID(FLASHTYPE_MICRON,MICRON_MT29F8G16ABA),"Micron MT29F8G16ABA"},\
+   {NAND_MAKE_ID(FLASHTYPE_HYNIX,HYNIX_H27U1G8F2B),"Hynix H27U1G8F2B"},       \
+   {NAND_MAKE_ID(FLASHTYPE_HYNIX,HYNIX_H27U518S2C),"Hynix H27U518S2C"},       \
+   {NAND_MAKE_ID(FLASHTYPE_MXIC,MXIC_MX30LF1208AA),"MXIC MX30LF1208AA"},      \
+   {NAND_MAKE_ID(FLASHTYPE_MXIC,MXIC_MX30LF1G08AA),"MXIC MX30LF1G08AA"},      \
+   {NAND_MAKE_ID(FLASHTYPE_SPANSION,SPANSION_S34ML01G1),"Spansion S34ML01G1"},\
+   {NAND_MAKE_ID(FLASHTYPE_SPANSION,SPANSION_S34ML02G1),"Spansion S34ML02G1"},\
+   {NAND_MAKE_ID(FLASHTYPE_SPANSION,SPANSION_S34ML04G1),"Spansion S34ML04G1"},\
+   {0,""}                                                                     \
+  }
+
+#define NAND_FLASH_MANUFACTURERS        \
+  {{FLASHTYPE_SAMSUNG, "Samsung"},      \
+   {FLASHTYPE_ST, "ST"},                \
+   {FLASHTYPE_MICRON, "Micron"},        \
+   {FLASHTYPE_HYNIX, "Hynix"},          \
+   {FLASHTYPE_TOSHIBA, "Toshiba"},      \
+   {FLASHTYPE_MXIC, "MXIC"},            \
+   {FLASHTYPE_SPANSION, "Spansion"},    \
+   {0,""}                               \
+  }
+
+/* Condition to determine the spare layout. */
+#define LAYOUT_PARMS(L,S,P)     \
+    (((unsigned int)(L)<<28) | ((unsigned int)(S)<<16) | (P))
+
+/* Each bit in the ECCMSK array represents a spare area byte. Bits that are
+ * set correspond to spare area bytes that are reserved for the ECC or bad
+ * block indicator. Bits that are not set can be used for data such as the
+ * JFFS2 clean marker. This macro returns 0 if the spare area byte at offset,
+ * OFS, is available and non-0 if it is being used for the ECC or BI.
+ */
+#define ECC_MASK_BIT(ECCMSK, OFS)   (ECCMSK[OFS / 8] & (1 << (OFS % 8)))
+
+#define SPARE_BI_MARKER         0
+#define SPARE_GOOD_MARKER       0xFF
+
+/* Fixed definition for NAND controller on all revision */
+#define CMD_NULL			0x00
+#define CMD_PAGE_READ			0x01
+#define CMD_SPARE_AREA_READ		0x02
+#define CMD_STATUS_READ			0x03
+#define CMD_PROGRAM_PAGE		0x04
+#define CMD_PROGRAM_SPARE_AREA		0x05
+#define CMD_COPY_BACK			0x06
+#define CMD_DEVICE_ID_READ		0x07
+#define CMD_BLOCK_ERASE			0x08
+#define CMD_FLASH_RESET			0x09
+#define CMD_BLOCKS_LOCK			0x0a
+#define CMD_BLOCKS_LOCK_DOWN		0x0b
+#define CMD_BLOCKS_UNLOCK		0x0c
+#define CMD_READ_BLOCKS_LOCK_STATUS	0x0d
+#define CMD_PARAMETER_READ		0x0e
+#define CMD_PARAMETER_CHANGE_COL	0x0f
+#define CMD_LOW_LEVEL_OP		0x10
+
+#define NBC_AUTO_DEV_ID_CFG		(1 << 30)
+
+#define NIS_CTLR_READY			(1 << 31)
+#define NIS_FLASH_READY			(1 << 30)
+#define NIS_CACHE_VALID			(1 << 29)
+#define NIS_SPARE_VALID			(1 << 28)
+#define NIS_FLASH_STS_MASK		0x000000ff
+
+#define NC_DEV_SIZE_SHIFT		24
+#define NC_DEV_SIZE_MASK		(0x0f << NC_DEV_SIZE_SHIFT)
+#define NC_FUL_ADDR_SHIFT		16
+#define NC_FUL_ADDR_MASK		(0x7 << NC_FUL_ADDR_SHIFT)
+#define NC_COL_ADDR_SHIFT		12
+#define NC_COL_ADDR_MASK		(0x7 << NC_COL_ADDR_SHIFT)
+#define NC_BLK_ADDR_SHIFT		8
+#define NC_BLK_ADDR_MASK		(0x07 << NC_BLK_ADDR_SHIFT)
+
+#define NAC_ECC_LVL_SHIFT		16
+#define NAC_ECC_LVL_MASK		0x001f0000
+#define NAC_ECC_LVL_DISABLE		0
+#define NAC_ECC_LVL_BCH_1		1
+#define NAC_ECC_LVL_BCH_2		2
+#define NAC_ECC_LVL_BCH_3		3
+#define NAC_ECC_LVL_BCH_4		4
+#define NAC_ECC_LVL_BCH_5		5
+#define NAC_ECC_LVL_BCH_6		6
+#define NAC_ECC_LVL_BCH_7		7
+#define NAC_ECC_LVL_BCH_8		8
+#define NAC_ECC_LVL_BCH_9		9
+#define NAC_ECC_LVL_BCH_10		10
+#define NAC_ECC_LVL_BCH_11		11
+#define NAC_ECC_LVL_BCH_12		12
+#define NAC_ECC_LVL_BCH_13		13
+#define NAC_ECC_LVL_BCH_14		14
+#define NAC_ECC_LVL_HAMMING		15	/* Hamming if spare are size = 16, BCH15 otherwise */
+#define NAC_ECC_LVL_BCH15		15
+#define NAC_ECC_LVL_BCH_16		16
+#define NAC_ECC_LVL_BCH_17		17
+/* BCH18 to 30 use sector size = 1K */
+#define NAC_SECTOR_SIZE_1K		(1 << 7)
+#define NAC_SPARE_SZ_SHIFT		0
+#define NAC_SPARE_SZ_MASK		0x0000007f
+
+#define NT_TREH_MASK			0x000f0000
+#define NT_TREH_SHIFT			16
+#define NT_TRP_MASK			0x00f00000
+#define NT_TRP_SHIFT			20
+#define NT_TREAD_MASK			0x0000000f
+#define NT_TREAD_SHIFT			0
+
+struct cfg_decode_map {
+	uint16_t dev_size_reg;
+	uint16_t dev_size_shift;
+	uint32_t dev_size_mask;
+	uint16_t block_size_reg;
+	uint16_t block_size_shift;
+	uint32_t block_size_mask;
+	uint16_t page_size_reg;
+	uint16_t page_size_shift;
+	uint32_t page_size_mask;
+	uint32_t *block_tbl;
+	uint32_t *page_tbl;
+};
+
+struct brcmnand_controller {
+	void __iomem *nand_base;
+	void __iomem *nand_fc;	/* flash cache */
+	uint16_t nand_version;
+	const uint16_t *reg_offsets;
+	const struct cfg_decode_map *cfg_dec_map;
+	uint8_t *flash_cache;
+};
+
+struct brcmnand_chip {
+	struct brcmnand_controller *ctrl;
+	uint32_t chip_device_id;
+	uint64_t chip_total_size;
+	uint32_t chip_block_size;
+	uint32_t chip_page_size;
+	uint32_t chip_spare_size;
+	uint32_t chip_spare_step_size;
+	uint32_t chip_ecc_level;
+	uint32_t sector_size_1k;
+	uint32_t chip_bi_index_1;
+	uint32_t chip_bi_index_2;
+};
+
+enum brcmnand_reg {
+	BRCMNAND_CMD_START = 0,
+	BRCMNAND_CMD_EXT_ADDRESS,
+	BRCMNAND_CMD_ADDRESS,
+	BRCMNAND_INTFC_STATUS,
+	BRCMNAND_CS_SELECT,
+	BRCMNAND_CS_XOR,
+	BRCMNAND_CS_ACC_CONTROL,
+	BRCMNAND_CS_CFG_EXT,
+	BRCMNAND_CS_CFG,
+	BRCMNAND_ID,
+	BRCMNAND_OOB_READ_BASE,
+	BRCMNAND_TIMING1,
+	BRCMNAND_TIMING2,
+};
+
+/* BRCMNAND v6.0 - v7.0 */
+static const u16 brcmnand_regs_v60[] = {
+	[BRCMNAND_CMD_START] = 0x04,
+	[BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
+	[BRCMNAND_CMD_ADDRESS] = 0x0c,
+	[BRCMNAND_INTFC_STATUS] = 0x14,
+	[BRCMNAND_CS_SELECT] = 0x18,
+	[BRCMNAND_CS_XOR] = 0x1c,
+	[BRCMNAND_CS_ACC_CONTROL] = 0x50,
+	[BRCMNAND_CS_CFG_EXT] = 0,
+	[BRCMNAND_CS_CFG] = 0x54,
+	[BRCMNAND_TIMING1] = 0x58,
+	[BRCMNAND_TIMING2] = 0x5c,
+	[BRCMNAND_ID] = 0x194,
+	[BRCMNAND_OOB_READ_BASE] = 0x200,
+};
+
+/* BRCMNAND v7.1 */
+static const u16 brcmnand_regs_v71[] = {
+	[BRCMNAND_CMD_START] = 0x04,
+	[BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
+	[BRCMNAND_CMD_ADDRESS] = 0x0c,
+	[BRCMNAND_INTFC_STATUS] = 0x14,
+	[BRCMNAND_CS_SELECT] = 0x18,
+	[BRCMNAND_CS_XOR] = 0x1c,
+	[BRCMNAND_CS_ACC_CONTROL] = 0x50,
+	[BRCMNAND_CS_CFG_EXT] = 0x54,
+	[BRCMNAND_CS_CFG] = 0x58,
+	[BRCMNAND_TIMING1] = 0x5c,
+	[BRCMNAND_TIMING2] = 0x60,
+	[BRCMNAND_ID] = 0x194,
+	[BRCMNAND_OOB_READ_BASE] = 0x200,
+};
+
+uint32_t blk_tbl_v60[] = {
+	SZ_8K,
+	SZ_16K,
+	SZ_128K,
+	SZ_256K,
+	SZ_512K,
+	SZ_1M,
+	SZ_2M,
+	0,
+};
+
+uint32_t pg_tbl_v60[] = {
+	SZ_512,
+	SZ_2K,
+	SZ_4K,
+	SZ_8K,
+	0,
+};
+
+static const struct cfg_decode_map cfg_decode_map_v60 = {
+	.dev_size_reg = BRCMNAND_CS_CFG,
+	.dev_size_shift = 24,
+	.dev_size_mask = (0xf << 24),
+	.block_size_reg = BRCMNAND_CS_CFG,
+	.block_size_shift = 28,
+	.block_size_mask = (0x7 << 28),
+	.page_size_reg = BRCMNAND_CS_CFG,
+	.page_size_shift = 20,
+	.page_size_mask = (0x3 << 20),
+	.block_tbl = blk_tbl_v60,
+	.page_tbl = pg_tbl_v60,
+};
+
+static const struct cfg_decode_map cfg_decode_map_v71 = {
+	.dev_size_reg = BRCMNAND_CS_CFG,
+	.dev_size_shift = 24,
+	.dev_size_mask = (0xf << 24),
+	.block_size_reg = BRCMNAND_CS_CFG_EXT,
+	.block_size_shift = 4,
+	.block_size_mask = (0xff << 4),
+	.page_size_reg = BRCMNAND_CS_CFG_EXT,
+	.page_size_shift = 0,
+	.page_size_mask = 0xf,
+	.block_tbl = NULL,
+	.page_tbl = NULL,
+};
+
+static struct brcmnand_chip nand_chip;
+static struct brcmnand_controller nand_ctrl;
+
+static u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
+{
+	return brcmnand_readl(ctrl->nand_base + offs);
+}
+
+static void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, u32 val)
+{
+	brcmnand_writel(val, ctrl->nand_base + offs);
+}
+
+static u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, enum brcmnand_reg reg)
+{
+	u16 offs = ctrl->reg_offsets[reg];
+
+	if (offs)
+		return nand_readreg(ctrl, offs);
+	else
+		return 0;
+}
+
+static void brcmnand_write_reg(struct brcmnand_controller *ctrl, enum brcmnand_reg reg, u32 val)
+{
+	u16 offs = ctrl->reg_offsets[reg];
+
+	if (offs)
+		nand_writereg(ctrl, offs, val);
+}
+
+static void brcmnand_rmw_reg(struct brcmnand_controller *ctrl, enum brcmnand_reg reg, u32 mask, unsigned
+			     int shift, u32 val)
+{
+	u32 tmp = brcmnand_read_reg(ctrl, reg);
+
+	tmp &= ~mask;
+	tmp |= val << shift;
+	brcmnand_write_reg(ctrl, reg, tmp);
+}
+
+static u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, uint32_t offset)
+{
+	return __raw_readl(ctrl->nand_fc + offset);
+}
+
+static u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
+{
+	u16 offset0, reg_offs;
+
+	offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
+
+	reg_offs = offset0 + (offs & ~0x03);
+
+	return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
+}
+
+static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
+{
+	ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
+
+	/* Only support v4.0+? */
+	if (ctrl->nand_version < 0x0600 || ctrl->nand_version > 0x0701) {
+		dev_err(ctrl->dev, "version %#x not supported\n", ctrl->nand_version);
+		return -ENODEV;
+	}
+
+	/* Register offsets */
+	if (ctrl->nand_version >= 0x0701) {
+		ctrl->reg_offsets = brcmnand_regs_v71;
+		ctrl->cfg_dec_map = &cfg_decode_map_v71;
+	} else {
+		ctrl->reg_offsets = brcmnand_regs_v60;
+		ctrl->cfg_dec_map = &cfg_decode_map_v60;
+	}
+
+	return 0;
+}
+
+static int brcmnand_wait_status(struct brcmnand_controller *ctrl, unsigned int status_mask)
+{
+
+	const unsigned int nand_poll_max = 2000000;
+
+	unsigned int data;
+	unsigned int poll_count = 0;
+	int ret = 0;
+
+	do {
+		data = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
+	} while (!(status_mask & data) && (++poll_count < nand_poll_max));
+
+	data = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
+	if (!(status_mask & data)) {
+		printf("Status wait timeout: nandsts=0x%8.8x mask=0x%8.8x, count=" "%u\n", data, status_mask, poll_count);
+		ret = -ETIMEDOUT;
+	}
+
+	return (ret);
+}
+
+extern int brcmnand_wait_cmd(struct brcmnand_controller *ctrl)
+{
+	return brcmnand_wait_status(ctrl, NIS_CTLR_READY);
+}
+
+extern int brcmnand_wait_device(struct brcmnand_controller *ctrl)
+{
+	return brcmnand_wait_status(ctrl, NIS_FLASH_READY);
+}
+
+extern int brcmnand_wait_cache(struct brcmnand_controller *ctrl)
+{
+	return brcmnand_wait_status(ctrl, NIS_CACHE_VALID);
+}
+
+extern int brcmnand_wait_spare(struct brcmnand_controller *ctrl)
+{
+	return brcmnand_wait_status(ctrl, NIS_SPARE_VALID);
+}
+
+static void brcmnand_reset_device(struct brcmnand_controller *ctrl)
+{
+	brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, (NBC_AUTO_DEV_ID_CFG | 1));
+	brcmnand_wait_device(ctrl);
+	brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, 0x0);
+}
+
+static uint32_t brcmnand_block_size_mapped(uint32_t * block_tbl, uint32_t block_size)
+{
+	uint32_t i = 0;
+
+	while (block_tbl[i]) {
+		if (block_tbl[i] == block_size)
+			return i;
+		i++;
+	}
+
+	printf("Invalid block size %dKB for this nand controller!\n", block_size >> 10);
+	return 0;
+}
+
+static uint64_t brcmnand_get_dev_size(struct brcmnand_controller *ctrl)
+{
+	uint32_t dev_size, reg;
+	const struct cfg_decode_map *cfg_map = ctrl->cfg_dec_map;
+
+	reg = brcmnand_read_reg(ctrl, cfg_map->dev_size_reg);
+	dev_size = (reg & cfg_map->dev_size_mask) >> cfg_map->dev_size_shift;
+
+	return 1ULL << (dev_size + 22);
+}
+
+static uint32_t brcmnand_get_blk_size(struct brcmnand_controller *ctrl)
+{
+	uint32_t blk_size, reg;
+	const struct cfg_decode_map *cfg_map = ctrl->cfg_dec_map;
+
+	reg = brcmnand_read_reg(ctrl, cfg_map->block_size_reg);
+	blk_size = (reg & cfg_map->block_size_mask) >> cfg_map->block_size_shift;
+
+	if (cfg_map->block_tbl)
+		return cfg_map->block_tbl[blk_size];
+	else
+		return 1 << (blk_size + 13);
+}
+
+static uint32_t brcmnand_get_pg_size(struct brcmnand_controller *ctrl)
+{
+	uint32_t page_size, reg;
+	const struct cfg_decode_map *cfg_map = ctrl->cfg_dec_map;
+
+	reg = brcmnand_read_reg(ctrl, cfg_map->page_size_reg);
+	page_size = (reg & cfg_map->page_size_mask) >> cfg_map->page_size_shift;
+
+	if (cfg_map->page_tbl)
+		return cfg_map->page_tbl[page_size];
+	else
+		return 1 << (page_size + 9);
+}
+
+static void brcmnand_set_dev_size(struct brcmnand_controller *ctrl, uint32_t dev_size_in_order)
+{
+	const struct cfg_decode_map *cfg_map = ctrl->cfg_dec_map;
+
+	brcmnand_rmw_reg(ctrl, cfg_map->dev_size_reg, cfg_map->dev_size_mask, cfg_map->dev_size_shift, dev_size_in_order - 22);
+}
+
+static void brcmnand_set_block_size(struct brcmnand_controller *ctrl, uint32_t block_size_in_order)
+{
+	const struct cfg_decode_map *cfg_map = ctrl->cfg_dec_map;
+	uint32_t block_size, reg_val;
+
+	if (cfg_map->block_tbl) {
+		block_size = 1 << block_size_in_order;
+		reg_val = brcmnand_block_size_mapped(cfg_map->block_tbl, block_size);
+	} else
+		reg_val = block_size_in_order - 13;
+
+	brcmnand_rmw_reg(ctrl, cfg_map->block_size_reg, cfg_map->block_size_mask, cfg_map->block_size_shift, reg_val);
+}
+
+static void brcmnand_copy_from_cache(struct brcmnand_controller *ctrl, unsigned char *buffer, int offset, int numbytes)
+{
+	int use_buffer = 0, read_bytes, i;
+	uint32_t *buf;
+
+#if defined(CONFIG_BCM47189)
+	{
+		uint32_t ioctrl = NAND_FLASH_CTRL_WRAP->ioctrl;
+		ioctrl = ioctrl | NAND_APB_LITTLE_ENDIAN;
+		NAND_FLASH_CTRL_WRAP->ioctrl = ioctrl;
+	}
+#endif
+	if (offset & 0x3) {
+		printk("brcmnand_copy_from_cache invalid offset %d!\n", offset);
+		return;
+	}
+
+	use_buffer = ((uintptr_t) buffer & 0x3) || (numbytes & 0x3);
+	if (use_buffer)
+		buf = (uint32_t *) ctrl->flash_cache;
+	else
+		buf = (uint32_t *) buffer;
+	read_bytes = ((numbytes + 0x3) >> 2) << 2;
+
+	debug(">> brcmnand_copy_from_cache - use_buffer %d buffer 0x%p offset %d read bytes %d\n",
+	      use_buffer, buf, offset, read_bytes);
+
+	for (i = 0; i < read_bytes; i += 4, buf++) {
+		*buf = brcmnand_read_fc(ctrl, i + offset);
+#if 0
+		debug("0x%08x ", *buf);
+		if ((i + 1) % 16 == 0)
+			debug("\n");
+#endif
+	}
+	//debug("\n");
+
+	if (use_buffer)
+		memcpy(buffer, ctrl->flash_cache, numbytes);
+
+#if defined(CONFIG_BCM47189)
+	{
+		uint32_t ioctrl = NAND_FLASH_CTRL_WRAP->ioctrl;
+		ioctrl = ioctrl & ~NAND_APB_LITTLE_ENDIAN;
+		NAND_FLASH_CTRL_WRAP->ioctrl = ioctrl;
+	}
+#endif
+
+}
+
+static void brcmnand_copy_from_spare(struct brcmnand_controller *ctrl, unsigned char *buffer, int numbytes)
+{
+	for (int i = 0; i < numbytes; i++)
+		buffer[i] = oob_reg_read(ctrl, i);
+}
+
+static void brcmnand_check_onfi(struct brcmnand_chip *chip, struct brcmnand_controller *ctrl)
+{
+	struct nand_onfi_params onfi;
+	uint64_t onfi_total_size;
+	uint32_t size_in_order = 0;
+
+	memset(&onfi, 0x0, sizeof(onfi));
+	brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, CMD_PARAMETER_READ);
+	if (brcmnand_wait_cmd(ctrl) == 0 && brcmnand_wait_cache(ctrl) == 0) {
+		// Hardware NAND controller does not take into account LUNs, so if this value is not 1 we calculate the die stack NAND size
+		brcmnand_copy_from_cache(ctrl, (unsigned char *)&onfi, 0, sizeof(onfi));
+		if ((onfi.sig[0] == 'O') && (onfi.sig[1] == 'N') && (onfi.sig[2] == 'F') && (onfi.sig[3] == 'I')) {
+			debug("ONFI detected, page size 0x%x, page per block %d block per lun %d lun count%d\n",
+			      le32_to_cpu(onfi.byte_per_page), le32_to_cpu(onfi.pages_per_block),
+			      le32_to_cpu(onfi.blocks_per_lun), onfi.lun_count);
+
+			//adjust size based on # of luns
+			if (onfi.lun_count != 1) {
+				onfi_total_size = le32_to_cpu(onfi.byte_per_page) * le32_to_cpu(onfi.pages_per_block);
+				onfi_total_size *= le32_to_cpu(onfi.blocks_per_lun);
+				onfi_total_size *= onfi.lun_count;
+
+				if (onfi_total_size != chip->chip_total_size) {
+					printf("Correct total size based on ONFI old size 0x%llx to new size 0x%llx\n",
+					       chip->chip_total_size, onfi_total_size);
+					chip->chip_total_size = onfi_total_size;
+					while (onfi_total_size >>= 1) {
+						size_in_order++;
+					}
+
+					brcmnand_set_dev_size(ctrl, size_in_order);
+				}
+			}
+		}
+	}
+}
+
+static int brcmnand_adjust_cfg(struct brcmnand_chip *chip)
+{
+	struct brcmnand_controller *ctrl = chip->ctrl;
+	const struct cfg_decode_map *cfg_map = ctrl->cfg_dec_map;
+	uint32_t mask, reg_val;
+	uint32_t ecc_lvl;
+
+	/* Special case changes from what the NAND controller configured. */
+	switch (NAND_CHIPID(chip)) {
+	case NAND_MAKE_ID(FLASHTYPE_HYNIX, HYNIX_H27U1G8F2B):
+		/* 128 MB device size, 4 full address bytes, 2 column address bytes, 2 block address bytes */
+		mask = cfg_map->dev_size_mask | NC_FUL_ADDR_MASK | NC_COL_ADDR_MASK | NC_BLK_ADDR_MASK;
+		reg_val =
+		    (5 << cfg_map->
+		     dev_size_shift) | (0x04 << NC_FUL_ADDR_SHIFT) | (0x2 << NC_COL_ADDR_SHIFT) | (0x2 << NC_BLK_ADDR_SHIFT);
+		brcmnand_rmw_reg(ctrl, BRCMNAND_CS_CFG, mask, 0, reg_val);
+		break;
+
+	case NAND_MAKE_ID(FLASHTYPE_SAMSUNG, SAMSUNG_K9F5608U0A):
+	case NAND_MAKE_ID(FLASHTYPE_SAMSUNG, SAMSUNG_K9F1208U0):
+	case NAND_MAKE_ID(FLASHTYPE_SAMSUNG, SAMSUNG_K9F1G08U0):
+	case NAND_MAKE_ID(FLASHTYPE_HYNIX, HYNIX_H27U518S2C):
+		/* Set device id "cell type" to 0 (SLC). */
+		chip->chip_device_id &= ~NAND_CI_CELLTYPE_MSK;
+		brcmnand_write_reg(ctrl, BRCMNAND_ID, chip->chip_device_id);
+		break;
+
+	case NAND_MAKE_ID(FLASHTYPE_MXIC, MXIC_MX30LF1208AA):
+		/* This 64MB device was detected as 256MB device on 63268. Manually update
+		 * device size in the cfg register.
+		 */
+		brcmnand_set_dev_size(ctrl, 26);
+		break;
+
+	case NAND_MAKE_ID(FLASHTYPE_SPANSION, SPANSION_S34ML01G1):
+		/* Set device size to 128MB, it is misconfigured to 512MB. */
+		brcmnand_set_dev_size(ctrl, 27);
+		break;
+
+	case NAND_MAKE_ID(FLASHTYPE_SPANSION, SPANSION_S34ML02G1):
+		/* Set device size to 256MB, it is misconfigured to 512MB. */
+		brcmnand_set_dev_size(ctrl, 28);
+		break;
+
+	case NAND_MAKE_ID(FLASHTYPE_SPANSION, SPANSION_S34ML04G1):
+		/* Set block size to 128KB, it is misconfigured to 512MB in 63138, 47189. */
+		if (ctrl->nand_version <= 0x00000700)
+			brcmnand_set_block_size(ctrl, 17);
+		break;
+	}
+
+	chip->chip_total_size = brcmnand_get_dev_size(ctrl);
+	chip->chip_block_size = brcmnand_get_blk_size(ctrl);
+	chip->chip_page_size = brcmnand_get_pg_size(ctrl);
+
+	/* for SPL we don't care spare area. Only need to know the bbi location */
+	reg_val = brcmnand_read_reg(ctrl, BRCMNAND_CS_ACC_CONTROL);
+	chip->chip_ecc_level = ecc_lvl = (reg_val & NAC_ECC_LVL_MASK) >> NAC_ECC_LVL_SHIFT;
+
+	/* The access control register spare size is the number of spare area
+	 * bytes per 512 bytes of data.  The chip_spare_size is the number
+	 * of spare area bytes per page.
+	 */
+	chip->chip_spare_step_size = ((reg_val & NAC_SPARE_SZ_MASK) >> NAC_SPARE_SZ_SHIFT);
+	chip->chip_spare_size = chip->chip_spare_step_size * (chip->chip_page_size >> 9);
+
+	if (ecc_lvl == NAC_ECC_LVL_HAMMING) {
+		if (chip->chip_page_size == 512) {
+			chip->chip_bi_index_1 = chip->chip_bi_index_2 = 5;
+		} else {
+			chip->chip_bi_index_1 = 0;
+			chip->chip_bi_index_2 = 1;
+		}
+	} else if (ecc_lvl == NAC_ECC_LVL_BCH_4 && chip->chip_page_size == 512) {
+		chip->chip_bi_index_1 = chip->chip_bi_index_2 = 5;
+	} else
+		chip->chip_bi_index_1 = chip->chip_bi_index_2 = 0;
+
+	chip->sector_size_1k = (reg_val & NAC_SECTOR_SIZE_1K) ? 1 : 0;
+
+	brcmnand_check_onfi(chip, ctrl);
+
+	return 0;
+}
+
+static void brcmnand_adjust_timing(struct brcmnand_chip *chip)
+{
+	struct brcmnand_controller *ctrl = chip->ctrl;
+
+	/* adjust reading timing */
+	/* Default of TRP=4 and TREAD=5 for Hynix parts on 63268 */
+	/* Almost all parts could use TRP=3 and TREAD=4 */
+
+	brcmnand_rmw_reg(ctrl, BRCMNAND_TIMING1, NT_TREH_MASK, NT_TREH_SHIFT, 2);
+	brcmnand_rmw_reg(ctrl, BRCMNAND_TIMING1, NT_TRP_MASK, NT_TRP_SHIFT, 4);
+
+	brcmnand_rmw_reg(ctrl, BRCMNAND_TIMING2, NT_TREAD_MASK, NT_TREAD_SHIFT, 5);
+}
+
+/* Simplified version for bad block marker read. Only read the first spare area step size */
+/* This is good enough for BBM */
+static int brcmnand_read_spare_area(struct brcmnand_chip *chip, uint64_t page_addr, unsigned char *buffer, int len)
+{
+	int ret = -EIO;
+	struct brcmnand_controller *ctrl = chip->ctrl;
+
+	if (len > chip->chip_spare_step_size)
+		len = chip->chip_spare_step_size;
+
+	brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, (uint32_t) page_addr);
+	brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, (uint32_t) (page_addr >> 32));
+	brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, CMD_PAGE_READ);
+
+	if ((ret = brcmnand_wait_cmd(ctrl)) == 0) {
+		/* wait until data is available in the spare area registers */
+		if ((ret = brcmnand_wait_spare(ctrl)) == 0)
+			brcmnand_copy_from_spare(ctrl, buffer, len);
+	}
+
+	return ret;
+}
+
+static int brcmnand_read_page(struct brcmnand_chip *chip, uint64_t start_addr, unsigned char *buffer, int len)
+{
+	int ret = -EIO;
+	struct brcmnand_controller *ctrl = chip->ctrl;
+
+	if (len <= chip->chip_block_size) {
+		uint64_t page_addr = start_addr & ~(chip->chip_page_size - 1);
+		uint32_t index = 0;
+		uint32_t subpage;
+		int length = len;
+
+		do {
+			for (subpage = 0, ret = 0; (subpage < chip->chip_page_size) && (ret == 0); subpage += CTRLR_CACHE_SIZE) {
+				brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, (uint32_t) page_addr + subpage);
+				brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, (uint32_t) (page_addr >> 32));
+				brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, CMD_PAGE_READ);
+
+				if ((ret = brcmnand_wait_cmd(ctrl)) == 0) {
+					/* wait until data is available in the cache */
+					if ((ret = brcmnand_wait_cache(ctrl)) != 0) {
+						ret = -EIO;
+					}
+
+					if ((ret == 0) && (start_addr < (page_addr + subpage + CTRLR_CACHE_SIZE)) && ((start_addr + len) > page_addr + subpage)) {	// copy from cache only if buffer is within the subpage
+						uint32_t copy_size, offset;
+
+						if (start_addr <= page_addr + subpage) {
+							offset = 0;
+
+							if ((start_addr + len) >= (page_addr + subpage + CTRLR_CACHE_SIZE))
+								copy_size = CTRLR_CACHE_SIZE;
+							else
+								copy_size = (start_addr + len) - (page_addr + subpage);
+						} else {	// start_addr > page_addr + subpage
+							offset = start_addr - (page_addr + subpage);
+
+							if ((start_addr + len) >= (page_addr + subpage + CTRLR_CACHE_SIZE))
+								copy_size = page_addr + subpage + CTRLR_CACHE_SIZE - start_addr;
+							else
+								copy_size = start_addr + len - start_addr;
+						}
+
+						brcmnand_copy_from_cache(ctrl, &buffer[index], offset, copy_size);
+
+						index += copy_size;
+						length -= copy_size;
+					}
+				}
+			}
+
+			if (ret != 0)
+				break;
+
+			page_addr += chip->chip_page_size;
+
+		} while (length);
+	}
+
+	return (ret);
+}
+
+void brcmnand_init(void)
+{
+	struct brcmnand_chip *chip = &nand_chip;
+	struct brcmnand_controller *ctrl = &nand_ctrl;
+
+	ctrl->flash_cache = memalign(sizeof(uint32_t), CTRLR_CACHE_SIZE);
+	if (ctrl->flash_cache == NULL) {
+		printf("nand_flash_init failed to allocate flash buffer!\n");
+		hang();
+	}
+
+	/* TODO get this base from device tree */
+	ctrl->nand_base = (void __iomem *)CONFIG_SYS_NAND_BASE;
+	ctrl->nand_fc = (void __iomem *)(CONFIG_SYS_NAND_BASE + 0x400);
+
+	chip->ctrl = ctrl;
+	brcmnand_revision_init(ctrl);
+	brcmnand_reset_device(ctrl);
+
+	/* Read the chip id. Only use the most signficant 16 bits. */
+	chip->chip_device_id = brcmnand_read_reg(ctrl, BRCMNAND_ID);
+	brcmnand_adjust_cfg(chip);
+	brcmnand_adjust_timing(chip);
+
+	printf("nand flash device id 0x%x, total size %dMB\n", chip->chip_device_id, (uint32_t) (chip->chip_total_size >> 20));
+	printf("block size %dKB, page size %d bytes, spare area %d bytes\n",
+	       chip->chip_block_size >> 10, chip->chip_page_size, chip->chip_spare_size);
+	if (chip->chip_ecc_level == 0)
+		printf("ECC disabled\n");
+	else if (chip->chip_ecc_level == NAC_ECC_LVL_HAMMING)
+		printf("ECC Hamming\n");
+	else {
+		printf("ECC BCH-%d", chip->chip_ecc_level << chip->sector_size_1k);
+		printf(" %s\n", chip->sector_size_1k ? "(1KB sector)" : "");
+	}
+}
+
+/* Check if the block is good or bad. If bad returns 1, if good returns 0 */
+int brcmnand_is_bad_block(int blk)
+{
+	struct brcmnand_chip *chip = &nand_chip;
+	unsigned char spare[16];
+	uint32_t page_addr = (blk * chip->chip_block_size) & ~(chip->chip_page_size - 1);
+	int i, size;
+
+	// always return good for block 0, because if it's a bad chip quite possibly the board is useless
+	if (blk == 0)
+		return 0;
+
+	/* bad block markers are always within first spare area step size. only need to read this many bytes */
+	size = max(chip->chip_bi_index_1, chip->chip_bi_index_2) + 1;
+	if (size > chip->chip_spare_step_size || size > 16) {
+		printf("bad block marker invalid location %d %d\n",
+			chip->chip_bi_index_1, chip->chip_bi_index_2);
+		return 1;
+	}
+	    
+	/* Read the spare area of first and second page and check for bad block indicator */
+	for (i = 0; i < 2; i += 1, page_addr += chip->chip_page_size) {
+		if (brcmnand_read_spare_area(chip, page_addr, spare, size) == 0) {
+			if ((spare[chip->chip_bi_index_1] != SPARE_GOOD_MARKER)
+			    || (spare[chip->chip_bi_index_2] != SPARE_GOOD_MARKER)) {
+				return 1;	// bad block
+			}
+		} else {
+			return 1;	//bad block
+		}
+	}
+
+	return 0;		// good block
+}
+
+int brcmnand_read_buf(int blk, int offset, u8 *buffer, u32 len)
+{
+	int ret;
+	struct brcmnand_chip *chip = &nand_chip;
+	uint64_t start_addr;
+	uint64_t blk_addr;
+	uint32_t blk_offset;
+	uint32_t size;
+	uint32_t total_block = chip->chip_total_size / chip->chip_block_size;
+
+	ret = len;
+
+	debug(">> brcmnand_read_buf - 1 blk=0x%8.8x, offset=%d, len=%d buffer 0x%p\n", blk, offset, len, buffer);
+
+	start_addr = (blk * chip->chip_block_size) + offset;
+	blk_addr = start_addr & ~(chip->chip_block_size - 1);
+	blk_offset = start_addr - blk_addr;
+	size = chip->chip_block_size - blk_offset;
+
+	if (size > len)
+		size = len;
+
+	if (blk >= total_block) {
+		printf("Attempt to read block number(%d) beyond the nand max blk(%d) \n", blk, total_block - 1);
+		return -EINVAL;
+	}
+
+	if (len)
+		do {
+			if (brcmnand_read_page(chip, start_addr, buffer, size) != 0) {
+				ret = -EIO;
+				break;
+			}
+
+			len -= size;
+			if (len) {
+				blk++;
+
+				debug(">> brcmnand_read_buf - 2 blk=0x%8.8x, len=%u\n", blk, len);
+
+				start_addr = blk * chip->chip_block_size;
+				buffer += size;
+				if (len > chip->chip_block_size)
+					size = chip->chip_block_size;
+				else
+					size = len;
+			}
+		} while (len);
+
+	if (brcmnand_is_bad_block(blk)) {	/* don't check for bad block during page read/write since may be reading/writing to bad block marker,
+					   check for bad block after read to allow for data recovery */
+		printf("brcmnand_read_buf(): Attempt to read bad nand block %d\n", blk);
+		return -EIO;
+	}
+
+	debug(">> brcmnand_read_buf - ret=%d\n", ret);
+
+	return (ret);
+}
+
+uint32_t brcmnand_get_page_size(void)
+{
+	return (nand_chip.chip_page_size);
+}
+
+uint32_t brcmnand_get_block_size(void)
+{
+	return (nand_chip.chip_block_size);
+}
+
+uint64_t brcmnand_get_total_size(void)
+{
+	return nand_chip.chip_total_size;
+}
+
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index aba8ac019d..50542a2b9a 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -3554,6 +3554,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 			pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
 				    __func__, page);
 			instr->state = MTD_ERASE_FAILED;
+			instr->fail_addr =
+				((loff_t)page << chip->page_shift);
 			goto erase_exit;
 		}
 
diff --git a/drivers/mtd/nand/raw/nand_util.c b/drivers/mtd/nand/raw/nand_util.c
index fc2235c1a0..ef3c939782 100644
--- a/drivers/mtd/nand/raw/nand_util.c
+++ b/drivers/mtd/nand/raw/nand_util.c
@@ -29,6 +29,7 @@
 #include <linux/mtd/mtd.h>
 #include <nand.h>
 #include <jffs2/jffs2.h>
+#include <linux/mtd/spinand.h>
 
 typedef struct erase_info	erase_info_t;
 typedef struct mtd_info		mtd_info_t;
@@ -59,6 +60,7 @@ int nand_erase_opts(struct mtd_info *mtd,
 	const char *mtd_device = mtd->name;
 	struct mtd_oob_ops oob_opts;
 	struct nand_chip *chip = mtd_to_nand(mtd);
+	bool spi_nand = !strncmp(mtd->dev->name, "spi-nand", 8);
 
 	if ((opts->offset & (mtd->erasesize - 1)) != 0) {
 		printf("Attempt to erase non block-aligned data\n");
@@ -84,15 +86,43 @@ int nand_erase_opts(struct mtd_info *mtd,
 	 */
 	if (opts->scrub) {
 		erase.scrub = opts->scrub;
-		/*
-		 * We don't need the bad block table anymore...
-		 * after scrub, there are no bad blocks left!
-		 */
-		if (chip->bbt) {
-			kfree(chip->bbt);
+
+		if (spi_nand)
+		{
+			struct spinand_device *spinand = mtd_to_spinand(mtd);
+			struct nand_device *nand = spinand_to_nand(spinand);
+
+			if (nanddev_bbt_is_initialized(nand))
+			{ // set unknown status in BBT of scrubbed blocks so that they are re-scanned, clearing BBT does not allow it to be rescanned and saved to memory
+				unsigned int entry;
+				struct nand_pos pos;
+				loff_t offs;
+
+				for (offs = erase.addr, erased_length = 0; erased_length < erase_length; offs += mtd->erasesize, erased_length++)
+				{
+					nanddev_offs_to_pos(nand, offs, &pos);
+					entry = nanddev_bbt_pos_to_entry(nand, &pos);
+					nanddev_bbt_set_block_status(nand, entry, NAND_BBT_BLOCK_STATUS_UNKNOWN);
+				}
+			}
+		}
+		else
+		{
+			printf("Please note: the FLASH blocks containing ONLY the BBT\n");
+			printf("should be erased so that ALL the FLASH blocks will be\n");
+			printf("automatically rescanned, rebuilding the BBT to match\n");
+			printf("the status of these newly scrubbed blocks\n");
+			/*
+			 * We don't need the bad block table anymore...
+			 * after scrub, there are no bad blocks left!
+			 */
+			if (chip->bbt) {
+				kfree(chip->bbt);
+			}
+
+			chip->bbt = NULL;
+			chip->options &= ~NAND_BBT_SCANNED;
 		}
-		chip->bbt = NULL;
-		chip->options &= ~NAND_BBT_SCANNED;
 	}
 
 	for (erased_length = 0;
@@ -137,7 +167,7 @@ int nand_erase_opts(struct mtd_info *mtd,
 		}
 
 		/* format for JFFS2 ? */
-		if (opts->jffs2 && chip->ecc.layout->oobavail >= 8) {
+		if (!spi_nand && opts->jffs2 && chip->ecc.layout->oobavail >= 8) {
 			struct mtd_oob_ops ops;
 			ops.ooblen = 8;
 			ops.datbuf = NULL;
diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
index dd6bacae34..6ff62dca6a 100644
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,4 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0
 
-spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o
+ifndef CONFIG_SPL_BUILD
+spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o broadcom.o
 obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
+else
+obj-$(CONFIG_MTD_SPI_NAND) += spinand_mini.o
+endif
diff --git a/drivers/mtd/nand/spi/broadcom.c b/drivers/mtd/nand/spi/broadcom.c
new file mode 100644
index 0000000000..e212669bbd
--- /dev/null
+++ b/drivers/mtd/nand/spi/broadcom.c
@@ -0,0 +1,1047 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Broadcom
+ *
+ * Author:
+ *	David Regan
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+
+#define FEATURE_STAT_ADDR   0xC0
+
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+
+///////////////////////////////////// toshiba device data /////////////////////////////////////
+
+#define SPINAND_MFR_TOSHIBA		0x98
+#define TOSHIBA_CFG_BUF_READ		BIT(3)
+
+
+static int toshibamicron_ooblayout_ecc(struct mtd_info *mtd, int section,
+				  struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	region->offset = 64;
+	region->length = 64;
+
+	return 0;
+}
+
+static int toshibamicron_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	// Reserve 2 bytes for the BBM.
+	region->offset = 2;
+	region->length = 62;
+
+	return 0;
+}
+
+static int toshiba_ooblayout_ecc(struct mtd_info *mtd, int section,
+				  struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	region->offset = 128;
+	region->length = 128;
+
+	return 0;
+}
+
+static int toshiba_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	// Reserve 2 bytes for the BBM.
+	region->offset = 2;
+	region->length = 126;
+
+	return 0;
+}
+
+
+
+static const struct mtd_ooblayout_ops toshibamicron_ooblayout =
+{
+	.ecc = toshibamicron_ooblayout_ecc,
+	.free = toshibamicron_ooblayout_free,
+};
+
+
+static const struct mtd_ooblayout_ops toshiba_ooblayout =
+{
+	.ecc = toshiba_ooblayout_ecc,
+	.free = toshiba_ooblayout_free,
+};
+
+
+static int select_target(struct spinand_device *spinand,
+				  unsigned int target)
+{
+	struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1),
+					  SPI_MEM_OP_NO_ADDR,
+					  SPI_MEM_OP_NO_DUMMY,
+					  SPI_MEM_OP_DATA_OUT(1,
+							spinand->scratchbuf,
+							1));
+
+	*spinand->scratchbuf = target;
+	return spi_mem_exec_op(spinand->slave, &op);
+}
+
+
+static const struct spinand_info toshiba_spinand_table[] =
+{
+	SPINAND_INFO("TC58CVG0S", 0xC2,
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&toshibamicron_ooblayout, NULL),
+		     SPINAND_SELECT_TARGET(select_target)),
+
+	SPINAND_INFO("TC58CVG1S", 0xCB,
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&toshibamicron_ooblayout, NULL),
+		     SPINAND_SELECT_TARGET(select_target)),
+
+	SPINAND_INFO("TC58CVG2S", 0xCD,
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&toshiba_ooblayout, NULL),
+		     SPINAND_SELECT_TARGET(select_target))
+};
+
+
+///////////////////////////////////// micron device data /////////////////////////////////////
+
+#define SPINAND_MFR_MICRON		0x2C
+
+#define MICRON_STATUS_ECC_MASK		GENMASK(7, 4)
+#define MICRON_STATUS_ECC_NO_BITFLIPS	(0 << 4)
+#define MICRON_STATUS_ECC_1TO3_BITFLIPS	(1 << 4)
+#define MICRON_STATUS_ECC_4TO6_BITFLIPS	(3 << 4)
+#define MICRON_STATUS_ECC_7TO8_BITFLIPS	(5 << 4)
+
+static int micron_ooblayout_ecc(struct mtd_info *mtd, int section,
+				  struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = (16 * section) + 8;
+	region->length = 8;
+
+	return 0;
+}
+
+static int micron_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	if (!section)
+	{
+		region->offset = 2;
+		region->length = 6;
+	}
+	else
+	{
+		region->offset = 16 * section;
+		region->length = 8;
+	}
+
+	return 0;
+}
+
+static int micron_ecc_get_status(struct spinand_device *spinand,
+					 u8 status)
+{
+	switch (status & MICRON_STATUS_ECC_MASK) {
+	case STATUS_ECC_NO_BITFLIPS:
+		return 0;
+
+	case STATUS_ECC_UNCOR_ERROR:
+		return -EBADMSG;
+
+	case MICRON_STATUS_ECC_1TO3_BITFLIPS:
+		return 3;
+
+	case MICRON_STATUS_ECC_4TO6_BITFLIPS:
+		return 6;
+
+	case MICRON_STATUS_ECC_7TO8_BITFLIPS:
+		return 8;
+
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static const struct mtd_ooblayout_ops micron_ooblayout =
+{
+	.ecc = micron_ooblayout_ecc,
+	.free = micron_ooblayout_free,
+};
+
+static const struct spinand_info micron_spinand_table[] =
+{
+	SPINAND_INFO("MT29F1G01AA", 0x12,
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&micron_ooblayout,
+				     micron_ecc_get_status)),
+
+	SPINAND_INFO("MT29F2G01AA", 0x22,
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), // bits_per_cell, pagesize, oobsize, pages_per_eraseblock, eraseblocks_per_lun, planes_per_lun, luns_per_target, ntargets	
+		     NAND_ECCREQ(8, 512), // strength, step_size (ecc per how many page bytes)
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&micron_ooblayout,
+				     micron_ecc_get_status)),
+
+	SPINAND_INFO("MT29F4G01AA", 0x32,
+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1), // bits_per_cell, pagesize, oobsize, pages_per_eraseblock, eraseblocks_per_lun, planes_per_lun, luns_per_target, ntargets	
+		     NAND_ECCREQ(8, 512), // strength, step_size (ecc per how many page bytes)
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&micron_ooblayout,
+				     micron_ecc_get_status)),
+
+	SPINAND_INFO("MT29F1G01A", 0x14,
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&toshibamicron_ooblayout,
+				     micron_ecc_get_status)),
+
+	SPINAND_INFO("MT29F2G01AB", 0x24,
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), // bits_per_cell, pagesize, oobsize, pages_per_eraseblock, eraseblocks_per_lun, planes_per_lun, luns_per_target, ntargets	
+		     NAND_ECCREQ(8, 512), // strength, step_size (ecc per how many page bytes)
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&toshibamicron_ooblayout,
+				     micron_ecc_get_status)),
+
+	SPINAND_INFO("MT29F4G01AB", 0x34,
+		     NAND_MEMORG(1, 4096, 128, 64, 2048, 1, 1, 1), // bits_per_cell, pagesize, oobsize, pages_per_eraseblock, eraseblocks_per_lun, planes_per_lun, luns_per_target, ntargets	
+		     NAND_ECCREQ(8, 512), // strength, step_size (ecc per how many page bytes)
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&toshibamicron_ooblayout,
+				     micron_ecc_get_status)),
+
+	SPINAND_INFO("MT29F4G01AD", 0x36,
+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1), // bits_per_cell, pagesize, oobsize, pages_per_eraseblock, eraseblocks_per_lun, planes_per_lun, luns_per_target, ntargets	
+		     NAND_ECCREQ(8, 512), // strength, step_size (ecc per how many page bytes)
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&toshibamicron_ooblayout,
+				     micron_ecc_get_status)),
+};
+
+///////////////////////////////////// winbond device data /////////////////////////////////////
+
+#define SPINAND_MFR_WINBOND		0xEF
+
+#define WINBOND_CFG_BUF_READ		BIT(3)
+
+static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
+				  struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = (16 * section) + 8;
+	region->length = 8;
+
+	return 0;
+}
+
+static int w25m02gv_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = (16 * section) + 2;
+	region->length = 6;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops w25m02gv_ooblayout = {
+	.ecc = w25m02gv_ooblayout_ecc,
+	.free = w25m02gv_ooblayout_free,
+};
+
+static const struct spinand_info winbond_spinand_table[] =
+{ // will need to fix this, Winbond actually uses two bytes to identify the device ID
+	SPINAND_INFO("W25M02GV", 0xAB,
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2),
+		     NAND_ECCREQ(1, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
+		     SPINAND_SELECT_TARGET(select_target)),
+	SPINAND_INFO("W25N01GV", 0xAA,
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(1, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
+};
+
+///////////////////////////////////// gigadevice device data /////////////////////////////////////
+
+#define SPINAND_MFR_GIGADEVICE_ESMT		0xC8
+#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS	(1 << 4)
+#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS	(3 << 4)
+
+#define GD5FXGQ4XEXXG_REG_STATUS2		0xf0
+
+
+static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section,
+				  struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = (16 * section) + 8;
+	region->length = 8;
+
+	return 0;
+}
+
+static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	if (section) {
+		region->offset = 16 * section;
+		region->length = 8;
+	} else {
+		/* section 0 has one byte reserved for bad block mark */
+		region->offset = 1;
+		region->length = 7;
+	}
+	return 0;
+}
+
+static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
+					 u8 status)
+{
+	switch (status & STATUS_ECC_MASK) {
+	case STATUS_ECC_NO_BITFLIPS:
+		return 0;
+
+	case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
+		/* 1-7 bits are flipped. return the maximum. */
+		return 7;
+
+	case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
+		return 8;
+
+	case STATUS_ECC_UNCOR_ERROR:
+		return -EBADMSG;
+
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static int gd5fxgq4xexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
+				       struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	region->offset = 64;
+	region->length = 64;
+
+	return 0;
+}
+
+static int gd5fxgq4xexxg_ooblayout_free(struct mtd_info *mtd, int section,
+					struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	/* Reserve 2 bytes for the BBM. */
+	region->offset = 2;
+	region->length = 62;
+
+	return 0;
+}
+
+static int gd5fxgq4xexxg2_ooblayout_ecc(struct mtd_info *mtd, int section,
+				       struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	region->offset = 128;
+	region->length = 128;
+
+	return 0;
+}
+
+static int gd5fxgq4xexxg2_ooblayout_free(struct mtd_info *mtd, int section,
+					struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	/* Reserve 2 bytes for the BBM. */
+	region->offset = 2;
+	region->length = 126;
+
+	return 0;
+}
+
+static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand,
+					u8 status)
+{
+	u8 status2;
+	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4XEXXG_REG_STATUS2,
+						      &status2);
+	int ret;
+
+	switch (status & STATUS_ECC_MASK) {
+	case STATUS_ECC_NO_BITFLIPS:
+		return 0;
+
+	case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
+		/*
+		 * Read status2 register to determine a more fine grained
+		 * bit error status
+		 */
+		ret = spi_mem_exec_op(spinand->slave, &op);
+		if (ret)
+			return ret;
+
+		/*
+		 * 4 ... 7 bits are flipped (1..4 can't be detected, so
+		 * report the maximum of 4 in this case
+		 */
+		/* bits sorted this way (3...0): ECCS1,ECCS0,ECCSE1,ECCSE0 */
+		return ((status & STATUS_ECC_MASK) >> 2) |
+			((status2 & STATUS_ECC_MASK) >> 4);
+
+	case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
+		return 8;
+
+	case STATUS_ECC_UNCOR_ERROR:
+		return -EBADMSG;
+
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout =
+{
+	.ecc = gd5fxgq4xa_ooblayout_ecc,
+	.free = gd5fxgq4xa_ooblayout_free,
+};
+
+static const struct mtd_ooblayout_ops gd5fxgq4xexxg_ooblayout =
+{
+	.ecc = gd5fxgq4xexxg_ooblayout_ecc,
+	.free = gd5fxgq4xexxg_ooblayout_free,
+};
+
+static const struct mtd_ooblayout_ops gd5fxgq4xexxg2_ooblayout =
+{
+	.ecc = gd5fxgq4xexxg2_ooblayout_ecc,
+	.free = gd5fxgq4xexxg2_ooblayout_free,
+};
+
+static const struct spinand_info gigadevice_spinand_table[] =
+{
+	SPINAND_INFO("GD5F1GQ4xA", 0xF1,
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
+				     gd5fxgq4xa_ecc_get_status)),
+	SPINAND_INFO("GD5F2GQ4xA", 0xF2,
+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
+				     gd5fxgq4xa_ecc_get_status)),
+	SPINAND_INFO("GD5F4GQ4xA", 0xF4,
+		     NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
+				     gd5fxgq4xa_ecc_get_status)),
+
+	SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), // bits_per_cell, pagesize, oobsize, pages_per_eraseblock, eraseblocks_per_lun, planes_per_lun, luns_per_target, ntargets	
+		     NAND_ECCREQ(8, 512), // strength, step_size (ecc per how many page bytes)
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout,
+				     gd5fxgq4xexxg_ecc_get_status)),
+
+	SPINAND_INFO("GD5F2GQ4UExxG", 0xd2,
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout,
+				     gd5fxgq4xexxg_ecc_get_status)),
+
+	SPINAND_INFO("GD5F4GQ4UExxG", 0xd4,
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&gd5fxgq4xexxg2_ooblayout,
+				     gd5fxgq4xexxg_ecc_get_status)),
+
+	SPINAND_INFO("GD5F4GQ6UExxG", 0x55,
+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout,
+				     gd5fxgq4xexxg_ecc_get_status)),
+};
+
+///////////////////////////////////// macronix device data /////////////////////////////////////
+
+#define SPINAND_MFR_MACRONIX		0xC2
+#define MACRONIX_ECCSR_MASK		0x0F
+
+static int mx35lfxge4ab_ooblayout_ecc(struct mtd_info *mtd, int section,
+				      struct mtd_oob_region *region)
+{
+	return -ERANGE;
+}
+
+static int mx35lfxge4ab_ooblayout_free(struct mtd_info *mtd, int section,
+				       struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	region->offset = 2;
+	region->length = mtd->oobsize - 2;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops mx35lfxge4ab_ooblayout = {
+	.ecc = mx35lfxge4ab_ooblayout_ecc,
+	.free = mx35lfxge4ab_ooblayout_free,
+};
+
+static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr)
+{
+	struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x7c, 1),
+					  SPI_MEM_OP_NO_ADDR,
+					  SPI_MEM_OP_DUMMY(1, 1),
+					  SPI_MEM_OP_DATA_IN(1, eccsr, 1));
+
+	int ret = spi_mem_exec_op(spinand->slave, &op);
+	if (ret)
+		return ret;
+
+	*eccsr &= MACRONIX_ECCSR_MASK;
+	return 0;
+}
+
+static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand,
+				       u8 status)
+{
+	struct nand_device *nand = spinand_to_nand(spinand);
+	u8 eccsr;
+
+	switch (status & STATUS_ECC_MASK) {
+	case STATUS_ECC_NO_BITFLIPS:
+		return 0;
+
+	case STATUS_ECC_UNCOR_ERROR:
+		return -EBADMSG;
+
+	case STATUS_ECC_HAS_BITFLIPS:
+		/*
+		 * Let's try to retrieve the real maximum number of bitflips
+		 * in order to avoid forcing the wear-leveling layer to move
+		 * data around if it's not necessary.
+		 */
+		if (mx35lf1ge4ab_get_eccsr(spinand, &eccsr))
+			return nand->eccreq.strength;
+
+		if (WARN_ON(eccsr > nand->eccreq.strength || !eccsr))
+			return nand->eccreq.strength;
+
+		return eccsr;
+
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static const struct spinand_info macronix_spinand_table[] = {
+	SPINAND_INFO("MX35LF1GE4AB", 0x12,
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
+				     mx35lf1ge4ab_ecc_get_status)),
+	SPINAND_INFO("MX35LF2GE4AB", 0x22,
+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
+};
+
+///////////////////////////////////// paragon device data /////////////////////////////////////
+
+#define SPINAND_MFR_PARAGON_FM	0xa1
+
+#define PN26G0XA_STATUS_ECC_BITMASK		(3 << 4)
+
+#define PN26G0XA_STATUS_ECC_NONE_DETECTED	(0 << 4)
+#define PN26G0XA_STATUS_ECC_1_7_CORRECTED	(1 << 4)
+#define PN26G0XA_STATUS_ECC_ERRORED		(2 << 4)
+#define PN26G0XA_STATUS_ECC_8_CORRECTED		(3 << 4)
+
+static int pn26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = 6 + (15 * section); /* 4 BBM + 2 user bytes */
+	region->length = 13;
+
+	return 0;
+}
+
+static int pn26g0xa_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 4)
+		return -ERANGE;
+
+	if (section == 4) {
+		region->offset = 64;
+		region->length = 64;
+	} else {
+		region->offset = 4 + (15 * section);
+		region->length = 2;
+	}
+
+	return 0;
+}
+
+static int pn26g0xa_ecc_get_status(struct spinand_device *spinand,
+				   u8 status)
+{
+	switch (status & PN26G0XA_STATUS_ECC_BITMASK) {
+	case PN26G0XA_STATUS_ECC_NONE_DETECTED:
+		return 0;
+
+	case PN26G0XA_STATUS_ECC_1_7_CORRECTED:
+		return 7;	/* Return upper limit by convention */
+
+	case PN26G0XA_STATUS_ECC_8_CORRECTED:
+		return 8;
+
+	case PN26G0XA_STATUS_ECC_ERRORED:
+		return -EBADMSG;
+
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static const struct mtd_ooblayout_ops pn26g0xa_ooblayout = {
+	.ecc = pn26g0xa_ooblayout_ecc,
+	.free = pn26g0xa_ooblayout_free,
+};
+
+
+static const struct spinand_info paragon_spinand_table[] = {
+	SPINAND_INFO("PN26G01A", 0xe1,
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&pn26g0xa_ooblayout,
+				     pn26g0xa_ecc_get_status)),
+	SPINAND_INFO("PN26G02A", 0xe2,
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&pn26g0xa_ooblayout,
+				     pn26g0xa_ecc_get_status)),
+};
+
+///////////////////////////////////// fm device data /////////////////////////////////////
+
+static int fm25s01_ooblayout_ecc(struct mtd_info *mtd, int section,
+				       struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	region->offset = 64;
+	region->length = 64;
+
+	return 0;
+}
+
+static int fm25s01_ooblayout_free(struct mtd_info *mtd, int section,
+					struct mtd_oob_region *region)
+{
+	if (section)
+		return -ERANGE;
+
+	/* Reserve 2 bytes for the BBM. */
+	region->offset = 2;
+	region->length = 62;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops fm25s01_ooblayout = {
+	.ecc = fm25s01_ooblayout_ecc,
+	.free = fm25s01_ooblayout_free,
+};
+
+static const struct spinand_info fm_spinand_table[] = {
+	SPINAND_INFO("FM25S01", 0xa1,
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(1, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&fm25s01_ooblayout, NULL)),
+	SPINAND_INFO("FM25S01A", 0xe4,
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(1, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&fm25s01_ooblayout, NULL)),
+};
+
+///////////////////////////////////// ESMT device data /////////////////////////////////////
+
+static int esmt_ooblayout_ecc(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = 16 * section;
+	region->length = 8;
+
+	if (section)
+	{
+		region->offset++;
+		region->length--;
+	}
+
+	return 0;
+}
+
+static int esmt_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = 8 + (16 * section);
+	region->length = 9;
+
+	if (section == 3)
+		region->length--;
+
+	return 0;
+}
+
+static int esmt2_ooblayout_ecc(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 4)
+		return -ERANGE;
+
+	if (!section)
+	{
+		region->offset = 0;
+		region->length = 2;
+	}
+	else
+	{
+		region->offset = 8 + (16 * (section - 1));
+		region->length = 10;
+
+		if (section == 4)
+			region->length -= 2;
+	}
+
+	return 0;
+}
+
+static int esmt2_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
+{
+	if (section > 3)
+		return -ERANGE;
+
+	region->offset = 2 + (16 * section);
+	region->length = 6;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops esmt_ooblayout = {
+	.ecc = esmt_ooblayout_ecc,
+	.free = esmt_ooblayout_free,
+};
+
+static const struct mtd_ooblayout_ops esmt2_ooblayout = {
+	.ecc = esmt2_ooblayout_ecc,
+	.free = esmt2_ooblayout_free,
+};
+
+static const struct spinand_info esmt_spinand_table[] = {
+	SPINAND_INFO("F50L1G41A", 0x21,
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(1, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&esmt_ooblayout, NULL)),
+	SPINAND_INFO("F50L1G41LB", 0x01,
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+		     NAND_ECCREQ(1, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&esmt2_ooblayout, NULL)),
+	SPINAND_INFO("F50L2G41LB", 0x0a,
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2),
+		     NAND_ECCREQ(1, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&esmt2_ooblayout, NULL),
+		     SPINAND_SELECT_TARGET(select_target)),
+};
+
+
+///////////////////////////////////// APIs /////////////////////////////////////
+
+
+/**
+ * spinand_detect - initialize device related part in spinand_device struct
+ * @spinand: SPI NAND device structure
+ */
+
+#define SPINAND_GENERIC_OP(out, in, buf)					\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(buf[0], 1),				\
+		   SPI_MEM_OP_ADDR(out - 1, buf[1], 1),			\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_IN(in, buf, 1))
+
+static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
+{ // this is not defined correctly in core.c, should be one dummy byte
+	//struct spi_mem_op op = SPINAND_READID_OP(1, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
+	buf[0] = 0x9F;
+	buf[1] = 0;
+	struct spi_mem_op op = SPINAND_GENERIC_OP(2, 4, buf);
+
+	int ret, i;
+
+	ret = spi_mem_exec_op(spinand->slave, &op);
+
+	printf("SPINAND ID");
+	for (i = 0; i < SPINAND_MAX_ID_LEN; i++)
+		printf(" 0x%x", buf[i]);
+	printf("\n");
+
+	return ret;
+}
+
+
+static int spinand_detect(struct spinand_device *spinand)
+{
+	u8 *id = spinand->id.data;
+	int ret;
+
+	ret = spinand_read_id_op(spinand, spinand->id.data);
+	if (ret)
+		return ret;
+
+
+	/*
+	 * SPI NAND is now probed correctly issuing dummy byte of value 0
+	 */
+
+	if (id[0] == SPINAND_MFR_TOSHIBA)
+	{
+		ret = spinand_match_and_init(spinand, toshiba_spinand_table, ARRAY_SIZE(toshiba_spinand_table), id[1]);
+	}
+	else if (id[0] == SPINAND_MFR_MICRON)
+	{
+		ret = spinand_match_and_init(spinand, micron_spinand_table, ARRAY_SIZE(micron_spinand_table), id[1]);
+	}
+	else if (id[0] == SPINAND_MFR_WINBOND)
+	{
+		ret = spinand_match_and_init(spinand, winbond_spinand_table, ARRAY_SIZE(winbond_spinand_table), id[1]);
+	}
+	else if (id[0] == SPINAND_MFR_MACRONIX)
+	{
+		ret = spinand_match_and_init(spinand, macronix_spinand_table, ARRAY_SIZE(macronix_spinand_table), id[1]);
+	}
+	else if (id[0] == SPINAND_MFR_PARAGON_FM)
+	{
+		if ((ret = spinand_match_and_init(spinand, paragon_spinand_table, ARRAY_SIZE(paragon_spinand_table), id[1])) < 0)
+			ret = spinand_match_and_init(spinand, fm_spinand_table, ARRAY_SIZE(fm_spinand_table), id[1]);
+	}
+	else if (id[0] == SPINAND_MFR_GIGADEVICE_ESMT)
+	{
+		if ((ret = spinand_match_and_init(spinand, esmt_spinand_table, ARRAY_SIZE(esmt_spinand_table), id[1])) < 0)
+			ret = spinand_match_and_init(spinand, gigadevice_spinand_table, ARRAY_SIZE(gigadevice_spinand_table), id[1]);
+	}
+	else if (id[1] == SPINAND_MFR_GIGADEVICE_ESMT)
+	{ // this is a hack for Gigadevice until they can get their act together, check this one last
+		ret = spinand_match_and_init(spinand, gigadevice_spinand_table, ARRAY_SIZE(gigadevice_spinand_table), id[0]);
+	}
+	else
+		printf("SPI NAND NOT FOUND!!!!!\n");
+
+	if (ret)
+			return ret;
+
+	return 1;
+}
+
+static const struct spinand_manufacturer_ops spinand_manuf_ops = {
+	.detect = spinand_detect,
+	.init = NULL,
+};
+
+const struct spinand_manufacturer broadcom_spinand_manufacturer = {
+	.id = 0,
+	.name = "Broadcom",
+	.ops = &spinand_manuf_ops,
+};
+
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index cb8ffa3fa9..5e38211333 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -315,24 +315,30 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
 	struct nand_device *nand = spinand_to_nand(spinand);
 	struct mtd_info *mtd = nanddev_to_mtd(nand);
 	struct nand_page_io_req adjreq = *req;
-	unsigned int nbytes = 0;
-	void *buf = NULL;
+	void *buf = spinand->databuf;
+	unsigned int nbytes;
 	u16 column = 0;
 	int ret;
 
-	memset(spinand->databuf, 0xff,
-	       nanddev_page_size(nand) +
-	       nanddev_per_page_oobsize(nand));
+	/*
+	 * Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
+	 * the cache content to 0xFF (depends on vendor implementation), so we
+	 * must fill the page cache entirely even if we only want to program
+	 * the data portion of the page, otherwise we might corrupt the BBM or
+	 * user data previously programmed in OOB area.
+	 */
+	nbytes = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
+	memset(spinand->databuf, 0xff, nbytes);
+	adjreq.dataoffs = 0;
+	adjreq.datalen = nanddev_page_size(nand);
+	adjreq.databuf.out = spinand->databuf;
+	adjreq.ooblen = nanddev_per_page_oobsize(nand);
+	adjreq.ooboffs = 0;
+	adjreq.oobbuf.out = spinand->oobbuf;
 
-	if (req->datalen) {
+	if (req->datalen)
 		memcpy(spinand->databuf + req->dataoffs, req->databuf.out,
 		       req->datalen);
-		adjreq.dataoffs = 0;
-		adjreq.datalen = nanddev_page_size(nand);
-		adjreq.databuf.out = spinand->databuf;
-		nbytes = adjreq.datalen;
-		buf = spinand->databuf;
-	}
 
 	if (req->ooblen) {
 		if (req->mode == MTD_OPS_AUTO_OOB)
@@ -343,14 +349,6 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
 		else
 			memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out,
 			       req->ooblen);
-
-		adjreq.ooblen = nanddev_per_page_oobsize(nand);
-		adjreq.ooboffs = 0;
-		nbytes += nanddev_per_page_oobsize(nand);
-		if (!buf) {
-			buf = spinand->oobbuf;
-			column = nanddev_page_size(nand);
-		}
 	}
 
 	spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
@@ -381,8 +379,8 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
 
 		/*
 		 * We need to use the RANDOM LOAD CACHE operation if there's
-		 * more than one iteration, because the LOAD operation resets
-		 * the cache to 0xff.
+		 * more than one iteration, because the LOAD operation might
+		 * reset the cache to 0xff.
 		 */
 		if (nbytes) {
 			column = op.addr.val;
@@ -589,12 +587,12 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
 		if (ret == -EBADMSG) {
 			ecc_failed = true;
 			mtd->ecc_stats.failed++;
-			ret = 0;
 		} else {
 			mtd->ecc_stats.corrected += ret;
 			max_bitflips = max_t(unsigned int, max_bitflips, ret);
 		}
 
+		ret = 0;
 		ops->retlen += iter.req.datalen;
 		ops->oobretlen += iter.req.ooblen;
 	}
@@ -651,16 +649,16 @@ static int spinand_mtd_write(struct mtd_info *mtd, loff_t to,
 static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
 {
 	struct spinand_device *spinand = nand_to_spinand(nand);
+	u8 marker[2] = { };
 	struct nand_page_io_req req = {
 		.pos = *pos,
-		.ooblen = 2,
+		.ooblen = sizeof(marker),
 		.ooboffs = 0,
-		.oobbuf.in = spinand->oobbuf,
+		.oobbuf.in = marker,
 		.mode = MTD_OPS_RAW,
 	};
 	int ret;
 
-	memset(spinand->oobbuf, 0, 2);
 	ret = spinand_select_target(spinand, pos->target);
 	if (ret)
 		return ret;
@@ -669,7 +667,7 @@ static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
 	if (ret)
 		return ret;
 
-	if (spinand->oobbuf[0] != 0xff || spinand->oobbuf[1] != 0xff)
+	if (hweight8(marker[0]) < 4)
 		return true;
 
 	return false;
@@ -698,11 +696,13 @@ static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs)
 static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos)
 {
 	struct spinand_device *spinand = nand_to_spinand(nand);
+	u8 marker[2] = {0,0};
 	struct nand_page_io_req req = {
 		.pos = *pos,
 		.ooboffs = 0,
-		.ooblen = 2,
-		.oobbuf.out = spinand->oobbuf,
+		.ooblen = sizeof(marker),
+		.oobbuf.out = marker,
+		.mode = MTD_OPS_RAW,
 	};
 	int ret;
 
@@ -715,11 +715,6 @@ static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos)
 	if (ret)
 		return ret;
 
-	ret = spinand_erase_op(spinand, pos);
-	if (ret)
-		return ret;
-
-	memset(spinand->oobbuf, 0, 2);
 	return spinand_write_page(spinand, &req);
 }
 
@@ -830,6 +825,7 @@ static const struct nand_ops spinand_ops = {
 };
 
 static const struct spinand_manufacturer *spinand_manufacturers[] = {
+	&broadcom_spinand_manufacturer,
 	&gigadevice_spinand_manufacturer,
 	&macronix_spinand_manufacturer,
 	&micron_spinand_manufacturer,
diff --git a/drivers/mtd/nand/spi/spinand_mini.c b/drivers/mtd/nand/spi/spinand_mini.c
new file mode 100644
index 0000000000..ebb958364d
--- /dev/null
+++ b/drivers/mtd/nand/spi/spinand_mini.c
@@ -0,0 +1,656 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Broadcom Ltd.
+ * Copyright (C) 2016-2017 Micron Technology, Inc.
+ *
+ * Authors:
+ *	Peter Pan <peterpandong@micron.com>
+ *	Boris Brezillon <boris.brezillon@bootlin.com>
+ */
+#include <common.h>
+#include <errno.h>
+
+#include <linux/mtd/spinand_mini.h>
+
+static struct spinandmini_device *spinand = NULL;
+
+static const struct spinandmini_info spinand_chip_table[] = {
+	{
+		/* TC58CVG0S */
+		{SPINAND_MFR_TOSHIBA, 0xC2}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* TC58CVG1S */
+		{SPINAND_MFR_TOSHIBA, 0xCB}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1)
+	},
+	{
+		/* TC58CVG2S */
+		{SPINAND_MFR_TOSHIBA, 0xCD}, 2,
+		SPINANDMINI_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1)
+	},
+	{
+		/* MT29F1G01AA */
+		{SPINAND_MFR_MICRON, 0x12}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* MT29F2G01AA */
+		{SPINAND_MFR_MICRON, 0x22}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1)
+	},
+	{
+		/* MT29F4G01AA */
+		{SPINAND_MFR_MICRON, 0x32}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1)
+	},
+	{
+		/* MT29F1G01A */
+		{SPINAND_MFR_MICRON, 0x14}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* MT29F2G01B */
+		{SPINAND_MFR_MICRON, 0x24}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1)
+	},
+	{
+		/* MT29F4G01AB */
+		{SPINAND_MFR_MICRON, 0x34}, 2,
+		SPINANDMINI_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1)
+	},
+	{
+		/* MT29F4G01AD */
+		{SPINAND_MFR_MICRON, 0x36}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2)
+	},
+	{
+		/* W25M02GV */
+		{SPINAND_MFR_WINBOND, 0xAB}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2)
+	},
+	{
+		/* W25N01GV */
+		{SPINAND_MFR_WINBOND, 0xAA}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* MX35LF1GE4AB */
+		{SPINAND_MFR_MACRONIX, 0x12}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* MX35LF2GE4AB */
+		{SPINAND_MFR_MACRONIX, 0x22}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1)
+	},
+	{
+		/* PN26G01A */
+		{SPINAND_MFR_PARAGON, 0xE1}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* PN26G02A */
+		{SPINAND_MFR_PARAGON, 0xE2}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1)
+	},
+	{
+		/* F50L1G41A */
+		{SPINAND_MFR_GIGADEVICE_ESMT, 0x21}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* F50L1G41LB */
+		{SPINAND_MFR_GIGADEVICE_ESMT, 0x01}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* F50L2G41LB */
+		{SPINAND_MFR_GIGADEVICE_ESMT, 0x0A}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2)
+	},
+	{
+		/* GD5F1GQ4xA */
+		{SPINAND_MFR_GIGADEVICE_ESMT, 0xF1}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* GD5F2GQ4xA */
+		{SPINAND_MFR_GIGADEVICE_ESMT, 0xF2}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1)
+	},
+	{
+		/* GD5F4GQ4xA */
+		{SPINAND_MFR_GIGADEVICE_ESMT, 0xF4}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1)
+	},
+	{
+		/* GD5F4GQ4UExxG */
+		{SPINAND_MFR_GIGADEVICE_ESMT, 0xD4}, 2,
+		SPINANDMINI_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1)
+	},
+	{
+		/* GD5F2GQ4UExxG */
+		{SPINAND_MFR_GIGADEVICE_ESMT, 0xD2}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1)
+	},
+	{
+		/* GD5F1GQ4UExxG */
+		{SPINAND_MFR_GIGADEVICE_ESMT, 0xD1}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* GD5F4GQ6UExxG */
+		{SPINAND_MFR_GIGADEVICE_ESMT, 0x55}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1)
+	},
+	{
+		/* GD5F1GQ4UFxxG */
+		{SPINAND_MFR_GIGADEVICE_ESMT, 0xB1, 0x48}, 3,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* FM25S01 */
+		{SPINAND_MFR_PARAGON, 0xA1}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* FM25S01A*/
+		{SPINAND_MFR_PARAGON, 0xE4}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1)
+	},
+	{
+		/* Unknonw, must be last entry*/
+		{0x0, 0x0}, 2,
+		SPINANDMINI_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1)
+	},
+
+};
+
+static int spinandchip_select_target(struct spinandmini_device *spinand,
+				  unsigned int target)
+{
+	u32 buf = target;  
+	struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1),
+					  SPI_MEM_OP_NO_ADDR,
+					  SPI_MEM_OP_NO_DUMMY,
+					  SPI_MEM_OP_DATA_OUT(1,
+							&buf,
+							1));
+
+	return spi_mem_exec_op(spinand->slave, &op);
+}
+
+static int spinandmini_read_reg_op(struct spinandmini_device *spinand, u8 reg, u8 *val)
+{
+	u8 feature = 0;
+	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg, &feature);
+	int ret;
+
+	ret = spi_mem_exec_op(spinand->slave, &op);
+	if (ret)
+		return ret;
+
+	*val = feature;
+	return 0;
+}
+
+static int spinandmini_write_reg_op(struct spinandmini_device *spinand, u8 reg, u8 val)
+{
+	struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg, &val);
+
+	return spi_mem_exec_op(spinand->slave, &op);
+}
+
+static int spinandmini_read_status(struct spinandmini_device *spinand, u8 *status)
+{
+	return spinandmini_read_reg_op(spinand, REG_STATUS, status);
+}
+
+static int spinandmini_get_cfg(struct spinandmini_device *spinand, u8 *cfg)
+{
+	if (WARN_ON(spinand->cur_target < 0 ||
+		    spinand->cur_target >= spinand->memorg->ntargets))
+		return -EINVAL;
+
+	*cfg = spinand->cfg_cache[spinand->cur_target];
+	return 0;
+}
+
+static int spinandmini_set_cfg(struct spinandmini_device *spinand, u8 cfg)
+{
+	int ret;
+
+	if (WARN_ON(spinand->cur_target < 0 ||
+		    spinand->cur_target >= spinand->memorg->ntargets))
+		return -EINVAL;
+
+	if (spinand->cfg_cache[spinand->cur_target] == cfg)
+		return 0;
+
+	ret = spinandmini_write_reg_op(spinand, REG_CFG, cfg);
+	if (ret)
+		return ret;
+
+	spinand->cfg_cache[spinand->cur_target] = cfg;
+	return 0;
+}
+
+static int spinandmini_upd_cfg(struct spinandmini_device *spinand, u8 mask, u8 val)
+{
+	int ret;
+	u8 cfg;
+
+	ret = spinandmini_get_cfg(spinand, &cfg);
+	if (ret)
+		return ret;
+
+	cfg &= ~mask;
+	cfg |= val;
+
+	return spinandmini_set_cfg(spinand, cfg);
+}
+
+static int spinandmini_ecc_enable(struct spinandmini_device *spinand,
+			      bool enable)
+{
+	return spinandmini_upd_cfg(spinand, CFG_ECC_ENABLE,
+			       enable ? CFG_ECC_ENABLE : 0);
+}
+
+static int spinandmini_load_page_op(struct spinandmini_device *spinand,
+				u64 page_addr)
+{
+	unsigned int row = page_addr >> spinand->page_shift;
+	struct spi_mem_op op = SPINAND_PAGE_READ_OP(row);
+
+	return spi_mem_exec_op(spinand->slave, &op);
+}
+
+static int spinandmini_read_from_cache_op(struct spinandmini_device *spinand,
+				      u64 page_addr, u32 page_offset,
+				      u8* buf, u32 len)
+{
+	struct spi_mem_op op =
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0);
+	u16 column = page_offset;
+	int ret;
+
+	//TODO plane bit at bit 12 or right above column MSB bit?? 
+	column |= ((page_addr >> spinand->block_shift) % spinand->memorg->planes_per_lun)<<12;
+	op.addr.val = column;
+
+	/*
+	 * Some controllers are limited in term of max RX data size. In this
+	 * case, just repeat the READ_CACHE operation after updating the
+	 * column.
+	 */
+	while (len) {
+		op.data.buf.in = buf;
+		op.data.nbytes = len;
+		ret = spi_mem_adjust_op_size(spinand->slave, &op);
+		if (ret)
+			return ret;
+
+		ret = spi_mem_exec_op(spinand->slave, &op);
+		if (ret)
+			return ret;
+
+		buf += op.data.nbytes;
+		len -= op.data.nbytes;
+		op.addr.val += op.data.nbytes;
+	}
+
+	return 0;
+}
+
+static int spinandmini_wait(struct spinandmini_device *spinand, u8 *s)
+{
+	unsigned long start, stop;
+	u8 status;
+	int ret;
+
+	start = get_timer(0);
+	stop = 400;
+	do {
+		ret = spinandmini_read_status(spinand, &status);
+		if (ret)
+			return ret;
+
+		if (!(status & STATUS_BUSY))
+			goto out;
+	} while (get_timer(start) < stop);
+
+	/*
+	 * Extra read, just in case the STATUS_READY bit has changed
+	 * since our last check
+	 */
+	ret = spinandmini_read_status(spinand, &status);
+	if (ret)
+		return ret;
+
+out:
+	if (s)
+		*s = status;
+
+	return status & STATUS_BUSY ? -ETIMEDOUT : 0;
+}
+
+static int spinandmini_read_id_op(struct spinandmini_device *spinand)
+{
+	/* looks most of the chhip use the op + addr method to detect id. 
+	 * TODO: Add parameter to this function to support op+dummy or op only 
+ 	*/
+	struct spi_mem_op op = SPINAND_READID_OP_ADDR(spinand->id.data,
+						 SPINAND_MAX_ID_LEN);
+
+	return spi_mem_exec_op(spinand->slave, &op);
+}
+
+static int spinandmini_reset_op(struct spinandmini_device *spinand)
+{
+	struct spi_mem_op op = SPINAND_RESET_OP;
+	int ret;
+
+	ret = spi_mem_exec_op(spinand->slave, &op);
+	if (ret)
+		return ret;
+
+	return spinandmini_wait(spinand, NULL);
+}
+
+static int spinandmini_lock_block(struct spinandmini_device *spinand, u8 lock)
+{
+	return spinandmini_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
+}
+
+static int spinandmini_select_target(struct spinandmini_device *spinand, unsigned int target)
+{
+	int ret;
+
+	if (WARN_ON(target >= spinand->memorg->ntargets))
+		return -EINVAL;
+
+	if (spinand->cur_target == target)
+		return 0;
+
+	if (spinand->memorg->ntargets == 1) {
+		spinand->cur_target = target;
+		return 0;
+	}
+
+	ret = spinand->select_target(spinand, target);
+	if (ret)
+		return ret;
+
+	spinand->cur_target = target;
+	return 0;
+}
+
+
+static int spinandmini_read_page(struct spinandmini_device *spinand,
+				      u64 page_addr, u32 page_offset,
+			 	      u8* buf, u32 len)
+{
+	u8 status;
+	int ret = 0;
+
+	ret = spinandmini_load_page_op(spinand, page_addr);
+	if (ret)
+		return ret;
+
+	ret = spinandmini_wait(spinand, &status);
+	if (ret < 0)
+		return ret;
+
+	ret = spinandmini_read_from_cache_op(spinand, page_addr, page_offset,
+					 buf, len);
+	return ret;
+}
+
+int spinandmini_read_buf(int blk, int offset, u8 *buffer, u32 len)
+{
+	int ret = 0, target = 0, readlen = len;
+	u64 addr, page_addr, page_boundary;
+	u32 page_offset;
+	u32 size;	
+
+	addr = (blk * spinand->block_size) + offset;
+	page_addr = addr & ~(spinand->page_size - 1);
+	page_offset = addr - page_addr;
+	page_boundary = page_addr + spinand->page_size;
+
+	size = page_boundary - addr;
+	if(size > len)
+		size = len;
+
+	while (len) {
+		target = page_addr >> spinand->target_shift;
+		ret = spinandmini_select_target(spinand, target);
+		if (ret)
+			break;
+
+		ret = spinandmini_ecc_enable(spinand, true);
+		if (ret)
+			break;
+
+		ret = spinandmini_read_page(spinand, page_addr, page_offset,
+			buffer, size);
+		if (ret)
+			break;
+
+		len -= size;
+		if (len) {
+			page_addr += spinand->page_size;
+			page_offset = 0;
+			buffer += size;
+			if(len > spinand->page_size)
+				size = spinand->page_size;
+			else
+				size = len;
+		}
+	}
+
+	return ret ? ret : readlen;
+}
+
+int spinandmini_is_bad_block(int blk)
+{
+	u8 oobbuf = 0;
+	u64 addr = (blk * spinand->block_size);
+	int target = addr >> spinand->target_shift;
+	int ret = 0;
+	
+	ret = spinandmini_select_target(spinand, target);
+	if (ret)
+		return 1;
+
+	ret = spinandmini_ecc_enable(spinand, false);
+	if (ret)
+		return 1;
+
+	ret = spinandmini_read_page(spinand, addr, spinand->page_size,
+		&oobbuf, 1);
+	if (ret)
+		return 1;
+
+	if (hweight8(oobbuf) < 4)
+		return 1;
+
+	return 0;
+}
+
+static void spinandmini_print_id(struct spinandmini_device *spinand)
+{
+	int i;
+	for (i = 0; i < spinand->id.len; i++)
+		printf("0x%02x ", spinand->id.data[i]);
+	printf("\n");
+}
+
+static int spinandmini_detect(struct spinandmini_device *spinand)
+{
+	int ret, i, tbl_size;
+	const struct spinandmini_info* spinand_info;
+	const struct spinandmini_mem_org* memorg;
+	u64 target_size;
+	
+	ret = spinandmini_reset_op(spinand);
+	if (ret)
+		return ret;
+
+	ret = spinandmini_read_id_op(spinand);
+	if (ret)
+		return ret;
+
+	tbl_size = sizeof(spinand_chip_table)/sizeof(struct spinandmini_info);
+	
+	for (i = 0; i < tbl_size; i++) {
+		spinand_info = &spinand_chip_table[i];
+		if (!memcmp(spinand_info->id, spinand->id.data, spinand_info->id_len))
+			break;
+	}
+	
+	if ( i == tbl_size) {
+		printf("unknown ID, use default setting\n");
+	}
+	memorg = spinand->memorg = &spinand_info->memorg;
+	spinand->id.len = spinand_info->id_len;
+	
+	spinand->page_size = memorg->pagesize;
+	spinand->page_shift = fls(spinand->page_size-1);
+	
+	spinand->block_size =
+		spinand->page_size * memorg->pages_per_eraseblock;
+	spinand->block_shift = fls(spinand->block_size-1);
+
+	target_size = spinand->block_size *
+		memorg->eraseblocks_per_lun *
+		memorg->luns_per_target;
+	spinand->target_shift = fls(target_size-1);
+	
+	spinand->total_size = target_size * memorg->ntargets;
+
+	spinand->select_target = spinandchip_select_target;
+	
+	if (spinand->memorg->ntargets > 1 && !spinand->select_target) {
+		return -EINVAL;
+	}
+
+	printf("SPI NAND ID: ");
+	spinandmini_print_id(spinand);
+	printf("%llu MiB, block size: %u KiB, page size: %u\n",
+		spinand->total_size>>20, spinand->block_size>>10, spinand->page_size);
+
+	return 0;
+}
+
+static int spinandmini_init_cfg_cache(struct spinandmini_device *spinand)
+{
+	unsigned int target;
+	int ret;
+
+	spinand->cfg_cache = malloc(sizeof(*spinand->cfg_cache) *
+				    spinand->memorg->ntargets);
+
+	if (!spinand->cfg_cache)
+		return -ENOMEM;
+
+	for (target = 0; target < spinand->memorg->ntargets; target++) {
+		ret = spinandmini_select_target(spinand, target);
+		if (ret)
+			return ret;
+
+		/*
+		 * We use spinand_read_reg_op() instead of spinand_get_cfg()
+		 * here to bypass the config cache.
+		 */
+		ret = spinandmini_read_reg_op(spinand, REG_CFG,
+					  &spinand->cfg_cache[target]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int spinandmini_initdev(struct spinandmini_device *spinand)
+{
+	int ret = 0, i;
+
+	ret = spinandmini_detect(spinand);
+	if (ret)
+		return ret;
+
+	ret = spinandmini_init_cfg_cache(spinand);
+	if (ret)
+		return ret;
+
+	/* After power up, all blocks are locked, so unlock them here. */
+	for (i = 0; i < spinand->memorg->ntargets; i++) {
+		ret = spinandmini_select_target(spinand, i);
+		if (ret)
+			break;
+
+		ret = spinandmini_lock_block(spinand, BL_ALL_UNLOCKED);
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+
+static int spinandmini_probe(struct udevice *dev)
+{
+	struct spinandmini_device *spinand_dev = dev_get_priv(dev);
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+
+	spinand = spinand_dev;
+	spinand->slave = slave;
+	
+	return spinandmini_initdev(spinand);
+}
+
+void spinandmini_init(void)
+{
+	struct udevice *dev;
+	int ret = -1;
+
+	ret = uclass_get_device_by_driver(UCLASS_MTD, DM_GET_DRIVER(spinand),
+		  &dev);
+	if (ret){
+		printf("SPI NAND failed to initialize. (error %d)\n", ret);
+		hang();
+	}
+
+	return;
+}
+
+u32 spinandmini_get_block_size(void)
+{
+	return spinand->block_size;
+}
+
+u32 spinandmini_get_page_size(void)
+{
+	return spinand->page_size;
+}
+
+u64 spinandmini_get_total_size(void)
+{
+	return spinand->total_size;  
+}
+
+static const struct udevice_id spinand_ids[] = {
+	{ .compatible = "spi-nand" },
+	{ /* sentinel */ },
+};
+
+U_BOOT_DRIVER(spinand) = {
+	.name = "spi_nand",
+	.id = UCLASS_MTD,
+	.of_match = spinand_ids,
+	.priv_auto_alloc_size = sizeof(struct spinandmini_device),
+	.probe = spinandmini_probe,
+};
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 2b17eae947..a78fd51ba7 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -1,6 +1,6 @@
 menu "UBI support"
 
-config CONFIG_UBI_SILENCE_MSG
+config UBI_SILENCE_MSG
 	bool "UBI silence verbose messages"
 	default ENV_IS_IN_UBI
 	help
diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
index 8ef7823b37..284f252235 100644
--- a/drivers/mtd/ubi/io.c
+++ b/drivers/mtd/ubi/io.c
@@ -1342,9 +1342,7 @@ static int self_check_write(struct ubi_device *ubi, const void *buf, int pnum,
 	for (i = 0; i < len; i++) {
 		uint8_t c = ((uint8_t *)buf)[i];
 		uint8_t c1 = ((uint8_t *)buf1)[i];
-#if !defined(CONFIG_UBI_SILENCE_MSG)
 		int dump_len = max_t(int, 128, len - i);
-#endif
 
 		if (c == c1)
 			continue;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index e6a4fdf30e..4c0e0d4808 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -65,7 +65,7 @@ config BCM_SF2_ETH_DEFAULT_PORT
 
 config BCM_SF2_ETH_GMAC
 	bool "Broadcom SF2 (Starfighter2) GMAC Ethernet support"
-	depends on BCM_SF2_ETH
+	depends on DM_ETH
 	help
 	  This flag enables the ethernet support for Broadcom platforms with
 	  GMAC such as Cygnus. This driver is based on the framework provided
@@ -90,6 +90,8 @@ config BCM6368_ETH
 	help
 	  This driver supports the BCM6368 Ethernet MAC.
 
+source "drivers/net/bcmbca/Kconfig"
+
 config DWC_ETH_QOS
 	bool "Synopsys DWC Ethernet QOS device support"
 	depends on DM_ETH
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 8d02a37896..0c0e80b437 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -10,8 +10,6 @@ obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o
 obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o
 obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
 obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
-obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
-obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
 obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
 obj-$(CONFIG_CS8900) += cs8900.o
 obj-$(CONFIG_TULIP) += dc2114x.o
@@ -77,3 +75,5 @@ obj-y += ti/
 obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
 obj-y += mscc_eswitch/
 obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
+obj-$(CONFIG_ARCH_BCMBCA) += bcmbca/
+
diff --git a/drivers/net/bcm-sf2-eth-gmac.c b/drivers/net/bcm-sf2-eth-gmac.c
deleted file mode 100644
index db3e79ade3..0000000000
--- a/drivers/net/bcm-sf2-eth-gmac.c
+++ /dev/null
@@ -1,971 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014-2017 Broadcom.
- */
-
-#ifdef BCM_GMAC_DEBUG
-#ifndef DEBUG
-#define DEBUG
-#endif
-#endif
-
-#include <config.h>
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <phy.h>
-
-#include "bcm-sf2-eth.h"
-#include "bcm-sf2-eth-gmac.h"
-
-#define SPINWAIT(exp, us) { \
-	uint countdown = (us) + 9; \
-	while ((exp) && (countdown >= 10)) {\
-		udelay(10); \
-		countdown -= 10; \
-	} \
-}
-
-#define RX_BUF_SIZE_ALIGNED	ALIGN(RX_BUF_SIZE, ARCH_DMA_MINALIGN)
-#define TX_BUF_SIZE_ALIGNED	ALIGN(TX_BUF_SIZE, ARCH_DMA_MINALIGN)
-#define DESCP_SIZE_ALIGNED	ALIGN(sizeof(dma64dd_t), ARCH_DMA_MINALIGN)
-
-static int gmac_disable_dma(struct eth_dma *dma, int dir);
-static int gmac_enable_dma(struct eth_dma *dma, int dir);
-
-/* DMA Descriptor */
-typedef struct {
-	/* misc control bits */
-	uint32_t	ctrl1;
-	/* buffer count and address extension */
-	uint32_t	ctrl2;
-	/* memory address of the date buffer, bits 31:0 */
-	uint32_t	addrlow;
-	/* memory address of the date buffer, bits 63:32 */
-	uint32_t	addrhigh;
-} dma64dd_t;
-
-uint32_t g_dmactrlflags;
-
-static uint32_t dma_ctrlflags(uint32_t mask, uint32_t flags)
-{
-	debug("%s enter\n", __func__);
-
-	g_dmactrlflags &= ~mask;
-	g_dmactrlflags |= flags;
-
-	/* If trying to enable parity, check if parity is actually supported */
-	if (g_dmactrlflags & DMA_CTRL_PEN) {
-		uint32_t control;
-
-		control = readl(GMAC0_DMA_TX_CTRL_ADDR);
-		writel(control | D64_XC_PD, GMAC0_DMA_TX_CTRL_ADDR);
-		if (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) {
-			/*
-			 * We *can* disable it, therefore it is supported;
-			 * restore control register
-			 */
-			writel(control, GMAC0_DMA_TX_CTRL_ADDR);
-		} else {
-			/* Not supported, don't allow it to be enabled */
-			g_dmactrlflags &= ~DMA_CTRL_PEN;
-		}
-	}
-
-	return g_dmactrlflags;
-}
-
-static inline void reg32_clear_bits(uint32_t reg, uint32_t value)
-{
-	uint32_t v = readl(reg);
-	v &= ~(value);
-	writel(v, reg);
-}
-
-static inline void reg32_set_bits(uint32_t reg, uint32_t value)
-{
-	uint32_t v = readl(reg);
-	v |= value;
-	writel(v, reg);
-}
-
-#ifdef BCM_GMAC_DEBUG
-static void dma_tx_dump(struct eth_dma *dma)
-{
-	dma64dd_t *descp = NULL;
-	uint8_t *bufp;
-	int i;
-
-	printf("TX DMA Register:\n");
-	printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n",
-	       readl(GMAC0_DMA_TX_CTRL_ADDR),
-	       readl(GMAC0_DMA_TX_PTR_ADDR),
-	       readl(GMAC0_DMA_TX_ADDR_LOW_ADDR),
-	       readl(GMAC0_DMA_TX_ADDR_HIGH_ADDR),
-	       readl(GMAC0_DMA_TX_STATUS0_ADDR),
-	       readl(GMAC0_DMA_TX_STATUS1_ADDR));
-
-	printf("TX Descriptors:\n");
-	for (i = 0; i < TX_BUF_NUM; i++) {
-		descp = (dma64dd_t *)(dma->tx_desc_aligned) + i;
-		printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n",
-		       descp->ctrl1, descp->ctrl2,
-		       descp->addrhigh, descp->addrlow);
-	}
-
-	printf("TX Buffers:\n");
-	/* Initialize TX DMA descriptor table */
-	for (i = 0; i < TX_BUF_NUM; i++) {
-		bufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE_ALIGNED);
-		printf("buf%d:0x%x; ", i, (uint32_t)bufp);
-	}
-	printf("\n");
-}
-
-static void dma_rx_dump(struct eth_dma *dma)
-{
-	dma64dd_t *descp = NULL;
-	uint8_t *bufp;
-	int i;
-
-	printf("RX DMA Register:\n");
-	printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n",
-	       readl(GMAC0_DMA_RX_CTRL_ADDR),
-	       readl(GMAC0_DMA_RX_PTR_ADDR),
-	       readl(GMAC0_DMA_RX_ADDR_LOW_ADDR),
-	       readl(GMAC0_DMA_RX_ADDR_HIGH_ADDR),
-	       readl(GMAC0_DMA_RX_STATUS0_ADDR),
-	       readl(GMAC0_DMA_RX_STATUS1_ADDR));
-
-	printf("RX Descriptors:\n");
-	for (i = 0; i < RX_BUF_NUM; i++) {
-		descp = (dma64dd_t *)(dma->rx_desc_aligned) + i;
-		printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n",
-		       descp->ctrl1, descp->ctrl2,
-		       descp->addrhigh, descp->addrlow);
-	}
-
-	printf("RX Buffers:\n");
-	for (i = 0; i < RX_BUF_NUM; i++) {
-		bufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED;
-		printf("buf%d:0x%x; ", i, (uint32_t)bufp);
-	}
-	printf("\n");
-}
-#endif
-
-static int dma_tx_init(struct eth_dma *dma)
-{
-	dma64dd_t *descp = NULL;
-	uint8_t *bufp;
-	int i;
-	uint32_t ctrl;
-
-	debug("%s enter\n", __func__);
-
-	/* clear descriptor memory */
-	memset((void *)(dma->tx_desc_aligned), 0,
-	       TX_BUF_NUM * DESCP_SIZE_ALIGNED);
-	memset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE_ALIGNED);
-
-	/* Initialize TX DMA descriptor table */
-	for (i = 0; i < TX_BUF_NUM; i++) {
-		descp = (dma64dd_t *)(dma->tx_desc_aligned) + i;
-		bufp = dma->tx_buf + i * TX_BUF_SIZE_ALIGNED;
-		/* clear buffer memory */
-		memset((void *)bufp, 0, TX_BUF_SIZE_ALIGNED);
-
-		ctrl = 0;
-		/* if last descr set endOfTable */
-		if (i == (TX_BUF_NUM-1))
-			ctrl = D64_CTRL1_EOT;
-		descp->ctrl1 = ctrl;
-		descp->ctrl2 = 0;
-		descp->addrlow = (uint32_t)bufp;
-		descp->addrhigh = 0;
-	}
-
-	/* flush descriptor and buffer */
-	descp = dma->tx_desc_aligned;
-	bufp = dma->tx_buf;
-	flush_dcache_range((unsigned long)descp,
-			   (unsigned long)descp +
-			   DESCP_SIZE_ALIGNED * TX_BUF_NUM);
-	flush_dcache_range((unsigned long)bufp,
-			   (unsigned long)bufp +
-			   TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
-
-	/* initialize the DMA channel */
-	writel((uint32_t)(dma->tx_desc_aligned), GMAC0_DMA_TX_ADDR_LOW_ADDR);
-	writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR);
-
-	/* now update the dma last descriptor */
-	writel(((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK,
-	       GMAC0_DMA_TX_PTR_ADDR);
-
-	return 0;
-}
-
-static int dma_rx_init(struct eth_dma *dma)
-{
-	uint32_t last_desc;
-	dma64dd_t *descp = NULL;
-	uint8_t *bufp;
-	uint32_t ctrl;
-	int i;
-
-	debug("%s enter\n", __func__);
-
-	/* clear descriptor memory */
-	memset((void *)(dma->rx_desc_aligned), 0,
-	       RX_BUF_NUM * DESCP_SIZE_ALIGNED);
-	/* clear buffer memory */
-	memset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE_ALIGNED);
-
-	/* Initialize RX DMA descriptor table */
-	for (i = 0; i < RX_BUF_NUM; i++) {
-		descp = (dma64dd_t *)(dma->rx_desc_aligned) + i;
-		bufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED;
-		ctrl = 0;
-		/* if last descr set endOfTable */
-		if (i == (RX_BUF_NUM - 1))
-			ctrl = D64_CTRL1_EOT;
-		descp->ctrl1 = ctrl;
-		descp->ctrl2 = RX_BUF_SIZE_ALIGNED;
-		descp->addrlow = (uint32_t)bufp;
-		descp->addrhigh = 0;
-
-		last_desc = ((uint32_t)(descp) & D64_XP_LD_MASK)
-				+ sizeof(dma64dd_t);
-	}
-
-	descp = dma->rx_desc_aligned;
-	bufp = dma->rx_buf;
-	/* flush descriptor and buffer */
-	flush_dcache_range((unsigned long)descp,
-			   (unsigned long)descp +
-			   DESCP_SIZE_ALIGNED * RX_BUF_NUM);
-	flush_dcache_range((unsigned long)(bufp),
-			   (unsigned long)bufp +
-			   RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
-
-	/* initailize the DMA channel */
-	writel((uint32_t)descp, GMAC0_DMA_RX_ADDR_LOW_ADDR);
-	writel(0, GMAC0_DMA_RX_ADDR_HIGH_ADDR);
-
-	/* now update the dma last descriptor */
-	writel(last_desc, GMAC0_DMA_RX_PTR_ADDR);
-
-	return 0;
-}
-
-static int dma_init(struct eth_dma *dma)
-{
-	debug(" %s enter\n", __func__);
-
-	/*
-	 * Default flags: For backwards compatibility both
-	 * Rx Overflow Continue and Parity are DISABLED.
-	 */
-	dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN, 0);
-
-	debug("rx burst len 0x%x\n",
-	      (readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK)
-	      >> D64_RC_BL_SHIFT);
-	debug("tx burst len 0x%x\n",
-	      (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_BL_MASK)
-	      >> D64_XC_BL_SHIFT);
-
-	dma_tx_init(dma);
-	dma_rx_init(dma);
-
-	/* From end of chip_init() */
-	/* enable the overflow continue feature and disable parity */
-	dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN /* mask */,
-		      DMA_CTRL_ROC /* value */);
-
-	return 0;
-}
-
-static int dma_deinit(struct eth_dma *dma)
-{
-	debug(" %s enter\n", __func__);
-
-	gmac_disable_dma(dma, MAC_DMA_RX);
-	gmac_disable_dma(dma, MAC_DMA_TX);
-
-	free(dma->tx_buf);
-	dma->tx_buf = NULL;
-	free(dma->tx_desc_aligned);
-	dma->tx_desc_aligned = NULL;
-
-	free(dma->rx_buf);
-	dma->rx_buf = NULL;
-	free(dma->rx_desc_aligned);
-	dma->rx_desc_aligned = NULL;
-
-	return 0;
-}
-
-int gmac_tx_packet(struct eth_dma *dma, void *packet, int length)
-{
-	uint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE_ALIGNED;
-
-	/* kick off the dma */
-	size_t len = length;
-	int txout = dma->cur_tx_index;
-	uint32_t flags;
-	dma64dd_t *descp = NULL;
-	uint32_t ctrl;
-	uint32_t last_desc = (((uint32_t)dma->tx_desc_aligned) +
-			      sizeof(dma64dd_t)) & D64_XP_LD_MASK;
-	size_t buflen;
-
-	debug("%s enter\n", __func__);
-
-	/* load the buffer */
-	memcpy(bufp, packet, len);
-
-	/* Add 4 bytes for Ethernet FCS/CRC */
-	buflen = len + 4;
-
-	ctrl = (buflen & D64_CTRL2_BC_MASK);
-
-	/* the transmit will only be one frame or set SOF, EOF */
-	/* also set int on completion */
-	flags = D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF;
-
-	/* txout points to the descriptor to uset */
-	/* if last descriptor then set EOT */
-	if (txout == (TX_BUF_NUM - 1)) {
-		flags |= D64_CTRL1_EOT;
-		last_desc = ((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK;
-	}
-
-	/* write the descriptor */
-	descp = ((dma64dd_t *)(dma->tx_desc_aligned)) + txout;
-	descp->addrlow = (uint32_t)bufp;
-	descp->addrhigh = 0;
-	descp->ctrl1 = flags;
-	descp->ctrl2 = ctrl;
-
-	/* flush descriptor and buffer */
-	flush_dcache_range((unsigned long)dma->tx_desc_aligned,
-			   (unsigned long)dma->tx_desc_aligned +
-			   DESCP_SIZE_ALIGNED * TX_BUF_NUM);
-	flush_dcache_range((unsigned long)bufp,
-			   (unsigned long)bufp + TX_BUF_SIZE_ALIGNED);
-
-	/* now update the dma last descriptor */
-	writel(last_desc, GMAC0_DMA_TX_PTR_ADDR);
-
-	/* tx dma should be enabled so packet should go out */
-
-	/* update txout */
-	dma->cur_tx_index = (txout + 1) & (TX_BUF_NUM - 1);
-
-	return 0;
-}
-
-bool gmac_check_tx_done(struct eth_dma *dma)
-{
-	/* wait for tx to complete */
-	uint32_t intstatus;
-	bool xfrdone = false;
-
-	debug("%s enter\n", __func__);
-
-	intstatus = readl(GMAC0_INT_STATUS_ADDR);
-
-	debug("int(0x%x)\n", intstatus);
-	if (intstatus & (I_XI0 | I_XI1 | I_XI2 | I_XI3)) {
-		xfrdone = true;
-		/* clear the int bits */
-		intstatus &= ~(I_XI0 | I_XI1 | I_XI2 | I_XI3);
-		writel(intstatus, GMAC0_INT_STATUS_ADDR);
-	} else {
-		debug("Tx int(0x%x)\n", intstatus);
-	}
-
-	return xfrdone;
-}
-
-int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf)
-{
-	void *bufp, *datap;
-	size_t rcvlen = 0, buflen = 0;
-	uint32_t stat0 = 0, stat1 = 0;
-	uint32_t control, offset;
-	uint8_t statbuf[HWRXOFF*2];
-
-	int index, curr, active;
-	dma64dd_t *descp = NULL;
-
-	/* udelay(50); */
-
-	/*
-	 * this api will check if a packet has been received.
-	 * If so it will return the address of the buffer and current
-	 * descriptor index will be incremented to the
-	 * next descriptor. Once done with the frame the buffer should be
-	 * added back onto the descriptor and the lastdscr should be updated
-	 * to this descriptor.
-	 */
-	index = dma->cur_rx_index;
-	offset = (uint32_t)(dma->rx_desc_aligned);
-	stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR) & D64_RS0_CD_MASK;
-	stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR) & D64_RS0_CD_MASK;
-	curr = ((stat0 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t);
-	active = ((stat1 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t);
-
-	/* check if any frame */
-	if (index == curr)
-		return -1;
-
-	debug("received packet\n");
-	debug("expect(0x%x) curr(0x%x) active(0x%x)\n", index, curr, active);
-	/* remove warning */
-	if (index == active)
-		;
-
-	/* get the packet pointer that corresponds to the rx descriptor */
-	bufp = dma->rx_buf + index * RX_BUF_SIZE_ALIGNED;
-
-	descp = (dma64dd_t *)(dma->rx_desc_aligned) + index;
-	/* flush descriptor and buffer */
-	flush_dcache_range((unsigned long)dma->rx_desc_aligned,
-			   (unsigned long)dma->rx_desc_aligned +
-			   DESCP_SIZE_ALIGNED * RX_BUF_NUM);
-	flush_dcache_range((unsigned long)bufp,
-			   (unsigned long)bufp + RX_BUF_SIZE_ALIGNED);
-
-	buflen = (descp->ctrl2 & D64_CTRL2_BC_MASK);
-
-	stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR);
-	stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR);
-
-	debug("bufp(0x%x) index(0x%x) buflen(0x%x) stat0(0x%x) stat1(0x%x)\n",
-	      (uint32_t)bufp, index, buflen, stat0, stat1);
-
-	dma->cur_rx_index = (index + 1) & (RX_BUF_NUM - 1);
-
-	/* get buffer offset */
-	control = readl(GMAC0_DMA_RX_CTRL_ADDR);
-	offset = (control & D64_RC_RO_MASK) >> D64_RC_RO_SHIFT;
-	rcvlen = *(uint16_t *)bufp;
-
-	debug("Received %d bytes\n", rcvlen);
-	/* copy status into temp buf then copy data from rx buffer */
-	memcpy(statbuf, bufp, offset);
-	datap = (void *)((uint32_t)bufp + offset);
-	memcpy(buf, datap, rcvlen);
-
-	/* update descriptor that is being added back on ring */
-	descp->ctrl2 = RX_BUF_SIZE_ALIGNED;
-	descp->addrlow = (uint32_t)bufp;
-	descp->addrhigh = 0;
-	/* flush descriptor */
-	flush_dcache_range((unsigned long)dma->rx_desc_aligned,
-			   (unsigned long)dma->rx_desc_aligned +
-			   DESCP_SIZE_ALIGNED * RX_BUF_NUM);
-
-	/* set the lastdscr for the rx ring */
-	writel(((uint32_t)descp) & D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
-
-	return (int)rcvlen;
-}
-
-static int gmac_disable_dma(struct eth_dma *dma, int dir)
-{
-	int status;
-
-	debug("%s enter\n", __func__);
-
-	if (dir == MAC_DMA_TX) {
-		/* address PR8249/PR7577 issue */
-		/* suspend tx DMA first */
-		writel(D64_XC_SE, GMAC0_DMA_TX_CTRL_ADDR);
-		SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &
-				     D64_XS0_XS_MASK)) !=
-			  D64_XS0_XS_DISABLED) &&
-			 (status != D64_XS0_XS_IDLE) &&
-			 (status != D64_XS0_XS_STOPPED), 10000);
-
-		/*
-		 * PR2414 WAR: DMA engines are not disabled until
-		 * transfer finishes
-		 */
-		writel(0, GMAC0_DMA_TX_CTRL_ADDR);
-		SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &
-				     D64_XS0_XS_MASK)) !=
-			  D64_XS0_XS_DISABLED), 10000);
-
-		/* wait for the last transaction to complete */
-		udelay(2);
-
-		status = (status == D64_XS0_XS_DISABLED);
-	} else {
-		/*
-		 * PR2414 WAR: DMA engines are not disabled until
-		 * transfer finishes
-		 */
-		writel(0, GMAC0_DMA_RX_CTRL_ADDR);
-		SPINWAIT(((status = (readl(GMAC0_DMA_RX_STATUS0_ADDR) &
-				     D64_RS0_RS_MASK)) !=
-			  D64_RS0_RS_DISABLED), 10000);
-
-		status = (status == D64_RS0_RS_DISABLED);
-	}
-
-	return status;
-}
-
-static int gmac_enable_dma(struct eth_dma *dma, int dir)
-{
-	uint32_t control;
-
-	debug("%s enter\n", __func__);
-
-	if (dir == MAC_DMA_TX) {
-		dma->cur_tx_index = 0;
-
-		/*
-		 * These bits 20:18 (burstLen) of control register can be
-		 * written but will take effect only if these bits are
-		 * valid. So this will not affect previous versions
-		 * of the DMA. They will continue to have those bits set to 0.
-		 */
-		control = readl(GMAC0_DMA_TX_CTRL_ADDR);
-
-		control |= D64_XC_XE;
-		if ((g_dmactrlflags & DMA_CTRL_PEN) == 0)
-			control |= D64_XC_PD;
-
-		writel(control, GMAC0_DMA_TX_CTRL_ADDR);
-
-		/* initailize the DMA channel */
-		writel((uint32_t)(dma->tx_desc_aligned),
-		       GMAC0_DMA_TX_ADDR_LOW_ADDR);
-		writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR);
-	} else {
-		dma->cur_rx_index = 0;
-
-		control = (readl(GMAC0_DMA_RX_CTRL_ADDR) &
-			   D64_RC_AE) | D64_RC_RE;
-
-		if ((g_dmactrlflags & DMA_CTRL_PEN) == 0)
-			control |= D64_RC_PD;
-
-		if (g_dmactrlflags & DMA_CTRL_ROC)
-			control |= D64_RC_OC;
-
-		/*
-		 * These bits 20:18 (burstLen) of control register can be
-		 * written but will take effect only if these bits are
-		 * valid. So this will not affect previous versions
-		 * of the DMA. They will continue to have those bits set to 0.
-		 */
-		control &= ~D64_RC_BL_MASK;
-		/* Keep default Rx burstlen */
-		control |= readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK;
-		control |= HWRXOFF << D64_RC_RO_SHIFT;
-
-		writel(control, GMAC0_DMA_RX_CTRL_ADDR);
-
-		/*
-		 * the rx descriptor ring should have
-		 * the addresses set properly;
-		 * set the lastdscr for the rx ring
-		 */
-		writel(((uint32_t)(dma->rx_desc_aligned) +
-			(RX_BUF_NUM - 1) * RX_BUF_SIZE_ALIGNED) &
-		       D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
-	}
-
-	return 0;
-}
-
-bool gmac_mii_busywait(unsigned int timeout)
-{
-	uint32_t tmp = 0;
-
-	while (timeout > 10) {
-		tmp = readl(GMAC_MII_CTRL_ADDR);
-		if (tmp & (1 << GMAC_MII_BUSY_SHIFT)) {
-			udelay(10);
-			timeout -= 10;
-		} else {
-			break;
-		}
-	}
-	return tmp & (1 << GMAC_MII_BUSY_SHIFT);
-}
-
-int gmac_miiphy_read(struct mii_dev *bus, int phyaddr, int devad, int reg)
-{
-	uint32_t tmp = 0;
-	u16 value = 0;
-
-	/* Busy wait timeout is 1ms */
-	if (gmac_mii_busywait(1000)) {
-		pr_err("%s: Prepare MII read: MII/MDIO busy\n", __func__);
-		return -1;
-	}
-
-	/* Read operation */
-	tmp = GMAC_MII_DATA_READ_CMD;
-	tmp |= (phyaddr << GMAC_MII_PHY_ADDR_SHIFT) |
-		(reg << GMAC_MII_PHY_REG_SHIFT);
-	debug("MII read cmd 0x%x, phy 0x%x, reg 0x%x\n", tmp, phyaddr, reg);
-	writel(tmp, GMAC_MII_DATA_ADDR);
-
-	if (gmac_mii_busywait(1000)) {
-		pr_err("%s: MII read failure: MII/MDIO busy\n", __func__);
-		return -1;
-	}
-
-	value = readl(GMAC_MII_DATA_ADDR) & 0xffff;
-	debug("MII read data 0x%x\n", value);
-	return value;
-}
-
-int gmac_miiphy_write(struct mii_dev *bus, int phyaddr, int devad, int reg,
-		      u16 value)
-{
-	uint32_t tmp = 0;
-
-	/* Busy wait timeout is 1ms */
-	if (gmac_mii_busywait(1000)) {
-		pr_err("%s: Prepare MII write: MII/MDIO busy\n", __func__);
-		return -1;
-	}
-
-	/* Write operation */
-	tmp = GMAC_MII_DATA_WRITE_CMD | (value & 0xffff);
-	tmp |= ((phyaddr << GMAC_MII_PHY_ADDR_SHIFT) |
-		(reg << GMAC_MII_PHY_REG_SHIFT));
-	debug("MII write cmd 0x%x, phy 0x%x, reg 0x%x, data 0x%x\n",
-	      tmp, phyaddr, reg, value);
-	writel(tmp, GMAC_MII_DATA_ADDR);
-
-	if (gmac_mii_busywait(1000)) {
-		pr_err("%s: MII write failure: MII/MDIO busy\n", __func__);
-		return -1;
-	}
-
-	return 0;
-}
-
-void gmac_init_reset(void)
-{
-	debug("%s enter\n", __func__);
-
-	/* set command config reg CC_SR */
-	reg32_set_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR);
-	udelay(GMAC_RESET_DELAY);
-}
-
-void gmac_clear_reset(void)
-{
-	debug("%s enter\n", __func__);
-
-	/* clear command config reg CC_SR */
-	reg32_clear_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR);
-	udelay(GMAC_RESET_DELAY);
-}
-
-static void gmac_enable_local(bool en)
-{
-	uint32_t cmdcfg;
-
-	debug("%s enter\n", __func__);
-
-	/* read command config reg */
-	cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
-
-	/* put mac in reset */
-	gmac_init_reset();
-
-	cmdcfg |= CC_SR;
-
-	/* first deassert rx_ena and tx_ena while in reset */
-	cmdcfg &= ~(CC_RE | CC_TE);
-	/* write command config reg */
-	writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
-
-	/* bring mac out of reset */
-	gmac_clear_reset();
-
-	/* if not enable exit now */
-	if (!en)
-		return;
-
-	/* enable the mac transmit and receive paths now */
-	udelay(2);
-	cmdcfg &= ~CC_SR;
-	cmdcfg |= (CC_RE | CC_TE);
-
-	/* assert rx_ena and tx_ena when out of reset to enable the mac */
-	writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
-
-	return;
-}
-
-int gmac_enable(void)
-{
-	gmac_enable_local(1);
-
-	/* clear interrupts */
-	writel(I_INTMASK, GMAC0_INT_STATUS_ADDR);
-	return 0;
-}
-
-int gmac_disable(void)
-{
-	gmac_enable_local(0);
-	return 0;
-}
-
-int gmac_set_speed(int speed, int duplex)
-{
-	uint32_t cmdcfg;
-	uint32_t hd_ena;
-	uint32_t speed_cfg;
-
-	hd_ena = duplex ? 0 : CC_HD;
-	if (speed == 1000) {
-		speed_cfg = 2;
-	} else if (speed == 100) {
-		speed_cfg = 1;
-	} else if (speed == 10) {
-		speed_cfg = 0;
-	} else {
-		pr_err("%s: Invalid GMAC speed(%d)!\n", __func__, speed);
-		return -1;
-	}
-
-	cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
-	cmdcfg &= ~(CC_ES_MASK | CC_HD);
-	cmdcfg |= ((speed_cfg << CC_ES_SHIFT) | hd_ena);
-
-	printf("Change GMAC speed to %dMB\n", speed);
-	debug("GMAC speed cfg 0x%x\n", cmdcfg);
-	writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
-
-	return 0;
-}
-
-int gmac_set_mac_addr(unsigned char *mac)
-{
-	/* set our local address */
-	debug("GMAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
-	      mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-	writel(htonl(*(uint32_t *)mac), UNIMAC0_MAC_MSB_ADDR);
-	writew(htons(*(uint32_t *)&mac[4]), UNIMAC0_MAC_LSB_ADDR);
-
-	return 0;
-}
-
-int gmac_mac_init(struct eth_device *dev)
-{
-	struct eth_info *eth = (struct eth_info *)(dev->priv);
-	struct eth_dma *dma = &(eth->dma);
-
-	uint32_t tmp;
-	uint32_t cmdcfg;
-	int chipid;
-
-	debug("%s enter\n", __func__);
-
-	/* Always use GMAC0 */
-	printf("Using GMAC%d\n", 0);
-
-	/* Reset AMAC0 core */
-	writel(0, AMAC0_IDM_RESET_ADDR);
-	tmp = readl(AMAC0_IO_CTRL_DIRECT_ADDR);
-	/* Set clock */
-	tmp &= ~(1 << AMAC0_IO_CTRL_CLK_250_SEL_SHIFT);
-	tmp |= (1 << AMAC0_IO_CTRL_GMII_MODE_SHIFT);
-	/* Set Tx clock */
-	tmp &= ~(1 << AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT);
-	writel(tmp, AMAC0_IO_CTRL_DIRECT_ADDR);
-
-	/* reset gmac */
-	/*
-	 * As AMAC is just reset, NO need?
-	 * set eth_data into loopback mode to ensure no rx traffic
-	 * gmac_loopback(eth_data, TRUE);
-	 * ET_TRACE(("%s gmac loopback\n", __func__));
-	 * udelay(1);
-	 */
-
-	cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
-	cmdcfg &= ~(CC_TE | CC_RE | CC_RPI | CC_TAI | CC_HD | CC_ML |
-		    CC_CFE | CC_RL | CC_RED | CC_PE | CC_TPI |
-		    CC_PAD_EN | CC_PF);
-	cmdcfg |= (CC_PROM | CC_NLC | CC_CFE);
-	/* put mac in reset */
-	gmac_init_reset();
-	writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
-	gmac_clear_reset();
-
-	/* enable clear MIB on read */
-	reg32_set_bits(GMAC0_DEV_CTRL_ADDR, DC_MROR);
-	/* PHY: set smi_master to drive mdc_clk */
-	reg32_set_bits(GMAC0_PHY_CTRL_ADDR, PC_MTE);
-
-	/* clear persistent sw intstatus */
-	writel(0, GMAC0_INT_STATUS_ADDR);
-
-	if (dma_init(dma) < 0) {
-		pr_err("%s: GMAC dma_init failed\n", __func__);
-		goto err_exit;
-	}
-
-	chipid = CHIPID;
-	printf("%s: Chip ID: 0x%x\n", __func__, chipid);
-
-	/* set switch bypass mode */
-	tmp = readl(SWITCH_GLOBAL_CONFIG_ADDR);
-	tmp |= (1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT);
-
-	/* Switch mode */
-	/* tmp &= ~(1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); */
-
-	writel(tmp, SWITCH_GLOBAL_CONFIG_ADDR);
-
-	tmp = readl(CRMU_CHIP_IO_PAD_CONTROL_ADDR);
-	tmp &= ~(1 << CDRU_IOMUX_FORCE_PAD_IN_SHIFT);
-	writel(tmp, CRMU_CHIP_IO_PAD_CONTROL_ADDR);
-
-	/* Set MDIO to internal GPHY */
-	tmp = readl(GMAC_MII_CTRL_ADDR);
-	/* Select internal MDC/MDIO bus*/
-	tmp &= ~(1 << GMAC_MII_CTRL_BYP_SHIFT);
-	/* select MDC/MDIO connecting to on-chip internal PHYs */
-	tmp &= ~(1 << GMAC_MII_CTRL_EXT_SHIFT);
-	/*
-	 * give bit[6:0](MDCDIV) with required divisor to set
-	 * the MDC clock frequency, 66MHZ/0x1A=2.5MHZ
-	 */
-	tmp |= 0x1A;
-
-	writel(tmp, GMAC_MII_CTRL_ADDR);
-
-	if (gmac_mii_busywait(1000)) {
-		pr_err("%s: Configure MDIO: MII/MDIO busy\n", __func__);
-		goto err_exit;
-	}
-
-	/* Configure GMAC0 */
-	/* enable one rx interrupt per received frame */
-	writel(1 << GMAC0_IRL_FRAMECOUNT_SHIFT, GMAC0_INTR_RECV_LAZY_ADDR);
-
-	/* read command config reg */
-	cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);
-	/* enable 802.3x tx flow control (honor received PAUSE frames) */
-	cmdcfg &= ~CC_RPI;
-	/* enable promiscuous mode */
-	cmdcfg |= CC_PROM;
-	/* Disable loopback mode */
-	cmdcfg &= ~CC_ML;
-	/* set the speed */
-	cmdcfg &= ~(CC_ES_MASK | CC_HD);
-	/* Set to 1Gbps and full duplex by default */
-	cmdcfg |= (2 << CC_ES_SHIFT);
-
-	/* put mac in reset */
-	gmac_init_reset();
-	/* write register */
-	writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR);
-	/* bring mac out of reset */
-	gmac_clear_reset();
-
-	/* set max frame lengths; account for possible vlan tag */
-	writel(PKTSIZE + 32, UNIMAC0_FRM_LENGTH_ADDR);
-
-	return 0;
-
-err_exit:
-	dma_deinit(dma);
-	return -1;
-}
-
-int gmac_add(struct eth_device *dev)
-{
-	struct eth_info *eth = (struct eth_info *)(dev->priv);
-	struct eth_dma *dma = &(eth->dma);
-	void *tmp;
-
-	/*
-	 * Desc has to be 16-byte aligned. But for dcache flush it must be
-	 * aligned to ARCH_DMA_MINALIGN.
-	 */
-	tmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * TX_BUF_NUM);
-	if (tmp == NULL) {
-		printf("%s: Failed to allocate TX desc Buffer\n", __func__);
-		return -1;
-	}
-
-	dma->tx_desc_aligned = (void *)tmp;
-	debug("TX Descriptor Buffer: %p; length: 0x%x\n",
-	      dma->tx_desc_aligned, DESCP_SIZE_ALIGNED * TX_BUF_NUM);
-
-	tmp = memalign(ARCH_DMA_MINALIGN, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
-	if (tmp == NULL) {
-		printf("%s: Failed to allocate TX Data Buffer\n", __func__);
-		free(dma->tx_desc_aligned);
-		return -1;
-	}
-	dma->tx_buf = (uint8_t *)tmp;
-	debug("TX Data Buffer: %p; length: 0x%x\n",
-	      dma->tx_buf, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
-
-	/* Desc has to be 16-byte aligned */
-	tmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * RX_BUF_NUM);
-	if (tmp == NULL) {
-		printf("%s: Failed to allocate RX Descriptor\n", __func__);
-		free(dma->tx_desc_aligned);
-		free(dma->tx_buf);
-		return -1;
-	}
-	dma->rx_desc_aligned = (void *)tmp;
-	debug("RX Descriptor Buffer: %p, length: 0x%x\n",
-	      dma->rx_desc_aligned, DESCP_SIZE_ALIGNED * RX_BUF_NUM);
-
-	tmp = memalign(ARCH_DMA_MINALIGN, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
-	if (tmp == NULL) {
-		printf("%s: Failed to allocate RX Data Buffer\n", __func__);
-		free(dma->tx_desc_aligned);
-		free(dma->tx_buf);
-		free(dma->rx_desc_aligned);
-		return -1;
-	}
-	dma->rx_buf = (uint8_t *)tmp;
-	debug("RX Data Buffer: %p; length: 0x%x\n",
-	      dma->rx_buf, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
-
-	g_dmactrlflags = 0;
-
-	eth->phy_interface = PHY_INTERFACE_MODE_GMII;
-
-	dma->tx_packet = gmac_tx_packet;
-	dma->check_tx_done = gmac_check_tx_done;
-
-	dma->check_rx_done = gmac_check_rx_done;
-
-	dma->enable_dma = gmac_enable_dma;
-	dma->disable_dma = gmac_disable_dma;
-
-	eth->miiphy_read = gmac_miiphy_read;
-	eth->miiphy_write = gmac_miiphy_write;
-
-	eth->mac_init = gmac_mac_init;
-	eth->disable_mac = gmac_disable;
-	eth->enable_mac = gmac_enable;
-	eth->set_mac_addr = gmac_set_mac_addr;
-	eth->set_mac_speed = gmac_set_speed;
-
-	return 0;
-}
diff --git a/drivers/net/bcm-sf2-eth-gmac.h b/drivers/net/bcm-sf2-eth-gmac.h
deleted file mode 100644
index 477667f4ea..0000000000
--- a/drivers/net/bcm-sf2-eth-gmac.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Broadcom Corporation.
- */
-
-#ifndef _BCM_SF2_ETH_GMAC_H_
-#define _BCM_SF2_ETH_GMAC_H_
-
-#define BCM_SF2_ETH_MAC_NAME	"gmac"
-
-#ifndef ETHHW_PORT_INT
-#define ETHHW_PORT_INT		8
-#endif
-
-#define GMAC0_REG_BASE			0x18042000
-#define GMAC0_DEV_CTRL_ADDR		GMAC0_REG_BASE
-#define GMAC0_INT_STATUS_ADDR		(GMAC0_REG_BASE + 0x020)
-#define GMAC0_INTR_RECV_LAZY_ADDR	(GMAC0_REG_BASE + 0x100)
-#define GMAC0_PHY_CTRL_ADDR		(GMAC0_REG_BASE + 0x188)
-
-
-#define GMAC_DMA_PTR_OFFSET		0x04
-#define GMAC_DMA_ADDR_LOW_OFFSET	0x08
-#define GMAC_DMA_ADDR_HIGH_OFFSET	0x0c
-#define GMAC_DMA_STATUS0_OFFSET		0x10
-#define GMAC_DMA_STATUS1_OFFSET		0x14
-
-#define GMAC0_DMA_TX_CTRL_ADDR		(GMAC0_REG_BASE + 0x200)
-#define GMAC0_DMA_TX_PTR_ADDR \
-		(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
-#define GMAC0_DMA_TX_ADDR_LOW_ADDR \
-		(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
-#define GMAC0_DMA_TX_ADDR_HIGH_ADDR \
-		(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
-#define GMAC0_DMA_TX_STATUS0_ADDR \
-		(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
-#define GMAC0_DMA_TX_STATUS1_ADDR \
-		(GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
-
-#define GMAC0_DMA_RX_CTRL_ADDR		(GMAC0_REG_BASE + 0x220)
-#define GMAC0_DMA_RX_PTR_ADDR \
-		(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
-#define GMAC0_DMA_RX_ADDR_LOW_ADDR \
-		(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
-#define GMAC0_DMA_RX_ADDR_HIGH_ADDR \
-		(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
-#define GMAC0_DMA_RX_STATUS0_ADDR \
-		(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
-#define GMAC0_DMA_RX_STATUS1_ADDR \
-		(GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
-
-#define UNIMAC0_CMD_CFG_ADDR		(GMAC0_REG_BASE + 0x808)
-#define UNIMAC0_MAC_MSB_ADDR		(GMAC0_REG_BASE + 0x80c)
-#define UNIMAC0_MAC_LSB_ADDR		(GMAC0_REG_BASE + 0x810)
-#define UNIMAC0_FRM_LENGTH_ADDR		(GMAC0_REG_BASE + 0x814)
-
-#define GMAC0_IRL_FRAMECOUNT_SHIFT	24
-
-/* transmit channel control */
-/* transmit enable */
-#define D64_XC_XE		0x00000001
-/* transmit suspend request */
-#define D64_XC_SE		0x00000002
-/* parity check disable */
-#define D64_XC_PD		0x00000800
-/* BurstLen bits */
-#define D64_XC_BL_MASK		0x001C0000
-#define D64_XC_BL_SHIFT		18
-
-/* transmit descriptor table pointer */
-/* last valid descriptor */
-#define D64_XP_LD_MASK		0x00001fff
-
-/* transmit channel status */
-/* transmit state */
-#define D64_XS0_XS_MASK		0xf0000000
-#define D64_XS0_XS_SHIFT	28
-#define D64_XS0_XS_DISABLED	0x00000000
-#define D64_XS0_XS_ACTIVE	0x10000000
-#define D64_XS0_XS_IDLE		0x20000000
-#define D64_XS0_XS_STOPPED	0x30000000
-#define D64_XS0_XS_SUSP		0x40000000
-
-/* receive channel control */
-/* receive enable */
-#define D64_RC_RE		0x00000001
-/* address extension bits */
-#define D64_RC_AE		0x00030000
-/* overflow continue */
-#define D64_RC_OC		0x00000400
-/* parity check disable */
-#define D64_RC_PD		0x00000800
-/* receive frame offset */
-#define D64_RC_RO_MASK		0x000000fe
-#define D64_RC_RO_SHIFT		1
-/* BurstLen bits */
-#define D64_RC_BL_MASK		0x001C0000
-#define D64_RC_BL_SHIFT		18
-
-/* flags for dma controller */
-/* partity enable */
-#define DMA_CTRL_PEN		(1 << 0)
-/* rx overflow continue */
-#define DMA_CTRL_ROC		(1 << 1)
-
-/* receive descriptor table pointer */
-/* last valid descriptor */
-#define D64_RP_LD_MASK		0x00001fff
-
-/* receive channel status */
-/* current descriptor pointer */
-#define D64_RS0_CD_MASK		0x00001fff
-/* receive state */
-#define D64_RS0_RS_MASK		0xf0000000
-#define D64_RS0_RS_SHIFT	28
-#define D64_RS0_RS_DISABLED	0x00000000
-#define D64_RS0_RS_ACTIVE	0x10000000
-#define D64_RS0_RS_IDLE		0x20000000
-#define D64_RS0_RS_STOPPED	0x30000000
-#define D64_RS0_RS_SUSP		0x40000000
-
-/* descriptor control flags 1 */
-/* core specific flags */
-#define D64_CTRL_COREFLAGS	0x0ff00000
-/* end of descriptor table */
-#define D64_CTRL1_EOT		((uint32_t)1 << 28)
-/* interrupt on completion */
-#define D64_CTRL1_IOC		((uint32_t)1 << 29)
-/* end of frame */
-#define D64_CTRL1_EOF		((uint32_t)1 << 30)
-/* start of frame */
-#define D64_CTRL1_SOF		((uint32_t)1 << 31)
-
-/* descriptor control flags 2 */
-/* buffer byte count. real data len must <= 16KB */
-#define D64_CTRL2_BC_MASK	0x00007fff
-/* address extension bits */
-#define D64_CTRL2_AE		0x00030000
-#define D64_CTRL2_AE_SHIFT	16
-/* parity bit */
-#define D64_CTRL2_PARITY	0x00040000
-/* control flags in the range [27:20] are core-specific and not defined here */
-#define D64_CTRL_CORE_MASK	0x0ff00000
-
-#define DC_MROR		0x00000010
-#define PC_MTE		0x00800000
-
-/* command config */
-#define CC_TE		0x00000001
-#define CC_RE		0x00000002
-#define CC_ES_MASK	0x0000000c
-#define CC_ES_SHIFT	2
-#define CC_PROM		0x00000010
-#define CC_PAD_EN	0x00000020
-#define CC_CF		0x00000040
-#define CC_PF		0x00000080
-#define CC_RPI		0x00000100
-#define CC_TAI		0x00000200
-#define CC_HD		0x00000400
-#define CC_HD_SHIFT	10
-#define CC_SR		0x00002000
-#define CC_ML		0x00008000
-#define CC_AE		0x00400000
-#define CC_CFE		0x00800000
-#define CC_NLC		0x01000000
-#define CC_RL		0x02000000
-#define CC_RED		0x04000000
-#define CC_PE		0x08000000
-#define CC_TPI		0x10000000
-#define CC_AT		0x20000000
-
-#define I_PDEE		0x00000400
-#define I_PDE		0x00000800
-#define I_DE		0x00001000
-#define I_RDU		0x00002000
-#define I_RFO		0x00004000
-#define I_XFU		0x00008000
-#define I_RI		0x00010000
-#define I_XI0		0x01000000
-#define I_XI1		0x02000000
-#define I_XI2		0x04000000
-#define I_XI3		0x08000000
-#define I_ERRORS	(I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU)
-#define DEF_INTMASK	(I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS)
-
-#define I_INTMASK	0x0f01fcff
-
-#define CHIP_DRU_BASE				0x0301d000
-#define CRMU_CHIP_IO_PAD_CONTROL_ADDR		(CHIP_DRU_BASE + 0x0bc)
-#define SWITCH_GLOBAL_CONFIG_ADDR		(CHIP_DRU_BASE + 0x194)
-
-#define CDRU_IOMUX_FORCE_PAD_IN_SHIFT		0
-#define CDRU_SWITCH_BYPASS_SWITCH_SHIFT		13
-
-#define AMAC0_IDM_RESET_ADDR			0x18110800
-#define AMAC0_IO_CTRL_DIRECT_ADDR		0x18110408
-#define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT		6
-#define AMAC0_IO_CTRL_GMII_MODE_SHIFT		5
-#define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT	3
-
-#define CHIPA_CHIP_ID_ADDR			0x18000000
-#define CHIPID		(readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF)
-#define CHIPREV		(((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF)
-#define CHIPSKU		(((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF)
-
-#define GMAC_MII_CTRL_ADDR		0x18002000
-#define GMAC_MII_CTRL_BYP_SHIFT		10
-#define GMAC_MII_CTRL_EXT_SHIFT		9
-#define GMAC_MII_DATA_ADDR		0x18002004
-#define GMAC_MII_DATA_READ_CMD		0x60020000
-#define GMAC_MII_DATA_WRITE_CMD		0x50020000
-#define GMAC_MII_BUSY_SHIFT		8
-#define GMAC_MII_PHY_ADDR_SHIFT		23
-#define GMAC_MII_PHY_REG_SHIFT		18
-
-#define GMAC_RESET_DELAY		2
-#define HWRXOFF				30
-#define MAXNAMEL			8
-#define NUMTXQ				4
-
-int gmac_add(struct eth_device *dev);
-
-#endif /* _BCM_SF2_ETH_GMAC_H_ */
diff --git a/drivers/net/bcmbca/Kconfig b/drivers/net/bcmbca/Kconfig
new file mode 100644
index 0000000000..13518467e1
--- /dev/null
+++ b/drivers/net/bcmbca/Kconfig
@@ -0,0 +1,167 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+config BCMBCA_RDP_ETH
+	bool "BCMBCA RDP based network driver"
+	select BCMBCA_RDP
+	depends on DM_ETH && ARCH_BCMBCA
+	default y if BCM63138
+	default y if BCM63148
+	default n
+	help
+	   This driver supports RDP based network driver
+
+config BCMBCA_XRDP_ETH
+	bool "BCMBCA XRDP based network driver"
+	depends on DM_ETH && ARCH_BCMBCA
+	default y if BCM6846
+	default y if BCM6856
+	default y if BCM6858
+	default y if BCM6878
+	default y if BCM63146
+	default y if BCM4912
+	default n
+	help
+	   This driver supports XRDP based network driver
+
+config BCMBCA_XRDP_ETH_SWITCH_IFACE
+	bool "BCMBCA XRDP network driver switch"
+	depends on BCMBCA_XRDP_ETH
+	default y
+	help
+	   Create a single ETH interface representing the whole switch
+
+config BCMBCA_LPORT
+	bool "BCMBCA LPORT driver"
+	default y if BCM6858
+	default n
+	help
+	   This driver supports lport
+
+config BCMBCA_XRDP
+	bool "BCMBCA XRDP driver"
+	default y if BCM6846
+	default y if BCM6856
+	default y if BCM6858
+	default y if BCM6878
+	default y if BCM63146
+	default y if BCM4912
+	default n
+	help
+	   This driver supports xrdp
+
+config BCMBCA_XRDP_PON
+	bool "BCMBCA XRDP driver for PON platform"
+	default y if BCM6846
+	default y if BCM6856
+	default y if BCM6858
+	default y if BCM6878
+	default n
+	help
+	   This driver supports xrdp for PON
+
+config BCMBCA_XRDP_DSL
+	bool "BCMBCA XRDP driver for DSL platform"
+	default y if BCM63146
+	default y if BCM4912
+	default n
+	help
+	   This driver supports xrdp for DSL
+
+config BCMBCA_PHY
+	bool "BCMBCA PHY framework driver"
+	default y if BCM6846
+	default y if BCM6856
+	default y if BCM6858
+	default y if BCM6878
+	default y if BCM63146
+	default y if BCM4912
+	default n
+	help
+	   This driver supports PHY framework
+
+config BCM_SELECTIVE_PHYS
+	bool "Selective PHYs"
+    depends on BCMBCA_PHY
+	default n
+
+config BCM_PHY_MAKO_A0
+	bool "Mako A0 support"
+	depends on BCM_SELECTIVE_PHYS
+	default n
+
+config BCM_PHY_ORCA_A0
+	bool "Orca A0 support"
+	depends on BCM_SELECTIVE_PHYS
+	default n
+
+config BCM_PHY_ORCA_B0
+	bool "Orca A0 support"
+	depends on BCM_SELECTIVE_PHYS
+	default n
+
+config BCM_PHY_BLACKFIN_A0
+	bool "Blackfin A0 support"
+	depends on BCM_SELECTIVE_PHYS
+	default n
+
+config BCM_PHY_BLACKFIN_B0
+	bool "Blackfin B0 support"
+	depends on BCM_SELECTIVE_PHYS
+	default n
+
+config BCM_PHY_LONGFIN_A0
+	bool "Longfin A0 support"
+	depends on BCM_SELECTIVE_PHYS
+	default n
+
+config BCM_PHY_LONGFIN_B0
+	bool "Longfin B0 support"
+	depends on BCM_SELECTIVE_PHYS
+	default n
+
+config BCMBCA_SYSPORT_V1
+	bool "BCMBCA Sysport version 1 support"
+	default y if BCM63158
+	default n
+	help
+	   This driver supports BCM System port v1.0
+
+config BCMBCA_SYSPORT_V2
+	bool "BCMBCA Sysport version 2 support"
+	default y if BCM63178
+	default y if BCM47622
+	default y if BCM6756
+	default n
+	help
+	   This driver supports BCM System port v2.0
+
+config BCMBCA_SWITCH
+	bool "BCMBCA Switch Driver"
+	default y if BCM63138
+	default y if BCM63148
+	default y if BCM63158
+	default y if BCM63178
+	default y if BCM4908
+	default y if BCM6756	
+	default n
+	help
+	   This driver supports BCMBCA Switch
+
+config BCMBCA_SF2_GMAC
+	bool "BCMBCA External Switch Driver"
+	default y if BCM4908
+	default n
+	help
+	   This driver supports BCMBCA External Switch
+
+config BCMBCA_EXT_SWITCH
+	bool "BCMBCA External Switch Driver"
+	default y if BCM47622
+	default y if BCM6756
+	default n
+	help
+	   This driver supports BCMBCA External Switch
+
diff --git a/drivers/net/bcmbca/Makefile b/drivers/net/bcmbca/Makefile
new file mode 100644
index 0000000000..e221fb2798
--- /dev/null
+++ b/drivers/net/bcmbca/Makefile
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+ifdef CONFIG_BCMBCA_XRDP_ETH
+
+ifdef CONFIG_BCMBCA_PMC
+EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/pmc
+endif
+
+ifdef CONFIG_BCMBCA_XRDP
+EXTRA_CFLAGS += -I$(srctree)/drivers/net/bcmbca/xrdp
+endif
+
+ifdef CONFIG_BCMBCA_PHY
+EXTRA_CFLAGS += -I$(srctree)/drivers/net/bcmbca/phy
+endif
+
+EXTRA_CFLAGS += -Werror
+obj-$(CONFIG_BCMBCA_XRDP_ETH) += bcmbca_xrdp_eth.o
+obj-$(CONFIG_BCMBCA_LPORT) += lport/
+obj-$(CONFIG_BCMBCA_PHY) += phy/
+
+ifdef CONFIG_BCMBCA_XRDP_PON
+EXTRA_CFLAGS += -DCONFIG_BCM_PON -DCONFIG_BCM_PON_XRDP -DBCM_PON_XRDP
+endif
+
+ifdef CONFIG_BCMBCA_XRDP_DSL
+EXTRA_CFLAGS += -DCONFIG_BCM_DSL -DCONFIG_BCM_DSL_XRDP -DBCM_DSL_XRDP
+endif
+
+CONFIG_XRDP_FULL ?= 0
+
+ifeq ($(strip $(CONFIG_XRDP_FULL)),1)
+obj-$(CONFIG_BCMBCA_XRDP) += xrdp_full/
+else
+obj-$(CONFIG_BCMBCA_XRDP) += xrdp/
+endif
+
+endif
+
+
+ifdef CONFIG_BCMBCA_RDP_ETH
+
+KBUILD_CPPFLAGS += -DLEGACY_RDP -DRDD_BASIC -DBCM_DSL_RDP
+
+ifdef CONFIG_BCM63138
+KBUILD_CPPFLAGS += -DDSL_63138
+endif
+
+ifdef CONFIG_BCM63148
+KBUILD_CPPFLAGS += -DDSL_63148
+endif
+
+UBOOTINCLUDE += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/rdp
+UBOOTINCLUDE += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/$(subst \",,$(CONFIG_SYS_SOC))/rdp_fw
+UBOOTINCLUDE += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/pmc
+
+obj-y += bcmbca_rdp_eth.o
+
+endif
+
+ifdef CONFIG_BCMBCA_SWITCH
+UBOOTINCLUDE += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/pmc
+ifdef_any_of = $(filter-out undefined,$(foreach v,$(1),$(origin $(v))))
+obj-y += bcm_ethsw_impl1.o bcm_ethsw_phy.o
+# the following 3 SOCs have specific PHY configurations
+ifneq ($(call ifdef_any_of,CONFIG_BCM63138 CONFIG_BCM63148 CONFIG_BCM4908),)
+obj-y += bcm_ethsw_phy_$(subst bcm,,$(subst ",,$(CONFIG_SYS_SOC))).o
+else
+obj-y += bcm_ethsw_phy_afe.o
+endif
+endif
+
+obj-$(CONFIG_BCMBCA_SYSPORT_V1) += bcmbca_sysport_v1.o
+obj-$(CONFIG_BCMBCA_SYSPORT_V2) += bcmbca_sysport_v2.o
+obj-$(CONFIG_BCMBCA_SF2_GMAC) += bcm-sf2-eth-gmac.o
+
+ifdef CONFIG_BCMBCA_EXT_SWITCH
+UBOOTINCLUDE += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/pmc
+obj-y += bcm_ethsw_ext.o bcm_ethsw_phy.o bcm_ethsw_phy_afe.o
+endif
+
diff --git a/drivers/net/bcmbca/bcm-sf2-eth-gmac.c b/drivers/net/bcmbca/bcm-sf2-eth-gmac.c
new file mode 100644
index 0000000000..7626cc4ffa
--- /dev/null
+++ b/drivers/net/bcmbca/bcm-sf2-eth-gmac.c
@@ -0,0 +1,513 @@
+/* SPDX-License-Identifier: GPL-2.0+
+*  *
+*   *  Copyright 2019 Broadcom Ltd.
+*    */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <phy.h>
+#include <asm/system.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include "pmc_drv.h"
+
+#include "asm/arch/gmac.h"
+#include "bcm_ethsw.h"
+
+/*---------------------------------------------------------------------*/
+/* specify number of BDs and buffers to use                            */
+/*---------------------------------------------------------------------*/
+#define NR_TX_BDS               40
+#define NR_RX_BDS               40
+#define ENET_ZLEN               60
+#define ENET_MAX_MTU_SIZE       1522    /* Body(1500) + EH_SIZE(14) + FCS(4) + VLAN(4) */
+#define DMA_MAX_BURST_LENGTH    8       /* in 64 bit words */
+#define ENET_BUF_SIZE           ((ENET_MAX_MTU_SIZE + 63) & ~63)
+#define DMA_FC_THRESH_LO        5
+#define DMA_FC_THRESH_HI        10
+#define EMAC_TX_WATERMARK       32
+
+// for now physical address = virtual
+#define  K0_TO_PHYS
+
+typedef struct sf2gmac_priv {
+
+	volatile GmacIntf *gmac_intf;
+	volatile GmacMac *gmac_mac;
+	volatile DmaRegs *dmaCtrl;
+
+	struct udevice *sf2_devp;
+	bcm_ethsw_ops_t *sf2_ops;
+	unsigned char *rcv_buffer;
+	int init;
+	
+	/* transmit variables */    
+	volatile DmaChannelCfg *txDma;      /* location of transmit DMA register set */
+	volatile DmaDesc *txBds;            /* Memory location of tx Dma BD ring */
+	volatile DmaDesc *txFirstBdPtr;     /* ptr to first allocated Tx BD */
+	volatile DmaDesc *txNextBdPtr;      /* ptr to next Tx BD to transmit with */
+	volatile DmaDesc *txLastBdPtr;      /* ptr to last allocated Tx BD */
+
+	/* receive variables */
+	volatile DmaChannelCfg *rxDma;      /* location of receive DMA register set */
+	volatile DmaDesc *rxBds;            /* Memory location of rx bd ring */
+	volatile DmaDesc *rxFirstBdPtr;     /* ptr to first allocated rx bd */
+	volatile DmaDesc *rxBdReadPtr;      /* ptr to next rx bd to be processed */
+	volatile DmaDesc *rxLastBdPtr;      /* ptr to last allocated rx bd */
+
+	uint8_t* rxBuffers;
+	uint8_t* txBuffers;
+
+} sf2gmac_priv;
+
+#define IncRxBdPtr(x, s) if (x == ((sf2gmac_priv *)s)->rxLastBdPtr) \
+                             x = ((sf2gmac_priv *)s)->rxBds; \
+                      else x++
+#define InctxBdPtr(x, s) if (x == ((sf2gmac_priv *)s)->txLastBdPtr) \
+                             x = ((sf2gmac_priv *)s)->txBds; \
+                      else x++
+
+
+#define DMA_RX_CHAN          0
+#define DMA_TX_CHAN          1
+
+#define CACHE_ALIGN     64
+
+
+/*
+ * init_dma: Initialize DMA control register
+ */
+
+#define NUM_PORTS	1 // only 1 port supported
+static void init_dma(struct sf2gmac_priv *softc)
+{
+	uint32_t *StateRam;
+	int i;
+
+	/*
+	 * clear State RAM
+	 */
+	StateRam = (uint32_t *)&softc->dmaCtrl->stram.s[0];
+	for (i = 0; i < sizeof(DmaStateRam) / sizeof(uint32_t) * NUM_PORTS * 2; i++)
+		StateRam[i] = 0;
+
+	/*
+	 * initialize IUDMA controller register
+	 */
+	softc->dmaCtrl->controller_cfg = DMA_FLOWC_CH1_EN;
+	softc->dmaCtrl->flowctl_ch1_thresh_lo = DMA_FC_THRESH_LO;
+	softc->dmaCtrl->flowctl_ch1_thresh_hi = DMA_FC_THRESH_HI;
+	softc->dmaCtrl->flowctl_ch1_alloc = 0;
+
+	// transmit
+	softc->txDma->cfg = 0;       /* initialize first (will enable later) */
+	softc->txDma->maxBurst = DMA_MAX_BURST_LENGTH;
+	softc->txDma->intMask = 0;   /* mask all ints */
+	/* clr any pending interrupts on channel */
+	softc->txDma->intStat = DMA_DONE|DMA_NO_DESC|DMA_BUFF_DONE;
+	softc->txDma->intMask = DMA_DONE;
+	softc->dmaCtrl->stram.s[DMA_TX_CHAN].baseDescPtr = (uint32_t)softc->txFirstBdPtr;
+
+	// receive
+	softc->rxDma->cfg = 0;  // initialize first (will enable later)
+	softc->rxDma->maxBurst = DMA_MAX_BURST_LENGTH;
+	softc->rxDma->intMask = 0;   /* mask all ints */
+	/* clr any pending interrupts on channel */
+	softc->rxDma->intStat = DMA_DONE|DMA_NO_DESC|DMA_BUFF_DONE;
+	softc->rxDma->intMask = DMA_DONE;
+	softc->dmaCtrl->stram.s[DMA_RX_CHAN].baseDescPtr = (uint32_t)softc->rxFirstBdPtr;
+}
+
+
+static void gmac_init(sf2gmac_priv *priv)
+{
+	volatile GmacIntf *GMAC_INTF = priv->gmac_intf;
+	volatile GmacMac *GMAC_MAC = priv->gmac_mac;
+
+	/* Reset GMAC */
+	GMAC_MAC->Cmd.sw_reset = 1;
+	udelay(20);
+	GMAC_MAC->Cmd.sw_reset = 0;
+
+	GMAC_INTF->Flush.txfifo_flush = 1;
+	GMAC_INTF->Flush.rxfifo_flush = 1;
+
+	GMAC_INTF->Flush.txfifo_flush = 0;
+	GMAC_INTF->Flush.rxfifo_flush = 0;
+
+	GMAC_INTF->MibCtrl.clrMib = 1;
+	GMAC_INTF->MibCtrl.clrMib = 0;
+
+	/* default CMD configuration */
+	GMAC_MAC->Cmd.eth_speed = CMD_ETH_SPEED_1000;
+
+	/* Disable Tx and Rx */
+	GMAC_MAC->Cmd.tx_ena = 0;
+	GMAC_MAC->Cmd.rx_ena = 0;
+
+	return;
+}
+
+static void gmac_enable_port(sf2gmac_priv *priv, int enable)
+{
+	volatile GmacMac *GMAC_MAC = priv->gmac_mac;
+
+	if( enable ) {
+		GMAC_MAC->Cmd.tx_ena = 1;
+		GMAC_MAC->Cmd.rx_ena = 1;
+	}
+	else {
+		GMAC_MAC->Cmd.tx_ena = 0;
+		GMAC_MAC->Cmd.rx_ena = 0;
+	}
+
+	return;
+}
+
+static int internal_open (struct sf2gmac_priv *softc)
+{
+	int i;
+	unsigned char *p;
+
+	softc->rxDma = &softc->dmaCtrl->chcfg[DMA_RX_CHAN];
+	softc->txDma = &softc->dmaCtrl->chcfg[DMA_TX_CHAN];
+
+	// If doing SW reboot in EPI the controller can still be active
+	softc->rxDma->cfg = 0;
+	softc->txDma->cfg = 0;
+	softc->dmaCtrl->controller_cfg &= ~DMA_MASTER_EN;
+
+	// noncached memory can only be allocated once
+	if (softc->txBds == NULL)
+	{
+		// allocate a chunk of non cached memory for packet descriptors
+		p = noncached_alloc((NR_TX_BDS + NR_RX_BDS) * sizeof(DmaDesc), CACHE_ALIGN);
+		if( p == NULL ) {
+			printf( "BCM63xx : Fail alloctxBds mem\n" );
+			return -1;
+		}
+
+		softc->txBds = (DmaDesc *)p;
+		p += (NR_TX_BDS * sizeof(DmaDesc));
+		softc->rxBds = (DmaDesc *)p;
+	}
+
+	// allocate memory for RX and TX data (cached memory)
+	softc->rxBuffers = (uint8_t*)memalign( CACHE_ALIGN, NR_RX_BDS * ENET_BUF_SIZE );
+	if( softc->rxBuffers == NULL ) {
+		printf( "BCM63xx : Failed allocRxBuffer mem\n" );
+		return -1;
+	}
+	invalidate_dcache_range((unsigned long)softc->rxBuffers, (unsigned long)softc->rxBuffers + NR_RX_BDS * ENET_BUF_SIZE);
+
+	softc->txBuffers = (uint8_t*)memalign( CACHE_ALIGN, NR_TX_BDS * ENET_BUF_SIZE );
+	if( softc->txBuffers == NULL ) {
+		printf( "BCM63xx : Failed alloc txBuffer mem\n" );
+		free( (void *)(softc->rxBuffers) );
+		softc->rxBuffers = NULL;
+		return -1;
+	}
+	invalidate_dcache_range((unsigned long)softc->txBuffers, (unsigned long)softc->txBuffers + NR_TX_BDS * ENET_BUF_SIZE);
+
+	/* Init the Receive Buffer Descriptor Ring. */
+	softc->rxFirstBdPtr = softc->rxBdReadPtr = softc->rxBds;     
+	softc->rxLastBdPtr = softc->rxBds + NR_RX_BDS - 1;
+
+	for(i = 0; i < NR_RX_BDS; i++) {
+		(softc->rxBds + i)->status  = DMA_OWN;
+		(softc->rxBds + i)->length  = ENET_BUF_SIZE;
+		(softc->rxBds + i)->address = K0_TO_PHYS( (uintptr_t)softc->rxBuffers + i * ENET_BUF_SIZE );
+		softc->dmaCtrl->flowctl_ch1_alloc = 1;
+	}
+	softc->rxLastBdPtr->status |= DMA_WRAP;
+
+	/* Init Transmit Buffer Descriptor Ring. */
+	softc->txFirstBdPtr = softc->txNextBdPtr =  softc->txBds;
+	softc->txLastBdPtr = softc->txBds + NR_TX_BDS - 1;
+
+	for(i = 0; i < NR_TX_BDS; i++) {
+		(softc->txBds + i)->status  = 0;
+		(softc->txBds + i)->length  = 0;
+		(softc->txBds + i)->address = K0_TO_PHYS( (uintptr_t)softc->txBuffers + i * ENET_BUF_SIZE );
+	}
+	softc->txLastBdPtr->status = DMA_WRAP;
+
+	/* init dma registers */
+	init_dma(softc);
+	softc->dmaCtrl->controller_cfg |= DMA_MASTER_EN;
+	softc->rxDma->cfg |= DMA_ENABLE;
+
+	softc->rcv_buffer = (unsigned char *)memalign(sizeof(int), ENET_BUF_SIZE);
+	if (softc->rcv_buffer == NULL) {
+		printf("failed to allocate receive buffer\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+static int bcmbca_sf2gmac_eth_start (struct udevice *dev)
+{
+	int rc = 0;
+	struct sf2gmac_priv *priv = dev_get_priv(dev);
+
+	debug("bcmbca_sf2gmac_eth_start called %s\n", dev->name);
+	if (priv->init)
+		return 0;
+
+	rc = internal_open(priv);
+	if (rc) {
+		printf("internal open failed rx %d\n", rc);
+		return rc;
+	}
+
+	if (priv->sf2_devp)
+		priv->sf2_ops->open (priv->sf2_devp);
+
+	gmac_init(priv);
+	gmac_enable_port(priv, 1);
+
+	priv->init = 1;
+	return 0;
+}
+
+static void bcmbca_sf2gmac_eth_stop(struct udevice *dev)
+{
+	struct sf2gmac_priv *priv = dev_get_priv(dev);
+
+	debug("bcmbca_sf2gmac_eth_stop called %s\n", dev->name);
+
+	return;
+}
+
+static int bcmbca_sf2gmac_eth_read_mac(struct udevice *dev)
+{
+	return 0;
+}
+
+static int bcmbca_sf2gmac_eth_send(struct udevice *dev, void *buffer, int length)
+{
+	volatile DmaDesc * CurrentBdPtr;
+	unsigned char * dstptr;
+	struct sf2gmac_priv *softc = dev_get_priv(dev);
+	uint32_t status, offset;
+	int timeout = 1000;
+
+	if (length > ENET_MAX_MTU_SIZE)
+	{
+		return -1;
+	}
+
+	CurrentBdPtr = softc->txNextBdPtr;
+
+	/* Find out if the next BD is available. */
+	if( CurrentBdPtr->status & DMA_OWN ) {
+		printf( "No tx BD available ?!\n" );
+		return -1;
+	}
+
+	dstptr = (unsigned char *)( CurrentBdPtr->address );
+	memcpy( dstptr, buffer, length );
+	flush_cache((unsigned long)dstptr, length);
+
+	/* Set status of DMA BD to be transmitted. */
+	status = DMA_SOP | DMA_EOP | DMA_APPEND_CRC | DMA_OWN;
+	if( CurrentBdPtr == softc->txLastBdPtr ) {
+		status |= DMA_WRAP;
+	}
+
+	CurrentBdPtr->length = length;
+	CurrentBdPtr->status = status;
+	
+	barrier();
+	softc->txDma->cfg |= DMA_ENABLE;
+
+	// poll dma status until done
+	do {
+		udelay(10);
+		invalidate_dcache_range((unsigned long)dstptr, (unsigned long)dstptr + CACHE_ALIGN);
+	} while((CurrentBdPtr->status & DMA_OWN) && timeout--);
+
+	if (timeout > 0) {
+		//Advance BD pointer to next in the chain.
+		InctxBdPtr( CurrentBdPtr, softc );
+		softc->txNextBdPtr = CurrentBdPtr;
+		return 0;
+	}
+	else {
+		printf("timeout sending packet of size %d\n", length);
+		// clear the buffer pointer and force the PD pointer 
+    	softc->txDma->intStat = DMA_DONE|DMA_NO_DESC|DMA_BUFF_DONE;
+		offset = softc->dmaCtrl->stram.s[DMA_TX_CHAN].state_data & RING_OFFSET_MASK;
+		softc->txNextBdPtr = (volatile DmaDesc *)((unsigned char *)softc->txFirstBdPtr + (offset * sizeof(DmaDesc)));
+		return -1;
+	}
+}
+
+static int bcmbca_sf2gmac_eth_recv(struct udevice *dev, int flags, uchar ** packetp)
+{
+	int length, rc = 0;
+	uint16_t dmaFlag;
+	uint8_t *srcptr;
+	volatile DmaDesc * CurrentBdPtr;
+	struct sf2gmac_priv *softc = dev_get_priv(dev);
+
+	dmaFlag = (uint16_t) softc->rxBdReadPtr->status;
+
+	if (!(dmaFlag & DMA_EOP)) {
+		return -1;
+	}
+
+	CurrentBdPtr = softc->rxBdReadPtr;
+	srcptr = CurrentBdPtr->address;
+
+	length = CurrentBdPtr->length;
+
+	if (length == ENET_BUF_SIZE || length < ENET_ZLEN || length > ENET_MAX_MTU_SIZE)
+	{
+		printf("received data length is incorrect %d\n", length);
+		rc = -1;
+		goto out;
+	}
+	invalidate_dcache_range((unsigned long)srcptr, (unsigned long)srcptr + ENET_BUF_SIZE);
+	barrier();
+
+	*packetp = softc->rcv_buffer;
+
+	memcpy (*packetp, srcptr, length);
+	rc = length;
+
+out:
+	CurrentBdPtr->length = ENET_BUF_SIZE;
+	CurrentBdPtr->status &= DMA_WRAP;
+	CurrentBdPtr->status |= DMA_OWN;
+
+	IncRxBdPtr( CurrentBdPtr, softc );
+	softc->rxBdReadPtr = CurrentBdPtr;
+	softc->dmaCtrl->flowctl_ch1_alloc = 1;
+
+	// enable rx dma
+	softc->rxDma->cfg = DMA_ENABLE;
+	return rc;
+}
+
+static int sf2gmac_free_pkt (struct udevice *dev, uchar *packet, int length)
+{
+	struct sf2gmac_priv *priv = dev_get_priv(dev);
+	if (packet != priv->rcv_buffer)
+		printf("why free this? %p\n", packet);
+
+	return 0;
+}
+
+static const struct eth_ops sf2gmac_eth_ops = {
+	.start = bcmbca_sf2gmac_eth_start,
+	.send = bcmbca_sf2gmac_eth_send,
+	.recv = bcmbca_sf2gmac_eth_recv,
+	.stop = bcmbca_sf2gmac_eth_stop,
+	.free_pkt = sf2gmac_free_pkt,
+	.read_rom_hwaddr = bcmbca_sf2gmac_eth_read_mac,
+};
+
+static int sf2gmac_probe (struct udevice *dev)
+{
+	int ret=0, size;
+	struct resource res;
+	struct udevice *sf2_devp;
+	struct sf2gmac_priv *priv = dev_get_priv(dev);
+	uint phandle_id;
+	const fdt32_t *list;
+
+	ret = dev_read_resource_byname(dev, "gmac-intf-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs gmac-intf-base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->gmac_intf = devm_ioremap(dev, res.start, resource_size(&res));
+
+	ret = dev_read_resource_byname(dev, "gmac-mac-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs gmac-mac-base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->gmac_mac = devm_ioremap(dev, res.start, resource_size(&res));
+
+	ret = dev_read_resource_byname(dev, "gmac-dma-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs gmac-dma-base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->dmaCtrl = devm_ioremap(dev, res.start, resource_size(&res));
+
+	priv->sf2_devp = NULL;
+	list = dev_read_prop (dev, "ethsw", &size);
+	if (size > 0) {
+		phandle_id = fdt32_to_cpu(*list);
+		if (!uclass_get_device_by_phandle_id(UCLASS_NOP, phandle_id, &sf2_devp))
+		{
+			printf("sf2 found, should have been probed name %s driver name %s\n", 
+			sf2_devp->name, sf2_devp->driver->name);
+			priv->sf2_devp = sf2_devp;
+			priv->sf2_ops = dev_get_priv(sf2_devp);
+			priv->sf2_ops->init (priv->sf2_devp);
+			PowerOnDevice(PMB_ADDR_GMAC);
+		}
+	}
+	// in case sf2 is not initialized, the sf2 gmac network interface will not work
+	if (priv->sf2_devp == NULL) {
+		printf("cannot find the pairing SF2 driver\n");
+		return -1;
+	}
+
+	priv->txBds = NULL;
+	priv->rxBds = NULL;	
+	priv->init = 0;
+
+	return 0;
+}
+
+static int sf2gmac_remove(struct udevice *dev)
+{
+	struct sf2gmac_priv *priv = dev_get_priv(dev);
+
+	if (!priv->init)
+		return 0;
+
+	if (priv->sf2_devp)
+		priv->sf2_ops->close (priv->sf2_devp);
+
+	gmac_enable_port(priv, 0);
+
+	free( (void *)(priv->rcv_buffer) );
+	free( (void *)(priv->rxBuffers) );
+	free( (void *)(priv->txBuffers) );
+	priv->rxBuffers = NULL;
+	priv->txBuffers = NULL;
+	priv->init = 0;
+	PowerOffDevice(PMB_ADDR_GMAC, 0);
+
+	return 0;
+}
+
+static const struct udevice_id bcmbca_sf2gmac_match_ids[] = {
+	{ .compatible = "brcm,bcmbca-sf2gmac"},
+	{ }
+};
+
+
+U_BOOT_DRIVER(sf2gmac) = {
+	.name	= "sf2-gmac",
+	.id	= UCLASS_ETH,
+	.of_match = bcmbca_sf2gmac_match_ids,
+	.flags  = DM_REMOVE_ACTIVE_ALL,
+	.probe	= sf2gmac_probe,
+	.remove	= sf2gmac_remove,
+	.ops	= &sf2gmac_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct sf2gmac_priv),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
diff --git a/drivers/net/bcmbca/bcm_ethsw.h b/drivers/net/bcmbca/bcm_ethsw.h
new file mode 100755
index 0000000000..35ebc9ef87
--- /dev/null
+++ b/drivers/net/bcmbca/bcm_ethsw.h
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2013 Broadcom
+ */
+/*
+ * 
+ */
+
+/* From boardparam.h */
+#define PHY_ADV_CAP_CFG_M       0x3F
+#define PHY_ADV_CAP_CFG_S       12
+#define ADVERTISE_10HD          (1 << PHY_ADV_CAP_CFG_S)
+#define ADVERTISE_10FD          (2 << PHY_ADV_CAP_CFG_S)
+#define ADVERTISE_100HD         (4 << PHY_ADV_CAP_CFG_S)
+#define ADVERTISE_100FD         (8 << PHY_ADV_CAP_CFG_S)
+#define ADVERTISE_1000HD        (16 << PHY_ADV_CAP_CFG_S)
+#define ADVERTISE_1000FD        (32 << PHY_ADV_CAP_CFG_S)
+#define ADVERTISE_ALL_GMII      (ADVERTISE_10HD | ADVERTISE_10FD | ADVERTISE_100HD | ADVERTISE_100FD | ADVERTISE_1000HD | ADVERTISE_1000FD)
+#define ADVERTISE_ALL_MII       (ADVERTISE_10HD | ADVERTISE_10FD | ADVERTISE_100HD | ADVERTISE_100FD)
+
+#define PHY_ADV_CFG_VALID_M     1
+#define PHY_ADV_CFG_VALID_S     18
+#define PHY_ADV_CFG_VALID       (PHY_ADV_CFG_VALID_M << PHY_ADV_CFG_VALID_S)
+
+#define MAC_CONN_M              0x1
+#define MAC_CONN_S              21
+#define MAC_CONNECTION          (MAC_CONN_M << MAC_CONN_S)
+#define MAC_PHY_IF              (0 << MAC_CONN_S)
+#define MAC_MAC_IF              (1 << MAC_CONN_S)
+
+#define MAC_CONN_VALID_M        1
+#define MAC_CONN_VALID_S        22
+#define MAC_CONN_VALID          (MAC_CONN_VALID_M << MAC_CONN_VALID_S)
+
+#define PHYID_LSBYTE_M           0xFF
+#define BCM_PHY_ID_M             0x1F
+
+#define IsPhyConnected(id)  (((id) & MAC_CONN_VALID)?(((id) & MAC_CONNECTION) != MAC_MAC_IF):(((id) & PHYID_LSBYTE_M) != 0xFF))
+#define IsPhyAdvCapConfigValid(id) (((id) & PHY_ADV_CFG_VALID)?1:0)
+
+#define K1CTL_REPEATER_DTE 0x400
+#if !defined(K1CTL_1000BT_FDX)
+#define K1CTL_1000BT_FDX 	0x200
+#endif
+#if !defined(K1CTL_1000BT_HDX)
+#define K1CTL_1000BT_HDX 	0x100
+#endif
+
+#define ETHSW_MDIO_BUSY                       (1 << 29)
+#define ETHSW_MDIO_FAIL                       (1 << 28)
+#define ETHSW_MDIO_CMD_SHIFT                  26
+#define ETHSW_MDIO_CMD_MASK                   (0x3<<ETHSW_MDIO_CMD_SHIFT) 
+#define ETHSW_MDIO_CMD_C22_READ               2
+#define ETHSW_MDIO_CMD_C22_WRITE              1
+#define ETHSW_MDIO_C22_PHY_ADDR_SHIFT         21
+#define ETHSW_MDIO_C22_PHY_ADDR_MASK          (0x1f<<ETHSW_MDIO_C22_PHY_ADDR_SHIFT)
+#define ETHSW_MDIO_C22_PHY_REG_SHIFT          16
+#define ETHSW_MDIO_C22_PHY_REG_MASK           (0x1f<<ETHSW_MDIO_C22_PHY_REG_SHIFT)
+#define ETHSW_MDIO_PHY_DATA_SHIFT             0
+#define ETHSW_MDIO_PHY_DATA_MASK              (0xffff<<ETHSW_MDIO_PHY_DATA_SHIFT)
+
+typedef struct sw_mdio {
+	uint32_t mdio_cmd;
+	uint32_t mdio_cfg;
+
+} sw_mdio;
+
+typedef struct bcm_ethsw_ops_t
+{
+    void (*init)(struct udevice *dev);
+    void (*open)(struct udevice *dev);
+    void (*close)(struct udevice *dev);
+} bcm_ethsw_ops_t;
+
+uint16_t bcm_ethsw_phy_read_reg(int phy_id, int reg);
+void bcm_ethsw_phy_write_reg(int phy_id, int reg, uint16_t data);
+
+
+
+void phy_advertise_caps(unsigned int phy_id);
+void gphy_powerup(int phy_base, u32 wkard_timeout, void *sphy_ctrl, void *qphy_ctrl, void *phy_test_ctrl);
+void phy_set_mdio_base(volatile sw_mdio *switch_mdio);
+
+#if defined(__UBOOT__)
+#define mii_write bcm_ethsw_phy_write_reg
+#define mii_read  bcm_ethsw_phy_read_reg
+#endif
diff --git a/drivers/net/bcmbca/bcm_ethsw_ext.c b/drivers/net/bcmbca/bcm_ethsw_ext.c
new file mode 100755
index 0000000000..4c89fa6cbf
--- /dev/null
+++ b/drivers/net/bcmbca/bcm_ethsw_ext.c
@@ -0,0 +1,596 @@
+/* SPDX-License-Identifier: GPL-2.0+
+*  *
+*   *  Copyright 2019 Broadcom Ltd.
+*    */
+
+
+#include <config.h>
+#include <common.h>
+#include <stdlib.h>
+#include <dm.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+
+//#include "asm/arch/ethsw.h"
+#include "mii_shared.h"
+//#include "pmc_drv.h"
+//#include "pmc_switch.h"
+#include "bcm_ethsw.h"
+
+#define BP_MAX_SWITCH_PORTS                     8
+#define BP_MAX_ENET_MACS                        2
+#if 0
+#define ETHSW_MDIO_BUSY                       (1 << 29)
+#define ETHSW_MDIO_FAIL                       (1 << 28)
+#define ETHSW_MDIO_CMD_SHIFT                  26
+#define ETHSW_MDIO_CMD_MASK                   (0x3<<ETHSW_MDIO_CMD_SHIFT) 
+#define ETHSW_MDIO_CMD_C22_READ               2
+#define ETHSW_MDIO_CMD_C22_WRITE              1
+#define ETHSW_MDIO_C22_PHY_ADDR_SHIFT         21
+#define ETHSW_MDIO_C22_PHY_ADDR_MASK          (0x1f<<ETHSW_MDIO_C22_PHY_ADDR_SHIFT)
+#define ETHSW_MDIO_C22_PHY_REG_SHIFT          16
+#define ETHSW_MDIO_C22_PHY_REG_MASK           (0x1f<<ETHSW_MDIO_C22_PHY_REG_SHIFT)
+#define ETHSW_MDIO_PHY_DATA_SHIFT             0
+#define ETHSW_MDIO_PHY_DATA_MASK              (0xffff<<ETHSW_MDIO_PHY_DATA_SHIFT)
+
+typedef struct sw_mdio {
+	uint32_t mdio_cmd;
+	uint32_t mdio_cfg;
+	uint32_t mdio_lvl_irq_clr;
+	uint32_t mdio_lvl_irq_msk;
+
+} sw_mdio;
+#endif
+struct bcmbca_extsw_priv {
+	bcm_ethsw_ops_t ops;
+	volatile uint32_t *serdes_cntrl;
+	int ext_sw_sgmii;
+	void *rgmii_ctrl;
+	void *gpio_pad_ctrl;
+	void *rgmii_select;
+};
+
+#if defined(CONFIG_BCM6756)
+#define     RGMII_VER7  7   /* for 6756 device          rgmii_ctrl   gpio_pad_ctrl */
+#endif
+ 
+typedef struct {
+    int delay_rx, delay_tx;
+    int is_1p8v, is_3p3v;
+    int pin_offset;
+} rgmii_params;
+
+#define RGMII_CTRL_REG                  (priv->rgmii_ctrl + 0)
+#define RGMII_RX_CLOCK_DELAY_CNTRL      (priv->rgmii_ctrl + 8)
+#define RGMII_SELECT                    (priv->rgmii_select)
+
+#define GPIO_PAD_CTRL               (priv->gpio_pad_ctrl + 0x0040)
+#define GPIO_TestPortBlkDataMsb     (priv->gpio_pad_ctrl + 0x0054)
+#define GPIO_TestPortBlkDataLsb     (priv->gpio_pad_ctrl + 0x0058)
+#define GPIO_TestPortCommand        (priv->gpio_pad_ctrl + 0x005c)
+
+#define LOAD_PAD_CTRL_CMD           0x22
+
+#define DEVICE_ADDRESS(_a) ((volatile uint8_t * const)(_a))
+#define WRITE_32(a, r) writel(*(uint32_t *)&(r), DEVICE_ADDRESS(a))
+#define READ_32(a, r) (*(volatile uint32_t *)&(r) = readl(DEVICE_ADDRESS(a)))
+
+static void bcm_set_padctrl(struct bcmbca_extsw_priv *priv, unsigned int pin_num, unsigned int pad_ctrl)
+{
+    unsigned int tp_blk_data_msb, tp_blk_data_lsb, tp_cmd;
+
+    tp_cmd = LOAD_PAD_CTRL_CMD;
+    tp_blk_data_msb = 0;
+    tp_blk_data_lsb = 0;
+    tp_blk_data_lsb |= pin_num;
+    tp_blk_data_lsb |= pad_ctrl;
+
+    WRITE_32(GPIO_TestPortBlkDataMsb, tp_blk_data_msb);
+    WRITE_32(GPIO_TestPortBlkDataLsb, tp_blk_data_lsb);
+    WRITE_32(GPIO_TestPortCommand, tp_cmd);
+}
+
+static void bcm_misc_hw_xmii_pads_init(struct bcmbca_extsw_priv *priv, rgmii_params *params)
+{
+    int num;
+    uint32_t tp_data;
+    uint32_t pad_ctrl;
+
+    for (num = 0; num < 12; num++)
+    {
+        tp_data = 0;
+#if defined(RGMII_VER7)
+        tp_data |= (6 /*14mA*/ << 12);
+        tp_data |= (((params->is_1p8v && (num < 6)) ? 1 : 0) << 15);    /* pad_amp_en */
+        tp_data |= ((num < 6 ? 0 : 1) << 16);       /*pad_ind - 0 for RX pads, 1 for TX pads */
+#else
+        tp_data |= (6 /*14mA*/ << 12);
+        tp_data |= ((params->is_1p8v ? 1 : 0) << 15);   /* pad_amp_en */
+        tp_data |= ((params->is_3p3v ? 1 : 0) << 17);   /* pad_sel_gmii */
+        tp_data |= ((num < 6 ? 0 : 1) << 16);       /*pad_ind - 0 for RX pads, 1 for TX pads */
+#endif
+        bcm_set_padctrl(priv, num+params->pin_offset, tp_data);
+    }
+}
+
+void rgmii_attach(struct udevice *dev, rgmii_params *params)
+{
+	struct bcmbca_extsw_priv *priv = dev_get_priv(dev);
+    uint32_t val;
+
+    READ_32(RGMII_CTRL_REG, val);
+    val |= (1 << 0);  /* RGMII_MODE_EN=1 */
+    val &= ~(7 << 2); /* Clear PORT_MODE */
+    val |= (3 << 2);  /* RGMII mode */
+
+    if (params->delay_tx)
+        val &= ~(1 << 1); /* ID_MODE_DIS=0 */
+    else
+        val |= (1 << 1); /* ID_MODE_DIS=1 */
+    WRITE_32(RGMII_CTRL_REG, val);
+
+#if defined(RGMII_VER7)
+    val = (params->delay_rx) ? 0xc8 : 0xe8 /*RXCLK_DLY_MODE_BYPASS*/;
+#else
+    val = (params->delay_rx) ? 0xc8 : 0xf8 /*ETHSW_RXCLK_IDDQ|ETHSW_RXCLK_BYPASS*/;
+#endif
+    WRITE_32(RGMII_RX_CLOCK_DELAY_CNTRL, val);
+
+    READ_32(GPIO_PAD_CTRL, val);
+#if defined(RGMII_VER7)
+    if (params->is_1p8v)
+        val &= ~(1 << 8);
+    else
+        val |= (1 << 8); /* rgmii_0_pad_modehv = 1 */
+#else
+    if (params->is_1p8v)
+        val = (val & ~(1<<8)) | (1<<10);             // 1.8v: & ~MISC_XMII_PAD_MODEHV | MISC_XMII_PAD_AMP_EN
+    else if (params->is_3p3v)
+        val = (val | (1<<8)) | (1<<9) & ~(1<<10);    // 3.3v: | MISC_XMII_PAD_MODEHV | MISC_XMII_PAD_SEL_GMII & ~MISC_XMII_PAD_AMP_EN
+    else
+        val = (val | (1<<8)) & ~(1<<9) & ~(1<<10);   // 2.5v: | MISC_XMII_PAD_MODEHV & ~MISC_XMII_PAD_SEL_GMII & ~MISC_XMII_PAD_AMP_EN
+#endif
+    WRITE_32(GPIO_PAD_CTRL, val);
+    
+    bcm_misc_hw_xmii_pads_init(priv, params);
+    if (RGMII_SELECT) {
+        val = 2;
+        WRITE_32(RGMII_SELECT, val);      // set crossbar to RGMII
+    }
+}
+
+//static volatile struct sw_mdio *ETHSW_MDIO = NULL;
+static int ext_sw_id = 0;
+static int ext_sw_sgmii = 0;
+
+//// external switch defintion & operations
+#define PBMAP_MIPS 0x100
+
+static uint32_t sw_rreg(int page, int reg, int len)
+{
+    uint16_t val;
+    uint32_t data32 = 0;
+    uint16_t *data = (uint16_t *)&data32;
+    int i;
+
+    val = (page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT) | REG_PPM_REG16_MDIO_ENABLE;
+    bcm_ethsw_phy_write_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG16, val);
+
+    val = (reg << REG_PPM_REG17_REG_NUMBER_SHIFT) | REG_PPM_REG17_OP_READ;
+    bcm_ethsw_phy_write_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG17, val);
+
+    for (i = 0; i < 20; i++) {
+        val = bcm_ethsw_phy_read_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG17);
+        if ((val & (REG_PPM_REG17_OP_WRITE | REG_PPM_REG17_OP_READ)) == REG_PPM_REG17_OP_DONE)
+            break;
+        udelay(10);
+    }
+
+    if (i >= 20) {
+        printf("sf2_rreg: mdio timeout!\n");
+        return data32;
+    }
+
+    switch (len) {
+    case 1:
+        val = bcm_ethsw_phy_read_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG24);
+        data[0] = (uint8_t)val; break;
+    case 2:
+        val = bcm_ethsw_phy_read_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG24);
+        data[0] = val; break;
+    case 4:
+        val = bcm_ethsw_phy_read_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG24);
+        data[0] = val;
+        val = bcm_ethsw_phy_read_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG25);
+        data[1] = val; break;
+    default:
+        printf("%s: len = %d NOT Handled !! \n", __FUNCTION__, len);
+        break;
+    }
+    //printk("sf2_rreg(page=%x reg=%x len=%d %04x %04x %04x %04x)\n", page, reg, len, data[0], data[1], data[2],data[3]);
+    return data32;
+}
+
+static void sw_wreg(int page, int reg, uint32_t data_in, int len)
+{
+    uint16_t val;
+    uint16_t *data = (uint16_t *)&data_in;
+    int i;
+
+    val = (page << REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT) | REG_PPM_REG16_MDIO_ENABLE;
+    bcm_ethsw_phy_write_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG16, val);
+
+    switch (len) {
+    case 1:
+        val = (uint8_t)(data[0]);
+        bcm_ethsw_phy_write_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG24, val); break;
+    case 2:
+        bcm_ethsw_phy_write_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG24, data[0]); break;
+    case 4:
+        bcm_ethsw_phy_write_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG24, data[0]);
+        bcm_ethsw_phy_write_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG25, data[1]); break;
+    default:
+        printf("%s: len = %d NOT Handled !! \n", __FUNCTION__, len);
+        return;
+    }
+
+    val = (reg << REG_PPM_REG17_REG_NUMBER_SHIFT) | REG_PPM_REG17_OP_WRITE;
+    bcm_ethsw_phy_write_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG17, val);
+
+    for (i = 0; i < 20; i++) {
+        val = bcm_ethsw_phy_read_reg(PSEUDO_PHY_ADDR, REG_PSEUDO_PHY_MII_REG17);
+        if ((val & (REG_PPM_REG17_OP_WRITE | REG_PPM_REG17_OP_READ)) == REG_PPM_REG17_OP_DONE)
+            break;
+        udelay(10);
+    }
+
+    if (i >= 20)
+        printf("sf2_wreg: mdio timeout!\n");
+}
+
+static void sw_reset(unsigned short configType)
+{
+    //uint32_t val;
+    
+    // todo: check (configType == BP_ENET_CONFIG_MDIO), now assume MDIO
+    ext_sw_id = sw_rreg(PAGE_MANAGEMENT, REG_DEVICE_ID, 4);
+    printf("Software Resetting Switch (Id=%x) ... ", ext_sw_id);
+    //val = sw_rreg(PAGE_CONTROL, SOFTWARE_RESET_CTRL, 1);
+    //sw_wreg(PAGE_CONTROL, SOFTWARE_RESET_CTRL, val|SOFTWARE_RESET|EN_SW_RST, 1);
+    sw_wreg(PAGE_CONTROL, SOFTWARE_RESET_CTRL, 0x83, 1);
+    for (; sw_rreg(PAGE_CONTROL, SOFTWARE_RESET_CTRL, 1)&SOFTWARE_RESET;) udelay(100);
+    printf("Done.\n");
+    udelay(1000);
+}
+
+static void sw_hw_ready(void)
+{
+    int i;
+
+	printf("switch id 0x%x\n", ext_sw_id);
+    if (!ext_sw_id) return;
+    printf("Waiting MAC port Rx/Tx to be enabled by hardware ...");
+    for( i = 0; i < BP_MAX_SWITCH_PORTS; i++ )
+    {
+        /* Wait until hardware enable the ports, or we will kill the hardware */
+        for(;sw_rreg(PAGE_CONTROL,PORT_CTRL_PORT+i,1) & PORT_CTRL_RX_DISABLE; udelay(100));
+    }
+}
+
+static void sw_setup(void)
+{
+    int i;
+    uint32_t val;
+
+    if (!ext_sw_id) return;
+
+    // check switch SGMII/RGMII boardparam matching 53134 strap value, if not display warning
+    val = sw_rreg(PAGE_STATUS,REG_STRAP_VAL,4);
+    if (val&REG_STRAP_P8_SEL_SGMII)
+    {
+        if (!ext_sw_sgmii) printk("\n!!!! Error: 53134 P8_SEL_SGMII is strapped high, but boardId selected is using RGMII interconnect.!!!!\n\n");
+    }
+    else
+    {
+        if (ext_sw_sgmii) printk("\n!!!! Error: 53134 P8_SEL_SGMII is strapped low, but boardId selected is using SGMII interconnect.!!!!\n\n");
+    }
+
+    printk("Disable Switch All MAC port Rx/Tx\n");
+    for( i = 0; i < BP_MAX_SWITCH_PORTS; i++ )
+    {
+        val = sw_rreg(PAGE_CONTROL,PORT_CTRL_PORT+i,1);
+        sw_wreg(PAGE_CONTROL, PORT_CTRL_PORT+i, val|PORT_CTRL_RXTX_DISABLE, 1);
+    }
+
+    /* Set switch to unmanaged mode and enable forwarding */
+    val = sw_rreg(PAGE_CONTROL,REG_SWITCH_MODE,1) | REG_SWITCH_MODE_SW_FWDG_EN | REG_SWITCH_MODE_RETRY_LIMIT_DIS;
+    sw_wreg(PAGE_CONTROL,REG_SWITCH_MODE, val & ~REG_SWITCH_MODE_FRAME_MANAGE_MODE, 1);
+    sw_wreg(PAGE_MANAGEMENT,REG_BRCM_HDR_CTRL,0,1);
+    val = sw_rreg(PAGE_CONTROL,REG_SWITCH_CONTROL,2) | REG_SWITCH_CONTROL_MII_DUMP_FWD_EN;
+    sw_wreg(PAGE_CONTROL,REG_SWITCH_CONTROL,val,2);
+    val = REG_CONTROL_MPSO_MII_SW_OVERRIDE|REG_CONTROL_MPSO_FLOW_CONTROL|REG_CONTROL_MPSO_SPEED1000|REG_CONTROL_MPSO_FDX|REG_CONTROL_MPSO_LINKPASS;
+    sw_wreg(PAGE_CONTROL,REG_CONTROL_MII1_PORT_STATE_OVERRIDE,val,1);
+
+    if (ext_sw_sgmii)
+    {
+        sw_wreg(0xe6, 0x00, 0x0001, 1);
+        sw_wreg(0x14, 0x3e, 0x8000, 2);  // BLK0 Block Address
+        sw_wreg(0x14, 0x20, 0x0c2f, 2);  // disable pll start sequencer
+        sw_wreg(0x14, 0x3e, 0x8300, 2);  // Digital Block Address
+        sw_wreg(0x14, 0x20, 0x010d, 2);  // enable fiber mode
+        sw_wreg(0x14, 0x30, 0xc010, 2);  // force 2.5G fiber enable, 50Mhz refclk
+
+        sw_wreg(0x14, 0x3e, 0x8340, 2);  // Digital5 Block Addres
+        sw_wreg(0x14, 0x34, 0x0001, 2);  // set os2 mode
+        sw_wreg(0x14, 0x3e, 0x8000, 2);  // BLK0 Block Address
+        sw_wreg(0x14, 0x00, 0x0140, 2);  // disable AN, set 1G mode
+        sw_wreg(0x14, 0x20, 0x2c2f, 2);  // enable pll start sequencer
+
+        sw_wreg(PAGE_CONTROL, 0x5d, 0x004a, 1); // port 5 override  no override
+        sw_wreg(PAGE_CONTROL, 0x0e, 0x008b, 1); // imp port override 2.5g duplex link up
+    }
+}
+
+static int saved = 0; 
+static uint32_t portCtrl[BP_MAX_SWITCH_PORTS], pbvlan[BP_MAX_SWITCH_PORTS];
+
+static void sw_reg_save(void)
+{
+    int i;
+
+    if (saved) return;
+    saved = 1;
+    for( i = 0; i < BP_MAX_SWITCH_PORTS; i++ )
+    {
+        portCtrl[i] = sw_rreg(PAGE_CONTROL,PORT_CTRL_PORT+i,1);
+        pbvlan[i] = sw_rreg(PAGE_PORT_BASED_VLAN,REG_VLAN_CTRL_P0+i*2,2);
+    }
+}
+
+static void sw_reg_restore(void)
+{
+    int i;
+    uint32_t val;
+
+    if (!saved) return;
+    for( i = 0; i < BP_MAX_SWITCH_PORTS; i++ )
+    {
+        val = sw_rreg(PAGE_CONTROL,PORT_CTRL_PORT+i,1) & PORT_CTRL_SWITCH_RESERVE;
+        val |= portCtrl[i] & ~PORT_CTRL_SWITCH_RESERVE;
+        sw_wreg(PAGE_CONTROL,PORT_CTRL_PORT+i,val,1);
+        sw_wreg(PAGE_PORT_BASED_VLAN,REG_VLAN_CTRL_P0+i*2, pbvlan[i],2);
+    }
+}
+
+static void sw_open(void)
+{
+    int i;
+    uint32_t val;
+
+    if (!ext_sw_id) return;
+    sw_reg_save();
+
+    printk ("Enable Switch MAC Port Rx/Tx, set PBVLAN to FAN out, set switch to NO-STP.\n");
+    for( i = 0; i < BP_MAX_SWITCH_PORTS; i++ )
+    {
+        /* Set Port VLAN to allow CPU traffic only */
+        sw_wreg(PAGE_PORT_BASED_VLAN,REG_VLAN_CTRL_P0+i*2,PBMAP_MIPS,2);
+
+        /* Setting switch to NO-STP mode; enable port TX/RX. */
+        val = sw_rreg(PAGE_CONTROL,PORT_CTRL_PORT+i,1) & (~(PORT_CTRL_RXTX_DISABLE|PORT_CTRL_PORT_STATUS_M));
+        sw_wreg(PAGE_CONTROL,PORT_CTRL_PORT+i,val|PORT_CTRL_NO_STP,1);
+    }
+}
+
+static void sw_close(void)
+{
+    if (!ext_sw_id) return;
+    //sw_reg_restore();
+}
+
+static uint16_t serdesRef50mVco6p25 [] =
+{
+    0x8000, 0x0c2f,
+    0x8308, 0xc000,
+    0x8050, 0x5740,
+    0x8051, 0x01d0,
+    0x8052, 0x19f0,
+    0x8053, 0xaab0,
+    0x8054, 0x8821,
+    0x8055, 0x0044,
+    0x8056, 0x8000,
+    0x8057, 0x0872,
+    0x8058, 0x0000,
+
+    0x8106, 0x0020,
+    0x8054, 0x8021,
+    0x8054, 0x8821,
+};
+
+static uint16_t serdesSet2p5GFiber [] =
+{
+    0x0010, 0x0C2F,       /* disable pll start sequencer */
+    0x8066, 0x0009,       /* Set AFE for 2.5G */
+    0x8065, 0x1620,       
+    0x8300, 0x0149,       /* enable fiber mode, also depend board parameters */
+    0x8308, 0xC010,       /* Force 2.5G Fiber, enable 50MHz refclk */
+    0x834a, 0x0001,       /* Set os2 mode */
+    0x0000, 0x0140,       /* disable AN, set 1G mode */
+    0x0010, 0x2C2F,       /* enable pll start sequencer */
+};
+
+uint16_t phy_read_ext_bank_reg(int phy_id, int reg)
+{
+    uint16_t bank = reg & BRCM_MIIEXT_BANK_MASK;;
+    uint16_t offset = (reg & BRCM_MIIEXT_OFF_MASK) + BRCM_MIIEXT_OFFSET;
+    uint16_t val;
+    
+    bcm_ethsw_phy_write_reg(phy_id, BRCM_MIIEXT_BANK, bank);
+    val = bcm_ethsw_phy_read_reg(phy_id, offset);
+    if (bank != BRCM_MIIEXT_DEF_BANK || offset == BRCM_MIIEXT_OFFSET)
+        bcm_ethsw_phy_write_reg(phy_id, BRCM_MIIEXT_BANK, BRCM_MIIEXT_DEF_BANK);
+        
+    return val;
+}
+
+void phy_write_ext_bank_reg(int phy_id, uint16_t reg, uint16_t data)
+{
+    uint16_t bank = reg & BRCM_MIIEXT_BANK_MASK;;
+    uint16_t offset = (reg & BRCM_MIIEXT_OFF_MASK) + BRCM_MIIEXT_OFFSET;
+
+    bcm_ethsw_phy_write_reg(phy_id, BRCM_MIIEXT_BANK, bank);
+    bcm_ethsw_phy_write_reg(phy_id, offset, data);
+    if (bank != BRCM_MIIEXT_DEF_BANK || offset == BRCM_MIIEXT_OFFSET)
+        bcm_ethsw_phy_write_reg(phy_id, BRCM_MIIEXT_BANK, BRCM_MIIEXT_DEF_BANK);
+}
+
+static void config_serdes(int phy_addr, uint16_t seq[], int seqSize)
+{
+    int i;
+    seqSize /= sizeof(seq[0]);
+    for (i=0; i<seqSize; i+=2)
+        if (seq[i] < 0x20)  // CL22 space
+            bcm_ethsw_phy_write_reg(phy_addr, seq[i], seq[i+1]);
+        else
+            phy_write_ext_bank_reg(phy_addr, seq[i], seq[i+1]);
+}
+
+#define SWITCH_REG_SERDES_IDDQ       (1<<0)
+#define SWITCH_REG_SERDES_PWRDWN     (1<<1)
+#define SWITCH_REG_SERDES_RESETPLL   (1<<3)
+#define SWITCH_REG_SERDES_RESETMDIO  (1<<4)
+#define SWITCH_REG_SERDES_RESET      (1<<5)
+
+static void phy_sgmii_init(volatile uint32_t *serdes_regp)
+{
+    int phy_addr = ext_sw_sgmii & BCM_PHY_ID_M;
+    uint32_t val32 = *serdes_regp;
+    
+    val32 |= SWITCH_REG_SERDES_RESETPLL|SWITCH_REG_SERDES_RESETMDIO|SWITCH_REG_SERDES_RESET;
+    val32 &= ~(SWITCH_REG_SERDES_IDDQ|SWITCH_REG_SERDES_PWRDWN);
+    *serdes_regp = val32;
+    udelay(1000);
+    val32 &= ~(SWITCH_REG_SERDES_RESETPLL|SWITCH_REG_SERDES_RESETMDIO|SWITCH_REG_SERDES_RESET);
+    *serdes_regp = val32;
+    udelay(1000);
+
+    // do dummy MDIO read to workaround ASIC problem
+    bcm_ethsw_phy_read_reg(phy_addr, 0);
+
+    config_serdes(phy_addr, serdesRef50mVco6p25, sizeof(serdesRef50mVco6p25));
+    udelay(1000);
+    // serdesSet2p5GFiber
+    config_serdes(phy_addr, serdesSet2p5GFiber, sizeof(serdesSet2p5GFiber));
+}
+
+static void bcm_ethsw_ext_init (struct udevice *dev)
+{
+	struct bcmbca_extsw_priv *priv = dev_get_priv(dev);
+    rgmii_params params = {};
+
+	sw_setup();
+	if (priv->rgmii_ctrl) {
+	    params.delay_rx = 1; params.delay_tx = 1;
+	    params.is_3p3v = 1;
+	    params.pin_offset = 56;
+	    rgmii_attach(dev, &params);
+	}
+}
+
+static void bcm_ethsw_ext_open (struct udevice *dev)
+{
+	struct bcmbca_extsw_priv *priv = dev_get_priv(dev);
+
+	sw_open();
+	// When using the SGMII for communicating with external switch
+	if (ext_sw_sgmii && priv->serdes_cntrl) 
+	{
+    	uint32_t val32 = priv->serdes_cntrl[0];
+		printf("serdes_cntrl %p reads 0x%x\n", priv->serdes_cntrl, val32);
+		phy_sgmii_init(priv->serdes_cntrl);
+	}
+}
+
+static void bcm_ethsw_ext_close (struct udevice *dev)
+{
+	printk("Restore Switch's MAC port Rx/Tx, PBVLAN back.\n");
+	sw_close();
+}
+
+#include <asm-generic/gpio.h>
+
+static int extsw_probe(struct udevice *dev)
+{
+	int ret;
+	struct resource res;
+	struct bcmbca_extsw_priv *priv = dev_get_priv(dev);
+	struct gpio_desc reset_gpiod;
+
+	priv->ops.init  = bcm_ethsw_ext_init;
+	priv->ops.open  = bcm_ethsw_ext_open;
+	priv->ops.close = bcm_ethsw_ext_close;
+
+	ret = dev_read_resource_byname(dev, "systemport-serdes-cntrl", &res);
+	priv->serdes_cntrl = NULL;
+	if (!ret) {
+		priv->serdes_cntrl = devm_ioremap(dev, res.start, resource_size(&res));
+	}
+
+	ret = dev_read_resource_byname(dev, "parent-rgmii-ctrl", &res);
+	priv->rgmii_ctrl = NULL;
+	if (!ret) {
+		priv->rgmii_ctrl = devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	ret = dev_read_resource_byname(dev, "parent-gpio-pad-ctrl", &res);
+	priv->gpio_pad_ctrl = NULL;
+	if (!ret) {
+		priv->gpio_pad_ctrl = devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	ret = dev_read_resource_byname(dev, "parent-rgmii-select", &res);
+	priv->rgmii_select = NULL;
+	if (!ret) {
+		priv->rgmii_select = devm_ioremap(dev, res.start, resource_size(&res));
+	}
+
+
+    if (gpio_request_by_name(dev, "switch-reset", 0, &reset_gpiod, GPIOD_IS_OUT) != -ENOENT) {
+        printk("Using GPIO %d to lift external switch out of Reset\n", reset_gpiod.offset);
+        dm_gpio_set_dir(&reset_gpiod);
+        dm_gpio_set_value(&reset_gpiod, 1);   /* reset active */
+        mdelay(100);
+        dm_gpio_set_value(&reset_gpiod, 0);   /* reset clear */
+        mdelay(100);
+    }
+	sw_reset(0);
+
+	sw_hw_ready();
+	// FIXME: skipping RGMII setup
+	priv->ext_sw_sgmii = 0;
+	priv->ext_sw_sgmii = dev_read_u32_default(dev, "extswsgmii_addr", 0);
+	ext_sw_sgmii = priv->ext_sw_sgmii;
+
+
+
+	return 0;
+}
+
+
+static const struct udevice_id bcmbca_extsw_match_ids[] = {
+	{ .compatible = "brcm,bcmbca-extsw"},
+	{ }
+};
+
+#if defined(CONFIG_BCM6756)
+U_BOOT_DRIVER(ethsw_ext) = {
+#else
+U_BOOT_DRIVER(ethsw) = {
+#endif
+	.name = "brcm,ethsw_ext",
+	.id = UCLASS_NOP,
+	.of_match = bcmbca_extsw_match_ids,
+	.flags  = DM_REMOVE_ACTIVE_ALL,
+	.probe = extsw_probe,
+	.priv_auto_alloc_size = sizeof(struct bcmbca_extsw_priv),
+};
+
diff --git a/drivers/net/bcmbca/bcm_ethsw_impl1.c b/drivers/net/bcmbca/bcm_ethsw_impl1.c
new file mode 100755
index 0000000000..9254d43ed1
--- /dev/null
+++ b/drivers/net/bcmbca/bcm_ethsw_impl1.c
@@ -0,0 +1,284 @@
+/* SPDX-License-Identifier: GPL-2.0+
+*  *
+*   *  Copyright 2019 Broadcom Ltd.
+*    */
+
+
+#include <config.h>
+#include <common.h>
+#include <stdlib.h>
+#include <dm.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+
+#include "asm/arch/ethsw.h"
+#include "mii_shared.h"
+#include "pmc_drv.h"
+#include "pmc_switch.h"
+#include "bcm_ethsw.h"
+
+#define BP_MAX_SWITCH_PORTS                     8
+#define BP_MAX_ENET_MACS                        2
+
+struct bcmbca_sf2_priv {
+    bcm_ethsw_ops_t ops;
+	volatile sw_mdio *switch_mdio;
+	volatile EthernetSwitchCore *switch_core;
+
+	void *sphy_ctrl;
+	void *qphy_ctrl;
+	void *phy_test_ctrl;
+	u32 phy_wkard_timeout;
+	int phy_base;
+	int num_phys;
+	uint32_t phy_ids[BP_MAX_SWITCH_PORTS];
+};
+
+static void bcm_ethsw_init(struct udevice *dev)
+{
+	unsigned int phy_ctrl;
+	int i = 0;
+	struct bcmbca_sf2_priv *priv = dev_get_priv(dev);
+
+	volatile EthernetSwitchCore *ETHSW_CORE=priv->switch_core;
+
+	printf("Initalizing switch low level hardware\n");
+
+
+	/* Reset switch */
+	if (ETHSW_CORE)
+	{
+		/* hard code to enable both zones clk temporarily. 
+		   need to parse the dts and enable accordinlgy.
+		*/
+		pmc_switch_enable_rgmii_zone_clk(1, 1);
+		/* power up the switch block */
+		pmc_switch_power_up();
+
+		printk("Software Resetting Switch ... ");
+		ETHSW_CORE->software_reset |= SOFTWARE_RESET | EN_SW_RST;
+		for (; ETHSW_CORE->software_reset & SOFTWARE_RESET;)
+			udelay(100);
+		printk("Done.\n");
+		udelay(1000);
+	}
+
+	gphy_powerup(priv->phy_base, priv->phy_wkard_timeout, priv->sphy_ctrl, priv->qphy_ctrl, priv->phy_test_ctrl);
+
+
+#if !defined(CONFIG_BCM6756)
+	// BCM6756 switch has reverse logic port will be reset disabled
+	if (ETHSW_CORE)
+	{
+		printk("Waiting MAC port Rx/Tx to be enabled by hardware ...");
+		for (i = 0; i < BP_MAX_SWITCH_PORTS; i++) {
+			/* Wait until hardware enable the ports, or we will kill the hardware */
+			for (; ETHSW_CORE->port_traffic_ctrl[i] & PORT_CTRL_RX_DISABLE;
+		    	 udelay(100)) ;
+		}
+	}
+#endif
+
+	if (priv->num_phys) {
+		for (i=0; i < priv->num_phys; i++) {
+			phy_advertise_caps(priv->phy_ids[i]);
+		}
+	}
+
+	printk("Done\n");
+
+	if (ETHSW_CORE)
+	{
+		/* disabled all MAC TX/RX. */
+		printk("Disable Switch All MAC port Rx/Tx\n");
+		for (i = 0; i < BP_MAX_SWITCH_PORTS; i++) {
+			ETHSW_CORE->port_traffic_ctrl[i] =
+		    	(ETHSW_CORE->
+		     	port_traffic_ctrl[i] & 0xff) | PORT_CTRL_RXTX_DISABLE;
+		}
+
+		/* Set switch to unmanaged mode and enable forwarding */
+		ETHSW_CORE->switch_mode =
+	    	((ETHSW_CORE->
+	      	switch_mode & 0xff) | ETHSW_SM_FORWARDING_EN |
+	     	ETHSW_SM_RETRY_LIMIT_DIS) & (~ETHSW_SM_MANAGED_MODE);
+		ETHSW_CORE->brcm_hdr_ctrl = 0;
+		ETHSW_CORE->switch_ctrl = (ETHSW_CORE->switch_ctrl & 0xffb0) |
+	    	ETHSW_SC_MII_DUMP_FORWARDING_EN | ETHSW_SC_MII2_VOL_SEL;
+
+		ETHSW_CORE->imp_port_state =
+	    	ETHSW_IPS_USE_REG_CONTENTS | ETHSW_IPS_TXFLOW_PAUSE_CAPABLE |
+		    ETHSW_IPS_RXFLOW_PAUSE_CAPABLE | ETHSW_IPS_SW_PORT_SPEED_1000M_2000M
+		    | ETHSW_IPS_DUPLEX_MODE | ETHSW_IPS_LINK_PASS;
+	}
+	return;
+}
+
+static void extsw_register_save_restore(volatile EthernetSwitchCore *ETHSW_CORE, int save)
+{
+	static int saved = 0;
+	static uint32_t portCtrl[BP_MAX_SWITCH_PORTS],
+	    pbvlan[BP_MAX_SWITCH_PORTS], reg;
+	int i;
+	int offset_jump = ARRAY_SIZE(ETHSW_CORE->port_vlan_ctrl) / 9;
+
+	if (save) {
+		saved = 1;
+		for (i = 0; i < BP_MAX_SWITCH_PORTS; i++) {
+			portCtrl[i] = ETHSW_CORE->port_traffic_ctrl[i] & 0xff;
+			pbvlan[i] =
+			    ETHSW_CORE->port_vlan_ctrl[offset_jump *
+						       i] & 0xffff;
+		}
+	} else {
+		if (saved) {
+			for (i = 0; i < BP_MAX_SWITCH_PORTS; i++) {
+				reg =
+				    ETHSW_CORE->
+				    port_traffic_ctrl[i] &
+				    PORT_CTRL_SWITCH_RESERVE;
+				reg |= portCtrl[i] & ~PORT_CTRL_SWITCH_RESERVE;
+				ETHSW_CORE->port_traffic_ctrl[i] = reg;
+				ETHSW_CORE->port_vlan_ctrl[offset_jump * i] =
+				    pbvlan[i];
+			}
+		}
+	}
+}
+
+/* SF2 switch init for CFE networking */
+/* Only Called by CFE Command Line */
+static void bcm_ethsw_open(struct udevice *dev)
+{
+	struct bcmbca_sf2_priv *priv = dev_get_priv(dev);
+
+	volatile EthernetSwitchCore *ETHSW_CORE=priv->switch_core;
+
+//#if defined(ETHSW_CORE)
+	if (ETHSW_CORE) {
+    	int i;
+    	int offset_jump=ARRAY_SIZE(ETHSW_CORE->port_vlan_ctrl)/9;
+
+    	/* Save MAC port and PBVLAN registers to save boot strap status */
+    	extsw_register_save_restore(ETHSW_CORE, 1);
+
+    	/* Enable MAC port Tx/Rx for CFE local traffic */
+    	printk ("Enable Switch MAC Port Rx/Tx, set PBVLAN to FAN out, set switch to NO-STP. offset_jump = %d\n", offset_jump);
+    	for( i = 0; i < BP_MAX_SWITCH_PORTS; i++ )
+    	{
+        	/* Set Port VLAN to allow CPU traffic only */
+        	ETHSW_CORE->port_vlan_ctrl[offset_jump*i] = PBMAP_MIPS;
+
+        	/* Setting switch to NO-STP mode; enable port TX/RX. */
+        	ETHSW_CORE->port_traffic_ctrl[i] = ((ETHSW_CORE->port_traffic_ctrl[i] & 0xff) & 
+            	(~(PORT_CTRL_RXTX_DISABLE|PORT_CTRL_PORT_STATUS_M))) | PORT_CTRL_NO_STP;
+    	}
+	}
+
+    return;
+}
+
+/* SF2 switch post process to restore switch status too boot strap status */
+static void bcm_ethsw_close(struct udevice *dev)
+{
+	struct bcmbca_sf2_priv *priv = dev_get_priv(dev);
+
+	volatile EthernetSwitchCore *ETHSW_CORE=priv->switch_core;
+	printk("Restore Switch's MAC port Rx/Tx, PBVLAN back.\n");
+
+	if (ETHSW_CORE)
+	{
+		extsw_register_save_restore(ETHSW_CORE, 0);
+	}
+}
+
+static int sf2_eth_probe(struct udevice *dev)
+{
+	struct resource res;
+	ofnode subnode, port_node, phy_node;
+	int ret, len;
+	const fdt32_t *list;
+	uint32_t phandle, phy_id;
+	struct bcmbca_sf2_priv *priv = dev_get_priv(dev);
+	const char *phy_mode;
+
+    priv->ops.init  = bcm_ethsw_init;
+    priv->ops.open  = bcm_ethsw_open;
+    priv->ops.close = bcm_ethsw_close;
+
+	priv->switch_mdio = NULL;
+	ret = dev_read_resource_byname(dev, "switchmdio-base", &res);
+	if (!ret) {
+		priv->switch_mdio = devm_ioremap(dev, res.start, resource_size(&res));
+		phy_set_mdio_base(priv->switch_mdio);
+	}
+	priv->switch_core = NULL;
+	ret = dev_read_resource_byname(dev, "switchcore-base", &res);
+	if (!ret) {
+		priv->switch_core = devm_ioremap(dev, res.start, resource_size(&res));
+	}
+
+	priv->sphy_ctrl = NULL;
+	ret = dev_read_resource_byname(dev, "sphy-ctrl", &res);
+	if (!ret) {
+		priv->sphy_ctrl = devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	priv->qphy_ctrl = NULL;
+	ret = dev_read_resource_byname(dev, "qphy-ctrl", &res);
+	if (!ret) {
+		priv->qphy_ctrl = devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	priv->phy_test_ctrl = NULL;
+	ret = dev_read_resource_byname(dev, "phy-test-ctrl", &res);
+	if (!ret) {
+		priv->phy_test_ctrl = devm_ioremap(dev, res.start, resource_size(&res));
+	}
+
+	priv->phy_base = dev_read_u32_default(dev, "phy_base", 1);
+	priv->phy_wkard_timeout = 0;
+	dev_read_u32(dev, "phy_wkard_timeout", &priv->phy_wkard_timeout);
+
+	printf("sf2 phy_base %d phy power on workaround timeout %d\n", priv->phy_base, priv->phy_wkard_timeout);
+
+	priv->num_phys = 0;	
+	dev_for_each_subnode(subnode, dev) {
+
+		ofnode_for_each_subnode(port_node, subnode) {
+
+			list = ofnode_get_property (port_node, "phy-handle", &len);
+			if (list) {
+
+				phandle = fdt32_to_cpu (*list);
+				phy_node = ofnode_get_by_phandle(phandle);
+				if (ofnode_valid(phy_node)) {
+					if (!ofnode_read_u32(phy_node, "reg", &phy_id)) {
+						debug("phy_id = 0x%x phandle %d\n", phy_id, phandle);
+					}
+					phy_mode = ofnode_read_string(port_node, "phy-mode");
+					// only worry about the GMII ports for now, add later
+					if (!strcasecmp(phy_mode, "gmii")) {
+						priv->phy_ids[priv->num_phys++] = (phy_id | ADVERTISE_ALL_GMII | PHY_ADV_CFG_VALID);
+					}
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+static const struct udevice_id bcmbca_sf2_match_ids[] = {
+	{ .compatible = "brcm,bcmbca-sf2"},
+	{ }
+};
+
+U_BOOT_DRIVER(ethsw) = {
+	.name = "brcm,ethsw",
+	.id = UCLASS_NOP,
+	.of_match = bcmbca_sf2_match_ids,
+	.flags  = DM_REMOVE_ACTIVE_ALL,
+	.probe = sf2_eth_probe,
+	.priv_auto_alloc_size = sizeof(struct bcmbca_sf2_priv),
+};
+
diff --git a/drivers/net/bcmbca/bcm_ethsw_phy.c b/drivers/net/bcmbca/bcm_ethsw_phy.c
new file mode 100644
index 0000000000..f1a098598d
--- /dev/null
+++ b/drivers/net/bcmbca/bcm_ethsw_phy.c
@@ -0,0 +1,320 @@
+#include <linux/ioport.h>
+
+#include "mii_shared.h"
+#include "asm/arch/ethsw.h"
+#include "bcm_ethsw.h"
+
+static volatile struct sw_mdio *ETHSW_MDIO = NULL;
+
+void phy_set_mdio_base(volatile sw_mdio *mdio_base)
+{
+	printf("switch set mdio_base %p\n", mdio_base);
+	ETHSW_MDIO = (sw_mdio *)mdio_base;
+}
+
+uint16_t bcm_ethsw_phy_read_reg(int phy_id, int reg)
+{
+	int reg_in, reg_out = 0;
+	int i = 0;
+
+	phy_id &= BCM_PHY_ID_M;
+
+	reg_in = ((phy_id << ETHSW_MDIO_C22_PHY_ADDR_SHIFT)&ETHSW_MDIO_C22_PHY_ADDR_MASK) |
+	((reg << ETHSW_MDIO_C22_PHY_REG_SHIFT)&ETHSW_MDIO_C22_PHY_REG_MASK) |
+	(ETHSW_MDIO_CMD_C22_READ << ETHSW_MDIO_CMD_SHIFT);
+	ETHSW_MDIO->mdio_cmd = reg_in | ETHSW_MDIO_BUSY;
+	do {
+		if (++i >= 10)  {
+
+			return 0;
+		}
+		udelay(1);
+		reg_out = ETHSW_MDIO->mdio_cmd;
+	} while (reg_out & ETHSW_MDIO_BUSY);
+
+	/* Read a second time to ensure it is reliable */
+	ETHSW_MDIO->mdio_cmd = reg_in | ETHSW_MDIO_BUSY;
+	i = 0;
+	do {
+		if (++i >= 10)  {
+		return 0;
+		}
+		udelay(1);
+		reg_out = ETHSW_MDIO->mdio_cmd;
+	} while (reg_out & ETHSW_MDIO_BUSY);
+
+	return (uint16_t)reg_out;
+}
+
+void bcm_ethsw_phy_write_reg(int phy_id, int reg, uint16_t data)
+{
+	int reg_value = 0;
+	int i = 0;
+
+	phy_id &= BCM_PHY_ID_M;
+
+	reg_value = ((phy_id << ETHSW_MDIO_C22_PHY_ADDR_SHIFT)&ETHSW_MDIO_C22_PHY_ADDR_MASK) |
+		((reg << ETHSW_MDIO_C22_PHY_REG_SHIFT)& ETHSW_MDIO_C22_PHY_REG_MASK) |
+		(ETHSW_MDIO_CMD_C22_WRITE << ETHSW_MDIO_CMD_SHIFT) | (data&ETHSW_MDIO_PHY_DATA_MASK);
+		ETHSW_MDIO->mdio_cmd = reg_value | ETHSW_MDIO_BUSY;
+
+	do {
+		if (++i >= 10)  {
+		return;
+		}
+		udelay(1);
+		reg_value = ETHSW_MDIO->mdio_cmd;
+	} while (reg_value & ETHSW_MDIO_BUSY);
+
+	return;
+}
+
+uint16_t bcm_ethsw_phy_read_misc_reg(int phy_id, int reg, int chn)
+{
+	uint16_t temp;
+	bcm_ethsw_phy_write_reg(phy_id, 0x18, 0x7);
+	temp = bcm_ethsw_phy_read_reg(phy_id, 0x18);
+	temp |= 0x800;
+	bcm_ethsw_phy_write_reg(phy_id, 0x18, temp);
+
+	temp = (chn << 13)|reg;
+	bcm_ethsw_phy_write_reg(phy_id, 0x17, temp);
+	return  bcm_ethsw_phy_read_reg(phy_id, 0x15);
+}
+
+void bcm_ethsw_phy_write_misc_reg(int phy_id, int reg, int chn, uint16_t data)
+{
+	uint16_t temp;
+	bcm_ethsw_phy_write_reg(phy_id, 0x18, 0x7);
+	temp = bcm_ethsw_phy_read_reg(phy_id, 0x18);
+	temp |= 0x800;
+	bcm_ethsw_phy_write_reg(phy_id, 0x18, temp);
+
+	temp = (chn << 13)|reg;
+	bcm_ethsw_phy_write_reg(phy_id, 0x17, temp);
+	bcm_ethsw_phy_write_reg(phy_id, 0x15, data);
+
+	return;
+}
+
+uint16_t bcm_ethsw_phy_read_exp_reg(int phy_id, int reg)
+{
+	bcm_ethsw_phy_write_reg(phy_id, 0x17, reg|0xf00);
+	return bcm_ethsw_phy_read_reg(phy_id, 0x15);
+}
+void bcm_ethsw_phy_write_exp_reg(int phy_id, int reg, uint16_t data)
+{
+	bcm_ethsw_phy_write_reg(phy_id, 0x17, reg|0xf00);
+	bcm_ethsw_phy_write_reg(phy_id, 0x15, data);
+	return;
+}
+
+/* FIXME - same code exists in robosw_reg.c */
+void phy_advertise_caps(unsigned int phy_id)
+{
+	uint16_t cap_mask = 0;
+
+	/* control advertising if boardparms says so */
+	if (IsPhyConnected(phy_id) && IsPhyAdvCapConfigValid(phy_id)) {
+		cap_mask = bcm_ethsw_phy_read_reg(phy_id, MII_ANAR);
+		cap_mask &= ~(ANAR_TXFD | ANAR_TXHD | ANAR_10FD | ANAR_10HD);
+		if (phy_id & ADVERTISE_10HD)
+			cap_mask |= ANAR_10HD;
+		if (phy_id & ADVERTISE_10FD)
+			cap_mask |= ANAR_10FD;
+		if (phy_id & ADVERTISE_100HD)
+			cap_mask |= ANAR_TXHD;
+		if (phy_id & ADVERTISE_100FD)
+			cap_mask |= ANAR_TXFD;
+		bcm_ethsw_phy_write_reg(phy_id, MII_ANAR, cap_mask);
+
+		cap_mask = bcm_ethsw_phy_read_reg(phy_id, MII_K1CTL);
+		cap_mask &= (~(K1CTL_1000BT_FDX | K1CTL_1000BT_HDX));
+		if (phy_id & ADVERTISE_1000HD)
+			cap_mask |= K1CTL_1000BT_HDX;
+		if (phy_id & ADVERTISE_1000FD)
+			cap_mask |= K1CTL_1000BT_FDX;
+		bcm_ethsw_phy_write_reg(phy_id, MII_K1CTL, cap_mask);
+	}
+
+	/* Always enable repeater mode */
+	cap_mask = bcm_ethsw_phy_read_reg(phy_id, MII_K1CTL);
+	cap_mask |= K1CTL_REPEATER_DTE;
+	bcm_ethsw_phy_write_reg(phy_id, MII_K1CTL, cap_mask);
+}
+
+static void sgphy_powerup(int phy_id, void *sphy_ctrl, void *phy_test_ctrl)
+{
+	uint32_t temp_data;
+	volatile unsigned int *addr;
+
+
+	addr = sphy_ctrl;
+
+	temp_data = *addr;
+
+	temp_data &= ~(ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK|ETHSW_SPHY_CTRL_EXT_PWR_DOWN_MASK|ETHSW_SPHY_CTRL_PHYAD_MASK);
+	temp_data |= ETHSW_SPHY_CTRL_RESET_MASK|(phy_id<<ETHSW_SPHY_CTRL_PHYAD_SHIFT);
+	*addr=temp_data;
+
+	udelay(1);
+#if defined(ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK)
+	temp_data &= ~(ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK);
+#endif
+	*addr=temp_data;
+
+	udelay(1000);
+
+	temp_data = *addr;
+	temp_data &= ~ETHSW_SPHY_CTRL_RESET_MASK;
+	*addr = temp_data;
+
+	udelay(1000);
+}
+
+static void qgphy_powerup(int phy_id, void *qphy_ctrl, void *phy_test_ctrl)
+{
+
+	uint32_t temp_data;
+	volatile unsigned int *addr;
+	addr = qphy_ctrl;
+
+	temp_data = *addr;
+
+	temp_data &= ~(ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK|ETHSW_QPHY_CTRL_EXT_PWR_DOWN_MASK|ETHSW_QPHY_CTRL_PHYAD_BASE_MASK);
+	temp_data |= ETHSW_QPHY_CTRL_RESET_MASK|(phy_id<<ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT);
+
+#if defined(ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK)
+	temp_data &= ~(ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK);
+#endif
+	*addr=temp_data;
+
+	udelay(1000);
+	temp_data = *addr;
+	temp_data &= ~ETHSW_QPHY_CTRL_RESET_MASK;
+	*addr=temp_data;
+
+	udelay(1000);
+
+}
+
+// Note : work around only needed for 63158 / 63178 / 47622
+static void qphy_init_power_workaround(int timeout, void *qphy_ctrl, void *phy_test_ctrl)
+{
+	unsigned int phy_ctrl;
+
+	*((unsigned int*)qphy_ctrl) |= ETHSW_QPHY_CTRL_RESET_MASK;
+	udelay(timeout);
+
+	*((unsigned int*)phy_test_ctrl)=1;
+
+	phy_ctrl = *((unsigned int*)qphy_ctrl);
+	phy_ctrl &= ~(ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK);
+#if defined(ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK)
+	phy_ctrl &= ~(ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK);
+#endif
+	*((unsigned int*)qphy_ctrl) = phy_ctrl;
+
+	udelay(timeout);
+
+	*((unsigned int*)qphy_ctrl) |= (ETHSW_QPHY_CTRL_IDDQ_BIAS_MASK);
+#if defined(ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK)
+	*((unsigned int*)qphy_ctrl) |= (ETHSW_QPHY_CTRL_IDDQ_GLOBAL_PWR_MASK);
+#endif
+	udelay(timeout);
+
+	phy_ctrl = *((unsigned int*)qphy_ctrl);
+	phy_ctrl &= ~(ETHSW_QPHY_CTRL_RESET_MASK);
+	*((unsigned int*)qphy_ctrl) = phy_ctrl;
+
+	udelay(timeout);
+
+	*((unsigned int*)phy_test_ctrl)=0;
+}
+
+static void sphy_init_power_workaround(int timeout, void *sphy_ctrl, void *phy_test_ctrl)
+{
+
+	unsigned int phy_ctrl;
+
+
+	*((unsigned int*)sphy_ctrl) |= ETHSW_SPHY_CTRL_RESET_MASK;
+	udelay(timeout);
+
+	*((unsigned int*)phy_test_ctrl)=1;
+
+
+	phy_ctrl = *((unsigned int*)sphy_ctrl);
+	phy_ctrl &= ~(ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK);
+#if defined(ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK)
+	phy_ctrl &= ~(ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK);
+#endif
+	*((unsigned int*)sphy_ctrl) = phy_ctrl;
+	udelay(timeout);
+
+	*((unsigned int*)sphy_ctrl) |= (ETHSW_SPHY_CTRL_IDDQ_BIAS_MASK);
+#if defined(ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK)
+	*((unsigned int*)sphy_ctrl) |= (ETHSW_SPHY_CTRL_IDDQ_GLOBAL_PWR_MASK);
+#endif
+	udelay(timeout);
+
+	phy_ctrl = *((unsigned int*)sphy_ctrl);
+	phy_ctrl &= ~(ETHSW_SPHY_CTRL_RESET_MASK);
+	*((unsigned int*)sphy_ctrl) = phy_ctrl;
+	udelay(timeout);
+
+	*((unsigned int*)phy_test_ctrl)=0;
+}
+
+extern void phy_adjust_afe(unsigned int phy_id_base, int is_quad);
+
+static void qphy_fixup(void *qphy_ctrl, void *phy_test_ctrl)
+{
+	int phy_id;
+	/* Internal QUAD PHY and Single PHY require some addition fixup on the PHY AFE */
+	phy_id = (*((unsigned int*)qphy_ctrl)&ETHSW_QPHY_CTRL_PHYAD_BASE_MASK)>>ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT;
+	phy_adjust_afe(phy_id, 1);
+} 
+
+static void sphy_fixup(void *sphy_ctrl, void *phy_test_ctrl)
+{
+	int phy_id;
+	phy_id = (*((unsigned int*)sphy_ctrl)&ETHSW_SPHY_CTRL_PHYAD_MASK)>>ETHSW_SPHY_CTRL_PHYAD_SHIFT;
+	phy_adjust_afe(phy_id, 0);
+}
+
+extern uint16_t bcm_ethsw_phy_read_reg(int phy_id, int reg);
+
+void gphy_powerup(int phy_base, u32 wkard_timeout, void *sphy_ctrl, void *qphy_ctrl, void *phy_test_ctrl)
+{
+	int phy_id = phy_base;
+
+	if(qphy_ctrl != NULL) {
+		if (wkard_timeout != 0) {
+			qphy_init_power_workaround(wkard_timeout, qphy_ctrl, phy_test_ctrl);
+		}
+		qgphy_powerup(phy_id, qphy_ctrl, phy_test_ctrl);
+		phy_id += 4;
+	}
+
+	if(sphy_ctrl != NULL) {
+		if (wkard_timeout != 0) {
+			sphy_init_power_workaround(wkard_timeout, sphy_ctrl, phy_test_ctrl);
+		}
+		sgphy_powerup(phy_id, sphy_ctrl, phy_test_ctrl);
+	}
+
+	/* add dummy read to workaround first MDIO read/write issue after power on */
+	bcm_ethsw_phy_read_reg(phy_base, 0x2);
+
+	if (qphy_ctrl != NULL) {
+		qphy_fixup(qphy_ctrl, phy_test_ctrl);
+	}
+	if (sphy_ctrl != NULL) {
+		sphy_fixup(sphy_ctrl, phy_test_ctrl);
+	}
+}
+
+
+
+
diff --git a/drivers/net/bcmbca/bcm_ethsw_phy_47622.c b/drivers/net/bcmbca/bcm_ethsw_phy_47622.c
new file mode 100644
index 0000000000..d5d7869075
--- /dev/null
+++ b/drivers/net/bcmbca/bcm_ethsw_phy_47622.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+
+*  *
+*   *  Copyright 2019 Broadcom Ltd.
+*    */
+
+#include <common.h>
+
+void phy_adjust_afe(unsigned int phy_id_base, int is_quad)
+{
+	unsigned int phy_id;
+	unsigned int phy_id_end = is_quad ? (phy_id_base + 4) : (phy_id_base + 1);
+
+	for( phy_id = phy_id_base; phy_id < phy_id_end; phy_id++ )
+	{
+		//reset phy
+		bcm_ethsw_phy_write_reg(phy_id, 0x0, 0x9140);
+	}
+	udelay(100);
+
+	for( phy_id = phy_id_base; phy_id < phy_id_end; phy_id++ )
+	{
+		//Turn off AOF
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x39, 0x1, 0x0000 );//AFE_TX_CONFIG_0
+
+		//1g AB symmetry Iq
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x3a, 0x2, 0x0BCC );//AFE_TX_CONFIG_1
+
+		//LPF BW
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x39, 0x0, 0x233F );//AFE_TX_IQ_RX_LP
+
+		//RCAL +6LSB to make impedance from 112 to 100ohm
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x3b, 0x0, 0xAD40 );//AFE_TEMPSEN_OTHERS
+
+		//since rcal make R smaller, make master current -4%
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0a, 0x0, 0x091B );//DSP_TAP10
+
+		//From EEE excel config file for Vitesse fix
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0021, 0x0002, 0x87F6 );// rx_on_tune 8 -> 0xf
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0022, 0x0002, 0x017D );// 100tx EEE bandwidth
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0026, 0x0002, 0x0015 );// enable ffe zero det for Vitesse interop
+
+	}
+
+	//Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
+	bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x10);
+	//Disable Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
+	bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x0);
+
+	return;
+
+}
+
diff --git a/drivers/net/bcmbca/bcm_ethsw_phy_4908.c b/drivers/net/bcmbca/bcm_ethsw_phy_4908.c
new file mode 100644
index 0000000000..54f1ede542
--- /dev/null
+++ b/drivers/net/bcmbca/bcm_ethsw_phy_4908.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+
+*  *
+*   *  Copyright 2019 Broadcom Ltd.
+*    */
+
+#include <common.h>
+
+void phy_adjust_afe(unsigned int phy_id_base, int is_quad)
+{
+    unsigned int phy_id;
+    unsigned int phy_id_end = is_quad ? (phy_id_base + 4) : (phy_id_base + 1);
+
+    for( phy_id = phy_id_base; phy_id < phy_id_end; phy_id++ )
+    {
+        //reset phy
+        bcm_ethsw_phy_write_reg(phy_id, 0x0, 0x9140);
+    }
+    udelay(100);
+
+    //CORE_BASE1E Force trim overwrite and set I_ext trim to 0000
+    bcm_ethsw_phy_write_reg(phy_id_base, 0x1e, 0x0010);
+    for( phy_id = phy_id_base; phy_id < phy_id_end; phy_id++ )
+    {
+        //AFE_RXCONFIG_1 Provide more margin for INL/DNL measurement on ATE  
+        bcm_ethsw_phy_write_misc_reg(phy_id, 0x38, 0x1, 0x9b2f);
+        //AFE_TX_CONFIG Set 1000BT Cfeed=011 to improve rise/fall time
+        bcm_ethsw_phy_write_misc_reg(phy_id, 0x39, 0x0, 0x0431);
+        //AFE_VDAC_ICTRL_0 Set Iq=1101 instead of 0111 for improving AB symmetry 
+        bcm_ethsw_phy_write_misc_reg(phy_id, 0x39, 0x1, 0xa7da);
+        //AFE_HPF_TRIM_OTHERS Set 100Tx/10BT to -4.5% swing & Set rCal offset for HT=0 code
+        bcm_ethsw_phy_write_misc_reg(phy_id, 0x3a, 0x0, 0x00e3);
+        //DSP_TAP10  Adjust I_int bias current trim by +0% swing, +0 tick
+        bcm_ethsw_phy_write_misc_reg(phy_id, 0xa, 0x0, 0x011b);
+    }
+
+    //Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
+    bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x10);
+    //Disable Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
+    bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x0);
+
+    return;
+}
+
+
diff --git a/drivers/net/bcmbca/bcm_ethsw_phy_63138.c b/drivers/net/bcmbca/bcm_ethsw_phy_63138.c
new file mode 100644
index 0000000000..e395ffbd78
--- /dev/null
+++ b/drivers/net/bcmbca/bcm_ethsw_phy_63138.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+
+*  *
+*   *  Copyright 2019 Broadcom Ltd.
+*    */
+
+#include <common.h>
+
+void phy_adjust_afe(unsigned int phy_id_base, int is_quad)
+{
+	unsigned int phy_id;
+	unsigned int phy_id_end =
+	    is_quad ? (phy_id_base + 4) : (phy_id_base + 1);
+
+	for (phy_id = phy_id_base; phy_id < phy_id_end; phy_id++) {
+		//reset phy
+		bcm_ethsw_phy_write_reg(phy_id, 0x0, 0x9140);
+		udelay(100);
+
+		//AFE_RXCONFIG_1 Provide more margin for INL/DNL measurement on ATE  
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x38, 0x1, 0x9b2f);
+		//AFE_TX_CONFIG Set 100BT Cfeed=011 to improve rise/fall time
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x39, 0x0, 0x0431);
+		//AFE_VDAC_ICTRL_0 Set Iq=1101 instead of 0111 for improving AB symmetry 
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x39, 0x1, 0xa7da);
+		//AFE_HPF_TRIM_OTHERS Set 100Tx/10BT to -4.5% swing & Set rCal offset for HT=0 code
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x3a, 0x0, 0x00e3);
+	}
+
+	//CORE_BASE1E Force trim overwrite and set I_ext trim to 0000
+	bcm_ethsw_phy_write_reg(phy_id_base, 0x1e, 0x10);
+	for (phy_id = phy_id_base; phy_id < phy_id_end; phy_id++) {
+		//Adjust bias current trim by +4% swing, +2 tick 'DSP_TAP10
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0xa, 0x0, 0x011b);
+	}
+
+	//Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
+	bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x10);
+	//Disable Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
+	bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x0);
+
+	return;
+}
+
diff --git a/drivers/net/bcmbca/bcm_ethsw_phy_63148.c b/drivers/net/bcmbca/bcm_ethsw_phy_63148.c
new file mode 100644
index 0000000000..b8c8092d0e
--- /dev/null
+++ b/drivers/net/bcmbca/bcm_ethsw_phy_63148.c
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+
+*  *
+*  *  Copyright 2019 Broadcom Ltd.
+*  */
+
+#include <common.h>
+
+void phy_adjust_afe(unsigned int phy_id_base, int is_quad)
+{
+	unsigned int phy_id;
+	unsigned int phy_id_end = is_quad ? (phy_id_base + 4) : (phy_id_base + 1);
+
+	for( phy_id = phy_id_base; phy_id < phy_id_end; phy_id++ )
+	{
+		//reset phy
+		bcm_ethsw_phy_write_reg(phy_id, 0x0, 0x9140);
+		udelay(100);
+		//Write analog control registers
+		//AFE_RXCONFIG_0
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x38, 0x0, 0xeb15);
+		//AFE_RXCONFIG_1. Replacing the previously suggested 0x9AAF for SS part. See JIRA HW63148-31
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x38, 0x1, 0x9b2f);
+		//AFE_RXCONFIG_2
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x38, 0x2, 0x2003);
+		//AFE_RX_LP_COUNTER
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x38, 0x3, 0x7fc0);
+		//AFE_TX_CONFIG
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x39, 0x0, 0x0060);
+		//AFE_VDAC_ICTRL_0
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x39, 0x1, 0xa7da);
+		//AFE_VDAC_OTHERS_0
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x39, 0x3, 0xa020);
+		//AFE_HPF_TRIM_OTHERS
+		bcm_ethsw_phy_write_misc_reg(phy_id, 0x3a, 0x0, 0x00e3);
+	}
+
+	//CORE_BASE1E Force trim overwrite and set I_ext trim to 0000
+	bcm_ethsw_phy_write_reg(phy_id_base, 0x1e, 0x0010);
+	for( phy_id = phy_id_base; phy_id < phy_id_end; phy_id++ )
+	{
+	   //Adjust bias current trim by +4% swing, +2 tick, increase PLL BW in GPHY link start up training 'DSP_TAP10
+	   bcm_ethsw_phy_write_misc_reg(phy_id, 0xa, 0x0, 0x111b);
+	}
+
+	//Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
+	bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x10);
+	//Disable Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
+	bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x0);
+
+	return;
+}
diff --git a/drivers/net/bcmbca/bcm_ethsw_phy_afe.c b/drivers/net/bcmbca/bcm_ethsw_phy_afe.c
new file mode 100644
index 0000000000..d5d7869075
--- /dev/null
+++ b/drivers/net/bcmbca/bcm_ethsw_phy_afe.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+
+*  *
+*   *  Copyright 2019 Broadcom Ltd.
+*    */
+
+#include <common.h>
+
+void phy_adjust_afe(unsigned int phy_id_base, int is_quad)
+{
+	unsigned int phy_id;
+	unsigned int phy_id_end = is_quad ? (phy_id_base + 4) : (phy_id_base + 1);
+
+	for( phy_id = phy_id_base; phy_id < phy_id_end; phy_id++ )
+	{
+		//reset phy
+		bcm_ethsw_phy_write_reg(phy_id, 0x0, 0x9140);
+	}
+	udelay(100);
+
+	for( phy_id = phy_id_base; phy_id < phy_id_end; phy_id++ )
+	{
+		//Turn off AOF
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x39, 0x1, 0x0000 );//AFE_TX_CONFIG_0
+
+		//1g AB symmetry Iq
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x3a, 0x2, 0x0BCC );//AFE_TX_CONFIG_1
+
+		//LPF BW
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x39, 0x0, 0x233F );//AFE_TX_IQ_RX_LP
+
+		//RCAL +6LSB to make impedance from 112 to 100ohm
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x3b, 0x0, 0xAD40 );//AFE_TEMPSEN_OTHERS
+
+		//since rcal make R smaller, make master current -4%
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0a, 0x0, 0x091B );//DSP_TAP10
+
+		//From EEE excel config file for Vitesse fix
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0021, 0x0002, 0x87F6 );// rx_on_tune 8 -> 0xf
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0022, 0x0002, 0x017D );// 100tx EEE bandwidth
+		bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0026, 0x0002, 0x0015 );// enable ffe zero det for Vitesse interop
+
+	}
+
+	//Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
+	bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x10);
+	//Disable Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
+	bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x0);
+
+	return;
+
+}
+
diff --git a/drivers/net/bcmbca/bcmbca_rdp_eth.c b/drivers/net/bcmbca/bcmbca_rdp_eth.c
new file mode 100644
index 0000000000..92201d8511
--- /dev/null
+++ b/drivers/net/bcmbca/bcmbca_rdp_eth.c
@@ -0,0 +1,355 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+
+#include "rdp_cpu_ring.h"
+#include "unimac_drv.h"
+#include "data_path_init.h"
+#include "bcm_ethsw.h"
+#include "pmc_rdp.h"
+#include "clk_rst.h"
+#include "mmu_map_v7.h"
+
+extern int rdp_post_init(void);
+extern void rdp_enable_ubus_masters(void);
+
+#define DATA_PATH_INIT(PARAMS)  data_path_init(PARAMS)
+#define DATA_PATH_GO()          data_path_go()
+#define DATA_PATH_SHUTDOWN()    (data_path_shutdown() | pmc_rdp_shut_down())
+
+#define TM_DEF_SIZE             0x1400000
+#define MC_DEF_SIZE             0x0400000
+
+
+#define MAX_RX_BUFSIZE        2048
+
+struct bcmenet_softc {
+	uint32_t init;
+	uint8_t hwaddr[14];
+	uint8_t macId;
+	uint8_t phyId;
+	uint8_t rx_buf[MAX_RX_BUFSIZE];
+
+	struct udevice *sf2_devp;
+	bcm_ethsw_ops_t *sf2_ops;
+};
+
+phys_addr_t ddr_tm_base_address_phys;
+phys_addr_t ddr_multicast_base_address_phys;
+unsigned char *ddr_tm_base_address;
+unsigned char *ddr_multicast_base_address;
+
+static int allocate_rdp_memory(void)
+{
+	int rc = 0;
+
+	/* In CFE, cached addresses and physical addresses are the same address. */
+	if (gd->ram_size > 256*SZ_1M) {
+		ddr_tm_base_address_phys = (phys_addr_t)(256*SZ_1M - TM_DEF_SIZE);
+		ddr_multicast_base_address_phys = (phys_addr_t)(256*SZ_1M - TM_DEF_SIZE - MC_DEF_SIZE);
+		mmu_set_region_dcache_behaviour(ddr_tm_base_address_phys, TM_DEF_SIZE, 
+			SECTION_ATTR_NONCACHED_MEM);
+		mmu_set_region_dcache_behaviour(ddr_multicast_base_address_phys, MC_DEF_SIZE, 
+			SECTION_ATTR_NONCACHED_MEM);
+#if 0
+		rc = fdt_add_mem_rsv((void *)gd->fdt_blob, ddr_tm_base_address_phys, TM_DEF_SIZE);
+		rc != fdt_add_mem_rsv((void *)gd->fdt_blob, ddr_multicast_base_address_phys, MC_DEF_SIZE);
+		if (rc) 
+			return rc;
+#endif
+		printf("\nWARNING: Memory region from 0x%08x - 0x%08x reserved used for runner\n", 
+		       256*SZ_1M - MC_DEF_SIZE - TM_DEF_SIZE, 256*SZ_1M-1);
+	} else {
+		ddr_tm_base_address_phys = noncached_alloc(TM_DEF_SIZE, 0x200000);
+		ddr_multicast_base_address_phys = noncached_alloc(MC_DEF_SIZE, 0x200000);
+	}
+
+	ddr_tm_base_address = (void *) ddr_tm_base_address_phys;
+	ddr_multicast_base_address = (void *) ddr_multicast_base_address_phys;
+
+	if (ddr_tm_base_address == NULL || ddr_multicast_base_address == NULL) {
+		printf("%s:%d Error allocating memory for Runner\n",
+		       __FUNCTION__, __LINE__);
+		return -1;
+	}
+
+	memset(ddr_tm_base_address, 0x00, TM_DEF_SIZE);
+	memset(ddr_multicast_base_address, 0x00, MC_DEF_SIZE);
+
+	return rc;
+}
+
+static int internal_open(struct bcmenet_softc *softc)
+{
+	S_DPI_CFG DpiBasicConfig;
+	int errorCode;
+
+	/* TBD.  This section is temporary to ensure that packets goto EMAC 1.
+	 *       CFE configures the SF2 in unmanaged mode. The board parameter
+	 *       entry is for managed mode.  A board parameter entry for unmanaged
+	 *       mode needs to be added.
+	 */
+	softc->macId = 1;
+
+	/* Initialize SF2 */
+	if (softc->sf2_devp)
+		softc->sf2_ops->open(softc->sf2_devp);
+
+	errorCode = pmc_rdp_init();
+	if (errorCode != DPI_RC_OK) {
+		printf("%s:%d pmc_rdp_init error(error code = %d)\n",
+		       __FUNCTION__, __LINE__, errorCode);
+		return -1;
+	}
+
+	rdp_enable_ubus_masters();
+
+	errorCode = get_rdp_freq((unsigned int *)&DpiBasicConfig.runner_freq);
+	if (errorCode != DPI_RC_OK) {
+		printf("%s:%d get_rdp_freq error(error code = %d)\n",
+		       __FUNCTION__, __LINE__, errorCode);
+		return -1;
+	}
+
+	DpiBasicConfig.mtu_size = 1536;
+	DpiBasicConfig.headroom_size = 0;
+	DpiBasicConfig.runner_tm_base_addr = (uint32_t) ddr_tm_base_address;
+	DpiBasicConfig.runner_tm_base_addr_phys =
+	    (uint32_t) ddr_tm_base_address_phys;
+	DpiBasicConfig.runner_tm_size =
+	  TM_DEF_SIZE / (1024 * 1024);
+	DpiBasicConfig.runner_mc_base_addr =
+	    (uint32_t) ddr_multicast_base_address;
+	DpiBasicConfig.runner_mc_base_addr_phys =
+	    (uint32_t) ddr_multicast_base_address_phys;
+	DpiBasicConfig.runner_mc_size =
+	    MC_DEF_SIZE / (1024 * 1024);
+
+	errorCode = DATA_PATH_INIT(&DpiBasicConfig);
+	if (errorCode != DPI_RC_OK) {
+		printf("%s:%d DATA_PATH_INIT error(error code = %d)\n",
+		       __FUNCTION__, __LINE__, errorCode);
+		return -1;
+	}
+
+	errorCode = rdp_post_init();
+	if (errorCode != DPI_RC_OK) {
+		printf("%s:%d rdp_post_init error(error code = %d)\n",
+		       __FUNCTION__, __LINE__, errorCode);
+		return -1;
+	}
+
+	errorCode = DATA_PATH_GO();
+	if (errorCode != DPI_RC_OK) {
+		printf("%s:%d DATA_PATH_GO error(error code = %d)\n",
+		       __FUNCTION__, __LINE__, errorCode);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int bcmbca_rdp_eth_send(struct udevice *dev, void *buffer, int length)
+{
+	struct bcmenet_softc *priv = dev_get_priv(dev);
+	unsigned char txbuf[60];
+	BL_LILAC_RDD_ERROR_DTE errorCode;
+
+	/* add padding to get 64 bytes frame (4bytes is CRC added by MAC).
+	   padding is zeroes up to 60 bytes */
+	if (length < 60) {
+		memcpy(txbuf, buffer, length);
+		memset(txbuf + length, 0, 60 - length);
+	}
+
+	if (length < 60) {
+		/* call runner driver to send the packet - driver will copy the data */
+		errorCode = rdd_cpu_tx_write_eth_packet(txbuf, 60,
+							BL_LILAC_RDD_EMAC_ID_0 +
+							priv->macId, 0,
+							BL_LILAC_RDD_QUEUE_0);
+	} else {
+		errorCode = rdd_cpu_tx_write_eth_packet(buffer, length,
+							BL_LILAC_RDD_EMAC_ID_0 +
+							priv->macId, 0,
+							BL_LILAC_RDD_QUEUE_0);
+	}
+
+	if (errorCode != BL_LILAC_RDD_OK) {
+		printf("%s: MAC=%d tx error = %d, len=%d\n", __FUNCTION__,
+		       priv->macId, errorCode, length);
+	}
+
+	return 0;
+}
+
+static int bcmbca_rdp_eth_recv(struct udevice *dev, int flags, uchar ** packetp)
+{
+
+	BL_LILAC_RDD_ERROR_DTE errorCode;
+	CPU_RX_PARAMS cpuRx;
+	struct bcmenet_softc *priv = dev_get_priv(dev);
+
+	cpuRx.data_ptr = (void *)priv->rx_buf;
+	/* call runner driver to receive the packet - driver will copy the data */
+	//waiting = rdp_cpu_ring_get_queued(BL_LILAC_RDD_CPU_RX_QUEUE_0);
+	//printf("There are %d packets waiting to be read\n",waiting);
+	errorCode =
+	    rdp_cpu_ring_read_packet_copy(BL_LILAC_RDD_CPU_RX_QUEUE_0, &cpuRx);
+	if ((errorCode != BL_LILAC_RDD_OK)
+	    && (errorCode != BL_LILAC_RDD_ERROR_CPU_RX_QUEUE_EMPTY)) {
+		printf("NET: RDD error receive : %d len=%d reason=%d\n",
+		       errorCode, (int)cpuRx.packet_size, cpuRx.reason);
+		return -EIO;
+	}
+
+	if (!cpuRx.packet_size
+	    && errorCode != BL_LILAC_RDD_ERROR_CPU_RX_QUEUE_EMPTY) {
+		printf("%s: Get zero length packet from RDD\n", __FUNCTION__);
+		return -EIO;
+	}
+
+	if (errorCode == BL_LILAC_RDD_ERROR_CPU_RX_QUEUE_EMPTY) {
+		return -EAGAIN;
+	}
+
+	if (errorCode != BL_LILAC_RDD_OK) {
+		return -EIO;
+	}
+
+	*packetp = priv->rx_buf;
+	return cpuRx.packet_size;
+}
+
+static int bcmbca_rdp_eth_start(struct udevice *dev)
+{
+	int rc;
+	bdmf_phys_addr_t ring_head;
+	struct bcmenet_softc *priv = dev_get_priv(dev);
+
+	debug("bcmbca_rdp_eth_start called %s\n", dev->name);
+
+	if (priv->init)
+		return 0;
+
+	rc = internal_open(priv);
+	if (rc) {
+		printk("internal open falled rc %d \n", rc);
+		return rc;
+	}
+
+	rc = rdp_cpu_ring_create_ring(BL_LILAC_RDD_CPU_RX_QUEUE_0,
+				      rdpa_ring_data, 32, &ring_head,
+				      BCM_PKTBUF_SIZE, NULL, 0);
+	if (rc) {
+		printk("Error creating CPU Rx Ring rc %d\n", rc);
+		return rc;
+	}
+
+	rc = rdd_ring_init(BL_LILAC_RDD_CPU_RX_QUEUE_0, 0,
+			   VIRT_TO_PHYS(ring_head), 32,
+			   sizeof(RDD_CPU_RX_DESCRIPTOR_DTS),
+			   BL_LILAC_RDD_CPU_RX_QUEUE_0, 0, 0, 0);
+	if (rc) {
+		printk("Error rdd_ring_init CPU Rx Ring rc %d\n", rc);
+		return rc;
+	}
+
+	priv->init = 1;
+	return 0;
+}
+
+static void bcmbca_rdp_eth_stop(struct udevice *dev)
+{
+	debug("bcmbca_rdp_eth_stop called %s\n", dev->name);
+
+	return;
+}
+
+static int bcmbca_rdp_eth_read_mac(struct udevice *dev)
+{
+	return 0;
+}
+
+static int bcmbca_rdp_eth_probe(struct udevice *dev)
+{
+	struct udevice *sf2_devp;
+	struct bcmenet_softc *priv = dev_get_priv(dev);
+	const char *ethsw_name = NULL;
+
+	debug("bcmbca_rdp_eth_probe called %s\n", dev->name);
+
+	ethsw_name = dev_read_string(dev, "ethsw");
+	priv->sf2_devp = NULL;
+
+	if (!uclass_get_device_by_name (UCLASS_NOP, ethsw_name, &sf2_devp)) {
+		printf("sf2 found, should have been probed %s\n", sf2_devp->name);
+		priv->sf2_devp = sf2_devp;
+		priv->sf2_ops = dev_get_priv(sf2_devp);
+		priv->sf2_ops->init(priv->sf2_devp);
+	}
+
+	priv->init = 0;
+
+	if (allocate_rdp_memory() != 0) {
+		printf("%s:%d allocate rdp memory failed\n",
+		       __FUNCTION__, __LINE__);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int bcmbca_rdp_eth_remove(struct udevice *dev)
+{
+	int rc = 0;
+	struct bcmenet_softc *priv = dev_get_priv(dev);
+
+	debug("bcmbca_rdp_eth_removed called %s\n", dev->name);
+
+	if (priv->sf2_devp)
+		priv->sf2_ops->close(priv->sf2_devp);
+
+	if (!priv->init)
+		return rc;
+
+	rc = rdp_cpu_ring_delete_ring(BL_LILAC_RDD_CPU_RX_QUEUE_0);
+	if (rc) {
+		printk("Error deleting CPU Rx Ring \n");
+		return -1;
+	}
+
+	rc = DATA_PATH_SHUTDOWN();
+
+	return rc;
+}
+
+static const struct eth_ops bcmbca_rdp_eth_ops = {
+	.start = bcmbca_rdp_eth_start,
+	.send = bcmbca_rdp_eth_send,
+	.recv = bcmbca_rdp_eth_recv,
+	.stop = bcmbca_rdp_eth_stop,
+	.read_rom_hwaddr = bcmbca_rdp_eth_read_mac,
+};
+
+static const struct udevice_id bcmbca_rdp_eth_ids[] = {
+	{.compatible = "brcm,bcmbca-rdp"},
+	{}
+};
+
+U_BOOT_DRIVER(eth_bcmbca_rdp) = {
+	.name	= "eth_bcmbca_rdp",
+	.id	= UCLASS_ETH,
+	.flags	= DM_REMOVE_ACTIVE_ALL,
+	.of_match = bcmbca_rdp_eth_ids,
+	.probe	= bcmbca_rdp_eth_probe,
+	.remove	= bcmbca_rdp_eth_remove,
+	.ops	= &bcmbca_rdp_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct bcmenet_softc),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/bcmbca/bcmbca_sysport_v1.c b/drivers/net/bcmbca/bcmbca_sysport_v1.c
new file mode 100644
index 0000000000..c1fc961277
--- /dev/null
+++ b/drivers/net/bcmbca/bcmbca_sysport_v1.c
@@ -0,0 +1,506 @@
+/* SPDX-License-Identifier: GPL-2.0+
+*  *
+*   *  Copyright 2019 Broadcom Ltd.
+*    */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+#include <config.h>
+#include <console.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <phy.h>
+#include <miiphy.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+#include <asm/system.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <environment.h>
+
+#include "bcmbca_sysport_v1.h"
+#include "bcm_ethsw.h"
+
+#define MAX_PKT_LEN                             (NET_DMA_BUFSIZE)
+
+struct sysport_priv
+{
+	int init;
+	int rx_read_idx;
+	int rx_cons_idx;
+	unsigned char *buffers;
+	sys_port_rbuf *sys_port_rbuf;
+	sys_port_rdma *sys_port_rdma;
+	sys_port_tdma *sys_port_tdma;
+	sys_port_umac *sys_port_umac;
+	sys_port_topctrl *sys_port_topctrl;
+
+	struct udevice *sf2_devp;
+	bcm_ethsw_ops_t *sf2_ops;
+};
+
+
+static void init_pkt_desc(volatile void *ptr, unsigned char *rx_dma_bufaddr)
+{
+	int i;
+	volatile PktDesc *pkt_desc=(PktDesc *)ptr;
+
+	for(i=0;i<(1<<SYSPORT_NUM_RX_PKT_DESC_LOG2);i++)
+	{
+		pkt_desc[i].address=(uintptr_t)rx_dma_bufaddr+(2048*i);
+		pkt_desc[i].address_hi=0;
+		pkt_desc[i].status=0;
+		pkt_desc[i].length=2048;
+	}
+}
+
+/* Enable System Port TX DMA */
+static int sysport_enable_tdma(struct sysport_priv *priv)
+{
+	volatile uint32_t reg;
+	int timeout = 1000;
+
+	// Disable ACB and enable TDMA
+	priv->sys_port_tdma->SYSTEMPORT_TDMA_CONTROL |= 0x01;
+
+	// Wait for TX DMA to become ready
+	do {
+		reg = priv->sys_port_tdma->SYSTEMPORT_TDMA_STATUS;
+		if (!(reg & 0x3)) {
+			return 0;
+		}
+		udelay(10);
+
+	} while (timeout--);
+
+	return -1;
+}
+/* Enable System Port RX DMA */
+static int sysport_enable_rdma(struct sysport_priv *priv)
+{
+	volatile uint32_t reg;
+	int timeout = 1000;
+
+	// Enable RX DMA and Ring Buffer mode
+	priv->sys_port_rdma->SYSTEMPORT_RDMA_CONTROL |= 0x01;
+
+	// Wait for RX DMA to become ready
+	do {
+		reg = priv->sys_port_rdma->SYSTEMPORT_RDMA_STATUS;
+		if (!(reg & 0x3)) {
+			return 0;
+		}
+		udelay(10);
+
+	} while (timeout--);
+
+	return -1;
+}
+
+
+
+static int sysport_init(struct udevice *dev)
+{
+	uint32_t v32 = 0;
+	struct sysport_priv *priv = dev_get_priv(dev);
+
+	if (!priv->init)
+	{
+		if (priv->sf2_devp)
+			priv->sf2_ops->open (priv->sf2_devp);
+
+		/* System Port RBUF configuration */
+		v32 = priv->sys_port_rbuf->SYSTEMPORT_RBUF_RBUF_CONTROL;     /* Read Chip Defaults */
+		v32 &= ~SYSPORT_RBUF_CTRL_RSB_EN_M;
+		v32 &= ~SYSPORT_RBUF_CTRL_4B_ALIGN_M;                 /* Disable 4-Byte IP Alignment */
+		v32 &= ~SYSPORT_RBUF_CTRL_BTAG_STRIP_M;               /* Do not strip BRCM TAG */
+		v32 |= SYSPORT_RBUF_CTRL_BAD_PKT_DISCARD_M;           /* Discard Bad Packets */
+		/* Read-Modify-Write */
+		priv->sys_port_rbuf->SYSTEMPORT_RBUF_RBUF_CONTROL=v32;
+
+		priv->sys_port_rbuf->SYSTEMPORT_RBUF_RBUF_PACKET_READY_THRESHOLD=0x80; /* Keep chip default */
+
+		/* System Port TBUF configuration -- No change, keep chip defaults */
+
+		/* System Port RDMA Configuration */
+
+		/* RDMA Control Register */
+		v32 = priv->sys_port_rdma->SYSTEMPORT_RDMA_CONTROL;  /* Read Chip Defaults */
+		v32 &= ~SYSPORT_RDMA_CTRL_RDMA_EN_M;          /* Disable RDMA */
+		v32 &= ~SYSPORT_RDMA_CTRL_RING_CFG_M;
+		v32 |= SYSPORT_RDMA_CTRL_DISCARD_EN_M;        /* Enable Pkt discard by RDMA when ring full */
+		v32 &= ~SYSPORT_RDMA_CTRL_DATA_OFFSET_M;       /* Zero data offset - this feature could be used later to reduce host buffer size */
+		v32 &= ~SYSPORT_RDMA_CTRL_DDR_DESC_RD_EN_M;    /* HW reads host desc from local desc memory */
+		v32 &= ~SYSPORT_RDMA_CTRL_DDR_DESC_WR_EN_M;
+		v32 |= SYSPORT_RDMA_CTRL_DDR_DESC_SWAP_M;     /* Both Byte and word swap enabled for Desc - TBD - need to understand */
+		/* Read-Modify-Write */
+		priv->sys_port_rdma->SYSTEMPORT_RDMA_CONTROL=v32;
+
+		/* RDMA Buffer and Ring Size Register */
+		v32 = 0;/* Reset register  */
+		v32 |= ( (SYSPORT_PKT_LEN_LOG2 << SYSPORT_RDMA_BSRS_BUF_SIZE_LOG2_S) & SYSPORT_RDMA_BSRS_BUF_SIZE_LOG2_M ); /* set buf size */
+		v32 |= ( ((1<<SYSPORT_NUM_RX_PKT_DESC_LOG2) << SYSPORT_RDMA_BSRS_RING_SIZE_S) & SYSPORT_RDMA_BSRS_RING_SIZE_M ); /* force chip default of 512 */
+		priv->sys_port_rdma->SYSTEMPORT_RDMA_BSRS=v32;
+		//priv->sys_port_rdma->SYSTEMPORT_RDMA_BSRS=8388619;
+
+
+		/* RDMA Consumer Index Register */
+		/* Initialize RX DMA consumer index - low 16 bit; High 16-bits are read-only */
+		priv->sys_port_rdma->SYSTEMPORT_RDMA_CONSUMER_INDEX=0x0;
+		priv->sys_port_rdma->SYSTEMPORT_RDMA_PRODUCER_INDEX=0x0;
+
+		/* RDMA Desc Start Address Registers */
+		/* In desciptor ring mode - start address is index = 0 */
+		priv->sys_port_rdma->SYSTEMPORT_RDMA_START_ADDRESS_LOW=0;
+		priv->sys_port_rdma->SYSTEMPORT_RDMA_START_ADDRESS_HIGH=0;
+
+
+		init_pkt_desc(priv->sys_port_rdma->SYSTEMPORT_RDMA_DESCRIPTOR_WORD, priv->buffers+(NET_DMA_BUFSIZE*NUM_TX_DMA_BUFFERS));
+
+		/* RDMA DDR Desc Ring Register */
+		priv->sys_port_rdma->SYSTEMPORT_RDMA_DDR_DESC_RING_START_LOW = 0;
+		priv->sys_port_rdma->SYSTEMPORT_RDMA_DDR_DESC_RING_START_HIGH = 0; /* Ideally we should put the Hi 8-bits here */
+
+		/* RDMA DDR Desc Ring Size Register */
+		priv->sys_port_rdma->SYSTEMPORT_RDMA_DDR_DESC_RING_SIZE = SYSPORT_NUM_RX_PKT_DESC_LOG2;
+
+		/* RDMA Multi-Buffer-Done-Interrupt-Threshold : No timeout & interrupt every packet */
+		priv->sys_port_rdma->SYSTEMPORT_RDMA_MULTIPLE_BUFFERS_DONE_INTERRUPT_THRESHOLD_PUSH_TIMER = 1;
+		/* enable DDR DESC write push timer to 1 timer tick (equals 1024 RDMA sys clocks */
+		priv->sys_port_rdma->SYSTEMPORT_RDMA_DDR_DESC_RING_PUSH_TIMER = (0x1 & SYSTEMPORT_RDMA_DDR_DESC_RING_PUSH_TIMER_TIMEOUT_M);
+		/* TDMA Block Configuration */
+
+		/* System port supports upto 16 Desc Rings;
+		Only one TX DDR Desc ring is used; It is mapped to TX-Queue[0] */
+
+		/* Enable TX Q#0 */
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_DESC[0].SYSTEMPORT_TDMA_DESC_RING_XX_HEAD_TAIL_PTR = SYSPORT_TDMA_DESC_RING_XX_HEAD_TAIL_PTR_RING_EN_M;
+
+		/* Initialize Producer & Consumer Index */
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_DESC[0].SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX = 0;
+		/* Q#0 DDR Desc Ring Address */
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_DESC[0].SYSTEMPORT_TDMA_DDR_DESC_RING_XX_START_LOW = 0;
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_DESC[0].SYSTEMPORT_TDMA_DDR_DESC_RING_XX_START_HIGH = 0; /* Ideally this should be high 8-bit of address */
+
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_DESC[0].SYSTEMPORT_TDMA_DESC_RING_XX_MAPPING = 0x40;
+		/* enable DDR DESC read push timer to 1 timer tick (equals 1024 TDMA sys clocks */
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_DESC[0].SYSTEMPORT_TDMA_DDR_DESC_RING_XX_PUSH_TIMER = (0x1 & SYSTEMPORT_TDMA_DDR_DESC_RING_PUSH_TIMER_TIMEOUT_M);
+		/* Q#0 DDR Desc Ring Size Log2 */
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_DESC[0].SYSTEMPORT_TDMA_DDR_DESC_RING_XX_SIZE = SYSPORT_NUM_TX_PKT_DESC_LOG2;
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_DESC[0].SYSTEMPORT_TDMA_DESC_RING_XX_INTR_CONTROL = 0x3;
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_DESC[0].SYSTEMPORT_TDMA_DESC_RING_XX_MAX_HYST_THRESHOLD = 0x00100009;
+		/* enable arbitrator for Q#0 */
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_TIER_2_ARBITER_CTRL = 0x1; /* Round Robin */
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_TIER_1_ARBITER_0_CTRL = 0x1;
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_TIER_1_ARBITER_1_CTRL = 0x1;
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_TIER_1_ARBITER_2_CTRL = 0x1;
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_TIER_1_ARBITER_3_CTRL = 0x1;
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_TIER_1_ARBITER_0_QUEUE_ENABLE = 0x000000ff;
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_TIER_1_ARBITER_1_QUEUE_ENABLE = 0x0000ff00;
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_TIER_1_ARBITER_2_QUEUE_ENABLE = 0x00ff0000;
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_TIER_1_ARBITER_3_QUEUE_ENABLE = 0xff000000;
+		/* TDMA Control Register */
+		v32 = priv->sys_port_tdma->SYSTEMPORT_TDMA_CONTROL; /* Read chip defaults */
+		v32 &= ~SYSPORT_TDMA_CONTROL_TSB_EN_M; /* Disable TSB */
+		v32 &= ~(SYSPORT_TDMA_CONTROL_DDR_DESC_RING_EN_M); /* Disable DDR Desc Ring fetch */
+		v32 |= SYSPORT_TDMA_CONTROL_NO_ACB_M; /* No ACB */
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_CONTROL = v32;
+
+		/* Enable Tier-1 arbiter for Q#0 */
+		priv->sys_port_tdma->SYSTEMPORT_TDMA_TIER_1_ARBITER_0_QUEUE_ENABLE=0x1;
+
+		// Enable RX DMA
+		if (sysport_enable_rdma(priv) < 0) {
+			return -1;
+		}
+
+		// Enable TX DMA
+		if (sysport_enable_tdma(priv) < 0) {
+			return -1;
+		}
+
+		v32 = priv->sys_port_umac->SYSTEMPORT_UMAC_CMD;
+		v32 |= SYSPORT_UMAC_CMD_TX_ENA_M; /* Enable TX */
+		v32 |= SYSPORT_UMAC_CMD_RX_ENA_M; /* Enable RX */
+		priv->sys_port_umac->SYSTEMPORT_UMAC_CMD=v32;
+
+
+		// Give SP some time to initialize
+		udelay(100);
+
+	}
+	priv->init++;
+	return 0;
+}
+
+
+static int sysport_send(struct udevice *dev, void *buffer, int length)
+{
+	int timeout = 1000;
+	struct sysport_priv *priv = dev_get_priv(dev);
+	volatile uint32_t p_index, c_index;
+	uint32_t txdesc_hi, txdesc_lo;
+
+	if (length > MAX_PKT_LEN) {
+		return -1;
+	}
+
+	memcpy((void *)(priv->buffers), buffer, length);
+	flush_cache((unsigned long)(priv->buffers), length);
+
+	// set up txdesc record: eop=1, sop=1, append_crc=1
+	txdesc_hi = (length << 18) | (3 << 16) | (1 << 11);
+	txdesc_lo = (uint32_t)priv->buffers;
+
+	// write tx desc to hw
+	// SYSTEMPORT_TDMA_DESCRIPTOR_00_WRITE_PORT_LO
+	priv->sys_port_tdma->SYSTEMPORT_TDMA_DESCRIPTOR_WRITE_PORT[0].SYSTEMPORT_TDMA_DESCRIPTOR_XX_WRITE_PORT_LO=txdesc_lo;
+
+	barrier();
+
+	// SYSTEMPORT_TDMA_DESCRIPTOR_00_WRITE_PORT_HI
+	priv->sys_port_tdma->SYSTEMPORT_TDMA_DESCRIPTOR_WRITE_PORT[0].SYSTEMPORT_TDMA_DESCRIPTOR_XX_WRITE_PORT_HI=txdesc_hi;
+
+	// wait until the packet is fully DMA'ed and stored into TBUF
+	do {
+		// SYSTEMPORT_TDMA_DESC_RING_00_PRODUCER_CONSUMER_INDEX
+		p_index = priv->sys_port_tdma->SYSTEMPORT_TDMA_DESC[0].SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX;
+		c_index = (p_index >> 16);
+		p_index &= 0xffff;
+		c_index &= 0xffff;
+
+	} while ((p_index != c_index) & timeout--);
+
+	if (timeout == 0) {
+		return -1;
+	}
+
+	return 0;
+
+
+}
+
+static int sysport_poll(struct sysport_priv *priv, uint32_t timeout_ms)
+{
+	int i = 0;
+	uint32_t p_index, c_index;
+
+	// SYSTEMPORT_RDMA_PRODUCER_INDEX...
+	p_index = priv->sys_port_rdma->SYSTEMPORT_RDMA_PRODUCER_INDEX & 0xffff;
+	c_index = priv->sys_port_rdma->SYSTEMPORT_RDMA_CONSUMER_INDEX & 0xffff;
+
+	if (p_index == c_index)
+		return -1;
+
+	return 0;
+}
+
+static int sysport_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	int rc = 0;
+	const uint8_t *bufaddr;
+	struct sysport_priv *priv = dev_get_priv(dev);
+	volatile PktDesc *pkt_desc;
+	int length;
+
+	if(sysport_poll(priv, 10) != 0)
+	{
+		return -1;
+	}
+
+
+	// Get RX DMA buffer address
+	pkt_desc=(PktDesc *)priv->sys_port_rdma->SYSTEMPORT_RDMA_DESCRIPTOR_WORD;
+
+	//flush_cache((void *)((const uint8_t *)NULL + pkt_desc[rx_read_idx].address, NET_DMA_BUFSIZE);
+	bufaddr = (uint8_t *)(const uint8_t *)NULL + pkt_desc[priv->rx_read_idx].address;
+	invalidate_dcache_range((unsigned long)bufaddr, (unsigned long) (bufaddr+NET_DMA_BUFSIZE));
+	barrier();
+	length=pkt_desc[priv->rx_read_idx%NUM_RX_DMA_BUFFERS].length;
+
+	if (length < ENET_ZLEN || length > MAX_PKT_LEN)
+	{
+		rc = -1;
+		goto out;
+	}
+	
+
+	*packetp=(unsigned char *) memalign(sizeof(int), MAX_PKT_LEN);
+	if (*packetp == NULL) {
+		printf("%s: malloc failed\n", __func__);
+		return -ENOMEM;
+	}
+
+	memcpy(*packetp, bufaddr, length);
+	rc=length;
+out:
+	// Advance RX read index
+	priv->rx_read_idx++;
+	priv->rx_read_idx &= (NUM_RX_DMA_BUFFERS - 1);
+
+	// Advance RX consumer index in HW
+	priv->rx_cons_idx++;
+	priv->rx_cons_idx &= 0xffff;
+	priv->sys_port_rdma->SYSTEMPORT_RDMA_CONSUMER_INDEX=priv->rx_cons_idx;
+
+	return rc;
+}
+
+static int sysport_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+	if(packet != NULL)
+		free(packet);
+	return 0;
+}
+
+static void sysport_halt(struct udevice *dev)
+{
+}
+
+static int sysport_read_rom_mac(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	u8 mac_addr[6]={0x02,0x10,0x00,0x00,0x00,0x01};
+        u8 mac_temp[6];
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_temp))
+	{
+		eth_env_set_enetaddr("ethaddr", mac_addr);
+	}
+	return 0;
+}
+
+static const struct eth_ops sysport_ops = {
+	.start			= sysport_init,
+	.send			= sysport_send,
+	.recv			= sysport_recv,
+	.free_pkt		= sysport_free_pkt,
+	.stop			= sysport_halt,
+//	.write_hwaddr		= sysport_setup_mac,
+	.read_rom_hwaddr	= sysport_read_rom_mac,
+};
+
+
+void sysport_reset(struct sysport_priv *priv)
+{
+
+    uint32_t v32=0;
+
+    v32 = priv->sys_port_umac->SYSTEMPORT_UMAC_CMD;
+    v32 &= ~SYSPORT_UMAC_CMD_TX_ENA_M; /* Disable TX */
+    v32 &= ~SYSPORT_UMAC_CMD_RX_ENA_M; /* Disable RX */
+    priv->sys_port_umac->SYSTEMPORT_UMAC_CMD=v32;
+    udelay(1000);
+    priv->sys_port_rdma->SYSTEMPORT_RDMA_CONTROL &= ~SYSPORT_RDMA_CTRL_RDMA_EN_M;
+    udelay(1000);
+    //RXCHK_CONTROL=0;
+    priv->sys_port_tdma->SYSTEMPORT_TDMA_CONTROL &= ~SYSPORT_TDMA_CONTROL_TDMA_EN_M;
+    udelay(1000);
+    priv->sys_port_topctrl->SYSTEMPORT_TOPCTRL_RX_FLUSH_CNTL=1;
+    priv->sys_port_topctrl->SYSTEMPORT_TOPCTRL_TX_FLUSH_CNTL=1;
+    udelay(1000);
+    priv->sys_port_topctrl->SYSTEMPORT_TOPCTRL_RX_FLUSH_CNTL=0;
+    priv->sys_port_topctrl->SYSTEMPORT_TOPCTRL_TX_FLUSH_CNTL=0;
+    udelay(1000);
+    priv->sys_port_tdma->SYSTEMPORT_TDMA_STATUS = 0x2; // initialize the Link List RAM.
+    udelay(10);
+}
+
+static int sysport_remove(struct udevice *dev)
+{
+	struct sysport_priv *priv = dev_get_priv(dev);
+
+	if (priv->sf2_devp)
+		priv->sf2_ops->close(priv->sf2_devp);
+	
+	sysport_reset(priv);
+	return 0;
+}
+
+static int sysport_probe(struct udevice *dev)
+{
+	struct resource res;
+	int ret=0, size;
+	struct udevice *sf2_devp;
+	struct sysport_priv *priv = dev_get_priv(dev);
+	uint phandle_id;
+	const fdt32_t *list;
+
+	priv->buffers=memalign(ARCH_DMA_MINALIGN, NUM_DMA_BUFFERS*NET_DMA_BUFSIZE);
+	if (priv->buffers == NULL) {
+		printf("%s: malloc failed\n", __func__);
+		return -ENOMEM;
+	}
+	memset(priv->buffers, 0x0, NUM_DMA_BUFFERS*NET_DMA_BUFSIZE);
+	flush_cache((unsigned long)(priv->buffers), NUM_DMA_BUFFERS*NET_DMA_BUFSIZE);
+	ret = dev_read_resource_byname(dev, "systemport-rbuf-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs systemport-rbuf--base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->sys_port_rbuf=devm_ioremap(dev, res.start, resource_size(&res));
+	ret = dev_read_resource_byname(dev, "systemport-rdma-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs systemport-rdma-base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->sys_port_rdma=devm_ioremap(dev, res.start, resource_size(&res));
+	ret = dev_read_resource_byname(dev, "systemport-tdma-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs systemport-tdma-base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->sys_port_tdma=devm_ioremap(dev, res.start, resource_size(&res));
+	ret = dev_read_resource_byname(dev, "systemport-umac-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs systemport-umac-base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->sys_port_umac=devm_ioremap(dev, res.start, resource_size(&res));
+	ret = dev_read_resource_byname(dev, "systemport-topctrl-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs systemport-topctrl-base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->sys_port_topctrl=devm_ioremap(dev, res.start, resource_size(&res));
+
+	// look for the SF2 driver
+	priv->sf2_devp = NULL;
+	list = dev_read_prop (dev, "ethsw", &size);
+	if (size > 0)
+	{
+		phandle_id = fdt32_to_cpu(*list);
+		if (!uclass_get_device_by_phandle_id(UCLASS_NOP, phandle_id, &sf2_devp))
+		{
+			printf("sf2 found, should have been probed name %s driver name %s\n", 
+			sf2_devp->name, sf2_devp->driver->name);
+			priv->sf2_devp = sf2_devp;
+			priv->sf2_ops = dev_get_priv(sf2_devp);
+			priv->sf2_ops->init (priv->sf2_devp);
+		}
+	}
+
+	sysport_reset(priv);
+	return 0;
+}
+
+static const struct udevice_id sysport_bcmbca_match_ids[] = {
+	{ .compatible = "brcm,bcmbca-systemport-v-1.0"},
+	{ }
+};
+
+
+U_BOOT_DRIVER(sysport) = {
+	.name	= "sysport",
+	.id	= UCLASS_ETH,
+	.of_match = sysport_bcmbca_match_ids,
+	.flags  = DM_REMOVE_ACTIVE_ALL,
+	.probe	= sysport_probe,
+	.remove	= sysport_remove,
+	.ops	= &sysport_ops,
+	.priv_auto_alloc_size = sizeof(struct sysport_priv),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/bcmbca/bcmbca_sysport_v1.h b/drivers/net/bcmbca/bcmbca_sysport_v1.h
new file mode 100644
index 0000000000..47544e21bf
--- /dev/null
+++ b/drivers/net/bcmbca/bcmbca_sysport_v1.h
@@ -0,0 +1,355 @@
+#include <common.h>
+
+/*====move this to a .h file===============================================*/
+#define SYSPORT_NUM_RX_PKT_DESC_LOG2  (7)
+
+#define SYSPORT_NUM_TX_PKT_DESC_LOG2  (0)
+
+#define SYSPORT_PKT_LEN_LOG2 (11)
+
+/* Number of RX DMA buffers */
+#define NUM_RX_DMA_BUFFERS		(1<<SYSPORT_NUM_RX_PKT_DESC_LOG2)
+
+/* Number of RX DMA buffers */
+#define NUM_TX_DMA_BUFFERS		(1<<SYSPORT_NUM_TX_PKT_DESC_LOG2)
+
+/* Total number of DMA buffers */
+#define NUM_DMA_BUFFERS			(NUM_RX_DMA_BUFFERS + NUM_TX_DMA_BUFFERS)
+
+/* RX/TX DMA buffer size */
+#define NET_DMA_BUFSIZE			2048
+
+/* DMA buffer size for SP_RDMA_BSRS_REG register (2048 bytes) */
+#define NET_DMA_SHIFT			11
+
+#define ENET_ZLEN                               60
+
+typedef struct PktDesc {
+    uint32_t address ;
+    uint32_t address_hi :8;
+    uint32_t status :10;
+    uint32_t length :14;
+}PktDesc;
+
+/*===================================================*/
+
+typedef struct sys_port_topctrl {
+	uint32_t SYSTEMPORT_TOPCTRL_REV_CNTL;
+	uint32_t SYSTEMPORT_TOPCTRL_RX_FLUSH_CNTL;
+	uint32_t SYSTEMPORT_TOPCTRL_TX_FLUSH_CNTL;
+	uint32_t SYSTEMPORT_TOPCTRL_MISC_CNTL;
+}sys_port_topctrl, SYSTEMPORT_TOPCTRL;
+
+typedef struct sys_port_mib
+{
+    uint32_t Pkts64Octets;            /* SYSTEMPORT_UMAC_GR64   */
+    uint32_t Pkts65to127Octets;       /* SYSTEMPORT_UMAC_GR127   */
+    uint32_t Pkts128to255Octets;      /* SYSTEMPORT_UMAC_GR255   */
+    uint32_t Pkts256to511Octets;      /* SYSTEMPORT_UMAC_GR511   */
+    uint32_t Pkts512to1023Octets;     /* SYSTEMPORT_UMAC_GR1023   */
+    uint32_t Pkts1024to1518Octets;    /* SYSTEMPORT_UMAC_GR1518   */
+    uint32_t Pkts1519to1522;          /* SYSTEMPORT_UMAC_GRMGV   */
+    uint32_t Pkts1523to2047;          /* SYSTEMPORT_UMAC_GR2047   */
+    uint32_t Pkts2048to4095;          /* SYSTEMPORT_UMAC_GR4095   */
+    uint32_t Pkts4096to8191;          /* SYSTEMPORT_UMAC_GR9216   */
+    uint32_t RxPkts;                  /* SYSTEMPORT_UMAC_GRPKT   */
+    uint32_t RxOctetsLo;              /* SYSTEMPORT_UMAC_GRBYT   */
+    uint32_t RxMulticastPkts;         /* SYSTEMPORT_UMAC_GRMCA   */
+    uint32_t RxBroadcastPkts;         /* SYSTEMPORT_UMAC_GRBCA   */
+    uint32_t RxFCSErrs;               /* SYSTEMPORT_UMAC_GRFCS   */
+    uint32_t RxCtrlFrame;             /* SYSTEMPORT_UMAC_GRXCF   */
+    uint32_t RxPausePkts;             /* SYSTEMPORT_UMAC_GRXPF   */
+    uint32_t RxUnknown;               /* SYSTEMPORT_UMAC_GRXUO   */
+    uint32_t RxAlignErrs;             /* SYSTEMPORT_UMAC_GRALN   */
+    uint32_t RxExcessSizeDisc;        /* SYSTEMPORT_UMAC_GRFLR   */
+    uint32_t RxSymbolError;           /* SYSTEMPORT_UMAC_GRCDE   */
+    uint32_t RxCarrierSenseErrs;      /* SYSTEMPORT_UMAC_GRFCR   */
+    uint32_t RxOversizePkts;          /* SYSTEMPORT_UMAC_GROVR   */
+    uint32_t RxJabbers;               /* SYSTEMPORT_UMAC_GRJBR   */
+    uint32_t RxMtuErrs;               /* SYSTEMPORT_UMAC_GRMTUE   */
+    uint32_t RxGoodPkts;              /* SYSTEMPORT_UMAC_GRPOK   */
+    uint32_t RxUnicastPkts;           /* SYSTEMPORT_UMAC_GRUC   */
+    uint32_t RxPPPPkts;               /* SYSTEMPORT_UMAC_GRPPP   */
+    uint32_t RxCRCMatchPkts;          /* SYSTEMPORT_UMAC_GRCRC   */
+    uint32_t dummy1[3];               /* uint8_t dummy6[12]   */
+    uint32_t TxPkts64Octets;          /* SYSTEMPORT_UMAC_TR64   */
+    uint32_t TxPkts65to127Octets;     /* SYSTEMPORT_UMAC_TR127   */
+    uint32_t TxPkts128to255Octets;    /* SYSTEMPORT_UMAC_TR255   */
+    uint32_t TxPkts256to511Octets;    /* SYSTEMPORT_UMAC_TR511   */
+    uint32_t TxPkts512to1023Octets;   /* SYSTEMPORT_UMAC_TR1023   */
+    uint32_t TxPkts1024to1518Octets;  /* SYSTEMPORT_UMAC_TR1518   */
+    uint32_t TxPkts1519to1522;        /* SYSTEMPORT_UMAC_TRMGV   */
+    uint32_t TxPkts1523to2047;        /* SYSTEMPORT_UMAC_TR2047   */
+    uint32_t TxPkts2048to4095;        /* SYSTEMPORT_UMAC_TR4095   */
+    uint32_t TxPkts4096to8191;        /* SYSTEMPORT_UMAC_TR9216   */
+    uint32_t TxPkts;                  /* SYSTEMPORT_UMAC_GTPKT   */
+    uint32_t TxMulticastPkts;         /* SYSTEMPORT_UMAC_GTMCA   */
+    uint32_t TxBroadcastPkts;         /* SYSTEMPORT_UMAC_GTBCA   */
+    uint32_t TxPausePkts;             /* SYSTEMPORT_UMAC_GTXPF   */
+    uint32_t TxCtrlFrame;             /* SYSTEMPORT_UMAC_GTXCF   */
+    uint32_t TxFCSErrs;               /* SYSTEMPORT_UMAC_GTFCS   */
+    uint32_t TxOversizePkts;          /* SYSTEMPORT_UMAC_GTOVR   */
+    uint32_t TxDeferredTx;            /* SYSTEMPORT_UMAC_GTDRF   */
+    uint32_t TxExcessiveDef;          /* SYSTEMPORT_UMAC_GTEDF   */
+    uint32_t TxSingleCol;             /* SYSTEMPORT_UMAC_GTSCL   */
+    uint32_t TxMultipleCol;           /* SYSTEMPORT_UMAC_GTMCL   */
+    uint32_t TxLateCol;               /* SYSTEMPORT_UMAC_GTLCL   */
+    uint32_t TxExcessiveCol;          /* SYSTEMPORT_UMAC_GTXCL   */
+    uint32_t TxFragments;             /* SYSTEMPORT_UMAC_GTFRG   */
+    uint32_t TxCol;                   /* SYSTEMPORT_UMAC_GTNCL   */
+    uint32_t TxJabber;                /* SYSTEMPORT_UMAC_GTJBR   */
+    uint32_t TxOctetsLo;              /* SYSTEMPORT_UMAC_GTBYT   */
+    uint32_t TxGoodPkts;              /* SYSTEMPORT_UMAC_GTPOK   */
+    uint32_t TxUnicastPkts;           /* SYSTEMPORT_UMAC_GTUC   */
+    uint32_t dummy2[3];               /* uint8_t dummy7[12]   */
+    uint32_t RxRuntPkts;              /* SYSTEMPORT_UMAC_RRPKT   */
+    uint32_t RxRuntValidFCSPkts;      /* SYSTEMPORT_UMAC_RRUND   */
+    uint32_t RxRuntInvalidFCSPkts;    /* SYSTEMPORT_UMAC_RRFRG   */
+    uint32_t RxRuntOctets;            /* SYSTEMPORT_UMAC_RRBYT   */
+
+    /* No mapping for below counters */
+    /* uint32_t RxUndersizePkts; */
+    /* uint32_t RxFragments; */
+
+}sys_port_mib;
+
+
+#define FIELD_MASK(bits, shift)  ( ( (1ULL<<(bits)) - 1 ) << shift )
+
+#define SYSPORT_UMAC_CMD_TX_ENA_M     FIELD_MASK(1,0)
+#define SYSPORT_UMAC_CMD_RX_ENA_M     FIELD_MASK(1,1)
+
+#define SYSPORT_UMAC_MPD_CTRL_MPD_EN  FIELD_MASK(1,0)
+
+typedef struct sys_port_umac {
+	uint32_t SYSTEMPORT_UMAC_UMAC_DUMMY;
+	uint32_t SYSTEMPORT_UMAC_HD_BKP_CNTL;
+	uint32_t SYSTEMPORT_UMAC_CMD;
+	uint32_t SYSTEMPORT_UMAC_MAC0;
+	uint32_t SYSTEMPORT_UMAC_MAC1;
+	uint32_t SYSTEMPORT_UMAC_FRM_LEN;
+	uint32_t SYSTEMPORT_UMAC_PAUSE_QUNAT;
+	uint32_t dummy1[9];
+	uint32_t SYSTEMPORT_UMAC_SFD_OFFSET;
+	uint32_t SYSTEMPORT_UMAC_MODE;
+	uint32_t SYSTEMPORT_UMAC_FRM_TAG0;
+	uint32_t SYSTEMPORT_UMAC_FRM_TAG1;
+	uint32_t dummy2[3];
+	uint32_t SYSTEMPORT_UMAC_TX_IPG_LEN;
+	uint32_t dummy3;
+	uint32_t SYSTEMPORT_UMAC_EEE_CTRL;
+	uint32_t SYSTEMPORT_UMAC_EEE_LPI_TIMER;
+	uint32_t SYSTEMPORT_UMAC_EEE_WAKE_TIMER;
+	uint32_t SYSTEMPORT_UMAC_EEE_REF_COUNT;
+	uint32_t dummy4;
+	uint32_t SYSTEMPORT_UMAC_RX_PKT_DROP_STATUS;
+	uint32_t SYSTEMPORT_UMAC_SYMMETRIC_IDLE_THRESHOLD;
+	uint32_t dummy5[164];
+	uint32_t SYSTEMPORT_UMAC_MACSEC_PROG_TX_CRC;
+	uint32_t SYSTEMPORT_UMAC_MACSEC_CNTRL;
+	uint32_t SYSTEMPORT_UMAC_TS_STATUS_CNTRL;
+	uint32_t SYSTEMPORT_UMAC_TX_TS_DATA;
+	uint32_t dummy6[4];
+	uint32_t SYSTEMPORT_UMAC_PAUSE_CNTRL;
+	uint32_t SYSTEMPORT_UMAC_TXFIFO_FLUSH;
+	uint32_t SYSTEMPORT_UMAC_RXFIFO_STAT;
+	uint32_t SYSTEMPORT_UMAC_TXFIFO_STAT;
+	uint32_t SYSTEMPORT_UMAC_PPP_CNTRL;
+	uint32_t SYSTEMPORT_UMAC_PPP_REFRESH_CNTRL;
+	uint32_t SYSTEMPORT_UMAC_TX_PAUSE_PREL0;
+	uint32_t SYSTEMPORT_UMAC_TX_PAUSE_PREL1;
+	uint32_t SYSTEMPORT_UMAC_TX_PAUSE_PREL2;
+	uint32_t SYSTEMPORT_UMAC_TX_PAUSE_PREL3;
+	uint32_t SYSTEMPORT_UMAC_RX_PAUSE_PREL0;
+	uint32_t SYSTEMPORT_UMAC_RX_PAUSE_PREL1;
+	uint32_t SYSTEMPORT_UMAC_RX_PAUSE_PREL2;
+	uint32_t SYSTEMPORT_UMAC_RX_PAUSE_PREL3;
+	uint32_t dummy7[38];
+	sys_port_mib sp_mib;
+	uint32_t dummy8[28];
+	uint32_t SYSTEMPORT_UMAC_MIB_CNTRL;
+	uint32_t dummy9[32];
+	uint32_t SYSTEMPORT_UMAC_RXERR_MASK;
+	uint32_t SYSTEMPORT_UMAC_RX_MAX_PKT_SIZE;
+	uint32_t dummy10[5];
+	uint32_t SYSTEMPORT_UMAC_MPD_CTRL;
+	uint32_t SYSTEMPORT_UMAC_PSW_MS;
+	uint32_t SYSTEMPORT_UMAC_PSW_LS;
+	uint32_t dummy11[8];
+	}sys_port_umac, SYSTEMPORT_UMAC;
+
+#define SYSPORT_RDMA_CTRL_RDMA_EN_M             FIELD_MASK(1,0)
+#define SYSPORT_RDMA_CTRL_RING_CFG_M            FIELD_MASK(1,1)
+#define SYSPORT_RDMA_CTRL_DISCARD_EN_M          FIELD_MASK(1,2)
+#define SYSPORT_RDMA_CTRL_DATA_OFFSET_M         FIELD_MASK(10,4)
+#define SYSPORT_RDMA_CTRL_DDR_DESC_RD_EN_M      FIELD_MASK(1,14)
+#define SYSPORT_RDMA_CTRL_DDR_DESC_WR_EN_M      FIELD_MASK(1,15)
+#define SYSPORT_RDMA_CTRL_DDR_DESC_SWAP_M       FIELD_MASK(2,16)
+
+#define SYSPORT_RDMA_BSRS_BUF_SIZE_LOG2_S       (0)
+#define SYSPORT_RDMA_BSRS_BUF_SIZE_LOG2_M       FIELD_MASK(4,0)
+#define SYSPORT_RDMA_BSRS_RING_SIZE_S           (16)
+#define SYSPORT_RDMA_BSRS_RING_SIZE_M           FIELD_MASK(16,16)
+
+#define SYSPORT_RDMA_STATUS_RDMA_DISABLED_M     FIELD_MASK(1,0)
+#define SYSPORT_RDMA_STATUS_DESC_RAM_BUSY_M     FIELD_MASK(1,1)
+
+#define SYSTEMPORT_RDMA_LOCRAM_DESCRING_SIZE_MAX  512
+
+#define SYSPORT_RDMA_PRODUCER_INDEX_PROD_IDX_M  FIELD_MASK(16,0)
+#define SYSPORT_RDMA_CONSUMER_INDEX_CONS_IDX_M  FIELD_MASK(16,0)
+#define SYSTEMPORT_RDMA_DDR_DESC_RING_PUSH_TIMER_TIMEOUT_M  FIELD_MASK(16,0)
+
+typedef struct sys_port_rdma {
+	uint32_t SYSTEMPORT_RDMA_DESCRIPTOR_WORD[1024];
+	uint32_t SYSTEMPORT_RDMA_CONTROL;
+	uint32_t SYSTEMPORT_RDMA_STATUS;
+	uint32_t SYSTEMPORT_RDMA_SYSBUS_BURST;
+	uint32_t SYSTEMPORT_RDMA_BSRS;
+	uint32_t SYSTEMPORT_RDMA_WRITE_POINTER_LOW;
+	uint32_t SYSTEMPORT_RDMA_WRITE_POINTER_HIGH;
+	uint32_t SYSTEMPORT_RDMA_PRODUCER_INDEX;
+	uint32_t SYSTEMPORT_RDMA_CONSUMER_INDEX;
+	uint32_t SYSTEMPORT_RDMA_START_ADDRESS_LOW;
+	uint32_t SYSTEMPORT_RDMA_START_ADDRESS_HIGH;
+	uint32_t SYSTEMPORT_RDMA_MULTIPLE_BUFFERS_DONE_INTERRUPT_THRESHOLD_PUSH_TIMER;
+	uint32_t SYSTEMPORT_RDMA_XON_XOFF_THRESHOLD;
+	uint32_t SYSTEMPORT_RDMA_READ_POINTER_LOW;
+	uint32_t SYSTEMPORT_RDMA_READ_POINTER_HIGH;
+	uint32_t SYSTEMPORT_RDMA_DESC_RAM_ARB_CONTROL;
+	uint32_t SYSTEMPORT_RDMA_DESC_RAM_RD_ARB_CFG;
+	uint32_t SYSTEMPORT_RDMA_DESC_RAM_WR_ARB_CFG;
+	uint32_t SYSTEMPORT_RDMA_DDR_DESC_RING_START_LOW;
+	uint32_t SYSTEMPORT_RDMA_DDR_DESC_RING_START_HIGH;
+	uint32_t SYSTEMPORT_RDMA_DDR_DESC_RING_SIZE;
+	uint32_t SYSTEMPORT_RDMA_DDR_DESC_RING_CTRL;
+	uint32_t SYSTEMPORT_RDMA_DDR_DESC_RING_PUSH_TIMER;
+	uint32_t SYSTEMPORT_RDMA_TEST;
+	uint32_t SYSTEMPORT_RDMA_DEBUG;
+
+}sys_port_rdma, SYSTEMPORT_RDMA;
+
+#define SYSPORT_RBUF_CTRL_RSB_EN_M            FIELD_MASK(1,0)
+#define SYSPORT_RBUF_CTRL_4B_ALIGN_M          FIELD_MASK(1,1)
+#define SYSPORT_RBUF_CTRL_BTAG_STRIP_M        FIELD_MASK(1,2)
+#define SYSPORT_RBUF_CTRL_BAD_PKT_DISCARD_M   FIELD_MASK(1,3)
+#define SYSPORT_RBUF_CTRL_CRC_REPLACE_M       FIELD_MASK(1,20)
+#define SYSPORT_RBUF_CTRL_RSB_SWAP_M          FIELD_MASK(2,22)
+#define SYSPORT_RBUF_CTRL_RSB_SWAP_S          22
+
+#define SYSPORT_RBUF_CTRL_RSB_SWAP_NONE       0
+#define SYSPORT_RBUF_CTRL_RSB_SWAP_32         1
+#define SYSPORT_RBUF_CTRL_RSB_SWAP_64         2
+#define SYSPORT_RBUF_CTRL_RSB_SWAP_32_64      3
+
+typedef struct sys_port_rbuf {
+	uint32_t SYSTEMPORT_RBUF_RBUF_CONTROL;
+	uint32_t SYSTEMPORT_RBUF_RBUF_PACKET_READY_THRESHOLD;
+	uint32_t SYSTEMPORT_RBUF_RBUF_STATUS;
+	uint32_t SYSTEMPORT_RBUF_RBUF_OVERFLOW_PACKET_DISCARD_COUNT;
+	uint32_t SYSTEMPORT_RBUF_RBUF_ERROR_PACKET_COUNT;
+}sys_port_rbuf, SYSTEMPORT_RBUF;
+
+
+typedef struct sys_port_tbuf {
+	uint32_t SYSTEMPORT_TBUF_TBUF_CONTROL;
+	uint32_t SYSTEMPORT_TBUF_TBUF_STATUS;
+}sys_port_tbuf, SYSTEMPORT_TBUF;
+
+#define SYSTEMPORT_TDMA_DESC_RING_MAX        16
+#define SYSTEMPORT_TDMA_LOCRAM_DESCRING_MAX  1024
+
+#define SYSTEMPORT_TDMA_TIMEOUT_TICK_NSEC    4096 // For 250MHz clock: 1024 * 4ns
+
+typedef struct systemport_tdma_descriptor_write_port
+{
+		uint32_t SYSTEMPORT_TDMA_DESCRIPTOR_XX_WRITE_PORT_LO;
+		uint32_t SYSTEMPORT_TDMA_DESCRIPTOR_XX_WRITE_PORT_HI;
+}systemport_tdma_descriptor_write_port;
+
+typedef struct systemport_tdma_descriptor_read_port
+{
+		uint32_t SYSTEMPORT_TDMA_DESCRIPTOR_XX_READ_PORT_LO;
+		uint32_t SYSTEMPORT_TDMA_DESCRIPTOR_XX_READ_PORT_HI;
+}systemport_tdma_descriptor_read_port;
+
+#define SYSPORT_TDMA_DESC_RING_XX_HEAD_TAIL_PTR_RING_EN_M                          FIELD_MASK(1,25)
+#define SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX_CONSUMER_INDEX_S      16
+#define SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX_CONSUMER_INDEX_M      FIELD_MASK(16,16)
+#define SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX_PRODUCER_INDEX_M      FIELD_MASK(16,0)
+
+#define SYSTEMPORT_TDMA_DESC_RING_XX_INTR_CONTROL_TIMEOUT_S                        16
+#define SYSTEMPORT_TDMA_DESC_RING_XX_INTR_CONTROL_TIMEOUT_M                        FIELD_MASK(16,16)
+#define SYSTEMPORT_TDMA_DESC_RING_XX_INTR_CONTROL_RING_EMPTY_INTR_EN_M             FIELD_MASK(1,15)
+#define SYSTEMPORT_TDMA_DESC_RING_XX_INTR_CONTROL_INTR_THRESHOLD_S                 0
+#define SYSTEMPORT_TDMA_DESC_RING_XX_INTR_CONTROL_INTR_THRESHOLD_M                 FIELD_MASK(15,0)
+
+typedef struct SYSTEMPORT_TDMA_DESC
+{
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_XX_HEAD_TAIL_PTR;
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_XX_COUNT;
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_XX_MAX_HYST_THRESHOLD;
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_XX_INTR_CONTROL;
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX;
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_XX_MAPPING;
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_XX_PCP_DEI_VID;
+	uint32_t SYSTEMPORT_TDMA_DDR_DESC_RING_XX_START_LOW;
+	uint32_t SYSTEMPORT_TDMA_DDR_DESC_RING_XX_START_HIGH;
+	uint32_t SYSTEMPORT_TDMA_DDR_DESC_RING_XX_SIZE;
+	uint32_t SYSTEMPORT_TDMA_DDR_DESC_RING_XX_CTRL;
+	uint32_t SYSTEMPORT_TDMA_DDR_DESC_RING_XX_PUSH_TIMER;
+}systemport_tdma_desc;
+
+#define SYSPORT_TDMA_CONTROL_TDMA_EN_M            FIELD_MASK(1,0)
+#define SYSPORT_TDMA_CONTROL_TSB_EN_M             FIELD_MASK(1,1)
+#define SYSPORT_TDMA_CONTROL_TSB_SWAP_M           FIELD_MASK(2,2)
+#define SYSPORT_TDMA_CONTROL_ACB_ALGO_M           FIELD_MASK(1,4)
+#define SYSPORT_TDMA_CONTROL_DATA_OFFSET_M        FIELD_MASK(10,5)
+#define SYSPORT_TDMA_CONTROL_VLAN_EN_M            FIELD_MASK(1,15)
+#define SYSPORT_TDMA_CONTROL_SW_BRCM_TAG_M        FIELD_MASK(1,16)
+#define SYSPORT_TDMA_CONTROL_DDR_DESC_RING_EN_M   FIELD_MASK(1,19)
+#define SYSPORT_TDMA_CONTROL_DDR_DESC_SWAP_M      FIELD_MASK(2,20)
+#define SYSPORT_TDMA_CONTROL_DDR_DESC_SWAP_S      20
+#define SYSPORT_TDMA_CONTROL_NO_ACB_M             FIELD_MASK(1,27)
+
+#define SYSPORT_TDMA_CONTROL_DDR_DESC_SWAP_NONE   0
+#define SYSPORT_TDMA_CONTROL_DDR_DESC_SWAP_32     1
+#define SYSPORT_TDMA_CONTROL_DDR_DESC_SWAP_64     2
+#define SYSPORT_TDMA_CONTROL_DDR_DESC_SWAP_32_64  3
+
+#define SYSPORT_TDMA_STATUS_TDMA_DISABLED_M       FIELD_MASK(1,0)
+#define SYSPORT_TDMA_STATUS_LL_RAM_INIT_BUSY_M    FIELD_MASK(1,1)
+
+#define SYSTEMPORT_TDMA_DDR_DESC_RING_PUSH_TIMER_TIMEOUT_M  FIELD_MASK(16,0)
+
+typedef struct sys_port_tdma {
+	systemport_tdma_descriptor_write_port SYSTEMPORT_TDMA_DESCRIPTOR_WRITE_PORT[16];
+	uint8_t dummy1[128];
+	systemport_tdma_descriptor_read_port  SYSTEMPORT_TDMA_DESCRIPTOR_READ_PORT[16];
+	uint8_t dummy2[128];
+	uint32_t SYSTEMPORT_TDMA_DESCRIPTOR_XX_READ_PORT_CMD[16];
+	uint8_t dummy3[64];
+	systemport_tdma_desc SYSTEMPORT_TDMA_DESC[16];
+	uint8_t dummy4[128];
+	uint32_t SYSTEMPORT_TDMA_CONTROL;
+	uint32_t SYSTEMPORT_TDMA_STATUS;
+	uint32_t SYSTEMPORT_TDMA_SYSBUS_BURST;
+	uint32_t SYSTEMPORT_TDMA_OVER_MAX_THRESHOLD_STATUS;
+	uint32_t SYSTEMPORT_TDMA_OVER_HYST_THRESHOLD_STATUS;
+	uint32_t SYSTEMPORT_TDMA_TPID;
+	uint32_t SYSTEMPORT_TDMA_FREE_LIST_HEAD_TAIL_PTR;
+	uint32_t SYSTEMPORT_TDMA_FREE_LIST_COUNT;
+	uint32_t SYSTEMPORT_TDMA_TIER_2_ARBITER_CTRL;
+	uint32_t SYSTEMPORT_TDMA_TIER_1_ARBITER_0_CTRL;
+	uint32_t SYSTEMPORT_TDMA_TIER_1_ARBITER_0_QUEUE_ENABLE;
+	uint32_t SYSTEMPORT_TDMA_TIER_1_ARBITER_1_CTRL;
+	uint32_t SYSTEMPORT_TDMA_TIER_1_ARBITER_1_QUEUE_ENABLE;
+	uint32_t SYSTEMPORT_TDMA_TIER_1_ARBITER_2_CTRL;
+	uint32_t SYSTEMPORT_TDMA_TIER_1_ARBITER_2_QUEUE_ENABLE;
+	uint32_t SYSTEMPORT_TDMA_TIER_1_ARBITER_3_CTRL;
+	uint32_t SYSTEMPORT_TDMA_TIER_1_ARBITER_3_QUEUE_ENABLE;
+	uint32_t SYSTEMPORT_TDMA_TEST;
+	uint32_t SYSTEMPORT_TDMA_DEBUG;
+
+}sys_port_tdma, SYSTEMPORT_TDMA;
+
diff --git a/drivers/net/bcmbca/bcmbca_sysport_v2.c b/drivers/net/bcmbca/bcmbca_sysport_v2.c
new file mode 100644
index 0000000000..726e4b5709
--- /dev/null
+++ b/drivers/net/bcmbca/bcmbca_sysport_v2.c
@@ -0,0 +1,796 @@
+/* SPDX-License-Identifier: GPL-2.0+
+*  *
+*   *  Copyright 2019 Broadcom Ltd.
+*    */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+#include <config.h>
+#include <console.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <phy.h>
+#include <miiphy.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+#include <asm/system.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+#include "bcm_ethsw.h"
+#include "bcmbca_sysport_v2.h"
+
+#define MAX_PKT_LEN                             (NET_DMA_BUFSIZE)
+enum sysport_ids
+{
+	SYSPORT_0,
+	SYSPORT_1,
+};
+
+#define MAX_ETHSW   2
+
+struct sysport_priv
+{
+	int init;
+	int active_sysport;
+	unsigned char *buffers[2];
+	sys_port_rbuf *sys_port_rbuf[2];
+	sys_port_rdma *sys_port_rdma[2];
+	sys_port_tdma *sys_port_tdma[2];
+	sys_port_umac *sys_port_umac[2];
+	sys_port_gib    *sys_port_gib;
+	sys_port_topctrl *sys_port_topctrl[2];
+
+	void		*switch_mdio;
+	void		*sphy_ctrl;
+	void		*phy_test_ctrl;
+	u32 		phy_wkard_timeout;
+	int 		phy_base;
+
+	struct udevice *ethsw_devp[MAX_ETHSW];
+	bcm_ethsw_ops_t *ethsw_ops[MAX_ETHSW];
+};
+
+char static_buff[2048];
+
+
+static void init_pkt_desc(volatile void *ptr, unsigned char *rx_dma_bufaddr)
+{
+	int i;
+	volatile PktDesc *pkt_desc=(PktDesc *)ptr;
+
+	for(i=0;i<(1<<SYSPORT_NUM_RX_PKT_DESC_LOG2);i++)
+	{
+		pkt_desc[i].address=(uintptr_t)rx_dma_bufaddr+(2048*i);
+		pkt_desc[i].address_hi=0;
+		pkt_desc[i].status=0;
+		pkt_desc[i].length=2048;
+	}
+}
+
+/* Enable System Port TX DMA */
+static int __sp_enable_tdma(volatile sys_port_tdma *sysport_tdma)
+{
+	volatile uint32_t reg;
+	int timeout = 1000;
+
+	// Disable ACB and enable TDMA
+	sysport_tdma->SYSTEMPORT_TDMA_CONTROL |= 0x01;
+
+	// Wait for TX DMA to become ready
+	do {
+		reg = sysport_tdma->SYSTEMPORT_TDMA_STATUS;
+		if (!(reg & 0x3)) {
+			return 0;
+		}
+		udelay(10);
+
+	} while (timeout--);
+
+	return -1;
+}/* Enable System Port RX DMA */
+
+
+/* Enable System Port TX DMA */
+static int sysport_enable_tdma(struct sysport_priv *priv)
+{
+	int init_0 =0, init_1=0;
+
+	if(priv->sys_port_tdma[0] != NULL)
+		init_0=__sp_enable_tdma(priv->sys_port_tdma[0]);
+	if(priv->sys_port_tdma[1] != NULL)
+		init_1=__sp_enable_tdma(priv->sys_port_tdma[1]);
+	if(init_0 != 0 || init_0 != 0)
+	{
+		init_0=-1;
+		printf("enble tdma failed [0] %d [1] %d\n", init_0, init_1);
+	}
+	return init_0;
+}
+
+static int __sp_enable_rdma(volatile sys_port_rdma *sysport_rdma)
+{
+	volatile uint32_t reg;
+	int timeout = 1000;
+
+	// Enable RX DMA and Ring Buffer mode
+	sysport_rdma->SYSTEMPORT_RDMA_CONTROL |= 0x01;
+
+	// Wait for RX DMA to become ready
+	do {
+		reg = sysport_rdma->SYSTEMPORT_RDMA_STATUS;
+		if (!(reg & 0x3)) {
+			return 0;
+		}
+		udelay(10);
+
+	} while (timeout--);
+
+	return -1;
+}
+
+/* Enable System Port RX DMA */
+static int sysport_enable_rdma(struct sysport_priv *priv)
+{
+
+	int init_0 =0, init_1=0;
+
+	if(priv->sys_port_rdma[0] != NULL)
+		init_0=__sp_enable_rdma(priv->sys_port_rdma[0]);
+
+	if(priv->sys_port_rdma[1] != NULL)
+		init_1=__sp_enable_rdma(priv->sys_port_rdma[1]);
+	if(init_0 != 0 || init_0 != 0)
+	{
+		init_0=-1;
+		printf("enble rdma failed [0] %d [1] %d\n", init_0, init_1);
+	}
+	return init_0;
+}
+
+static int __sp_init(volatile sys_port_rbuf *sysport_rbuf, volatile sys_port_rdma *sysport_rdma, volatile sys_port_tdma *sysport_tdma, unsigned char *dma_buffer_addr)
+{
+
+	/* all memory allocation are done already */
+	uint32_t v32 = 0;
+
+	/* System Port RBUF configuration */
+	v32 = sysport_rbuf->SYSTEMPORT_RBUF_RBUF_CONTROL;     /* Read Chip Defaults */
+	v32 &= ~SYSPORT_RBUF_CTRL_RSB_MODE_M;                   /* Disable RSB */
+	v32 &= ~SYSPORT_RBUF_CTRL_4B_ALIGN_M;                 /* Disable 4-Byte IP Alignment */
+	v32 &= ~SYSPORT_RBUF_CTRL_BTAG_STRIP_M;               /* Do not strip BRCM TAG */
+	v32 |= SYSPORT_RBUF_CTRL_BAD_PKT_DISCARD_M;           /* Discard Bad Packets */
+	/* Read-Modify-Write */
+	sysport_rbuf->SYSTEMPORT_RBUF_RBUF_CONTROL=v32; 
+
+	sysport_rbuf->SYSTEMPORT_RBUF_RBUF_PACKET_READY_THRESHOLD=0x80; /* Keep chip default */
+
+	/* System Port TBUF configuration -- No change, keep chip defaults */
+
+	/* System Port RDMA Configuration */
+
+/*since default has the correct values, and there is bit variation between 63158/178 and 47622, keep this unchanged */
+#if 0
+	/* RDMA Control Register */
+	v32 = sysport_rdma->SYSTEMPORT_RDMA_CONTROL;  /* Read Chip Defaults */
+	v32 &= ~SYSPORT_RDMA_CTRL_RDMA_EN_M;          /* Disable RDMA */
+	v32 &= ~SYSPORT_RDMA_CTRL_RING_CFG_bit1_M;          /* Enable Descriptor Ring Mode */
+	v32 |= SYSPORT_RDMA_CTRL_DISCARD_EN_M;        /* Enable Pkt discard by RDMA when ring full */
+	v32 &= ~SYSPORT_RDMA_CTRL_DATA_OFFSET_M;       /* Zero data offset - this feature could be used later to reduce host buffer size */
+	v32 &= ~SYSPORT_RDMA_CTRL_DDR_DESC_WR_EN_M;
+//	v32 |= SYSPORT_RDMA_CTRL_DDR_DESC_SWAP_M;     /* Both Byte and word swap enabled for Desc - TBD - need to understand */
+	/* Read-Modify-Write */
+	sysport_rdma->SYSTEMPORT_RDMA_CONTROL=v32; 
+#endif
+
+	/* RDMA Buffer and Ring Size Register */
+	//v32 = 0;/* Reset register  */
+	//v32 |= ( (SYSPORT_PKT_LEN_LOG2 << SYSPORT_RDMA_BSRS_BUF_SIZE_LOG2_S) & SYSPORT_RDMA_BSRS_BUF_SIZE_LOG2_M ); /* set buf size */
+	//v32 |= ( ((1<<SYSPORT_NUM_RX_PKT_DESC_LOG2) << SYSPORT_RDMA_BSRS_RING_SIZE_S) & SYSPORT_RDMA_BSRS_RING_SIZE_M ); /* force chip default of 512 */
+	sysport_rdma->SYSTEMPORT_RDMA_LOCRAM_DESCRING_SIZE[0]=SYSPORT_RDMA_RING_EN | (1<<SYSPORT_NUM_RX_PKT_DESC_LOG2);
+	sysport_rdma->SYSTEMPORT_RDMA_PKTBUF_SIZE[0]=SYSPORT_PKT_LEN_LOG2;
+
+
+	/* RDMA Consumer Index Register */
+	/* Initialize RX DMA consumer index - low 16 bit; High 16-bits are read-only */
+	sysport_rdma->SYSTEMPORT_RDMA_CINDEX[0]=0x0;
+	sysport_rdma->SYSTEMPORT_RDMA_PINDEX[0]=0x0;
+
+	/* RDMA Desc Start Address Registers */
+	/* In desciptor ring mode - start address is index = 0 */
+	sysport_rdma->SYSTEMPORT_RDMA_DDR_DESC_RING_START[0]=0;
+	sysport_rdma->SYSTEMPORT_RDMA_DDR_DESC_RING_START[1]=0;
+
+
+	init_pkt_desc(sysport_rdma->SYSTEMPORT_RDMA_DESCRIPTOR, dma_buffer_addr);
+
+	/* RDMA DDR Desc Ring Register */
+	//sysport_rdma->SYSTEMPORT_RDMA_DDR_DESC_RING_START_LOW = 0;
+	//sysport_rdma->SYSTEMPORT_RDMA_DDR_DESC_RING_START_HIGH = 0; /* Ideally we should put the Hi 8-bits here */
+
+	/* RDMA DDR Desc Ring Size Register */
+	sysport_rdma->SYSTEMPORT_RDMA_DDR_DESC_RING_SIZE[0] = SYSPORT_NUM_RX_PKT_DESC_LOG2;
+
+	/* RDMA Multi-Buffer-Done-Interrupt-Threshold : No timeout & interrupt every packet */
+	//sysport_rdma->SYSTEMPORT_RDMA_MULTIPLE_BUFFERS_DONE_INTERRUPT_THRESHOLD_PUSH_TIMER = 1;
+	/* enable DDR DESC write push timer to 1 timer tick (equals 1024 RDMA sys clocks */
+	//sysport_rdma->SYSTEMPORT_RDMA_DDR_DESC_RING_WR_PUSH_TIMER[0] = (0x1 & SYSTEMPORT_RDMA_DDR_DESC_RING_PUSH_TIMER_TIMEOUT_M);
+	/* TDMA Block Configuration */
+
+	/* System port supports upto 16 Desc Rings;
+	Only one TX DDR Desc ring is used; It is mapped to TX-Queue[0] */
+
+	/* Enable TX Q#0 */
+	//sysport_tdma->SYSTEMPORT_TDMA_DESC_RING_HEAD_TAIL_PTR[0] = SYSPORT_TDMA_DESC_RING_XX_HEAD_TAIL_PTR_RING_EN_M;
+
+	sysport_tdma->SYSTEMPORT_TDMA_DESC_RING_CONTROL[0]=SYSTEMPORT_TDMA_DESC_RING_CONTROL_RING_EN;
+	/* Initialize Producer & Consumer Index */
+	sysport_tdma->SYSTEMPORT_TDMA_DESC_RING_PRODUCER_CONSUMER_INDEX[0] = 0;
+	/* Q#0 DDR Desc Ring Address */
+	sysport_tdma->SYSTEMPORT_TDMA_DDR_DESC_RING_START[0] = 0;
+	sysport_tdma->SYSTEMPORT_TDMA_DDR_DESC_RING_START[1] = 0; /* Ideally this should be high 8-bit of address */
+
+	sysport_tdma->SYSTEMPORT_TDMA_DESC_RING_MAPPING[0] = 0x40;
+	/* enable DDR DESC read push timer to 1 timer tick (equals 1024 TDMA sys clocks */
+	sysport_tdma->SYSTEMPORT_TDMA_DDR_DESC_RING_PUSH_TIMER[0] = (0x1 & SYSTEMPORT_TDMA_DDR_DESC_RING_PUSH_TIMER_TIMEOUT_M);
+	/* Q#0 DDR Desc Ring Size Log2 */
+	sysport_tdma->SYSTEMPORT_TDMA_DDR_DESC_RING_SIZE[0] = SYSPORT_NUM_TX_PKT_DESC_LOG2;
+	sysport_tdma->SYSTEMPORT_TDMA_DESC_RING_INTR_CONTROL[0] = 0x3;
+	sysport_tdma->SYSTEMPORT_TDMA_DESC_RING_MAX_THRESHOLD[0] = 0x00100009;
+	/* enable arbitrator for Q#0 */
+	sysport_tdma->SYSTEMPORT_TDMA_TIER2_ARBITER_CTRL = 0x1; /* Round Robin */
+	sysport_tdma->SYSTEMPORT_TDMA_TIER1_ARBITER_CTRL[0] = 0x1;
+	sysport_tdma->SYSTEMPORT_TDMA_TIER1_ARBITER_CTRL[1] = 0x1;
+	sysport_tdma->SYSTEMPORT_TDMA_TIER1_ARBITER_CTRL[2] = 0x1;
+	sysport_tdma->SYSTEMPORT_TDMA_TIER1_ARBITER_CTRL[3] = 0x1;
+	sysport_tdma->SYSTEMPORT_TDMA_TIER1_ARBITER_QUEUE_ENABLE[0] = 0x000000ff;
+	sysport_tdma->SYSTEMPORT_TDMA_TIER1_ARBITER_QUEUE_ENABLE[1] = 0x0000ff00;
+	sysport_tdma->SYSTEMPORT_TDMA_TIER1_ARBITER_QUEUE_ENABLE[2] = 0x00ff0000;
+	sysport_tdma->SYSTEMPORT_TDMA_TIER1_ARBITER_QUEUE_ENABLE[3] = 0xff000000;
+	/* TDMA Control Register */
+	v32 = sysport_tdma->SYSTEMPORT_TDMA_CONTROL; /* Read chip defaults */
+	v32 &= ~SYSPORT_TDMA_CONTROL_TSB_EN_M; /* Disable TSB */
+	v32 &= ~(SYSPORT_TDMA_CONTROL_RING_CFG_M); /* Disable DDR Desc Ring fetch */
+	v32 &= ~(SYSPORT_TDMA_CONTROL_ACB_EN_M); /* No ACB */
+	sysport_tdma->SYSTEMPORT_TDMA_CONTROL = v32;
+
+	/* Enable Tier-1 arbiter for Q#0 */
+	sysport_tdma->SYSTEMPORT_TDMA_TIER1_ARBITER_QUEUE_ENABLE[0]=0x1;
+
+
+	return 0;
+}
+
+
+static int sysport_init(struct udevice *dev)
+{
+	struct sysport_priv *priv = dev_get_priv(dev);
+	uint32_t v32;
+	int i;
+
+	if (!priv->init)
+	{
+		for (i = 0; i < MAX_ETHSW; i++)
+    		if (priv->ethsw_devp[i])
+    			priv->ethsw_ops[i]->open (priv->ethsw_devp[i]);
+
+		/* all memory allocation are done already */
+		if (priv->sys_port_rbuf[0] != NULL) {
+			__sp_init(priv->sys_port_rbuf[0], priv->sys_port_rdma[0], priv->sys_port_tdma[0], priv->buffers[0]); 
+		}
+		if (priv->sys_port_rbuf[1] != NULL) {
+			__sp_init(priv->sys_port_rbuf[1], priv->sys_port_rdma[1], priv->sys_port_tdma[1], priv->buffers[1]); 
+		}
+
+		if(priv->sys_port_gib != NULL)
+		{
+			v32=priv->sys_port_gib->SYSTEMPORT_GIB_CONTROL;
+			v32 |= SYSPORT_GIB_CONTROL_TX_EN | SYSPORT_GIB_CONTROL_RX_EN;
+			priv->sys_port_gib->SYSTEMPORT_GIB_CONTROL = v32;
+		}
+
+		// Enable RX DMA
+		if (sysport_enable_rdma(priv) < 0) {
+			// Print SPIF for System Port Init Failed
+
+			return -1;
+		}
+
+		// Enable TX DMA
+		if (sysport_enable_tdma(priv) < 0) {
+			// Print SPIF for System Port Init Failed
+
+			return -1;
+		}
+
+		if(priv->sys_port_umac[0] != NULL)
+		{
+			v32 = priv->sys_port_umac[0]->SYSTEMPORT_UMAC_CMD;
+			v32 |= SYSPORT_UNIMAC_COMMAND_CONFIG_TX_EN; /* Enable TX */
+			v32 |= SYSPORT_UNIMAC_COMMAND_CONFIG_RX_EN; /* Enable RX */
+			priv->sys_port_umac[0]->SYSTEMPORT_UMAC_CMD=v32;
+		}
+		if(priv->sys_port_umac[1] != NULL)
+		{
+			v32 = priv->sys_port_umac[1]->SYSTEMPORT_UMAC_CMD;
+			v32 |= SYSPORT_UNIMAC_COMMAND_CONFIG_TX_EN; /* Enable TX */
+			v32 |= SYSPORT_UNIMAC_COMMAND_CONFIG_RX_EN; /* Enable RX */
+			priv->sys_port_umac[1]->SYSTEMPORT_UMAC_CMD=v32;
+		}
+
+		// Give SP some time to initialize
+		udelay(100);
+
+
+			
+	}
+	priv->init++;
+	return 0;
+}
+
+
+static int __sp_send(volatile sys_port_tdma *sysport_tdma, unsigned char* tx_dma_bufaddr, uint8_t *buffer, uint32_t length)
+{
+	int timeout = 1000;
+	uint32_t p_index, c_index;
+	uint32_t txdesc_hi, txdesc_lo;
+
+	if (length > MAX_PKT_LEN) {
+		// Print SPWE for SP Write Error
+
+		return -1;
+	}
+
+	memcpy((void *)(tx_dma_bufaddr), buffer, length);
+	flush_cache((unsigned long)tx_dma_bufaddr, NET_DMA_BUFSIZE);
+
+	// set up txdesc record: eop=1, sop=1, append_crc=1
+	txdesc_hi = (length << 18) | (3 << 16) | (1 << 11);
+	txdesc_lo = (uint32_t)(tx_dma_bufaddr);
+
+	// write tx desc to hw
+	// SYSTEMPORT_TDMA_DESCRIPTOR_00_WRITE_PORT_LO
+	sysport_tdma->SYSTEMPORT_TDMA_DESCRIPTOR_WRITE_PORT[0].SYSTEMPORT_TDMA_DESCRIPTOR_XX_WRITE_PORT_LO=txdesc_lo;
+
+        barrier();
+
+	// SYSTEMPORT_TDMA_DESCRIPTOR_00_WRITE_PORT_HI
+	sysport_tdma->SYSTEMPORT_TDMA_DESCRIPTOR_WRITE_PORT[0].SYSTEMPORT_TDMA_DESCRIPTOR_XX_WRITE_PORT_HI=txdesc_hi;
+
+	// wait until the packet is fully DMA'ed and stored into TBUF
+	do {
+		// SYSTEMPORT_TDMA_DESC_RING_00_PRODUCER_CONSUMER_INDEX
+		p_index = sysport_tdma->SYSTEMPORT_TDMA_DESC_RING_PRODUCER_CONSUMER_INDEX[0];
+		c_index = (p_index >> 16);
+		p_index &= 0xffff;
+		c_index &= 0xffff;
+
+	} while ((p_index != c_index) && timeout--);
+
+	if (timeout == 0) {
+		// Print SPWF for SP Write Failed
+
+		return -1;
+	}
+
+	return 0;
+}
+
+static int sysport_send(struct udevice *dev, void *buffer, int length)
+{
+	struct sysport_priv *priv=(struct sysport_priv*)dev->priv;
+
+	if(priv->active_sysport==SYSPORT_0)
+		__sp_send(priv->sys_port_tdma[0], priv->buffers[0], buffer, length);
+	if((priv->active_sysport==SYSPORT_1) && (priv->sys_port_tdma[1]))
+		__sp_send(priv->sys_port_tdma[1], priv->buffers[1], buffer, length);
+	return 0;
+
+
+}
+
+static int __sp_poll(volatile sys_port_rdma *sysport_rdma)
+{
+	uint32_t p_index, c_index;
+
+	// SYSTEMPORT_RDMA_PRODUCER_INDEX...
+	p_index = sysport_rdma->SYSTEMPORT_RDMA_PINDEX[0] & 0xffff;
+	c_index = sysport_rdma->SYSTEMPORT_RDMA_CINDEX[0] & 0xffff;
+
+	return (p_index == c_index);
+}
+
+static int sysport_poll(struct sysport_priv *priv, uint32_t timeout_ms)
+{
+	int i=0;
+	while (1) {
+
+		if(priv->sys_port_rdma[0] != NULL && __sp_poll(priv->sys_port_rdma[0]) == 0)
+		{
+			priv->active_sysport=SYSPORT_0;
+			return 0;
+		}
+ 		else if(priv->sys_port_rdma[1] != NULL && __sp_poll(priv->sys_port_rdma[1]) == 0)
+		{
+			priv->active_sysport=SYSPORT_1;
+			return 0;
+		}
+		if (i++ > timeout_ms)
+		{
+			return -1;
+		}
+		udelay(500);
+	}
+	return 0;
+}
+
+int __sp_recv(volatile sys_port_rdma *sysport_rdma, uint8_t *buffer, uint32_t *length)
+{
+	int rc = 0;
+	unsigned short rx_read_idx;
+	const uint8_t *bufaddr;
+	volatile PktDesc *pkt_desc;
+
+	rx_read_idx=sysport_rdma->SYSTEMPORT_RDMA_CINDEX[0];
+	rx_read_idx=rx_read_idx%NUM_RX_DMA_BUFFERS;
+	// Get RX DMA buffer address
+	pkt_desc=(PktDesc *)sysport_rdma->SYSTEMPORT_RDMA_DESCRIPTOR;
+
+	flush_cache(pkt_desc[rx_read_idx].address, NET_DMA_BUFSIZE);
+	bufaddr = (uint8_t *)((const uint8_t *)NULL + pkt_desc[rx_read_idx].address);
+
+	*length=pkt_desc[rx_read_idx].length;
+
+
+	if (*length < ENET_ZLEN || *length > MAX_PKT_LEN) {
+		// Print SPRE for System Port Read Error
+
+		rc = -1;
+		goto out;
+	}
+
+	memcpy(buffer, bufaddr, *length);
+        barrier();
+
+out:
+	sysport_rdma->SYSTEMPORT_RDMA_CINDEX[0]+=1;
+
+	return rc;
+}
+
+
+
+static int sysport_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	struct sysport_priv *priv = dev_get_priv(dev);
+	int rc = -1;
+	int length=0;
+
+	if(sysport_poll(priv, 2) == 0)
+	{
+		*packetp=(unsigned char *) static_buff;//memalign(sizeof(int), MAX_PKT_LEN);
+		if (*packetp == NULL) {
+			printf("%s: malloc failed\n", __func__);
+			rc = -ENOMEM;
+		} else {
+			if(priv->sys_port_rdma[0] != NULL && priv->active_sysport == SYSPORT_0)
+			{
+				__sp_recv(priv->sys_port_rdma[0], *packetp, &length);
+			}
+			else if(priv->sys_port_rdma[1] != NULL) 
+			{
+				__sp_recv(priv->sys_port_rdma[1], *packetp, &length);
+			}
+			rc = length;
+		}
+	}
+	return rc;
+}
+
+static int sysport_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+	if(packet != NULL && packet != static_buff)
+		free(packet);
+	return 0;
+}
+
+static void sysport_halt(struct udevice *dev)
+{
+}
+
+static int sysport_remove(struct udevice *dev)
+{
+	struct sysport_priv *priv = dev_get_priv(dev);
+	int i;
+
+	printf("remove sysport\n");
+	{
+	    for (i = 0; i < MAX_ETHSW; i++)
+    		if (priv->ethsw_devp[i])
+    			priv->ethsw_ops[i]->close (priv->ethsw_devp[i]);
+
+		sysport_reset(priv, 0, 1);
+
+		if(priv->sys_port_rdma[1] != NULL) 
+			sysport_reset(priv, 1, 1);
+	}
+
+	return 0;
+}
+
+
+static int sysport_read_rom_mac(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	u8 mac_addr[6]={0x02,0x10,0x00,0x00,0x00,0x01};
+        u8 mac_temp[6];
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_temp))
+	{
+		eth_env_set_enetaddr("ethaddr", mac_addr);
+	}
+	return 0;
+}
+
+static const struct eth_ops sysport_ops = {
+	.start			= sysport_init,
+	.send			= sysport_send,
+	.recv			= sysport_recv,
+	.free_pkt		= sysport_free_pkt,
+	.stop			= sysport_halt,
+//	.write_hwaddr		= sysport_setup_mac,
+	.read_rom_hwaddr	= sysport_read_rom_mac,
+};
+
+
+
+
+void sysport_reset(struct sysport_priv *priv, int port, int pmc_reset)
+{
+	volatile uint32_t v32;
+	uint16_t p_idx, c_idx, timeout;
+
+	if (priv->sys_port_umac[port])
+	{
+		v32 = priv->sys_port_umac[port]->SYSTEMPORT_UMAC_CMD;
+		v32 &= ~SYSPORT_UNIMAC_COMMAND_CONFIG_RX_EN; /* disable RX */
+		priv->sys_port_umac[port]->SYSTEMPORT_UMAC_CMD = v32;
+	}
+	if(priv->sys_port_gib != NULL)
+	{
+		v32 = priv->sys_port_gib->SYSTEMPORT_GIB_CONTROL;
+		v32 &= ~SYSPORT_GIB_CONTROL_RX_EN;
+		priv->sys_port_gib->SYSTEMPORT_GIB_CONTROL = v32;
+	}
+	// in case there is still DMA going on, wait for the last bit to finish	
+	udelay (1000);
+
+	// Disable and Flush RX DMA
+	priv->sys_port_rdma[port]->SYSTEMPORT_RDMA_CONTROL &= ~SYSPORT_RDMA_CTRL_RDMA_EN_M;
+	priv->sys_port_topctrl[port]->SYSTEMPORT_TOPCTRL_RX_FLUSH_CNTL=1;
+
+	if(priv->sys_port_gib != NULL)
+	{
+		v32 = priv->sys_port_gib->SYSTEMPORT_GIB_CONTROL;
+		v32 &= ~SYSPORT_GIB_CONTROL_RX_FLUSH;
+		priv->sys_port_gib->SYSTEMPORT_GIB_CONTROL = v32;
+	}
+
+	// Disable TX DMA
+	priv->sys_port_tdma[port]->SYSTEMPORT_TDMA_CONTROL &= ~SYSPORT_TDMA_CONTROL_TDMA_EN_M;
+	// wait till TXDMA is completed
+	timeout = 1000;
+	v32 = priv->sys_port_tdma[port]->SYSTEMPORT_TDMA_DESC_RING_PRODUCER_CONSUMER_INDEX[0];
+
+	p_idx = (uint16_t)(v32 & SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX_PRODUCER_INDEX_M);
+	c_idx = (uint16_t)(v32 >> SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX_CONSUMER_INDEX_S);
+
+	while ((p_idx != c_idx) && timeout)
+	{
+		udelay(1000);  	// will need to increase wait time if system port speed is slower 
+						// (e.g, it takes 1.2ms to transmit 1518 bytes packets when system port is running at 10 Mbps)
+		timeout --;
+		v32 = priv->sys_port_tdma[port]->SYSTEMPORT_TDMA_DESC_RING_PRODUCER_CONSUMER_INDEX[0];
+		p_idx = (uint16_t)(v32 & SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX_PRODUCER_INDEX_M);
+		c_idx = (uint16_t)(v32 >> SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX_CONSUMER_INDEX_S);
+	}
+	printf("system port tx wait %d timeout %d p %d c %d\n", port, timeout, p_idx, c_idx);
+	priv->sys_port_tdma[port]->SYSTEMPORT_TDMA_DESC_RING_PRODUCER_CONSUMER_INDEX[0] = 0;	
+
+	if (priv->sys_port_umac[port])
+	{
+		v32 = priv->sys_port_umac[port]->SYSTEMPORT_UMAC_CMD;
+		v32 &= ~SYSPORT_UNIMAC_COMMAND_CONFIG_TX_EN; /* disable RX */
+		priv->sys_port_umac[port]->SYSTEMPORT_UMAC_CMD = v32;
+	}
+	if(priv->sys_port_gib != NULL)
+	{
+		v32 = priv->sys_port_gib->SYSTEMPORT_GIB_CONTROL;
+		v32 &= ~SYSPORT_GIB_CONTROL_TX_EN;
+		priv->sys_port_gib->SYSTEMPORT_GIB_CONTROL = v32;
+	}
+	priv->sys_port_topctrl[port]->SYSTEMPORT_TOPCTRL_TX_FLUSH_CNTL=1;
+	udelay(100);
+
+	priv->sys_port_topctrl[port]->SYSTEMPORT_TOPCTRL_RX_FLUSH_CNTL=0;
+	priv->sys_port_topctrl[port]->SYSTEMPORT_TOPCTRL_TX_FLUSH_CNTL=0;
+
+	if(priv->sys_port_gib != NULL)
+	{
+		v32 = priv->sys_port_gib->SYSTEMPORT_GIB_CONTROL;
+		v32 &= ~SYSPORT_GIB_CONTROL_TX_FLUSH;
+		v32 &= ~SYSPORT_GIB_CONTROL_RX_FLUSH;
+		priv->sys_port_gib->SYSTEMPORT_GIB_CONTROL = v32;
+	}
+
+	if (pmc_reset)
+	{
+		pmc_sysport_reset_system_port(port);
+	}
+}
+
+static int sysport_probe(struct udevice *dev)
+{
+	struct resource res;
+	int ret=0, size, i;
+	struct sysport_priv *priv = dev_get_priv(dev);
+	struct udevice *ethsw_devp;
+	bcm_ethsw_ops_t *ethsw_ops;
+	uint phandle_id;
+	const fdt32_t *list;
+
+	priv->active_sysport=SYSPORT_0;
+
+	priv->buffers[0]=memalign(ARCH_DMA_MINALIGN, NUM_DMA_BUFFERS*NET_DMA_BUFSIZE);
+	if (priv->buffers[0] == NULL) {
+		printf("%s: malloc failed\n", __func__);
+		return -ENOMEM;
+	}
+	memset(priv->buffers[0], 0x0, NUM_DMA_BUFFERS*NET_DMA_BUFSIZE);
+	flush_cache((unsigned long)(priv->buffers[0]), NUM_DMA_BUFFERS*NET_DMA_BUFSIZE);
+	
+	priv->buffers[1]=memalign(ARCH_DMA_MINALIGN, NUM_DMA_BUFFERS*NET_DMA_BUFSIZE);
+	if (priv->buffers[1] == NULL) {
+		printf("%s: malloc failed\n", __func__);
+		return -ENOMEM;
+	}
+	memset(priv->buffers[1], 0x0, NUM_DMA_BUFFERS*NET_DMA_BUFSIZE);
+	flush_cache((unsigned long)(priv->buffers[1]), NUM_DMA_BUFFERS*NET_DMA_BUFSIZE);
+	
+	ret = dev_read_resource_byname(dev, "systemport-rbuf-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs systemport-rbuf--base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->sys_port_rbuf[0]=devm_ioremap(dev, res.start, resource_size(&res));
+	ret = dev_read_resource_byname(dev, "systemport-rdma-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs systemport-rdma-base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->sys_port_rdma[0]=devm_ioremap(dev, res.start, resource_size(&res));
+	ret = dev_read_resource_byname(dev, "systemport-tdma-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs systemport-tdma-base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->sys_port_tdma[0]=devm_ioremap(dev, res.start, resource_size(&res));
+	ret = dev_read_resource_byname(dev, "systemport-gib-base", &res);
+	if (!ret) {
+		//dev_err(dev, "can't get regs systemport-gib-base address(ret = %d)!\n", ret);
+		priv->sys_port_gib=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+
+	ret = dev_read_resource_byname(dev, "systemport-umac-base", &res);
+	if (!ret) {
+		//dev_err(dev, "can't get regs systemport-umac-base address(ret = %d)!\n", ret);
+		//return ret;
+		priv->sys_port_umac[0]=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	ret = dev_read_resource_byname(dev, "systemport-topctrl-base", &res);
+	if (ret) {
+		dev_err(dev, "can't get regs systemport-topctrl-base address(ret = %d)!\n", ret);
+		return ret;
+	}
+	priv->sys_port_topctrl[0]=devm_ioremap(dev, res.start, resource_size(&res));
+
+	// read in systemport 1 registers
+	ret = dev_read_resource_byname(dev, "systemport1-rbuf-base", &res);
+	if (!ret) {
+		priv->sys_port_rbuf[1]=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	ret = dev_read_resource_byname(dev, "systemport1-rdma-base", &res);
+	if (!ret) {
+		priv->sys_port_rdma[1]=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	ret = dev_read_resource_byname(dev, "systemport1-tdma-base", &res);
+	if (!ret) {
+		priv->sys_port_tdma[1]=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+
+	ret = dev_read_resource_byname(dev, "systemport1-umac-base", &res);
+	if (!ret) {
+		priv->sys_port_umac[1]=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+	ret = dev_read_resource_byname(dev, "systemport1-topctrl-base", &res);
+	if (!ret) {
+		priv->sys_port_topctrl[1]=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+
+	if (priv->sys_port_rbuf[1]) {
+#if defined (CONFIG_BCMBCA_PMC_SYSPORT)
+		priv->active_sysport=SYSPORT_1;
+		pmc_sysport_power_up();
+#endif
+	}
+	ret = dev_read_resource_byname(dev, "systemport-switchmdio-base", &res);
+	priv->switch_mdio=NULL;
+	if (!ret) {
+		priv->switch_mdio=devm_ioremap(dev, res.start, resource_size(&res));
+		phy_set_mdio_base(priv->switch_mdio);
+	}
+
+	ret = dev_read_resource_byname(dev, "phy-test-ctrl", &res);
+	priv->phy_test_ctrl=NULL;
+	if (!ret) {
+		priv->phy_test_ctrl=devm_ioremap(dev, res.start, resource_size(&res));
+	}
+
+	ret = dev_read_resource_byname(dev, "sphy-ctrl", &res);
+	priv->sphy_ctrl=NULL;
+	if (!ret) {
+		priv->sphy_ctrl=devm_ioremap(dev, res.start, resource_size(&res));
+
+		// sysport driver only takes care of of PHY power on for 47622 when sphy is specified
+		priv->phy_base = dev_read_u32_default(dev, "phy_base", 1);
+		priv->phy_wkard_timeout = 0;
+		dev_read_u32(dev, "phy_wkard_timeout", &priv->phy_wkard_timeout);
+
+		printf("calling phy_wkard_timeout %d\n", priv->phy_wkard_timeout);
+		gphy_powerup(priv->phy_base, priv->phy_wkard_timeout, priv->sphy_ctrl, NULL, priv->phy_test_ctrl);
+		phy_advertise_caps(priv->phy_base | ADVERTISE_ALL_GMII | PHY_ADV_CFG_VALID);
+	}
+	// look for the switch driver
+	for (i = 0; i < MAX_ETHSW; i++ )
+	{
+		priv->ethsw_devp[i] = NULL;
+		list = dev_read_prop(dev, (i)? "ethsw_ext":"ethsw", &size);
+		if (size > 0)
+		{
+			phandle_id = fdt32_to_cpu(*list);
+			if (!uclass_get_device_by_phandle_id(UCLASS_NOP, phandle_id, &ethsw_devp))
+			{
+				printf("%s eth switch found, should have been probed name %s driver name %s\n", i? "ext":"", 
+				ethsw_devp->name, ethsw_devp->driver->name);
+				ethsw_ops = dev_get_priv(ethsw_devp);
+				priv->ethsw_devp[i] = ethsw_devp;
+				priv->ethsw_ops[i] = ethsw_ops;
+				ethsw_ops->init (ethsw_devp);
+			}
+		}
+	}
+
+	return 0;
+}
+
+static const struct udevice_id sysport_bcmbca_match_ids[] = {
+	{ .compatible = "brcm,bcmbca-systemport-v2.0"},
+	{ }
+};
+
+
+U_BOOT_DRIVER(sysport) = {
+	.name	= "sysport",
+	.id	= UCLASS_ETH,
+	.of_match = sysport_bcmbca_match_ids,
+	.flags = DM_REMOVE_ACTIVE_ALL,
+//	.ofdata_to_platdata = sysport_ofdata_to_platdata,
+	.probe	= sysport_probe,
+	.remove	= sysport_remove,
+	.ops	= &sysport_ops,
+	.priv_auto_alloc_size = sizeof(struct sysport_priv),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
diff --git a/drivers/net/bcmbca/bcmbca_sysport_v2.h b/drivers/net/bcmbca/bcmbca_sysport_v2.h
new file mode 100644
index 0000000000..d4a156c241
--- /dev/null
+++ b/drivers/net/bcmbca/bcmbca_sysport_v2.h
@@ -0,0 +1,293 @@
+
+#include <common.h>
+
+/*====move this to a .h file===============================================*/
+#define SYSPORT_NUM_RX_PKT_DESC_LOG2  (7)
+
+#define SYSPORT_NUM_TX_PKT_DESC_LOG2  (0)
+
+#define SYSPORT_PKT_LEN_LOG2 (11)
+
+/* Number of RX DMA buffers */
+#define NUM_RX_DMA_BUFFERS		(1<<SYSPORT_NUM_RX_PKT_DESC_LOG2)
+
+/* Number of RX DMA buffers */
+#define NUM_TX_DMA_BUFFERS		(1<<SYSPORT_NUM_TX_PKT_DESC_LOG2)
+
+/* Total number of DMA buffers */
+#define NUM_DMA_BUFFERS			(NUM_RX_DMA_BUFFERS + NUM_TX_DMA_BUFFERS)
+
+/* RX/TX DMA buffer size */
+#define NET_DMA_BUFSIZE			2048
+
+/* DMA buffer size for SP_RDMA_BSRS_REG register (2048 bytes) */
+#define NET_DMA_SHIFT			11
+
+#define ENET_ZLEN                               60
+
+typedef struct PktDesc {
+    uint32_t address ;
+    uint32_t address_hi :8;
+    uint32_t status :10;
+    uint32_t length :14;
+}PktDesc;
+
+/*===================================================*/
+
+typedef struct sys_port_topctrl {
+	uint32_t SYSTEMPORT_TOPCTRL_REV_CNTL;
+	uint32_t SYSTEMPORT_TOPCTRL_RX_FLUSH_CNTL;
+	uint32_t SYSTEMPORT_TOPCTRL_TX_FLUSH_CNTL;
+	uint32_t SYSTEMPORT_TOPCTRL_MISC_CNTL;
+	uint32_t SYSTEMPORT_TOPCTRL_PM_CNTL;
+	uint32_t SYSTEMPORT_TOPCTRL_PM_STATUS;
+	uint32_t SYSTEMPORT_TOPCTRL_TIMER_TICK_CNTL;
+	uint32_t SYSTEMPORT_TOPCTRL_WR_REPLY_CFG;
+	uint32_t SYSTEMPORT_TOPCTRL_MISC_SWAP_CFG;
+	uint32_t SYSTEMPORT_TOPCTRL_UMAC_RXERR_MASK;
+	uint32_t SYSTEMPORT_TOPCTRL_MIB_MAX_PKT_SIZE;
+	uint32_t SYSTEMPORT_TOPCTRL_TIMER0_TIMEOUT_PERIOD;
+	uint32_t reserved[3];
+	uint32_t SYSTEMPORT_TOPCTRL_TIMER1_TIMEOUT_PERIOD;
+}sys_port_topctrl, SYSTEMPORT_TOPCTRL;
+
+
+#define FIELD_MASK(bits, shift)  ( ( (1ULL<<(bits)) - 1 ) << shift )
+
+
+#define SYSPORT_RDMA_CTRL_RDMA_EN_M             FIELD_MASK(1,0)
+#if defined(CONFIG_BCM6756)
+#define SYSPORT_RDMA_CTRL_RING_CFG_M            FIELD_MASK(2,1)
+#define SYSPORT_RDMA_CTRL_RING_CFG_bit0_M       FIELD_MASK(1,1)
+#define SYSPORT_RDMA_CTRL_RING_CFG_bit1_M       FIELD_MASK(1,2)
+#define SYSPORT_RDMA_CTRL_DISCARD_EN_M          FIELD_MASK(1,3)
+#else
+#define SYSPORT_RDMA_CTRL_RING_CFG_bit1_M       FIELD_MASK(1,1)
+#define SYSPORT_RDMA_CTRL_DISCARD_EN_M          FIELD_MASK(1,2)
+#define SYSPORT_RDMA_CTRL_RING_CFG_bit0_M       FIELD_MASK(1,14)
+#endif
+#define SYSPORT_RDMA_CTRL_DATA_OFFSET_M         FIELD_MASK(10,4)
+#define SYSPORT_RDMA_CTRL_DDR_DESC_WR_EN_M      FIELD_MASK(1,15)
+#define SYSPORT_RDMA_CTRL_PSB_EN_M              FIELD_MASK(1,18)
+
+#define SYSPORT_RDMA_STATUS_RDMA_DISABLED_M     FIELD_MASK(1,0)
+#define SYSPORT_RDMA_STATUS_DESC_RAM_BUSY_M     FIELD_MASK(1,1)
+
+#define SYSTEMPORT_RDMA_LOCRAM_DESCRING_SIZE_MAX            256
+#define SYSTEMPORT_RDMA_LOCRAM_DESCRING_SIZE_RING_FLUSH_M   FIELD_MASK(1,16)
+#define SYSTEMPORT_RDMA_LOCRAM_DESCRING_SIZE_RING_EN_M      FIELD_MASK(1,17)
+
+#define SYSPORT_RDMA_PSB_INTR_CFG_THRESHOLD_M     FIELD_MASK(16,0)
+#define SYSPORT_RDMA_PSB_INTR_CFG_THRESHOLD_S     0
+#define SYSPORT_RDMA_PSB_INTR_CFG_TIMEOUT_M       FIELD_MASK(16,16)
+#define SYSPORT_RDMA_PSB_INTR_CFG_TIMEOUT_S       16
+
+typedef struct sys_port_rdma {
+	uint32_t SYSTEMPORT_RDMA_DESCRIPTOR[1024];
+	uint32_t SYSTEMPORT_RDMA_DESC_WRITE_PORT[16];
+	uint32_t SYSTEMPORT_RDMA_DESC_READ_PORT[16];
+	uint32_t SYSTEMPORT_RDMA_CONTROL;
+	uint32_t SYSTEMPORT_RDMA_STATUS;
+	uint32_t SYSTEMPORT_RDMA_SYSBUS_BURST;
+	uint32_t SYSTEMPORT_RDMA_SWITCH_PORT_BP_EN;
+	uint32_t SYSTEMPORT_RDMA_RXQ_TO_SWITCH_EGRESS_QUEUES_BP_MAP[8];
+#define SYSPORT_RDMA_RING_EN	(1<<17)
+	uint32_t SYSTEMPORT_RDMA_LOCRAM_DESCRING_SIZE[8];
+	uint32_t SYSTEMPORT_RDMA_PKTBUF_SIZE[8];
+	uint32_t SYSTEMPORT_RDMA_PINDEX[8];
+	uint32_t SYSTEMPORT_RDMA_CINDEX[8];
+	uint32_t SYSTEMPORT_RDMA_BUFDONE_INTR_CFG[8];
+	uint32_t SYSTEMPORT_RDMA_XON_XOFF_CFG[8];
+	uint32_t SYSTEMPORT_RDMA_DDR_DESC_RING_START[16];
+	uint32_t SYSTEMPORT_RDMA_DDR_DESC_RING_SIZE[8];
+	uint32_t SYSTEMPORT_RDMA_DDR_DESC_RING_CTRL[8];
+	uint32_t SYSTEMPORT_RDMA_DDR_DESC_RING_WR_PUSH_TIMER[8];
+#if defined(CONFIG_BCM6756)
+	uint32_t SYSTEMPORT_RDMA_DISCARD_CNT[8];
+#endif
+	uint32_t SYSTEMPORT_RDMA_BP_STATUS;
+	uint32_t SYSTEMPORT_RDMA_DESC_RAM_ARB_CONTROL;
+	uint32_t SYSTEMPORT_RDMA_DESC_RAM_RD_ARB_CFG;
+	uint32_t SYSTEMPORT_RDMA_DESC_RAM_WR_ARB_CFG;
+	uint32_t SYSTEMPORT_RDMA_PSB_INTR_CFG;
+	uint32_t SYSTEMPORT_RDMA_PSB_ADDR_LO;
+	uint32_t SYSTEMPORT_RDMA_PSB_ADDR_HI;
+#if defined(CONFIG_BCM6756)
+	uint32_t SYSTEMPORT_RDMA_MPM_CFG;
+#endif
+	uint32_t SYSTEMPORT_RDMA_TEST;
+	uint32_t SYSTEMPORT_RDMA_DEBUG;
+}sys_port_rdma, SYSTEMPORT_RDMA;
+
+
+#define SYSPORT_RBUF_CTRL_RSB_MODE_M          FIELD_MASK(2,0)
+#define SYSPORT_RBUF_CTRL_RSB_MODE_S          0
+#define SYSPORT_RBUF_CTRL_4B_ALIGN_M          FIELD_MASK(1,2)
+#define SYSPORT_RBUF_CTRL_BTAG_STRIP_M        FIELD_MASK(1,3)
+#define SYSPORT_RBUF_CTRL_BAD_PKT_DISCARD_M   FIELD_MASK(1,4)
+#define SYSPORT_RBUF_CTRL_CRC_REPLACE_M       FIELD_MASK(1,21)
+
+#define SYSPORT_RBUF_CTRL_RSB_MODE_NO_RSB     0
+#define SYSPORT_RBUF_CTRL_RSB_MODE_RSB8       1
+#define SYSPORT_RBUF_CTRL_RSB_MODE_RSB32      2
+
+#define SYSPORT_RBUF_PACKET_READY_THRESHOLD_PKT_RDY_THRESHOLD_M   FIELD_MASK(10,0)
+#define SYSPORT_RBUF_PACKET_READY_THRESHOLD_PKT_RDY_THRESHOLD_S   0
+#define SYSPORT_RBUF_PACKET_READY_THRESHOLD_RESUME_THRESHOLD_M    FIELD_MASK(10,16)
+#define SYSPORT_RBUF_PACKET_READY_THRESHOLD_RESUME_THRESHOLD_S    16
+
+typedef struct sys_port_rbuf {
+	uint32_t SYSTEMPORT_RBUF_RBUF_CONTROL;
+	uint32_t SYSTEMPORT_RBUF_RBUF_PACKET_READY_THRESHOLD;
+	uint32_t SYSTEMPORT_RBUF_RBUF_STATUS;
+	uint32_t SYSTEMPORT_RBUF_RBUF_OVERFLOW_PACKET_DISCARD_COUNT;
+	uint32_t SYSTEMPORT_RBUF_RBUF_ERROR_PACKET_COUNT;
+}sys_port_rbuf, SYSTEMPORT_RBUF;
+
+#define SYSTEMPORT_TDMA_DESC_RING_MAX        28
+#define SYSTEMPORT_TDMA_LOCRAM_DESCRING_MAX  896
+
+#define SYSTEMPORT_TDMA_TIMEOUT_TICK_NSEC    1000 // tick = 1 usec (internal timer)
+
+typedef struct systemport_tdma_descriptor_write_port
+{
+		uint32_t SYSTEMPORT_TDMA_DESCRIPTOR_XX_WRITE_PORT_LO;
+		uint32_t SYSTEMPORT_TDMA_DESCRIPTOR_XX_WRITE_PORT_HI;
+}systemport_tdma_descriptor_write_port;
+
+typedef struct systemport_tdma_descriptor_read_port
+{
+		uint32_t SYSTEMPORT_TDMA_DESCRIPTOR_XX_READ_PORT_LO;
+		uint32_t SYSTEMPORT_TDMA_DESCRIPTOR_XX_READ_PORT_HI;
+}systemport_tdma_descriptor_read_port;
+
+#define SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX_CONSUMER_INDEX_S      16
+#define SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX_CONSUMER_INDEX_M      FIELD_MASK(16,16)
+#define SYSTEMPORT_TDMA_DESC_RING_XX_PRODUCER_CONSUMER_INDEX_PRODUCER_INDEX_M      FIELD_MASK(16,0)
+
+#define SYSPORT_TDMA_CONTROL_TDMA_EN_M                  FIELD_MASK(1,0)
+#define SYSPORT_TDMA_CONTROL_TSB_EN_M                   FIELD_MASK(1,1)
+#define SYSPORT_TDMA_CONTROL_DATA_OFFSET_M              FIELD_MASK(10,5)
+#define SYSPORT_TDMA_CONTROL_VLAN_EN_M                  FIELD_MASK(1,15)
+#define SYSPORT_TDMA_CONTROL_SW_BRCM_TAG_M              FIELD_MASK(1,16)
+#define SYSPORT_TDMA_CONTROL_WNC_PKT_SIZE_UPDATE_MODE   FIELD_MASK(1,17)
+#define SYSPORT_TDMA_CONTROL_SYNC_PKT_SIZE_UPDATE_MODE  FIELD_MASK(1,18)
+#define SYSPORT_TDMA_CONTROL_RING_CFG_M                 FIELD_MASK(1,19)
+#define SYSPORT_TDMA_CONTROL_MAX_INFLIGHT_PBUFDMA       FIELD_MASK(5,22)
+#define SYSPORT_TDMA_CONTROL_ACB_EN_M                   FIELD_MASK(1,27)
+#define SYSPORT_TDMA_CONTROL_CSB_WR_EN                  FIELD_MASK(1,28)
+#define SYSPORT_TDMA_CONTROL_TPD_16b_EN                 FIELD_MASK(1,29)
+
+#define SYSPORT_TDMA_DESC_RING_CONTROL_FLUSH_M          FIELD_MASK(1,0)
+#define SYSPORT_TDMA_DESC_RING_CONTROL_RING_EN_M        FIELD_MASK(1,1)
+
+#define SYSPORT_TDMA_DESC_RING_INTR_CONTROL_THRESHOLD_S      0
+#define SYSPORT_TDMA_DESC_RING_INTR_CONTROL_EMPTY_INTR_EN_M  FIELD_MASK(1,15)
+#define SYSPORT_TDMA_DESC_RING_INTR_CONTROL_TIMEOUT_S        16
+
+#define SYSPORT_TDMA_DESC_RING_MAPPING_QID_M            FIELD_MASK(3,0)
+#define SYSPORT_TDMA_DESC_RING_MAPPING_QID_S            0
+#define SYSPORT_TDMA_DESC_RING_MAPPING_PORT_ID_S        3
+#define SYSPORT_TDMA_DESC_RING_MAPPING_IGNORE_STATUS_M  FIELD_MASK(1,6)
+#define SYSPORT_TDMA_DESC_RING_MAPPING_CREDIT_S         8
+
+#define SYSTEMPORT_TDMA_ARBITER_MODE_SP           0
+#define SYSTEMPORT_TDMA_ARBITER_MODE_RR           1
+#define SYSTEMPORT_TDMA_ARBITER_MODE_WRR          2
+#define SYSTEMPORT_TDMA_ARBITER_MODE_DRR          3
+
+#define SYSPORT_TDMA_STATUS_TDMA_DISABLED_M       FIELD_MASK(1,0)
+#define SYSPORT_TDMA_STATUS_LL_RAM_INIT_BUSY_M    FIELD_MASK(1,1)
+
+#define SYSTEMPORT_TDMA_DDR_DESC_RING_PUSH_TIMER_TIMEOUT_M  FIELD_MASK(16,0)
+
+#define SYSTEMPORT_TDMA_TIER1_ARBITER_CTRL_CREDIT_M             FIELD_MASK(16,4)
+#define SYSTEMPORT_TDMA_TIER1_ARBITER_CTRL_CREDIT_S             4
+#define SYSTEMPORT_TDMA_TIER1_ARBITER_CTRL_IGNORE_CONGESTION_M  FIELD_MASK(1,2)
+#define SYSTEMPORT_TDMA_TIER1_ARBITER_CTRL_IGNORE_CONGESTION_S  2
+#define SYSTEMPORT_TDMA_TIER1_ARBITER_CTRL_ARB_MODE_M           FIELD_MASK(2,0)
+#define SYSTEMPORT_TDMA_TIER1_ARBITER_CTRL_ARB_MODE_S           0
+
+#define SYSPORT_TDMA_CSB_INTR_CFG_THRESHOLD_M     FIELD_MASK(16,0)
+#define SYSPORT_TDMA_CSB_INTR_CFG_THRESHOLD_S     0
+#define SYSPORT_TDMA_CSB_INTR_CFG_TIMEOUT_M       FIELD_MASK(16,16)
+#define SYSPORT_TDMA_CSB_INTR_CFG_TIMEOUT_S       16
+
+typedef struct sys_port_tdma {
+	systemport_tdma_descriptor_write_port SYSTEMPORT_TDMA_DESCRIPTOR_WRITE_PORT[32];
+	systemport_tdma_descriptor_read_port  SYSTEMPORT_TDMA_DESCRIPTOR_READ_PORT[32];
+#define SYSTEMPORT_TDMA_DESC_RING_CONTROL_RING_EN 0x02
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_CONTROL[32];
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_HEAD_TAIL_PTR[32];
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_COUNT[32];
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_MAX_THRESHOLD[32];
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_INTR_CONTROL[32];
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_PRODUCER_CONSUMER_INDEX[32];
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_MAPPING[32];
+	uint32_t SYSTEMPORT_TDMA_DESC_RING_PCP_DEI_VID[32];
+	uint32_t SYSTEMPORT_TDMA_DDR_DESC_RING_START[64];
+	uint32_t SYSTEMPORT_TDMA_DDR_DESC_RING_SIZE[32];
+	uint32_t SYSTEMPORT_TDMA_DDR_DESC_RING_CTRL[32];
+	uint32_t SYSTEMPORT_TDMA_DDR_DESC_RING_PUSH_TIMER[32];
+#if defined(CONFIG_BCM6756)
+	uint32_t SYSTEMPORT_TDMA_LS_CFG[32];
+#endif
+	uint32_t SYSTEMPORT_TDMA_DESC_READ_CMD;
+	uint32_t SYSTEMPORT_TDMA_CONTROL;
+	uint32_t SYSTEMPORT_TDMA_STATUS;
+	uint32_t SYSTEMPORT_TDMA_SYSBUS_BURST;
+	uint32_t SYSTEMPORT_TDMA_TIER1_ARBITER_CTRL[8];
+	uint32_t SYSTEMPORT_TDMA_TIER1_ARBITER_QUEUE_ENABLE[8];
+	uint32_t SYSTEMPORT_TDMA_TIER2_ARBITER_CTRL;
+	uint32_t SYSTEMPORT_TDMA_OVER_MAX_THRESHOLD_STATUS;
+	uint32_t SYSTEMPORT_TDMA_OVER_HYST_THRESHOLD_STATUS;
+	uint32_t SYSTEMPORT_TDMA_TPID;
+	uint32_t SYSTEMPORT_TDMA_FREE_LIST_HEAD_TAIL_PTR;
+	uint32_t SYSTEMPORT_TDMA_FREE_LIST_COUNT;
+	uint32_t SYSTEMPORT_TDMA_CSB_INTR_CFG;
+	uint32_t SYSTEMPORT_TDMA_CSB_ADDR_LO;
+	uint32_t SYSTEMPORT_TDMA_CSB_ADDR_HI;
+
+#if defined(CONFIG_BCM6756)
+	uint32_t SYSTEMPORT_TDMA_MPM_CFG;
+	uint32_t SYSTEMPORT_TDMA_RRING_PRODUCER_INDEX;
+	uint32_t SYSTEMPORT_TDMA_RRING_CONSUMER_INDEX;
+	uint32_t SYSTEMPORT_TDMA_RRING_ADDR_LO;
+	uint32_t SYSTEMPORT_TDMA_RRING_ADDR_HI;
+	uint32_t SYSTEMPORT_TDMA_RRING_SIZE;
+	uint32_t SYSTEMPORT_TDMA_RRING_BURST_CTRL;
+	uint32_t SYSTEMPORT_TDMA_RRING_WR_PUSH_TIMER;
+	uint32_t SYSTEMPORT_TDMA_RRING_CTRL;
+	uint32_t SYSTEMPORT_TDMA_RRING_INTR_CFG;
+	uint32_t SYSTEMPORT_TDMA_LS_ETHERTYPE;
+#endif
+	uint32_t SYSTEMPORT_TDMA_TEST;
+	uint32_t SYSTEMPORT_TDMA_DEBUG;
+
+#if defined(CONFIG_BCM6756)
+	uint32_t SYSTEMPORT_TDMA_RRING_BP_COUNT;
+#endif
+}sys_port_tdma, SYSTEMPORT_TDMA;
+
+typedef struct sys_port_gib {
+#define SYSPORT_GIB_CONTROL_RX_EN 0x02
+#define SYSPORT_GIB_CONTROL_TX_EN 0x01
+#define SYSPORT_GIB_CONTROL_RX_FLUSH 0x08
+#define SYSPORT_GIB_CONTROL_TX_FLUSH 0x04
+	uint32_t SYSTEMPORT_GIB_CONTROL;
+	uint32_t SYSTEMPORT_GIB_STATUS;
+	uint32_t SYSTEMPORT_GIB_MAC_DA_1;
+	uint32_t SYSTEMPORT_GIB_MAC_DA_0;
+	uint32_t SYSTEMPORT_GIB_RCVD_PKT_ERR_CNT;
+	uint32_t SYSTEMPORT_GIB_PKT_SIZE_CONTROL;
+} sys_port_gib, SYSTEMPORT_GIB;
+
+
+typedef struct sys_port_umac {
+	uint32_t SYSTEMPORT_UMAC_UMAC_DUMMY;
+	uint32_t SYSTEMPORT_UMAC_HD_BKP_CNTL;             //0x804
+#define SYSPORT_UNIMAC_COMMAND_CONFIG_ENA_EXT_CONFIG        FIELD_MASK(1,22)
+#define SYSPORT_UNIMAC_COMMAND_CONFIG_RX_EN 0x02
+#define SYSPORT_UNIMAC_COMMAND_CONFIG_TX_EN 0x01
+	uint32_t SYSTEMPORT_UMAC_CMD;
+}sys_port_umac;
diff --git a/drivers/net/bcmbca/bcmbca_xrdp_eth.c b/drivers/net/bcmbca/bcmbca_xrdp_eth.c
new file mode 100644
index 0000000000..d1e6a45b45
--- /dev/null
+++ b/drivers/net/bcmbca/bcmbca_xrdp_eth.c
@@ -0,0 +1,605 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright 2019 Broadcom Ltd.
+ *	Ido Brezel <ido.brezel@broadcom.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+#include <environment.h>
+#include <command.h>
+#include <dm/lists.h>
+#include <dm/device-internal.h>
+
+#ifdef CONFIG_BCMBCA_PMC_XRDP
+#include "pmc_xrdp.h"
+#endif
+#ifdef CONFIG_BCM6858
+#include "pmc_lport.h"
+#endif
+#ifdef CONFIG_BCMBCA_UBUS
+#include "bcm_ubus4.h"
+#endif
+
+#include "bca_common.h"
+#include "bus_drv.h"
+#include "mac_drv.h"
+#include "phy_drv.h"
+#include "bcmbca_xrdp_api.h"
+
+
+/* Min frame ethernet frame size without FCS */
+#define ETH_ZLEN 60
+
+static int active_port = -1;
+
+#ifdef CONFIG_BCMBCA_XRDP_ETH_SWITCH_IFACE
+static int env_active_port = -1;
+#define ENV_ACTIVE_PORT     "active_port"
+
+static int get_env_active_port(void)
+{
+	char *env = env_get(ENV_ACTIVE_PORT);
+
+	if (!env)
+		return -1;
+
+	return simple_strtoul(env, NULL, 10);
+}
+
+int bcmbca_xrdp_eth_active_port_get(void)
+{
+	return active_port;
+}
+
+int bcmbca_xrdp_eth_active_port_set(int port)
+{
+	phy_dev_t *phy_dev;
+
+	if (port < 0 || port >= dt_get_ports_num()) {
+		printf("port %d is out of range\n", port);
+		return -1;
+	}
+
+	phy_dev = dt_get_phy_dev(port);
+	if (!phy_dev) {
+		printf("port %d is not availabe\n", port);
+		return -1;
+	}
+
+	if (!phy_dev->link) {
+		printf("port %d can not be set to active when the link is down"\
+			"\n", port);
+		return -1;
+	}
+
+	active_port = port;
+
+	return 0;
+}
+
+int bcmbca_xrdp_eth_env_active_port_set(int port)
+{
+	env_active_port = -1;
+
+	if (port == -1)
+		return 0;
+
+	if (bcmbca_xrdp_eth_active_port_set(port))
+		return -1;
+
+	env_active_port = port;
+
+	return 0;
+}
+
+static int active_port_handle_poll(int port, int link)
+{
+	return env_active_port != -1; /* skip */
+}
+
+static void env_active_port_init(void)
+{
+	active_port = env_active_port = get_env_active_port();
+	if (active_port != -1)
+        printf("Active port was set to %d according to the environment "\
+        	"variable\n", active_port);
+}
+#endif
+
+static void mac_set_cfg_by_phy(phy_dev_t *phy_dev, mac_dev_t *mac_dev)
+{
+	mac_cfg_t mac_cfg = {};
+
+	if (!mac_dev || !phy_dev)
+		return;
+
+	mac_dev_disable(mac_dev);
+	mac_dev_cfg_get(mac_dev, &mac_cfg);
+
+	if (phy_dev->speed == PHY_SPEED_10)
+		mac_cfg.speed = MAC_SPEED_10;
+	else if (phy_dev->speed == PHY_SPEED_100)
+		mac_cfg.speed = MAC_SPEED_100;
+	else if (phy_dev->speed == PHY_SPEED_1000)
+		mac_cfg.speed = MAC_SPEED_1000;
+	else if (phy_dev->speed == PHY_SPEED_2500)
+		mac_cfg.speed = MAC_SPEED_2500;
+	else if (phy_dev->speed == PHY_SPEED_5000)
+		mac_cfg.speed = MAC_SPEED_5000;
+	else if (phy_dev->speed == PHY_SPEED_10000)
+		mac_cfg.speed = MAC_SPEED_10000;
+	else
+		mac_cfg.speed = MAC_SPEED_UNKNOWN;
+
+	mac_cfg.duplex = phy_dev->duplex == PHY_DUPLEX_FULL ? MAC_DUPLEX_FULL :
+		MAC_DUPLEX_HALF;
+	mac_dev_cfg_set(mac_dev, &mac_cfg);
+
+	if (phy_dev->link) {
+		char eth_addr[6];
+
+		eth_env_get_enetaddr("ethaddr", (uchar *)eth_addr);
+		// XXX: TODO
+		//struct eth_pdata *pdata = dev_get_platdata(dev);
+		//memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
+		mac_dev_pause_set(mac_dev, phy_dev->pause_rx, phy_dev->pause_tx,
+			eth_addr);
+		mac_dev_enable(mac_dev);
+	}
+}
+
+static int _net_init(void)
+{
+	int rc = 0;
+	static int is_initialized;
+
+	if (is_initialized)
+		return -1;
+
+#ifdef CONFIG_BCMBCA_UBUS
+	bcm_ubus_config();
+#endif
+
+#ifdef CONFIG_BCM6858
+	rc = pmc_lport_init();
+	if (rc) {
+		printf("pmc lport init failed\n");
+		goto error;
+	}
+#endif
+
+#ifdef CONFIG_BCMBCA_PMC_XRDP
+	rc = pmc_xrdp_init();
+	if (rc) {
+		printf("pmc xrdp init failed\n");
+		goto error;
+	}
+#endif
+
+	rc = bcmbca_xrdp_init();
+	if (rc) {
+		printf("XRDP init failed\n");
+		goto error;
+	}
+
+#ifndef CONFIG_BCMBCA_IKOS
+	rc = dt_probe();
+	if (rc) {
+		printf("device tree probe failed\n");
+		goto error;
+	}
+#endif
+
+	is_initialized = 1;
+
+error:
+	return rc;
+}
+
+static int _net_uninit(void)
+{
+	int i;
+	int rc = 0;
+
+	for (i = 0; i < dt_get_ports_num(); i++) {
+		mac_dev_t *mac_dev = dt_get_mac_dev(i);
+		phy_dev_t *phy_dev = dt_get_phy_dev(i);
+
+		if (phy_dev) {
+			phy_dev_power_set(phy_dev, 0);
+			phy_dev_del(phy_dev);
+		}
+
+		if (mac_dev) {
+			mac_dev_disable(mac_dev);
+			mac_dev_del(mac_dev);
+		}
+	}
+
+#ifdef CONFIG_BCMBCA_PMC_XRDP
+	rc = pmc_xrdp_shutdown();
+	if (rc) {
+		printf("pmc xrdp init failed\n");
+		goto exit;
+	}
+#endif
+
+#ifdef CONFIG_BCM6858
+	rc = pmc_lport_shutdown();
+	if (rc) {
+		printf("pmc lport shutdown failed\n");
+		goto exit;
+	}
+#endif
+
+#if defined(CONFIG_BCM6858) || defined(CONFIG_BCMBCA_PMC_XRDP)
+exit:
+#endif
+	return rc;
+}
+
+static void phy_poll(void)
+{
+	int i;
+
+	for (i = 0; i < dt_get_ports_num(); i++) {
+		int link;
+		mac_dev_t *mac_dev = dt_get_mac_dev(i);
+		phy_dev_t *phy_dev = dt_get_phy_dev(i);
+
+		if (!phy_dev)
+			continue;
+
+		link = phy_dev->link;
+		phy_dev_read_status(phy_dev);
+
+		if (link != phy_dev->link) {
+			mac_set_cfg_by_phy(phy_dev, mac_dev);
+			phy_dev_print_status(phy_dev);
+		}
+
+#ifdef CONFIG_BCMBCA_XRDP_ETH_SWITCH_IFACE
+		if (active_port_handle_poll(i, phy_dev->link))
+			continue;
+#endif
+
+		if (!phy_dev->link && active_port == i)
+			active_port = -1;
+
+		if (phy_dev->link && active_port < 0) {
+			active_port = i;
+			printf("active port %d\n", i);
+		}
+	}
+}
+
+void bcmbca_xrdp_eth_init(void)
+{
+	printf("XRDP Ethernet driver initialize\n");
+
+	unregister_cli_job_cb(bcmbca_xrdp_eth_init);
+	if (!_net_init())
+		register_cli_job_cb(1000, phy_poll);
+
+#ifdef CONFIG_BCMBCA_XRDP_ETH_SWITCH_IFACE
+	env_active_port_init();
+#endif
+}
+
+void bcmbca_xrdp_eth_uninit(void)
+{
+	printf("XRDP Ethernet driver un-initialize\n");
+
+	_net_uninit();
+}
+
+int bcmbca_xrdp_eth_phy_status(void)
+{
+	int i;
+	uint32_t phyid;
+
+	printk("|============================================================"\
+		"==========================|\n");
+	printf("|  Id |  State  |   Phy   | Addr |   Speed   | Duplex | Flowc"\
+	    "tl  |   Bus   |   PHYID   |\n");
+	printk("|============================================================"\
+		"==========================|\n");
+
+	for (i = 0; i < dt_get_ports_num(); i++) {
+		phy_dev_t *phy_dev = dt_get_phy_dev(i);
+
+		if (!phy_dev)
+			continue;
+
+		printk("| %2d  ", i);
+
+		phy_dev_phyid_get(phy_dev, &phyid);
+
+		printf("| %s%s ", i == active_port ? "*" : " ", phy_dev->link ?
+			" Up   " : " Down ");
+		printf("| %7s ", phy_dev->phy_drv->name);
+		printf("| 0x%02x ", phy_dev->addr);
+		printf("| %9s ", phy_dev->speed == PHY_SPEED_UNKNOWN ? "" :
+			phy_dev_speed_to_str(phy_dev->speed));
+		printf("| %5s  ", phy_dev->duplex == PHY_DUPLEX_UNKNOWN ? "" :
+			phy_dev_duplex_to_str(phy_dev->duplex));
+		printf("|  %4s	 ", phy_dev_flowctrl_to_str(phy_dev->pause_rx,
+			phy_dev->pause_tx));
+		printf("| %7s ", phy_dev->mii_type == PHY_MII_TYPE_UNKNOWN ? ""
+			: phy_dev_mii_type_to_str(phy_dev->mii_type));
+		printf("| %04x:%04x ", phyid >> 16, phyid & 0xffff);
+		printf("|\n");
+	}
+
+	printk("|============================================================"\
+		"==========================|\n");
+
+    return 0;
+}
+
+int bcmbca_xrdp_eth_mac_status(void)
+{
+	int i;
+
+	printk("|============================================================"\
+		"==========================|\n");
+	printf("|  Id |  State	|   Mac   | Addr |   Speed   | Duplex | "\
+		"Flowctl |  RX Pkt  |  TX Pkt  |\n");
+	printk("|============================================================"\
+		"==========================|\n");
+
+	for (i = 0; i < dt_get_ports_num(); i++) {
+		mac_dev_t *mac_dev = dt_get_mac_dev(i);
+		mac_cfg_t mac_cfg = {};
+		mac_stats_t mac_stats = {};
+		int pause_rx, pause_tx;
+
+		if (!mac_dev)
+			continue;
+
+		if (mac_dev_cfg_get(mac_dev, &mac_cfg)) {
+			printf("Failed to get MAC configuration\n");
+			continue;
+		}
+
+		if (mac_dev_stats_get(mac_dev, &mac_stats)) {
+			printf("Failed to get MAC statistics\n");
+			continue;
+		}
+
+		if (mac_dev_pause_get(mac_dev, &pause_rx, &pause_tx)) {
+			printf("Failed to get MAC pause status\n");
+			continue;
+		}
+
+		printk("| %2d  ", i);
+		printf("| %s%s ", i == active_port ? "*" : " ",
+			mac_dev->enabled ? " Up   " : " Down ");
+		printf("| %7s ", mac_dev->mac_drv->name);
+		printf("| 0x%02x ", mac_dev->mac_id);
+		printf("| %9s ", !mac_dev->enabled ||
+			mac_cfg.speed == MAC_SPEED_UNKNOWN ? "" :
+			phy_dev_speed_to_str(mac_cfg.speed));
+		printf("| %5s  ", !mac_dev->enabled ||
+			mac_cfg.duplex == MAC_DUPLEX_UNKNOWN ? "" :
+			phy_dev_duplex_to_str(mac_cfg.duplex));
+		printf("|  %4s	 ", mac_dev->enabled ?
+			phy_dev_flowctrl_to_str(pause_rx, pause_tx) : "");
+		printf("| %08lld ", mac_stats.rx_packet);
+		printf("| %08lld ", mac_stats.tx_packet);
+		printf("|\n");
+	}
+
+	printk("|============================================================"\
+		"==========================|\n");
+
+    return 0;
+}
+
+int do_eth_print_status(cmd_tbl_t *cmdtp, int flag, int argc,
+	char *const argv[])
+{
+	char *cmd = NULL;
+
+	if (argc == 2)
+		cmd = argv[1];
+
+	if (argc > 2)
+		return cmd_usage(cmdtp);
+
+	if (!cmd || !strcmp(cmd, "mac"))
+		bcmbca_xrdp_eth_mac_status();
+
+	if (!cmd || !strcmp(cmd, "phy"))
+		bcmbca_xrdp_eth_phy_status();
+
+	return 0;
+}
+
+U_BOOT_CMD(
+		xrdpeth_status, 7, 0, do_eth_print_status,
+		"Broadcom BCA XRDP eth controller management",
+		"xrdp_status [type]\n"
+		" - Print the XRDP Ethernet network driver status tables\n"
+		" - Argument can be phy or mac. If no argument provided,"
+		"both tables will be printed\n"
+		);
+
+static int get_ethaddr(struct udevice *dev)
+{
+	uchar v_mac[6] = {};
+
+	if (eth_env_get_enetaddr("ethaddr", v_mac)) {
+		eth_env_set_enetaddr_by_index("eth", dev->seq, v_mac);
+		printf("Using MAC Address %pM\n", v_mac);
+	}
+
+	return 0;
+}
+
+static int bcmbca_eth_probe(struct udevice *dev)
+{
+	get_ethaddr(dev);
+
+	return 0;
+}
+
+static int bcmbca_eth_start(struct udevice *dev)
+{
+#ifndef CONFIG_BCMBCA_XRDP_ETH_SWITCH_IFACE
+	uint32_t phyid;
+	phy_dev_t *phy_dev;
+
+	active_port = dev->seq;
+
+	phy_dev = dt_get_phy_dev(active_port);
+	if (!phy_dev) {
+		netdev_err(port->dev, "cannot connect to phy\n");
+		return -ENODEV;
+	}
+
+	phy_dev_phyid_get(phy_dev, &phyid);
+
+	if (!phy_dev->link) {
+		printf("%s: No link\n", phy_dev->phy_drv->name);
+		return -1;
+	}
+#endif
+
+	return 0;
+}
+
+static void bcmbca_eth_stop(struct udevice *dev)
+{
+	return;
+}
+
+static int bcmbca_eth_remove(struct udevice *dev)
+{
+	return 0;
+}
+
+static int bcmbca_eth_send(struct udevice *dev, void *buffer, int length)
+{
+	int rc;
+	uint8_t txbuf[ETH_ZLEN];
+	void *bufp = buffer;
+
+	if (length < ETH_ZLEN) {
+		memcpy(txbuf, buffer, length);
+		memset(txbuf + length, 0, ETH_ZLEN - length);
+		bufp = txbuf;
+	}
+
+	rc = bcmbca_xrdp_send(bufp, length, active_port);
+	if (rc) {
+		printf("%s:Failed to send packet len %d: error = %d\n",
+			__func__, length, rc);
+	}
+
+    return 0;
+}
+
+static int bcmbca_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	uint16_t length;
+	uint8_t rx_port;
+	int rc;
+
+	*packetp = net_rx_packets[0];
+	rc = bcmbca_xrdp_recv(packetp, &length, &rx_port);
+	if (rc == -ENOSR)
+		return -EAGAIN;
+
+	if (rx_port != active_port)
+		return -EAGAIN;
+
+	return length;
+}
+
+static const struct eth_ops bcmbca_eth_ops = {
+	.start = bcmbca_eth_start,
+	.send = bcmbca_eth_send,
+	.recv = bcmbca_eth_recv,
+	.stop = bcmbca_eth_stop,
+};
+
+static const struct udevice_id xrdp_ids[] = {
+	{
+		.compatible = "brcm,enet",
+		.data = 0,
+	},
+	{ }
+};
+
+#ifndef CONFIG_BCMBCA_XRDP_ETH_SWITCH_IFACE
+static struct driver xrdp_driver = {
+#else
+U_BOOT_DRIVER(xrdp_base) = {
+#endif
+	.name	= "xrdp_eth",
+	.id	= UCLASS_ETH,
+	.probe	= bcmbca_eth_probe,
+	.remove = bcmbca_eth_remove,
+	.ops	= &bcmbca_eth_ops,
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+#ifdef CONFIG_BCMBCA_XRDP_ETH_SWITCH_IFACE
+	.of_match = xrdp_ids,
+#endif
+};
+
+#ifndef CONFIG_BCMBCA_XRDP_ETH_SWITCH_IFACE
+static int xrdp_base_bind(struct udevice *parent)
+{
+	const void *blob = gd->fdt_blob;
+	int node = dev_of_offset(parent);
+	struct uclass_driver *drv;
+	struct udevice *dev;
+	struct eth_pdata *plat;
+	int subnode;
+	char *name;
+	u32 id;
+
+	/* Lookup eth driver */
+	drv = lists_uclass_lookup(UCLASS_ETH);
+	if (!drv) {
+		puts("Cannot find eth driver\n");
+		return -ENOENT;
+	}
+
+	node = fdt_first_subnode(blob, node);
+	fdt_for_each_subnode(subnode, blob, node) {
+		/* Skip disabled ports */
+		if (!fdtdec_get_is_enabled(blob, subnode))
+			continue;
+
+		plat = calloc(1, sizeof(*plat));
+		if (!plat)
+			return -ENOMEM;
+
+		id = fdtdec_get_int(blob, subnode, "reg", -1);
+
+		name = calloc(1, 16);
+		if (!name) {
+			free(plat);
+			return -ENOMEM;
+		}
+		sprintf(name, "xrdp-eth-%d", id);
+
+		/* Create child device UCLASS_ETH and bind it */
+		device_bind(parent, &xrdp_driver, name, plat, subnode, &dev);
+		dev_set_of_offset(dev, subnode);
+	}
+
+    return 0;
+}
+
+U_BOOT_DRIVER(xrdp_base) = {
+	.name	= "xrdp_base",
+	.id	= UCLASS_MISC,
+	.of_match = xrdp_ids,
+	.bind	= xrdp_base_bind,
+};
+#endif
diff --git a/drivers/net/bcmbca/lport/Makefile b/drivers/net/bcmbca/lport/Makefile
new file mode 100644
index 0000000000..4df5352cf3
--- /dev/null
+++ b/drivers/net/bcmbca/lport/Makefile
@@ -0,0 +1,41 @@
+BRCM_CHIP = $(patsubst "bcm%",%,$(CONFIG_SYS_SOC))
+BCMBCA_PATH = $(srctree)/drivers/net/bcmbca
+
+EXTRA_CFLAGS += -I$(BCMBCA_PATH)/phy
+EXTRA_CFLAGS += -I$(BCMBCA_PATH)/lport
+EXTRA_CFLAGS += -I$(BCMBCA_PATH)/lport/ag
+EXTRA_CFLAGS += -I$(BCMBCA_PATH)/xrdp
+EXTRA_CFLAGS += -I$(srctree)/include/dt-bindings/leds
+
+EXTRA_CFLAGS += -DCONFIG_BCM9$(BRCM_CHIP)
+
+obj-y += \
+	lport_drv.o \
+    lport_mdio.o \
+    lport_stats.o \
+    serdes_access.o \
+    merlin_direct_access.o \
+	ag/BCM6858_A0_LPORT_AG.o \
+	ag/BCM6858_A0LPORT_CTRL_AG.o \
+	ag/BCM6858_A0LPORT_INTR_AG.o \
+	ag/BCM6858_A0LPORT_LED_AG.o \
+	ag/BCM6858_A0LPORT_MAB_AG.o \
+	ag/BCM6858_A0LPORT_MDIO_AG.o \
+	ag/BCM6858_A0LPORT_MIB_AG.o \
+	ag/BCM6858_A0LPORT_RGMII_AG.o \
+	ag/BCM6858_A0LPORT_SRDS_AG.o \
+	ag/BCM6858_A0LPORT_XLMAC_AG.o \
+	ag/BCM6858_A0MIB_CONF_AG.o \
+	ag/BCM6858_A0XLMAC_CONF_AG.o \
+	ag/bcm6858_drivers_lport_ag.o \
+	ag/bcm6858_lport_ctrl_ag.o \
+	ag/bcm6858_lport_intr_ag.o \
+	ag/bcm6858_lport_led_ag.o \
+	ag/bcm6858_lport_mab_ag.o \
+	ag/bcm6858_lport_mdio_ag.o \
+	ag/bcm6858_lport_mib_ag.o \
+	ag/bcm6858_lport_rgmii_ag.o \
+	ag/bcm6858_lport_srds_ag.o \
+	ag/bcm6858_lport_xlmac_ag.o \
+	ag/bcm6858_mib_conf_ag.o \
+	ag/bcm6858_xlmac_conf_ag.o
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_CTRL_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_CTRL_AG.c
new file mode 100644
index 0000000000..8442cccc71
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_CTRL_AG.c
@@ -0,0 +1,1223 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+#if RU_INCLUDE_FIELD_DB
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD =
+{
+    "TIMEOUT_RST_DISABLE",
+#if RU_INCLUDE_DESC
+    "",
+    "When this bit is set, LPORT internal register bus bridges are not automatically reseted/reinitalized when the UBUS slave port times out.\n",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_P4_MODE
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD =
+{
+    "P4_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "P4 Mode:\n"
+    "0 : P4 operates in GMII mode.\n"
+    "1 : P4 operates in XGMII mode.\n",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_P0_MODE
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD =
+{
+    "P0_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "P0 Mode:\n"
+    "0 : P0 operates in GMII mode.\n"
+    "1 : P0 operates in XGMII mode.\n",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD =
+{
+    "GPORT_SEL_7",
+#if RU_INCLUDE_DESC
+    "",
+    "Port 7 PHY Select (Gigabit Mode):\n"
+    "0 : P7 is unconnected.\n"
+    "1 : SERDES0 is connected to P7.\n",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD =
+{
+    "GPORT_SEL_6",
+#if RU_INCLUDE_DESC
+    "",
+    "Port 6 PHY Select (Gigabit Mode):\n"
+    "0 : RGMII2 is connected to P6.\n"
+    "1 : SERDES3 is connected to P6.\n",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD =
+{
+    "GPORT_SEL_5",
+#if RU_INCLUDE_DESC
+    "",
+    "Port 5 PHY Select (Gigabit Mode):\n"
+    "0 : RGMII1 is connected to P5.\n"
+    "1 : SERDES2 is connected to P5.\n",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD =
+{
+    "GPORT_SEL_4",
+#if RU_INCLUDE_DESC
+    "",
+    "Port 4 PHY Select (Gigabit Mode):\n"
+    "0 : RGMII0 is connected to P4.\n"
+    "1 : SERDES1 is connected to P4.\n",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD =
+{
+    "GPORT_SEL_3",
+#if RU_INCLUDE_DESC
+    "",
+    "Port 3 PHY Select (Gigabit Mode):\n"
+    "0 : EGPHY4 is connected to P3.\n"
+    "1 : SERDES3 is connected to P3.\n",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD =
+{
+    "GPORT_SEL_2",
+#if RU_INCLUDE_DESC
+    "",
+    "Port 2 PHY Select (Gigabit Mode):\n"
+    "0 : EGPHY3 is connected to P2.\n"
+    "1 : SERDES2 is connected to P2.\n",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD =
+{
+    "GPORT_SEL_1",
+#if RU_INCLUDE_DESC
+    "",
+    "Port 1 PHY Select (Gigabit Mode):\n"
+    "0 : EGPHY2 is connected to P1.\n"
+    "1 : SERDES1 is connected to P1.\n",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD =
+{
+    "GPORT_SEL_0",
+#if RU_INCLUDE_DESC
+    "",
+    "Port 0 PHY Select (Gigabit Mode):\n"
+    "0 : EGPHY1 is connected to P0.\n"
+    "1 : SERDES0 is connected to P0.\n",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_REVISION_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LPORT_REVISION_LPORT_REV
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD =
+{
+    "LPORT_REV",
+#if RU_INCLUDE_DESC
+    "",
+    "LPORT revision.",
+#endif
+    LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD_MASK,
+    0,
+    LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD_WIDTH,
+    LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_REVISION_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD =
+{
+    "QUAD_PHY_REV",
+#if RU_INCLUDE_DESC
+    "",
+    "Quad EGPHY Revision Control Register.",
+#endif
+    LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD =
+{
+    "PLL_REFCLK_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "These bits are used to select the reference clock source to EGPHY:\n"
+    "00 : i_pll_refclk[0].\n"
+    "01 : i_pll_refclk[1].\n"
+    "10 : i_pll_refclk[2].\n"
+    "11 : TVCO.\n"
+    "Note: Do note change these bits from their default value before consulting with Broadcom.",
+#endif
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD =
+{
+    "PLL_SEL_DIV5",
+#if RU_INCLUDE_DESC
+    "",
+    "These bits are used to select the frequency of the reference clock source to EGPHY:\n"
+    "00 : 25MHz.\n"
+    "01 : 54MHz.\n"
+    "10 : 50MHz.\n"
+    "11 : reserved.\n"
+    "Note: Do note change these bits from their default value before consulting with Broadcom.",
+#endif
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD =
+{
+    "PLL_CLK125_250_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit is used to select the EGPHY PLL output clock frequency:\n"
+    "0 : 125MHz.\n"
+    "1 : 250MHz.\n"
+    "Note: Do note change this bit from its default value before consulting with Broadcom.",
+#endif
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD =
+{
+    "PHY_TEST_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "Enables EGPHY test mode within chip testmux:\n"
+    "0 : EGPHY is not in test mode.\n"
+    "1 : EGPHY is in test mode.\n"
+    "Note:This bit is combined with PHY_SEL.",
+#endif
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD =
+{
+    "PHY_PHYAD",
+#if RU_INCLUDE_DESC
+    "",
+    "Quad EGPHY base PHY address. "
+    "EGPHYs within quad EGPHY are addressed as base address + offset where offset=0,1,2,3.",
+#endif
+    LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_CNTRL_RESERVED1
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD =
+{
+    "RESERVED1",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD =
+{
+    "PHY_RESET",
+#if RU_INCLUDE_DESC
+    "",
+    "Quad EGPHY system reset. Must be held high for at leaset 60 us while system clock is running. "
+    "After reset de-assertion no EGPHY activity should occur for 20 us.",
+#endif
+    LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_CNTRL_CK25_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD =
+{
+    "CK25_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "Enable 25 MHz clock to quad EGPHY. "
+    "This bit should be cleared in quad EGPHY power down mode only when MDIO access is not required.",
+#endif
+    LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD =
+{
+    "IDDQ_GLOBAL_PWR",
+#if RU_INCLUDE_DESC
+    "",
+    "Enables isolation cells for quad EGPHY power gating.",
+#endif
+    LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD =
+{
+    "FORCE_DLL_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "Force DLL on.",
+#endif
+    LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD =
+{
+    "EXT_PWR_DOWN",
+#if RU_INCLUDE_DESC
+    "",
+    "When any of bits is set, corresponding EGPHY AFE is powered down. "
+    "When 4'b1111 and force_dll_en=0, quad EGPHY DLL is also powered down. "
+    "Requires SW reset to bring EGPHY back from power down.",
+#endif
+    LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD =
+{
+    "IDDQ_BIAS",
+#if RU_INCLUDE_DESC
+    "",
+    "Power down BIAS. When 1'b1. the internal bias is put into iddq mode. "
+    "The energy_det output is not valid when this input is set. "
+    "Requires HW reset(see bit 8 of this register) to bring EGPHY back from power down.",
+#endif
+    LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD =
+{
+    "GPHY_TEST_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "EGPHY test status. When 1'b1 indicates that EGPHY is in test mode.",
+#endif
+    LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD =
+{
+    "RECOVERED_CLK_LOCK",
+#if RU_INCLUDE_DESC
+    "",
+    "When 1'b1 indicates that recovered clock is locked.",
+#endif
+    LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD =
+{
+    "PLL_LOCK",
+#if RU_INCLUDE_DESC
+    "",
+    "When 1'b1 indicates that Quad EGPHY DLL is locked.",
+#endif
+    LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD =
+{
+    "ENERGY_DET_APD",
+#if RU_INCLUDE_DESC
+    "",
+    "Filtered Energy Detect in Auto-Power Down mode.",
+#endif
+    LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD =
+{
+    "ENERGY_DET_MASKED",
+#if RU_INCLUDE_DESC
+    "",
+    "Filtered Energy Detect.",
+#endif
+    LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD_MASK,
+    0,
+    LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD_WIDTH,
+    LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD =
+{
+    "LED_ON_TIME",
+#if RU_INCLUDE_DESC
+    "",
+    "Led ON time. Expressed in 50us units.",
+#endif
+    LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_MASK,
+    0,
+    LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_WIDTH,
+    LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD =
+{
+    "LED_OFF_TIME",
+#if RU_INCLUDE_DESC
+    "",
+    "Led OFF time. Expressed in 50us  units.",
+#endif
+    LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_MASK,
+    0,
+    LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_WIDTH,
+    LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LED_SERIAL_CNTRL_SMODE
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD =
+{
+    "SMODE",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates number of LED signals per port that are shifted out:\n"
+    "11 : 4 LEDs per port mode (SPDLNK_LED[2:0] and ACT_LED).\n"
+    "10 : 3 LEDs per port mode (SPDLNK_LED[2:0]).\n"
+    "01 : 3 LEDs per port mode (SPDLNK_LED[1:0] and ACT_LED).\n"
+    "00 : 2 LEDs per port mode (SPDLNK_LED[1:0])",
+#endif
+    LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD_MASK,
+    0,
+    LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD_WIDTH,
+    LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD =
+{
+    "SLED_CLK_FREQUENCY",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates SLED_CLK frequency.\n"
+    "0 : SLED_CLK is 6.25Mhz.\n"
+    "1 : SLED_CLK is 3.125Mhz.",
+#endif
+    LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD_MASK,
+    0,
+    LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD_WIDTH,
+    LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD =
+{
+    "SLED_CLK_POL",
+#if RU_INCLUDE_DESC
+    "",
+    "When this bit is 1'b1 serial LED clock(SCLK) polarity is inveretd. "
+    "Used with shift registers that trigger on the falling edge.",
+#endif
+    LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD_MASK,
+    0,
+    LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD_WIDTH,
+    LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD =
+{
+    "REFRESH_PERIOD",
+#if RU_INCLUDE_DESC
+    "",
+    "Serial LED refresh period. "
+    "Expressed in 5ms units. Value of 0 means 32x5ms period.",
+#endif
+    LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD_MASK,
+    0,
+    LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD_WIDTH,
+    LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD =
+{
+    "PORT_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When the corresponding bit is set, port LEDs are shifted out. "
+    "When all bits are cleared, serial LED interface is disabled.",
+#endif
+    LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD_MASK,
+    0,
+    LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD_WIDTH,
+    LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+/******************************************************************************
+ * Register: LPORT_CTRL_LPORT_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_CTRL_LPORT_CNTRL_FIELDS[] =
+{
+    &LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD,
+    &LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD,
+    &LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD,
+    &LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD,
+    &LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD,
+    &LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD,
+    &LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD,
+    &LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD,
+    &LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD,
+    &LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD,
+    &LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD,
+    &LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_CTRL_LPORT_CNTRL_REG = 
+{
+    "LPORT_CNTRL",
+#if RU_INCLUDE_DESC
+    "LPORT Control Register",
+    "",
+#endif
+    LPORT_CTRL_LPORT_CNTRL_REG_OFFSET,
+    0,
+    0,
+    205,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    12,
+    LPORT_CTRL_LPORT_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_CTRL_LPORT_REVISION
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_CTRL_LPORT_REVISION_FIELDS[] =
+{
+    &LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD,
+    &LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_CTRL_LPORT_REVISION_REG = 
+{
+    "LPORT_REVISION",
+#if RU_INCLUDE_DESC
+    "LPORT Revision Control Register",
+    "",
+#endif
+    LPORT_CTRL_LPORT_REVISION_REG_OFFSET,
+    0,
+    0,
+    206,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_CTRL_LPORT_REVISION_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_CTRL_QEGPHY_REVISION
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_CTRL_QEGPHY_REVISION_FIELDS[] =
+{
+    &LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD,
+    &LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_CTRL_QEGPHY_REVISION_REG = 
+{
+    "QEGPHY_REVISION",
+#if RU_INCLUDE_DESC
+    "QEGPHY Revision Control Register",
+    "",
+#endif
+    LPORT_CTRL_QEGPHY_REVISION_REG_OFFSET,
+    0,
+    0,
+    207,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_CTRL_QEGPHY_REVISION_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_CTRL_QEGPHY_TEST_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_CTRL_QEGPHY_TEST_CNTRL_FIELDS[] =
+{
+    &LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD,
+    &LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD,
+    &LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD,
+    &LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD,
+    &LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_REG = 
+{
+    "QEGPHY_TEST_CNTRL",
+#if RU_INCLUDE_DESC
+    "Quad GPHY Test Control Register",
+    "",
+#endif
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_REG_OFFSET,
+    0,
+    0,
+    208,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_CTRL_QEGPHY_TEST_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_CTRL_QEGPHY_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_CTRL_QEGPHY_CNTRL_FIELDS[] =
+{
+    &LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD,
+    &LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD,
+    &LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD,
+    &LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD,
+    &LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD,
+    &LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD,
+    &LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD,
+    &LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD,
+    &LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_CTRL_QEGPHY_CNTRL_REG = 
+{
+    "QEGPHY_CNTRL",
+#if RU_INCLUDE_DESC
+    "Quad GPHY Control Register",
+    "",
+#endif
+    LPORT_CTRL_QEGPHY_CNTRL_REG_OFFSET,
+    0,
+    0,
+    209,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    LPORT_CTRL_QEGPHY_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_CTRL_QEGPHY_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_CTRL_QEGPHY_STATUS_FIELDS[] =
+{
+    &LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD,
+    &LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD,
+    &LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD,
+    &LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD,
+    &LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD,
+    &LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_CTRL_QEGPHY_STATUS_REG = 
+{
+    "QEGPHY_STATUS",
+#if RU_INCLUDE_DESC
+    "Quad GPHY Status Register",
+    "",
+#endif
+    LPORT_CTRL_QEGPHY_STATUS_REG_OFFSET,
+    0,
+    0,
+    210,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_CTRL_QEGPHY_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_CTRL_LED_BLINK_RATE_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_CTRL_LED_BLINK_RATE_CNTRL_FIELDS[] =
+{
+    &LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD,
+    &LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_CTRL_LED_BLINK_RATE_CNTRL_REG = 
+{
+    "LED_BLINK_RATE_CNTRL",
+#if RU_INCLUDE_DESC
+    "Aggregate LED Blink Rate Control Register",
+    "",
+#endif
+    LPORT_CTRL_LED_BLINK_RATE_CNTRL_REG_OFFSET,
+    0,
+    0,
+    211,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_CTRL_LED_BLINK_RATE_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_CTRL_LED_SERIAL_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_CTRL_LED_SERIAL_CNTRL_FIELDS[] =
+{
+    &LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD,
+    &LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD,
+    &LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD,
+    &LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD,
+    &LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD,
+    &LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_CTRL_LED_SERIAL_CNTRL_REG = 
+{
+    "LED_SERIAL_CNTRL",
+#if RU_INCLUDE_DESC
+    "LED Serial Control Register",
+    "",
+#endif
+    LPORT_CTRL_LED_SERIAL_CNTRL_REG_OFFSET,
+    0,
+    0,
+    212,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_CTRL_LED_SERIAL_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Block: LPORT_CTRL
+ ******************************************************************************/
+static const ru_reg_rec *LPORT_CTRL_REGS[] =
+{
+    &LPORT_CTRL_LPORT_CNTRL_REG,
+    &LPORT_CTRL_LPORT_REVISION_REG,
+    &LPORT_CTRL_QEGPHY_REVISION_REG,
+    &LPORT_CTRL_QEGPHY_TEST_CNTRL_REG,
+    &LPORT_CTRL_QEGPHY_CNTRL_REG,
+    &LPORT_CTRL_QEGPHY_STATUS_REG,
+    &LPORT_CTRL_LED_BLINK_RATE_CNTRL_REG,
+    &LPORT_CTRL_LED_SERIAL_CNTRL_REG,
+};
+
+unsigned long LPORT_CTRL_ADDRS[] =
+{
+    0x8013c000,
+};
+
+const ru_block_rec LPORT_CTRL_BLOCK = 
+{
+    "LPORT_CTRL",
+    LPORT_CTRL_ADDRS,
+    1,
+    8,
+    LPORT_CTRL_REGS
+};
+
+/* End of file BCM6858_A0LPORT_CTRL.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_INTR_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_INTR_AG.c
new file mode 100644
index 0000000000..1196f7aaaa
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_INTR_AG.c
@@ -0,0 +1,5849 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+#if RU_INCLUDE_FIELD_DB
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_STATUS_XLMAC_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD =
+{
+    "XLMAC_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
+    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
+    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD =
+{
+    "MDIO_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO read error. No response to MDIO read.",
+#endif
+    LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD =
+{
+    "MDIO_DONE_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO transaction completed.",
+#endif
+    LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD =
+{
+    "MIB_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mib_reg_err_intr[1:0].\n"
+    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
+#endif
+    LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD =
+{
+    "MAC_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mac_reg_err_int[1:0].\n"
+    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
+#endif
+    LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD =
+{
+    "UBUS_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "UBUS transaction error.",
+#endif
+    LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_SET_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_SET_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_SET_XLMAC_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD =
+{
+    "XLMAC_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
+    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
+    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD =
+{
+    "MDIO_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO read error. No response to MDIO read.",
+#endif
+    LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD =
+{
+    "MDIO_DONE_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO transaction completed.",
+#endif
+    LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD =
+{
+    "MIB_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mib_reg_err_intr[1:0].\n"
+    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
+#endif
+    LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD =
+{
+    "MAC_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mac_reg_err_int[1:0].\n"
+    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
+#endif
+    LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD =
+{
+    "UBUS_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "UBUS transaction error.",
+#endif
+    LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_CLEAR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD =
+{
+    "XLMAC_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
+    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
+    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD =
+{
+    "MDIO_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO read error. No response to MDIO read.",
+#endif
+    LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD =
+{
+    "MDIO_DONE_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO transaction completed.",
+#endif
+    LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD =
+{
+    "MIB_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mib_reg_err_intr[1:0].\n"
+    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
+#endif
+    LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD =
+{
+    "MAC_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mac_reg_err_int[1:0].\n"
+    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
+#endif
+    LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD =
+{
+    "UBUS_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "UBUS transaction error.",
+#endif
+    LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD =
+{
+    "MDIO_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD =
+{
+    "MDIO_DONE_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD =
+{
+    "MIB_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD =
+{
+    "MAC_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD =
+{
+    "UBUS_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD =
+{
+    "MDIO_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD =
+{
+    "MDIO_DONE_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD =
+{
+    "MIB_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD =
+{
+    "MAC_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD =
+{
+    "UBUS_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD =
+{
+    "MDIO_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD =
+{
+    "MDIO_DONE_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD =
+{
+    "MIB_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD =
+{
+    "MAC_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD =
+{
+    "UBUS_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_STATUS_XLMAC_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD =
+{
+    "XLMAC_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
+    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
+    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD =
+{
+    "MDIO_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO read error. No response to MDIO read.",
+#endif
+    LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD =
+{
+    "MDIO_DONE_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO transaction completed.",
+#endif
+    LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD =
+{
+    "MIB_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mib_reg_err_intr[1:0].\n"
+    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
+#endif
+    LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD =
+{
+    "MAC_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mac_reg_err_int[1:0].\n"
+    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
+#endif
+    LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD =
+{
+    "UBUS_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "UBUS transaction error.",
+#endif
+    LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_SET_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_SET_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_SET_XLMAC_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD =
+{
+    "XLMAC_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
+    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
+    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD =
+{
+    "MDIO_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO read error. No response to MDIO read.",
+#endif
+    LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD =
+{
+    "MDIO_DONE_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO transaction completed.",
+#endif
+    LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD =
+{
+    "MIB_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mib_reg_err_intr[1:0].\n"
+    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
+#endif
+    LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD =
+{
+    "MAC_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mac_reg_err_int[1:0].\n"
+    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
+#endif
+    LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD =
+{
+    "UBUS_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "UBUS transaction error.",
+#endif
+    LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_CLEAR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD =
+{
+    "XLMAC_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Interrupt generated by XLMAC signaling various events as described in XLMAC_INTR_STATUS.\n"
+    "Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "tx_timesync_fifo_entry_valid_intr[7:0].\n"
+    "PTP timestamp available for read. Bits [7:4] correspond to XLMAC1 and bits [3:0] to XLMAC0.",
+#endif
+    LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects loss of energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high energy detect interrupt signal (signals presence of the link partner) asserted "
+    "when any of PHYs within QGPHY detects the energy. Based on QGPHY energy_det_apd.",
+#endif
+    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD =
+{
+    "MDIO_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO read error. No response to MDIO read.",
+#endif
+    LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD =
+{
+    "MDIO_DONE_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO transaction completed.",
+#endif
+    LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD =
+{
+    "MIB_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mib_reg_err_intr[1:0].\n"
+    "MIB register transaction error. Bit 1 corresponds to MIB1 and bit 0 to MIB0.",
+#endif
+    LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD =
+{
+    "MAC_REG_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "mac_reg_err_int[1:0].\n"
+    "XLMAC register transaction error. Bit 1 corresponds to XLMAC1 and bit 0 to XLMAC0.",
+#endif
+    LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD =
+{
+    "UBUS_ERR_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "UBUS transaction error.",
+#endif
+    LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD =
+{
+    "MDIO_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD =
+{
+    "MDIO_DONE_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD =
+{
+    "MIB_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD =
+{
+    "MAC_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD =
+{
+    "UBUS_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD =
+{
+    "MDIO_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD =
+{
+    "MDIO_DONE_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD =
+{
+    "MIB_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD =
+{
+    "MAC_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD =
+{
+    "UBUS_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac rx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac tx cdc single bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD =
+{
+    "MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  mac tx cdc double bit error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD =
+{
+    "TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for  tx timesync fifo entry valid interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_OFF_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD =
+{
+    "QGPHY_ENERGY_ON_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for qgphy energy on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD =
+{
+    "MDIO_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD =
+{
+    "MDIO_DONE_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mdio done interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD =
+{
+    "MIB_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mib register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD =
+{
+    "MAC_REG_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for mac register error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD =
+{
+    "UBUS_ERR_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for ubus error interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD =
+{
+    "MAB_STATUS_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
+    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
+#endif
+    LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "RX Remote Fault Interrupt for P4 and P0.",
+#endif
+    LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high signal detect interrupt (signals presence of the link partner).\n"
+    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
+    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
+    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
+    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD =
+{
+    "LINK_DOWN_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
+#endif
+    LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD =
+{
+    "LINK_UP_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
+#endif
+    LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_SET_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_SET_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD =
+{
+    "MAB_STATUS_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
+    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
+#endif
+    LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "RX Remote Fault Interrupt for P4 and P0.",
+#endif
+    LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high signal detect interrupt (signals presence of the link partner).\n"
+    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
+    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
+    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
+    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD =
+{
+    "LINK_DOWN_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
+#endif
+    LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_SET_LINK_UP_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD =
+{
+    "LINK_UP_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
+#endif
+    LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_CLEAR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD =
+{
+    "MAB_STATUS_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
+    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
+#endif
+    LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "RX Remote Fault Interrupt for P4 and P0.",
+#endif
+    LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high signal detect interrupt (signals presence of the link partner).\n"
+    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
+    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
+    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
+    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD =
+{
+    "LINK_DOWN_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
+#endif
+    LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD =
+{
+    "LINK_UP_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
+#endif
+    LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD =
+{
+    "LINK_DOWN_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD =
+{
+    "LINK_UP_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_SET_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD =
+{
+    "LINK_DOWN_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD =
+{
+    "LINK_UP_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD =
+{
+    "LINK_DOWN_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD =
+{
+    "LINK_UP_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD =
+{
+    "MAB_STATUS_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
+    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
+#endif
+    LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "RX Remote Fault Interrupt for P4 and P0.",
+#endif
+    LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high signal detect interrupt (signals presence of the link partner).\n"
+    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
+    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
+    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
+    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD =
+{
+    "LINK_DOWN_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
+#endif
+    LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD =
+{
+    "LINK_UP_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
+#endif
+    LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_SET_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_SET_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD =
+{
+    "MAB_STATUS_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
+    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
+#endif
+    LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "RX Remote Fault Interrupt for P4 and P0.",
+#endif
+    LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high signal detect interrupt (signals presence of the link partner).\n"
+    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
+    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
+    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
+    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD =
+{
+    "LINK_DOWN_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
+#endif
+    LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_SET_LINK_UP_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD =
+{
+    "LINK_UP_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
+#endif
+    LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_CLEAR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD =
+{
+    "MAB_STATUS_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Asserted when any of statuses get set in MSBUS Adaptation Block Status Register(s).\n"
+    "Index 1 corresponds to MSBUS Adaptation Block 1 (i.e. XLMAC1) and index 0 to MSBUS Adaptation Block 0 (i.e. XLMAC0).",
+#endif
+    LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "RX Remote Fault Interrupt for P4 and P0.",
+#endif
+    LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Inverted sd_on interrupt. Interrupt to serdes lane mapping is same as for dserdes_sd_on_intr[3:0]. "
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high signal detect interrupt (signals presence of the link partner).\n"
+    "dserdes_sd_on_intr[3] corresponds to MERLIN 1, lane 1.\n"
+    "dserdes_sd_on_intr[2] corresponds to MERLIN 1, lane 0.\n"
+    "dserdes_sd_on_intr[1] corresponds to MERLIN 0, lane 1.\n"
+    "dserdes_sd_on_intr[0] corresponds to MERLIN 0, lane 0.\n"
+    "Based on filtered signal detect.",
+#endif
+    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD =
+{
+    "LINK_DOWN_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link down interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link down event.",
+#endif
+    LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD =
+{
+    "LINK_UP_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "Link up interrupt for P7:P0. Interrupt corresponds to the attached PHY/interface link up event.",
+#endif
+    LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD =
+{
+    "LINK_DOWN_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD =
+{
+    "LINK_UP_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_SET_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD =
+{
+    "LINK_DOWN_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD =
+{
+    "LINK_UP_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD =
+{
+    "RX_REMOTE_FAULT_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for rx remote fault interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD =
+{
+    "DSERDES_SD_OFF_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect off interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD =
+{
+    "DSERDES_SD_ON_INTR",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for dual serdes signal detect on interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD =
+{
+    "LINK_DOWN_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link down interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD =
+{
+    "LINK_UP_INTR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit corresponds to the mask for link up interrupt. See register description above for details of how to use this bit.",
+#endif
+    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_MASK,
+    0,
+    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_WIDTH,
+    LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_CPU_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_CPU_STATUS_FIELDS[] =
+{
+    &LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD,
+    &LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD,
+    &LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
+    &LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD,
+    &LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD,
+    &LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD,
+    &LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD,
+    &LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_CPU_STATUS_REG = 
+{
+    "0_CPU_STATUS",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_0_CPU_STATUS_REG_OFFSET,
+    0,
+    0,
+    271,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    10,
+    LPORT_INTR_0_CPU_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_CPU_SET
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_CPU_SET_FIELDS[] =
+{
+    &LPORT_INTR_0_CPU_SET_RESERVED0_FIELD,
+    &LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD,
+    &LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
+    &LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD,
+    &LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD,
+    &LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD,
+    &LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD,
+    &LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_CPU_SET_REG = 
+{
+    "0_CPU_SET",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_0_CPU_SET_REG_OFFSET,
+    0,
+    0,
+    272,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    10,
+    LPORT_INTR_0_CPU_SET_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_CPU_CLEAR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_CPU_CLEAR_FIELDS[] =
+{
+    &LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD,
+    &LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD,
+    &LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
+    &LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD,
+    &LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD,
+    &LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD,
+    &LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD,
+    &LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_CPU_CLEAR_REG = 
+{
+    "0_CPU_CLEAR",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_0_CPU_CLEAR_REG_OFFSET,
+    0,
+    0,
+    273,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    10,
+    LPORT_INTR_0_CPU_CLEAR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_CPU_MASK_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_CPU_MASK_STATUS_FIELDS[] =
+{
+    &LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_CPU_MASK_STATUS_REG = 
+{
+    "0_CPU_MASK_STATUS",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_0_CPU_MASK_STATUS_REG_OFFSET,
+    0,
+    0,
+    274,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    13,
+    LPORT_INTR_0_CPU_MASK_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_CPU_MASK_SET
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_CPU_MASK_SET_FIELDS[] =
+{
+    &LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_CPU_MASK_SET_REG = 
+{
+    "0_CPU_MASK_SET",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_0_CPU_MASK_SET_REG_OFFSET,
+    0,
+    0,
+    275,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    13,
+    LPORT_INTR_0_CPU_MASK_SET_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_CPU_MASK_CLEAR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_CPU_MASK_CLEAR_FIELDS[] =
+{
+    &LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_CPU_MASK_CLEAR_REG = 
+{
+    "0_CPU_MASK_CLEAR",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_0_CPU_MASK_CLEAR_REG_OFFSET,
+    0,
+    0,
+    276,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    13,
+    LPORT_INTR_0_CPU_MASK_CLEAR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_PCI_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_PCI_STATUS_FIELDS[] =
+{
+    &LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD,
+    &LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD,
+    &LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
+    &LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD,
+    &LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD,
+    &LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD,
+    &LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD,
+    &LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_PCI_STATUS_REG = 
+{
+    "0_PCI_STATUS",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_0_PCI_STATUS_REG_OFFSET,
+    0,
+    0,
+    277,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    10,
+    LPORT_INTR_0_PCI_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_PCI_SET
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_PCI_SET_FIELDS[] =
+{
+    &LPORT_INTR_0_PCI_SET_RESERVED0_FIELD,
+    &LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD,
+    &LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
+    &LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD,
+    &LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD,
+    &LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD,
+    &LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD,
+    &LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_PCI_SET_REG = 
+{
+    "0_PCI_SET",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_0_PCI_SET_REG_OFFSET,
+    0,
+    0,
+    278,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    10,
+    LPORT_INTR_0_PCI_SET_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_PCI_CLEAR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_PCI_CLEAR_FIELDS[] =
+{
+    &LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD,
+    &LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD,
+    &LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD,
+    &LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD,
+    &LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD,
+    &LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD,
+    &LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD,
+    &LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD,
+    &LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_PCI_CLEAR_REG = 
+{
+    "0_PCI_CLEAR",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_0_PCI_CLEAR_REG_OFFSET,
+    0,
+    0,
+    279,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    10,
+    LPORT_INTR_0_PCI_CLEAR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_PCI_MASK_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_PCI_MASK_STATUS_FIELDS[] =
+{
+    &LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_PCI_MASK_STATUS_REG = 
+{
+    "0_PCI_MASK_STATUS",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_0_PCI_MASK_STATUS_REG_OFFSET,
+    0,
+    0,
+    280,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    13,
+    LPORT_INTR_0_PCI_MASK_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_PCI_MASK_SET
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_PCI_MASK_SET_FIELDS[] =
+{
+    &LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_PCI_MASK_SET_REG = 
+{
+    "0_PCI_MASK_SET",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_0_PCI_MASK_SET_REG_OFFSET,
+    0,
+    0,
+    281,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    13,
+    LPORT_INTR_0_PCI_MASK_SET_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_0_PCI_MASK_CLEAR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_0_PCI_MASK_CLEAR_FIELDS[] =
+{
+    &LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_0_PCI_MASK_CLEAR_REG = 
+{
+    "0_PCI_MASK_CLEAR",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_0_PCI_MASK_CLEAR_REG_OFFSET,
+    0,
+    0,
+    282,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    13,
+    LPORT_INTR_0_PCI_MASK_CLEAR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_CPU_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_CPU_STATUS_FIELDS[] =
+{
+    &LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD,
+    &LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD,
+    &LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD,
+    &LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD,
+    &LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_CPU_STATUS_REG = 
+{
+    "1_CPU_STATUS",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_1_CPU_STATUS_REG_OFFSET,
+    0,
+    0,
+    283,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_INTR_1_CPU_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_CPU_SET
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_CPU_SET_FIELDS[] =
+{
+    &LPORT_INTR_1_CPU_SET_RESERVED0_FIELD,
+    &LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD,
+    &LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD,
+    &LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD,
+    &LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_CPU_SET_REG = 
+{
+    "1_CPU_SET",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_1_CPU_SET_REG_OFFSET,
+    0,
+    0,
+    284,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_INTR_1_CPU_SET_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_CPU_CLEAR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_CPU_CLEAR_FIELDS[] =
+{
+    &LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD,
+    &LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD,
+    &LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD,
+    &LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD,
+    &LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_CPU_CLEAR_REG = 
+{
+    "1_CPU_CLEAR",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_1_CPU_CLEAR_REG_OFFSET,
+    0,
+    0,
+    285,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_INTR_1_CPU_CLEAR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_CPU_MASK_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_CPU_MASK_STATUS_FIELDS[] =
+{
+    &LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD,
+    &LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD,
+    &LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD,
+    &LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_CPU_MASK_STATUS_REG = 
+{
+    "1_CPU_MASK_STATUS",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_1_CPU_MASK_STATUS_REG_OFFSET,
+    0,
+    0,
+    286,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_INTR_1_CPU_MASK_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_CPU_MASK_SET
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_CPU_MASK_SET_FIELDS[] =
+{
+    &LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD,
+    &LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD,
+    &LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD,
+    &LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_CPU_MASK_SET_REG = 
+{
+    "1_CPU_MASK_SET",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_1_CPU_MASK_SET_REG_OFFSET,
+    0,
+    0,
+    287,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_INTR_1_CPU_MASK_SET_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_CPU_MASK_CLEAR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_CPU_MASK_CLEAR_FIELDS[] =
+{
+    &LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD,
+    &LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD,
+    &LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD,
+    &LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_CPU_MASK_CLEAR_REG = 
+{
+    "1_CPU_MASK_CLEAR",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_1_CPU_MASK_CLEAR_REG_OFFSET,
+    0,
+    0,
+    288,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_INTR_1_CPU_MASK_CLEAR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_PCI_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_PCI_STATUS_FIELDS[] =
+{
+    &LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD,
+    &LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD,
+    &LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD,
+    &LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD,
+    &LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_PCI_STATUS_REG = 
+{
+    "1_PCI_STATUS",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_1_PCI_STATUS_REG_OFFSET,
+    0,
+    0,
+    289,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_INTR_1_PCI_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_PCI_SET
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_PCI_SET_FIELDS[] =
+{
+    &LPORT_INTR_1_PCI_SET_RESERVED0_FIELD,
+    &LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD,
+    &LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD,
+    &LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD,
+    &LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_PCI_SET_REG = 
+{
+    "1_PCI_SET",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_1_PCI_SET_REG_OFFSET,
+    0,
+    0,
+    290,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_INTR_1_PCI_SET_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_PCI_CLEAR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_PCI_CLEAR_FIELDS[] =
+{
+    &LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD,
+    &LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD,
+    &LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD,
+    &LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD,
+    &LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_PCI_CLEAR_REG = 
+{
+    "1_PCI_CLEAR",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Clear Register",
+    "This read-only register shows the current status of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  The assertion of any of these interrupts will cause an interrupt to the CPU "
+    "processor if the interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change."
+    "This read-only register shows the current status of the interrupts for the PCI bus.  There is one bit per "
+    "interrupt source.  The assertion of any of these interrupts will cause an interrupt to the PCI bus if the"
+    "interrupt's mask bit is zero."
+    "\nFor each bit: 1 = asserted. 0 = not asserted."
+    "This write-only register is used to set interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the interrupt corresponding to that bit.  Writing a 0 has "
+    "no effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros "
+    "written to them are not affected."
+    "\nFor each bit: 1 = set the corresponding interrupt bit. 0 = no change."
+    "This write-only register is used to clear interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the interrupt corresponding to that bit.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = clear the corresponding interrupt bit. 0 = no change.",
+#endif
+    LPORT_INTR_1_PCI_CLEAR_REG_OFFSET,
+    0,
+    0,
+    291,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_INTR_1_PCI_CLEAR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_PCI_MASK_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_PCI_MASK_STATUS_FIELDS[] =
+{
+    &LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD,
+    &LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD,
+    &LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD,
+    &LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_PCI_MASK_STATUS_REG = 
+{
+    "1_PCI_MASK_STATUS",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_1_PCI_MASK_STATUS_REG_OFFSET,
+    0,
+    0,
+    292,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_INTR_1_PCI_MASK_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_PCI_MASK_SET
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_PCI_MASK_SET_FIELDS[] =
+{
+    &LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD,
+    &LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD,
+    &LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD,
+    &LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_PCI_MASK_SET_REG = 
+{
+    "1_PCI_MASK_SET",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_1_PCI_MASK_SET_REG_OFFSET,
+    0,
+    0,
+    293,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_INTR_1_PCI_MASK_SET_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_INTR_1_PCI_MASK_CLEAR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_INTR_1_PCI_MASK_CLEAR_FIELDS[] =
+{
+    &LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD,
+    &LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD,
+    &LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD,
+    &LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD,
+    &LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD,
+    &LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_INTR_1_PCI_MASK_CLEAR_REG = 
+{
+    "1_PCI_MASK_CLEAR",
+#if RU_INCLUDE_DESC
+    "PCI interrupt Mask Clear Register",
+    "This read-only register shows the current masking of the interrupts for the CPU processor.  There is one "
+    "bit per interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to "
+    "that bit is currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the CPU processor.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change."
+    "This read-only register shows the current masking of the interrupts for the PCI bus.  There is one bit per"
+    "interrupt source.  A value of 1 in a bit position indicates that the interrupt corresponding to that bit is"
+    "currently masked.  Masking does not prevent the interrupt from appearing in the status register."
+    "\nFor each bit: 1 = masked. 0 = not masked."
+    "This write-only register is used to disable interrupts for the PCI bus.  There is one bit per interrupt source."
+    "Writing a 1 to a bit in this register will set the mask bit for the corresponding interrupt.  Writing a 0 has no"
+    "effect.  Note that it is not necessary to read-modify-write this register because bits that have zeros written "
+    "to them are not affected."
+    "\nFor each bit: 1 = disable the corresponding interrupt. 0 = no change."
+    "This write-only register is used to enable interrupts for the PCI bus.  There is one bit per interrupt "
+    "source.  Writing a 1 to a bit in this register will clear the mask bit for the corresponding interrupt.  Writing "
+    "a 0 has no effect.  Note that it is not necessary to read-modify-write this register because bits that have "
+    "zeros written to them are not affected."
+    "\nFor each bit: 1 = enable the corresponding interrupt. 0 = no change.",
+#endif
+    LPORT_INTR_1_PCI_MASK_CLEAR_REG_OFFSET,
+    0,
+    0,
+    294,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_INTR_1_PCI_MASK_CLEAR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Block: LPORT_INTR
+ ******************************************************************************/
+static const ru_reg_rec *LPORT_INTR_REGS[] =
+{
+    &LPORT_INTR_0_CPU_STATUS_REG,
+    &LPORT_INTR_0_CPU_SET_REG,
+    &LPORT_INTR_0_CPU_CLEAR_REG,
+    &LPORT_INTR_0_CPU_MASK_STATUS_REG,
+    &LPORT_INTR_0_CPU_MASK_SET_REG,
+    &LPORT_INTR_0_CPU_MASK_CLEAR_REG,
+    &LPORT_INTR_0_PCI_STATUS_REG,
+    &LPORT_INTR_0_PCI_SET_REG,
+    &LPORT_INTR_0_PCI_CLEAR_REG,
+    &LPORT_INTR_0_PCI_MASK_STATUS_REG,
+    &LPORT_INTR_0_PCI_MASK_SET_REG,
+    &LPORT_INTR_0_PCI_MASK_CLEAR_REG,
+    &LPORT_INTR_1_CPU_STATUS_REG,
+    &LPORT_INTR_1_CPU_SET_REG,
+    &LPORT_INTR_1_CPU_CLEAR_REG,
+    &LPORT_INTR_1_CPU_MASK_STATUS_REG,
+    &LPORT_INTR_1_CPU_MASK_SET_REG,
+    &LPORT_INTR_1_CPU_MASK_CLEAR_REG,
+    &LPORT_INTR_1_PCI_STATUS_REG,
+    &LPORT_INTR_1_PCI_SET_REG,
+    &LPORT_INTR_1_PCI_CLEAR_REG,
+    &LPORT_INTR_1_PCI_MASK_STATUS_REG,
+    &LPORT_INTR_1_PCI_MASK_SET_REG,
+    &LPORT_INTR_1_PCI_MASK_CLEAR_REG,
+};
+
+unsigned long LPORT_INTR_ADDRS[] =
+{
+    0x8013d500,
+};
+
+const ru_block_rec LPORT_INTR_BLOCK = 
+{
+    "LPORT_INTR",
+    LPORT_INTR_ADDRS,
+    1,
+    24,
+    LPORT_INTR_REGS
+};
+
+/* End of file BCM6858_A0LPORT_INTR.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_LED_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_LED_AG.c
new file mode 100644
index 0000000000..3a7068c4a6
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_LED_AG.c
@@ -0,0 +1,1022 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+#if RU_INCLUDE_FIELD_DB
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_LED_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_LED_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_LNK_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD =
+{
+    "LNK_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When this bit is set MAC/PHY provided link indication is overridden using lnk_status_ovrd.",
+#endif
+    LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD_WIDTH,
+    LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_SPD_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD =
+{
+    "SPD_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When this bit is set MAC/PHY provided speed indications are overridden using led_spd_ovrd[2:0].",
+#endif
+    LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD_WIDTH,
+    LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_LNK_STATUS_OVRD
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD =
+{
+    "LNK_STATUS_OVRD",
+#if RU_INCLUDE_DESC
+    "",
+    "Link status override. Used only for LED.",
+#endif
+    LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD_WIDTH,
+    LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_LED_SPD_OVRD
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD =
+{
+    "LED_SPD_OVRD",
+#if RU_INCLUDE_DESC
+    "",
+    "LED speed override. Default encoding is:\n"
+    "000 : 10Mb/s.\n"
+    "001 : 100Mb/s.\n"
+    "010 : 1000Mb/s.\n"
+    "011 : 2.5Gb/s.\n"
+    "100 : 10Gb/s or higher.\n"
+    "101 : Custom speed 1.\n"
+    "110 : Custom speed 2.\n"
+    "111 : no-link.\n"
+    "Using this register LED speeds can be encoded in any way that suits customer application.",
+#endif
+    LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD_WIDTH,
+    LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_ACT_LED_POL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD =
+{
+    "ACT_LED_POL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "When set to 1'b1 inverts polarity of the activity signal that is used for ACT_LED.",
+#endif
+    LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD_WIDTH,
+    LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD =
+{
+    "SPDLNK_LED2_ACT_POL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "When set to 1'b1 inverts polarity of the activity signal that is used for SPDLNK_LED[2]. "
+    "Applicable only when the activity drives this LED.",
+#endif
+    LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_WIDTH,
+    LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD =
+{
+    "SPDLNK_LED1_ACT_POL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "When set to 1'b1 inverts polarity of the activity signal that is used for SPDLNK_LED[1]. "
+    "Applicable only when the activity drives this LED.",
+#endif
+    LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_WIDTH,
+    LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD =
+{
+    "SPDLNK_LED0_ACT_POL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "When set to 1'b1 inverts polarity of the activity signal that is used for SPDLNK_LED[0]. "
+    "Applicable only when the activity drives this LED.",
+#endif
+    LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_WIDTH,
+    LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_ACT_LED_ACT_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD =
+{
+    "ACT_LED_ACT_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "Selects source of activity for ACT_LED. For encoding see description for spdlnk_led0_act_sel.",
+#endif
+    LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_WIDTH,
+    LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD =
+{
+    "SPDLNK_LED2_ACT_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "Selects source of activity for SPDLNK_LED[2]. For encoding see description for spdlnk_led0_act_sel.",
+#endif
+    LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_WIDTH,
+    LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD =
+{
+    "SPDLNK_LED1_ACT_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "Selects source of activity for SPDLNK_LED[1]. For encoding see description for spdlnk_led0_act_sel.",
+#endif
+    LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_WIDTH,
+    LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD =
+{
+    "SPDLNK_LED0_ACT_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "Selects source of the activity for SPDLNK_LED[0]:\n"
+    "0 : LED is 0 when link is up and blinks when there is activity.\n"
+    "1 : LED is 1 and blinks when there is activity.",
+#endif
+    LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_WIDTH,
+    LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_TX_ACT_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_TX_ACT_EN_FIELD =
+{
+    "TX_ACT_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "Enables TX_SOP event to contribute to the activity.",
+#endif
+    LPORT_LED_CNTRL_TX_ACT_EN_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_TX_ACT_EN_FIELD_WIDTH,
+    LPORT_LED_CNTRL_TX_ACT_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_CNTRL_RX_ACT_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_CNTRL_RX_ACT_EN_FIELD =
+{
+    "RX_ACT_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "Enables RX_SOP event to contribute to the activity.",
+#endif
+    LPORT_LED_CNTRL_RX_ACT_EN_FIELD_MASK,
+    0,
+    LPORT_LED_CNTRL_RX_ACT_EN_FIELD_WIDTH,
+    LPORT_LED_CNTRL_RX_ACT_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD =
+{
+    "RSVD_SEL_SPD_ENCODE_2",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved SPDLNK_LED_SEL[2:0] encoding select.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD =
+{
+    "RSVD_SEL_SPD_ENCODE_1",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved SPDLNK_LED_SEL[2:0] encoding select.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD =
+{
+    "SEL_10G_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED_SEL[2:0] encoding for 10Gb/s and higher link speed.\n"
+    "When SPDLNK_LED_SEL[x] = 1'''b0, SPDLNK_LED[x] is driven by bits [17:0] of Link and Speed Encoding Register.\n"
+    "When SPDLNK_LED_SEL[x] = 1'''b1, SPDLNK_LED[x] is driven by the activity.\n",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD =
+{
+    "SEL_2500M_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED_SEL[2:0] encoding for 2500Mb/s link speed.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD =
+{
+    "SEL_1000M_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED_SEL[2:0] encoding for 1000Mb/s link speed.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD =
+{
+    "SEL_100M_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED_SEL[2:0] encoding for 100Mb/s link speed.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD =
+{
+    "SEL_10M_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED_SEL[2:0] encoding for 10Mb/s link speed.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD =
+{
+    "SEL_NO_LINK_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED_SEL[2:0] encoding for the no-link state.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD =
+{
+    "RSVD_SPD_ENCODE_2",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved SPDLNK_LED_SEL[2:0] encoding.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD =
+{
+    "RSVD_SPD_ENCODE_1",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved SPDLNK_LED_SEL[2:0] encoding.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD =
+{
+    "M10G_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED[2:0] encoding for 10Gb/s and higherlink speed.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD =
+{
+    "M2500_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED[2:0] encoding for 2.5Gb/s link speed.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD =
+{
+    "M1000_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED[2:0] encoding for 1Gb/s link speed.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD =
+{
+    "M100_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED[2:0] encoding for 100Mb/s link speed.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD =
+{
+    "M10_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED[2:0] encoding for 10Mb/s link speed.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD =
+{
+    "NO_LINK_ENCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "SPDLNK_LED[2:0] encoding for the no-link state.",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_MASK,
+    0,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_WIDTH,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD =
+{
+    "LNK_POL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "When set to 1'b1 inverts polarity of the link signal that is used for aggregate LNK_LED.",
+#endif
+    LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_MASK,
+    0,
+    LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_WIDTH,
+    LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD =
+{
+    "ACT_POL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "When set to 1'b1 inverts polarity of the activity signal that is used for aggregate ACT_LED.",
+#endif
+    LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_MASK,
+    0,
+    LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_WIDTH,
+    LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD =
+{
+    "ACT_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "Selects behavior for aggregate ACT_LED. Encoded as:"
+    "0 : LED is 0 when aggregate link is up and blinks when there is activity. "
+    "    LED is 1 when aggregate link is down.\n"
+    "1 : LED is 1 and blinks when there is activity, regardless of the aggregate link status.\n",
+#endif
+    LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_MASK,
+    0,
+    LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_WIDTH,
+    LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD =
+{
+    "PORT_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When the corresponding bit is set, port LEDs are included in aggregate LED signals. "
+    "When all bits are cleared, aggregate LED interface is disabled.",
+#endif
+    LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_MASK,
+    0,
+    LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_WIDTH,
+    LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD =
+{
+    "LED_ON_TIME",
+#if RU_INCLUDE_DESC
+    "",
+    "Led ON time. Expressed in 50us units.",
+#endif
+    LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_MASK,
+    0,
+    LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_WIDTH,
+    LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME
+ ******************************************************************************/
+const ru_field_rec LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD =
+{
+    "LED_OFF_TIME",
+#if RU_INCLUDE_DESC
+    "",
+    "Led OFF time. Expressed in 50us  units.",
+#endif
+    LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_MASK,
+    0,
+    LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_WIDTH,
+    LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+/******************************************************************************
+ * Register: LPORT_LED_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_LED_CNTRL_FIELDS[] =
+{
+    &LPORT_LED_CNTRL_RESERVED0_FIELD,
+    &LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD,
+    &LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD,
+    &LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD,
+    &LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD,
+    &LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD,
+    &LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD,
+    &LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD,
+    &LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD,
+    &LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD,
+    &LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD,
+    &LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD,
+    &LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD,
+    &LPORT_LED_CNTRL_TX_ACT_EN_FIELD,
+    &LPORT_LED_CNTRL_RX_ACT_EN_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_LED_CNTRL_REG = 
+{
+    "CNTRL",
+#if RU_INCLUDE_DESC
+    "LED 7 Control Register",
+    "",
+#endif
+    LPORT_LED_CNTRL_REG_OFFSET,
+    0,
+    0,
+    200,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    15,
+    LPORT_LED_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_LED_LINK_AND_SPEED_ENCODING_SEL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_FIELDS[] =
+{
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_REG = 
+{
+    "LINK_AND_SPEED_ENCODING_SEL",
+#if RU_INCLUDE_DESC
+    "LED 7 Link And Speed Encoding Selection Register",
+    "",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_REG_OFFSET,
+    0,
+    0,
+    201,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_LED_LINK_AND_SPEED_ENCODING
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_LED_LINK_AND_SPEED_ENCODING_FIELDS[] =
+{
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_LED_LINK_AND_SPEED_ENCODING_REG = 
+{
+    "LINK_AND_SPEED_ENCODING",
+#if RU_INCLUDE_DESC
+    "LED 7 Link And Speed Encoding Register",
+    "",
+#endif
+    LPORT_LED_LINK_AND_SPEED_ENCODING_REG_OFFSET,
+    0,
+    0,
+    202,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    LPORT_LED_LINK_AND_SPEED_ENCODING_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_LED_AGGREGATE_LED_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_LED_AGGREGATE_LED_CNTRL_FIELDS[] =
+{
+    &LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD,
+    &LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD,
+    &LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD,
+    &LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD,
+    &LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_LED_AGGREGATE_LED_CNTRL_REG = 
+{
+    "AGGREGATE_LED_CNTRL",
+#if RU_INCLUDE_DESC
+    "Aggregate LED Control Register",
+    "",
+#endif
+    LPORT_LED_AGGREGATE_LED_CNTRL_REG_OFFSET,
+    0,
+    0,
+    203,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_LED_AGGREGATE_LED_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_FIELDS[] =
+{
+    &LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD,
+    &LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_REG = 
+{
+    "AGGREGATE_LED_BLINK_RATE_CNTRL",
+#if RU_INCLUDE_DESC
+    "Aggregate LED Blink Rate Control Register",
+    "",
+#endif
+    LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_OFFSET,
+    0,
+    0,
+    204,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Block: LPORT_LED
+ ******************************************************************************/
+static const ru_reg_rec *LPORT_LED_REGS[] =
+{
+    &LPORT_LED_CNTRL_REG,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_REG,
+    &LPORT_LED_LINK_AND_SPEED_ENCODING_REG,
+    &LPORT_LED_AGGREGATE_LED_CNTRL_REG,
+    &LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_REG,
+};
+
+unsigned long LPORT_LED_ADDRS[] =
+{
+    0x8013c074,
+    0x8013c080,
+    0x8013c08c,
+    0x8013c098,
+    0x8013c0a4,
+    0x8013c0b0,
+    0x8013c0bc,
+    0x8013c0c8,
+};
+
+const ru_block_rec LPORT_LED_BLOCK = 
+{
+    "LPORT_LED",
+    LPORT_LED_ADDRS,
+    8,
+    5,
+    LPORT_LED_REGS
+};
+
+/* End of file BCM6858_A0LPORT_LED.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_MAB_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_MAB_AG.c
new file mode 100644
index 0000000000..416d3d26b3
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_MAB_AG.c
@@ -0,0 +1,824 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+#if RU_INCLUDE_FIELD_DB
+/******************************************************************************
+ * Field: LPORT_MAB_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_MAB_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_MAB_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_MAB_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_CNTRL_LINK_DOWN_RST_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD =
+{
+    "LINK_DOWN_RST_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When this bit is set asynchronous RX and TX FIFOs are reset for a port when the link goes down "
+    "that is when the local fault is detected.",
+#endif
+    LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_MASK,
+    0,
+    LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_WIDTH,
+    LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_CNTRL_RESERVED1
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_CNTRL_RESERVED1_FIELD =
+{
+    "RESERVED1",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_MAB_CNTRL_RESERVED1_FIELD_MASK,
+    0,
+    LPORT_MAB_CNTRL_RESERVED1_FIELD_WIDTH,
+    LPORT_MAB_CNTRL_RESERVED1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_CNTRL_XGMII_TX_RST
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD =
+{
+    "XGMII_TX_RST",
+#if RU_INCLUDE_DESC
+    "",
+    "When set resets 10G Port 0 asynchronous TX FIFO and associated logic (such as credit logic).",
+#endif
+    LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_MASK,
+    0,
+    LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_WIDTH,
+    LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_CNTRL_GMII_TX_RST
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_CNTRL_GMII_TX_RST_FIELD =
+{
+    "GMII_TX_RST",
+#if RU_INCLUDE_DESC
+    "",
+    "When a bit in this vector is set it resets corresponding port (Port 3-0) asynchronous TX FIFO "
+    "and associated logic (such as credit logic and byte slicers).",
+#endif
+    LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_MASK,
+    0,
+    LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_WIDTH,
+    LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_CNTRL_RESERVED2
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_CNTRL_RESERVED2_FIELD =
+{
+    "RESERVED2",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_MAB_CNTRL_RESERVED2_FIELD_MASK,
+    0,
+    LPORT_MAB_CNTRL_RESERVED2_FIELD_WIDTH,
+    LPORT_MAB_CNTRL_RESERVED2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_CNTRL_XGMII_RX_RST
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD =
+{
+    "XGMII_RX_RST",
+#if RU_INCLUDE_DESC
+    "",
+    "When set resets 10G Port 0 asynchronous RX FIFO and associated logic.",
+#endif
+    LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_MASK,
+    0,
+    LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_WIDTH,
+    LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_CNTRL_GMII_RX_RST
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_CNTRL_GMII_RX_RST_FIELD =
+{
+    "GMII_RX_RST",
+#if RU_INCLUDE_DESC
+    "",
+    "When a bit in this vector is set it resets corresponding port (Port 3-0) asynchronous RX FIFO "
+    "and associated logic (such as byte packers).",
+#endif
+    LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_MASK,
+    0,
+    LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_WIDTH,
+    LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_WRR_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_WRR_CTRL_ARB_MODE
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD =
+{
+    "ARB_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "Arbiter Mode\n"
+    "1'b0 - Fixed Mode. TDM slots allocated regardless of the port activity.\n"
+    "1'b1 - Work-Conserving Mode. TDM slots allocation is affected by the port activity.",
+#endif
+    LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_WIDTH,
+    LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD =
+{
+    "P7_WEIGHT",
+#if RU_INCLUDE_DESC
+    "",
+    "P7 weight expressed in TDM time slots.",
+#endif
+    LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_WIDTH,
+    LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD =
+{
+    "P6_WEIGHT",
+#if RU_INCLUDE_DESC
+    "",
+    "P6 weight expressed in TDM time slots.",
+#endif
+    LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_WIDTH,
+    LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD =
+{
+    "P5_WEIGHT",
+#if RU_INCLUDE_DESC
+    "",
+    "P5 weight expressed in TDM time slots.",
+#endif
+    LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_WIDTH,
+    LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD =
+{
+    "P4_WEIGHT",
+#if RU_INCLUDE_DESC
+    "",
+    "P4 weight expressed in TDM time slots.\n"
+    "Allocated port bandwidth is equal to TOTAL_BW*(Px_WEIGHT/SUM(P4_WEIGHT,...,P7_WEIGHT) (where TOTAL_BW is 25.6Gb/as for 400MHz MSBUS clock).",
+#endif
+    LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_WIDTH,
+    LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_THRESHOLD_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_WIDTH,
+    LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD =
+{
+    "XGMII1_TX_THRESHOLD",
+#if RU_INCLUDE_DESC
+    "",
+    "XGMII1 (P4) asynchronous TX FIFO read depth at which packet dequeue starts.",
+#endif
+    LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_WIDTH,
+    LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD =
+{
+    "GMII7_TX_THRESHOLD",
+#if RU_INCLUDE_DESC
+    "",
+    "GMII P7 asynchronous TX FIFO read depth at which packet dequeue starts.",
+#endif
+    LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_WIDTH,
+    LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD =
+{
+    "GMII6_TX_THRESHOLD",
+#if RU_INCLUDE_DESC
+    "",
+    "GMII P6 asynchronous TX FIFO read depth at which packet dequeue starts.",
+#endif
+    LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_WIDTH,
+    LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD =
+{
+    "GMII5_TX_THRESHOLD",
+#if RU_INCLUDE_DESC
+    "",
+    "GMII P5 asynchronous TX FIFO read depth at which packet dequeue starts.",
+#endif
+    LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_WIDTH,
+    LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD =
+{
+    "GMII4_TX_THRESHOLD",
+#if RU_INCLUDE_DESC
+    "",
+    "GMII P4 asynchronous TX FIFO read depth at which packet dequeue starts.",
+#endif
+    LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_MASK,
+    0,
+    LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_WIDTH,
+    LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_WIDTH,
+    LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD =
+{
+    "TXCTL",
+#if RU_INCLUDE_DESC
+    "",
+    "When LINK_DOWN_RST_EN = 1 and link is down content of this register is sent to serdes over XGMII interface. "
+    " In GMII mode 0 is sent.",
+#endif
+    LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_MASK,
+    0,
+    LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_WIDTH,
+    LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_LINK_DOWN_TX_DATA_TXD
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD =
+{
+    "TXD",
+#if RU_INCLUDE_DESC
+    "",
+    "When LINK_DOWN_RST_EN = 1 and link is down content of this register is sent to serdes over XGMII interface. "
+    "In GMII mode 0's are sent.",
+#endif
+    LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_MASK,
+    0,
+    LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_WIDTH,
+    LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_MAB_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_MAB_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_MAB_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD =
+{
+    "XGMII_RX_AFIFO_OVERRUN",
+#if RU_INCLUDE_DESC
+    "",
+    "10G Port 0 asynchronous RX FIFO over-run status.",
+#endif
+    LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_MASK,
+    0,
+    LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_WIDTH,
+    LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD =
+{
+    "GMII_RX_AFIFO_OVERRUN_VECT",
+#if RU_INCLUDE_DESC
+    "",
+    "Port 3-0 asynchronous RX FIFO over-run status.",
+#endif
+    LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_MASK,
+    0,
+    LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_WIDTH,
+    LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD =
+{
+    "XGMII_TX_FRM_UNDERRUN",
+#if RU_INCLUDE_DESC
+    "",
+    "10G Port 0 TX frame under-run status.",
+#endif
+    LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_MASK,
+    0,
+    LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_WIDTH,
+    LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD =
+{
+    "XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN",
+#if RU_INCLUDE_DESC
+    "",
+    "10G Port 0 TX credits under-run status.",
+#endif
+    LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_MASK,
+    0,
+    LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_WIDTH,
+    LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD =
+{
+    "GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT",
+#if RU_INCLUDE_DESC
+    "",
+    "Port 3-0 TX credits under-run status.",
+#endif
+    LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_MASK,
+    0,
+    LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_WIDTH,
+    LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD =
+{
+    "XGMII_TX_AFIFO_OVERRUN",
+#if RU_INCLUDE_DESC
+    "",
+    "10G Port 0 asynchronous TX FIFO over-run status.",
+#endif
+    LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_MASK,
+    0,
+    LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_WIDTH,
+    LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT
+ ******************************************************************************/
+const ru_field_rec LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD =
+{
+    "GMII_TX_AFIFO_OVERRUN_VECT",
+#if RU_INCLUDE_DESC
+    "",
+    "Port 3-0 asynchronous TX FIFO over-run status.",
+#endif
+    LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_MASK,
+    0,
+    LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_WIDTH,
+    LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+/******************************************************************************
+ * Register: LPORT_MAB_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MAB_CNTRL_FIELDS[] =
+{
+    &LPORT_MAB_CNTRL_RESERVED0_FIELD,
+    &LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD,
+    &LPORT_MAB_CNTRL_RESERVED1_FIELD,
+    &LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD,
+    &LPORT_MAB_CNTRL_GMII_TX_RST_FIELD,
+    &LPORT_MAB_CNTRL_RESERVED2_FIELD,
+    &LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD,
+    &LPORT_MAB_CNTRL_GMII_RX_RST_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MAB_CNTRL_REG = 
+{
+    "CNTRL",
+#if RU_INCLUDE_DESC
+    "MSBUS 1 Adaptation Control Register",
+    "",
+#endif
+    LPORT_MAB_CNTRL_REG_OFFSET,
+    0,
+    0,
+    295,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    8,
+    LPORT_MAB_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_MAB_TX_WRR_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MAB_TX_WRR_CTRL_FIELDS[] =
+{
+    &LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD,
+    &LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD,
+    &LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD,
+    &LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD,
+    &LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD,
+    &LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MAB_TX_WRR_CTRL_REG = 
+{
+    "TX_WRR_CTRL",
+#if RU_INCLUDE_DESC
+    "MSBUS 1 Adaptation TX WRR Control Register",
+    "",
+#endif
+    LPORT_MAB_TX_WRR_CTRL_REG_OFFSET,
+    0,
+    0,
+    296,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_MAB_TX_WRR_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_MAB_TX_THRESHOLD
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MAB_TX_THRESHOLD_FIELDS[] =
+{
+    &LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD,
+    &LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD,
+    &LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD,
+    &LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD,
+    &LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD,
+    &LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MAB_TX_THRESHOLD_REG = 
+{
+    "TX_THRESHOLD",
+#if RU_INCLUDE_DESC
+    "MSBUS 1 Adaptation TX Threshold Register",
+    "",
+#endif
+    LPORT_MAB_TX_THRESHOLD_REG_OFFSET,
+    0,
+    0,
+    297,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_MAB_TX_THRESHOLD_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_MAB_LINK_DOWN_TX_DATA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MAB_LINK_DOWN_TX_DATA_FIELDS[] =
+{
+    &LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD,
+    &LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD,
+    &LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MAB_LINK_DOWN_TX_DATA_REG = 
+{
+    "LINK_DOWN_TX_DATA",
+#if RU_INCLUDE_DESC
+    "MSBUS 1 Adaptation Link down TX Data Register",
+    "",
+#endif
+    LPORT_MAB_LINK_DOWN_TX_DATA_REG_OFFSET,
+    0,
+    0,
+    298,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_MAB_LINK_DOWN_TX_DATA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_MAB_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MAB_STATUS_FIELDS[] =
+{
+    &LPORT_MAB_STATUS_RESERVED0_FIELD,
+    &LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD,
+    &LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD,
+    &LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD,
+    &LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD,
+    &LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD,
+    &LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD,
+    &LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MAB_STATUS_REG = 
+{
+    "STATUS",
+#if RU_INCLUDE_DESC
+    "MSBUS 1 Adaptation Status Register",
+    "",
+#endif
+    LPORT_MAB_STATUS_REG_OFFSET,
+    0,
+    0,
+    299,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    8,
+    LPORT_MAB_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Block: LPORT_MAB
+ ******************************************************************************/
+static const ru_reg_rec *LPORT_MAB_REGS[] =
+{
+    &LPORT_MAB_CNTRL_REG,
+    &LPORT_MAB_TX_WRR_CTRL_REG,
+    &LPORT_MAB_TX_THRESHOLD_REG,
+    &LPORT_MAB_LINK_DOWN_TX_DATA_REG,
+    &LPORT_MAB_STATUS_REG,
+};
+
+unsigned long LPORT_MAB_ADDRS[] =
+{
+    0x8013d700,
+    0x8013d800,
+};
+
+const ru_block_rec LPORT_MAB_BLOCK = 
+{
+    "LPORT_MAB",
+    LPORT_MAB_ADDRS,
+    2,
+    5,
+    LPORT_MAB_REGS
+};
+
+/* End of file BCM6858_A0LPORT_MAB.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_MDIO_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_MDIO_AG.c
new file mode 100644
index 0000000000..c9bf8bb18a
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_MDIO_AG.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+#if RU_INCLUDE_FIELD_DB
+/******************************************************************************
+ * Field: LPORT_MDIO_CMD_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CMD_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_MDIO_CMD_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_MDIO_CMD_RESERVED0_FIELD_WIDTH,
+    LPORT_MDIO_CMD_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CMD_START_BUSY
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CMD_START_BUSY_FIELD =
+{
+    "START_BUSY",
+#if RU_INCLUDE_DESC
+    "",
+    "START_BUSY, Self-clearing, CPU writes this bit to 1 in order to initiate MDIO transaction. When transaction completes hardware will clear this bit.",
+#endif
+    LPORT_MDIO_CMD_START_BUSY_FIELD_MASK,
+    0,
+    LPORT_MDIO_CMD_START_BUSY_FIELD_WIDTH,
+    LPORT_MDIO_CMD_START_BUSY_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CMD_FAIL
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CMD_FAIL_FIELD =
+{
+    "FAIL",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit is set when PHY does not reply to READ command (PHY does not drive 0 on bus turnaround).",
+#endif
+    LPORT_MDIO_CMD_FAIL_FIELD_MASK,
+    0,
+    LPORT_MDIO_CMD_FAIL_FIELD_WIDTH,
+    LPORT_MDIO_CMD_FAIL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CMD_OP_CODE
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CMD_OP_CODE_FIELD =
+{
+    "OP_CODE",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO command that is OP[1:0]:\n"
+    "00 - Address for clause 45.\n"
+    "01 - Write.\n"
+    "10 - Read increment for clause 45.\n"
+    "11 - Read for clause 45.\n"
+    "10 - Read for clause 22.\n",
+#endif
+    LPORT_MDIO_CMD_OP_CODE_FIELD_MASK,
+    0,
+    LPORT_MDIO_CMD_OP_CODE_FIELD_WIDTH,
+    LPORT_MDIO_CMD_OP_CODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CMD_PHY_PRT_ADDR
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD =
+{
+    "PHY_PRT_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "PHY address[4:0] for clause 22, Port address[4:0] for Clause 45.",
+#endif
+    LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD_MASK,
+    0,
+    LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD_WIDTH,
+    LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CMD_REG_DEV_ADDR
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD =
+{
+    "REG_DEV_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "Register address[4:0] for clause 22, Device address[4:0] for Clause 45.",
+#endif
+    LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD_MASK,
+    0,
+    LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD_WIDTH,
+    LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CMD_DATA_ADDR
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CMD_DATA_ADDR_FIELD =
+{
+    "DATA_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO Read/Write data[15:0], clause 22 and 45 or MDIO address[15:0] for clause 45\".",
+#endif
+    LPORT_MDIO_CMD_DATA_ADDR_FIELD_MASK,
+    0,
+    LPORT_MDIO_CMD_DATA_ADDR_FIELD_WIDTH,
+    LPORT_MDIO_CMD_DATA_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CFG_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CFG_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_MDIO_CFG_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_MDIO_CFG_RESERVED0_FIELD_WIDTH,
+    LPORT_MDIO_CFG_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CFG_SUPRESS_PREAMBLE
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD =
+{
+    "SUPRESS_PREAMBLE",
+#if RU_INCLUDE_DESC
+    "",
+    "When this bit set, preamble (32 consectutive 1's) is suppressed for MDIO transaction that is MDIO transaction starts with ST.",
+#endif
+    LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD_MASK,
+    0,
+    LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD_WIDTH,
+    LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD =
+{
+    "FREE_RUN_CLK_ENABLE",
+#if RU_INCLUDE_DESC
+    "",
+    "When this bit set, MDIO clock is enabled and running.",
+#endif
+    LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD_MASK,
+    0,
+    LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD_WIDTH,
+    LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CFG_MDIO_CLK_DIVIDER
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD =
+{
+    "MDIO_CLK_DIVIDER",
+#if RU_INCLUDE_DESC
+    "",
+    "MDIO clock divider[7:0], Reference clock (typically 250 MHz) is divided by 2x(MDIO_CLK_DIVIDER+1) to generate MDIO clock(MDC).",
+#endif
+    LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_MASK,
+    0,
+    LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_WIDTH,
+    LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CFG_RESERVED2
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CFG_RESERVED2_FIELD =
+{
+    "RESERVED2",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_MDIO_CFG_RESERVED2_FIELD_MASK,
+    0,
+    LPORT_MDIO_CFG_RESERVED2_FIELD_WIDTH,
+    LPORT_MDIO_CFG_RESERVED2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MDIO_CFG_MDIO_CLAUSE
+ ******************************************************************************/
+const ru_field_rec LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD =
+{
+    "MDIO_CLAUSE",
+#if RU_INCLUDE_DESC
+    "",
+    "0: Clause 45.\n"
+    "1: Clause 22.",
+#endif
+    LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD_MASK,
+    0,
+    LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD_WIDTH,
+    LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+/******************************************************************************
+ * Register: LPORT_MDIO_CMD
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MDIO_CMD_FIELDS[] =
+{
+    &LPORT_MDIO_CMD_RESERVED0_FIELD,
+    &LPORT_MDIO_CMD_START_BUSY_FIELD,
+    &LPORT_MDIO_CMD_FAIL_FIELD,
+    &LPORT_MDIO_CMD_OP_CODE_FIELD,
+    &LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD,
+    &LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD,
+    &LPORT_MDIO_CMD_DATA_ADDR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MDIO_CMD_REG = 
+{
+    "CMD",
+#if RU_INCLUDE_DESC
+    "MDIO Command Register",
+    "",
+#endif
+    LPORT_MDIO_CMD_REG_OFFSET,
+    0,
+    0,
+    269,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_MDIO_CMD_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_MDIO_CFG
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MDIO_CFG_FIELDS[] =
+{
+    &LPORT_MDIO_CFG_RESERVED0_FIELD,
+    &LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD,
+    &LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD,
+    &LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD,
+    &LPORT_MDIO_CFG_RESERVED2_FIELD,
+    &LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MDIO_CFG_REG = 
+{
+    "CFG",
+#if RU_INCLUDE_DESC
+    "MDIO Configuration Register",
+    "",
+#endif
+    LPORT_MDIO_CFG_REG_OFFSET,
+    0,
+    0,
+    270,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_MDIO_CFG_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Block: LPORT_MDIO
+ ******************************************************************************/
+static const ru_reg_rec *LPORT_MDIO_REGS[] =
+{
+    &LPORT_MDIO_CMD_REG,
+    &LPORT_MDIO_CFG_REG,
+};
+
+unsigned long LPORT_MDIO_ADDRS[] =
+{
+    0x8013d400,
+};
+
+const ru_block_rec LPORT_MDIO_BLOCK = 
+{
+    "LPORT_MDIO",
+    LPORT_MDIO_ADDRS,
+    1,
+    2,
+    LPORT_MDIO_REGS
+};
+
+/* End of file BCM6858_A0LPORT_MDIO.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_MIB_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_MIB_AG.c
new file mode 100644
index 0000000000..5296a216a8
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_MIB_AG.c
@@ -0,0 +1,47693 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+#if RU_INCLUDE_FIELD_DB
+/******************************************************************************
+ * Field: LPORT_MIB_GRX64_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRX64_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRX64_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRX64_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRX64_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRX127_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRX127_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRX127_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRX127_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRX127_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRX255_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRX255_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRX255_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRX255_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRX255_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRX511_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRX511_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRX511_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRX511_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRX511_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRX1023_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRX1023_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRX1023_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRX1023_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRX1023_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRX1518_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRX1518_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRX1518_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRX1518_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRX1518_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRX1522_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRX1522_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRX1522_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRX1522_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRX1522_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRX2047_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRX2047_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRX2047_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRX2047_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRX2047_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRX4095_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRX4095_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRX4095_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRX4095_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRX4095_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRX9216_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRX9216_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRX9216_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRX9216_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRX9216_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRX16383_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRX16383_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRX16383_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRX16383_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRX16383_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPKT_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPKT_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPKT_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPKT_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPKT_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXUCA_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXUCA_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXUCA_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXUCA_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXUCA_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXMCA_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXMCA_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXMCA_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXMCA_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXMCA_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXBCA_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXBCA_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXBCA_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXBCA_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXBCA_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXFCS_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXFCS_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXFCS_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXFCS_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXFCS_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXCF_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXCF_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXCF_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXCF_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXCF_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPF_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPF_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPF_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPF_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPF_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPP_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPP_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPP_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPP_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPP_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXUO_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXUO_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXUO_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXUO_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXUO_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXUDA_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXUDA_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXUDA_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXUDA_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXUDA_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXWSA_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXWSA_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXWSA_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXWSA_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXWSA_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXALN_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXALN_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXALN_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXALN_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXALN_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXFLR_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXFLR_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXFLR_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXFLR_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXFLR_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXFRERR_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXFRERR_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXFRERR_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXFRERR_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXFRERR_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXFCR_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXFCR_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXFCR_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXFCR_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXFCR_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXOVR_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXOVR_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXOVR_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXOVR_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXOVR_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXJBR_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXJBR_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXJBR_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXJBR_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXJBR_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXMTUE_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXMTUE_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXMTUE_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXMTUE_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXMTUE_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXMCRC_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXMCRC_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXMCRC_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXMCRC_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXMCRC_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPRM_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPRM_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPRM_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPRM_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPRM_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXVLN_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXVLN_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXVLN_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXVLN_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXVLN_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXDVLN_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXDVLN_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXDVLN_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXDVLN_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXDVLN_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXTRFU_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXTRFU_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXTRFU_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXTRFU_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXTRFU_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPOK_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPOK_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPOK_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPOK_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPOK_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCOFF0_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCOFF1_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCOFF2_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCOFF3_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCOFF4_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCOFF5_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCOFF6_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCOFF7_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCP0_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCP0_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCP0_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCP0_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCP0_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCP1_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCP1_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCP1_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCP1_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCP1_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCP2_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCP2_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCP2_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCP2_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCP2_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCP3_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCP3_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCP3_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCP3_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCP3_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCP4_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCP4_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCP4_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCP4_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCP4_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCP5_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCP5_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCP5_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCP5_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCP5_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCP6_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCP6_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCP6_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCP6_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCP6_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPFCP7_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPFCP7_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPFCP7_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPFCP7_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPFCP7_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXSCHCRC_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXSCHCRC_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXSCHCRC_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXSCHCRC_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXSCHCRC_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXBYT_COUNT48
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXBYT_COUNT48_FIELD =
+{
+    "COUNT48",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 48 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXBYT_COUNT48_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXBYT_COUNT48_FIELD_WIDTH,
+    LPORT_MIB_GRXBYT_COUNT48_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXRPKT_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXRPKT_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXRPKT_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXRPKT_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXRPKT_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXUND_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXUND_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXUND_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXUND_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXUND_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXFRG_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXFRG_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXFRG_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXFRG_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXFRG_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXRBYT_COUNT48
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXRBYT_COUNT48_FIELD =
+{
+    "COUNT48",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 48 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXRBYT_COUNT48_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXRBYT_COUNT48_FIELD_WIDTH,
+    LPORT_MIB_GRXRBYT_COUNT48_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTX64_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTX64_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTX64_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTX64_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTX64_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTX127_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTX127_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTX127_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTX127_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTX127_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTX255_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTX255_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTX255_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTX255_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTX255_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTX511_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTX511_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTX511_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTX511_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTX511_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTX1023_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTX1023_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTX1023_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTX1023_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTX1023_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTX1518_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTX1518_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTX1518_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTX1518_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTX1518_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTX1522_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTX1522_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTX1522_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTX1522_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTX1522_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTX2047_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTX2047_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTX2047_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTX2047_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTX2047_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTX4095_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTX4095_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTX4095_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTX4095_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTX4095_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTX9216_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTX9216_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTX9216_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTX9216_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTX9216_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTX16383_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTX16383_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTX16383_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTX16383_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTX16383_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPOK_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPOK_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPOK_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPOK_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPOK_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPKT_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPKT_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPKT_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPKT_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPKT_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXUCA_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXUCA_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXUCA_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXUCA_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXUCA_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXMCA_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXMCA_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXMCA_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXMCA_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXMCA_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXBCA_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXBCA_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXBCA_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXBCA_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXBCA_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPF_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPF_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPF_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPF_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPF_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPFC_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPFC_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPFC_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPFC_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPFC_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXJBR_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXJBR_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXJBR_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXJBR_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXJBR_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXFCS_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXFCS_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXFCS_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXFCS_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXFCS_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXCF_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXCF_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXCF_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXCF_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXCF_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXOVR_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXOVR_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXOVR_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXOVR_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXOVR_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXDFR_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXDFR_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXDFR_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXDFR_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXDFR_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXEDF_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXEDF_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXEDF_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXEDF_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXEDF_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXSCL_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXSCL_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXSCL_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXSCL_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXSCL_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXMCL_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXMCL_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXMCL_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXMCL_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXMCL_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXLCL_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXLCL_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXLCL_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXLCL_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXLCL_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXXCL_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXXCL_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXXCL_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXXCL_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXXCL_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXFRG_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXFRG_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXFRG_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXFRG_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXFRG_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXERR_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXERR_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXERR_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXERR_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXERR_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXVLN_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXVLN_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXVLN_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXVLN_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXVLN_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXDVLN_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXDVLN_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXDVLN_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXDVLN_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXDVLN_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXRPKT_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXRPKT_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXRPKT_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXRPKT_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXRPKT_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXUFL_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXUFL_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXUFL_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXUFL_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXUFL_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPFCP0_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPFCP0_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPFCP0_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPFCP0_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPFCP0_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPFCP1_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPFCP1_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPFCP1_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPFCP1_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPFCP1_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPFCP2_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPFCP2_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPFCP2_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPFCP2_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPFCP2_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPFCP3_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPFCP3_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPFCP3_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPFCP3_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPFCP3_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPFCP4_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPFCP4_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPFCP4_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPFCP4_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPFCP4_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPFCP5_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPFCP5_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPFCP5_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPFCP5_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPFCP5_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPFCP6_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPFCP6_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPFCP6_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPFCP6_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPFCP6_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXPFCP7_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXPFCP7_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXPFCP7_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXPFCP7_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXPFCP7_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXNCL_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXNCL_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXNCL_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXNCL_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXNCL_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXBYT_COUNT48
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXBYT_COUNT48_FIELD =
+{
+    "COUNT48",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 48 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXBYT_COUNT48_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXBYT_COUNT48_FIELD_WIDTH,
+    LPORT_MIB_GTXBYT_COUNT48_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXLPI_COUNT32
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXLPI_COUNT32_FIELD =
+{
+    "COUNT32",
+#if RU_INCLUDE_DESC
+    "",
+    "The 32-bit MIB counter value.\n"
+    "This MIB counter is 32 bits wide in hardware, unlike most of other MIB counters (which are more than 32 bits wide).",
+#endif
+    LPORT_MIB_GRXLPI_COUNT32_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXLPI_COUNT32_FIELD_WIDTH,
+    LPORT_MIB_GRXLPI_COUNT32_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXDLPI_COUNT32
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXDLPI_COUNT32_FIELD =
+{
+    "COUNT32",
+#if RU_INCLUDE_DESC
+    "",
+    "The 32-bit MIB counter value.\n"
+    "This MIB counter is 32 bits wide in hardware, unlike most of other MIB counters (which are more than 32 bits wide).",
+#endif
+    LPORT_MIB_GRXDLPI_COUNT32_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXDLPI_COUNT32_FIELD_WIDTH,
+    LPORT_MIB_GRXDLPI_COUNT32_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXLPI_COUNT32
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXLPI_COUNT32_FIELD =
+{
+    "COUNT32",
+#if RU_INCLUDE_DESC
+    "",
+    "The 32-bit MIB counter value.\n"
+    "This MIB counter is 32 bits wide in hardware, unlike most of other MIB counters (which are more than 32 bits wide).",
+#endif
+    LPORT_MIB_GTXLPI_COUNT32_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXLPI_COUNT32_FIELD_WIDTH,
+    LPORT_MIB_GTXLPI_COUNT32_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXDLPI_COUNT32
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXDLPI_COUNT32_FIELD =
+{
+    "COUNT32",
+#if RU_INCLUDE_DESC
+    "",
+    "The 32-bit MIB counter value.\n"
+    "This MIB counter is 32 bits wide in hardware, unlike most of other MIB counters (which are more than 32 bits wide).",
+#endif
+    LPORT_MIB_GTXDLPI_COUNT32_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXDLPI_COUNT32_FIELD_WIDTH,
+    LPORT_MIB_GTXDLPI_COUNT32_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXPTLLFC_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXPTLLFC_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXPTLLFC_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXPTLLFC_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXPTLLFC_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXLTLLFC_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXLTLLFC_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXLTLLFC_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXLTLLFC_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXLTLLFC_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GRXLLFCFCS_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_MIB_GTXLTLLFC_COUNT40
+ ******************************************************************************/
+const ru_field_rec LPORT_MIB_GTXLTLLFC_COUNT40_FIELD =
+{
+    "COUNT40",
+#if RU_INCLUDE_DESC
+    "",
+    "This MIB counter is 40 bits wide in hardware.\n"
+    "LPORT register reads and writes are however 32 bits per transaction.\n"
+    "When reading from this address, higher counter bits are copied to MIBx 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register.\n"
+    "Similarly, when writing to this address, higher MIB counter bits are taken from MIBx 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access MIB counters (see MIBx Indirect Access registers).",
+#endif
+    LPORT_MIB_GTXLTLLFC_COUNT40_FIELD_MASK,
+    0,
+    LPORT_MIB_GTXLTLLFC_COUNT40_FIELD_WIDTH,
+    LPORT_MIB_GTXLTLLFC_COUNT40_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRX64
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRX64_FIELDS[] =
+{
+    &LPORT_MIB_GRX64_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRX64_REG = 
+{
+    "GRX64",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRX64_REG_OFFSET,
+    0,
+    0,
+    74,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRX64_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRX127
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRX127_FIELDS[] =
+{
+    &LPORT_MIB_GRX127_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRX127_REG = 
+{
+    "GRX127",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRX127_REG_OFFSET,
+    0,
+    0,
+    75,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRX127_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRX255
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRX255_FIELDS[] =
+{
+    &LPORT_MIB_GRX255_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRX255_REG = 
+{
+    "GRX255",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRX255_REG_OFFSET,
+    0,
+    0,
+    76,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRX255_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRX511
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRX511_FIELDS[] =
+{
+    &LPORT_MIB_GRX511_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRX511_REG = 
+{
+    "GRX511",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRX511_REG_OFFSET,
+    0,
+    0,
+    77,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRX511_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRX1023
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRX1023_FIELDS[] =
+{
+    &LPORT_MIB_GRX1023_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRX1023_REG = 
+{
+    "GRX1023",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRX1023_REG_OFFSET,
+    0,
+    0,
+    78,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRX1023_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRX1518
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRX1518_FIELDS[] =
+{
+    &LPORT_MIB_GRX1518_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRX1518_REG = 
+{
+    "GRX1518",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRX1518_REG_OFFSET,
+    0,
+    0,
+    79,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRX1518_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRX1522
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRX1522_FIELDS[] =
+{
+    &LPORT_MIB_GRX1522_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRX1522_REG = 
+{
+    "GRX1522",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRX1522_REG_OFFSET,
+    0,
+    0,
+    80,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRX1522_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRX2047
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRX2047_FIELDS[] =
+{
+    &LPORT_MIB_GRX2047_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRX2047_REG = 
+{
+    "GRX2047",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRX2047_REG_OFFSET,
+    0,
+    0,
+    81,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRX2047_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRX4095
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRX4095_FIELDS[] =
+{
+    &LPORT_MIB_GRX4095_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRX4095_REG = 
+{
+    "GRX4095",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRX4095_REG_OFFSET,
+    0,
+    0,
+    82,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRX4095_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRX9216
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRX9216_FIELDS[] =
+{
+    &LPORT_MIB_GRX9216_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRX9216_REG = 
+{
+    "GRX9216",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRX9216_REG_OFFSET,
+    0,
+    0,
+    83,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRX9216_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRX16383
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRX16383_FIELDS[] =
+{
+    &LPORT_MIB_GRX16383_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRX16383_REG = 
+{
+    "GRX16383",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRX16383_REG_OFFSET,
+    0,
+    0,
+    84,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRX16383_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPKT
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPKT_FIELDS[] =
+{
+    &LPORT_MIB_GRXPKT_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPKT_REG = 
+{
+    "GRXPKT",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPKT_REG_OFFSET,
+    0,
+    0,
+    85,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPKT_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXUCA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXUCA_FIELDS[] =
+{
+    &LPORT_MIB_GRXUCA_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXUCA_REG = 
+{
+    "GRXUCA",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXUCA_REG_OFFSET,
+    0,
+    0,
+    86,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXUCA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXMCA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXMCA_FIELDS[] =
+{
+    &LPORT_MIB_GRXMCA_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXMCA_REG = 
+{
+    "GRXMCA",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXMCA_REG_OFFSET,
+    0,
+    0,
+    87,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXMCA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXBCA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXBCA_FIELDS[] =
+{
+    &LPORT_MIB_GRXBCA_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXBCA_REG = 
+{
+    "GRXBCA",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXBCA_REG_OFFSET,
+    0,
+    0,
+    88,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXBCA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXFCS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXFCS_FIELDS[] =
+{
+    &LPORT_MIB_GRXFCS_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXFCS_REG = 
+{
+    "GRXFCS",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXFCS_REG_OFFSET,
+    0,
+    0,
+    89,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXFCS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXCF
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXCF_FIELDS[] =
+{
+    &LPORT_MIB_GRXCF_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXCF_REG = 
+{
+    "GRXCF",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXCF_REG_OFFSET,
+    0,
+    0,
+    90,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXCF_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPF
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPF_FIELDS[] =
+{
+    &LPORT_MIB_GRXPF_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPF_REG = 
+{
+    "GRXPF",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPF_REG_OFFSET,
+    0,
+    0,
+    91,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPF_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPP
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPP_FIELDS[] =
+{
+    &LPORT_MIB_GRXPP_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPP_REG = 
+{
+    "GRXPP",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPP_REG_OFFSET,
+    0,
+    0,
+    92,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPP_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXUO
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXUO_FIELDS[] =
+{
+    &LPORT_MIB_GRXUO_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXUO_REG = 
+{
+    "GRXUO",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXUO_REG_OFFSET,
+    0,
+    0,
+    93,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXUO_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXUDA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXUDA_FIELDS[] =
+{
+    &LPORT_MIB_GRXUDA_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXUDA_REG = 
+{
+    "GRXUDA",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXUDA_REG_OFFSET,
+    0,
+    0,
+    94,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXUDA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXWSA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXWSA_FIELDS[] =
+{
+    &LPORT_MIB_GRXWSA_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXWSA_REG = 
+{
+    "GRXWSA",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXWSA_REG_OFFSET,
+    0,
+    0,
+    95,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXWSA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXALN
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXALN_FIELDS[] =
+{
+    &LPORT_MIB_GRXALN_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXALN_REG = 
+{
+    "GRXALN",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXALN_REG_OFFSET,
+    0,
+    0,
+    96,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXALN_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXFLR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXFLR_FIELDS[] =
+{
+    &LPORT_MIB_GRXFLR_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXFLR_REG = 
+{
+    "GRXFLR",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXFLR_REG_OFFSET,
+    0,
+    0,
+    97,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXFLR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXFRERR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXFRERR_FIELDS[] =
+{
+    &LPORT_MIB_GRXFRERR_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXFRERR_REG = 
+{
+    "GRXFRERR",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXFRERR_REG_OFFSET,
+    0,
+    0,
+    98,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXFRERR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXFCR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXFCR_FIELDS[] =
+{
+    &LPORT_MIB_GRXFCR_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXFCR_REG = 
+{
+    "GRXFCR",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXFCR_REG_OFFSET,
+    0,
+    0,
+    99,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXFCR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXOVR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXOVR_FIELDS[] =
+{
+    &LPORT_MIB_GRXOVR_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXOVR_REG = 
+{
+    "GRXOVR",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXOVR_REG_OFFSET,
+    0,
+    0,
+    100,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXOVR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXJBR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXJBR_FIELDS[] =
+{
+    &LPORT_MIB_GRXJBR_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXJBR_REG = 
+{
+    "GRXJBR",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXJBR_REG_OFFSET,
+    0,
+    0,
+    101,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXJBR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXMTUE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXMTUE_FIELDS[] =
+{
+    &LPORT_MIB_GRXMTUE_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXMTUE_REG = 
+{
+    "GRXMTUE",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXMTUE_REG_OFFSET,
+    0,
+    0,
+    102,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXMTUE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXMCRC
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXMCRC_FIELDS[] =
+{
+    &LPORT_MIB_GRXMCRC_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXMCRC_REG = 
+{
+    "GRXMCRC",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXMCRC_REG_OFFSET,
+    0,
+    0,
+    103,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXMCRC_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPRM
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPRM_FIELDS[] =
+{
+    &LPORT_MIB_GRXPRM_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPRM_REG = 
+{
+    "GRXPRM",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPRM_REG_OFFSET,
+    0,
+    0,
+    104,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPRM_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXVLN
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXVLN_FIELDS[] =
+{
+    &LPORT_MIB_GRXVLN_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXVLN_REG = 
+{
+    "GRXVLN",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXVLN_REG_OFFSET,
+    0,
+    0,
+    105,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXVLN_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXDVLN
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXDVLN_FIELDS[] =
+{
+    &LPORT_MIB_GRXDVLN_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXDVLN_REG = 
+{
+    "GRXDVLN",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXDVLN_REG_OFFSET,
+    0,
+    0,
+    106,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXDVLN_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXTRFU
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXTRFU_FIELDS[] =
+{
+    &LPORT_MIB_GRXTRFU_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXTRFU_REG = 
+{
+    "GRXTRFU",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXTRFU_REG_OFFSET,
+    0,
+    0,
+    107,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXTRFU_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPOK
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPOK_FIELDS[] =
+{
+    &LPORT_MIB_GRXPOK_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPOK_REG = 
+{
+    "GRXPOK",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPOK_REG_OFFSET,
+    0,
+    0,
+    108,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPOK_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCOFF0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCOFF0_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCOFF0_REG = 
+{
+    "GRXPFCOFF0",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCOFF0_REG_OFFSET,
+    0,
+    0,
+    109,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCOFF0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCOFF1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCOFF1_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCOFF1_REG = 
+{
+    "GRXPFCOFF1",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCOFF1_REG_OFFSET,
+    0,
+    0,
+    110,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCOFF1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCOFF2
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCOFF2_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCOFF2_REG = 
+{
+    "GRXPFCOFF2",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCOFF2_REG_OFFSET,
+    0,
+    0,
+    111,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCOFF2_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCOFF3
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCOFF3_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCOFF3_REG = 
+{
+    "GRXPFCOFF3",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCOFF3_REG_OFFSET,
+    0,
+    0,
+    112,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCOFF3_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCOFF4
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCOFF4_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCOFF4_REG = 
+{
+    "GRXPFCOFF4",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCOFF4_REG_OFFSET,
+    0,
+    0,
+    113,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCOFF4_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCOFF5
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCOFF5_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCOFF5_REG = 
+{
+    "GRXPFCOFF5",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCOFF5_REG_OFFSET,
+    0,
+    0,
+    114,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCOFF5_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCOFF6
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCOFF6_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCOFF6_REG = 
+{
+    "GRXPFCOFF6",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCOFF6_REG_OFFSET,
+    0,
+    0,
+    115,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCOFF6_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCOFF7
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCOFF7_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCOFF7_REG = 
+{
+    "GRXPFCOFF7",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCOFF7_REG_OFFSET,
+    0,
+    0,
+    116,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCOFF7_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCP0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCP0_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCP0_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCP0_REG = 
+{
+    "GRXPFCP0",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCP0_REG_OFFSET,
+    0,
+    0,
+    117,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCP0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCP1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCP1_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCP1_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCP1_REG = 
+{
+    "GRXPFCP1",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCP1_REG_OFFSET,
+    0,
+    0,
+    118,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCP1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCP2
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCP2_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCP2_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCP2_REG = 
+{
+    "GRXPFCP2",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCP2_REG_OFFSET,
+    0,
+    0,
+    119,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCP2_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCP3
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCP3_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCP3_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCP3_REG = 
+{
+    "GRXPFCP3",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCP3_REG_OFFSET,
+    0,
+    0,
+    120,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCP3_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCP4
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCP4_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCP4_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCP4_REG = 
+{
+    "GRXPFCP4",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCP4_REG_OFFSET,
+    0,
+    0,
+    121,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCP4_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCP5
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCP5_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCP5_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCP5_REG = 
+{
+    "GRXPFCP5",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCP5_REG_OFFSET,
+    0,
+    0,
+    122,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCP5_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCP6
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCP6_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCP6_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCP6_REG = 
+{
+    "GRXPFCP6",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCP6_REG_OFFSET,
+    0,
+    0,
+    123,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCP6_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPFCP7
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPFCP7_FIELDS[] =
+{
+    &LPORT_MIB_GRXPFCP7_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPFCP7_REG = 
+{
+    "GRXPFCP7",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPFCP7_REG_OFFSET,
+    0,
+    0,
+    124,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPFCP7_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXSCHCRC
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXSCHCRC_FIELDS[] =
+{
+    &LPORT_MIB_GRXSCHCRC_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXSCHCRC_REG = 
+{
+    "GRXSCHCRC",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXSCHCRC_REG_OFFSET,
+    0,
+    0,
+    125,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXSCHCRC_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXBYT
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXBYT_FIELDS[] =
+{
+    &LPORT_MIB_GRXBYT_COUNT48_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXBYT_REG = 
+{
+    "GRXBYT",
+#if RU_INCLUDE_DESC
+    "Transmit Byte Counter for XLMAC0/port0 (LPORT port0)",
+    "Receive Byte Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 48 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (47:32)."
+    "Receive Runt Byte Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 48 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (47:32)."
+    "Transmit Byte Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 48 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (47:32).",
+#endif
+    LPORT_MIB_GRXBYT_REG_OFFSET,
+    0,
+    0,
+    126,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXBYT_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXRPKT
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXRPKT_FIELDS[] =
+{
+    &LPORT_MIB_GRXRPKT_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXRPKT_REG = 
+{
+    "GRXRPKT",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXRPKT_REG_OFFSET,
+    0,
+    0,
+    127,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXRPKT_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXUND
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXUND_FIELDS[] =
+{
+    &LPORT_MIB_GRXUND_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXUND_REG = 
+{
+    "GRXUND",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXUND_REG_OFFSET,
+    0,
+    0,
+    128,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXUND_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXFRG
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXFRG_FIELDS[] =
+{
+    &LPORT_MIB_GRXFRG_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXFRG_REG = 
+{
+    "GRXFRG",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXFRG_REG_OFFSET,
+    0,
+    0,
+    129,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXFRG_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXRBYT
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXRBYT_FIELDS[] =
+{
+    &LPORT_MIB_GRXRBYT_COUNT48_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXRBYT_REG = 
+{
+    "GRXRBYT",
+#if RU_INCLUDE_DESC
+    "Transmit Byte Counter for XLMAC0/port0 (LPORT port0)",
+    "Receive Byte Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 48 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (47:32)."
+    "Receive Runt Byte Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 48 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (47:32)."
+    "Transmit Byte Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 48 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (47:32).",
+#endif
+    LPORT_MIB_GRXRBYT_REG_OFFSET,
+    0,
+    0,
+    130,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXRBYT_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTX64
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTX64_FIELDS[] =
+{
+    &LPORT_MIB_GTX64_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTX64_REG = 
+{
+    "GTX64",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTX64_REG_OFFSET,
+    0,
+    0,
+    131,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTX64_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTX127
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTX127_FIELDS[] =
+{
+    &LPORT_MIB_GTX127_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTX127_REG = 
+{
+    "GTX127",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTX127_REG_OFFSET,
+    0,
+    0,
+    132,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTX127_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTX255
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTX255_FIELDS[] =
+{
+    &LPORT_MIB_GTX255_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTX255_REG = 
+{
+    "GTX255",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTX255_REG_OFFSET,
+    0,
+    0,
+    133,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTX255_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTX511
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTX511_FIELDS[] =
+{
+    &LPORT_MIB_GTX511_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTX511_REG = 
+{
+    "GTX511",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTX511_REG_OFFSET,
+    0,
+    0,
+    134,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTX511_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTX1023
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTX1023_FIELDS[] =
+{
+    &LPORT_MIB_GTX1023_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTX1023_REG = 
+{
+    "GTX1023",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTX1023_REG_OFFSET,
+    0,
+    0,
+    135,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTX1023_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTX1518
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTX1518_FIELDS[] =
+{
+    &LPORT_MIB_GTX1518_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTX1518_REG = 
+{
+    "GTX1518",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTX1518_REG_OFFSET,
+    0,
+    0,
+    136,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTX1518_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTX1522
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTX1522_FIELDS[] =
+{
+    &LPORT_MIB_GTX1522_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTX1522_REG = 
+{
+    "GTX1522",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTX1522_REG_OFFSET,
+    0,
+    0,
+    137,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTX1522_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTX2047
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTX2047_FIELDS[] =
+{
+    &LPORT_MIB_GTX2047_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTX2047_REG = 
+{
+    "GTX2047",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTX2047_REG_OFFSET,
+    0,
+    0,
+    138,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTX2047_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTX4095
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTX4095_FIELDS[] =
+{
+    &LPORT_MIB_GTX4095_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTX4095_REG = 
+{
+    "GTX4095",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTX4095_REG_OFFSET,
+    0,
+    0,
+    139,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTX4095_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTX9216
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTX9216_FIELDS[] =
+{
+    &LPORT_MIB_GTX9216_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTX9216_REG = 
+{
+    "GTX9216",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTX9216_REG_OFFSET,
+    0,
+    0,
+    140,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTX9216_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTX16383
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTX16383_FIELDS[] =
+{
+    &LPORT_MIB_GTX16383_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTX16383_REG = 
+{
+    "GTX16383",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTX16383_REG_OFFSET,
+    0,
+    0,
+    141,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTX16383_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPOK
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPOK_FIELDS[] =
+{
+    &LPORT_MIB_GTXPOK_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPOK_REG = 
+{
+    "GTXPOK",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPOK_REG_OFFSET,
+    0,
+    0,
+    142,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPOK_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPKT
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPKT_FIELDS[] =
+{
+    &LPORT_MIB_GTXPKT_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPKT_REG = 
+{
+    "GTXPKT",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPKT_REG_OFFSET,
+    0,
+    0,
+    143,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPKT_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXUCA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXUCA_FIELDS[] =
+{
+    &LPORT_MIB_GTXUCA_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXUCA_REG = 
+{
+    "GTXUCA",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXUCA_REG_OFFSET,
+    0,
+    0,
+    144,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXUCA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXMCA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXMCA_FIELDS[] =
+{
+    &LPORT_MIB_GTXMCA_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXMCA_REG = 
+{
+    "GTXMCA",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXMCA_REG_OFFSET,
+    0,
+    0,
+    145,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXMCA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXBCA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXBCA_FIELDS[] =
+{
+    &LPORT_MIB_GTXBCA_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXBCA_REG = 
+{
+    "GTXBCA",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXBCA_REG_OFFSET,
+    0,
+    0,
+    146,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXBCA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPF
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPF_FIELDS[] =
+{
+    &LPORT_MIB_GTXPF_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPF_REG = 
+{
+    "GTXPF",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPF_REG_OFFSET,
+    0,
+    0,
+    147,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPF_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPFC
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPFC_FIELDS[] =
+{
+    &LPORT_MIB_GTXPFC_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPFC_REG = 
+{
+    "GTXPFC",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPFC_REG_OFFSET,
+    0,
+    0,
+    148,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPFC_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXJBR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXJBR_FIELDS[] =
+{
+    &LPORT_MIB_GTXJBR_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXJBR_REG = 
+{
+    "GTXJBR",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXJBR_REG_OFFSET,
+    0,
+    0,
+    149,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXJBR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXFCS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXFCS_FIELDS[] =
+{
+    &LPORT_MIB_GTXFCS_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXFCS_REG = 
+{
+    "GTXFCS",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXFCS_REG_OFFSET,
+    0,
+    0,
+    150,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXFCS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXCF
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXCF_FIELDS[] =
+{
+    &LPORT_MIB_GTXCF_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXCF_REG = 
+{
+    "GTXCF",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXCF_REG_OFFSET,
+    0,
+    0,
+    151,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXCF_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXOVR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXOVR_FIELDS[] =
+{
+    &LPORT_MIB_GTXOVR_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXOVR_REG = 
+{
+    "GTXOVR",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXOVR_REG_OFFSET,
+    0,
+    0,
+    152,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXOVR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXDFR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXDFR_FIELDS[] =
+{
+    &LPORT_MIB_GTXDFR_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXDFR_REG = 
+{
+    "GTXDFR",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXDFR_REG_OFFSET,
+    0,
+    0,
+    153,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXDFR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXEDF
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXEDF_FIELDS[] =
+{
+    &LPORT_MIB_GTXEDF_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXEDF_REG = 
+{
+    "GTXEDF",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXEDF_REG_OFFSET,
+    0,
+    0,
+    154,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXEDF_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXSCL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXSCL_FIELDS[] =
+{
+    &LPORT_MIB_GTXSCL_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXSCL_REG = 
+{
+    "GTXSCL",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXSCL_REG_OFFSET,
+    0,
+    0,
+    155,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXSCL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXMCL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXMCL_FIELDS[] =
+{
+    &LPORT_MIB_GTXMCL_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXMCL_REG = 
+{
+    "GTXMCL",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXMCL_REG_OFFSET,
+    0,
+    0,
+    156,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXMCL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXLCL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXLCL_FIELDS[] =
+{
+    &LPORT_MIB_GTXLCL_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXLCL_REG = 
+{
+    "GTXLCL",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXLCL_REG_OFFSET,
+    0,
+    0,
+    157,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXLCL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXXCL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXXCL_FIELDS[] =
+{
+    &LPORT_MIB_GTXXCL_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXXCL_REG = 
+{
+    "GTXXCL",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXXCL_REG_OFFSET,
+    0,
+    0,
+    158,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXXCL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXFRG
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXFRG_FIELDS[] =
+{
+    &LPORT_MIB_GTXFRG_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXFRG_REG = 
+{
+    "GTXFRG",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXFRG_REG_OFFSET,
+    0,
+    0,
+    159,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXFRG_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXERR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXERR_FIELDS[] =
+{
+    &LPORT_MIB_GTXERR_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXERR_REG = 
+{
+    "GTXERR",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXERR_REG_OFFSET,
+    0,
+    0,
+    160,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXERR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXVLN
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXVLN_FIELDS[] =
+{
+    &LPORT_MIB_GTXVLN_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXVLN_REG = 
+{
+    "GTXVLN",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXVLN_REG_OFFSET,
+    0,
+    0,
+    161,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXVLN_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXDVLN
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXDVLN_FIELDS[] =
+{
+    &LPORT_MIB_GTXDVLN_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXDVLN_REG = 
+{
+    "GTXDVLN",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXDVLN_REG_OFFSET,
+    0,
+    0,
+    162,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXDVLN_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXRPKT
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXRPKT_FIELDS[] =
+{
+    &LPORT_MIB_GTXRPKT_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXRPKT_REG = 
+{
+    "GTXRPKT",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXRPKT_REG_OFFSET,
+    0,
+    0,
+    163,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXRPKT_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXUFL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXUFL_FIELDS[] =
+{
+    &LPORT_MIB_GTXUFL_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXUFL_REG = 
+{
+    "GTXUFL",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXUFL_REG_OFFSET,
+    0,
+    0,
+    164,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXUFL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPFCP0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPFCP0_FIELDS[] =
+{
+    &LPORT_MIB_GTXPFCP0_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPFCP0_REG = 
+{
+    "GTXPFCP0",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPFCP0_REG_OFFSET,
+    0,
+    0,
+    165,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPFCP0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPFCP1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPFCP1_FIELDS[] =
+{
+    &LPORT_MIB_GTXPFCP1_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPFCP1_REG = 
+{
+    "GTXPFCP1",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPFCP1_REG_OFFSET,
+    0,
+    0,
+    166,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPFCP1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPFCP2
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPFCP2_FIELDS[] =
+{
+    &LPORT_MIB_GTXPFCP2_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPFCP2_REG = 
+{
+    "GTXPFCP2",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPFCP2_REG_OFFSET,
+    0,
+    0,
+    167,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPFCP2_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPFCP3
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPFCP3_FIELDS[] =
+{
+    &LPORT_MIB_GTXPFCP3_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPFCP3_REG = 
+{
+    "GTXPFCP3",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPFCP3_REG_OFFSET,
+    0,
+    0,
+    168,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPFCP3_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPFCP4
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPFCP4_FIELDS[] =
+{
+    &LPORT_MIB_GTXPFCP4_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPFCP4_REG = 
+{
+    "GTXPFCP4",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPFCP4_REG_OFFSET,
+    0,
+    0,
+    169,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPFCP4_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPFCP5
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPFCP5_FIELDS[] =
+{
+    &LPORT_MIB_GTXPFCP5_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPFCP5_REG = 
+{
+    "GTXPFCP5",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPFCP5_REG_OFFSET,
+    0,
+    0,
+    170,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPFCP5_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPFCP6
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPFCP6_FIELDS[] =
+{
+    &LPORT_MIB_GTXPFCP6_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPFCP6_REG = 
+{
+    "GTXPFCP6",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPFCP6_REG_OFFSET,
+    0,
+    0,
+    171,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPFCP6_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXPFCP7
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXPFCP7_FIELDS[] =
+{
+    &LPORT_MIB_GTXPFCP7_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXPFCP7_REG = 
+{
+    "GTXPFCP7",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXPFCP7_REG_OFFSET,
+    0,
+    0,
+    172,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXPFCP7_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXNCL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXNCL_FIELDS[] =
+{
+    &LPORT_MIB_GTXNCL_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXNCL_REG = 
+{
+    "GTXNCL",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXNCL_REG_OFFSET,
+    0,
+    0,
+    173,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXNCL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXBYT
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXBYT_FIELDS[] =
+{
+    &LPORT_MIB_GTXBYT_COUNT48_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXBYT_REG = 
+{
+    "GTXBYT",
+#if RU_INCLUDE_DESC
+    "Transmit Byte Counter for XLMAC0/port0 (LPORT port0)",
+    "Receive Byte Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 48 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (47:32)."
+    "Receive Runt Byte Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 48 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (47:32)."
+    "Transmit Byte Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 48 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (47:32).",
+#endif
+    LPORT_MIB_GTXBYT_REG_OFFSET,
+    0,
+    0,
+    174,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXBYT_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXLPI
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXLPI_FIELDS[] =
+{
+    &LPORT_MIB_GRXLPI_COUNT32_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXLPI_REG = 
+{
+    "GRXLPI",
+#if RU_INCLUDE_DESC
+    "TX EEE LPI Duration Counter for XLMAC0/port0 (LPORT port0)",
+    "RX EEE LPI Event Counter"
+    "RX EEE LPI Duration Counter"
+    "TX EEE LPI Event Counter"
+    "TX EEE LPI Duration Counter",
+#endif
+    LPORT_MIB_GRXLPI_REG_OFFSET,
+    0,
+    0,
+    175,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXLPI_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXDLPI
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXDLPI_FIELDS[] =
+{
+    &LPORT_MIB_GRXDLPI_COUNT32_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXDLPI_REG = 
+{
+    "GRXDLPI",
+#if RU_INCLUDE_DESC
+    "TX EEE LPI Duration Counter for XLMAC0/port0 (LPORT port0)",
+    "RX EEE LPI Event Counter"
+    "RX EEE LPI Duration Counter"
+    "TX EEE LPI Event Counter"
+    "TX EEE LPI Duration Counter",
+#endif
+    LPORT_MIB_GRXDLPI_REG_OFFSET,
+    0,
+    0,
+    176,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXDLPI_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXLPI
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXLPI_FIELDS[] =
+{
+    &LPORT_MIB_GTXLPI_COUNT32_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXLPI_REG = 
+{
+    "GTXLPI",
+#if RU_INCLUDE_DESC
+    "TX EEE LPI Duration Counter for XLMAC0/port0 (LPORT port0)",
+    "RX EEE LPI Event Counter"
+    "RX EEE LPI Duration Counter"
+    "TX EEE LPI Event Counter"
+    "TX EEE LPI Duration Counter",
+#endif
+    LPORT_MIB_GTXLPI_REG_OFFSET,
+    0,
+    0,
+    177,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXLPI_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXDLPI
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXDLPI_FIELDS[] =
+{
+    &LPORT_MIB_GTXDLPI_COUNT32_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXDLPI_REG = 
+{
+    "GTXDLPI",
+#if RU_INCLUDE_DESC
+    "TX EEE LPI Duration Counter for XLMAC0/port0 (LPORT port0)",
+    "RX EEE LPI Event Counter"
+    "RX EEE LPI Duration Counter"
+    "TX EEE LPI Event Counter"
+    "TX EEE LPI Duration Counter",
+#endif
+    LPORT_MIB_GTXDLPI_REG_OFFSET,
+    0,
+    0,
+    178,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXDLPI_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXPTLLFC
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXPTLLFC_FIELDS[] =
+{
+    &LPORT_MIB_GRXPTLLFC_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXPTLLFC_REG = 
+{
+    "GRXPTLLFC",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXPTLLFC_REG_OFFSET,
+    0,
+    0,
+    179,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXPTLLFC_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXLTLLFC
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXLTLLFC_FIELDS[] =
+{
+    &LPORT_MIB_GRXLTLLFC_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXLTLLFC_REG = 
+{
+    "GRXLTLLFC",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXLTLLFC_REG_OFFSET,
+    0,
+    0,
+    180,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXLTLLFC_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GRXLLFCFCS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GRXLLFCFCS_FIELDS[] =
+{
+    &LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GRXLLFCFCS_REG = 
+{
+    "GRXLLFCFCS",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GRXLLFCFCS_REG_OFFSET,
+    0,
+    0,
+    181,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GRXLLFCFCS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_MIB_GTXLTLLFC
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_MIB_GTXLTLLFC_FIELDS[] =
+{
+    &LPORT_MIB_GTXLTLLFC_COUNT40_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_MIB_GTXLTLLFC_REG = 
+{
+    "GTXLTLLFC",
+#if RU_INCLUDE_DESC
+    "Transmit Logical Type LLFC message counter for XLMAC0/port0 (LPORT port0)",
+    "Receive 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive 9217 to 16838 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive frame/packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive FCS Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PAUSE Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC (Per-Priority Pause) Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported Opcode Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Unsupported DA for PAUSE/PFC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Wrong SA Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Alignment Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Length Out of Range Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Code Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive False Carrier Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Oversized Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Jabber Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive MTU Check Error Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Matched CRC Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Promiscuous Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Truncated Frame Counter (due to RX FIFO full)\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0 XON to XOFF\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive SCH CRC Error\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Undersize Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 64 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 65 to 127 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 128 to 255 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 256 to 511 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 512 to 1023 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1024 to 1518 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 1522 Byte Good VLAN Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 1519 to 2047 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 2048 to 4095 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 4096 to 9216 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit 9217 to 16383 Byte Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Good Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Packet/Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Unicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multicast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Broadcast Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC/Per-Priority Pause Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Jabber Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FCS Error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Control Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Oversize Packet Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Deferral Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Single Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Multiple Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Late Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Excessive Collision Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Fragment Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Error (set by system) Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Double VLAN Tag Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit RUNT Frame Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit FIFO Underrun Counter.\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 0\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 1\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 2\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 3\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 4\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 5\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 6\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit PFC Frame Priority 7\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Total Collision Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Physical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Logical Type LLFC message Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Receive Type LLFC message with CRC error Counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32)."
+    "Transmit Logical Type LLFC message counter\n"
+    "\n"
+    "IMPORTANT: This MIB counter is 40 bits wide (which is more than 32 bits).\n"
+    "See Description on how to access the higher counter bits (39:32).",
+#endif
+    LPORT_MIB_GTXLTLLFC_REG_OFFSET,
+    0,
+    0,
+    182,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_MIB_GTXLTLLFC_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Block: LPORT_MIB
+ ******************************************************************************/
+static const ru_reg_rec *LPORT_MIB_REGS[] =
+{
+    &LPORT_MIB_GRX64_REG,
+    &LPORT_MIB_GRX127_REG,
+    &LPORT_MIB_GRX255_REG,
+    &LPORT_MIB_GRX511_REG,
+    &LPORT_MIB_GRX1023_REG,
+    &LPORT_MIB_GRX1518_REG,
+    &LPORT_MIB_GRX1522_REG,
+    &LPORT_MIB_GRX2047_REG,
+    &LPORT_MIB_GRX4095_REG,
+    &LPORT_MIB_GRX9216_REG,
+    &LPORT_MIB_GRX16383_REG,
+    &LPORT_MIB_GRXPKT_REG,
+    &LPORT_MIB_GRXUCA_REG,
+    &LPORT_MIB_GRXMCA_REG,
+    &LPORT_MIB_GRXBCA_REG,
+    &LPORT_MIB_GRXFCS_REG,
+    &LPORT_MIB_GRXCF_REG,
+    &LPORT_MIB_GRXPF_REG,
+    &LPORT_MIB_GRXPP_REG,
+    &LPORT_MIB_GRXUO_REG,
+    &LPORT_MIB_GRXUDA_REG,
+    &LPORT_MIB_GRXWSA_REG,
+    &LPORT_MIB_GRXALN_REG,
+    &LPORT_MIB_GRXFLR_REG,
+    &LPORT_MIB_GRXFRERR_REG,
+    &LPORT_MIB_GRXFCR_REG,
+    &LPORT_MIB_GRXOVR_REG,
+    &LPORT_MIB_GRXJBR_REG,
+    &LPORT_MIB_GRXMTUE_REG,
+    &LPORT_MIB_GRXMCRC_REG,
+    &LPORT_MIB_GRXPRM_REG,
+    &LPORT_MIB_GRXVLN_REG,
+    &LPORT_MIB_GRXDVLN_REG,
+    &LPORT_MIB_GRXTRFU_REG,
+    &LPORT_MIB_GRXPOK_REG,
+    &LPORT_MIB_GRXPFCOFF0_REG,
+    &LPORT_MIB_GRXPFCOFF1_REG,
+    &LPORT_MIB_GRXPFCOFF2_REG,
+    &LPORT_MIB_GRXPFCOFF3_REG,
+    &LPORT_MIB_GRXPFCOFF4_REG,
+    &LPORT_MIB_GRXPFCOFF5_REG,
+    &LPORT_MIB_GRXPFCOFF6_REG,
+    &LPORT_MIB_GRXPFCOFF7_REG,
+    &LPORT_MIB_GRXPFCP0_REG,
+    &LPORT_MIB_GRXPFCP1_REG,
+    &LPORT_MIB_GRXPFCP2_REG,
+    &LPORT_MIB_GRXPFCP3_REG,
+    &LPORT_MIB_GRXPFCP4_REG,
+    &LPORT_MIB_GRXPFCP5_REG,
+    &LPORT_MIB_GRXPFCP6_REG,
+    &LPORT_MIB_GRXPFCP7_REG,
+    &LPORT_MIB_GRXSCHCRC_REG,
+    &LPORT_MIB_GRXBYT_REG,
+    &LPORT_MIB_GRXRPKT_REG,
+    &LPORT_MIB_GRXUND_REG,
+    &LPORT_MIB_GRXFRG_REG,
+    &LPORT_MIB_GRXRBYT_REG,
+    &LPORT_MIB_GTX64_REG,
+    &LPORT_MIB_GTX127_REG,
+    &LPORT_MIB_GTX255_REG,
+    &LPORT_MIB_GTX511_REG,
+    &LPORT_MIB_GTX1023_REG,
+    &LPORT_MIB_GTX1518_REG,
+    &LPORT_MIB_GTX1522_REG,
+    &LPORT_MIB_GTX2047_REG,
+    &LPORT_MIB_GTX4095_REG,
+    &LPORT_MIB_GTX9216_REG,
+    &LPORT_MIB_GTX16383_REG,
+    &LPORT_MIB_GTXPOK_REG,
+    &LPORT_MIB_GTXPKT_REG,
+    &LPORT_MIB_GTXUCA_REG,
+    &LPORT_MIB_GTXMCA_REG,
+    &LPORT_MIB_GTXBCA_REG,
+    &LPORT_MIB_GTXPF_REG,
+    &LPORT_MIB_GTXPFC_REG,
+    &LPORT_MIB_GTXJBR_REG,
+    &LPORT_MIB_GTXFCS_REG,
+    &LPORT_MIB_GTXCF_REG,
+    &LPORT_MIB_GTXOVR_REG,
+    &LPORT_MIB_GTXDFR_REG,
+    &LPORT_MIB_GTXEDF_REG,
+    &LPORT_MIB_GTXSCL_REG,
+    &LPORT_MIB_GTXMCL_REG,
+    &LPORT_MIB_GTXLCL_REG,
+    &LPORT_MIB_GTXXCL_REG,
+    &LPORT_MIB_GTXFRG_REG,
+    &LPORT_MIB_GTXERR_REG,
+    &LPORT_MIB_GTXVLN_REG,
+    &LPORT_MIB_GTXDVLN_REG,
+    &LPORT_MIB_GTXRPKT_REG,
+    &LPORT_MIB_GTXUFL_REG,
+    &LPORT_MIB_GTXPFCP0_REG,
+    &LPORT_MIB_GTXPFCP1_REG,
+    &LPORT_MIB_GTXPFCP2_REG,
+    &LPORT_MIB_GTXPFCP3_REG,
+    &LPORT_MIB_GTXPFCP4_REG,
+    &LPORT_MIB_GTXPFCP5_REG,
+    &LPORT_MIB_GTXPFCP6_REG,
+    &LPORT_MIB_GTXPFCP7_REG,
+    &LPORT_MIB_GTXNCL_REG,
+    &LPORT_MIB_GTXBYT_REG,
+    &LPORT_MIB_GRXLPI_REG,
+    &LPORT_MIB_GRXDLPI_REG,
+    &LPORT_MIB_GTXLPI_REG,
+    &LPORT_MIB_GTXDLPI_REG,
+    &LPORT_MIB_GRXPTLLFC_REG,
+    &LPORT_MIB_GRXLTLLFC_REG,
+    &LPORT_MIB_GRXLLFCFCS_REG,
+    &LPORT_MIB_GTXLTLLFC_REG,
+};
+
+unsigned long LPORT_MIB_ADDRS[] =
+{
+    0x80139000,
+    0x80139400,
+    0x80139800,
+    0x80139c00,
+    0x8013b000,
+    0x8013b400,
+    0x8013b800,
+    0x8013bc00,
+};
+
+const ru_block_rec LPORT_MIB_BLOCK = 
+{
+    "LPORT_MIB",
+    LPORT_MIB_ADDRS,
+    8,
+    109,
+    LPORT_MIB_REGS
+};
+
+/* End of file BCM6858_A0LPORT_MIB.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_RGMII_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_RGMII_AG.c
new file mode 100644
index 0000000000..5370ef63b9
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_RGMII_AG.c
@@ -0,0 +1,2528 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+#if RU_INCLUDE_FIELD_DB
+/******************************************************************************
+ * Field: LPORT_RGMII_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_CNTRL_COL_CRS_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD =
+{
+    "COL_CRS_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "When this bit is set to 1'''b1, COL signal toward the MAC is 1'''b0 and CRS signal toward the MAC is 1'''b1.\n"
+    "Applicable to MII/rvMII interfaces and used in case where link partner does not support COL/CRS or the link is full-duplex. "
+    "Note that as per IEEE 802.3 MACs ignore COL/CRS in full-duplex mode and therefore it is not necessary required to set this bit.",
+#endif
+    LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD_MASK,
+    0,
+    LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD_WIDTH,
+    LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_CNTRL_RX_ERR_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD =
+{
+    "RX_ERR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "When this bit is set to 1'''b1, RX_ERR signal toward the MAC is 1'''b0 (i.e. no error). "
+    "Applicable to MII/rvMII interfaces and used in case where link partner does not support RX_ERR.",
+#endif
+    LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD_MASK,
+    0,
+    LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD_WIDTH,
+    LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_CNTRL_LPI_COUNT
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_CNTRL_LPI_COUNT_FIELD =
+{
+    "LPI_COUNT",
+#if RU_INCLUDE_DESC
+    "",
+    "Specifies number of cycles after which TX_CLK will be stopped (after LPI is asserted), "
+    "if the clock stopping is enabled.",
+#endif
+    LPORT_RGMII_CNTRL_LPI_COUNT_FIELD_MASK,
+    0,
+    LPORT_RGMII_CNTRL_LPI_COUNT_FIELD_WIDTH,
+    LPORT_RGMII_CNTRL_LPI_COUNT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_CNTRL_TX_CLK_STOP_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD =
+{
+    "TX_CLK_STOP_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set enables stopping TX_CLK after LPI is asserted. "
+    "This bit should be set only when the connected EEE PHY supports it.",
+#endif
+    LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD_WIDTH,
+    LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_CNTRL_TX_PAUSE_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD =
+{
+    "TX_PAUSE_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "Tx Pause as negotiated by the attached PHY. Obtained by SW via MDIO.",
+#endif
+    LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD_WIDTH,
+    LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_CNTRL_RX_PAUSE_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD =
+{
+    "RX_PAUSE_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "Rx Pause as negotiated by the attached PHY. Obtained by SW via MDIO.",
+#endif
+    LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD_WIDTH,
+    LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_CNTRL_RVMII_REF_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD =
+{
+    "RVMII_REF_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "Selects clock in RvMII mode.\n"
+    "0 : RvMII reference clock is 50MHz.\n"
+    "1 : RvMII reference clock is 25MHz.",
+#endif
+    LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD_WIDTH,
+    LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_CNTRL_PORT_MODE
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_CNTRL_PORT_MODE_FIELD =
+{
+    "PORT_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "Port Mode encoded as:\n"
+    "000 : Internal EPHY (MII).\n"
+    "001 : Internal GPHY (GMII/MII).\n"
+    "010 : External EPHY (MII).\n"
+    "011 : External GPHY (RGMII).\n"
+    "100 : External RvMII.\n"
+    "Not all combinations are applicable to all chips.",
+#endif
+    LPORT_RGMII_CNTRL_PORT_MODE_FIELD_MASK,
+    0,
+    LPORT_RGMII_CNTRL_PORT_MODE_FIELD_WIDTH,
+    LPORT_RGMII_CNTRL_PORT_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_CNTRL_ID_MODE_DIS
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD =
+{
+    "ID_MODE_DIS",
+#if RU_INCLUDE_DESC
+    "",
+    "RGMII Internal Delay (ID) mode disable.\n"
+    "When set RGMII transmit clock edges are aligned with the data.\n"
+    "When cleared RGMII transmit clock edges are centered in the middle of (transmit) data valid window.",
+#endif
+    LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD_MASK,
+    0,
+    LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD_WIDTH,
+    LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_CNTRL_RGMII_MODE_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD =
+{
+    "RGMII_MODE_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set this bit enables RGMII interface. "
+    "This bit acts as a reset for RGMII block abd therefore it can be used to reset RGMII block when needed.",
+#endif
+    LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD_WIDTH,
+    LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_IB_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_IB_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_IB_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_IB_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_IB_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD =
+{
+    "IB_STATUS_OVRD",
+#if RU_INCLUDE_DESC
+    "",
+    "When this bit is set, RGMII in-band status can be overridden by bits [3:0] of this register by SW.",
+#endif
+    LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD_MASK,
+    0,
+    LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD_WIDTH,
+    LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_IB_STATUS_LINK_DECODE
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD =
+{
+    "LINK_DECODE",
+#if RU_INCLUDE_DESC
+    "",
+    "RGMII link indication as extracted from in-band signaling.\n"
+    "1 : Link Up.\n"
+    "0 : Link Down.",
+#endif
+    LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD_MASK,
+    0,
+    LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD_WIDTH,
+    LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_IB_STATUS_DUPLEX_DECODE
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD =
+{
+    "DUPLEX_DECODE",
+#if RU_INCLUDE_DESC
+    "",
+    "RGMII duplex mode as extracted from in-band signaling.\n"
+    "1 : Full Duplex.\n"
+    "0 : Half Duplex.",
+#endif
+    LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD_MASK,
+    0,
+    LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD_WIDTH,
+    LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_IB_STATUS_SPEED_DECODE
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD =
+{
+    "SPEED_DECODE",
+#if RU_INCLUDE_DESC
+    "",
+    "RGMII operating speed as extracted from in-band signaling.\n"
+    "00 : 10Mbp/s.\n"
+    "01 : 100Mbp/s.\n"
+    "10 : 1000Mbp/s.\n"
+    "11 : reserved.",
+#endif
+    LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD_MASK,
+    0,
+    LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD_WIDTH,
+    LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD =
+{
+    "RESET",
+#if RU_INCLUDE_DESC
+    "",
+    "When set it resets 2ns delay line.",
+#endif
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD_WIDTH,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD =
+{
+    "DLY_OVERRIDE",
+#if RU_INCLUDE_DESC
+    "",
+    "Overrides HW selected delay.",
+#endif
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_WIDTH,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD =
+{
+    "DLY_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "When set delay line delay is ~2ns and when cleared delay line is > 2.2ns. Valid only when DLY_OVERRIDE bit is set.",
+#endif
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD =
+{
+    "BYPASS",
+#if RU_INCLUDE_DESC
+    "",
+    "When set it puts 2ns delay line in bypass mode (default). This bit should be cleared only in non-ID mode.",
+#endif
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_WIDTH,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD =
+{
+    "IDDQ",
+#if RU_INCLUDE_DESC
+    "",
+    "When set puts 2ns delay line in IDDQ mode."
+    "Requires HW reset (see bit 8 of this register) to bring 2ns delay line from power down.",
+#endif
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_WIDTH,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD =
+{
+    "DRNG",
+#if RU_INCLUDE_DESC
+    "",
+    "VCDL control. Contact BRCM for more information",
+#endif
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_WIDTH,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD =
+{
+    "CTRI",
+#if RU_INCLUDE_DESC
+    "",
+    "Charge pump current control. Contact BRCM for more information",
+#endif
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_WIDTH,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD =
+{
+    "ATE_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set enables ATE testing",
+#endif
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD =
+{
+    "PKT_COUNT_RST",
+#if RU_INCLUDE_DESC
+    "",
+    "When set resets received packets counter. Used only in packet generation mode (PKT_GEN_MODE bit is set).",
+#endif
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD =
+{
+    "GOOD_COUNT",
+#if RU_INCLUDE_DESC
+    "",
+    "Count that specifies how many consecutive {EXPECTED_DATA_0, EXPECTED_DATA_1, EXPECTED_DATA_2, EXPECTED_DATA_3 } patterns should be received before RX_OK signal is asserted.\n"
+    " In packet generation mode it specifies number of expected packets.",
+#endif
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD =
+{
+    "EXPECTED_DATA_1",
+#if RU_INCLUDE_DESC
+    "",
+    "Data expected on the odd rising edge of the RXC clock on the RGMII Rx interface. Bits[12:9] of this register are used only in MII modes and they represent RXD[3:0]. Bit 17 corresponds RX_ER.\n"
+    "Not used in Packet Generation mode.",
+#endif
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD =
+{
+    "EXPECTED_DATA_0",
+#if RU_INCLUDE_DESC
+    "",
+    "Data expected on the even rising edge of the RXC clock on the RGMII Rx interface. Bits[3:0] of this register are used only in MII modes and they represent RXD[3:0]. Bit 8 corresponds RX_ER.\n"
+    "Not used in Packet Generation mode.",
+#endif
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD =
+{
+    "EXPECTED_DATA_3",
+#if RU_INCLUDE_DESC
+    "",
+    "Data expected on the odd rising edge of the RXC clock on the RGMII Rx interface. Bits[12:9] of this register are used only in MII modes and they represent RXD[3:0]. Bit 17 corresponds RX_ER.\n"
+    "Not used in Packet Generation mode.",
+#endif
+    LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD =
+{
+    "EXPECTED_DATA_2",
+#if RU_INCLUDE_DESC
+    "",
+    "Data expected on the even rising edge of the RXC clock on the RGMII Rx interface. Bits[3:0] of this register are used only in MII modes and they represent RXD[3:0]. Bit 8 corresponds RX_ER.\n"
+    "Not used in Packet Generation mode.",
+#endif
+    LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_STATUS_0_RX_OK
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD =
+{
+    "RX_OK",
+#if RU_INCLUDE_DESC
+    "",
+    "Test Status. This bit is cleared by HW on the rising edge of RX_CTL and asserted if GOOD_COUNT consective expected patterns are detected.\n"
+    "In packet generation mode this bit is cleared when PKT_COUNT_RST bit is set and set when received packet count = GOOD_COUNT. ",
+#endif
+    LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD =
+{
+    "RECEIVED_DATA_1",
+#if RU_INCLUDE_DESC
+    "",
+    "Data received on the odd rising edge of the RXC clock on the RGMII Rx interface. In MII modes, only Bits[12:9] of this register are used only for RXD[3:0]. Bit[17]: RX_ER\n"
+    "In Packet Generation mode bits [7:0] are 2nd received byte after SOF.",
+#endif
+    LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD =
+{
+    "RECEIVED_DATA_0",
+#if RU_INCLUDE_DESC
+    "",
+    "Data received on the even rising edge of the RXC clock on the RGMII Rx interface. In MII modes, only Bits[3:0] of this register are used only for RXD[3:0]. Bit[8]: RX_ER\n"
+    "In Packet Generation mode bits [7:0] are 1st received byte after SOF.",
+#endif
+    LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD =
+{
+    "RECEIVED_DATA_3",
+#if RU_INCLUDE_DESC
+    "",
+    "Data received on the odd rising edge of the RXC clock on the RGMII Rx interface. In MII modes, only Bits[12:9] of this register are used only for RXD[3:0]. Bit[17]: RX_ER\n"
+    "In Packet Generation mode bits [7:0] are 4th received byte after SOF.",
+#endif
+    LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD =
+{
+    "RECEIVED_DATA_2",
+#if RU_INCLUDE_DESC
+    "",
+    "Data received on the even rising edge of the RXC clock on the RGMII Rx interface. In MII modes, only Bits[3:0] of this register are used only for RXD[3:0]. Bit[8]: RX_ER\n"
+    "In Packet Generation mode bits [7:0] are 3rd received byte after SOF.",
+#endif
+    LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_WIDTH,
+    LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD =
+{
+    "PKT_IPG",
+#if RU_INCLUDE_DESC
+    "",
+    "Inter-packet gap in packet generation mode.",
+#endif
+    LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD =
+{
+    "PAYLOAD_LENGTH",
+#if RU_INCLUDE_DESC
+    "",
+    "Generated packet payload in bytes. Must be between 46B and 1500B.",
+#endif
+    LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD =
+{
+    "PKT_CNT",
+#if RU_INCLUDE_DESC
+    "",
+    "Number of packets generated when START_STOP bit is set.  When program to 0 it means infinite number of packets will be transmit (i.e. until START_STOP is cleared). ",
+#endif
+    LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD =
+{
+    "PKT_GEN_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When this bit is set ATE test logic operates in the packet generation mode.",
+#endif
+    LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_CNTRL_START_STOP
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD =
+{
+    "START_STOP",
+#if RU_INCLUDE_DESC
+    "",
+    "start_stop. When set transmit state matchin starts outputing programmed pattern over RGMII TX interface. When cleared transmit state machine stops outputting data.",
+#endif
+    LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD =
+{
+    "START_STOP_OVRD",
+#if RU_INCLUDE_DESC
+    "",
+    "START_STOP override. When this bit is set, transmit state machine will be controlled by START_STOP bit of this register instead of the chip pin.",
+#endif
+    LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_DATA_0_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD =
+{
+    "TX_DATA_1",
+#if RU_INCLUDE_DESC
+    "",
+    "Data transmitted on the odd rising edge of the TXC clock on the RGMII Tx interface. In case of MII, only bit[12:9] are used to transmit TXD[3:0]. Bit 17: TX_ER\n"
+    "In Packet Generation mode bits [7:0] are 2nd byte of MAC DA.",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD =
+{
+    "TX_DATA_0",
+#if RU_INCLUDE_DESC
+    "",
+    "Data transmitted on the even rising edge of the TXC clock on the RGMII Tx interface. In case of MII, only bit[3:0] are used to transmit TXD[3:0]. Bit 8: TX_ER\n"
+    "In Packet Generation mode bits [7:0] are 1st byte of MAC DA.",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_DATA_1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD =
+{
+    "TX_DATA_3",
+#if RU_INCLUDE_DESC
+    "",
+    "Data transmitted on the odd rising edge of the TXC clock on the RGMII Tx interface. In case of MII, only bit[12:9] are used to transmit TXD[3:0]. Bit 17: TX_ER\n"
+    "In Packet Generation mode bits [7:0] are 4th byte of MAC DA.",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD =
+{
+    "TX_DATA_2",
+#if RU_INCLUDE_DESC
+    "",
+    "Data transmitted on the even rising edge of the TXC clock on the RGMII Tx interface. In case of MII, only bit[3:0] are used to transmit TXD[3:0]. Bit 8: TX_ER\n"
+    "In Packet Generation mode bits [7:0] are 3rd byte of MAC DA.",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD =
+{
+    "ETHER_TYPE",
+#if RU_INCLUDE_DESC
+    "",
+    "Generated packet Ethertype",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD =
+{
+    "TX_DATA_5",
+#if RU_INCLUDE_DESC
+    "",
+    "In Packet Generation mode bits [7:0] are 6th byte of MAC DA",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD =
+{
+    "TX_DATA_4",
+#if RU_INCLUDE_DESC
+    "",
+    "In Packet Generation mode bits [7:0] are 5th byte of MAC DA.",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD_MASK,
+    0,
+    LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD_WIDTH,
+    LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD =
+{
+    "TXD3_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "txd3 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD =
+{
+    "TXD3_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "txd3 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD =
+{
+    "TXD2_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "txd2 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD =
+{
+    "TXD2_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "txd2 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD =
+{
+    "TXD1_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "txd1 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD =
+{
+    "TXD1_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "txd1 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD =
+{
+    "TXD0_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "txd0 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD =
+{
+    "TXD0_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "txd0 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD =
+{
+    "TXCLK_ID_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "txclk ID mode CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD =
+{
+    "TXCLK_ID_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "txclk ID mode CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD =
+{
+    "TXCLK_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "txclk NON_ID mode CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD =
+{
+    "TXCLK_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "txclk NON-ID mode CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD =
+{
+    "TXCTL_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "txctl CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD =
+{
+    "TXCTL_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "txctl CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD =
+{
+    "RXD3_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd3 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD =
+{
+    "RXD3_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd3 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD =
+{
+    "RXD2_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd2 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD =
+{
+    "RXD2_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd2 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD =
+{
+    "RXD1_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd1 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD =
+{
+    "RXD1_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd1 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD =
+{
+    "RXD0_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd0 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD =
+{
+    "RXD0_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd0 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD =
+{
+    "RXD7_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd7 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD =
+{
+    "RXD7_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd7 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD =
+{
+    "RXD6_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd6 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD =
+{
+    "RXD6_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd6 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD =
+{
+    "RXD5_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd5 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD =
+{
+    "RXD5_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd5 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD =
+{
+    "RXD4_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd4 CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD =
+{
+    "RXD4_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "rxd4 CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD =
+{
+    "RXCLK_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "rxclk CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD =
+{
+    "RXCLK_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "rxclk CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD =
+{
+    "RXCTL_NEG_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "rxctl_neg CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD =
+{
+    "RXCTL_NEG_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "rxctl_neg CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD =
+{
+    "RXCTL_POS_DEL_OVRD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "rxctl_pos CKTAP delay override enable. When set enables CKTAP delay to be controlled from this register.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL
+ ******************************************************************************/
+const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD =
+{
+    "RXCTL_POS_DEL_SEL",
+#if RU_INCLUDE_DESC
+    "",
+    "rxctl_pos CKTAP delay control. Refer to the CKTAP datasheet for programming.",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_MASK,
+    0,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_WIDTH,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+/******************************************************************************
+ * Register: LPORT_RGMII_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_CNTRL_FIELDS[] =
+{
+    &LPORT_RGMII_CNTRL_RESERVED0_FIELD,
+    &LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD,
+    &LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD,
+    &LPORT_RGMII_CNTRL_LPI_COUNT_FIELD,
+    &LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD,
+    &LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD,
+    &LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD,
+    &LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD,
+    &LPORT_RGMII_CNTRL_PORT_MODE_FIELD,
+    &LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD,
+    &LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_CNTRL_REG = 
+{
+    "CNTRL",
+#if RU_INCLUDE_DESC
+    "RGMII port 2 Control Register",
+    "",
+#endif
+    LPORT_RGMII_CNTRL_REG_OFFSET,
+    0,
+    0,
+    213,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    11,
+    LPORT_RGMII_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_IB_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_IB_STATUS_FIELDS[] =
+{
+    &LPORT_RGMII_IB_STATUS_RESERVED0_FIELD,
+    &LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD,
+    &LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD,
+    &LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD,
+    &LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_IB_STATUS_REG = 
+{
+    "IB_STATUS",
+#if RU_INCLUDE_DESC
+    "RGMII port 2 InBand Status Register",
+    "",
+#endif
+    LPORT_RGMII_IB_STATUS_REG_OFFSET,
+    0,
+    0,
+    214,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_RGMII_IB_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_RX_CLOCK_DELAY_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_FIELDS[] =
+{
+    &LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD,
+    &LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD,
+    &LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD,
+    &LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD,
+    &LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD,
+    &LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD,
+    &LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD,
+    &LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_REG = 
+{
+    "RX_CLOCK_DELAY_CNTRL",
+#if RU_INCLUDE_DESC
+    "RGMII port 2 RX Clock Delay Control Register",
+    "",
+#endif
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_REG_OFFSET,
+    0,
+    0,
+    215,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    8,
+    LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_FIELDS[] =
+{
+    &LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD,
+    &LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD,
+    &LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD,
+    &LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD,
+    &LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD,
+    &LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_REG = 
+{
+    "ATE_RX_CNTRL_EXP_DATA",
+#if RU_INCLUDE_DESC
+    "RGMII port 2 ATE RX Control and Expected Data Register",
+    "",
+#endif
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_REG_OFFSET,
+    0,
+    0,
+    216,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_ATE_RX_EXP_DATA_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_ATE_RX_EXP_DATA_1_FIELDS[] =
+{
+    &LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD,
+    &LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD,
+    &LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_REG = 
+{
+    "ATE_RX_EXP_DATA_1",
+#if RU_INCLUDE_DESC
+    "RGMII port 2 ATE RX Expected Data 1 Register",
+    "",
+#endif
+    LPORT_RGMII_ATE_RX_EXP_DATA_1_REG_OFFSET,
+    0,
+    0,
+    217,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_RGMII_ATE_RX_EXP_DATA_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_ATE_RX_STATUS_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_ATE_RX_STATUS_0_FIELDS[] =
+{
+    &LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD,
+    &LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD,
+    &LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD,
+    &LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_ATE_RX_STATUS_0_REG = 
+{
+    "ATE_RX_STATUS_0",
+#if RU_INCLUDE_DESC
+    "RGMII port 2 ATE RX Status 0 Register",
+    "",
+#endif
+    LPORT_RGMII_ATE_RX_STATUS_0_REG_OFFSET,
+    0,
+    0,
+    218,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    4,
+    LPORT_RGMII_ATE_RX_STATUS_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_ATE_RX_STATUS_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_ATE_RX_STATUS_1_FIELDS[] =
+{
+    &LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD,
+    &LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD,
+    &LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_ATE_RX_STATUS_1_REG = 
+{
+    "ATE_RX_STATUS_1",
+#if RU_INCLUDE_DESC
+    "RGMII port 2 ATE RX Status 1 Register",
+    "",
+#endif
+    LPORT_RGMII_ATE_RX_STATUS_1_REG_OFFSET,
+    0,
+    0,
+    219,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_RGMII_ATE_RX_STATUS_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_ATE_TX_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_ATE_TX_CNTRL_FIELDS[] =
+{
+    &LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD,
+    &LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD,
+    &LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD,
+    &LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD,
+    &LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD,
+    &LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD,
+    &LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_ATE_TX_CNTRL_REG = 
+{
+    "ATE_TX_CNTRL",
+#if RU_INCLUDE_DESC
+    "RGMII port 2 ATE TX Control Register",
+    "",
+#endif
+    LPORT_RGMII_ATE_TX_CNTRL_REG_OFFSET,
+    0,
+    0,
+    220,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_RGMII_ATE_TX_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_ATE_TX_DATA_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_ATE_TX_DATA_0_FIELDS[] =
+{
+    &LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD,
+    &LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD,
+    &LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_ATE_TX_DATA_0_REG = 
+{
+    "ATE_TX_DATA_0",
+#if RU_INCLUDE_DESC
+    "RGMII port 2 ATE TX Data 0 Register",
+    "",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_0_REG_OFFSET,
+    0,
+    0,
+    221,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_RGMII_ATE_TX_DATA_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_ATE_TX_DATA_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_ATE_TX_DATA_1_FIELDS[] =
+{
+    &LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD,
+    &LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD,
+    &LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_ATE_TX_DATA_1_REG = 
+{
+    "ATE_TX_DATA_1",
+#if RU_INCLUDE_DESC
+    "RGMII port 2 ATE TX Data 1 Register",
+    "",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_1_REG_OFFSET,
+    0,
+    0,
+    222,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_RGMII_ATE_TX_DATA_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_ATE_TX_DATA_2
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_ATE_TX_DATA_2_FIELDS[] =
+{
+    &LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD,
+    &LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD,
+    &LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_ATE_TX_DATA_2_REG = 
+{
+    "ATE_TX_DATA_2",
+#if RU_INCLUDE_DESC
+    "RGMII port 2 ATE TX Data 2 Register",
+    "",
+#endif
+    LPORT_RGMII_ATE_TX_DATA_2_REG_OFFSET,
+    0,
+    0,
+    223,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_RGMII_ATE_TX_DATA_2_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_TX_DELAY_CNTRL_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_TX_DELAY_CNTRL_0_FIELDS[] =
+{
+    &LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_TX_DELAY_CNTRL_0_REG = 
+{
+    "TX_DELAY_CNTRL_0",
+#if RU_INCLUDE_DESC
+    "RGMII Append 2 TX Delay Control 0 Register",
+    "",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_0_REG_OFFSET,
+    0,
+    0,
+    224,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    LPORT_RGMII_TX_DELAY_CNTRL_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_TX_DELAY_CNTRL_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_TX_DELAY_CNTRL_1_FIELDS[] =
+{
+    &LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_TX_DELAY_CNTRL_1_REG = 
+{
+    "TX_DELAY_CNTRL_1",
+#if RU_INCLUDE_DESC
+    "RGMII Append 2 TX Delay Control 1 Register",
+    "",
+#endif
+    LPORT_RGMII_TX_DELAY_CNTRL_1_REG_OFFSET,
+    0,
+    0,
+    225,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_RGMII_TX_DELAY_CNTRL_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_RX_DELAY_CNTRL_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_RX_DELAY_CNTRL_0_FIELDS[] =
+{
+    &LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_RX_DELAY_CNTRL_0_REG = 
+{
+    "RX_DELAY_CNTRL_0",
+#if RU_INCLUDE_DESC
+    "RGMII Append 2 RX Delay Control 0 Register",
+    "",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_0_REG_OFFSET,
+    0,
+    0,
+    226,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    LPORT_RGMII_RX_DELAY_CNTRL_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_RX_DELAY_CNTRL_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_RX_DELAY_CNTRL_1_FIELDS[] =
+{
+    &LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_RX_DELAY_CNTRL_1_REG = 
+{
+    "RX_DELAY_CNTRL_1",
+#if RU_INCLUDE_DESC
+    "RGMII Append 2 RX Delay Control 1 Register",
+    "",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_1_REG_OFFSET,
+    0,
+    0,
+    227,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    LPORT_RGMII_RX_DELAY_CNTRL_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_RGMII_RX_DELAY_CNTRL_2
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_RGMII_RX_DELAY_CNTRL_2_FIELDS[] =
+{
+    &LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD,
+    &LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_RGMII_RX_DELAY_CNTRL_2_REG = 
+{
+    "RX_DELAY_CNTRL_2",
+#if RU_INCLUDE_DESC
+    "RGMII Append 2 RX Delay Control 2 Register",
+    "",
+#endif
+    LPORT_RGMII_RX_DELAY_CNTRL_2_REG_OFFSET,
+    0,
+    0,
+    228,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_RGMII_RX_DELAY_CNTRL_2_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Block: LPORT_RGMII
+ ******************************************************************************/
+static const ru_reg_rec *LPORT_RGMII_REGS[] =
+{
+    &LPORT_RGMII_CNTRL_REG,
+    &LPORT_RGMII_IB_STATUS_REG,
+    &LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_REG,
+    &LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_REG,
+    &LPORT_RGMII_ATE_RX_EXP_DATA_1_REG,
+    &LPORT_RGMII_ATE_RX_STATUS_0_REG,
+    &LPORT_RGMII_ATE_RX_STATUS_1_REG,
+    &LPORT_RGMII_ATE_TX_CNTRL_REG,
+    &LPORT_RGMII_ATE_TX_DATA_0_REG,
+    &LPORT_RGMII_ATE_TX_DATA_1_REG,
+    &LPORT_RGMII_ATE_TX_DATA_2_REG,
+    &LPORT_RGMII_TX_DELAY_CNTRL_0_REG,
+    &LPORT_RGMII_TX_DELAY_CNTRL_1_REG,
+    &LPORT_RGMII_RX_DELAY_CNTRL_0_REG,
+    &LPORT_RGMII_RX_DELAY_CNTRL_1_REG,
+    &LPORT_RGMII_RX_DELAY_CNTRL_2_REG,
+};
+
+unsigned long LPORT_RGMII_ADDRS[] =
+{
+    0x8013c100,
+    0x8013c10c,
+    0x8013c118,
+};
+
+const ru_block_rec LPORT_RGMII_BLOCK = 
+{
+    "LPORT_RGMII",
+    LPORT_RGMII_ADDRS,
+    3,
+    16,
+    LPORT_RGMII_REGS
+};
+
+/* End of file BCM6858_A0LPORT_RGMII.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_SRDS_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_SRDS_AG.c
new file mode 100644
index 0000000000..6509d2be5a
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_SRDS_AG.c
@@ -0,0 +1,1929 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+#if RU_INCLUDE_FIELD_DB
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD =
+{
+    "SERDES_REV",
+#if RU_INCLUDE_DESC
+    "",
+    "SERDES Revision Control Register.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD =
+{
+    "ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Transaction Status. When transaction completes "
+    "(START_BUSY = 0 after it was set to 1) and this bit is set "
+    "it indicates that register transaction completed with error.",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD =
+{
+    "START_BUSY",
+#if RU_INCLUDE_DESC
+    "",
+    "START_BUSY, Self-clearing. CPU writes this bit to 1 in order to initiate indirect register "
+    "read/write transaction. When transaction completes hardware clears this bit.",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD =
+{
+    "R_W",
+#if RU_INCLUDE_DESC
+    "",
+    "Register transaction:\n"
+    "0 : Register Write.\n'"
+    "1 : Register Read.\n",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD =
+{
+    "REG_DATA",
+#if RU_INCLUDE_DESC
+    "",
+    "Register READ/WRITE Data.",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD =
+{
+    "REG_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access, address register.",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD =
+{
+    "REG_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access, data mask register."
+    "When a bit in this mask is set (1'b1), writing to the corresponding data bit is disabled.",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD =
+{
+    "ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Transaction Status. When transaction completes "
+    "(START_BUSY = 0 after it was set to 1) and this bit is set "
+    "it indicates that register transaction completed with error.",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD =
+{
+    "START_BUSY",
+#if RU_INCLUDE_DESC
+    "",
+    "START_BUSY, Self-clearing. CPU writes this bit to 1 in order to initiate indirect register "
+    "read/write transaction. When transaction completes hardware clears this bit.",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD =
+{
+    "R_W",
+#if RU_INCLUDE_DESC
+    "",
+    "Register transaction:\n"
+    "0 : Register Write.\n'"
+    "1 : Register Read.\n",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD =
+{
+    "REG_DATA",
+#if RU_INCLUDE_DESC
+    "",
+    "Register READ/WRITE Data.",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD =
+{
+    "REG_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access, address register.",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD =
+{
+    "REG_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access, data mask register."
+    "When a bit in this mask is set (1'b1), writing to the corresponding data bit is disabled.",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD =
+{
+    "ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Transaction Status. When transaction completes "
+    "(START_BUSY = 0 after it was set to 1) and this bit is set "
+    "it indicates that register transaction completed with error.",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD =
+{
+    "START_BUSY",
+#if RU_INCLUDE_DESC
+    "",
+    "START_BUSY, Self-clearing. CPU writes this bit to 1 in order to initiate indirect register "
+    "read/write transaction. When transaction completes hardware clears this bit.",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD =
+{
+    "R_W",
+#if RU_INCLUDE_DESC
+    "",
+    "Register transaction:\n"
+    "0 : Register Write.\n'"
+    "1 : Register Read.\n",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD =
+{
+    "REG_DATA",
+#if RU_INCLUDE_DESC
+    "",
+    "Register READ/WRITE Data.",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD =
+{
+    "REG_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access, address register.",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD =
+{
+    "REG_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access, data mask register."
+    "When a bit in this mask is set (1'b1), writing to the corresponding data bit is disabled.",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD =
+{
+    "ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Transaction Status. When transaction completes "
+    "(START_BUSY = 0 after it was set to 1) and this bit is set "
+    "it indicates that register transaction completed with error.",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD =
+{
+    "START_BUSY",
+#if RU_INCLUDE_DESC
+    "",
+    "START_BUSY, Self-clearing. CPU writes this bit to 1 in order to initiate indirect register "
+    "read/write transaction. When transaction completes hardware clears this bit.",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD =
+{
+    "R_W",
+#if RU_INCLUDE_DESC
+    "",
+    "Register transaction:\n"
+    "0 : Register Write.\n'"
+    "1 : Register Read.\n",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD =
+{
+    "REG_DATA",
+#if RU_INCLUDE_DESC
+    "",
+    "Register READ/WRITE Data.",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD =
+{
+    "REG_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access, address register.",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD =
+{
+    "REG_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access, data mask register."
+    "When a bit in this mask is set (1'b1), writing to the corresponding data bit is disabled.",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD_MASK,
+    0,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD_WIDTH,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD =
+{
+    "SERDES_TEST_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set single SERDES MDIO is controlled by a MDIO master connected to chip pins. Debug only function.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD =
+{
+    "SERDES_LN_OFFSET",
+#if RU_INCLUDE_DESC
+    "",
+    "SERDES Lane Offset device address for Clause 45.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD =
+{
+    "SERDES_PRTAD",
+#if RU_INCLUDE_DESC
+    "",
+    "SERDES port address for Clause 45",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD =
+{
+    "RESERVED1",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD =
+{
+    "RESERVED2",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD =
+{
+    "SERDES_RESET",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high SERDES system reset. Resets whole SERDES core. "
+    " Must be held high for at least 150ns after IDDQ is de-asserted.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD =
+{
+    "REFCLK_RESET",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high SERDES reference clock logic reset. Resets logic operating in SERDES reference clock domain.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD =
+{
+    "IDDQ",
+#if RU_INCLUDE_DESC
+    "",
+    "IDDQ Enable. Powers down SERDES analog front end and turn off all clocks. MDIO is not operational.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD =
+{
+    "MOD_DEF0",
+#if RU_INCLUDE_DESC
+    "",
+    "When 0 indicates presence of the optical module.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD =
+{
+    "EXT_SIG_DET",
+#if RU_INCLUDE_DESC
+    "",
+    "Non-filtered signal detect (or loss of signal) from the pin as provided by the external optical module. "
+    "Please consult used optical module datasheet for polarity. "
+    "NVRAM bit that indicates expected polarity is recommended.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD =
+{
+    "PLL_LOCK",
+#if RU_INCLUDE_DESC
+    "",
+    "PLL Lock. When 1'b1, indicates that single SERDES PLL is locked.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD =
+{
+    "LINK_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "Link Status. When 1'b1, indicates that link is up for the respective SERDES core.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD =
+{
+    "CDR_LOCK",
+#if RU_INCLUDE_DESC
+    "",
+    "CDR Lock. When 1'b1, indicates that CDR is locked for the respective SERDES core.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD =
+{
+    "RX_SIGDET",
+#if RU_INCLUDE_DESC
+    "",
+    "Filtered Rx Signal Detect. When 1'b1 indicates presence of the signal on Rx pins for the respective SERDES core.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD =
+{
+    "SERDES_TEST_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set single SERDES MDIO is controlled by a MDIO master connected to chip pins. Debug only function.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD =
+{
+    "SERDES_LN_OFFSET",
+#if RU_INCLUDE_DESC
+    "",
+    "SERDES Lane Offset device address for Clause 45.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD =
+{
+    "SERDES_PRTAD",
+#if RU_INCLUDE_DESC
+    "",
+    "SERDES port address for Clause 45",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD =
+{
+    "RESERVED1",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD =
+{
+    "RESERVED2",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD =
+{
+    "SERDES_RESET",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high SERDES system reset. Resets whole SERDES core. "
+    " Must be held high for at least 150ns after IDDQ is de-asserted.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD =
+{
+    "REFCLK_RESET",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high SERDES reference clock logic reset. Resets logic operating in SERDES reference clock domain.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD =
+{
+    "IDDQ",
+#if RU_INCLUDE_DESC
+    "",
+    "IDDQ Enable. Powers down SERDES analog front end and turn off all clocks. MDIO is not operational.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD =
+{
+    "MOD_DEF0",
+#if RU_INCLUDE_DESC
+    "",
+    "When 0 indicates presence of the optical module.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD =
+{
+    "EXT_SIG_DET",
+#if RU_INCLUDE_DESC
+    "",
+    "Non-filtered signal detect (or loss of signal) from the pin as provided by the external optical module. "
+    "Please consult used optical module datasheet for polarity. "
+    "NVRAM bit that indicates expected polarity is recommended.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD =
+{
+    "PLL_LOCK",
+#if RU_INCLUDE_DESC
+    "",
+    "PLL Lock. When 1'b1, indicates that single SERDES PLL is locked.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD =
+{
+    "LINK_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "Link Status. When 1'b1, indicates that link is up for the respective SERDES core.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD =
+{
+    "CDR_LOCK",
+#if RU_INCLUDE_DESC
+    "",
+    "CDR Lock. When 1'b1, indicates that CDR is locked for the respective SERDES core.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET
+ ******************************************************************************/
+const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD =
+{
+    "RX_SIGDET",
+#if RU_INCLUDE_DESC
+    "",
+    "Filtered Rx Signal Detect. When 1'b1 indicates presence of the signal on Rx pins for the respective SERDES core.",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD_MASK,
+    0,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD_WIDTH,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+/******************************************************************************
+ * Register: LPORT_SRDS_DUAL_SERDES_REVISION
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_DUAL_SERDES_REVISION_FIELDS[] =
+{
+    &LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_DUAL_SERDES_REVISION_REG = 
+{
+    "DUAL_SERDES_REVISION",
+#if RU_INCLUDE_DESC
+    "Dual SERDES Revision Control Register",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_REVISION_REG_OFFSET,
+    0,
+    0,
+    183,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_SRDS_DUAL_SERDES_REVISION_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG = 
+{
+    "SERDES_0_INDIR_ACC_CNTRL_0",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Control Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_OFFSET,
+    0,
+    0,
+    184,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG = 
+{
+    "SERDES_0_INDIR_ACC_ADDR_0",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Address Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_OFFSET,
+    0,
+    0,
+    185,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG = 
+{
+    "SERDES_0_INDIR_ACC_MASK_0",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Mask Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_OFFSET,
+    0,
+    0,
+    186,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG = 
+{
+    "SERDES_0_INDIR_ACC_CNTRL_1",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Control Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_OFFSET,
+    0,
+    0,
+    187,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG = 
+{
+    "SERDES_0_INDIR_ACC_ADDR_1",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Address Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_OFFSET,
+    0,
+    0,
+    188,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG = 
+{
+    "SERDES_0_INDIR_ACC_MASK_1",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Mask Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_OFFSET,
+    0,
+    0,
+    189,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG = 
+{
+    "SERDES_1_INDIR_ACC_CNTRL_0",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Control Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_OFFSET,
+    0,
+    0,
+    190,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG = 
+{
+    "SERDES_1_INDIR_ACC_ADDR_0",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Address Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_OFFSET,
+    0,
+    0,
+    191,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG = 
+{
+    "SERDES_1_INDIR_ACC_MASK_0",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Mask Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_OFFSET,
+    0,
+    0,
+    192,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG = 
+{
+    "SERDES_1_INDIR_ACC_CNTRL_1",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Control Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_OFFSET,
+    0,
+    0,
+    193,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG = 
+{
+    "SERDES_1_INDIR_ACC_ADDR_1",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Address Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_OFFSET,
+    0,
+    0,
+    194,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_FIELDS[] =
+{
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG = 
+{
+    "SERDES_1_INDIR_ACC_MASK_1",
+#if RU_INCLUDE_DESC
+    "SERDES 1 Indirect Access Mask Register 1",
+    "",
+#endif
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_OFFSET,
+    0,
+    0,
+    195,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_DUAL_SERDES_0_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_DUAL_SERDES_0_CNTRL_FIELDS[] =
+{
+    &LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_REG = 
+{
+    "DUAL_SERDES_0_CNTRL",
+#if RU_INCLUDE_DESC
+    "Dual SERDES 0 Control Register",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_REG_OFFSET,
+    0,
+    0,
+    196,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    LPORT_SRDS_DUAL_SERDES_0_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_DUAL_SERDES_0_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_DUAL_SERDES_0_STATUS_FIELDS[] =
+{
+    &LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_REG = 
+{
+    "DUAL_SERDES_0_STATUS",
+#if RU_INCLUDE_DESC
+    "Dual SERDES 1 Status Register",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_REG_OFFSET,
+    0,
+    0,
+    197,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_SRDS_DUAL_SERDES_0_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_DUAL_SERDES_1_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_DUAL_SERDES_1_CNTRL_FIELDS[] =
+{
+    &LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_REG = 
+{
+    "DUAL_SERDES_1_CNTRL",
+#if RU_INCLUDE_DESC
+    "Dual SERDES 1 Control Register",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_REG_OFFSET,
+    0,
+    0,
+    198,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    LPORT_SRDS_DUAL_SERDES_1_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: LPORT_SRDS_DUAL_SERDES_1_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_SRDS_DUAL_SERDES_1_STATUS_FIELDS[] =
+{
+    &LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD,
+    &LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_REG = 
+{
+    "DUAL_SERDES_1_STATUS",
+#if RU_INCLUDE_DESC
+    "Dual SERDES 1 Status Register",
+    "",
+#endif
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_REG_OFFSET,
+    0,
+    0,
+    199,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    7,
+    LPORT_SRDS_DUAL_SERDES_1_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Block: LPORT_SRDS
+ ******************************************************************************/
+static const ru_reg_rec *LPORT_SRDS_REGS[] =
+{
+    &LPORT_SRDS_DUAL_SERDES_REVISION_REG,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG,
+    &LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG,
+    &LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG,
+    &LPORT_SRDS_DUAL_SERDES_0_CNTRL_REG,
+    &LPORT_SRDS_DUAL_SERDES_0_STATUS_REG,
+    &LPORT_SRDS_DUAL_SERDES_1_CNTRL_REG,
+    &LPORT_SRDS_DUAL_SERDES_1_STATUS_REG,
+};
+
+unsigned long LPORT_SRDS_ADDRS[] =
+{
+    0x8013c00c,
+};
+
+const ru_block_rec LPORT_SRDS_BLOCK = 
+{
+    "LPORT_SRDS",
+    LPORT_SRDS_ADDRS,
+    1,
+    17,
+    LPORT_SRDS_REGS
+};
+
+/* End of file BCM6858_A0LPORT_SRDS.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_XLMAC_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_XLMAC_AG.c
new file mode 100644
index 0000000000..2404ef975f
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_XLMAC_AG.c
@@ -0,0 +1,8396 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+#if RU_INCLUDE_FIELD_DB
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD =
+{
+    "EXTENDED_HIG2_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "Extended Higig 2 header is also known as sirius header. Setting this bit to 0 will disable parsing for the extended header bit(5th bit of 8th header byte) in HG2 header and hence all the Higig 2 packets will be treated as normal Higig2 packets irrespective of extended header bit value. Default value of this field is 1 which will enable parsing extended header bit in every Higig 2 header.",
+#endif
+    LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_LINK_STATUS_SELECT
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD =
+{
+    "LINK_STATUS_SELECT",
+#if RU_INCLUDE_DESC
+    "",
+    "This configuration chooses between link status indication from software (SW_LINK_STATUS) or the hardware link status (hw_link_status)indication from the TSC. If reset, it selects the software link status",
+#endif
+    LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_SW_LINK_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD =
+{
+    "SW_LINK_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "Link status indication from Software. If set, indicates that link is active.",
+#endif
+    LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD =
+{
+    "XGMII_IPG_CHECK_DISABLE",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, this will override the one column idle/sequence ordered set check before SOP in XGMII mode - effectively supporting  reception of packets with 1 byte IPG in XGMII mode",
+#endif
+    LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_RS_SOFT_RESET
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD =
+{
+    "RS_SOFT_RESET",
+#if RU_INCLUDE_DESC
+    "",
+    "Resets the RS layer functionality - Fault detection and related responses are disabled and IDLEs are sent on line",
+#endif
+    LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_RSVD_5
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_RSVD_5_FIELD =
+{
+    "RSVD_5",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_CTRL_RSVD_5_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_RSVD_5_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_RSVD_5_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD =
+{
+    "LOCAL_LPBK_LEAK_ENB",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, during the local loopback mode, the transmit packets are also sent to the transmit line interface, apart from the loopback operation",
+#endif
+    LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_RSVD_4
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_RSVD_4_FIELD =
+{
+    "RSVD_4",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_CTRL_RSVD_4_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_RSVD_4_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_RSVD_4_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_SOFT_RESET
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_SOFT_RESET_FIELD =
+{
+    "SOFT_RESET",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, disables the corresponding port logic and status registers only. Packet data and flow control logic is disabled. Fault handling is active and the MAC will continue to respond to credits from TSC. When the soft reset is cleared MAC will issue a fresh set of credits to EP in transmit side.",
+#endif
+    LPORT_XLMAC_CTRL_SOFT_RESET_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_SOFT_RESET_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_SOFT_RESET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_LAG_FAILOVER_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD =
+{
+    "LAG_FAILOVER_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, enable LAG Failover. This bit has priority over LOCAL_LPBK. The lag failover kicks in when the link status selected by LINK_STATUS_SELECT transitions from 1 to 0. TSC clock and TSC credits must be active for lag failover.",
+#endif
+    LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD =
+{
+    "REMOVE_FAILOVER_LPBK",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, XLMAC will move from lag failover state to normal operation. This bit should be set after link is up.",
+#endif
+    LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_RSVD_1
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_RSVD_1_FIELD =
+{
+    "RSVD_1",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_CTRL_RSVD_1_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_RSVD_1_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_RSVD_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_LOCAL_LPBK
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD =
+{
+    "LOCAL_LPBK",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, enables local loopback from TX to RX. This loopback is on the line side after clock domain crossing - from the last TX pipeline stage to the first RX pipeline stage. Hence, TSC clock and TSC credits must be active for loopback. LAG_FAILOVER_EN should be disabled for this bit to work.",
+#endif
+    LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_RX_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_RX_EN_FIELD =
+{
+    "RX_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, enables MAC receive datapath and flowcontrol logic.",
+#endif
+    LPORT_XLMAC_CTRL_RX_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_RX_EN_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_RX_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CTRL_TX_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CTRL_TX_EN_FIELD =
+{
+    "TX_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, enables MAC transmit datapath and flowcontrol logic. When disabled, MAC will respond to TSC credits with IDLE codewords.",
+#endif
+    LPORT_XLMAC_CTRL_TX_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CTRL_TX_EN_FIELD_WIDTH,
+    LPORT_XLMAC_CTRL_TX_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_MODE_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_MODE_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_MODE_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_MODE_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_MODE_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_MODE_SPEED_MODE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_MODE_SPEED_MODE_FIELD =
+{
+    "SPEED_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "Port Speed, used for LED indications and internal buffer sizing.",
+#endif
+    LPORT_XLMAC_MODE_SPEED_MODE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_MODE_SPEED_MODE_FIELD_WIDTH,
+    LPORT_XLMAC_MODE_SPEED_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD =
+{
+    "NO_SOP_FOR_CRC_HG",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, excludes the SOP byte for CRC calculation in HIGIG modes",
+#endif
+    LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD_MASK,
+    0,
+    LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD_WIDTH,
+    LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_MODE_HDR_MODE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_MODE_HDR_MODE_FIELD =
+{
+    "HDR_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "Packet Header mode.",
+#endif
+    LPORT_XLMAC_MODE_HDR_MODE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_MODE_HDR_MODE_FIELD_WIDTH,
+    LPORT_XLMAC_MODE_HDR_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_SPARE0_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_SPARE0_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_SPARE0_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_SPARE0_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_SPARE0_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_SPARE0_RSVD
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_SPARE0_RSVD_FIELD =
+{
+    "RSVD",
+#if RU_INCLUDE_DESC
+    "",
+    "SPARE REGISTER 0",
+#endif
+    LPORT_XLMAC_SPARE0_RSVD_FIELD_MASK,
+    0,
+    LPORT_XLMAC_SPARE0_RSVD_FIELD_WIDTH,
+    LPORT_XLMAC_SPARE0_RSVD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_SPARE1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_SPARE1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_SPARE1_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_SPARE1_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_SPARE1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_SPARE1_RSVD
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_SPARE1_RSVD_FIELD =
+{
+    "RSVD",
+#if RU_INCLUDE_DESC
+    "",
+    "SPARE REGISTER 1",
+#endif
+    LPORT_XLMAC_SPARE1_RSVD_FIELD_MASK,
+    0,
+    LPORT_XLMAC_SPARE1_RSVD_FIELD_WIDTH,
+    LPORT_XLMAC_SPARE1_RSVD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_TX_THRESHOLD
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD =
+{
+    "TX_THRESHOLD",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates the number of 16-byte cells that are buffered per packet in the Tx CDC FIFO, before starting transmission of the packet on the line side.\n"
+    "This setting is useful to prevent underflow issues if the EP logic pumps in data at port rate, rather than bursting at full rate.\n"
+    "This mode will increase the overall latency.\n"
+    "In quad port mode, this field should be set >= 1 and <= 4 for each port.\n"
+    "In single port mode, this field should be set >= 1 and <= 16 for the four lane port (port0).\n"
+    "In dual port mode, this field should be set >= 1 and <= 8 for each two lane port (port0 and port2).\n"
+    "In tri1/tri2, this field should be set >= 1 and <= 4 for each single lane port, and >= 1 and <= 8 for the two lane port.",
+#endif
+    LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_EP_DISCARD
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD =
+{
+    "EP_DISCARD",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, MAC accepts packets from the EP but does not write to the CDC FIFO and discards them on the core side without updating the statistics.",
+#endif
+    LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD =
+{
+    "TX_PREAMBLE_LENGTH",
+#if RU_INCLUDE_DESC
+    "",
+    "Number of preamble bytes for transmit IEEE packets, this value should include the K.SOP & SFD character as well",
+#endif
+    LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_THROT_DENOM
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD =
+{
+    "THROT_DENOM",
+#if RU_INCLUDE_DESC
+    "",
+    "Number of bytes to transmit before adding THROT_NUM bytes to the IPG.  This configuration is used for WAN IPG throttling. Refer MAC specs for more details.",
+#endif
+    LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_THROT_NUM
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD =
+{
+    "THROT_NUM",
+#if RU_INCLUDE_DESC
+    "",
+    "Number of bytes of extra IPG added whenever THROT_DENOM bytes have been transmitted. This configuration is used for WAN IPG throttling. Refer MAC specs for more details.",
+#endif
+    LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_AVERAGE_IPG
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD =
+{
+    "AVERAGE_IPG",
+#if RU_INCLUDE_DESC
+    "",
+    "Average interpacket gap. Must be programmed >= 8. Per packet IPG will vary based on DIC for 10G+ speeds.",
+#endif
+    LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD =
+{
+    "PAD_THRESHOLD",
+#if RU_INCLUDE_DESC
+    "",
+    "If padding is enabled, packets smaller than PAD_THRESHOLD are padded to this size. This must be set to a value >= 17 (decimal)",
+#endif
+    LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_PAD_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD =
+{
+    "PAD_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, enable XLMAC to pad packets smaller than PAD_THRESHOLD on the Tx",
+#endif
+    LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_TX_ANY_START
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD =
+{
+    "TX_ANY_START",
+#if RU_INCLUDE_DESC
+    "",
+    "If reset, MAC forces the first byte of a packet to be /S/ character (0xFB) irrespective of incoming EP data at SOP location in HIGIG modes",
+#endif
+    LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_DISCARD
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_DISCARD_FIELD =
+{
+    "DISCARD",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, MAC accepts packets from the EP and discards them on the line side.  The statistics are updated.",
+#endif
+    LPORT_XLMAC_TX_CTRL_DISCARD_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_DISCARD_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_DISCARD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_CRC_MODE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD =
+{
+    "CRC_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "CRC mode for Transmit Side",
+#endif
+    LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD =
+{
+    "XLMAC_TX_CTRL_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "10 upper bits of the TX CTRL Register",
+#endif
+    LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD =
+{
+    "XLMAC_TX_CTRL_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the TX CTRL register",
+#endif
+    LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_MAC_SA_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_MAC_SA_CTRL_SA
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD =
+{
+    "CTRL_SA",
+#if RU_INCLUDE_DESC
+    "",
+    "Source Address for PAUSE/PFC packets generated by the MAC",
+#endif
+    LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD_WIDTH,
+    LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD =
+{
+    "SA_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "16 upper bits of the SA",
+#endif
+    LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD_WIDTH,
+    LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD =
+{
+    "SA_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the SA",
+#endif
+    LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD_WIDTH,
+    LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CTRL_RX_PASS_PFC
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD =
+{
+    "RX_PASS_PFC",
+#if RU_INCLUDE_DESC
+    "",
+    "This configuration is used to pass or drop pfc packetw when pfc_ether_type is not equal to 0x8808.              \n"
+    "If set, PFC frames are passed to system side. Otherwise, PFC frames are dropped in XLMAC.\n"
+    "This configuration is used in Rx CDC mode only.",
+#endif
+    LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD =
+{
+    "RX_PASS_PAUSE",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, PAUSE frames are passed to sytem side. Otherwise, PAUSE frames are dropped in XLMAC \n"
+    "This configuration is used in Rx CDC mode only.",
+#endif
+    LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD =
+{
+    "RX_PASS_CTRL",
+#if RU_INCLUDE_DESC
+    "",
+    "This configuration is used to drop or pass all control frames (with ether type 0x8808) except pause packets.\n"
+    "If set, all control frames are passed to system side. \n"
+    "Otherwise, control frames (including pfc frames wih ether type 0x8808) are dropped in XLMAC.\n"
+    "This configuration is used in Rx CDC mode only.",
+#endif
+    LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CTRL_RSVD_3
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD =
+{
+    "RSVD_3",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CTRL_RSVD_2
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD =
+{
+    "RSVD_2",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD =
+{
+    "RUNT_THRESHOLD",
+#if RU_INCLUDE_DESC
+    "",
+    "The runt threshold, below which the packets are dropped (CDC mode) or marked as runt (Low latency mode). Should be programmed < 96 bytes (decimal)",
+#endif
+    LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD =
+{
+    "STRICT_PREAMBLE",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, MAC checks for IEEE Ethernet preamble - K.SOP +  6 \"0x55\" preamble bytes + \"0xD5\" SFD character - if this sequence is missing it is treated as an errored packet",
+#endif
+    LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CTRL_STRIP_CRC
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD =
+{
+    "STRIP_CRC",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, CRC is stripped from the received packet",
+#endif
+    LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CTRL_RX_ANY_START
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD =
+{
+    "RX_ANY_START",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, MAC allows any undefined control character to start a packet",
+#endif
+    LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CTRL_RSVD_1
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD =
+{
+    "RSVD_1",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_MAC_SA_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_MAC_SA_RX_SA
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD =
+{
+    "RX_SA",
+#if RU_INCLUDE_DESC
+    "",
+    "Source Address recognized for MAC control packets in addition to the standard 0x0180C2000001",
+#endif
+    LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD_WIDTH,
+    LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD =
+{
+    "SA_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "16 upper bits of the receive SA",
+#endif
+    LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD_WIDTH,
+    LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD =
+{
+    "SA_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the receive SA",
+#endif
+    LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD_WIDTH,
+    LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_MAX_SIZE_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD =
+{
+    "RX_MAX_SIZE",
+#if RU_INCLUDE_DESC
+    "",
+    "Maximum packet size in receive direction, exclusive of preamble & CRC in strip mode. Packets greater than this size are truncated to this value.",
+#endif
+    LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_WIDTH,
+    LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_VLAN_TAG_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD =
+{
+    "OUTER_VLAN_TAG_ENABLE",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, MAC enables VLAN tag detection using the OUTER_VLAN_TAG",
+#endif
+    LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_WIDTH,
+    LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD =
+{
+    "INNER_VLAN_TAG_ENABLE",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, MAC enables VLAN tag detection using the INNER_VLAN_TAG",
+#endif
+    LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_WIDTH,
+    LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD =
+{
+    "OUTER_VLAN_TAG",
+#if RU_INCLUDE_DESC
+    "",
+    "TPID field for Outer VLAN tag",
+#endif
+    LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_WIDTH,
+    LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD =
+{
+    "INNER_VLAN_TAG",
+#if RU_INCLUDE_DESC
+    "",
+    "TPID field for Inner VLAN tag",
+#endif
+    LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_WIDTH,
+    LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD =
+{
+    "RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, the Receive Pause, PFC & LLFC timers are reset whenever the link status is down, or local or remote faults are received.",
+#endif
+    LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD =
+{
+    "DROP_TX_DATA_ON_LINK_INTERRUPT",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit determines the way MAC handles data during link interruption state, if LINK_INTERRUPTION_DISABLE is reset.\n"
+    "If set, during link interruption state, MAC drops transmit-data (statistics are updated) and sends IDLEs on the wire.\n"
+    "If reset, transmit data is stalled in the internal FIFO under link interruption state.",
+#endif
+    LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD =
+{
+    "DROP_TX_DATA_ON_REMOTE_FAULT",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit determines the way MAC handles data during remote fault state, if REMOTE_FAULT_DISABLE is reset.\n"
+    "If set, during remote fault state, MAC drops transmit-data (statistics are updated) and sends IDLEs on the wire.\n"
+    "If reset, transmit data is stalled in the internal FIFO under remote fault state.",
+#endif
+    LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD =
+{
+    "DROP_TX_DATA_ON_LOCAL_FAULT",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit determines the way MAC handles data during local fault state, if LOCAL_FAULT_DISABLE is reset.\n"
+    "If set, during local fault state, MAC drops transmit-data (statistics are updated) and sends remote faults on the wire.\n"
+    "If reset, transmit data is stalled in the internal FIFO under local fault state.",
+#endif
+    LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD =
+{
+    "LINK_INTERRUPTION_DISABLE",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit determines the transmit response during link interruption state. The LINK_INTERRUPTION_STATUS bit is always updated irrespective of this configuration.\n"
+    "If set, MAC will continue to transmit data irrespective of LINK_INTERRUPTION_STATUS.\n"
+    "If reset, MAC transmit behavior is governed by DROP_TX_DATA_ON_LINK_INTERRUPT configuration.",
+#endif
+    LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD =
+{
+    "USE_EXTERNAL_FAULTS_FOR_TX",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, the transmit fault responses are determined from input pins rather than internal receive status. \n"
+    "In this mode, input fault from pins (from a peer MAC) is directly relayed on the transmit side of this MAC.\n"
+    "See specification document for more details.",
+#endif
+    LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD =
+{
+    "REMOTE_FAULT_DISABLE",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit determines the transmit response during remote fault state. The REMOTE_FAULT_STATUS bit is always updated irrespective of this configuration.\n"
+    "If set, MAC will continue to transmit data irrespective of REMOTE_FAULT_STATUS.\n"
+    "If reset, MAC transmit behavior is governed by DROP_TX_DATA_ON_REMOTE_FAULT configuration.",
+#endif
+    LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD =
+{
+    "LOCAL_FAULT_DISABLE",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit determines the transmit response during local fault state. The LOCAL_FAULT_STATUS bit is always updated irrespective of this configuration.\n"
+    "If set, MAC will continue to transmit data irrespective of LOCAL_FAULT_STATUS.\n"
+    "If reset, MAC transmit behavior is governed by DROP_TX_DATA_ON_LOCAL_FAULT configuration.",
+#endif
+    LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD =
+{
+    "LINK_INTERRUPTION_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "True when link interruption state is detected as per RS layer state machine. Sticky bit is cleared by CLEAR_LINK_INTERRUPTION_STATUS.",
+#endif
+    LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD =
+{
+    "REMOTE_FAULT_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "True when remote fault state is detected as per RS layer state machine. Sticky bit is cleared by CLEAR_REMOTE_FAULT_STATUS.",
+#endif
+    LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD =
+{
+    "LOCAL_FAULT_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "True when local fault state is detected as per RS layer state machine. Sticky bit is cleared by CLEAR_LOCAL_FAULT_STATUS",
+#endif
+    LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD =
+{
+    "CLEAR_LINK_INTERRUPTION_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky LINK_INTERRUPTION_STATUS bit",
+#endif
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD =
+{
+    "CLEAR_REMOTE_FAULT_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky REMOTE_FAULT_STATUS bit",
+#endif
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD =
+{
+    "CLEAR_LOCAL_FAULT_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky LOCAL_FAULT_STATUS bit",
+#endif
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PAUSE_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD =
+{
+    "PAUSE_XOFF_TIMER",
+#if RU_INCLUDE_DESC
+    "",
+    "Pause time value sent in the timer field for XOFF state (unit is 512 bit-times)",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_WIDTH,
+    LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PAUSE_CTRL_RSVD_2
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD =
+{
+    "RSVD_2",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD_WIDTH,
+    LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PAUSE_CTRL_RSVD_1
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD =
+{
+    "RSVD_1",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD_WIDTH,
+    LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD =
+{
+    "RX_PAUSE_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables detection of pause frames in the receive direction and pause/resume the transmit data path",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD_WIDTH,
+    LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD =
+{
+    "TX_PAUSE_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables the transmission of pause frames whenever there is a transition on txbkp input to MAC from MMU",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD_WIDTH,
+    LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD =
+{
+    "PAUSE_REFRESH_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables the periodic re-generation of XOFF pause frames based on the interval specified in PAUSE_REFRESH_TIMER",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_WIDTH,
+    LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD =
+{
+    "PAUSE_REFRESH_TIMER",
+#if RU_INCLUDE_DESC
+    "",
+    "This field specifies the interval at which pause frames are re-generated during XOFF state, provided PAUSE_REFRESH_EN is set (unit is 512 bit-times)",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_WIDTH,
+    LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD =
+{
+    "XLMAC_PAUSE_CTRL_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "5 upper bits of the XLMAC Pause CTRL register",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD_WIDTH,
+    LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD =
+{
+    "XLMAC_PAUSE_CTRL_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the XLMAC Pause CTRL register",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD_WIDTH,
+    LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_TX_PFC_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD =
+{
+    "TX_PFC_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables the transmission of PFC frames",
+#endif
+    LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_RX_PFC_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD =
+{
+    "RX_PFC_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables detection of PFC frames in the receive direction and generation of COSMAPs to MMU based on incoming timer values",
+#endif
+    LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD =
+{
+    "PFC_STATS_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables the generation of receive and transmit PFC events into the corresponding statistics vectors (RSV and TSV)",
+#endif
+    LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_RSVD
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_RSVD_FIELD =
+{
+    "RSVD",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_PFC_CTRL_RSVD_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_RSVD_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_RSVD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD =
+{
+    "FORCE_PFC_XON",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, forces the MAC to generate an XON indication to the MMU for all classes of service in the receive direction",
+#endif
+    LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD =
+{
+    "PFC_REFRESH_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables the periodic re-generation of PFC frames based on the interval specified in PFC_REFRESH_TIMER",
+#endif
+    LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD =
+{
+    "PFC_XOFF_TIMER",
+#if RU_INCLUDE_DESC
+    "",
+    "Pause time value sent in the timer field for classes in XOFF state (unit is 512 bit-times)",
+#endif
+    LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD =
+{
+    "PFC_REFRESH_TIMER",
+#if RU_INCLUDE_DESC
+    "",
+    "This field specifies the interval at which PFC frames are re-generated for a class of service in XOFF state, provided PFC_REFRESH_EN is set (unit is 512 bit-times)",
+#endif
+    LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD =
+{
+    "LLFC_REFRESH_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables the periodic re-generation of LLFC frames based on the interval specified in LLFC_REFRESH_TIMER",
+#endif
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD =
+{
+    "RESERVED1",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD =
+{
+    "LLFC_REFRESH_TIMER",
+#if RU_INCLUDE_DESC
+    "",
+    "This field specifies the interval at which LLFC frames are re-generated for a class of service in XOFF state, provided LLFC_REFRESH_EN is set (unit is 512 bit-times)",
+#endif
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_TYPE_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD =
+{
+    "PFC_ETH_TYPE",
+#if RU_INCLUDE_DESC
+    "",
+    "This field is used in the ETHERTYPE field of the PFC frame that is generated and transmitted by the MAC and also used for detection in the receive direction",
+#endif
+    LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_OPCODE_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD =
+{
+    "PFC_OPCODE",
+#if RU_INCLUDE_DESC
+    "",
+    "This field is used in the OPCODE field of the PFC frame that is generated and transmitted by the MAC and also used for detection in the receive direction",
+#endif
+    LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_DA_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_DA_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_PFC_DA_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_DA_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_DA_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_DA_PFC_MACDA
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD =
+{
+    "PFC_MACDA",
+#if RU_INCLUDE_DESC
+    "",
+    "This field is used in the destination-address field of the PFC frame that is generated and transmitted by the MAC and also used for detection in the receive direction",
+#endif
+    LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD =
+{
+    "PFC_MACDA_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "16 upper bits of the PFC DA",
+#endif
+    LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD =
+{
+    "PFC_MACDA_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the PFC DA",
+#endif
+    LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD_WIDTH,
+    LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_LLFC_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_LLFC_CTRL_LLFC_IMG
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD =
+{
+    "LLFC_IMG",
+#if RU_INCLUDE_DESC
+    "",
+    "This field indicates the minimum Inter Message Gap that is enforced by the MAC between 2 LLFC messages in the transmit direction (unit is 1 credit)",
+#endif
+    LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD_MASK,
+    0,
+    LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD_WIDTH,
+    LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD =
+{
+    "NO_SOM_FOR_CRC_LLFC",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, LLFC CRC computation does not include the SOM character",
+#endif
+    LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_MASK,
+    0,
+    LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_WIDTH,
+    LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD =
+{
+    "LLFC_CRC_IGNORE",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, disables the CRC check for LLFC messages in the receive direction",
+#endif
+    LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_WIDTH,
+    LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD =
+{
+    "LLFC_CUT_THROUGH_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "When LLFC_IN_IPG_ONLY is reset, the mode of transmission of LLFC messages is controlled by this bit depending upon whether the LLFC message is XON or XOFF\n"
+    "When LLFC_CUT_THROUGH_MODE is reset, all LLFC messages are transmitted pre-emptively (within a packet)\n"
+    "When LLFC_CUT_THROUGH_MODE is set, only XOFF LLFC messages are transmitted pre-emptively, XON LLFC messages are transmitted during IPG",
+#endif
+    LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_WIDTH,
+    LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD =
+{
+    "LLFC_IN_IPG_ONLY",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, all LLFC messages are transmitted during IPG\n"
+    "When reset, the mode of insertion of LLFC messages is controlled by LLFC_CUT_THROUGH_MODE",
+#endif
+    LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_MASK,
+    0,
+    LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_WIDTH,
+    LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD =
+{
+    "RX_LLFC_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables processing of LLFC frames in the receive direction and generation of COSMAPs to MMU",
+#endif
+    LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD_WIDTH,
+    LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD =
+{
+    "TX_LLFC_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables the generation and transmission of LLFC frames in the transmit direction",
+#endif
+    LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD_WIDTH,
+    LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD =
+{
+    "LLFC_XOFF_TIME",
+#if RU_INCLUDE_DESC
+    "",
+    "Pause time value sent in the XOFF_TIME field of the outgoing LLFC message",
+#endif
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_WIDTH,
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD =
+{
+    "TX_LLFC_FC_OBJ_LOGICAL",
+#if RU_INCLUDE_DESC
+    "",
+    "This field is used in the FC_OBJ_LOGICAL field of the outgoing LLFC message",
+#endif
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_WIDTH,
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD =
+{
+    "TX_LLFC_MSG_TYPE_LOGICAL",
+#if RU_INCLUDE_DESC
+    "",
+    "This field is used in the MSG_TYPE_LOGICAL field of the outgoing LLFC message",
+#endif
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_WIDTH,
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD =
+{
+    "RX_LLFC_FC_OBJ_PHYSICAL",
+#if RU_INCLUDE_DESC
+    "",
+    "This value is compared against the FC_OBJ_PHYSICAL field of an incoming LLFC message in order to decode the message",
+#endif
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD =
+{
+    "RX_LLFC_MSG_TYPE_PHYSICAL",
+#if RU_INCLUDE_DESC
+    "",
+    "This value is compared against the MSG_TYPE_PHYSICAL field of an incoming LLFC message in order to decode the message",
+#endif
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD =
+{
+    "RX_LLFC_FC_OBJ_LOGICAL",
+#if RU_INCLUDE_DESC
+    "",
+    "This value is compared against the FC_OBJ_LOGICAL field of an incoming LLFC message in order to decode the message",
+#endif
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD =
+{
+    "RX_LLFC_MSG_TYPE_LOGICAL",
+#if RU_INCLUDE_DESC
+    "",
+    "This value is compared against the MSG_TYPE_LOGICAL field of an incoming LLFC message in order to decode the message",
+#endif
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_WIDTH,
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD =
+{
+    "TS_ENTRY_VALID",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high qualifier for the TimeStamp & SEQUENCE_ID fields.",
+#endif
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_WIDTH,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD =
+{
+    "SEQUENCE_ID",
+#if RU_INCLUDE_DESC
+    "",
+    "The Sequence Identifier extracted from the Timesync packet based on the header offset",
+#endif
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_WIDTH,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD =
+{
+    "TIME_STAMP",
+#if RU_INCLUDE_DESC
+    "",
+    "The TimeStamp value of the Tx two-step enabled packet.",
+#endif
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_WIDTH,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD =
+{
+    "ENTRY_COUNT",
+#if RU_INCLUDE_DESC
+    "",
+    "Number of TX time stamps currently buffered in TX Time Stamp FIFO. A valid entry is popped out whenever XLMAC_TX_TIMESTMAP_FIFO_DATA is read",
+#endif
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_WIDTH,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_FIFO_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_FIFO_STATUS_LINK_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD =
+{
+    "LINK_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "This bit indicates the link status used by XLMAC EEE and lag-failover state machines. This reflects the live status of the link as seen by the MAC. If set, indicates that link is active.",
+#endif
+    LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD =
+{
+    "RX_PKT_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates RX packet fifo overflow",
+#endif
+    LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD =
+{
+    "TX_TS_FIFO_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates overflow occurred in TX two-step Time Stamp FIFO",
+#endif
+    LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD =
+{
+    "TX_LLFC_MSG_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates TX LLFC message fifo overflow",
+#endif
+    LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_FIFO_STATUS_RSVD_2
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD =
+{
+    "RSVD_2",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD_MASK,
+    0,
+    LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD_WIDTH,
+    LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD =
+{
+    "TX_PKT_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates tx packet fifo overflow",
+#endif
+    LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD =
+{
+    "TX_PKT_UNDERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates tx packet fifo underflow",
+#endif
+    LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD =
+{
+    "RX_MSG_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates rx message fifo overflow",
+#endif
+    LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_FIFO_STATUS_RSVD_1
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD =
+{
+    "RSVD_1",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD_MASK,
+    0,
+    LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD_WIDTH,
+    LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD =
+{
+    "CLEAR_RX_PKT_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky RX_PKT_OVERFLOW status bit.",
+#endif
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD =
+{
+    "CLEAR_TX_TS_FIFO_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky TX_TS_FIFO_OVERFLOW status bit.",
+#endif
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD =
+{
+    "CLEAR_TX_LLFC_MSG_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky TX_LLFC_MSG_OVERFLOW status bit.",
+#endif
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD =
+{
+    "RSVD_2",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD =
+{
+    "CLEAR_TX_PKT_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky TX_PKT_OVERFLOW status bit.",
+#endif
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD =
+{
+    "CLEAR_TX_PKT_UNDERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky TX_PKT_UNDERFLOW status bit",
+#endif
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD =
+{
+    "CLEAR_RX_MSG_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky RX_MSG_OVERFLOW status bit",
+#endif
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD =
+{
+    "RSVD_1",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD =
+{
+    "RSVD",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD_MASK,
+    0,
+    LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD_WIDTH,
+    LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD =
+{
+    "LAG_FAILOVER_LOOPBACK",
+#if RU_INCLUDE_DESC
+    "",
+    "Set when XLMAC is in lag failover state",
+#endif
+    LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_MASK,
+    0,
+    LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_WIDTH,
+    LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_EEE_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_EEE_CTRL_RSVD
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_EEE_CTRL_RSVD_FIELD =
+{
+    "RSVD",
+#if RU_INCLUDE_DESC
+    "",
+    "Reserved",
+#endif
+    LPORT_XLMAC_EEE_CTRL_RSVD_FIELD_MASK,
+    0,
+    LPORT_XLMAC_EEE_CTRL_RSVD_FIELD_WIDTH,
+    LPORT_XLMAC_EEE_CTRL_RSVD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_EEE_CTRL_EEE_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD =
+{
+    "EEE_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables EEE state machine in the transmit direction and LPI detection/prediction in the receive direction",
+#endif
+    LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD_WIDTH,
+    LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD =
+{
+    "EEE_REF_COUNT",
+#if RU_INCLUDE_DESC
+    "",
+    "This field controls clock divider used to generate ~1us reference pulses used by EEE timers. It specifies integer number of clock cycles for 1us reference using tsc_clk",
+#endif
+    LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD_MASK,
+    0,
+    LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD_WIDTH,
+    LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD =
+{
+    "EEE_WAKE_TIMER",
+#if RU_INCLUDE_DESC
+    "",
+    "This is the duration for which MAC must wait to go back to ACTIVE state from LPI state when it receives packet/flow-control frames for transmission. Unit is micro seconds",
+#endif
+    LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_MASK,
+    0,
+    LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_WIDTH,
+    LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD =
+{
+    "EEE_DELAY_ENTRY_TIMER",
+#if RU_INCLUDE_DESC
+    "",
+    "This is the duration for which the MAC must wait in EMPTY state before transitioning to LPI state. Unit is micro seconds",
+#endif
+    LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_MASK,
+    0,
+    LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_WIDTH,
+    LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD =
+{
+    "XLMAC_EEE_TIMERS_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "32 upper bits of the EEE timer register",
+#endif
+    LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD_WIDTH,
+    LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD =
+{
+    "XLMAC_EEE_TIMERS_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the EEE Timer",
+#endif
+    LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD_WIDTH,
+    LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD =
+{
+    "ONE_SECOND_TIMER",
+#if RU_INCLUDE_DESC
+    "",
+    "This is the duration for which EEE FSM must wait when Link status becomes active before transitioning to ACTIVE state. Unit is micro seconds",
+#endif
+    LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_MASK,
+    0,
+    LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_WIDTH,
+    LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD =
+{
+    "HIGIG_HDR_0",
+#if RU_INCLUDE_DESC
+    "",
+    "In HiGig2 mode, this register contains bits 127:64 of 16-byte HiGig2 header. \n"
+    "In HiGig+ mode, bits 31:0 of this register contains bits 95:64 of 12-byte HiGig+ header.\n"
+    "This field is used for constructing the module header for HiGig2/HiGig+ pause and PFC frames in the transmit direction.",
+#endif
+    LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_WIDTH,
+    LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD =
+{
+    "HIGIG_HDR_0_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "32 upper bits of the HIGIG_HDR_0",
+#endif
+    LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD_WIDTH,
+    LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD =
+{
+    "HIGIG_HDR_0_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the HIGIG_HDR_0",
+#endif
+    LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD_WIDTH,
+    LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD =
+{
+    "HIGIG_HDR_1",
+#if RU_INCLUDE_DESC
+    "",
+    "In HiGig2 mode, this register contains bits 63:0 of 16-byte HiGig2 header. \n"
+    "In HiGig+ mode, this register contains bits 63:0 of 12-byte HiGig+ header.\n"
+    "This field is used for constructing the module header for HiGig2/HiGig+ pause and PFC frames in the transmit direction.",
+#endif
+    LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_MASK,
+    0,
+    LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_WIDTH,
+    LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD =
+{
+    "HIGIG_HDR_1_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "32 upper bits of the HIGIG_HDR_1",
+#endif
+    LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD_WIDTH,
+    LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD =
+{
+    "HIGIG_HDR_1_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the HIGIG_HDR_1",
+#endif
+    LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD_WIDTH,
+    LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD =
+{
+    "GMII_LPI_PREDICT_MODE_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables LPI prediction",
+#endif
+    LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_WIDTH,
+    LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD =
+{
+    "GMII_LPI_PREDICT_THRESHOLD",
+#if RU_INCLUDE_DESC
+    "",
+    "If GMII_LPI_PREDICT_MODE_EN is set then this field defines the number of IDLEs to be received before allowing LPIs to be sent to Link Partner",
+#endif
+    LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_MASK,
+    0,
+    LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_WIDTH,
+    LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD =
+{
+    "TS_USE_CS_OFFSET",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, indicates that the checksum offset is referenced by input port checksumoffset, else checksum offset is referenced by txtsoffset",
+#endif
+    LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_WIDTH,
+    LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD =
+{
+    "TS_TSTS_ADJUST",
+#if RU_INCLUDE_DESC
+    "",
+    "This is an unsigned value to account for synchronization delay of TS timer from TS clk to TSC_CLK domain. Unit is 1ns.\n"
+    "The latency is [2.5 TSC_CLK period + 1 TS_CLK period].",
+#endif
+    LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_WIDTH,
+    LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD =
+{
+    "TS_OSTS_ADJUST",
+#if RU_INCLUDE_DESC
+    "",
+    "This is a signed value which is 2s complement added to synchronized timestamp to account for MAC pipeline delay in OSTS. Unit is 1ns\n"
+    "The latency is [6 TSC_CLK period + 1 TS_CLK period ].",
+#endif
+    LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_WIDTH,
+    LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD =
+{
+    "RX_TIMER_BYTE_ADJUST_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables byte based adjustment for receive timestamp capture. This should be enabled in GMII/MII modes only.",
+#endif
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_WIDTH,
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD =
+{
+    "RX_TIMER_BYTE_ADJUST",
+#if RU_INCLUDE_DESC
+    "",
+    "This is a per byte unsigned value which is subtracted from sampled timestamp to account for timestamp jitter due to wider MSBUS interface. Unit is 1ns",
+#endif
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_WIDTH,
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD =
+{
+    "TX_TIMER_BYTE_ADJUST_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, enables byte based adjustment for transmit timestamp capture (OSTS and TSTS). This should be enabled in GMII/MII modes only.",
+#endif
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_WIDTH,
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD =
+{
+    "TX_TIMER_BYTE_ADJUST",
+#if RU_INCLUDE_DESC
+    "",
+    "This is a per byte unsigned value which is added to sampled timestamp to account for timestamp jitter due to wider MSBUS interface. Unit is 1ns",
+#endif
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_WIDTH,
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD =
+{
+    "PROG_TX_CRC",
+#if RU_INCLUDE_DESC
+    "",
+    "Programmable CRC value used to corrupt the Tx CRC. The computed CRC is replaced by this programmed CRC value based on TX_CRC_CORRUPTION_MODE",
+#endif
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD =
+{
+    "TX_CRC_CORRUPTION_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, the computed CRC is replaced with PROG_TX_CRC, else computed CRC is inverted",
+#endif
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD =
+{
+    "TX_CRC_CORRUPT_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, MAC enables the CRC corruption on the transmitted packets. Mode of corruption is determined by TX_CRC_CORRUPTION_MODE",
+#endif
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD =
+{
+    "TX_ERR_CORRUPTS_CRC",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, this bit causes packets with TXERR to corrupt the CRC of the packet when it is transmitted.\n"
+    "When reset, packets with TXERR are transmitted with /E/ termination character (/T/ is not enforced); packet CRC is unaffected",
+#endif
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD =
+{
+    "XLMAC_TX_CRC_CORRUPT_CTRL_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "3 Upper bits of the Tx CRC corrupt control register",
+#endif
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD =
+{
+    "XLMAC_TX_CRC_CORRUPT_CTRL_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the Tx CRC corrupt control register",
+#endif
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2E_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD =
+{
+    "E2EFC_DUAL_MODID_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, dual modid is enabled for E2EFC (Only 32 ports IBP is sent out). When reset, single modid is enabled for E2EFC (64 ports IBP is sent)",
+#endif
+    LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_WIDTH,
+    LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD =
+{
+    "E2ECC_LEGACY_IMP_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, legacy E2ECC stage2 loading enabled (single stage2 buffer for all ports). When reset, new E2ECC stage2 loading enabled (per port stage2 buffer)",
+#endif
+    LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_WIDTH,
+    LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD =
+{
+    "E2ECC_DUAL_MODID_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, dual modid is enabled for E2ECC. When reset, single modid is enabled for E2ECC",
+#endif
+    LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_WIDTH,
+    LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD =
+{
+    "HONOR_PAUSE_FOR_E2E",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, E2ECC/FC frames are not transmitted during pause state. When reset, E2ECC/FC frames are transmitted even during pause state similar to other flow control frames.",
+#endif
+    LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_WIDTH,
+    LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2E_CTRL_E2E_ENABLE
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD =
+{
+    "E2E_ENABLE",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, MAC enables E2EFC/E2ECC frame generation and transmission.",
+#endif
+    LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD_WIDTH,
+    LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD =
+{
+    "E2ECC_MODULE_HDR_0",
+#if RU_INCLUDE_DESC
+    "",
+    "In HiGig2 mode, this register contains bits 127:64 of 16-byte HiGig2 header. \n"
+    "In HiGig+ mode, this register contains bits 95:32 of 12-byte HiGig+ header.\n"
+    "This field is used for constructing the module header for HiGig2/HiGig+ E2ECC frames in the transmit direction.",
+#endif
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD =
+{
+    "E2ECC_MODULE_HDR_0_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "32 upper bits of the E2ECC_MODULE_HDR_0",
+#endif
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD =
+{
+    "E2ECC_MODULE_HDR_0_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the E2ECC_MODULE_HDR_0",
+#endif
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD =
+{
+    "E2ECC_MODULE_HDR_1",
+#if RU_INCLUDE_DESC
+    "",
+    "In HiGig2 mode, this register contains bits 63:0 of 16-byte HiGig2 header.\n"
+    "In HiGig+ mode, bits 63:32 of this register contains bits 31:0 of 12-byte HiGig+ header.\n"
+    "This field is used for constructing the module header for HiGig2/HiGig+ E2ECC frames in the transmit direction.",
+#endif
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD =
+{
+    "E2ECC_MODULE_HDR_1_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "32 upper bits of the E2ECC_MODULE_HDR_1",
+#endif
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD =
+{
+    "E2ECC_MODULE_HDR_1_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the E2ECC_MODULE_HDR_1",
+#endif
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD =
+{
+    "E2ECC_DATA_HDR_0",
+#if RU_INCLUDE_DESC
+    "",
+    "This register contains bits 127:64 of 16-byte IEEE header (DA + SA + Length/Type + Opcode).\n"
+    "This field is used for constructing the Ethernet header for HiGig2/HiGig+ E2ECC frames in the transmit direction.",
+#endif
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD =
+{
+    "E2ECC_DATA_HDR_0_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "32 upper bits of the E2ECC_DATA_HDR_0",
+#endif
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD =
+{
+    "E2ECC_DATA_HDR_0_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the E2ECC_DATA_HDR_0",
+#endif
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD =
+{
+    "E2ECC_DATA_HDR_1",
+#if RU_INCLUDE_DESC
+    "",
+    "This register contains bits 63:0 of 16-byte IEEE header (DA + SA + Length/Type + Opcode).\n"
+    "This field is used for constructing the Ethernet header for HiGig2/HiGig+ E2ECC frames in the transmit direction.",
+#endif
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD =
+{
+    "E2ECC_DATA_HDR_1_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "32 upper bits of the E2ECC_DATA_HDR_1",
+#endif
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD =
+{
+    "E2ECC_DATA_HDR_1_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the E2ECC_DATA_HDR_1",
+#endif
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD_WIDTH,
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD =
+{
+    "E2EFC_MODULE_HDR_0",
+#if RU_INCLUDE_DESC
+    "",
+    "In HiGig2 mode, this register contains bits 127:64 of 16-byte HiGig2 header. \n"
+    "In HiGig+ mode, this register contains bits 95:32 of 12-byte HiGig+ header.\n"
+    "This field is used for constructing the module header for HiGig2/HiGig+ E2EFC frames in the transmit direction.",
+#endif
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD =
+{
+    "E2EFC_MODULE_HDR_0_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "32 upper bits of the E2EFC_MODULE_HDR_0",
+#endif
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD =
+{
+    "E2EFC_MODULE_HDR_0_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the E2EFC_MODULE_HDR_0",
+#endif
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD =
+{
+    "E2EFC_MODULE_HDR_1",
+#if RU_INCLUDE_DESC
+    "",
+    "In HiGig2 mode, this register contains bits 63:0 of 16-byte HiGig2 header.\n"
+    "In HiGig+ mode, bits 63:32 of this register contains bits 31:0 of 12-byte HiGig+ header.\n"
+    "This field is used for constructing the module header for HiGig2/HiGig+ E2EFC frames in the transmit direction.",
+#endif
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD =
+{
+    "E2EFC_MODULE_HDR_1_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "32 upper bits of the E2EFC_MODULE_HDR_1",
+#endif
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD =
+{
+    "E2EFC_MODULE_HDR_1_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the E2EFC_MODULE_HDR_1",
+#endif
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD =
+{
+    "E2EFC_DATA_HDR_0",
+#if RU_INCLUDE_DESC
+    "",
+    "This register contains bits 127:64 of 16-byte IEEE header (DA + SA + Length/Type + Opcode).\n"
+    "This field is used for constructing the Ethernet header for HiGig2/HiGig+ E2EFC frames in the transmit direction.",
+#endif
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD =
+{
+    "E2EFC_DATA_HDR_0_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "32 upper bits of the E2EFC_DATA_HDR_0",
+#endif
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD =
+{
+    "E2EFC_DATA_HDR_0_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the E2EFC_DATA_HDR_0",
+#endif
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD =
+{
+    "E2EFC_DATA_HDR_1",
+#if RU_INCLUDE_DESC
+    "",
+    "This register contains bits 63:0 of 16-byte IEEE header (DA + SA + Length/Type + Opcode).\n"
+    "This field is used for constructing the Ethernet header for HiGig2/HiGig+ E2EFC frames in the transmit direction.",
+#endif
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD =
+{
+    "E2EFC_DATA_HDR_1_HI",
+#if RU_INCLUDE_DESC
+    "",
+    "32 upper bits of the E2EFC_DATA_HDR_1",
+#endif
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD =
+{
+    "E2EFC_DATA_HDR_1_LO",
+#if RU_INCLUDE_DESC
+    "",
+    "32 lower bits of the E2EFC_DATA_HDR_1",
+#endif
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD_MASK,
+    0,
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD_WIDTH,
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD =
+{
+    "CELL_CNT",
+#if RU_INCLUDE_DESC
+    "",
+    "Number of cell counts in XLMAC TX FIFO.\n"
+    "Should range from 0 to 32 for XLMAC core in single port mode, or 0 to 16 if XLMAC core is in dual port mode, or 0 to 8 if XLMAC core is in quad port mode during traffic.\n"
+    "This should reset to 0 after the traffic has stopped for all port modes.",
+#endif
+    LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD_WIDTH,
+    LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD =
+{
+    "REQ_CNT",
+#if RU_INCLUDE_DESC
+    "",
+    "Number of cell requests made to Egress Pipeline. \n"
+    "Should range from 0 to 32 for XLMAC core in single port mode, or 0 to 16 if XLMAC core is in dual port mode, or 0 to 8 if XLMAC core is in quad port mode during traffic.\n"
+    "This should saturate at the maximum value for the corresponding port mode after traffic has stopped.",
+#endif
+    LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_WIDTH,
+    LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_MEM_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD =
+{
+    "TX_CDC_MEM_CTRL_TM",
+#if RU_INCLUDE_DESC
+    "",
+    "Test mode configuration of Tx CDC Memory",
+#endif
+    LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_MASK,
+    0,
+    LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_WIDTH,
+    LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD =
+{
+    "RX_CDC_MEM_CTRL_TM",
+#if RU_INCLUDE_DESC
+    "",
+    "Test mode configuration of Rx CDC Memory.",
+#endif
+    LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_MASK,
+    0,
+    LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_WIDTH,
+    LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_ECC_CTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD =
+{
+    "TX_CDC_ECC_CTRL_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, MAC enables Tx CDC memory ECC logic",
+#endif
+    LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_WIDTH,
+    LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD =
+{
+    "RX_CDC_ECC_CTRL_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, MAC enables Rx CDC memory ECC logic",
+#endif
+    LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_MASK,
+    0,
+    LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_WIDTH,
+    LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD =
+{
+    "TX_CDC_FORCE_DOUBLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Tx CDC memory force double bit error enable. The LSB 2 bits will be inverted at the next memory read.\n"
+    "This should never be asserted simultaneously with TX_CDC_FORCE_SINGLE_BIT_ERR.\n"
+    "In order to inject double bit error again, this bit needs to be written to 0 before being re-written to 1.",
+#endif
+    LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD =
+{
+    "RX_CDC_FORCE_DOUBLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Rx CDC memory force double bit error enable. The LSB 2 bits will be inverted at the next memory read.\n"
+    "This should never be asserted simultaneously with force RX_CDC_FORCE_SINGLE_BIT_ERR.\n"
+    "In order to inject double bit error again, this bit needs to be written to 0 before being re-written to 1.",
+#endif
+    LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD =
+{
+    "TX_CDC_FORCE_SINGLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Tx CDC memory force single bit error enable. The LSB 1 bit will be inverted at the next memory read.\n"
+    "This should never be asserted simultaneously with TX_CDC_FORCE_DOUBLE_BIT_ERR.\n"
+    "In order to inject single bit error again, this bit needs to be written to 0 before being re-written to 1.",
+#endif
+    LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD =
+{
+    "RX_CDC_FORCE_SINGLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Rx CDC memory force single bit error enable. The LSB 1 bit will be inverted at the next memory read.\n"
+    "This should never be asserted simultaneously with RX_CDC_FORCE_DOUBLE_BIT_ERR.\n"
+    "In order to inject single bit error again, this bit needs to be written to 0 before being re-written to 1.",
+#endif
+    LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD =
+{
+    "RX_CDC_DOUBLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "This status bit indicates a double bit error occurred in the Rx CDC memory",
+#endif
+    LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD =
+{
+    "RX_CDC_SINGLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "This status bit indicates a single bit error occurred in the Rx CDC memory",
+#endif
+    LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD =
+{
+    "TX_CDC_DOUBLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "This status bit indicates a double bit error occurred in the Tx CDC memory",
+#endif
+    LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD =
+{
+    "TX_CDC_SINGLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "This status bit indicates a single bit error occurred in the Tx CDC memory",
+#endif
+    LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD =
+{
+    "CLEAR_TX_CDC_DOUBLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky TX_CDC_DOUBLE_BIT_ERR status bit",
+#endif
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD =
+{
+    "CLEAR_TX_CDC_SINGLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky TX_CDC_SINGLE_BIT_ERR status bit",
+#endif
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD =
+{
+    "CLEAR_RX_CDC_DOUBLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky RX_CDC_DOUBLE_BIT_ERR status bit",
+#endif
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD =
+{
+    "CLEAR_RX_CDC_SINGLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "A rising edge on this register bit (0->1), clears the sticky RX_CDC_SINGLE_BIT_ERR status bit",
+#endif
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD =
+{
+    "SUM_TS_ENTRY_VALID",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high qualifier for the TimeStamp & SEQUENCE_ID fields.",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD =
+{
+    "SUM_LINK_INTERRUPTION_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "True when link interruption state is detected as per RS layer state machine. Sticky bit is cleared by CLEAR_LINK_INTERRUPTION_STATUS.",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD =
+{
+    "SUM_REMOTE_FAULT_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "True when remote fault state is detected as per RS layer state machine. Sticky bit is cleared by CLEAR_REMOTE_FAULT_STATUS.",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD =
+{
+    "SUM_LOCAL_FAULT_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "True when local fault state is detected as per RS layer state machine. Sticky bit is cleared by CLEAR_LOCAL_FAULT_STATUS",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD =
+{
+    "SUM_RX_CDC_DOUBLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "This status bit indicates a double bit error occurred in the Rx CDC memory",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD =
+{
+    "SUM_RX_CDC_SINGLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "This status bit indicates a single bit error occurred in the Rx CDC memory",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD =
+{
+    "SUM_TX_CDC_DOUBLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "This status bit indicates a double bit error occurred in the Tx CDC memory",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD =
+{
+    "SUM_TX_CDC_SINGLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "This status bit indicates a single bit error occurred in the Tx CDC memory",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD =
+{
+    "SUM_RX_MSG_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates rx message fifo overflow",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD =
+{
+    "SUM_RX_PKT_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates RX packet fifo overflow",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD =
+{
+    "SUM_TX_TS_FIFO_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates overflow occurred in TX two-step Time Stamp FIFO",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD =
+{
+    "SUM_TX_LLFC_MSG_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates TX LLFC message fifo overflow",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD =
+{
+    "SUM_TX_PKT_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates tx packet fifo overflow",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD =
+{
+    "SUM_TX_PKT_UNDERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, indicates tx packet fifo underflow",
+#endif
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD =
+{
+    "EN_TS_ENTRY_VALID",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_TS_ENTRY_VALID can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD =
+{
+    "EN_LINK_INTERRUPTION_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_LINK_INTERRUPTION_STATUS can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD =
+{
+    "EN_REMOTE_FAULT_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_REMOTE_FAULT_STATUS can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD =
+{
+    "EN_LOCAL_FAULT_STATUS",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_LOCAL_FAULT_STATUS can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD =
+{
+    "EN_RX_CDC_DOUBLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_RX_CDC_DOUBLE_BIT_ERR can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD =
+{
+    "EN_RX_CDC_SINGLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_RX_CDC_SINGLE_BIT_ERR can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD =
+{
+    "EN_TX_CDC_DOUBLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_TX_CDC_DOUBLE_BIT_ERR can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD =
+{
+    "EN_TX_CDC_SINGLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_TX_CDC_SINGLE_BIT_ERR can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD =
+{
+    "EN_RX_MSG_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_RX_MSG_OVERFLOW can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD =
+{
+    "EN_RX_PKT_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_RX_PKT_OVERFLOW can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD =
+{
+    "EN_TX_TS_FIFO_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_TX_TS_FIFO_OVERFLOW can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD =
+{
+    "EN_TX_LLFC_MSG_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_TX_LLFC_MSG_OVERFLOW can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD =
+{
+    "EN_TX_PKT_OVERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_TX_PKT_OVERFLOW can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD =
+{
+    "EN_TX_PKT_UNDERFLOW",
+#if RU_INCLUDE_DESC
+    "",
+    "If set, SUM_TX_PKT_UNDERFLOW can set mac interrupt.",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_MASK,
+    0,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_WIDTH,
+    LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_VERSION_ID_RESERVED0
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD_MASK,
+    0,
+    LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD_WIDTH,
+    LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: LPORT_XLMAC_VERSION_ID_XLMAC_VERSION
+ ******************************************************************************/
+const ru_field_rec LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD =
+{
+    "XLMAC_VERSION",
+#if RU_INCLUDE_DESC
+    "",
+    "XLMAC IP Version ID - corresponds to RTL/DV label",
+#endif
+    LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD_MASK,
+    0,
+    LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD_WIDTH,
+    LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD,
+    &LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD,
+    &LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD,
+    &LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD,
+    &LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD,
+    &LPORT_XLMAC_CTRL_RSVD_5_FIELD,
+    &LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD,
+    &LPORT_XLMAC_CTRL_RSVD_4_FIELD,
+    &LPORT_XLMAC_CTRL_SOFT_RESET_FIELD,
+    &LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD,
+    &LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD,
+    &LPORT_XLMAC_CTRL_RSVD_1_FIELD,
+    &LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD,
+    &LPORT_XLMAC_CTRL_RX_EN_FIELD,
+    &LPORT_XLMAC_CTRL_TX_EN_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_CTRL_REG = 
+{
+    "CTRL",
+#if RU_INCLUDE_DESC
+    "MAC control for XLMAC0/port0 (LPORT port0)",
+    "MAC control.",
+#endif
+    LPORT_XLMAC_CTRL_REG_OFFSET,
+    0,
+    0,
+    0,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    16,
+    LPORT_XLMAC_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_MODE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_MODE_FIELDS[] =
+{
+    &LPORT_XLMAC_MODE_RESERVED0_FIELD,
+    &LPORT_XLMAC_MODE_SPEED_MODE_FIELD,
+    &LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD,
+    &LPORT_XLMAC_MODE_HDR_MODE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_MODE_REG = 
+{
+    "MODE",
+#if RU_INCLUDE_DESC
+    "XLMAC Mode register for XLMAC0/port0 (LPORT port0)",
+    "XLMAC Mode register",
+#endif
+    LPORT_XLMAC_MODE_REG_OFFSET,
+    0,
+    0,
+    1,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    4,
+    LPORT_XLMAC_MODE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_SPARE0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_SPARE0_FIELDS[] =
+{
+    &LPORT_XLMAC_SPARE0_RESERVED0_FIELD,
+    &LPORT_XLMAC_SPARE0_RSVD_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_SPARE0_REG = 
+{
+    "SPARE0",
+#if RU_INCLUDE_DESC
+    "Spare reg 0 for ECO for XLMAC0/port0 (LPORT port0)",
+    "Spare reg 0 for ECO",
+#endif
+    LPORT_XLMAC_SPARE0_REG_OFFSET,
+    0,
+    0,
+    2,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_SPARE0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_SPARE1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_SPARE1_FIELDS[] =
+{
+    &LPORT_XLMAC_SPARE1_RESERVED0_FIELD,
+    &LPORT_XLMAC_SPARE1_RSVD_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_SPARE1_REG = 
+{
+    "SPARE1",
+#if RU_INCLUDE_DESC
+    "Spare reg 1 for ECO for XLMAC0/port0 (LPORT port0)",
+    "Spare reg 1 for ECO",
+#endif
+    LPORT_XLMAC_SPARE1_REG_OFFSET,
+    0,
+    0,
+    3,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_SPARE1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TX_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TX_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD,
+    &LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD,
+    &LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD,
+    &LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD,
+    &LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD,
+    &LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD,
+    &LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD,
+    &LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD,
+    &LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD,
+    &LPORT_XLMAC_TX_CTRL_DISCARD_FIELD,
+    &LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TX_CTRL_REG = 
+{
+    "TX_CTRL",
+#if RU_INCLUDE_DESC
+    "Transmit control for XLMAC0/port0 (LPORT port0)",
+    "Transmit control.\n"
+    "\n"
+    "This XLMAC core register is 42 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_TX_CTRL) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_TX_CTRL_REG_OFFSET,
+    0,
+    0,
+    4,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    12,
+    LPORT_XLMAC_TX_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TX_CTRL_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TX_CTRL_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD,
+    &LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD,
+    &LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TX_CTRL_OVERLAY_REG = 
+{
+    "TX_CTRL_OVERLAY",
+#if RU_INCLUDE_DESC
+    "Transmit control for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "Transmit control.\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_TX_CTRL, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 42 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_TX_CTRL) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_TX_CTRL_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    5,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_TX_CTRL_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TX_MAC_SA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TX_MAC_SA_FIELDS[] =
+{
+    &LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD,
+    &LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TX_MAC_SA_REG = 
+{
+    "TX_MAC_SA",
+#if RU_INCLUDE_DESC
+    "Transmit Source Address for XLMAC0/port0 (LPORT port0)",
+    "Transmit Source Address.\n"
+    "\n"
+    "This XLMAC core register is 48 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_TX_MAC_SA) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_TX_MAC_SA_REG_OFFSET,
+    0,
+    0,
+    6,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_TX_MAC_SA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TX_MAC_SA_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TX_MAC_SA_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD,
+    &LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD,
+    &LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_REG = 
+{
+    "TX_MAC_SA_OVERLAY",
+#if RU_INCLUDE_DESC
+    "Transmit Source Address for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "Transmit Source Address.\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_TX_MAC_SA, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 48 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_TX_MAC_SA) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_TX_MAC_SA_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    7,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_TX_MAC_SA_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_RX_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_RX_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD,
+    &LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD,
+    &LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD,
+    &LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD,
+    &LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD,
+    &LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD,
+    &LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD,
+    &LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD,
+    &LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD,
+    &LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_RX_CTRL_REG = 
+{
+    "RX_CTRL",
+#if RU_INCLUDE_DESC
+    "Receive control for XLMAC0/port0 (LPORT port0)",
+    "Receive control.",
+#endif
+    LPORT_XLMAC_RX_CTRL_REG_OFFSET,
+    0,
+    0,
+    8,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    11,
+    LPORT_XLMAC_RX_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_RX_MAC_SA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_RX_MAC_SA_FIELDS[] =
+{
+    &LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD,
+    &LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_RX_MAC_SA_REG = 
+{
+    "RX_MAC_SA",
+#if RU_INCLUDE_DESC
+    "Receive source address for XLMAC0/port0 (LPORT port0)",
+    "Receive source address.\n"
+    "\n"
+    "This XLMAC core register is 48 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_RX_MAC_SA) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_RX_MAC_SA_REG_OFFSET,
+    0,
+    0,
+    9,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_RX_MAC_SA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_RX_MAC_SA_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_RX_MAC_SA_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD,
+    &LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD,
+    &LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_REG = 
+{
+    "RX_MAC_SA_OVERLAY",
+#if RU_INCLUDE_DESC
+    "Receive source address for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "Receive source address.\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_RX_MAC_SA, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 48 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_RX_MAC_SA) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_RX_MAC_SA_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    10,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_RX_MAC_SA_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_RX_MAX_SIZE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_RX_MAX_SIZE_FIELDS[] =
+{
+    &LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD,
+    &LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_RX_MAX_SIZE_REG = 
+{
+    "RX_MAX_SIZE",
+#if RU_INCLUDE_DESC
+    "Receive maximum packet size for XLMAC0/port0 (LPORT port0)",
+    "Receive maximum packet size.",
+#endif
+    LPORT_XLMAC_RX_MAX_SIZE_REG_OFFSET,
+    0,
+    0,
+    11,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_RX_MAX_SIZE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_RX_VLAN_TAG
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_RX_VLAN_TAG_FIELDS[] =
+{
+    &LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD,
+    &LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD,
+    &LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD,
+    &LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD,
+    &LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_RX_VLAN_TAG_REG = 
+{
+    "RX_VLAN_TAG",
+#if RU_INCLUDE_DESC
+    "Inner and Outer VLAN tag fields for XLMAC0/port0 (LPORT port0)",
+    "Inner and Outer VLAN tag fields\n"
+    "\n"
+    "This XLMAC core register is 34 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_RX_VLAN_TAG) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_RX_VLAN_TAG_REG_OFFSET,
+    0,
+    0,
+    12,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_XLMAC_RX_VLAN_TAG_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_RX_LSS_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_RX_LSS_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD,
+    &LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD,
+    &LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD,
+    &LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD,
+    &LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD,
+    &LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD,
+    &LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD,
+    &LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_RX_LSS_CTRL_REG = 
+{
+    "RX_LSS_CTRL",
+#if RU_INCLUDE_DESC
+    "Control for LSS (ordered set) messages for XLMAC0/port0 (LPORT port0)",
+    "Control for LSS (ordered set) messages",
+#endif
+    LPORT_XLMAC_RX_LSS_CTRL_REG_OFFSET,
+    0,
+    0,
+    13,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    LPORT_XLMAC_RX_LSS_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_RX_LSS_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_RX_LSS_STATUS_FIELDS[] =
+{
+    &LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD,
+    &LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD,
+    &LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD,
+    &LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_RX_LSS_STATUS_REG = 
+{
+    "RX_LSS_STATUS",
+#if RU_INCLUDE_DESC
+    "Status for RS layerThese bits are sticky by nature, and can be cleared by writing to the clear register for XLMAC0/port0 (LPORT port0)",
+    "Status for RS layer. These bits are sticky by nature, and can be cleared by writing to the clear register",
+#endif
+    LPORT_XLMAC_RX_LSS_STATUS_REG_OFFSET,
+    0,
+    0,
+    14,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    4,
+    LPORT_XLMAC_RX_LSS_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_CLEAR_RX_LSS_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_CLEAR_RX_LSS_STATUS_FIELDS[] =
+{
+    &LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD,
+    &LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD,
+    &LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD,
+    &LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_REG = 
+{
+    "CLEAR_RX_LSS_STATUS",
+#if RU_INCLUDE_DESC
+    "Clear the XLMAC_RX_LSS_STATUS register, used for resetting the sticky status bits for XLMAC0/port0 (LPORT port0)",
+    "Clear the XLMAC_RX_LSS_STATUS register, used for resetting the sticky status bits",
+#endif
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_REG_OFFSET,
+    0,
+    0,
+    15,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    4,
+    LPORT_XLMAC_CLEAR_RX_LSS_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_PAUSE_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_PAUSE_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD,
+    &LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD,
+    &LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD,
+    &LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD,
+    &LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD,
+    &LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD,
+    &LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_PAUSE_CTRL_REG = 
+{
+    "PAUSE_CTRL",
+#if RU_INCLUDE_DESC
+    "PAUSE control register for XLMAC0/port0 (LPORT port0)",
+    "PAUSE control register\n"
+    "\n"
+    "This XLMAC core register is 37 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_PAUSE_CTRL) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_REG_OFFSET,
+    0,
+    0,
+    16,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    8,
+    LPORT_XLMAC_PAUSE_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_PAUSE_CTRL_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_PAUSE_CTRL_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD,
+    &LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD,
+    &LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_REG = 
+{
+    "PAUSE_CTRL_OVERLAY",
+#if RU_INCLUDE_DESC
+    "PAUSE control register for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "PAUSE control register\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_PAUSE_CTRL, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 37 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_PAUSE_CTRL) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_PAUSE_CTRL_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    17,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_PAUSE_CTRL_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_PFC_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_PFC_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD,
+    &LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD,
+    &LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD,
+    &LPORT_XLMAC_PFC_CTRL_RSVD_FIELD,
+    &LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD,
+    &LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD,
+    &LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD,
+    &LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_PFC_CTRL_REG = 
+{
+    "PFC_CTRL",
+#if RU_INCLUDE_DESC
+    "PFC control register for XLMAC0/port0 (LPORT port0)",
+    "PFC control register\n"
+    "\n"
+    "This XLMAC core register is 38 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_PFC_CTRL) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_PFC_CTRL_REG_OFFSET,
+    0,
+    0,
+    18,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    LPORT_XLMAC_PFC_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_PFC_CTRL_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_PFC_CTRL_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD,
+    &LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD,
+    &LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD,
+    &LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_REG = 
+{
+    "PFC_CTRL_OVERLAY",
+#if RU_INCLUDE_DESC
+    "PFC control register for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "PFC control register\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_PFC_CTRL, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 33 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_PFC_CTRL) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    19,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    4,
+    LPORT_XLMAC_PFC_CTRL_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_PFC_TYPE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_PFC_TYPE_FIELDS[] =
+{
+    &LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD,
+    &LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_PFC_TYPE_REG = 
+{
+    "PFC_TYPE",
+#if RU_INCLUDE_DESC
+    "PFC Ethertype for XLMAC0/port0 (LPORT port0)",
+    "PFC Ethertype",
+#endif
+    LPORT_XLMAC_PFC_TYPE_REG_OFFSET,
+    0,
+    0,
+    20,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_PFC_TYPE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_PFC_OPCODE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_PFC_OPCODE_FIELDS[] =
+{
+    &LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD,
+    &LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_PFC_OPCODE_REG = 
+{
+    "PFC_OPCODE",
+#if RU_INCLUDE_DESC
+    "PFC Opcode for XLMAC0/port0 (LPORT port0)",
+    "PFC Opcode",
+#endif
+    LPORT_XLMAC_PFC_OPCODE_REG_OFFSET,
+    0,
+    0,
+    21,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_PFC_OPCODE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_PFC_DA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_PFC_DA_FIELDS[] =
+{
+    &LPORT_XLMAC_PFC_DA_RESERVED0_FIELD,
+    &LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_PFC_DA_REG = 
+{
+    "PFC_DA",
+#if RU_INCLUDE_DESC
+    "PFC Destination Address for XLMAC0/port0 (LPORT port0)",
+    "PFC Destination Address.\n"
+    "\n"
+    "This XLMAC core register is 48 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_PFC_DA) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_PFC_DA_REG_OFFSET,
+    0,
+    0,
+    22,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_PFC_DA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_PFC_DA_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_PFC_DA_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD,
+    &LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD,
+    &LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_PFC_DA_OVERLAY_REG = 
+{
+    "PFC_DA_OVERLAY",
+#if RU_INCLUDE_DESC
+    "PFC Destination Address for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "PFC Destination Address.\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_PFC_DA, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 48 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_PFC_DA) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_PFC_DA_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    23,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_PFC_DA_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_LLFC_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_LLFC_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD,
+    &LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD,
+    &LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD,
+    &LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD,
+    &LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD,
+    &LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD,
+    &LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_LLFC_CTRL_REG = 
+{
+    "LLFC_CTRL",
+#if RU_INCLUDE_DESC
+    "LLFC Control Register for XLMAC0/port0 (LPORT port0)",
+    "LLFC Control Register",
+#endif
+    LPORT_XLMAC_LLFC_CTRL_REG_OFFSET,
+    0,
+    0,
+    24,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    8,
+    LPORT_XLMAC_LLFC_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TX_LLFC_MSG_FIELDS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TX_LLFC_MSG_FIELDS_FIELDS[] =
+{
+    &LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD,
+    &LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD,
+    &LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD,
+    &LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_REG = 
+{
+    "TX_LLFC_MSG_FIELDS",
+#if RU_INCLUDE_DESC
+    "Programmable TX LLFC Message fields for XLMAC0/port0 (LPORT port0)",
+    "Programmable TX LLFC Message fields.",
+#endif
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_REG_OFFSET,
+    0,
+    0,
+    25,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    4,
+    LPORT_XLMAC_TX_LLFC_MSG_FIELDS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_RX_LLFC_MSG_FIELDS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_RX_LLFC_MSG_FIELDS_FIELDS[] =
+{
+    &LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD,
+    &LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD,
+    &LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD,
+    &LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD,
+    &LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_REG = 
+{
+    "RX_LLFC_MSG_FIELDS",
+#if RU_INCLUDE_DESC
+    "Programmable RX LLFC Message fields for XLMAC0/port0 (LPORT port0)",
+    "Programmable RX LLFC Message fields",
+#endif
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_REG_OFFSET,
+    0,
+    0,
+    26,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_XLMAC_RX_LLFC_MSG_FIELDS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_FIELDS[] =
+{
+    &LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD,
+    &LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD,
+    &LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD,
+    &LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_REG = 
+{
+    "TX_TIMESTAMP_FIFO_DATA",
+#if RU_INCLUDE_DESC
+    "The TimeStamp value of the Tx two-step packets for XLMAC0/port0 (LPORT port0)",
+    "The TimeStamp value of the Tx two-step packets.\n"
+    "\n"
+    "This XLMAC core register is 49 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_TX_TIMESTAMP_FIFO_DATA) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_REG_OFFSET,
+    0,
+    0,
+    27,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    4,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_FIELDS[] =
+{
+    &LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD,
+    &LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_REG = 
+{
+    "TX_TIMESTAMP_FIFO_STATUS",
+#if RU_INCLUDE_DESC
+    "Tx TimeStamp FIFO Status for XLMAC0/port0 (LPORT port0)",
+    "Tx TimeStamp FIFO Status.",
+#endif
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_REG_OFFSET,
+    0,
+    0,
+    28,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_FIFO_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_FIFO_STATUS_FIELDS[] =
+{
+    &LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD,
+    &LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD,
+    &LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD,
+    &LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD,
+    &LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD,
+    &LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD,
+    &LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD,
+    &LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD,
+    &LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD,
+    &LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_FIFO_STATUS_REG = 
+{
+    "FIFO_STATUS",
+#if RU_INCLUDE_DESC
+    "FIFO status registerThese bits (except LINK_STATUS) are sticky by nature, and can be cleared by writing to the clear register. for XLMAC0/port0 (LPORT port0)",
+    "FIFO status register. These bits (except LINK_STATUS) are sticky by nature, and can be cleared by writing to the clear register.",
+#endif
+    LPORT_XLMAC_FIFO_STATUS_REG_OFFSET,
+    0,
+    0,
+    29,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    10,
+    LPORT_XLMAC_FIFO_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_CLEAR_FIFO_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_CLEAR_FIFO_STATUS_FIELDS[] =
+{
+    &LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD,
+    &LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD,
+    &LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD,
+    &LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD,
+    &LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD,
+    &LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD,
+    &LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD,
+    &LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD,
+    &LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_REG = 
+{
+    "CLEAR_FIFO_STATUS",
+#if RU_INCLUDE_DESC
+    "Clear XLMAC_FIFO_STATUS register, used for resetting the sticky status bits for XLMAC0/port0 (LPORT port0)",
+    "Clear XLMAC_FIFO_STATUS register, used for resetting the sticky status bits",
+#endif
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_REG_OFFSET,
+    0,
+    0,
+    30,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    LPORT_XLMAC_CLEAR_FIFO_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_LAG_FAILOVER_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_LAG_FAILOVER_STATUS_FIELDS[] =
+{
+    &LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD,
+    &LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD,
+    &LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_REG = 
+{
+    "LAG_FAILOVER_STATUS",
+#if RU_INCLUDE_DESC
+    "Lag Failover Status for XLMAC0/port0 (LPORT port0)",
+    "Lag Failover Status.",
+#endif
+    LPORT_XLMAC_LAG_FAILOVER_STATUS_REG_OFFSET,
+    0,
+    0,
+    31,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_LAG_FAILOVER_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_EEE_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_EEE_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_EEE_CTRL_RSVD_FIELD,
+    &LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_EEE_CTRL_REG = 
+{
+    "EEE_CTRL",
+#if RU_INCLUDE_DESC
+    "Register for EEE Control  for XLMAC0/port0 (LPORT port0)",
+    "Register for EEE Control",
+#endif
+    LPORT_XLMAC_EEE_CTRL_REG_OFFSET,
+    0,
+    0,
+    32,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_EEE_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_EEE_TIMERS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_EEE_TIMERS_FIELDS[] =
+{
+    &LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD,
+    &LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD,
+    &LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_EEE_TIMERS_REG = 
+{
+    "EEE_TIMERS",
+#if RU_INCLUDE_DESC
+    "EEE Timers for XLMAC0/port0 (LPORT port0)",
+    "EEE Timers\n"
+    "\n"
+    "This XLMAC core register is 64 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_EEE_TIMERS) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_EEE_TIMERS_REG_OFFSET,
+    0,
+    0,
+    33,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_EEE_TIMERS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_EEE_TIMERS_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_EEE_TIMERS_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD,
+    &LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_EEE_TIMERS_OVERLAY_REG = 
+{
+    "EEE_TIMERS_OVERLAY",
+#if RU_INCLUDE_DESC
+    "EEE Timers for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "EEE Timers\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_EEE_TIMERS, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 64 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_EEE_TIMERS) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_EEE_TIMERS_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    34,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_EEE_TIMERS_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_FIELDS[] =
+{
+    &LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD,
+    &LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_REG = 
+{
+    "EEE_1_SEC_LINK_STATUS_TIMER",
+#if RU_INCLUDE_DESC
+    "EEE One Second Link Status Timer for XLMAC0/port0 (LPORT port0)",
+    "EEE One Second Link Status Timer",
+#endif
+    LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_REG_OFFSET,
+    0,
+    0,
+    35,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_HIGIG_HDR_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_HIGIG_HDR_0_FIELDS[] =
+{
+    &LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_0_REG = 
+{
+    "HIGIG_HDR_0",
+#if RU_INCLUDE_DESC
+    "HiGig2 and HiHig+ header register - MS bytes for XLMAC0/port0 (LPORT port0)",
+    "HiGig2 and HiHig+ header register - MS bytes\n"
+    "\n"
+    "This XLMAC core register is 64 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_HIGIG_HDR_0) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_HIGIG_HDR_0_REG_OFFSET,
+    0,
+    0,
+    36,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_XLMAC_HIGIG_HDR_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_HIGIG_HDR_0_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD,
+    &LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_REG = 
+{
+    "HIGIG_HDR_0_OVERLAY",
+#if RU_INCLUDE_DESC
+    "HiGig2 and HiHig+ header register - MS bytes for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "HiGig2 and HiHig+ header register - MS bytes\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_HIGIG_HDR_0, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 64 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_HIGIG_HDR_0) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    37,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_HIGIG_HDR_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_HIGIG_HDR_1_FIELDS[] =
+{
+    &LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_1_REG = 
+{
+    "HIGIG_HDR_1",
+#if RU_INCLUDE_DESC
+    "HiGig2 and HiHig+ header register - LS bytes for XLMAC0/port0 (LPORT port0)",
+    "HiGig2 and HiHig+ header register - LS bytes\n"
+    "\n"
+    "This XLMAC core register is 64 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_HIGIG_HDR_1) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_HIGIG_HDR_1_REG_OFFSET,
+    0,
+    0,
+    38,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_XLMAC_HIGIG_HDR_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_HIGIG_HDR_1_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD,
+    &LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_REG = 
+{
+    "HIGIG_HDR_1_OVERLAY",
+#if RU_INCLUDE_DESC
+    "HiGig2 and HiHig+ header register - LS bytes for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "HiGig2 and HiHig+ header register - LS bytes\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_HIGIG_HDR_1, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 64 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_HIGIG_HDR_1) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    39,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_GMII_EEE_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_GMII_EEE_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD,
+    &LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_GMII_EEE_CTRL_REG = 
+{
+    "GMII_EEE_CTRL",
+#if RU_INCLUDE_DESC
+    "MAC EEE control in GMII mode for XLMAC0/port0 (LPORT port0)",
+    "MAC EEE control in GMII mode.",
+#endif
+    LPORT_XLMAC_GMII_EEE_CTRL_REG_OFFSET,
+    0,
+    0,
+    40,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_GMII_EEE_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TIMESTAMP_ADJUST
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TIMESTAMP_ADJUST_FIELDS[] =
+{
+    &LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD,
+    &LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD,
+    &LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD,
+    &LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TIMESTAMP_ADJUST_REG = 
+{
+    "TIMESTAMP_ADJUST",
+#if RU_INCLUDE_DESC
+    "Timestamp Adjust registerRefer specification document for more details for XLMAC0/port0 (LPORT port0)",
+    "Timestamp Adjust register. Refer specification document for more details",
+#endif
+    LPORT_XLMAC_TIMESTAMP_ADJUST_REG_OFFSET,
+    0,
+    0,
+    41,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    4,
+    LPORT_XLMAC_TIMESTAMP_ADJUST_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_FIELDS[] =
+{
+    &LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD,
+    &LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD,
+    &LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD,
+    &LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD,
+    &LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_REG = 
+{
+    "TIMESTAMP_BYTE_ADJUST",
+#if RU_INCLUDE_DESC
+    "Timestamp Byte Adjust registerRefer specification document for more details for XLMAC0/port0 (LPORT port0)",
+    "Timestamp Byte Adjust register. Refer specification document for more details",
+#endif
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_REG_OFFSET,
+    0,
+    0,
+    42,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TX_CRC_CORRUPT_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD,
+    &LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD,
+    &LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD,
+    &LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_REG = 
+{
+    "TX_CRC_CORRUPT_CTRL",
+#if RU_INCLUDE_DESC
+    "Tx CRC corrupt control register for XLMAC0/port0 (LPORT port0)",
+    "Tx CRC corrupt control register\n"
+    "\n"
+    "This XLMAC core register is 35 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_TX_CRC_CORRUPT_CTRL) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_REG_OFFSET,
+    0,
+    0,
+    43,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD,
+    &LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD,
+    &LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_REG = 
+{
+    "TX_CRC_CORRUPT_CTRL_OVERLAY",
+#if RU_INCLUDE_DESC
+    "Tx CRC corrupt control register for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "Tx CRC corrupt control register\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_TX_CRC_CORRUPT_CTRL, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 35 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_TX_CRC_CORRUPT_CTRL) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    44,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2E_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2E_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD,
+    &LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD,
+    &LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD,
+    &LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD,
+    &LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2E_CTRL_REG = 
+{
+    "E2E_CTRL",
+#if RU_INCLUDE_DESC
+    "Transmit E2EFC/E2ECC control register for XLMAC0/port0 (LPORT port0)",
+    "Transmit E2EFC/E2ECC control register",
+#endif
+    LPORT_XLMAC_E2E_CTRL_REG_OFFSET,
+    0,
+    0,
+    45,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    LPORT_XLMAC_E2E_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2ECC_MODULE_HDR_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2ECC_MODULE_HDR_0_FIELDS[] =
+{
+    &LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_REG = 
+{
+    "E2ECC_MODULE_HDR_0",
+#if RU_INCLUDE_DESC
+    "E2ECC module header register - MS bytes for XLMAC0/port0 (LPORT port0)",
+    "E2ECC module header register - MS bytes\n"
+    "\n"
+    "This XLMAC core register is 64 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2ECC_MODULE_HDR_0) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_REG_OFFSET,
+    0,
+    0,
+    46,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD,
+    &LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_REG = 
+{
+    "E2ECC_MODULE_HDR_0_OVERLAY",
+#if RU_INCLUDE_DESC
+    "E2ECC module header register - MS bytes for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "E2ECC module header register - MS bytes\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_E2ECC_MODULE_HDR_0, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 64 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2ECC_MODULE_HDR_0) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    47,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2ECC_MODULE_HDR_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2ECC_MODULE_HDR_1_FIELDS[] =
+{
+    &LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_REG = 
+{
+    "E2ECC_MODULE_HDR_1",
+#if RU_INCLUDE_DESC
+    "E2ECC module header register - LS bytes for XLMAC0/port0 (LPORT port0)",
+    "E2ECC module header register - LS bytes\n"
+    "\n"
+    "This XLMAC core register is 64 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2ECC_MODULE_HDR_1) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_REG_OFFSET,
+    0,
+    0,
+    48,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD,
+    &LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_REG = 
+{
+    "E2ECC_MODULE_HDR_1_OVERLAY",
+#if RU_INCLUDE_DESC
+    "E2ECC module header register - LS bytes for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "E2ECC module header register - LS bytes\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_E2ECC_MODULE_HDR_1, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 64 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2ECC_MODULE_HDR_1) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    49,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2ECC_DATA_HDR_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2ECC_DATA_HDR_0_FIELDS[] =
+{
+    &LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_REG = 
+{
+    "E2ECC_DATA_HDR_0",
+#if RU_INCLUDE_DESC
+    "E2ECC Ethernet header register - MS bytes for XLMAC0/port0 (LPORT port0)",
+    "E2ECC Ethernet header register - MS bytes\n"
+    "\n"
+    "This XLMAC core register is 64 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2ECC_DATA_HDR_0) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_REG_OFFSET,
+    0,
+    0,
+    50,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD,
+    &LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_REG = 
+{
+    "E2ECC_DATA_HDR_0_OVERLAY",
+#if RU_INCLUDE_DESC
+    "E2ECC Ethernet header register - MS bytes for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "E2ECC Ethernet header register - MS bytes\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_E2ECC_DATA_HDR_0, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 64 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2ECC_DATA_HDR_0) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    51,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2ECC_DATA_HDR_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2ECC_DATA_HDR_1_FIELDS[] =
+{
+    &LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_REG = 
+{
+    "E2ECC_DATA_HDR_1",
+#if RU_INCLUDE_DESC
+    "E2ECC Ethernet header register - LS bytes for XLMAC0/port0 (LPORT port0)",
+    "E2ECC Ethernet header register - LS bytes\n"
+    "\n"
+    "This XLMAC core register is 64 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2ECC_DATA_HDR_1) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_REG_OFFSET,
+    0,
+    0,
+    52,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD,
+    &LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_REG = 
+{
+    "E2ECC_DATA_HDR_1_OVERLAY",
+#if RU_INCLUDE_DESC
+    "E2ECC Ethernet header register - LS bytes for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "E2ECC Ethernet header register - LS bytes\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_E2ECC_DATA_HDR_1, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 64 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2ECC_DATA_HDR_1) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    53,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2EFC_MODULE_HDR_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2EFC_MODULE_HDR_0_FIELDS[] =
+{
+    &LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_REG = 
+{
+    "E2EFC_MODULE_HDR_0",
+#if RU_INCLUDE_DESC
+    "E2EFC module header register - MS bytes for XLMAC0/port0 (LPORT port0)",
+    "E2EFC module header register - MS bytes\n"
+    "\n"
+    "This XLMAC core register is 64 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2EFC_MODULE_HDR_0) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_REG_OFFSET,
+    0,
+    0,
+    54,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD,
+    &LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_REG = 
+{
+    "E2EFC_MODULE_HDR_0_OVERLAY",
+#if RU_INCLUDE_DESC
+    "E2EFC module header register - MS bytes for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "E2EFC module header register - MS bytes\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_E2EFC_MODULE_HDR_0, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 64 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2EFC_MODULE_HDR_0) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    55,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2EFC_MODULE_HDR_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2EFC_MODULE_HDR_1_FIELDS[] =
+{
+    &LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_REG = 
+{
+    "E2EFC_MODULE_HDR_1",
+#if RU_INCLUDE_DESC
+    "E2EFC module header register - LS bytes for XLMAC0/port0 (LPORT port0)",
+    "E2EFC module header register - LS bytes\n"
+    "\n"
+    "This XLMAC core register is 64 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2EFC_MODULE_HDR_1) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_REG_OFFSET,
+    0,
+    0,
+    56,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD,
+    &LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_REG = 
+{
+    "E2EFC_MODULE_HDR_1_OVERLAY",
+#if RU_INCLUDE_DESC
+    "E2EFC module header register - LS bytes for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "E2EFC module header register - LS bytes\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_E2EFC_MODULE_HDR_1, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 64 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2EFC_MODULE_HDR_1) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    57,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2EFC_DATA_HDR_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2EFC_DATA_HDR_0_FIELDS[] =
+{
+    &LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_REG = 
+{
+    "E2EFC_DATA_HDR_0",
+#if RU_INCLUDE_DESC
+    "E2EFC Ethernet header register - MS bytes for XLMAC0/port0 (LPORT port0)",
+    "E2EFC Ethernet header register - MS bytes\n"
+    "\n"
+    "This XLMAC core register is 64 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2EFC_DATA_HDR_0) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_REG_OFFSET,
+    0,
+    0,
+    58,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD,
+    &LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_REG = 
+{
+    "E2EFC_DATA_HDR_0_OVERLAY",
+#if RU_INCLUDE_DESC
+    "E2EFC Ethernet header register - MS bytes for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "E2EFC Ethernet header register - MS bytes\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_E2EFC_DATA_HDR_0, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 64 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2EFC_DATA_HDR_0) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    59,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2EFC_DATA_HDR_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2EFC_DATA_HDR_1_FIELDS[] =
+{
+    &LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_REG = 
+{
+    "E2EFC_DATA_HDR_1",
+#if RU_INCLUDE_DESC
+    "E2EFC Ethernet header register - LS bytes for XLMAC0/port0 (LPORT port0)",
+    "E2EFC Ethernet header register - LS bytes\n"
+    "\n"
+    "This XLMAC core register is 64 bits wide in hardware. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2EFC_DATA_HDR_1) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).\n"
+    "\n"
+    "NOTE: THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW",
+#endif
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_REG_OFFSET,
+    0,
+    0,
+    60,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_FIELDS[] =
+{
+    &LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD,
+    &LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_REG = 
+{
+    "E2EFC_DATA_HDR_1_OVERLAY",
+#if RU_INCLUDE_DESC
+    "E2EFC Ethernet header register - LS bytes for XLMAC0/port0 (LPORT port0) - OVERLAY VIEW.",
+    "E2EFC Ethernet header register - LS bytes\n"
+    "\n"
+    "This is not a separate register - this is the same register (same address/same hardware) as ...XLMAC_E2EFC_DATA_HDR_1, here just presented with an alternative/overlay field layout view.\n"
+    "\n"
+    "This XLMAC core register, in this \"overlay\" view, has 64 bits. LPORT register reads and writes are however 32 bits per transaction. When reading from this address, higher XLMAC register bits are copied to XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be obtained by reading from that register. Similarly, when writing to this address, higher XLMAC register bits are taken from XLMAC0 32-bit Direct Access Data Write Register, so it is important to ensure proper value for the higher bits is present in that register prior to writing to this (...XLMAC_E2EFC_DATA_HDR_1) register.\n"
+    "Alternatively, Indirect Access mechanism can be used to access XLMAC core registers (see XLMACx Indirect Access registers).",
+#endif
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_REG_OFFSET,
+    0,
+    0,
+    61,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TXFIFO_CELL_CNT
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TXFIFO_CELL_CNT_FIELDS[] =
+{
+    &LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD,
+    &LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TXFIFO_CELL_CNT_REG = 
+{
+    "TXFIFO_CELL_CNT",
+#if RU_INCLUDE_DESC
+    "XLMAC TX FIFO Cell Count register for XLMAC0/port0 (LPORT port0)",
+    "XLMAC TX FIFO Cell Count register",
+#endif
+    LPORT_XLMAC_TXFIFO_CELL_CNT_REG_OFFSET,
+    0,
+    0,
+    62,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_TXFIFO_CELL_CNT_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TXFIFO_CELL_REQ_CNT
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_FIELDS[] =
+{
+    &LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD,
+    &LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REG = 
+{
+    "TXFIFO_CELL_REQ_CNT",
+#if RU_INCLUDE_DESC
+    "XLMAC TX FIFO Cell Request Count Register for XLMAC0/port0 (LPORT port0)",
+    "XLMAC TX FIFO Cell Request Count Register",
+#endif
+    LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REG_OFFSET,
+    0,
+    0,
+    63,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_MEM_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_MEM_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD,
+    &LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_MEM_CTRL_REG = 
+{
+    "MEM_CTRL",
+#if RU_INCLUDE_DESC
+    "Memory Control register for XLMAC0/port0 (LPORT port0)",
+    "Memory Control register",
+#endif
+    LPORT_XLMAC_MEM_CTRL_REG_OFFSET,
+    0,
+    0,
+    64,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_MEM_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_ECC_CTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_ECC_CTRL_FIELDS[] =
+{
+    &LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD,
+    &LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD,
+    &LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_ECC_CTRL_REG = 
+{
+    "ECC_CTRL",
+#if RU_INCLUDE_DESC
+    "XLMAC memories ECC control register for XLMAC0/port0 (LPORT port0)",
+    "XLMAC memories ECC control register",
+#endif
+    LPORT_XLMAC_ECC_CTRL_REG_OFFSET,
+    0,
+    0,
+    65,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_ECC_CTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_FIELDS[] =
+{
+    &LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD,
+    &LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_REG = 
+{
+    "ECC_FORCE_DOUBLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "XLMAC memories double bit error control register for XLMAC0/port0 (LPORT port0)",
+    "XLMAC memories double bit error control register",
+#endif
+    LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_REG_OFFSET,
+    0,
+    0,
+    66,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_FIELDS[] =
+{
+    &LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD,
+    &LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_REG = 
+{
+    "ECC_FORCE_SINGLE_BIT_ERR",
+#if RU_INCLUDE_DESC
+    "XLMAC memories single bit error control register for XLMAC0/port0 (LPORT port0)",
+    "XLMAC memories single bit error control register",
+#endif
+    LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_REG_OFFSET,
+    0,
+    0,
+    67,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_RX_CDC_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_RX_CDC_ECC_STATUS_FIELDS[] =
+{
+    &LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD,
+    &LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_REG = 
+{
+    "RX_CDC_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "Rx CDC memory ECC status registerThese bits are sticky by nature, and can be cleared by writing to the clear register. for XLMAC0/port0 (LPORT port0)",
+    "Rx CDC memory ECC status register. These bits are sticky by nature, and can be cleared by writing to the clear register.",
+#endif
+    LPORT_XLMAC_RX_CDC_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    68,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_RX_CDC_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_TX_CDC_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_TX_CDC_ECC_STATUS_FIELDS[] =
+{
+    &LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD,
+    &LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_REG = 
+{
+    "TX_CDC_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "Tx CDC memory ECC status registerThese bits are sticky by nature, and can be cleared by writing to the clear register. for XLMAC0/port0 (LPORT port0)",
+    "Tx CDC memory ECC status register. These bits are sticky by nature, and can be cleared by writing to the clear register.",
+#endif
+    LPORT_XLMAC_TX_CDC_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    69,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    LPORT_XLMAC_TX_CDC_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_CLEAR_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_CLEAR_ECC_STATUS_FIELDS[] =
+{
+    &LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD,
+    &LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_CLEAR_ECC_STATUS_REG = 
+{
+    "CLEAR_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "Clear ECC status register, used to reset the sticky status bits for XLMAC0/port0 (LPORT port0)",
+    "Clear ECC status register, used to reset the sticky status bits",
+#endif
+    LPORT_XLMAC_CLEAR_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    70,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    LPORT_XLMAC_CLEAR_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_INTR_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_INTR_STATUS_FIELDS[] =
+{
+    &LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD,
+    &LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_INTR_STATUS_REG = 
+{
+    "INTR_STATUS",
+#if RU_INCLUDE_DESC
+    "XLMAC interrupt status register for XLMAC0/port0 (LPORT port0)",
+    "XLMAC interrupt status register",
+#endif
+    LPORT_XLMAC_INTR_STATUS_REG_OFFSET,
+    0,
+    0,
+    71,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    15,
+    LPORT_XLMAC_INTR_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_INTR_ENABLE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_INTR_ENABLE_FIELDS[] =
+{
+    &LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD,
+    &LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_INTR_ENABLE_REG = 
+{
+    "INTR_ENABLE",
+#if RU_INCLUDE_DESC
+    "XLMAC interrupt enable register for XLMAC0/port0 (LPORT port0)",
+    "XLMAC interrupt enable register",
+#endif
+    LPORT_XLMAC_INTR_ENABLE_REG_OFFSET,
+    0,
+    0,
+    72,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    15,
+    LPORT_XLMAC_INTR_ENABLE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Register: LPORT_XLMAC_VERSION_ID
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *LPORT_XLMAC_VERSION_ID_FIELDS[] =
+{
+    &LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD,
+    &LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec LPORT_XLMAC_VERSION_ID_REG = 
+{
+    "VERSION_ID",
+#if RU_INCLUDE_DESC
+    "Version ID register for XLMAC0/port0 (LPORT port0)",
+    "Version ID register",
+#endif
+    LPORT_XLMAC_VERSION_ID_REG_OFFSET,
+    0,
+    0,
+    73,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    LPORT_XLMAC_VERSION_ID_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_64
+};
+
+/******************************************************************************
+ * Block: LPORT_XLMAC
+ ******************************************************************************/
+static const ru_reg_rec *LPORT_XLMAC_REGS[] =
+{
+    &LPORT_XLMAC_CTRL_REG,
+    &LPORT_XLMAC_MODE_REG,
+    &LPORT_XLMAC_SPARE0_REG,
+    &LPORT_XLMAC_SPARE1_REG,
+    &LPORT_XLMAC_TX_CTRL_REG,
+    &LPORT_XLMAC_TX_CTRL_OVERLAY_REG,
+    &LPORT_XLMAC_TX_MAC_SA_REG,
+    &LPORT_XLMAC_TX_MAC_SA_OVERLAY_REG,
+    &LPORT_XLMAC_RX_CTRL_REG,
+    &LPORT_XLMAC_RX_MAC_SA_REG,
+    &LPORT_XLMAC_RX_MAC_SA_OVERLAY_REG,
+    &LPORT_XLMAC_RX_MAX_SIZE_REG,
+    &LPORT_XLMAC_RX_VLAN_TAG_REG,
+    &LPORT_XLMAC_RX_LSS_CTRL_REG,
+    &LPORT_XLMAC_RX_LSS_STATUS_REG,
+    &LPORT_XLMAC_CLEAR_RX_LSS_STATUS_REG,
+    &LPORT_XLMAC_PAUSE_CTRL_REG,
+    &LPORT_XLMAC_PAUSE_CTRL_OVERLAY_REG,
+    &LPORT_XLMAC_PFC_CTRL_REG,
+    &LPORT_XLMAC_PFC_CTRL_OVERLAY_REG,
+    &LPORT_XLMAC_PFC_TYPE_REG,
+    &LPORT_XLMAC_PFC_OPCODE_REG,
+    &LPORT_XLMAC_PFC_DA_REG,
+    &LPORT_XLMAC_PFC_DA_OVERLAY_REG,
+    &LPORT_XLMAC_LLFC_CTRL_REG,
+    &LPORT_XLMAC_TX_LLFC_MSG_FIELDS_REG,
+    &LPORT_XLMAC_RX_LLFC_MSG_FIELDS_REG,
+    &LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_REG,
+    &LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_REG,
+    &LPORT_XLMAC_FIFO_STATUS_REG,
+    &LPORT_XLMAC_CLEAR_FIFO_STATUS_REG,
+    &LPORT_XLMAC_LAG_FAILOVER_STATUS_REG,
+    &LPORT_XLMAC_EEE_CTRL_REG,
+    &LPORT_XLMAC_EEE_TIMERS_REG,
+    &LPORT_XLMAC_EEE_TIMERS_OVERLAY_REG,
+    &LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_REG,
+    &LPORT_XLMAC_HIGIG_HDR_0_REG,
+    &LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_REG,
+    &LPORT_XLMAC_HIGIG_HDR_1_REG,
+    &LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_REG,
+    &LPORT_XLMAC_GMII_EEE_CTRL_REG,
+    &LPORT_XLMAC_TIMESTAMP_ADJUST_REG,
+    &LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_REG,
+    &LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_REG,
+    &LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_REG,
+    &LPORT_XLMAC_E2E_CTRL_REG,
+    &LPORT_XLMAC_E2ECC_MODULE_HDR_0_REG,
+    &LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_REG,
+    &LPORT_XLMAC_E2ECC_MODULE_HDR_1_REG,
+    &LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_REG,
+    &LPORT_XLMAC_E2ECC_DATA_HDR_0_REG,
+    &LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_REG,
+    &LPORT_XLMAC_E2ECC_DATA_HDR_1_REG,
+    &LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_REG,
+    &LPORT_XLMAC_E2EFC_MODULE_HDR_0_REG,
+    &LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_REG,
+    &LPORT_XLMAC_E2EFC_MODULE_HDR_1_REG,
+    &LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_REG,
+    &LPORT_XLMAC_E2EFC_DATA_HDR_0_REG,
+    &LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_REG,
+    &LPORT_XLMAC_E2EFC_DATA_HDR_1_REG,
+    &LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_REG,
+    &LPORT_XLMAC_TXFIFO_CELL_CNT_REG,
+    &LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REG,
+    &LPORT_XLMAC_MEM_CTRL_REG,
+    &LPORT_XLMAC_ECC_CTRL_REG,
+    &LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_REG,
+    &LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_REG,
+    &LPORT_XLMAC_RX_CDC_ECC_STATUS_REG,
+    &LPORT_XLMAC_TX_CDC_ECC_STATUS_REG,
+    &LPORT_XLMAC_CLEAR_ECC_STATUS_REG,
+    &LPORT_XLMAC_INTR_STATUS_REG,
+    &LPORT_XLMAC_INTR_ENABLE_REG,
+    &LPORT_XLMAC_VERSION_ID_REG,
+};
+
+unsigned long LPORT_XLMAC_ADDRS[] =
+{
+    0x80138000,
+    0x80138400,
+    0x80138800,
+    0x80138c00,
+    0x8013a000,
+    0x8013a400,
+    0x8013a800,
+    0x8013ac00,
+};
+
+const ru_block_rec LPORT_XLMAC_BLOCK = 
+{
+    "LPORT_XLMAC",
+    LPORT_XLMAC_ADDRS,
+    8,
+    74,
+    LPORT_XLMAC_REGS
+};
+
+/* End of file BCM6858_A0LPORT_XLMAC.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0MIB_CONF_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0MIB_CONF_AG.c
new file mode 100644
index 0000000000..0e8f365c40
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0MIB_CONF_AG.c
@@ -0,0 +1,2923 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+#if RU_INCLUDE_FIELD_DB
+/******************************************************************************
+ * Field: MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD =
+{
+    "WRITE_DATA",
+#if RU_INCLUDE_DESC
+    "",
+    "Direct register access data write register, bits [63:32]. "
+    "Used only for 64-bit register accesses.",
+#endif
+    MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_MASK,
+    0,
+    MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_WIDTH,
+    MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_DIR_ACC_DATA_READ_READ_DATA
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD =
+{
+    "READ_DATA",
+#if RU_INCLUDE_DESC
+    "",
+    "Direct register access data read register, bits [63:32]. "
+    "Used only for 64-bit register accesses.",
+#endif
+    MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_MASK,
+    0,
+    MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_WIDTH,
+    MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_0_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD =
+{
+    "ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Transaction Status. When transaction completes (START_BUSY = 0 after it was set to 1) "
+    "and this bit is set it indicates that register transaction completed with error.",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD =
+{
+    "START_BUSY",
+#if RU_INCLUDE_DESC
+    "",
+    "START_BUSY, Self-clearing. CPU writes this bit to 1 in order to initiate indirect register "
+    "read/write transaction. When transaction completes hardware clears this bit.",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_0_R_W
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD =
+{
+    "R_W",
+#if RU_INCLUDE_DESC
+    "",
+    "Register transaction:\n"
+    "0 : Register Write.\n'"
+    "1 : Register Read.\n",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD =
+{
+    "REG_PORT_ID",
+#if RU_INCLUDE_DESC
+    "",
+    "Register Port ID.",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD =
+{
+    "REG_OFFSET",
+#if RU_INCLUDE_DESC
+    "",
+    "Register offset.\n"
+    "Note: Bit 7 is ignored by HW. Write it as 0.",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD =
+{
+    "DATA_LOW",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access data register, bits [31:0].",
+#endif
+    MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD =
+{
+    "DATA_HIGH",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access data register, bits [63:32]. "
+    "Used only for 64-bit register accesses.",
+#endif
+    MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_1_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD =
+{
+    "ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Transaction Status. When transaction completes (START_BUSY = 0 after it was set to 1) "
+    "and this bit is set it indicates that register transaction completed with error.",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD =
+{
+    "START_BUSY",
+#if RU_INCLUDE_DESC
+    "",
+    "START_BUSY, Self-clearing. CPU writes this bit to 1 in order to initiate indirect register "
+    "read/write transaction. When transaction completes hardware clears this bit.",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_1_R_W
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD =
+{
+    "R_W",
+#if RU_INCLUDE_DESC
+    "",
+    "Register transaction:\n"
+    "0 : Register Write.\n'"
+    "1 : Register Read.\n",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD =
+{
+    "REG_PORT_ID",
+#if RU_INCLUDE_DESC
+    "",
+    "Register Port ID.",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD =
+{
+    "REG_OFFSET",
+#if RU_INCLUDE_DESC
+    "",
+    "Register offset.\n"
+    "Note: Bit 7 is ignored by HW. Write it as 0.",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD =
+{
+    "DATA_LOW",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access data register, bits [31:0].",
+#endif
+    MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD =
+{
+    "DATA_HIGH",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access data register, bits [63:32]. "
+    "Used only for 64-bit register accesses.",
+#endif
+    MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_MASK,
+    0,
+    MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_WIDTH,
+    MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_CNTRL_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_CNTRL_EEE_CNT_MODE
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD =
+{
+    "EEE_CNT_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "RX and TX EEE Duration Counter Behavior\n"
+    "0 : Counter behavior is asymmetric mode (100Base-TX, for example).\n"
+    "1 : Counter behavior is symmetric mode (1000Base-T, for example).",
+#endif
+    MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD_MASK,
+    0,
+    MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD_WIDTH,
+    MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_CNTRL_SATURATE_EN
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_CNTRL_SATURATE_EN_FIELD =
+{
+    "SATURATE_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When a bit in this vector is set corresponding XLMAC port statistic counters "
+    "saturate at their respective maximum values.",
+#endif
+    MIB_CONF_CNTRL_SATURATE_EN_FIELD_MASK,
+    0,
+    MIB_CONF_CNTRL_SATURATE_EN_FIELD_WIDTH,
+    MIB_CONF_CNTRL_SATURATE_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_CNTRL_COR_EN
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_CNTRL_COR_EN_FIELD =
+{
+    "COR_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When a bit in this vector is set corresponding XLMAC port statistic counters are clear-on-read.",
+#endif
+    MIB_CONF_CNTRL_COR_EN_FIELD_MASK,
+    0,
+    MIB_CONF_CNTRL_COR_EN_FIELD_WIDTH,
+    MIB_CONF_CNTRL_COR_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_CNTRL_CNT_RST
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_CNTRL_CNT_RST_FIELD =
+{
+    "CNT_RST",
+#if RU_INCLUDE_DESC
+    "",
+    "When a bit in this vector is set corresponding XLMAC port statistic counters are reset.",
+#endif
+    MIB_CONF_CNTRL_CNT_RST_FIELD_MASK,
+    0,
+    MIB_CONF_CNTRL_CNT_RST_FIELD_WIDTH,
+    MIB_CONF_CNTRL_CNT_RST_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD =
+{
+    "CNT",
+#if RU_INCLUDE_DESC
+    "",
+    "Timer to generate 10us pulse based on 25MHz refclk. Using LFSR to count up to 250 value.",
+#endif
+    MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_MASK,
+    0,
+    MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_WIDTH,
+    MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD =
+{
+    "MAX_PKT_SIZE",
+#if RU_INCLUDE_DESC
+    "",
+    "Maximum Packet Size, defaults to 1518B. Packets over this size are counted by MIB as oversized.",
+#endif
+    MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK,
+    0,
+    MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH,
+    MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD =
+{
+    "MAX_PKT_SIZE",
+#if RU_INCLUDE_DESC
+    "",
+    "Maximum Packet Size, defaults to 1518B. Packets over this size are counted by MIB as oversized.",
+#endif
+    MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK,
+    0,
+    MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH,
+    MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD =
+{
+    "MAX_PKT_SIZE",
+#if RU_INCLUDE_DESC
+    "",
+    "Maximum Packet Size, defaults to 1518B. Packets over this size are counted by MIB as oversized.",
+#endif
+    MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK,
+    0,
+    MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH,
+    MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD =
+{
+    "MAX_PKT_SIZE",
+#if RU_INCLUDE_DESC
+    "",
+    "Maximum Packet Size, defaults to 1518B. Packets over this size are counted by MIB as oversized.",
+#endif
+    MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK,
+    0,
+    MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH,
+    MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_ECC_CNTRL_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_ECC_CNTRL_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_ECC_CNTRL_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_ECC_CNTRL_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_ECC_CNTRL_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD =
+{
+    "TX_MIB_ECC_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "ECC enable for Tx MIB memories.",
+#endif
+    MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_MASK,
+    0,
+    MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_WIDTH,
+    MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD =
+{
+    "RX_MIB_ECC_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "ECC enable for Rx MIB memories.",
+#endif
+    MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_MASK,
+    0,
+    MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_WIDTH,
+    MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD =
+{
+    "FORCE_TX_MEM3_SERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Tx MIB memory instance 3 single bit ECC error. Do not assert together with force double bit ECC error.",
+#endif
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD =
+{
+    "FORCE_TX_MEM2_SERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Tx MIB memory instance 2 single bit ECC error. Do not assert together with force double bit ECC error.",
+#endif
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD =
+{
+    "FORCE_TX_MEM1_SERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Tx MIB memory instance 1 single bit ECC error. Do not assert together with force double bit ECC error.",
+#endif
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD =
+{
+    "FORCE_TX_MEM0_SERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Tx MIB memory instance 0 single bit ECC error. Do not assert together with force double bit ECC error.",
+#endif
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD =
+{
+    "FORCE_RX_MEM4_SERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Rx MIB memory instance 4 single bit ECC error. Do not assert together with force double bit ECC error.",
+#endif
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD =
+{
+    "FORCE_RX_MEM3_SERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Rx MIB memory instance 3 single bit ECC error. Do not assert together with force double bit ECC error.",
+#endif
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD =
+{
+    "FORCE_RX_MEM2_SERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Rx MIB memory instance 2 single bit ECC error. Do not assert together with force double bit ECC error.",
+#endif
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD =
+{
+    "FORCE_RX_MEM1_SERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Rx MIB memory instance 1 single bit ECC error. Do not assert together with force double bit ECC error.",
+#endif
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD =
+{
+    "FORCE_RX_MEM0_SERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Rx MIB memory instance 0 single bit ECC error. Do not assert together with force double bit ECC error.",
+#endif
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD =
+{
+    "FORCE_TX_MEM3_DERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Tx MIB memory instance 3 double bit ECC error. Do not assert together with force single bit ECC error.",
+#endif
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD =
+{
+    "FORCE_TX_MEM2_DERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Tx MIB memory instance 2 double bit ECC error. Do not assert together with force single bit ECC error.",
+#endif
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD =
+{
+    "FORCE_TX_MEM1_DERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Tx MIB memory instance 1 double bit ECC error. Do not assert together with force single bit ECC error.",
+#endif
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD =
+{
+    "FORCE_TX_MEM0_DERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Tx MIB memory instance 0 double bit ECC error. Do not assert together with force single bit ECC error.",
+#endif
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD =
+{
+    "FORCE_RX_MEM4_DERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Rx MIB memory instance 4 double bit ECC error. Do not assert together with force single bit ECC error.",
+#endif
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD =
+{
+    "FORCE_RX_MEM3_DERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Rx MIB memory instance 3 double bit ECC error. Do not assert together with force single bit ECC error.",
+#endif
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD =
+{
+    "FORCE_RX_MEM2_DERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Rx MIB memory instance 2 double bit ECC error. Do not assert together with force single bit ECC error.",
+#endif
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD =
+{
+    "FORCE_RX_MEM1_DERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Rx MIB memory instance 1 double bit ECC error. Do not assert together with force single bit ECC error.",
+#endif
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD =
+{
+    "FORCE_RX_MEM0_DERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Self-clearing. "
+    "Force Rx MIB memory instance 0 double bit ECC error. Do not assert together with force single bit ECC error.",
+#endif
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_MASK,
+    0,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_WIDTH,
+    MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD =
+{
+    "MEM_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "First memory address in which single bit error or double bit error is detected.",
+#endif
+    MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD =
+{
+    "DOUBLE_BIT_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Double Bit Error indicates an uncorrectable error occurred.",
+#endif
+    MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD =
+{
+    "MULTI_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates more than one single bit error or double bit error are detected.",
+#endif
+    MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD =
+{
+    "ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Single Bit Error (correctable) or Double Bit Error (Uncorrectable) occurred.",
+#endif
+    MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD =
+{
+    "MEM_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "First memory address in which single bit error or double bit error is detected.",
+#endif
+    MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD =
+{
+    "DOUBLE_BIT_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Double Bit Error indicates an uncorrectable error occurred.",
+#endif
+    MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD =
+{
+    "MULTI_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates more than one single bit error or double bit error are detected.",
+#endif
+    MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD =
+{
+    "ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Single Bit Error (correctable) or Double Bit Error (Uncorrectable) occurred.",
+#endif
+    MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD =
+{
+    "MEM_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "First memory address in which single bit error or double bit error is detected.",
+#endif
+    MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD =
+{
+    "DOUBLE_BIT_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Double Bit Error indicates an uncorrectable error occurred.",
+#endif
+    MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD =
+{
+    "MULTI_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates more than one single bit error or double bit error are detected.",
+#endif
+    MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD =
+{
+    "ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Single Bit Error (correctable) or Double Bit Error (Uncorrectable) occurred.",
+#endif
+    MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD =
+{
+    "MEM_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "First memory address in which single bit error or double bit error is detected.",
+#endif
+    MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD =
+{
+    "DOUBLE_BIT_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Double Bit Error indicates an uncorrectable error occurred.",
+#endif
+    MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD =
+{
+    "MULTI_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates more than one single bit error or double bit error are detected.",
+#endif
+    MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD =
+{
+    "ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Single Bit Error (correctable) or Double Bit Error (Uncorrectable) occurred.",
+#endif
+    MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD =
+{
+    "MEM_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "First memory address in which single bit error or double bit error is detected.",
+#endif
+    MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD =
+{
+    "DOUBLE_BIT_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Double Bit Error indicates an uncorrectable error occurred.",
+#endif
+    MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD =
+{
+    "MULTI_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates more than one single bit error or double bit error are detected.",
+#endif
+    MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD =
+{
+    "ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Single Bit Error (correctable) or Double Bit Error (Uncorrectable) occurred.",
+#endif
+    MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD =
+{
+    "MEM_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "First memory address in which single bit error or double bit error is detected.",
+#endif
+    MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD =
+{
+    "DOUBLE_BIT_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Double Bit Error indicates an uncorrectable error occurred.",
+#endif
+    MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD =
+{
+    "MULTI_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates more than one single bit error or double bit error are detected.",
+#endif
+    MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD =
+{
+    "ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Single Bit Error (correctable) or Double Bit Error (Uncorrectable) occurred.",
+#endif
+    MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD =
+{
+    "MEM_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "First memory address in which single bit error or double bit error is detected.",
+#endif
+    MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD =
+{
+    "DOUBLE_BIT_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Double Bit Error indicates an uncorrectable error occurred.",
+#endif
+    MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD =
+{
+    "MULTI_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates more than one single bit error or double bit error are detected.",
+#endif
+    MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD =
+{
+    "ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Single Bit Error (correctable) or Double Bit Error (Uncorrectable) occurred.",
+#endif
+    MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD =
+{
+    "MEM_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "First memory address in which single bit error or double bit error is detected.",
+#endif
+    MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD =
+{
+    "DOUBLE_BIT_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Double Bit Error indicates an uncorrectable error occurred.",
+#endif
+    MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD =
+{
+    "MULTI_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates more than one single bit error or double bit error are detected.",
+#endif
+    MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD =
+{
+    "ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Single Bit Error (correctable) or Double Bit Error (Uncorrectable) occurred.",
+#endif
+    MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_WIDTH,
+    MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD =
+{
+    "MEM_ADDR",
+#if RU_INCLUDE_DESC
+    "",
+    "First memory address in which single bit error or double bit error is detected.",
+#endif
+    MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD =
+{
+    "DOUBLE_BIT_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Double Bit Error indicates an uncorrectable error occurred.",
+#endif
+    MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD =
+{
+    "MULTI_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Indicates more than one single bit error or double bit error are detected.",
+#endif
+    MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+/******************************************************************************
+ * Field: MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR
+ ******************************************************************************/
+const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD =
+{
+    "ECC_ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Single Bit Error (correctable) or Double Bit Error (Uncorrectable) occurred.",
+#endif
+    MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_MASK,
+    0,
+    MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_WIDTH,
+    MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_read
+#endif
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+/******************************************************************************
+ * Register: MIB_CONF_DIR_ACC_DATA_WRITE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_DIR_ACC_DATA_WRITE_FIELDS[] =
+{
+    &MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_DIR_ACC_DATA_WRITE_REG = 
+{
+    "DIR_ACC_DATA_WRITE",
+#if RU_INCLUDE_DESC
+    "MIB 1 32-bit Direct Access Data Write Register",
+    "",
+#endif
+    MIB_CONF_DIR_ACC_DATA_WRITE_REG_OFFSET,
+    0,
+    0,
+    243,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    MIB_CONF_DIR_ACC_DATA_WRITE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_DIR_ACC_DATA_READ
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_DIR_ACC_DATA_READ_FIELDS[] =
+{
+    &MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_DIR_ACC_DATA_READ_REG = 
+{
+    "DIR_ACC_DATA_READ",
+#if RU_INCLUDE_DESC
+    "MIB 1 32-bit Direct Access Data Read Register",
+    "",
+#endif
+    MIB_CONF_DIR_ACC_DATA_READ_REG_OFFSET,
+    0,
+    0,
+    244,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    MIB_CONF_DIR_ACC_DATA_READ_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_INDIR_ACC_ADDR_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_INDIR_ACC_ADDR_0_FIELDS[] =
+{
+    &MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD,
+    &MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD,
+    &MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD,
+    &MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD,
+    &MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD,
+    &MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_INDIR_ACC_ADDR_0_REG = 
+{
+    "INDIR_ACC_ADDR_0",
+#if RU_INCLUDE_DESC
+    "MIB 1 Indirect Access Address Register",
+    "",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET,
+    0,
+    0,
+    245,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    MIB_CONF_INDIR_ACC_ADDR_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_INDIR_ACC_DATA_LOW_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_INDIR_ACC_DATA_LOW_0_FIELDS[] =
+{
+    &MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_LOW_0_REG = 
+{
+    "INDIR_ACC_DATA_LOW_0",
+#if RU_INCLUDE_DESC
+    "MIB 1 Indirect Access Data Low Register",
+    "",
+#endif
+    MIB_CONF_INDIR_ACC_DATA_LOW_0_REG_OFFSET,
+    0,
+    0,
+    246,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    MIB_CONF_INDIR_ACC_DATA_LOW_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_INDIR_ACC_DATA_HIGH_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_INDIR_ACC_DATA_HIGH_0_FIELDS[] =
+{
+    &MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_HIGH_0_REG = 
+{
+    "INDIR_ACC_DATA_HIGH_0",
+#if RU_INCLUDE_DESC
+    "MIB 1 Indirect Access Data High Register",
+    "",
+#endif
+    MIB_CONF_INDIR_ACC_DATA_HIGH_0_REG_OFFSET,
+    0,
+    0,
+    247,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    MIB_CONF_INDIR_ACC_DATA_HIGH_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_INDIR_ACC_ADDR_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_INDIR_ACC_ADDR_1_FIELDS[] =
+{
+    &MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD,
+    &MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD,
+    &MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD,
+    &MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD,
+    &MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD,
+    &MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_INDIR_ACC_ADDR_1_REG = 
+{
+    "INDIR_ACC_ADDR_1",
+#if RU_INCLUDE_DESC
+    "MIB 1 Indirect Access Address Register",
+    "",
+#endif
+    MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET,
+    0,
+    0,
+    248,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    MIB_CONF_INDIR_ACC_ADDR_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_INDIR_ACC_DATA_LOW_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_INDIR_ACC_DATA_LOW_1_FIELDS[] =
+{
+    &MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_LOW_1_REG = 
+{
+    "INDIR_ACC_DATA_LOW_1",
+#if RU_INCLUDE_DESC
+    "MIB 1 Indirect Access Data Low Register",
+    "",
+#endif
+    MIB_CONF_INDIR_ACC_DATA_LOW_1_REG_OFFSET,
+    0,
+    0,
+    249,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    MIB_CONF_INDIR_ACC_DATA_LOW_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_INDIR_ACC_DATA_HIGH_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_INDIR_ACC_DATA_HIGH_1_FIELDS[] =
+{
+    &MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_HIGH_1_REG = 
+{
+    "INDIR_ACC_DATA_HIGH_1",
+#if RU_INCLUDE_DESC
+    "MIB 1 Indirect Access Data High Register",
+    "",
+#endif
+    MIB_CONF_INDIR_ACC_DATA_HIGH_1_REG_OFFSET,
+    0,
+    0,
+    250,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    MIB_CONF_INDIR_ACC_DATA_HIGH_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_CNTRL_FIELDS[] =
+{
+    &MIB_CONF_CNTRL_RESERVED0_FIELD,
+    &MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD,
+    &MIB_CONF_CNTRL_SATURATE_EN_FIELD,
+    &MIB_CONF_CNTRL_COR_EN_FIELD,
+    &MIB_CONF_CNTRL_CNT_RST_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_CNTRL_REG = 
+{
+    "CNTRL",
+#if RU_INCLUDE_DESC
+    "MIB 1 Control Register",
+    "",
+#endif
+    MIB_CONF_CNTRL_REG_OFFSET,
+    0,
+    0,
+    251,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    MIB_CONF_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_EEE_PULSE_DURATION_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_EEE_PULSE_DURATION_CNTRL_FIELDS[] =
+{
+    &MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD,
+    &MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_EEE_PULSE_DURATION_CNTRL_REG = 
+{
+    "EEE_PULSE_DURATION_CNTRL",
+#if RU_INCLUDE_DESC
+    "MIB 1 EEE Pulse Duration Control Register",
+    "",
+#endif
+    MIB_CONF_EEE_PULSE_DURATION_CNTRL_REG_OFFSET,
+    0,
+    0,
+    252,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    MIB_CONF_EEE_PULSE_DURATION_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_GPORT0_MAX_PKT_SIZE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_GPORT0_MAX_PKT_SIZE_FIELDS[] =
+{
+    &MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD,
+    &MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_GPORT0_MAX_PKT_SIZE_REG = 
+{
+    "GPORT0_MAX_PKT_SIZE",
+#if RU_INCLUDE_DESC
+    "MIB 1 Max Packet Size Register",
+    "",
+#endif
+    MIB_CONF_GPORT0_MAX_PKT_SIZE_REG_OFFSET,
+    0,
+    0,
+    253,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    MIB_CONF_GPORT0_MAX_PKT_SIZE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_GPORT1_MAX_PKT_SIZE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_GPORT1_MAX_PKT_SIZE_FIELDS[] =
+{
+    &MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD,
+    &MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_GPORT1_MAX_PKT_SIZE_REG = 
+{
+    "GPORT1_MAX_PKT_SIZE",
+#if RU_INCLUDE_DESC
+    "MIB 1 Max Packet Size Register",
+    "",
+#endif
+    MIB_CONF_GPORT1_MAX_PKT_SIZE_REG_OFFSET,
+    0,
+    0,
+    254,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    MIB_CONF_GPORT1_MAX_PKT_SIZE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_GPORT2_MAX_PKT_SIZE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_GPORT2_MAX_PKT_SIZE_FIELDS[] =
+{
+    &MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD,
+    &MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_GPORT2_MAX_PKT_SIZE_REG = 
+{
+    "GPORT2_MAX_PKT_SIZE",
+#if RU_INCLUDE_DESC
+    "MIB 1 Max Packet Size Register",
+    "",
+#endif
+    MIB_CONF_GPORT2_MAX_PKT_SIZE_REG_OFFSET,
+    0,
+    0,
+    255,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    MIB_CONF_GPORT2_MAX_PKT_SIZE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_GPORT3_MAX_PKT_SIZE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_GPORT3_MAX_PKT_SIZE_FIELDS[] =
+{
+    &MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD,
+    &MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_GPORT3_MAX_PKT_SIZE_REG = 
+{
+    "GPORT3_MAX_PKT_SIZE",
+#if RU_INCLUDE_DESC
+    "MIB 1 Max Packet Size Register",
+    "",
+#endif
+    MIB_CONF_GPORT3_MAX_PKT_SIZE_REG_OFFSET,
+    0,
+    0,
+    256,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    MIB_CONF_GPORT3_MAX_PKT_SIZE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_ECC_CNTRL
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_ECC_CNTRL_FIELDS[] =
+{
+    &MIB_CONF_ECC_CNTRL_RESERVED0_FIELD,
+    &MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD,
+    &MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_ECC_CNTRL_REG = 
+{
+    "ECC_CNTRL",
+#if RU_INCLUDE_DESC
+    "MIB 1 ECC Control Register",
+    "",
+#endif
+    MIB_CONF_ECC_CNTRL_REG_OFFSET,
+    0,
+    0,
+    257,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    3,
+    MIB_CONF_ECC_CNTRL_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_FORCE_SB_ECC_ERR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_FORCE_SB_ECC_ERR_FIELDS[] =
+{
+    &MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD,
+    &MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD,
+    &MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD,
+    &MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD,
+    &MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD,
+    &MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD,
+    &MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD,
+    &MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD,
+    &MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD,
+    &MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_FORCE_SB_ECC_ERR_REG = 
+{
+    "FORCE_SB_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "MIB 1 Force Single Bit ECC Error Register",
+    "",
+#endif
+    MIB_CONF_FORCE_SB_ECC_ERR_REG_OFFSET,
+    0,
+    0,
+    258,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    10,
+    MIB_CONF_FORCE_SB_ECC_ERR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_FORCE_DB_ECC_ERR
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_FORCE_DB_ECC_ERR_FIELDS[] =
+{
+    &MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD,
+    &MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD,
+    &MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD,
+    &MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD,
+    &MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD,
+    &MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD,
+    &MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD,
+    &MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD,
+    &MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD,
+    &MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_FORCE_DB_ECC_ERR_REG = 
+{
+    "FORCE_DB_ECC_ERR",
+#if RU_INCLUDE_DESC
+    "MIB 1 Force Double Bit ECC Error Register",
+    "",
+#endif
+    MIB_CONF_FORCE_DB_ECC_ERR_REG_OFFSET,
+    0,
+    0,
+    259,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    10,
+    MIB_CONF_FORCE_DB_ECC_ERR_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_RX_MEM0_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_RX_MEM0_ECC_STATUS_FIELDS[] =
+{
+    &MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD,
+    &MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD,
+    &MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD,
+    &MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD,
+    &MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_RX_MEM0_ECC_STATUS_REG = 
+{
+    "RX_MEM0_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "MIB 1 TX MEM3 ECC Status Register",
+    "",
+#endif
+    MIB_CONF_RX_MEM0_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    260,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    MIB_CONF_RX_MEM0_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_RX_MEM1_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_RX_MEM1_ECC_STATUS_FIELDS[] =
+{
+    &MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD,
+    &MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD,
+    &MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD,
+    &MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD,
+    &MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_RX_MEM1_ECC_STATUS_REG = 
+{
+    "RX_MEM1_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "MIB 1 TX MEM3 ECC Status Register",
+    "",
+#endif
+    MIB_CONF_RX_MEM1_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    261,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    MIB_CONF_RX_MEM1_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_RX_MEM2_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_RX_MEM2_ECC_STATUS_FIELDS[] =
+{
+    &MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD,
+    &MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD,
+    &MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD,
+    &MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD,
+    &MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_RX_MEM2_ECC_STATUS_REG = 
+{
+    "RX_MEM2_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "MIB 1 TX MEM3 ECC Status Register",
+    "",
+#endif
+    MIB_CONF_RX_MEM2_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    262,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    MIB_CONF_RX_MEM2_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_RX_MEM3_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_RX_MEM3_ECC_STATUS_FIELDS[] =
+{
+    &MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD,
+    &MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD,
+    &MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD,
+    &MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD,
+    &MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_RX_MEM3_ECC_STATUS_REG = 
+{
+    "RX_MEM3_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "MIB 1 TX MEM3 ECC Status Register",
+    "",
+#endif
+    MIB_CONF_RX_MEM3_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    263,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    MIB_CONF_RX_MEM3_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_RX_MEM4_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_RX_MEM4_ECC_STATUS_FIELDS[] =
+{
+    &MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD,
+    &MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD,
+    &MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD,
+    &MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD,
+    &MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_RX_MEM4_ECC_STATUS_REG = 
+{
+    "RX_MEM4_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "MIB 1 TX MEM3 ECC Status Register",
+    "",
+#endif
+    MIB_CONF_RX_MEM4_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    264,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    MIB_CONF_RX_MEM4_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_TX_MEM0_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_TX_MEM0_ECC_STATUS_FIELDS[] =
+{
+    &MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD,
+    &MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD,
+    &MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD,
+    &MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD,
+    &MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_TX_MEM0_ECC_STATUS_REG = 
+{
+    "TX_MEM0_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "MIB 1 TX MEM3 ECC Status Register",
+    "",
+#endif
+    MIB_CONF_TX_MEM0_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    265,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    MIB_CONF_TX_MEM0_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_TX_MEM1_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_TX_MEM1_ECC_STATUS_FIELDS[] =
+{
+    &MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD,
+    &MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD,
+    &MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD,
+    &MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD,
+    &MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_TX_MEM1_ECC_STATUS_REG = 
+{
+    "TX_MEM1_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "MIB 1 TX MEM3 ECC Status Register",
+    "",
+#endif
+    MIB_CONF_TX_MEM1_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    266,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    MIB_CONF_TX_MEM1_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_TX_MEM2_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_TX_MEM2_ECC_STATUS_FIELDS[] =
+{
+    &MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD,
+    &MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD,
+    &MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD,
+    &MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD,
+    &MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_TX_MEM2_ECC_STATUS_REG = 
+{
+    "TX_MEM2_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "MIB 1 TX MEM3 ECC Status Register",
+    "",
+#endif
+    MIB_CONF_TX_MEM2_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    267,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    MIB_CONF_TX_MEM2_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: MIB_CONF_TX_MEM3_ECC_STATUS
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *MIB_CONF_TX_MEM3_ECC_STATUS_FIELDS[] =
+{
+    &MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD,
+    &MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD,
+    &MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD,
+    &MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD,
+    &MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec MIB_CONF_TX_MEM3_ECC_STATUS_REG = 
+{
+    "TX_MEM3_ECC_STATUS",
+#if RU_INCLUDE_DESC
+    "MIB 1 TX MEM3 ECC Status Register",
+    "",
+#endif
+    MIB_CONF_TX_MEM3_ECC_STATUS_REG_OFFSET,
+    0,
+    0,
+    268,
+#if RU_INCLUDE_ACCESS
+    ru_access_read,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    5,
+    MIB_CONF_TX_MEM3_ECC_STATUS_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Block: MIB_CONF
+ ******************************************************************************/
+static const ru_reg_rec *MIB_CONF_REGS[] =
+{
+    &MIB_CONF_DIR_ACC_DATA_WRITE_REG,
+    &MIB_CONF_DIR_ACC_DATA_READ_REG,
+    &MIB_CONF_INDIR_ACC_ADDR_0_REG,
+    &MIB_CONF_INDIR_ACC_DATA_LOW_0_REG,
+    &MIB_CONF_INDIR_ACC_DATA_HIGH_0_REG,
+    &MIB_CONF_INDIR_ACC_ADDR_1_REG,
+    &MIB_CONF_INDIR_ACC_DATA_LOW_1_REG,
+    &MIB_CONF_INDIR_ACC_DATA_HIGH_1_REG,
+    &MIB_CONF_CNTRL_REG,
+    &MIB_CONF_EEE_PULSE_DURATION_CNTRL_REG,
+    &MIB_CONF_GPORT0_MAX_PKT_SIZE_REG,
+    &MIB_CONF_GPORT1_MAX_PKT_SIZE_REG,
+    &MIB_CONF_GPORT2_MAX_PKT_SIZE_REG,
+    &MIB_CONF_GPORT3_MAX_PKT_SIZE_REG,
+    &MIB_CONF_ECC_CNTRL_REG,
+    &MIB_CONF_FORCE_SB_ECC_ERR_REG,
+    &MIB_CONF_FORCE_DB_ECC_ERR_REG,
+    &MIB_CONF_RX_MEM0_ECC_STATUS_REG,
+    &MIB_CONF_RX_MEM1_ECC_STATUS_REG,
+    &MIB_CONF_RX_MEM2_ECC_STATUS_REG,
+    &MIB_CONF_RX_MEM3_ECC_STATUS_REG,
+    &MIB_CONF_RX_MEM4_ECC_STATUS_REG,
+    &MIB_CONF_TX_MEM0_ECC_STATUS_REG,
+    &MIB_CONF_TX_MEM1_ECC_STATUS_REG,
+    &MIB_CONF_TX_MEM2_ECC_STATUS_REG,
+    &MIB_CONF_TX_MEM3_ECC_STATUS_REG,
+};
+
+unsigned long MIB_CONF_ADDRS[] =
+{
+    0x8013d100,
+    0x8013d300,
+};
+
+const ru_block_rec MIB_CONF_BLOCK = 
+{
+    "MIB_CONF",
+    MIB_CONF_ADDRS,
+    2,
+    26,
+    MIB_CONF_REGS
+};
+
+/* End of file BCM6858_A0MIB_CONF.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0XLMAC_CONF_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0XLMAC_CONF_AG.c
new file mode 100644
index 0000000000..e5fbfb447a
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0XLMAC_CONF_AG.c
@@ -0,0 +1,1269 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+#if RU_INCLUDE_FIELD_DB
+/******************************************************************************
+ * Field: XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD =
+{
+    "WRITE_DATA",
+#if RU_INCLUDE_DESC
+    "",
+    "Direct register access data write register, bits [63:32]. "
+    "Used only for 64-bit register accesses.",
+#endif
+    XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_MASK,
+    0,
+    XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_WIDTH,
+    XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD =
+{
+    "READ_DATA",
+#if RU_INCLUDE_DESC
+    "",
+    "Direct register access data read register, bits [63:32]. "
+    "Used only for 64-bit register accesses.",
+#endif
+    XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_MASK,
+    0,
+    XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_WIDTH,
+    XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_0_ERR
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD =
+{
+    "ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Transaction Status. When transaction completes (START_BUSY = 0 after it was set to 1) "
+    "and this bit is set it indicates that register transaction completed with error.",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD =
+{
+    "START_BUSY",
+#if RU_INCLUDE_DESC
+    "",
+    "START_BUSY, Self-clearing. CPU writes this bit to 1 in order to initiate indirect register "
+    "read/write transaction. When transaction completes hardware clears this bit.",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_0_R_W
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD =
+{
+    "R_W",
+#if RU_INCLUDE_DESC
+    "",
+    "Register transaction:\n"
+    "0 : Register Write.\n'"
+    "1 : Register Read.\n",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD =
+{
+    "REG_PORT_ID",
+#if RU_INCLUDE_DESC
+    "",
+    "Register Port ID.",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD =
+{
+    "REG_OFFSET",
+#if RU_INCLUDE_DESC
+    "",
+    "Register offset.\n"
+    "Note: Bit 7 is ignored by HW. Write it as 0.",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD =
+{
+    "DATA_LOW",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access data register, bits [31:0].",
+#endif
+    XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD =
+{
+    "DATA_HIGH",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access data register, bits [63:32]. "
+    "Used only for 64-bit register accesses.",
+#endif
+    XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_1_ERR
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD =
+{
+    "ERR",
+#if RU_INCLUDE_DESC
+    "",
+    "Transaction Status. When transaction completes (START_BUSY = 0 after it was set to 1) "
+    "and this bit is set it indicates that register transaction completed with error.",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD =
+{
+    "START_BUSY",
+#if RU_INCLUDE_DESC
+    "",
+    "START_BUSY, Self-clearing. CPU writes this bit to 1 in order to initiate indirect register "
+    "read/write transaction. When transaction completes hardware clears this bit.",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_1_R_W
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD =
+{
+    "R_W",
+#if RU_INCLUDE_DESC
+    "",
+    "Register transaction:\n"
+    "0 : Register Write.\n'"
+    "1 : Register Read.\n",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD =
+{
+    "REG_PORT_ID",
+#if RU_INCLUDE_DESC
+    "",
+    "Register Port ID.",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD =
+{
+    "REG_OFFSET",
+#if RU_INCLUDE_DESC
+    "",
+    "Register offset.\n"
+    "Note: Bit 7 is ignored by HW. Write it as 0.",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD =
+{
+    "DATA_LOW",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access data register, bits [31:0].",
+#endif
+    XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD =
+{
+    "DATA_HIGH",
+#if RU_INCLUDE_DESC
+    "",
+    "Indirect register access data register, bits [63:32]. "
+    "Used only for 64-bit register accesses.",
+#endif
+    XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_MASK,
+    0,
+    XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_WIDTH,
+    XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_CONFIG_RESERVED0
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_CONFIG_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    XLMAC_CONF_CONFIG_RESERVED0_FIELD_MASK,
+    0,
+    XLMAC_CONF_CONFIG_RESERVED0_FIELD_WIDTH,
+    XLMAC_CONF_CONFIG_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_CONFIG_XLMAC_RESET
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD =
+{
+    "XLMAC_RESET",
+#if RU_INCLUDE_DESC
+    "",
+    "Active high XLMAC hard reset.",
+#endif
+    XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD_MASK,
+    0,
+    XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD_WIDTH,
+    XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD =
+{
+    "RX_DUAL_CYCLE_TDM_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, Rx CDC FIFO read TDM order has same port for 2 consecutive cycles.\n"
+    "This is a strap input for the MAC core and should be changed only while hard reset is asserted.",
+#endif
+    XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_MASK,
+    0,
+    XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_WIDTH,
+    XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD =
+{
+    "RX_NON_LINEAR_QUAD_TDM_EN",
+#if RU_INCLUDE_DESC
+    "",
+    "When set, RX CDC FIFO read TDM generation order for quad mode is 0,2,1,3. Otherwise, it is 0,1,2,3.\n"
+    "This is a strap input for the MAC core and should be changed only while hard reset is asserted.",
+#endif
+    XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_MASK,
+    0,
+    XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_WIDTH,
+    XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD =
+{
+    "RX_FLEX_TDM_ENABLE",
+#if RU_INCLUDE_DESC
+    "",
+    "Enables non-linear TDM generation on the receive system interface, "
+    " based on data availability in Rx FIFOs.\n"
+    "0 : Flex TDM Enabled.\n"
+    "1 : Flex TDM Disabled.\n",
+#endif
+    XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_MASK,
+    0,
+    XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_WIDTH,
+    XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_CONFIG_MAC_MODE
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_CONFIG_MAC_MODE_FIELD =
+{
+    "MAC_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "Number of ports supported by XLMAC.\n"
+    "000 : Quad Port.\n"
+    "001 : Tri-Port (2/3). Ports 0 and 1 are single lane ports, "
+    "      and port 2 is an aggregate port made up of lanes 2 and 3.\n"
+    "010 : Tri-Port (0/1). Ports 2 and 3 are single lane ports, "
+    "      and port 0 is an aggregate port made up of lanes 0 and 1.\n"
+    "011 : Dual Port.\n"
+    "1xx : Single Port.",
+#endif
+    XLMAC_CONF_CONFIG_MAC_MODE_FIELD_MASK,
+    0,
+    XLMAC_CONF_CONFIG_MAC_MODE_FIELD_WIDTH,
+    XLMAC_CONF_CONFIG_MAC_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD =
+{
+    "OSTS_TIMER_DISABLE",
+#if RU_INCLUDE_DESC
+    "",
+    "OSTS time-stamping disable.\n"
+    "0 : OSTS Enabled.\n"
+    "1 : OSTS Disabled.\n",
+#endif
+    XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD_MASK,
+    0,
+    XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD_WIDTH,
+    XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_CONFIG_BYPASS_OSTS
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD =
+{
+    "BYPASS_OSTS",
+#if RU_INCLUDE_DESC
+    "",
+    "Bypasses transmit OSTS functionality. When set, reduces Tx path latency.\n"
+    "0 : Do not bypass transmit OSTS function.\n"
+    "1 : Bypass transmit OSTS function.\n"
+    "XLMAC must be reset for this bit to take effect.",
+#endif
+    XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD_MASK,
+    0,
+    XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD_WIDTH,
+    XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD =
+{
+    "EGR_1588_TIMESTAMPING_MODE",
+#if RU_INCLUDE_DESC
+    "",
+    "1588 Egress Time-stamping mode.\n"
+    "0 : Legacy, sign extended 32-bit timestamp mode.\n"
+    "1 : 48-bit timestamp mode.\n"
+    "XLMAC must be reset for this bit to take effect.",
+#endif
+    XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_MASK,
+    0,
+    XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_WIDTH,
+    XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INTERRUPT_CHECK_RESERVED0
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD_MASK,
+    0,
+    XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD_WIDTH,
+    XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD =
+{
+    "XLMAC_INTR_CHECK",
+#if RU_INCLUDE_DESC
+    "",
+    "Each bit of this field corresponds to one XLMAC port."
+    "SW should write 1 to the corresponding bit(s) of this field any time XLMAC interrupt is in use and "
+    "all events obtained by reading XLMAC status register are serviced and "
+    "corresponding statuses cleared. Prevents XLMAC interrupt race condition.",
+#endif
+    XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_MASK,
+    0,
+    XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_WIDTH,
+    XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD_MASK,
+    0,
+    XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD_WIDTH,
+    XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD =
+{
+    "RSV_ERR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "These bits define mask for bits [37:16] of RSV vector. If any of un-masked bits "
+    "(with the exception of bit 23 that is GOOD_PACKET_RECEIVED) is set, "
+    "XLMAC asserts RXERR on its system receive interface.",
+#endif
+    XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK,
+    0,
+    XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH,
+    XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD_MASK,
+    0,
+    XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD_WIDTH,
+    XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD =
+{
+    "RSV_ERR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "These bits define mask for bits [37:16] of RSV vector. If any of un-masked bits "
+    "(with the exception of bit 23 that is GOOD_PACKET_RECEIVED) is set, "
+    "XLMAC asserts RXERR on its system receive interface.",
+#endif
+    XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK,
+    0,
+    XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH,
+    XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD_MASK,
+    0,
+    XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD_WIDTH,
+    XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD =
+{
+    "RSV_ERR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "These bits define mask for bits [37:16] of RSV vector. If any of un-masked bits "
+    "(with the exception of bit 23 that is GOOD_PACKET_RECEIVED) is set, "
+    "XLMAC asserts RXERR on its system receive interface.",
+#endif
+    XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK,
+    0,
+    XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH,
+    XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD =
+{
+    "RESERVED0",
+#if RU_INCLUDE_DESC
+    "",
+    "",
+#endif
+    XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD_MASK,
+    0,
+    XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD_WIDTH,
+    XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+/******************************************************************************
+ * Field: XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK
+ ******************************************************************************/
+const ru_field_rec XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD =
+{
+    "RSV_ERR_MASK",
+#if RU_INCLUDE_DESC
+    "",
+    "These bits define mask for bits [37:16] of RSV vector. If any of un-masked bits "
+    "(with the exception of bit 23 that is GOOD_PACKET_RECEIVED) is set, "
+    "XLMAC asserts RXERR on its system receive interface.",
+#endif
+    XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK,
+    0,
+    XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH,
+    XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw
+#endif
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+/******************************************************************************
+ * Register: XLMAC_CONF_DIR_ACC_DATA_WRITE
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_DIR_ACC_DATA_WRITE_FIELDS[] =
+{
+    &XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_DIR_ACC_DATA_WRITE_REG = 
+{
+    "DIR_ACC_DATA_WRITE",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 32-bit Direct Access Data Write Register",
+    "",
+#endif
+    XLMAC_CONF_DIR_ACC_DATA_WRITE_REG_OFFSET,
+    0,
+    0,
+    229,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    XLMAC_CONF_DIR_ACC_DATA_WRITE_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_DIR_ACC_DATA_READ
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_DIR_ACC_DATA_READ_FIELDS[] =
+{
+    &XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_DIR_ACC_DATA_READ_REG = 
+{
+    "DIR_ACC_DATA_READ",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 32-bit Direct Access Data Read Register",
+    "",
+#endif
+    XLMAC_CONF_DIR_ACC_DATA_READ_REG_OFFSET,
+    0,
+    0,
+    230,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    XLMAC_CONF_DIR_ACC_DATA_READ_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_INDIR_ACC_ADDR_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_INDIR_ACC_ADDR_0_FIELDS[] =
+{
+    &XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD,
+    &XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD,
+    &XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD,
+    &XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD,
+    &XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD,
+    &XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_INDIR_ACC_ADDR_0_REG = 
+{
+    "INDIR_ACC_ADDR_0",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Indirect Access Address Register",
+    "",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET,
+    0,
+    0,
+    231,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    XLMAC_CONF_INDIR_ACC_ADDR_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_INDIR_ACC_DATA_LOW_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_INDIR_ACC_DATA_LOW_0_FIELDS[] =
+{
+    &XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_0_REG = 
+{
+    "INDIR_ACC_DATA_LOW_0",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Indirect Access Data Low Register",
+    "",
+#endif
+    XLMAC_CONF_INDIR_ACC_DATA_LOW_0_REG_OFFSET,
+    0,
+    0,
+    232,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    XLMAC_CONF_INDIR_ACC_DATA_LOW_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_INDIR_ACC_DATA_HIGH_0
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_FIELDS[] =
+{
+    &XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_REG = 
+{
+    "INDIR_ACC_DATA_HIGH_0",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Indirect Access Data High Register",
+    "",
+#endif
+    XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_REG_OFFSET,
+    0,
+    0,
+    233,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_INDIR_ACC_ADDR_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_INDIR_ACC_ADDR_1_FIELDS[] =
+{
+    &XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD,
+    &XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD,
+    &XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD,
+    &XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD,
+    &XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD,
+    &XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_INDIR_ACC_ADDR_1_REG = 
+{
+    "INDIR_ACC_ADDR_1",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Indirect Access Address Register",
+    "",
+#endif
+    XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET,
+    0,
+    0,
+    234,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    6,
+    XLMAC_CONF_INDIR_ACC_ADDR_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_INDIR_ACC_DATA_LOW_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_INDIR_ACC_DATA_LOW_1_FIELDS[] =
+{
+    &XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_1_REG = 
+{
+    "INDIR_ACC_DATA_LOW_1",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Indirect Access Data Low Register",
+    "",
+#endif
+    XLMAC_CONF_INDIR_ACC_DATA_LOW_1_REG_OFFSET,
+    0,
+    0,
+    235,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    XLMAC_CONF_INDIR_ACC_DATA_LOW_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_INDIR_ACC_DATA_HIGH_1
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_FIELDS[] =
+{
+    &XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_REG = 
+{
+    "INDIR_ACC_DATA_HIGH_1",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Indirect Access Data High Register",
+    "",
+#endif
+    XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_REG_OFFSET,
+    0,
+    0,
+    236,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    1,
+    XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_CONFIG
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_CONFIG_FIELDS[] =
+{
+    &XLMAC_CONF_CONFIG_RESERVED0_FIELD,
+    &XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD,
+    &XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD,
+    &XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD,
+    &XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD,
+    &XLMAC_CONF_CONFIG_MAC_MODE_FIELD,
+    &XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD,
+    &XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD,
+    &XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_CONFIG_REG = 
+{
+    "CONFIG",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Configure Register",
+    "",
+#endif
+    XLMAC_CONF_CONFIG_REG_OFFSET,
+    0,
+    0,
+    237,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    9,
+    XLMAC_CONF_CONFIG_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_INTERRUPT_CHECK
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_INTERRUPT_CHECK_FIELDS[] =
+{
+    &XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD,
+    &XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_INTERRUPT_CHECK_REG = 
+{
+    "INTERRUPT_CHECK",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Interrupt Check Register",
+    "",
+#endif
+    XLMAC_CONF_INTERRUPT_CHECK_REG_OFFSET,
+    0,
+    0,
+    238,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    XLMAC_CONF_INTERRUPT_CHECK_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_PORT_0_RXERR_MASK
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_PORT_0_RXERR_MASK_FIELDS[] =
+{
+    &XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD,
+    &XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_PORT_0_RXERR_MASK_REG = 
+{
+    "PORT_0_RXERR_MASK",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Port 3 RXERR Mask Register",
+    "",
+#endif
+    XLMAC_CONF_PORT_0_RXERR_MASK_REG_OFFSET,
+    0,
+    0,
+    239,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    XLMAC_CONF_PORT_0_RXERR_MASK_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_PORT_1_RXERR_MASK
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_PORT_1_RXERR_MASK_FIELDS[] =
+{
+    &XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD,
+    &XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_PORT_1_RXERR_MASK_REG = 
+{
+    "PORT_1_RXERR_MASK",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Port 3 RXERR Mask Register",
+    "",
+#endif
+    XLMAC_CONF_PORT_1_RXERR_MASK_REG_OFFSET,
+    0,
+    0,
+    240,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    XLMAC_CONF_PORT_1_RXERR_MASK_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_PORT_2_RXERR_MASK
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_PORT_2_RXERR_MASK_FIELDS[] =
+{
+    &XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD,
+    &XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_PORT_2_RXERR_MASK_REG = 
+{
+    "PORT_2_RXERR_MASK",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Port 3 RXERR Mask Register",
+    "",
+#endif
+    XLMAC_CONF_PORT_2_RXERR_MASK_REG_OFFSET,
+    0,
+    0,
+    241,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    XLMAC_CONF_PORT_2_RXERR_MASK_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Register: XLMAC_CONF_PORT_3_RXERR_MASK
+ ******************************************************************************/
+#if RU_INCLUDE_FIELD_DB
+static const ru_field_rec *XLMAC_CONF_PORT_3_RXERR_MASK_FIELDS[] =
+{
+    &XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD,
+    &XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD,
+};
+
+#endif /* RU_INCLUDE_FIELD_DB */
+
+const ru_reg_rec XLMAC_CONF_PORT_3_RXERR_MASK_REG = 
+{
+    "PORT_3_RXERR_MASK",
+#if RU_INCLUDE_DESC
+    "XLMAC 1 Port 3 RXERR Mask Register",
+    "",
+#endif
+    XLMAC_CONF_PORT_3_RXERR_MASK_REG_OFFSET,
+    0,
+    0,
+    242,
+#if RU_INCLUDE_ACCESS
+    ru_access_rw,
+#endif
+#if RU_INCLUDE_FIELD_DB
+    2,
+    XLMAC_CONF_PORT_3_RXERR_MASK_FIELDS,
+#endif /* RU_INCLUDE_FIELD_DB */
+    ru_reg_size_32
+};
+
+/******************************************************************************
+ * Block: XLMAC_CONF
+ ******************************************************************************/
+static const ru_reg_rec *XLMAC_CONF_REGS[] =
+{
+    &XLMAC_CONF_DIR_ACC_DATA_WRITE_REG,
+    &XLMAC_CONF_DIR_ACC_DATA_READ_REG,
+    &XLMAC_CONF_INDIR_ACC_ADDR_0_REG,
+    &XLMAC_CONF_INDIR_ACC_DATA_LOW_0_REG,
+    &XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_REG,
+    &XLMAC_CONF_INDIR_ACC_ADDR_1_REG,
+    &XLMAC_CONF_INDIR_ACC_DATA_LOW_1_REG,
+    &XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_REG,
+    &XLMAC_CONF_CONFIG_REG,
+    &XLMAC_CONF_INTERRUPT_CHECK_REG,
+    &XLMAC_CONF_PORT_0_RXERR_MASK_REG,
+    &XLMAC_CONF_PORT_1_RXERR_MASK_REG,
+    &XLMAC_CONF_PORT_2_RXERR_MASK_REG,
+    &XLMAC_CONF_PORT_3_RXERR_MASK_REG,
+};
+
+unsigned long XLMAC_CONF_ADDRS[] =
+{
+    0x8013d000,
+    0x8013d200,
+};
+
+const ru_block_rec XLMAC_CONF_BLOCK = 
+{
+    "XLMAC_CONF",
+    XLMAC_CONF_ADDRS,
+    2,
+    14,
+    XLMAC_CONF_REGS
+};
+
+/* End of file BCM6858_A0XLMAC_CONF.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0_LPORT_AG.c b/drivers/net/bcmbca/lport/ag/BCM6858_A0_LPORT_AG.c
new file mode 100644
index 0000000000..b5a4aaf2ed
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0_LPORT_AG.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "ru.h"
+
+/******************************************************************************
+ * Chip: BCM6858_A0
+ ******************************************************************************/
+const ru_block_rec *RU_LPORT_BLOCKS[] =
+{
+    &LPORT_XLMAC_BLOCK,
+    &LPORT_MIB_BLOCK,
+    &LPORT_SRDS_BLOCK,
+    &LPORT_LED_BLOCK,
+    &LPORT_CTRL_BLOCK,
+    &LPORT_RGMII_BLOCK,
+    &XLMAC_CONF_BLOCK,
+    &MIB_CONF_BLOCK,
+    &LPORT_MDIO_BLOCK,
+    &LPORT_INTR_BLOCK,
+    &LPORT_MAB_BLOCK,
+    NULL
+};
+
+/* End of file BCM6858_A0.c */
diff --git a/drivers/net/bcmbca/lport/ag/BCM6858_A0_LPORT_AG.h b/drivers/net/bcmbca/lport/ag/BCM6858_A0_LPORT_AG.h
new file mode 100644
index 0000000000..96ec78127f
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/BCM6858_A0_LPORT_AG.h
@@ -0,0 +1,6151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_A0_AG_H_
+#define _BCM6858_A0_AG_H_
+
+#include "ru.h"
+
+/******************************************************************************
+ * BCM6858_A0 Fields
+ ******************************************************************************/
+extern const ru_field_rec LPORT_XLMAC_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_CTRL_RESERVED0_FIELD_MASK  0xffffffffffff8000UL
+#define LPORT_XLMAC_CTRL_RESERVED0_FIELD_WIDTH 49
+#define LPORT_XLMAC_CTRL_RESERVED0_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD;
+#define LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD_MASK  0x0000000000004000UL
+#define LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD;
+#define LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD_MASK  0x0000000000002000UL
+#define LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD;
+#define LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD_MASK  0x0000000000001000UL
+#define LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD;
+#define LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_MASK  0x0000000000000800UL
+#define LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD;
+#define LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD_MASK  0x0000000000000400UL
+#define LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD_SHIFT 10
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_RSVD_5_FIELD;
+#define LPORT_XLMAC_CTRL_RSVD_5_FIELD_MASK  0x0000000000000200UL
+#define LPORT_XLMAC_CTRL_RSVD_5_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_RSVD_5_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD;
+#define LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_MASK  0x0000000000000100UL
+#define LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_RSVD_4_FIELD;
+#define LPORT_XLMAC_CTRL_RSVD_4_FIELD_MASK  0x0000000000000080UL
+#define LPORT_XLMAC_CTRL_RSVD_4_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_RSVD_4_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_SOFT_RESET_FIELD;
+#define LPORT_XLMAC_CTRL_SOFT_RESET_FIELD_MASK  0x0000000000000040UL
+#define LPORT_XLMAC_CTRL_SOFT_RESET_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_SOFT_RESET_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD;
+#define LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD_MASK  0x0000000000000020UL
+#define LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD;
+#define LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD_MASK  0x0000000000000010UL
+#define LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_RSVD_1_FIELD;
+#define LPORT_XLMAC_CTRL_RSVD_1_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_CTRL_RSVD_1_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_RSVD_1_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD;
+#define LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_RX_EN_FIELD;
+#define LPORT_XLMAC_CTRL_RX_EN_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_CTRL_RX_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_RX_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_CTRL_TX_EN_FIELD;
+#define LPORT_XLMAC_CTRL_TX_EN_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_CTRL_TX_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_CTRL_TX_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_MODE_RESERVED0_FIELD;
+#define LPORT_XLMAC_MODE_RESERVED0_FIELD_MASK  0xffffffffffffff80UL
+#define LPORT_XLMAC_MODE_RESERVED0_FIELD_WIDTH 57
+#define LPORT_XLMAC_MODE_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_XLMAC_MODE_SPEED_MODE_FIELD;
+#define LPORT_XLMAC_MODE_SPEED_MODE_FIELD_MASK  0x0000000000000070UL
+#define LPORT_XLMAC_MODE_SPEED_MODE_FIELD_WIDTH 3
+#define LPORT_XLMAC_MODE_SPEED_MODE_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD;
+#define LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD_WIDTH 1
+#define LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_MODE_HDR_MODE_FIELD;
+#define LPORT_XLMAC_MODE_HDR_MODE_FIELD_MASK  0x0000000000000007UL
+#define LPORT_XLMAC_MODE_HDR_MODE_FIELD_WIDTH 3
+#define LPORT_XLMAC_MODE_HDR_MODE_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_SPARE0_RESERVED0_FIELD;
+#define LPORT_XLMAC_SPARE0_RESERVED0_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_SPARE0_RESERVED0_FIELD_WIDTH 32
+#define LPORT_XLMAC_SPARE0_RESERVED0_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_SPARE0_RSVD_FIELD;
+#define LPORT_XLMAC_SPARE0_RSVD_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_SPARE0_RSVD_FIELD_WIDTH 32
+#define LPORT_XLMAC_SPARE0_RSVD_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_SPARE1_RESERVED0_FIELD;
+#define LPORT_XLMAC_SPARE1_RESERVED0_FIELD_MASK  0xfffffffffffffffcUL
+#define LPORT_XLMAC_SPARE1_RESERVED0_FIELD_WIDTH 62
+#define LPORT_XLMAC_SPARE1_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_SPARE1_RSVD_FIELD;
+#define LPORT_XLMAC_SPARE1_RSVD_FIELD_MASK  0x0000000000000003UL
+#define LPORT_XLMAC_SPARE1_RSVD_FIELD_WIDTH 2
+#define LPORT_XLMAC_SPARE1_RSVD_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD_MASK  0xfffffc0000000000UL
+#define LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD_WIDTH 22
+#define LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD_SHIFT 42
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD;
+#define LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD_MASK  0x000003c000000000UL
+#define LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD_WIDTH 4
+#define LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD_SHIFT 38
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD;
+#define LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD_MASK  0x0000002000000000UL
+#define LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD_WIDTH 1
+#define LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD_SHIFT 37
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD;
+#define LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_MASK  0x0000001e00000000UL
+#define LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_WIDTH 4
+#define LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_SHIFT 33
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD;
+#define LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD_MASK  0x00000001fe000000UL
+#define LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD_WIDTH 8
+#define LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD_SHIFT 25
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD;
+#define LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD_MASK  0x0000000001f80000UL
+#define LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD_WIDTH 6
+#define LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD_SHIFT 19
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD;
+#define LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD_MASK  0x000000000007f000UL
+#define LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD_WIDTH 7
+#define LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD;
+#define LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD_MASK  0x0000000000000fe0UL
+#define LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD_WIDTH 7
+#define LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD;
+#define LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD_MASK  0x0000000000000010UL
+#define LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD;
+#define LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD_WIDTH 1
+#define LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_DISCARD_FIELD;
+#define LPORT_XLMAC_TX_CTRL_DISCARD_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_TX_CTRL_DISCARD_FIELD_WIDTH 1
+#define LPORT_XLMAC_TX_CTRL_DISCARD_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD;
+#define LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD_MASK  0x0000000000000003UL
+#define LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD_WIDTH 2
+#define LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD;
+#define LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD_MASK  0xfffffc0000000000UL
+#define LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH 22
+#define LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT 42
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD;
+#define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD_MASK  0x000003ff00000000UL
+#define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD_WIDTH 10
+#define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD;
+#define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD;
+#define LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD_MASK  0xffff000000000000UL
+#define LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD_WIDTH 16
+#define LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD_SHIFT 48
+
+extern const ru_field_rec LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD;
+#define LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD_MASK  0x0000ffffffffffffUL
+#define LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD_WIDTH 48
+#define LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD;
+#define LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD_MASK  0xffff000000000000UL
+#define LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD_WIDTH 16
+#define LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD_SHIFT 48
+
+extern const ru_field_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD;
+#define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD_MASK  0x0000ffff00000000UL
+#define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD_WIDTH 16
+#define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD;
+#define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD_MASK  0xffffffffffff0000UL
+#define LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD_WIDTH 48
+#define LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD;
+#define LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD_MASK  0x0000000000008000UL
+#define LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD;
+#define LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD_MASK  0x0000000000004000UL
+#define LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD;
+#define LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD_MASK  0x0000000000002000UL
+#define LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD;
+#define LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD_MASK  0x0000000000001000UL
+#define LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD;
+#define LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD_MASK  0x0000000000000800UL
+#define LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD;
+#define LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD_MASK  0x00000000000007f0UL
+#define LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD_WIDTH 7
+#define LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD;
+#define LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD;
+#define LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD;
+#define LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD;
+#define LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD;
+#define LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD_MASK  0xffff000000000000UL
+#define LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD_WIDTH 16
+#define LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD_SHIFT 48
+
+extern const ru_field_rec LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD;
+#define LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD_MASK  0x0000ffffffffffffUL
+#define LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD_WIDTH 48
+#define LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD;
+#define LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD_MASK  0xffff000000000000UL
+#define LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD_WIDTH 16
+#define LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD_SHIFT 48
+
+extern const ru_field_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD;
+#define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD_MASK  0x0000ffff00000000UL
+#define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD_WIDTH 16
+#define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD;
+#define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD;
+#define LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD_MASK  0xffffffffffffc000UL
+#define LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD_WIDTH 50
+#define LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD;
+#define LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_MASK  0x0000000000003fffUL
+#define LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_WIDTH 14
+#define LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD;
+#define LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD_MASK  0xfffffffc00000000UL
+#define LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD_WIDTH 30
+#define LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD_SHIFT 34
+
+extern const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD;
+#define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_MASK  0x0000000200000000UL
+#define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_SHIFT 33
+
+extern const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD;
+#define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_MASK  0x0000000100000000UL
+#define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD;
+#define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_WIDTH 16
+#define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD;
+#define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_WIDTH 16
+#define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD_MASK  0xffffffffffffff00UL
+#define LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD_WIDTH 56
+#define LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD;
+#define LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_MASK  0x0000000000000080UL
+#define LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD;
+#define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_MASK  0x0000000000000040UL
+#define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD;
+#define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_MASK  0x0000000000000020UL
+#define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD;
+#define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_MASK  0x0000000000000010UL
+#define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD;
+#define LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD;
+#define LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD;
+#define LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD;
+#define LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD;
+#define LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD_MASK  0xfffffffffffffff8UL
+#define LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD_WIDTH 61
+#define LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD;
+#define LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD;
+#define LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD;
+#define LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD;
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_MASK  0xfffffffffffffff8UL
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_WIDTH 61
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD;
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD;
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD;
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD_MASK  0xffffffe000000000UL
+#define LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD_WIDTH 27
+#define LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD_SHIFT 37
+
+extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD;
+#define LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_MASK  0x0000001fffe00000UL
+#define LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_WIDTH 16
+#define LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_SHIFT 21
+
+extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD;
+#define LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD_MASK  0x0000000000100000UL
+#define LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD_WIDTH 1
+#define LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD;
+#define LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD_MASK  0x0000000000080000UL
+#define LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD_WIDTH 1
+#define LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD_SHIFT 19
+
+extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD;
+#define LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD_MASK  0x0000000000040000UL
+#define LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD;
+#define LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD_MASK  0x0000000000020000UL
+#define LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD_SHIFT 17
+
+extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD;
+#define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_MASK  0x0000000000010000UL
+#define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD;
+#define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_WIDTH 16
+#define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD;
+#define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD_MASK  0xffffffe000000000UL
+#define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH 27
+#define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT 37
+
+extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD;
+#define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD_MASK  0x0000001f00000000UL
+#define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD_WIDTH 5
+#define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD;
+#define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD_MASK  0xffffffc000000000UL
+#define LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD_WIDTH 26
+#define LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD_SHIFT 38
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD_MASK  0x0000002000000000UL
+#define LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD_SHIFT 37
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD_MASK  0x0000001000000000UL
+#define LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD_SHIFT 36
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD_MASK  0x0000000800000000UL
+#define LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD_SHIFT 35
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_RSVD_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_RSVD_FIELD_MASK  0x0000000400000000UL
+#define LPORT_XLMAC_PFC_CTRL_RSVD_FIELD_WIDTH 1
+#define LPORT_XLMAC_PFC_CTRL_RSVD_FIELD_SHIFT 34
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD_MASK  0x0000000200000000UL
+#define LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD_WIDTH 1
+#define LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD_SHIFT 33
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD_MASK  0x0000000100000000UL
+#define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD_WIDTH 16
+#define LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_WIDTH 16
+#define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD_MASK  0xfffffffe00000000UL
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH 31
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT 33
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD_MASK  0x0000000100000000UL
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD_WIDTH 16
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD;
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD_WIDTH 16
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD;
+#define LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD_MASK  0xffffffffffff0000UL
+#define LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD_WIDTH 48
+#define LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD;
+#define LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_WIDTH 16
+#define LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD;
+#define LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD_MASK  0xffffffffffff0000UL
+#define LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD_WIDTH 48
+#define LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD;
+#define LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD_WIDTH 16
+#define LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_PFC_DA_RESERVED0_FIELD;
+#define LPORT_XLMAC_PFC_DA_RESERVED0_FIELD_MASK  0xffff000000000000UL
+#define LPORT_XLMAC_PFC_DA_RESERVED0_FIELD_WIDTH 16
+#define LPORT_XLMAC_PFC_DA_RESERVED0_FIELD_SHIFT 48
+
+extern const ru_field_rec LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD;
+#define LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD_MASK  0x0000ffffffffffffUL
+#define LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD_WIDTH 48
+#define LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD;
+#define LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD_MASK  0xffff000000000000UL
+#define LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD_WIDTH 16
+#define LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD_SHIFT 48
+
+extern const ru_field_rec LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD;
+#define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD_MASK  0x0000ffff00000000UL
+#define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD_WIDTH 16
+#define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD;
+#define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD_MASK  0xffffffffffffc000UL
+#define LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD_WIDTH 50
+#define LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD;
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD_MASK  0x0000000000003fc0UL
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD_WIDTH 8
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD;
+#define LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_MASK  0x0000000000000020UL
+#define LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_WIDTH 1
+#define LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD;
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_MASK  0x0000000000000010UL
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_WIDTH 1
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD;
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_WIDTH 1
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD;
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_WIDTH 1
+#define LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD;
+#define LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD;
+#define LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD;
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_MASK  0xfffffffff0000000UL
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_WIDTH 36
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD;
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_MASK  0x000000000ffff000UL
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_WIDTH 16
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD;
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_MASK  0x0000000000000f00UL
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_WIDTH 4
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD;
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_WIDTH 8
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD;
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_MASK  0xffffffffff000000UL
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_WIDTH 40
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD;
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_WIDTH 4
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD;
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_MASK  0x00000000000ff000UL
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_WIDTH 8
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD;
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_MASK  0x0000000000000f00UL
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_WIDTH 4
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD;
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_WIDTH 8
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD;
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_MASK  0xfffe000000000000UL
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_WIDTH 15
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_SHIFT 49
+
+extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD;
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_MASK  0x0001000000000000UL
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_WIDTH 1
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_SHIFT 48
+
+extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD;
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_MASK  0x0000ffff00000000UL
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_WIDTH 16
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD;
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_WIDTH 32
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD;
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffffffffffffff8UL
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_WIDTH 61
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD;
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_MASK  0x0000000000000007UL
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_WIDTH 3
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD;
+#define LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD_MASK  0xfffffffffffffe00UL
+#define LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD_WIDTH 55
+#define LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD;
+#define LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD_MASK  0x0000000000000100UL
+#define LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD;
+#define LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_MASK  0x0000000000000080UL
+#define LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD;
+#define LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_MASK  0x0000000000000040UL
+#define LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD;
+#define LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_MASK  0x0000000000000020UL
+#define LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD;
+#define LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD_MASK  0x0000000000000010UL
+#define LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD_WIDTH 1
+#define LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD;
+#define LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD;
+#define LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD;
+#define LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD;
+#define LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD_WIDTH 1
+#define LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD;
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD_MASK  0xffffffffffffff00UL
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD_WIDTH 56
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD;
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_MASK  0x0000000000000080UL
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD;
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_MASK  0x0000000000000040UL
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD;
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_MASK  0x0000000000000020UL
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD;
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD_MASK  0x0000000000000010UL
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD;
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD;
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD;
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD;
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD;
+#define LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD_MASK  0xfffffffffffffffcUL
+#define LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD_WIDTH 62
+#define LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD;
+#define LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD_WIDTH 1
+#define LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD;
+#define LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_WIDTH 1
+#define LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD_MASK  0xfffffffffffffffcUL
+#define LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD_WIDTH 62
+#define LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_EEE_CTRL_RSVD_FIELD;
+#define LPORT_XLMAC_EEE_CTRL_RSVD_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_EEE_CTRL_RSVD_FIELD_WIDTH 1
+#define LPORT_XLMAC_EEE_CTRL_RSVD_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD;
+#define LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD;
+#define LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD_MASK  0xffff000000000000UL
+#define LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD_WIDTH 16
+#define LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD_SHIFT 48
+
+extern const ru_field_rec LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD;
+#define LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_MASK  0x0000ffff00000000UL
+#define LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_WIDTH 16
+#define LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD;
+#define LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_WIDTH 32
+#define LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD;
+#define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD_WIDTH 32
+#define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD;
+#define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD;
+#define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_MASK  0xffffffffff000000UL
+#define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_WIDTH 40
+#define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD;
+#define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_MASK  0x0000000000ffffffUL
+#define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_WIDTH 24
+#define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD;
+#define LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_MASK  0xffffffffffffffffUL
+#define LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_WIDTH 64
+#define LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD;
+#define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD_WIDTH 32
+#define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD;
+#define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD;
+#define LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_MASK  0xffffffffffffffffUL
+#define LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_WIDTH 64
+#define LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD;
+#define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD_WIDTH 32
+#define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD;
+#define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD_MASK  0xfffffffffffe0000UL
+#define LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD_WIDTH 47
+#define LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD;
+#define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_MASK  0x0000000000010000UL
+#define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD;
+#define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_WIDTH 16
+#define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD;
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_MASK  0xffffffffffff0000UL
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_WIDTH 48
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD;
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_MASK  0x0000000000008000UL
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_WIDTH 1
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD;
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_MASK  0x0000000000007e00UL
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_WIDTH 6
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD;
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_MASK  0x00000000000001ffUL
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_WIDTH 9
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD;
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_MASK  0xffffffffffc00000UL
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_WIDTH 42
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_SHIFT 22
+
+extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD;
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_MASK  0x0000000000200000UL
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_SHIFT 21
+
+extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD;
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_MASK  0x00000000001ff800UL
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_WIDTH 10
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD;
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_MASK  0x0000000000000400UL
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_SHIFT 10
+
+extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD;
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_MASK  0x00000000000003ffUL
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_WIDTH 10
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_MASK  0xfffffff800000000UL
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_WIDTH 29
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_SHIFT 35
+
+extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD;
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_MASK  0x00000007fffffff8UL
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_WIDTH 32
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD;
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_WIDTH 1
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD;
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD;
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_WIDTH 1
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD;
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD_MASK  0xfffffff800000000UL
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH 29
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT 35
+
+extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD;
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD_MASK  0x0000000700000000UL
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD_WIDTH 3
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD;
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD_MASK  0xffffffffffffffe0UL
+#define LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD_WIDTH 59
+#define LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD;
+#define LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_MASK  0x0000000000000010UL
+#define LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD;
+#define LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD;
+#define LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD;
+#define LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_WIDTH 1
+#define LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD;
+#define LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD_WIDTH 1
+#define LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD;
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_MASK  0xffffffffffffffffUL
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_WIDTH 64
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD;
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD;
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD;
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_MASK  0xffffffffffffffffUL
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_WIDTH 64
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD;
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD;
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD;
+#define LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_MASK  0xffffffffffffffffUL
+#define LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_WIDTH 64
+#define LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD;
+#define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD;
+#define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD;
+#define LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_MASK  0xffffffffffffffffUL
+#define LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_WIDTH 64
+#define LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD;
+#define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD;
+#define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD;
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_MASK  0xffffffffffffffffUL
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_WIDTH 64
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD;
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD;
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD;
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_MASK  0xffffffffffffffffUL
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_WIDTH 64
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD;
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD;
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD;
+#define LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_MASK  0xffffffffffffffffUL
+#define LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_WIDTH 64
+#define LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD;
+#define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD;
+#define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD;
+#define LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_MASK  0xffffffffffffffffUL
+#define LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_WIDTH 64
+#define LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD;
+#define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD_MASK  0xffffffff00000000UL
+#define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD_SHIFT 32
+
+extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD;
+#define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD_WIDTH 32
+#define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD;
+#define LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD_MASK  0xffffffffffffffc0UL
+#define LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD_WIDTH 58
+#define LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD;
+#define LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD_MASK  0x000000000000003fUL
+#define LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD_WIDTH 6
+#define LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD;
+#define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_MASK  0xffffffffffffffc0UL
+#define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_WIDTH 58
+#define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD;
+#define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_MASK  0x000000000000003fUL
+#define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_WIDTH 6
+#define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD_MASK  0xffffffffff000000UL
+#define LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD_WIDTH 40
+#define LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD;
+#define LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_MASK  0x0000000000fff000UL
+#define LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_WIDTH 12
+#define LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD;
+#define LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_MASK  0x0000000000000fffUL
+#define LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_WIDTH 12
+#define LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD;
+#define LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD_MASK  0xfffffffffffffffcUL
+#define LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD_WIDTH 62
+#define LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD;
+#define LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD;
+#define LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_WIDTH 1
+#define LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD;
+#define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_MASK  0xfffffffffffffffcUL
+#define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_WIDTH 62
+#define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD;
+#define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_MASK  0xfffffffffffffffcUL
+#define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_WIDTH 62
+#define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD;
+#define LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD_MASK  0xfffffffffffffffcUL
+#define LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD_WIDTH 62
+#define LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD;
+#define LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD_MASK  0xfffffffffffffffcUL
+#define LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD_WIDTH 62
+#define LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD;
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD_MASK  0xfffffffffffffff0UL
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD_WIDTH 60
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD_MASK  0xffffffffffffc000UL
+#define LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD_WIDTH 50
+#define LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_MASK  0x0000000000002000UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_MASK  0x0000000000001000UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_MASK  0x0000000000000800UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_MASK  0x0000000000000400UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_SHIFT 10
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK  0x0000000000000200UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK  0x0000000000000100UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK  0x0000000000000080UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK  0x0000000000000040UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_MASK  0x0000000000000020UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_MASK  0x0000000000000010UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD_MASK  0xffffffffffffc000UL
+#define LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD_WIDTH 50
+#define LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_MASK  0x0000000000002000UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_MASK  0x0000000000001000UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_MASK  0x0000000000000800UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_MASK  0x0000000000000400UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_SHIFT 10
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK  0x0000000000000200UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK  0x0000000000000100UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK  0x0000000000000080UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK  0x0000000000000040UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_MASK  0x0000000000000020UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_MASK  0x0000000000000010UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_MASK  0x0000000000000008UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_MASK  0x0000000000000004UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_MASK  0x0000000000000002UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD;
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_MASK  0x0000000000000001UL
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_WIDTH 1
+#define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD;
+#define LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD_MASK  0xffffffffffff0000UL
+#define LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD_WIDTH 48
+#define LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD;
+#define LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD_WIDTH 16
+#define LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRX64_COUNT40_FIELD;
+#define LPORT_MIB_GRX64_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRX64_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRX64_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRX127_COUNT40_FIELD;
+#define LPORT_MIB_GRX127_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRX127_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRX127_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRX255_COUNT40_FIELD;
+#define LPORT_MIB_GRX255_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRX255_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRX255_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRX511_COUNT40_FIELD;
+#define LPORT_MIB_GRX511_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRX511_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRX511_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRX1023_COUNT40_FIELD;
+#define LPORT_MIB_GRX1023_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRX1023_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRX1023_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRX1518_COUNT40_FIELD;
+#define LPORT_MIB_GRX1518_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRX1518_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRX1518_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRX1522_COUNT40_FIELD;
+#define LPORT_MIB_GRX1522_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRX1522_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRX1522_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRX2047_COUNT40_FIELD;
+#define LPORT_MIB_GRX2047_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRX2047_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRX2047_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRX4095_COUNT40_FIELD;
+#define LPORT_MIB_GRX4095_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRX4095_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRX4095_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRX9216_COUNT40_FIELD;
+#define LPORT_MIB_GRX9216_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRX9216_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRX9216_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRX16383_COUNT40_FIELD;
+#define LPORT_MIB_GRX16383_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRX16383_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRX16383_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPKT_COUNT40_FIELD;
+#define LPORT_MIB_GRXPKT_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPKT_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPKT_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXUCA_COUNT40_FIELD;
+#define LPORT_MIB_GRXUCA_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXUCA_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXUCA_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXMCA_COUNT40_FIELD;
+#define LPORT_MIB_GRXMCA_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXMCA_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXMCA_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXBCA_COUNT40_FIELD;
+#define LPORT_MIB_GRXBCA_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXBCA_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXBCA_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXFCS_COUNT40_FIELD;
+#define LPORT_MIB_GRXFCS_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXFCS_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXFCS_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXCF_COUNT40_FIELD;
+#define LPORT_MIB_GRXCF_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXCF_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXCF_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPF_COUNT40_FIELD;
+#define LPORT_MIB_GRXPF_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPF_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPF_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPP_COUNT40_FIELD;
+#define LPORT_MIB_GRXPP_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPP_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPP_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXUO_COUNT40_FIELD;
+#define LPORT_MIB_GRXUO_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXUO_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXUO_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXUDA_COUNT40_FIELD;
+#define LPORT_MIB_GRXUDA_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXUDA_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXUDA_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXWSA_COUNT40_FIELD;
+#define LPORT_MIB_GRXWSA_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXWSA_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXWSA_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXALN_COUNT40_FIELD;
+#define LPORT_MIB_GRXALN_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXALN_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXALN_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXFLR_COUNT40_FIELD;
+#define LPORT_MIB_GRXFLR_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXFLR_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXFLR_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXFRERR_COUNT40_FIELD;
+#define LPORT_MIB_GRXFRERR_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXFRERR_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXFRERR_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXFCR_COUNT40_FIELD;
+#define LPORT_MIB_GRXFCR_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXFCR_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXFCR_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXOVR_COUNT40_FIELD;
+#define LPORT_MIB_GRXOVR_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXOVR_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXOVR_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXJBR_COUNT40_FIELD;
+#define LPORT_MIB_GRXJBR_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXJBR_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXJBR_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXMTUE_COUNT40_FIELD;
+#define LPORT_MIB_GRXMTUE_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXMTUE_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXMTUE_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXMCRC_COUNT40_FIELD;
+#define LPORT_MIB_GRXMCRC_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXMCRC_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXMCRC_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPRM_COUNT40_FIELD;
+#define LPORT_MIB_GRXPRM_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPRM_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPRM_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXVLN_COUNT40_FIELD;
+#define LPORT_MIB_GRXVLN_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXVLN_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXVLN_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXDVLN_COUNT40_FIELD;
+#define LPORT_MIB_GRXDVLN_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXDVLN_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXDVLN_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXTRFU_COUNT40_FIELD;
+#define LPORT_MIB_GRXTRFU_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXTRFU_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXTRFU_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPOK_COUNT40_FIELD;
+#define LPORT_MIB_GRXPOK_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPOK_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPOK_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCP0_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCP0_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCP0_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCP0_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCP1_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCP1_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCP1_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCP1_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCP2_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCP2_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCP2_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCP2_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCP3_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCP3_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCP3_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCP3_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCP4_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCP4_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCP4_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCP4_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCP5_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCP5_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCP5_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCP5_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCP6_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCP6_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCP6_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCP6_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPFCP7_COUNT40_FIELD;
+#define LPORT_MIB_GRXPFCP7_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPFCP7_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPFCP7_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXSCHCRC_COUNT40_FIELD;
+#define LPORT_MIB_GRXSCHCRC_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXSCHCRC_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXSCHCRC_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXBYT_COUNT48_FIELD;
+#define LPORT_MIB_GRXBYT_COUNT48_FIELD_MASK  0x0000ffffffffffffUL
+#define LPORT_MIB_GRXBYT_COUNT48_FIELD_WIDTH 48
+#define LPORT_MIB_GRXBYT_COUNT48_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXRPKT_COUNT40_FIELD;
+#define LPORT_MIB_GRXRPKT_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXRPKT_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXRPKT_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXUND_COUNT40_FIELD;
+#define LPORT_MIB_GRXUND_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXUND_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXUND_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXFRG_COUNT40_FIELD;
+#define LPORT_MIB_GRXFRG_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXFRG_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXFRG_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXRBYT_COUNT48_FIELD;
+#define LPORT_MIB_GRXRBYT_COUNT48_FIELD_MASK  0x0000ffffffffffffUL
+#define LPORT_MIB_GRXRBYT_COUNT48_FIELD_WIDTH 48
+#define LPORT_MIB_GRXRBYT_COUNT48_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTX64_COUNT40_FIELD;
+#define LPORT_MIB_GTX64_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTX64_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTX64_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTX127_COUNT40_FIELD;
+#define LPORT_MIB_GTX127_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTX127_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTX127_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTX255_COUNT40_FIELD;
+#define LPORT_MIB_GTX255_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTX255_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTX255_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTX511_COUNT40_FIELD;
+#define LPORT_MIB_GTX511_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTX511_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTX511_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTX1023_COUNT40_FIELD;
+#define LPORT_MIB_GTX1023_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTX1023_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTX1023_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTX1518_COUNT40_FIELD;
+#define LPORT_MIB_GTX1518_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTX1518_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTX1518_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTX1522_COUNT40_FIELD;
+#define LPORT_MIB_GTX1522_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTX1522_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTX1522_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTX2047_COUNT40_FIELD;
+#define LPORT_MIB_GTX2047_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTX2047_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTX2047_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTX4095_COUNT40_FIELD;
+#define LPORT_MIB_GTX4095_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTX4095_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTX4095_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTX9216_COUNT40_FIELD;
+#define LPORT_MIB_GTX9216_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTX9216_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTX9216_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTX16383_COUNT40_FIELD;
+#define LPORT_MIB_GTX16383_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTX16383_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTX16383_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPOK_COUNT40_FIELD;
+#define LPORT_MIB_GTXPOK_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPOK_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPOK_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPKT_COUNT40_FIELD;
+#define LPORT_MIB_GTXPKT_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPKT_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPKT_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXUCA_COUNT40_FIELD;
+#define LPORT_MIB_GTXUCA_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXUCA_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXUCA_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXMCA_COUNT40_FIELD;
+#define LPORT_MIB_GTXMCA_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXMCA_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXMCA_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXBCA_COUNT40_FIELD;
+#define LPORT_MIB_GTXBCA_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXBCA_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXBCA_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPF_COUNT40_FIELD;
+#define LPORT_MIB_GTXPF_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPF_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPF_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPFC_COUNT40_FIELD;
+#define LPORT_MIB_GTXPFC_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPFC_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPFC_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXJBR_COUNT40_FIELD;
+#define LPORT_MIB_GTXJBR_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXJBR_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXJBR_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXFCS_COUNT40_FIELD;
+#define LPORT_MIB_GTXFCS_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXFCS_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXFCS_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXCF_COUNT40_FIELD;
+#define LPORT_MIB_GTXCF_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXCF_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXCF_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXOVR_COUNT40_FIELD;
+#define LPORT_MIB_GTXOVR_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXOVR_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXOVR_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXDFR_COUNT40_FIELD;
+#define LPORT_MIB_GTXDFR_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXDFR_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXDFR_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXEDF_COUNT40_FIELD;
+#define LPORT_MIB_GTXEDF_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXEDF_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXEDF_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXSCL_COUNT40_FIELD;
+#define LPORT_MIB_GTXSCL_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXSCL_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXSCL_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXMCL_COUNT40_FIELD;
+#define LPORT_MIB_GTXMCL_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXMCL_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXMCL_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXLCL_COUNT40_FIELD;
+#define LPORT_MIB_GTXLCL_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXLCL_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXLCL_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXXCL_COUNT40_FIELD;
+#define LPORT_MIB_GTXXCL_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXXCL_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXXCL_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXFRG_COUNT40_FIELD;
+#define LPORT_MIB_GTXFRG_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXFRG_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXFRG_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXERR_COUNT40_FIELD;
+#define LPORT_MIB_GTXERR_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXERR_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXERR_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXVLN_COUNT40_FIELD;
+#define LPORT_MIB_GTXVLN_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXVLN_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXVLN_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXDVLN_COUNT40_FIELD;
+#define LPORT_MIB_GTXDVLN_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXDVLN_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXDVLN_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXRPKT_COUNT40_FIELD;
+#define LPORT_MIB_GTXRPKT_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXRPKT_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXRPKT_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXUFL_COUNT40_FIELD;
+#define LPORT_MIB_GTXUFL_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXUFL_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXUFL_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPFCP0_COUNT40_FIELD;
+#define LPORT_MIB_GTXPFCP0_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPFCP0_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPFCP0_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPFCP1_COUNT40_FIELD;
+#define LPORT_MIB_GTXPFCP1_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPFCP1_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPFCP1_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPFCP2_COUNT40_FIELD;
+#define LPORT_MIB_GTXPFCP2_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPFCP2_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPFCP2_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPFCP3_COUNT40_FIELD;
+#define LPORT_MIB_GTXPFCP3_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPFCP3_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPFCP3_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPFCP4_COUNT40_FIELD;
+#define LPORT_MIB_GTXPFCP4_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPFCP4_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPFCP4_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPFCP5_COUNT40_FIELD;
+#define LPORT_MIB_GTXPFCP5_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPFCP5_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPFCP5_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPFCP6_COUNT40_FIELD;
+#define LPORT_MIB_GTXPFCP6_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPFCP6_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPFCP6_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXPFCP7_COUNT40_FIELD;
+#define LPORT_MIB_GTXPFCP7_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXPFCP7_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXPFCP7_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXNCL_COUNT40_FIELD;
+#define LPORT_MIB_GTXNCL_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXNCL_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXNCL_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXBYT_COUNT48_FIELD;
+#define LPORT_MIB_GTXBYT_COUNT48_FIELD_MASK  0x0000ffffffffffffUL
+#define LPORT_MIB_GTXBYT_COUNT48_FIELD_WIDTH 48
+#define LPORT_MIB_GTXBYT_COUNT48_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXLPI_COUNT32_FIELD;
+#define LPORT_MIB_GRXLPI_COUNT32_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_MIB_GRXLPI_COUNT32_FIELD_WIDTH 32
+#define LPORT_MIB_GRXLPI_COUNT32_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXDLPI_COUNT32_FIELD;
+#define LPORT_MIB_GRXDLPI_COUNT32_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_MIB_GRXDLPI_COUNT32_FIELD_WIDTH 32
+#define LPORT_MIB_GRXDLPI_COUNT32_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXLPI_COUNT32_FIELD;
+#define LPORT_MIB_GTXLPI_COUNT32_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_MIB_GTXLPI_COUNT32_FIELD_WIDTH 32
+#define LPORT_MIB_GTXLPI_COUNT32_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXDLPI_COUNT32_FIELD;
+#define LPORT_MIB_GTXDLPI_COUNT32_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_MIB_GTXDLPI_COUNT32_FIELD_WIDTH 32
+#define LPORT_MIB_GTXDLPI_COUNT32_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXPTLLFC_COUNT40_FIELD;
+#define LPORT_MIB_GRXPTLLFC_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXPTLLFC_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXPTLLFC_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXLTLLFC_COUNT40_FIELD;
+#define LPORT_MIB_GRXLTLLFC_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXLTLLFC_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXLTLLFC_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD;
+#define LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MIB_GTXLTLLFC_COUNT40_FIELD;
+#define LPORT_MIB_GTXLTLLFC_COUNT40_FIELD_MASK  0x000000ffffffffffUL
+#define LPORT_MIB_GTXLTLLFC_COUNT40_FIELD_WIDTH 40
+#define LPORT_MIB_GTXLTLLFC_COUNT40_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD_WIDTH 16
+#define LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD_WIDTH 16
+#define LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_MASK  0x00000000fff80000UL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_WIDTH 13
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD_MASK  0x0000000000040000UL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_MASK  0x0000000000020000UL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_SHIFT 17
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD_MASK  0x0000000000010000UL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_WIDTH 32
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_MASK  0x00000000fff80000UL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_WIDTH 13
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD_MASK  0x0000000000040000UL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_MASK  0x0000000000020000UL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_SHIFT 17
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD_MASK  0x0000000000010000UL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_WIDTH 32
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_MASK  0x00000000fff80000UL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_WIDTH 13
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD_MASK  0x0000000000040000UL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_MASK  0x0000000000020000UL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_SHIFT 17
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD_MASK  0x0000000000010000UL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_WIDTH 32
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_MASK  0x00000000fff80000UL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_WIDTH 13
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD_MASK  0x0000000000040000UL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_MASK  0x0000000000020000UL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_SHIFT 17
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD_MASK  0x0000000000010000UL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD_WIDTH 1
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_MASK  0x00000000ffffffffUL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_WIDTH 32
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD_WIDTH 16
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD_MASK  0x00000000fff80000UL
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD_WIDTH 13
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD_MASK  0x0000000000040000UL
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD_WIDTH 1
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD_MASK  0x000000000003e000UL
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD_WIDTH 5
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD_MASK  0x0000000000001f00UL
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD_WIDTH 5
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD_MASK  0x00000000000000c0UL
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD_MASK  0x0000000000000038UL
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD_WIDTH 3
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD_MASK  0x0000000000000004UL
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD_WIDTH 1
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD_MASK  0x0000000000000002UL
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD_WIDTH 1
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD_MASK  0x0000000000000001UL
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD_WIDTH 1
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD_MASK  0x00000000fffff800UL
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD_WIDTH 21
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD_MASK  0x0000000000000600UL
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD_MASK  0x0000000000000180UL
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD_MASK  0x0000000000000040UL
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD_WIDTH 1
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD_MASK  0x0000000000000030UL
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD_MASK  0x000000000000000cUL
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD_MASK  0x0000000000000003UL
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD_MASK  0x00000000fff80000UL
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD_WIDTH 13
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD_MASK  0x0000000000040000UL
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD_WIDTH 1
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD_MASK  0x000000000003e000UL
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD_WIDTH 5
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD_MASK  0x0000000000001f00UL
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD_WIDTH 5
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD_MASK  0x00000000000000c0UL
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD_MASK  0x0000000000000038UL
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD_WIDTH 3
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD_MASK  0x0000000000000004UL
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD_WIDTH 1
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD_MASK  0x0000000000000002UL
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD_WIDTH 1
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD_MASK  0x0000000000000001UL
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD_WIDTH 1
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD_MASK  0x00000000fffff800UL
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD_WIDTH 21
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD_MASK  0x0000000000000600UL
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD_MASK  0x0000000000000180UL
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD_MASK  0x0000000000000040UL
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD_WIDTH 1
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD_MASK  0x0000000000000030UL
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD_MASK  0x000000000000000cUL
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD;
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD_MASK  0x0000000000000003UL
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD_WIDTH 2
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_LED_CNTRL_RESERVED0_FIELD;
+#define LPORT_LED_CNTRL_RESERVED0_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_LED_CNTRL_RESERVED0_FIELD_WIDTH 16
+#define LPORT_LED_CNTRL_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD;
+#define LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD_MASK  0x0000000000008000UL
+#define LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD;
+#define LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD_MASK  0x0000000000004000UL
+#define LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD;
+#define LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD_MASK  0x0000000000002000UL
+#define LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD;
+#define LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD_MASK  0x0000000000001c00UL
+#define LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD_WIDTH 3
+#define LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD_SHIFT 10
+
+extern const ru_field_rec LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD;
+#define LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD_MASK  0x0000000000000200UL
+#define LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD;
+#define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_MASK  0x0000000000000100UL
+#define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD;
+#define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_MASK  0x0000000000000080UL
+#define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD;
+#define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_MASK  0x0000000000000040UL
+#define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD;
+#define LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_MASK  0x0000000000000020UL
+#define LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD;
+#define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_MASK  0x0000000000000010UL
+#define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD;
+#define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_MASK  0x0000000000000008UL
+#define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD;
+#define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_MASK  0x0000000000000004UL
+#define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_LED_CNTRL_TX_ACT_EN_FIELD;
+#define LPORT_LED_CNTRL_TX_ACT_EN_FIELD_MASK  0x0000000000000002UL
+#define LPORT_LED_CNTRL_TX_ACT_EN_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_TX_ACT_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_LED_CNTRL_RX_ACT_EN_FIELD;
+#define LPORT_LED_CNTRL_RX_ACT_EN_FIELD_MASK  0x0000000000000001UL
+#define LPORT_LED_CNTRL_RX_ACT_EN_FIELD_WIDTH 1
+#define LPORT_LED_CNTRL_RX_ACT_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_MASK  0x00000000ff000000UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_WIDTH 8
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD_MASK  0x0000000000e00000UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD_SHIFT 21
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD_MASK  0x00000000001c0000UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_MASK  0x0000000000038000UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_MASK  0x0000000000007000UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_MASK  0x0000000000000e00UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_MASK  0x00000000000001c0UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_MASK  0x0000000000000038UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_MASK  0x0000000000000007UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_MASK  0x00000000ff000000UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_WIDTH 8
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD_MASK  0x0000000000e00000UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD_SHIFT 21
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD_MASK  0x00000000001c0000UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_MASK  0x0000000000038000UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_MASK  0x0000000000007000UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_MASK  0x0000000000000e00UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_MASK  0x00000000000001c0UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_MASK  0x0000000000000038UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_MASK  0x0000000000000007UL
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_WIDTH 3
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD;
+#define LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD_MASK  0x00000000fff80000UL
+#define LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD_WIDTH 13
+#define LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD;
+#define LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_MASK  0x0000000000040000UL
+#define LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_WIDTH 1
+#define LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD;
+#define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_MASK  0x0000000000020000UL
+#define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_WIDTH 1
+#define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_SHIFT 17
+
+extern const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD;
+#define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_MASK  0x0000000000010000UL
+#define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_WIDTH 1
+#define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD;
+#define LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_WIDTH 16
+#define LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD;
+#define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_WIDTH 16
+#define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD;
+#define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_WIDTH 16
+#define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD_MASK  0x00000000fffff800UL
+#define LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD_WIDTH 21
+#define LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD_MASK  0x0000000000000400UL
+#define LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD_WIDTH 1
+#define LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD_SHIFT 10
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD_MASK  0x0000000000000200UL
+#define LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD_WIDTH 1
+#define LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD_MASK  0x0000000000000100UL
+#define LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD_WIDTH 1
+#define LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD_MASK  0x0000000000000080UL
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD_WIDTH 1
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD_MASK  0x0000000000000040UL
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD_WIDTH 1
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD_MASK  0x0000000000000020UL
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD_WIDTH 1
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD_MASK  0x0000000000000010UL
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD_WIDTH 1
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD_MASK  0x0000000000000008UL
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD_WIDTH 1
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD_MASK  0x0000000000000004UL
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD_WIDTH 1
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD_MASK  0x0000000000000002UL
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD_WIDTH 1
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD;
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD_MASK  0x0000000000000001UL
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD_WIDTH 1
+#define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD;
+#define LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD_WIDTH 16
+#define LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD;
+#define LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD_WIDTH 16
+#define LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD;
+#define LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD_WIDTH 16
+#define LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD;
+#define LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD_WIDTH 16
+#define LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD;
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD_MASK  0x00000000ffffffc0UL
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD_WIDTH 26
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD;
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD_MASK  0x0000000000000030UL
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD_WIDTH 2
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD;
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD_MASK  0x000000000000000cUL
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD_WIDTH 2
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD;
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD_MASK  0x0000000000000002UL
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD_WIDTH 1
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD;
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD_MASK  0x0000000000000001UL
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD_WIDTH 1
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD;
+#define LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD_MASK  0x00000000fffe0000UL
+#define LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD_WIDTH 15
+#define LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD;
+#define LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD_MASK  0x000000000001f000UL
+#define LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD_WIDTH 5
+#define LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD;
+#define LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD_MASK  0x0000000000000e00UL
+#define LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD_WIDTH 3
+#define LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD;
+#define LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD_MASK  0x0000000000000100UL
+#define LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD_WIDTH 1
+#define LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD;
+#define LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD_MASK  0x0000000000000080UL
+#define LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD_WIDTH 1
+#define LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD;
+#define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD_MASK  0x0000000000000040UL
+#define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD_WIDTH 1
+#define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD;
+#define LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD_MASK  0x0000000000000020UL
+#define LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD_WIDTH 1
+#define LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD;
+#define LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD_MASK  0x000000000000001eUL
+#define LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD_WIDTH 4
+#define LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD;
+#define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD_MASK  0x0000000000000001UL
+#define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD_WIDTH 1
+#define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD;
+#define LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD_MASK  0x00000000ffffc000UL
+#define LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD_WIDTH 18
+#define LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD;
+#define LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD_MASK  0x0000000000002000UL
+#define LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD_WIDTH 1
+#define LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD;
+#define LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD_MASK  0x0000000000001e00UL
+#define LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD_WIDTH 4
+#define LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD;
+#define LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD_MASK  0x0000000000000100UL
+#define LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD_WIDTH 1
+#define LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD;
+#define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD_MASK  0x00000000000000f0UL
+#define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD_WIDTH 4
+#define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD;
+#define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD_MASK  0x000000000000000fUL
+#define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD_WIDTH 4
+#define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD;
+#define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_WIDTH 16
+#define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD;
+#define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_WIDTH 16
+#define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD;
+#define LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD_MASK  0x00000000fe000000UL
+#define LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD_WIDTH 7
+#define LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD_SHIFT 25
+
+extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD;
+#define LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD_MASK  0x0000000001800000UL
+#define LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD_WIDTH 2
+#define LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD;
+#define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD_MASK  0x0000000000400000UL
+#define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD_WIDTH 1
+#define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD_SHIFT 22
+
+extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD;
+#define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD_MASK  0x0000000000200000UL
+#define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD_WIDTH 1
+#define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD_SHIFT 21
+
+extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD;
+#define LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD_MASK  0x00000000001f0000UL
+#define LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD_WIDTH 5
+#define LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD;
+#define LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD_WIDTH 16
+#define LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_CNTRL_RESERVED0_FIELD;
+#define LPORT_RGMII_CNTRL_RESERVED0_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_RGMII_CNTRL_RESERVED0_FIELD_WIDTH 16
+#define LPORT_RGMII_CNTRL_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD;
+#define LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD_MASK  0x0000000000008000UL
+#define LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD_WIDTH 1
+#define LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD;
+#define LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD_MASK  0x0000000000004000UL
+#define LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD_WIDTH 1
+#define LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_RGMII_CNTRL_LPI_COUNT_FIELD;
+#define LPORT_RGMII_CNTRL_LPI_COUNT_FIELD_MASK  0x0000000000003e00UL
+#define LPORT_RGMII_CNTRL_LPI_COUNT_FIELD_WIDTH 5
+#define LPORT_RGMII_CNTRL_LPI_COUNT_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD;
+#define LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD_MASK  0x0000000000000100UL
+#define LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD;
+#define LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD_MASK  0x0000000000000080UL
+#define LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD;
+#define LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD_MASK  0x0000000000000040UL
+#define LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD;
+#define LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD_MASK  0x0000000000000020UL
+#define LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD_WIDTH 1
+#define LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_RGMII_CNTRL_PORT_MODE_FIELD;
+#define LPORT_RGMII_CNTRL_PORT_MODE_FIELD_MASK  0x000000000000001cUL
+#define LPORT_RGMII_CNTRL_PORT_MODE_FIELD_WIDTH 3
+#define LPORT_RGMII_CNTRL_PORT_MODE_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD;
+#define LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD_MASK  0x0000000000000002UL
+#define LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD_WIDTH 1
+#define LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD;
+#define LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD_MASK  0x0000000000000001UL
+#define LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_IB_STATUS_RESERVED0_FIELD;
+#define LPORT_RGMII_IB_STATUS_RESERVED0_FIELD_MASK  0x00000000ffffffe0UL
+#define LPORT_RGMII_IB_STATUS_RESERVED0_FIELD_WIDTH 27
+#define LPORT_RGMII_IB_STATUS_RESERVED0_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD;
+#define LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD_MASK  0x0000000000000010UL
+#define LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD_WIDTH 1
+#define LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD;
+#define LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD_MASK  0x0000000000000008UL
+#define LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD_WIDTH 1
+#define LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD;
+#define LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD_MASK  0x0000000000000004UL
+#define LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD_WIDTH 1
+#define LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD;
+#define LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD_MASK  0x0000000000000003UL
+#define LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD_WIDTH 2
+#define LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD;
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_MASK  0x00000000fffffe00UL
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_WIDTH 23
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD;
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD_MASK  0x0000000000000100UL
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD;
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_MASK  0x0000000000000080UL
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD;
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_MASK  0x0000000000000040UL
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD;
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_MASK  0x0000000000000020UL
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD;
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_MASK  0x0000000000000010UL
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD;
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_MASK  0x000000000000000cUL
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_WIDTH 2
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD;
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_MASK  0x0000000000000003UL
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_WIDTH 2
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD;
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_MASK  0x00000000f0000000UL
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_WIDTH 4
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD;
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_MASK  0x0000000008000000UL
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_SHIFT 27
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD;
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_MASK  0x0000000004000000UL
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_WIDTH 1
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD;
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_MASK  0x0000000003fc0000UL
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_WIDTH 8
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD;
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_MASK  0x000000000003fe00UL
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD;
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_MASK  0x00000000000001ffUL
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD;
+#define LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD_MASK  0x00000000fffc0000UL
+#define LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD_WIDTH 14
+#define LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD;
+#define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_MASK  0x000000000003fe00UL
+#define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD;
+#define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_MASK  0x00000000000001ffUL
+#define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD;
+#define LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD_MASK  0x00000000fff80000UL
+#define LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD_WIDTH 13
+#define LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD;
+#define LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD_MASK  0x0000000000040000UL
+#define LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD_WIDTH 1
+#define LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD;
+#define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_MASK  0x000000000003fe00UL
+#define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD;
+#define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_MASK  0x00000000000001ffUL
+#define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD;
+#define LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD_MASK  0x00000000fffc0000UL
+#define LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD_WIDTH 14
+#define LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD;
+#define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_MASK  0x000000000003fe00UL
+#define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD;
+#define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_MASK  0x00000000000001ffUL
+#define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD;
+#define LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD_MASK  0x00000000f0000000UL
+#define LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD_WIDTH 4
+#define LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD;
+#define LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD_MASK  0x000000000fc00000UL
+#define LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD_WIDTH 6
+#define LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD_SHIFT 22
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD;
+#define LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_MASK  0x00000000003ff800UL
+#define LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_WIDTH 11
+#define LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD;
+#define LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD_MASK  0x00000000000007f8UL
+#define LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD_WIDTH 8
+#define LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD;
+#define LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD_MASK  0x0000000000000004UL
+#define LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD_SHIFT 2
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD;
+#define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD_MASK  0x0000000000000002UL
+#define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD_WIDTH 1
+#define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD;
+#define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD_MASK  0x0000000000000001UL
+#define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD_WIDTH 1
+#define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD;
+#define LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD_MASK  0x00000000fffc0000UL
+#define LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD_WIDTH 14
+#define LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD;
+#define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD_MASK  0x000000000003fe00UL
+#define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD;
+#define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD_MASK  0x00000000000001ffUL
+#define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD;
+#define LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD_MASK  0x00000000fffc0000UL
+#define LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD_WIDTH 14
+#define LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD;
+#define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD_MASK  0x000000000003fe00UL
+#define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD;
+#define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD_MASK  0x00000000000001ffUL
+#define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD_WIDTH 9
+#define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD;
+#define LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD_WIDTH 16
+#define LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD;
+#define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD_WIDTH 8
+#define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD;
+#define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD_WIDTH 8
+#define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD_MASK  0x00000000f0000000UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD_WIDTH 4
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_MASK  0x0000000008000000UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_SHIFT 27
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_MASK  0x0000000007e00000UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_SHIFT 21
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_MASK  0x0000000000100000UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_MASK  0x00000000000fc000UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_MASK  0x0000000000002000UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_MASK  0x0000000000001f80UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_MASK  0x0000000000000040UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_MASK  0x000000000000003fUL
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD_MASK  0x00000000fffe0000UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD_WIDTH 15
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_MASK  0x0000000000010000UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_MASK  0x000000000000f000UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_WIDTH 4
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_MASK  0x0000000000000800UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_MASK  0x0000000000000780UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_WIDTH 4
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_MASK  0x0000000000000040UL
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD;
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_MASK  0x000000000000003fUL
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD_MASK  0x00000000f0000000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD_WIDTH 4
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_MASK  0x0000000008000000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_SHIFT 27
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_MASK  0x0000000007e00000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_SHIFT 21
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_MASK  0x0000000000100000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_MASK  0x00000000000fc000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_MASK  0x0000000000002000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_MASK  0x0000000000001f80UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_MASK  0x0000000000000040UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_MASK  0x000000000000003fUL
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD_MASK  0x00000000f0000000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD_WIDTH 4
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_MASK  0x0000000008000000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_SHIFT 27
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_MASK  0x0000000007e00000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_SHIFT 21
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_MASK  0x0000000000100000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_MASK  0x00000000000fc000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_MASK  0x0000000000002000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_MASK  0x0000000000001f80UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_MASK  0x0000000000000040UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_MASK  0x000000000000003fUL
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD_MASK  0x00000000fff80000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD_WIDTH 13
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD_SHIFT 19
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_MASK  0x0000000000040000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_SHIFT 18
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_MASK  0x000000000003c000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_WIDTH 4
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_MASK  0x0000000000002000UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_MASK  0x0000000000001f80UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_MASK  0x0000000000000040UL
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_WIDTH 1
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD;
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_MASK  0x000000000000003fUL
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_WIDTH 6
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD;
+#define XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_MASK  0x00000000ffffffffUL
+#define XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_WIDTH 32
+#define XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD;
+#define XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_MASK  0x00000000ffffffffUL
+#define XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_WIDTH 32
+#define XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_MASK  0x00000000ffffe000UL
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_WIDTH 19
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_MASK  0x0000000000001000UL
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_WIDTH 1
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_SHIFT 12
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_MASK  0x0000000000000800UL
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_WIDTH 1
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_SHIFT 11
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_MASK  0x0000000000000400UL
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_WIDTH 1
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_SHIFT 10
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_MASK  0x0000000000000300UL
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_WIDTH 2
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_SHIFT 8
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_MASK  0x00000000000000ffUL
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_WIDTH 8
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD;
+#define XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_MASK  0x00000000ffffffffUL
+#define XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_WIDTH 32
+#define XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD;
+#define XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_MASK  0x00000000ffffffffUL
+#define XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_WIDTH 32
+#define XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_MASK  0x00000000ffffe000UL
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_WIDTH 19
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_MASK  0x0000000000001000UL
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_WIDTH 1
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_SHIFT 12
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_MASK  0x0000000000000800UL
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_WIDTH 1
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_SHIFT 11
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_MASK  0x0000000000000400UL
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_WIDTH 1
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_SHIFT 10
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_MASK  0x0000000000000300UL
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_WIDTH 2
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_SHIFT 8
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD;
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_MASK  0x00000000000000ffUL
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_WIDTH 8
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD;
+#define XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_MASK  0x00000000ffffffffUL
+#define XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_WIDTH 32
+#define XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD;
+#define XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_MASK  0x00000000ffffffffUL
+#define XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_WIDTH 32
+#define XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_CONFIG_RESERVED0_FIELD;
+#define XLMAC_CONF_CONFIG_RESERVED0_FIELD_MASK  0x00000000fffffc00UL
+#define XLMAC_CONF_CONFIG_RESERVED0_FIELD_WIDTH 22
+#define XLMAC_CONF_CONFIG_RESERVED0_FIELD_SHIFT 10
+
+extern const ru_field_rec XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD;
+#define XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD_MASK  0x0000000000000200UL
+#define XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD_WIDTH 1
+#define XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD_SHIFT 9
+
+extern const ru_field_rec XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD;
+#define XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_MASK  0x0000000000000100UL
+#define XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_WIDTH 1
+#define XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_SHIFT 8
+
+extern const ru_field_rec XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD;
+#define XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_MASK  0x0000000000000080UL
+#define XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_WIDTH 1
+#define XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_SHIFT 7
+
+extern const ru_field_rec XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD;
+#define XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_MASK  0x0000000000000040UL
+#define XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_WIDTH 1
+#define XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_SHIFT 6
+
+extern const ru_field_rec XLMAC_CONF_CONFIG_MAC_MODE_FIELD;
+#define XLMAC_CONF_CONFIG_MAC_MODE_FIELD_MASK  0x0000000000000038UL
+#define XLMAC_CONF_CONFIG_MAC_MODE_FIELD_WIDTH 3
+#define XLMAC_CONF_CONFIG_MAC_MODE_FIELD_SHIFT 3
+
+extern const ru_field_rec XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD;
+#define XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD_MASK  0x0000000000000004UL
+#define XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD_WIDTH 1
+#define XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD_SHIFT 2
+
+extern const ru_field_rec XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD;
+#define XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD_MASK  0x0000000000000002UL
+#define XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD_WIDTH 1
+#define XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD_SHIFT 1
+
+extern const ru_field_rec XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD;
+#define XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_MASK  0x0000000000000001UL
+#define XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_WIDTH 1
+#define XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD;
+#define XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD_MASK  0x00000000fffffff0UL
+#define XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD_WIDTH 28
+#define XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD_SHIFT 4
+
+extern const ru_field_rec XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD;
+#define XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_MASK  0x000000000000000fUL
+#define XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_WIDTH 4
+#define XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD;
+#define XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD_MASK  0x00000000ffc00000UL
+#define XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD_WIDTH 10
+#define XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD_SHIFT 22
+
+extern const ru_field_rec XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD;
+#define XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK  0x00000000003fffffUL
+#define XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22
+#define XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD;
+#define XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD_MASK  0x00000000ffc00000UL
+#define XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD_WIDTH 10
+#define XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD_SHIFT 22
+
+extern const ru_field_rec XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD;
+#define XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK  0x00000000003fffffUL
+#define XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22
+#define XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD;
+#define XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD_MASK  0x00000000ffc00000UL
+#define XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD_WIDTH 10
+#define XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD_SHIFT 22
+
+extern const ru_field_rec XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD;
+#define XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK  0x00000000003fffffUL
+#define XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22
+#define XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD;
+#define XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD_MASK  0x00000000ffc00000UL
+#define XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD_WIDTH 10
+#define XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD_SHIFT 22
+
+extern const ru_field_rec XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD;
+#define XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK  0x00000000003fffffUL
+#define XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22
+#define XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD;
+#define MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_MASK  0x00000000ffffffffUL
+#define MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_WIDTH 32
+#define MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD;
+#define MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_MASK  0x00000000ffffffffUL
+#define MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_WIDTH 32
+#define MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_MASK  0x00000000ffffe000UL
+#define MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_WIDTH 19
+#define MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_MASK  0x0000000000001000UL
+#define MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_WIDTH 1
+#define MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_SHIFT 12
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_MASK  0x0000000000000800UL
+#define MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_WIDTH 1
+#define MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_SHIFT 11
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_MASK  0x0000000000000400UL
+#define MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_WIDTH 1
+#define MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_SHIFT 10
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_MASK  0x0000000000000300UL
+#define MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_WIDTH 2
+#define MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_SHIFT 8
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_MASK  0x00000000000000ffUL
+#define MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_WIDTH 8
+#define MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD;
+#define MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_MASK  0x00000000ffffffffUL
+#define MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_WIDTH 32
+#define MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD;
+#define MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_MASK  0x00000000ffffffffUL
+#define MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_WIDTH 32
+#define MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_MASK  0x00000000ffffe000UL
+#define MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_WIDTH 19
+#define MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_SHIFT 13
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_MASK  0x0000000000001000UL
+#define MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_WIDTH 1
+#define MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_SHIFT 12
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_MASK  0x0000000000000800UL
+#define MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_WIDTH 1
+#define MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_SHIFT 11
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_MASK  0x0000000000000400UL
+#define MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_WIDTH 1
+#define MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_SHIFT 10
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_MASK  0x0000000000000300UL
+#define MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_WIDTH 2
+#define MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_SHIFT 8
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD;
+#define MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_MASK  0x00000000000000ffUL
+#define MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_WIDTH 8
+#define MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD;
+#define MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_MASK  0x00000000ffffffffUL
+#define MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_WIDTH 32
+#define MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD;
+#define MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_MASK  0x00000000ffffffffUL
+#define MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_WIDTH 32
+#define MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_CNTRL_RESERVED0_FIELD;
+#define MIB_CONF_CNTRL_RESERVED0_FIELD_MASK  0x00000000ffff0000UL
+#define MIB_CONF_CNTRL_RESERVED0_FIELD_WIDTH 16
+#define MIB_CONF_CNTRL_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD;
+#define MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD_MASK  0x000000000000f000UL
+#define MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD_WIDTH 4
+#define MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD_SHIFT 12
+
+extern const ru_field_rec MIB_CONF_CNTRL_SATURATE_EN_FIELD;
+#define MIB_CONF_CNTRL_SATURATE_EN_FIELD_MASK  0x0000000000000f00UL
+#define MIB_CONF_CNTRL_SATURATE_EN_FIELD_WIDTH 4
+#define MIB_CONF_CNTRL_SATURATE_EN_FIELD_SHIFT 8
+
+extern const ru_field_rec MIB_CONF_CNTRL_COR_EN_FIELD;
+#define MIB_CONF_CNTRL_COR_EN_FIELD_MASK  0x00000000000000f0UL
+#define MIB_CONF_CNTRL_COR_EN_FIELD_WIDTH 4
+#define MIB_CONF_CNTRL_COR_EN_FIELD_SHIFT 4
+
+extern const ru_field_rec MIB_CONF_CNTRL_CNT_RST_FIELD;
+#define MIB_CONF_CNTRL_CNT_RST_FIELD_MASK  0x000000000000000fUL
+#define MIB_CONF_CNTRL_CNT_RST_FIELD_WIDTH 4
+#define MIB_CONF_CNTRL_CNT_RST_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD;
+#define MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_MASK  0x00000000ffffff00UL
+#define MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_WIDTH 24
+#define MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_SHIFT 8
+
+extern const ru_field_rec MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD;
+#define MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_MASK  0x00000000000000ffUL
+#define MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_WIDTH 8
+#define MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD;
+#define MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_MASK  0x00000000ffffc000UL
+#define MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18
+#define MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD;
+#define MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK  0x0000000000003fffUL
+#define MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14
+#define MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD;
+#define MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_MASK  0x00000000ffffc000UL
+#define MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18
+#define MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD;
+#define MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK  0x0000000000003fffUL
+#define MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14
+#define MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD;
+#define MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_MASK  0x00000000ffffc000UL
+#define MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18
+#define MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD;
+#define MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK  0x0000000000003fffUL
+#define MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14
+#define MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD;
+#define MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_MASK  0x00000000ffffc000UL
+#define MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18
+#define MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD;
+#define MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK  0x0000000000003fffUL
+#define MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14
+#define MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_ECC_CNTRL_RESERVED0_FIELD;
+#define MIB_CONF_ECC_CNTRL_RESERVED0_FIELD_MASK  0x00000000fffffffcUL
+#define MIB_CONF_ECC_CNTRL_RESERVED0_FIELD_WIDTH 30
+#define MIB_CONF_ECC_CNTRL_RESERVED0_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD;
+#define MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_WIDTH 1
+#define MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD;
+#define MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_WIDTH 1
+#define MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD;
+#define MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD_MASK  0x00000000fffffe00UL
+#define MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD_WIDTH 23
+#define MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD;
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_MASK  0x0000000000000100UL
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_SHIFT 8
+
+extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD;
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_MASK  0x0000000000000080UL
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_SHIFT 7
+
+extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD;
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_MASK  0x0000000000000040UL
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_SHIFT 6
+
+extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD;
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_MASK  0x0000000000000020UL
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_SHIFT 5
+
+extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD;
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_MASK  0x0000000000000010UL
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_SHIFT 4
+
+extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD;
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_MASK  0x0000000000000008UL
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_SHIFT 3
+
+extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD;
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_MASK  0x0000000000000004UL
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD;
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD;
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD;
+#define MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD_MASK  0x00000000fffffe00UL
+#define MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD_WIDTH 23
+#define MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD;
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_MASK  0x0000000000000100UL
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_SHIFT 8
+
+extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD;
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_MASK  0x0000000000000080UL
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_SHIFT 7
+
+extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD;
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_MASK  0x0000000000000040UL
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_SHIFT 6
+
+extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD;
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_MASK  0x0000000000000020UL
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_SHIFT 5
+
+extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD;
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_MASK  0x0000000000000010UL
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_SHIFT 4
+
+extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD;
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_MASK  0x0000000000000008UL
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_SHIFT 3
+
+extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD;
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_MASK  0x0000000000000004UL
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD;
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD;
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_WIDTH 1
+#define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD;
+#define MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_MASK  0x00000000ffffff80UL
+#define MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_WIDTH 25
+#define MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD;
+#define MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_MASK  0x0000000000000078UL
+#define MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4
+#define MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3
+
+extern const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK  0x0000000000000004UL
+#define MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD;
+#define MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_MASK  0x00000000ffffff80UL
+#define MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_WIDTH 25
+#define MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD;
+#define MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_MASK  0x0000000000000078UL
+#define MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4
+#define MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3
+
+extern const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK  0x0000000000000004UL
+#define MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD;
+#define MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_MASK  0x00000000ffffff80UL
+#define MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_WIDTH 25
+#define MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD;
+#define MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_MASK  0x0000000000000078UL
+#define MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4
+#define MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3
+
+extern const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK  0x0000000000000004UL
+#define MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD;
+#define MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_MASK  0x00000000ffffff80UL
+#define MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_WIDTH 25
+#define MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD;
+#define MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_MASK  0x0000000000000078UL
+#define MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4
+#define MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3
+
+extern const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK  0x0000000000000004UL
+#define MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD;
+#define MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_MASK  0x00000000ffffff80UL
+#define MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_WIDTH 25
+#define MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD;
+#define MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_MASK  0x0000000000000078UL
+#define MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4
+#define MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3
+
+extern const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK  0x0000000000000004UL
+#define MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD;
+#define MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD;
+#define MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_MASK  0x00000000ffffff80UL
+#define MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_WIDTH 25
+#define MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD;
+#define MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_MASK  0x0000000000000078UL
+#define MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4
+#define MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3
+
+extern const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK  0x0000000000000004UL
+#define MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD;
+#define MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_MASK  0x00000000ffffff80UL
+#define MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_WIDTH 25
+#define MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD;
+#define MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_MASK  0x0000000000000078UL
+#define MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4
+#define MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3
+
+extern const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK  0x0000000000000004UL
+#define MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD;
+#define MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_MASK  0x00000000ffffff80UL
+#define MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_WIDTH 25
+#define MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD;
+#define MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_MASK  0x0000000000000078UL
+#define MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4
+#define MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3
+
+extern const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK  0x0000000000000004UL
+#define MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD;
+#define MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_MASK  0x00000000ffffff80UL
+#define MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_WIDTH 25
+#define MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_SHIFT 7
+
+extern const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD;
+#define MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_MASK  0x0000000000000078UL
+#define MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4
+#define MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3
+
+extern const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK  0x0000000000000004UL
+#define MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2
+
+extern const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK  0x0000000000000002UL
+#define MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1
+
+extern const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD;
+#define MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_MASK  0x0000000000000001UL
+#define MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1
+#define MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MDIO_CMD_RESERVED0_FIELD;
+#define LPORT_MDIO_CMD_RESERVED0_FIELD_MASK  0x00000000c0000000UL
+#define LPORT_MDIO_CMD_RESERVED0_FIELD_WIDTH 2
+#define LPORT_MDIO_CMD_RESERVED0_FIELD_SHIFT 30
+
+extern const ru_field_rec LPORT_MDIO_CMD_START_BUSY_FIELD;
+#define LPORT_MDIO_CMD_START_BUSY_FIELD_MASK  0x0000000020000000UL
+#define LPORT_MDIO_CMD_START_BUSY_FIELD_WIDTH 1
+#define LPORT_MDIO_CMD_START_BUSY_FIELD_SHIFT 29
+
+extern const ru_field_rec LPORT_MDIO_CMD_FAIL_FIELD;
+#define LPORT_MDIO_CMD_FAIL_FIELD_MASK  0x0000000010000000UL
+#define LPORT_MDIO_CMD_FAIL_FIELD_WIDTH 1
+#define LPORT_MDIO_CMD_FAIL_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_MDIO_CMD_OP_CODE_FIELD;
+#define LPORT_MDIO_CMD_OP_CODE_FIELD_MASK  0x000000000c000000UL
+#define LPORT_MDIO_CMD_OP_CODE_FIELD_WIDTH 2
+#define LPORT_MDIO_CMD_OP_CODE_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD;
+#define LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD_MASK  0x0000000003e00000UL
+#define LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD_WIDTH 5
+#define LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD_SHIFT 21
+
+extern const ru_field_rec LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD;
+#define LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD_MASK  0x00000000001f0000UL
+#define LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD_WIDTH 5
+#define LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_MDIO_CMD_DATA_ADDR_FIELD;
+#define LPORT_MDIO_CMD_DATA_ADDR_FIELD_MASK  0x000000000000ffffUL
+#define LPORT_MDIO_CMD_DATA_ADDR_FIELD_WIDTH 16
+#define LPORT_MDIO_CMD_DATA_ADDR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MDIO_CFG_RESERVED0_FIELD;
+#define LPORT_MDIO_CFG_RESERVED0_FIELD_MASK  0x00000000ffffc000UL
+#define LPORT_MDIO_CFG_RESERVED0_FIELD_WIDTH 18
+#define LPORT_MDIO_CFG_RESERVED0_FIELD_SHIFT 14
+
+extern const ru_field_rec LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD;
+#define LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD_MASK  0x0000000000002000UL
+#define LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD_WIDTH 1
+#define LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD;
+#define LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD_MASK  0x0000000000001000UL
+#define LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD_WIDTH 1
+#define LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD;
+#define LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_MASK  0x0000000000000ff0UL
+#define LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_WIDTH 8
+#define LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_MDIO_CFG_RESERVED2_FIELD;
+#define LPORT_MDIO_CFG_RESERVED2_FIELD_MASK  0x000000000000000eUL
+#define LPORT_MDIO_CFG_RESERVED2_FIELD_WIDTH 3
+#define LPORT_MDIO_CFG_RESERVED2_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD;
+#define LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD_MASK  0x0000000000000001UL
+#define LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD_WIDTH 1
+#define LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD;
+#define LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD;
+#define LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_MASK  0x000000007f800000UL
+#define LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD;
+#define LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD;
+#define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD;
+#define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD;
+#define LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_CPU_SET_RESERVED0_FIELD;
+#define LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD;
+#define LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_MASK  0x000000007f800000UL
+#define LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD;
+#define LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD;
+#define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD;
+#define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD;
+#define LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD;
+#define LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD;
+#define LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_MASK  0x000000007f800000UL
+#define LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD;
+#define LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD;
+#define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD;
+#define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD;
+#define LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD;
+#define LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000060000000UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000018000000UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000006000000UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000001800000UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000060000000UL
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000018000000UL
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000006000000UL
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000001800000UL
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000060000000UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000018000000UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000006000000UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000001800000UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD;
+#define LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD;
+#define LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_MASK  0x000000007f800000UL
+#define LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD;
+#define LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD;
+#define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD;
+#define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD;
+#define LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_PCI_SET_RESERVED0_FIELD;
+#define LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD;
+#define LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_MASK  0x000000007f800000UL
+#define LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD;
+#define LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD;
+#define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD;
+#define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD;
+#define LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD;
+#define LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD;
+#define LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_MASK  0x000000007f800000UL
+#define LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD;
+#define LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD;
+#define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD;
+#define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD;
+#define LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD;
+#define LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000060000000UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000018000000UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000006000000UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000001800000UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000060000000UL
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000018000000UL
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000006000000UL
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000001800000UL
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_MASK  0x0000000080000000UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_SHIFT 31
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000060000000UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000018000000UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000006000000UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK  0x0000000001800000UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK  0x00000000007f8000UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK  0x0000000000007800UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK  0x0000000000000780UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4
+#define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_MASK  0x0000000000000040UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_MASK  0x0000000000000020UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000018UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_MASK  0x0000000000000006UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1
+
+extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_MASK  0x0000000000000001UL
+#define LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1
+#define LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD;
+#define LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_MASK  0x00000000f0000000UL
+#define LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD;
+#define LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_MASK  0x000000000c000000UL
+#define LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD;
+#define LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD;
+#define LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD;
+#define LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_CPU_SET_RESERVED0_FIELD;
+#define LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_MASK  0x00000000f0000000UL
+#define LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD;
+#define LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_MASK  0x000000000c000000UL
+#define LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD;
+#define LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD;
+#define LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD;
+#define LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD;
+#define LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_MASK  0x00000000f0000000UL
+#define LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD;
+#define LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_MASK  0x000000000c000000UL
+#define LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD;
+#define LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD;
+#define LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD;
+#define LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD;
+#define LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_MASK  0x00000000fc000000UL
+#define LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_WIDTH 6
+#define LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD;
+#define LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD;
+#define LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD;
+#define LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD;
+#define LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_MASK  0x00000000fc000000UL
+#define LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_WIDTH 6
+#define LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD;
+#define LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD;
+#define LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD;
+#define LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD;
+#define LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_MASK  0x00000000fc000000UL
+#define LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_WIDTH 6
+#define LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD;
+#define LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD;
+#define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD;
+#define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD;
+#define LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_MASK  0x00000000f0000000UL
+#define LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD;
+#define LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_MASK  0x000000000c000000UL
+#define LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD;
+#define LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD;
+#define LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD;
+#define LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_PCI_SET_RESERVED0_FIELD;
+#define LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_MASK  0x00000000f0000000UL
+#define LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD;
+#define LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_MASK  0x000000000c000000UL
+#define LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD;
+#define LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD;
+#define LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD;
+#define LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD;
+#define LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_MASK  0x00000000f0000000UL
+#define LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_SHIFT 28
+
+extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD;
+#define LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_MASK  0x000000000c000000UL
+#define LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD;
+#define LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2
+#define LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD;
+#define LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD;
+#define LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD;
+#define LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_MASK  0x00000000fc000000UL
+#define LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_WIDTH 6
+#define LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD;
+#define LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD;
+#define LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD;
+#define LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD;
+#define LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_MASK  0x00000000fc000000UL
+#define LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_WIDTH 6
+#define LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD;
+#define LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD;
+#define LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD;
+#define LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD;
+#define LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_MASK  0x00000000fc000000UL
+#define LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_WIDTH 6
+#define LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_SHIFT 26
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD;
+#define LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK  0x0000000003000000UL
+#define LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2
+#define LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD;
+#define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK  0x0000000000f00000UL
+#define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD;
+#define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH 4
+#define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD;
+#define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_MASK  0x000000000000ff00UL
+#define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD;
+#define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_WIDTH 8
+#define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MAB_CNTRL_RESERVED0_FIELD;
+#define LPORT_MAB_CNTRL_RESERVED0_FIELD_MASK  0x00000000fffe0000UL
+#define LPORT_MAB_CNTRL_RESERVED0_FIELD_WIDTH 15
+#define LPORT_MAB_CNTRL_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD;
+#define LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_MASK  0x0000000000010000UL
+#define LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_WIDTH 1
+#define LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_MAB_CNTRL_RESERVED1_FIELD;
+#define LPORT_MAB_CNTRL_RESERVED1_FIELD_MASK  0x000000000000e000UL
+#define LPORT_MAB_CNTRL_RESERVED1_FIELD_WIDTH 3
+#define LPORT_MAB_CNTRL_RESERVED1_FIELD_SHIFT 13
+
+extern const ru_field_rec LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD;
+#define LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_MASK  0x0000000000001000UL
+#define LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_WIDTH 1
+#define LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_MAB_CNTRL_GMII_TX_RST_FIELD;
+#define LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_MASK  0x0000000000000f00UL
+#define LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_WIDTH 4
+#define LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_MAB_CNTRL_RESERVED2_FIELD;
+#define LPORT_MAB_CNTRL_RESERVED2_FIELD_MASK  0x00000000000000e0UL
+#define LPORT_MAB_CNTRL_RESERVED2_FIELD_WIDTH 3
+#define LPORT_MAB_CNTRL_RESERVED2_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD;
+#define LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_MASK  0x0000000000000010UL
+#define LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_WIDTH 1
+#define LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_MAB_CNTRL_GMII_RX_RST_FIELD;
+#define LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_MASK  0x000000000000000fUL
+#define LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_WIDTH 4
+#define LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD;
+#define LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_MASK  0x00000000fffe0000UL
+#define LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_WIDTH 15
+#define LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_SHIFT 17
+
+extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD;
+#define LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_MASK  0x0000000000010000UL
+#define LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_WIDTH 1
+#define LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD;
+#define LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_MASK  0x000000000000f000UL
+#define LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_WIDTH 4
+#define LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD;
+#define LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_MASK  0x0000000000000f00UL
+#define LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_WIDTH 4
+#define LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD;
+#define LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_MASK  0x00000000000000f0UL
+#define LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_WIDTH 4
+#define LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD;
+#define LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_MASK  0x000000000000000fUL
+#define LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_WIDTH 4
+#define LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD;
+#define LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_MASK  0x00000000fff00000UL
+#define LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_WIDTH 12
+#define LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_SHIFT 20
+
+extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD;
+#define LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_MASK  0x00000000000f0000UL
+#define LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_WIDTH 4
+#define LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD;
+#define LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_MASK  0x000000000000f000UL
+#define LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_WIDTH 4
+#define LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_SHIFT 12
+
+extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD;
+#define LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_MASK  0x0000000000000f00UL
+#define LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_WIDTH 4
+#define LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD;
+#define LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_MASK  0x00000000000000f0UL
+#define LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_WIDTH 4
+#define LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD;
+#define LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_MASK  0x000000000000000fUL
+#define LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_WIDTH 4
+#define LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD;
+#define LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_MASK  0x00000000fffffe00UL
+#define LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_WIDTH 23
+#define LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD;
+#define LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_MASK  0x0000000000000100UL
+#define LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_WIDTH 1
+#define LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_SHIFT 8
+
+extern const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD;
+#define LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_MASK  0x00000000000000ffUL
+#define LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_WIDTH 8
+#define LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_SHIFT 0
+
+extern const ru_field_rec LPORT_MAB_STATUS_RESERVED0_FIELD;
+#define LPORT_MAB_STATUS_RESERVED0_FIELD_MASK  0x00000000ffff0000UL
+#define LPORT_MAB_STATUS_RESERVED0_FIELD_WIDTH 16
+#define LPORT_MAB_STATUS_RESERVED0_FIELD_SHIFT 16
+
+extern const ru_field_rec LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD;
+#define LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_MASK  0x0000000000008000UL
+#define LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_WIDTH 1
+#define LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_SHIFT 15
+
+extern const ru_field_rec LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD;
+#define LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_MASK  0x0000000000007800UL
+#define LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_WIDTH 4
+#define LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_SHIFT 11
+
+extern const ru_field_rec LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD;
+#define LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_MASK  0x0000000000000400UL
+#define LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_WIDTH 1
+#define LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_SHIFT 10
+
+extern const ru_field_rec LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD;
+#define LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_MASK  0x0000000000000200UL
+#define LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_WIDTH 1
+#define LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_SHIFT 9
+
+extern const ru_field_rec LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD;
+#define LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_MASK  0x00000000000001e0UL
+#define LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_WIDTH 4
+#define LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_SHIFT 5
+
+extern const ru_field_rec LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD;
+#define LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_MASK  0x0000000000000010UL
+#define LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_WIDTH 1
+#define LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_SHIFT 4
+
+extern const ru_field_rec LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD;
+#define LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_MASK  0x000000000000000fUL
+#define LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_WIDTH 4
+#define LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_SHIFT 0
+
+
+
+/******************************************************************************
+ * BCM6858_A0 Registers
+ ******************************************************************************/
+extern const ru_reg_rec LPORT_XLMAC_CTRL_REG;
+#define LPORT_XLMAC_CTRL_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec LPORT_XLMAC_MODE_REG;
+#define LPORT_XLMAC_MODE_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec LPORT_XLMAC_SPARE0_REG;
+#define LPORT_XLMAC_SPARE0_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec LPORT_XLMAC_SPARE1_REG;
+#define LPORT_XLMAC_SPARE1_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec LPORT_XLMAC_TX_CTRL_REG;
+#define LPORT_XLMAC_TX_CTRL_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec LPORT_XLMAC_TX_CTRL_OVERLAY_REG;
+#define LPORT_XLMAC_TX_CTRL_OVERLAY_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec LPORT_XLMAC_TX_MAC_SA_REG;
+#define LPORT_XLMAC_TX_MAC_SA_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_REG;
+#define LPORT_XLMAC_TX_MAC_SA_OVERLAY_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec LPORT_XLMAC_RX_CTRL_REG;
+#define LPORT_XLMAC_RX_CTRL_REG_OFFSET 0x00000030
+
+extern const ru_reg_rec LPORT_XLMAC_RX_MAC_SA_REG;
+#define LPORT_XLMAC_RX_MAC_SA_REG_OFFSET 0x00000038
+
+extern const ru_reg_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_REG;
+#define LPORT_XLMAC_RX_MAC_SA_OVERLAY_REG_OFFSET 0x00000038
+
+extern const ru_reg_rec LPORT_XLMAC_RX_MAX_SIZE_REG;
+#define LPORT_XLMAC_RX_MAX_SIZE_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec LPORT_XLMAC_RX_VLAN_TAG_REG;
+#define LPORT_XLMAC_RX_VLAN_TAG_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec LPORT_XLMAC_RX_LSS_CTRL_REG;
+#define LPORT_XLMAC_RX_LSS_CTRL_REG_OFFSET 0x00000050
+
+extern const ru_reg_rec LPORT_XLMAC_RX_LSS_STATUS_REG;
+#define LPORT_XLMAC_RX_LSS_STATUS_REG_OFFSET 0x00000058
+
+extern const ru_reg_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_REG;
+#define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_REG_OFFSET 0x00000060
+
+extern const ru_reg_rec LPORT_XLMAC_PAUSE_CTRL_REG;
+#define LPORT_XLMAC_PAUSE_CTRL_REG_OFFSET 0x00000068
+
+extern const ru_reg_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_REG;
+#define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_REG_OFFSET 0x00000068
+
+extern const ru_reg_rec LPORT_XLMAC_PFC_CTRL_REG;
+#define LPORT_XLMAC_PFC_CTRL_REG_OFFSET 0x00000070
+
+extern const ru_reg_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_REG;
+#define LPORT_XLMAC_PFC_CTRL_OVERLAY_REG_OFFSET 0x00000070
+
+extern const ru_reg_rec LPORT_XLMAC_PFC_TYPE_REG;
+#define LPORT_XLMAC_PFC_TYPE_REG_OFFSET 0x00000078
+
+extern const ru_reg_rec LPORT_XLMAC_PFC_OPCODE_REG;
+#define LPORT_XLMAC_PFC_OPCODE_REG_OFFSET 0x00000080
+
+extern const ru_reg_rec LPORT_XLMAC_PFC_DA_REG;
+#define LPORT_XLMAC_PFC_DA_REG_OFFSET 0x00000088
+
+extern const ru_reg_rec LPORT_XLMAC_PFC_DA_OVERLAY_REG;
+#define LPORT_XLMAC_PFC_DA_OVERLAY_REG_OFFSET 0x00000088
+
+extern const ru_reg_rec LPORT_XLMAC_LLFC_CTRL_REG;
+#define LPORT_XLMAC_LLFC_CTRL_REG_OFFSET 0x00000090
+
+extern const ru_reg_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_REG;
+#define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_REG_OFFSET 0x00000098
+
+extern const ru_reg_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_REG;
+#define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_REG_OFFSET 0x000000a0
+
+extern const ru_reg_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_REG;
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_REG_OFFSET 0x000000a8
+
+extern const ru_reg_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_REG;
+#define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_REG_OFFSET 0x000000b0
+
+extern const ru_reg_rec LPORT_XLMAC_FIFO_STATUS_REG;
+#define LPORT_XLMAC_FIFO_STATUS_REG_OFFSET 0x000000b8
+
+extern const ru_reg_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_REG;
+#define LPORT_XLMAC_CLEAR_FIFO_STATUS_REG_OFFSET 0x000000c0
+
+extern const ru_reg_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_REG;
+#define LPORT_XLMAC_LAG_FAILOVER_STATUS_REG_OFFSET 0x000000c8
+
+extern const ru_reg_rec LPORT_XLMAC_EEE_CTRL_REG;
+#define LPORT_XLMAC_EEE_CTRL_REG_OFFSET 0x000000d0
+
+extern const ru_reg_rec LPORT_XLMAC_EEE_TIMERS_REG;
+#define LPORT_XLMAC_EEE_TIMERS_REG_OFFSET 0x000000d8
+
+extern const ru_reg_rec LPORT_XLMAC_EEE_TIMERS_OVERLAY_REG;
+#define LPORT_XLMAC_EEE_TIMERS_OVERLAY_REG_OFFSET 0x000000d8
+
+extern const ru_reg_rec LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_REG;
+#define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_REG_OFFSET 0x000000e0
+
+extern const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_0_REG;
+#define LPORT_XLMAC_HIGIG_HDR_0_REG_OFFSET 0x000000e8
+
+extern const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_REG;
+#define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_REG_OFFSET 0x000000e8
+
+extern const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_1_REG;
+#define LPORT_XLMAC_HIGIG_HDR_1_REG_OFFSET 0x000000f0
+
+extern const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_REG;
+#define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_REG_OFFSET 0x000000f0
+
+extern const ru_reg_rec LPORT_XLMAC_GMII_EEE_CTRL_REG;
+#define LPORT_XLMAC_GMII_EEE_CTRL_REG_OFFSET 0x000000f8
+
+extern const ru_reg_rec LPORT_XLMAC_TIMESTAMP_ADJUST_REG;
+#define LPORT_XLMAC_TIMESTAMP_ADJUST_REG_OFFSET 0x00000100
+
+extern const ru_reg_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_REG;
+#define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_REG_OFFSET 0x00000108
+
+extern const ru_reg_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_REG;
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_REG_OFFSET 0x00000110
+
+extern const ru_reg_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_REG;
+#define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_REG_OFFSET 0x00000110
+
+extern const ru_reg_rec LPORT_XLMAC_E2E_CTRL_REG;
+#define LPORT_XLMAC_E2E_CTRL_REG_OFFSET 0x00000118
+
+extern const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_REG;
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_0_REG_OFFSET 0x00000120
+
+extern const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_REG;
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_REG_OFFSET 0x00000120
+
+extern const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_REG;
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_1_REG_OFFSET 0x00000128
+
+extern const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_REG;
+#define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_REG_OFFSET 0x00000128
+
+extern const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_REG;
+#define LPORT_XLMAC_E2ECC_DATA_HDR_0_REG_OFFSET 0x00000130
+
+extern const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_REG;
+#define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_REG_OFFSET 0x00000130
+
+extern const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_REG;
+#define LPORT_XLMAC_E2ECC_DATA_HDR_1_REG_OFFSET 0x00000138
+
+extern const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_REG;
+#define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_REG_OFFSET 0x00000138
+
+extern const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_REG;
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_0_REG_OFFSET 0x00000140
+
+extern const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_REG;
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_REG_OFFSET 0x00000140
+
+extern const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_REG;
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_1_REG_OFFSET 0x00000148
+
+extern const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_REG;
+#define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_REG_OFFSET 0x00000148
+
+extern const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_REG;
+#define LPORT_XLMAC_E2EFC_DATA_HDR_0_REG_OFFSET 0x00000150
+
+extern const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_REG;
+#define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_REG_OFFSET 0x00000150
+
+extern const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_REG;
+#define LPORT_XLMAC_E2EFC_DATA_HDR_1_REG_OFFSET 0x00000158
+
+extern const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_REG;
+#define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_REG_OFFSET 0x00000158
+
+extern const ru_reg_rec LPORT_XLMAC_TXFIFO_CELL_CNT_REG;
+#define LPORT_XLMAC_TXFIFO_CELL_CNT_REG_OFFSET 0x00000160
+
+extern const ru_reg_rec LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REG;
+#define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REG_OFFSET 0x00000168
+
+extern const ru_reg_rec LPORT_XLMAC_MEM_CTRL_REG;
+#define LPORT_XLMAC_MEM_CTRL_REG_OFFSET 0x00000170
+
+extern const ru_reg_rec LPORT_XLMAC_ECC_CTRL_REG;
+#define LPORT_XLMAC_ECC_CTRL_REG_OFFSET 0x00000178
+
+extern const ru_reg_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_REG;
+#define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_REG_OFFSET 0x00000180
+
+extern const ru_reg_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_REG;
+#define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_REG_OFFSET 0x00000188
+
+extern const ru_reg_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_REG;
+#define LPORT_XLMAC_RX_CDC_ECC_STATUS_REG_OFFSET 0x00000190
+
+extern const ru_reg_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_REG;
+#define LPORT_XLMAC_TX_CDC_ECC_STATUS_REG_OFFSET 0x00000198
+
+extern const ru_reg_rec LPORT_XLMAC_CLEAR_ECC_STATUS_REG;
+#define LPORT_XLMAC_CLEAR_ECC_STATUS_REG_OFFSET 0x000001a0
+
+extern const ru_reg_rec LPORT_XLMAC_INTR_STATUS_REG;
+#define LPORT_XLMAC_INTR_STATUS_REG_OFFSET 0x000001a8
+
+extern const ru_reg_rec LPORT_XLMAC_INTR_ENABLE_REG;
+#define LPORT_XLMAC_INTR_ENABLE_REG_OFFSET 0x000001b0
+
+extern const ru_reg_rec LPORT_XLMAC_VERSION_ID_REG;
+#define LPORT_XLMAC_VERSION_ID_REG_OFFSET 0x000001b8
+
+extern const ru_reg_rec LPORT_MIB_GRX64_REG;
+#define LPORT_MIB_GRX64_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec LPORT_MIB_GRX127_REG;
+#define LPORT_MIB_GRX127_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec LPORT_MIB_GRX255_REG;
+#define LPORT_MIB_GRX255_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec LPORT_MIB_GRX511_REG;
+#define LPORT_MIB_GRX511_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec LPORT_MIB_GRX1023_REG;
+#define LPORT_MIB_GRX1023_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec LPORT_MIB_GRX1518_REG;
+#define LPORT_MIB_GRX1518_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec LPORT_MIB_GRX1522_REG;
+#define LPORT_MIB_GRX1522_REG_OFFSET 0x00000030
+
+extern const ru_reg_rec LPORT_MIB_GRX2047_REG;
+#define LPORT_MIB_GRX2047_REG_OFFSET 0x00000038
+
+extern const ru_reg_rec LPORT_MIB_GRX4095_REG;
+#define LPORT_MIB_GRX4095_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec LPORT_MIB_GRX9216_REG;
+#define LPORT_MIB_GRX9216_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec LPORT_MIB_GRX16383_REG;
+#define LPORT_MIB_GRX16383_REG_OFFSET 0x00000050
+
+extern const ru_reg_rec LPORT_MIB_GRXPKT_REG;
+#define LPORT_MIB_GRXPKT_REG_OFFSET 0x00000058
+
+extern const ru_reg_rec LPORT_MIB_GRXUCA_REG;
+#define LPORT_MIB_GRXUCA_REG_OFFSET 0x00000060
+
+extern const ru_reg_rec LPORT_MIB_GRXMCA_REG;
+#define LPORT_MIB_GRXMCA_REG_OFFSET 0x00000068
+
+extern const ru_reg_rec LPORT_MIB_GRXBCA_REG;
+#define LPORT_MIB_GRXBCA_REG_OFFSET 0x00000070
+
+extern const ru_reg_rec LPORT_MIB_GRXFCS_REG;
+#define LPORT_MIB_GRXFCS_REG_OFFSET 0x00000078
+
+extern const ru_reg_rec LPORT_MIB_GRXCF_REG;
+#define LPORT_MIB_GRXCF_REG_OFFSET 0x00000080
+
+extern const ru_reg_rec LPORT_MIB_GRXPF_REG;
+#define LPORT_MIB_GRXPF_REG_OFFSET 0x00000088
+
+extern const ru_reg_rec LPORT_MIB_GRXPP_REG;
+#define LPORT_MIB_GRXPP_REG_OFFSET 0x00000090
+
+extern const ru_reg_rec LPORT_MIB_GRXUO_REG;
+#define LPORT_MIB_GRXUO_REG_OFFSET 0x00000098
+
+extern const ru_reg_rec LPORT_MIB_GRXUDA_REG;
+#define LPORT_MIB_GRXUDA_REG_OFFSET 0x000000a0
+
+extern const ru_reg_rec LPORT_MIB_GRXWSA_REG;
+#define LPORT_MIB_GRXWSA_REG_OFFSET 0x000000a8
+
+extern const ru_reg_rec LPORT_MIB_GRXALN_REG;
+#define LPORT_MIB_GRXALN_REG_OFFSET 0x000000b0
+
+extern const ru_reg_rec LPORT_MIB_GRXFLR_REG;
+#define LPORT_MIB_GRXFLR_REG_OFFSET 0x000000b8
+
+extern const ru_reg_rec LPORT_MIB_GRXFRERR_REG;
+#define LPORT_MIB_GRXFRERR_REG_OFFSET 0x000000c0
+
+extern const ru_reg_rec LPORT_MIB_GRXFCR_REG;
+#define LPORT_MIB_GRXFCR_REG_OFFSET 0x000000c8
+
+extern const ru_reg_rec LPORT_MIB_GRXOVR_REG;
+#define LPORT_MIB_GRXOVR_REG_OFFSET 0x000000d0
+
+extern const ru_reg_rec LPORT_MIB_GRXJBR_REG;
+#define LPORT_MIB_GRXJBR_REG_OFFSET 0x000000d8
+
+extern const ru_reg_rec LPORT_MIB_GRXMTUE_REG;
+#define LPORT_MIB_GRXMTUE_REG_OFFSET 0x000000e0
+
+extern const ru_reg_rec LPORT_MIB_GRXMCRC_REG;
+#define LPORT_MIB_GRXMCRC_REG_OFFSET 0x000000e8
+
+extern const ru_reg_rec LPORT_MIB_GRXPRM_REG;
+#define LPORT_MIB_GRXPRM_REG_OFFSET 0x000000f0
+
+extern const ru_reg_rec LPORT_MIB_GRXVLN_REG;
+#define LPORT_MIB_GRXVLN_REG_OFFSET 0x000000f8
+
+extern const ru_reg_rec LPORT_MIB_GRXDVLN_REG;
+#define LPORT_MIB_GRXDVLN_REG_OFFSET 0x00000100
+
+extern const ru_reg_rec LPORT_MIB_GRXTRFU_REG;
+#define LPORT_MIB_GRXTRFU_REG_OFFSET 0x00000108
+
+extern const ru_reg_rec LPORT_MIB_GRXPOK_REG;
+#define LPORT_MIB_GRXPOK_REG_OFFSET 0x00000110
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCOFF0_REG;
+#define LPORT_MIB_GRXPFCOFF0_REG_OFFSET 0x00000118
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCOFF1_REG;
+#define LPORT_MIB_GRXPFCOFF1_REG_OFFSET 0x00000120
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCOFF2_REG;
+#define LPORT_MIB_GRXPFCOFF2_REG_OFFSET 0x00000128
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCOFF3_REG;
+#define LPORT_MIB_GRXPFCOFF3_REG_OFFSET 0x00000130
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCOFF4_REG;
+#define LPORT_MIB_GRXPFCOFF4_REG_OFFSET 0x00000138
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCOFF5_REG;
+#define LPORT_MIB_GRXPFCOFF5_REG_OFFSET 0x00000140
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCOFF6_REG;
+#define LPORT_MIB_GRXPFCOFF6_REG_OFFSET 0x00000148
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCOFF7_REG;
+#define LPORT_MIB_GRXPFCOFF7_REG_OFFSET 0x00000150
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCP0_REG;
+#define LPORT_MIB_GRXPFCP0_REG_OFFSET 0x00000158
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCP1_REG;
+#define LPORT_MIB_GRXPFCP1_REG_OFFSET 0x00000160
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCP2_REG;
+#define LPORT_MIB_GRXPFCP2_REG_OFFSET 0x00000168
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCP3_REG;
+#define LPORT_MIB_GRXPFCP3_REG_OFFSET 0x00000170
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCP4_REG;
+#define LPORT_MIB_GRXPFCP4_REG_OFFSET 0x00000178
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCP5_REG;
+#define LPORT_MIB_GRXPFCP5_REG_OFFSET 0x00000180
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCP6_REG;
+#define LPORT_MIB_GRXPFCP6_REG_OFFSET 0x00000188
+
+extern const ru_reg_rec LPORT_MIB_GRXPFCP7_REG;
+#define LPORT_MIB_GRXPFCP7_REG_OFFSET 0x00000190
+
+extern const ru_reg_rec LPORT_MIB_GRXSCHCRC_REG;
+#define LPORT_MIB_GRXSCHCRC_REG_OFFSET 0x00000198
+
+extern const ru_reg_rec LPORT_MIB_GRXBYT_REG;
+#define LPORT_MIB_GRXBYT_REG_OFFSET 0x000001a0
+
+extern const ru_reg_rec LPORT_MIB_GRXRPKT_REG;
+#define LPORT_MIB_GRXRPKT_REG_OFFSET 0x000001a8
+
+extern const ru_reg_rec LPORT_MIB_GRXUND_REG;
+#define LPORT_MIB_GRXUND_REG_OFFSET 0x000001b0
+
+extern const ru_reg_rec LPORT_MIB_GRXFRG_REG;
+#define LPORT_MIB_GRXFRG_REG_OFFSET 0x000001b8
+
+extern const ru_reg_rec LPORT_MIB_GRXRBYT_REG;
+#define LPORT_MIB_GRXRBYT_REG_OFFSET 0x000001c0
+
+extern const ru_reg_rec LPORT_MIB_GTX64_REG;
+#define LPORT_MIB_GTX64_REG_OFFSET 0x000001c8
+
+extern const ru_reg_rec LPORT_MIB_GTX127_REG;
+#define LPORT_MIB_GTX127_REG_OFFSET 0x000001d0
+
+extern const ru_reg_rec LPORT_MIB_GTX255_REG;
+#define LPORT_MIB_GTX255_REG_OFFSET 0x000001d8
+
+extern const ru_reg_rec LPORT_MIB_GTX511_REG;
+#define LPORT_MIB_GTX511_REG_OFFSET 0x000001e0
+
+extern const ru_reg_rec LPORT_MIB_GTX1023_REG;
+#define LPORT_MIB_GTX1023_REG_OFFSET 0x000001e8
+
+extern const ru_reg_rec LPORT_MIB_GTX1518_REG;
+#define LPORT_MIB_GTX1518_REG_OFFSET 0x000001f0
+
+extern const ru_reg_rec LPORT_MIB_GTX1522_REG;
+#define LPORT_MIB_GTX1522_REG_OFFSET 0x000001f8
+
+extern const ru_reg_rec LPORT_MIB_GTX2047_REG;
+#define LPORT_MIB_GTX2047_REG_OFFSET 0x00000200
+
+extern const ru_reg_rec LPORT_MIB_GTX4095_REG;
+#define LPORT_MIB_GTX4095_REG_OFFSET 0x00000208
+
+extern const ru_reg_rec LPORT_MIB_GTX9216_REG;
+#define LPORT_MIB_GTX9216_REG_OFFSET 0x00000210
+
+extern const ru_reg_rec LPORT_MIB_GTX16383_REG;
+#define LPORT_MIB_GTX16383_REG_OFFSET 0x00000218
+
+extern const ru_reg_rec LPORT_MIB_GTXPOK_REG;
+#define LPORT_MIB_GTXPOK_REG_OFFSET 0x00000220
+
+extern const ru_reg_rec LPORT_MIB_GTXPKT_REG;
+#define LPORT_MIB_GTXPKT_REG_OFFSET 0x00000228
+
+extern const ru_reg_rec LPORT_MIB_GTXUCA_REG;
+#define LPORT_MIB_GTXUCA_REG_OFFSET 0x00000230
+
+extern const ru_reg_rec LPORT_MIB_GTXMCA_REG;
+#define LPORT_MIB_GTXMCA_REG_OFFSET 0x00000238
+
+extern const ru_reg_rec LPORT_MIB_GTXBCA_REG;
+#define LPORT_MIB_GTXBCA_REG_OFFSET 0x00000240
+
+extern const ru_reg_rec LPORT_MIB_GTXPF_REG;
+#define LPORT_MIB_GTXPF_REG_OFFSET 0x00000248
+
+extern const ru_reg_rec LPORT_MIB_GTXPFC_REG;
+#define LPORT_MIB_GTXPFC_REG_OFFSET 0x00000250
+
+extern const ru_reg_rec LPORT_MIB_GTXJBR_REG;
+#define LPORT_MIB_GTXJBR_REG_OFFSET 0x00000258
+
+extern const ru_reg_rec LPORT_MIB_GTXFCS_REG;
+#define LPORT_MIB_GTXFCS_REG_OFFSET 0x00000260
+
+extern const ru_reg_rec LPORT_MIB_GTXCF_REG;
+#define LPORT_MIB_GTXCF_REG_OFFSET 0x00000268
+
+extern const ru_reg_rec LPORT_MIB_GTXOVR_REG;
+#define LPORT_MIB_GTXOVR_REG_OFFSET 0x00000270
+
+extern const ru_reg_rec LPORT_MIB_GTXDFR_REG;
+#define LPORT_MIB_GTXDFR_REG_OFFSET 0x00000278
+
+extern const ru_reg_rec LPORT_MIB_GTXEDF_REG;
+#define LPORT_MIB_GTXEDF_REG_OFFSET 0x00000280
+
+extern const ru_reg_rec LPORT_MIB_GTXSCL_REG;
+#define LPORT_MIB_GTXSCL_REG_OFFSET 0x00000288
+
+extern const ru_reg_rec LPORT_MIB_GTXMCL_REG;
+#define LPORT_MIB_GTXMCL_REG_OFFSET 0x00000290
+
+extern const ru_reg_rec LPORT_MIB_GTXLCL_REG;
+#define LPORT_MIB_GTXLCL_REG_OFFSET 0x00000298
+
+extern const ru_reg_rec LPORT_MIB_GTXXCL_REG;
+#define LPORT_MIB_GTXXCL_REG_OFFSET 0x000002a0
+
+extern const ru_reg_rec LPORT_MIB_GTXFRG_REG;
+#define LPORT_MIB_GTXFRG_REG_OFFSET 0x000002a8
+
+extern const ru_reg_rec LPORT_MIB_GTXERR_REG;
+#define LPORT_MIB_GTXERR_REG_OFFSET 0x000002b0
+
+extern const ru_reg_rec LPORT_MIB_GTXVLN_REG;
+#define LPORT_MIB_GTXVLN_REG_OFFSET 0x000002b8
+
+extern const ru_reg_rec LPORT_MIB_GTXDVLN_REG;
+#define LPORT_MIB_GTXDVLN_REG_OFFSET 0x000002c0
+
+extern const ru_reg_rec LPORT_MIB_GTXRPKT_REG;
+#define LPORT_MIB_GTXRPKT_REG_OFFSET 0x000002c8
+
+extern const ru_reg_rec LPORT_MIB_GTXUFL_REG;
+#define LPORT_MIB_GTXUFL_REG_OFFSET 0x000002d0
+
+extern const ru_reg_rec LPORT_MIB_GTXPFCP0_REG;
+#define LPORT_MIB_GTXPFCP0_REG_OFFSET 0x000002d8
+
+extern const ru_reg_rec LPORT_MIB_GTXPFCP1_REG;
+#define LPORT_MIB_GTXPFCP1_REG_OFFSET 0x000002e0
+
+extern const ru_reg_rec LPORT_MIB_GTXPFCP2_REG;
+#define LPORT_MIB_GTXPFCP2_REG_OFFSET 0x000002e8
+
+extern const ru_reg_rec LPORT_MIB_GTXPFCP3_REG;
+#define LPORT_MIB_GTXPFCP3_REG_OFFSET 0x000002f0
+
+extern const ru_reg_rec LPORT_MIB_GTXPFCP4_REG;
+#define LPORT_MIB_GTXPFCP4_REG_OFFSET 0x000002f8
+
+extern const ru_reg_rec LPORT_MIB_GTXPFCP5_REG;
+#define LPORT_MIB_GTXPFCP5_REG_OFFSET 0x00000300
+
+extern const ru_reg_rec LPORT_MIB_GTXPFCP6_REG;
+#define LPORT_MIB_GTXPFCP6_REG_OFFSET 0x00000308
+
+extern const ru_reg_rec LPORT_MIB_GTXPFCP7_REG;
+#define LPORT_MIB_GTXPFCP7_REG_OFFSET 0x00000310
+
+extern const ru_reg_rec LPORT_MIB_GTXNCL_REG;
+#define LPORT_MIB_GTXNCL_REG_OFFSET 0x00000318
+
+extern const ru_reg_rec LPORT_MIB_GTXBYT_REG;
+#define LPORT_MIB_GTXBYT_REG_OFFSET 0x00000320
+
+extern const ru_reg_rec LPORT_MIB_GRXLPI_REG;
+#define LPORT_MIB_GRXLPI_REG_OFFSET 0x00000328
+
+extern const ru_reg_rec LPORT_MIB_GRXDLPI_REG;
+#define LPORT_MIB_GRXDLPI_REG_OFFSET 0x00000330
+
+extern const ru_reg_rec LPORT_MIB_GTXLPI_REG;
+#define LPORT_MIB_GTXLPI_REG_OFFSET 0x00000338
+
+extern const ru_reg_rec LPORT_MIB_GTXDLPI_REG;
+#define LPORT_MIB_GTXDLPI_REG_OFFSET 0x00000340
+
+extern const ru_reg_rec LPORT_MIB_GRXPTLLFC_REG;
+#define LPORT_MIB_GRXPTLLFC_REG_OFFSET 0x00000348
+
+extern const ru_reg_rec LPORT_MIB_GRXLTLLFC_REG;
+#define LPORT_MIB_GRXLTLLFC_REG_OFFSET 0x00000350
+
+extern const ru_reg_rec LPORT_MIB_GRXLLFCFCS_REG;
+#define LPORT_MIB_GRXLLFCFCS_REG_OFFSET 0x00000358
+
+extern const ru_reg_rec LPORT_MIB_GTXLTLLFC_REG;
+#define LPORT_MIB_GTXLTLLFC_REG_OFFSET 0x00000360
+
+extern const ru_reg_rec LPORT_SRDS_DUAL_SERDES_REVISION_REG;
+#define LPORT_SRDS_DUAL_SERDES_REVISION_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG;
+#define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_OFFSET 0x0000002c
+
+extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG;
+#define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_OFFSET 0x00000030
+
+extern const ru_reg_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_REG;
+#define LPORT_SRDS_DUAL_SERDES_0_CNTRL_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_REG;
+#define LPORT_SRDS_DUAL_SERDES_0_STATUS_REG_OFFSET 0x00000044
+
+extern const ru_reg_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_REG;
+#define LPORT_SRDS_DUAL_SERDES_1_CNTRL_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_REG;
+#define LPORT_SRDS_DUAL_SERDES_1_STATUS_REG_OFFSET 0x0000004c
+
+extern const ru_reg_rec LPORT_LED_CNTRL_REG;
+#define LPORT_LED_CNTRL_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_REG;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec LPORT_LED_LINK_AND_SPEED_ENCODING_REG;
+#define LPORT_LED_LINK_AND_SPEED_ENCODING_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec LPORT_LED_AGGREGATE_LED_CNTRL_REG;
+#define LPORT_LED_AGGREGATE_LED_CNTRL_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_REG;
+#define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec LPORT_CTRL_LPORT_CNTRL_REG;
+#define LPORT_CTRL_LPORT_CNTRL_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec LPORT_CTRL_LPORT_REVISION_REG;
+#define LPORT_CTRL_LPORT_REVISION_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec LPORT_CTRL_QEGPHY_REVISION_REG;
+#define LPORT_CTRL_QEGPHY_REVISION_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_REG;
+#define LPORT_CTRL_QEGPHY_TEST_CNTRL_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec LPORT_CTRL_QEGPHY_CNTRL_REG;
+#define LPORT_CTRL_QEGPHY_CNTRL_REG_OFFSET 0x00000044
+
+extern const ru_reg_rec LPORT_CTRL_QEGPHY_STATUS_REG;
+#define LPORT_CTRL_QEGPHY_STATUS_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec LPORT_CTRL_LED_BLINK_RATE_CNTRL_REG;
+#define LPORT_CTRL_LED_BLINK_RATE_CNTRL_REG_OFFSET 0x000000d4
+
+extern const ru_reg_rec LPORT_CTRL_LED_SERIAL_CNTRL_REG;
+#define LPORT_CTRL_LED_SERIAL_CNTRL_REG_OFFSET 0x000000d8
+
+extern const ru_reg_rec LPORT_RGMII_CNTRL_REG;
+#define LPORT_RGMII_CNTRL_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec LPORT_RGMII_IB_STATUS_REG;
+#define LPORT_RGMII_IB_STATUS_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_REG;
+#define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_REG;
+#define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_REG_OFFSET 0x0000004c
+
+extern const ru_reg_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_REG;
+#define LPORT_RGMII_ATE_RX_EXP_DATA_1_REG_OFFSET 0x00000050
+
+extern const ru_reg_rec LPORT_RGMII_ATE_RX_STATUS_0_REG;
+#define LPORT_RGMII_ATE_RX_STATUS_0_REG_OFFSET 0x00000054
+
+extern const ru_reg_rec LPORT_RGMII_ATE_RX_STATUS_1_REG;
+#define LPORT_RGMII_ATE_RX_STATUS_1_REG_OFFSET 0x00000058
+
+extern const ru_reg_rec LPORT_RGMII_ATE_TX_CNTRL_REG;
+#define LPORT_RGMII_ATE_TX_CNTRL_REG_OFFSET 0x0000005c
+
+extern const ru_reg_rec LPORT_RGMII_ATE_TX_DATA_0_REG;
+#define LPORT_RGMII_ATE_TX_DATA_0_REG_OFFSET 0x00000060
+
+extern const ru_reg_rec LPORT_RGMII_ATE_TX_DATA_1_REG;
+#define LPORT_RGMII_ATE_TX_DATA_1_REG_OFFSET 0x00000064
+
+extern const ru_reg_rec LPORT_RGMII_ATE_TX_DATA_2_REG;
+#define LPORT_RGMII_ATE_TX_DATA_2_REG_OFFSET 0x00000068
+
+extern const ru_reg_rec LPORT_RGMII_TX_DELAY_CNTRL_0_REG;
+#define LPORT_RGMII_TX_DELAY_CNTRL_0_REG_OFFSET 0x00000094
+
+extern const ru_reg_rec LPORT_RGMII_TX_DELAY_CNTRL_1_REG;
+#define LPORT_RGMII_TX_DELAY_CNTRL_1_REG_OFFSET 0x00000098
+
+extern const ru_reg_rec LPORT_RGMII_RX_DELAY_CNTRL_0_REG;
+#define LPORT_RGMII_RX_DELAY_CNTRL_0_REG_OFFSET 0x0000009c
+
+extern const ru_reg_rec LPORT_RGMII_RX_DELAY_CNTRL_1_REG;
+#define LPORT_RGMII_RX_DELAY_CNTRL_1_REG_OFFSET 0x000000a0
+
+extern const ru_reg_rec LPORT_RGMII_RX_DELAY_CNTRL_2_REG;
+#define LPORT_RGMII_RX_DELAY_CNTRL_2_REG_OFFSET 0x000000a4
+
+extern const ru_reg_rec XLMAC_CONF_DIR_ACC_DATA_WRITE_REG;
+#define XLMAC_CONF_DIR_ACC_DATA_WRITE_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec XLMAC_CONF_DIR_ACC_DATA_READ_REG;
+#define XLMAC_CONF_DIR_ACC_DATA_READ_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_ADDR_0_REG;
+#define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_0_REG;
+#define XLMAC_CONF_INDIR_ACC_DATA_LOW_0_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_REG;
+#define XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_ADDR_1_REG;
+#define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_1_REG;
+#define XLMAC_CONF_INDIR_ACC_DATA_LOW_1_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_REG;
+#define XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec XLMAC_CONF_CONFIG_REG;
+#define XLMAC_CONF_CONFIG_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec XLMAC_CONF_INTERRUPT_CHECK_REG;
+#define XLMAC_CONF_INTERRUPT_CHECK_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec XLMAC_CONF_PORT_0_RXERR_MASK_REG;
+#define XLMAC_CONF_PORT_0_RXERR_MASK_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec XLMAC_CONF_PORT_1_RXERR_MASK_REG;
+#define XLMAC_CONF_PORT_1_RXERR_MASK_REG_OFFSET 0x0000002c
+
+extern const ru_reg_rec XLMAC_CONF_PORT_2_RXERR_MASK_REG;
+#define XLMAC_CONF_PORT_2_RXERR_MASK_REG_OFFSET 0x00000030
+
+extern const ru_reg_rec XLMAC_CONF_PORT_3_RXERR_MASK_REG;
+#define XLMAC_CONF_PORT_3_RXERR_MASK_REG_OFFSET 0x00000034
+
+extern const ru_reg_rec MIB_CONF_DIR_ACC_DATA_WRITE_REG;
+#define MIB_CONF_DIR_ACC_DATA_WRITE_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec MIB_CONF_DIR_ACC_DATA_READ_REG;
+#define MIB_CONF_DIR_ACC_DATA_READ_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec MIB_CONF_INDIR_ACC_ADDR_0_REG;
+#define MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_LOW_0_REG;
+#define MIB_CONF_INDIR_ACC_DATA_LOW_0_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_HIGH_0_REG;
+#define MIB_CONF_INDIR_ACC_DATA_HIGH_0_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec MIB_CONF_INDIR_ACC_ADDR_1_REG;
+#define MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_LOW_1_REG;
+#define MIB_CONF_INDIR_ACC_DATA_LOW_1_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_HIGH_1_REG;
+#define MIB_CONF_INDIR_ACC_DATA_HIGH_1_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec MIB_CONF_CNTRL_REG;
+#define MIB_CONF_CNTRL_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec MIB_CONF_EEE_PULSE_DURATION_CNTRL_REG;
+#define MIB_CONF_EEE_PULSE_DURATION_CNTRL_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec MIB_CONF_GPORT0_MAX_PKT_SIZE_REG;
+#define MIB_CONF_GPORT0_MAX_PKT_SIZE_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec MIB_CONF_GPORT1_MAX_PKT_SIZE_REG;
+#define MIB_CONF_GPORT1_MAX_PKT_SIZE_REG_OFFSET 0x0000002c
+
+extern const ru_reg_rec MIB_CONF_GPORT2_MAX_PKT_SIZE_REG;
+#define MIB_CONF_GPORT2_MAX_PKT_SIZE_REG_OFFSET 0x00000030
+
+extern const ru_reg_rec MIB_CONF_GPORT3_MAX_PKT_SIZE_REG;
+#define MIB_CONF_GPORT3_MAX_PKT_SIZE_REG_OFFSET 0x00000034
+
+extern const ru_reg_rec MIB_CONF_ECC_CNTRL_REG;
+#define MIB_CONF_ECC_CNTRL_REG_OFFSET 0x00000038
+
+extern const ru_reg_rec MIB_CONF_FORCE_SB_ECC_ERR_REG;
+#define MIB_CONF_FORCE_SB_ECC_ERR_REG_OFFSET 0x0000003c
+
+extern const ru_reg_rec MIB_CONF_FORCE_DB_ECC_ERR_REG;
+#define MIB_CONF_FORCE_DB_ECC_ERR_REG_OFFSET 0x00000040
+
+extern const ru_reg_rec MIB_CONF_RX_MEM0_ECC_STATUS_REG;
+#define MIB_CONF_RX_MEM0_ECC_STATUS_REG_OFFSET 0x00000044
+
+extern const ru_reg_rec MIB_CONF_RX_MEM1_ECC_STATUS_REG;
+#define MIB_CONF_RX_MEM1_ECC_STATUS_REG_OFFSET 0x00000048
+
+extern const ru_reg_rec MIB_CONF_RX_MEM2_ECC_STATUS_REG;
+#define MIB_CONF_RX_MEM2_ECC_STATUS_REG_OFFSET 0x0000004c
+
+extern const ru_reg_rec MIB_CONF_RX_MEM3_ECC_STATUS_REG;
+#define MIB_CONF_RX_MEM3_ECC_STATUS_REG_OFFSET 0x00000050
+
+extern const ru_reg_rec MIB_CONF_RX_MEM4_ECC_STATUS_REG;
+#define MIB_CONF_RX_MEM4_ECC_STATUS_REG_OFFSET 0x00000054
+
+extern const ru_reg_rec MIB_CONF_TX_MEM0_ECC_STATUS_REG;
+#define MIB_CONF_TX_MEM0_ECC_STATUS_REG_OFFSET 0x00000058
+
+extern const ru_reg_rec MIB_CONF_TX_MEM1_ECC_STATUS_REG;
+#define MIB_CONF_TX_MEM1_ECC_STATUS_REG_OFFSET 0x0000005c
+
+extern const ru_reg_rec MIB_CONF_TX_MEM2_ECC_STATUS_REG;
+#define MIB_CONF_TX_MEM2_ECC_STATUS_REG_OFFSET 0x00000060
+
+extern const ru_reg_rec MIB_CONF_TX_MEM3_ECC_STATUS_REG;
+#define MIB_CONF_TX_MEM3_ECC_STATUS_REG_OFFSET 0x00000064
+
+extern const ru_reg_rec LPORT_MDIO_CMD_REG;
+#define LPORT_MDIO_CMD_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec LPORT_MDIO_CFG_REG;
+#define LPORT_MDIO_CFG_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec LPORT_INTR_0_CPU_STATUS_REG;
+#define LPORT_INTR_0_CPU_STATUS_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec LPORT_INTR_0_CPU_SET_REG;
+#define LPORT_INTR_0_CPU_SET_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec LPORT_INTR_0_CPU_CLEAR_REG;
+#define LPORT_INTR_0_CPU_CLEAR_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec LPORT_INTR_0_CPU_MASK_STATUS_REG;
+#define LPORT_INTR_0_CPU_MASK_STATUS_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec LPORT_INTR_0_CPU_MASK_SET_REG;
+#define LPORT_INTR_0_CPU_MASK_SET_REG_OFFSET 0x00000010
+
+extern const ru_reg_rec LPORT_INTR_0_CPU_MASK_CLEAR_REG;
+#define LPORT_INTR_0_CPU_MASK_CLEAR_REG_OFFSET 0x00000014
+
+extern const ru_reg_rec LPORT_INTR_0_PCI_STATUS_REG;
+#define LPORT_INTR_0_PCI_STATUS_REG_OFFSET 0x00000018
+
+extern const ru_reg_rec LPORT_INTR_0_PCI_SET_REG;
+#define LPORT_INTR_0_PCI_SET_REG_OFFSET 0x0000001c
+
+extern const ru_reg_rec LPORT_INTR_0_PCI_CLEAR_REG;
+#define LPORT_INTR_0_PCI_CLEAR_REG_OFFSET 0x00000020
+
+extern const ru_reg_rec LPORT_INTR_0_PCI_MASK_STATUS_REG;
+#define LPORT_INTR_0_PCI_MASK_STATUS_REG_OFFSET 0x00000024
+
+extern const ru_reg_rec LPORT_INTR_0_PCI_MASK_SET_REG;
+#define LPORT_INTR_0_PCI_MASK_SET_REG_OFFSET 0x00000028
+
+extern const ru_reg_rec LPORT_INTR_0_PCI_MASK_CLEAR_REG;
+#define LPORT_INTR_0_PCI_MASK_CLEAR_REG_OFFSET 0x0000002c
+
+extern const ru_reg_rec LPORT_INTR_1_CPU_STATUS_REG;
+#define LPORT_INTR_1_CPU_STATUS_REG_OFFSET 0x00000100
+
+extern const ru_reg_rec LPORT_INTR_1_CPU_SET_REG;
+#define LPORT_INTR_1_CPU_SET_REG_OFFSET 0x00000104
+
+extern const ru_reg_rec LPORT_INTR_1_CPU_CLEAR_REG;
+#define LPORT_INTR_1_CPU_CLEAR_REG_OFFSET 0x00000108
+
+extern const ru_reg_rec LPORT_INTR_1_CPU_MASK_STATUS_REG;
+#define LPORT_INTR_1_CPU_MASK_STATUS_REG_OFFSET 0x0000010c
+
+extern const ru_reg_rec LPORT_INTR_1_CPU_MASK_SET_REG;
+#define LPORT_INTR_1_CPU_MASK_SET_REG_OFFSET 0x00000110
+
+extern const ru_reg_rec LPORT_INTR_1_CPU_MASK_CLEAR_REG;
+#define LPORT_INTR_1_CPU_MASK_CLEAR_REG_OFFSET 0x00000114
+
+extern const ru_reg_rec LPORT_INTR_1_PCI_STATUS_REG;
+#define LPORT_INTR_1_PCI_STATUS_REG_OFFSET 0x00000118
+
+extern const ru_reg_rec LPORT_INTR_1_PCI_SET_REG;
+#define LPORT_INTR_1_PCI_SET_REG_OFFSET 0x0000011c
+
+extern const ru_reg_rec LPORT_INTR_1_PCI_CLEAR_REG;
+#define LPORT_INTR_1_PCI_CLEAR_REG_OFFSET 0x00000120
+
+extern const ru_reg_rec LPORT_INTR_1_PCI_MASK_STATUS_REG;
+#define LPORT_INTR_1_PCI_MASK_STATUS_REG_OFFSET 0x00000124
+
+extern const ru_reg_rec LPORT_INTR_1_PCI_MASK_SET_REG;
+#define LPORT_INTR_1_PCI_MASK_SET_REG_OFFSET 0x00000128
+
+extern const ru_reg_rec LPORT_INTR_1_PCI_MASK_CLEAR_REG;
+#define LPORT_INTR_1_PCI_MASK_CLEAR_REG_OFFSET 0x0000012c
+
+extern const ru_reg_rec LPORT_MAB_CNTRL_REG;
+#define LPORT_MAB_CNTRL_REG_OFFSET 0x00000000
+
+extern const ru_reg_rec LPORT_MAB_TX_WRR_CTRL_REG;
+#define LPORT_MAB_TX_WRR_CTRL_REG_OFFSET 0x00000004
+
+extern const ru_reg_rec LPORT_MAB_TX_THRESHOLD_REG;
+#define LPORT_MAB_TX_THRESHOLD_REG_OFFSET 0x00000008
+
+extern const ru_reg_rec LPORT_MAB_LINK_DOWN_TX_DATA_REG;
+#define LPORT_MAB_LINK_DOWN_TX_DATA_REG_OFFSET 0x0000000c
+
+extern const ru_reg_rec LPORT_MAB_STATUS_REG;
+#define LPORT_MAB_STATUS_REG_OFFSET 0x00000010
+
+
+
+/******************************************************************************
+ * BCM6858_A0 Blocks
+ ******************************************************************************/
+extern const ru_block_rec LPORT_XLMAC_BLOCK;
+extern const ru_block_rec LPORT_MIB_BLOCK;
+extern const ru_block_rec LPORT_SRDS_BLOCK;
+extern const ru_block_rec LPORT_LED_BLOCK;
+extern const ru_block_rec LPORT_CTRL_BLOCK;
+extern const ru_block_rec LPORT_RGMII_BLOCK;
+extern const ru_block_rec XLMAC_CONF_BLOCK;
+extern const ru_block_rec MIB_CONF_BLOCK;
+extern const ru_block_rec LPORT_MDIO_BLOCK;
+extern const ru_block_rec LPORT_INTR_BLOCK;
+extern const ru_block_rec LPORT_MAB_BLOCK;
+extern const ru_block_rec *RU_LPORT_BLOCKS[];
+
+
+#define RU_BLK_COUNT 11
+#define RU_REG_COUNT 300
+#define RU_FLD_COUNT 1041
+
+
+#endif /* End of file BCM6858_A0.h */
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_drivers_lport_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_drivers_lport_ag.c
new file mode 100644
index 0000000000..2f6fdac50d
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_drivers_lport_ag.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+
+
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_drivers_lport_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_drivers_lport_ag.h
new file mode 100644
index 0000000000..f1c9dc9652
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_drivers_lport_ag.h
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_LPORT_COMMON_AG_H_
+#define _BCM6858_LPORT_COMMON_AG_H_
+
+#include "lport_print.h"
+#include "bcmtypes.h"
+#include "ru.h"
+#include "BCM6858_A0_LPORT_AG.h"
+
+#define _1BITS_MAX_VAL_ (1U<<1)
+#define _2BITS_MAX_VAL_ (1U<<2)
+#define _3BITS_MAX_VAL_ (1U<<3)
+#define _4BITS_MAX_VAL_ (1U<<4)
+#define _5BITS_MAX_VAL_ (1U<<5)
+#define _6BITS_MAX_VAL_ (1U<<6)
+#define _7BITS_MAX_VAL_ (1U<<7)
+#define _9BITS_MAX_VAL_ (1U<<9)
+#define _10BITS_MAX_VAL_ (1U<<10)
+#define _11BITS_MAX_VAL_ (1U<<11)
+#define _12BITS_MAX_VAL_ (1U<<12)
+#define _13BITS_MAX_VAL_ (1U<<13)
+#define _14BITS_MAX_VAL_ (1U<<14)
+#define _15BITS_MAX_VAL_ (1U<<15)
+#define _17BITS_MAX_VAL_ (1U<<17)
+#define _18BITS_MAX_VAL_ (1U<<18)
+#define _19BITS_MAX_VAL_ (1U<<19)
+#define _20BITS_MAX_VAL_ (1U<<20)
+#define _21BITS_MAX_VAL_ (1U<<21)
+#define _22BITS_MAX_VAL_ (1U<<22)
+#define _23BITS_MAX_VAL_ (1U<<23)
+#define _24BITS_MAX_VAL_ (1U<<24)
+#define _25BITS_MAX_VAL_ (1U<<25)
+#define _26BITS_MAX_VAL_ (1U<<26)
+#define _27BITS_MAX_VAL_ (1U<<27)
+#define _28BITS_MAX_VAL_ (1U<<28)
+#define _29BITS_MAX_VAL_ (1U<<29)
+#define _30BITS_MAX_VAL_ (1U<<30)
+#define _31BITS_MAX_VAL_ (1U<<31)
+#define _33BITS_MAX_VAL_ (1lU<<33)
+#define _34BITS_MAX_VAL_ (1lU<<34)
+#define _35BITS_MAX_VAL_ (1lU<<35)
+#define _36BITS_MAX_VAL_ (1lU<<36)
+#define _37BITS_MAX_VAL_ (1lU<<37)
+#define _38BITS_MAX_VAL_ (1lU<<38)
+#define _39BITS_MAX_VAL_ (1lU<<39)
+#define _40BITS_MAX_VAL_ (1lU<<40)
+#define _41BITS_MAX_VAL_ (1lU<<41)
+#define _42BITS_MAX_VAL_ (1lU<<42)
+#define _43BITS_MAX_VAL_ (1lU<<43)
+#define _44BITS_MAX_VAL_ (1lU<<44)
+#define _45BITS_MAX_VAL_ (1lU<<45)
+#define _46BITS_MAX_VAL_ (1lU<<46)
+#define _47BITS_MAX_VAL_ (1lU<<47)
+#define _48BITS_MAX_VAL_ (1lU<<48)
+#define _49BITS_MAX_VAL_ (1lU<<49)
+#define _50BITS_MAX_VAL_ (1lU<<50)
+#define _51BITS_MAX_VAL_ (1lU<<51)
+#define _52BITS_MAX_VAL_ (1lU<<52)
+#define _53BITS_MAX_VAL_ (1lU<<53)
+#define _54BITS_MAX_VAL_ (1lU<<54)
+#define _55BITS_MAX_VAL_ (1lU<<55)
+#define _56BITS_MAX_VAL_ (1lU<<56)
+#define _57BITS_MAX_VAL_ (1lU<<57)
+#define _58BITS_MAX_VAL_ (1lU<<58)
+#define _59BITS_MAX_VAL_ (1lU<<59)
+#define _60BITS_MAX_VAL_ (1lU<<60)
+#define _61BITS_MAX_VAL_ (1lU<<61)
+#define _62BITS_MAX_VAL_ (1lU<<62)
+#define _63BITS_MAX_VAL_ (1lU<<63)
+
+
+static inline void ag_ru_block_addr_print(int block_idx)
+{
+	int addr_idx;
+	for (addr_idx = 0; addr_idx < RU_LPORT_BLOCKS[block_idx]->addr_count; addr_idx++)
+	{
+		pr_info("block %s[%d] address = 0x%16lx\n", RU_LPORT_BLOCKS[block_idx]->name, addr_idx,
+			RU_LPORT_BLOCKS[block_idx]->addr[addr_idx]);
+	}
+}
+
+static inline void ag_ru_blocks_data_print(void)
+{
+	int block_idx;
+	for (block_idx = 0; block_idx < RU_BLK_COUNT; block_idx++)
+	{
+		ag_ru_block_addr_print(block_idx);
+	}
+}
+#endif
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_ctrl_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_lport_ctrl_ag.c
new file mode 100644
index 0000000000..9e0fe6addd
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_ctrl_ag.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_lport_ctrl_ag.h"
+int ag_drv_lport_ctrl_control_set(const lport_ctrl_control *control)
+{
+    uint32_t reg_lport_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!control)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((control->timeout_rst_disable >= _1BITS_MAX_VAL_) ||
+       (control->p4_mode >= _1BITS_MAX_VAL_) ||
+       (control->p0_mode >= _1BITS_MAX_VAL_) ||
+       (control->gport_sel_7 >= _1BITS_MAX_VAL_) ||
+       (control->gport_sel_6 >= _1BITS_MAX_VAL_) ||
+       (control->gport_sel_5 >= _1BITS_MAX_VAL_) ||
+       (control->gport_sel_4 >= _1BITS_MAX_VAL_) ||
+       (control->gport_sel_3 >= _1BITS_MAX_VAL_) ||
+       (control->gport_sel_2 >= _1BITS_MAX_VAL_) ||
+       (control->gport_sel_1 >= _1BITS_MAX_VAL_) ||
+       (control->gport_sel_0 >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_lport_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LPORT_CNTRL, TIMEOUT_RST_DISABLE, reg_lport_cntrl, control->timeout_rst_disable);
+    reg_lport_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LPORT_CNTRL, P4_MODE, reg_lport_cntrl, control->p4_mode);
+    reg_lport_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LPORT_CNTRL, P0_MODE, reg_lport_cntrl, control->p0_mode);
+    reg_lport_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_7, reg_lport_cntrl, control->gport_sel_7);
+    reg_lport_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_6, reg_lport_cntrl, control->gport_sel_6);
+    reg_lport_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_5, reg_lport_cntrl, control->gport_sel_5);
+    reg_lport_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_4, reg_lport_cntrl, control->gport_sel_4);
+    reg_lport_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_3, reg_lport_cntrl, control->gport_sel_3);
+    reg_lport_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_2, reg_lport_cntrl, control->gport_sel_2);
+    reg_lport_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_1, reg_lport_cntrl, control->gport_sel_1);
+    reg_lport_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_0, reg_lport_cntrl, control->gport_sel_0);
+
+    RU_REG_WRITE(0, LPORT_CTRL, LPORT_CNTRL, reg_lport_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_control_get(lport_ctrl_control *control)
+{
+    uint32_t reg_lport_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!control)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_CTRL, LPORT_CNTRL, reg_lport_cntrl);
+
+    control->timeout_rst_disable = RU_FIELD_GET(0, LPORT_CTRL, LPORT_CNTRL, TIMEOUT_RST_DISABLE, reg_lport_cntrl);
+    control->p4_mode = RU_FIELD_GET(0, LPORT_CTRL, LPORT_CNTRL, P4_MODE, reg_lport_cntrl);
+    control->p0_mode = RU_FIELD_GET(0, LPORT_CTRL, LPORT_CNTRL, P0_MODE, reg_lport_cntrl);
+    control->gport_sel_7 = RU_FIELD_GET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_7, reg_lport_cntrl);
+    control->gport_sel_6 = RU_FIELD_GET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_6, reg_lport_cntrl);
+    control->gport_sel_5 = RU_FIELD_GET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_5, reg_lport_cntrl);
+    control->gport_sel_4 = RU_FIELD_GET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_4, reg_lport_cntrl);
+    control->gport_sel_3 = RU_FIELD_GET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_3, reg_lport_cntrl);
+    control->gport_sel_2 = RU_FIELD_GET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_2, reg_lport_cntrl);
+    control->gport_sel_1 = RU_FIELD_GET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_1, reg_lport_cntrl);
+    control->gport_sel_0 = RU_FIELD_GET(0, LPORT_CTRL, LPORT_CNTRL, GPORT_SEL_0, reg_lport_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_lport_revision_get(uint16_t *lport_rev)
+{
+    uint32_t reg_lport_revision=0;
+
+#ifdef VALIDATE_PARMS
+    if(!lport_rev)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_CTRL, LPORT_REVISION, reg_lport_revision);
+
+    *lport_rev = RU_FIELD_GET(0, LPORT_CTRL, LPORT_REVISION, LPORT_REV, reg_lport_revision);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_qegphy_revision_get(uint16_t *quad_phy_rev)
+{
+    uint32_t reg_qegphy_revision=0;
+
+#ifdef VALIDATE_PARMS
+    if(!quad_phy_rev)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_CTRL, QEGPHY_REVISION, reg_qegphy_revision);
+
+    *quad_phy_rev = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_REVISION, QUAD_PHY_REV, reg_qegphy_revision);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_qegphy_test_cntrl_set(uint8_t pll_refclk_sel, uint8_t pll_sel_div5, uint8_t pll_clk125_250_sel, uint8_t phy_test_en)
+{
+    uint32_t reg_qegphy_test_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if((pll_refclk_sel >= _2BITS_MAX_VAL_) ||
+       (pll_sel_div5 >= _2BITS_MAX_VAL_) ||
+       (pll_clk125_250_sel >= _1BITS_MAX_VAL_) ||
+       (phy_test_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_qegphy_test_cntrl = RU_FIELD_SET(0, LPORT_CTRL, QEGPHY_TEST_CNTRL, PLL_REFCLK_SEL, reg_qegphy_test_cntrl, pll_refclk_sel);
+    reg_qegphy_test_cntrl = RU_FIELD_SET(0, LPORT_CTRL, QEGPHY_TEST_CNTRL, PLL_SEL_DIV5, reg_qegphy_test_cntrl, pll_sel_div5);
+    reg_qegphy_test_cntrl = RU_FIELD_SET(0, LPORT_CTRL, QEGPHY_TEST_CNTRL, PLL_CLK125_250_SEL, reg_qegphy_test_cntrl, pll_clk125_250_sel);
+    reg_qegphy_test_cntrl = RU_FIELD_SET(0, LPORT_CTRL, QEGPHY_TEST_CNTRL, PHY_TEST_EN, reg_qegphy_test_cntrl, phy_test_en);
+
+    RU_REG_WRITE(0, LPORT_CTRL, QEGPHY_TEST_CNTRL, reg_qegphy_test_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_qegphy_test_cntrl_get(uint8_t *pll_refclk_sel, uint8_t *pll_sel_div5, uint8_t *pll_clk125_250_sel, uint8_t *phy_test_en)
+{
+    uint32_t reg_qegphy_test_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!pll_refclk_sel || !pll_sel_div5 || !pll_clk125_250_sel || !phy_test_en)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_CTRL, QEGPHY_TEST_CNTRL, reg_qegphy_test_cntrl);
+
+    *pll_refclk_sel = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_TEST_CNTRL, PLL_REFCLK_SEL, reg_qegphy_test_cntrl);
+    *pll_sel_div5 = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_TEST_CNTRL, PLL_SEL_DIV5, reg_qegphy_test_cntrl);
+    *pll_clk125_250_sel = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_TEST_CNTRL, PLL_CLK125_250_SEL, reg_qegphy_test_cntrl);
+    *phy_test_en = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_TEST_CNTRL, PHY_TEST_EN, reg_qegphy_test_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_qegphy_cntrl_set(const lport_ctrl_qegphy_cntrl *qegphy_cntrl)
+{
+    uint32_t reg_qegphy_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!qegphy_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((qegphy_cntrl->phy_phyad >= _5BITS_MAX_VAL_) ||
+       (qegphy_cntrl->phy_reset >= _1BITS_MAX_VAL_) ||
+       (qegphy_cntrl->ck25_en >= _1BITS_MAX_VAL_) ||
+       (qegphy_cntrl->iddq_global_pwr >= _1BITS_MAX_VAL_) ||
+       (qegphy_cntrl->force_dll_en >= _1BITS_MAX_VAL_) ||
+       (qegphy_cntrl->ext_pwr_down >= _4BITS_MAX_VAL_) ||
+       (qegphy_cntrl->iddq_bias >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_qegphy_cntrl = RU_FIELD_SET(0, LPORT_CTRL, QEGPHY_CNTRL, PHY_PHYAD, reg_qegphy_cntrl, qegphy_cntrl->phy_phyad);
+    reg_qegphy_cntrl = RU_FIELD_SET(0, LPORT_CTRL, QEGPHY_CNTRL, PHY_RESET, reg_qegphy_cntrl, qegphy_cntrl->phy_reset);
+    reg_qegphy_cntrl = RU_FIELD_SET(0, LPORT_CTRL, QEGPHY_CNTRL, CK25_EN, reg_qegphy_cntrl, qegphy_cntrl->ck25_en);
+    reg_qegphy_cntrl = RU_FIELD_SET(0, LPORT_CTRL, QEGPHY_CNTRL, IDDQ_GLOBAL_PWR, reg_qegphy_cntrl, qegphy_cntrl->iddq_global_pwr);
+    reg_qegphy_cntrl = RU_FIELD_SET(0, LPORT_CTRL, QEGPHY_CNTRL, FORCE_DLL_EN, reg_qegphy_cntrl, qegphy_cntrl->force_dll_en);
+    reg_qegphy_cntrl = RU_FIELD_SET(0, LPORT_CTRL, QEGPHY_CNTRL, EXT_PWR_DOWN, reg_qegphy_cntrl, qegphy_cntrl->ext_pwr_down);
+    reg_qegphy_cntrl = RU_FIELD_SET(0, LPORT_CTRL, QEGPHY_CNTRL, IDDQ_BIAS, reg_qegphy_cntrl, qegphy_cntrl->iddq_bias);
+
+    RU_REG_WRITE(0, LPORT_CTRL, QEGPHY_CNTRL, reg_qegphy_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_qegphy_cntrl_get(lport_ctrl_qegphy_cntrl *qegphy_cntrl)
+{
+    uint32_t reg_qegphy_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!qegphy_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_CTRL, QEGPHY_CNTRL, reg_qegphy_cntrl);
+
+    qegphy_cntrl->phy_phyad = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_CNTRL, PHY_PHYAD, reg_qegphy_cntrl);
+    qegphy_cntrl->phy_reset = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_CNTRL, PHY_RESET, reg_qegphy_cntrl);
+    qegphy_cntrl->ck25_en = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_CNTRL, CK25_EN, reg_qegphy_cntrl);
+    qegphy_cntrl->iddq_global_pwr = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_CNTRL, IDDQ_GLOBAL_PWR, reg_qegphy_cntrl);
+    qegphy_cntrl->force_dll_en = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_CNTRL, FORCE_DLL_EN, reg_qegphy_cntrl);
+    qegphy_cntrl->ext_pwr_down = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_CNTRL, EXT_PWR_DOWN, reg_qegphy_cntrl);
+    qegphy_cntrl->iddq_bias = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_CNTRL, IDDQ_BIAS, reg_qegphy_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_qegphy_status_get(lport_ctrl_qegphy_status *qegphy_status)
+{
+    uint32_t reg_qegphy_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!qegphy_status)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_CTRL, QEGPHY_STATUS, reg_qegphy_status);
+
+    qegphy_status->gphy_test_status = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_STATUS, GPHY_TEST_STATUS, reg_qegphy_status);
+    qegphy_status->recovered_clk_lock = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_STATUS, RECOVERED_CLK_LOCK, reg_qegphy_status);
+    qegphy_status->pll_lock = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_STATUS, PLL_LOCK, reg_qegphy_status);
+    qegphy_status->energy_det_apd = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_STATUS, ENERGY_DET_APD, reg_qegphy_status);
+    qegphy_status->energy_det_masked = RU_FIELD_GET(0, LPORT_CTRL, QEGPHY_STATUS, ENERGY_DET_MASKED, reg_qegphy_status);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_led_blink_rate_cntrl_set(uint16_t led_on_time, uint16_t led_off_time)
+{
+    uint32_t reg_led_blink_rate_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+#endif
+
+    reg_led_blink_rate_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LED_BLINK_RATE_CNTRL, LED_ON_TIME, reg_led_blink_rate_cntrl, led_on_time);
+    reg_led_blink_rate_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LED_BLINK_RATE_CNTRL, LED_OFF_TIME, reg_led_blink_rate_cntrl, led_off_time);
+
+    RU_REG_WRITE(0, LPORT_CTRL, LED_BLINK_RATE_CNTRL, reg_led_blink_rate_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_led_blink_rate_cntrl_get(uint16_t *led_on_time, uint16_t *led_off_time)
+{
+    uint32_t reg_led_blink_rate_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!led_on_time || !led_off_time)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_CTRL, LED_BLINK_RATE_CNTRL, reg_led_blink_rate_cntrl);
+
+    *led_on_time = RU_FIELD_GET(0, LPORT_CTRL, LED_BLINK_RATE_CNTRL, LED_ON_TIME, reg_led_blink_rate_cntrl);
+    *led_off_time = RU_FIELD_GET(0, LPORT_CTRL, LED_BLINK_RATE_CNTRL, LED_OFF_TIME, reg_led_blink_rate_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_led_serial_cntrl_set(const lport_ctrl_led_serial_cntrl *led_serial_cntrl)
+{
+    uint32_t reg_led_serial_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!led_serial_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((led_serial_cntrl->smode >= _2BITS_MAX_VAL_) ||
+       (led_serial_cntrl->sled_clk_frequency >= _1BITS_MAX_VAL_) ||
+       (led_serial_cntrl->sled_clk_pol >= _1BITS_MAX_VAL_) ||
+       (led_serial_cntrl->refresh_period >= _5BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_led_serial_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LED_SERIAL_CNTRL, SMODE, reg_led_serial_cntrl, led_serial_cntrl->smode);
+    reg_led_serial_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LED_SERIAL_CNTRL, SLED_CLK_FREQUENCY, reg_led_serial_cntrl, led_serial_cntrl->sled_clk_frequency);
+    reg_led_serial_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LED_SERIAL_CNTRL, SLED_CLK_POL, reg_led_serial_cntrl, led_serial_cntrl->sled_clk_pol);
+    reg_led_serial_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LED_SERIAL_CNTRL, REFRESH_PERIOD, reg_led_serial_cntrl, led_serial_cntrl->refresh_period);
+    reg_led_serial_cntrl = RU_FIELD_SET(0, LPORT_CTRL, LED_SERIAL_CNTRL, PORT_EN, reg_led_serial_cntrl, led_serial_cntrl->port_en);
+
+    RU_REG_WRITE(0, LPORT_CTRL, LED_SERIAL_CNTRL, reg_led_serial_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_ctrl_led_serial_cntrl_get(lport_ctrl_led_serial_cntrl *led_serial_cntrl)
+{
+    uint32_t reg_led_serial_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!led_serial_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_CTRL, LED_SERIAL_CNTRL, reg_led_serial_cntrl);
+
+    led_serial_cntrl->smode = RU_FIELD_GET(0, LPORT_CTRL, LED_SERIAL_CNTRL, SMODE, reg_led_serial_cntrl);
+    led_serial_cntrl->sled_clk_frequency = RU_FIELD_GET(0, LPORT_CTRL, LED_SERIAL_CNTRL, SLED_CLK_FREQUENCY, reg_led_serial_cntrl);
+    led_serial_cntrl->sled_clk_pol = RU_FIELD_GET(0, LPORT_CTRL, LED_SERIAL_CNTRL, SLED_CLK_POL, reg_led_serial_cntrl);
+    led_serial_cntrl->refresh_period = RU_FIELD_GET(0, LPORT_CTRL, LED_SERIAL_CNTRL, REFRESH_PERIOD, reg_led_serial_cntrl);
+    led_serial_cntrl->port_en = RU_FIELD_GET(0, LPORT_CTRL, LED_SERIAL_CNTRL, PORT_EN, reg_led_serial_cntrl);
+
+    return 0;
+}
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_ctrl_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_lport_ctrl_ag.h
new file mode 100644
index 0000000000..1b9c00763c
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_ctrl_ag.h
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_LPORT_CTRL_AG_H_
+#define _BCM6858_LPORT_CTRL_AG_H_
+
+#include "access_macros.h"
+#include "bcmtypes.h"
+typedef struct
+{
+    uint8_t timeout_rst_disable;
+    uint8_t p4_mode;
+    uint8_t p0_mode;
+    uint8_t gport_sel_7;
+    uint8_t gport_sel_6;
+    uint8_t gport_sel_5;
+    uint8_t gport_sel_4;
+    uint8_t gport_sel_3;
+    uint8_t gport_sel_2;
+    uint8_t gport_sel_1;
+    uint8_t gport_sel_0;
+} lport_ctrl_control;
+
+typedef struct
+{
+    uint8_t phy_phyad;
+    uint8_t phy_reset;
+    uint8_t ck25_en;
+    uint8_t iddq_global_pwr;
+    uint8_t force_dll_en;
+    uint8_t ext_pwr_down;
+    uint8_t iddq_bias;
+} lport_ctrl_qegphy_cntrl;
+
+typedef struct
+{
+    uint8_t gphy_test_status;
+    uint8_t recovered_clk_lock;
+    uint8_t pll_lock;
+    uint8_t energy_det_apd;
+    uint8_t energy_det_masked;
+} lport_ctrl_qegphy_status;
+
+typedef struct
+{
+    uint8_t smode;
+    uint8_t sled_clk_frequency;
+    uint8_t sled_clk_pol;
+    uint8_t refresh_period;
+    uint16_t port_en;
+} lport_ctrl_led_serial_cntrl;
+
+int ag_drv_lport_ctrl_control_set(const lport_ctrl_control *control);
+int ag_drv_lport_ctrl_control_get(lport_ctrl_control *control);
+int ag_drv_lport_ctrl_lport_revision_get(uint16_t *lport_rev);
+int ag_drv_lport_ctrl_qegphy_revision_get(uint16_t *quad_phy_rev);
+int ag_drv_lport_ctrl_qegphy_test_cntrl_set(uint8_t pll_refclk_sel, uint8_t pll_sel_div5, uint8_t pll_clk125_250_sel, uint8_t phy_test_en);
+int ag_drv_lport_ctrl_qegphy_test_cntrl_get(uint8_t *pll_refclk_sel, uint8_t *pll_sel_div5, uint8_t *pll_clk125_250_sel, uint8_t *phy_test_en);
+int ag_drv_lport_ctrl_qegphy_cntrl_set(const lport_ctrl_qegphy_cntrl *qegphy_cntrl);
+int ag_drv_lport_ctrl_qegphy_cntrl_get(lport_ctrl_qegphy_cntrl *qegphy_cntrl);
+int ag_drv_lport_ctrl_qegphy_status_get(lport_ctrl_qegphy_status *qegphy_status);
+int ag_drv_lport_ctrl_led_blink_rate_cntrl_set(uint16_t led_on_time, uint16_t led_off_time);
+int ag_drv_lport_ctrl_led_blink_rate_cntrl_get(uint16_t *led_on_time, uint16_t *led_off_time);
+int ag_drv_lport_ctrl_led_serial_cntrl_set(const lport_ctrl_led_serial_cntrl *led_serial_cntrl);
+int ag_drv_lport_ctrl_led_serial_cntrl_get(lport_ctrl_led_serial_cntrl *led_serial_cntrl);
+
+#ifdef USE_BDMF_SHELL
+bdmfmon_handle_t ag_drv_lport_ctrl_cli_init(bdmfmon_handle_t driver_dir);
+#endif
+
+
+#endif
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_intr_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_lport_intr_ag.c
new file mode 100644
index 0000000000..946aa3c19f
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_intr_ag.c
@@ -0,0 +1,757 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_lport_intr_ag.h"
+int ag_drv_lport_intr_status_0_set(const lport_intr_status_0 *status_0)
+{
+    uint32_t reg_0_cpu_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!status_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((status_0->qgphy_energy_off_intr >= _4BITS_MAX_VAL_) ||
+       (status_0->qgphy_energy_on_intr >= _4BITS_MAX_VAL_) ||
+       (status_0->mdio_err_intr >= _1BITS_MAX_VAL_) ||
+       (status_0->mdio_done_intr >= _1BITS_MAX_VAL_) ||
+       (status_0->mib_reg_err_intr >= _2BITS_MAX_VAL_) ||
+       (status_0->mac_reg_err_intr >= _2BITS_MAX_VAL_) ||
+       (status_0->ubus_err_intr >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_0_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_STATUS, XLMAC_INTR, reg_0_cpu_status, status_0->xlmac_intr);
+    reg_0_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_STATUS, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR, reg_0_cpu_status, status_0->tx_timesync_fifo_entry_valid_intr);
+    reg_0_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_STATUS, QGPHY_ENERGY_OFF_INTR, reg_0_cpu_status, status_0->qgphy_energy_off_intr);
+    reg_0_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_STATUS, QGPHY_ENERGY_ON_INTR, reg_0_cpu_status, status_0->qgphy_energy_on_intr);
+    reg_0_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_STATUS, MDIO_ERR_INTR, reg_0_cpu_status, status_0->mdio_err_intr);
+    reg_0_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_STATUS, MDIO_DONE_INTR, reg_0_cpu_status, status_0->mdio_done_intr);
+    reg_0_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_STATUS, MIB_REG_ERR_INTR, reg_0_cpu_status, status_0->mib_reg_err_intr);
+    reg_0_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_STATUS, MAC_REG_ERR_INTR, reg_0_cpu_status, status_0->mac_reg_err_intr);
+    reg_0_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_STATUS, UBUS_ERR_INTR, reg_0_cpu_status, status_0->ubus_err_intr);
+
+    RU_REG_WRITE(0, LPORT_INTR, 0_CPU_STATUS, reg_0_cpu_status);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_status_0_get(lport_intr_status_0 *status_0)
+{
+    uint32_t reg_0_cpu_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!status_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 0_CPU_STATUS, reg_0_cpu_status);
+
+    status_0->xlmac_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_STATUS, XLMAC_INTR, reg_0_cpu_status);
+    status_0->tx_timesync_fifo_entry_valid_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_STATUS, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR, reg_0_cpu_status);
+    status_0->qgphy_energy_off_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_STATUS, QGPHY_ENERGY_OFF_INTR, reg_0_cpu_status);
+    status_0->qgphy_energy_on_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_STATUS, QGPHY_ENERGY_ON_INTR, reg_0_cpu_status);
+    status_0->mdio_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_STATUS, MDIO_ERR_INTR, reg_0_cpu_status);
+    status_0->mdio_done_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_STATUS, MDIO_DONE_INTR, reg_0_cpu_status);
+    status_0->mib_reg_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_STATUS, MIB_REG_ERR_INTR, reg_0_cpu_status);
+    status_0->mac_reg_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_STATUS, MAC_REG_ERR_INTR, reg_0_cpu_status);
+    status_0->ubus_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_STATUS, UBUS_ERR_INTR, reg_0_cpu_status);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_set_0_set(const lport_intr_set_0 *set_0)
+{
+    uint32_t reg_0_cpu_set=0;
+
+#ifdef VALIDATE_PARMS
+    if(!set_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((set_0->qgphy_energy_off_intr >= _4BITS_MAX_VAL_) ||
+       (set_0->qgphy_energy_on_intr >= _4BITS_MAX_VAL_) ||
+       (set_0->mdio_err_intr >= _1BITS_MAX_VAL_) ||
+       (set_0->mdio_done_intr >= _1BITS_MAX_VAL_) ||
+       (set_0->mib_reg_err_intr >= _2BITS_MAX_VAL_) ||
+       (set_0->mac_reg_err_intr >= _2BITS_MAX_VAL_) ||
+       (set_0->ubus_err_intr >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_0_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_SET, XLMAC_INTR, reg_0_cpu_set, set_0->xlmac_intr);
+    reg_0_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_SET, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR, reg_0_cpu_set, set_0->tx_timesync_fifo_entry_valid_intr);
+    reg_0_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_SET, QGPHY_ENERGY_OFF_INTR, reg_0_cpu_set, set_0->qgphy_energy_off_intr);
+    reg_0_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_SET, QGPHY_ENERGY_ON_INTR, reg_0_cpu_set, set_0->qgphy_energy_on_intr);
+    reg_0_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_SET, MDIO_ERR_INTR, reg_0_cpu_set, set_0->mdio_err_intr);
+    reg_0_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_SET, MDIO_DONE_INTR, reg_0_cpu_set, set_0->mdio_done_intr);
+    reg_0_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_SET, MIB_REG_ERR_INTR, reg_0_cpu_set, set_0->mib_reg_err_intr);
+    reg_0_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_SET, MAC_REG_ERR_INTR, reg_0_cpu_set, set_0->mac_reg_err_intr);
+    reg_0_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_SET, UBUS_ERR_INTR, reg_0_cpu_set, set_0->ubus_err_intr);
+
+    RU_REG_WRITE(0, LPORT_INTR, 0_CPU_SET, reg_0_cpu_set);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_set_0_get(lport_intr_set_0 *set_0)
+{
+    uint32_t reg_0_cpu_set=0;
+
+#ifdef VALIDATE_PARMS
+    if(!set_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 0_CPU_SET, reg_0_cpu_set);
+
+    set_0->xlmac_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_SET, XLMAC_INTR, reg_0_cpu_set);
+    set_0->tx_timesync_fifo_entry_valid_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_SET, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR, reg_0_cpu_set);
+    set_0->qgphy_energy_off_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_SET, QGPHY_ENERGY_OFF_INTR, reg_0_cpu_set);
+    set_0->qgphy_energy_on_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_SET, QGPHY_ENERGY_ON_INTR, reg_0_cpu_set);
+    set_0->mdio_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_SET, MDIO_ERR_INTR, reg_0_cpu_set);
+    set_0->mdio_done_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_SET, MDIO_DONE_INTR, reg_0_cpu_set);
+    set_0->mib_reg_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_SET, MIB_REG_ERR_INTR, reg_0_cpu_set);
+    set_0->mac_reg_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_SET, MAC_REG_ERR_INTR, reg_0_cpu_set);
+    set_0->ubus_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_SET, UBUS_ERR_INTR, reg_0_cpu_set);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_clear_0_set(const lport_intr_clear_0 *clear_0)
+{
+    uint32_t reg_0_cpu_clear=0;
+
+#ifdef VALIDATE_PARMS
+    if(!clear_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((clear_0->qgphy_energy_off_intr >= _4BITS_MAX_VAL_) ||
+       (clear_0->qgphy_energy_on_intr >= _4BITS_MAX_VAL_) ||
+       (clear_0->mdio_err_intr >= _1BITS_MAX_VAL_) ||
+       (clear_0->mdio_done_intr >= _1BITS_MAX_VAL_) ||
+       (clear_0->mib_reg_err_intr >= _2BITS_MAX_VAL_) ||
+       (clear_0->mac_reg_err_intr >= _2BITS_MAX_VAL_) ||
+       (clear_0->ubus_err_intr >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_0_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_CLEAR, XLMAC_INTR, reg_0_cpu_clear, clear_0->xlmac_intr);
+    reg_0_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_CLEAR, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR, reg_0_cpu_clear, clear_0->tx_timesync_fifo_entry_valid_intr);
+    reg_0_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_CLEAR, QGPHY_ENERGY_OFF_INTR, reg_0_cpu_clear, clear_0->qgphy_energy_off_intr);
+    reg_0_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_CLEAR, QGPHY_ENERGY_ON_INTR, reg_0_cpu_clear, clear_0->qgphy_energy_on_intr);
+    reg_0_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_CLEAR, MDIO_ERR_INTR, reg_0_cpu_clear, clear_0->mdio_err_intr);
+    reg_0_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_CLEAR, MDIO_DONE_INTR, reg_0_cpu_clear, clear_0->mdio_done_intr);
+    reg_0_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_CLEAR, MIB_REG_ERR_INTR, reg_0_cpu_clear, clear_0->mib_reg_err_intr);
+    reg_0_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_CLEAR, MAC_REG_ERR_INTR, reg_0_cpu_clear, clear_0->mac_reg_err_intr);
+    reg_0_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_CLEAR, UBUS_ERR_INTR, reg_0_cpu_clear, clear_0->ubus_err_intr);
+
+    RU_REG_WRITE(0, LPORT_INTR, 0_CPU_CLEAR, reg_0_cpu_clear);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_clear_0_get(lport_intr_clear_0 *clear_0)
+{
+    uint32_t reg_0_cpu_clear=0;
+
+#ifdef VALIDATE_PARMS
+    if(!clear_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 0_CPU_CLEAR, reg_0_cpu_clear);
+
+    clear_0->xlmac_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_CLEAR, XLMAC_INTR, reg_0_cpu_clear);
+    clear_0->tx_timesync_fifo_entry_valid_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_CLEAR, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR, reg_0_cpu_clear);
+    clear_0->qgphy_energy_off_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_CLEAR, QGPHY_ENERGY_OFF_INTR, reg_0_cpu_clear);
+    clear_0->qgphy_energy_on_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_CLEAR, QGPHY_ENERGY_ON_INTR, reg_0_cpu_clear);
+    clear_0->mdio_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_CLEAR, MDIO_ERR_INTR, reg_0_cpu_clear);
+    clear_0->mdio_done_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_CLEAR, MDIO_DONE_INTR, reg_0_cpu_clear);
+    clear_0->mib_reg_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_CLEAR, MIB_REG_ERR_INTR, reg_0_cpu_clear);
+    clear_0->mac_reg_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_CLEAR, MAC_REG_ERR_INTR, reg_0_cpu_clear);
+    clear_0->ubus_err_intr = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_CLEAR, UBUS_ERR_INTR, reg_0_cpu_clear);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_status_0_set(const lport_intr_mask_status_0 *mask_status_0)
+{
+    uint32_t reg_0_cpu_mask_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_status_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((mask_status_0->mac_rx_cdc_single_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_status_0->mac_rx_cdc_double_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_status_0->mac_tx_cdc_single_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_status_0->mac_tx_cdc_double_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_status_0->qgphy_energy_off_intr_mask >= _4BITS_MAX_VAL_) ||
+       (mask_status_0->qgphy_energy_on_intr_mask >= _4BITS_MAX_VAL_) ||
+       (mask_status_0->mdio_err_intr_mask >= _1BITS_MAX_VAL_) ||
+       (mask_status_0->mdio_done_intr_mask >= _1BITS_MAX_VAL_) ||
+       (mask_status_0->mib_reg_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_status_0->mac_reg_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_status_0->ubus_err_intr_mask >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->mac_rx_cdc_single_bit_err_intr_mask);
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->mac_rx_cdc_double_bit_err_intr_mask);
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->mac_tx_cdc_single_bit_err_intr_mask);
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->mac_tx_cdc_double_bit_err_intr_mask);
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->tx_timesync_fifo_entry_valid_intr_mask);
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, QGPHY_ENERGY_OFF_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->qgphy_energy_off_intr_mask);
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, QGPHY_ENERGY_ON_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->qgphy_energy_on_intr_mask);
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MDIO_ERR_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->mdio_err_intr_mask);
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MDIO_DONE_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->mdio_done_intr_mask);
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MIB_REG_ERR_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->mib_reg_err_intr_mask);
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MAC_REG_ERR_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->mac_reg_err_intr_mask);
+    reg_0_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_STATUS, UBUS_ERR_INTR_MASK, reg_0_cpu_mask_status, mask_status_0->ubus_err_intr_mask);
+
+    RU_REG_WRITE(0, LPORT_INTR, 0_CPU_MASK_STATUS, reg_0_cpu_mask_status);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_status_0_get(lport_intr_mask_status_0 *mask_status_0)
+{
+    uint32_t reg_0_cpu_mask_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_status_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 0_CPU_MASK_STATUS, reg_0_cpu_mask_status);
+
+    mask_status_0->mac_rx_cdc_single_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_status);
+    mask_status_0->mac_rx_cdc_double_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_status);
+    mask_status_0->mac_tx_cdc_single_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_status);
+    mask_status_0->mac_tx_cdc_double_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_status);
+    mask_status_0->tx_timesync_fifo_entry_valid_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK, reg_0_cpu_mask_status);
+    mask_status_0->qgphy_energy_off_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, QGPHY_ENERGY_OFF_INTR_MASK, reg_0_cpu_mask_status);
+    mask_status_0->qgphy_energy_on_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, QGPHY_ENERGY_ON_INTR_MASK, reg_0_cpu_mask_status);
+    mask_status_0->mdio_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MDIO_ERR_INTR_MASK, reg_0_cpu_mask_status);
+    mask_status_0->mdio_done_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MDIO_DONE_INTR_MASK, reg_0_cpu_mask_status);
+    mask_status_0->mib_reg_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MIB_REG_ERR_INTR_MASK, reg_0_cpu_mask_status);
+    mask_status_0->mac_reg_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, MAC_REG_ERR_INTR_MASK, reg_0_cpu_mask_status);
+    mask_status_0->ubus_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_STATUS, UBUS_ERR_INTR_MASK, reg_0_cpu_mask_status);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_set_0_set(const lport_intr_mask_set_0 *mask_set_0)
+{
+    uint32_t reg_0_cpu_mask_set=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_set_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((mask_set_0->mac_rx_cdc_single_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_set_0->mac_rx_cdc_double_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_set_0->mac_tx_cdc_single_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_set_0->mac_tx_cdc_double_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_set_0->qgphy_energy_off_intr_mask >= _4BITS_MAX_VAL_) ||
+       (mask_set_0->qgphy_energy_on_intr_mask >= _4BITS_MAX_VAL_) ||
+       (mask_set_0->mdio_err_intr_mask >= _1BITS_MAX_VAL_) ||
+       (mask_set_0->mdio_done_intr_mask >= _1BITS_MAX_VAL_) ||
+       (mask_set_0->mib_reg_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_set_0->mac_reg_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_set_0->ubus_err_intr_mask >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->mac_rx_cdc_single_bit_err_intr_mask);
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->mac_rx_cdc_double_bit_err_intr_mask);
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->mac_tx_cdc_single_bit_err_intr_mask);
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->mac_tx_cdc_double_bit_err_intr_mask);
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->tx_timesync_fifo_entry_valid_intr_mask);
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, QGPHY_ENERGY_OFF_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->qgphy_energy_off_intr_mask);
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, QGPHY_ENERGY_ON_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->qgphy_energy_on_intr_mask);
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, MDIO_ERR_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->mdio_err_intr_mask);
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, MDIO_DONE_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->mdio_done_intr_mask);
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, MIB_REG_ERR_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->mib_reg_err_intr_mask);
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, MAC_REG_ERR_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->mac_reg_err_intr_mask);
+    reg_0_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_SET, UBUS_ERR_INTR_MASK, reg_0_cpu_mask_set, mask_set_0->ubus_err_intr_mask);
+
+    RU_REG_WRITE(0, LPORT_INTR, 0_CPU_MASK_SET, reg_0_cpu_mask_set);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_set_0_get(lport_intr_mask_set_0 *mask_set_0)
+{
+    uint32_t reg_0_cpu_mask_set=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_set_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 0_CPU_MASK_SET, reg_0_cpu_mask_set);
+
+    mask_set_0->mac_rx_cdc_single_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_set);
+    mask_set_0->mac_rx_cdc_double_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_set);
+    mask_set_0->mac_tx_cdc_single_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_set);
+    mask_set_0->mac_tx_cdc_double_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_set);
+    mask_set_0->tx_timesync_fifo_entry_valid_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK, reg_0_cpu_mask_set);
+    mask_set_0->qgphy_energy_off_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, QGPHY_ENERGY_OFF_INTR_MASK, reg_0_cpu_mask_set);
+    mask_set_0->qgphy_energy_on_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, QGPHY_ENERGY_ON_INTR_MASK, reg_0_cpu_mask_set);
+    mask_set_0->mdio_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, MDIO_ERR_INTR_MASK, reg_0_cpu_mask_set);
+    mask_set_0->mdio_done_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, MDIO_DONE_INTR_MASK, reg_0_cpu_mask_set);
+    mask_set_0->mib_reg_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, MIB_REG_ERR_INTR_MASK, reg_0_cpu_mask_set);
+    mask_set_0->mac_reg_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, MAC_REG_ERR_INTR_MASK, reg_0_cpu_mask_set);
+    mask_set_0->ubus_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_SET, UBUS_ERR_INTR_MASK, reg_0_cpu_mask_set);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_clear_0_set(const lport_intr_mask_clear_0 *mask_clear_0)
+{
+    uint32_t reg_0_cpu_mask_clear=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_clear_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((mask_clear_0->mac_rx_cdc_single_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_clear_0->mac_rx_cdc_double_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_clear_0->mac_tx_cdc_single_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_clear_0->mac_tx_cdc_double_bit_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_clear_0->qgphy_energy_off_intr_mask >= _4BITS_MAX_VAL_) ||
+       (mask_clear_0->qgphy_energy_on_intr_mask >= _4BITS_MAX_VAL_) ||
+       (mask_clear_0->mdio_err_intr_mask >= _1BITS_MAX_VAL_) ||
+       (mask_clear_0->mdio_done_intr_mask >= _1BITS_MAX_VAL_) ||
+       (mask_clear_0->mib_reg_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_clear_0->mac_reg_err_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_clear_0->ubus_err_intr_mask >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->mac_rx_cdc_single_bit_err_intr_mask);
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->mac_rx_cdc_double_bit_err_intr_mask);
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->mac_tx_cdc_single_bit_err_intr_mask);
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->mac_tx_cdc_double_bit_err_intr_mask);
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->tx_timesync_fifo_entry_valid_intr_mask);
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, QGPHY_ENERGY_OFF_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->qgphy_energy_off_intr_mask);
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, QGPHY_ENERGY_ON_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->qgphy_energy_on_intr_mask);
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MDIO_ERR_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->mdio_err_intr_mask);
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MDIO_DONE_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->mdio_done_intr_mask);
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MIB_REG_ERR_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->mib_reg_err_intr_mask);
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MAC_REG_ERR_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->mac_reg_err_intr_mask);
+    reg_0_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, UBUS_ERR_INTR_MASK, reg_0_cpu_mask_clear, mask_clear_0->ubus_err_intr_mask);
+
+    RU_REG_WRITE(0, LPORT_INTR, 0_CPU_MASK_CLEAR, reg_0_cpu_mask_clear);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_clear_0_get(lport_intr_mask_clear_0 *mask_clear_0)
+{
+    uint32_t reg_0_cpu_mask_clear=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_clear_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 0_CPU_MASK_CLEAR, reg_0_cpu_mask_clear);
+
+    mask_clear_0->mac_rx_cdc_single_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_clear);
+    mask_clear_0->mac_rx_cdc_double_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_clear);
+    mask_clear_0->mac_tx_cdc_single_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_clear);
+    mask_clear_0->mac_tx_cdc_double_bit_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK, reg_0_cpu_mask_clear);
+    mask_clear_0->tx_timesync_fifo_entry_valid_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK, reg_0_cpu_mask_clear);
+    mask_clear_0->qgphy_energy_off_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, QGPHY_ENERGY_OFF_INTR_MASK, reg_0_cpu_mask_clear);
+    mask_clear_0->qgphy_energy_on_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, QGPHY_ENERGY_ON_INTR_MASK, reg_0_cpu_mask_clear);
+    mask_clear_0->mdio_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MDIO_ERR_INTR_MASK, reg_0_cpu_mask_clear);
+    mask_clear_0->mdio_done_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MDIO_DONE_INTR_MASK, reg_0_cpu_mask_clear);
+    mask_clear_0->mib_reg_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MIB_REG_ERR_INTR_MASK, reg_0_cpu_mask_clear);
+    mask_clear_0->mac_reg_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, MAC_REG_ERR_INTR_MASK, reg_0_cpu_mask_clear);
+    mask_clear_0->ubus_err_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 0_CPU_MASK_CLEAR, UBUS_ERR_INTR_MASK, reg_0_cpu_mask_clear);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_status_1_set(const lport_intr_status_1 *status_1)
+{
+    uint32_t reg_1_cpu_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!status_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((status_1->mab_status_intr >= _2BITS_MAX_VAL_) ||
+       (status_1->rx_remote_fault_intr >= _2BITS_MAX_VAL_) ||
+       (status_1->dserdes_sd_off_intr >= _4BITS_MAX_VAL_) ||
+       (status_1->dserdes_sd_on_intr >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_1_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_STATUS, MAB_STATUS_INTR, reg_1_cpu_status, status_1->mab_status_intr);
+    reg_1_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_STATUS, RX_REMOTE_FAULT_INTR, reg_1_cpu_status, status_1->rx_remote_fault_intr);
+    reg_1_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_STATUS, DSERDES_SD_OFF_INTR, reg_1_cpu_status, status_1->dserdes_sd_off_intr);
+    reg_1_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_STATUS, DSERDES_SD_ON_INTR, reg_1_cpu_status, status_1->dserdes_sd_on_intr);
+    reg_1_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_STATUS, LINK_DOWN_INTR, reg_1_cpu_status, status_1->link_down_intr);
+    reg_1_cpu_status = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_STATUS, LINK_UP_INTR, reg_1_cpu_status, status_1->link_up_intr);
+
+    RU_REG_WRITE(0, LPORT_INTR, 1_CPU_STATUS, reg_1_cpu_status);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_status_1_get(lport_intr_status_1 *status_1)
+{
+    uint32_t reg_1_cpu_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!status_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 1_CPU_STATUS, reg_1_cpu_status);
+
+    status_1->mab_status_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_STATUS, MAB_STATUS_INTR, reg_1_cpu_status);
+    status_1->rx_remote_fault_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_STATUS, RX_REMOTE_FAULT_INTR, reg_1_cpu_status);
+    status_1->dserdes_sd_off_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_STATUS, DSERDES_SD_OFF_INTR, reg_1_cpu_status);
+    status_1->dserdes_sd_on_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_STATUS, DSERDES_SD_ON_INTR, reg_1_cpu_status);
+    status_1->link_down_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_STATUS, LINK_DOWN_INTR, reg_1_cpu_status);
+    status_1->link_up_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_STATUS, LINK_UP_INTR, reg_1_cpu_status);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_set_1_set(const lport_intr_set_1 *set_1)
+{
+    uint32_t reg_1_cpu_set=0;
+
+#ifdef VALIDATE_PARMS
+    if(!set_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((set_1->mab_status_intr >= _2BITS_MAX_VAL_) ||
+       (set_1->rx_remote_fault_intr >= _2BITS_MAX_VAL_) ||
+       (set_1->dserdes_sd_off_intr >= _4BITS_MAX_VAL_) ||
+       (set_1->dserdes_sd_on_intr >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_1_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_SET, MAB_STATUS_INTR, reg_1_cpu_set, set_1->mab_status_intr);
+    reg_1_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_SET, RX_REMOTE_FAULT_INTR, reg_1_cpu_set, set_1->rx_remote_fault_intr);
+    reg_1_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_SET, DSERDES_SD_OFF_INTR, reg_1_cpu_set, set_1->dserdes_sd_off_intr);
+    reg_1_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_SET, DSERDES_SD_ON_INTR, reg_1_cpu_set, set_1->dserdes_sd_on_intr);
+    reg_1_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_SET, LINK_DOWN_INTR, reg_1_cpu_set, set_1->link_down_intr);
+    reg_1_cpu_set = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_SET, LINK_UP_INTR, reg_1_cpu_set, set_1->link_up_intr);
+
+    RU_REG_WRITE(0, LPORT_INTR, 1_CPU_SET, reg_1_cpu_set);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_set_1_get(lport_intr_set_1 *set_1)
+{
+    uint32_t reg_1_cpu_set=0;
+
+#ifdef VALIDATE_PARMS
+    if(!set_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 1_CPU_SET, reg_1_cpu_set);
+
+    set_1->mab_status_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_SET, MAB_STATUS_INTR, reg_1_cpu_set);
+    set_1->rx_remote_fault_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_SET, RX_REMOTE_FAULT_INTR, reg_1_cpu_set);
+    set_1->dserdes_sd_off_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_SET, DSERDES_SD_OFF_INTR, reg_1_cpu_set);
+    set_1->dserdes_sd_on_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_SET, DSERDES_SD_ON_INTR, reg_1_cpu_set);
+    set_1->link_down_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_SET, LINK_DOWN_INTR, reg_1_cpu_set);
+    set_1->link_up_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_SET, LINK_UP_INTR, reg_1_cpu_set);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_clear_1_set(const lport_intr_clear_1 *clear_1)
+{
+    uint32_t reg_1_cpu_clear=0;
+
+#ifdef VALIDATE_PARMS
+    if(!clear_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((clear_1->mab_status_intr >= _2BITS_MAX_VAL_) ||
+       (clear_1->rx_remote_fault_intr >= _2BITS_MAX_VAL_) ||
+       (clear_1->dserdes_sd_off_intr >= _4BITS_MAX_VAL_) ||
+       (clear_1->dserdes_sd_on_intr >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_1_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_CLEAR, MAB_STATUS_INTR, reg_1_cpu_clear, clear_1->mab_status_intr);
+    reg_1_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_CLEAR, RX_REMOTE_FAULT_INTR, reg_1_cpu_clear, clear_1->rx_remote_fault_intr);
+    reg_1_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_CLEAR, DSERDES_SD_OFF_INTR, reg_1_cpu_clear, clear_1->dserdes_sd_off_intr);
+    reg_1_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_CLEAR, DSERDES_SD_ON_INTR, reg_1_cpu_clear, clear_1->dserdes_sd_on_intr);
+    reg_1_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_CLEAR, LINK_DOWN_INTR, reg_1_cpu_clear, clear_1->link_down_intr);
+    reg_1_cpu_clear = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_CLEAR, LINK_UP_INTR, reg_1_cpu_clear, clear_1->link_up_intr);
+
+    RU_REG_WRITE(0, LPORT_INTR, 1_CPU_CLEAR, reg_1_cpu_clear);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_clear_1_get(lport_intr_clear_1 *clear_1)
+{
+    uint32_t reg_1_cpu_clear=0;
+
+#ifdef VALIDATE_PARMS
+    if(!clear_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 1_CPU_CLEAR, reg_1_cpu_clear);
+
+    clear_1->mab_status_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_CLEAR, MAB_STATUS_INTR, reg_1_cpu_clear);
+    clear_1->rx_remote_fault_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_CLEAR, RX_REMOTE_FAULT_INTR, reg_1_cpu_clear);
+    clear_1->dserdes_sd_off_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_CLEAR, DSERDES_SD_OFF_INTR, reg_1_cpu_clear);
+    clear_1->dserdes_sd_on_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_CLEAR, DSERDES_SD_ON_INTR, reg_1_cpu_clear);
+    clear_1->link_down_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_CLEAR, LINK_DOWN_INTR, reg_1_cpu_clear);
+    clear_1->link_up_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_CLEAR, LINK_UP_INTR, reg_1_cpu_clear);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_status_1_set(const lport_intr_mask_status_1 *mask_status_1)
+{
+    uint32_t reg_1_cpu_mask_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_status_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((mask_status_1->rx_remote_fault_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_status_1->dserdes_sd_off_intr >= _4BITS_MAX_VAL_) ||
+       (mask_status_1->dserdes_sd_on_intr >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_1_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_STATUS, RX_REMOTE_FAULT_INTR_MASK, reg_1_cpu_mask_status, mask_status_1->rx_remote_fault_intr_mask);
+    reg_1_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_STATUS, DSERDES_SD_OFF_INTR, reg_1_cpu_mask_status, mask_status_1->dserdes_sd_off_intr);
+    reg_1_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_STATUS, DSERDES_SD_ON_INTR, reg_1_cpu_mask_status, mask_status_1->dserdes_sd_on_intr);
+    reg_1_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_STATUS, LINK_DOWN_INTR_MASK, reg_1_cpu_mask_status, mask_status_1->link_down_intr_mask);
+    reg_1_cpu_mask_status = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_STATUS, LINK_UP_INTR_MASK, reg_1_cpu_mask_status, mask_status_1->link_up_intr_mask);
+
+    RU_REG_WRITE(0, LPORT_INTR, 1_CPU_MASK_STATUS, reg_1_cpu_mask_status);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_status_1_get(lport_intr_mask_status_1 *mask_status_1)
+{
+    uint32_t reg_1_cpu_mask_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_status_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 1_CPU_MASK_STATUS, reg_1_cpu_mask_status);
+
+    mask_status_1->rx_remote_fault_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_STATUS, RX_REMOTE_FAULT_INTR_MASK, reg_1_cpu_mask_status);
+    mask_status_1->dserdes_sd_off_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_STATUS, DSERDES_SD_OFF_INTR, reg_1_cpu_mask_status);
+    mask_status_1->dserdes_sd_on_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_STATUS, DSERDES_SD_ON_INTR, reg_1_cpu_mask_status);
+    mask_status_1->link_down_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_STATUS, LINK_DOWN_INTR_MASK, reg_1_cpu_mask_status);
+    mask_status_1->link_up_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_STATUS, LINK_UP_INTR_MASK, reg_1_cpu_mask_status);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_set_1_set(const lport_intr_mask_set_1 *mask_set_1)
+{
+    uint32_t reg_1_cpu_mask_set=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_set_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((mask_set_1->rx_remote_fault_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_set_1->dserdes_sd_off_intr >= _4BITS_MAX_VAL_) ||
+       (mask_set_1->dserdes_sd_on_intr >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_1_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_SET, RX_REMOTE_FAULT_INTR_MASK, reg_1_cpu_mask_set, mask_set_1->rx_remote_fault_intr_mask);
+    reg_1_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_SET, DSERDES_SD_OFF_INTR, reg_1_cpu_mask_set, mask_set_1->dserdes_sd_off_intr);
+    reg_1_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_SET, DSERDES_SD_ON_INTR, reg_1_cpu_mask_set, mask_set_1->dserdes_sd_on_intr);
+    reg_1_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_SET, LINK_DOWN_INTR_MASK, reg_1_cpu_mask_set, mask_set_1->link_down_intr_mask);
+    reg_1_cpu_mask_set = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_SET, LINK_UP_INTR_MASK, reg_1_cpu_mask_set, mask_set_1->link_up_intr_mask);
+
+    RU_REG_WRITE(0, LPORT_INTR, 1_CPU_MASK_SET, reg_1_cpu_mask_set);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_set_1_get(lport_intr_mask_set_1 *mask_set_1)
+{
+    uint32_t reg_1_cpu_mask_set=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_set_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 1_CPU_MASK_SET, reg_1_cpu_mask_set);
+
+    mask_set_1->rx_remote_fault_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_SET, RX_REMOTE_FAULT_INTR_MASK, reg_1_cpu_mask_set);
+    mask_set_1->dserdes_sd_off_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_SET, DSERDES_SD_OFF_INTR, reg_1_cpu_mask_set);
+    mask_set_1->dserdes_sd_on_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_SET, DSERDES_SD_ON_INTR, reg_1_cpu_mask_set);
+    mask_set_1->link_down_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_SET, LINK_DOWN_INTR_MASK, reg_1_cpu_mask_set);
+    mask_set_1->link_up_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_SET, LINK_UP_INTR_MASK, reg_1_cpu_mask_set);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_clear_1_set(const lport_intr_mask_clear_1 *mask_clear_1)
+{
+    uint32_t reg_1_cpu_mask_clear=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_clear_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((mask_clear_1->rx_remote_fault_intr_mask >= _2BITS_MAX_VAL_) ||
+       (mask_clear_1->dserdes_sd_off_intr >= _4BITS_MAX_VAL_) ||
+       (mask_clear_1->dserdes_sd_on_intr >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_1_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_CLEAR, RX_REMOTE_FAULT_INTR_MASK, reg_1_cpu_mask_clear, mask_clear_1->rx_remote_fault_intr_mask);
+    reg_1_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_CLEAR, DSERDES_SD_OFF_INTR, reg_1_cpu_mask_clear, mask_clear_1->dserdes_sd_off_intr);
+    reg_1_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_CLEAR, DSERDES_SD_ON_INTR, reg_1_cpu_mask_clear, mask_clear_1->dserdes_sd_on_intr);
+    reg_1_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_CLEAR, LINK_DOWN_INTR_MASK, reg_1_cpu_mask_clear, mask_clear_1->link_down_intr_mask);
+    reg_1_cpu_mask_clear = RU_FIELD_SET(0, LPORT_INTR, 1_CPU_MASK_CLEAR, LINK_UP_INTR_MASK, reg_1_cpu_mask_clear, mask_clear_1->link_up_intr_mask);
+
+    RU_REG_WRITE(0, LPORT_INTR, 1_CPU_MASK_CLEAR, reg_1_cpu_mask_clear);
+
+    return 0;
+}
+
+int ag_drv_lport_intr_mask_clear_1_get(lport_intr_mask_clear_1 *mask_clear_1)
+{
+    uint32_t reg_1_cpu_mask_clear=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mask_clear_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_INTR, 1_CPU_MASK_CLEAR, reg_1_cpu_mask_clear);
+
+    mask_clear_1->rx_remote_fault_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_CLEAR, RX_REMOTE_FAULT_INTR_MASK, reg_1_cpu_mask_clear);
+    mask_clear_1->dserdes_sd_off_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_CLEAR, DSERDES_SD_OFF_INTR, reg_1_cpu_mask_clear);
+    mask_clear_1->dserdes_sd_on_intr = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_CLEAR, DSERDES_SD_ON_INTR, reg_1_cpu_mask_clear);
+    mask_clear_1->link_down_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_CLEAR, LINK_DOWN_INTR_MASK, reg_1_cpu_mask_clear);
+    mask_clear_1->link_up_intr_mask = RU_FIELD_GET(0, LPORT_INTR, 1_CPU_MASK_CLEAR, LINK_UP_INTR_MASK, reg_1_cpu_mask_clear);
+
+    return 0;
+}
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_intr_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_lport_intr_ag.h
new file mode 100644
index 0000000000..39f30741a6
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_intr_ag.h
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_LPORT_INTR_AG_H_
+#define _BCM6858_LPORT_INTR_AG_H_
+
+#include "access_macros.h"
+#include "bcmtypes.h"
+typedef struct
+{
+    uint8_t xlmac_intr;
+    uint8_t tx_timesync_fifo_entry_valid_intr;
+    uint8_t qgphy_energy_off_intr;
+    uint8_t qgphy_energy_on_intr;
+    uint8_t mdio_err_intr;
+    uint8_t mdio_done_intr;
+    uint8_t mib_reg_err_intr;
+    uint8_t mac_reg_err_intr;
+    uint8_t ubus_err_intr;
+} lport_intr_status_0;
+
+typedef struct
+{
+    uint8_t xlmac_intr;
+    uint8_t tx_timesync_fifo_entry_valid_intr;
+    uint8_t qgphy_energy_off_intr;
+    uint8_t qgphy_energy_on_intr;
+    uint8_t mdio_err_intr;
+    uint8_t mdio_done_intr;
+    uint8_t mib_reg_err_intr;
+    uint8_t mac_reg_err_intr;
+    uint8_t ubus_err_intr;
+} lport_intr_set_0;
+
+typedef struct
+{
+    uint8_t xlmac_intr;
+    uint8_t tx_timesync_fifo_entry_valid_intr;
+    uint8_t qgphy_energy_off_intr;
+    uint8_t qgphy_energy_on_intr;
+    uint8_t mdio_err_intr;
+    uint8_t mdio_done_intr;
+    uint8_t mib_reg_err_intr;
+    uint8_t mac_reg_err_intr;
+    uint8_t ubus_err_intr;
+} lport_intr_clear_0;
+
+typedef struct
+{
+    uint8_t mac_rx_cdc_single_bit_err_intr_mask;
+    uint8_t mac_rx_cdc_double_bit_err_intr_mask;
+    uint8_t mac_tx_cdc_single_bit_err_intr_mask;
+    uint8_t mac_tx_cdc_double_bit_err_intr_mask;
+    uint8_t tx_timesync_fifo_entry_valid_intr_mask;
+    uint8_t qgphy_energy_off_intr_mask;
+    uint8_t qgphy_energy_on_intr_mask;
+    uint8_t mdio_err_intr_mask;
+    uint8_t mdio_done_intr_mask;
+    uint8_t mib_reg_err_intr_mask;
+    uint8_t mac_reg_err_intr_mask;
+    uint8_t ubus_err_intr_mask;
+} lport_intr_mask_status_0;
+
+typedef struct
+{
+    uint8_t mac_rx_cdc_single_bit_err_intr_mask;
+    uint8_t mac_rx_cdc_double_bit_err_intr_mask;
+    uint8_t mac_tx_cdc_single_bit_err_intr_mask;
+    uint8_t mac_tx_cdc_double_bit_err_intr_mask;
+    uint8_t tx_timesync_fifo_entry_valid_intr_mask;
+    uint8_t qgphy_energy_off_intr_mask;
+    uint8_t qgphy_energy_on_intr_mask;
+    uint8_t mdio_err_intr_mask;
+    uint8_t mdio_done_intr_mask;
+    uint8_t mib_reg_err_intr_mask;
+    uint8_t mac_reg_err_intr_mask;
+    uint8_t ubus_err_intr_mask;
+} lport_intr_mask_set_0;
+
+typedef struct
+{
+    uint8_t mac_rx_cdc_single_bit_err_intr_mask;
+    uint8_t mac_rx_cdc_double_bit_err_intr_mask;
+    uint8_t mac_tx_cdc_single_bit_err_intr_mask;
+    uint8_t mac_tx_cdc_double_bit_err_intr_mask;
+    uint8_t tx_timesync_fifo_entry_valid_intr_mask;
+    uint8_t qgphy_energy_off_intr_mask;
+    uint8_t qgphy_energy_on_intr_mask;
+    uint8_t mdio_err_intr_mask;
+    uint8_t mdio_done_intr_mask;
+    uint8_t mib_reg_err_intr_mask;
+    uint8_t mac_reg_err_intr_mask;
+    uint8_t ubus_err_intr_mask;
+} lport_intr_mask_clear_0;
+
+typedef struct
+{
+    uint8_t mab_status_intr;
+    uint8_t rx_remote_fault_intr;
+    uint8_t dserdes_sd_off_intr;
+    uint8_t dserdes_sd_on_intr;
+    uint8_t link_down_intr;
+    uint8_t link_up_intr;
+} lport_intr_status_1;
+
+typedef struct
+{
+    uint8_t mab_status_intr;
+    uint8_t rx_remote_fault_intr;
+    uint8_t dserdes_sd_off_intr;
+    uint8_t dserdes_sd_on_intr;
+    uint8_t link_down_intr;
+    uint8_t link_up_intr;
+} lport_intr_set_1;
+
+typedef struct
+{
+    uint8_t mab_status_intr;
+    uint8_t rx_remote_fault_intr;
+    uint8_t dserdes_sd_off_intr;
+    uint8_t dserdes_sd_on_intr;
+    uint8_t link_down_intr;
+    uint8_t link_up_intr;
+} lport_intr_clear_1;
+
+typedef struct
+{
+    uint8_t rx_remote_fault_intr_mask;
+    uint8_t dserdes_sd_off_intr;
+    uint8_t dserdes_sd_on_intr;
+    uint8_t link_down_intr_mask;
+    uint8_t link_up_intr_mask;
+} lport_intr_mask_status_1;
+
+typedef struct
+{
+    uint8_t rx_remote_fault_intr_mask;
+    uint8_t dserdes_sd_off_intr;
+    uint8_t dserdes_sd_on_intr;
+    uint8_t link_down_intr_mask;
+    uint8_t link_up_intr_mask;
+} lport_intr_mask_set_1;
+
+typedef struct
+{
+    uint8_t rx_remote_fault_intr_mask;
+    uint8_t dserdes_sd_off_intr;
+    uint8_t dserdes_sd_on_intr;
+    uint8_t link_down_intr_mask;
+    uint8_t link_up_intr_mask;
+} lport_intr_mask_clear_1;
+
+int ag_drv_lport_intr_status_0_set(const lport_intr_status_0 *status_0);
+int ag_drv_lport_intr_status_0_get(lport_intr_status_0 *status_0);
+int ag_drv_lport_intr_set_0_set(const lport_intr_set_0 *set_0);
+int ag_drv_lport_intr_set_0_get(lport_intr_set_0 *set_0);
+int ag_drv_lport_intr_clear_0_set(const lport_intr_clear_0 *clear_0);
+int ag_drv_lport_intr_clear_0_get(lport_intr_clear_0 *clear_0);
+int ag_drv_lport_intr_mask_status_0_set(const lport_intr_mask_status_0 *mask_status_0);
+int ag_drv_lport_intr_mask_status_0_get(lport_intr_mask_status_0 *mask_status_0);
+int ag_drv_lport_intr_mask_set_0_set(const lport_intr_mask_set_0 *mask_set_0);
+int ag_drv_lport_intr_mask_set_0_get(lport_intr_mask_set_0 *mask_set_0);
+int ag_drv_lport_intr_mask_clear_0_set(const lport_intr_mask_clear_0 *mask_clear_0);
+int ag_drv_lport_intr_mask_clear_0_get(lport_intr_mask_clear_0 *mask_clear_0);
+int ag_drv_lport_intr_status_1_set(const lport_intr_status_1 *status_1);
+int ag_drv_lport_intr_status_1_get(lport_intr_status_1 *status_1);
+int ag_drv_lport_intr_set_1_set(const lport_intr_set_1 *set_1);
+int ag_drv_lport_intr_set_1_get(lport_intr_set_1 *set_1);
+int ag_drv_lport_intr_clear_1_set(const lport_intr_clear_1 *clear_1);
+int ag_drv_lport_intr_clear_1_get(lport_intr_clear_1 *clear_1);
+int ag_drv_lport_intr_mask_status_1_set(const lport_intr_mask_status_1 *mask_status_1);
+int ag_drv_lport_intr_mask_status_1_get(lport_intr_mask_status_1 *mask_status_1);
+int ag_drv_lport_intr_mask_set_1_set(const lport_intr_mask_set_1 *mask_set_1);
+int ag_drv_lport_intr_mask_set_1_get(lport_intr_mask_set_1 *mask_set_1);
+int ag_drv_lport_intr_mask_clear_1_set(const lport_intr_mask_clear_1 *mask_clear_1);
+int ag_drv_lport_intr_mask_clear_1_get(lport_intr_mask_clear_1 *mask_clear_1);
+
+#ifdef USE_BDMF_SHELL
+bdmfmon_handle_t ag_drv_lport_intr_cli_init(bdmfmon_handle_t driver_dir);
+#endif
+
+
+#endif
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_led_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_lport_led_ag.c
new file mode 100644
index 0000000000..459baedf3b
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_led_ag.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_lport_led_ag.h"
+#define BLOCK_ADDR_COUNT_BITS 3
+#define BLOCK_ADDR_COUNT (1<<BLOCK_ADDR_COUNT_BITS)
+
+int ag_drv_lport_led_cntrl_set(uint8_t led_id, const lport_led_cntrl *cntrl)
+{
+    uint32_t reg_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((led_id >= BLOCK_ADDR_COUNT) ||
+       (cntrl->lnk_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (cntrl->spd_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (cntrl->lnk_status_ovrd >= _1BITS_MAX_VAL_) ||
+       (cntrl->led_spd_ovrd >= _3BITS_MAX_VAL_) ||
+       (cntrl->act_led_pol_sel >= _1BITS_MAX_VAL_) ||
+       (cntrl->spdlnk_led2_act_pol_sel >= _1BITS_MAX_VAL_) ||
+       (cntrl->spdlnk_led1_act_pol_sel >= _1BITS_MAX_VAL_) ||
+       (cntrl->spdlnk_led0_act_pol_sel >= _1BITS_MAX_VAL_) ||
+       (cntrl->act_led_act_sel >= _1BITS_MAX_VAL_) ||
+       (cntrl->spdlnk_led2_act_sel >= _1BITS_MAX_VAL_) ||
+       (cntrl->spdlnk_led1_act_sel >= _1BITS_MAX_VAL_) ||
+       (cntrl->spdlnk_led0_act_sel >= _1BITS_MAX_VAL_) ||
+       (cntrl->tx_act_en >= _1BITS_MAX_VAL_) ||
+       (cntrl->rx_act_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, LNK_OVRD_EN, reg_cntrl, cntrl->lnk_ovrd_en);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, SPD_OVRD_EN, reg_cntrl, cntrl->spd_ovrd_en);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, LNK_STATUS_OVRD, reg_cntrl, cntrl->lnk_status_ovrd);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, LED_SPD_OVRD, reg_cntrl, cntrl->led_spd_ovrd);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, ACT_LED_POL_SEL, reg_cntrl, cntrl->act_led_pol_sel);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, SPDLNK_LED2_ACT_POL_SEL, reg_cntrl, cntrl->spdlnk_led2_act_pol_sel);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, SPDLNK_LED1_ACT_POL_SEL, reg_cntrl, cntrl->spdlnk_led1_act_pol_sel);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, SPDLNK_LED0_ACT_POL_SEL, reg_cntrl, cntrl->spdlnk_led0_act_pol_sel);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, ACT_LED_ACT_SEL, reg_cntrl, cntrl->act_led_act_sel);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, SPDLNK_LED2_ACT_SEL, reg_cntrl, cntrl->spdlnk_led2_act_sel);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, SPDLNK_LED1_ACT_SEL, reg_cntrl, cntrl->spdlnk_led1_act_sel);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, SPDLNK_LED0_ACT_SEL, reg_cntrl, cntrl->spdlnk_led0_act_sel);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, TX_ACT_EN, reg_cntrl, cntrl->tx_act_en);
+    reg_cntrl = RU_FIELD_SET(led_id, LPORT_LED, CNTRL, RX_ACT_EN, reg_cntrl, cntrl->rx_act_en);
+
+    RU_REG_WRITE(led_id, LPORT_LED, CNTRL, reg_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_led_cntrl_get(uint8_t led_id, lport_led_cntrl *cntrl)
+{
+    uint32_t reg_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((led_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(led_id, LPORT_LED, CNTRL, reg_cntrl);
+
+    cntrl->lnk_ovrd_en = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, LNK_OVRD_EN, reg_cntrl);
+    cntrl->spd_ovrd_en = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, SPD_OVRD_EN, reg_cntrl);
+    cntrl->lnk_status_ovrd = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, LNK_STATUS_OVRD, reg_cntrl);
+    cntrl->led_spd_ovrd = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, LED_SPD_OVRD, reg_cntrl);
+    cntrl->act_led_pol_sel = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, ACT_LED_POL_SEL, reg_cntrl);
+    cntrl->spdlnk_led2_act_pol_sel = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, SPDLNK_LED2_ACT_POL_SEL, reg_cntrl);
+    cntrl->spdlnk_led1_act_pol_sel = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, SPDLNK_LED1_ACT_POL_SEL, reg_cntrl);
+    cntrl->spdlnk_led0_act_pol_sel = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, SPDLNK_LED0_ACT_POL_SEL, reg_cntrl);
+    cntrl->act_led_act_sel = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, ACT_LED_ACT_SEL, reg_cntrl);
+    cntrl->spdlnk_led2_act_sel = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, SPDLNK_LED2_ACT_SEL, reg_cntrl);
+    cntrl->spdlnk_led1_act_sel = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, SPDLNK_LED1_ACT_SEL, reg_cntrl);
+    cntrl->spdlnk_led0_act_sel = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, SPDLNK_LED0_ACT_SEL, reg_cntrl);
+    cntrl->tx_act_en = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, TX_ACT_EN, reg_cntrl);
+    cntrl->rx_act_en = RU_FIELD_GET(led_id, LPORT_LED, CNTRL, RX_ACT_EN, reg_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_led_link_and_speed_encoding_sel_set(uint8_t led_id, const lport_led_link_and_speed_encoding_sel *link_and_speed_encoding_sel)
+{
+    uint32_t reg_link_and_speed_encoding_sel=0;
+
+#ifdef VALIDATE_PARMS
+    if(!link_and_speed_encoding_sel)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((led_id >= BLOCK_ADDR_COUNT) ||
+       (link_and_speed_encoding_sel->rsvd_sel_spd_encode_2 >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding_sel->rsvd_sel_spd_encode_1 >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding_sel->sel_10g_encode >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding_sel->sel_2500m_encode >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding_sel->sel_1000m_encode >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding_sel->sel_100m_encode >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding_sel->sel_10m_encode >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding_sel->sel_no_link_encode >= _3BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_link_and_speed_encoding_sel = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, RSVD_SEL_SPD_ENCODE_2, reg_link_and_speed_encoding_sel, link_and_speed_encoding_sel->rsvd_sel_spd_encode_2);
+    reg_link_and_speed_encoding_sel = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, RSVD_SEL_SPD_ENCODE_1, reg_link_and_speed_encoding_sel, link_and_speed_encoding_sel->rsvd_sel_spd_encode_1);
+    reg_link_and_speed_encoding_sel = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_10G_ENCODE, reg_link_and_speed_encoding_sel, link_and_speed_encoding_sel->sel_10g_encode);
+    reg_link_and_speed_encoding_sel = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_2500M_ENCODE, reg_link_and_speed_encoding_sel, link_and_speed_encoding_sel->sel_2500m_encode);
+    reg_link_and_speed_encoding_sel = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_1000M_ENCODE, reg_link_and_speed_encoding_sel, link_and_speed_encoding_sel->sel_1000m_encode);
+    reg_link_and_speed_encoding_sel = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_100M_ENCODE, reg_link_and_speed_encoding_sel, link_and_speed_encoding_sel->sel_100m_encode);
+    reg_link_and_speed_encoding_sel = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_10M_ENCODE, reg_link_and_speed_encoding_sel, link_and_speed_encoding_sel->sel_10m_encode);
+    reg_link_and_speed_encoding_sel = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_NO_LINK_ENCODE, reg_link_and_speed_encoding_sel, link_and_speed_encoding_sel->sel_no_link_encode);
+
+    RU_REG_WRITE(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, reg_link_and_speed_encoding_sel);
+
+    return 0;
+}
+
+int ag_drv_lport_led_link_and_speed_encoding_sel_get(uint8_t led_id, lport_led_link_and_speed_encoding_sel *link_and_speed_encoding_sel)
+{
+    uint32_t reg_link_and_speed_encoding_sel=0;
+
+#ifdef VALIDATE_PARMS
+    if(!link_and_speed_encoding_sel)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((led_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, reg_link_and_speed_encoding_sel);
+
+    link_and_speed_encoding_sel->rsvd_sel_spd_encode_2 = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, RSVD_SEL_SPD_ENCODE_2, reg_link_and_speed_encoding_sel);
+    link_and_speed_encoding_sel->rsvd_sel_spd_encode_1 = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, RSVD_SEL_SPD_ENCODE_1, reg_link_and_speed_encoding_sel);
+    link_and_speed_encoding_sel->sel_10g_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_10G_ENCODE, reg_link_and_speed_encoding_sel);
+    link_and_speed_encoding_sel->sel_2500m_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_2500M_ENCODE, reg_link_and_speed_encoding_sel);
+    link_and_speed_encoding_sel->sel_1000m_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_1000M_ENCODE, reg_link_and_speed_encoding_sel);
+    link_and_speed_encoding_sel->sel_100m_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_100M_ENCODE, reg_link_and_speed_encoding_sel);
+    link_and_speed_encoding_sel->sel_10m_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_10M_ENCODE, reg_link_and_speed_encoding_sel);
+    link_and_speed_encoding_sel->sel_no_link_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING_SEL, SEL_NO_LINK_ENCODE, reg_link_and_speed_encoding_sel);
+
+    return 0;
+}
+
+int ag_drv_lport_led_link_and_speed_encoding_set(uint8_t led_id, const lport_led_link_and_speed_encoding *link_and_speed_encoding)
+{
+    uint32_t reg_link_and_speed_encoding=0;
+
+#ifdef VALIDATE_PARMS
+    if(!link_and_speed_encoding)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((led_id >= BLOCK_ADDR_COUNT) ||
+       (link_and_speed_encoding->rsvd_spd_encode_2 >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding->rsvd_spd_encode_1 >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding->m10g_encode >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding->m2500_encode >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding->m1000_encode >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding->m100_encode >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding->m10_encode >= _3BITS_MAX_VAL_) ||
+       (link_and_speed_encoding->no_link_encode >= _3BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_link_and_speed_encoding = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, RSVD_SPD_ENCODE_2, reg_link_and_speed_encoding, link_and_speed_encoding->rsvd_spd_encode_2);
+    reg_link_and_speed_encoding = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, RSVD_SPD_ENCODE_1, reg_link_and_speed_encoding, link_and_speed_encoding->rsvd_spd_encode_1);
+    reg_link_and_speed_encoding = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, M10G_ENCODE, reg_link_and_speed_encoding, link_and_speed_encoding->m10g_encode);
+    reg_link_and_speed_encoding = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, M2500_ENCODE, reg_link_and_speed_encoding, link_and_speed_encoding->m2500_encode);
+    reg_link_and_speed_encoding = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, M1000_ENCODE, reg_link_and_speed_encoding, link_and_speed_encoding->m1000_encode);
+    reg_link_and_speed_encoding = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, M100_ENCODE, reg_link_and_speed_encoding, link_and_speed_encoding->m100_encode);
+    reg_link_and_speed_encoding = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, M10_ENCODE, reg_link_and_speed_encoding, link_and_speed_encoding->m10_encode);
+    reg_link_and_speed_encoding = RU_FIELD_SET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, NO_LINK_ENCODE, reg_link_and_speed_encoding, link_and_speed_encoding->no_link_encode);
+
+    RU_REG_WRITE(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, reg_link_and_speed_encoding);
+
+    return 0;
+}
+
+int ag_drv_lport_led_link_and_speed_encoding_get(uint8_t led_id, lport_led_link_and_speed_encoding *link_and_speed_encoding)
+{
+    uint32_t reg_link_and_speed_encoding=0;
+
+#ifdef VALIDATE_PARMS
+    if(!link_and_speed_encoding)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((led_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, reg_link_and_speed_encoding);
+
+    link_and_speed_encoding->rsvd_spd_encode_2 = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, RSVD_SPD_ENCODE_2, reg_link_and_speed_encoding);
+    link_and_speed_encoding->rsvd_spd_encode_1 = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, RSVD_SPD_ENCODE_1, reg_link_and_speed_encoding);
+    link_and_speed_encoding->m10g_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, M10G_ENCODE, reg_link_and_speed_encoding);
+    link_and_speed_encoding->m2500_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, M2500_ENCODE, reg_link_and_speed_encoding);
+    link_and_speed_encoding->m1000_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, M1000_ENCODE, reg_link_and_speed_encoding);
+    link_and_speed_encoding->m100_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, M100_ENCODE, reg_link_and_speed_encoding);
+    link_and_speed_encoding->m10_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, M10_ENCODE, reg_link_and_speed_encoding);
+    link_and_speed_encoding->no_link_encode = RU_FIELD_GET(led_id, LPORT_LED, LINK_AND_SPEED_ENCODING, NO_LINK_ENCODE, reg_link_and_speed_encoding);
+
+    return 0;
+}
+
+int ag_drv_lport_led_aggregate_led_cntrl_set(uint8_t led_id, uint8_t lnk_pol_sel, uint8_t act_pol_sel, uint8_t act_sel, uint16_t port_en)
+{
+    uint32_t reg_aggregate_led_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if((led_id >= BLOCK_ADDR_COUNT) ||
+       (lnk_pol_sel >= _1BITS_MAX_VAL_) ||
+       (act_pol_sel >= _1BITS_MAX_VAL_) ||
+       (act_sel >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_aggregate_led_cntrl = RU_FIELD_SET(led_id, LPORT_LED, AGGREGATE_LED_CNTRL, LNK_POL_SEL, reg_aggregate_led_cntrl, lnk_pol_sel);
+    reg_aggregate_led_cntrl = RU_FIELD_SET(led_id, LPORT_LED, AGGREGATE_LED_CNTRL, ACT_POL_SEL, reg_aggregate_led_cntrl, act_pol_sel);
+    reg_aggregate_led_cntrl = RU_FIELD_SET(led_id, LPORT_LED, AGGREGATE_LED_CNTRL, ACT_SEL, reg_aggregate_led_cntrl, act_sel);
+    reg_aggregate_led_cntrl = RU_FIELD_SET(led_id, LPORT_LED, AGGREGATE_LED_CNTRL, PORT_EN, reg_aggregate_led_cntrl, port_en);
+
+    RU_REG_WRITE(led_id, LPORT_LED, AGGREGATE_LED_CNTRL, reg_aggregate_led_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_led_aggregate_led_cntrl_get(uint8_t led_id, uint8_t *lnk_pol_sel, uint8_t *act_pol_sel, uint8_t *act_sel, uint16_t *port_en)
+{
+    uint32_t reg_aggregate_led_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!lnk_pol_sel || !act_pol_sel || !act_sel || !port_en)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((led_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(led_id, LPORT_LED, AGGREGATE_LED_CNTRL, reg_aggregate_led_cntrl);
+
+    *lnk_pol_sel = RU_FIELD_GET(led_id, LPORT_LED, AGGREGATE_LED_CNTRL, LNK_POL_SEL, reg_aggregate_led_cntrl);
+    *act_pol_sel = RU_FIELD_GET(led_id, LPORT_LED, AGGREGATE_LED_CNTRL, ACT_POL_SEL, reg_aggregate_led_cntrl);
+    *act_sel = RU_FIELD_GET(led_id, LPORT_LED, AGGREGATE_LED_CNTRL, ACT_SEL, reg_aggregate_led_cntrl);
+    *port_en = RU_FIELD_GET(led_id, LPORT_LED, AGGREGATE_LED_CNTRL, PORT_EN, reg_aggregate_led_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_led_aggregate_led_blink_rate_cntrl_set(uint8_t led_id, uint16_t led_on_time, uint16_t led_off_time)
+{
+    uint32_t reg_aggregate_led_blink_rate_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if((led_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_aggregate_led_blink_rate_cntrl = RU_FIELD_SET(led_id, LPORT_LED, AGGREGATE_LED_BLINK_RATE_CNTRL, LED_ON_TIME, reg_aggregate_led_blink_rate_cntrl, led_on_time);
+    reg_aggregate_led_blink_rate_cntrl = RU_FIELD_SET(led_id, LPORT_LED, AGGREGATE_LED_BLINK_RATE_CNTRL, LED_OFF_TIME, reg_aggregate_led_blink_rate_cntrl, led_off_time);
+
+    RU_REG_WRITE(led_id, LPORT_LED, AGGREGATE_LED_BLINK_RATE_CNTRL, reg_aggregate_led_blink_rate_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_led_aggregate_led_blink_rate_cntrl_get(uint8_t led_id, uint16_t *led_on_time, uint16_t *led_off_time)
+{
+    uint32_t reg_aggregate_led_blink_rate_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!led_on_time || !led_off_time)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((led_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(led_id, LPORT_LED, AGGREGATE_LED_BLINK_RATE_CNTRL, reg_aggregate_led_blink_rate_cntrl);
+
+    *led_on_time = RU_FIELD_GET(led_id, LPORT_LED, AGGREGATE_LED_BLINK_RATE_CNTRL, LED_ON_TIME, reg_aggregate_led_blink_rate_cntrl);
+    *led_off_time = RU_FIELD_GET(led_id, LPORT_LED, AGGREGATE_LED_BLINK_RATE_CNTRL, LED_OFF_TIME, reg_aggregate_led_blink_rate_cntrl);
+
+    return 0;
+}
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_led_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_lport_led_ag.h
new file mode 100644
index 0000000000..99a3c8aed8
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_led_ag.h
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_LPORT_LED_AG_H_
+#define _BCM6858_LPORT_LED_AG_H_
+
+#include "access_macros.h"
+#include "bcmtypes.h"
+typedef struct
+{
+    uint8_t lnk_ovrd_en;
+    uint8_t spd_ovrd_en;
+    uint8_t lnk_status_ovrd;
+    uint8_t led_spd_ovrd;
+    uint8_t act_led_pol_sel;
+    uint8_t spdlnk_led2_act_pol_sel;
+    uint8_t spdlnk_led1_act_pol_sel;
+    uint8_t spdlnk_led0_act_pol_sel;
+    uint8_t act_led_act_sel;
+    uint8_t spdlnk_led2_act_sel;
+    uint8_t spdlnk_led1_act_sel;
+    uint8_t spdlnk_led0_act_sel;
+    uint8_t tx_act_en;
+    uint8_t rx_act_en;
+} lport_led_cntrl;
+
+typedef struct
+{
+    uint8_t rsvd_sel_spd_encode_2;
+    uint8_t rsvd_sel_spd_encode_1;
+    uint8_t sel_10g_encode;
+    uint8_t sel_2500m_encode;
+    uint8_t sel_1000m_encode;
+    uint8_t sel_100m_encode;
+    uint8_t sel_10m_encode;
+    uint8_t sel_no_link_encode;
+} lport_led_link_and_speed_encoding_sel;
+
+typedef struct
+{
+    uint8_t rsvd_spd_encode_2;
+    uint8_t rsvd_spd_encode_1;
+    uint8_t m10g_encode;
+    uint8_t m2500_encode;
+    uint8_t m1000_encode;
+    uint8_t m100_encode;
+    uint8_t m10_encode;
+    uint8_t no_link_encode;
+} lport_led_link_and_speed_encoding;
+
+int ag_drv_lport_led_cntrl_set(uint8_t led_id, const lport_led_cntrl *cntrl);
+int ag_drv_lport_led_cntrl_get(uint8_t led_id, lport_led_cntrl *cntrl);
+int ag_drv_lport_led_link_and_speed_encoding_sel_set(uint8_t led_id, const lport_led_link_and_speed_encoding_sel *link_and_speed_encoding_sel);
+int ag_drv_lport_led_link_and_speed_encoding_sel_get(uint8_t led_id, lport_led_link_and_speed_encoding_sel *link_and_speed_encoding_sel);
+int ag_drv_lport_led_link_and_speed_encoding_set(uint8_t led_id, const lport_led_link_and_speed_encoding *link_and_speed_encoding);
+int ag_drv_lport_led_link_and_speed_encoding_get(uint8_t led_id, lport_led_link_and_speed_encoding *link_and_speed_encoding);
+int ag_drv_lport_led_aggregate_led_cntrl_set(uint8_t led_id, uint8_t lnk_pol_sel, uint8_t act_pol_sel, uint8_t act_sel, uint16_t port_en);
+int ag_drv_lport_led_aggregate_led_cntrl_get(uint8_t led_id, uint8_t *lnk_pol_sel, uint8_t *act_pol_sel, uint8_t *act_sel, uint16_t *port_en);
+int ag_drv_lport_led_aggregate_led_blink_rate_cntrl_set(uint8_t led_id, uint16_t led_on_time, uint16_t led_off_time);
+int ag_drv_lport_led_aggregate_led_blink_rate_cntrl_get(uint8_t led_id, uint16_t *led_on_time, uint16_t *led_off_time);
+
+#ifdef USE_BDMF_SHELL
+bdmfmon_handle_t ag_drv_lport_led_cli_init(bdmfmon_handle_t driver_dir);
+#endif
+
+
+#endif
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_mab_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mab_ag.c
new file mode 100644
index 0000000000..39b4219ff5
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mab_ag.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_lport_mab_ag.h"
+#define BLOCK_ADDR_COUNT_BITS 1
+#define BLOCK_ADDR_COUNT (1<<BLOCK_ADDR_COUNT_BITS)
+
+int ag_drv_lport_mab_cntrl_set(uint8_t xlmac_id, const lport_mab_cntrl *cntrl)
+{
+    uint32_t reg_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (cntrl->link_down_rst_en >= _1BITS_MAX_VAL_) ||
+       (cntrl->xgmii_tx_rst >= _1BITS_MAX_VAL_) ||
+       (cntrl->gmii_tx_rst >= _4BITS_MAX_VAL_) ||
+       (cntrl->xgmii_rx_rst >= _1BITS_MAX_VAL_) ||
+       (cntrl->gmii_rx_rst >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_cntrl = RU_FIELD_SET(xlmac_id, LPORT_MAB, CNTRL, LINK_DOWN_RST_EN, reg_cntrl, cntrl->link_down_rst_en);
+    reg_cntrl = RU_FIELD_SET(xlmac_id, LPORT_MAB, CNTRL, XGMII_TX_RST, reg_cntrl, cntrl->xgmii_tx_rst);
+    reg_cntrl = RU_FIELD_SET(xlmac_id, LPORT_MAB, CNTRL, GMII_TX_RST, reg_cntrl, cntrl->gmii_tx_rst);
+    reg_cntrl = RU_FIELD_SET(xlmac_id, LPORT_MAB, CNTRL, XGMII_RX_RST, reg_cntrl, cntrl->xgmii_rx_rst);
+    reg_cntrl = RU_FIELD_SET(xlmac_id, LPORT_MAB, CNTRL, GMII_RX_RST, reg_cntrl, cntrl->gmii_rx_rst);
+
+    RU_REG_WRITE(xlmac_id, LPORT_MAB, CNTRL, reg_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_mab_cntrl_get(uint8_t xlmac_id, lport_mab_cntrl *cntrl)
+{
+    uint32_t reg_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, LPORT_MAB, CNTRL, reg_cntrl);
+
+    cntrl->link_down_rst_en = RU_FIELD_GET(xlmac_id, LPORT_MAB, CNTRL, LINK_DOWN_RST_EN, reg_cntrl);
+    cntrl->xgmii_tx_rst = RU_FIELD_GET(xlmac_id, LPORT_MAB, CNTRL, XGMII_TX_RST, reg_cntrl);
+    cntrl->gmii_tx_rst = RU_FIELD_GET(xlmac_id, LPORT_MAB, CNTRL, GMII_TX_RST, reg_cntrl);
+    cntrl->xgmii_rx_rst = RU_FIELD_GET(xlmac_id, LPORT_MAB, CNTRL, XGMII_RX_RST, reg_cntrl);
+    cntrl->gmii_rx_rst = RU_FIELD_GET(xlmac_id, LPORT_MAB, CNTRL, GMII_RX_RST, reg_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_mab_tx_wrr_ctrl_set(uint8_t xlmac_id, const lport_mab_tx_wrr_ctrl *tx_wrr_ctrl)
+{
+    uint32_t reg_tx_wrr_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_wrr_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (tx_wrr_ctrl->arb_mode >= _1BITS_MAX_VAL_) ||
+       (tx_wrr_ctrl->p7_weight >= _4BITS_MAX_VAL_) ||
+       (tx_wrr_ctrl->p6_weight >= _4BITS_MAX_VAL_) ||
+       (tx_wrr_ctrl->p5_weight >= _4BITS_MAX_VAL_) ||
+       (tx_wrr_ctrl->p4_weight >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_tx_wrr_ctrl = RU_FIELD_SET(xlmac_id, LPORT_MAB, TX_WRR_CTRL, ARB_MODE, reg_tx_wrr_ctrl, tx_wrr_ctrl->arb_mode);
+    reg_tx_wrr_ctrl = RU_FIELD_SET(xlmac_id, LPORT_MAB, TX_WRR_CTRL, P7_WEIGHT, reg_tx_wrr_ctrl, tx_wrr_ctrl->p7_weight);
+    reg_tx_wrr_ctrl = RU_FIELD_SET(xlmac_id, LPORT_MAB, TX_WRR_CTRL, P6_WEIGHT, reg_tx_wrr_ctrl, tx_wrr_ctrl->p6_weight);
+    reg_tx_wrr_ctrl = RU_FIELD_SET(xlmac_id, LPORT_MAB, TX_WRR_CTRL, P5_WEIGHT, reg_tx_wrr_ctrl, tx_wrr_ctrl->p5_weight);
+    reg_tx_wrr_ctrl = RU_FIELD_SET(xlmac_id, LPORT_MAB, TX_WRR_CTRL, P4_WEIGHT, reg_tx_wrr_ctrl, tx_wrr_ctrl->p4_weight);
+
+    RU_REG_WRITE(xlmac_id, LPORT_MAB, TX_WRR_CTRL, reg_tx_wrr_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_mab_tx_wrr_ctrl_get(uint8_t xlmac_id, lport_mab_tx_wrr_ctrl *tx_wrr_ctrl)
+{
+    uint32_t reg_tx_wrr_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_wrr_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, LPORT_MAB, TX_WRR_CTRL, reg_tx_wrr_ctrl);
+
+    tx_wrr_ctrl->arb_mode = RU_FIELD_GET(xlmac_id, LPORT_MAB, TX_WRR_CTRL, ARB_MODE, reg_tx_wrr_ctrl);
+    tx_wrr_ctrl->p7_weight = RU_FIELD_GET(xlmac_id, LPORT_MAB, TX_WRR_CTRL, P7_WEIGHT, reg_tx_wrr_ctrl);
+    tx_wrr_ctrl->p6_weight = RU_FIELD_GET(xlmac_id, LPORT_MAB, TX_WRR_CTRL, P6_WEIGHT, reg_tx_wrr_ctrl);
+    tx_wrr_ctrl->p5_weight = RU_FIELD_GET(xlmac_id, LPORT_MAB, TX_WRR_CTRL, P5_WEIGHT, reg_tx_wrr_ctrl);
+    tx_wrr_ctrl->p4_weight = RU_FIELD_GET(xlmac_id, LPORT_MAB, TX_WRR_CTRL, P4_WEIGHT, reg_tx_wrr_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_mab_tx_threshold_set(uint8_t xlmac_id, const lport_mab_tx_threshold *tx_threshold)
+{
+    uint32_t reg_tx_threshold=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_threshold)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (tx_threshold->xgmii1_tx_threshold >= _4BITS_MAX_VAL_) ||
+       (tx_threshold->gmii7_tx_threshold >= _4BITS_MAX_VAL_) ||
+       (tx_threshold->gmii6_tx_threshold >= _4BITS_MAX_VAL_) ||
+       (tx_threshold->gmii5_tx_threshold >= _4BITS_MAX_VAL_) ||
+       (tx_threshold->gmii4_tx_threshold >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_tx_threshold = RU_FIELD_SET(xlmac_id, LPORT_MAB, TX_THRESHOLD, XGMII1_TX_THRESHOLD, reg_tx_threshold, tx_threshold->xgmii1_tx_threshold);
+    reg_tx_threshold = RU_FIELD_SET(xlmac_id, LPORT_MAB, TX_THRESHOLD, GMII7_TX_THRESHOLD, reg_tx_threshold, tx_threshold->gmii7_tx_threshold);
+    reg_tx_threshold = RU_FIELD_SET(xlmac_id, LPORT_MAB, TX_THRESHOLD, GMII6_TX_THRESHOLD, reg_tx_threshold, tx_threshold->gmii6_tx_threshold);
+    reg_tx_threshold = RU_FIELD_SET(xlmac_id, LPORT_MAB, TX_THRESHOLD, GMII5_TX_THRESHOLD, reg_tx_threshold, tx_threshold->gmii5_tx_threshold);
+    reg_tx_threshold = RU_FIELD_SET(xlmac_id, LPORT_MAB, TX_THRESHOLD, GMII4_TX_THRESHOLD, reg_tx_threshold, tx_threshold->gmii4_tx_threshold);
+
+    RU_REG_WRITE(xlmac_id, LPORT_MAB, TX_THRESHOLD, reg_tx_threshold);
+
+    return 0;
+}
+
+int ag_drv_lport_mab_tx_threshold_get(uint8_t xlmac_id, lport_mab_tx_threshold *tx_threshold)
+{
+    uint32_t reg_tx_threshold=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_threshold)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, LPORT_MAB, TX_THRESHOLD, reg_tx_threshold);
+
+    tx_threshold->xgmii1_tx_threshold = RU_FIELD_GET(xlmac_id, LPORT_MAB, TX_THRESHOLD, XGMII1_TX_THRESHOLD, reg_tx_threshold);
+    tx_threshold->gmii7_tx_threshold = RU_FIELD_GET(xlmac_id, LPORT_MAB, TX_THRESHOLD, GMII7_TX_THRESHOLD, reg_tx_threshold);
+    tx_threshold->gmii6_tx_threshold = RU_FIELD_GET(xlmac_id, LPORT_MAB, TX_THRESHOLD, GMII6_TX_THRESHOLD, reg_tx_threshold);
+    tx_threshold->gmii5_tx_threshold = RU_FIELD_GET(xlmac_id, LPORT_MAB, TX_THRESHOLD, GMII5_TX_THRESHOLD, reg_tx_threshold);
+    tx_threshold->gmii4_tx_threshold = RU_FIELD_GET(xlmac_id, LPORT_MAB, TX_THRESHOLD, GMII4_TX_THRESHOLD, reg_tx_threshold);
+
+    return 0;
+}
+
+int ag_drv_lport_mab_link_down_tx_data_set(uint8_t xlmac_id, uint8_t txctl, uint8_t txd)
+{
+    uint32_t reg_link_down_tx_data=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (txctl >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_link_down_tx_data = RU_FIELD_SET(xlmac_id, LPORT_MAB, LINK_DOWN_TX_DATA, TXCTL, reg_link_down_tx_data, txctl);
+    reg_link_down_tx_data = RU_FIELD_SET(xlmac_id, LPORT_MAB, LINK_DOWN_TX_DATA, TXD, reg_link_down_tx_data, txd);
+
+    RU_REG_WRITE(xlmac_id, LPORT_MAB, LINK_DOWN_TX_DATA, reg_link_down_tx_data);
+
+    return 0;
+}
+
+int ag_drv_lport_mab_link_down_tx_data_get(uint8_t xlmac_id, uint8_t *txctl, uint8_t *txd)
+{
+    uint32_t reg_link_down_tx_data=0;
+
+#ifdef VALIDATE_PARMS
+    if(!txctl || !txd)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, LPORT_MAB, LINK_DOWN_TX_DATA, reg_link_down_tx_data);
+
+    *txctl = RU_FIELD_GET(xlmac_id, LPORT_MAB, LINK_DOWN_TX_DATA, TXCTL, reg_link_down_tx_data);
+    *txd = RU_FIELD_GET(xlmac_id, LPORT_MAB, LINK_DOWN_TX_DATA, TXD, reg_link_down_tx_data);
+
+    return 0;
+}
+
+int ag_drv_lport_mab_status_get(uint8_t xlmac_id, lport_mab_status *status)
+{
+    uint32_t reg_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!status)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, LPORT_MAB, STATUS, reg_status);
+
+    status->xgmii_rx_afifo_overrun = RU_FIELD_GET(xlmac_id, LPORT_MAB, STATUS, XGMII_RX_AFIFO_OVERRUN, reg_status);
+    status->gmii_rx_afifo_overrun_vect = RU_FIELD_GET(xlmac_id, LPORT_MAB, STATUS, GMII_RX_AFIFO_OVERRUN_VECT, reg_status);
+    status->xgmii_tx_frm_underrun = RU_FIELD_GET(xlmac_id, LPORT_MAB, STATUS, XGMII_TX_FRM_UNDERRUN, reg_status);
+    status->xgmii_outstanding_credits_cnt_underrun = RU_FIELD_GET(xlmac_id, LPORT_MAB, STATUS, XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN, reg_status);
+    status->gmii_outstanding_credits_cnt_underrun_vect = RU_FIELD_GET(xlmac_id, LPORT_MAB, STATUS, GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT, reg_status);
+    status->xgmii_tx_afifo_overrun = RU_FIELD_GET(xlmac_id, LPORT_MAB, STATUS, XGMII_TX_AFIFO_OVERRUN, reg_status);
+    status->gmii_tx_afifo_overrun_vect = RU_FIELD_GET(xlmac_id, LPORT_MAB, STATUS, GMII_TX_AFIFO_OVERRUN_VECT, reg_status);
+
+    return 0;
+}
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_mab_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mab_ag.h
new file mode 100644
index 0000000000..2d54794296
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mab_ag.h
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_LPORT_MAB_AG_H_
+#define _BCM6858_LPORT_MAB_AG_H_
+
+#include "access_macros.h"
+#include "bcmtypes.h"
+typedef struct
+{
+    uint8_t link_down_rst_en;
+    uint8_t xgmii_tx_rst;
+    uint8_t gmii_tx_rst;
+    uint8_t xgmii_rx_rst;
+    uint8_t gmii_rx_rst;
+} lport_mab_cntrl;
+
+typedef struct
+{
+    uint8_t arb_mode;
+    uint8_t p7_weight;
+    uint8_t p6_weight;
+    uint8_t p5_weight;
+    uint8_t p4_weight;
+} lport_mab_tx_wrr_ctrl;
+
+typedef struct
+{
+    uint8_t xgmii1_tx_threshold;
+    uint8_t gmii7_tx_threshold;
+    uint8_t gmii6_tx_threshold;
+    uint8_t gmii5_tx_threshold;
+    uint8_t gmii4_tx_threshold;
+} lport_mab_tx_threshold;
+
+typedef struct
+{
+    uint8_t xgmii_rx_afifo_overrun;
+    uint8_t gmii_rx_afifo_overrun_vect;
+    uint8_t xgmii_tx_frm_underrun;
+    uint8_t xgmii_outstanding_credits_cnt_underrun;
+    uint8_t gmii_outstanding_credits_cnt_underrun_vect;
+    uint8_t xgmii_tx_afifo_overrun;
+    uint8_t gmii_tx_afifo_overrun_vect;
+} lport_mab_status;
+
+int ag_drv_lport_mab_cntrl_set(uint8_t xlmac_id, const lport_mab_cntrl *cntrl);
+int ag_drv_lport_mab_cntrl_get(uint8_t xlmac_id, lport_mab_cntrl *cntrl);
+int ag_drv_lport_mab_tx_wrr_ctrl_set(uint8_t xlmac_id, const lport_mab_tx_wrr_ctrl *tx_wrr_ctrl);
+int ag_drv_lport_mab_tx_wrr_ctrl_get(uint8_t xlmac_id, lport_mab_tx_wrr_ctrl *tx_wrr_ctrl);
+int ag_drv_lport_mab_tx_threshold_set(uint8_t xlmac_id, const lport_mab_tx_threshold *tx_threshold);
+int ag_drv_lport_mab_tx_threshold_get(uint8_t xlmac_id, lport_mab_tx_threshold *tx_threshold);
+int ag_drv_lport_mab_link_down_tx_data_set(uint8_t xlmac_id, uint8_t txctl, uint8_t txd);
+int ag_drv_lport_mab_link_down_tx_data_get(uint8_t xlmac_id, uint8_t *txctl, uint8_t *txd);
+int ag_drv_lport_mab_status_get(uint8_t xlmac_id, lport_mab_status *status);
+
+#ifdef USE_BDMF_SHELL
+bdmfmon_handle_t ag_drv_lport_mab_cli_init(bdmfmon_handle_t driver_dir);
+#endif
+
+
+#endif
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_mdio_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mdio_ag.c
new file mode 100644
index 0000000000..bd72b6efd9
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mdio_ag.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_lport_mdio_ag.h"
+int ag_drv_lport_mdio_control_set(const lport_mdio_control *control)
+{
+    uint32_t reg_cmd=0;
+
+#ifdef VALIDATE_PARMS
+    if(!control)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((control->start_busy >= _1BITS_MAX_VAL_) ||
+       (control->fail >= _1BITS_MAX_VAL_) ||
+       (control->op_code >= _2BITS_MAX_VAL_) ||
+       (control->phy_prt_addr >= _5BITS_MAX_VAL_) ||
+       (control->reg_dev_addr >= _5BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_cmd = RU_FIELD_SET(0, LPORT_MDIO, CMD, START_BUSY, reg_cmd, control->start_busy);
+    reg_cmd = RU_FIELD_SET(0, LPORT_MDIO, CMD, FAIL, reg_cmd, control->fail);
+    reg_cmd = RU_FIELD_SET(0, LPORT_MDIO, CMD, OP_CODE, reg_cmd, control->op_code);
+    reg_cmd = RU_FIELD_SET(0, LPORT_MDIO, CMD, PHY_PRT_ADDR, reg_cmd, control->phy_prt_addr);
+    reg_cmd = RU_FIELD_SET(0, LPORT_MDIO, CMD, REG_DEV_ADDR, reg_cmd, control->reg_dev_addr);
+    reg_cmd = RU_FIELD_SET(0, LPORT_MDIO, CMD, DATA_ADDR, reg_cmd, control->data_addr);
+
+    RU_REG_WRITE(0, LPORT_MDIO, CMD, reg_cmd);
+
+    return 0;
+}
+
+int ag_drv_lport_mdio_control_get(lport_mdio_control *control)
+{
+    uint32_t reg_cmd=0;
+
+#ifdef VALIDATE_PARMS
+    if(!control)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_MDIO, CMD, reg_cmd);
+
+    control->start_busy = RU_FIELD_GET(0, LPORT_MDIO, CMD, START_BUSY, reg_cmd);
+    control->fail = RU_FIELD_GET(0, LPORT_MDIO, CMD, FAIL, reg_cmd);
+    control->op_code = RU_FIELD_GET(0, LPORT_MDIO, CMD, OP_CODE, reg_cmd);
+    control->phy_prt_addr = RU_FIELD_GET(0, LPORT_MDIO, CMD, PHY_PRT_ADDR, reg_cmd);
+    control->reg_dev_addr = RU_FIELD_GET(0, LPORT_MDIO, CMD, REG_DEV_ADDR, reg_cmd);
+    control->data_addr = RU_FIELD_GET(0, LPORT_MDIO, CMD, DATA_ADDR, reg_cmd);
+
+    return 0;
+}
+
+int ag_drv_lport_mdio_cfg_set(uint8_t free_run_clk_enable, uint8_t supress_preamble, uint8_t mdio_clk_divider, uint8_t mdio_clause)
+{
+    uint32_t reg_cfg=0;
+
+#ifdef VALIDATE_PARMS
+    if((supress_preamble >= _1BITS_MAX_VAL_) ||
+       (mdio_clause >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_cfg = RU_FIELD_SET(0, LPORT_MDIO, CFG, FREE_RUN_CLK_ENABLE, reg_cfg, free_run_clk_enable);
+    reg_cfg = RU_FIELD_SET(0, LPORT_MDIO, CFG, SUPRESS_PREAMBLE, reg_cfg, supress_preamble);
+    reg_cfg = RU_FIELD_SET(0, LPORT_MDIO, CFG, MDIO_CLK_DIVIDER, reg_cfg, mdio_clk_divider);
+    reg_cfg = RU_FIELD_SET(0, LPORT_MDIO, CFG, MDIO_CLAUSE, reg_cfg, mdio_clause);
+
+    RU_REG_WRITE(0, LPORT_MDIO, CFG, reg_cfg);
+
+    return 0;
+}
+
+int ag_drv_lport_mdio_cfg_get(uint8_t *free_run_clk_enable, uint8_t *supress_preamble, uint8_t *mdio_clk_divider, uint8_t *mdio_clause)
+{
+    uint32_t reg_cfg=0;
+
+#ifdef VALIDATE_PARMS
+    if(!supress_preamble || !mdio_clk_divider || !mdio_clause)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_MDIO, CFG, reg_cfg);
+
+    *free_run_clk_enable = RU_FIELD_GET(0, LPORT_MDIO, CFG, FREE_RUN_CLK_ENABLE, reg_cfg);
+    *supress_preamble = RU_FIELD_GET(0, LPORT_MDIO, CFG, SUPRESS_PREAMBLE, reg_cfg);
+    *mdio_clk_divider = RU_FIELD_GET(0, LPORT_MDIO, CFG, MDIO_CLK_DIVIDER, reg_cfg);
+    *mdio_clause = RU_FIELD_GET(0, LPORT_MDIO, CFG, MDIO_CLAUSE, reg_cfg);
+
+    return 0;
+}
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_mdio_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mdio_ag.h
new file mode 100644
index 0000000000..6e1495b632
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mdio_ag.h
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_LPORT_MDIO_AG_H_
+#define _BCM6858_LPORT_MDIO_AG_H_
+
+#include "access_macros.h"
+#include "bcmtypes.h"
+typedef struct
+{
+    uint8_t start_busy;
+    uint8_t fail;
+    uint8_t op_code;
+    uint8_t phy_prt_addr;
+    uint8_t reg_dev_addr;
+    uint16_t data_addr;
+} lport_mdio_control;
+
+int ag_drv_lport_mdio_control_set(const lport_mdio_control *control);
+int ag_drv_lport_mdio_control_get(lport_mdio_control *control);
+int ag_drv_lport_mdio_cfg_set(uint8_t free_run_clk_enable, uint8_t supress_preamble, uint8_t mdio_clk_divider, uint8_t mdio_clause);
+int ag_drv_lport_mdio_cfg_get(uint8_t *free_run_clk_enable, uint8_t *supress_preamble, uint8_t *mdio_clk_divider, uint8_t *mdio_clause);
+
+#ifdef USE_BDMF_SHELL
+bdmfmon_handle_t ag_drv_lport_mdio_cli_init(bdmfmon_handle_t driver_dir);
+#endif
+
+
+#endif
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_mib_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mib_ag.c
new file mode 100644
index 0000000000..c8cb3fe9bd
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mib_ag.c
@@ -0,0 +1,4807 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_lport_mib_ag.h"
+#include "mib_indirect_access.h"
+
+#define BLOCK_ADDR_COUNT_BITS 3
+#define BLOCK_ADDR_COUNT (1<<BLOCK_ADDR_COUNT_BITS)
+
+int ag_drv_lport_mib_grx64_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grx64=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grx64 = RU_FIELD_SET(port_id, LPORT_MIB, GRX64, COUNT40, reg_grx64, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRX64, reg_grx64);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx64_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grx64=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRX64, reg_grx64);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRX64, COUNT40, reg_grx64);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx127_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grx127=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grx127 = RU_FIELD_SET(port_id, LPORT_MIB, GRX127, COUNT40, reg_grx127, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRX127, reg_grx127);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx127_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grx127=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRX127, reg_grx127);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRX127, COUNT40, reg_grx127);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx255_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grx255=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grx255 = RU_FIELD_SET(port_id, LPORT_MIB, GRX255, COUNT40, reg_grx255, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRX255, reg_grx255);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx255_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grx255=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRX255, reg_grx255);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRX255, COUNT40, reg_grx255);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx511_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grx511=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grx511 = RU_FIELD_SET(port_id, LPORT_MIB, GRX511, COUNT40, reg_grx511, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRX511, reg_grx511);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx511_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grx511=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRX511, reg_grx511);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRX511, COUNT40, reg_grx511);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx1023_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grx1023=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grx1023 = RU_FIELD_SET(port_id, LPORT_MIB, GRX1023, COUNT40, reg_grx1023, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRX1023, reg_grx1023);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx1023_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grx1023=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRX1023, reg_grx1023);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRX1023, COUNT40, reg_grx1023);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx1518_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grx1518=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grx1518 = RU_FIELD_SET(port_id, LPORT_MIB, GRX1518, COUNT40, reg_grx1518, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRX1518, reg_grx1518);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx1518_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grx1518=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRX1518, reg_grx1518);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRX1518, COUNT40, reg_grx1518);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx1522_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grx1522=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grx1522 = RU_FIELD_SET(port_id, LPORT_MIB, GRX1522, COUNT40, reg_grx1522, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRX1522, reg_grx1522);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx1522_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grx1522=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRX1522, reg_grx1522);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRX1522, COUNT40, reg_grx1522);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx2047_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grx2047=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grx2047 = RU_FIELD_SET(port_id, LPORT_MIB, GRX2047, COUNT40, reg_grx2047, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRX2047, reg_grx2047);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx2047_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grx2047=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRX2047, reg_grx2047);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRX2047, COUNT40, reg_grx2047);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx4095_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grx4095=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grx4095 = RU_FIELD_SET(port_id, LPORT_MIB, GRX4095, COUNT40, reg_grx4095, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRX4095, reg_grx4095);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx4095_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grx4095=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRX4095, reg_grx4095);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRX4095, COUNT40, reg_grx4095);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx9216_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grx9216=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grx9216 = RU_FIELD_SET(port_id, LPORT_MIB, GRX9216, COUNT40, reg_grx9216, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRX9216, reg_grx9216);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx9216_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grx9216=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRX9216, reg_grx9216);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRX9216, COUNT40, reg_grx9216);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx16383_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grx16383=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grx16383 = RU_FIELD_SET(port_id, LPORT_MIB, GRX16383, COUNT40, reg_grx16383, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRX16383, reg_grx16383);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grx16383_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grx16383=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRX16383, reg_grx16383);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRX16383, COUNT40, reg_grx16383);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpkt_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpkt=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpkt = RU_FIELD_SET(port_id, LPORT_MIB, GRXPKT, COUNT40, reg_grxpkt, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPKT, reg_grxpkt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpkt_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpkt=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPKT, reg_grxpkt);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPKT, COUNT40, reg_grxpkt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxuca_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxuca=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxuca = RU_FIELD_SET(port_id, LPORT_MIB, GRXUCA, COUNT40, reg_grxuca, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXUCA, reg_grxuca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxuca_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxuca=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXUCA, reg_grxuca);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXUCA, COUNT40, reg_grxuca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxmca_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxmca=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxmca = RU_FIELD_SET(port_id, LPORT_MIB, GRXMCA, COUNT40, reg_grxmca, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXMCA, reg_grxmca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxmca_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxmca=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXMCA, reg_grxmca);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXMCA, COUNT40, reg_grxmca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxbca_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxbca=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxbca = RU_FIELD_SET(port_id, LPORT_MIB, GRXBCA, COUNT40, reg_grxbca, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXBCA, reg_grxbca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxbca_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxbca=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXBCA, reg_grxbca);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXBCA, COUNT40, reg_grxbca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxfcs_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxfcs=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxfcs = RU_FIELD_SET(port_id, LPORT_MIB, GRXFCS, COUNT40, reg_grxfcs, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXFCS, reg_grxfcs);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxfcs_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxfcs=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXFCS, reg_grxfcs);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXFCS, COUNT40, reg_grxfcs);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxcf_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxcf=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxcf = RU_FIELD_SET(port_id, LPORT_MIB, GRXCF, COUNT40, reg_grxcf, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXCF, reg_grxcf);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxcf_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxcf=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXCF, reg_grxcf);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXCF, COUNT40, reg_grxcf);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpf_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpf=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpf = RU_FIELD_SET(port_id, LPORT_MIB, GRXPF, COUNT40, reg_grxpf, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPF, reg_grxpf);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpf_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpf=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPF, reg_grxpf);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPF, COUNT40, reg_grxpf);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpp_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpp=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpp = RU_FIELD_SET(port_id, LPORT_MIB, GRXPP, COUNT40, reg_grxpp, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPP, reg_grxpp);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpp_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpp=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPP, reg_grxpp);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPP, COUNT40, reg_grxpp);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxuo_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxuo=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxuo = RU_FIELD_SET(port_id, LPORT_MIB, GRXUO, COUNT40, reg_grxuo, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXUO, reg_grxuo);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxuo_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxuo=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXUO, reg_grxuo);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXUO, COUNT40, reg_grxuo);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxuda_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxuda=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxuda = RU_FIELD_SET(port_id, LPORT_MIB, GRXUDA, COUNT40, reg_grxuda, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXUDA, reg_grxuda);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxuda_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxuda=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXUDA, reg_grxuda);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXUDA, COUNT40, reg_grxuda);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxwsa_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxwsa=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxwsa = RU_FIELD_SET(port_id, LPORT_MIB, GRXWSA, COUNT40, reg_grxwsa, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXWSA, reg_grxwsa);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxwsa_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxwsa=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXWSA, reg_grxwsa);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXWSA, COUNT40, reg_grxwsa);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxaln_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxaln=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxaln = RU_FIELD_SET(port_id, LPORT_MIB, GRXALN, COUNT40, reg_grxaln, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXALN, reg_grxaln);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxaln_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxaln=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXALN, reg_grxaln);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXALN, COUNT40, reg_grxaln);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxflr_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxflr=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxflr = RU_FIELD_SET(port_id, LPORT_MIB, GRXFLR, COUNT40, reg_grxflr, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXFLR, reg_grxflr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxflr_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxflr=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXFLR, reg_grxflr);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXFLR, COUNT40, reg_grxflr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxfrerr_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxfrerr=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxfrerr = RU_FIELD_SET(port_id, LPORT_MIB, GRXFRERR, COUNT40, reg_grxfrerr, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXFRERR, reg_grxfrerr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxfrerr_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxfrerr=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXFRERR, reg_grxfrerr);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXFRERR, COUNT40, reg_grxfrerr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxfcr_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxfcr=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxfcr = RU_FIELD_SET(port_id, LPORT_MIB, GRXFCR, COUNT40, reg_grxfcr, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXFCR, reg_grxfcr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxfcr_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxfcr=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXFCR, reg_grxfcr);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXFCR, COUNT40, reg_grxfcr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxovr_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxovr=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxovr = RU_FIELD_SET(port_id, LPORT_MIB, GRXOVR, COUNT40, reg_grxovr, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXOVR, reg_grxovr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxovr_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxovr=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXOVR, reg_grxovr);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXOVR, COUNT40, reg_grxovr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxjbr_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxjbr=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxjbr = RU_FIELD_SET(port_id, LPORT_MIB, GRXJBR, COUNT40, reg_grxjbr, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXJBR, reg_grxjbr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxjbr_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxjbr=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXJBR, reg_grxjbr);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXJBR, COUNT40, reg_grxjbr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxmtue_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxmtue=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxmtue = RU_FIELD_SET(port_id, LPORT_MIB, GRXMTUE, COUNT40, reg_grxmtue, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXMTUE, reg_grxmtue);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxmtue_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxmtue=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXMTUE, reg_grxmtue);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXMTUE, COUNT40, reg_grxmtue);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxmcrc_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxmcrc=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxmcrc = RU_FIELD_SET(port_id, LPORT_MIB, GRXMCRC, COUNT40, reg_grxmcrc, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXMCRC, reg_grxmcrc);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxmcrc_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxmcrc=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXMCRC, reg_grxmcrc);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXMCRC, COUNT40, reg_grxmcrc);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxprm_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxprm=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxprm = RU_FIELD_SET(port_id, LPORT_MIB, GRXPRM, COUNT40, reg_grxprm, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPRM, reg_grxprm);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxprm_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxprm=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPRM, reg_grxprm);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPRM, COUNT40, reg_grxprm);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxvln_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxvln=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxvln = RU_FIELD_SET(port_id, LPORT_MIB, GRXVLN, COUNT40, reg_grxvln, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXVLN, reg_grxvln);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxvln_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxvln=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXVLN, reg_grxvln);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXVLN, COUNT40, reg_grxvln);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxdvln_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxdvln=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxdvln = RU_FIELD_SET(port_id, LPORT_MIB, GRXDVLN, COUNT40, reg_grxdvln, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXDVLN, reg_grxdvln);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxdvln_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxdvln=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXDVLN, reg_grxdvln);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXDVLN, COUNT40, reg_grxdvln);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxtrfu_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxtrfu=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxtrfu = RU_FIELD_SET(port_id, LPORT_MIB, GRXTRFU, COUNT40, reg_grxtrfu, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXTRFU, reg_grxtrfu);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxtrfu_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxtrfu=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXTRFU, reg_grxtrfu);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXTRFU, COUNT40, reg_grxtrfu);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpok_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpok=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpok = RU_FIELD_SET(port_id, LPORT_MIB, GRXPOK, COUNT40, reg_grxpok, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPOK, reg_grxpok);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpok_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpok=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPOK, reg_grxpok);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPOK, COUNT40, reg_grxpok);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff0_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcoff0=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcoff0 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCOFF0, COUNT40, reg_grxpfcoff0, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCOFF0, reg_grxpfcoff0);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff0_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcoff0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCOFF0, reg_grxpfcoff0);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCOFF0, COUNT40, reg_grxpfcoff0);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff1_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcoff1=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcoff1 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCOFF1, COUNT40, reg_grxpfcoff1, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCOFF1, reg_grxpfcoff1);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff1_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcoff1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCOFF1, reg_grxpfcoff1);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCOFF1, COUNT40, reg_grxpfcoff1);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff2_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcoff2=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcoff2 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCOFF2, COUNT40, reg_grxpfcoff2, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCOFF2, reg_grxpfcoff2);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff2_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcoff2=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCOFF2, reg_grxpfcoff2);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCOFF2, COUNT40, reg_grxpfcoff2);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff3_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcoff3=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcoff3 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCOFF3, COUNT40, reg_grxpfcoff3, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCOFF3, reg_grxpfcoff3);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff3_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcoff3=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCOFF3, reg_grxpfcoff3);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCOFF3, COUNT40, reg_grxpfcoff3);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff4_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcoff4=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcoff4 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCOFF4, COUNT40, reg_grxpfcoff4, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCOFF4, reg_grxpfcoff4);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff4_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcoff4=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCOFF4, reg_grxpfcoff4);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCOFF4, COUNT40, reg_grxpfcoff4);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff5_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcoff5=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcoff5 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCOFF5, COUNT40, reg_grxpfcoff5, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCOFF5, reg_grxpfcoff5);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff5_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcoff5=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCOFF5, reg_grxpfcoff5);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCOFF5, COUNT40, reg_grxpfcoff5);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff6_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcoff6=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcoff6 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCOFF6, COUNT40, reg_grxpfcoff6, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCOFF6, reg_grxpfcoff6);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff6_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcoff6=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCOFF6, reg_grxpfcoff6);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCOFF6, COUNT40, reg_grxpfcoff6);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff7_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcoff7=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcoff7 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCOFF7, COUNT40, reg_grxpfcoff7, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCOFF7, reg_grxpfcoff7);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcoff7_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcoff7=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCOFF7, reg_grxpfcoff7);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCOFF7, COUNT40, reg_grxpfcoff7);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp0_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcp0=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcp0 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCP0, COUNT40, reg_grxpfcp0, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCP0, reg_grxpfcp0);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp0_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcp0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCP0, reg_grxpfcp0);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCP0, COUNT40, reg_grxpfcp0);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp1_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcp1=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcp1 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCP1, COUNT40, reg_grxpfcp1, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCP1, reg_grxpfcp1);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp1_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcp1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCP1, reg_grxpfcp1);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCP1, COUNT40, reg_grxpfcp1);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp2_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcp2=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcp2 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCP2, COUNT40, reg_grxpfcp2, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCP2, reg_grxpfcp2);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp2_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcp2=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCP2, reg_grxpfcp2);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCP2, COUNT40, reg_grxpfcp2);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp3_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcp3=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcp3 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCP3, COUNT40, reg_grxpfcp3, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCP3, reg_grxpfcp3);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp3_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcp3=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCP3, reg_grxpfcp3);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCP3, COUNT40, reg_grxpfcp3);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp4_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcp4=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcp4 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCP4, COUNT40, reg_grxpfcp4, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCP4, reg_grxpfcp4);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp4_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcp4=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCP4, reg_grxpfcp4);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCP4, COUNT40, reg_grxpfcp4);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp5_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcp5=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcp5 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCP5, COUNT40, reg_grxpfcp5, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCP5, reg_grxpfcp5);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp5_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcp5=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCP5, reg_grxpfcp5);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCP5, COUNT40, reg_grxpfcp5);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp6_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcp6=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcp6 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCP6, COUNT40, reg_grxpfcp6, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCP6, reg_grxpfcp6);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp6_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcp6=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCP6, reg_grxpfcp6);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCP6, COUNT40, reg_grxpfcp6);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp7_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxpfcp7=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxpfcp7 = RU_FIELD_SET(port_id, LPORT_MIB, GRXPFCP7, COUNT40, reg_grxpfcp7, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPFCP7, reg_grxpfcp7);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxpfcp7_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxpfcp7=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPFCP7, reg_grxpfcp7);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPFCP7, COUNT40, reg_grxpfcp7);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxschcrc_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxschcrc=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxschcrc = RU_FIELD_SET(port_id, LPORT_MIB, GRXSCHCRC, COUNT40, reg_grxschcrc, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXSCHCRC, reg_grxschcrc);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxschcrc_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxschcrc=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXSCHCRC, reg_grxschcrc);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXSCHCRC, COUNT40, reg_grxschcrc);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxbyt_set(uint8_t port_id, uint64_t count48)
+{
+    uint64_t reg_grxbyt=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count48 >= _48BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxbyt = RU_FIELD_SET(port_id, LPORT_MIB, GRXBYT, COUNT48, reg_grxbyt, (uint64_t)count48);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXBYT, reg_grxbyt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxbyt_get(uint8_t port_id, uint64_t *count48)
+{
+    uint64_t reg_grxbyt=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count48)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXBYT, reg_grxbyt);
+
+    *count48 = RU_FIELD_GET(port_id, LPORT_MIB, GRXBYT, COUNT48, reg_grxbyt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxrpkt_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxrpkt=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxrpkt = RU_FIELD_SET(port_id, LPORT_MIB, GRXRPKT, COUNT40, reg_grxrpkt, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXRPKT, reg_grxrpkt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxrpkt_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxrpkt=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXRPKT, reg_grxrpkt);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXRPKT, COUNT40, reg_grxrpkt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxund_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxund=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxund = RU_FIELD_SET(port_id, LPORT_MIB, GRXUND, COUNT40, reg_grxund, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXUND, reg_grxund);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxund_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxund=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXUND, reg_grxund);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXUND, COUNT40, reg_grxund);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxfrg_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxfrg=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxfrg = RU_FIELD_SET(port_id, LPORT_MIB, GRXFRG, COUNT40, reg_grxfrg, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXFRG, reg_grxfrg);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxfrg_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxfrg=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXFRG, reg_grxfrg);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXFRG, COUNT40, reg_grxfrg);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxrbyt_set(uint8_t port_id, uint64_t count48)
+{
+    uint64_t reg_grxrbyt=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count48 >= _48BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxrbyt = RU_FIELD_SET(port_id, LPORT_MIB, GRXRBYT, COUNT48, reg_grxrbyt, (uint64_t)count48);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXRBYT, reg_grxrbyt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxrbyt_get(uint8_t port_id, uint64_t *count48)
+{
+    uint64_t reg_grxrbyt=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count48)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXRBYT, reg_grxrbyt);
+
+    *count48 = RU_FIELD_GET(port_id, LPORT_MIB, GRXRBYT, COUNT48, reg_grxrbyt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx64_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtx64=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtx64 = RU_FIELD_SET(port_id, LPORT_MIB, GTX64, COUNT40, reg_gtx64, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTX64, reg_gtx64);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx64_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtx64=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTX64, reg_gtx64);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTX64, COUNT40, reg_gtx64);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx127_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtx127=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtx127 = RU_FIELD_SET(port_id, LPORT_MIB, GTX127, COUNT40, reg_gtx127, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTX127, reg_gtx127);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx127_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtx127=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTX127, reg_gtx127);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTX127, COUNT40, reg_gtx127);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx255_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtx255=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtx255 = RU_FIELD_SET(port_id, LPORT_MIB, GTX255, COUNT40, reg_gtx255, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTX255, reg_gtx255);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx255_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtx255=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTX255, reg_gtx255);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTX255, COUNT40, reg_gtx255);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx511_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtx511=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtx511 = RU_FIELD_SET(port_id, LPORT_MIB, GTX511, COUNT40, reg_gtx511, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTX511, reg_gtx511);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx511_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtx511=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTX511, reg_gtx511);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTX511, COUNT40, reg_gtx511);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx1023_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtx1023=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtx1023 = RU_FIELD_SET(port_id, LPORT_MIB, GTX1023, COUNT40, reg_gtx1023, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTX1023, reg_gtx1023);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx1023_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtx1023=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTX1023, reg_gtx1023);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTX1023, COUNT40, reg_gtx1023);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx1518_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtx1518=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtx1518 = RU_FIELD_SET(port_id, LPORT_MIB, GTX1518, COUNT40, reg_gtx1518, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTX1518, reg_gtx1518);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx1518_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtx1518=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTX1518, reg_gtx1518);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTX1518, COUNT40, reg_gtx1518);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx1522_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtx1522=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtx1522 = RU_FIELD_SET(port_id, LPORT_MIB, GTX1522, COUNT40, reg_gtx1522, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTX1522, reg_gtx1522);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx1522_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtx1522=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTX1522, reg_gtx1522);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTX1522, COUNT40, reg_gtx1522);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx2047_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtx2047=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtx2047 = RU_FIELD_SET(port_id, LPORT_MIB, GTX2047, COUNT40, reg_gtx2047, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTX2047, reg_gtx2047);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx2047_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtx2047=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTX2047, reg_gtx2047);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTX2047, COUNT40, reg_gtx2047);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx4095_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtx4095=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtx4095 = RU_FIELD_SET(port_id, LPORT_MIB, GTX4095, COUNT40, reg_gtx4095, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTX4095, reg_gtx4095);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx4095_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtx4095=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTX4095, reg_gtx4095);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTX4095, COUNT40, reg_gtx4095);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx9216_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtx9216=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtx9216 = RU_FIELD_SET(port_id, LPORT_MIB, GTX9216, COUNT40, reg_gtx9216, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTX9216, reg_gtx9216);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx9216_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtx9216=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTX9216, reg_gtx9216);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTX9216, COUNT40, reg_gtx9216);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx16383_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtx16383=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtx16383 = RU_FIELD_SET(port_id, LPORT_MIB, GTX16383, COUNT40, reg_gtx16383, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTX16383, reg_gtx16383);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtx16383_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtx16383=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTX16383, reg_gtx16383);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTX16383, COUNT40, reg_gtx16383);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpok_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpok=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpok = RU_FIELD_SET(port_id, LPORT_MIB, GTXPOK, COUNT40, reg_gtxpok, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPOK, reg_gtxpok);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpok_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpok=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPOK, reg_gtxpok);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPOK, COUNT40, reg_gtxpok);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpkt_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpkt=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpkt = RU_FIELD_SET(port_id, LPORT_MIB, GTXPKT, COUNT40, reg_gtxpkt, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPKT, reg_gtxpkt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpkt_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpkt=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPKT, reg_gtxpkt);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPKT, COUNT40, reg_gtxpkt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxuca_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxuca=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxuca = RU_FIELD_SET(port_id, LPORT_MIB, GTXUCA, COUNT40, reg_gtxuca, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXUCA, reg_gtxuca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxuca_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxuca=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXUCA, reg_gtxuca);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXUCA, COUNT40, reg_gtxuca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxmca_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxmca=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxmca = RU_FIELD_SET(port_id, LPORT_MIB, GTXMCA, COUNT40, reg_gtxmca, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXMCA, reg_gtxmca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxmca_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxmca=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXMCA, reg_gtxmca);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXMCA, COUNT40, reg_gtxmca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxbca_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxbca=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxbca = RU_FIELD_SET(port_id, LPORT_MIB, GTXBCA, COUNT40, reg_gtxbca, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXBCA, reg_gtxbca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxbca_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxbca=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXBCA, reg_gtxbca);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXBCA, COUNT40, reg_gtxbca);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpf_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpf=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpf = RU_FIELD_SET(port_id, LPORT_MIB, GTXPF, COUNT40, reg_gtxpf, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPF, reg_gtxpf);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpf_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpf=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPF, reg_gtxpf);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPF, COUNT40, reg_gtxpf);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfc_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpfc=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpfc = RU_FIELD_SET(port_id, LPORT_MIB, GTXPFC, COUNT40, reg_gtxpfc, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPFC, reg_gtxpfc);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfc_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpfc=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPFC, reg_gtxpfc);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPFC, COUNT40, reg_gtxpfc);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxjbr_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxjbr=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxjbr = RU_FIELD_SET(port_id, LPORT_MIB, GTXJBR, COUNT40, reg_gtxjbr, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXJBR, reg_gtxjbr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxjbr_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxjbr=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXJBR, reg_gtxjbr);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXJBR, COUNT40, reg_gtxjbr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxfcs_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxfcs=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxfcs = RU_FIELD_SET(port_id, LPORT_MIB, GTXFCS, COUNT40, reg_gtxfcs, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXFCS, reg_gtxfcs);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxfcs_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxfcs=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXFCS, reg_gtxfcs);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXFCS, COUNT40, reg_gtxfcs);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxcf_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxcf=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxcf = RU_FIELD_SET(port_id, LPORT_MIB, GTXCF, COUNT40, reg_gtxcf, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXCF, reg_gtxcf);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxcf_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxcf=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXCF, reg_gtxcf);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXCF, COUNT40, reg_gtxcf);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxovr_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxovr=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxovr = RU_FIELD_SET(port_id, LPORT_MIB, GTXOVR, COUNT40, reg_gtxovr, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXOVR, reg_gtxovr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxovr_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxovr=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXOVR, reg_gtxovr);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXOVR, COUNT40, reg_gtxovr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxdfr_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxdfr=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxdfr = RU_FIELD_SET(port_id, LPORT_MIB, GTXDFR, COUNT40, reg_gtxdfr, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXDFR, reg_gtxdfr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxdfr_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxdfr=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXDFR, reg_gtxdfr);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXDFR, COUNT40, reg_gtxdfr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxedf_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxedf=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxedf = RU_FIELD_SET(port_id, LPORT_MIB, GTXEDF, COUNT40, reg_gtxedf, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXEDF, reg_gtxedf);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxedf_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxedf=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXEDF, reg_gtxedf);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXEDF, COUNT40, reg_gtxedf);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxscl_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxscl=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxscl = RU_FIELD_SET(port_id, LPORT_MIB, GTXSCL, COUNT40, reg_gtxscl, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXSCL, reg_gtxscl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxscl_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxscl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXSCL, reg_gtxscl);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXSCL, COUNT40, reg_gtxscl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxmcl_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxmcl=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxmcl = RU_FIELD_SET(port_id, LPORT_MIB, GTXMCL, COUNT40, reg_gtxmcl, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXMCL, reg_gtxmcl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxmcl_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxmcl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXMCL, reg_gtxmcl);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXMCL, COUNT40, reg_gtxmcl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxlcl_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxlcl=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxlcl = RU_FIELD_SET(port_id, LPORT_MIB, GTXLCL, COUNT40, reg_gtxlcl, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXLCL, reg_gtxlcl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxlcl_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxlcl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXLCL, reg_gtxlcl);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXLCL, COUNT40, reg_gtxlcl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxxcl_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxxcl=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxxcl = RU_FIELD_SET(port_id, LPORT_MIB, GTXXCL, COUNT40, reg_gtxxcl, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXXCL, reg_gtxxcl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxxcl_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxxcl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXXCL, reg_gtxxcl);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXXCL, COUNT40, reg_gtxxcl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxfrg_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxfrg=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxfrg = RU_FIELD_SET(port_id, LPORT_MIB, GTXFRG, COUNT40, reg_gtxfrg, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXFRG, reg_gtxfrg);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxfrg_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxfrg=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXFRG, reg_gtxfrg);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXFRG, COUNT40, reg_gtxfrg);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxerr_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxerr=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxerr = RU_FIELD_SET(port_id, LPORT_MIB, GTXERR, COUNT40, reg_gtxerr, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXERR, reg_gtxerr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxerr_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxerr=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXERR, reg_gtxerr);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXERR, COUNT40, reg_gtxerr);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxvln_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxvln=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxvln = RU_FIELD_SET(port_id, LPORT_MIB, GTXVLN, COUNT40, reg_gtxvln, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXVLN, reg_gtxvln);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxvln_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxvln=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXVLN, reg_gtxvln);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXVLN, COUNT40, reg_gtxvln);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxdvln_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxdvln=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxdvln = RU_FIELD_SET(port_id, LPORT_MIB, GTXDVLN, COUNT40, reg_gtxdvln, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXDVLN, reg_gtxdvln);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxdvln_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxdvln=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXDVLN, reg_gtxdvln);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXDVLN, COUNT40, reg_gtxdvln);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxrpkt_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxrpkt=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxrpkt = RU_FIELD_SET(port_id, LPORT_MIB, GTXRPKT, COUNT40, reg_gtxrpkt, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXRPKT, reg_gtxrpkt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxrpkt_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxrpkt=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXRPKT, reg_gtxrpkt);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXRPKT, COUNT40, reg_gtxrpkt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxufl_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxufl=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxufl = RU_FIELD_SET(port_id, LPORT_MIB, GTXUFL, COUNT40, reg_gtxufl, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXUFL, reg_gtxufl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxufl_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxufl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXUFL, reg_gtxufl);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXUFL, COUNT40, reg_gtxufl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp0_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpfcp0=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpfcp0 = RU_FIELD_SET(port_id, LPORT_MIB, GTXPFCP0, COUNT40, reg_gtxpfcp0, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPFCP0, reg_gtxpfcp0);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp0_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpfcp0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPFCP0, reg_gtxpfcp0);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPFCP0, COUNT40, reg_gtxpfcp0);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp1_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpfcp1=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpfcp1 = RU_FIELD_SET(port_id, LPORT_MIB, GTXPFCP1, COUNT40, reg_gtxpfcp1, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPFCP1, reg_gtxpfcp1);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp1_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpfcp1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPFCP1, reg_gtxpfcp1);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPFCP1, COUNT40, reg_gtxpfcp1);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp2_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpfcp2=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpfcp2 = RU_FIELD_SET(port_id, LPORT_MIB, GTXPFCP2, COUNT40, reg_gtxpfcp2, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPFCP2, reg_gtxpfcp2);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp2_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpfcp2=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPFCP2, reg_gtxpfcp2);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPFCP2, COUNT40, reg_gtxpfcp2);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp3_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpfcp3=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpfcp3 = RU_FIELD_SET(port_id, LPORT_MIB, GTXPFCP3, COUNT40, reg_gtxpfcp3, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPFCP3, reg_gtxpfcp3);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp3_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpfcp3=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPFCP3, reg_gtxpfcp3);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPFCP3, COUNT40, reg_gtxpfcp3);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp4_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpfcp4=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpfcp4 = RU_FIELD_SET(port_id, LPORT_MIB, GTXPFCP4, COUNT40, reg_gtxpfcp4, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPFCP4, reg_gtxpfcp4);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp4_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpfcp4=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPFCP4, reg_gtxpfcp4);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPFCP4, COUNT40, reg_gtxpfcp4);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp5_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpfcp5=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpfcp5 = RU_FIELD_SET(port_id, LPORT_MIB, GTXPFCP5, COUNT40, reg_gtxpfcp5, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPFCP5, reg_gtxpfcp5);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp5_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpfcp5=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPFCP5, reg_gtxpfcp5);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPFCP5, COUNT40, reg_gtxpfcp5);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp6_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpfcp6=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpfcp6 = RU_FIELD_SET(port_id, LPORT_MIB, GTXPFCP6, COUNT40, reg_gtxpfcp6, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPFCP6, reg_gtxpfcp6);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp6_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpfcp6=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPFCP6, reg_gtxpfcp6);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPFCP6, COUNT40, reg_gtxpfcp6);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp7_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxpfcp7=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxpfcp7 = RU_FIELD_SET(port_id, LPORT_MIB, GTXPFCP7, COUNT40, reg_gtxpfcp7, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXPFCP7, reg_gtxpfcp7);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxpfcp7_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxpfcp7=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXPFCP7, reg_gtxpfcp7);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXPFCP7, COUNT40, reg_gtxpfcp7);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxncl_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxncl=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxncl = RU_FIELD_SET(port_id, LPORT_MIB, GTXNCL, COUNT40, reg_gtxncl, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXNCL, reg_gtxncl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxncl_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxncl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXNCL, reg_gtxncl);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXNCL, COUNT40, reg_gtxncl);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxbyt_set(uint8_t port_id, uint64_t count48)
+{
+    uint64_t reg_gtxbyt=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count48 >= _48BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxbyt = RU_FIELD_SET(port_id, LPORT_MIB, GTXBYT, COUNT48, reg_gtxbyt, (uint64_t)count48);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXBYT, reg_gtxbyt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxbyt_get(uint8_t port_id, uint64_t *count48)
+{
+    uint64_t reg_gtxbyt=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count48)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXBYT, reg_gtxbyt);
+
+    *count48 = RU_FIELD_GET(port_id, LPORT_MIB, GTXBYT, COUNT48, reg_gtxbyt);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxlpi_set(uint8_t port_id, uint32_t count32)
+{
+    uint64_t reg_grxlpi=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxlpi = RU_FIELD_SET(port_id, LPORT_MIB, GRXLPI, COUNT32, reg_grxlpi, (uint64_t)count32);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXLPI, reg_grxlpi);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxlpi_get(uint8_t port_id, uint32_t *count32)
+{
+    uint64_t reg_grxlpi=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count32)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXLPI, reg_grxlpi);
+
+    *count32 = RU_FIELD_GET(port_id, LPORT_MIB, GRXLPI, COUNT32, reg_grxlpi);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxdlpi_set(uint8_t port_id, uint32_t count32)
+{
+    uint64_t reg_grxdlpi=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxdlpi = RU_FIELD_SET(port_id, LPORT_MIB, GRXDLPI, COUNT32, reg_grxdlpi, (uint64_t)count32);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXDLPI, reg_grxdlpi);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxdlpi_get(uint8_t port_id, uint32_t *count32)
+{
+    uint64_t reg_grxdlpi=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count32)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXDLPI, reg_grxdlpi);
+
+    *count32 = RU_FIELD_GET(port_id, LPORT_MIB, GRXDLPI, COUNT32, reg_grxdlpi);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxlpi_set(uint8_t port_id, uint32_t count32)
+{
+    uint64_t reg_gtxlpi=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxlpi = RU_FIELD_SET(port_id, LPORT_MIB, GTXLPI, COUNT32, reg_gtxlpi, (uint64_t)count32);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXLPI, reg_gtxlpi);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxlpi_get(uint8_t port_id, uint32_t *count32)
+{
+    uint64_t reg_gtxlpi=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count32)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXLPI, reg_gtxlpi);
+
+    *count32 = RU_FIELD_GET(port_id, LPORT_MIB, GTXLPI, COUNT32, reg_gtxlpi);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxdlpi_set(uint8_t port_id, uint32_t count32)
+{
+    uint64_t reg_gtxdlpi=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxdlpi = RU_FIELD_SET(port_id, LPORT_MIB, GTXDLPI, COUNT32, reg_gtxdlpi, (uint64_t)count32);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXDLPI, reg_gtxdlpi);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxdlpi_get(uint8_t port_id, uint32_t *count32)
+{
+    uint64_t reg_gtxdlpi=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count32)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXDLPI, reg_gtxdlpi);
+
+    *count32 = RU_FIELD_GET(port_id, LPORT_MIB, GTXDLPI, COUNT32, reg_gtxdlpi);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxptllfc_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxptllfc=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxptllfc = RU_FIELD_SET(port_id, LPORT_MIB, GRXPTLLFC, COUNT40, reg_grxptllfc, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXPTLLFC, reg_grxptllfc);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxptllfc_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxptllfc=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXPTLLFC, reg_grxptllfc);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXPTLLFC, COUNT40, reg_grxptllfc);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxltllfc_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxltllfc=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxltllfc = RU_FIELD_SET(port_id, LPORT_MIB, GRXLTLLFC, COUNT40, reg_grxltllfc, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXLTLLFC, reg_grxltllfc);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxltllfc_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxltllfc=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXLTLLFC, reg_grxltllfc);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXLTLLFC, COUNT40, reg_grxltllfc);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxllfcfcs_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_grxllfcfcs=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_grxllfcfcs = RU_FIELD_SET(port_id, LPORT_MIB, GRXLLFCFCS, COUNT40, reg_grxllfcfcs, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GRXLLFCFCS, reg_grxllfcfcs);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_grxllfcfcs_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_grxllfcfcs=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GRXLLFCFCS, reg_grxllfcfcs);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GRXLLFCFCS, COUNT40, reg_grxllfcfcs);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxltllfc_set(uint8_t port_id, uint64_t count40)
+{
+    uint64_t reg_gtxltllfc=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (count40 >= _40BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gtxltllfc = RU_FIELD_SET(port_id, LPORT_MIB, GTXLTLLFC, COUNT40, reg_gtxltllfc, (uint64_t)count40);
+
+    MIB_INDIRECT_WRITE(port_id, LPORT_MIB, GTXLTLLFC, reg_gtxltllfc);
+
+    return 0;
+}
+
+int ag_drv_lport_mib_gtxltllfc_get(uint8_t port_id, uint64_t *count40)
+{
+    uint64_t reg_gtxltllfc=0;
+
+#ifdef VALIDATE_PARMS
+    if(!count40)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    MIB_INDIRECT_READ(port_id, LPORT_MIB, GTXLTLLFC, reg_gtxltllfc);
+
+    *count40 = RU_FIELD_GET(port_id, LPORT_MIB, GTXLTLLFC, COUNT40, reg_gtxltllfc);
+
+    return 0;
+}
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_mib_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mib_ag.h
new file mode 100644
index 0000000000..45ef01f902
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_mib_ag.h
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_LPORT_MIB_AG_H_
+#define _BCM6858_LPORT_MIB_AG_H_
+
+#include "access_macros.h"
+#include "bcmtypes.h"
+int ag_drv_lport_mib_grx64_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grx64_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grx127_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grx127_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grx255_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grx255_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grx511_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grx511_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grx1023_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grx1023_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grx1518_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grx1518_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grx1522_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grx1522_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grx2047_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grx2047_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grx4095_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grx4095_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grx9216_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grx9216_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grx16383_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grx16383_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpkt_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpkt_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxuca_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxuca_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxmca_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxmca_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxbca_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxbca_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxfcs_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxfcs_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxcf_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxcf_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpf_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpf_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpp_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpp_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxuo_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxuo_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxuda_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxuda_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxwsa_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxwsa_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxaln_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxaln_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxflr_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxflr_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxfrerr_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxfrerr_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxfcr_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxfcr_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxovr_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxovr_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxjbr_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxjbr_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxmtue_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxmtue_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxmcrc_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxmcrc_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxprm_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxprm_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxvln_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxvln_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxdvln_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxdvln_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxtrfu_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxtrfu_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpok_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpok_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcoff0_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcoff0_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcoff1_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcoff1_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcoff2_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcoff2_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcoff3_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcoff3_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcoff4_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcoff4_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcoff5_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcoff5_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcoff6_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcoff6_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcoff7_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcoff7_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcp0_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcp0_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcp1_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcp1_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcp2_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcp2_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcp3_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcp3_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcp4_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcp4_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcp5_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcp5_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcp6_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcp6_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxpfcp7_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxpfcp7_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxschcrc_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxschcrc_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxbyt_set(uint8_t port_id, uint64_t count48);
+int ag_drv_lport_mib_grxbyt_get(uint8_t port_id, uint64_t *count48);
+int ag_drv_lport_mib_grxrpkt_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxrpkt_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxund_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxund_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxfrg_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxfrg_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxrbyt_set(uint8_t port_id, uint64_t count48);
+int ag_drv_lport_mib_grxrbyt_get(uint8_t port_id, uint64_t *count48);
+int ag_drv_lport_mib_gtx64_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtx64_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtx127_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtx127_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtx255_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtx255_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtx511_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtx511_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtx1023_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtx1023_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtx1518_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtx1518_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtx1522_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtx1522_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtx2047_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtx2047_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtx4095_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtx4095_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtx9216_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtx9216_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtx16383_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtx16383_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpok_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpok_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpkt_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpkt_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxuca_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxuca_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxmca_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxmca_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxbca_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxbca_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpf_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpf_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpfc_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpfc_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxjbr_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxjbr_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxfcs_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxfcs_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxcf_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxcf_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxovr_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxovr_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxdfr_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxdfr_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxedf_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxedf_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxscl_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxscl_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxmcl_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxmcl_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxlcl_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxlcl_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxxcl_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxxcl_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxfrg_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxfrg_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxerr_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxerr_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxvln_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxvln_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxdvln_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxdvln_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxrpkt_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxrpkt_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxufl_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxufl_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpfcp0_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpfcp0_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpfcp1_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpfcp1_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpfcp2_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpfcp2_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpfcp3_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpfcp3_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpfcp4_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpfcp4_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpfcp5_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpfcp5_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpfcp6_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpfcp6_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxpfcp7_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxpfcp7_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxncl_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxncl_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxbyt_set(uint8_t port_id, uint64_t count48);
+int ag_drv_lport_mib_gtxbyt_get(uint8_t port_id, uint64_t *count48);
+int ag_drv_lport_mib_grxlpi_set(uint8_t port_id, uint32_t count32);
+int ag_drv_lport_mib_grxlpi_get(uint8_t port_id, uint32_t *count32);
+int ag_drv_lport_mib_grxdlpi_set(uint8_t port_id, uint32_t count32);
+int ag_drv_lport_mib_grxdlpi_get(uint8_t port_id, uint32_t *count32);
+int ag_drv_lport_mib_gtxlpi_set(uint8_t port_id, uint32_t count32);
+int ag_drv_lport_mib_gtxlpi_get(uint8_t port_id, uint32_t *count32);
+int ag_drv_lport_mib_gtxdlpi_set(uint8_t port_id, uint32_t count32);
+int ag_drv_lport_mib_gtxdlpi_get(uint8_t port_id, uint32_t *count32);
+int ag_drv_lport_mib_grxptllfc_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxptllfc_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxltllfc_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxltllfc_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_grxllfcfcs_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_grxllfcfcs_get(uint8_t port_id, uint64_t *count40);
+int ag_drv_lport_mib_gtxltllfc_set(uint8_t port_id, uint64_t count40);
+int ag_drv_lport_mib_gtxltllfc_get(uint8_t port_id, uint64_t *count40);
+
+#ifdef USE_BDMF_SHELL
+bdmfmon_handle_t ag_drv_lport_mib_cli_init(bdmfmon_handle_t driver_dir);
+#endif
+
+
+#endif
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_rgmii_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_lport_rgmii_ag.c
new file mode 100644
index 0000000000..0a653c9fdb
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_rgmii_ag.c
@@ -0,0 +1,909 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_lport_rgmii_ag.h"
+#define BLOCK_ADDR_COUNT_BITS 2
+#define BLOCK_ADDR_COUNT (1<<BLOCK_ADDR_COUNT_BITS)
+
+int ag_drv_lport_rgmii_cntrl_set(uint8_t rgmii_id, const lport_rgmii_cntrl *cntrl)
+{
+    uint32_t reg_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (cntrl->col_crs_mask >= _1BITS_MAX_VAL_) ||
+       (cntrl->rx_err_mask >= _1BITS_MAX_VAL_) ||
+       (cntrl->lpi_count >= _5BITS_MAX_VAL_) ||
+       (cntrl->tx_clk_stop_en >= _1BITS_MAX_VAL_) ||
+       (cntrl->tx_pause_en >= _1BITS_MAX_VAL_) ||
+       (cntrl->rx_pause_en >= _1BITS_MAX_VAL_) ||
+       (cntrl->rvmii_ref_sel >= _1BITS_MAX_VAL_) ||
+       (cntrl->port_mode >= _3BITS_MAX_VAL_) ||
+       (cntrl->id_mode_dis >= _1BITS_MAX_VAL_) ||
+       (cntrl->rgmii_mode_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, CNTRL, COL_CRS_MASK, reg_cntrl, cntrl->col_crs_mask);
+    reg_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, CNTRL, RX_ERR_MASK, reg_cntrl, cntrl->rx_err_mask);
+    reg_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, CNTRL, LPI_COUNT, reg_cntrl, cntrl->lpi_count);
+    reg_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, CNTRL, TX_CLK_STOP_EN, reg_cntrl, cntrl->tx_clk_stop_en);
+    reg_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, CNTRL, TX_PAUSE_EN, reg_cntrl, cntrl->tx_pause_en);
+    reg_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, CNTRL, RX_PAUSE_EN, reg_cntrl, cntrl->rx_pause_en);
+    reg_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, CNTRL, RVMII_REF_SEL, reg_cntrl, cntrl->rvmii_ref_sel);
+    reg_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, CNTRL, PORT_MODE, reg_cntrl, cntrl->port_mode);
+    reg_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, CNTRL, ID_MODE_DIS, reg_cntrl, cntrl->id_mode_dis);
+    reg_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, CNTRL, RGMII_MODE_EN, reg_cntrl, cntrl->rgmii_mode_en);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, CNTRL, reg_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_cntrl_get(uint8_t rgmii_id, lport_rgmii_cntrl *cntrl)
+{
+    uint32_t reg_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, CNTRL, reg_cntrl);
+
+    cntrl->col_crs_mask = RU_FIELD_GET(rgmii_id, LPORT_RGMII, CNTRL, COL_CRS_MASK, reg_cntrl);
+    cntrl->rx_err_mask = RU_FIELD_GET(rgmii_id, LPORT_RGMII, CNTRL, RX_ERR_MASK, reg_cntrl);
+    cntrl->lpi_count = RU_FIELD_GET(rgmii_id, LPORT_RGMII, CNTRL, LPI_COUNT, reg_cntrl);
+    cntrl->tx_clk_stop_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, CNTRL, TX_CLK_STOP_EN, reg_cntrl);
+    cntrl->tx_pause_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, CNTRL, TX_PAUSE_EN, reg_cntrl);
+    cntrl->rx_pause_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, CNTRL, RX_PAUSE_EN, reg_cntrl);
+    cntrl->rvmii_ref_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, CNTRL, RVMII_REF_SEL, reg_cntrl);
+    cntrl->port_mode = RU_FIELD_GET(rgmii_id, LPORT_RGMII, CNTRL, PORT_MODE, reg_cntrl);
+    cntrl->id_mode_dis = RU_FIELD_GET(rgmii_id, LPORT_RGMII, CNTRL, ID_MODE_DIS, reg_cntrl);
+    cntrl->rgmii_mode_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, CNTRL, RGMII_MODE_EN, reg_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ib_status_set(uint8_t rgmii_id, uint8_t ib_status_ovrd, uint8_t link_decode, uint8_t duplex_decode, uint8_t speed_decode)
+{
+    uint32_t reg_ib_status=0;
+
+#ifdef VALIDATE_PARMS
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (ib_status_ovrd >= _1BITS_MAX_VAL_) ||
+       (link_decode >= _1BITS_MAX_VAL_) ||
+       (duplex_decode >= _1BITS_MAX_VAL_) ||
+       (speed_decode >= _2BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ib_status = RU_FIELD_SET(rgmii_id, LPORT_RGMII, IB_STATUS, IB_STATUS_OVRD, reg_ib_status, ib_status_ovrd);
+    reg_ib_status = RU_FIELD_SET(rgmii_id, LPORT_RGMII, IB_STATUS, LINK_DECODE, reg_ib_status, link_decode);
+    reg_ib_status = RU_FIELD_SET(rgmii_id, LPORT_RGMII, IB_STATUS, DUPLEX_DECODE, reg_ib_status, duplex_decode);
+    reg_ib_status = RU_FIELD_SET(rgmii_id, LPORT_RGMII, IB_STATUS, SPEED_DECODE, reg_ib_status, speed_decode);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, IB_STATUS, reg_ib_status);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ib_status_get(uint8_t rgmii_id, uint8_t *ib_status_ovrd, uint8_t *link_decode, uint8_t *duplex_decode, uint8_t *speed_decode)
+{
+    uint32_t reg_ib_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!ib_status_ovrd || !link_decode || !duplex_decode || !speed_decode)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, IB_STATUS, reg_ib_status);
+
+    *ib_status_ovrd = RU_FIELD_GET(rgmii_id, LPORT_RGMII, IB_STATUS, IB_STATUS_OVRD, reg_ib_status);
+    *link_decode = RU_FIELD_GET(rgmii_id, LPORT_RGMII, IB_STATUS, LINK_DECODE, reg_ib_status);
+    *duplex_decode = RU_FIELD_GET(rgmii_id, LPORT_RGMII, IB_STATUS, DUPLEX_DECODE, reg_ib_status);
+    *speed_decode = RU_FIELD_GET(rgmii_id, LPORT_RGMII, IB_STATUS, SPEED_DECODE, reg_ib_status);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_rx_clock_delay_cntrl_set(uint8_t rgmii_id, const lport_rgmii_rx_clock_delay_cntrl *rx_clock_delay_cntrl)
+{
+    uint32_t reg_rx_clock_delay_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_clock_delay_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (rx_clock_delay_cntrl->reset >= _1BITS_MAX_VAL_) ||
+       (rx_clock_delay_cntrl->dly_override >= _1BITS_MAX_VAL_) ||
+       (rx_clock_delay_cntrl->dly_sel >= _1BITS_MAX_VAL_) ||
+       (rx_clock_delay_cntrl->bypass >= _1BITS_MAX_VAL_) ||
+       (rx_clock_delay_cntrl->iddq >= _1BITS_MAX_VAL_) ||
+       (rx_clock_delay_cntrl->drng >= _2BITS_MAX_VAL_) ||
+       (rx_clock_delay_cntrl->ctri >= _2BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_rx_clock_delay_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, RESET, reg_rx_clock_delay_cntrl, rx_clock_delay_cntrl->reset);
+    reg_rx_clock_delay_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, DLY_OVERRIDE, reg_rx_clock_delay_cntrl, rx_clock_delay_cntrl->dly_override);
+    reg_rx_clock_delay_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, DLY_SEL, reg_rx_clock_delay_cntrl, rx_clock_delay_cntrl->dly_sel);
+    reg_rx_clock_delay_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, BYPASS, reg_rx_clock_delay_cntrl, rx_clock_delay_cntrl->bypass);
+    reg_rx_clock_delay_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, IDDQ, reg_rx_clock_delay_cntrl, rx_clock_delay_cntrl->iddq);
+    reg_rx_clock_delay_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, DRNG, reg_rx_clock_delay_cntrl, rx_clock_delay_cntrl->drng);
+    reg_rx_clock_delay_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, CTRI, reg_rx_clock_delay_cntrl, rx_clock_delay_cntrl->ctri);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, reg_rx_clock_delay_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_rx_clock_delay_cntrl_get(uint8_t rgmii_id, lport_rgmii_rx_clock_delay_cntrl *rx_clock_delay_cntrl)
+{
+    uint32_t reg_rx_clock_delay_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_clock_delay_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, reg_rx_clock_delay_cntrl);
+
+    rx_clock_delay_cntrl->reset = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, RESET, reg_rx_clock_delay_cntrl);
+    rx_clock_delay_cntrl->dly_override = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, DLY_OVERRIDE, reg_rx_clock_delay_cntrl);
+    rx_clock_delay_cntrl->dly_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, DLY_SEL, reg_rx_clock_delay_cntrl);
+    rx_clock_delay_cntrl->bypass = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, BYPASS, reg_rx_clock_delay_cntrl);
+    rx_clock_delay_cntrl->iddq = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, IDDQ, reg_rx_clock_delay_cntrl);
+    rx_clock_delay_cntrl->drng = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, DRNG, reg_rx_clock_delay_cntrl);
+    rx_clock_delay_cntrl->ctri = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_CLOCK_DELAY_CNTRL, CTRI, reg_rx_clock_delay_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_rx_cntrl_exp_data_set(uint8_t rgmii_id, const lport_rgmii_ate_rx_cntrl_exp_data *ate_rx_cntrl_exp_data)
+{
+    uint32_t reg_ate_rx_cntrl_exp_data=0;
+
+#ifdef VALIDATE_PARMS
+    if(!ate_rx_cntrl_exp_data)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (ate_rx_cntrl_exp_data->ate_en >= _1BITS_MAX_VAL_) ||
+       (ate_rx_cntrl_exp_data->pkt_count_rst >= _1BITS_MAX_VAL_) ||
+       (ate_rx_cntrl_exp_data->expected_data_1 >= _9BITS_MAX_VAL_) ||
+       (ate_rx_cntrl_exp_data->expected_data_0 >= _9BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ate_rx_cntrl_exp_data = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, ATE_EN, reg_ate_rx_cntrl_exp_data, ate_rx_cntrl_exp_data->ate_en);
+    reg_ate_rx_cntrl_exp_data = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, PKT_COUNT_RST, reg_ate_rx_cntrl_exp_data, ate_rx_cntrl_exp_data->pkt_count_rst);
+    reg_ate_rx_cntrl_exp_data = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, GOOD_COUNT, reg_ate_rx_cntrl_exp_data, ate_rx_cntrl_exp_data->good_count);
+    reg_ate_rx_cntrl_exp_data = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, EXPECTED_DATA_1, reg_ate_rx_cntrl_exp_data, ate_rx_cntrl_exp_data->expected_data_1);
+    reg_ate_rx_cntrl_exp_data = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, EXPECTED_DATA_0, reg_ate_rx_cntrl_exp_data, ate_rx_cntrl_exp_data->expected_data_0);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, reg_ate_rx_cntrl_exp_data);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_rx_cntrl_exp_data_get(uint8_t rgmii_id, lport_rgmii_ate_rx_cntrl_exp_data *ate_rx_cntrl_exp_data)
+{
+    uint32_t reg_ate_rx_cntrl_exp_data=0;
+
+#ifdef VALIDATE_PARMS
+    if(!ate_rx_cntrl_exp_data)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, reg_ate_rx_cntrl_exp_data);
+
+    ate_rx_cntrl_exp_data->ate_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, ATE_EN, reg_ate_rx_cntrl_exp_data);
+    ate_rx_cntrl_exp_data->pkt_count_rst = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, PKT_COUNT_RST, reg_ate_rx_cntrl_exp_data);
+    ate_rx_cntrl_exp_data->good_count = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, GOOD_COUNT, reg_ate_rx_cntrl_exp_data);
+    ate_rx_cntrl_exp_data->expected_data_1 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, EXPECTED_DATA_1, reg_ate_rx_cntrl_exp_data);
+    ate_rx_cntrl_exp_data->expected_data_0 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_CNTRL_EXP_DATA, EXPECTED_DATA_0, reg_ate_rx_cntrl_exp_data);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_rx_exp_data_1_set(uint8_t rgmii_id, uint16_t expected_data_3, uint16_t expected_data_2)
+{
+    uint32_t reg_ate_rx_exp_data_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (expected_data_3 >= _9BITS_MAX_VAL_) ||
+       (expected_data_2 >= _9BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ate_rx_exp_data_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_RX_EXP_DATA_1, EXPECTED_DATA_3, reg_ate_rx_exp_data_1, expected_data_3);
+    reg_ate_rx_exp_data_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_RX_EXP_DATA_1, EXPECTED_DATA_2, reg_ate_rx_exp_data_1, expected_data_2);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, ATE_RX_EXP_DATA_1, reg_ate_rx_exp_data_1);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_rx_exp_data_1_get(uint8_t rgmii_id, uint16_t *expected_data_3, uint16_t *expected_data_2)
+{
+    uint32_t reg_ate_rx_exp_data_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!expected_data_3 || !expected_data_2)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, ATE_RX_EXP_DATA_1, reg_ate_rx_exp_data_1);
+
+    *expected_data_3 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_EXP_DATA_1, EXPECTED_DATA_3, reg_ate_rx_exp_data_1);
+    *expected_data_2 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_EXP_DATA_1, EXPECTED_DATA_2, reg_ate_rx_exp_data_1);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_rx_status_0_get(uint8_t rgmii_id, uint8_t *rx_ok, uint16_t *received_data_1, uint16_t *received_data_0)
+{
+    uint32_t reg_ate_rx_status_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_ok || !received_data_1 || !received_data_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, ATE_RX_STATUS_0, reg_ate_rx_status_0);
+
+    *rx_ok = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_STATUS_0, RX_OK, reg_ate_rx_status_0);
+    *received_data_1 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_STATUS_0, RECEIVED_DATA_1, reg_ate_rx_status_0);
+    *received_data_0 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_STATUS_0, RECEIVED_DATA_0, reg_ate_rx_status_0);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_rx_status_1_get(uint8_t rgmii_id, uint16_t *received_data_3, uint16_t *received_data_2)
+{
+    uint32_t reg_ate_rx_status_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!received_data_3 || !received_data_2)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, ATE_RX_STATUS_1, reg_ate_rx_status_1);
+
+    *received_data_3 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_STATUS_1, RECEIVED_DATA_3, reg_ate_rx_status_1);
+    *received_data_2 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_RX_STATUS_1, RECEIVED_DATA_2, reg_ate_rx_status_1);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_tx_cntrl_set(uint8_t rgmii_id, const lport_rgmii_ate_tx_cntrl *ate_tx_cntrl)
+{
+    uint32_t reg_ate_tx_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!ate_tx_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (ate_tx_cntrl->pkt_ipg >= _6BITS_MAX_VAL_) ||
+       (ate_tx_cntrl->payload_length >= _11BITS_MAX_VAL_) ||
+       (ate_tx_cntrl->pkt_gen_en >= _1BITS_MAX_VAL_) ||
+       (ate_tx_cntrl->start_stop >= _1BITS_MAX_VAL_) ||
+       (ate_tx_cntrl->start_stop_ovrd >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ate_tx_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, PKT_IPG, reg_ate_tx_cntrl, ate_tx_cntrl->pkt_ipg);
+    reg_ate_tx_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, PAYLOAD_LENGTH, reg_ate_tx_cntrl, ate_tx_cntrl->payload_length);
+    reg_ate_tx_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, PKT_CNT, reg_ate_tx_cntrl, ate_tx_cntrl->pkt_cnt);
+    reg_ate_tx_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, PKT_GEN_EN, reg_ate_tx_cntrl, ate_tx_cntrl->pkt_gen_en);
+    reg_ate_tx_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, START_STOP, reg_ate_tx_cntrl, ate_tx_cntrl->start_stop);
+    reg_ate_tx_cntrl = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, START_STOP_OVRD, reg_ate_tx_cntrl, ate_tx_cntrl->start_stop_ovrd);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, reg_ate_tx_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_tx_cntrl_get(uint8_t rgmii_id, lport_rgmii_ate_tx_cntrl *ate_tx_cntrl)
+{
+    uint32_t reg_ate_tx_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!ate_tx_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, reg_ate_tx_cntrl);
+
+    ate_tx_cntrl->pkt_ipg = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, PKT_IPG, reg_ate_tx_cntrl);
+    ate_tx_cntrl->payload_length = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, PAYLOAD_LENGTH, reg_ate_tx_cntrl);
+    ate_tx_cntrl->pkt_cnt = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, PKT_CNT, reg_ate_tx_cntrl);
+    ate_tx_cntrl->pkt_gen_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, PKT_GEN_EN, reg_ate_tx_cntrl);
+    ate_tx_cntrl->start_stop = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, START_STOP, reg_ate_tx_cntrl);
+    ate_tx_cntrl->start_stop_ovrd = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_CNTRL, START_STOP_OVRD, reg_ate_tx_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_tx_data_0_set(uint8_t rgmii_id, uint16_t tx_data_1, uint16_t tx_data_0)
+{
+    uint32_t reg_ate_tx_data_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (tx_data_1 >= _9BITS_MAX_VAL_) ||
+       (tx_data_0 >= _9BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ate_tx_data_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_0, TX_DATA_1, reg_ate_tx_data_0, tx_data_1);
+    reg_ate_tx_data_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_0, TX_DATA_0, reg_ate_tx_data_0, tx_data_0);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, ATE_TX_DATA_0, reg_ate_tx_data_0);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_tx_data_0_get(uint8_t rgmii_id, uint16_t *tx_data_1, uint16_t *tx_data_0)
+{
+    uint32_t reg_ate_tx_data_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_data_1 || !tx_data_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, ATE_TX_DATA_0, reg_ate_tx_data_0);
+
+    *tx_data_1 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_0, TX_DATA_1, reg_ate_tx_data_0);
+    *tx_data_0 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_0, TX_DATA_0, reg_ate_tx_data_0);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_tx_data_1_set(uint8_t rgmii_id, uint16_t tx_data_3, uint16_t tx_data_2)
+{
+    uint32_t reg_ate_tx_data_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (tx_data_3 >= _9BITS_MAX_VAL_) ||
+       (tx_data_2 >= _9BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ate_tx_data_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_1, TX_DATA_3, reg_ate_tx_data_1, tx_data_3);
+    reg_ate_tx_data_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_1, TX_DATA_2, reg_ate_tx_data_1, tx_data_2);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, ATE_TX_DATA_1, reg_ate_tx_data_1);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_tx_data_1_get(uint8_t rgmii_id, uint16_t *tx_data_3, uint16_t *tx_data_2)
+{
+    uint32_t reg_ate_tx_data_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_data_3 || !tx_data_2)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, ATE_TX_DATA_1, reg_ate_tx_data_1);
+
+    *tx_data_3 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_1, TX_DATA_3, reg_ate_tx_data_1);
+    *tx_data_2 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_1, TX_DATA_2, reg_ate_tx_data_1);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_tx_data_2_set(uint8_t rgmii_id, uint16_t ether_type, uint8_t tx_data_5, uint8_t tx_data_4)
+{
+    uint32_t reg_ate_tx_data_2=0;
+
+#ifdef VALIDATE_PARMS
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ate_tx_data_2 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_2, ETHER_TYPE, reg_ate_tx_data_2, ether_type);
+    reg_ate_tx_data_2 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_2, TX_DATA_5, reg_ate_tx_data_2, tx_data_5);
+    reg_ate_tx_data_2 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_2, TX_DATA_4, reg_ate_tx_data_2, tx_data_4);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, ATE_TX_DATA_2, reg_ate_tx_data_2);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_ate_tx_data_2_get(uint8_t rgmii_id, uint16_t *ether_type, uint8_t *tx_data_5, uint8_t *tx_data_4)
+{
+    uint32_t reg_ate_tx_data_2=0;
+
+#ifdef VALIDATE_PARMS
+    if(!ether_type || !tx_data_5 || !tx_data_4)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, ATE_TX_DATA_2, reg_ate_tx_data_2);
+
+    *ether_type = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_2, ETHER_TYPE, reg_ate_tx_data_2);
+    *tx_data_5 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_2, TX_DATA_5, reg_ate_tx_data_2);
+    *tx_data_4 = RU_FIELD_GET(rgmii_id, LPORT_RGMII, ATE_TX_DATA_2, TX_DATA_4, reg_ate_tx_data_2);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_tx_delay_cntrl_0_set(uint8_t rgmii_id, const lport_rgmii_tx_delay_cntrl_0 *tx_delay_cntrl_0)
+{
+    uint32_t reg_tx_delay_cntrl_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_delay_cntrl_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (tx_delay_cntrl_0->txd3_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_0->txd3_del_sel >= _6BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_0->txd2_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_0->txd2_del_sel >= _6BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_0->txd1_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_0->txd1_del_sel >= _6BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_0->txd0_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_0->txd0_del_sel >= _6BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_tx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD3_DEL_OVRD_EN, reg_tx_delay_cntrl_0, tx_delay_cntrl_0->txd3_del_ovrd_en);
+    reg_tx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD3_DEL_SEL, reg_tx_delay_cntrl_0, tx_delay_cntrl_0->txd3_del_sel);
+    reg_tx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD2_DEL_OVRD_EN, reg_tx_delay_cntrl_0, tx_delay_cntrl_0->txd2_del_ovrd_en);
+    reg_tx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD2_DEL_SEL, reg_tx_delay_cntrl_0, tx_delay_cntrl_0->txd2_del_sel);
+    reg_tx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD1_DEL_OVRD_EN, reg_tx_delay_cntrl_0, tx_delay_cntrl_0->txd1_del_ovrd_en);
+    reg_tx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD1_DEL_SEL, reg_tx_delay_cntrl_0, tx_delay_cntrl_0->txd1_del_sel);
+    reg_tx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD0_DEL_OVRD_EN, reg_tx_delay_cntrl_0, tx_delay_cntrl_0->txd0_del_ovrd_en);
+    reg_tx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD0_DEL_SEL, reg_tx_delay_cntrl_0, tx_delay_cntrl_0->txd0_del_sel);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, reg_tx_delay_cntrl_0);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_tx_delay_cntrl_0_get(uint8_t rgmii_id, lport_rgmii_tx_delay_cntrl_0 *tx_delay_cntrl_0)
+{
+    uint32_t reg_tx_delay_cntrl_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_delay_cntrl_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, reg_tx_delay_cntrl_0);
+
+    tx_delay_cntrl_0->txd3_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD3_DEL_OVRD_EN, reg_tx_delay_cntrl_0);
+    tx_delay_cntrl_0->txd3_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD3_DEL_SEL, reg_tx_delay_cntrl_0);
+    tx_delay_cntrl_0->txd2_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD2_DEL_OVRD_EN, reg_tx_delay_cntrl_0);
+    tx_delay_cntrl_0->txd2_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD2_DEL_SEL, reg_tx_delay_cntrl_0);
+    tx_delay_cntrl_0->txd1_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD1_DEL_OVRD_EN, reg_tx_delay_cntrl_0);
+    tx_delay_cntrl_0->txd1_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD1_DEL_SEL, reg_tx_delay_cntrl_0);
+    tx_delay_cntrl_0->txd0_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD0_DEL_OVRD_EN, reg_tx_delay_cntrl_0);
+    tx_delay_cntrl_0->txd0_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_0, TXD0_DEL_SEL, reg_tx_delay_cntrl_0);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_tx_delay_cntrl_1_set(uint8_t rgmii_id, const lport_rgmii_tx_delay_cntrl_1 *tx_delay_cntrl_1)
+{
+    uint32_t reg_tx_delay_cntrl_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_delay_cntrl_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (tx_delay_cntrl_1->txclk_id_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_1->txclk_id_del_sel >= _4BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_1->txclk_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_1->txclk_del_sel >= _4BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_1->txctl_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (tx_delay_cntrl_1->txctl_del_sel >= _6BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_tx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCLK_ID_DEL_OVRD_EN, reg_tx_delay_cntrl_1, tx_delay_cntrl_1->txclk_id_del_ovrd_en);
+    reg_tx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCLK_ID_DEL_SEL, reg_tx_delay_cntrl_1, tx_delay_cntrl_1->txclk_id_del_sel);
+    reg_tx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCLK_DEL_OVRD_EN, reg_tx_delay_cntrl_1, tx_delay_cntrl_1->txclk_del_ovrd_en);
+    reg_tx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCLK_DEL_SEL, reg_tx_delay_cntrl_1, tx_delay_cntrl_1->txclk_del_sel);
+    reg_tx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCTL_DEL_OVRD_EN, reg_tx_delay_cntrl_1, tx_delay_cntrl_1->txctl_del_ovrd_en);
+    reg_tx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCTL_DEL_SEL, reg_tx_delay_cntrl_1, tx_delay_cntrl_1->txctl_del_sel);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, reg_tx_delay_cntrl_1);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_tx_delay_cntrl_1_get(uint8_t rgmii_id, lport_rgmii_tx_delay_cntrl_1 *tx_delay_cntrl_1)
+{
+    uint32_t reg_tx_delay_cntrl_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_delay_cntrl_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, reg_tx_delay_cntrl_1);
+
+    tx_delay_cntrl_1->txclk_id_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCLK_ID_DEL_OVRD_EN, reg_tx_delay_cntrl_1);
+    tx_delay_cntrl_1->txclk_id_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCLK_ID_DEL_SEL, reg_tx_delay_cntrl_1);
+    tx_delay_cntrl_1->txclk_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCLK_DEL_OVRD_EN, reg_tx_delay_cntrl_1);
+    tx_delay_cntrl_1->txclk_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCLK_DEL_SEL, reg_tx_delay_cntrl_1);
+    tx_delay_cntrl_1->txctl_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCTL_DEL_OVRD_EN, reg_tx_delay_cntrl_1);
+    tx_delay_cntrl_1->txctl_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, TX_DELAY_CNTRL_1, TXCTL_DEL_SEL, reg_tx_delay_cntrl_1);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_rx_delay_cntrl_0_set(uint8_t rgmii_id, const lport_rgmii_rx_delay_cntrl_0 *rx_delay_cntrl_0)
+{
+    uint32_t reg_rx_delay_cntrl_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_delay_cntrl_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (rx_delay_cntrl_0->rxd3_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_0->rxd3_del_sel >= _6BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_0->rxd2_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_0->rxd2_del_sel >= _6BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_0->rxd1_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_0->rxd1_del_sel >= _6BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_0->rxd0_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_0->rxd0_del_sel >= _6BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_rx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD3_DEL_OVRD_EN, reg_rx_delay_cntrl_0, rx_delay_cntrl_0->rxd3_del_ovrd_en);
+    reg_rx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD3_DEL_SEL, reg_rx_delay_cntrl_0, rx_delay_cntrl_0->rxd3_del_sel);
+    reg_rx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD2_DEL_OVRD_EN, reg_rx_delay_cntrl_0, rx_delay_cntrl_0->rxd2_del_ovrd_en);
+    reg_rx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD2_DEL_SEL, reg_rx_delay_cntrl_0, rx_delay_cntrl_0->rxd2_del_sel);
+    reg_rx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD1_DEL_OVRD_EN, reg_rx_delay_cntrl_0, rx_delay_cntrl_0->rxd1_del_ovrd_en);
+    reg_rx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD1_DEL_SEL, reg_rx_delay_cntrl_0, rx_delay_cntrl_0->rxd1_del_sel);
+    reg_rx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD0_DEL_OVRD_EN, reg_rx_delay_cntrl_0, rx_delay_cntrl_0->rxd0_del_ovrd_en);
+    reg_rx_delay_cntrl_0 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD0_DEL_SEL, reg_rx_delay_cntrl_0, rx_delay_cntrl_0->rxd0_del_sel);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, reg_rx_delay_cntrl_0);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_rx_delay_cntrl_0_get(uint8_t rgmii_id, lport_rgmii_rx_delay_cntrl_0 *rx_delay_cntrl_0)
+{
+    uint32_t reg_rx_delay_cntrl_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_delay_cntrl_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, reg_rx_delay_cntrl_0);
+
+    rx_delay_cntrl_0->rxd3_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD3_DEL_OVRD_EN, reg_rx_delay_cntrl_0);
+    rx_delay_cntrl_0->rxd3_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD3_DEL_SEL, reg_rx_delay_cntrl_0);
+    rx_delay_cntrl_0->rxd2_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD2_DEL_OVRD_EN, reg_rx_delay_cntrl_0);
+    rx_delay_cntrl_0->rxd2_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD2_DEL_SEL, reg_rx_delay_cntrl_0);
+    rx_delay_cntrl_0->rxd1_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD1_DEL_OVRD_EN, reg_rx_delay_cntrl_0);
+    rx_delay_cntrl_0->rxd1_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD1_DEL_SEL, reg_rx_delay_cntrl_0);
+    rx_delay_cntrl_0->rxd0_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD0_DEL_OVRD_EN, reg_rx_delay_cntrl_0);
+    rx_delay_cntrl_0->rxd0_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_0, RXD0_DEL_SEL, reg_rx_delay_cntrl_0);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_rx_delay_cntrl_1_set(uint8_t rgmii_id, const lport_rgmii_rx_delay_cntrl_1 *rx_delay_cntrl_1)
+{
+    uint32_t reg_rx_delay_cntrl_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_delay_cntrl_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (rx_delay_cntrl_1->rxd7_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_1->rxd7_del_sel >= _6BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_1->rxd6_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_1->rxd6_del_sel >= _6BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_1->rxd5_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_1->rxd5_del_sel >= _6BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_1->rxd4_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_1->rxd4_del_sel >= _6BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_rx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD7_DEL_OVRD_EN, reg_rx_delay_cntrl_1, rx_delay_cntrl_1->rxd7_del_ovrd_en);
+    reg_rx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD7_DEL_SEL, reg_rx_delay_cntrl_1, rx_delay_cntrl_1->rxd7_del_sel);
+    reg_rx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD6_DEL_OVRD_EN, reg_rx_delay_cntrl_1, rx_delay_cntrl_1->rxd6_del_ovrd_en);
+    reg_rx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD6_DEL_SEL, reg_rx_delay_cntrl_1, rx_delay_cntrl_1->rxd6_del_sel);
+    reg_rx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD5_DEL_OVRD_EN, reg_rx_delay_cntrl_1, rx_delay_cntrl_1->rxd5_del_ovrd_en);
+    reg_rx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD5_DEL_SEL, reg_rx_delay_cntrl_1, rx_delay_cntrl_1->rxd5_del_sel);
+    reg_rx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD4_DEL_OVRD_EN, reg_rx_delay_cntrl_1, rx_delay_cntrl_1->rxd4_del_ovrd_en);
+    reg_rx_delay_cntrl_1 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD4_DEL_SEL, reg_rx_delay_cntrl_1, rx_delay_cntrl_1->rxd4_del_sel);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, reg_rx_delay_cntrl_1);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_rx_delay_cntrl_1_get(uint8_t rgmii_id, lport_rgmii_rx_delay_cntrl_1 *rx_delay_cntrl_1)
+{
+    uint32_t reg_rx_delay_cntrl_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_delay_cntrl_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, reg_rx_delay_cntrl_1);
+
+    rx_delay_cntrl_1->rxd7_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD7_DEL_OVRD_EN, reg_rx_delay_cntrl_1);
+    rx_delay_cntrl_1->rxd7_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD7_DEL_SEL, reg_rx_delay_cntrl_1);
+    rx_delay_cntrl_1->rxd6_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD6_DEL_OVRD_EN, reg_rx_delay_cntrl_1);
+    rx_delay_cntrl_1->rxd6_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD6_DEL_SEL, reg_rx_delay_cntrl_1);
+    rx_delay_cntrl_1->rxd5_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD5_DEL_OVRD_EN, reg_rx_delay_cntrl_1);
+    rx_delay_cntrl_1->rxd5_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD5_DEL_SEL, reg_rx_delay_cntrl_1);
+    rx_delay_cntrl_1->rxd4_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD4_DEL_OVRD_EN, reg_rx_delay_cntrl_1);
+    rx_delay_cntrl_1->rxd4_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_1, RXD4_DEL_SEL, reg_rx_delay_cntrl_1);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_rx_delay_cntrl_2_set(uint8_t rgmii_id, const lport_rgmii_rx_delay_cntrl_2 *rx_delay_cntrl_2)
+{
+    uint32_t reg_rx_delay_cntrl_2=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_delay_cntrl_2)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT) ||
+       (rx_delay_cntrl_2->rxclk_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_2->rxclk_del_sel >= _4BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_2->rxctl_neg_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_2->rxctl_neg_del_sel >= _6BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_2->rxctl_pos_del_ovrd_en >= _1BITS_MAX_VAL_) ||
+       (rx_delay_cntrl_2->rxctl_pos_del_sel >= _6BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_rx_delay_cntrl_2 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCLK_DEL_OVRD_EN, reg_rx_delay_cntrl_2, rx_delay_cntrl_2->rxclk_del_ovrd_en);
+    reg_rx_delay_cntrl_2 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCLK_DEL_SEL, reg_rx_delay_cntrl_2, rx_delay_cntrl_2->rxclk_del_sel);
+    reg_rx_delay_cntrl_2 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCTL_NEG_DEL_OVRD_EN, reg_rx_delay_cntrl_2, rx_delay_cntrl_2->rxctl_neg_del_ovrd_en);
+    reg_rx_delay_cntrl_2 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCTL_NEG_DEL_SEL, reg_rx_delay_cntrl_2, rx_delay_cntrl_2->rxctl_neg_del_sel);
+    reg_rx_delay_cntrl_2 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCTL_POS_DEL_OVRD_EN, reg_rx_delay_cntrl_2, rx_delay_cntrl_2->rxctl_pos_del_ovrd_en);
+    reg_rx_delay_cntrl_2 = RU_FIELD_SET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCTL_POS_DEL_SEL, reg_rx_delay_cntrl_2, rx_delay_cntrl_2->rxctl_pos_del_sel);
+
+    RU_REG_WRITE(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, reg_rx_delay_cntrl_2);
+
+    return 0;
+}
+
+int ag_drv_lport_rgmii_rx_delay_cntrl_2_get(uint8_t rgmii_id, lport_rgmii_rx_delay_cntrl_2 *rx_delay_cntrl_2)
+{
+    uint32_t reg_rx_delay_cntrl_2=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_delay_cntrl_2)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((rgmii_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, reg_rx_delay_cntrl_2);
+
+    rx_delay_cntrl_2->rxclk_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCLK_DEL_OVRD_EN, reg_rx_delay_cntrl_2);
+    rx_delay_cntrl_2->rxclk_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCLK_DEL_SEL, reg_rx_delay_cntrl_2);
+    rx_delay_cntrl_2->rxctl_neg_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCTL_NEG_DEL_OVRD_EN, reg_rx_delay_cntrl_2);
+    rx_delay_cntrl_2->rxctl_neg_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCTL_NEG_DEL_SEL, reg_rx_delay_cntrl_2);
+    rx_delay_cntrl_2->rxctl_pos_del_ovrd_en = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCTL_POS_DEL_OVRD_EN, reg_rx_delay_cntrl_2);
+    rx_delay_cntrl_2->rxctl_pos_del_sel = RU_FIELD_GET(rgmii_id, LPORT_RGMII, RX_DELAY_CNTRL_2, RXCTL_POS_DEL_SEL, reg_rx_delay_cntrl_2);
+
+    return 0;
+}
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_rgmii_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_lport_rgmii_ag.h
new file mode 100644
index 0000000000..a9165993e5
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_rgmii_ag.h
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_LPORT_RGMII_AG_H_
+#define _BCM6858_LPORT_RGMII_AG_H_
+
+#include "access_macros.h"
+#include "bcmtypes.h"
+typedef struct
+{
+    uint8_t col_crs_mask;
+    uint8_t rx_err_mask;
+    uint8_t lpi_count;
+    uint8_t tx_clk_stop_en;
+    uint8_t tx_pause_en;
+    uint8_t rx_pause_en;
+    uint8_t rvmii_ref_sel;
+    uint8_t port_mode;
+    uint8_t id_mode_dis;
+    uint8_t rgmii_mode_en;
+} lport_rgmii_cntrl;
+
+typedef struct
+{
+    uint8_t reset;
+    uint8_t dly_override;
+    uint8_t dly_sel;
+    uint8_t bypass;
+    uint8_t iddq;
+    uint8_t drng;
+    uint8_t ctri;
+} lport_rgmii_rx_clock_delay_cntrl;
+
+typedef struct
+{
+    uint8_t ate_en;
+    uint8_t pkt_count_rst;
+    uint8_t good_count;
+    uint16_t expected_data_1;
+    uint16_t expected_data_0;
+} lport_rgmii_ate_rx_cntrl_exp_data;
+
+typedef struct
+{
+    uint8_t pkt_ipg;
+    uint16_t payload_length;
+    uint8_t pkt_cnt;
+    uint8_t pkt_gen_en;
+    uint8_t start_stop;
+    uint8_t start_stop_ovrd;
+} lport_rgmii_ate_tx_cntrl;
+
+typedef struct
+{
+    uint8_t txd3_del_ovrd_en;
+    uint8_t txd3_del_sel;
+    uint8_t txd2_del_ovrd_en;
+    uint8_t txd2_del_sel;
+    uint8_t txd1_del_ovrd_en;
+    uint8_t txd1_del_sel;
+    uint8_t txd0_del_ovrd_en;
+    uint8_t txd0_del_sel;
+} lport_rgmii_tx_delay_cntrl_0;
+
+typedef struct
+{
+    uint8_t txclk_id_del_ovrd_en;
+    uint8_t txclk_id_del_sel;
+    uint8_t txclk_del_ovrd_en;
+    uint8_t txclk_del_sel;
+    uint8_t txctl_del_ovrd_en;
+    uint8_t txctl_del_sel;
+} lport_rgmii_tx_delay_cntrl_1;
+
+typedef struct
+{
+    uint8_t rxd3_del_ovrd_en;
+    uint8_t rxd3_del_sel;
+    uint8_t rxd2_del_ovrd_en;
+    uint8_t rxd2_del_sel;
+    uint8_t rxd1_del_ovrd_en;
+    uint8_t rxd1_del_sel;
+    uint8_t rxd0_del_ovrd_en;
+    uint8_t rxd0_del_sel;
+} lport_rgmii_rx_delay_cntrl_0;
+
+typedef struct
+{
+    uint8_t rxd7_del_ovrd_en;
+    uint8_t rxd7_del_sel;
+    uint8_t rxd6_del_ovrd_en;
+    uint8_t rxd6_del_sel;
+    uint8_t rxd5_del_ovrd_en;
+    uint8_t rxd5_del_sel;
+    uint8_t rxd4_del_ovrd_en;
+    uint8_t rxd4_del_sel;
+} lport_rgmii_rx_delay_cntrl_1;
+
+typedef struct
+{
+    uint8_t rxclk_del_ovrd_en;
+    uint8_t rxclk_del_sel;
+    uint8_t rxctl_neg_del_ovrd_en;
+    uint8_t rxctl_neg_del_sel;
+    uint8_t rxctl_pos_del_ovrd_en;
+    uint8_t rxctl_pos_del_sel;
+} lport_rgmii_rx_delay_cntrl_2;
+
+int ag_drv_lport_rgmii_cntrl_set(uint8_t rgmii_id, const lport_rgmii_cntrl *cntrl);
+int ag_drv_lport_rgmii_cntrl_get(uint8_t rgmii_id, lport_rgmii_cntrl *cntrl);
+int ag_drv_lport_rgmii_ib_status_set(uint8_t rgmii_id, uint8_t ib_status_ovrd, uint8_t link_decode, uint8_t duplex_decode, uint8_t speed_decode);
+int ag_drv_lport_rgmii_ib_status_get(uint8_t rgmii_id, uint8_t *ib_status_ovrd, uint8_t *link_decode, uint8_t *duplex_decode, uint8_t *speed_decode);
+int ag_drv_lport_rgmii_rx_clock_delay_cntrl_set(uint8_t rgmii_id, const lport_rgmii_rx_clock_delay_cntrl *rx_clock_delay_cntrl);
+int ag_drv_lport_rgmii_rx_clock_delay_cntrl_get(uint8_t rgmii_id, lport_rgmii_rx_clock_delay_cntrl *rx_clock_delay_cntrl);
+int ag_drv_lport_rgmii_ate_rx_cntrl_exp_data_set(uint8_t rgmii_id, const lport_rgmii_ate_rx_cntrl_exp_data *ate_rx_cntrl_exp_data);
+int ag_drv_lport_rgmii_ate_rx_cntrl_exp_data_get(uint8_t rgmii_id, lport_rgmii_ate_rx_cntrl_exp_data *ate_rx_cntrl_exp_data);
+int ag_drv_lport_rgmii_ate_rx_exp_data_1_set(uint8_t rgmii_id, uint16_t expected_data_3, uint16_t expected_data_2);
+int ag_drv_lport_rgmii_ate_rx_exp_data_1_get(uint8_t rgmii_id, uint16_t *expected_data_3, uint16_t *expected_data_2);
+int ag_drv_lport_rgmii_ate_rx_status_0_get(uint8_t rgmii_id, uint8_t *rx_ok, uint16_t *received_data_1, uint16_t *received_data_0);
+int ag_drv_lport_rgmii_ate_rx_status_1_get(uint8_t rgmii_id, uint16_t *received_data_3, uint16_t *received_data_2);
+int ag_drv_lport_rgmii_ate_tx_cntrl_set(uint8_t rgmii_id, const lport_rgmii_ate_tx_cntrl *ate_tx_cntrl);
+int ag_drv_lport_rgmii_ate_tx_cntrl_get(uint8_t rgmii_id, lport_rgmii_ate_tx_cntrl *ate_tx_cntrl);
+int ag_drv_lport_rgmii_ate_tx_data_0_set(uint8_t rgmii_id, uint16_t tx_data_1, uint16_t tx_data_0);
+int ag_drv_lport_rgmii_ate_tx_data_0_get(uint8_t rgmii_id, uint16_t *tx_data_1, uint16_t *tx_data_0);
+int ag_drv_lport_rgmii_ate_tx_data_1_set(uint8_t rgmii_id, uint16_t tx_data_3, uint16_t tx_data_2);
+int ag_drv_lport_rgmii_ate_tx_data_1_get(uint8_t rgmii_id, uint16_t *tx_data_3, uint16_t *tx_data_2);
+int ag_drv_lport_rgmii_ate_tx_data_2_set(uint8_t rgmii_id, uint16_t ether_type, uint8_t tx_data_5, uint8_t tx_data_4);
+int ag_drv_lport_rgmii_ate_tx_data_2_get(uint8_t rgmii_id, uint16_t *ether_type, uint8_t *tx_data_5, uint8_t *tx_data_4);
+int ag_drv_lport_rgmii_tx_delay_cntrl_0_set(uint8_t rgmii_id, const lport_rgmii_tx_delay_cntrl_0 *tx_delay_cntrl_0);
+int ag_drv_lport_rgmii_tx_delay_cntrl_0_get(uint8_t rgmii_id, lport_rgmii_tx_delay_cntrl_0 *tx_delay_cntrl_0);
+int ag_drv_lport_rgmii_tx_delay_cntrl_1_set(uint8_t rgmii_id, const lport_rgmii_tx_delay_cntrl_1 *tx_delay_cntrl_1);
+int ag_drv_lport_rgmii_tx_delay_cntrl_1_get(uint8_t rgmii_id, lport_rgmii_tx_delay_cntrl_1 *tx_delay_cntrl_1);
+int ag_drv_lport_rgmii_rx_delay_cntrl_0_set(uint8_t rgmii_id, const lport_rgmii_rx_delay_cntrl_0 *rx_delay_cntrl_0);
+int ag_drv_lport_rgmii_rx_delay_cntrl_0_get(uint8_t rgmii_id, lport_rgmii_rx_delay_cntrl_0 *rx_delay_cntrl_0);
+int ag_drv_lport_rgmii_rx_delay_cntrl_1_set(uint8_t rgmii_id, const lport_rgmii_rx_delay_cntrl_1 *rx_delay_cntrl_1);
+int ag_drv_lport_rgmii_rx_delay_cntrl_1_get(uint8_t rgmii_id, lport_rgmii_rx_delay_cntrl_1 *rx_delay_cntrl_1);
+int ag_drv_lport_rgmii_rx_delay_cntrl_2_set(uint8_t rgmii_id, const lport_rgmii_rx_delay_cntrl_2 *rx_delay_cntrl_2);
+int ag_drv_lport_rgmii_rx_delay_cntrl_2_get(uint8_t rgmii_id, lport_rgmii_rx_delay_cntrl_2 *rx_delay_cntrl_2);
+
+#ifdef USE_BDMF_SHELL
+bdmfmon_handle_t ag_drv_lport_rgmii_cli_init(bdmfmon_handle_t driver_dir);
+#endif
+
+
+#endif
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_srds_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_lport_srds_ag.c
new file mode 100644
index 0000000000..f0268f3866
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_srds_ag.c
@@ -0,0 +1,641 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_lport_srds_ag.h"
+int ag_drv_lport_srds_merlin_rev_get(uint16_t *serdes_rev)
+{
+    uint32_t reg_dual_serdes_revision=0;
+
+#ifdef VALIDATE_PARMS
+    if(!serdes_rev)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, DUAL_SERDES_REVISION, reg_dual_serdes_revision);
+
+    *serdes_rev = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_REVISION, SERDES_REV, reg_dual_serdes_revision);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_cntrl_0_set(uint8_t err, uint8_t start_busy, uint8_t r_w, uint16_t reg_data)
+{
+    uint32_t reg_serdes_0_indir_acc_cntrl_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((err >= _1BITS_MAX_VAL_) ||
+       (start_busy >= _1BITS_MAX_VAL_) ||
+       (r_w >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_serdes_0_indir_acc_cntrl_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_0, ERR, reg_serdes_0_indir_acc_cntrl_0, err);
+    reg_serdes_0_indir_acc_cntrl_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_0, START_BUSY, reg_serdes_0_indir_acc_cntrl_0, start_busy);
+    reg_serdes_0_indir_acc_cntrl_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_0, R_W, reg_serdes_0_indir_acc_cntrl_0, r_w);
+    reg_serdes_0_indir_acc_cntrl_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_0, REG_DATA, reg_serdes_0_indir_acc_cntrl_0, reg_data);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_0, reg_serdes_0_indir_acc_cntrl_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_cntrl_0_get(uint8_t *err, uint8_t *start_busy, uint8_t *r_w, uint16_t *reg_data)
+{
+    uint32_t reg_serdes_0_indir_acc_cntrl_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!err || !start_busy || !r_w || !reg_data)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_0, reg_serdes_0_indir_acc_cntrl_0);
+
+    *err = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_0, ERR, reg_serdes_0_indir_acc_cntrl_0);
+    *start_busy = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_0, START_BUSY, reg_serdes_0_indir_acc_cntrl_0);
+    *r_w = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_0, R_W, reg_serdes_0_indir_acc_cntrl_0);
+    *reg_data = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_0, REG_DATA, reg_serdes_0_indir_acc_cntrl_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_addr_0_set(uint32_t reg_addr)
+{
+    uint32_t reg_serdes_0_indir_acc_addr_0=0;
+
+#ifdef VALIDATE_PARMS
+#endif
+
+    reg_serdes_0_indir_acc_addr_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_ADDR_0, REG_ADDR, reg_serdes_0_indir_acc_addr_0, reg_addr);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_0_INDIR_ACC_ADDR_0, reg_serdes_0_indir_acc_addr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_addr_0_get(uint32_t *reg_addr)
+{
+    uint32_t reg_serdes_0_indir_acc_addr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!reg_addr)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_0_INDIR_ACC_ADDR_0, reg_serdes_0_indir_acc_addr_0);
+
+    *reg_addr = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_ADDR_0, REG_ADDR, reg_serdes_0_indir_acc_addr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_mask_0_set(uint16_t reg_mask)
+{
+    uint32_t reg_serdes_0_indir_acc_mask_0=0;
+
+#ifdef VALIDATE_PARMS
+#endif
+
+    reg_serdes_0_indir_acc_mask_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_MASK_0, REG_MASK, reg_serdes_0_indir_acc_mask_0, reg_mask);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_0_INDIR_ACC_MASK_0, reg_serdes_0_indir_acc_mask_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_mask_0_get(uint16_t *reg_mask)
+{
+    uint32_t reg_serdes_0_indir_acc_mask_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!reg_mask)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_0_INDIR_ACC_MASK_0, reg_serdes_0_indir_acc_mask_0);
+
+    *reg_mask = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_MASK_0, REG_MASK, reg_serdes_0_indir_acc_mask_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_cntrl_1_set(uint8_t err, uint8_t start_busy, uint8_t r_w, uint16_t reg_data)
+{
+    uint32_t reg_serdes_0_indir_acc_cntrl_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((err >= _1BITS_MAX_VAL_) ||
+       (start_busy >= _1BITS_MAX_VAL_) ||
+       (r_w >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_serdes_0_indir_acc_cntrl_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_1, ERR, reg_serdes_0_indir_acc_cntrl_1, err);
+    reg_serdes_0_indir_acc_cntrl_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_1, START_BUSY, reg_serdes_0_indir_acc_cntrl_1, start_busy);
+    reg_serdes_0_indir_acc_cntrl_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_1, R_W, reg_serdes_0_indir_acc_cntrl_1, r_w);
+    reg_serdes_0_indir_acc_cntrl_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_1, REG_DATA, reg_serdes_0_indir_acc_cntrl_1, reg_data);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_1, reg_serdes_0_indir_acc_cntrl_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_cntrl_1_get(uint8_t *err, uint8_t *start_busy, uint8_t *r_w, uint16_t *reg_data)
+{
+    uint32_t reg_serdes_0_indir_acc_cntrl_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!err || !start_busy || !r_w || !reg_data)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_1, reg_serdes_0_indir_acc_cntrl_1);
+
+    *err = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_1, ERR, reg_serdes_0_indir_acc_cntrl_1);
+    *start_busy = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_1, START_BUSY, reg_serdes_0_indir_acc_cntrl_1);
+    *r_w = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_1, R_W, reg_serdes_0_indir_acc_cntrl_1);
+    *reg_data = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_CNTRL_1, REG_DATA, reg_serdes_0_indir_acc_cntrl_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_addr_1_set(uint32_t reg_addr)
+{
+    uint32_t reg_serdes_0_indir_acc_addr_1=0;
+
+#ifdef VALIDATE_PARMS
+#endif
+
+    reg_serdes_0_indir_acc_addr_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_ADDR_1, REG_ADDR, reg_serdes_0_indir_acc_addr_1, reg_addr);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_0_INDIR_ACC_ADDR_1, reg_serdes_0_indir_acc_addr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_addr_1_get(uint32_t *reg_addr)
+{
+    uint32_t reg_serdes_0_indir_acc_addr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!reg_addr)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_0_INDIR_ACC_ADDR_1, reg_serdes_0_indir_acc_addr_1);
+
+    *reg_addr = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_ADDR_1, REG_ADDR, reg_serdes_0_indir_acc_addr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_mask_1_set(uint16_t reg_mask)
+{
+    uint32_t reg_serdes_0_indir_acc_mask_1=0;
+
+#ifdef VALIDATE_PARMS
+#endif
+
+    reg_serdes_0_indir_acc_mask_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_MASK_1, REG_MASK, reg_serdes_0_indir_acc_mask_1, reg_mask);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_0_INDIR_ACC_MASK_1, reg_serdes_0_indir_acc_mask_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_0_indir_acc_mask_1_get(uint16_t *reg_mask)
+{
+    uint32_t reg_serdes_0_indir_acc_mask_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!reg_mask)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_0_INDIR_ACC_MASK_1, reg_serdes_0_indir_acc_mask_1);
+
+    *reg_mask = RU_FIELD_GET(0, LPORT_SRDS, SERDES_0_INDIR_ACC_MASK_1, REG_MASK, reg_serdes_0_indir_acc_mask_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_cntrl_0_set(uint8_t err, uint8_t start_busy, uint8_t r_w, uint16_t reg_data)
+{
+    uint32_t reg_serdes_1_indir_acc_cntrl_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((err >= _1BITS_MAX_VAL_) ||
+       (start_busy >= _1BITS_MAX_VAL_) ||
+       (r_w >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_serdes_1_indir_acc_cntrl_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_0, ERR, reg_serdes_1_indir_acc_cntrl_0, err);
+    reg_serdes_1_indir_acc_cntrl_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_0, START_BUSY, reg_serdes_1_indir_acc_cntrl_0, start_busy);
+    reg_serdes_1_indir_acc_cntrl_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_0, R_W, reg_serdes_1_indir_acc_cntrl_0, r_w);
+    reg_serdes_1_indir_acc_cntrl_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_0, REG_DATA, reg_serdes_1_indir_acc_cntrl_0, reg_data);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_0, reg_serdes_1_indir_acc_cntrl_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_cntrl_0_get(uint8_t *err, uint8_t *start_busy, uint8_t *r_w, uint16_t *reg_data)
+{
+    uint32_t reg_serdes_1_indir_acc_cntrl_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!err || !start_busy || !r_w || !reg_data)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_0, reg_serdes_1_indir_acc_cntrl_0);
+
+    *err = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_0, ERR, reg_serdes_1_indir_acc_cntrl_0);
+    *start_busy = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_0, START_BUSY, reg_serdes_1_indir_acc_cntrl_0);
+    *r_w = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_0, R_W, reg_serdes_1_indir_acc_cntrl_0);
+    *reg_data = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_0, REG_DATA, reg_serdes_1_indir_acc_cntrl_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_addr_0_set(uint32_t reg_addr)
+{
+    uint32_t reg_serdes_1_indir_acc_addr_0=0;
+
+#ifdef VALIDATE_PARMS
+#endif
+
+    reg_serdes_1_indir_acc_addr_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_ADDR_0, REG_ADDR, reg_serdes_1_indir_acc_addr_0, reg_addr);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_1_INDIR_ACC_ADDR_0, reg_serdes_1_indir_acc_addr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_addr_0_get(uint32_t *reg_addr)
+{
+    uint32_t reg_serdes_1_indir_acc_addr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!reg_addr)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_1_INDIR_ACC_ADDR_0, reg_serdes_1_indir_acc_addr_0);
+
+    *reg_addr = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_ADDR_0, REG_ADDR, reg_serdes_1_indir_acc_addr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_mask_0_set(uint16_t reg_mask)
+{
+    uint32_t reg_serdes_1_indir_acc_mask_0=0;
+
+#ifdef VALIDATE_PARMS
+#endif
+
+    reg_serdes_1_indir_acc_mask_0 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_MASK_0, REG_MASK, reg_serdes_1_indir_acc_mask_0, reg_mask);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_1_INDIR_ACC_MASK_0, reg_serdes_1_indir_acc_mask_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_mask_0_get(uint16_t *reg_mask)
+{
+    uint32_t reg_serdes_1_indir_acc_mask_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!reg_mask)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_1_INDIR_ACC_MASK_0, reg_serdes_1_indir_acc_mask_0);
+
+    *reg_mask = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_MASK_0, REG_MASK, reg_serdes_1_indir_acc_mask_0);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_cntrl_1_set(uint8_t err, uint8_t start_busy, uint8_t r_w, uint16_t reg_data)
+{
+    uint32_t reg_serdes_1_indir_acc_cntrl_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((err >= _1BITS_MAX_VAL_) ||
+       (start_busy >= _1BITS_MAX_VAL_) ||
+       (r_w >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_serdes_1_indir_acc_cntrl_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_1, ERR, reg_serdes_1_indir_acc_cntrl_1, err);
+    reg_serdes_1_indir_acc_cntrl_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_1, START_BUSY, reg_serdes_1_indir_acc_cntrl_1, start_busy);
+    reg_serdes_1_indir_acc_cntrl_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_1, R_W, reg_serdes_1_indir_acc_cntrl_1, r_w);
+    reg_serdes_1_indir_acc_cntrl_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_1, REG_DATA, reg_serdes_1_indir_acc_cntrl_1, reg_data);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_1, reg_serdes_1_indir_acc_cntrl_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_cntrl_1_get(uint8_t *err, uint8_t *start_busy, uint8_t *r_w, uint16_t *reg_data)
+{
+    uint32_t reg_serdes_1_indir_acc_cntrl_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!err || !start_busy || !r_w || !reg_data)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_1, reg_serdes_1_indir_acc_cntrl_1);
+
+    *err = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_1, ERR, reg_serdes_1_indir_acc_cntrl_1);
+    *start_busy = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_1, START_BUSY, reg_serdes_1_indir_acc_cntrl_1);
+    *r_w = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_1, R_W, reg_serdes_1_indir_acc_cntrl_1);
+    *reg_data = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_CNTRL_1, REG_DATA, reg_serdes_1_indir_acc_cntrl_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_addr_1_set(uint32_t reg_addr)
+{
+    uint32_t reg_serdes_1_indir_acc_addr_1=0;
+
+#ifdef VALIDATE_PARMS
+#endif
+
+    reg_serdes_1_indir_acc_addr_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_ADDR_1, REG_ADDR, reg_serdes_1_indir_acc_addr_1, reg_addr);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_1_INDIR_ACC_ADDR_1, reg_serdes_1_indir_acc_addr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_addr_1_get(uint32_t *reg_addr)
+{
+    uint32_t reg_serdes_1_indir_acc_addr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!reg_addr)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_1_INDIR_ACC_ADDR_1, reg_serdes_1_indir_acc_addr_1);
+
+    *reg_addr = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_ADDR_1, REG_ADDR, reg_serdes_1_indir_acc_addr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_mask_1_set(uint16_t reg_mask)
+{
+    uint32_t reg_serdes_1_indir_acc_mask_1=0;
+
+#ifdef VALIDATE_PARMS
+#endif
+
+    reg_serdes_1_indir_acc_mask_1 = RU_FIELD_SET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_MASK_1, REG_MASK, reg_serdes_1_indir_acc_mask_1, reg_mask);
+
+    RU_REG_WRITE(0, LPORT_SRDS, SERDES_1_INDIR_ACC_MASK_1, reg_serdes_1_indir_acc_mask_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_serdes_1_indir_acc_mask_1_get(uint16_t *reg_mask)
+{
+    uint32_t reg_serdes_1_indir_acc_mask_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!reg_mask)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, SERDES_1_INDIR_ACC_MASK_1, reg_serdes_1_indir_acc_mask_1);
+
+    *reg_mask = RU_FIELD_GET(0, LPORT_SRDS, SERDES_1_INDIR_ACC_MASK_1, REG_MASK, reg_serdes_1_indir_acc_mask_1);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_dual_serdes_0_cntrl_set(const lport_srds_dual_serdes_0_cntrl *dual_serdes_0_cntrl)
+{
+    uint32_t reg_dual_serdes_0_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!dual_serdes_0_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((dual_serdes_0_cntrl->serdes_test_en >= _1BITS_MAX_VAL_) ||
+       (dual_serdes_0_cntrl->serdes_ln_offset >= _5BITS_MAX_VAL_) ||
+       (dual_serdes_0_cntrl->serdes_prtad >= _5BITS_MAX_VAL_) ||
+       (dual_serdes_0_cntrl->serdes_reset >= _1BITS_MAX_VAL_) ||
+       (dual_serdes_0_cntrl->refclk_reset >= _1BITS_MAX_VAL_) ||
+       (dual_serdes_0_cntrl->iddq >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_dual_serdes_0_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, SERDES_TEST_EN, reg_dual_serdes_0_cntrl, dual_serdes_0_cntrl->serdes_test_en);
+    reg_dual_serdes_0_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, SERDES_LN_OFFSET, reg_dual_serdes_0_cntrl, dual_serdes_0_cntrl->serdes_ln_offset);
+    reg_dual_serdes_0_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, SERDES_PRTAD, reg_dual_serdes_0_cntrl, dual_serdes_0_cntrl->serdes_prtad);
+    reg_dual_serdes_0_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, SERDES_RESET, reg_dual_serdes_0_cntrl, dual_serdes_0_cntrl->serdes_reset);
+    reg_dual_serdes_0_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, REFCLK_RESET, reg_dual_serdes_0_cntrl, dual_serdes_0_cntrl->refclk_reset);
+    reg_dual_serdes_0_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, IDDQ, reg_dual_serdes_0_cntrl, dual_serdes_0_cntrl->iddq);
+
+    RU_REG_WRITE(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, reg_dual_serdes_0_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_dual_serdes_0_cntrl_get(lport_srds_dual_serdes_0_cntrl *dual_serdes_0_cntrl)
+{
+    uint32_t reg_dual_serdes_0_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!dual_serdes_0_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, reg_dual_serdes_0_cntrl);
+
+    dual_serdes_0_cntrl->serdes_test_en = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, SERDES_TEST_EN, reg_dual_serdes_0_cntrl);
+    dual_serdes_0_cntrl->serdes_ln_offset = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, SERDES_LN_OFFSET, reg_dual_serdes_0_cntrl);
+    dual_serdes_0_cntrl->serdes_prtad = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, SERDES_PRTAD, reg_dual_serdes_0_cntrl);
+    dual_serdes_0_cntrl->serdes_reset = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, SERDES_RESET, reg_dual_serdes_0_cntrl);
+    dual_serdes_0_cntrl->refclk_reset = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, REFCLK_RESET, reg_dual_serdes_0_cntrl);
+    dual_serdes_0_cntrl->iddq = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_CNTRL, IDDQ, reg_dual_serdes_0_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_dual_serdes_0_status_get(lport_srds_dual_serdes_0_status *dual_serdes_0_status)
+{
+    uint32_t reg_dual_serdes_0_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!dual_serdes_0_status)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, DUAL_SERDES_0_STATUS, reg_dual_serdes_0_status);
+
+    dual_serdes_0_status->mod_def0 = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_STATUS, MOD_DEF0, reg_dual_serdes_0_status);
+    dual_serdes_0_status->ext_sig_det = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_STATUS, EXT_SIG_DET, reg_dual_serdes_0_status);
+    dual_serdes_0_status->pll_lock = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_STATUS, PLL_LOCK, reg_dual_serdes_0_status);
+    dual_serdes_0_status->link_status = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_STATUS, LINK_STATUS, reg_dual_serdes_0_status);
+    dual_serdes_0_status->cdr_lock = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_STATUS, CDR_LOCK, reg_dual_serdes_0_status);
+    dual_serdes_0_status->rx_sigdet = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_0_STATUS, RX_SIGDET, reg_dual_serdes_0_status);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_dual_serdes_1_cntrl_set(const lport_srds_dual_serdes_1_cntrl *dual_serdes_1_cntrl)
+{
+    uint32_t reg_dual_serdes_1_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!dual_serdes_1_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((dual_serdes_1_cntrl->serdes_test_en >= _1BITS_MAX_VAL_) ||
+       (dual_serdes_1_cntrl->serdes_ln_offset >= _5BITS_MAX_VAL_) ||
+       (dual_serdes_1_cntrl->serdes_prtad >= _5BITS_MAX_VAL_) ||
+       (dual_serdes_1_cntrl->serdes_reset >= _1BITS_MAX_VAL_) ||
+       (dual_serdes_1_cntrl->refclk_reset >= _1BITS_MAX_VAL_) ||
+       (dual_serdes_1_cntrl->iddq >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_dual_serdes_1_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, SERDES_TEST_EN, reg_dual_serdes_1_cntrl, dual_serdes_1_cntrl->serdes_test_en);
+    reg_dual_serdes_1_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, SERDES_LN_OFFSET, reg_dual_serdes_1_cntrl, dual_serdes_1_cntrl->serdes_ln_offset);
+    reg_dual_serdes_1_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, SERDES_PRTAD, reg_dual_serdes_1_cntrl, dual_serdes_1_cntrl->serdes_prtad);
+    reg_dual_serdes_1_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, SERDES_RESET, reg_dual_serdes_1_cntrl, dual_serdes_1_cntrl->serdes_reset);
+    reg_dual_serdes_1_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, REFCLK_RESET, reg_dual_serdes_1_cntrl, dual_serdes_1_cntrl->refclk_reset);
+    reg_dual_serdes_1_cntrl = RU_FIELD_SET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, IDDQ, reg_dual_serdes_1_cntrl, dual_serdes_1_cntrl->iddq);
+
+    RU_REG_WRITE(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, reg_dual_serdes_1_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_dual_serdes_1_cntrl_get(lport_srds_dual_serdes_1_cntrl *dual_serdes_1_cntrl)
+{
+    uint32_t reg_dual_serdes_1_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!dual_serdes_1_cntrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, reg_dual_serdes_1_cntrl);
+
+    dual_serdes_1_cntrl->serdes_test_en = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, SERDES_TEST_EN, reg_dual_serdes_1_cntrl);
+    dual_serdes_1_cntrl->serdes_ln_offset = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, SERDES_LN_OFFSET, reg_dual_serdes_1_cntrl);
+    dual_serdes_1_cntrl->serdes_prtad = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, SERDES_PRTAD, reg_dual_serdes_1_cntrl);
+    dual_serdes_1_cntrl->serdes_reset = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, SERDES_RESET, reg_dual_serdes_1_cntrl);
+    dual_serdes_1_cntrl->refclk_reset = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, REFCLK_RESET, reg_dual_serdes_1_cntrl);
+    dual_serdes_1_cntrl->iddq = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_CNTRL, IDDQ, reg_dual_serdes_1_cntrl);
+
+    return 0;
+}
+
+int ag_drv_lport_srds_dual_serdes_1_status_get(lport_srds_dual_serdes_1_status *dual_serdes_1_status)
+{
+    uint32_t reg_dual_serdes_1_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!dual_serdes_1_status)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+#endif
+
+    RU_REG_READ(0, LPORT_SRDS, DUAL_SERDES_1_STATUS, reg_dual_serdes_1_status);
+
+    dual_serdes_1_status->mod_def0 = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_STATUS, MOD_DEF0, reg_dual_serdes_1_status);
+    dual_serdes_1_status->ext_sig_det = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_STATUS, EXT_SIG_DET, reg_dual_serdes_1_status);
+    dual_serdes_1_status->pll_lock = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_STATUS, PLL_LOCK, reg_dual_serdes_1_status);
+    dual_serdes_1_status->link_status = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_STATUS, LINK_STATUS, reg_dual_serdes_1_status);
+    dual_serdes_1_status->cdr_lock = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_STATUS, CDR_LOCK, reg_dual_serdes_1_status);
+    dual_serdes_1_status->rx_sigdet = RU_FIELD_GET(0, LPORT_SRDS, DUAL_SERDES_1_STATUS, RX_SIGDET, reg_dual_serdes_1_status);
+
+    return 0;
+}
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_srds_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_lport_srds_ag.h
new file mode 100644
index 0000000000..6f8e39d82e
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_srds_ag.h
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_LPORT_SRDS_AG_H_
+#define _BCM6858_LPORT_SRDS_AG_H_
+
+#include "access_macros.h"
+#include "bcmtypes.h"
+typedef struct
+{
+    uint8_t serdes_test_en;
+    uint8_t serdes_ln_offset;
+    uint8_t serdes_prtad;
+    uint8_t serdes_reset;
+    uint8_t refclk_reset;
+    uint8_t iddq;
+} lport_srds_dual_serdes_0_cntrl;
+
+typedef struct
+{
+    uint8_t mod_def0;
+    uint8_t ext_sig_det;
+    uint8_t pll_lock;
+    uint8_t link_status;
+    uint8_t cdr_lock;
+    uint8_t rx_sigdet;
+} lport_srds_dual_serdes_0_status;
+
+typedef struct
+{
+    uint8_t serdes_test_en;
+    uint8_t serdes_ln_offset;
+    uint8_t serdes_prtad;
+    uint8_t serdes_reset;
+    uint8_t refclk_reset;
+    uint8_t iddq;
+} lport_srds_dual_serdes_1_cntrl;
+
+typedef struct
+{
+    uint8_t mod_def0;
+    uint8_t ext_sig_det;
+    uint8_t pll_lock;
+    uint8_t link_status;
+    uint8_t cdr_lock;
+    uint8_t rx_sigdet;
+} lport_srds_dual_serdes_1_status;
+
+int ag_drv_lport_srds_merlin_rev_get(uint16_t *serdes_rev);
+int ag_drv_lport_srds_serdes_0_indir_acc_cntrl_0_set(uint8_t err, uint8_t start_busy, uint8_t r_w, uint16_t reg_data);
+int ag_drv_lport_srds_serdes_0_indir_acc_cntrl_0_get(uint8_t *err, uint8_t *start_busy, uint8_t *r_w, uint16_t *reg_data);
+int ag_drv_lport_srds_serdes_0_indir_acc_addr_0_set(uint32_t reg_addr);
+int ag_drv_lport_srds_serdes_0_indir_acc_addr_0_get(uint32_t *reg_addr);
+int ag_drv_lport_srds_serdes_0_indir_acc_mask_0_set(uint16_t reg_mask);
+int ag_drv_lport_srds_serdes_0_indir_acc_mask_0_get(uint16_t *reg_mask);
+int ag_drv_lport_srds_serdes_0_indir_acc_cntrl_1_set(uint8_t err, uint8_t start_busy, uint8_t r_w, uint16_t reg_data);
+int ag_drv_lport_srds_serdes_0_indir_acc_cntrl_1_get(uint8_t *err, uint8_t *start_busy, uint8_t *r_w, uint16_t *reg_data);
+int ag_drv_lport_srds_serdes_0_indir_acc_addr_1_set(uint32_t reg_addr);
+int ag_drv_lport_srds_serdes_0_indir_acc_addr_1_get(uint32_t *reg_addr);
+int ag_drv_lport_srds_serdes_0_indir_acc_mask_1_set(uint16_t reg_mask);
+int ag_drv_lport_srds_serdes_0_indir_acc_mask_1_get(uint16_t *reg_mask);
+int ag_drv_lport_srds_serdes_1_indir_acc_cntrl_0_set(uint8_t err, uint8_t start_busy, uint8_t r_w, uint16_t reg_data);
+int ag_drv_lport_srds_serdes_1_indir_acc_cntrl_0_get(uint8_t *err, uint8_t *start_busy, uint8_t *r_w, uint16_t *reg_data);
+int ag_drv_lport_srds_serdes_1_indir_acc_addr_0_set(uint32_t reg_addr);
+int ag_drv_lport_srds_serdes_1_indir_acc_addr_0_get(uint32_t *reg_addr);
+int ag_drv_lport_srds_serdes_1_indir_acc_mask_0_set(uint16_t reg_mask);
+int ag_drv_lport_srds_serdes_1_indir_acc_mask_0_get(uint16_t *reg_mask);
+int ag_drv_lport_srds_serdes_1_indir_acc_cntrl_1_set(uint8_t err, uint8_t start_busy, uint8_t r_w, uint16_t reg_data);
+int ag_drv_lport_srds_serdes_1_indir_acc_cntrl_1_get(uint8_t *err, uint8_t *start_busy, uint8_t *r_w, uint16_t *reg_data);
+int ag_drv_lport_srds_serdes_1_indir_acc_addr_1_set(uint32_t reg_addr);
+int ag_drv_lport_srds_serdes_1_indir_acc_addr_1_get(uint32_t *reg_addr);
+int ag_drv_lport_srds_serdes_1_indir_acc_mask_1_set(uint16_t reg_mask);
+int ag_drv_lport_srds_serdes_1_indir_acc_mask_1_get(uint16_t *reg_mask);
+int ag_drv_lport_srds_dual_serdes_0_cntrl_set(const lport_srds_dual_serdes_0_cntrl *dual_serdes_0_cntrl);
+int ag_drv_lport_srds_dual_serdes_0_cntrl_get(lport_srds_dual_serdes_0_cntrl *dual_serdes_0_cntrl);
+int ag_drv_lport_srds_dual_serdes_0_status_get(lport_srds_dual_serdes_0_status *dual_serdes_0_status);
+int ag_drv_lport_srds_dual_serdes_1_cntrl_set(const lport_srds_dual_serdes_1_cntrl *dual_serdes_1_cntrl);
+int ag_drv_lport_srds_dual_serdes_1_cntrl_get(lport_srds_dual_serdes_1_cntrl *dual_serdes_1_cntrl);
+int ag_drv_lport_srds_dual_serdes_1_status_get(lport_srds_dual_serdes_1_status *dual_serdes_1_status);
+
+#ifdef USE_BDMF_SHELL
+bdmfmon_handle_t ag_drv_lport_srds_cli_init(bdmfmon_handle_t driver_dir);
+#endif
+
+
+#endif
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_xlmac_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_lport_xlmac_ag.c
new file mode 100644
index 0000000000..6c2968d0dc
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_xlmac_ag.c
@@ -0,0 +1,3463 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_lport_xlmac_ag.h"
+#include "xlmac_indirect_access.h"
+
+#define BLOCK_ADDR_COUNT_BITS 3
+#define BLOCK_ADDR_COUNT (1<<BLOCK_ADDR_COUNT_BITS)
+
+int ag_drv_lport_xlmac_ctrl_set(uint8_t port_id, const lport_xlmac_ctrl *ctrl)
+{
+    uint64_t reg_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (ctrl->extended_hig2_en >= _1BITS_MAX_VAL_) ||
+       (ctrl->link_status_select >= _1BITS_MAX_VAL_) ||
+       (ctrl->sw_link_status >= _1BITS_MAX_VAL_) ||
+       (ctrl->xgmii_ipg_check_disable >= _1BITS_MAX_VAL_) ||
+       (ctrl->rs_soft_reset >= _1BITS_MAX_VAL_) ||
+       (ctrl->rsvd_5 >= _1BITS_MAX_VAL_) ||
+       (ctrl->local_lpbk_leak_enb >= _1BITS_MAX_VAL_) ||
+       (ctrl->rsvd_4 >= _1BITS_MAX_VAL_) ||
+       (ctrl->soft_reset >= _1BITS_MAX_VAL_) ||
+       (ctrl->lag_failover_en >= _1BITS_MAX_VAL_) ||
+       (ctrl->remove_failover_lpbk >= _1BITS_MAX_VAL_) ||
+       (ctrl->rsvd_1 >= _1BITS_MAX_VAL_) ||
+       (ctrl->local_lpbk >= _1BITS_MAX_VAL_) ||
+       (ctrl->rx_en >= _1BITS_MAX_VAL_) ||
+       (ctrl->tx_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, EXTENDED_HIG2_EN, reg_ctrl, (uint64_t)ctrl->extended_hig2_en);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, LINK_STATUS_SELECT, reg_ctrl, (uint64_t)ctrl->link_status_select);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, SW_LINK_STATUS, reg_ctrl, (uint64_t)ctrl->sw_link_status);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, XGMII_IPG_CHECK_DISABLE, reg_ctrl, (uint64_t)ctrl->xgmii_ipg_check_disable);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, RS_SOFT_RESET, reg_ctrl, (uint64_t)ctrl->rs_soft_reset);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, RSVD_5, reg_ctrl, (uint64_t)ctrl->rsvd_5);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, LOCAL_LPBK_LEAK_ENB, reg_ctrl, (uint64_t)ctrl->local_lpbk_leak_enb);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, RSVD_4, reg_ctrl, (uint64_t)ctrl->rsvd_4);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, SOFT_RESET, reg_ctrl, (uint64_t)ctrl->soft_reset);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, LAG_FAILOVER_EN, reg_ctrl, (uint64_t)ctrl->lag_failover_en);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, REMOVE_FAILOVER_LPBK, reg_ctrl, (uint64_t)ctrl->remove_failover_lpbk);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, RSVD_1, reg_ctrl, (uint64_t)ctrl->rsvd_1);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, LOCAL_LPBK, reg_ctrl, (uint64_t)ctrl->local_lpbk);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, RX_EN, reg_ctrl, (uint64_t)ctrl->rx_en);
+    reg_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, CTRL, TX_EN, reg_ctrl, (uint64_t)ctrl->tx_en);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, CTRL, reg_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_ctrl_get(uint8_t port_id, lport_xlmac_ctrl *ctrl)
+{
+    uint64_t reg_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, CTRL, reg_ctrl);
+
+    ctrl->extended_hig2_en = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, EXTENDED_HIG2_EN, reg_ctrl);
+    ctrl->link_status_select = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, LINK_STATUS_SELECT, reg_ctrl);
+    ctrl->sw_link_status = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, SW_LINK_STATUS, reg_ctrl);
+    ctrl->xgmii_ipg_check_disable = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, XGMII_IPG_CHECK_DISABLE, reg_ctrl);
+    ctrl->rs_soft_reset = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, RS_SOFT_RESET, reg_ctrl);
+    ctrl->rsvd_5 = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, RSVD_5, reg_ctrl);
+    ctrl->local_lpbk_leak_enb = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, LOCAL_LPBK_LEAK_ENB, reg_ctrl);
+    ctrl->rsvd_4 = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, RSVD_4, reg_ctrl);
+    ctrl->soft_reset = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, SOFT_RESET, reg_ctrl);
+    ctrl->lag_failover_en = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, LAG_FAILOVER_EN, reg_ctrl);
+    ctrl->remove_failover_lpbk = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, REMOVE_FAILOVER_LPBK, reg_ctrl);
+    ctrl->rsvd_1 = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, RSVD_1, reg_ctrl);
+    ctrl->local_lpbk = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, LOCAL_LPBK, reg_ctrl);
+    ctrl->rx_en = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, RX_EN, reg_ctrl);
+    ctrl->tx_en = RU_FIELD_GET(port_id, LPORT_XLMAC, CTRL, TX_EN, reg_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_mode_set(uint8_t port_id, uint8_t speed_mode, uint8_t no_sop_for_crc_hg, uint8_t hdr_mode)
+{
+    uint64_t reg_mode=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (speed_mode >= _3BITS_MAX_VAL_) ||
+       (no_sop_for_crc_hg >= _1BITS_MAX_VAL_) ||
+       (hdr_mode >= _3BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_mode = RU_FIELD_SET(port_id, LPORT_XLMAC, MODE, SPEED_MODE, reg_mode, (uint64_t)speed_mode);
+    reg_mode = RU_FIELD_SET(port_id, LPORT_XLMAC, MODE, NO_SOP_FOR_CRC_HG, reg_mode, (uint64_t)no_sop_for_crc_hg);
+    reg_mode = RU_FIELD_SET(port_id, LPORT_XLMAC, MODE, HDR_MODE, reg_mode, (uint64_t)hdr_mode);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, MODE, reg_mode);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_mode_get(uint8_t port_id, uint8_t *speed_mode, uint8_t *no_sop_for_crc_hg, uint8_t *hdr_mode)
+{
+    uint64_t reg_mode=0;
+
+#ifdef VALIDATE_PARMS
+    if(!speed_mode || !no_sop_for_crc_hg || !hdr_mode)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, MODE, reg_mode);
+
+    *speed_mode = RU_FIELD_GET(port_id, LPORT_XLMAC, MODE, SPEED_MODE, reg_mode);
+    *no_sop_for_crc_hg = RU_FIELD_GET(port_id, LPORT_XLMAC, MODE, NO_SOP_FOR_CRC_HG, reg_mode);
+    *hdr_mode = RU_FIELD_GET(port_id, LPORT_XLMAC, MODE, HDR_MODE, reg_mode);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_spare0_set(uint8_t port_id, uint32_t rsvd)
+{
+    uint64_t reg_spare0=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_spare0 = RU_FIELD_SET(port_id, LPORT_XLMAC, SPARE0, RSVD, reg_spare0, (uint64_t)rsvd);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, SPARE0, reg_spare0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_spare0_get(uint8_t port_id, uint32_t *rsvd)
+{
+    uint64_t reg_spare0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rsvd)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, SPARE0, reg_spare0);
+
+    *rsvd = RU_FIELD_GET(port_id, LPORT_XLMAC, SPARE0, RSVD, reg_spare0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_spare1_set(uint8_t port_id, uint8_t rsvd)
+{
+    uint64_t reg_spare1=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (rsvd >= _2BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_spare1 = RU_FIELD_SET(port_id, LPORT_XLMAC, SPARE1, RSVD, reg_spare1, (uint64_t)rsvd);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, SPARE1, reg_spare1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_spare1_get(uint8_t port_id, uint8_t *rsvd)
+{
+    uint64_t reg_spare1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rsvd)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, SPARE1, reg_spare1);
+
+    *rsvd = RU_FIELD_GET(port_id, LPORT_XLMAC, SPARE1, RSVD, reg_spare1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_ctrl_set(uint8_t port_id, const lport_xlmac_tx_ctrl *tx_ctrl)
+{
+    uint64_t reg_tx_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (tx_ctrl->tx_threshold >= _4BITS_MAX_VAL_) ||
+       (tx_ctrl->ep_discard >= _1BITS_MAX_VAL_) ||
+       (tx_ctrl->tx_preamble_length >= _4BITS_MAX_VAL_) ||
+       (tx_ctrl->throt_num >= _6BITS_MAX_VAL_) ||
+       (tx_ctrl->average_ipg >= _7BITS_MAX_VAL_) ||
+       (tx_ctrl->pad_threshold >= _7BITS_MAX_VAL_) ||
+       (tx_ctrl->pad_en >= _1BITS_MAX_VAL_) ||
+       (tx_ctrl->tx_any_start >= _1BITS_MAX_VAL_) ||
+       (tx_ctrl->discard >= _1BITS_MAX_VAL_) ||
+       (tx_ctrl->crc_mode >= _2BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_tx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL, TX_THRESHOLD, reg_tx_ctrl, (uint64_t)tx_ctrl->tx_threshold);
+    reg_tx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL, EP_DISCARD, reg_tx_ctrl, (uint64_t)tx_ctrl->ep_discard);
+    reg_tx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL, TX_PREAMBLE_LENGTH, reg_tx_ctrl, (uint64_t)tx_ctrl->tx_preamble_length);
+    reg_tx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL, THROT_DENOM, reg_tx_ctrl, (uint64_t)tx_ctrl->throt_denom);
+    reg_tx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL, THROT_NUM, reg_tx_ctrl, (uint64_t)tx_ctrl->throt_num);
+    reg_tx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL, AVERAGE_IPG, reg_tx_ctrl, (uint64_t)tx_ctrl->average_ipg);
+    reg_tx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL, PAD_THRESHOLD, reg_tx_ctrl, (uint64_t)tx_ctrl->pad_threshold);
+    reg_tx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL, PAD_EN, reg_tx_ctrl, (uint64_t)tx_ctrl->pad_en);
+    reg_tx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL, TX_ANY_START, reg_tx_ctrl, (uint64_t)tx_ctrl->tx_any_start);
+    reg_tx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL, DISCARD, reg_tx_ctrl, (uint64_t)tx_ctrl->discard);
+    reg_tx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL, CRC_MODE, reg_tx_ctrl, (uint64_t)tx_ctrl->crc_mode);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, TX_CTRL, reg_tx_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_ctrl_get(uint8_t port_id, lport_xlmac_tx_ctrl *tx_ctrl)
+{
+    uint64_t reg_tx_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TX_CTRL, reg_tx_ctrl);
+
+    tx_ctrl->tx_threshold = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL, TX_THRESHOLD, reg_tx_ctrl);
+    tx_ctrl->ep_discard = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL, EP_DISCARD, reg_tx_ctrl);
+    tx_ctrl->tx_preamble_length = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL, TX_PREAMBLE_LENGTH, reg_tx_ctrl);
+    tx_ctrl->throt_denom = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL, THROT_DENOM, reg_tx_ctrl);
+    tx_ctrl->throt_num = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL, THROT_NUM, reg_tx_ctrl);
+    tx_ctrl->average_ipg = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL, AVERAGE_IPG, reg_tx_ctrl);
+    tx_ctrl->pad_threshold = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL, PAD_THRESHOLD, reg_tx_ctrl);
+    tx_ctrl->pad_en = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL, PAD_EN, reg_tx_ctrl);
+    tx_ctrl->tx_any_start = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL, TX_ANY_START, reg_tx_ctrl);
+    tx_ctrl->discard = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL, DISCARD, reg_tx_ctrl);
+    tx_ctrl->crc_mode = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL, CRC_MODE, reg_tx_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_ctrl_overlay_set(uint8_t port_id, uint16_t xlmac_tx_ctrl_hi, uint32_t xlmac_tx_ctrl_lo)
+{
+    uint64_t reg_tx_ctrl_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (xlmac_tx_ctrl_hi >= _10BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_tx_ctrl_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL_OVERLAY, XLMAC_TX_CTRL_HI, reg_tx_ctrl_overlay, (uint64_t)xlmac_tx_ctrl_hi);
+    reg_tx_ctrl_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CTRL_OVERLAY, XLMAC_TX_CTRL_LO, reg_tx_ctrl_overlay, (uint64_t)xlmac_tx_ctrl_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, TX_CTRL_OVERLAY, reg_tx_ctrl_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_ctrl_overlay_get(uint8_t port_id, uint16_t *xlmac_tx_ctrl_hi, uint32_t *xlmac_tx_ctrl_lo)
+{
+    uint64_t reg_tx_ctrl_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!xlmac_tx_ctrl_hi || !xlmac_tx_ctrl_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TX_CTRL_OVERLAY, reg_tx_ctrl_overlay);
+
+    *xlmac_tx_ctrl_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL_OVERLAY, XLMAC_TX_CTRL_HI, reg_tx_ctrl_overlay);
+    *xlmac_tx_ctrl_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CTRL_OVERLAY, XLMAC_TX_CTRL_LO, reg_tx_ctrl_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_mac_sa_set(uint8_t port_id, uint64_t ctrl_sa)
+{
+    uint64_t reg_tx_mac_sa=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (ctrl_sa >= _48BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_tx_mac_sa = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_MAC_SA, CTRL_SA, reg_tx_mac_sa, (uint64_t)ctrl_sa);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, TX_MAC_SA, reg_tx_mac_sa);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_mac_sa_get(uint8_t port_id, uint64_t *ctrl_sa)
+{
+    uint64_t reg_tx_mac_sa=0;
+
+#ifdef VALIDATE_PARMS
+    if(!ctrl_sa)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TX_MAC_SA, reg_tx_mac_sa);
+
+    *ctrl_sa = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_MAC_SA, CTRL_SA, reg_tx_mac_sa);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_mac_sa_overlay_set(uint8_t port_id, uint16_t sa_hi, uint32_t sa_lo)
+{
+    uint64_t reg_tx_mac_sa_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_tx_mac_sa_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_MAC_SA_OVERLAY, SA_HI, reg_tx_mac_sa_overlay, (uint64_t)sa_hi);
+    reg_tx_mac_sa_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_MAC_SA_OVERLAY, SA_LO, reg_tx_mac_sa_overlay, (uint64_t)sa_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, TX_MAC_SA_OVERLAY, reg_tx_mac_sa_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_mac_sa_overlay_get(uint8_t port_id, uint16_t *sa_hi, uint32_t *sa_lo)
+{
+    uint64_t reg_tx_mac_sa_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!sa_hi || !sa_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TX_MAC_SA_OVERLAY, reg_tx_mac_sa_overlay);
+
+    *sa_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_MAC_SA_OVERLAY, SA_HI, reg_tx_mac_sa_overlay);
+    *sa_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_MAC_SA_OVERLAY, SA_LO, reg_tx_mac_sa_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_ctrl_set(uint8_t port_id, const lport_xlmac_rx_ctrl *rx_ctrl)
+{
+    uint64_t reg_rx_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (rx_ctrl->rx_pass_pfc >= _1BITS_MAX_VAL_) ||
+       (rx_ctrl->rx_pass_pause >= _1BITS_MAX_VAL_) ||
+       (rx_ctrl->rx_pass_ctrl >= _1BITS_MAX_VAL_) ||
+       (rx_ctrl->rsvd_3 >= _1BITS_MAX_VAL_) ||
+       (rx_ctrl->rsvd_2 >= _1BITS_MAX_VAL_) ||
+       (rx_ctrl->runt_threshold >= _7BITS_MAX_VAL_) ||
+       (rx_ctrl->strict_preamble >= _1BITS_MAX_VAL_) ||
+       (rx_ctrl->strip_crc >= _1BITS_MAX_VAL_) ||
+       (rx_ctrl->rx_any_start >= _1BITS_MAX_VAL_) ||
+       (rx_ctrl->rsvd_1 >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_rx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_CTRL, RX_PASS_PFC, reg_rx_ctrl, (uint64_t)rx_ctrl->rx_pass_pfc);
+    reg_rx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_CTRL, RX_PASS_PAUSE, reg_rx_ctrl, (uint64_t)rx_ctrl->rx_pass_pause);
+    reg_rx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_CTRL, RX_PASS_CTRL, reg_rx_ctrl, (uint64_t)rx_ctrl->rx_pass_ctrl);
+    reg_rx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_CTRL, RSVD_3, reg_rx_ctrl, (uint64_t)rx_ctrl->rsvd_3);
+    reg_rx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_CTRL, RSVD_2, reg_rx_ctrl, (uint64_t)rx_ctrl->rsvd_2);
+    reg_rx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_CTRL, RUNT_THRESHOLD, reg_rx_ctrl, (uint64_t)rx_ctrl->runt_threshold);
+    reg_rx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_CTRL, STRICT_PREAMBLE, reg_rx_ctrl, (uint64_t)rx_ctrl->strict_preamble);
+    reg_rx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_CTRL, STRIP_CRC, reg_rx_ctrl, (uint64_t)rx_ctrl->strip_crc);
+    reg_rx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_CTRL, RX_ANY_START, reg_rx_ctrl, (uint64_t)rx_ctrl->rx_any_start);
+    reg_rx_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_CTRL, RSVD_1, reg_rx_ctrl, (uint64_t)rx_ctrl->rsvd_1);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, RX_CTRL, reg_rx_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_ctrl_get(uint8_t port_id, lport_xlmac_rx_ctrl *rx_ctrl)
+{
+    uint64_t reg_rx_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, RX_CTRL, reg_rx_ctrl);
+
+    rx_ctrl->rx_pass_pfc = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CTRL, RX_PASS_PFC, reg_rx_ctrl);
+    rx_ctrl->rx_pass_pause = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CTRL, RX_PASS_PAUSE, reg_rx_ctrl);
+    rx_ctrl->rx_pass_ctrl = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CTRL, RX_PASS_CTRL, reg_rx_ctrl);
+    rx_ctrl->rsvd_3 = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CTRL, RSVD_3, reg_rx_ctrl);
+    rx_ctrl->rsvd_2 = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CTRL, RSVD_2, reg_rx_ctrl);
+    rx_ctrl->runt_threshold = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CTRL, RUNT_THRESHOLD, reg_rx_ctrl);
+    rx_ctrl->strict_preamble = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CTRL, STRICT_PREAMBLE, reg_rx_ctrl);
+    rx_ctrl->strip_crc = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CTRL, STRIP_CRC, reg_rx_ctrl);
+    rx_ctrl->rx_any_start = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CTRL, RX_ANY_START, reg_rx_ctrl);
+    rx_ctrl->rsvd_1 = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CTRL, RSVD_1, reg_rx_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_mac_sa_set(uint8_t port_id, uint64_t rx_sa)
+{
+    uint64_t reg_rx_mac_sa=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (rx_sa >= _48BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_rx_mac_sa = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_MAC_SA, RX_SA, reg_rx_mac_sa, (uint64_t)rx_sa);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, RX_MAC_SA, reg_rx_mac_sa);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_mac_sa_get(uint8_t port_id, uint64_t *rx_sa)
+{
+    uint64_t reg_rx_mac_sa=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_sa)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, RX_MAC_SA, reg_rx_mac_sa);
+
+    *rx_sa = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_MAC_SA, RX_SA, reg_rx_mac_sa);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_mac_sa_overlay_set(uint8_t port_id, uint16_t sa_hi, uint32_t sa_lo)
+{
+    uint64_t reg_rx_mac_sa_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_rx_mac_sa_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_MAC_SA_OVERLAY, SA_HI, reg_rx_mac_sa_overlay, (uint64_t)sa_hi);
+    reg_rx_mac_sa_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_MAC_SA_OVERLAY, SA_LO, reg_rx_mac_sa_overlay, (uint64_t)sa_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, RX_MAC_SA_OVERLAY, reg_rx_mac_sa_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_mac_sa_overlay_get(uint8_t port_id, uint16_t *sa_hi, uint32_t *sa_lo)
+{
+    uint64_t reg_rx_mac_sa_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!sa_hi || !sa_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, RX_MAC_SA_OVERLAY, reg_rx_mac_sa_overlay);
+
+    *sa_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_MAC_SA_OVERLAY, SA_HI, reg_rx_mac_sa_overlay);
+    *sa_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_MAC_SA_OVERLAY, SA_LO, reg_rx_mac_sa_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_max_size_set(uint8_t port_id, uint16_t rx_max_size)
+{
+    uint64_t reg_rx_max_size=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (rx_max_size >= _14BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_rx_max_size = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_MAX_SIZE, RX_MAX_SIZE, reg_rx_max_size, (uint64_t)rx_max_size);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, RX_MAX_SIZE, reg_rx_max_size);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_max_size_get(uint8_t port_id, uint16_t *rx_max_size)
+{
+    uint64_t reg_rx_max_size=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_max_size)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, RX_MAX_SIZE, reg_rx_max_size);
+
+    *rx_max_size = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_MAX_SIZE, RX_MAX_SIZE, reg_rx_max_size);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_vlan_tag_set(uint8_t port_id, uint8_t outer_vlan_tag_enable, uint8_t inner_vlan_tag_enable, uint16_t outer_vlan_tag, uint16_t inner_vlan_tag)
+{
+    uint64_t reg_rx_vlan_tag=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (outer_vlan_tag_enable >= _1BITS_MAX_VAL_) ||
+       (inner_vlan_tag_enable >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_rx_vlan_tag = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_VLAN_TAG, OUTER_VLAN_TAG_ENABLE, reg_rx_vlan_tag, (uint64_t)outer_vlan_tag_enable);
+    reg_rx_vlan_tag = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_VLAN_TAG, INNER_VLAN_TAG_ENABLE, reg_rx_vlan_tag, (uint64_t)inner_vlan_tag_enable);
+    reg_rx_vlan_tag = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_VLAN_TAG, OUTER_VLAN_TAG, reg_rx_vlan_tag, (uint64_t)outer_vlan_tag);
+    reg_rx_vlan_tag = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_VLAN_TAG, INNER_VLAN_TAG, reg_rx_vlan_tag, (uint64_t)inner_vlan_tag);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, RX_VLAN_TAG, reg_rx_vlan_tag);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_vlan_tag_get(uint8_t port_id, uint8_t *outer_vlan_tag_enable, uint8_t *inner_vlan_tag_enable, uint16_t *outer_vlan_tag, uint16_t *inner_vlan_tag)
+{
+    uint64_t reg_rx_vlan_tag=0;
+
+#ifdef VALIDATE_PARMS
+    if(!outer_vlan_tag_enable || !inner_vlan_tag_enable || !outer_vlan_tag || !inner_vlan_tag)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, RX_VLAN_TAG, reg_rx_vlan_tag);
+
+    *outer_vlan_tag_enable = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_VLAN_TAG, OUTER_VLAN_TAG_ENABLE, reg_rx_vlan_tag);
+    *inner_vlan_tag_enable = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_VLAN_TAG, INNER_VLAN_TAG_ENABLE, reg_rx_vlan_tag);
+    *outer_vlan_tag = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_VLAN_TAG, OUTER_VLAN_TAG, reg_rx_vlan_tag);
+    *inner_vlan_tag = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_VLAN_TAG, INNER_VLAN_TAG, reg_rx_vlan_tag);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_lss_ctrl_set(uint8_t port_id, const lport_xlmac_rx_lss_ctrl *rx_lss_ctrl)
+{
+    uint64_t reg_rx_lss_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_lss_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (rx_lss_ctrl->reset_flow_control_timers_on_link_down >= _1BITS_MAX_VAL_) ||
+       (rx_lss_ctrl->drop_tx_data_on_link_interrupt >= _1BITS_MAX_VAL_) ||
+       (rx_lss_ctrl->drop_tx_data_on_remote_fault >= _1BITS_MAX_VAL_) ||
+       (rx_lss_ctrl->drop_tx_data_on_local_fault >= _1BITS_MAX_VAL_) ||
+       (rx_lss_ctrl->link_interruption_disable >= _1BITS_MAX_VAL_) ||
+       (rx_lss_ctrl->use_external_faults_for_tx >= _1BITS_MAX_VAL_) ||
+       (rx_lss_ctrl->remote_fault_disable >= _1BITS_MAX_VAL_) ||
+       (rx_lss_ctrl->local_fault_disable >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_rx_lss_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LSS_CTRL, RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN, reg_rx_lss_ctrl, (uint64_t)rx_lss_ctrl->reset_flow_control_timers_on_link_down);
+    reg_rx_lss_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LSS_CTRL, DROP_TX_DATA_ON_LINK_INTERRUPT, reg_rx_lss_ctrl, (uint64_t)rx_lss_ctrl->drop_tx_data_on_link_interrupt);
+    reg_rx_lss_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LSS_CTRL, DROP_TX_DATA_ON_REMOTE_FAULT, reg_rx_lss_ctrl, (uint64_t)rx_lss_ctrl->drop_tx_data_on_remote_fault);
+    reg_rx_lss_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LSS_CTRL, DROP_TX_DATA_ON_LOCAL_FAULT, reg_rx_lss_ctrl, (uint64_t)rx_lss_ctrl->drop_tx_data_on_local_fault);
+    reg_rx_lss_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LSS_CTRL, LINK_INTERRUPTION_DISABLE, reg_rx_lss_ctrl, (uint64_t)rx_lss_ctrl->link_interruption_disable);
+    reg_rx_lss_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LSS_CTRL, USE_EXTERNAL_FAULTS_FOR_TX, reg_rx_lss_ctrl, (uint64_t)rx_lss_ctrl->use_external_faults_for_tx);
+    reg_rx_lss_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LSS_CTRL, REMOTE_FAULT_DISABLE, reg_rx_lss_ctrl, (uint64_t)rx_lss_ctrl->remote_fault_disable);
+    reg_rx_lss_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LSS_CTRL, LOCAL_FAULT_DISABLE, reg_rx_lss_ctrl, (uint64_t)rx_lss_ctrl->local_fault_disable);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, RX_LSS_CTRL, reg_rx_lss_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_lss_ctrl_get(uint8_t port_id, lport_xlmac_rx_lss_ctrl *rx_lss_ctrl)
+{
+    uint64_t reg_rx_lss_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_lss_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, RX_LSS_CTRL, reg_rx_lss_ctrl);
+
+    rx_lss_ctrl->reset_flow_control_timers_on_link_down = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LSS_CTRL, RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN, reg_rx_lss_ctrl);
+    rx_lss_ctrl->drop_tx_data_on_link_interrupt = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LSS_CTRL, DROP_TX_DATA_ON_LINK_INTERRUPT, reg_rx_lss_ctrl);
+    rx_lss_ctrl->drop_tx_data_on_remote_fault = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LSS_CTRL, DROP_TX_DATA_ON_REMOTE_FAULT, reg_rx_lss_ctrl);
+    rx_lss_ctrl->drop_tx_data_on_local_fault = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LSS_CTRL, DROP_TX_DATA_ON_LOCAL_FAULT, reg_rx_lss_ctrl);
+    rx_lss_ctrl->link_interruption_disable = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LSS_CTRL, LINK_INTERRUPTION_DISABLE, reg_rx_lss_ctrl);
+    rx_lss_ctrl->use_external_faults_for_tx = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LSS_CTRL, USE_EXTERNAL_FAULTS_FOR_TX, reg_rx_lss_ctrl);
+    rx_lss_ctrl->remote_fault_disable = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LSS_CTRL, REMOTE_FAULT_DISABLE, reg_rx_lss_ctrl);
+    rx_lss_ctrl->local_fault_disable = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LSS_CTRL, LOCAL_FAULT_DISABLE, reg_rx_lss_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_lss_status_get(uint8_t port_id, uint8_t *link_interruption_status, uint8_t *remote_fault_status, uint8_t *local_fault_status)
+{
+    uint64_t reg_rx_lss_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!link_interruption_status || !remote_fault_status || !local_fault_status)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, RX_LSS_STATUS, reg_rx_lss_status);
+
+    *link_interruption_status = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LSS_STATUS, LINK_INTERRUPTION_STATUS, reg_rx_lss_status);
+    *remote_fault_status = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LSS_STATUS, REMOTE_FAULT_STATUS, reg_rx_lss_status);
+    *local_fault_status = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LSS_STATUS, LOCAL_FAULT_STATUS, reg_rx_lss_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_clear_rx_lss_status_set(uint8_t port_id, uint8_t clear_link_interruption_status, uint8_t clear_remote_fault_status, uint8_t clear_local_fault_status)
+{
+    uint64_t reg_clear_rx_lss_status=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (clear_link_interruption_status >= _1BITS_MAX_VAL_) ||
+       (clear_remote_fault_status >= _1BITS_MAX_VAL_) ||
+       (clear_local_fault_status >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_clear_rx_lss_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_RX_LSS_STATUS, CLEAR_LINK_INTERRUPTION_STATUS, reg_clear_rx_lss_status, (uint64_t)clear_link_interruption_status);
+    reg_clear_rx_lss_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_RX_LSS_STATUS, CLEAR_REMOTE_FAULT_STATUS, reg_clear_rx_lss_status, (uint64_t)clear_remote_fault_status);
+    reg_clear_rx_lss_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_RX_LSS_STATUS, CLEAR_LOCAL_FAULT_STATUS, reg_clear_rx_lss_status, (uint64_t)clear_local_fault_status);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, CLEAR_RX_LSS_STATUS, reg_clear_rx_lss_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_clear_rx_lss_status_get(uint8_t port_id, uint8_t *clear_link_interruption_status, uint8_t *clear_remote_fault_status, uint8_t *clear_local_fault_status)
+{
+    uint64_t reg_clear_rx_lss_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!clear_link_interruption_status || !clear_remote_fault_status || !clear_local_fault_status)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, CLEAR_RX_LSS_STATUS, reg_clear_rx_lss_status);
+
+    *clear_link_interruption_status = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_RX_LSS_STATUS, CLEAR_LINK_INTERRUPTION_STATUS, reg_clear_rx_lss_status);
+    *clear_remote_fault_status = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_RX_LSS_STATUS, CLEAR_REMOTE_FAULT_STATUS, reg_clear_rx_lss_status);
+    *clear_local_fault_status = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_RX_LSS_STATUS, CLEAR_LOCAL_FAULT_STATUS, reg_clear_rx_lss_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pause_ctrl_set(uint8_t port_id, const lport_xlmac_pause_ctrl *pause_ctrl)
+{
+    uint64_t reg_pause_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!pause_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (pause_ctrl->rsvd_2 >= _1BITS_MAX_VAL_) ||
+       (pause_ctrl->rsvd_1 >= _1BITS_MAX_VAL_) ||
+       (pause_ctrl->rx_pause_en >= _1BITS_MAX_VAL_) ||
+       (pause_ctrl->tx_pause_en >= _1BITS_MAX_VAL_) ||
+       (pause_ctrl->pause_refresh_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_pause_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PAUSE_CTRL, PAUSE_XOFF_TIMER, reg_pause_ctrl, (uint64_t)pause_ctrl->pause_xoff_timer);
+    reg_pause_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PAUSE_CTRL, RSVD_2, reg_pause_ctrl, (uint64_t)pause_ctrl->rsvd_2);
+    reg_pause_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PAUSE_CTRL, RSVD_1, reg_pause_ctrl, (uint64_t)pause_ctrl->rsvd_1);
+    reg_pause_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PAUSE_CTRL, RX_PAUSE_EN, reg_pause_ctrl, (uint64_t)pause_ctrl->rx_pause_en);
+    reg_pause_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PAUSE_CTRL, TX_PAUSE_EN, reg_pause_ctrl, (uint64_t)pause_ctrl->tx_pause_en);
+    reg_pause_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PAUSE_CTRL, PAUSE_REFRESH_EN, reg_pause_ctrl, (uint64_t)pause_ctrl->pause_refresh_en);
+    reg_pause_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PAUSE_CTRL, PAUSE_REFRESH_TIMER, reg_pause_ctrl, (uint64_t)pause_ctrl->pause_refresh_timer);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, PAUSE_CTRL, reg_pause_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pause_ctrl_get(uint8_t port_id, lport_xlmac_pause_ctrl *pause_ctrl)
+{
+    uint64_t reg_pause_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!pause_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, PAUSE_CTRL, reg_pause_ctrl);
+
+    pause_ctrl->pause_xoff_timer = RU_FIELD_GET(port_id, LPORT_XLMAC, PAUSE_CTRL, PAUSE_XOFF_TIMER, reg_pause_ctrl);
+    pause_ctrl->rsvd_2 = RU_FIELD_GET(port_id, LPORT_XLMAC, PAUSE_CTRL, RSVD_2, reg_pause_ctrl);
+    pause_ctrl->rsvd_1 = RU_FIELD_GET(port_id, LPORT_XLMAC, PAUSE_CTRL, RSVD_1, reg_pause_ctrl);
+    pause_ctrl->rx_pause_en = RU_FIELD_GET(port_id, LPORT_XLMAC, PAUSE_CTRL, RX_PAUSE_EN, reg_pause_ctrl);
+    pause_ctrl->tx_pause_en = RU_FIELD_GET(port_id, LPORT_XLMAC, PAUSE_CTRL, TX_PAUSE_EN, reg_pause_ctrl);
+    pause_ctrl->pause_refresh_en = RU_FIELD_GET(port_id, LPORT_XLMAC, PAUSE_CTRL, PAUSE_REFRESH_EN, reg_pause_ctrl);
+    pause_ctrl->pause_refresh_timer = RU_FIELD_GET(port_id, LPORT_XLMAC, PAUSE_CTRL, PAUSE_REFRESH_TIMER, reg_pause_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pause_ctrl_overlay_set(uint8_t port_id, uint8_t xlmac_pause_ctrl_hi, uint32_t xlmac_pause_ctrl_lo)
+{
+    uint64_t reg_pause_ctrl_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (xlmac_pause_ctrl_hi >= _5BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_pause_ctrl_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, PAUSE_CTRL_OVERLAY, XLMAC_PAUSE_CTRL_HI, reg_pause_ctrl_overlay, (uint64_t)xlmac_pause_ctrl_hi);
+    reg_pause_ctrl_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, PAUSE_CTRL_OVERLAY, XLMAC_PAUSE_CTRL_LO, reg_pause_ctrl_overlay, (uint64_t)xlmac_pause_ctrl_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, PAUSE_CTRL_OVERLAY, reg_pause_ctrl_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pause_ctrl_overlay_get(uint8_t port_id, uint8_t *xlmac_pause_ctrl_hi, uint32_t *xlmac_pause_ctrl_lo)
+{
+    uint64_t reg_pause_ctrl_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!xlmac_pause_ctrl_hi || !xlmac_pause_ctrl_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, PAUSE_CTRL_OVERLAY, reg_pause_ctrl_overlay);
+
+    *xlmac_pause_ctrl_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, PAUSE_CTRL_OVERLAY, XLMAC_PAUSE_CTRL_HI, reg_pause_ctrl_overlay);
+    *xlmac_pause_ctrl_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, PAUSE_CTRL_OVERLAY, XLMAC_PAUSE_CTRL_LO, reg_pause_ctrl_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_ctrl_set(uint8_t port_id, const lport_xlmac_pfc_ctrl *pfc_ctrl)
+{
+    uint64_t reg_pfc_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!pfc_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (pfc_ctrl->tx_pfc_en >= _1BITS_MAX_VAL_) ||
+       (pfc_ctrl->rx_pfc_en >= _1BITS_MAX_VAL_) ||
+       (pfc_ctrl->pfc_stats_en >= _1BITS_MAX_VAL_) ||
+       (pfc_ctrl->rsvd >= _1BITS_MAX_VAL_) ||
+       (pfc_ctrl->force_pfc_xon >= _1BITS_MAX_VAL_) ||
+       (pfc_ctrl->pfc_refresh_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_pfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_CTRL, TX_PFC_EN, reg_pfc_ctrl, (uint64_t)pfc_ctrl->tx_pfc_en);
+    reg_pfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_CTRL, RX_PFC_EN, reg_pfc_ctrl, (uint64_t)pfc_ctrl->rx_pfc_en);
+    reg_pfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_CTRL, PFC_STATS_EN, reg_pfc_ctrl, (uint64_t)pfc_ctrl->pfc_stats_en);
+    reg_pfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_CTRL, RSVD, reg_pfc_ctrl, (uint64_t)pfc_ctrl->rsvd);
+    reg_pfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_CTRL, FORCE_PFC_XON, reg_pfc_ctrl, (uint64_t)pfc_ctrl->force_pfc_xon);
+    reg_pfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_CTRL, PFC_REFRESH_EN, reg_pfc_ctrl, (uint64_t)pfc_ctrl->pfc_refresh_en);
+    reg_pfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_CTRL, PFC_XOFF_TIMER, reg_pfc_ctrl, (uint64_t)pfc_ctrl->pfc_xoff_timer);
+    reg_pfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_CTRL, PFC_REFRESH_TIMER, reg_pfc_ctrl, (uint64_t)pfc_ctrl->pfc_refresh_timer);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, PFC_CTRL, reg_pfc_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_ctrl_get(uint8_t port_id, lport_xlmac_pfc_ctrl *pfc_ctrl)
+{
+    uint64_t reg_pfc_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!pfc_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, PFC_CTRL, reg_pfc_ctrl);
+
+    pfc_ctrl->tx_pfc_en = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_CTRL, TX_PFC_EN, reg_pfc_ctrl);
+    pfc_ctrl->rx_pfc_en = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_CTRL, RX_PFC_EN, reg_pfc_ctrl);
+    pfc_ctrl->pfc_stats_en = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_CTRL, PFC_STATS_EN, reg_pfc_ctrl);
+    pfc_ctrl->rsvd = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_CTRL, RSVD, reg_pfc_ctrl);
+    pfc_ctrl->force_pfc_xon = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_CTRL, FORCE_PFC_XON, reg_pfc_ctrl);
+    pfc_ctrl->pfc_refresh_en = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_CTRL, PFC_REFRESH_EN, reg_pfc_ctrl);
+    pfc_ctrl->pfc_xoff_timer = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_CTRL, PFC_XOFF_TIMER, reg_pfc_ctrl);
+    pfc_ctrl->pfc_refresh_timer = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_CTRL, PFC_REFRESH_TIMER, reg_pfc_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_ctrl_overlay_set(uint8_t port_id, uint8_t llfc_refresh_en, uint16_t llfc_refresh_timer)
+{
+    uint64_t reg_pfc_ctrl_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (llfc_refresh_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_pfc_ctrl_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_CTRL_OVERLAY, LLFC_REFRESH_EN, reg_pfc_ctrl_overlay, (uint64_t)llfc_refresh_en);
+    reg_pfc_ctrl_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_CTRL_OVERLAY, LLFC_REFRESH_TIMER, reg_pfc_ctrl_overlay, (uint64_t)llfc_refresh_timer);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, PFC_CTRL_OVERLAY, reg_pfc_ctrl_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_ctrl_overlay_get(uint8_t port_id, uint8_t *llfc_refresh_en, uint16_t *llfc_refresh_timer)
+{
+    uint64_t reg_pfc_ctrl_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!llfc_refresh_en || !llfc_refresh_timer)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, PFC_CTRL_OVERLAY, reg_pfc_ctrl_overlay);
+
+    *llfc_refresh_en = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_CTRL_OVERLAY, LLFC_REFRESH_EN, reg_pfc_ctrl_overlay);
+    *llfc_refresh_timer = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_CTRL_OVERLAY, LLFC_REFRESH_TIMER, reg_pfc_ctrl_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_type_set(uint8_t port_id, uint16_t pfc_eth_type)
+{
+    uint64_t reg_pfc_type=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_pfc_type = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_TYPE, PFC_ETH_TYPE, reg_pfc_type, (uint64_t)pfc_eth_type);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, PFC_TYPE, reg_pfc_type);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_type_get(uint8_t port_id, uint16_t *pfc_eth_type)
+{
+    uint64_t reg_pfc_type=0;
+
+#ifdef VALIDATE_PARMS
+    if(!pfc_eth_type)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, PFC_TYPE, reg_pfc_type);
+
+    *pfc_eth_type = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_TYPE, PFC_ETH_TYPE, reg_pfc_type);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_opcode_set(uint8_t port_id, uint16_t pfc_opcode)
+{
+    uint64_t reg_pfc_opcode=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_pfc_opcode = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_OPCODE, PFC_OPCODE, reg_pfc_opcode, (uint64_t)pfc_opcode);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, PFC_OPCODE, reg_pfc_opcode);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_opcode_get(uint8_t port_id, uint16_t *pfc_opcode)
+{
+    uint64_t reg_pfc_opcode=0;
+
+#ifdef VALIDATE_PARMS
+    if(!pfc_opcode)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, PFC_OPCODE, reg_pfc_opcode);
+
+    *pfc_opcode = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_OPCODE, PFC_OPCODE, reg_pfc_opcode);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_da_set(uint8_t port_id, uint64_t pfc_macda)
+{
+    uint64_t reg_pfc_da=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (pfc_macda >= _48BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_pfc_da = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_DA, PFC_MACDA, reg_pfc_da, (uint64_t)pfc_macda);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, PFC_DA, reg_pfc_da);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_da_get(uint8_t port_id, uint64_t *pfc_macda)
+{
+    uint64_t reg_pfc_da=0;
+
+#ifdef VALIDATE_PARMS
+    if(!pfc_macda)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, PFC_DA, reg_pfc_da);
+
+    *pfc_macda = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_DA, PFC_MACDA, reg_pfc_da);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_da_overlay_set(uint8_t port_id, uint16_t pfc_macda_hi, uint32_t pfc_macda_lo)
+{
+    uint64_t reg_pfc_da_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_pfc_da_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_DA_OVERLAY, PFC_MACDA_HI, reg_pfc_da_overlay, (uint64_t)pfc_macda_hi);
+    reg_pfc_da_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, PFC_DA_OVERLAY, PFC_MACDA_LO, reg_pfc_da_overlay, (uint64_t)pfc_macda_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, PFC_DA_OVERLAY, reg_pfc_da_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_pfc_da_overlay_get(uint8_t port_id, uint16_t *pfc_macda_hi, uint32_t *pfc_macda_lo)
+{
+    uint64_t reg_pfc_da_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!pfc_macda_hi || !pfc_macda_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, PFC_DA_OVERLAY, reg_pfc_da_overlay);
+
+    *pfc_macda_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_DA_OVERLAY, PFC_MACDA_HI, reg_pfc_da_overlay);
+    *pfc_macda_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, PFC_DA_OVERLAY, PFC_MACDA_LO, reg_pfc_da_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_llfc_ctrl_set(uint8_t port_id, const lport_xlmac_llfc_ctrl *llfc_ctrl)
+{
+    uint64_t reg_llfc_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!llfc_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (llfc_ctrl->no_som_for_crc_llfc >= _1BITS_MAX_VAL_) ||
+       (llfc_ctrl->llfc_crc_ignore >= _1BITS_MAX_VAL_) ||
+       (llfc_ctrl->llfc_cut_through_mode >= _1BITS_MAX_VAL_) ||
+       (llfc_ctrl->llfc_in_ipg_only >= _1BITS_MAX_VAL_) ||
+       (llfc_ctrl->rx_llfc_en >= _1BITS_MAX_VAL_) ||
+       (llfc_ctrl->tx_llfc_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_llfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, LLFC_CTRL, LLFC_IMG, reg_llfc_ctrl, (uint64_t)llfc_ctrl->llfc_img);
+    reg_llfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, LLFC_CTRL, NO_SOM_FOR_CRC_LLFC, reg_llfc_ctrl, (uint64_t)llfc_ctrl->no_som_for_crc_llfc);
+    reg_llfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, LLFC_CTRL, LLFC_CRC_IGNORE, reg_llfc_ctrl, (uint64_t)llfc_ctrl->llfc_crc_ignore);
+    reg_llfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, LLFC_CTRL, LLFC_CUT_THROUGH_MODE, reg_llfc_ctrl, (uint64_t)llfc_ctrl->llfc_cut_through_mode);
+    reg_llfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, LLFC_CTRL, LLFC_IN_IPG_ONLY, reg_llfc_ctrl, (uint64_t)llfc_ctrl->llfc_in_ipg_only);
+    reg_llfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, LLFC_CTRL, RX_LLFC_EN, reg_llfc_ctrl, (uint64_t)llfc_ctrl->rx_llfc_en);
+    reg_llfc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, LLFC_CTRL, TX_LLFC_EN, reg_llfc_ctrl, (uint64_t)llfc_ctrl->tx_llfc_en);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, LLFC_CTRL, reg_llfc_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_llfc_ctrl_get(uint8_t port_id, lport_xlmac_llfc_ctrl *llfc_ctrl)
+{
+    uint64_t reg_llfc_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!llfc_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, LLFC_CTRL, reg_llfc_ctrl);
+
+    llfc_ctrl->llfc_img = RU_FIELD_GET(port_id, LPORT_XLMAC, LLFC_CTRL, LLFC_IMG, reg_llfc_ctrl);
+    llfc_ctrl->no_som_for_crc_llfc = RU_FIELD_GET(port_id, LPORT_XLMAC, LLFC_CTRL, NO_SOM_FOR_CRC_LLFC, reg_llfc_ctrl);
+    llfc_ctrl->llfc_crc_ignore = RU_FIELD_GET(port_id, LPORT_XLMAC, LLFC_CTRL, LLFC_CRC_IGNORE, reg_llfc_ctrl);
+    llfc_ctrl->llfc_cut_through_mode = RU_FIELD_GET(port_id, LPORT_XLMAC, LLFC_CTRL, LLFC_CUT_THROUGH_MODE, reg_llfc_ctrl);
+    llfc_ctrl->llfc_in_ipg_only = RU_FIELD_GET(port_id, LPORT_XLMAC, LLFC_CTRL, LLFC_IN_IPG_ONLY, reg_llfc_ctrl);
+    llfc_ctrl->rx_llfc_en = RU_FIELD_GET(port_id, LPORT_XLMAC, LLFC_CTRL, RX_LLFC_EN, reg_llfc_ctrl);
+    llfc_ctrl->tx_llfc_en = RU_FIELD_GET(port_id, LPORT_XLMAC, LLFC_CTRL, TX_LLFC_EN, reg_llfc_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_llfc_msg_fields_set(uint8_t port_id, uint16_t llfc_xoff_time, uint8_t tx_llfc_fc_obj_logical, uint8_t tx_llfc_msg_type_logical)
+{
+    uint64_t reg_tx_llfc_msg_fields=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (tx_llfc_fc_obj_logical >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_tx_llfc_msg_fields = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_LLFC_MSG_FIELDS, LLFC_XOFF_TIME, reg_tx_llfc_msg_fields, (uint64_t)llfc_xoff_time);
+    reg_tx_llfc_msg_fields = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_LLFC_MSG_FIELDS, TX_LLFC_FC_OBJ_LOGICAL, reg_tx_llfc_msg_fields, (uint64_t)tx_llfc_fc_obj_logical);
+    reg_tx_llfc_msg_fields = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_LLFC_MSG_FIELDS, TX_LLFC_MSG_TYPE_LOGICAL, reg_tx_llfc_msg_fields, (uint64_t)tx_llfc_msg_type_logical);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, TX_LLFC_MSG_FIELDS, reg_tx_llfc_msg_fields);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_llfc_msg_fields_get(uint8_t port_id, uint16_t *llfc_xoff_time, uint8_t *tx_llfc_fc_obj_logical, uint8_t *tx_llfc_msg_type_logical)
+{
+    uint64_t reg_tx_llfc_msg_fields=0;
+
+#ifdef VALIDATE_PARMS
+    if(!llfc_xoff_time || !tx_llfc_fc_obj_logical || !tx_llfc_msg_type_logical)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TX_LLFC_MSG_FIELDS, reg_tx_llfc_msg_fields);
+
+    *llfc_xoff_time = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_LLFC_MSG_FIELDS, LLFC_XOFF_TIME, reg_tx_llfc_msg_fields);
+    *tx_llfc_fc_obj_logical = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_LLFC_MSG_FIELDS, TX_LLFC_FC_OBJ_LOGICAL, reg_tx_llfc_msg_fields);
+    *tx_llfc_msg_type_logical = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_LLFC_MSG_FIELDS, TX_LLFC_MSG_TYPE_LOGICAL, reg_tx_llfc_msg_fields);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_llfc_msg_fields_set(uint8_t port_id, uint8_t rx_llfc_fc_obj_physical, uint8_t rx_llfc_msg_type_physical, uint8_t rx_llfc_fc_obj_logical, uint8_t rx_llfc_msg_type_logical)
+{
+    uint64_t reg_rx_llfc_msg_fields=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (rx_llfc_fc_obj_physical >= _4BITS_MAX_VAL_) ||
+       (rx_llfc_fc_obj_logical >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_rx_llfc_msg_fields = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LLFC_MSG_FIELDS, RX_LLFC_FC_OBJ_PHYSICAL, reg_rx_llfc_msg_fields, (uint64_t)rx_llfc_fc_obj_physical);
+    reg_rx_llfc_msg_fields = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LLFC_MSG_FIELDS, RX_LLFC_MSG_TYPE_PHYSICAL, reg_rx_llfc_msg_fields, (uint64_t)rx_llfc_msg_type_physical);
+    reg_rx_llfc_msg_fields = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LLFC_MSG_FIELDS, RX_LLFC_FC_OBJ_LOGICAL, reg_rx_llfc_msg_fields, (uint64_t)rx_llfc_fc_obj_logical);
+    reg_rx_llfc_msg_fields = RU_FIELD_SET(port_id, LPORT_XLMAC, RX_LLFC_MSG_FIELDS, RX_LLFC_MSG_TYPE_LOGICAL, reg_rx_llfc_msg_fields, (uint64_t)rx_llfc_msg_type_logical);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, RX_LLFC_MSG_FIELDS, reg_rx_llfc_msg_fields);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_llfc_msg_fields_get(uint8_t port_id, uint8_t *rx_llfc_fc_obj_physical, uint8_t *rx_llfc_msg_type_physical, uint8_t *rx_llfc_fc_obj_logical, uint8_t *rx_llfc_msg_type_logical)
+{
+    uint64_t reg_rx_llfc_msg_fields=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_llfc_fc_obj_physical || !rx_llfc_msg_type_physical || !rx_llfc_fc_obj_logical || !rx_llfc_msg_type_logical)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, RX_LLFC_MSG_FIELDS, reg_rx_llfc_msg_fields);
+
+    *rx_llfc_fc_obj_physical = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LLFC_MSG_FIELDS, RX_LLFC_FC_OBJ_PHYSICAL, reg_rx_llfc_msg_fields);
+    *rx_llfc_msg_type_physical = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LLFC_MSG_FIELDS, RX_LLFC_MSG_TYPE_PHYSICAL, reg_rx_llfc_msg_fields);
+    *rx_llfc_fc_obj_logical = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LLFC_MSG_FIELDS, RX_LLFC_FC_OBJ_LOGICAL, reg_rx_llfc_msg_fields);
+    *rx_llfc_msg_type_logical = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_LLFC_MSG_FIELDS, RX_LLFC_MSG_TYPE_LOGICAL, reg_rx_llfc_msg_fields);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_timestamp_fifo_data_get(uint8_t port_id, uint8_t *ts_entry_valid, uint16_t *sequence_id, uint32_t *time_stamp)
+{
+    uint64_t reg_tx_timestamp_fifo_data=0;
+
+#ifdef VALIDATE_PARMS
+    if(!ts_entry_valid || !sequence_id || !time_stamp)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TX_TIMESTAMP_FIFO_DATA, reg_tx_timestamp_fifo_data);
+
+    *ts_entry_valid = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_TIMESTAMP_FIFO_DATA, TS_ENTRY_VALID, reg_tx_timestamp_fifo_data);
+    *sequence_id = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_TIMESTAMP_FIFO_DATA, SEQUENCE_ID, reg_tx_timestamp_fifo_data);
+    *time_stamp = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_TIMESTAMP_FIFO_DATA, TIME_STAMP, reg_tx_timestamp_fifo_data);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_timestamp_fifo_status_get(uint8_t port_id, uint8_t *entry_count)
+{
+    uint64_t reg_tx_timestamp_fifo_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!entry_count)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TX_TIMESTAMP_FIFO_STATUS, reg_tx_timestamp_fifo_status);
+
+    *entry_count = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_TIMESTAMP_FIFO_STATUS, ENTRY_COUNT, reg_tx_timestamp_fifo_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_fifo_status_get(uint8_t port_id, lport_xlmac_fifo_status *fifo_status)
+{
+    uint64_t reg_fifo_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!fifo_status)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, FIFO_STATUS, reg_fifo_status);
+
+    fifo_status->link_status = RU_FIELD_GET(port_id, LPORT_XLMAC, FIFO_STATUS, LINK_STATUS, reg_fifo_status);
+    fifo_status->rx_pkt_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, FIFO_STATUS, RX_PKT_OVERFLOW, reg_fifo_status);
+    fifo_status->tx_ts_fifo_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, FIFO_STATUS, TX_TS_FIFO_OVERFLOW, reg_fifo_status);
+    fifo_status->tx_llfc_msg_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, FIFO_STATUS, TX_LLFC_MSG_OVERFLOW, reg_fifo_status);
+    fifo_status->rsvd_2 = RU_FIELD_GET(port_id, LPORT_XLMAC, FIFO_STATUS, RSVD_2, reg_fifo_status);
+    fifo_status->tx_pkt_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, FIFO_STATUS, TX_PKT_OVERFLOW, reg_fifo_status);
+    fifo_status->tx_pkt_underflow = RU_FIELD_GET(port_id, LPORT_XLMAC, FIFO_STATUS, TX_PKT_UNDERFLOW, reg_fifo_status);
+    fifo_status->rx_msg_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, FIFO_STATUS, RX_MSG_OVERFLOW, reg_fifo_status);
+    fifo_status->rsvd_1 = RU_FIELD_GET(port_id, LPORT_XLMAC, FIFO_STATUS, RSVD_1, reg_fifo_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_clear_fifo_status_set(uint8_t port_id, const lport_xlmac_clear_fifo_status *clear_fifo_status)
+{
+    uint64_t reg_clear_fifo_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!clear_fifo_status)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (clear_fifo_status->clear_rx_pkt_overflow >= _1BITS_MAX_VAL_) ||
+       (clear_fifo_status->clear_tx_ts_fifo_overflow >= _1BITS_MAX_VAL_) ||
+       (clear_fifo_status->clear_tx_llfc_msg_overflow >= _1BITS_MAX_VAL_) ||
+       (clear_fifo_status->rsvd_2 >= _1BITS_MAX_VAL_) ||
+       (clear_fifo_status->clear_tx_pkt_overflow >= _1BITS_MAX_VAL_) ||
+       (clear_fifo_status->clear_tx_pkt_underflow >= _1BITS_MAX_VAL_) ||
+       (clear_fifo_status->clear_rx_msg_overflow >= _1BITS_MAX_VAL_) ||
+       (clear_fifo_status->rsvd_1 >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_clear_fifo_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_RX_PKT_OVERFLOW, reg_clear_fifo_status, (uint64_t)clear_fifo_status->clear_rx_pkt_overflow);
+    reg_clear_fifo_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_TX_TS_FIFO_OVERFLOW, reg_clear_fifo_status, (uint64_t)clear_fifo_status->clear_tx_ts_fifo_overflow);
+    reg_clear_fifo_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_TX_LLFC_MSG_OVERFLOW, reg_clear_fifo_status, (uint64_t)clear_fifo_status->clear_tx_llfc_msg_overflow);
+    reg_clear_fifo_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, RSVD_2, reg_clear_fifo_status, (uint64_t)clear_fifo_status->rsvd_2);
+    reg_clear_fifo_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_TX_PKT_OVERFLOW, reg_clear_fifo_status, (uint64_t)clear_fifo_status->clear_tx_pkt_overflow);
+    reg_clear_fifo_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_TX_PKT_UNDERFLOW, reg_clear_fifo_status, (uint64_t)clear_fifo_status->clear_tx_pkt_underflow);
+    reg_clear_fifo_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_RX_MSG_OVERFLOW, reg_clear_fifo_status, (uint64_t)clear_fifo_status->clear_rx_msg_overflow);
+    reg_clear_fifo_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, RSVD_1, reg_clear_fifo_status, (uint64_t)clear_fifo_status->rsvd_1);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, reg_clear_fifo_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_clear_fifo_status_get(uint8_t port_id, lport_xlmac_clear_fifo_status *clear_fifo_status)
+{
+    uint64_t reg_clear_fifo_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!clear_fifo_status)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, reg_clear_fifo_status);
+
+    clear_fifo_status->clear_rx_pkt_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_RX_PKT_OVERFLOW, reg_clear_fifo_status);
+    clear_fifo_status->clear_tx_ts_fifo_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_TX_TS_FIFO_OVERFLOW, reg_clear_fifo_status);
+    clear_fifo_status->clear_tx_llfc_msg_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_TX_LLFC_MSG_OVERFLOW, reg_clear_fifo_status);
+    clear_fifo_status->rsvd_2 = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, RSVD_2, reg_clear_fifo_status);
+    clear_fifo_status->clear_tx_pkt_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_TX_PKT_OVERFLOW, reg_clear_fifo_status);
+    clear_fifo_status->clear_tx_pkt_underflow = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_TX_PKT_UNDERFLOW, reg_clear_fifo_status);
+    clear_fifo_status->clear_rx_msg_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, CLEAR_RX_MSG_OVERFLOW, reg_clear_fifo_status);
+    clear_fifo_status->rsvd_1 = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_FIFO_STATUS, RSVD_1, reg_clear_fifo_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_lag_failover_status_get(uint8_t port_id, uint8_t *rsvd, uint8_t *lag_failover_loopback)
+{
+    uint64_t reg_lag_failover_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rsvd || !lag_failover_loopback)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, LAG_FAILOVER_STATUS, reg_lag_failover_status);
+
+    *rsvd = RU_FIELD_GET(port_id, LPORT_XLMAC, LAG_FAILOVER_STATUS, RSVD, reg_lag_failover_status);
+    *lag_failover_loopback = RU_FIELD_GET(port_id, LPORT_XLMAC, LAG_FAILOVER_STATUS, LAG_FAILOVER_LOOPBACK, reg_lag_failover_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_eee_ctrl_set(uint8_t port_id, uint8_t rsvd, uint8_t eee_en)
+{
+    uint64_t reg_eee_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (rsvd >= _1BITS_MAX_VAL_) ||
+       (eee_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_eee_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, EEE_CTRL, RSVD, reg_eee_ctrl, (uint64_t)rsvd);
+    reg_eee_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, EEE_CTRL, EEE_EN, reg_eee_ctrl, (uint64_t)eee_en);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, EEE_CTRL, reg_eee_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_eee_ctrl_get(uint8_t port_id, uint8_t *rsvd, uint8_t *eee_en)
+{
+    uint64_t reg_eee_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rsvd || !eee_en)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, EEE_CTRL, reg_eee_ctrl);
+
+    *rsvd = RU_FIELD_GET(port_id, LPORT_XLMAC, EEE_CTRL, RSVD, reg_eee_ctrl);
+    *eee_en = RU_FIELD_GET(port_id, LPORT_XLMAC, EEE_CTRL, EEE_EN, reg_eee_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_eee_timers_set(uint8_t port_id, uint16_t eee_ref_count, uint16_t eee_wake_timer, uint32_t eee_delay_entry_timer)
+{
+    uint64_t reg_eee_timers=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_eee_timers = RU_FIELD_SET(port_id, LPORT_XLMAC, EEE_TIMERS, EEE_REF_COUNT, reg_eee_timers, (uint64_t)eee_ref_count);
+    reg_eee_timers = RU_FIELD_SET(port_id, LPORT_XLMAC, EEE_TIMERS, EEE_WAKE_TIMER, reg_eee_timers, (uint64_t)eee_wake_timer);
+    reg_eee_timers = RU_FIELD_SET(port_id, LPORT_XLMAC, EEE_TIMERS, EEE_DELAY_ENTRY_TIMER, reg_eee_timers, (uint64_t)eee_delay_entry_timer);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, EEE_TIMERS, reg_eee_timers);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_eee_timers_get(uint8_t port_id, uint16_t *eee_ref_count, uint16_t *eee_wake_timer, uint32_t *eee_delay_entry_timer)
+{
+    uint64_t reg_eee_timers=0;
+
+#ifdef VALIDATE_PARMS
+    if(!eee_ref_count || !eee_wake_timer || !eee_delay_entry_timer)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, EEE_TIMERS, reg_eee_timers);
+
+    *eee_ref_count = RU_FIELD_GET(port_id, LPORT_XLMAC, EEE_TIMERS, EEE_REF_COUNT, reg_eee_timers);
+    *eee_wake_timer = RU_FIELD_GET(port_id, LPORT_XLMAC, EEE_TIMERS, EEE_WAKE_TIMER, reg_eee_timers);
+    *eee_delay_entry_timer = RU_FIELD_GET(port_id, LPORT_XLMAC, EEE_TIMERS, EEE_DELAY_ENTRY_TIMER, reg_eee_timers);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_eee_timers_overlay_set(uint8_t port_id, uint32_t xlmac_eee_timers_hi, uint32_t xlmac_eee_timers_lo)
+{
+    uint64_t reg_eee_timers_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_eee_timers_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, EEE_TIMERS_OVERLAY, XLMAC_EEE_TIMERS_HI, reg_eee_timers_overlay, (uint64_t)xlmac_eee_timers_hi);
+    reg_eee_timers_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, EEE_TIMERS_OVERLAY, XLMAC_EEE_TIMERS_LO, reg_eee_timers_overlay, (uint64_t)xlmac_eee_timers_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, EEE_TIMERS_OVERLAY, reg_eee_timers_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_eee_timers_overlay_get(uint8_t port_id, uint32_t *xlmac_eee_timers_hi, uint32_t *xlmac_eee_timers_lo)
+{
+    uint64_t reg_eee_timers_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!xlmac_eee_timers_hi || !xlmac_eee_timers_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, EEE_TIMERS_OVERLAY, reg_eee_timers_overlay);
+
+    *xlmac_eee_timers_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, EEE_TIMERS_OVERLAY, XLMAC_EEE_TIMERS_HI, reg_eee_timers_overlay);
+    *xlmac_eee_timers_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, EEE_TIMERS_OVERLAY, XLMAC_EEE_TIMERS_LO, reg_eee_timers_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_eee_1_sec_link_status_timer_set(uint8_t port_id, uint32_t one_second_timer)
+{
+    uint64_t reg_eee_1_sec_link_status_timer=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (one_second_timer >= _24BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_eee_1_sec_link_status_timer = RU_FIELD_SET(port_id, LPORT_XLMAC, EEE_1_SEC_LINK_STATUS_TIMER, ONE_SECOND_TIMER, reg_eee_1_sec_link_status_timer, (uint64_t)one_second_timer);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, EEE_1_SEC_LINK_STATUS_TIMER, reg_eee_1_sec_link_status_timer);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_eee_1_sec_link_status_timer_get(uint8_t port_id, uint32_t *one_second_timer)
+{
+    uint64_t reg_eee_1_sec_link_status_timer=0;
+
+#ifdef VALIDATE_PARMS
+    if(!one_second_timer)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, EEE_1_SEC_LINK_STATUS_TIMER, reg_eee_1_sec_link_status_timer);
+
+    *one_second_timer = RU_FIELD_GET(port_id, LPORT_XLMAC, EEE_1_SEC_LINK_STATUS_TIMER, ONE_SECOND_TIMER, reg_eee_1_sec_link_status_timer);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_higig_hdr_0_set(uint8_t port_id, uint64_t higig_hdr_0)
+{
+    uint64_t reg_higig_hdr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_higig_hdr_0 = RU_FIELD_SET(port_id, LPORT_XLMAC, HIGIG_HDR_0, HIGIG_HDR_0, reg_higig_hdr_0, (uint64_t)higig_hdr_0);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, HIGIG_HDR_0, reg_higig_hdr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_higig_hdr_0_get(uint8_t port_id, uint64_t *higig_hdr_0)
+{
+    uint64_t reg_higig_hdr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!higig_hdr_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, HIGIG_HDR_0, reg_higig_hdr_0);
+
+    *higig_hdr_0 = RU_FIELD_GET(port_id, LPORT_XLMAC, HIGIG_HDR_0, HIGIG_HDR_0, reg_higig_hdr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_higig_hdr_0_overlay_set(uint8_t port_id, uint32_t higig_hdr_0_hi, uint32_t higig_hdr_0_lo)
+{
+    uint64_t reg_higig_hdr_0_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_higig_hdr_0_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, HIGIG_HDR_0_OVERLAY, HIGIG_HDR_0_HI, reg_higig_hdr_0_overlay, (uint64_t)higig_hdr_0_hi);
+    reg_higig_hdr_0_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, HIGIG_HDR_0_OVERLAY, HIGIG_HDR_0_LO, reg_higig_hdr_0_overlay, (uint64_t)higig_hdr_0_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, HIGIG_HDR_0_OVERLAY, reg_higig_hdr_0_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_higig_hdr_0_overlay_get(uint8_t port_id, uint32_t *higig_hdr_0_hi, uint32_t *higig_hdr_0_lo)
+{
+    uint64_t reg_higig_hdr_0_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!higig_hdr_0_hi || !higig_hdr_0_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, HIGIG_HDR_0_OVERLAY, reg_higig_hdr_0_overlay);
+
+    *higig_hdr_0_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, HIGIG_HDR_0_OVERLAY, HIGIG_HDR_0_HI, reg_higig_hdr_0_overlay);
+    *higig_hdr_0_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, HIGIG_HDR_0_OVERLAY, HIGIG_HDR_0_LO, reg_higig_hdr_0_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_higig_hdr_1_set(uint8_t port_id, uint64_t higig_hdr_1)
+{
+    uint64_t reg_higig_hdr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_higig_hdr_1 = RU_FIELD_SET(port_id, LPORT_XLMAC, HIGIG_HDR_1, HIGIG_HDR_1, reg_higig_hdr_1, (uint64_t)higig_hdr_1);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, HIGIG_HDR_1, reg_higig_hdr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_higig_hdr_1_get(uint8_t port_id, uint64_t *higig_hdr_1)
+{
+    uint64_t reg_higig_hdr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!higig_hdr_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, HIGIG_HDR_1, reg_higig_hdr_1);
+
+    *higig_hdr_1 = RU_FIELD_GET(port_id, LPORT_XLMAC, HIGIG_HDR_1, HIGIG_HDR_1, reg_higig_hdr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_higig_hdr_1_overlay_set(uint8_t port_id, uint32_t higig_hdr_1_hi, uint32_t higig_hdr_1_lo)
+{
+    uint64_t reg_higig_hdr_1_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_higig_hdr_1_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, HIGIG_HDR_1_OVERLAY, HIGIG_HDR_1_HI, reg_higig_hdr_1_overlay, (uint64_t)higig_hdr_1_hi);
+    reg_higig_hdr_1_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, HIGIG_HDR_1_OVERLAY, HIGIG_HDR_1_LO, reg_higig_hdr_1_overlay, (uint64_t)higig_hdr_1_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, HIGIG_HDR_1_OVERLAY, reg_higig_hdr_1_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_higig_hdr_1_overlay_get(uint8_t port_id, uint32_t *higig_hdr_1_hi, uint32_t *higig_hdr_1_lo)
+{
+    uint64_t reg_higig_hdr_1_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!higig_hdr_1_hi || !higig_hdr_1_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, HIGIG_HDR_1_OVERLAY, reg_higig_hdr_1_overlay);
+
+    *higig_hdr_1_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, HIGIG_HDR_1_OVERLAY, HIGIG_HDR_1_HI, reg_higig_hdr_1_overlay);
+    *higig_hdr_1_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, HIGIG_HDR_1_OVERLAY, HIGIG_HDR_1_LO, reg_higig_hdr_1_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_gmii_eee_ctrl_set(uint8_t port_id, uint8_t gmii_lpi_predict_mode_en, uint16_t gmii_lpi_predict_threshold)
+{
+    uint64_t reg_gmii_eee_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (gmii_lpi_predict_mode_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gmii_eee_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, GMII_EEE_CTRL, GMII_LPI_PREDICT_MODE_EN, reg_gmii_eee_ctrl, (uint64_t)gmii_lpi_predict_mode_en);
+    reg_gmii_eee_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, GMII_EEE_CTRL, GMII_LPI_PREDICT_THRESHOLD, reg_gmii_eee_ctrl, (uint64_t)gmii_lpi_predict_threshold);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, GMII_EEE_CTRL, reg_gmii_eee_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_gmii_eee_ctrl_get(uint8_t port_id, uint8_t *gmii_lpi_predict_mode_en, uint16_t *gmii_lpi_predict_threshold)
+{
+    uint64_t reg_gmii_eee_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!gmii_lpi_predict_mode_en || !gmii_lpi_predict_threshold)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, GMII_EEE_CTRL, reg_gmii_eee_ctrl);
+
+    *gmii_lpi_predict_mode_en = RU_FIELD_GET(port_id, LPORT_XLMAC, GMII_EEE_CTRL, GMII_LPI_PREDICT_MODE_EN, reg_gmii_eee_ctrl);
+    *gmii_lpi_predict_threshold = RU_FIELD_GET(port_id, LPORT_XLMAC, GMII_EEE_CTRL, GMII_LPI_PREDICT_THRESHOLD, reg_gmii_eee_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_timestamp_adjust_set(uint8_t port_id, uint8_t ts_use_cs_offset, uint8_t ts_tsts_adjust, uint16_t ts_osts_adjust)
+{
+    uint64_t reg_timestamp_adjust=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (ts_use_cs_offset >= _1BITS_MAX_VAL_) ||
+       (ts_tsts_adjust >= _6BITS_MAX_VAL_) ||
+       (ts_osts_adjust >= _9BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_timestamp_adjust = RU_FIELD_SET(port_id, LPORT_XLMAC, TIMESTAMP_ADJUST, TS_USE_CS_OFFSET, reg_timestamp_adjust, (uint64_t)ts_use_cs_offset);
+    reg_timestamp_adjust = RU_FIELD_SET(port_id, LPORT_XLMAC, TIMESTAMP_ADJUST, TS_TSTS_ADJUST, reg_timestamp_adjust, (uint64_t)ts_tsts_adjust);
+    reg_timestamp_adjust = RU_FIELD_SET(port_id, LPORT_XLMAC, TIMESTAMP_ADJUST, TS_OSTS_ADJUST, reg_timestamp_adjust, (uint64_t)ts_osts_adjust);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, TIMESTAMP_ADJUST, reg_timestamp_adjust);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_timestamp_adjust_get(uint8_t port_id, uint8_t *ts_use_cs_offset, uint8_t *ts_tsts_adjust, uint16_t *ts_osts_adjust)
+{
+    uint64_t reg_timestamp_adjust=0;
+
+#ifdef VALIDATE_PARMS
+    if(!ts_use_cs_offset || !ts_tsts_adjust || !ts_osts_adjust)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TIMESTAMP_ADJUST, reg_timestamp_adjust);
+
+    *ts_use_cs_offset = RU_FIELD_GET(port_id, LPORT_XLMAC, TIMESTAMP_ADJUST, TS_USE_CS_OFFSET, reg_timestamp_adjust);
+    *ts_tsts_adjust = RU_FIELD_GET(port_id, LPORT_XLMAC, TIMESTAMP_ADJUST, TS_TSTS_ADJUST, reg_timestamp_adjust);
+    *ts_osts_adjust = RU_FIELD_GET(port_id, LPORT_XLMAC, TIMESTAMP_ADJUST, TS_OSTS_ADJUST, reg_timestamp_adjust);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_timestamp_byte_adjust_set(uint8_t port_id, uint8_t rx_timer_byte_adjust_en, uint16_t rx_timer_byte_adjust, uint8_t tx_timer_byte_adjust_en, uint16_t tx_timer_byte_adjust)
+{
+    uint64_t reg_timestamp_byte_adjust=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (rx_timer_byte_adjust_en >= _1BITS_MAX_VAL_) ||
+       (rx_timer_byte_adjust >= _10BITS_MAX_VAL_) ||
+       (tx_timer_byte_adjust_en >= _1BITS_MAX_VAL_) ||
+       (tx_timer_byte_adjust >= _10BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_timestamp_byte_adjust = RU_FIELD_SET(port_id, LPORT_XLMAC, TIMESTAMP_BYTE_ADJUST, RX_TIMER_BYTE_ADJUST_EN, reg_timestamp_byte_adjust, (uint64_t)rx_timer_byte_adjust_en);
+    reg_timestamp_byte_adjust = RU_FIELD_SET(port_id, LPORT_XLMAC, TIMESTAMP_BYTE_ADJUST, RX_TIMER_BYTE_ADJUST, reg_timestamp_byte_adjust, (uint64_t)rx_timer_byte_adjust);
+    reg_timestamp_byte_adjust = RU_FIELD_SET(port_id, LPORT_XLMAC, TIMESTAMP_BYTE_ADJUST, TX_TIMER_BYTE_ADJUST_EN, reg_timestamp_byte_adjust, (uint64_t)tx_timer_byte_adjust_en);
+    reg_timestamp_byte_adjust = RU_FIELD_SET(port_id, LPORT_XLMAC, TIMESTAMP_BYTE_ADJUST, TX_TIMER_BYTE_ADJUST, reg_timestamp_byte_adjust, (uint64_t)tx_timer_byte_adjust);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, TIMESTAMP_BYTE_ADJUST, reg_timestamp_byte_adjust);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_timestamp_byte_adjust_get(uint8_t port_id, uint8_t *rx_timer_byte_adjust_en, uint16_t *rx_timer_byte_adjust, uint8_t *tx_timer_byte_adjust_en, uint16_t *tx_timer_byte_adjust)
+{
+    uint64_t reg_timestamp_byte_adjust=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_timer_byte_adjust_en || !rx_timer_byte_adjust || !tx_timer_byte_adjust_en || !tx_timer_byte_adjust)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TIMESTAMP_BYTE_ADJUST, reg_timestamp_byte_adjust);
+
+    *rx_timer_byte_adjust_en = RU_FIELD_GET(port_id, LPORT_XLMAC, TIMESTAMP_BYTE_ADJUST, RX_TIMER_BYTE_ADJUST_EN, reg_timestamp_byte_adjust);
+    *rx_timer_byte_adjust = RU_FIELD_GET(port_id, LPORT_XLMAC, TIMESTAMP_BYTE_ADJUST, RX_TIMER_BYTE_ADJUST, reg_timestamp_byte_adjust);
+    *tx_timer_byte_adjust_en = RU_FIELD_GET(port_id, LPORT_XLMAC, TIMESTAMP_BYTE_ADJUST, TX_TIMER_BYTE_ADJUST_EN, reg_timestamp_byte_adjust);
+    *tx_timer_byte_adjust = RU_FIELD_GET(port_id, LPORT_XLMAC, TIMESTAMP_BYTE_ADJUST, TX_TIMER_BYTE_ADJUST, reg_timestamp_byte_adjust);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_crc_corrupt_ctrl_set(uint8_t port_id, uint32_t prog_tx_crc, uint8_t tx_crc_corruption_mode, uint8_t tx_crc_corrupt_en, uint8_t tx_err_corrupts_crc)
+{
+    uint64_t reg_tx_crc_corrupt_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (tx_crc_corruption_mode >= _1BITS_MAX_VAL_) ||
+       (tx_crc_corrupt_en >= _1BITS_MAX_VAL_) ||
+       (tx_err_corrupts_crc >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_tx_crc_corrupt_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL, PROG_TX_CRC, reg_tx_crc_corrupt_ctrl, (uint64_t)prog_tx_crc);
+    reg_tx_crc_corrupt_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL, TX_CRC_CORRUPTION_MODE, reg_tx_crc_corrupt_ctrl, (uint64_t)tx_crc_corruption_mode);
+    reg_tx_crc_corrupt_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL, TX_CRC_CORRUPT_EN, reg_tx_crc_corrupt_ctrl, (uint64_t)tx_crc_corrupt_en);
+    reg_tx_crc_corrupt_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL, TX_ERR_CORRUPTS_CRC, reg_tx_crc_corrupt_ctrl, (uint64_t)tx_err_corrupts_crc);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL, reg_tx_crc_corrupt_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_crc_corrupt_ctrl_get(uint8_t port_id, uint32_t *prog_tx_crc, uint8_t *tx_crc_corruption_mode, uint8_t *tx_crc_corrupt_en, uint8_t *tx_err_corrupts_crc)
+{
+    uint64_t reg_tx_crc_corrupt_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!prog_tx_crc || !tx_crc_corruption_mode || !tx_crc_corrupt_en || !tx_err_corrupts_crc)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL, reg_tx_crc_corrupt_ctrl);
+
+    *prog_tx_crc = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL, PROG_TX_CRC, reg_tx_crc_corrupt_ctrl);
+    *tx_crc_corruption_mode = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL, TX_CRC_CORRUPTION_MODE, reg_tx_crc_corrupt_ctrl);
+    *tx_crc_corrupt_en = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL, TX_CRC_CORRUPT_EN, reg_tx_crc_corrupt_ctrl);
+    *tx_err_corrupts_crc = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL, TX_ERR_CORRUPTS_CRC, reg_tx_crc_corrupt_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_crc_corrupt_ctrl_overlay_set(uint8_t port_id, uint8_t xlmac_tx_crc_corrupt_ctrl_hi, uint32_t xlmac_tx_crc_corrupt_ctrl_lo)
+{
+    uint64_t reg_tx_crc_corrupt_ctrl_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (xlmac_tx_crc_corrupt_ctrl_hi >= _3BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_tx_crc_corrupt_ctrl_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL_OVERLAY, XLMAC_TX_CRC_CORRUPT_CTRL_HI, reg_tx_crc_corrupt_ctrl_overlay, (uint64_t)xlmac_tx_crc_corrupt_ctrl_hi);
+    reg_tx_crc_corrupt_ctrl_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL_OVERLAY, XLMAC_TX_CRC_CORRUPT_CTRL_LO, reg_tx_crc_corrupt_ctrl_overlay, (uint64_t)xlmac_tx_crc_corrupt_ctrl_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL_OVERLAY, reg_tx_crc_corrupt_ctrl_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_crc_corrupt_ctrl_overlay_get(uint8_t port_id, uint8_t *xlmac_tx_crc_corrupt_ctrl_hi, uint32_t *xlmac_tx_crc_corrupt_ctrl_lo)
+{
+    uint64_t reg_tx_crc_corrupt_ctrl_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!xlmac_tx_crc_corrupt_ctrl_hi || !xlmac_tx_crc_corrupt_ctrl_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL_OVERLAY, reg_tx_crc_corrupt_ctrl_overlay);
+
+    *xlmac_tx_crc_corrupt_ctrl_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL_OVERLAY, XLMAC_TX_CRC_CORRUPT_CTRL_HI, reg_tx_crc_corrupt_ctrl_overlay);
+    *xlmac_tx_crc_corrupt_ctrl_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CRC_CORRUPT_CTRL_OVERLAY, XLMAC_TX_CRC_CORRUPT_CTRL_LO, reg_tx_crc_corrupt_ctrl_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2e_ctrl_set(uint8_t port_id, const lport_xlmac_e2e_ctrl *e2e_ctrl)
+{
+    uint64_t reg_e2e_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2e_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (e2e_ctrl->e2efc_dual_modid_en >= _1BITS_MAX_VAL_) ||
+       (e2e_ctrl->e2ecc_legacy_imp_en >= _1BITS_MAX_VAL_) ||
+       (e2e_ctrl->e2ecc_dual_modid_en >= _1BITS_MAX_VAL_) ||
+       (e2e_ctrl->honor_pause_for_e2e >= _1BITS_MAX_VAL_) ||
+       (e2e_ctrl->e2e_enable >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2e_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, E2E_CTRL, E2EFC_DUAL_MODID_EN, reg_e2e_ctrl, (uint64_t)e2e_ctrl->e2efc_dual_modid_en);
+    reg_e2e_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, E2E_CTRL, E2ECC_LEGACY_IMP_EN, reg_e2e_ctrl, (uint64_t)e2e_ctrl->e2ecc_legacy_imp_en);
+    reg_e2e_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, E2E_CTRL, E2ECC_DUAL_MODID_EN, reg_e2e_ctrl, (uint64_t)e2e_ctrl->e2ecc_dual_modid_en);
+    reg_e2e_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, E2E_CTRL, HONOR_PAUSE_FOR_E2E, reg_e2e_ctrl, (uint64_t)e2e_ctrl->honor_pause_for_e2e);
+    reg_e2e_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, E2E_CTRL, E2E_ENABLE, reg_e2e_ctrl, (uint64_t)e2e_ctrl->e2e_enable);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2E_CTRL, reg_e2e_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2e_ctrl_get(uint8_t port_id, lport_xlmac_e2e_ctrl *e2e_ctrl)
+{
+    uint64_t reg_e2e_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2e_ctrl)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2E_CTRL, reg_e2e_ctrl);
+
+    e2e_ctrl->e2efc_dual_modid_en = RU_FIELD_GET(port_id, LPORT_XLMAC, E2E_CTRL, E2EFC_DUAL_MODID_EN, reg_e2e_ctrl);
+    e2e_ctrl->e2ecc_legacy_imp_en = RU_FIELD_GET(port_id, LPORT_XLMAC, E2E_CTRL, E2ECC_LEGACY_IMP_EN, reg_e2e_ctrl);
+    e2e_ctrl->e2ecc_dual_modid_en = RU_FIELD_GET(port_id, LPORT_XLMAC, E2E_CTRL, E2ECC_DUAL_MODID_EN, reg_e2e_ctrl);
+    e2e_ctrl->honor_pause_for_e2e = RU_FIELD_GET(port_id, LPORT_XLMAC, E2E_CTRL, HONOR_PAUSE_FOR_E2E, reg_e2e_ctrl);
+    e2e_ctrl->e2e_enable = RU_FIELD_GET(port_id, LPORT_XLMAC, E2E_CTRL, E2E_ENABLE, reg_e2e_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_module_hdr_0_set(uint8_t port_id, uint64_t e2ecc_module_hdr_0)
+{
+    uint64_t reg_e2ecc_module_hdr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2ecc_module_hdr_0 = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_0, E2ECC_MODULE_HDR_0, reg_e2ecc_module_hdr_0, (uint64_t)e2ecc_module_hdr_0);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_0, reg_e2ecc_module_hdr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_module_hdr_0_get(uint8_t port_id, uint64_t *e2ecc_module_hdr_0)
+{
+    uint64_t reg_e2ecc_module_hdr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2ecc_module_hdr_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_0, reg_e2ecc_module_hdr_0);
+
+    *e2ecc_module_hdr_0 = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_0, E2ECC_MODULE_HDR_0, reg_e2ecc_module_hdr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_module_hdr_0_overlay_set(uint8_t port_id, uint32_t e2ecc_module_hdr_0_hi, uint32_t e2ecc_module_hdr_0_lo)
+{
+    uint64_t reg_e2ecc_module_hdr_0_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2ecc_module_hdr_0_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_0_OVERLAY, E2ECC_MODULE_HDR_0_HI, reg_e2ecc_module_hdr_0_overlay, (uint64_t)e2ecc_module_hdr_0_hi);
+    reg_e2ecc_module_hdr_0_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_0_OVERLAY, E2ECC_MODULE_HDR_0_LO, reg_e2ecc_module_hdr_0_overlay, (uint64_t)e2ecc_module_hdr_0_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_0_OVERLAY, reg_e2ecc_module_hdr_0_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_module_hdr_0_overlay_get(uint8_t port_id, uint32_t *e2ecc_module_hdr_0_hi, uint32_t *e2ecc_module_hdr_0_lo)
+{
+    uint64_t reg_e2ecc_module_hdr_0_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2ecc_module_hdr_0_hi || !e2ecc_module_hdr_0_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_0_OVERLAY, reg_e2ecc_module_hdr_0_overlay);
+
+    *e2ecc_module_hdr_0_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_0_OVERLAY, E2ECC_MODULE_HDR_0_HI, reg_e2ecc_module_hdr_0_overlay);
+    *e2ecc_module_hdr_0_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_0_OVERLAY, E2ECC_MODULE_HDR_0_LO, reg_e2ecc_module_hdr_0_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_module_hdr_1_set(uint8_t port_id, uint64_t e2ecc_module_hdr_1)
+{
+    uint64_t reg_e2ecc_module_hdr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2ecc_module_hdr_1 = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_1, E2ECC_MODULE_HDR_1, reg_e2ecc_module_hdr_1, (uint64_t)e2ecc_module_hdr_1);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_1, reg_e2ecc_module_hdr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_module_hdr_1_get(uint8_t port_id, uint64_t *e2ecc_module_hdr_1)
+{
+    uint64_t reg_e2ecc_module_hdr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2ecc_module_hdr_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_1, reg_e2ecc_module_hdr_1);
+
+    *e2ecc_module_hdr_1 = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_1, E2ECC_MODULE_HDR_1, reg_e2ecc_module_hdr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_module_hdr_1_overlay_set(uint8_t port_id, uint32_t e2ecc_module_hdr_1_hi, uint32_t e2ecc_module_hdr_1_lo)
+{
+    uint64_t reg_e2ecc_module_hdr_1_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2ecc_module_hdr_1_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_1_OVERLAY, E2ECC_MODULE_HDR_1_HI, reg_e2ecc_module_hdr_1_overlay, (uint64_t)e2ecc_module_hdr_1_hi);
+    reg_e2ecc_module_hdr_1_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_1_OVERLAY, E2ECC_MODULE_HDR_1_LO, reg_e2ecc_module_hdr_1_overlay, (uint64_t)e2ecc_module_hdr_1_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_1_OVERLAY, reg_e2ecc_module_hdr_1_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_module_hdr_1_overlay_get(uint8_t port_id, uint32_t *e2ecc_module_hdr_1_hi, uint32_t *e2ecc_module_hdr_1_lo)
+{
+    uint64_t reg_e2ecc_module_hdr_1_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2ecc_module_hdr_1_hi || !e2ecc_module_hdr_1_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_1_OVERLAY, reg_e2ecc_module_hdr_1_overlay);
+
+    *e2ecc_module_hdr_1_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_1_OVERLAY, E2ECC_MODULE_HDR_1_HI, reg_e2ecc_module_hdr_1_overlay);
+    *e2ecc_module_hdr_1_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_MODULE_HDR_1_OVERLAY, E2ECC_MODULE_HDR_1_LO, reg_e2ecc_module_hdr_1_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_data_hdr_0_set(uint8_t port_id, uint64_t e2ecc_data_hdr_0)
+{
+    uint64_t reg_e2ecc_data_hdr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2ecc_data_hdr_0 = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_0, E2ECC_DATA_HDR_0, reg_e2ecc_data_hdr_0, (uint64_t)e2ecc_data_hdr_0);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_0, reg_e2ecc_data_hdr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_data_hdr_0_get(uint8_t port_id, uint64_t *e2ecc_data_hdr_0)
+{
+    uint64_t reg_e2ecc_data_hdr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2ecc_data_hdr_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_0, reg_e2ecc_data_hdr_0);
+
+    *e2ecc_data_hdr_0 = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_0, E2ECC_DATA_HDR_0, reg_e2ecc_data_hdr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_data_hdr_0_overlay_set(uint8_t port_id, uint32_t e2ecc_data_hdr_0_hi, uint32_t e2ecc_data_hdr_0_lo)
+{
+    uint64_t reg_e2ecc_data_hdr_0_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2ecc_data_hdr_0_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_0_OVERLAY, E2ECC_DATA_HDR_0_HI, reg_e2ecc_data_hdr_0_overlay, (uint64_t)e2ecc_data_hdr_0_hi);
+    reg_e2ecc_data_hdr_0_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_0_OVERLAY, E2ECC_DATA_HDR_0_LO, reg_e2ecc_data_hdr_0_overlay, (uint64_t)e2ecc_data_hdr_0_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_0_OVERLAY, reg_e2ecc_data_hdr_0_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_data_hdr_0_overlay_get(uint8_t port_id, uint32_t *e2ecc_data_hdr_0_hi, uint32_t *e2ecc_data_hdr_0_lo)
+{
+    uint64_t reg_e2ecc_data_hdr_0_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2ecc_data_hdr_0_hi || !e2ecc_data_hdr_0_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_0_OVERLAY, reg_e2ecc_data_hdr_0_overlay);
+
+    *e2ecc_data_hdr_0_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_0_OVERLAY, E2ECC_DATA_HDR_0_HI, reg_e2ecc_data_hdr_0_overlay);
+    *e2ecc_data_hdr_0_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_0_OVERLAY, E2ECC_DATA_HDR_0_LO, reg_e2ecc_data_hdr_0_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_data_hdr_1_set(uint8_t port_id, uint64_t e2ecc_data_hdr_1)
+{
+    uint64_t reg_e2ecc_data_hdr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2ecc_data_hdr_1 = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_1, E2ECC_DATA_HDR_1, reg_e2ecc_data_hdr_1, (uint64_t)e2ecc_data_hdr_1);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_1, reg_e2ecc_data_hdr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_data_hdr_1_get(uint8_t port_id, uint64_t *e2ecc_data_hdr_1)
+{
+    uint64_t reg_e2ecc_data_hdr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2ecc_data_hdr_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_1, reg_e2ecc_data_hdr_1);
+
+    *e2ecc_data_hdr_1 = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_1, E2ECC_DATA_HDR_1, reg_e2ecc_data_hdr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_data_hdr_1_overlay_set(uint8_t port_id, uint32_t e2ecc_data_hdr_1_hi, uint32_t e2ecc_data_hdr_1_lo)
+{
+    uint64_t reg_e2ecc_data_hdr_1_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2ecc_data_hdr_1_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_1_OVERLAY, E2ECC_DATA_HDR_1_HI, reg_e2ecc_data_hdr_1_overlay, (uint64_t)e2ecc_data_hdr_1_hi);
+    reg_e2ecc_data_hdr_1_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_1_OVERLAY, E2ECC_DATA_HDR_1_LO, reg_e2ecc_data_hdr_1_overlay, (uint64_t)e2ecc_data_hdr_1_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_1_OVERLAY, reg_e2ecc_data_hdr_1_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2ecc_data_hdr_1_overlay_get(uint8_t port_id, uint32_t *e2ecc_data_hdr_1_hi, uint32_t *e2ecc_data_hdr_1_lo)
+{
+    uint64_t reg_e2ecc_data_hdr_1_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2ecc_data_hdr_1_hi || !e2ecc_data_hdr_1_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_1_OVERLAY, reg_e2ecc_data_hdr_1_overlay);
+
+    *e2ecc_data_hdr_1_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_1_OVERLAY, E2ECC_DATA_HDR_1_HI, reg_e2ecc_data_hdr_1_overlay);
+    *e2ecc_data_hdr_1_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, E2ECC_DATA_HDR_1_OVERLAY, E2ECC_DATA_HDR_1_LO, reg_e2ecc_data_hdr_1_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_module_hdr_0_set(uint8_t port_id, uint64_t e2efc_module_hdr_0)
+{
+    uint64_t reg_e2efc_module_hdr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2efc_module_hdr_0 = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_0, E2EFC_MODULE_HDR_0, reg_e2efc_module_hdr_0, (uint64_t)e2efc_module_hdr_0);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_0, reg_e2efc_module_hdr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_module_hdr_0_get(uint8_t port_id, uint64_t *e2efc_module_hdr_0)
+{
+    uint64_t reg_e2efc_module_hdr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2efc_module_hdr_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_0, reg_e2efc_module_hdr_0);
+
+    *e2efc_module_hdr_0 = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_0, E2EFC_MODULE_HDR_0, reg_e2efc_module_hdr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_module_hdr_0_overlay_set(uint8_t port_id, uint32_t e2efc_module_hdr_0_hi, uint32_t e2efc_module_hdr_0_lo)
+{
+    uint64_t reg_e2efc_module_hdr_0_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2efc_module_hdr_0_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_0_OVERLAY, E2EFC_MODULE_HDR_0_HI, reg_e2efc_module_hdr_0_overlay, (uint64_t)e2efc_module_hdr_0_hi);
+    reg_e2efc_module_hdr_0_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_0_OVERLAY, E2EFC_MODULE_HDR_0_LO, reg_e2efc_module_hdr_0_overlay, (uint64_t)e2efc_module_hdr_0_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_0_OVERLAY, reg_e2efc_module_hdr_0_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_module_hdr_0_overlay_get(uint8_t port_id, uint32_t *e2efc_module_hdr_0_hi, uint32_t *e2efc_module_hdr_0_lo)
+{
+    uint64_t reg_e2efc_module_hdr_0_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2efc_module_hdr_0_hi || !e2efc_module_hdr_0_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_0_OVERLAY, reg_e2efc_module_hdr_0_overlay);
+
+    *e2efc_module_hdr_0_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_0_OVERLAY, E2EFC_MODULE_HDR_0_HI, reg_e2efc_module_hdr_0_overlay);
+    *e2efc_module_hdr_0_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_0_OVERLAY, E2EFC_MODULE_HDR_0_LO, reg_e2efc_module_hdr_0_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_module_hdr_1_set(uint8_t port_id, uint64_t e2efc_module_hdr_1)
+{
+    uint64_t reg_e2efc_module_hdr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2efc_module_hdr_1 = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_1, E2EFC_MODULE_HDR_1, reg_e2efc_module_hdr_1, (uint64_t)e2efc_module_hdr_1);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_1, reg_e2efc_module_hdr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_module_hdr_1_get(uint8_t port_id, uint64_t *e2efc_module_hdr_1)
+{
+    uint64_t reg_e2efc_module_hdr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2efc_module_hdr_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_1, reg_e2efc_module_hdr_1);
+
+    *e2efc_module_hdr_1 = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_1, E2EFC_MODULE_HDR_1, reg_e2efc_module_hdr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_module_hdr_1_overlay_set(uint8_t port_id, uint32_t e2efc_module_hdr_1_hi, uint32_t e2efc_module_hdr_1_lo)
+{
+    uint64_t reg_e2efc_module_hdr_1_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2efc_module_hdr_1_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_1_OVERLAY, E2EFC_MODULE_HDR_1_HI, reg_e2efc_module_hdr_1_overlay, (uint64_t)e2efc_module_hdr_1_hi);
+    reg_e2efc_module_hdr_1_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_1_OVERLAY, E2EFC_MODULE_HDR_1_LO, reg_e2efc_module_hdr_1_overlay, (uint64_t)e2efc_module_hdr_1_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_1_OVERLAY, reg_e2efc_module_hdr_1_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_module_hdr_1_overlay_get(uint8_t port_id, uint32_t *e2efc_module_hdr_1_hi, uint32_t *e2efc_module_hdr_1_lo)
+{
+    uint64_t reg_e2efc_module_hdr_1_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2efc_module_hdr_1_hi || !e2efc_module_hdr_1_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_1_OVERLAY, reg_e2efc_module_hdr_1_overlay);
+
+    *e2efc_module_hdr_1_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_1_OVERLAY, E2EFC_MODULE_HDR_1_HI, reg_e2efc_module_hdr_1_overlay);
+    *e2efc_module_hdr_1_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_MODULE_HDR_1_OVERLAY, E2EFC_MODULE_HDR_1_LO, reg_e2efc_module_hdr_1_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_data_hdr_0_set(uint8_t port_id, uint64_t e2efc_data_hdr_0)
+{
+    uint64_t reg_e2efc_data_hdr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2efc_data_hdr_0 = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_0, E2EFC_DATA_HDR_0, reg_e2efc_data_hdr_0, (uint64_t)e2efc_data_hdr_0);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_0, reg_e2efc_data_hdr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_data_hdr_0_get(uint8_t port_id, uint64_t *e2efc_data_hdr_0)
+{
+    uint64_t reg_e2efc_data_hdr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2efc_data_hdr_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_0, reg_e2efc_data_hdr_0);
+
+    *e2efc_data_hdr_0 = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_0, E2EFC_DATA_HDR_0, reg_e2efc_data_hdr_0);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_data_hdr_0_overlay_set(uint8_t port_id, uint32_t e2efc_data_hdr_0_hi, uint32_t e2efc_data_hdr_0_lo)
+{
+    uint64_t reg_e2efc_data_hdr_0_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2efc_data_hdr_0_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_0_OVERLAY, E2EFC_DATA_HDR_0_HI, reg_e2efc_data_hdr_0_overlay, (uint64_t)e2efc_data_hdr_0_hi);
+    reg_e2efc_data_hdr_0_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_0_OVERLAY, E2EFC_DATA_HDR_0_LO, reg_e2efc_data_hdr_0_overlay, (uint64_t)e2efc_data_hdr_0_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_0_OVERLAY, reg_e2efc_data_hdr_0_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_data_hdr_0_overlay_get(uint8_t port_id, uint32_t *e2efc_data_hdr_0_hi, uint32_t *e2efc_data_hdr_0_lo)
+{
+    uint64_t reg_e2efc_data_hdr_0_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2efc_data_hdr_0_hi || !e2efc_data_hdr_0_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_0_OVERLAY, reg_e2efc_data_hdr_0_overlay);
+
+    *e2efc_data_hdr_0_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_0_OVERLAY, E2EFC_DATA_HDR_0_HI, reg_e2efc_data_hdr_0_overlay);
+    *e2efc_data_hdr_0_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_0_OVERLAY, E2EFC_DATA_HDR_0_LO, reg_e2efc_data_hdr_0_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_data_hdr_1_set(uint8_t port_id, uint64_t e2efc_data_hdr_1)
+{
+    uint64_t reg_e2efc_data_hdr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2efc_data_hdr_1 = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_1, E2EFC_DATA_HDR_1, reg_e2efc_data_hdr_1, (uint64_t)e2efc_data_hdr_1);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_1, reg_e2efc_data_hdr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_data_hdr_1_get(uint8_t port_id, uint64_t *e2efc_data_hdr_1)
+{
+    uint64_t reg_e2efc_data_hdr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2efc_data_hdr_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_1, reg_e2efc_data_hdr_1);
+
+    *e2efc_data_hdr_1 = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_1, E2EFC_DATA_HDR_1, reg_e2efc_data_hdr_1);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_data_hdr_1_overlay_set(uint8_t port_id, uint32_t e2efc_data_hdr_1_hi, uint32_t e2efc_data_hdr_1_lo)
+{
+    uint64_t reg_e2efc_data_hdr_1_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_e2efc_data_hdr_1_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_1_OVERLAY, E2EFC_DATA_HDR_1_HI, reg_e2efc_data_hdr_1_overlay, (uint64_t)e2efc_data_hdr_1_hi);
+    reg_e2efc_data_hdr_1_overlay = RU_FIELD_SET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_1_OVERLAY, E2EFC_DATA_HDR_1_LO, reg_e2efc_data_hdr_1_overlay, (uint64_t)e2efc_data_hdr_1_lo);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_1_OVERLAY, reg_e2efc_data_hdr_1_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_e2efc_data_hdr_1_overlay_get(uint8_t port_id, uint32_t *e2efc_data_hdr_1_hi, uint32_t *e2efc_data_hdr_1_lo)
+{
+    uint64_t reg_e2efc_data_hdr_1_overlay=0;
+
+#ifdef VALIDATE_PARMS
+    if(!e2efc_data_hdr_1_hi || !e2efc_data_hdr_1_lo)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_1_OVERLAY, reg_e2efc_data_hdr_1_overlay);
+
+    *e2efc_data_hdr_1_hi = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_1_OVERLAY, E2EFC_DATA_HDR_1_HI, reg_e2efc_data_hdr_1_overlay);
+    *e2efc_data_hdr_1_lo = RU_FIELD_GET(port_id, LPORT_XLMAC, E2EFC_DATA_HDR_1_OVERLAY, E2EFC_DATA_HDR_1_LO, reg_e2efc_data_hdr_1_overlay);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_txfifo_cell_cnt_get(uint8_t port_id, uint8_t *cell_cnt)
+{
+    uint64_t reg_txfifo_cell_cnt=0;
+
+#ifdef VALIDATE_PARMS
+    if(!cell_cnt)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TXFIFO_CELL_CNT, reg_txfifo_cell_cnt);
+
+    *cell_cnt = RU_FIELD_GET(port_id, LPORT_XLMAC, TXFIFO_CELL_CNT, CELL_CNT, reg_txfifo_cell_cnt);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_txfifo_cell_req_cnt_get(uint8_t port_id, uint8_t *req_cnt)
+{
+    uint64_t reg_txfifo_cell_req_cnt=0;
+
+#ifdef VALIDATE_PARMS
+    if(!req_cnt)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TXFIFO_CELL_REQ_CNT, reg_txfifo_cell_req_cnt);
+
+    *req_cnt = RU_FIELD_GET(port_id, LPORT_XLMAC, TXFIFO_CELL_REQ_CNT, REQ_CNT, reg_txfifo_cell_req_cnt);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_mem_ctrl_set(uint8_t port_id, uint16_t tx_cdc_mem_ctrl_tm, uint16_t rx_cdc_mem_ctrl_tm)
+{
+    uint64_t reg_mem_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (tx_cdc_mem_ctrl_tm >= _12BITS_MAX_VAL_) ||
+       (rx_cdc_mem_ctrl_tm >= _12BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_mem_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, MEM_CTRL, TX_CDC_MEM_CTRL_TM, reg_mem_ctrl, (uint64_t)tx_cdc_mem_ctrl_tm);
+    reg_mem_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, MEM_CTRL, RX_CDC_MEM_CTRL_TM, reg_mem_ctrl, (uint64_t)rx_cdc_mem_ctrl_tm);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, MEM_CTRL, reg_mem_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_mem_ctrl_get(uint8_t port_id, uint16_t *tx_cdc_mem_ctrl_tm, uint16_t *rx_cdc_mem_ctrl_tm)
+{
+    uint64_t reg_mem_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_cdc_mem_ctrl_tm || !rx_cdc_mem_ctrl_tm)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, MEM_CTRL, reg_mem_ctrl);
+
+    *tx_cdc_mem_ctrl_tm = RU_FIELD_GET(port_id, LPORT_XLMAC, MEM_CTRL, TX_CDC_MEM_CTRL_TM, reg_mem_ctrl);
+    *rx_cdc_mem_ctrl_tm = RU_FIELD_GET(port_id, LPORT_XLMAC, MEM_CTRL, RX_CDC_MEM_CTRL_TM, reg_mem_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_ecc_ctrl_set(uint8_t port_id, uint8_t tx_cdc_ecc_ctrl_en, uint8_t rx_cdc_ecc_ctrl_en)
+{
+    uint64_t reg_ecc_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (tx_cdc_ecc_ctrl_en >= _1BITS_MAX_VAL_) ||
+       (rx_cdc_ecc_ctrl_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ecc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, ECC_CTRL, TX_CDC_ECC_CTRL_EN, reg_ecc_ctrl, (uint64_t)tx_cdc_ecc_ctrl_en);
+    reg_ecc_ctrl = RU_FIELD_SET(port_id, LPORT_XLMAC, ECC_CTRL, RX_CDC_ECC_CTRL_EN, reg_ecc_ctrl, (uint64_t)rx_cdc_ecc_ctrl_en);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, ECC_CTRL, reg_ecc_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_ecc_ctrl_get(uint8_t port_id, uint8_t *tx_cdc_ecc_ctrl_en, uint8_t *rx_cdc_ecc_ctrl_en)
+{
+    uint64_t reg_ecc_ctrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_cdc_ecc_ctrl_en || !rx_cdc_ecc_ctrl_en)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, ECC_CTRL, reg_ecc_ctrl);
+
+    *tx_cdc_ecc_ctrl_en = RU_FIELD_GET(port_id, LPORT_XLMAC, ECC_CTRL, TX_CDC_ECC_CTRL_EN, reg_ecc_ctrl);
+    *rx_cdc_ecc_ctrl_en = RU_FIELD_GET(port_id, LPORT_XLMAC, ECC_CTRL, RX_CDC_ECC_CTRL_EN, reg_ecc_ctrl);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_ecc_force_double_bit_err_set(uint8_t port_id, uint8_t tx_cdc_force_double_bit_err, uint8_t rx_cdc_force_double_bit_err)
+{
+    uint64_t reg_ecc_force_double_bit_err=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (tx_cdc_force_double_bit_err >= _1BITS_MAX_VAL_) ||
+       (rx_cdc_force_double_bit_err >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ecc_force_double_bit_err = RU_FIELD_SET(port_id, LPORT_XLMAC, ECC_FORCE_DOUBLE_BIT_ERR, TX_CDC_FORCE_DOUBLE_BIT_ERR, reg_ecc_force_double_bit_err, (uint64_t)tx_cdc_force_double_bit_err);
+    reg_ecc_force_double_bit_err = RU_FIELD_SET(port_id, LPORT_XLMAC, ECC_FORCE_DOUBLE_BIT_ERR, RX_CDC_FORCE_DOUBLE_BIT_ERR, reg_ecc_force_double_bit_err, (uint64_t)rx_cdc_force_double_bit_err);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, ECC_FORCE_DOUBLE_BIT_ERR, reg_ecc_force_double_bit_err);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_ecc_force_double_bit_err_get(uint8_t port_id, uint8_t *tx_cdc_force_double_bit_err, uint8_t *rx_cdc_force_double_bit_err)
+{
+    uint64_t reg_ecc_force_double_bit_err=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_cdc_force_double_bit_err || !rx_cdc_force_double_bit_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, ECC_FORCE_DOUBLE_BIT_ERR, reg_ecc_force_double_bit_err);
+
+    *tx_cdc_force_double_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, ECC_FORCE_DOUBLE_BIT_ERR, TX_CDC_FORCE_DOUBLE_BIT_ERR, reg_ecc_force_double_bit_err);
+    *rx_cdc_force_double_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, ECC_FORCE_DOUBLE_BIT_ERR, RX_CDC_FORCE_DOUBLE_BIT_ERR, reg_ecc_force_double_bit_err);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_ecc_force_single_bit_err_set(uint8_t port_id, uint8_t tx_cdc_force_single_bit_err, uint8_t rx_cdc_force_single_bit_err)
+{
+    uint64_t reg_ecc_force_single_bit_err=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (tx_cdc_force_single_bit_err >= _1BITS_MAX_VAL_) ||
+       (rx_cdc_force_single_bit_err >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ecc_force_single_bit_err = RU_FIELD_SET(port_id, LPORT_XLMAC, ECC_FORCE_SINGLE_BIT_ERR, TX_CDC_FORCE_SINGLE_BIT_ERR, reg_ecc_force_single_bit_err, (uint64_t)tx_cdc_force_single_bit_err);
+    reg_ecc_force_single_bit_err = RU_FIELD_SET(port_id, LPORT_XLMAC, ECC_FORCE_SINGLE_BIT_ERR, RX_CDC_FORCE_SINGLE_BIT_ERR, reg_ecc_force_single_bit_err, (uint64_t)rx_cdc_force_single_bit_err);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, ECC_FORCE_SINGLE_BIT_ERR, reg_ecc_force_single_bit_err);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_ecc_force_single_bit_err_get(uint8_t port_id, uint8_t *tx_cdc_force_single_bit_err, uint8_t *rx_cdc_force_single_bit_err)
+{
+    uint64_t reg_ecc_force_single_bit_err=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_cdc_force_single_bit_err || !rx_cdc_force_single_bit_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, ECC_FORCE_SINGLE_BIT_ERR, reg_ecc_force_single_bit_err);
+
+    *tx_cdc_force_single_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, ECC_FORCE_SINGLE_BIT_ERR, TX_CDC_FORCE_SINGLE_BIT_ERR, reg_ecc_force_single_bit_err);
+    *rx_cdc_force_single_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, ECC_FORCE_SINGLE_BIT_ERR, RX_CDC_FORCE_SINGLE_BIT_ERR, reg_ecc_force_single_bit_err);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_rx_cdc_ecc_status_get(uint8_t port_id, uint8_t *rx_cdc_double_bit_err, uint8_t *rx_cdc_single_bit_err)
+{
+    uint64_t reg_rx_cdc_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rx_cdc_double_bit_err || !rx_cdc_single_bit_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, RX_CDC_ECC_STATUS, reg_rx_cdc_ecc_status);
+
+    *rx_cdc_double_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CDC_ECC_STATUS, RX_CDC_DOUBLE_BIT_ERR, reg_rx_cdc_ecc_status);
+    *rx_cdc_single_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, RX_CDC_ECC_STATUS, RX_CDC_SINGLE_BIT_ERR, reg_rx_cdc_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_tx_cdc_ecc_status_get(uint8_t port_id, uint8_t *tx_cdc_double_bit_err, uint8_t *tx_cdc_single_bit_err)
+{
+    uint64_t reg_tx_cdc_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_cdc_double_bit_err || !tx_cdc_single_bit_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, TX_CDC_ECC_STATUS, reg_tx_cdc_ecc_status);
+
+    *tx_cdc_double_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CDC_ECC_STATUS, TX_CDC_DOUBLE_BIT_ERR, reg_tx_cdc_ecc_status);
+    *tx_cdc_single_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, TX_CDC_ECC_STATUS, TX_CDC_SINGLE_BIT_ERR, reg_tx_cdc_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_clear_ecc_status_set(uint8_t port_id, uint8_t clear_tx_cdc_double_bit_err, uint8_t clear_tx_cdc_single_bit_err, uint8_t clear_rx_cdc_double_bit_err, uint8_t clear_rx_cdc_single_bit_err)
+{
+    uint64_t reg_clear_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (clear_tx_cdc_double_bit_err >= _1BITS_MAX_VAL_) ||
+       (clear_tx_cdc_single_bit_err >= _1BITS_MAX_VAL_) ||
+       (clear_rx_cdc_double_bit_err >= _1BITS_MAX_VAL_) ||
+       (clear_rx_cdc_single_bit_err >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_clear_ecc_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_ECC_STATUS, CLEAR_TX_CDC_DOUBLE_BIT_ERR, reg_clear_ecc_status, (uint64_t)clear_tx_cdc_double_bit_err);
+    reg_clear_ecc_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_ECC_STATUS, CLEAR_TX_CDC_SINGLE_BIT_ERR, reg_clear_ecc_status, (uint64_t)clear_tx_cdc_single_bit_err);
+    reg_clear_ecc_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_ECC_STATUS, CLEAR_RX_CDC_DOUBLE_BIT_ERR, reg_clear_ecc_status, (uint64_t)clear_rx_cdc_double_bit_err);
+    reg_clear_ecc_status = RU_FIELD_SET(port_id, LPORT_XLMAC, CLEAR_ECC_STATUS, CLEAR_RX_CDC_SINGLE_BIT_ERR, reg_clear_ecc_status, (uint64_t)clear_rx_cdc_single_bit_err);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, CLEAR_ECC_STATUS, reg_clear_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_clear_ecc_status_get(uint8_t port_id, uint8_t *clear_tx_cdc_double_bit_err, uint8_t *clear_tx_cdc_single_bit_err, uint8_t *clear_rx_cdc_double_bit_err, uint8_t *clear_rx_cdc_single_bit_err)
+{
+    uint64_t reg_clear_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!clear_tx_cdc_double_bit_err || !clear_tx_cdc_single_bit_err || !clear_rx_cdc_double_bit_err || !clear_rx_cdc_single_bit_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, CLEAR_ECC_STATUS, reg_clear_ecc_status);
+
+    *clear_tx_cdc_double_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_ECC_STATUS, CLEAR_TX_CDC_DOUBLE_BIT_ERR, reg_clear_ecc_status);
+    *clear_tx_cdc_single_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_ECC_STATUS, CLEAR_TX_CDC_SINGLE_BIT_ERR, reg_clear_ecc_status);
+    *clear_rx_cdc_double_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_ECC_STATUS, CLEAR_RX_CDC_DOUBLE_BIT_ERR, reg_clear_ecc_status);
+    *clear_rx_cdc_single_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, CLEAR_ECC_STATUS, CLEAR_RX_CDC_SINGLE_BIT_ERR, reg_clear_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_intr_status_get(uint8_t port_id, lport_xlmac_intr_status *intr_status)
+{
+    uint64_t reg_intr_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!intr_status)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, INTR_STATUS, reg_intr_status);
+
+    intr_status->sum_ts_entry_valid = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_TS_ENTRY_VALID, reg_intr_status);
+    intr_status->sum_link_interruption_status = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_LINK_INTERRUPTION_STATUS, reg_intr_status);
+    intr_status->sum_remote_fault_status = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_REMOTE_FAULT_STATUS, reg_intr_status);
+    intr_status->sum_local_fault_status = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_LOCAL_FAULT_STATUS, reg_intr_status);
+    intr_status->sum_rx_cdc_double_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_RX_CDC_DOUBLE_BIT_ERR, reg_intr_status);
+    intr_status->sum_rx_cdc_single_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_RX_CDC_SINGLE_BIT_ERR, reg_intr_status);
+    intr_status->sum_tx_cdc_double_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_TX_CDC_DOUBLE_BIT_ERR, reg_intr_status);
+    intr_status->sum_tx_cdc_single_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_TX_CDC_SINGLE_BIT_ERR, reg_intr_status);
+    intr_status->sum_rx_msg_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_RX_MSG_OVERFLOW, reg_intr_status);
+    intr_status->sum_rx_pkt_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_RX_PKT_OVERFLOW, reg_intr_status);
+    intr_status->sum_tx_ts_fifo_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_TX_TS_FIFO_OVERFLOW, reg_intr_status);
+    intr_status->sum_tx_llfc_msg_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_TX_LLFC_MSG_OVERFLOW, reg_intr_status);
+    intr_status->sum_tx_pkt_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_TX_PKT_OVERFLOW, reg_intr_status);
+    intr_status->sum_tx_pkt_underflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_STATUS, SUM_TX_PKT_UNDERFLOW, reg_intr_status);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_intr_enable_set(uint8_t port_id, const lport_xlmac_intr_enable *intr_enable)
+{
+    uint64_t reg_intr_enable=0;
+
+#ifdef VALIDATE_PARMS
+    if(!intr_enable)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT) ||
+       (intr_enable->en_ts_entry_valid >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_link_interruption_status >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_remote_fault_status >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_local_fault_status >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_rx_cdc_double_bit_err >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_rx_cdc_single_bit_err >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_tx_cdc_double_bit_err >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_tx_cdc_single_bit_err >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_rx_msg_overflow >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_rx_pkt_overflow >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_tx_ts_fifo_overflow >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_tx_llfc_msg_overflow >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_tx_pkt_overflow >= _1BITS_MAX_VAL_) ||
+       (intr_enable->en_tx_pkt_underflow >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TS_ENTRY_VALID, reg_intr_enable, (uint64_t)intr_enable->en_ts_entry_valid);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_LINK_INTERRUPTION_STATUS, reg_intr_enable, (uint64_t)intr_enable->en_link_interruption_status);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_REMOTE_FAULT_STATUS, reg_intr_enable, (uint64_t)intr_enable->en_remote_fault_status);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_LOCAL_FAULT_STATUS, reg_intr_enable, (uint64_t)intr_enable->en_local_fault_status);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_RX_CDC_DOUBLE_BIT_ERR, reg_intr_enable, (uint64_t)intr_enable->en_rx_cdc_double_bit_err);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_RX_CDC_SINGLE_BIT_ERR, reg_intr_enable, (uint64_t)intr_enable->en_rx_cdc_single_bit_err);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_CDC_DOUBLE_BIT_ERR, reg_intr_enable, (uint64_t)intr_enable->en_tx_cdc_double_bit_err);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_CDC_SINGLE_BIT_ERR, reg_intr_enable, (uint64_t)intr_enable->en_tx_cdc_single_bit_err);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_RX_MSG_OVERFLOW, reg_intr_enable, (uint64_t)intr_enable->en_rx_msg_overflow);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_RX_PKT_OVERFLOW, reg_intr_enable, (uint64_t)intr_enable->en_rx_pkt_overflow);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_TS_FIFO_OVERFLOW, reg_intr_enable, (uint64_t)intr_enable->en_tx_ts_fifo_overflow);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_LLFC_MSG_OVERFLOW, reg_intr_enable, (uint64_t)intr_enable->en_tx_llfc_msg_overflow);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_PKT_OVERFLOW, reg_intr_enable, (uint64_t)intr_enable->en_tx_pkt_overflow);
+    reg_intr_enable = RU_FIELD_SET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_PKT_UNDERFLOW, reg_intr_enable, (uint64_t)intr_enable->en_tx_pkt_underflow);
+
+    XLMAC_INDIRECT_WRITE(port_id, LPORT_XLMAC, INTR_ENABLE, reg_intr_enable);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_intr_enable_get(uint8_t port_id, lport_xlmac_intr_enable *intr_enable)
+{
+    uint64_t reg_intr_enable=0;
+
+#ifdef VALIDATE_PARMS
+    if(!intr_enable)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, INTR_ENABLE, reg_intr_enable);
+
+    intr_enable->en_ts_entry_valid = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TS_ENTRY_VALID, reg_intr_enable);
+    intr_enable->en_link_interruption_status = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_LINK_INTERRUPTION_STATUS, reg_intr_enable);
+    intr_enable->en_remote_fault_status = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_REMOTE_FAULT_STATUS, reg_intr_enable);
+    intr_enable->en_local_fault_status = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_LOCAL_FAULT_STATUS, reg_intr_enable);
+    intr_enable->en_rx_cdc_double_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_RX_CDC_DOUBLE_BIT_ERR, reg_intr_enable);
+    intr_enable->en_rx_cdc_single_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_RX_CDC_SINGLE_BIT_ERR, reg_intr_enable);
+    intr_enable->en_tx_cdc_double_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_CDC_DOUBLE_BIT_ERR, reg_intr_enable);
+    intr_enable->en_tx_cdc_single_bit_err = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_CDC_SINGLE_BIT_ERR, reg_intr_enable);
+    intr_enable->en_rx_msg_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_RX_MSG_OVERFLOW, reg_intr_enable);
+    intr_enable->en_rx_pkt_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_RX_PKT_OVERFLOW, reg_intr_enable);
+    intr_enable->en_tx_ts_fifo_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_TS_FIFO_OVERFLOW, reg_intr_enable);
+    intr_enable->en_tx_llfc_msg_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_LLFC_MSG_OVERFLOW, reg_intr_enable);
+    intr_enable->en_tx_pkt_overflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_PKT_OVERFLOW, reg_intr_enable);
+    intr_enable->en_tx_pkt_underflow = RU_FIELD_GET(port_id, LPORT_XLMAC, INTR_ENABLE, EN_TX_PKT_UNDERFLOW, reg_intr_enable);
+
+    return 0;
+}
+
+int ag_drv_lport_xlmac_version_id_get(uint8_t port_id, uint16_t *xlmac_version)
+{
+    uint64_t reg_version_id=0;
+
+#ifdef VALIDATE_PARMS
+    if(!xlmac_version)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((port_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    XLMAC_INDIRECT_READ(port_id, LPORT_XLMAC, VERSION_ID, reg_version_id);
+
+    *xlmac_version = RU_FIELD_GET(port_id, LPORT_XLMAC, VERSION_ID, XLMAC_VERSION, reg_version_id);
+
+    return 0;
+}
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_lport_xlmac_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_lport_xlmac_ag.h
new file mode 100644
index 0000000000..433390d6da
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_lport_xlmac_ag.h
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_LPORT_XLMAC_AG_H_
+#define _BCM6858_LPORT_XLMAC_AG_H_
+
+#include "access_macros.h"
+#include "bcmtypes.h"
+typedef struct
+{
+    uint8_t extended_hig2_en;
+    uint8_t link_status_select;
+    uint8_t sw_link_status;
+    uint8_t xgmii_ipg_check_disable;
+    uint8_t rs_soft_reset;
+    uint8_t rsvd_5;
+    uint8_t local_lpbk_leak_enb;
+    uint8_t rsvd_4;
+    uint8_t soft_reset;
+    uint8_t lag_failover_en;
+    uint8_t remove_failover_lpbk;
+    uint8_t rsvd_1;
+    uint8_t local_lpbk;
+    uint8_t rx_en;
+    uint8_t tx_en;
+} lport_xlmac_ctrl;
+
+typedef struct
+{
+    uint8_t tx_threshold;
+    uint8_t ep_discard;
+    uint8_t tx_preamble_length;
+    uint8_t throt_denom;
+    uint8_t throt_num;
+    uint8_t average_ipg;
+    uint8_t pad_threshold;
+    uint8_t pad_en;
+    uint8_t tx_any_start;
+    uint8_t discard;
+    uint8_t crc_mode;
+} lport_xlmac_tx_ctrl;
+
+typedef struct
+{
+    uint8_t rx_pass_pfc;
+    uint8_t rx_pass_pause;
+    uint8_t rx_pass_ctrl;
+    uint8_t rsvd_3;
+    uint8_t rsvd_2;
+    uint8_t runt_threshold;
+    uint8_t strict_preamble;
+    uint8_t strip_crc;
+    uint8_t rx_any_start;
+    uint8_t rsvd_1;
+} lport_xlmac_rx_ctrl;
+
+typedef struct
+{
+    uint8_t reset_flow_control_timers_on_link_down;
+    uint8_t drop_tx_data_on_link_interrupt;
+    uint8_t drop_tx_data_on_remote_fault;
+    uint8_t drop_tx_data_on_local_fault;
+    uint8_t link_interruption_disable;
+    uint8_t use_external_faults_for_tx;
+    uint8_t remote_fault_disable;
+    uint8_t local_fault_disable;
+} lport_xlmac_rx_lss_ctrl;
+
+typedef struct
+{
+    uint16_t pause_xoff_timer;
+    uint8_t rsvd_2;
+    uint8_t rsvd_1;
+    uint8_t rx_pause_en;
+    uint8_t tx_pause_en;
+    uint8_t pause_refresh_en;
+    uint16_t pause_refresh_timer;
+} lport_xlmac_pause_ctrl;
+
+typedef struct
+{
+    uint8_t tx_pfc_en;
+    uint8_t rx_pfc_en;
+    uint8_t pfc_stats_en;
+    uint8_t rsvd;
+    uint8_t force_pfc_xon;
+    uint8_t pfc_refresh_en;
+    uint16_t pfc_xoff_timer;
+    uint16_t pfc_refresh_timer;
+} lport_xlmac_pfc_ctrl;
+
+typedef struct
+{
+    uint8_t llfc_img;
+    uint8_t no_som_for_crc_llfc;
+    uint8_t llfc_crc_ignore;
+    uint8_t llfc_cut_through_mode;
+    uint8_t llfc_in_ipg_only;
+    uint8_t rx_llfc_en;
+    uint8_t tx_llfc_en;
+} lport_xlmac_llfc_ctrl;
+
+typedef struct
+{
+    uint8_t link_status;
+    uint8_t rx_pkt_overflow;
+    uint8_t tx_ts_fifo_overflow;
+    uint8_t tx_llfc_msg_overflow;
+    uint8_t rsvd_2;
+    uint8_t tx_pkt_overflow;
+    uint8_t tx_pkt_underflow;
+    uint8_t rx_msg_overflow;
+    uint8_t rsvd_1;
+} lport_xlmac_fifo_status;
+
+typedef struct
+{
+    uint8_t clear_rx_pkt_overflow;
+    uint8_t clear_tx_ts_fifo_overflow;
+    uint8_t clear_tx_llfc_msg_overflow;
+    uint8_t rsvd_2;
+    uint8_t clear_tx_pkt_overflow;
+    uint8_t clear_tx_pkt_underflow;
+    uint8_t clear_rx_msg_overflow;
+    uint8_t rsvd_1;
+} lport_xlmac_clear_fifo_status;
+
+typedef struct
+{
+    uint8_t e2efc_dual_modid_en;
+    uint8_t e2ecc_legacy_imp_en;
+    uint8_t e2ecc_dual_modid_en;
+    uint8_t honor_pause_for_e2e;
+    uint8_t e2e_enable;
+} lport_xlmac_e2e_ctrl;
+
+typedef struct
+{
+    uint8_t sum_ts_entry_valid;
+    uint8_t sum_link_interruption_status;
+    uint8_t sum_remote_fault_status;
+    uint8_t sum_local_fault_status;
+    uint8_t sum_rx_cdc_double_bit_err;
+    uint8_t sum_rx_cdc_single_bit_err;
+    uint8_t sum_tx_cdc_double_bit_err;
+    uint8_t sum_tx_cdc_single_bit_err;
+    uint8_t sum_rx_msg_overflow;
+    uint8_t sum_rx_pkt_overflow;
+    uint8_t sum_tx_ts_fifo_overflow;
+    uint8_t sum_tx_llfc_msg_overflow;
+    uint8_t sum_tx_pkt_overflow;
+    uint8_t sum_tx_pkt_underflow;
+} lport_xlmac_intr_status;
+
+typedef struct
+{
+    uint8_t en_ts_entry_valid;
+    uint8_t en_link_interruption_status;
+    uint8_t en_remote_fault_status;
+    uint8_t en_local_fault_status;
+    uint8_t en_rx_cdc_double_bit_err;
+    uint8_t en_rx_cdc_single_bit_err;
+    uint8_t en_tx_cdc_double_bit_err;
+    uint8_t en_tx_cdc_single_bit_err;
+    uint8_t en_rx_msg_overflow;
+    uint8_t en_rx_pkt_overflow;
+    uint8_t en_tx_ts_fifo_overflow;
+    uint8_t en_tx_llfc_msg_overflow;
+    uint8_t en_tx_pkt_overflow;
+    uint8_t en_tx_pkt_underflow;
+} lport_xlmac_intr_enable;
+
+int ag_drv_lport_xlmac_ctrl_set(uint8_t port_id, const lport_xlmac_ctrl *ctrl);
+int ag_drv_lport_xlmac_ctrl_get(uint8_t port_id, lport_xlmac_ctrl *ctrl);
+int ag_drv_lport_xlmac_mode_set(uint8_t port_id, uint8_t speed_mode, uint8_t no_sop_for_crc_hg, uint8_t hdr_mode);
+int ag_drv_lport_xlmac_mode_get(uint8_t port_id, uint8_t *speed_mode, uint8_t *no_sop_for_crc_hg, uint8_t *hdr_mode);
+int ag_drv_lport_xlmac_spare0_set(uint8_t port_id, uint32_t rsvd);
+int ag_drv_lport_xlmac_spare0_get(uint8_t port_id, uint32_t *rsvd);
+int ag_drv_lport_xlmac_spare1_set(uint8_t port_id, uint8_t rsvd);
+int ag_drv_lport_xlmac_spare1_get(uint8_t port_id, uint8_t *rsvd);
+int ag_drv_lport_xlmac_tx_ctrl_set(uint8_t port_id, const lport_xlmac_tx_ctrl *tx_ctrl);
+int ag_drv_lport_xlmac_tx_ctrl_get(uint8_t port_id, lport_xlmac_tx_ctrl *tx_ctrl);
+int ag_drv_lport_xlmac_tx_ctrl_overlay_set(uint8_t port_id, uint16_t xlmac_tx_ctrl_hi, uint32_t xlmac_tx_ctrl_lo);
+int ag_drv_lport_xlmac_tx_ctrl_overlay_get(uint8_t port_id, uint16_t *xlmac_tx_ctrl_hi, uint32_t *xlmac_tx_ctrl_lo);
+int ag_drv_lport_xlmac_tx_mac_sa_set(uint8_t port_id, uint64_t ctrl_sa);
+int ag_drv_lport_xlmac_tx_mac_sa_get(uint8_t port_id, uint64_t *ctrl_sa);
+int ag_drv_lport_xlmac_tx_mac_sa_overlay_set(uint8_t port_id, uint16_t sa_hi, uint32_t sa_lo);
+int ag_drv_lport_xlmac_tx_mac_sa_overlay_get(uint8_t port_id, uint16_t *sa_hi, uint32_t *sa_lo);
+int ag_drv_lport_xlmac_rx_ctrl_set(uint8_t port_id, const lport_xlmac_rx_ctrl *rx_ctrl);
+int ag_drv_lport_xlmac_rx_ctrl_get(uint8_t port_id, lport_xlmac_rx_ctrl *rx_ctrl);
+int ag_drv_lport_xlmac_rx_mac_sa_set(uint8_t port_id, uint64_t rx_sa);
+int ag_drv_lport_xlmac_rx_mac_sa_get(uint8_t port_id, uint64_t *rx_sa);
+int ag_drv_lport_xlmac_rx_mac_sa_overlay_set(uint8_t port_id, uint16_t sa_hi, uint32_t sa_lo);
+int ag_drv_lport_xlmac_rx_mac_sa_overlay_get(uint8_t port_id, uint16_t *sa_hi, uint32_t *sa_lo);
+int ag_drv_lport_xlmac_rx_max_size_set(uint8_t port_id, uint16_t rx_max_size);
+int ag_drv_lport_xlmac_rx_max_size_get(uint8_t port_id, uint16_t *rx_max_size);
+int ag_drv_lport_xlmac_rx_vlan_tag_set(uint8_t port_id, uint8_t outer_vlan_tag_enable, uint8_t inner_vlan_tag_enable, uint16_t outer_vlan_tag, uint16_t inner_vlan_tag);
+int ag_drv_lport_xlmac_rx_vlan_tag_get(uint8_t port_id, uint8_t *outer_vlan_tag_enable, uint8_t *inner_vlan_tag_enable, uint16_t *outer_vlan_tag, uint16_t *inner_vlan_tag);
+int ag_drv_lport_xlmac_rx_lss_ctrl_set(uint8_t port_id, const lport_xlmac_rx_lss_ctrl *rx_lss_ctrl);
+int ag_drv_lport_xlmac_rx_lss_ctrl_get(uint8_t port_id, lport_xlmac_rx_lss_ctrl *rx_lss_ctrl);
+int ag_drv_lport_xlmac_rx_lss_status_get(uint8_t port_id, uint8_t *link_interruption_status, uint8_t *remote_fault_status, uint8_t *local_fault_status);
+int ag_drv_lport_xlmac_clear_rx_lss_status_set(uint8_t port_id, uint8_t clear_link_interruption_status, uint8_t clear_remote_fault_status, uint8_t clear_local_fault_status);
+int ag_drv_lport_xlmac_clear_rx_lss_status_get(uint8_t port_id, uint8_t *clear_link_interruption_status, uint8_t *clear_remote_fault_status, uint8_t *clear_local_fault_status);
+int ag_drv_lport_xlmac_pause_ctrl_set(uint8_t port_id, const lport_xlmac_pause_ctrl *pause_ctrl);
+int ag_drv_lport_xlmac_pause_ctrl_get(uint8_t port_id, lport_xlmac_pause_ctrl *pause_ctrl);
+int ag_drv_lport_xlmac_pause_ctrl_overlay_set(uint8_t port_id, uint8_t xlmac_pause_ctrl_hi, uint32_t xlmac_pause_ctrl_lo);
+int ag_drv_lport_xlmac_pause_ctrl_overlay_get(uint8_t port_id, uint8_t *xlmac_pause_ctrl_hi, uint32_t *xlmac_pause_ctrl_lo);
+int ag_drv_lport_xlmac_pfc_ctrl_set(uint8_t port_id, const lport_xlmac_pfc_ctrl *pfc_ctrl);
+int ag_drv_lport_xlmac_pfc_ctrl_get(uint8_t port_id, lport_xlmac_pfc_ctrl *pfc_ctrl);
+int ag_drv_lport_xlmac_pfc_ctrl_overlay_set(uint8_t port_id, uint8_t llfc_refresh_en, uint16_t llfc_refresh_timer);
+int ag_drv_lport_xlmac_pfc_ctrl_overlay_get(uint8_t port_id, uint8_t *llfc_refresh_en, uint16_t *llfc_refresh_timer);
+int ag_drv_lport_xlmac_pfc_type_set(uint8_t port_id, uint16_t pfc_eth_type);
+int ag_drv_lport_xlmac_pfc_type_get(uint8_t port_id, uint16_t *pfc_eth_type);
+int ag_drv_lport_xlmac_pfc_opcode_set(uint8_t port_id, uint16_t pfc_opcode);
+int ag_drv_lport_xlmac_pfc_opcode_get(uint8_t port_id, uint16_t *pfc_opcode);
+int ag_drv_lport_xlmac_pfc_da_set(uint8_t port_id, uint64_t pfc_macda);
+int ag_drv_lport_xlmac_pfc_da_get(uint8_t port_id, uint64_t *pfc_macda);
+int ag_drv_lport_xlmac_pfc_da_overlay_set(uint8_t port_id, uint16_t pfc_macda_hi, uint32_t pfc_macda_lo);
+int ag_drv_lport_xlmac_pfc_da_overlay_get(uint8_t port_id, uint16_t *pfc_macda_hi, uint32_t *pfc_macda_lo);
+int ag_drv_lport_xlmac_llfc_ctrl_set(uint8_t port_id, const lport_xlmac_llfc_ctrl *llfc_ctrl);
+int ag_drv_lport_xlmac_llfc_ctrl_get(uint8_t port_id, lport_xlmac_llfc_ctrl *llfc_ctrl);
+int ag_drv_lport_xlmac_tx_llfc_msg_fields_set(uint8_t port_id, uint16_t llfc_xoff_time, uint8_t tx_llfc_fc_obj_logical, uint8_t tx_llfc_msg_type_logical);
+int ag_drv_lport_xlmac_tx_llfc_msg_fields_get(uint8_t port_id, uint16_t *llfc_xoff_time, uint8_t *tx_llfc_fc_obj_logical, uint8_t *tx_llfc_msg_type_logical);
+int ag_drv_lport_xlmac_rx_llfc_msg_fields_set(uint8_t port_id, uint8_t rx_llfc_fc_obj_physical, uint8_t rx_llfc_msg_type_physical, uint8_t rx_llfc_fc_obj_logical, uint8_t rx_llfc_msg_type_logical);
+int ag_drv_lport_xlmac_rx_llfc_msg_fields_get(uint8_t port_id, uint8_t *rx_llfc_fc_obj_physical, uint8_t *rx_llfc_msg_type_physical, uint8_t *rx_llfc_fc_obj_logical, uint8_t *rx_llfc_msg_type_logical);
+int ag_drv_lport_xlmac_tx_timestamp_fifo_data_get(uint8_t port_id, uint8_t *ts_entry_valid, uint16_t *sequence_id, uint32_t *time_stamp);
+int ag_drv_lport_xlmac_tx_timestamp_fifo_status_get(uint8_t port_id, uint8_t *entry_count);
+int ag_drv_lport_xlmac_fifo_status_get(uint8_t port_id, lport_xlmac_fifo_status *fifo_status);
+int ag_drv_lport_xlmac_clear_fifo_status_set(uint8_t port_id, const lport_xlmac_clear_fifo_status *clear_fifo_status);
+int ag_drv_lport_xlmac_clear_fifo_status_get(uint8_t port_id, lport_xlmac_clear_fifo_status *clear_fifo_status);
+int ag_drv_lport_xlmac_lag_failover_status_get(uint8_t port_id, uint8_t *rsvd, uint8_t *lag_failover_loopback);
+int ag_drv_lport_xlmac_eee_ctrl_set(uint8_t port_id, uint8_t rsvd, uint8_t eee_en);
+int ag_drv_lport_xlmac_eee_ctrl_get(uint8_t port_id, uint8_t *rsvd, uint8_t *eee_en);
+int ag_drv_lport_xlmac_eee_timers_set(uint8_t port_id, uint16_t eee_ref_count, uint16_t eee_wake_timer, uint32_t eee_delay_entry_timer);
+int ag_drv_lport_xlmac_eee_timers_get(uint8_t port_id, uint16_t *eee_ref_count, uint16_t *eee_wake_timer, uint32_t *eee_delay_entry_timer);
+int ag_drv_lport_xlmac_eee_timers_overlay_set(uint8_t port_id, uint32_t xlmac_eee_timers_hi, uint32_t xlmac_eee_timers_lo);
+int ag_drv_lport_xlmac_eee_timers_overlay_get(uint8_t port_id, uint32_t *xlmac_eee_timers_hi, uint32_t *xlmac_eee_timers_lo);
+int ag_drv_lport_xlmac_eee_1_sec_link_status_timer_set(uint8_t port_id, uint32_t one_second_timer);
+int ag_drv_lport_xlmac_eee_1_sec_link_status_timer_get(uint8_t port_id, uint32_t *one_second_timer);
+int ag_drv_lport_xlmac_higig_hdr_0_set(uint8_t port_id, uint64_t higig_hdr_0);
+int ag_drv_lport_xlmac_higig_hdr_0_get(uint8_t port_id, uint64_t *higig_hdr_0);
+int ag_drv_lport_xlmac_higig_hdr_0_overlay_set(uint8_t port_id, uint32_t higig_hdr_0_hi, uint32_t higig_hdr_0_lo);
+int ag_drv_lport_xlmac_higig_hdr_0_overlay_get(uint8_t port_id, uint32_t *higig_hdr_0_hi, uint32_t *higig_hdr_0_lo);
+int ag_drv_lport_xlmac_higig_hdr_1_set(uint8_t port_id, uint64_t higig_hdr_1);
+int ag_drv_lport_xlmac_higig_hdr_1_get(uint8_t port_id, uint64_t *higig_hdr_1);
+int ag_drv_lport_xlmac_higig_hdr_1_overlay_set(uint8_t port_id, uint32_t higig_hdr_1_hi, uint32_t higig_hdr_1_lo);
+int ag_drv_lport_xlmac_higig_hdr_1_overlay_get(uint8_t port_id, uint32_t *higig_hdr_1_hi, uint32_t *higig_hdr_1_lo);
+int ag_drv_lport_xlmac_gmii_eee_ctrl_set(uint8_t port_id, uint8_t gmii_lpi_predict_mode_en, uint16_t gmii_lpi_predict_threshold);
+int ag_drv_lport_xlmac_gmii_eee_ctrl_get(uint8_t port_id, uint8_t *gmii_lpi_predict_mode_en, uint16_t *gmii_lpi_predict_threshold);
+int ag_drv_lport_xlmac_timestamp_adjust_set(uint8_t port_id, uint8_t ts_use_cs_offset, uint8_t ts_tsts_adjust, uint16_t ts_osts_adjust);
+int ag_drv_lport_xlmac_timestamp_adjust_get(uint8_t port_id, uint8_t *ts_use_cs_offset, uint8_t *ts_tsts_adjust, uint16_t *ts_osts_adjust);
+int ag_drv_lport_xlmac_timestamp_byte_adjust_set(uint8_t port_id, uint8_t rx_timer_byte_adjust_en, uint16_t rx_timer_byte_adjust, uint8_t tx_timer_byte_adjust_en, uint16_t tx_timer_byte_adjust);
+int ag_drv_lport_xlmac_timestamp_byte_adjust_get(uint8_t port_id, uint8_t *rx_timer_byte_adjust_en, uint16_t *rx_timer_byte_adjust, uint8_t *tx_timer_byte_adjust_en, uint16_t *tx_timer_byte_adjust);
+int ag_drv_lport_xlmac_tx_crc_corrupt_ctrl_set(uint8_t port_id, uint32_t prog_tx_crc, uint8_t tx_crc_corruption_mode, uint8_t tx_crc_corrupt_en, uint8_t tx_err_corrupts_crc);
+int ag_drv_lport_xlmac_tx_crc_corrupt_ctrl_get(uint8_t port_id, uint32_t *prog_tx_crc, uint8_t *tx_crc_corruption_mode, uint8_t *tx_crc_corrupt_en, uint8_t *tx_err_corrupts_crc);
+int ag_drv_lport_xlmac_tx_crc_corrupt_ctrl_overlay_set(uint8_t port_id, uint8_t xlmac_tx_crc_corrupt_ctrl_hi, uint32_t xlmac_tx_crc_corrupt_ctrl_lo);
+int ag_drv_lport_xlmac_tx_crc_corrupt_ctrl_overlay_get(uint8_t port_id, uint8_t *xlmac_tx_crc_corrupt_ctrl_hi, uint32_t *xlmac_tx_crc_corrupt_ctrl_lo);
+int ag_drv_lport_xlmac_e2e_ctrl_set(uint8_t port_id, const lport_xlmac_e2e_ctrl *e2e_ctrl);
+int ag_drv_lport_xlmac_e2e_ctrl_get(uint8_t port_id, lport_xlmac_e2e_ctrl *e2e_ctrl);
+int ag_drv_lport_xlmac_e2ecc_module_hdr_0_set(uint8_t port_id, uint64_t e2ecc_module_hdr_0);
+int ag_drv_lport_xlmac_e2ecc_module_hdr_0_get(uint8_t port_id, uint64_t *e2ecc_module_hdr_0);
+int ag_drv_lport_xlmac_e2ecc_module_hdr_0_overlay_set(uint8_t port_id, uint32_t e2ecc_module_hdr_0_hi, uint32_t e2ecc_module_hdr_0_lo);
+int ag_drv_lport_xlmac_e2ecc_module_hdr_0_overlay_get(uint8_t port_id, uint32_t *e2ecc_module_hdr_0_hi, uint32_t *e2ecc_module_hdr_0_lo);
+int ag_drv_lport_xlmac_e2ecc_module_hdr_1_set(uint8_t port_id, uint64_t e2ecc_module_hdr_1);
+int ag_drv_lport_xlmac_e2ecc_module_hdr_1_get(uint8_t port_id, uint64_t *e2ecc_module_hdr_1);
+int ag_drv_lport_xlmac_e2ecc_module_hdr_1_overlay_set(uint8_t port_id, uint32_t e2ecc_module_hdr_1_hi, uint32_t e2ecc_module_hdr_1_lo);
+int ag_drv_lport_xlmac_e2ecc_module_hdr_1_overlay_get(uint8_t port_id, uint32_t *e2ecc_module_hdr_1_hi, uint32_t *e2ecc_module_hdr_1_lo);
+int ag_drv_lport_xlmac_e2ecc_data_hdr_0_set(uint8_t port_id, uint64_t e2ecc_data_hdr_0);
+int ag_drv_lport_xlmac_e2ecc_data_hdr_0_get(uint8_t port_id, uint64_t *e2ecc_data_hdr_0);
+int ag_drv_lport_xlmac_e2ecc_data_hdr_0_overlay_set(uint8_t port_id, uint32_t e2ecc_data_hdr_0_hi, uint32_t e2ecc_data_hdr_0_lo);
+int ag_drv_lport_xlmac_e2ecc_data_hdr_0_overlay_get(uint8_t port_id, uint32_t *e2ecc_data_hdr_0_hi, uint32_t *e2ecc_data_hdr_0_lo);
+int ag_drv_lport_xlmac_e2ecc_data_hdr_1_set(uint8_t port_id, uint64_t e2ecc_data_hdr_1);
+int ag_drv_lport_xlmac_e2ecc_data_hdr_1_get(uint8_t port_id, uint64_t *e2ecc_data_hdr_1);
+int ag_drv_lport_xlmac_e2ecc_data_hdr_1_overlay_set(uint8_t port_id, uint32_t e2ecc_data_hdr_1_hi, uint32_t e2ecc_data_hdr_1_lo);
+int ag_drv_lport_xlmac_e2ecc_data_hdr_1_overlay_get(uint8_t port_id, uint32_t *e2ecc_data_hdr_1_hi, uint32_t *e2ecc_data_hdr_1_lo);
+int ag_drv_lport_xlmac_e2efc_module_hdr_0_set(uint8_t port_id, uint64_t e2efc_module_hdr_0);
+int ag_drv_lport_xlmac_e2efc_module_hdr_0_get(uint8_t port_id, uint64_t *e2efc_module_hdr_0);
+int ag_drv_lport_xlmac_e2efc_module_hdr_0_overlay_set(uint8_t port_id, uint32_t e2efc_module_hdr_0_hi, uint32_t e2efc_module_hdr_0_lo);
+int ag_drv_lport_xlmac_e2efc_module_hdr_0_overlay_get(uint8_t port_id, uint32_t *e2efc_module_hdr_0_hi, uint32_t *e2efc_module_hdr_0_lo);
+int ag_drv_lport_xlmac_e2efc_module_hdr_1_set(uint8_t port_id, uint64_t e2efc_module_hdr_1);
+int ag_drv_lport_xlmac_e2efc_module_hdr_1_get(uint8_t port_id, uint64_t *e2efc_module_hdr_1);
+int ag_drv_lport_xlmac_e2efc_module_hdr_1_overlay_set(uint8_t port_id, uint32_t e2efc_module_hdr_1_hi, uint32_t e2efc_module_hdr_1_lo);
+int ag_drv_lport_xlmac_e2efc_module_hdr_1_overlay_get(uint8_t port_id, uint32_t *e2efc_module_hdr_1_hi, uint32_t *e2efc_module_hdr_1_lo);
+int ag_drv_lport_xlmac_e2efc_data_hdr_0_set(uint8_t port_id, uint64_t e2efc_data_hdr_0);
+int ag_drv_lport_xlmac_e2efc_data_hdr_0_get(uint8_t port_id, uint64_t *e2efc_data_hdr_0);
+int ag_drv_lport_xlmac_e2efc_data_hdr_0_overlay_set(uint8_t port_id, uint32_t e2efc_data_hdr_0_hi, uint32_t e2efc_data_hdr_0_lo);
+int ag_drv_lport_xlmac_e2efc_data_hdr_0_overlay_get(uint8_t port_id, uint32_t *e2efc_data_hdr_0_hi, uint32_t *e2efc_data_hdr_0_lo);
+int ag_drv_lport_xlmac_e2efc_data_hdr_1_set(uint8_t port_id, uint64_t e2efc_data_hdr_1);
+int ag_drv_lport_xlmac_e2efc_data_hdr_1_get(uint8_t port_id, uint64_t *e2efc_data_hdr_1);
+int ag_drv_lport_xlmac_e2efc_data_hdr_1_overlay_set(uint8_t port_id, uint32_t e2efc_data_hdr_1_hi, uint32_t e2efc_data_hdr_1_lo);
+int ag_drv_lport_xlmac_e2efc_data_hdr_1_overlay_get(uint8_t port_id, uint32_t *e2efc_data_hdr_1_hi, uint32_t *e2efc_data_hdr_1_lo);
+int ag_drv_lport_xlmac_txfifo_cell_cnt_get(uint8_t port_id, uint8_t *cell_cnt);
+int ag_drv_lport_xlmac_txfifo_cell_req_cnt_get(uint8_t port_id, uint8_t *req_cnt);
+int ag_drv_lport_xlmac_mem_ctrl_set(uint8_t port_id, uint16_t tx_cdc_mem_ctrl_tm, uint16_t rx_cdc_mem_ctrl_tm);
+int ag_drv_lport_xlmac_mem_ctrl_get(uint8_t port_id, uint16_t *tx_cdc_mem_ctrl_tm, uint16_t *rx_cdc_mem_ctrl_tm);
+int ag_drv_lport_xlmac_ecc_ctrl_set(uint8_t port_id, uint8_t tx_cdc_ecc_ctrl_en, uint8_t rx_cdc_ecc_ctrl_en);
+int ag_drv_lport_xlmac_ecc_ctrl_get(uint8_t port_id, uint8_t *tx_cdc_ecc_ctrl_en, uint8_t *rx_cdc_ecc_ctrl_en);
+int ag_drv_lport_xlmac_ecc_force_double_bit_err_set(uint8_t port_id, uint8_t tx_cdc_force_double_bit_err, uint8_t rx_cdc_force_double_bit_err);
+int ag_drv_lport_xlmac_ecc_force_double_bit_err_get(uint8_t port_id, uint8_t *tx_cdc_force_double_bit_err, uint8_t *rx_cdc_force_double_bit_err);
+int ag_drv_lport_xlmac_ecc_force_single_bit_err_set(uint8_t port_id, uint8_t tx_cdc_force_single_bit_err, uint8_t rx_cdc_force_single_bit_err);
+int ag_drv_lport_xlmac_ecc_force_single_bit_err_get(uint8_t port_id, uint8_t *tx_cdc_force_single_bit_err, uint8_t *rx_cdc_force_single_bit_err);
+int ag_drv_lport_xlmac_rx_cdc_ecc_status_get(uint8_t port_id, uint8_t *rx_cdc_double_bit_err, uint8_t *rx_cdc_single_bit_err);
+int ag_drv_lport_xlmac_tx_cdc_ecc_status_get(uint8_t port_id, uint8_t *tx_cdc_double_bit_err, uint8_t *tx_cdc_single_bit_err);
+int ag_drv_lport_xlmac_clear_ecc_status_set(uint8_t port_id, uint8_t clear_tx_cdc_double_bit_err, uint8_t clear_tx_cdc_single_bit_err, uint8_t clear_rx_cdc_double_bit_err, uint8_t clear_rx_cdc_single_bit_err);
+int ag_drv_lport_xlmac_clear_ecc_status_get(uint8_t port_id, uint8_t *clear_tx_cdc_double_bit_err, uint8_t *clear_tx_cdc_single_bit_err, uint8_t *clear_rx_cdc_double_bit_err, uint8_t *clear_rx_cdc_single_bit_err);
+int ag_drv_lport_xlmac_intr_status_get(uint8_t port_id, lport_xlmac_intr_status *intr_status);
+int ag_drv_lport_xlmac_intr_enable_set(uint8_t port_id, const lport_xlmac_intr_enable *intr_enable);
+int ag_drv_lport_xlmac_intr_enable_get(uint8_t port_id, lport_xlmac_intr_enable *intr_enable);
+int ag_drv_lport_xlmac_version_id_get(uint8_t port_id, uint16_t *xlmac_version);
+
+#ifdef USE_BDMF_SHELL
+bdmfmon_handle_t ag_drv_lport_xlmac_cli_init(bdmfmon_handle_t driver_dir);
+#endif
+
+
+#endif
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_mib_conf_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_mib_conf_ag.c
new file mode 100644
index 0000000000..c529111cec
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_mib_conf_ag.c
@@ -0,0 +1,1099 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_mib_conf_ag.h"
+#define BLOCK_ADDR_COUNT_BITS 1
+#define BLOCK_ADDR_COUNT (1<<BLOCK_ADDR_COUNT_BITS)
+
+int ag_drv_mib_conf_mib0_write_holding_set(uint8_t xlmac_id, uint32_t write_data)
+{
+    uint32_t reg_dir_acc_data_write=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_dir_acc_data_write = RU_FIELD_SET(xlmac_id, MIB_CONF, DIR_ACC_DATA_WRITE, WRITE_DATA, reg_dir_acc_data_write, write_data);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, DIR_ACC_DATA_WRITE, reg_dir_acc_data_write);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_mib0_write_holding_get(uint8_t xlmac_id, uint32_t *write_data)
+{
+    uint32_t reg_dir_acc_data_write=0;
+
+#ifdef VALIDATE_PARMS
+    if(!write_data)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, DIR_ACC_DATA_WRITE, reg_dir_acc_data_write);
+
+    *write_data = RU_FIELD_GET(xlmac_id, MIB_CONF, DIR_ACC_DATA_WRITE, WRITE_DATA, reg_dir_acc_data_write);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_mib0_read_holding_set(uint8_t xlmac_id, uint32_t read_data)
+{
+    uint32_t reg_dir_acc_data_read=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_dir_acc_data_read = RU_FIELD_SET(xlmac_id, MIB_CONF, DIR_ACC_DATA_READ, READ_DATA, reg_dir_acc_data_read, read_data);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, DIR_ACC_DATA_READ, reg_dir_acc_data_read);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_mib0_read_holding_get(uint8_t xlmac_id, uint32_t *read_data)
+{
+    uint32_t reg_dir_acc_data_read=0;
+
+#ifdef VALIDATE_PARMS
+    if(!read_data)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, DIR_ACC_DATA_READ, reg_dir_acc_data_read);
+
+    *read_data = RU_FIELD_GET(xlmac_id, MIB_CONF, DIR_ACC_DATA_READ, READ_DATA, reg_dir_acc_data_read);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_addr_0_set(uint8_t xlmac_id, const mib_conf_indir_acc_addr_0 *indir_acc_addr_0)
+{
+    uint32_t reg_indir_acc_addr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!indir_acc_addr_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (indir_acc_addr_0->err >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_0->start_busy >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_0->r_w >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_0->reg_port_id >= _2BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_addr_0 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, ERR, reg_indir_acc_addr_0, indir_acc_addr_0->err);
+    reg_indir_acc_addr_0 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, START_BUSY, reg_indir_acc_addr_0, indir_acc_addr_0->start_busy);
+    reg_indir_acc_addr_0 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, R_W, reg_indir_acc_addr_0, indir_acc_addr_0->r_w);
+    reg_indir_acc_addr_0 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, REG_PORT_ID, reg_indir_acc_addr_0, indir_acc_addr_0->reg_port_id);
+    reg_indir_acc_addr_0 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, REG_OFFSET, reg_indir_acc_addr_0, indir_acc_addr_0->reg_offset);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, reg_indir_acc_addr_0);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_addr_0_get(uint8_t xlmac_id, mib_conf_indir_acc_addr_0 *indir_acc_addr_0)
+{
+    uint32_t reg_indir_acc_addr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!indir_acc_addr_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, reg_indir_acc_addr_0);
+
+    indir_acc_addr_0->err = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, ERR, reg_indir_acc_addr_0);
+    indir_acc_addr_0->start_busy = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, START_BUSY, reg_indir_acc_addr_0);
+    indir_acc_addr_0->r_w = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, R_W, reg_indir_acc_addr_0);
+    indir_acc_addr_0->reg_port_id = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, REG_PORT_ID, reg_indir_acc_addr_0);
+    indir_acc_addr_0->reg_offset = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_0, REG_OFFSET, reg_indir_acc_addr_0);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_data_low_0_set(uint8_t xlmac_id, uint32_t data_low)
+{
+    uint32_t reg_indir_acc_data_low_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_data_low_0 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_DATA_LOW_0, DATA_LOW, reg_indir_acc_data_low_0, data_low);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, INDIR_ACC_DATA_LOW_0, reg_indir_acc_data_low_0);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_data_low_0_get(uint8_t xlmac_id, uint32_t *data_low)
+{
+    uint32_t reg_indir_acc_data_low_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!data_low)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, INDIR_ACC_DATA_LOW_0, reg_indir_acc_data_low_0);
+
+    *data_low = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_DATA_LOW_0, DATA_LOW, reg_indir_acc_data_low_0);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_data_high_0_set(uint8_t xlmac_id, uint32_t data_high)
+{
+    uint32_t reg_indir_acc_data_high_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_data_high_0 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_DATA_HIGH_0, DATA_HIGH, reg_indir_acc_data_high_0, data_high);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, INDIR_ACC_DATA_HIGH_0, reg_indir_acc_data_high_0);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_data_high_0_get(uint8_t xlmac_id, uint32_t *data_high)
+{
+    uint32_t reg_indir_acc_data_high_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!data_high)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, INDIR_ACC_DATA_HIGH_0, reg_indir_acc_data_high_0);
+
+    *data_high = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_DATA_HIGH_0, DATA_HIGH, reg_indir_acc_data_high_0);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_addr_1_set(uint8_t xlmac_id, const mib_conf_indir_acc_addr_1 *indir_acc_addr_1)
+{
+    uint32_t reg_indir_acc_addr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!indir_acc_addr_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (indir_acc_addr_1->err >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_1->start_busy >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_1->r_w >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_1->reg_port_id >= _2BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_addr_1 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, ERR, reg_indir_acc_addr_1, indir_acc_addr_1->err);
+    reg_indir_acc_addr_1 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, START_BUSY, reg_indir_acc_addr_1, indir_acc_addr_1->start_busy);
+    reg_indir_acc_addr_1 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, R_W, reg_indir_acc_addr_1, indir_acc_addr_1->r_w);
+    reg_indir_acc_addr_1 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, REG_PORT_ID, reg_indir_acc_addr_1, indir_acc_addr_1->reg_port_id);
+    reg_indir_acc_addr_1 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, REG_OFFSET, reg_indir_acc_addr_1, indir_acc_addr_1->reg_offset);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, reg_indir_acc_addr_1);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_addr_1_get(uint8_t xlmac_id, mib_conf_indir_acc_addr_1 *indir_acc_addr_1)
+{
+    uint32_t reg_indir_acc_addr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!indir_acc_addr_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, reg_indir_acc_addr_1);
+
+    indir_acc_addr_1->err = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, ERR, reg_indir_acc_addr_1);
+    indir_acc_addr_1->start_busy = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, START_BUSY, reg_indir_acc_addr_1);
+    indir_acc_addr_1->r_w = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, R_W, reg_indir_acc_addr_1);
+    indir_acc_addr_1->reg_port_id = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, REG_PORT_ID, reg_indir_acc_addr_1);
+    indir_acc_addr_1->reg_offset = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_ADDR_1, REG_OFFSET, reg_indir_acc_addr_1);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_data_low_1_set(uint8_t xlmac_id, uint32_t data_low)
+{
+    uint32_t reg_indir_acc_data_low_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_data_low_1 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_DATA_LOW_1, DATA_LOW, reg_indir_acc_data_low_1, data_low);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, INDIR_ACC_DATA_LOW_1, reg_indir_acc_data_low_1);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_data_low_1_get(uint8_t xlmac_id, uint32_t *data_low)
+{
+    uint32_t reg_indir_acc_data_low_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!data_low)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, INDIR_ACC_DATA_LOW_1, reg_indir_acc_data_low_1);
+
+    *data_low = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_DATA_LOW_1, DATA_LOW, reg_indir_acc_data_low_1);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_data_high_1_set(uint8_t xlmac_id, uint32_t data_high)
+{
+    uint32_t reg_indir_acc_data_high_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_data_high_1 = RU_FIELD_SET(xlmac_id, MIB_CONF, INDIR_ACC_DATA_HIGH_1, DATA_HIGH, reg_indir_acc_data_high_1, data_high);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, INDIR_ACC_DATA_HIGH_1, reg_indir_acc_data_high_1);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_indir_acc_data_high_1_get(uint8_t xlmac_id, uint32_t *data_high)
+{
+    uint32_t reg_indir_acc_data_high_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!data_high)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, INDIR_ACC_DATA_HIGH_1, reg_indir_acc_data_high_1);
+
+    *data_high = RU_FIELD_GET(xlmac_id, MIB_CONF, INDIR_ACC_DATA_HIGH_1, DATA_HIGH, reg_indir_acc_data_high_1);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_control_set(uint8_t xlmac_id, uint8_t eee_cnt_mode, uint8_t saturate_en, uint8_t cor_en, uint8_t cnt_rst)
+{
+    uint32_t reg_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (eee_cnt_mode >= _4BITS_MAX_VAL_) ||
+       (saturate_en >= _4BITS_MAX_VAL_) ||
+       (cor_en >= _4BITS_MAX_VAL_) ||
+       (cnt_rst >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_cntrl = RU_FIELD_SET(xlmac_id, MIB_CONF, CNTRL, EEE_CNT_MODE, reg_cntrl, eee_cnt_mode);
+    reg_cntrl = RU_FIELD_SET(xlmac_id, MIB_CONF, CNTRL, SATURATE_EN, reg_cntrl, saturate_en);
+    reg_cntrl = RU_FIELD_SET(xlmac_id, MIB_CONF, CNTRL, COR_EN, reg_cntrl, cor_en);
+    reg_cntrl = RU_FIELD_SET(xlmac_id, MIB_CONF, CNTRL, CNT_RST, reg_cntrl, cnt_rst);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, CNTRL, reg_cntrl);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_control_get(uint8_t xlmac_id, uint8_t *eee_cnt_mode, uint8_t *saturate_en, uint8_t *cor_en, uint8_t *cnt_rst)
+{
+    uint32_t reg_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!eee_cnt_mode || !saturate_en || !cor_en || !cnt_rst)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, CNTRL, reg_cntrl);
+
+    *eee_cnt_mode = RU_FIELD_GET(xlmac_id, MIB_CONF, CNTRL, EEE_CNT_MODE, reg_cntrl);
+    *saturate_en = RU_FIELD_GET(xlmac_id, MIB_CONF, CNTRL, SATURATE_EN, reg_cntrl);
+    *cor_en = RU_FIELD_GET(xlmac_id, MIB_CONF, CNTRL, COR_EN, reg_cntrl);
+    *cnt_rst = RU_FIELD_GET(xlmac_id, MIB_CONF, CNTRL, CNT_RST, reg_cntrl);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_eee_pulse_duration_cntrl_set(uint8_t xlmac_id, uint8_t cnt)
+{
+    uint32_t reg_eee_pulse_duration_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_eee_pulse_duration_cntrl = RU_FIELD_SET(xlmac_id, MIB_CONF, EEE_PULSE_DURATION_CNTRL, CNT, reg_eee_pulse_duration_cntrl, cnt);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, EEE_PULSE_DURATION_CNTRL, reg_eee_pulse_duration_cntrl);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_eee_pulse_duration_cntrl_get(uint8_t xlmac_id, uint8_t *cnt)
+{
+    uint32_t reg_eee_pulse_duration_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!cnt)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, EEE_PULSE_DURATION_CNTRL, reg_eee_pulse_duration_cntrl);
+
+    *cnt = RU_FIELD_GET(xlmac_id, MIB_CONF, EEE_PULSE_DURATION_CNTRL, CNT, reg_eee_pulse_duration_cntrl);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_gport0_max_pkt_size_set(uint8_t xlmac_id, uint16_t max_pkt_size)
+{
+    uint32_t reg_gport0_max_pkt_size=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (max_pkt_size >= _14BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gport0_max_pkt_size = RU_FIELD_SET(xlmac_id, MIB_CONF, GPORT0_MAX_PKT_SIZE, MAX_PKT_SIZE, reg_gport0_max_pkt_size, max_pkt_size);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, GPORT0_MAX_PKT_SIZE, reg_gport0_max_pkt_size);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_gport0_max_pkt_size_get(uint8_t xlmac_id, uint16_t *max_pkt_size)
+{
+    uint32_t reg_gport0_max_pkt_size=0;
+
+#ifdef VALIDATE_PARMS
+    if(!max_pkt_size)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, GPORT0_MAX_PKT_SIZE, reg_gport0_max_pkt_size);
+
+    *max_pkt_size = RU_FIELD_GET(xlmac_id, MIB_CONF, GPORT0_MAX_PKT_SIZE, MAX_PKT_SIZE, reg_gport0_max_pkt_size);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_gport1_max_pkt_size_set(uint8_t xlmac_id, uint16_t max_pkt_size)
+{
+    uint32_t reg_gport1_max_pkt_size=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (max_pkt_size >= _14BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gport1_max_pkt_size = RU_FIELD_SET(xlmac_id, MIB_CONF, GPORT1_MAX_PKT_SIZE, MAX_PKT_SIZE, reg_gport1_max_pkt_size, max_pkt_size);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, GPORT1_MAX_PKT_SIZE, reg_gport1_max_pkt_size);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_gport1_max_pkt_size_get(uint8_t xlmac_id, uint16_t *max_pkt_size)
+{
+    uint32_t reg_gport1_max_pkt_size=0;
+
+#ifdef VALIDATE_PARMS
+    if(!max_pkt_size)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, GPORT1_MAX_PKT_SIZE, reg_gport1_max_pkt_size);
+
+    *max_pkt_size = RU_FIELD_GET(xlmac_id, MIB_CONF, GPORT1_MAX_PKT_SIZE, MAX_PKT_SIZE, reg_gport1_max_pkt_size);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_gport2_max_pkt_size_set(uint8_t xlmac_id, uint16_t max_pkt_size)
+{
+    uint32_t reg_gport2_max_pkt_size=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (max_pkt_size >= _14BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gport2_max_pkt_size = RU_FIELD_SET(xlmac_id, MIB_CONF, GPORT2_MAX_PKT_SIZE, MAX_PKT_SIZE, reg_gport2_max_pkt_size, max_pkt_size);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, GPORT2_MAX_PKT_SIZE, reg_gport2_max_pkt_size);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_gport2_max_pkt_size_get(uint8_t xlmac_id, uint16_t *max_pkt_size)
+{
+    uint32_t reg_gport2_max_pkt_size=0;
+
+#ifdef VALIDATE_PARMS
+    if(!max_pkt_size)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, GPORT2_MAX_PKT_SIZE, reg_gport2_max_pkt_size);
+
+    *max_pkt_size = RU_FIELD_GET(xlmac_id, MIB_CONF, GPORT2_MAX_PKT_SIZE, MAX_PKT_SIZE, reg_gport2_max_pkt_size);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_gport3_max_pkt_size_set(uint8_t xlmac_id, uint16_t max_pkt_size)
+{
+    uint32_t reg_gport3_max_pkt_size=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (max_pkt_size >= _14BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_gport3_max_pkt_size = RU_FIELD_SET(xlmac_id, MIB_CONF, GPORT3_MAX_PKT_SIZE, MAX_PKT_SIZE, reg_gport3_max_pkt_size, max_pkt_size);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, GPORT3_MAX_PKT_SIZE, reg_gport3_max_pkt_size);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_gport3_max_pkt_size_get(uint8_t xlmac_id, uint16_t *max_pkt_size)
+{
+    uint32_t reg_gport3_max_pkt_size=0;
+
+#ifdef VALIDATE_PARMS
+    if(!max_pkt_size)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, GPORT3_MAX_PKT_SIZE, reg_gport3_max_pkt_size);
+
+    *max_pkt_size = RU_FIELD_GET(xlmac_id, MIB_CONF, GPORT3_MAX_PKT_SIZE, MAX_PKT_SIZE, reg_gport3_max_pkt_size);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_ecc_cntrl_set(uint8_t xlmac_id, uint8_t tx_mib_ecc_en, uint8_t rx_mib_ecc_en)
+{
+    uint32_t reg_ecc_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (tx_mib_ecc_en >= _1BITS_MAX_VAL_) ||
+       (rx_mib_ecc_en >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_ecc_cntrl = RU_FIELD_SET(xlmac_id, MIB_CONF, ECC_CNTRL, TX_MIB_ECC_EN, reg_ecc_cntrl, tx_mib_ecc_en);
+    reg_ecc_cntrl = RU_FIELD_SET(xlmac_id, MIB_CONF, ECC_CNTRL, RX_MIB_ECC_EN, reg_ecc_cntrl, rx_mib_ecc_en);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, ECC_CNTRL, reg_ecc_cntrl);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_ecc_cntrl_get(uint8_t xlmac_id, uint8_t *tx_mib_ecc_en, uint8_t *rx_mib_ecc_en)
+{
+    uint32_t reg_ecc_cntrl=0;
+
+#ifdef VALIDATE_PARMS
+    if(!tx_mib_ecc_en || !rx_mib_ecc_en)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, ECC_CNTRL, reg_ecc_cntrl);
+
+    *tx_mib_ecc_en = RU_FIELD_GET(xlmac_id, MIB_CONF, ECC_CNTRL, TX_MIB_ECC_EN, reg_ecc_cntrl);
+    *rx_mib_ecc_en = RU_FIELD_GET(xlmac_id, MIB_CONF, ECC_CNTRL, RX_MIB_ECC_EN, reg_ecc_cntrl);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_force_sb_ecc_err_set(uint8_t xlmac_id, const mib_conf_force_sb_ecc_err *force_sb_ecc_err)
+{
+    uint32_t reg_force_sb_ecc_err=0;
+
+#ifdef VALIDATE_PARMS
+    if(!force_sb_ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (force_sb_ecc_err->force_tx_mem3_serr >= _1BITS_MAX_VAL_) ||
+       (force_sb_ecc_err->force_tx_mem2_serr >= _1BITS_MAX_VAL_) ||
+       (force_sb_ecc_err->force_tx_mem1_serr >= _1BITS_MAX_VAL_) ||
+       (force_sb_ecc_err->force_tx_mem0_serr >= _1BITS_MAX_VAL_) ||
+       (force_sb_ecc_err->force_rx_mem4_serr >= _1BITS_MAX_VAL_) ||
+       (force_sb_ecc_err->force_rx_mem3_serr >= _1BITS_MAX_VAL_) ||
+       (force_sb_ecc_err->force_rx_mem2_serr >= _1BITS_MAX_VAL_) ||
+       (force_sb_ecc_err->force_rx_mem1_serr >= _1BITS_MAX_VAL_) ||
+       (force_sb_ecc_err->force_rx_mem0_serr >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_force_sb_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_TX_MEM3_SERR, reg_force_sb_ecc_err, force_sb_ecc_err->force_tx_mem3_serr);
+    reg_force_sb_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_TX_MEM2_SERR, reg_force_sb_ecc_err, force_sb_ecc_err->force_tx_mem2_serr);
+    reg_force_sb_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_TX_MEM1_SERR, reg_force_sb_ecc_err, force_sb_ecc_err->force_tx_mem1_serr);
+    reg_force_sb_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_TX_MEM0_SERR, reg_force_sb_ecc_err, force_sb_ecc_err->force_tx_mem0_serr);
+    reg_force_sb_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_RX_MEM4_SERR, reg_force_sb_ecc_err, force_sb_ecc_err->force_rx_mem4_serr);
+    reg_force_sb_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_RX_MEM3_SERR, reg_force_sb_ecc_err, force_sb_ecc_err->force_rx_mem3_serr);
+    reg_force_sb_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_RX_MEM2_SERR, reg_force_sb_ecc_err, force_sb_ecc_err->force_rx_mem2_serr);
+    reg_force_sb_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_RX_MEM1_SERR, reg_force_sb_ecc_err, force_sb_ecc_err->force_rx_mem1_serr);
+    reg_force_sb_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_RX_MEM0_SERR, reg_force_sb_ecc_err, force_sb_ecc_err->force_rx_mem0_serr);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, reg_force_sb_ecc_err);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_force_sb_ecc_err_get(uint8_t xlmac_id, mib_conf_force_sb_ecc_err *force_sb_ecc_err)
+{
+    uint32_t reg_force_sb_ecc_err=0;
+
+#ifdef VALIDATE_PARMS
+    if(!force_sb_ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, reg_force_sb_ecc_err);
+
+    force_sb_ecc_err->force_tx_mem3_serr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_TX_MEM3_SERR, reg_force_sb_ecc_err);
+    force_sb_ecc_err->force_tx_mem2_serr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_TX_MEM2_SERR, reg_force_sb_ecc_err);
+    force_sb_ecc_err->force_tx_mem1_serr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_TX_MEM1_SERR, reg_force_sb_ecc_err);
+    force_sb_ecc_err->force_tx_mem0_serr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_TX_MEM0_SERR, reg_force_sb_ecc_err);
+    force_sb_ecc_err->force_rx_mem4_serr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_RX_MEM4_SERR, reg_force_sb_ecc_err);
+    force_sb_ecc_err->force_rx_mem3_serr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_RX_MEM3_SERR, reg_force_sb_ecc_err);
+    force_sb_ecc_err->force_rx_mem2_serr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_RX_MEM2_SERR, reg_force_sb_ecc_err);
+    force_sb_ecc_err->force_rx_mem1_serr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_RX_MEM1_SERR, reg_force_sb_ecc_err);
+    force_sb_ecc_err->force_rx_mem0_serr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_SB_ECC_ERR, FORCE_RX_MEM0_SERR, reg_force_sb_ecc_err);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_force_db_ecc_err_set(uint8_t xlmac_id, const mib_conf_force_db_ecc_err *force_db_ecc_err)
+{
+    uint32_t reg_force_db_ecc_err=0;
+
+#ifdef VALIDATE_PARMS
+    if(!force_db_ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (force_db_ecc_err->force_tx_mem3_derr >= _1BITS_MAX_VAL_) ||
+       (force_db_ecc_err->force_tx_mem2_derr >= _1BITS_MAX_VAL_) ||
+       (force_db_ecc_err->force_tx_mem1_derr >= _1BITS_MAX_VAL_) ||
+       (force_db_ecc_err->force_tx_mem0_derr >= _1BITS_MAX_VAL_) ||
+       (force_db_ecc_err->force_rx_mem4_derr >= _1BITS_MAX_VAL_) ||
+       (force_db_ecc_err->force_rx_mem3_derr >= _1BITS_MAX_VAL_) ||
+       (force_db_ecc_err->force_rx_mem2_derr >= _1BITS_MAX_VAL_) ||
+       (force_db_ecc_err->force_rx_mem1_derr >= _1BITS_MAX_VAL_) ||
+       (force_db_ecc_err->force_rx_mem0_derr >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_force_db_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_TX_MEM3_DERR, reg_force_db_ecc_err, force_db_ecc_err->force_tx_mem3_derr);
+    reg_force_db_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_TX_MEM2_DERR, reg_force_db_ecc_err, force_db_ecc_err->force_tx_mem2_derr);
+    reg_force_db_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_TX_MEM1_DERR, reg_force_db_ecc_err, force_db_ecc_err->force_tx_mem1_derr);
+    reg_force_db_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_TX_MEM0_DERR, reg_force_db_ecc_err, force_db_ecc_err->force_tx_mem0_derr);
+    reg_force_db_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_RX_MEM4_DERR, reg_force_db_ecc_err, force_db_ecc_err->force_rx_mem4_derr);
+    reg_force_db_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_RX_MEM3_DERR, reg_force_db_ecc_err, force_db_ecc_err->force_rx_mem3_derr);
+    reg_force_db_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_RX_MEM2_DERR, reg_force_db_ecc_err, force_db_ecc_err->force_rx_mem2_derr);
+    reg_force_db_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_RX_MEM1_DERR, reg_force_db_ecc_err, force_db_ecc_err->force_rx_mem1_derr);
+    reg_force_db_ecc_err = RU_FIELD_SET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_RX_MEM0_DERR, reg_force_db_ecc_err, force_db_ecc_err->force_rx_mem0_derr);
+
+    RU_REG_WRITE(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, reg_force_db_ecc_err);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_force_db_ecc_err_get(uint8_t xlmac_id, mib_conf_force_db_ecc_err *force_db_ecc_err)
+{
+    uint32_t reg_force_db_ecc_err=0;
+
+#ifdef VALIDATE_PARMS
+    if(!force_db_ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, reg_force_db_ecc_err);
+
+    force_db_ecc_err->force_tx_mem3_derr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_TX_MEM3_DERR, reg_force_db_ecc_err);
+    force_db_ecc_err->force_tx_mem2_derr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_TX_MEM2_DERR, reg_force_db_ecc_err);
+    force_db_ecc_err->force_tx_mem1_derr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_TX_MEM1_DERR, reg_force_db_ecc_err);
+    force_db_ecc_err->force_tx_mem0_derr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_TX_MEM0_DERR, reg_force_db_ecc_err);
+    force_db_ecc_err->force_rx_mem4_derr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_RX_MEM4_DERR, reg_force_db_ecc_err);
+    force_db_ecc_err->force_rx_mem3_derr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_RX_MEM3_DERR, reg_force_db_ecc_err);
+    force_db_ecc_err->force_rx_mem2_derr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_RX_MEM2_DERR, reg_force_db_ecc_err);
+    force_db_ecc_err->force_rx_mem1_derr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_RX_MEM1_DERR, reg_force_db_ecc_err);
+    force_db_ecc_err->force_rx_mem0_derr = RU_FIELD_GET(xlmac_id, MIB_CONF, FORCE_DB_ECC_ERR, FORCE_RX_MEM0_DERR, reg_force_db_ecc_err);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_rx_mem0_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err)
+{
+    uint32_t reg_rx_mem0_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mem_addr || !double_bit_ecc_err || !multi_ecc_err || !ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, RX_MEM0_ECC_STATUS, reg_rx_mem0_ecc_status);
+
+    *mem_addr = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM0_ECC_STATUS, MEM_ADDR, reg_rx_mem0_ecc_status);
+    *double_bit_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM0_ECC_STATUS, DOUBLE_BIT_ECC_ERR, reg_rx_mem0_ecc_status);
+    *multi_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM0_ECC_STATUS, MULTI_ECC_ERR, reg_rx_mem0_ecc_status);
+    *ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM0_ECC_STATUS, ECC_ERR, reg_rx_mem0_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_rx_mem1_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err)
+{
+    uint32_t reg_rx_mem1_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mem_addr || !double_bit_ecc_err || !multi_ecc_err || !ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, RX_MEM1_ECC_STATUS, reg_rx_mem1_ecc_status);
+
+    *mem_addr = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM1_ECC_STATUS, MEM_ADDR, reg_rx_mem1_ecc_status);
+    *double_bit_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM1_ECC_STATUS, DOUBLE_BIT_ECC_ERR, reg_rx_mem1_ecc_status);
+    *multi_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM1_ECC_STATUS, MULTI_ECC_ERR, reg_rx_mem1_ecc_status);
+    *ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM1_ECC_STATUS, ECC_ERR, reg_rx_mem1_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_rx_mem2_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err)
+{
+    uint32_t reg_rx_mem2_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mem_addr || !double_bit_ecc_err || !multi_ecc_err || !ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, RX_MEM2_ECC_STATUS, reg_rx_mem2_ecc_status);
+
+    *mem_addr = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM2_ECC_STATUS, MEM_ADDR, reg_rx_mem2_ecc_status);
+    *double_bit_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM2_ECC_STATUS, DOUBLE_BIT_ECC_ERR, reg_rx_mem2_ecc_status);
+    *multi_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM2_ECC_STATUS, MULTI_ECC_ERR, reg_rx_mem2_ecc_status);
+    *ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM2_ECC_STATUS, ECC_ERR, reg_rx_mem2_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_rx_mem3_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err)
+{
+    uint32_t reg_rx_mem3_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mem_addr || !double_bit_ecc_err || !multi_ecc_err || !ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, RX_MEM3_ECC_STATUS, reg_rx_mem3_ecc_status);
+
+    *mem_addr = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM3_ECC_STATUS, MEM_ADDR, reg_rx_mem3_ecc_status);
+    *double_bit_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM3_ECC_STATUS, DOUBLE_BIT_ECC_ERR, reg_rx_mem3_ecc_status);
+    *multi_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM3_ECC_STATUS, MULTI_ECC_ERR, reg_rx_mem3_ecc_status);
+    *ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM3_ECC_STATUS, ECC_ERR, reg_rx_mem3_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_rx_mem4_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err)
+{
+    uint32_t reg_rx_mem4_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mem_addr || !double_bit_ecc_err || !multi_ecc_err || !ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, RX_MEM4_ECC_STATUS, reg_rx_mem4_ecc_status);
+
+    *mem_addr = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM4_ECC_STATUS, MEM_ADDR, reg_rx_mem4_ecc_status);
+    *double_bit_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM4_ECC_STATUS, DOUBLE_BIT_ECC_ERR, reg_rx_mem4_ecc_status);
+    *multi_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM4_ECC_STATUS, MULTI_ECC_ERR, reg_rx_mem4_ecc_status);
+    *ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, RX_MEM4_ECC_STATUS, ECC_ERR, reg_rx_mem4_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_tx_mem0_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err)
+{
+    uint32_t reg_tx_mem0_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mem_addr || !double_bit_ecc_err || !multi_ecc_err || !ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, TX_MEM0_ECC_STATUS, reg_tx_mem0_ecc_status);
+
+    *mem_addr = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM0_ECC_STATUS, MEM_ADDR, reg_tx_mem0_ecc_status);
+    *double_bit_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM0_ECC_STATUS, DOUBLE_BIT_ECC_ERR, reg_tx_mem0_ecc_status);
+    *multi_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM0_ECC_STATUS, MULTI_ECC_ERR, reg_tx_mem0_ecc_status);
+    *ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM0_ECC_STATUS, ECC_ERR, reg_tx_mem0_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_tx_mem1_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err)
+{
+    uint32_t reg_tx_mem1_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mem_addr || !double_bit_ecc_err || !multi_ecc_err || !ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, TX_MEM1_ECC_STATUS, reg_tx_mem1_ecc_status);
+
+    *mem_addr = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM1_ECC_STATUS, MEM_ADDR, reg_tx_mem1_ecc_status);
+    *double_bit_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM1_ECC_STATUS, DOUBLE_BIT_ECC_ERR, reg_tx_mem1_ecc_status);
+    *multi_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM1_ECC_STATUS, MULTI_ECC_ERR, reg_tx_mem1_ecc_status);
+    *ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM1_ECC_STATUS, ECC_ERR, reg_tx_mem1_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_tx_mem2_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err)
+{
+    uint32_t reg_tx_mem2_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mem_addr || !double_bit_ecc_err || !multi_ecc_err || !ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, TX_MEM2_ECC_STATUS, reg_tx_mem2_ecc_status);
+
+    *mem_addr = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM2_ECC_STATUS, MEM_ADDR, reg_tx_mem2_ecc_status);
+    *double_bit_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM2_ECC_STATUS, DOUBLE_BIT_ECC_ERR, reg_tx_mem2_ecc_status);
+    *multi_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM2_ECC_STATUS, MULTI_ECC_ERR, reg_tx_mem2_ecc_status);
+    *ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM2_ECC_STATUS, ECC_ERR, reg_tx_mem2_ecc_status);
+
+    return 0;
+}
+
+int ag_drv_mib_conf_tx_mem3_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err)
+{
+    uint32_t reg_tx_mem3_ecc_status=0;
+
+#ifdef VALIDATE_PARMS
+    if(!mem_addr || !double_bit_ecc_err || !multi_ecc_err || !ecc_err)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, MIB_CONF, TX_MEM3_ECC_STATUS, reg_tx_mem3_ecc_status);
+
+    *mem_addr = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM3_ECC_STATUS, MEM_ADDR, reg_tx_mem3_ecc_status);
+    *double_bit_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM3_ECC_STATUS, DOUBLE_BIT_ECC_ERR, reg_tx_mem3_ecc_status);
+    *multi_ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM3_ECC_STATUS, MULTI_ECC_ERR, reg_tx_mem3_ecc_status);
+    *ecc_err = RU_FIELD_GET(xlmac_id, MIB_CONF, TX_MEM3_ECC_STATUS, ECC_ERR, reg_tx_mem3_ecc_status);
+
+    return 0;
+}
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_mib_conf_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_mib_conf_ag.h
new file mode 100644
index 0000000000..7406fd6a69
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_mib_conf_ag.h
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_MIB_CONF_AG_H_
+#define _BCM6858_MIB_CONF_AG_H_
+
+#include "access_macros.h"
+#include "bcmtypes.h"
+typedef struct
+{
+    uint8_t err;
+    uint8_t start_busy;
+    uint8_t r_w;
+    uint8_t reg_port_id;
+    uint8_t reg_offset;
+} mib_conf_indir_acc_addr_0;
+
+typedef struct
+{
+    uint8_t err;
+    uint8_t start_busy;
+    uint8_t r_w;
+    uint8_t reg_port_id;
+    uint8_t reg_offset;
+} mib_conf_indir_acc_addr_1;
+
+typedef struct
+{
+    uint8_t force_tx_mem3_serr;
+    uint8_t force_tx_mem2_serr;
+    uint8_t force_tx_mem1_serr;
+    uint8_t force_tx_mem0_serr;
+    uint8_t force_rx_mem4_serr;
+    uint8_t force_rx_mem3_serr;
+    uint8_t force_rx_mem2_serr;
+    uint8_t force_rx_mem1_serr;
+    uint8_t force_rx_mem0_serr;
+} mib_conf_force_sb_ecc_err;
+
+typedef struct
+{
+    uint8_t force_tx_mem3_derr;
+    uint8_t force_tx_mem2_derr;
+    uint8_t force_tx_mem1_derr;
+    uint8_t force_tx_mem0_derr;
+    uint8_t force_rx_mem4_derr;
+    uint8_t force_rx_mem3_derr;
+    uint8_t force_rx_mem2_derr;
+    uint8_t force_rx_mem1_derr;
+    uint8_t force_rx_mem0_derr;
+} mib_conf_force_db_ecc_err;
+
+int ag_drv_mib_conf_mib0_write_holding_set(uint8_t xlmac_id, uint32_t write_data);
+int ag_drv_mib_conf_mib0_write_holding_get(uint8_t xlmac_id, uint32_t *write_data);
+int ag_drv_mib_conf_mib0_read_holding_set(uint8_t xlmac_id, uint32_t read_data);
+int ag_drv_mib_conf_mib0_read_holding_get(uint8_t xlmac_id, uint32_t *read_data);
+int ag_drv_mib_conf_indir_acc_addr_0_set(uint8_t xlmac_id, const mib_conf_indir_acc_addr_0 *indir_acc_addr_0);
+int ag_drv_mib_conf_indir_acc_addr_0_get(uint8_t xlmac_id, mib_conf_indir_acc_addr_0 *indir_acc_addr_0);
+int ag_drv_mib_conf_indir_acc_data_low_0_set(uint8_t xlmac_id, uint32_t data_low);
+int ag_drv_mib_conf_indir_acc_data_low_0_get(uint8_t xlmac_id, uint32_t *data_low);
+int ag_drv_mib_conf_indir_acc_data_high_0_set(uint8_t xlmac_id, uint32_t data_high);
+int ag_drv_mib_conf_indir_acc_data_high_0_get(uint8_t xlmac_id, uint32_t *data_high);
+int ag_drv_mib_conf_indir_acc_addr_1_set(uint8_t xlmac_id, const mib_conf_indir_acc_addr_1 *indir_acc_addr_1);
+int ag_drv_mib_conf_indir_acc_addr_1_get(uint8_t xlmac_id, mib_conf_indir_acc_addr_1 *indir_acc_addr_1);
+int ag_drv_mib_conf_indir_acc_data_low_1_set(uint8_t xlmac_id, uint32_t data_low);
+int ag_drv_mib_conf_indir_acc_data_low_1_get(uint8_t xlmac_id, uint32_t *data_low);
+int ag_drv_mib_conf_indir_acc_data_high_1_set(uint8_t xlmac_id, uint32_t data_high);
+int ag_drv_mib_conf_indir_acc_data_high_1_get(uint8_t xlmac_id, uint32_t *data_high);
+int ag_drv_mib_conf_control_set(uint8_t xlmac_id, uint8_t eee_cnt_mode, uint8_t saturate_en, uint8_t cor_en, uint8_t cnt_rst);
+int ag_drv_mib_conf_control_get(uint8_t xlmac_id, uint8_t *eee_cnt_mode, uint8_t *saturate_en, uint8_t *cor_en, uint8_t *cnt_rst);
+int ag_drv_mib_conf_eee_pulse_duration_cntrl_set(uint8_t xlmac_id, uint8_t cnt);
+int ag_drv_mib_conf_eee_pulse_duration_cntrl_get(uint8_t xlmac_id, uint8_t *cnt);
+int ag_drv_mib_conf_gport0_max_pkt_size_set(uint8_t xlmac_id, uint16_t max_pkt_size);
+int ag_drv_mib_conf_gport0_max_pkt_size_get(uint8_t xlmac_id, uint16_t *max_pkt_size);
+int ag_drv_mib_conf_gport1_max_pkt_size_set(uint8_t xlmac_id, uint16_t max_pkt_size);
+int ag_drv_mib_conf_gport1_max_pkt_size_get(uint8_t xlmac_id, uint16_t *max_pkt_size);
+int ag_drv_mib_conf_gport2_max_pkt_size_set(uint8_t xlmac_id, uint16_t max_pkt_size);
+int ag_drv_mib_conf_gport2_max_pkt_size_get(uint8_t xlmac_id, uint16_t *max_pkt_size);
+int ag_drv_mib_conf_gport3_max_pkt_size_set(uint8_t xlmac_id, uint16_t max_pkt_size);
+int ag_drv_mib_conf_gport3_max_pkt_size_get(uint8_t xlmac_id, uint16_t *max_pkt_size);
+int ag_drv_mib_conf_ecc_cntrl_set(uint8_t xlmac_id, uint8_t tx_mib_ecc_en, uint8_t rx_mib_ecc_en);
+int ag_drv_mib_conf_ecc_cntrl_get(uint8_t xlmac_id, uint8_t *tx_mib_ecc_en, uint8_t *rx_mib_ecc_en);
+int ag_drv_mib_conf_force_sb_ecc_err_set(uint8_t xlmac_id, const mib_conf_force_sb_ecc_err *force_sb_ecc_err);
+int ag_drv_mib_conf_force_sb_ecc_err_get(uint8_t xlmac_id, mib_conf_force_sb_ecc_err *force_sb_ecc_err);
+int ag_drv_mib_conf_force_db_ecc_err_set(uint8_t xlmac_id, const mib_conf_force_db_ecc_err *force_db_ecc_err);
+int ag_drv_mib_conf_force_db_ecc_err_get(uint8_t xlmac_id, mib_conf_force_db_ecc_err *force_db_ecc_err);
+int ag_drv_mib_conf_rx_mem0_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err);
+int ag_drv_mib_conf_rx_mem1_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err);
+int ag_drv_mib_conf_rx_mem2_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err);
+int ag_drv_mib_conf_rx_mem3_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err);
+int ag_drv_mib_conf_rx_mem4_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err);
+int ag_drv_mib_conf_tx_mem0_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err);
+int ag_drv_mib_conf_tx_mem1_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err);
+int ag_drv_mib_conf_tx_mem2_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err);
+int ag_drv_mib_conf_tx_mem3_ecc_status_get(uint8_t xlmac_id, uint8_t *mem_addr, uint8_t *double_bit_ecc_err, uint8_t *multi_ecc_err, uint8_t *ecc_err);
+
+#ifdef USE_BDMF_SHELL
+bdmfmon_handle_t ag_drv_mib_conf_cli_init(bdmfmon_handle_t driver_dir);
+#endif
+
+
+#endif
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_xlmac_conf_ag.c b/drivers/net/bcmbca/lport/ag/bcm6858_xlmac_conf_ag.c
new file mode 100644
index 0000000000..46466b65db
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_xlmac_conf_ag.c
@@ -0,0 +1,681 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_xlmac_conf_ag.h"
+#define BLOCK_ADDR_COUNT_BITS 1
+#define BLOCK_ADDR_COUNT (1<<BLOCK_ADDR_COUNT_BITS)
+
+int ag_drv_xlmac_conf_dir_acc_data_write_set(uint8_t xlmac_id, uint32_t write_data)
+{
+    uint32_t reg_dir_acc_data_write=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_dir_acc_data_write = RU_FIELD_SET(xlmac_id, XLMAC_CONF, DIR_ACC_DATA_WRITE, WRITE_DATA, reg_dir_acc_data_write, write_data);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, DIR_ACC_DATA_WRITE, reg_dir_acc_data_write);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_dir_acc_data_write_get(uint8_t xlmac_id, uint32_t *write_data)
+{
+    uint32_t reg_dir_acc_data_write=0;
+
+#ifdef VALIDATE_PARMS
+    if(!write_data)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, DIR_ACC_DATA_WRITE, reg_dir_acc_data_write);
+
+    *write_data = RU_FIELD_GET(xlmac_id, XLMAC_CONF, DIR_ACC_DATA_WRITE, WRITE_DATA, reg_dir_acc_data_write);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_dir_acc_data_read_set(uint8_t xlmac_id, uint32_t read_data)
+{
+    uint32_t reg_dir_acc_data_read=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_dir_acc_data_read = RU_FIELD_SET(xlmac_id, XLMAC_CONF, DIR_ACC_DATA_READ, READ_DATA, reg_dir_acc_data_read, read_data);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, DIR_ACC_DATA_READ, reg_dir_acc_data_read);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_dir_acc_data_read_get(uint8_t xlmac_id, uint32_t *read_data)
+{
+    uint32_t reg_dir_acc_data_read=0;
+
+#ifdef VALIDATE_PARMS
+    if(!read_data)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, DIR_ACC_DATA_READ, reg_dir_acc_data_read);
+
+    *read_data = RU_FIELD_GET(xlmac_id, XLMAC_CONF, DIR_ACC_DATA_READ, READ_DATA, reg_dir_acc_data_read);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_addr_0_set(uint8_t xlmac_id, const xlmac_conf_indir_acc_addr_0 *indir_acc_addr_0)
+{
+    uint32_t reg_indir_acc_addr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!indir_acc_addr_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (indir_acc_addr_0->err >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_0->start_busy >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_0->r_w >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_0->reg_port_id >= _2BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_addr_0 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, ERR, reg_indir_acc_addr_0, indir_acc_addr_0->err);
+    reg_indir_acc_addr_0 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, START_BUSY, reg_indir_acc_addr_0, indir_acc_addr_0->start_busy);
+    reg_indir_acc_addr_0 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, R_W, reg_indir_acc_addr_0, indir_acc_addr_0->r_w);
+    reg_indir_acc_addr_0 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, REG_PORT_ID, reg_indir_acc_addr_0, indir_acc_addr_0->reg_port_id);
+    reg_indir_acc_addr_0 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, REG_OFFSET, reg_indir_acc_addr_0, indir_acc_addr_0->reg_offset);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, reg_indir_acc_addr_0);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_addr_0_get(uint8_t xlmac_id, xlmac_conf_indir_acc_addr_0 *indir_acc_addr_0)
+{
+    uint32_t reg_indir_acc_addr_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!indir_acc_addr_0)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, reg_indir_acc_addr_0);
+
+    indir_acc_addr_0->err = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, ERR, reg_indir_acc_addr_0);
+    indir_acc_addr_0->start_busy = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, START_BUSY, reg_indir_acc_addr_0);
+    indir_acc_addr_0->r_w = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, R_W, reg_indir_acc_addr_0);
+    indir_acc_addr_0->reg_port_id = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, REG_PORT_ID, reg_indir_acc_addr_0);
+    indir_acc_addr_0->reg_offset = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_0, REG_OFFSET, reg_indir_acc_addr_0);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_data_low_0_set(uint8_t xlmac_id, uint32_t data_low)
+{
+    uint32_t reg_indir_acc_data_low_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_data_low_0 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_LOW_0, DATA_LOW, reg_indir_acc_data_low_0, data_low);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_LOW_0, reg_indir_acc_data_low_0);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_data_low_0_get(uint8_t xlmac_id, uint32_t *data_low)
+{
+    uint32_t reg_indir_acc_data_low_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!data_low)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_LOW_0, reg_indir_acc_data_low_0);
+
+    *data_low = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_LOW_0, DATA_LOW, reg_indir_acc_data_low_0);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_data_high_0_set(uint8_t xlmac_id, uint32_t data_high)
+{
+    uint32_t reg_indir_acc_data_high_0=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_data_high_0 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_HIGH_0, DATA_HIGH, reg_indir_acc_data_high_0, data_high);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_HIGH_0, reg_indir_acc_data_high_0);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_data_high_0_get(uint8_t xlmac_id, uint32_t *data_high)
+{
+    uint32_t reg_indir_acc_data_high_0=0;
+
+#ifdef VALIDATE_PARMS
+    if(!data_high)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_HIGH_0, reg_indir_acc_data_high_0);
+
+    *data_high = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_HIGH_0, DATA_HIGH, reg_indir_acc_data_high_0);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_addr_1_set(uint8_t xlmac_id, const xlmac_conf_indir_acc_addr_1 *indir_acc_addr_1)
+{
+    uint32_t reg_indir_acc_addr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!indir_acc_addr_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (indir_acc_addr_1->err >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_1->start_busy >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_1->r_w >= _1BITS_MAX_VAL_) ||
+       (indir_acc_addr_1->reg_port_id >= _2BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_addr_1 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, ERR, reg_indir_acc_addr_1, indir_acc_addr_1->err);
+    reg_indir_acc_addr_1 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, START_BUSY, reg_indir_acc_addr_1, indir_acc_addr_1->start_busy);
+    reg_indir_acc_addr_1 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, R_W, reg_indir_acc_addr_1, indir_acc_addr_1->r_w);
+    reg_indir_acc_addr_1 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, REG_PORT_ID, reg_indir_acc_addr_1, indir_acc_addr_1->reg_port_id);
+    reg_indir_acc_addr_1 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, REG_OFFSET, reg_indir_acc_addr_1, indir_acc_addr_1->reg_offset);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, reg_indir_acc_addr_1);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_addr_1_get(uint8_t xlmac_id, xlmac_conf_indir_acc_addr_1 *indir_acc_addr_1)
+{
+    uint32_t reg_indir_acc_addr_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!indir_acc_addr_1)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, reg_indir_acc_addr_1);
+
+    indir_acc_addr_1->err = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, ERR, reg_indir_acc_addr_1);
+    indir_acc_addr_1->start_busy = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, START_BUSY, reg_indir_acc_addr_1);
+    indir_acc_addr_1->r_w = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, R_W, reg_indir_acc_addr_1);
+    indir_acc_addr_1->reg_port_id = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, REG_PORT_ID, reg_indir_acc_addr_1);
+    indir_acc_addr_1->reg_offset = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_ADDR_1, REG_OFFSET, reg_indir_acc_addr_1);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_data_low_1_set(uint8_t xlmac_id, uint32_t data_low)
+{
+    uint32_t reg_indir_acc_data_low_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_data_low_1 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_LOW_1, DATA_LOW, reg_indir_acc_data_low_1, data_low);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_LOW_1, reg_indir_acc_data_low_1);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_data_low_1_get(uint8_t xlmac_id, uint32_t *data_low)
+{
+    uint32_t reg_indir_acc_data_low_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!data_low)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_LOW_1, reg_indir_acc_data_low_1);
+
+    *data_low = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_LOW_1, DATA_LOW, reg_indir_acc_data_low_1);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_data_high_1_set(uint8_t xlmac_id, uint32_t data_high)
+{
+    uint32_t reg_indir_acc_data_high_1=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_indir_acc_data_high_1 = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_HIGH_1, DATA_HIGH, reg_indir_acc_data_high_1, data_high);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_HIGH_1, reg_indir_acc_data_high_1);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_indir_acc_data_high_1_get(uint8_t xlmac_id, uint32_t *data_high)
+{
+    uint32_t reg_indir_acc_data_high_1=0;
+
+#ifdef VALIDATE_PARMS
+    if(!data_high)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_HIGH_1, reg_indir_acc_data_high_1);
+
+    *data_high = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INDIR_ACC_DATA_HIGH_1, DATA_HIGH, reg_indir_acc_data_high_1);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_config_set(uint8_t xlmac_id, const xlmac_conf_config *config)
+{
+    uint32_t reg_config=0;
+
+#ifdef VALIDATE_PARMS
+    if(!config)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 1);
+        return 1;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (config->xlmac_reset >= _1BITS_MAX_VAL_) ||
+       (config->rx_dual_cycle_tdm_en >= _1BITS_MAX_VAL_) ||
+       (config->rx_non_linear_quad_tdm_en >= _1BITS_MAX_VAL_) ||
+       (config->rx_flex_tdm_enable >= _1BITS_MAX_VAL_) ||
+       (config->mac_mode >= _3BITS_MAX_VAL_) ||
+       (config->osts_timer_disable >= _1BITS_MAX_VAL_) ||
+       (config->bypass_osts >= _1BITS_MAX_VAL_) ||
+       (config->egr_1588_timestamping_mode >= _1BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_config = RU_FIELD_SET(xlmac_id, XLMAC_CONF, CONFIG, XLMAC_RESET, reg_config, config->xlmac_reset);
+    reg_config = RU_FIELD_SET(xlmac_id, XLMAC_CONF, CONFIG, RX_DUAL_CYCLE_TDM_EN, reg_config, config->rx_dual_cycle_tdm_en);
+    reg_config = RU_FIELD_SET(xlmac_id, XLMAC_CONF, CONFIG, RX_NON_LINEAR_QUAD_TDM_EN, reg_config, config->rx_non_linear_quad_tdm_en);
+    reg_config = RU_FIELD_SET(xlmac_id, XLMAC_CONF, CONFIG, RX_FLEX_TDM_ENABLE, reg_config, config->rx_flex_tdm_enable);
+    reg_config = RU_FIELD_SET(xlmac_id, XLMAC_CONF, CONFIG, MAC_MODE, reg_config, config->mac_mode);
+    reg_config = RU_FIELD_SET(xlmac_id, XLMAC_CONF, CONFIG, OSTS_TIMER_DISABLE, reg_config, config->osts_timer_disable);
+    reg_config = RU_FIELD_SET(xlmac_id, XLMAC_CONF, CONFIG, BYPASS_OSTS, reg_config, config->bypass_osts);
+    reg_config = RU_FIELD_SET(xlmac_id, XLMAC_CONF, CONFIG, EGR_1588_TIMESTAMPING_MODE, reg_config, config->egr_1588_timestamping_mode);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, CONFIG, reg_config);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_config_get(uint8_t xlmac_id, xlmac_conf_config *config)
+{
+    uint32_t reg_config=0;
+
+#ifdef VALIDATE_PARMS
+    if(!config)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, CONFIG, reg_config);
+
+    config->xlmac_reset = RU_FIELD_GET(xlmac_id, XLMAC_CONF, CONFIG, XLMAC_RESET, reg_config);
+    config->rx_dual_cycle_tdm_en = RU_FIELD_GET(xlmac_id, XLMAC_CONF, CONFIG, RX_DUAL_CYCLE_TDM_EN, reg_config);
+    config->rx_non_linear_quad_tdm_en = RU_FIELD_GET(xlmac_id, XLMAC_CONF, CONFIG, RX_NON_LINEAR_QUAD_TDM_EN, reg_config);
+    config->rx_flex_tdm_enable = RU_FIELD_GET(xlmac_id, XLMAC_CONF, CONFIG, RX_FLEX_TDM_ENABLE, reg_config);
+    config->mac_mode = RU_FIELD_GET(xlmac_id, XLMAC_CONF, CONFIG, MAC_MODE, reg_config);
+    config->osts_timer_disable = RU_FIELD_GET(xlmac_id, XLMAC_CONF, CONFIG, OSTS_TIMER_DISABLE, reg_config);
+    config->bypass_osts = RU_FIELD_GET(xlmac_id, XLMAC_CONF, CONFIG, BYPASS_OSTS, reg_config);
+    config->egr_1588_timestamping_mode = RU_FIELD_GET(xlmac_id, XLMAC_CONF, CONFIG, EGR_1588_TIMESTAMPING_MODE, reg_config);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_interrupt_check_set(uint8_t xlmac_id, uint8_t xlmac_intr_check)
+{
+    uint32_t reg_interrupt_check=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (xlmac_intr_check >= _4BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_interrupt_check = RU_FIELD_SET(xlmac_id, XLMAC_CONF, INTERRUPT_CHECK, XLMAC_INTR_CHECK, reg_interrupt_check, xlmac_intr_check);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, INTERRUPT_CHECK, reg_interrupt_check);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_interrupt_check_get(uint8_t xlmac_id, uint8_t *xlmac_intr_check)
+{
+    uint32_t reg_interrupt_check=0;
+
+#ifdef VALIDATE_PARMS
+    if(!xlmac_intr_check)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, INTERRUPT_CHECK, reg_interrupt_check);
+
+    *xlmac_intr_check = RU_FIELD_GET(xlmac_id, XLMAC_CONF, INTERRUPT_CHECK, XLMAC_INTR_CHECK, reg_interrupt_check);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_port_0_rxerr_mask_set(uint8_t xlmac_id, uint32_t rsv_err_mask)
+{
+    uint32_t reg_port_0_rxerr_mask=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (rsv_err_mask >= _22BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_port_0_rxerr_mask = RU_FIELD_SET(xlmac_id, XLMAC_CONF, PORT_0_RXERR_MASK, RSV_ERR_MASK, reg_port_0_rxerr_mask, rsv_err_mask);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, PORT_0_RXERR_MASK, reg_port_0_rxerr_mask);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_port_0_rxerr_mask_get(uint8_t xlmac_id, uint32_t *rsv_err_mask)
+{
+    uint32_t reg_port_0_rxerr_mask=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rsv_err_mask)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, PORT_0_RXERR_MASK, reg_port_0_rxerr_mask);
+
+    *rsv_err_mask = RU_FIELD_GET(xlmac_id, XLMAC_CONF, PORT_0_RXERR_MASK, RSV_ERR_MASK, reg_port_0_rxerr_mask);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_port_1_rxerr_mask_set(uint8_t xlmac_id, uint32_t rsv_err_mask)
+{
+    uint32_t reg_port_1_rxerr_mask=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (rsv_err_mask >= _22BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_port_1_rxerr_mask = RU_FIELD_SET(xlmac_id, XLMAC_CONF, PORT_1_RXERR_MASK, RSV_ERR_MASK, reg_port_1_rxerr_mask, rsv_err_mask);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, PORT_1_RXERR_MASK, reg_port_1_rxerr_mask);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_port_1_rxerr_mask_get(uint8_t xlmac_id, uint32_t *rsv_err_mask)
+{
+    uint32_t reg_port_1_rxerr_mask=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rsv_err_mask)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, PORT_1_RXERR_MASK, reg_port_1_rxerr_mask);
+
+    *rsv_err_mask = RU_FIELD_GET(xlmac_id, XLMAC_CONF, PORT_1_RXERR_MASK, RSV_ERR_MASK, reg_port_1_rxerr_mask);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_port_2_rxerr_mask_set(uint8_t xlmac_id, uint32_t rsv_err_mask)
+{
+    uint32_t reg_port_2_rxerr_mask=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (rsv_err_mask >= _22BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_port_2_rxerr_mask = RU_FIELD_SET(xlmac_id, XLMAC_CONF, PORT_2_RXERR_MASK, RSV_ERR_MASK, reg_port_2_rxerr_mask, rsv_err_mask);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, PORT_2_RXERR_MASK, reg_port_2_rxerr_mask);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_port_2_rxerr_mask_get(uint8_t xlmac_id, uint32_t *rsv_err_mask)
+{
+    uint32_t reg_port_2_rxerr_mask=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rsv_err_mask)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, PORT_2_RXERR_MASK, reg_port_2_rxerr_mask);
+
+    *rsv_err_mask = RU_FIELD_GET(xlmac_id, XLMAC_CONF, PORT_2_RXERR_MASK, RSV_ERR_MASK, reg_port_2_rxerr_mask);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_port_3_rxerr_mask_set(uint8_t xlmac_id, uint32_t rsv_err_mask)
+{
+    uint32_t reg_port_3_rxerr_mask=0;
+
+#ifdef VALIDATE_PARMS
+    if((xlmac_id >= BLOCK_ADDR_COUNT) ||
+       (rsv_err_mask >= _22BITS_MAX_VAL_))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    reg_port_3_rxerr_mask = RU_FIELD_SET(xlmac_id, XLMAC_CONF, PORT_3_RXERR_MASK, RSV_ERR_MASK, reg_port_3_rxerr_mask, rsv_err_mask);
+
+    RU_REG_WRITE(xlmac_id, XLMAC_CONF, PORT_3_RXERR_MASK, reg_port_3_rxerr_mask);
+
+    return 0;
+}
+
+int ag_drv_xlmac_conf_port_3_rxerr_mask_get(uint8_t xlmac_id, uint32_t *rsv_err_mask)
+{
+    uint32_t reg_port_3_rxerr_mask=0;
+
+#ifdef VALIDATE_PARMS
+    if(!rsv_err_mask)
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 2);
+        return 2;
+    }
+    if((xlmac_id >= BLOCK_ADDR_COUNT))
+    {
+        pr_err("ERROR driver %s:%u|(%d)\n", __FILE__, __LINE__, 0);
+        return 0;
+    }
+#endif
+
+    RU_REG_READ(xlmac_id, XLMAC_CONF, PORT_3_RXERR_MASK, reg_port_3_rxerr_mask);
+
+    *rsv_err_mask = RU_FIELD_GET(xlmac_id, XLMAC_CONF, PORT_3_RXERR_MASK, RSV_ERR_MASK, reg_port_3_rxerr_mask);
+
+    return 0;
+}
+
diff --git a/drivers/net/bcmbca/lport/ag/bcm6858_xlmac_conf_ag.h b/drivers/net/bcmbca/lport/ag/bcm6858_xlmac_conf_ag.h
new file mode 100644
index 0000000000..68f4dd544b
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcm6858_xlmac_conf_ag.h
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BCM6858_XLMAC_CONF_AG_H_
+#define _BCM6858_XLMAC_CONF_AG_H_
+
+#include "access_macros.h"
+#include "bcmtypes.h"
+typedef struct
+{
+    uint8_t err;
+    uint8_t start_busy;
+    uint8_t r_w;
+    uint8_t reg_port_id;
+    uint8_t reg_offset;
+} xlmac_conf_indir_acc_addr_0;
+
+typedef struct
+{
+    uint8_t err;
+    uint8_t start_busy;
+    uint8_t r_w;
+    uint8_t reg_port_id;
+    uint8_t reg_offset;
+} xlmac_conf_indir_acc_addr_1;
+
+typedef struct
+{
+    uint8_t xlmac_reset;
+    uint8_t rx_dual_cycle_tdm_en;
+    uint8_t rx_non_linear_quad_tdm_en;
+    uint8_t rx_flex_tdm_enable;
+    uint8_t mac_mode;
+    uint8_t osts_timer_disable;
+    uint8_t bypass_osts;
+    uint8_t egr_1588_timestamping_mode;
+} xlmac_conf_config;
+
+int ag_drv_xlmac_conf_dir_acc_data_write_set(uint8_t xlmac_id, uint32_t write_data);
+int ag_drv_xlmac_conf_dir_acc_data_write_get(uint8_t xlmac_id, uint32_t *write_data);
+int ag_drv_xlmac_conf_dir_acc_data_read_set(uint8_t xlmac_id, uint32_t read_data);
+int ag_drv_xlmac_conf_dir_acc_data_read_get(uint8_t xlmac_id, uint32_t *read_data);
+int ag_drv_xlmac_conf_indir_acc_addr_0_set(uint8_t xlmac_id, const xlmac_conf_indir_acc_addr_0 *indir_acc_addr_0);
+int ag_drv_xlmac_conf_indir_acc_addr_0_get(uint8_t xlmac_id, xlmac_conf_indir_acc_addr_0 *indir_acc_addr_0);
+int ag_drv_xlmac_conf_indir_acc_data_low_0_set(uint8_t xlmac_id, uint32_t data_low);
+int ag_drv_xlmac_conf_indir_acc_data_low_0_get(uint8_t xlmac_id, uint32_t *data_low);
+int ag_drv_xlmac_conf_indir_acc_data_high_0_set(uint8_t xlmac_id, uint32_t data_high);
+int ag_drv_xlmac_conf_indir_acc_data_high_0_get(uint8_t xlmac_id, uint32_t *data_high);
+int ag_drv_xlmac_conf_indir_acc_addr_1_set(uint8_t xlmac_id, const xlmac_conf_indir_acc_addr_1 *indir_acc_addr_1);
+int ag_drv_xlmac_conf_indir_acc_addr_1_get(uint8_t xlmac_id, xlmac_conf_indir_acc_addr_1 *indir_acc_addr_1);
+int ag_drv_xlmac_conf_indir_acc_data_low_1_set(uint8_t xlmac_id, uint32_t data_low);
+int ag_drv_xlmac_conf_indir_acc_data_low_1_get(uint8_t xlmac_id, uint32_t *data_low);
+int ag_drv_xlmac_conf_indir_acc_data_high_1_set(uint8_t xlmac_id, uint32_t data_high);
+int ag_drv_xlmac_conf_indir_acc_data_high_1_get(uint8_t xlmac_id, uint32_t *data_high);
+int ag_drv_xlmac_conf_config_set(uint8_t xlmac_id, const xlmac_conf_config *config);
+int ag_drv_xlmac_conf_config_get(uint8_t xlmac_id, xlmac_conf_config *config);
+int ag_drv_xlmac_conf_interrupt_check_set(uint8_t xlmac_id, uint8_t xlmac_intr_check);
+int ag_drv_xlmac_conf_interrupt_check_get(uint8_t xlmac_id, uint8_t *xlmac_intr_check);
+int ag_drv_xlmac_conf_port_0_rxerr_mask_set(uint8_t xlmac_id, uint32_t rsv_err_mask);
+int ag_drv_xlmac_conf_port_0_rxerr_mask_get(uint8_t xlmac_id, uint32_t *rsv_err_mask);
+int ag_drv_xlmac_conf_port_1_rxerr_mask_set(uint8_t xlmac_id, uint32_t rsv_err_mask);
+int ag_drv_xlmac_conf_port_1_rxerr_mask_get(uint8_t xlmac_id, uint32_t *rsv_err_mask);
+int ag_drv_xlmac_conf_port_2_rxerr_mask_set(uint8_t xlmac_id, uint32_t rsv_err_mask);
+int ag_drv_xlmac_conf_port_2_rxerr_mask_get(uint8_t xlmac_id, uint32_t *rsv_err_mask);
+int ag_drv_xlmac_conf_port_3_rxerr_mask_set(uint8_t xlmac_id, uint32_t rsv_err_mask);
+int ag_drv_xlmac_conf_port_3_rxerr_mask_get(uint8_t xlmac_id, uint32_t *rsv_err_mask);
+
+#ifdef USE_BDMF_SHELL
+bdmfmon_handle_t ag_drv_xlmac_conf_cli_init(bdmfmon_handle_t driver_dir);
+#endif
+
+
+#endif
+
diff --git a/drivers/net/bcmbca/lport/ag/bcmtypes.h b/drivers/net/bcmbca/lport/ag/bcmtypes.h
new file mode 100644
index 0000000000..70b00e9147
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/bcmtypes.h
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+    Copyright 2007-2015 Broadcom Corporation
+
+    
+*/
+
+//
+// bcmtypes.h - misc useful typedefs
+//
+#ifndef BCMTYPES_H
+#define BCMTYPES_H
+
+#ifndef __ASSEMBLER__
+
+// These are also defined in typedefs.h in the application area, so I need to
+// protect against re-definition.
+
+#ifndef _TYPEDEFS_H_
+
+typedef unsigned char   uint8;
+typedef unsigned short  uint16;
+typedef unsigned int    uint32;
+typedef unsigned long long  uint64;
+typedef signed char     int8;
+typedef signed short    int16;
+typedef signed int     int32;
+typedef signed long long    int64;
+typedef unsigned long  BcmHandle;
+
+#if !defined(__cplusplus) && !defined(__KERNEL__) && !defined(_LINUX_TYPES_H) && !defined(_LINUX_IF_H)
+typedef int bool;
+#endif
+
+#endif
+
+typedef unsigned char  byte;
+
+typedef unsigned long   HANDLE,*PULONG;
+typedef int             DWORD,*PDWORD;
+#ifndef LONG
+typedef signed long     LONG,*PLONG;
+#endif
+
+typedef unsigned int    *PUINT;
+typedef signed int      INT;
+
+typedef unsigned short  *PUSHORT;
+typedef signed short    SHORT,*PSHORT;
+typedef unsigned short  WORD,*PWORD;
+
+typedef unsigned char   *PUCHAR;
+typedef signed char     *PCHAR;
+
+typedef void            *PVOID;
+
+typedef unsigned char   BOOLEAN, *PBOOL, *PBOOLEAN;
+
+typedef unsigned char   BYTE,*PBYTE;
+
+typedef signed int      *PINT;
+
+#ifndef NUMBER_TYPES_ALREADY_DEFINED
+#define NUMBER_TYPES_ALREADY_DEFINED
+typedef signed char     INT8;
+typedef signed char     SINT8;
+typedef signed short    INT16;
+typedef signed short    SINT16;
+typedef signed int      INT32;
+typedef signed int      sint32;
+typedef signed int      SINT32;
+typedef signed long long SINT64;
+
+typedef unsigned char   UINT8;
+typedef unsigned short  UINT16;
+typedef unsigned int    UINT32;
+typedef unsigned long long UINT64;
+#endif
+
+#ifndef BOOL_TYPE_ALREADY_DEFINED
+#define BOOL_TYPE_ALREADY_DEFINED
+typedef unsigned char   UBOOL8;
+#endif
+
+#ifndef BASE_TYPE_ALREADY_DEFINED
+#define BASE_TYPE_ALREADY_DEFINED
+typedef unsigned char   UCHAR;
+typedef unsigned short  USHORT;
+typedef unsigned int    UINT;
+typedef unsigned long   ULONG;
+#endif
+
+typedef void            VOID;
+typedef unsigned char   BOOL;
+
+// These are also defined in typedefs.h in the application area, so I need to
+// protect against re-definition.
+#ifndef TYPEDEFS_H
+
+// Maximum and minimum values for a signed 16 bit integer.
+#define MAX_INT16 32767
+#define MIN_INT16 -32768
+
+// Useful for true/false return values.  This uses the
+// Taligent notation (k for constant).
+typedef enum
+{
+    kFalse = 0,
+    kTrue = 1
+} Bool;
+
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE  0
+#endif
+
+#define READ32(addr)        (*(volatile UINT32 *)((ULONG)&addr))
+#define READ16(addr)        (*(volatile UINT16 *)((ULONG)&addr))
+#define READ8(addr)         (*(volatile UINT8  *)((ULONG)&addr))
+
+typedef unsigned long long uint64_aligned __attribute__((aligned(8)));
+typedef signed long long int64_aligned __attribute__((aligned(8)));
+
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#define BCM_IOC_PTR(ptr_t, ptr) union { ptr_t ptr; uint64_aligned ptr##64; }
+#define BCM_IOC_PTR_ZERO_EXT(ptr) if (is_compat_task()) ((ptr##64) = (uint64_aligned)(uint32_t)(ptr##64))
+#else
+#define BCM_IOC_PTR(ptr_t, ptr) ptr_t ptr;
+#define BCM_IOC_PTR_ZERO_EXT(ptr)
+#endif
+
+/*Example usage of above types/macro to a create 32/64-bit compatible ioctl message:
+  typedef struct {
+    uint8 exByte;
+    BCM_IOC_PTR(void*, exPtr);
+    uint32 exWord; /.Never use long. Always use (u)int32./
+    uint64_aligned ex64bitValue; /.Never use long long. Always use (u)int64_aligned../
+  } ExampleIoctlMsg;
+*/
+#endif
+
+#endif
diff --git a/drivers/net/bcmbca/lport/ag/mib_indirect_access.h b/drivers/net/bcmbca/lport/ag/mib_indirect_access.h
new file mode 100644
index 0000000000..8373f08251
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/mib_indirect_access.h
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+   
+   */
+/*
+ * mib_indirect_access.h
+ *
+ *  Created on: 6 áñôè× 2015
+ *      Author: yonatani
+ */
+
+#ifndef SHARED_OPENSOURCE_DRV_LPORT_MIB_INDIRECT_ACCESS_H_
+#define SHARED_OPENSOURCE_DRV_LPORT_MIB_INDIRECT_ACCESS_H_
+#include "bcm6858_mib_conf_ag.h"
+
+#define MIB_INDIRECT_WRITE(i,b,r,v) mib_indirect_write(i, RU_BLK(b).addr[i]+RU_REG_OFFSET(b,r),v)
+#define MIB_INDIRECT_READ(i,b,r,v) mib_indirect_read(i, RU_BLK(b).addr[i]+RU_REG_OFFSET(b,r),&v)
+
+static void mib_indirect_write(uint32_t portid, uint64_t address, uint64_t val)
+{
+    //fill using holding register
+    uint32_t xlmacid = (portid >> 2) & 0x1;
+    uint32_t holding = (uint32_t)((val >> 32) & 0xFFFFFFFF);
+    uint32_t regval = (uint32_t)(val & 0xFFFFFFFF);
+    ag_drv_mib_conf_mib0_write_holding_set(xlmacid, holding);
+
+    WRITE_32(address, regval);
+}
+
+static void mib_indirect_read(uint32_t portid, uint64_t address, uint64_t *val)
+{
+    //fill using holding register
+    uint32_t xlmacid = (portid >> 2) & 0x1;
+    uint32_t value32;
+    uint32_t holding;
+
+    READ_32(address, value32);
+
+    ag_drv_mib_conf_mib0_read_holding_get(xlmacid, &holding);
+
+    *val = (((uint64_t)holding << 32) | value32);
+}
+
+#endif //SHARED_OPENSOURCE_DRV_LPORT_MIB_INDIRECT_ACCESS_H_
diff --git a/drivers/net/bcmbca/lport/ag/ru.h b/drivers/net/bcmbca/lport/ag/ru.h
new file mode 100644
index 0000000000..4a6ebeda79
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/ru.h
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+#ifndef _RU_H_
+#define _RU_H_
+/**
+ * \brief Register tracking utilities
+ *
+ * The register track module provides functionality to comprehensively debug
+ * register level transactions.  It is a slow interface that should be used in
+ * parallel to standard direct read/write transactions.  The module can parse
+ * registers into easy read field format.  Registers may be looked up by name
+ * or address.
+ *
+ */
+#include "ru_config.h"
+#include "ru_types.h"
+#include "ru_chip.h"
+
+/**
+ * \brief Write a register
+ *
+ * This function writes a value to a register.  If debugging is enabled the
+ * written value may be logged.
+ *
+ * \param blk_inst Block instance number
+ * \param blk Register block record
+ * \param reg Register record
+ * \param val Value to write
+ *
+ * \return
+ * 0 if successful
+ */
+#define RU_REG_WRITE(i,b,r,v) WRITE_32(RU_BLK(b).addr[i]+RU_REG_OFFSET(b,r),v)
+
+
+/**
+ * \brief Read a register
+ *
+ * This function reads a register.  If debugging is enabled the value read may
+ * be logged.
+ *
+ * \param blk_inst Block instance number
+ * \param blk Register block record
+ * \param reg Register record
+ * \param val Read back register value
+ *
+ * \return
+ * 0 if successful
+ */
+extern
+uint32_t ru_reg_read(ru_block_inst blk_inst,
+                const ru_block_rec *blk,
+                const ru_reg_rec *reg);
+#define RU_REG_READ(i,b,r,reg) READ_32(RU_BLK(b).addr[i]+RU_REG_OFFSET(b,r),reg)
+
+
+/**
+ * \brief Set a register field
+ *
+ * This function sets a field in a register.  The value if applied to the
+ * supplied old register value and returned.  If debbuging is enabled an
+ * assertion will be raised if the field is out of range with range being
+ * determined by the width of the field. If the field is out of range it will
+ * not be set and the original old value will be returned.
+ *
+ * \param blk_inst Block instance number
+ * \param blk Register block record
+ * \param reg Register record
+ * \param fld Register field record
+ * \param reg_val Old register value to write in to
+ * \param fld_val Field value to write
+ *
+ * \return
+ * val with new field value applied
+ */
+extern
+uint32_t ru_field_set(ru_block_inst blk_inst,
+                      const ru_block_rec *blk,
+                      const ru_reg_rec *reg,
+                      const ru_field_rec *fld,
+                      uint32_t reg_val,
+                      uint32_t fld_val);
+#define RU_FIELD_SET(i,b,r,f,rv,fv)                                         \
+    (((rv) & ~RU_FLD_MASK(b,r,f)) | (fv << RU_FLD_SHIFT(b,r,f)))
+
+
+/**
+ * \brief Get a register field
+ *
+ * This function gets a field in a register.  The value returned is justified to
+ * bit [0]. This function does not support any debug features.
+ *
+ * \param blk_inst Block instance number
+ * \param blk Register block record
+ * \param reg Register record
+ * \param fld Register field record
+ * \param reg_val Old register value to read from
+ *
+ * \return
+ * Bit [0] justified field value
+ */
+#define RU_FIELD_GET(i,b,r,f,rv)                                            \
+    (((rv) & RU_FLD_MASK(b,r,f)) >> RU_FLD_SHIFT(b,r,f))
+
+
+#endif /* End of file _RU_H_ */
diff --git a/drivers/net/bcmbca/lport/ag/ru_chip.h b/drivers/net/bcmbca/lport/ag/ru_chip.h
new file mode 100644
index 0000000000..656ac9cf39
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/ru_chip.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _RU_CHIP_H_
+#define _RU_CHIP_H_
+
+#include "BCM6858_A0_LPORT_AG.h"
+
+#endif /* End of file ru_chip.h */
diff --git a/drivers/net/bcmbca/lport/ag/ru_config.h b/drivers/net/bcmbca/lport/ag/ru_config.h
new file mode 100644
index 0000000000..5f5bdaeef1
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/ru_config.h
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    */
+
+/**
+ * \brief Register Utility configuration and common includes
+ */
+#ifndef _RU_CONFIG_H_
+#define _RU_CONFIG_H_
+
+
+/******************************************************************************
+ * Optimizations
+ ******************************************************************************/
+
+/* Register access bypasses function interface and error checking instead
+   generating register accesses as inline memory dereference. This must be used 
+   with RU_EXTERNAL_REGISTER_ADDRESSING and RU_OFFLINE_TEST disabled. */
+#ifndef RU_FUNCTION_REG_ACCESS
+#define RU_FUNCTION_REG_ACCESS 0
+#endif
+
+/* Remove field bounds checking from RU_FIELD_SET.  This may be disabled once
+   software has stabilized and bounds checking begins to hurt performance. */
+#ifndef RU_FIELD_CHECK_ENABLE
+#define RU_FIELD_CHECK_ENABLE 1
+#endif
+
+/* Include title and description strings from RBD.  Note, this will take up a
+   very large amount of RAM on bigger systems. */ 
+#ifndef RU_INCLUDE_DESC
+#define RU_INCLUDE_DESC 0
+#endif
+
+/* Include field defitions in the register database */
+#ifndef RU_INCLUDE_FIELD_DB
+#define RU_INCLUDE_FIELD_DB 1
+#endif
+
+/* Include read/write access field in database */
+#ifndef RU_INCLUDE_ACCESS
+#define RU_INCLUDE_ACCESS 1
+#endif
+
+/******************************************************************************
+ * Logging
+ ******************************************************************************/
+
+/* Number of register accesses in the register logging ring buffer */
+#ifndef RU_LOG_SIZE
+#define RU_LOG_SIZE 65536
+#endif
+
+/* Number of unique logging rules that may be used at any time */
+#ifndef RU_RULE_POOL_SIZE
+#define RU_RULE_POOL_SIZE 256
+#endif
+
+/******************************************************************************
+ * Print and error
+ ******************************************************************************/
+
+/* Optional assert function to call when field bounds checking fails or logging
+   rule allocation fails.  Print function will also be called when this 
+   occurs. */
+#define RU_ASSERT()
+
+/******************************************************************************
+ * Test and miscellaneous
+ ******************************************************************************/
+
+/* Registers are directly accessed as pointers to RAM using base and offset
+   calculations from the block and register records.  If register access is 
+   redirected over another bus set this to 0 and implement new versions of
+   ru_reg_write and ru_reg_read. */
+#ifndef RU_EXTERNAL_REGISTER_ADDRESSING
+#define RU_EXTERNAL_REGISTER_ADDRESSING 0
+#endif
+
+/* Register access is redirected to an internal buffer for testing functions
+   when hardware access is not available. It is only meaningful if 
+   RU_DIRECT_REGISTER_ADDRESSING is enabled. */
+#ifndef RU_OFFLINE_TEST
+#define RU_OFFLINE_TEST 0
+#endif
+
+/* Set this to 1 to include a stub main function for simple compile checks */
+#ifndef RU_TEST_COMPILE_STUB
+#define RU_TEST_COMPILE_STUB 0
+#endif
+
+#endif /* End of file _RU_CONFIG_H_ */
+
diff --git a/drivers/net/bcmbca/lport/ag/ru_types.h b/drivers/net/bcmbca/lport/ag/ru_types.h
new file mode 100644
index 0000000000..2bf5e550cf
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/ru_types.h
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    */
+#ifndef _RU_TYPES_H_
+#define _RU_TYPES_H_
+/**
+ * \brief Register tracking type definitions
+ *
+ * The register track module provides functionality to comprehensively debug
+ * register level transactions.  It is a slow interface that should be used in
+ * parallel to standard direct read/write transactions.  The module can parse
+ * registers into easy read field format.  Registers may be looked up by name
+ * or address.
+ *
+ */
+
+#include "lport_types.h"
+#include "ru_config.h"
+
+typedef enum
+{
+    ru_access_read      = 0x01,         /*< Read only */
+    ru_access_write     = 0x02,         /*< Write only */
+    ru_access_rw        = 0x03          /*< Read/write */
+} ru_access;
+
+typedef enum
+{
+	ru_reg_size_8,
+	ru_reg_size_16,
+	ru_reg_size_32,
+	ru_reg_size_64
+}ru_reg_size;
+
+typedef struct
+{
+    const char *name;                   /*< Name of field from reg spec */
+#if RU_INCLUDE_DESC
+    const char *title;                  /*< Short title of the field */
+    const char *desc;                   /*< Detail description */
+#endif
+    uint64_t mask;                      /*< Field bit mask */
+    uint32_t align;                     /*< Unknown, used by register macro */
+    uint32_t bits;                      /*< Field bit width */
+    uint32_t shift;                     /*< Field bit offset */
+#if RU_INCLUDE_ACCESS
+    ru_access access;                   /*< Field read/write access */
+#endif
+} ru_field_rec;                         /*< Field info record */
+
+typedef struct
+{
+    const char *name;                   /*< Name of register from reg spec */
+#if RU_INCLUDE_DESC
+    const char *title;                  /*< Short title of the register */
+    const char *desc;                   /*< Detail description */
+#endif
+    unsigned long addr;                      /*< Block relative register address */
+    uint32_t ram_count;                 /*< RAM addresses, 0 for std register */
+    uint32_t offset;                    /*< Offset of next index in RAM types */
+    uint32_t log_idx;                   /*< Register ID for debug logging */
+#if RU_INCLUDE_ACCESS
+    ru_access access;                   /*< Register read/write access */
+#endif
+#if RU_INCLUDE_FIELD_DB
+    uint32_t field_count;               /*< Number of fields, private */
+    const ru_field_rec **fields;        /*< All fields for register, private */
+#endif
+    ru_reg_size	reg_size;
+} ru_reg_rec;                           /*< Register info record */
+
+typedef struct
+{
+    const char *name;                   /*< Name of the block */
+    unsigned long *addr;                     /*< Block base addresses */
+    uint8_t addr_count;                 /*< Number of block instances */
+    uint32_t reg_count;                 /*< Number of registers, private */
+    const ru_reg_rec **regs;            /*< All registers for block, private */
+} ru_block_rec;                         /*< Info for a block instance */
+
+typedef enum
+{
+    ru_log_none     = 0x00,             /*< Do not log */
+    ru_log_read     = 0x01,             /*< Log read access only */
+    ru_log_write    = 0x02,             /*< Log write access only */
+    ru_log_both     = 0x03              /*< Log both read and write */
+} ru_log_type;                          /*< Access logging type */
+
+typedef enum
+{
+    ru_op_equal,                        /*< (Register & Mask) == Value */
+    ru_op_not_equal,                    /*< (Register & Mask) != Value */
+    ru_op_greater_than,                 /*< (Register & Mask) > Value */
+    ru_op_less_than                     /*< (Register & Mask) < Value */
+} ru_log_op;                            /*< Logging comparator operation */
+
+typedef enum
+{
+	PARAM_NOT_IN_RANGE,
+	BAD_PARAM,
+	ERROR_IN_PARAM,
+} ru_ret_codes;
+
+
+#define RU_BLK(b) b##_BLOCK
+#define RU_REG(b,r) b##_##r##_REG
+#define RU_REG_OFFSET(b,r) b##_##r##_REG_OFFSET
+#define RU_REG_RAM_CNT(b,r) b##_##r##_REG_RAM_CNT
+#define RU_FLD(b,r,f) b##_##r##_##f##_FIELD
+#define RU_FLD_MASK(b,r,f) b##_##r##_##f##_FIELD_MASK
+#define RU_FLD_SHIFT(b,r,f) b##_##r##_##f##_FIELD_SHIFT
+
+typedef uint8_t ru_block_inst;          /*< Multiple block instance index */
+typedef uint32_t ru_ram_addr;           /*< Index for RAM mapped registers */
+
+#endif /* End of file _RU_TYPES_H_ */
diff --git a/drivers/net/bcmbca/lport/ag/xlmac_indirect_access.h b/drivers/net/bcmbca/lport/ag/xlmac_indirect_access.h
new file mode 100644
index 0000000000..21fd62920a
--- /dev/null
+++ b/drivers/net/bcmbca/lport/ag/xlmac_indirect_access.h
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+   
+   */
+/*
+ * xlmac_indirect_access.h
+ *
+ *  Created on: 6 áñôè× 2015
+ *      Author: yonatani
+ */
+
+#ifndef SHARED_OPENSOURCE_DRV_LPORT_XLMAC_INDIRECT_ACCESS_H_
+#define SHARED_OPENSOURCE_DRV_LPORT_XLMAC_INDIRECT_ACCESS_H_
+
+#include "ru_types.h"
+#include "bcm6858_xlmac_conf_ag.h"
+
+#define XLMAC_INDIRECT_WRITE(i,b,r,v) xlmac_indirect_write(i,RU_BLK(b).addr[i] + RU_REG_OFFSET(b,r),v)
+#define XLMAC_INDIRECT_READ(i,b,r,v) xlmac_indirect_read(i,RU_BLK(b).addr[i] + RU_REG_OFFSET(b,r),&v)
+
+static void xlmac_indirect_write(uint32_t portid, uint64_t address, uint64_t val)
+{
+    //fill using holding register
+    uint32_t xlmacid = (portid >> 2) & 0x1;
+    uint32_t holding = (uint32_t)((val >> 32) & 0xFFFFFFFF);
+    uint32_t regval = (uint32_t)(val & 0xFFFFFFFF);
+    ag_drv_xlmac_conf_dir_acc_data_write_set(xlmacid, holding);
+
+    WRITE_32(address, regval);
+}
+
+static void xlmac_indirect_read(uint32_t portid, uint64_t address, uint64_t *val)
+{
+    //fill using holding register
+    uint32_t xlmacid = (portid >> 2) & 0x1;
+    uint32_t value32;
+    uint32_t holding;
+
+    READ_32(address, value32);
+
+    ag_drv_xlmac_conf_dir_acc_data_read_get(xlmacid, &holding);
+
+    *val = (((uint64_t)holding << 32) | value32);
+}
+
+#endif /* SHARED_OPENSOURCE_DRV_LPORT_XLMAC_INDIRECT_ACCESS_H_ */
diff --git a/drivers/net/bcmbca/lport/lport_compat.h b/drivers/net/bcmbca/lport/lport_compat.h
new file mode 100644
index 0000000000..d8199de8ba
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_compat.h
@@ -0,0 +1,21 @@
+#ifndef _LPORT_DELAY_H_
+#define _LPORT_DELAY_H_
+
+#ifdef  __UBOOT__
+#define EXPORT_SYMBOL(...)
+#define UDELAY(_a) udelay(_a)
+#include <linux/delay.h>
+#include <linux/string.h>
+#else
+#define UDELAY(_a) udelay(_a)
+#include <asm/delay.h>
+#include "lport_intr.h"
+#include <linux/workqueue.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/completion.h>
+#include <linux/jiffies.h>
+#include <linux/string.h>
+#endif
+
+#endif
diff --git a/drivers/net/bcmbca/lport/lport_defs.h b/drivers/net/bcmbca/lport/lport_defs.h
new file mode 100644
index 0000000000..5c06629b4c
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_defs.h
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+   
+   */
+/*
+ * lport_defs.h
+ *
+ *  Created on: April 2015
+ *      Author: yonatani
+ */
+
+#ifndef SHARED_OPENSOURCE_DRV_LPORT_LPORT_DEFS_H_
+#define SHARED_OPENSOURCE_DRV_LPORT_LPORT_DEFS_H_
+
+#include "lport_types.h"
+
+//defines
+#define LPORT_TX_THRESHOLD 4
+#define LPORT_NUM_OF_PORTS_PER_XLMAC 4
+#define LPORT_NUM_OF_XLMACS 2
+/* ONLY 7 ports are applicable in revision A0 */
+#define LPORT_NUM_OF_PORTS ((LPORT_NUM_OF_XLMACS * LPORT_NUM_OF_PORTS_PER_XLMAC))
+#define LPORT_NUM_OF_RGMII 3
+#define LPORT_LAST_EGPHY_PORT 3
+#define LPORT_FIRST_RGMII_PORT 4
+#define LPORT_IS_SERDES_PORT(mux) (mux >= PORT_SGMII && mux <= PORT_XFI)
+#define LPORT_IS_XFI_PORT(mux) (mux >= PORT_SFI && mux <= PORT_XFI)
+
+/* TSC_CLK = 644MHz = 1.553ns, TS_CLK = 250MHz = 4ns
+ * ts_tsts_adjust = 2.5 TSC_CLK period + One TS_CLK period = 2.5 * 1.553 + 4 = 7.88
+ * ts_osts_adjust = 6 TSC CLK period + One TS_CLK period = 6 * 1.553 + 4 = 13.2
+ */
+#define TS_TSTS_ADJ 8
+#define TS_OSTS_ADJ 13
+
+//typedefs
+typedef enum
+{
+    LPORT_ERR_OK = 0,
+    LPORT_ERR_PARAM = -1,
+    LPORT_ERR_STATE = -2,
+    LPORT_ERR_IO = -3,
+    LPORT_ERR_RANGE = -3,
+    LPORT_ERR_FIFO_EMPTY = -4,
+    LPORT_ERR_INVALID = -5,
+}LPORT_RC;
+
+typedef enum
+{
+    PORT_UNAVAIL = 0,
+    PORT_SGMII,
+    PORT_SGMII_AN_IEEE_CL37,
+    PORT_SGMII_AN_USER_CL37,
+    PORT_SGMII_AN_SLAVE,
+    PORT_SGMII_AN_MASTER,
+    PORT_HSGMII,
+    PORT_SFI,
+    PORT_XFI,
+    PORT_GPHY,
+    PORT_RGMII
+}LPORT_PORT_MUX_SELECT;
+
+typedef enum
+{
+    LPORT_RATE_UNKNOWN = 0,
+    LPORT_RATE_10MB,
+    LPORT_RATE_100MB,
+    LPORT_RATE_1000MB,
+    LPORT_RATE_2500MB,
+    LPORT_RATE_10G,
+}LPORT_PORT_RATE;
+
+typedef enum
+{
+    LPORT_HALF_DUPLEX,
+    LPORT_FULL_DUPLEX
+}LPORT_PORT_DUPLEX;
+
+typedef enum
+{
+    XLMAC_CRC_APPEND,
+    XLMAC_CRC_KEEP,
+    XLMAC_CRC_REPLACE,
+    XLMAC_CRC_PERPKT
+}XLMAC_CRC_MODE;
+
+typedef struct
+{
+    uint8_t valid;
+    uint8_t eee_enable;
+    uint8_t rvmii_ref;/*0=50mhz,1=25mhz*/
+    uint8_t portmode;/*2=Mii,3=RGMII,4=RvMII*/
+    uint8_t delay_rx;/*rgmii rx delay enabled*/
+    uint8_t delay_tx;/*rgmii tx delay enabled*/
+    uint8_t ib_status_overide;/*if set user can set the status ,used when working in MAC2MAC mode*/
+    uint8_t is_1p8v; /*rgmii connected to 1.8v*/
+    uint8_t phy_attached; /*Phy is connected to RGMII port*/
+    uint16_t phyid;/*PhyID if exists*/
+}lport_rgmii_cfg_s;
+
+typedef struct
+{
+    LPORT_PORT_MUX_SELECT prt_mux_sel[LPORT_NUM_OF_PORTS];
+    int has_rgmii_cfg;
+    lport_rgmii_cfg_s rgmii_cfg[LPORT_NUM_OF_RGMII];
+}lport_init_s;
+
+typedef struct
+{
+    uint8_t local_loopback;
+    uint8_t pad_en;
+    uint8_t pad_threashold;
+    uint8_t average_igp;
+    uint8_t tx_threshold;
+    uint8_t tx_preamble_len;
+    uint8_t throt_num;
+    uint8_t throt_denom;
+    LPORT_PORT_RATE speed;
+}lport_port_cfg_s;
+
+typedef struct
+{
+    uint64_t tx_ctrl_sa;
+    uint64_t rx_ctrl_sa;
+    uint8_t  rx_pass_ctrl;
+    uint8_t  rx_pass_pause;
+    uint16_t pause_xoff_timer;
+    uint8_t  rx_pause_en;
+    uint8_t  tx_pause_en;
+    uint8_t  pause_refresh_en;
+    uint16_t pause_refresh_timer;
+}lport_flow_ctrl_cfg_s;
+
+typedef struct
+{
+    uint8_t autoneg_en;
+    uint8_t port_up;
+    LPORT_PORT_RATE rate;
+    LPORT_PORT_DUPLEX duplex;
+    uint8_t rx_pause_en;
+    uint8_t tx_pause_en;
+}lport_port_status_s;
+
+typedef struct
+{
+    uint8_t autoneg_en;
+    uint8_t port_up;
+    uint32_t rate_adv_map;
+    LPORT_PORT_DUPLEX duplex;
+    uint8_t rx_pause_en;
+    uint8_t tx_pause_en;
+}lport_port_phycfg_s;
+
+typedef struct
+{
+    uint8_t rgmii_da_mac[6];
+    uint16_t payload_len;
+    uint8_t ate_en;
+}lport_rgmii_ate_s;
+
+#endif /* SHARED_OPENSOURCE_DRV_LPORT_LPORT_DEFS_H_ */
diff --git a/drivers/net/bcmbca/lport/lport_drv.c b/drivers/net/bcmbca/lport/lport_drv.c
new file mode 100644
index 0000000000..937d73e167
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_drv.c
@@ -0,0 +1,1924 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+   
+   */
+/*
+ * lport_drv.c
+ *
+ *  Created on: April 2015
+ *      Author: yonatani
+ */
+
+//includes
+#include "bcm6858_drivers_lport_ag.h"
+#include "bcm6858_lport_ctrl_ag.h"
+#include "bcm6858_lport_xlmac_ag.h"
+#include "bcm6858_lport_mab_ag.h"
+#include "bcm6858_lport_rgmii_ag.h"
+#include "bcm6858_xlmac_conf_ag.h"
+#include "bcm6858_mib_conf_ag.h"
+#include "bcm6858_lport_led_ag.h"
+#include "bcm6858_lport_intr_ag.h"
+#include "bcm6858_lport_srds_ag.h"
+#include "lport_compat.h"
+#include "lport_drv.h"
+#include "lport_intr.h"
+#include "lport_mdio.h"
+#include "serdes_access.h"
+#include "bcm_bca_leds_dt_bindings.h"
+#include "bcm_bca_leds.h"
+#include "dt_access.h"
+
+static uintptr_t lport_phys_base;
+static uintptr_t lport_virt_base;
+static uintptr_t misc_virt_base;
+static uintptr_t xlif_virt_base;
+static uint16_t base_addr = 1;
+
+static void remap_ru_block_single_virtbase(const ru_block_rec *ru_block, uintptr_t virt_offset)
+{
+    uint32_t addr_itr;
+    uintptr_t phys_addr, virt_addr;
+
+    for (addr_itr = 0; addr_itr < ru_block->addr_count; addr_itr++)
+    {
+        phys_addr = ru_block->addr[addr_itr];
+        virt_addr = ru_block->addr[addr_itr] + virt_offset;
+        ru_block->addr[addr_itr] = virt_addr;
+
+        pr_err("%-11s %1d Remapped physical 0x%lx to virtual 0x%lx\n",
+            ru_block->name, addr_itr, phys_addr, virt_addr);
+    }
+}
+
+/* This function is a utility to fix virtual address of the RU/HAL based driver.
+ * After calling this function all RU addresses will turn virtual and no translation is needed during read/write
+ * ru_blocks[] is the main ru object of the lport block
+ */
+static void remap_ru_block_addrs(void)
+{
+    const ru_block_rec **ru_blocks = RU_LPORT_BLOCKS;
+    uint32_t blk;
+    uintptr_t virt_offset = lport_virt_base - lport_phys_base;
+
+    for (blk = 0; ru_blocks[blk]; blk++)
+    {
+        remap_ru_block_single_virtbase(ru_blocks[blk], virt_offset);
+    }
+}
+
+static int lport_probe(dt_device_t *pdev)
+{
+    int ret;
+    dt_handle_t node = dt_dev_get_handle(pdev);
+
+    lport_virt_base = dt_dev_remap_resource(pdev, 0);
+    if (IS_ERR(lport_virt_base))
+    {
+        ret = PTR_ERR(lport_virt_base);
+        lport_virt_base = NULL;
+        goto Exit;
+    }
+
+    misc_virt_base = dt_dev_remap(pdev, 1);
+    if (IS_ERR(misc_virt_base))
+    {
+        ret = PTR_ERR(misc_virt_base);
+        misc_virt_base = NULL;
+        goto Exit;
+    }
+
+    xlif_virt_base = dt_dev_remap(pdev, 2);
+    if (IS_ERR(xlif_virt_base))
+    {
+        ret = PTR_ERR(xlif_virt_base);
+        xlif_virt_base = NULL;
+        goto Exit;
+    }
+
+    lport_phys_base = dt_dev_read_addr(pdev ,0);
+    if (!lport_phys_base)
+    {
+        ret = -1;
+        goto Exit;
+    }
+
+    remap_ru_block_addrs();
+
+    base_addr = dt_property_read_u32_default(node, "base-addr", base_addr);
+
+    dev_dbg(&pdev->dev, "base-addr=%d\n", base_addr);
+    dev_info(&pdev->dev, "registered\n");
+
+    return 0;
+
+Exit:
+    return ret;
+}
+
+#ifdef __UBOOT__
+static const struct udevice_id lport_ids[] = {
+    { .compatible = "brcm,lport" },
+    { /* end of list */ },
+};
+
+U_BOOT_DRIVER(brcm_lport) = {
+    .name	= "brcm-lport",
+    .id	= UCLASS_MISC,
+    .of_match = lport_ids,
+    .probe = lport_probe,
+};
+#else
+static const struct of_device_id of_platform_table[] = {
+    { .compatible = "brcm,lport" },
+    { /* end of list */ },
+};
+
+static struct platform_driver of_platform_driver = {
+    .driver = {
+        .name = "brcm-lport",
+        .of_match_table = of_platform_table,
+    },
+    .probe = lport_probe,
+};
+module_platform_driver(of_platform_driver);
+#endif
+
+int lport_set_rgmii_ib_status(uint32_t rgmii_id, lport_port_status_s *port_status);
+
+#define LPORT_XLMAC_G9991_RSV_MASK (0x20058)
+/*
+ *LPORT MUX OPTIONS:
+ *
+ *LPORT Block has two instances of XLMAC BLOCKS which has Muxes towards the user ports, these muxes can select the XLMAC function
+ *
+ * XLMAC0 Options:
+ * 1. Port 0 as 10G Merlin (ports 1,2,3 are disabled).
+ * 2. All 4 Ports to Merlins in rates 2.5G/1G/100M/10M
+ * 3. All 4 ports to QGphy
+ * 4. Combination of Merlin & QGphy
+ *
+ * XLMAC1 Options:
+ * 1. Port 4 as 10G Merlin (ports 5,6,7 are disabled).
+ * 2. All 3 Ports to RGMII
+ * 3. All 4 ports to Merlin in rates 2.5G/1G/100M/10M
+ * 4. Combination of Merlin & RGMII
+ *
+ */
+
+/*This mux define is used to configure register LPORT_REG_CNTRL*/
+typedef enum
+{
+    LPORT_MUX_REG_SERDES = 1,
+    LPORT_MUX_REG_RGMII = 0,
+    LPORT_MUX_REG_EGPHY = 0
+}E_LPORT_MUX_REG;
+
+typedef enum
+{
+    LPORT_XLMAC_GMII,
+    LPORT_XLMAC_XGMII
+}E_LPORT_XLMAC_MODE;
+
+static lport_init_s lport_init_cfg = {};
+static lport_init_s lport_curr_cfg = {};
+static lport_rgmii_cfg_s local_lport_rgmii_cfg[LPORT_NUM_OF_RGMII] = {{}};
+
+int validate_lport_configuration(lport_init_s *init_params)
+{
+    int iter;
+    LPORT_PORT_MUX_SELECT *prt_mux_sel = init_params->prt_mux_sel;
+
+    //validate only port 0 & 4 are assigned as possible 10G
+    for (iter = 0; iter < LPORT_NUM_OF_PORTS; iter++)
+    {
+        //valivate RGMII only from XLMAC1 only
+        if (iter < 4 && prt_mux_sel[iter] == PORT_RGMII)
+        {
+            pr_err("Port %d can't work in RGMII mode\n", iter);
+            return LPORT_ERR_PARAM;
+        }
+        if (iter > 3 && prt_mux_sel[iter] == PORT_GPHY)
+        {
+            pr_err("Port %d can't work in GPHY mode\n", iter);
+            return LPORT_ERR_PARAM;
+        }
+        if (iter != 0 && iter != 4 && LPORT_IS_XFI_PORT(prt_mux_sel[iter]))
+        {
+            pr_err("Port %d can't work in XFI mode\n", iter);
+            return LPORT_ERR_PARAM;
+        }
+    }
+
+    //validate no collision on serdes mux
+    if (LPORT_IS_SERDES_PORT(prt_mux_sel[0]) && LPORT_IS_SERDES_PORT(prt_mux_sel[7]))
+    {
+        pr_err("ERROR: Only one port(0,7) can be muxed to Merlin at the same time\n");
+        return LPORT_ERR_PARAM;
+    }
+
+    if (LPORT_IS_SERDES_PORT(prt_mux_sel[1]) && LPORT_IS_SERDES_PORT(prt_mux_sel[4]))
+    {
+        pr_err("ERROR: Only one port(1,4) can be muxed to Merlin at the same time\n");
+        return LPORT_ERR_PARAM;
+    }
+
+    if (LPORT_IS_SERDES_PORT(prt_mux_sel[2]) && LPORT_IS_SERDES_PORT(prt_mux_sel[5]))
+    {
+        pr_err("ERROR: Only one port(2,5) can be muxed to Merlin at the same time\n");
+        return LPORT_ERR_PARAM;
+    }
+
+    if (LPORT_IS_SERDES_PORT(prt_mux_sel[3]) && LPORT_IS_SERDES_PORT(prt_mux_sel[6]))
+    {
+        pr_err("ERROR: Only one port(3,6) can be muxed to Merlin at the same time\n");
+        return LPORT_ERR_PARAM;
+    }
+
+    return LPORT_ERR_OK;
+}
+
+static int lport_speed_to_xlmac(LPORT_PORT_RATE lport_speed)
+{
+    int ret = 0;
+
+    switch (lport_speed)
+    {
+    case LPORT_RATE_10MB:
+        ret = 0;
+        break;
+    case LPORT_RATE_100MB:
+        ret = 1;
+        break;
+    case LPORT_RATE_1000MB:
+        ret = 2;
+        break;
+    case LPORT_RATE_2500MB:
+        ret = 3;
+        break;
+    case LPORT_RATE_10G:
+        ret = 4;
+        break;
+    case LPORT_RATE_UNKNOWN:
+    default:
+        pr_err("Wrong lport speed %d\n", lport_speed);
+    }
+
+    return ret;
+}
+
+LPORT_PORT_RATE lport_speed_get(uint8_t portid)
+{
+    uint8_t speed_mode, no_sop_for_crc_hg, hdr_mode;
+    LPORT_PORT_RATE lport_speed = LPORT_RATE_UNKNOWN;
+
+    if (ag_drv_lport_xlmac_mode_get(portid, &speed_mode, &no_sop_for_crc_hg, &hdr_mode))
+        return LPORT_RATE_UNKNOWN;
+
+    switch (speed_mode)
+    {
+    case 0: /* 10M */
+        lport_speed = LPORT_RATE_10MB;
+        break;
+
+    case 1: /* 100Mbps */
+        lport_speed = LPORT_RATE_100MB;
+        break;
+
+    case 2: /* 1000Mbps */
+        lport_speed = LPORT_RATE_1000MB;
+        break;
+
+    case 3: /* 2500Mbps */
+        lport_speed = LPORT_RATE_2500MB;
+        break;
+
+    case 4: /* 5000/10000Mbps */
+        lport_speed = LPORT_RATE_10G;
+        break;
+
+    default:
+        lport_speed = LPORT_RATE_UNKNOWN;
+    }
+
+    return lport_speed;
+}
+
+
+static int xlmac_init(lport_init_s *init_params)
+{
+    lport_xlmac_ctrl     ctrl;
+    lport_xlmac_tx_ctrl  tx_ctrl;
+    lport_xlmac_rx_ctrl  rx_ctrl;
+#ifdef CONFIG_BCM_PTP_1588
+    xlmac_conf_config config = {};
+#endif
+    uint32_t i;
+    int rc = LPORT_ERR_OK;
+
+    for (i = 0; i < LPORT_NUM_OF_PORTS; i++)
+    {
+        LPORT_PORT_MUX_SELECT prt_mux_sel = init_params->prt_mux_sel[i];
+
+        if (prt_mux_sel != PORT_UNAVAIL)
+        {
+            rc = ag_drv_lport_xlmac_ctrl_get(i, &ctrl);
+            rc = rc ? rc : ag_drv_lport_xlmac_tx_ctrl_get(i, &tx_ctrl);
+
+#ifdef G9991
+            /*In G9991 Application, DSP engine sends to XLMAC segmented frames which are not
+             * native ethernet frames, XLMAC will try to match ethertype to EthernetII and will fail
+             * then it will pass to BBH RX failure signal, need to mask this failure bit to prevent it*/
+            rc = rc ? rc : ag_drv_xlmac_conf_port_0_rxerr_mask_set(0, LPORT_XLMAC_G9991_RSV_MASK);
+            rc = rc ? rc : ag_drv_xlmac_conf_port_1_rxerr_mask_set(0, LPORT_XLMAC_G9991_RSV_MASK);
+            rc = rc ? rc : ag_drv_xlmac_conf_port_2_rxerr_mask_set(0, LPORT_XLMAC_G9991_RSV_MASK);
+            rc = rc ? rc : ag_drv_xlmac_conf_port_3_rxerr_mask_set(0, LPORT_XLMAC_G9991_RSV_MASK);
+            rc = rc ? rc : ag_drv_xlmac_conf_port_0_rxerr_mask_set(1, LPORT_XLMAC_G9991_RSV_MASK);
+            rc = rc ? rc : ag_drv_xlmac_conf_port_1_rxerr_mask_set(1, LPORT_XLMAC_G9991_RSV_MASK);
+            rc = rc ? rc : ag_drv_xlmac_conf_port_2_rxerr_mask_set(1, LPORT_XLMAC_G9991_RSV_MASK);
+            rc = rc ? rc : ag_drv_xlmac_conf_port_3_rxerr_mask_set(1, LPORT_XLMAC_G9991_RSV_MASK);
+#endif
+            /*TODO: Change crc_mode to PER_PACKET when HW confirm usage
+             * when doing REPLACE packet must be padded by 4 bytes*/
+            tx_ctrl.crc_mode = XLMAC_CRC_PERPKT;
+            tx_ctrl.pad_en = 1;
+
+            /*In order to prevent Underflow*/
+            tx_ctrl.tx_threshold = LPORT_TX_THRESHOLD;
+            rc = rc ? rc : ag_drv_lport_xlmac_tx_ctrl_set(i, &tx_ctrl);
+
+            rc = rc ? rc : ag_drv_lport_xlmac_rx_ctrl_get(i, &rx_ctrl);
+            rx_ctrl.strip_crc = 0;
+            rc = rc ? rc : ag_drv_lport_xlmac_rx_ctrl_set(i, &rx_ctrl);
+
+            switch (prt_mux_sel)
+            {
+            case PORT_SFI ... PORT_XFI:
+                rc = rc ? rc : ag_drv_lport_xlmac_mode_set(i, lport_speed_to_xlmac(LPORT_RATE_10G), 0, 0);
+                break;
+            case PORT_HSGMII:
+                rc = rc ? rc : ag_drv_lport_xlmac_mode_set(i, lport_speed_to_xlmac(LPORT_RATE_2500MB), 0, 0);
+                break;
+            default:
+                rc = rc ? rc : ag_drv_lport_xlmac_mode_set(i, lport_speed_to_xlmac(LPORT_RATE_1000MB), 0, 0);
+            }
+
+            rc = rc ? rc : ag_drv_lport_xlmac_tx_crc_corrupt_ctrl_set(i ,0 ,0 ,0, 0);
+
+            ctrl.soft_reset = 0;
+            rc = rc ? rc : ag_drv_lport_xlmac_ctrl_set(i, &ctrl);
+
+            rc = rc ? rc : ag_drv_lport_xlmac_timestamp_adjust_set(i, 0, TS_TSTS_ADJ, TS_OSTS_ADJ);
+        }
+    }
+
+#ifdef CONFIG_BCM_PTP_1588
+    for (i = 0; i < LPORT_NUM_OF_XLMACS; i++)
+    {
+        rc = rc ? rc : ag_drv_xlmac_conf_config_get(i, &config);
+
+        config.osts_timer_disable = 0;
+        config.bypass_osts = 0;
+        config.egr_1588_timestamping_mode = 1;
+
+        rc = rc ? rc : ag_drv_xlmac_conf_config_set(i, &config);
+    }
+#endif
+
+    return rc;
+}
+
+static int msbus_init(lport_init_s *init_params)
+{
+    lport_mab_cntrl mab_cntrl;
+    lport_mab_tx_wrr_ctrl wrr;
+    uint32_t i, j;
+    int rc = LPORT_ERR_OK;
+
+    for (i = 0; i < LPORT_NUM_OF_XLMACS; i++) 
+    {
+        rc = rc ? rc : ag_drv_lport_mab_cntrl_get(i, &mab_cntrl);
+        rc = rc ? rc : ag_drv_lport_mab_tx_wrr_ctrl_get(i, &wrr);
+
+        mab_cntrl.link_down_rst_en = 0x1;
+
+        mab_cntrl.gmii_rx_rst = 0xf;
+        mab_cntrl.gmii_tx_rst = 0xf;
+        mab_cntrl.xgmii_rx_rst = 0x1;
+        mab_cntrl.xgmii_tx_rst = 0x1;
+
+        wrr.p4_weight = 0;
+        wrr.p5_weight = 0;
+        wrr.p6_weight = 0;
+        wrr.p7_weight = 0;
+
+        for (j = 0; j < LPORT_NUM_OF_PORTS_PER_XLMAC; j++)
+        {
+            uint32_t idx = i * LPORT_NUM_OF_PORTS_PER_XLMAC + j;
+
+            if (init_params->prt_mux_sel[idx] != PORT_UNAVAIL)
+            {
+                if (LPORT_IS_XFI_PORT(init_params->prt_mux_sel[idx]))
+                {
+                    mab_cntrl.xgmii_rx_rst = 0x0;
+                    mab_cntrl.xgmii_tx_rst = 0x0;
+                    wrr.p4_weight = 3;
+                }
+                else
+                {
+                    mab_cntrl.gmii_rx_rst &= ~(1 << j);
+                    mab_cntrl.gmii_tx_rst &= ~(1 << j);
+
+                    if (j == 0)
+                        wrr.p4_weight = 1;
+                    if (j == 1)
+                        wrr.p5_weight = 1;
+                    if (j == 2)
+                        wrr.p6_weight = 1;
+                    if (j == 3)
+                        wrr.p7_weight = 1;
+                }
+            }
+        }
+
+        wrr.arb_mode = 0;
+        rc = rc ? rc : ag_drv_lport_mab_tx_wrr_ctrl_set(i, &wrr);
+        rc = rc ? rc : ag_drv_lport_mab_cntrl_set(i , &mab_cntrl);
+    }
+
+    return rc;
+}
+
+int lport_mux_init(lport_init_s *init_params)
+{
+    lport_ctrl_control control = {};
+
+    //go over all 8 ports and configure the output
+
+    if (LPORT_IS_XFI_PORT(init_params->prt_mux_sel[0]))
+        control.p0_mode = LPORT_XLMAC_XGMII;
+    else
+        control.p0_mode = LPORT_XLMAC_GMII;
+
+    if (LPORT_IS_XFI_PORT(init_params->prt_mux_sel[4]))
+        control.p4_mode = LPORT_XLMAC_XGMII;
+    else
+        control.p4_mode = LPORT_XLMAC_GMII;
+
+    if (LPORT_IS_SERDES_PORT(init_params->prt_mux_sel[0]))
+        control.gport_sel_0 = LPORT_MUX_REG_SERDES;
+    else
+        control.gport_sel_0 = LPORT_MUX_REG_EGPHY;
+
+    if (LPORT_IS_SERDES_PORT(init_params->prt_mux_sel[1]))
+        control.gport_sel_1 = LPORT_MUX_REG_SERDES;
+    else
+        control.gport_sel_1 = LPORT_MUX_REG_EGPHY;
+
+    if (LPORT_IS_SERDES_PORT(init_params->prt_mux_sel[2]))
+        control.gport_sel_2 = LPORT_MUX_REG_SERDES;
+    else
+        control.gport_sel_2 = LPORT_MUX_REG_EGPHY;
+
+    if (LPORT_IS_SERDES_PORT(init_params->prt_mux_sel[3]))
+        control.gport_sel_3 = LPORT_MUX_REG_SERDES;
+    else
+        control.gport_sel_3 = LPORT_MUX_REG_EGPHY;
+
+    if (LPORT_IS_SERDES_PORT(init_params->prt_mux_sel[4]))
+        control.gport_sel_4 = LPORT_MUX_REG_SERDES;
+    else
+        control.gport_sel_4 = LPORT_MUX_REG_RGMII;
+
+    if (LPORT_IS_SERDES_PORT(init_params->prt_mux_sel[5]))
+        control.gport_sel_5 = LPORT_MUX_REG_SERDES;
+    else
+        control.gport_sel_5 = LPORT_MUX_REG_RGMII;
+
+    if (LPORT_IS_SERDES_PORT(init_params->prt_mux_sel[6]))
+        control.gport_sel_6 = LPORT_MUX_REG_SERDES;
+    else
+        control.gport_sel_6 = LPORT_MUX_REG_RGMII;
+
+    if (LPORT_IS_SERDES_PORT(init_params->prt_mux_sel[7]))
+        control.gport_sel_7 = LPORT_MUX_REG_SERDES;
+    else
+        control.gport_sel_7 = LPORT_MUX_REG_RGMII;
+
+    return ag_drv_lport_ctrl_control_set(&control);
+}
+
+static int rgmii_init(lport_init_s *init_params)
+{
+    uint32_t i;
+    lport_rgmii_cfg_s rgmii_cfg;
+    int rc = LPORT_ERR_OK;
+    int has_phy;
+
+    for (i = LPORT_FIRST_RGMII_PORT; i < LPORT_NUM_OF_PORTS; i++)
+    {
+        if (init_params->prt_mux_sel[i] != PORT_RGMII)
+            continue;
+
+        if (lport_get_rgmii_cfg(i, &rgmii_cfg))
+        {
+            pr_err("Failed to get RGMII configuration for lport %d\n", i);
+            return -1;
+        }
+
+        has_phy = init_params->rgmii_cfg[i - LPORT_FIRST_RGMII_PORT].phy_attached;
+        rgmii_cfg.is_1p8v = init_params->rgmii_cfg[i - LPORT_FIRST_RGMII_PORT].is_1p8v;
+        rgmii_cfg.delay_rx = init_params->rgmii_cfg[i - LPORT_FIRST_RGMII_PORT].delay_rx;
+        rgmii_cfg.delay_tx = init_params->rgmii_cfg[i - LPORT_FIRST_RGMII_PORT].delay_tx;
+
+        rgmii_cfg.ib_status_overide = 0;
+        rgmii_cfg.portmode = 3;
+        rgmii_cfg.valid = 1;
+
+
+        if (lport_set_rgmii_cfg(i, &rgmii_cfg))
+        {
+            pr_err("Failed to set RGMII configuration for lport %d\n", i);
+            return -1;
+        }
+
+        if (!has_phy)
+        {
+
+            lport_port_status_s port_status = {};
+
+            port_status.port_up = 1;
+            port_status.rate = LPORT_RATE_1000MB;
+            port_status.duplex = 1;
+
+            rc = rc ? rc : lport_set_rgmii_ib_status(i - LPORT_FIRST_RGMII_PORT, &port_status);
+        }
+    }
+
+    return rc;
+}
+
+/*
+** Misc Register Set Definitions.
+*/
+
+typedef struct Misc {
+    uint32_t miscStrapBus;                       /* 0x00 */
+#define MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT        5
+#define MISC_STRAP_BUS_BOOT_SEL0_4_MASK         (0x18 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL5_SHIFT          11
+#define MISC_STRAP_BUS_BOOT_SEL5_MASK           (0x1 << MISC_STRAP_BUS_BOOT_SEL5_SHIFT)
+#define BOOT_SEL5_STRAP_ADJ_SHIFT               (MISC_STRAP_BUS_BOOT_SEL5_SHIFT-MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+
+    /* boot select bits 0-2 */
+#define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+#define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL0_4_SHIFT)
+
+    /* boot select bits 3-5 */
+#define BOOT_SEL_STRAP_NAND_2K_PAGE             0x00
+#define BOOT_SEL_STRAP_NAND_4K_PAGE             0x08
+#define BOOT_SEL_STRAP_NAND_8K_PAGE             0x10
+#define BOOT_SEL_STRAP_NAND_512B_PAGE           0x18
+#define BOOT_SEL_STRAP_SPI_NOR                  0x38
+#define BOOT_SEL_STRAP_EMMC                     0x30
+#define BOOT_SEL_STRAP_SPI_NAND                 0x28
+
+#define BOOT_SEL_STRAP_BOOT_SEL_MASK            (0x38)
+#define BOOT_SEL_STRAP_PAGE_SIZE_MASK           (0x7)
+
+#define MISC_STRAP_BUS_PCIE_SATA_MASK           (1 << 3)
+#define MISC_STRAP_BUS_BOOROM_BOOT_N            (1 << 10 )
+#define MISC_STRAP_BUS_B53_NO_BOOT              (1 << 12) /* 1 = PMC boots before B53 */
+#define MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT       13
+#define MISC_STRAP_BUS_PMC_ROM_BOOT             (0x1 << MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT) /* 1 = PMC boot */
+#define MISC_STRAP_BUS_CPU_SLOW_FREQ            (1 << 14) /* 1 = Slow 400MHz cpu freq */
+#define MISC_STRAP_BUS_PMC_BOOT_AVS             (1 << 20) /* 1 = PMC run AVS */
+#define MISC_STRAP_BUS_PMC_BOOT_FLASH           (1 << 21) /* 1 = PMC boot from flash */ 
+#define MISC_STRAP_BUS_UBUS_FREQ_SHIFT          22
+#define MISC_STRAP_BUS_UBUS_FREQ_MASK           (1 << MISC_STRAP_BUS_UBUS_FREQ_SHIFT) /* 1 = 2GHz, 0 = 1GHz */  
+#define MISC_STRAP_DDR_16B_EN_SHIFT             26
+#define MISC_STRAP_DDR_16B_EN_MASK              (1 << MISC_STRAP_DDR_16B_EN_SHIFT)
+#define MISC_STRAP_DDR_DENSITY_SHIFT            15
+#define MISC_STRAP_DDR_DENSITY_MASK             (3 << MISC_STRAP_DDR_DENSITY_SHIFT) /* 1=8Gb, 2=4Gb, 3=2Gb */
+#define MISC_STRAP_DDR_OVERRIDE_N_SHIFT         17
+#define MISC_STRAP_DDR_OVERRIDE_N_MASK          (1 << MISC_STRAP_DDR_OVERRIDE_N_SHIFT)
+#define MISC_STRAP_OEC_SHIFT                    24
+#define MISC_STRAP_OEC_MASK                     (0x3 << MISC_STRAP_OEC_SHIFT)
+#define MISC_STRAP_OEC_156MHZ                   0x1
+#define MISC_STRAP_OEC_155MHZ                   0x2
+#define MISC_STRAP_OEC_50MHZ                    0x3
+
+    uint32_t miscStrapOverride;                  /* 0x04 */
+    uint32_t miscSWdebug[6];                     /* 0x08-0x1c */
+    uint32_t miscWDresetCtrl;                    /* 0x20 */
+    uint32_t miscSWdebugNW[2];                   /* 0x24-0x28 */
+    uint32_t miscSoftResetB;                     /* 0x2c */
+    uint32_t miscPLLstatus;                      /* 0x30 */
+    uint32_t miscDierevid;                       /* 0x34 */
+    uint32_t miscSPImasterCtrl;                  /* 0x38 */
+    uint32_t miscAltBoot;                        /* 0x3c */
+    uint32_t miscPeriphCtrl;                     /* 0x40 */
+#define MISC_PCIE_CTRL_CORE_SOFT_RESET_MASK     (0x7)
+    uint32_t miscPCIECtrl;                       /* 0x44 */
+    uint32_t miscAdslClockSample;                /* 0x48 */
+    uint32_t miscRNGCtrl;                        /* 0x4c */
+    uint32_t miscMbox0_data;                     /* 0x50 */
+    uint32_t miscMbox1_data;                     /* 0x54 */
+    uint32_t miscMbox2_data;                     /* 0x58 */
+    uint32_t miscMbox3_data;                     /* 0x5c */
+    uint32_t miscMbox_ctrl;                      /* 0x60 */
+    uint32_t miscMIIPadCtrl;                     /* 0x64 */
+    uint32_t miscRGMII1PadCtrl;                  /* 0x68 */
+    uint32_t miscRGMII2PadCtrl;                  /* 0x6c */
+    uint32_t miscRGMII3PadCtrl;                  /* 0x70 */
+    uint32_t miscMIIPullCtrl;                    /* 0x74 */
+    uint32_t miscRGMII1PullCtrl;                 /* 0x78 */
+    uint32_t miscRGMII2PullCtrl;                 /* 0x7c */
+    uint32_t miscRGMII3PullCtrl;                 /* 0x80 */
+    uint32_t miscWDenReset;                      /* 0x84 */
+    uint32_t miscBootOverlayEn;                  /* 0x88 */
+    uint32_t miscSGMIIfiber;                     /* 0x8c */
+    uint32_t miscUNIMACCtrl;                     /* 0x90 */
+    uint32_t miscMaskUBUSErr;                    /* 0x94 */
+    uint32_t miscTOSsync;                        /* 0x98 */
+    uint32_t miscPM0_1_status;                   /* 0x9c */
+    uint32_t miscPM2_3_status;                   /* 0xa0 */
+    uint32_t miscSGB_status;                     /* 0xa4 */
+    uint32_t miscPM0_1_config;                   /* 0xa8 */
+    uint32_t miscPM2_3_config;                   /* 0xac */
+    uint32_t miscSGB_config;                     /* 0xb0 */
+    uint32_t miscPM0_1_tmon_config;              /* 0xb4 */
+    uint32_t miscPM2_3_tmon_config;              /* 0xb8 */
+    uint32_t miscSGB_tmon_config;                /* 0xbc */
+    uint32_t miscMDIOmasterSelect;               /* 0xc0 */
+    uint32_t miscUSIMCtrl;                       /* 0xc4 */
+    uint32_t miscUSIMPadCtrl;                    /* 0xc8 */
+    uint32_t miscPerSpareReg[3];                 /* 0xcc - 0xd4 */
+    uint32_t miscDgSensePadCtrl;                 /* 0xd8 */
+#define DG_CTRL_SHIFT   4
+#define DG_EN_SHIFT     3
+#define DG_TRIM_SHIFT   0
+    uint32_t miscPeriphMiscCtrl;                 /* 0xdc */
+    uint32_t miscPeriphMiscStat;                 /* 0xe0 */
+} Misc;
+
+#define MISC ((volatile Misc * const)misc_virt_base)
+
+#pragma pack(push,1)
+typedef struct
+{
+    uint32_t GMII_PAD_SEL:3;
+    uint32_t GMII_PAD_AMP_EN:1;
+    uint32_t GMII_PAD_SEL_GMII:1;
+    uint32_t GMII_PAD_IND:1;
+    uint32_t GMII_PAD_MODEHV:1;
+    uint32_t Reserved:25;
+} pad_ctrl_t;
+#pragma pack(pop)
+
+static int rgmii_port_pad_is_1p8v(uint32_t portid)
+{
+    volatile pad_ctrl_t *pad_ctrl;
+
+    if (portid == 4)
+        pad_ctrl = (pad_ctrl_t *)&MISC->miscRGMII3PadCtrl;
+    else if (portid == 5)
+        pad_ctrl = (pad_ctrl_t *)&MISC->miscRGMII1PadCtrl;
+    else if (portid == 6)
+        pad_ctrl = (pad_ctrl_t *)&MISC->miscRGMII2PadCtrl;
+    else
+        return 0;
+
+    return pad_ctrl->GMII_PAD_AMP_EN ? 1 : 0;
+}
+
+static void rgmii_port_pad_init(uint32_t portid, int is_1p8v)
+{
+    uint32_t pad_sel = 6; /* 14mA */
+    volatile pad_ctrl_t *pad_ctrl;
+
+    if (portid == 4)
+        pad_ctrl = (pad_ctrl_t *)&MISC->miscRGMII3PadCtrl;
+    else if (portid == 5)
+        pad_ctrl = (pad_ctrl_t *)&MISC->miscRGMII1PadCtrl;
+    else if (portid == 6)
+        pad_ctrl = (pad_ctrl_t *)&MISC->miscRGMII2PadCtrl;
+    else
+        return;
+
+    if (is_1p8v)
+    {
+        pad_ctrl->GMII_PAD_MODEHV = 0;
+        pad_ctrl->GMII_PAD_SEL_GMII = 0;
+        pad_ctrl->GMII_PAD_AMP_EN = 1;
+        pad_ctrl->GMII_PAD_IND = 0;
+        pad_ctrl->GMII_PAD_SEL = pad_sel;
+    }
+    else
+    {
+        pad_ctrl->GMII_PAD_MODEHV = 1;
+        pad_ctrl->GMII_PAD_SEL_GMII = 0;
+        pad_ctrl->GMII_PAD_AMP_EN = 0;
+        pad_ctrl->GMII_PAD_IND = 0;
+        pad_ctrl->GMII_PAD_SEL = pad_sel;
+    }
+}
+
+int lport_get_rgmii_cfg(uint32_t portid, lport_rgmii_cfg_s *rgmii_cfg)
+{
+    lport_rgmii_cntrl cntrl;
+    lport_rgmii_rx_clock_delay_cntrl rx_clock_delay_cntrl;
+    int rc;
+
+    if (portid < LPORT_FIRST_RGMII_PORT)
+    {
+        pr_err("LPORT RGMII port %d is not RGMII.Should be 4,5,6 only.\n", portid);
+        return LPORT_ERR_PARAM;
+    }
+
+    memcpy(rgmii_cfg, &local_lport_rgmii_cfg[portid-4], sizeof(lport_rgmii_cfg_s));
+
+    if ((rc = ag_drv_lport_rgmii_cntrl_get(portid-4, &cntrl)))
+        return rc;
+
+    if ((rc = ag_drv_lport_rgmii_rx_clock_delay_cntrl_get(portid-4, &rx_clock_delay_cntrl)))
+        return rc;
+
+    rgmii_cfg->eee_enable = cntrl.tx_clk_stop_en;
+    rgmii_cfg->rvmii_ref = cntrl.rvmii_ref_sel;
+    rgmii_cfg->delay_rx = rx_clock_delay_cntrl.bypass ? 0 : 1;
+    rgmii_cfg->delay_tx = cntrl.id_mode_dis ? 0: 1;
+    rgmii_cfg->portmode = cntrl.port_mode;
+    rgmii_cfg->is_1p8v = rgmii_port_pad_is_1p8v(portid);
+
+    return 0;
+}
+
+int lport_set_rgmii_cfg(uint32_t portid, lport_rgmii_cfg_s *rgmii_cfg)
+{
+    lport_rgmii_cntrl cntrl;
+    lport_rgmii_rx_clock_delay_cntrl rx_clock_delay_cntrl;
+    int rc;
+
+    if (portid < LPORT_FIRST_RGMII_PORT)
+    {
+        pr_err("LPORT RGMII port %d is not RGMII.Should be 4,5,6 only.\n", portid);
+        return LPORT_ERR_PARAM;
+    }
+
+    rgmii_port_pad_init(portid, rgmii_cfg->is_1p8v);
+
+    if ((rc = ag_drv_lport_rgmii_cntrl_get(portid-4, &cntrl)))
+        return rc;
+
+    if ((rc = ag_drv_lport_rgmii_rx_clock_delay_cntrl_get(portid-4, &rx_clock_delay_cntrl)))
+        return rc;
+
+    cntrl.tx_clk_stop_en = rgmii_cfg->eee_enable;
+    cntrl.rvmii_ref_sel = rgmii_cfg->rvmii_ref;
+    cntrl.id_mode_dis = rgmii_cfg->delay_tx ? 0 : 1;
+    cntrl.port_mode = rgmii_cfg->portmode;
+    cntrl.rgmii_mode_en = rgmii_cfg->valid;
+
+    rx_clock_delay_cntrl.iddq = 0;
+    rx_clock_delay_cntrl.bypass = rgmii_cfg->delay_rx ? 0 : 1;
+    rx_clock_delay_cntrl.dly_sel = 1;
+    rx_clock_delay_cntrl.dly_override = 1;
+    rx_clock_delay_cntrl.reset = 0;
+
+    if ((rc = ag_drv_lport_rgmii_cntrl_set(portid-4, &cntrl)))
+        return rc;
+
+    if ((rc = ag_drv_lport_rgmii_rx_clock_delay_cntrl_set(portid-4, &rx_clock_delay_cntrl)))
+        return rc;
+
+    memcpy(&local_lport_rgmii_cfg[portid-4],rgmii_cfg, sizeof(lport_rgmii_cfg_s));
+
+    return rc;
+}
+
+static int qgphy_init(lport_init_s *init_params)
+{
+    uint32_t i;
+    uint8_t ports_enabled = 0;
+    lport_ctrl_qegphy_cntrl qegphy_cntrl ;
+    lport_ctrl_qegphy_status qegphy_status;
+    uint8_t pll_refclk_sel, pll_sel_div5, pll_clk125_250_sel, phy_test_en;
+
+    /* To ensure minimum power consumption, the following steps should be
+     * applied to the GPHY control signals. This should be done immediately
+     * upon startup, before the decision is made to enable the GPHY or not,
+     * in order to cover all cases.
+     */
+
+    ag_drv_lport_ctrl_qegphy_cntrl_get(&qegphy_cntrl);
+    ag_drv_lport_ctrl_qegphy_test_cntrl_get(&pll_refclk_sel, &pll_sel_div5, &pll_clk125_250_sel, &phy_test_en);
+
+    /* Assert reset_n (active low) */
+    qegphy_cntrl.phy_reset = 1;
+    ag_drv_lport_ctrl_qegphy_cntrl_set(&qegphy_cntrl);
+    UDELAY(900);
+
+    /* Set GPHY's pll_clk125_250_sel to 250MHz */
+    ag_drv_lport_ctrl_qegphy_test_cntrl_set(pll_refclk_sel, pll_sel_div5, 1, phy_test_en);
+    UDELAY(900);
+
+    /* Deassert iddq_global_pwr and iddq_bias */
+    qegphy_cntrl.iddq_global_pwr = 0;
+    qegphy_cntrl.iddq_bias = 0;
+    ag_drv_lport_ctrl_qegphy_cntrl_set(&qegphy_cntrl);
+    UDELAY(900);
+
+    for (i = 0; i <= LPORT_LAST_EGPHY_PORT; i++)
+    {
+        if (init_params->prt_mux_sel[i] == PORT_GPHY)
+        {
+            ports_enabled |= (1 << i);
+        }
+    }
+
+    if (!ports_enabled)
+    {
+        /* Assert iddq_global_pwr and iddq_bias */
+        qegphy_cntrl.iddq_global_pwr = 1;
+        qegphy_cntrl.iddq_bias = 1;
+        ag_drv_lport_ctrl_qegphy_cntrl_set(&qegphy_cntrl);
+        UDELAY(900);
+
+        /* Deassert reset_n */
+        qegphy_cntrl.phy_reset = 0;
+        ag_drv_lport_ctrl_qegphy_cntrl_set(&qegphy_cntrl);
+        UDELAY(900);
+
+        ag_drv_lport_ctrl_qegphy_test_cntrl_set(pll_refclk_sel, pll_sel_div5, 0, phy_test_en);
+        UDELAY(900);
+
+        /* Assert reset_n (active low) */
+        qegphy_cntrl.phy_reset = 1;
+        ag_drv_lport_ctrl_qegphy_cntrl_set(&qegphy_cntrl);
+
+        pr_err("LPORT EGPHY not muxed, skipping init\n");
+        return LPORT_ERR_OK;
+    }
+
+    qegphy_cntrl.phy_phyad = base_addr;
+
+    qegphy_cntrl.ext_pwr_down = ~ports_enabled & 0x0f;
+    ag_drv_lport_ctrl_qegphy_cntrl_set(&qegphy_cntrl);
+    UDELAY(900);
+
+    ag_drv_lport_ctrl_qegphy_test_cntrl_set(pll_refclk_sel, pll_sel_div5, 0, phy_test_en);
+    UDELAY(900);
+
+    /* Deassert reset_n */
+    qegphy_cntrl.phy_reset = 0;
+    ag_drv_lport_ctrl_qegphy_cntrl_set(&qegphy_cntrl);
+    UDELAY(900);
+
+    /* Check for PLL Lock */
+    ag_drv_lport_ctrl_qegphy_status_get(&qegphy_status);
+
+    if (!qegphy_status.pll_lock)
+        pr_info("LPORT QEGPHY PLL is not Locked!");
+
+    return LPORT_ERR_OK;
+}
+
+uint16_t lport_qgphy_base_addr_get(void)
+{
+    return base_addr;
+}
+
+int lport_led_init(void *_leds_info)
+{
+    bca_leds_info_t *leds_info = (bca_leds_info_t *)_leds_info;
+    lport_led_link_and_speed_encoding_sel spdlnk_sel;
+    lport_led_link_and_speed_encoding spdlnk;
+    lport_ctrl_led_serial_cntrl led_serial_cntrl;
+    lport_led_cntrl led_ctrl;
+    uint8_t activity = 0;
+    uint32_t port = leds_info->port_id;
+    int i;
+    uint32_t led_link;
+    uint32_t led_activity;
+    uint16_t aggregate_en;
+    uint8_t lnk_pol, act_pol, act_sel;
+
+    if(port == 0xff)
+    {
+        /* No led data provided */
+        return 0;
+    }
+
+    ag_drv_lport_led_aggregate_led_cntrl_get(7, &lnk_pol, &act_pol, &act_sel, &aggregate_en);
+    ag_drv_lport_ctrl_led_serial_cntrl_get(&led_serial_cntrl);
+    lnk_pol = 1;
+    act_sel = 1;
+    act_pol = 0;
+
+    if (leds_info->activity[3] || leds_info->link[3])
+        led_serial_cntrl.smode |= 3;
+    else 
+        led_serial_cntrl.smode |= 2;
+
+    ag_drv_lport_led_link_and_speed_encoding_sel_get(port, &spdlnk_sel);
+    ag_drv_lport_led_cntrl_get(port, &led_ctrl);
+    ag_drv_lport_led_link_and_speed_encoding_get(port, &spdlnk);
+
+    led_serial_cntrl.port_en |= (1 << port);
+    if (!leds_info->skip_in_aggregate)
+        aggregate_en |= (1 << port);
+
+    spdlnk_sel.sel_10g_encode = 0;
+    spdlnk_sel.sel_1000m_encode = 0;
+    spdlnk_sel.sel_100m_encode = 0;
+    spdlnk_sel.sel_2500m_encode = 0;
+    spdlnk_sel.sel_10m_encode = 0;
+    spdlnk_sel.sel_no_link_encode = 0;
+
+    spdlnk.m10g_encode = 7;
+    spdlnk.m2500_encode = 7;
+    spdlnk.m1000_encode = 7;
+    spdlnk.m100_encode = 7;
+    spdlnk.m10_encode = 7;
+    spdlnk.no_link_encode = 7;
+
+    for (i = 0; i < 3; i++)
+    {
+        led_link = leds_info->link[i];
+        led_activity = leds_info->activity[i];
+
+        if (led_link & LED_SPEED_10G)
+            spdlnk.m10g_encode &= ~(1<<i);
+        if (led_link & LED_SPEED_2500)
+            spdlnk.m2500_encode &= ~(1<<i);
+        if (led_link & LED_SPEED_1G)
+            spdlnk.m1000_encode &= ~(1<<i);
+        if (led_link & LED_SPEED_100)
+            spdlnk.m100_encode &= ~(1<<i);
+        if (led_link & LED_SPEED_10)
+            spdlnk.m10_encode &= ~(1<<i);
+
+        if (led_activity & LED_SPEED_10G)
+            spdlnk_sel.sel_10g_encode |= (1<<i);
+        if (led_activity & LED_SPEED_2500)
+            spdlnk_sel.sel_2500m_encode |= (1<<i);
+        if (led_activity & LED_SPEED_1G)
+            spdlnk_sel.sel_1000m_encode |= (1<<i);
+        if (led_activity & LED_SPEED_100)
+            spdlnk_sel.sel_100m_encode |= (1<<i);
+        if (led_activity & LED_SPEED_10)
+            spdlnk_sel.sel_10m_encode |= (1<<i);
+
+        /* to configure the speed led to show activity only for specified
+           speeds */
+        if (led_activity && !(led_link & led_activity))
+            activity = 1;
+
+        switch (i)
+        {
+        case 0:
+            led_ctrl.spdlnk_led0_act_sel = activity;
+            break;
+        case 1:
+            led_ctrl.spdlnk_led1_act_sel = activity;
+            break;
+        case 2:
+            led_ctrl.spdlnk_led2_act_sel = activity;
+            break;
+        }
+    }
+
+    if (led_serial_cntrl.smode == 3)
+        led_ctrl.act_led_act_sel = leds_info->link[3] ? 0 : 1;
+
+    ag_drv_lport_led_link_and_speed_encoding_sel_set(port, &spdlnk_sel);
+    ag_drv_lport_led_cntrl_set(port, &led_ctrl);
+    ag_drv_lport_led_link_and_speed_encoding_set(port, &spdlnk);
+    ag_drv_lport_ctrl_led_serial_cntrl_set(&led_serial_cntrl);
+    ag_drv_lport_led_aggregate_led_cntrl_set(7, lnk_pol, act_pol, act_sel, aggregate_en);
+
+    return 0;
+}
+
+void lport_serdes_drv_register(void);
+
+int lport_init_driver(lport_init_s *init_params)
+{
+    static int init = 0;
+
+    if (validate_lport_configuration(init_params))
+    {
+        pr_err("LPORT configuration validation failed\n");
+        return LPORT_ERR_PARAM;
+    }
+
+    if (!init)
+    {
+#ifdef LPORT_INTERRUPTS
+        if (lport_intr_init())
+        {
+            pr_err("Init LPORT interrupts failed\n");
+            return LPORT_ERR_PARAM;
+        }
+        UDELAY(1000);
+        pr_err("INTR!\n");
+#endif
+
+        lport_serdes_drv_register();
+
+        if (lport_mdio_bus_init())
+        {
+            pr_err("Init LPORT interrupts failed\n");
+            return LPORT_ERR_PARAM;
+        }
+        UDELAY(1000);
+        pr_err("MDIO!\n");
+
+        init = 1;
+    }
+
+    if (qgphy_init(init_params))
+    {
+        pr_err("Init LPORT EGPHY failed\n");
+        return LPORT_ERR_PARAM;
+    }
+    UDELAY(1000);
+    pr_err("QEGPHY!\n");
+
+    if (xlmac_init(init_params))
+    {
+        pr_err("Init LPORT XLMAC failed\n");
+        return LPORT_ERR_PARAM;
+    }
+    UDELAY(1000);
+    pr_err("XLMAC!\n");
+
+    if (lport_mux_init(init_params))
+    {
+        pr_err("Init LPORT MUX failed\n");
+        return LPORT_ERR_PARAM;
+    }
+    UDELAY(1000);
+    pr_err("MUX!\n");
+
+    if (lport_serdes_init(init_params))
+    {
+        pr_err("Failed to initialize Merlin Serdes\n");
+#if !defined(__UBOOT__)
+        return LPORT_ERR_PARAM;
+#endif
+    }
+    UDELAY(1000);
+    pr_err("SERDES!\n");
+
+    if (msbus_init(init_params))
+    {
+        pr_err("Init LPORT MSBUS failed\n");
+        return LPORT_ERR_PARAM;
+    }
+    UDELAY(1000);
+    pr_err("MSBUS!\n");
+
+    if (rgmii_init(init_params))
+    {
+        pr_err("Init LPORT RGMII failed\n");
+        return LPORT_ERR_PARAM;
+    }
+    UDELAY(1000);
+    pr_err("RGMII!\n");
+
+    memcpy(&lport_init_cfg, init_params, sizeof(lport_init_cfg));
+    memcpy(&lport_curr_cfg, init_params, sizeof(lport_curr_cfg));
+
+    return LPORT_ERR_OK;
+}
+
+int lport_get_port_mux(uint32_t portid, LPORT_PORT_MUX_SELECT *prt_mux_sel)
+{
+    *prt_mux_sel = lport_curr_cfg.prt_mux_sel[portid];
+
+    return 0;
+}
+
+int lport_set_port_mux(uint32_t portid, LPORT_PORT_MUX_SELECT prt_mux_sel)
+{
+    lport_init_s init_params = lport_curr_cfg;
+
+    if (init_params.prt_mux_sel[portid] == prt_mux_sel)
+        return 0;
+
+    init_params.prt_mux_sel[portid] = prt_mux_sel;
+
+    if (validate_lport_configuration(&init_params))
+        return LPORT_ERR_PARAM;
+
+    if (lport_mux_init(&init_params))
+        return LPORT_ERR_PARAM;
+    UDELAY(1000);
+
+    if (lport_serdes_init(&init_params))
+#if !defined(__UBOOT__)
+        return LPORT_ERR_PARAM;
+#endif
+    UDELAY(1000);
+
+    lport_curr_cfg.prt_mux_sel[portid] = prt_mux_sel;
+
+    return LPORT_ERR_OK;
+}
+
+int lport_get_port_configuration(uint32_t portid, lport_port_cfg_s *port_conf)
+{
+    int rc;
+    lport_xlmac_ctrl xlmac_ctrl;
+    lport_xlmac_tx_ctrl xlmac_tx_ctrl;
+    lport_xlmac_rx_ctrl xlmac_rx_ctrl;
+
+    rc = ag_drv_lport_xlmac_ctrl_get(portid, &xlmac_ctrl);
+    rc = rc ? rc : ag_drv_lport_xlmac_tx_ctrl_get(portid, &xlmac_tx_ctrl);
+    rc = rc ? rc : ag_drv_lport_xlmac_rx_ctrl_get(portid, &xlmac_rx_ctrl);
+    port_conf->average_igp = xlmac_tx_ctrl.average_ipg;
+    port_conf->pad_en = xlmac_tx_ctrl.pad_en;
+    port_conf->local_loopback = xlmac_ctrl.local_lpbk;
+    port_conf->pad_threashold = xlmac_tx_ctrl.pad_threshold;
+    port_conf->tx_preamble_len = xlmac_tx_ctrl.tx_preamble_length;
+    port_conf->tx_threshold = xlmac_tx_ctrl.tx_threshold;
+    port_conf->throt_num = xlmac_tx_ctrl.throt_num;
+    port_conf->throt_denom = xlmac_tx_ctrl.throt_denom;
+    port_conf->speed = lport_speed_get((uint8_t)portid);
+
+    return rc;
+}
+
+int lport_set_port_configuration(uint32_t portid, lport_port_cfg_s *port_conf)
+{
+    int rc = 0;
+    lport_xlmac_ctrl xlmac_ctrl;
+    lport_xlmac_tx_ctrl xlmac_tx_ctrl;
+    lport_xlmac_rx_ctrl xlmac_rx_ctrl;
+    LPORT_PORT_MUX_SELECT curr_mux = lport_curr_cfg.prt_mux_sel[portid];
+    LPORT_PORT_MUX_SELECT init_mux = lport_init_cfg.prt_mux_sel[portid];
+
+    if (curr_mux == PORT_RGMII)
+    {
+        lport_port_status_s port_status = {};
+
+        port_status.port_up = port_conf->speed == LPORT_RATE_UNKNOWN ? 0 : 1;
+        port_status.rate = port_conf->speed;
+        port_status.duplex = 1;
+
+        rc = rc ? rc : lport_set_rgmii_ib_status(portid - LPORT_FIRST_RGMII_PORT, &port_status);
+    }
+
+    if (LPORT_IS_SERDES_PORT(init_mux))
+    {
+        LPORT_PORT_MUX_SELECT new_mux = curr_mux;
+
+        if (port_conf->speed == LPORT_RATE_UNKNOWN)
+#ifdef LPORT_SERDES_LINK_POWER_DOWN
+            new_mux = PORT_UNAVAIL;
+#endif
+        if (port_conf->speed == LPORT_RATE_100MB)
+            new_mux = PORT_SGMII;
+        if (port_conf->speed == LPORT_RATE_1000MB)
+            new_mux = PORT_SGMII;
+        if (port_conf->speed == LPORT_RATE_2500MB)
+            new_mux = PORT_HSGMII;
+        if (port_conf->speed == LPORT_RATE_10G)
+            new_mux = PORT_XFI;
+
+        rc = rc ? rc : lport_set_port_mux(portid, new_mux);
+#ifndef LPORT_SERDES_LINK_POWER_DOWN
+        if (port_conf->speed == LPORT_RATE_UNKNOWN)
+            return 0;
+#endif
+
+        if (port_conf->speed == LPORT_RATE_100MB)
+            rc = rc ? : lport_serdes_speed_set(portid, port_conf->speed);
+    }
+
+    if (port_conf->speed == LPORT_RATE_UNKNOWN)
+        port_conf->speed = LPORT_RATE_10MB;
+
+    rc = rc ? rc : ag_drv_lport_xlmac_ctrl_get(portid, &xlmac_ctrl);
+    rc = rc ? rc : ag_drv_lport_xlmac_tx_ctrl_get(portid, &xlmac_tx_ctrl);
+    rc = rc ? rc : ag_drv_lport_xlmac_rx_ctrl_get(portid, &xlmac_rx_ctrl);
+
+    xlmac_ctrl.local_lpbk = port_conf->local_loopback;
+    rc = rc ? rc : ag_drv_lport_xlmac_mode_set(portid, lport_speed_to_xlmac(port_conf->speed), 0, 0);
+
+    xlmac_tx_ctrl.average_ipg = port_conf->average_igp;
+    xlmac_tx_ctrl.pad_en = port_conf->pad_en;
+    xlmac_tx_ctrl.pad_threshold = port_conf->pad_threashold;
+    xlmac_tx_ctrl.tx_preamble_length = port_conf->tx_preamble_len;
+    xlmac_tx_ctrl.throt_num = port_conf->throt_num;
+    xlmac_tx_ctrl.throt_denom = port_conf->throt_denom;
+
+    rc = rc ? rc : ag_drv_lport_xlmac_ctrl_set(portid, &xlmac_ctrl);
+    rc = rc ? rc : ag_drv_lport_xlmac_tx_ctrl_set(portid, &xlmac_tx_ctrl);
+    rc = rc ? rc : ag_drv_lport_xlmac_rx_ctrl_set(portid, &xlmac_rx_ctrl);
+
+    return rc;
+}
+
+int lport_get_pause_configuration(uint32_t portid, lport_flow_ctrl_cfg_s *flow_ctrl)
+{
+    int rc;
+    lport_xlmac_rx_ctrl xlmac_rx_ctrl;
+    lport_xlmac_pause_ctrl pause_ctrl;
+
+    rc = ag_drv_lport_xlmac_rx_ctrl_get(portid, &xlmac_rx_ctrl);
+    rc = rc ? rc : ag_drv_lport_xlmac_tx_mac_sa_get(portid, &flow_ctrl->tx_ctrl_sa);
+    rc = rc ? rc : ag_drv_lport_xlmac_rx_mac_sa_get(portid, &flow_ctrl->rx_ctrl_sa);
+    rc = rc ? rc : ag_drv_lport_xlmac_pause_ctrl_get(portid, &pause_ctrl);
+
+    flow_ctrl->pause_refresh_en = pause_ctrl.pause_refresh_en;
+    flow_ctrl->pause_refresh_timer = pause_ctrl.pause_refresh_timer;
+    flow_ctrl->pause_xoff_timer = pause_ctrl.pause_xoff_timer;
+    flow_ctrl->rx_pass_ctrl = xlmac_rx_ctrl.rx_pass_ctrl;
+    flow_ctrl->rx_pass_pause = xlmac_rx_ctrl.rx_pass_pause;
+    flow_ctrl->rx_pause_en = pause_ctrl.rx_pause_en;
+    flow_ctrl->tx_pause_en = pause_ctrl.tx_pause_en;
+
+    return rc;
+}
+
+int lport_set_pause_configuration(uint32_t portid, lport_flow_ctrl_cfg_s *flow_ctrl)
+{
+    int rc;
+    lport_xlmac_rx_ctrl xlmac_rx_ctrl;
+    lport_xlmac_pause_ctrl pause_ctrl;
+
+    rc = ag_drv_lport_xlmac_rx_ctrl_get(portid, &xlmac_rx_ctrl);
+    rc = rc ? rc : ag_drv_lport_xlmac_tx_mac_sa_set(portid, flow_ctrl->tx_ctrl_sa);
+    rc = rc ? rc : ag_drv_lport_xlmac_rx_mac_sa_set(portid, flow_ctrl->rx_ctrl_sa);
+    rc = rc ? rc : ag_drv_lport_xlmac_pause_ctrl_get(portid, &pause_ctrl);
+
+    pause_ctrl.pause_refresh_en = flow_ctrl->pause_refresh_en;
+    pause_ctrl.pause_refresh_timer = flow_ctrl->pause_refresh_timer;
+    pause_ctrl.pause_xoff_timer = flow_ctrl->pause_xoff_timer;
+    xlmac_rx_ctrl.rx_pass_ctrl = flow_ctrl->rx_pass_ctrl;
+    xlmac_rx_ctrl.rx_pass_pause = flow_ctrl->rx_pass_pause;
+    pause_ctrl.rx_pause_en = flow_ctrl->rx_pause_en;
+    pause_ctrl.tx_pause_en = flow_ctrl->tx_pause_en;
+
+    rc = rc ? rc : ag_drv_lport_xlmac_rx_ctrl_set(portid, &xlmac_rx_ctrl);
+    rc = rc ? rc : ag_drv_lport_xlmac_pause_ctrl_set(portid, &pause_ctrl);
+
+    return rc;
+}
+
+static int lport_port_msbus_enable(uint32_t portid, uint8_t enable)
+{
+    uint8_t xlmac_id = portid < LPORT_NUM_OF_PORTS_PER_XLMAC ? 0 : 1;
+    uint8_t bit = portid < LPORT_NUM_OF_PORTS_PER_XLMAC ? portid : portid - LPORT_NUM_OF_PORTS_PER_XLMAC;
+    lport_mab_cntrl mab_cntrl;
+    int rc = LPORT_ERR_OK;
+
+    rc = rc ? rc : ag_drv_lport_mab_cntrl_get(xlmac_id, &mab_cntrl);
+
+    if (LPORT_IS_XFI_PORT(lport_curr_cfg.prt_mux_sel[portid]))
+    {
+        if (enable)
+        {
+            mab_cntrl.xgmii_rx_rst = 0;
+            mab_cntrl.xgmii_tx_rst = 0;
+        }
+        else
+        {
+            mab_cntrl.xgmii_rx_rst = 1;
+            mab_cntrl.xgmii_tx_rst = 1;
+        }
+    }
+    else
+    {
+        if (enable)
+        {
+            mab_cntrl.gmii_rx_rst &= ~(1 << bit);
+            mab_cntrl.gmii_tx_rst &= ~(1 << bit);
+        }
+        else
+        {
+            mab_cntrl.gmii_rx_rst |= (1 << bit);
+            mab_cntrl.gmii_tx_rst |= (1 << bit);
+        }
+    }
+
+    rc = rc ? rc : ag_drv_lport_mab_cntrl_set(xlmac_id, &mab_cntrl);
+
+    return rc;
+}
+
+static int lport_port_xlamc_enable(uint32_t portid, uint8_t enable)
+{
+    lport_xlmac_ctrl xlmac_ctrl;
+    int rc = LPORT_ERR_OK;
+
+    rc = rc ? rc : ag_drv_lport_xlmac_ctrl_get(portid, &xlmac_ctrl);
+    xlmac_ctrl.soft_reset = enable ? 0 : 1;
+    rc = rc ? rc : ag_drv_lport_xlmac_ctrl_set(portid, &xlmac_ctrl);
+
+    return rc;
+}
+
+typedef struct
+{
+    uint32_t if_enable; 
+    uint32_t read_credits; 
+    uint32_t set_credits; 
+    uint32_t out_ctrl; 
+    uint32_t urun_port_enable;
+    uint32_t tx_threshold;
+} xlif_tx_if;
+
+typedef struct
+{
+    uint32_t xlif_rx_if_channel[3];              // 0x00 - 0x0b
+    uint32_t xlif_rsvd_1[5];                     // 0x0c - 0x1f
+    uint32_t xlif_rx_flow_control_channel[2];    // 0x20 - 0x27
+    uint32_t xlif_rsvd_2[6];                     // 0x28 - 0x3f
+    xlif_tx_if xlif_tx_if_channel;               // 0x40 - 0x57
+    uint32_t xlif_rsvd_3[2];                     // 0x58 - 0x5f
+    uint32_t xlif_tx_flow_control_channel[2];    // 0x60 - 0x67
+    uint32_t xlif_rsvd_4[2];                     // 0x68 - 0x6f
+    uint32_t debug_bus_channel[1];               // 0x70 - 0x73
+    uint32_t xlif_rsvd_5[1];                     // 0x74 - 0x77
+    uint32_t xlif_eee_channel[1];                // 0x78 - 0x7b
+    uint32_t q_off_channel[1];                   // 0x7c - 0x7f
+    uint32_t xlif_rsvd_6[96];                    // 0x80 - 0x67f
+
+} xlif_ch;
+
+#define XLIF_REG ((volatile xlif_ch *)xlif_virt_base)
+
+static int lport_port_xlif_enable(uint32_t portid, uint8_t enable)
+{
+    int rc = LPORT_ERR_OK;
+
+    volatile xlif_ch *p_xlif_ch = XLIF_REG;
+
+    if (enable)
+        p_xlif_ch[portid].xlif_tx_if_channel.set_credits &= ~(1<<12);
+    else
+        p_xlif_ch[portid].xlif_tx_if_channel.set_credits = (1<<12);
+
+    return rc;
+}
+
+static int lport_port_enable(uint32_t portid, uint8_t enable)
+{
+    int rc = LPORT_ERR_OK;
+
+    if (enable)
+    {
+        rc = rc ? rc : lport_port_xlif_enable(portid, 1);
+        UDELAY(1000);
+        rc = rc ? rc : lport_port_xlamc_enable(portid, 1);
+        UDELAY(1000);
+        rc = rc ? rc : lport_port_msbus_enable(portid, 1);
+        UDELAY(1000);
+    }
+    else
+    {
+        rc = rc ? rc : lport_port_msbus_enable(portid, 0);
+        UDELAY(1000);
+        rc = rc ? rc : lport_port_xlamc_enable(portid, 0);
+        UDELAY(1000);
+        rc = rc ? rc : lport_port_xlif_enable(portid, 0);
+        UDELAY(1000);
+    }
+
+    return rc;
+}
+
+int lport_port_credits_restart(uint32_t portid)
+{
+    lport_xlmac_ctrl xlmac_ctrl;
+    int rc = LPORT_ERR_OK;
+
+    rc = rc ? rc : ag_drv_lport_xlmac_ctrl_get(portid, &xlmac_ctrl);
+    xlmac_ctrl.rx_en = 0;
+    xlmac_ctrl.tx_en = 0;
+    rc = rc ? rc : ag_drv_lport_xlmac_ctrl_set(portid, &xlmac_ctrl);
+
+    rc = rc ? rc : lport_port_enable(portid, 0);
+    rc = rc ? rc : lport_port_enable(portid, 1);
+
+    rc = rc ? rc : ag_drv_lport_xlmac_ctrl_get(portid, &xlmac_ctrl);
+    xlmac_ctrl.rx_en = 1;
+    xlmac_ctrl.tx_en = 1;
+    rc = rc ? rc : ag_drv_lport_xlmac_ctrl_set(portid, &xlmac_ctrl);
+
+    return rc;
+}
+
+int lport_get_port_rxtx_enable(uint32_t portid, uint8_t *rx_en, uint8_t *tx_en)
+{
+    int rc;
+    lport_xlmac_ctrl xlmac_ctrl;
+
+    rc = ag_drv_lport_xlmac_ctrl_get(portid, &xlmac_ctrl);
+
+    *rx_en = xlmac_ctrl.rx_en;
+    *tx_en = xlmac_ctrl.tx_en;
+
+    return rc;
+}
+
+int lport_set_port_rxtx_enable(uint32_t portid, uint8_t rx_en, uint8_t tx_en)
+{
+    int rc;
+    lport_xlmac_ctrl xlmac_ctrl;
+
+    rc = ag_drv_lport_xlmac_ctrl_get(portid, &xlmac_ctrl);
+
+    if (xlmac_ctrl.rx_en != rx_en && xlmac_ctrl.tx_en != tx_en)
+    {
+        if (rx_en && tx_en)
+            lport_port_enable(portid, 1);
+        else if (!rx_en && !tx_en)
+            lport_port_enable(portid, 0);
+    }
+
+    rc = rc ? rc : ag_drv_lport_xlmac_ctrl_get(portid, &xlmac_ctrl);
+
+    xlmac_ctrl.rx_en = rx_en;
+    xlmac_ctrl.tx_en = tx_en;
+
+    return rc ? rc : ag_drv_lport_xlmac_ctrl_set(portid, &xlmac_ctrl);
+}
+
+int  lport_get_phyid(uint32_t port, uint16_t *phyid)
+{
+    lport_ctrl_qegphy_cntrl qegphy_cntrl;
+    int rc = LPORT_ERR_OK;
+
+    if (lport_curr_cfg.prt_mux_sel[port] == PORT_UNAVAIL)
+    {
+        pr_err("%s(%d):LPORT failed to reset phy,Port %d is not configured\n"
+            ,__FUNCTION__, __LINE__, port);
+        return LPORT_ERR_STATE;
+    }
+
+    if (lport_curr_cfg.prt_mux_sel[port] == PORT_GPHY)
+    {
+        rc = ag_drv_lport_ctrl_qegphy_cntrl_get(&qegphy_cntrl);
+        *phyid = qegphy_cntrl.phy_phyad + port;
+    }
+    else if (lport_curr_cfg.prt_mux_sel[port] == PORT_RGMII)
+    {
+        if (local_lport_rgmii_cfg[port - LPORT_FIRST_RGMII_PORT].phy_attached)
+        {
+            *phyid = local_lport_rgmii_cfg[port - LPORT_FIRST_RGMII_PORT].phyid;
+        }
+        else
+        {
+            pr_err("%s(%d):LPORT No phy attached to RGMII port %d\n"
+                ,__FUNCTION__, __LINE__, port);
+            return LPORT_ERR_STATE;
+        }
+    }
+    return rc;
+}
+
+#define MII_AUXSTA  0x19	/* aux status register */
+
+/*This status analysis is for Broadcom's PHYs only as it described in the EGPHY register specification */
+int lport_get_brcm_phy_status(uint16_t phyid,lport_port_status_s *port_status)
+{
+    int rc;
+    uint16_t    regval = 0;
+    uint8_t     autoneg_hcd;
+
+    rc = lport_mdio22_rd(phyid, MII_AUXSTA, &regval);
+    if (rc)
+        return rc;
+
+    /*check if link is up*/
+    port_status->port_up = (regval & 0x4) ? 1: 0;
+
+    if (!port_status->port_up)
+    {
+        port_status->rate = LPORT_RATE_UNKNOWN;
+        port_status->duplex = 0;
+        return LPORT_ERR_OK;
+    }
+
+    port_status->autoneg_en = ( regval & 0x8000)?  1 : 0;
+
+    autoneg_hcd = (regval & 0x0700) >> 8;
+    switch (autoneg_hcd)
+    {
+    case 0x1:
+        port_status->duplex = LPORT_HALF_DUPLEX;
+        port_status->rate = LPORT_RATE_10MB;
+        break;
+    case 0x2:
+        port_status->duplex = LPORT_FULL_DUPLEX;
+        port_status->rate = LPORT_RATE_10MB;
+        break;
+    case 0x3:
+        port_status->duplex = LPORT_HALF_DUPLEX;
+        port_status->rate = LPORT_RATE_100MB;
+        break;
+    case 0x5:
+        port_status->duplex = LPORT_FULL_DUPLEX;
+        port_status->rate = LPORT_RATE_100MB;
+        break;
+    case 0x6:
+        port_status->duplex = LPORT_HALF_DUPLEX;
+        port_status->rate = LPORT_RATE_1000MB;
+        break;
+    case 0x7:
+        port_status->duplex = LPORT_FULL_DUPLEX;
+        port_status->rate = LPORT_RATE_1000MB;
+        break;
+    case 0x4:
+    default:
+        pr_err("%s(%d):LPORT phy autoneg bad status %d\n"
+            ,__FUNCTION__, __LINE__, autoneg_hcd);
+        port_status->port_up = 0;
+        return LPORT_ERR_STATE;
+    }
+    port_status->rx_pause_en = (regval & 0x1) ? 1 : 0;
+    port_status->tx_pause_en = (regval & 0x2) ? 1 : 0;
+
+    return rc;
+}
+
+int lport_set_rgmii_ib_status(uint32_t rgmii_id, lport_port_status_s *port_status)
+{
+    int rc;
+    uint8_t ib_status_ovrd;
+    uint8_t link_decode;
+    uint8_t duplex_decode;
+    uint8_t speed_decode;
+
+    ib_status_ovrd = 1;
+    link_decode = port_status->port_up;
+    duplex_decode = port_status->duplex == LPORT_FULL_DUPLEX ? 1 : 0;
+    speed_decode = port_status->rate == LPORT_RATE_10MB ? 0 : port_status->rate == LPORT_RATE_100MB ? 1 :
+        port_status->rate == LPORT_RATE_1000MB ? 2 : 3;
+
+    rc = ag_drv_lport_rgmii_ib_status_set(rgmii_id, ib_status_ovrd, link_decode,
+        duplex_decode, speed_decode);
+    return rc;
+}
+
+int lport_get_rgmii_ib_status(uint32_t rgmii_id, lport_port_status_s *port_status)
+{
+    int rc;
+    uint8_t ib_status_ovrd;
+    uint8_t link_decode;
+    uint8_t duplex_decode;
+    uint8_t speed_decode;
+    lport_rgmii_cntrl cntrl;
+
+    rc = ag_drv_lport_rgmii_ib_status_get(rgmii_id, &ib_status_ovrd, &link_decode,
+        &duplex_decode, &speed_decode);
+    if (link_decode)
+    {
+        port_status->port_up = 1;
+        port_status->duplex = duplex_decode ? LPORT_FULL_DUPLEX:LPORT_HALF_DUPLEX;
+        switch (speed_decode)
+        {
+        case 0:
+            port_status->rate = LPORT_RATE_10MB;
+            break;
+        case 1:
+            port_status->rate = LPORT_RATE_100MB;
+            break;
+        case 2:
+            port_status->rate = LPORT_RATE_1000MB;
+            break;
+        default:
+            port_status->rate = LPORT_RATE_UNKNOWN;
+            return LPORT_ERR_STATE;
+        }
+
+        rc = ag_drv_lport_rgmii_cntrl_get(rgmii_id, &cntrl);
+        port_status->rx_pause_en = cntrl.rx_pause_en;
+        port_status->tx_pause_en = cntrl.tx_pause_en;
+    }
+    else
+    {
+        port_status->port_up = 0;
+        port_status->rate = LPORT_RATE_UNKNOWN;
+    }
+
+    return rc;
+}
+
+int lport_get_port_status(uint32_t port, lport_port_status_s *port_status)
+{
+    int rc = LPORT_ERR_OK;
+    lport_ctrl_qegphy_status qegphy_status;
+    uint32_t    portstatus;
+    uint16_t    phyid;
+
+    switch (lport_curr_cfg.prt_mux_sel[port])
+    {
+    case PORT_UNAVAIL:
+        port_status->port_up = 0;
+        port_status->rate = LPORT_RATE_UNKNOWN;
+        port_status->duplex = 0;
+        break;
+
+    case PORT_GPHY:
+        /*first try to check for link status through the direct status register*/
+        rc = ag_drv_lport_ctrl_qegphy_status_get(&qegphy_status);
+        portstatus = qegphy_status.recovered_clk_lock & (1 << port);
+
+        /*only when link is up go further*/
+        if (rc || !portstatus)
+        {
+            port_status->port_up = 0;
+            port_status->rate = LPORT_RATE_UNKNOWN;
+            return rc;
+        }
+
+        rc = lport_get_phyid(port, &phyid);
+        rc = rc ? rc : lport_get_brcm_phy_status(phyid, port_status);
+        break;
+
+        /*in case of RGMII, check if IB status is enabled before trying to go to phy*/
+    case PORT_RGMII:
+        if (local_lport_rgmii_cfg[port-LPORT_FIRST_RGMII_PORT].valid)
+        {
+            if (local_lport_rgmii_cfg[port-LPORT_FIRST_RGMII_PORT].phy_attached &&
+                local_lport_rgmii_cfg[port-LPORT_FIRST_RGMII_PORT].ib_status_overide)
+            {
+                rc = lport_get_phyid(port, &phyid);
+                rc = rc ? rc : lport_get_brcm_phy_status(phyid, port_status);
+                if (rc)
+                {
+                    local_lport_rgmii_cfg[port-LPORT_FIRST_RGMII_PORT].phy_attached = 0;
+                    pr_err("Port %d: External PHY not attached\n", port);
+                }
+                rc = rc ? rc : lport_set_rgmii_ib_status(port - LPORT_FIRST_RGMII_PORT, port_status);
+            }
+            else
+            {
+                rc = lport_get_rgmii_ib_status(port - LPORT_FIRST_RGMII_PORT, port_status);
+            }
+        }
+        else
+        {
+            rc = LPORT_ERR_STATE;
+        }
+        break;
+
+    case PORT_SGMII ... PORT_XFI:
+        {
+            uint8_t msk = 0x2;
+            lport_srds_dual_serdes_0_status srds_0_status = {};
+            lport_srds_dual_serdes_1_status srds_1_status = {};
+            uint8_t port_stts = 0;
+
+            switch (port)
+            {
+            case 0:
+            case 7:
+                msk = 0x1;
+            case 1:
+            case 4:
+                rc = ag_drv_lport_srds_dual_serdes_0_status_get(&srds_0_status);
+                port_stts = (srds_0_status.link_status & msk) ? 1 : 0; 
+                break;
+            case 2:
+            case 5:
+                msk = 0x1;
+            case 3:
+            case 6:
+                rc = ag_drv_lport_srds_dual_serdes_1_status_get(&srds_1_status);
+                port_stts = (srds_1_status.link_status & msk) ? 1 : 0; 
+                break;
+            }
+
+            if (port_stts)
+                rc = lport_serdes_get_status(port, port_status);
+            else
+                port_status->port_up = port_stts;
+        }
+    }
+    return rc;
+}
+
+int lport_rgmii_ate_config(uint32_t port, lport_rgmii_ate_s *rgmii_ate_conf)
+{
+    int rc;
+    lport_rgmii_ate_tx_cntrl ate_tx_cntrl;
+    uint32_t rgmii_id = port - LPORT_FIRST_RGMII_PORT;
+
+    rc = ag_drv_lport_rgmii_ate_tx_cntrl_get(rgmii_id, &ate_tx_cntrl);
+    ate_tx_cntrl.payload_length = rgmii_ate_conf->payload_len;
+    rc = rc ? rc : ag_drv_lport_rgmii_ate_tx_cntrl_set(rgmii_id, &ate_tx_cntrl);
+
+    rc = rc ? rc : ag_drv_lport_rgmii_ate_tx_data_0_set(rgmii_id, rgmii_ate_conf->rgmii_da_mac[1],
+        rgmii_ate_conf->rgmii_da_mac[0]);
+    rc = rc ? rc : ag_drv_lport_rgmii_ate_tx_data_1_set(rgmii_id, rgmii_ate_conf->rgmii_da_mac[3],
+        rgmii_ate_conf->rgmii_da_mac[2]);
+    rc = rc ? rc : ag_drv_lport_rgmii_ate_tx_data_2_set(rgmii_id, 0x800,
+        rgmii_ate_conf->rgmii_da_mac[5], rgmii_ate_conf->rgmii_da_mac[4]);
+    return rc;
+}
+
+int lport_rgmii_ate_start(uint32_t port, uint32_t num_of_packets, uint8_t pkt_gen_en)
+{
+    int rc;
+    lport_rgmii_ate_tx_cntrl ate_tx_cntrl;
+    lport_rgmii_ate_rx_cntrl_exp_data ate_rx_cntrl_exp_data;
+    uint32_t rgmii_id = port - LPORT_FIRST_RGMII_PORT;
+
+    rc = ag_drv_lport_rgmii_ate_rx_cntrl_exp_data_get(rgmii_id, &ate_rx_cntrl_exp_data);
+    ate_rx_cntrl_exp_data.ate_en = 1;
+    rc = rc ? rc : ag_drv_lport_rgmii_ate_rx_cntrl_exp_data_get(rgmii_id, &ate_rx_cntrl_exp_data);
+    rc = rc ? rc : ag_drv_lport_rgmii_ate_tx_cntrl_get(rgmii_id, &ate_tx_cntrl);
+    ate_tx_cntrl.pkt_cnt = num_of_packets;
+    ate_tx_cntrl.pkt_gen_en = pkt_gen_en;
+    rc = rc ? rc : ag_drv_lport_rgmii_ate_tx_cntrl_set(rgmii_id, &ate_tx_cntrl);
+    return rc;
+}
+
+int lport_port_mtu_get(uint32_t portid, uint16_t *port_mtu)
+{
+    return ag_drv_lport_xlmac_rx_max_size_get(portid, port_mtu);
+}
+
+int lport_port_mtu_set(uint32_t portid, uint16_t port_mtu)
+{
+    uint8_t xlmacid = portid >> 2;
+    uint8_t instance = portid % 4;
+
+    /* set the XLMAC MTU */
+    ag_drv_lport_xlmac_rx_max_size_set(portid, 0x3fff);
+
+    /* align the MIB max packet size for accurate accounting */
+    switch (instance)
+    {
+    case 0:
+        return ag_drv_mib_conf_gport0_max_pkt_size_set(xlmacid, port_mtu);
+    case 1:
+        return ag_drv_mib_conf_gport1_max_pkt_size_set(xlmacid, port_mtu);
+    case 2:
+        return ag_drv_mib_conf_gport2_max_pkt_size_set(xlmacid, port_mtu);
+    case 3:
+        return ag_drv_mib_conf_gport3_max_pkt_size_set(xlmacid, port_mtu);
+    default:
+        pr_err("%s(%d):Wrong portid %d",__FUNCTION__, __LINE__, portid);
+        return LPORT_ERR_PARAM;
+    }
+}
+
+int lport_get_port_link_status(uint32_t port, uint8_t *link_up)
+{
+    lport_ctrl_qegphy_status qegphy_status;
+
+    switch (lport_curr_cfg.prt_mux_sel[port])
+    {
+    case PORT_GPHY:
+        ag_drv_lport_ctrl_qegphy_status_get(&qegphy_status);
+        *link_up = qegphy_status.recovered_clk_lock & (1 << port) ? 1 : 0;
+        break;
+    case PORT_RGMII:
+        {
+            uint8_t ib_status_ovrd;
+            uint8_t link_decode;
+            uint8_t duplex_decode;
+            uint8_t speed_decode;
+
+            ag_drv_lport_rgmii_ib_status_get(port - LPORT_FIRST_RGMII_PORT, &ib_status_ovrd, &link_decode,
+                &duplex_decode, &speed_decode);
+            *link_up = link_decode;
+            break;
+        }
+    case PORT_SGMII ... PORT_XFI:
+        break;
+    case PORT_UNAVAIL:
+        *link_up = 0;
+        break;
+    }
+
+    return LPORT_ERR_OK;
+}
+
+int lport_port_eee_set(uint32_t portid, uint8_t enable)
+{
+    int ret = 0;
+    uint8_t speed_mode, no_sop_for_crc_hg, hdr_mode;
+    uint16_t eee_ref_count = 0, eee_wake_timer = 0;
+    uint32_t eee_delay_entry_timer = 0;
+
+    if ((ret = ag_drv_lport_xlmac_eee_ctrl_set(portid, 0, enable)))
+        return ret;
+
+    /* Determine EEE timers only when EEE is enabled */
+    if (enable)
+    {
+        if ((ret = ag_drv_lport_xlmac_mode_get(portid, &speed_mode, &no_sop_for_crc_hg, &hdr_mode)))
+            return ret;
+
+        eee_ref_count = 0x280; /* 640 Mhz */
+
+        switch (speed_mode) {
+        case 1: /* 100Mbps */
+            {
+                eee_wake_timer = 0x1e; /* 30 uS */
+                eee_delay_entry_timer = 0x3c; /* 60 uS */
+                break;
+            }
+        case 2: /* 1000Mbps */
+            {
+                eee_wake_timer = 0x11; /* 17 uS */
+                eee_delay_entry_timer = 0x22; /* 34 uS */
+                break;
+            }
+        case 3: /* 2500Mbps */
+            {
+                eee_wake_timer = 0x20; /* 32 uS */
+                eee_delay_entry_timer = 0x320; /* 800 uS */
+                break;
+            }
+        case 4: /* 10000Mbps */
+            {
+                eee_wake_timer = 0x20; /* 32 uS */
+                eee_delay_entry_timer = 0xc8; /* 200 uS */
+                break;
+            }
+        default:
+            return -1;
+        }
+    }
+
+    if ((ret = ag_drv_lport_xlmac_eee_timers_set(portid, eee_ref_count, eee_wake_timer, eee_delay_entry_timer)))
+        return ret;
+
+    return 0;
+}
+
+char *lport_rate_to_str(LPORT_PORT_RATE rate)
+{
+    switch (rate)
+    {
+    case LPORT_RATE_10MB: return "10M";
+    case LPORT_RATE_100MB: return "100M";
+    case LPORT_RATE_1000MB: return "1G";
+    case LPORT_RATE_2500MB: return "2.5G";
+    case LPORT_RATE_10G: return "10G";
+    default: return "Unknown";
+    }
+    return "Unkown";
+}
+
+int lport_str_to_rate(char *str)
+{
+    if (!strcmp(str, "10M"))
+        return LPORT_RATE_10MB;
+    if (!strcmp(str, "100M"))
+        return LPORT_RATE_100MB;
+    if (!strcmp(str, "1G"))
+        return LPORT_RATE_1000MB;
+    if (!strcmp(str, "2.5G"))
+        return LPORT_RATE_2500MB;
+    if (!strcmp(str, "10G"))
+        return LPORT_RATE_10G;
+
+    return LPORT_RATE_UNKNOWN;
+}
+
+int lport_get_next_ts_from_fifo(uint8_t port_id, uint16_t *sequence_id, uint32_t *time_stamp)
+{
+    int rc;
+    uint8_t entry_count, ts_entry_valid;
+
+    ag_drv_lport_xlmac_tx_timestamp_fifo_status_get(port_id, &entry_count);
+
+    pr_debug("lport_get_next_ts_from_fifo: entry_count = %u\n", entry_count);
+
+    if (entry_count)
+    {
+        rc = ag_drv_lport_xlmac_tx_timestamp_fifo_data_get(port_id, &ts_entry_valid, sequence_id, time_stamp);
+
+        if (rc || !ts_entry_valid)
+        {
+            pr_err("failed to get TS. rc = %d, valid = %u\n", rc, ts_entry_valid);
+            return rc ? rc : LPORT_ERR_INVALID;
+        }
+    }
+    else
+        return LPORT_ERR_FIFO_EMPTY;
+
+    return LPORT_ERR_OK;
+}
+EXPORT_SYMBOL(lport_get_next_ts_from_fifo);
diff --git a/drivers/net/bcmbca/lport/lport_drv.h b/drivers/net/bcmbca/lport/lport_drv.h
new file mode 100644
index 0000000000..25d1fb02ff
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_drv.h
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+/*
+ * lport_drv.h
+ *
+ *  Created on: April 2015
+ *      Author: yonatani
+ */
+
+#ifndef SHARED_OPENSOURCE_DRV_LPORT_LPORT_DRV_H_
+#define SHARED_OPENSOURCE_DRV_LPORT_LPORT_DRV_H_
+
+//includes
+#include "lport_defs.h"
+
+//APIs
+int lport_init_driver(lport_init_s *init_params);
+int lport_get_port_mux(uint32_t portid, LPORT_PORT_MUX_SELECT *prt_mux_sel);
+int lport_set_port_mux(uint32_t portid, LPORT_PORT_MUX_SELECT prt_mux_sel);
+int lport_get_port_configuration(uint32_t portid, lport_port_cfg_s *port_conf);
+int lport_set_port_configuration(uint32_t portid, lport_port_cfg_s *port_conf);
+int lport_port_mtu_set(uint32_t portid, uint16_t port_mtu);
+int lport_port_mtu_get(uint32_t portid, uint16_t *port_mtu);
+LPORT_PORT_RATE lport_speed_get(uint8_t portid);
+int lport_get_pause_configuration(uint32_t portid, lport_flow_ctrl_cfg_s *flow_ctrl);
+int lport_set_pause_configuration(uint32_t portid, lport_flow_ctrl_cfg_s *flow_ctrl);
+int lport_set_port_rxtx_enable(uint32_t portid, uint8_t rx_en, uint8_t tx_en);
+int lport_get_port_rxtx_enable(uint32_t portid, uint8_t *rx_en, uint8_t *tx_en);
+int lport_port_credits_restart(uint32_t portid);
+int lport_get_rgmii_cfg(uint32_t portid, lport_rgmii_cfg_s *rgmii_cfg);
+int lport_set_rgmii_cfg(uint32_t portid, lport_rgmii_cfg_s *rgmii_cfg);
+int lport_get_port_status(uint32_t port, lport_port_status_s *port_status);
+int lport_get_port_link_status(uint32_t port, uint8_t *link_up);
+int lport_port_eee_set(uint32_t portid, uint8_t enable);
+int lport_rgmii_ate_config(uint32_t port, lport_rgmii_ate_s *rgmii_ate_conf);
+int lport_rgmii_ate_start(uint32_t port, uint32_t num_of_packets, uint8_t pkt_gen_en);
+int lport_get_brcm_phy_status(uint16_t phyid,lport_port_status_s *port_status);
+int lport_get_next_ts_from_fifo(uint8_t port_id, uint16_t *sequence_id, uint32_t *time_stamp);
+
+char *lport_rate_to_str(LPORT_PORT_RATE rate);
+int lport_str_to_rate(char *str);
+#endif /* SHARED_OPENSOURCE_DRV_LPORT_LPORT_DRV_H_ */
diff --git a/drivers/net/bcmbca/lport/lport_intr.c b/drivers/net/bcmbca/lport/lport_intr.c
new file mode 100644
index 0000000000..43b62b4292
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_intr.c
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+/*
+ * lport_intr.c
+ *
+ * LPORT interrupt layer
+ *
+ *  Created on: Dec 2015
+ *  Author: Kosta Sopov kosta@broadcom.com
+ */
+
+#include <linux/bitops.h>
+#include "bcm_intr.h"
+#include "ru.h"
+#include "bcm6858_lport_intr_ag.h"
+#include "6858_intr.h"
+#include "lport_defs.h"
+#include "lport_intr.h"
+
+#define ENTITY_ID_COUNT 7
+
+typedef struct _intr_handler_s intr_handler_s;
+
+typedef struct _intr_handler_s
+{
+    lport_intr_info_s info;
+    uint32_t register_num;
+    uint32_t mask;
+    int (*status_get_cb)(intr_handler_s *, uint32_t);
+    lport_intr_cb_t isr_cb;
+    void *isr_priv;
+} intr_handler_s;
+
+static int port_link_status_get(intr_handler_s *handler, uint32_t reg_val);
+
+intr_handler_s
+    mdio_done_h = { .info = {.intr_id = LPORT_MDIO_DONE}, .mask = LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_MASK},
+    mdio_error_h = { .info = {.intr_id = LPORT_MDIO_READ_ERROR}, .mask = LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_MASK};
+
+intr_handler_s
+    port0_link_h = { .info = {.intr_id = LPORT_PORT_LINK, .entity_id = 0}, .register_num = 1,
+        .mask = (1U << LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT) | (1U << LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT), 
+        .status_get_cb = port_link_status_get},
+    port1_link_h = { .info = {.intr_id = LPORT_PORT_LINK, .entity_id = 1}, .register_num = 1,
+        .mask = (1U << (LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 1)) | (1U << (LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 1)), 
+        .status_get_cb = port_link_status_get},
+    port2_link_h = { .info = {.intr_id = LPORT_PORT_LINK, .entity_id = 2}, .register_num = 1, 
+        .mask = (1U << (LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 2)) | (1U << (LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 2)), 
+        .status_get_cb = port_link_status_get},
+    port3_link_h = { .info = {.intr_id = LPORT_PORT_LINK, .entity_id = 3}, .register_num = 1, 
+        .mask = (1U << (LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 3)) | (1U << (LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 3)), 
+        .status_get_cb = port_link_status_get},
+    port4_link_h = { .info = {.intr_id = LPORT_PORT_LINK, .entity_id = 4}, .register_num = 1, 
+        .mask = (1U << (LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 4)) | (1U << (LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 4)), 
+        .status_get_cb = port_link_status_get},
+    port5_link_h = { .info = {.intr_id = LPORT_PORT_LINK, .entity_id = 5}, .register_num = 1,
+        .mask = (1U << (LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 5)) | (1U << (LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 5)), 
+        .status_get_cb = port_link_status_get},
+    port6_link_h = { .info = {.intr_id = LPORT_PORT_LINK, .entity_id = 6}, .register_num = 1, 
+        .mask = (1U << (LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 6)) | (1U << (LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 6)), 
+        .status_get_cb = port_link_status_get},
+    port0_remote_fault_h = { .info = {.intr_id = LPORT_REMOTE_FAULT, .entity_id = 0}, .register_num = 1, 
+        .mask = (1U << LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT)},
+    port4_remote_fault_h = { .info = {.intr_id = LPORT_REMOTE_FAULT, .entity_id = 1}, .register_num = 1, 
+        .mask = (1U << (LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT + 1))};
+
+intr_handler_s
+    tx_timesync_fifo_h = { .info = {.intr_id = LPORT_TIMESYNC_FIFO}, .mask = LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK};
+
+/* Interrupt info registry - 2 registers, 32 bits each */
+static intr_handler_s *bit_to_handler[2][32] = 
+{
+[0] = 
+   {
+       [LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_SHIFT] = &mdio_done_h,
+       [LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_SHIFT] = &mdio_error_h,
+       [LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT] = &tx_timesync_fifo_h,
+       [LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT+1] = &tx_timesync_fifo_h,
+       [LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT+2] = &tx_timesync_fifo_h,
+       [LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT+3] = &tx_timesync_fifo_h,
+       [LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT+4] = &tx_timesync_fifo_h,
+       [LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT+5] = &tx_timesync_fifo_h,
+       [LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT+6] = &tx_timesync_fifo_h,
+       [LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT+7] = &tx_timesync_fifo_h,
+
+   },
+[1] = 
+   {
+       [LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT] = &port0_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 1] = &port1_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 2] = &port2_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 3] = &port3_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 4] = &port4_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 5] = &port5_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT + 6] = &port6_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT] = &port0_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 1] = &port1_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 2] = &port2_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 3] = &port3_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 4] = &port4_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 5] = &port5_link_h,
+       [LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT + 6] = &port6_link_h,
+       [LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT] = &port0_remote_fault_h,
+       [LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT + 1] = &port4_remote_fault_h
+    }
+};
+
+static intr_handler_s *id_to_handler[LPORT_INTR_LAST][ENTITY_ID_COUNT] = 
+{
+    [LPORT_MDIO_DONE] = {&mdio_done_h},
+    [LPORT_MDIO_READ_ERROR] = {&mdio_error_h},
+    [LPORT_PORT_LINK] = {&port0_link_h, &port1_link_h, &port2_link_h, &port3_link_h, &port4_link_h, &port5_link_h, &port6_link_h},
+    [LPORT_REMOTE_FAULT] = {&port0_remote_fault_h, &port4_remote_fault_h},
+    [LPORT_TIMESYNC_FIFO] = {&tx_timesync_fifo_h}
+};
+
+#define INTR_DISABLE 0
+#define INTR_ENABLE 1
+
+static void intr0_mask_set(uint32_t mask);
+static void intr1_mask_set(uint32_t mask);
+static void intr0_mask_clear(uint32_t mask);
+static void intr1_mask_clear(uint32_t mask);
+
+void (*intr_enable_op[2][2])(uint32_t) = 
+{
+    {intr0_mask_set, intr0_mask_clear}, 
+    {intr1_mask_set, intr1_mask_clear}  
+};
+
+static int port_link_status_get(intr_handler_s *handler, uint32_t reg_val)
+{
+    if (reg_val & LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_MASK)
+        return 1;
+    return 0;
+}
+
+static void intr0_mask_set(uint32_t mask)
+{
+    RU_REG_WRITE(0, LPORT_INTR, 0_CPU_MASK_SET, mask);
+}
+
+static void intr1_mask_set(uint32_t mask)
+{
+    RU_REG_WRITE(0, LPORT_INTR, 1_CPU_MASK_SET, mask);
+}
+
+static void intr0_mask_clear(uint32_t mask)
+{
+    RU_REG_WRITE(0, LPORT_INTR, 0_CPU_MASK_CLEAR, mask);
+}
+
+static void intr1_mask_clear(uint32_t mask)
+{
+    RU_REG_WRITE(0, LPORT_INTR, 1_CPU_MASK_CLEAR, mask);
+}
+
+static int lport_isr(int irq, void *priv)
+{
+    uint32_t status_reg_val = 0, active_bit;
+    uint32_t register_num = (uint64_t)priv;
+    uint32_t mask;
+
+    if (register_num == 0)
+    {
+        RU_REG_READ(0, LPORT_INTR, 0_CPU_STATUS, status_reg_val);
+        RU_REG_READ(0, LPORT_INTR, 0_CPU_MASK_STATUS, mask);
+    }
+    else
+    {
+        RU_REG_READ(0, LPORT_INTR, 1_CPU_STATUS, status_reg_val);
+        RU_REG_READ(0, LPORT_INTR, 1_CPU_MASK_STATUS, mask);
+    }
+
+    while (status_reg_val)
+    {
+        intr_handler_s *handler;
+
+        active_bit = ffs(status_reg_val) - 1;
+        handler = bit_to_handler[register_num][active_bit];
+
+        if (!handler || !(status_reg_val & ~mask)) 
+            goto cont;
+
+        if (handler->status_get_cb)
+            handler->info.status = handler->status_get_cb(handler, status_reg_val);
+        else
+            handler->info.status = status_reg_val & handler->mask;
+
+        if (handler->isr_cb)
+            handler->isr_cb(&handler->info, handler->isr_priv);
+cont:
+        /* prepare status for next iteration */
+        status_reg_val &= handler ? ~(handler->mask) : ~(1U << active_bit);
+    }
+
+    return IRQ_HANDLED;
+}
+
+static void do_intr_clear(intr_handler_s *intr_handler)
+{ 
+    if (intr_handler->register_num == 0)
+        RU_REG_WRITE(0, LPORT_INTR, 0_CPU_CLEAR, intr_handler->mask);
+    else
+        RU_REG_WRITE(0, LPORT_INTR, 1_CPU_CLEAR, intr_handler->mask);
+}
+
+int lport_intr_init(void)
+{
+    uint32_t mask = 0xffffffff;
+    int res = 0;
+
+    RU_REG_WRITE(0, LPORT_INTR, 0_CPU_MASK_SET, mask);
+    RU_REG_WRITE(0, LPORT_INTR, 1_CPU_MASK_SET, mask);
+    if ((res = BcmHalMapInterrupt((FN_HANDLER)lport_isr, (void *)0, INTERRUPT_ID_LPORT_INTR_0_CPU_OUT)))
+        return res;
+    if ((res = BcmHalMapInterrupt((FN_HANDLER)lport_isr, (void *)1, INTERRUPT_ID_LPORT_INTR_1_CPU_OUT)))
+        return res;
+
+    return res;
+}
+
+int lport_intr_register(LPORT_INTR_ID intr_id, uint32_t entity_id, lport_intr_cb_t isr_cb, void *priv)
+{
+    intr_handler_s *intr_handler;
+
+    if (entity_id >= ENTITY_ID_COUNT || intr_id >= LPORT_INTR_LAST)
+        return LPORT_ERR_PARAM; /* wrong param */
+
+    intr_handler = id_to_handler[intr_id][entity_id];
+    if (intr_handler->isr_cb)
+        return LPORT_ERR_STATE; /* Already registered */
+
+    intr_handler->isr_cb = isr_cb;
+    intr_handler->isr_priv = priv;
+
+    return LPORT_ERR_OK;
+}
+EXPORT_SYMBOL(lport_intr_register);
+
+void lport_intr_unregister(LPORT_INTR_ID intr_id, uint32_t entity_id)
+{
+    intr_handler_s *intr_handler;
+
+    if (entity_id >= ENTITY_ID_COUNT || intr_id >= LPORT_INTR_LAST)
+        return;
+    intr_handler = id_to_handler[intr_id][entity_id];
+    if (!intr_handler)
+        return;
+
+    intr_enable_op[intr_handler->register_num][INTR_DISABLE](intr_handler->mask);
+    intr_handler->isr_cb = NULL;
+}
+
+void lport_intr_enable(LPORT_INTR_ID intr_id, uint32_t entity_id, int enable)
+{
+    intr_handler_s *intr_handler;
+
+    if (entity_id >= ENTITY_ID_COUNT || intr_id >= LPORT_INTR_LAST)
+        return;
+    intr_handler = id_to_handler[intr_id][entity_id];
+    if (!intr_handler)
+        return;
+
+    intr_enable_op[intr_handler->register_num][enable](intr_handler->mask);
+}
+EXPORT_SYMBOL(lport_intr_enable);
+
+void lport_intr_clear(LPORT_INTR_ID intr_id, uint32_t entity_id)
+{
+     intr_handler_s *intr_handler;
+
+    if (entity_id >= ENTITY_ID_COUNT || intr_id >= LPORT_INTR_LAST)
+        return;
+    intr_handler = id_to_handler[intr_id][entity_id];
+    if (!intr_handler)
+        return;
+
+    do_intr_clear(intr_handler);
+}
+EXPORT_SYMBOL(lport_intr_clear);
+
diff --git a/drivers/net/bcmbca/lport/lport_intr.h b/drivers/net/bcmbca/lport/lport_intr.h
new file mode 100644
index 0000000000..d6bf12bb18
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_intr.h
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+/*
+ *  lport_intr.h
+ *
+ *  LPORT interrupt layer
+ * 
+ *  Created on: Dec 2015
+ *  Author: Kosta Sopov kosta@broadcom.com
+ */
+
+#ifndef SHARED_OPENSOURCE_DRV_LPORT_LPORT_INT_H_
+#define SHARED_OPENSOURCE_DRV_LPORT_LPORT_INT_H_
+
+typedef enum 
+{
+    LPORT_MDIO_DONE,
+    LPORT_MDIO_READ_ERROR,
+    LPORT_PORT_LINK,
+    LPORT_REMOTE_FAULT,
+    LPORT_TIMESYNC_FIFO,
+    LPORT_INTR_LAST
+} LPORT_INTR_ID;
+
+typedef struct 
+{
+    int intr_id;
+
+    /* Entity Id:
+        PORT(0-7), SERDES(0-3), QGPHY(0-3) or XMLAC(0-1), 
+        depends on intr_id that was requested
+    */
+    uint32_t entity_id; 
+
+    /* Status: 
+        LPORT_PORT_LINK: 0 - link off, 1 - link on
+        LPORT_SERDER_SIGNAL: 0 - signal off, 1 - signal on
+        LPORT_QGPHY_ENERGY: 0 - no energy detected, 1 - energy detected
+        LPORT_XLMAC: event as described in XLMAC_INTR_STATUS in XLMAC spec
+        LPORT_UBUS_ERROR, LPORT_MDIO_DONE, LPORT_MDIO_READ_ERROR: ignore, always 0
+    */
+    int status;
+} lport_intr_info_s;
+
+typedef void(*lport_intr_cb_t)(const lport_intr_info_s *info, void *priv);
+
+int lport_intr_init(void);
+
+/* Note: interrupt must be enabled using lport_intr_enable in order to start getting interrupts */
+int lport_intr_register(LPORT_INTR_ID intr_id, uint32_t entity_id, lport_intr_cb_t cb, void *priv);
+
+void lport_intr_unregister(LPORT_INTR_ID intr_id, uint32_t entity_id);
+void lport_intr_enable(LPORT_INTR_ID intr_id, uint32_t entity_id, int enable);
+void lport_intr_clear(LPORT_INTR_ID intr_id, uint32_t entity_id);
+
+#define lport_mdio_intr_register(intr_id, cb, cb_priv) lport_intr_register(intr_id, 0, cb, cb_priv)
+#define lport_mdio_intr_unregister(intr_id) lport_intr_unregister(intr_id, 0)
+#define lport_mdio_intr_enable(intr_id,enable) lport_intr_enable(intr_id, 0, enable)
+#define lport_mdio_intr_clear(intr_id) lport_intr_clear(intr_id, 0)
+
+#endif
diff --git a/drivers/net/bcmbca/lport/lport_mdio.c b/drivers/net/bcmbca/lport/lport_mdio.c
new file mode 100644
index 0000000000..8716328fb0
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_mdio.c
@@ -0,0 +1,435 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+   
+   */
+/*
+ * lport_mdio.c
+ *
+ *  Created on: 24 Sep 2015
+ *      Author: yonatani
+ */
+
+#include "bcm6858_drivers_lport_ag.h"
+#include "lport_defs.h"
+#include "bcm6858_lport_mdio_ag.h"
+#include "lport_mdio.h"
+#include "lport_compat.h"
+
+typedef enum
+{
+    MDIO_CL45 = 0,
+    MDIO_CL22,
+} E_MDIO_CL_TYPE;
+
+typedef enum
+{
+    MDIO_CL45_ADDRESS =0,
+    MDIO_WRITE,
+    MDIO_CL45_RDINC,
+    MDIO_CL22_RD = MDIO_CL45_RDINC,
+    MDIO_CL45_RD,
+} E_MDIO_OPCODE;
+
+#define LPORT_ACCESS_MDIO_TRANSACTION_RETRY 1000
+#define LPORT_ACCESS_MDIO_TRANSACTION_TIMEOUT_MS 1000
+
+#if LPORT_MDIO_TRANS_LOCKED
+#include <linux/mutex.h>
+#define MDIO_CHECK_CNTX_LOCK do{ \
+    if(in_interrupt()) BUG(); \
+    mutex_lock(&mdio_mtx); \
+}while(0);
+
+#define MDIO_CNTX_UNLOCK mutex_unlock(&mdio_mtx)
+DEFINE_MUTEX(mdio_mtx);
+#else
+#define MDIO_CHECK_CNTX_LOCK
+#define MDIO_CNTX_UNLOCK
+#endif
+
+#if LPORT_MDIO_TRANS_INT
+DECLARE_COMPLETION(mdio_done);
+static uint32_t mdio_timeout;
+#endif
+
+#if LPORT_MDIO_TRANS_INT
+static void mdio_trans_done_isr(const lport_intr_info_s *info, void *priv)
+{
+    struct completion *mdio_done_isr = (struct completion *)priv;
+    lport_mdio_intr_enable(LPORT_MDIO_DONE,0);
+    lport_mdio_intr_clear(LPORT_MDIO_DONE);
+    complete(mdio_done_isr);
+}
+
+static uint32_t mdio_set_and_wait_polling(lport_mdio_control *control)
+{
+    int rc = LPORT_ERR_OK;
+    uint32_t retries = LPORT_ACCESS_MDIO_TRANSACTION_RETRY;
+
+    /* Poll for transaction end & not error */
+    do
+    {
+        UDELAY(10);
+        rc = ag_drv_lport_mdio_control_get(control);
+    } while ((!rc) && retries-- && control->start_busy && (!control->fail));
+
+    if (!retries)
+    {
+        pr_err( "%s(%d):LPORT MDIO write transaction passed too many retries rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, rc, control->fail, control->start_busy);
+        return LPORT_ERR_IO;
+    }
+    else if (control->fail || control->start_busy || rc)
+    {
+        pr_err( "%s(%d):LPORT MDIO write transaction failed or busy rc=%d,fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, rc, control->fail, control->start_busy);
+        return LPORT_ERR_IO;
+    }
+
+    return rc;
+}
+
+static uint32_t mdio_set_and_wait(lport_mdio_control *control)
+{
+    int rc = LPORT_ERR_OK;
+    int rv = 0;
+
+    reinit_completion(&mdio_done);
+
+    /* First Arm the mdio interrupt */
+    lport_mdio_intr_clear(LPORT_MDIO_DONE);
+    lport_mdio_intr_enable(LPORT_MDIO_DONE, 1);
+
+    ag_drv_lport_mdio_control_set(control);
+
+    rv = wait_for_completion_interruptible_timeout(&mdio_done, mdio_timeout);
+    if (rv == -ERESTARTSYS)
+    {
+        /* Try to wait again as polling on this time, Wake up by unexpected interrupt signal from kernel. */
+        pr_err("%s(%d):LPORT MDIO Received -ERESTARTSYS, Try to wait again as polling on this time, rc=%d\n",
+            __FUNCTION__, __LINE__, rc);
+
+        rc = mdio_set_and_wait_polling(control);
+        if (rc || control->fail || control->start_busy)
+        {
+            pr_err("%s(%d):LPORT MDIO interface is not ready rc=%d, fail=%d, busy=%d\n",
+                __FUNCTION__, __LINE__, rc, control->fail, control->start_busy);
+            rc =  LPORT_ERR_IO;
+        }
+        goto done;
+    }
+    else if (rv == 0)
+    {
+        rc =  LPORT_ERR_IO;
+        goto done;
+    }
+
+    rc = ag_drv_lport_mdio_control_get(control);
+    if (rc || control->fail || control->start_busy)
+    {
+        pr_err("%s(%d):LPORT MDIO interface is not ready rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, rc, control->fail, control->start_busy);
+        rc =  LPORT_ERR_IO;
+    }
+
+done:
+    return rc;
+}
+#else
+static uint32_t mdio_set_and_wait(lport_mdio_control *control)
+{
+    int rc = LPORT_ERR_OK;
+    uint32_t retries = LPORT_ACCESS_MDIO_TRANSACTION_RETRY;
+
+    rc = ag_drv_lport_mdio_control_set(control);
+    if (rc)
+    {
+        pr_err("%s(%d):LPORT MDIO interface is not ready, fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, control->fail, control->start_busy);
+        return LPORT_ERR_IO;
+
+    }
+
+    /* Poll for transaction end & not error */
+    do
+    {
+        UDELAY(10);
+        rc = ag_drv_lport_mdio_control_get(control);
+    }while ((!rc) && retries-- && control->start_busy && (!control->fail));
+
+    if (!retries)
+    {
+        pr_err(
+            "%s(%d):LPORT MDIO write transaction passed too many retries rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, rc, control->fail, control->start_busy);
+        return LPORT_ERR_IO;
+    }
+    else if (control->fail || control->start_busy || rc)
+    {
+        pr_err(
+            "%s(%d):LPORT MDIO write transaction failed or busy rc=%d,fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, rc, control->fail, control->start_busy);
+        return LPORT_ERR_IO;
+    }
+    return rc;
+}
+#endif
+
+int lport_mdio_bus_init(void)
+{
+    int rc = LPORT_ERR_OK;
+    uint8_t free_run_clk_enable;
+    uint8_t supress_preamble;
+    uint8_t mdio_clk_divider;
+    uint8_t mdio_clause;
+
+#if LPORT_MDIO_TRANS_LOCKED
+    mutex_init(&mdio_mtx);
+#endif
+#if LPORT_MDIO_TRANS_INT
+    init_completion(&mdio_done);
+    lport_mdio_intr_register(LPORT_MDIO_DONE,mdio_trans_done_isr, &mdio_done);
+    mdio_timeout = msecs_to_jiffies(LPORT_ACCESS_MDIO_TRANSACTION_TIMEOUT_MS);
+    pr_debug ("LPORT MDIO on Interrupt mode\n");
+#endif
+
+    rc = ag_drv_lport_mdio_cfg_get(&free_run_clk_enable,&supress_preamble,&mdio_clk_divider,&mdio_clause);
+    /*
+     * Reference clock (typically 250 MHz) is divided by 2x(mdio_clk_divider+1) to generate MDIO clock(MDC),
+     * For example: 0 = 125MHz, 9 = 12.5MHz,  12 = 9.6MHz, 63 = 1.95MHz, 127 = 0.98MHz, 255 = 0.49MHz
+     */
+    mdio_clk_divider = 12;
+    free_run_clk_enable = 1;
+    rc = rc ? rc: ag_drv_lport_mdio_cfg_set(free_run_clk_enable,supress_preamble,mdio_clk_divider,mdio_clause);
+
+    return rc;
+}
+
+int lport_mdio22_wr(uint16_t phyid,uint16_t addr, uint16_t data)
+{
+    uint8_t free_run_clk_enable;
+    uint8_t supress_preamble;
+    uint8_t mdio_clk_divider;
+    uint8_t mdio_clause;
+    lport_mdio_control control;
+    int rc = LPORT_ERR_OK;
+
+    MDIO_CHECK_CNTX_LOCK;
+
+    rc = ag_drv_lport_mdio_control_get(&control);
+    if (rc || control.start_busy)
+    {
+        pr_err("%s(%d):LPORT MDIO interface is not ready rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__,__LINE__, rc, control.fail, control.start_busy);
+        rc =  LPORT_ERR_IO;
+        goto done;
+    }
+    rc = ag_drv_lport_mdio_cfg_get(&free_run_clk_enable,&supress_preamble,&mdio_clk_divider,&mdio_clause);
+
+    mdio_clause = MDIO_CL22;
+
+    rc = rc ? rc: ag_drv_lport_mdio_cfg_set(free_run_clk_enable,supress_preamble,mdio_clk_divider,mdio_clause);
+
+    control.phy_prt_addr = phyid;
+    control.reg_dev_addr = addr;
+    control.data_addr = data;
+    control.start_busy = 1;
+    control.op_code =MDIO_WRITE;
+    control.fail = 0;
+
+    if ( mdio_set_and_wait(&control) )
+    {
+        pr_err("%s(%d):LPORT MDIO transaction failed rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__,__LINE__, rc, control.fail, control.start_busy);
+        rc =  LPORT_ERR_IO;
+        goto done;
+    }
+
+done:
+    MDIO_CNTX_UNLOCK;
+    return rc;
+}
+EXPORT_SYMBOL(lport_mdio22_wr);
+
+int lport_mdio22_rd(uint16_t phyid,uint16_t addr, uint16_t *data)
+{
+    uint8_t free_run_clk_enable;
+    uint8_t supress_preamble;
+    uint8_t mdio_clk_divider;
+    uint8_t mdio_clause;
+    lport_mdio_control control;
+    int rc = LPORT_ERR_OK;
+
+    MDIO_CHECK_CNTX_LOCK;
+    rc = ag_drv_lport_mdio_control_get(&control);
+    if(rc /* || control.fail */ || control.start_busy)
+    {
+        pr_err("%s(%d):LPORT MDIO interface is not ready rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__,__LINE__, rc, control.fail, control.start_busy);
+        rc =  LPORT_ERR_IO;
+        goto done;
+    }
+    rc = ag_drv_lport_mdio_cfg_get(&free_run_clk_enable,&supress_preamble,&mdio_clk_divider,&mdio_clause);
+
+    mdio_clause = MDIO_CL22;
+
+    rc = rc ? rc: ag_drv_lport_mdio_cfg_set(free_run_clk_enable,supress_preamble,mdio_clk_divider,mdio_clause);
+
+    control.phy_prt_addr = phyid;
+    control.reg_dev_addr = addr;
+    control.start_busy = 1;
+    control.op_code =MDIO_CL22_RD;
+    control.fail = 0;
+
+    if ( mdio_set_and_wait(&control) )
+    {
+        pr_err("%s(%d):LPORT MDIO transaction failed rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__,__LINE__, rc, control.fail, control.start_busy);
+        rc =  LPORT_ERR_IO;
+        goto done;
+    }
+
+    //read the result,mdio_set_and_wait also fetch the result
+    *data = control.data_addr;
+
+done:
+    MDIO_CNTX_UNLOCK;
+    return rc;
+}
+EXPORT_SYMBOL(lport_mdio22_rd);
+
+int lport_mdio45_rd(uint16_t phyid, uint16_t devid, uint16_t addr, uint16_t *data)
+{
+    uint8_t free_run_clk_enable;
+    uint8_t supress_preamble;
+    uint8_t mdio_clk_divider;
+    uint8_t mdio_clause;
+    lport_mdio_control control;
+    int rc = LPORT_ERR_OK;
+
+    MDIO_CHECK_CNTX_LOCK;
+    rc = ag_drv_lport_mdio_control_get(&control);
+    if (rc || control.start_busy)
+    {
+        pr_err(
+            "%s(%d):LPORT MDIO interface is not ready rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, rc, control.fail, control.start_busy);
+        rc = LPORT_ERR_IO;
+        goto done;
+    }
+    rc = ag_drv_lport_mdio_cfg_get(&free_run_clk_enable,&supress_preamble, &mdio_clk_divider,
+        &mdio_clause);
+
+    mdio_clause = MDIO_CL45;
+
+    rc = rc ?
+        rc :
+        ag_drv_lport_mdio_cfg_set(free_run_clk_enable,supress_preamble, mdio_clk_divider,
+            mdio_clause);
+
+    //write the CL45 address
+    control.phy_prt_addr = phyid;
+    control.reg_dev_addr = devid;
+    control.data_addr = addr;
+    control.start_busy = 1;
+    control.op_code = MDIO_CL45_ADDRESS;
+    control.fail = 0;
+
+    if (mdio_set_and_wait(&control))
+    {
+        pr_err(
+            "%s(%d):LPORT MDIO transaction failed rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, rc, control.fail, control.start_busy);
+        rc = LPORT_ERR_IO;
+        goto done;
+    }
+
+    //write the read request
+    control.start_busy = 1;
+    control.op_code = MDIO_CL45_RD;
+
+    if (mdio_set_and_wait(&control))
+    {
+        pr_err(
+            "%s(%d):LPORT MDIO transaction failed rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, rc, control.fail, control.start_busy);
+        rc = LPORT_ERR_IO;
+        goto done;
+    }
+
+    //read the result,mdio_set_and_wait also fetch the result
+    *data = control.data_addr;
+done:
+    MDIO_CNTX_UNLOCK;
+    return rc;
+}
+EXPORT_SYMBOL(lport_mdio45_rd);
+
+int lport_mdio45_wr(uint16_t phyid, uint16_t devid, uint16_t addr,
+    uint16_t data)
+{
+    uint8_t free_run_clk_enable;
+    uint8_t supress_preamble;
+    uint8_t mdio_clk_divider;
+    uint8_t mdio_clause;
+    lport_mdio_control control;
+    int rc = LPORT_ERR_OK;
+
+    MDIO_CHECK_CNTX_LOCK;
+    rc = ag_drv_lport_mdio_control_get(&control);
+    if (rc || control.start_busy)
+    {
+        pr_err( "%s(%d):LPORT MDIO interface is not ready rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, rc, control.fail, control.start_busy);
+        rc = LPORT_ERR_IO;
+        goto done;
+    }
+    rc = ag_drv_lport_mdio_cfg_get(&free_run_clk_enable,&supress_preamble, &mdio_clk_divider,
+        &mdio_clause);
+
+    mdio_clause = MDIO_CL45;
+
+    rc = rc ?
+        rc :
+        ag_drv_lport_mdio_cfg_set(free_run_clk_enable,supress_preamble, mdio_clk_divider,
+            mdio_clause);
+
+    //write the CL45 address
+    control.phy_prt_addr = phyid;
+    control.reg_dev_addr = devid;
+    control.data_addr = addr;
+    control.start_busy = 1;
+    control.op_code = MDIO_CL45_ADDRESS;
+    control.fail = 0;
+
+    if (mdio_set_and_wait(&control))
+    {
+        pr_err(
+            "%s(%d):LPORT MDIO transaction failed rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, rc, control.fail, control.start_busy);
+        rc = LPORT_ERR_IO;
+        goto done;
+    }
+
+    //write the read request
+    control.start_busy = 1;
+    control.op_code = MDIO_WRITE;
+    control.data_addr = data;
+
+    if (mdio_set_and_wait(&control))
+    {
+        pr_err(
+            "%s(%d):LPORT MDIO transaction failed rc=%d, fail=%d, busy=%d\n",
+            __FUNCTION__, __LINE__, rc, control.fail, control.start_busy);
+        rc = LPORT_ERR_IO;
+        goto done;
+    }
+
+done:
+    MDIO_CNTX_UNLOCK;
+    return rc;
+}
+EXPORT_SYMBOL(lport_mdio45_wr);
diff --git a/drivers/net/bcmbca/lport/lport_mdio.h b/drivers/net/bcmbca/lport/lport_mdio.h
new file mode 100644
index 0000000000..40057041d0
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_mdio.h
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+/*
+ * lport_mdio.h
+ *
+ *  Created on: April 2015
+ *      Author: yonatani
+ */
+
+#ifndef SHARED_OPENSOURCE_DRV_LPORT_LPORT_MDIO_H_
+#define SHARED_OPENSOURCE_DRV_LPORT_LPORT_MDIO_H_
+
+#define LPORT_MDIO_MODE_INTERRUPT 1
+#define LPORT_MDIO_MODE_POLLING   2
+#define LPORT_MDIO_TRANS_LOCK     1
+#define LPORT_MDIO_TRANS_NOLOCK   2
+
+
+#ifdef LPORT_INTERRUPTS
+#define LPORT_MDIO_MODE LPORT_MDIO_MODE_INTERRUPT
+#define LPORT_MDIO_TRANSACTION LPORT_MDIO_TRANS_LOCK
+#else
+#define LPORT_MDIO_MODE LPORT_MDIO_MODE_POLLING
+#define LPORT_MDIO_TRANSACTION LPORT_MDIO_TRANS_NOLOCK
+#endif
+
+#define LPORT_MDIO_TRANS_LOCKED (LPORT_MDIO_TRANSACTION == LPORT_MDIO_TRANS_LOCK)
+#define LPORT_MDIO_TRANS_INT     (LPORT_MDIO_MODE == LPORT_MDIO_MODE_INTERRUPT)
+
+int lport_mdio_bus_init(void);
+int lport_mdio22_wr(uint16_t phyid,uint16_t addr, uint16_t data);
+int lport_mdio22_rd(uint16_t phyid,uint16_t addr, uint16_t *data);
+int lport_mdio45_rd(uint16_t phyid, uint16_t devid, uint16_t addr, uint16_t *data);
+int lport_mdio45_wr(uint16_t phyid, uint16_t devid, uint16_t addr, uint16_t data);
+
+#endif /* SHARED_OPENSOURCE_DRV_LPORT_LPORT_MDIO_H_ */
diff --git a/drivers/net/bcmbca/lport/lport_print.h b/drivers/net/bcmbca/lport/lport_print.h
new file mode 100644
index 0000000000..26eb1c1578
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_print.h
@@ -0,0 +1,15 @@
+#ifndef _LPORT_PRINT_H_
+#define _LPORT_PRINT_H_
+
+#ifdef __UBOOT__
+#include <stdio.h>
+#define pr_err printf
+#define pr_info printf
+#define pr_debug(...)
+#define RU_PRINT(...) printf(__VA_ARGS__)
+#else
+#include <linux/printk.h>
+#define RU_PRINT(...) pr_info(__VA_ARGS__)
+#endif
+
+#endif
diff --git a/drivers/net/bcmbca/lport/lport_proc.c b/drivers/net/bcmbca/lport/lport_proc.c
new file mode 100644
index 0000000000..7ff34cbfb7
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_proc.c
@@ -0,0 +1,777 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+   
+   */
+/*
+ * lport_proc.c
+ *
+ *  Created on: Jan 2016
+ *  Author: Kosta Sopov kosta.sopov@broadcom.com
+ */
+
+#include <linux/kernel.h>
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+#include <linux/io.h>
+
+#include "proc_cmd.h"
+#include "lport_drv.h"
+#include "lport_stats.h"
+#include "lport_mdio.h"
+#include "serdes_access.h"
+
+#define PROC_DIR           "driver/lport"
+#define CMD_PROC_FILE      "cmd"
+#define SERDES_PROC_FILE   "serdes_cmd"
+
+#define LPORT_MAX_PHY_ID 31
+#define ANSI_COLOR_RED     "\x1b[31m"
+#define ANSI_COLOR_GREEN   "\x1b[32m"
+#define ANSI_COLOR_YELLOW  "\x1b[33m"
+#define ANSI_COLOR_BLUE    "\x1b[34m"
+#define ANSI_COLOR_MAGENTA "\x1b[35m"
+#define ANSI_COLOR_CYAN    "\x1b[36m"
+#define ANSI_COLOR_RESET   "\x1b[0m"
+
+static struct proc_dir_entry *proc_dir;
+static struct proc_dir_entry *cmd_proc_file;
+static struct proc_dir_entry *serdes_cmd_proc_file;
+
+static int lport_port_validate(int argc, char *argv[], const char *usage, int min, int max)
+{
+    int port;
+
+    if (argc < 2)
+        goto error;
+
+    if (kstrtos32(argv[1], 10, &port))
+        goto error;
+
+    if (port < min || port > max)
+        goto error;
+
+    return port;
+
+error:
+    pr_info("%s\n", usage);
+    return -1;
+}
+
+static int lport_proc_cmd_init(int argc, char *argv[])
+{
+    char *usage = "Usage: init <mux_map>\nMux map: String, 1 char for every port (S|I|U|L|M|H|X|G|R)\nZ-Unavailabe\n"
+        "S-SGMII\nI-SGMII_AN_IEEE_CL37\nU-SGMII_AN_USER_CL37\nL-SGMII_AN_SLAVE\nM-SGMII_AN_MASTER\n"
+        "H-HSGMII\nX-XFI\nG-GPHY\nR-RGMII\nExample: init GGGGXRRZ";
+    lport_init_s init_params;
+    int i, res;
+
+    if (argc < 2)
+    {
+        pr_info("%s\n", usage);
+        return 0;
+    }
+    if (strlen(argv[1]) != LPORT_NUM_OF_PORTS)
+    {
+        pr_err("Wrong params\n%s\n", usage);
+        return 0;
+    }
+
+    for (i = 0; i <  LPORT_NUM_OF_PORTS; i++)
+        switch (argv[1][i])
+        {
+        case 'S': init_params.prt_mux_sel[i] = PORT_SGMII; break;
+        case 'I': init_params.prt_mux_sel[i] = PORT_SGMII_AN_IEEE_CL37; break;
+        case 'U': init_params.prt_mux_sel[i] = PORT_SGMII_AN_USER_CL37; break;
+        case 'L': init_params.prt_mux_sel[i] = PORT_SGMII_AN_SLAVE; break;
+        case 'M': init_params.prt_mux_sel[i] = PORT_SGMII_AN_MASTER; break;
+        case 'H': init_params.prt_mux_sel[i] = PORT_HSGMII; break;
+        case 'X': init_params.prt_mux_sel[i] = PORT_XFI; break;
+        case 'G': init_params.prt_mux_sel[i] = PORT_GPHY; break;
+        case 'R': init_params.prt_mux_sel[i] = PORT_RGMII; break;
+        case 'Z': init_params.prt_mux_sel[i] = PORT_UNAVAIL; break;
+        default: 
+                  pr_err("Wrong map char \'%c\'\n%s\n", argv[1][i], usage);
+                  return 0;
+        }
+
+    if (!(res = lport_init_driver(&init_params)))
+        pr_info("lport init done\n");
+    else
+        pr_err("lport init failed; err %d\n", res);
+
+    return 0;
+}
+
+static int lport_proc_cmd_rxtx_enable(int argc, char *argv[])
+{
+    char *usage = "Usage: rxtx_enable <port id (0-6)> [<rx_enable 0|1> <tx_enable 0|1>]";
+    int port;
+    uint8_t rx_enable, tx_enable;
+
+    if ((port = lport_port_validate(argc, argv, usage, 0, 6)) == -1)
+        return 0;
+
+    if (argc == 2)
+    {
+        lport_get_port_rxtx_enable(port, &rx_enable, &tx_enable);
+        pr_info("Port %d: rx_enable %d, tx_enable %d\n", port, rx_enable, tx_enable);
+        return 0;
+    }
+    if (argc < 4)
+        goto error;
+
+    if (kstrtou8(argv[2], 10, &rx_enable) || kstrtou8(argv[3], 10, &tx_enable))
+        goto error;
+
+    lport_set_port_rxtx_enable(port, rx_enable, tx_enable);
+
+    return 0;
+
+error:
+    pr_info("Wrong params\n%s\n", usage);
+    return 0;
+}
+
+static int lport_proc_cmd_reset(int argc, char *argv[])
+{
+    char *usage = "Usage: reset <port id (0-6)>]";
+    int port;
+
+    if ((port = lport_port_validate(argc, argv, usage, 0, 6)) == -1)
+        return 0;
+
+    if (argc < 2)
+        goto error;
+
+    lport_port_credits_restart(port);
+
+    return 0;
+
+error:
+    pr_info("Wrong params\n%s\n", usage);
+    return 0;
+}
+
+static int lport_proc_cmd_rate(int argc, char *argv[])
+{
+    int port;
+    lport_port_cfg_s port_conf;
+    LPORT_PORT_RATE rate; 
+    char *lport_rate_usage = "Usage: rate <port id (0-6)> [10M|100M|1G|2.5G|10G]";
+
+    if ((port = lport_port_validate(argc, argv, lport_rate_usage, 0, 6)) == -1)
+        return 0;
+
+    lport_get_port_configuration(port, &port_conf);
+
+    if (argc == 2)
+    {
+        pr_info("Port %d rate: %s\n", port, lport_rate_to_str(port_conf.speed));
+        return 0;
+    }
+
+    if ((rate = lport_str_to_rate(argv[2])) == LPORT_RATE_UNKNOWN)
+    {
+        pr_info("Wrong param\n%s\n", lport_rate_usage);
+        return 0;
+    }
+
+    port_conf.speed = rate;
+    lport_set_port_configuration(port, &port_conf);
+
+    return 0;
+}
+
+static char *lport_duplex_to_str(LPORT_PORT_DUPLEX duplex)
+{
+    return duplex == LPORT_HALF_DUPLEX ? "Half duplex" : "Full duplex";
+}
+
+static int lport_proc_cmd_status(int argc, char *argv[])
+{
+    int port;
+    lport_port_status_s port_status = {};
+    char *lport_status_usage = "Usage: lport_status <port id (0-6)>";
+
+    if ((port = lport_port_validate(argc, argv, lport_status_usage, 0, 6)) == -1)
+        return -1;
+
+    lport_get_port_status(port, &port_status);
+    pr_info("Port %d status:\n", port);
+    pr_info("\tautoneg_en: %d\n", port_status.autoneg_en);
+    pr_info("\tport_up: %d\n", port_status.port_up);
+    pr_info("\trate: %s\n", lport_rate_to_str(port_status.rate));
+    pr_info("\tduplex: %s\n", lport_duplex_to_str(port_status.duplex));
+    pr_info("\trx_pause_en: %d\n", port_status.rx_pause_en);
+    pr_info("\ttx_pause_en: %d\n", port_status.tx_pause_en);
+
+    return 0;
+}
+
+static int lport_proc_cmd_stats(int argc, char *argv[])
+{
+    int port, clean = 0;
+    lport_rx_stats_s rx_stats;
+    lport_tx_stats_s tx_stats;
+    char *lport_stats_usage = "Usage: lport_stats <port id (0-6)> [\"clean\"]";
+
+    if ((port = lport_port_validate(argc, argv, lport_stats_usage, 0, 6)) == -1)
+        return -1;
+
+    if (argc >= 3)
+    {
+        if (strcmp(argv[2], "clean"))
+        {
+            pr_info("%s\n", lport_stats_usage);
+            return 0;
+        }
+        clean = 1;
+    }
+
+    lport_stats_get_rx(port, &rx_stats);
+    lport_stats_get_tx(port, &tx_stats);
+
+    pr_info("\x1b[33m\t\tLPORT %d Statistics %s\x1B[0m\n\x1b[0m", port,clean ? "Clear":"");
+    pr_info("+----------------+---------++----------------+---------+\n");
+    pr_info("| Counter        | Value   || Counter        | Value   |\n");
+    pr_info("+----------------+---------++----------------+---------+\n");
+    pr_info("| Rx Packet OK   |%9llu|| Tx Packet OK   |%9llu|\n", rx_stats.GRXPOK, tx_stats.GTXPOK);
+    pr_info("| Rx 64 Byte     |0x%07llx|| Tx 64 Byte     |0x%07llx|\n", rx_stats.GRX64, tx_stats.GTX64);
+    pr_info("| Rx 65 to 127   |%9llu|| Tx 65 to 127   |%9llu|\n", rx_stats.GRX127, tx_stats.GTX127);
+    pr_info("| Rx 128 to 255  |%9llu|| Tx 128 to 255  |%9llu|\n", rx_stats.GRX255, tx_stats.GTX255);
+    pr_info("| Rx 256 to 511  |%9llu|| Tx 256 to 511  |%9llu|\n", rx_stats.GRX511, tx_stats.GTX511);
+    pr_info("| Rx 512 to 1023 |%9llu|| Tx 512 to 1023 |%9llu|\n", rx_stats.GRX1023, tx_stats.GTX1023);
+    pr_info("| Rx 1024 to 1518|%9llu|| Tx 1024 to 1518|%9llu|\n", rx_stats.GRX1518, tx_stats.GTX1518);
+    pr_info("| Rx 1519 to 2047|%9llu|| Tx 1519 to 2047|%9llu|\n", rx_stats.GRX2047, tx_stats.GTX2047);
+    pr_info("| Rx frame       |%9llu|| Tx frame       |%9llu|\n", rx_stats.GRXPKT, tx_stats.GTXPKT);
+    pr_info("| Rx Bytes       |0x%07llx|| Tx Bytes       |0x%07llx|\n", rx_stats.GRXBYT, tx_stats.GTXBYT);
+    pr_info("| Rx Unicast     |%9llu|| Tx Unicast     |%9llu|\n", rx_stats.GRXUCA, tx_stats.GTXUCA);
+    pr_info("| Rx Multicast   |%9llu|| Tx Multicast   |%9llu|\n", rx_stats.GRXMCA, tx_stats.GTXUCA);
+    pr_info("| Rx Broadcast   |%9llu|| Tx Broadcast   |%9llu|\n", rx_stats.GRXBCA, tx_stats.GTXBCA);
+    pr_info("| Rx FCS Error   |%9llu|| Tx FCS Error   |%9llu|\n", rx_stats.GRXFCS, tx_stats.GTXFCS);
+    pr_info("| Rx Control     |%9llu|| Tx Control     |%9llu|\n", rx_stats.GRXCF, tx_stats.GTXCF);
+    pr_info("| Rx PAUSE       |%9llu|| Tx PAUSE       |%9llu|\n", rx_stats.GRXPF, tx_stats.GTXCF);
+    pr_info("| Rx PFC         |%9llu|| Tx PFC         |%9llu|\n", rx_stats.GRXPP, tx_stats.GTXPFC);
+    pr_info("| Rx Unsup Op    |%9llu|| Tx Oversized   |%9llu|\n", rx_stats.GRXUO, tx_stats.GTXOVR);
+    pr_info("| Rx Unsup DA    |%9llu||                |         |\n", rx_stats.GRXUDA);
+    pr_info("| Rx Wrong SA    |%9llu||                |         |\n", rx_stats.GRXWSA);
+    pr_info("| Rx Align Error |%9llu||                |         |\n", rx_stats.GRXALN);
+    pr_info("| Rx Length OOR  |%9llu||                |         |\n", rx_stats.GRXFLR);
+    pr_info("| Rx Code Error  |%9llu||                |         |\n", rx_stats.GRXFRERR);
+    pr_info("| Rx False Carri |%9llu||                |         |\n", rx_stats.GRXFCR);
+    pr_info("| Rx Oversized   |%9llu||                |         |\n", rx_stats.GRXOVR);
+    pr_info("| Rx Jabber      |%9llu||                |         |\n", rx_stats.GRXJBR);
+    pr_info("| Rx MTU ERR     |%9llu||                |         |\n", rx_stats.GRXMTUE);
+    pr_info("| Rx Truncated   |%9llu||                |         |\n", rx_stats.GRXTRFU);
+    pr_info("| Rx SCH CRC     |%9llu||                |         |\n", rx_stats.GRXSCHCRC);
+    pr_info("| Rx RUNT        |%9llu||                |         |\n", rx_stats.GRXRPKT);
+    pr_info("| Rx RUNT Bytes  |0x%07llx||                |         |\n", rx_stats.GRXRBYT);
+    pr_info("| Rx Undersize   |%9llu||                |         |\n", rx_stats.GRXUND);
+    pr_info("| Rx Fragment    |%9llu||                |         |\n", rx_stats.GRXFRG);
+    pr_info("+----------------+---------++----------------+---------+\n");
+
+    if (clean)
+        lport_stats_reset(port);
+
+    return 0;
+}
+
+static int lport_proc_cmd_phy_reg(int argc, char *argv[])
+{
+    char *lport_phy_usage = "Usage: phy_reg <phy_id (0-31)> <register (hex)> [value (hex)]";
+    int phyid, is_write_op = 0;
+    uint16_t reg, val;
+
+    if (argc < 3)
+        goto error;
+
+    if (kstrtos32(argv[1], 10, &phyid) || phyid < 0 || phyid > LPORT_MAX_PHY_ID)
+        goto error;
+
+    if (kstrtou16(argv[2], 16, &reg))
+        goto error;
+
+    if (argc > 3)
+    {
+        if (kstrtou16(argv[3], 16, &val))
+            goto error;
+
+        if (lport_mdio22_wr(phyid, reg, val))
+        {
+            pr_err("Failed to write register 0x%x\n", reg);
+            return 0;
+        }
+        is_write_op = 1;
+    }
+    if (lport_mdio22_rd(phyid, reg, &val))
+    {
+        pr_err("Failed to read register 0x%x\n", reg);
+        return -1;
+    }
+    pr_info("%s Phy Reg 0x%02x = 0x%04x\n", is_write_op ? "Write" : "Read", reg, val);
+    return 0;
+
+error:
+    pr_info("%s\n", lport_phy_usage);
+    return 0;
+}
+
+static int lport_proc_cmd_serdes_reg(int argc, char *argv[])
+{
+    char *lport_serdes_reg_usage = "Usage: serdes_reg <serdes id 0|1> <addr (hex)> [mask (hex)] [value (hex)]";
+    int serdes_id;
+    E_MERLIN_ID id;
+    uint16_t reg_addr, mask = 0, value;
+
+    if (argc < 3)
+        goto error;
+
+    if (kstrtos32(argv[1], 10, &serdes_id))
+        goto error;
+
+    switch (serdes_id)
+    {
+    case 0: id = MERLIN_ID_0; break;
+    case 1: id = MERLIN_ID_1; break;
+    default: goto error;
+    }
+
+    if (kstrtou16(argv[2], 16, &reg_addr))
+        goto error;
+
+    if (argc >= 4 && kstrtou16(argv[3], 16, &mask))
+        goto error;
+
+    if (argc < 5)
+    {
+        /* Register read was requested */
+        read_serdes_reg(id, reg_addr, mask, &value);
+        pr_info("0x%x\n", value);
+        return 0;
+    }
+
+    /* Register write was requested */
+    if (kstrtou16(argv[4], 16, &value))
+        goto error;
+
+    write_serdes_reg(id, reg_addr, mask, value);
+
+    return 0;
+
+error:
+    pr_info("%s\n", lport_serdes_reg_usage);
+    return -1;
+}
+
+static int lport_proc_cmd_serdes_tx_dis(int argc, char *argv[])
+{
+     char *serdes_tx_dis_usage = "Usage: serdes_tx_dis <port id (0-6)> <state 0|1>";
+     int port;
+     uint32_t  gpio_state = 0;
+
+     if ( argc != 3 )
+         goto error;
+
+     if ((port = lport_port_validate(argc, argv, serdes_tx_dis_usage, 0, 6)) == -1)
+         return 0;
+
+     if (kstrtos32(argv[2], 10, &gpio_state))
+         goto error;
+
+     if (gpio_state > 1)
+         goto error;
+
+     port_write_tx_dis_state(port, gpio_state); 
+
+     return 0;
+
+error:
+
+     pr_info("%s\n", serdes_tx_dis_usage);
+     return -1;
+}
+
+
+
+extern int lport_serdes_set_loopback(uint32_t port, uint32_t loopback_mode, uint32_t enable);
+extern int lport_serdes_diag(uint32_t port, uint32_t cmd);
+extern int lport_serdes_read_reg(uint32_t port, uint16_t device_type, uint16_t reg_address);
+extern int lport_serdes_write_reg(uint32_t port, uint16_t device_type, uint16_t reg_address, uint32_t value);
+
+static int serdes_proc_cmd_reg(int argc, char *argv[])
+{
+    char *serdes_proc_cmd_reg_usage = "Usage: reg <port_id (0-6)> <device type> <addr (hex)> [value (hex)]";
+    uint32_t port_id = 0xFFFFFFFF;
+    uint16_t dev_type = 0;
+    uint16_t addr = 0;
+    uint16_t value = 0;
+
+    if (argc < 4)
+        goto wrong_params;
+
+    if (kstrtou32(argv[1], 10, &port_id))
+        goto wrong_params;
+
+    if( port_id > 6)
+        goto wrong_params;
+
+    if (kstrtou16(argv[2], 10, &dev_type))
+        goto wrong_params;
+
+
+    if (kstrtou16(argv[3], 16, &addr))
+        goto wrong_params;
+
+    if (argc < 5)
+    {
+        /* read requested */
+        return lport_serdes_read_reg(port_id, dev_type, addr);
+    }
+
+    if (kstrtou16(argv[4], 16, &value))
+        goto wrong_params;
+
+    return lport_serdes_write_reg(port_id, dev_type, addr, value);
+
+wrong_params:
+    pr_info("%s\n", serdes_proc_cmd_reg_usage);
+    return -1;
+}
+
+static int serdes_proc_cmd_prbs_generation(int argc, char *argv[])
+{
+    char *wrong_params_msg = 
+        "Usage: prbs <port_id (0-6)> <pattern_type(0-7)[|PRBS7|PRBS9|PRBS11|PRBS15|PRBS23|PRBS31|PRBS58|8180|]>";
+      
+    uint32_t port_id = 0xffffffff;
+    uint32_t pattern_type = 0xffffffff;
+
+    if (argc < 3)
+        goto wrong_params;
+
+    if (kstrtou32(argv[1], 10, &port_id))
+        goto wrong_params;
+
+    if( port_id > 6)
+        goto wrong_params;
+
+
+    if (kstrtou32(argv[2], 10, &pattern_type))
+        goto wrong_params;
+
+    if( pattern_type >= SERDES_PRBS_PATTERN_TYPE_LAST)
+        goto wrong_params;
+
+    return lport_serdes_prbs_generation(port_id, pattern_type);
+
+wrong_params:
+    pr_info("portId[%d] pattern_type[%d]\n", port_id, pattern_type);
+    pr_info("%s\n", wrong_params_msg);
+    return -1;
+}
+
+
+static int serdes_proc_cmd_prbs_monitor(int argc, char *argv[])
+{
+    char *wrong_params_msg = 
+                "Usage: prbs <port_id (0-6)> <pattern_type(0-7)[|PRBS7|PRBS9|PRBS11|PRBS15|PRBS23|PRBS31|PRBS58|]>";
+      
+    uint32_t port_id = 0xffffffff;
+    uint32_t pattern_type = 0xffffffff;
+
+    if (argc < 3)
+        goto wrong_params;
+
+    if (kstrtou32(argv[1], 10, &port_id))
+        goto wrong_params;
+
+    if( port_id > 6)
+        goto wrong_params;
+
+    if (kstrtou32(argv[2], 10, &pattern_type))
+        goto wrong_params;
+
+    /* programable pattern not support in monitor mode */
+    if( pattern_type > SERDE_SPRBS_PATTERN_TYPE_PRBS58)
+        goto wrong_params;
+
+    return lport_serdes_prbs_monitor(port_id, pattern_type);
+
+
+wrong_params:
+    pr_info("portId[%d] pattern_type[%d]\n", port_id, pattern_type);
+    pr_info("%s\n", wrong_params_msg);
+    return -1;
+}
+
+static int serdes_proc_cmd_prbs_stat(int argc, char *argv[])
+{
+    char *serdes_proc_cmd_prbs_usage = "Usage: prbs <port_id (0-6)>";
+    uint32_t port_id;
+
+    if (argc < 2)
+        goto wrong_params;
+
+    if (kstrtou32(argv[1], 10, &port_id))
+        goto wrong_params;
+
+    if( port_id > 6)
+        goto wrong_params;
+
+    return lport_serdes_prbs_stats_get(port_id);
+
+wrong_params:
+    pr_info("%s\n", serdes_proc_cmd_prbs_usage);
+    return -1;
+}
+
+
+static int serdes_proc_cmd_stats(int argc, char *argv[])
+{
+    char *serdes_proc_cmd_stats_usage = "Usage: stats <port_id (0-6)>";
+    uint32_t port_id;
+
+    if (argc < 2)
+        goto wrong_params;
+
+    if (kstrtou32(argv[1], 10, &port_id))
+        goto wrong_params;
+
+    if( port_id > 6)
+        goto wrong_params;
+
+    return lport_serdes_diag(port_id, 2);
+
+wrong_params:
+    pr_info("%s\n", serdes_proc_cmd_stats_usage);
+    return -1;
+}
+
+static int serdes_proc_cmd_status(int argc, char *argv[])
+{
+    char *serdes_proc_cmd_status_usage = "Usage: status <port_id (0-6)>";
+    uint32_t port_id;
+
+    if (argc < 2)
+        goto wrong_params;
+
+    if (kstrtou32(argv[1], 10, &port_id))
+        goto wrong_params;
+
+    if( port_id > 6)
+        goto wrong_params;
+
+    return lport_serdes_diag(port_id, 1);
+
+wrong_params:
+    pr_info("%s\n", serdes_proc_cmd_status_usage);
+    return -1;
+}
+
+static int serdes_proc_cmd_loopback(int argc, char *argv[])
+{
+    char *serdes_proc_cmd_loopback_usage = "Usage: loopback <port_id (0-6)> <loopback mode (1-4)> <enable (0-1)>";
+    uint32_t port_id, mode, enable;
+
+    if (argc < 4)
+        goto wrong_params;
+
+    if (kstrtou32(argv[1], 10, &port_id))
+        goto wrong_params;
+
+    if( port_id > 6)
+        goto wrong_params;
+
+    if (kstrtou32(argv[2], 10, &mode))
+        goto wrong_params;
+
+    if( mode > 4 || mode == 0)
+        goto wrong_params;
+
+    if (kstrtou32(argv[3], 10, &enable))
+        goto wrong_params;
+
+    if( enable > 1)
+        goto wrong_params;
+
+    return lport_serdes_set_loopback(port_id, mode, enable);
+
+wrong_params:
+    pr_info("%s\n", serdes_proc_cmd_loopback_usage);
+    pr_info("Loopback modes: \n 1 - PCS Local loopback\n 2 - PCS Remote loopback\n"
+        " 3 - PMD Local Loopback\n 4 - PMD Remote Loopback\n");  
+    return -1;
+}
+
+static int serdes_proc_cmd_tx_cfg(int argc, char *argv[])
+{
+    uint32_t port_id;
+    merlin_tx_cfg_t tx_cfg;
+    char *serdes_proc_cmd_tx_cfg_usage = "Usage: txcfg <port (0-6)> [<pre (0-10)> <main (1-60)> <post1> <post2 (0-5)> <post2to1 (0-1)> <en_pre (0-1)> <en_post1 (0-1)> <en_post2 (0-1)> <tx_refcalshunt (0-15)> <hpf (0-15)]\n\
+    \n\
+    1. if post2 != 0: post1 (0-18), (pre + post1) <= 22\n\
+    2. if post2 == 0: post1 (0-23), (pre + post1) <= 27\n\
+    3. (pre + post1 + post2 + 1)    <= main\n\
+    4. (pre + main + post1 + post2) <= 60\n";
+
+    if (argc < 2)
+        goto wrong_params;
+    
+    if (kstrtou32(argv[1], 10, &port_id))
+        goto wrong_params;
+
+    if (port_id > 6)
+        goto wrong_params;
+    
+    if (argc == 2)
+    {
+        lport_serdes_get_tx_cfg(port_id, &tx_cfg);
+
+        pr_info("pre            %d\n", tx_cfg.pre);
+        pr_info("main           %d\n", tx_cfg.main);
+        pr_info("post1          %d\n", tx_cfg.post1);
+        pr_info("post2          %d\n", tx_cfg.post2);
+        pr_info("post2to1       %d\n", tx_cfg.post2to1);
+        pr_info("en_pre         %d\n", tx_cfg.en_pre);
+        pr_info("en_post1       %d\n", tx_cfg.en_post1);
+        pr_info("en_post2       %d\n", tx_cfg.en_post2);
+        pr_info("tx_refcalshunt %d\n", tx_cfg.tx_refcalshunt);
+        pr_info("hpf            %d\n", tx_cfg.hpf);
+
+        return 0;
+    }
+    else if (argc < 12)
+        goto wrong_params;
+
+    if (kstrtou16(argv[2], 10, &tx_cfg.pre))
+        goto wrong_params;
+
+    if (kstrtou16(argv[3], 10, &tx_cfg.main))
+        goto wrong_params;
+
+    if (kstrtou16(argv[4], 10, &tx_cfg.post1))
+        goto wrong_params;
+
+    if (kstrtou16(argv[5], 10, &tx_cfg.post2))
+        goto wrong_params;
+
+    if (kstrtou16(argv[6], 10, &tx_cfg.post2to1))
+        goto wrong_params;
+
+    if (kstrtou16(argv[7], 10, &tx_cfg.en_pre))
+        goto wrong_params;
+
+    if (kstrtou16(argv[8], 10, &tx_cfg.en_post1))
+        goto wrong_params;
+
+    if (kstrtou16(argv[9], 10, &tx_cfg.en_post2))
+        goto wrong_params;
+
+    if (kstrtou16(argv[10], 10, &tx_cfg.tx_refcalshunt))
+        goto wrong_params;
+
+    if (kstrtou16(argv[11], 10, &tx_cfg.hpf))
+        goto wrong_params;
+
+    return lport_serdes_set_tx_cfg(port_id, &tx_cfg);
+
+wrong_params:
+    pr_info("%s\n", serdes_proc_cmd_tx_cfg_usage);
+    return -1;
+}
+
+static struct proc_cmd_ops command_entries[] = {
+    { .name = "init", .do_command	= lport_proc_cmd_init},
+    {. name = "rxtx_enable", .do_command = lport_proc_cmd_rxtx_enable},
+    {. name = "reset", .do_command = lport_proc_cmd_reset},
+    { .name = "rate", .do_command	= lport_proc_cmd_rate},
+    { .name = "status", .do_command	= lport_proc_cmd_status},
+    { .name = "stats", .do_command	= lport_proc_cmd_stats},
+    { .name = "phy_reg", .do_command	= lport_proc_cmd_phy_reg},
+    { .name = "serdes_reg", .do_command	= lport_proc_cmd_serdes_reg},
+    { .name = "serdes_tx_dis", .do_command	= lport_proc_cmd_serdes_tx_dis},
+};
+
+static struct proc_cmd_table lport_command_table = {
+    .module_name = "LPORT",
+    .size = ARRAY_SIZE(command_entries),
+    .ops = command_entries
+};
+
+static struct proc_cmd_ops serdes_command_entries[] = {
+    { .name = "reg",        .do_command = serdes_proc_cmd_reg},
+    {. name = "prbs_gen",   .do_command = serdes_proc_cmd_prbs_generation},
+    {. name = "prbs_mon",   .do_command = serdes_proc_cmd_prbs_monitor},
+    {. name = "prbs_stat",  .do_command = serdes_proc_cmd_prbs_stat},
+    { .name = "stats",      .do_command = serdes_proc_cmd_stats},
+    { .name = "status",     .do_command = serdes_proc_cmd_status},
+    { .name = "loopback",   .do_command = serdes_proc_cmd_loopback},
+    { .name = "txcfg",      .do_command = serdes_proc_cmd_tx_cfg},
+};
+
+static struct proc_cmd_table serdes_command_table = {
+    .module_name = "SERDES",
+    .size = ARRAY_SIZE(serdes_command_entries),
+    .ops = serdes_command_entries
+};
+
+static void lport_proc_exit(void)
+{
+    if (serdes_cmd_proc_file) 
+    {
+        remove_proc_entry(SERDES_PROC_FILE, proc_dir);
+        serdes_cmd_proc_file = NULL;
+    }	
+
+    if (cmd_proc_file) 
+    {
+        remove_proc_entry(CMD_PROC_FILE, proc_dir);
+        cmd_proc_file = NULL;
+    }	
+    if (proc_dir)
+    {
+        remove_proc_entry(PROC_DIR, NULL);
+        proc_dir = NULL;
+    }	
+}
+
+int __init lport_proc_init(void)
+{
+    int status = 0;
+
+    proc_dir = proc_mkdir(PROC_DIR, NULL);
+    if (!proc_dir) 
+    {
+        pr_err("Failed to create PROC directory %s.\n",
+            PROC_DIR);
+        goto error;
+    }
+    cmd_proc_file = proc_create_cmd(CMD_PROC_FILE, proc_dir,
+        &lport_command_table);
+    if (!cmd_proc_file) 
+    {
+        pr_err("Failed to create %s\n", CMD_PROC_FILE);
+        goto error;
+    }
+
+    serdes_cmd_proc_file = proc_create_cmd(SERDES_PROC_FILE, proc_dir,
+                                                &serdes_command_table);
+    if (!serdes_cmd_proc_file) 
+    {
+        pr_err("Failed to create serdes %s\n", SERDES_PROC_FILE);
+        goto error;
+    }
+
+    return status;
+
+error:
+    if (proc_dir)
+        lport_proc_exit();
+
+    status = -EIO;
+    return status;
+}
+postcore_initcall(lport_proc_init);
diff --git a/drivers/net/bcmbca/lport/lport_stats.c b/drivers/net/bcmbca/lport/lport_stats.c
new file mode 100644
index 0000000000..fefc501891
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_stats.c
@@ -0,0 +1,376 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+   
+   */
+/*
+ * lport_stats.c
+ *
+ *  Created on: 16 áñôè× 2015
+ *      Author: yonatani
+ */
+#include "lport_defs.h"
+#include "lport_stats.h"
+#include "bcm6858_lport_mib_ag.h"
+#include "bcm6858_mib_conf_ag.h"
+
+
+int lport_stats_get_rx(uint32_t portid, lport_rx_stats_s *rx_stats)
+{
+    int rc;
+    rc = ag_drv_lport_mib_grx64_get(portid, &rx_stats->GRX64);
+    rc = rc ? rc :ag_drv_lport_mib_grx127_get(portid, &rx_stats->GRX127);
+    rc = rc ? rc :ag_drv_lport_mib_grx255_get(portid, &rx_stats->GRX255);
+    rc = rc ? rc :ag_drv_lport_mib_grx511_get(portid,&rx_stats->GRX511);
+    rc = rc ? rc :ag_drv_lport_mib_grx1023_get(portid,&rx_stats->GRX1023);
+    rc = rc ? rc :ag_drv_lport_mib_grx1518_get(portid,&rx_stats->GRX1518);
+    rc = rc ? rc :ag_drv_lport_mib_grx1522_get(portid,&rx_stats->GRX1522);
+    rc = rc ? rc :ag_drv_lport_mib_grx2047_get(portid,&rx_stats->GRX2047);
+    rc = rc ? rc :ag_drv_lport_mib_grx4095_get(portid,&rx_stats->GRX4095);
+    rc = rc ? rc :ag_drv_lport_mib_grx9216_get(portid,&rx_stats->GRX9216);
+    rc = rc ? rc :ag_drv_lport_mib_grx16383_get(portid,&rx_stats->GRX16383);
+    rc = rc ? rc :ag_drv_lport_mib_grxpkt_get(portid,&rx_stats->GRXPKT);
+    rc = rc ? rc :ag_drv_lport_mib_grxuca_get(portid,&rx_stats->GRXUCA);
+    rc = rc ? rc :ag_drv_lport_mib_grxmca_get(portid,&rx_stats->GRXMCA);
+    rc = rc ? rc :ag_drv_lport_mib_grxbca_get(portid,&rx_stats->GRXBCA);
+    rc = rc ? rc :ag_drv_lport_mib_grxfcs_get(portid,&rx_stats->GRXFCS);
+    rc = rc ? rc :ag_drv_lport_mib_grxcf_get(portid,&rx_stats->GRXCF);
+    rc = rc ? rc :ag_drv_lport_mib_grxpp_get(portid,&rx_stats->GRXPP);
+    rc = rc ? rc :ag_drv_lport_mib_grxpf_get(portid,&rx_stats->GRXPF);
+    rc = rc ? rc :ag_drv_lport_mib_grxuo_get(portid,&rx_stats->GRXUDA);
+    rc = rc ? rc :ag_drv_lport_mib_grxwsa_get(portid,&rx_stats->GRXWSA);
+    rc = rc ? rc :ag_drv_lport_mib_grxaln_get(portid,&rx_stats->GRXALN);
+    rc = rc ? rc :ag_drv_lport_mib_grxflr_get(portid,&rx_stats->GRXFLR);
+    rc = rc ? rc :ag_drv_lport_mib_grxfrerr_get(portid,&rx_stats->GRXFRERR);
+    rc = rc ? rc :ag_drv_lport_mib_grxfcr_get(portid,&rx_stats->GRXFCR);
+    rc = rc ? rc :ag_drv_lport_mib_grxovr_get(portid,&rx_stats->GRXOVR);
+    rc = rc ? rc :ag_drv_lport_mib_grxjbr_get(portid,&rx_stats->GRXJBR);
+    rc = rc ? rc :ag_drv_lport_mib_grxmtue_get(portid,&rx_stats->GRXMTUE);
+    rc = rc ? rc :ag_drv_lport_mib_grxmcrc_get(portid,&rx_stats->GRXMCRC);
+    rc = rc ? rc :ag_drv_lport_mib_grxprm_get(portid,&rx_stats->GRXPRM);
+    rc = rc ? rc :ag_drv_lport_mib_grxvln_get(portid,&rx_stats->GRXVLN);
+    rc = rc ? rc :ag_drv_lport_mib_grxdvln_get(portid,&rx_stats->GRXDVLN);
+    rc = rc ? rc :ag_drv_lport_mib_grxtrfu_get(portid,&rx_stats->GRXTRFU);
+    rc = rc ? rc :ag_drv_lport_mib_grxpok_get(portid,&rx_stats->GRXPOK);
+    rc = rc ? rc :ag_drv_lport_mib_grxschcrc_get(portid, &rx_stats->GRXSCHCRC);
+    rc = rc ? rc :ag_drv_lport_mib_grxbyt_get(portid,&rx_stats->GRXBYT);
+    rc = rc ? rc :ag_drv_lport_mib_grxrpkt_get(portid,&rx_stats->GRXRPKT);
+    rc = rc ? rc :ag_drv_lport_mib_grxund_get(portid,&rx_stats->GRXUND);
+    rc = rc ? rc :ag_drv_lport_mib_grxfrg_get(portid,&rx_stats->GRXFRG);
+    rc = rc ? rc :ag_drv_lport_mib_grxrbyt_get(portid,&rx_stats->GRXRBYT);
+    rc = rc ? rc :ag_drv_lport_mib_grxlpi_get(portid,&rx_stats->GRXLPI);
+    rc = rc ? rc :ag_drv_lport_mib_grxdlpi_get(portid,&rx_stats->GRXDLPI);
+    rc = rc ? rc :ag_drv_lport_mib_grxptllfc_get(portid,&rx_stats->GRXPTLLFC);
+    rc = rc ? rc :ag_drv_lport_mib_grxltllfc_get(portid,&rx_stats->GRXLTLLFC);
+    rc = rc ? rc :ag_drv_lport_mib_grxllfcfcs_get(portid,&rx_stats->GRXLLFCFCS);
+    rc = rc ? rc :ag_drv_lport_mib_grxuo_get(portid, &rx_stats->GRXUO);
+    return rc;
+}
+
+int lport_stats_get_tx(uint32_t portid, lport_tx_stats_s *tx_stats)
+{
+    int rc;
+    rc = ag_drv_lport_mib_gtx64_get(portid, &tx_stats->GTX64);
+    rc = rc ? rc :ag_drv_lport_mib_gtx127_get(portid, &tx_stats->GTX127);
+    rc = rc ? rc :ag_drv_lport_mib_gtx255_get(portid, &tx_stats->GTX255);
+    rc = rc ? rc :ag_drv_lport_mib_gtx511_get(portid, &tx_stats->GTX511);
+    rc = rc ? rc :ag_drv_lport_mib_gtx1023_get(portid, &tx_stats->GTX1023);
+    rc = rc ? rc :ag_drv_lport_mib_gtx1518_get(portid, &tx_stats->GTX1518);
+    rc = rc ? rc :ag_drv_lport_mib_gtx1522_get(portid, &tx_stats->GTX1522);
+    rc = rc ? rc :ag_drv_lport_mib_gtx2047_get(portid, &tx_stats->GTX2047);
+    rc = rc ? rc :ag_drv_lport_mib_gtx4095_get(portid, &tx_stats->GTX4095);
+    rc = rc ? rc :ag_drv_lport_mib_gtx9216_get(portid, &tx_stats->GTX9216);
+    rc = rc ? rc :ag_drv_lport_mib_gtx16383_get(portid, &tx_stats->GTX16383);
+    rc = rc ? rc :ag_drv_lport_mib_gtxpok_get(portid, &tx_stats->GTXPOK);
+    rc = rc ? rc :ag_drv_lport_mib_gtxpkt_get(portid, &tx_stats->GTXPKT);
+    rc = rc ? rc :ag_drv_lport_mib_gtxuca_get(portid, &tx_stats->GTXUCA);
+    rc = rc ? rc :ag_drv_lport_mib_gtxmca_get(portid, &tx_stats->GTXMCA);
+    rc = rc ? rc :ag_drv_lport_mib_gtxbca_get(portid, &tx_stats->GTXBCA);
+    rc = rc ? rc :ag_drv_lport_mib_gtxpf_get(portid, &tx_stats->GTXPF);
+    rc = rc ? rc :ag_drv_lport_mib_gtxpfc_get(portid, &tx_stats->GTXPFC);
+    rc = rc ? rc :ag_drv_lport_mib_gtxjbr_get(portid, &tx_stats->GTXJBR);
+    rc = rc ? rc :ag_drv_lport_mib_gtxfcs_get(portid, &tx_stats->GTXFCS);
+    rc = rc ? rc :ag_drv_lport_mib_gtxcf_get(portid, &tx_stats->GTXCF);
+    rc = rc ? rc :ag_drv_lport_mib_gtxovr_get(portid, &tx_stats->GTXOVR);
+    rc = rc ? rc :ag_drv_lport_mib_gtxdfr_get(portid, &tx_stats->GTXDFR);
+    rc = rc ? rc :ag_drv_lport_mib_gtxedf_get(portid, &tx_stats->GTXEDF);
+    rc = rc ? rc :ag_drv_lport_mib_gtxscl_get(portid, &tx_stats->GTXSCL);
+    rc = rc ? rc :ag_drv_lport_mib_gtxmcl_get(portid, &tx_stats->GTXMCL);
+    rc = rc ? rc :ag_drv_lport_mib_gtxlcl_get(portid, &tx_stats->GTXLCL);
+    rc = rc ? rc :ag_drv_lport_mib_gtxxcl_get(portid, &tx_stats->GTXXCL);
+    rc = rc ? rc :ag_drv_lport_mib_gtxfrg_get(portid, &tx_stats->GTXFRG);
+    rc = rc ? rc :ag_drv_lport_mib_gtxerr_get(portid, &tx_stats->GTXERR);
+    rc = rc ? rc :ag_drv_lport_mib_gtxvln_get(portid, &tx_stats->GTXVLN);
+    rc = rc ? rc :ag_drv_lport_mib_gtxdvln_get(portid, &tx_stats->GTXDVLN);
+    rc = rc ? rc :ag_drv_lport_mib_gtxrpkt_get(portid, &tx_stats->GTXRPKT);
+    rc = rc ? rc :ag_drv_lport_mib_gtxufl_get(portid, &tx_stats->GTXUFL);
+    rc = rc ? rc :ag_drv_lport_mib_gtxncl_get(portid, &tx_stats->GTXNCL);
+    rc = rc ? rc :ag_drv_lport_mib_gtxbyt_get(portid, &tx_stats->GTXBYT);
+    rc = rc ? rc :ag_drv_lport_mib_gtxlpi_get(portid, &tx_stats->GTXLPI);
+    rc = rc ? rc :ag_drv_lport_mib_gtxdlpi_get(portid, &tx_stats->GTXDLPI);
+    rc = rc ? rc :ag_drv_lport_mib_gtxltllfc_get(portid, &tx_stats->GTXLTLLFC);
+    return rc;
+}
+
+int lport_stats_rst_rx_single(uint32_t portid,  LPORT_STATS_RX_TYPE stat_type)
+{
+    switch(stat_type)
+    {
+    case (STAT_GRX64):
+        return ag_drv_lport_mib_gtx64_set(portid, 0);
+    case (STAT_GRX127):
+        return ag_drv_lport_mib_grx127_set(portid, 0);
+    case (STAT_GRX255):
+        return ag_drv_lport_mib_grx255_set(portid, 0);
+    case (STAT_GRX511):
+        return ag_drv_lport_mib_grx511_set(portid, 0);
+    case (STAT_GRX1023):
+        return ag_drv_lport_mib_grx1023_set(portid, 0);
+    case (STAT_GRX1518):
+        return ag_drv_lport_mib_grx1518_set(portid, 0);
+    case (STAT_GRX1522):
+        return ag_drv_lport_mib_grx1522_set(portid, 0);
+    case (STAT_GRX2047):
+        return ag_drv_lport_mib_grx2047_set(portid, 0);
+    case (STAT_GRX4095):
+        return ag_drv_lport_mib_grx4095_set(portid, 0);
+    case (STAT_GRX9216):
+        return ag_drv_lport_mib_grx9216_set(portid, 0);
+    case (STAT_GRX16383):
+        return ag_drv_lport_mib_grx16383_set(portid, 0);
+    case (STAT_GRXPKT):
+        return ag_drv_lport_mib_grxpkt_set(portid, 0);
+    case (STAT_GRXUCA):
+        return ag_drv_lport_mib_grxuca_set(portid, 0);
+    case (STAT_GRXMCA):
+        return ag_drv_lport_mib_grxmca_set(portid, 0);
+    case (STAT_GRXBCA):
+        return ag_drv_lport_mib_grxbca_set(portid, 0);
+    case (STAT_GRXFCS):
+        return ag_drv_lport_mib_grxfcs_set(portid, 0);
+    case (STAT_GRXCF):
+        return ag_drv_lport_mib_grxcf_set(portid, 0);
+    case (STAT_GRXPF):
+        return ag_drv_lport_mib_grxpp_set(portid, 0);
+    case (STAT_GRXPP):
+        return ag_drv_lport_mib_grxuo_set(portid, 0);
+    case (STAT_GRXUO):
+        return ag_drv_lport_mib_grxuda_set(portid, 0);
+    case (STAT_GRXUDA):
+        return ag_drv_lport_mib_grxwsa_set(portid, 0);
+    case (STAT_GRXWSA):
+        return ag_drv_lport_mib_grxaln_set(portid, 0);
+    case (STAT_GRXALN):
+        return ag_drv_lport_mib_grxflr_set(portid, 0);
+    case (STAT_GRXFLR):
+        return ag_drv_lport_mib_grxflr_set(portid, 0);
+    case (STAT_GRXFRERR):
+        return ag_drv_lport_mib_grxfrerr_set(portid, 0);
+    case (STAT_GRXFCR):
+        return ag_drv_lport_mib_grxfcr_set(portid, 0);
+    case (STAT_GRXOVR):
+        return ag_drv_lport_mib_grxovr_set(portid, 0);
+    case (STAT_GRXJBR):
+        return ag_drv_lport_mib_grxjbr_set(portid, 0);
+    case (STAT_GRXMTUE):
+        return ag_drv_lport_mib_grxmtue_set(portid, 0);
+    case (STAT_GRXMCRC):
+        return ag_drv_lport_mib_grxmcrc_set(portid, 0);
+    case (STAT_GRXPRM):
+        return ag_drv_lport_mib_grxprm_set(portid, 0);
+    case (STAT_GRXVLN):
+        return ag_drv_lport_mib_grxvln_set(portid, 0);
+    case (STAT_GRXDVLN):
+        return ag_drv_lport_mib_grxdvln_set(portid, 0);
+    case (STAT_GRXTRFU):
+        return ag_drv_lport_mib_grxtrfu_set(portid, 0);
+    case (STAT_GRXPOK):
+        return ag_drv_lport_mib_grxpok_set(portid, 0);
+    case (STAT_GRXSCHCRC):
+        return ag_drv_lport_mib_grxschcrc_set(portid, 0);
+    case (STAT_GRXBYT):
+        return ag_drv_lport_mib_grxbyt_set(portid, 0);
+    case (STAT_GRXRPKT):
+        return ag_drv_lport_mib_grxrpkt_set(portid, 0);
+    case (STAT_GRXUND):
+        return ag_drv_lport_mib_grxund_set(portid, 0);
+    case (STAT_GRXFRG):
+        return ag_drv_lport_mib_grxfrg_set(portid, 0);
+    case (STAT_GRXRBYT):
+        return ag_drv_lport_mib_grxrbyt_set(portid, 0);
+    case (STAT_GRXLPI):
+        return ag_drv_lport_mib_grxlpi_set(portid, 0);
+    case (STAT_GRXDLPI):
+        return ag_drv_lport_mib_grxdlpi_set(portid, 0);
+    case (STAT_GRXPTLLFC):
+        return ag_drv_lport_mib_grxptllfc_set(portid, 0);
+    case (STAT_GRXLTLLFC):
+        return ag_drv_lport_mib_grxltllfc_set(portid, 0);
+    case (STAT_GRXLLFCFCS):
+        return ag_drv_lport_mib_grxllfcfcs_set(portid, 0);
+    default:
+        return LPORT_ERR_PARAM;
+    }
+
+    return LPORT_ERR_OK;
+}
+
+int lport_stats_rst_tx_single(uint32_t portid,  LPORT_STATS_TX_TYPE stat_type)
+{
+    switch(stat_type)
+    {
+    case(STAT_GTX64):
+        return ag_drv_lport_mib_gtx64_set(portid, 0);
+    case(STAT_GTX127):
+        return ag_drv_lport_mib_gtx127_set(portid, 0);
+    case(STAT_GTX255):
+        return ag_drv_lport_mib_gtx255_set(portid, 0);
+    case(STAT_GTX511):
+        return ag_drv_lport_mib_gtx511_set(portid, 0);
+    case(STAT_GTX1023):
+        return ag_drv_lport_mib_gtx1023_set(portid, 0);
+    case(STAT_GTX1518):
+        return ag_drv_lport_mib_gtx1518_set(portid, 0);
+    case(STAT_GTX1522):
+        return ag_drv_lport_mib_gtx1522_set(portid, 0);
+    case(STAT_GTX2047):
+        return ag_drv_lport_mib_gtx2047_set(portid, 0);
+    case(STAT_GTX4095):
+        return ag_drv_lport_mib_gtx4095_set(portid, 0);
+    case(STAT_GTX9216):
+        return ag_drv_lport_mib_gtx9216_set(portid, 0);
+    case(STAT_GTX16383):
+        return ag_drv_lport_mib_gtx16383_set(portid, 0);
+    case(STAT_GTXPOK):
+        return ag_drv_lport_mib_gtxpok_set(portid, 0);
+    case(STAT_GTXPKT):
+        return ag_drv_lport_mib_gtxpkt_set(portid, 0);
+    case(STAT_GTXUCA):
+        return ag_drv_lport_mib_gtxuca_set(portid, 0);
+    case(STAT_GTXMCA):
+        return ag_drv_lport_mib_gtxmca_set(portid, 0);
+    case(STAT_GTXBCA):
+        return ag_drv_lport_mib_gtxbca_set(portid, 0);
+    case(STAT_GTXPF):
+        return ag_drv_lport_mib_gtxpf_set(portid, 0);
+    case(STAT_GTXPFC):
+        return ag_drv_lport_mib_gtxpfc_set(portid, 0);
+    case(STAT_GTXJBR):
+        return ag_drv_lport_mib_gtxjbr_set(portid, 0);
+    case(STAT_GTXFCS):
+        return ag_drv_lport_mib_gtxfcs_set(portid, 0);
+    case(STAT_GTXCF):
+        return ag_drv_lport_mib_gtxcf_set(portid, 0);
+    case(STAT_GTXOVR):
+        return ag_drv_lport_mib_gtxovr_set(portid, 0);
+    case(STAT_GTXDFR):
+        return ag_drv_lport_mib_gtxdfr_set(portid, 0);
+    case(STAT_GTXEDF):
+        return ag_drv_lport_mib_gtxedf_set(portid, 0);
+    case(STAT_GTXSCL):
+        return ag_drv_lport_mib_gtxscl_set(portid, 0);
+    case(STAT_GTXMCL):
+        return ag_drv_lport_mib_gtxmcl_set(portid, 0);
+    case(STAT_GTXLCL):
+        return ag_drv_lport_mib_gtxlcl_set(portid, 0);
+    case(STAT_GTXXCL):
+        return ag_drv_lport_mib_gtxxcl_set(portid, 0);
+    case(STAT_GTXFRG):
+        return ag_drv_lport_mib_gtxfrg_set(portid, 0);
+    case(STAT_GTXERR):
+        return ag_drv_lport_mib_gtxerr_set(portid, 0);
+    case(STAT_GTXVLN):
+        return ag_drv_lport_mib_gtxvln_set(portid, 0);
+    case(STAT_GTXDVLN):
+        return ag_drv_lport_mib_gtxdvln_set(portid, 0);
+    case(STAT_GTXRPKT):
+        return ag_drv_lport_mib_gtxrpkt_set(portid, 0);
+    case(STAT_GTXUFL):
+        return ag_drv_lport_mib_gtxufl_set(portid, 0);
+    case(STAT_GTXNCL):
+        return ag_drv_lport_mib_gtxncl_set(portid, 0);
+    case(STAT_GTXBYT):
+        return ag_drv_lport_mib_gtxbyt_set(portid, 0);
+    case(STAT_GTXLPI):
+        return ag_drv_lport_mib_gtxlpi_set(portid, 0);
+    case(STAT_GTXDLPI):
+        return ag_drv_lport_mib_gtxdlpi_set(portid, 0);
+    case(STAT_GTXLTLLFC):
+        return ag_drv_lport_mib_gtxltllfc_set(portid, 0);
+    default:
+        return LPORT_ERR_PARAM;
+    }
+    return LPORT_ERR_OK;
+}
+
+int lport_stats_cfg_set(uint32_t portid, lport_stats_cfg_s *stats_cfg)
+{
+    uint8_t xlmacid = portid >> 2;
+    uint8_t instance = portid % 4;
+    uint8_t eee_cnt_mode;
+    uint8_t saturate_en;
+    uint8_t cor_en;
+    uint8_t cnt_rst;
+
+    ag_drv_mib_conf_control_get(xlmacid, &eee_cnt_mode, &saturate_en,
+        &cor_en, &cnt_rst);
+
+    if(stats_cfg->saturate_en)
+        saturate_en |= (1 << instance);
+    else
+        saturate_en &= ~(1 << instance);
+
+    if(stats_cfg->cor_en)
+        cor_en |= (1 << instance);
+    else
+        cor_en &= ~(1 << instance);
+
+    return ag_drv_mib_conf_control_set(xlmacid, eee_cnt_mode, saturate_en,
+        cor_en, cnt_rst);
+}
+
+int lport_stats_cfg_get(uint32_t portid, lport_stats_cfg_s *stats_cfg)
+{
+    uint8_t xlmacid = portid >> 2;
+    uint8_t instance = portid % 4;
+    uint8_t eee_sym_mode;
+    uint8_t saturate_en;
+    uint8_t cor_en;
+    uint8_t cnt_rst;
+
+    ag_drv_mib_conf_control_get(xlmacid, &eee_sym_mode, &saturate_en,
+        &cor_en, &cnt_rst);
+
+    stats_cfg->saturate_en = (saturate_en & (1 << instance)) != 0;
+    stats_cfg->eee_sym_mode = (eee_sym_mode & (1 << instance)) != 0;
+    stats_cfg->cor_en =( cor_en & (1 << instance)) != 0;
+
+    return 0;
+}
+
+int lport_stats_reset(uint32_t portid)
+{
+    uint8_t xlmacid = portid >> 2;
+    uint8_t instance = portid % 4;
+    uint8_t eee_cnt_mode;
+    uint8_t saturate_en;
+    uint8_t cor_en;
+    uint8_t cnt_rst;
+
+    ag_drv_mib_conf_control_get(xlmacid, &eee_cnt_mode, &saturate_en,
+        &cor_en, &cnt_rst);
+
+    cnt_rst |= (1 << instance);
+
+    ag_drv_mib_conf_control_set(xlmacid, eee_cnt_mode, saturate_en,
+        cor_en, cnt_rst );
+
+    cnt_rst &= ~(1 << instance);
+
+    ag_drv_mib_conf_control_set(xlmacid, eee_cnt_mode, saturate_en,
+        cor_en, cnt_rst );
+
+    return 0;
+}
diff --git a/drivers/net/bcmbca/lport/lport_stats.h b/drivers/net/bcmbca/lport/lport_stats.h
new file mode 100644
index 0000000000..358958b6c5
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_stats.h
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+/*
+ * lport_stats.h
+ *
+ *  Created on: April 2015
+ *      Author: yonatani
+ */
+
+#ifndef SHARED_OPENSOURCE_DRV_LPORT_LPORT_STATS_H_
+#define SHARED_OPENSOURCE_DRV_LPORT_LPORT_STATS_H_
+
+#include "lport_types.h"
+
+typedef enum
+{
+    STAT_GRX64,   /*< Receive 64 Byte Frame Counter */
+    STAT_GRX127,  /*< Receive 65 to 127 Byte Frame Counter*/
+    STAT_GRX255,   /*< Receive 128 to 255 Byte Frame Counter*/
+    STAT_GRX511,   /*< Receive 256 to 511 Byte Frame Counter*/
+    STAT_GRX1023,  /*< Receive 512 to 1023 Byte Frame Counter*/
+    STAT_GRX1518,  /*< Receive 1024 to 1518 Byte Frame Counter*/
+    STAT_GRX1522,  /*< Receive 1519 to 1522 Byte Good VLAN Frame Counter*/
+    STAT_GRX2047,  /*< Receive 1519 to 2047 Byte Frame Counter*/
+    STAT_GRX4095,  /*< Receive 2048 to 4095 Byte Frame Counter*/
+    STAT_GRX9216,  /*< Receive 4096 to 9216 Byte Frame Counter*/
+    STAT_GRX16383, /*< Receive 9217 to 16838 Byte Frame Counter*/
+    STAT_GRXPKT,   /*< Receive frame/packet Counter*/
+    STAT_GRXUCA,   /*< Receive Unicast Frame Counter*/
+    STAT_GRXMCA,   /*< Receive Multicast Frame Counter*/
+    STAT_GRXBCA,   /*< Receive Broadcast Frame Counter*/
+    STAT_GRXFCS,   /*< Receive FCS Error Frame Counter*/
+    STAT_GRXCF,    /*< Receive Control Frame Counter*/
+    STAT_GRXPF,    /*< Receive PAUSE Frame Counter*/
+    STAT_GRXPP,    /*< Receive PFC (Per-Priority Pause) Frame Counter*/
+    STAT_GRXUO,    /*< Receive Unsupported Opcode Frame Counter*/
+    STAT_GRXUDA,   /*< Receive Unsupported DA for PAUSE/PFC Frame Counter*/
+    STAT_GRXWSA,   /*< Receive Wrong SA Frame Counter*/
+    STAT_GRXALN,   /*< Receive Alignment Error Frame Counter*/
+    STAT_GRXFLR,   /*< Receive Length Out of Range Frame Counter*/
+    STAT_GRXFRERR, /*< Receive Code Error Frame Counter*/
+    STAT_GRXFCR,   /*< Receive False Carrier Counter*/
+    STAT_GRXOVR,   /*< Receive Oversized Frame Counter*/
+    STAT_GRXJBR,   /*< Receive Jabber Frame Counter*/
+    STAT_GRXMTUE,  /*< Receive MTU Check Error Frame Counter*/
+    STAT_GRXMCRC,  /*< Matched CRC Frame Counter*/
+    STAT_GRXPRM,   /*< Receive Promiscuous Frame Counter*/
+    STAT_GRXVLN,   /*< Receive VLAN Tag Frame Counter*/
+    STAT_GRXDVLN,  /*< Receive Double VLAN Tag Frame Counter*/
+    STAT_GRXTRFU,  /*< Receive Truncated Frame Counter (due to RX FIFO full)*/
+    STAT_GRXPOK,   /*< Receive Good Packet Counter*/
+/*PFC are not in use in this platform */
+#if 0
+    RXPFCOFF0   /*< Receive PFC Frame Priority 0 XON to XOFF*/
+    RXPFCOFF1   /*< Receive PFC Frame Priority 1*/
+    RXPFCOFF2   /*< Receive PFC Frame Priority 2*/
+    RXPFCOFF3   /*< Receive PFC Frame Priority 3*/
+    RXPFCOFF4   /*< Receive PFC Frame Priority 4*/
+    RXPFCOFF5   /*< Receive PFC Frame Priority 5*/
+    RXPFCOFF6   /*< Receive PFC Frame Priority 6*/
+    RXPFCOFF7   /*< Receive PFC Frame Priority 7*/
+    RXPFCP0     /*< Receive PFC Frame Priority 0*/
+    RXPFCP1     /*< Receive PFC Frame Priority 1*/
+    RXPFCP2     /*< Receive PFC Frame Priority 2*/
+    RXPFCP3     /*< Receive PFC Frame Priority 3*/
+    RXPFCP4     /*< Receive PFC Frame Priority 4*/
+    RXPFCP5     /*< Receive PFC Frame Priority 5*/
+    RXPFCP6     /*< Receive PFC Frame Priority 6*/
+    RXPFCP7     /*< Receive PFC Frame Priority 7*/
+#endif
+    STAT_GRXSCHCRC,    /*< Receive SCH CRC Error*/
+    STAT_GRXBYT,   /*< Receive Byte Counter*/
+    STAT_GRXRPKT,  /*< Receive RUNT Frame Counter*/
+    STAT_GRXUND,   /*< Receive Undersize Frame Counter*/
+    STAT_GRXFRG,   /*< Receive Fragment Counter*/
+    STAT_GRXRBYT,  /*< Receive Runt Byte Counter*/
+    STAT_GRXLPI,   /*< RX EEE LPI Event Counter*/
+    STAT_GRXDLPI,  /*< RX EEE LPI Duration Counte*/
+    STAT_GRXPTLLFC,    /*< Receive Physical Type LLFC message counter*/
+    STAT_GRXLTLLFC,   /*< Receive Logical Type LLFC message Counter*/
+    STAT_GRXLLFCFCS   /*< Receive Type LLFC message with CRC error Counter*/
+}LPORT_STATS_RX_TYPE;
+
+typedef enum
+{
+    STAT_GTX64,    /*< Transmit 64 Byte Frame Counter*/
+    STAT_GTX127,   /*< Transmit 65 to 127 Byte Frame Counter*/
+    STAT_GTX255,   /*< Transmit 128 to 255 Byte Frame Counter*/
+    STAT_GTX511,   /*< Transmit 256 to 511 Byte Frame Counter*/
+    STAT_GTX1023,  /*< Transmit 512 to 1023 Byte Frame Counter*/
+    STAT_GTX1518,  /*< Transmit 1024 to 1518 Byte Frame Counter*/
+    STAT_GTX1522,  /*< Transmit 1519 to 1522 Byte Good VLAN Frame Counter*/
+    STAT_GTX2047,  /*< Transmit 1519 to 2047 Byte Frame Counter*/
+    STAT_GTX4095,  /*< Transmit 2048 to 4095 Byte Frame Counter*/
+    STAT_GTX9216,  /*< Transmit 4096 to 9216 Byte Frame Counter*/
+    STAT_GTX16383, /*< Transmit 9217 to 16383 Byte Frame Counter*/
+    STAT_GTXPOK,   /*< Transmit Good Packet Counter*/
+    STAT_GTXPKT,   /*< Transmit Packet/Frame Counter*/
+    STAT_GTXUCA,   /*< Transmit Unicast Frame Counter*/
+    STAT_GTXMCA,   /*< Transmit Multicast Frame Counter*/
+    STAT_GTXBCA,   /*< Transmit Broadcast Frame Counter*/
+    STAT_GTXPF,    /*< Transmit Pause Control Frame Counter*/
+    STAT_GTXPFC,   /*< Transmit PFC/Per-Priority Pause Control Frame Counter*/
+    STAT_GTXJBR,   /*< Transmit Jabber Counter*/
+    STAT_GTXFCS,   /*< Transmit FCS Error Counter*/
+    STAT_GTXCF,    /*< Transmit Control Frame Counter*/
+    STAT_GTXOVR,   /*< Transmit Oversize Packet Counter*/
+    STAT_GTXDFR,   /*< Transmit Single Deferral Frame Counter*/
+    STAT_GTXEDF,   /*< Transmit Multiple Deferral Frame Counter*/
+    STAT_GTXSCL,   /*< Transmit Single Collision Frame Counter*/
+    STAT_GTXMCL,   /*< Transmit Multiple Collision Frame Counter*/
+    STAT_GTXLCL,   /*< Transmit Late Collision Frame Counter*/
+    STAT_GTXXCL,   /*< Transmit Excessive Collision Frame Counter*/
+    STAT_GTXFRG,   /*< Transmit Fragment Counter*/
+    STAT_GTXERR,   /*< Transmit Error (set by system) Counter*/
+    STAT_GTXVLN,   /*< Transmit VLAN Tag Frame Counter*/
+    STAT_GTXDVLN,  /*< Transmit Double VLAN Tag Frame Counter*/
+    STAT_GTXRPKT,  /*< Transmit RUNT Frame Counter*/
+    STAT_GTXUFL,   /*< Transmit FIFO Underrun Counter.*/
+#if 0
+    STAT_GTXPFCP0, /*< Transmit PFC Frame Priority 0*/
+    STAT_GTXPFCP1, /*< Transmit PFC Frame Priority 1*/
+    STAT_GTXPFCP2, /*< Transmit PFC Frame Priority 2*/
+    STAT_GTXPFCP3, /*< Transmit PFC Frame Priority 3*/
+    STAT_GTXPFCP4, /*< Transmit PFC Frame Priority 4*/
+    STAT_GTXPFCP5, /*< Transmit PFC Frame Priority 5*/
+    STAT_GTXPFCP6 /*< Transmit PFC Frame Priority 6*/
+    STAT_GTXPFCP7, /*< Transmit PFC Frame Priority 7*/
+#endif
+    STAT_GTXNCL,   /*< Transmit Total Collision Counter*/
+    STAT_GTXBYT,   /*< Transmit Byte Counter*/
+    STAT_GTXLPI,   /*< TX EEE LPI Event Counter*/
+    STAT_GTXDLPI,  /*< TX EEE LPI Duration Counter*/
+    STAT_GTXLTLLFC    /*< Transmit Logical Type LLFC message counter*/
+}LPORT_STATS_TX_TYPE;
+
+typedef struct
+{
+    uint64_t    GRX64;   /*< Receive 64 Byte Frame Counter */
+    uint64_t    GRX127;  /*< Receive 65 to 127 Byte Frame Counter*/
+    uint64_t    GRX255;   /*< Receive 128 to 255 Byte Frame Counter*/
+    uint64_t    GRX511;   /*< Receive 256 to 511 Byte Frame Counter*/
+    uint64_t    GRX1023;  /*< Receive 512 to 1023 Byte Frame Counter*/
+    uint64_t    GRX1518;  /*< Receive 1024 to 1518 Byte Frame Counter*/
+    uint64_t    GRX1522;  /*< Receive 1519 to 1522 Byte Good VLAN Frame Counter*/
+    uint64_t    GRX2047;  /*< Receive 1519 to 2047 Byte Frame Counter*/
+    uint64_t    GRX4095;  /*< Receive 2048 to 4095 Byte Frame Counter*/
+    uint64_t    GRX9216;  /*< Receive 4096 to 9216 Byte Frame Counter*/
+    uint64_t    GRX16383; /*< Receive 9217 to 16838 Byte Frame Counter*/
+    uint64_t    GRXPKT;   /*< Receive frame/packet Counter*/
+    uint64_t    GRXUCA;   /*< Receive Unicast Frame Counter*/
+    uint64_t    GRXMCA;   /*< Receive Multicast Frame Counter*/
+    uint64_t    GRXBCA;   /*< Receive Broadcast Frame Counter*/
+    uint64_t    GRXFCS;   /*< Receive FCS Error Frame Counter*/
+    uint64_t    GRXCF;    /*< Receive Control Frame Counter*/
+    uint64_t    GRXPF;    /*< Receive PAUSE Frame Counter*/
+    uint64_t    GRXPP;    /*< Receive PFC (Per-Priority Pause) Frame Counter*/
+    uint64_t    GRXUO;    /*< Receive Unsupported Opcode Frame Counter*/
+    uint64_t    GRXUDA;   /*< Receive Unsupported DA for PAUSE/PFC Frame Counter*/
+    uint64_t    GRXWSA;   /*< Receive Wrong SA Frame Counter*/
+    uint64_t    GRXALN;   /*< Receive Alignment Error Frame Counter*/
+    uint64_t    GRXFLR;   /*< Receive Length Out of Range Frame Counter*/
+    uint64_t    GRXFRERR; /*< Receive Code Error Frame Counter*/
+    uint64_t    GRXFCR;   /*< Receive False Carrier Counter*/
+    uint64_t    GRXOVR;   /*< Receive Oversized Frame Counter*/
+    uint64_t    GRXJBR;   /*< Receive Jabber Frame Counter*/
+    uint64_t    GRXMTUE;  /*< Receive MTU Check Error Frame Counter*/
+    uint64_t    GRXMCRC;  /*< Matched CRC Frame Counter*/
+    uint64_t    GRXPRM;   /*< Receive Promiscuous Frame Counter*/
+    uint64_t    GRXVLN;   /*< Receive VLAN Tag Frame Counter*/
+    uint64_t    GRXDVLN;  /*< Receive Double VLAN Tag Frame Counter*/
+    uint64_t    GRXTRFU;  /*< Receive Truncated Frame Counter (due to RX FIFO full)*/
+    uint64_t    GRXPOK;   /*< Receive Good Packet Counter*/
+/*PFC are not in use in this platform */
+#if 0
+    uint64_t    RXPFCOFF0   /*< Receive PFC Frame Priority 0 XON to XOFF*/
+    uint64_t    RXPFCOFF1   /*< Receive PFC Frame Priority 1*/
+    uint64_t    RXPFCOFF2   /*< Receive PFC Frame Priority 2*/
+    uint64_t    RXPFCOFF3   /*< Receive PFC Frame Priority 3*/
+    uint64_t    RXPFCOFF4   /*< Receive PFC Frame Priority 4*/
+    uint64_t    RXPFCOFF5   /*< Receive PFC Frame Priority 5*/
+    uint64_t    RXPFCOFF6   /*< Receive PFC Frame Priority 6*/
+    uint64_t    RXPFCOFF7   /*< Receive PFC Frame Priority 7*/
+    uint64_t    RXPFCP0     /*< Receive PFC Frame Priority 0*/
+    uint64_t    RXPFCP1     /*< Receive PFC Frame Priority 1*/
+    uint64_t    RXPFCP2     /*< Receive PFC Frame Priority 2*/
+    uint64_t    RXPFCP3     /*< Receive PFC Frame Priority 3*/
+    uint64_t    RXPFCP4     /*< Receive PFC Frame Priority 4*/
+    uint64_t    RXPFCP5     /*< Receive PFC Frame Priority 5*/
+    uint64_t    RXPFCP6     /*< Receive PFC Frame Priority 6*/
+    uint64_t    RXPFCP7     /*< Receive PFC Frame Priority 7*/
+#endif
+    uint64_t    GRXSCHCRC;    /*< Receive SCH CRC Error*/
+    uint64_t    GRXBYT;   /*< Receive Byte Counter*/
+    uint64_t    GRXRPKT;  /*< Receive RUNT Frame Counter*/
+    uint64_t    GRXUND;   /*< Receive Undersize Frame Counter*/
+    uint64_t    GRXFRG;   /*< Receive Fragment Counter*/
+    uint64_t    GRXRBYT;  /*< Receive Runt Byte Counter*/
+    uint32_t    GRXLPI;   /*< RX EEE LPI Event Counter*/
+    uint32_t    GRXDLPI;  /*< RX EEE LPI Duration Counte*/
+    uint64_t    GRXPTLLFC;    /*< Receive Physical Type LLFC message counter*/
+    uint64_t    GRXLTLLFC;   /*< Receive Logical Type LLFC message Counter*/
+    uint64_t    GRXLLFCFCS;   /*< Receive Type LLFC message with CRC error Counter*/
+}lport_rx_stats_s;
+
+typedef struct
+{
+    uint64_t    GTX64;    /*< Transmit 64 Byte Frame Counter*/
+    uint64_t    GTX127;   /*< Transmit 65 to 127 Byte Frame Counter*/
+    uint64_t    GTX255;   /*< Transmit 128 to 255 Byte Frame Counter*/
+    uint64_t    GTX511;   /*< Transmit 256 to 511 Byte Frame Counter*/
+    uint64_t    GTX1023;  /*< Transmit 512 to 1023 Byte Frame Counter*/
+    uint64_t    GTX1518;  /*< Transmit 1024 to 1518 Byte Frame Counter*/
+    uint64_t    GTX1522;  /*< Transmit 1519 to 1522 Byte Good VLAN Frame Counter*/
+    uint64_t    GTX2047;  /*< Transmit 1519 to 2047 Byte Frame Counter*/
+    uint64_t    GTX4095;  /*< Transmit 2048 to 4095 Byte Frame Counter*/
+    uint64_t    GTX9216;  /*< Transmit 4096 to 9216 Byte Frame Counter*/
+    uint64_t    GTX16383; /*< Transmit 9217 to 16383 Byte Frame Counter*/
+    uint64_t    GTXPOK;   /*< Transmit Good Packet Counter*/
+    uint64_t    GTXPKT;   /*< Transmit Packet/Frame Counter*/
+    uint64_t    GTXUCA;   /*< Transmit Unicast Frame Counter*/
+    uint64_t    GTXMCA;   /*< Transmit Multicast Frame Counter*/
+    uint64_t    GTXBCA;   /*< Transmit Broadcast Frame Counter*/
+    uint64_t    GTXPF;    /*< Transmit Pause Control Frame Counter*/
+    uint64_t    GTXPFC;   /*< Transmit PFC/Per-Priority Pause Control Frame Counter*/
+    uint64_t    GTXJBR;   /*< Transmit Jabber Counter*/
+    uint64_t    GTXFCS;   /*< Transmit FCS Error Counter*/
+    uint64_t    GTXCF;    /*< Transmit Control Frame Counter*/
+    uint64_t    GTXOVR;   /*< Transmit Oversize Packet Counter*/
+    uint64_t    GTXDFR;   /*< Transmit Single Deferral Frame Counter*/
+    uint64_t    GTXEDF;   /*< Transmit Multiple Deferral Frame Counter*/
+    uint64_t    GTXSCL;   /*< Transmit Single Collision Frame Counter*/
+    uint64_t    GTXMCL;   /*< Transmit Multiple Collision Frame Counter*/
+    uint64_t    GTXLCL;   /*< Transmit Late Collision Frame Counter*/
+    uint64_t    GTXXCL;   /*< Transmit Excessive Collision Frame Counter*/
+    uint64_t    GTXFRG;   /*< Transmit Fragment Counter*/
+    uint64_t    GTXERR;   /*< Transmit Error (set by system) Counter*/
+    uint64_t    GTXVLN;   /*< Transmit VLAN Tag Frame Counter*/
+    uint64_t    GTXDVLN;  /*< Transmit Double VLAN Tag Frame Counter*/
+    uint64_t    GTXRPKT;  /*< Transmit RUNT Frame Counter*/
+    uint64_t    GTXUFL;   /*< Transmit FIFO Underrun Counter.*/
+#if 0
+    uint64_t    GTXPFCP0; /*< Transmit PFC Frame Priority 0*/
+    uint64_t    GTXPFCP1; /*< Transmit PFC Frame Priority 1*/
+    uint64_t    GTXPFCP2; /*< Transmit PFC Frame Priority 2*/
+    uint64_t    GTXPFCP3; /*< Transmit PFC Frame Priority 3*/
+    uint64_t    GTXPFCP4; /*< Transmit PFC Frame Priority 4*/
+    uint64_t    GTXPFCP5; /*< Transmit PFC Frame Priority 5*/
+    uint64_t    GTXPFCP6 /*< Transmit PFC Frame Priority 6*/
+    uint64_t    GTXPFCP7; /*< Transmit PFC Frame Priority 7*/
+#endif
+    uint64_t    GTXNCL;   /*< Transmit Total Collision Counter*/
+    uint64_t    GTXBYT;   /*< Transmit Byte Counter*/
+    uint32_t    GTXLPI;   /*< TX EEE LPI Event Counter*/
+    uint32_t    GTXDLPI;  /*< TX EEE LPI Duration Counter*/
+    uint64_t    GTXLTLLFC;    /*< Transmit Logical Type LLFC message counter*/
+}lport_tx_stats_s;
+
+typedef struct
+{
+    uint8_t saturate_en; /*< Saturate counter on respective max value*/
+    uint8_t cor_en; /*< Enable clear on read */
+    uint8_t eee_sym_mode; /*< EEE Counter symetric mode */
+}lport_stats_cfg_s;
+
+int lport_stats_get_rx(uint32_t portid, lport_rx_stats_s *rx_stats);
+int lport_stats_get_tx(uint32_t portid, lport_tx_stats_s *tx_stats);
+int lport_stats_rst_rx_single(uint32_t portid, LPORT_STATS_RX_TYPE stat_type);
+int lport_stats_rst_tx_single(uint32_t portid,  LPORT_STATS_TX_TYPE stat_type);
+int lport_stats_cfg_get(uint32_t portid, lport_stats_cfg_s *stats_cfg);
+int lport_stats_cfg_set(uint32_t portid, lport_stats_cfg_s *stats_cfg);
+int lport_stats_reset(uint32_t portid);
+
+#endif /* SHARED_OPENSOURCE_DRV_LPORT_LPORT_STATS_H_ */
diff --git a/drivers/net/bcmbca/lport/lport_types.h b/drivers/net/bcmbca/lport/lport_types.h
new file mode 100644
index 0000000000..f5f2078a4f
--- /dev/null
+++ b/drivers/net/bcmbca/lport/lport_types.h
@@ -0,0 +1,6 @@
+#ifndef _LPORT_TYPES_H_
+#define _LPORT_TYPES_H_
+
+#include <linux/types.h>
+
+#endif
diff --git a/drivers/net/bcmbca/lport/merlin_direct_access.c b/drivers/net/bcmbca/lport/merlin_direct_access.c
new file mode 100644
index 0000000000..d503a047da
--- /dev/null
+++ b/drivers/net/bcmbca/lport/merlin_direct_access.c
@@ -0,0 +1,741 @@
+/***********************************************************************/
+/*                                                                     */
+/*   MODULE:  merlin_direct_access.c                                   */
+/*   DATE:    01/03/2016                                               */
+/*   PURPOSE: Callback functions for Lport                             */
+/*                                                                     */
+/***********************************************************************/
+
+#include "lport_types.h"
+#include "lport_print.h"
+#include "lport_compat.h"
+#include "lport_defs.h"
+#include "lport_drv.h"
+#include "serdes_access.h"
+/* Microcode */
+#include "merlin_direct_ucode_image.h"
+
+#ifdef MERLIN_DEBUG
+#define MERLIN_DBG pr_err
+#else
+#define MERLIN_DBG(...)
+#endif
+
+#define MERLIN_ERR pr_err
+
+#define MERLIN_INFO MERLIN_ERR
+
+#define MERLIN_LANES_PER_CORE   2
+#define MERLIN_MAX_CORE_NUMBER  2
+#define MERLIN_MAX_LANE_NUMBER  MERLIN_LANES_PER_CORE*MERLIN_MAX_CORE_NUMBER
+/*RMIC/PMI address*/
+#define MMD_TYPE_OFFSET      27
+#define LANE_ADDRESS_OFFSET  16
+
+#define MASK_BIT(a) (1<<(a))
+#define MASK_BITS_TO(x) ((1<<(x))-1)
+#define MASK_BITS_BETWEEN(l, h) (MASK_BITS_TO(((h)+1)) & ~(MASK_BITS_TO(l)))
+#define MASK_ALL_BITS_16 (0xFFFF)
+
+#define MARLIN_SET_BIT(reg, posn)    ((reg) | (1L << (posn)))
+#define MARLIN_CLEAR_BIT(reg, posn)  ((reg) & ~(1L << (posn)))
+
+#define RAM_CORE_BASE   0x0050
+#define RAM_LANE_BASE   0x0400
+#define RAM_CORE_SIZE   0x0040
+#define RAM_LANE_SIZE   0x0100
+
+static int merlin_direct_tx_cfg_set(E_MERLIN_LANE lane_index, merlin_tx_cfg_t *tx_cfg);
+
+static inline void MERLIN_READ_REG(uint16_t dev_type, E_MERLIN_LANE lane_id, uint16_t reg_addr, uint16_t mask, uint16_t shift, uint16_t *value)
+{
+    uint32_t addr = 0;
+
+    addr = ((dev_type) << MMD_TYPE_OFFSET) | (((uint32_t)(lane_id % MERLIN_LANES_PER_CORE)) << LANE_ADDRESS_OFFSET) | reg_addr;
+    read_serdes_reg(lane_id / MERLIN_LANES_PER_CORE, addr, mask, value);
+    *value >>= shift;
+}
+
+static inline void MERLIN_WRITE_REG(uint16_t dev_type, E_MERLIN_LANE lane_id, uint16_t reg_addr, uint16_t mask, uint16_t shift, uint16_t value)
+{
+    uint32_t addr = 0;
+
+    addr = ((dev_type) << MMD_TYPE_OFFSET) | (((uint32_t)(lane_id % MERLIN_LANES_PER_CORE)) << LANE_ADDRESS_OFFSET) | reg_addr;
+    write_serdes_reg(lane_id / MERLIN_LANES_PER_CORE, addr, mask, value << shift);
+}
+
+static inline void MERLIN_RAM_ADDR(E_MERLIN_LANE lane_id, uint16_t size, uint16_t addr)
+{
+    if (lane_id % MERLIN_LANES_PER_CORE)
+        addr += RAM_LANE_SIZE;
+
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd202, MASK_BITS_BETWEEN(7, 8), 7, 0x2); /* ram memory access */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd202, MASK_BITS_BETWEEN(9, 9), 9, size > 1 ? 0x00 : 0x01); /* access mode word/byte */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd201, MASK_BITS_BETWEEN(0, 15), 0, addr); /* ram address */
+}
+
+static inline void MERLIN_READ_RAM(E_MERLIN_LANE lane_id, uint16_t size, uint16_t addr, uint16_t *value)
+{
+    MERLIN_RAM_ADDR(lane_id, size, addr);
+    MERLIN_READ_REG(0x1, lane_id, 0xd204, MASK_BITS_BETWEEN(0, 15), 0, value); /* read ram data */
+
+    if (size > 1)
+        *value = ((*value & 0xff) << 8) | (*value >> 8);
+}
+
+static inline void MERLIN_WRITE_RAM(E_MERLIN_LANE lane_id, uint16_t size, uint16_t addr, uint16_t value)
+{
+    if (size > 1)
+        value = ((value & 0xff) << 8) | (value >> 8);
+
+    MERLIN_RAM_ADDR(lane_id, size, addr);
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd203, MASK_BITS_BETWEEN(0, 15), 0, value); /* write ram data */
+}
+
+static int merlin_direct_microcode_load(E_MERLIN_ID merlin_id, uint8_t *code_image, uint16_t code_len)
+{
+    uint32_t lane_id;
+    uint16_t is_init_done;
+    uint16_t padded_len, data, count = 0;
+    uint8_t lsb_data;
+    uint16_t load_result0 = 0;
+    uint16_t load_result1 = 0;
+
+    lane_id = merlin_id * MERLIN_LANES_PER_CORE;
+
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0f2, MASK_BIT(6), 6, 0x1); /*uc_active*/
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0f2, MASK_BIT(0), 0, 0x1); /*core_dp_s_rstb*/
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd20d, MASK_BIT(1), 1, 0x1); /*micro_system_reset_n*/
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd20d, MASK_BIT(0), 0, 0x1); /*micro_system_clk_en*/
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd202, MASK_BIT(15), 15, 0x1); /*init_cmd*/
+
+    UDELAY(10000);
+
+    MERLIN_READ_REG(0x1, lane_id, 0xd205, MASK_BIT(15), 15, &is_init_done);
+    if (!is_init_done)
+    {
+        MERLIN_ERR("Failed to init serdes %d engine\n", merlin_id);
+        return -1;
+    }
+
+    padded_len = (code_len + 7) & 0xfff8 ; /* number of bytes to be writen, have to be multiple of 4 */ 
+
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd200, MASK_ALL_BITS_16, 0, padded_len - 1); /*ram_cnt*/
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd201, MASK_ALL_BITS_16, 0, 0x0); /*ram_addr*/
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd202, MASK_BIT(1), 1, 0x0); /*stop*/
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd202, MASK_BIT(3), 3, 0x1); /*write */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd202, MASK_BIT(0), 0, 0x1); /*run*/
+    for (count = 0; count < padded_len; count+=2)
+    {
+        lsb_data = (count < code_len) ? code_image[count] : 0x0;
+        data = ((count + 1) < code_len) ? code_image[count + 1] : 0x0;
+        data = (data << 8) | lsb_data;
+
+        MERLIN_WRITE_REG(0x1, lane_id, 0xd203, MASK_ALL_BITS_16, 0, data);
+    }
+
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd202, MASK_BIT(3), 3, 0x0); /*write */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd202, MASK_BIT(0), 0, 0x0); /*run*/
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd202, MASK_BIT(1), 1, 0x1); /* stop */
+    /* Verify microcode load */
+    MERLIN_READ_REG(0x1, lane_id, 0xd205, MASK_BIT(0), 0, &load_result0);
+    MERLIN_READ_REG(0x1, lane_id, 0xd205, MASK_BIT(1), 1, &load_result1);
+    if (load_result0 || load_result1)
+    {
+        MERLIN_ERR("Failed load firmware ERR0: %d ERR1: %d\n", load_result0, load_result1);
+        return -2;
+    }
+
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd202, MASK_BIT(4), 4, 0x1); /* mdio_dw8051_reset_n */
+    UDELAY(10000);
+
+    return 0;
+}
+
+static int merlin_direct_core_init(E_MERLIN_ID merlin_id, E_MERLIN_VCO pll)
+{
+    int rc;
+    uint32_t lane_id;
+
+    rc = merlin_direct_microcode_load(merlin_id, merlin_mptwo_ucode_image, MERLIN_MPTWO_UCODE_IMAGE_SIZE);
+    if (rc)
+    {
+        MERLIN_ERR("Failed to load microcode to serdes%d %d\n",merlin_id, rc);
+        return rc;
+    }
+
+    lane_id = merlin_id * MERLIN_LANES_PER_CORE;
+
+    MERLIN_WRITE_REG(0x1, lane_id, 0xffdc, MASK_BITS_BETWEEN(0, 4), 0, 0xa); /* broadcast address */
+    /* PMD Setup 50MHz */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0b9, MASK_BIT(0), 0, 0x0); /* mmd_resetb */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0b3, MASK_BITS_BETWEEN(11, 15), 11, 0x4); /* div */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0b6, MASK_BITS_BETWEEN(12, 15), 12, 0x0); /* i_ndiv_frac_l */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0b7, MASK_BITS_BETWEEN(0, 13), 0, 0x1000); /* i_ndiv_frac_h */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0b8, MASK_BIT(14), 14, 0x1); /* i_pll_sdm_pwrdnb */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0b8, MASK_BIT(13), 13, 0x1); /* mmd_en */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0b8, MASK_BIT(12), 12, 0x0); /* mmd_prsc4or5pwdb */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0b8, MASK_BIT(11), 11, 0x1); /* mmd_prsc8or9pwdb */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0b8, MASK_BIT(10), 10, 0x1); /* mmd_div_range */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0b8, MASK_BITS_BETWEEN(0, 9), 0, 0xce); /* i_ndiv_int */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0b9, MASK_BITS_BETWEEN(0, 2), 0, 0x3); /* i_pll_frac_mode, mmd_resetb */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x9100, MASK_BITS_BETWEEN(13, 15), 13, 0x6); /* refclk_sel */
+
+    /* AN Timer Speed Up */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x9107, MASK_BITS_BETWEEN(15,15), 15, 0x00); /* tick_override */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x9250, MASK_BITS_BETWEEN(0,15), 0, 0x029a); /* cl73_restart_timer */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x9251, MASK_BITS_BETWEEN(0,15), 0, 0x029a); /* cl37_ack_timer */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x9252, MASK_BITS_BETWEEN(0,15), 0, 0xa000); /* cl37_error_timer */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x9253, MASK_BITS_BETWEEN(0,15), 0, 0x10ee); /* cl73_break_link_timer */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x9254, MASK_BITS_BETWEEN(0,15), 0, 0xa000); /* cl73_error_timer */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x9255, MASK_BITS_BETWEEN(0,15), 0, 0x0bb8); /* cl73_pd_dme_lock_timer */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x9256, MASK_BITS_BETWEEN(0,15), 0, 0x1b00); /* cl73_link_up_timer */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x9257, MASK_BITS_BETWEEN(0,15), 0, 0x8235); /* link_fail_inhibit_timer_cl72 */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x9258, MASK_BITS_BETWEEN(0,15), 0, 0x8235); /* link_fail_inhibit_timer_ncl72 */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x925a, MASK_BITS_BETWEEN(0,15), 0, 0x8235); /* cl72_max_wait_timer */
+    MERLIN_WRITE_REG(0x3, lane_id, 0x925c, MASK_BITS_BETWEEN(0,15), 0, 0x000f); /* ignore_link_timer_period */
+
+    /* Datapath Reset */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0f2, MASK_BIT(0), 0, 0x1); /* core_dp_s_rstb */
+    UDELAY(10000);
+
+    /* afe_hw_version */
+    MERLIN_WRITE_RAM(lane_id, 1, RAM_CORE_BASE + 0x0f, 0x1);
+
+    return 0;
+}
+
+#pragma pack(push,1)
+typedef struct {
+    uint16_t lane_cfg_from_pcs:1;
+    uint16_t an_enabled:1;
+    uint16_t dfe_on:1;
+    uint16_t force_brdfe_on:1;
+    uint16_t media_type:2;
+    uint16_t unreliable_los:1;
+    uint16_t scrambling_dis:1;
+    uint16_t cl72_auto_polarity_en:1;
+    uint16_t cl72_restart_timeout_en:1;
+    uint16_t reserved:6;
+} lane_config_t;
+#pragma pack(pop)
+
+static int merlin_direct_lane_init(E_MERLIN_LANE lane_id, LPORT_PORT_MUX_SELECT mux_sel)
+{
+    merlin_tx_cfg_t tx_cfg = {};
+    lane_config_t lane_conf = {};
+
+    /* Change Speed */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd082, MASK_BITS_BETWEEN(0, 15), 0, 0x0000);
+    MERLIN_WRITE_REG(0x3, lane_id, 0x0000, MASK_BIT(15), 15, 0x1); /* lane reset */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd081, MASK_BIT(1), 1, 0x0); /* ln_dp_s_rstb */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd0e3, MASK_BIT(1), 1, 0x1); /* byppass pmd tx oversampling */
+
+    switch (mux_sel)
+    {
+    case PORT_SGMII:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(11), 11, 0x0); /* credit_sw_en */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(6), 6, 0x1); /* SW_actual_speed_force_en */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(0, 5), 0, 0x2); /* SW_actual_speed */
+        break; 
+    case PORT_SGMII_AN_IEEE_CL37:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(12,13), 12, 0x1); /* use_ieee_reg_ctrl_sel */
+        MERLIN_WRITE_REG(0x0, lane_id, 0x0004, MASK_BIT(5), 5, 0x1); /* duplex */
+        MERLIN_WRITE_REG(0x0, lane_id, 0x0000, MASK_BIT(12), 12, 0x1); /* AN enable */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(11), 11, 0x0); /* credit_sw_en */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(6), 6, 0x0); /* SW_actual_speed_force_en */
+        break;
+    case PORT_SGMII_AN_USER_CL37:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(12,13), 12, 0x2); /*use_ieee_reg_ctrl_sel */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc481, MASK_BIT(4), 4, 0x1); /* duplex */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc480, MASK_BIT(6), 6, 0x1); /* AN enable */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(11), 11, 0x0); /* credit_sw_en */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(6), 6, 0x0); /* SW_actual_speed_force_en */
+        break;
+    case PORT_SGMII_AN_MASTER:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(12,13), 12, 0x2); /* use_ieee_reg_ctrl_sel */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc481, MASK_BIT(2), 2, 0x1); /* duplex */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc481, MASK_BITS_BETWEEN(0,1), 0, 0x2); /* speed */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc481, MASK_BIT(9), 9, 0x1); /* mater */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc480, MASK_BITS_BETWEEN(6,7), 6, 0x3); /* AN enable */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(11), 11, 0x0); /* credit_sw_en */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(6), 6, 0x0); /* SW_actual_speed_force_en */
+        break;
+    case PORT_SGMII_AN_SLAVE:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(12,13), 12, 0x2); /* use_ieee_reg_ctrl_sel */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc480, MASK_BITS_BETWEEN(6,7), 6, 0x3); /* AN enable */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(11), 11, 0x0); /* credit_sw_e n*/
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(6), 6, 0x0); /* SW_actual_speed_force_en */
+        break;
+    case PORT_HSGMII:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(11), 11, 0x0); /* credit_sw_en */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(6), 6, 0x1); /* SW_actual_speed_force_en */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(0, 5), 0, 0x3); /* SW_actual_speed */
+        MERLIN_WRITE_REG(0x3, lane_id, 0x9270, MASK_BITS_BETWEEN(0, 15), 0, 0x0021); /* Reg2p5G_ClockCount0 */
+        MERLIN_WRITE_REG(0x3, lane_id, 0x9233, MASK_BITS_BETWEEN(0, 15), 0, 0x0002); /* Reg2p5G_modulo */
+        break;
+    case PORT_SFI:
+    case PORT_XFI:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(11), 11, 0x0); /* credit_sw_en */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(6), 6, 0x1); /* SW_actual_speed_force_en */
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(0, 5), 0, 0xf); /* SW_actual_speed */
+        break;
+    default:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc457, MASK_BITS_BETWEEN(0, 15), 0, 0x0000);
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(0, 15), 0, 0x1002);
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc433, MASK_BITS_BETWEEN(0, 15), 0, 0x01c8);
+        MERLIN_WRITE_REG(0x1, lane_id, 0xd081, MASK_BITS_BETWEEN(0, 15), 0, 0x0001);
+        MERLIN_WRITE_REG(0x1, lane_id, 0xd082, MASK_BITS_BETWEEN(0, 15), 0, 0x0033);
+        return 0;
+    }
+
+    MERLIN_WRITE_REG(0x3, lane_id, 0xc457, MASK_BIT(0), 0, 0x1); /* rx_rstb_lane */
+    MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BIT(7), 7, 0x1); /* mac_creditenable */
+    MERLIN_WRITE_REG(0x3, lane_id, 0xc433, MASK_BIT(1), 1, 0x1); /* tx_rstb_lane */
+    MERLIN_WRITE_REG(0x3, lane_id, 0xc433, MASK_BIT(0), 0, 0x1); /* enable_tx_lane */
+
+    /* LPI pass-through */
+    MERLIN_WRITE_REG(0x3, lane_id, 0xc450, MASK_BIT(2), 2, 0x1); /* lpi_enable */
+
+    /* Transmitter Configuration */
+    switch (mux_sel)
+    {
+    case PORT_SGMII:
+    case PORT_SGMII_AN_MASTER:
+    case PORT_SGMII_AN_SLAVE:
+        tx_cfg = (merlin_tx_cfg_t){ 0, 40, 0, 0, 1, 1, 1, 1, 4, 0 };
+        break;
+    case PORT_SGMII_AN_IEEE_CL37:
+    case PORT_SGMII_AN_USER_CL37:
+        tx_cfg = (merlin_tx_cfg_t){ 2, 44, 11, 2, 1, 1, 1, 1, 5, 0 };
+        break;
+    case PORT_HSGMII:
+        tx_cfg = (merlin_tx_cfg_t){ 0, 60, 0, 0, 1, 1, 1, 1, 5, 4 };
+        break;
+    case PORT_SFI:
+        tx_cfg = (merlin_tx_cfg_t){ 2, 44, 11, 2, 0, 1, 1, 1, 5, 0 };
+        break;
+    case PORT_XFI:
+        tx_cfg = (merlin_tx_cfg_t){ 0, 46, 8, 0, 0, 1, 1, 1, 5, 0 };
+        break;
+    default:
+       return -1;
+    }
+
+    merlin_direct_tx_cfg_set(lane_id, &tx_cfg);
+
+    /* Lane configuration (RAM Variables) */
+    MERLIN_READ_RAM(lane_id, 2, RAM_LANE_BASE + 0x00, (uint16_t *)&lane_conf);
+
+    switch (mux_sel)
+    {
+    case PORT_SGMII:
+        break; 
+    case PORT_SGMII_AN_MASTER:
+    case PORT_SGMII_AN_SLAVE:
+        lane_conf.an_enabled = 1;
+        lane_conf.lane_cfg_from_pcs = 1;
+        break;
+    case PORT_SGMII_AN_IEEE_CL37:
+    case PORT_SGMII_AN_USER_CL37:
+        lane_conf.media_type = 2;
+        lane_conf.an_enabled = 1;
+        lane_conf.lane_cfg_from_pcs = 1;
+        break;
+    case PORT_HSGMII:
+        break;
+    case PORT_XFI:
+        break;
+    case PORT_SFI:
+        lane_conf.dfe_on = 1;
+        lane_conf.media_type = 2;
+        lane_conf.unreliable_los = 0;
+        break;
+    default:
+        return -1;
+    }
+
+    MERLIN_WRITE_RAM(lane_id, 2, RAM_LANE_BASE + 0x00, *(uint16_t *)&lane_conf);
+
+    /* Datapath Reset */
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd081, MASK_BIT(1), 1, 0x1); /* ln_dp_s_rstb */
+    UDELAY(10000);
+
+    return 0;
+}
+
+static int merlin_direct_get_status(E_MERLIN_LANE lane_id, lport_port_status_s *port_status)
+{
+    uint16_t port_speed;
+    uint16_t port_up;
+
+    MERLIN_READ_REG(0x3, lane_id, 0xc474, MASK_BIT(1), 1, &port_up);
+    MERLIN_READ_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(0, 5), 0, &port_speed);
+    port_status->port_up = port_up;
+    switch (port_speed)
+    {
+    case 0:
+        port_status->rate = LPORT_RATE_10MB;
+        break;
+    case 1:
+        port_status->rate = LPORT_RATE_100MB;
+        break;
+    case 2:
+        port_status->rate = LPORT_RATE_1000MB;
+        break;
+    case 3:
+        port_status->rate = LPORT_RATE_2500MB;
+        break;
+    case 4:
+        port_status->rate = LPORT_RATE_2500MB;
+        break;
+    case 0xD:
+    case 0x34:
+        port_status->rate = LPORT_RATE_1000MB;
+        break;
+    case 0xf:
+    case 0x1b:
+    case 0x1f:
+    case 0x33:
+        port_status->rate = LPORT_RATE_10G;
+        break;
+    default:
+        port_status->rate = LPORT_RATE_UNKNOWN;
+        break;
+    }
+    port_status->duplex = LPORT_FULL_DUPLEX; 
+    return 0;
+}
+
+static int merlin_direct_speed_set(E_MERLIN_LANE lane_id, LPORT_PORT_RATE port_rate)
+{
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd081, MASK_BIT(1), 1, 0x0); /* ln_dp_s_rstb */
+    UDELAY(10000);
+
+    switch (port_rate)
+    {
+    case LPORT_RATE_10G:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(0, 5), 0, 0xf); /* SW_actual_speed */
+        break;
+    case LPORT_RATE_2500MB:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(0, 5), 0, 0x3); /* SW_actual_speed */
+        break;
+    case LPORT_RATE_1000MB:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(0, 5), 0, 0x2); /* SW_actual_speed */
+        break;
+    case LPORT_RATE_100MB:
+        MERLIN_WRITE_REG(0x3, lane_id, 0xc30b, MASK_BITS_BETWEEN(0, 5), 0, 0x1); /* SW_actual_speed */
+        break;
+    default:
+        MERLIN_ERR("Trying to set invalid port speed %d \n", port_rate);
+        return -1;
+        break;
+    }
+
+    MERLIN_WRITE_REG(0x1, lane_id, 0xd081, MASK_BIT(1), 1, 0x1); /* ln_dp_s_rstb */
+    UDELAY(10000);
+
+    return 0;
+}
+
+static int merlin_direct_lane_status_get(uint16_t lane_index, merlin_status_t *status)
+{
+    MERLIN_READ_REG(3, lane_index, 0xc441, MASK_BIT(8), 8, &status->tx_LOCAL_FAULT);
+    MERLIN_READ_REG(3, lane_index, 0xc441, MASK_BIT(7), 7, &status->tx_REMOTE_FAULT);
+    MERLIN_READ_REG(3, lane_index, 0xc470, MASK_BIT(3), 3, &status->PMD_LOCK);
+    MERLIN_READ_REG(3, lane_index, 0xc470, MASK_BIT(0), 0, &status->signal_ok);
+    MERLIN_READ_REG(3, lane_index, 0xc474, MASK_BIT(8), 8, &status->rx_LOCAL_FAULT);
+    MERLIN_READ_REG(3, lane_index, 0xc474, MASK_BIT(7), 7, &status->rx_REMOTE_FAULT);
+    MERLIN_READ_REG(3, lane_index, 0xc474, MASK_BIT(1), 1, &status->rx_LINK_STATUS);
+    MERLIN_READ_REG(3, lane_index, 0xc474, MASK_BIT(0), 0, &status->rx_SYNC_STATUS);
+    MERLIN_READ_REG(1, lane_index, 0xd128, MASK_BIT(9), 9, &status->pll_lock);
+
+    return 0;
+}
+
+static int merlin_direct_lane_stats_get(uint16_t lane_index, merlin_stats_t *stats)
+{
+    MERLIN_READ_REG(3, lane_index, 0xc468, MASK_BITS_BETWEEN(0, 7), 0, &stats->kcode66ErrCount);
+    MERLIN_READ_REG(3, lane_index, 0xc468, MASK_BITS_BETWEEN(8, 15), 8, &stats->sync66ErrCount);
+    MERLIN_READ_REG(3, lane_index, 0xc469, MASK_BITS_BETWEEN(2, 9), 2, &stats->cl49ieee_errored_blocks);
+    MERLIN_READ_REG(3, lane_index, 0xc46e, MASK_BITS_BETWEEN(0, 7), 0, &stats->BER_count_per_ln);
+    MERLIN_READ_REG(3, lane_index, 0x9227, MASK_BITS_BETWEEN(0, 7), 0, &stats->cl49_invalid_sh_cnt);
+    MERLIN_READ_REG(3, lane_index, 0x9227, MASK_BITS_BETWEEN(8, 15), 8, &stats->cl49_valid_sh_cnt);
+
+    return 0;
+}
+
+static int merlin_direct_lane_prbs_stats_get(uint16_t lane_index, merlin_prbs_stats_t *stats)
+{
+    uint16_t reg_lo, reg_hi;
+
+    reg_lo = 0;
+    MERLIN_READ_REG(1, lane_index, 0xD0D9, MASK_ALL_BITS_16, 0, &reg_lo);
+    stats->prbs_lock_status = (reg_lo & 0x1);//1- PRBS checker is locked 
+
+    reg_lo = reg_hi = 0; 
+    MERLIN_READ_REG(1, lane_index, 0xD0DA, MASK_ALL_BITS_16, 0, &reg_hi);
+    MERLIN_READ_REG(1, lane_index, 0xD0DB, MASK_ALL_BITS_16, 0, &reg_lo);
+
+    stats->prbs_lock_lost =  (uint16_t)(reg_hi >> 15);
+
+    // Clear bit 15 it is prbs lock lost status bit;
+    reg_hi = MARLIN_CLEAR_BIT(reg_hi, 15);
+
+    stats->prbs_error = ((uint32_t)(reg_hi) << 16) | (uint32_t)reg_lo;
+
+    return 0;
+}
+
+static int merlin_direct_lane_prbs_generate(uint16_t lane_index, uint16_t* p_prbs_type)
+{
+    uint32_t prog_patten_gen_mode = 
+        (*p_prbs_type == SERDES_PRBS_PATTERN_TYPE_8180) ? 1 : 0; //bit pattern 8 ones / 8 zeros 
+    uint16_t reg_val = 1;//Enable prbs_generator(bit 0)
+
+    if (prog_patten_gen_mode)
+    {
+        /* In case that prbs generator was enable  */
+        MERLIN_WRITE_REG(1, lane_index, 0xD0E1, MASK_BIT(0), 0, 0x0);
+
+        /*
+         * Default fixed pattern  8 ones / 8 zeros
+         * Enable fix pattern + default fixed pattern
+         */
+        MERLIN_WRITE_REG(1, lane_index, 0xD0E0, MASK_BITS_BETWEEN(0, 15), 0, 0x3);  
+    }
+    else
+    {
+        /* Disable fixed pattern */
+        MERLIN_WRITE_REG(1, lane_index, 0xD0E0, MASK_BIT(0), 0, 0x0);
+
+        reg_val |= (*p_prbs_type << 1);
+        /* Enable prbs_generator(bit 0) with prbs type: PRBS7|PRBS9|PRBS11|PRBS15|PRBS23|PRBS31|PRBS58 */
+        MERLIN_WRITE_REG(1, lane_index, 0xD0E1, MASK_BITS_BETWEEN(0,3), 0, reg_val);
+    } 	
+
+    return 0;
+}
+
+
+static int merlin_direct_lane_prbs_monitor(uint16_t lane_index, uint16_t* p_prbs_type)
+{
+    uint16_t reg_val = 1;//Enable prbs_generator(bit 0)
+
+    reg_val |= (*p_prbs_type << 1);
+
+    /* Enable prbs_generator control with prbs type  //PRBS7|PRBS9|PRBS11|PRBS15|PRBS23|PRBS31|PRBS58 + prbs_en bit 0 */
+    MERLIN_WRITE_REG(1, lane_index, 0xD0D1, MASK_BITS_BETWEEN(0,3), 0, reg_val);
+
+    return 0;
+}
+
+
+static int merlin_direct_core_id_get(uint16_t lane_index, merlin_serdes_id_t *id)
+{
+    MERLIN_READ_REG(3, lane_index, 0x910e, MASK_BITS_BETWEEN(14, 15), 14, &id->rev_letter);
+    MERLIN_READ_REG(3, lane_index, 0x910e, MASK_BITS_BETWEEN(11, 13), 11, &id->rev_number);
+    MERLIN_READ_REG(3, lane_index, 0x910e, MASK_BITS_BETWEEN(9, 10), 9, &id->bonding);
+    MERLIN_READ_REG(3, lane_index, 0x910e, MASK_BITS_BETWEEN(6, 8), 6, &id->tech_proc);
+    MERLIN_READ_REG(3, lane_index, 0x910e, MASK_BITS_BETWEEN(0, 5), 0, &id->model_number);
+    return 0;
+}
+
+static int merlin_direct_loopback_set(E_MERLIN_LANE lane_index, merlin_loopback_set_t *in)
+{
+    int ret = 0;
+    uint16_t lane_map;
+
+    switch(in->mode)
+    {
+    case MERLIN_PCS_LOCAL_LOOPBACK:
+        MERLIN_READ_REG(3, lane_index, 0x9109, MASK_BITS_BETWEEN(4, 7), 4, &lane_map);
+        if(!in->enable)
+            lane_map |= 1<<lane_index;
+        else
+            lane_map &= ~(1<<lane_index);
+        MERLIN_WRITE_REG(1, lane_index, 0xd0c1, MASK_BIT(7), 7, (in->enable != 0));
+        MERLIN_WRITE_REG(3, lane_index, 0x9109, MASK_BITS_BETWEEN(4, 7), 4, lane_map);
+        break;
+    case MERLIN_PCS_REMOTE_LOOPBACK:
+        MERLIN_READ_REG(3, lane_index, 0x9109, MASK_BITS_BETWEEN(12, 15), 12, &lane_map);
+        if(!in->enable)
+            lane_map |= 1<<lane_index;
+        else
+            lane_map &= ~(1<<lane_index);
+        MERLIN_WRITE_REG(3, lane_index, 0x9109, MASK_BITS_BETWEEN(12, 15), 12, lane_map);
+        break;
+    case MERLIN_PMD_LOCAL_LOOPBACK:
+        MERLIN_WRITE_REG(1, lane_index, 0xd0c1, MASK_BIT(7), 7, (in->enable != 0));
+        MERLIN_WRITE_REG(1, lane_index, 0xd0d2, MASK_BIT(0), 0, in->enable);
+        break;
+    case MERLIN_PMD_REMOTE_LOOPBACK:
+        if (in->enable)
+        {
+            /*locks Loop timing */
+            MERLIN_WRITE_REG(1, lane_index, 0xd075, MASK_BIT(2), 2, 0);
+            MERLIN_WRITE_REG(1, lane_index, 0xd070, MASK_BIT(0), 0, 1);
+            MERLIN_WRITE_REG(1, lane_index, 0xd070, MASK_BIT(1), 1, 1);
+            UDELAY(25);
+            MERLIN_WRITE_REG(1, lane_index, 0xd070, MASK_BIT(2), 2, 1);
+            MERLIN_WRITE_REG(1, lane_index, 0xd0e2, MASK_BIT(0), 0, 1);
+            UDELAY(50);
+        }
+        else
+        {
+            MERLIN_WRITE_REG(1, lane_index, 0xd0e2, MASK_BIT(0), 0, 0);
+            MERLIN_WRITE_REG(1, lane_index, 0xd070, MASK_BIT(2), 2, 0);
+            MERLIN_WRITE_REG(1, lane_index, 0xd070, MASK_BIT(1), 1, 0);
+            MERLIN_WRITE_REG(1, lane_index, 0xd070, MASK_BIT(0), 0, 0);
+            MERLIN_WRITE_REG(1, lane_index, 0xd075, MASK_BIT(2), 2, 1);
+        }
+        break;
+    default:
+        MERLIN_ERR("loopback mode %d is not supported\n", in->mode);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+static int merlin_direct_tx_cfg_set(E_MERLIN_LANE lane_index, merlin_tx_cfg_t *tx_cfg)
+{
+    uint32_t parameters_valid = 0;
+
+    if ((tx_cfg->pre > 10) || (tx_cfg->pre < 0))
+        MERLIN_ERR("ERR_CODE_TXFIR_PRE_INVALID\n");
+    else if ((tx_cfg->main > 60) || (tx_cfg->main < 0))
+        MERLIN_ERR("ERR_CODE_TXFIR_MAIN_INVALID\n");
+    else if (((tx_cfg->post2 != 0) && (tx_cfg->post1 > 18)) || (tx_cfg->post1 < 0))
+        MERLIN_ERR("ERR_CODE_TXFIR_POST1_POST2_INVALID\n");
+    else if (((tx_cfg->post2 == 0) && (tx_cfg->post1 > 23)) || (tx_cfg->post1 < 0))
+        MERLIN_ERR("ERR_CODE_TXFIR_POST1_POST2_INVALID\n");
+    else if (tx_cfg->post2 > 5)
+        MERLIN_ERR("ERR_CODE_TXFIR_POST2_INVALID\n");
+    else if (tx_cfg->main < (tx_cfg->pre + tx_cfg->post1 + tx_cfg->post2 + 1))
+        MERLIN_ERR("ERR_CODE_TXFIR_SUM_LIMIT\n");
+    else if ((tx_cfg->pre + tx_cfg->main + tx_cfg->post1 + tx_cfg->post2) > 60)
+        MERLIN_ERR("ERR_CODE_TXFIR_SUM_LIMIT\n");
+    else if ((tx_cfg->post2 != 0) && ((tx_cfg->pre + tx_cfg->post1) > 22))
+        MERLIN_ERR("ERR_CODE_TXFIR_SUM_LIMIT\n");
+    else if ((tx_cfg->post2 == 0) && ((tx_cfg->pre + tx_cfg->post1) > 27))
+        MERLIN_ERR("ERR_CODE_TXFIR_SUM_LIMIT\n");
+    else if ((tx_cfg->post2to1 < 0) || tx_cfg->post2to1 > 1)
+        MERLIN_ERR("ERR_CODE_POST2TO1_INVALID\n");
+    else if ((tx_cfg->en_pre < 0) || tx_cfg->en_pre > 1)
+        MERLIN_ERR("ERR_CODE_EN_PRE_INVALID\n");
+    else if ((tx_cfg->en_post1 < 0) || tx_cfg->en_post1 > 1)
+        MERLIN_ERR("ERR_CODE_EN_POST1_INVALID\n");
+    else if ((tx_cfg->en_post2 < 0) || tx_cfg->en_post2 > 1)
+        MERLIN_ERR("ERR_CODE_EN_POST2_INVALID\n");
+    else if ((tx_cfg->tx_refcalshunt < 0) || tx_cfg->tx_refcalshunt > 15)
+        MERLIN_ERR("ERR_CODE_TX_REFCALSHUNT_INVALID\n");
+    else if ((tx_cfg->hpf < 0) || tx_cfg->hpf > 15)
+        MERLIN_ERR("ERR_CODE_HPF_INVALID\n");
+    else
+        parameters_valid = 1;
+
+    if (parameters_valid != 1)
+        return -1;
+
+    MERLIN_WRITE_REG(1, lane_index, 0xd110, MASK_BITS_BETWEEN(0, 3), 0, tx_cfg->pre);
+    MERLIN_WRITE_REG(1, lane_index, 0xd111, MASK_BITS_BETWEEN(0, 5), 0, tx_cfg->main);
+    MERLIN_WRITE_REG(1, lane_index, 0xd110, MASK_BITS_BETWEEN(5, 9), 5, tx_cfg->post1);
+    MERLIN_WRITE_REG(1, lane_index, 0xd111, MASK_BITS_BETWEEN(7, 10), 7, tx_cfg->post2);
+    MERLIN_WRITE_REG(1, lane_index, 0xd0a5, MASK_BIT(15), 15, tx_cfg->post2to1);
+    MERLIN_WRITE_REG(1, lane_index, 0xd0a5, MASK_BIT(14), 14, tx_cfg->en_pre);
+    MERLIN_WRITE_REG(1, lane_index, 0xd0a5, MASK_BIT(13), 13, tx_cfg->en_post1);
+    MERLIN_WRITE_REG(1, lane_index, 0xd0a5, MASK_BIT(12), 12, tx_cfg->en_post2);
+    MERLIN_WRITE_REG(1, lane_index, 0xd0a3, MASK_BITS_BETWEEN(2, 5), 2, tx_cfg->tx_refcalshunt);
+    MERLIN_WRITE_REG(1, lane_index, 0xd0a2, MASK_BITS_BETWEEN(0, 3), 0, tx_cfg->hpf);
+
+    return 0;
+}
+
+static int merlin_direct_tx_cfg_get(E_MERLIN_LANE lane_index, merlin_tx_cfg_t *tx_cfg)
+{
+    MERLIN_READ_REG(1, lane_index, 0xd110, MASK_BITS_BETWEEN(0, 3), 0, &tx_cfg->pre);
+    MERLIN_READ_REG(1, lane_index, 0xd111, MASK_BITS_BETWEEN(0, 5), 0, &tx_cfg->main);
+    MERLIN_READ_REG(1, lane_index, 0xd110, MASK_BITS_BETWEEN(5, 9), 5, &tx_cfg->post1);
+    MERLIN_READ_REG(1, lane_index, 0xd111, MASK_BITS_BETWEEN(7, 10), 7, &tx_cfg->post2);
+    MERLIN_READ_REG(1, lane_index, 0xd0a5, MASK_BIT(15), 15, &tx_cfg->post2to1);
+    MERLIN_READ_REG(1, lane_index, 0xd0a5, MASK_BIT(14), 14, &tx_cfg->en_pre);
+    MERLIN_READ_REG(1, lane_index, 0xd0a5, MASK_BIT(13), 13, &tx_cfg->en_post1);
+    MERLIN_READ_REG(1, lane_index, 0xd0a5, MASK_BIT(12), 12, &tx_cfg->en_post2);
+    MERLIN_READ_REG(1, lane_index, 0xd0a3, MASK_BITS_BETWEEN(2, 5), 2, &tx_cfg->tx_refcalshunt);
+    MERLIN_READ_REG(1, lane_index, 0xd0a2, MASK_BITS_BETWEEN(0, 3), 0, &tx_cfg->hpf);
+
+    return 0;
+}
+
+static int  merlin_direct_ioctl(E_MERLIN_LANE lane_index, merlin_command_t cmd, merlin_control_t *data)
+{
+    int ret = 0;
+
+    switch(cmd)
+    {
+    case MERLIN_CMD_STATUS_GET:
+        ret = merlin_direct_lane_status_get(lane_index, &data->status);
+        break;
+    case MERLIN_CMD_STATS_GET:
+        ret = merlin_direct_lane_stats_get(lane_index, &data->stats);
+        break;
+    case MERLIN_CMD_PRBS_GENRATE:
+        ret = merlin_direct_lane_prbs_generate(lane_index, &data->prbs_type);
+        break;
+    case MERLIN_CMD_PRBS_MONITOR:
+        ret = merlin_direct_lane_prbs_monitor(lane_index, &data->prbs_type);
+        break;
+    case MERLIN_CMD_PRBS_STATS_GET:
+        ret = merlin_direct_lane_prbs_stats_get(lane_index, &data->prbs_stats);
+        break;
+    case MERLIN_CMD_FORCE_LINK_DOWN:
+        MERLIN_WRITE_REG(1, lane_index, 0x09, 0x1, 1+lane_index, 0x0);
+        break;
+    case MERLIN_CMD_FORCE_LINK_UP:
+        MERLIN_WRITE_REG(1, lane_index, 0x09, 0x1, 1+lane_index, 0x1);
+        break;
+    case MERLIN_CMD_ID:
+        ret = merlin_direct_core_id_get(lane_index, &data->serdes_id);
+        break;
+    case MERLIN_CMD_REG_READ:
+        if (data->reg_data.device_type == 9)
+            MERLIN_READ_RAM(lane_index, 2, data->reg_data.reg_addr, &data->reg_data.reg_value);
+        else
+            MERLIN_READ_REG(data->reg_data.device_type, lane_index, data->reg_data.reg_addr, 0xffff, 0, &data->reg_data.reg_value);
+        break;
+    case MERLIN_CMD_REG_WRITE:
+        if (data->reg_data.device_type == 9)
+            MERLIN_WRITE_RAM(lane_index, 2, data->reg_data.reg_addr, data->reg_data.reg_value);
+        else
+            MERLIN_WRITE_REG(data->reg_data.device_type, lane_index, data->reg_data.reg_addr, 0xffff, 0, data->reg_data.reg_value);
+        break;
+    case MERLIN_CMD_LOOPBACK_SET:
+        ret = merlin_direct_loopback_set(lane_index, &data->loopback);
+        break;
+    case MERLIN_CMD_TXCFG_SET:
+        ret = merlin_direct_tx_cfg_set(lane_index, &data->tx_cfg);
+        break;
+    case MERLIN_CMD_TXCFG_GET:
+        ret = merlin_direct_tx_cfg_get(lane_index, &data->tx_cfg);
+        break;
+    default:
+        MERLIN_ERR("Command %d is not supported\n", cmd);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
+extern merlin_sdk_cb_s merlin_callbacks;
+
+void lport_serdes_drv_register(void)
+{
+    merlin_callbacks.merlin_core_init = merlin_direct_core_init;
+    merlin_callbacks.merlin_lane_init = merlin_direct_lane_init;
+    merlin_callbacks.merlin_speed_set = merlin_direct_speed_set;
+    merlin_callbacks.merlin_get_status = merlin_direct_get_status;
+    merlin_callbacks.merlin_ioctl = merlin_direct_ioctl;
+}
diff --git a/drivers/net/bcmbca/lport/merlin_direct_ucode_image.h b/drivers/net/bcmbca/lport/merlin_direct_ucode_image.h
new file mode 100644
index 0000000000..47ecf60a70
--- /dev/null
+++ b/drivers/net/bcmbca/lport/merlin_direct_ucode_image.h
@@ -0,0 +1,2132 @@
+#define MERLIN_MPTWO_UCODE_IMAGE_VERSION "D10E_12"  /* matches the version number from microcode */
+#define MERLIN_MPTWO_UCODE_IMAGE_SIZE    25503
+#define MERLIN_MPTWO_UCODE_IMAGE_CRC     0x555B
+
+unsigned char merlin_mptwo_ucode_image[MERLIN_MPTWO_UCODE_IMAGE_SIZE] = {
+  0x75, 0x81, 0x31, 0x02, 0x57, 0xae, 0xe5, 0x31, 0x70, 0x28, 0x12, 0x4d,
+  0xbe, 0x12, 0x5d, 0x44, 0x90, 0x00, 0x60, 0xe0, 0x30, 0xe0, 0x08, 0x12,
+  0x2e, 0x6f, 0x70, 0x03, 0x12, 0x2e, 0xe2, 0x90, 0x00, 0x66, 0xe0, 0xb4,
+  0xff, 0x0c, 0xa3, 0xe0, 0xb4, 0xff, 0x07, 0xe4, 0xfd, 0x7f, 0x16, 0x12,
+  0x3a, 0xfb, 0x90, 0x04, 0x83, 0xe0, 0xa3, 0xf0, 0x7f, 0x1e, 0x12, 0x5f,
+  0xed, 0x8e, 0x0e, 0x8f, 0x0f, 0xe5, 0x0e, 0x13, 0x13, 0x13, 0x54, 0x1f,
+  0x90, 0x04, 0x83, 0xf0, 0xef, 0x54, 0x10, 0x70, 0x11, 0xe5, 0x0f, 0x78,
+  0x05, 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9, 0x54, 0x3f, 0xff, 0x12,
+  0x08, 0xc2, 0x90, 0x04, 0x11, 0xe0, 0x60, 0x2f, 0x64, 0x01, 0x70, 0x03,
+  0x02, 0x08, 0x29, 0x90, 0x04, 0x11, 0xe0, 0xb4, 0x02, 0x03, 0x02, 0x38,
+  0xed, 0x90, 0x04, 0x11, 0xe0, 0xb4, 0x03, 0x03, 0x02, 0x33, 0x75, 0x90,
+  0x04, 0x11, 0xe0, 0xb4, 0x04, 0x03, 0x02, 0x17, 0x1f, 0x90, 0x04, 0x11,
+  0xe0, 0xb4, 0x05, 0x03, 0x02, 0x42, 0xc9, 0x90, 0x00, 0x5f, 0xe0, 0x64,
+  0x03, 0x60, 0x19, 0x7f, 0xa2, 0x12, 0x60, 0x3f, 0xef, 0x54, 0x0f, 0x60,
+  0x0f, 0x75, 0xa5, 0x0c, 0x75, 0xa6, 0xff, 0x75, 0xa7, 0xf3, 0x75, 0x9e,
+  0xd1, 0x75, 0x9c, 0x18, 0xe4, 0x90, 0x04, 0x48, 0xf0, 0x12, 0x2e, 0xa9,
+  0x20, 0xe0, 0x53, 0x90, 0x04, 0x00, 0xe0, 0xc3, 0x13, 0x30, 0xe0, 0x4a,
+  0x90, 0x04, 0x83, 0xe0, 0xd3, 0x94, 0x03, 0x40, 0x41, 0x90, 0x04, 0x89,
+  0xe0, 0x60, 0x3b, 0x12, 0x08, 0x90, 0x70, 0x36, 0x12, 0x5c, 0x2f, 0xa8,
+  0x04, 0xa9, 0x05, 0xaa, 0x06, 0xc3, 0x74, 0xff, 0x9f, 0xf5, 0x0d, 0x74,
+  0xff, 0x9a, 0xf5, 0x0c, 0x74, 0xff, 0x99, 0xf5, 0x0b, 0x74, 0xff, 0x98,
+  0xf5, 0x0a, 0x7f, 0x60, 0x7e, 0xea, 0x7d, 0xff, 0x7c, 0xff, 0xf8, 0x12,
+  0x2f, 0x2b, 0x40, 0x0a, 0x7d, 0x02, 0x7f, 0x1e, 0x12, 0x3a, 0xfb, 0x02,
+  0x03, 0xee, 0x90, 0x04, 0x84, 0xe0, 0x70, 0x0d, 0x90, 0x04, 0x83, 0xe0,
+  0x60, 0x07, 0x7d, 0x02, 0x7f, 0x03, 0x12, 0x3a, 0xfb, 0x90, 0x04, 0x83,
+  0xe0, 0x14, 0x70, 0x03, 0x02, 0x02, 0xc8, 0x04, 0x60, 0x03, 0x02, 0x03,
+  0x53, 0x90, 0x04, 0x84, 0xe0, 0x60, 0x07, 0x7d, 0x02, 0x7f, 0x01, 0x12,
+  0x3a, 0xfb, 0x7f, 0x89, 0x12, 0x60, 0x3f, 0xef, 0x54, 0x07, 0xc3, 0x13,
+  0xff, 0x14, 0x60, 0x13, 0x04, 0x60, 0x03, 0x02, 0x02, 0x47, 0x90, 0x04,
+  0x3f, 0xe0, 0x60, 0x03, 0x12, 0x5c, 0x86, 0x12, 0x2e, 0xe9, 0x22, 0x12,
+  0x08, 0xa8, 0x70, 0x17, 0x75, 0xa4, 0x04, 0x12, 0x2e, 0x16, 0x75, 0x9c,
+  0x18, 0x7f, 0x0d, 0x7e, 0x00, 0x7d, 0x00, 0x7c, 0x00, 0x12, 0x5b, 0xa4,
+  0x02, 0x5e, 0xc9, 0x12, 0x08, 0xa8, 0x64, 0x01, 0x70, 0x0f, 0x12, 0x60,
+  0x0e, 0xef, 0x70, 0x03, 0x02, 0x08, 0x29, 0x12, 0x2e, 0x13, 0x75, 0x9c,
+  0x18, 0x7f, 0x86, 0x12, 0x60, 0x3f, 0xef, 0x54, 0x01, 0xf5, 0x09, 0x60,
+  0x3b, 0x12, 0x60, 0x45, 0x90, 0x04, 0x3c, 0xe0, 0x30, 0xe0, 0x01, 0x22,
+  0x12, 0x2e, 0xf6, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x86, 0x12, 0x53, 0x65,
+  0x75, 0xa4, 0x70, 0x75, 0xa6, 0x0f, 0x12, 0x2e, 0x19, 0x75, 0x9c, 0x12,
+  0x75, 0xa4, 0x90, 0x75, 0xa6, 0x0f, 0x12, 0x2e, 0x19, 0x75, 0x9c, 0x12,
+  0x75, 0xa4, 0x80, 0x75, 0xa6, 0x0f, 0x12, 0x2e, 0x19, 0x75, 0x9c, 0x12,
+  0x12, 0x2e, 0xb3, 0x75, 0x9a, 0x85, 0x12, 0x5c, 0x86, 0x90, 0x04, 0x01,
+  0xe0, 0x30, 0xe0, 0x03, 0x12, 0x59, 0x1e, 0x12, 0x08, 0x45, 0x7d, 0x02,
+  0x12, 0x08, 0x2a, 0x7d, 0x02, 0x7f, 0x02, 0x12, 0x3a, 0xfb, 0x12, 0x27,
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+  0xff, 0x64, 0x01, 0x22, 0xa3, 0xe0, 0x90, 0x04, 0x4e, 0xf0, 0x90, 0x04,
+  0x62, 0xe0, 0x90, 0x04, 0x4d, 0xf0, 0x90, 0x04, 0x1c, 0xe0, 0xff, 0xa3,
+  0xe0, 0xa3, 0xcf, 0xf0, 0xa3, 0xef, 0xf0, 0x22, 0xef, 0x54, 0x3f, 0x13,
+  0x13, 0x13, 0x54, 0x1f, 0x22, 0xad, 0x07, 0x75, 0xa4, 0x01, 0xd3, 0xed,
+  0x64, 0x80, 0x94, 0x80, 0x22, 0xe0, 0xff, 0x90, 0x04, 0x24, 0xe0, 0xfc,
+  0xa3, 0xe0, 0xfd, 0x22, 0x90, 0x04, 0x0f, 0xe0, 0x13, 0x13, 0x13, 0x54,
+  0x1f, 0x22, 0xce, 0xa2, 0xe7, 0x13, 0xce, 0x13, 0x22, 0xaf, 0x16, 0xef,
+  0x33, 0x95, 0xe0, 0xef, 0xf5, 0xa4, 0x75, 0xa6, 0xc0, 0x22, 0x90, 0x04,
+  0x50, 0xe0, 0xff, 0xd3, 0x64, 0x80, 0x94, 0x80, 0x22, 0x90, 0x04, 0x53,
+  0xe0, 0xff, 0x90, 0x04, 0x56, 0xe0, 0xd3, 0x9f, 0x22, 0xef, 0xfd, 0xed,
+  0x54, 0x7f, 0xf5, 0xa4, 0x74, 0x08, 0xf5, 0xa5, 0x75, 0xa6, 0x80, 0x75,
+  0xa7, 0xf7, 0x75, 0x9a, 0x04, 0x22, 0x90, 0x04, 0x53, 0xf0, 0x90, 0x04,
+  0x20, 0xf0, 0xa3, 0xf0, 0x90, 0x04, 0x20, 0xf0, 0xa3, 0xf0, 0x22, 0xe4,
+  0xf5, 0xa5, 0x75, 0xa6, 0xff, 0x75, 0xa7, 0xfb, 0x75, 0x9a, 0x04, 0x22,
+  0xff, 0xee, 0x90, 0x04, 0x24, 0xf0, 0xa3, 0xef, 0xf0, 0x22, 0xe4, 0xf5,
+  0xa4, 0x75, 0xa5, 0x04, 0x75, 0xa6, 0xff, 0x75, 0xa7, 0x93, 0x22, 0xe5,
+  0x12, 0x25, 0xe0, 0xff, 0xe5, 0x11, 0x33, 0xfe, 0x22, 0x75, 0xa5, 0x02,
+  0x75, 0xa6, 0xff, 0x75, 0xa7, 0xf8, 0x75, 0x9a, 0x01, 0x22, 0xe0, 0xfe,
+  0xa3, 0xe0, 0xff, 0xc3, 0xe4, 0x9f, 0xff, 0xe4, 0x9e, 0xfe, 0x22, 0xef,
+  0xf0, 0x90, 0x04, 0x22, 0xa3, 0xe0, 0x22, 0x90, 0x04, 0x56, 0xe0, 0xc3,
+  0x94, 0x2a, 0x22, 0x90, 0x04, 0x57, 0x74, 0x1f, 0xf0, 0xff, 0x12, 0x5c,
+  0xfa, 0x90, 0x04, 0x1e, 0x74, 0x80, 0xf0, 0xa3, 0xe4, 0xf0, 0x22, 0xee,
+  0xc3, 0x64, 0x80, 0xf8, 0xef, 0x64, 0x80, 0x98, 0x22, 0xf4, 0xfc, 0xe0,
+  0x5c, 0xfc, 0xa3, 0xe0, 0x5d, 0xfd, 0xec, 0x4e, 0xfe, 0xed, 0x4f, 0xff,
+  0x22, 0x75, 0xa6, 0xf3, 0x75, 0xa7, 0x0f, 0x75, 0x9a, 0x30, 0x22, 0xef,
+  0x54, 0x1f, 0xff, 0x7e, 0x00, 0x22, 0xef, 0xf5, 0xa4, 0xc3, 0xed, 0x64,
+  0x80, 0x94, 0x80, 0x22, 0x75, 0xa4, 0x80, 0x75, 0xa6, 0x7f, 0x75, 0xa7,
+  0xff, 0x75, 0x9a, 0x10, 0x22, 0xe5, 0x18, 0xf0, 0xe5, 0x19, 0xa3, 0xf0,
+  0x90, 0x04, 0x62, 0xe0, 0x22, 0xe0, 0x90, 0x04, 0x1e, 0xfb, 0xe0, 0xf5,
+  0x1e, 0xa3, 0xe0, 0xf5, 0x1f, 0x22, 0xef, 0x25, 0xe0, 0x25, 0xe0, 0xf5,
+  0xa5, 0x75, 0xa6, 0xff, 0x75, 0xa7, 0x83, 0x75, 0x9a, 0x14, 0x22, 0xeb,
+  0x4f, 0xff, 0xea, 0x4e, 0xfe, 0xe9, 0x4d, 0xfd, 0xe8, 0x4c, 0xfc, 0xef,
+  0x24, 0xf1, 0x22, 0x90, 0x04, 0x50, 0xe0, 0xf4, 0x04, 0xff, 0x22, 0xef,
+  0x33, 0x33, 0x33, 0x54, 0xf8, 0xf0, 0x22, 0xef, 0x25, 0xe0, 0x24, 0x47,
+  0xf5, 0x82, 0xe4, 0x34, 0x62, 0xf5, 0x83, 0x74, 0x01, 0x93, 0x22, 0xff,
+  0xee, 0x55, 0x83, 0xfe, 0xef, 0x55, 0x82, 0xff, 0xe5, 0x82, 0xf4, 0xfd,
+  0xe5, 0x83, 0x22, 0x90, 0x04, 0x40, 0xf0, 0x7f, 0x00, 0x22, 0xff, 0xf0,
+  0x90, 0x04, 0x22, 0xe4, 0xf0, 0xa3, 0xef, 0xf0, 0x22, 0x12, 0x5e, 0xf5,
+  0x90, 0x04, 0x40, 0x22, 0xd3, 0x90, 0x04, 0x27, 0xe0, 0x94, 0xf8, 0x90,
+  0x04, 0x26, 0xe0, 0x64, 0x80, 0x94, 0x80, 0x22, 0x90, 0x04, 0x45, 0xe0,
+  0xff, 0x33, 0x95, 0xe0, 0xfe, 0x22, 0xee, 0xff, 0x33, 0x95, 0xe0, 0xef,
+  0x33, 0x95, 0xe0, 0xef, 0x75, 0xf0, 0xff, 0xa4, 0x22, 0x90, 0x04, 0x09,
+  0xe0, 0xff, 0x13, 0x13, 0x13, 0x54, 0x1f, 0x22, 0xfe, 0xf0, 0xa3, 0xef,
+  0xf0, 0xc3, 0xee, 0x64, 0x80, 0x94, 0x80, 0x22, 0x90, 0x04, 0x1c, 0xee,
+  0xf0, 0xa3, 0xef, 0xf0, 0x22, 0xc3, 0xef, 0x64, 0x80, 0xf8, 0xee, 0x64,
+  0x80, 0x98, 0x22, 0xfe, 0xee, 0xf5, 0xa5, 0xe4, 0xf5, 0xa6, 0x75, 0xa7,
+  0xf8, 0x75, 0x9a, 0x04, 0x22, 0x85, 0x12, 0x20, 0x85, 0x13, 0x21, 0x85,
+  0x11, 0x22, 0xad, 0x19, 0xac, 0x18, 0x22, 0xef, 0x54, 0x7f, 0xc4, 0x13,
+  0x13, 0x54, 0x03, 0x22, 0xf0, 0x90, 0x04, 0x4b, 0xe0, 0x04, 0xf0, 0x22,
+  0xef, 0x54, 0x0f, 0x13, 0x13, 0x54, 0x3f, 0xc3, 0x94, 0x02, 0xe4, 0x94,
+  0x00, 0x22, 0x90, 0x04, 0x20, 0xee, 0xf0, 0xa3, 0xef, 0xf0, 0x22, 0x90,
+  0x04, 0x40, 0xf0, 0x90, 0x04, 0x83, 0x74, 0xff, 0xf0, 0x22, 0x3e, 0x90,
+  0x04, 0x22, 0xf0, 0xa3, 0xef, 0xf0, 0x22, 0x90, 0x04, 0x62, 0x74, 0x01,
+  0xf0, 0x22, 0x90, 0x04, 0x4d, 0x74, 0x01, 0xf0, 0x22, 0xff, 0x33, 0x95,
+  0xe0, 0xfe, 0xef, 0x22, 0x8f, 0x82, 0x8e, 0x83, 0xaf, 0x05, 0xeb, 0xae,
+  0x02, 0xa8, 0x07, 0x08, 0x22, 0xd3, 0x64, 0x80, 0xf8, 0xed, 0x64, 0x80,
+  0x98, 0x22, 0x90, 0x04, 0x4c, 0xe0, 0x64, 0x01, 0x22, 0x90, 0x04, 0x29,
+  0xe0, 0x2f, 0xf0, 0x90, 0x04, 0x28, 0xe0, 0x3e, 0xf0, 0x22, 0x90, 0x04,
+  0x6d, 0xe0, 0xff, 0x90, 0x04, 0x50, 0xe0, 0x2f, 0xff, 0x22, 0xfe, 0x90,
+  0x00, 0x57, 0xe0, 0x9f, 0x90, 0x00, 0x56, 0xe0, 0x9e, 0x22, 0x64, 0x80,
+  0xf8, 0xeb, 0x64, 0x80, 0x98, 0x22, 0xd3, 0xe5, 0x82, 0x94, 0x00, 0xe5,
+  0x83, 0x64, 0x80, 0x94, 0x80, 0x22, 0xd3, 0xe5, 0x1f, 0x94, 0x00, 0xe5,
+  0x1e, 0x64, 0x80, 0x94, 0x80, 0x22, 0x90, 0x04, 0x60, 0xe0, 0xfb, 0x7a,
+  0x00, 0x22, 0xff, 0xe0, 0xc3, 0x9f, 0xf5, 0x10, 0xd3, 0x64, 0x80, 0x94,
+  0x78, 0x22, 0xee, 0x54, 0x03, 0x90, 0x04, 0x1e, 0xf0, 0xa3, 0xef, 0xf0,
+  0x22, 0x2f, 0x25, 0xe0, 0xa2, 0xe7, 0x13, 0xff, 0xe4, 0xf5, 0xa4, 0x22,
+  0xc3, 0xe5, 0x1b, 0x64, 0x80, 0x94, 0x80, 0x22, 0x74, 0x04, 0xf5, 0xa5,
+  0x75, 0xa6, 0xfd, 0x75, 0xa7, 0x93, 0x22, 0x90, 0x04, 0x07, 0xe0, 0xfe,
+  0x13, 0x13, 0x13, 0x54, 0x1f, 0x22, 0x75, 0xa6, 0x7f, 0x75, 0xa7, 0xfc,
+  0x75, 0x9a, 0x04, 0x22, 0xe4, 0xf5, 0xa4, 0xf5, 0xa5, 0xf5, 0xa6, 0xf5,
+  0xa7, 0x22, 0xc3, 0xe4, 0x95, 0x82, 0xff, 0xe4, 0x95, 0x83, 0xfe, 0x22,
+  0xc3, 0xe4, 0x95, 0x1f, 0xff, 0xe4, 0x95, 0x1e, 0xfe, 0x22, 0xcf, 0x24,
+  0x01, 0xcf, 0x34, 0x00, 0xa2, 0xe7, 0x13, 0x22, 0x75, 0xa4, 0x01, 0x75,
+  0xa6, 0xfe, 0x22, 0x75, 0xa7, 0x8b, 0x75, 0x9a, 0x30, 0x22, 0xef, 0x54,
+  0x3f, 0xc4, 0x13, 0x54, 0x07, 0x64, 0x01, 0x22, 0xe5, 0x17, 0x25, 0xe0,
+  0xff, 0xe5, 0x16, 0x33, 0xfe, 0x22, 0xe5, 0x10, 0x64, 0x80, 0x94, 0x80,
+  0x22, 0x90, 0x04, 0x20, 0xe0, 0xfe, 0xa3, 0x22, 0x90, 0x04, 0x28, 0xf0,
+  0xa3, 0xf0, 0x22, 0x90, 0x04, 0x40, 0xf0, 0x7f, 0x00, 0x22, 0x90, 0x04,
+  0x52, 0xe0, 0xc3, 0x64, 0x80, 0x94, 0x80, 0x22, 0x90, 0x04, 0x77, 0xf0,
+  0xe5, 0x31, 0x25, 0xe0, 0x24, 0x9b, 0xf5, 0x82, 0xe4, 0x34, 0x63, 0xf5,
+  0x83, 0xe4, 0x93, 0x22, 0x90, 0x04, 0x38, 0xe0, 0xfe, 0xa3, 0xe0, 0xff,
+  0xe4, 0xfc, 0xfd, 0x78, 0x10, 0x12, 0x2b, 0xc9, 0xa8, 0x04, 0xa9, 0x05,
+  0xaa, 0x06, 0xab, 0x07, 0xa3, 0xe0, 0xfe, 0xa3, 0xe0, 0xff, 0xeb, 0x4f,
+  0x22, 0x90, 0x04, 0x38, 0xf0, 0xa3, 0xf0, 0xa3, 0xf0, 0xa3, 0xf0, 0x22,
+  0xfe, 0x74, 0x01, 0x93, 0x90, 0x04, 0x77, 0xff, 0xe0, 0xfd, 0x7c, 0x00,
+  0xef, 0x2d, 0xff, 0xec, 0x3e, 0xfe, 0x74, 0x00, 0x2f, 0xf5, 0x82, 0x74,
+  0x01, 0x3e, 0xf5, 0x83, 0x22, 0xee, 0x33, 0x95, 0xe0, 0xfd, 0xfc, 0x78,
+  0x0a, 0x02, 0x2b, 0xc9, 0xfc, 0x74, 0x01, 0x93, 0xfd, 0x90, 0x04, 0x77,
+  0xe0, 0xfe, 0xfb, 0x7a, 0x00, 0xed, 0x2b, 0xfd, 0xea, 0x3c, 0xfc, 0x74,
+  0x00, 0x2d, 0xf5, 0x82, 0x74, 0x01, 0x3c, 0xf5, 0x83, 0xef, 0xf0, 0x22,
+  0xe4, 0x90, 0x00, 0x5a, 0xf0, 0xa3, 0xf0, 0x90, 0x00, 0x58, 0xf0, 0xa3,
+  0xf0, 0x7e, 0x02, 0x7f, 0xf8, 0xfd, 0x7b, 0x01, 0x7a, 0x01, 0x79, 0x00,
+  0x02, 0x2c, 0x16, 0xe4, 0xf5, 0xa4, 0xf5, 0xa5, 0x75, 0xa6, 0xc0, 0x22,
+  0xef, 0x54, 0x3f, 0xff, 0x7e, 0x00, 0x7d, 0x20, 0x7c, 0x00, 0x22, 0x90,
+  0x00, 0x65, 0x74, 0x01, 0xf0, 0x90, 0x04, 0x11, 0xe0, 0xd3, 0x94, 0x00,
+  0x22, 0xe4, 0xf5, 0xa4, 0x75, 0xa6, 0xdf, 0x75, 0xa7, 0xff, 0x75, 0x9a,
+  0x11, 0x22, 0x7f, 0xf1, 0x12, 0x60, 0x16, 0xef, 0x33, 0x95, 0xe0, 0xef,
+  0xf5, 0xa4, 0x75, 0xa6, 0xc0, 0x22, 0x75, 0xa5, 0x10, 0x75, 0xa6, 0xff,
+  0x75, 0xa7, 0xef, 0x75, 0x9a, 0x04, 0x22, 0x90, 0x04, 0x17, 0xe0, 0x54,
+  0x01, 0xd3, 0x94, 0x00, 0x22, 0x90, 0x04, 0x00, 0xe0, 0xfe, 0xa3, 0xe0,
+  0x78, 0x02, 0x22, 0xf5, 0xa5, 0x75, 0xa6, 0xf6, 0x75, 0xa7, 0xff, 0x75,
+  0x9a, 0x40, 0x22, 0x90, 0x04, 0x24, 0xe0, 0xfe, 0xa3, 0xe0, 0xff, 0xc3,
+  0x94, 0xf0, 0xee, 0x64, 0x80, 0x94, 0x7f, 0x22, 0xe4, 0xf5, 0xa4, 0xf5,
+  0xa5, 0x75, 0xa6, 0xff, 0x22, 0xfe, 0xef, 0x25, 0xe0, 0xff, 0xee, 0x33,
+  0xfe, 0xef, 0x24, 0x02, 0xff, 0xe4, 0x3e, 0x90, 0x04, 0x24, 0xf0, 0xa3,
+  0xef, 0xf0, 0x22, 0x75, 0x10, 0x00, 0xf5, 0x11, 0xf5, 0xa4, 0xe5, 0x10,
+  0xf5, 0xa5, 0x22, 0x90, 0x00, 0x61, 0xe0, 0xff, 0xe4, 0xfc, 0xfd, 0xfe,
+  0x12, 0x2b, 0xc9, 0xab, 0x25, 0xaa, 0x24, 0xa9, 0x23, 0xa8, 0x22, 0xd3,
+  0x02, 0x2b, 0xa5, 0xff, 0xea, 0x4e, 0xfe, 0xe9, 0xfd, 0xe8, 0xfc, 0xef,
+  0x25, 0x13, 0xff, 0xee, 0x35, 0x12, 0xfe, 0xed, 0x35, 0x11, 0xfd, 0xec,
+  0x35, 0x10, 0xfc, 0x22, 0xe4, 0xf5, 0xa4, 0xf5, 0xa5, 0xf5, 0xa6, 0xf5,
+  0xa7, 0x22, 0xfc, 0xab, 0x26, 0xaa, 0x25, 0xa9, 0x24, 0xa8, 0x23, 0x02,
+  0x2b, 0xa5, 0x90, 0x04, 0x78, 0xe0, 0x64, 0x80, 0xf8, 0xef, 0x64, 0x80,
+  0x98, 0x22, 0x75, 0xa4, 0x20, 0x75, 0xa6, 0xdf, 0x75, 0xa7, 0xff, 0x75,
+  0x9a, 0x10, 0x22, 0xe4, 0xf5, 0xa4, 0xf5, 0xa5, 0x75, 0xa6, 0xfe, 0x75,
+  0xa7, 0xff, 0x22, 0x90, 0x04, 0x11, 0xe0, 0xff, 0xd3, 0x94, 0x01, 0x22,
+  0x90, 0x04, 0x24, 0xe0, 0xfe, 0xa3, 0xe0, 0xf5, 0xa4, 0xee, 0xf5, 0xa5,
+  0x22, 0x90, 0x04, 0x24, 0x74, 0xff, 0xf0, 0xa3, 0x74, 0xe1, 0xf0, 0x22,
+  0xc3, 0x90, 0x04, 0x27, 0xe0, 0x94, 0x04, 0x90, 0x04, 0x26, 0xe0, 0x64,
+  0x80, 0x94, 0x80, 0x7d, 0x00, 0x22, 0x90, 0x04, 0x26, 0xe0, 0xfe, 0xa3,
+  0xe0, 0xff, 0xc3, 0x94, 0x04, 0xee, 0x64, 0x80, 0x94, 0x80, 0x22, 0xfe,
+  0xfd, 0xfc, 0xab, 0x14, 0xaa, 0x13, 0xa9, 0x12, 0xa8, 0x11, 0xc3, 0x02,
+  0x2b, 0xa5, 0xd3, 0xef, 0x94, 0x0f, 0xee, 0x64, 0x80, 0x94, 0x80, 0x22,
+  0xc3, 0x90, 0x04, 0x25, 0xe0, 0x94, 0x1f, 0x90, 0x04, 0x24, 0xe0, 0x64,
+  0x80, 0x94, 0x80, 0x22, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x43, 0x22, 0x75,
+  0xa7, 0xff, 0x75, 0x9a, 0x44, 0x22, 0x90, 0x04, 0x26, 0xe0, 0xa2, 0xe7,
+  0x13, 0xa3, 0xe0, 0x13, 0x54, 0x01, 0xff, 0x7d, 0x01, 0x22, 0x90, 0x04,
+  0x49, 0xe0, 0xd3, 0x94, 0x01, 0x22, 0x90, 0x04, 0x4e, 0xe0, 0xd3, 0x64,
+  0x80, 0x94, 0x80, 0x22, 0xfa, 0x12, 0x2b, 0x30, 0x75, 0x11, 0x00, 0xf5,
+  0x10, 0x22, 0x7e, 0x00, 0x7d, 0x00, 0x7b, 0x01, 0x02, 0x2c, 0x16, 0x4f,
+  0x90, 0x04, 0x14, 0xff, 0xee, 0xf0, 0xa3, 0xef, 0xf0, 0x22, 0xaf, 0x16,
+  0xef, 0x33, 0x95, 0xe0, 0xfe, 0xef, 0x22, 0xef, 0x24, 0xff, 0xff, 0xee,
+  0x34, 0xff, 0xfe, 0x22, 0xe4, 0xf5, 0xa4, 0xf5, 0xa5, 0x75, 0xa6, 0xfd,
+  0x22, 0x90, 0x00, 0x65, 0xe0, 0xc4, 0x54, 0xf0, 0x44, 0xc0, 0xfe, 0xef,
+  0x4e, 0xff, 0x22, 0x90, 0x04, 0x4e, 0xef, 0xf0, 0x90, 0x04, 0x11, 0x22,
+  0xef, 0xfe, 0xee, 0xf5, 0xa5, 0xe4, 0xf5, 0xa6, 0xf5, 0xa7, 0x75, 0x9a,
+  0x0d, 0x22, 0x54, 0x80, 0xfc, 0xe4, 0xfb, 0xfa, 0xf9, 0xf8, 0xc3, 0x02,
+  0x2b, 0xa5, 0x75, 0xa5, 0x04, 0x75, 0xa6, 0xff, 0x22, 0x75, 0xa5, 0x08,
+  0x75, 0xa6, 0xff, 0x22, 0x90, 0x04, 0x24, 0xe4, 0xf0, 0xa3, 0x22, 0x75,
+  0xa5, 0x02, 0x75, 0xa6, 0xff, 0x22, 0xab, 0x27, 0xaa, 0x28, 0xa9, 0x29,
+  0x22, 0xab, 0x13, 0xaa, 0x12, 0xa9, 0x11, 0xa8, 0x10, 0xd3, 0x02, 0x2b,
+  0xa5, 0x90, 0x04, 0x77, 0xf0, 0x90, 0x04, 0x16, 0xf0, 0x22, 0x90, 0x04,
+  0x17, 0xe0, 0xc4, 0x54, 0x03, 0x22, 0x90, 0x00, 0x50, 0xe0, 0xc3, 0x13,
+  0xa3, 0xe0, 0x13, 0x54, 0x1f, 0x22, 0x90, 0x04, 0x15, 0xe0, 0xc3, 0x94,
+  0xfb, 0xe4, 0x94, 0x00, 0x22, 0xe4, 0x90, 0x04, 0x14, 0xf0, 0xa3, 0xf0,
+  0x22, 0x90, 0x04, 0x17, 0xe0, 0xff, 0x54, 0x02, 0xd3, 0x94, 0x00, 0x22,
+  0x90, 0x04, 0x26, 0xa3, 0xe0, 0x54, 0x01, 0xff, 0xe4, 0xfd, 0x22, 0xfc,
+  0x74, 0x01, 0x93, 0xfd, 0x90, 0x04, 0x77, 0xe0, 0x22, 0x75, 0xa7, 0xfb,
+  0x75, 0x9a, 0xd1, 0x22, 0xe4, 0xff, 0xfe, 0xfd, 0xe5, 0x23, 0x22, 0x12,
+  0x60, 0x25, 0x90, 0x04, 0x79, 0x22, 0x90, 0x04, 0x3f, 0x74, 0x01, 0xf0,
+  0x22, 0x24, 0x00, 0xf9, 0xec, 0x34, 0x04, 0x22, 0x24, 0x00, 0xf9, 0xec,
+  0x34, 0x04, 0x22, 0xe4, 0xf5, 0x18, 0x90, 0x04, 0x14, 0xe0, 0x30, 0xe7,
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+  0x4d, 0xf0, 0xe5, 0x10, 0xb4, 0x01, 0x1f, 0xe5, 0x14, 0xb5, 0x16, 0x15,
+  0xc3, 0xe5, 0x13, 0x94, 0xff, 0xe5, 0x12, 0x64, 0x80, 0x94, 0x7f, 0x50,
+  0x08, 0x90, 0x04, 0x7c, 0x74, 0x01, 0xf0, 0x80, 0x05, 0xe4, 0x90, 0x04,
+  0x7c, 0xf0, 0xad, 0x14, 0xaf, 0x10, 0x12, 0x30, 0xe1, 0x90, 0x04, 0x1e,
+  0xe5, 0x12, 0xf0, 0xa3, 0xe5, 0x13, 0xf0, 0x90, 0x04, 0x4f, 0xe0, 0x90,
+  0x04, 0x4e, 0x12, 0x12, 0x4c, 0x22, 0xc2, 0xd5, 0x30, 0xf7, 0x07, 0xb2,
+  0xd5, 0x63, 0xf0, 0xff, 0x05, 0xf0, 0x30, 0xe7, 0x0c, 0xb2, 0xd5, 0xf4,
+  0x04, 0x84, 0x63, 0xf0, 0xff, 0x05, 0xf0, 0x80, 0x01, 0x84, 0x30, 0xd5,
+  0x02, 0xf4, 0x04, 0x22, 0xbb, 0x01, 0x06, 0x89, 0x82, 0x8a, 0x83, 0xe0,
+  0x22, 0x50, 0x02, 0xe7, 0x22, 0xbb, 0xfe, 0x02, 0xe3, 0x22, 0x89, 0x82,
+  0x8a, 0x83, 0xe4, 0x93, 0x22, 0xbb, 0x01, 0x09, 0x89, 0x82, 0x8a, 0x83,
+  0xf8, 0xe0, 0x28, 0xf0, 0x22, 0x50, 0x03, 0x27, 0xf7, 0x22, 0xbb, 0xfe,
+  0x05, 0xf8, 0xe3, 0x28, 0xf3, 0x22, 0x8a, 0x83, 0x89, 0x82, 0xf8, 0xe4,
+  0x93, 0x28, 0x22, 0xbb, 0x01, 0x06, 0x89, 0x82, 0x8a, 0x83, 0xf0, 0x22,
+  0x50, 0x02, 0xf7, 0x22, 0xbb, 0xfe, 0x01, 0xf3, 0x22, 0xef, 0x8d, 0xf0,
+  0xa4, 0xa8, 0xf0, 0xcf, 0x8c, 0xf0, 0xa4, 0x28, 0xce, 0x8d, 0xf0, 0xa4,
+  0x2e, 0xfe, 0x22, 0xeb, 0x9f, 0xf5, 0xf0, 0xea, 0x9e, 0x42, 0xf0, 0xe9,
+  0x9d, 0x42, 0xf0, 0xec, 0x64, 0x80, 0xc8, 0x64, 0x80, 0x98, 0x45, 0xf0,
+  0x22, 0xeb, 0x9f, 0xf5, 0xf0, 0xea, 0x9e, 0x42, 0xf0, 0xe9, 0x9d, 0x42,
+  0xf0, 0xe8, 0x9c, 0x45, 0xf0, 0x22, 0xe8, 0x60, 0x0f, 0xec, 0xc3, 0x13,
+  0xfc, 0xed, 0x13, 0xfd, 0xee, 0x13, 0xfe, 0xef, 0x13, 0xff, 0xd8, 0xf1,
+  0x22, 0xe8, 0x60, 0x0f, 0xef, 0xc3, 0x33, 0xff, 0xee, 0x33, 0xfe, 0xed,
+  0x33, 0xfd, 0xec, 0x33, 0xfc, 0xd8, 0xf1, 0x22, 0xbb, 0x01, 0x07, 0x89,
+  0x82, 0x8a, 0x83, 0x02, 0x2c, 0x4e, 0x50, 0x05, 0xe9, 0xf8, 0x02, 0x2c,
+  0x42, 0xbb, 0xfe, 0x05, 0xe9, 0xf8, 0x02, 0x2c, 0x5a, 0x89, 0x82, 0x8a,
+  0x83, 0x02, 0x2c, 0x66, 0xbb, 0x01, 0x07, 0x89, 0x82, 0x8a, 0x83, 0x02,
+  0x2c, 0x82, 0x50, 0x05, 0xe9, 0xf8, 0x02, 0x2c, 0x76, 0xbb, 0xfe, 0x05,
+  0xe9, 0xf8, 0x02, 0x2c, 0x8e, 0x22, 0xef, 0x4e, 0x60, 0x12, 0xef, 0x60,
+  0x01, 0x0e, 0xed, 0xbb, 0x01, 0x0b, 0x89, 0x82, 0x8a, 0x83, 0xf0, 0xa3,
+  0xdf, 0xfc, 0xde, 0xfa, 0x22, 0x89, 0xf0, 0x50, 0x07, 0xf7, 0x09, 0xdf,
+  0xfc, 0xa9, 0xf0, 0x22, 0xbb, 0xfe, 0xfc, 0xf3, 0x09, 0xdf, 0xfc, 0xa9,
+  0xf0, 0x22, 0xe6, 0xfc, 0x08, 0xe6, 0xfd, 0x08, 0xe6, 0xfe, 0x08, 0xe6,
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+  0xff, 0x22, 0xe2, 0xfc, 0x08, 0xe2, 0xfd, 0x08, 0xe2, 0xfe, 0x08, 0xe2,
+  0xff, 0x22, 0xe4, 0x93, 0xfc, 0x74, 0x01, 0x93, 0xfd, 0x74, 0x02, 0x93,
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+  0xee, 0xf0, 0xa3, 0xef, 0xf0, 0x22, 0xec, 0xf2, 0x08, 0xed, 0xf2, 0x08,
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+  0xff, 0x75, 0xa7, 0x83, 0x75, 0x9a, 0x14, 0x75, 0xa4, 0x0d, 0xe4, 0xf5,
+  0xa5, 0x75, 0xa6, 0xe0, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x15, 0x75, 0xa4,
+  0x0d, 0xe4, 0xf5, 0xa5, 0x75, 0xa6, 0xf0, 0x75, 0xa7, 0xfc, 0x75, 0x9a,
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+  0xd8, 0x75, 0xa7, 0x13, 0x75, 0x9a, 0x25, 0x12, 0x14, 0x5b, 0x75, 0xa7,
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+  0xa7, 0x40, 0x75, 0x9a, 0x2b, 0xe4, 0xf5, 0xa4, 0xf5, 0xa5, 0x75, 0xa6,
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+  0x31, 0x12, 0x15, 0x34, 0x75, 0x9a, 0x32, 0x12, 0x15, 0x34, 0x75, 0x9a,
+  0x33, 0xe4, 0xf5, 0xa4, 0x12, 0x14, 0xbb, 0xe4, 0xf5, 0xa4, 0xf5, 0xa5,
+  0x75, 0xa6, 0xf0, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x41, 0xe4, 0xf5, 0xa4,
+  0xf5, 0xa5, 0x75, 0xa6, 0xf8, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x42, 0x12,
+  0x14, 0x5b, 0x12, 0x15, 0xdc, 0x12, 0x14, 0x5b, 0x12, 0x15, 0xe3, 0x12,
+  0x14, 0x5b, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x45, 0x12, 0x14, 0x5b, 0x75,
+  0xa7, 0xff, 0x75, 0x9a, 0x46, 0x12, 0x14, 0x5b, 0x75, 0xa7, 0xff, 0x75,
+  0x9a, 0x47, 0x12, 0x14, 0x5b, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x48, 0xe4,
+  0xf5, 0xa4, 0xf5, 0xa5, 0x75, 0xa6, 0x80, 0x75, 0xa7, 0xff, 0x75, 0x9a,
+  0x49, 0x12, 0x16, 0x3c, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x51, 0x12, 0x15,
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+  0xa4, 0x50, 0x75, 0xa6, 0x03, 0x75, 0xa7, 0xff, 0x75, 0x9e, 0xd1, 0x22,
+  0x74, 0xf8, 0x25, 0x1c, 0xf5, 0x82, 0xe4, 0x34, 0x03, 0xf5, 0x83, 0xe0,
+  0xff, 0x74, 0x00, 0x25, 0x1c, 0xf5, 0x82, 0xe4, 0x34, 0x01, 0xf5, 0x83,
+  0xef, 0xf0, 0x22, 0xae, 0x15, 0xaf, 0x16, 0xee, 0xc4, 0xf8, 0x54, 0xf0,
+  0xc8, 0xef, 0xc4, 0x54, 0x0f, 0x48, 0x54, 0x03, 0x22, 0x75, 0xa4, 0x01,
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+  0x04, 0x00, 0xe0, 0xfe, 0xa3, 0xe0, 0x22, 0x54, 0xfe, 0xf0, 0x90, 0x00,
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+  0xa7, 0xff, 0x75, 0x9a, 0x10, 0x22, 0xf5, 0x83, 0x74, 0xff, 0xf0, 0x90,
+  0x00, 0x66, 0xe0, 0xfc, 0xa3, 0xe0, 0xfd, 0xec, 0xff, 0x74, 0x01, 0x22,
+  0xe5, 0x1a, 0x24, 0x08, 0xff, 0xe5, 0x19, 0x34, 0xfd, 0xfe, 0xc3, 0xe5,
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+  0x75, 0xa6, 0xff, 0x75, 0xa7, 0xef, 0x75, 0x9a, 0x10, 0x22, 0xe4, 0xf5,
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+  0xff, 0xf5, 0x15, 0xed, 0x34, 0xff, 0xf5, 0x14, 0xec, 0x34, 0xff, 0xf5,
+  0x13, 0x7f, 0x38, 0x12, 0x5f, 0xed, 0x12, 0x12, 0x14, 0x7f, 0x39, 0x12,
+  0x5f, 0xed, 0x12, 0x13, 0x0a, 0x12, 0x0f, 0x3c, 0x12, 0x11, 0x7b, 0xf5,
+  0x1a, 0xee, 0x34, 0xff, 0xf5, 0x19, 0xed, 0x34, 0xff, 0xf5, 0x18, 0xec,
+  0x34, 0xff, 0xf5, 0x17, 0x90, 0x04, 0x4f, 0x12, 0x10, 0x69, 0x40, 0x02,
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+  0xf0, 0x90, 0x04, 0x53, 0xe0, 0x04, 0xf0, 0x90, 0x04, 0x53, 0xe0, 0xd3,
+  0x94, 0x05, 0x50, 0x11, 0x12, 0x0f, 0x88, 0xe4, 0xf5, 0x2a, 0xa3, 0xe0,
+  0xff, 0x12, 0x45, 0x01, 0x8f, 0x1b, 0xe4, 0x80, 0x1b, 0x90, 0x04, 0x53,
+  0xe0, 0xd3, 0x94, 0x07, 0x50, 0x18, 0x12, 0x0f, 0x88, 0x75, 0x2a, 0x01,
+  0xa3, 0xe0, 0xff, 0x12, 0x45, 0x01, 0x8f, 0x1b, 0x90, 0x04, 0x62, 0xe0,
+  0x90, 0x04, 0x4d, 0xf0, 0x80, 0x09, 0x90, 0x04, 0x50, 0xe0, 0xf5, 0x1b,
+  0x12, 0x12, 0x86, 0x90, 0x04, 0x50, 0xe0, 0xa3, 0xf0, 0x90, 0x04, 0x50,
+  0xe5, 0x1b, 0xf0, 0xe5, 0x10, 0x60, 0x03, 0xb4, 0x01, 0x0a, 0x90, 0x04,
+  0x50, 0xe0, 0xff, 0x12, 0x5c, 0xfa, 0x80, 0x06, 0x12, 0x12, 0xbe, 0x12,
+  0x56, 0x0e, 0x90, 0x04, 0x4d, 0xe0, 0x64, 0x01, 0x70, 0x5c, 0xe5, 0x10,
+  0x70, 0x12, 0x12, 0x10, 0x66, 0x40, 0x02, 0x80, 0x03, 0x12, 0x11, 0x8b,
+  0x90, 0x04, 0x0f, 0x12, 0x11, 0x93, 0x80, 0x46, 0xe5, 0x10, 0xb4, 0x01,
+  0x12, 0x12, 0x10, 0x66, 0x40, 0x02, 0x80, 0x03, 0x12, 0x11, 0x8b, 0x90,
+  0x04, 0x10, 0x12, 0x11, 0x93, 0x80, 0x2f, 0xe5, 0x10, 0xb4, 0x02, 0x16,
+  0x12, 0x10, 0x66, 0x40, 0x02, 0x80, 0x03, 0x12, 0x11, 0x8b, 0xef, 0x33,
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+  0x46, 0xd3, 0xed, 0x64, 0x80, 0x94, 0xbf, 0x40, 0x06, 0xed, 0x24, 0xc1,
+  0xff, 0x80, 0x02, 0x7f, 0x00, 0xac, 0x07, 0xec, 0x12, 0x0f, 0x66, 0x44,
+  0x04, 0x12, 0x0e, 0xc7, 0x12, 0x0e, 0xbd, 0x75, 0x9a, 0x2b, 0xec, 0x12,
+  0x0f, 0x65, 0x44, 0x06, 0x12, 0x0e, 0xc7, 0x12, 0x0e, 0xbd, 0x75, 0x9a,
+  0x2b, 0xec, 0xff, 0x33, 0x95, 0xe0, 0xfe, 0xed, 0xfb, 0x33, 0x95, 0xe0,
+  0xfa, 0xc3, 0xeb, 0x9f, 0xff, 0xea, 0x9e, 0x12, 0x0f, 0x69, 0x44, 0x02,
+  0x12, 0x0e, 0xc7, 0x02, 0x32, 0x36, 0x12, 0x10, 0x36, 0x40, 0x04, 0xaf,
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+  0xac, 0x07, 0xec, 0x12, 0x0f, 0x66, 0x44, 0x0a, 0x12, 0x0e, 0xc7, 0x12,
+  0x0e, 0xbd, 0x75, 0x9a, 0x2b, 0xec, 0x12, 0x0f, 0x65, 0x44, 0x0c, 0x12,
+  0x0e, 0xc7, 0x12, 0x0e, 0xbd, 0x75, 0x9a, 0x2b, 0x12, 0x10, 0x36, 0x40,
+  0x04, 0xaf, 0x05, 0x80, 0x04, 0xed, 0xf4, 0x04, 0xff, 0xef, 0x33, 0x95,
+  0xe0, 0xec, 0xfb, 0x33, 0x95, 0xe0, 0xfa, 0xc3, 0xef, 0x9b, 0xff, 0xef,
+  0xf5, 0xa4, 0x12, 0x10, 0x36, 0x40, 0x04, 0xaf, 0x05, 0x80, 0x04, 0xed,
+  0xf4, 0x04, 0xff, 0xef, 0x33, 0x95, 0xe0, 0xfe, 0xc3, 0xef, 0x9b, 0xee,
+  0x9a, 0x54, 0x01, 0x44, 0x08, 0x12, 0x0e, 0xc7, 0x12, 0x0e, 0xbd, 0x75,
+  0x9a, 0x2b, 0x12, 0x11, 0x3d, 0x50, 0x04, 0x7f, 0x01, 0x80, 0x02, 0x7f,
+  0x00, 0x12, 0x11, 0x3a, 0x7e, 0x00, 0xee, 0x54, 0x01, 0x44, 0x14, 0x12,
+  0x0e, 0xc7, 0x12, 0x0e, 0xbd, 0x75, 0x9a, 0x2b, 0x12, 0x11, 0x3d, 0x50,
+  0x04, 0x7f, 0x01, 0x80, 0x02, 0x7f, 0x00, 0x12, 0x11, 0x3a, 0x7e, 0x00,
+  0xee, 0x54, 0x01, 0x44, 0x16, 0x12, 0x0e, 0xc7, 0x80, 0x1c, 0x12, 0x0f,
+  0x64, 0x44, 0x0e, 0x12, 0x0e, 0xc7, 0x80, 0x12, 0x12, 0x0f, 0x64, 0x44,
+  0x10, 0x12, 0x0e, 0xc7, 0x80, 0x08, 0x12, 0x0f, 0x64, 0x44, 0x12, 0x12,
+  0x0e, 0xc7, 0x12, 0x0e, 0xbd, 0x75, 0x9a, 0x2b, 0x22, 0x22, 0x90, 0x04,
+  0x45, 0xe0, 0x90, 0x04, 0x4f, 0xf0, 0x90, 0x04, 0x0d, 0xe0, 0xff, 0xa3,
+  0xe0, 0xc3, 0x9f, 0xff, 0xe4, 0x94, 0x00, 0xa2, 0xe7, 0x13, 0xfe, 0xef,
+  0x13, 0x12, 0x10, 0xb0, 0x12, 0x12, 0xaa, 0x70, 0x31, 0x90, 0x04, 0x7d,
+  0xe0, 0xc3, 0x94, 0x07, 0x40, 0x49, 0xe4, 0xf0, 0x12, 0x10, 0x3f, 0xd3,
+  0x94, 0x0c, 0xec, 0x64, 0x80, 0x94, 0x80, 0x40, 0x07, 0x90, 0x04, 0x45,
+  0xe0, 0x14, 0x80, 0x2f, 0xc3, 0xed, 0x94, 0xf4, 0xec, 0x64, 0x80, 0x94,
+  0x7f, 0x50, 0x28, 0x90, 0x04, 0x45, 0xe0, 0x04, 0x80, 0x1d, 0x90, 0x04,
+  0x25, 0xe0, 0x24, 0x04, 0xff, 0x90, 0x04, 0x24, 0xe0, 0x34, 0x00, 0xfe,
+  0xef, 0x78, 0x03, 0x12, 0x10, 0x52, 0xd8, 0xfb, 0xff, 0x90, 0x04, 0x45,
+  0xe0, 0xc3, 0x9f, 0x90, 0x04, 0x4f, 0xf0, 0x90, 0x04, 0x4f, 0xe0, 0xff,
+  0xc3, 0x64, 0x80, 0x94, 0x98, 0x50, 0x05, 0x74, 0x18, 0xf0, 0x80, 0x0e,
+  0xd3, 0xef, 0x64, 0x80, 0x94, 0xac, 0x40, 0x06, 0x90, 0x04, 0x4f, 0x74,
+  0x2c, 0xf0, 0x90, 0x04, 0x4f, 0xe0, 0xff, 0x90, 0x04, 0x45, 0xe0, 0xfe,
+  0x6f, 0x70, 0x03, 0x02, 0x33, 0x72, 0xee, 0xfd, 0x33, 0x95, 0xe0, 0xfc,
+  0xef, 0x33, 0x95, 0xe0, 0xfe, 0xc3, 0xef, 0x9d, 0xff, 0xee, 0x9c, 0xfe,
+  0xef, 0x78, 0x03, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8, 0xf9, 0x12, 0x10,
+  0xb0, 0x90, 0x04, 0x4f, 0xe0, 0xff, 0x90, 0x04, 0x45, 0xf0, 0x12, 0x56,
+  0x65, 0x90, 0x04, 0x0e, 0xe0, 0xff, 0x90, 0x04, 0x25, 0xe0, 0x2f, 0xff,
+  0x90, 0x04, 0x24, 0xe0, 0x34, 0x00, 0x90, 0x04, 0x26, 0x12, 0x12, 0x08,
+  0x50, 0x09, 0xe4, 0x90, 0x04, 0x26, 0xf0, 0xa3, 0xf0, 0x80, 0x0b, 0x12,
+  0x11, 0xd4, 0x40, 0x06, 0xe4, 0xf0, 0xa3, 0x74, 0xf8, 0xf0, 0x90, 0x04,
+  0x26, 0xa3, 0xe0, 0x90, 0x04, 0x0e, 0xf0, 0x90, 0x04, 0x0d, 0x12, 0x10,
+  0x3d, 0xc3, 0xef, 0x9d, 0xff, 0xe4, 0x9c, 0xa3, 0x12, 0x12, 0x08, 0x50,
+  0x09, 0xe4, 0x90, 0x04, 0x26, 0xf0, 0xa3, 0xf0, 0x80, 0x0b, 0x12, 0x11,
+  0xd4, 0x40, 0x06, 0xe4, 0xf0, 0xa3, 0x74, 0xf8, 0xf0, 0x90, 0x04, 0x26,
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+  0x21, 0x7f, 0x36, 0x12, 0x5f, 0xed, 0x12, 0x14, 0x15, 0xc0, 0x04, 0xc0,
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+  0xfd, 0xe8, 0xfc, 0x12, 0x51, 0xa3, 0x12, 0x13, 0xbc, 0x12, 0x16, 0xeb,
+  0x12, 0x14, 0x2a, 0x12, 0x5e, 0xb2, 0xd3, 0xef, 0x64, 0x80, 0x94, 0x61,
+  0x50, 0x38, 0x12, 0x15, 0xcc, 0x50, 0x2c, 0x12, 0x56, 0xba, 0x7f, 0x1f,
+  0x12, 0x5c, 0xfa, 0x12, 0x5e, 0xf5, 0xe5, 0x10, 0x12, 0x13, 0xb8, 0x12,
+  0x13, 0xf8, 0xe4, 0xf0, 0xe5, 0x10, 0xc3, 0x94, 0xff, 0x40, 0x04, 0x7f,
+  0x00, 0x80, 0x06, 0x90, 0x04, 0x77, 0xe0, 0x04, 0xff, 0x90, 0x04, 0x77,
+  0xef, 0xf0, 0x22, 0x12, 0x16, 0x84, 0x74, 0x63, 0xf0, 0x22, 0x12, 0x5e,
+  0xb2, 0xef, 0x14, 0xff, 0x12, 0x5c, 0xfa, 0x12, 0x5e, 0xf5, 0x90, 0x04,
+  0x77, 0xe5, 0x10, 0xf0, 0x22, 0x8d, 0x82, 0x8c, 0x83, 0xad, 0x07, 0x79,
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+  0xe5, 0x21, 0x12, 0x12, 0xd6, 0x50, 0x0f, 0xc3, 0xe5, 0x20, 0x12, 0x12,
+  0xa2, 0x40, 0x07, 0xe5, 0x20, 0x12, 0x12, 0xd6, 0x50, 0x03, 0x7f, 0x00,
+  0x22, 0xe5, 0x22, 0x6d, 0x70, 0x32, 0xe5, 0x82, 0x45, 0x83, 0x70, 0x02,
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+  0xde, 0x40, 0x06, 0xae, 0x83, 0xaf, 0x82, 0x80, 0x03, 0x12, 0x13, 0x52,
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+  0x37, 0xe5, 0x1f, 0x45, 0x1e, 0x70, 0x02, 0xff, 0x22, 0xd3, 0xed, 0x12,
+  0x12, 0xd6, 0x40, 0x02, 0x7a, 0xff, 0x12, 0x12, 0xea, 0x40, 0x06, 0xae,
+  0x1e, 0xaf, 0x1f, 0x80, 0x03, 0x12, 0x13, 0x5c, 0x8e, 0x23, 0x8f, 0x24,
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+  0x9d, 0x40, 0x05, 0xec, 0x9d, 0xfd, 0x80, 0x0b, 0x90, 0x04, 0x16, 0xe0,
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+  0x15, 0xe5, 0x15, 0x70, 0xc0, 0x05, 0x14, 0x80, 0xbc, 0xae, 0x16, 0xaf,
+  0x17, 0x22, 0x7f, 0x42, 0x12, 0x60, 0x3f, 0xef, 0x54, 0x07, 0x90, 0x04,
+  0x59, 0x12, 0x11, 0xc2, 0x90, 0x04, 0x59, 0x12, 0x10, 0x3d, 0x90, 0x04,
+  0x5b, 0xe0, 0xfe, 0xfb, 0x90, 0x04, 0x2c, 0x12, 0x0e, 0xf2, 0x75, 0x20,
+  0x01, 0x75, 0x21, 0x07, 0x75, 0x22, 0xff, 0x12, 0x40, 0x76, 0x90, 0x04,
+  0x59, 0x12, 0x10, 0xeb, 0x90, 0x04, 0x5b, 0xf0, 0x90, 0x04, 0x62, 0xe0,
+  0x90, 0x04, 0x5d, 0xf0, 0x90, 0x04, 0x24, 0xe0, 0xff, 0xa3, 0xe0, 0x90,
+  0x04, 0x2c, 0xcf, 0xf0, 0xa3, 0xef, 0xf0, 0x90, 0x04, 0x59, 0xe0, 0xf5,
+  0xa4, 0x75, 0xa6, 0xf8, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x42, 0x22, 0x8f,
+  0x10, 0x7f, 0x38, 0x12, 0x5f, 0xed, 0x7c, 0x00, 0xef, 0x25, 0x10, 0xff,
+  0xec, 0x3e, 0x90, 0x04, 0x1c, 0xf0, 0xa3, 0xef, 0xf0, 0x90, 0x04, 0x57,
+  0xe0, 0xfe, 0x33, 0x95, 0xe0, 0x90, 0x04, 0x26, 0xf0, 0xa3, 0xce, 0xf0,
+  0xff, 0x12, 0x0e, 0xe2, 0xe4, 0xf5, 0x20, 0x75, 0x21, 0x1f, 0x75, 0x22,
+  0xff, 0x12, 0x40, 0x76, 0x90, 0x04, 0x57, 0xef, 0xf0, 0x90, 0x04, 0x26,
+  0x12, 0x10, 0x0c, 0x90, 0x04, 0x57, 0xe0, 0xff, 0x12, 0x5c, 0xfa, 0x90,
+  0x04, 0x60, 0xe0, 0x60, 0x07, 0x90, 0x04, 0x82, 0x74, 0x01, 0xf0, 0x22,
+  0xe4, 0x90, 0x04, 0x82, 0xf0, 0x22, 0x90, 0x04, 0x40, 0xe0, 0x24, 0xea,
+  0x60, 0x2e, 0x14, 0x60, 0x3e, 0x80, 0x00, 0x90, 0x04, 0x49, 0xe0, 0x70,
+  0x3f, 0x12, 0x0e, 0xfa, 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9, 0x30,
+  0xe0, 0x32, 0x90, 0x04, 0x5f, 0xe0, 0x70, 0x19, 0x7f, 0x09, 0x12, 0x5a,
+  0x3d, 0x90, 0x04, 0x5f, 0x74, 0x01, 0xf0, 0x74, 0x16, 0x12, 0x12, 0x6b,
+  0x12, 0x5f, 0xe1, 0xef, 0x70, 0x03, 0x7f, 0x02, 0x22, 0x7f, 0x09, 0x12,
+  0x49, 0xb3, 0x74, 0x17, 0x12, 0x12, 0x6b, 0x12, 0x5f, 0xe1, 0xef, 0x70,
+  0x03, 0x7f, 0x02, 0x22, 0x74, 0x18, 0x12, 0x11, 0xbb, 0x22, 0x8f, 0x1d,
+  0x7f, 0x0a, 0x12, 0x5f, 0xed, 0xee, 0xff, 0xe5, 0x1d, 0x12, 0x13, 0x15,
+  0x75, 0xa5, 0x01, 0x12, 0x13, 0x3e, 0xef, 0x30, 0xe7, 0x09, 0x12, 0x10,
+  0xa3, 0xef, 0xf4, 0x04, 0xff, 0x80, 0x06, 0x75, 0xa5, 0x04, 0x12, 0x10,
+  0xa6, 0x90, 0x04, 0x44, 0xe0, 0x60, 0x19, 0x75, 0xa4, 0x01, 0x75, 0xa6,
+  0x80, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x04, 0xe4, 0xfe, 0x12, 0x12, 0x1d,
+  0x50, 0x16, 0x12, 0x0f, 0x7b, 0x0e, 0x80, 0xf5, 0x12, 0x10, 0x7d, 0x12,
+  0x0f, 0x7b, 0xe4, 0xf5, 0xa5, 0x75, 0xa6, 0xff, 0x12, 0x10, 0x8b, 0x22,
+  0x22, 0x8f, 0x1a, 0x7f, 0x0a, 0x12, 0x60, 0x3f, 0xe5, 0x1a, 0x12, 0x13,
+  0x15, 0x75, 0xa5, 0x02, 0x12, 0x13, 0x3e, 0xef, 0x30, 0xe7, 0x09, 0x12,
+  0x10, 0xa3, 0xef, 0xf4, 0x04, 0xff, 0x80, 0x06, 0x75, 0xa5, 0x04, 0x12,
+  0x10, 0xa6, 0x90, 0x04, 0x44, 0xe0, 0x60, 0x19, 0x75, 0xa4, 0x01, 0x75,
+  0xa6, 0x80, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x04, 0xe4, 0xfe, 0x12, 0x12,
+  0x1d, 0x50, 0x16, 0x12, 0x0f, 0x7b, 0x0e, 0x80, 0xf5, 0x12, 0x10, 0x7d,
+  0x12, 0x0f, 0x7b, 0xe4, 0xf5, 0xa5, 0x75, 0xa6, 0xff, 0x12, 0x10, 0x8b,
+  0x22, 0x22, 0x90, 0x04, 0x49, 0xe0, 0x70, 0x02, 0x80, 0x2f, 0x90, 0x04,
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+  0x12, 0x0f, 0xe0, 0x22, 0x12, 0x59, 0x5b, 0x8f, 0x1e, 0x8e, 0x1d, 0x8d,
+  0x1c, 0x8c, 0x1b, 0x90, 0x04, 0x22, 0xee, 0xf0, 0xa3, 0xef, 0xf0, 0x78,
+  0x10, 0x12, 0x2b, 0xb6, 0x90, 0x04, 0x20, 0xee, 0xf0, 0xa3, 0xef, 0xf0,
+  0x22, 0x12, 0x0e, 0xa8, 0xe4, 0xf5, 0xa4, 0x75, 0xa5, 0x24, 0x75, 0xa6,
+  0xf3, 0x12, 0x13, 0x77, 0x75, 0xa4, 0x60, 0x12, 0x0f, 0x1e, 0xe4, 0xf5,
+  0xa4, 0x75, 0xa5, 0x38, 0x12, 0x0e, 0xd9, 0x22, 0x12, 0x12, 0x94, 0x80,
+  0x05, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8, 0xf9, 0x12, 0x11, 0xab, 0x90,
+  0x04, 0x2e, 0x12, 0x11, 0x19, 0x90, 0x04, 0x2e, 0xee, 0xf0, 0xa3, 0xef,
+  0xf0, 0x22, 0x12, 0x12, 0x94, 0x80, 0x05, 0xc3, 0x33, 0xce, 0x33, 0xce,
+  0xd8, 0xf9, 0x12, 0x11, 0xab, 0x90, 0x04, 0x30, 0x12, 0x11, 0x19, 0x90,
+  0x04, 0x30, 0xee, 0xf0, 0xa3, 0xef, 0xf0, 0x22, 0x12, 0x0e, 0xa8, 0xe4,
+  0xf5, 0xa4, 0x12, 0x0f, 0xf7, 0x12, 0x0e, 0xd3, 0x75, 0xa4, 0x03, 0xe4,
+  0xf5, 0xa5, 0x75, 0xa6, 0xfc, 0x75, 0xa7, 0xff, 0x75, 0x9a, 0x33, 0x22,
+  0x7f, 0x1f, 0x12, 0x5e, 0x4c, 0x75, 0xa4, 0x10, 0xe4, 0xf5, 0xa5, 0x75,
+  0xa6, 0xcf, 0x12, 0x14, 0x83, 0xe4, 0xf5, 0xa4, 0x12, 0x16, 0x76, 0x12,
+  0x16, 0xf5, 0x22, 0xad, 0x07, 0xed, 0x75, 0xf0, 0x08, 0xa4, 0xae, 0xf0,
+  0xf5, 0xa4, 0xee, 0x54, 0x01, 0x12, 0x0e, 0xc7, 0x12, 0x0e, 0xbd, 0x75,
+  0x9a, 0x2b, 0x22, 0xab, 0x07, 0xaa, 0x06, 0xea, 0x5c, 0xfe, 0xeb, 0x5d,
+  0x25, 0xe0, 0xff, 0xee, 0x33, 0xfe, 0xc3, 0xeb, 0x9f, 0xff, 0xea, 0x9e,
+  0xfe, 0x22, 0x7f, 0x3a, 0x12, 0x5f, 0xed, 0xee, 0x54, 0x3f, 0xfe, 0x7d,
+  0x00, 0x7c, 0x20, 0x12, 0x5e, 0x9b, 0xee, 0xff, 0xef, 0xf4, 0x04, 0xff,
+  0x22, 0x90, 0xe0, 0x00, 0x74, 0x04, 0xf0, 0x04, 0xf0, 0x90, 0xe0, 0x00,
+  0xe0, 0x20, 0xe0, 0xf9, 0x90, 0xe0, 0x00, 0x74, 0x06, 0xf0, 0x22, 0x12,
+  0x0e, 0xa8, 0x75, 0xa4, 0x20, 0x75, 0xa5, 0xa0, 0x75, 0xa6, 0xd3, 0x12,
+  0x11, 0x2c, 0x12, 0x0f, 0x1b, 0x12, 0x0e, 0xd3, 0x22, 0xe4, 0xf5, 0xa5,
+  0x12, 0x0e, 0xc0, 0x75, 0x9a, 0x30, 0x12, 0x0e, 0xbd, 0x75, 0x9a, 0x30,
+  0x12, 0x11, 0x44, 0x12, 0x12, 0x6f, 0x22, 0x12, 0x0e, 0xa8, 0xe4, 0xf5,
+  0xa4, 0x75, 0xa5, 0x24, 0x75, 0xa6, 0xff, 0x12, 0x13, 0x77, 0x75, 0xa4,
+  0x60, 0x12, 0x0f, 0x1e, 0x22, 0x12, 0x0e, 0xa8, 0x12, 0x0f, 0xf4, 0x75,
+  0xa4, 0x60, 0x75, 0xa5, 0x60, 0x12, 0x0f, 0x21, 0x12, 0x0e, 0xd3, 0x22,
+  0x12, 0x5e, 0xb2, 0x90, 0x04, 0x4f, 0xef, 0xf0, 0xe4, 0x12, 0x16, 0xa5,
+  0x7f, 0x1c, 0x02, 0x5f, 0x45, 0x12, 0x0e, 0xa8, 0x75, 0xa4, 0x0c, 0x75,
+  0xa5, 0xb0, 0x12, 0x11, 0x29, 0x12, 0x0e, 0xd3, 0x22, 0x12, 0x0e, 0xa8,
+  0x75, 0xa4, 0x0c, 0x75, 0xa5, 0xa0, 0x12, 0x11, 0x29, 0x12, 0x0e, 0xd3,
+  0x22, 0x12, 0x0e, 0xa8, 0xe4, 0xf5, 0xa4, 0x75, 0xa5, 0x90, 0x12, 0x11,
+  0x29, 0x12, 0x0e, 0xd3, 0x22, 0x12, 0x0e, 0xa8, 0x12, 0x0f, 0xf4, 0x75,
+  0xa4, 0x60, 0x12, 0x0f, 0x1e, 0x12, 0x0e, 0xd3, 0x22, 0xaf, 0xbc, 0xad,
+  0x07, 0xe5, 0xbd, 0x54, 0x03, 0xfc, 0xae, 0x04, 0xaf, 0x05, 0x22, 0x12,
+  0x12, 0x0d, 0x50, 0x08, 0xef, 0xf4, 0xff, 0xee, 0xf4, 0xfe, 0x80, 0x00,
+  0x22, 0x8f, 0x9e, 0x8d, 0x9d, 0xad, 0xa9, 0xaf, 0xaa, 0xef, 0xfe, 0xed,
+  0xff, 0x22, 0xef, 0xf5, 0xa4, 0x75, 0xa6, 0xfe, 0x75, 0xa7, 0xff, 0x75,
+  0x9a, 0x91, 0x22, 0x12, 0x0e, 0xa8, 0x12, 0x0f, 0xf4, 0x12, 0x0f, 0x1b,
+  0x12, 0x0e, 0xd3, 0x22, 0x12, 0x0e, 0xa8, 0x12, 0x0e, 0xbd, 0x75, 0x9a,
+  0x30, 0x12, 0x11, 0x44, 0x22, 0xd2, 0xc8, 0xd2, 0xc9, 0xd2, 0xcb, 0xe4,
+  0xf5, 0xbf, 0xd2, 0xca, 0x22, 0x90, 0x04, 0x83, 0xe0, 0x7f, 0x00, 0xb4,
+  0x07, 0x02, 0x7f, 0x01, 0x22, 0x8f, 0x9b, 0xad, 0xa9, 0xaf, 0xaa, 0xef,
+  0xfe, 0xed, 0xff, 0x22, 0x90, 0x00, 0x5f, 0xe0, 0x7f, 0x00, 0x70, 0x02,
+  0x7f, 0x01, 0x22, 0x75, 0xa4, 0x80, 0xe4, 0x12, 0x15, 0x37, 0x75, 0x9a,
+  0x0d, 0x22, 0x90, 0xe0, 0x01, 0xe0, 0x54, 0x01, 0xff, 0x22, 0xef, 0x24,
+  0x0f, 0xa2, 0xe7, 0x13, 0xff, 0x22, 0x8f, 0x9e, 0x8d, 0x9d, 0xaf, 0xa9,
+  0x22, 0xef, 0x25, 0xe0, 0x24, 0xf1, 0xff, 0x22, 0x75, 0xa4, 0xc0, 0x12,
+  0x16, 0x5c, 0x22, 0x75, 0xa4, 0x80, 0x12, 0x16, 0x5c, 0x22, 0x8f, 0x9b,
+  0xaf, 0xaa, 0x22, 0x8f, 0x9b, 0xaf, 0xa9, 0x22, 0x22, 0x22, 0x22, 0x00,
+  0x00, 0x10, 0x21, 0x20, 0x42, 0x30, 0x63, 0x40, 0x84, 0x50, 0xa5, 0x60,
+  0xc6, 0x70, 0xe7, 0x81, 0x08, 0x91, 0x29, 0xa1, 0x4a, 0xb1, 0x6b, 0xc1,
+  0x8c, 0xd1, 0xad, 0xe1, 0xce, 0xf1, 0xef, 0x12, 0x31, 0x02, 0x10, 0x32,
+  0x73, 0x22, 0x52, 0x52, 0xb5, 0x42, 0x94, 0x72, 0xf7, 0x62, 0xd6, 0x93,
+  0x39, 0x83, 0x18, 0xb3, 0x7b, 0xa3, 0x5a, 0xd3, 0xbd, 0xc3, 0x9c, 0xf3,
+  0xff, 0xe3, 0xde, 0x24, 0x62, 0x34, 0x43, 0x04, 0x20, 0x14, 0x01, 0x64,
+  0xe6, 0x74, 0xc7, 0x44, 0xa4, 0x54, 0x85, 0xa5, 0x6a, 0xb5, 0x4b, 0x85,
+  0x28, 0x95, 0x09, 0xe5, 0xee, 0xf5, 0xcf, 0xc5, 0xac, 0xd5, 0x8d, 0x36,
+  0x53, 0x26, 0x72, 0x16, 0x11, 0x06, 0x30, 0x76, 0xd7, 0x66, 0xf6, 0x56,
+  0x95, 0x46, 0xb4, 0xb7, 0x5b, 0xa7, 0x7a, 0x97, 0x19, 0x87, 0x38, 0xf7,
+  0xdf, 0xe7, 0xfe, 0xd7, 0x9d, 0xc7, 0xbc, 0x48, 0xc4, 0x58, 0xe5, 0x68,
+  0x86, 0x78, 0xa7, 0x08, 0x40, 0x18, 0x61, 0x28, 0x02, 0x38, 0x23, 0xc9,
+  0xcc, 0xd9, 0xed, 0xe9, 0x8e, 0xf9, 0xaf, 0x89, 0x48, 0x99, 0x69, 0xa9,
+  0x0a, 0xb9, 0x2b, 0x5a, 0xf5, 0x4a, 0xd4, 0x7a, 0xb7, 0x6a, 0x96, 0x1a,
+  0x71, 0x0a, 0x50, 0x3a, 0x33, 0x2a, 0x12, 0xdb, 0xfd, 0xcb, 0xdc, 0xfb,
+  0xbf, 0xeb, 0x9e, 0x9b, 0x79, 0x8b, 0x58, 0xbb, 0x3b, 0xab, 0x1a, 0x6c,
+  0xa6, 0x7c, 0x87, 0x4c, 0xe4, 0x5c, 0xc5, 0x2c, 0x22, 0x3c, 0x03, 0x0c,
+  0x60, 0x1c, 0x41, 0xed, 0xae, 0xfd, 0x8f, 0xcd, 0xec, 0xdd, 0xcd, 0xad,
+  0x2a, 0xbd, 0x0b, 0x8d, 0x68, 0x9d, 0x49, 0x7e, 0x97, 0x6e, 0xb6, 0x5e,
+  0xd5, 0x4e, 0xf4, 0x3e, 0x13, 0x2e, 0x32, 0x1e, 0x51, 0x0e, 0x70, 0xff,
+  0x9f, 0xef, 0xbe, 0xdf, 0xdd, 0xcf, 0xfc, 0xbf, 0x1b, 0xaf, 0x3a, 0x9f,
+  0x59, 0x8f, 0x78, 0x91, 0x88, 0x81, 0xa9, 0xb1, 0xca, 0xa1, 0xeb, 0xd1,
+  0x0c, 0xc1, 0x2d, 0xf1, 0x4e, 0xe1, 0x6f, 0x10, 0x80, 0x00, 0xa1, 0x30,
+  0xc2, 0x20, 0xe3, 0x50, 0x04, 0x40, 0x25, 0x70, 0x46, 0x60, 0x67, 0x83,
+  0xb9, 0x93, 0x98, 0xa3, 0xfb, 0xb3, 0xda, 0xc3, 0x3d, 0xd3, 0x1c, 0xe3,
+  0x7f, 0xf3, 0x5e, 0x02, 0xb1, 0x12, 0x90, 0x22, 0xf3, 0x32, 0xd2, 0x42,
+  0x35, 0x52, 0x14, 0x62, 0x77, 0x72, 0x56, 0xb5, 0xea, 0xa5, 0xcb, 0x95,
+  0xa8, 0x85, 0x89, 0xf5, 0x6e, 0xe5, 0x4f, 0xd5, 0x2c, 0xc5, 0x0d, 0x34,
+  0xe2, 0x24, 0xc3, 0x14, 0xa0, 0x04, 0x81, 0x74, 0x66, 0x64, 0x47, 0x54,
+  0x24, 0x44, 0x05, 0xa7, 0xdb, 0xb7, 0xfa, 0x87, 0x99, 0x97, 0xb8, 0xe7,
+  0x5f, 0xf7, 0x7e, 0xc7, 0x1d, 0xd7, 0x3c, 0x26, 0xd3, 0x36, 0xf2, 0x06,
+  0x91, 0x16, 0xb0, 0x66, 0x57, 0x76, 0x76, 0x46, 0x15, 0x56, 0x34, 0xd9,
+  0x4c, 0xc9, 0x6d, 0xf9, 0x0e, 0xe9, 0x2f, 0x99, 0xc8, 0x89, 0xe9, 0xb9,
+  0x8a, 0xa9, 0xab, 0x58, 0x44, 0x48, 0x65, 0x78, 0x06, 0x68, 0x27, 0x18,
+  0xc0, 0x08, 0xe1, 0x38, 0x82, 0x28, 0xa3, 0xcb, 0x7d, 0xdb, 0x5c, 0xeb,
+  0x3f, 0xfb, 0x1e, 0x8b, 0xf9, 0x9b, 0xd8, 0xab, 0xbb, 0xbb, 0x9a, 0x4a,
+  0x75, 0x5a, 0x54, 0x6a, 0x37, 0x7a, 0x16, 0x0a, 0xf1, 0x1a, 0xd0, 0x2a,
+  0xb3, 0x3a, 0x92, 0xfd, 0x2e, 0xed, 0x0f, 0xdd, 0x6c, 0xcd, 0x4d, 0xbd,
+  0xaa, 0xad, 0x8b, 0x9d, 0xe8, 0x8d, 0xc9, 0x7c, 0x26, 0x6c, 0x07, 0x5c,
+  0x64, 0x4c, 0x45, 0x3c, 0xa2, 0x2c, 0x83, 0x1c, 0xe0, 0x0c, 0xc1, 0xef,
+  0x1f, 0xff, 0x3e, 0xcf, 0x5d, 0xdf, 0x7c, 0xaf, 0x9b, 0xbf, 0xba, 0x8f,
+  0xd9, 0x9f, 0xf8, 0x6e, 0x17, 0x7e, 0x36, 0x4e, 0x55, 0x5e, 0x74, 0x2e,
+  0x93, 0x3e, 0xb2, 0x0e, 0xd1, 0x1e, 0xf0, 0x1c, 0xa0, 0x1c, 0x18, 0x1b,
+  0x98, 0x1b, 0x18, 0x1a, 0x90, 0x1a, 0x10, 0x19, 0x88, 0x19, 0x08, 0x18,
+  0x80, 0x18, 0x00, 0x17, 0x80, 0x16, 0xf8, 0x16, 0x78, 0x15, 0xf0, 0x15,
+  0x70, 0x14, 0xe8, 0x14, 0x68, 0x13, 0xe8, 0x13, 0x60, 0x12, 0xe0, 0x12,
+  0x58, 0x00, 0x00, 0x00, 0x03, 0x00, 0x06, 0x00, 0x09, 0x00, 0x0c, 0x00,
+  0x0f, 0x00, 0x12, 0x00, 0x15, 0x00, 0x18, 0x00, 0x1b, 0x00, 0x1e, 0x00,
+  0x21, 0x00, 0x24, 0x00, 0x27, 0x00, 0x2a, 0x00, 0x2d, 0x00, 0x30, 0x00,
+  0x33, 0x00, 0x36, 0x00, 0x39, 0x00, 0x3c, 0x00, 0x3f, 0x00, 0x42, 0x00,
+  0x45, 0x00, 0x48, 0x00, 0x4b, 0x00, 0x54, 0x00, 0x5d, 0x00, 0x66, 0x00,
+  0x6f, 0x00, 0x78, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x05, 0x00, 0x0a, 0x00,
+  0x0f, 0x00, 0x14, 0x00, 0x19, 0x00, 0x1e, 0x00, 0x23, 0x00, 0x28, 0x00,
+  0x2d, 0x00, 0x32, 0x00, 0x37, 0x00, 0x3c, 0x00, 0x41, 0x00, 0x46, 0x00,
+  0x4b, 0x00, 0x50, 0x00, 0x55, 0x00, 0x5a, 0x00, 0x5f, 0x00, 0x64, 0x00,
+  0x69, 0x00, 0x6e, 0x00, 0x73, 0x00, 0x78, 0x00, 0x7d, 0x00, 0x8c, 0x00,
+  0x9b, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xc8, 0x00, 0xd2, 0x00, 0x00, 0x00,
+  0x09, 0x00, 0x12, 0x00, 0x1b, 0x00, 0x24, 0x00, 0x2d, 0x00, 0x36, 0x00,
+  0x3f, 0x00, 0x48, 0x00, 0x51, 0x00, 0x5a, 0x00, 0x63, 0x00, 0x6c, 0x00,
+  0x75, 0x00, 0x7e, 0x00, 0x87, 0x00, 0x90, 0x00, 0x99, 0x00, 0xa2, 0x00,
+  0xab, 0x00, 0xb4, 0x00, 0xbd, 0x00, 0xc6, 0x00, 0xcf, 0x00, 0xd8, 0x00,
+  0xf0, 0x01, 0x08, 0x01, 0x20, 0x01, 0x38, 0x01, 0x50, 0x01, 0x68, 0x01,
+  0x80, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x1e, 0x00, 0x2d, 0x00, 0x3c, 0x00,
+  0x4b, 0x00, 0x5a, 0x00, 0x69, 0x00, 0x78, 0x00, 0x87, 0x00, 0x96, 0x00,
+  0xa5, 0x00, 0xb4, 0x00, 0xc3, 0x00, 0xd2, 0x00, 0xe1, 0x00, 0xf0, 0x00,
+  0xff, 0x01, 0x0e, 0x01, 0x1d, 0x01, 0x2c, 0x01, 0x3b, 0x01, 0x4a, 0x01,
+  0x59, 0x01, 0x68, 0x01, 0x90, 0x01, 0xb8, 0x01, 0xe0, 0x02, 0x08, 0x02,
+  0x30, 0x02, 0x58, 0x02, 0x80, 0x1a, 0x1a, 0x1b, 0x1b, 0x1c, 0x1d, 0x1e,
+  0x1f, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x29,
+  0x2a, 0x2a, 0x22, 0x23, 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28,
+  0x29, 0x29, 0x2a, 0x2a, 0x2b, 0x2b, 0x2c, 0x2c, 0x2d, 0x2e, 0x2f, 0x00,
+  0x00, 0x01, 0x80
+};
diff --git a/drivers/net/bcmbca/lport/serdes_access.c b/drivers/net/bcmbca/lport/serdes_access.c
new file mode 100644
index 0000000000..72e3a5176f
--- /dev/null
+++ b/drivers/net/bcmbca/lport/serdes_access.c
@@ -0,0 +1,680 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+   
+   */
+/*
+ * serdes_access.c
+ *
+ *  Created on: April 2015
+ *      Author: yonatani
+ */
+
+#include "serdes_access.h"
+#include "bcm6858_lport_srds_ag.h"
+#include "bcm6858_drivers_lport_ag.h"
+#include "lport_compat.h"
+#include "lport_mdio.h"
+#include "lport_defs.h"
+
+merlin_sdk_cb_s merlin_callbacks = {};
+
+#define MERLIN_AER_ADDRESS 0xFFDE
+#define SERDES_PLL_LOCK_RETRIES 100
+#define PMI_DELAY UDELAY(10)
+
+/* Ports 0,7 maps to Merlin Core 0 Lane 0
+ * Ports 1,4 maps to Merlin Core 0 Lane 1
+ * Ports 2,5 maps to Merlin Core 1 Lane 0
+ * Ports 3,6 maps to Merlin Core 1 Lane 1
+ *
+ */
+
+static E_MERLIN_LANE port_to_lane[] = {
+    MERLIN_LANE_0,
+    MERLIN_LANE_1,
+    MERLIN_LANE_2,
+    MERLIN_LANE_3,
+    MERLIN_LANE_1,
+    MERLIN_LANE_2,
+    MERLIN_LANE_3,
+    MERLIN_LANE_0
+};
+
+static E_MERLIN_ID port_to_core[] = {
+    MERLIN_ID_0,
+    MERLIN_ID_0,
+    MERLIN_ID_1,
+    MERLIN_ID_1,
+    MERLIN_ID_0,
+    MERLIN_ID_1,
+    MERLIN_ID_1,
+    MERLIN_ID_0,
+};
+
+static E_MERLIN_ID lane_to_core[] = {
+    MERLIN_ID_0,
+    MERLIN_ID_0,
+    MERLIN_ID_1,
+    MERLIN_ID_1,
+};
+
+static uint16_t g_merlin_mdio_address[2] = {0x8, 0x9};
+
+static int write_serdes_pmi(E_MERLIN_ID merlin_id, uint32_t addr, uint16_t mask, uint16_t value)
+{
+    int rc;
+    uint8_t err = 0;
+    uint8_t start_busy = 1;
+    uint8_t r_w = 0; /* Means write operation */
+    uint16_t reg_data = value;
+
+    if (!merlin_id)
+    {
+        rc = ag_drv_lport_srds_serdes_0_indir_acc_addr_0_set(addr);
+        rc = rc ? rc : ag_drv_lport_srds_serdes_0_indir_acc_mask_0_set(~mask);
+        rc = rc ? rc : ag_drv_lport_srds_serdes_0_indir_acc_cntrl_0_set(err, start_busy, r_w, reg_data);
+
+        PMI_DELAY;
+
+        //validate no error after writing
+        rc = rc ? rc : ag_drv_lport_srds_serdes_0_indir_acc_cntrl_0_get(&err, &start_busy, &r_w, &reg_data);
+    }
+    else
+    {
+        rc = ag_drv_lport_srds_serdes_1_indir_acc_addr_0_set(addr);
+        rc = rc ? rc : ag_drv_lport_srds_serdes_1_indir_acc_mask_0_set(~mask);
+        rc = rc ? rc : ag_drv_lport_srds_serdes_1_indir_acc_cntrl_0_set(err, start_busy, r_w, reg_data);
+
+        PMI_DELAY;
+
+        //validate no error after writing
+        rc = rc ? rc : ag_drv_lport_srds_serdes_1_indir_acc_cntrl_0_get(&err, &start_busy, &r_w, &reg_data);
+    }
+
+    if (rc | err | start_busy)
+    {
+        pr_err("Error while validating write to Serdes %d: Busy=%d,Err=%d,Rc=%d\n",
+            merlin_id, start_busy, err, rc);
+        return LPORT_ERR_IO;
+    }
+    return LPORT_ERR_OK;
+}
+
+static int read_serdes_pmi(E_MERLIN_ID merlin_id, uint32_t addr, uint16_t mask, uint16_t *value)
+{
+    int rc;
+    uint8_t err = 0;
+    uint8_t start_busy = 1;
+    uint8_t r_w = 1; /* Means read operation */
+    uint16_t reg_data = 0;
+
+    if (!merlin_id)
+    {
+        rc = ag_drv_lport_srds_serdes_0_indir_acc_addr_0_set(addr);
+        rc = rc ? rc : ag_drv_lport_srds_serdes_0_indir_acc_cntrl_0_set(err, start_busy, r_w, reg_data);
+
+        PMI_DELAY;
+
+        //validate no error after writing
+        rc = rc ? rc : ag_drv_lport_srds_serdes_0_indir_acc_cntrl_0_get(&err, &start_busy, &r_w, &reg_data);
+    }
+    else
+    {
+        rc = ag_drv_lport_srds_serdes_1_indir_acc_addr_0_set(addr);
+        rc = rc ? rc : ag_drv_lport_srds_serdes_1_indir_acc_cntrl_0_set(err, start_busy, r_w, reg_data);
+
+        PMI_DELAY;
+
+        //validate no error after writing
+        rc = rc ? rc : ag_drv_lport_srds_serdes_1_indir_acc_cntrl_0_get(&err, &start_busy, &r_w, &reg_data);
+    }
+    if (rc | err | start_busy)
+    {
+        pr_err("Error while validating write to Serdes %d: Busy=%d,Err=%d,Rc=%d\n",
+            merlin_id, start_busy, err, rc);
+        return LPORT_ERR_IO;
+    }
+    *value = reg_data & mask;
+    return LPORT_ERR_OK;
+}
+
+int write_serdes_reg(E_MERLIN_ID merlin_id, uint32_t addr,uint16_t mask,uint16_t value)
+{
+    return write_serdes_pmi(merlin_id,addr,mask,value);
+}
+
+int read_serdes_reg(E_MERLIN_ID merlin_id, uint32_t addr, uint16_t mask, uint16_t *value)
+{
+    return read_serdes_pmi(merlin_id,addr,mask,value);
+}
+
+int serdes_get_pll_lock(E_MERLIN_ID core_id)
+{
+    lport_srds_dual_serdes_0_status serdes0_status;
+    lport_srds_dual_serdes_1_status serdes1_status;
+    uint32_t pll_lock_retry = SERDES_PLL_LOCK_RETRIES;
+
+    if (core_id == MERLIN_ID_0)
+    {
+        do
+        {
+            UDELAY(10000);
+            ag_drv_lport_srds_dual_serdes_0_status_get(&serdes0_status);
+        }while(!serdes0_status.pll_lock && --pll_lock_retry);
+
+        if(!serdes0_status.pll_lock)
+        {
+            pr_err("%s(%d):Failed to LOCK PLL of Serdes 0\n",__FUNCTION__,__LINE__);
+            return LPORT_ERR_IO;
+        }
+    }
+    else
+    {
+        /* Poll PLL */
+        do
+        {
+            UDELAY(10000);
+            ag_drv_lport_srds_dual_serdes_1_status_get(&serdes1_status);
+        }while(!serdes1_status.pll_lock && --pll_lock_retry);
+
+        if(!serdes1_status.pll_lock)
+        {
+            pr_err("%s(%d):Failed to LOCK PLL of Serdes 1\n",__FUNCTION__,__LINE__);
+            return LPORT_ERR_IO;
+        }
+    }
+
+    return LPORT_ERR_OK;
+}
+
+static E_MERLIN_VCO core_vco[2] = {};
+
+static int merlin_core_init(E_MERLIN_ID core_id, E_MERLIN_VCO vco)
+{
+    int disable;
+    lport_srds_dual_serdes_0_cntrl serdes0_cntrl;
+    lport_srds_dual_serdes_1_cntrl serdes1_cntrl;
+
+    if (core_vco[core_id] == vco)
+        return LPORT_ERR_OK;
+
+    disable = vco == MERLIN_VCO_UNKNOWN;
+
+#ifndef LPORT_SERDES_POWER_SAVING
+    if (disable)
+        return LPORT_ERR_OK;
+#endif
+
+    /* check if we need to reset core */
+    if (core_id == MERLIN_ID_0)
+    {
+        ag_drv_lport_srds_dual_serdes_0_cntrl_get(&serdes0_cntrl);
+
+        serdes0_cntrl.serdes_reset = 1;
+        serdes0_cntrl.refclk_reset = 1;
+        ag_drv_lport_srds_dual_serdes_0_cntrl_set(&serdes0_cntrl);
+        UDELAY(10000);
+
+        serdes0_cntrl.iddq = disable;
+        ag_drv_lport_srds_dual_serdes_0_cntrl_set(&serdes0_cntrl);
+        UDELAY(10000);
+
+        serdes0_cntrl.serdes_reset = disable;
+        serdes0_cntrl.refclk_reset = disable;
+        ag_drv_lport_srds_dual_serdes_0_cntrl_set(&serdes0_cntrl);
+        UDELAY(10000);
+
+        serdes0_cntrl.serdes_prtad = g_merlin_mdio_address[MERLIN_ID_0];
+        ag_drv_lport_srds_dual_serdes_0_cntrl_set(&serdes0_cntrl);
+        UDELAY(10000);
+    }
+    else
+    {
+        ag_drv_lport_srds_dual_serdes_1_cntrl_get(&serdes1_cntrl);
+
+        serdes1_cntrl.serdes_reset = 1;
+        serdes1_cntrl.refclk_reset = 1;
+        ag_drv_lport_srds_dual_serdes_1_cntrl_set(&serdes1_cntrl);
+        UDELAY(10000);
+
+        serdes1_cntrl.iddq = disable;
+        ag_drv_lport_srds_dual_serdes_1_cntrl_set(&serdes1_cntrl);
+        UDELAY(10000);
+
+        serdes1_cntrl.serdes_reset = disable;
+        serdes1_cntrl.refclk_reset = disable;
+        ag_drv_lport_srds_dual_serdes_1_cntrl_set(&serdes1_cntrl);
+        UDELAY(10000);
+
+        serdes1_cntrl.serdes_prtad = g_merlin_mdio_address[MERLIN_ID_1];
+        ag_drv_lport_srds_dual_serdes_1_cntrl_set(&serdes1_cntrl);
+        UDELAY(10000);
+    } 
+
+    if (disable)
+    {
+        core_vco[core_id] = MERLIN_VCO_UNKNOWN;
+        return LPORT_ERR_OK;
+    }
+
+    /* Check Merlin Driver registration */
+    if (!merlin_callbacks.merlin_core_init)
+    {
+        pr_err("Merlin driver not registered, Failed to init SERDES \n");
+        return LPORT_ERR_STATE;
+    }
+
+    if (merlin_callbacks.merlin_core_init(core_id, vco))
+    {
+        pr_err("%s(%d):merlin_core_init merlin_id=%d failed\n", __FUNCTION__,
+            __LINE__, core_id);
+        return LPORT_ERR_IO;
+    }
+
+    if (serdes_get_pll_lock(core_id))
+        return LPORT_ERR_IO;
+
+    core_vco[core_id] = vco;
+
+    return LPORT_ERR_OK;
+}
+
+#ifdef LPORT_REMOTE_FAULT_HANDLER
+static void *tx_dis_gpio_lane_priv[4];
+static void (*tx_disable_gpio_ctrl)(void *priv, int value);
+
+void lport_serdes_tx_disable_gpio_ctrl_set(void (*_tx_disable_gpio_ctrl)(void *priv, int value))
+{
+    tx_disable_gpio_ctrl = _tx_disable_gpio_ctrl;
+}
+
+int lport_serdes_tx_disable_gpio_assign(int port, void *priv)
+{
+    E_MERLIN_LANE lane_id;
+
+    if (port >= sizeof(port_to_lane)/sizeof(port_to_lane[0]))
+        return -1;
+
+    lane_id = port_to_lane[port];
+    tx_dis_gpio_lane_priv[lane_id] = priv;
+
+    return 0;
+}
+
+static void tx_gpio_enable(E_MERLIN_LANE lane_id, uint32_t enable)
+{
+    if (!tx_disable_gpio_ctrl)
+        return;
+
+    tx_disable_gpio_ctrl(tx_dis_gpio_lane_priv[lane_id], enable ? 0 : 1);
+}
+
+typedef struct
+{
+    struct work_struct base_work;
+    const lport_intr_info_s *info;
+} serdes_work_t;
+
+static void serdes_work_cb(struct work_struct *work)
+{
+    serdes_work_t *serdes_work = container_of(work, serdes_work_t, base_work);
+    uint32_t lane_id = serdes_work->info->entity_id;
+    lport_srds_dual_serdes_0_cntrl serdes0_cntrl;
+    merlin_status_t status = {};
+
+    kfree(serdes_work);
+    msleep(1000);
+
+    ag_drv_lport_srds_dual_serdes_0_cntrl_get(&serdes0_cntrl);
+
+    if (serdes0_cntrl.serdes_reset == 1)
+        return;
+
+    if (merlin_callbacks.merlin_ioctl(lane_id, MERLIN_CMD_STATUS_GET, (merlin_control_t *)&status))
+        return;
+
+    if (status.rx_REMOTE_FAULT)
+    {
+        tx_gpio_enable(lane_id, 0);
+        tx_gpio_enable(lane_id, 1);
+        msleep(1000);
+    }
+
+    lport_intr_clear(LPORT_REMOTE_FAULT, lane_id);
+    lport_intr_enable(LPORT_REMOTE_FAULT, lane_id, 1);
+}
+
+static int serdes_queue_work(const lport_intr_info_s *info)
+{
+    serdes_work_t *serdes_work = kmalloc(sizeof(serdes_work_t), GFP_ATOMIC);
+    if (!serdes_work)
+    {
+        pr_err("serdes_queue_work: kmalloc failed to allocate work struct\n");
+        return -1;
+    }
+
+    INIT_WORK(&serdes_work->base_work, serdes_work_cb);
+    serdes_work->info = info;
+
+    queue_work(system_unbound_wq, &serdes_work->base_work);
+
+    return 0;
+}
+
+static void remote_fault_handler(const lport_intr_info_s *info, void *priv)
+{
+    uint32_t lane_id = info->entity_id;
+
+    lport_intr_enable(LPORT_REMOTE_FAULT, lane_id, 0);
+    lport_intr_clear(LPORT_REMOTE_FAULT, lane_id);
+
+    /* Schedule a work queue to restart the TX laser */
+    if (serdes_queue_work(info))
+    {
+        /* Enable interuupt back in case of failure */
+        lport_intr_enable(LPORT_REMOTE_FAULT, lane_id, 1);
+    }
+}
+
+static void remote_fault_enable(E_MERLIN_LANE lane_id, int enable)
+{
+    if (!(lane_id == MERLIN_LANE_0 || lane_id == MERLIN_LANE_1))
+        return;
+
+    if (enable)
+    {
+        lport_intr_register(LPORT_REMOTE_FAULT, lane_id, remote_fault_handler, NULL);
+        lport_intr_clear(LPORT_REMOTE_FAULT, lane_id);
+        lport_intr_enable(LPORT_REMOTE_FAULT, lane_id, 1);
+    }
+    else
+    {
+        lport_intr_enable(LPORT_REMOTE_FAULT, lane_id, 0);
+        lport_intr_clear(LPORT_REMOTE_FAULT, lane_id);
+        lport_intr_unregister(LPORT_REMOTE_FAULT, lane_id);
+    }
+}
+#else
+void lport_serdes_tx_disable_gpio_ctrl_set(void (*_tx_disable_gpio_ctrl)(void *priv, int value)) { };
+int lport_serdes_tx_disable_gpio_assign(int port, void *priv) { return 0; };
+#endif
+
+static void lane_tx_enable(E_MERLIN_LANE lane_id, int enable)
+{
+#ifdef LPORT_REMOTE_FAULT_HANDLER
+    if (enable)
+    {
+        tx_gpio_enable(lane_id, 1);
+        remote_fault_enable(lane_id, 1);
+    }
+    else
+    {
+        remote_fault_enable(lane_id, 0);
+        tx_gpio_enable(lane_id, 0);
+    }
+#endif
+}
+
+static LPORT_PORT_MUX_SELECT lane_mux[4] = {};
+
+static int merlin_lane_init(E_MERLIN_LANE lane_id, LPORT_PORT_MUX_SELECT prt_mux_sel)
+{
+    E_MERLIN_ID core = lane_to_core[lane_id];
+
+    if (lane_mux[lane_id] == prt_mux_sel)
+        return LPORT_ERR_OK;
+
+    if (core_vco[core] == MERLIN_VCO_UNKNOWN)
+    {
+        lane_mux[lane_id] = PORT_UNAVAIL;
+        return LPORT_ERR_OK;
+    }
+
+    /* Check Merlin Driver registration */
+    if (!merlin_callbacks.merlin_lane_init)
+    {
+        pr_err("Merlin driver not registered, Failed to init SERDES \n");
+        return LPORT_ERR_STATE;
+    }
+
+    if (merlin_callbacks.merlin_lane_init(lane_id, prt_mux_sel))
+    {
+        pr_err("%s(%d):merlin_lane_init lane_id=%d failed\n", __FUNCTION__,
+            __LINE__, lane_id);
+        return LPORT_ERR_IO;
+    }
+
+    lane_mux[lane_id] = prt_mux_sel;
+
+    lane_tx_enable(lane_id, prt_mux_sel != PORT_UNAVAIL);
+
+    return LPORT_ERR_OK;
+}
+
+int port_write_tx_dis_state(uint32_t port, uint32_t state)
+{
+    E_MERLIN_LANE lane_id = port_to_lane[port];
+
+    lane_tx_enable(lane_id, state == 0);
+
+    return 0;
+}
+
+int lport_serdes_init(lport_init_s *init_params)
+{
+    uint32_t i;
+    E_MERLIN_VCO vco[2] = {};
+    LPORT_PORT_MUX_SELECT mux[4] = {};
+
+    for (i = 0; i < LPORT_NUM_OF_PORTS; i++)
+    {
+        LPORT_PORT_MUX_SELECT prt_mux_sel = init_params->prt_mux_sel[i];
+
+        if (LPORT_IS_SERDES_PORT(prt_mux_sel))
+        {
+            E_MERLIN_LANE lane = port_to_lane[i];
+            E_MERLIN_ID core = port_to_core[i];
+
+            mux[lane] = prt_mux_sel;
+            vco[core] = MERLIN_VCO_103125_MHZ;
+        }
+    }
+
+    for (i = 0; i < 2; i++) /* All cores: 0, 1 */ 
+    {
+        merlin_core_init(i, vco[i]);
+    }
+
+    for (i = 0; i < 4; i++) /* All lanes: 0, 1, 2, 3 */
+    {
+        merlin_lane_init(i, mux[i]);
+    }
+
+    return LPORT_ERR_OK;
+}
+
+int lport_serdes_get_status(uint32_t port, lport_port_status_s *port_status)
+{
+    return merlin_callbacks.merlin_get_status(port_to_lane[port], port_status);
+}
+
+int lport_serdes_speed_set(uint32_t port, LPORT_PORT_RATE rate)
+{
+    return merlin_callbacks.merlin_speed_set(port_to_lane[port], rate);
+}
+
+int lport_serdes_set_loopback(uint32_t port, uint32_t loopback_mode, uint32_t enable)
+{
+    merlin_control_t control = {};
+    control.loopback.mode = loopback_mode;
+    control.loopback.enable = enable;
+    return merlin_callbacks.merlin_ioctl(port_to_lane[port], MERLIN_CMD_LOOPBACK_SET, &control);
+}
+
+int lport_serdes_set_tx_cfg(uint32_t port, merlin_tx_cfg_t *tx_cfg)
+{
+    int rc;
+    merlin_control_t control = {};
+
+    control.tx_cfg = *tx_cfg;
+
+    rc = merlin_callbacks.merlin_ioctl(port_to_lane[port], MERLIN_CMD_TXCFG_SET, &control);
+    if (rc)
+    {
+        pr_err("Failed to get merlin command %d \n", rc);
+        goto exit;
+    }
+
+exit:    
+    return rc;
+}
+
+int lport_serdes_get_tx_cfg(uint32_t port, merlin_tx_cfg_t *tx_cfg)
+{
+    int rc;
+    merlin_control_t control = {};
+
+    rc = merlin_callbacks.merlin_ioctl(port_to_lane[port], MERLIN_CMD_TXCFG_GET, &control);
+    if (rc)
+    {
+        pr_err("Failed to get merlin command %d \n", rc);
+        goto exit;
+    }
+
+    *tx_cfg = control.tx_cfg;
+
+exit:    
+    return rc;
+}
+
+int lport_serdes_diag(uint32_t port, uint32_t cmd)
+{
+    int rc;
+    merlin_control_t control = {};
+    merlin_command_t merlin_cmd = cmd == 1 ? MERLIN_CMD_STATUS_GET : cmd == 2 ? MERLIN_CMD_STATS_GET : 0;
+
+    rc = merlin_callbacks.merlin_ioctl(port_to_lane[port], merlin_cmd, &control);
+
+    if (rc)
+    {
+        pr_err("Failed to get merlin command %d \n", rc);
+        goto exit;
+    }
+
+    switch(merlin_cmd)
+    {
+    case MERLIN_CMD_STATUS_GET:
+        pr_info("tx_LOCAL_FAULT: %d\n", control.status.tx_LOCAL_FAULT);
+        pr_info("tx_REMOTE_FAULT: %d\n", control.status.tx_REMOTE_FAULT);
+        pr_info("PMD_LOCK: %d\n", control.status.PMD_LOCK);
+        pr_info("signal_ok: %d\n", control.status.signal_ok);
+        pr_info("rx_LOCAL_FAULT: %d\n", control.status.rx_LOCAL_FAULT);
+        pr_info("rx_REMOTE_FAULT: %d\n", control.status.rx_REMOTE_FAULT);
+        pr_info("rx_LINK_STATUS: %d\n", control.status.rx_LINK_STATUS);
+        pr_info("rx_SYNC_STATUS: %d\n", control.status.rx_SYNC_STATUS);
+        pr_info("pll_lock: %d\n", control.status.pll_lock);
+        break;
+    case MERLIN_CMD_STATS_GET:
+        pr_info("\nkcode66ErrCount: %d\n", control.stats.kcode66ErrCount);
+        pr_info("sync66ErrCount: %d\n", control.stats.sync66ErrCount);
+        pr_info("cl49ieee_errored_blocks: %d\n", control.stats.cl49ieee_errored_blocks);
+        pr_info("BER_count_per_ln: %d\n", control.stats.BER_count_per_ln);
+        pr_info("cl49_valid_sh_cnt: %d\n", control.stats.cl49_valid_sh_cnt);
+        pr_info("cl49_invalid_sh_cnt: %d\n", control.stats.cl49_invalid_sh_cnt);
+        break;
+    default:
+        pr_info("Not implemented yet\n");
+        break;
+    } 
+exit:
+    return rc;
+}
+
+
+int lport_serdes_prbs_generation(uint32_t port, E_SERDES_PRBS_PATTERN_TYPE pattern_type)
+{
+    int rc = 0;
+    merlin_control_t control = {};
+
+    control.prbs_type = (uint16_t)pattern_type;
+
+    rc = merlin_callbacks.merlin_ioctl(port_to_lane[port], MERLIN_CMD_PRBS_GENRATE, &control);
+    if (rc)
+    {
+        pr_err("Failed to get merlin command %d \n", rc);
+        goto exit;
+    }
+
+exit:
+    return rc;
+}
+
+int lport_serdes_prbs_monitor(uint32_t port, E_SERDES_PRBS_PATTERN_TYPE pattern_type)
+{
+    int rc = 0;
+    merlin_control_t control = {};
+
+    control.prbs_type = (uint16_t)pattern_type;
+
+    rc = merlin_callbacks.merlin_ioctl(port_to_lane[port], MERLIN_CMD_PRBS_MONITOR, &control);
+    if (rc)
+    {
+        pr_err("Failed to get merlin command %d \n", rc);
+        goto exit;
+    }
+
+exit:
+    return rc;
+}
+
+int lport_serdes_prbs_stats_get(uint32_t port)
+{
+    int rc;
+    merlin_control_t control = {};
+    rc = merlin_callbacks.merlin_ioctl(port_to_lane[port], MERLIN_CMD_PRBS_STATS_GET, &control);
+    if (rc)
+    {
+        pr_err("Failed to get merlin command %d \n", rc);
+        goto exit;
+    }
+
+    pr_info("prbs_lock_status:0x%x\n", control.prbs_stats.prbs_lock_status);
+    pr_info("prbs_lock_lost:0x%x\n", control.prbs_stats.prbs_lock_lost);
+    pr_info("prbs_error:    0x%x\n", control.prbs_stats.prbs_error);
+
+exit:
+    return rc;
+}
+
+int lport_serdes_read_reg(uint32_t port, uint16_t device_type, uint16_t reg_address)
+{
+    int rc;
+    merlin_control_t control = {};
+
+    control.reg_data.device_type = device_type;
+    control.reg_data.reg_addr = reg_address;
+
+    rc = merlin_callbacks.merlin_ioctl(port_to_lane[port], MERLIN_CMD_REG_READ, &control);
+
+    if (!rc)
+        pr_info("\n 0x%04X: 0x%04X\n", reg_address, control.reg_data.reg_value);
+
+    return rc;
+}
+
+int lport_serdes_write_reg(uint32_t port, uint16_t device_type, uint16_t reg_address, uint16_t value)
+{
+    int rc;
+    merlin_control_t control = {};
+
+    control.reg_data.device_type = device_type;
+    control.reg_data.reg_addr = reg_address;
+    control.reg_data.reg_value = value;
+
+    rc = merlin_callbacks.merlin_ioctl(port_to_lane[port], MERLIN_CMD_REG_WRITE, &control);
+
+    return rc;
+}
diff --git a/drivers/net/bcmbca/lport/serdes_access.h b/drivers/net/bcmbca/lport/serdes_access.h
new file mode 100644
index 0000000000..22beec7a28
--- /dev/null
+++ b/drivers/net/bcmbca/lport/serdes_access.h
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+   
+   */
+/*
+
+ * serdes_access.h
+ *
+ *  Created on: August 2015
+ *      Author: yonatani
+ */
+
+#ifndef SHARED_OPENSOURCE_DRV_LPORT_SERDES_ACCESS_H_
+#define SHARED_OPENSOURCE_DRV_LPORT_SERDES_ACCESS_H_
+
+#include "lport_defs.h"
+
+typedef enum {
+    MERLIN_ID_0,
+    MERLIN_ID_1
+} E_MERLIN_ID;
+
+typedef enum {
+    MERLIN_LANE_0,
+    MERLIN_LANE_1,
+    MERLIN_LANE_2,
+    MERLIN_LANE_3
+} E_MERLIN_LANE;
+
+typedef enum {
+    MERLIN_VCO_UNKNOWN,
+    MERLIN_VCO_9375_MHZ,
+    MERLIN_VCO_103125_MHZ
+} E_MERLIN_VCO;
+
+typedef enum {
+    SERDES_PRBS_PATTERN_TYPE_PRBS7,
+    SERDES_PRBS_PATTERN_TYPE_PRBS9,
+    SERDES_PRBS_PATTERN_TYPE_PRBS11,
+    SERDES_PRBS_PATTERN_TYPE_PRBS15,
+    SERDES_PRBS_PATTERN_TYPE_PRBS23,
+    SERDE_SPRBS_PATTERN_TYPE_PRBS31,
+    SERDE_SPRBS_PATTERN_TYPE_PRBS58,
+    SERDES_PRBS_PATTERN_TYPE_8180,
+    SERDES_PRBS_PATTERN_TYPE_LAST,
+} E_SERDES_PRBS_PATTERN_TYPE;
+
+/* TODO move to separate include*/
+typedef enum {
+    MERLIN_CMD_STATS_GET,
+    MERLIN_CMD_STATUS_GET,
+    MERLIN_CMD_FORCE_LINK_DOWN,
+    MERLIN_CMD_FORCE_LINK_UP,
+    MERLIN_CMD_PRBS_STATS_GET,
+    MERLIN_CMD_PRBS_GENRATE,
+    MERLIN_CMD_PRBS_MONITOR,
+    MERLIN_CMD_ID,
+    MERLIN_CMD_REG_WRITE,
+    MERLIN_CMD_REG_READ,
+    MERLIN_CMD_LOOPBACK_SET,
+    MERLIN_CMD_TXCFG_SET,
+    MERLIN_CMD_TXCFG_GET
+} merlin_command_t;
+
+typedef enum {
+    MERLIN_LOOPBACK_NONE = 0,
+    MERLIN_PCS_LOCAL_LOOPBACK,
+    MERLIN_PCS_REMOTE_LOOPBACK,
+    MERLIN_PMD_LOCAL_LOOPBACK,
+    MERLIN_PMD_REMOTE_LOOPBACK 
+} merlin_loopback_mode;
+
+typedef struct {
+    uint16_t tx_LOCAL_FAULT;
+    uint16_t tx_REMOTE_FAULT;
+    uint16_t PMD_LOCK;
+    uint16_t signal_ok;
+    uint16_t rx_LOCAL_FAULT;
+    uint16_t rx_REMOTE_FAULT;
+    uint16_t rx_LINK_STATUS;
+    uint16_t rx_SYNC_STATUS;
+    uint16_t pll_lock;
+} merlin_status_t;
+
+
+typedef struct {
+    uint16_t kcode66ErrCount;
+    uint16_t sync66ErrCount;
+    uint16_t cl49ieee_errored_blocks;
+    uint16_t BER_count_per_ln;
+    uint16_t cl49_valid_sh_cnt;
+    uint16_t cl49_invalid_sh_cnt;
+} merlin_stats_t;
+
+typedef struct {
+    uint32_t prbs_error;
+    uint16_t prbs_lock_lost;
+    uint16_t prbs_lock_status;
+} merlin_prbs_stats_t;
+
+
+typedef struct {
+    uint16_t rev_letter;
+    uint16_t rev_number;
+    uint16_t bonding;
+    uint16_t tech_proc;
+    uint16_t model_number;
+} merlin_serdes_id_t;
+
+typedef struct {
+    uint16_t device_type;
+    uint16_t reg_addr;
+    uint16_t reg_value;
+} merlin_reg_access_t;
+
+typedef struct {
+    merlin_loopback_mode mode;
+    uint8_t enable;
+} merlin_loopback_set_t;
+
+typedef struct {
+    uint16_t pre;
+    uint16_t main;
+    uint16_t post1;
+    uint16_t post2;
+    uint16_t post2to1;
+    uint16_t en_pre;
+    uint16_t en_post1;
+    uint16_t en_post2;
+    uint16_t tx_refcalshunt;
+    uint16_t hpf;
+} merlin_tx_cfg_t;
+
+typedef union {
+    merlin_status_t status;
+    merlin_stats_t  stats;
+    merlin_prbs_stats_t prbs_stats;
+    merlin_serdes_id_t serdes_id;
+    uint16_t val;
+    uint16_t prbs_type;
+    merlin_reg_access_t reg_data;
+    merlin_loopback_set_t loopback;
+    merlin_tx_cfg_t tx_cfg;
+} merlin_control_t;
+
+
+typedef int (*merlin_core_init_cb)(E_MERLIN_ID core_id, E_MERLIN_VCO vco);
+typedef int (*merlin_lane_init_cb)(E_MERLIN_LANE lane_id, LPORT_PORT_MUX_SELECT mux_sel);
+typedef int (*merlin_speed_set_cb)(E_MERLIN_LANE lane_id, LPORT_PORT_RATE port_rate);
+typedef int (*merlin_get_status_cb)(E_MERLIN_LANE lane_index, lport_port_status_s *port_status);
+typedef int (*merlin_ioctl_cb)(E_MERLIN_LANE lane_id, merlin_command_t cmd, merlin_control_t *data);
+
+typedef struct {
+    merlin_core_init_cb merlin_core_init;
+    merlin_lane_init_cb merlin_lane_init;
+    merlin_speed_set_cb merlin_speed_set;
+    merlin_get_status_cb merlin_get_status;
+    merlin_ioctl_cb merlin_ioctl;
+} merlin_sdk_cb_s;
+
+int write_serdes_reg(E_MERLIN_ID merlin_id, uint32_t addr,uint16_t mask,uint16_t value);
+int read_serdes_reg(E_MERLIN_ID merlin_id, uint32_t addr, uint16_t mask,uint16_t *value);
+int lport_serdes_init(lport_init_s *init_params);
+int lport_serdes_get_status(uint32_t port, lport_port_status_s *port_status);
+int lport_serdes_speed_set(uint32_t port, LPORT_PORT_RATE rate);
+int lport_serdes_set_tx_cfg(uint32_t port, merlin_tx_cfg_t *tx_cfg);
+int lport_serdes_get_tx_cfg(uint32_t port, merlin_tx_cfg_t *tx_cfg);
+
+/* Control SFP TX disable GPIO state */
+int port_write_tx_dis_state(uint32_t port, uint32_t state);
+
+
+/* 
+    Generation MPRBB pattern on SERDES Port
+    MPRB Pattern are:
+        PRBS7|PRBS9|PRBS11|PRBS15|PRBS23|PRBS31|PRBS58|8180
+*/
+int lport_serdes_prbs_generation(uint32_t port,E_SERDES_PRBS_PATTERN_TYPE pattern_type);
+/* 
+    Monitor MPRBB pattern on SERDES Port
+    MPRB Pattern are:
+        PRBS7|PRBS9|PRBS11|PRBS15|PRBS23|PRBS31|PRBS58|
+*/
+int lport_serdes_prbs_monitor(uint32_t port, E_SERDES_PRBS_PATTERN_TYPE pattern_type);
+
+/* Get Counter Ststistics after ebable MPRB */
+int lport_serdes_prbs_stats_get(uint32_t port);
+
+#endif /* SHARED_OPENSOURCE_DRV_LPORT_SERDES_ACCESS_H_ */
diff --git a/drivers/net/bcmbca/mii_shared.h b/drivers/net/bcmbca/mii_shared.h
new file mode 100755
index 0000000000..1e0ad221cf
--- /dev/null
+++ b/drivers/net/bcmbca/mii_shared.h
@@ -0,0 +1,371 @@
+/*  *********************************************************************
+    *  Broadcom Common Firmware Environment (CFE)
+    *  
+    *  MII register definitions			File: mii.h
+    *  
+    *  Register and bit definitions for the standard MII management
+    *  interface.
+    *  
+    *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
+    *  
+    *********************************************************************  
+    *
+    *  Copyright 2000,2001,2002,2003
+    *  Broadcom Corporation. All rights reserved.
+    *  
+    *  This software is furnished under license and may be used and 
+    *  copied only in accordance with the following terms and 
+    *  conditions.  Subject to these conditions, you may download, 
+    *  copy, install, use, modify and distribute modified or unmodified 
+    *  copies of this software in source and/or binary form.  No title 
+    *  or ownership is transferred hereby.
+    *  
+    *  1) Any source code used, modified or distributed must reproduce 
+    *     and retain this copyright notice and list of conditions 
+    *     as they appear in the source file.
+    *  
+    *  2) No right is granted to use any trade name, trademark, or 
+    *     logo of Broadcom Corporation.  The "Broadcom Corporation" 
+    *     name may not be used to endorse or promote products derived 
+    *     from this software without the prior written permission of 
+    *     Broadcom Corporation.
+    *  
+    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
+    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
+    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 
+    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 
+    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
+    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 
+    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 
+    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 
+    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 
+    *     THE POSSIBILITY OF SUCH DAMAGE.
+    ********************************************************************* */
+
+#ifndef _MII_H_
+#define _MII_H_
+
+/* Access/command codes */
+
+#define	MII_COMMAND_START	0x01
+#define	MII_COMMAND_READ	0x02
+#define	MII_COMMAND_WRITE	0x01
+#define	MII_COMMAND_ACK		0x02
+
+/* Registers */
+
+#define	MII_BMCR	0x00	/* Basic Mode Control (rw) */
+#define	MII_BMSR	0x01	/* Basic Mode Status (ro) */
+#define MII_PHYIDR1	0x02
+#define MII_PHYIDR2	0x03
+#define MII_ANAR	0x04	/* Autonegotiation Advertisement */
+#define	MII_ANLPAR	0x05	/* Autonegotiation Link Partner Ability (rw) */
+#define MII_ANER	0x06	/* Autonegotiation Expansion */
+#define MII_K1CTL	0x09	/* 1000baseT control */
+#define MII_K1STSR	0x0A	/* 1K Status Register (ro) */
+#define MII_AUXCTL	0x18	/* aux control register */
+#define MII_AUXSTA  0x19	/* aux status register */
+
+/* Basic Mode Control register (RW) */
+
+#define BMCR_RESET		0x8000
+#define BMCR_LOOPBACK		0x4000
+#define BMCR_SPEED0		0x2000
+#define BMCR_ANENABLE		0x1000
+#define BMCR_POWERDOWN		0x0800
+#define BMCR_ISOLATE		0x0400
+#define BMCR_RESTARTAN		0x0200
+#define BMCR_DUPLEX		0x0100
+#define BMCR_COLTEST		0x0080
+#define BMCR_SPEED1		0x0040
+#define BMCR_SPEED1000		(BMCR_SPEED1)
+#define BMCR_SPEED100		(BMCR_SPEED0)
+#define BMCR_SPEED10		0
+
+/* Basic Mode Status register (RO) */
+
+#define BMSR_100BT4		0x8000
+#define BMSR_100BT_FDX		0x4000
+#define BMSR_100BT_HDX  	0x2000
+#define BMSR_10BT_FDX   	0x1000
+#define BMSR_10BT_HDX   	0x0800
+#define BMSR_100BT2_FDX 	0x0400
+#define BMSR_100BT2_HDX 	0x0200
+#define BMSR_1000BT_XSR		0x0100
+#define BMSR_PRESUP		0x0040
+#define BMSR_ANCOMPLETE		0x0020
+#define BMSR_REMFAULT		0x0010
+#define BMSR_AUTONEG		0x0008
+#define BMSR_LINKSTAT		0x0004
+#define BMSR_JABDETECT		0x0002
+#define BMSR_EXTCAPAB		0x0001
+
+/* PHY Identifer registers (RO) */
+
+#define PHYIDR1 		0x2000
+#define PHYIDR2			0x5C60
+
+/* Autonegotiation Advertisement register (RW) */
+
+#define ANAR_NP			0x8000
+#define ANAR_RF			0x2000
+#define ANAR_ASYPAUSE		0x0800
+#define ANAR_PAUSE		0x0400
+#define ANAR_T4			0x0200
+#define ANAR_TXFD		0x0100
+#define ANAR_TXHD		0x0080
+#define ANAR_10FD		0x0040
+#define ANAR_10HD		0x0020
+#define ANAR_PSB		0x001F
+
+#define PSB_802_3		0x0001	/* 802.3 */
+
+/* Autonegotiation Link Partner Abilities register (RW) */
+
+#define ANLPAR_NP		0x8000
+#define ANLPAR_ACK		0x4000
+#define ANLPAR_RF		0x2000
+#define ANLPAR_ASYPAUSE		0x0800
+#define ANLPAR_PAUSE		0x0400
+#define ANLPAR_T4		0x0200
+#define ANLPAR_TXFD		0x0100
+#define ANLPAR_TXHD		0x0080
+#define ANLPAR_10FD		0x0040
+#define ANLPAR_10HD		0x0020
+#define ANLPAR_PSB		0x001F
+
+/* Autonegotiation Expansion register (RO) */
+
+#define ANER_PDF		0x0010
+#define ANER_LPNPABLE		0x0008
+#define ANER_NPABLE		0x0004
+#define ANER_PAGERX		0x0002
+#define ANER_LPANABLE		0x0001
+
+#define ANNPTR_NP		0x8000
+#define ANNPTR_MP		0x2000
+#define ANNPTR_ACK2		0x1000
+#define ANNPTR_TOGTX		0x0800
+#define ANNPTR_CODE		0x0008
+
+#define ANNPRR_NP		0x8000
+#define ANNPRR_MP		0x2000
+#define ANNPRR_ACK3		0x1000
+#define ANNPRR_TOGTX		0x0800
+#define ANNPRR_CODE		0x0008
+
+#define K1TCR_TESTMODE		0x0000
+#define K1TCR_MSMCE		0x1000
+#define K1TCR_MSCV		0x0800
+#define K1TCR_RPTR		0x0400
+#define K1TCR_1000BT_FDX 	0x200
+#define K1TCR_1000BT_HDX 	0x100
+
+#define K1STSR_MSMCFLT		0x8000
+#define K1STSR_MSCFGRES		0x4000
+#define K1STSR_LRSTAT		0x2000
+#define K1STSR_RRSTAT		0x1000
+#define K1STSR_LP1KFD		0x0800
+#define K1STSR_LP1KHD   	0x0400
+#define K1STSR_LPASMDIR		0x0200
+
+#define K1SCR_1KX_FDX		0x8000
+#define K1SCR_1KX_HDX		0x4000
+#define K1SCR_1KT_FDX		0x2000
+#define K1SCR_1KT_HDX		0x1000
+
+/*---------------------------------------------------------------------*/
+/* Broadcom PHY MII register address                                   */
+/* use when PhyType is BP_ENET_INTERNAL_PHY                            */
+/*---------------------------------------------------------------------*/
+#define MII_ASR                             0x19
+#define MII_INTERRUPT                       0x1A
+#define MII_RESERVED_1B                     0x1B
+#define MII_BRCM_TEST                       0x1F
+
+/* MII ASR register. */
+#define MII_ASR_DONE(r) ((r & 0x8000) != 0)
+#define MII_ASR_LINK(r) ((r & 0x0004) != 0)
+#define MII_ASR_FDX(r)  (((r & 0x0700) == 0x0700) || ((r & 0x0700) == 0x0500) || ((r & 0x0700) == 0x0200))
+#define MII_ASR_1000(r) (((r & 0x0700) == 0x0700) || ((r & 0x0700) == 0x0600))
+#define MII_ASR_100(r)  (((r & 0x0700) == 0x0500) || ((r & 0x0700) == 0x0300))
+#define MII_ASR_10(r)   (((r & 0x0700) == 0x0200) || ((r & 0x0700) == 0x0100))
+
+/* Reserved 0x1B register */
+#define MII_RESERVED_1B_ACT_LED             0x0004
+
+/* Broadcom Test register. */
+#define MII_BRCM_TEST_SHADOW2_ENABLE        0x0004
+
+/* MII Interrupt register. */
+#define MII_INTR_ENABLE                     0x4000
+
+#define BCM50612_PHYID2  0x5E60
+#define BCM54610_PHYID2  0xBD63
+#define BCM_PHYID_M      0xFFF0
+
+#define MII_REGISTER_1C                     0x1c
+#define MII_1C_WRITE_ENABLE             (1 << 15)
+#define MII_1C_SHADOW_REG_SEL_S         10
+#define MII_1C_SHADOW_REG_SEL_M         0x1F
+#define MII_1C_SHADOW_CLK_ALIGN_CTRL        0x3
+#define GTXCLK_DELAY_BYPASS_DISABLE     (1 << 9)
+#define MII_1C_SHADOW_LED_CONTROL           0x9
+#define ACT_LINK_LED_ENABLE             (1 << 4)
+#define MII_1C_EXTERNAL_CONTROL_1           0xB
+#define LOM_LED_MODE                    (1 << 2)
+#define RGMII_MODE_SEL_M                0x3
+#define RGMII_MODE_SEL_S                3
+#define RGMII_MODE_3P3V                 0x0
+#define RGMII_MODE_2P5V                 0x1
+#define RGMII_MODE_1P8V                 0x2
+
+#define PAGE_CONTROL                        0x00
+#define PORT_CTRL_PORT                      0
+#define PORT_CTRL_PORT_STATUS_S         5
+#define PORT_CTRL_PORT_STATUS_M         (7<<PORT_CTRL_PORT_STATUS_S)
+#define PORT_CTRL_NO_STP                (0<<PORT_CTRL_PORT_STATUS_S)
+#define PORT_CTRL_PORT_FORWARDING       (5<<PORT_CTRL_PORT_STATUS_S)
+#define PORT_CTRL_SWITCH_RESERVE        (7<<2)
+#define PORT_CTRL_TX_DISABLE            0x2
+#define PORT_CTRL_RX_DISABLE            0x1
+#define PORT_CTRL_RXTX_DISABLE          (PORT_CTRL_TX_DISABLE|PORT_CTRL_RX_DISABLE)
+#define SOFTWARE_RESET_CTRL                 0x79
+#define SOFTWARE_RESET                  (1<<7)
+#define EN_SW_RST                       (1<<4)
+
+#define PAGE_SELECT                         0xff
+
+/* Control page registers */
+#define REG_MII_PORT_CONTROL                0x08
+#define REG_SWITCH_MODE                     0x0b
+#define REG_CONTROL_MII1_PORT_STATE_OVERRIDE 0x0e
+#define REG_POWER_DOWN_MODE                 0x0f
+
+#define REG_CONTROL_MPSO_MII_SW_OVERRIDE          0x80
+#define REG_CONTROL_MPSO_FLOW_CONTROL             0x30
+/* Below two bits : bit03:02 for speed */
+#define REG_CONTROL_MPSO_SPEED100                 0x04
+#define REG_CONTROL_MPSO_SPEED1000                0x08
+#define REG_CONTROL_MPSO_FDX                      0x02
+#define REG_CONTROL_MPSO_LINKPASS                 0x01
+
+/* MII Port Control Register, Page 0x00 Address 0x08 */
+#define REG_MII_PORT_CONTROL_RX_UCST_EN           0x10
+#define REG_MII_PORT_CONTROL_RX_MCST_EN           0x08
+#define REG_MII_PORT_CONTROL_RX_BCST_EN           0x04
+
+/* Switch mode register, Page 0x00 Address 0x0b */
+#define REG_SWITCH_MODE_FRAME_MANAGE_MODE   0x01
+#define REG_SWITCH_MODE_SW_FWDG_EN          0x02
+#define REG_SWITCH_MODE_RETRY_LIMIT_DIS     0x04
+
+/* MII1 Port State Override Register Page 0x00 Address 0x0e */
+#define REG_CONTROL_MPSO_MII_SW_OVERRIDE    0x80
+#define REG_CONTROL_MPSO_REVERSE_MII        0x10
+#define REG_CONTROL_MPSO_LP_FLOW_CONTROL    0x08
+#define REG_CONTROL_MPSO_TX_FLOW_CONTROL    0x20
+#define REG_CONTROL_MPSO_RX_FLOW_CONTROL    0x10
+#define REG_CONTROL_MPSO_SPEED100           0x04
+#define REG_CONTROL_MPSO_SPEED1000          0x08
+#define REG_CONTROL_MPSO_FDX                0x02
+#define REG_CONTROL_MPSO_LINKPASS           0x01
+
+/* Power down mode register Page 0x00 Address 0x0f */
+#define REG_POWER_DOWN_MODE_PORT1_PHY_DISABLE     0x01
+#define REG_POWER_DOWN_MODE_PORT2_PHY_DISABLE     0x02
+#define REG_POWER_DOWN_MODE_PORT3_PHY_DISABLE     0x04
+#define REG_POWER_DOWN_MODE_PORT4_PHY_DISABLE     0x08
+#define REG_POWER_DOWN_MODE_PORT5_PHY_DISABLE     0x10
+
+/* Switch control register page 0x0 */
+#define REG_SWITCH_CONTROL                  0x22
+#define REG_SWITCH_CONTROL_MII_DUMP_FWD_EN  0x40
+
+#define PAGE_STATUS                         0x01
+#define REG_STRAP_VAL                               0x70
+#define REG_STRAP_P8_SEL_SGMII                      1<<9
+
+#define PAGE_MANAGEMENT                     0x02
+/* Device ID register page 0x02 */
+#define REG_DEVICE_ID                       0x30
+#define REG_GLOBAL_CONFIG                   0x00
+#define REG_BRCM_HDR_CTRL                   0x03
+
+/* Global Configuration Regiater Page 0x02 Address 0x00 */
+#define ENABLE_MII_PORT                     0x80
+
+/* Broadcom Header Control Register Page 0x02 Address 0x03*/
+#define REG_BRCM_HDR_ENABLE                 0x01
+
+#define PAGE_PORT_BASED_VLAN                0x31
+#define REG_VLAN_CTRL_P0                    0x00
+
+/*---------------------------------------------------------------------*/
+/* 5325 Switch SPI Interface                                           */
+/* use when configuration type is BP_ENET_CONFIG_SPI_SSB_x             */
+/*---------------------------------------------------------------------*/
+#define BCM5325_SPI_CMD_LEN                 1
+#define BCM5325_SPI_ADDR_LEN                1
+#define BCM5325_SPI_PREPENDCNT              (BCM5325_SPI_CMD_LEN+BCM5325_SPI_ADDR_LEN)
+
+/* 5325 SPI Status Register */
+#define BCM5325_SPI_STS                     0xfe
+
+/* 5325 SPI Status Register definition */
+#define BCM5325_SPI_CMD_SPIF                0x80
+#define BCM5325_SPI_CMD_RACK                0x20
+
+/* 5325 Command Byte definition */
+#define BCM5325_SPI_CMD_READ                0x00	/* bit 0 - Read/Write */
+#define BCM5325_SPI_CMD_WRITE               0x01	/* bit 0 - Read/Write */
+#define BCM5325_SPI_CHIPID_MASK             0x7	/* bit 3:1 - Chip ID */
+#define BCM5325_SPI_CHIPID_SHIFT            1
+#define BCM5325_SPI_CMD_NORMAL              0x60	/* bit 7:4 - Mode */
+#define BCM5325_SPI_CMD_FAST                0x10	/* bit 4 - Mode */
+
+/*---------------------------------------------------------------------*/
+/* 5325 Switch Pseudo PHY MII Register                                 */
+/* use when configuration type is BP_ENET_CONFIG_MDIO_PSEUDO_PHY       */
+/*---------------------------------------------------------------------*/
+#define PSEUDO_PHY_ADDR             0x1e	/* Pseduo PHY address */
+
+/* Pseudo PHY MII registers */
+#define REG_PSEUDO_PHY_MII_REG16    0x10	/* register 16 - Switch Register Set Access Control Register */
+#define REG_PSEUDO_PHY_MII_REG17    0x11	/* register 17 - Switch Register Set Read/Write Control Register */
+#define REG_PSEUDO_PHY_MII_REG24    0x18	/* register 24 - Switch Accesss Register bit 15:0 */
+#define REG_PSEUDO_PHY_MII_REG25    0x19	/* register 25 - Switch Accesss Register bit 31:16 */
+#define REG_PSEUDO_PHY_MII_REG26    0x20	/* register 26 - Switch Accesss Register bit 47:32 */
+#define REG_PSEUDO_PHY_MII_REG27    0x21	/* register 27 - Switch Accesss Register bit 63:48 */
+
+/*Pseudo PHY MII register 16 Switch Register Set Access Control Register */
+#define REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT  8	/* bit 8..15 - switch page number */
+#define REG_PPM_REG16_MDIO_ENABLE               0x01	/* bit 0 - set MDC/MDIO access enable */
+
+/*Pseudo PHY MII register 17 Switch Register Set Read/Write Control Register */
+#define REG_PPM_REG17_REG_NUMBER_SHIFT          8	/* bit 8..15 - switch register number */
+#define REG_PPM_REG17_OP_DONE       0x00	/* bit 0..1 - no operation */
+#define REG_PPM_REG17_OP_WRITE      0x01	/* bit 0..1 - write operation */
+#define REG_PPM_REG17_OP_READ       0x02	/* bit 0..1 - read operation */
+
+/****************************************************************************
+    Broadcom Extended PHY registers
+****************************************************************************/
+#define BRCM_MIIEXT_BANK            0x1f
+#define BRCM_MIIEXT_BANK_MASK       0xfff0
+#define BRCM_MIIEXT_ADDR_RANGE      0xffe0
+#define BRCM_MIIEXT_DEF_BANK        0x8000
+#define BRCM_MIIEXT_OFFSET          0x10
+#define BRCM_MIIEXT_OFF_MASK    0xf
+
+uint32_t mii_read(uint32_t uPhyAddr, uint32_t uRegAddr);
+void mii_write(uint32_t uPhyAddr, uint32_t uRegAddr, uint32_t data);
+
+#define K1CTL_REPEATER_DTE	0x400
+#define K1CTL_1000BT_FDX 	0x200
+#define K1CTL_1000BT_HDX 	0x100
+
+#endif /* _MII_H_ */
diff --git a/drivers/net/bcmbca/phy/Makefile b/drivers/net/bcmbca/phy/Makefile
new file mode 100644
index 0000000000..d670f53d0a
--- /dev/null
+++ b/drivers/net/bcmbca/phy/Makefile
@@ -0,0 +1,99 @@
+BRCM_CHIP = $(patsubst "bcm%",%,$(CONFIG_SYS_SOC))
+BCMBCA_PATH = $(srctree)/drivers/net/bcmbca
+
+EXTRA_CFLAGS += -I$(BCMBCA_PATH)/phy
+EXTRA_CFLAGS += -I$(BCMBCA_PATH)/lport
+EXTRA_CFLAGS += -I$(BCMBCA_PATH)/lport/ag
+EXTRA_CFLAGS += -I$(BCMBCA_PATH)/xrdp
+EXTRA_CFLAGS += -I$(srctree)/include/dt-bindings/leds
+
+EXTRA_CFLAGS += -DCONFIG_BCM9$(BRCM_CHIP) -D_BYTE_ORDER_LITTLE_ENDIAN_
+
+ifneq ($(findstring _$(strip $(BRCM_CHIP))_,_6846_6856_6878_),)
+    DRV_OBJS += unimac_drv_impl1.o
+endif
+ifneq ($(findstring _$(strip $(BRCM_CHIP))_,_63146_4912_),)
+    DRV_OBJS += unimac_drv_impl2.o
+endif
+
+ifneq ($(findstring _$(strip $(BRCM_CHIP))_,_6858_6846_6856_6878_63146_4912_),)
+    DRV_OBJS += mac_drv.o
+    DRV_OBJS += bus_drv.o
+    DRV_OBJS += phy_drv.o
+    DRV_OBJS += phy_drv_mii.o
+    DRV_OBJS += phy_drv_brcm.o
+    DRV_OBJS += dt_access.o
+    DRV_OBJS += dt_parsing.o
+ifeq ($(strip ${BRCM_CHIP}),6858)
+    DRV_OBJS += bus_drv_6858.o
+    DRV_OBJS += mac_drv_lport.o
+    DRV_OBJS += phy_drv_6858_egphy.o
+    DRV_OBJS += phy_drv_ext1.o
+    DRV_OBJS += phy_drv_ext2.o
+    DRV_OBJS += phy_drv_ext3.o
+    DRV_OBJS += phy_drv_lport_serdes.o
+    EXTRA_CFLAGS += -DMAC_LPORT
+    EXTRA_CFLAGS += -DPHY_6858_EGPHY -DPHY_EXT1 -DPHY_EXT2 -DPHY_EXT3 -DPHY_LPORT_SERDES
+    EXTRA_CFLAGS += -DLPORT_SERDES_POWER_SAVING -DLPORT_SERDES_SPEED_DETECT -DLPORT_SERDES_EXTERNAL_SIGNAL_DETECT
+endif
+ifeq ($(strip ${BRCM_CHIP}),6856)
+    DRV_OBJS += mdio_drv_common.o
+    DRV_OBJS += mdio_drv_impl5.o
+    DRV_OBJS += bus_drv_mdio_v1.o
+    DRV_OBJS += mac_drv_unimac.o
+    DRV_OBJS += phy_drv_6846_egphy.o
+    DRV_OBJS += phy_drv_6856_sgmii.o
+    DRV_OBJS += phy_drv_sgmii_plus2.o
+    DRV_OBJS += phy_drv_ext1.o
+    DRV_OBJS += phy_drv_ext3.o
+    DRV_OBJS += brcm_rgmii.o
+    EXTRA_CFLAGS += -DBRCM_RGMII
+    EXTRA_CFLAGS += -DMAC_UNIMAC
+    EXTRA_CFLAGS += -DPHY_6846_EGPHY -DPHY_6856_SGMII -DPHY_EXT1 -DPHY_EXT3 
+endif
+ifeq ($(strip ${BRCM_CHIP}),6846)
+    DRV_OBJS += mdio_drv_common.o
+    DRV_OBJS += mdio_drv_impl5.o
+    DRV_OBJS += bus_drv_mdio_v1.o
+    DRV_OBJS += mac_drv_unimac.o
+    DRV_OBJS += phy_drv_6846_egphy.o
+    DRV_OBJS += phy_drv_ext1.o
+    DRV_OBJS += brcm_rgmii.o
+    EXTRA_CFLAGS += -DBRCM_RGMII
+    EXTRA_CFLAGS += -DMAC_UNIMAC
+    EXTRA_CFLAGS += -DPHY_6846_EGPHY -DPHY_EXT1
+endif
+ifeq ($(strip ${BRCM_CHIP}),6878)
+    DRV_OBJS += mdio_drv_common.o
+    DRV_OBJS += mdio_drv_impl5.o
+    DRV_OBJS += bus_drv_mdio_v1.o
+    DRV_OBJS += mac_drv_unimac.o
+    DRV_OBJS += phy_drv_6846_egphy.o
+    DRV_OBJS += xrdp_led_init.o
+    DRV_OBJS += phy_drv_ext1.o
+    DRV_OBJS += brcm_rgmii.o
+    EXTRA_CFLAGS += -DBRCM_RGMII
+    EXTRA_CFLAGS += -DMAC_UNIMAC
+    EXTRA_CFLAGS += -DPHY_6846_EGPHY -DPHY_EXT1 -DXRDP_LED
+endif
+ifneq ($(findstring _$(strip $(BRCM_CHIP))_,_63146_4912_),)
+    # FIXME! Complete the phy drv
+    DRV_OBJS += mdio_drv_common.o
+    DRV_OBJS += mdio_drv_impl5.o
+    DRV_OBJS += bus_drv_mdio_v1.o
+    DRV_OBJS += mac_drv_unimac.o
+    DRV_OBJS += phy_drv_63146_egphy.o
+    DRV_OBJS += ephy_led_init.o
+    #DRV_OBJS += phy_drv_ext1.o
+    EXTRA_CFLAGS += -DMAC_UNIMAC
+    EXTRA_CFLAGS += -DPHY_63146_EGPHY -DEPHY_LED
+    #EXTRA_CFLAGS += -DPHY_EXT1
+ifeq ($(strip ${BRCM_CHIP}),63146)
+    # 4912 doesn't have SGPHY. It only has QGPHY
+    EXTRA_CFLAGS += -DPHY_63146_EGPHY_WITH_SGPHY
+endif
+endif
+endif
+
+obj-y += DRV_OBJS
+
diff --git a/drivers/net/bcmbca/phy/blackfin_a0_firmware.h b/drivers/net/bcmbca/phy/blackfin_a0_firmware.h
new file mode 100644
index 0000000000..760e72d40a
--- /dev/null
+++ b/drivers/net/bcmbca/phy/blackfin_a0_firmware.h
@@ -0,0 +1,9226 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Feb 2018
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Firmware for external 2.5G/5G/10G phys: Blackfin BCM8489x, BCM5499x
+ */
+
+char blackfin_a0_version[] = "Blackfin A0 v00-02-04-2018-05-10";
+
+uint32_t blackfin_a0_firmware[] = {
+    0xea000017, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe320f000, 0xe59ff018, 0xe59ff018, 
+    0x000004ac, 0x000297e0, 0x00029734, 0x00028a68, 0x0002834c, 0x00000000, 0x00028710, 0x000284b0, 
+    0x0002d418, 0xc0de512e, 0x00000000, 0x00000000, 0x00000000, 0x0002d418, 0x00004002, 0x00000000, 
+    0xf1205a2d, 0xe59f13a4, 0xe5910000, 0xe3800102, 0xe5810000, 0xe59f1398, 0xe3040440, 0xe1c100b0, 
+    0xe59f0390, 0xe5901000, 0xe3110010, 0x0a000003, 0xe7c0101f, 0xe7c4121f, 0xe59f037c, 0xe5801000, 
+    0xe3a00064, 0xe2500001, 0xe3500000, 0x1afffffc, 0xe59f0368, 0xe3a01004, 0xe580102c, 0xe59f0360, 
+    0xe1d090b0, 0xe3190001, 0x1a00008d, 0xe59f0354, 0xe3a02010, 0xe3822020, 0xe1d010b0, 0xe0013002, 
+    0xe1530002, 0x1afffffb, 0xe201300f, 0xe59f5338, 0xe3a06055, 0xe1c560b0, 0xe59f0330, 0xe1d010b0, 
+    0xe3c11d0f, 0xe1a02303, 0xe2022d0f, 0xe1811002, 0xe59f031c, 0xe1c010b0, 0xe59f0318, 0xe1d010b0, 
+    0xe3c11001, 0xe1a021a3, 0xe1a02002, 0xe2022001, 0xe1811002, 0xe59f0300, 0xe1c010b0, 0xe59f02fc, 
+    0xe1d010b0, 0xe3c11a0e, 0xe1a02683, 0xe2022a0e, 0xe1811002, 0xe59f02e8, 0xe1c010b0, 0xe59f02e4, 
+    0xe1d010b0, 0xe3c11a0f, 0xe1a02603, 0xe2022a0f, 0xe1811002, 0xe59f02d0, 0xe1c010b0, 0xe59f02cc, 
+    0xe1d010b0, 0xe3c11b0f, 0xe3c1100f, 0xe1a02503, 0xe2022b0f, 0xe1811002, 0xe1a02003, 0xe202200f, 
+    0xe1811002, 0xe59f02a8, 0xe1c010b0, 0xe3a060c3, 0xe1c560b0, 0xe59f029c, 0xe3a01000, 0xe1c010b0, 
+    0xe35600c3, 0x1a000001, 0xe3a0100a, 0xea000000, 0xe3a01004, 0xe59f0280, 0xe1c010b0, 0xe59f027c, 
+    0xe1d000b0, 0xe3100b01, 0x0a00000e, 0xe3100b02, 0x0a00000c, 0xe59f0268, 0xe3051510, 0xe1c010b0, 
+    0xe59f0260, 0xe30c1ccc, 0xe1c010b0, 0xe59f0258, 0xe3011510, 0xe1c010b0, 0xe59f0250, 0xe30c1d09, 
+    0xe1c010b0, 0xea000003, 0xe59f0234, 0xe3051508, 0xe1c010b0, 0xeaffffff, 0xe59f0234, 0xe30f140f, 
+    0xe1c010b0, 0xe35600c3, 0x0a000010, 0xe59f0224, 0xe3a01044, 0xe1c010b0, 0xe3a01040, 0xe1c010b0, 
+    0xe3a01008, 0xe59f0210, 0xe1d020b0, 0xe0012002, 0xe1510002, 0x1afffffb, 0xe59f0200, 0xe1d020b0, 
+    0xe0012002, 0xe1510002, 0x1afffffb, 0xea00000f, 0xe3a01004, 0xe3811001, 0xe59f01e4, 0xe1d020b0, 
+    0xe1510002, 0x1afffffc, 0xe3a00902, 0xe2500001, 0xe3500000, 0x1afffffc, 0xe59f01c8, 0xe3a01000, 
+    0xe1c010b0, 0xe59f01c0, 0xe3a01d06, 0xe1c010b0, 0xe3a060ff, 0xe1c560b0, 0xe59f0138, 0xe5901000, 
+    0xe7c0101f, 0xe7c4121f, 0xe59f01a0, 0xe5801000, 0xe59f012c, 0xe3899001, 0xe1c090b0, 0xe3a06000, 
+    0xe1c560b0, 0xe59f0188, 0xe1d090b0, 0xe3190001, 0x1a000002, 0xe3899001, 0xe1c090b0, 0xea00ff37, 
+    0xe59f1170, 0xee091f11, 0xe59fa16c, 0xe59fb16c, 0xe51f02f8, 0xe51f12f8, 0xe1a02000, 0xe1500001, 
+    0x0a000024, 0xe51f0304, 0xe3500000, 0x1a000021, 0xe51f2304, 0xe3a01000, 0xe59f0144, 0xe1c010b0, 
+    0xe3e00000, 0xe59f713c, 0xe3a09008, 0xe4d13001, 0xe3510064, 0xca000002, 0xe3510061, 0xba000000, 
+    0xeafffff9, 0xe3a08000, 0xe7e043d3, 0xe7e05fd0, 0xe0346005, 0xe1a00080, 0x0a000000, 0xe0200007, 
+    0xe1a03083, 0xe2888001, 0xe1580009, 0xbafffff5, 0xe1510002, 0xbaffffec, 0xe5912000, 0xe58a0000, 
+    0xe58b2000, 0xe3e03000, 0xe1520003, 0x0a000001, 0xe1500002, 0x1a000009, 0xe3a03901, 0xe59f00c0, 
+    0xe1c030b0, 0xe59f5040, 0xe59f0028, 0xe5901000, 0xe3811040, 0xe3811020, 0xe5801000, 0xe51ff3e4, 
+    0xe3a03902, 0xe59f0098, 0xe1c030b0, 0xeafffffe, 0xf0002010, 0xf23c808c, 0xf0003000, 0xc0003000, 
+    0xc0002000, 0xc23d014c, 0xf23d0206, 0xf23d0228, 0xf203f01a, 0xf603f01a, 0xf203f018, 0xf603f018, 
+    0xf203f016, 0xf603f016, 0xf203f00a, 0xf603f00a, 0xf203f004, 0xf603f004, 0xf6034000, 0xf6034002, 
+    0xf23c8038, 0xf603f012, 0xf603f00e, 0xf603f010, 0xf603f00c, 0xf63c8308, 0xf603f02e, 0xca03f03a, 
+    0xd203f03a, 0xf23d000c, 0xf23d0000, 0xf23d0004, 0xf4003000, 0xf2034020, 0x00040021, 0x00000048, 
+    0x0000004c, 0xf23c801a, 0x04c11db7, 0xebffffff, 0xebffffff, 0xebffffff, 0xebffffff, 0xe3a01401, 
+    0xee110f10, 0xe1800001, 0xe3c00a02, 0xee010f10, 0xee110f30, 0xe3800040, 0xe3800501, 0xee010f30, 
+    0xe59f0084, 0xe3a010d1, 0xe121f001, 0xe1a0d000, 0xe3a010d2, 0xe121f001, 0xe2400080, 0xe1a0d000, 
+    0xe3a010d7, 0xe121f001, 0xe2400c02, 0xe1a0d000, 0xe3a010db, 0xe121f001, 0xe2400080, 0xe1a0d000, 
+    0xe3a010d3, 0xe121f001, 0xe2400080, 0xe1a0d000, 0xe3a010df, 0xe121f001, 0xe2400c02, 0xe1a0d000, 
+    0xe3a010d3, 0xe121f001, 0xe59f0024, 0xe59f1018, 0xe59f2024, 0xe4802004, 0xe1500001, 0xbafffffc, 
+    0xeb000007, 0xe59fc014, 0xe12fff1c, 0x00057800, 0x00057000, 0x0004d914, 0x0004ef14, 0xa5a5a5a5, 
+    0x000005ac, 0xe3a00701, 0xe3a02008, 0xee191f11, 0xe2011d3e, 0xe1811000, 0xe1811102, 0xe3811001, 
+    0xee091f11, 0xf57ff04f, 0xe12fff1e, 0xfa000000, 0xfa000035, 0xe890a00a, 0x44820c00, 0xf1aa4483, 
+    0x45da0701, 0xf000d101, 0xf2aff861, 0xe8ba0e09, 0xf013000f, 0xbf180f01, 0xf0431afb, 0x47180301, 
+    0x0002b488, 0x0002b4e8, 0xf04f440a, 0xf8100c00, 0xf0133b01, 0xbf080407, 0x4b01f810, 0xbf08111d, 
+    0x5b01f810, 0xd0051e64, 0x6b01f810, 0xf8011e64, 0xd1f96b01, 0x0f08f013, 0xf810bf1e, 0x1cad4b01, 
+    0xd1091b0c, 0xbf581e6d, 0xcb01f801, 0xe005d5fa, 0x6b01f814, 0x6b01f801, 0xd5f91e6d, 0xd3d64291, 
+    0x00004770, 0xbf243a10, 0xc178c878, 0x0752d8fa, 0xc830bf24, 0xbf44c130, 0x600c6804, 0x00004770, 
+    0x24002300, 0x26002500, 0xbf283a10, 0xd8fbc178, 0xbf280752, 0xbf48c130, 0x4770600b, 0xe89db51f, 
+    0xf0270003, 0xbd1ffb96, 0xbd10b510, 0xfddff027, 0xf7ff4611, 0xf000fff3, 0xf027f8bd, 0xb403fdfd, 
+    0xfff2f7ff, 0xf027bc03, 0x0000fe2b, 0x4ff8e92d, 0x0800f04f, 0x0005468a, 0x46464604, 0xd0184647, 
+    0xf02a4608, 0x4602f923, 0x2000460b, 0x4180f04f, 0xf968f029, 0x9124f8df, 0x20004602, 0x4649460b, 
+    0xff48f029, 0x464b2200, 0xfe88f029, 0x91004683, 0x2000e00c, 0xe8bd4601, 0x4b408ff8, 0x22000864, 
+    0x46394630, 0xfe7af029, 0x460f4606, 0xd8f42c01, 0x46394630, 0xf8b6f02a, 0x20014601, 0xf02a4088, 
+    0x4604f8de, 0x46284689, 0xf8f0f02a, 0x4622464b, 0xff20f029, 0x9b00e035, 0x4620465a, 0xf02a4629, 
+    0xd332f8f9, 0xe0232000, 0x462b4622, 0x46194610, 0xf92cf02a, 0x46042200, 0x0801f108, 0xf04f460d, 
+    0xf02a4380, 0xd811fa21, 0xfa002001, 0xf02af008, 0x4602f8b6, 0x4921460b, 0xf0292000, 0x4632fefb, 
+    0xf029463b, 0x4606fe3b, 0xe004460f, 0x0001f109, 0x46814550, 0xf04fd3d8, 0x462032ff, 0xf02a4629, 
+    0x45d0ff2c, 0x460d4604, 0x4630d3c5, 0xe7a24639, 0x4606b570, 0x461d4614, 0x0104e9dd, 0xf862f02a, 
+    0x4630b2c1, 0xff72f7ff, 0x462b4622, 0xfafaf02a, 0x4b0c4a0b, 0xfecef029, 0x22004b0b, 0xf8e6f02a, 
+    0xf04f4b0a, 0xf02a3233, 0x4b09fa15, 0xf02a2200, 0xf02af8dd, 0xb280f847, 0x0000bd70, 0x3ff00000, 
+    0x4ea4a8c1, 0x400a9340, 0x40340000, 0x40333333, 0x40240000, 0xbe4af002, 0xe28fc0bf, 0xe12fff1c, 
+    0x68124afb, 0xd00b4210, 0x68104afa, 0x6f00f5b0, 0x4bf9da06, 0xf843681b, 0x68101020, 0x60101c40, 
+    0xb5104770, 0xf7ff4604, 0x2000ffeb, 0xffb2f006, 0x46204601, 0x4010e8bd, 0xb570e7e2, 0x4605460c, 
+    0xf00848ee, 0x4621ff30, 0xf7ff4628, 0x4cebffea, 0x68214628, 0xffd4f7ff, 0x46286861, 0xffd0f7ff, 
+    0x462868a1, 0xffccf7ff, 0x462868e1, 0x4070e8bd, 0xb570e7c6, 0x4605460c, 0xf00848e1, 0x4621ffb6, 
+    0xf7ff4628, 0x48dfffce, 0xf2402200, 0xf02871ff, 0x4601f800, 0xf7ff4628, 0x4cd9ffb3, 0xf9b48861, 
+    0xeb000000, 0x46284101, 0xffaaf7ff, 0xf9b488e1, 0xeb000004, 0x46284101, 0x4070e8bd, 0xb570e7a0, 
+    0x48cb4605, 0x42056800, 0x188cd016, 0x4621b152, 0xf7ff4628, 0x2000ff95, 0xff5cf006, 0x46284601, 
+    0xff8ef7ff, 0x880849c8, 0xf3c01c40, 0x60080009, 0x680949c6, 0x4020f841, 0x48c5bd70, 0xb5102100, 
+    0xff9ff027, 0x212048c2, 0xf0273064, 0x48c1ff9a, 0x22462100, 0x0400f640, 0x80428001, 0x80c18081, 
+    0x48bd4621, 0xf0286800, 0x48b3ff95, 0x68004621, 0xff80f028, 0x00a148b9, 0xe8bd6800, 0xf0284010, 
+    0xb570bf89, 0xf240b281, 0xf3c01500, 0x2008040e, 0x52b8f04f, 0xffb3f7ff, 0xd8032cff, 0xb2e049ad, 
+    0xe0043108, 0x4f50f5b4, 0x49add205, 0xf851b2e0, 0x47800020, 0x48a64605, 0x30644629, 0xff61f027, 
+    0x462148a3, 0xff5df027, 0xf64f48a1, 0x307471ff, 0xff57f027, 0xf248489e, 0xe8bd0100, 0x30704070, 
+    0xbf4ff027, 0xf241489a, 0xb5101122, 0xf0273066, 0x4897ff48, 0x30642108, 0xff43f027, 0xbd102008, 
+    0xf00cb510, 0xb2c1fb9c, 0x30684891, 0xff39f027, 0x88014894, 0x3066488e, 0xff33f027, 0xbd102004, 
+    0xb510488b, 0xf0273068, 0x498eff29, 0x20018008, 0xfceff00c, 0xbd102004, 0xb510488b, 0x0000f990, 
+    0x4883b281, 0xf0273066, 0x2004ff1c, 0x4880bd10, 0x3066b510, 0xff12f027, 0x70084983, 0xbd102004, 
+    0xb5104882, 0x487a7801, 0xf0273066, 0x4880ff0a, 0x48777801, 0xf0273068, 0x487eff04, 0x48747801, 
+    0xf027306a, 0x2004fefe, 0x4871bd10, 0x3066b510, 0xfef4f027, 0xb2c04975, 0x28014c75, 0xd0037008, 
+    0x70202000, 0xbd102004, 0x30684869, 0xfee6f027, 0x4871e7f7, 0xb5104971, 0x78097800, 0xeb000180, 
+    0x496f1001, 0xeb007809, 0x496e0081, 0x44087809, 0x485fb281, 0xf0273066, 0x486bfed4, 0xfecef027, 
+    0x485b4601, 0xf0273068, 0x4867fecc, 0xf0271c80, 0x4601fec5, 0x306a4856, 0xfec3f027, 0x1d004862, 
+    0xfebcf027, 0x48524601, 0xf027306c, 0x485ffeba, 0x01017800, 0x306e484e, 0xfeb3f027, 0xbd102004, 
+    0xb570484b, 0xf0273066, 0x4604fea9, 0x306e4848, 0xfea4f027, 0xb2054953, 0x0003f004, 0xf3c47008, 
+    0x494f0081, 0xf3c47008, 0x494c1001, 0xf3c47008, 0x49491081, 0x483e7008, 0xf0273068, 0x494cfe8f, 
+    0x483b8008, 0xf027306a, 0x494afe89, 0x48388008, 0xf027306c, 0x4948fe83, 0x04208008, 0xf3c5d502, 
+    0xe0001006, 0x49412000, 0x20047008, 0xb510bd70, 0x22014c42, 0x46202102, 0xfe9bf027, 0x482c4601, 
+    0xf0273066, 0x2206fe6e, 0x21404620, 0xfe91f027, 0x48274601, 0xf0273068, 0x2205fe64, 0x21204620, 
+    0xfe87f027, 0x48224601, 0xf027306a, 0x2004fe5a, 0x481fbd10, 0x3066b510, 0xfe50f027, 0x22014c2f, 
+    0x46032102, 0xf0274620, 0x4819fe66, 0xf0273068, 0x2206fe45, 0x21404603, 0xf0274620, 0x4814fe5c, 
+    0xf027306a, 0x2205fe3b, 0x21204603, 0xf0274620, 0x2004fe52, 0x480ebd10, 0x3012b510, 0xfe2ef027, 
+    0x0101f000, 0x3066480a, 0xfe2bf027, 0xbd102004, 0x00057ffc, 0x00057ff0, 0x000401e4, 0x000413e8, 
+    0x00040538, 0xf2030430, 0x00057ff4, 0x00057ff8, 0xf23c800a, 0x00040010, 0x000401e0, 0x000401dc, 
+    0x00040158, 0x00040270, 0x0004055c, 0x000402ac, 0x000402ad, 0x000402f5, 0x000402ce, 0x000402cd, 
+    0x00040278, 0x00040277, 0xf2035118, 0x00040279, 0x0004027c, 0x0004027e, 0x00040280, 0xf38e0040, 
+    0xb51048fe, 0x48fe7801, 0xfdebf027, 0xe7be2004, 0xb51048fb, 0xfde2f027, 0x700849f8, 0xe7b62004, 
+    0x4cf8b510, 0x22042300, 0x46202110, 0xfdf3f027, 0x46202300, 0x21202205, 0xfdedf027, 0x230048f0, 
+    0x461a2101, 0xf0273854, 0x2004fde6, 0xb570e79f, 0x230f4cec, 0x46192200, 0xf0274620, 0xf240fddc, 
+    0x1ca07507, 0xf0274629, 0x1d20fdbc, 0xf0274629, 0x2301fdb8, 0x22044620, 0xf0272110, 0x2301fdcc, 
+    0x22054620, 0xf0272120, 0x48ddfdc6, 0x22002301, 0x38544619, 0xfdbff027, 0xbd702004, 0xb51048da, 
+    0x48d77801, 0xfd9df027, 0x780148d8, 0x1c8048d4, 0xfd97f027, 0xe76a2004, 0xb51048d1, 0xfd8ef027, 
+    0x700849d1, 0x1c8048ce, 0xfd88f027, 0x700849cf, 0xe75c2004, 0xb51048ce, 0x28037800, 0x2100d011, 
+    0xf02748c7, 0x48cbfd7e, 0x48c57801, 0xf0271c80, 0x48c9fd78, 0x48c27801, 0xf0271d00, 0x2004fd72, 
+    0x2101e745, 0x48bee7ec, 0xf027b510, 0x49c1fd67, 0x20047008, 0x48c1e73b, 0xf990b510, 0x28040000, 
+    0x2805d009, 0x2803d007, 0x2802d005, 0x2801d024, 0x2008d022, 0x4cb3e72b, 0x22002301, 0x3c824619, 
+    0xf0274620, 0x2301fd68, 0x22034620, 0xf0272108, 0x2301fd62, 0x22024620, 0xf0272104, 0x1ca0fd5c, 
+    0xfd3cf027, 0xf0271d20, 0x2300fd39, 0x21014620, 0xf027461a, 0xe03bfd50, 0x23014ca9, 0x03d9220f, 
+    0xf0274620, 0x2301fd48, 0x220e4620, 0xf0270399, 0x2301fd42, 0x21024620, 0xf027461a, 0x2300fd3c, 
+    0x22014620, 0xf0272102, 0x2301fd36, 0x22004620, 0xf0274619, 0x4c9afd30, 0x46203c0a, 0xfd0ef027, 
+    0xf0274620, 0x1ca4fd0b, 0xf0274620, 0x4620fd07, 0xfd04f027, 0x46201ca4, 0xfd00f027, 0xf0274620, 
+    0x1ca4fcfd, 0xf0274620, 0x4620fcf9, 0xfcf6f027, 0xe6cc2004, 0x47f0e92d, 0xf0274881, 0x4d80fcef, 
+    0x4886b2c4, 0x1cae1cad, 0x0804f105, 0x0000f990, 0x0906f105, 0xd0082804, 0xd0062805, 0xd0042803, 
+    0xd04e2802, 0xd04c2801, 0x4f76e080, 0x22032301, 0x21083f82, 0xf0274638, 0x2301fcee, 0x22024638, 
+    0xf0272104, 0xb114fce8, 0xd01b2c01, 0x486de06e, 0xf027387e, 0x4601fcc3, 0xf0274628, 0x4869fcc2, 
+    0xf0273880, 0x4601fcbb, 0xf0274630, 0x4865fcba, 0xf0273876, 0x4601fcb3, 0xf0274640, 0x4861fcb2, 
+    0xe0193878, 0x387a485f, 0xfca8f027, 0x46284601, 0xfca7f027, 0x387c485b, 0xfca0f027, 0x46304601, 
+    0xfc9ff027, 0x38724857, 0xfc98f027, 0x46404601, 0xfc97f027, 0x38744853, 0xfc90f027, 0x46484601, 
+    0xb114e032, 0xd0122c01, 0x4c55e030, 0x46201fa4, 0xfc84f027, 0x46304601, 0xfc83f027, 0xf0274620, 
+    0x4601fc7d, 0xf0274628, 0x1ca4fc7c, 0x4c4ce010, 0x46203c08, 0xfc72f027, 0x46304601, 0xfc71f027, 
+    0xf0274620, 0x4601fc6b, 0xf0274628, 0x1ea4fc6a, 0xf0274620, 0x4601fc63, 0xf0274648, 0x4620fc62, 
+    0xfc5cf027, 0x46404601, 0xfc5bf027, 0xe8bd2004, 0x483387f0, 0x1c80b510, 0xfc50f027, 0x70204c39, 
+    0xf027482f, 0x7821fc4b, 0xf00cb2c0, 0x2004f852, 0xb570e61d, 0x0500f244, 0x220e4833, 0xf0274629, 
+    0x4c27fc68, 0x4830b178, 0x4629220e, 0xf0273844, 0xb140fc60, 0x2200482c, 0x38502101, 0xfc59f027, 
+    0x2101b108, 0x2100e000, 0xf0274620, 0x4825fc2a, 0x481b7801, 0xf0271c80, 0x2004fc24, 0x4923bd70, 
+    0xb5102000, 0x46022301, 0x46197008, 0xf0274820, 0x481ffc32, 0xf0273044, 0x4601fc11, 0xf0274810, 
+    0x481bfc10, 0xf0273046, 0x4601fc09, 0x1c80480c, 0xfc07f027, 0x30484816, 0xfc00f027, 0x48084601, 
+    0xf0271d00, 0x4812fbfe, 0xf027304a, 0x4601fbf7, 0x1d804803, 0xfbf5f027, 0xe5c82004, 0x000402c9, 
+    0xf23c8070, 0xf203526c, 0x000402ca, 0x000402cb, 0x0004057b, 0x000402d0, 0x0004058a, 0x000401fc, 
+    0xf38f215e, 0x00040321, 0xf38f2050, 0x00040299, 0xf2030406, 0xb51048f7, 0x48f77801, 0xfbd1f027, 
+    0x780148f6, 0x1c8048f4, 0xfbcbf027, 0xe59e2004, 0xb51048f1, 0xfbc2f027, 0x700849ee, 0x1c8048ee, 
+    0xfbbcf027, 0x700849ed, 0xe5902004, 0x4cecb510, 0x0000f994, 0x48e8b281, 0xfbb3f027, 0x28027820, 
+    0x48e5d108, 0xf0273062, 0x4601fba9, 0x1c8048e2, 0xfba7f027, 0xe57a2004, 0x41f0e92d, 0xf02748de, 
+    0x49dffb9d, 0x4ddcb240, 0xf8df4fde, 0x356a836c, 0x37104edc, 0x70082802, 0x0862f108, 0x2000d03e, 
+    0x22037008, 0x21084603, 0xf0274638, 0x2300fb8d, 0x22014628, 0xf0272102, 0x2301fb9e, 0x220a4628, 
+    0xf0270299, 0x2301fb98, 0x220b4628, 0xf02702d9, 0x2301fb92, 0x21024638, 0xf027461a, 0x2301fb75, 
+    0x21024630, 0xf027461a, 0x2300fb6f, 0x22014638, 0xf0272102, 0x2300fb69, 0x22014630, 0xf0272102, 
+    0x2300fb63, 0x21014628, 0xf027461a, 0x2100fb74, 0xf0274640, 0x2004fb56, 0x81f0e8bd, 0x1c8048b6, 
+    0xfb4cf027, 0x2c1ab2c4, 0x2c2ad00b, 0x2c3ad009, 0x2c0bd007, 0x2c0cd005, 0x2c0dd003, 0x2c0ed001, 
+    0x4621d1e9, 0xf0274640, 0x2208fb3c, 0x23014628, 0xf0270151, 0x2301fb50, 0x22094628, 0xf0270259, 
+    0x2301fb4a, 0x22004628, 0xf0274619, 0x48a5fb44, 0x303049a5, 0xfb1ff027, 0x46302301, 0x21042202, 
+    0xfb22f027, 0x46382301, 0x21042202, 0xfb1cf027, 0x2200489e, 0xf990b261, 0xf0180000, 0x499cfc9c, 
+    0x70082001, 0x489be7b7, 0x7801b510, 0xf0274892, 0x4899fb08, 0x48907801, 0xf0271c80, 0x4897fb02, 
+    0x488d7801, 0xf0271d00, 0x2004fafc, 0x488ae4cf, 0xf027b510, 0x498ffaf3, 0x48877008, 0xf0271c80, 
+    0x498dfaed, 0x48847008, 0xf0271d00, 0x498bfae7, 0x20047008, 0x488ae4bb, 0x7842b570, 0x1000f990, 
+    0xea4178c3, 0xf9902102, 0xb2892002, 0x2203ea42, 0xb2957943, 0x2004f990, 0x0006f990, 0x2203ea42, 
+    0x4875b286, 0x1c80b294, 0xfacbf027, 0x46294872, 0xf0271d00, 0x4870fac6, 0x1d804621, 0xfac1f027, 
+    0x4631486d, 0xf0273008, 0x2004fabc, 0xb570bd70, 0x4e694874, 0x1cb64c72, 0x46307805, 0xfaaef027, 
+    0x46307020, 0xfaaaf027, 0x70601200, 0x46301cb6, 0xfaa4f027, 0x463070a0, 0xfaa0f027, 0x70e01200, 
+    0x46301cb6, 0xfa9af027, 0x46307120, 0xfa96f027, 0x71601200, 0xf0271cb0, 0x4629fa91, 0x462071a0, 
+    0xfa13f026, 0x2008b108, 0x2004bd70, 0xb510bd70, 0x48514c5b, 0x7a611c80, 0xfa83f027, 0x7a21484e, 
+    0xf0271d00, 0x2004fa7e, 0x4856e451, 0x4c54b570, 0x48497805, 0xf0271c80, 0x7260fa71, 0x1d004846, 
+    0xfa6cf027, 0x7221b2c1, 0x462a7a60, 0xfb28f024, 0xbd702004, 0xb510484c, 0xfa60f027, 0x483e4601, 
+    0xfa5ff027, 0x1c804848, 0xfa58f027, 0x483a4601, 0xf0271c80, 0x4844fa56, 0xf0271d00, 0x4601fa4f, 
+    0x1d004835, 0xfa4df027, 0x1d80483f, 0xfa46f027, 0x48314601, 0xf0271d80, 0x2004fa44, 0xe92de417, 
+    0x482d41ff, 0xfa3af027, 0x70084938, 0xf0084838, 0x4e37f96a, 0x4f372400, 0xf8dfad02, 0x200080dc, 
+    0x463a4936, 0xe9cd4643, 0xf8560100, 0xf7ff0024, 0xf825f9cf, 0x1c640014, 0x2c04b264, 0x481edbef, 
+    0x1008f8bd, 0xf0271c80, 0x481bfa1c, 0x100af8bd, 0xf0271d00, 0x4818fa16, 0x100cf8bd, 0xf0271d80, 
+    0x4815fa10, 0x100ef8bd, 0xf0273008, 0x2004fa0a, 0xe6b1b004, 0xb510481c, 0xf0271e80, 0x4601f9ff, 
+    0xf027480d, 0x2004f9fe, 0x480be411, 0xf027b510, 0x491bf9f5, 0x48086008, 0xf0271c80, 0x4919f9ef, 
+    0x48056008, 0xf0271d00, 0x4917f9e9, 0x20047008, 0x0000e405, 0x000402f7, 0xf23c8070, 0x000402f8, 
+    0x0004052a, 0xf0008160, 0x00501bd0, 0x00040242, 0x000402f9, 0x000402cc, 0x0004057b, 0x00040575, 
+    0x0004d108, 0x00040320, 0xc23d0144, 0x00040299, 0x000413e8, 0xb573eab3, 0x4030ab15, 0x40300000, 
+    0x000402b4, 0x000402b8, 0x000402b3, 0xb51048fe, 0xb2818800, 0xf02748fd, 0x48fdf9b4, 0xb2818800, 
+    0x1c8048fa, 0xf9adf027, 0x780148fa, 0x1d0048f7, 0xf9a7f027, 0xe40e2004, 0xb51048f4, 0xf99ef027, 
+    0x600849f5, 0x1c8048f1, 0xf998f027, 0x600849f3, 0x1d0048ee, 0xf992f027, 0x600849f1, 0xe4082004, 
+    0xb51048ed, 0xb2818800, 0xf02748e8, 0x48ebf98a, 0xb2818800, 0x1c8048e5, 0xf983f027, 0x880048e8, 
+    0x48e2b281, 0xf0271d00, 0x2004f97c, 0x48e5e408, 0x7801b510, 0xf02748dd, 0x2004f974, 0x48dbe40a, 
+    0xf027b510, 0x49dff96b, 0x20047008, 0xe92de412, 0x200841f0, 0x0144f248, 0x52b8f04f, 0xf99ff7ff, 
+    0x26004cd9, 0x78204fd1, 0xd1092801, 0x46382200, 0xf0272103, 0xb918f97e, 0x700648d4, 0xfcfff00b, 
+    0x46382200, 0xf0272103, 0x2202f974, 0x211c7020, 0xf0274638, 0x49cef96e, 0x70082205, 0x46382120, 
+    0xf967f027, 0x8304f8df, 0x4cca2801, 0x0802f108, 0x2208d10d, 0x7100f64f, 0xf0274640, 0xf029f95a, 
+    0xf06ff985, 0xf0290207, 0xe9c4fff8, 0x22060100, 0x21404638, 0xf94df027, 0x28014dbf, 0x2200d10c, 
+    0x21ff4640, 0xf945f027, 0xf970f029, 0x0204f06f, 0xffe3f029, 0x0100e9c5, 0x46382207, 0xf0272180, 
+    0x2801f938, 0x49b6d103, 0xe9c448b4, 0x22080100, 0x01514638, 0xf92df027, 0xd1032801, 0x48b149b2, 
+    0x0100e9c5, 0xf2402209, 0x46382100, 0xf921f027, 0xd1012801, 0x700648ad, 0xf240220a, 0x46384100, 
+    0xf917f027, 0xd1012801, 0x700648a9, 0xe5932004, 0x41f0e92d, 0xf2482008, 0xf04f0145, 0xf7ff52b8, 
+    0x48a2f91e, 0x7400f64f, 0x22084d90, 0x78034621, 0xf0274628, 0x499ef8f0, 0x46282200, 0x21ff780b, 
+    0xf8e9f027, 0x22084993, 0x0100e9d1, 0xff95f029, 0xf8d8f029, 0x4621b283, 0x22081cad, 0xf0274628, 
+    0x488df8da, 0xe9d02205, 0xf0290100, 0xf029ff86, 0xb283f8c9, 0x22004628, 0xf02721ff, 0x4882f8cc, 
+    0x22001cae, 0x78032103, 0xf0274630, 0x487ff8c4, 0x210c2202, 0x46307803, 0xf8bdf027, 0x22044d7c, 
+    0x46302170, 0xf027782b, 0x2300f8b6, 0x7180f64f, 0x46302207, 0xf8aff027, 0x1cb5782a, 0xb1521cae, 
+    0x2a014c7c, 0x2a02d049, 0x2100d052, 0xf0274628, 0x2100f888, 0x4f78e059, 0xe9d72203, 0xf0290100, 
+    0xf029ff4c, 0x28fff85f, 0x20ffdb00, 0x4628b283, 0x21ff2200, 0xf88ff027, 0xe9d72203, 0xf0290102, 
+    0xf029ff3c, 0x28fff84f, 0x20ffdb00, 0xb2834621, 0x22084628, 0xf87ff027, 0xe9d72203, 0xf0290104, 
+    0xf029ff2c, 0x28fff83f, 0x20ffdb00, 0x4630b283, 0x21ff2200, 0xf86ff027, 0xe9d72203, 0xf0290106, 
+    0xf029ff1c, 0x28fff82f, 0x20ffdb00, 0xb2834621, 0x22084630, 0xf85ff027, 0xe9d4e01a, 0xf0290100, 
+    0xb281f851, 0xf0274628, 0xe9d4f83c, 0xe0090102, 0x0104e9d4, 0xf846f029, 0x4628b281, 0xf831f027, 
+    0x0106e9d4, 0xf83ef029, 0x4630b281, 0xf829f027, 0xe4d12004, 0x5ff0e92d, 0x80d0f8df, 0x46402100, 
+    0xf81ff027, 0x0902f108, 0x46482100, 0xf819f027, 0x0a04f108, 0x46502100, 0xf813f027, 0x0b06f108, 
+    0x46582100, 0xf80df027, 0x4f3d4c3c, 0x88204d3d, 0x417ff5a0, 0xd01339ff, 0x28017838, 0x2204d110, 
+    0x21104628, 0xf825f027, 0x46062203, 0x46282108, 0xf81ff027, 0xd1014286, 0xe0002000, 0x80202001, 
+    0x0000f997, 0x4640b281, 0xffebf026, 0x46488821, 0xffe7f026, 0x46282204, 0xf0272110, 0x4601f80a, 
+    0xf0264650, 0x2203ffde, 0x21084628, 0xf801f027, 0x46584601, 0xffd5f026, 0xe8bd2004, 0xe92d9ff0, 
+    0x480a5ff0, 0xffcaf026, 0x46044d1c, 0x70fff64f, 0x42818829, 0x2008d138, 0x1137f248, 0x52b8f04f, 
+    0xfffdf7fe, 0xe7e82008, 0x000402b4, 0xf23c8070, 0x000402b8, 0x000402b3, 0x000402c0, 0x000402c4, 
+    0x000402bc, 0x000402af, 0x00040318, 0x00040304, 0x00040319, 0x00040308, 0x00040310, 0xb71758e2, 
+    0x3fae00d1, 0x538ef34d, 0x3ff42474, 0x00040305, 0x00040306, 0x0004d118, 0x0004d138, 0x00040300, 
+    0x0004023b, 0xf38f2056, 0xf04f4efe, 0x80280a02, 0x4ffe49fd, 0x0000f996, 0x0b02f101, 0x83f0f8df, 
+    0x93f0f8df, 0xd0264284, 0xd0142c01, 0xa000f8a5, 0x7034200a, 0xf831f006, 0x48f72301, 0x029c220a, 
+    0xf0264621, 0x48f4ff71, 0x220a2301, 0x1d004621, 0xff6af026, 0x4608e024, 0xff60f026, 0x46587038, 
+    0xff5cf026, 0x0000f888, 0x1d0048e7, 0xff56f026, 0x0000f889, 0x2c01e7dc, 0x4608d110, 0xff4ef026, 
+    0x46587038, 0xff4af026, 0x0000f888, 0x1d0048de, 0xff44f026, 0x0000f889, 0xfa14f00c, 0xa000f8a5, 
+    0xe76a2004, 0xb57048d8, 0xf0261e80, 0x4604ff37, 0xf02648d5, 0xea40ff33, 0x48d34404, 0xf0261d00, 
+    0x4605ff2d, 0x1c8048d0, 0xff28f026, 0x4620b148, 0xff24f026, 0x48cc4601, 0xf0261d80, 0x2004ff22, 
+    0x4629bd70, 0xe7f84620, 0xb51048cd, 0x68004ccb, 0x48cc6020, 0x48cc6060, 0x48cc60a0, 0x48cc60e0, 
+    0x48cc6120, 0x48cc6160, 0x48cc61a0, 0x48cc61e0, 0x48cc6220, 0x62606800, 0x62a048cb, 0x62e02000, 
+    0x63606320, 0xf02263a0, 0x63e0fd55, 0xb2814620, 0x1d0048b5, 0xfef5f026, 0x0c014620, 0x1c8048b2, 
+    0xfeeff026, 0x211048b0, 0xf0261e80, 0x2004feea, 0x48b2e46a, 0xb281b510, 0x1d0048ab, 0xfee1f026, 
+    0x0c0148ae, 0x1c8048a8, 0xfedbf026, 0xe45b2004, 0xb51048a5, 0xf0261d00, 0x4604fed1, 0x1c8048a2, 
+    0xfeccf026, 0x4400eb04, 0xb2818820, 0xf026489e, 0x6820fec8, 0x489c0c01, 0xf0261e80, 0x2004fec2, 
+    0x4899e442, 0x1d00b570, 0xfeb8f026, 0x48964604, 0xf0261c80, 0xeb04feb3, 0x48934400, 0xfeaef026, 
+    0x48914605, 0xf0261e80, 0xeb05fea9, 0x60204000, 0xbd702004, 0x41f0e92d, 0x25004e98, 0x24004f9b, 
+    0x0044eb07, 0xfe9af026, 0x01c5eb04, 0xb2241c64, 0xf8262c08, 0xdbf30011, 0xb22d1c6d, 0xdbee2d40, 
+    0xe5a42004, 0xb5104880, 0xf0261d00, 0x4c88fe87, 0x487d6020, 0xf0261c80, 0x6821fe81, 0x4000ea41, 
+    0x20046020, 0xb510e43a, 0x88204c81, 0x4876b281, 0xf0261d00, 0x6820fe76, 0x48730c01, 0xf0261c80, 
+    0x2004fe70, 0x4870e42a, 0x1e80b538, 0xfe66f026, 0x486db245, 0xfe62f026, 0x486bb244, 0xf0261c80, 
+    0xb242fe5d, 0x0000f04f, 0xd0062d01, 0x46214b73, 0x20019000, 0xfb6af004, 0x4975e00b, 0xeb014a6f, 
+    0xf9311144, 0xf8423010, 0x1c403020, 0x2810b240, 0x2004dbf7, 0x4964bd38, 0xb5102000, 0xf6406008, 
+    0x485f0100, 0xf0276800, 0x4857fe35, 0x1e802100, 0xfe37f026, 0xe4372004, 0x48662208, 0x0151b570, 
+    0xfe57f026, 0x22054c50, 0x46032120, 0x46203c58, 0xfe41f026, 0x22024d60, 0x46282104, 0xfe49f026, 
+    0x4603220d, 0x0100f242, 0xf0264620, 0x2202fe34, 0x21044628, 0xfe3df026, 0x48434603, 0x21012200, 
+    0xf0263850, 0x4d56fe28, 0x48542202, 0x1000f995, 0x211c5c43, 0xf0264620, 0x4852fe1e, 0xf2402209, 
+    0x78036100, 0xf0264620, 0x484afe16, 0x21802207, 0xf02630a0, 0x2201fe1e, 0x21024603, 0xf0264620, 
+    0x7828fe0a, 0x4070e8bd, 0xbabff00b, 0xf026b510, 0xb281fb97, 0x482c4604, 0xf0261c80, 0x482afde2, 
+    0x1d000c21, 0xfdddf026, 0xe4342004, 0xf2414826, 0xb5102134, 0xf0261d80, 0x4c28fdd4, 0xb2814620, 
+    0x1d004821, 0xfdcdf026, 0x0c014620, 0x1c80481e, 0xfdc7f026, 0xfb84f026, 0xf0266020, 0x6060fba1, 
+    0xfb8ef026, 0xf02660a0, 0x60e0fb93, 0xfb80f026, 0xf0266120, 0x6160fb9d, 0x48132106, 0xf0261e80, 
+    0x2004fdb0, 0xe92de407, 0x480f5ff0, 0x1e802700, 0xfda4f026, 0x480c4604, 0xfda0f026, 0x8088f8df, 
+    0x0507f000, 0x1602f3c0, 0xb080f8df, 0x3300f3c4, 0x2903f3c4, 0x0000f998, 0x041ff004, 0xd07d2801, 
+    0xe0352802, 0x0004023b, 0xf23c8072, 0x000402fc, 0x000402fd, 0x000402fe, 0xf0001030, 0x000418b8, 
+    0x000401e4, 0x00057ff8, 0x00057ff0, 0x00057ff4, 0x00057ffc, 0x00057c00, 0x00057c40, 0x00057800, 
+    0x00057c80, 0x000401e0, 0x00041698, 0xf203612e, 0x00041258, 0xf38f2002, 0xf3074084, 0x0002b6ea, 
+    0x00040242, 0x0004057b, 0x00040248, 0xf20308e2, 0x2803d00b, 0x0205f04f, 0x0120f04f, 0xf8dfd002, 
+    0xe045a428, 0x465846da, 0xf8dfe006, 0x2205a41c, 0xf10a2120, 0xe03b0a40, 0xfd5df026, 0x464b2200, 
+    0x4650210f, 0xfd57f026, 0xf6432300, 0x461a71ff, 0xf02648fe, 0xf8dffd39, 0x2c1aa3f8, 0xf1c5d22a, 
+    0xf64f0008, 0xeb0071ff, 0xea010040, 0xf04f2000, 0xeb0131ff, 0x48f70150, 0xfd1df026, 0x211848f3, 
+    0xf0261f00, 0x48f4fd18, 0x5146ea44, 0x48f14301, 0xf0263808, 0xf89afd10, 0xe0001000, 0xf44fe002, 
+    0xe0421080, 0xa3a0f8df, 0x21202205, 0x0a20f10a, 0xe7c14650, 0xf04fd102, 0xe023000b, 0xd01c2c1b, 
+    0xd01c2c1c, 0xd01c2c1d, 0xf998200b, 0x05721000, 0x3181ea42, 0x4187ea41, 0x1140ea41, 0x48dd4301, 
+    0xf0263808, 0x48d9fce8, 0x1f002119, 0xfce3f026, 0x780048da, 0xd0072804, 0x200fe007, 0x2010e7e5, 
+    0x2011e7e3, 0xe7e02701, 0x2e03006d, 0xf240d902, 0xe0044000, 0xeb062001, 0x40880146, 0x2100b280, 
+    0xeb054345, 0xebc01085, 0xf00500c0, 0xf1b9fcbb, 0xd01e0f00, 0x0000f998, 0xd0132801, 0xd00b2802, 
+    0xf04f2803, 0xf04f0301, 0xf04f0204, 0xd0010110, 0xe00c48bd, 0xe00a4658, 0x230148bb, 0x21102204, 
+    0xe0043040, 0x230148b8, 0x21102204, 0xf0263020, 0x2c1afcc2, 0x48b7d206, 0x221c2301, 0x38080719, 
+    0xfca2f026, 0x1000f89a, 0x1080f44f, 0xfc8af005, 0xe4c22004, 0xb51048b2, 0x48b27801, 0xfc91f026, 
+    0xe5a52004, 0xb51048af, 0xfc88f026, 0x700849ac, 0xe59d2004, 0x47fce92d, 0x4cac48ab, 0xf9901ca5, 
+    0xf1041000, 0xf1040904, 0x29030a06, 0x2905d018, 0x2904d016, 0xf248d014, 0x46200600, 0xf0264631, 
+    0x4631fc70, 0xf0264628, 0x4631fc6c, 0xf0264648, 0x4631fc68, 0xf0264650, 0x2000fc64, 0x87fce8bd, 
+    0xf007489b, 0x499bfb90, 0x4e992000, 0xf8df4f9a, 0xe9cd826c, 0x68300100, 0x4643463a, 0xfbf8f7fe, 
+    0x4000f500, 0x4620b281, 0xfc4bf026, 0x20004991, 0x4643463a, 0x0100e9cd, 0xf7fe6870, 0xf500fbe9, 
+    0xb2814000, 0xf0264628, 0x498afc3c, 0x463a2000, 0xe9cd4643, 0x68b00100, 0xfbdaf7fe, 0x4000f500, 
+    0x4648b281, 0xfc2df026, 0x20004982, 0x4643463a, 0x0100e9cd, 0xf7fe68f0, 0xf500fbcb, 0xb2814000, 
+    0x487fe7b8, 0xf990b510, 0xb2810000, 0xf0264875, 0x487cfc18, 0x48737801, 0xf0261c80, 0x2004fc12, 
+    0x4870e526, 0xf026b510, 0x4975fc09, 0x486d7008, 0xf0261c80, 0x4973fc03, 0x20077008, 0xfd21f005, 
+    0xe5152004, 0xb5104870, 0x48667801, 0xfbf9f026, 0x7801486e, 0x1c804863, 0xfbf3f026, 0xe5072004, 
+    0xb5104860, 0xfbeaf026, 0x70084967, 0x1c80485d, 0xfbe4f026, 0x70084965, 0xf0052007, 0x2004fd02, 
+    0xe92de4f6, 0xf8df47f0, 0xf2419164, 0x220c0800, 0xf1a94604, 0x46410908, 0xf0264648, 0x4e5cfbfa, 
+    0x4f5c2801, 0xd10c4d5c, 0x683802c1, 0xfbd2f027, 0x46412300, 0x4648220c, 0xfbddf026, 0x70302000, 
+    0xf9966028, 0x28040000, 0x6838da7c, 0xf8206829, 0x68284011, 0x60281c40, 0x38264842, 0xfbaef026, 
+    0x682a6839, 0x8134f8df, 0xf1084c4c, 0xf821080e, 0x68280012, 0x60281c40, 0xf0264620, 0x6839fb9f, 
+    0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4c42d9f2, 0xf1043420, 0x46200802, 0xfb8ef026, 
+    0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0x80e8f8df, 0xf1084c39, 0x4620080e, 
+    0xfb7cf026, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0x80c8f8df, 0xf1084c31, 
+    0x46200814, 0xfb6af026, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0x341c4c29, 
+    0x0802f104, 0xf0264620, 0x6839fb59, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0xf8dfd9f2, 
+    0x4c218088, 0x0808f108, 0xf0264620, 0x6839fb47, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 
+    0xe033d9f2, 0x0000e159, 0xf2030882, 0xf1000408, 0x00040243, 0xf1000488, 0x00080400, 0x00040242, 
+    0x00040298, 0xf23c8070, 0x000401fc, 0xf20351ac, 0x000413e8, 0x40300000, 0xb573eab3, 0x4030ab15, 
+    0x000401fa, 0x000401fb, 0x000402a4, 0x000402a5, 0x000402ec, 0x00040590, 0x000402e0, 0xf2034200, 
+    0xf2039004, 0xf38fffc0, 0xf38f2000, 0xf8df4cfe, 0x341483f8, 0x081ef108, 0xf0264620, 0x6839faff, 
+    0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0xf8dfd9f2, 0x4cf583d8, 0x08d2f108, 0xf0264620, 
+    0x6839faed, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4cecd9f2, 0x83b0f8df, 0xf1a83460, 
+    0x46200802, 0xfadaf026, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0x300a48e2, 
+    0xfaccf026, 0x682a6839, 0x0012f821, 0x1c406828, 0x48dd6028, 0xf026300c, 0x6839fac1, 0xf8df682a, 
+    0xf1088368, 0xf8210850, 0x68280012, 0x60281c40, 0xeb082400, 0xf0260044, 0x6839fab1, 0x682a1c64, 
+    0x0012f821, 0x1c406828, 0x2c076028, 0xf8dfd9f1, 0x24008338, 0x0820f108, 0x0044eb08, 0xfa9ef026, 
+    0x1c646839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f12c1f, 0xf02648c6, 0x6839fa91, 0xf821682a, 
+    0x68280012, 0x60281c40, 0x1c8048c1, 0xfa86f026, 0x682a6839, 0x0012f821, 0x1c406828, 0x48bc6028, 
+    0xf0263020, 0x6839fa7b, 0xf821682a, 0x68280012, 0x60281c40, 0x302648b6, 0xfa70f026, 0x682a6839, 
+    0x0012f821, 0x1c406828, 0x48b16028, 0xf0263040, 0x6839fa65, 0xf821682a, 0x68280012, 0x60281c40, 
+    0x304248ab, 0xfa5af026, 0x682a6839, 0xf8214ca8, 0x68280012, 0x60281c40, 0xf1043478, 0x46200806, 
+    0xfa4cf026, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0xf1044c9e, 0x46200804, 
+    0xfa3cf026, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0x34324c96, 0x0804f104, 
+    0xf0264620, 0x6839fa2b, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4c8ed9f2, 0xf1043460, 
+    0x46200804, 0xfa1af026, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0x347a4c85, 
+    0x0804f104, 0xf0264620, 0x6839fa09, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4c7dd9f2, 
+    0xf10434ac, 0x46200804, 0xf9f8f026, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 
+    0xf0264875, 0x6839f9eb, 0xf821682a, 0x68280012, 0x60281c40, 0x1c407830, 0xe8bd7030, 0x4a6f87f0, 
+    0x71fff640, 0x1c406810, 0xf3f1fb90, 0x0013fb01, 0x28006010, 0x496ad105, 0x1c407808, 0x000ff000, 
+    0x47708008, 0x5ff0e92d, 0x46304e66, 0xf9c6f026, 0x88914a65, 0xd0484281, 0xf64fd205, 0xeba373ff, 
+    0x44010101, 0xeba0e001, 0x4f610101, 0xc16cf8df, 0x0101f101, 0xb28d8090, 0x6839485c, 0x2000f8dc, 
+    0x0000ea45, 0x0022f841, 0xffc9f7ff, 0xa154f8df, 0x46b12400, 0xf1aa46e0, 0xf10a0a08, 0xe0220b02, 
+    0xf0264650, 0x4606f99b, 0xf0264658, 0x683af997, 0x4100ea46, 0x0000f8d8, 0x1020f842, 0xffaff7ff, 
+    0x1f004848, 0xf98af026, 0x46484606, 0xf986f026, 0xea46683a, 0xf8d84100, 0xf8420000, 0xf7ff1020, 
+    0x1c64ff9e, 0x42acb2a4, 0xe4e2d3da, 0x2005b570, 0xf920f005, 0x4d394c3e, 0x682a6821, 0x0022f841, 
+    0xff8df7ff, 0x6821483b, 0x6800682a, 0x0022f841, 0xff85f7ff, 0xf0264838, 0x4606f961, 0x38144836, 
+    0xf95cf026, 0xea466821, 0x682a4000, 0x0022f841, 0xff75f7ff, 0xf0264825, 0x4e29f951, 0x508df100, 
+    0x8831682a, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x481eff66, 0xf0261c80, 0x4928f941, 0x4408682a, 
+    0xea408831, 0x68214001, 0x0022f841, 0xff57f7ff, 0x1d004816, 0xf932f026, 0xf1008831, 0x682a508e, 
+    0x4001ea40, 0xf8416821, 0xf7ff0022, 0x480fff48, 0xf0261d80, 0x491af923, 0x4408682a, 0xea408831, 
+    0x68214001, 0x0022f841, 0xff39f7ff, 0x30104807, 0xf914f026, 0xf1008831, 0x682a5095, 0x4001ea40, 
+    0xf8416821, 0xe01d0022, 0xf38f2000, 0xf38f2200, 0xf38e0000, 0xf38f0000, 0xf2039000, 0x000402d4, 
+    0x000402e4, 0xf23c826c, 0x00040000, 0xeeee0000, 0x0004058c, 0x000402e8, 0xf38fffd4, 0x11b00000, 
+    0x11d00000, 0xff0bf7ff, 0xf02648f9, 0x49f9f8e7, 0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 
+    0xfefdf7ff, 0x1c8048f2, 0xf8d8f026, 0xf1008831, 0x682a5096, 0x4001ea40, 0xf8416821, 0xf7ff0022, 
+    0x48ebfeee, 0xf0261d00, 0x49ebf8c9, 0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 0xfedff7ff, 
+    0x301648e3, 0xf8baf026, 0xf1008831, 0x682a509d, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48dcfed0, 
+    0xf0263018, 0x49ddf8ab, 0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 0xfec1f7ff, 0x301a48d4, 
+    0xf89cf026, 0xf1008831, 0x682a509e, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48cdfeb2, 0xf026301c, 
+    0x49cff88d, 0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 0xfea3f7ff, 0x306848c5, 0xf87ef026, 
+    0xf1008831, 0x682a50a0, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48befe94, 0xf026306a, 0x8831f86f, 
+    0x50a8f100, 0xea40682a, 0x68214001, 0x0022f841, 0xfe85f7ff, 0x306c48b6, 0xf860f026, 0xf1008831, 
+    0x682a50b0, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48b4fe76, 0xf852f026, 0xf1008831, 0x682a50b8, 
+    0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48aefe68, 0xf844f026, 0xf1008831, 0x682a50c0, 0x4001ea40, 
+    0xf8416821, 0xe8bd0022, 0xe6584070, 0xb5102005, 0xffe0f004, 0x680a49a5, 0xd2034282, 0x681a4ba4, 
+    0x601a1c52, 0xe41b6008, 0x5ff0e92d, 0x48984604, 0xf0263068, 0x2204f823, 0xf00021f0, 0x489a051f, 
+    0xf847f026, 0xf7ffb2c7, 0x4e9affe1, 0xf8df2207, 0xf8df8268, 0x6831b268, 0xf8c84658, 0xf2401000, 
+    0xf0261180, 0xf8dff836, 0xf04f9258, 0xb3000a01, 0x46582205, 0xf0262120, 0x2801f82c, 0xf899d10c, 
+    0x42850000, 0x2200d008, 0x211f4658, 0xf821f026, 0x1000f899, 0xd00c4288, 0x46582205, 0xf0262120, 
+    0xb940f818, 0x46582200, 0xf026211f, 0x42a8f812, 0xf8c6d101, 0x2206a000, 0x21404880, 0xf809f026, 
+    0xf899b148, 0x428d1000, 0xf899d105, 0x42870001, 0x2c00d101, 0xf889d073, 0x2c0a5000, 0xb1e4f8df, 
+    0xf8894d79, 0xd9057001, 0x0000f8db, 0xf8406829, 0xe0104021, 0xd1102c01, 0xf0254874, 0x4607ffbf, 
+    0x1e804872, 0xffbaf025, 0xea47682a, 0xf8db4100, 0xf8400000, 0xf7ff1022, 0x4868fdd2, 0xf2402207, 
+    0xf0251180, 0xb170ffd6, 0x22074864, 0x1180f240, 0xffcff025, 0x68302801, 0x77fff640, 0xb3e8d010, 
+    0xd0242801, 0xf7ffe026, 0x4d5cfe21, 0x46281dad, 0xff94f025, 0xb2811c40, 0xf0254628, 0xe051ff92, 
+    0xd1522801, 0x9154f8df, 0x220e0381, 0xf0254648, 0xb318ffb0, 0x30106828, 0xdb2542b8, 0x60302000, 
+    0xf8c82301, 0x220a0000, 0x02994648, 0xf8d8e038, 0xb1e00000, 0x000cf8d9, 0xd30c42b8, 0xf1f7fbb0, 
+    0x0311fb07, 0xf1016829, 0x45630c10, 0xf8d9d80c, 0x42912008, 0x42b8d808, 0xe001d21a, 0xe057e004, 
+    0x31106829, 0xd2134281, 0xfde0f7ff, 0xf8dbe01a, 0xf04f0000, 0x682a31ff, 0x1022f840, 0xfd6ff7ff, 
+    0xf8c96828, 0xf2000008, 0xf8c970ff, 0xe7eb000c, 0x60302000, 0xf8c82301, 0x48300000, 0x0299220a, 
+    0xff59f025, 0x28016830, 0x482cd007, 0xf2402207, 0xf0251180, 0x2802ff5e, 0x4828d120, 0x21402206, 
+    0xff57f025, 0xb9ccb9d0, 0x22004c29, 0x4620210f, 0xff4ff025, 0x2200b190, 0x210f4620, 0xff49f025, 
+    0xf100fa0a, 0xf240b28c, 0xe0052500, 0x46282100, 0xff08f004, 0xb2a41e64, 0xd1f72c00, 0x2200481d, 
+    0xf0252101, 0x2801ff36, 0xe8bdd102, 0xe5395ff0, 0x4915e58b, 0xb5102000, 0x49176008, 0x490c8008, 
+    0x20056008, 0xfea6f004, 0x60084908, 0x0000e6cb, 0xf38f2212, 0x12b00000, 0x12d00000, 0x13b00000, 
+    0x13d00000, 0xf38f2012, 0xf38f0004, 0x000402f0, 0x000402e8, 0x000402d8, 0x000402dc, 0xf20351a4, 
+    0x00040000, 0x0004058c, 0x000402d4, 0xf2039028, 0xf23c802a, 0xf23c8260, 0x000402e4, 0x4ff8e92d, 
+    0xb3fcf8df, 0x2800f240, 0x46152700, 0x460e2209, 0x46414604, 0x97004658, 0xfeebf025, 0xd1112801, 
+    0x200049f8, 0x72fff640, 0xf8416809, 0x1c407020, 0xd3fa4290, 0x46412300, 0x46582209, 0xfecbf025, 
+    0xffa7f7ff, 0xf2482c01, 0xeb050900, 0xd0162606, 0xd02e2c02, 0xa3b0f8df, 0x4dec2c03, 0x0100f242, 
+    0x0801f04f, 0x2cfed02b, 0x2c04d07e, 0x220dd125, 0x4658465c, 0xfebdf025, 0xd0762801, 0x220fe084, 
+    0x465c4649, 0xf0254658, 0x2800feb4, 0x220ed015, 0x0100f244, 0xf0254620, 0x2800feac, 0x220ad10d, 
+    0x4100f240, 0xf0254620, 0x2800fea4, 0x48d8d105, 0x48d8e000, 0xf7ff4430, 0xe8bdfe47, 0x220d8ff8, 
+    0x46584654, 0x7002f88a, 0xfe93f025, 0xd1032801, 0x20aaf64a, 0xfa85f7ff, 0xf44f4fcf, 0x46ca0000, 
+    0x900046d9, 0x4ac6e00d, 0x46682100, 0xf0043a2a, 0x2801fede, 0x48c9d0e1, 0xf7ff4430, 0xf884fe25, 
+    0x220f8002, 0x46484651, 0xfe73f025, 0xd1d42801, 0x46280381, 0xf025220e, 0x2800fe6c, 0x2204d1cd, 
+    0x21104628, 0xfe65f025, 0xd1c62800, 0x46282205, 0xf0252120, 0x2800fe5e, 0x2203d1bf, 0x21084638, 
+    0xfe57f025, 0xd1b82800, 0x46382204, 0xf0252110, 0x2800fe50, 0x2205d1b1, 0x21204638, 0xfe49f025, 
+    0xd1aa2800, 0xe001220a, 0xe009e008, 0x4100f240, 0xf0254648, 0x2800fe3e, 0xe79ed0b5, 0xe79a48a8, 
+    0x30bbf64b, 0xfa2df7ff, 0xf640220b, 0x46200100, 0xfe2ff025, 0xf04f0001, 0x465630dd, 0x7002f88a, 
+    0x4647d007, 0xf04f4683, 0x46ca0802, 0x4900f240, 0xf8dfe056, 0xf44fa24c, 0x46470100, 0xf1aa4683, 
+    0xf2400a2a, 0x91004800, 0x2101e00b, 0x46684652, 0xfe6df004, 0xd0d02801, 0xb33078b0, 0xf7ff2000, 
+    0x220ffdb3, 0x46204649, 0xfe03f025, 0xd1c42801, 0x46280381, 0xf025220e, 0x2800fdfc, 0x2204d1bd, 
+    0x21104628, 0xfdf5f025, 0xd1b62801, 0x22044885, 0xf02521f0, 0x2801fdee, 0x220ad0af, 0x46204641, 
+    0xfde7f025, 0xd0d02800, 0x4658e747, 0xfd8cf7ff, 0xe7d670b7, 0xf244220e, 0x46280100, 0xfdd9f025, 
+    0x78b02800, 0x2802d008, 0xf04fd007, 0xf7ff30ee, 0xf886fd7b, 0xe0038002, 0x2000b1c0, 0xfd74f7ff, 
+    0x4651220f, 0xf0254620, 0x2801fdc4, 0x2204d185, 0x21104628, 0xfdbdf025, 0xd1d52801, 0x4649220a, 
+    0xf0254620, 0x2800fdb6, 0xe716d0d4, 0xf7ff4658, 0x70b7fd5b, 0x4864e7e4, 0xf025b510, 0x2200fd7f, 
+    0x20014601, 0xfdbbf7fd, 0x1c80485f, 0xfd76f025, 0x46012200, 0xf7fd2001, 0x485bfdb2, 0xf0251d00, 
+    0x2200fd6d, 0xe8bd4601, 0x20014010, 0xbda7f7fd, 0x460cb570, 0x22004615, 0x20014601, 0xfd9ff7fd, 
+    0x46212200, 0xf7fd2001, 0x4629fd9a, 0x4070e8bd, 0x20012200, 0xbd93f7fd, 0x41f0e92d, 0xf2482008, 
+    0xf04f0125, 0xf7fd52b8, 0x4d48fd8a, 0xf242220d, 0x46280100, 0xfd6df025, 0x4604220c, 0x0100f241, 
+    0xf0254628, 0x4d42fd66, 0xf1054204, 0xf1050602, 0xf1050704, 0xd01c0406, 0xf025483e, 0x4601fd2f, 
+    0xf0254628, 0x483bfd2e, 0xf0251c80, 0x4601fd27, 0xf0254630, 0x4837fd26, 0xf0251d00, 0x4601fd1f, 
+    0xf0254638, 0x4833fd1e, 0xf0251d80, 0x4601fd17, 0x2100e00c, 0xf0254628, 0x2100fd14, 0xf0254630, 
+    0x2100fd10, 0xf0254638, 0x2100fd0c, 0xf0254620, 0x4829fd08, 0xfd02f025, 0x48254601, 0xf0253008, 
+    0x2004fd00, 0x81f0e8bd, 0xb5104821, 0xfcf6f025, 0x80084922, 0x1c80481e, 0xfcf0f025, 0x80084920, 
+    0x1d00481b, 0xfceaf025, 0x481e4601, 0xfce9f025, 0xe4b82004, 0xb5104819, 0x48158801, 0xfce1f025, 
+    0x88014817, 0x1c804812, 0xfcdbf025, 0xf0254815, 0x4601fcd5, 0x1d00480e, 0xfcd3f025, 0xe4a22004, 
+    0xf20351a4, 0x0004058c, 0x00040000, 0xf2039026, 0xaaaa0000, 0xbbbb0000, 0xf2035040, 0xcccc0000, 
+    0xdddcdddd, 0xf38f0004, 0xf38e002c, 0xf38fffd4, 0xf23c8070, 0xf38f2210, 0xf3cf2008, 0x0004031c, 
+    0x0004031e, 0xf23d014e, 0x41f0e92d, 0x8400f8df, 0x21022201, 0xf0254640, 0xf108fccc, 0x46050402, 
+    0x46202201, 0xf0252102, 0xea45fcc4, 0x48f90100, 0xfc97f025, 0x22024df8, 0x46282104, 0xfcb9f025, 
+    0x22024ef5, 0x46072104, 0x4630360a, 0xfcb1f025, 0x0100ea47, 0x1c8048ef, 0xfc83f025, 0x46202201, 
+    0xf0252102, 0x2202fca6, 0x21044604, 0xf0254630, 0xea44fca0, 0x46400600, 0x21022201, 0xfc99f025, 
+    0x46042202, 0x46282104, 0xfc93f025, 0xea464304, 0xb2810044, 0x1d0048df, 0xfc63f025, 0xe7612004, 
+    0x4ff8e92d, 0xf02548db, 0xb2c4fc59, 0x1c8048d9, 0xfc54f025, 0x9000b2c0, 0x1d0048d6, 0xfc4ef025, 
+    0xf8dfb2c5, 0x4ed68358, 0x07a84fd6, 0xf640d570, 0x46380900, 0x46492301, 0xf025220b, 0xf8dffc5c, 
+    0x2206a330, 0x46232140, 0xf0254650, 0xb184fc54, 0xf6412314, 0x22087100, 0x0004f1aa, 0xfc4bf025, 
+    0x232748c3, 0xf2402204, 0x389a31f0, 0xfc43f025, 0xf898e003, 0xf0060000, 0xf8dff995, 0x2308b2f4, 
+    0xf10b2200, 0x211f0b14, 0xf0254658, 0x2324fc34, 0x7100f643, 0x46582208, 0xfc2df025, 0x46cb2300, 
+    0x4649220b, 0xf0254638, 0x2301fc26, 0x220b4659, 0xf0254630, 0x2201fc20, 0x21024623, 0x465046d1, 
+    0xfc19f025, 0x46232207, 0x46482180, 0xfc13f025, 0x46592300, 0x4630220b, 0xfc0df025, 0x9298f8df, 
+    0x21022301, 0x4648461a, 0xfc05f025, 0x22009b00, 0x46482101, 0xfbfff025, 0x46482300, 0x21022201, 
+    0xfbf9f025, 0x22029b00, 0x46482104, 0xfbf3f025, 0xd06d07e8, 0x0900f241, 0x230146ba, 0x220c4649, 
+    0xf0254638, 0x4d92fbe8, 0x21082203, 0x1cad4623, 0xf0254628, 0xb17cfbe0, 0xf6412310, 0x22087100, 
+    0xf0251f28, 0x488afbd8, 0x22042324, 0x31f0f240, 0xf0253898, 0xe003fbd0, 0x0000f898, 0xf922f006, 
+    0x23084f83, 0x37162200, 0x4638211f, 0xfbc3f025, 0xf6432320, 0x22087100, 0xf0254638, 0x2300fbbc, 
+    0x220c464f, 0x46504649, 0xfbb5f025, 0x46392301, 0x4630220c, 0xfbaff025, 0x46232201, 0x46282102, 
+    0xfba9f025, 0x46232204, 0x46282110, 0xfba3f025, 0x46392300, 0x4630220c, 0xfb9df025, 0x23014c6e, 
+    0x461a2102, 0x4620340a, 0xfb95f025, 0x22009b00, 0x46202101, 0xfb8ff025, 0x46202300, 0x21022201, 
+    0xfb89f025, 0x22029b00, 0x46202104, 0xfb83f025, 0xe4f22004, 0xb5104864, 0x485e7801, 0xfb61f025, 
+    0x88004862, 0x485bb281, 0xf0251c80, 0x2004fb5a, 0x4858e45c, 0xf025b510, 0x495bfb51, 0x48557008, 
+    0xf0251c80, 0x4959fb4b, 0x20046008, 0x4858e44e, 0xf990b510, 0xb2810000, 0xf025484e, 0x2004fb42, 
+    0x484ce444, 0xf025b510, 0x4951fb39, 0x20047008, 0x4951e43c, 0xb5102200, 0xe9d14c4e, 0x46230100, 
+    0xfbd4f027, 0xfb0ef027, 0x4842b281, 0xfb29f025, 0x2200494a, 0xe9d14623, 0xf0270100, 0xf027fbc7, 
+    0xb281fb01, 0x1c80483b, 0xfb1bf025, 0x78014844, 0x1d004838, 0xfb15f025, 0x48424943, 0x78007809, 
+    0x2101ea40, 0x1d804833, 0xfb0bf025, 0x7801483f, 0x30084830, 0xfb05f025, 0xe4072004, 0xb510482d, 
+    0xfafcf025, 0x4c33b200, 0xd0081c41, 0xfb37f027, 0x46232200, 0xf97ef027, 0xe9c24a2f, 0x48250100, 
+    0xf0251c80, 0xb200faeb, 0xd0081c41, 0xfb27f027, 0x46232200, 0xf96ef027, 0xe9c24a28, 0x481d0100, 
+    0xf0251d00, 0x4926fadb, 0x1da44c1a, 0x46207008, 0xfad4f025, 0x0a014a24, 0x70112920, 0x2020d901, 
+    0x46207010, 0xfacaf025, 0x7008491e, 0x30084811, 0xfac4f025, 0x7008491d, 0xe5da2004, 0xb510481c, 
+    0x480c7801, 0xfabdf025, 0x7801481a, 0x1c804809, 0xfab7f025, 0x78014818, 0x1d004806, 0xfab1f025, 
+    0x78014816, 0x1d804803, 0xfaabf025, 0xe5c02004, 0xf2035336, 0xf23c8070, 0xf307409a, 0x00040242, 
+    0xf23c8306, 0xf2035026, 0x000404ee, 0x000404f0, 0x0004031a, 0x40c38800, 0x00040288, 0x00040290, 
+    0x00040287, 0x00040566, 0x00040565, 0x00040567, 0x000404ec, 0x0004059c, 0x0004059d, 0x000404ed, 
+    0xb5104845, 0xfa7af025, 0x70084944, 0x1c804842, 0xfa74f025, 0xf0004942, 0x70080003, 0x1d00483e, 
+    0xfa6cf025, 0xf000493f, 0x70080003, 0x1d80483a, 0xfa64f025, 0x7008493c, 0xe57a2004, 0xb510483b, 
+    0x48357801, 0xfa5df025, 0x78014839, 0x1c804832, 0xfa57f025, 0xe56c2004, 0xb510482f, 0xfa4ef025, 
+    0x70084932, 0x1c80482c, 0xfa48f025, 0x70084930, 0xe55e2004, 0xb510482f, 0x48277801, 0xfa41f025, 
+    0xe5562004, 0xb5104824, 0xfa38f025, 0x70084929, 0xe54e2004, 0xb5104828, 0x481f7801, 0xfa31f025, 
+    0xe5462004, 0xb510481c, 0xfa28f025, 0x70084922, 0xe53e2004, 0xb5104821, 0x48177801, 0xfa21f025, 
+    0x7801481f, 0x1c804814, 0xfa1bf025, 0xe5302004, 0xb5104811, 0xfa12f025, 0x70084918, 0x1c80480e, 
+    0xfa0cf025, 0x70084916, 0xe5222004, 0xb5104815, 0x48097801, 0xfa05f025, 0x78014813, 0x1c804806, 
+    0xf9fff025, 0xe5142004, 0xb5104803, 0xf9f6f025, 0x7008490c, 0xe50c2004, 0xf23c8070, 0x000404ec, 
+    0x0004059c, 0x0004059d, 0x000404ed, 0x000404f4, 0x000404f5, 0x000404f6, 0x000402ae, 0x000404fc, 
+    0x000404fd, 0x000402b0, 0x000402b2, 0xf01cb510, 0xf016f99b, 0xf000f955, 0xf000f87d, 0xf021fede, 
+    0x2001f970, 0x0000bd10, 0x48fab570, 0x31b4f64b, 0xf9c7f025, 0x250148f8, 0x24004af8, 0x49f94bf8, 
+    0x28d08800, 0x28f0d049, 0x7014d047, 0x700c701d, 0x600448f5, 0x600448f5, 0x700448f5, 0x800448f5, 
+    0x800448f5, 0x700448f5, 0x700448f5, 0x700448f5, 0xf0044620, 0x49f4f987, 0x48f47008, 0x48f47004, 
+    0xb1007800, 0x49f32020, 0x21248008, 0x700448f2, 0x700448f2, 0x700448f2, 0x700548f2, 0x700548f2, 
+    0x720448f2, 0x70047244, 0x210c7041, 0x70c47084, 0x71417104, 0x718449ef, 0x600848ed, 0x48ee49ef, 
+    0x48ef6008, 0x28018800, 0xf04fd00b, 0x49ed0001, 0xd1097008, 0x0002f04f, 0x7015e008, 0x700d701c, 
+    0xf04fe7b6, 0xe7f20002, 0x0001f04f, 0x700849e6, 0x2144f240, 0xf02548e5, 0x49e5f964, 0x4000f241, 
+    0x48e48008, 0x680049e4, 0xf44f6008, 0x49e320be, 0xbd706008, 0xf007b510, 0x2201fb5e, 0x20051e94, 
+    0xf0044621, 0x2201f90d, 0x20004621, 0xf908f004, 0xf805f022, 0xff78f7ff, 0xf99ff7fd, 0xfefaf008, 
+    0xfa60f016, 0xff64f009, 0xfa36f021, 0xfb3af023, 0xfb98f004, 0x210448af, 0xf025384c, 0xe8bdf932, 
+    0xf0054010, 0xe92dba05, 0xf8df47f0, 0x28049334, 0x4617461e, 0xa020f8dd, 0x4604460d, 0x4800f640, 
+    0x2c05d017, 0x2000d027, 0xfc03f005, 0x4632462b, 0x46204639, 0xfc62f005, 0x46202100, 0xfccff005, 
+    0x46412300, 0x4648220a, 0xf925f025, 0x46082100, 0x4608e027, 0xfbedf005, 0x4632462b, 0x46204639, 
+    0xfc4cf005, 0x2100b12f, 0xf0054620, 0x2302fcb8, 0x4651e010, 0x4608e7f8, 0xfbdbf005, 0x4632462b, 
+    0x46204639, 0xfc3af005, 0x2100b1b6, 0xf0054620, 0x2301fca6, 0x220a4641, 0xf0254648, 0x2101f8fc, 
+    0xf0194608, 0xf505f9db, 0xe8bd7100, 0xf04f47f0, 0x12505280, 0xb913f7fd, 0xe7e74651, 0x47f0e92d, 
+    0x48a00005, 0x0400f04f, 0x7004468a, 0x7004489e, 0x7004489e, 0x7004489e, 0x7004489e, 0x7004489e, 
+    0x489ed124, 0x700449a1, 0x7004489d, 0x7004489d, 0x7004489d, 0x70082004, 0x7008499d, 0x7008499d, 
+    0x7008499d, 0x7004489d, 0x7004489d, 0x7004489d, 0x7004489d, 0x7004489d, 0x7004489d, 0x7004489d, 
+    0x7004489d, 0x7004489d, 0x7004489d, 0x489d2701, 0x489d7007, 0x489d7007, 0x489d7007, 0x489d7007, 
+    0x489d7007, 0x489d7007, 0x489d7007, 0x489d7007, 0x489d7004, 0x489d7004, 0x489d7004, 0x489d7004, 
+    0x489d7004, 0x489d7004, 0x489d7004, 0x489d7004, 0x489d7004, 0x489d8004, 0x489d8004, 0x489d7004, 
+    0x489d7004, 0x489d7004, 0x489d7004, 0x489d7004, 0x20018004, 0xfbcef007, 0xf0072005, 0x489afbe7, 
+    0xf8202100, 0x1c494011, 0x2904b249, 0x2001dbf9, 0xfbfaf007, 0xf0072000, 0xb935fbf7, 0x78014893, 
+    0x29034893, 0x2103d020, 0x48927001, 0x0f04f1ba, 0xf8df4a4f, 0xf8dfc140, 0x70048140, 0xf8df488e, 
+    0x494e9150, 0x70044b8e, 0x4e8e488c, 0xd00d4d8e, 0x2000f8cc, 0x0f05f1ba, 0x8000f8c1, 0x4a8bd02e, 
+    0x2a126812, 0xe119d054, 0xe7de7007, 0x2000f8cc, 0x72b8f644, 0x8000f8c1, 0x2000f8a9, 0x28037800, 
+    0xb1c8d019, 0xd0172801, 0xd0152802, 0x7818701c, 0x0140eb00, 0x1000eb01, 0x00c0eb06, 0x79016028, 
+    0x7f047982, 0x79424411, 0x440a7d87, 0x1b097ec1, 0x443c7e44, 0x2002e020, 0xe7e87018, 0x72dcf242, 
+    0x2000f8a9, 0x28037800, 0xb300d023, 0xd01e2801, 0xd01c2802, 0x7818701c, 0x0140eb00, 0x1000eb01, 
+    0x00c0eb06, 0x79016028, 0x7f447982, 0x79424411, 0x7ec1440a, 0x7d841b09, 0x83c14421, 0x44217c44, 
+    0x44217d04, 0x442279c4, 0x1c891a51, 0xe0c1e0e0, 0xe0bde0c2, 0xf23c80ba, 0x000404fe, 0x000402b0, 
+    0x000402cc, 0x00040575, 0x00057f7c, 0x00057f80, 0x00040235, 0x00040236, 0x00040238, 0x0004023a, 
+    0x0004023b, 0x00040242, 0x00040243, 0x000401fc, 0x0004052b, 0x00040240, 0x00040277, 0x00040278, 
+    0x000404f6, 0x00040577, 0x00040579, 0x0004d108, 0x0003d090, 0x00040580, 0x1e8c2120, 0x00040584, 
+    0x0004031c, 0x000402ca, 0x000402cb, 0xf23d014e, 0x00040588, 0x000401dc, 0x0004058c, 0x00040590, 
+    0xf2030802, 0x000401ff, 0x00040200, 0x00040201, 0x00040202, 0x00040203, 0x00040204, 0x00040205, 
+    0x00040206, 0x00040207, 0x00040208, 0x00040209, 0x0004020a, 0x0004020b, 0x0004020c, 0x0004020d, 
+    0x0004020e, 0x0004020f, 0x00040210, 0x00040211, 0x00040212, 0x00040213, 0x00040285, 0x00040edb, 
+    0x00040edc, 0x00040214, 0x00040215, 0x00040216, 0x00040217, 0x00040218, 0x00040219, 0x0004021a, 
+    0x0004021b, 0x0004021c, 0x0004021d, 0x0004021e, 0x0004021f, 0x00040220, 0x00040221, 0x00040222, 
+    0x00040223, 0x00040224, 0x00040226, 0x00040228, 0x0004022a, 0x0004022b, 0x0004022c, 0x0004022d, 
+    0x000401fe, 0x0004054c, 0x0004054e, 0x00040234, 0x00040248, 0x00040244, 0x00040245, 0x000402ae, 
+    0x00040322, 0x00040324, 0x00040598, 0x000401f0, 0xe720701f, 0xe71e7018, 0x600a4afe, 0x4200f241, 
+    0x2000f8a9, 0x28037800, 0x2800d005, 0x2801d07e, 0x2802d07c, 0x701cd07a, 0xeb007818, 0xeb010140, 
+    0xeb061000, 0x602800c0, 0x31147ec1, 0x217883c1, 0x7c80f643, 0xf8a02200, 0x27051044, 0x0042eb02, 
+    0x1002eb00, 0x00c0eb06, 0x79016028, 0xf8b07984, 0x4421e01e, 0x44217944, 0x44747c44, 0xe015f890, 
+    0x040eeba4, 0x84878444, 0xf8b07c44, 0x4474e01e, 0xe015f890, 0x040eeba4, 0xe017f890, 0x040eeba4, 
+    0x7b0485c4, 0x7b448544, 0x7ac486c4, 0xe00ef890, 0x34404474, 0xf1018744, 0x87840448, 0x1f24004c, 
+    0x4042f8a0, 0xf8b079c4, 0x4474e01e, 0xe011f890, 0x4474448e, 0xe014f890, 0xf8b04474, 0xf5c4e000, 
+    0xeb045400, 0xf8a0049e, 0x79c44048, 0xe012f890, 0xf8904474, 0x448ee013, 0xf5c44474, 0x86445400, 
+    0xf8907a84, 0x4474e009, 0x5400f5c4, 0x404af8a0, 0xf8907bc4, 0x4474e010, 0x404cf8a0, 0x0444ebac, 
+    0x404ef8a0, 0xf8a03c10, 0xe0004050, 0xf890e01e, 0x1c524058, 0xe05bf890, 0x4474b252, 0xe05cf890, 
+    0xf8904471, 0x4421e059, 0x405af890, 0x1b094474, 0x105ef8a0, 0xdb812a03, 0xeb007818, 0xeb010140, 
+    0xeb061000, 0x602800c0, 0x87f0e8bd, 0xe7637018, 0x4ff1e92d, 0x210048a8, 0xf024b082, 0x48a6fe62, 
+    0x1f802100, 0xfe5df024, 0x240048a4, 0x46207004, 0xff78f004, 0xfbc4f008, 0xf0069802, 0x48a0ffcb, 
+    0x28017800, 0x2000d000, 0xf8cbf019, 0x200f2300, 0x4619461a, 0x46189000, 0xffe6f006, 0x20009902, 
+    0xfd6cf7ff, 0xf8df9802, 0x4d97925c, 0x4e972803, 0xf899d025, 0x78290000, 0xd1244308, 0x78014894, 
+    0x78004894, 0xf8faf00a, 0x4a944993, 0x78127809, 0xe9cd4011, 0x48920100, 0x48927803, 0x40037800, 
+    0x78024891, 0x78004891, 0x48914002, 0x48917801, 0x40017800, 0xf00a9802, 0x7030f8cb, 0x498ee003, 
+    0x70342022, 0x488d8008, 0x90007800, 0x7831488c, 0x488c7803, 0x98027802, 0xfcd5f7ff, 0x27017833, 
+    0x8224f8df, 0xd1012b03, 0x7000f888, 0x68004887, 0xd0162812, 0xd0142816, 0x21004885, 0x9a029400, 
+    0x00407800, 0xf017b240, 0xf016fd19, 0x7828f9c2, 0x28034d80, 0x2801d025, 0xf899d008, 0xb9e00000, 
+    0x2100e00f, 0x20049a02, 0xe7ec9400, 0xff49f015, 0x2100702f, 0x46089400, 0x9a027833, 0xfcfef017, 
+    0x4875e012, 0x28027800, 0x2801d00b, 0x4873d005, 0x21012200, 0xfdedf024, 0xf015b118, 0x702fff32, 
+    0xf015e002, 0x702cff3c, 0xf8df2200, 0x210391b4, 0xf899486c, 0xf0243000, 0xf899fdce, 0x22000000, 
+    0xa1a8f8df, 0x0140eb00, 0x1000eb01, 0xeb014966, 0xf8ca00c0, 0x210f0000, 0x3068f890, 0xf0244864, 
+    0xf04ffdba, 0x486339ff, 0xf0244649, 0x4962fd94, 0xf8c12300, 0x46a19000, 0x46192401, 0xe9cd4622, 
+    0x78284900, 0xf004b240, 0x4854feb5, 0x7b00f647, 0x46592300, 0x38242208, 0xfd9df024, 0x23004f4f, 
+    0x461a217f, 0x46383f22, 0xfd95f024, 0x46592300, 0x46382208, 0xfd8ff024, 0x1f3821d2, 0xfd71f024, 
+    0x1fb82100, 0xfd6df024, 0xf0092002, 0x484bfb32, 0x494c4a4b, 0x808480c4, 0x80048044, 0xf0057833, 
+    0x2172fd53, 0xf7fc05a0, 0x0321fd74, 0x23004c46, 0x4620220c, 0xfd6ff024, 0xf2422300, 0x220d0100, 
+    0xf0244620, 0x2300fd68, 0x0100f244, 0x4620220e, 0xfd61f024, 0x0700f248, 0x23004620, 0x220f4639, 
+    0xfd59f024, 0x28037830, 0x4831d07a, 0x220f2301, 0x38364639, 0xfd4ff024, 0x0000f8da, 0x7f8046d3, 
+    0xfcc4f006, 0xa0c4f8df, 0x4c312000, 0xf8ba4f31, 0x78223000, 0x1000f997, 0xfe81f005, 0x3000f8ba, 
+    0x78222000, 0x1000f997, 0xfb3cf006, 0xfb36f002, 0xe0524818, 0x2245cdc0, 0xf23c80b8, 0x00040d84, 
+    0x000402b2, 0x000402a4, 0x00040234, 0x0004057b, 0x000402cf, 0x000402cc, 0x000402d0, 0x0004058a, 
+    0x00040577, 0x00040578, 0x00040579, 0x0004057a, 0x00040575, 0x00040576, 0x000402fa, 0x000402f7, 
+    0x000402cb, 0x000402ca, 0x00040248, 0x000401f0, 0x00040209, 0x00040502, 0x000401fb, 0xf2035040, 
+    0x00040322, 0xf203005e, 0x00040324, 0x00040598, 0xf2030448, 0xf1000048, 0x000402a8, 0x00040538, 
+    0x00040520, 0x0004054e, 0xf20305c0, 0x00040270, 0x000402c8, 0x000401ec, 0x7800e002, 0xe01ab1b0, 
+    0x208049fa, 0x3001f991, 0x0013f82d, 0x3000f991, 0x0013f82d, 0x3003f991, 0xf82d4668, 0xf9919013, 
+    0xf82d1002, 0xf0059011, 0xe775fc03, 0xf2407831, 0xf0021000, 0x2001facd, 0xfc3ff006, 0x46544dec, 
+    0x3000f8ba, 0x1000f997, 0x782a7830, 0xfdf7f005, 0x782a8823, 0x1000f997, 0xf0067830, 0x48e5fab3, 
+    0xf2402200, 0xf02471ff, 0xf8dffcb4, 0x2200a38c, 0x71fff240, 0x0000f8aa, 0x1c8048de, 0xfca9f024, 
+    0x48deb201, 0x461a2300, 0xf9ba8001, 0xf0040000, 0x2101fe3b, 0x46082302, 0xf0042208, 0xf8dbf924, 
+    0x46da0000, 0x1064f9b0, 0x0066f9b0, 0xf8f6f004, 0x0000f8da, 0x2062f890, 0x1061f890, 0x0060f890, 
+    0xf8d2f004, 0xb338f8df, 0x220c2300, 0x0100f24f, 0xf0244658, 0x2300fc59, 0x7100f640, 0x46582208, 
+    0xfc52f024, 0x46582300, 0x21f02204, 0xfc4cf024, 0x46582300, 0x461a210f, 0xfc46f024, 0xb2f4f8df, 
+    0x2200230f, 0xf10b4619, 0x46580b58, 0xfc53f024, 0x46582300, 0x21802207, 0xfc4df024, 0x46582300, 
+    0x21202205, 0xfc47f024, 0xf0182001, 0x8820fe1b, 0x20009000, 0xf997782b, 0x78312000, 0xfd5df018, 
+    0xfcd8f018, 0xf0042000, 0xf004f81d, 0xf004f821, 0xf002f83c, 0x7831fde4, 0xf0059802, 0xf005f8c3, 
+    0x48a4ffb8, 0x22002301, 0x38244619, 0xfc23f024, 0x780148a4, 0xf0042000, 0x489efd78, 0x21022301, 
+    0x3816461a, 0xfc17f024, 0xf0182000, 0x4c9efc75, 0x22012300, 0x46202102, 0xfc0df024, 0x23004d9b, 
+    0x21022201, 0xf0244628, 0xf04ffc06, 0x23004771, 0x22114638, 0x3100f44f, 0xfbe6f024, 0x46382301, 
+    0x46192200, 0xfbe0f024, 0xf2442100, 0xf0030000, 0x2300fbc9, 0x21014638, 0xf024461a, 0x2301fbd5, 
+    0x21024620, 0xf024461a, 0x2301fbe6, 0x21024628, 0xf024461a, 0x2100fbe0, 0xf0082004, 0xf008fd00, 
+    0x4c83fbcf, 0x28007820, 0x2002d07e, 0xfdccf008, 0x68004880, 0xfbf3f026, 0x4b804a7f, 0xfc56f026, 
+    0xfb90f026, 0x2100b200, 0xfba9f008, 0xf0082000, 0x2001fb50, 0xfb4df008, 0xf0082002, 0x2003fb4a, 
+    0xfb47f008, 0xf9954d76, 0xf0080000, 0xf995faf9, 0xf0080000, 0x4873fb8d, 0xf02421c0, 0x4d72fb92, 
+    0x0000f995, 0xf022b280, 0x2001fbd1, 0xfc7af005, 0x2000f998, 0x200c2100, 0xfbf6f005, 0xf0082000, 
+    0x2001fb21, 0x46039000, 0x46014602, 0xfb9af008, 0xf0032003, 0x7829fc43, 0x78302200, 0xfc61f009, 
+    0x48634962, 0x78007809, 0x0100e9cd, 0x78034861, 0x78024861, 0x78014861, 0x78004861, 0xfd84f009, 
+    0xfe33f002, 0xf64f485f, 0xf02471ff, 0x485efb5a, 0xb2818800, 0x1c80485b, 0xfb53f024, 0x8800485b, 
+    0x4858b281, 0xf0243016, 0x4859fb4c, 0xb2818800, 0x1d004854, 0xfb45f024, 0x21004852, 0xf0243018, 
+    0x4850fb40, 0xe0002100, 0x301ae02f, 0xfb39f024, 0x2100484c, 0xf024301c, 0x484afb34, 0x301e2100, 
+    0xfb2ff024, 0x2300484b, 0x21102204, 0xfb43f024, 0x0000f8da, 0x106cf8b0, 0x206ef8b0, 0x0042f8b0, 
+    0xeb004411, 0x49440051, 0x20028008, 0xf8814943, 0xf0139000, 0x2300fcb6, 0x210f4841, 0xf024461a, 
+    0x7820fb2a, 0xd0112801, 0x2000e013, 0xfd1cf008, 0x46082100, 0xfb03f008, 0x0000f998, 0xf0084645, 
+    0xf995faa8, 0xf0080000, 0xe768fa5b, 0xf0042001, 0xe8bdfc19, 0xf0124ffe, 0xb510bd4b, 0xfafcf010, 
+    0xfc23f00a, 0xf9e4f00b, 0xfb9bf00b, 0xffdcf00b, 0xfc99f00d, 0xfbbff00e, 0xfefff00e, 0xfa9ef00f, 
+    0xfa20f01a, 0xfc78f01c, 0xfbb7f01a, 0xfb5af01b, 0xfee9f01f, 0xf98af01b, 0xfea7f01f, 0xf925f021, 
+    0xf9e8f01f, 0x4010e8bd, 0xb8bbf019, 0x00040520, 0x000402c8, 0xf203503a, 0x0004050a, 0x0004050c, 
+    0xf100004c, 0x00040243, 0xf2031008, 0xf203000a, 0x00040502, 0x0004025c, 0xeb851eb8, 0x4054f851, 
+    0x00040249, 0xf2030864, 0x00040242, 0x00040571, 0x00040572, 0x0004057d, 0x0004057c, 0x0004057f, 
+    0x0004057e, 0xf203513c, 0x00040ef4, 0x00040f20, 0x00057f80, 0xf2035250, 0x00040506, 0x000402f5, 
+    0xf23c8316, 0xe92d500f, 0xe59f0984, 0xfb000dcb, 0xe3a02103, 0xe3a01030, 0xe3a00010, 0xfbfff15e, 
+    0xe3a02103, 0xe3a01031, 0xe3a00010, 0xfbfff15a, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d4070, 
+    0xe3a00003, 0xfa000d9c, 0xe3a00002, 0xfa000d9a, 0xe3a00001, 0xfa000d98, 0xe3a00011, 0xfa000d96, 
+    0xe3a00012, 0xfa000d94, 0xe3a00001, 0xfb000cf8, 0xe3a00002, 0xfb000cf6, 0xe3a00004, 0xfb000cf4, 
+    0xe59f0910, 0xfb000dad, 0xe59f090c, 0xe3a03001, 0xe3a0200c, 0xe3011000, 0xfb00912d, 0xe59f08fc, 
+    0xe1d000d0, 0xe3700001, 0x0a00000f, 0xe3a02000, 0xe3a01007, 0xe1a00002, 0xfb0014d5, 0xe59f18e0, 
+    0xe3a00001, 0xe59f28e0, 0xe1c100b6, 0xe1c100b4, 0xe1c100b2, 0xe1c100b0, 0xe59f08c8, 0xe59f18cc, 
+    0xe5d03000, 0xe59f08b8, 0xfa001506, 0xe59f18c0, 0xe3a00000, 0xe59f58bc, 0xe3a02000, 0xe5c10000, 
+    0xe3a0000f, 0xe1c500b0, 0xe2851000, 0xe59f08a8, 0xe5900000, 0xfa00801b, 0xe59f48a0, 0xe3a02000, 
+    0xe5941000, 0xe0800001, 0xe5840000, 0xe59f0890, 0xe2851000, 0xe5900000, 0xfa008012, 0xe5941000, 
+    0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f0874, 0xe2851000, 0xe5900000, 0xfa00800a, 0xe5941000, 
+    0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f0858, 0xe2851000, 0xe5900000, 0xfa008002, 0xe5941000, 
+    0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f083c, 0xe2851000, 0xe5900000, 0xfa007ffa, 0xe5941000, 
+    0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f0820, 0xe2851000, 0xe5900000, 0xfa007ff2, 0xe5941000, 
+    0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f0804, 0xe2851000, 0xe5900000, 0xfa007fea, 0xe5941000, 
+    0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f07e8, 0xe2851000, 0xe5900000, 0xfa007fe2, 0xe5941000, 
+    0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f07cc, 0xe2851000, 0xe5900000, 0xfa007fda, 0xe5941000, 
+    0xe3a02000, 0xe0800001, 0xe5840000, 0xe3a00007, 0xe1c500b0, 0xe59f07a8, 0xe2851000, 0xe5900000, 
+    0xfa007fd0, 0xe5941000, 0xe0800001, 0xe5840000, 0xe8bd8070, 0xe1a01000, 0xe59f0788, 0xe92d4010, 
+    0xe1d000b0, 0xe3500000, 0x13a02103, 0x13011101, 0x1a00001e, 0xe59f2770, 0xe59f0770, 0xe59f4770, 
+    0xe1510002, 0x1a000005, 0xe3a02004, 0xe3a01010, 0xfb0090b6, 0xe20000ff, 0xe3a01011, 0xea00000d, 
+    0xe59f2750, 0xe1510002, 0x1a000005, 0xe3a02005, 0xe3a01020, 0xfb0090ad, 0xe20000ff, 0xe3a01012, 
+    0xea000004, 0xe3a02003, 0xe3a01008, 0xfb0090a7, 0xe20000ff, 0xe3a01001, 0xe3500001, 0xe1c410b2, 
+    0x0a000005, 0xebffff54, 0xe3a02103, 0xe3a01001, 0xe8bd4010, 0xe3a00010, 0xeafff076, 0xe3a02103, 
+    0xe3001101, 0xe3a00010, 0xfbfff0a3, 0xe1d400f2, 0xe3a02103, 0xe2801090, 0xe3a00010, 0xfbfff09e, 
+    0xe59f16d8, 0xe3a02103, 0xe59f06cc, 0xe5d11000, 0xe5d00000, 0xe0800081, 0xe2801c02, 0xe3a00010, 
+    0xfbfff095, 0xe3a00005, 0xe1c400b0, 0xe59f0690, 0xe3a02000, 0xe59f1698, 0xe5900000, 0xfa007f89, 
+    0xe59f1658, 0xe5912000, 0xe0800002, 0xe5810000, 0xe3a00004, 0xfb000c36, 0xe8bd4010, 0xe3a0000b, 
+    0xea000cb8, 0xe92d503f, 0xe59f4608, 0xe1a00004, 0xfb000cea, 0xe3a02103, 0xe3a01032, 0xe3a00010, 
+    0xfbfff07d, 0xe1a00004, 0xebffffa9, 0xe3a02103, 0xe3a01033, 0xe3a00010, 0xfbfff077, 0xf57ff05f, 
+    0xe8bd503f, 0xe25ef004, 0xe92d50ff, 0xe59f0630, 0xfa009051, 0xe59f062c, 0xfb000cd8, 0xe3a02103, 
+    0xe3a01034, 0xe3a00010, 0xfbfff06b, 0xe3a00002, 0xfa000cb1, 0xe59f0610, 0xe3a03000, 0xe3a02008, 
+    0xe3001100, 0xfb009052, 0xe59f05d8, 0xe1d000b0, 0xe3500000, 0x13a02103, 0x13011102, 0x1a000041, 
+    0xe59f05e8, 0xe3a05000, 0xe59f75e4, 0xe59f458c, 0xe5d00000, 0xe3500000, 0x0a000023, 0xe59f05d4, 
+    0xe59f15d4, 0xe59f65d4, 0xe1d000d0, 0xe1d110d0, 0xe1800001, 0xe1d610d0, 0xe1900001, 0x1a000033, 
+    0xe3a00005, 0xfa000c02, 0xe59f15b4, 0xe240093d, 0xe2400d09, 0xe3a02000, 0xe5810000, 0xe3a00001, 
+    0xe5c60000, 0xe3a0003e, 0xe1c700b0, 0xe2871000, 0xe59f0524, 0xe5900000, 0xfa007f3a, 0xe5941000, 
+    0xe0800001, 0xe5840000, 0xe59f0578, 0xe59f1578, 0xe5d00000, 0xe2800001, 0xe2000007, 0xe0800200, 
+    0xe0810100, 0xe5805008, 0xea000018, 0xe59f055c, 0xe5900000, 0xe3500000, 0x0a000000, 0xeafffffe, 
+    0xe59f054c, 0xe3a02000, 0xe59f1524, 0xe5d00000, 0xe3500003, 0x13500002, 0x059f04b4, 0x05c05000, 
+    0xe3a00009, 0xe1c700b0, 0xe59f04d4, 0xe5900000, 0xfa007f1c, 0xe5941000, 0xe3a02103, 0xe0800001, 
+    0xe3a01002, 0xe5840000, 0xe3a00010, 0xfbfff01a, 0xe3a02103, 0xe3a01035, 0xe3a00010, 0xfbfff016, 
+    0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xe92d503f, 0xe59f04e0, 0xfb000c79, 0xe3a02103, 0xe3a01036, 
+    0xe3a00010, 0xfbfff00c, 0xe59f0478, 0xe1d000b0, 0xe3500000, 0x0a00000a, 0xe3a02103, 0xe3011103, 
+    0xe3a00010, 0xfbfff004, 0xe3a02103, 0xe3a01037, 0xe3a00010, 0xfbfff000, 0xf57ff05f, 0xe8bd503f, 
+    0xe25ef004, 0xe59f0464, 0xe5d00000, 0xe3500000, 0x0afffff4, 0xe59f045c, 0xe59f245c, 0xe1d010d0, 
+    0xe1d220d0, 0xe1911002, 0x1affffee, 0xe3a04001, 0xe5c04000, 0xe59f0460, 0xe3a03000, 0xe1a02004, 
+    0xe3a01002, 0xfb008fda, 0xe3a00000, 0xfa000ded, 0xe59f0448, 0xe5d00000, 0xe3500000, 0x1a000003, 
+    0xe3a00802, 0xe3001803, 0xfbffefbc, 0xfb001f85, 0xe3a00001, 0xfa006c2c, 0xe59f0408, 0xe59f1408, 
+    0xe5d00000, 0xe2800001, 0xe2000007, 0xe0800200, 0xe0810100, 0xe5804008, 0xe3a00005, 0xfa000b8c, 
+    0xe59f13dc, 0xe240093d, 0xe2400d09, 0xe5810000, 0xe3a00000, 0xe59f1358, 0xe5c10000, 0xe3a00002, 
+    0xfa000c15, 0xe3a00003, 0xfa000c13, 0xe59f0398, 0xe3a03000, 0xe3a02008, 0xe3001100, 0xfb008fb4, 
+    0xe3a02007, 0xe3a01000, 0xe3a00001, 0xfb00148f, 0xe59f13ac, 0xe3a00043, 0xe3a02000, 0xe1c100b0, 
+    0xe59f0314, 0xe5900000, 0xfa007eb6, 0xe59f130c, 0xe5912000, 0xe0800002, 0xe5810000, 0xeaffffb1, 
+    0xe92d5fff, 0xe3a02103, 0xe3a01038, 0xe3a00010, 0xfbffefb1, 0xe59f036c, 0xe3a0200e, 0xe3041000, 
+    0xfb008fa2, 0xe59f4360, 0xe3500000, 0xe59fb35c, 0x13a00000, 0x1a000003, 0xe3a0200e, 0xe3041000, 
+    0xe1a00004, 0xfb008f99, 0xe5cb0000, 0xe59f0340, 0xfa008f81, 0xe1a08000, 0xe3a0200c, 0xe3011000, 
+    0xe1a00004, 0xfb008f91, 0xe59f9328, 0xe5c90000, 0xe59f0324, 0xfa008f78, 0xe59f1320, 0xe6bf4070, 
+    0xe7e003d4, 0xe5c10000, 0xe59f0314, 0xfa008f72, 0xe6bf6070, 0xe59f030c, 0xfa008f6f, 0xe6bf5070, 
+    0xe59f0304, 0xfa008f6c, 0xe6bf7070, 0xe3a02000, 0xe1a01006, 0xe3a00001, 0xfbffef87, 0xe3a02000, 
+    0xe1a01005, 0xe3a00001, 0xfbffef83, 0xe3a02000, 0xe1a01004, 0xe3a00001, 0xfbffef7f, 0xe59fa244, 
+    0xe5da0000, 0xe3100018, 0x0a000006, 0xe3e00000, 0xfa002114, 0xe59f22b4, 0xe3041004, 0xe3a00004, 
+    0xfbffef75, 0xea000042, 0xe5db1000, 0xe3a02000, 0xe3a00001, 0xfbffef70, 0xe5db1000, 0xe2053c01, 
+    0xe1da00b0, 0xe3510000, 0x13800080, 0x03c00080, 0xe1ca00b0, 0xe3150b01, 0x13510000, 0xe2060010, 
+    0x03a02000, 0x13a02001, 0xe1900003, 0x13140010, 0x0a000003, 0xe5d90000, 0xe3500000, 0x03a00001, 
+    0x0a000000, 0xe3a00000, 0xe206c020, 0xe193300c, 0x13140020, 0x0a000003, 0xe5d93000, 0xe3530000, 
+    0x03a03001, 0x0a000000, 0xe3a03000, 0xe3520000, 0x1a000005, 0xe59f2218, 0xe1d220d0, 0xe1911002, 
+    0x1a000007, 0xe1900003, 0x0a000005, 0xe59f0204, 0xe1d010d0, 0xe3510003, 0x13510004, 0x13510005, 
+    0x0bfffded, 0xe3180003, 0x0a000011, 0xe3e00000, 0xfa0020dc, 0xe59f01e0, 0xe3a0106d, 0xe3a02000, 
+    0xe1c060b2, 0xe1c040b4, 0xe1c050b6, 0xe1c070b8, 0xe1c010b0, 0xe2801000, 0xe59f01c0, 0xe5900000, 
+    0xfa007e30, 0xe59f10f4, 0xe5912000, 0xe0800002, 0xe5810000, 0xe3a02103, 0xe3a01039, 0xe3a00010, 
+    0xfbffef2d, 0xe59f0198, 0xfb000b94, 0xf57ff05f, 0xe8bd5fff, 0xe25ef004, 0xe92d500f, 0xe59f0184, 
+    0xfb000b8e, 0xe3a02103, 0xe3a0103a, 0xe3a00010, 0xfbffef21, 0xe3a02103, 0xe3a0103b, 0xe3a00010, 
+    0xfbffef1d, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0150, 0xfb000b80, 0xe3a02103, 
+    0xe3a0103c, 0xe3a00010, 0xfbffef13, 0xe59f113c, 0xe3a00008, 0xe3a02000, 0xe1c100b0, 0xe59f0080, 
+    0xe5900000, 0xfa007e07, 0xe59f1050, 0xe5912000, 0xe0800002, 0xe5810000, 0xe3a02103, 0xe3a0103d, 
+    0xe3a00010, 0xfbffef04, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xf0001104, 0xf0001114, 0xf203902c, 
+    0x00040262, 0x00040538, 0x0004057b, 0x00040520, 0x0004054e, 0x00040286, 0x000405f0, 0x00040f10, 
+    0x000401f4, 0x0004063c, 0x0004064c, 0x0004065c, 0x0004066c, 0x00040688, 0x0004069c, 0x000406ac, 
+    0x000406bc, 0x000406cc, 0x00040240, 0xf0001214, 0xf2035040, 0x000405f8, 0xf0001224, 0x000402d0, 
+    0x0004058a, 0xf23c80b8, 0xf0001124, 0xf2035126, 0x00040ed8, 0x000405b0, 0x00040285, 0x00040edb, 
+    0x00040edc, 0x0004026c, 0x00040ef4, 0x00041698, 0x00057f70, 0x00040574, 0xf0001134, 0xf2035114, 
+    0x00040502, 0x000405b8, 0xf2060000, 0xf38fffc0, 0x0004023d, 0xf2039048, 0x0004023c, 0xf2039026, 
+    0x0004023e, 0xf2039028, 0xf2039018, 0xf2039016, 0xcccc0000, 0x00040235, 0x00040242, 0x0004d158, 
+    0x0004114c, 0xf0001144, 0xf0001154, 0xf0001164, 0x000405c0, 0xe92d500f, 0xe59f0c6c, 0xfb000b27, 
+    0xe3a02103, 0xe3a0103e, 0xe3a00010, 0xfbffeeba, 0xebfffd61, 0xe3a02103, 0xe3a01007, 0xe3a00402, 
+    0xfbffeeb5, 0xe3a02103, 0xe3a0103f, 0xe3a00010, 0xfbffeeb1, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f0c24, 0xfb000b14, 0xe3a02103, 0xe3a01040, 0xe3a00010, 0xfbffeea7, 0xe3a02103, 
+    0xe3a01041, 0xe3a00010, 0xfbffeea3, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d50ff, 0xe59f0bf0, 
+    0xfb000b06, 0xe59f0bec, 0xfa008e7b, 0xe3500000, 0x0a00001c, 0xe59f4be0, 0xe3a01001, 0xe1a00004, 
+    0xfb008e76, 0xe284000c, 0xe3a01000, 0xfb008e73, 0xe30b1bbb, 0xe1a00004, 0xfb008e70, 0xe59f4bbc, 
+    0xe3a00062, 0xe1c400b0, 0xe59f0bb4, 0xfa008e6a, 0xe1c400b2, 0xe2841000, 0xe59f0ba8, 0xe3a02000, 
+    0xe5900000, 0xfa007d7f, 0xe51f11d0, 0xe5912000, 0xe0800002, 0xe5810000, 0xe59f0b8c, 0xe30f1fff, 
+    0xfb008e5e, 0xea00003e, 0xe59f0b80, 0xfa008e5a, 0xe3500000, 0x0a00003a, 0xe59f6b74, 0xe1a00006, 
+    0xfa008e55, 0xe51f122c, 0xe1b007a0, 0xe51f41ec, 0xe2865074, 0xe5c10000, 0x0a00002b, 0xe3a03000, 
+    0xe3a0200f, 0xe3081000, 0xe1a00006, 0xfb008e58, 0xe3a03001, 0xe3a0200b, 0xe3001800, 0xe1a00006, 
+    0xfb008e53, 0xe59f0b2c, 0xe5d00000, 0xe3500000, 0x1a000013, 0xe1a00006, 0xfa008e3f, 0xe59f1b18, 
+    0xe7e006d0, 0xe5c10000, 0xe1a00006, 0xfa008e3a, 0xe59f1b08, 0xe7e00550, 0xe5c10000, 0xe1a00006, 
+    0xfa008e35, 0xe59f1af8, 0xe7e203d0, 0xe5c10000, 0xe1a00006, 0xfa008e30, 0xe59f1ae8, 0xe7e102d0, 
+    0xe5c10000, 0xe3081000, 0xe1a00005, 0xfb008e2b, 0xe1d400b0, 0xe3800010, 0xe1c400b0, 0xe3a00004, 
+    0xfa000a8d, 0xebfffcec, 0xea000005, 0xe30f1fff, 0xe1a00005, 0xfb008e21, 0xe1d400b0, 0xe3c00010, 
+    0xe1c400b0, 0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xe92d500f, 0xe59f0a90, 0xfb000aa0, 0xe3a02103, 
+    0xe3a01085, 0xe3a00010, 0xfbffee33, 0xe3a0000a, 0xfa000a79, 0xe59f0a74, 0xe3a03000, 0xe3a0200a, 
+    0xe3001400, 0xfa008e0f, 0xe59f0a64, 0xe3a03000, 0xe3a0200a, 0xe3001400, 0xfa008e0a, 0xebfffcce, 
+    0xe3a02103, 0xe3a01086, 0xe3a00010, 0xfbffee22, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 
+    0xe59f0a30, 0xfb000a85, 0xe51f42fc, 0xe5d40000, 0xe3500001, 0x0a000002, 0xe3500002, 0x0a00001e, 
+    0xea00002a, 0xe3a02103, 0xe3a01042, 0xe3a00010, 0xfbffee11, 0xe51f0374, 0xe1d000b0, 0xe3500000, 
+    0x0a000008, 0xe3a02103, 0xe3001176, 0xe3a00010, 0xfbffee09, 0xe3a02103, 0xe3a01043, 0xe3a00010, 
+    0xfbffee05, 0xea000019, 0xe59f09cc, 0xfa008de2, 0xe1a01000, 0xe3a02000, 0xe3a00010, 0xfbffedfe, 
+    0xe3a03001, 0xe59f09b4, 0xe3a02000, 0xe1a01003, 0xfb008de7, 0xebfffca0, 0xeaffffed, 0xe3a00001, 
+    0xfb0015c3, 0xe51f5390, 0xe3a03001, 0xe3a02000, 0xe1a01003, 0xe1a00005, 0xfb008ddd, 0xe3a03001, 
+    0xe3a01002, 0xe1a02003, 0xe1a00005, 0xfb008dd8, 0xe59f096c, 0xe1d000d0, 0xe3500003, 0x13500005, 
+    0x13500004, 0x1a000005, 0xe59f0958, 0xe5d00000, 0xe3500001, 0x051f1468, 0x03a00001, 0x05c10000, 
+    0xe3a00000, 0xe5c40000, 0xe3a0000b, 0xfa000a22, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d500f, 
+    0xe59f0924, 0xfb000a3d, 0xe3a02103, 0xe3a01087, 0xe3a00010, 0xfbffedd0, 0xe3a0000c, 0xfa000a16, 
+    0xe59f08e8, 0xe3a03000, 0xe3a0200c, 0xe3011000, 0xfa008dac, 0xe59f08d8, 0xe3a03000, 0xe3a0200c, 
+    0xe3011000, 0xfa008da7, 0xebfffc6b, 0xe3a02103, 0xe3a01088, 0xe3a00010, 0xfbffedbf, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f08bc, 0xfb000a22, 0xe3a02103, 0xe3a01044, 0xe3a00010, 
+    0xfbffedb5, 0xe3a02103, 0xe3a01045, 0xe3a00010, 0xfbffedb1, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe3a02103, 0xe3a0107f, 0xe3a00010, 0xfbffeda9, 0xe59f0878, 0xfb000a10, 0xe3a02103, 
+    0xe3a01080, 0xe3a00010, 0xfbffeda3, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0854, 
+    0xfb000a06, 0xe3a02103, 0xe3a0104a, 0xe3a00010, 0xfbffed99, 0xe3a02103, 0xe3a0104b, 0xe3a00010, 
+    0xfbffed95, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0820, 0xfb0009f8, 0xe3a02103, 
+    0xe3a01083, 0xe3a00010, 0xfbffed8b, 0xe3a02103, 0xe3a01084, 0xe3a00010, 0xfbffed87, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe51f45a8, 0xe1a00004, 0xfb0009e9, 0xe3a02103, 0xe3a01023, 
+    0xe3a00010, 0xfbffed7c, 0xe1a00004, 0xebfffca8, 0xe3a02103, 0xe3a01024, 0xe3a00010, 0xfbffed76, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d503f, 0xe51f45e0, 0xe1a00004, 0xfb0009d8, 0xe3a02103, 
+    0xe3a01025, 0xe3a00010, 0xfbffed6b, 0xe1a00004, 0xebfffc97, 0xe3a02103, 0xe3a01026, 0xe3a00010, 
+    0xfbffed65, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d500f, 0xe59f0764, 0xfb0009c8, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0750, 0xfb0009c2, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f073c, 0xfb0009bc, 0xe3a02103, 0xe3a01085, 0xe3a00010, 0xfbffed4f, 0xe3a02103, 
+    0xe3a01086, 0xe3a00010, 0xfbffed4b, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0708, 
+    0xfb0009ae, 0xe3a02103, 0xe3a01058, 0xe3a00010, 0xfbffed41, 0xe3a02103, 0xe3a01059, 0xe3a00010, 
+    0xfbffed3d, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe59f06d4, 0xfb0009a0, 0xe3a02103, 
+    0xe3a0105e, 0xe3a00010, 0xfbffed33, 0xe59f06c0, 0xfa008d0e, 0xe59f46bc, 0xe584000c, 0xe59f06b8, 
+    0xfa008d0a, 0xe6bf2070, 0xe1c420b6, 0xe594000c, 0xe1b01fa0, 0xe5c41002, 0x1a000042, 0xe7e11d50, 
+    0xe5c41000, 0xe7e41850, 0xe5c41001, 0xe1a01800, 0xe1c400b8, 0xe3a00010, 0xfbffed1f, 0xe5d40000, 
+    0xe3500001, 0x1a000037, 0xe1d410d1, 0xe3510007, 0x1a000024, 0xe1d420f8, 0xe30f3ff8, 0xe6ff0072, 
+    0xe1500003, 0x1309302a, 0x11500003, 0x1a00000e, 0xe1d400f6, 0xe3a01007, 0xe1d11000, 0x0a000029, 
+    0xe2001027, 0xe59f0634, 0xe3510022, 0x03a03001, 0x0a000002, 0xe3510002, 0x03a03000, 0x1a000021, 
+    0xe3a02008, 0xe3001100, 0xea000009, 0xe30f3fe0, 0xe1500003, 0x1a000008, 0xe1d400b6, 0xe3100902, 
+    0x0a000018, 0xe59f05f8, 0xe3a03001, 0xe3a02002, 0xe3a01004, 0xfb008ce6, 0xea000012, 0xe1a00802, 
+    0xe1b00820, 0x0a000002, 0xe351001e, 0x1a00000d, 0xea000003, 0xe1d400b6, 0xe3100902, 0x1b0090b8, 
+    0xea000008, 0xe1d400b8, 0xe3041191, 0xe6ff0070, 0xe1500001, 0x1a000003, 0xe5d40006, 0xe3100001, 
+    0x0a000000, 0xeafffffe, 0xe3a02103, 0xe3a0105f, 0xe3a00010, 0xfbffece0, 0xf57ff05f, 0xe8bd503f, 
+    0xe25ef004, 0xe92d500f, 0xe3a02103, 0xe3a01060, 0xe3a00010, 0xfbffecd8, 0xe59f0568, 0xfb00093f, 
+    0xe3a02103, 0xe3a01061, 0xe3a00010, 0xfbffecd2, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 
+    0xe3a02103, 0xe3a0107c, 0xe3a00010, 0xfbffecca, 0xfa0011d1, 0xe59f0530, 0xfb000930, 0xe3a01001, 
+    0xe3a00008, 0xfa0011b0, 0xe3a00000, 0xfb0011d6, 0xe3a0001e, 0xfa000908, 0xe3a0001f, 0xfa000906, 
+    0xebfffb65, 0xe3a02103, 0xe3a0107d, 0xe3a00010, 0xfbffecb9, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f04e4, 0xfb00091c, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f04d0, 
+    0xfb000916, 0xe3a0001f, 0xfb0008fb, 0xe59f14c4, 0xe21000ff, 0xe5c10000, 0x1a000004, 0xe59f04b8, 
+    0xe3a03000, 0xe3a0200a, 0xe3001400, 0xfb008c90, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 
+    0xe59f0498, 0xfb000905, 0xe3a02103, 0xe3a0106a, 0xe3a00010, 0xfbffec98, 0xe3a02103, 0xe3a0106b, 
+    0xe3a00010, 0xfbffec94, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe59f0464, 0xfb0008f7, 
+    0xe3a02103, 0xe3a0104c, 0xe3a00010, 0xfbffec8a, 0xe3a00021, 0xfb0008d8, 0xe59f1448, 0xe6af0070, 
+    0xe51f49a0, 0xe3500000, 0xe5c10000, 0xe1d400b0, 0x0a00001a, 0xe3500000, 0x0a00001e, 0xe59f1428, 
+    0xe3a00023, 0xe3a02000, 0xe1c100b0, 0xe51f09d0, 0xe5900000, 0xfa007b73, 0xe51f1a00, 0xe5912000, 
+    0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3001110, 0xe3800002, 0xe1c400b0, 0xe3a00010, 
+    0xfbffec6d, 0xe3a02103, 0xe3a0104d, 0xe3a00010, 0xfbffec69, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 
+    0xe3d00002, 0xe1c400b0, 0x0bfffb0b, 0xe3a02103, 0xe3a01010, 0xeafffff0, 0xebfffb07, 0xeaffffe9, 
+    0xe92d503f, 0xe59f03a4, 0xfb0008c4, 0xe3a02103, 0xe3a01068, 0xe3a00010, 0xfbffec57, 0xe51f09fc, 
+    0xe3a0200e, 0xe3041000, 0xfb008c48, 0xe51f49e0, 0xe3500000, 0x13a00022, 0x1b00901b, 0xe5c40000, 
+    0xe31000ff, 0xe51f4a84, 0xe1d400b0, 0x0a00001a, 0xe3500000, 0x0a000022, 0xe59f1354, 0xe3a00022, 
+    0xe3a02000, 0xe1c100b0, 0xe51f0aac, 0xe5900000, 0xfa007b3c, 0xe51f1adc, 0xe5912000, 0xe0800002, 
+    0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3001111, 0xe3800001, 0xe1c400b0, 0xe3a00201, 0xfbffec36, 
+    0xe3a02103, 0xe3a01069, 0xe3a00010, 0xfbffec32, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3c00001, 
+    0xe3a01011, 0xe3a02103, 0xe1c400b0, 0xe3a00201, 0xfbffec29, 0xe1d400b0, 0xe3500000, 0x0bffface, 
+    0xeaffffee, 0xebfffacc, 0xeaffffe5, 0xe92d500f, 0xe59f02c0, 0xfb000889, 0xe3a02103, 0xe3a01052, 
+    0xe3a00010, 0xfbffec1c, 0xe3a02103, 0xe3a01053, 0xe3a00010, 0xfbffec18, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d50ff, 0xe3a02103, 0xe3a0105a, 0xe3a00010, 0xfbffec10, 0xe59f027c, 0xfb000877, 
+    0xe59f6278, 0xe3a03001, 0xe1a02003, 0xe3a01002, 0xe1a00006, 0xfb008bf6, 0xe59f5264, 0xe3a00001, 
+    0xe5c50000, 0xfb004f8d, 0xe59f0258, 0xe3a02000, 0xe1d010b0, 0xe3a00010, 0xfbffebff, 0xe59f0248, 
+    0xe3a02005, 0xe51f4bc4, 0xe3a01020, 0xe5d00000, 0xe3500000, 0xe1d400b0, 0x03a03000, 0x13a03001, 
+    0x03c00020, 0x13800020, 0xe1c400b0, 0xe59f021c, 0xfb008bdf, 0xe59f0218, 0xe5d00000, 0xe3500000, 
+    0xe1d400b0, 0x03c00040, 0x13800040, 0xe1c400b0, 0xe6ff0070, 0xe3d00060, 0x0a000011, 0xe3a02103, 
+    0xe3a01022, 0xe3a00010, 0xfbffebe3, 0xe3a03000, 0xe3a02001, 0xe3a01002, 0xe1a00006, 0xfb008bcc, 
+    0xe3a00000, 0xe5c50000, 0xe3a02103, 0xe3a0105b, 0xe3a00010, 0xfbffebd8, 0xf57ff05f, 0xe8bd50ff, 
+    0xe25ef004, 0xebfffa7c, 0xeafffff6, 0xe92d503f, 0xe59f01a0, 0xfb000839, 0xe3a02103, 0xe3a0104e, 
+    0xe3a00010, 0xfbffebcc, 0xe59f018c, 0xfa008baa, 0xe59f1188, 0xe200001f, 0xe1c100b0, 0xe59f1180, 
+    0xe1d120f0, 0xe1500002, 0x0a000018, 0xe51f4cac, 0xe3500000, 0xe1c100b0, 0xe1d400b0, 0x0a00005a, 
+    0xe3500000, 0x0a000062, 0xe59f1158, 0xe3a00021, 0xe3a02000, 0xe1c100b0, 0xe51f0cdc, 0xe5900000, 
+    0xfa007ab0, 0xe51f1d0c, 0xe5912000, 0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3a01012, 
+    0xe3800004, 0xe1c400b0, 0xe3a00201, 0xfbffebaa, 0xe3a02103, 0xe3a0104f, 0xe3a00010, 0xfbffeba6, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xf0001174, 0xf0001184, 0xf0001194, 0xf23c8082, 0xf23c806e, 
+    0x000405c8, 0xf23c800a, 0x00040ecc, 0xf23c807e, 0xf23c8084, 0xf23c800c, 0x00040263, 0x00040548, 
+    0x00040549, 0x0004054a, 0x0004054b, 0xf00011a4, 0xf0001030, 0xf0001034, 0xf00011b4, 0xf38f0004, 
+    0xf38f20e0, 0x000401fc, 0x00040287, 0xf00011c4, 0xf00011d4, 0xf00011e4, 0xf00011f4, 0xf0001204, 
+    0xf0001234, 0xf0001244, 0xf0001254, 0xf0001274, 0xf00012a4, 0xf1000288, 0x000405a0, 0xf100028c, 
+    0xf23c8038, 0xf23c830c, 0xf00012b4, 0xf00012c4, 0xf00012e4, 0xf00012f4, 0x00040282, 0xf20350f6, 
+    0xf0001304, 0xf0001314, 0x0004023a, 0x000405d0, 0xf0001324, 0x000405d8, 0xf0001334, 0xf0001344, 
+    0xf23c801c, 0x0004052e, 0x0004052c, 0x0004052b, 0xf38f2054, 0x00040529, 0xf0001354, 0xf2020012, 
+    0x00040236, 0x00040238, 0x000405e0, 0xe3c00004, 0xe3001112, 0xe3a02103, 0xe1c400b0, 0xe3a00201, 
+    0xfbffeb5d, 0xe1d400b0, 0xe3500000, 0x0bfffa02, 0xeaffffae, 0xebfffa00, 0xeaffffa5, 0xe92d5fff, 
+    0xe59f03b4, 0xfb0007bd, 0xe3a02103, 0xe3a01050, 0xe3a00010, 0xfbffeb50, 0xe59f43a0, 0xe1a00004, 
+    0xfa008b2d, 0xe59f6398, 0xe1a006a0, 0xe5c60000, 0xe1a00004, 0xfa008b28, 0xe59f7388, 0xe7e22550, 
+    0xe51f50f0, 0xe51f4ea4, 0xe5c72000, 0xe5d51003, 0xe5d60000, 0xe1510000, 0x1a000004, 0xe3500004, 
+    0x1a000023, 0xe5d53004, 0xe1530002, 0x0a000025, 0xe59f9354, 0xe3510000, 0xe51f8f00, 0x03500007, 
+    0x0a00002a, 0xe59fa344, 0xe3a03000, 0xe3a0200c, 0xe3011000, 0xe1a0000a, 0xfb008b1d, 0xe3a03000, 
+    0xe3a0200b, 0xe3001800, 0xe1a0000a, 0xfb008b18, 0xe1d400b0, 0xe3d00008, 0x0a000022, 0xe3a00006, 
+    0xe1c900b0, 0xe59f1300, 0xe3a02000, 0xe51f0f30, 0xe5900000, 0xfa007a1b, 0xe5981000, 0xe0800001, 
+    0xe5880000, 0xe5d60000, 0xe5c50003, 0xe5d70000, 0xe5c50004, 0xe5d60000, 0xe3500000, 0x01d400b0, 
+    0x03c00008, 0x0a000001, 0xe1d400b0, 0xe3800008, 0xe3a01051, 0xe3a02103, 0xe1c400b0, 0xe3a00010, 
+    0xfbffeb0d, 0xf57ff05f, 0xe8bd5fff, 0xe25ef004, 0xe3a0006e, 0xe1c900b0, 0xe59f128c, 0xe3a02000, 
+    0xe59f028c, 0xeaffffe1, 0xebfff9ab, 0xeaffffe4, 0xe92d500f, 0xe59f027c, 0xfb000768, 0xe3a02103, 
+    0xe3a01074, 0xe3a00010, 0xfbffeafb, 0xe3a02103, 0xe3a01075, 0xe3a00010, 0xfbffeaf7, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0248, 0xfb00075a, 0xe3a02103, 0xe3a0106c, 0xe3a00010, 
+    0xfbffeaed, 0xe3a02103, 0xe3a0106d, 0xe3a00010, 0xfbffeae9, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f0214, 0xfb00074c, 0xe3a02103, 0xe3a01046, 0xe3a00010, 0xfbffeadf, 0xe3a02103, 
+    0xe3a01047, 0xe3a00010, 0xfbffeadb, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe3a02103, 
+    0xe3a01081, 0xe3a00010, 0xfbffead3, 0xe59f01d0, 0xe3a04000, 0xe59f21d4, 0xe1d010b0, 0xe3510001, 
+    0x03a01002, 0x01c010b0, 0xe59f01b8, 0xe59f11c0, 0xe1c040b6, 0xe1c040b4, 0xe1c040b2, 0xe1c040b0, 
+    0xe59f01a4, 0xe5d03000, 0xe59f0198, 0xfa000e9d, 0xe3a00001, 0xfa001427, 0xe3a01000, 0xe3a00040, 
+    0xfa000697, 0xe3a00000, 0xfa001422, 0xe59f0184, 0xe3a0100f, 0xfb008a99, 0xe59f017c, 0xfb00071f, 
+    0xe59f0178, 0xe1d000d0, 0xe3500003, 0x13500005, 0x13500004, 0x1a000019, 0xe59f0164, 0xe59f5168, 
+    0xe5901000, 0xe2811001, 0xe5801000, 0xe59f0154, 0xe5d00000, 0xe3500000, 0x0a000017, 0xe3a00501, 
+    0xe3a01071, 0xfbffea91, 0xe1d500b0, 0xe3500014, 0x9a00000a, 0xe3a02103, 0xe3a01081, 0xe3a00010, 
+    0xfbffea9d, 0xe3a03000, 0xe59f0120, 0xe1a02003, 0xe3a01001, 0xfb008a86, 0xe1c540b0, 0xebfff93e, 
+    0xe3a02103, 0xe3a01082, 0xe3a00010, 0xfbffea92, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3a00005, 
+    0xfa000643, 0xe59f10e8, 0xe5911000, 0xe0400001, 0xe3500000, 0xc1d500b0, 0xc2800001, 0xc1c500b0, 
+    0xd1c540b0, 0xdaffffed, 0xeaffffde, 0xe92d500f, 0xe59f00c0, 0xfb0006e9, 0xe3a02103, 0xe3a0105c, 
+    0xe3a00010, 0xfbffea7c, 0xe3a02103, 0xe3a0105d, 0xe3a00010, 0xfbffea78, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f008c, 0xfb0006db, 0xe3a02103, 0xe3a01062, 0xe3a00010, 0xfbffea6e, 
+    0xe3a02103, 0xe3a01063, 0xe3a00010, 0xfbffea6a, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xf0001364, 
+    0xf2020108, 0x00040234, 0x00040528, 0x000405e8, 0xf38fffd2, 0x00040e64, 0xf0001374, 0xf0001394, 
+    0xf00013a4, 0x00040268, 0x00040538, 0x0004057b, 0x00040520, 0x0004054e, 0xf20305c4, 0xf00013b4, 
+    0x00040242, 0x00040264, 0x00040d84, 0x0004054c, 0xf20305cc, 0x0004026c, 0xf00013c4, 0xf00013d4, 
+    0x4ff0e92d, 0x49ff468b, 0x469ab087, 0x22004690, 0xe9dd6809, 0x880f9510, 0xeb00e02c, 0xf1b80180, 
+    0xeb020f00, 0xdd010441, 0xe0002101, 0x28002100, 0x2302dd01, 0x2308e000, 0x4103fb11, 0xf9334bf2, 
+    0x21006011, 0xfb02e013, 0x42731c07, 0x401cf935, 0xdd01429c, 0xe00046a6, 0x45b6469e, 0x429cda03, 
+    0x4623dd02, 0x4633e000, 0xf8251c49, 0x42b9301c, 0x1c52d3e9, 0xd3d0454a, 0x4ee40079, 0x124aea4f, 
+    0xf109fb01, 0x02c8ea42, 0xea42b20c, 0x4301014b, 0xf0414630, 0x46390780, 0xfc0df022, 0x7100f447, 
+    0xf0224630, 0x2000fc08, 0x21019005, 0x1d33462a, 0xe9cd9004, 0x46211002, 0x90019000, 0xfc00f000, 
+    0x7180f447, 0xf0224630, 0x0275fbf6, 0x126f2400, 0x1c64e002, 0xd20642ac, 0x46392208, 0xf0224630, 
+    0x2800fc01, 0xb007d1f5, 0x8ff0e8bd, 0x4fffe92d, 0xb08348c4, 0x9318f8df, 0xa048f8dd, 0xe9dd6800, 
+    0x88058b10, 0x086fb22e, 0xe0102400, 0xf004fb05, 0x1000f8d9, 0xeb014632, 0xfb170340, 0xeb0af004, 
+    0xeb0b0140, 0xf0220040, 0x1c64fa15, 0x4544b224, 0xf8d9dbec, 0xac031000, 0x8100e9cd, 0x000fe894, 
+    0xff5ef7ff, 0xe92de7cf, 0xb0854fff, 0x90032000, 0x28019805, 0x9807d002, 0x2002b158, 0x92a4f8df, 
+    0x26004683, 0xf8d94634, 0x88070000, 0x0857ea4f, 0x2008e04b, 0xfb07e7f2, 0x48a7fa04, 0x900249a5, 
+    0xeb019813, 0xb970058a, 0x46394628, 0xfb92f023, 0x0000f8d9, 0x46424629, 0x3080f9b0, 0xeb009812, 
+    0xf0220046, 0xf8d9fb56, 0x4b9c0000, 0x78814a9c, 0x0094f8d0, 0x0100e9cd, 0x46289903, 0xfcaef022, 
+    0x46424997, 0x0028f851, 0x60084994, 0xf8d94629, 0xf9b00000, 0x48923084, 0xfb4cf022, 0x0000f8d9, 
+    0x99024642, 0x3084f9b0, 0xf022488c, 0x4988fb43, 0x4628b23a, 0xeb016809, 0x9902034a, 0xf9aaf022, 
+    0xeb061c64, 0xb2060008, 0x455cb224, 0x4880dbb3, 0x6801ac05, 0xb100e9cd, 0x000fe894, 0xfef0f7ff, 
+    0xe761b009, 0x47f0e92d, 0x00d24c76, 0x4f77b086, 0x0541ea42, 0x46384305, 0xf4456824, 0xf8dd7180, 
+    0x8824a038, 0x435c0064, 0xf884fa0f, 0xfb33f022, 0xf2402400, 0x027e1900, 0x1c64e002, 0xd20642b4, 
+    0x46492208, 0xf0224638, 0x2800fb3d, 0xf445d1f5, 0x46387100, 0xfb1ff022, 0x4a642000, 0x90052101, 
+    0x46531d12, 0xe9cd9004, 0x46410102, 0x90019000, 0xf0002001, 0xb006fb15, 0x87f0e8bd, 0x4ff8e92d, 
+    0x4b584698, 0xe9dd4e5a, 0x681ba90a, 0x6833881d, 0x46439300, 0xf7ff086f, 0x2400ffb5, 0xb22e46b3, 
+    0xfb17e010, 0xf8dbf004, 0xeb091000, 0xeb0a0340, 0xfb050240, 0xeb01f004, 0x46310040, 0xf97cf022, 
+    0xb2241c64, 0xdbec4544, 0x8ff8e8bd, 0x4fffe92d, 0x4615b085, 0x28012200, 0xd0159203, 0x2202b1b5, 
+    0xa100f8df, 0x9b029202, 0x2000f8da, 0x4a408816, 0x68120874, 0x462a9200, 0xff84f7ff, 0x0800f04f, 
+    0xb0f0f8df, 0xe05c4645, 0xe7e92201, 0xe7e72208, 0xfb064937, 0xf8dff005, 0x680990e0, 0x0780eb0b, 
+    0xeb01464b, 0x463a0040, 0xf022b231, 0xf8daf945, 0x46220000, 0xf9b04932, 0x46383088, 0xfa79f022, 
+    0x0000f8da, 0x492d4622, 0x3088f9b0, 0xf0224648, 0x4a2afa70, 0x468c492a, 0xf8416810, 0x20000024, 
+    0xf8426010, 0x20010024, 0x1a31e00b, 0x3020f85c, 0x3021f84c, 0x3020f852, 0x1c40425b, 0xf842b200, 
+    0x42a03021, 0xf8dadbf1, 0x46d10000, 0x463a9b03, 0xf8d07881, 0xe9cd0094, 0x49180100, 0xf0224818, 
+    0x9812fe97, 0xfb14b188, 0x4638f105, 0xeb0b4622, 0xf0220181, 0x1c6df9ef, 0x0004eb08, 0xf880fa0f, 
+    0x9802b22d, 0xdba34285, 0xf8d9e71a, 0x46220000, 0x308cf9b0, 0xeb009808, 0x46380148, 0xfa3af022, 
+    0x0000e7e9, 0x00040598, 0x00040600, 0xf1000100, 0x000401dc, 0x00049908, 0x0004b908, 0x0004c908, 
+    0x0004c108, 0x2801b570, 0xdc01460d, 0xe0004956, 0x24004956, 0x1640eb01, 0x42408828, 0xeb06b281, 
+    0xf0220044, 0x1c64fa3e, 0x1cadb224, 0xdbf32c10, 0xb570bd70, 0x460e2801, 0x494bdc01, 0x494be000, 
+    0xeb012400, 0xeb051540, 0xf0220044, 0xb200fa27, 0xf0232109, 0x4240f983, 0x0014f826, 0xb2241c64, 
+    0xdbf02c10, 0xb570bd70, 0x21204d41, 0xf0236828, 0x2400fa21, 0xb2606829, 0xffc4f7ff, 0xb2241c64, 
+    0xdbf72c04, 0xe92dbd70, 0x460741fc, 0x4e384839, 0x71fff64f, 0x88006800, 0x01c0ea01, 0xf0236830, 
+    0x2500fa09, 0x2f012400, 0xb1acd014, 0x68312002, 0x46222300, 0x0100e9cd, 0x46384629, 0xfd90f7ff, 
+    0xb2641c64, 0xdbee2c04, 0xb26d1c6d, 0xdbe92d04, 0x81fce8bd, 0xe7ea2001, 0xe7e82008, 0xb5102000, 
+    0xffd1f7ff, 0xf7ff2001, 0xe8bdffce, 0xe7ba4010, 0x4a20b57c, 0x68124d1e, 0x8814682b, 0x46162200, 
+    0xf823e007, 0x1c526012, 0xf823b212, 0x1c520012, 0x42a2b212, 0x2601dbf5, 0x29038018, 0x2400d00e, 
+    0x23006828, 0xb261461a, 0x6000e9cd, 0xf7ff2001, 0x1c64fd57, 0x2c04b224, 0xbd7cdbf2, 0x20014c0e, 
+    0x6300e9cd, 0x461a2300, 0x1000f994, 0xfd48f7ff, 0x23006828, 0xe9cd461a, 0xf9946000, 0x20011001, 
+    0xfd3ef7ff, 0x0000bd7c, 0xf20304a2, 0xf20305a4, 0x000401dc, 0x00040598, 0x00040520, 0x4fffe92d, 
+    0x48b8b087, 0xb2e0f8df, 0x4fb8460d, 0x71fff64f, 0xf5009003, 0x90026080, 0x6a80f50b, 0xf50748b4, 
+    0x90066980, 0x90042000, 0x48b24690, 0x88006800, 0x08469005, 0x0180ea01, 0xf0239806, 0x48aef97b, 
+    0xf0239905, 0x4cacf967, 0x3080f44f, 0x20006020, 0x0280eb04, 0x1010f935, 0x02891c40, 0x28106051, 
+    0x4da4dbf6, 0x68289b02, 0xf8d07881, 0xe9cd0094, 0x48a10100, 0x2103e9dd, 0xfa80f022, 0x9905489e, 
+    0xf948f023, 0x3080f44f, 0x20006020, 0x0280eb04, 0x1010f938, 0x02891c40, 0x28106051, 0x4895dbf6, 
+    0x465a4653, 0x78816800, 0x0094f8d0, 0x0100e9cd, 0x99044891, 0xfa62f022, 0x1c702400, 0xe02a9000, 
+    0xf85b9803, 0xf85a2024, 0xf8501024, 0x469c3024, 0xf003fb02, 0xf8539b02, 0xfb023024, 0x4352f503, 
+    0x0003fb01, 0x581cfb01, 0x2101fb01, 0xd009120d, 0xf0234629, 0xf847f86d, 0x46290024, 0xf0234640, 
+    0xe004f867, 0x1000f240, 0x0024f847, 0xf8492000, 0x98000024, 0x42841c64, 0x980adbd2, 0x9814e0da, 
+    0xe0cf1e40, 0x78004875, 0xd00d2805, 0x0f01f1bb, 0x9807d020, 0xeb014972, 0x49722540, 0x2440eb01, 
+    0x90022001, 0xe06c2000, 0xf1bb4d6f, 0x4c6f0f01, 0xd0034658, 0x0f00f1ba, 0x2002d00a, 0x46039500, 
+    0xe9cd4652, 0x99074001, 0xf7ff4658, 0xe7e9fdc7, 0xe7f32008, 0x49669807, 0x2540eb01, 0xe7dd4965, 
+    0xf006fb18, 0xb2006839, 0x2010f935, 0x4a624351, 0x1020f842, 0x1026f857, 0x2010f934, 0x4a5f4351, 
+    0x1020f842, 0xe01f2101, 0xf857180a, 0xf9353021, 0xf934c012, 0xfb03e012, 0xf859f30c, 0xfb0cc021, 
+    0x4b553c1e, 0xc022f843, 0x3021f857, 0xc012f934, 0xe012f935, 0xf30cfb03, 0xc021f859, 0xfb0c1c49, 
+    0x4b4e3c0e, 0xc022f843, 0xdbdd42b1, 0x78094943, 0xd1132905, 0xc120f8df, 0xf8df2100, 0xe00be120, 
+    0xf85c180a, 0x121b3022, 0x3012f825, 0x3022f85e, 0x1c49121b, 0x3012f824, 0xdbf142b1, 0x0001f108, 
+    0x9902b240, 0x42884680, 0x4834dbaa, 0x28057800, 0x4b3ad00a, 0x4a382400, 0xf8426818, 0x601c0026, 
+    0xf8431c70, 0xe0144026, 0x1500e9cd, 0x23009402, 0x46529907, 0xf7ff4658, 0xe031fc79, 0xf8521a09, 
+    0xf8425021, 0xf8535020, 0x42491021, 0x1020f843, 0x99051c40, 0xdbf14288, 0x4a1f4d1e, 0x68289b04, 
+    0xf8d07881, 0xe9cd0094, 0x49240100, 0xf0224822, 0x6828fc5f, 0x99064632, 0x308cf9b0, 0xf0224816, 
+    0x9806f819, 0xeb004631, 0xf0230046, 0x9806f843, 0xe9cd2300, 0x99070400, 0x4658461a, 0xfc73f7ff, 
+    0x0001f1aa, 0xea5fb240, 0xf57f0a00, 0xf10baf2b, 0xb2400001, 0x46832801, 0xaf21f77f, 0xe8bdb00b, 
+    0x00008ff0, 0x00042908, 0x00041908, 0x00042108, 0x00043108, 0x00040598, 0x00049908, 0x00040ed8, 
+    0x00044908, 0x00045108, 0x00048908, 0x00049108, 0x00043908, 0x00044108, 0x0004c108, 0x0004c908, 
+    0x5ff0e92d, 0x461f4d53, 0x46902301, 0xb030f8dd, 0xf8dd460c, 0x2102a038, 0x9028f8dd, 0x4628461a, 
+    0xf809f022, 0x20042100, 0xffdcf000, 0x2c404e4a, 0x7100f643, 0x0660dd08, 0x2310d406, 0x22084630, 
+    0xffe2f021, 0xe01f2310, 0xdd012c1f, 0xd5f406a0, 0xdd082c0f, 0xd40606e0, 0x46302304, 0xf0212208, 
+    0x2304ffd3, 0x2c07e010, 0x0720dd08, 0x2302d406, 0x22084630, 0xffc8f021, 0xe0052302, 0x46302301, 
+    0xf0212208, 0x2301ffc1, 0x22004630, 0xf021213f, 0x4e31ffbb, 0x21042202, 0x1d36464b, 0xf0214630, 
+    0x2201ffb3, 0x2102465b, 0xf0214630, 0x2200ffad, 0x21014653, 0xf0214630, 0x4e27ffa7, 0x9b0b2202, 
+    0x36142104, 0xf0214630, 0x9b0dff9f, 0x21022201, 0xf0214630, 0x9b0fff99, 0x21012200, 0xf0214630, 
+    0x481dff93, 0x46232200, 0x71fff64f, 0xf0211f00, 0x4819ff8b, 0x30084641, 0xff7df021, 0x46391d30, 
+    0xff79f021, 0x22002301, 0xf04f4619, 0xf0214070, 0x04b4ff7b, 0x3e084e10, 0x4620e00e, 0xff60f000, 
+    0xdc091e04, 0x46204c0d, 0xff68f021, 0x5180f440, 0xf0214620, 0xe004ff66, 0xf0214630, 0x2801ff59, 
+    0x4628d1eb, 0x5ff0e8bd, 0x22012300, 0xf0212102, 0x0000bf72, 0xf203529a, 0xf000000c, 0xf203517c, 
+    0x220048a5, 0x31fff240, 0xf021b510, 0xb200ff5b, 0xb5f8bd10, 0x20004605, 0xf7ff9000, 0x4c9ffff1, 
+    0x80204e9f, 0x0000f44f, 0xe0099000, 0x46322108, 0xf0004668, 0x2801ffbc, 0xf7ffd005, 0x8020ffe1, 
+    0x42a88820, 0xbdf8dcf2, 0x5fffe92d, 0x9254f8df, 0xf8df4607, 0x2202b254, 0x450ee9dd, 0x824cf8df, 
+    0xf8992600, 0xf8df0000, 0xf000a248, 0xf89b0101, 0xea020000, 0xf8980040, 0x43012000, 0xea002004, 
+    0x43010082, 0x0000f89a, 0xea022208, 0x430100c0, 0x22104888, 0xea027800, 0x43011000, 0x22204886, 
+    0xea027800, 0x43011040, 0x78004884, 0xea410780, 0x48796110, 0xf0213808, 0x4881feee, 0x780001f9, 
+    0x1100ea41, 0x38144874, 0xfee5f021, 0x9801497d, 0x01c07809, 0x1101ea40, 0x3810486f, 0xfedbf021, 
+    0x98024979, 0x01c07809, 0x1101ea40, 0x380c486a, 0xfed1f021, 0x1f004868, 0x210fb39f, 0xfecbf021, 
+    0xf8984f65, 0x4b640000, 0x28013708, 0xf899d02c, 0x28010000, 0xf89bd06e, 0x28010000, 0xf89ad06a, 
+    0x28010000, 0x4621d066, 0x1d00485b, 0xfeb3f021, 0x46382300, 0x21062201, 0xfeb6f021, 0x46382301, 
+    0x46192200, 0xfeb0f021, 0x28009810, 0x4852d107, 0x21042202, 0xf0213010, 0x2800feb5, 0xe8bdd067, 
+    0xe7ff9fff, 0xe7c92100, 0x0e214858, 0x2105ea41, 0xe000f890, 0xea400a20, 0xf1be6005, 0xd1100f01, 
+    0x6200f3c5, 0xf3c500d6, 0xea462200, 0xf0010682, 0x18920201, 0x0602ea46, 0x0201f000, 0x0602ea46, 
+    0xf004b2f6, 0xf40008ff, 0xea48407f, 0xea4f0800, 0xea404014, 0xf4004005, 0xea48007f, 0xf0010800, 
+    0x4943407f, 0x0800ea48, 0x2006ea4f, 0xea407809, 0x49401081, 0xea407809, 0x493f1001, 0xea407809, 
+    0x483e0181, 0xea417800, 0x46180100, 0xfe53f021, 0xe7994641, 0x88014829, 0xf0214618, 0x4826fe4c, 
+    0x1d004621, 0xfe47f021, 0xe7922301, 0xf0002002, 0x2801fdf7, 0x4c22d00b, 0xf0214620, 0xb004fe3f, 
+    0x7100f440, 0xe8bd4620, 0xf0215ff0, 0x2200be3a, 0x21014638, 0xfe46f021, 0xd1e72800, 0xb5fee78f, 
+    0x23012500, 0x4629462a, 0x95004628, 0xffccf003, 0x24004e11, 0x46233610, 0x46302203, 0xf0212108, 
+    0x2301fe23, 0x22024630, 0xf0212104, 0x2100fe1d, 0x460a9502, 0xe9cd4608, 0xf7ff1100, 0x1c64fee5, 
+    0x2c02b264, 0xb003dbe7, 0x23004630, 0xe8bd2202, 0x210440f0, 0xbe08f021, 0xf0008014, 0x00040226, 
+    0xf203517a, 0x00040223, 0x00040221, 0x0004021c, 0x0004021f, 0x00040203, 0x00040201, 0x000401fe, 
+    0x00040209, 0x00040207, 0x00040205, 0x000402b2, 0x00040214, 0x00040215, 0x00040216, 0x00040217, 
+    0x41f0e92d, 0x4d172301, 0x4607220a, 0x4628029c, 0xf0214621, 0x00a6fdf0, 0x46304639, 0xfdc2f000, 
+    0x46212300, 0x4628220a, 0xfde5f021, 0x46304639, 0xfdb8f000, 0x22012300, 0x1f282102, 0x41f0e8bd, 
+    0xbdd9f021, 0xb1404a08, 0x0041ea41, 0x00c1ea40, 0x6170f440, 0xf0214610, 0x0048bdb4, 0x0081ea40, 
+    0x0000e7f4, 0xf20350f6, 0xf20352ac, 0x41f0e92d, 0x28014afe, 0xd0094607, 0x2f0249fd, 0x880e48fd, 
+    0xf6478805, 0xd0092012, 0xd0212f03, 0x46102100, 0xfd97f021, 0x46352600, 0xe0234634, 0x880c49f6, 
+    0x4285b916, 0x4605d200, 0x4006eb05, 0xdc0142a0, 0xb2841e40, 0x4080f240, 0xd2014284, 0xe0044604, 
+    0x6f00f5b4, 0xf240d301, 0xf24074ff, 0xe0061104, 0xb9162400, 0xd2004285, 0xf2404605, 0x46101100, 
+    0xfd6ff021, 0x463148e1, 0xf0211d00, 0x48dffd6a, 0x1d804629, 0xfd65f021, 0x462148dc, 0xf0213008, 
+    0x48dafd60, 0xb10f3822, 0xe0002301, 0x22012300, 0xf0212102, 0x48d9fd70, 0xe8bd7007, 0x48d881f0, 
+    0xf990b510, 0x48d71000, 0xd0052903, 0xd0122904, 0xd0082905, 0xe0152000, 0x21202205, 0xfd69f021, 
+    0x48d1b180, 0x2204e005, 0xf0212110, 0xb148fd62, 0x780048ce, 0x2203e006, 0xf0212108, 0xb108fd5a, 
+    0xe7f648cb, 0x4010e8bd, 0x48c0e780, 0x2112f240, 0x41f0e92d, 0xf021381c, 0x48bcfd24, 0x0115f647, 
+    0xf021381a, 0x48c3fd1e, 0x2173f240, 0xfd19f021, 0x210248b6, 0xf0213818, 0x48b4fd14, 0x0400f243, 
+    0x38144621, 0xfd0df021, 0x212048b0, 0xf0213810, 0x48b9fd08, 0xf0212100, 0x48b7fd04, 0x11fef240, 
+    0xf0211c80, 0x48b4fcfe, 0x220c2300, 0x38164621, 0xfd11f021, 0x4cb148aa, 0x78004db1, 0xd07d2803, 
+    0x70a82001, 0x7020203c, 0x02017820, 0xf5a11e40, 0x43017180, 0xb289489d, 0xf021380e, 0x489bfce2, 
+    0x3103f240, 0xf021380c, 0x7820fcdc, 0xb2811e40, 0x1f804896, 0xfcd5f021, 0x1e407820, 0x4893b281, 
+    0xf0213808, 0x489bfcce, 0x7180f64f, 0xf0213808, 0x4898fcc8, 0x6170f64f, 0xf0211f80, 0x488bfcc2, 
+    0x38222110, 0xfcbdf021, 0xf64a4888, 0x3820210a, 0xfcb7f021, 0x22094c93, 0xf2404e93, 0x78202100, 
+    0x1300f340, 0x1c5b4630, 0xfcc5f021, 0x22047820, 0xf3402110, 0x488c1300, 0x300c1c5b, 0xfcbbf021, 
+    0x22087820, 0xf3400151, 0x46301300, 0xf0211c5b, 0x2300fcb2, 0x22044630, 0xf0212110, 0x2300fcac, 
+    0x21014630, 0xf021461a, 0x2300fca6, 0x22014630, 0xf0212102, 0x2300fca0, 0x22024630, 0xf0212104, 
+    0x2300fc9a, 0x22034630, 0xf0212108, 0x7820fc94, 0x00c0f3c0, 0xfd6df002, 0xe00078a8, 0x2128e112, 
+    0x40c12214, 0x1db040c2, 0x2102ea41, 0xfc69f021, 0x216878a8, 0x40c12254, 0x486b40c2, 0x2102ea41, 
+    0xf0213008, 0x4859fc5e, 0x0120f244, 0xf021381e, 0x4865fc58, 0x1511f241, 0x30104629, 0xfc51f021, 
+    0x21004861, 0xf0213012, 0x7820fc4c, 0x0040f3c0, 0xfd91f002, 0x210c4857, 0xf02130a4, 0x4e55fc42, 
+    0x7400f641, 0x46212303, 0x22081cb6, 0xf0214630, 0x2304fc52, 0x22004630, 0xf021211f, 0x4e4dfc4c, 
+    0x22082305, 0x36a04621, 0xf0214630, 0x230afc44, 0x22004630, 0xf021211f, 0x1cb6fc3e, 0x46302301, 
+    0x21702204, 0xfc37f021, 0x46302300, 0x461a2107, 0xfc31f021, 0x21004844, 0xf02138a4, 0x4842fc12, 
+    0x38a22100, 0xfc0df021, 0x2102483f, 0xf02138b6, 0x483dfc08, 0x38782100, 0xfc03f021, 0xfeaff7ff, 
+    0x211b482a, 0xf0213844, 0x4f39fbfc, 0x4680f240, 0x22104936, 0x46384633, 0xfbf6f021, 0x46332200, 
+    0x71fff64f, 0xf0214638, 0x4932fbef, 0xf0211d38, 0x4e2dfbe2, 0x220e2300, 0x0100f24c, 0x46303616, 
+    0xfbf9f021, 0xf6432302, 0x22087100, 0xf0214630, 0x2300fbf2, 0x22064630, 0xf02121c0, 0x2303fbec, 
+    0x22004630, 0xf021213f, 0x4821fbe6, 0x22182302, 0xf04f383c, 0xf02161e0, 0x4e16fbc7, 0x461a2308, 
+    0x36a64621, 0xf0214630, 0x2302fbd6, 0x22044630, 0xf0212130, 0x2307fbd0, 0x22004630, 0xf021210f, 
+    0x4811fbca, 0x30142109, 0x0000e026, 0xf2035114, 0x0004027c, 0x0004027e, 0x00040280, 0x0004027b, 
+    0x00040242, 0xf38f007c, 0x00040277, 0x000402ce, 0x000402cd, 0xf203050a, 0xf2030818, 0x0004027a, 
+    0x0004061c, 0x00040279, 0xf20352a0, 0xffff0000, 0xf1000040, 0x00080005, 0xfb83f021, 0xf24448fc, 
+    0xf021310f, 0x48fbfb7e, 0xf0214629, 0x4dfafb7a, 0x2218230e, 0x46280421, 0xfb76f021, 0x4628230e, 
+    0x02212210, 0xfb70f021, 0x4621230c, 0x46282208, 0xfb6af021, 0xe8bd4628, 0x230c41f0, 0x211f2200, 
+    0xbb62f021, 0x7020207c, 0x70a82000, 0xe92de66c, 0x48ec5ffc, 0x4ce92600, 0xf8df4637, 0x4aec83a4, 
+    0xf8df7800, 0xf3c093b0, 0x48e70180, 0x88006800, 0x48e60845, 0xb3007800, 0xf8897893, 0x4be63001, 
+    0x469a4ae6, 0xf7ff4693, 0xf8dffd7d, 0x20009388, 0x46029000, 0xf8994643, 0xb2410001, 0xf7ff2001, 
+    0x48dff845, 0xfb01f002, 0xf89949dd, 0xf8310001, 0x20011010, 0x1008f8a9, 0x7813e013, 0x3001f889, 
+    0x4ad94bd8, 0xf938e7dd, 0x1e0a1010, 0x4251da00, 0xdd0442b1, 0xd5000011, 0x46074251, 0x1c40b20e, 
+    0x2d80b200, 0x2180d901, 0x4629e000, 0xdcea4281, 0xb2381fbf, 0x1a289000, 0x1700f240, 0xf5a79001, 
+    0xb2067080, 0x46052000, 0x0026f844, 0x9800e016, 0x44284659, 0xf980fa0f, 0xf3c01b78, 0x46500245, 
+    0xfc5df020, 0xf85443c0, 0x07c02026, 0x0019f938, 0x4410d021, 0xb22d1c6d, 0x0026f844, 0x42a89801, 
+    0x1c7fdce5, 0xf5b7b23f, 0xdbd87fc0, 0xf06f2600, 0x46350804, 0x077ff06f, 0x0025f854, 0xfffef023, 
+    0xfe6af023, 0xf0244642, 0xf023f998, 0x287ffaab, 0x217fdb03, 0x1a10e002, 0x4601e7dc, 0xdc0042b9, 
+    0xb2494639, 0x1025f844, 0xfb011c6d, 0xb22d6600, 0xdbe12d80, 0x2500489f, 0x4ea46106, 0x00c5eb04, 
+    0xf8346841, 0xf3610035, 0xb281201f, 0x0045eb06, 0xfaa7f021, 0xb22d1c6d, 0xdbef2d40, 0x9ffce8bd, 
+    0x47f0e92d, 0xf240489a, 0xf8df1890, 0x4e919268, 0x28007800, 0x4892d16b, 0xf0026934, 0x4890fa66, 
+    0xf8307871, 0x81700011, 0xf0234620, 0x4992ffcf, 0xf0234607, 0xf023ffdf, 0x4c90fe1f, 0x46232200, 
+    0xfb24f023, 0x050bf06f, 0xf024462a, 0xf023f946, 0x1040fa59, 0x210180b0, 0xf0244638, 0xf023f96c, 
+    0x2200fe0b, 0xf0234623, 0x462afb11, 0xf935f024, 0xfa48f023, 0x80f01040, 0xfc5af002, 0xd2064540, 
+    0x0000f8d9, 0xd8022811, 0xf0024640, 0x4f7cfc4c, 0x462c2500, 0x4620703d, 0xf837f003, 0x428c7871, 
+    0x4605d100, 0x42887839, 0xb2c1dd00, 0x1c647039, 0x2c04b2e4, 0x4964d3ef, 0x22001c6d, 0x8e496809, 
+    0x0065eba1, 0x1ec0b200, 0xeb0017c1, 0xf0216191, 0x1a40013f, 0x4865b283, 0x380a213f, 0xfa4bf021, 
+    0x23034868, 0xf247220c, 0xf0210100, 0x88f0fa44, 0xb2814240, 0x380e485d, 0xfa23f021, 0x424088b0, 
+    0x485ab281, 0xf021380c, 0x88b0fa1c, 0xb2814240, 0x30904856, 0xfa15f021, 0x7800485b, 0xf9b6b360, 
+    0xeb000004, 0xf3c00040, 0xf002004f, 0x484ffbfc, 0xf021381c, 0x4540fa03, 0xf8d9d206, 0x28110000, 
+    0x4640d802, 0xfbeff002, 0x2300484e, 0xf240220a, 0x380a4100, 0xfa0ff021, 0x20082101, 0xfc06f002, 
+    0xf0022000, 0xf002fc54, 0x4848fc39, 0x28027800, 0x2803d005, 0xe009d003, 0x70fff647, 0x4841e7d5, 
+    0x22012300, 0x30142102, 0xf9f5f021, 0xe8bd7870, 0xf24f87f0, 0xea401060, 0xb2810041, 0xb5104833, 
+    0xf0213810, 0x4831f9ce, 0x4100f240, 0xf0211e80, 0x2207f9c8, 0xe8bd2101, 0x20004010, 0xbb99f002, 
+    0x47fce92d, 0x807cf8df, 0x4e312301, 0x4d212200, 0xf8984f30, 0xe9cd0000, 0xf3c07600, 0x78280980, 
+    0x4618b241, 0xfe9af7fe, 0x24004817, 0xf8b16801, 0xf8b10074, 0xe00a2076, 0x1010f837, 0xf301fb11, 
+    0x1010f836, 0xb2801c40, 0x3101fb11, 0x4282440c, 0x4821d2f2, 0xf8407829, 0x48204021, 0xf8c3f002, 
+    0x7828491f, 0x2020f851, 0xd43b1b11, 0xe03a460b, 0xf2030816, 0xf20352aa, 0xf1000010, 0x00043908, 
+    0x00044108, 0x00040279, 0x00040598, 0x00040502, 0x00040518, 0x0004061c, 0x8365f253, 0x7425eef5, 
+    0x00040540, 0xaf77a42e, 0xca4fa6c1, 0xf2030510, 0x00040ed8, 0x000401f0, 0x40e00000, 0x40220000, 
+    0x00040283, 0xf2035100, 0x00040eda, 0x00040277, 0x00049108, 0x00048908, 0x00041248, 0x000413e8, 
+    0x00041238, 0x4f5e424b, 0x24004e5e, 0x0fa2ebb3, 0x2900db0d, 0x4249da00, 0x0f62ebb1, 0xf857da05, 
+    0xf64b1020, 0x429112f6, 0x5434d90f, 0x2900e00d, 0x4249da00, 0x0fe2ebb1, 0xf857db05, 0xf24a2020, 
+    0x428a51bd, 0x2101d201, 0x484f5431, 0xb3207800, 0x484e7831, 0x7871b1e1, 0x78b1b1d1, 0x78f1b1c1, 
+    0xf898b1b1, 0x07c91000, 0x4949d010, 0x29047809, 0x230fd00a, 0x211f2200, 0xf92df021, 0x46494845, 
+    0xf7ff7800, 0xe008fb4f, 0xe7f3231f, 0xe7f12300, 0x211f2300, 0xf021461a, 0x7828f91e, 0xb2c01c40, 
+    0x28047028, 0x702cd300, 0x87fce8bd, 0x41fce92d, 0x24004d39, 0xf8df4e39, 0x230180e8, 0x46182200, 
+    0x6500e9cd, 0xf7feb261, 0xf8d8fdd9, 0x21002000, 0x0074f8b2, 0x3076f8b2, 0xf836e00a, 0xfb122010, 
+    0xf835f702, 0x1c402010, 0xfb12b280, 0x44117202, 0xd2f24283, 0xf840482b, 0x482b1024, 0x1024f840, 
+    0xb2e41c64, 0xd3d82c04, 0x81fce8bd, 0xb5704827, 0xf6414e23, 0x780075ff, 0x08411c40, 0x79c26830, 
+    0x441a7943, 0x79007983, 0x44104418, 0x5000f5c0, 0x481f1a44, 0x46292200, 0xf8dbf021, 0x7c516832, 
+    0x44198bd3, 0x1b004408, 0x5000f500, 0x78d0b201, 0xf3f0fb91, 0x1113fb00, 0x1a40b179, 0xb2007e11, 
+    0x1a401a20, 0xf5c04629, 0xb2835000, 0xe8bd4810, 0x22004070, 0xf0213096, 0x2000b8ae, 0x0000e7ee, 
+    0x000413e8, 0x00040628, 0x00040261, 0xf20352a0, 0x00040242, 0x00040502, 0x00049108, 0x00048908, 
+    0x00040598, 0x00041238, 0x00041248, 0x00040283, 0xf203504a, 0x460db570, 0xeb014929, 0x21001000, 
+    0xf0214604, 0x2001f868, 0x0185eb00, 0xe8bd4620, 0xf0214070, 0x4922b860, 0x1000eb01, 0xf0212102, 
+    0x491fb85a, 0xeb01b510, 0xf0211000, 0xf3c0f851, 0xbd100040, 0x310c491a, 0x1000eb01, 0xb848f021, 
+    0x4604b510, 0xd0091c40, 0xf7ff4620, 0xb118fff3, 0xf7ff4620, 0xb108ffe6, 0xbd102000, 0xbd102001, 
+    0x41f0e92d, 0x480e4605, 0x460f4616, 0x1405eb00, 0x46202102, 0xf82ff021, 0x46394809, 0xeb003008, 
+    0xf0211005, 0x2100f828, 0xf0214620, 0x2001f824, 0x0186eb00, 0xe8bd4620, 0xf02141f0, 0x0000b81c, 
+    0xf0008100, 0xd0052801, 0xd0032802, 0xd0032804, 0xd0032805, 0x47702000, 0x47702002, 0x47702001, 
+    0x47701e40, 0xe0004088, 0x28001e40, 0x4770d1fc, 0x41f0e92d, 0x460c4e51, 0x8140f8df, 0x1d374605, 
+    0x080cf108, 0x2201e00d, 0x21024630, 0xf80af021, 0xd00e2801, 0x46382200, 0xf0212101, 0x2801f803, 
+    0x4640d007, 0xffe4f020, 0x42a01a28, 0xe8bdd3eb, 0x4c4381f0, 0xf0204620, 0xf440ffe1, 0x46206180, 
+    0x41f0e8bd, 0xbfddf020, 0x47f0e92d, 0x460f4614, 0x46994605, 0xf0204618, 0xf242ffd1, 0xb1387610, 
+    0xd02f2c01, 0x44282000, 0x4648b281, 0xffc9f020, 0x23014d34, 0x21802207, 0xf0204628, 0xf04fffc5, 
+    0x46286880, 0x46412301, 0xf020221a, 0x4648ffbd, 0xffb4f020, 0xd1fa2800, 0x46282301, 0x21802207, 
+    0xffb2f020, 0x46412301, 0x4628221a, 0xffacf020, 0xd0002c01, 0x19f02600, 0x4648b281, 0x47f0e8bd, 
+    0xbf9ff020, 0xe7ce4630, 0x41f0e92d, 0x4615461c, 0x4607460e, 0xf7ff2000, 0x1b04ff3d, 0x2000e010, 
+    0xff38f7ff, 0x28001b00, 0x4c15dc0a, 0xf0204620, 0xf440ff85, 0x46207100, 0x41f0e8bd, 0xbf81f020, 
+    0xf0204638, 0x4030ff7b, 0xd1e842a8, 0xb570e78f, 0x68004603, 0x4615460c, 0x28001e40, 0xdc0b6018, 
+    0xf0204610, 0x2101ff6b, 0x430840a1, 0x4628b281, 0xff67f020, 0xbd702001, 0xbd702000, 0xf0008120, 
+    0xf203517e, 0xf0001000, 0xe28fc04d, 0xe12fff1c, 0x2101e7fe, 0xd2042820, 0x23014081, 0x4853b242, 
+    0x3820e004, 0x4081b242, 0x23014851, 0xbf4cf020, 0xeb024a50, 0xf0201000, 0x2101bf3e, 0xd2052820, 
+    0xb2424081, 0x23004849, 0xe0053808, 0xb2423820, 0x48474081, 0x38082300, 0xbf36f020, 0x28202101, 
+    0x4081d205, 0x4841b242, 0x38082301, 0x3820e005, 0x4081b242, 0x2301483e, 0xf0203808, 0x2101bf25, 
+    0xd2042820, 0xb2424081, 0x301c4838, 0x3820e004, 0x4081b242, 0x300c4836, 0xbf24f020, 0x41f0e92d, 
+    0x4934460d, 0x4613461f, 0x9e063908, 0x1400eb01, 0x46202204, 0xf0202130, 0x2203ff07, 0x21084620, 
+    0xf020462b, 0x2202ff01, 0x21044620, 0xf020463b, 0x4620fefb, 0xe8bd4633, 0x220041f0, 0xf0202103, 
+    0xb570bef3, 0xe8bdb118, 0xf0204070, 0x4c21bee1, 0x1f244d21, 0xf0204620, 0x3410fedb, 0xd9f942ac, 
+    0xe92dbd70, 0x240141f0, 0xd20e2820, 0xb2424e17, 0x36284084, 0x23014615, 0x46304621, 0xfed4f020, 
+    0x46212301, 0x462a1d37, 0x3820e00e, 0xb2424e10, 0x36184084, 0x23014615, 0x46304621, 0xfec4f020, 
+    0x46212301, 0x462a1d37, 0xf0204638, 0x2300febd, 0x462a4621, 0xf0204630, 0x4621feb7, 0x4638462a, 
+    0x41f0e8bd, 0xf0202300, 0x0000beaf, 0xf0001008, 0xf0001508, 0xf0001108, 0xf00013f4, 0xf04fb510, 
+    0x48ff34ff, 0xf0204621, 0x48fefe96, 0xf0204621, 0x48fbfe92, 0x30084621, 0xfe8df020, 0x462148f9, 
+    0xf0203008, 0x49f8fe88, 0xf02048f8, 0x48f7fe84, 0x301049f7, 0xfe7ff020, 0x49f648f4, 0xf0203020, 
+    0x48f2fe7a, 0x303049f4, 0xfe75f020, 0x49f348ef, 0xf0203040, 0x48edfe70, 0x305049f1, 0xfe6bf020, 
+    0x49f048ea, 0xf0203060, 0x48e8fe66, 0x307049ee, 0xfe61f020, 0x49ed48e5, 0xf0203080, 0x48e3fe5c, 
+    0x309049eb, 0xfe57f020, 0x49ea48e0, 0xf02030a0, 0x48defe52, 0x30b049e8, 0xfe4df020, 0x49e748db, 
+    0xf02030c0, 0x48d9fe48, 0x30d049e5, 0xfe43f020, 0x49e448d6, 0xf02030e0, 0x48d4fe3e, 0x30f049e2, 
+    0xfe39f020, 0x48e249e1, 0xfe35f020, 0x49e148e0, 0xf0203010, 0x48defe30, 0x302049df, 0xfe2bf020, 
+    0x49de48db, 0xf0203030, 0x48d9fe26, 0x304049dc, 0xfe21f020, 0x49db48d6, 0xf0203050, 0x48d4fe1c, 
+    0x306049d9, 0xfe17f020, 0x49d848d1, 0xf0203070, 0x48cffe12, 0x308049d4, 0xfe0df020, 0x49d248cc, 
+    0xf0203090, 0x48cafe08, 0x30a049d1, 0xfe03f020, 0x49d048c7, 0xf02030b0, 0x48c5fdfe, 0x30c049ce, 
+    0xfdf9f020, 0x49c848c2, 0xf02030d0, 0x48c0fdf4, 0x30e049ca, 0xfdeff020, 0x49c948bd, 0xf02030f0, 
+    0x49c8fdea, 0xf02048c8, 0x48c7fde6, 0x301049c7, 0xfde1f020, 0x49c648c4, 0xf0203020, 0x48c2fddc, 
+    0x303049c4, 0xfdd7f020, 0x49c348bf, 0xf0203040, 0x48bdfdd2, 0x305049c1, 0xfdcdf020, 0x49c048ba, 
+    0xf0203060, 0x48b8fdc8, 0x307049be, 0xfdc3f020, 0x49ad48b5, 0xf0203080, 0x48b3fdbe, 0x309049ba, 
+    0xfdb9f020, 0x49b948b0, 0xf02030a0, 0x48aefdb4, 0x30b049b7, 0xfdaff020, 0x49b648ab, 0xf02030c0, 
+    0x48a9fdaa, 0x30d049b4, 0xfda5f020, 0x499e48a6, 0xf02030e0, 0x48a4fda0, 0x4010e8bd, 0x30f0499a, 
+    0xbd99f020, 0xf7ffb57c, 0x2000fef9, 0xfea9f7ff, 0x2400b662, 0x22019400, 0x20064623, 0xf7ff4621, 
+    0x2006fe7d, 0xfe49f7ff, 0x94002300, 0x46192201, 0xf7ff2007, 0x2007fe73, 0xfe3ff7ff, 0x94002300, 
+    0x46192203, 0xf7ff2001, 0x2300fe69, 0x22039400, 0x20114619, 0xfe62f7ff, 0x94002300, 0x46192203, 
+    0xf7ff2012, 0x2001fe5b, 0xfe27f7ff, 0xf7ff2011, 0x2012fe24, 0xfe21f7ff, 0x94002300, 0x46192202, 
+    0xf7ff4610, 0x2002fe4b, 0xfe28f7ff, 0x94002300, 0x46192203, 0xf7ff201e, 0x201efe41, 0xfe0df7ff, 
+    0x94002300, 0x46192203, 0xf7ff201f, 0x201ffe37, 0xfe03f7ff, 0x94002201, 0x46112300, 0xf7ff201c, 
+    0x4e7efe2d, 0x21022301, 0x4630461a, 0xfd53f020, 0xf64f487a, 0x462975ff, 0xf020382a, 0x4877fd32, 
+    0x382c4629, 0xfd2df020, 0x46302300, 0x21042202, 0xfd41f020, 0x46294871, 0xf020380a, 0x486ffd22, 
+    0x380c4629, 0xfd1df020, 0xfa0cf005, 0xf0051e60, 0x2301f88b, 0x22004630, 0xf0204619, 0x2201fd2c, 
+    0x23009400, 0x20044611, 0xfdf8f7ff, 0xf7ff2004, 0x2300fdc4, 0x22039400, 0x20224619, 0xfdeef7ff, 
+    0xf7ff2022, 0x2300fdba, 0x22039400, 0x20214619, 0xfde4f7ff, 0xf7ff2021, 0x2300fdb0, 0x22019400, 
+    0x20254619, 0xfddaf7ff, 0xf7ff2025, 0x2300fda6, 0x22019400, 0x20264619, 0xfdd0f7ff, 0xf7ff2026, 
+    0x484ffd9c, 0x717ff647, 0xfcdbf020, 0x94002300, 0x46192201, 0xf7ff2024, 0x2024fdc1, 0xfd8df7ff, 
+    0x94002300, 0x46192201, 0xf7ff2009, 0x4844fdb7, 0x38164629, 0xfcc5f020, 0x46294841, 0xf0203814, 
+    0x483ffcc0, 0x0500f248, 0x381a4629, 0xfcb9f020, 0x4629483b, 0xf0203818, 0x2009fcb4, 0xfd6df7ff, 
+    0xf64f2300, 0x220170e0, 0x21079000, 0x46189001, 0xf8f8f01b, 0x94002201, 0x46102300, 0xe0612107, 
+    0xf0001000, 0xf0001500, 0x00004344, 0xf0001108, 0x000046c4, 0x00004708, 0x0000488c, 0x00004a00, 
+    0x00004c38, 0x00004c70, 0x00004dd4, 0x00004e20, 0x00004e58, 0x00004ff0, 0x0000505c, 0x0000517c, 
+    0x000051e8, 0x00005220, 0x00005258, 0x00005290, 0xf0001208, 0x000052c8, 0x0000530c, 0x00005350, 
+    0x00005368, 0x00005380, 0x000079b1, 0x000053b8, 0x000053f0, 0x00005564, 0x0000559c, 0x00005600, 
+    0x00005618, 0x0000565c, 0xf0001308, 0x00005694, 0x00005760, 0x0000584c, 0x00005884, 0x0000598c, 
+    0x00005b7c, 0x00005cd0, 0x00005d08, 0x00005d40, 0x00005d78, 0x00005ecc, 0x00005f04, 0xf2039046, 
+    0xf23c8094, 0xf01b9401, 0xf64ff88d, 0x900070f8, 0x90012300, 0x21072201, 0xf01b2002, 0xf249f883, 
+    0x9000002a, 0x90012300, 0x21072201, 0xf01b2003, 0xf244f879, 0x90001091, 0x90012300, 0x211e2201, 
+    0xf01b2004, 0x2201f86f, 0x23009400, 0x201a4611, 0xfd04f7ff, 0xf7ff201a, 0xf004fcd0, 0x2201fa6b, 
+    0x23009400, 0x202b4611, 0xfcf8f7ff, 0xf7ff202b, 0xe8bdfcc4, 0x4802407c, 0x31bbf64b, 0xbc01f020, 
+    0xf23c80ba, 0x46032200, 0x2107481e, 0xbbfcf020, 0x4c1cb510, 0x22042300, 0x21103cc0, 0xf0204620, 
+    0x2301fbf3, 0x22064620, 0xf0202140, 0x2300fbed, 0x22064620, 0xf0202140, 0x2301fbe7, 0x22044620, 
+    0x4010e8bd, 0xf0202110, 0xb510bbdf, 0x23004c0d, 0x3cc02205, 0x46202120, 0xfbd6f020, 0x46202301, 
+    0x21802207, 0xfbd0f020, 0x46202300, 0x21802207, 0xfbcaf020, 0x46202301, 0xe8bd2205, 0x21204010, 
+    0xbbc2f020, 0xf10008c0, 0xf04fb570, 0x46054671, 0xf6402200, 0x21010400, 0x46304603, 0xfbb4f020, 
+    0xd0172d01, 0x05264635, 0x221f4628, 0xf0204631, 0x2801fbb9, 0x1e64d00e, 0x2c00b224, 0x4c44dcf4, 
+    0xf0204620, 0xf440fb9b, 0x46204100, 0x4070e8bd, 0xbb97f020, 0x2200bd70, 0xf04f2101, 0xb5104071, 
+    0xfba0f020, 0xbd10b240, 0x4c3ab570, 0x22104615, 0xf44f460e, 0x4603017f, 0xf0204620, 0x2200fb85, 
+    0x21ff4633, 0xf0204620, 0x462bfb7f, 0xe8bd4620, 0x22084070, 0x7100f64f, 0xbb76f020, 0x4c2db570, 
+    0x460d2210, 0x341c492c, 0x46204603, 0xfb6cf020, 0x4620462b, 0x4070e8bd, 0xf64f2200, 0xf02071ff, 
+    0xb570bb63, 0x22044c23, 0x4603460d, 0x21f03418, 0xf0204620, 0x462bfb59, 0xe8bd4620, 0x22004070, 
+    0xf020210f, 0xe92dbb51, 0x4c1a41f0, 0x4615461f, 0x1d24460e, 0x220c4603, 0x0100f241, 0xf0204620, 
+    0x2208fb43, 0x46204633, 0xf0200151, 0x2204fb3d, 0x21f0462b, 0xf0204620, 0x463bfb37, 0xe8bd4620, 
+    0x220041f0, 0xf0202103, 0xb570bb2f, 0x461d4c09, 0x461321f0, 0x22043414, 0xf0204620, 0x462bfb25, 
+    0xe8bd4620, 0x22004070, 0xf020210f, 0x0000bb1d, 0xf203517c, 0xf1000004, 0xffff0000, 0x41f0e92d, 
+    0x460e1e52, 0xb2541e5b, 0x4603b25d, 0xf04f2218, 0x4ffd51f8, 0xf0204638, 0x2210fb07, 0xf44f4633, 
+    0x463811f8, 0xfb00f020, 0x46232208, 0x7100f641, 0xf0204638, 0x462bfaf9, 0xe8bd4638, 0x220041f0, 
+    0xf020211f, 0xe92dbaf1, 0xf44f4ff8, 0x46802780, 0x461d2000, 0xa028f8dd, 0x460e4614, 0x0110f243, 
+    0x46389000, 0xfacdf7f8, 0xf1041c70, 0xd0010001, 0xe011b188, 0x261ab108, 0x2100e00e, 0xf7f84638, 
+    0x2100faaf, 0xf7f84638, 0x2100faab, 0xf7f84638, 0xe8bdfaa7, 0x241a8ff8, 0x4971f04f, 0x46482300, 
+    0x21102204, 0xfac0f020, 0x461a2300, 0xb270b261, 0xffa4f7ff, 0x461a2300, 0x46184619, 0xff85f7ff, 
+    0x20012100, 0xff4df7ff, 0x464148cf, 0xf0203018, 0x48cdfaa2, 0x22002301, 0x30244619, 0xfaa4f020, 
+    0x1f0048c9, 0xfa94f020, 0x46384601, 0xfa78f7f8, 0xf02048c5, 0x4601fa8d, 0xf7f84638, 0x4641fa71, 
+    0xf7f84638, 0x4ec1fa6d, 0x2000f240, 0xf7ff7831, 0xf8dffa79, 0x4cbf82fc, 0x0000f898, 0xf994b948, 
+    0xb1152000, 0x4629980b, 0x2100e001, 0xf0014608, 0x2301fb31, 0x2211464f, 0x04594648, 0xfa74f020, 
+    0x46382301, 0x46192200, 0xfa6ef020, 0xb2c8f8df, 0x0000f44f, 0x4900f04f, 0xe0069000, 0x465a2101, 
+    0xf7ff4668, 0x2801fae4, 0x221fd006, 0x46384649, 0xfa68f020, 0xd0f12800, 0x0000f898, 0xf1bab970, 
+    0xd0040f00, 0x2000f994, 0x980b4629, 0xb12de004, 0xf9942100, 0x46082000, 0xfafcf001, 0x46382301, 
+    0x03d9220f, 0xfa40f020, 0xf2407831, 0xf7ff2000, 0xe76efa29, 0x43f8e92d, 0x2680f44f, 0x20004680, 
+    0x460d4614, 0x0120f243, 0x46309000, 0xfa19f7f8, 0xf1041c68, 0xd0010001, 0xe011b188, 0x251ab108, 
+    0x2100e00e, 0xf7f84630, 0x2100f9fb, 0xf7f84630, 0x2100f9f7, 0xf7f84630, 0xe8bdf9f3, 0x241a83f8, 
+    0x4771f04f, 0x46382300, 0x21102204, 0xfa0cf020, 0x46082100, 0xb26ab263, 0xfef0f7ff, 0x461a2300, 
+    0x46184619, 0xfed1f7ff, 0x20002101, 0xfe99f7ff, 0x46414875, 0xf0203018, 0x4873f9ee, 0x22002301, 
+    0x30244619, 0xf9f0f020, 0x1f00486f, 0xf9e0f020, 0x46304601, 0xf9c4f7f8, 0xf020486b, 0x4601f9d9, 
+    0xf7f84630, 0x4641f9bd, 0xf7f84630, 0x4c67f9b9, 0x2800f240, 0x78214640, 0xf9c4f7ff, 0x46382301, 
+    0x04592211, 0xf9d0f020, 0x46382301, 0x46192200, 0xf9caf020, 0xf44f4d60, 0x90000000, 0x02061ead, 
+    0x210fe006, 0x4668462a, 0xfa41f7ff, 0xd0062801, 0x4631221f, 0xf0204638, 0x2800f9c5, 0x2301d0f1, 
+    0x220f4638, 0xf02003d9, 0x7821f9af, 0xf7ff4640, 0xe792f999, 0x4fffe92d, 0x469bb081, 0x46162000, 
+    0x2980f44f, 0xe9dd460f, 0xf8dd540e, 0xf2438044, 0x90000130, 0xf7f84648, 0x1c78f984, 0x1c70d101, 
+    0x1c68d002, 0xe004d004, 0xd1021c68, 0xd0031c60, 0x1c60251a, 0xe010d010, 0x464c2100, 0xf7f84648, 
+    0x2100f95f, 0xf7f84620, 0x2100f95b, 0xf7f84620, 0xb005f957, 0x8ff0e8bd, 0xf04f241a, 0x23014a71, 
+    0x22044650, 0xf0202110, 0xb263f96f, 0xb271b26a, 0xf7ffb278, 0x2300fe53, 0x4619461a, 0xf7ff4618, 
+    0x9810fe34, 0xfa4fb241, 0xf7fff08b, 0x4826fdfa, 0x30189901, 0xf94ff020, 0x23014823, 0x46192200, 
+    0xf0203024, 0x4820f951, 0xf0201f00, 0x4601f941, 0x4648464c, 0xf924f7f8, 0xf020481b, 0x4601f939, 
+    0xf7f84620, 0x9901f91d, 0xf7f84620, 0x4d17f919, 0x2b00f240, 0x78294658, 0xf924f7ff, 0x4c154e14, 
+    0xb9587830, 0x2000f994, 0x0008ea5f, 0x4601d002, 0xe0019813, 0x46082100, 0xf9dcf001, 0x46572301, 
+    0x46502211, 0xf0200459, 0x2301f91f, 0x22004638, 0xf0204619, 0xf8dff919, 0xf44fa020, 0xf04f0000, 
+    0x90004900, 0x0000e011, 0xf100000c, 0x00040243, 0x00040502, 0x00040248, 0xf203517c, 0x46522100, 
+    0xf7ff4668, 0x2801f984, 0x221fd006, 0x46384649, 0xf908f020, 0xd0f12800, 0xb9787830, 0xb1209812, 
+    0x2000f994, 0x98134641, 0xf1b8e006, 0xd0050f00, 0xf9942100, 0x46082000, 0xf99cf001, 0x46382301, 
+    0x03d9220f, 0xf8e0f020, 0x46587829, 0xf8caf7ff, 0xe92de75f, 0xf44f47f0, 0x461e2480, 0x46894617, 
+    0xf2434680, 0x46200160, 0xf8bbf7f8, 0x4571f04f, 0x46282301, 0x21102204, 0xf8c6f020, 0xfa4fb27b, 
+    0x461af188, 0xf7ff4608, 0x2300fda9, 0x4619461a, 0xf7ff4618, 0xb271fd8a, 0xf089fa4f, 0xfd51f7ff, 
+    0x48c02300, 0x461a2101, 0xf8aef020, 0x382848bd, 0xf89ef020, 0x46204601, 0xf882f7f8, 0x382448b9, 
+    0xf896f020, 0x46204601, 0xf87af7f8, 0x46202100, 0xf876f7f8, 0x46282300, 0x10612211, 0xf894f020, 
+    0xe8bd4628, 0x230147f0, 0x46192200, 0xb88cf020, 0xb51048ad, 0x7800b086, 0x2000b188, 0x21019004, 
+    0x22099005, 0xe9cd460b, 0x200b1002, 0x90004611, 0xf2409001, 0xf7ff2000, 0xb006fecd, 0x4ca3bd10, 
+    0x21012200, 0xf0204620, 0xb990f894, 0x46202201, 0xf0202102, 0xb960f88e, 0x46202202, 0xf0202104, 
+    0xb930f888, 0x46202203, 0xf0202108, 0x2800f882, 0x2001d0d4, 0x4894e7d2, 0xb087b530, 0xb9d07800, 
+    0x22004c92, 0x46202101, 0xf873f020, 0x2201b988, 0x21024620, 0xf86df020, 0x2202b958, 0x21044620, 
+    0xf867f020, 0x2203b928, 0x21084620, 0xf861f020, 0x2401b108, 0x2400e000, 0x25019404, 0x9000200b, 
+    0x462b2209, 0x5402e9cd, 0x94054611, 0x02689001, 0xfe80f7ff, 0x9000200c, 0x94042301, 0x9405220a, 
+    0x5402e9cd, 0x90014611, 0xf7ff02d8, 0xb007fe73, 0x220bbd30, 0x2000f240, 0xb5104611, 0xfddaf7ff, 
+    0xf640220c, 0xe8bd0000, 0x46114010, 0x486ee5d2, 0x7800b51c, 0x4c6db9d0, 0x21012200, 0xf0204620, 
+    0xb988f828, 0x46202201, 0xf0202102, 0xb958f822, 0x46202202, 0xf0202104, 0xb928f81c, 0x46202203, 
+    0xf0202108, 0xb108f816, 0xe0002401, 0xf2402400, 0x22092000, 0x46114623, 0x94019400, 0xfcf3f7ff, 
+    0x4623220a, 0xf6404611, 0x94000000, 0xf7ff9401, 0xbd1cfcea, 0x41ffe92d, 0x466c2300, 0x429a2200, 
+    0x2108d101, 0x2102e000, 0x1542eb00, 0xeb051e49, 0xe00305c3, 0xb91e5c6e, 0xb2491e49, 0xdaf92900, 
+    0x0582eb04, 0x1c521c49, 0x2a04b252, 0xdbe654e9, 0xb25b1c5b, 0xdbe12b04, 0x46182300, 0x0180eb04, 
+    0x42995609, 0x460bdd00, 0xb2401c40, 0xdbf52804, 0x22044d3c, 0x3d2821f0, 0xf01f4628, 0x2300ffa5, 
+    0x20004619, 0xd0054288, 0x0280eb04, 0x429a5652, 0x4613dd00, 0xb2401c40, 0xdbf32804, 0xb2491c49, 
+    0xdbee2904, 0x46282200, 0xf01f2103, 0x4d2dff8d, 0x46283518, 0xff7cf01f, 0x4601230f, 0x27012200, 
+    0xeb042000, 0x5cb60680, 0xfa07b916, 0x43b1f603, 0x1e5b1c40, 0x2804b240, 0x1c52dbf3, 0x2a04b252, 
+    0x4628dbee, 0xff67f01f, 0x81ffe8bd, 0x41f0e92d, 0x46042300, 0x20004619, 0xd0054288, 0x0280eb04, 
+    0x429a5652, 0x4613dd00, 0xb2401c40, 0xdbf32804, 0xb2491c49, 0xdbee2904, 0x22084812, 0x38280151, 
+    0xff52f01f, 0x35184d0f, 0xf01f4628, 0x231fff41, 0x22004601, 0x20002601, 0x0780eb04, 0xb9175cbf, 
+    0xf703fa06, 0x1c4043b9, 0xb2401e5b, 0xdbf32804, 0xb2521c52, 0xdbee2a04, 0xe8bd4628, 0xf01f41f0, 
+    0x0000bf2a, 0xf1000030, 0x00040502, 0xf2030024, 0x22002301, 0xb5104619, 0xf01f48fe, 0x2300ff3c, 
+    0x210148fd, 0xf01f461a, 0xe8bdff36, 0x48fb4010, 0x0140f242, 0xbf15f01f, 0x4df7b570, 0x2203b28b, 
+    0x1ead4604, 0x46282108, 0xff25f01f, 0x4628b2a3, 0x4070e8bd, 0x21042202, 0xbf1df01f, 0x4deeb570, 
+    0x2201b28b, 0x1ead4604, 0x46282102, 0xff13f01f, 0x4628b2a3, 0x4070e8bd, 0x21012200, 0xbf0bf01f, 
+    0x4de5b570, 0x2206b283, 0x1ead460c, 0x46282140, 0xff01f01f, 0x4628b2a3, 0x4070e8bd, 0x21202205, 
+    0xbef9f01f, 0x48dcb283, 0xf2402208, 0x1e803100, 0xbef1f01f, 0x41f0e92d, 0x4690461f, 0x46084604, 
+    0x5606e9dd, 0xffeef7ff, 0x462043e1, 0xffd8f7ff, 0x46404639, 0xffc2f7ff, 0x46284631, 0x41f0e8bd, 
+    0xb570e7aa, 0x23014dcc, 0x03de220f, 0x46311ead, 0xf01f4628, 0x2301fed0, 0x22074628, 0xf01f2180, 
+    0x2001feca, 0xffcef7ff, 0xe00f0234, 0xf7fe4620, 0x1e04fe97, 0x4cc2dc0a, 0xf01f4620, 0xf040fe9f, 
+    0x46200101, 0x4070e8bd, 0xbe9bf01f, 0x4631220f, 0xf01f4628, 0x2800febe, 0xbd70d1e8, 0x230148b6, 
+    0x21102204, 0xf01f1e80, 0xe92dbea6, 0x4db241f0, 0x4000f500, 0xb281460f, 0x46283d14, 0xfe81f01f, 
+    0x0400f44f, 0xe00e1226, 0xf7fe4620, 0x1e04fe69, 0x4cabdc09, 0xf01f4620, 0xf040fe71, 0x46200102, 
+    0xfe6ff01f, 0x220fe006, 0x46284631, 0xfe91f01f, 0xd1e92800, 0xf2424639, 0xe8bd0000, 0xf7fe41f0, 
+    0xb570be51, 0x46164d9e, 0x4604220f, 0x460b3d9a, 0x0100f248, 0xf01f4628, 0x220dfe6e, 0xf2464633, 
+    0x46280100, 0xfe67f01f, 0x4628b2a3, 0x4070e8bd, 0xf6412200, 0xf01f71ff, 0xb283be5e, 0x2200488e, 
+    0x30602101, 0xbe57f01f, 0x41f0e92d, 0x461e4d8a, 0xf248b293, 0x35200400, 0x220f4688, 0x46214607, 
+    0xf01f4628, 0xb2bbfe48, 0x77fff240, 0x46392200, 0xf01f4628, 0x4621fe40, 0xb2b31eac, 0x220f4620, 
+    0xfe39f01f, 0xf388fa1f, 0x46204639, 0x41f0e8bd, 0xf01f2200, 0xb570be30, 0x48794605, 0x46162301, 
+    0x460c3892, 0x461a2102, 0xfe25f01f, 0x0045ea44, 0xb2834c73, 0x71fff640, 0x22003c8e, 0xf01f4620, 
+    0x2301fe1a, 0x220c4620, 0xf01f0319, 0x4631fe14, 0x4070e8bd, 0xf7fe2004, 0xb570bde5, 0x48684605, 
+    0x46162301, 0x460c3898, 0x461a2102, 0xfe03f01f, 0x0045ea44, 0xb2834c62, 0x71fff640, 0x22003c96, 
+    0xf01f4620, 0x2301fdf8, 0x220c4620, 0xf01f0319, 0x4631fdf2, 0x4070e8bd, 0xf7fe2004, 0xe92dbdc3, 
+    0x4d5847f0, 0x461f0004, 0x46894690, 0x0300f04f, 0xf240d418, 0x46282600, 0x46312209, 0xfddbf01f, 
+    0x2301e00d, 0x22094631, 0xf01f4628, 0x2300fdd4, 0x22094631, 0xf01f4628, 0x1e64fdce, 0x2c00b224, 
+    0xe016dcef, 0x46282208, 0x46310156, 0xfdc3f01f, 0x2301e00d, 0x22084631, 0xf01f4628, 0x2300fdbc, 
+    0x22084631, 0xf01f4628, 0x1c64fdb6, 0x2c00b224, 0x2004dbef, 0xf7fe4639, 0x463afd85, 0x46484641, 
+    0x47f0e8bd, 0xb570e777, 0xb2834d33, 0x4604220b, 0xf6401cad, 0x46280100, 0xfd9df01f, 0x4628b2a3, 
+    0x4070e8bd, 0xf241220c, 0xf01f0100, 0xe92dbd94, 0x4c2d41f0, 0x46062904, 0x2800f240, 0x4500f240, 
+    0x2905d002, 0xe009d004, 0x46032209, 0xe0024641, 0x4603220a, 0x46204629, 0xfd7df01f, 0x220c4f1e, 
+    0xf2414633, 0x1ebf0100, 0xf01f4638, 0x220dfd74, 0xf2424633, 0x46380100, 0xfd6df01f, 0x4633220b, 
+    0x0100f640, 0xf01f4638, 0x2202fd66, 0x21044633, 0xf01f1cb8, 0x4811fd60, 0xf01f3010, 0x220ffd3f, 
+    0x1d384633, 0x0100f248, 0xfd55f01f, 0x2300b98e, 0x220a4629, 0xf01f4638, 0x2209fd4e, 0x46414633, 
+    0xf01f4620, 0x220afd48, 0x46294633, 0xf01f4620, 0xe00bfd42, 0xf2020126, 0xf2035024, 0xf2020000, 
+    0xf203517e, 0xf2035092, 0xf2039000, 0xe8bd2001, 0xb57081f0, 0x23004de1, 0x46042203, 0x46282108, 
+    0xfd29f01f, 0x46282300, 0x21042202, 0xfd23f01f, 0x46282300, 0x461a2101, 0xfd1df01f, 0x1cae2300, 
+    0x2101461a, 0xf01f4630, 0xb374fd16, 0xd0362c01, 0xd0342c02, 0xd1402c03, 0x46282300, 0x21102204, 
+    0xfd09f01f, 0x46302300, 0x21042202, 0xfd03f01f, 0x46282301, 0x21082203, 0xfcfdf01f, 0x46282301, 
+    0x21042202, 0xfcf7f01f, 0x46282301, 0x46192200, 0xfcf1f01f, 0x22002301, 0x46304619, 0xfcebf01f, 
+    0xe8bd2000, 0xf0134070, 0x2300bdab, 0x22044628, 0xf01f2110, 0x2300fce0, 0x21042202, 0x2301e7ed, 
+    0x22044628, 0xf01f2110, 0x2301fcd6, 0x22024630, 0xf01f2104, 0x2001fcd0, 0xbd70e7e3, 0x5ff0e92d, 
+    0x48ae4604, 0x4693469a, 0x46892200, 0xf240387c, 0xf24033c2, 0xf01f71ff, 0xf8dffcbe, 0x2c0482a0, 
+    0x0500f247, 0x1600f240, 0x087ef1a8, 0x6700f240, 0x2c05d002, 0xe01cd01a, 0x0f00f1b9, 0xf1bad119, 
+    0xd0160f03, 0x46402301, 0x46192200, 0xfca3f01f, 0x46402302, 0x21062201, 0xfc9df01f, 0x46312301, 
+    0x46402208, 0xfc97f01f, 0xe02f2302, 0x0f00f1bb, 0x2300d019, 0x22014640, 0xf01f2106, 0x2300fc8c, 
+    0x22094639, 0xf01f4640, 0x2300fc86, 0x22084631, 0xf01f4640, 0x2300fc80, 0x461a2101, 0xe8bd4640, 
+    0xf01f5ff0, 0x2301bc78, 0x22004640, 0xf01f4619, 0x2303fc72, 0x22014640, 0xf01f2106, 0x2301fc6c, 
+    0x22084631, 0xf01f4640, 0x2303fc66, 0x22094639, 0xf01f4640, 0x2301fc60, 0x220c4629, 0xe92de7de, 
+    0x4c765ff0, 0x4f754605, 0x3f503c5a, 0xf8dfb151, 0x290181cc, 0x76fff64f, 0x0836f1a8, 0x2902d00c, 
+    0xe060d020, 0x46202300, 0x461a2101, 0xfc43f01f, 0x21012300, 0xe0cb461a, 0x46202301, 0x21042202, 
+    0xfc39f01f, 0x46202300, 0x21082203, 0xfc33f01f, 0x46402101, 0xfc15f01f, 0x46314860, 0xf01f3834, 
+    0xe040fc10, 0x46202300, 0x21042202, 0xfc23f01f, 0x46202301, 0x21082203, 0xfc1df01f, 0x1101f240, 
+    0xf01f4640, 0x4855fbfe, 0x38324631, 0xfbf9f01f, 0x46314852, 0xf01f3830, 0x4850fbf4, 0x382e4631, 
+    0xfbeff01f, 0x4631484d, 0xf01f382c, 0x484bfbea, 0x382a4631, 0xfbe5f01f, 0x46314848, 0xf01f3828, 
+    0x4846fbe0, 0x38264631, 0xfbdbf01f, 0x46314843, 0xf01f3824, 0x4842fbd6, 0xf2402208, 0x78037100, 
+    0xf01f4638, 0x4e3dfbe8, 0x78fff640, 0xb0ecf8df, 0x7afff240, 0x2d043e58, 0x0902f106, 0x0b7cf1ab, 
+    0x2d05d002, 0xe041d01f, 0xf6402200, 0x46413356, 0xf01f4630, 0xf240fbd0, 0x464135c2, 0x462b2200, 
+    0xf01f4648, 0x2200fbc8, 0x4651462b, 0xf01f4658, 0x2303fbc2, 0x0100f24f, 0x4638220c, 0xfbbbf01f, 
+    0x7394f240, 0x2200e01d, 0x439af640, 0x46304641, 0xfbb1f01f, 0xf2402200, 0x46415304, 0xf01f4648, 
+    0x2200fbaa, 0x2382f240, 0x46584651, 0xfba3f01f, 0xf24f2306, 0x220c0100, 0xf01f4638, 0xf240fb9c, 
+    0x46417396, 0x46302200, 0xfb95f01f, 0x46202300, 0x21102204, 0xfb8ff01f, 0x46202301, 0x46192200, 
+    0xfb89f01f, 0x46382301, 0x46192200, 0xfb83f01f, 0x2320480a, 0x213f2200, 0xf01f3854, 0x2301fb7c, 
+    0x22024638, 0xf01f2104, 0x2300fb76, 0x21102204, 0xe8bd4638, 0xf01f5ff0, 0x0000bb6e, 0xf2035336, 
+    0x000402f8, 0x47f0e92d, 0x23014dfa, 0x461a460c, 0x46282102, 0xfb5ff01f, 0x780949f7, 0x2301b929, 
+    0x22004628, 0xf01f4619, 0xf8dffb56, 0x230193c8, 0x03de220f, 0x0902f109, 0x46484631, 0xfb4bf01f, 
+    0xf2464dee, 0x220d0800, 0x68284641, 0x3020f890, 0xf01f4648, 0x6828fb40, 0x77fff641, 0x46392200, 
+    0x46488c43, 0xfb37f01f, 0x0902f109, 0x23004631, 0x220f4648, 0xfb2ff01f, 0x220d6828, 0xf8904641, 
+    0x46483026, 0xfb27f01f, 0x22006828, 0x8c834639, 0xf01f4648, 0xf109fb20, 0x46310902, 0x46482301, 
+    0xf01f220f, 0x6828fb18, 0x4641220d, 0x302cf890, 0xf01f4648, 0x6828fb10, 0x46392200, 0x46488dc3, 
+    0xfb09f01f, 0x0902f109, 0x23014631, 0x220f4648, 0xfb01f01f, 0x2c01b134, 0x2c02d008, 0x2c03d006, 
+    0xe00fd008, 0xf8906828, 0xe0063027, 0xf8906828, 0xe0023028, 0xf8906828, 0x220d3029, 0x46484641, 
+    0xfae9f01f, 0x22006828, 0x8d434639, 0xf01f4648, 0xf8dffae2, 0x230092e0, 0x4631220f, 0x090af109, 
+    0xf01f4648, 0x6828fad8, 0x4644220d, 0xf8904641, 0x46483034, 0xfacff01f, 0x22006828, 0x8ec34639, 
+    0xf01f4648, 0x4631fac8, 0x0602f109, 0x46302300, 0xf01f220f, 0x6828fac0, 0x4621220d, 0x3030f890, 
+    0xf01f4630, 0x6828fab8, 0x46392200, 0x3048f8b0, 0x30f048a0, 0xfaaff01f, 0x7e806828, 0x47f0e8bd, 
+    0xbbb9f000, 0x47f0e92d, 0xf6414c9d, 0xf8df7100, 0xf240c270, 0x3c9635f0, 0x0600f24f, 0xf04f1ca7, 
+    0x28040306, 0x0208f04f, 0x0902f10c, 0x46604688, 0xf01fd02d, 0x2303fa90, 0x22004620, 0xf01f210f, 
+    0x230cfa8a, 0x22044629, 0xf01f4620, 0x2304fa84, 0x220c4631, 0xf01f4620, 0x2303fa7e, 0x22004638, 
+    0xf01f210f, 0x230dfa78, 0x22044629, 0xf01f4638, 0x2302fa72, 0x22084641, 0xf01f4648, 0x4631fa6c, 
+    0xe8bd4638, 0x230447f0, 0xf01f220c, 0xf01fba64, 0x2303fa62, 0x22004620, 0xf01f210f, 0x230bfa5c, 
+    0x22044629, 0xf01f4620, 0x2304fa56, 0x220c4631, 0xf01f4620, 0x2303fa50, 0x22004638, 0xf01f210f, 
+    0x230cfa4a, 0xe92de7d0, 0x240041fc, 0x94012003, 0xfaf4f7fe, 0xf7fe2002, 0x2001faf1, 0xfaeef7fe, 
+    0xf7fe2011, 0x2012faeb, 0xfae8f7fe, 0xf7fe2001, 0x2002f9b2, 0xf9aff7fe, 0xf7fe2004, 0x2301f9ac, 
+    0x220c4860, 0xf01f0319, 0x485ffa26, 0x485f7004, 0x20007004, 0xfc85f013, 0x6800485d, 0xd1072801, 
+    0xf640485c, 0x60040100, 0x6800485b, 0xf9f2f020, 0x8800485a, 0x2301b128, 0x22004859, 0xf01f4619, 
+    0xf004fa0a, 0x2001f9fa, 0xfc5df7ff, 0xf6412200, 0x20040300, 0x94004611, 0xfb86f001, 0x78014851, 
+    0xf7ff2000, 0x4843fc64, 0x22012300, 0x38b02102, 0xf9f1f01f, 0x22084c3f, 0x34522300, 0x46200151, 
+    0xf9e9f01f, 0xf44f4d3b, 0x4f3a0100, 0x910135a8, 0x3fa8138e, 0x2103e00c, 0xa801462a, 0xfa47f7fe, 
+    0xd00c2801, 0x46312301, 0x46202209, 0xf9d3f01f, 0x46382206, 0xf01f2140, 0x2800f9dc, 0x4c3ad1eb, 
+    0x22032301, 0x46202108, 0xf9c5f01f, 0x46202300, 0x21082203, 0xf9bff01f, 0x78004834, 0xfbc0f7fd, 
+    0x4d332301, 0x035c220d, 0x46214628, 0xf9b3f01f, 0x1daf2301, 0x463803de, 0x4631220f, 0xf9abf01f, 
+    0x46312300, 0x4638220f, 0xf9a5f01f, 0x46212300, 0x4628220d, 0xf99ff01f, 0xf7ff2000, 0x2001faa3, 
+    0xf928f010, 0xfdc3f010, 0xfb46f7f8, 0x23004c11, 0x461a2101, 0x46203cbc, 0xf98df01f, 0x46202300, 
+    0x21022201, 0xf987f01f, 0x46202300, 0x21042202, 0xf981f01f, 0x46202300, 0x21082203, 0xf97bf01f, 
+    0x2300480f, 0x4631220f, 0xf01f38c4, 0xe8bdf974, 0x000081fc, 0xf20350d4, 0x00040502, 0x00040598, 
+    0xf2035332, 0xf203902c, 0x000401fc, 0x000402b2, 0x00057f74, 0x00057ff0, 0x000401e4, 0x00040240, 
+    0xf38f20e0, 0x00040242, 0xf2036100, 0x00040243, 0xf23c8306, 0xf04f2102, 0x0488422b, 0xf7f7b510, 
+    0x2003f96e, 0xfd77f002, 0xf0022006, 0xe8bdfd74, 0xf0014010, 0x0000ba72, 0x41f0e92d, 0x845cf8df, 
+    0xb283461c, 0x22064615, 0x21c0460e, 0x46404607, 0xf931f01f, 0x4640b2b3, 0x21302204, 0xf92bf01f, 
+    0x4640b2ab, 0x210c2202, 0xf925f01f, 0x4640b2a3, 0x21032200, 0xf91ff01f, 0x8420f8df, 0x2206b2bb, 
+    0x081cf108, 0x464021c0, 0xf915f01f, 0x4640b2b3, 0x21302204, 0xf90ff01f, 0x4640b2ab, 0x210c2202, 
+    0xf909f01f, 0x4640b2a3, 0x21032200, 0xf903f01f, 0x4ffbb2bb, 0x21032200, 0xf01f4638, 0xb2b3f8fc, 
+    0x22024638, 0xf01f210c, 0xb2abf8f6, 0x22044638, 0xf01f2130, 0xb2a3f8f0, 0xe8bd4638, 0x220641f0, 
+    0xf01f21c0, 0xb570b8e8, 0x23014cec, 0x46052200, 0x46193c40, 0xf01f4620, 0x4ae8f8de, 0x4620462b, 
+    0x4070e8bd, 0x21013a2e, 0xbff5f01f, 0x460db570, 0xf7ff4604, 0x2200ffe8, 0x0022f854, 0xd90142a8, 
+    0xbd702001, 0xb2521c52, 0xdbf52a04, 0xbd702000, 0x4605b570, 0x230048d9, 0x0100f248, 0x3834220f, 
+    0xf8b9f01f, 0x24004ed5, 0xf8353e12, 0xf3c00014, 0xf4400009, 0xeb066180, 0xf01f0044, 0x1c64f892, 
+    0x2c04b264, 0xbd70dbf1, 0x48ccb283, 0x21012200, 0xf01f383e, 0xe92db8a0, 0x4fc847f0, 0xf640b293, 
+    0x46140800, 0x460d3f1e, 0x4606220b, 0x46384641, 0xf891f01f, 0x0900f247, 0xb2ab4638, 0x220c4649, 
+    0xf889f01f, 0x0a00f248, 0xb2b34638, 0x220f4651, 0xf881f01f, 0x46411cbf, 0x4638b2a3, 0xf01f220b, 
+    0xb2abf87a, 0x220c4649, 0xf01f4638, 0xb2b3f874, 0x220f4651, 0xf01f4638, 0x1cbff86e, 0xb2a34641, 
+    0x220b4638, 0xf867f01f, 0x4649b2ab, 0x4638220c, 0xf861f01f, 0x4651b2b3, 0x4638220f, 0xf85bf01f, 
+    0x4641b2a3, 0x220b1cbc, 0xf01f4620, 0xb2abf854, 0x220c4649, 0xf01f4620, 0xb2b3f84e, 0x46204651, 
+    0x47f0e8bd, 0xf01f220f, 0xb510b846, 0x489b4604, 0xf01f380a, 0xf000f823, 0x8020001f, 0x38084897, 
+    0xf81cf01f, 0x001ff000, 0x48948060, 0xf01f1f80, 0xf000f815, 0x80a0001f, 0x1f004890, 0xf80ef01f, 
+    0x001ff000, 0xbd1080e0, 0x2b03b570, 0x4605460c, 0xf992d108, 0x20011002, 0x0011f825, 0x1003f992, 
+    0x0011f825, 0x16e0f240, 0x22054886, 0xf01f4631, 0x8821f820, 0x44082205, 0x48838020, 0xf01f4631, 
+    0x8861f818, 0x44082205, 0x48808060, 0xf01f4631, 0x88a1f810, 0x44082205, 0x487d80a0, 0xf01f4631, 
+    0x88e1f808, 0x80e04408, 0xf0012001, 0x2000fb7d, 0xfb7af001, 0x24004e71, 0xf8153e0a, 0xf0000014, 
+    0xf040001f, 0xeb060120, 0xf01e0044, 0x1c64ffca, 0x2c04b264, 0xbd70dbf1, 0x4605b5f0, 0xf5b52000, 
+    0x46043f80, 0x210fd301, 0x2107e000, 0x2701004a, 0xf302fa07, 0xfa001c4a, 0x4422f202, 0x42aa441a, 
+    0xfa07d804, 0xea46f601, 0x46140000, 0xea4fd003, 0xf1a10393, 0x29000101, 0x42aadb01, 0xbdf0d1ea, 
+    0x460cb510, 0x48554601, 0xf01e1e80, 0x4621ff9a, 0xe8bd4858, 0xf01e4010, 0x4850bf94, 0x21022301, 
+    0x3840461a, 0xbfa7f01e, 0x4d53b570, 0x4614b283, 0x220c460e, 0x0100f24f, 0xf01e4628, 0x2208ff9c, 
+    0xb2b34628, 0xf01e0151, 0x2c03ff96, 0x2c02d013, 0x2c01d01b, 0x2c00d023, 0x2300d12b, 0x22044628, 
+    0xf01e2110, 0x2300ff88, 0x461a2101, 0xe8bd4628, 0xf01e4070, 0x2300bf80, 0x22074628, 0xf01e2180, 
+    0x2300ff7a, 0x21082203, 0x2300e7f0, 0x22064628, 0xf01e2140, 0x2300ff70, 0x21042202, 0x2300e7e6, 
+    0x22054628, 0xf01e2120, 0x2300ff66, 0x21022201, 0xbd70e7dc, 0x4d30b570, 0x460c2a03, 0x2a02d013, 
+    0x2a01d01b, 0x2a00d023, 0xb283d12b, 0x22044628, 0xf01e2110, 0x2200ff50, 0x2101b2a3, 0xe8bd4628, 
+    0xf01e4070, 0xb283bf48, 0x22074628, 0xf01e2180, 0x2203ff42, 0x2108b2a3, 0xb283e7f0, 0x22064628, 
+    0xf01e2140, 0x2202ff38, 0x2104b2a3, 0xb283e7e6, 0x22054628, 0xf01e2120, 0x2201ff2e, 0x2102b2a3, 
+    0xbd70e7dc, 0x4814b283, 0x21012200, 0xf01e1f00, 0xb570bf22, 0x220c4c09, 0x46034605, 0xf2413c46, 
+    0x46200100, 0xff17f01e, 0x4620462b, 0x4070e8bd, 0xf240220a, 0xf01e4100, 0x0000bf0e, 0xf2030446, 
+    0xf2035124, 0xf203c65e, 0xf203ce5e, 0xf203d65e, 0xf203de5e, 0xf2031012, 0xf2030024, 0x46032200, 
+    0x210f48a6, 0xbef7f01e, 0xb51048a4, 0xfed6f01e, 0x000ff000, 0x4603bd10, 0x220048a0, 0x31fff240, 
+    0xf01e3844, 0xb510bee8, 0x46034604, 0x2207489b, 0x38482180, 0xfedff01e, 0x22004898, 0x46232101, 
+    0xf01e1f00, 0x2200fed8, 0xe8bd4623, 0x48944010, 0xf01e2101, 0xb570bed0, 0x220d4c90, 0x46034605, 
+    0xf2423c48, 0x46200100, 0xfec5f01e, 0x4620462b, 0x4070e8bd, 0xf640220b, 0xf01e0100, 0xb510bebc, 
+    0x23014c88, 0x21402206, 0xf01e4620, 0x2301feb4, 0x22024620, 0xf01e2104, 0x2301feae, 0x21024620, 
+    0xf01e461a, 0x2301fea8, 0x22004620, 0xf01e4619, 0x1ca4fea2, 0x46202301, 0x21402206, 0xfe9bf01e, 
+    0x46202301, 0x21042202, 0xfe95f01e, 0x46202301, 0x461a2102, 0xfe8ff01e, 0x46202301, 0x46192200, 
+    0xfe89f01e, 0x23011ca4, 0x22064620, 0xf01e2140, 0x2301fe82, 0x22024620, 0xf01e2104, 0x2301fe7c, 
+    0x21024620, 0xf01e461a, 0x2301fe76, 0x22004620, 0xf01e4619, 0x1ca4fe70, 0x46202301, 0x21402206, 
+    0xfe69f01e, 0x46202301, 0x21042202, 0xfe63f01e, 0x46202301, 0x461a2102, 0xfe5df01e, 0x46202301, 
+    0x46192200, 0xfe57f01e, 0x23011d24, 0x22024620, 0xf01e2104, 0x2301fe50, 0x21024620, 0xf01e461a, 
+    0x2301fe4a, 0xe8bd4620, 0x22004010, 0xf01e4619, 0xb570be42, 0x46144d49, 0x460e2201, 0x460335aa, 
+    0x46282102, 0xfe37f01e, 0x46281e64, 0x2204b2a3, 0xf01e2170, 0x4633fe30, 0xe8bd4628, 0x22004070, 
+    0xf01e2101, 0x4601be28, 0x30ac483c, 0xbe09f01e, 0x30ac483a, 0xbe02f01e, 0x4838b283, 0xf2402200, 
+    0x381871ff, 0xbe17f01e, 0x4c34b510, 0x2200b283, 0x71fff643, 0x46203c32, 0xfe0df01e, 0x46202301, 
+    0xe8bd220e, 0x03994010, 0xbe05f01e, 0x460b2801, 0x2802d00e, 0x2804d009, 0x2808d004, 0x2203d10a, 
+    0xe0072108, 0x21042202, 0x2201e004, 0xe0012102, 0x21012200, 0xb2524824, 0xbdedf01e, 0x460b2801, 
+    0x2802d010, 0x2804d00b, 0x2808d005, 0x220cd10c, 0x0100f247, 0x2208e008, 0x7100f240, 0x2170e004, 
+    0xe0012204, 0x22002107, 0xb2524817, 0xf01e1c80, 0x4601bdd2, 0x1d004814, 0xbdb3f01e, 0x210f4812, 
+    0xf01e1f00, 0x4603bdae, 0x2200480f, 0x3828211f, 0xbdc1f01e, 0x480c4601, 0xf01e382a, 0x4603bda2, 
+    0x22084809, 0x7100f640, 0xf01e382c, 0x4603bdb4, 0x22004805, 0x382c2101, 0xbdadf01e, 0xf2030448, 
+    0xf2031012, 0xf2030000, 0xf20305de, 0x41f0e92d, 0x48fe4604, 0xfcb7f7ff, 0x21004bfd, 0xf24a4dfd, 
+    0x4afa0700, 0x2662f249, 0xb9b05c60, 0x28126818, 0x2816d00d, 0xf995d00b, 0x28040000, 0x2805d007, 
+    0xf852d005, 0x42b00021, 0x2001d905, 0xf852e004, 0x42b80021, 0x2000d8f9, 0x1c495460, 0x2904b249, 
+    0xe8bddbe2, 0x200181f0, 0xf012b510, 0x2000fdd5, 0xfe89f7ff, 0xf2402100, 0xf7ff1000, 0x4ce6fdb1, 
+    0x68202100, 0x2038f890, 0x003af9b0, 0xfee9f7fe, 0xf9b06820, 0xf7ff003e, 0x48e0ff47, 0xf6407801, 
+    0xe8bd0000, 0xf7fd4010, 0xe92dbd2d, 0x48da4ff3, 0x6800b087, 0xea4f8800, 0x200409d0, 0x48d89006, 
+    0x28037800, 0x2002d101, 0x27009006, 0x48d5e081, 0x980857c4, 0xa802b1f8, 0x6014f930, 0xf930a804, 
+    0xf2065014, 0xfb1612ff, 0xf240f006, 0xfb1531fe, 0x428a0005, 0xf205d803, 0x428a12ff, 0x0100d921, 
+    0xfd4af7ff, 0x04f1b200, 0xf2f0fb91, 0xfb9104e9, 0x1080f1f0, 0xf8dfe020, 0x23018310, 0x22004dc3, 
+    0x46184621, 0x5800e9cd, 0xf9e8f7fc, 0xf935a802, 0xf9386019, 0xf8205019, 0xa8046014, 0x5014f820, 
+    0x0280e7cf, 0xfd28f7ff, 0x05b1b200, 0xf2f0fb91, 0xfb9105a9, 0x1140f1f0, 0xf44f4680, 0xea4f3000, 
+    0xea4f1b62, 0xf6401a61, 0xf7f60101, 0xf44ffcca, 0x46313000, 0xfcb4f7f6, 0x3000f44f, 0xf7f64629, 
+    0xf44ffcaf, 0x46513000, 0xfcaaf7f6, 0x3000f44f, 0xf7f64659, 0xf44ffca5, 0x46413000, 0xfca0f7f6, 
+    0xfa1f48a3, 0xeb00f18b, 0xf01e0084, 0x48a0fcba, 0xf18afa1f, 0xeb001c80, 0xf01e0084, 0x489cfcb2, 
+    0xf188fa1f, 0xeb003810, 0xf01e0044, 0x1c7ffcaa, 0x9806b2ff, 0xf4ff4287, 0x4c95af7a, 0x22082302, 
+    0x7100f64f, 0x46203c1e, 0xfcb5f01e, 0x46202201, 0xf3c8210e, 0xf01e234f, 0x9807fcae, 0x21012200, 
+    0x4620b283, 0xfca7f01e, 0xe8bdb009, 0x20008ff0, 0xf7ffb510, 0x2101fece, 0xf7ff2008, 0x2101fe97, 
+    0xf7ff2004, 0x2101fe93, 0xf7ff2002, 0x2101fe8f, 0xf7ff4608, 0x2103fe8b, 0xf7ff2008, 0x2103fe9f, 
+    0xf7ff2004, 0x2103fe9b, 0xf7ff2002, 0x2103fe97, 0xf7ff2001, 0xf240fe93, 0xf7ff3000, 0x2010febb, 
+    0xfeb1f7ff, 0xf7ff2005, 0xe8bdfeba, 0xf7ff4010, 0x4870bea5, 0xb5102100, 0xfc53f01e, 0xffc7f7ff, 
+    0x4010e8bd, 0xf7fd201c, 0xe92dbd08, 0x48624ff0, 0xf8dfb087, 0xf10db1a4, 0xf10d0814, 0x68000904, 
+    0x08458800, 0x46a22400, 0xa000f8cd, 0x3000f8db, 0x20012200, 0x465f4656, 0xf7fcb261, 0xf04ff947, 
+    0x46c430ff, 0x6014f828, 0x0014f829, 0x2000683a, 0xe011464b, 0x1010f932, 0xda001e0f, 0xf93c4279, 
+    0x4571e014, 0x2f00dd06, 0x427fda00, 0x7014f82c, 0x0014f823, 0xb2001c40, 0xdbeb42a8, 0x1014f933, 
+    0x0c00f04f, 0xe009460f, 0x0011f932, 0xda002800, 0x1c494240, 0xfa0f4460, 0xb209fc80, 0xdbf342a9, 
+    0x2000a903, 0x1cecea4f, 0x6014f821, 0xe00f4606, 0xe010f932, 0x0f00f1be, 0xf1ceda01, 0x44760e00, 
+    0x4566b236, 0xf821dd02, 0xe0030014, 0xb2001c40, 0xdced4287, 0xb2241c64, 0xdba52c04, 0x24002001, 
+    0xf9334622, 0xf9335010, 0x42b56014, 0x4604dd00, 0x6010f931, 0x7012f931, 0xf9331bad, 0x1bf66012, 
+    0xdd0042b5, 0x1c404602, 0x2804b200, 0xf833dbe9, 0xf8390014, 0xf8313012, 0xebc01012, 0x1a400043, 
+    0xb2043808, 0xdd712c00, 0xd00107e0, 0xb2241c64, 0x4e1a4d22, 0xeb008828, 0x80280064, 0x10607831, 
+    0xfd23f7fe, 0x22017833, 0x1000f9b5, 0xf7fe4620, 0x7831fdd6, 0x1000f240, 0xfb94f7fd, 0x0500f44f, 
+    0x11f4f240, 0xf7f64628, 0xf04ffb8c, 0x46283134, 0xfb76f7f6, 0x1004f9bd, 0xf7f64628, 0xf9bdfb71, 
+    0x46281006, 0xfb6cf7f6, 0x0000e01a, 0x000413e8, 0x000401f0, 0x00040242, 0x00040598, 0x00040243, 
+    0x0004057b, 0x00040520, 0x00049108, 0x00048908, 0xf2030040, 0xf2030400, 0x000401e8, 0x00040506, 
+    0x1008f9bd, 0xf7f64628, 0xf9bdfb4b, 0x4628100a, 0xfb46f7f6, 0x100cf9bd, 0xf7f64628, 0xf9bdfb41, 
+    0x4628100e, 0xfb3cf7f6, 0x1010f9bd, 0xf7f64628, 0xf9bdfb37, 0x46281012, 0xfb32f7f6, 0x46284621, 
+    0xfb2ef7f6, 0x462849b2, 0xfb2af7f6, 0xe6bcb007, 0x5ffce92d, 0x48af4606, 0x92bcf8df, 0x46a82500, 
+    0x88006800, 0x0b50ea4f, 0x42ac2400, 0xf04fd102, 0xe0040000, 0xf104da02, 0xe0000001, 0xf8d94620, 
+    0xfa4f7000, 0x4629fa80, 0x4652463b, 0x0001f04f, 0x8000f8cd, 0xf83af7fc, 0x0084eb06, 0xb9585d40, 
+    0x46384659, 0xfb26f01f, 0x46522300, 0x46292001, 0x7800e9cd, 0xff57f7fb, 0xb2641c64, 0xdbd42c04, 
+    0xb26d1c6d, 0xdbcf2d04, 0x46212400, 0x42882000, 0xeb06d004, 0x5c520280, 0x2401b102, 0xb2401c40, 
+    0xdbf42804, 0xb2491c49, 0xdbef2904, 0x46304e8b, 0xfaf4f01e, 0xb16cb200, 0x0507f040, 0xb2a92400, 
+    0x0044eb06, 0xfaedf01e, 0xb2641c64, 0xdbf62c04, 0x9ffce8bd, 0x0507f020, 0xe92de7f0, 0x487d4ff0, 
+    0x21012200, 0x085af04f, 0x6800b087, 0x08478800, 0x4071f04f, 0xfae6f01e, 0x9005b240, 0xf7fd2000, 
+    0xf8dfff13, 0x2600a1d4, 0x240046b1, 0xd10242b4, 0x0000f04f, 0xda02e004, 0x0001f104, 0x4620e000, 
+    0xb000f8da, 0x4631b242, 0xf04f465b, 0xf8cd0001, 0xf7fb9000, 0x2500ffcb, 0x4658463a, 0xf105fb07, 
+    0xfa51f013, 0xdc034540, 0xb26d1e6d, 0xdaf32d00, 0xeb00a801, 0x1c6d0084, 0x558542b4, 0x2101d101, 
+    0x1c645581, 0x2c04b264, 0x1c76dbd0, 0x2e04b276, 0xa801dbcb, 0xff4cf7ff, 0xf7fea801, 0x9805fb27, 
+    0xfed2f7fd, 0x0400f44f, 0x11f4f240, 0xf7f64620, 0x4852fa78, 0xfa82f01e, 0x46204601, 0xfa60f7f6, 
+    0x1c80484e, 0xfa7af01e, 0x46204601, 0xfa58f7f6, 0x1d00484a, 0xfa72f01e, 0x46204601, 0xfa50f7f6, 
+    0x1d804846, 0xfa6af01e, 0x46204601, 0xfa48f7f6, 0xf01e4843, 0x4601fa5d, 0xf7f64620, 0x4840fa41, 
+    0xf01e3040, 0x4601fa55, 0xf7f64620, 0x4938fa39, 0xf7f64620, 0xe709fa35, 0x4ff8e92d, 0x48354606, 
+    0x90d4f8df, 0xf04f460d, 0x68003aff, 0x08478800, 0x46a02400, 0x8000f8cd, 0x3000f8d9, 0x20012200, 
+    0xf7fbb261, 0xf825ff53, 0x20008014, 0xf826464a, 0xe012a014, 0xf9316811, 0x1e0b1010, 0x4259da00, 
+    0xc014f935, 0xdd064561, 0xd5000019, 0xf8254259, 0xf8261014, 0x1c400014, 0x42b8b200, 0x1c64dbea, 
+    0x2c04b224, 0xe8bddbd6, 0x491a8ff8, 0x43f8e92d, 0x4d196809, 0xea4f8809, 0x21000951, 0x460a9100, 
+    0xb241682b, 0xf7fb2001, 0x2200ff21, 0x8000f8d5, 0x46104613, 0x46144611, 0xf838e012, 0xfb155014, 
+    0x17eef505, 0x41731952, 0xce04fba5, 0xfb0617e7, 0xfb05e604, 0xeb1c6507, 0x41690000, 0xb2241c64, 
+    0xdbea454c, 0xeb6ef01d, 0xe8bdb200, 0x000083f8, 0xdcba01f5, 0x00040598, 0x000401e8, 0xf2030000, 
+    0xf1000008, 0x5ff0e92d, 0x4de72301, 0x039c220e, 0x46214628, 0xf9eff01e, 0x46282301, 0x031e220c, 
+    0xf01e4631, 0x2301f9e8, 0x220b4628, 0x463902df, 0xf9e1f01e, 0x4800f240, 0x23014628, 0x220a4641, 
+    0xf9d9f01e, 0x2900f240, 0x23014628, 0x22094649, 0xf9d1f01e, 0x1a00f240, 0x23014628, 0x22084651, 
+    0xf9c9f01e, 0x46282301, 0x21802207, 0xf9c3f01e, 0x46282301, 0x21402206, 0xf9bdf01e, 0x0b02f105, 
+    0x23014621, 0x220e4658, 0xf9b5f01e, 0x46312301, 0x4658220c, 0xf9aff01e, 0x46392301, 0x4658220b, 
+    0xf9a9f01e, 0x46412301, 0x4658220a, 0xf9a3f01e, 0x46492301, 0x46582209, 0xf99df01e, 0x46512301, 
+    0x46582208, 0xf997f01e, 0x46582301, 0x21802207, 0xf991f01e, 0x46582301, 0x21402206, 0xf98bf01e, 
+    0x46212301, 0x1d28220e, 0xf985f01e, 0x46312301, 0x1d28220c, 0xf97ff01e, 0x46392301, 0x1d28220b, 
+    0xf979f01e, 0x46412301, 0x1d28220a, 0xf973f01e, 0x46492301, 0x1d282209, 0xf96df01e, 0x46512301, 
+    0x1d282208, 0xf967f01e, 0x22072301, 0x1d282180, 0xf961f01e, 0x22062301, 0x1d282140, 0xf95bf01e, 
+    0x1dac4621, 0x46202301, 0xf01e220e, 0x2301f954, 0x220c4631, 0xf01e4620, 0x2301f94e, 0x220b4639, 
+    0xf01e4620, 0x2301f948, 0x220a4641, 0xf01e4620, 0x2301f942, 0x22094649, 0xf01e4620, 0x2301f93c, 
+    0x22084651, 0xf01e4620, 0x2301f936, 0x22074620, 0xf01e2180, 0x2301f930, 0x22064620, 0xf01e2140, 
+    0x2301f92a, 0x22054628, 0xf01e2120, 0x2301f924, 0x22034628, 0xf01e2108, 0x2301f91e, 0x21024628, 
+    0xf01e461a, 0x2301f918, 0x22054658, 0xf01e2120, 0x2301f912, 0x22034658, 0xf01e2108, 0x2301f90c, 
+    0x21024658, 0xf01e461a, 0x2301f906, 0x21202205, 0xf01e1ea0, 0x2301f900, 0x21082203, 0xf01e1ea0, 
+    0x2301f8fa, 0x461a2102, 0xf01e1ea0, 0x2301f8f4, 0x22054620, 0xf01e2120, 0x2301f8ee, 0x22034620, 
+    0xf01e2108, 0x2301f8e8, 0x21024620, 0xf01e461a, 0x2301f8e2, 0x22044628, 0xf01e2110, 0x2301f8dc, 
+    0x22024628, 0xf01e2104, 0x2301f8d6, 0x22004628, 0xf01e4619, 0x2301f8d0, 0x22044658, 0xf01e2110, 
+    0x2301f8ca, 0x22024658, 0xf01e2104, 0x2301f8c4, 0x22004658, 0xf01e4619, 0x2301f8be, 0x21102204, 
+    0xf01e1ea0, 0x2301f8b8, 0x21042202, 0xf01e1ea0, 0x2301f8b2, 0x46192200, 0xf01e1ea0, 0x2301f8ac, 
+    0x22044620, 0xf01e2110, 0x2301f8a6, 0x22024620, 0xf01e2104, 0x2301f8a0, 0x22004620, 0xf01e4619, 
+    0x1ca4f89a, 0x46202301, 0x21042202, 0xf893f01e, 0x46202301, 0x461a2102, 0xf88df01e, 0xe8bd4620, 
+    0x23015ff0, 0x46192200, 0xb885f01e, 0x482e4603, 0x217f2200, 0xf01e300e, 0xb510b87e, 0x482a4604, 
+    0x71fff64f, 0xf01e3032, 0x4827f85c, 0x30342100, 0xf857f01e, 0xb2a34824, 0x21012200, 0x4010e8bd, 
+    0xf01e3030, 0xe92db868, 0x4c1f41f0, 0xb283461d, 0x34104616, 0x2206460f, 0x21c04620, 0xf85bf01e, 
+    0x4620b2bb, 0x21302204, 0xf855f01e, 0x4620b2b3, 0x210c2202, 0xf84ff01e, 0x4620b2ab, 0x41f0e8bd, 
+    0x21032200, 0xb847f01e, 0x480fb283, 0x21012200, 0xf01e3012, 0xb570b840, 0xd0130004, 0x4d0a2300, 
+    0x35302201, 0x46282102, 0xf835f01e, 0x4628b2a3, 0x21012200, 0xf82ff01e, 0x1da82104, 0x4070e8bd, 
+    0xb80ff01e, 0xe7ea2301, 0xf2031000, 0x5fffe92d, 0x48994681, 0xb264f8df, 0x68002500, 0xea4f8800, 
+    0x48970a50, 0x0045eb00, 0xf01d9003, 0xb207fff7, 0x42ac2400, 0xf04fd102, 0xe0040000, 0xf104da02, 
+    0xe0000001, 0x42ac4620, 0x9002b240, 0xf04fd102, 0xe0010608, 0x0602f04f, 0xf04fd102, 0xe00b0106, 
+    0xf04fdd02, 0xe0010001, 0x0000f04f, 0x0000eba4, 0x0040ea4f, 0x0104f1c0, 0x0301f04f, 0x1244eb09, 
+    0x0001f1a6, 0x02c5eb02, 0x0c06eb01, 0x5c11e01e, 0xd01d2901, 0xdb102803, 0xd10e2c03, 0xd10c2d03, 
+    0x1000f819, 0xeb09b9a1, 0xf8910100, 0xf1bee028, 0xd10d0f00, 0x1050f891, 0xebacb951, 0x1e490100, 
+    0xf101fa03, 0x1e40438f, 0xb240b23f, 0xdade2800, 0x9a021c40, 0xf880fa4f, 0x20004629, 0xf8db9000, 
+    0xf7fb3000, 0x45b0fcb3, 0xeba6da17, 0xf8db0108, 0x465e2000, 0xf00afb11, 0xfb18b281, 0xeb02f00a, 
+    0xf01e0040, 0x2100ff97, 0x9a026830, 0xe9cd460b, 0x20000100, 0xf7fb4629, 0x1c64fbc6, 0x2c04b264, 
+    0xb2b9db87, 0xf01d9803, 0x1c6dff7c, 0x2d04b26d, 0xaf77f6ff, 0x9fffe8bd, 0x4ff0e92d, 0xb0a3484e, 
+    0x88006800, 0x0850ea4f, 0x7800484e, 0xd2012850, 0xe0002020, 0x22002010, 0x21014681, 0x4071f04f, 
+    0xff70f01d, 0x9021b240, 0xf7fd2000, 0xf8dffb9d, 0x2600a10c, 0x240046b3, 0xd10242b4, 0x0000f04f, 
+    0xda02e004, 0x0001f104, 0x4620e000, 0xb24242b4, 0x2508d101, 0x2502e000, 0xb000f8cd, 0x3000f8da, 
+    0x46572000, 0xf7fb4631, 0xa801fc51, 0xeb0046ba, 0x1e6d1044, 0x07c6eb00, 0xf8dae00e, 0x46420000, 
+    0xf105fb18, 0xfecff012, 0xdd014548, 0xe0002001, 0x55782000, 0xb26d1e6d, 0xdaee2d00, 0xb2641c64, 
+    0xdbc92c04, 0xb2761c76, 0xdbc42e04, 0xf7ffa801, 0xa801ff0d, 0xff3ef7fd, 0xf7fd9821, 0xf44ffb55, 
+    0xf2400400, 0x462011f4, 0xfefbf7f5, 0xf01d481c, 0x4601ff05, 0xf7f54620, 0x4819fee3, 0xf01d1c80, 
+    0x4601fefd, 0xf7f54620, 0x4815fedb, 0xf01d1d00, 0x4601fef5, 0xf7f54620, 0x4811fed3, 0xf01d1d80, 
+    0x4601feed, 0xf7f54620, 0x480ffecb, 0xfee0f01d, 0x46204601, 0xfec4f7f5, 0x3040480b, 0xfed8f01d, 
+    0x46204601, 0xfebcf7f5, 0x46204908, 0xfeb8f7f5, 0xe8bdb023, 0x00008ff0, 0x00040598, 0x000401e8, 
+    0xf2031000, 0x00040504, 0xf1000008, 0xdcba01f5, 0x23004831, 0xf248220f, 0xb5100100, 0xfedbf01d, 
+    0x7801482e, 0xf7fc2040, 0x2300fead, 0x2201482c, 0x4010e8bd, 0xf01d2102, 0x210fbece, 0x422bf04f, 
+    0x2000f44f, 0xf7f5b508, 0xf7fffeea, 0x2100ffe1, 0xf0004608, 0x2300f895, 0x21014822, 0xf01d461a, 
+    0x2000feba, 0x0200f242, 0x46014603, 0xf0009000, 0xbd08f83b, 0x481a4601, 0x29043022, 0x2905d006, 
+    0x2300d006, 0x21032200, 0xbea5f01d, 0xe7f92303, 0xe7f72302, 0xf7ffb508, 0x2101ffed, 0xf0004608, 
+    0x2301f86f, 0x2102480e, 0xf01d461a, 0x2301fe94, 0x2200480c, 0xf01d4619, 0x2000fe8e, 0x7203f247, 
+    0xf6402317, 0x90004102, 0x1084f240, 0xf80cf000, 0x4008e8bd, 0xbcbef001, 0xf2035026, 0x00040243, 
+    0xf23c8310, 0xf203529a, 0x47f0e92d, 0x460d4c66, 0x461eb281, 0x8020f8dd, 0x46204617, 0xfe51f01d, 
+    0x1ca5b2a9, 0xf01d4628, 0xf104fe4c, 0xb2b90a04, 0xf01d4650, 0xb2b1fe46, 0x46301da6, 0xfe41f01d, 
+    0xfa1f1daf, 0x4638f188, 0xfe3bf01d, 0x2301b672, 0x9154f8df, 0x0800f248, 0x090cf109, 0x220f4641, 
+    0xf01d4648, 0x2300fe48, 0x220f4641, 0xf01d4648, 0xb662fe42, 0x46202100, 0xfe23f01d, 0x46282100, 
+    0xfe1ff01d, 0x46502100, 0xfe1bf01d, 0x46302100, 0xfe17f01d, 0xe8bd4638, 0x210047f0, 0xbe11f01d, 
+    0x4c41b570, 0x460d220a, 0x34104606, 0xf2404603, 0x46204100, 0xfe1ff01d, 0x46332209, 0x2100f240, 
+    0xf01d4620, 0x462bfe18, 0xe8bd4620, 0x22024070, 0xf01d2104, 0xb510be10, 0x23014c33, 0x3410220e, 
+    0x46200399, 0xfe07f01d, 0x46202301, 0x21402206, 0xfe01f01d, 0x482d2301, 0x46192200, 0xfdfbf01d, 
+    0x23014c2b, 0x21102204, 0xf01d4620, 0x2301fdf4, 0x22024620, 0xf01d2104, 0x2301fdee, 0x22034620, 
+    0xf01d2108, 0x2300fde8, 0x22044620, 0xf01d2110, 0x4c20fde2, 0x22042300, 0x46202110, 0xfddbf01d, 
+    0x46202301, 0xe8bd2204, 0x21104010, 0xbdd3f01d, 0x41f0e92d, 0x00064d18, 0xd009461c, 0xd00d2903, 
+    0xd00b2905, 0xd0092904, 0xd0032902, 0xd0012901, 0xe0112300, 0x0204f042, 0x0404f043, 0x210f4f0f, 
+    0x22004613, 0xf01d4638, 0x2204fdb6, 0x21f04623, 0xf01d4638, 0x4633fdb0, 0xe8bd4628, 0x220441f0, 
+    0xf01d2110, 0x0000bda8, 0xf23c8300, 0xf23d0004, 0xf203529a, 0xf2039000, 0xf23c80a0, 0xf23d012a, 
+    0x4cfeb570, 0x2801b398, 0x2802d035, 0x2803d037, 0x2301d01f, 0x22004620, 0xf01d4619, 0xf44ffd8c, 
+    0x21003580, 0xf7fc4628, 0x2301fd5d, 0x21024620, 0xf01d461a, 0x2100fd80, 0xf7fc4628, 0x2301fd53, 
+    0x22024620, 0xf01d2104, 0x2100fd76, 0xf7fc4628, 0x2301fd49, 0x21082203, 0xf01d4620, 0x2300fd6c, 
+    0xe8bd48e7, 0x21014070, 0xf01d461a, 0x2301bd64, 0x46192200, 0x2301e7f0, 0x461a2102, 0x2301e7ec, 
+    0x21042202, 0xb570e7e8, 0xb3904cdc, 0xd0342801, 0xd0362802, 0xf04f2803, 0xd0360300, 0x46202200, 
+    0xf01d2101, 0xf44ffd48, 0x21003580, 0xf7fc4628, 0x2300fd19, 0x22014620, 0xf01d2102, 0x2100fd3c, 
+    0xf7fc4628, 0x2300fd0f, 0x22024620, 0xf01d2104, 0x2100fd32, 0xf7fc4628, 0x2300fd05, 0x22034620, 
+    0xf01d2108, 0x4628fd28, 0x4070e8bd, 0xf7fc2100, 0x2300bcf9, 0x461a2101, 0x2300e009, 0x21022201, 
+    0x2300e005, 0x21042202, 0x2203e001, 0x46202108, 0x4070e8bd, 0xbd0ff01d, 0x2202b510, 0x21044604, 
+    0x48b84603, 0xfd07f01d, 0x220248b7, 0x46232104, 0xfd01f01d, 0x220248b5, 0x46232104, 0xfcfbf01d, 
+    0x46232202, 0x4010e8bd, 0x210448b1, 0xbcf3f01d, 0x4604b510, 0x48ab4603, 0x21102204, 0xf01d380c, 
+    0x48a9fcea, 0x21102204, 0x380c4623, 0xfce3f01d, 0x220448a6, 0x46232110, 0xf01d380c, 0x48a4fcdc, 
+    0x21102204, 0xe8bd4623, 0x380c4010, 0xbcd3f01d, 0x4605b570, 0x489b4603, 0x2400f240, 0x46212209, 
+    0xf01d3814, 0x4898fcc8, 0x462b2209, 0x38144621, 0xfcc1f01d, 0x22094895, 0x4621462b, 0xf01d3814, 
+    0x4893fcba, 0x4621462b, 0x4070e8bd, 0x38142209, 0xbcb1f01d, 0x2200b510, 0x21014604, 0x48894603, 
+    0xfca9f01d, 0x22004888, 0x46232101, 0xfca3f01d, 0x22004886, 0x46232101, 0xfc9df01d, 0x46232200, 
+    0x4010e8bd, 0x21014882, 0xbc95f01d, 0xf240b570, 0x460514c0, 0x46032206, 0x4621487a, 0xfc8bf01d, 
+    0x22064879, 0x4621462b, 0xfc85f01d, 0x22064877, 0x4621462b, 0xfc7ff01d, 0x4621462b, 0x4070e8bd, 
+    0x22064873, 0xbc77f01d, 0x2201b510, 0x21024604, 0x486c4603, 0xfc6ff01d, 0x2201486b, 0x46232102, 
+    0xfc69f01d, 0x22014869, 0x46232102, 0xfc63f01d, 0x46232201, 0x4010e8bd, 0x21024865, 0xbc5bf01d, 
+    0x4604b510, 0x485f4603, 0x21012200, 0xf01d3824, 0x485dfc52, 0x21012200, 0x38244623, 0xfc4bf01d, 
+    0x2200485a, 0x46232101, 0xf01d3824, 0x4858fc44, 0x21012200, 0xe8bd4623, 0x38244010, 0xbc3bf01d, 
+    0x4604b510, 0x484f4603, 0x21702204, 0xf01d3820, 0x484dfc32, 0x21702204, 0x38204623, 0xfc2bf01d, 
+    0x2204484a, 0x46232170, 0xf01d3820, 0x4848fc24, 0x21702204, 0xe8bd4623, 0x38204010, 0xbc1bf01d, 
+    0x4c3eb570, 0x21012200, 0x1ca44605, 0x46204603, 0xfc11f01d, 0x462b2201, 0x46202102, 0xfc0bf01d, 
+    0x462b2202, 0x46202104, 0xfc05f01d, 0x4620462b, 0x4070e8bd, 0x21082203, 0xbbfdf01d, 0x2201b510, 
+    0x21064604, 0x48334603, 0xfbf5f01d, 0x22014832, 0x46232106, 0xfbeff01d, 0x22014830, 0x46232106, 
+    0xfbe9f01d, 0x46232201, 0x4010e8bd, 0x2106482c, 0xbbe1f01d, 0xb283b570, 0x48224604, 0x75e0f641, 
+    0x46292205, 0xf01d380c, 0x481ffbd6, 0x2205b2a3, 0x380c4629, 0xfbcff01d, 0xb2a3481c, 0x46292205, 
+    0xf01d380c, 0xb2a3fbc8, 0x46294819, 0x4070e8bd, 0x380c2205, 0xbbbff01d, 0x4e16b570, 0x0503f000, 
+    0x0482f3c0, 0x46233682, 0x46302202, 0xf01d211c, 0x2200fbb2, 0x2103462b, 0xf01d4630, 0x4e0efbac, 
+    0x211c2202, 0x36824623, 0xf01d4630, 0x2200fba4, 0x2103462b, 0xf01d4630, 0xe013fb9e, 0xf2034222, 
+    0xf20305cc, 0xf203c624, 0xf203ce24, 0xf203d624, 0xf203de24, 0xf203c186, 0xf203c986, 0xf203d186, 
+    0xf203d986, 0x22024eff, 0x4623211c, 0xf01d4630, 0x2200fb82, 0x2103462b, 0xf01d4630, 0x4623fb7c, 
+    0x22024cf9, 0x4620211c, 0xfb75f01d, 0x4620462b, 0x4070e8bd, 0x21032200, 0xbb6df01d, 0x2203b510, 
+    0x21384604, 0x48f14603, 0xfb65f01d, 0x220348f0, 0x46232138, 0xfb5ff01d, 0x220348ea, 0x46232138, 
+    0xf01d38fc, 0x48e8fb58, 0x21382203, 0xe8bd4623, 0x38fc4010, 0xbb4ff01d, 0x4ff7e92d, 0xa394f8df, 
+    0x0601f002, 0x09c0f3c2, 0xf3c2460c, 0x9b000880, 0x0740f3c2, 0x0100f643, 0x4650220b, 0xfb3bf01d, 
+    0x0503f004, 0x0100f24c, 0x462b220e, 0xf01d4650, 0xf3c4fb32, 0x22000380, 0x2101461c, 0x0002f10a, 
+    0xfb29f01d, 0x4b00f240, 0x23004650, 0x220a4659, 0xfb21f01d, 0x46592301, 0x4650220a, 0xfb1bf01d, 
+    0x46592300, 0x4650220a, 0xfb15f01d, 0xa328f8df, 0x9b00220b, 0x0100f643, 0xf01d4650, 0x220efb0c, 
+    0xf24c462b, 0x46500100, 0xfb05f01d, 0x46232200, 0xf10a2101, 0xf01d0002, 0x2300fafe, 0x220a4659, 
+    0xf01d4650, 0x2301faf8, 0x220a4659, 0xf01d4650, 0x2300faf2, 0x220a4659, 0xf01d4650, 0xf8dffaec, 
+    0x220ba2dc, 0xf6439b00, 0x46500100, 0xfae3f01d, 0x462b220e, 0x0100f24c, 0xf01d4650, 0x2200fadc, 
+    0x21014623, 0x0002f10a, 0xfad5f01d, 0x46592300, 0x4650220a, 0xfacff01d, 0x46592301, 0x4650220a, 
+    0xfac9f01d, 0x46592300, 0x4650220a, 0xfac3f01d, 0xa28cf8df, 0x9b00220b, 0x0100f643, 0xf01d4650, 
+    0x220efaba, 0xf24c462b, 0x46500100, 0xfab3f01d, 0x46232200, 0xf10a2101, 0xf01d0002, 0x2300faac, 
+    0x220a4659, 0xf01d4650, 0x2301faa6, 0x220a4659, 0xf01d4650, 0x2300faa0, 0x220a4659, 0xf01d4650, 
+    0x4c8cfa9a, 0x21012200, 0x3408463b, 0xf01d4620, 0x2201fa92, 0x2102464b, 0xf01d4620, 0x2202fa8c, 
+    0x21044643, 0xf01d4620, 0x2203fa86, 0x21084633, 0xf01d4620, 0x4c80fa80, 0x21012200, 0x3408463b, 
+    0xf01d4620, 0x2201fa78, 0x2102464b, 0xf01d4620, 0x2202fa72, 0x21044643, 0xf01d4620, 0x2203fa6c, 
+    0x21084633, 0xf01d4620, 0x4c74fa66, 0x21012200, 0x3408463b, 0xf01d4620, 0x2201fa5e, 0x2102464b, 
+    0xf01d4620, 0x2202fa58, 0x21044643, 0xf01d4620, 0x2203fa52, 0x21084633, 0xf01d4620, 0x4c68fa4c, 
+    0x21012200, 0x3408463b, 0xf01d4620, 0x2201fa44, 0x2102464b, 0xf01d4620, 0x2202fa3e, 0x21044643, 
+    0xf01d4620, 0xb003fa38, 0x46204633, 0xe8bd2203, 0x21084ff0, 0xba2ff01d, 0xb283b570, 0x48534604, 
+    0x21802207, 0xf01d307c, 0x4851fa26, 0x2207b2a3, 0x307c2180, 0xfa1ff01d, 0xb2a3484a, 0x21802207, 
+    0xf01d3880, 0x4848fa18, 0x2207b2a3, 0x38802180, 0xfa11f01d, 0xf2404845, 0xb2a34500, 0x220a4629, 
+    0xf01d307e, 0x4842fa08, 0x220ab2a3, 0x307e4629, 0xfa01f01d, 0xb2a3483b, 0x4629220a, 0xf01d387e, 
+    0xb2a3f9fa, 0x46294838, 0x4070e8bd, 0x387e220a, 0xb9f1f01d, 0x41f0e92d, 0x22054c34, 0x46802120, 
+    0x4603347a, 0xf01d4620, 0x4d31f9e6, 0x21202205, 0x357a4643, 0xf01d4628, 0x4e2af9de, 0x21202205, 
+    0x3e824643, 0xf01d4630, 0x4f27f9d6, 0x21202205, 0x3f824643, 0xf01d4638, 0x2204f9ce, 0x21104643, 
+    0xf01d4620, 0x2204f9c8, 0x21104643, 0xf01d4628, 0x2204f9c2, 0x21104643, 0xf01d4630, 0x2204f9bc, 
+    0x21104643, 0xf01d4638, 0xe8bdf9b6, 0x210041f0, 0x1000f240, 0xb986f7fc, 0x41f0e92d, 0x22064c13, 
+    0x46802140, 0x4603347e, 0xf01d4620, 0x4d10f9a4, 0x21402206, 0x357e4643, 0xf01d4628, 0x4e09f99c, 
+    0x21402206, 0x3e7e4643, 0xf01d4630, 0x4f06f994, 0x21402206, 0x3f7e4643, 0xf01d4638, 0x2205f98c, 
+    0xe00f4643, 0xf203d208, 0xf203da08, 0xf203c10c, 0xf203c90c, 0xf203c610, 0xf203ce10, 0xf203d610, 
+    0xf203de10, 0x46202120, 0xf975f01d, 0x46432205, 0x46282120, 0xf96ff01d, 0x46432205, 0x46302120, 
+    0xf969f01d, 0x46432205, 0x46382120, 0xf963f01d, 0x41f0e8bd, 0xf2412100, 0xf7fc0000, 0xb510b933, 
+    0x46042204, 0x46032130, 0xf01d48fe, 0x48fef954, 0x21302204, 0xf01d4623, 0x48fcf94e, 0x21302204, 
+    0xf01d4623, 0x2204f948, 0xe8bd4623, 0x48f84010, 0xf01d2130, 0xb570b940, 0x14c0f240, 0x22064605, 
+    0x48f44603, 0xf01d4621, 0x48f3f936, 0x462b2206, 0xf01d4621, 0x48f1f930, 0x462b2206, 0xf01d4621, 
+    0x462bf92a, 0xe8bd4621, 0x48ed4070, 0xf01d2206, 0xe92db922, 0x4de75fff, 0x0400f641, 0x46894617, 
+    0x46803576, 0x4603220b, 0xba0fe9dd, 0x46284621, 0xf911f01d, 0x464b2208, 0x01564628, 0xf01d4631, 
+    0x2207f90a, 0x2180463b, 0xf01d4628, 0x9b03f904, 0x21602205, 0xf01d4628, 0x9b0ef8fe, 0x21082203, 
+    0xf01d4628, 0x2202f8f8, 0x2104465b, 0xf01d4628, 0x2200f8f2, 0x21034653, 0xf01d4628, 0x4dcef8ec, 
+    0x4643220b, 0x35764621, 0xf01d4628, 0x2208f8e4, 0x4631464b, 0xf01d4628, 0x2207f8de, 0x2180463b, 
+    0xf01d4628, 0x9b03f8d8, 0x21602205, 0xf01d4628, 0x9b0ef8d2, 0x21082203, 0xf01d4628, 0x2202f8cc, 
+    0x2104465b, 0xf01d4628, 0x2200f8c6, 0x21034653, 0xf01d4628, 0x4db9f8c0, 0x4643220b, 0x35764621, 
+    0xf01d4628, 0x2208f8b8, 0x4631464b, 0xf01d4628, 0x2207f8b2, 0x2180463b, 0xf01d4628, 0x9b03f8ac, 
+    0x21602205, 0xf01d4628, 0x9b0ef8a6, 0x21082203, 0xf01d4628, 0x2202f8a0, 0x2104465b, 0xf01d4628, 
+    0x2200f89a, 0x21034653, 0xf01d4628, 0x4621f894, 0x220b4ca3, 0x34764643, 0xf01d4620, 0x2208f88c, 
+    0x4631464b, 0xf01d4620, 0x2207f886, 0x2180463b, 0xf01d4620, 0x9b03f880, 0x21602205, 0xf01d4620, 
+    0x9b0ef87a, 0x21082203, 0xf01d4620, 0x2202f874, 0x2104465b, 0xf01d4620, 0xb004f86e, 0x46204653, 
+    0xe8bd2200, 0x21035ff0, 0xb865f01d, 0x41f0e92d, 0xf2444d88, 0x220e0400, 0x3580460e, 0x46034607, 
+    0x46284621, 0xf857f01d, 0x46332206, 0x46282140, 0xf851f01d, 0x220e4d80, 0x4621463b, 0x46283580, 
+    0xf849f01d, 0x46332206, 0x46282140, 0xf843f01d, 0x220e4d7a, 0x4621463b, 0x46283580, 0xf83bf01d, 
+    0x46332206, 0x46282140, 0xf835f01d, 0x4c744621, 0x463b220e, 0x46203480, 0xf82df01d, 0x46204633, 
+    0x41f0e8bd, 0x21402206, 0xb825f01d, 0x43fee92d, 0x486c4686, 0x468c2600, 0x0f03f1be, 0x46324637, 
+    0xf8804633, 0x46b0e000, 0x46344867, 0x70014635, 0x46304631, 0xf1bed00f, 0xd00c0f05, 0x0f04f1be, 
+    0xf1bed009, 0xd0390f02, 0x0f00f1be, 0xf1bed036, 0xd0330f01, 0xf1bce038, 0xd00f0f01, 0x0f02f1bc, 
+    0xf1bcd010, 0xd00f0f03, 0x0f04f1bc, 0xf1bcd011, 0xd0140f05, 0x0f06f1bc, 0xe025d018, 0x23022201, 
+    0xe0214690, 0xe7f92701, 0x20032601, 0x463146b0, 0x2701e00a, 0x463b463a, 0x46384639, 0x2601e004, 
+    0x46322002, 0x46314633, 0xe00d2401, 0x22012602, 0x46134630, 0x46144611, 0xe0054615, 0x46372601, 
+    0x46334632, 0x46304631, 0x8000f8cd, 0x1001e9cd, 0x46304639, 0xfe9df7ff, 0x4629b003, 0xe8bd4620, 
+    0xe75343f0, 0x47f0e92d, 0xea252501, 0x43950401, 0xd16b2801, 0x80bcf8df, 0xf1082b00, 0xd04e087e, 
+    0x367e4e2d, 0xd06b2b01, 0x377e4f2c, 0xd0732b02, 0x90acf8df, 0xf1092b03, 0xd031097e, 0x46232205, 
+    0x46402120, 0xff97f01c, 0x462b2206, 0x46402140, 0xff91f01c, 0x3800f44f, 0x46402100, 0xff62f7fb, 
+    0x46232205, 0x46302120, 0xff85f01c, 0x462b2206, 0x46302140, 0xff7ff01c, 0x46402100, 0xff52f7fb, 
+    0x46232205, 0x46382120, 0xff75f01c, 0x462b2206, 0x46382140, 0xff6ff01c, 0x46402100, 0xff42f7fb, 
+    0x46232205, 0x464c2120, 0xf01c4648, 0x2206ff64, 0x2140462b, 0xe8bd4620, 0xf01c47f0, 0x2205bf5c, 
+    0xe0144623, 0xf203c600, 0xf203ce00, 0xf203d600, 0xf203de00, 0xf203c10c, 0xf203c90c, 0xf203d10c, 
+    0xf203d90c, 0x00040302, 0x00040303, 0x2120e01f, 0xf01c4640, 0x2206ff40, 0x2140462b, 0xe7da4640, 
+    0x46232205, 0x46302120, 0xff35f01c, 0x462b2206, 0x46302140, 0xe7ffe7cf, 0x46232205, 0x46382120, 
+    0xff29f01c, 0x462b2206, 0x46382140, 0xe8bde7c3, 0xb51087f0, 0x46042200, 0x46032103, 0xf01c48ba, 
+    0x48baff1a, 0x21032200, 0xf01c4623, 0x48b8ff14, 0x21032200, 0xf01c4623, 0x2200ff0e, 0xe8bd4623, 
+    0x48b44010, 0xf01c2103, 0x2208bf06, 0xb5704603, 0x46050154, 0x462148b0, 0xfefdf01c, 0x220848af, 
+    0x4621462b, 0xfef7f01c, 0x220848ad, 0x4621462b, 0xfef1f01c, 0x4621462b, 0x4070e8bd, 0x220848a9, 
+    0xbee9f01c, 0xb283b510, 0x489f4604, 0x21042202, 0xf01c3880, 0x489dfee0, 0x2202b2a3, 0x38802104, 
+    0xfed9f01c, 0xb2a3489a, 0x21042202, 0xf01c3880, 0x4898fed2, 0x2202b2a3, 0xe8bd2104, 0x38804010, 
+    0xbec9f01c, 0x41f0e92d, 0x23004c93, 0x46072206, 0x21403c42, 0xf01c4620, 0x4d90febe, 0x22062300, 
+    0x21403d42, 0xf01c4628, 0x4e8dfeb6, 0x22062300, 0x21403e42, 0xf01c4630, 0xf8dffeae, 0x23008228, 
+    0xf1a82206, 0x21400842, 0xf01c4640, 0x2207fea4, 0x2180463b, 0xf01c4620, 0x2207fe9e, 0x2180463b, 
+    0xf01c4628, 0x2207fe98, 0x2180463b, 0xf01c4630, 0x2207fe92, 0x2180463b, 0xf01c4640, 0x2208fe8c, 
+    0x23004620, 0x46390157, 0xfe85f01c, 0x46392301, 0x46202208, 0xfe7ff01c, 0x46392300, 0x46282208, 
+    0xfe79f01c, 0x46392301, 0x46282208, 0xfe73f01c, 0x46392300, 0x46302208, 0xfe6df01c, 0x46392301, 
+    0x46302208, 0xfe67f01c, 0x46392300, 0x46402208, 0xfe61f01c, 0x46404639, 0x41f0e8bd, 0x22082301, 
+    0xbe59f01c, 0x47f0e92d, 0x4e5b4d5f, 0xf8df4f5b, 0x361c9170, 0xa16cf8df, 0x7828371c, 0x091cf109, 
+    0x0a1cf10a, 0x7868b1a8, 0x78a8b3b8, 0x4650b3b0, 0xfe24f01c, 0x0006f000, 0xd04c2806, 0x0800f04f, 
+    0xf01c4650, 0xf000fe1b, 0x28050005, 0x2400d00f, 0x4630e00e, 0xfe12f01c, 0x0006f000, 0xd0032806, 
+    0x0800f04f, 0xe7ec4630, 0x0801f04f, 0x2401e7fa, 0xea447828, 0x28010408, 0x7868d030, 0xd03a2801, 
+    0x280178a8, 0x4656d049, 0xf01c4650, 0xf000fdf7, 0x28060006, 0x2500d044, 0xe000e022, 0x4638e00d, 
+    0xfdecf01c, 0x0006f000, 0xd0032806, 0x0800f04f, 0xe7c64638, 0x0801f04f, 0x4648e7fa, 0xfddef01c, 
+    0x0006f000, 0xd0032806, 0x0800f04f, 0xe7b84648, 0x0801f04f, 0xf04fe7fa, 0xe7b10801, 0xe7d44630, 
+    0xe0114630, 0xe0002001, 0x43282000, 0x28024420, 0x2001db18, 0x4638e6bb, 0xfdc0f01c, 0x0006f000, 
+    0xd0082806, 0x46382500, 0xfdb8f01c, 0x0005f000, 0xd1e92805, 0x2501e7e6, 0x464ee7f5, 0xe7b44648, 
+    0xe7dd2501, 0xe6a22000, 0x4604b510, 0x480e4603, 0x21802207, 0xf01c1f80, 0x480cfdbe, 0x21802207, 
+    0x1f804623, 0xfdb7f01c, 0x22074809, 0x46232180, 0xf01c1f80, 0x4807fdb0, 0x21802207, 0xe8bd4623, 
+    0x1f804010, 0xbda7f01c, 0xf203c18c, 0xf203c98c, 0xf203d18c, 0xf203d98c, 0xf203c642, 0xf203ce42, 
+    0xf203d642, 0xf203de42, 0x00040520, 0x5ff0e92d, 0x20004683, 0xf974f7ff, 0x230448fe, 0x210e2201, 
+    0xfd89f01c, 0x230448fc, 0x210e2201, 0xfd83f01c, 0x230448fa, 0x210e2201, 0xfd7df01c, 0x230448f8, 
+    0x210e2201, 0xfd77f01c, 0x23014df6, 0x21402206, 0xf01c4628, 0x2208fd70, 0x23004628, 0x46210154, 
+    0xfd69f01c, 0x23004df0, 0x00612209, 0xf01c4628, 0x2300fd62, 0x22084621, 0xf01c4628, 0x2300fd5c, 
+    0x22074628, 0xf01c2180, 0x2300fd56, 0x22064628, 0xf01c2140, 0x4ee5fd50, 0x22072300, 0x46302180, 
+    0xfd49f01c, 0x46212300, 0x46302208, 0xfd43f01c, 0x46302301, 0x21402206, 0xfd3df01c, 0x46302301, 
+    0x21082203, 0xfd37f01c, 0x46302300, 0x21022201, 0xfd31f01c, 0x23014ed3, 0x46192200, 0x46303e0e, 
+    0xfd29f01c, 0x833cf8df, 0x220f2301, 0xf1a803df, 0x46390802, 0xf01c4640, 0xf8dffd1e, 0x2301a334, 
+    0x46212208, 0xf01c4650, 0x2300fd16, 0x22034650, 0xf01c2108, 0x2301fd10, 0x22034630, 0xf01c2108, 
+    0xf1a8fd0a, 0x210f0904, 0xf01c4648, 0x2002fcea, 0xfddff7ff, 0xf7ff2001, 0x2301f8a3, 0x22054628, 
+    0xf01c2120, 0x2301fcf8, 0x22044628, 0xf01c2110, 0x2301fcf2, 0x22034628, 0xf01c2108, 0x2301fcec, 
+    0x22024628, 0xf01c2104, 0x2100fce6, 0xf01c4648, 0x2300fcc8, 0x22034630, 0xf01c2108, 0x2300fcdc, 
+    0x220f4639, 0xf01c4640, 0x2300fcd6, 0x21014630, 0xf01c461a, 0x2301fcd0, 0x22074628, 0xf01c2180, 
+    0x2301fcca, 0x22064628, 0xf01c2140, 0x2300fcc4, 0x22084621, 0xf01c4650, 0x489efcbe, 0x46587801, 
+    0xfc94f7ff, 0xf7ff2000, 0x4899fdb0, 0x5468f64a, 0x30084621, 0xfc95f01c, 0x46214895, 0xf01c300a, 
+    0x4893fc90, 0x300c2100, 0xfc8bf01c, 0xf00b2004, 0x2100fe28, 0xf00c2001, 0x4650fcf7, 0x5ff0e8bd, 
+    0x22032301, 0xf01c2108, 0xe92dbc96, 0x46045ff0, 0xf7ff2000, 0x2c04f875, 0x2c05d004, 0x2200d002, 
+    0xe0b64611, 0x78004884, 0xd1012801, 0xd07d2c05, 0x220b2100, 0xf7ff4608, 0x4d7af92f, 0x22062300, 
+    0x46282140, 0xfc77f01c, 0x1b00f240, 0x23014628, 0x22084659, 0xfc6ff01c, 0xa1ccf8df, 0x2500f240, 
+    0x46292300, 0x46502209, 0xfc65f01c, 0x46592300, 0x46502208, 0xfc5ff01c, 0x46502300, 0x21802207, 
+    0xfc59f01c, 0x46502300, 0x21402206, 0xfc53f01c, 0x23004e66, 0x21802207, 0xf01c4630, 0x2300fc4c, 
+    0x22084659, 0xf01c4630, 0x2300fc46, 0x22064630, 0xf01c2140, 0x2300fc40, 0x22034630, 0xf01c2108, 
+    0x2300fc3a, 0x22014630, 0xf01c2102, 0x4e55fc34, 0x22002301, 0x3e0e4619, 0xf01c4630, 0xf8dffc2c, 
+    0xf2489144, 0x23010800, 0xf1a94641, 0x220f0902, 0xf01c4648, 0xf1a9fc20, 0x210f0704, 0xf01c4638, 
+    0x2000fc00, 0xfcf5f7ff, 0xf7fe2000, 0x2300ffb9, 0x22054650, 0xf01c2120, 0x2300fc0e, 0x22044650, 
+    0xf01c2110, 0x2300fc08, 0xe0002203, 0x2108e02f, 0xf01c4650, 0x2300fc00, 0x22024650, 0xf01c2104, 
+    0x2100fbfa, 0xf01c4638, 0x2300fbdc, 0x220f4641, 0xf01c4648, 0x2300fbf0, 0x21014630, 0xf01c461a, 
+    0x2301fbea, 0x22094629, 0xf01c4650, 0x2301fbe4, 0x22084659, 0xf01c4650, 0x482efbde, 0x46207801, 
+    0xfbb4f7ff, 0x5ff0e8bd, 0xf7ff2001, 0x220bbcce, 0x20062105, 0xb5f8e74f, 0x46042803, 0x2c04d028, 
+    0x2c05d026, 0x2500d024, 0xd0492c02, 0xd0472c01, 0xd0792c06, 0xd0782c07, 0xd0772c08, 0xf7fe2000, 
+    0xb2e0ffd9, 0xfe22f7ff, 0x23042101, 0x22004608, 0xfbf8f7ff, 0x78004819, 0xd0682801, 0x200a2104, 
+    0xfb64f00f, 0x95002300, 0x46192201, 0xe0ee4618, 0xf7ffb2c0, 0x2030ff0a, 0xffbcf7fe, 0x20062100, 
+    0xfb54f00f, 0x23042201, 0x46104611, 0xfbdaf7ff, 0xe0df2001, 0xf203c602, 0xf203ce02, 0xf203d602, 
+    0xf203de02, 0xf23c830e, 0xf23c804a, 0xf2034228, 0xf2039000, 0x000402f4, 0x000402b2, 0x000404fc, 
+    0x22014efa, 0x46302102, 0xfb83f01c, 0x2c02b108, 0xb2e0d102, 0xfddaf7ff, 0x20062100, 0xfb26f00f, 
+    0xf04f2c02, 0xd0230100, 0xf00f2005, 0x2300fb1f, 0x22019500, 0x46104619, 0xfa70f00f, 0x20012102, 
+    0xfb34f7ff, 0x48ea2300, 0x461a2101, 0xfb53f01c, 0xf7fe2001, 0x2201fe41, 0x21024630, 0xfb59f01c, 
+    0x2c02b1c8, 0xe01cd017, 0xe037e02a, 0xe07fe052, 0xf00f2002, 0x2300fafb, 0x22029500, 0x21014618, 
+    0xfa4cf00f, 0x780148db, 0xf7ff2002, 0x2010fb0f, 0xff50f7fe, 0x2201e7d6, 0x46112304, 0xf7ff4610, 
+    0x2201fb71, 0x21024630, 0xfb33f01c, 0xd0702801, 0x46302202, 0xf01c2104, 0x2801fb2c, 0xbdf8d069, 
+    0x23042200, 0x20014611, 0xfb5cf7ff, 0xf7fe2004, 0xe8bdfd77, 0x200140f8, 0xbef2f7fe, 0x23014cc6, 
+    0x21802207, 0xf01c4620, 0x2301fb06, 0x22094620, 0xf01c0259, 0x2208fb00, 0x23014620, 0xf01c0151, 
+    0x2300fafa, 0x22044620, 0xf01c2110, 0x2304faf4, 0xe01a2200, 0x78204cb9, 0xfe57f7ff, 0xf7fe2030, 
+    0x2100ff09, 0xf00f2006, 0x48b5faa1, 0xb19b7803, 0x21009500, 0x20007822, 0xf9f0f00f, 0xf04f48b1, 
+    0x78000304, 0xd0102803, 0x21012201, 0x2001b001, 0x40f0e8bd, 0xbb16f7ff, 0x462b48ab, 0x95007800, 
+    0xd1e62801, 0x21017822, 0x2200e7e5, 0xe7ed4611, 0x46082100, 0xfa7af00f, 0xf04f48a4, 0xf04f0201, 
+    0x46110300, 0x95007800, 0xd0072803, 0xf00f2001, 0x2000f9c5, 0x40f8e8bd, 0xbce6f7ff, 0xe7f62002, 
+    0xf04f2109, 0xf44f422b, 0xb5102000, 0xfac7f7f4, 0xf2402001, 0xf7f411f4, 0x4895fa74, 0x20017801, 
+    0xfa5ef7f4, 0x20014993, 0xfa5af7f4, 0x23004892, 0xf2402208, 0xf01c3100, 0x4990fa8e, 0x4a902000, 
+    0x808880c8, 0x80088048, 0x498e4885, 0x488b7803, 0xfa5af7fd, 0xf44f2172, 0xf7f40080, 0x2000fa7a, 
+    0xfda6f7fe, 0x48882300, 0x461a210f, 0xfa73f01c, 0xf7fe2000, 0x2004fd7d, 0xfd15f7fe, 0xf7fe2001, 
+    0x2100fd5b, 0xf7fb2040, 0xe8bdfa3d, 0x20004010, 0xbd52f7fe, 0xf64b4870, 0xb5f831b5, 0xf01c3070, 
+    0x2301fa40, 0x220e4879, 0x4621039c, 0xfa53f01c, 0x48692301, 0x46192200, 0xfa4df01c, 0x23042200, 
+    0x20014611, 0xfa8ef7ff, 0xff9af7ff, 0x607ff46f, 0x0395f647, 0x0202f247, 0x0102f640, 0xf2439000, 
+    0xf7fe1045, 0x486afbc1, 0xf01c2100, 0x485bfa1a, 0x78004a58, 0xf7ff7811, 0x2003fa09, 0xfdf0f7fe, 
+    0xf00c2000, 0x2007fab8, 0xfaeff00c, 0xf00c2001, 0x2001fb0e, 0xfe22f7fe, 0xfb6ef00b, 0xf7fe2001, 
+    0x2001ffeb, 0xfb2ef7ff, 0x23034857, 0x21c02206, 0xf01c1f00, 0x2001fa10, 0xfc46f7ff, 0xf7ff2001, 
+    0x2000f819, 0xf858f7ff, 0xf7ff2001, 0x2000f855, 0xf852f7ff, 0xf7ff2000, 0x00e6f80d, 0x15f4f240, 
+    0x46304629, 0xf9cdf7f4, 0x7100f241, 0xf7f44630, 0x4f40f9b7, 0x46394630, 0xf9b2f7f4, 0xf7ff2003, 
+    0x2005fe1a, 0xfe7af7fe, 0xf7ff2000, 0x2001f8a4, 0xf89af00d, 0xf7ff2000, 0x2003fe0e, 0xfe6ef7fe, 
+    0xf7ff2007, 0x4629f898, 0xf7f44630, 0xf241f9aa, 0x46307101, 0xf994f7f4, 0x46304639, 0xf990f7f4, 
+    0x4621b001, 0x23004830, 0xe8bd220e, 0x1d8040f0, 0xb9c1f01c, 0x4c1eb570, 0x21012300, 0x4620461a, 
+    0xf9b9f01c, 0xf01c1fa0, 0x1ea5f999, 0x46282302, 0x21072200, 0xf9aff01c, 0x46282302, 0x21702204, 
+    0xf9a9f01c, 0xf2402302, 0x22087100, 0xf01c4628, 0x2302f9a2, 0x0100f247, 0x4628220c, 0xf99bf01c, 
+    0x1f202100, 0xf97df01c, 0x46202301, 0x46192200, 0xf991f01c, 0xf7fe2001, 0x2100fc7f, 0xf7fb2040, 
+    0xe8bdf961, 0x20004070, 0xbc76f7fe, 0xf38f007c, 0xf20305cc, 0x000402f4, 0xf23c804a, 0x00040242, 
+    0x0004057b, 0x00040234, 0x000404f6, 0x000404fd, 0x00040502, 0xdcba01f5, 0xf2035022, 0x00040538, 
+    0x00040520, 0x0004054e, 0xf203e804, 0xf23c830c, 0xf2034224, 0x41f0e92d, 0x461d4c4e, 0x4616b283, 
+    0x460f2206, 0x462021c0, 0xf955f01c, 0x4620b2bb, 0x21302204, 0xf94ff01c, 0x4620b2b3, 0x210c2202, 
+    0xf949f01c, 0x4620b2ab, 0x41f0e8bd, 0x21032200, 0xb941f01c, 0x41f0e92d, 0x46144698, 0x460e2301, 
+    0x46072102, 0x461a483c, 0xf935f01c, 0xf2412100, 0xf7fb0000, 0x4d39f907, 0x220a2301, 0x46280299, 
+    0xf929f01c, 0x463b2204, 0x11f0f240, 0xf01c4628, 0x2201f922, 0x21024633, 0xf01c4628, 0x1d2ff91c, 
+    0x0100f640, 0x0600f24c, 0x2c01b134, 0x2c02d006, 0x2c03d004, 0xe013d009, 0xe0002300, 0x46282301, 
+    0xf01c220b, 0x2300f908, 0x2300e005, 0x220b4628, 0xf901f01c, 0x46312301, 0x4638220e, 0xf8fbf01c, 
+    0x4643220f, 0x0100f248, 0xf01c4628, 0x4628f8f4, 0x41f0e8bd, 0x22022301, 0xf01c2104, 0x4817b8ec, 
+    0xb5102100, 0xf01c3016, 0x4814f8cc, 0x30182100, 0xf8c7f01c, 0x21004811, 0xf01c3012, 0x480ff8c2, 
+    0x30142100, 0xf8bdf01c, 0x2100480c, 0xf01c301a, 0x480af8b8, 0x301c2100, 0xf8b3f01c, 0x21004807, 
+    0xf01c301e, 0x4805f8ae, 0xe8bd2100, 0x30204010, 0xb8a7f01c, 0xf2030484, 0xf23c8310, 0xf2036100, 
+    0x2801b158, 0x2802d00f, 0x2803d013, 0x2301d117, 0x21024885, 0xf01c461a, 0x4883b8ae, 0x21022301, 
+    0x3860461a, 0x4880e7f7, 0x21022301, 0x3840461a, 0x487de7f1, 0x21022301, 0x3820461a, 0x4770e7eb, 
+    0x4879b281, 0xf01c38e0, 0xb510b87c, 0x23014c76, 0x46192200, 0x46203ce0, 0xf88df01c, 0x46202301, 
+    0x461a2102, 0xf887f01c, 0x46202301, 0x21042202, 0xf881f01c, 0x46202301, 0xe8bd2203, 0x21084010, 
+    0xb879f01c, 0x4868b283, 0x21c02206, 0xf01c38de, 0xb158b872, 0xd00f2801, 0xd0132802, 0xd1172803, 
+    0x48612301, 0x46192200, 0xb865f01c, 0x2301485e, 0x46192200, 0xe7f73860, 0x2301485b, 0x46192200, 
+    0xe7f13840, 0x23014858, 0x46192200, 0xe7eb3820, 0xb5704770, 0x36fff240, 0x1c754614, 0x2801b1a8, 
+    0x2802d019, 0x2803d01d, 0xb28bd121, 0x4e4e4631, 0x360e2200, 0xf01c4630, 0xb2a3f83e, 0x46304629, 
+    0x4070e8bd, 0xf01c220a, 0xb28bb836, 0x4e464631, 0x3e522200, 0xb28be7ee, 0x4e434631, 0x3e322200, 
+    0xb28be7e8, 0x4e404631, 0x3e122200, 0xbd70e7e2, 0x483db283, 0x21032200, 0xf01c3880, 0xb283b81c, 
+    0xb5104839, 0x460c2200, 0xf64738d8, 0xf01c71ff, 0x4835f812, 0xe8bdb2a1, 0x38d64010, 0xbff1f01b, 
+    0x4d31b570, 0x220f2301, 0x3de003dc, 0x46284621, 0xf801f01c, 0x46284621, 0x4070e8bd, 0x220f2300, 
+    0xbff9f01b, 0x41f0e92d, 0x4603461f, 0x46144826, 0x22099e06, 0x460d387c, 0x2100f240, 0xffebf01b, 
+    0x22074821, 0x462b2180, 0xf01b385e, 0x481effe4, 0x21802207, 0x383e4623, 0xffddf01b, 0x2207481a, 
+    0x463b2180, 0xf01b381e, 0x4633ffd6, 0xe8bd4816, 0x220741f0, 0x1c802180, 0xbfcdf01b, 0xf64fb430, 
+    0xb1680400, 0xd0112801, 0xd0152802, 0xd1192803, 0x220b480d, 0x4621460b, 0xbc30300e, 0xbfbbf01b, 
+    0x220b4809, 0x4621460b, 0xe7f63852, 0x220b4806, 0x4621460b, 0xe7f03832, 0x220b4803, 0x4621460b, 
+    0xe7ea3812, 0x4770bc30, 0xf20308e0, 0x2100b51c, 0x91019100, 0x1010f82d, 0x1000f8bd, 0xf01b48fa, 
+    0x48f9ff80, 0x1002f8bd, 0xf01b3020, 0x48f6ff7a, 0x1004f8bd, 0xf01b3040, 0x48f3ff74, 0x1006f8bd, 
+    0xf01b3060, 0xbd1cff6e, 0x220448f0, 0x4ceeb510, 0xf9902130, 0x3c740000, 0x4620b283, 0xff7bf01b, 
+    0x46202304, 0x210f2200, 0xff75f01b, 0x46202301, 0x21402206, 0xff6ff01b, 0xf01b1ca0, 0x4604ff4f, 
+    0x387048e1, 0xff4af01b, 0x4000eb04, 0xbd101040, 0xb50848df, 0xf2447801, 0xf7fa0000, 0x48daff33, 
+    0x01c9f640, 0xf01b387e, 0x48d7ff3c, 0x1101f241, 0xf01b387c, 0x2000ff36, 0xfedbf7ff, 0xf7ff2001, 
+    0x2002fed8, 0xfed5f7ff, 0xf7ff2003, 0x48cefed2, 0x22062301, 0xf01b2140, 0x48cbff3e, 0x22062301, 
+    0x30202140, 0xff37f01b, 0x230148c7, 0x21402206, 0xf01b3040, 0x48c4ff30, 0x22062301, 0x30602140, 
+    0xff29f01b, 0x90002001, 0x46024603, 0xf7ff4601, 0xbd08ff29, 0xf44fb570, 0xf6403400, 0x46200102, 
+    0xfeeff7f3, 0x1d0048b8, 0xfef8f01b, 0x48b64605, 0xf01b1c80, 0xeb05fef3, 0x46204100, 0xfed0f7f3, 
+    0x302448b1, 0xfeeaf01b, 0x48af4605, 0xf01b3022, 0xeb05fee5, 0x46204100, 0xfec2f7f3, 0x304448aa, 
+    0xfedcf01b, 0x48a84605, 0xf01b3042, 0xeb05fed7, 0x46204100, 0xfeb4f7f3, 0x306448a3, 0xfecef01b, 
+    0x48a14605, 0xf01b3062, 0xeb05fec9, 0x46204100, 0xfea6f7f3, 0x4070e8bd, 0xf7ff20f0, 0x2804be41, 
+    0x2201d010, 0xf0824082, 0xb200000f, 0xd00b2901, 0x1000ea40, 0xb283b200, 0x22004893, 0x388221ff, 
+    0xbec9f01b, 0xe7f620ff, 0xeb012102, 0xf0401000, 0xe7ef000f, 0xf44fb570, 0xf6403400, 0x46200102, 
+    0xfe8ff7f3, 0x1d004888, 0xfe98f01b, 0x48864605, 0xf01b1c80, 0xeb05fe93, 0x46204100, 0xfe70f7f3, 
+    0x30244881, 0xfe8af01b, 0x487f4605, 0xf01b3022, 0xeb05fe85, 0x46204100, 0xfe62f7f3, 0x3044487a, 
+    0xfe7cf01b, 0x48784605, 0xf01b3042, 0xeb05fe77, 0x46204100, 0xfe54f7f3, 0x30644873, 0xfe6ef01b, 
+    0x48714605, 0xf01b3062, 0xeb05fe69, 0x46204100, 0xfe46f7f3, 0x2100486d, 0x0000f990, 0x4070e8bd, 
+    0xe92de79d, 0x000c41f0, 0xeb014967, 0x46801040, 0x2731d401, 0x2711e000, 0x21402206, 0xfe79f01b, 
+    0xb2462c00, 0x4264da00, 0xb2244862, 0x0000f990, 0xd0022804, 0xd0022805, 0x00a0e003, 0x0060e000, 
+    0x4640b204, 0xf01b2100, 0x2500fe3c, 0x4639e005, 0xf01b4640, 0x1c6dfe36, 0x42a5b22d, 0xb2b3dbf7, 
+    0xe8bd4640, 0x220641f0, 0xf01b2140, 0xb570be44, 0x3d7e4d4d, 0xb1201cac, 0xd00a2801, 0xd10f2802, 
+    0x2306e02a, 0x22044628, 0xf01b21f0, 0x2303fe34, 0x2307e001, 0x2204e021, 0x21704620, 0xfe2bf01b, 
+    0x46282305, 0x21f02204, 0xfe25f01b, 0x46202302, 0x21702204, 0xfe1ff01b, 0xf24f2305, 0x220c0100, 
+    0xf01b4628, 0x4620fe18, 0x0100f247, 0x4070e8bd, 0x220c2302, 0xbe0ff01b, 0x46282308, 0x21f02204, 
+    0xfe09f01b, 0xe7d62302, 0x482f4601, 0x387eb570, 0x4424f242, 0xf2411c85, 0x29083613, 0x4287f247, 
+    0xe8dfd22b, 0x0704f001, 0x1610160a, 0xf2451f18, 0xe00a2163, 0x4185f247, 0xf247e001, 0xf01b7187, 
+    0x4631fdd0, 0xf240e014, 0xf01b418c, 0x4621fdca, 0x4611e00e, 0xf249e7f3, 0xf01b61a7, 0xf240fdc2, 
+    0xe0052102, 0x01c9f64b, 0xfdbbf01b, 0x1101f240, 0xe8bd4628, 0xf01b4070, 0xbd70bdb4, 0x4c12b570, 
+    0x210f2200, 0x3c7e4605, 0xf01b4620, 0x1b40fdd2, 0x280fb240, 0x200fdd01, 0x2800e002, 0x2000da00, 
+    0x4620b283, 0x4070e8bd, 0x210f2200, 0xbdb3f01b, 0x9902b430, 0xf245b181, 0x21002408, 0x41991aa4, 
+    0xf06fda11, 0xe0350109, 0xf2030882, 0x00040248, 0x00040243, 0x00040242, 0xda012b00, 0xe0292101, 
+    0x31fff04f, 0xf244e026, 0x1a510100, 0x0100f173, 0xf06fdb02, 0xe01d0103, 0x0400f242, 0xf1731b14, 
+    0xf06f0400, 0xda150101, 0xda132b00, 0x1049030c, 0x41991aa4, 0x4c65db04, 0x1aa413a1, 0xda014199, 
+    0xe0072102, 0x13e14c62, 0x41991aa2, 0x2104da01, 0x210ae000, 0xb2c9bc30, 0xbda0f7ff, 0xf244485d, 
+    0xb510310f, 0xfd4df01b, 0x2307485a, 0xf6402208, 0x38127100, 0xfd5ff01b, 0x23014856, 0x46192200, 
+    0xf01b306a, 0x4853fd58, 0x22002301, 0x308a4619, 0xfd51f01b, 0x2301484f, 0x46192200, 0xf01b30aa, 
+    0x484cfd4a, 0x22002301, 0xe8bd4619, 0x30ca4010, 0xbd41f01b, 0x4605b570, 0x0103f640, 0x3000f44f, 
+    0xfd0ff7f3, 0xfca1f7ff, 0x21004c43, 0xf9944608, 0xf7fc2000, 0xf7fffdcf, 0xb201fda7, 0x14027025, 
+    0xf7ff4610, 0xf994fd0c, 0xf7ff0000, 0xf994fc69, 0xf7ff0000, 0xf994fcae, 0xf7ff0000, 0x2100fcf9, 
+    0xf7fc2001, 0xf994ffc2, 0x21002000, 0xf7fc200c, 0x2101fd6b, 0x2000f994, 0xf7fc4608, 0xe8bdfdab, 
+    0xe6474070, 0x4ff8e92d, 0x482c4682, 0x90b0f8df, 0x46e82500, 0x6800462a, 0x1052f890, 0x1000f88d, 
+    0x1054f890, 0x1001f88d, 0x0056f890, 0x0002f88d, 0x1000f999, 0x0001eb0d, 0xf81021ff, 0x481d3c03, 
+    0xf01b3050, 0x2704fce8, 0xf1ba2610, 0xd0230f00, 0xf7ff2400, 0x4138fd59, 0xb2e41c64, 0x440542b4, 
+    0xf44fd3f7, 0x46293080, 0xfc9af7f3, 0x2000f999, 0xeb081268, 0x22000102, 0x1c03f811, 0x49114348, 
+    0xf1c17809, 0x41080115, 0x31fff240, 0x0309f3c0, 0x30524808, 0xfcbff01b, 0x22024806, 0x46532104, 
+    0xf01b304a, 0xe8bdfcb8, 0x00008ff8, 0xffffc000, 0xffffadf8, 0xf2030816, 0x00040248, 0x00040598, 
+    0x00040242, 0x00040243, 0x4cb3b510, 0x4620b281, 0xfc87f01b, 0x46202100, 0xfc83f01b, 0xf64f4cae, 
+    0x3c1071ff, 0xf01b4620, 0x4620fc7c, 0x4010e8bd, 0xf01b2100, 0xf04fbc76, 0xb51030ff, 0xffe4f7ff, 
+    0xf01b48a6, 0xe8bdfc65, 0x20044010, 0xbd25f7fa, 0x9c02b510, 0x70427001, 0x70c47083, 0xb570bd10, 
+    0x24004d9f, 0x0600f647, 0x4631230f, 0xeb05220b, 0xf01b0044, 0x1c64fc70, 0xdbf52c04, 0xb570bd70, 
+    0x24004d97, 0x0600f647, 0x46312300, 0xeb05220b, 0xf01b0044, 0x1c64fc60, 0xdbf52c04, 0xe92dbd70, 
+    0x4f9041f0, 0x46052400, 0x1600f240, 0x0804f107, 0x3044eb06, 0x4638b281, 0xfc33f01b, 0xf01b4640, 
+    0xf825fc2d, 0x1c640014, 0xdbf12c04, 0x81f0e8bd, 0x41f0e92d, 0x24004e82, 0x070ef06f, 0x36104605, 
+    0x0044eb06, 0xfc1af01b, 0xfc70f01d, 0xf01e463a, 0xeb05fae4, 0x1c6402c4, 0xe9c22c04, 0xdbef0100, 
+    0xb510e7e4, 0x46204c78, 0xfc08f01b, 0xf01b4620, 0xf010fc05, 0xd0000020, 0xbd102001, 0x220d4873, 
+    0x0100f242, 0xf01bb510, 0x2800fc24, 0x2001d000, 0xe92dbd10, 0xf24441f0, 0x460c0600, 0x4607220e, 
+    0x486b4603, 0xf01b4631, 0x4865fc06, 0x387e2100, 0xfbe7f01b, 0x4d664866, 0x3d443850, 0xd00e2c02, 
+    0xd0132c01, 0x22002300, 0xf01b2101, 0x463bfbf4, 0x46284631, 0x41f0e8bd, 0xf01b220e, 0x2200bbec, 
+    0x2101463b, 0xfbe7f01b, 0xe7f12300, 0xe7ea463b, 0x41f0e92d, 0x461f4c56, 0x460e4615, 0x46033422, 
+    0x46202200, 0xf01b2103, 0x2202fbd6, 0x210c4633, 0xf01b4620, 0x2204fbd0, 0x2130462b, 0xf01b4620, 
+    0x2206fbca, 0x21c0463b, 0xf01b4620, 0x4620fbc4, 0x41f0e8bd, 0x23012208, 0xf01b0151, 0xb570bbbc, 
+    0x22004d43, 0x35222103, 0xf01b4628, 0x2202fbc2, 0x210c4604, 0xf01b4628, 0xea44fbbc, 0x46280480, 
+    0x21302204, 0xfbb5f01b, 0x1400ea44, 0x22064628, 0xf01b21c0, 0xea44fbae, 0xb2801080, 0xb570bd70, 
+    0x4604460d, 0x46114833, 0xfb7bf01b, 0x46294831, 0xf01b1e80, 0x482ffb76, 0xe8bd4621, 0x1f004070, 
+    0xbb6ff01b, 0xe9ddb5f0, 0xe9dd5408, 0xf8dd7606, 0xb109c014, 0x0002f040, 0xf040b10a, 0xb10b0001, 
+    0x0008f040, 0x0f00f1bc, 0xf040d001, 0xb10f0004, 0x0010f040, 0xf040b10d, 0xb10e0020, 0x0040f040, 
+    0xd0012c00, 0x0080f040, 0x2801bdf0, 0xd00cb510, 0xd1152803, 0x22024818, 0xf01b213c, 0xb2c0fb6a, 
+    0xd00e2807, 0xd10a2808, 0x4814e00d, 0x213c2202, 0xfb5ff01b, 0x2806b2c0, 0x2807d003, 0x2003d003, 
+    0x2004bd10, 0x2005bd10, 0x2200bd10, 0x480c4603, 0xf01b2107, 0x0000bb40, 0xf203902a, 0xf0001144, 
+    0xf38f2200, 0xf38f2360, 0xf3cfffc2, 0xf38fffd4, 0xf38f2050, 0xf38e0030, 0xf2060000, 0xf2020000, 
+    0xf2070000, 0x220c2301, 0x0319b570, 0x46204cfe, 0xfb21f01b, 0x46202301, 0x21402206, 0xfb1bf01b, 
+    0x46202300, 0x21202205, 0xfb15f01b, 0x46202300, 0x21102204, 0xfb0ff01b, 0x46202301, 0x21802207, 
+    0xfb09f01b, 0xf2442300, 0x220e0100, 0xf01b4620, 0x4cedfb02, 0x220a2300, 0x4100f240, 0x46203c10, 
+    0xfaf9f01b, 0x46202208, 0x01512300, 0xfaf3f01b, 0xf2404de5, 0x230014c0, 0x1dad4621, 0x46282206, 
+    0xfae9f01b, 0x46282306, 0x21382203, 0xfae3f01b, 0x46282306, 0x21072200, 0xfaddf01b, 0x46212306, 
+    0x461a1cad, 0xf01b4628, 0x1faefad6, 0x46302302, 0x21072200, 0xfacff01b, 0x46282300, 0x461a2107, 
+    0xfac9f01b, 0x46212306, 0x4630461a, 0xfac3f01b, 0x4ccd4621, 0x3c0c2306, 0x4620461a, 0xfabbf01b, 
+    0xe8bd4620, 0x23064070, 0x21072200, 0xbab3f01b, 0x43f8e92d, 0x9314f8df, 0x49c52500, 0x27032601, 
+    0x0802f04f, 0x0000f899, 0x7080f440, 0x0000f8a9, 0x29017809, 0xf3c0d038, 0x91001181, 0x0103f000, 
+    0x1301f3c0, 0x0281f3c0, 0xf7ff48ba, 0xf365fe11, 0xf3660407, 0xf368240f, 0xf3674417, 0xf899641f, 
+    0xb0010000, 0xf3c00782, 0x0f520381, 0xf102fa04, 0x005b1222, 0xf3c0409a, 0x43111301, 0x005b1422, 
+    0x1081f3c0, 0x4311409a, 0x00401622, 0x43f0e8bd, 0x43114082, 0x0003f001, 0x1381f3c1, 0x1201f3c1, 
+    0x0181f3c1, 0xbe84f7ff, 0x0103f000, 0xf3c09100, 0xf3c00381, 0xf3c01201, 0x489e1181, 0xfdd8f7ff, 
+    0x0407f367, 0x240ff368, 0x4417f366, 0x641ff365, 0xb538e7c5, 0xd0042801, 0xb1282403, 0x88004893, 
+    0xf7ffb138, 0xe01dff95, 0x94002302, 0x21002201, 0x488fe015, 0x28017800, 0x2303d006, 0x21012202, 
+    0xf7ff2000, 0xe7effe55, 0x22012300, 0x20032102, 0xfe4ef7ff, 0x90002000, 0x22022301, 0x48852103, 
+    0xfda6f7ff, 0x4c834884, 0x1000f990, 0x70015c61, 0x3003f994, 0x2002f994, 0x1001f994, 0x0000f994, 
+    0xf8b8f7ff, 0x3003f994, 0x2002f994, 0x1001f994, 0x0000f994, 0xf8d0f7fc, 0x3003f994, 0x2002f994, 
+    0x1001f994, 0x0000f994, 0xf99df7fd, 0x3003f994, 0x2002f994, 0x1001f994, 0x0000f994, 0xfc41f00f, 
+    0xfe3df7ff, 0x4038e8bd, 0x486c4601, 0xb9d9f01b, 0x5ff0e92d, 0xf64b4869, 0x30a831b8, 0xf9d1f01b, 
+    0x23014d67, 0x0399220e, 0xf01b4628, 0x4c65f9e4, 0x22022300, 0x46202104, 0xf9ddf01b, 0x8180f8df, 
+    0x22022301, 0x0860f108, 0x46402104, 0xf9d3f01b, 0xf241485d, 0x11370600, 0x28988800, 0x2888d07e, 
+    0x28a8d0fc, 0x28b8d0fa, 0x2894d0f8, 0x2884d077, 0x28a4d0fc, 0x28b4d0fa, 0x2301d0f8, 0x220c4631, 
+    0xf01b4620, 0x2301f9b8, 0x22084639, 0xf01b4620, 0x2301f9b2, 0x22074620, 0xf01b2180, 0x2301f9ac, 
+    0x21402206, 0xf01b4620, 0x2301f9a6, 0x22054620, 0xf01b2120, 0x4c43f9a0, 0x220f2301, 0x03d93c20, 
+    0xf01b4620, 0x2301f998, 0x220c4631, 0xf01b4620, 0x2300f992, 0x22064620, 0xf01b2140, 0x2300f98c, 
+    0x22054620, 0xf01b2120, 0x4838f986, 0x22062300, 0xf01b2140, 0xf240f980, 0x48354a00, 0x46512300, 
+    0xf01b220a, 0xf8dff978, 0xf640b0cc, 0x23010900, 0x220b4649, 0xf01b4658, 0x2002f96e, 0xff19f7ff, 
+    0x23004821, 0x21802207, 0xf01b382c, 0x482af964, 0x20017801, 0xfd4df7ff, 0x23014c26, 0x46392208, 
+    0x46203c1c, 0xf957f01b, 0x46202301, 0x21202205, 0xf951f01b, 0x22042301, 0xe0012110, 0xe08be07c, 
+    0xf01b4620, 0x4817f948, 0x30382100, 0xf929f01b, 0x46282301, 0x46192200, 0xf93df01b, 0x46312301, 
+    0x4628220c, 0xf937f01b, 0x46282301, 0x0359220d, 0xf931f01b, 0x46392300, 0x46442208, 0xf01b4640, 
+    0xf240f92a, 0xe01911d4, 0xf203902c, 0x00040270, 0x000402c8, 0x00040520, 0x00040248, 0xf23c8012, 
+    0xf38f0000, 0xf38e0040, 0x000404fe, 0xf203507c, 0xf38fffc0, 0xf38f2050, 0x00040321, 0x30a448fe, 
+    0xf8eff01b, 0xf24048fc, 0x30a61129, 0xf8e9f01b, 0x46492301, 0x4620220b, 0xf8fdf01b, 0x46512300, 
+    0x4620220a, 0xf8f7f01b, 0x23014cf3, 0x4649220b, 0x46203464, 0xf8eff01b, 0x46512301, 0x4620220a, 
+    0xf8e9f01b, 0x46202301, 0x461a2102, 0xf8e3f01b, 0x46202301, 0x46192200, 0xf8ddf01b, 0x46582300, 
+    0x21302204, 0xf8d7f01b, 0x5ff0e8bd, 0x48e32301, 0x46192200, 0xb8cff01b, 0x46312300, 0x4620220c, 
+    0xf8c9f01b, 0x46392300, 0x46202208, 0xf8c3f01b, 0x22072301, 0xe7152180, 0xe6ff2300, 0x210a4ad8, 
+    0xb5102005, 0xf8dbf7f3, 0xf7fa2004, 0x2002f834, 0xf831f7fa, 0xf00c2002, 0x49d2fd14, 0x70082002, 
+    0x780048d1, 0x22ffb920, 0x46112004, 0xf9b6f7f5, 0x230148ce, 0x210f2200, 0xf89df01b, 0x230b48c7, 
+    0x210f2200, 0xf01b385a, 0x48c3f896, 0x21042202, 0xf01b307c, 0x2801f89e, 0x2000d110, 0xff2ff7fd, 
+    0x23014cbe, 0x3c32220a, 0x46200299, 0xf883f01b, 0x46202208, 0x01512301, 0xf87df01b, 0x48bc2301, 
+    0x03d9220f, 0xf877f01b, 0x210048b4, 0x4010e8bd, 0xf01b3848, 0xe92db856, 0x4ab141f0, 0x2005210b, 
+    0xf88df7f3, 0xf7f92004, 0x2002ffe6, 0xffe3f7f9, 0xf00c2001, 0x49abfcc6, 0x22002001, 0x70084603, 
+    0x48aa210f, 0xf857f01b, 0xf2414da4, 0x23000400, 0x3d504621, 0x4628220c, 0xf84df01b, 0x1eae2303, 
+    0x22004619, 0xf01b4630, 0x2301f846, 0x22024630, 0xf01b2104, 0x2301f840, 0x220f4630, 0x463903df, 
+    0xf839f01b, 0x46212301, 0x4628220c, 0xf833f01b, 0x46212300, 0x4628220c, 0xf82df01b, 0x46392300, 
+    0x4630220f, 0xf827f01b, 0x46302300, 0x461a2103, 0xf821f01b, 0x46302300, 0x21042202, 0xf81bf01b, 
+    0x220e488c, 0xf01b00a1, 0x2800f824, 0xe8bdd003, 0xf00c41f0, 0xe8bdbcf9, 0x498781f0, 0xb5102000, 
+    0xf7ff7008, 0x4883fb9c, 0x220c2301, 0x1d800319, 0xf801f01b, 0xf7fd2002, 0xf7fffea2, 0x487cfb6c, 
+    0x303a2100, 0xffddf01a, 0x21014879, 0xf01a3054, 0x4877ffd8, 0x0100f642, 0xf01a3052, 0x4c6fffd2, 
+    0x220a2301, 0x02993c32, 0xf01a4620, 0x2301ffe4, 0x22094620, 0xf01a0259, 0x2208ffde, 0x23014620, 
+    0xf01a0151, 0xf00cffd8, 0xf7f4fc8a, 0x2100f985, 0xf00b4608, 0x2109f829, 0xe8bd4a61, 0x20054010, 
+    0xbfedf7f2, 0xb5704865, 0x78004d65, 0x2301b108, 0x2300e000, 0x22034628, 0xf01a2108, 0x4c61ffbc, 
+    0xb1f17821, 0x46282301, 0x21042202, 0xffb3f01a, 0x46282301, 0x461a2102, 0xffadf01a, 0x78214855, 
+    0x2901302c, 0x2301d901, 0x2300e000, 0x21012200, 0xffa1f01a, 0x4c524854, 0x78011d24, 0x2301b161, 
+    0x2300e00b, 0x22024628, 0xf01a2104, 0x2300ff94, 0x22014628, 0xe7eb2102, 0x46202300, 0x21012200, 
+    0xff89f01a, 0x78094949, 0x2301b109, 0x2300e000, 0x22014620, 0xf01a2102, 0x4d41ff7e, 0x21022201, 
+    0x46283d38, 0xff85f01a, 0x46042206, 0x46282140, 0xff7ff01a, 0x46284304, 0x21202205, 0xff79f01a, 
+    0x483b4304, 0x4c3cb2e3, 0x21102204, 0x48397003, 0x46207003, 0xff5ff01a, 0x46202300, 0x21082203, 
+    0xff59f01a, 0x4070e8bd, 0x21004834, 0xbf39f01a, 0xf3c04a33, 0x70111100, 0x11c0f3c0, 0x70114a31, 
+    0x78094931, 0xd11b2901, 0xf3c04a30, 0x70110180, 0x01c0f3c0, 0x70114a2e, 0x1140f3c0, 0x70114a2d, 
+    0x1180f3c0, 0x70114a2c, 0x0201f000, 0xf3c0492b, 0x780b0040, 0x700a431a, 0x780a4929, 0x700a4302, 
+    0xe92d4770, 0xf8df5ff0, 0x2300909c, 0x4e214d22, 0xf8894f26, 0x4b243000, 0xb158781b, 0xc090f8df, 
+    0xf8df2801, 0xf8df806c, 0xf89ca064, 0xea4fe00b, 0xe03f1cde, 0x0000e056, 0xf38f0000, 0xf38f22d2, 
+    0xcccc0000, 0x000401fc, 0x0004023d, 0xf23c8316, 0xf38f201c, 0xf2039026, 0x00040304, 0x00040277, 
+    0xf38e0078, 0x00040278, 0x000402cd, 0x000402ce, 0x0004056e, 0x00040568, 0xf2035256, 0xf23c8026, 
+    0x0004058a, 0x000402cf, 0x00040576, 0x0004057d, 0x0004057c, 0x00040571, 0x00040572, 0x0004057f, 
+    0x0004057e, 0x0004056a, 0x00040573, 0x00040570, 0x000413d8, 0x2802d01c, 0x2000d02a, 0x0000f88a, 
+    0x0000f888, 0x70307028, 0x29037038, 0x8404f8df, 0xa404f8df, 0xb404f8df, 0x2905d023, 0x2904d036, 
+    0xe05cd049, 0x680048fe, 0xd3172818, 0xe7ec703b, 0xd1ea2a01, 0xc000f888, 0x1040f3ce, 0xc000f88a, 
+    0x1280f3ce, 0x70307028, 0xf889703b, 0xe7dc2000, 0xd1032a01, 0xc000f888, 0xc000f88a, 0x7033702b, 
+    0x2201e7e4, 0x21024640, 0xfea3f01a, 0xf88a2201, 0x21020000, 0xf01a4640, 0x49eafe9c, 0x70082405, 
+    0x783849e9, 0x0000f88b, 0xe0287008, 0x46402206, 0xf01a2140, 0x2206fe8e, 0x0000f88a, 0x46402140, 
+    0xfe87f01a, 0x240449df, 0x49df7008, 0xf88b7830, 0x70080000, 0x2205e013, 0x21204640, 0xfe79f01a, 
+    0xf88a2205, 0x21200000, 0xf01a4640, 0x49d5fe72, 0x70082403, 0x782849d4, 0x0000f88b, 0x25017008, 
+    0x1000f89a, 0x4fd248d1, 0x4ed22901, 0x8348f8df, 0xf89bd103, 0x29011000, 0x49cad004, 0x29017809, 
+    0xe027d024, 0x680949c6, 0xd3092912, 0x70012102, 0x1000f899, 0xf004fa05, 0xf4404308, 0xe008403c, 
+    0x70012103, 0x1000f899, 0xf004fa05, 0xf4404308, 0xb281406e, 0xf01a4638, 0x4640fe14, 0xe8bd7035, 
+    0x23005ff0, 0x21082203, 0xbe25f01a, 0x780949b6, 0xd00e2901, 0x70042400, 0x46232203, 0x46402108, 
+    0xfe19f01a, 0x46382100, 0xfdfbf01a, 0xe8bd7034, 0x21059ff0, 0x23017001, 0x22034640, 0xf01a2108, 
+    0x2301fe0a, 0x220048ad, 0xf01a4619, 0xf899fe04, 0xfa051000, 0x4308f004, 0xf440b280, 0x4638414f, 
+    0xfddff01a, 0xe7e27035, 0x41f0e92d, 0x210448a0, 0x4614461f, 0x22022301, 0xe9dd3816, 0xf01a5606, 
+    0x4623fdea, 0x220a4c9a, 0x4100f240, 0x46203c40, 0xfde1f01a, 0x463b2209, 0x2100f240, 0xf01a4620, 
+    0x2206fdda, 0x2140462b, 0xf01a4620, 0x4633fdd4, 0xe8bd4620, 0x220541f0, 0xf01a2120, 0xb57cbdcc, 
+    0xd1642801, 0x79c9498e, 0x498e098a, 0x700a2a01, 0x498dd15d, 0xf7ff7809, 0x498cfe94, 0x7809488c, 
+    0xe9cd7800, 0x488b0100, 0x488b7803, 0x488b7802, 0x488b7801, 0xf7ff7800, 0x4d76ffb7, 0xf640220b, 
+    0x1cad0100, 0xf01a4628, 0x4c79fdb4, 0x21012200, 0x3c404603, 0xf01a4620, 0x220afd9e, 0x4100f240, 
+    0xf01a4628, 0x2201fda6, 0x21024603, 0xf01a4620, 0x2300fd92, 0x22024620, 0xf01a2104, 0x2209fd8c, 
+    0x2100f240, 0xf01a4628, 0x2203fd94, 0x21084603, 0xf01a4620, 0x2201fd80, 0x21024628, 0xfd89f01a, 
+    0x46032204, 0x46202110, 0xfd75f01a, 0x1f242301, 0x22004619, 0xf01a4620, 0x2300fd6e, 0x21014620, 
+    0xf01a461a, 0xe8bdfd68, 0xf7f8407c, 0xbd7cbff8, 0xe9ddb530, 0xb10c5403, 0xd0022804, 0xb95ab11d, 
+    0x2003e004, 0xb911bd30, 0xe002b932, 0x2000b109, 0xb10bbd30, 0xbd302002, 0xbd302001, 0xd0004308, 
+    0x47702001, 0x4c57b570, 0x46202103, 0xfd29f01a, 0xf6474854, 0x30187100, 0xfd23f01a, 0xf2404851, 
+    0x301a4101, 0xfd1df01a, 0x210f484f, 0xfd19f01a, 0xf7fd2005, 0x2181f9c3, 0xf01a1f20, 0x494bfd12, 
+    0x4620220f, 0xf248780b, 0xf01a0100, 0x4d48fd24, 0xb3607828, 0x46202301, 0x21402206, 0xfd1bf01a, 
+    0xf6477828, 0x1e404100, 0x220ab283, 0xf01a4620, 0x4840fd12, 0x21802207, 0x46207803, 0xfd0bf01a, 
+    0x46202301, 0x21202205, 0xfd05f01a, 0xf90cf011, 0x23004827, 0x213e2201, 0xf01a3874, 0x2004fcfc, 
+    0xfc79f7f9, 0x4070e8bd, 0xf7f9200b, 0x2300bda7, 0x21402206, 0xe92de7da, 0xf8df5ff0, 0xf24fb0ac, 
+    0x23000a00, 0xf10b4688, 0x46810b64, 0x4651220c, 0xf01a4658, 0xf10bfce0, 0xf6400402, 0x23004100, 
+    0x220a4620, 0xfcd7f01a, 0xf240481e, 0x4d107100, 0x36fff240, 0xf240309a, 0x3d7477ff, 0x0f03f1b8, 
+    0x2300d061, 0xf01a2208, 0x230cfcc6, 0x22014628, 0xe031213e, 0xf38e0040, 0x0004056e, 0x0004056f, 
+    0x000401f0, 0x00040568, 0x00040569, 0x00040eda, 0xf38f0076, 0x00040ed9, 0xf2035256, 0xf23c8024, 
+    0x000413d8, 0x00040503, 0x00040242, 0x00040571, 0x00040572, 0x0004057d, 0x0004057c, 0x0004057f, 
+    0x0004057e, 0xf38f2056, 0xf2039012, 0x000402fc, 0x000402fd, 0x000402fe, 0xfc8df01a, 0x46312324, 
+    0x46202200, 0xfc87f01a, 0x46512303, 0x4620220c, 0xfc81f01a, 0x3304f240, 0x22004639, 0xf01a4658, 
+    0xf1b9fc7a, 0xd1270f01, 0xf6402301, 0x220a4100, 0xf01a4620, 0x4651fc70, 0xe8bd4658, 0x230f5ff0, 
+    0xf01a220c, 0x2303bc68, 0xf01a2208, 0x230cfc64, 0x22014628, 0xf01a213e, 0x231bfc5e, 0x22004631, 
+    0xf01a4620, 0x2304fc58, 0x220c4651, 0xf01a4620, 0xf240fc52, 0xe7cf4300, 0x0000e639, 0x4ff0e92d, 
+    0xb2bcf8df, 0xf8dfb087, 0xf8db92b4, 0xf8d90000, 0x88008000, 0x20009004, 0xfd55f7fb, 0x4000f240, 
+    0x0a01f04f, 0xf8cd2205, 0x1044a00c, 0xe9cd9400, 0xf8d92001, 0x1f920000, 0xf2402103, 0xf2406500, 
+    0xf24016df, 0x465317a7, 0xfdc0f00d, 0xf04f489d, 0x78000100, 0x46082803, 0xf8d9d013, 0xf9333000, 
+    0x2a002011, 0x4252da00, 0x42a11c49, 0xdbf64410, 0x20001244, 0xdd1342b4, 0x1464eba4, 0x1165eba5, 
+    0x4a91e014, 0x2001f992, 0x2382eb08, 0x2011f933, 0xda002a00, 0x1c494252, 0x441042a1, 0xe7e7dbf6, 
+    0xda0842bc, 0x1464eb04, 0x1165eb05, 0xb2401c40, 0x2810b20d, 0xf44fdbde, 0xf2400800, 0x464011f4, 
+    0xfbbff7f2, 0x46404981, 0xfbaaf7f2, 0x46404639, 0xfba6f7f2, 0x46404621, 0xfba2f7f2, 0x46404631, 
+    0xfb9ef7f2, 0x46404629, 0xfb9af7f2, 0x46404978, 0xfb96f7f2, 0xf7f92000, 0x4e76fff7, 0x4800f240, 
+    0x78314640, 0xfb9ef7f9, 0xf7f82001, 0x4f72f99c, 0x68389904, 0xfbaef01b, 0x0000f8db, 0x106cf8b0, 
+    0xf8206838, 0xf8db5011, 0x10692000, 0x01a5eb01, 0x24004249, 0x206cf8b2, 0xeb004625, 0x80410042, 
+    0x68382300, 0xe9cd461a, 0x20010500, 0xf7f7b261, 0x1c64ffca, 0x2c04b2a4, 0x2000d3f2, 0xf973f7f8, 
+    0x78204c5e, 0xd0232801, 0xf00e2002, 0x7831fbf5, 0xf7f92040, 0xf7fefb67, 0x7831fccd, 0x0000f244, 
+    0xfb60f7f9, 0x4640220b, 0x46112300, 0x95019500, 0xf879f7fa, 0xf241220d, 0x23000000, 0x95004611, 
+    0xf7fa9501, 0x4f4ef870, 0xb3d87838, 0xe03e2001, 0xf00e2000, 0x220efbd1, 0x0900f640, 0x46484611, 
+    0xf918f7fa, 0xf00e2002, 0x7831fbc7, 0xf7f92040, 0x200cfb39, 0x220d9000, 0x23014657, 0xe9cd4611, 
+    0x9504a502, 0x90019505, 0xf7fa4640, 0x200df993, 0x23019000, 0xe9cd4602, 0x46017502, 0x95059504, 
+    0x46489001, 0xf986f7fa, 0x9000200e, 0x46022301, 0x7502e9cd, 0x95044601, 0x90019505, 0xf7fa4648, 
+    0xe7c0f979, 0x7820e7ff, 0xd1bf2801, 0xf00c2000, 0x4605ffa4, 0xf7f92000, 0x7831ff57, 0x464046c1, 
+    0xfb00f7f9, 0xd0362d00, 0xd13407e8, 0xf2464d25, 0xf8df0a00, 0x220d8094, 0xf9954651, 0xb2830000, 
+    0xf01a4640, 0x2301fb18, 0x220f4640, 0xf01a03d9, 0x2001fb12, 0xfb70f00e, 0x46487831, 0xfae2f7f9, 
+    0x481a7839, 0xf9952900, 0x5c411000, 0x7820d102, 0xd0012801, 0xe0002001, 0xf00c2000, 0x2300fe23, 
+    0x220d4651, 0xf01a4640, 0xb007faf6, 0xe8bd2000, 0xf00e4ff0, 0xb007bb51, 0x8ff0e8bd, 0x000401dc, 
+    0x00040598, 0x0004057b, 0x00040520, 0x99339933, 0xdcba01f5, 0x00040243, 0x000401e8, 0x00040502, 
+    0x000402a4, 0x0004022e, 0xf2035092, 0x00040524, 0x41ffe92d, 0xf04f4efe, 0x15505200, 0x1000f996, 
+    0xfaedf7f2, 0xfe7af7ff, 0xf7f92000, 0xf44ffeed, 0xf2400500, 0x462811f4, 0xfa93f7f2, 0x462849f5, 
+    0xfa7ef7f2, 0xf9944cf4, 0xb2810000, 0xf7f24628, 0x49f2fa88, 0xf7f24628, 0x4668fa73, 0xf9c3f7fb, 
+    0x0000f994, 0xd0011c40, 0xe0232007, 0xf2404dec, 0xf8df2700, 0xf99583b0, 0x1c400000, 0xeb0017c1, 
+    0xf0217191, 0x1a400103, 0x24007028, 0xb1087828, 0xe0004639, 0x46204641, 0xfc13f7fe, 0xb2641c64, 
+    0xdbf32c04, 0x28007828, 0x48dfd105, 0xf7f57800, 0x2003fbff, 0xe8bd7030, 0xe92d81ff, 0x24005ffc, 
+    0x46a24615, 0xff4ef01c, 0xfa0f4ed8, 0xf8dff980, 0x27018360, 0x0b80f44f, 0x49d74ad6, 0x80374668, 
+    0xa006f8ad, 0xa002f8ad, 0xa004f8ad, 0xa000f8ad, 0x3000f898, 0xfa38f7fb, 0x46582172, 0xfa59f7f2, 
+    0x46482202, 0xf00e2107, 0x4668fabd, 0xfa0df7fb, 0x46692000, 0x2010f931, 0xdb0142aa, 0x5010f821, 
+    0xb2401c40, 0xdbf52804, 0x780048c4, 0xd1042803, 0xf99048c3, 0xf8210003, 0xf8987010, 0x46683000, 
+    0x49bd4abc, 0xfa10f7fb, 0x46582172, 0xfa31f7f2, 0x28028830, 0x1c64d103, 0x2c0ab264, 0xf8a6dbbc, 
+    0xe8bda000, 0xe92d9ffc, 0x4fa947f0, 0x5200f04f, 0x60782050, 0xf9971550, 0xf7f21000, 0x4eb1fa40, 
+    0xf8df2000, 0x4aab82ac, 0x80f049ab, 0x807080b0, 0x46308030, 0x3000f898, 0xf9e6f7fb, 0x0980f44f, 
+    0x46482172, 0xfa05f7f2, 0xf2402202, 0x21071048, 0xfa68f00e, 0x4630251e, 0xf7fb2401, 0x2000f9b6, 
+    0x1010f936, 0xdb0142a9, 0x5010f826, 0x1010f936, 0xdc0142a1, 0x4010f826, 0xb2401c40, 0xdbef2804, 
+    0x3000f898, 0x49944a93, 0xf7fb4896, 0x2172f9bd, 0xf7f24648, 0x2060f9de, 0xe8bd6078, 0xb53887f0, 
+    0x20004c83, 0x20309000, 0x46686060, 0xfc2ef7fb, 0x7801488a, 0x29034668, 0x4a89d104, 0xf9922101, 
+    0x54812003, 0x78094982, 0xd10c2903, 0xf9914981, 0xf9912000, 0x5c823002, 0xf99154c2, 0xf9912001, 
+    0x5c821003, 0xf89d5442, 0x4d7f0000, 0xf89db1b8, 0xb1e80001, 0x0002f89d, 0xf89db188, 0xb1700003, 
+    0xf2422040, 0x60600110, 0xf7f20640, 0x2003f986, 0x23017020, 0x22004628, 0xf01a4619, 0xf89df99c, 
+    0xb1280001, 0x46282301, 0x461a2102, 0xf993f01a, 0x0002f89d, 0x2301b128, 0x22024628, 0xf01a2104, 
+    0xf89df98a, 0x28000003, 0x2301d005, 0x22034628, 0xf01a2108, 0xbd38f980, 0x5ff0e92d, 0x8e804604, 
+    0x26014d53, 0x7f96f5b0, 0x1a05f240, 0x1b61f240, 0xdc35d07b, 0xf2a04550, 0xd0691105, 0x28f0dc18, 
+    0xdc06d074, 0x28ceb330, 0x28cfd075, 0x60aed170, 0x28f1e07c, 0xf5b0d05c, 0xd1697f82, 0x22004944, 
+    0x311068e8, 0xff0bf015, 0x1d4060a8, 0xe050d07c, 0xd04d2910, 0x2907dc0f, 0x2908d077, 0x290fd048, 
+    0x493bd156, 0x68e82200, 0xf0153110, 0x60a8fef8, 0xd06b1d40, 0x291fe03d, 0x2920d069, 0xe037d148, 
+    0xf2a04558, 0xd0331161, 0xf5b0dc1b, 0xd07d7fa6, 0xf111dc07, 0xd02b0034, 0xd0782813, 0xd1372814, 
+    0xf5a0e026, 0x384d7080, 0x2813d022, 0x4928d130, 0x68e82200, 0xf0153110, 0x60a8fed2, 0xd0671d40, 
+    0x291ae017, 0xdc0fd014, 0xd07d2911, 0xd00f2912, 0xd11d2919, 0x2200491e, 0x311068e8, 0xfebff015, 
+    0x1d4060a8, 0xe004d071, 0xd06f2921, 0xd10f2922, 0xf04f60ae, 0x491632ff, 0x311068e8, 0xfedef015, 
+    0x1d0060a8, 0x68a8d005, 0xe157e00c, 0xe002e0a5, 0x20cee0d4, 0x490ee207, 0x68e82200, 0xf0153110, 
+    0x60a8fecd, 0xd0671d41, 0xd1e22801, 0xf2404f08, 0x37101000, 0x3000f9b7, 0xd05f2b0f, 0xf04f0542, 
+    0xf04f080a, 0xe0244c20, 0xe0cbe0b6, 0xe119e0ef, 0x00040630, 0x99349934, 0x0004022e, 0xdcba01f5, 
+    0x00040508, 0xfffffa00, 0x00040242, 0x00040268, 0x0004057b, 0x00040520, 0x0004054e, 0x00040234, 
+    0x00040518, 0x00040538, 0xf2035018, 0xe137e156, 0x2b10e17d, 0x2b0ad03a, 0xf995d1ab, 0xf8df1000, 
+    0xb3919420, 0xd06f2903, 0xd06e2906, 0xd06d2902, 0xd06c2904, 0xd06b290c, 0xd06a2907, 0xd0692905, 
+    0xd0682909, 0xe002290a, 0xe19be17a, 0xd06fe1a0, 0xd18e290b, 0x46624619, 0xf8b1f7f2, 0x8038200b, 
+    0xf04f48f8, 0x463932ff, 0xf0156800, 0x60a8fe38, 0xd0731d00, 0xe19268a8, 0xe19420cf, 0x4222f04f, 
+    0xf7f24619, 0x702ef89c, 0xe030e773, 0xf99149ee, 0x29031000, 0x2905d003, 0x2904d001, 0x49ebd102, 
+    0xb1217809, 0x702e210f, 0xf889f7f2, 0x4619e761, 0xf7f24662, 0xf000f884, 0x2000fa70, 0xf8a77028, 
+    0x46028000, 0x68e849e2, 0xfe09f015, 0x1d0060a8, 0x68a8d001, 0x20f0e007, 0x49dde165, 0x68e82200, 
+    0xfdfdf015, 0x1d4060a8, 0x20f1d1ce, 0xf7ffe15b, 0x2002fe66, 0xffd4f7f8, 0xf899b920, 0x1e400000, 
+    0xd2092806, 0xe008200a, 0xe036e01a, 0xe084e052, 0xe0c0e09f, 0xe0fde0dd, 0x8038200f, 0x220049cc, 
+    0xf01568e8, 0x60a8fddc, 0xd0021d00, 0xe6cc68a8, 0xf240e111, 0xe1361004, 0xa034f8a4, 0x9ff0e8bd, 
+    0xfdf1f7ff, 0x70282006, 0x220049c1, 0xf01568e8, 0x60a8fdc6, 0xd0021d00, 0xe00968a8, 0xf240e115, 
+    0xe120100c, 0x220049ba, 0xf01568e8, 0x60a8fdb8, 0xd1891d40, 0x100df240, 0x2370e115, 0xf7f2606b, 
+    0x49b4f81e, 0x48b4221e, 0xfd77f7ff, 0x60682080, 0x70282002, 0x220049ae, 0xf01568e8, 0x60a8fda0, 
+    0xd0011d00, 0xe6a368a8, 0x1014f240, 0xf240e0fb, 0xe0f81015, 0x606b2390, 0xf801f7f2, 0x20012100, 
+    0xf832f00a, 0xf44f2100, 0xf7f81080, 0x2100ffab, 0xf00a4608, 0xf00ef829, 0xf7f9f86d, 0xf7f9fbb9, 
+    0x20a0fbd4, 0x20046068, 0x49997028, 0x68e82200, 0xfd75f015, 0x1d0060a8, 0x68a8d001, 0xf240e008, 
+    0xe0d01024, 0x22004992, 0xf01568e8, 0x60a8fd68, 0xd1ae1d40, 0x1025f240, 0xf000e0c5, 0x200cf991, 
+    0x498b7028, 0x68e82200, 0xfd59f015, 0x1d0060a8, 0x68a8d001, 0xf240e008, 0xe0b4102c, 0x22004984, 
+    0xf01568e8, 0x60a8fd4c, 0xd1921d40, 0x102df240, 0xf7ffe0a9, 0x2002fcbd, 0xff22f7f8, 0x200ab108, 
+    0x200fe000, 0x497a8038, 0x68e82200, 0xfd37f015, 0x1d0060a8, 0x68a8d001, 0xf240e008, 0xe0921040, 
+    0x22004973, 0xf01568e8, 0x60a8fd2a, 0xd1c01d40, 0x1041f240, 0xf7f1e087, 0xf007ff92, 0x2005f815, 
+    0x496b7028, 0x68e82200, 0xfd19f015, 0x1d0060a8, 0x68a8d001, 0xf240e008, 0xe074104c, 0x22004964, 
+    0xf01568e8, 0x60a8fd0c, 0xd1a21d40, 0x104df240, 0xf000e069, 0xf899f8ff, 0x28030000, 0x2002d005, 
+    0xfedef7f8, 0x200ab120, 0xf8a7e003, 0xe0018000, 0x8038200f, 0x22004956, 0xf01568e8, 0x60a8fcf0, 
+    0xd0011d00, 0xe61968a8, 0x1060f240, 0xf8a4e04b, 0xe713b034, 0xf8acf000, 0x0000f899, 0xf43f2803, 
+    0xf885add6, 0x22008000, 0x68e84949, 0xfcd7f015, 0x1d0060a8, 0x68a8d001, 0xf240e008, 0xe0321072, 
+    0x22004943, 0xf01568e8, 0x60a8fcca, 0xd19e1d40, 0x1073f240, 0xf000e027, 0x2002f837, 0xfea0f7f8, 
+    0x200ab108, 0x200fe000, 0x49398038, 0x68e82200, 0xfcb5f015, 0x1d0060a8, 0x68a8d001, 0xf240e5f1, 
+    0xe010107a, 0x107bf240, 0xf240e00d, 0xe00a1082, 0x2200482c, 0x6800492e, 0xfca1f015, 0x1d4060a8, 
+    0xf240d193, 0x86a01083, 0x2200e6c8, 0xb5102101, 0x503bf2af, 0xfadef015, 0x20032108, 0xfc3cf015, 
+    0x39104923, 0xbd1060c8, 0xf00cb510, 0x4923f877, 0xf0194823, 0x2801fca5, 0x1300f240, 0x21e2d019, 
+    0x4618461c, 0xfe9df7f1, 0x46202100, 0xfe88f7f1, 0x01d0f242, 0xf7f14620, 0x481afea0, 0x28017800, 
+    0x2100d01b, 0xe8bd4818, 0xf2014010, 0xf019312b, 0x4813be98, 0x79c04915, 0x1000f3c0, 0x28007008, 
+    0x4c0bd00a, 0x5200f04f, 0x3c104618, 0x1000f994, 0xfec5f7f1, 0x7020200b, 0xf242bd10, 0xe7e17110, 
+    0x00040234, 0x000406cc, 0x00040242, 0x000402a4, 0x00040640, 0x44b861ec, 0x43a4170a, 0x0002b868, 
+    0x000413d8, 0x00040502, 0xf23c80ba, 0x00040204, 0x4965b50e, 0x70082001, 0x78004864, 0x4864b148, 
+    0x48647801, 0x48647803, 0x48647802, 0xf7fc7800, 0x4863f89f, 0xf9904963, 0xf7f70000, 0x4a62fc1a, 
+    0x48602104, 0xfd22f019, 0xf04f4860, 0xf9905200, 0x15501000, 0xfe83f7f1, 0xf00e2004, 0x495cf8f9, 
+    0x20007008, 0x46014602, 0xe9cd9002, 0xf7f70000, 0xbd0eff0b, 0x4c55b510, 0x5200f04f, 0xf9941550, 
+    0xf7f11000, 0xf00cfe6c, 0xb158fb42, 0x78004851, 0xd0022803, 0x70202009, 0x2004bd10, 0xfdbbf7f8, 
+    0xe7f8200b, 0xf7fa2000, 0x4841ff4e, 0xf7f47800, 0x4849ffaf, 0x70222203, 0x49412300, 0x4000f990, 
+    0xf990550b, 0x23014001, 0xf990550b, 0x23024002, 0xf990550b, 0x540a0003, 0x4010e8bd, 0xba95f00c, 
+    0x4c3ab510, 0x5200f04f, 0x606020b0, 0xf9941550, 0xf7f11000, 0x20b1fe34, 0xf00d6060, 0xf7f9feab, 
+    0xf7f9f9f7, 0x20bbfa12, 0x48326060, 0xb1707800, 0xd00c2807, 0x606020e0, 0x22004830, 0x20026801, 
+    0xfd9ef7f8, 0xf826f00d, 0x606020f0, 0x20c0bd10, 0xf00d6060, 0x20d0f81f, 0xb570e7f7, 0x20104c23, 
+    0x01052101, 0x46286060, 0xfdbbf7f1, 0x11f4f240, 0xf7f14628, 0x4822fdb6, 0xf0406800, 0x462841d0, 
+    0xfd9ef7f1, 0x4628491f, 0xfd9af7f1, 0xf7fa2000, 0xf7fafd2b, 0x2020fe22, 0x48176060, 0x49102400, 
+    0x2000f990, 0xf990548c, 0x22013001, 0xf99054ca, 0x22023002, 0xf99054ca, 0x22030003, 0xf00c540a, 
+    0x4811fa34, 0xbd707004, 0x00040203, 0x000404ed, 0x00040242, 0x0004059d, 0x0004059c, 0x000404ec, 
+    0x00040518, 0x00041258, 0x000412d8, 0x00040630, 0x00040205, 0x00040234, 0x00040520, 0x00040584, 
+    0x00057f78, 0xdcba01f5, 0x00040508, 0x4cffb510, 0x4280f04f, 0xf9b41510, 0xf7f11000, 0xf00cfdb0, 
+    0xb168fa86, 0x22112300, 0x3100f44f, 0x4071f04f, 0xfd6af019, 0xf7f92001, 0x200ef9a7, 0xbd108020, 
+    0x80202007, 0x220048f2, 0xf99049f2, 0x54ca3000, 0x3001f990, 0x54ca2201, 0x3002f990, 0x54ca2202, 
+    0x0003f990, 0x540a2203, 0x4010e8bd, 0xb9ddf00c, 0xf04f48e6, 0xb5104280, 0x1000f9b0, 0xf7f11510, 
+    0x48e5fd7e, 0xfd11f7fa, 0x200049e3, 0x2301221e, 0x4010f931, 0xdb012c1e, 0x2010f821, 0x4010f931, 
+    0xdc012c01, 0x3010f821, 0xb2401c40, 0xdbef2804, 0x4ad748da, 0x780349da, 0xf7fa48d7, 0x2172fd15, 
+    0x0080f44f, 0xfd35f7f1, 0x4010e8bd, 0xbddcf006, 0x41f0e92d, 0xf04f4ecd, 0x15104280, 0x1000f9b6, 
+    0xfd4df7f1, 0xf8daf7ff, 0xf7f92000, 0x48cdf94d, 0x0000f990, 0xd0011c40, 0xe01f2012, 0xf2404dca, 
+    0xf8df2700, 0xf9958328, 0x1c400000, 0xeb0017c1, 0xf0217191, 0x1a400103, 0x24007028, 0xb1087828, 
+    0xe0004639, 0x46204641, 0xfe8bf7fd, 0xb2641c64, 0xdbf32c04, 0x28007828, 0x2007d101, 0xe8bd8030, 
+    0xe92d81f0, 0xa0ba4ff0, 0xb08d4fbb, 0x1000e9d0, 0x100be9cd, 0x683d48b9, 0x28126800, 0xf648d314, 
+    0x9004409c, 0x30adf646, 0xf2429005, 0x9006707a, 0x1029f241, 0xf6409007, 0x90083063, 0x40e7f240, 
+    0xf2409009, 0xe01320a9, 0x30a4f244, 0xf2439004, 0x9005401c, 0x4016f241, 0xf6409006, 0x9007003d, 
+    0x505bf240, 0xf2409008, 0x9009207f, 0x104df240, 0xb258f8df, 0x4a00f240, 0xf04f900a, 0x46564280, 
+    0xf9bb4650, 0xf7f11000, 0x2100fcda, 0x2000f44f, 0xfc88f7f8, 0x24052101, 0x1e8a0208, 0x6102e9cd, 
+    0x0400e9cd, 0x23006838, 0xf00c2108, 0x2200fe3f, 0x46114613, 0xeb052000, 0xf9372741, 0x1c406010, 
+    0x28ffb280, 0x2386fbc6, 0x1c49d9f7, 0x2904b2c9, 0x9804d3f0, 0x4e8a0c95, 0x3583ea45, 0xd80142a8, 
+    0xe0337034, 0x70302000, 0xa8044604, 0x0184eb00, 0x42a96849, 0xf850d822, 0xeb007024, 0x68400084, 
+    0xf01b1a38, 0x4680fcb3, 0x1b784689, 0xfcaef01b, 0x460f4605, 0x1901a80b, 0x78495d04, 0xf01b1b08, 
+    0x462afc8e, 0xf01b463b, 0x4642fcf1, 0xf01b464b, 0xf01bfad1, 0x4420fc57, 0xe0037030, 0xb2a41c64, 
+    0xd3d32c06, 0xb9087830, 0x70302064, 0xf6407830, 0x46540100, 0x70303023, 0xf7f14650, 0x7831fc22, 
+    0xf7f14620, 0x2100fc0d, 0xf0092001, 0x4c65fc9d, 0x4e5a2500, 0x46204a56, 0x80e54959, 0x806580a5, 
+    0x78338025, 0xfc10f7fa, 0x0880f44f, 0x46402172, 0xfc2ff7f1, 0x22004f5c, 0x46382101, 0xfc39f019, 
+    0x2201b988, 0x21024638, 0xfc33f019, 0x2202b958, 0x21044638, 0xfc2df019, 0x2203b928, 0x21084638, 
+    0xfc27f019, 0x2001b110, 0xff06f7fb, 0xf2402202, 0x210710c3, 0xfc76f00d, 0xf7fa484a, 0xf9bbfbc6, 
+    0x20001002, 0x2010f934, 0xdb01428a, 0x1010f824, 0xb2401c40, 0xdbf52804, 0x4a357833, 0x48414938, 
+    0xfbd2f7fa, 0x46402172, 0xfbf3f7f1, 0xf00d2002, 0x2000fc53, 0xfd07f7fa, 0xf7fb2000, 0x2100fba5, 
+    0xf0092001, 0x2100fc41, 0x2000f44f, 0xfbbaf7f8, 0xf00d2004, 0x4935fe7d, 0x21007008, 0x4608460a, 
+    0xe9cd9502, 0xf7f71100, 0x2100fc8f, 0xf0094608, 0xb00dfc2b, 0x8ff0e8bd, 0xf04f481c, 0xf9b04280, 
+    0x15101000, 0xbbebf7f1, 0xb5102101, 0x4620028c, 0xfb97f7f1, 0x11f4f240, 0xf7f14620, 0x4924fb92, 
+    0xf0406808, 0x462041f0, 0xfb7af7f1, 0x46204921, 0xfb76f7f1, 0x201e490d, 0x20018048, 0xfcb2f7f9, 
+    0x2400480b, 0xf990490b, 0x548c2000, 0x3001f990, 0x54ca2201, 0x3002f990, 0x54ca2202, 0x0003f990, 
+    0x540a2203, 0xf811f00c, 0xe0254807, 0x00040648, 0x00040520, 0x00040518, 0x00040540, 0x0004057b, 
+    0x0004054e, 0x0004022e, 0x00040508, 0xfffffa00, 0x321e0a05, 0x0064503c, 0x000401dc, 0x000401f0, 
+    0x00040504, 0x00040538, 0xf20305c2, 0x00040205, 0x00057f78, 0xdcba01f5, 0xbd107004, 0x5ff0e92d, 
+    0x8e804604, 0xf2404dfc, 0xf8df1b4e, 0x4558a3f0, 0x1801f240, 0x1967f240, 0xdc32d074, 0xf2a04540, 
+    0xd0641101, 0x28e6dc16, 0xdc05d06d, 0x28c4b318, 0x28c5d06c, 0xe073d169, 0xd05828e7, 0x7f80f5b0, 
+    0x49edd163, 0x68682200, 0xf0153108, 0x1d40f8f8, 0xe04cd07e, 0xd04a291c, 0x2909dc0e, 0x290ad079, 
+    0x291bd045, 0x49e4d151, 0x68682200, 0xf0153108, 0x1d40f8e6, 0xe03ad06e, 0xd06c2943, 0xd1442944, 
+    0x4548e035, 0x1167f2a0, 0xdc1ad031, 0x7faff5b0, 0xdc07d07e, 0x0018f111, 0x2807d029, 0x2808d079, 
+    0xe024d133, 0x7080f5a0, 0xd020385f, 0xd12c2807, 0x220049d1, 0x31086868, 0xf8c1f015, 0xd0691d40, 
+    0x2910e015, 0xdc0ed013, 0xd06e2907, 0xd00e2908, 0xd11a290f, 0x220049c8, 0x31086868, 0xf8aff015, 
+    0xd07c1d40, 0x291be003, 0x291cd07a, 0x49c2d10d, 0x32fff04f, 0x31086868, 0xf8d0f015, 0xd10b1d01, 
+    0xe1c320c4, 0xe080e11d, 0xe0aae000, 0x220049ba, 0x31086868, 0xf8c2f015, 0xd0471d41, 0xd1e62801, 
+    0x27004eb5, 0x4000f240, 0xf9b63608, 0x290f1000, 0x0502d03e, 0xd0412911, 0xd1d8290a, 0x1000f9b5, 
+    0x29024faf, 0x2901d06b, 0x2903d07d, 0xe003d07c, 0xe09ce085, 0xe0dae0bd, 0xd0762904, 0xd0752905, 
+    0xd0742906, 0xd0732907, 0xd0722910, 0xd0712912, 0xd0702908, 0xd1ba290e, 0xfad1f7f1, 0x0170f242, 
+    0xf7f106c8, 0x200bfa8a, 0x200f8030, 0xe0028028, 0xe0f6e111, 0xf8dae13a, 0xf04f0000, 0x463132ff, 
+    0xf84df015, 0xd0711d01, 0xe140e16c, 0xe16d20c5, 0x4224f04f, 0xfab3f7f1, 0xe798802f, 0xf9934b91, 
+    0x2b033000, 0x2b05d003, 0x2b04d001, 0x4b8ed102, 0xb133781b, 0x802f2113, 0xfaa1f7f1, 0xe145e787, 
+    0xf04fe14a, 0xf7f14220, 0xf7fffa9a, 0x4982fead, 0x80282002, 0x8030200a, 0x68682200, 0xf0153108, 
+    0x1d01f81e, 0x20e6d107, 0x497be140, 0x68682200, 0xf0153108, 0x1d40f814, 0x20e7d1cf, 0x7838e136, 
+    0xd1022801, 0xf7f82002, 0xf7fff9d6, 0x4972fe85, 0x80282001, 0x68682200, 0xf0153108, 0x1d01f800, 
+    0xaf05f47f, 0xe00ee008, 0xe045e02c, 0xe083e06a, 0xe0bbe0a2, 0xe0f4e0dd, 0x1000f240, 0xf8a4e116, 
+    0xe8bd8034, 0xf7f19ff0, 0x2100fa5a, 0xf0092001, 0x4961fa8b, 0x80282003, 0x68682200, 0xf0143108, 
+    0x1d01ffde, 0xf240d109, 0xe0ff100a, 0x495ae0f1, 0x68682200, 0xf0143108, 0x1d40ffd2, 0xf240d18d, 
+    0xe0f3100b, 0xfa3bf7f1, 0xf44f2100, 0xf7f81080, 0xf005f9e9, 0x4950feab, 0x80282004, 0x68682200, 
+    0xf0143108, 0x1d01ffbc, 0xaed3f47f, 0x101cf240, 0xf240e0dc, 0xe0d9101d, 0xfa21f7f1, 0x46082100, 
+    0xfa52f009, 0x28017838, 0x4943d00a, 0x80282005, 0x68682200, 0xf0143108, 0x1d01ffa2, 0xe00cd004, 
+    0xf7f82002, 0xe6f2f968, 0x1044f240, 0x493ae0be, 0x68682200, 0xf0143108, 0x1d40ff92, 0xf240d1f3, 
+    0xe0b31045, 0xf91ef000, 0x20064933, 0x22008028, 0x31086868, 0xff83f014, 0xd1081d01, 0xb034f8a4, 
+    0x492de78f, 0x68682200, 0xf0143108, 0x1d40ff78, 0xf240d1d9, 0xe099104f, 0xf8a9f000, 0xf7f82002, 
+    0xb108f94f, 0xe000200a, 0x4923200f, 0x22008030, 0x31086868, 0xff63f014, 0xd1081d01, 0x1056f240, 
+    0x491de084, 0x68682200, 0xf0143108, 0x1d40ff58, 0xf240d1b9, 0xe0791057, 0xfca3f7ff, 0x20104916, 
+    0x22008028, 0x31086868, 0xff49f014, 0xd1081d01, 0x105ef240, 0x4910e06a, 0x68682200, 0xf0143108, 
+    0x1d40ff3e, 0xf240d19f, 0xe05f105f, 0xfc50f7ff, 0xf7f82002, 0xb108f915, 0xe000200a, 0x4906200f, 
+    0x22008030, 0x31086868, 0xff29f014, 0xf47f1d01, 0xf240ae65, 0xe0491066, 0x00040648, 0x000406cc, 
+    0x00040234, 0x00040242, 0x000402a4, 0x9034f8a4, 0xf7ffe727, 0x2008fbfd, 0x496c8028, 0x68682200, 
+    0xff0df014, 0xd1071d01, 0x106ef240, 0x4967e02e, 0x68682200, 0xff03f014, 0xd1891d40, 0x106ff240, 
+    0xf7ffe024, 0x2002fbb3, 0xf8daf7f8, 0x200ab108, 0x200fe000, 0x495d8030, 0x68682200, 0xfeeff014, 
+    0xf47f1d01, 0xf240ae3d, 0xe00f1076, 0x1077f240, 0xf240e00c, 0xe0091082, 0x22004954, 0x0000f8da, 
+    0xfeddf014, 0xd19d1d40, 0x1083f240, 0xe6e886a0, 0x21012200, 0xf2afb510, 0xf014409b, 0x2108fd1b, 
+    0xf0142003, 0x4949fe79, 0x60483908, 0xb5f8bd10, 0x90002000, 0xf7fa4668, 0x4845fb69, 0x28037800, 
+    0x4844d110, 0x2000f990, 0x3002f990, 0x2002f81d, 0x2003f80d, 0x2001f990, 0x0003f990, 0x2002f81d, 
+    0x2000f80d, 0x0000f89d, 0xd03a2800, 0x0001f89d, 0xd0362800, 0x0002f89d, 0xd0322800, 0x0003f89d, 
+    0xd02e2800, 0x0410f242, 0x06e54621, 0xf7f14628, 0x2000f8c4, 0xfd08f7f8, 0x22074b2c, 0x3b084e2e, 
+    0x801a4630, 0x22002301, 0xf0194619, 0x2301f8d4, 0x21024630, 0xf019461a, 0x2301f8ce, 0x22024630, 
+    0xf0192104, 0x2301f8c8, 0x22034630, 0xf0192108, 0x4822f8c2, 0x28106800, 0x4621d803, 0xf7f14628, 
+    0xbdf8f89c, 0xb50e4819, 0xf04f3808, 0xf9b04280, 0x15101000, 0xf8d3f7f1, 0x20004919, 0x70084a1c, 
+    0x70084918, 0x70084918, 0x70084918, 0x70112101, 0x49184602, 0x49187008, 0x46017008, 0x0000e9cd, 
+    0x20019002, 0xf950f7f7, 0x0140f242, 0xf7f10648, 0xf7faf874, 0x2001f8e2, 0xfcb6f7f8, 0x2100b003, 
+    0x2000f44f, 0xeb04f85d, 0xb85cf7f8, 0x00040650, 0x0004057b, 0x00040520, 0xf2035018, 0x000401f0, 
+    0x00040223, 0x00040221, 0x0004021c, 0x0004021f, 0x00040203, 0x00040201, 0x000401fe, 0x5ff0e92d, 
+    0x46044da9, 0x4ea98e80, 0x686b28c8, 0xdc15d070, 0xd0342893, 0xb300dc0d, 0xd16a2892, 0x46182200, 
+    0x0108f105, 0xfe3af014, 0xd0261d41, 0xd1192801, 0x28b4e025, 0x28b5d06f, 0xe013d15b, 0xd01128d1, 
+    0x28c9dc0c, 0x28d0d00e, 0x4997d153, 0x46182200, 0xf0143108, 0x1d40fdf4, 0xe003d07e, 0xd07c28da, 
+    0xd14628db, 0xf04f4990, 0x686832ff, 0xf0143108, 0x1d01fe15, 0x2092d1d8, 0x2093e0c0, 0xf8dfe0be, 
+    0x27008228, 0x2000f240, 0x0808f108, 0x1000f9b8, 0xd027290f, 0xf04f2912, 0xf04f090a, 0xf04f5240, 
+    0xd0274b00, 0xd1dd290a, 0x1000f9b5, 0xf837f7f1, 0x0000f9b5, 0xd06d2802, 0xd077280a, 0xd1d12806, 
+    0x0170f242, 0xf7f04658, 0x200bffe8, 0x0000f8a8, 0x80282007, 0x1e7a6830, 0xf0144641, 0x1d01fdb0, 
+    0xe088d06f, 0x4223f04f, 0xf819f7f1, 0xe7b9802f, 0xe084e05d, 0xf9934b6e, 0x2b033000, 0x2b05d003, 
+    0x2b04d001, 0x4b6bd102, 0xb12b781b, 0x802f2109, 0xf805f7f1, 0xe033e7a6, 0x4a20f04f, 0x46524607, 
+    0xfffdf7f0, 0x465221f1, 0xf7f04638, 0xf242fff8, 0x46580150, 0xffb1f7f0, 0xf7f82000, 0x485efbf5, 
+    0xf44f7801, 0xf7f72080, 0xf44fff9d, 0xf6403000, 0xf7f00103, 0xe001ff96, 0xe046e043, 0xff25f7fc, 
+    0xf8dff7f9, 0x20024950, 0x22008028, 0x9000f8a8, 0x68683108, 0xfd63f014, 0xd1071d01, 0xe03d20b4, 
+    0x22004949, 0x31084618, 0xfd59f014, 0xd1ae1d40, 0xe03320b5, 0x22004944, 0x9000f8a5, 0x31086868, 
+    0xfd4df014, 0xd1081d01, 0xe02720c8, 0x493ee00a, 0x46182200, 0xf0143108, 0x1d40fd42, 0x20c9d197, 
+    0xe010e01c, 0xf82bf000, 0x20064937, 0x22008028, 0x31086868, 0xfd33f014, 0xf47f1d01, 0x20d0af3c, 
+    0x20d1e00c, 0x20dae00a, 0x492fe008, 0x68302200, 0xf0143108, 0x1d40fd24, 0x20dbd18c, 0xe8bd86a0, 
+    0x22009ff0, 0xb5102101, 0x200ff2af, 0xfb62f014, 0x20032108, 0xfcc0f014, 0x60484923, 0xb570bd10, 
+    0x20012100, 0xffb0f008, 0xf44f2100, 0xf7f72000, 0x2100ff29, 0xf0084608, 0x4c20ffa7, 0x46082100, 
+    0x2000f994, 0xffe6f7f9, 0x0550f242, 0x06ee4629, 0xf7f04630, 0xf005ff22, 0x4629fbd9, 0xf7f04630, 
+    0x2100ff1c, 0xf7fa2001, 0xf994f9e0, 0x21002000, 0xf7f9200c, 0x2101ff89, 0x2000f994, 0xf7f94608, 
+    0xf7fdffc9, 0x4629f867, 0xf7f04630, 0x2300ff06, 0x0bb12211, 0x4071f04f, 0xff06f018, 0x4070e8bd, 
+    0xf7f82001, 0x0000bb41, 0x00040658, 0x000406cc, 0x00040242, 0x000402a4, 0x00040243, 0x00040248, 
+    0x43fee92d, 0x4900f04f, 0x0870f242, 0x46412600, 0xf7f04648, 0x2000fee2, 0xfb26f7f8, 0x270148fa, 
+    0x463a4cfa, 0x70074dfa, 0x80200278, 0x90022000, 0x0104e9d5, 0x0100e9cd, 0x46384639, 0xffa4f7f6, 
+    0x4af549f4, 0x78084bf7, 0x48f47010, 0x70087800, 0x680a49f3, 0x2a1049f4, 0x4af4d906, 0x2a017812, 
+    0x780ad102, 0xd0032a05, 0x2a03780a, 0xe004d013, 0x78124aef, 0xd1002a01, 0x97001e96, 0xeb06780a, 
+    0x781b0040, 0xb2402100, 0xfdd8f00b, 0x46484641, 0xfea3f7f0, 0x2203e015, 0x00409700, 0x2002e7f1, 
+    0xfe4ef7f7, 0xd0092801, 0x46204ce2, 0xfe96f018, 0x7180f440, 0xf0184620, 0xe005fe94, 0xff40f7f6, 
+    0x88208020, 0xd1ea2800, 0x1000f9b5, 0xf04fb003, 0xf64042a0, 0xe8bd0000, 0xf7f043f0, 0xe92dbec0, 
+    0x250043fe, 0xf83af00b, 0x48d449d3, 0xfc68f018, 0xf6402801, 0xd01a0900, 0x464c21e2, 0xf7f04648, 
+    0x2100fe60, 0xf7f04620, 0xf242fe4b, 0x462001d0, 0xfe63f7f0, 0x780048ca, 0xd0702801, 0x48c92100, 
+    0xf201b003, 0xe8bd312e, 0xf01843f0, 0x4ebdbe5a, 0xf7fe7830, 0x4cc1f8a4, 0x79e049c3, 0x00c0f3c0, 
+    0x28007008, 0xf242d06f, 0x06c80170, 0xfe45f7f0, 0xf7f82000, 0xf44ffa89, 0xf6403000, 0xf7f00103, 
+    0xf7fcfe30, 0x7a22fdc2, 0x82e0f8df, 0xf0027a60, 0xea400203, 0x28402002, 0x0000f8a8, 0x2002d973, 
+    0xfdd8f7f7, 0x48b24601, 0x68004cb3, 0x49b11a43, 0x2000f9b1, 0xf1f2fbb3, 0x60211cc9, 0x43511e89, 
+    0xfe16f7f7, 0x27014898, 0x7007463a, 0x4c978821, 0x0000f8b8, 0x8258f8df, 0x80201a40, 0x90022000, 
+    0x1004e9d8, 0x1000e9cd, 0x46384639, 0xfedcf7f6, 0x4a914990, 0x70107808, 0x78004890, 0x49907008, 
+    0x4991680a, 0xd9062a10, 0x78124a90, 0xd1022a01, 0x2a05780a, 0x780ad004, 0xd0102a03, 0xe034e005, 
+    0x78124a8b, 0xd1002a01, 0x97001e95, 0xeb05780a, 0x78330040, 0xb2402100, 0xfd10f00b, 0x2203e016, 
+    0x00409700, 0xe01ee7f5, 0xf7f72002, 0x2801fd89, 0x4c80d009, 0xf0184620, 0xf040fdd1, 0x46200180, 
+    0xfdcff018, 0xf7f6e005, 0x8020fe7b, 0x28008820, 0xf9b8d1ea, 0xf04f1000, 0x464442a0, 0xf7f04648, 
+    0x2007fdfe, 0xe8bd8020, 0xf24283fe, 0xe7567110, 0x41f0e92d, 0xff72f00a, 0x4870496f, 0xfba0f018, 
+    0x28014e6f, 0x0500f640, 0x21e2d017, 0xf7f04628, 0x2100fd98, 0xf7f04628, 0xf242fd83, 0x462801d0, 
+    0xfd9bf7f0, 0x28017830, 0x2100d03f, 0xe8bd4865, 0xf50141f0, 0xf018714b, 0x485abd94, 0xf7fd7800, 
+    0x4c53ffde, 0x42a0f04f, 0xf9b44628, 0xf7f01000, 0x485afdc6, 0x0702f04f, 0x4d614a60, 0x09c87901, 
+    0xd0017010, 0xb1387830, 0x28017830, 0x2004d11b, 0xf82ef00d, 0xe0157028, 0x1002f3c1, 0x70084959, 
+    0xf00d2004, 0xb2c0f825, 0x78317028, 0x4956b951, 0x1c8a7809, 0xd9014290, 0xe003702a, 0x42881e89, 
+    0x7029da00, 0xe8bd8027, 0xf24281f0, 0xe7bd7110, 0xb5fe483b, 0x28126800, 0x2100d304, 0x1080f44f, 
+    0xfd40f7f7, 0x20014949, 0x4c314e36, 0x78307008, 0xd0042801, 0xd0022802, 0x46012000, 0x4d32e041, 
+    0x78284f43, 0xd1052805, 0x46382201, 0xf0182102, 0xb940fd60, 0x28047828, 0x2200d107, 0x21014638, 
+    0xfd57f018, 0x2001b108, 0x2000e000, 0x17c101c0, 0x0104e9c4, 0x28017830, 0x4e35d11e, 0x3e3c7828, 
+    0xd1052805, 0x46302206, 0xf0182140, 0xb940fd42, 0x28047828, 0x2205d107, 0x21204630, 0xfd39f018, 
+    0x2001b108, 0x2000e000, 0x2304e9d4, 0x17c10140, 0x43194310, 0x0104e9c4, 0x02096920, 0x6110ea41, 
+    0x22000200, 0x0104e9c4, 0x90022000, 0x0104e9d4, 0x0100e9cd, 0x46112001, 0xfdc6f7f6, 0x491d4819, 
+    0x70087800, 0x0000bdfe, 0x0004021f, 0x00040226, 0x00040668, 0x00040209, 0x0004020a, 0x00040207, 
+    0x000401f0, 0x0004057b, 0x00040242, 0x000402b2, 0x0004031a, 0xf203517c, 0x0002b868, 0x000413d8, 
+    0x00040502, 0xf23c80ba, 0x00040220, 0x00040228, 0x00040230, 0x00040588, 0x00040514, 0x00040212, 
+    0x00040205, 0x0004020b, 0x00040206, 0x000401fe, 0xf38e007c, 0x0004020c, 0x4ffee92d, 0x8e804604, 
+    0xf2404dff, 0xf5b01b1d, 0xd07d7f80, 0x28d3dc1b, 0xdc0fd038, 0x28a4b368, 0x28a5d03f, 0x28d2d047, 
+    0x6868d173, 0xf1052200, 0xf0140108, 0x1d40fa68, 0xe027d06c, 0xd06a28e4, 0xd02328e5, 0xd06728ec, 
+    0xd16228ed, 0x4558e01e, 0x111df2a0, 0xdc11d01a, 0x001cf111, 0x2813d016, 0x2814d07c, 0x281bd012, 
+    0x49e7d153, 0x68682200, 0xf0143108, 0x1d40fa48, 0xe007d071, 0xd06f2907, 0xd0032908, 0xd06c2911, 
+    0xd1422912, 0xf04f49de, 0x686832ff, 0xf0143108, 0x1d01fa65, 0x20a4d107, 0x49d9e154, 0x68682200, 
+    0xf0143108, 0x1d41fa5b, 0x2801d03b, 0x4ed4d1ea, 0xf6402700, 0x36080000, 0x1000f9b6, 0xd032290f, 
+    0x8340f8df, 0xf04f2913, 0xf04f42a0, 0xf04f0901, 0xd02e0a03, 0xd1d5290a, 0x1000f9b5, 0xd05a2901, 
+    0xd07b2903, 0xd0752902, 0xd0742904, 0xd0732905, 0xd0722906, 0xd1c52907, 0xf934f000, 0x8030200b, 
+    0x80282009, 0xe0041e7a, 0xe0f1e0ae, 0xe056e041, 0x48bde079, 0x68004631, 0xf9f1f014, 0xd0711d01, 
+    0x20a5e10c, 0xf04fe10e, 0xf7f04225, 0x802ffc58, 0x4bb6e7a8, 0x3000f993, 0xd0032b03, 0xd0012b05, 
+    0xd1022b04, 0x781b4bb2, 0x210ab143, 0xf7f0802f, 0xe797fc46, 0xe0c9e0a9, 0xe0e8e0db, 0x4220f04f, 
+    0xfc3df7f0, 0xfea4f7ff, 0x0000f898, 0xf8a5b170, 0x200a9000, 0x220049a2, 0x68688030, 0xf0143108, 
+    0x1d01f9be, 0xaf53f47f, 0xe0db20d2, 0xa000f8a5, 0x20d3e7ef, 0xf7ffe0d6, 0x2002fe2b, 0xfb90f7f7, 
+    0x200ab108, 0x200fe000, 0x80304995, 0x68682200, 0xf0143108, 0x1d01f9a4, 0x20e4d107, 0x4990e0c2, 
+    0x68682200, 0xf0143108, 0x1d40f99a, 0x20e5d1b0, 0xe003e0b8, 0xe052e021, 0xe08be072, 0xf94af000, 
+    0xf7f72002, 0xb108fb6d, 0xe000200a, 0x4984200f, 0x22008030, 0x31086868, 0xf981f014, 0xd1081d01, 
+    0xe09f20ec, 0x497ee090, 0x68682200, 0xf0143108, 0x1d40f976, 0x20edd18c, 0xf7f0e094, 0x497dfbe0, 
+    0xf8812201, 0x497c9000, 0x9000f881, 0xe9d59702, 0xe9cd0104, 0x21000100, 0xf7f64610, 0xf898fc65, 
+    0x28010000, 0x2004d00a, 0x496d8028, 0x68682200, 0xf0143108, 0x1d01f954, 0xe00bd003, 0xa000f8a5, 
+    0xf240e7f3, 0xe06d1000, 0x22004965, 0x31086868, 0xf945f014, 0xd1a91d40, 0x1001f240, 0xf000e062, 
+    0xf898f89c, 0x28010000, 0x2005d00a, 0x8028495c, 0x68682200, 0xf0143108, 0x1d01f932, 0xe00ad002, 
+    0xe7f32006, 0x1014f240, 0x4955e04c, 0x68682200, 0xf0143108, 0x1d40f924, 0xf240d188, 0xe0411015, 
+    0xfccdf7ff, 0xf7f72002, 0xb108fafb, 0xe000200a, 0x494b200f, 0x22008030, 0x31086868, 0xf90ff014, 
+    0xf47f1d01, 0xf240aec4, 0xe02b101c, 0xb034f8a4, 0x8ffee8bd, 0xfc44f7ff, 0x20074941, 0x22008028, 
+    0x31086868, 0xf8fbf014, 0xd1081d01, 0x1024f240, 0x493be018, 0x68682200, 0xf0143108, 0x1d40f8f0, 
+    0xf240d1a9, 0xe00d1025, 0x102ef240, 0x4836e00a, 0x49332200, 0x68003108, 0xf8e1f014, 0xd19a1d40, 
+    0x102ff240, 0xe7d386a0, 0x21012200, 0xf2afb510, 0xf0133057, 0x2108ff1f, 0xf0142003, 0x4928f87d, 
+    0xbd106048, 0xf04f4826, 0xb51042a0, 0x0400f640, 0x1000f9b0, 0xf7f04620, 0xf240fb32, 0x46202101, 
+    0xfadff7f0, 0x24004825, 0x49274a26, 0x808480c4, 0x80048044, 0x78034822, 0xf7f94820, 0x2172fad5, 
+    0x0080f44f, 0xfaf5f7f0, 0x21004820, 0xf44f7004, 0xe8bd3080, 0xf7f74010, 0xb5febac5, 0xf6404c10, 
+    0xf04f0600, 0x463042a0, 0x1000f9b4, 0xfb07f7f0, 0x463010b1, 0xfab5f7f0, 0x20014915, 0x22014d16, 
+    0x48147008, 0x70287800, 0x90022000, 0x0104e9d4, 0x0100e9cd, 0x46104611, 0xfb86f7f6, 0xe01f4c0f, 
+    0x00040668, 0x00040502, 0x000406cc, 0x00040242, 0x000402a4, 0x00040211, 0x0004020d, 0x00040538, 
+    0x0004057b, 0x00040520, 0x0004054e, 0x00040556, 0x0004020f, 0x00040206, 0x00040207, 0x00040205, 
+    0x22034f30, 0x21387823, 0xf0184638, 0x782bfaa4, 0x21072200, 0xf0184638, 0x7829fa9e, 0xf7f04630, 
+    0x7821fa5f, 0xf7f04630, 0xe8bdfa5b, 0x482640fe, 0xba4bf7f9, 0x41f0e92d, 0xfc30f00a, 0x48244923, 
+    0xf85ef018, 0x28014c23, 0x0600f640, 0x21e2d017, 0xf7f04630, 0x2100fa56, 0xf7f04630, 0xf242fa41, 
+    0x463001d0, 0xfa59f7f0, 0x28017820, 0x2100d026, 0xe8bd4819, 0xf20141f0, 0xf018312d, 0x4817ba52, 
+    0xf7fd7800, 0x4d12fc9c, 0x09c179a8, 0x70014814, 0x4f14d011, 0x42a0f04f, 0xf9b74630, 0xf7f01000, 
+    0x4911fa7e, 0xf3c079a8, 0x70081002, 0x28017820, 0x2001d002, 0xe4d68038, 0xe7fb2004, 0x7110f242, 
+    0x0000e7d6, 0xf203501a, 0x00040530, 0x0002b868, 0x000413d8, 0x00040502, 0xf23c80ba, 0x0004057b, 
+    0x0004020e, 0x00040668, 0x00040206, 0x43fee92d, 0xf04f48fe, 0xf9b042c0, 0xf2411002, 0xf7f00000, 
+    0x49fbfa4e, 0x22012000, 0x46117008, 0x0000e9cd, 0x46109002, 0xfad8f7f6, 0xf6404cf6, 0x46400800, 
+    0xf7f77821, 0xf242f9ef, 0x46310680, 0x46380637, 0xf9f3f7f0, 0xf9954df0, 0x29051000, 0x2903d02b, 
+    0xb111d029, 0xf0032007, 0x7821f9e5, 0xf7f74640, 0x4631f9d9, 0xf7f04638, 0x48e8f9e0, 0x68004ce8, 
+    0xd80c2811, 0x28017820, 0x2047d109, 0x0000f8ad, 0xf99548e4, 0x68021000, 0xf0124668, 0x7820fb03, 
+    0xd1212800, 0xfc1af7fc, 0xf99048df, 0xe8bd0000, 0xf7fc43fe, 0x2905b96e, 0x2903d002, 0xe00cd007, 
+    0xf8ad204d, 0x46680000, 0xfce4f012, 0x204ae005, 0x0000f8ad, 0xf0124668, 0x2007f912, 0xf9aaf003, 
+    0x46407821, 0xf99ef7f7, 0x83fee8bd, 0x4ffee92d, 0x240048ce, 0x4dc849c6, 0x20017004, 0xf9957008, 
+    0xb1380000, 0x4eca2140, 0x49ca8031, 0x29047809, 0xe014d003, 0x2100f240, 0xb180e7f5, 0xf2402020, 
+    0x803011f4, 0x463804c7, 0xf97bf7f0, 0x31baf64b, 0xf7f04638, 0x49c0f965, 0xf7f04638, 0x48bff961, 
+    0x28027800, 0x01c0d101, 0x4eb48030, 0x28106830, 0x2000d802, 0xfdb8f7f7, 0x94022100, 0x46102201, 
+    0x1100e9cd, 0xf7f64611, 0x2101fa3f, 0xf7f82000, 0x200ffa65, 0xfa1df7f6, 0x4900f04f, 0x0780f242, 
+    0x46484639, 0xf959f7f0, 0xf7f72002, 0x4604f903, 0x0000f995, 0xd01c2805, 0xd01a2803, 0xf0092000, 
+    0x2002ff56, 0xf8f6f7f7, 0x1a214aa5, 0x825cf8df, 0x7a504ca4, 0xf0027a12, 0xea400203, 0xf8d82002, 
+    0x1a892004, 0x3011eba0, 0x20008020, 0xfd7cf7f7, 0x2001e009, 0xffb3f009, 0x2000e7e3, 0xffaff009, 
+    0x1e408820, 0x88208020, 0xd8f62801, 0x464c4639, 0xf7f04648, 0x6830f922, 0xd8032811, 0xf00c2003, 
+    0xe002f99b, 0xf00c2004, 0x46baf999, 0x46a14639, 0xf7f04620, 0x2001f912, 0xf9cbf7f6, 0x0000f995, 
+    0xd0012805, 0xd1152803, 0x25004f87, 0xeb072400, 0x46211645, 0xf9364628, 0xf00c2014, 0x1c64fb24, 
+    0x2c10b2e4, 0x1c6dd3f5, 0x2d04b2ed, 0x2003d3ee, 0xfb2af00c, 0x46484651, 0xf8eff7f0, 0x1002f9b8, 
+    0xf04fb003, 0xf24142c0, 0xe8bd0000, 0xf7f04ff0, 0xe92db926, 0x4e684ffe, 0x0000f996, 0x2420b128, 
+    0x7809496c, 0xd0022904, 0x2440e012, 0xb178e7f8, 0xf2402410, 0x052511f4, 0xf7f04628, 0xf64bf8c2, 
+    0x462831ba, 0xf8acf7f0, 0x46284963, 0xf8a8f7f0, 0x9188f8df, 0x0000f899, 0xd1002802, 0xf9962440, 
+    0x28050000, 0x2803d035, 0x2000d033, 0xfebff009, 0x485b495e, 0xfea4f017, 0xd02e2801, 0xf2414c5c, 
+    0x21e20500, 0x1c406820, 0x46286020, 0xf899f7f0, 0x46286821, 0xf884f7f0, 0x01d0f242, 0xf7f04628, 
+    0x4847f89c, 0x28017800, 0x2100d07e, 0xf5014851, 0xf018714c, 0x4850f896, 0x78004950, 0x0007f000, 
+    0x1000eb00, 0x2020f851, 0xf8411c52, 0xe8bd2020, 0x20018ffe, 0xff03f009, 0x4f41e7ca, 0x79f84948, 
+    0x0040f3c0, 0x28007008, 0x7a39d0f1, 0x7a784d3d, 0x0103f001, 0x2001ea40, 0x802842a0, 0x2002dde7, 
+    0xf818f7f7, 0x483f4601, 0x68004c40, 0x493e1a43, 0x2000f9b1, 0xf1f2fbb3, 0x60211cc9, 0x43511e89, 
+    0xf856f7f7, 0x20014922, 0x70082201, 0x88218828, 0x49271a40, 0x20008008, 0x90024611, 0x0000e9cd, 
+    0xf7f64610, 0x2101f921, 0xf7f82000, 0xf7f9f947, 0x200ff8b4, 0xf8fdf7f6, 0x4a00f04f, 0x0b80f242, 
+    0x46504659, 0xf839f7f0, 0xb9607830, 0x21004c16, 0xf994200c, 0xf7f92000, 0x2101f8a7, 0x2000f994, 
+    0xf7f94608, 0x2002f8e7, 0xffd4f7f6, 0xf9964604, 0x28050000, 0x2803d052, 0x2000d050, 0xfe27f009, 
+    0xf7f62002, 0xe033ffc7, 0x0000e0a1, 0x00040680, 0x00040221, 0x00040243, 0x00040ed8, 0x000401f0, 
+    0x00040502, 0x00040ef8, 0x00040248, 0x0004021f, 0x00040226, 0x00040242, 0xdcba01f5, 0x00040556, 
+    0x000413d8, 0x00040228, 0x0004d168, 0x0002b868, 0x0004029c, 0xf23c80ba, 0x00040ef4, 0x00041698, 
+    0x00040222, 0x00040230, 0x00040588, 0x00040514, 0x1a207a3a, 0xf0027a79, 0xea410203, 0x4ffe2102, 
+    0x1a80687a, 0x3010eba1, 0x0103f640, 0xf44f8028, 0xf7ef3000, 0xf7fbffc6, 0xe009ff58, 0xf0092001, 
+    0xe7adfe4e, 0xf0092000, 0x8828fe4a, 0x80281e40, 0x28018828, 0x465cd8f6, 0x46554659, 0xf7ef4650, 
+    0x2004ffbc, 0xf83af00c, 0x46284621, 0xffb5f7ef, 0xf7f62001, 0xf996f86e, 0x28050000, 0x2803d001, 
+    0xf8dfd116, 0x25008398, 0xeb082400, 0x46211645, 0xf9364628, 0xf00c2014, 0x1c64f9c6, 0x2c10b2e4, 
+    0x1c6dd3f5, 0x2d04b2ed, 0x2003d3ee, 0xf9ccf00c, 0x0000f899, 0xd10b2802, 0xf6400400, 0xf7ef0103, 
+    0xf7fbff80, 0x48d6ff12, 0xff82f017, 0x600849d5, 0x46504659, 0xff81f7ef, 0x1002f9b7, 0x42c0f04f, 
+    0x0000f241, 0xffbbf7ef, 0x8078200b, 0xf242e6ef, 0xe6db7110, 0x5ff0e92d, 0x932cf8df, 0x0b00f04f, 
+    0x465d465c, 0xf99946da, 0x28050000, 0x2803d00a, 0x2001d008, 0xfd6bf009, 0x26014fc4, 0x28017838, 
+    0xe02bd004, 0xf0092001, 0xe7f5fdda, 0x0000f899, 0x48bfbb20, 0xfe87f7f8, 0x49bd48be, 0x28037800, 
+    0x48bdd110, 0x2000f990, 0x3002f990, 0x2022f851, 0x2023f841, 0x2001f990, 0x0003f990, 0x2022f851, 
+    0x2020f841, 0x20004ab5, 0x3020f851, 0xd9004293, 0x1c402600, 0x2804b2c0, 0xb12ed3f6, 0x48b149b0, 
+    0xfd1ef017, 0xd0082801, 0x68204caf, 0x60201c40, 0x0008f3c0, 0xd07d2801, 0xf8dfe1a9, 0x49ab82a8, 
+    0x0007f898, 0x0080f3c0, 0x28007008, 0x49a8d073, 0x0009f898, 0xc2a0f8df, 0xe2a0f8df, 0x700a0982, 
+    0xf3c049a4, 0x700a1201, 0x0103f000, 0x0281f3c0, 0xf88c48a3, 0xf88e2000, 0x78031000, 0xd1222b01, 
+    0x0008f898, 0x600af898, 0x000ff000, 0x0701f000, 0x2607ea46, 0x0740f3c0, 0x040ff366, 0x600bf898, 
+    0x2607ea46, 0x0780f3c0, 0x441ff366, 0x600cf898, 0xea4608c0, 0xf3662607, 0xf898050f, 0xea46600d, 
+    0xf3602000, 0x488f451f, 0x42827800, 0x488ed103, 0x42817800, 0x1e52d07e, 0xf0021e49, 0x07880703, 
+    0xb34b0f06, 0x1100f240, 0x1c48b2a2, 0xd101428a, 0x040ff360, 0x428a0c22, 0xf360d101, 0xb2aa441f, 
+    0xd101428a, 0x050ff360, 0x428a0c2a, 0xf360d101, 0xf999451f, 0x28050000, 0x2803d074, 0xb220d072, 
+    0xf0182109, 0x4240fe0b, 0xb2024631, 0xf00c4638, 0xe002f8ca, 0xe112e11c, 0x1420e01e, 0xf0182109, 
+    0x4240fdfd, 0x4638b202, 0xf00c1c71, 0xb228f8bc, 0xf0182109, 0x4240fdf3, 0x4638b202, 0xf00c1cb1, 
+    0x1428f8b2, 0xf0182109, 0x4240fde9, 0x4638b202, 0xf00c1cf1, 0xe083f8a8, 0x100af898, 0x29802081, 
+    0xf888d101, 0xf898000a, 0x2980100b, 0xf888d101, 0xf898000b, 0x2980100c, 0xf888d101, 0xf898000c, 
+    0x2980100d, 0xf888d101, 0xf999000d, 0x28050000, 0x2803d029, 0xf898d027, 0x2108000a, 0xfdbef018, 
+    0x46314240, 0x4638b202, 0xf87df00c, 0x000bf898, 0xe0002108, 0xf018e066, 0x4240fdb1, 0x4638b202, 
+    0xf00c1c71, 0xf898f870, 0x2108000c, 0xfda6f018, 0xb2024240, 0x1cb14638, 0xf865f00c, 0x000df898, 
+    0xe7b02108, 0xf898e01e, 0x2108000a, 0xfd96f018, 0x482a4241, 0x1447eb00, 0x1016f824, 0x000bf898, 
+    0xf0182108, 0xeb04fd8b, 0x42400446, 0x80602108, 0x000cf898, 0xfd82f018, 0x80a04240, 0x000df898, 
+    0xe0192108, 0x2109b220, 0xfd78f018, 0x481b4241, 0x1747eb00, 0xf8271420, 0x21091016, 0xfd6ef018, 
+    0x0446eb07, 0x21094240, 0xb2288060, 0xfd66f018, 0x80a04240, 0x21091428, 0xfd60f018, 0x80e04240, 
+    0x78184b22, 0xd00d2801, 0xf04f481b, 0x491d0a01, 0x78004a1d, 0x49197008, 0x70117809, 0xd1014308, 
+    0x70182001, 0x78304e1a, 0xd0532801, 0x4c194810, 0x78217802, 0xe02f428a, 0x00040680, 0x0004d168, 
+    0xf000812c, 0x00040558, 0x00040ed8, 0x00040502, 0x000413e8, 0x0004057b, 0x00040520, 0x0001a02b, 
+    0x0002b868, 0x000413d8, 0x0004029c, 0x0004021d, 0x00040218, 0x00040219, 0x0004021a, 0x0004021b, 
+    0x000402b2, 0x00040214, 0x00040215, 0x0004022d, 0x0004022c, 0x00040216, 0x48fed11c, 0x78004dfe, 
+    0x4298782b, 0x4302d116, 0x1c5bd007, 0x7028b2d8, 0xd3052804, 0xb000f885, 0x2001e00f, 0xe00c7030, 
+    0xd10a2801, 0xb2c81c49, 0x28047020, 0xf884d305, 0xe002b000, 0x0f00f1ba, 0x2107d008, 0x48efe004, 
+    0x28007800, 0x2108d002, 0x804148ed, 0x9ff0e8bd, 0x0500f241, 0x462821e2, 0xfd73f7ef, 0x46286821, 
+    0xfd5ef7ef, 0x01d0f242, 0xf7ef4628, 0x7838fd76, 0xd01d2801, 0x48e32100, 0x312ff201, 0xfd71f017, 
+    0x49e248e1, 0xf0007800, 0xeb000007, 0xf8511000, 0x1c522020, 0x2020f841, 0x0000f899, 0xd1d52800, 
+    0x280a6820, 0x7838dbd2, 0xd1cf2801, 0xe7cb2110, 0x7110f242, 0xb5fee7df, 0xf04f48d1, 0xf9b042c0, 
+    0xf2411002, 0xf7ef0000, 0x4ed1fd8a, 0x78302500, 0xf242b168, 0x06080180, 0xfd3ff7ef, 0x49cb48ca, 
+    0xf0007800, 0xeb000007, 0xf8411000, 0x49c95020, 0x4ccd2001, 0x49c87008, 0x49c87008, 0x49c8700d, 
+    0x49c8700d, 0x49bc7008, 0xf9967008, 0x28050000, 0x2803d043, 0x2000d041, 0xff5af009, 0xb2404621, 
+    0xfae7f7f5, 0xf0092001, 0xf104ff53, 0xb2400120, 0xfadff7f5, 0xf0092002, 0xf104ff4b, 0xb2400140, 
+    0xfad7f7f5, 0xf0092003, 0xf104ff43, 0xb2400160, 0xfacff7f5, 0x88a088e1, 0x0108f3c1, 0x0008f3c0, 
+    0x4101ea40, 0xf3c08860, 0x0fc20008, 0x04020413, 0x4310ea43, 0x43198820, 0xf3c09502, 0x43020008, 
+    0x71d0ea41, 0x2100e9cd, 0x46112201, 0xf7f54610, 0x7830fdbb, 0xb1a84ca5, 0xf8dfe01e, 0x2100c294, 
+    0xeb0c2000, 0xeb041741, 0xf8371241, 0xf8223010, 0x1c403010, 0x2810b200, 0x1c49dbf7, 0x2904b2c9, 
+    0xe7c7d3ee, 0x0000f994, 0xf7f54997, 0x4a99fa92, 0x48952104, 0xfb9af017, 0x0000f994, 0x40fee8bd, 
+    0xba66f009, 0x43f0e92d, 0xf2414885, 0xb0870900, 0x42c0f04f, 0x1002f9b0, 0xf7ef4648, 0xf7f8fcf0, 
+    0xf242ff52, 0x06cf0150, 0xf7ef4638, 0x488afca6, 0xf2422600, 0x78000570, 0xd0132803, 0xf04f4c87, 
+    0x4611020c, 0x28037820, 0x0df8d01a, 0xfa62f7f7, 0x462946a8, 0x4638463d, 0xfc8ff7ef, 0x78384f80, 
+    0xe012b188, 0xf2402300, 0x1e5a2000, 0x210e9600, 0xf7f79601, 0xf7fbf998, 0x4629fddd, 0xe03b4638, 
+    0x0000f640, 0xf7fbe7e2, 0x2001fdd5, 0xe9cd9604, 0x200c0602, 0x23019000, 0x220e9605, 0x03589001, 
+    0xf7f74611, 0x4646fac7, 0x46284641, 0xfc65f7ef, 0xb9c87838, 0x2000f994, 0xd0012a04, 0xd1132a05, 
+    0x7800485b, 0x2100b980, 0xf7f82001, 0x4c65ff1e, 0x200c2100, 0x2000f994, 0xfcc6f7f8, 0xf9942101, 
+    0x46082000, 0xfd06f7f8, 0x220c2301, 0x200e4619, 0xfb6ff7f7, 0x46284631, 0xfc3ff7ef, 0xf44f485a, 
+    0xf7f831b8, 0x2800fb83, 0xf240d010, 0x464c11f4, 0xf7ef4648, 0x4955fc26, 0xf7ef4620, 0xb007fc11, 
+    0x49534620, 0x43f0e8bd, 0xbc0af7ef, 0xe8bdb007, 0x483b83f0, 0x42c0f04f, 0xf9b0b510, 0xf2411002, 
+    0xf7ef0000, 0x4c46fc5c, 0xb9087820, 0xf9cdf004, 0x28017820, 0xf004d101, 0xf7f8f9c8, 0xe8bdffc6, 
+    0xf0044010, 0xe92dba11, 0x4c2d4ff0, 0xf04fb087, 0xf24142c0, 0xf9b40000, 0xf7ef1002, 0x4d38fc40, 
+    0x28017828, 0x483bd110, 0xf44f7801, 0xf7f62080, 0x2000fbe9, 0xf838f7f7, 0x3000f44f, 0x0103f640, 
+    0xfbdff7ef, 0xfb71f7fb, 0x4a00f04f, 0x0980f242, 0x46504649, 0xfbe1f7ef, 0x2701482f, 0xf04f260c, 
+    0x68000800, 0xd2022811, 0x28017828, 0x2301d111, 0x220d9600, 0x8010f8cd, 0x46110258, 0x7802e9cd, 
+    0x8014f8cd, 0xf7f79601, 0x4649fa25, 0xf7ef4650, 0x2100fbc4, 0xf0072001, 0x7828fc37, 0xb3e846ab, 
+    0x0000f994, 0x220d2301, 0x46119004, 0xe9cd9600, 0xe0347002, 0x00040219, 0x00040217, 0x0004022d, 
+    0x00040680, 0xf23c80ba, 0x00040ef4, 0x00041698, 0x00040ed8, 0x000401ff, 0x0004021c, 0x00040214, 
+    0x00040215, 0x00040216, 0x00041258, 0x00040518, 0x00041488, 0x000412d8, 0x00040234, 0x00040242, 
+    0x00040502, 0x00040248, 0x000413e8, 0x77777771, 0xdcba01f5, 0x00040243, 0x000401f0, 0x9601e015, 
+    0x02989005, 0xf9d6f7f7, 0x46504649, 0xfb75f7ef, 0x0000f994, 0x220e2301, 0x46119600, 0x96019004, 
+    0x7002e9cd, 0x03589005, 0xf7fbe050, 0x48fafcc3, 0xf44f7801, 0xf7f63080, 0x2301fb55, 0x220d9600, 
+    0x02984645, 0xe9cd4611, 0xf8cd7802, 0xf8cd8010, 0x96018014, 0xf9aef7f7, 0x46504649, 0xfb4df7ef, 
+    0xf241220e, 0x96000800, 0xe9cd2301, 0x46117502, 0x95044640, 0x95059601, 0xf99cf7f7, 0x46504649, 
+    0xfb3bf7ef, 0xfc96f7fb, 0x780048e4, 0x7820b990, 0x2100b180, 0xf7f82001, 0x4de1fdf8, 0x200c2100, 
+    0x2000f995, 0xfba0f7f8, 0xf9952101, 0x46082000, 0xfbe0f7f8, 0x0000f994, 0x9600220e, 0x46112301, 
+    0x96019004, 0x7002e9cd, 0x46409005, 0xf972f7f7, 0x464946c8, 0x46504655, 0xfb0ff7ef, 0x46082100, 
+    0xfb82f007, 0x46284641, 0xfb07f7ef, 0x0000f89b, 0x020ef04f, 0xf04f46d9, 0x28000301, 0x0000f994, 
+    0x46119600, 0x96019004, 0x7002e9cd, 0xd0309005, 0xf7f70358, 0x4644f94f, 0x46284641, 0xfaedf7ef, 
+    0xf44f48c0, 0xf7f83190, 0xb170fa31, 0x0600f241, 0x11f4f240, 0xf7ef4630, 0x49bbfad4, 0xf7ef4630, 
+    0x49bafabf, 0xf7ef4630, 0x2301fabb, 0x0000f899, 0x4619220c, 0xf7f7200e, 0x2100f9fc, 0x1000f44f, 
+    0xfac0f7f6, 0x4621b007, 0xe8bd4628, 0xf7ef4ff0, 0xf244bac4, 0xe7cc0000, 0x5ff0e92d, 0xf04f4eac, 
+    0xf24142c0, 0xf9b60000, 0xf7ef1002, 0xf04ffaf8, 0xf2424900, 0x46210470, 0xf7ef4648, 0x4fa5faae, 
+    0x080ef04f, 0x28017838, 0xf7f7d179, 0x2300fa21, 0xf44f2211, 0xf04f3100, 0xf0174071, 0x2001faa5, 
+    0xfee2f7f6, 0xf017489c, 0x499cfa93, 0x29106809, 0x499bd801, 0x2100e000, 0xb25cf8df, 0x4c8e46a2, 
+    0xf1ab1a45, 0x46510b0c, 0xf7ef4648, 0x2000fa86, 0xfecaf7f6, 0xff42f009, 0xf500b1a0, 0x78214080, 
+    0xf7f71040, 0x488ffbf2, 0x78232201, 0x1000f9b0, 0xf7f72000, 0x2001fca4, 0xfeb6f7f6, 0xf44f7821, 
+    0xe0052080, 0xf7f62001, 0x7821feaf, 0x3080f44f, 0xfa58f7f6, 0x46582201, 0xf0172102, 0x2801fa73, 
+    0x487dd018, 0x21012200, 0xf0173808, 0x2801fa6b, 0x4879d010, 0xfa4cf017, 0xd8c442a8, 0xf7f62001, 
+    0x7821fe93, 0x2080f44f, 0xfa3cf7f6, 0x28017838, 0xe014d00a, 0x46284d74, 0xfa40f017, 0x0110f040, 
+    0xf0174628, 0xe7e9fa3e, 0xfbf8f009, 0x4870496f, 0xf826f017, 0xd0022801, 0x80702010, 0xf8a6e4a6, 
+    0xe4a38002, 0x47fce92d, 0x4d6b486a, 0x78287801, 0x2832b109, 0x4969d302, 0xb1017809, 0x4e682101, 
+    0x282d4c68, 0xf9947031, 0xd2011000, 0xd0232904, 0xd201284b, 0xd01f2905, 0xf8df2700, 0xf240918c, 
+    0x23003800, 0x22084641, 0xf0174648, 0x7830fa24, 0xd0012801, 0xd05e2f00, 0xf04f484d, 0xf9b042c0, 
+    0xf2411002, 0xf7ef0000, 0x2000fa3a, 0xfe3cf7f6, 0x78004848, 0xe009b110, 0xe7de2701, 0x3000f44f, 
+    0x0103f640, 0xf9ddf7ef, 0xf96ff7fb, 0x28017830, 0xf994d006, 0x28040000, 0x2805d019, 0xe031d023, 
+    0x28037820, 0x2301d12e, 0x22084641, 0xf0174648, 0xf240f9f2, 0xf8ad1000, 0xf8ad0006, 0xf8ad0002, 
+    0xf8ad0004, 0x46680000, 0xf922f7f8, 0x7828e01a, 0xd203280f, 0x2100220d, 0xe0112006, 0x281e380f, 
+    0x220bd210, 0x7828e003, 0xd203280f, 0x2100220d, 0xe0052003, 0x285f380f, 0x220bd204, 0x20022100, 
+    0xfe7af7f9, 0x20012100, 0xfa1ef007, 0xf44f2100, 0xf7f62080, 0xe8bdf997, 0xb53e87fc, 0xf04f4c1c, 
+    0xf24142c0, 0xf9b40000, 0xf7ef1002, 0x4927f9d8, 0x4a272000, 0x21027008, 0x22017011, 0x0000e9cd, 
+    0x90024611, 0xf7f54610, 0x4812fa5f, 0x7800490b, 0x1000f991, 0xd03d4308, 0x70202000, 0x3040f640, 
+    0x48186060, 0x0000f990, 0xd0352804, 0xd1022805, 0x6080f241, 0xbd3e6060, 0x00040243, 0x00040ed8, 
+    0x00040248, 0x000413e8, 0x77777772, 0xdcba01f5, 0x00040680, 0x00040502, 0xf000812c, 0x000401f0, 
+    0x01e84800, 0x00040506, 0xf203517c, 0x0002b868, 0x000413d8, 0x000402ac, 0x00040504, 0x000402ad, 
+    0x000402f5, 0x00040242, 0xf203e800, 0x0004021f, 0x000401fe, 0xe7c02001, 0x5000f642, 0xe92de7ca, 
+    0x4dfe5ff0, 0x1b53f240, 0x46048e81, 0xa3f0f8df, 0x68ab4559, 0x1053f2a1, 0xdc4cd03d, 0x7f93f5b1, 
+    0xdc20d075, 0x1207f240, 0xf2a14291, 0xd0781007, 0xb381dc10, 0xd06b29d8, 0xd06a29d9, 0x7f83f5b1, 
+    0x2200d168, 0xf1054618, 0xf012010c, 0x1d40fee8, 0xe066d072, 0xd0702811, 0xd0622812, 0xd06d2819, 
+    0xd157281a, 0xf240e05d, 0x42911233, 0x1033f2a1, 0xdc11d057, 0x010cf110, 0x2905d053, 0x2906d07e, 
+    0x290bd04f, 0x49ddd146, 0x46182200, 0xf012310c, 0x1d40fec6, 0xe044d073, 0xd0712805, 0xd0402806, 
+    0xd137281f, 0x220049d5, 0x310c4618, 0xfeb7f012, 0xd0661d40, 0x2846e035, 0xdc1cd033, 0xd07d2829, 
+    0x2807dc08, 0x2808d07b, 0x281fd02b, 0x2820d078, 0xe026d120, 0xd024282a, 0xd0722831, 0xd0202832, 
+    0xd1172845, 0x220049c5, 0x310c4618, 0xfe97f012, 0xd0671d40, 0x2869e015, 0xdc0cd07d, 0xd07b2859, 
+    0xd00e285a, 0xd0782861, 0xd1032862, 0xe0ffe009, 0xe01ee015, 0x286ae073, 0x2873d003, 0x2874d06e, 
+    0x49b6d16d, 0x32fff04f, 0x310c68a8, 0xfea6f012, 0xd10a1d01, 0xe25420d8, 0xe0b6e096, 0x49afe0d0, 
+    0x46182200, 0xf012310c, 0x1d41fe99, 0x2801d058, 0x4eaad1e7, 0xf2412700, 0x360c0000, 0x1000f9b6, 
+    0xd04f290f, 0x29144ba7, 0x829cf8df, 0x42c0f04f, 0x090af04f, 0x290ad04c, 0xe003d1d3, 0xe0fce0e0, 
+    0xe128e10b, 0x1002f9b5, 0xd0792913, 0xd06f2901, 0xd06e2902, 0xd06d2910, 0xd06c2911, 0xd06b2912, 
+    0xd06a2903, 0xd069290e, 0xd068290f, 0x29042706, 0x2906d075, 0x2907d074, 0xe004d073, 0xe127e16b, 
+    0xe186e152, 0x2908e1a8, 0x2909d06c, 0x270bd06b, 0xd069290a, 0xd1a4290b, 0xfe38f7fe, 0x200c8037, 
+    0xf04f8068, 0xf8da32ff, 0x46310000, 0xfe17f012, 0xd0741d01, 0xe1dde1f1, 0xe1c4e1a7, 0xe0ece1e7, 
+    0xe1ee20d9, 0x4226f04f, 0xf879f7ef, 0xe788806f, 0x3000f993, 0xd0032b03, 0xd0012b05, 0xd1022b04, 
+    0x781b4b7a, 0x210db123, 0xf7ef806f, 0xe778f868, 0x4220f04f, 0xf863f7ef, 0xfe7ff7ff, 0x0000f898, 
+    0xd00f2803, 0x496d2013, 0x22008068, 0x9000f8a6, 0x68a8310c, 0xfde3f012, 0xf47f1d01, 0xf240aef8, 
+    0xe1be1006, 0xe7ee200e, 0x1007f240, 0xe007e1b9, 0xe040e026, 0xe06ee057, 0xe099e082, 0xe0d1e0ae, 
+    0xfdd0f7ff, 0x2001495d, 0x22008068, 0x310c68a8, 0xfdc5f012, 0xd10e1d01, 0x1018f240, 0xe0ede1a1, 
+    0xe120e103, 0xe15ae13b, 0x4954e177, 0x46182200, 0xf012310c, 0x1d40fdb4, 0xf240d1a9, 0xe1901019, 
+    0xfa92f000, 0x2002494d, 0x22008068, 0x310c68a8, 0xfda5f012, 0xd1091d01, 0x1020f240, 0xe173e181, 
+    0x22004946, 0x310c4618, 0xfd99f012, 0xd18e1d40, 0x1021f240, 0xf7ffe175, 0x4940fcff, 0x68a82200, 
+    0xf012310c, 0x1d01fd8c, 0xf240d108, 0xe1681026, 0x2200493a, 0x310c4618, 0xfd81f012, 0xd1861d40, 
+    0x1027f240, 0xf000e15d, 0x4934fa29, 0x68a82200, 0xf012310c, 0x1d01fd74, 0xf240d108, 0xe150102c, 
+    0x2200492e, 0x310c4618, 0xfd69f012, 0xd1b31d40, 0x102df240, 0xf7eee145, 0xf004ffd2, 0x4927f855, 
+    0x80682012, 0x68a82200, 0xf012310c, 0x1d01fd58, 0xae8ff47f, 0x1032f240, 0xf240e133, 0xe1301033, 
+    0xf9dbf000, 0x2200491d, 0x310c68a8, 0xfd47f012, 0xd1081d01, 0x1038f240, 0x4918e123, 0x46182200, 
+    0xf012310c, 0x1d40fd3c, 0xf240d186, 0xe1181039, 0x28037818, 0xf7ffd101, 0x4910fb56, 0x80682004, 
+    0x68a82200, 0xf012310c, 0x1d01fd2a, 0xae70f47f, 0x1052f240, 0xf8a4e105, 0xe51fb034, 0xfb29f7ff, 
+    0x200f4906, 0x22008068, 0x310c68a8, 0xfd17f012, 0xd1121d01, 0x105af240, 0x0000e0f3, 0x00040680, 
+    0x000406cc, 0x00040242, 0x00040234, 0x000402a4, 0x220049fe, 0xf0124618, 0x1d40fd02, 0xf240d197, 
+    0xe0de105b, 0xfa6ef7ff, 0x0000f898, 0xd0092803, 0x80682003, 0x220049f5, 0xf01268a8, 0x1d01fcf0, 
+    0xe016d00f, 0xf7f52002, 0x48f1feb6, 0xf44f7801, 0xf7f51080, 0x2000ff07, 0xfb56f7f6, 0xfd0ff00b, 
+    0xf240e65f, 0xe0bc1072, 0x220049e8, 0xf0124618, 0x1d40fcd6, 0xf240d1f4, 0xe0b21073, 0xf9abf7ff, 
+    0x2200806f, 0x68a849e1, 0xfcc9f012, 0xd1071d01, 0x107cf240, 0x49dde0a5, 0x46182200, 0xfcbff012, 
+    0xd1dd1d40, 0x107df240, 0xf7fee09b, 0x2002ff73, 0xfe96f7f5, 0x200ab108, 0x200fe000, 0x49d38030, 
+    0x68a82200, 0xfcabf012, 0xd1071d01, 0x1084f240, 0x49cee087, 0x46182200, 0xfca1f012, 0xd1bf1d40, 
+    0x1085f240, 0xf000e07d, 0x48caf8df, 0x28017800, 0x48c9d103, 0x28017800, 0x806fd00b, 0x49c32200, 
+    0xf01268a8, 0x1d01fc8c, 0xadf2f47f, 0x1098f240, 0x2008e067, 0xe7f18068, 0x1099f240, 0xf000e061, 
+    0x48bef871, 0x28017800, 0x2009d009, 0x49b78068, 0x68a82200, 0xfc73f012, 0xd0031d01, 0xf8a5e00a, 
+    0xe7f49002, 0x10acf240, 0x49b0e04b, 0x46182200, 0xfc65f012, 0xd18d1d40, 0x10adf240, 0xf7fee041, 
+    0x2002fda8, 0xfe3cf7f5, 0x200ab108, 0x200fe000, 0x49a68030, 0x68a82200, 0xfc51f012, 0xd1071d01, 
+    0x10b4f240, 0x49a1e02d, 0x46182200, 0xfc47f012, 0xd1861d40, 0x10b5f240, 0xf7fee023, 0x806ffcc7, 
+    0x499a2200, 0xf01268a8, 0x1d01fc3a, 0xf240d107, 0xe01610bc, 0x22004995, 0xf0124618, 0x1d40fc30, 
+    0xf240d18d, 0xe00c10bd, 0x10c6f240, 0x498fe009, 0xf8da2200, 0xf0120000, 0x1d40fc22, 0xf240d1bb, 
+    0x86a010c7, 0x2200e41a, 0xb5102101, 0x50f1f2af, 0xfa60f012, 0x20032108, 0xfbbef012, 0x390c4983, 
+    0xbd106088, 0xb53e4881, 0xf241380c, 0xf04f0400, 0xf9b042c0, 0x46201002, 0xfe71f7ee, 0x46202104, 
+    0xfe1ff7ee, 0x4620497a, 0xf7f57809, 0x2000fe1b, 0xf818f00b, 0xf990487a, 0x28050000, 0x2803d004, 
+    0x2003d002, 0xf850f00b, 0x0180f242, 0xf7ee0608, 0x4874fe14, 0x49742400, 0x70044d74, 0x70082001, 
+    0x2002e00e, 0xfdbcf7f5, 0xd0092801, 0x46284d70, 0xfe04f016, 0x0140f040, 0xf0164628, 0xe006fe02, 
+    0x46282200, 0xf0162101, 0x2800fe0d, 0x2100d1e9, 0x22019402, 0xe9cd4610, 0x46111100, 0xfec4f7f4, 
+    0x403ee8bd, 0xbbbef008, 0xb5fe4862, 0x4a637800, 0x4e5e1e40, 0x0103f000, 0xeb02485f, 0x78001241, 
+    0x07801e40, 0xeb020f00, 0xf8320140, 0x888b0010, 0xf3c088cc, 0x88490008, 0x0308f3c3, 0x0408f3c4, 
+    0x0108f3c1, 0x4404ea43, 0x041b0fcb, 0x4311ea43, 0x040d431c, 0xea444305, 0xe00e74d0, 0xf7f52002, 
+    0x2801fd6f, 0x4e4ad009, 0xf0164630, 0xf040fdb7, 0x46300120, 0xfdb5f016, 0x2200e006, 0x21014630, 
+    0xfdc0f016, 0xd1e92800, 0x95002001, 0x46014602, 0x4001e9cd, 0xfe78f7f4, 0xb510bdfe, 0xf04f4c33, 
+    0xf24142c0, 0x3c0c0000, 0x1002f9b4, 0xfdd7f7ee, 0xfaadf009, 0x200eb110, 0xbd108060, 0x80602010, 
+    0x49384837, 0x700a7802, 0x704a7842, 0x708a7882, 0x70c878c0, 0x4010e8bd, 0xba17f009, 0x41f0e92d, 
+    0xf04f4c22, 0xf24142c0, 0x3c0c0000, 0x1002f9b4, 0xfdb5f7ee, 0xf942f7fc, 0xf7f62000, 0x482af9b5, 
+    0x0000f990, 0xd0031c40, 0x80602011, 0x81f0e8bd, 0xf2404d26, 0x4f262600, 0x0000f995, 0x17c11c40, 
+    0x7191eb00, 0x0103f021, 0x70281a40, 0x78282400, 0x4631b108, 0x4639e000, 0xf7fa4620, 0x1c64fef2, 
+    0x2c04b264, 0xe7e1dbf3, 0xf04f4808, 0xb57042c0, 0xf9b0380c, 0xf2411002, 0xf7ee0000, 0xf242fd80, 
+    0x06cd0170, 0xf7ee4628, 0xe023fd38, 0x0004068c, 0x00040243, 0x0004022c, 0x0004022d, 0x00040502, 
+    0x00040ed8, 0x0004021c, 0x0004021e, 0xf000801c, 0xf203517c, 0x00040216, 0x00040217, 0x00041258, 
+    0x00040520, 0x00040518, 0x0004022e, 0x00040508, 0xfffffa00, 0x0be82100, 0xfd04f7f5, 0x78214c12, 
+    0xd1032901, 0x0ae82100, 0xfcfcf7f5, 0x0180f242, 0xf7ee4628, 0x480dfd02, 0x7802490e, 0x2a01480c, 
+    0x4a0dd103, 0x2a037812, 0x221ed009, 0xfa95f7fc, 0x28007820, 0xe8bdd106, 0xf7fa4070, 0x4807be4b, 
+    0xe7f3221e, 0x0000bd70, 0x00040502, 0x000402f5, 0x43e187ae, 0x450f6429, 0x00040242, 0x4361c7ae, 
+    0x48ffb5fe, 0x0400f242, 0x42e0f04f, 0x1006f9b0, 0xf7ee4620, 0x2107fd14, 0xf7ee4620, 0x04a6fcc2, 
+    0x05a0f242, 0x46304629, 0xfcc7f7ee, 0x220048f5, 0x92007002, 0x2201e9cd, 0x46112201, 0xf7f44610, 
+    0x4629fd93, 0xf7ee4630, 0x4ceffcb8, 0x2000f994, 0x2a02b122, 0x2a03d008, 0xe010d006, 0xf7f62000, 
+    0x2301f8f3, 0xe006220c, 0xf7f62000, 0x48e7f8ed, 0x220d2301, 0x21017800, 0xf7f6200e, 0x4629fbca, 
+    0xf7ee4630, 0x7820fc9a, 0x48e1b930, 0x220e2300, 0x0100f244, 0xfcaff016, 0x200149de, 0xbdfe7008, 
+    0x4ffee92d, 0xf2424ed8, 0x78300a00, 0xd1132803, 0x11f4f240, 0x46504654, 0xfc73f7ee, 0x3199f243, 
+    0xf7ee4620, 0x49d4fc5d, 0xf7ee4620, 0x48d4fc59, 0x680049d2, 0xfc6cf7f5, 0x200149ca, 0x70082700, 
+    0x700748d0, 0x0000f996, 0x2140b138, 0x80114ace, 0x780949ce, 0xd0032904, 0xf240e005, 0xe7f52100, 
+    0x2020b108, 0x48ca8010, 0x28027800, 0x01c0d101, 0x21008010, 0x22019702, 0xe9cd4610, 0x46111100, 
+    0xfd22f7f4, 0xf7f62002, 0xf04ffd6d, 0xf2424800, 0x46210490, 0xf7ee4640, 0xf7f5fc40, 0x4db0f9a1, 
+    0x80a849bc, 0xb1097809, 0xfd61f006, 0xfb6ef7f5, 0x28037830, 0x201ed10c, 0xfcebf7f4, 0xf00a2003, 
+    0x48abfcab, 0x220e2300, 0x0100f244, 0xfc43f016, 0xf7f42005, 0x46a1fcde, 0x46404621, 0xfc1df7ee, 
+    0xf0082001, 0x49acfa9c, 0x4cac2301, 0xf8df461a, 0x7a48b2b0, 0xf0017a09, 0xea400103, 0x80202001, 
+    0x46582102, 0xfc27f016, 0x46582300, 0x21022201, 0xfc21f016, 0x46582301, 0x46192200, 0xfc1bf016, 
+    0x2001e005, 0xfa7bf008, 0x1e408820, 0x88208020, 0xd8f62801, 0x7800489b, 0xd0072801, 0xd0052802, 
+    0xf00a2005, 0x7830fc6b, 0xe00bb120, 0xf00a2006, 0xe7f8fc63, 0xb1287828, 0x1e912201, 0xf7f52005, 
+    0x702ffb9f, 0x4649464c, 0x46404646, 0xfbd5f7ee, 0x2301488b, 0x21102204, 0xf01630aa, 0x4888fbec, 
+    0x220f2301, 0x30d403d9, 0xfbe5f016, 0x1004f9b5, 0xf7f52000, 0xf9b5f9ee, 0xf04f1006, 0x465042e0, 
+    0xfbfdf7ee, 0x4621b003, 0xe8bd4630, 0xf7ee4ff0, 0xe92dbbb4, 0x4e6c4ffe, 0x0800f242, 0x28037830, 
+    0xf240d113, 0x464411f4, 0xf7ee4640, 0xf241fb9a, 0x46201199, 0xfb84f7ee, 0x46204967, 0xfb80f7ee, 
+    0x49664867, 0xf7f56800, 0x2001fb93, 0xfa17f008, 0x4869496d, 0xf984f016, 0xd0292801, 0x21e24c6b, 
+    0x68204645, 0x60201c40, 0xf7ee4640, 0x6821fb7a, 0xf7ee4628, 0xf242fb65, 0x462801d0, 0xfb7df7ee, 
+    0x78004852, 0xd07c2801, 0x48612100, 0x3132f201, 0xfb77f016, 0x7800485f, 0x0007f000, 0x1100eb00, 
+    0xeb00485d, 0x68410081, 0x60411c49, 0x8ffee8bd, 0x495a4d51, 0xf01079e8, 0x70080001, 0xf996d0f6, 
+    0xb1291000, 0x4a492020, 0x2a047812, 0xe003d002, 0xe7f82040, 0x2010b101, 0x78094945, 0xd1002902, 
+    0x7a2a2040, 0x7a694c45, 0x0203f002, 0x2102ea41, 0x80214281, 0x2002ddda, 0xfaecf7f5, 0x48484601, 
+    0x9124f8df, 0x1a436800, 0xf9b14946, 0xfbb32000, 0x1cc9f1f2, 0x1000f8c9, 0x43511e89, 0xfb28f7f5, 
+    0x20014928, 0xf04f4a30, 0x46570a00, 0x482d7008, 0xa000f880, 0xf8b98821, 0x1a090000, 0xb2818011, 
+    0xf016483a, 0x2100fb1e, 0x22019702, 0xe9cd4610, 0x46111100, 0xfbe8f7f4, 0xf7f62002, 0xf04ffc33, 
+    0xf2424900, 0x46590b90, 0xf7ee4648, 0xf7f5fb06, 0x4f13f867, 0x8078491f, 0xb1097809, 0xfc27f006, 
+    0xe0b8e000, 0xfa32f7f5, 0x28037830, 0x201ed10c, 0xfbaff7f4, 0xf00a2003, 0x480dfb6f, 0x220e2300, 
+    0x0100f244, 0xfb07f016, 0xf7f42005, 0x4659fba2, 0xf7ee4648, 0x2001fae2, 0xf961f008, 0xe0377a68, 
+    0x00040694, 0x00040223, 0x00040ed8, 0x00040502, 0xf2030416, 0x00040201, 0xdcba01f5, 0x0066ff30, 
+    0x00040558, 0x00040221, 0x00040226, 0x00040242, 0x00040556, 0x0004027b, 0x000413d8, 0x00040228, 
+    0xf203504c, 0x0004057b, 0x0002b868, 0x000402a0, 0xf23c80ba, 0x00040ef4, 0x00041698, 0x00040224, 
+    0x00040230, 0x00040588, 0x00040514, 0xf203519a, 0x23017a29, 0xf001461a, 0xea400103, 0x80202001, 
+    0x4dfd2102, 0xf0164628, 0x2300fab6, 0x22014628, 0xf0162102, 0x2301fab0, 0x22004628, 0xf0164619, 
+    0xe005faaa, 0xf0082001, 0x8820f90a, 0x80201e40, 0x28018820, 0x48f1d8f6, 0x28017800, 0x2802d007, 
+    0x2005d005, 0xfafaf00a, 0xb1207830, 0x2006e00c, 0xfaf2f00a, 0x7838e7f8, 0x2201b130, 0x20051e91, 
+    0xfa2ef7f5, 0xa000f887, 0x4659465c, 0x4648464d, 0xfa63f7ee, 0x230148e0, 0x21102204, 0xf01630aa, 
+    0x48ddfa7a, 0x220f2301, 0x30d403d9, 0xfa73f016, 0x1002f9b7, 0xf7f52001, 0xf9b7f87c, 0xf04f1006, 
+    0x464042e0, 0xfa8bf7ee, 0x46284621, 0xfa45f7ee, 0x80f82006, 0xf242e6da, 0xe6c67110, 0x2001b570, 
+    0xf8bdf008, 0x48cf49ce, 0xf82af016, 0x28014ece, 0x0500f242, 0x4ccdd026, 0x682021e2, 0x60201c40, 
+    0xf7ee4628, 0x6821fa1e, 0xf7ee4628, 0xf242fa09, 0x462801d0, 0xfa21f7ee, 0x28017830, 0x2100d032, 
+    0xf20148c3, 0xf0163131, 0x48c2fa1c, 0xf0007800, 0xeb000007, 0x48c01100, 0x0081eb00, 0x1c496841, 
+    0xbd706041, 0x79c048b7, 0x1140f3c0, 0x700148bb, 0x780048bb, 0xd1f42801, 0xd0f22900, 0xf04f4cb9, 
+    0x462842e0, 0x1006f9b4, 0xfa39f7ee, 0x46282106, 0xf9e7f7ee, 0x28017830, 0x2004d002, 0xbd7080e0, 
+    0xe7fb2005, 0x7110f242, 0xe92de7ca, 0x4fad4ff0, 0xf04fb087, 0xf24242e0, 0xf9b70000, 0xf7ee1006, 
+    0x4ca9fa1e, 0x0b01f04f, 0x4ea84d9f, 0xb1c87820, 0x210048a0, 0x78004aa0, 0x0007f000, 0x1000eb00, 
+    0x0080eb02, 0x78286041, 0xf7fab908, 0x7820fb23, 0xd02b2802, 0xb9987828, 0xf44f7831, 0xf7f53080, 
+    0xe00df9b1, 0xb9687828, 0xfb14f7fa, 0xf44f7831, 0xf7f52000, 0xf242f9a7, 0x06080180, 0xf9adf7ee, 
+    0xb9987820, 0x0001f997, 0x90042301, 0x9005220e, 0xe9cd4611, 0x200cb002, 0x90019000, 0xf7f50398, 
+    0xf242fff9, 0x06c80190, 0xf997f7ee, 0x46a07828, 0x1000f994, 0xd17c4308, 0x25004885, 0xf8c3f7f7, 
+    0xa1d8f8df, 0xf89a4a82, 0x28030000, 0x4982d109, 0xf9914880, 0xf8423002, 0xf9910023, 0xf8421003, 
+    0x68110021, 0xf8522401, 0x42880024, 0x4601d201, 0x1c644625, 0x2c04b264, 0xf44fdbf5, 0xf6403000, 
+    0xf7ee0103, 0xf7faf95e, 0x4c74f8f0, 0x46082100, 0x2000f994, 0xfa1ef7f7, 0xf9f6f7fa, 0x46072203, 
+    0x2138486f, 0xf0167025, 0xf8dff984, 0xb15891b8, 0x0000f899, 0xd5070740, 0x0000f89a, 0xd0032803, 
+    0x78004869, 0xe0007020, 0xb2397025, 0xf7fa1438, 0x4966f946, 0xf8812002, 0xf7fab000, 0xf994fb55, 
+    0xf7fa0000, 0xf994f89d, 0xf7fa0000, 0xf994f8e2, 0xf7fa0000, 0x485af92d, 0x21382203, 0xf959f016, 
+    0xf899b128, 0x07400000, 0xf7fad501, 0xf7fafbd7, 0x7831fa81, 0x0000f242, 0xf914f7f5, 0x20012100, 
+    0xfbe3f7f7, 0x2000f994, 0x200c2100, 0xf98cf7f7, 0xe005e000, 0xf9942101, 0x46082000, 0xf9caf7f7, 
+    0x0000f898, 0x28034644, 0x2301d00c, 0x4619220c, 0xf7f6200e, 0x7820f82e, 0x2100b920, 0x0000f44f, 
+    0xf8f0f7f5, 0xf242b007, 0x06c80190, 0x4ff0e8bd, 0xb8f3f7ee, 0x4ffee92d, 0x46044d32, 0xf2408e80, 
+    0x28fe1b0f, 0xd07368ab, 0x28dddc1b, 0xdc0fd039, 0x28b0b370, 0x28b1d070, 0x28dcd077, 0x2200d16b, 
+    0xf1054618, 0xf011010c, 0x1d40feaa, 0xe028d07e, 0xd07c28ee, 0xd02428ef, 0xd07928f6, 0xd15a28f7, 
+    0x4558e01f, 0x110ff2a0, 0xdc12d01b, 0xd01828ff, 0x7f83f5b0, 0xf111d06d, 0xd0120008, 0xd14a2807, 
+    0x22004918, 0x310c4618, 0xfe89f011, 0xd07d1d40, 0x2907e007, 0x2908d07b, 0x2911d003, 0x2912d078, 
+    0x4910d139, 0x32fff04f, 0x310c68a8, 0xfea6f011, 0xd1361d01, 0xe17c20b0, 0xf203504c, 0x0004057b, 
+    0x0002b868, 0x000413d8, 0x00040502, 0x000402a0, 0xf23c80ba, 0x00040ef4, 0x00041698, 0x00040202, 
+    0x00040201, 0x00040694, 0x00040ed8, 0x00040243, 0x000413e8, 0x00029395, 0x00040520, 0x00040248, 
+    0xf38f007c, 0x00040279, 0x0004061d, 0x00040246, 0xe001e0eb, 0xe126e009, 0x220049c7, 0xf0114618, 
+    0x1d41fe6d, 0x2801d03d, 0x4fc3d1bb, 0xf2422600, 0xf9b70000, 0x290f1000, 0xf04fd035, 0xf04f42e0, 
+    0xf04f0802, 0xf04f0901, 0xe0030a03, 0xe093e085, 0xe0e7e0a9, 0xd02c2915, 0xd1a2290a, 0x1006f9b5, 
+    0xd07c2901, 0xd0732909, 0xd0722902, 0xd0712903, 0xd0702904, 0xd06f2905, 0xd1922906, 0xfb60f7ff, 
+    0x8038200b, 0x80e82007, 0xe0021e72, 0xe0f9e0e9, 0x48aae105, 0x68004639, 0xfe01f011, 0xd0741d01, 
+    0x20b1e103, 0xf04fe105, 0xf7ee4227, 0x80eef868, 0x4ba3e777, 0x3000f993, 0xd0032b03, 0xd0012b05, 
+    0xd1022b04, 0x781b4b9f, 0x2108b123, 0xf7ee80ee, 0xe766f856, 0x4220f04f, 0xf7ee4607, 0x2105f850, 
+    0xf7ed4638, 0x2101fffe, 0xf7f62000, 0x2004f8f5, 0xf882f00a, 0x49954894, 0xf9917800, 0x43081000, 
+    0x2000d014, 0x70684992, 0x46102201, 0xa000f881, 0x96022100, 0x1100e9cd, 0xf7f44611, 0x488df8c5, 
+    0x9006f8a5, 0x28027800, 0xe003d002, 0xe7e92001, 0x8006f8a5, 0x4880210a, 0x80012200, 0x68a84601, 
+    0xfdadf011, 0xf47f1d01, 0x20dcaf00, 0xe006e0b1, 0xe031e01c, 0xe06fe052, 0x20dde086, 0xf7ffe0a9, 
+    0x2009fde4, 0x497480e8, 0x68a82200, 0xfd97f011, 0xd1061d01, 0xe09c20ee, 0x2200496f, 0xf0114618, 
+    0x1d40fd8e, 0x20efd194, 0xe085e093, 0xf8a2f000, 0x8006f8a5, 0x49682200, 0xf01168a8, 0x1d01fd80, 
+    0x20f6d106, 0x4964e085, 0x46182200, 0xfd77f011, 0xd18e1d40, 0xe07c20f7, 0xffe1f7ed, 0x20004966, 
+    0xf8812201, 0x46019000, 0x0043e88d, 0x46104611, 0xf86af7f4, 0xa006f8a5, 0x49572200, 0xf01168a8, 
+    0x1d01fd5e, 0x20fed106, 0x4953e063, 0x46182200, 0xfd55f011, 0xd1c51d40, 0xe05a20ff, 0xfd3ef7ff, 
+    0xf7f42002, 0xb108ff2d, 0xe000200a, 0x8038200f, 0x22004949, 0xf01168a8, 0x1d01fd42, 0xf240d107, 
+    0xe0461006, 0x22004944, 0xf0114618, 0x1d40fd38, 0xf240d1a8, 0xe03c1007, 0xfbabf7ff, 0xf7f42002, 
+    0xb108ff0f, 0xe000200a, 0x8038200f, 0x2200493a, 0xf01168a8, 0x1d01fd24, 0xae98f47f, 0x100ef240, 
+    0xf8a4e027, 0xe505b034, 0xfabaf7ff, 0x80e82006, 0x22004931, 0xf01168a8, 0x1d01fd12, 0xf240d107, 
+    0xe0161016, 0x2200492c, 0xf0114618, 0x1d40fd08, 0xf240d18f, 0xe00c1017, 0x1020f240, 0x4827e009, 
+    0x49252200, 0xf0116800, 0x1d40fcfa, 0xf240d1a3, 0x86a01021, 0x2200e4de, 0xb5102101, 0x30abf2af, 
+    0xfb38f011, 0x20022108, 0xfc96f011, 0x390c491a, 0xbd106088, 0xb5104821, 0xb3307800, 0x7800481b, 
+    0x481fbb18, 0x28037800, 0x4815d01f, 0x28037800, 0x481cd102, 0xb1c07800, 0xf04f480f, 0x380c42e0, 
+    0x1006f9b0, 0x0000f242, 0xff39f7ed, 0xf7f52000, 0xf7f7fb3b, 0xf7f7ff81, 0x2001fc10, 0xfb34f7f5, 
+    0xf44f2100, 0xf7f41000, 0xf242fedd, 0xe8bd0190, 0x06c84010, 0xbee1f7ed, 0x000406a0, 0x000406cc, 
+    0x00040242, 0x000402a4, 0x00040502, 0x00040ed8, 0x000401fe, 0x00040556, 0x00040201, 0x000402af, 
+    0x0004057b, 0x000402f5, 0x41f0e92d, 0x0800f244, 0x4640210a, 0xfeb5f7ed, 0x23074cfc, 0xf24f220c, 
+    0x46200100, 0xfec0f015, 0xf6402307, 0x22087100, 0xf0154620, 0x48f6feb9, 0x78014ef7, 0x290148f5, 
+    0x7831d102, 0xd00a2905, 0xf0152104, 0x48f3feaa, 0x78002400, 0x48f2b3a0, 0xb1107800, 0x2108e012, 
+    0x2100e7f3, 0xf7f72001, 0x4deef960, 0x200c2100, 0x2000f995, 0xff08f7f6, 0xf9952101, 0x46082000, 
+    0xff48f7f6, 0x78284de8, 0xd1002801, 0xf2402401, 0xf04f11f4, 0x46387780, 0xfe73f7ed, 0x2122f249, 
+    0xf7ed4638, 0xf995fe5d, 0x46381000, 0xfe58f7ed, 0x46384621, 0xfe54f7ed, 0x463849dc, 0xfe50f7ed, 
+    0x200d7831, 0xd1032905, 0x780949d9, 0x200fb901, 0x23011902, 0x000ef104, 0xf7f54619, 0xf242fd8a, 
+    0x06c801b0, 0xfe59f7ed, 0xe8bd4640, 0x210b41f0, 0xbe47f7ed, 0x5ff0e92d, 0x46044dce, 0xf5b08e80, 
+    0x686b7fb6, 0xdc12d07d, 0xd07b28ec, 0xb318dc05, 0xd02c288c, 0xd176288d, 0x28ede033, 0xf5b0d01c, 
+    0xd0717f98, 0x7080f5a0, 0xd16c3831, 0xf5b0e014, 0xd06a7fbd, 0xf5a0dc08, 0x386d7080, 0x2805d00c, 
+    0x2806d07e, 0xe007d15f, 0x7080f5a0, 0xd003387b, 0xd076280d, 0xd156280e, 0xf04f49b6, 0x686832ff, 
+    0xf0113108, 0x1d01fc1b, 0x208cd107, 0x49b1e232, 0x46182200, 0xf0113108, 0x1d41fc11, 0x2801d027, 
+    0x4eacd1ea, 0xf2442700, 0x36080900, 0x1000f9b6, 0xd01e290f, 0xf2422916, 0xf04f0bb0, 0xd01f4800, 
+    0x1000f9b5, 0xd07d2901, 0xd1d52902, 0x46420388, 0xfe35f7ed, 0xff28f7ff, 0x8030200b, 0x1e7a489e, 
+    0x68004631, 0xfbbbf011, 0xd06c1d01, 0x208de1fe, 0xf04fe200, 0x46484228, 0xfe21f7ed, 0xe7bb802f, 
+    0xa234f8df, 0x0000f99a, 0xd00f2803, 0xd00d2805, 0xd00b2804, 0x46422103, 0x802f4648, 0xfe0ff7ed, 
+    0xe195e7aa, 0xe1e6e05b, 0xe1cce0f4, 0x4220f04f, 0x4648464e, 0xfe03f7ed, 0x46302109, 0xfdb1f7ed, 
+    0x46404659, 0xfdb9f7ed, 0x78304e84, 0xd0172801, 0xd0152802, 0xf0092005, 0x4881fe2f, 0xe0017800, 
+    0xe1bde195, 0xd00d2801, 0x200a802f, 0x22004979, 0x80083108, 0xf0116868, 0x1d01fb72, 0xe034d02d, 
+    0xe7e82006, 0x48772301, 0x0299220a, 0xfdb3f015, 0xf7f52000, 0x4874f9d9, 0x28116800, 0x2100d803, 
+    0xf7f44648, 0xf89afd7f, 0x20081000, 0x29042300, 0x7831d10c, 0xd1092901, 0x2010496c, 0x29027809, 
+    0xe001d104, 0xe188e015, 0x23012004, 0x21017832, 0xfc50f7f9, 0x80282001, 0x20ece7c7, 0x495de18a, 
+    0x46182200, 0xf0113108, 0x1d40fb3a, 0x20edd187, 0xf242e180, 0x06c801b0, 0xfd5ff7ed, 0x4f5c46b8, 
+    0xf887485c, 0x78018000, 0x0000f242, 0xfd4af7f4, 0x22054854, 0x300a2120, 0xfd7bf015, 0xb158f8df, 
+    0x2801b2c0, 0xd0497038, 0x2205484e, 0x300a2120, 0xfd6ff015, 0xa124f8df, 0x7038b2c0, 0x1000f89a, 
+    0xd1162903, 0xd0392801, 0xf6414846, 0x220071ff, 0x30ba460b, 0xfd4ff015, 0x78014846, 0x0000f248, 
+    0xfd20f7f4, 0x2205483f, 0x300a2120, 0xfd51f015, 0xb2c07038, 0xd0212801, 0x46482198, 0xfd11f7ed, 
+    0x6800483e, 0x2000b188, 0xf95ef7f5, 0x01b0f242, 0xf7ed06c8, 0x482afd12, 0x3190f240, 0x8000f8a5, 
+    0x78024b37, 0xf7f41e48, 0x4836fd2f, 0xfc3bf7f6, 0x1000f89a, 0x29034833, 0xe07dd06d, 0x4200f04f, 
+    0x1000f9b5, 0xf7ed0c10, 0x482ffd3a, 0xfcf0f015, 0x20024607, 0xfc9ef7f4, 0xf89b1a39, 0xf0000000, 
+    0xeb000007, 0x48291200, 0x0082eb00, 0x62812200, 0x80282002, 0x68014826, 0x60011c49, 0x200a4915, 
+    0x68688030, 0xf0113108, 0x1d01faaa, 0xf240d108, 0xe0ef1030, 0x2200490f, 0x31084618, 0xfa9ff011, 
+    0xf47f1d40, 0xf240ae93, 0xe0e31031, 0xf100004c, 0x000402b2, 0xf2031034, 0x00040242, 0x00040ed8, 
+    0x00040502, 0x00040248, 0x00040f1c, 0xdcba01f5, 0x0004027b, 0x000406a8, 0x000406cc, 0x0004057b, 
+    0x00040201, 0xf2035022, 0x000401f0, 0x00040322, 0x0004022b, 0x00040243, 0x00040ef4, 0x00057f70, 
+    0xf23c80ba, 0x000413e8, 0xf0008128, 0x00041698, 0x00057f84, 0x4960e7ff, 0x2000f991, 0x3002f991, 
+    0x2022f850, 0x2023f840, 0x2001f991, 0x1003f991, 0x2022f850, 0x2021f840, 0x3200e9d0, 0x1002e9d0, 
+    0xeb01189f, 0x44670c00, 0x5ce8f64f, 0x0f97ebbc, 0x4293d917, 0x461fd901, 0x4617e000, 0xd9014281, 
+    0xe000468c, 0x45674684, 0x4293d905, 0x4618d901, 0x4610e004, 0x4281e002, 0x4608d900, 0x42884947, 
+    0x4847d94f, 0xb3787800, 0xf9b14946, 0x28140000, 0x1c40da2b, 0xf89b8008, 0x22000000, 0xf0001c40, 
+    0xeb000007, 0x48401100, 0x0081eb00, 0xf5016881, 0x60816180, 0x8000f8a5, 0x8030203f, 0x493b483c, 
+    0xf0116800, 0x1d01fa0c, 0xf240d108, 0xe051106c, 0x22004837, 0x68004935, 0xfa01f011, 0xf47f1d40, 
+    0xf240adf5, 0xe045106d, 0x2002e7ff, 0xfbd8f7f4, 0x200ab108, 0x200fe000, 0x492c8030, 0x68682200, 
+    0xf9edf011, 0xd1071d01, 0x1072f240, 0x4927e032, 0x46182200, 0xf9e3f011, 0xd1e01d40, 0x1073f240, 
+    0x2002e028, 0xfbbcf7f4, 0x200ab108, 0x200fe000, 0x491e8030, 0x68682200, 0xf9d1f011, 0xd1071d01, 
+    0x107af240, 0x4919e016, 0x46182200, 0xf9c7f011, 0xd1c41d40, 0x107bf240, 0xf240e00c, 0xe0091088, 
+    0x22004814, 0x68004911, 0xf9b9f011, 0xd1b61d40, 0x1089f240, 0xe8bd86a0, 0x22009ff0, 0xb5102101, 
+    0x40eff2af, 0xfff6f010, 0x20032108, 0xf954f011, 0x39084906, 0xbd106048, 0x00040520, 0x00013880, 
+    0x00040ed8, 0x00040ede, 0x00041698, 0x000406b0, 0x00040f10, 0x000406cc, 0x5ffce92d, 0xf2482700, 
+    0x210c0000, 0xfbadf7ed, 0x220248fc, 0xf0152104, 0xb110fbe0, 0xf7f52000, 0x4cf9fe26, 0xf7f67820, 
+    0x7820f921, 0xffa3f006, 0xf8dcf007, 0x83d4f8df, 0x0a04f640, 0x0000f898, 0xf8dfbbe8, 0xf04fb3cc, 
+    0x464c0900, 0x0000f89b, 0x0007f000, 0x1200eb00, 0xeb0048ee, 0xf8c00082, 0x2301902c, 0x220048ec, 
+    0xeb004621, 0x48eb2644, 0x2544eb00, 0xe9cd4618, 0xf7f35600, 0x48e8f873, 0x68022100, 0x0074f8b2, 
+    0x3076f8b2, 0xf835e00a, 0xfb122010, 0xf836fc02, 0x1c402010, 0xfb12b280, 0x4411c202, 0xd2f24283, 
+    0xf84048de, 0x48de1024, 0x1024f840, 0x49de48dd, 0x2044eb00, 0xe010e000, 0x2144eb01, 0xe9cd2200, 
+    0x23011000, 0x46104621, 0xf848f7f3, 0xb2641c64, 0xdbc22c04, 0x0000f898, 0x4ed4b398, 0xf0154630, 
+    0xea00fb4d, 0x4630040a, 0xfb48f015, 0x0580f000, 0xf0154630, 0xf400fb43, 0x20045680, 0xfce1f004, 
+    0x0000f898, 0xb39046c1, 0x20012100, 0xfbacf005, 0xf0052000, 0xf8dff8b2, 0x49c6a318, 0x0000f89a, 
+    0x4ac5b150, 0x0580f025, 0x06927812, 0xf424d401, 0x4fc26400, 0xd8232801, 0x78124ac1, 0xd01d2a01, 
+    0xe7ffe02b, 0x9000f8cb, 0xf8df4649, 0x258092f8, 0x465448bd, 0xf8c9016e, 0xf0151000, 0xf8b9fb12, 
+    0xb2810000, 0x301448b8, 0xfb0bf015, 0xe7ffe7c5, 0x46082101, 0xfb78f005, 0xe7ca2001, 0xd9012801, 
+    0xe0002002, 0x70082003, 0x220049b0, 0xf7f42004, 0x200bfab7, 0xfbb1f7f4, 0xf8df2600, 0xf89882b4, 
+    0xb9200000, 0x0000f89a, 0x2001b108, 0x2000e000, 0xfdf8f7f9, 0x0000f898, 0x48a6b920, 0xb1087800, 
+    0xe0002008, 0x432c2000, 0x433c4304, 0xb2a04334, 0x61e0f440, 0xf0154895, 0x489ffad4, 0xf0152100, 
+    0xf899fad0, 0xb9480000, 0x2001499c, 0x499c7008, 0x499c7008, 0x20007008, 0x7008499b, 0xf7f92001, 
+    0x489afc96, 0x0000f990, 0xfa63f7f9, 0x0000f898, 0xd0112801, 0x48962100, 0xeb008800, 0xebc20240, 
+    0xe8bd10c0, 0xeb015ffc, 0xf2a000c0, 0xb28110e5, 0x1c80487e, 0xbaa5f015, 0x7110f242, 0xe92de7eb, 
+    0x4e8c5ffc, 0x498c4604, 0x0a00f04f, 0x68738e80, 0x7f8ff5b0, 0xd075680d, 0x28e2dc12, 0xdc05d073, 
+    0x28b6b318, 0x28b7d02c, 0xe033d16e, 0xd01c28e3, 0x7f89f5b0, 0xf5a0d069, 0x38137080, 0xe014d164, 
+    0x7fd7f5b0, 0xdc08d072, 0x7080f5a0, 0xd00c381f, 0xd06c2869, 0xd157286a, 0xf5a0e1d4, 0x38af7080, 
+    0x2821d003, 0x2822d078, 0x4972d14e, 0x32fff04f, 0x31086870, 0xf862f011, 0xd1071d01, 0xe21a20b6, 
+    0x2200496c, 0x31084618, 0xf858f011, 0xd01f1d41, 0xd1ea2801, 0x27004d67, 0xf9b53508, 0x290f1000, 
+    0x2917d018, 0x4210f04f, 0xf9b6d030, 0xf2481000, 0xf7ed0000, 0xf9b6fa84, 0xf8df0000, 0x2801b108, 
+    0x2802d055, 0x4852d1d1, 0x28017800, 0xe1dad075, 0xe1f020b7, 0x4229f04f, 0x0000f248, 0xfa6ff7ed, 
+    0x4a534956, 0x68088037, 0x42906812, 0x1c40da01, 0x88086008, 0x4844b281, 0xf0151c80, 0x4850fa22, 
+    0xe7b27007, 0xe028e108, 0xe0d2e1d6, 0xf990482c, 0x28030000, 0x2805d00c, 0x2804d00a, 0x2103d008, 
+    0x0000f248, 0xf7ed8037, 0xe79efa4a, 0xe161e194, 0x4220f04f, 0x0000f248, 0xfa41f7ed, 0x2001493d, 
+    0x200a8030, 0x22008028, 0x31086870, 0xffc7f010, 0xd1081d01, 0xe1ae20e2, 0x4936e1a4, 0x46182200, 
+    0xf0103108, 0x1d40ffbc, 0x20e3d1cb, 0xf8dfe1a3, 0x230180d4, 0x461a2102, 0xf0154640, 0x2300f9fc, 
+    0x22014640, 0xf0152102, 0x2002f9f6, 0xfab7f7f4, 0x90b4f8df, 0x482db120, 0x28017800, 0xe0fbd07e, 
+    0x0000f99b, 0x8020f8df, 0xb020f8df, 0xd04f2805, 0xd0522802, 0xd0502803, 0xe157e086, 0xf3074084, 
+    0x00040242, 0x00040ed8, 0x00040ef4, 0x00041698, 0x00044108, 0x00043908, 0x00040598, 0x00041238, 
+    0x00041248, 0x00045108, 0x00044908, 0xf23c80b8, 0x0004027b, 0x00040574, 0x00040279, 0xffff8000, 
+    0x00040287, 0x00040f20, 0xf203513e, 0x0ee6b280, 0x00040502, 0x00040f1c, 0xf203086e, 0x00040246, 
+    0x00040247, 0x00040260, 0x00040261, 0x00040248, 0x00057f78, 0x000406b8, 0x00040f10, 0x00057f80, 
+    0x00040d84, 0xf23c8314, 0x00040ede, 0x000404ee, 0x0000f9b9, 0xdb042814, 0xf9b9e036, 0x28040000, 
+    0x489eda32, 0xf2427801, 0xf7f40000, 0xf8b9f95b, 0x1c491000, 0x1000f8a9, 0x0000f898, 0xf0001c40, 
+    0xeb000007, 0xeb0b1100, 0x68810081, 0x6180f501, 0x203f6081, 0x22008037, 0xe0008028, 0x4891e047, 
+    0x6800498f, 0xff1bf010, 0xd1071d01, 0x1012f240, 0x498be101, 0x46282200, 0xff11f010, 0xf47f1d40, 
+    0xf240aebe, 0xe0f61013, 0x68004887, 0x4888b148, 0x319bf240, 0x4b858037, 0x1e487802, 0xf954f7f4, 
+    0xf898e6c3, 0x22000000, 0xf0001c40, 0xeb000007, 0xeb0b1100, 0x68810081, 0x7100f501, 0x80376081, 
+    0x80282009, 0x4976487b, 0xf0106800, 0x1d01fee8, 0xf240d108, 0xe0ce101e, 0x22004876, 0x68004970, 
+    0xfeddf010, 0xd1db1d40, 0x101ff240, 0xf89be0c3, 0xbb880000, 0xf7f64870, 0xf8dff836, 0x220081c0, 
+    0x0000f248, 0x1000f8d8, 0xf939f7ed, 0xf8df2500, 0x220081a8, 0x0000f248, 0x1025f858, 0xf92ff7ed, 
+    0x20004967, 0x4b684a67, 0x0100e9cd, 0x0025f858, 0xf88ef7ed, 0x48614602, 0x42826800, 0x4963d208, 
+    0x0000f248, 0xf7ed8037, 0xf04ff91a, 0xe66c0a01, 0xb2ed1c6d, 0xd3da2d04, 0x0f00f1ba, 0xf8a9d1a0, 
+    0xf89b7000, 0xb1380000, 0x68084959, 0x60081c40, 0x4858b281, 0xf8c5f015, 0xfff1f7f8, 0x20014d56, 
+    0xf7f57829, 0x4955fb44, 0x0000f995, 0x49547008, 0xb1b98809, 0x22734953, 0x2201800a, 0x2200708a, 
+    0x485170c8, 0xf0106800, 0x1d01fe7a, 0xf240d108, 0xe0601088, 0x2200484c, 0x6800494a, 0xfe6ff010, 
+    0xd0231d40, 0xf0154849, 0x2301f899, 0x220f4848, 0xf01503d9, 0xf7eef8b0, 0x2002fa5f, 0xf94df7f4, 
+    0x20082100, 0xfaa2f7f6, 0xf7f62001, 0x2001faf0, 0xfacff7f6, 0x2002492a, 0x200a8030, 0x80082200, 
+    0xf0106870, 0x1d01fe4c, 0xe00ad003, 0x1089f240, 0xf240e031, 0xe02e10ae, 0x22004921, 0xf0104618, 
+    0x1d40fe3e, 0xf240d193, 0xe02410af, 0x0000f89b, 0xf7f9b948, 0xf44ff91d, 0xf6403000, 0xf7ed0103, 
+    0xf7f8f850, 0xf7ffffe2, 0x203ffc97, 0x48158028, 0x49132200, 0xf0106800, 0x1d01fe22, 0xf240d107, 
+    0xe00810d0, 0x2200490e, 0xf0104628, 0x1d40fe18, 0xf240d1d8, 0x86a010d1, 0x9ffce8bd, 0x21012200, 
+    0xf2afb510, 0xf01040c5, 0x2108fc55, 0xf0102003, 0x4903fdb3, 0x60483908, 0x0000bd10, 0x00040243, 
+    0x000406c0, 0x00040f10, 0x00057f70, 0xf23c80ba, 0x00040502, 0x000406cc, 0x000413e8, 0x000404f0, 
+    0x40300000, 0xb573eab3, 0x4030ab15, 0xdead0000, 0x00040f20, 0xf2035152, 0x00040242, 0x000401fc, 
+    0x0004031c, 0x0004d1e8, 0x00040ea4, 0xf2060010, 0xf203501a, 0x800849fd, 0xe92d4770, 0xf8df4ff8, 
+    0xf240b3f0, 0x8e812779, 0x4df84604, 0x0a00f04f, 0x93e0f8df, 0xf8db42b9, 0xf2a13000, 0xf1052079, 
+    0xd0640608, 0xf5b1dc64, 0xd07c7fcf, 0xf5b1dc2d, 0xd0797fa4, 0x29b4dc13, 0xdc06d077, 0xd0752900, 
+    0xd07429ac, 0xd17329ad, 0x29b5e125, 0xf5b1d071, 0xd06f7f92, 0x7180f5a1, 0xd1f43925, 0xf5b1e11b, 
+    0xd0687fb3, 0xf5a1dc08, 0x39497180, 0x2917d072, 0x2918d071, 0xe390d1e7, 0x7180f5a1, 0xd0fa3967, 
+    0xd069292d, 0xd1de292e, 0xf240e299, 0x42912202, 0x2002f2a1, 0xdc14d078, 0x7fe4f5b1, 0xdc07d075, 
+    0x0163f110, 0x2909d072, 0x290ad071, 0xe2bdd1cb, 0x7180f5a1, 0xd0de39c9, 0xd0692905, 0xd1c22906, 
+    0x2862e36b, 0xdc06d077, 0xd0d42801, 0xd0732830, 0xd1b82831, 0x2863e35e, 0x2876d0a3, 0x49c3d1b3, 
+    0x68682200, 0xf0103108, 0x1d40fd5a, 0xe3ead07d, 0xf5b049c1, 0x680f7f9f, 0xdc5ed05c, 0xd01128de, 
+    0x285adc2b, 0xdc17d00e, 0xd06f2851, 0xd06e2852, 0xd1982859, 0x220049b5, 0x31086868, 0xfd3ff010, 
+    0xd0651d40, 0xe25fe0b7, 0xe0bfe1ad, 0xe0a7e09b, 0xe0c5e3ef, 0xe1e6e182, 0xd07228a9, 0xd00828aa, 
+    0xd18a28dd, 0x220049ad, 0xf0104618, 0x1d40fd28, 0xe0a0d068, 0xe1c8e19e, 0xf5b0e22a, 0xd0117f97, 
+    0xf5a0dc17, 0x381f7080, 0x2801d074, 0x280ed045, 0x48a3d189, 0x499d2200, 0x68003108, 0xfd0ff010, 
+    0xd0681d40, 0xe3fd2004, 0xe27ce2d5, 0xe246e233, 0xf5a0e292, 0x38357080, 0x2801d071, 0x2808d0ac, 
+    0x4898d184, 0x49912200, 0x68003108, 0xfcf7f010, 0xd06f1d40, 0xe36fe3e7, 0x4993e2e4, 0x7fc0f5b0, 
+    0xc000f8d1, 0xdc2ed02b, 0x7fa8f5b0, 0xdc15d063, 0x7080f5a0, 0xd07c3845, 0xd07b2801, 0xd198280a, 
+    0x22004982, 0x31084638, 0xe393e003, 0xe3e2e3dc, 0xf010e3f2, 0x1d40fcd4, 0xe04cd06d, 0x7080f5a0, 
+    0xd0693871, 0xd0462801, 0xd19a280e, 0x2200487f, 0x31084976, 0xf0106800, 0x1d40fcc2, 0x2006d07e, 
+    0xe3efe3d8, 0xf5b0e3ef, 0xd0117fc8, 0xf5a0dc14, 0x38877080, 0x2801d073, 0x2808d072, 0x4874d198, 
+    0x496a2200, 0x68003108, 0xfca9f010, 0xd0681d40, 0xe3bf2008, 0xe3fee3fe, 0x7000f5a0, 0xd070385d, 
+    0xd1852801, 0x4961e017, 0x80302007, 0x68682200, 0xf0103108, 0x1d01fc94, 0x20acd108, 0xe3ebe202, 
+    0x2200495a, 0x31086868, 0xfc89f010, 0xd1021d40, 0xe7f320ad, 0x4955e3f5, 0x32fff04f, 0x31086868, 
+    0xfcacf010, 0xd1071d01, 0xe7e720b4, 0x2200494f, 0x31086868, 0xfca2f010, 0xd0431d41, 0xd1ea2801, 
+    0x1000f9b6, 0x4220f04f, 0x2000f44f, 0xfed7f7ec, 0xe3fde003, 0xe3fde3fd, 0xf9b6e3fd, 0xf8df0000, 
+    0x28078134, 0x2806d030, 0xf8dfd075, 0x2805812c, 0x2870d072, 0x2871d071, 0x4f48d070, 0xd06e2808, 
+    0xd06d280b, 0xd06c2809, 0xd06b2821, 0xd06a2822, 0xd0692823, 0xd1be2820, 0xe0032002, 0xe3f0e3f0, 
+    0xe3f0e3f0, 0xfe07f7f3, 0x464f2003, 0x0000f889, 0xfe48f7f3, 0x7008493a, 0x0000f997, 0xfc8bf00a, 
+    0xe3f6e7a9, 0xe19d20b5, 0x8028200b, 0x464f4650, 0xa000f889, 0xfe36f7f3, 0x70084931, 0x78004831, 
+    0x4831b140, 0x78037839, 0x78024830, 0x78004830, 0xf88ef7f7, 0xfc17f7f5, 0x0000f8b8, 0x482db918, 
+    0xf0127800, 0xf7f5fabb, 0x4f2bfd05, 0x22072300, 0x46382180, 0xfe4ff014, 0x46382301, 0x21402206, 
+    0xfe49f014, 0x46382300, 0x21082203, 0xfe43f014, 0x46382300, 0x21022201, 0xfe3df014, 0x2006490b, 
+    0x22008030, 0x31086868, 0xfbe9f010, 0xd13a1d01, 0x1024f240, 0xe03ce156, 0xe315e1f0, 0xe396e35c, 
+    0xe3efe3ef, 0xe3efe3ef, 0x0000e3ef, 0x000406c8, 0x00040ea4, 0x00040242, 0x000406bc, 0x0004d1f4, 
+    0x0004063c, 0x0004064c, 0x00040688, 0x0004066c, 0x0004069c, 0x0004031c, 0x000404fe, 0x00040240, 
+    0x00040243, 0x000404ed, 0x0004059d, 0x0004059c, 0x000404ec, 0x00040320, 0xf2034228, 0x220049fc, 
+    0xf0106868, 0x1d40fbac, 0xadfef47f, 0x1025f240, 0xf8b8e118, 0xb1e80000, 0x780048f6, 0xd0192801, 
+    0x217348f5, 0x80012200, 0xa002f880, 0x1000f899, 0x460170c1, 0x0000f8db, 0xfb91f010, 0xd1071d01, 
+    0x1048f240, 0x49ece0fe, 0x46182200, 0xfb87f010, 0xd01a1d40, 0x8028200c, 0x465748e8, 0xa000f880, 
+    0xf7f92000, 0x48e6fa82, 0x28017800, 0x48e5d010, 0xb3987800, 0x8030206e, 0x220048e3, 0x680049dc, 
+    0xfb6df010, 0xd01b1d01, 0xf240e023, 0xe0d91049, 0x80302066, 0x220048dd, 0x680049d5, 0xfb5ff010, 
+    0xd1081d01, 0x1060f240, 0x48d8e0cc, 0x49d02200, 0xf0106800, 0x1d40fb54, 0xf240d16f, 0xe0c11061, 
+    0x1066f240, 0x48d0e0be, 0x49c92200, 0xf0106800, 0x1d40fb46, 0xf240d161, 0xe0b31067, 0x48cce7ff, 
+    0x28017800, 0x48c3d01d, 0x28017800, 0x48c9d034, 0x28018800, 0x48c8d046, 0x28017800, 0x48c7d03f, 
+    0x28017800, 0x48c6d03b, 0x28017800, 0x48c5d037, 0x28017800, 0xf8dfd06f, 0xf8988310, 0xb3d80000, 
+    0x2000e0b4, 0xf997f7f8, 0xf7f72003, 0x2007f9f7, 0xfc21f7f7, 0xfeb0f003, 0xf44f2100, 0xf7f33080, 
+    0x2000fd31, 0xfbfbf7f7, 0xf80cf7fa, 0x200249b7, 0x800806c2, 0xe062211a, 0x80302022, 0x220049a4, 
+    0xf0106868, 0x1d01fafc, 0xf240d107, 0xe0691094, 0x2200499f, 0xf0106868, 0x1d40faf2, 0x48a5d00e, 
+    0xb1c08800, 0x80302021, 0x22004999, 0xf0106868, 0x1d01fae6, 0xe00cd005, 0xe044e046, 0x1095f240, 
+    0xf240e050, 0xe04d109e, 0x22004991, 0xf0106868, 0x1d40fad6, 0x4898d004, 0x28017800, 0xe015d003, 
+    0x109ff240, 0x2023e03e, 0x49898030, 0x68682200, 0xfac5f010, 0xd1071d01, 0x10a8f240, 0x4984e032, 
+    0x68682200, 0xfabbf010, 0xd0051d40, 0x7800488b, 0xd0042801, 0xe00fe009, 0x10a9f240, 0xf04fe022, 
+    0x21125280, 0xf7ec1250, 0x4885fd1a, 0x28017800, 0x0702d109, 0xe0022113, 0xf04f2115, 0xf44f5280, 
+    0xf7ec2000, 0xe098fd0c, 0x78004881, 0x2070b1a8, 0x496f8030, 0x68682200, 0xfa91f010, 0xd1071d01, 
+    0x10c8f240, 0x496ae207, 0x68682200, 0xfa87f010, 0xd1761d40, 0x10c9f240, 0x4876e1fd, 0xb1a87800, 
+    0x80302071, 0x22004962, 0xf0106868, 0x1d01fa78, 0xf240d107, 0xe1ee10ce, 0x2200495d, 0xf0106868, 
+    0x1d40fa6e, 0xf240d169, 0xe1e410cf, 0xf990486a, 0x486a1000, 0x43017800, 0x4969d037, 0x80722201, 
+    0xb1e0700f, 0x78004867, 0xd0180903, 0x1f10ebb2, 0x2011d101, 0x2302e004, 0x1f10ebb3, 0x2012d102, 
+    0xe00c8070, 0xebb32303, 0xd1011f10, 0xe0042011, 0xebb32304, 0xd1021f10, 0x80702012, 0x2005700a, 
+    0x22008030, 0x68684942, 0xfa39f010, 0xd1071d01, 0x2002f240, 0x493ee1af, 0x68682200, 0xfa2ff010, 
+    0xd12a1d40, 0x2003f240, 0x2000e1a5, 0xf8a3f7f8, 0xf7f72003, 0x2007f903, 0xfb2df7f7, 0xfdbcf003, 
+    0x0000f898, 0xd1182801, 0x8030203a, 0x22004846, 0x6800492f, 0xfa13f010, 0xd1091d01, 0x2032f240, 
+    0xe00ae189, 0x22004840, 0x68004929, 0xfa07f010, 0xd0101d40, 0x21014829, 0x483c7001, 0x29017801, 
+    0xac52f47f, 0xa000f880, 0x48392300, 0x21022201, 0xfc41f014, 0xf240e56f, 0xe16c2033, 0x200d491f, 
+    0x48208028, 0xa000f881, 0xbb807800, 0x1002f9b6, 0x29014830, 0x2911d003, 0x2004d068, 0xf8b8e071, 
+    0x29941000, 0x2998d011, 0x2984d00f, 0x2988d00d, 0x29a4d00b, 0x29a8d009, 0x29b4d007, 0x29b8d005, 
+    0x2103d003, 0x1000f889, 0x2300e05d, 0x0100f241, 0xf014220c, 0x2007fc10, 0x49058030, 0x68682200, 
+    0xf9bdf010, 0xd13c1d01, 0x2064f240, 0xe04ae3ef, 0x000406d0, 0x00040235, 0x0004d1f4, 0x0004059e, 
+    0x00040262, 0x00040234, 0x00040e64, 0x000411f8, 0x0004023b, 0x00040236, 0x0004023a, 0x00040529, 
+    0x0004052b, 0x0004023d, 0x0004023c, 0x00040300, 0x000401f9, 0x000401f8, 0x000401fa, 0x000402a4, 
+    0x0004057b, 0x000402a5, 0x00040eb0, 0x0004052e, 0xf23c801c, 0xf38e0040, 0x220049fc, 0xf0106868, 
+    0x1d40f97e, 0xf240d10f, 0xe3b02065, 0x1000f8b8, 0xd0152998, 0xd0132988, 0xd01129a8, 0xd00f29b8, 
+    0xf8892005, 0xf8990000, 0x464f0000, 0xfb7af7f3, 0x700849ef, 0x780148ef, 0x290148ef, 0xe027d01d, 
+    0x46072208, 0x01512300, 0xfba5f014, 0x46382300, 0x21402206, 0xfb9ff014, 0x80302007, 0x220049e3, 
+    0xf0106868, 0x1d01f94c, 0xabeff47f, 0x2078f240, 0xe37de37d, 0x2079f240, 0x49e0e379, 0x29017809, 
+    0x49dfd106, 0x29206809, 0x7839d302, 0xd0352905, 0xa000f880, 0x0000f997, 0xffadf7f7, 0xf7f72005, 
+    0x2000f80d, 0xfa37f7f7, 0xfc53f7ee, 0xf7f97838, 0x48d4f82c, 0x1c496801, 0x20026001, 0xfafaf7f3, 
+    0x600849d1, 0xf7ef7838, 0x48d0fce3, 0x68012200, 0xf7f32002, 0x48cefb05, 0x70c17839, 0xf8802126, 
+    0xe001a004, 0xe16de026, 0x22008001, 0xf8db4601, 0xf0100000, 0x1d01f904, 0xe00ad003, 0x70012101, 
+    0xf240e7c8, 0xe33220ca, 0x220049c1, 0xf0104618, 0x1d40f8f6, 0x48bfd011, 0x28017800, 0x48bed010, 
+    0x68012200, 0xf7f32001, 0x48bcfadb, 0x28017800, 0x2003d016, 0xe45e8028, 0xf240e00f, 0xe31620cb, 
+    0x80302020, 0x220049a9, 0xf0106868, 0x1d01f8d8, 0xab96f47f, 0x20d2f240, 0xf240e309, 0xe30620d3, 
+    0xe7e72002, 0xe07fe03e, 0x200249ad, 0x82b4f8df, 0xf889464f, 0xf8810000, 0xf898a000, 0xb9200000, 
+    0x20fe22ff, 0xf7ee4611, 0x2002fc19, 0xff33f7f7, 0xf7f62006, 0x2000ff93, 0xf9bdf7f7, 0xfc4cf003, 
+    0x0000f898, 0xf7f9b908, 0x489ffa39, 0xf0142100, 0xe002fad8, 0xe0ede0ba, 0x4995e0fc, 0x78382226, 
+    0xf88170c8, 0x800aa004, 0xff9ff7f8, 0x22004990, 0x0000f8db, 0xf893f010, 0xd1081d01, 0x3022f240, 
+    0xe133e2c5, 0x2200498a, 0xf0104618, 0x1d40f888, 0xf240d1a1, 0xe2ba3023, 0x20014989, 0x0000f889, 
+    0xf881464f, 0xf7f7a000, 0x2006fef6, 0xff56f7f6, 0xf7f72000, 0xf003f980, 0x4882fc0f, 0xb9087800, 
+    0xfa49f7f9, 0x21004880, 0xfa9bf014, 0xe0037838, 0xe123e11c, 0xe165e127, 0x22264975, 0xf88170c8, 
+    0x800aa004, 0xff61f7f8, 0x22004971, 0x0000f8db, 0xf855f010, 0xf47f1d01, 0xf240ab2a, 0xe2863056, 
+    0xe176e168, 0xe18ee17c, 0x3057f240, 0xf04fe27f, 0xf9b55280, 0x12501000, 0xfab1f7ec, 0x0000f9b5, 
+    0x0817f04f, 0xd005280a, 0xf0318839, 0xd10c0108, 0xe262e057, 0x78004865, 0x2002b960, 0xfb3ff7f3, 
+    0x8838b140, 0x0008f030, 0xf04fd029, 0x21195280, 0xe0f91250, 0xfe9bf005, 0xf7f42000, 0x495cfb73, 
+    0x4a502001, 0x495b6008, 0x68086812, 0xda014290, 0x60081c40, 0xb2818808, 0x30244853, 0xfa41f014, 
+    0x1000f899, 0xf7f42000, 0x4953fcc2, 0xf881201c, 0xf7f3a000, 0x2000fb03, 0xfd9cf7f6, 0x2002e151, 
+    0xfaebf7f3, 0x80282009, 0x2200484c, 0x8000f8a6, 0x68004936, 0xfff3f00f, 0xd10c1d01, 0x3098f240, 
+    0xe0b3e225, 0xe13ee132, 0xe223e159, 0x2200492f, 0xf00f4638, 0x1d40ffe4, 0xadecf47f, 0x3099f240, 
+    0x2803e215, 0x2804d018, 0x2802d027, 0x2808d03f, 0x2809d07f, 0x2002d1a9, 0xf99df7f3, 0x22004837, 
+    0x8000f8a6, 0x68004921, 0xffc9f00f, 0xf47f1d01, 0xf240aaf2, 0xe1fa30c8, 0x80302010, 0x22004830, 
+    0x6800491a, 0xffbbf00f, 0xf47f1d01, 0xf240aaa9, 0xe1ec30a6, 0x30a7f240, 0x2012e1e9, 0x48298030, 
+    0x49122200, 0xf00f6800, 0x1d01ffaa, 0xf240d108, 0xe1dc30ae, 0x22004823, 0x6800490c, 0xff9ff00f, 
+    0xd0011d40, 0xe6b52005, 0x30aff240, 0x2011e1cf, 0x481d8030, 0x49052200, 0xf00f6800, 0x1d01ff90, 
+    0xaa96f47f, 0x30b6f240, 0xe032e1c1, 0x000406d0, 0x00040243, 0x000402b0, 0x000402b2, 0x000402b1, 
+    0x000401f0, 0x00057f78, 0x00040558, 0x00040584, 0x0004d1f4, 0x000402a4, 0x00040580, 0x00040502, 
+    0x0004059e, 0x0004023d, 0xf203511c, 0x00040eda, 0x00057f7c, 0x00057f80, 0x000401fc, 0x000406bc, 
+    0x0004063c, 0x0004065c, 0x0004064c, 0x30b7f240, 0x2016e18d, 0x48d08030, 0x49ce2200, 0xf00f6800, 
+    0x1d01ff4e, 0xf240d108, 0xe18030be, 0x220048ca, 0x680049c8, 0xff43f00f, 0xd0011d40, 0xe6592009, 
+    0x30bff240, 0xf240e173, 0xe17030c9, 0x2800f44f, 0x1000f9b5, 0x5280f04f, 0xf7ec4640, 0x8838f9a0, 
+    0x0008f030, 0xe002d112, 0xf999f7ec, 0xf9b5e532, 0x21140000, 0xd00e2804, 0xd02d2805, 0xd03c2806, 
+    0xd0522807, 0xd00a2808, 0xd0082809, 0x46402118, 0x5280f04f, 0x48b1e7e8, 0x28037800, 0x48b0d006, 
+    0x68012200, 0xf7f32001, 0xe513f8fb, 0x220048ad, 0x49a88031, 0xf00f6800, 0x1d01ff02, 0xf240d107, 
+    0xe13430ea, 0x220049a3, 0xf00f4660, 0x1d40fef8, 0xf240d1cc, 0xe12a30eb, 0x80302013, 0x220048a2, 
+    0x6800499c, 0xfeebf00f, 0xf47f1d01, 0xf240aa26, 0xe11c30f8, 0x30f9f240, 0x489ae119, 0x80312200, 
+    0x68004994, 0xfedbf00f, 0xd1071d01, 0x4000f240, 0x4990e10d, 0x46602200, 0xfed1f00f, 0xd0011d40, 
+    0xe5e72007, 0x4001f240, 0x2015e101, 0x488f8030, 0x49882200, 0xf00f6800, 0x1d01fec2, 0xaa16f47f, 
+    0x4008f240, 0xf240e0f3, 0xe0f04009, 0xf04f4888, 0x78000200, 0x4987b108, 0x4987e000, 0xf7f32001, 
+    0x200af89f, 0xf8dfe5c6, 0x200e8214, 0xf8988028, 0x07c00000, 0x2101d199, 0xfac2f7f6, 0xf9b82000, 
+    0x1c471000, 0x07c94139, 0x2201d105, 0x4611b2c3, 0xf7f74610, 0xb238f927, 0xdbf02804, 0x2003e49a, 
+    0xfd73f7f8, 0xc1d8f8df, 0x2803b240, 0xf889464f, 0xd0020000, 0xd0172805, 0xf8b8e021, 0x28940000, 
+    0x2884d005, 0x28a4d003, 0x28b4d001, 0x2005d103, 0x23087038, 0x2898e00e, 0x2888d009, 0x28a8d007, 
+    0x28b8d005, 0xe00ad003, 0x0000f8b8, 0x2004e7f3, 0x23077038, 0x22024660, 0xf014213c, 0x7838f8ac, 
+    0xf7f346b9, 0xf8dff86f, 0x2300817c, 0x21402206, 0x0000f888, 0x8028200f, 0xf014485b, 0x485af89c, 
+    0x22012300, 0xf0142102, 0x4858f896, 0x22062301, 0xf0142140, 0x4855f890, 0x22022300, 0xf0142104, 
+    0x7838f88a, 0xf9d6f7f6, 0xf8cd4951, 0x7838a000, 0x4950780b, 0x4950780a, 0xf7ee7809, 0x2000ff34, 
+    0xfe27f7f8, 0x1000f898, 0x2800f44f, 0xf7f34640, 0x2700f849, 0x46082100, 0xf93ef7f4, 0xf6472200, 
+    0x46110300, 0xf8cd4610, 0xf7f6a000, 0x483df9ed, 0x46407801, 0xf836f7f3, 0x11f4f240, 0xf7ec4640, 
+    0x4837f830, 0x21ff2200, 0xf0143042, 0x4601f862, 0xf7ec4640, 0x4939f815, 0xf7ec4640, 0x1c7ff811, 
+    0x2f40b23f, 0x482ed01c, 0x21ff2200, 0xf0143042, 0x28fff850, 0xf899d0ce, 0x464f0000, 0xfd92f7f4, 
+    0x2200482f, 0x70c17839, 0xf8802126, 0x8001a004, 0xf8db4601, 0xf00f0000, 0x1d01fde2, 0xe011d00a, 
+    0x46384f28, 0xf80af014, 0x0104f040, 0xf0144638, 0xe7e0f808, 0x40d6f240, 0x4921e009, 0x46182200, 
+    0xfdcdf00f, 0xf47f1d40, 0xf240ace6, 0x86a040d7, 0x8ff8e8bd, 0xe4dd2010, 0x2200481b, 0xb5102101, 
+    0xfc08f00f, 0x20052108, 0xfd66f00f, 0x39084901, 0xbd106048, 0x000406d0, 0x000406ac, 0x00040234, 
+    0x00040580, 0x00040688, 0x0004066c, 0x0004069c, 0x00040ed9, 0x0094c5f0, 0x00b71b00, 0x00040236, 
+    0xf2060000, 0x00040243, 0xf2034228, 0xf23c8310, 0x000402cb, 0x000402ca, 0x0004057b, 0xdcba01f5, 
+    0x0004d1f4, 0xf203517c, 0x0001385b, 0x4ff1e92d, 0xb09448fa, 0x83e8f8df, 0x27002404, 0xf8b06800, 
+    0x91121078, 0xa07af8b0, 0x907cf8b0, 0xb07ef8b0, 0x4df42600, 0x22002301, 0x46184631, 0x8500e9cd, 
+    0xfc8cf7f1, 0xf8389912, 0xfb100011, 0x9812f100, 0x0010f835, 0x1100fb10, 0x001af838, 0xf200fb10, 
+    0x001af835, 0x2200fb10, 0x0019f838, 0xfb104411, 0xf835f300, 0xfb100019, 0xf8383300, 0xfb10001b, 
+    0xf835fc00, 0xad02001b, 0xc000fb10, 0x44084418, 0x1106eb05, 0x0027f841, 0xf2412100, 0xf7f20000, 
+    0x1c76ff61, 0x2e04b276, 0x1c7fdbc3, 0x42a7b23f, 0x2700dbbe, 0xe0142100, 0xb2001c48, 0x1207eb05, 
+    0xe00b4684, 0x3021f852, 0x6020f852, 0xdd0342b3, 0x6021f842, 0x3020f842, 0xb2001c40, 0xdbf142a0, 
+    0x42a14661, 0x1c7fdbe8, 0x2f04b27f, 0xeb04dbe2, 0x200071d4, 0xeb051049, 0xf8521200, 0x9a143021, 
+    0x3020f842, 0xb2401c40, 0xdbf42804, 0xe8bdb015, 0xe92d8ff0, 0x49b94ff3, 0x2000b085, 0x9003468a, 
+    0x88046808, 0x1c700866, 0xfa0f9002, 0x2500fb80, 0x0000f8da, 0xfb059905, 0xf9b0f704, 0x9a023088, 
+    0x0047eb01, 0x468149b0, 0xfee3f013, 0x0000f8da, 0x9a0249ae, 0x3088f9b0, 0xeb009806, 0x46800047, 
+    0xfed7f013, 0x46584aa8, 0xe00b4ba8, 0xf8521a21, 0xf8427021, 0xf8537020, 0x42491021, 0x1020f843, 
+    0xb2001c40, 0xdbf142a0, 0x0000f8da, 0x4aa04657, 0x78819b03, 0x0094f8d0, 0x0100e9cd, 0x489a499b, 
+    0xfb06f014, 0x4631489a, 0x0086eb00, 0xfee2f014, 0x4b966838, 0x78814a94, 0x0094f8d0, 0x0100e9cd, 
+    0x99034893, 0xf80af014, 0x46496838, 0xf9b09a02, 0x488d3084, 0xfeaef013, 0x46416838, 0xf9b09a02, 
+    0x488a3084, 0xfea6f013, 0xb26d1c6d, 0xdb9f2d04, 0xe78cb007, 0x47fce92d, 0x48804607, 0x46154688, 
+    0x68002301, 0xfb078806, 0xea4ff406, 0xeb020956, 0xeb080144, 0x22000044, 0x0100e9cd, 0x46184639, 
+    0xfb9cf7f1, 0x9006fb07, 0x2014f835, 0xf8282100, 0xf8252010, 0xf8251014, 0xe8bd1010, 0x487687fc, 
+    0x41f0e92d, 0x1000f990, 0x4f724874, 0x78002904, 0x2905d005, 0x283cd00e, 0x2001d212, 0x28bee011, 
+    0x2000d901, 0x496ee00d, 0x78092002, 0xd1082903, 0xe0062005, 0xd201284b, 0xe0022006, 0xe0002008, 
+    0x4a682004, 0xc188f8df, 0xebc02100, 0xf06f00c0, 0xeb02080c, 0x20000ec0, 0x04c1eb07, 0x0000e9c4, 
+    0x1a0b4640, 0x1a43d500, 0xda012800, 0xe0004242, 0xf85c4602, 0x1c405023, 0xf85e280e, 0xe9d46022, 
+    0xfbc52300, 0xe9c42306, 0xdbea2300, 0x29111c49, 0x2000dbe1, 0x01c0eb07, 0x8889680a, 0xea43040b, 
+    0xf84c4112, 0x1c401020, 0xdbf32811, 0x5100f04f, 0x0000f8dc, 0xdc124288, 0xf85c2000, 0x00522020, 
+    0x2020f84c, 0x28111c40, 0xe7f1dbf7, 0x2020f85c, 0xf84c1052, 0x1c402020, 0xdbf72811, 0xf04fe001, 
+    0xf8dc4180, 0x42880000, 0x0000f04f, 0xf85cdcee, 0xf1011020, 0xf84c5100, 0x1c401020, 0xdbf62811, 
+    0x81f0e8bd, 0x4ffee92d, 0xa0b0f8df, 0x2100468c, 0x39fff04f, 0x469b9102, 0x46134f2b, 0x1000f8da, 
+    0x46484606, 0x2101880d, 0x0455eb01, 0xe0112100, 0x1205fb06, 0xe012f83c, 0x2012f833, 0xfe0efb1e, 
+    0xe202fb12, 0x2021f847, 0xdd014282, 0x4610b101, 0xb2091c49, 0xdbeb42a1, 0xd07d2800, 0xf44f2200, 
+    0xe0020100, 0xb2121c52, 0x42881040, 0x2a00dafa, 0x2100dd0a, 0xf857e006, 0x41133021, 0x3021f847, 
+    0xb2091c49, 0xdbf642a1, 0xf44f2100, 0xe0020280, 0xb2091c49, 0x42900040, 0x2900dbfa, 0x2000dd0a, 
+    0xf857e006, 0x408a2020, 0x2020f847, 0xb2001c40, 0xdbf642a0, 0x21402000, 0x0000e01e, 0x00040598, 
+    0x00048908, 0x00049108, 0x0004c108, 0x0004c908, 0x00049908, 0x0004a108, 0x00040242, 0x00040504, 
+    0x0004057b, 0x000406e0, 0x2020f857, 0xda012a40, 0x1020f847, 0xb2001c40, 0xdbf542a0, 0xb2234aff, 
+    0x46484698, 0xf0144611, 0x4643fd3b, 0x1ae8e006, 0x0020f857, 0x0023f847, 0xb21b1c5b, 0xdbf642ab, 
+    0xf005fb06, 0xeb0b4622, 0x48f40180, 0xfd02f013, 0xf04f980c, 0xf8406180, 0x48f11026, 0xf0144629, 
+    0xf8dafd79, 0x4aef0000, 0xf8d07881, 0xe9cd0094, 0x49eb0100, 0xe00048e9, 0x9b02e02e, 0xf988f014, 
+    0xf04f49e8, 0xe0095200, 0xf8512000, 0x005b3020, 0x3020f841, 0xb2001c40, 0xdbf6281f, 0x42906808, 
+    0xf04fddf2, 0x68084280, 0xf04f4290, 0xdd090000, 0x3020f851, 0xf841105b, 0x1c403020, 0x281fb200, 
+    0xe7f0dbf6, 0x2020f851, 0x5200f102, 0x2020f841, 0xb2001c40, 0xdbf5281f, 0x8ffee8bd, 0x4ff7e92d, 
+    0x76c8f500, 0xf1004607, 0xf04f08c8, 0x6030507e, 0xf0166838, 0x4604fa63, 0x42406878, 0xfa5ef016, 
+    0xf0164621, 0x6070f95d, 0x68384604, 0xfa56f016, 0xf8c2f016, 0x46214689, 0x46084605, 0xfa7af016, 
+    0xf8baf016, 0x22004bc0, 0xfef4f015, 0x462a464b, 0xfdbcf015, 0xfab0f015, 0x98024682, 0xf1002402, 
+    0xe0570b01, 0xf04f2501, 0xe00e0900, 0x0025f857, 0xfa34f016, 0xf8561b61, 0xf0161021, 0x4649fa5b, 
+    0xf8c6f016, 0x46811c6d, 0x42a5b22d, 0xf857dbee, 0xf0160024, 0x4649fa23, 0xf8baf016, 0x4000f080, 
+    0xf0164651, 0x2501f91d, 0xe00d4681, 0xf8561b60, 0x46481020, 0xfa3ef016, 0x1025f856, 0xf8a8f016, 
+    0x0025f848, 0xb22d1c6d, 0xdbef42a5, 0x46084649, 0x9024f848, 0xfa2ef016, 0xf86ef016, 0x22004b9a, 
+    0xfea8f015, 0x46894605, 0xf0164650, 0x462af865, 0xf015464b, 0xf015fd6b, 0x4682fa5f, 0x1c642001, 
+    0xf858e005, 0xf8461020, 0x1c401020, 0x42a0b200, 0xb224dbf7, 0xdba5455c, 0x24009d02, 0xe00b1cad, 
+    0x0024f856, 0xf016210f, 0xf016fba6, 0x9901f99b, 0x0024f841, 0xb2241c64, 0xdbf142ac, 0xe92de75c, 
+    0xf8df4ff7, 0xb084a208, 0x46934680, 0x90032000, 0xf8da2101, 0x88060000, 0x0156eb01, 0x497c9102, 
+    0x0072f8b0, 0x1a088809, 0xb2050040, 0xda002d00, 0xf1a62500, 0x42850011, 0xb205dd00, 0x48712400, 
+    0xf0144631, 0x4a6ffc77, 0xeb042000, 0x180f1104, 0x3027f858, 0x1c401947, 0x029bb200, 0xf8422811, 
+    0xdbf43027, 0x0000f8da, 0x4a644b65, 0xf8d07881, 0xe9cd0094, 0x48630100, 0xf0139903, 0xfb04fd8f, 
+    0x9905f706, 0x0909f06f, 0x464b485c, 0xeb019a02, 0xf0130187, 0x485afbde, 0x0187eb0b, 0x464b9a02, 
+    0xfbd7f013, 0xb2641c64, 0xdbc82c04, 0xe92de580, 0x46825fff, 0x68004855, 0x20018807, 0xeb002600, 
+    0x25000b57, 0xfb06e02b, 0x98025407, 0x2014f930, 0xf850980e, 0x9803c024, 0xfe0cfb02, 0x1014f930, 
+    0xf850980f, 0xfb013024, 0xfb02e003, 0xfb01fe03, 0xfb12e31c, 0x0140f202, 0x2101fb11, 0x1943ea4f, 
+    0x468810c9, 0xfb74f014, 0x0014f82a, 0x46484641, 0xfb6ef014, 0x1c6d9901, 0xf821b22d, 0x455d0014, 
+    0x1c76dbd1, 0x2e04b276, 0x2000dbcb, 0x46524601, 0x1307fb00, 0xb2401c40, 0xf82a2804, 0xdbf61013, 
+    0xb0049901, 0xe8bd4610, 0xe4c25ff0, 0x4fffe92d, 0x90b8f8df, 0x2000b083, 0xf8d99002, 0x88050000, 
+    0x086f2001, 0xf7f11c7c, 0x2000f9de, 0xf9dbf7f1, 0xa090f8df, 0xfb84fa0f, 0xf8d92600, 0x99100000, 
+    0xfb064622, 0xf9b0f805, 0xeb013088, 0x491b0048, 0xfb9ff013, 0x0000f8d9, 0x99114622, 0x3088f9b0, 
+    0x0048eb01, 0xf0134916, 0x4a14fb94, 0x4b144658, 0x1a29e00b, 0xc021f852, 0xc020f842, 0x1021f853, 
+    0xf8434249, 0x1c401020, 0x42a8b200, 0xf8d9dbf1, 0x4a0c0000, 0x78819b02, 0x0094f8d0, 0x0100e9cd, 
+    0x48064907, 0xffc4f013, 0x7800480a, 0x2801b1e0, 0x2000d01d, 0x1203e9dd, 0xe00d1a89, 0x0004c108, 
+    0x0004c908, 0x00049908, 0x3ff00000, 0x00040598, 0x00040506, 0x00040322, 0xb2414408, 0xdd152900, 
+    0x0000f04f, 0xe00e4652, 0x0001f04f, 0xf04fe7e2, 0xe7df30ff, 0x3020f852, 0xf301fa43, 0x3020f842, 
+    0x0001f100, 0x42a0b200, 0xe00edbf4, 0x4248da0d, 0xb2434651, 0xe0062000, 0x2020f851, 0xf841409a, 
+    0x1c402020, 0x42a0b200, 0x1e78dbf6, 0xb28146d0, 0x0084eb0a, 0xfb5ef014, 0x23002101, 0x461a2001, 
+    0x8100e9cd, 0xf7f04631, 0x1c76ff9e, 0x2e04b276, 0xaf73f6ff, 0x0000f8d9, 0x1068f890, 0xb0079803, 
+    0xe8bd1a08, 0xb2c04ff0, 0xbc68f7f4, 0x2000b570, 0xfbc2f007, 0x23004df9, 0x21082203, 0xf0134628, 
+    0x4cf7fb5a, 0x28017820, 0x2300d028, 0x22024628, 0xf0132104, 0x2301fb50, 0x22004628, 0xf0134619, 
+    0x2001fb4a, 0xfc5ff7f4, 0x48ee2301, 0x46192200, 0xfb41f013, 0x49ed48ec, 0x780a6800, 0xf9b02101, 
+    0xf7f30044, 0x2100fd2a, 0x1000f240, 0xfb0af7f2, 0xb1287820, 0x4070e8bd, 0xbafbf7f3, 0xe7d52301, 
+    0x4070e8bd, 0xbab7f7f3, 0x4ff0e92d, 0xb08948e0, 0xc80f466d, 0x000fe88d, 0x90042000, 0xf8451e41, 
+    0x1c401020, 0x2804b240, 0x2000dbf9, 0xff3cf7f2, 0x24004fd3, 0x835cf8df, 0x0b30f242, 0x9358f8df, 
+    0xf2402600, 0x78382a00, 0xd0032801, 0x0000f998, 0xd0054286, 0xd05b2c00, 0x46304651, 0xfc81f7f7, 
+    0xb2761c76, 0xdbee2e04, 0xfa52f7f3, 0x4a00f04f, 0x465946d9, 0xf7eb4650, 0x2300fad0, 0xf44f2211, 
+    0xf04f3100, 0xf0134071, 0x2001facf, 0xff0cf7f2, 0xf7ffa805, 0x2000fb0b, 0xff06f7f2, 0xaa052000, 
+    0xf855ae04, 0xf8523020, 0x42991020, 0x5434dd02, 0x1020f845, 0xb2401c40, 0xdbf22804, 0x46504649, 
+    0xfaabf7eb, 0xb2641c64, 0xdbb72c04, 0xf04f2000, 0xf8554480, 0x42a11020, 0x460cda00, 0xb2401c40, 
+    0xdbf62804, 0xf8df46b9, 0x4647a2b4, 0x82b0f8df, 0xf8992500, 0x28010000, 0xf997d003, 0x42850000, 
+    0x5770d010, 0x2801b130, 0x2802d006, 0xe009d006, 0xe7a24649, 0xe0024651, 0xe00049a2, 0x46284641, 
+    0xfc1ff7f7, 0xb26d1c6d, 0xdbe22d04, 0x4000f04f, 0xf7eb4659, 0x2080fa72, 0x01a0f243, 0xfa61f7eb, 
+    0x1010f89d, 0x0013f99d, 0x2012f99d, 0x6101ea40, 0x0011f99d, 0xea400400, 0x43012002, 0xf7eb2080, 
+    0x9900fa3f, 0xf7eb2080, 0x9901fa3b, 0xf7eb2080, 0x9902fa37, 0xf7eb2080, 0x9903fa33, 0xf7eb2080, 
+    0xb009fa2f, 0xe8bd4620, 0xb5708ff0, 0x78304e7c, 0xf7f3b908, 0x2100f9f0, 0xf0032001, 0x2100fab5, 
+    0x2080f44f, 0xfa2ef7f2, 0x20012100, 0xfaacf003, 0x682c4d7d, 0x20c0f424, 0x78306028, 0x497bb9c0, 
+    0x78094874, 0x6000f990, 0xd0222903, 0x17c81cf1, 0x7090eb01, 0x0003f020, 0xb2401a08, 0xfcfaf7f7, 
+    0xf7ff2001, 0xf7f3ff11, 0x4630f9c6, 0xfcf2f7f7, 0xf7ff2001, 0xf7f3ff09, 0xf242f9be, 0x06480140, 
+    0xfa0bf7eb, 0x2100602c, 0x4070e8bd, 0xf0032001, 0x4967ba7b, 0x1c405788, 0x72d0eb00, 0x0201f022, 
+    0xb2401a80, 0xe7d95608, 0x4ff0e92d, 0x1e412000, 0xe9cdb087, 0xe9cd0105, 0x485e0102, 0x485e6804, 
+    0x28017800, 0x257fd07e, 0xb170f8df, 0x90042000, 0x46074681, 0x4a5a4680, 0x4638495a, 0xfb1af7ff, 
+    0x4b5a4859, 0x49574a56, 0x46389000, 0xfbbaf7ff, 0x465a2000, 0xf8514956, 0x1c406020, 0xf108b200, 
+    0xf8420101, 0xfa0f6028, 0x281ff881, 0x4e51dbf2, 0x1007eb07, 0xeb062210, 0x484d0180, 0xf7ff468a, 
+    0x2000fc7d, 0xf85a426e, 0xf5011020, 0xf3417180, 0x42a9214f, 0x1010f824, 0x4629dd00, 0xf82442b1, 
+    0xda001010, 0xf8244631, 0x1c401010, 0x2810b200, 0x2000dde9, 0xf8344601, 0x1c402010, 0x4411b200, 
+    0x2811b209, 0x8c20dbf7, 0xa0f0f8df, 0x493a1a40, 0x1e47eb0a, 0xeb018420, 0x49391347, 0xeb012000, 
+    0xeb041147, 0xf9bc0c40, 0x42aa2002, 0x462add00, 0x2010f821, 0x2002f9bc, 0xda0042b2, 0xf04f4632, 
+    0xf8210c10, 0xf82e2010, 0xebbc2010, 0xf8230f40, 0xdd032010, 0xdd01454a, 0xf982fa4f, 0xb2001c40, 
+    0xe0002810, 0xdbdce00e, 0xf7f04638, 0x1c7fff1b, 0x2f04b27f, 0xaf7ff6ff, 0xfe09f7f1, 0x78004816, 
+    0xe0c2b110, 0xe76f25ff, 0xf990481e, 0x28030000, 0x2804d03a, 0x2805d03c, 0xe0b2d03f, 0xf20350e6, 
+    0x00040502, 0xf2031012, 0x00040598, 0x00040243, 0x0002b704, 0x00040248, 0xfffffd00, 0xfffffa00, 
+    0xfffffe00, 0xfffffc00, 0x00057ffc, 0x0004057b, 0x00040520, 0x000401e8, 0x000402b2, 0x00046908, 
+    0x00042108, 0x00041908, 0x000418f8, 0x00045908, 0x00049908, 0x00041588, 0x00041508, 0x00041408, 
+    0x00041488, 0x00040242, 0x780048fd, 0xe078b148, 0x780048fc, 0xd3042896, 0x48fae073, 0x28827800, 
+    0x48f9d26f, 0xbbe87800, 0x46b82700, 0x20004af7, 0xf853465b, 0xf1a11028, 0xf8425100, 0x1c401020, 
+    0xf108b200, 0xfa0f0101, 0x281ff881, 0xf7ffdbf1, 0x48effa56, 0x1107eb07, 0xeb002210, 0x48eb0181, 
+    0xf7ff4689, 0x2000fbab, 0x1020f859, 0x7180f501, 0x214ff341, 0xf82442a9, 0xdd001010, 0x42b14629, 
+    0x1010f824, 0x4631da00, 0x1010f824, 0xb2001c40, 0xdde92810, 0x46012000, 0x2010f834, 0x44111c40, 
+    0xe000b209, 0xb200e02d, 0xdbf52811, 0xeb0a8c20, 0x4ad91c47, 0x49d71a40, 0x20008420, 0x1e47eb01, 
+    0x1147eb02, 0x0340eb04, 0x2002f9b3, 0xdd0042aa, 0xf821462a, 0xf9b32010, 0x42b22002, 0x4632da00, 
+    0x2010f821, 0x2010f82c, 0x2010f82e, 0xb2001c40, 0xdbe72810, 0xf7f04638, 0x1c7ffe55, 0x2f04b27f, 
+    0x2100db94, 0xf0034608, 0x48c4f90f, 0x28037800, 0x48bcd006, 0x28fa7800, 0x48bbd802, 0xb3a07800, 
+    0x90022000, 0x46082100, 0xf8fef003, 0x4cbc9a02, 0xdd462a00, 0x230148bb, 0xf00c9906, 0x9806fb08, 
+    0x31c8f44f, 0x0c014348, 0xf0134620, 0xf8dff87a, 0x240082d8, 0x46554eb0, 0xeb082200, 0xeb051744, 
+    0xeb061344, 0xf8311144, 0xf8270012, 0xf8230012, 0x1c520012, 0x2a10b212, 0x4620dbf5, 0xfe12f7f0, 
+    0xb2641c64, 0xdbe72c04, 0xe7ffe020, 0x204449a5, 0x22102301, 0x46198008, 0xf7f24610, 0x48a3ff7a, 
+    0xf44f7801, 0xf7f22000, 0xa803f83d, 0x489d9000, 0xaa022301, 0xf00ba906, 0x2000fbd8, 0xfc84f7f2, 
+    0xf64fe7b0, 0x462071ff, 0xf83bf013, 0x49994a98, 0xf7ff488f, 0x4996fb94, 0x4a984b97, 0xe9cd4899, 
+    0x4997b100, 0xfbe3f7ff, 0x78004897, 0xf44fb938, 0xf6403000, 0xf7eb0103, 0xf7f6f814, 0x4990ffa6, 
+    0x4b8d4890, 0xe9cd4a8d, 0xe9dd0100, 0xf7ff1004, 0x2100fc1d, 0xf0034608, 0xb007f887, 0xe92de5c3, 
+    0x488a4ff0, 0xac01b099, 0x4f784d7d, 0x0838f10d, 0xf04f3580, 0xc80f0901, 0x000fe884, 0x68004884, 
+    0x08468800, 0x4b712400, 0xf8cd2200, 0x20019000, 0xf7f0b261, 0x2000fd0b, 0x0cc4eb08, 0x0000e9cc, 
+    0xf857e009, 0x1c401020, 0x2300e9dc, 0xfbc1b200, 0xe9cc2301, 0x42b02300, 0x1c64dbf3, 0x2c04b2e4, 
+    0xa816d3e1, 0xffb1f7f3, 0x46c22400, 0x0b58f10d, 0x46a14626, 0xf93b465f, 0x281e0014, 0x201edd02, 
+    0x0014f827, 0x0014f937, 0xda012800, 0x9014f827, 0x02c4eb0a, 0xca034690, 0x78124a66, 0xf0120052, 
+    0xe9c8f91b, 0x46840100, 0x46884863, 0x1014f937, 0x0011f830, 0x0c810382, 0x7e00fba2, 0xe000fb01, 
+    0x0109fb02, 0x2200205d, 0x3e00fba7, 0xe000fb01, 0x0002fb07, 0x46410d5a, 0xea421543, 0x466022c0, 
+    0xe920f012, 0xeb07af06, 0x469002c4, 0xc2031986, 0x78004852, 0xd10c2801, 0x0034f857, 0xffccf7f3, 
+    0xf248b280, 0x0fc20100, 0x0200e9c8, 0xf8251840, 0xa9010b02, 0x0034f837, 0x1024f851, 0x0401f104, 
+    0x2c04b2e4, 0xd3a58008, 0x78004834, 0xd1002803, 0x463019b6, 0xffb0f7f3, 0x4841b284, 0x6800345d, 
+    0xd0012812, 0xd1022816, 0x434420a2, 0x483d0a24, 0xf244220e, 0xf0120100, 0xb1a0ff8c, 0xf012483a, 
+    0xf644ff5d, 0x428831a4, 0xf244d803, 0x4288713c, 0x4608d200, 0xf6444344, 0x49341070, 0xf0f0fbb4, 
+    0xb0196008, 0x4830e4ff, 0xf0121f00, 0xf242ff47, 0x428801d0, 0xf641d803, 0x428851b0, 0x4608d200, 
+    0xf6414344, 0xe7e87040, 0xe92d4821, 0x680041f0, 0x0068f890, 0xf852f7f4, 0xf0062000, 0x4c10ffad, 
+    0x22032300, 0x21083c50, 0xf0124620, 0x4e16ff44, 0xb1107830, 0x78004804, 0x2301b108, 0xe037e039, 
+    0x000402f5, 0x00040504, 0x000402a4, 0x00049908, 0x00041588, 0x00041508, 0x00041488, 0x0004057b, 
+    0xf203513c, 0x000406d8, 0x00041258, 0x00040243, 0x00047908, 0x00046908, 0x00042108, 0x00041908, 
+    0x00043108, 0x00042908, 0x00040502, 0x0002b714, 0x00040598, 0x00040322, 0x00040d86, 0x00040298, 
+    0x000401f0, 0xf203e80a, 0xc23d0148, 0x00040594, 0x46202300, 0x21042202, 0xfefdf012, 0x46202301, 
+    0x46192200, 0xfef7f012, 0xf7f42001, 0x4c94f80c, 0x22082301, 0x3100f240, 0xf0124620, 0x2301feec, 
+    0x22004620, 0xf0124619, 0x2301fee6, 0x2200488d, 0xf0124619, 0x488cfee0, 0x78022101, 0xf9b0488b, 
+    0xf7f30000, 0xf240f8a8, 0x21001700, 0xf7f14638, 0x2100fea9, 0xf0022001, 0x4d85ff27, 0xf424682c, 
+    0x602820c0, 0xf7f02001, 0x2100fc9e, 0xf7f14638, 0x7830fe99, 0xd0182801, 0xfe99f7f2, 0x22112300, 
+    0x3100f44f, 0x4071f04f, 0xfe9ef012, 0xf7f22001, 0xf242fadb, 0x06c80130, 0xfe8ff7ea, 0x46082100, 
+    0xff02f002, 0xe8bd602c, 0x200081f0, 0xfc7bf7f0, 0xfe31f7f2, 0xe92de7e2, 0xf7ff5ff0, 0x496efe70, 
+    0x0891f04f, 0xf240486b, 0x4a7353aa, 0x55dcf240, 0x78094e6a, 0x4f6a6800, 0xf8df2901, 0xf8dfc1a8, 
+    0xf8dfe1a8, 0xf8df91a8, 0xf8dfa1a8, 0x4c6bb1a8, 0x1000f992, 0x2903d002, 0xe001d059, 0xd0042903, 
+    0xd0782905, 0xd07a2904, 0xf5b0e083, 0xdd0b7faf, 0x41e2f240, 0xdd004288, 0x4b614608, 0x0140eb00, 
+    0x5104f5a1, 0xe00a39ba, 0xda00287d, 0x4b5d207d, 0x01c0eb00, 0x1180ebc1, 0x4139f5a1, 0xfb0139aa, 
+    0x0c003000, 0xe05e7020, 0xdd004298, 0xebc04618, 0xeb061140, 0xfb010181, 0x0d407000, 0xf240e017, 
+    0xfb016151, 0xfb01c100, 0xf3c0e000, 0x70205047, 0xd94e2891, 0x8000f884, 0x42a8e04b, 0x4628dd00, 
+    0x1151f240, 0x9301fb00, 0xa000fb03, 0x70200d80, 0xf641e03f, 0xfb007185, 0x4943b301, 0x1000fb03, 
+    0x5087f3c0, 0x28fa7020, 0x20fad933, 0xf5b0e7ef, 0xdb0d7fa1, 0x512cf240, 0xdd004288, 0x4b3b4608, 
+    0x434121a9, 0x4b3a4419, 0x3000fb01, 0xe7b90d80, 0x1000eba0, 0xeb004937, 0xebc00040, 0xeb011000, 
+    0xf3c01040, 0x70204007, 0xd90c287b, 0x7020207b, 0xe000e00c, 0xf5b0e003, 0xddb07fc3, 0xf5b0e7a4, 
+    0xddc67f9b, 0xb2c0e7b9, 0xd902283c, 0x1dc0b2c0, 0x4829e7bd, 0x28017800, 0x2802d005, 0x4927d003, 
+    0x43087809, 0xf992d110, 0x28040000, 0x2805d002, 0xe009d005, 0x28147820, 0x380ad906, 0x7820e003, 
+    0xd901283c, 0x70203008, 0x0100f640, 0x4628030d, 0xfda7f7ea, 0x46287821, 0x5ff0e8bd, 0xbd90f7ea, 
+    0xf2030444, 0xf2031012, 0x00040243, 0x00040506, 0x00057ffc, 0x00040594, 0x00040284, 0xfffa6eca, 
+    0x10133079, 0xffe89b85, 0x1dcb8bb0, 0xfff063b3, 0x2ec83679, 0xffa22500, 0x00040242, 0x00040504, 
+    0x005d41c4, 0x00c96ba6, 0x61737224, 0xfff7c4ea, 0x18e997a9, 0x00a84018, 0x0004057b, 0x000404f6, 
+    0x5fffe92d, 0x4680f04f, 0x221e4693, 0x4681468a, 0x46314603, 0x46204cfe, 0xfd76f012, 0x464b1d25, 
+    0x4631221e, 0xf0124628, 0xf105fd6f, 0x464b0804, 0x4631221e, 0xf0124640, 0x4631fd67, 0xf108464b, 
+    0x221e0604, 0xf0124630, 0xf04ffd5f, 0x464b5700, 0x4639221d, 0xf0124620, 0x221dfd57, 0x4639464b, 
+    0xf0124628, 0x221dfd51, 0x4639464b, 0xf0124640, 0x221dfd4b, 0x4639464b, 0xf0124630, 0x107ffd45, 
+    0x221c464b, 0x46204639, 0xfd3ef012, 0x464b221c, 0x46284639, 0xfd38f012, 0x464b221c, 0x46404639, 
+    0xfd32f012, 0x464b221c, 0x46304639, 0xfd2cf012, 0x4653123f, 0x46392214, 0xf0124620, 0x2214fd25, 
+    0x46394653, 0xf0124628, 0x2214fd1f, 0x46394653, 0xf0124640, 0x2214fd19, 0x46394653, 0xf0124630, 
+    0x2208fd13, 0x4620465b, 0x46390157, 0xfd0cf012, 0x465b2208, 0x46284639, 0xfd06f012, 0x465b2208, 
+    0x46404639, 0xfd00f012, 0x465b2208, 0x46304639, 0xfcfaf012, 0x9b03013f, 0x4639220c, 0xf0124620, 
+    0x9b03fcf3, 0x4639220c, 0xf0124628, 0x9b03fced, 0x4639220c, 0xf0124640, 0x9b03fce7, 0x4639b004, 
+    0x220c4630, 0x5ff0e8bd, 0xbcdef012, 0x4604b510, 0x48b04601, 0xfcd5f012, 0x462148af, 0xfcd1f012, 
+    0x462148ae, 0xfccdf012, 0x48ad4621, 0x4010e8bd, 0xbcc7f012, 0x4604b510, 0x48a64601, 0xf0121e80, 
+    0x48a5fcc0, 0x1e804621, 0xfcbbf012, 0x462148a3, 0xf0121e80, 0x48a2fcb6, 0xe8bd4621, 0x1e804010, 
+    0xbcaff012, 0x4604b510, 0x489a4601, 0xf0121f00, 0x4899fca8, 0x1f004621, 0xfca3f012, 0x46214897, 
+    0xf0121f00, 0x4896fc9e, 0xe8bd4621, 0x1f004010, 0xbc97f012, 0x4604b510, 0x488e4601, 0xf0121f80, 
+    0x488dfc90, 0x1f804621, 0xfc8bf012, 0x4621488b, 0xf0121f80, 0x488afc86, 0xe8bd4621, 0x1f804010, 
+    0xbc7ff012, 0x4604b510, 0x48824601, 0xf0123816, 0x4881fc78, 0x38164621, 0xfc73f012, 0x4621487f, 
+    0xf0123816, 0x487efc6e, 0xe8bd4621, 0x38164010, 0xbc67f012, 0x5fffe92d, 0xf2484d7a, 0x46920400, 
+    0x220f468b, 0x46034681, 0x46284621, 0xfc73f012, 0x0600f247, 0x220c465b, 0x46284631, 0xfc6bf012, 
+    0x465310f7, 0x46392209, 0xf0124628, 0xf240fc64, 0x9b031880, 0x46412207, 0xf0124628, 0x9b0efc5c, 
+    0x21602205, 0xf0124628, 0x9b0ffc56, 0x21102204, 0xf0124628, 0x9b10fc50, 0x21082203, 0xf0124628, 
+    0x9b11fc4a, 0x21072200, 0xf0124628, 0x4d5efc44, 0x464b220f, 0x46284621, 0xfc3df012, 0x465b220c, 
+    0x46284631, 0xfc37f012, 0x46532209, 0x46284639, 0xfc31f012, 0x22079b03, 0x46284641, 0xfc2bf012, 
+    0x22059b0e, 0x46282160, 0xfc25f012, 0x22049b0f, 0x46282110, 0xfc1ff012, 0x22039b10, 0x46282108, 
+    0xfc19f012, 0x22009b11, 0x46282107, 0xfc13f012, 0x220f4d46, 0x4621464b, 0xf0124628, 0x220cfc0c, 
+    0x4631465b, 0xf0124628, 0x2209fc06, 0x46394653, 0xf0124628, 0x9b03fc00, 0x46412207, 0xf0124628, 
+    0x9b0efbfa, 0x21602205, 0xf0124628, 0x9b0ffbf4, 0x21102204, 0xf0124628, 0x9b10fbee, 0x21082203, 
+    0xf0124628, 0x9b11fbe8, 0x21072200, 0xf0124628, 0x4621fbe2, 0x220f4c2e, 0x4620464b, 0xfbdbf012, 
+    0x465b220c, 0x46204631, 0xfbd5f012, 0x46532209, 0x46204639, 0xfbcff012, 0x22079b03, 0x46204641, 
+    0xfbc9f012, 0x22059b0e, 0x46202160, 0xfbc3f012, 0x22049b0f, 0x46202110, 0xfbbdf012, 0x22039b10, 
+    0x46202108, 0xfbb7f012, 0xb0049b11, 0x22004620, 0x5ff0e8bd, 0xf0122107, 0xe92dbbae, 0x460541f0, 
+    0x36fff240, 0x480f0044, 0x460f2200, 0xf8313836, 0x44203015, 0xf0124631, 0x480bfb9e, 0x0545eb07, 
+    0x46312200, 0x88eb3836, 0xf0124420, 0xe011fb94, 0xf10008b0, 0xf203c658, 0xf203ce58, 0xf203d658, 
+    0xf203de58, 0xf203c486, 0xf203cc86, 0xf203d486, 0xf203dc86, 0x220048ff, 0x463189ab, 0xf0124420, 
+    0x48fdfb7a, 0x8a6b4631, 0x44202200, 0x41f0e8bd, 0xbb71f012, 0x00c0eb00, 0x0045b570, 0xf24048f7, 
+    0x460c76ff, 0x46312200, 0xf0124428, 0x8020fb72, 0x48f32200, 0x44284631, 0xfb6bf012, 0x220080a0, 
+    0x463148ec, 0x44283840, 0xfb63f012, 0x22008120, 0x463148e9, 0x44283840, 0xfb5bf012, 0x220081a0, 
+    0x463148e6, 0x44281c80, 0xfb53f012, 0x22008060, 0x463148e3, 0x44281c80, 0xfb4bf012, 0x220080e0, 
+    0x463148dc, 0x4428383e, 0xfb43f012, 0x22008160, 0x463148d9, 0x4428383e, 0xfb3bf012, 0xf2402100, 
+    0x81e04500, 0xeb042000, 0xf9330381, 0x42aa2010, 0xf5a2db01, 0xf8236200, 0x1c402010, 0x2802b240, 
+    0x1c49dbf3, 0x2904b249, 0xbd70dbec, 0x4604b510, 0x48ca4603, 0x21012200, 0xf0123070, 0x48c8fb0c, 
+    0x21012200, 0x30704623, 0xfb05f012, 0x220048c1, 0x46232101, 0xf0123030, 0x48bffafe, 0x21012200, 
+    0xe8bd4623, 0x30304010, 0xbaf5f012, 0x43f8e92d, 0xf44f4dba, 0x4eba0000, 0x35744fb6, 0x82d8f8df, 
+    0x4cb83674, 0xf1083734, 0x90000834, 0x2102e006, 0x46684622, 0xfb4bf7f1, 0xd01b2801, 0x46282200, 
+    0xf0122101, 0x2800fae6, 0x2200d0f1, 0x21014630, 0xfadff012, 0xd0ea2800, 0x46382200, 0xf0122101, 
+    0x2800fad8, 0x2200d0e3, 0x21014640, 0xfad1f012, 0xd0dc2800, 0x83f8e8bd, 0x41f0e92d, 0x00c0eb00, 
+    0x77fff240, 0x4615880b, 0x489c0044, 0x460e2200, 0x46394420, 0xfaaff012, 0x22004899, 0x463988b3, 
+    0xf0124420, 0x4893faa8, 0x89332200, 0x38404639, 0xf0124420, 0x4890faa0, 0x89b32200, 0x38404639, 
+    0xf0124420, 0x488dfa98, 0x88732200, 0x1c804639, 0xf0124420, 0x488afa90, 0x88f32200, 0x1c804639, 
+    0xf0124420, 0x4883fa88, 0x89732200, 0x383e4639, 0xf0124420, 0x4880fa80, 0x89f32200, 0x383e4639, 
+    0xf0124420, 0x487dfa78, 0x882b2200, 0x1d004639, 0xf0124420, 0x487afa70, 0x89eb2200, 0x1d004639, 
+    0xf0124420, 0x4873fa68, 0x8bab2200, 0x383c4639, 0xf0124420, 0x4870fa60, 0x8d6b2200, 0x383c4639, 
+    0xf0124420, 0x486dfa58, 0x886b2200, 0x1d804639, 0xf0124420, 0x486afa50, 0x8a2b2200, 0x1d804639, 
+    0xf0124420, 0x4863fa48, 0x8beb2200, 0x383a4639, 0xf0124420, 0x4860fa40, 0x8dab2200, 0x383a4639, 
+    0xf0124420, 0x485dfa38, 0x88ab2200, 0x30084639, 0xf0124420, 0x485afa30, 0x8a6b2200, 0x30084639, 
+    0xf0124420, 0x4853fa28, 0x8c2b2200, 0x38384639, 0xf0124420, 0x4850fa20, 0x8deb2200, 0x38384639, 
+    0xf0124420, 0x484dfa18, 0x88eb2200, 0x300a4639, 0xf0124420, 0x484afa10, 0x8aab2200, 0x300a4639, 
+    0xf0124420, 0x4843fa08, 0x8c6b2200, 0x38364639, 0xf0124420, 0x4840fa00, 0x8e2b2200, 0x38364639, 
+    0xf0124420, 0x483df9f8, 0x892b2200, 0x300c4639, 0xf0124420, 0x483af9f0, 0x8aeb2200, 0x300c4639, 
+    0xf0124420, 0x4833f9e8, 0x8cab2200, 0x38344639, 0xf0124420, 0x4830f9e0, 0x8e6b2200, 0x38344639, 
+    0xf0124420, 0x482df9d8, 0x896b2200, 0x300e4639, 0xf0124420, 0x482af9d0, 0x8b2b2200, 0x300e4639, 
+    0xf0124420, 0x4823f9c8, 0x8ceb2200, 0x38324639, 0xf0124420, 0x4820f9c0, 0x8eab2200, 0x38324639, 
+    0xf0124420, 0x481df9b8, 0x89ab2200, 0x30104639, 0xf0124420, 0x481af9b0, 0x8b6b2200, 0x30104639, 
+    0xf0124420, 0x4813f9a8, 0x8d2b2200, 0x38304639, 0xf0124420, 0x4810f9a0, 0x8eeb2200, 0x38304639, 
+    0xe8bd4420, 0xf01241f0, 0xb510b996, 0x46034604, 0x2200480a, 0x3058217f, 0xf98df012, 0x22004808, 
+    0x4623217f, 0xf0123058, 0x2200f986, 0x217f4801, 0xe0094623, 0xf203d450, 0xf203dc50, 0xf203c410, 
+    0xf203cc10, 0xf203517a, 0xf0123018, 0x2200f974, 0xe8bd4623, 0x48fe4010, 0xf012217f, 0xe92db96c, 
+    0x4ffc47f0, 0x89832200, 0x4604213f, 0xf0124638, 0x4df9f962, 0x8ba32200, 0x4628213f, 0xf95bf012, 
+    0x83d8f8df, 0x8da32200, 0x4640213f, 0xf953f012, 0x93bcf8df, 0x8fa32200, 0xf1a9213f, 0x46480902, 
+    0xf949f012, 0x7600f643, 0x220889e3, 0x46384631, 0xf941f012, 0x22088be3, 0x46284631, 0xf93bf012, 
+    0x22088de3, 0x46404631, 0xf935f012, 0x46318fe3, 0xe8bd4648, 0x220847f0, 0xb92df012, 0x47f0e92d, 
+    0x22004fdc, 0x213f8903, 0x46041ebf, 0xf0124638, 0x4dd9f922, 0x8b232200, 0x1ead213f, 0xf0124628, 
+    0xf8dff91a, 0x22008358, 0x213f8d23, 0x0802f1a8, 0xf0124640, 0xf8dff910, 0x22009338, 0x213f8f23, 
+    0x0904f1a9, 0xf0124648, 0xf643f906, 0x89637600, 0x46312208, 0xf0124638, 0x8b63f8fe, 0x46312208, 
+    0xf0124628, 0x8d63f8f8, 0x46312208, 0xf0124640, 0x8f63f8f2, 0x46484631, 0x47f0e8bd, 0xf0122208, 
+    0xe92db8ea, 0x4fbb47f0, 0x88832200, 0x1f3f213f, 0x46384604, 0xf8dff012, 0x22004db7, 0x213f8aa3, 
+    0x46281f2d, 0xf8d7f012, 0x82d0f8df, 0x8ca32200, 0xf1a8213f, 0x46400804, 0xf8cdf012, 0x92b0f8df, 
+    0x8ea32200, 0xf1a9213f, 0x46480906, 0xf8c3f012, 0x7600f643, 0x220888e3, 0x46384631, 0xf8bbf012, 
+    0x22088ae3, 0x46284631, 0xf8b5f012, 0x22088ce3, 0x46404631, 0xf8aff012, 0x46318ee3, 0xe8bd4648, 
+    0x220847f0, 0xb8a7f012, 0x47f0e92d, 0x22004f99, 0x213f8803, 0x46041fbf, 0xf0124638, 0x4d96f89c, 
+    0x8a232200, 0x1fad213f, 0xf0124628, 0xf8dff894, 0x2200824c, 0x213f8c23, 0x0806f1a8, 0xf0124640, 
+    0xf8dff88a, 0x2200922c, 0x213f8e23, 0x0908f1a9, 0xf0124648, 0xf643f880, 0x88637600, 0x46312208, 
+    0xf0124638, 0x8a63f878, 0x46312208, 0xf0124628, 0x8c63f872, 0x46312208, 0xf0124640, 0x8e63f86c, 
+    0x46484631, 0x47f0e8bd, 0xf0122208, 0xb510b864, 0x22018803, 0x4604213e, 0xf0124879, 0x8863f85c, 
+    0x48782201, 0xf012213e, 0x88a3f856, 0x48762201, 0xf012213e, 0x88e3f850, 0xe8bd2201, 0x48734010, 
+    0xf012213e, 0xb510b848, 0x46042201, 0x4603213e, 0xf012486b, 0x486bf840, 0x213e2201, 0xf0124623, 
+    0x4869f83a, 0x213e2201, 0xf0124623, 0x2201f834, 0xe8bd4623, 0x48654010, 0xf012213e, 0xb510b82c, 
+    0x46014604, 0x301a485e, 0xf80bf012, 0x4621485d, 0xf012301a, 0x485cf806, 0x301a4621, 0xf801f012, 
+    0x4621485a, 0x4010e8bd, 0xf011301a, 0xb510bffa, 0x4604b283, 0x2200484f, 0x30a4217f, 0xf80bf012, 
+    0xb2a3484c, 0x217f2200, 0xf01230b4, 0x4849f804, 0x2200b2a3, 0x30c4217f, 0xfffdf011, 0xb2a34846, 
+    0x217f2200, 0xf01130a4, 0x4843fff6, 0x2200b2a3, 0x30b4217f, 0xffeff011, 0xb2a3483f, 0x217f2200, 
+    0xf01130c4, 0x483dffe8, 0x2200b2a3, 0x30a4217f, 0xffe1f011, 0xb2a34839, 0x217f2200, 0xf01130b4, 
+    0x4836ffda, 0x2200b2a3, 0x30c4217f, 0xffd3f011, 0xb2a3482f, 0x217f2200, 0xf01130a2, 0x482cffcc, 
+    0x2200b2a3, 0x30b2217f, 0xffc5f011, 0xb2a34828, 0x217f2200, 0x4010e8bd, 0xf01130c2, 0xb510bfbc, 
+    0x46014604, 0x30384826, 0xff9bf011, 0x46214825, 0xf0113038, 0x4824ff96, 0x30384621, 0xff91f011, 
+    0x46214822, 0x4010e8bd, 0xf0113038, 0xb510bf8a, 0x46014604, 0x3008481a, 0xff83f011, 0x46214819, 
+    0xf0113008, 0x4818ff7e, 0x30084621, 0xff79f011, 0x46214816, 0x4010e8bd, 0xf0113008, 0xb570bf72, 
+    0x0400f241, 0x220c4605, 0x480d4603, 0xf0114621, 0x480cff82, 0x462b220c, 0xf0114621, 0x480aff7c, 
+    0x462b220c, 0xf0114621, 0x220cff76, 0xe00f462b, 0xf203dc68, 0xf203c466, 0xf203cc66, 0xf203d466, 
+    0xf203c640, 0xf203ce40, 0xf203d640, 0xf203de40, 0x48fe4621, 0x4070e8bd, 0xbf5df011, 0x4604b510, 
+    0x48fb4601, 0xff3df011, 0x462148fa, 0xff39f011, 0x462148f9, 0xff35f011, 0x462148f4, 0x4010e8bd, 
+    0xf0113030, 0xb510bf2e, 0x4604b283, 0x220048f0, 0x38ee217f, 0xff3ff011, 0xb2a348ed, 0x217f2200, 
+    0xf01138de, 0x48eaff38, 0x2200b2a3, 0x38ce217f, 0xff31f011, 0xb2a348e7, 0x217f2200, 0xf01138ee, 
+    0x48e4ff2a, 0x2200b2a3, 0x38de217f, 0xff23f011, 0xb2a348e0, 0x217f2200, 0xf01138ce, 0x48deff1c, 
+    0x2200b2a3, 0x38ee217f, 0xff15f011, 0xb2a348da, 0x217f2200, 0xf01138de, 0x48d7ff0e, 0x2200b2a3, 
+    0x38ce217f, 0xff07f011, 0xb2a348d0, 0x217f2200, 0xf01138be, 0x48cdff00, 0x2200b2a3, 0x38ae217f, 
+    0xfef9f011, 0xb2a348c9, 0x217f2200, 0x4010e8bd, 0xf011389e, 0xb510bef0, 0x4604b283, 0x220048c7, 
+    0xf011217f, 0x48c5fee8, 0x2200b2a3, 0x3010217f, 0xfee1f011, 0xb2a348c1, 0x217f2200, 0xf0113020, 
+    0xb2a3feda, 0x220048be, 0xf011217f, 0x48bcfed4, 0x2200b2a3, 0x3010217f, 0xfecdf011, 0xb2a348b8, 
+    0x217f2200, 0xf0113020, 0xb2a3fec6, 0x220048b5, 0xf011217f, 0x48b3fec0, 0x2200b2a3, 0x3010217f, 
+    0xfeb9f011, 0xb2a348af, 0x217f2200, 0xf0113020, 0xb2a3feb2, 0x220048ac, 0xf011217f, 0x48aafeac, 
+    0x2200b2a3, 0x3010217f, 0xfea5f011, 0xb2a348a6, 0x217f2200, 0x4010e8bd, 0xf0113020, 0xb510be9c, 
+    0x46034604, 0x2206489a, 0x38242140, 0xfe93f011, 0x22064898, 0x46232140, 0xf0113824, 0x4896fe8c, 
+    0x21402206, 0x38244623, 0xfe85f011, 0x2206488f, 0x46232140, 0x4010e8bd, 0xf011300c, 0xb510be7c, 
+    0x4604b283, 0x2200488d, 0x1f00217f, 0xfe73f011, 0xb2a3488a, 0x217f2200, 0xf011300c, 0x4887fe6c, 
+    0x2200b2a3, 0x301c217f, 0xfe65f011, 0xb2a34884, 0x217f2200, 0xf0111f00, 0x4881fe5e, 0x2200b2a3, 
+    0x300c217f, 0xfe57f011, 0xb2a3487d, 0x217f2200, 0xf011301c, 0x487bfe50, 0x2200b2a3, 0x1f00217f, 
+    0xfe49f011, 0xb2a34877, 0x217f2200, 0xf011300c, 0x4874fe42, 0x2200b2a3, 0x301c217f, 0xfe3bf011, 
+    0xb2a34871, 0x217f2200, 0xf0111f00, 0x486efe34, 0x2200b2a3, 0x300c217f, 0xfe2df011, 0xb2a3486a, 
+    0x217f2200, 0x4010e8bd, 0xf011301c, 0xb510be24, 0x46034604, 0x22004861, 0x38842101, 0xfe1bf011, 
+    0x2200485f, 0x46232101, 0xf0113884, 0x485dfe14, 0x21012200, 0x38844623, 0xfe0df011, 0x2200485a, 
+    0x46232101, 0x4010e8bd, 0xf0113884, 0xb510be04, 0x46034604, 0x2200484e, 0x38302101, 0xfdfbf011, 
+    0x2200484c, 0x46232101, 0xf0113830, 0x484afdf4, 0x21012200, 0x38304623, 0xfdedf011, 0x46232200, 
+    0x4010e8bd, 0x21014841, 0xbde5f011, 0x4605b570, 0x483f4603, 0x0400f244, 0x4621220e, 0xf0113822, 
+    0x483cfdda, 0x462b220e, 0x38224621, 0xfdd3f011, 0x220e4839, 0x4621462b, 0xf0113822, 0x4833fdcc, 
+    0x4621462b, 0x4070e8bd, 0x300e220e, 0xbdc3f011, 0x4ff0e92d, 0x11f4f240, 0x070cb0bb, 0xf7e94620, 
+    0xf241fd90, 0x462071a0, 0xfd7af7e9, 0x46204e2f, 0xf7e94631, 0x2001fd75, 0xffc8f7ff, 0xf7ff2000, 
+    0x482bfa95, 0x22012306, 0xf011211e, 0x2300fda4, 0x461a2101, 0xf7ff4608, 0x2001f803, 0xff97f7ff, 
+    0xf7ff2000, 0x2001ff94, 0xff91f7ff, 0xf7ff2000, 0xf240ff6e, 0xf7ff10e0, 0xf240f8f5, 0x462011f4, 
+    0xfd5ff7e9, 0x71a1f241, 0xf7e94620, 0x4631fd49, 0xf7e94620, 0x2040fd45, 0xff01f7ff, 0xf7ff2001, 
+    0x20fffede, 0xf8c6f7ff, 0xf7ff20ff, 0x1527f8ab, 0xf7ff4638, 0x2000f88f, 0xf878f7ff, 0xf7ff2000, 
+    0x2001fd3e, 0xfd3bf7ff, 0xe0132100, 0xf203de40, 0xf203c670, 0xf203ce70, 0xf203d670, 0xf203c506, 
+    0xf203cd06, 0xf203d506, 0xf203dd06, 0xdcba01f5, 0xf203e80c, 0xf7f02040, 0x2000fd25, 0xfd1ff7ff, 
+    0xf7ff20ff, 0x20fff897, 0xf87cf7ff, 0xf7ff2000, 0x2000f861, 0xf84af7ff, 0xf7ff2000, 0xf240fe4c, 
+    0x462011f4, 0xfd0df7e9, 0x71a3f241, 0xf7e94620, 0x4631fcf7, 0xf7e94620, 0x2000fcf3, 0xfde3f7ff, 
+    0xf7ff14e0, 0x20fffd84, 0xf874f7ff, 0xf7ff20ff, 0x1420f859, 0xf83ef7ff, 0x7500f640, 0xf7ff4628, 
+    0x2001f825, 0xfd8bf7ff, 0x1800f240, 0xf7ff4640, 0x1460fdb5, 0xfd53f7ff, 0x0000f642, 0xfd4ff7ff, 
+    0x46402100, 0xfcdef7f0, 0x46402100, 0xfcdaf7f0, 0xf7ff2000, 0x2000fd74, 0xfd59f7ff, 0xf7ff2000, 
+    0x20fffd3e, 0xf846f7ff, 0xf7ff20ff, 0x2000f82b, 0xf810f7ff, 0xf7fe2000, 0xf240fff9, 0x462011f4, 
+    0xfcbff7e9, 0x71a4f241, 0xf7e94620, 0x4631fca9, 0xf7e94620, 0x2040fca5, 0xfcc9f7ff, 0xf7ff20ff, 
+    0x20fff829, 0xf80ef7ff, 0xf7fe4638, 0x4628fff3, 0xffdcf7fe, 0xf7ff2000, 0x4640fca2, 0xfc9ff7ff, 
+    0x20402100, 0xfc9ef7f0, 0xf7ff2000, 0x20fffc98, 0xf810f7ff, 0xf7fe20ff, 0x2000fff5, 0xffdaf7fe, 
+    0xf7fe2000, 0xf240ffc3, 0x462011f4, 0xfc89f7e9, 0x71a5f241, 0xf7e94620, 0x4631fc73, 0xf7e94620, 
+    0x2000fc6f, 0xfc5ff7ff, 0x24002003, 0x23029400, 0xe9cd4621, 0x22064002, 0x94014620, 0xf81af7ff, 
+    0x0080f244, 0xffb6f7fe, 0xf7fe4628, 0x2000ff9f, 0xa93a2201, 0xa930540a, 0x4010f821, 0xb2401c40, 
+    0xdbf62804, 0x93fcf8df, 0x0800f04f, 0xa3f8f8df, 0xb3f8f8df, 0x21004efe, 0xeb012000, 0xeb0602c1, 
+    0x23000282, 0x3020f842, 0xb2401c40, 0xdbf82802, 0xb2491c49, 0xdbef2904, 0x24002700, 0x2c00e06b, 
+    0xf240d069, 0xf7fe10ff, 0xf240ffb5, 0xf7fe10fe, 0x2100ff99, 0xf7f02040, 0x2001fc35, 0xf946f7ff, 
+    0x20402100, 0xfc2ef7f0, 0xf960f7ff, 0x20402100, 0xfc28f7f0, 0xf0114648, 0xf856fc31, 0xfa011024, 
+    0xf846f080, 0x46500024, 0xfc28f011, 0x0584eb06, 0xfa016a69, 0x6268f080, 0xf0114658, 0x6ca9fc1f, 
+    0xf080fa01, 0x48db64a8, 0xfc18f011, 0xfa016ee9, 0x66e8f080, 0xf7ff2000, 0x1c64f919, 0x2c02b264, 
+    0x1c7fdbbd, 0x2f10b27f, 0x2100dbb7, 0xeb012000, 0xeb0602c1, 0xf8520282, 0x33083020, 0xf842111b, 
+    0x1c403020, 0x2802b240, 0x1c49dbf5, 0x2904b249, 0x2000dbec, 0xeb00ab3a, 0xeb0601c0, 0xf8560281, 
+    0x68541021, 0x60911a61, 0x4249d500, 0x5c1a6091, 0xd0052a01, 0x20ffe018, 0xff4cf7fe, 0xe79620ff, 
+    0x5fd0f5b1, 0xa930da04, 0x2010f831, 0xe0061c52, 0x5ff0f5b1, 0xa930dd06, 0x2010f831, 0xf8211e52, 
+    0xe0012010, 0x54192100, 0xb2401c40, 0xdbd22804, 0xf7ffa830, 0xf108fb7c, 0xfa0f0001, 0xf1b8f880, 
+    0xf6ff0f0f, 0x2004af58, 0x95002500, 0x462a2302, 0x5002e9cd, 0x46284629, 0xf7fe9501, 0x20ffff4b, 
+    0xff18f7fe, 0xf7fe20ff, 0x2000fefd, 0xfee2f7fe, 0xf7fe2000, 0xf240fecb, 0x070c11f4, 0xf7e94620, 
+    0xf241fb90, 0x462071a6, 0xfb7af7e9, 0x4620499a, 0xfb76f7e9, 0xab042100, 0xeb032000, 0xf8221201, 
+    0x1c405010, 0x2808b240, 0x1c49dbf9, 0x2904b249, 0x4618dbf2, 0xfaf8f7ff, 0xf7ffa804, 0xa804fab2, 
+    0xfa6cf7ff, 0xf7ffa804, 0x2000fa2a, 0xf9fdf7ff, 0xf7fe20ff, 0x20fffedf, 0xfec4f7fe, 0x0080f645, 
+    0xfea8f7fe, 0x7000f640, 0xfe90f7fe, 0x95002002, 0x95012100, 0xe9cd2301, 0x22065002, 0xf7fe4608, 
+    0x2100fef9, 0x200046a8, 0xeb014642, 0xeb0603c1, 0x46900383, 0x2020f843, 0xb2401c40, 0xdbf82804, 
+    0xb2491c49, 0xdbee2904, 0x24002700, 0xb134e007, 0xd0072c01, 0xd0082c02, 0xd10d2c03, 0xf640e008, 
+    0xe0077000, 0x7001f640, 0xf640e004, 0xe0017002, 0x7003f640, 0xfe5af7fe, 0x20402100, 0xfb22f7f0, 
+    0xf7ff2001, 0x2100f833, 0xf7f02040, 0xf7fffb1b, 0x2100f84d, 0xf7f02040, 0x485afb15, 0xfb1ef011, 
+    0x1024f856, 0xf080fa01, 0x0024f846, 0xf0114856, 0xeb06fb15, 0x6a690584, 0xf080fa01, 0x48536268, 
+    0xfb0cf011, 0xfa016ca9, 0x64a8f080, 0xf0114851, 0x6ee9fb05, 0xf080fa01, 0x200066e8, 0xf806f7ff, 
+    0xb2641c64, 0xdbb22c04, 0xb23f1c7f, 0xdbac2f80, 0xf44f2400, 0xaf042900, 0xeb04ad2c, 0xeb0602c4, 
+    0xf8560082, 0xe9d02022, 0x68403102, 0x1a181acb, 0xf8451880, 0xd4010024, 0xe0002000, 0x45484240, 
+    0x0024f845, 0x483ddb00, 0x1a89ab2c, 0x0024f843, 0xf3410340, 0x290011cf, 0x4249da00, 0x2900b209, 
+    0xfb11d05f, 0x0889f101, 0xfa7cf012, 0xf242a932, 0xf8410200, 0xeb000024, 0xeb0101c0, 0xeb021100, 
+    0x0b8b1181, 0x1104eb07, 0xeb00800b, 0xeb031300, 0xeb021340, 0x0b9b1383, 0xeb00804b, 0xeb031340, 
+    0xeb022300, 0x0b9b1303, 0xf240808b, 0x43431369, 0x1303eb02, 0x80cb0b9b, 0x1380ebc0, 0x03c3ebc3, 
+    0x1303eb02, 0x810b0b9b, 0x1300eb00, 0x2340eb03, 0x1303eb02, 0x814b0b9b, 0x2371f240, 0xeb024343, 
+    0x0b9b1303, 0xf240818b, 0x435823d9, 0x1000eb02, 0x81c80b80, 0xeb072000, 0xf8321204, 0x29401010, 
+    0x213fd300, 0x1010f822, 0xb2401c40, 0xdbf42808, 0xb2641c64, 0xdb802c04, 0xf7ffa804, 0xa804f9e5, 
+    0xe094e00e, 0xf203c4a0, 0xf203cca0, 0xf203d4a0, 0x0004d200, 0xf203dca0, 0xdcba01f5, 0x0007ffff, 
+    0xf98ff7ff, 0xf7ffa804, 0xa804f949, 0xf907f7ff, 0xf7ff2000, 0x2404f8da, 0x8000f8cd, 0xf8cd2200, 
+    0x23028004, 0xe9cd4611, 0x46108402, 0xfde2f7fe, 0xf7fe20ff, 0x20fffdaf, 0xfd94f7fe, 0xf7fe2000, 
+    0x2000fd79, 0xfd62f7fe, 0x11f4f240, 0x4628070d, 0xfa27f7e9, 0x71a7f241, 0xf7e94628, 0x49f9fa11, 
+    0xf7e94628, 0x20fffa0d, 0xfd94f7fe, 0xf7fe20ff, 0xf244fd79, 0xf7fe0080, 0xf640fd5d, 0xf7fe7000, 
+    0xf04ffd45, 0x21000900, 0x460cab14, 0xebc1ad22, 0x200002c1, 0x0242eb03, 0x4010f822, 0xb2401c40, 
+    0xdbf92808, 0xeb052000, 0xf8220281, 0x1c404010, 0x2802b240, 0x1c49dbf9, 0x2904b249, 0x461adbe7, 
+    0x46484629, 0xff58f7fe, 0xf0092002, 0x460301ff, 0x1400e9cd, 0xe9cd2100, 0x22064002, 0xf7fe4608, 
+    0x4bd9fd89, 0x20002100, 0x02c1eb01, 0x0282eb03, 0xf8424698, 0x1c404020, 0x2809b240, 0x1c49dbf8, 
+    0x2904b249, 0x2700dbef, 0x462c2500, 0x2000e02e, 0xeb074641, 0xf8221204, 0x1c401010, 0x2808b240, 
+    0xe747dbf9, 0x2c01b314, 0x2c02d023, 0x2c03d07e, 0x2c04d01f, 0x2c05d07b, 0x2c06d01b, 0x2c07d078, 
+    0x2c08d017, 0x2c09d075, 0x2c0ad013, 0x2c0bd072, 0x2c0cd00f, 0x2c0dd06f, 0x2c0ed00b, 0x2c0fd06c, 
+    0x2c10d007, 0x2c11d069, 0xe002d109, 0x10fff240, 0x20ffe000, 0xfd0ef7fe, 0xf7fe20ff, 0x2100fcf3, 
+    0xf7f02040, 0x2001f98f, 0xfea0f7fe, 0x20402100, 0xf988f7f0, 0xfebaf7fe, 0x20402100, 0xf982f7f0, 
+    0x48aa07e0, 0xf011d07e, 0xf858f989, 0xb2001025, 0x1a084646, 0x0025f848, 0xf01148a5, 0xeb06f97f, 
+    0xb2000685, 0x1a086a71, 0x48a26270, 0xf976f011, 0xb2006cb1, 0x64b01a08, 0xf011489f, 0x6ef1f96f, 
+    0x1a08b200, 0x1c6d66f0, 0x2000b26d, 0xfe6ef7fe, 0xb2641c64, 0xdb952c12, 0xb23f1c7f, 0xdb832f80, 
+    0x46432100, 0xeb012000, 0xeb0302c1, 0xf8520282, 0x34404020, 0xf84211e4, 0x1c404020, 0x2809b240, 
+    0x1c49dbf5, 0x2904b249, 0xe007dbec, 0xe0e5e0e0, 0xe0f1e0eb, 0xe0fde0f7, 0xe124e11e, 0x4a822100, 
+    0xeb01ab36, 0xf85200c1, 0xeb024020, 0x94030280, 0x44206850, 0x0021f843, 0xf8d26896, 0x0333e00c, 
+    0xfb9346f3, 0xeb06f7f0, 0x031c030e, 0xf4f0fb94, 0x5800f504, 0x191d6914, 0xfb95032d, 0xf505f5f0, 
+    0x95005500, 0xeb046955, 0xeb0c0c05, 0xea4f0c43, 0xfb9c3c0c, 0xf50efef0, 0xf8cd4e80, 0xf8d2e004, 
+    0xe000e018, 0xeb05e0f6, 0x46f20c0e, 0x0e83ea4f, 0x0e44eb0e, 0xea4f44f4, 0xeb0a0e84, 0xeb0e03c3, 
+    0xebc60e45, 0x44731606, 0xe01cf8d2, 0x160beb06, 0xe008f8cd, 0x060beba6, 0xeb066a12, 0xeb0404c4, 
+    0xeb040485, 0x4473044a, 0xea4f4474, 0x44223c0c, 0x031b9c03, 0xfcf0fb9c, 0xfb930312, 0xfb92f3f0, 
+    0x0324f2f0, 0x5e00e9dd, 0xfaf0fb94, 0x5780f507, 0x0008eb07, 0x040eeb05, 0xe144f8df, 0xf50c4420, 
+    0x44604c00, 0x3380f503, 0xf5024418, 0x441032f0, 0x5080f500, 0x1100033c, 0xf5f0fb94, 0xaf144c47, 
+    0x5b80f5ca, 0xf685fa04, 0x05c1ebc1, 0x3408ea4f, 0x6015f827, 0xf6f0fb94, 0x0445eb07, 0xf686fa0e, 
+    0x9d008066, 0xfb95032d, 0x031bf6f0, 0xf586fa0e, 0xf8dd80a5, 0xea4fe004, 0xfb95350e, 0x4d39f6f0, 
+    0xf586fa05, 0xea4f80e5, 0xfb95350c, 0x4d36f6f0, 0xf586fa05, 0xfb938125, 0x4b34f5f0, 0xfa030312, 
+    0x8163f385, 0xf3f0fb92, 0xfa024a31, 0x81a2f283, 0x320aea4f, 0x3afff240, 0xf3f0fb92, 0xfa024a2d, 
+    0xab22f583, 0x5021f823, 0x350bea4f, 0x4b00f240, 0xf0f0fb95, 0xf080fa02, 0x0281eb03, 0x80504b1f, 
+    0xf9342000, 0x455a2010, 0xf824db76, 0xe077a010, 0xf7fe20ff, 0xf240fbcf, 0xe6be10fe, 0x30fef240, 
+    0xfbc8f7fe, 0x30fdf240, 0xf240e6b7, 0xf7fe70fc, 0xf240fbc1, 0xe6b070fb, 0x40fbf640, 0xfbbaf7fe, 
+    0x40f7f640, 0xf641e6a9, 0xf7fe40f3, 0xf641fbb3, 0xe6a240ef, 0x40e3f643, 0xfbacf7fe, 0x40dff643, 
+    0x0000e69b, 0xdcba01f5, 0x0004d200, 0xf203c4a0, 0xf203cca0, 0xf203d4a0, 0xf203dca0, 0xfffffc00, 
+    0xfffff800, 0xfffff000, 0xffffe000, 0xffffc000, 0xffff8800, 0xfffffe00, 0x40c3f647, 0xfb8af7fe, 
+    0x40bff647, 0xf64fe679, 0xf7fe0087, 0xf64ffb83, 0xe672007f, 0xf812f011, 0x1025f858, 0xfa014646, 
+    0xf848f080, 0x48fe0025, 0xf808f011, 0x0685eb06, 0xfa016a71, 0x6270f080, 0xf01048fa, 0x6cb1ffff, 
+    0xf080fa01, 0x48f864b0, 0xfff8f010, 0xfa016ef1, 0x66f0f080, 0xe7ffe689, 0xda01429a, 0x3010f824, 
+    0xb2401c40, 0xf6ff2807, 0x1c49af7c, 0x2904b249, 0xaea5f6ff, 0x463aa922, 0xf7fe4648, 0xf109fd3d, 
+    0xfa4f0001, 0xf1b9f980, 0xf6ff0f03, 0x2104adbc, 0x90002000, 0x46022302, 0x0102e9cd, 0x90014601, 
+    0xfb68f7fe, 0xf7fe20ff, 0x20fffb35, 0xfb1af7fe, 0xf7fe2000, 0x2000faff, 0xfae8f7fe, 0x11f4f240, 
+    0x4620070c, 0xffadf7e8, 0x71a8f241, 0xf7e84620, 0x49d6ff97, 0xf7e84620, 0x2600ff93, 0x0998f10d, 
+    0x1123f240, 0x464a2000, 0x0340eb00, 0xeb021c40, 0xb2400343, 0xf8232804, 0xdbf51016, 0x4630a926, 
+    0xfc0bf7fe, 0xf7fe20ff, 0x20fffb05, 0xfaeaf7fe, 0x0080f244, 0xfacef7fe, 0x7000f640, 0xfab6f7fe, 
+    0x24002105, 0xe9cdb2f0, 0xe9cd4102, 0x23020400, 0x22064621, 0xf7fe4620, 0x4bbdfb1d, 0x20002100, 
+    0x02c1eb01, 0x0282eb03, 0x4020f842, 0xb2401c40, 0xdbf92803, 0xb2491c49, 0xdbf02904, 0x46982400, 
+    0xb124e005, 0xd0052c01, 0xd10f2c02, 0xf240e007, 0xe00010ff, 0xf7fe20ff, 0x20fffacd, 0x20ffe004, 
+    0xfac8f7fe, 0x10fef240, 0xfaacf7fe, 0x20402100, 0xff48f7ef, 0xeb082700, 0x20010584, 0xfc56f7fe, 
+    0x20402100, 0xff3ef7ef, 0xfc70f7fe, 0x20402100, 0xff38f7ef, 0xf010489f, 0xf858ff41, 0xfa022024, 
+    0x4897f180, 0x1024f848, 0xff38f010, 0xfa016a69, 0x6268f080, 0xf0104893, 0x6ca9ff31, 0xf080fa01, 
+    0x489164a8, 0xff2af010, 0xfa016ee9, 0x66e8f080, 0xf7fe2000, 0x1c7ffc2b, 0x2f10b23f, 0x1c64dbcd, 
+    0x2c03b264, 0x2100dbad, 0x20004645, 0x02c1eb01, 0x0282eb05, 0x3020f852, 0x111b3308, 0x3020f842, 
+    0xb2401c40, 0xdbf52803, 0xb2491c49, 0xdbec2904, 0x4630a922, 0xfbaef7fe, 0x46a82400, 0x465daf2c, 
+    0x00c4eb04, 0x2020f858, 0x0080eb08, 0x68806841, 0x0141eba2, 0xf8471809, 0xd5001024, 0xa8224249, 
+    0x1024f847, 0x2024f930, 0x0084eb00, 0x0002f9b0, 0x01c04410, 0x3000f510, 0x4240d500, 0xf0110100, 
+    0xeb04fe91, 0xb2000244, 0x0142eb09, 0xf82142a8, 0xdb000016, 0x1c644650, 0x2c04b264, 0x0016f821, 
+    0xa926dbce, 0xf7fe4630, 0x1c76fb38, 0x2e03b276, 0xaf16f6ff, 0x20002104, 0x23029000, 0xe9cd4602, 
+    0x46010102, 0xf7fe9001, 0xf240fa55, 0xf7fe1000, 0x2000fa39, 0xfa1ef7fe, 0xf7fe2000, 0x2000fa03, 
+    0xf9e8f7fe, 0xf7fe2000, 0xf240f9d1, 0x070c11f4, 0xf7e84620, 0x4950fe96, 0xf7e84620, 0x494bfe81, 
+    0xf7e84620, 0x484dfe7d, 0x22012300, 0xf010211e, 0xb03bfeb2, 0x8ff0e8bd, 0x23002201, 0x46104611, 
+    0xf7feb510, 0x2001f90d, 0xf8a1f7ff, 0xf7ff2000, 0x2001f89e, 0xf89bf7ff, 0xf7ff2000, 0xf240f878, 
+    0x46201400, 0xf9fef7fe, 0xf7fe2000, 0x483cff4c, 0x22082300, 0xf0104621, 0x483afe8e, 0x22082300, 
+    0xf0104621, 0x4838fe88, 0x22082300, 0xf0104621, 0x2300fe82, 0xe8bd4621, 0x48344010, 0xf0102208, 
+    0x4933be7a, 0x47707008, 0x5fffe92d, 0xf2484d29, 0x46920400, 0x3d0a468b, 0x220f4681, 0x46214603, 
+    0xf0104628, 0xf247fe68, 0x465b0600, 0x4631220c, 0xf0104628, 0x10f7fe60, 0x22094653, 0x46284639, 
+    0xfe59f010, 0x1880f240, 0x22079b03, 0x46284641, 0xfe51f010, 0x22059b0e, 0x46282160, 0xfe4bf010, 
+    0x22049b0f, 0x46282110, 0xfe45f010, 0x22039b10, 0x46282108, 0xfe3ff010, 0x22009b11, 0x46282107, 
+    0xfe39f010, 0x220f4d06, 0x4621464b, 0x46283d0a, 0xfe31f010, 0x465b220c, 0x46284631, 0x0000e01a, 
+    0xf203cca0, 0xf203d4a0, 0xf203dca0, 0xdcba01f5, 0x0004d200, 0xf203c4a0, 0x0017adce, 0xf203e80c, 
+    0xf203c670, 0xf203ce70, 0xf203d670, 0xf203de70, 0x000402f6, 0xfe0ff010, 0x46532209, 0x46284639, 
+    0xfe09f010, 0x22079b03, 0x46284641, 0xfe03f010, 0x22059b0e, 0x46282160, 0xfdfdf010, 0x22049b0f, 
+    0x46282110, 0xfdf7f010, 0x22039b10, 0x46282108, 0xfdf1f010, 0x22009b11, 0x46282107, 0xfdebf010, 
+    0x220f4dff, 0x4621464b, 0xf0104628, 0x220cfde4, 0x4631465b, 0xf0104628, 0x2209fdde, 0x46394653, 
+    0xf0104628, 0x9b03fdd8, 0x46412207, 0xf0104628, 0x9b0efdd2, 0x21602205, 0xf0104628, 0x9b0ffdcc, 
+    0x21102204, 0xf0104628, 0x9b10fdc6, 0x21082203, 0xf0104628, 0x9b11fdc0, 0x21072200, 0xf0104628, 
+    0x4621fdba, 0x220f4ce7, 0x4620464b, 0xfdb3f010, 0x465b220c, 0x46204631, 0xfdadf010, 0x46532209, 
+    0x46204639, 0xfda7f010, 0x22079b03, 0x46204641, 0xfda1f010, 0x22059b0e, 0x46202160, 0xfd9bf010, 
+    0x22049b0f, 0x46202110, 0xfd95f010, 0x22039b10, 0x46202108, 0xfd8ff010, 0xb0049b11, 0x22004620, 
+    0x5ff0e8bd, 0xf0102107, 0xe92dbd86, 0x4dce5fff, 0x0400f248, 0x468b4692, 0x4681220f, 0x46214603, 
+    0xf0104628, 0xf247fd78, 0x465b0600, 0x4631220c, 0xf0104628, 0x10f7fd70, 0x22094653, 0x46284639, 
+    0xfd69f010, 0x1880f240, 0x22079b03, 0x46284641, 0xfd61f010, 0x22059b0e, 0x46282160, 0xfd5bf010, 
+    0x22049b0f, 0x46282110, 0xfd55f010, 0x22039b10, 0x46282108, 0xfd4ff010, 0x22009b11, 0x46282107, 
+    0xfd49f010, 0x220f4db1, 0x4621464b, 0xf0104628, 0x220cfd42, 0x4631465b, 0xf0104628, 0x2209fd3c, 
+    0x46394653, 0xf0104628, 0x9b03fd36, 0x46412207, 0xf0104628, 0x9b0efd30, 0x21602205, 0xf0104628, 
+    0x9b0ffd2a, 0x21102204, 0xf0104628, 0x9b10fd24, 0x21082203, 0xf0104628, 0x9b11fd1e, 0x21072200, 
+    0xf0104628, 0x4d96fd18, 0x464b220f, 0x1ead4621, 0xf0104628, 0x220cfd10, 0x4631465b, 0xf0104628, 
+    0x2209fd0a, 0x46394653, 0xf0104628, 0x9b03fd04, 0x46412207, 0xf0104628, 0x9b0efcfe, 0x21602205, 
+    0xf0104628, 0x9b0ffcf8, 0x21102204, 0xf0104628, 0x9b10fcf2, 0x21082203, 0xf0104628, 0x9b11fcec, 
+    0x21072200, 0xf0104628, 0x4621fce6, 0x220f4c7d, 0x1ea4464b, 0xf0104620, 0x220cfcde, 0x4631465b, 
+    0xf0104620, 0x2209fcd8, 0x46394653, 0xf0104620, 0x9b03fcd2, 0x46412207, 0xf0104620, 0x9b0efccc, 
+    0x21602205, 0xf0104620, 0x9b0ffcc6, 0x21102204, 0xf0104620, 0x9b10fcc0, 0x21082203, 0xf0104620, 
+    0x9b11fcba, 0x4620b004, 0xe8bd2200, 0x21075ff0, 0xbcb1f010, 0x5fffe92d, 0xf2484d63, 0x46920400, 
+    0x1ead468b, 0x220f4681, 0x46214603, 0xf0104628, 0xf247fca2, 0x465b0600, 0x4631220c, 0xf0104628, 
+    0x10f7fc9a, 0x22094653, 0x46284639, 0xfc93f010, 0x1880f240, 0x22079b03, 0x46284641, 0xfc8bf010, 
+    0x22059b0e, 0x46282160, 0xfc85f010, 0x22049b0f, 0x46282110, 0xfc7ff010, 0x22039b10, 0x46282108, 
+    0xfc79f010, 0x22009b11, 0x46282107, 0xfc73f010, 0x220f4d46, 0x4621464b, 0x46281ead, 0xfc6bf010, 
+    0x465b220c, 0x46284631, 0xfc65f010, 0x46532209, 0x46284639, 0xfc5ff010, 0x22079b03, 0x46284641, 
+    0xfc59f010, 0x22059b0e, 0x46282160, 0xfc53f010, 0x22049b0f, 0x46282110, 0xfc4df010, 0x22039b10, 
+    0x46282108, 0xfc47f010, 0x22009b11, 0x46282107, 0xfc41f010, 0x220f4d2a, 0x4621464b, 0x46281f2d, 
+    0xfc39f010, 0x465b220c, 0x46284631, 0xfc33f010, 0x46532209, 0x46284639, 0xfc2df010, 0x22079b03, 
+    0x46284641, 0xfc27f010, 0x22059b0e, 0x46282160, 0xfc21f010, 0x22049b0f, 0x46282110, 0xfc1bf010, 
+    0x22039b10, 0x46282108, 0xfc15f010, 0x22009b11, 0x46282107, 0xfc0ff010, 0x4c124621, 0x464b220f, 
+    0x46201f24, 0xfc07f010, 0x465b220c, 0x46204631, 0xfc01f010, 0x46532209, 0x46204639, 0xfbfbf010, 
+    0x22079b03, 0x46204641, 0xfbf5f010, 0x22059b0e, 0x46202160, 0xfbeff010, 0x46202204, 0xe0072110, 
+    0xf203d496, 0xf203dc96, 0xf203c494, 0xf203cc94, 0xf0109b0f, 0x9b10fbe0, 0x21082203, 0xf0104620, 
+    0x9b11fbda, 0x4620b004, 0xe8bd2200, 0x21075ff0, 0xbbd1f010, 0x5fffe92d, 0x0400f248, 0x220f4692, 
+    0x4681468b, 0x46214603, 0x46284dfe, 0xfbc3f010, 0x0600f247, 0x220c465b, 0x46284631, 0xfbbbf010, 
+    0x465310f7, 0x46392209, 0xf0104628, 0xf240fbb4, 0x9b031800, 0x46412208, 0xf0104628, 0x9b0efbac, 
+    0x21802207, 0xf0104628, 0x9b03fba6, 0x21402206, 0xf0104628, 0x9b0efba0, 0x21202205, 0xf0104628, 
+    0x9b03fb9a, 0x21102204, 0xf0104628, 0x9b0efb94, 0x21082203, 0xf0104628, 0x9b0ffb8e, 0x21042202, 
+    0xf0104628, 0x9b0ffb88, 0x21022201, 0xf0104628, 0x9b0ffb82, 0x21012200, 0xf0104628, 0x4ddafb7c, 
+    0x464b220f, 0x46284621, 0xfb75f010, 0x465b220c, 0x46284631, 0xfb6ff010, 0x46532209, 0x46284639, 
+    0xfb69f010, 0x22089b03, 0x46284641, 0xfb63f010, 0x22079b0e, 0x46282180, 0xfb5df010, 0x22069b03, 
+    0x46282140, 0xfb57f010, 0x22059b0e, 0x46282120, 0xfb51f010, 0x22049b03, 0x46282110, 0xfb4bf010, 
+    0x22039b0e, 0x46282108, 0xfb45f010, 0x22029b0f, 0x46282104, 0xfb3ff010, 0x22019b0f, 0x46282102, 
+    0xfb39f010, 0x22009b0f, 0x46282101, 0xfb33f010, 0x220f4db6, 0x4621464b, 0xf0104628, 0x220cfb2c, 
+    0x4631465b, 0xf0104628, 0x2209fb26, 0x46394653, 0xf0104628, 0x9b03fb20, 0x46412208, 0xf0104628, 
+    0x9b0efb1a, 0x21802207, 0xf0104628, 0x9b03fb14, 0x21402206, 0xf0104628, 0x9b0efb0e, 0x21202205, 
+    0xf0104628, 0x9b03fb08, 0x21102204, 0xf0104628, 0x9b0efb02, 0x21082203, 0xf0104628, 0x9b0ffafc, 
+    0x21042202, 0xf0104628, 0x9b0ffaf6, 0x21022201, 0xf0104628, 0x9b0ffaf0, 0x21012200, 0xf0104628, 
+    0x4621faea, 0x220f4c92, 0x4620464b, 0xfae3f010, 0x465b220c, 0x46204631, 0xfaddf010, 0x46532209, 
+    0x46204639, 0xfad7f010, 0x22089b03, 0x46204641, 0xfad1f010, 0x22079b0e, 0x46202180, 0xfacbf010, 
+    0x22069b03, 0x46202140, 0xfac5f010, 0x22059b0e, 0x46202120, 0xfabff010, 0x22049b03, 0x46202110, 
+    0xfab9f010, 0x22039b0e, 0x46202108, 0xfab3f010, 0x22029b0f, 0x46202104, 0xfaadf010, 0x22019b0f, 
+    0x46202102, 0xfaa7f010, 0xb0049b0f, 0x22004620, 0x5ff0e8bd, 0xf0102101, 0xb57fba9e, 0x11f4f240, 
+    0x070c4606, 0xf7e84620, 0xf241fa6c, 0x462071ab, 0xfa56f7e8, 0x46204967, 0xfa52f7e8, 0xf7fe2001, 
+    0x200afc66, 0xfa5bf7fe, 0x94002400, 0x46202202, 0x46112301, 0xf7ff9401, 0x2007fead, 0x21009400, 
+    0x23029401, 0x4002e9cd, 0x46082204, 0xfdc2f7ff, 0x94002506, 0x94012100, 0x46082302, 0xe9cd2204, 
+    0xf7ff4502, 0x2100fce2, 0x23029400, 0x22044608, 0xe9cd9401, 0xf7ff4502, 0x4630fbe7, 0xff46f7fd, 
+    0x200bb004, 0x4070e8bd, 0xba29f7fe, 0x4604b510, 0x48494601, 0xfa35f010, 0x46214848, 0xfa31f010, 
+    0x46214847, 0xfa2df010, 0x48464621, 0x4010e8bd, 0xba27f010, 0x4ff0e92d, 0xb08b2000, 0xff26f7fd, 
+    0xf44f2100, 0xf7ef3080, 0x2000fa0d, 0xfc2ff7fe, 0xf7fe2001, 0x2100fc2c, 0xf7ef2040, 0xf241fa03, 
+    0xf7ff4008, 0x2701ffd3, 0x96032606, 0x95002500, 0x46322302, 0x5701e9cd, 0x46284629, 0xfd9af7fd, 
+    0x95002301, 0x46192202, 0x95012000, 0xfe42f7ff, 0xf7fe2000, 0x2000fbec, 0xfef8f7fd, 0x46a82400, 
+    0x0a10f10d, 0xf24046b9, 0x464d3bff, 0xb2e72100, 0x23024608, 0xe9cd2206, 0xe9cd9602, 0xf7fd7800, 
+    0x2100fd79, 0xf7ef2040, 0x2001f9cd, 0xfedef7fd, 0x20402100, 0xf9c6f7ef, 0xfef8f7fd, 0x20402100, 
+    0xf9c0f7ef, 0xf7fd2000, 0x2100fed1, 0x46082302, 0xe9cd2206, 0xe9cd7500, 0xf7fd5602, 0x2100fd5b, 
+    0xf7ef2040, 0x2001f9af, 0xfec0f7fd, 0x20402100, 0xf9a8f7ef, 0xfedaf7fd, 0x20402100, 0xf9a2f7ef, 
+    0xe0112200, 0xf203c490, 0xf203cc90, 0xf203d490, 0xf203dc90, 0xdcba01f5, 0xf203c660, 0xf203ce60, 
+    0xf203d660, 0xf203de60, 0x465f48ff, 0xf0104659, 0xf82af9c0, 0x48fd0014, 0x46552200, 0xf0104639, 
+    0xeb05f9b8, 0x46390544, 0x80e82200, 0xf01048f8, 0x81a8f9b0, 0x48f72200, 0xf0104639, 0x8268f9aa, 
+    0xf7fd2000, 0x2100fe83, 0xf7ef2040, 0xa904f96b, 0xf7fdb260, 0x1c64fde2, 0x2c03b224, 0x2100db85, 
+    0xf7ef2040, 0x2001f95f, 0xfb61f7fe, 0xf7fd2001, 0x2100fe6d, 0xf7ef2040, 0xb00bf955, 0x8ff0e8bd, 
+    0x2200b510, 0x21014604, 0x48e34603, 0xf95cf010, 0x220048e1, 0x46232101, 0xf0101d00, 0x48def955, 
+    0x21012200, 0x30084623, 0xf94ef010, 0x220048da, 0x46232101, 0x4010e8bd, 0xf010300c, 0xb510b945, 
+    0x46042201, 0x46032102, 0xf01048d3, 0x48d2f93d, 0x21022201, 0x1d004623, 0xf936f010, 0x220148ce, 
+    0x46232102, 0xf0103008, 0x48cbf92f, 0x21022201, 0xe8bd4623, 0x300c4010, 0xb926f010, 0x2204b510, 
+    0x21304604, 0x48c44603, 0xf91ef010, 0x220448c2, 0x46232130, 0xf0101d00, 0x48bff917, 0x21302204, 
+    0x30084623, 0xf910f010, 0x220448bb, 0x46232130, 0x4010e8bd, 0xf010300c, 0x2208b907, 0xb5704603, 
+    0x46050154, 0x462148b4, 0xf8fef010, 0x220848b2, 0x4621462b, 0xf0101d00, 0x48aff8f7, 0x462b2208, 
+    0x30084621, 0xf8f0f010, 0x462b48ab, 0xe8bd4621, 0x22084070, 0xf010300c, 0xb570b8e7, 0x1470f44f, 
+    0x22124605, 0x48a44603, 0xf0104621, 0x48a2f8dd, 0x462b2212, 0x1d004621, 0xf8d6f010, 0x2212489e, 
+    0x4621462b, 0xf0103008, 0x489bf8cf, 0x4621462b, 0x4070e8bd, 0x300c2212, 0xb8c6f010, 0xf04fb570, 
+    0x460564e0, 0x46032218, 0x46214893, 0xf8bcf010, 0x22184891, 0x4621462b, 0xf0101d00, 0x488ef8b5, 
+    0x462b2218, 0x30084621, 0xf8aef010, 0x462b488a, 0xe8bd4621, 0x22184070, 0xf010300c, 0xb510b8a5, 
+    0x46034604, 0x22004884, 0x384c2101, 0xf89cf010, 0x22004881, 0x46232101, 0xf0103848, 0x487ef895, 
+    0x21012200, 0x38444623, 0xf88ef010, 0x2200487a, 0x46232101, 0xf010383c, 0x4877f887, 0x21012200, 
+    0x38384623, 0xf880f010, 0x22004873, 0x46232101, 0xf0103834, 0x4870f879, 0x21012200, 0x382c4623, 
+    0xf872f010, 0x2200486c, 0x46232101, 0xf0103828, 0x4869f86b, 0x21012200, 0x38244623, 0xf864f010, 
+    0x22004865, 0x46232101, 0xf010381c, 0x4862f85d, 0x21012200, 0x38184623, 0xf856f010, 0x2200485e, 
+    0x46232101, 0x4010e8bd, 0xf0103814, 0xb510b84d, 0x46034604, 0x22044858, 0x384c2110, 0xf844f010, 
+    0x22044855, 0x46232110, 0xf0103848, 0x4852f83d, 0x21102204, 0x38444623, 0xf836f010, 0x2204484e, 
+    0x46232110, 0xf010383c, 0x484bf82f, 0x21102204, 0x38384623, 0xf828f010, 0x22044847, 0x46232110, 
+    0xf0103834, 0x4844f821, 0x21102204, 0x382c4623, 0xf81af010, 0x22044840, 0x46232110, 0xf0103828, 
+    0x483df813, 0x21102204, 0x38244623, 0xf80cf010, 0x22044839, 0x46232110, 0xf010381c, 0x4836f805, 
+    0x21102204, 0x38184623, 0xfffef00f, 0x22044832, 0x46232110, 0x4010e8bd, 0xf00f3814, 0xb570bff5, 
+    0x46034605, 0xf240482c, 0x22087400, 0x384c4621, 0xffeaf00f, 0x22084828, 0x4621462b, 0xf00f3848, 
+    0x4825ffe3, 0x462b2208, 0x38444621, 0xffdcf00f, 0x22084821, 0x4621462b, 0xf00f383c, 0x481effd5, 
+    0x462b2208, 0x38384621, 0xffcef00f, 0x2208481a, 0x4621462b, 0xf00f3834, 0x4817ffc7, 0x462b2208, 
+    0x382c4621, 0xffc0f00f, 0x22084813, 0x4621462b, 0xf00f3828, 0x4810ffb9, 0x462b2208, 0x38244621, 
+    0xffb2f00f, 0x2208480c, 0x4621462b, 0xf00f381c, 0x4809ffab, 0x462b2208, 0x38184621, 0xffa4f00f, 
+    0x462b2208, 0xe0094621, 0xf203c4f2, 0xf203ccf2, 0xf203d4f2, 0xf203dcf2, 0xf1000854, 0xe8bd4879, 
+    0x38144070, 0xbf90f00f, 0x460eb570, 0x48764604, 0x2c012101, 0x7001d100, 0x4d742e01, 0x7029d100, 
+    0x78007829, 0x2101b24b, 0x4608b242, 0xf9f8f7fd, 0x20042100, 0xff66f7ee, 0x7800486d, 0xf7ffb240, 
+    0x2001ff7e, 0xff23f7ff, 0xf7ffb2e0, 0x2003fec8, 0xfea4f7ff, 0xf7ff200b, 0x2000fe80, 0xfe5df7ff, 
+    0xf7ff2001, 0x4630fe3b, 0xfe19f7ff, 0xe8bd7828, 0xb2404070, 0xb570e5f4, 0x0400f24f, 0x220c4605, 
+    0x485c4603, 0xf00f4621, 0x485bff66, 0x462b220c, 0xf00f4621, 0x4859ff60, 0x462b220c, 0xf00f4621, 
+    0x4857ff5a, 0x462b220c, 0xf00f4621, 0x4851ff54, 0x462b220c, 0x302a4621, 0xff4df00f, 0x220c484e, 
+    0x4621462b, 0xf00f302a, 0x484cff46, 0x462b220c, 0x302a4621, 0xff3ff00f, 0x462b4849, 0xe8bd4621, 
+    0x220c4070, 0xf00f302a, 0xb570bf36, 0x46034605, 0xf6474840, 0x220b0400, 0x1f004621, 0xff2bf00f, 
+    0x220b483d, 0x4621462b, 0xf00f1f00, 0x483bff24, 0x462b220b, 0x1f004621, 0xff1df00f, 0x462b4838, 
+    0xe8bd4621, 0x220b4070, 0xf00f1f00, 0xb510bf14, 0x46034604, 0x2200482f, 0x1f802103, 0xff0bf00f, 
+    0x2200482d, 0x46232103, 0xf00f1f80, 0x482bff04, 0x21032200, 0x1f804623, 0xfefdf00f, 0x22004828, 
+    0x46232103, 0x4010e8bd, 0xf00f1f80, 0xe92dbef4, 0x4e2447f0, 0x4f1f2400, 0x1904f640, 0x8074f8df, 
+    0xf8df3e08, 0x3f40a080, 0x0812f108, 0x4649b2c5, 0xf00f4650, 0x42a5fec6, 0x20c4eb06, 0x2301d108, 
+    0x21102204, 0xfed7f00f, 0xeb072301, 0xe00720c4, 0x22042300, 0xf00f2110, 0x2300fece, 0x20c4eb07, 
+    0x21022201, 0xfec7f00f, 0x22042301, 0xeb082110, 0xf00f20c4, 0x1c64fec0, 0x2c04b2e4, 0xe8bdd3d7, 
+    0x000087f0, 0xf1000854, 0x00040244, 0x00040245, 0x000402f6, 0xf203c650, 0xf203ce50, 0xf203d650, 
+    0xf203de50, 0xf203c48a, 0x46032208, 0x0154b570, 0x48ff4605, 0xf00f4621, 0x48fefe9e, 0x462b2208, 
+    0xf00f4621, 0x48fcfe98, 0x462b2208, 0xf00f4621, 0x462bfe92, 0xe8bd4621, 0x48f84070, 0xf00f2208, 
+    0xb510be8a, 0x46042207, 0x46032180, 0xf00f48f0, 0x48f0fe82, 0x21802207, 0xf00f4623, 0x48eefe7c, 
+    0x21802207, 0xf00f4623, 0x2207fe76, 0xe8bd4623, 0x48ea4010, 0xf00f2180, 0x220cbe6e, 0xb5704603, 
+    0x46050294, 0x462148e2, 0xfe65f00f, 0x220c48e1, 0x4621462b, 0xfe5ff00f, 0x220c48df, 0x4621462b, 
+    0xfe59f00f, 0x4621462b, 0x4070e8bd, 0x220c48db, 0xbe51f00f, 0x4605b570, 0x48d54603, 0x2400f240, 
+    0x46212209, 0xf00f1c80, 0x48d2fe46, 0x462b2209, 0x1c804621, 0xfe3ff00f, 0x220948cf, 0x4621462b, 
+    0xf00f1c80, 0x48cdfe38, 0x4621462b, 0x4070e8bd, 0x1c802209, 0xbe2ff00f, 0x4604b510, 0x48c44603, 
+    0x21072200, 0xf00f3008, 0x48c2fe26, 0x21072200, 0x30084623, 0xfe1ff00f, 0x220048bf, 0x46232107, 
+    0xf00f3008, 0x48bdfe18, 0x21072200, 0xe8bd4623, 0x30084010, 0xbe0ff00f, 0x4605b570, 0x48b44603, 
+    0x0400f246, 0x4621220d, 0xf00f387a, 0x48b1fe04, 0x462b220d, 0x387a4621, 0xfdfdf00f, 0x220d48ae, 
+    0x4621462b, 0xf00f387a, 0x48acfdf6, 0x4621462b, 0x4070e8bd, 0x387a220d, 0xbdedf00f, 0x4604b510, 
+    0x48a34603, 0x21012200, 0xf00f387c, 0x48a1fde4, 0x21012200, 0x387c4623, 0xfdddf00f, 0x2200489e, 
+    0x46232101, 0xf00f387c, 0x489cfdd6, 0x21012200, 0xe8bd4623, 0x387c4010, 0xbdcdf00f, 0x4605b570, 
+    0x48934603, 0x0400f241, 0x4621220c, 0xf00f387a, 0x4890fdc2, 0x462b220c, 0x387a4621, 0xfdbbf00f, 
+    0x220c488d, 0x4621462b, 0xf00f387a, 0x488bfdb4, 0x4621462b, 0x4070e8bd, 0x387a220c, 0xbdabf00f, 
+    0x4604b510, 0x48824603, 0x21022201, 0xf00f3876, 0x4880fda2, 0x21022201, 0x38764623, 0xfd9bf00f, 
+    0x2201487d, 0x46232102, 0xf00f3876, 0x487bfd94, 0x21022201, 0xe8bd4623, 0x38764010, 0xbd8bf00f, 
+    0x4605b570, 0x48724603, 0x0400f248, 0x4621220f, 0xf00f387a, 0x486ffd80, 0x462b220f, 0x387a4621, 
+    0xfd79f00f, 0x220f486c, 0x4621462b, 0xf00f387a, 0x486afd72, 0x4621462b, 0x4070e8bd, 0x387a220f, 
+    0xbd69f00f, 0x4604b510, 0x48614603, 0x21012200, 0xf00f3876, 0x485ffd60, 0x21012200, 0x38764623, 
+    0xfd59f00f, 0x2200485c, 0x46232101, 0xf00f3876, 0x485afd52, 0x21012200, 0xe8bd4623, 0x38764010, 
+    0xbd49f00f, 0x5ff3e92d, 0xf7ff2000, 0x2001ffdb, 0xffb6f7ff, 0x78204c52, 0x2001b948, 0xff90f7ff, 
+    0x20402100, 0xfd0ef7ee, 0xf7ff2000, 0x2001ff89, 0xff64f7ff, 0x20402100, 0xfd04f7ee, 0xf7ff2000, 
+    0x2001ff5d, 0xff3af7ff, 0xf7ff2003, 0x7820ff15, 0x3900f44f, 0xd1792800, 0x70202001, 0xfecaf7ff, 
+    0xf7ff2007, 0xf8dffee9, 0xf241a0e8, 0xf8df0600, 0x2400b0e0, 0x0a76f1aa, 0xf1aa1077, 0xf10b0804, 
+    0x46550b84, 0x46502301, 0x21042202, 0xfd03f00f, 0x46482100, 0xfcd6f7ee, 0x46282300, 0x21042202, 
+    0xfcf9f00f, 0x46312301, 0x4640220c, 0xfcf3f00f, 0x46392301, 0x4640220b, 0xfcedf00f, 0x46582200, 
+    0xf00f217f, 0xb245fcf6, 0x23004639, 0x220b4640, 0xfce1f00f, 0x46312300, 0x4640220c, 0xfcdbf00f, 
+    0x2d7e1e6d, 0x1c64d303, 0x2c0ab264, 0xf8dfdbc9, 0x2400a064, 0xb05cf8df, 0x0a76f1aa, 0x0804f1aa, 
+    0x0b84f10b, 0x23014655, 0x22024650, 0xf00f2104, 0x2100fcc2, 0xf7ee4648, 0x2300fc95, 0x22024628, 
+    0xf00f2104, 0x2301fcb8, 0x220c4631, 0xf00f4640, 0x2301fcb2, 0x220b4639, 0xf00f4640, 0x2200fcac, 
+    0x217f4658, 0xfcb5f00f, 0xe00bb245, 0x0000e09e, 0xf203c280, 0xf203ca80, 0xf203d280, 0xf203da80, 
+    0x000408d8, 0x46392300, 0x4640220b, 0xfc93f00f, 0x46312300, 0x4640220c, 0xfc8df00f, 0x2d7e1e6d, 
+    0x1c64d303, 0x2c0ab264, 0xf8dfdbbc, 0x2400a514, 0xb50cf8df, 0x0804f1aa, 0x0bfaf10b, 0x23014655, 
+    0x22024650, 0xf00f2104, 0x2100fc76, 0xf7ee4648, 0x2300fc49, 0x22024628, 0xf00f2104, 0x2301fc6c, 
+    0x220c4631, 0xf00f4640, 0x2301fc66, 0x220b4639, 0xf00f4640, 0x2200fc60, 0x217f4658, 0xfc69f00f, 
+    0x4639b245, 0x46402300, 0xf00f220b, 0x2300fc54, 0x220c4631, 0xf00f4640, 0x1e6dfc4e, 0xd3032d7e, 
+    0xb2641c64, 0xdbc92c0a, 0xa498f8df, 0xf8df2400, 0xf1aab494, 0xf10b0804, 0x46550bfa, 0x46502301, 
+    0x21042202, 0xfc37f00f, 0x46482100, 0xfc0af7ee, 0x46282300, 0x21042202, 0xfc2df00f, 0x46312301, 
+    0x4640220c, 0xfc27f00f, 0x46392301, 0x4640220b, 0xfc21f00f, 0x46582200, 0xf00f217f, 0xb245fc2a, 
+    0x23004639, 0x220b4640, 0xfc15f00f, 0x46312300, 0x4640220c, 0xfc0ff00f, 0x2d7e1e6d, 0x1c64d303, 
+    0x2c0ab264, 0x2000dbc9, 0xfdb4f7ff, 0xf7ff2003, 0x9800fd94, 0xfd75f7ff, 0xf7ff9801, 0x2100fd55, 
+    0x4648464c, 0xfbcef7ee, 0x23014dff, 0x461a2102, 0xf00f4628, 0x2100fbf0, 0xf7ee2040, 0x4efafbc3, 
+    0x22063676, 0x21404630, 0xfbf3f00f, 0x2900b241, 0x2300d1f7, 0x22014628, 0xf00f2102, 0x2100fbdc, 
+    0xf7ee4620, 0x4df1fbaf, 0x21022301, 0x4628461a, 0xfbd1f00f, 0x20402100, 0xfba4f7ee, 0x36764eeb, 
+    0x46302206, 0xf00f2140, 0xb241fbd4, 0xd1f72900, 0x46282300, 0x21022201, 0xfbbdf00f, 0x46202100, 
+    0xfb90f7ee, 0x23014dde, 0x461a2102, 0x46283580, 0xfbb1f00f, 0x20402100, 0xfb84f7ee, 0x36f64ed8, 
+    0x46302206, 0xf00f2140, 0xb241fbb4, 0xd1f72900, 0x46282300, 0x21022201, 0xfb9df00f, 0x46202100, 
+    0xfb70f7ee, 0x23014ccf, 0x461a2102, 0x46203480, 0xfb91f00f, 0x20402100, 0xfb64f7ee, 0x35f64dc9, 
+    0x46282206, 0xf00f2140, 0xb241fb94, 0xd1f72900, 0x46202300, 0x21022201, 0xfb7df00f, 0xf7ff2000, 
+    0xe8bdfcf0, 0x20005ffc, 0xe92de4ce, 0x46804ff0, 0x460f48bf, 0xa2fcf8df, 0xad10b099, 0xe885c81e, 
+    0xc81e001e, 0xe88dad04, 0xc81e001e, 0x001ee885, 0xad14c81e, 0x001ee885, 0xad0cc81e, 0x001ee885, 
+    0xac08c80f, 0xe8842500, 0x2400000f, 0x29c5ea4f, 0x0144eb09, 0x060aeb01, 0xf00f4630, 0x0b03fb2f, 
+    0x021ff000, 0x1145f3c0, 0xf1b84618, 0xd10d0f01, 0xc040f9bd, 0xdd02458c, 0xb2801f18, 0xf9bde004, 
+    0x458cc000, 0x1d18da02, 0x1010f8bd, 0xd10d2f01, 0xc050f9bd, 0xdd014594, 0xe0041e40, 0xc030f9bd, 
+    0xda034594, 0xf8bd1c40, 0xb2802020, 0xd0074298, 0xeb000300, 0x44101041, 0x4630b281, 0xfb01f00f, 
+    0x2c421c64, 0x1c6ddbc4, 0x2d04b26d, 0x2500dbbd, 0x0a10f10d, 0x0b20f10d, 0xea4f2402, 0x488d29c5, 
+    0x0144eb09, 0x180e30a0, 0xf00f4630, 0x0b03fae7, 0x021ff000, 0x1145f3c0, 0xf1b84618, 0xd1150f01, 
+    0x0c40f10d, 0x0c44eb0c, 0xc002f9bc, 0xdd02458c, 0xb2801f18, 0x46ece007, 0x0c44eb0c, 0xc002f9bc, 
+    0xda03458c, 0xeb0a1d18, 0x88490144, 0xd1162f01, 0x0c50f10d, 0x0c44eb0c, 0xc002f9bc, 0xdd014594, 
+    0xe0081e40, 0x0c30f10d, 0x0c44eb0c, 0xc002f9bc, 0xda044594, 0xeb0b1c40, 0xb2800244, 0x42988852, 
+    0x0300d007, 0x1041eb00, 0xb2814410, 0xf00f4630, 0x1c64faa8, 0xdbb22c06, 0xb26d1c6d, 0xdbab2d04, 
+    0xe8bdb019, 0xe92d8ff0, 0x4c5f47f0, 0x220c4691, 0x3c8a468a, 0x02964607, 0x46314603, 0xf00f4620, 
+    0x4d5afaaa, 0x463b220c, 0x3d8a4631, 0xf00f4628, 0xf8dffaa2, 0x220c814c, 0x4631463b, 0x080af1a8, 
+    0xf00f4640, 0x4631fa98, 0x220c4e4e, 0x3e0a463b, 0xf00f4630, 0xf240fa90, 0x46533700, 0x46392208, 
+    0xf00f4620, 0x2208fa88, 0x46394653, 0xf00f4628, 0x2208fa82, 0x46394653, 0xf00f4640, 0x2208fa7c, 
+    0x46394653, 0xf00f4630, 0x2206fa76, 0x21c0464b, 0xf00f4620, 0x2206fa70, 0x21c0464b, 0xf00f4628, 
+    0x2206fa6a, 0x21c0464b, 0xf00f4640, 0x464bfa64, 0xe8bd4630, 0x220647f0, 0xf00f21c0, 0x2000ba5c, 
+    0xf7ffb510, 0x2202fcef, 0x20012103, 0xff9bf7ff, 0xf7f22000, 0x2001f8a1, 0xf89ef7f2, 0xf7f22000, 
+    0x2101f89b, 0xf7ff2000, 0x2100fcfd, 0xf7ff2001, 0xf44ffecc, 0x21003400, 0xf7ee4620, 0x2101fa13, 
+    0xf7ff2000, 0x2100fcef, 0xf7ff2001, 0x2101fceb, 0xf7ff2000, 0x2100feba, 0xf7ee4620, 0x2100fa03, 
+    0x4010e8bd, 0xe4dd2001, 0x41f0e92d, 0x23004c16, 0x21042202, 0xf00f4620, 0x4d14fa1e, 0x22022300, 
+    0x46282104, 0xfa17f00f, 0x23004e0d, 0x36802202, 0x46302104, 0xfa0ff00f, 0x23004f0a, 0x37802202, 
+    0x46382104, 0xfa07f00f, 0x20402100, 0xf9daf7ee, 0x46202301, 0x21042202, 0xf9fdf00f, 0xe00b2301, 
+    0xf203d20a, 0xf203da0a, 0xf203c28a, 0xf203ca8a, 0x0002b724, 0xf203c000, 0x46282202, 0xf00f2104, 
+    0x2301f9ea, 0x22024630, 0xf00f2104, 0x2301f9e4, 0x22024638, 0xf00f2104, 0xf24af9de, 0x48674410, 
+    0xf00f4621, 0x4866f9be, 0xf00f4621, 0x4865f9ba, 0xf00f4621, 0x4864f9b6, 0xf00f4621, 0x485ff9b2, 
+    0x240cf24a, 0x1e804621, 0xf9abf00f, 0x4621485c, 0xf00f1e80, 0x485bf9a6, 0x1e804621, 0xf9a1f00f, 
+    0x46214859, 0xf00f1e80, 0x4854f99c, 0x46211f24, 0xf00f1f00, 0x4852f996, 0x1f004621, 0xf991f00f, 
+    0x46214850, 0xf00f1f00, 0x484ff98c, 0x1f004621, 0xf987f00f, 0xf24a4849, 0x46211406, 0xf00f1f80, 
+    0x4847f980, 0x1f804621, 0xf97bf00f, 0x46214845, 0xf00f1f80, 0x4844f976, 0x1f804621, 0xf971f00f, 
+    0xf246483e, 0x46211404, 0xf00f3808, 0x483cf96a, 0x38084621, 0xf965f00f, 0x4621483a, 0xf00f3808, 
+    0x4839f960, 0x38084621, 0xf95bf00f, 0xf2424833, 0x46211404, 0xf00f380a, 0x4831f954, 0x380a4621, 
+    0xf94ff00f, 0x4621482f, 0xf00f380a, 0x482ef94a, 0x380a4621, 0xf945f00f, 0xf2404828, 0x46213480, 
+    0xf00f3054, 0x4826f93e, 0x30544621, 0xf939f00f, 0x46214824, 0xf00f3054, 0x4621f934, 0xe8bd4822, 
+    0x305441f0, 0xb92df00f, 0xf240b5f8, 0x462114f4, 0x46280725, 0xf915f7e7, 0x71bbf241, 0xf7e74628, 
+    0x4e1af8ff, 0x46314628, 0xf8faf7e7, 0xf7f12000, 0x2030fd73, 0xfd4ef7f1, 0xf7f12001, 0x2200ff3b, 
+    0x21009200, 0x22034613, 0xf0024608, 0xf7fff837, 0x2003fefb, 0xfec3f7ff, 0xf7f12000, 0x4621ff2b, 
+    0xf7e74628, 0xf241f8ee, 0x462871bc, 0xf8d8f7e7, 0x46284631, 0x40f8e8bd, 0xb8d2f7e7, 0xf203c0aa, 
+    0xf203c8aa, 0xf203d0aa, 0xf203d8aa, 0xdcba01f5, 0x4c3cb570, 0x211f2300, 0x4620461a, 0xf8fbf00f, 
+    0xf2404838, 0x220535e0, 0x301a4629, 0xf901f00f, 0x46032205, 0x46204629, 0xf8edf00f, 0x46202301, 
+    0x0299220a, 0xf8e7f00f, 0x23024c2e, 0xf24f220c, 0x34200100, 0xf00f4620, 0x2304f8de, 0x22004620, 
+    0xf00f210f, 0x2301f8d8, 0x210f2200, 0xf00f1f20, 0x2301f8d2, 0x210f2200, 0xe8bd1ea0, 0xf00f4070, 
+    0x4821b8ca, 0xf00fb510, 0x4920f8a9, 0x80084a20, 0x1140f3c0, 0xf3c07011, 0x4a1e1180, 0x4a1e7011, 
+    0xf3c07011, 0x4a1d11c0, 0x1000f3c0, 0x22087011, 0x7008491b, 0x48140151, 0xf00f1d00, 0x4919f8ba, 
+    0x20007008, 0x70084918, 0x2100bd10, 0x6e084a17, 0xd1014290, 0x66092000, 0x480bb281, 0xb881f00f, 
+    0xf64b4809, 0xb51031b3, 0xf00f3086, 0xf7fff87a, 0xf7ffffec, 0x490effc6, 0x70082000, 0x4010e8bd, 
+    0x0000e786, 0xf23c8204, 0xf23c8034, 0x0004052c, 0x000402c8, 0x000402ad, 0x000402ac, 0x00040529, 
+    0x0004052a, 0x0004052b, 0x00040320, 0xf1205a2d, 0x0004055c, 0x4db7b570, 0x2200b283, 0x21014604, 
+    0xf00f4628, 0xb2a3f868, 0x22014628, 0xf00f2102, 0xb2a3f862, 0x22024628, 0xf00f2104, 0x2301f85c, 
+    0x22034628, 0xf00f2108, 0xb2a3f856, 0xe8bd4628, 0x22044070, 0xf00f2110, 0xe92db84e, 0x48a641f0, 
+    0xf00f2100, 0x48a4f82e, 0x1c802100, 0xf829f00f, 0x210048a1, 0xf00f1d00, 0x489ff824, 0x1d802100, 
+    0xf81ff00f, 0x2100489c, 0xf00f3008, 0x489af81a, 0x300a2100, 0xf815f00f, 0x21004897, 0xf00f300c, 
+    0x4895f810, 0x300e2100, 0xf80bf00f, 0x21004892, 0xf00f3010, 0x4890f806, 0x30122140, 0xf801f00f, 
+    0x2100488d, 0xf00e3014, 0x488bfffc, 0x30162104, 0xfff7f00e, 0x21004888, 0xf00e3018, 0x4886fff2, 
+    0x301a2100, 0xffedf00e, 0x21004883, 0xf00e301c, 0x4882ffe8, 0xf00e2100, 0x4881ffe4, 0x1cad4d7d, 
+    0x487d7801, 0x1c843020, 0x29001e86, 0x0100f04f, 0x4607d019, 0xffd5f00e, 0x46382301, 0x21202205, 
+    0xffe9f00e, 0x46202100, 0xffcbf00e, 0x46282100, 0xffc7f00e, 0x4100f240, 0xf00e4630, 0xe8bdffc2, 
+    0x200141f0, 0xf00ee766, 0x2100ffbc, 0xf00e4620, 0x2100ffb8, 0xf00e4628, 0xf242ffb4, 0xe7eb4192, 
+    0x460cb510, 0x78094966, 0xd1152900, 0x4862b283, 0x21032200, 0xf00e301e, 0x485fffbe, 0x2200b2a3, 
+    0x1d00210f, 0xffb7f00e, 0x485a2301, 0xe8bd2205, 0x21204010, 0xbfaff00e, 0x4859bd10, 0x28007800, 
+    0x4855d106, 0x21032300, 0x301e461a, 0xbfa3f00e, 0xb5104770, 0x4952460c, 0x29007809, 0xb283d115, 
+    0x2203484d, 0x301e2118, 0xff95f00e, 0xb2a3484a, 0x210f2200, 0xf00e300a, 0x2301ff8e, 0x22064845, 
+    0x4010e8bd, 0xf00e2140, 0xbd10bf86, 0x78004844, 0xd1062800, 0x23004840, 0x21182203, 0xf00e301e, 
+    0x4770bf7a, 0x460cb510, 0x7809493d, 0xd1152900, 0x4839b283, 0x21c02206, 0xf00e301e, 0x4836ff6c, 
+    0x2200b2a3, 0x3010210f, 0xff65f00e, 0x48312301, 0xe8bd2207, 0x21804010, 0xbf5df00e, 0x4830bd10, 
+    0x28007800, 0x482cd106, 0x22062300, 0x301e21c0, 0xbf51f00e, 0x48284770, 0x22062301, 0x30202140, 
+    0xbf49f00e, 0x23004824, 0x21402206, 0xf00e3020, 0xb510bf42, 0x4922460c, 0x29007809, 0xb283d115, 
+    0x220c481d, 0x0291301e, 0xff35f00e, 0xb2a3481a, 0x210f2200, 0xf00e301c, 0x2301ff2e, 0x22094815, 
+    0x4010e8bd, 0xf00e0259, 0xbd10bf26, 0x78004814, 0xd1062800, 0x4810220c, 0x02912300, 0xf00e301e, 
+    0x4770bf1a, 0xf000b510, 0x2100f81d, 0xf7ff2001, 0x2100ff47, 0xf7ff2001, 0x2100ff6c, 0xf7ff2001, 
+    0x2100ff91, 0xf7ff2001, 0x2100ffb6, 0x4010e8bd, 0xe7be2001, 0xf20351d8, 0xf2035058, 0xf23d0122, 
+    0x0004052a, 0xf7ffb510, 0x2301fea8, 0x220048ff, 0xf00e4619, 0x48fefef0, 0x22042301, 0xf00e2110, 
+    0x4cfafeea, 0x22022301, 0x21041ca4, 0xf00e4620, 0x2301fee2, 0x22034620, 0xf00e2108, 0x4cf4fedc, 
+    0x22022301, 0x21041da4, 0xf00e4620, 0x2301fed4, 0x21024620, 0xf00e461a, 0x2301fece, 0x21402206, 
+    0xf00e1da0, 0x48eafec8, 0x22072301, 0x30122180, 0xfec1f00e, 0x23014ce5, 0x34082202, 0x46202104, 
+    0xfeb9f00e, 0x46202301, 0x21082203, 0xfeb3f00e, 0x48df2301, 0x03d9220f, 0x4010e8bd, 0xf00e3018, 
+    0x48dabeaa, 0x22002301, 0x1f004619, 0xf00eb510, 0x2100fea2, 0x4010e8bd, 0xf7ff2002, 0x48d3bed1, 
+    0x21012300, 0x1f00461a, 0xf00eb510, 0xe8bdfe94, 0xf7ff4010, 0xe92dbee2, 0x4dce5ff0, 0x080ff001, 
+    0x46142300, 0xf04f2202, 0x21040901, 0xf00e4628, 0x2301fe82, 0x22064628, 0xf00e2140, 0x2301fe7c, 
+    0x22074628, 0xf00e2180, 0x2300fe76, 0x22044628, 0xf00e2110, 0x2300fe70, 0x22054628, 0xf00e2120, 
+    0x2300fe6a, 0x22014628, 0xf00e2102, 0x2300fe64, 0x22034628, 0xf00e2108, 0x4fb7fe5e, 0x080af1a8, 
+    0xf8df4eb5, 0x3f18b2d4, 0xa2d0f8df, 0xf1b83e08, 0xd2760f05, 0xf008e8df, 0xf6f7f903, 0xf8df00f5, 
+    0x1c6082c0, 0x2300d011, 0x22064628, 0xf00e2140, 0xb3ecfe42, 0x28091e60, 0x48a7d854, 0x0148ea4f, 
+    0xf00e3810, 0x2130fe18, 0x48a3e056, 0x46414644, 0xf00e3810, 0x4621fe10, 0xf00e4658, 0x2300fe0c, 
+    0x22064628, 0xf00e2140, 0x2300fe26, 0x22074628, 0xf00e2180, 0x2301fe20, 0x21024628, 0xf00e461a, 
+    0x4894fe1a, 0x1c802118, 0xfdfbf00e, 0x21184891, 0xf00e3008, 0x2300fdf6, 0x21022201, 0xf00e4628, 
+    0x2301fe0a, 0x461a2102, 0xf00e4628, 0xe1b0fe04, 0x2301e7ff, 0x21024638, 0xf00e461a, 0x2301fde5, 
+    0x21024630, 0xf00e461a, 0x2300fddf, 0x22014638, 0xf00e2102, 0x2300fdd9, 0x22014630, 0xf00e2102, 
+    0xe185fdd3, 0x000bf1a4, 0xd80b2859, 0x497d487a, 0xf00e3810, 0x212cfdc0, 0x1c804876, 0xfdc1f00e, 
+    0xe183e187, 0x0065f1a4, 0x7fc8f5b0, 0x4872d206, 0x38104975, 0xfdaff00e, 0xe7ed2128, 0x10f5f2a4, 
+    0x7ffaf5b0, 0x486cd206, 0x38104970, 0xfda3f00e, 0xe7e12124, 0x30e9f2a4, 0x6f7af5b0, 0x4866d206, 
+    0x3810496b, 0xfd97f00e, 0xe7d52120, 0x5098f5a4, 0x3187f241, 0x42883889, 0x485fd806, 0x38104965, 
+    0xfd89f00e, 0xe7c7211c, 0x501cf5a4, 0x413ff649, 0x42883811, 0x4858d806, 0x38104641, 0xfd7bf00e, 
+    0xe7b92118, 0x4043f5a4, 0x314ff24c, 0x42883851, 0x4851d806, 0x38104958, 0xfd6df00e, 0xe7ab2114, 
+    0xf5a44956, 0x38a130c3, 0xd8064288, 0x4954484a, 0xf00e3810, 0x2110fd60, 0x4852e79e, 0x44204952, 
+    0xd8064288, 0x49514844, 0xf00e3810, 0x210cfd54, 0x484fe792, 0x4420494f, 0xd8064288, 0x4651483e, 
+    0xf00e3810, 0x2108fd48, 0x484be786, 0x4420494b, 0xd8854288, 0x494a4838, 0xf00e3810, 0x2104fd3c, 
+    0xe050e77a, 0xe01ee041, 0x4833e7ff, 0x46514654, 0xf00e3810, 0x4621fd30, 0xf00e4658, 0x482dfd2c, 
+    0x1c802108, 0xfd2df00e, 0x2108482a, 0xf00e3008, 0x2300fd28, 0x22064628, 0xf00e2140, 0x2300fd3c, 
+    0x21802207, 0x2301e72a, 0x21024638, 0xf00e461a, 0x2301fd1b, 0x21024630, 0xf00e461a, 0x2300fd15, 
+    0x22014638, 0xf00e2102, 0x2300fd0f, 0x22014630, 0xf00e2102, 0x2300fd09, 0x22074628, 0xf00e2180, 
+    0x2301fd1a, 0x21202205, 0x2300e0b5, 0x22074628, 0xf00e2180, 0x4923fd10, 0xf00e4658, 0x480dfcec, 
+    0x30082102, 0x4820e72a, 0x0000f990, 0xd03d2803, 0xd03b2805, 0xd0392804, 0xd0702802, 0xf04f2801, 
+    0xd0780301, 0x21402206, 0x0000e6ee, 0xf20351de, 0xf203505e, 0xf23c80da, 0xf0008178, 0x0501bd00, 
+    0x0f053700, 0x1b898f80, 0x1908b100, 0x1687d280, 0x1406f400, 0x11861580, 0x0c845880, 0x00061a7f, 
+    0x0a037a00, 0xfff85edf, 0x0007a11f, 0x07829b80, 0xfff0bdbf, 0x003d08ff, 0xffb3b4bf, 0x004c4b3f, 
+    0x0280de80, 0x01406f40, 0x000401fc, 0x46382301, 0x461a2102, 0xfca8f00e, 0x46302301, 0x461a2102, 
+    0xfca2f00e, 0x48f749f6, 0xfc95f00e, 0x46282300, 0x21402206, 0xfcaff00e, 0x210548f3, 0xfc91f00e, 
+    0x210a48f1, 0xf00e1c80, 0x48effc8c, 0x1d002105, 0xfc87f00e, 0x46282301, 0x21042202, 0xfc9bf00e, 
+    0x46382300, 0x21022201, 0xfc7ef00e, 0x46302300, 0x21022201, 0xfc78f00e, 0xe000e03b, 0x49e0e00b, 
+    0xf00e48e0, 0x2300fc68, 0x22064628, 0xf00e2140, 0x2105fc82, 0x2201e6a0, 0x21024638, 0xfc64f00e, 
+    0x46302301, 0x461a2102, 0xfc5ef00e, 0x46382300, 0x21022201, 0xfc58f00e, 0x46302300, 0x21022201, 
+    0xfc52f00e, 0x46282300, 0x21402206, 0xfc63f00e, 0x22042301, 0x46282110, 0xfc5df00e, 0xe8bd4628, 
+    0x23015ff0, 0x21082203, 0xbc55f00e, 0x0f00f1b9, 0x2300d00d, 0x22034630, 0xf00e2108, 0x4630fc35, 
+    0x5ff0e8bd, 0x22032301, 0xf00e2108, 0xe8bdbc2d, 0x48be9ff0, 0x22042301, 0xb5102110, 0xfc3bf00e, 
+    0x20012100, 0xfc95f7ff, 0x780048b9, 0xd10d2802, 0x380a48b5, 0xfc12f00e, 0xd107280e, 0x220048b5, 
+    0xf990210e, 0xe8bd0000, 0xe5944010, 0xb570bd10, 0x28034db1, 0xd0044cad, 0xd0172805, 0xd0172804, 
+    0x2300e030, 0x22024628, 0xf00e210c, 0x2301fc14, 0x22074620, 0xf00e2180, 0x2300fc0e, 0x22044620, 
+    0xf00e2110, 0xf7fffc08, 0xe017fc81, 0xe0002302, 0x46282301, 0x210c2202, 0xfbfdf00e, 0x46202300, 
+    0x21802207, 0xfbf7f00e, 0x46202300, 0x21102204, 0xfbf1f00e, 0x20022100, 0xfc4bf7ff, 0x20022100, 
+    0xfca7f7ff, 0x20022100, 0xfc95f7ff, 0x78004890, 0xd10b2802, 0x380a488c, 0xfbc0f00e, 0x488db241, 
+    0xf9902200, 0xe8bd0000, 0xe5444070, 0xb510bd70, 0xfc23f7ff, 0xfc4af7ff, 0xfc71f7ff, 0xfc82f7ff, 
+    0xfca4f7ff, 0x23004c84, 0x461a2101, 0xf00e4620, 0x2300fbc2, 0x22024620, 0xf00e210c, 0x4c7bfbbc, 
+    0x22072300, 0x46202180, 0xfbb5f00e, 0x46202300, 0x21102204, 0xfbaff00e, 0x78004875, 0xd10f2802, 
+    0x23014c71, 0x1ea42206, 0x46202140, 0xfba3f00e, 0x46202301, 0xe8bd2207, 0x21804010, 0xbb9bf00e, 
+    0x496bbd10, 0xf991b510, 0xb1891000, 0xd0142901, 0xd1432902, 0x380a4864, 0xfb70f00e, 0xd13d280e, 
+    0x22004864, 0xf990210e, 0xe8bd0000, 0xe4f24010, 0x4010e8bd, 0xf7ff2000, 0x4c5cbb0d, 0x2801b300, 
+    0x2802d020, 0x2301d12a, 0x22044620, 0xf00e2110, 0x2301fb72, 0x22034620, 0xf00e2108, 0x4857fb6c, 
+    0xf244220e, 0xf00e0100, 0x4c53fb74, 0xd0132801, 0x22002300, 0x46202101, 0x4010e8bd, 0xbb5bf00e, 
+    0xe0002300, 0x46202301, 0x21102204, 0xfb53f00e, 0x22032300, 0xe7ee2108, 0xe7ea2301, 0xb570bd10, 
+    0xf9944c43, 0xb1100000, 0xd0042801, 0x2001e010, 0xfad0f7ff, 0x4d3de00c, 0x22042300, 0x46282110, 
+    0xfb39f00e, 0x46282300, 0x21082203, 0xfb33f00e, 0xfbe8f7ff, 0x48382300, 0x461a2101, 0xfb2bf00e, 
+    0x28027820, 0x4c30d10f, 0x22062301, 0x21401ea4, 0xf00e4620, 0x4620fb20, 0x4070e8bd, 0x22072301, 
+    0xf00e2180, 0xbd70bb18, 0x20022100, 0xf7ffb510, 0x4827fbc2, 0x28027800, 0x4823d10b, 0xf00e380a, 
+    0xb241faed, 0x22004823, 0x0000f990, 0x4010e8bd, 0xbd10e471, 0xf7ffb510, 0x481dfbb5, 0x28027800, 
+    0x4c19d10f, 0x22062301, 0x21401ea4, 0xf00e4620, 0x2301faf2, 0x22074620, 0x4010e8bd, 0xf00e2180, 
+    0xbd10baea, 0x20012100, 0xbb6cf7ff, 0xb5102200, 0xb1284614, 0x2b091e43, 0x2000d20a, 0xbd10700c, 
+    0x700c20ff, 0xfbb0bd10, 0x1c52f0f3, 0xe000b2d2, 0x280a230a, 0x2805d8f7, 0x2001d312, 0xe0107008, 
+    0x1e0a6e00, 0xf0008168, 0xf23c80dc, 0xf2035078, 0x0004052a, 0x00040242, 0xf20351da, 0xf38fffd4, 
+    0x4610700c, 0x0fc2bd10, 0x7fd1ebb2, 0xf1c1d203, 0x440831ff, 0x1a404770, 0x48184770, 0xf990b510, 
+    0x28030000, 0x2805d010, 0x2804d00e, 0x4814d00c, 0xfa84f00e, 0xd4050780, 0xf00e4812, 0xb2c0fa7f, 
+    0xd0002800, 0xbd102001, 0x22054c0f, 0x46202120, 0xfa9ff00e, 0xd0f52800, 0x46202204, 0xf00e2110, 
+    0x2801fa98, 0x4809d0ee, 0xfa68f00e, 0xd1e92800, 0x1c804806, 0xfa62f00e, 0x0000e7e2, 0x000401fc, 
+    0xf3cfffc2, 0xf3cf2002, 0xf203502c, 0xf23c80e8, 0x4604b570, 0x680048f7, 0x0050f8b0, 0x104030a6, 
+    0xea400400, 0xf0400044, 0x48f30138, 0xfa43f00e, 0x210048f1, 0xf00e3084, 0x48f0fa3e, 0xea404dee, 
+    0x357c3184, 0xf00e4628, 0x48edfa36, 0x20107801, 0xfa28f7ed, 0xea4048eb, 0x46283184, 0xfa2bf00e, 
+    0xbd702001, 0x210048e4, 0xf00eb510, 0xe8bdfa24, 0xf0014010, 0xb510bbd4, 0x4604b086, 0xfa1cf001, 
+    0xd0222800, 0x308048dc, 0xfa12f00e, 0x010bf3c0, 0xda022953, 0x31adf601, 0x3953e000, 0x0c810508, 
+    0x1d0048d5, 0xfa07f00e, 0x4ad32101, 0x90002000, 0x4623323c, 0x0102e9cd, 0x91059104, 0x5130f240, 
+    0x20019001, 0xf9fcf7ec, 0xb0062001, 0xe92dbd10, 0x000741f0, 0xf8df48cc, 0x68058334, 0xf998d103, 
+    0xf7ff0000, 0xf505ff95, 0xf5057626, 0x463074a6, 0xffc1f7ff, 0xffb6f7ff, 0x46202200, 0x68334629, 
+    0xc0081c52, 0xb2126873, 0x2a533610, 0xdbf6c108, 0xd1032f01, 0x0000f998, 0xff7af7ff, 0x22012100, 
+    0xf8344608, 0xb10b3b02, 0xb2894311, 0x00521c40, 0xb212b200, 0xdbf42810, 0xf8df2200, 0xf8dfe2d4, 
+    0x3520c2d4, 0x20004690, 0x8002f80c, 0x030ff001, 0x1603f3c1, 0x0383eb0e, 0x0686eb0e, 0x30c0f8d3, 
+    0x6080f8d6, 0xf3c14433, 0xeb0e2603, 0x6c360686, 0x0b0e4433, 0x6026f85e, 0xf9354433, 0xeb036b02, 
+    0x429e03c3, 0x2301da01, 0x2300e000, 0x6002f81c, 0x7b02f814, 0x4087405f, 0x433e0849, 0xb2001c40, 
+    0x31c3ea41, 0x2808b289, 0x6002f80c, 0x4b9adbce, 0x1c52549e, 0x2a10b212, 0xe8bddbc5, 0xb5f081f0, 
+    0x4607b085, 0x2500488b, 0x21014e90, 0x462c9500, 0x6800462a, 0x304ef9b0, 0x0000f996, 0xfa9af001, 
+    0x21802001, 0xe9cd2305, 0x90004001, 0xe9cd4618, 0xf9961403, 0x21072000, 0xfa4df001, 0xf95cf001, 
+    0xf001b118, 0x0005f977, 0xb17fd110, 0x6480f04f, 0x11f4f240, 0xf7e64620, 0xf246f944, 0x46206166, 
+    0xf92ef7e6, 0x4620497d, 0xf92af7e6, 0xfaf7f001, 0x24004e78, 0xf0014620, 0xf846f964, 0x1c640024, 
+    0x2c04b264, 0xb005dbf6, 0xbdf04628, 0x4ff3e92d, 0xb08b486d, 0x4c724689, 0xf640af04, 0x68000200, 
+    0xf5009007, 0x91095180, 0x88244962, 0xf8b16809, 0x1ae3305e, 0x005b2410, 0xfc83fa0f, 0x93082300, 
+    0x461e1e5d, 0x1028e887, 0x46989f0b, 0x104cf8b1, 0x6700f507, 0xeba74b5d, 0xeba7070c, 0x39100141, 
+    0xf9932702, 0xea4f3000, 0xeb017ce1, 0xf36f4c9c, 0xeba10c0d, 0xf04f010c, 0xb2090c05, 0x1702e9cd, 
+    0x2c00e9cd, 0x46612207, 0xfab0f001, 0x22004855, 0x46934613, 0x0000f990, 0x900a9202, 0x494d4610, 
+    0x540f2700, 0xb2001c40, 0xdbf82810, 0xeb094261, 0x30200004, 0xe12b9003, 0x44089806, 0x98091907, 
+    0x7017f830, 0x30fff04f, 0x0047eb00, 0xfa0f9f07, 0x980afa80, 0x44204408, 0xc010f837, 0x0040eb07, 
+    0x0c02f830, 0x0000ebac, 0xfa0f00c0, 0x2001f980, 0xea4f4f37, 0xeb070c80, 0xfa231780, 0xfa22fe0c, 
+    0xf00efc0c, 0xf00c0e0f, 0x1c400c0f, 0xe02ef837, 0xf837b200, 0x2803702c, 0x0c07ebae, 0x0709eb0c, 
+    0xf987fa0f, 0xf8dfdbe4, 0xf003e0a8, 0xf002070f, 0xf8cd0c0f, 0xf83e9000, 0xf83e7027, 0xf00b002c, 
+    0x1a3f0c0f, 0x0009eb07, 0xf980fa0f, 0xf0009802, 0xf83e070f, 0xf83e002c, 0x1a3f7027, 0x45469800, 
+    0xb2004438, 0xd9049000, 0x0008eba6, 0x0e00f04f, 0x2000e002, 0x0e06eba8, 0x88374e1b, 0xf60afb17, 
+    0x9701b237, 0x0707eba9, 0x0609fb19, 0x0807fb07, 0x0700e9dd, 0x1bc04691, 0xfb009f00, 0xfb17e000, 
+    0x9f02ec07, 0x4566469e, 0xea4fd220, 0xea4f034e, 0xe01f0249, 0x00040598, 0xf1000404, 0x000c04e5, 
+    0x00040243, 0x000c14e5, 0x000401dc, 0x00040518, 0x000412d8, 0x000413d8, 0x000413f8, 0xdcba01f5, 
+    0x00040506, 0x0004050e, 0x00040510, 0x4666007b, 0x024bea4f, 0xd2114540, 0x0f01f1ba, 0x46504680, 
+    0x2000d000, 0x3ffff1ba, 0x0047ea40, 0xd0039002, 0xea402000, 0xe00f004b, 0xe7fa2001, 0x0f01f1ba, 
+    0xd0004650, 0xf1ba2000, 0xea403fff, 0x9002004e, 0x2000d00a, 0x0049ea40, 0x46834546, 0xfa23d20e, 
+    0x07c0f004, 0xe001d105, 0xe7f32001, 0xf004fa22, 0x2001e00a, 0xf04fe00a, 0xe00730ff, 0x40e09802, 
+    0xd1f607c0, 0xf004fa2b, 0xd1f407c0, 0xda002800, 0x9f0b4240, 0x1b3f440f, 0x7ce7ea4f, 0x6c1ceb07, 
+    0x0cfff02c, 0x0e0ceba7, 0xc020f8dd, 0xd10145e6, 0x2000b178, 0xdb3842a1, 0xc010f8dd, 0x0c5cea4f, 
+    0x2001b100, 0x70c0ea4c, 0x98059004, 0xd0021c40, 0x2001e01b, 0x9804e7ee, 0x4c27f5a0, 0x0cbbf1bc, 
+    0xf643d113, 0x443870e1, 0x17c527bb, 0x4595eb00, 0x050df36f, 0xb2001b40, 0x48f69005, 0x7007251f, 
+    0x704727a7, 0x70872700, 0x1c6870c7, 0x2d80d00d, 0x48f1da09, 0x28074028, 0x9804d105, 0x48ed0e07, 
+    0x00e5eb00, 0x1c6d7007, 0x9803b22d, 0xb2091c49, 0xdd024288, 0xf6ff2d80, 0x9805aecf, 0xe8bdb00d, 
+    0xe92d8ff0, 0xf8df4ff8, 0x2200a39c, 0xf04f4fe3, 0x4de334ff, 0x6680f507, 0xf8da463b, 0x88000000, 
+    0x0950ea4f, 0x90002000, 0xf99048df, 0x20011000, 0xfcacf7eb, 0x1000f8da, 0xf9b74bdc, 0xf8910000, 
+    0x78192068, 0x44111fc9, 0x80304108, 0xe0212001, 0x0240eb07, 0x1010f937, 0x2c02f932, 0xf8da1a89, 
+    0xf8922000, 0x781ac068, 0x44621fd2, 0xb2094111, 0xf8261c62, 0xd0051010, 0x460a2900, 0x4252da00, 
+    0xdd054542, 0x46042900, 0x4249da00, 0xf881fa0f, 0xb2001c40, 0xdbdb4548, 0xda002c03, 0xea4f2403, 
+    0xeb0601e8, 0xf9320244, 0x28000c06, 0x4240da00, 0xdd014288, 0xe0101ee4, 0x0c04f932, 0xda002800, 
+    0x42884240, 0x1ea4dd01, 0xf932e007, 0x28000c02, 0x4240da00, 0xdd004288, 0x20001e64, 0x18c1b263, 
+    0x1011f836, 0x1010f825, 0xb2001c40, 0xdbf62811, 0x22004eaf, 0x00c2eb05, 0x1008f9b0, 0x4006f9b0, 
+    0x7002f9b0, 0xf9b04421, 0x443c4004, 0xeb014421, 0xeb0604c1, 0x600c1182, 0x4008f9b0, 0x7006f9b0, 
+    0xf9b0443c, 0x443c7004, 0x7002f9b0, 0xeb041be4, 0x604c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 
+    0x1be47004, 0x7002f9b0, 0xeb04443c, 0x608c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1be47004, 
+    0x7002f9b0, 0xeb041be4, 0x60cc04c4, 0x4008f9b0, 0x7006f9b0, 0xc002f9b0, 0xf9b01be4, 0x44677004, 
+    0xeb04443c, 0x610c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x443c7004, 0x7002f9b0, 0xeb041be4, 
+    0x614c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb04443c, 0x618c04c4, 
+    0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb041be4, 0x61cc04c4, 0x4006f9b0, 
+    0xf9b01c52, 0xb2127008, 0xc002f9b0, 0xf9b01be4, 0x44677004, 0xeb04443c, 0x620c04c4, 0x4006f9b0, 
+    0x7008f9b0, 0xf9b01be4, 0x443c7004, 0x7002f9b0, 0xeb041be4, 0x624c04c4, 0x4006f9b0, 0x7008f9b0, 
+    0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb04443c, 0x628c04c4, 0x4006f9b0, 0x7008f9b0, 0xf9b01be4, 
+    0x1be47004, 0x7002f9b0, 0xeb041be4, 0x62cc04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1b3c7004, 
+    0x7002f9b0, 0xeb04443c, 0x630c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1b3c7004, 0x7002f9b0, 
+    0xeb041be4, 0x634c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x443c7004, 0x7002f9b0, 0xeb041b3c, 
+    0x638c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0xf9b07004, 0x44380002, 0x42404420, 0xeb002a04, 
+    0x63c800c0, 0xaf16f6ff, 0x493a8828, 0x00c0eb00, 0x80080040, 0x70034838, 0x8ff8e8bd, 0xf7ffb510, 
+    0x2002fe90, 0xfde6f7ec, 0xf2404604, 0xf6431100, 0xf7ff7060, 0x2002fcfb, 0xfddcf7ec, 0x1a20492f, 
+    0x1000f9b1, 0xf0f1fbb0, 0x6008492d, 0xe92dbd10, 0xf24041f0, 0xf7ff2500, 0x2400fe74, 0x36fff04f, 
+    0x6700f643, 0x0800f248, 0x4629e02e, 0xf7ff4638, 0x1c41fcdd, 0xf5a0d01e, 0xb200507e, 0x6480f04f, 
+    0xeb000fc1, 0xf2403081, 0xb20611f4, 0xf7e54620, 0x491cfdf8, 0xf7e54620, 0x491bfde3, 0xf7e54620, 
+    0x4631fddf, 0xf7e54620, 0x4918fddb, 0xf7e54620, 0xe00dfdd7, 0x1c641979, 0xb22417c8, 0x4090eb01, 
+    0x000df36f, 0xb2071a08, 0xf0f5fb98, 0xdccc42a0, 0xe4624630, 0x000413d8, 0x80000007, 0x00043908, 
+    0x00044308, 0x00040598, 0x00040518, 0x00040322, 0x000412d8, 0x00040510, 0x0004050e, 0x00040588, 
+    0x00040514, 0xa5a55a5a, 0xdde50000, 0xdcba01f5, 0x5c0849fe, 0xe92d4770, 0x4cfd47f0, 0xf248b283, 
+    0x26000700, 0x25074639, 0x220f4620, 0xfdd3f00d, 0xf2402380, 0x220031ff, 0xf00d4620, 0x2306fdcc, 
+    0x21ff2200, 0xf00d1ca0, 0x48f2fdc6, 0x217f2200, 0xf8b06800, 0x1d20304a, 0xfdbdf00d, 0x0802f1a4, 
+    0x46444639, 0xf00d4640, 0xf248fd9c, 0x46200180, 0xfd97f00d, 0xa398f8df, 0xf8df2400, 0xf10a939c, 
+    0xf04f0a0e, 0xf04f0204, 0xf89901f0, 0x28030000, 0xd0054650, 0xfdadf00d, 0x070043c0, 0xe004d01b, 
+    0xfda7f00d, 0x0000ea35, 0x1c64d013, 0xdbe842bc, 0x46442301, 0x4640220a, 0x4629029d, 0xfd8bf00d, 
+    0x46292300, 0x4620220a, 0xfd85f00d, 0xe8bd4630, 0x260187f0, 0x2200e7ec, 0x210f4650, 0xfd89f00d, 
+    0xf00049ce, 0x700a0201, 0x0240f3c0, 0xf3c0704a, 0x708a0280, 0x00c0f3c0, 0xe7ea70c8, 0x220048c4, 
+    0x41f0e92d, 0xf6433030, 0xf00d71ff, 0xb204fd72, 0x07e04dc3, 0x2301d00e, 0x22094628, 0x4631025e, 
+    0xfd59f00d, 0x46312300, 0x46282209, 0xfd53f00d, 0xb2241e64, 0xf2404fb7, 0x68381600, 0x006af8b0, 
+    0xfa0f1a20, 0x2400f880, 0x2301e00c, 0x22084631, 0xf00d4628, 0x2300fd40, 0x22084631, 0xf00d4628, 
+    0x1c64fd3a, 0x7a016838, 0x44117a42, 0xf8b07a82, 0xeb02006a, 0x44080050, 0x0f40ebb4, 0x6838dbe5, 
+    0xeba87a01, 0x49a70041, 0xf3c03062, 0x7809004c, 0xfe7bf7ed, 0xe8bd4640, 0xe92d81f0, 0x468943f0, 
+    0xb11ab143, 0xf1a44ca0, 0xe00d0584, 0xf1a44c9f, 0xe0090584, 0x4c9cb122, 0xf1a43ca8, 0xe0030584, 
+    0x34a84c99, 0x0584f1a4, 0xe004f890, 0xb9026807, 0xf04f2201, 0xe01f0c00, 0x46192300, 0xfa274618, 
+    0x07f6f600, 0xf1c0d007, 0xf8140820, 0x40736008, 0x6028f855, 0x1c404071, 0x2820b200, 0xea5fdbef, 
+    0xd00370ce, 0x40437820, 0x40416828, 0xf10c469e, 0x460f0c01, 0xfc8cfa0f, 0xdbdd4594, 0x7e00e9c9, 
+    0x83f0e8bd, 0x47fce92d, 0x48814682, 0x9204f8df, 0xf8df2501, 0x460f81ec, 0x7001464a, 0x464002a9, 
+    0xfd94f00d, 0x487c4606, 0x0000f990, 0xd0172803, 0xd0222802, 0xd02d2801, 0x3012486d, 0xfc9ef00d, 
+    0x486b9001, 0xf00d3014, 0x9000fc99, 0x30164868, 0xfc94f00d, 0x24009900, 0x4001ea40, 0xe02c9000, 
+    0x30244863, 0xfc8af00d, 0x48619001, 0xf00d3026, 0x9000fc85, 0x3028485e, 0x485de7ea, 0xf00d301e, 
+    0x9001fc7d, 0x3020485a, 0xfc78f00d, 0x48589000, 0xe7dd3022, 0x30184856, 0xfc70f00d, 0x48549001, 
+    0xf00d301a, 0x9000fc6b, 0x301c4851, 0x4669e7d0, 0x46082200, 0xff61f7ff, 0x46531c64, 0xdbf642bc, 
+    0x462a4669, 0xf7ff4608, 0x9800ff58, 0x4848b281, 0xf00d300a, 0x9800fc56, 0x48450c01, 0xf00d3008, 
+    0x9801fc50, 0x4842b281, 0xf00d1d80, 0xf246fc4a, 0x46440700, 0x46392300, 0x4640220d, 0xfc5bf00d, 
+    0xf2404846, 0xf9903120, 0x28040000, 0x2805d01e, 0xf44fd01f, 0x464b107a, 0x43452210, 0xf0f1fb95, 
+    0x1a304621, 0xf00d3020, 0x2300fd21, 0x220d4639, 0xf00d4620, 0x4833fc40, 0x78032201, 0xf9b04838, 
+    0x20001000, 0xfe4bf7ed, 0x87fce8bd, 0x007af44f, 0xf44fe7e1, 0xe7de00fa, 0xb2834a2f, 0x4d24b570, 
+    0xf24821ff, 0x70110400, 0x4621220f, 0xf00d4628, 0x2380fc22, 0x31fff240, 0x46282200, 0xfc1bf00d, 
+    0x22002306, 0x1ca821ff, 0xfc15f00d, 0x22004819, 0x6800217f, 0x304af8b0, 0xf00d1d28, 0x4621fc0c, 
+    0x23011eac, 0x220f4620, 0xfc05f00d, 0x46202300, 0x21402206, 0xfbfff00d, 0x46202300, 0x21202205, 
+    0xfbf9f00d, 0x46202300, 0x21102204, 0xfbf3f00d, 0x46202300, 0x461a210f, 0xfbedf00d, 0x46202300, 
+    0x21802207, 0xfbe7f00d, 0xe01b2301, 0x00040518, 0xf2035094, 0x00040598, 0x00040234, 0x0004051c, 
+    0xf2035092, 0x00040243, 0x00040a08, 0x00040b58, 0x0004022f, 0xf000810c, 0x0004022e, 0x00040242, 
+    0x00040506, 0xe8bd4620, 0x22074070, 0xf00d2180, 0xe92dbbc2, 0x4ffb41f0, 0x46062400, 0x0500f248, 
+    0x46382204, 0xf00d21f0, 0xb240fbc4, 0x1c64b910, 0xdbf542ac, 0x46382204, 0xf00d21f0, 0xb204fbba, 
+    0x072148f1, 0x2103d501, 0x0761e00c, 0x2102d501, 0x07a1e008, 0x2101d501, 0x07e1e004, 0x2100d001, 
+    0x21ffe000, 0xb2487001, 0xd0041c41, 0x5c0949e7, 0xf7ff4630, 0xb260feb7, 0xb510e66d, 0xf7ff4604, 
+    0x4620ff5b, 0x4010e8bd, 0xb510e7c3, 0x21004ce0, 0xf99448de, 0x54812000, 0x2001f994, 0x54812101, 
+    0x2002f994, 0x54812102, 0x2003f994, 0x54812103, 0x3003f990, 0x2002f990, 0x1001f990, 0x0000f990, 
+    0xfa2af7ee, 0x3003f994, 0x2002f994, 0x1001f994, 0x0000f994, 0x4010e8bd, 0xb9fcf7f1, 0xa902b57f, 
+    0xf7ef4668, 0x48cbf8e9, 0x7800466b, 0xd1102803, 0xf99048c9, 0xf9901000, 0xf8332002, 0xf8231011, 
+    0xf9901012, 0xf9901001, 0xf8330003, 0xf8231011, 0x21001010, 0xf8334608, 0x1c402010, 0x4411b200, 
+    0x2804b209, 0x1c89dbf7, 0x49bc1088, 0xf8b5680d, 0x1a40106e, 0x1000f9bd, 0xf020b200, 0x20010401, 
+    0x2010f933, 0xdd00428a, 0x1c404611, 0x2804b200, 0xf8b5dbf6, 0x1c492042, 0x0070f8b5, 0x0101f021, 
+    0x0342eb00, 0x88104aae, 0xeb014245, 0x44190145, 0x1b61b20d, 0x0061eba0, 0x48aab201, 0x22018011, 
+    0x46287803, 0xfd1bf7ed, 0x4628b004, 0xe92dbd70, 0xb0894ff0, 0x9294f8df, 0x4d9c2000, 0xa284f8df, 
+    0x0804f10d, 0x48a09006, 0x0000f990, 0x489b9005, 0x88006800, 0x20000846, 0x46049007, 0xa801a903, 
+    0xf87af7ef, 0xf8904893, 0xf1bee000, 0xd1100f03, 0xf9904891, 0xf9902000, 0xf8383002, 0xf8282012, 
+    0xf9902013, 0xf9902001, 0xf8380003, 0xf8282012, 0xf8992010, 0x2000c000, 0x466f4683, 0x562aa903, 
+    0x0f01f1bc, 0xb002f807, 0x3010f931, 0x2140d008, 0xdd0a428b, 0x1010f938, 0xda0442b1, 0xe0032101, 
+    0x1100f240, 0x2102e7f4, 0x1c4054b9, 0x2804b2c0, 0x487fd3e4, 0x28037800, 0x2001d102, 0x0003f88d, 
+    0x0f03f1be, 0xf89dd107, 0xf88d0000, 0xf89d0002, 0xf88d0001, 0xf2420003, 0x06c80170, 0xfa7df7e5, 
+    0x0b00f44f, 0x11f4f240, 0xf7e54658, 0x4971fa6a, 0xf7e54658, 0x4f66fa55, 0x1003f997, 0x0000f997, 
+    0x2001f997, 0x3001eb00, 0x1002f997, 0xeb010209, 0x44011102, 0xf7e54658, 0x4867fa43, 0xfa5ef00d, 
+    0x46584601, 0xfa3cf7e5, 0xf00d4864, 0x4601fa51, 0xf7e54658, 0xf89dfa35, 0xf89d1003, 0xf89d0000, 
+    0xeb002001, 0xf89d3001, 0x02091002, 0x1102eb01, 0x46584401, 0xfa24f7e5, 0x0000f89d, 0x1001f89d, 
+    0x2900b158, 0x1002f89d, 0xb301d001, 0x2900e022, 0x1003f89d, 0xb139d015, 0xb151e01c, 0x1002f89d, 
+    0xf89db9d1, 0xb1680003, 0x78797838, 0x70787039, 0xf89de022, 0x28000002, 0x0003f89d, 0xb908d01b, 
+    0xb939e01a, 0x78797838, 0x70787039, 0xf89de02a, 0xb1891003, 0xd0142802, 0x1001f89d, 0xd0102902, 
+    0x2002f89d, 0xd00c2a02, 0x3003f89d, 0xd0082b02, 0xd1172801, 0xb1a8e010, 0x78f978b8, 0x70f870b9, 
+    0x482fe010, 0xf89a2201, 0xf9b03000, 0xf06f1000, 0xf7ed000f, 0xe005fc24, 0xd1032901, 0xd1012a01, 
+    0xd0132b01, 0x4658492e, 0xf9caf7e5, 0xfe7df7ff, 0x0000f899, 0x481c2801, 0x0000f990, 0xd0035c29, 
+    0x78004828, 0xd0072801, 0xe0062001, 0xf44f4924, 0xf7e50000, 0xe010f9b5, 0xf7ff2000, 0xf89afd13, 
+    0xf44f1000, 0xf7ec2080, 0x1c64f9bd, 0x2c03b224, 0xaef4f6ff, 0x28009807, 0xf7ffd07e, 0x2000fe7f, 
+    0xfe02f7ec, 0x78284d17, 0xd02d2801, 0xf9aff7ed, 0x0670f242, 0x06f74631, 0xf7e54638, 0x7828f9ae, 
+    0xe037b328, 0xf20350a2, 0x0004022e, 0x00040524, 0x00040518, 0x0004057b, 0x00040520, 0x00040598, 
+    0x00040506, 0x00040243, 0x00040248, 0x000402a4, 0x00040234, 0x77777776, 0xf2030446, 0xf100000c, 
+    0xdcba01f5, 0x00040502, 0xf935f7ed, 0x2100e7d0, 0xf7ee2001, 0x4c54fc4a, 0x200c2100, 0x2000f994, 
+    0xf9f2f7ee, 0xf9942101, 0x46082000, 0xfa32f7ee, 0xfad0f7f1, 0x463146b1, 0xf7e54638, 0xf7fff96e, 
+    0xb204fb46, 0xd0271c60, 0x90062001, 0xf7ec2000, 0x07e0fdab, 0x4845d00a, 0xf89a2201, 0xf9b03000, 
+    0x46101000, 0xfb8bf7ed, 0xb2241c64, 0x1000f89a, 0x46541060, 0xfac9f7ed, 0x22017823, 0x20004c3b, 
+    0x1000f9b4, 0xfb7bf7ed, 0xa801a903, 0xfef4f7ee, 0x78004837, 0xe0002803, 0xd110e061, 0xf9904835, 
+    0xf9902000, 0xf8383002, 0xf8282012, 0xf9902013, 0xf9902001, 0xf8380003, 0xf8282012, 0xf9bd2010, 
+    0x20011004, 0xf9334643, 0x428a2010, 0x4611da00, 0xb2c01c40, 0xd3f62804, 0x39084e27, 0x6831b208, 
+    0x798b794a, 0x790b441a, 0x0060eb03, 0x44108823, 0x441a8f4a, 0xf8911a10, 0xb2002038, 0xf7ed2100, 
+    0x6830fab0, 0x0040f9b0, 0xfb0ef7ee, 0x1000f89a, 0x0000f640, 0xf8f6f7ec, 0x28017828, 0x4812d016, 
+    0x0000f990, 0x1cc09005, 0xeb0017c1, 0xf0217191, 0x1a400103, 0xf7f1b240, 0xf7edfbcd, 0x4649f8e8, 
+    0xf7e54638, 0x7828f8ea, 0xe005b118, 0xf860f7ed, 0x9805e7f5, 0xfbbef7f1, 0xf7ec2001, 0x9806fd25, 
+    0xe8bdb009, 0x00008ff0, 0x00040248, 0x00040506, 0x0004057b, 0x00040520, 0x00040598, 0x2a05b570, 
+    0xd0019e04, 0xd10b2a04, 0xd0072b01, 0xd0052b02, 0x4b4b4a4a, 0x781b7812, 0xd101431a, 0xb2401c80, 
+    0x2101b119, 0x0040eb01, 0x0040e000, 0x280cb240, 0x2400da03, 0x050cf1c0, 0xf1a0e014, 0x290c010c, 
+    0x2401d203, 0x0518f1c0, 0xf1a0e00c, 0x290c0118, 0x2402d203, 0x0524f1c0, 0x2824e004, 0x2403db02, 
+    0x0530f1c0, 0x0200f04f, 0xf04fb2a3, 0x2e010103, 0x4834d040, 0xf8aff00d, 0xb2a34832, 0x21032200, 
+    0xf00d1c80, 0x482ff8a8, 0x2200b2a3, 0x1d002103, 0xf8a1f00d, 0xb2a3482b, 0x21032200, 0xf00d1d80, 
+    0x4828f89a, 0x2200b2ab, 0x302e210f, 0xf893f00d, 0xb2a34e25, 0x210c2202, 0xf00d4630, 0xb2a3f88c, 
+    0x22004630, 0xf00d2103, 0x1cb6f886, 0x4630b2a3, 0x210c2202, 0xf87ff00d, 0x4630b2a3, 0x21032200, 
+    0xf879f00d, 0x210f2200, 0x1cb0b2ab, 0x4070e8bd, 0xb871f00d, 0x30084813, 0xf86df00d, 0xb2a34811, 
+    0x21032200, 0xf00d300a, 0x480ef866, 0x2200b2a3, 0x300c2103, 0xf85ff00d, 0xb2a3480a, 0x21032200, 
+    0xf00d300e, 0x4807f858, 0x2200b2ab, 0x3030210f, 0xf851f00d, 0x4070e8bd, 0xb9a0f7ed, 0x0004057b, 
+    0x000404f6, 0xf2034200, 0xf203900e, 0x4d11b570, 0x0303f000, 0x4604220e, 0x0100f24c, 0xf00d4628, 
+    0x2200f83a, 0x1ca82107, 0x0382f3c4, 0xf833f00d, 0x46282301, 0x21202205, 0xf82df00d, 0x20402100, 
+    0xf800f7ec, 0xe8bd4628, 0x23004070, 0x21202205, 0xb821f00d, 0xf203f042, 0x4cfeb510, 0xf7ebe002, 
+    0xb160ffaf, 0xf00c4620, 0x0300fff3, 0x0002f04f, 0xf7ebd4f5, 0x49f8ff9f, 0x20016008, 0x4cf7bd10, 
+    0xf00c4620, 0xf040ffeb, 0x46200110, 0xffe9f00c, 0xbd102000, 0xb51048ef, 0xf00c1d00, 0x0fc0ffd9, 
+    0x49ecbd10, 0x0003f1c0, 0xeb01310c, 0xf00c0080, 0xe92dbfcf, 0xf8df41f0, 0x108d839c, 0x4604b086, 
+    0x0840f1a8, 0x2b01b133, 0x2b02d014, 0x2b03d06e, 0xe0a8d06f, 0x90052000, 0x90042201, 0x46239000, 
+    0xe9cd9001, 0x00880202, 0xb2014642, 0xf7ea2001, 0xe098ffb7, 0xf04f2a07, 0xd0540600, 0x0745eb05, 
+    0x4640e019, 0xffa4f00c, 0x0026f844, 0xf00c4640, 0x1971ff9f, 0x0021f844, 0xf00c4640, 0xeb06ff99, 
+    0xf8440145, 0x46400021, 0xff92f00c, 0x1c7619b9, 0xf844b236, 0x42ae0021, 0xe074dbe3, 0x46404647, 
+    0xff86f00c, 0x0202f000, 0x0101f000, 0x31c2ea41, 0x1026f844, 0x0108f000, 0x0280f3c0, 0x3141ea42, 
+    0xf8441972, 0xf0001022, 0xf3c00120, 0xea421200, 0xeb0621c1, 0xf8440245, 0xf0001022, 0xf3c00180, 
+    0xea401080, 0xeb052041, 0x44310145, 0x0021f844, 0xf00c4638, 0x4638ff5d, 0xff5af00c, 0xf00c4638, 
+    0x1c76ff57, 0x42aeb236, 0xe03cdbc8, 0x46472600, 0xe015e013, 0xf00c4638, 0x1971ff4b, 0x0021f844, 
+    0xf00c4638, 0xf844ff45, 0x46380026, 0xff40f00c, 0xf00c4638, 0x1c76ff3d, 0x42aeb236, 0xe022dbea, 
+    0x463e2700, 0x4640e01d, 0xff32f00c, 0x0027f844, 0x46401c7f, 0xf00cb23f, 0xf844ff2b, 0x1c7f0027, 
+    0xb23f4640, 0xff24f00c, 0x0027f844, 0x46401c7f, 0xf00cb23f, 0xf844ff1d, 0x1c7f0027, 0xb23f1c76, 
+    0x42aeb236, 0xb006dbdf, 0x2100488a, 0xe8bd387c, 0xf00c41f0, 0xe92dbf10, 0x27005ff0, 0x2b0b4698, 
+    0xe9dd4692, 0xf8dd6b0d, 0x460c902c, 0xd1044605, 0x46494880, 0xf00c301c, 0x1c60fefe, 0x2c07d007, 
+    0x2d05d106, 0x2d06d001, 0x2701d102, 0x2400e000, 0xdd022e00, 0x1e401070, 0x4876b206, 0x30084631, 
+    0xfee9f00c, 0xea4f980c, 0xea41718b, 0xea417109, 0x980a5100, 0x40c0ea41, 0x4187ea40, 0x318aea41, 
+    0x2088ea41, 0x1144ea40, 0x4329486a, 0x5ff0e8bd, 0xbed1f00c, 0x460db570, 0x9c041059, 0xea410409, 
+    0xea411142, 0xea4101c5, 0xf0400040, 0x48610110, 0xf00c387c, 0x2c00fec0, 0x485ed006, 0xe8bd4621, 
+    0x38784070, 0xbeb7f00c, 0xb570bd70, 0x48594606, 0x460d4614, 0xf6402200, 0x1d0071ff, 0xfec2f00c, 
+    0xb925b12e, 0x0064ebb0, 0xf500d501, 0xf6436040, 0xe8bd71ff, 0x00834070, 0x2200484e, 0xf00c3878, 
+    0xb5f0bea3, 0x56614c4e, 0x29013c10, 0x2910d011, 0x2501da0f, 0x408d1e49, 0xf04f6065, 0x408d35ff, 
+    0x6021b2a9, 0x040989a1, 0x892160e1, 0x60a10409, 0x2100e001, 0x68676061, 0x2f00b132, 0x6826d01c, 
+    0xe9d42100, 0xe0264502, 0xd0152f00, 0x21006826, 0x4502e9d4, 0xf850e00d, 0x423a2021, 0x4332d002, 
+    0x2021f840, 0xd002422a, 0xf8404322, 0x1c492021, 0xebb1b209, 0xdbee0f43, 0xf850bdf0, 0x423a2021, 
+    0x4332d002, 0x2021f840, 0xd002422a, 0xf8404322, 0x1d092021, 0xebb1b209, 0xdbee0f43, 0x4825bdf0, 
+    0x22032301, 0x30482108, 0xbe4ef00c, 0x4fffe92d, 0xf04fb081, 0x46980900, 0x460d4614, 0x0a01f04f, 
+    0x464f9e0e, 0xb00fe9dd, 0x7f80f5b6, 0x9000f8cd, 0x4430dc01, 0xf1bbb200, 0xd0050f05, 0x1c612000, 
+    0x2c07d00e, 0xe00cd006, 0xf04f1040, 0xf04f0901, 0xe7f40a00, 0xd0012d05, 0xd1022d06, 0xe0072701, 
+    0x490f2400, 0x5d49310b, 0xd1012901, 0x0800f04f, 0xea410401, 0xea411149, 0xf0400048, 0x48050118, 
+    0xf00c387c, 0x4803fe08, 0x30089900, 0xfe03f00c, 0xe00704b9, 0xf1000480, 0x00040230, 0xf203517e, 
+    0x00040b8c, 0x3088ea41, 0x1144ea40, 0x4329481d, 0x481d4301, 0xfdeff00c, 0x7801481c, 0x4000f240, 
+    0xfde0f7eb, 0x700aea4f, 0x4187ea40, 0x3188ea41, 0x208bea41, 0x1044ea40, 0xf4404328, 0x48122100, 
+    0xfdd9f00c, 0xfdd8f7ff, 0xd0182800, 0xf00c4810, 0xb204fdd5, 0x46329900, 0xf7ff4648, 0x0070ff16, 
+    0xb2019b11, 0x462a9801, 0xfdf3f7ff, 0xff77f7ff, 0x46339801, 0x4629463a, 0xff23f7ff, 0xb0054620, 
+    0x8ff0e8bd, 0x00080400, 0xf1000480, 0x00040243, 0xf2035120, 0x4ff0e92d, 0x2000b089, 0x48fe9007, 
+    0x20099005, 0x900449fd, 0xf8df48fd, 0x680cb3fc, 0x48fc9006, 0x78009408, 0xd10a2804, 0x0000f89b, 
+    0xd1062803, 0x784048f9, 0xd0022801, 0x1c8048f4, 0xf8df9006, 0x22b183dc, 0x21014ff7, 0xf5044ef5, 
+    0xf5045a80, 0xf8c859c0, 0x46352000, 0x0000f997, 0xfec5f7f0, 0x0000f997, 0xfd7af7f0, 0xf8c821b2, 
+    0x20001000, 0xfd1ef7f0, 0xf7f02002, 0xf997ff8d, 0xf7f00000, 0x2100fd1e, 0x0000f244, 0xfd6ff7f0, 
+    0x0000f997, 0xfcccf7f0, 0xf44f2100, 0xf7eb2000, 0x21b3fd59, 0x23c048e1, 0x1000f8c8, 0xf2402200, 
+    0xf00c11ff, 0xf997fd78, 0xf7f00000, 0x4fdcfdcf, 0xe00b2000, 0x780949db, 0x2901b3f1, 0x49dad050, 
+    0x1010f831, 0x1010f825, 0xb2001c40, 0x88096839, 0x0f51ebb0, 0x48ccdbee, 0x0800f04f, 0x28037800, 
+    0x2300d041, 0x461a2101, 0x5800e9cd, 0xf7ea4608, 0x2101f97a, 0x230548c1, 0x2b00f240, 0xf8cd028a, 
+    0x9103b000, 0x3201e9cd, 0x68001e8a, 0x2105460b, 0xfedcf7ff, 0xf04f48bc, 0x78000100, 0x46082803, 
+    0x4ab6d02a, 0x681346dc, 0x2011f933, 0xda002a00, 0x1c494252, 0xe0004410, 0xb209e010, 0xdbf34561, 
+    0x21001240, 0xdd042810, 0x10401c49, 0x2906b249, 0x48b6dbf8, 0x28037800, 0xe020d020, 0xe7af49b4, 
+    0x398049b1, 0x48a9e7ac, 0xe9cd2300, 0x461a5800, 0x1001f990, 0xe7ba2001, 0x46dc4aa4, 0xf9929b08, 
+    0xeb032001, 0xf9332382, 0x2a002011, 0x4252da00, 0xb2091c49, 0x44104561, 0xe7d1dbf5, 0xf8df2105, 
+    0xf8dfe288, 0x2000c280, 0xf1ae4b9f, 0xe00c0e80, 0x2000f89c, 0xd07d2a00, 0xd07c2a01, 0x2010f933, 
+    0xf825410a, 0x1c402010, 0x683ab200, 0xebb08812, 0xdbed0f52, 0x20b44f8e, 0x461a2300, 0x60384619, 
+    0xe9cd2001, 0xf7ea5800, 0x20b5f8fe, 0x23006038, 0x461a2101, 0x5800e9cd, 0xf7ea4608, 0x20b6f8f4, 
+    0x23006038, 0x461a2102, 0xe9cd2001, 0xf7ea5800, 0x20b7f8ea, 0x23006038, 0x461a2103, 0xe9cd2001, 
+    0xf7ea5800, 0x20b8f8e0, 0x60384641, 0xf8462000, 0x1c401020, 0xf5b0b200, 0xdbf87f00, 0x46bb2500, 
+    0xf7eb2002, 0x4f7afc37, 0x3f204623, 0x20b961f8, 0x3105eb00, 0x1000f8cb, 0x0000f640, 0x48689000, 
+    0x9a062101, 0xf00d3846, 0x2002fb9f, 0xfc22f7eb, 0xf64069f9, 0x1a080200, 0x486e61f8, 0xf1002100, 
+    0xf8400814, 0x1e491025, 0x1015f828, 0x46082100, 0x3020f854, 0xb2001c40, 0x44194290, 0x12c9dbf8, 
+    0xf8542000, 0x1a5b3020, 0x3020f844, 0xb2001c40, 0xe0014290, 0xe012e00f, 0x4852dbf3, 0x0000f990, 
+    0xd00f2804, 0xd00f2805, 0x22042700, 0x40ba2000, 0x6300f5c2, 0x4a56e019, 0x2010f932, 0xf93ee770, 
+    0xe76d2010, 0xe7f02702, 0xe7ee2701, 0x0e01eb00, 0xc020f854, 0xb2091c49, 0xe02ef854, 0xf84444f4, 
+    0x428ac020, 0x1c40dcf2, 0xf04fb200, 0x42830100, 0x2000dcf7, 0x0e06f1c7, 0xf854e009, 0x4411c021, 
+    0xfa0cb209, 0xf844fc0e, 0x1c40c020, 0x428bb200, 0x2100dcf3, 0x2200f240, 0xda044290, 0x1020f844, 
+    0xb2001c40, 0x20bae7f8, 0xeb00464b, 0xf8cb3105, 0xe9dd1000, 0x46521004, 0x0100e9cd, 0x46209907, 
+    0xfd2cf00c, 0x4b3320bb, 0x3105eb00, 0x1000f8cb, 0xf1c7200e, 0xf85a070c, 0xf8592020, 0x413a1020, 
+    0x41394352, 0x2101fb01, 0x1020f844, 0x2020f856, 0x01e1eb02, 0x1020f846, 0x1020f854, 0x2025f853, 
+    0xdd034291, 0x1025f843, 0x0015f828, 0xb2001c40, 0xdbe028c3, 0x1015f938, 0xeb041e48, 0xf8540c81, 
+    0xf8543021, 0x44082020, 0xc004f8dc, 0x41c8f04f, 0x0743eba2, 0x1ad24467, 0xfb9212bb, 0xeb02f2f3, 
+    0x4a132040, 0x61903a20, 0xfb8069d2, 0x17d30101, 0xed38f00b, 0x0000e020, 0x0002c1c8, 0x000401dc, 
+    0xf203044c, 0x00040242, 0x0004057b, 0x00040520, 0x00040634, 0x00043908, 0x00040248, 0xf2030864, 
+    0x00040598, 0x00040322, 0x00040d44, 0x00040234, 0x00040bc4, 0x0004d628, 0x840cf8df, 0x4240f04f, 
+    0xf1411880, 0xeb0831ff, 0xe9c707c5, 0x48ff0100, 0x1035f858, 0x1025f840, 0x3000f44f, 0x1103f240, 
+    0xfb6ff7e4, 0x68397938, 0xea420402, 0xb2814011, 0x3000f44f, 0xfb54f7e4, 0x0035f838, 0xf44fb281, 
+    0xf7e43000, 0x20bcfb4d, 0x3105eb00, 0x1000f8cb, 0xb26d1c6d, 0xf6ff2d05, 0xf108aed3, 0xf1020228, 
+    0x25000314, 0x60151e68, 0x200e8018, 0x1020f856, 0x1020f844, 0x1020f856, 0x7025f852, 0xdd0342b9, 
+    0x1025f842, 0x0015f823, 0xb2001c40, 0xdbed28c3, 0x1015f933, 0xeb041e48, 0xf8560481, 0xf8563021, 
+    0x44082020, 0xf04f6864, 0xeba241c8, 0x44340643, 0x12a31ad2, 0xf2f3fb92, 0x2040eb02, 0x61904ad4, 
+    0xfb8069d2, 0x17d30101, 0xecacf00b, 0xf04f4ece, 0x18824240, 0xf141465f, 0xeb0630ff, 0xf44f04c5, 
+    0xe9c43800, 0x48c92000, 0x1035f856, 0x20bd6141, 0x1103f240, 0x0000f8cb, 0xf7e44640, 0x7920fb02, 
+    0x04026821, 0x4011ea42, 0x4640b281, 0xfae8f7e4, 0x0035f836, 0x4640b281, 0xfae2f7e4, 0x0035f836, 
+    0xb2017922, 0x0c006820, 0x4002ea40, 0xf7f0b200, 0x20befaf6, 0x48b76038, 0x0000f990, 0xfa50f7f0, 
+    0x603820bf, 0x2001b009, 0x4ff0e8bd, 0xb8dbf7ea, 0x4ffee92d, 0x21012500, 0xf04f462c, 0x462a4071, 
+    0xf00c9502, 0x4eabfaef, 0xd0092801, 0xf2402301, 0xf99631fe, 0x22000000, 0xfa9bf7f0, 0x8ffee8bd, 
+    0x48a52208, 0xf00c0151, 0x2208faf4, 0x01512300, 0xfb80fa4f, 0xf00c48a0, 0x48a0fade, 0x090af04f, 
+    0xf04f4f9f, 0xf8df0301, 0xf04f827c, 0x78000200, 0xd04b2801, 0x8700e9cd, 0x1000f996, 0xf7e92001, 
+    0xf8dfff9d, 0x2000c268, 0xa25cf8df, 0xf10c4643, 0xf85c0850, 0xf93ae030, 0xf9371010, 0xf9332011, 
+    0xfba21011, 0x19552e0e, 0x2030f858, 0x0001f100, 0xfba1b2c0, 0x190c1202, 0xd3ea4548, 0x1b2c488c, 
+    0x1000f996, 0x0500f04f, 0xf04f4f81, 0xf8400203, 0x69784021, 0x0138f04f, 0x0001f100, 0x48856178, 
+    0xfaa7f00c, 0xd07d2800, 0x81ecf8df, 0x22022303, 0x08c4f108, 0x4640210c, 0xfa8df00c, 0x91d8f8df, 
+    0x0000f44f, 0xf1099002, 0xe09b0956, 0xe9cd4871, 0xf9908700, 0x20011000, 0xff50f7e9, 0xf8df2400, 
+    0x21c981cc, 0x0850f108, 0xfa01fb19, 0x4a6f486e, 0xf9303a28, 0x486b1014, 0x0011f830, 0x0014f822, 
+    0xf8324a67, 0x4a695011, 0xf10afb11, 0xf8223a14, 0xfb105014, 0xfb15f200, 0xfb812205, 0x04c12302, 
+    0x46162000, 0xf00b461f, 0x0c02ebbe, 0xea42485f, 0x463b4201, 0xeb001409, 0xe9c000c4, 0x04e92100, 
+    0x20004632, 0xebaef00b, 0xea420c02, 0xeb084201, 0x140900c4, 0xb2e41c64, 0xe9c0454c, 0xd3c52100, 
+    0x21004c4c, 0x0000f994, 0xfb59f7f0, 0x2000494b, 0x461a2301, 0x46017008, 0x0000f994, 0xf9d9f7f0, 
+    0x2203484c, 0xf00c2138, 0x2800fa34, 0x4c42d032, 0x22022303, 0x210c34c4, 0xf00c4620, 0xf44ffa1c, 
+    0xe0000100, 0x4d3ce06a, 0x35569102, 0x210ae006, 0xa802462a, 0xfa7bf7eb, 0xd0062801, 0x46202202, 
+    0xf00c210c, 0x2800fa16, 0x4833d1f1, 0xf00c30cc, 0x4c2ff9e5, 0x48308160, 0xf00c30ca, 0x81a0f9df, 
+    0x30d4482d, 0xf9daf00c, 0x482b81e0, 0xf00c30d2, 0x8220f9d5, 0x210be08e, 0xa802464a, 0xfa57f7eb, 
+    0xd0062801, 0x46402202, 0xf00c210c, 0x2800f9f2, 0x4821d1f1, 0xf00c30cc, 0x8078f9c1, 0x30ca481e, 
+    0xf9bcf00c, 0x481c80b8, 0xf00c30d4, 0x80f8f9b7, 0x30d24819, 0xf9b2f00c, 0x8138b200, 0x1002f9b7, 
+    0x200af9b7, 0xd10f4291, 0x2004f9b7, 0x300cf9b7, 0xd109429a, 0x2006f9b7, 0x300ef9b7, 0xd103429a, 
+    0x2010f9b7, 0xd0034290, 0x2501697a, 0x617a1e52, 0x88b98179, 0x88f981b9, 0x823881f9, 0x950017e3, 
+    0xf9964622, 0xe0170000, 0x0004d600, 0x00041220, 0x00040ba4, 0x00040248, 0xf2035126, 0x00040246, 
+    0x00049108, 0x00048908, 0x0002b6f0, 0x0004d2b8, 0x00041210, 0xf38f007c, 0xfbdaf7f0, 0x0200f248, 
+    0x10510055, 0xdd152c00, 0xdd0f4294, 0x220048c3, 0xf00c213f, 0x281af98e, 0xf240d202, 0xe00111ff, 
+    0x31fef240, 0xdc0f42ac, 0xe00d0849, 0xdd08428c, 0xe0092103, 0x42904260, 0x42a8dd05, 0x2105dd01, 
+    0x2102e002, 0x2100e000, 0x0000f996, 0x461a2301, 0xf90ff7f0, 0x48b22208, 0xf38bfa1f, 0xf00c0151, 
+    0xe66bf95a, 0x4ff0e92d, 0xf44fb089, 0x90023000, 0x48ac1084, 0xf932f00c, 0x0003f010, 0x0100f241, 
+    0x2801d005, 0x2802d005, 0x2803d007, 0x9102d006, 0xf244e004, 0x90020000, 0x9402e000, 0x98022200, 
+    0xeb002101, 0x104070d0, 0xf04f9007, 0xf00c4071, 0x2801f929, 0x489cd175, 0x0b0af04f, 0x28017800, 
+    0x2400d005, 0x78004899, 0xd1722800, 0xf8dfe06c, 0x2500a260, 0x21004893, 0xeb003014, 0xf00c1045, 
+    0x4994f900, 0x23012000, 0xf8212200, 0x48920015, 0x1015f830, 0xf8201c49, 0x49901015, 0xe9cd4618, 
+    0xb2691a00, 0xfddaf7e9, 0xe03f2400, 0x23c9488c, 0xf9304a8c, 0x48891014, 0x0011f830, 0x0014f822, 
+    0xf83a3214, 0xf8226011, 0xfb1b6014, 0xfb11f203, 0xfb10f102, 0xfb16f200, 0xfb812206, 0x04c17302, 
+    0x46982000, 0xf00b463a, 0x4b7eea4e, 0xeb050c02, 0x33280985, 0x4201ea42, 0x1009eb03, 0x14094643, 
+    0x00c4eb00, 0x2100e9c0, 0x463a04f1, 0xf00b2000, 0x0c02ea3a, 0xea424b74, 0xeb034201, 0x14091009, 
+    0x00c4eb00, 0xb2e41c64, 0x2100e9c0, 0xd3bd455c, 0xb2ed1c6d, 0xd39d2d04, 0x21004863, 0x486b7001, 
+    0xb0097001, 0x8ff0e8bd, 0xf9904869, 0x42840000, 0x4868d078, 0x28017800, 0x4867d0f3, 0x28017800, 
+    0x4866d0ef, 0x28017800, 0x4e59d0eb, 0x4d5b2301, 0x2200b261, 0x4618468a, 0x5600e9cd, 0xfd6ef7e9, 
+    0x20004d58, 0x0384eb04, 0x35284601, 0xeb054681, 0x95081503, 0x46024d54, 0xeb054680, 0x93011303, 
+    0x9b08e02a, 0xeb034f4a, 0xe9d303c0, 0x4b4c5600, 0x3010f933, 0xf9379300, 0xfba53013, 0x17dfce03, 
+    0xe303fb06, 0x3307fb05, 0x0909eb1c, 0x41594f43, 0xeb039b01, 0xe9d303c0, 0x9b005600, 0x3013f937, 
+    0xce03fba5, 0xfb0617df, 0xfb05e303, 0xeb1c3307, 0x415a0808, 0xb2c01c40, 0xd3d24558, 0x0008ebb9, 
+    0x0102eb61, 0x4300f06f, 0x1a1b2200, 0xda02418a, 0x4000f06f, 0x4a3ae005, 0xf1711a82, 0xda0031ff, 
+    0xad034837, 0x46012800, 0x0024f845, 0x4249da00, 0x42919a02, 0x2800dd0d, 0x482cda05, 0x01fff04f, 
+    0xe0147001, 0xdd2ee034, 0xf04f4828, 0x70010101, 0x4a26e01b, 0x1000f992, 0xd0220049, 0x46012800, 
+    0x4249da00, 0x42999b07, 0x2800dd1b, 0x4819da0c, 0x1014f830, 0x0102f1a1, 0x1014f820, 0x0101f06f, 
+    0xf7f04650, 0xe00ef99e, 0xf04fdd0d, 0x46500102, 0xf997f7f0, 0xf830480f, 0x1c891014, 0x1014f820, 
+    0x2000e001, 0x49177010, 0x0024f855, 0x0024f841, 0xb2e41c64, 0xf4ff2c04, 0xe742aed5, 0xf2034202, 
+    0xf2035126, 0xf203086e, 0x00040247, 0x00040502, 0x00049108, 0x0004024a, 0x00040252, 0x00048908, 
+    0x0002b6f0, 0x0004d358, 0x0004d4c0, 0x00040ba4, 0x00040248, 0x00040285, 0x00040edb, 0x00040edc, 
+    0x80000001, 0x00041210, 0x41f0e92d, 0x460e2400, 0x46252809, 0xe8dfd215, 0x0705f000, 0x140c0a15, 
+    0x0012100e, 0xe00d2409, 0x25012408, 0x2401e00a, 0x2404e008, 0x2402e006, 0x2405e004, 0x2406e002, 
+    0x2403e000, 0xb12e4f0e, 0xf00b4638, 0xf000ff97, 0xe000000f, 0x02314620, 0x1104ea41, 0x46384301, 
+    0xf00bb289, 0x462bff8e, 0xe8bd4805, 0x220041f0, 0x30402101, 0xbf9ff00b, 0xe7c52100, 0xe7c32101, 
+    0xf2030460, 0x41f0e92d, 0x2a014e19, 0x0880f44f, 0x46074614, 0xd001b24d, 0xd1112c02, 0x46402170, 
+    0xff5ff7e3, 0xf7ed4638, 0x2000f967, 0xfedcf7ec, 0x46292001, 0x70302200, 0xfeddf7ec, 0xd0032c02, 
+    0x2c02b13c, 0xe00fd005, 0xf44f2100, 0xf7ea2080, 0x2200ff49, 0x46104629, 0xfecdf7ec, 0x70302000, 
+    0x46402171, 0xff65f7e3, 0xe8bd2001, 0x000081f0, 0x00040d84, 0x4cf4b510, 0xf00b4620, 0xf64eff3f, 
+    0x400861ee, 0x1111f241, 0x46204401, 0x4010e8bd, 0xbf37f00b, 0x4cecb510, 0xf00b4620, 0xf242ff2f, 
+    0x43012122, 0xf00b4620, 0x4620ff2c, 0xff26f00b, 0x51ddf64d, 0x46204001, 0x4010e8bd, 0xbf21f00b, 
+    0xf241b570, 0x46050400, 0x4603220c, 0x462148df, 0xff31f00b, 0x220c48de, 0x4621462b, 0xff2bf00b, 
+    0x220c48dc, 0x4621462b, 0xff25f00b, 0x4621462b, 0x4070e8bd, 0x220c48d8, 0xbf1df00b, 0x47f0e92d, 
+    0xf6404cd2, 0x220b0600, 0x46074689, 0x46314603, 0xf00b4620, 0x4dceff10, 0x463b220b, 0x46284631, 
+    0xff09f00b, 0x832cf8df, 0x463b220b, 0x46404631, 0xff01f00b, 0x4ec84631, 0x463b220b, 0xf00b4630, 
+    0xf240fefa, 0x464b4700, 0x4639220a, 0xf00b4620, 0x220afef2, 0x4639464b, 0xf00b4628, 0x220afeec, 
+    0x4639464b, 0xf00b4640, 0x464bfee6, 0x46304639, 0x47f0e8bd, 0xf00b220a, 0xb510bede, 0x46042205, 
+    0x460321e0, 0xf00b48b1, 0x48b1fed6, 0x21e02205, 0xf00b4623, 0x48affed0, 0x21e02205, 0xf00b4623, 
+    0x2205feca, 0xe8bd4623, 0x48ab4010, 0xf00b21e0, 0x2200bec2, 0x48a94603, 0xf00b2107, 0xb570bebc, 
+    0xf2484da6, 0x23000400, 0x220f4621, 0xf00b4628, 0x2301feb2, 0x220f4621, 0xf00b4628, 0x4621feac, 
+    0xe8bd4628, 0x23004070, 0xf00b220f, 0xb570bea4, 0x46042801, 0xd000460d, 0x4899b92c, 0x460b2204, 
+    0xf00b2130, 0x2c02fe98, 0x2c00d001, 0x4894d108, 0xe8bd462b, 0x22044070, 0x30802130, 0xbe8bf00b, 
+    0xe92dbd70, 0x0c1741f0, 0x28014615, 0x4606460c, 0xb9ced000, 0xd0002c01, 0x4889b94c, 0x1d004639, 
+    0xfe5ff00b, 0xb2a94886, 0xf00b1d80, 0x2c02fe5a, 0xb94cd000, 0x46394882, 0xf00b3008, 0x4880fe52, 
+    0x300ab2a9, 0xfe4df00b, 0xd0012e02, 0xd11c2e00, 0xd0002c01, 0x487ab94c, 0x30844639, 0xfe41f00b, 
+    0xb2a94877, 0xf00b3086, 0x2c02fe3c, 0x2c00d001, 0x4873d10b, 0x30884639, 0xfe33f00b, 0x4870b2a9, 
+    0x41f0e8bd, 0xf00b308a, 0xe8bdbe2c, 0x4b6d81f0, 0xb130b510, 0xd0072801, 0xd00d2802, 0xd1092803, 
+    0x2200e00d, 0xe0012103, 0x210c2202, 0xf00b4618, 0xb241fe40, 0xbd10b2c8, 0x21302204, 0x2206e7f6, 
+    0xe7f321c0, 0x4d59b570, 0x1cad4604, 0xf00b4628, 0x4e5dfe05, 0x0000f364, 0x46304601, 0xfe01f00b, 
+    0xd1092c00, 0xf00b4628, 0xf020fdf9, 0x46300102, 0x4070e8bd, 0xbdf5f00b, 0xb570bd70, 0x1ca44c4b, 
+    0xf00b4620, 0x4d50fdeb, 0x0102f040, 0xf00b4628, 0x4620fde8, 0xfde2f00b, 0x0102f020, 0xe8bd4628, 
+    0xf00b4070, 0xb57fbdde, 0x46144b48, 0xcb4e460d, 0x004ee88d, 0xffabf7ff, 0x0020f85d, 0xeb00b2a1, 
+    0xf00b0045, 0xbd7ffdce, 0x4604b510, 0x1c804837, 0xfdc4f00b, 0x7100f240, 0x2104ea01, 0x60e2f420, 
+    0xe8bd4308, 0xf0404010, 0x48370110, 0xbdb9f00b, 0x2801b510, 0xd0004604, 0x2301b92c, 0x22004830, 
+    0xf00b4619, 0x2c02fdc8, 0x2c00d001, 0x482cd108, 0x22002301, 0xe8bd4619, 0x30804010, 0xbdbbf00b, 
+    0xe92dbd10, 0x4c2741f0, 0xb283461d, 0x22004616, 0x2103460f, 0xf00b4620, 0xb2bbfdae, 0x22024620, 
+    0xf00b210c, 0xb2b3fda8, 0x22044620, 0xf00b2130, 0xb2abfda2, 0xe8bd4620, 0x220641f0, 0xf00b21c0, 
+    0xb570bd9a, 0x4604b283, 0xf6414810, 0x220b0500, 0x1c804629, 0xfd8ff00b, 0xb2a3480d, 0x4629220b, 
+    0xf00b1c80, 0x480bfd88, 0x220bb2a3, 0x1c804629, 0xfd81f00b, 0x4808b2a3, 0xe8bd4629, 0x220b4070, 
+    0xf00b1c80, 0x0000bd78, 0xf23c8000, 0xf2033040, 0xf2033240, 0xf2033440, 0xf2033640, 0xf2033a00, 
+    0xf2033b00, 0xf2035026, 0xf2033842, 0x0002b784, 0x41f0e92d, 0xf7f82400, 0x4862febe, 0xf8df4f62, 
+    0x4e64c190, 0x48617801, 0xf990683a, 0x2b033000, 0x4d61d005, 0xd00e2b05, 0xd01d2b04, 0x485fe026, 
+    0x28126800, 0xf64dd302, 0xe00160f7, 0x60eaf64e, 0x14124342, 0x7830e01a, 0xd0072801, 0xd0052802, 
+    0x4000f89c, 0xd0014320, 0xe00f2401, 0xb1087828, 0xe00b2404, 0xe0092403, 0x28017830, 0x2802d029, 
+    0xf89cd027, 0x43204000, 0x2402d023, 0x70fff643, 0xdb004282, 0x4d4a1e42, 0xeb052000, 0xf1c01404, 
+    0xf9340507, 0x42955015, 0x1c40dc03, 0x2808b200, 0x4a43dbf5, 0x0007f1c0, 0x2b043290, 0x5010f812, 
+    0xd00c4a40, 0xd02b2b05, 0xd25f2d0c, 0xb3287810, 0x7828e01e, 0x2406b108, 0x2405e7d8, 0x7830e7d6, 
+    0xd0082801, 0xd0062802, 0x3000f89c, 0xd0024303, 0xd0512803, 0x2d2de007, 0x2401d201, 0x2400e020, 
+    0x2402e01e, 0x2d0ce01c, 0x7810d246, 0xd0f82800, 0xd238290f, 0xe0172407, 0xe0152406, 0xe00f2405, 
+    0x28017830, 0x2802d005, 0xf89cd003, 0x43183000, 0x2d23d1e9, 0x2404d201, 0x2d2de002, 0x2403d21e, 
+    0x78004821, 0xd0e72801, 0x2c002000, 0x4604da00, 0xf00b481e, 0x8838fca6, 0x481cb281, 0xf00b3020, 
+    0x7831fca0, 0xeb000320, 0x44282001, 0x4817b281, 0xf00b3026, 0x4620fc96, 0x81f0e8bd, 0xd3c02d41, 
+    0xd2bc2d55, 0x2919e7b9, 0xe7c5d2c8, 0xd3c52d23, 0xd3d02d2d, 0xd3d22d37, 0xd3b22d41, 0xd2ae2d4b, 
+    0x0000e7ab, 0x00040504, 0x00040594, 0x00040242, 0x000404f6, 0x0004057b, 0x00040502, 0x000401f0, 
+    0x00040dc4, 0x000402ac, 0x000402ad, 0xf2035182, 0xb50848fe, 0x90008800, 0x780348fd, 0xf99048fd, 
+    0x48fd2000, 0x20007801, 0xfd97f7ff, 0x4008e8bd, 0xf7ed2004, 0xb57cbf18, 0xf7f02001, 0x4cf7f906, 
+    0x4bf82204, 0x48f6b241, 0x70212903, 0x2905d002, 0xe022d014, 0x29948819, 0x2984d00c, 0x29a4d00a, 
+    0x29b4d008, 0x2998d006, 0x29a8d011, 0x2988d00f, 0xe00ad00d, 0x70212105, 0xe00a2307, 0x29988819, 
+    0x2988d005, 0x29a8d003, 0x29b8d001, 0x2306d105, 0x22027022, 0xf00b213c, 0x7820fc3e, 0xfc02f7ea, 
+    0x700849e1, 0xf7ef2008, 0x7820f866, 0xfd82f7ed, 0xf7ee2005, 0x2000f8c3, 0xfaedf7ee, 0x250049d6, 
+    0x23019500, 0x461a7820, 0xf7e67809, 0x2101fadc, 0xf7ed4608, 0xf640fdf5, 0xf6474100, 0x23177203, 
+    0x00889500, 0xfda0f7ed, 0x210248d0, 0xfbf9f00b, 0xf64048cf, 0xf00b7131, 0x2001fbf4, 0x46022300, 
+    0x0500e9cd, 0xf7eb4619, 0x49cafd15, 0x60082019, 0xe92dbd7c, 0x4fc85ffc, 0x8e804606, 0xb31cf8df, 
+    0x831cf8df, 0x683b28e2, 0xdc05d075, 0x289ab170, 0x289bd018, 0xe020d170, 0xd00628e3, 0x7f90f5b0, 
+    0xf5a0d06b, 0x38217080, 0xe1b0d166, 0xf04f49bb, 0xf8db32ff, 0x1d090000, 0xf9c0f007, 0xd1081d01, 
+    0xe0aa209a, 0x220049b5, 0x0000f8db, 0xf0071d09, 0x1d41f9b5, 0x2801d02d, 0x48b0d1e8, 0xf9b01d00, 
+    0x296e1000, 0xf04fd1e2, 0x46815580, 0x4220f04f, 0xf7e34628, 0xf898fbe4, 0xf04f1000, 0x46445290, 
+    0xf7e34628, 0x7820fbdc, 0xd0772800, 0xf04f2500, 0x24010a05, 0xd00e2801, 0xd0462802, 0xd0492803, 
+    0xd07d2804, 0xd06b2805, 0xd06a2806, 0xd0692807, 0x209be174, 0xf7fce071, 0xf7fffcf4, 0xf7ffff2c, 
+    0x4893ff17, 0x220f2300, 0x0100f248, 0xf00b301a, 0x2201fb92, 0x46112300, 0x4500e9cd, 0xf7eb4610, 
+    0x4890fc99, 0xfb6af00b, 0x8008498f, 0x488f0701, 0x8004d004, 0xe00ee003, 0xe044e050, 0x22008005, 
+    0xf8a94986, 0x6838a000, 0xf0071d09, 0x1d01f928, 0x20e2d107, 0x4981e041, 0x46182200, 0xf0071d09, 
+    0x1d40f91e, 0x20e3d179, 0xf7ffe037, 0xf7fffef4, 0xe120fedf, 0xfeeff7ff, 0x23004d7d, 0xf640220b, 
+    0x46280100, 0xfb57f00b, 0x46282301, 0x0319220c, 0xfb51f00b, 0xf640486e, 0xf00b1137, 0x4875fb32, 
+    0x496e2200, 0x70041d09, 0xa000f8a9, 0xf0076838, 0x1d01f8f6, 0xf240d10d, 0xe00e1020, 0xe00fe105, 
+    0xe0efe06f, 0x4965e100, 0x46182200, 0xf0071d09, 0x1d40f8e6, 0xf240d1c6, 0x86b01021, 0x9ffce8bd, 
+    0xfeb9f7ff, 0xfea4f7ff, 0xf9904854, 0x28050000, 0x2804d034, 0x2000d034, 0x7809495f, 0xd0312901, 
+    0xd0352902, 0xd0392904, 0xd03d2905, 0xd0412906, 0x462c2500, 0xfc53f7ff, 0x88004844, 0x48449000, 
+    0x48447803, 0x2000f990, 0x78014843, 0xf7ff2003, 0x2004fc24, 0xfc3df7ff, 0x46082100, 0xfc57f7ff, 
+    0x462a2101, 0xf7ff2000, 0x2102fc6c, 0x20004622, 0xfc67f7ff, 0xf7ff2000, 0xe0b8fd1b, 0xe7cb2001, 
+    0xe7c92002, 0x7580f241, 0x2480f641, 0xe01640c5, 0x2580f243, 0x3480f243, 0xe01040c5, 0x1580f645, 
+    0x2480f645, 0xe00a40c5, 0x2580f648, 0x4480f648, 0xe00440c5, 0x6580f24c, 0x0480f64c, 0x40c440c5, 
+    0xf7ffe7b8, 0xf7fffe58, 0xf7fffe43, 0x2100fcb6, 0x46082240, 0xfcc7f7ff, 0x2101220d, 0xf7ff2000, 
+    0x2205fcc2, 0x20002102, 0xfcbdf7ff, 0x21002240, 0xf7ff2001, 0x2101fcb8, 0x4608220d, 0xfcb3f7ff, 
+    0x21022205, 0xf7ff2001, 0x2240fcae, 0x20022100, 0xfca9f7ff, 0x2101220d, 0xf7ff2002, 0x2102fca4, 
+    0x46082205, 0xfc9ff7ff, 0x21002240, 0xf7ff2003, 0x220dfc9a, 0x20032101, 0xfc95f7ff, 0x21022205, 
+    0xf7ff2003, 0x2000fc90, 0x0000e028, 0x00040270, 0x000402c8, 0x000401ec, 0x0004057b, 0x00040242, 
+    0xf2020000, 0x000404fe, 0x00040243, 0xf23c8304, 0xf203502a, 0x000401f0, 0x000406cc, 0x00040e64, 
+    0x00040234, 0xf2035136, 0x00040272, 0x00040274, 0xf38fffd2, 0x00040248, 0x00040528, 0xfc32f7ff, 
+    0xf7ff2003, 0x2301fc71, 0x46192200, 0x5400e9cd, 0xf7eb4618, 0x2301fb5f, 0x46182200, 0xe9cd2102, 
+    0xe00e5400, 0xfdd7f7ff, 0xfdc2f7ff, 0xf6404838, 0xf00b7131, 0x2300fa26, 0x46182201, 0x4500e9cd, 
+    0xf7eb4611, 0xe002fb47, 0xf7eb2001, 0xf898fbd6, 0x28070000, 0xae4af43f, 0xd0fb2800, 0xfadaf7ff, 
+    0x2200e644, 0xb5102101, 0x30b9f2af, 0xfe22f006, 0x20022108, 0xff80f006, 0x60084926, 0xb57cbd10, 
+    0xf7ea2000, 0x2100fe41, 0xf7fe2006, 0x4822f9cf, 0x4c222500, 0x95004629, 0x46287802, 0xf7fe7823, 
+    0x2004f91d, 0xfc00f7ef, 0x8800481d, 0x481d9000, 0x78037821, 0xf990481c, 0x20002000, 0xfb1df7ff, 
+    0xf7eb2000, 0x2001faff, 0x46022300, 0x0500e9cd, 0x46184601, 0xfafef7eb, 0x21004814, 0xf9d1f00b, 
+    0xf2414c13, 0x78210000, 0xf9bcf7ea, 0x0550f242, 0x06ee4629, 0xf7e34630, 0x7821f9c0, 0xf7ea0bf0, 
+    0x4629f9b1, 0xe8bd4630, 0xf7e3407c, 0x0000b9b6, 0xf203502a, 0x00040e64, 0x00040242, 0x0004057b, 
+    0x00040270, 0x000402c8, 0x000401ec, 0xf2034220, 0x00040243, 0x43f8e92d, 0x48ff4606, 0x600149fd, 
+    0xf00b48fe, 0x2000f998, 0xfddef7ea, 0xffb6f7e8, 0x83ecf8df, 0x2400f240, 0xf8984620, 0xf7e81000, 
+    0x48f8ffb7, 0x71fff64f, 0xf985f00b, 0x20022100, 0xf910f7ea, 0x230048f4, 0x21022201, 0xf99bf00b, 
+    0x93c8f8df, 0x22092300, 0x46484621, 0xf993f00b, 0x230148ee, 0x03d9220f, 0xf00b3012, 0x4fe6f98c, 
+    0x1d3f2500, 0xb2e12400, 0x0014f837, 0xb2024240, 0xf7ffb2e8, 0x1c64fb88, 0xdbf42c10, 0x2d041c6d, 
+    0x2000dbf0, 0xfb4ef7ff, 0xf7ff2003, 0x48dffb8d, 0x21012300, 0x30a0461a, 0xf96df00b, 0x46082100, 
+    0xfa4cf7eb, 0x680048da, 0x38087f80, 0xf7edb2c0, 0x2300f8dd, 0x22074648, 0xf00b2180, 0x2300f95c, 
+    0x210148d4, 0xf00b461a, 0x2000f956, 0xf8989000, 0x22033000, 0x20084601, 0xf860f7fe, 0x23004dce, 
+    0x21e02205, 0xf00b4628, 0x4cccf946, 0x22052300, 0x462021e0, 0xf93ff00b, 0x8324f8df, 0x22052300, 
+    0x464021e0, 0xf937f00b, 0x9318f8df, 0x22052300, 0x464821e0, 0xf92ff00b, 0xf7eb2001, 0x2100fa33, 
+    0x2080f44f, 0xf8fef7ea, 0x20012100, 0xf97cf7fb, 0xf2402202, 0x210710c3, 0xf984f7ff, 0xf7ec48ba, 
+    0x2000f8d4, 0xf978f7ff, 0x23022100, 0x22084608, 0xfda9f7ea, 0x2100230c, 0x4608461a, 0xfddef7ea, 
+    0x461a2300, 0x46184619, 0xfdbff7ea, 0x20002101, 0xfd87f7ea, 0x22112300, 0x3100f44f, 0x4071f04f, 
+    0xf8e2f00b, 0xf7ea2001, 0xf44ffd1f, 0x21001700, 0xf7ea4638, 0x230cf8c7, 0x461a2100, 0xf7ea4608, 
+    0x2100fdbd, 0xf7ea4638, 0x230df8bd, 0x461a2100, 0xf7ea4608, 0x2100fdb3, 0xf7ea4638, 0x04f0f8b3, 
+    0x10c02205, 0x0f4321e0, 0xf00b4628, 0x04b0f8d4, 0x10c02205, 0x0f4321e0, 0xf00b4620, 0x0470f8cc, 
+    0x10c02205, 0x0f4321e0, 0xf00b4640, 0x0430f8c4, 0x10c02205, 0x0f4321e0, 0xf00b4648, 0xe8bdf8bc, 
+    0x200243f8, 0xb837f7ea, 0x47f0e92d, 0x4605b088, 0xae042000, 0xf8464601, 0x1c401020, 0xdbfa2804, 
+    0x91e8f8df, 0xf8df2400, 0xf248a1e4, 0xf1090800, 0x466f0918, 0x0a06f10a, 0x21004640, 0xf872f7ea, 
+    0x466b2101, 0x4650464a, 0xffb5f00b, 0xf8562000, 0xf8571020, 0x44112020, 0x1020f846, 0x28041c40, 
+    0x1c64dbf5, 0xdbe72c40, 0xf8562000, 0x31201020, 0xf8451189, 0x1c401020, 0xdbf62804, 0xf105b008, 
+    0xe8bd0010, 0x460387f0, 0xb5102000, 0xe005188c, 0x2011f833, 0xfb121c49, 0x4410f202, 0xdcf7428c, 
+    0xe92dbd10, 0xf04f4ff8, 0x46044571, 0xf00b4628, 0x2300f83f, 0x21014683, 0x4628461a, 0xf844f00b, 
+    0x465046aa, 0xf834f00b, 0xd1fa07c0, 0x25004857, 0xf8d046a9, 0x22008000, 0x4610b269, 0x460e4643, 
+    0x9000f8cd, 0xfd42f7e8, 0x46be2700, 0x463a46bc, 0x0012f938, 0xdb012800, 0xe0004603, 0xb2194243, 
+    0xdd0242b9, 0x4686460f, 0x1c524694, 0x2a80b212, 0x2280dbee, 0x21004640, 0xec00e9c4, 0xffb3f7ff, 
+    0x60a02280, 0x46404611, 0xffadf7ff, 0x60e02280, 0x00514640, 0xffa7f7ff, 0xf2402280, 0x61201180, 
+    0xf7ff4640, 0x2280ffa0, 0x46406160, 0xf7ff0091, 0x2280ff9a, 0x2180f240, 0x464061a0, 0xff93f7ff, 
+    0xf2402280, 0x61e03100, 0xf7ff4640, 0x2280ff8c, 0x3180f240, 0x46406220, 0xff85f7ff, 0x62602701, 
+    0x46433428, 0x46312000, 0xf8cdb27a, 0xf7e89000, 0x2280fced, 0x21004640, 0xff75f7ff, 0x60202280, 
+    0x46404611, 0xff6ff7ff, 0x60601c7f, 0x3408b23f, 0xdbe62f04, 0xb22d1c6d, 0xdb8c2d04, 0x46504659, 
+    0xffb9f00a, 0xe8bd4620, 0xe92d8ff8, 0xf5ad4ff0, 0xf7ff7d0b, 0x2000fe0f, 0x4601ad40, 0x1020f845, 
+    0x28401c40, 0x2000dbfa, 0x417ff06f, 0x4690aa86, 0x0000e01e, 0x00046908, 0x00040e70, 0xf0003088, 
+    0x0004057b, 0xf1000048, 0xf23c8310, 0xf2030400, 0x00040598, 0xf2031012, 0xf2033040, 0xf2033240, 
+    0xf2033440, 0xf2033640, 0x00040538, 0x000401e8, 0x1020f842, 0x28041c40, 0x2400dbd9, 0xf50d46eb, 
+    0xf2407a00, 0x26004700, 0x0900f1c7, 0xd0642c00, 0xb2704649, 0xf915f7ef, 0x2e041c76, 0x2100dbf6, 
+    0x0000f44f, 0xff5ef7e9, 0xf7ff4668, 0xa880ff1a, 0xfecaf7ff, 0x46dc2000, 0xeb0c0101, 0xeb050681, 
+    0x68b30281, 0x42bb6897, 0xf85cdd06, 0xf8457021, 0x68767021, 0x6301e9c2, 0x188e2203, 0x3026f85c, 
+    0x7026f855, 0xdd0142bb, 0x3026f845, 0x2a0f1c52, 0xf858ddf3, 0x46423020, 0x1020f85a, 0xdd01428b, 
+    0x1020f842, 0x28041c40, 0x1c64dbd6, 0xdbb82c02, 0x680448fe, 0xf8522000, 0x1c401020, 0xc4022804, 
+    0xa884dbf9, 0xff01f7eb, 0xa9842000, 0x2010f931, 0x28041c40, 0xdbf9c404, 0xf8552000, 0xf8441020, 
+    0x1c401020, 0xdbf82840, 0xf44f2100, 0xf7e91080, 0xf50dff09, 0xe8bd7d0b, 0x46398ff0, 0xb510e799, 
+    0x20004604, 0xe0074602, 0x3012f934, 0xda012b00, 0xe0001ac0, 0x1c524418, 0xdbf5428a, 0xb5ffbd10, 
+    0x466d2300, 0xf845461c, 0x1c5b4023, 0xdbfa2b04, 0xe0162300, 0x6013f930, 0x44349c00, 0xeb009400, 
+    0x9e010443, 0xf9b41d1b, 0x443e7002, 0xf9b49601, 0x9e027004, 0x9602443e, 0x4006f9b4, 0x44349e03, 
+    0x428b9403, 0x108bdbe6, 0xb2141e92, 0xf8552100, 0xeb022021, 0x41220263, 0x2021f845, 0x29041c49, 
+    0x2100dbf5, 0xf830e014, 0x9c002011, 0xf8201b12, 0xeb002011, 0x9d010241, 0x1b648854, 0x88948054, 
+    0x1b649d02, 0x88d48094, 0x1b649d03, 0x1d0980d4, 0xdbe84299, 0xe92dbdff, 0xb0934ff0, 0xfd0af7ff, 
+    0x9004200a, 0x4dba2300, 0x210148ba, 0x4400f240, 0xf00a461a, 0x2300fea9, 0x461a2101, 0x4071f04f, 
+    0xfea2f00a, 0xf7fe2000, 0x2140ff17, 0xf7ea2000, 0x48aefb25, 0x090df04f, 0x20006807, 0x90094680, 
+    0x49ad9012, 0x80c84aae, 0x80488088, 0x48ab8008, 0x780349ac, 0xf7eb48a8, 0xf44ffe77, 0x21001680, 
+    0xf7e94630, 0x2101fe6f, 0x46082304, 0xf7ed2200, 0x2100fed9, 0xf7e94630, 0x12b1fe65, 0x0b01f04f, 
+    0x23009400, 0x46281e5a, 0xb101e9cd, 0xf8cd2103, 0xf7feb00c, 0x2600f81b, 0x0a38f10d, 0xfb069a04, 
+    0x4621f004, 0x0040eb05, 0xf7ff4684, 0x4660ff58, 0xf7ff4621, 0xf84aff44, 0x1c760026, 0xdbed2e04, 
+    0x4100f240, 0x23009400, 0x1e5a4628, 0xb101e9cd, 0xf8cd2103, 0xf7fdb00c, 0x2600fff9, 0x46219a04, 
+    0xf004fb06, 0x0040eb05, 0xf7ff4684, 0x4660ff38, 0xf7ff4621, 0xf85aff24, 0x18812026, 0x1026f84a, 
+    0x2e041c76, 0xf240dbea, 0x94004100, 0x46282300, 0xe9cd1e5a, 0x2103b101, 0xb00cf8cd, 0xffd6f7fd, 
+    0x9a042600, 0xfb064621, 0xeb05f004, 0x46840040, 0xff15f7ff, 0x46214660, 0xff01f7ff, 0x2026f85a, 
+    0xf84a1881, 0x1c761026, 0xdbea2e04, 0x94002001, 0x02811e82, 0xe9cd2300, 0x21030101, 0x46289003, 
+    0xffb4f7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 0x46840040, 0xfef3f7ff, 0x46214660, 0xfedff7ff, 
+    0x2026f85a, 0x188146d3, 0x1026f84a, 0x2e041c76, 0x2201dbe9, 0x46112304, 0xf7ed4610, 0x2100fe43, 
+    0x1080f44f, 0xfdcef7e9, 0x48544953, 0xf8a14a54, 0xf8a19006, 0xf8a19004, 0xf8a19002, 0x78039000, 
+    0x484d4950, 0xfdc0f7eb, 0x23022101, 0x22084608, 0xfa79f7ea, 0xf242220b, 0x46110600, 0xf7ea4630, 
+    0x220cfb89, 0x46114630, 0xfb84f7ea, 0x4630220d, 0xf7ea4611, 0x2001fb7f, 0x1e829400, 0x23000281, 
+    0x0101e9cd, 0x90032103, 0xf7fd4628, 0x2600ff5f, 0x0a28f10d, 0xfb069a04, 0x4621f004, 0x0040eb05, 
+    0xf7ff4684, 0x4660fe9c, 0xf7ff4621, 0xf84afe88, 0x1c760026, 0xdbed2e04, 0x94002001, 0x02811e82, 
+    0xe9cd2300, 0x21030101, 0x46289003, 0xff3ef7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 0x46840040, 
+    0xfe7df7ff, 0x46214660, 0xfe69f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 0xdbea2e04, 0x94002001, 
+    0x02811e82, 0xe9cd2300, 0x21030101, 0x46289003, 0xff1cf7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 
+    0x46840040, 0xfe5bf7ff, 0x46214660, 0xfe47f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 0xdbea2e04, 
+    0x94002001, 0x02811e82, 0xe9cd2300, 0x21030101, 0x46289003, 0xfefaf7fd, 0x9a042600, 0xfb064621, 
+    0xeb05f004, 0x46840040, 0x0000e00e, 0x00040e70, 0x00041908, 0xf1000030, 0x00040538, 0x0004057b, 
+    0x00040520, 0x0004054e, 0xfe29f7ff, 0x46214660, 0xfe15f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 
+    0xdbda2e04, 0xf7ffa805, 0x2000fc7f, 0xab054651, 0xf852465a, 0x603e6020, 0x6020f851, 0xf853607e, 
+    0x1c406020, 0x370c60be, 0xdbf22804, 0x21402600, 0xf7eeb270, 0x1c76fea6, 0xdbf82e04, 0x0801f108, 
+    0x0f40f1b8, 0x9812da01, 0x2100e66b, 0x1080f44f, 0xfce8f7e9, 0xea409809, 0xea412100, 0xea414100, 
+    0x60386000, 0x2109ea49, 0x4109ea41, 0x6009ea41, 0xb0136078, 0xe92de5cf, 0x250041f0, 0x4700f240, 
+    0x21004efe, 0xf7e94638, 0x4630fccd, 0xfcd6f00a, 0x0720b204, 0x48f9d0f5, 0x1c80b2a1, 0xfcd1f00a, 
+    0x000ff004, 0xd00f2801, 0xd0112802, 0xd0132803, 0xf64f2501, 0xea0470f0, 0x46300100, 0xfcc1f00a, 
+    0xd0de2d00, 0x81f0e8bd, 0xf7ff4620, 0xe7f0fe04, 0xf7ff4620, 0xe7ecfcfa, 0xf7ff4620, 0xe7e8fb0b, 
+    0x4ff8e92d, 0xf64f48e6, 0xf8df71ff, 0x6800b398, 0x08478800, 0xf00a4658, 0x2100fc9e, 0xf7e92002, 
+    0xf7f1fc29, 0x4ee0f8f1, 0x94002400, 0x21012203, 0x7833200a, 0xfbc2f7fd, 0xf8def7f1, 0x20012100, 
+    0xfd02f7fa, 0xf942f7f7, 0x20012100, 0xfcfcf7fa, 0x210048d6, 0x68052201, 0x94004608, 0xf7e8462b, 
+    0x2100f995, 0x4628463a, 0xfc1df7ff, 0x46802201, 0x462b2000, 0x94004611, 0xf988f7e8, 0x463a2100, 
+    0xf7ff4628, 0x2203fc10, 0x21024682, 0x2000462b, 0xf7e89400, 0x2100f97b, 0x4628463a, 0xfc03f7ff, 
+    0x46812203, 0x462b2000, 0x94004611, 0xf96ef7e8, 0x463a2100, 0xf7ff4628, 0x4cbdfbf6, 0x0200f242, 
+    0xda054590, 0xda034592, 0xda014591, 0xdb014290, 0xe0004db8, 0x46584db8, 0xf00a4629, 0x2000fc3c, 
+    0xf7ea6025, 0xf7e8f881, 0xf7f0fa59, 0x4dabff5a, 0x35742400, 0xb2241c64, 0xf800f7f0, 0xfcf4f7f7, 
+    0xf945f7fd, 0xf249b110, 0xe003010d, 0xddf12c05, 0x31adf640, 0xf00a4628, 0x2100fc24, 0xf7fa2001, 
+    0xf7f3fc93, 0xf7f2f959, 0xf7f2fff4, 0xf7f3ff5b, 0xf7f2f80a, 0x2000fec0, 0xf856f7ea, 0xf7fc2000, 
+    0x499efe47, 0xf7e8b240, 0x2001f9d4, 0xfe40f7fc, 0xb240499a, 0xf7e83120, 0x2002f9cc, 0xfe38f7fc, 
+    0xb2404996, 0xf7e83140, 0x2003f9c4, 0xfe30f7fc, 0xb2404992, 0xf7e83160, 0xf8dff9bc, 0x25008240, 
+    0xeb082400, 0x46211745, 0x0014f837, 0xb2024240, 0xf7fe4628, 0x1c64fe08, 0x2c10b2e4, 0x1c6dd3f3, 
+    0x2d04b2ed, 0x2000d3ec, 0xfdccf7fe, 0xf7fe2003, 0x2300fe0b, 0x21014882, 0xf00a461a, 0x2100fbec, 
+    0xf7ea4608, 0x4c7ffccb, 0x0500f241, 0x78214628, 0xfbb8f7e9, 0x20012100, 0xfc36f7fa, 0xf7fe2004, 
+    0x7821fc3b, 0xf7e94628, 0x2001fbad, 0xfffcf7e9, 0x01e87821, 0xfba6f7e9, 0xf7e92000, 0x2002fff5, 
+    0xfcd0f7ea, 0x23004d70, 0x210c2202, 0xf00a4628, 0x7830fbc2, 0x2801b120, 0x2802d004, 0xe004d002, 
+    0xe0002005, 0xf7fe2006, 0x2301fc19, 0x220a4628, 0x4639029f, 0xfbaff00a, 0x46387821, 0xfb82f7e9, 
+    0xf7e92001, 0x4855ffd1, 0x38160179, 0xfb89f00a, 0x23007832, 0x20082101, 0xfa5cf7ee, 0x485b2300, 
+    0x461a2101, 0xfb97f00a, 0xfaa9f7ee, 0x20014c58, 0xf7ea7821, 0x4957fdfc, 0x70087820, 0xf8e2f7eb, 
+    0xf7f92004, 0xe8bdfd0e, 0x21004ff8, 0xf7fa2001, 0xe92dbbdb, 0x21005ff0, 0xf7e92002, 0x4848faeb, 
+    0x22092301, 0x38a00259, 0xfb75f00a, 0xf7e92000, 0xf7e8ff9b, 0x4842f973, 0x0a00f248, 0x46512301, 
+    0x388e220f, 0xfb67f00a, 0xf7ea2001, 0x483cfc6b, 0x38402100, 0xfb45f00a, 0x23014839, 0x21802207, 
+    0xf00a38a0, 0x4c37fb58, 0x4500f240, 0x78214628, 0xfb28f7e9, 0x23014e34, 0x3672220f, 0x463003d9, 
+    0xfb49f00a, 0x46302380, 0x1e692200, 0xfb43f00a, 0x22002306, 0x1cb021ff, 0xfb3df00a, 0x8080f8df, 
+    0x217f2200, 0x0000f8d8, 0x304af8b0, 0xf00a1d30, 0xf1a6fb32, 0x01690b02, 0x4658465e, 0xfb11f00a, 
+    0x0180f248, 0xf00a4630, 0x7821fb0c, 0xf7e94628, 0xf44ffaf9, 0xf2400900, 0x464f11f4, 0xf7e24648, 
+    0x491dfaf0, 0xf7e24638, 0x4817fadb, 0xfaf6f00a, 0x46384601, 0xfad4f7e2, 0x30804813, 0xfaeef00a, 
+    0x46384601, 0xfaccf7e2, 0x46384914, 0xfac8f7e2, 0x3080480d, 0xfae2f00a, 0xe0214601, 0xf2035136, 
+    0x00040598, 0xf1000048, 0x0004057b, 0x000401e8, 0x000402a8, 0x8421b7ed, 0x84217bde, 0x00041258, 
+    0xf20304a0, 0x00040243, 0xf2035022, 0xf2036104, 0x00040242, 0x000401fc, 0x90010000, 0xdcba01f5, 
+    0x307448aa, 0xfabdf00a, 0x46292300, 0x4630220a, 0xfad1f00a, 0x46292301, 0x4630220a, 0xfacbf00a, 
+    0x46292300, 0x4630220a, 0xfac5f00a, 0x220d48a0, 0x0100f246, 0x0000f990, 0x4630b283, 0xfabbf00a, 
+    0x46302300, 0x21202205, 0xfab5f00a, 0x46302301, 0x21202205, 0xfaaff00a, 0x46572600, 0x220f4893, 
+    0x38724639, 0xfab5f00a, 0x1c76b918, 0x42beb236, 0xf7fcdbf4, 0x4682fd33, 0x11f4f240, 0x4648464e, 
+    0xfa6ff7e2, 0x4630498b, 0xfa5af7e2, 0x38724887, 0xfa74f00a, 0x46304601, 0xfa52f7e2, 0x46304651, 
+    0xfa4ef7e2, 0x46304984, 0xfa4af7e2, 0x0000f8d8, 0x8f412201, 0x44088f80, 0x2100b200, 0xfc01f7ea, 
+    0xf7eb2074, 0x2301fc61, 0x220f4639, 0xf00a4658, 0x4e7afa72, 0x220b2300, 0x0100f640, 0xf00a4630, 
+    0x2300fa6a, 0x220a4629, 0xf00a4630, 0x2300fa64, 0x2100f240, 0x46302209, 0xfa5df00a, 0x46302208, 
+    0x01512300, 0xfa57f00a, 0x46302303, 0x21c02206, 0xfa51f00a, 0xf6474869, 0x23007600, 0x22084631, 
+    0xf00a1c80, 0xf8dffa48, 0x23008194, 0x461a217f, 0x0804f108, 0xf00a4640, 0x2300fa3e, 0x22084631, 
+    0xf00a4640, 0x2002fa38, 0xfb3cf7ea, 0x46082100, 0xfb02f7ea, 0x78304e5a, 0x2801b120, 0x2802d004, 
+    0xe004d002, 0xe0002005, 0xf7fe2006, 0x4853fa87, 0x220a2301, 0x30084629, 0xfa1df00a, 0x46287821, 
+    0xf9f0f7e9, 0x46394849, 0xf00a3816, 0x7832f9fa, 0x21012300, 0xf7ee2008, 0x2300f8cd, 0x21014849, 
+    0xf00a461a, 0x7821fa08, 0xf7e94628, 0xf7eef9db, 0x4c45f916, 0x78212001, 0xfc69f7ea, 0x78204943, 
+    0xf7ea7008, 0x4638ff4f, 0x5ff0e8bd, 0xf04f2102, 0xf7e24210, 0xb570ba14, 0xf7e34604, 0x2000fb8c, 
+    0xfaf0f7ea, 0x23004d35, 0xf240220a, 0x35084100, 0xf00a4628, 0x2100f9e0, 0xf7ea2001, 0x2100faad, 
+    0xf7ea2001, 0x2301fabb, 0x22064628, 0xf00a2140, 0x2301f9d2, 0x22054628, 0xf00a2120, 0x492cf9cc, 
+    0x4a232019, 0x20006008, 0xf991492a, 0x54d03000, 0x3001f991, 0x54d02001, 0x3002f991, 0x54d02002, 
+    0x1003f991, 0x54502003, 0xfe2ff7fc, 0xf0072000, 0x2300fe15, 0x46192201, 0xf007b2e0, 0x2300fa87, 
+    0x4619461a, 0xf007b2e0, 0x481bfca1, 0x780006ea, 0x010ff000, 0x29011250, 0x2902d004, 0x2903d008, 
+    0xe00dd00c, 0xf7e22116, 0xf7fff9ba, 0xe007fe12, 0xf7e22117, 0xf7fff9b4, 0xe001fcc3, 0xfc8bf7ff, 
+    0x4070e8bd, 0xf7e92002, 0x0000b906, 0xf2035136, 0x00040518, 0x90010001, 0xdcba01f5, 0xf203501a, 
+    0x0004057b, 0xf2036104, 0x00040242, 0x000401fc, 0x000401f0, 0x00040520, 0x000402a5, 0x43f8e92d, 
+    0x46044d4f, 0xb1208e80, 0xd00d287e, 0xd134287f, 0x494be014, 0x32fff04f, 0x1d096828, 0xff3ef005, 
+    0xd1071d01, 0xe027207e, 0x22004945, 0x1d096828, 0xff34f005, 0xd01e1d41, 0xd1ea2801, 0x1d004840, 
+    0x28298800, 0x483fd1e5, 0x21042202, 0xf951f00a, 0xb2c04b3d, 0x28014f3d, 0xf04f4e3d, 0xf44f58a8, 
+    0xf6400900, 0xf04f0100, 0x4618020b, 0xf00ad007, 0xb1e8f940, 0x207fe038, 0xe8bd86a0, 0xf00a83f8, 
+    0x2801f938, 0xf996d130, 0x28030000, 0x2805d006, 0x2804d004, 0x7838d002, 0xd1252801, 0xf2404642, 
+    0x46481160, 0xf93bf7e2, 0xf7ea2000, 0xe01bfb6c, 0x0000f996, 0xd0062803, 0xd0042805, 0xd0022804, 
+    0x28017838, 0x4642d110, 0x1161f240, 0xf7e24648, 0x2001f926, 0xfb57f7ea, 0xf6412000, 0x46020300, 
+    0x90004601, 0xfa80f7ec, 0xfaa6f7e3, 0x22024819, 0xf00a2104, 0x2201f8fe, 0x48174603, 0xf00a2102, 
+    0xf996f8ea, 0x28030000, 0x2805d003, 0x2804d001, 0xf001d101, 0x4811f9af, 0x28017800, 0xf7e3d18d, 
+    0xe776fc39, 0x21012200, 0xf2afb510, 0xf005102f, 0x2108fcd1, 0xf0052003, 0x4901fe2f, 0xbd106008, 
+    0x00040e94, 0xf3074084, 0xf2035026, 0x00040235, 0x000401fc, 0xf2039026, 0xf23c801a, 0x00040299, 
+    0x4ff8e92d, 0x8310f8df, 0x8e804604, 0xf8d82889, 0xd0213004, 0xb190dc0c, 0xd1732888, 0x220049bf, 
+    0xf0054618, 0x1d41fe8b, 0x2801d014, 0xe013d107, 0x7fa2f5b0, 0xf5a0d067, 0x38457080, 0x49b7d162, 
+    0x32fff04f, 0x0004f8d8, 0xfe78f005, 0xd1ea1d01, 0xe0e22088, 0xe0e02089, 0xf04f4eb0, 0x17d54220, 
+    0xf9b64628, 0xf7e21000, 0xf996f8aa, 0x46281004, 0xf7e24aab, 0xf9b6f8a4, 0xf8df0000, 0x4baaa2a8, 
+    0xd0172826, 0xd1da2873, 0x0002f996, 0xf9984642, 0x42881000, 0xf99ad105, 0xf9921000, 0x42a95001, 
+    0x7010d0cd, 0x1003f996, 0x1001f888, 0xf007781a, 0xe7c4fda7, 0x46997818, 0xfd0ef007, 0xf8df489b, 
+    0x4d9cb270, 0x28018800, 0xf899d01e, 0x464f0000, 0xfcb4f007, 0xf6402300, 0x22087100, 0xf00a4628, 
+    0xf996f84a, 0x29001003, 0xf04fdda9, 0x17504260, 0xf865f7e2, 0x0003f996, 0x28044a8f, 0x2805d078, 
+    0xe0a0d077, 0xe07ee08a, 0xf00a488c, 0x2301f817, 0x22084607, 0x7100f640, 0x462846aa, 0xf82bf00a, 
+    0x0707f007, 0xd0192f01, 0xd01a2f02, 0x462b2503, 0x22014650, 0xf00a211e, 0x487ef81e, 0x21382203, 
+    0x301e463b, 0xf817f00a, 0x2202487d, 0xf00a2104, 0x2801f820, 0x0a01f04f, 0xe00ad006, 0x23062504, 
+    0x2505e7e6, 0xe7e32307, 0xfdf0f007, 0x4285b2c0, 0xf899d01c, 0x464f0000, 0xfc60f007, 0x23007839, 
+    0x46282202, 0xf8d2f007, 0x46287933, 0x2000f89b, 0xf0077839, 0xf7e3faeb, 0x4869f99f, 0x21042201, 
+    0xa000f8cd, 0x3380f44f, 0xf82ef7e9, 0x0003f996, 0x1000f899, 0xfcc7f007, 0x78004862, 0xd0192801, 
+    0x78004861, 0xd0152801, 0xf0072000, 0x2208fde8, 0x0151485e, 0xffddf009, 0x207370b0, 0x22008030, 
+    0xf8d8494e, 0xf0050004, 0x1d01fd7a, 0xe00fd008, 0xe026e016, 0xf0072001, 0xf886fdd2, 0xe7eca002, 
+    0x1044f240, 0x4945e009, 0x46182200, 0xfd67f005, 0xf47f1d40, 0xf240af4e, 0x86a01045, 0x8ff8e8bd, 
+    0x1000f89b, 0xd10e2903, 0x23007839, 0x20022201, 0xf87cf007, 0x23007839, 0x20042203, 0xfa96f007, 
+    0x7811e057, 0xf99ab161, 0x4b411000, 0xd1042904, 0xc000f893, 0x0f00f1bc, 0x2805d002, 0xe00fd00d, 
+    0x23007839, 0x20032202, 0xf860f007, 0x78392300, 0x461a2003, 0xfa7af007, 0x7810e01d, 0xd0212802, 
+    0xd1022904, 0x28027818, 0x78f0d01c, 0x78392300, 0xf0072201, 0x7933f84b, 0x78f02200, 0xf0077839, 
+    0xf996fa65, 0x28050003, 0x2804d01f, 0x2802d01f, 0x2801d01f, 0x2303d01f, 0x22014628, 0xf009211e, 
+    0xe6bcff5a, 0x230078f0, 0x22027839, 0xf82ef007, 0x78f02300, 0x461a7839, 0xfa48f007, 0x280578f0, 
+    0x2306d001, 0x2307e7e8, 0x2305e7e6, 0x2304e7e4, 0x2302e7e2, 0x2301e7e0, 0x2200e7de, 0xb5102101, 
+    0x3003f2af, 0xfb36f005, 0x20022108, 0xfc94f005, 0x60484901, 0x0000bd10, 0x00040ea0, 0x0004d648, 
+    0xe0000100, 0x00040242, 0x00040320, 0x0004031c, 0x0004057b, 0xf23c8022, 0x000402cb, 0xc23d014e, 
+    0xf3074084, 0x00040235, 0x0004023d, 0xf38f2002, 0x000402ca, 0x4ff0e92d, 0xa408f8df, 0xb0852001, 
+    0x5298f04f, 0x1000f99a, 0xff29f7e1, 0xf8df48fe, 0x7800b3fc, 0x4ffeb3f0, 0x21402206, 0xf0094638, 
+    0xf000ff08, 0x463809ff, 0x21202205, 0xff01f009, 0xf0004cf7, 0x220108ff, 0x2102343c, 0xf0094620, 
+    0xb2c6fef8, 0x22004620, 0xf0092101, 0x2208fef2, 0x4638b2c5, 0xf0090151, 0x220cfeec, 0x48ed4604, 
+    0x0100f241, 0xfee5f009, 0x46384384, 0x21802207, 0xf009b2e4, 0x220bfede, 0x48e64607, 0x0100f640, 
+    0xfed7f009, 0x48e44387, 0xf89bb2f9, 0x78073000, 0xe000a801, 0x9704e006, 0x96004622, 0x0308e880, 
+    0xe00b462b, 0xf89b2201, 0x20001000, 0xe9cd4603, 0xe9cd1001, 0x46020203, 0x90004601, 0x0000f248, 
+    0xfb20f7ee, 0x46112200, 0xfb09f7ee, 0xf88a210f, 0xb0051000, 0x4ff0e8bd, 0xb8fdf7e4, 0x212c48c9, 
+    0xf04fb570, 0x46225498, 0x20017041, 0xfeb7f7e1, 0x680048ca, 0xd01a2812, 0xd01b2813, 0xd01c2815, 
+    0xd01d2816, 0xd01e2817, 0xd01f2818, 0xd0202819, 0xd0212820, 0xd0222821, 0xd0232822, 0xd0242811, 
+    0xd02528ff, 0xd0262801, 0xd0272810, 0x2120e02b, 0xe0254622, 0x46222121, 0x2123e022, 0xe01f4622, 
+    0x46222124, 0x2133e01c, 0xe0194622, 0x46222136, 0x2137e016, 0xe0134622, 0x46222138, 0x2139e010, 
+    0xe00d4622, 0x4622213a, 0x211fe00a, 0xe0074622, 0x4622212f, 0x2130e004, 0xe0014622, 0x4622211e, 
+    0xf7e12001, 0x48a6fe6c, 0xfe28f009, 0x46012200, 0xf7e12001, 0x489efe64, 0xf009380a, 0x4604fe1f, 
+    0x380c489b, 0xfe1af009, 0x48994605, 0xf009380e, 0x4622fe15, 0xe8bd4629, 0xf7e44070, 0xe92db8a9, 
+    0x4e905ffc, 0xf04f2001, 0xf9965298, 0xf7e11001, 0x488ffe46, 0xf009380a, 0x4607fe01, 0x380c488c, 
+    0xfdfcf009, 0x8228f8df, 0xf1a84605, 0x4640080e, 0xfdf4f009, 0x463a4604, 0xf7e44629, 0x220ff889, 
+    0x0100f248, 0xf0094640, 0xf996fe14, 0xf0001002, 0xf8df08ff, 0xf8df9210, 0x2904a210, 0xb20cf8df, 
+    0x2932d00e, 0x2905d05b, 0x5298f04f, 0x211cd076, 0xf7e12001, 0xf1b8fe14, 0xd06e0f01, 0xe115202b, 
+    0xf04f2001, 0xf7e15298, 0x6970fe0a, 0x2141f3c4, 0x61704308, 0x6f85f5b0, 0x4975d020, 0xd1ea4288, 
+    0xd00007a8, 0x49732001, 0x0240f3c5, 0xf0057008, 0xf8990001, 0x43111000, 0x1000f889, 0x3000f89a, 
+    0x43184a6d, 0x0000f88a, 0x3000f89b, 0xe9cd7812, 0x4a6a2300, 0x4a6a7813, 0xe03a7812, 0xf3c44969, 
+    0x4a691082, 0x4d692804, 0x4b6a4f69, 0x2000d009, 0x70107008, 0x70284601, 0x46187038, 0xfd91f009, 
+    0x2001e7b9, 0xf3c47008, 0x70100080, 0x0040f3c4, 0xf0047028, 0x70380001, 0x0c0105e0, 0x2001e7ed, 
+    0x5298f04f, 0xfdbbf7e1, 0xf7ee4620, 0x485afe41, 0x28017800, 0x4850d19f, 0x1000f89b, 0xe9cd7800, 
+    0x484e0100, 0x1000f899, 0x484d7803, 0xf89a7802, 0xf7ee0000, 0xe78eff89, 0xe0a6e000, 0xf7e12001, 
+    0x69b1fd9e, 0xf5a1483d, 0x3a974258, 0x2210d005, 0x4368f5a1, 0xd0433b6d, 0x4a48e049, 0x0103f005, 
+    0x141ff361, 0xf3c780b4, 0x70113100, 0xf3c521ff, 0xf5b2028b, 0xd0046f80, 0x7f60f415, 0x2111d000, 
+    0x2c10e081, 0x2c20d015, 0xb194d013, 0xd0152c01, 0xd0152c02, 0xd0152c03, 0xd0152c04, 0xd0152c05, 
+    0xd0152c06, 0xd0152c07, 0xd0152c08, 0xd0152c09, 0x2112e069, 0x200f6001, 0xe0197030, 0xe0622113, 
+    0xe0602115, 0xe05e2116, 0xe05c2117, 0xe05a2118, 0xe0582119, 0xe0562120, 0xe0542121, 0xe0522122, 
+    0x1145f3c4, 0xd1022902, 0x07090861, 0x6002d04a, 0x010bf3c7, 0xf0094822, 0x4821fd04, 0x1c802100, 
+    0xfcfff009, 0xb2818b30, 0x1d00481d, 0xfcf9f009, 0x220069b0, 0xf3c021ff, 0x48194307, 0xf0091d80, 
+    0xe718fd0a, 0x00040ea8, 0x00040575, 0x000402d0, 0xf38e0040, 0xf38f0008, 0x000402cc, 0x000401f0, 
+    0xf38fffd0, 0x0004057f, 0x0004057e, 0x00040571, 0x00fa073e, 0x00040578, 0x00040572, 0x0004057d, 
+    0x0004057c, 0x00040569, 0x0004056b, 0x0004056c, 0x0004056d, 0xf23c8026, 0x00040576, 0x000402b1, 
+    0xf203515c, 0x60012101, 0x2002e7b2, 0xe8bd7070, 0xe92d9ffc, 0xf04f47fc, 0x46525a98, 0x20014dfe, 
+    0x1001f995, 0xfcebf7e1, 0xf00948fc, 0x4604fca7, 0x1e8048fa, 0xfca2f009, 0x93e0f8df, 0xf1a94606, 
+    0x46480904, 0xfc9af009, 0x46314622, 0xff30f7e3, 0xf248220f, 0x46480100, 0xfcbbf009, 0x08fff000, 
+    0x0100f242, 0x4648220d, 0xfcb3f009, 0xf240b2c7, 0x220071ff, 0xf0094648, 0x2f01fcac, 0xd108b2c0, 
+    0xd0122809, 0x280b2703, 0x2805d041, 0x2806d054, 0x2129d05e, 0x20014652, 0xfcb1f7e1, 0x0f01f1b8, 
+    0x202bd001, 0xe8bd7068, 0x212787fc, 0x20014652, 0xfca5f7e1, 0x463148da, 0xfc63f009, 0x50c0f414, 
+    0x2001d000, 0x4ed849d7, 0x70084fd8, 0x20c0f3c4, 0x703049d7, 0x3000f3c4, 0xf3c47038, 0x700800c0, 
+    0xea00200e, 0x48d31154, 0x48d37001, 0xfc49f009, 0x48d349d2, 0x78007809, 0x0100e9cd, 0x783148d1, 
+    0x48d17803, 0x78387802, 0xfe5ef7ee, 0x2128e7c6, 0x20014652, 0xfc73f7e1, 0x4accb2e0, 0xea4649cc, 
+    0x61284000, 0xd1024290, 0x2000f3c4, 0x2000e000, 0x20327008, 0xe015706f, 0x46522125, 0xf7e12001, 
+    0x0370fc5e, 0x0084ea40, 0x20046168, 0xe009706f, 0x46522126, 0xf7e12001, 0xea44fc52, 0x61a820c6, 
+    0x706f2005, 0xe79970a8, 0xf04f49ab, 0x4ab930ff, 0x70487008, 0x20007088, 0x61486188, 0x21106108, 
+    0x49b56011, 0x49b57008, 0x49b57008, 0x49b57008, 0x49b57008, 0x49a67008, 0x49b47008, 0x49a77008, 
+    0x49a77008, 0x49aa7008, 0x49b17008, 0x499d7008, 0x49a47008, 0x49a47008, 0x499c7008, 0x499a7008, 
+    0x49ac7008, 0x47707008, 0xf7ffb57c, 0x48aaffcd, 0xf0092108, 0x48a9fbd6, 0x48a97801, 0xf7ee7800, 
+    0x48a8fefa, 0x0500f241, 0x340a4c8c, 0x2a988802, 0x2a88d00e, 0x2aa8d00c, 0x2ab8d00a, 0x2a94d008, 
+    0x2a84d010, 0x2aa4d00e, 0x2ab4d00c, 0xe00fd00a, 0x46292300, 0x4620220c, 0xfbcdf009, 0x23002208, 
+    0xe0020151, 0x46292300, 0x4620220c, 0xfbc3f009, 0x46202300, 0x21042202, 0xfbbdf009, 0x23004877, 
+    0x461a2101, 0xf0093042, 0xf7eefbb6, 0x2000fbeb, 0x46039000, 0x46014602, 0xf7ee9001, 0x4870fdb5, 
+    0x30422100, 0xfb8df009, 0x21004873, 0xf009304a, 0x4871fb88, 0x304c2100, 0xfb83f009, 0x2100486e, 
+    0xf009304e, 0x486cfb7e, 0x21ff2300, 0x3050461a, 0xfb91f009, 0xf7e82001, 0x2011fc30, 0xfc2df7e8, 
+    0xf7e82012, 0x2002fc2a, 0xf933f7ee, 0x22024876, 0xf0092104, 0x2401fb8e, 0xd1092801, 0x22014873, 
+    0x70044973, 0xf7e82004, 0x200bfb1b, 0xfc15f7e8, 0x201b4970, 0x220c2300, 0x46297008, 0x7044484e, 
+    0x1d804869, 0xfb67f009, 0x2102b002, 0xe8bd2001, 0xf04f4070, 0xf7e14270, 0xe92dbb82, 0x4c465ff0, 
+    0x8e804605, 0x0901f04f, 0x28f0b130, 0x28f1d014, 0xf8c4d134, 0xe01a900c, 0xff26f7ff, 0xf04f493e, 
+    0x68a032ff, 0xf005311c, 0x60e0f929, 0xd0011d00, 0xe00868e0, 0xe02020f0, 0x22004937, 0x311c68a0, 
+    0xf91cf005, 0x1d4160e0, 0x2801d016, 0x4f32d1e6, 0x4620f04f, 0x46322001, 0xf9b7371c, 0xf7e11000, 
+    0xf9b7fb4e, 0x293a1000, 0x293bd00a, 0x2001d00e, 0xf7e14632, 0xe7d1fb44, 0x86a820f1, 0x9ff0e8bd, 
+    0xff22f7ff, 0x20017862, 0xe1ac7821, 0x78004842, 0xd00c2801, 0x0001f994, 0xd00a2801, 0xd00b2802, 
+    0xd00c2803, 0xd00d2806, 0xd00e2807, 0xf884e00f, 0xf0009001, 0xe00afa41, 0xfe2bf7ff, 0xf7ffe007, 
+    0xe004fcce, 0xfa01f000, 0xf000e001, 0x7860f9c7, 0xd101282b, 0xfc52f7ff, 0x1000f994, 0x5b98f04f, 
+    0xd068290d, 0xd077290e, 0xd0712931, 0xf24a2934, 0xd06e0605, 0xd06d2935, 0xa020f8df, 0xf1aa290f, 
+    0xd0680a0a, 0x2910262d, 0xf8dfd078, 0x29198090, 0x0701f242, 0xe043d073, 0x00040ea8, 0xf38e0036, 
+    0xf38f0034, 0x0004057a, 0x0004057f, 0x0004057e, 0x00040573, 0x00040276, 0xf2035112, 0x00040571, 
+    0x00040572, 0x0004057d, 0x0004057c, 0x002901d4, 0x00040576, 0x000401f0, 0x0004056b, 0x0004056c, 
+    0x0004056d, 0x00040569, 0x0004056f, 0x00040570, 0x00040578, 0x0004058a, 0xf38f228a, 0x000404fd, 
+    0x000404fc, 0x000404fe, 0xf2039026, 0x00040574, 0x684ee180, 0x000401fd, 0x0004023e, 0xf38fffce, 
+    0xd07d291a, 0xd07c2911, 0xd07b2912, 0xd07a2913, 0xd079292d, 0x2001e108, 0xf7e1465a, 0x2200faa0, 
+    0x0009f24a, 0xf7ed4611, 0x2034feda, 0xe003e014, 0xe018e016, 0xe03ee024, 0x465a2001, 0xfa8ff7e1, 
+    0x212948fb, 0xea417800, 0xf2402200, 0xf24a11d4, 0xf7ed000b, 0x2031fec4, 0xe0507020, 0xe05ee03b, 
+    0xfb48f7ff, 0x2001e0da, 0xf7e1465a, 0xf240fa78, 0xf24012cf, 0x463071d0, 0xfeb1f7ed, 0xe7eb2035, 
+    0x465a2001, 0xfa6bf7e1, 0x20194fea, 0x70202207, 0x46382180, 0xfa4df009, 0x46062208, 0x01514638, 
+    0xfa47f009, 0x0040ea46, 0xf248b281, 0x22004000, 0xfe95f7ed, 0x2001e023, 0xf7e1465a, 0x4631fa50, 
+    0xf0094650, 0x2100fa0e, 0x120af240, 0xf7ed4630, 0x2010fe86, 0x2001e7c0, 0xf7e1465a, 0x48d6fa40, 
+    0x0200f04f, 0x46114fd5, 0x28017800, 0x2000d010, 0xfe75f7ed, 0x46382100, 0xf9f3f009, 0xe0047026, 
+    0xe047e02b, 0xe056e049, 0xf7e3e06d, 0xe085fc64, 0x1006f240, 0xfe63f7ed, 0x3100f248, 0x2001e7eb, 
+    0xf7e1465a, 0x7860fa1c, 0xd103282c, 0x680048c4, 0xd0072801, 0xf24a2297, 0x211b0006, 0xfe4ff7ed, 
+    0xe789201a, 0x46382200, 0xf7ed4611, 0x4639fe48, 0xf0094640, 0x7026f9c6, 0x2001e063, 0xf7e1465a, 
+    0x48b8f9fe, 0x0108f248, 0x0800f241, 0xf4008800, 0xea41707e, 0x48b40640, 0x48b07807, 0xf0091f80, 
+    0xf367f9ad, 0x4641301f, 0x4630b282, 0xfe27f7ed, 0xe761200e, 0xf868f000, 0x2001e040, 0xf7e1465a, 
+    0xf24af9de, 0x4646010a, 0xf0094640, 0x2013f99a, 0x46307020, 0x2001e00f, 0xf7e1465a, 0x489df9d0, 
+    0xf0093038, 0xf000f98b, 0x4647010e, 0xf0094640, 0x4638f988, 0xf0097026, 0x2200f981, 0x20014601, 
+    0xf9bdf7e1, 0x2001e01a, 0xf7e1465a, 0x2100f9b8, 0x2000f44f, 0xf966f7e8, 0x2100488e, 0xf0093812, 
+    0x488cf970, 0x38102100, 0xf96bf009, 0x46504639, 0xf967f009, 0x46404639, 0xf963f009, 0x282d7820, 
+    0x7860d102, 0xd003282c, 0x20027862, 0xe00a7821, 0x20004986, 0x7008465a, 0x2001211d, 0xf98ff7e1, 
+    0x20037862, 0xf7e37821, 0xe617fa79, 0x21012200, 0xf2afb510, 0xf00430f9, 0x2108fd5d, 0xf0042004, 
+    0x497bfebb, 0xbd106088, 0x4c79b570, 0xf04f2001, 0xf9945298, 0xf7e11000, 0x78e2f972, 0xb1324d75, 
+    0xf2482a01, 0xd0040100, 0xd0062a02, 0xf24ae00a, 0x46280108, 0xf925f009, 0x4628e004, 0xf921f009, 
+    0x70202012, 0xf0094628, 0x2200f919, 0x20014601, 0xf955f7e1, 0x1c4078e0, 0xbd7070e0, 0x41f0e92d, 
+    0xf04f4c63, 0x20015698, 0xf9944632, 0xf7e11001, 0x4f60f946, 0xf248220f, 0x1cbf0100, 0xf0094638, 
+    0x2200f928, 0xf2404605, 0x463871ff, 0xf921f009, 0x46384680, 0xf8f2f009, 0x46012200, 0xf7e12001, 
+    0xf994f92e, 0x29081002, 0x2001d109, 0xf7e14632, 0x4851f926, 0xf0094641, 0x2006f8e4, 0x2d007060, 
+    0x202bd101, 0xe8bd7060, 0xe92d81f0, 0x4c4841f0, 0xf04f2001, 0xf9945298, 0xf7e11001, 0x4f45f910, 
+    0xf248220f, 0x1cbf0100, 0xf0094638, 0x220df8f2, 0xf2424680, 0x46380100, 0xf8ebf009, 0x46062200, 
+    0x71fff240, 0xf0094638, 0x4605f8e4, 0xf0094638, 0x2200f8b5, 0x20014601, 0xf8f1f7e1, 0xd1052e01, 
+    0xd1032d0a, 0x70a02008, 0x70602007, 0x0f00f1b8, 0x202bd1c9, 0xe7c67060, 0x41f0e92d, 0xf04f4c2c, 
+    0x20015898, 0xf9944642, 0xf7e11001, 0x4f21f8d8, 0x46383f1a, 0xf892f009, 0x46052200, 0x20014601, 
+    0xf8cdf7e1, 0x26004825, 0xf241220c, 0x70060100, 0xf0094638, 0xb130f8ae, 0xf8d4f7ee, 0x7020200d, 
+    0x70602002, 0x220fe016, 0x0100f248, 0xf0094638, 0xb128f8a0, 0x70202011, 0x70602006, 0xe00970e6, 
+    0x7020202d, 0x7060202b, 0x212eb925, 0x20014642, 0xf8a5f7e1, 0x20014912, 0x70082200, 0x49112004, 
+    0xf81ef7e8, 0x41f0e8bd, 0xf7e8200b, 0x0000b916, 0x00040575, 0xf38e0040, 0x00040568, 0xf23c8024, 
+    0x000401f0, 0x000404fe, 0x000402b0, 0x000401fd, 0x00040ea8, 0xf38fffce, 0xf2035112, 0x0004059e, 
+    0x00040574, 0x684ee180, 0x483fb570, 0xf009255c, 0x4604f835, 0x1e80483c, 0xf830f009, 0xf4044a3b, 
+    0x8011717f, 0x0103f004, 0x80114a39, 0x5254f5a0, 0xf0243a90, 0xd11e0103, 0x40a0f5a1, 0xd02c3890, 
+    0xd02a1f00, 0xd0281f00, 0x4fa1f5b1, 0x3014d025, 0x1f00d023, 0x3818d021, 0x1f00d01f, 0x1f00d01d, 
+    0x3808d01b, 0x3820d019, 0x3820d017, 0x303cd015, 0x1f00d013, 0x2000d011, 0x4826b188, 0x21e02205, 
+    0xf827f009, 0x22004924, 0x70084c24, 0x46202101, 0xf81ff009, 0xd00b2801, 0x2001e010, 0xf7fae7ec, 
+    0x481cf8f1, 0x31b0f64b, 0xf0083082, 0xe7feffea, 0x46202301, 0x21102204, 0xfffdf008, 0xf64f4817, 
+    0x300871ff, 0xffddf008, 0x46202301, 0x21042202, 0xfff1f008, 0x46202301, 0x461a2102, 0xffebf008, 
+    0x6828490f, 0xf6426008, 0x480a21a2, 0xf0083818, 0x4808ffc8, 0x0102f244, 0xf008381a, 0xe8bdffc2, 
+    0xf7f94070, 0x0000bf8a, 0xf2020006, 0x000404fe, 0x00040500, 0xf23c8038, 0x000401ec, 0xf23c8318, 
+    0x000404f8, 0x4d1eb570, 0x8e804604, 0x285eb120, 0x285fd00d, 0xe014d125, 0xf04f4919, 0x682832ff, 
+    0xf0041d09, 0x1d01fd9b, 0x205ed107, 0x4914e018, 0x68282200, 0xf0041d09, 0x1d41fd91, 0x2801d00f, 
+    0x4e0fd1ea, 0x88301d36, 0xd1e52862, 0x2102480d, 0xff87f008, 0x0002f9b6, 0xf803f7e1, 0x205fe7dc, 
+    0xbd7086a0, 0x21012200, 0xf2afb510, 0xf0040067, 0x2108fb91, 0xf0042003, 0x4901fcef, 0xbd106008, 
+    0x00040ecc, 0xf23c806e, 0x41f0e92d, 0x22014dff, 0x46282106, 0xff8df008, 0x1cb74efd, 0xb3201eb4, 
+    0x46282201, 0xf0082106, 0x2801ff84, 0x2201d029, 0x21064628, 0xff7df008, 0xd1252802, 0x0100f243, 
+    0xf0084630, 0x219cff4e, 0xf0084638, 0x2301ff4a, 0x22004620, 0xf008210f, 0x4620ff5e, 0x41f0e8bd, 
+    0x22042301, 0xf0082110, 0xf240bf56, 0x46307507, 0xf0084629, 0x4629ff36, 0xf0084638, 0x230fff32, 
+    0xf240e7e6, 0xe7db1100, 0x81f0e8bd, 0x4604b510, 0xffbaf7ff, 0x20012100, 0xf80ef7e9, 0xb2a348dc, 
+    0x21012200, 0xf0083824, 0xe8bdff36, 0x20034010, 0xb838f7e9, 0x4668b51f, 0xfe45f7e9, 0xb2819800, 
+    0xf00848d4, 0x9800ff0e, 0x48d20c01, 0xf0081c80, 0x9801ff08, 0x48cfb281, 0xf0081d00, 0x9801ff02, 
+    0x48cc0c01, 0xf0081d80, 0x9802fefc, 0x48c9b281, 0xf0083008, 0x9802fef6, 0x48c60c01, 0xf008300a, 
+    0x9803fef0, 0x48c3b281, 0xf008300c, 0x9803feea, 0x48c00c01, 0xf008300e, 0xbd1ffee4, 0x4cbeb570, 
+    0xf04f2001, 0xf24052a0, 0x06051103, 0x462870e0, 0xff15f7e0, 0x11f4f240, 0xf7e04628, 0xf64efec2, 
+    0x462861ee, 0xfeacf7e0, 0x462849b4, 0xfea8f7e0, 0x48b32300, 0x461a2101, 0xfeddf008, 0x200049b1, 
+    0x70084ab1, 0x7f201369, 0xf0001c40, 0xeb000007, 0xeb021000, 0x60810080, 0xf7e72002, 0xe8bdff7f, 
+    0x20034070, 0xbf7af7e7, 0x4ff0e92d, 0x49a74689, 0x469b4690, 0xf04f2201, 0x46560a00, 0x02536809, 
+    0xf8c88809, 0xf8aba000, 0xeb023000, 0x9a090151, 0xfc81fa0f, 0xa000f8a2, 0x2500e055, 0xeb06e02c, 
+    0xf1be0e05, 0xd4040f02, 0x018eeb00, 0x7c08f851, 0x2700e000, 0x46544652, 0x33fff04f, 0xd40618e9, 
+    0xda044561, 0x0103eb0e, 0x1021f850, 0x2100e000, 0xda03428f, 0x463a4614, 0xe007460f, 0xda02428a, 
+    0x460a4614, 0x428ce002, 0x460cda00, 0x2b031c5b, 0x1c6ddbe4, 0x402ef849, 0xdbd04565, 0xe01f2300, 
+    0xf8d818f1, 0xf8505000, 0xf8594021, 0x1a611021, 0x1a6d17ca, 0x0402eb7a, 0x2a00da11, 0x2100da01, 
+    0xf04fe007, 0x24004580, 0x41941a6d, 0xf04fda01, 0xf8c85100, 0xf8ab1000, 0x99093000, 0x1c5b800e, 
+    0xdbdd4563, 0xebb64466, 0xdba60f8c, 0x8ff0e8bd, 0x43f8e92d, 0x460f2400, 0x4616461d, 0xf04f9400, 
+    0xf8dd52a0, 0xf9b08020, 0xf04f1000, 0xf7e07080, 0x4867fe66, 0x48607004, 0x710470c4, 0x68004865, 
+    0x4865b178, 0x28017800, 0x2100d008, 0xf201485c, 0x30083102, 0xfe15f008, 0x83f8e8bd, 0x7110f242, 
+    0x703ce7f4, 0x30fff04f, 0xf8c86030, 0x0c010000, 0x602c4850, 0xf0081f80, 0x4c4efe04, 0x23002208, 
+    0x01513c1c, 0xf0084620, 0x4d4afe16, 0x0100f44f, 0x35384f52, 0x138e9100, 0x2104e00c, 0x4668462a, 
+    0xfe75f7e7, 0xd00c2801, 0x46312301, 0x46202209, 0xfe01f008, 0x46382206, 0xf0082140, 0x2800fe0a, 
+    0x483bd1eb, 0x22042300, 0x1e802110, 0xfdf3f008, 0xe92de7c2, 0x25004ff8, 0x4699460e, 0xe9dd4690, 
+    0x9500ab0a, 0x52a0f04f, 0x1000f9b0, 0x7080f04f, 0xfe05f7e0, 0x4c30483a, 0x483a6005, 0xf9947005, 
+    0x1c400005, 0xf8dfd114, 0x2100c0e0, 0xe0dcf8df, 0xeb0c2000, 0xeb0e1741, 0xf8371241, 0xf8223010, 
+    0x1c403010, 0xdbf82810, 0x29041c49, 0x7165dbf0, 0x70054827, 0x712570e5, 0x5000f8c8, 0x5000f8c9, 
+    0x5000f8ca, 0x5000f8cb, 0x28007960, 0x7860d17e, 0xd07c2800, 0x0002f994, 0x28007030, 0x4d15d076, 
+    0x0000f44f, 0xf2404e13, 0x3d1c2800, 0x36384f1b, 0xe00c9000, 0x46322105, 0xf7e74668, 0x2801fe08, 
+    0x2301d00c, 0x22094641, 0xf0084628, 0x2206fd94, 0x21404638, 0xfd9df008, 0xd1eb2800, 0x23014804, 
+    0xf2402200, 0x303036ff, 0xe0214631, 0xf2020126, 0xf2035252, 0xf2035142, 0x00040ed8, 0xdcba01f5, 
+    0xf23c80b2, 0x00040286, 0x00041698, 0x00040598, 0x00040285, 0x00057f70, 0x00040502, 0xf203502c, 
+    0x00040560, 0x00040564, 0x00041408, 0x00041508, 0xfd61f008, 0x230f48ff, 0x46312200, 0xfd5bf008, 
+    0xbb0888e0, 0xf7e72002, 0x2208fdf8, 0x23014628, 0xf0080151, 0x2100fd50, 0xf7e72040, 0x2003fd23, 
+    0xfdebf7e7, 0x20402100, 0xfd1cf7e7, 0x20082100, 0xff3cf7e9, 0xf7e92001, 0x48eeff8a, 0x22042300, 
+    0x38302110, 0xfd37f008, 0xe0012207, 0xe037e033, 0x46082101, 0xfeedf7e9, 0x218c48e7, 0xfd11f008, 
+    0x23ff48e4, 0x46312200, 0xf0083816, 0x48e1fd24, 0x2200233f, 0x11fff240, 0xf0081e80, 0x48dffd1c, 
+    0x28017800, 0xf644d019, 0x48dd6120, 0xeb008800, 0xebc20240, 0xeb0110c0, 0x8ba100c0, 0xf5a04408, 
+    0xb281707a, 0x301448d4, 0xfcebf008, 0xb2818ba0, 0xf00848d4, 0xe8bdfce6, 0xf2478ff8, 0xe7e45130, 
+    0x70352141, 0x52a0f04f, 0x7080f04f, 0xfd17f7e0, 0xe92de7f1, 0xb0834fff, 0x20054607, 0x0b00f04f, 
+    0xfc78f7e7, 0x60e04cc8, 0x780048c8, 0xd0372801, 0xd0352802, 0xf00848c6, 0x4605fcc1, 0x1c8048c4, 
+    0xfcbcf008, 0x4000ea45, 0x20006160, 0x636070e0, 0x90004680, 0xf2402100, 0xf7e74000, 0x48bdfca3, 
+    0xb3287800, 0x20004cb8, 0x7580f04f, 0x11f4f240, 0x462870e0, 0xfc95f7e0, 0x462849b7, 0xfc80f7e0, 
+    0x462849b6, 0xfc7cf7e0, 0x1c407f20, 0x0007f000, 0x1100eb00, 0xeb0048b2, 0x68810081, 0xe1843110, 
+    0x1f0048ab, 0xfc8af008, 0x48a94605, 0xe7c71e80, 0xf7e72005, 0x4ca4fc2f, 0x48a46120, 0x28017800, 
+    0x2802d013, 0x48a2d011, 0xfc78f008, 0x48a04605, 0xf0081c80, 0xea45fc73, 0x61a04000, 0x0103e9d4, 
+    0xd90a4281, 0x1c091a41, 0x4899e008, 0xf0081f00, 0x4605fc65, 0x1e804896, 0x1a41e7eb, 0xf04f4a99, 
+    0xf04f0004, 0xf04f0a14, 0xf992091e, 0x2a052000, 0x2a04d002, 0xe009d005, 0xf04f2005, 0x22140a0f, 
+    0x2006e003, 0x0a0af04f, 0x4691220f, 0x488640c1, 0xe9d09101, 0x42810105, 0x1a0cd202, 0xe0001c24, 
+    0xf5b41a0c, 0xd3013f80, 0x3480f5a4, 0x44a09801, 0xfc8cf00a, 0x460e4605, 0xf00a4620, 0x4b82fc87, 
+    0xf00a2200, 0x462afcd3, 0xf00a4633, 0x4605fab3, 0x460e487e, 0x2300e9d0, 0xf00a4628, 0x4872fdc5, 
+    0xd20d6b41, 0x63411c49, 0x46314879, 0x2300e9d0, 0xf00a4628, 0xd207fdb9, 0x6b41486b, 0xe0021c49, 
+    0xda012900, 0x63412100, 0x46594867, 0x45836b40, 0x4608dd00, 0xb1274683, 0xd30245d0, 0x200b4962, 
+    0x1c786348, 0x45c8d004, 0x495fd302, 0x6348200b, 0x48674631, 0x2300e9d0, 0xf00a4628, 0xd303fd95, 
+    0x6b414859, 0xdd7c290a, 0x915cf8df, 0xf9992101, 0x28020000, 0x2803d008, 0xb3a7d006, 0xf889484f, 
+    0x78001003, 0xe03bb380, 0x9805b36f, 0x7a80f04f, 0xf2407001, 0x465011f4, 0xfbc3f7e0, 0x41caf64a, 
+    0xf7e04650, 0x4641fbad, 0xf7e04650, 0x4b51fba9, 0x46282200, 0xf00a4631, 0xf00afc69, 0x4601fbd3, 
+    0xf7e04650, 0xf8d9fb9d, 0x46501034, 0xfb98f7e0, 0xf9909805, 0x46501000, 0xfb92f7e0, 0x4650493f, 
+    0xfb8ef7e0, 0xe009e00c, 0xf44fe7ff, 0xf6403000, 0xf7e00103, 0xf7ecfb96, 0xe001fb28, 0x70019806, 
+    0x7a80f04f, 0x1bf4f240, 0x46594650, 0xfb89f7e0, 0x20aaf64a, 0x46501839, 0xfb72f7e0, 0xf9909805, 
+    0x46501000, 0xfb6cf7e0, 0xf9909806, 0x46501000, 0xfb66f7e0, 0xf0084830, 0x4601fb81, 0xf7e04650, 
+    0x482bfb5f, 0xe9d04631, 0x46282300, 0xfd1cf00a, 0x4621d20a, 0x46504654, 0xfb52f7e0, 0x46209901, 
+    0xe089e000, 0xfb4cf7e0, 0x1010f8d9, 0x4655464c, 0xf7e04650, 0x68e1fb45, 0xf7e04628, 0x4e17fb41, 
+    0x46314628, 0xfb3cf7e0, 0x01c0f242, 0xf7e00648, 0x4810fb54, 0xb3887800, 0x70e12100, 0xf994b13f, 
+    0x28020000, 0x2803d001, 0x9805d101, 0x46597001, 0xe0244628, 0xf2035280, 0xf23c80a6, 0x00040502, 
+    0x00057f78, 0xf203513e, 0x00040ed8, 0x0004057b, 0xf2036116, 0x00040285, 0x0bbbdead, 0xdcba01f5, 
+    0x00041698, 0x00040242, 0x40140000, 0x00040288, 0x00040290, 0x40c38800, 0xf203502c, 0xf7e0e01d, 
+    0xf64afb10, 0x462821bb, 0xfafaf7e0, 0x46284631, 0xfaf6f7e0, 0x1c407f20, 0x0007f000, 0x1100eb00, 
+    0xeb0048fe, 0x68810081, 0x60813120, 0x980449fc, 0xf9946008, 0xb0070003, 0xf994e4c8, 0x28020000, 
+    0x2803d004, 0x2003d002, 0xfbc8f7e7, 0x46284659, 0xfae7f7e0, 0x31bbf64b, 0xf7e04628, 0x4641fad1, 
+    0xf7e04628, 0x6b61facd, 0xf7e04628, 0x4631fac9, 0xf7e04628, 0xe009fac5, 0x61416981, 0x60c16901, 
+    0x1c409800, 0x28329000, 0xae24f4ff, 0xf04fb1c7, 0xf2407480, 0x462011f4, 0xfac3f7e0, 0x31bdf64b, 
+    0xf7e04620, 0x4641faad, 0xf7e04620, 0x49ddfaa9, 0x6b494620, 0xfaa4f7e0, 0x462049db, 0xfaa0f7e0, 
+    0xf99048d8, 0xe7b60003, 0x4ffee92d, 0xf04f4cd4, 0xf04f0a00, 0x468052a0, 0xa000f88d, 0xa004f88d, 
+    0x1000f9b0, 0x7080f04f, 0xf7e06826, 0x4dcdfae8, 0xb12078e8, 0xf8c52000, 0xe8bda030, 0x68218ffe, 
+    0x46a32001, 0x21c0f421, 0x63286021, 0xff03f7e7, 0x20009002, 0xfed8f7e7, 0x466a2000, 0x4631ab01, 
+    0xfdb7f7ff, 0x63282002, 0x780048c0, 0xf04fb190, 0xf2407480, 0x462011f4, 0xa030f8c5, 0xfa71f7e0, 
+    0x71fff64f, 0xf7e04620, 0x49b7fa5b, 0xf7e04620, 0xe19dfa57, 0x63282003, 0x62e82096, 0x0004f89d, 
+    0xd07d2800, 0x63282005, 0x28007828, 0x2006d079, 0x090af04f, 0x466aab01, 0x63284631, 0xf7ff2001, 
+    0x48aafd88, 0xb1107800, 0xa030f8c5, 0x2007e180, 0x48a76328, 0x0000f990, 0xd0022805, 0xd1012804, 
+    0x46812003, 0x0000f89d, 0xd07d2800, 0x7480f04f, 0x11f4f240, 0xf7e04620, 0xf649fa34, 0x46200176, 
+    0xfa1ef7e0, 0x46204998, 0xfa1af7e0, 0xe07e2400, 0x78004898, 0xd0142801, 0xd0122802, 0xf0084896, 
+    0x4607fa2d, 0x1c804894, 0xfa28f008, 0x4000ea47, 0x696961a8, 0x45491a41, 0x4890d313, 0xb1407800, 
+    0x488de00f, 0xf0081f00, 0x4607fa19, 0x1e80488a, 0xf44fe7ea, 0xf6403000, 0xf7e00103, 0xf7ecfa02, 
+    0x6ae8f994, 0x42841f40, 0xf04fd317, 0xf2407780, 0x463811f4, 0xf9f5f7e0, 0x7189f246, 0xf7e04638, 
+    0x4621f9df, 0xf7e04638, 0x69a9f9db, 0xf7e04638, 0x4975f9d7, 0xf7e04638, 0x6ae8f9d3, 0xe0011e40, 
+    0xe05ae058, 0xd1014284, 0x70e82001, 0xf2402100, 0xf7e74000, 0x486df9d7, 0xb3287800, 0x7780f04f, 
+    0xa003f885, 0xf2404654, 0x463811f4, 0xa000f88d, 0xf9c7f7e0, 0x4638496a, 0xf9b2f7e0, 0x46384962, 
+    0xf9aef7e0, 0xe0007f28, 0x1c40e018, 0x0007f000, 0x1100eb00, 0xeb004859, 0x68810081, 0x60813130, 
+    0x6000f8cb, 0xe0e3632c, 0x1c6469a8, 0x6ae86168, 0xf4ff4284, 0x2003af7d, 0xfa80f7e7, 0xb1e078e8, 
+    0x7480f04f, 0x11f4f240, 0xf7e04620, 0xf64cf99a, 0x462041cc, 0xf984f7e0, 0x4620494b, 0xf980f7e0, 
+    0xb1187828, 0xf8a82143, 0xe0061000, 0xf8a82009, 0xe0020000, 0xf7e79802, 0x2008fdd7, 0x78e86328, 
+    0xd1792800, 0x28007828, 0x9802d076, 0xfdccf7e7, 0x78004842, 0xf7ecb908, 0x2002fadd, 0xf8854657, 
+    0xf7e7a004, 0xf8dffa3a, 0x220890fc, 0x6328200a, 0x46482301, 0xf0080151, 0x2009f98e, 0xf44f6328, 
+    0xe0120400, 0x2c001e64, 0x4c37dc09, 0xf0084620, 0xf040f95f, 0x46200140, 0xf95df008, 0x2301e00d, 
+    0x22094648, 0xf0080259, 0x482ef976, 0x21402206, 0xf00838fa, 0x2800f97e, 0x482cd1e4, 0xf94ef008, 
+    0xf004b204, 0x1e490101, 0x0002f004, 0xd0724308, 0x70e82001, 0xf7e72002, 0xf04ffa11, 0xf2407980, 
+    0x464811f4, 0xf92df7e0, 0x46484921, 0xf918f7e0, 0x38fa481c, 0xf932f008, 0x4104ea40, 0xf7e04648, 
+    0x4911f90f, 0xf7e04648, 0x4810f90b, 0xb1a07800, 0x11f4f240, 0x4648464c, 0xf7e070ef, 0x4915f912, 
+    0xf7e04620, 0x4908f8fd, 0xf7e04620, 0x7f28f8f9, 0xf0001c40, 0xe01f0007, 0xe026e03d, 0x00041698, 
+    0x00057ffc, 0x00040ed8, 0xdcba01f5, 0x00040285, 0x00040242, 0x0004057b, 0xf2036116, 0x00040502, 
+    0x0ddddead, 0xf2035126, 0xf000306c, 0xf2060040, 0x00011104, 0x0eeedead, 0x1100eb00, 0xeb0048fe, 
+    0x68810081, 0x60813130, 0x78e8e00f, 0x7828b198, 0x2043b118, 0x0000f8a8, 0x2109e002, 0x1000f8a8, 
+    0xf7e7200b, 0x48f5f9ab, 0xf8cb7007, 0x632f6000, 0x0003f995, 0xf8cbe631, 0xe6756000, 0x5ffce92d, 
+    0xf2404def, 0x4eef49dd, 0x8e814604, 0x4bcaf240, 0xa3b4f8df, 0x48bcf240, 0x45496bab, 0xf2a16837, 
+    0xd06a40dd, 0x4559dc2e, 0x40caf2a1, 0xdc12d071, 0xf2a14541, 0xd06d40bc, 0xb311dc06, 0x0132f110, 
+    0x2901d06b, 0xe072d168, 0xd0562801, 0xd07d2808, 0xd1612809, 0x280ce051, 0xdc06d079, 0xd04c2801, 
+    0xd0752806, 0xd1572807, 0x280de047, 0x2812d045, 0x49d3d152, 0x46382200, 0xf003313c, 0x1d40fe60, 
+    0xe03ad067, 0xd0382818, 0x280cdc20, 0xdc0ed035, 0xd07d2805, 0xd0302806, 0xd13d280b, 0x220049c8, 
+    0x313c4638, 0xfe4bf003, 0xd0721d40, 0x2811e025, 0x2812d070, 0x2817d021, 0x49c1d12e, 0x46382200, 
+    0xf003313c, 0x1d40fe3c, 0xe016d070, 0xd0142826, 0x281ddc0f, 0x281ed06b, 0x2825d00f, 0x49b8d11c, 
+    0xf8da2200, 0x313c0000, 0xfe29f003, 0xd07d1d40, 0x2829e003, 0x282ad07b, 0x49b1d10e, 0x32fff04f, 
+    0x313c6ba8, 0xfe4af003, 0xd10c1d01, 0x408af240, 0xe0dfe1e0, 0xe000e09e, 0x49a9e090, 0x46182200, 
+    0xf003313c, 0x1d41fe3b, 0x2801d03d, 0x4fa4d1e5, 0xf1a7373c, 0xf9b70114, 0x280f0000, 0x283fd038, 
+    0x2843d040, 0x2844d07c, 0xe003d07b, 0xe0fee0a3, 0xe119e0dd, 0xd0752845, 0xd0742846, 0xd0732848, 
+    0xd0722849, 0xd071284a, 0xd070284c, 0xd06f284d, 0xd06e2847, 0xd1c0283e, 0x1000f995, 0xf7ff4638, 
+    0x2800fd53, 0x8838d0b9, 0x0200f04f, 0xe0022809, 0xe139e120, 0x4639e14e, 0x6ba8d07b, 0xfdcff003, 
+    0xd0771d01, 0xf240e192, 0xe193408b, 0xe16ee15c, 0x91004b83, 0x33244982, 0xf1011f1a, 0xf7ff003c, 
+    0xe79af9b7, 0x3118497e, 0x1f031f08, 0x0100e9cd, 0x39181f1a, 0xf7ff3028, 0x88e8fa0c, 0x2002b920, 
+    0xf8bdf7e7, 0xd1882800, 0xe0014978, 0xe168e163, 0x28007808, 0x8928d181, 0x81281c40, 0x70082001, 
+    0x80382043, 0x0000f995, 0xd0012802, 0xd10b2803, 0x1c408968, 0x486e8168, 0xf2487801, 0xf7e60000, 
+    0x2000ffb1, 0xf892f7ff, 0x22004965, 0x313c6ba8, 0xfd85f003, 0xd1131d01, 0x8034f8a4, 0x9ffce8bd, 
+    0xe033e013, 0xe06de051, 0xe0a0e08c, 0xe0dee0cc, 0xe10ce0fa, 0x2200495a, 0x313c4618, 0xfd6ff003, 
+    0xd1ae1d40, 0x40bdf240, 0x4b55e134, 0x49549100, 0x1f1a3324, 0x003cf101, 0xf940f000, 0x22004950, 
+    0x313c6ba8, 0xfd5bf003, 0xd10a1d01, 0x40c4f240, 0xe106e120, 0x494ae112, 0x46182200, 0xf003313c, 
+    0x1d40fd4e, 0xf240d18d, 0xe11340c5, 0x23004a44, 0x32249100, 0xf1011f11, 0xf000001c, 0x4940fb06, 
+    0x6ba82200, 0xf003313c, 0x1d01fd3a, 0xf8a4d108, 0xe7b3b034, 0x2200493a, 0x313c4618, 0xfd2ff003, 
+    0xd1871d40, 0x40cbf240, 0x4835e0f4, 0xe9d52300, 0x303c1208, 0xf9dbf001, 0x22004931, 0x313c6ba8, 
+    0xfd1df003, 0xd1081d01, 0x40d0f240, 0x492ce0e2, 0x46182200, 0xf003313c, 0x1d40fd12, 0xf240d1a1, 
+    0xe0d740d1, 0xf9954b26, 0x33281000, 0x0208f1a3, 0x001cf102, 0xfc60f001, 0x22004921, 0x313c6ba8, 
+    0xfcfdf003, 0xd1081d01, 0x40d6f240, 0x491ce0c2, 0x46182200, 0xf003313c, 0x1d40fcf2, 0xf240d1a2, 
+    0xe0b740d7, 0xf9954816, 0x303c1000, 0xfddcf001, 0x22004913, 0x313c6830, 0xfce1f003, 0xf47f1d01, 
+    0xf240ae7e, 0xe0a540dc, 0x9034f8a4, 0x4b0ce756, 0x1000f995, 0xf1a33328, 0xf1020208, 0xf001001c, 
+    0x4907fe15, 0x6ba82200, 0xf003313c, 0x1d01fcc8, 0xf240d115, 0xe08d40e2, 0x00041698, 0x00040286, 
+    0x00040ed8, 0x00040688, 0x000406cc, 0x00040285, 0x00040243, 0x22004948, 0xf0034618, 0x1d40fcb0, 
+    0xf240d19c, 0xe07540e3, 0x1000f995, 0xf0014842, 0x4941fe36, 0x68302200, 0xfca1f003, 0xf47f1d01, 
+    0xf240ae53, 0xe06540e8, 0x40e9f240, 0x4b3ae062, 0x1000f995, 0x48383b14, 0x0208f1a3, 0xff3ef001, 
+    0x22004935, 0xf0036ba8, 0x1d01fc8a, 0xf240d107, 0xe04f40ee, 0x22004930, 0xf0034618, 0x1d40fc80, 
+    0xf240d18c, 0xe04540ef, 0x1000f995, 0xf002482a, 0x4929f9d1, 0x68302200, 0xfc71f003, 0xf47f1d01, 
+    0xf240ae32, 0xe03540f4, 0x40f5f240, 0xf995e032, 0x48211000, 0xf0016a2a, 0x491fffc5, 0x6ba82200, 
+    0xfc5df003, 0xd1071d01, 0x40faf240, 0x491ae022, 0x46182200, 0xfc53f003, 0xd1a11d40, 0x40fbf240, 
+    0xf8dae018, 0xf0030000, 0x1d01fc4a, 0xae1ef47f, 0x5002f240, 0xf240e00e, 0xe00b5003, 0x5006f240, 
+    0x490de008, 0x46182200, 0xfc39f003, 0xd1871d40, 0x5007f240, 0xe6b186a0, 0x21012200, 0xf2afb510, 
+    0xf00340e3, 0x2108fa77, 0xf0032004, 0x4902fbd5, 0x6388393c, 0x0000bd10, 0x00040f14, 0x4fffe92d, 
+    0x0b00f04f, 0xb083460e, 0x465c4682, 0xf04f48fe, 0xf8cd52a0, 0xf9bab008, 0xf8d01000, 0x48fb9000, 
+    0x5880f509, 0x88056800, 0x7080f04f, 0xfe77f7df, 0xf7e72000, 0x4ff6fa79, 0x220c2300, 0x0100f24f, 
+    0xf0074638, 0x2300fe31, 0x7100f640, 0x46382208, 0xfe2af007, 0x46382300, 0x21f02204, 0xfe24f007, 
+    0x46382300, 0x461a210f, 0xfe1ef007, 0x210048e9, 0xfe17f007, 0x94002200, 0x46112310, 0xf7e94610, 
+    0x48e5ffb3, 0x48e57004, 0xb9887800, 0x28037830, 0xf44fd00e, 0xf6403000, 0xf7df0103, 0xf7ebfdf2, 
+    0x48dffd84, 0xf9902100, 0x46082000, 0xfeb2f7e8, 0x22084cdc, 0x01512300, 0xf0074620, 0xf44ffe0c, 
+    0x91020100, 0xe00d138f, 0x21074ad6, 0x3254a802, 0xfe6df7e6, 0xd00d2801, 0x46392301, 0x46202209, 
+    0xfdf9f007, 0x220648cf, 0x38fa2140, 0xfe01f007, 0xd1e92800, 0x240148cc, 0x0000f990, 0xd0022805, 
+    0xd0022804, 0x2402e002, 0x2404e000, 0x1000f996, 0x4fc748c6, 0xd0042903, 0xd00f2902, 0xd01a2905, 
+    0xf9b7e020, 0x29011000, 0x2203da04, 0xf0072138, 0xb108fde0, 0xe00f48bf, 0xe00d48bf, 0x1000f9b7, 
+    0xda042901, 0x21382203, 0xfdd3f007, 0x48bbb108, 0x48bbe002, 0x48bbe000, 0xfb042200, 0x2002f100, 
+    0xfd5ef7e6, 0x20022100, 0xfd24f7e6, 0xf04f9805, 0x4cb531ff, 0x60014ab5, 0xf8c19906, 0x6820b000, 
+    0x60201c40, 0x1c498811, 0xb2818011, 0x301848a5, 0xfd87f007, 0x46597820, 0xb2b4f8df, 0x0007f000, 
+    0x1200eb00, 0x0082eb0b, 0x20056301, 0xfd22f7e6, 0xf0026822, 0xeb010107, 0xeb0b1301, 0xe9c10183, 
+    0x48a4020d, 0x63c88800, 0x680048a3, 0xf7e56408, 0x48a2ff36, 0x213f2200, 0xfd8bf007, 0xd3012811, 
+    0xe0002001, 0xf8df2000, 0x2301b23c, 0xf1ab8178, 0x029c0b30, 0x220a4658, 0xf0074621, 0x2300fd6c, 
+    0x220a4621, 0xf0074658, 0x4895fd66, 0xb9107800, 0xf7fe2000, 0x4884fe1b, 0xf9967801, 0xf7e20000, 
+    0x2301fc6d, 0x220e488f, 0xf0070399, 0xf996fd54, 0x4c8d0000, 0xb234f8df, 0x4e8d2802, 0x2803d004, 
+    0x2805d01e, 0xe07dd042, 0xf7fb2001, 0x2100ff1b, 0xf7e72001, 0x8820fe23, 0x48869000, 0x3000f89b, 
+    0xf9907831, 0x20072000, 0xfe57f7fb, 0x48822301, 0x46192200, 0xfd2ff007, 0xf7fb2000, 0xe05cfd8d, 
+    0x28018978, 0x487dd114, 0x23082200, 0x4000f990, 0xe9cd4610, 0x46219800, 0xf9f0f7e5, 0x23014978, 
+    0x22004878, 0x0100e9cd, 0x46184621, 0xf9e6f7e5, 0x78004875, 0xd1052801, 0xfee4f7fb, 0x20012100, 
+    0xfdecf7e7, 0xf7fb2004, 0xe03bfd67, 0x90008820, 0xf89b4868, 0x78313000, 0x2000f990, 0xf7fb2007, 
+    0x2301fe1c, 0x22004864, 0xf0074619, 0x2002fcf4, 0xfc80f7e6, 0x60084965, 0x49652002, 0x20007008, 
+    0xfd4af7fb, 0x22204963, 0xf0074863, 0xf8dffc74, 0x24008170, 0x23014f5b, 0xf005fb04, 0xeb082200, 
+    0xeb070140, 0xe9cd0040, 0x46210100, 0xf7e54618, 0x1c64f9a5, 0x2c04b264, 0x7831dbed, 0x1000f240, 
+    0xfad6f7e5, 0x7480f04f, 0x11f4f240, 0xf7df4620, 0xf243fc98, 0x46203100, 0xfc82f7df, 0x4620494f, 
+    0x1000f991, 0xfc7cf7df, 0x4620494d, 0xf7df6809, 0x494cfc77, 0xf7df4620, 0x2144fc73, 0x1000f8aa, 
+    0xe8bdb007, 0xe92d8ff0, 0x469041f0, 0x24014a1f, 0x88126812, 0x0e52eb04, 0xeb081ea4, 0xfa0f0c04, 
+    0x2200f78c, 0xfb026806, 0xf853c50e, 0x42b55025, 0x6005d301, 0x1c52800f, 0x2a04b212, 0x1c64dbf2, 
+    0x2c01b224, 0xe8bddde9, 0xe92d81f0, 0xb0934fff, 0x20004d35, 0x90124688, 0x900b4834, 0x6800480b, 
+    0xf2408804, 0xfbb01000, 0xea4ff0f4, 0xf10a0a54, 0xb2400701, 0x4804900e, 0x900a6800, 0x5080f500, 
+    0x200a9009, 0x0000e054, 0x000401e8, 0x00040598, 0xf100004c, 0xf2031034, 0x00040d84, 0x00040502, 
+    0x00040248, 0xf2035126, 0x00040242, 0xf38f007c, 0x00040f28, 0x02faf080, 0x015752a0, 0x017d7840, 
+    0x0094c5f0, 0x03b9aca0, 0x00040ef4, 0x00040f24, 0x00041698, 0x0004054c, 0x00040264, 0xf2034202, 
+    0x00040285, 0xf2030416, 0x00040270, 0x000402c8, 0x0004057b, 0x000401ec, 0xf20305ae, 0x00040518, 
+    0x00049108, 0x00048908, 0x0004056a, 0x00040558, 0x00040556, 0x00041508, 0x00041258, 0x00040ed8, 
+    0x000401f0, 0xdcba01f5, 0x00046908, 0x00047908, 0xf0f0fbb4, 0x52a0f04f, 0x9008b200, 0xf9b09813, 
+    0xf04f1000, 0xf7df7080, 0x2100fc2a, 0x3080f44f, 0xfbd8f7e6, 0xf99048fd, 0x28050000, 0x2804d001, 
+    0x2100d104, 0x3000f44f, 0xfbccf7e6, 0x21002000, 0x1020f845, 0xb2001c40, 0x6f80f5b0, 0x9816dbf7, 
+    0xd1782800, 0x93c8f8df, 0x0000f899, 0xd1182803, 0xf24848f0, 0x78010600, 0xf7e64630, 0x48eefbb3, 
+    0xb9087800, 0xfd16f7eb, 0xf04f48ec, 0x89400100, 0xd00d2801, 0xf7e64630, 0xf899fba5, 0x28030000, 
+    0xf999d009, 0x28020000, 0x2805d005, 0xe060d003, 0x0000f244, 0x48e2e7ef, 0xfba0f007, 0x2100b206, 
+    0x3000f44f, 0xfb8ef7e6, 0xd5120770, 0x70fbf64f, 0x0100ea06, 0xf00748da, 0x48d4fb94, 0x28037800, 
+    0xf899d107, 0x28020000, 0x2100d103, 0xf7e60400, 0x4ed3fb79, 0xf0074630, 0xb201fb81, 0xd5050608, 
+    0x707ff64f, 0x46304001, 0xfb7bf007, 0xf0074630, 0xb201fb75, 0xd50c04c8, 0x70fff64e, 0x46304001, 
+    0xfb6ff007, 0x20012100, 0xfbdef7f7, 0xf7f72000, 0xf899f8e4, 0x28050000, 0xf44fd10d, 0x21003600, 
+    0xf7e64630, 0x2100fb4f, 0xf7e64630, 0x2100fb4b, 0xf7e64630, 0x48b6fb47, 0x0000f990, 0xd0012802, 
+    0xd1062805, 0xfc70f7e8, 0x9011b200, 0xf7e82008, 0xf242fc65, 0x064801c0, 0xfb3ff7df, 0x90062000, 
+    0x9010b220, 0x0900f04f, 0x01c0f242, 0xf7df0648, 0x2301fb34, 0x21059810, 0xe88d029a, 0x48a9000f, 
+    0x23001f8a, 0x68002108, 0xfce0f7fa, 0x49a52600, 0xfb064622, 0x6809f004, 0x0040eb01, 0x680949a2, 
+    0x3080f9b1, 0xf00749a1, 0x489ffae4, 0x4aa14ba0, 0x78816800, 0x0094f8d0, 0x0100e9cd, 0x9912489b, 
+    0xfc3cf007, 0xe268f8df, 0xe0172000, 0xf8514999, 0xf85e3020, 0xfb811020, 0xfbc31201, 0x4b8f1203, 
+    0x1204e9c3, 0x0307fb06, 0xea410d89, 0x1c402182, 0xc023f855, 0x4461b200, 0x1023f845, 0xdbe542b8, 
+    0xf007fb06, 0x22004982, 0x2020f845, 0x1000f991, 0xd0012902, 0xd1032905, 0x0154eb00, 0x2021f845, 
+    0x68099920, 0x0f94ebb1, 0xeb00d103, 0xf8450094, 0x1c762020, 0x2e04b276, 0xf109dba9, 0xfa0f0001, 
+    0xf1b9f980, 0xdb8f0f02, 0xb9689806, 0x990ba80d, 0x9000ab05, 0x4628aa07, 0xfc16f7fe, 0x0034f9bd, 
+    0xfb90496e, 0x8108f0f7, 0x1c409806, 0x9006b200, 0xf6ff2801, 0xf242af77, 0x064801c0, 0xfaadf7df, 
+    0xf9904863, 0x28020000, 0x2805d001, 0x9811d103, 0xf7e8b2c0, 0x4961fbc3, 0x90042000, 0x81881e40, 
+    0x68004865, 0xd37d2812, 0xbbe09816, 0x7800485a, 0x4857bbc8, 0x28027800, 0x05c0d177, 0x11f4f240, 
+    0xfa7ff7df, 0x7080f04f, 0x1199f641, 0xfa68f7df, 0x9168f8df, 0x7080f04f, 0x1000f999, 0xfa60f7df, 
+    0x1034f9bd, 0x7080f04f, 0xfa5af7df, 0xf04f4e4b, 0xf9b67080, 0xf7df1008, 0xf999fa53, 0xf9b60000, 
+    0x42881008, 0xf8ddd14a, 0x2000901c, 0x90004606, 0x0014f9bd, 0x0007fb06, 0x1020f855, 0x7080f04f, 
+    0xfa3ef7df, 0xe040e000, 0x0014f9bd, 0x0007fb06, 0x0020f855, 0xda014548, 0x96004681, 0xb2761c76, 
+    0xdbe52e04, 0x7980f04f, 0x46489900, 0xfa28f7df, 0x1014f9bd, 0xf7df4648, 0xf7ebfa23, 0x4e37fad5, 
+    0x99001402, 0xb2017031, 0xf7eb4610, 0x4934fa38, 0x70082001, 0xf7eb2002, 0xf996fc47, 0xf7eb0000, 
+    0xf996f98f, 0xf7eb0000, 0xf996f9d4, 0xf7eb0000, 0xf996fa1f, 0x46481000, 0xfa02f7df, 0xf04f4929, 
+    0xe0007080, 0xf7dfe096, 0x4e1cf9fb, 0xbb608830, 0x1014f9bd, 0x0903f04f, 0xfb91462b, 0xf106f0f9, 
+    0xb202010c, 0xf7ffa804, 0xf9bdfd7e, 0x1a220014, 0xf1f9fb92, 0x1a10b20a, 0x28081d00, 0xf106d905, 
+    0x462b010c, 0xf7ffa804, 0x89b0fd6e, 0xf8dd462b, 0x80f0b010, 0x0014f9bd, 0xeb004908, 0x310c70d0, 
+    0xa8041042, 0xfd5ff7ff, 0xe02de01e, 0x00040242, 0x00040ed8, 0x00040243, 0x00040502, 0x00040f28, 
+    0xf23c80b8, 0x000401dc, 0x00040598, 0x00049908, 0x0004c908, 0x0004c108, 0x000401f0, 0x00040248, 
+    0x00040246, 0xdcba01f5, 0x0014f9bd, 0xeb011a21, 0x104971d1, 0x1a10b20a, 0x28081d00, 0x49fed904, 
+    0x462ba804, 0xfd2ff7ff, 0x100cf9b6, 0x42819808, 0x2000da03, 0x1e409004, 0xf9bd81b0, 0x00410014, 
+    0x2101b20e, 0x0194eb01, 0xdc034281, 0xeb044241, 0xb20e0141, 0xdc05287d, 0xa80449ef, 0x4632462b, 
+    0xfd11f7ff, 0x960f9804, 0xf9bd900c, 0x282b0014, 0x0140eb00, 0xdb03b20a, 0x0180eba0, 0xb20a4421, 
+    0xdc072845, 0x0f94ebb0, 0x49e3d004, 0x462ba804, 0xfcf9f7ff, 0xf188fa1f, 0xf00748e0, 0x48dff982, 
+    0xf188fa1f, 0xf0071c80, 0xf108f97c, 0xb2810001, 0x1d0048da, 0xf975f007, 0xf3c09807, 0x48d7214f, 
+    0xf0071d80, 0xf8bdf96e, 0xb2810014, 0x300a48d3, 0xf967f007, 0x7980f04f, 0x11f4f240, 0xf7df4648, 
+    0xf240f950, 0x46487177, 0xf93af7df, 0x46484ecc, 0xf7df6831, 0xf9bdf935, 0x46481014, 0xf930f7df, 
+    0x0a019807, 0xf7df4648, 0x49c6f92b, 0xf7df4648, 0x7830f927, 0xf8df2600, 0xf0009300, 0xf8df0007, 
+    0xf1a9c30c, 0xeb00090c, 0x48bf1200, 0x0082eb00, 0x8803e9c0, 0x8014f8c0, 0x1014f9bd, 0x61c19101, 
+    0x1034f9bd, 0x9b076201, 0x0a5a6246, 0x08a06182, 0xf8c89000, 0x98150000, 0xf8a96006, 0xf8a96002, 
+    0xf99c6004, 0x28030000, 0xf04fd005, 0xd1050604, 0x1cf4f240, 0xf04fe004, 0xe7f80632, 0x0c0af04f, 
+    0xe038f8dd, 0xfe0efb16, 0xebbe9e0e, 0xf8cd2f53, 0xfb1ce018, 0xb236f606, 0x9801d222, 0x0000f8c8, 
+    0x60029815, 0xb28143c8, 0x1d00489c, 0xf8f9f007, 0x7800489e, 0x98042803, 0xebb6d006, 0xd86c2f10, 
+    0xf8a92001, 0xe0680002, 0x2f10ebb6, 0xf9b9d865, 0x9908200c, 0xdb60428a, 0xf8a92101, 0xe05c1002, 
+    0xd02b2803, 0x7080f04f, 0x11f4f240, 0xf8c9f7df, 0x7080f04f, 0x0180f648, 0xf8b2f7df, 0xf04f4e88, 
+    0x68317080, 0xf8acf7df, 0x78014889, 0x7080f04f, 0xf8a6f7df, 0x1000f8d8, 0x7080f04f, 0xf8a0f7df, 
+    0xf04f4980, 0xf7df7080, 0x6830f89b, 0xdb142801, 0x7800487f, 0xd8102823, 0xe0102180, 0x68009820, 
+    0xd0071c41, 0x0000f8c8, 0xf8a92101, 0xf8a9a00c, 0xe01b1002, 0xa000f8c8, 0xf04fe018, 0xf8c831ff, 
+    0xf04f1000, 0xf2407680, 0x463011f4, 0xf889f7df, 0x1000f8d8, 0xf7df4630, 0x496af873, 0xf7df4630, 
+    0x2100f86f, 0x1002f8a9, 0x1004f8a9, 0x30b8f608, 0x4862b281, 0xf0071d00, 0x4866f884, 0x28126800, 
+    0xf9bdd370, 0xebb00014, 0xd1080f94, 0x2002f8b9, 0xb9224649, 0xa00cf8a1, 0xf8a92201, 0x4b5b2002, 
+    0x1000f993, 0xd1102903, 0x0f54ebb0, 0x1f0ad004, 0x0254eb02, 0xd1084282, 0x6002f8b9, 0xb926464a, 
+    0x81969e00, 0xf8a92601, 0x9a086002, 0xdc044290, 0xf8a92200, 0xf8a92002, 0x29032004, 0xf8b9d151, 
+    0x46481002, 0x9920b921, 0x81818809, 0x80412101, 0x000af8b9, 0xd1442801, 0xf9904847, 0x90030000, 
+    0x0000f8b8, 0xf04fb206, 0x45560000, 0x2100d10a, 0xfb009b09, 0x1c40f20a, 0x2808b200, 0x1012f823, 
+    0xe00cdbf6, 0x9b0a2200, 0x610afb00, 0xb2001c40, 0xf8232808, 0x9b092011, 0x2011f823, 0xe9dddbf3, 
+    0x20082109, 0xe88d2300, 0x99030007, 0x4618461a, 0xfc2cf7e4, 0x45564831, 0xf04f4a31, 0xd1020100, 
+    0xe0048001, 0xf822e047, 0xf8201016, 0x21011016, 0xe9cd9100, 0x23002001, 0x20019903, 0xf7e4461a, 
+    0xf9b9fc15, 0x464e0006, 0x100cf9b9, 0xd04d4288, 0xbb818871, 0x7809491d, 0xd0772903, 0x215bea5f, 
+    0x9908d044, 0xdb414288, 0xf2402001, 0x80b011f4, 0xf7de0600, 0xf04fffd6, 0xf2457080, 0xf7de5122, 
+    0xf9b6ffbf, 0xf04f1004, 0xf7de7080, 0xea4fffb9, 0xf04f215b, 0xf7de7080, 0xf9b6ffb3, 0xf04f100c, 
+    0xf7de7080, 0xf9b6ffad, 0xf04f1006, 0xf7de7080, 0x4904ffa7, 0xe019e016, 0x00040f34, 0xf23c80aa, 
+    0x00040ef4, 0xdcba01f5, 0x00041698, 0x00040ed8, 0x00040504, 0x000401f0, 0x00040518, 0x00049108, 
+    0x00048908, 0x7080f04f, 0xff8af7de, 0xb3609816, 0x70d0f240, 0x26009000, 0xf04f1081, 0xf7de7080, 
+    0xf04fff90, 0xf2437080, 0xf7de3111, 0xf04fff79, 0xf2407080, 0xf7de71d0, 0x48feff73, 0xf04f7801, 
+    0xf7de7080, 0xf04fff6d, 0xf2407080, 0xf7de71d0, 0x49f9ff67, 0x7080f04f, 0xff62f7de, 0x0014f9bd, 
+    0xdb0e2819, 0xe00f9900, 0xe0aae000, 0xebb22205, 0xd8cb2f5b, 0x42889908, 0x2001dbc8, 0x0004f8a9, 
+    0xf640e7c4, 0x910071a0, 0xebb19b07, 0xd2252f53, 0xf1a72103, 0x45600c08, 0xf9b9dc0b, 0xeb002008, 
+    0xfb020e01, 0x9a0bee07, 0x202ef852, 0xdb0042b2, 0xebb04616, 0xd0020f54, 0x0f94ebb0, 0xf9b9d10a, 
+    0xfb022008, 0x9a0b1e07, 0x028eeb02, 0x42b26c92, 0x4616db00, 0xb2091c89, 0xdddc2907, 0xebb02100, 
+    0xd0020f54, 0x0f94ebb0, 0x2102d100, 0x2008f9b9, 0x464c1d49, 0x0207fb02, 0x2022f855, 0x42b2410a, 
+    0x9900db03, 0x2f53ebb1, 0x9a15d302, 0x60112100, 0x4fca2100, 0x9a157039, 0x2a006812, 0x381cdd07, 
+    0xd8042808, 0x780048c6, 0x2001b908, 0x98047038, 0x980e0a42, 0x0340eb00, 0x10c0ebc3, 0x1f00ebb2, 
+    0x8061d800, 0x225bea4f, 0x1f00ebb2, 0x80a1d800, 0x7080f04f, 0x11f4f240, 0xfef3f7de, 0x7080f04f, 
+    0x1122f241, 0xfedcf7de, 0x1000f997, 0x7080f04f, 0xfed6f7de, 0xf04f9900, 0xf7de7080, 0x9807fed1, 
+    0xf04f0a41, 0xf7de7080, 0xf9bdfecb, 0xf04f1014, 0xf7de7080, 0xf04ffec5, 0x46317080, 0xfec0f7de, 
+    0x1002f9b4, 0x7080f04f, 0xfebaf7de, 0x1004f9b4, 0x7080f04f, 0xfeb4f7de, 0xf04f499f, 0xf7de7080, 
+    0xe9ddfeaf, 0xebb00106, 0xd33d2f51, 0x7480f04f, 0x11f4f240, 0xf7de4620, 0xf648feb4, 0x46200181, 
+    0xfe9ef7de, 0x46204e97, 0xf7de6831, 0x4f91fe99, 0x78394620, 0xfe94f7de, 0x1000f8d8, 0xf7de4620, 
+    0x498dfe8f, 0xf7de4620, 0x6830fe8b, 0xdb042801, 0x28237838, 0x2080d801, 0xf04fe001, 0xf24030ff, 
+    0xf8c811f4, 0x46200000, 0xfe8bf7de, 0x1000f8d8, 0xf7de4620, 0x4980fe75, 0xf7de4620, 0x2100fe71, 
+    0x1002f8a9, 0x1004f8a9, 0x68019820, 0x0000f8d8, 0xd1634281, 0xd0611c40, 0x0000f8b9, 0x4975464c, 
+    0xb2001c40, 0x0000f8a9, 0x29467809, 0x2802d311, 0x8863db0d, 0xd10a2b01, 0x2a0188a2, 0x9b04d107, 
+    0x0200f04f, 0xd301455b, 0xe00080a2, 0x29468062, 0x2801d847, 0x980cdb45, 0xebb22232, 0xd20c2f50, 
+    0xb9518861, 0x300cf9b4, 0x428b9908, 0x2101db05, 0x990f8061, 0x980c81a1, 0x980c9004, 0x2f50ebb2, 
+    0x88a0d22f, 0xf9b4bb48, 0x9808100c, 0xdb284281, 0x80a02001, 0xf04f980f, 0x80e07680, 0x11f4f240, 
+    0xb030f8dd, 0xf7de4630, 0xf245fe2c, 0x46305111, 0xfe16f7de, 0x1004f9b4, 0xf7de4630, 0xea4ffe11, 
+    0x4630215b, 0xfe0cf7de, 0x1006f9b4, 0xf7de4630, 0x4949fe07, 0xf7de4630, 0xe002fe03, 0xf8a92000, 
+    0x98160000, 0x2000bbf0, 0x90019000, 0xf7e7a802, 0xf8d8fdec, 0x1c400000, 0x2600d028, 0x4634466f, 
+    0x0000f8d8, 0x44309a0b, 0x1020f855, 0x0020f852, 0xdb104281, 0xebc01a08, 0x08401080, 0xfe3cf7e7, 
+    0x4a39a902, 0x1014f931, 0x011ff1c1, 0x1011f832, 0x0b884341, 0x2000e000, 0x0014f827, 0x000aeb06, 
+    0x1c641c40, 0xb206b224, 0xdbd92c04, 0x1000f8bd, 0xf006482e, 0x482dfde6, 0x1002f8bd, 0xf0061c80, 
+    0xe000fde0, 0x4829e00b, 0x1004f8bd, 0xf0061d00, 0x4826fdd8, 0x1006f8bd, 0xf0061d80, 0xf04ffdd2, 
+    0xf2407580, 0x462811f4, 0xfdbbf7de, 0x2122f240, 0xf7de4628, 0x9820fda5, 0x46286801, 0xfda0f7de, 
+    0x1000f8d8, 0xf7de4628, 0x9807fd9b, 0x46280a01, 0xfd96f7de, 0x1002f9b9, 0x4628464c, 0xfd90f7de, 
+    0x100cf9b4, 0xf7de4628, 0x9804fd8b, 0x46280a01, 0xfd86f7de, 0x1004f9b4, 0xf7de4628, 0xf9b4fd81, 
+    0x46281006, 0xfd7cf7de, 0x211bea4f, 0xf7de4628, 0xe00dfd77, 0x00040504, 0xdcba01f5, 0x00040f1d, 
+    0x00040502, 0x00040ef4, 0x00040d86, 0xf2035154, 0x462849fe, 0xfd64f7de, 0x01c0f242, 0xf7de0648, 
+    0x9813fd7c, 0x80012145, 0xe8bdb017, 0xe92d8ff0, 0xb0854fff, 0x20004688, 0x48f59003, 0x48f56804, 
+    0x28017800, 0x257fd01c, 0x210148f3, 0x52a0f04f, 0xf8b06800, 0xeb019000, 0x210a0a59, 0xf0f1fbb9, 
+    0x9004b200, 0xf99048ed, 0x9805b000, 0x1000f9b0, 0x7080f04f, 0xfd93f7de, 0x98084ee9, 0xe023b110, 
+    0xe7e125ff, 0x0000f996, 0xd01d2805, 0xd01b2803, 0x680048e4, 0xd2042816, 0xf44f2100, 0xf7e53000, 
+    0x48e1fd31, 0x90008800, 0x780348e0, 0xf99048e0, 0x48e02000, 0x20007801, 0xfe6ff7fa, 0x48de2300, 
+    0x461a2101, 0xfd47f006, 0x464948dc, 0xfd22f007, 0x270048d3, 0x0000f990, 0xd0042803, 0x91022104, 
+    0xb1119908, 0x2101e007, 0x2805e7f9, 0x465fd103, 0xb2401c78, 0x49d29002, 0x0688eb01, 0x48d1e13d, 
+    0x28067800, 0x0000f04f, 0x49cfd310, 0xeb014acc, 0xe0052187, 0x3020f851, 0x3020f842, 0xb2001c40, 
+    0xdbf74550, 0xf85048c9, 0xe00b0027, 0x4bc449c8, 0xf851e005, 0xf8432020, 0x1c402020, 0x4550b200, 
+    0x6808dbf7, 0x1c08f856, 0xebb14abd, 0xdd000fe0, 0xf84610c1, 0xf8561c08, 0xebb11c04, 0xdd000fa0, 
+    0xf8461081, 0xf8421c04, 0x68710028, 0x0fa0ebb1, 0x1081dd00, 0x68b16071, 0x0fe0ebb1, 0x10c1dd00, 
+    0x49a860b1, 0x29126809, 0x4bb1d336, 0x88593b18, 0xd1172901, 0xe00cf9b3, 0xc2a4f8df, 0x018eeb0c, 
+    0x2c04f851, 0x0fa0ebb2, 0x1082dd00, 0x2c04f841, 0xf84c1082, 0xf8d1202e, 0xebbcc004, 0xdc000fa0, 
+    0x604a4662, 0x29018899, 0xf9b3d116, 0xf8df3006, 0xeb0cc270, 0xf8510183, 0xebb22c04, 0xdd000fa0, 
+    0xf8411082, 0x10822c04, 0x2023f84c, 0xebb3684b, 0xdc000fa0, 0x604a461a, 0x001af1a8, 0xd918280a, 
+    0x38184893, 0x100cf9b0, 0x290a391a, 0x8841d802, 0xd00e2901, 0x1006f9b0, 0x2908391c, 0x8880d802, 
+    0xd0062801, 0x498b2000, 0x3ffff1b8, 0xd0027008, 0x2001e004, 0x4887e7f7, 0x70012102, 0xf08afa0f, 
+    0xe0074a7f, 0x0100eba9, 0x1021f852, 0x1020f842, 0xb2001c40, 0xdbf54548, 0x4a7f486f, 0x68009b03, 
+    0xf8d07881, 0xe9cd0094, 0x49740100, 0xf0074874, 0x4979f86f, 0x5200f04f, 0x2000e009, 0x3020f851, 
+    0xf841005b, 0x1c403020, 0x2811b200, 0x6808dbf6, 0xddf24290, 0x4280f04f, 0x42906808, 0x0000f04f, 
+    0xf851dd09, 0x105b3020, 0x3020f841, 0xb2001c40, 0xdbf62811, 0xf851e7f0, 0xf1022020, 0xf8415200, 
+    0x1c402020, 0x2811b200, 0x4864dbf5, 0x1107eb07, 0xeb002210, 0x48600181, 0xf7f29100, 0x2000fedf, 
+    0x9900426a, 0x1020f851, 0x7180f501, 0x214ff341, 0xf82442a9, 0xdd001010, 0x42914629, 0x1010f824, 
+    0x4611da00, 0x1010f824, 0xb2001c40, 0xdde82810, 0x46012000, 0x3010f834, 0xb2001c40, 0xb2094419, 
+    0xdbf72811, 0x45989b04, 0x8c20db02, 0x84201a40, 0x2000494b, 0x1347eb01, 0x0c40eb04, 0x1002f9bc, 
+    0xdd0042a9, 0xf8234629, 0xf9bc1010, 0x42911002, 0x4611da00, 0x1010f823, 0xb2001c40, 0xdbeb2810, 
+    0x21014840, 0x1c7f4a40, 0x7800b27f, 0x0007f000, 0x1000eb00, 0x0080eb02, 0x98026241, 0xf6ff4287, 
+    0x4833aebe, 0x88003818, 0x4f38b998, 0x4e342100, 0xeb072000, 0xeb061341, 0xf8321241, 0xf823c010, 
+    0x1c40c010, 0x2810b200, 0x1c49dbf7, 0x2904b249, 0x9808dbee, 0x481abb40, 0x28057800, 0xf8dfd124, 
+    0x220080a0, 0x39fff04f, 0xeb084610, 0x4649134b, 0x466f4616, 0xf8334249, 0xb209e010, 0x1c40543e, 
+    0x2201fb1e, 0xb212b200, 0xdbf32810, 0x0040f1c2, 0x2100b200, 0xdd042808, 0x0108f1a0, 0x0c01f04f, 
+    0xf110b209, 0xe0330f08, 0x0000e079, 0xdcba01f5, 0x000401e8, 0x000402b2, 0x00040598, 0x00040248, 
+    0x00040ed8, 0x000401f0, 0x00040270, 0x000402c8, 0x000401ec, 0x0004057b, 0xf20305ae, 0x0004c908, 
+    0x0004c108, 0x00040504, 0x00045908, 0x000418f8, 0x00040f40, 0x00040f1c, 0x00049908, 0x00041588, 
+    0x00041488, 0x00040ef4, 0x00041698, 0x0004d654, 0x3008da03, 0x424046cc, 0xf1ccb201, 0x29000c00, 
+    0x2910dd0f, 0x2000dd0d, 0x42524662, 0x5c3eb212, 0x543e4416, 0xb2001c40, 0xdbf62810, 0xb2093910, 
+    0x1e48e7ed, 0xd80c280f, 0xe0082000, 0x0200f1cc, 0xfc82fa0f, 0x44625c3a, 0x1c40543a, 0x4288b200, 
+    0x2000dbf4, 0xf8334646, 0x563a1010, 0xf8234411, 0x1c401010, 0x2810b200, 0x2100dbf5, 0xd00a4559, 
+    0xeb062000, 0xf8331241, 0xf8227010, 0x1c407010, 0x2810b200, 0x1c49dbf7, 0x2904b249, 0xf8dfdbee, 
+    0xf89883d0, 0x28030000, 0xf8dfd11e, 0x2101c3c8, 0x2000426f, 0x1641eb0c, 0x0240eb04, 0x3002f9b2, 
+    0xdd0042ab, 0xf826462b, 0xf9b23010, 0x42ba2002, 0x463ada00, 0x2010f826, 0xb2001c40, 0xdbeb2810, 
+    0xb2491c49, 0xdbe42904, 0x01c0f242, 0xf7de0648, 0xf998fae4, 0x28020000, 0x2803d005, 0x2805d005, 
+    0x210fd008, 0x2146e002, 0x2149e000, 0x80019805, 0xe55ab009, 0xe7f9214c, 0x4fffe92d, 0xb08748d6, 
+    0x7880f04f, 0x2600461f, 0xf04f4615, 0x680052a0, 0x20018804, 0x0954eb00, 0xf9b09807, 0x46401000, 
+    0xfafdf7de, 0x01c0f242, 0xf7de0648, 0x6828fab6, 0x68296038, 0x1c4a48c9, 0xf44fd004, 0x435132c8, 
+    0xe0010c09, 0x71fff64f, 0xfaabf006, 0x11f4f240, 0xf7de4640, 0xf243fa96, 0x46403133, 0xfa80f7de, 
+    0x46406839, 0xfa7cf7de, 0x46406829, 0xfa78f7de, 0xf9b048bb, 0x4640100a, 0xfa72f7de, 0x220048b9, 
+    0xf006213f, 0x4601fab6, 0xf7de4640, 0x48b6fa69, 0x46407801, 0xfa64f7de, 0x464049b4, 0xfa60f7de, 
+    0x49b348b4, 0xf7e56800, 0xf8dffa73, 0x2500a2cc, 0xb2c8f8df, 0x829cf8df, 0xeb0a2000, 0xeb0b1345, 
+    0xeb081145, 0xf8d71245, 0xf1bcc000, 0xd0363fff, 0xc010f832, 0xc010f821, 0xb2401c40, 0xdbf22810, 
+    0xf7e44628, 0x1c6df80f, 0x2d04b26d, 0x2001dbe4, 0xfad2f7fa, 0x01c0f242, 0xf7de0648, 0x48a0fa4e, 
+    0xf9902300, 0x20015000, 0x46289000, 0x1245eb0a, 0x1145eb0b, 0xf8b2f7e4, 0x20004f9a, 0x1345eb08, 
+    0xeb0746c4, 0xf8331145, 0xf8212010, 0x1c402010, 0x2810b240, 0x4894dbf7, 0xb1187800, 0xf833e004, 
+    0xe7c7c010, 0xfb86f7ea, 0x46ba2500, 0x488c2701, 0x0000f990, 0xd0164285, 0x23004887, 0x1145eb0b, 
+    0xeb009700, 0x46281245, 0xf888f7e4, 0xeb082000, 0xeb0a1145, 0xf8311245, 0xf8223010, 0x1c403010, 
+    0x2810b240, 0x1c6ddbf7, 0x2d04b26d, 0xf8dfdbdf, 0x497aa1fc, 0x0000f99a, 0xffcbf7e3, 0x21044a7c, 
+    0xf0064876, 0x4d78f8d3, 0xb9187828, 0x70074879, 0xff0ef7f9, 0x70074878, 0xf8b4f7fa, 0x22034877, 
+    0xf0062138, 0xb108fa16, 0xf8f0f7e5, 0x0bc0f242, 0x4000f04f, 0xf7de4659, 0xf8dff9e0, 0x210e81c4, 
+    0x0000f998, 0xd0172803, 0xd0152805, 0x9100220e, 0x96042301, 0x96052080, 0x7602e9cd, 0x46119101, 
+    0xf828f7e6, 0x4000f04f, 0xf7de4659, 0xf898f9c6, 0x28030000, 0xe017d00b, 0x91002301, 0x9604220e, 
+    0x96050218, 0x7602e9cd, 0x46119101, 0x200fe7e8, 0x23019000, 0xe9cd4602, 0x46017602, 0x96059604, 
+    0x02589001, 0xf806f7e6, 0x4800f04f, 0x46404659, 0xf9a3f7de, 0xf7e74853, 0xf99af8d6, 0x48511000, 
+    0x0021f850, 0x3fc0f5b0, 0x4659d930, 0xf7de4640, 0x4f4df994, 0xf8df2000, 0x4e4dc134, 0xe0154a4d, 
+    0x1010f837, 0x1010f82c, 0x0140eb07, 0x3200f8b1, 0xf82c1901, 0xf8363011, 0xf8223010, 0xeb063010, 
+    0x1c400340, 0x3200f8b3, 0x3011f822, 0xdbe74548, 0x46404659, 0xf971f7de, 0x6800483f, 0xf240b130, 
+    0x4b3e31a6, 0x1e48782a, 0xf98ef7e5, 0x220f2301, 0x46104619, 0xf88df7e6, 0xf9b04821, 0x28010000, 
+    0x2805db18, 0xdb00b245, 0x4f352505, 0xf44f2400, 0xe00d3600, 0x46307839, 0xf944f7e5, 0x46302100, 
+    0xf940f7e5, 0x46302100, 0xf93cf7e5, 0xb2641c64, 0xdbef42ac, 0x46404659, 0xf93ff7de, 0x21489807, 
+    0xb00b8001, 0x8ff0e8bd, 0x21014a26, 0x4604b510, 0xf7ee7011, 0x4824ff92, 0x80012104, 0x8020200a, 
+    0x01c0f242, 0x4010e8bd, 0xf7de0780, 0x0000b926, 0x00040ed8, 0x00041488, 0x00040598, 0xf203513c, 
+    0x00040f28, 0xf2034202, 0x00040504, 0xdcba01f5, 0x00167fc4, 0x00040558, 0x00041408, 0x00041258, 
+    0x00040248, 0x00041508, 0x00040502, 0x00040518, 0x000412d8, 0x00040246, 0x00040247, 0xf38f007c, 
+    0x00040242, 0x000413e8, 0x00044908, 0x00048908, 0x00045108, 0x00049108, 0x00057f70, 0xf23c80ba, 
+    0x00040243, 0x00040203, 0x00040682, 0x47f0e92d, 0x7780f04f, 0x1000f9b0, 0x4614461d, 0x52a0f04f, 
+    0x46384606, 0xf91bf7de, 0x4900f04f, 0x08c0f242, 0x46484641, 0xf8d1f7de, 0x60286820, 0x4a976820, 
+    0xd0041c41, 0x31c8f44f, 0x0c014348, 0xf64fe001, 0x461071ff, 0xf8c5f006, 0x11f4f240, 0xf7de4638, 
+    0xf243f8b0, 0x46383133, 0xf89af7de, 0x46386829, 0xf896f7de, 0x46386821, 0xf892f7de, 0x46384988, 
+    0xf88ef7de, 0x49874888, 0xf7e56800, 0x4641f8a1, 0xf7de4648, 0x2048f8a2, 0xe8bd8030, 0xe92d87f0, 
+    0xf04f4ff0, 0xf24b7480, 0x26007598, 0x11f4f240, 0x4620b087, 0xf885f7de, 0x0177f649, 0xf7de4620, 
+    0x497af86f, 0xf9b14620, 0xf7de1000, 0x4974f869, 0xf7de4620, 0xf8dff865, 0x4c76b1d8, 0x0000f89b, 
+    0xf44fb968, 0xf6403000, 0xf7de0103, 0xf7e9f86a, 0x2100fffc, 0x2000f994, 0xf7e74608, 0x46a1f92b, 
+    0x4000f994, 0x90002001, 0x2300486c, 0xa1a8f8df, 0x1144eb00, 0xeb0a4620, 0xf7e31244, 0x4f68fecf, 
+    0x4b682000, 0x1144eb07, 0x1244eb03, 0xf8314698, 0xf8224010, 0x1c404010, 0x2810b200, 0xf89bdbf6, 
+    0xb9080000, 0xf9a6f7ea, 0x27012400, 0x0000f999, 0xd0174284, 0x23004859, 0x1244eb0a, 0xeb009700, 
+    0x46201144, 0xfeaaf7e3, 0x20004955, 0x1244eb08, 0x1144eb01, 0x3010f831, 0x3010f822, 0xb2001c40, 
+    0xdbf72810, 0xb2641c64, 0xdbdf2c04, 0x4800f04f, 0x0ac0f242, 0x46514654, 0xf7de4640, 0x200ef81e, 
+    0x23019000, 0xe9cd4602, 0x46017602, 0x96059604, 0x02189001, 0xfe6ef7e5, 0x46404621, 0xf80df7de, 
+    0x0000f89b, 0x2100b9a0, 0xf7e72001, 0xf999face, 0x21002000, 0x464c200c, 0xf876f7e7, 0xf9942101, 
+    0x46082000, 0xf8b6f7e7, 0x70074837, 0xfd10f7f9, 0x22034836, 0xf0062138, 0xb108f81c, 0xfef6f7e4, 
+    0x220f2301, 0x46104619, 0xff13f7e5, 0xf44f4f30, 0x78393000, 0xffd6f7e4, 0x46404651, 0xffddf7dd, 
+    0x88004822, 0xd1362801, 0x492a481f, 0xf7e46800, 0x4e29ffcf, 0xf44f2400, 0x48273880, 0xff03f7e6, 
+    0x42a86830, 0x6870d808, 0xd80542a8, 0x42a868b0, 0x68f0d802, 0xd90742a8, 0x46407839, 0xffb2f7e4, 
+    0xb2641c64, 0xdbe82c0a, 0x7580f04f, 0x11f4f240, 0xf7dd4628, 0xf241ff95, 0x46281100, 0xff90f7dd, 
+    0x46284621, 0xff8cf7dd, 0x4628b007, 0xe8bd4904, 0xf7dd4ff0, 0xb007bf85, 0x8ff0e8bd, 0xf203513c, 
+    0xdcba01f5, 0x001312d0, 0x00040558, 0x00040f32, 0x00040502, 0x00040248, 0x00041408, 0x00041258, 
+    0x00041488, 0x00041508, 0x00040246, 0xf38f007c, 0x00040243, 0x005a000a, 0x000413e8, 0x4ffee92d, 
+    0x48fe4680, 0x4615461f, 0x52a0f04f, 0x1000f9b8, 0x88066800, 0x7080f04f, 0xffb1f7dd, 0x01c0f242, 
+    0xf7dd0648, 0xf8dfff6a, 0x240093d8, 0xa3d4f8df, 0x0b01f04f, 0xf006fb04, 0xb000f8cd, 0x461a2300, 
+    0x0140eb09, 0x0040eb0a, 0x0101e9cd, 0x46212001, 0xfb6cf7e3, 0xb2641c64, 0xdbeb2c04, 0x49ea48eb, 
+    0xf7e46800, 0x2000ff45, 0x0100f640, 0x46024603, 0xf7e89000, 0x48e6f8e9, 0x90008800, 0x780348e5, 
+    0xf99048e5, 0x48e52000, 0x20007801, 0xf875f7fa, 0x48e32300, 0x461a2101, 0xff4df005, 0x780048e1, 
+    0xd1022801, 0xf7fa2003, 0x2100f95f, 0xf7e64608, 0x2000f825, 0xf916f7fa, 0x60386828, 0x48da6829, 
+    0xd0041c4a, 0x32c8f44f, 0x0c094351, 0xf64fe001, 0xf00571ff, 0xf04fff16, 0xf2407480, 0x462011f4, 
+    0xfefff7dd, 0x3133f243, 0xf7dd4620, 0x6839fee9, 0xf7dd4620, 0x6829fee5, 0xf7dd4620, 0x49cbfee1, 
+    0xf7dd4620, 0x11e4fedd, 0x46202100, 0xfeeaf7e4, 0x46202100, 0xfee6f7e4, 0xf7f92003, 0xf242ff6d, 
+    0x064801c0, 0xfee9f7dd, 0x106548c1, 0xb1687800, 0x46282400, 0xf7e42100, 0x1c64fed5, 0x2c0fb264, 
+    0x2147dbf7, 0x1000f8a8, 0x8ffee8bd, 0xf832f7ea, 0x46282400, 0xf7e42100, 0x1c64fec5, 0x2c0fb264, 
+    0xe7eedbf7, 0x5ffce92d, 0x1000f9b0, 0x52a0f04f, 0xf04f4681, 0xf7dd7080, 0xf242ff02, 0x064801c0, 
+    0xfebbf7dd, 0x4daa489d, 0x88006800, 0x78280844, 0x48a8b950, 0xb9387800, 0x3000f44f, 0x0103f640, 
+    0xfe9ff7dd, 0xfe31f7e9, 0xf7f92003, 0xf04fff25, 0x46ab0800, 0x465e2500, 0xb1207830, 0xf7f82000, 
+    0xb978f8da, 0x2001e001, 0x1c6de7f9, 0xdbf32d64, 0x68004899, 0xf240b358, 0x4b9821c2, 0x1e487832, 
+    0xfeb2f7e4, 0x220d4896, 0xf2464d8f, 0x3daa0100, 0x0000f990, 0x4628b283, 0xfe9df005, 0x46282300, 
+    0x21202205, 0xfe97f005, 0x46282301, 0x21202205, 0xfe91f005, 0x0a00f04f, 0x0700f248, 0x48824655, 
+    0x4639220f, 0xf0053878, 0xb978fe94, 0x4881e008, 0x28057800, 0x4883d102, 0xfd95f7e6, 0xe183210f, 
+    0x42bd1c6d, 0xf1badbeb, 0xd0400f00, 0x22004876, 0x71fff643, 0xf0053878, 0x07c0fe7c, 0xf242d07e, 
+    0x064801c0, 0xfe49f7dd, 0x7580f04f, 0x11f4f240, 0xf7dd4628, 0xf241fe36, 0x46281111, 0xfe20f7dd, 
+    0xa1c4f8df, 0xf99a4628, 0xf7dd1000, 0x4967fe19, 0xf7dd4628, 0x2500fe15, 0xf89b46b3, 0x28010000, 
+    0x486ad004, 0x0000f990, 0xd04a4285, 0x27004e68, 0x20019700, 0x4629463a, 0xf7e36833, 0xf89afb37, 
+    0x68310000, 0xd01a2801, 0x800f1e60, 0xf9b9e02e, 0xf04f1000, 0xf04f52a0, 0xf7dd7080, 0x4855fe50, 
+    0x28057800, 0x4854d00a, 0x28006800, 0xf240d006, 0x4b5221c4, 0x1e487832, 0xfe26f7e4, 0xeb01e0db, 
+    0xf8200044, 0x20007c02, 0xe0051e62, 0x0340eb01, 0xf821885b, 0x1c403010, 0xdbf74290, 0xeb01e008, 
+    0xf8320240, 0xf8212c02, 0x1e402010, 0xdcf62800, 0x23006830, 0x0700e9cd, 0x461a2001, 0xf7e34629, 
+    0x1c6dfa22, 0x2d04b26d, 0x4e41dba7, 0x462f2500, 0x22009700, 0x46104629, 0xe0006833, 0xf7e3e0b1, 
+    0xf89afae5, 0x68310000, 0xd0022801, 0x800f1e60, 0xeb01e016, 0xf8200044, 0x20007c02, 0xe0051e63, 
+    0x0240eb01, 0xf8218852, 0x1c402010, 0xdbf74298, 0xeb01e008, 0xf8320240, 0xf8212c02, 0x1e402010, 
+    0xdcf62800, 0x23006830, 0x0700e9cd, 0x4629461a, 0xf7e34618, 0x1c6df9e8, 0x2d04b26d, 0xf89bdbc8, 
+    0xb9d00000, 0x3000f44f, 0x0103f640, 0xfd89f7dd, 0xfd1bf7e9, 0x2200481d, 0x0000f990, 0x68339700, 
+    0x46014605, 0xf7e32001, 0xf89afaa1, 0x68310000, 0xd02f2801, 0x800f1e60, 0xe04de043, 0x00040598, 
+    0x00049108, 0x00048908, 0x00393870, 0x00040558, 0x00040270, 0x000402c8, 0x000401ec, 0x0004057b, 
+    0xf20305ae, 0x0004056b, 0xf203513c, 0xdcba01f5, 0x00040502, 0x00040ed8, 0x00057f70, 0xf23c80ba, 
+    0x00040518, 0x000413e8, 0x00040f1e, 0x00040248, 0x000401e8, 0x0044eb01, 0x7c02f820, 0x1e622000, 
+    0xeb01e005, 0x885b0340, 0x3010f821, 0x42901c40, 0xe008dbf7, 0x0240eb01, 0x2c02f832, 0x2010f821, 
+    0x28001e40, 0x6830dcf6, 0xe9cd2300, 0x20010700, 0x4629461a, 0xf977f7e3, 0x1000f89a, 0xf88a4249, 
+    0xf89b1000, 0xb9080000, 0xfe84f7e9, 0x01c0f242, 0xf7dd0648, 0xf108fd22, 0xf1b80801, 0xf6ff0f04, 
+    0xf7f7ae79, 0x4ca8ffcb, 0x68202100, 0x2038f890, 0x003af9b0, 0xfeb5f7e5, 0xf9b06820, 0xf7e6003e, 
+    0x2301ff13, 0x220f48a1, 0x463903df, 0xfd23f005, 0x4ca04e9f, 0x28057830, 0xf89bd005, 0x465d0000, 
+    0xd00b2801, 0xf44fe00f, 0x78212500, 0xf7e44628, 0x7821fce9, 0xf7e44628, 0xe011fce5, 0xf2427821, 
+    0xf7e40000, 0x2004fcdf, 0xfd66f7f9, 0x46387821, 0xfcd8f7e4, 0xb9187828, 0xfe23f7e5, 0xfe3af7e9, 
+    0x28057830, 0x2149d004, 0x1000f8a9, 0x9ffce8bd, 0xe7f92148, 0x4ff0e92d, 0x1000f9b0, 0xb0892600, 
+    0x52a0f04f, 0x7080f04f, 0xfd09f7dd, 0x01c0f242, 0xf7dd0648, 0x4f80fcc2, 0x4440f649, 0xb9387838, 
+    0x3000f44f, 0x0103f640, 0xfcabf7dd, 0xfc3df7e9, 0xf7f92003, 0xf8dffd31, 0x230091e4, 0x81e0f8df, 
+    0x0a04f04f, 0xf9994977, 0xf8cd0000, 0xeb08a000, 0xeb011240, 0xf7e31140, 0xf242fb11, 0x064801c0, 
+    0xfc9bf7dd, 0xb9307838, 0x496f4870, 0xf7e46800, 0xf7e9fc8f, 0x46cbfdef, 0xf8df46c1, 0x250081a8, 
+    0x0000f99b, 0xd0094285, 0x46282300, 0x1245eb09, 0xa000f8cd, 0x1145eb08, 0xfaf0f7e3, 0xb26d1c6d, 
+    0xdbed2d04, 0x01c0f242, 0xf7dd0648, 0x7838fc76, 0x280146bb, 0x4f57d118, 0x783904c0, 0xfc62f7e4, 
+    0x3900f44f, 0x46487839, 0xfc5cf7e4, 0xfd62f7e9, 0xf44f7839, 0xf7e42080, 0xf640fc55, 0x46480103, 
+    0xfc4ff7dd, 0xfbe1f7e9, 0xf7f92003, 0xf8dffcd5, 0x2700a140, 0xf04f250e, 0xf2400801, 0x95001900, 
+    0x4648220e, 0x46112301, 0x8602e9cd, 0x96059604, 0xf7e59501, 0xf242fa9f, 0x064801c0, 0xfc3df7dd, 
+    0xdd112f01, 0xf7e64842, 0xf8dafb6e, 0x46501000, 0xd20942a1, 0x42a16841, 0x6881d206, 0xd20342a1, 
+    0x000cf8da, 0xd30342a0, 0xb27f1c7f, 0xdbd62f10, 0x0000f89b, 0x4937b920, 0x8000f881, 0xf938f7f9, 
+    0x22034835, 0xf0052138, 0xb108fc44, 0xfb1ef7e4, 0xf8ad2047, 0x48310018, 0x48256802, 0x1000f990, 
+    0xf7ffa806, 0x46c3fd3f, 0x270046a8, 0x220e4655, 0x8000f8cd, 0x46112301, 0xb602e9cd, 0x96044648, 
+    0x8004f8cd, 0xf7e59605, 0x2f00fa55, 0x4820dd0e, 0xfb29f7e6, 0x42a06828, 0x6868d208, 0xd20542a0, 
+    0x42a068a8, 0x68e8d202, 0xd30342a0, 0xb27f1c7f, 0xdbdc2f10, 0xf7e64816, 0x2003fb16, 0xfc5cf7f9, 
+    0x220f2301, 0x46104619, 0xfb03f7e5, 0x68004814, 0xd8052811, 0x2000b009, 0x4ff0e8bd, 0xb814f7e5, 
+    0xe8bdb009, 0x00008ff0, 0x00040598, 0xf2035092, 0x00040ed8, 0x00040243, 0x00040502, 0x00040248, 
+    0x00041508, 0x00041258, 0x001312d0, 0x00040558, 0x000413e8, 0x00040246, 0xf38f007c, 0x00040ef8, 
+    0x000401f0, 0x47f0e92d, 0x35e0f240, 0x4617461e, 0x22054688, 0x48134604, 0xe9dd4629, 0xf0059a08, 
+    0xb2c0fbc8, 0x011ff008, 0x1040ea05, 0xf2404301, 0xea004000, 0x43012087, 0x0000f640, 0x20c6ea00, 
+    0x48094301, 0x41a0f441, 0x00c4eb00, 0xfb83f005, 0xea4a4805, 0x1d004109, 0x00c4eb00, 0x47f0e8bd, 
+    0xbb79f005, 0xf23c821e, 0xf1000200, 0x5ff0e92d, 0xb3f4f8df, 0x8e804604, 0xf8df2600, 0xf240a3f0, 
+    0x4dfb1215, 0xf8df4290, 0xf2a083ec, 0xf8df1115, 0xf8db93e8, 0xd0123000, 0x28dfdc23, 0xdc0fd0fb, 
+    0x2880b3a0, 0x2881d03e, 0x28ded046, 0x48f3d17e, 0x46292200, 0xf0016800, 0x1d40f922, 0xe260d077, 
+    0x7f80f5b0, 0xf5a0d074, 0x38017080, 0x2813d0f7, 0x49e7d16c, 0x46182200, 0xf911f001, 0xd0681d40, 
+    0x48e7e24f, 0x68002969, 0xdc08d07e, 0xd07c291f, 0xd0e42920, 0xd0792933, 0xd1572934, 0x296ae241, 
+    0x2983d0dd, 0x2984d073, 0xe23ad150, 0x49d8e7ff, 0x32fff04f, 0x0008f8d9, 0xf920f001, 0xd1071d01, 
+    0xe2032080, 0x220049d2, 0x0008f8d9, 0xf916f001, 0xd0201d41, 0xd1ea2801, 0x1000f9b5, 0xd1e6296d, 
+    0x17d0074a, 0xfb4bf7dd, 0x464a8868, 0x0000f8a9, 0x1004f9b5, 0x1002f8a9, 0x0006f9b5, 0x0004f8a9, 
+    0x0543b1c0, 0x4fc7d40b, 0x3000f89a, 0x7000f997, 0xd002433b, 0x2081e00e, 0x05c0e1d8, 0x0688d50a, 
+    0x80164630, 0xf040d502, 0xe0010020, 0x0010f040, 0x0000f8a9, 0x0000f898, 0xd00b2801, 0x220648ba, 
+    0xf0052140, 0xb150fb06, 0xe0092702, 0xe04ae1bf, 0xe0ace089, 0x700648b5, 0x700648b5, 0x2700e013, 
+    0x220d48b1, 0x0100f242, 0xfaf3f005, 0x2001b100, 0x2f014307, 0x2000d01e, 0x2f0249ac, 0xd01b7008, 
+    0x49ab2000, 0xe0037008, 0xe0cbe172, 0xe195e0ed, 0x0000f9b9, 0x04c24649, 0xf420d52c, 0xf2415080, 
+    0xf8a90700, 0x220c0000, 0x463948a2, 0xfad1f005, 0xe01ab120, 0xe7df2001, 0xe7e22001, 0x7800489e, 
+    0x4a9eb198, 0x46392005, 0xfad9f7dd, 0x8028203b, 0x22004892, 0x6800498e, 0xf861f001, 0xf47f1d01, 
+    0x20deaf3c, 0x20dfe172, 0x4a94e170, 0xf2412005, 0xe1940101, 0x06824f92, 0xf020d55c, 0x80080020, 
+    0x0002f899, 0x06804a8d, 0x2005d537, 0x0120f242, 0xfab5f7dd, 0x703e488b, 0x28017800, 0x488ad00f, 
+    0x28017800, 0x4889d00b, 0x28018800, 0x4888d007, 0x28017800, 0x487bd003, 0x28017800, 0xf89ad106, 
+    0xb9180000, 0x0000f898, 0xd0752800, 0x80282071, 0x2200496f, 0x0000f8db, 0xf821f001, 0xd1071d01, 
+    0x1000f240, 0x496ae132, 0x46182200, 0xf817f001, 0xd1611d40, 0x1001f240, 0x2120e128, 0xf7dd2005, 
+    0xf89afa7e, 0x28010000, 0xf898d0df, 0x28000000, 0x2007d0db, 0x495e8028, 0xf8db2200, 0xf0000000, 
+    0x1d01fffe, 0xaeeaf47f, 0x1014f240, 0xf240e10e, 0xe10b1015, 0xd56206c2, 0x0010f020, 0xf8998008, 
+    0x4a5e0002, 0xd53806c0, 0xf2422005, 0xf7dd0110, 0x485cfa56, 0x7800703e, 0xd00f2801, 0x7800485a, 
+    0xd00b2801, 0x88004859, 0xd0072801, 0x78004858, 0xd0032801, 0x7800484b, 0xd1062801, 0x0000f89a, 
+    0xf898b918, 0x28000000, 0x2070d016, 0x49408028, 0xf8db2200, 0xf0000000, 0x1d01ffc2, 0xf240d107, 
+    0xe0d31034, 0x2200493a, 0xf0004618, 0x1d40ffb8, 0xf240d102, 0xe0c91035, 0x2110e048, 0xf7dd2005, 
+    0xf89afa1e, 0x28010000, 0xf898d040, 0xb3e80000, 0x80282007, 0x2200492e, 0x0000f8db, 0xff9ff000, 
+    0xd1071d01, 0x1048f240, 0x4929e0b0, 0x46182200, 0xff95f000, 0xd1291d40, 0x1049f240, 0x0442e0a6, 
+    0xf420d574, 0x80084080, 0x0002f8b9, 0x04404a2b, 0x2102d577, 0xf7dd2005, 0x482ef9f2, 0x7800703e, 
+    0x482db148, 0x482d7801, 0x482d7803, 0x482d7802, 0xf7e77800, 0x4824fbed, 0x78004922, 0x1000f991, 
+    0x49184308, 0x1000f991, 0xe0004308, 0xd103e01b, 0xfb62f7de, 0xfe98f7f6, 0x88004823, 0x480cb198, 
+    0x22002173, 0x80013010, 0x70812101, 0x7809491a, 0x460170c1, 0x6800480a, 0xff51f000, 0xd13b1d01, 
+    0x107ef240, 0xe076e062, 0x000406cc, 0x0004023d, 0x0004d6d4, 0x0004023c, 0x00041144, 0x00040eb0, 
+    0x00040ea4, 0x00040235, 0xf38fffc0, 0x000401f8, 0x000401f9, 0xf203902c, 0x000401fd, 0xcccc0000, 
+    0x0004059e, 0x00040529, 0x0004052b, 0x00040236, 0x0004023a, 0x000404ed, 0x00040242, 0x0004059d, 
+    0x0004059c, 0x000404ec, 0x0004031c, 0xe008e031, 0x22004937, 0xff13f000, 0xd1521d40, 0x107ff240, 
+    0x2103e024, 0xf7dd2005, 0xf7def97a, 0xf7f6fb05, 0x4830fe51, 0xb3708800, 0x2173482d, 0x80012200, 
+    0x7086492d, 0x70c17809, 0x482c4601, 0xf0006800, 0x1d01fef6, 0xf240d106, 0xe0071098, 0x22004924, 
+    0xfeedf000, 0xd12c1d40, 0x1099f240, 0xe8bd86a0, 0x07429ff0, 0xf020d525, 0xf8a90004, 0xf8980000, 
+    0x28010000, 0x481ed104, 0xf0308800, 0xd0030040, 0x21084a1c, 0xe014e012, 0x21044f1a, 0x463a4608, 
+    0xf93df7dd, 0x22024818, 0xf0052104, 0x2801f922, 0x2004d00d, 0xf88ff7e4, 0x463a2106, 0xf7dd2004, 
+    0xf8b9f92e, 0x28000000, 0xae18f47f, 0x2105e5bf, 0xe7f3463a, 0x21012200, 0xf2afb510, 0xf000502f, 
+    0x2108fcf9, 0xf0002004, 0x4908fe57, 0xbd106088, 0x0004d6e4, 0x0004031c, 0x00040242, 0x00040ea4, 
+    0x00040240, 0xcccc0000, 0xf2039026, 0x00041144, 0x4ef0e92d, 0x4606b09e, 0xf8df2500, 0xf240a420, 
+    0xf88d3276, 0x9518506c, 0x8e80951c, 0xf2a04290, 0xd07d3176, 0xb150dc05, 0xd01428ce, 0xd17828cf, 
+    0x2901e01c, 0x29b8d076, 0x29b9d075, 0x49fbd171, 0x32fff04f, 0x001cf8da, 0xf0003124, 0x1d01fe9f, 
+    0x20ced108, 0x49f5e379, 0xf8da2200, 0x3124001c, 0xfe94f000, 0xd0111d41, 0xd1e82801, 0x302448ef, 
+    0x28658800, 0x48eed1e3, 0x22022301, 0xf0052104, 0x48ecf8a2, 0x28027800, 0xe012d002, 0xe35c20cf, 
+    0x780048e9, 0xd10c2801, 0xb3a0f8df, 0x0000f89b, 0x2801b1e0, 0x2802d024, 0x2803d029, 0xf88bd07e, 
+    0x22085000, 0x015148e2, 0xf893f005, 0xd0762800, 0x0008f8ba, 0x1c40210a, 0xf8aab280, 0xfbb00008, 
+    0xfb01f2f1, 0x28000012, 0xe1dcd06a, 0xfc07f7e9, 0xf88b2001, 0x48d70000, 0x48d77005, 0xe7e07005, 
+    0xfc3ff7e9, 0x2002b108, 0x2001e05d, 0xf7e9e05b, 0x2800fc45, 0xf7e9d0f7, 0x2100fbe2, 0x3080f44f, 
+    0xf830f7e4, 0xc334f8df, 0x4ccd2000, 0xe0032200, 0xe3f9e314, 0xe3f8e22b, 0x01c0eb04, 0x2200e9c1, 
+    0x01c0eb0c, 0x28041c40, 0x2200e9c1, 0x2700dbee, 0xf7e9a819, 0x4668fbe4, 0xfbfaf7e9, 0xa8192400, 
+    0x0014f830, 0xf872f007, 0x22004bbe, 0xfea2f006, 0xeb024aba, 0x469903c4, 0xf006cb0c, 0xe9c9fddf, 
+    0x46680100, 0xeb004bb7, 0x220000c4, 0x0100e9d0, 0xfe90f006, 0xeb024ab2, 0x469903c4, 0xf006cb0c, 
+    0x1c64fdcd, 0xe9c92c04, 0xdbd80100, 0xf2402100, 0xf7e32000, 0x1c7fffe7, 0xe0022f64, 0xe169e006, 
+    0xdbc5e09c, 0xf88b2003, 0xe77a0000, 0xf10d2000, 0xac100c20, 0xeb042200, 0xe9c101c0, 0xeb0c2200, 
+    0x1c4001c0, 0xe9c12804, 0xdbf32200, 0xa8192700, 0xfb95f7e9, 0xf7e94668, 0x2400fbab, 0xf830a819, 
+    0xf0070014, 0x4b97f823, 0xf0062200, 0xaa08fe53, 0x03c4eb02, 0xcb0c4699, 0xfd90f006, 0x0100e9c9, 
+    0x4b904668, 0x00c4eb00, 0xe9d02200, 0xf0060100, 0xaa10fe41, 0x03c4eb02, 0xcb0c4699, 0xfd7ef006, 
+    0x2c041c64, 0x0100e9c9, 0x2100dbd8, 0x2000f240, 0xff98f7e3, 0x2f641c7f, 0x2700dbc9, 0xa808463c, 
+    0x00c4eb00, 0x2300e9d0, 0xeb00487c, 0xe9d101c4, 0x46810100, 0xf007911d, 0xf006fa45, 0x2800ff73, 
+    0x4240da00, 0xffcbf006, 0x464a9b1d, 0xfe12f006, 0xe9d34b75, 0xf0072300, 0xd206f927, 0x7808496d, 
+    0xd00128ff, 0x70081c40, 0x486d2701, 0x00c4eb00, 0x2300e9d0, 0xeb00a810, 0xe9d101c4, 0xf0060100, 
+    0x4b6afdf9, 0x2300e9d3, 0xf90ef007, 0x4962d206, 0x28ff7808, 0x1c40d001, 0x27017008, 0x2c041c64, 
+    0x2f00dbbd, 0xaf6ef43f, 0xfb09f7e9, 0xf44f2100, 0xf7e33000, 0xf7e9ff47, 0xe704faf2, 0x7800485c, 
+    0xd17d2802, 0xf004485b, 0xb2c4ff49, 0x000ff004, 0xd176280a, 0xfcb1f7f6, 0x915cf8df, 0xd0382801, 
+    0x4f544856, 0xf9903724, 0x28030000, 0x2805d043, 0x2804d041, 0x2300d03f, 0x22044638, 0xf0042110, 
+    0x484cff4a, 0xf004301e, 0x4607ff29, 0x301c4849, 0xff24f004, 0x4b00ea47, 0x30224846, 0xff1ef004, 
+    0x48444607, 0xf0043020, 0xea47ff19, 0x90004000, 0xebb02003, 0xd1201f14, 0x1014f8da, 0xf7f64658, 
+    0xf8dafc72, 0x46071018, 0xf7f69800, 0x4438fc6c, 0xf88de024, 0x27fe506c, 0x1000f89a, 0xd10729fe, 
+    0x0002f89a, 0xd1034284, 0x0000f899, 0xd13c2801, 0x32fff04f, 0x2301e065, 0x2001e7be, 0x1f14ebb0, 
+    0xf8dad103, 0x46581014, 0x2002e006, 0x1f14ebb0, 0xf8dad105, 0x98001018, 0xfc45f7f6, 0xa91b9018, 
+    0xb014f8ca, 0xf8ca9800, 0x98180018, 0xfc0ef7f6, 0xf89a4607, 0x42a00002, 0xf899d142, 0xe0010000, 
+    0xe018e051, 0xd03b2801, 0x1000f89a, 0xd105428f, 0x106cf89d, 0x0001f89a, 0xd0064281, 0xb2614809, 
+    0xf9909a18, 0xf7f60000, 0xf88af846, 0xf89d7000, 0xf88a106c, 0xf88a1001, 0xe0344002, 0x00041150, 
+    0xf23c8318, 0x00040242, 0x00040318, 0x00040304, 0xf38f2002, 0x00040305, 0x00040306, 0x0004d118, 
+    0x0004d138, 0x40590000, 0x00040308, 0x00040310, 0x0004052a, 0xf23c80d2, 0x000402f9, 0x000401fc, 
+    0xb2619a18, 0xf99048f7, 0xf7f60000, 0xf889f814, 0xe7ca5000, 0x5008f8aa, 0xf88a21fd, 0xf88a1002, 
+    0xf88a1000, 0x220f1001, 0xf24848ef, 0xf0040100, 0xbb70fea0, 0x0010f8ba, 0x1c404654, 0xf8aab280, 
+    0x07010010, 0xf000d00a, 0x2801000f, 0x2802d00c, 0x2803d011, 0x2804d016, 0xe023d01c, 0xf0022000, 
+    0xb281ff07, 0xe01b48e1, 0xf0022001, 0xb281ff97, 0x1c8048de, 0x2004e014, 0xfefaf002, 0x48dbb281, 
+    0xe00d1d00, 0xf0022005, 0xb281fef3, 0x1d8048d7, 0xe031e006, 0xf0022006, 0xb281feeb, 0x300848d3, 
+    0xfe3ff004, 0x49d348d2, 0x78004fd3, 0xd0022801, 0x2a01680a, 0x7c22d114, 0xd11d0712, 0x28014acf, 
+    0x6813d102, 0xda114598, 0x29016809, 0x49ccd00a, 0xda114541, 0xd0282801, 0x70fff647, 0xdd0b4540, 
+    0xe0042300, 0x680949c7, 0xdc1a4588, 0x46382301, 0x21022201, 0xfe2ff004, 0xf99048c3, 0x28030000, 
+    0x2805d018, 0x2804d016, 0xf8aad014, 0x2723500e, 0x780048be, 0xd07d2801, 0x1003f89a, 0xd17a2900, 
+    0x4bbbe1b2, 0x4419681b, 0x49bae7d2, 0x68096810, 0xe7d31a40, 0x000ef8ba, 0xf8aa1c40, 0x48b6000e, 
+    0xfdecf004, 0x04c04604, 0xf89ad507, 0xf000000e, 0x28050007, 0xf7f4d101, 0x0620fbbd, 0x48afd518, 
+    0x28017800, 0xf7f8d005, 0x48adfc9d, 0xb1387800, 0xf89ae00b, 0x06c0000e, 0xf7f8d10a, 0xe007fc93, 
+    0x780048a8, 0x2001b108, 0x2000e000, 0xf8daf7e9, 0xd50c0720, 0x780048a4, 0xd1062801, 0x780048a3, 
+    0xf89ab918, 0x06c0000e, 0xf7f8d101, 0x0420fad1, 0xf8bad515, 0x4657000e, 0xd1010580, 0xfbf0f7e3, 
+    0xf0107bb8, 0xd10a0f05, 0x78384f99, 0xf7e3b138, 0x4998fcad, 0x703d2001, 0xf7e37008, 0x4896fbe1, 
+    0x28017800, 0x4895d158, 0x28017800, 0xf89ad154, 0x4a930005, 0xb2c01c40, 0x0005f88a, 0x42907812, 
+    0x4890d94a, 0xf88a46d1, 0x78005005, 0xd02a2801, 0xe0012802, 0xe070e06d, 0x488bd025, 0xfd7ef004, 
+    0x48894607, 0xf0041c80, 0xf8d9fd79, 0xea471020, 0x4b864000, 0x42884f86, 0x781ad005, 0x40912101, 
+    0x4311683a, 0x78196039, 0xb2ca1c49, 0x701a4981, 0x428a7809, 0x701dd300, 0xf8c92200, 0x46100020, 
+    0x2701683b, 0x4878e010, 0xf0041f00, 0x4607fd57, 0x1e804875, 0xfa07e7d7, 0xea1cfc00, 0xd0010f03, 
+    0xb2d21c52, 0xb2c01c40, 0xd3f44288, 0x78004872, 0xd9014282, 0x901c2001, 0xd5090560, 0x000ef89a, 
+    0xd1050700, 0x1f80485c, 0xfd38f004, 0xd10307c0, 0x2801981c, 0xaf2bf47f, 0x901c2000, 0xfe4ef7fb, 
+    0x21434866, 0x80012200, 0x48654601, 0xf0006800, 0x1d01faf6, 0xf240d108, 0xe0f23076, 0x22004860, 
+    0x6800495e, 0xfaebf000, 0xd1e31d40, 0x3077f240, 0xf89ae0e7, 0x46540003, 0xf89ab1a0, 0x46540003, 
+    0xd0312801, 0xfecef7e7, 0x71a02121, 0x28002222, 0x000af9b4, 0x2823d051, 0x2822d02f, 0x2821d034, 
+    0xe041d039, 0x1c407920, 0x7120b2c0, 0xd3172828, 0x2205484c, 0xf0042120, 0xb928fd1c, 0x384e482e, 
+    0xfcecf004, 0xd00c07c0, 0x28238960, 0x2300d007, 0x22018167, 0x46184619, 0xf7f79500, 0x7125fc0f, 
+    0x2001e094, 0xe7fa70e0, 0xf7e72003, 0x2001fb98, 0xfe28f7e7, 0x70e02002, 0x2300e088, 0x22018162, 
+    0x46104619, 0xe00d9500, 0x81612300, 0x46192201, 0x95002002, 0x2020e006, 0x23008160, 0x22019500, 
+    0x20034619, 0xfbeaf7f7, 0x1c4089a0, 0x4812b281, 0x384c81a1, 0xfcb5f004, 0x2820e05e, 0x2821d004, 
+    0x2822d009, 0xe057d050, 0x81612300, 0x46192201, 0x95002002, 0x2300e04e, 0x22018162, 0x46104619, 
+    0xe0479500, 0x00040242, 0xf2020000, 0xf23d0142, 0x000402b3, 0x000402bc, 0xf20351da, 0x000402b4, 
+    0xffff8001, 0x000402c0, 0x000401fc, 0x0004059e, 0x000402c4, 0x000402b8, 0xf23c80b8, 0x00040247, 
+    0x00040502, 0x0004027b, 0x00040246, 0x00040f1c, 0x00040260, 0x00040261, 0x00040287, 0x00040286, 
+    0x00040567, 0x0004057b, 0xf2036116, 0x00040564, 0x00040560, 0x00040565, 0x00040566, 0x00041174, 
+    0x00040f10, 0xf38f2034, 0x81672300, 0x46192201, 0x95004618, 0xfb82f7f7, 0xf7e72002, 0x2000fb10, 
+    0xfda0f7e7, 0xe00170e5, 0x5004f88a, 0x48162129, 0x80012200, 0x48154601, 0xf0006800, 0x1d01fa10, 
+    0xf240d10a, 0xe00c402e, 0xe7ffe00c, 0x2200480f, 0x6800490d, 0xfa03f000, 0xf47f1d40, 0xf240ab88, 
+    0x86b0402f, 0xe8bdb01e, 0x22008ef0, 0xb5102101, 0x1043f6af, 0xf83ef000, 0x200a2108, 0xf99cf000, 
+    0x39244901, 0xbd1061c8, 0x00041174, 0x00040e94, 0xb5082008, 0xfcbdf7e3, 0x90002000, 0x46032201, 
+    0x20084601, 0xfcfaf7e3, 0x20084908, 0xfcc0f7e3, 0xf7e34807, 0x2008fd16, 0xfcbff7e3, 0xf2462201, 
+    0xe8bd11a8, 0x20034008, 0xbbbaf7e3, 0x000249d0, 0xf0001184, 0xf8bcf000, 0x8e80e7fc, 0xd1012800, 
+    0xbbc8f005, 0x22004770, 0xf2af4611, 0xf0000011, 0x0000b801, 0x47f0e92d, 0x460e4691, 0x20384682, 
+    0xfc20f000, 0xd0440004, 0xf8df4f86, 0x6838821c, 0x2500b9d8, 0xeb05603c, 0xeb080185, 0xf0000081, 
+    0x1c6df905, 0xd3f62d02, 0x3028487f, 0xf8fef000, 0x303c487d, 0xf8faf000, 0x3050487b, 0xf8f6f000, 
+    0x30284879, 0x30146178, 0x2e0261b8, 0x2601d300, 0x86a02000, 0xa000f8c4, 0xe9c41d20, 0xf000690b, 
+    0xf104f8f0, 0xf0000018, 0x6124f8ec, 0x000af1c6, 0x61a06264, 0x68796ae0, 0xd9004288, 0xeb006078, 
+    0xeb080180, 0x1d210081, 0xf8def000, 0xe8bd2001, 0xf04f87f0, 0xe7fa30ff, 0x4d62b570, 0x68a9460e, 
+    0x6828180c, 0xf0001d00, 0x6829f8f5, 0x68a8604c, 0xd2014284, 0xe00069a8, 0x1d096968, 0xf8d2f000, 
+    0xd0062e00, 0x46306829, 0x4070e8bd, 0xf0003118, 0xbd70b8c9, 0xf000b570, 0x4d52fb2d, 0x1a4068e9, 
+    0xe02f6128, 0x0101f1a1, 0x1c406129, 0xd10360a8, 0x1005e9d5, 0x0105e9c5, 0x69684e4b, 0xb1f16801, 
+    0x68c468c0, 0x6860e01c, 0x428868a9, 0xb672d81a, 0xf0001d20, 0x6aa0f8bf, 0xf104b118, 0xf0000018, 
+    0xb662f8b9, 0x68696ae0, 0xd9004288, 0xeb006068, 0x1d210080, 0x0080eb06, 0xf886f000, 0x2400e7dd, 
+    0xd1e02c00, 0x68a86929, 0xd1cb2900, 0xbd7060e8, 0xf000b510, 0xf7fff840, 0x4932ffbd, 0x68484a32, 
+    0x2800e003, 0x1e40d01b, 0xeb006048, 0xf8520380, 0x2b003023, 0xeb00d0f5, 0xeb020080, 0x68420080, 
+    0xf1006852, 0x60420308, 0xd101429a, 0x60426852, 0x600868d0, 0x6b016802, 0x4010e8bd, 0xbd104710, 
+    0x6801b570, 0x68c0b111, 0xe00068c4, 0xf1042400, 0x46050018, 0xf86ef000, 0x4629481b, 0xf0003050, 
+    0x4918f843, 0x68096ae0, 0x42886ac9, 0x2001d301, 0x2000bd70, 0xe92dbd70, 0x4d1341f0, 0x4f124e11, 
+    0xe01a3550, 0x6828b672, 0x68e8b110, 0xe00068c4, 0xf1042400, 0xf0000018, 0xb662f84d, 0xf0001d20, 
+    0x6ae0f849, 0x42886871, 0x6070d900, 0x0080eb00, 0xeb071d21, 0xf0000080, 0x6828f817, 0xd1e12800, 
+    0x81f0e8bd, 0x0004117c, 0x0004d6f0, 0x32fff04f, 0x0108f100, 0x1201e9c0, 0x610160c1, 0x60012100, 
+    0x21004770, 0x47706101, 0x68536842, 0x6843604b, 0x6853608b, 0x60516099, 0x61086041, 0x1c496801, 
+    0x47706001, 0x680bb510, 0xd0021c5a, 0x0208f100, 0x6902e002, 0x6852e004, 0x68246854, 0xd9fa429c, 
+    0x604b6853, 0x608a6099, 0x61086051, 0x1c496801, 0xbd106001, 0x1201e9d0, 0xe9d0608a, 0x60511201, 
+    0x684a6901, 0xd1014282, 0x604a6882, 0x61022200, 0x1e406808, 0x47706008, 0x0005b570, 0xd028460e, 
+    0xf000204c, 0x0004fabf, 0xfb05d023, 0x1c40f006, 0xfab8f000, 0xb1c86020, 0x0106fb05, 0x21006061, 
+    0x1e6963a1, 0xfb0160a0, 0x63e50006, 0xf04f60e0, 0xe9c430ff, 0x64a06010, 0x0010f104, 0xff96f7ff, 
+    0x0024f104, 0xff92f7ff, 0xbd704620, 0xf0004620, 0x2000faa5, 0xb510bd70, 0x6c024613, 0xb16a4604, 
+    0x68e0b183, 0xebfef003, 0x6c2068e1, 0x60e11a09, 0x42916822, 0x6861d202, 0x60e01a08, 0x1c406ba0, 
+    0xbd1063a0, 0xf00368a0, 0x6c21ebee, 0x440868a0, 0x686160a0, 0xd3f14288, 0x60a06820, 0xb570e7ee, 
+    0x460e4615, 0xb6724604, 0xf875f000, 0xb145b160, 0x0110f104, 0xf7ff4628, 0xb662fe8f, 0x0003f06f, 
+    0xb662bd70, 0xbd702000, 0xbf00b662, 0x6ba0b672, 0x42886be1, 0x2200d20e, 0x46204631, 0xffbbf7ff, 
+    0x25016a60, 0xf104b138, 0xf7ff0024, 0xb110fef9, 0xe0001fad, 0xb6622500, 0xbd704628, 0x460bb570, 
+    0xb6724604, 0xb1f06b80, 0xbf00b662, 0x6ba0b672, 0x6c22b330, 0x441068e0, 0x686160e0, 0xd3014288, 
+    0x60e06820, 0x1e406ba0, 0x68e163a0, 0xf0034618, 0x6920eb9a, 0xb1a02501, 0x0010f104, 0xfed0f7ff, 
+    0x1fadb178, 0xb142e00d, 0x0124f104, 0xf7ff4610, 0xb662fe43, 0x0003f06f, 0xb662bd70, 0xbd702000, 
+    0xb6622500, 0xbd704628, 0x4604b570, 0x46156b80, 0x42906be2, 0x2200d20d, 0xf7ff4620, 0xb945ff6c, 
+    0xb1306a60, 0x0024f104, 0xfeaaf7ff, 0x2001b108, 0x4628bd70, 0xb510bd70, 0xf0004604, 0x6ba0fa54, 
+    0x42886be1, 0x2401d101, 0x2400e000, 0xfa51f000, 0xbd104620, 0x680148ed, 0x6800b111, 0x47706b00, 
+    0x47702000, 0x5ff0e92d, 0x4615469a, 0x46834689, 0xe9dd2058, 0xf000680a, 0x0004f9d5, 0x00afd009, 
+    0xf0004638, 0x6320f9cf, 0x22a5b3d8, 0xf0034639, 0x2c00fbaf, 0x6b21d07e, 0x0003f06f, 0x0085eb00, 
+    0x44084635, 0xf0204649, 0x22200707, 0x0034f104, 0xebcef003, 0xf8842000, 0x2d0a0053, 0x2509d300, 
+    0x1d2062e5, 0xfeadf7ff, 0x0018f104, 0xfea9f7ff, 0xf1c56124, 0x6264010a, 0x46384652, 0x465961a1, 
+    0xf9baf000, 0xf0006020, 0x4fc8f9fe, 0x1c4068b8, 0x68b860b8, 0x9318f8df, 0xd0082801, 0xb35069b8, 
+    0xe7ffe02e, 0xf0004620, 0x2400f999, 0x603ce7c1, 0xeb052500, 0xeb090185, 0xf7ff0081, 0x1c6dfe77, 
+    0xd3f62d0a, 0x30c848ba, 0xfe70f7ff, 0x30dc48b8, 0xfe6cf7ff, 0x30f048b6, 0xfe68f7ff, 0xf7ff48b5, 
+    0x48b4fe65, 0xf7ff3014, 0x48b2fe61, 0x63b8383c, 0x63f83014, 0x6838e004, 0x42b06ac0, 0x603cd800, 
+    0x69396ae0, 0xd9004288, 0x6af96138, 0x1c496561, 0x697962f9, 0xd9004288, 0xeb006178, 0xeb090180, 
+    0x1d210081, 0xfe50f7ff, 0xf0002501, 0xf1b8f9b2, 0xe0000f00, 0xd001e00c, 0x4000f8c8, 0xb12069b8, 
+    0x6ac06838, 0xd20042b0, 0x4628df00, 0x9ff0e8bd, 0x35fff04f, 0xb570e7f9, 0x69e84d94, 0x6a28b118, 
+    0x62281c40, 0x68e8bd70, 0x60e81c40, 0xb93068e8, 0x6be96ba8, 0x63e863a9, 0x1c406aa8, 0x4e8c62a8, 
+    0x6860e018, 0x428868e9, 0x1d20d8ec, 0xfe42f7ff, 0xb1186aa0, 0x0018f104, 0xfe3cf7ff, 0x69696ae0, 
+    0xd9004288, 0xeb006168, 0x1d210080, 0x0080eb06, 0xfe0af7ff, 0x68006ba8, 0x6ba8b118, 0x68c468c0, 
+    0x2400e000, 0xd1dc2c00, 0xe92dbd70, 0x270047f0, 0xf959f000, 0x69f04e75, 0x61f01e40, 0xbb7869f0, 
+    0xb36868b0, 0x81ccf8df, 0xf8df2500, 0xf1a891c4, 0xe0180814, 0x0018f104, 0xfe0cf7ff, 0xf7ff1d20, 
+    0x6ae0fe09, 0x42886971, 0x6170d900, 0x0180eb00, 0x0081eb09, 0xf7ff1d21, 0x6ae0fdd7, 0x6ac96831, 
+    0xd3004288, 0xf8d82501, 0x46401000, 0x68c0b111, 0xe00068c4, 0x2c002400, 0x6a30d1dc, 0xe008b930, 
+    0xf7ffe00f, 0x6a30ff88, 0x62301e40, 0x28006a30, 0xb915d1f7, 0x28016a70, 0x2701d103, 0x62702000, 
+    0xf000df00, 0x4638f916, 0x87f0e8bd, 0x69c1484f, 0x61c11c49, 0xf0004770, 0xdf00f870, 0xfc6af7ff, 
+    0xb51fe7f9, 0x484e2400, 0x4623a14b, 0x2200f240, 0x94019400, 0x94039402, 0xfeb4f7ff, 0xd1082801, 
+    0x2101b672, 0x61814841, 0xe8bd60c4, 0xf000401f, 0xbd1fb8e3, 0xf000b510, 0x483cf8e6, 0xf00068c4, 
+    0x4620f8e8, 0x4939bd10, 0x4a3969c8, 0x2001b120, 0x47706248, 0x61481e40, 0xeb006948, 0xf8520080, 
+    0x28000020, 0xd0f56948, 0x0080eb00, 0x0080eb02, 0x68526842, 0x0308f100, 0x429a6042, 0x6852d101, 
+    0x68d06042, 0x6b086008, 0xd0e22800, 0x6b4a6808, 0x42906d40, 0x6c08d0dd, 0x30086c8a, 0xd20f4290, 
+    0x6d406808, 0x68c86348, 0x60106c0a, 0x1d006c08, 0x6c0a6408, 0x60106b48, 0x1d006c08, 0x47706408, 
+    0x63082000, 0xb5104770, 0x6b004604, 0xf846f000, 0xe8bd4620, 0xf0004010, 0xb570b841, 0x68684d13, 
+    0xd0222800, 0xff82f7ff, 0x68304e12, 0x2400b158, 0xff2bf7ff, 0xd1182c00, 0xf885f000, 0xb1206830, 
+    0x68c468f0, 0x2401e002, 0x2400e7f2, 0xf7ff1d20, 0x68a8fd41, 0x60a81e40, 0x1e406868, 0xf0006068, 
+    0x4620f878, 0x4070e8bd, 0xbd70e7cd, 0x00041198, 0x0004d754, 0x0004d858, 0x454c4449, 0x00000000, 
+    0x00024797, 0x4604b510, 0xff50f7ff, 0xf0034620, 0x4604f8bd, 0xfef9f7ff, 0xbd104620, 0x0004b510, 
+    0xf7ffd008, 0x4620ff43, 0xf8dff003, 0x4010e8bd, 0xbeebf7ff, 0x0000bd10, 0x60011d09, 0xf04f1f01, 
+    0x600b33aa, 0xf04f1f09, 0x60083312, 0x600b1f09, 0xf04f1f09, 0x600b3311, 0xf04f1f09, 0x600b3310, 
+    0xf04f1f09, 0x600b3309, 0xf04f1f09, 0x600b3308, 0xf04f1f09, 0x600b3307, 0xf04f1f09, 0x600b3306, 
+    0xf04f1f09, 0x600b3305, 0xf04f1f09, 0x600b3304, 0xf04f1f09, 0x600b3303, 0xf04f1f09, 0x600b3302, 
+    0x105b1f09, 0x1f09600b, 0x1f09600a, 0x600a223f, 0xf8402100, 0x47701d44, 0xf7ffb510, 0xf003fb49, 
+    0x2000ef92, 0xb672bd10, 0x68414808, 0x60411c49, 0x48064770, 0x29006841, 0x6841d006, 0x60411e49, 
+    0x28006840, 0xb662d100, 0x00004770, 0x000411e4, 0xe92d503f, 0xe59f0068, 0xfa000f9f, 0xfbffff24, 
+    0xe59f4060, 0xe1d400b0, 0xe2800001, 0xe6ff0070, 0xe1c400b0, 0xe3500b01, 0x3a00000c, 0xe2841008, 
+    0xe3a00065, 0xe3a02000, 0xe1c100b0, 0xe59f0038, 0xe5900000, 0xfafffeab, 0xe59f1030, 0xe5912000, 
+    0xe0800002, 0xe5810000, 0xe3a00000, 0xe1c400b0, 0xe59f001c, 0xfbff8c11, 0xf57ff05f, 0xe8bd503f, 
+    0xe25ef004, 0xf23c824a, 0x000411e4, 0x0004116c, 0x000401f4, 0xf0001184, 0x21012300, 0xb510461a, 
+    0xf00348fe, 0x48fdff18, 0x220e2300, 0x0100f244, 0x4010e8bd, 0xf0033010, 0xe92dbf0e, 0x48f75ff0, 
+    0x011af24a, 0xf003301e, 0x48f4feec, 0x3100f240, 0xf0033020, 0x4cf2fee6, 0x01eff243, 0x302248ef, 
+    0xf0037822, 0x48edfede, 0x3184f249, 0xf0033026, 0x48eafed8, 0x30282100, 0xfed3f003, 0xf24448e7, 
+    0x302c0100, 0xfecdf003, 0xf24348e4, 0x302e0100, 0xfec7f003, 0xf2417820, 0x4ce01115, 0x2712f241, 
+    0x1ca53430, 0x1d264620, 0xfebbf003, 0x46284639, 0xfeb7f003, 0x46302113, 0xfeb3f003, 0x21001da7, 
+    0xf0034638, 0xf105feae, 0xf2470806, 0x46404121, 0xfea7f003, 0x0906f106, 0x46482100, 0xfea1f003, 
+    0x0b06f107, 0x0a00f241, 0x46584651, 0xfe99f003, 0x0006f108, 0x2100f64a, 0xfe93f003, 0xf24448c7, 
+    0x304e01ff, 0xfe8df003, 0x46511fa0, 0xfe89f003, 0x1fa02100, 0xfe85f003, 0x46202100, 0xfe81f003, 
+    0x46282100, 0xfe7df003, 0x46302100, 0xfe79f003, 0x46382100, 0xfe75f003, 0x46402100, 0xfe71f003, 
+    0x46482100, 0xfe6df003, 0x46582100, 0xfe69f003, 0xf1082100, 0xf0030006, 0x48b0fe64, 0x304e2100, 
+    0xfe5ff003, 0x412df643, 0xf0034620, 0xf642fe5a, 0x46281128, 0xfe55f003, 0x46302174, 0xfe51f003, 
+    0xf24848a6, 0x304e0107, 0xfe4bf003, 0x46511fa0, 0xfe47f003, 0x1fa02100, 0xfe43f003, 0x46202100, 
+    0xfe3ff003, 0x46282100, 0xfe3bf003, 0x46302100, 0xfe37f003, 0x21004899, 0xf003304e, 0x2103fe32, 
+    0xf0034620, 0xf240fe2e, 0x46285140, 0xfe29f003, 0x6140f640, 0xf0034630, 0xf640fe24, 0x46380141, 
+    0xfe1ff003, 0x3144f241, 0xf0034640, 0xf108fe1a, 0xf2450006, 0xf003011c, 0x2140fe14, 0x0006f109, 
+    0xfe0ff003, 0x0006f10b, 0x113bf645, 0xfe09f003, 0xf2404882, 0x30444100, 0xfe03f003, 0x1fa021d0, 
+    0x5ff0e8bd, 0xbdfdf003, 0x5ff0e92d, 0xf24a487b, 0x301e011a, 0xfdf5f003, 0xf2404878, 0x30203100, 
+    0xfdeff003, 0x21ef4875, 0xf0033022, 0x4873fdea, 0x3104f241, 0xf0033026, 0x4870fde4, 0x1180f240, 
+    0xf0033028, 0x486dfdde, 0x0100f244, 0xf003302c, 0x486afdd8, 0x0100f243, 0xf003302e, 0x4c67fdd2, 
+    0x1105f240, 0x46203430, 0xfdcbf003, 0xf2401ca5, 0x46282102, 0xfdc5f003, 0x0904f104, 0x4648210f, 
+    0xfdbff003, 0x0a06f104, 0x5100f240, 0xf0034650, 0xf105fdb8, 0xf2470b06, 0x4658318e, 0xfdb1f003, 
+    0x0606f109, 0x0800f241, 0x46304641, 0xfda9f003, 0x46411cb7, 0xf0034638, 0x1d30fda4, 0x2100f64a, 
+    0xfd9ff003, 0xf244484d, 0x304e01ff, 0xfd99f003, 0x46411fa0, 0xfd95f003, 0x1fa02100, 0xfd91f003, 
+    0x46202100, 0xfd8df003, 0x46282100, 0xfd89f003, 0x46482100, 0xfd85f003, 0x46502100, 0xfd81f003, 
+    0x46582100, 0xfd7df003, 0x46302100, 0xfd79f003, 0x46382100, 0xfd75f003, 0x1d302100, 0xfd71f003, 
+    0x21004836, 0xf003304e, 0xf243fd6c, 0x46205114, 0xfd67f003, 0x1130f243, 0xf0034628, 0x210bfd62, 
+    0xf0034648, 0x2106fd5e, 0xf0034630, 0x482bfd5a, 0x0127f248, 0xf003304e, 0x1fa0fd54, 0xf0034641, 
+    0x2100fd50, 0xf0031fa0, 0x2100fd4c, 0xf0034620, 0x2100fd48, 0xf0034628, 0x2100fd44, 0xf0034648, 
+    0x2100fd40, 0xf0034658, 0x2100fd3c, 0xf0034630, 0x2100fd38, 0xf0031d30, 0x1dbefd34, 0x46302100, 
+    0xfd2ff003, 0x21004815, 0xf003304e, 0x2101fd2a, 0xf0034620, 0xf240fd26, 0x46285140, 0xfd21f003, 
+    0x6140f640, 0xf0034648, 0xf640fd1c, 0x46500141, 0xfd17f003, 0x3144f241, 0xf0034658, 0x1f30fd12, 
+    0x0114f248, 0xfd0df003, 0xf2481eb0, 0xf0037160, 0xf644fd08, 0x46303133, 0x0000e004, 0xf2039800, 
+    0x00040548, 0xfcfdf003, 0xf2401cb0, 0xf0034100, 0x21d0fcf8, 0xe8bd1fa0, 0xf0035ff0, 0xe92dbcf2, 
+    0x48ff4ff0, 0xaf03b09d, 0xe887c84e, 0xc84e004e, 0xe887af07, 0xc84e004e, 0xe887af0b, 0xc80f004e, 
+    0xe886ae0f, 0x2002000f, 0xf925f7e7, 0xf7e62000, 0x2000f985, 0xfbaff7e6, 0xfe3ef7f2, 0xf7e62001, 
+    0x48f0f88f, 0xf0032100, 0x48effccc, 0xfcc6f003, 0x21014eee, 0xf0034630, 0x49edfcc4, 0xb1107808, 
+    0xfec2f7ff, 0xf7ffe001, 0x48e8fdc8, 0x220a2300, 0x4100f240, 0xf0033010, 0x4fe4fcce, 0x220c2301, 
+    0x0319372e, 0xf0034638, 0x2301fcc6, 0x220d4638, 0xf0030359, 0x48dffcc0, 0x71fff647, 0xfca1f003, 
+    0x46302301, 0x46192200, 0xfcb5f003, 0x46302301, 0x461a2102, 0xfcaff003, 0x46304ed7, 0xfc8ef003, 
+    0x800849d6, 0x1140f240, 0xf0034630, 0x2000fc8a, 0x22029000, 0x46014603, 0xfbb0f7f6, 0x23014ecd, 
+    0x46192200, 0x46303e10, 0xfc95f003, 0x46302300, 0x461a2101, 0xfc8ff003, 0x23004ec2, 0x3e0c2203, 
+    0x46302108, 0xfc87f003, 0xf44f4fc5, 0x78390080, 0xfc58f7e2, 0x46302301, 0x21082203, 0xfc7bf003, 
+    0x383848b9, 0xfc5af003, 0x28e4b2c0, 0x2003d00e, 0x23029000, 0x21002201, 0xf7e748ba, 0xf04fffe9, 
+    0xf10d0901, 0x46c80a64, 0xe012ae1b, 0x90002000, 0x22022301, 0xe7ef2103, 0xb2a0d10b, 0xd1082801, 
+    0x28010c20, 0xb2a8d105, 0xd1022801, 0x28010c28, 0x48add07b, 0xf2497801, 0xea400000, 0xb2813041, 
+    0x301048a2, 0xfc2df003, 0xf44f4fa5, 0x46580b80, 0xf7e27839, 0x7839fc17, 0xf7e24658, 0x489bfc13, 
+    0xf0033012, 0xf8dffc1b, 0xf10de27c, 0x0b020b4c, 0x2103f3c0, 0x1703f3c0, 0x3003f99e, 0x0f01f1b9, 
+    0x2013f82b, 0x2002f99e, 0x1012f82b, 0x1001f99e, 0x7011f82b, 0x070ff000, 0x0000f99e, 0x7010f82b, 
+    0xf1b9d008, 0xd0270f02, 0xfc84fa1f, 0x0f00f1bc, 0xe06ad05a, 0x0c04f10d, 0xe013f83b, 0xe013f82c, 
+    0xe012f83b, 0xe012f82c, 0xe011f83b, 0xe011f82c, 0x7010f82c, 0xf8262700, 0xf8267010, 0xf3677011, 
+    0xf367040f, 0xf826050f, 0xf3677012, 0xf367441f, 0xf826451f, 0xe0857013, 0x0c04f10d, 0xe010f83c, 
+    0xd10445be, 0x7010f826, 0x040ff368, 0xf82ae001, 0xf83c7010, 0x46de7011, 0x0011f83b, 0xd1054287, 
+    0x441ff368, 0x0011f826, 0xe073e002, 0x0011f82a, 0x7012f83c, 0xf83e4671, 0x42870012, 0xf826d104, 
+    0xf3680012, 0xe001050f, 0x0012f82a, 0x2013f83c, 0x0013f831, 0xd1044282, 0x451ff368, 0x0013f826, 
+    0xf82ae050, 0xe04d0013, 0xc010f83a, 0xd0054567, 0x0c04f10d, 0xc010f83c, 0xd1044567, 0x7010f826, 
+    0x040ff368, 0xf826e001, 0x0c20c010, 0xf83bd111, 0xf83a0011, 0x42b87011, 0xaf01d004, 0x7011f837, 
+    0xd10442b8, 0x441ff368, 0x0011f826, 0xf826e001, 0x04287011, 0xd1110c00, 0x0012f83b, 0x1012f83a, 
+    0xd0044288, 0xf831a901, 0x42881012, 0xf826d104, 0xf3680012, 0xe001050f, 0x1012f826, 0xd1110c28, 
+    0x0013f83b, 0x1013f83a, 0xd0044288, 0xf831a901, 0x42881013, 0xf368d104, 0xf826451f, 0xe0010013, 
+    0x1013f826, 0x0001f109, 0x09fff000, 0x0f03f1b9, 0xaf02f67f, 0x0000f04f, 0xf836465d, 0xf8251010, 
+    0xf1001010, 0xb2c00001, 0xd9f62803, 0x809cf8df, 0x4f2c2400, 0xf108ae15, 0xeb080814, 0xf0030044, 
+    0xf1c4fb2d, 0x1c640103, 0x5679b2e4, 0xf8262c03, 0xd9f20011, 0x46a92400, 0xaf1746b8, 0x5004f918, 
+    0x0015f839, 0xd05c2802, 0xd05a2803, 0xd0582804, 0x0015f836, 0xf85af006, 0xf851a90b, 0xf0061025, 
+    0xa90ff869, 0x1025f851, 0xfed2f005, 0xf816f006, 0xb2e41c64, 0xf8272c03, 0xd9df0015, 0x24004d13, 
+    0xf04f4e13, 0xf8370864, 0x78281014, 0xfbb1b108, 0xeb06f1f8, 0xf0030044, 0x1c64faf4, 0xe019b2e4, 
+    0x0002b794, 0xf203900c, 0xf23c804a, 0xf2039800, 0x0004054a, 0xf23c8310, 0xf38fffc0, 0x000411f4, 
+    0x00040243, 0x00040520, 0x00040548, 0x00040549, 0xf203512e, 0xd9d62c03, 0x104cf8bd, 0x0052f8bd, 
+    0x2050f8bd, 0x3001ea40, 0x104ef8bd, 0xea410209, 0x43081102, 0x4894b281, 0xfac3f003, 0xe8bdb01d, 
+    0xf8368ff0, 0xf0060015, 0xa903f801, 0x1025f851, 0xf810f006, 0xe7a5a907, 0x5ff0e92d, 0x8e804604, 
+    0x8228f8df, 0x46d4f240, 0x42b04d89, 0x41d4f2a0, 0x47a1f240, 0x49a0f240, 0xdc17d072, 0xf2a042b8, 
+    0xd03741a1, 0xb300dc0d, 0xd12f4548, 0x22006868, 0x0108f105, 0xf892f7ff, 0xd0291d41, 0xd11a2801, 
+    0x2925e028, 0x2926d07e, 0xe014d120, 0xd012290d, 0x2901dc0c, 0x290cd00f, 0x4975d118, 0x68682200, 
+    0xf7ff3108, 0x1d40f84c, 0xe004d06d, 0xd06b292a, 0xd10b292b, 0x496ee0b7, 0x32fff04f, 0x31086868, 
+    0xf86cf7ff, 0xd1d71d01, 0x9034f8a4, 0x9ff0e8bd, 0xe7fb86a7, 0xf04f4b66, 0xf04f52c0, 0x33085000, 
+    0x1000f9b3, 0xd02c2966, 0xd05d2968, 0xd0792969, 0xd1e02967, 0xf7db469a, 0x2300fa92, 0x2101485d, 
+    0xf003461a, 0x495cfa68, 0x23012000, 0x70082200, 0x8801485a, 0x0110f021, 0x48598001, 0xf0034619, 
+    0xf7e8fa5a, 0x2107f865, 0x1000f8aa, 0x22004950, 0x0000f8d8, 0xf7ff3108, 0x1d01f802, 0xe070d067, 
+    0x469ae044, 0xfa6bf7db, 0xb138f8df, 0xf0034658, 0x1c40fa25, 0x4658b281, 0xfa23f003, 0xf7e22004, 
+    0x4849faed, 0xf44f7801, 0xf7e22000, 0x2168fa0b, 0x1000f8aa, 0x2200493e, 0x31086868, 0xffdff7fe, 
+    0xe0021d01, 0xe03fe005, 0xd108e044, 0x40c6f240, 0x4937e059, 0x68682200, 0xf7fe3108, 0x1d40ffd0, 
+    0xf240d189, 0xe04e40c7, 0xf7db469a, 0xf7fffa38, 0x2169fd06, 0x1000f8aa, 0x2200492d, 0x31086868, 
+    0xffbdf7fe, 0xd1071d01, 0xe77f86a6, 0x22004928, 0x31086868, 0xffb3f7fe, 0xd18a1d40, 0x40d5f240, 
+    0xe7ffe031, 0xf7db469a, 0x2167fa1a, 0x1000f8aa, 0x2200491f, 0x31086868, 0xffa1f7fe, 0xf47f1d01, 
+    0xf240af52, 0xe01e40e0, 0x40e1f240, 0xf240e01b, 0xe01840fe, 0x22004916, 0x0000f8d8, 0xf7fe3108, 
+    0x1d40ff8e, 0xf7e7d00d, 0x8829fd46, 0xf0034817, 0x4817f9b8, 0x220b2300, 0x0100f640, 0xf9cbf003, 
+    0xf240e739, 0x86a040ff, 0x2200e740, 0xb5102101, 0x201bf2af, 0xfdbef7fe, 0x20022108, 0xff1cf7fe, 
+    0x60484903, 0x0000bd10, 0xf203512c, 0x000406cc, 0x000411f4, 0xf2039800, 0x00040262, 0x00040240, 
+    0xf38f20e0, 0xf2039ffe, 0x00040243, 0xf38fffc0, 0xf23c800c, 0x22052301, 0xb5102120, 0x46204cfe, 
+    0xf999f003, 0x46202301, 0x21402206, 0xf993f003, 0xe8bd2100, 0x20044010, 0xb964f7e2, 0x4cf6b510, 
+    0x22042301, 0x2110347e, 0xf0034620, 0x2303f984, 0x22024620, 0xf003210c, 0x2302f97e, 0x22004620, 
+    0x4010e8bd, 0xf0032103, 0xb510b976, 0x23014cea, 0x21042202, 0xf0034620, 0x2301f96e, 0x21024620, 
+    0xf003461a, 0x2301f968, 0x22004620, 0xf0034619, 0x2100f962, 0x4010e8bd, 0xf7e22004, 0x48dfb933, 
+    0x31b6f64b, 0xf003b510, 0x4cddf93c, 0xf7ff7820, 0x7820ffdc, 0xffc2f7ff, 0xe8bd7820, 0xe7a94010, 
+    0x41f0e92d, 0x48d74604, 0x0700f24f, 0x46394420, 0x46052304, 0xf003220c, 0x2308f93e, 0x113e4628, 
+    0x4631461a, 0xf937f003, 0x46282308, 0x21f02204, 0xf931f003, 0x46282308, 0x210f2200, 0xf92bf003, 
+    0x230948c8, 0x4639220c, 0x44201c80, 0xf0034605, 0x2309f922, 0x22084631, 0xf0034628, 0x2304f91c, 
+    0x21f04628, 0xf003461a, 0x2300f916, 0x210f4628, 0xf003461a, 0x48bbf910, 0x76fff643, 0x46312319, 
+    0x220030d2, 0xf0034420, 0x48b6f906, 0x78fff641, 0x46412306, 0x220030d4, 0xf0034420, 0x48b1f8fc, 
+    0x7500f64f, 0x46292301, 0x442030d6, 0x46072208, 0xf8f1f003, 0x46382300, 0x461a21ff, 0xf8ebf003, 
+    0x230048a8, 0x461a213f, 0x442030d8, 0xf8e3f003, 0x117748a4, 0x46392305, 0x22003062, 0xf0034420, 
+    0x48a0f8da, 0x2200237d, 0x30c84631, 0xf0034420, 0x489cf8d2, 0x2200231f, 0x30604639, 0xf0034420, 
+    0x4898f8ca, 0x22002332, 0x30cc4631, 0xf0034420, 0x4894f8c2, 0x22002331, 0x30d04641, 0x46064420, 
+    0xf8b9f003, 0x2301488f, 0x46292208, 0x442030ca, 0xf0034605, 0x2300f8b0, 0x21ff4628, 0xf003461a, 
+    0x4888f8aa, 0x2200231f, 0x30ce4641, 0x46044420, 0xf8a1f003, 0x0500f24e, 0x23004630, 0x220d4629, 
+    0xf899f003, 0x46204629, 0x41f0e8bd, 0x220d2300, 0xb891f003, 0x4ff8e92d, 0x48784605, 0x46162400, 
+    0xf640220b, 0x38820100, 0xf0039400, 0x4976f892, 0x0ffff010, 0x2d03d006, 0x2d05d066, 0x2d04d011, 
+    0xe010d00f, 0xd0142d03, 0xd0012d05, 0xd1012d04, 0xd00e2e02, 0x28017808, 0x2d02d101, 0x2401d009, 
+    0x2e02e007, 0x7808d06d, 0xd1012801, 0xd0682d02, 0x4d672405, 0x9194f8df, 0x0800f24e, 0xf2441cae, 
+    0xf2400700, 0xf6433aff, 0xb3e47bff, 0xd0782c01, 0x370c4f5f, 0xd0722c04, 0xd1712c05, 0xf7ff9800, 
+    0x2303feff, 0x220d4641, 0xf0034648, 0x2350f844, 0x22004651, 0xf0034628, 0x4855f83e, 0x461a2300, 
+    0x1e804659, 0xf837f003, 0x23004851, 0xf24f220c, 0x1f000100, 0xf82ff003, 0x2300484d, 0x21102204, 
+    0xf003380c, 0x230ff828, 0x22034630, 0xf0032178, 0x4847f822, 0x22002303, 0x380e210f, 0xf81bf003, 
+    0x22092300, 0xe01ee001, 0x4841e01b, 0x6100f640, 0xf0033810, 0x2300f810, 0x0100f248, 0x4628220f, 
+    0xf809f003, 0x46382300, 0x21022201, 0xf803f003, 0x46382300, 0x461a2101, 0xe8bdb001, 0xf0024ff0, 
+    0x2404bffa, 0x2305e795, 0x220d4641, 0xf0024648, 0x2301fff2, 0x220e4639, 0xf0024628, 0x2302ffec, 
+    0x22014630, 0xf0022106, 0x2319ffe6, 0x22004651, 0xf0024628, 0xf243ffe0, 0xe01f2300, 0xe067e001, 
+    0x9800e06e, 0xfe8cf7ff, 0x46412305, 0x4648220d, 0xffd1f002, 0x46392301, 0x4628220e, 0xffcbf002, 
+    0x46302302, 0x21062201, 0xffc5f002, 0x4651231f, 0x46282200, 0xffbff002, 0x0300f241, 0x22004814, 
+    0x1e804659, 0xffb7f002, 0x23004811, 0xf24f220c, 0x1f000100, 0xffaff002, 0x2300480d, 0x21102204, 
+    0xf002380c, 0x230fffa8, 0x22034630, 0xf0022178, 0x2303ffa2, 0xe00d2200, 0xf3074004, 0xf23c80ba, 
+    0x00040320, 0xf3072402, 0x000402c9, 0xf3072200, 0xf303a170, 0x210f48fe, 0xff8df002, 0x230048fc, 
+    0xf6402209, 0x1e806100, 0xff85f002, 0xf2482300, 0x220f0100, 0xf0024628, 0x2300ff7e, 0x21014630, 
+    0xf002461a, 0x2301ff78, 0x22004630, 0xe7734619, 0x46412303, 0x4648220d, 0xff6df002, 0xe7272342, 
+    0x8ff8e8bd, 0xb149b430, 0x46034cea, 0x220048e8, 0x38602101, 0xbc304420, 0xbf5df002, 0xe7f42400, 
+    0x460db570, 0x4ce3b19a, 0x460334c0, 0x220048e0, 0x30642101, 0xf0024420, 0x48ddff4e, 0x21012200, 
+    0x3044462b, 0xe8bd4420, 0xf0024070, 0x2400bf44, 0xb430e7eb, 0x4cd7b149, 0x48d54603, 0x21012200, 
+    0x44203846, 0xf002bc30, 0x2400bf36, 0xb430e7f4, 0x4cd1b151, 0x48ce4603, 0xf242220d, 0x30860100, 
+    0xbc304420, 0xbf27f002, 0xe7f32400, 0x5ffce92d, 0x4605000f, 0x4690469b, 0xf44fd012, 0xf8df1400, 
+    0xf240a31c, 0x46282900, 0xfe84f7ff, 0x21004ac4, 0x1c902362, 0x0f00f1bb, 0x80018011, 0xe011d002, 
+    0xe7ec2400, 0xd00b2d03, 0xd0012d05, 0xd1022d04, 0x0f02f1b8, 0x2138d004, 0x21a88011, 0xe0028001, 
+    0x80112126, 0x88118003, 0xf0218803, 0xf4230101, 0xf0417380, 0x80110140, 0x7600f443, 0xf04f4623, 
+    0x80060202, 0xb1074648, 0xf0014631, 0x2000f8ff, 0xf7ff4639, 0x2001ff77, 0xf7ff4639, 0x2000ffa8, 
+    0xf7ff4639, 0x48a7ff96, 0x21012300, 0x4420461a, 0xf0029001, 0x48a3fed0, 0x22012300, 0x44203848, 
+    0x21024681, 0xf002464e, 0x2300fec6, 0x21014630, 0xf002461a, 0x2001fec0, 0xf7ff4639, 0x2f01ff7a, 
+    0x4893d004, 0x30642102, 0xfe9bf002, 0x0f00f1bb, 0x4895d17e, 0x28017800, 0x2d03d103, 0x2d02d02a, 
+    0x4890d028, 0x23002208, 0x01513052, 0xf0024420, 0x488efea2, 0x220b2300, 0x0100f640, 0x46064420, 
+    0xfe99f002, 0x46302301, 0x21402206, 0xfe93f002, 0xf2402300, 0x220a4100, 0xf0024630, 0x2d03fe8c, 
+    0x2d05d07e, 0x2d04d07d, 0x2d02d07c, 0x2d01d07b, 0xe105d07a, 0x220c487d, 0x44202302, 0x46800291, 
+    0xfe79f002, 0xf241487a, 0x442001ee, 0xfe59f002, 0xf24a4877, 0x1c800100, 0xf0024420, 0x4874fe52, 
+    0x31b8f640, 0x44201d00, 0xfe4bf002, 0xf6414870, 0x1d803100, 0xf0024420, 0x486dfe44, 0x2635f248, 
+    0x30084631, 0xf0024420, 0x4869fe3c, 0x300a4631, 0xf0024420, 0x4866fe36, 0x300e4631, 0xf0024420, 
+    0x4863fe30, 0x3012210f, 0xf0024420, 0x485dfe2a, 0x2205231c, 0x31e0f240, 0x4420305c, 0xf0029000, 
+    0x4e58fe3a, 0x2d03365e, 0x2d02d003, 0xe01cd010, 0xf04fe0bd, 0x210c4260, 0xf7da1750, 0x19a0fe50, 
+    0x46062301, 0x21082203, 0xfe25f002, 0xe0072300, 0x230019a0, 0x22034606, 0xf0022108, 0x2301fe1c, 
+    0x22054630, 0xf0022120, 0x9800fe16, 0x22002301, 0xf002211f, 0x2208fe10, 0x23014842, 0xe0040151, 
+    0xe014e013, 0xe0b2e043, 0x3052e0b3, 0xf0024420, 0x2300fe02, 0x0100f640, 0x4640220b, 0xfdfbf002, 
+    0x46402300, 0x21402206, 0x230fe061, 0x4839e011, 0x0f01f1b8, 0xf1b8d003, 0xd00e0f02, 0x7800e070, 
+    0xf04f2120, 0xea414260, 0x17502100, 0xfe07f7da, 0x46302320, 0x213f2200, 0x7800e049, 0xf04f2121, 
+    0xea414260, 0x17502100, 0xfdf9f7da, 0x46302329, 0x213f2200, 0xfdcff002, 0xd0512f01, 0x23014824, 
+    0x210f2200, 0xf00238a6, 0x2301fdc6, 0x4822e02b, 0x0f01f1b8, 0xf1b8d003, 0xd00b0f02, 0x7800e040, 
+    0xf04f2110, 0xea414260, 0x17502100, 0xfdd7f7da, 0xe7ce2321, 0x21117800, 0x4260f04f, 0x2100ea41, 
+    0xf7da1750, 0x2328fdcc, 0x22004630, 0xf002213f, 0x2f01fda2, 0x480ed024, 0x22002304, 0x38a6210f, 
+    0xfd99f002, 0x480a2304, 0x210f2200, 0xe01538a2, 0xf303a162, 0x00200060, 0x002001c0, 0x0004d108, 
+    0x00041204, 0xf30788ae, 0x000402c9, 0xf3078616, 0xf30724a6, 0x000402cb, 0x000402ca, 0xfd7bf002, 
+    0x230148ff, 0x21802207, 0xf0024420, 0x48fdfd74, 0x21022301, 0x4420461a, 0xfd6df002, 0x1008f89a, 
+    0xf89a463a, 0xf7ff0009, 0x48f7fe0b, 0x22012300, 0x44202102, 0xfd5ff002, 0x220049f4, 0x800a1c88, 
+    0x22048002, 0x0f00f1bb, 0x2224d005, 0x2302e018, 0x2301e76f, 0x4beee76d, 0x2b01781b, 0x2d03d103, 
+    0x2d02d01b, 0x2314d019, 0x2d04800b, 0x2d02d004, 0x2d01d002, 0x8002d000, 0xf0228802, 0x32200260, 
+    0xb16f8002, 0xf240b291, 0x22023000, 0xf0004623, 0x48dfff4d, 0xb1287800, 0x2203e008, 0xe7ef800a, 
+    0xe7f08809, 0x46504639, 0xfc8ff001, 0x46482301, 0x461a2102, 0xfd1ff002, 0x46482301, 0x46192200, 
+    0xfd19f002, 0x46392001, 0xfdacf7ff, 0x98012301, 0x46192200, 0xfd0ff002, 0xb00248ce, 0x44202301, 
+    0x5ff0e8bd, 0x21042202, 0xbd05f002, 0x5ff0e92d, 0x23014dc9, 0x46172120, 0x46042205, 0xf0024628, 
+    0x2c03fcfa, 0x0600f244, 0x41dff240, 0x2c05d008, 0x2c04d009, 0x2c02d011, 0x2c01d07f, 0xe021d07f, 
+    0x4310f240, 0xf240e001, 0x46284308, 0xf0022200, 0x2300fce2, 0x220e4631, 0x2200e011, 0x4304f240, 
+    0x46284688, 0xfcd7f002, 0x46312301, 0x4628220e, 0xfcd1f002, 0xd1052f03, 0x46412382, 0x46282200, 
+    0xfcc9f002, 0x230148ac, 0x21202205, 0xf0021c80, 0xf8dffcc2, 0x2301a2a4, 0x46192200, 0x0a0af10a, 
+    0xf0024650, 0x2301fcb8, 0x0b04f10a, 0x22004619, 0xf0024658, 0x2301fcb0, 0x0502f1aa, 0x22004619, 
+    0xf0024628, 0x2301fca8, 0x46191d2e, 0x46302200, 0xfca1f002, 0xf6412c03, 0xf2406800, 0xd03019e0, 
+    0xd02e2c05, 0xd02c2c04, 0x2c024f94, 0x2c01d058, 0xf64fd173, 0x46540500, 0x46292306, 0x4650220b, 
+    0xfc89f002, 0x46292306, 0x465d220b, 0xf0024658, 0x2300fc82, 0x22054620, 0xf0022120, 0x2300fc7c, 
+    0x22054628, 0xf0022120, 0x7839fc76, 0xd07d2901, 0xd07c2900, 0xe000e095, 0x2382e001, 0x2341e785, 
+    0x2302e783, 0x22094641, 0xf0024628, 0x2302fc64, 0x22094641, 0xf0024630, 0x2303fc5e, 0x2205464c, 
+    0x46284649, 0xfc57f002, 0x46212303, 0x46302205, 0xfc51f002, 0x46282301, 0x21102204, 0xfc4bf002, 
+    0x46302301, 0x21102204, 0xfc45f002, 0x46282303, 0x210e2201, 0xfc3ff002, 0x22012303, 0xe03b210e, 
+    0x46412303, 0x46282209, 0xfc35f002, 0x46412303, 0x46302209, 0xfc2ff002, 0x46282300, 0x21102204, 
+    0xfc29f002, 0x46302300, 0x21102204, 0xfc23f002, 0x28017838, 0xb148d002, 0xe05ee014, 0x46282302, 
+    0x210e2201, 0xfc17f002, 0xe0062304, 0x46282300, 0x210e2201, 0xfc0ff002, 0x46302302, 0x210e2201, 
+    0xfc09f002, 0x464c2303, 0x46492205, 0xf0024628, 0x2303fc02, 0x22054621, 0xf0024630, 0x2300fbfc, 
+    0x21014628, 0xf002461a, 0xe001fbf6, 0xe00ce005, 0x46302300, 0x461a2101, 0x2304e02b, 0x22014620, 
+    0xf002211e, 0x2304fbe8, 0x2302e006, 0x22014620, 0xf002211e, 0x2302fbe0, 0x22014628, 0xf002211e, 
+    0x2306fbda, 0x76c0f240, 0x4631461a, 0xf0024620, 0x2306fbd2, 0x461a4631, 0xf0024628, 0x2300fbcc, 
+    0x21014620, 0xf002461a, 0x2300fbc6, 0x21014628, 0xe8bd461a, 0xf0025ff0, 0xe8bdbbbe, 0xb4309ff0, 
+    0xf04fb159, 0x46031420, 0x2200481e, 0x31fff240, 0x44203022, 0xf002bc30, 0x2400bbae, 0xb430e7f3, 
+    0xf04fb151, 0x46031420, 0x22004816, 0x301c2101, 0xbc304420, 0xbb9ff002, 0xe7f42400, 0x0005b570, 
+    0xf44fd048, 0x20011400, 0xf0004621, 0x2000fddd, 0xf7ff4629, 0x2001ffe4, 0xf7ff4629, 0x4629ffe0, 
+    0x10f4f240, 0xffcbf7ff, 0x46212000, 0xfdccf000, 0xf44f2100, 0xf7e11080, 0x2100fb55, 0x0000e010, 
+    0xf3078616, 0xf303a1c6, 0xf302012c, 0x00041208, 0x000402c9, 0xf30788a0, 0xf3074080, 0x00040321, 
+    0x2080f44f, 0xfb3ef7e1, 0x230148c0, 0x46192200, 0xf0024420, 0x4cbefb60, 0x22042300, 0x46202110, 
+    0xfb59f002, 0xe8bd4620, 0x23014070, 0x21102204, 0xbb51f002, 0xe7b62400, 0x48b52300, 0x21082203, 
+    0xbb49f002, 0x48b30002, 0xf1a0b570, 0xf1a00404, 0xd00a0506, 0xd00f2a01, 0xd1232a02, 0xd01c2901, 
+    0xf0022104, 0x2102fb1e, 0x2901e00c, 0x2108d015, 0xfb17f002, 0xe0052104, 0xd0052901, 0xf002210c, 
+    0x2106fb10, 0xe0044628, 0xf0022108, 0x2110fb0a, 0xe8bd4620, 0xf0024070, 0x2104bb04, 0xfb01f002, 
+    0xe7f52100, 0xb570bd70, 0x48994604, 0x0100f244, 0x2c04307c, 0x2c05d01a, 0x2300d018, 0xf002220e, 
+    0x4d94fb0a, 0x220d2301, 0x03593d08, 0xf0024628, 0x2c01fb02, 0x0100f241, 0x2c02d00a, 0x2c03d008, 
+    0x2c05d008, 0x2c04d006, 0xe008d004, 0xe7e52301, 0xe0002300, 0x46282301, 0xf002220c, 0x2301faec, 
+    0x22034628, 0xf0022108, 0x2301fae6, 0x22024628, 0xf0022104, 0x2301fae0, 0x22004628, 0xf0024619, 
+    0x4d7cfada, 0x22052301, 0x21201ead, 0xf0024628, 0x2301fad2, 0x22044628, 0xf0022110, 0x2c01facc, 
+    0x2c02d001, 0x4874d104, 0x78004621, 0xff7af7ff, 0x4070e8bd, 0x486e2301, 0x21082203, 0xbabbf002, 
+    0x47f0e92d, 0x460c4d6b, 0x0100f248, 0x6900f640, 0xf2401cad, 0x10cf1a00, 0x0300f04f, 0xf04f2800, 
+    0xd06a020f, 0x4628460e, 0xfaa5f002, 0x8180f8df, 0x22052300, 0x087ef108, 0x46402120, 0xfa9bf002, 
+    0x46392301, 0x4628220c, 0xfa95f002, 0x4649b2a3, 0x46282209, 0xfa8ff002, 0x46512301, 0x46282208, 
+    0xfa89f002, 0x46282301, 0x46192200, 0xfa83f002, 0x46312301, 0x4628220f, 0xfa7df002, 0x46402301, 
+    0x21202205, 0xfa77f002, 0x23014c4a, 0x1d242209, 0x46200259, 0xfa6ff002, 0x46512300, 0x46202208, 
+    0xfa69f002, 0x46202300, 0x21082203, 0xfa63f002, 0x88004842, 0x2301b3d8, 0x22034620, 0xf0022108, 
+    0x2301fa5a, 0x22024620, 0xf0022104, 0x2100fa54, 0xf7e12004, 0x2300fa27, 0x22024620, 0xf0022104, 
+    0x2100fa4a, 0xf7e12004, 0x2301fa1d, 0x22024620, 0xf0022104, 0x2301fa40, 0x4628e021, 0xfa3bf002, 
+    0x46392301, 0x4628220c, 0xfa35f002, 0x4649b2a3, 0x46282209, 0xfa2ff002, 0x46512301, 0x46282208, 
+    0xfa29f002, 0x46282301, 0x46192200, 0xe7ffe7aa, 0x46202300, 0x21042202, 0xfa1df002, 0x46202300, 
+    0x47f0e8bd, 0x21022201, 0xba15f002, 0x4c18b510, 0x21102204, 0x4620347c, 0xfa1bf002, 0xd0162801, 
+    0x46202203, 0xf0022108, 0x2801fa14, 0x2202d011, 0x21044620, 0xfa0df002, 0xd00c2801, 0x46202201, 
+    0xf0022102, 0x2801fa06, 0x2001d007, 0x2003bd10, 0x2005bd10, 0x2004bd10, 0x2002bd10, 0x4603bd10, 
+    0x22044804, 0x38082110, 0xb9e5f002, 0xf3072200, 0xf3074004, 0xf3074188, 0x00040321, 0x0004031e, 
+    0x47f0e92d, 0x23014cff, 0x46192200, 0xf0024620, 0x2301f9d2, 0x21024620, 0xf002461a, 0x48f9f9cc, 
+    0x5507f643, 0x76fff643, 0x2200462b, 0x30424631, 0xf9c1f002, 0x1c7748f3, 0x463b2200, 0x46313044, 
+    0xf9b9f002, 0xf64048ef, 0x22002888, 0x30464643, 0xf0024631, 0x48ebf9b0, 0x09e2f241, 0x464b2200, 
+    0x46313048, 0xf9a7f002, 0x220048e6, 0x46314643, 0xf002304a, 0x48e3f9a0, 0x461a2300, 0x304c4631, 
+    0xf999f002, 0x220048df, 0x4631462b, 0xf002304e, 0x48dcf992, 0x463b2200, 0x30504631, 0xf98bf002, 
+    0x220048d8, 0x4631462b, 0xf0023052, 0x48d5f984, 0x463b2200, 0x30544631, 0xf97df002, 0x220048d1, 
+    0x46314643, 0xf0023056, 0x48cef976, 0x464b2200, 0x30584631, 0xf96ff002, 0x220048ca, 0x46314643, 
+    0xf002305a, 0x48c7f968, 0x461a2300, 0x305c4631, 0xf961f002, 0x220048c3, 0x4631462b, 0xf002305e, 
+    0x48c0f95a, 0x463b2200, 0x30604631, 0xf953f002, 0x220048bc, 0x4631462b, 0xf0023062, 0x48b9f94c, 
+    0x463b2200, 0x30644631, 0xf945f002, 0x220048b5, 0x46314643, 0xf0023066, 0x48b2f93e, 0x464b2200, 
+    0x30684631, 0xf937f002, 0x220048ae, 0x46314643, 0xf002306a, 0x48abf930, 0x461a2300, 0x306c4631, 
+    0xf929f002, 0x220048a7, 0x4631462b, 0xf002306e, 0x48a4f922, 0x463b2200, 0x30704631, 0xf91bf002, 
+    0x220048a0, 0x4631462b, 0xf0023072, 0x489df914, 0x463b2200, 0x30744631, 0xf90df002, 0x22004899, 
+    0x46314643, 0xf0023076, 0x4896f906, 0x464b2200, 0x30784631, 0xf8fff002, 0x22004892, 0x46314643, 
+    0xf002307a, 0x488ff8f8, 0x461a2300, 0x307c4631, 0xf8f1f002, 0x2200488b, 0x4631462b, 0xf002307e, 
+    0x4888f8ea, 0x463b2200, 0x30804631, 0xf8e3f002, 0xe8bd4620, 0x230147f0, 0x21042202, 0xb8dbf002, 
+    0x41f0e92d, 0x23014c7f, 0x1f242202, 0x46202104, 0xf8d1f002, 0x46202301, 0x21082203, 0xf8cbf002, 
+    0xf6434878, 0xf6435407, 0x462375ff, 0x46292200, 0xf0021c80, 0x4873f8c0, 0x22001c6e, 0x1d004633, 
+    0xf0024629, 0x486ff8b8, 0x2788f640, 0x463b2200, 0x46291d80, 0xf8aff002, 0xf241486a, 0x220008e2, 
+    0x30084643, 0xf0024629, 0x4866f8a6, 0x463b2200, 0x300a4629, 0xf89ff002, 0x23004862, 0x4629461a, 
+    0xf002300c, 0x485ff898, 0x46232200, 0x300e4629, 0xf891f002, 0x2200485b, 0x46294633, 0xf0023010, 
+    0x4858f88a, 0x46232200, 0x30124629, 0xf883f002, 0x22004854, 0x46294633, 0xf0023014, 0x4851f87c, 
+    0x463b2200, 0x30164629, 0xf875f002, 0x2200484d, 0x46294643, 0xf0023018, 0x484af86e, 0x463b2200, 
+    0x301a4629, 0xf867f002, 0x23004846, 0x4629461a, 0xf002301c, 0x4843f860, 0x46232200, 0x301e4629, 
+    0xf859f002, 0x2200483f, 0x46294633, 0xf0023020, 0x483cf852, 0x46232200, 0x30224629, 0xf84bf002, 
+    0x22004838, 0x46294633, 0xf0023024, 0x4835f844, 0x463b2200, 0x30264629, 0xf83df002, 0x22004831, 
+    0x46294643, 0xf0023028, 0x482ef836, 0x463b2200, 0x302a4629, 0xf82ff002, 0x2300482a, 0x4629461a, 
+    0xf002302c, 0x4827f828, 0x46232200, 0x302e4629, 0xf821f002, 0x22004823, 0x46294633, 0xf0023030, 
+    0x4820f81a, 0x46232200, 0x30324629, 0xf813f002, 0x2200481c, 0x46294633, 0xf0023034, 0x4819f80c, 
+    0x463b2200, 0x30364629, 0xf805f002, 0x22004815, 0x46294643, 0xf0013038, 0x4812fffe, 0x463b2200, 
+    0x303a4629, 0xfff7f001, 0x2300480e, 0x4629461a, 0xf001303c, 0x480bfff0, 0x46232200, 0x303e4629, 
+    0xffe9f001, 0x22004807, 0x46294633, 0xf0013040, 0xe8bdffe2, 0x480341f0, 0x22002301, 0x1e804619, 
+    0x0000e002, 0xf2030a04, 0xbfd5f001, 0x4c2fb570, 0xd0282803, 0x28051d25, 0x2804d035, 0x2301d154, 
+    0x22024620, 0xf0012104, 0x2301ffc6, 0x22034620, 0xf0012108, 0x2301ffc0, 0x21024628, 0xf001461a, 
+    0x2301ffba, 0x22004628, 0xf0014619, 0xf7ffffb4, 0xf7fffed7, 0x2302fdd5, 0x21032200, 0xe8bd4620, 
+    0xf0014070, 0x2300bfa8, 0x21034620, 0xf001461a, 0x2300ffa2, 0x22024620, 0xf0012104, 0x2300ff9c, 
+    0x21082203, 0x2301e7ea, 0x22024620, 0xf0012104, 0x2301ff92, 0x22034620, 0xf0012108, 0x2300ff8c, 
+    0x22014628, 0xf0012102, 0x2300ff86, 0x21014628, 0xf001461a, 0x2301ff80, 0x22004620, 0xf0012103, 
+    0xe8bdff7a, 0xe69b4070, 0x0000bd70, 0xf2030a00, 0x5ff0e92d, 0x00044eb7, 0x2301d005, 0x22044630, 
+    0xf0012110, 0x4db3ff68, 0x211c2202, 0x1ead4623, 0xf0014628, 0x2301ff60, 0x22054628, 0xf0012120, 
+    0xf240ff5a, 0x21004700, 0xf7e04638, 0x2301ff2b, 0x21802207, 0xf0011ca8, 0x2100ff4e, 0xf7e04638, 
+    0x2200ff21, 0x1da81e79, 0xff53f001, 0x4fa2b18c, 0xf8df2c03, 0xf06f9288, 0xf8df0609, 0xf8dfa284, 
+    0xd016b284, 0xd0142c04, 0xd01e2c05, 0xd0492c06, 0xf003e033, 0x4a9cff6b, 0xf0034b9c, 0x4a9cffb7, 
+    0xf0044b9c, 0xf003f8e7, 0xf004fca7, 0x4680fbfb, 0xf003e035, 0x4632ff5b, 0xfdcff004, 0x463b2200, 
+    0xffa4f003, 0x4653464a, 0xf003e00a, 0x4632ff4f, 0xfdc3f004, 0x463b2200, 0xff98f003, 0x464a4b8e, 
+    0xfd78f003, 0xfc88f003, 0xf0044659, 0x498bfb19, 0xfc40f004, 0xfbd6f004, 0x46284680, 0x22022300, 
+    0xf001211c, 0x2301fef8, 0x22054628, 0xf0012120, 0x4878fef2, 0x22042300, 0xf0012110, 0x4640feec, 
+    0x9ff0e8bd, 0xff22f003, 0xf0044632, 0x2200fd96, 0xf003463b, 0x4b7aff6b, 0xe7d1464a, 0x5ff0e92d, 
+    0x23014e78, 0x46052203, 0x46302108, 0xfed3f001, 0x46302302, 0x21032200, 0xfecdf001, 0x0a02f1a6, 
+    0x0900f248, 0x46492300, 0x4650220f, 0xfec3f001, 0x4b00f240, 0x46582100, 0xfe94f7e0, 0x46302400, 
+    0x22022300, 0xf0012104, 0x2301feb6, 0x22024630, 0xf0012104, 0x1c64feb0, 0x2c18b264, 0x4861dbef, 
+    0xf2402200, 0x300c31ff, 0xfeb3f001, 0xf2a04607, 0x2822108b, 0xf240d301, 0x2d0117a0, 0x2d05d002, 
+    0xe00dd002, 0xe0002300, 0x46302301, 0x21032200, 0xfe91f001, 0x46492300, 0x4650220f, 0xfe8bf001, 
+    0x46582100, 0xfe5ef7e0, 0x46302400, 0x22022300, 0xf0012104, 0x2301fe80, 0x22024630, 0xf0012104, 
+    0x1c64fe7a, 0x2c18b264, 0x4846dbef, 0xf2402200, 0x300c31ff, 0xfe7df001, 0x46042d01, 0x2d05d002, 
+    0xe018d008, 0xf0034638, 0x4605fea1, 0xf640460f, 0xe00670a0, 0xf0034638, 0x4605fe99, 0xf643460f, 
+    0x43606080, 0xfe92f003, 0x463b462a, 0xfcc2f003, 0xfbd2f003, 0x46404680, 0xfb24f004, 0x46042300, 
+    0x46302203, 0xf0012108, 0xb220fe46, 0x2000e758, 0xf7ffb510, 0xb281fecd, 0x38ce481e, 0xfe21f001, 
+    0xf7ff2001, 0xb281ff5b, 0x38cc481a, 0xfe19f001, 0xf7ff2004, 0xb281febd, 0x38ca4816, 0xfe11f001, 
+    0xf7ff2005, 0xb281feb5, 0x38c84812, 0xfe09f001, 0xf7ff2006, 0xb281fead, 0xe8bd480e, 0x38c64010, 
+    0xbdfff001, 0x48182301, 0x46192200, 0xf001b510, 0x4c08fe12, 0x22002301, 0x1ea44619, 0xf0014620, 
+    0x2301fe0a, 0x21024620, 0xf001461a, 0xe8bdfe04, 0xe7bc4010, 0xf23d0210, 0x408db000, 0x9999999a, 
+    0x3fe99999, 0x447a0000, 0x0ded288d, 0x3fe130be, 0xd70a3d71, 0x407ba8a3, 0x3fd99999, 0x461c4000, 
+    0x3fc99999, 0xf203f052, 0xf23d0004, 0x41f0e92d, 0x48a84607, 0x4616461c, 0x46884420, 0xf2412300, 
+    0x220c0100, 0xf0014605, 0x2e02fdd6, 0x2300d01a, 0x22004628, 0xf0012103, 0x489efdce, 0x0100f242, 
+    0x44201d80, 0xfdadf001, 0x4639489a, 0x44201d00, 0xfda7f001, 0x46414897, 0x44203008, 0x41f0e8bd, 
+    0xbd9ff001, 0xe7e32301, 0x43f8e92d, 0x2100460c, 0x49909100, 0x1c8a1f09, 0x1d0a18a7, 0x186518a6, 
+    0xd07c2800, 0x46282300, 0x21022201, 0xfda3f001, 0x46282300, 0x461a2101, 0xfd9df001, 0x46282100, 
+    0xfd7ff001, 0x46382100, 0xfd7bf001, 0x46302100, 0xfd77f001, 0x2100487f, 0x44201d00, 0xfd71f001, 
+    0x2100487c, 0x44201d80, 0xfd6bf001, 0x21004879, 0x44203008, 0xfd65f001, 0x21004876, 0x4420300a, 
+    0xfd5ff001, 0x21004873, 0x4420300c, 0xfd59f001, 0x21004870, 0x4420300e, 0xfd53f001, 0x2100486d, 
+    0x44203010, 0xfd4df001, 0x2100486a, 0x44203012, 0xfd47f001, 0x21004867, 0x44203014, 0xfd41f001, 
+    0x21004864, 0x44203016, 0xfd3bf001, 0x21004861, 0x44203018, 0xfd35f001, 0x2100485e, 0x4420301e, 
+    0xfd2ff001, 0x2100485b, 0x44203020, 0xfd29f001, 0x21004858, 0x44203022, 0xfd23f001, 0x21004855, 
+    0x44203024, 0xfd1df001, 0x21004852, 0x44203026, 0xfd17f001, 0x2107484f, 0x44203028, 0xe05ae000, 
+    0xfd0ff001, 0x2100484b, 0x4420302a, 0xfd09f001, 0x21004848, 0x4420302c, 0xfd03f001, 0x21004845, 
+    0x4420302e, 0xfcfdf001, 0x21004842, 0x44203030, 0xfcf7f001, 0x2100483f, 0x44203032, 0xfcf1f001, 
+    0x2100483c, 0x4420303c, 0xfcebf001, 0x21004839, 0x4420303e, 0xfce5f001, 0x21004836, 0x44203044, 
+    0xfcdff001, 0x30464833, 0x1f00f5b4, 0x4420d01f, 0x2101f248, 0xfcd5f001, 0x2100482e, 0x44203048, 
+    0xfccff001, 0xf240482b, 0x304c1101, 0xf0014420, 0x4828fcc8, 0x304e2100, 0xf0014420, 0x4825fcc2, 
+    0x30502100, 0xf0014420, 0xe8bdfcbc, 0x482283f8, 0x3101f248, 0x2301e7de, 0x22004628, 0xf0014619, 
+    0x2301fcca, 0x22004638, 0xf0014619, 0xf240fcc4, 0x46303900, 0x46492302, 0xf0012208, 0xf44ffcbc, 
+    0x90000080, 0xf8df4813, 0x1c808054, 0xe0064404, 0x4642210b, 0xf7e04668, 0x2801fd1a, 0x2200d006, 
+    0x21014620, 0xfcb5f001, 0xd1f12801, 0x46492300, 0x46302208, 0xfc9ff001, 0x46282301, 0x461a2102, 
+    0xfc99f001, 0x46382301, 0x461a2102, 0xfc93f001, 0x0000e7bb, 0xf303a404, 0xf323a44a, 0xf203517e, 
+    0x4605b5f0, 0xb1532000, 0x2d0b2400, 0xf240d301, 0x293d1001, 0xf440d301, 0xb1147081, 0x2401e003, 
+    0x2a12e7f3, 0x2a00dc01, 0xf440da01, 0xb10c7082, 0xdc012a18, 0xda012a00, 0x7082f440, 0xd3012b07, 
+    0x7084f440, 0x18f718ae, 0x428f1dbf, 0xf440dd01, 0x44297090, 0x44194411, 0xdd01293c, 0x70a0f440, 
+    0x2e18b124, 0xf440dd01, 0xbdf070c0, 0xdcfa2e12, 0xb40fbdf0, 0xa802b510, 0xfce4f000, 0xf000a80a, 
+    0xf8bdfcaf, 0xf64f1042, 0xf00170ff, 0xea000101, 0xf8bd0241, 0xf0011040, 0x43110101, 0x0241ea00, 
+    0x103ef8bd, 0x0101f001, 0xea004311, 0xf8bd0141, 0xf000003c, 0x43080001, 0x0046f8ad, 0xf000a812, 
+    0xf8bdfc33, 0x48fe1026, 0xfc0bf001, 0xf8bd48fc, 0x1e80103a, 0xfc05f001, 0xf8bd48f9, 0x1d001046, 
+    0xfbfff001, 0xf8bd48f6, 0x1c801068, 0xfbf9f001, 0x2000bc10, 0xfb14f85d, 0x4ff0e92d, 0x0903ea5f, 
+    0xb0ab4690, 0x4607468b, 0x2000d01b, 0x46822120, 0xf000a815, 0x2114fe15, 0xf000a826, 0x2400fe11, 
+    0x21244625, 0xa81d462e, 0xfe0af000, 0x0f00f1ba, 0xf1b8d00d, 0xdd060f12, 0x0006f1a8, 0xb2c02206, 
+    0x2001e009, 0x2200e7e2, 0x00fff008, 0xf008e003, 0xf00900ff, 0xebab02ff, 0x1a090107, 0xf0011a89, 
+    0xf04f0cff, 0x07d30101, 0x2a06d101, 0xf8add301, 0x2a021098, 0xf8add301, 0x2a0410a0, 0x2a06d305, 
+    0x10a4f8ad, 0xf8add301, 0x4ace109c, 0x2a01403a, 0x2f0ad001, 0xf8addb01, 0x2f021074, 0xf8addb01, 
+    0x2f04108c, 0xf8addb01, 0x2f061086, 0xf8addb01, 0x2f081080, 0x2f0adb05, 0x107af8ad, 0xf8addb01, 
+    0x07c2106a, 0x2808d101, 0xf8add301, 0x28021054, 0xf8add301, 0x2804105c, 0xf8add301, 0x28061060, 
+    0x2808d305, 0x1064f8ad, 0xf8add301, 0xf8bd1058, 0xb9fb306a, 0xd00107c2, 0xd2192808, 0xd2172812, 
+    0x207af8bd, 0xd1012a01, 0xd211280a, 0x2080f8bd, 0xd1012a01, 0xd20b280c, 0x2086f8bd, 0xd1012a01, 
+    0xd205280e, 0x208cf8bd, 0xd1032a01, 0xd3012810, 0x106cf8ad, 0x207af8bd, 0x0a02ea5f, 0x280ad103, 
+    0xf8add301, 0xf8bd107c, 0xea5f2080, 0xd1030902, 0xd301280c, 0x1082f8ad, 0x2086f8bd, 0x0802ea5f, 
+    0x280ed103, 0xf8add301, 0xf8bd1088, 0xb91f708c, 0xd3012810, 0x108ef8ad, 0x2074f8bd, 0x2812b9b2, 
+    0xf1bad212, 0xd1010f01, 0xd20d280a, 0x0f01f1b9, 0x280cd101, 0xf1b8d208, 0xd1010f01, 0xd203280e, 
+    0xd1032f01, 0xd3012810, 0x1076f8ad, 0x0f00f1bc, 0xf1acd07d, 0xf00c0c01, 0xea5f00ff, 0xd0017cc0, 
+    0x040ff361, 0xd0f30840, 0x7cc0ea5f, 0x1e40d005, 0x441ff361, 0x00fff010, 0xb92dd0ea, 0xf0101e80, 
+    0xf36100ff, 0xd0e3050f, 0x4c15ea5f, 0x1e80d105, 0x451ff361, 0x00fff010, 0xea5fd0da, 0xd17c4c14, 
+    0xc09ef8bd, 0x0f00f1bc, 0xf8bdd10f, 0xf1bcc09c, 0xd10a0f00, 0xf8ad1e80, 0xf361109e, 0xf010441f, 
+    0xd0c500ff, 0x0c01ea5f, 0xf8bdd16b, 0xf1bcc09a, 0xd10f0f00, 0xc098f8bd, 0x0f00f1bc, 0x1e80d10a, 
+    0x109af8ad, 0x441ff361, 0x00fff010, 0xea5fd0b0, 0xd1560c01, 0xc05af8bd, 0x0f00f1bc, 0xf8bdd10f, 
+    0xf1bcc058, 0xd10a0f00, 0xf8ad1e80, 0xf361105a, 0xf010441f, 0xd09b00ff, 0x0c01ea5f, 0xf8bdd141, 
+    0xf1bcc056, 0xd10f0f00, 0xc054f8bd, 0x0f00f1bc, 0x1e80d10a, 0x1056f8ad, 0x441ff361, 0x00fff010, 
+    0xea5fd086, 0xd12c0c01, 0xc078f8bd, 0xe0d6e000, 0x0f00f1bc, 0xb97ad110, 0xc076f8bd, 0x0f00f1bc, 
+    0x1e80d10a, 0x1078f8ad, 0x441ff361, 0x00fff010, 0xea5fd089, 0xd1140c01, 0xc06ef8bd, 0x0f00f1bc, 
+    0xb953d10f, 0xc06cf8bd, 0x0f00f1bc, 0xf361d109, 0xf8ad441f, 0x1e80106e, 0xe002e000, 0x00fff010, 
+    0xf8bdd08f, 0xf1bcc0a6, 0xd10a0f00, 0xc0a4f8bd, 0x0f00f1bc, 0x1e80d105, 0x10a6f8ad, 0x00fff010, 
+    0xf8bdd094, 0xf1bcc0a2, 0xd10a0f00, 0xc0a0f8bd, 0x0f00f1bc, 0x1e80d105, 0x10a2f8ad, 0x00fff010, 
+    0xf8bdd084, 0xf1bcc066, 0xd10a0f00, 0xc064f8bd, 0x0f00f1bc, 0x1e80d105, 0x1066f8ad, 0x00fff010, 
+    0xf8bdd07d, 0xf1bcc062, 0xd10a0f00, 0xc060f8bd, 0x0f00f1bc, 0x1e80d105, 0x1062f8ad, 0x00fff010, 
+    0xf8bdd06d, 0xf1bcc05e, 0xd10a0f00, 0xc05cf8bd, 0x0f00f1bc, 0x1e80d105, 0x105ef8ad, 0x00fff010, 
+    0xf8bdd05d, 0xf1bcc090, 0xd10e0f00, 0xf8bdb96f, 0xb957708e, 0xf8ad1e80, 0xf0101090, 0xe00300ff, 
+    0xf303a238, 0x80000001, 0xf8bdd049, 0xb95f708a, 0x0f00f1b8, 0xf8bdd108, 0xb92f7088, 0xf8ad1e80, 
+    0xf010108a, 0xd03a00ff, 0x7084f8bd, 0xf1b9b95f, 0xd1080f00, 0x7082f8bd, 0x1e80b92f, 0x1084f8ad, 
+    0x00fff010, 0xf8bdd02b, 0xb95f707e, 0x0f00f1ba, 0xf8bdd108, 0xb92f707c, 0xf8ad1e80, 0xf010107e, 
+    0xd01c00ff, 0x709ef8bd, 0xf8bdbbf7, 0xbbdf709c, 0xc09af8bd, 0x0f00f1bc, 0xf8bdd110, 0xf1bcc098, 
+    0xd10b0f00, 0xf8ad1e80, 0xf010109e, 0xf8ad00ff, 0xd004109a, 0x0c01ea5f, 0xbb2fd128, 0xe08fe000, 
+    0xc05af8bd, 0x0f00f1bc, 0xf8bdd110, 0xf1bcc058, 0xd10b0f00, 0xf8ad1e80, 0xf010109e, 0xf8ad00ff, 
+    0xd07d105a, 0x0c01ea5f, 0xb96fd110, 0x7056f8bd, 0xf8bdb957, 0xb93f7054, 0xf8ad1e80, 0xf010109e, 
+    0xf8ad00ff, 0xe0001056, 0xd069e000, 0x709af8bd, 0xf8bdbb37, 0xbb1f7098, 0xc05af8bd, 0x0f00f1bc, 
+    0xf8bdd110, 0xf1bcc058, 0xd10b0f00, 0xf8ad1e80, 0xf010109a, 0xf8ad00ff, 0xd051105a, 0x0c01ea5f, 
+    0xb96fd10e, 0x7056f8bd, 0xf8bdb957, 0xb93f7054, 0xf8ad1e80, 0xf010109a, 0xf8ad00ff, 0xd03f1056, 
+    0x705af8bd, 0xf8bdb987, 0xb96f7058, 0x7056f8bd, 0xf8bdb957, 0xb93f7054, 0xf8ad1e80, 0xf010105a, 
+    0xf8ad00ff, 0xd02b1056, 0x709ef8bd, 0xf8bdbb4f, 0xbb37709c, 0xc078f8bd, 0x0f00f1bc, 0xb982d111, 
+    0xc076f8bd, 0x0f00f1bc, 0x1e80d10b, 0x109ef8ad, 0x00fff010, 0x1078f8ad, 0xea5fd012, 0xd1120c01, 
+    0xf8bdb97f, 0xb967706e, 0xf8bdb95b, 0xb947706c, 0xf8ad1e80, 0xf010109e, 0xf8ad00ff, 0xe001106e, 
+    0xe000e080, 0xf8bdd07e, 0xbb47709a, 0x7098f8bd, 0xf8bdbb2f, 0xf1bcc078, 0xd1110f00, 0xf8bdb982, 
+    0xf1bcc076, 0xd10b0f00, 0xf8ad1e80, 0xf010109a, 0xf8ad00ff, 0xd07e1078, 0x0c01ea5f, 0xb977d10f, 
+    0x706ef8bd, 0xb953b95f, 0x706cf8bd, 0x1e80b93f, 0x109af8ad, 0x00fff010, 0x106ef8ad, 0xf8bdd06b, 
+    0xbb47705a, 0x7058f8bd, 0xf8bdbb2f, 0xf1bcc078, 0xd1110f00, 0xf8bdb982, 0xf1bcc076, 0xd10b0f00, 
+    0xf8ad1e80, 0xf010105a, 0xf8ad00ff, 0xd0521078, 0x0c01ea5f, 0xb977d10f, 0x706ef8bd, 0xb953b95f, 
+    0x706cf8bd, 0x1e80b93f, 0x105af8ad, 0x00fff010, 0x106ef8ad, 0xf8bdd03f, 0xbb577056, 0x7054f8bd, 
+    0xf8bdbb3f, 0xf1bcc078, 0xd1110f00, 0xf8bdb982, 0xf1bcc076, 0xd10b0f00, 0xf8ad1e80, 0xf0101056, 
+    0xf8ad00ff, 0xd0261078, 0x0c01ea5f, 0xb987d111, 0x706ef8bd, 0xb963b96f, 0x706cf8bd, 0xf8adb94f, 
+    0xe0001056, 0x1e80e017, 0x106ef8ad, 0x0ffff010, 0xf8bdd011, 0xb9700078, 0xf8bdb96a, 0xb9500076, 
+    0x006ef8bd, 0xb933b938, 0x006cf8bd, 0xf8adb918, 0xf8ad1078, 0x2222106e, 0xa80ca91d, 0xea86f000, 
+    0x2214ab09, 0xe883a926, 0xa8040070, 0xea7ef000, 0xe897af19, 0xaf15000f, 0x000fe88d, 0x000fe897, 
+    0xfc47f7ff, 0xe8bdb02b, 0xe92d8ff0, 0xf99047f0, 0x25007000, 0x8001f990, 0xf9902901, 0xf9906002, 
+    0xd0714003, 0x46324623, 0x46384641, 0xfbf8f7ff, 0xd1690005, 0x2300b15c, 0x220d4db3, 0x0100f242, 
+    0xf0014628, 0x2f00f878, 0x2301dd03, 0x2301e002, 0x2300e7f2, 0x0100f241, 0x4628220c, 0xf86bf001, 
+    0xdd012e00, 0xe0002301, 0xf6402300, 0x220b0100, 0xf0014628, 0x2c00f860, 0x2301dd01, 0x2300e000, 
+    0x4100f240, 0x4628220a, 0xf855f001, 0x22004d9e, 0x3d82210f, 0xb2fb4628, 0xf84df001, 0x213f2200, 
+    0xf0081ca8, 0xf00103ff, 0x2208f846, 0x7100f641, 0xb2f34628, 0xf83ff001, 0x22004893, 0x30d6210f, 
+    0xf001b2e3, 0x4623f838, 0x46414632, 0xf7ff4638, 0x4605fc23, 0x2200488c, 0x3834210f, 0xf839f001, 
+    0xc224f8df, 0x2801b240, 0x0c0af1ac, 0x0902f10c, 0x2804d002, 0xe014d009, 0x46602301, 0x21802207, 
+    0xf819f001, 0xe0072300, 0x2300e01b, 0x22074660, 0xf0012180, 0x2301f810, 0x22004648, 0xf0012101, 
+    0xeb07f80a, 0x44300008, 0x4c774420, 0x282d1f24, 0x2305dd01, 0x2304e000, 0x22024620, 0xf000213c, 
+    0x4628fffa, 0x87f0e8bd, 0xf64f7f02, 0xf00271ff, 0xea010201, 0x7e820342, 0x0201f002, 0xea01431a, 
+    0x7e020342, 0x0201f002, 0xea01431a, 0x7d820342, 0x0201f002, 0xea01431a, 0x7d020342, 0x0201f002, 
+    0xea01431a, 0x7c820342, 0x0201f002, 0xea01431a, 0x7c020342, 0x0201f002, 0xea01431a, 0x7b820342, 
+    0x0201f002, 0xea01431a, 0x7b020342, 0x0201f002, 0xea01431a, 0x7a820342, 0x0201f002, 0xea01431a, 
+    0x7a020342, 0x0201f002, 0xea01431a, 0x79820342, 0x0201f002, 0xea01431a, 0x79020342, 0x0201f002, 
+    0xea01431a, 0x78820342, 0x0201f002, 0xea01431a, 0x78010242, 0x0101f001, 0x84014311, 0x47702000, 
+    0xf64f7b82, 0xf00271ff, 0xea010201, 0x7b020342, 0x0201f002, 0xea01431a, 0x7a820342, 0x0201f002, 
+    0xea01431a, 0x7a020342, 0x0201f002, 0xea01431a, 0x79820342, 0x0201f002, 0xea01431a, 0x79020342, 
+    0x0201f002, 0xea01431a, 0x78820342, 0x0201f002, 0xea01431a, 0x78010242, 0x0101f001, 0x82414311, 
+    0x47702000, 0xf64f7e82, 0xf00271ff, 0xea010201, 0x7e020342, 0x0201f002, 0xea01431a, 0x7d820342, 
+    0x0201f002, 0x7c83431a, 0x0282ea01, 0x0301f003, 0x0242ea01, 0x7c024313, 0x0343ea01, 0x0201f002, 
+    0xea01431a, 0x7b820342, 0x0201f002, 0xea01431a, 0x7b020342, 0x0201f002, 0xea01431a, 0x7a820342, 
+    0x0201f002, 0xea01431a, 0x7a020342, 0x0201f002, 0x7983431a, 0x0242ea01, 0x0301f003, 0x79024313, 
+    0x0343ea01, 0x0201f002, 0xea01431a, 0x78820342, 0x0201f002, 0xea01431a, 0x78010242, 0x0101f001, 
+    0x83c14311, 0x47702000, 0xf303a14a, 0x4606b570, 0xf984f000, 0xf1066805, 0xf020000b, 0x42b40407, 
+    0x2000bf98, 0x462bd915, 0xb1ba686a, 0x42a06810, 0xf104d310, 0x42880108, 0x6850bf3c, 0xd3076058, 
+    0x19106851, 0x68116041, 0x60011b09, 0x60146058, 0xbd701d10, 0x68524613, 0xd1e72a00, 0x46284621, 
+    0xf964f000, 0xd1de2800, 0xb570bd70, 0x1f054604, 0xf954f000, 0x2c006800, 0x6844bf18, 0x2c00d01b, 
+    0x42acbf18, 0x4620bf3c, 0xd3f86864, 0x180a6801, 0xbf1842aa, 0xd1036045, 0x4605682a, 0x60014411, 
+    0x19416828, 0xbf1842a1, 0xd104606c, 0x60696861, 0x44086821, 0xbd706028, 0x0320f1b2, 0xf1c2d50a, 
+    0xfa010320, 0xfa20f102, 0xfa00f303, 0xea41f002, 0x47700103, 0xf103fa00, 0x0000f04f, 0xf1b24770, 
+    0xd50a0320, 0x0320f1c2, 0xf002fa20, 0xf303fa01, 0xf102fa21, 0x0003ea40, 0xfa214770, 0xf04ff003, 
+    0x47700100, 0xe92d4010, 0xe1b040c1, 0xe02440a3, 0x5a000002, 0xe2700000, 0xe2611000, 0x32411001, 
+    0xe1130003, 0x5a000002, 0xe2722000, 0xe2633000, 0x32433001, 0xeb0000a1, 0xe3140101, 0x0a000002, 
+    0xe2700000, 0xe2611000, 0x32411001, 0xe3140102, 0x0a000002, 0xe2722000, 0xe2633000, 0x32433001, 
+    0xe8bd8010, 0xe3520003, 0x9a000017, 0xe210c003, 0x0a000008, 0xe4d13001, 0xe35c0002, 0xe082200c, 
+    0x94d1c001, 0xe4c03001, 0x34d13001, 0x94c0c001, 0xe2422004, 0x34c03001, 0xe2113003, 0x0a000012, 
+    0xe2522008, 0x3a000004, 0xe4913004, 0xe2522008, 0xe491c004, 0xe8a01008, 0xeafffff9, 0xe2922004, 
+    0x54913004, 0x54803004, 0xe1a00000, 0xe1b02f82, 0x24d13001, 0x24d1c001, 0x44d12001, 0x24c03001, 
+    0x24c0c001, 0x44c02001, 0xe12fff1e, 0xe92d4010, 0xe2522020, 0x3a000005, 0xe8b15018, 0xe2522020, 
+    0xe8a05018, 0xe8b15018, 0xe8a05018, 0x2afffff9, 0xe1b0ce02, 0x28b15018, 0x28a05018, 0x48b10018, 
+    0x48a00018, 0xe8bd4010, 0xe1b0cf02, 0x24913004, 0x24803004, 0x012fff1e, 0xe1b02f82, 0x20d130b2, 
+    0x44d12001, 0x20c030b2, 0x44c02001, 0xe12fff1e, 0x03fff002, 0x2203ea43, 0x4202ea42, 0xba55f000, 
+    0x0200f04f, 0x4613b500, 0x46964694, 0xbf223920, 0x500ce8a0, 0x500ce8a0, 0x0120f1b1, 0xaff7f4bf, 
+    0xbf280709, 0x500ce8a0, 0xc00cbf48, 0xeb04f85d, 0xbf280089, 0x2b04f840, 0x4770bf08, 0xf820bf48, 
+    0xf0112b02, 0xbf184f80, 0x2b01f800, 0x00004770, 0xe3100003, 0xe92d4010, 0xe1a04000, 0x03110003, 
+    0x1a00000a, 0xe59fe04c, 0xe2522004, 0xba000006, 0xe4913004, 0xe043c00e, 0xe1ccc003, 0xe01cc38e, 
+    0x04803004, 0x0afffff7, 0xe2411004, 0xe2822004, 0xe2522001, 0xba000005, 0xe4d13001, 0xe3530000, 
+    0xe4c03001, 0x1afffff9, 0xe1a01002, 0xfb0000fc, 0xe1a00004, 0xe8bd8010, 0x01010101, 0x47704800, 
+    0x0004d8bc, 0x47704770, 0x47704770, 0x4604b538, 0x2000460a, 0xf0004669, 0x2800fa3c, 0x4602d005, 
+    0x99004620, 0xfa0af000, 0xbd382001, 0xf0002001, 0xb5f8ba1d, 0xfa22f000, 0x20004605, 0x2010460c, 
+    0x4606bf00, 0x42a019a8, 0x4632d90d, 0x20004669, 0xfa1ff000, 0xbf080007, 0xfa08f000, 0x42a09800, 
+    0x4605bf18, 0xf7ff19c4, 0x6005ffc9, 0x1df04607, 0x0007f020, 0x46281946, 0xf80af000, 0xd00642b4, 
+    0x68384631, 0xe8bd1ba2, 0xf00040f8, 0xbdf8b9d7, 0x60012100, 0x1001e9c0, 0x20104770, 0x00004770, 
+    0xe92d4070, 0xe1a04003, 0xe1a05002, 0xe1a03001, 0xe1a02000, 0xe3540000, 0x11a0c004, 0x01a0c005, 
+    0xe16fef1c, 0xe28e0001, 0xe1a0c01c, 0x127ee03f, 0x027ee01f, 0x4a000094, 0xe3530000, 0x116f1f13, 
+    0x016f1f12, 0x1271103f, 0x0271101f, 0xe051600e, 0x4a000092, 0x52760004, 0x5a000093, 0xe24e0020, 
+    0xe3500004, 0xd1a01035, 0xd18cc001, 0xe28f1f9f, 0xe1a0ce2c, 0xe35e001f, 0xe791c10c, 0x824ee020, 
+    0xe26e6020, 0x8a000048, 0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 
+    0xe2611000, 0x32411001, 0xe081019c, 0xe08cc001, 0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 
+    0xe1811004, 0xe2700000, 0xe2611000, 0x32411001, 0xe3530000, 0xe081019c, 0xe08cc001, 0x0a000009, 
+    0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 0xe2611000, 0x32411001, 
+    0xe081019c, 0xe08cc001, 0xe080129c, 0xe3a01000, 0xe0a1039c, 0xe1a00e30, 0xe1a04611, 0xe1800004, 
+    0xe1a01e31, 0xe0846590, 0xe0522006, 0xe0244591, 0xe0c33004, 0xe3530001, 0x31520005, 0x38bd8070, 
+    0xe086429c, 0xe3a04000, 0xe0a4639c, 0xe26ec020, 0xe1a06e36, 0xe1a03c14, 0xe1866003, 0xe3a03000, 
+    0xe1a04e34, 0xe08ce596, 0xe0900006, 0xe0a11004, 0xe042200e, 0xe1520005, 0x38bd8070, 0xe2900001, 
+    0xe2a11000, 0xe0422005, 0xe052c005, 0x21a0200c, 0xe2b00000, 0xe2a11000, 0xe052c005, 0x21a0200c, 
+    0xe2b00000, 0xe2a11000, 0xe8bd8070, 0xe080159c, 0xe3a01000, 0xe0a1049c, 0xe1a01611, 0xe1a06e30, 
+    0xe1811006, 0xe26e6020, 0xe2611000, 0xe1a00610, 0xe2700000, 0x32411001, 0xe081019c, 0xe08cc001, 
+    0xe080159c, 0xe3a01000, 0xe0a1049c, 0xe1a01611, 0xe1a06e30, 0xe1811006, 0xe26e6020, 0xe2611000, 
+    0xe1a00610, 0xe2700000, 0x32411001, 0xe081019c, 0xe08cc001, 0xe24cc001, 0xe080129c, 0xe3a01000, 
+    0xe0a1039c, 0xe1a00e31, 0xe0816590, 0xe0522006, 0xe0211490, 0xe0c33001, 0xe1530004, 0x01520005, 
+    0x33a01000, 0x38bd8070, 0xe081629c, 0xe3a06000, 0xe0a6139c, 0xe3a01000, 0xe1a06e36, 0xe08ce596, 
+    0xe0800006, 0xe052200e, 0xe02ec496, 0xe0c3300e, 0xe1530004, 0x01520005, 0x38bd8070, 0xe2800001, 
+    0xe0522005, 0xe0c33004, 0xe8bd8070, 0xe92d000c, 0xe3a01000, 0xe3a00000, 0xe1a00000, 0xe8bd807c, 
+    0xe3a01000, 0xe3a00000, 0xe8bd8070, 0xe266e020, 0xe3a00000, 0xe3a01000, 0xe1a04614, 0xe1a0ce35, 
+    0xe1a05615, 0xe184400c, 0xe052e005, 0xe0d3c004, 0xe0a00000, 0x21a0300c, 0x21a0200e, 0xe2566001, 
+    0x38bd8070, 0xe1b040a4, 0xe1a05065, 0xeafffff5, 0xf0f0f0f0, 0xe38e38e3, 0xd79435e5, 0xcccccccc, 
+    0xc30c30c3, 0xba2e8ba2, 0xb21642c8, 0xaaaaaaaa, 0xa3d70a3d, 0x9d89d89d, 0x97b425ed, 0x92492492, 
+    0x8d3dcb08, 0x88888888, 0x84210842, 0x80000000, 0xf000b510, 0x6800f82f, 0xb510bd10, 0xf0004604, 
+    0x6004f829, 0xf04fbd10, 0x29040200, 0x8012f0c0, 0x0c03f010, 0xada6f43f, 0x0c04f1cc, 0x0f02f1bc, 
+    0xf800bf18, 0xbfa82b01, 0x2b02f820, 0x010ceba1, 0xbd98f7ff, 0x7cc1ea5f, 0xf800bf24, 0xf8002b01, 
+    0xbf482b01, 0x2b01f800, 0x00004770, 0x47704800, 0x0004d8b4, 0x47704800, 0x0004d8b4, 0x6843468c, 
+    0xbf182b00, 0xbf38428b, 0xd3f84618, 0x44186803, 0xd0074288, 0x0003f10c, 0x0007f020, 0x1a411d00, 
+    0x46011a52, 0x600a1d08, 0xbc6ff7ff, 0xf000b510, 0xe8bdf85f, 0xf0004010, 0x0000b855, 0x46694b12, 
+    0x5280f500, 0x601a428a, 0x4611d801, 0x60194770, 0xb5304770, 0x466b4d0c, 0x5380f5a3, 0x4422682c, 
+    0xd80f429a, 0xf5021a9b, 0xeb035080, 0xeb0273d3, 0x42980363, 0x4618d900, 0xf0201dc0, 0x600c0207, 
+    0x602a1b10, 0x0000bd30, 0x0004120c, 0x46754770, 0xffacf7ff, 0x000546ae, 0x46534669, 0x0007f020, 
+    0xb0184685, 0xf001b520, 0xe8bdeab8, 0xf04f4020, 0xf04f0600, 0xf04f0700, 0xf04f0800, 0xf0210b00, 
+    0x46ac0107, 0x09c0e8ac, 0x09c0e8ac, 0x09c0e8ac, 0x09c0e8ac, 0x4770468d, 0xf3af4604, 0x46208000, 
+    0xf9fdf7d8, 0xd0012800, 0xb82af000, 0x00004770, 0x2801b510, 0x2100d005, 0xf000a003, 0x2001f827, 
+    0xa109bd10, 0x0000e7f8, 0x52474953, 0x4d454d54, 0x754f203a, 0x666f2074, 0x61656820, 0x656d2070, 
+    0x79726f6d, 0x00000000, 0x6548203a, 0x6d207061, 0x726f6d65, 0x6f632079, 0x70757272, 0x00646574, 
+    0x20184901, 0xe7fedfab, 0x00020026, 0x4605b570, 0x200a460c, 0x1c6de000, 0xf811f000, 0x7828b135, 
+    0xd1f82800, 0x1c64e002, 0xf809f000, 0x7820b114, 0xd1f82800, 0x4070e8bd, 0xf3af200a, 0xb5088000, 
+    0xf88d4669, 0x20030000, 0xbd08dfab, 0xe92d0003, 0xe59f0050, 0xe580e000, 0xe59f004c, 0xe5901000, 
+    0xe3510000, 0x1a000001, 0xe59f1040, 0xe5801000, 0xe2811001, 0xe5801000, 0xe59f0034, 0xee151f10, 
+    0xe5801000, 0xe59f002c, 0xee161f10, 0xe5801000, 0xe59f0024, 0xee151f11, 0xe5801000, 0xe8bd0003, 
+    0xe25ef008, 0xe320f000, 0xf000300c, 0xf0003010, 0xdead0000, 0xf0003020, 0xf0003024, 0xf0003028, 
+    0xf04fb500, 0xee116060, 0xea011f30, 0xee010100, 0xee111f30, 0xf3bf0f30, 0xf85d8f6f, 0x4770eb04, 
+    0xee15b500, 0xf3bf0f10, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f30, 0xf85d8f6f, 0x4770eb04, 
+    0xee15b500, 0xf3bf0f11, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f31, 0xf85d8f6f, 0x4770eb04, 
+    0xee16b500, 0xf3bf0f10, 0xf85d8f6f, 0x4770eb04, 0xee16b500, 0xf3bf0f50, 0xf85d8f6f, 0x4770eb04, 
+    0x5ffce92d, 0x4601468a, 0x0000f04f, 0x2b01f811, 0x03bbf04f, 0xd128429a, 0x2b01f811, 0x03a7f04f, 
+    0xd122429a, 0x2b01f811, 0xd11e4282, 0x2b01f811, 0xd11a4282, 0xf04f4650, 0xf04f0a00, 0x5c8c0200, 
+    0x050aea84, 0x06fff005, 0x5016f830, 0x261aea4f, 0x0a06ea85, 0x0201f102, 0xdbf02a0a, 0xf04f5a8c, 
+    0x45540001, 0xf04fd001, 0xe8bd0000, 0x00009ffc, 0xe92d500f, 0xe14fc000, 0xe92d1000, 0xe59f0028, 
+    0xe5901000, 0xe201103f, 0xe1a01201, 0xe59f201c, 0xe0822001, 0xe5920000, 0xe8bd1000, 0xe16ff00c, 
+    0xe8bd500f, 0xe25ef004, 0xe320f000, 0xf0001014, 0xf0001104, 0x5ff0e92d, 0x7f80f5b2, 0x2a80d003, 
+    0x2a40d004, 0xf8dfd005, 0xe00490f8, 0x90f4f8df, 0xf8dfe001, 0xea4f90f4, 0xea4f0a52, 0x880c0b92, 
+    0x4b02f823, 0xf8238804, 0xf8314b02, 0xf823401b, 0xf8304b02, 0xf823401b, 0xf04f4b02, 0xf8190701, 
+    0xf8315007, 0xf8234015, 0xf8304b02, 0xf8234015, 0xebaa4b02, 0xf8310505, 0xf1c44015, 0xf8230400, 
+    0xf8304b02, 0xf8234015, 0xf1074b02, 0x455f0701, 0xafe5f6ff, 0x9ff0e8bd, 0x5ff0e92d, 0x7f80f5b1, 
+    0x2980d003, 0x2940d004, 0xf8dfd005, 0xe0049074, 0x9070f8df, 0xf8dfe001, 0xea4f9070, 0xea4f0a51, 
+    0xf04f0b91, 0xf9300700, 0x801c4b02, 0x4b02f930, 0xf1078014, 0xf9300701, 0xf8234b02, 0xf930401b, 
+    0xf8226b02, 0xf819601b, 0xf9305007, 0xf8234b02, 0xf9304015, 0xf8226b02, 0xebaa6015, 0xf9300505, 
+    0xf1c44b02, 0xf8230400, 0xf9304015, 0xf8226b02, 0xf1076015, 0x455f0701, 0xafe5f6ff, 0x9ff0e8bd, 
+    0x0002c9c8, 0x0002ca08, 0x0002ca28, 0x5ff0e92d, 0x0a00f04f, 0x4694468b, 0x1000f9b0, 0x2002f9b0, 
+    0x0302eb01, 0x5004f9b0, 0x6006f9b0, 0x0706eb05, 0x0806eba5, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 
+    0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0402eba1, 
+    0x0706eb05, 0x0806eba5, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 
+    0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0301eba2, 0x0706eb05, 0x0806eba5, 0x0907eb03, 
+    0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 
+    0x9b04f84c, 0x0302eb01, 0x0400f1c3, 0x0706eb05, 0x0806eba5, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 
+    0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0008f100, 
+    0x0a01f10a, 0xf6ff45da, 0xe8bdaf87, 0x00009ff0, 0xe92d500f, 0xe14fc000, 0xe92d1000, 0xe59f0028, 
+    0xe5901000, 0xe201103f, 0xe1a01201, 0xe59f201c, 0xe0822001, 0xe5920000, 0xe8bd1000, 0xe16ff00c, 
+    0xe8bd500f, 0xe25ef004, 0xe320f000, 0xf000100c, 0xf0001104, 0x5ffce92d, 0x0300f04f, 0x4023f850, 
+    0x4023f841, 0x0301f103, 0xf6ff4293, 0xe8bdaff7, 0xe92d9ffc, 0xf04f5ffc, 0x2b000500, 0xf1c3da02, 
+    0xe00b0300, 0x4025f850, 0xf403fa04, 0x4025f841, 0x0501f105, 0xf6ff4295, 0xe00aaff5, 0x4025f850, 
+    0xf403fa44, 0x4025f841, 0x0501f105, 0xf6ff4295, 0xe8bdaff5, 0xe92d9ffc, 0xf04f5ffc, 0xf8300300, 
+    0xf8214013, 0xf1034013, 0x42930301, 0xaff7f6ff, 0x9ffce8bd, 0x5ffce92d, 0x0300f04f, 0x4013f930, 
+    0x4023f841, 0x0301f103, 0xf6ff4293, 0xe8bdaff7, 0xe92d9ffc, 0xf04f5ff0, 0xf9300500, 0xfa044b02, 
+    0xf841f403, 0xf1054b04, 0x42950501, 0xaff5f6ff, 0x9ff0e8bd, 0x5ffce92d, 0x0701f1a3, 0x0601f04f, 
+    0xf607fa06, 0x0500f04f, 0x4025f850, 0xfa444434, 0xf821f403, 0xf1054015, 0x42950501, 0xaff4f6ff, 
+    0x9ffce8bd, 0xe92d5ffc, 0xeafffffe, 0xe8bd9ffc, 0x6800b500, 0xb500bd00, 0xbd006001, 0x8800b500, 
+    0xb500bd00, 0xbd008001, 0x41f0e92d, 0xea246804, 0xfa030401, 0xea05f502, 0xea440501, 0x60040405, 
+    0x81f0e8bd, 0x41f0e92d, 0xea006800, 0xfa200001, 0xe8bdf002, 0xe92d81f0, 0x880441f0, 0x0401ea24, 
+    0xf502fa03, 0x0501ea05, 0x0405ea44, 0xe8bd8004, 0xe92d81f0, 0x880041f0, 0x0001ea00, 0xf002fa20, 
+    0x81f0e8bd, 0xe59f1150, 0xe5910000, 0xe590e000, 0xe59f0148, 0xe8be0002, 0xe5801000, 0xe8be0001, 
+    0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 0xef000000, 0xe12fff1e, 0xe28ee004, 
+    0xe92d0001, 0xe94d2000, 0xe320f000, 0xe24dd004, 0xe8bd0001, 0xe9204000, 0xe1a0e000, 0xe8bd0001, 
+    0xe94e7fff, 0xe320f000, 0xe24ee03c, 0xe14f0000, 0xe92e0001, 0xe59f00e4, 0xe5900000, 0xe92e0001, 
+    0xe59f10d4, 0xe5910000, 0xe580e000, 0xe59f00d0, 0xe1a0e00f, 0xe12fff10, 0xe59f10bc, 0xe5910000, 
+    0xe590e000, 0xe59f00b4, 0xe8be0002, 0xe5801000, 0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 
+    0xe59ee03c, 0xe25ef004, 0xe92d0001, 0xe94d2000, 0xe320f000, 0xe24dd004, 0xe8bd0001, 0xe9204000, 
+    0xe1a0e000, 0xe8bd0001, 0xe94e7fff, 0xe320f000, 0xe24ee03c, 0xe14f0000, 0xe92e0001, 0xe59f005c, 
+    0xe5900000, 0xe92e0001, 0xe59f104c, 0xe5910000, 0xe580e000, 0xe59f004c, 0xe1a0e00f, 0xe12fff10, 
+    0xe59f003c, 0xe1a0e00f, 0xe12fff10, 0xe59f1028, 0xe5910000, 0xe590e000, 0xe59f0020, 0xe8be0002, 
+    0xe5801000, 0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 0x00041198, 
+    0x000411e8, 0x000247e7, 0x00024677, 0x41f0e92d, 0x460c4603, 0xea218819, 0x80190104, 0x0104ea41, 
+    0x42806810, 0x8019dcfc, 0x81f0e8bd, 0x41f0e92d, 0xea45880d, 0x800d0502, 0x0502ea25, 0x4284681c, 
+    0x800ddcfc, 0x81f0e8bd, 0xe92d0003, 0xe59f0034, 0xe59f1034, 0xe5801000, 0xe59f0030, 0xee151f31, 
+    0xe5801000, 0xe59f0028, 0xee151f30, 0xe5801000, 0xe59f0020, 0xee161f50, 0xe5801000, 0xe8bd0003, 
+    0xe25ef004, 0xe320f000, 0xf0003010, 0xfec0dead, 0xf000302c, 0xf0003030, 0xf0003034, 0x5ffce92d, 
+    0xf1a59d0d, 0xf04f0c05, 0xfa0b0b01, 0xea4ffa05, 0xb40c0a9a, 0x9a10b403, 0xf1009800, 0xf04f0104, 
+    0xf84d0e00, 0xf04fcd04, 0xb4040900, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 
+    0x0505eba3, 0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 
+    0xfb360600, 0xf8414413, 0xf840c03a, 0xeb02403a, 0xf84002cb, 0xf8417b08, 0xf1098b08, 0x45d10901, 
+    0xafd4f6ff, 0x00caeb00, 0x01caeb01, 0xf10ebc04, 0x45de0e01, 0xafc7f6ff, 0x0b4bea4f, 0x0a5aea4f, 
+    0xcb04f85d, 0x0c01f1ac, 0x0f00f1bc, 0x9800dcb4, 0x0104f100, 0x0e00f04f, 0x2982f645, 0x6803b404, 
+    0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 0xf8400606, 0xf841503a, 
+    0xf840603a, 0xf8417b08, 0xeb028b08, 0x680302cb, 0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 
+    0xeba30806, 0xeba40505, 0x68130606, 0x0545ea4f, 0x0646ea4f, 0xfc13fb35, 0xf403fb35, 0xcc03fb36, 
+    0x0600f1c6, 0x4413fb36, 0xc03af841, 0x403af840, 0x120beb02, 0x7b08f840, 0x8b08f841, 0xf8506803, 
+    0x680c503a, 0x603af851, 0x0705eba3, 0x0806eba4, 0x4426441d, 0x0307eb08, 0x0807eba8, 0x0343ea4f, 
+    0x0848ea4f, 0xf309fb33, 0xf809fb38, 0x303af840, 0x803af841, 0x5b08f840, 0x6b08f841, 0xf8506803, 
+    0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 0x0606eba4, 0xea4f6813, 0xea4f0545, 
+    0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 0xf8414413, 0xf840c03a, 0xeb02403a, 
+    0xf840120b, 0xf8417b08, 0x68038b08, 0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba50806, 
+    0xeba40503, 0xf8410606, 0xf840503a, 0xf840603a, 0xf8417b08, 0x68038b08, 0x503af850, 0xf851680c, 
+    0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 0x68130606, 0x0545ea4f, 0x0646ea4f, 0xfc13fb35, 
+    0xf403fb35, 0xcc03fb36, 0x0600f1c6, 0x4413fb36, 0xc03af841, 0x403af840, 0x120beb02, 0x7b08f840, 
+    0x8b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0806eba4, 0x4426441d, 0x0307eb08, 
+    0x0807eba8, 0x0343ea4f, 0x0848ea4f, 0xf309fb33, 0xf809fb38, 0x0300f1c3, 0x803af840, 0x303af841, 
+    0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 
+    0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 
+    0xf8414413, 0xf840c03a, 0xeb02403a, 0xf84002cb, 0xf8417b08, 0xeb008b08, 0xeb0100ca, 0xbc0401ca, 
+    0x0e01f10e, 0xf6ff45de, 0xea4faee9, 0xea4f0b4b, 0x98000a5a, 0x0104f100, 0x0800f04f, 0x2982f645, 
+    0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0206eb04, 0x0505eba3, 0x0606eba4, 0x503af840, 
+    0x603af841, 0x7b08f840, 0x2b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0206eba4, 
+    0x4426441d, 0x0307eb02, 0x0207eba2, 0x0343ea4f, 0x0242ea4f, 0xf309fb33, 0xf209fb32, 0x303af840, 
+    0x203af841, 0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0206eb04, 
+    0x0503eba5, 0x0606eba4, 0x503af841, 0x603af840, 0x7b08f840, 0x2b08f841, 0xf8506803, 0x680c503a, 
+    0x603af851, 0x0705eba3, 0x0206eba4, 0x4426441d, 0x0307eb02, 0x0207eba2, 0x0343ea4f, 0x0242ea4f, 
+    0xf309fb33, 0xf209fb32, 0x0300f1c3, 0x203af840, 0x303af841, 0x5b08f840, 0x6b08f841, 0x00caeb00, 
+    0x01caeb01, 0x0801f108, 0xf6ff45d8, 0xea4faf89, 0x98000b4b, 0x0104f100, 0x0800f04f, 0x2b08f850, 
+    0x3b08f850, 0x4b08f850, 0xf8516805, 0xf8516b08, 0xf8517b08, 0xf8d19b08, 0xeb02a000, 0xeba20c04, 
+    0xeb060204, 0xeba60409, 0xeb030609, 0xeba30905, 0xeb070305, 0xeba7050a, 0xeb0c070a, 0xebac0a09, 
+    0xeb040c09, 0xeba40905, 0xeb020405, 0xeba20507, 0xeb060207, 0xeba60703, 0xf8400603, 0xf8402908, 
+    0xf8405908, 0xf840c908, 0xf841ab20, 0xf8417908, 0xf8416908, 0xf8414908, 0xf1089b20, 0x45d80801, 
+    0xafbcf6ff, 0x058bea4f, 0xf985fab5, 0x091ef1c9, 0x0c1ff1c9, 0x0b59ea4f, 0x0b01f10b, 0x0901f009, 
+    0xbc0344cb, 0xf850bc0c, 0xf8509b04, 0xf850ab04, 0xf8504b04, 0xeb09790c, 0xeba9060a, 0xf04f090a, 
+    0xfa460800, 0xfa49f60b, 0xfa44f90b, 0xfa47f40b, 0x6016f70b, 0x8000f8c3, 0x9025f842, 0x8025f843, 
+    0x0655ea4f, 0xf842442e, 0xf8434026, 0xf1c77026, 0xf8420700, 0xf8434015, 0xf8dd7015, 0xf04fe030, 
+    0xb4200402, 0x6034f850, 0x0004f100, 0x7034f850, 0x0004f100, 0xf90cfa04, 0xf9a9fa99, 0x0109eba5, 
+    0xf1a1fa91, 0xf10cfa21, 0x01fef001, 0x8031f850, 0x0004f100, 0x1031f850, 0x000cf1a0, 0x0a08eb06, 
+    0x0608eba6, 0x0801eb07, 0x0701eba7, 0x1029f85e, 0x0767ea4f, 0xf511fb36, 0x0600f1c6, 0x5501fb38, 
+    0xf601fb36, 0x0a6aea4f, 0x6611fb38, 0x0105eb0a, 0x0a05ebaa, 0x0806eb07, 0x0706eba7, 0xf10bfa41, 
+    0xf80bfa48, 0xfa0bfa4a, 0xf70bfa47, 0x1029f842, 0x8029f843, 0xeb09bc20, 0xf8420605, 0xf843a026, 
+    0xeba57026, 0xf1c70609, 0xf8420700, 0xf843a026, 0x442e7026, 0x0800f1c8, 0x1026f842, 0x8026f843, 
+    0x0402f104, 0xdb9c42ac, 0x5ffce8bd, 0x00004770, 0x5ffce92d, 0xf04f9e0d, 0xfa0b0b01, 0xea4ff506, 
+    0xf1a60555, 0xf1c90902, 0x68060c1f, 0x9025f850, 0x4015f850, 0x7015f851, 0x0700f1c7, 0x0a09eba6, 
+    0xea4f44b1, 0xea4f0a6a, 0xf8420969, 0xf8429b04, 0xf842ab04, 0xf8424b04, 0xf8dd790c, 0xf04fe030, 
+    0xfa040402, 0xfa99f90c, 0xf850f9a9, 0xf8513029, 0xeba58029, 0xf8500609, 0xf851a026, 0xeb037026, 
+    0xeba3060a, 0xeba8030a, 0x44b80a07, 0x7029f85e, 0x0a6aea4f, 0xfb07fb33, 0xf317fb33, 0xbb17fb38, 
+    0x0800f1c8, 0x0666ea4f, 0x3307fb38, 0x0806eb03, 0x0303eba6, 0x060aeb0b, 0x0b0aebab, 0x8034f842, 
+    0x0204f102, 0x6034f842, 0x0204f102, 0x0809eba5, 0xf8a8fa98, 0xf80cfa28, 0x08fef008, 0x3038f842, 
+    0x0204f102, 0xb038f842, 0x020cf1a2, 0x0402f104, 0xdbb642ac, 0xf1a59d0d, 0xf04f0c01, 0xfa0a0a01, 
+    0xea4ffb05, 0xb4040b9b, 0x98009a0d, 0x0e00f04f, 0x0b5bea4f, 0xcd04f84d, 0x1b08f850, 0x3b08f850, 
+    0x4b08f850, 0x5914f850, 0x6b08f850, 0x7b08f850, 0x8b08f850, 0x9904f850, 0x0c03eb01, 0x0103eba1, 
+    0x0307eb06, 0x0607eba6, 0x0705eb04, 0x0405eba4, 0x0509eb08, 0x0809eba8, 0x0907eb0c, 0x0c07ebac, 
+    0x0705eb03, 0x0305eba3, 0x0508eb01, 0x0108eba1, 0x0804eb06, 0x0604eba6, 0x5908f840, 0xc908f840, 
+    0x1908f840, 0x9b1cf840, 0x6908f840, 0x3908f840, 0x8908f840, 0x7b1cf840, 0x0e01f10e, 0xf6ff45de, 
+    0xf85dafbb, 0xea4fcb04, 0xea4f0b5b, 0xf1ac0a8a, 0x98000c02, 0x0104f100, 0x0e00f04f, 0x2982f645, 
+    0xf8506803, 0x680c503a, 0x603af851, 0x0805eb03, 0x0305eba3, 0x0506eb04, 0x0406eba4, 0x303af840, 
+    0x403af841, 0x8b08f840, 0x5b08f841, 0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0x680c6803, 
+    0x0806eba5, 0xfb384435, 0xfb35f809, 0xeb03f509, 0xeba30608, 0xeb040308, 0xeba40805, 0xf8400405, 
+    0xf841303a, 0xf840403a, 0xf8416b08, 0x680c8b08, 0x603af851, 0xf8506803, 0xeba3503a, 0x44330806, 
+    0x0605eb04, 0x0405eba4, 0x303af840, 0x403af841, 0x8b08f840, 0x6b08f841, 0x503af850, 0x603af851, 
+    0x0545ea4f, 0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 0x0506eba5, 0xf809fb38, 0xf509fb35, 
+    0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 
+    0x00caeb00, 0x01caeb01, 0x0e01f10e, 0xf6ff45de, 0xea4faf87, 0xea4f0b5b, 0xf1ac0a4a, 0x98000c01, 
+    0x0104f100, 0x0e00f04f, 0x6803b404, 0x503af850, 0xf851680c, 0xeb03603a, 0xeba30805, 0xeb040305, 
+    0xeba40506, 0xea4f0406, 0xea4f03e3, 0xea4f04e4, 0xea4f08e8, 0xf84005e5, 0xf841303a, 0xf840403a, 
+    0xf8418b08, 0xeb025b08, 0x680302cb, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 
+    0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 
+    0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 
+    0x8b08f841, 0x02cbeb02, 0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0x680c6803, 0x0806eba5, 
+    0xfb384435, 0xfb35f809, 0xeb03f509, 0xeba30608, 0xeb040308, 0xeba40805, 0xea4f0405, 0xea4f03e3, 
+    0xea4f04e4, 0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8416b08, 0xeb028b08, 0x680302cb, 
+    0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 
+    0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 
+    0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0xf851680c, 
+    0x6803603a, 0x503af850, 0x0806eba3, 0xeb044433, 0xeba40605, 0xea4f0405, 0xea4f03e3, 0xea4f04e4, 
+    0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8418b08, 0xeb026b08, 0x680302cb, 0x503af850, 
+    0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 
+    0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 
+    0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0x503af850, 0x603af851, 
+    0x0545ea4f, 0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 0x0506eba5, 0xf809fb38, 0xf509fb35, 
+    0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 
+    0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0xf8506803, 0x680c503a, 0x603af851, 
+    0x0545ea4f, 0xea4f6817, 0xfb350646, 0xf1c5f807, 0xfb350500, 0xfb36f517, 0xfb368817, 0xeb035507, 
+    0xeba30608, 0xeb040308, 0xeba40805, 0xea4f0405, 0xea4f03e3, 0xea4f04e4, 0xea4f06e6, 0xf84008e8, 
+    0xf841303a, 0xf840403a, 0xf8416b08, 0xeb028b08, 0xeb0002cb, 0xeb0100ca, 0xbc0401ca, 0x0e01f10e, 
+    0xf6ff45de, 0xea4faea1, 0xea4f0b5b, 0xf1ac0a4a, 0x98000c01, 0x0104f100, 0x0e00f04f, 0x0900f04f, 
+    0x6803b404, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 
+    0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x303af840, 
+    0x403af841, 0x02cbeb02, 0x6b08f840, 0x8b08f841, 0x0901f109, 0xf6ff45d1, 0xeb00afd4, 0xeb0100ca, 
+    0xbc0401ca, 0x0e01f10e, 0xf6ff45de, 0xea4fafc7, 0xea4f0b5b, 0xf1ac0a4a, 0xf1bc0c01, 0xdcb80f00, 
+    0xe8bdbc04, 0x47705ffc, 0x41f0e92d, 0x88079c06, 0x0701ea27, 0x0801ea47, 0x0500f04f, 0xf8a08007, 
+    0x88168000, 0x6025f843, 0x0501f105, 0xdbf542a5, 0xe8bdbf00, 0xe92d81f0, 0x880541f0, 0x0701ea25, 
+    0x0801ea45, 0xf8a08007, 0xf04f8000, 0xf04f0604, 0xf8320500, 0xf8327b02, 0xea488b02, 0xf8434707, 
+    0xf1057b04, 0x42b50501, 0xe8bddbf3, 0x000081f0, 0x5ffce92d, 0xf0f1fb90, 0x9ffce8bd, 0x5ffce92d, 
+    0xd0022908, 0x0008f340, 0xf340e001, 0xe8bd0007, 0x00009ffc, 0xe92d4001, 0xe14f0000, 0xe3100020, 
+    0x115e00b2, 0x13c00cff, 0x051e0004, 0x03c004ff, 0xe35000fe, 0x0a000007, 0xe35000ff, 0x0a000009, 
+    0xe3500000, 0x0a000001, 0xe8bd4001, 0xe1b0f00e, 0xe8bd4001, 0xeafffc60, 0xe14f0000, 0xe38000c0, 
+    0xe16ff000, 0xea000003, 0xe14f0000, 0xe3c000c0, 0xe16ff000, 0xeaffffff, 0xe8bd4001, 0xe1b0f00e, 
+    0x5ffce92d, 0x0400f04f, 0x5024f851, 0xf6f5fbb0, 0x6024f842, 0x0401f104, 0xf6ff429c, 0xe8bdaff5, 
+    0x00009ffc, 0x5ffce92d, 0xf0f1fbb0, 0x9ffce8bd, 0x0004d914, 0x0004ef14, 0xe51f0010, 0xe12fff1e, 
+    0xe92d0003, 0xe59f0010, 0xe59f1010, 0xe5801000, 0xe8bd0003, 0xe25ef004, 0xe320f000, 0xf0003010, 
+    0xdef0dead, 0xe51ff004, 0x0000d4b1, 0xe51ff004, 0x00007a1f, 0x46c04778, 0xe92d41f0, 0xf10c0080, 
+    0xe59f1028, 0xe5910000, 0xe3500000, 0x0a000003, 0xe3a00000, 0xe5810000, 0xf1080080, 0xe8bd81f0, 
+    0xf1080080, 0xf57ff04f, 0xe320f003, 0xe8bd81f0, 0x000401f4, 0x5ff0e92d, 0x0200f04f, 0x0300f04f, 
+    0x3022f840, 0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0x00009ff0, 0x5ff0e92d, 0x0200f04f, 0x0300f04f, 
+    0x3012f820, 0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0x00499ff0, 0x20c1ea50, 0x2004bf18, 0xbf180d4a, 
+    0x0001f040, 0x72fff240, 0x5f51ebb2, 0xf040bf08, 0x28010002, 0x2005bf08, 0xe92d4770, 0x460441f0, 
+    0x461e4615, 0xf0371e4f, 0xeb000206, 0xe9d101c7, 0xd00d0100, 0x4633462a, 0xf868f001, 0xeb041e7f, 
+    0xe9d303c7, 0xf0002300, 0xf037fd89, 0xd1f10206, 0xd0232f02, 0xd0112f04, 0xd1312f06, 0x4633462a, 
+    0xf854f001, 0x230ae9d4, 0xfd78f000, 0x4633462a, 0xf84cf001, 0x2308e9d4, 0xfd70f000, 0x4633462a, 
+    0xf844f001, 0x2306e9d4, 0xfd68f000, 0x4633462a, 0xf83cf001, 0x2304e9d4, 0xfd60f000, 0x4633462a, 
+    0xf834f001, 0x2302e9d4, 0xfd58f000, 0x4633462a, 0xf82cf001, 0x2300e9d4, 0x41f0e8bd, 0xbd4ef000, 
+    0x81f0e8bd, 0x22004902, 0x46104613, 0xbe02f000, 0x3ff00000, 0xbd42f000, 0x46132200, 0x46114610, 
+    0xbdf8f000, 0xf2402000, 0xf04f3201, 0xf00141e0, 0x0000be34, 0x20004a02, 0xf0010711, 0x0000be2e, 
+    0xfffffd01, 0x4df0e92d, 0x461c4616, 0x2800460f, 0xf021b094, 0xf0234100, 0xbf144200, 0x25002501, 
+    0xc410f8df, 0x0547eb05, 0xea4f4465, 0x429d036c, 0x0035d32b, 0x2501bf18, 0x0544eb05, 0x44ac4bfe, 
+    0xd322459c, 0x0306ea52, 0xd0024bfc, 0xd105429f, 0xb014b948, 0x20004619, 0x8df0e8bd, 0xbf082800, 
+    0x0c00f04f, 0xf04fd001, 0xeb0c0c01, 0xf5130347, 0xd80a1f00, 0xbf142e00, 0x0c01f04f, 0x0c00f04f, 
+    0x0344eb0c, 0x1f00f513, 0x4632d907, 0x46394623, 0xe8bdb014, 0xf7ff4df0, 0xf8dfbf9d, 0xf04f83a4, 
+    0x2f000a00, 0x4542bfb8, 0x4be6da23, 0xbfa8429a, 0x0a02f04f, 0x4be1da1d, 0xdc1a4293, 0xeb034be2, 
+    0x2b145322, 0xf1c3dd08, 0xfa260c34, 0xfa03f30c, 0x45b4fc0c, 0xe008d10d, 0xf1c3b95e, 0xfa220c14, 
+    0xfa03f30c, 0x4594fc0c, 0xf003d103, 0xf1c30301, 0xea510a02, 0xd11b0300, 0xda192c00, 0xbf182f00, 
+    0x0f02f1ba, 0xf1bad002, 0xd0070f01, 0xf7fe2002, 0xb014fb54, 0x4df0e8bd, 0xbf54f7ff, 0xf7fe2002, 
+    0xf7fffb4c, 0xf081ff4f, 0xb0144100, 0x8df0e8bd, 0xd16b0033, 0xd1204542, 0x4280f107, 0x1280f512, 
+    0x2800bf02, 0x49bd2000, 0x48bcd0ef, 0xdc054288, 0xbfa42c00, 0x46214618, 0xe007dae7, 0xda051e20, 
+    0xf080b014, 0x46184100, 0x8df0e8bd, 0x447949b7, 0x0100e9d1, 0xe8bdb014, 0xf8df8df0, 0x4562c2c0, 
+    0x2c00d12a, 0xb139da24, 0xd1174541, 0xbf042800, 0x46022000, 0xe006d11c, 0x2002b140, 0xfb0df7fe, 
+    0xff20f7ff, 0x4639460a, 0xbad2f000, 0x46394aa4, 0x2000b014, 0x011ef362, 0x8df0e8bd, 0x463bda08, 
+    0x46614602, 0x2000b014, 0x4df0e8bd, 0xbd02f000, 0xb0144639, 0x8df0e8bd, 0xda174541, 0x4f80f1b4, 
+    0xf1a4d00c, 0xf1b35300, 0xd10f53ff, 0xdb0d1e3b, 0xb0144619, 0x4df0e8bd, 0xbbd8f000, 0x463bb014, 
+    0x46194602, 0x4df0e8bd, 0xbf00f000, 0xf0270005, 0xd1384300, 0x4541b1d1, 0x2f00d135, 0x2c00dd04, 
+    0x2000bfa4, 0xdad44641, 0xdd012f00, 0xdb1f2c00, 0xda162f00, 0xdb142c00, 0x0000f04f, 0x0f01f1ba, 
+    0x497fbf14, 0xb0144982, 0x8df0e8bd, 0x0f02f1ba, 0x2f00bf18, 0xf1bad00c, 0xd1090f01, 0xda072f00, 
+    0x2f00e00b, 0x2c00bfb8, 0xf1bada0d, 0xd0040f01, 0x2000b014, 0xe8bd4601, 0xb0148df0, 0xf04f2000, 
+    0xe8bd4100, 0xf04f8df0, 0x46b80c01, 0x7ce7eb0c, 0xc044f8cd, 0x0c0aea5c, 0xf8dfd00d, 0x4562c1b8, 
+    0xf8dfdd7e, 0x4b6dc1b4, 0xdd124562, 0xdb0a428b, 0xdb182c00, 0x2001e023, 0xfa7ff7fe, 0xe8bdb014, 
+    0xf7ff4df0, 0x4a5dbe89, 0xdc02428a, 0xdc0a2c00, 0x4299e015, 0x2c00da02, 0xe004da11, 0x42994b57, 
+    0x2c00dd19, 0x2002dd0b, 0xfa67f7fe, 0xfe7af7ff, 0xb0144a53, 0x021ef361, 0xe8bd4611, 0x20028df0, 
+    0xfa5bf7fe, 0xfe76f7ff, 0xb0144a4c, 0x021ef361, 0xe8bd4611, 0x22008df0, 0xf0014641, 0xf06ff883, 
+    0x46050201, 0xf001460f, 0x4b4dfc98, 0x3255f04f, 0xffa0f000, 0x463b462a, 0xfe68f000, 0x22004b49, 
+    0xff98f000, 0x463b462a, 0x468b4680, 0x46194610, 0xfe5cf000, 0x465b4642, 0xfe58f000, 0x46804b42, 
+    0xf04f4628, 0x910942c0, 0xf0004639, 0x9107fe4f, 0x46404683, 0x4b3c4a3d, 0xf0009909, 0x4a3cfe47, 
+    0x46284680, 0x91014b3b, 0xf0004639, 0x9b01fe3f, 0xf0014642, 0x900cf847, 0x4602460d, 0xe000460b, 
+    0x9907e00e, 0xf0004658, 0x9b07fb59, 0x465a4688, 0x46382700, 0xf836f001, 0x462b9a0c, 0xb976f000, 
+    0x1f80f5b1, 0x0000f04f, 0x4628da07, 0x22354619, 0xfc43f001, 0xf06f4605, 0xeb000034, 0xf3c15221, 
+    0x4b250013, 0x31fff2a2, 0x677ff040, 0xf0474298, 0x91015740, 0xf04fbfd8, 0xdd0c0b00, 0x4281491f, 
+    0xf04fbfc8, 0xdc060b01, 0x0b00f04f, 0xf5a79801, 0x1c401780, 0x481a9001, 0x46394478, 0x00cbeb00, 
+    0xe9d09704, 0x46282300, 0x93099212, 0xfffaf000, 0x0000e028, 0x001fffff, 0x000fffff, 0x3ff00000, 
+    0x7ff00000, 0x43400000, 0xfffffc01, 0x00001d4e, 0xfff00000, 0x41e00000, 0x43f00000, 0x3fefffff, 
+    0x3fd55555, 0x3fe00000, 0x3ff71547, 0x652b82fe, 0xf85ddf44, 0x3e54ae0b, 0x0003988e, 0x000bb67a, 
+    0x00001a1c, 0x1007e9cd, 0x9b094628, 0x99049a12, 0xfae4f000, 0x20004602, 0x49fe460b, 0xfb9af000, 
+    0x46029100, 0x900c460b, 0x1007e9dd, 0xfdaef000, 0x46889006, 0x447848f8, 0x68009a12, 0xf04f900e, 
+    0xea405000, 0xeb000067, 0xf500408b, 0x9b092100, 0x2700980e, 0xf0009102, 0x9b04ffa5, 0xf000462a, 
+    0x463afec9, 0xf0004643, 0x9104fd91, 0x46384605, 0x9b024641, 0xf0009a0e, 0xe9ddfd89, 0xf0003207, 
+    0x9b04feb9, 0xf000462a, 0x9b00ff8d, 0xf0009a0c, 0x9a06fd7d, 0x91094643, 0x900c4619, 0xf0004610, 
+    0x4605fd75, 0x48dd4602, 0x9107460b, 0x44782106, 0xfcf3f7ff, 0x462a9b07, 0x90009102, 0x46194610, 
+    0xfd64f000, 0x9a009b02, 0xfd60f000, 0x46439a06, 0x46384605, 0x46199100, 0xfa80f000, 0x9a0c9b09, 
+    0xfd54f000, 0x462a9b00, 0xfa78f000, 0x4643463a, 0x90089100, 0x46194610, 0xfd48f000, 0x22004bc8, 
+    0x90049107, 0xfa6af000, 0x9a089b00, 0xfa66f000, 0x460d4bc3, 0x4638463a, 0xff44f000, 0x9a049b07, 
+    0xff40f000, 0x9a089b00, 0xfe64f000, 0x9104463a, 0x4641462b, 0x4610900a, 0xfd28f000, 0x1007e9cd, 
+    0x9a064643, 0x980a9904, 0xfd20f000, 0x4680462b, 0x460d980c, 0x9909463a, 0xfd18f000, 0x462b4642, 
+    0xfa3cf000, 0x46809100, 0x460b4602, 0x1007e9dd, 0xfa34f000, 0x3207e9dd, 0x2000460f, 0xf0004605, 
+    0x9b00ff11, 0xf0004642, 0x4ba6fe35, 0x46284680, 0x4260f04f, 0x46399109, 0xfcf8f000, 0x90049102, 
+    0x4aa14640, 0x99094b9f, 0xfcf0f000, 0x46804a9f, 0x4b9f4628, 0x46399103, 0xfce8f000, 0x46429b03, 
+    0xfa0cf000, 0x447a4a9b, 0x03cbeb02, 0x2300e9d3, 0xfa04f000, 0x98014605, 0xf0009105, 0x9000fc70, 
+    0xe9dd462a, 0x91030304, 0xf0009902, 0x4a92f9f7, 0xeb02447a, 0xe9d303cb, 0x46932300, 0xf0009301, 
+    0x9b03f9ed, 0xf0009a00, 0x9b03f9e9, 0x9a004688, 0x46382700, 0xfec6f000, 0x465a9b01, 0xfec2f000, 
+    0x9a049b02, 0xfebef000, 0x462a9b05, 0xfde2f000, 0x4d789b11, 0xf1aa2200, 0xea530c01, 0x9206030c, 
+    0x4d7ed101, 0xf04f9206, 0x46320a00, 0xf0004623, 0x4623fc9d, 0x46839103, 0x46304652, 0xf0004619, 
+    0x463afea1, 0xf0004643, 0x9b03fc91, 0xf000465a, 0x463af9b5, 0x46064643, 0x4650468b, 0xf0004621, 
+    0x4604fc85, 0x4632460f, 0xf000465b, 0x4a6cf9a7, 0x4291468a, 0xebaadb21, 0xea530302, 0xd1100200, 
+    0x463b4622, 0xfe7ef000, 0x46804a66, 0x4b664630, 0x46599101, 0xf992f000, 0x46429b01, 0xfd64f000, 
+    0x2002d22b, 0xf839f7fe, 0xfc4cf7ff, 0x4629460a, 0xf362b014, 0xe8bd011e, 0x4b5c8df0, 0x4200f02a, 
+    0xd31a429a, 0xeb0a4a5a, 0xea530302, 0xd1080200, 0x463b4622, 0xfe56f000, 0x465b4632, 0xfd44f000, 
+    0x2002d80b, 0xf819f7fe, 0xfc34f7ff, 0x5310ea4f, 0x4629460a, 0x5303ea4f, 0x494ee7da, 0x0800f04f, 
+    0xf02a4a4d, 0x42824000, 0x5120eb01, 0x484bda25, 0x1c80f44f, 0x1c494478, 0xfa2c6802, 0x4450f001, 
+    0x0301f1ac, 0x510af3c0, 0x31fff2a1, 0x0f00f1ba, 0xf301fa23, 0x0c13f3c0, 0x0114f1c1, 0x1c80f44c, 
+    0xf801fa2c, 0x0303ea20, 0xf1c8bfb8, 0x46200800, 0xf0004639, 0x4604fe17, 0x4630460f, 0x46224659, 
+    0xf000463b, 0x4b36f92b, 0x0a00f04f, 0x46529103, 0xf0004650, 0xe9cdfbfb, 0x46501007, 0x4b324a31, 
+    0xf0009903, 0x9102fbf3, 0x463b4622, 0x90049903, 0xf0004650, 0x4632fdf7, 0xf000465b, 0x4a2bfd1b, 
+    0xf0004b2b, 0x9b02fbe3, 0xf0009a04, 0x4607f907, 0x4602468a, 0xe9dd460b, 0xf0001007, 0xe9ddf8ff, 
+    0x46043207, 0xf000460e, 0x463afddd, 0xf0004653, 0x4622fd01, 0x900c4633, 0x4610460f, 0xf0004619, 
+    0x4682fbc5, 0x481b4602, 0x460b468b, 0x44782105, 0x0000e032, 0x3ff00000, 0x00001a06, 0x00001936, 
+    0x40080000, 0x3feec709, 0xdc3a03fd, 0x145b01f5, 0xbe3e2fe0, 0x0000180e, 0x000017d4, 0xbff00000, 
+    0x40900000, 0x652b82fe, 0x3c971547, 0x4090cc00, 0x3f6f3400, 0xfffffc01, 0x3fe00000, 0x00001708, 
+    0x3fe62e43, 0x0ca86c39, 0xbe205c61, 0xfefa39ef, 0x3fe62e42, 0x00001606, 0xfb0ff7ff, 0x465b4652, 
+    0xfb84f000, 0x46334622, 0xfcb4f000, 0x46829a0c, 0x463b468b, 0x46314620, 0xfb78f000, 0x463b9a0c, 
+    0xf89cf000, 0x46072200, 0xf04f4650, 0x91004380, 0xf0004659, 0x9103fd77, 0x465b4652, 0x900a4631, 
+    0xf0004620, 0x9b03fb63, 0xf0009a0a, 0x9b00f943, 0xf000463a, 0x4622fd67, 0xf0004633, 0x4b12fd63, 
+    0xf0002200, 0x460efc87, 0x5108eb01, 0x15084604, 0xdc102800, 0x46204642, 0xf0014631, 0xf7fff96e, 
+    0x2804fab8, 0xf7ffbf08, 0x4642fb35, 0x46314620, 0xf963f001, 0x98064604, 0x4629460b, 0x4622b014, 
+    0x4df0e8bd, 0xbb32f000, 0x3ff00000, 0x41f0e92d, 0x460f4606, 0xfc6af000, 0x460d0004, 0x2001bf18, 
+    0xf0204328, 0xf1c04000, 0xf100607f, 0x0fc040e0, 0x1c30d00e, 0x2001bf18, 0xf0204338, 0xf1c04000, 
+    0xf100607f, 0x0fc040e0, 0x2001bf04, 0xfee5f7fd, 0x46294620, 0x81f0e8bd, 0x4200f021, 0x5260f1a2, 
+    0x1f80f5b2, 0x4300f001, 0xf1d2bf28, 0xd90b6c7f, 0x1c00ea5f, 0x02c2ea43, 0x7050eb42, 0x4770bf18, 
+    0xf020bf28, 0x47700001, 0x1f80f5b2, 0x4618bfbc, 0xea4f4770, 0xf51c0c41, 0xd2021f00, 0xf0014608, 
+    0xb570b860, 0xfb8cf000, 0x89000000, 0xbff6f7ff, 0x4000f04f, 0x0080f5a0, 0x00004770, 0xea91b510, 
+    0xbf480f03, 0x4300f083, 0x84e4f100, 0xeb711a84, 0xd2050c03, 0xeb431912, 0x1b00030c, 0x010ceb61, 
+    0xe124f8df, 0x5411ea4f, 0x5c13eba4, 0x0f43ea1e, 0xea9ebf18, 0xd0735f44, 0x030eea23, 0x0e20f1dc, 
+    0x5104ea21, 0x1380f443, 0xfa22d332, 0xeb10fe0c, 0xfa23000e, 0xeb41fe0c, 0xf1cc010e, 0xfa030e20, 
+    0xeb10fe0e, 0xf151000e, 0xf5b10100, 0xf1cc1f80, 0xd2320e20, 0x5104eb01, 0xf20efa12, 0x4010e8bd, 
+    0x4770bf58, 0xbf381c40, 0x0242ea5f, 0x4770bf18, 0xbf142800, 0x0001f020, 0x0100f141, 0x0341ea4f, 
+    0x1f00f513, 0x4770bf38, 0x41c0f1a1, 0xbb76f000, 0xeb432a01, 0xf1ac0203, 0xf1dc0c20, 0xbf320e1f, 
+    0x0e00f04f, 0xf30cfa23, 0x0003eb10, 0x5104eb41, 0x5f11ebb4, 0xeba1d0d0, 0xf5015104, 0x08491180, 
+    0x0030ea5f, 0x5104eb01, 0xf150d30e, 0xbf380000, 0xfe0efa12, 0xe8bdd108, 0xe7c94010, 0xbf381c40, 
+    0x0242ea5f, 0xe7c3d1ca, 0x4010e8bd, 0x0341ea4f, 0x1f00f513, 0x4770bf38, 0x41c0f1a1, 0xbb3ef000, 
+    0x5f44ea9e, 0xea11d008, 0xe8bd0f5e, 0xbf044010, 0x4100f001, 0x47702000, 0x4010e8bd, 0xf000b570, 
+    0xbf00fadf, 0x3ebefb64, 0xffe00000, 0xf04f4902, 0xf0010000, 0xbf00b820, 0x7ff80000, 0xbf581049, 
+    0x4140f1c1, 0xbf58105b, 0x4340f1c3, 0xf3ef428b, 0x47708000, 0x41c0e92d, 0xf8dfb430, 0xea3cc2a0, 
+    0xbf181411, 0x1413ea3c, 0x80ecf000, 0x0503ea81, 0x1411ea1c, 0x74d5ea44, 0xea1cbf18, 0xf0001513, 
+    0xeba480c7, 0xf04f0405, 0xea454500, 0xea4521c1, 0xea4123c3, 0xea435150, 0xf1045352, 0x4299747f, 
+    0x3400f504, 0x20c0ea4f, 0x22c2ea4f, 0x4290bf08, 0x809cf000, 0x6513ea4f, 0x1640f20f, 0xea4f5d76, 
+    0xfb064513, 0xf1c7f705, 0xfb067780, 0xea4ff707, 0xfba737d7, 0x42766803, 0x3880f5c8, 0xce06fba7, 
+    0xf1a8bf38, 0xfb070801, 0xf04fe608, 0xfba60e00, 0xfbe68c02, 0xf1dcce03, 0xf1ce0c00, 0xbf384e00, 
+    0x0e01f1ae, 0x580cfba6, 0x0700f04f, 0x0500f04f, 0x870efbe6, 0xc608fba1, 0xce07fba0, 0x060eeb16, 
+    0x0500f145, 0x6507fbe1, 0x4ee0f115, 0xf5a4bf7e, 0xea5f3480, 0x416d0646, 0x0780f116, 0x0500f145, 
+    0x2717ea4f, 0x6606ea4f, 0x6705ea47, 0x46def1a6, 0x5f80f1b6, 0x2515ea4f, 0x4638d91f, 0x0c01f024, 
+    0x71c4eb05, 0x6ffef1bc, 0x110ceb01, 0xbcf0d802, 0x8100e8bd, 0xbf5c4224, 0x1e80f501, 0x7fc4ea9e, 
+    0xbcf0d402, 0x8100e8bd, 0xd4384224, 0xf1a1bcf0, 0xe8bd41c0, 0xf0004100, 0xea4fba71, 0xea4222d2, 
+    0xea4f5243, 0xfba723d3, 0xea4f8602, 0xea4020d0, 0xfb075041, 0xea1e6603, 0xea4f0f0e, 0xfb0521d1, 
+    0xbf586602, 0x5600eba6, 0x5600ebb6, 0x0e52ea4f, 0x7ec3ea4e, 0x0e0eeb18, 0x0e53eb56, 0xeb18d5bd, 
+    0x415e0802, 0xf1551c7f, 0xe7b60500, 0x1580f44f, 0x0700f04f, 0x0600f04f, 0x0800f04f, 0xbcf0e7ad, 
+    0x0000f04f, 0x41c0f101, 0x4100f001, 0x8100e8bd, 0x1f0cea11, 0x1513ea0c, 0xe00cd000, 0x1f0cea13, 
+    0x8025f000, 0x0000f04f, 0xea81bcf0, 0xf0010103, 0xe8bd4100, 0xbcf08100, 0x4100e8bd, 0x0103ea81, 
+    0xba1cf000, 0xe8bdbcf0, 0xb5704100, 0xf9c8f000, 0x3efc7e09, 0xb807f000, 0x0103ea81, 0x0000f04f, 
+    0x4100f001, 0xea814770, 0xf0000103, 0xbcf0ba07, 0x4100e8bd, 0x0000f04f, 0x47704921, 0xf9fbfdff, 
+    0xf2f4f5f7, 0xebedeef0, 0xe4e6e8e9, 0xdee0e1e3, 0xd8dadbdd, 0xd3d4d5d7, 0xcdcfd0d1, 0xc8cacbcc, 
+    0xc4c5c6c7, 0xbfc0c1c2, 0xbbbcbdbe, 0xb7b8b9ba, 0xb3b4b5b6, 0xafb0b1b2, 0xabacadae, 0xa8a8a9aa, 
+    0xa4a5a6a7, 0xa1a2a3a3, 0x9e9f9fa0, 0x9b9c9c9d, 0x9899999a, 0x95969797, 0x93939495, 0x90919192, 
+    0x8e8e8f8f, 0x8b8c8c8d, 0x89898a8b, 0x87878888, 0x84858586, 0x82838384, 0x80818182, 0x07ff0000, 
+    0x7ff80000, 0x0341ea4f, 0x5353ea4f, 0x6380f5a3, 0x031ef1d3, 0xf1d3bfc8, 0xdd0c0c21, 0x4200f04f, 
+    0x22c1ea42, 0x5250ea42, 0xfc03fa32, 0x7ce1ea8c, 0x70e1ebac, 0x2b104770, 0x2000bfc4, 0xf5034770, 
+    0xf1bc7c78, 0xd0043fff, 0x4200f06f, 0x0021ea82, 0xb5704770, 0xf944f000, 0x80249249, 0x47702000, 
+    0x0000e7f2, 0x5311ea4f, 0x6380f5a3, 0x031ef1d3, 0xf1d3bfa8, 0xdb080c20, 0x4200f04f, 0x22c1ea42, 
+    0x5250ea52, 0xf003fa32, 0x42094770, 0x2b10d40b, 0x2000bfc4, 0xf5034770, 0xf1bc7c78, 0xd0053fff, 
+    0x30fff04f, 0xf04f4770, 0x47700000, 0xf000b570, 0xbf00f917, 0x80249249, 0x47702000, 0xf010e7f0, 
+    0xbf484200, 0xfab04240, 0xfa10f380, 0xd00af103, 0x031df1c3, 0x6380f503, 0x5041ea4f, 0x5203eb02, 
+    0x21d1eb02, 0xf04f4770, 0x47700000, 0xf380fab0, 0xf103fa10, 0xf1c3d00a, 0xf503031d, 0xea4f6380, 
+    0xea4f5041, 0xeb025203, 0x477021d1, 0x0000f04f, 0x00004770, 0x0c03ea51, 0xf51cd417, 0xbf581f80, 
+    0x1f80f5bc, 0x8006f100, 0xbf184299, 0xbf084770, 0x47704290, 0xf511d707, 0xbf581f80, 0x1f80f513, 
+    0x4299d419, 0x42894770, 0xf51c4770, 0xd5081f80, 0x1f80f5bc, 0x428bd5f7, 0x4770bf18, 0x4282bf08, 
+    0xf44f4770, 0xeb1c1c00, 0xbf380f41, 0x0f43eb1c, 0x428bd201, 0xb5704770, 0xf8b2f000, 0x00492492, 
+    0x5100f04f, 0x5380f04f, 0xbdd8f7ff, 0xc148f8df, 0xea1cb570, 0xbf1e1e11, 0x1513ea1c, 0x0f0cea9e, 
+    0x0f0cea95, 0x806ff000, 0x0403ea81, 0x134cea23, 0x7ed4ea4e, 0x114cea21, 0x1180f441, 0x1380f443, 
+    0xfba144ae, 0xfba04c02, 0xf1ae6503, 0x19367e7f, 0x050ceb55, 0x4c03fba1, 0x0300f14c, 0x1c02fba0, 
+    0x060ceb16, 0xf1534165, 0x42090300, 0xf046bf18, 0xf4130601, 0xd10b7f00, 0x3103ea4f, 0x3005ea4f, 
+    0xea410334, 0xea405115, 0xf06f5016, 0xe00a0203, 0x21c3ea4f, 0x20c5ea4f, 0xea4102f4, 0xea405155, 
+    0xf06f5056, 0xeb020202, 0xeb01422e, 0xea855502, 0xd00a71ce, 0x0c44ea5f, 0xf024bf18, 0xf1504400, 
+    0xf1410000, 0xea200100, 0xf24070d4, 0x45627cfe, 0xbd70d200, 0xbf1442a8, 0x4480f04f, 0x4440f04f, 
+    0xbf082e00, 0xf1be2400, 0xbfa86f80, 0x41c0f1a1, 0x4070e8bd, 0x8082f280, 0x0000f04f, 0x41c0f101, 
+    0x4100f001, 0xea9e4770, 0xea0c0f0c, 0xbf181513, 0x0f0cea95, 0xf04fd006, 0xea810000, 0xf00e0e03, 
+    0xbd704100, 0xf81cf000, 0x3e010089, 0xb807f000, 0xb809f000, 0x0c43ea4f, 0x5c5cea5f, 0xea81d008, 
+    0xf0000103, 0xea4fb85b, 0xea5f0c41, 0xd1f65c5c, 0x0000f04f, 0x47704901, 0x07ff0000, 0x7ff80000, 
+    0x0e02f10e, 0x0e03f02e, 0x6b04f85e, 0xd4054236, 0xeb432a01, 0xf5150503, 0xd8121f00, 0xeb412801, 
+    0xf51c0c01, 0xd80c1f00, 0xea4fd10e, 0xf5157cd1, 0xeb0c1f00, 0xf10c0c4c, 0xbf080c02, 0x7cd3eb4c, 
+    0xf04fe004, 0xe0010c08, 0x7cd3ea4f, 0x054ceb0c, 0xf605fa26, 0x0607f006, 0x0c04f1b6, 0xeb0ed206, 
+    0xe8bd0c86, 0xf04c4070, 0x47600c01, 0xf00ce8df, 0x02020b09, 0x4100f04f, 0x0000f04f, 0x2100f5a1, 
+    0x4619bd70, 0x28014610, 0x0401eb51, 0xf5d4bf18, 0xbf841400, 0xf0012000, 0xbd704100, 0xf5a00808, 
+    0xea4f1100, 0x47700131, 0x0c01ea53, 0xf51cd417, 0xbf581f80, 0x1f80f5bc, 0x8006f100, 0xbf18428b, 
+    0xbf084770, 0x47704282, 0xf513d707, 0xbf581f80, 0x1f80f511, 0x428bd419, 0x429b4770, 0xf51c4770, 
+    0xd5081f80, 0x1f80f5bc, 0x4299d5f7, 0x4770bf18, 0x4290bf08, 0xf44f4770, 0xeb1c1c00, 0xbf380f43, 
+    0x0f41eb1c, 0x4299d201, 0xb40f4770, 0xbc03bc0c, 0xbec1f7ff, 0x0f03ea91, 0xf081b510, 0xf53f4100, 
+    0xf083abf5, 0xf0004300, 0x0000b8d5, 0x41f0e92d, 0x1c80f501, 0x1f00f5bc, 0x80a9f2c0, 0x5c11ea4f, 
+    0x510cea21, 0x0cfdf10c, 0x1180f441, 0x0c5cea5f, 0x7cc0f50c, 0x0040d301, 0xa4304149, 0xea410289, 
+    0x02875190, 0x0c0a0e8e, 0xfb045da4, 0xfb02f604, 0xf1c6f606, 0xfba44640, 0x0df66206, 0x2642ea46, 
+    0xf406fb06, 0x2301fba4, 0xf1c34252, 0xbf384340, 0xfba61e5b, 0x24004202, 0x2403fbe6, 0xea420bd2, 
+    0xfba64644, 0xfba12306, 0xfba3e202, 0xfbe3e407, 0x42644261, 0x4e40f1c2, 0xf1aebf38, 0xfba60e01, 
+    0xf04f2304, 0xfbe60200, 0xfba2320e, 0x00344603, 0x6462fbe2, 0xe606fba1, 0xe807fba4, 0x6861fbe4, 
+    0xf1c84276, 0xbf385840, 0x0801f1a8, 0xe406fba2, 0xe508fba3, 0x5468fbe2, 0xe605fba1, 0xe804fba7, 
+    0x8664fbe1, 0x0520f118, 0x0600f156, 0xf1a809a8, 0x09b1081b, 0x083ff008, 0x0f0af1b8, 0x6086ea40, 
+    0xeb01d91c, 0xe8bd510c, 0xbf0081f0, 0xe8eef5fc, 0xd3d8dde2, 0xc3c7cbcf, 0xb6b9bdc0, 0xacaeb1b4, 
+    0xa3a5a7a9, 0x9b9d9fa1, 0x9596989a, 0x8f909293, 0x898b8c8d, 0x85868788, 0x81828384, 0x6800fba0, 
+    0xf201fb00, 0x0842eb08, 0x2887ebb8, 0x1834d507, 0x0401eb58, 0x1c40d5d5, 0x0100f151, 0x1a34e7d1, 
+    0x0401eb78, 0x1e40d4cd, 0x0100f171, 0xea5fe7c9, 0xea5f0c4c, 0xd10d5c9c, 0xf04fd305, 0xf0010000, 
+    0xe8bd4100, 0xe8bd81f0, 0xb57041f0, 0xfea8f7ff, 0xbeffdb6d, 0x41f0e8bd, 0x0000f04f, 0x47704900, 
+    0x7ff80000, 0xea91b510, 0xbf480f03, 0x4300f083, 0xab1cf53f, 0xeb711a84, 0xd2070c03, 0xf08c1912, 
+    0xeb434c00, 0x1b00030c, 0x010ceb61, 0xe1a4f8df, 0x5411ea4f, 0x5c13eba4, 0x0f43ea1e, 0xea9ebf18, 
+    0xf0005f44, 0xea2380b0, 0x4252036e, 0x5104ea21, 0x036eebc3, 0x1e5bbf38, 0x0e20f1dc, 0xfa22d325, 
+    0xeb10fe0c, 0xfa43000e, 0xeb41fe0c, 0xf1cc010e, 0xfa030e20, 0xeb10fe0e, 0xf151000e, 0xf1cc0100, 
+    0xd4290e20, 0xf20efa12, 0x5104eb01, 0x4010e8bd, 0x4770bf58, 0xbf1c1c40, 0x4f00f1b2, 0x28004770, 
+    0x1c49bf0c, 0x0001f020, 0xeb124770, 0xeb430e02, 0xbf180203, 0x0e01f04f, 0x0242ea4e, 0x0c20f1ac, 
+    0x0e1ef1dc, 0xfa43d954, 0xeb10fe0c, 0xf151000e, 0xf1cc31ff, 0xd5d50e1e, 0x0e01f10e, 0xfe0efa12, 
+    0xeb414140, 0xeb010101, 0xea5f5c44, 0xd9105c5c, 0x70deeb10, 0x5104eb01, 0xf1bebf38, 0xe8bd4f00, 
+    0xbf184010, 0x28004770, 0x1c49bf0c, 0x0001f020, 0xd2304770, 0x2cd4ea4f, 0x1100f511, 0x6400f424, 
+    0xfab1d01b, 0x3a0bf281, 0x1ea41aa4, 0x0320f1d2, 0xfa304091, 0x4319f303, 0xeb014090, 0x2c0071cc, 
+    0x5104eb01, 0x4010e8bd, 0x4770bfa8, 0x41c0f101, 0x0000f04f, 0x4100f001, 0xfab04770, 0xfa10f380, 
+    0xd100f103, 0x1ae4bd10, 0x05483c17, 0xe7e40ac9, 0x5104eb01, 0x1049bd10, 0x5104eb01, 0x4010e8bd, 
+    0x0030ea4f, 0xf04fe002, 0x47700100, 0xbf08004a, 0xd0f84200, 0x1f00f5b2, 0x4770bf28, 0x4100f001, 
+    0x0000f04f, 0xea9e4770, 0xd0075f44, 0x0f5eea11, 0x4010e8bd, 0x2100bf04, 0x47702000, 0x4010e8bd, 
+    0xf7ffb570, 0xbf00fdbd, 0x3ef6df40, 0x4100f083, 0x47704610, 0xffe00000, 0xea4f0043, 0xea4f0cd3, 
+    0x40430c3c, 0x0740bf1f, 0x5160f10c, 0x4ffef013, 0xf01c4770, 0xd1036f00, 0xf00c2000, 0x47704100, 
+    0x4300f00c, 0x7050ea43, 0xea40b510, 0xf00000cc, 0xbf00fa22, 0x92000000, 0x0100ea4f, 0xbddef7ff, 
+    0x4100f04f, 0x0000f04f, 0x2100f5a1, 0x00004770, 0x0f01ea90, 0xf081bf48, 0xf1004100, 0x1a42825e, 
+    0x1a80bf3c, 0xea4f1889, 0xf04f52d0, 0xea1c4c7f, 0xeba20f41, 0xbf1853d1, 0x6f02ea9c, 0x803bf000, 
+    0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 0xfc03fa21, 0x0c0ceb10, 0xf102d21e, 0xea5f32ff, 0xeb40201c, 
+    0xbf3850c2, 0xf01c4770, 0xea4f0f7f, 0xbf180c40, 0x4f7ff1bc, 0x4770bf38, 0x0320f1c3, 0xbf084099, 
+    0x0001f020, 0x4f7ff1bc, 0x4770bf38, 0x40c0f1a0, 0xba17f000, 0x003cea4f, 0xeb400a00, 0xbf2850c2, 
+    0x0ffff01c, 0x0c40ea4f, 0xbf18d0e6, 0x4f7ff1bc, 0x4770bf38, 0xea9ce7ea, 0xd0056f02, 0x0f5cea10, 
+    0xf000bf08, 0x47704000, 0xf000b510, 0xbf00f9b4, 0x3ebefb64, 0xf0004801, 0xbf00ba6e, 0x7fc00000, 
+    0x0c7ff44f, 0x12d0ea1c, 0xea1cbf1e, 0xea9213d1, 0xea930f0c, 0xf0000f0c, 0xea908085, 0xbf480f01, 
+    0x7280f442, 0x0c00f440, 0x0000f441, 0x417ff02c, 0x407ff020, 0x4281b500, 0x0203eba2, 0x1c08f20f, 
+    0x4e50ebac, 0x0000f1c0, 0xe000f89e, 0x0e4eea4f, 0xfc0efb00, 0x0049bf38, 0x1c2cea4f, 0x02faf502, 
+    0xf30efb0c, 0x1eceea4f, 0x2c11ea4f, 0x21c1ea4f, 0x5e63eb0e, 0x4222eb42, 0xfc0cfb0e, 0x531cea4f, 
+    0x1103fb00, 0x2c11ea4f, 0x3101ea4f, 0xfc0cfb0e, 0x4cdcea4f, 0x110cfb00, 0xbf2842c1, 0xeb4c1809, 
+    0xf85d3303, 0xeb10eb04, 0xeb430141, 0xf5b250c2, 0xbf380f7c, 0xd5294770, 0x0ff0f012, 0xf100bf1c, 
+    0xf00040c0, 0x47704000, 0x83828100, 0x87868584, 0x8c8b8988, 0x918f8e8d, 0x96959392, 0x9c9a9997, 
+    0xa2a09f9d, 0xa8a7a5a3, 0xb0aeacaa, 0xb7b5b3b2, 0xc0bebcb9, 0xc9c7c5c2, 0xd4d1cecc, 0xdfdcd9d7, 
+    0xece9e6e2, 0xfaf7f3f0, 0x000000fe, 0x0c40ea4f, 0x7c80f10c, 0x4f7ef1bc, 0x4770bf28, 0x40c0f1b0, 
+    0xb95ff000, 0x0f01ea90, 0x13d1ea0c, 0xf442bf48, 0x45627280, 0x4563bf38, 0xf413d207, 0xd0160f7f, 
+    0x0001ea80, 0x4000f000, 0xb5104770, 0xf903f000, 0x3efc7e09, 0xb805f000, 0x0001ea80, 0x4000f000, 
+    0xea804770, 0xf0000001, 0xf0004000, 0xf412b93a, 0xbf040f7f, 0x47704802, 0x0001ea80, 0xb931f000, 
+    0x7fc00000, 0x0e0b0041, 0x029ef1d3, 0xf450d908, 0xea4f0300, 0xfa232303, 0xbf48f002, 0x47704240, 
+    0xf000b510, 0xbf00f8d8, 0x80249249, 0x47702000, 0x4200f06f, 0x0020ea82, 0x00004770, 0xf1d10dc1, 
+    0xdb06029e, 0x2300ea4f, 0x4300f043, 0xf002fa23, 0x42004770, 0xea4fd507, 0xf1b10140, 0xd2024ffe, 
+    0x0000f04f, 0xb5104770, 0xf8b5f000, 0x80249249, 0x47702000, 0x0020ea6f, 0x00004770, 0x4100f010, 
+    0x4240bf48, 0xf380fab0, 0xf203fa10, 0x039df1c3, 0xea51d00b, 0xeb0151c3, 0x06532012, 0x4770bf38, 
+    0x0001f100, 0xf020bf08, 0x47700001, 0xf380fab0, 0xf203fa10, 0x039df1c3, 0x05d9d00a, 0x2012eb01, 
+    0xbf380653, 0xf1004770, 0xbf080001, 0x0001f020, 0x00004770, 0x0c7ff44f, 0x12d0ea1c, 0xea1cbf1e, 
+    0xea9213d1, 0xea930f0c, 0xf0000f0c, 0xea908047, 0xbf480f01, 0x7280f442, 0x4c00f04f, 0x2000ea4c, 
+    0x2101ea4c, 0x0203eb02, 0x1301fba0, 0x0200f5a2, 0xbf182900, 0x0301f043, 0xbf28005b, 0x0333ea4f, 
+    0x4222eb42, 0x2c13ea5f, 0x50c2eb4c, 0xebbcbf2e, 0xf5b26f43, 0x47700f7c, 0x6c03ea4f, 0x4f00f1bc, 
+    0xf020bf08, 0xf5b20001, 0xbf380f7c, 0xd50b4770, 0x02fff082, 0x3f80f512, 0x4770bfc8, 0x40c0f100, 
+    0xf000bfd8, 0x47704000, 0x0c00f500, 0x0c4cea5f, 0x4770bf48, 0x40c0f1b0, 0xb873f000, 0x0f01ea90, 
+    0x13d1ea0c, 0xf442bf48, 0x45627280, 0x4563bf38, 0xea80d204, 0xf0000001, 0x47704000, 0xf000b510, 
+    0xbf00f81a, 0x3e010089, 0xb807f000, 0xb809f000, 0x0c41ea5f, 0x6c1cea5f, 0xea80d008, 0xf0000001, 
+    0xea5fb850, 0xea5f0c40, 0xd1f66c1c, 0x4000f04f, 0x0080f5a0, 0xf10e4770, 0xf02e0e02, 0xf85e0e03, 
+    0x42244b04, 0xea4fd404, 0xf1b20241, 0xd8114f7f, 0x0340ea4f, 0x4f7ff1b3, 0xd10ed80c, 0x7cd0ea4f, 
+    0x4f7ff1b2, 0x0c4ceb0c, 0x0c02f10c, 0xeb4cbf08, 0xe0047cd1, 0x0c08f04f, 0xea4fe001, 0xeb0c7cd1, 
+    0xfa24034c, 0xf004f403, 0xf1b40407, 0xd2060c04, 0x0c84eb0e, 0x4010e8bd, 0x0c01f04c, 0xe8df4760, 
+    0x0807f00c, 0xf04f0202, 0xf5a04000, 0xbd100080, 0x00424608, 0xf1d2bf18, 0xbf887280, 0x4000f000, 
+    0x21ffbd10, 0x50d0ea41, 0x477005c0, 0x0f01ea90, 0xf081bf48, 0xf53f4100, 0x1a42ada2, 0xf082d804, 
+    0xeba04200, 0x44110002, 0x52d0ea4f, 0x4c7ff04f, 0x0f41ea1c, 0x53d1eba2, 0xea9cbf18, 0xd04a6f02, 
+    0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 0xfc03fa21, 0x0c0cebb0, 0xf012d40f, 0xd0360ffe, 0x004cea5f, 
+    0x1200d51d, 0x50c2eb40, 0x4770bf38, 0x0f3ff01c, 0x4770bf18, 0xf1a2e00b, 0xea5f0201, 0xeb40201c, 
+    0xbf3850c2, 0xf01c4770, 0xbf180f7f, 0xf1c34770, 0x40990320, 0x1e40bf14, 0x0001f020, 0x08804770, 
+    0x2312ea4f, 0x4770bf08, 0xfc80fab0, 0x020ceba2, 0x0c28f1cc, 0xf00cfa60, 0x2f12ea93, 0xeb00bf04, 
+    0x477050c2, 0x70c3ea4f, 0x0a134770, 0x10dcea5f, 0x4770bf08, 0xea9ce7f6, 0xd0046f02, 0x0f5cea10, 
+    0x2000bf08, 0xb5104770, 0xff45f7ff, 0x3ef6df40, 0x4000f081, 0xf00c4770, 0x2b09030f, 0x2008bf08, 
+    0x807ff000, 0xd00b2b0a, 0xbf182b08, 0xbf084770, 0x0f40f01c, 0xf04fd00a, 0xf04f0000, 0x47700100, 
+    0x0f40f01c, 0xf04fbf18, 0x47704000, 0x0f10f01c, 0xf020d008, 0xf0004370, 0xea42427f, 0xea4f01d3, 
+    0x47707043, 0x4060f000, 0x427ff021, 0x0200ea42, 0x407ff001, 0x7072ea40, 0xf04f4770, 0xf44c0cff, 
+    0xea1c6ce0, 0xbf1c5311, 0x0c03ea9c, 0xbfc24594, 0xeb0142da, 0x47705102, 0xd00d2b00, 0x0f00f1bc, 
+    0x2a00d00f, 0x4100f001, 0xf041bfa4, 0xf04141e0, 0xf04f617f, 0x47700000, 0x4100f001, 0x0000f04f, 
+    0xea504770, 0xf04f3301, 0xbf180c9b, 0x6c80f04c, 0xaf7cf47e, 0xf04f4770, 0xea1202ff, 0xbf1c52d0, 
+    0x03fff092, 0xbfc2428b, 0xeb0042d1, 0x477050c1, 0xd00a2a00, 0xd00b2b00, 0xf0002900, 0xbfa44000, 
+    0x40fef040, 0x0000f440, 0xf0004770, 0x47704000, 0xf04f0243, 0xbf180c0b, 0x6c80f04c, 0xad0af47f, 
+    0xf41c4770, 0xd0111f80, 0x2fe0f41c, 0xea6fd003, 0x004931cc, 0xf04f4770, 0xf3ef5040, 0xf0228200, 
+    0xea424270, 0xf3820200, 0x47708800, 0x0000f04f, 0xfb904770, 0xfb02f2f1, 0x46100111, 0xfbb04770, 
+    0xfb02f2f1, 0x46100111, 0x02004770, 0x03010604, 0x00160011, 0x0020001b, 0x002a0025, 0x0034002f, 
+    0x003c0039, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xf2035190, 0xf2035192, 0xf2035194, 
+    0xf2035196, 0x00030008, 0x00030003, 0x00040004, 0x00000008, 0x00100034, 0x00100010, 0x001f001f, 
+    0x00000034, 0x00080020, 0x00080008, 0x00100010, 0x00000020, 0x00010004, 0x00030001, 0x00040003, 
+    0x00000004, 0x0006001c, 0x00080006, 0x0014000b, 0x0000001c, 0x00040010, 0x00060004, 0x000c0008, 
+    0x00000010, 0xf2033070, 0xf2033270, 0xf2033470, 0xf2033670, 0x3f7ec56d, 0x3f700d1b, 0x3f7240b8, 
+    0x3f833333, 0x41c55c29, 0x41726666, 0x411c28f6, 0xc03f5c29, 0x3f7a8588, 0x3f6cb296, 0x3f6de69b, 
+    0x3f822d0e, 0xc39030a4, 0xc39eb99a, 0xc390651f, 0xc39cd852, 0x00000000, 0x00000000, 0x3ff00000, 
+    0x00000000, 0x3ff80000, 0x00000000, 0x00000000, 0x40000000, 0x3fe2b803, 0x00000000, 0x00000000, 
+    0x43cfd006, 0x3e4cfdeb, 0x33333303, 0x3fe33333, 0xdb6fabff, 0x3fdb6db6, 0x518f264d, 0x3fd55555, 
+    0xa91d4101, 0x3fd17460, 0x93c9db65, 0x3fcd864a, 0x4a454eef, 0x3fca7e28, 0x5555553e, 0x3fc55555, 
+    0x16bebd93, 0xbf66c16c, 0xaf25de2c, 0x3f11566a, 0xc5d26bf1, 0xbebbbd41, 0x72bea4d0, 0x3e663769, 
+    0x00000000, 0x00000000, 0xc0c10000, 0x0140c181, 0x03c0c301, 0xc2410280, 0x06c0c601, 0xc7410780, 
+    0xc5c10500, 0x0440c481, 0x0cc0cc01, 0xcd410d80, 0xcfc10f00, 0x0e40ce81, 0xcac10a00, 0x0b40cb81, 
+    0x09c0c901, 0xc8410880, 0x18c0d801, 0xd9411980, 0xdbc11b00, 0x1a40da81, 0xdec11e00, 0x1f40df81, 
+    0x1dc0dd01, 0xdc411c80, 0xd4c11400, 0x1540d581, 0x17c0d701, 0xd6411680, 0x12c0d201, 0xd3411380, 
+    0xd1c11100, 0x1040d081, 0x30c0f001, 0xf1413180, 0xf3c13300, 0x3240f281, 0xf6c13600, 0x3740f781, 
+    0x35c0f501, 0xf4413480, 0xfcc13c00, 0x3d40fd81, 0x3fc0ff01, 0xfe413e80, 0x3ac0fa01, 0xfb413b80, 
+    0xf9c13900, 0x3840f881, 0xe8c12800, 0x2940e981, 0x2bc0eb01, 0xea412a80, 0x2ec0ee01, 0xef412f80, 
+    0xedc12d00, 0x2c40ec81, 0x24c0e401, 0xe5412580, 0xe7c12700, 0x2640e681, 0xe2c12200, 0x2340e381, 
+    0x21c0e101, 0xe0412080, 0x60c0a001, 0xa1416180, 0xa3c16300, 0x6240a281, 0xa6c16600, 0x6740a781, 
+    0x65c0a501, 0xa4416480, 0xacc16c00, 0x6d40ad81, 0x6fc0af01, 0xae416e80, 0x6ac0aa01, 0xab416b80, 
+    0xa9c16900, 0x6840a881, 0xb8c17800, 0x7940b981, 0x7bc0bb01, 0xba417a80, 0x7ec0be01, 0xbf417f80, 
+    0xbdc17d00, 0x7c40bc81, 0x74c0b401, 0xb5417580, 0xb7c17700, 0x7640b681, 0xb2c17200, 0x7340b381, 
+    0x71c0b101, 0xb0417080, 0x90c15000, 0x51409181, 0x53c09301, 0x92415280, 0x56c09601, 0x97415780, 
+    0x95c15500, 0x54409481, 0x5cc09c01, 0x9d415d80, 0x9fc15f00, 0x5e409e81, 0x9ac15a00, 0x5b409b81, 
+    0x59c09901, 0x98415880, 0x48c08801, 0x89414980, 0x8bc14b00, 0x4a408a81, 0x8ec14e00, 0x4f408f81, 
+    0x4dc08d01, 0x8c414c80, 0x84c14400, 0x45408581, 0x47c08701, 0x86414680, 0x42c08201, 0x83414380, 
+    0x81c14100, 0x40408081, 0x0002ca38, 0x00040000, 0x00001210, 0x000005e8, 0x0002d3ec, 0x00057f70, 
+    0x00000018, 0x00000644, 0x0002d404, 0x00057ff0, 0x00000010, 0x00000644, 0x0002d3ec, 0x00041210, 
+    0x0000c6a4, 0x00000660, 0x0002d3ec, 0x0004d8b4, 0x00000060, 0x00000660, 0x0002d3ec, 0x00057800, 
+    0x00000490, 0x00000660, 0x00007fff, 0xf3747f62, 0xe7077d8a, 0xdad87a7d, 0xcf047642, 0xc3a970e3, 
+    0xb8e36a6e, 0xaecc62f2, 0xa57e5a82, 0x9d0e5134, 0x9592471d, 0x8f1d3c57, 0x89be30fc, 0x85832528, 
+    0x827618f9, 0x809e0c8c, 0x80000000, 0x809ef374, 0x8276e707, 0x8583dad8, 0x89becf04, 0x8f1dc3a9, 
+    0x9592b8e3, 0x9d0eaecc, 0xa57ea57e, 0xaecc9d0e, 0xb8e39592, 0xc3a98f1d, 0xcf0489be, 0xdad88583, 
+    0xe7078276, 0xf374809e, 0x00008000, 0x0c8c809e, 0x18f98276, 0x25288583, 0x30fc89be, 0x3c578f1d, 
+    0x471d9592, 0x51349d0e, 0x5a82a57e, 0x62f2aecc, 0x6a6eb8e3, 0x70e3c3a9, 0x7642cf04, 0x7a7ddad8, 
+    0x7d8ae707, 0x7f62f374, 0x7fff0000, 0x7f620c8c, 0x7d8a18f9, 0x7a7d2528, 0x764230fc, 0x70e33c57, 
+    0x6a6e471d, 0x62f25134, 0x5a825a82, 0x513462f2, 0x471d6a6e, 0x3c5770e3, 0x30fc7642, 0x25287a7d, 
+    0x18f97d8a, 0x0c8c7f62, 0x00007fff, 0xf9b87fd9, 0xf3747f62, 0xed387e9d, 0xe7077d8a, 0xe0e67c2a, 
+    0xdad87a7d, 0xd4e17885, 0xcf047642, 0xc94673b6, 0xc3a970e3, 0xbe326dca, 0xb8e36a6e, 0xb3c066d0, 
+    0xaecc62f2, 0xaa0a5ed7, 0xa57e5a82, 0xa12955f6, 0x9d0e5134, 0x99304c40, 0x9592471d, 0x923641ce, 
+    0x8f1d3c57, 0x8c4a36ba, 0x89be30fc, 0x877b2b1f, 0x85832528, 0x83d61f1a, 0x827618f9, 0x816312c8, 
+    0x809e0c8c, 0x80270648, 0x80000000, 0x8027f9b8, 0x809ef374, 0x8163ed38, 0x8276e707, 0x83d6e0e6, 
+    0x8583dad8, 0x877bd4e1, 0x89becf04, 0x8c4ac946, 0x8f1dc3a9, 0x9236be32, 0x9592b8e3, 0x9930b3c0, 
+    0x9d0eaecc, 0xa129aa0a, 0xa57ea57e, 0xaa0aa129, 0xaecc9d0e, 0xb3c09930, 0xb8e39592, 0xbe329236, 
+    0xc3a98f1d, 0xc9468c4a, 0xcf0489be, 0xd4e1877b, 0xdad88583, 0xe0e683d6, 0xe7078276, 0xed388163, 
+    0xf374809e, 0xf9b88027, 0x00008000, 0x06488027, 0x0c8c809e, 0x12c88163, 0x18f98276, 0x1f1a83d6, 
+    0x25288583, 0x2b1f877b, 0x30fc89be, 0x36ba8c4a, 0x3c578f1d, 0x41ce9236, 0x471d9592, 0x4c409930, 
+    0x51349d0e, 0x55f6a129, 0x5a82a57e, 0x5ed7aa0a, 0x62f2aecc, 0x66d0b3c0, 0x6a6eb8e3, 0x6dcabe32, 
+    0x70e3c3a9, 0x73b6c946, 0x7642cf04, 0x7885d4e1, 0x7a7ddad8, 0x7c2ae0e6, 0x7d8ae707, 0x7e9ded38, 
+    0x7f62f374, 0x7fd9f9b8, 0x7fff0000, 0x7fd90648, 0x7f620c8c, 0x7e9d12c8, 0x7d8a18f9, 0x7c2a1f1a, 
+    0x7a7d2528, 0x78852b1f, 0x764230fc, 0x73b636ba, 0x70e33c57, 0x6dca41ce, 0x6a6e471d, 0x66d04c40, 
+    0x62f25134, 0x5ed755f6, 0x5a825a82, 0x55f65ed7, 0x513462f2, 0x4c4066d0, 0x471d6a6e, 0x41ce6dca, 
+    0x3c5770e3, 0x36ba73b6, 0x30fc7642, 0x2b1f7885, 0x25287a7d, 0x1f1a7c2a, 0x18f97d8a, 0x12c87e9d, 
+    0x0c8c7f62, 0x06487fd9, 0x00007fff, 0xfcdc7ff6, 0xf9b87fd9, 0xf6957fa7, 0xf3747f62, 0xf0557f0a, 
+    0xed387e9d, 0xea1e7e1e, 0xe7077d8a, 0xe3f47ce4, 0xe0e67c2a, 0xdddc7b5d, 0xdad87a7d, 0xd7d9798a, 
+    0xd4e17885, 0xd1ef776c, 0xcf047642, 0xcc217505, 0xc94673b6, 0xc6737255, 0xc3a970e3, 0xc0e96f5f, 
+    0xbe326dca, 0xbb856c24, 0xb8e36a6e, 0xb64c68a7, 0xb3c066d0, 0xb14064e9, 0xaecc62f2, 0xac6560ec, 
+    0xaa0a5ed7, 0xa7bd5cb4, 0xa57e5a82, 0xa34c5843, 0xa12955f6, 0x9f14539b, 0x9d0e5134, 0x9b174ec0, 
+    0x99304c40, 0x975949b4, 0x9592471d, 0x93dc447b, 0x923641ce, 0x90a13f17, 0x8f1d3c57, 0x8dab398d, 
+    0x8c4a36ba, 0x8afb33df, 0x89be30fc, 0x88942e11, 0x877b2b1f, 0x86762827, 0x85832528, 0x84a32224, 
+    0x83d61f1a, 0x831c1c0c, 0x827618f9, 0x81e215e2, 0x816312c8, 0x80f60fab, 0x809e0c8c, 0x8059096b, 
+    0x80270648, 0x800a0324, 0x80000000, 0x800afcdc, 0x8027f9b8, 0x8059f695, 0x809ef374, 0x80f6f055, 
+    0x8163ed38, 0x81e2ea1e, 0x8276e707, 0x831ce3f4, 0x83d6e0e6, 0x84a3dddc, 0x8583dad8, 0x8676d7d9, 
+    0x877bd4e1, 0x8894d1ef, 0x89becf04, 0x8afbcc21, 0x8c4ac946, 0x8dabc673, 0x8f1dc3a9, 0x90a1c0e9, 
+    0x9236be32, 0x93dcbb85, 0x9592b8e3, 0x9759b64c, 0x9930b3c0, 0x9b17b140, 0x9d0eaecc, 0x9f14ac65, 
+    0xa129aa0a, 0xa34ca7bd, 0xa57ea57e, 0xa7bda34c, 0xaa0aa129, 0xac659f14, 0xaecc9d0e, 0xb1409b17, 
+    0xb3c09930, 0xb64c9759, 0xb8e39592, 0xbb8593dc, 0xbe329236, 0xc0e990a1, 0xc3a98f1d, 0xc6738dab, 
+    0xc9468c4a, 0xcc218afb, 0xcf0489be, 0xd1ef8894, 0xd4e1877b, 0xd7d98676, 0xdad88583, 0xdddc84a3, 
+    0xe0e683d6, 0xe3f4831c, 0xe7078276, 0xea1e81e2, 0xed388163, 0xf05580f6, 0xf374809e, 0xf6958059, 
+    0xf9b88027, 0xfcdc800a, 0x00008000, 0x0324800a, 0x06488027, 0x096b8059, 0x0c8c809e, 0x0fab80f6, 
+    0x12c88163, 0x15e281e2, 0x18f98276, 0x1c0c831c, 0x1f1a83d6, 0x222484a3, 0x25288583, 0x28278676, 
+    0x2b1f877b, 0x2e118894, 0x30fc89be, 0x33df8afb, 0x36ba8c4a, 0x398d8dab, 0x3c578f1d, 0x3f1790a1, 
+    0x41ce9236, 0x447b93dc, 0x471d9592, 0x49b49759, 0x4c409930, 0x4ec09b17, 0x51349d0e, 0x539b9f14, 
+    0x55f6a129, 0x5843a34c, 0x5a82a57e, 0x5cb4a7bd, 0x5ed7aa0a, 0x60ecac65, 0x62f2aecc, 0x64e9b140, 
+    0x66d0b3c0, 0x68a7b64c, 0x6a6eb8e3, 0x6c24bb85, 0x6dcabe32, 0x6f5fc0e9, 0x70e3c3a9, 0x7255c673, 
+    0x73b6c946, 0x7505cc21, 0x7642cf04, 0x776cd1ef, 0x7885d4e1, 0x798ad7d9, 0x7a7ddad8, 0x7b5ddddc, 
+    0x7c2ae0e6, 0x7ce4e3f4, 0x7d8ae707, 0x7e1eea1e, 0x7e9ded38, 0x7f0af055, 0x7f62f374, 0x7fa7f695, 
+    0x7fd9f9b8, 0x7ff6fcdc, 0x7fff0000, 0x7ff60324, 0x7fd90648, 0x7fa7096b, 0x7f620c8c, 0x7f0a0fab, 
+    0x7e9d12c8, 0x7e1e15e2, 0x7d8a18f9, 0x7ce41c0c, 0x7c2a1f1a, 0x7b5d2224, 0x7a7d2528, 0x798a2827, 
+    0x78852b1f, 0x776c2e11, 0x764230fc, 0x750533df, 0x73b636ba, 0x7255398d, 0x70e33c57, 0x6f5f3f17, 
+    0x6dca41ce, 0x6c24447b, 0x6a6e471d, 0x68a749b4, 0x66d04c40, 0x64e94ec0, 0x62f25134, 0x60ec539b, 
+    0x5ed755f6, 0x5cb45843, 0x5a825a82, 0x58435cb4, 0x55f65ed7, 0x539b60ec, 0x513462f2, 0x4ec064e9, 
+    0x4c4066d0, 0x49b468a7, 0x471d6a6e, 0x447b6c24, 0x41ce6dca, 0x3f176f5f, 0x3c5770e3, 0x398d7255, 
+    0x36ba73b6, 0x33df7505, 0x30fc7642, 0x2e11776c, 0x2b1f7885, 0x2827798a, 0x25287a7d, 0x22247b5d, 
+    0x1f1a7c2a, 0x1c0c7ce4, 0x18f97d8a, 0x15e27e1e, 0x12c87e9d, 0x0fab7f0a, 0x0c8c7f62, 0x096b7fa7, 
+    0x06487fd9, 0x03247ff6, 0x00007fff, 0xfe6e7ffe, 0xfcdc7ff6, 0xfb4a7fea, 0xf9b87fd9, 0xf8277fc2, 
+    0xf6957fa7, 0xf5057f87, 0xf3747f62, 0xf1e47f38, 0xf0557f0a, 0xeec67ed6, 0xed387e9d, 0xebab7e60, 
+    0xea1e7e1e, 0xe8927dd6, 0xe7077d8a, 0xe57d7d3a, 0xe3f47ce4, 0xe26d7c89, 0xe0e67c2a, 0xdf617bc6, 
+    0xdddc7b5d, 0xdc597aef, 0xdad87a7d, 0xd9587a06, 0xd7d9798a, 0xd65c790a, 0xd4e17885, 0xd36777fb, 
+    0xd1ef776c, 0xd07976d9, 0xcf047642, 0xcd9275a6, 0xcc217505, 0xcab27460, 0xc94673b6, 0xc7db7308, 
+    0xc6737255, 0xc50d719e, 0xc3a970e3, 0xc2487023, 0xc0e96f5f, 0xbf8c6e97, 0xbe326dca, 0xbcda6cf9, 
+    0xbb856c24, 0xba336b4b, 0xb8e36a6e, 0xb796698c, 0xb64c68a7, 0xb50567bd, 0xb3c066d0, 0xb27f65de, 
+    0xb14064e9, 0xb00563ef, 0xaecc62f2, 0xad9761f1, 0xac6560ec, 0xab365fe4, 0xaa0a5ed7, 0xa8e25dc8, 
+    0xa7bd5cb4, 0xa69c5b9d, 0xa57e5a82, 0xa4635964, 0xa34c5843, 0xa238571e, 0xa12955f6, 0xa01c54ca, 
+    0x9f14539b, 0x9e0f5269, 0x9d0e5134, 0x9c114ffb, 0x9b174ec0, 0x9a224d81, 0x99304c40, 0x98434afb, 
+    0x975949b4, 0x9674486a, 0x9592471d, 0x94b545cd, 0x93dc447b, 0x93074326, 0x923641ce, 0x91694074, 
+    0x90a13f17, 0x8fdd3db8, 0x8f1d3c57, 0x8e623af3, 0x8dab398d, 0x8cf83825, 0x8c4a36ba, 0x8ba0354e, 
+    0x8afb33df, 0x8a5a326e, 0x89be30fc, 0x89272f87, 0x88942e11, 0x88052c99, 0x877b2b1f, 0x86f629a4, 
+    0x86762827, 0x85fa26a8, 0x85832528, 0x851123a7, 0x84a32224, 0x843a209f, 0x83d61f1a, 0x83771d93, 
+    0x831c1c0c, 0x82c61a83, 0x827618f9, 0x822a176e, 0x81e215e2, 0x81a01455, 0x816312c8, 0x812a113a, 
+    0x80f60fab, 0x80c80e1c, 0x809e0c8c, 0x80790afb, 0x8059096b, 0x803e07d9, 0x80270648, 0x801604b6, 
+    0x800a0324, 0x80020192, 0x80000000, 0x8002fe6e, 0x800afcdc, 0x8016fb4a, 0x8027f9b8, 0x803ef827, 
+    0x8059f695, 0x8079f505, 0x809ef374, 0x80c8f1e4, 0x80f6f055, 0x812aeec6, 0x8163ed38, 0x81a0ebab, 
+    0x81e2ea1e, 0x822ae892, 0x8276e707, 0x82c6e57d, 0x831ce3f4, 0x8377e26d, 0x83d6e0e6, 0x843adf61, 
+    0x84a3dddc, 0x8511dc59, 0x8583dad8, 0x85fad958, 0x8676d7d9, 0x86f6d65c, 0x877bd4e1, 0x8805d367, 
+    0x8894d1ef, 0x8927d079, 0x89becf04, 0x8a5acd92, 0x8afbcc21, 0x8ba0cab2, 0x8c4ac946, 0x8cf8c7db, 
+    0x8dabc673, 0x8e62c50d, 0x8f1dc3a9, 0x8fddc248, 0x90a1c0e9, 0x9169bf8c, 0x9236be32, 0x9307bcda, 
+    0x93dcbb85, 0x94b5ba33, 0x9592b8e3, 0x9674b796, 0x9759b64c, 0x9843b505, 0x9930b3c0, 0x9a22b27f, 
+    0x9b17b140, 0x9c11b005, 0x9d0eaecc, 0x9e0fad97, 0x9f14ac65, 0xa01cab36, 0xa129aa0a, 0xa238a8e2, 
+    0xa34ca7bd, 0xa463a69c, 0xa57ea57e, 0xa69ca463, 0xa7bda34c, 0xa8e2a238, 0xaa0aa129, 0xab36a01c, 
+    0xac659f14, 0xad979e0f, 0xaecc9d0e, 0xb0059c11, 0xb1409b17, 0xb27f9a22, 0xb3c09930, 0xb5059843, 
+    0xb64c9759, 0xb7969674, 0xb8e39592, 0xba3394b5, 0xbb8593dc, 0xbcda9307, 0xbe329236, 0xbf8c9169, 
+    0xc0e990a1, 0xc2488fdd, 0xc3a98f1d, 0xc50d8e62, 0xc6738dab, 0xc7db8cf8, 0xc9468c4a, 0xcab28ba0, 
+    0xcc218afb, 0xcd928a5a, 0xcf0489be, 0xd0798927, 0xd1ef8894, 0xd3678805, 0xd4e1877b, 0xd65c86f6, 
+    0xd7d98676, 0xd95885fa, 0xdad88583, 0xdc598511, 0xdddc84a3, 0xdf61843a, 0xe0e683d6, 0xe26d8377, 
+    0xe3f4831c, 0xe57d82c6, 0xe7078276, 0xe892822a, 0xea1e81e2, 0xebab81a0, 0xed388163, 0xeec6812a, 
+    0xf05580f6, 0xf1e480c8, 0xf374809e, 0xf5058079, 0xf6958059, 0xf827803e, 0xf9b88027, 0xfb4a8016, 
+    0xfcdc800a, 0xfe6e8002, 0x00008000, 0x01928002, 0x0324800a, 0x04b68016, 0x06488027, 0x07d9803e, 
+    0x096b8059, 0x0afb8079, 0x0c8c809e, 0x0e1c80c8, 0x0fab80f6, 0x113a812a, 0x12c88163, 0x145581a0, 
+    0x15e281e2, 0x176e822a, 0x18f98276, 0x1a8382c6, 0x1c0c831c, 0x1d938377, 0x1f1a83d6, 0x209f843a, 
+    0x222484a3, 0x23a78511, 0x25288583, 0x26a885fa, 0x28278676, 0x29a486f6, 0x2b1f877b, 0x2c998805, 
+    0x2e118894, 0x2f878927, 0x30fc89be, 0x326e8a5a, 0x33df8afb, 0x354e8ba0, 0x36ba8c4a, 0x38258cf8, 
+    0x398d8dab, 0x3af38e62, 0x3c578f1d, 0x3db88fdd, 0x3f1790a1, 0x40749169, 0x41ce9236, 0x43269307, 
+    0x447b93dc, 0x45cd94b5, 0x471d9592, 0x486a9674, 0x49b49759, 0x4afb9843, 0x4c409930, 0x4d819a22, 
+    0x4ec09b17, 0x4ffb9c11, 0x51349d0e, 0x52699e0f, 0x539b9f14, 0x54caa01c, 0x55f6a129, 0x571ea238, 
+    0x5843a34c, 0x5964a463, 0x5a82a57e, 0x5b9da69c, 0x5cb4a7bd, 0x5dc8a8e2, 0x5ed7aa0a, 0x5fe4ab36, 
+    0x60ecac65, 0x61f1ad97, 0x62f2aecc, 0x63efb005, 0x64e9b140, 0x65deb27f, 0x66d0b3c0, 0x67bdb505, 
+    0x68a7b64c, 0x698cb796, 0x6a6eb8e3, 0x6b4bba33, 0x6c24bb85, 0x6cf9bcda, 0x6dcabe32, 0x6e97bf8c, 
+    0x6f5fc0e9, 0x7023c248, 0x70e3c3a9, 0x719ec50d, 0x7255c673, 0x7308c7db, 0x73b6c946, 0x7460cab2, 
+    0x7505cc21, 0x75a6cd92, 0x7642cf04, 0x76d9d079, 0x776cd1ef, 0x77fbd367, 0x7885d4e1, 0x790ad65c, 
+    0x798ad7d9, 0x7a06d958, 0x7a7ddad8, 0x7aefdc59, 0x7b5ddddc, 0x7bc6df61, 0x7c2ae0e6, 0x7c89e26d, 
+    0x7ce4e3f4, 0x7d3ae57d, 0x7d8ae707, 0x7dd6e892, 0x7e1eea1e, 0x7e60ebab, 0x7e9ded38, 0x7ed6eec6, 
+    0x7f0af055, 0x7f38f1e4, 0x7f62f374, 0x7f87f505, 0x7fa7f695, 0x7fc2f827, 0x7fd9f9b8, 0x7feafb4a, 
+    0x7ff6fcdc, 0x7ffefe6e, 0x7fff0000, 0x7ffe0192, 0x7ff60324, 0x7fea04b6, 0x7fd90648, 0x7fc207d9, 
+    0x7fa7096b, 0x7f870afb, 0x7f620c8c, 0x7f380e1c, 0x7f0a0fab, 0x7ed6113a, 0x7e9d12c8, 0x7e601455, 
+    0x7e1e15e2, 0x7dd6176e, 0x7d8a18f9, 0x7d3a1a83, 0x7ce41c0c, 0x7c891d93, 0x7c2a1f1a, 0x7bc6209f, 
+    0x7b5d2224, 0x7aef23a7, 0x7a7d2528, 0x7a0626a8, 0x798a2827, 0x790a29a4, 0x78852b1f, 0x77fb2c99, 
+    0x776c2e11, 0x76d92f87, 0x764230fc, 0x75a6326e, 0x750533df, 0x7460354e, 0x73b636ba, 0x73083825, 
+    0x7255398d, 0x719e3af3, 0x70e33c57, 0x70233db8, 0x6f5f3f17, 0x6e974074, 0x6dca41ce, 0x6cf94326, 
+    0x6c24447b, 0x6b4b45cd, 0x6a6e471d, 0x698c486a, 0x68a749b4, 0x67bd4afb, 0x66d04c40, 0x65de4d81, 
+    0x64e94ec0, 0x63ef4ffb, 0x62f25134, 0x61f15269, 0x60ec539b, 0x5fe454ca, 0x5ed755f6, 0x5dc8571e, 
+    0x5cb45843, 0x5b9d5964, 0x5a825a82, 0x59645b9d, 0x58435cb4, 0x571e5dc8, 0x55f65ed7, 0x54ca5fe4, 
+    0x539b60ec, 0x526961f1, 0x513462f2, 0x4ffb63ef, 0x4ec064e9, 0x4d8165de, 0x4c4066d0, 0x4afb67bd, 
+    0x49b468a7, 0x486a698c, 0x471d6a6e, 0x45cd6b4b, 0x447b6c24, 0x43266cf9, 0x41ce6dca, 0x40746e97, 
+    0x3f176f5f, 0x3db87023, 0x3c5770e3, 0x3af3719e, 0x398d7255, 0x38257308, 0x36ba73b6, 0x354e7460, 
+    0x33df7505, 0x326e75a6, 0x30fc7642, 0x2f8776d9, 0x2e11776c, 0x2c9977fb, 0x2b1f7885, 0x29a4790a, 
+    0x2827798a, 0x26a87a06, 0x25287a7d, 0x23a77aef, 0x22247b5d, 0x209f7bc6, 0x1f1a7c2a, 0x1d937c89, 
+    0x1c0c7ce4, 0x1a837d3a, 0x18f97d8a, 0x176e7dd6, 0x15e27e1e, 0x14557e60, 0x12c87e9d, 0x113a7ed6, 
+    0x0fab7f0a, 0x0e1c7f38, 0x0c8c7f62, 0x0afb7f87, 0x096b7fa7, 0x07d97fc2, 0x06487fd9, 0x04b67fea, 
+    0x03247ff6, 0x01927ffe, 0x50102000, 0x68284808, 0x64244404, 0x74345414, 0x62224202, 0x72325212, 
+    0x6a2a4a0a, 0x7a3a5a1a, 0x61214101, 0x71315111, 0x69294909, 0x79395919, 0x65254505, 0x75355515, 
+    0x6d2d4d0d, 0x7d3d5d1d, 0x28081000, 0x34142404, 0x32122202, 0x3a1a2a0a, 0x31112101, 0x39192909, 
+    0x35152505, 0x3d1d2d0d, 0x14040800, 0x1a0a1202, 0x19091101, 0x1d0d1505, 0xffff1603, 0x2309e123, 
+    0xc51a0a01, 0x1a042908, 0x2f1a0c19, 0x04411a04, 0x1a046b1a, 0x01230493, 0x046f1a0b, 0x2904b31a, 
+    0x08f71a24, 0x1a0c8123, 0xa11a0491, 0x04cf1a04, 0x8b32dd23, 0x23483361, 0x391a0d1d, 0x04551a04, 
+    0x1a04871a, 0x751b0497, 0x0f22440e, 0x2304d31a, 0xb51a101f, 0x04d11a04, 0x2304ed1a, 0x471b1119, 
+    0x04196812, 0x232db923, 0x951a2e69, 0x29506904, 0x1c971a04, 0x1b04ef1a, 0x199c134f, 0x04951a04, 
+    0x1b04df1a, 0x19101455, 0x04ed1a04, 0xbc15191b, 0x15230419, 0x04bf1a18, 0x951b3c69, 0x04197c31, 
+    0x1a04cf1a, 0xf31a04e3, 0xb45d1a04, 0xc42f091b, 0x6f1a0419, 0x047f1a34, 0x23048f1a, 0x9d1a1691, 
+    0x04b91acc, 0x1a04d51a, 0xf51a04e5, 0x34051b04, 0x1a041958, 0x4d1a0431, 0x04691a04, 0x931b6069, 
+    0x1b22e81a, 0x1a08b11a, 0xb8a904e3, 0x1a041e09, 0x451a3815, 0x04671a04, 0x1a208123, 0x291a0465, 
+    0x10d71a44, 0x1a1c8d23, 0x282904ad, 0x1b1d0723, 0x192c1f35, 0x24231a04, 0x3304431a, 0x802319e5, 
+    0x04c01a05, 0x1a04d01a, 0x323104f0, 0xb2018210, 0x01041aff, 0x01015a71, 0xff3a1201, 0x21998101, 
+    0x03013103, 0x313d7c8a, 0x01999a2b, 0x333fa93c, 0x3fd3d301, 0x78a92119, 0x13091601, 0xc21309b1, 
+    0x52071241, 0x88027222, 0x8ce70410, 0xae0ded28, 0x8ef34d3f, 0xf4247453, 0x10212980, 0x4008010c, 
+    0x03054c4b, 0x01060204, 0x06041248, 0x01080102, 0x0c020302, 0x010f0a05, 0xc00e220f, 0x01031c21, 
+    0x0c292c03, 0x19390479, 0x11024e12, 0x1ab71274, 0x024b04b1, 0x0414b405, 0x401a1504, 0x1a073202, 
+    0x14120830, 0x76013514, 0x7e127f12, 0x78127b12, 0x0c227512, 0x12080813, 0x29042980, 0xc9c8140c, 
+    0xbdc81c02, 0x180d0e02, 0x2b2a2007, 0x49dc4998, 0x09c73998, 0x7012981f, 0x69046a1a, 0x06063c98, 
+    0x06329816, 0x20121812, 0x12b60a1a, 0x123f123b, 0x123c123e, 0x9838ba3a, 0x1bc70b1a, 0x2b98ca08, 
+    0x0c3202bb, 0x1a191018, 0x98039a98, 0x20090c29, 0x1a4b1298, 0x98690446, 0x1708083c, 0x12053298, 
+    0x08101a0c, 0x1d126d12, 0x1e1a1f12, 0x4a1c1206, 0x98598c1b, 0x2afb0a1a, 0xba1a9828, 0xff1b316d, 
+    0xff0242ff, 0xff1fb107, 0xff07ff3f, 0x013a0203, 0xff1b1102, 0x0f1a0c0f, 0x1a03e20a, 0x03810101, 
+    0x79aeae5e, 0x22440169, 0x14da2380, 0x751a1908, 0x0dffffd4, 0x80ffffe8, 0x0bfffff5, 0x74fffffb, 
+    0xa2fffffe, 0x38ffffff, 0x1838851a, 0xffc75c12, 0xffe6caff, 0xfff8ceff, 0xfffdb2ff, 0x239d4aff, 
+    0xe61a021c, 0x044f1a04, 0xe9483b1a, 0x2cbb1a38, 0xffcf2b1e, 0x1a684eff, 0x792304be, 0x385e1a04, 
+    0x1a40361a, 0x941a3464, 0x1af83278, 0x551a18ae, 0x2a9b1920, 0x2a2338ff, 0x680a1808, 0x0effffc8, 
+    0xb4fffff1, 0x2ce41a14, 0x1a244a1a, 0xcf1e3c58, 0xedfffffa, 0x031d2340, 0x1a18b81a, 0xd12a0cc0, 
+    0x2338197c, 0x0a181604, 0xfffff6b7, 0xfffff499, 0x7d367c42, 0xd0fffffc, 0x1a28561a, 0xc51a3097, 
+    0x04781a44, 0x1a0cc31a, 0x3e1a4cd4, 0x1a382918, 0x921e400a, 0x71ffffcc, 0x09221118, 0x273c6a1a, 
+    0xfffff925, 0x771a11a3, 0xf7a91e30, 0x1cb7ffff, 0x1a0b1c23, 0xc11a38ef, 0x233829ac, 0x0e181a8f, 
+    0xffffd049, 0xffffe845, 0xfffff578, 0xe01a7cf9, 0xc0341ab0, 0x3228351a, 0x38eb1a97, 0x38196dc2, 
+    0x183e3423, 0xffe5ab0a, 0xffd3afff, 0x1a3cbaff, 0x9b1a6018, 0xcccf1a54, 0x1a8c2e1a, 0xf21ab8bd, 
+    0x44501a0c, 0x5a04f81a, 0x9423e016, 0x320a180e, 0x5effffd2, 0xfefffff2, 0x18091aa0, 0x3228281a, 
+    0x1a3d328a, 0xc91a7c36, 0x04791a3c, 0x691ac632, 0x2118413c, 0xe77154c7, 0x73b8aa63, 0x39dc5531, 
+    0x1cee2a98, 0x0e77154c, 0x073b8aa6, 0x839dc553, 0xc1cee2a9, 0x1f601a1f, 0x1a1fb01a, 0xac1a1f58, 
+    0x5622181f, 0x4c766f4d, 0xa63b37a6, 0x531d9bd3, 0xa98ecde9, 0x54c766f4, 0xaa63b37a, 0x5531d9bd, 
+    0x2a98ecde, 0x1f151a1f, 0x1a1f8a1a, 0xe21a1fc5, 0x1f711a1f, 0x1a1fb81a, 0xee1a1fdc, 0x1f771a1f, 
+    0x1a1f3b1a, 0xce521f9d, 0x39010113, 0x29074902, 0x190d2910, 0x1105390a, 0xc40d2028, 0xe206f6d9, 
+    0x71037b6c, 0x3881bdb6, 0x9c40dedb, 0xce206f6d, 0x671037b6, 0xb3881bdb, 0x861a1fed, 0x1fc31a1f, 
+    0x1a1f611a, 0x581a1fb0, 0x1f2c1a1f, 0x1a1f961a, 0xe51a1fcb, 0x1f721a1f, 0x181f392a, 0x81ab6016, 
+    0x40d5b038, 0x206ad89c, 0x10356cce, 0x881ab667, 0x1a465bb3, 0x561a65ad, 0x1a1f1965, 0x6d1a1fdb, 
+    0x1fb61a1f, 0x2a1fdb1a, 0xaa699ded, 0xb3499c79, 0x1e29ac39, 0x84250d18, 0x42124210, 0x21092108, 
+    0x1a0b1084, 0x841a0b08, 0x0b421a0b, 0x690b211a, 0x0b041a14, 0x1a0b021a, 0x18111401, 0x5294a120, 
+    0x294a5042, 0x94a52821, 0x4a529410, 0x25294a08, 0x1294a584, 0x094a5242, 0x84a52921, 0x14421a14, 
+    0x1a14211a, 0x081b1410, 0x101a1f21, 0x1f081a1f, 0x1a1f841a, 0x211a1f42, 0x1f101a1f, 0x2a1f081a, 
+    0x49c1a484, 0x1a05c9b6, 0x401a2c80, 0x20100a2c, 0x1ab0a99c, 0x481a0b90, 0x14a41a0b, 0x1a14521a, 
+    0x941a1429, 0x144a1a14, 0x191fa51a, 0x14481a14, 0x0494a414, 0x02421014, 0x01210814, 0x23108423, 
+    0x88190842, 0x19116519, 0x65191165, 0x081a1f19, 0x1f841a1f, 0x1a1f421a, 0x106a1f21, 0x05019a8e, 
+    0x1301a5b9, 0x0e100a18, 0x100f100f, 0x04100110, 0x01393539, 0xff143a01, 0xfe1c01ff, 0x290802ff, 
+    0xfffd144e, 0x04fb1a04, 0xfffffe16, 0xf61406ff, 0xf31c0dff, 0x140e09ff, 0x1411fff9, 0x141dffe7, 
+    0x120fffe6, 0xffea1402, 0xffc8142a, 0xffd2143a, 0x14111214, 0x145effc5, 0x1a6dff8f, 0x3f121cb5, 
+    0xd3ff6f14, 0xd8ff1014, 0xe5ff8116, 0x1810ecff, 0x02dcfe1f, 0x0469fc42, 0x04c4fb3c, 0x03befb97, 
+    0x01e1fd24, 0x121bff14, 0xff28147f, 0xff2d14f0, 0xffc11691, 0x144bfff1, 0x1471ff93, 0x163bffa2, 
+    0xffecffef, 0xffc6142e, 0xffd61c38, 0xf1147816, 0xe31c1aff, 0x1a1819ff, 0xf73a7807, 0x1a0a1290, 
+    0x0212b4fa, 0x05fffc1c, 0xba035a04, 0x1902c449, 0xdc025a01, 0xfb1c0332, 0x1a520cff, 0x08120413, 
+    0xe8140612, 0xcc1429ff, 0xda1a34ff, 0x1421120e, 0x1475ffb2, 0x1a7eff77, 0x8e127cb4, 0xfeda1618, 
+    0xfdad01c3, 0xfd0402c1, 0xfd3f02fc, 0xfe3d0253, 0xe8720126, 0x82144c12, 0x8b1489ff, 0xdf3e4eff, 
+    0x26fff8ff, 0xffd71c40, 0xf8149a18, 0xed1a11ff, 0x9ef41a04, 0xa4fd5a21, 0x141cfe1a, 0x1a09ffea, 
+    0x57122a11, 0x6cff9214, 0xf7ffb916, 0xea1e80ff, 0xb301b7fe, 0xfd121160, 0x3f030b18, 0x49024dfd, 
+    0x800116fe, 0x14471228, 0x1a6eff94, 0xef1a56a9, 0xa4161a28, 0x481b1021, 0xfa20131e, 0x1f23fd21, 
+    0xc6286226, 0xfe2d4f2a, 0xd932d62f, 0x6b390a35, 0x4020283c, 0x47cf43cb, 0x50924c10, 0x5a675558, 
+    0x656f5fc2, 0x71cf6b72, 0x7fb2788e, 0x8f478743, 0x100297c5, 0xa93fff0c, 0x28016201, 0xe6010201, 
+    0xb712cb12, 0x3fff2018, 0x02bd035f, 0x01eb0236, 0x0179018f, 0x3fff0151, 0x03970434, 0x027602e0, 
+    0x01de01fe, 0x0e1810a4, 0x033903ff, 0x021c0290, 0x019a01ae, 0x0e18106b, 0x02d10373, 0x01ff024a, 
+    0x019201a3, 0x0e08106a, 0x10048d21, 0xcb037604, 0xf4022302, 0xc940b001, 0x23122130, 0x37122d12, 
+    0x4b124112, 0x11025512, 0x02dd165f, 0xc01e0180, 0x5eff7d1b, 0x78ff71ff, 0x6aff6bff, 0x93ff80ff, 
+    0x66ff81ff, 0xa3ff73ff, 0xbaffdfff, 0x2f010eff, 0x1a3c1909, 0x086901ff, 0x19961902, 0x631e09cb, 
+    0x03ffff17, 0x23010265, 0x30234874, 0x157c2323, 0x230ed823, 0xc9230b1e, 0x073c2308, 0x23061a23, 
+    0xb323054e, 0x043e1a04, 0x1a03db23, 0x4f1a048d, 0x04231a04, 0x1a02f423, 0xb91a04d5, 0x049c1a04, 
+    0x1a04891a, 0x691a0478, 0x04611a04, 0x1a045b1a, 0x4e1a044d, 0x044b1a04, 0x1a04411a, 0x441a0446, 
+    0x08405a04, 0x1a044c5a, 0x631a0458, 0x04711a04, 0x1a04831a, 0x931a048c, 0x609a5a04, 0xb81a0429, 
+    0x04c71a04, 0x1a04d31a, 0xf91a04ef, 0x880a1a04, 0x1a04251a, 0x541a0448, 0x04831a04, 0x1a04a61a, 
+    0xdf1a04b7, 0x04fd1a04, 0x1abc1b1a, 0x711a0454, 0x04a31a04, 0x1a04d01a, 0x1f1a04f4, 0x045d1adc, 
+    0x1a04931a, 0x2a1a04dc, 0x047f1af0, 0x2304e91a, 0xa01a0747, 0x04f91a04, 0x1a085a23, 0x252304c4, 
+    0x049e1a09, 0x1a0a1b23, 0x592304c2, 0x04ce1a0b, 0x230c7e23, 0x3d230d4f, 0x0f32230e, 0x23102623, 
+    0x8f23116c, 0x13e02312, 0x23154223, 0xaf1b169c, 0x191a4017, 0x231b222c, 0xa9231ca7, 0x2127231e, 
+    0x23236523, 0x3723262c, 0x2c182329, 0x232ea523, 0x04233238, 0x39392336, 0x1b3e4c23, 0x22c0423c, 
+    0x4acc2347, 0x23507523, 0x03235568, 0x6102235b, 0xcc64971b, 0xfb236b22, 0x778e2370, 0x1b7dd823, 
+    0x1a7c83b0, 0x8e22a887, 0x2391ab23, 0xd92397e5, 0x9e142398, 0xe39f7223, 0xfd749ddd, 0x8d19fdfd, 
+    0x1b026f01, 0x0f2603ff, 0x00000027, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x0005c000, 0xffffffff, 0xe594f000, 0xb07415bb, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
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+    0x072d2503, 0x37404e35, 0x29005419, 0x7f40d019, 0xd4090700, 0x22184b2d, 0x20172116, 0x5659569a, 
+    0x23005618, 0xfc19f006, 0x82ae8aa8, 0x20016821, 0x840819c9, 0x68004823, 0x07807800, 0x1c4017c0, 
+    0x8aa8bdf8, 0x682182ae, 0x19c92004, 0x20008408, 0xb5febdf8, 0x24004d1b, 0x30806828, 0x28007c80, 
+    0xf002d119, 0x270ffdab, 0xf006033f, 0x4e1cfdd3, 0x68310c00, 0x1a400c09, 0xdd0c42b8, 0x21ff4819, 
+    0x21f07081, 0x70047041, 0xf0062003, 0x6830ffb7, 0x18400439, 0x4e0e6030, 0x480f6831, 0x18083040, 
+    0x0bc08d00, 0x2300d106, 0x461a9907, 0x94002001, 0xff69f006, 0x31806829, 0x72c87a88, 0x68024804, 
+    0xe011200d, 0x20000090, 0x00007ad2, 0x20000200, 0x20000084, 0x0001a040, 0x0001a180, 0x0000fffa, 
+    0x20000088, 0x2000008c, 0x18100340, 0x0ac28f80, 0x0601728a, 0xd1030fc9, 0x0e800680, 0xf9ecf002, 
+    0x7c416828, 0xd0192900, 0xf007000b, 0x0708f983, 0x0b080507, 0x0713110e, 0xfe7ff000, 0xf000bdfe, 
+    0xbdfefef1, 0xff71f001, 0xf001bdfe, 0xbdfef991, 0xe0002000, 0xf0012001, 0xbdfefac0, 0x22522100, 
+    0x88015411, 0x078a4dfe, 0x2a002401, 0x0589db24, 0x3080d522, 0x29037a81, 0x2911d91e, 0x7d40d01c, 
+    0xd0192800, 0x68304ef7, 0x037f270d, 0x8e8019c0, 0xd11107c0, 0xfd7ff006, 0x49f31c40, 0x42884240, 
+    0x2102d30a, 0xf006201e, 0x2003ffc6, 0x8a810700, 0x68308285, 0xe30819c0, 0x68304eec, 0x7ac13080, 
+    0xd1062900, 0x28007a80, 0x2101d013, 0xf0062003, 0x6830ffb2, 0x7ac13080, 0xd9012903, 0xd1082911, 
+    0x28037a80, 0x2811d905, 0x2101d003, 0xf0062026, 0x48deffa2, 0x46026800, 0x7a913280, 0xd0212900, 
+    0xd07d2901, 0xd07c2902, 0xd07b2903, 0x7a823040, 0x4ed64fd3, 0x00133f0e, 0xf90cf007, 0xf4f5f625, 
+    0xf2f3f3f3, 0xf0f1f2f2, 0xecedeeef, 0xe8e9eaeb, 0xe4e5e6e7, 0xe3e2e3e3, 0xe3e3e3e3, 0xe2e3e3e2, 
+    0x00e2e1e1, 0x4fc97ad0, 0xd0032800, 0x20012102, 0xff71f006, 0x68314ec3, 0x180848c5, 0x07408a40, 
+    0xd0230f80, 0xd0292801, 0x30406838, 0x28007a40, 0xf002d001, 0x6839fc35, 0x31402001, 0x68307488, 
+    0x19c04fbc, 0x07408e00, 0x28010f80, 0x4cbad07e, 0x28007d20, 0xe760d000, 0x46039000, 0x21042201, 
+    0xf0069001, 0x2001fed2, 0xbdfe7520, 0x30406838, 0x28007a40, 0xf002d0f9, 0xbdfefc13, 0x680148a9, 
+    0x38c048ac, 0x89801808, 0x0fc007c0, 0x2003d012, 0x8a810700, 0x48a38285, 0x68022100, 0x38c048a5, 
+    0x81811810, 0xfc3bf002, 0x22bf6838, 0x7a013080, 0x72014011, 0x07362603, 0x20028ab0, 0xe00243c0, 
+    0xe156e0bb, 0x82b0e22b, 0x21024896, 0x48996802, 0x181038c0, 0xf0028141, 0x4894fbe3, 0x78006800, 
+    0xd00107c0, 0xfc4df006, 0x68394f8e, 0x18084890, 0x68398ac0, 0x0f000700, 0x310131ff, 0x23008d89, 
+    0x0fc90789, 0x43010109, 0x68004888, 0x0a028800, 0x43110212, 0x0a000600, 0x20034301, 0x91012202, 
+    0x46119000, 0xf0062001, 0xf002fe70, 0xf7fffd03, 0x2800fe4b, 0x8ab04b81, 0x2002d013, 0x82b043c0, 
+    0x2002683a, 0x1851497e, 0xe00080c8, 0x8ab0e03d, 0x210d82b3, 0x0189683a, 0x024020d1, 0x84c11810, 
+    0x82b3e010, 0x683a21ff, 0x20d13141, 0x18100240, 0x8ab084c1, 0x43c02002, 0x683a82b0, 0x49702000, 
+    0x80c81851, 0x82b58ab0, 0x486d6839, 0x18083040, 0x48668144, 0x7ac16800, 0x72c11c49, 0xe374bdfe, 
+    0xe307e1e2, 0xe3fde389, 0xe20ae276, 0xe398e2ce, 0xe2fbe321, 0xe2b8e2bf, 0xe250e36e, 0xe2a3e224, 
+    0xe1ffe21a, 0xe1eae2e8, 0x2403e1e1, 0x8aa00724, 0x43c02002, 0x683182a0, 0x19c92002, 0x68308548, 
+    0x8d8019c0, 0x0fc007c0, 0x8aa0d007, 0x683182a5, 0x19c92000, 0xf0028588, 0xf002fbd0, 0x484efb7c, 
+    0x07c07800, 0xf006d001, 0x484bfbbb, 0x88002102, 0xba402300, 0x90019100, 0x21052201, 0xf0064618, 
+    0x4945fdf4, 0x75082000, 0xfc5af002, 0x82a58aa0, 0x20016831, 0x854819c9, 0x4601e7b0, 0x7a4a3140, 
+    0x2a004e3a, 0x7880d005, 0xd1252800, 0x28007a08, 0x2000d022, 0x48387288, 0x06407800, 0x6830d539, 
+    0x07c07800, 0x492fd035, 0x4831680a, 0x8ac01810, 0x0f000700, 0xd1912808, 0x07002003, 0x82858a82, 
+    0x2300680e, 0x32404a2e, 0x807318b6, 0x82858a83, 0x18806808, 0xe7818044, 0xfb02f002, 0xfd94f7ff, 
+    0xd0d82800, 0x07002003, 0x82858a81, 0x680b491d, 0x025222d1, 0x84dc189b, 0x82858a83, 0x33ff680b, 
+    0x859c3301, 0x82858a83, 0x20006809, 0x84c81889, 0x4b14e7c1, 0x250d6818, 0x1940036d, 0x07808e40, 
+    0xd1090fc0, 0x07002003, 0x49168a81, 0x20018281, 0x03406819, 0x84081949, 0x19406818, 0x0ac28f80, 
+    0x46016830, 0x728a3180, 0xd0212a01, 0x1c497a81, 0x68187281, 0x8f401940, 0xb2c02300, 0xe0132202, 
+    0x0000fffe, 0x20000084, 0x0000ea60, 0x20000090, 0x0001a300, 0x0001a1c0, 0x20000200, 0x0000fc0f, 
+    0x0001a0c0, 0x0000dfff, 0x94002107, 0xe00b9001, 0x28017ac8, 0x6818d00b, 0x8f401940, 0xb2c02300, 
+    0x21062202, 0x90019400, 0xf0062001, 0x6830fd4e, 0x4601e0f7, 0x7a8a3140, 0x2a004efc, 0xd003724c, 
+    0x94002002, 0xe0f29001, 0x085279ca, 0x71ca0052, 0x28007880, 0x7a08d158, 0xd0552800, 0x07002003, 
+    0x21208a81, 0x828143c9, 0x200049f1, 0x210d680a, 0x18510349, 0xf0028408, 0x4dedfdc8, 0x48ed682a, 
+    0x8ac01810, 0x07006829, 0x31ff0f00, 0x8d893101, 0x07892300, 0x01090fc9, 0x68304301, 0x0a028800, 
+    0x43110212, 0x0a000600, 0x20034301, 0x90009101, 0x211a2202, 0xf0062001, 0x48dffd08, 0x88002102, 
+    0xba40460a, 0x90019100, 0x21192300, 0xf0062001, 0x6830fcfc, 0x46843080, 0x06407a00, 0x2200d474, 
+    0x07092103, 0x20848a88, 0x828843c0, 0x682e07d0, 0x4bd20e00, 0x1d0018f6, 0x200085b0, 0x28102100, 
+    0x231fd205, 0xe0041a1b, 0xfcc8f002, 0x4603e7b5, 0x4ecb3b10, 0x8ab7b2db, 0xd0072a00, 0x43ff271f, 
+    0x682f82b7, 0x19be4ec5, 0xe00685f3, 0x82b74fc5, 0x021e682f, 0x18fb4bc1, 0x4ec0859e, 0x36802300, 
+    0x19bf682f, 0x0a3f8a3f, 0x0fff07ff, 0x1c49d001, 0x1c5bb2c9, 0x2b0ab2db, 0x2800d3f2, 0x2905d004, 
+    0x281fd81e, 0xe017d002, 0xd9152905, 0x2a0048b4, 0xd0088a81, 0x43c9211f, 0x682b8281, 0x49af2010, 
+    0x85c81859, 0x49afe00c, 0x20018281, 0x0300682b, 0x185949aa, 0xe0038588, 0xb2c01c40, 0xd3ad2820, 
+    0xb2d21c52, 0xd39b2a02, 0x8a8148a5, 0x43c92104, 0x682a8281, 0x49a12000, 0x85881851, 0x7a004660, 
+    0x43082140, 0x72084661, 0x8a81489d, 0x8281499e, 0x682a2101, 0x200d0389, 0x18100340, 0x48948401, 
+    0x200d6801, 0x18080340, 0x4d908f80, 0x68290ac0, 0x72883180, 0xd0052803, 0x29037ac9, 0x2911d908, 
+    0xe00dd006, 0x28037ac8, 0x2101d00a, 0xe0052025, 0xd9052803, 0xd0032811, 0x20262101, 0xfccbf006, 
+    0x30406828, 0xe6197484, 0x94007244, 0x23009401, 0x21152202, 0xf0062001, 0x4881fc48, 0x82858a81, 
+    0x6801487b, 0x0340200d, 0x86441808, 0x2911e606, 0x2000d00a, 0xf00643c0, 0xf006fa3a, 0x6830fa4d, 
+    0x5c09218a, 0xd0032907, 0x30406830, 0xe5f57284, 0x29007881, 0x3040d106, 0x29007a01, 0x2113d002, 
+    0xe0cb7281, 0xfb67f003, 0xd0cc2802, 0x8a81486c, 0x82844c6e, 0x22804966, 0x230d680d, 0x18ed035b, 
+    0x8a82806a, 0x68098284, 0x18c92000, 0x68308048, 0x30402106, 0xe5d17281, 0xf81bf005, 0xd0b22802, 
+    0xf817f005, 0xd0ae2801, 0xf928f004, 0xd0aa2802, 0x21536830, 0x29005c09, 0x2901d004, 0x7801d12a, 
+    0xd5270749, 0x06007800, 0x2017d424, 0xfa98f000, 0xfb19f003, 0x21056830, 0x20098441, 0xf974f004, 
+    0x202b2104, 0xfc57f006, 0xfee8f003, 0x31606831, 0xf0007008, 0x6830fa5a, 0x3040210b, 0xf0007281, 
+    0x2800fa9c, 0xf004d092, 0x6830fae5, 0x7dc03040, 0xd0ee2800, 0x23006830, 0x78023060, 0x02127841, 
+    0x43117880, 0x43010400, 0x22012003, 0x90009101, 0x46102112, 0xfbb9f006, 0x21006830, 0x74813040, 
+    0x68307501, 0x31404601, 0x2a287aca, 0x2a29d001, 0x7d0ad102, 0xd06d2a01, 0x2a007cca, 0x2a01d004, 
+    0x7803d10a, 0xd507075b, 0x061b7803, 0x2300d404, 0x71833060, 0xe0027203, 0x71843060, 0x2a027204, 
+    0x4827d323, 0x82878a82, 0x23024c21, 0x220d6825, 0x18ad0352, 0x8a83862b, 0x82834b25, 0x15006823, 
+    0x8610189a, 0xe1362009, 0x72812100, 0x8a82481c, 0x4b178287, 0x220d681d, 0x18ad0352, 0x8a858629, 
+    0x82854d1b, 0x18806818, 0xf0048601, 0x2800ff09, 0xe533d000, 0xf004e073, 0x2802f8be, 0x6830d0f9, 
+    0x7bc13080, 0xd0312900, 0x73c12100, 0x202e2104, 0xfbd1f006, 0xf836f005, 0xd1ea2800, 0x680a4904, 
+    0x0340200d, 0x8e921812, 0xe01407d2, 0x20000090, 0x20000084, 0x0001a300, 0x20000200, 0x0001a100, 
+    0x30000000, 0x0000e0ff, 0x0000bfff, 0x0000ff7f, 0x0000fcff, 0xd07de057, 0x21886830, 0x07495c09, 
+    0x3040d579, 0x28007cc0, 0xe0ead076, 0xfdf1f004, 0xd0be2802, 0x202c2104, 0xfb9df006, 0x30406830, 
+    0x07497981, 0x7d80d505, 0xd0022801, 0xfc1ff004, 0xf004e001, 0x2802fc74, 0x6830d0ab, 0x5c092184, 
+    0xd1522900, 0x79813060, 0xd0022902, 0xd0022900, 0x7184e009, 0x2104e00c, 0xf006202d, 0xf004fb7c, 
+    0x2802fcfe, 0x6830d095, 0x79803060, 0xd1922801, 0x30606830, 0x29027a01, 0xf004d01c, 0x6830fadc, 
+    0x79813060, 0xd1862901, 0x28017a00, 0x6830d183, 0x7d813040, 0xd0062901, 0x1c497d01, 0x7501b2c9, 
+    0xd2002904, 0x6831e72d, 0x3240460a, 0x28007cd0, 0xe027d002, 0xe7ea7204, 0x07438808, 0x790bd522, 
+    0xd505061d, 0x0e400658, 0xf00073d0, 0xe019fbf3, 0x0f9b0683, 0xd0152b02, 0x07127992, 0x0600d512, 
+    0x3180d410, 0x06c07b48, 0xf005d40c, 0x2802f8d9, 0xe002d08f, 0xe07ae032, 0x6830e06f, 0x79003080, 
+    0xd1832800, 0x21956830, 0x29005c09, 0x3040d00d, 0x292c7ac1, 0x2116d009, 0xf7ff7281, 0x6830f98d, 
+    0x7ac03040, 0xd000282c, 0x6830e468, 0x5c092156, 0xd1002901, 0x7801e73a, 0xd4fb0609, 0x30602100, 
+    0xf00471c1, 0x2802fd9e, 0x6830d0ee, 0x79c03060, 0xd0f62800, 0x30806830, 0xe71c73c4, 0x072d2503, 
+    0x4b3a8aaa, 0x4a3a82ab, 0x68112700, 0x840f1809, 0x82ab8aa9, 0x21206812, 0x84011810, 0xf89bf006, 
+    0x42401c40, 0x08c02101, 0x42880409, 0x1e49d301, 0xb281e000, 0x82416830, 0x1c497b01, 0x30407301, 
+    0x21027204, 0xf006200e, 0x6830fad6, 0x30804601, 0x2a007d42, 0x7e42d00b, 0xd0082a00, 0x22078aaa, 
+    0x82aa43d2, 0x68124a22, 0x18d24b22, 0x73078517, 0x748c3140, 0x72882002, 0xf003e410, 0x2802fa64, 
+    0x6830d0a2, 0x308022fb, 0x40117a01, 0x201f7201, 0xf822f004, 0x21156830, 0x72813040, 0x07092103, 
+    0xe0008a88, 0x2080e00d, 0x828843c0, 0x21804810, 0x200d6802, 0x18100340, 0x68318401, 0x318020ff, 
+    0x68307288, 0x74843040, 0xf8e7f000, 0xd0d32800, 0x7a016830, 0xd1e109c9, 0x5c092190, 0xd1dd2900, 
+    0x75843040, 0xf860f7ff, 0x0000e656, 0x0000ffdf, 0x20000084, 0x0001a080, 0xd0162800, 0xd0152801, 
+    0x00402100, 0x1c490840, 0xb2490040, 0xdafa2800, 0x22e00dc0, 0x17ca4010, 0x18520ed2, 0x01520952, 
+    0x221f1a89, 0x18401a51, 0x4770b2c0, 0x477020e0, 0x2403b5f0, 0x8aa10724, 0x82a149fa, 0xdd012800, 
+    0xe0002101, 0x4af82100, 0x4ef80289, 0x68321889, 0x037f270d, 0x811119d2, 0x21002301, 0x4245025b, 
+    0x8aa2e007, 0x82a24af2, 0x19d26832, 0x1c498113, 0x2800b249, 0x4602db01, 0x462ae000, 0xdcf0428a, 
+    0xb5f0bdf0, 0x215348eb, 0x23016800, 0x270d5c09, 0x4ae72403, 0x037f025b, 0x4de40724, 0xd00c2900, 
+    0x5e412126, 0x46084ee4, 0xd00c3011, 0xd017290f, 0x82a28aa0, 0x19c06828, 0x8aa08103, 0x682882a2, 
+    0x810319c0, 0x203ee01b, 0xf7ff43c0, 0x2001ffb1, 0xffaef7ff, 0x20ff8aa0, 0x200182a0, 0xe00b0280, 
+    0x43c0203e, 0xffa4f7ff, 0xf7ff2001, 0x8aa0ffa1, 0x82a020ff, 0x02c02001, 0x19896829, 0x48cd8488, 
+    0x8cc16800, 0x84c11c49, 0xb530bdf0, 0x07002003, 0x4aca8a81, 0x49c58282, 0x680d2400, 0x18ed4bc6, 
+    0x8a84842c, 0x680c8282, 0x18e31c52, 0x8a82841a, 0x43d22280, 0x68098282, 0x220d2080, 0x18890352, 
+    0x48bc8408, 0x680021ff, 0x72813080, 0x48b7bd30, 0x49b96800, 0x8e801840, 0x16800480, 0x47704240, 
+    0x2103b530, 0x8a8a0709, 0x828a138a, 0x06924242, 0x0dd2230d, 0x18d4025b, 0x681d4bac, 0x18ad4aae, 
+    0x8a8c82ec, 0x828c4cad, 0x1c61681b, 0x82d1189a, 0x680949a8, 0x70483160, 0x48a6bd30, 0x30806800, 
+    0x28077a80, 0x2000d001, 0x20014770, 0xb5704770, 0x210048a0, 0x7f226804, 0x429a7da3, 0x1ad0d301, 
+    0x20ffe002, 0x18801ac0, 0x8ce0b2c5, 0xd1012863, 0x03c92101, 0xd3012aff, 0xe0002000, 0xb2c01c50, 
+    0xd1024283, 0x03b62601, 0x429a4331, 0x2201d102, 0x43110352, 0x82a14329, 0xb570bd70, 0xffd7f7ff, 
+    0xf7ff4605, 0x2800ffca, 0x4c8ad063, 0x7d086821, 0xd25e28fb, 0x5e8a2226, 0xd05a2a63, 0x7cce3140, 
+    0x49854882, 0x2e004b86, 0x3210d016, 0x68022a1f, 0x1856d81d, 0x5eb22228, 0x02926800, 0x8d401840, 
+    0x4310b2c0, 0xfed8f7ff, 0x68204602, 0x5a092144, 0x18087f00, 0xe01c541a, 0x18566802, 0x5eb22230, 
+    0x02926800, 0x8e401840, 0x0d800580, 0x1856e007, 0x5eb2222c, 0x02926800, 0x8dc01840, 0x4310b2c0, 
+    0xfebaf7ff, 0x68204601, 0x5a122244, 0x18107f00, 0x68205419, 0xf7ff7705, 0x211fff5a, 0xdc1c42c8, 
+    0x22446820, 0x7f045a12, 0x19122100, 0x7f015499, 0xd30129ff, 0xe0002100, 0x77011c49, 0x5e412126, 
+    0xda07291f, 0xfeddf7ff, 0xf7ff201f, 0xf7ffff49, 0xbd70ff1c, 0x84c12163, 0xf7ffbd70, 0x1e40ff38, 
+    0xe7f2b240, 0xf7ffb5f0, 0x4607ff62, 0xff55f7ff, 0xd06f2800, 0x68304e4f, 0x29fb7d01, 0x2126d26a, 
+    0x29635e41, 0x3040d066, 0x4c487cc0, 0x4b4c4d4a, 0xd00b2800, 0x68203110, 0xd812291f, 0x20281941, 
+    0x68215e08, 0x19490280, 0xe0118d49, 0x19416820, 0x5e082030, 0x02806821, 0x8e491949, 0x0d890589, 
+    0x1941e007, 0x5e08202c, 0x02806821, 0x8dc91949, 0x4308b2c9, 0xfe50f7ff, 0x68304601, 0x5a122244, 
+    0x18107f00, 0x68305419, 0x77072126, 0x291f5e41, 0xf7ffda02, 0xe02bfe86, 0x5a122244, 0x19d22100, 
+    0x7f015499, 0xd30129ff, 0xe0002100, 0x77011c49, 0xfeddf7ff, 0x43ff271e, 0xdd2442b8, 0x30406830, 
+    0x28007cc0, 0x2004d017, 0xfe42f7ff, 0x07002003, 0x21ff8a81, 0x20018281, 0x02406821, 0x84881949, 
+    0x84c76830, 0xfec3f7ff, 0xb2401e40, 0xfec8f7ff, 0xfe9bf7ff, 0x203ebdf0, 0xf7ff43c0, 0x2001fe29, 
+    0xfe26f7ff, 0x6831e7ec, 0x84c82063, 0xb510bdf0, 0xfe00f005, 0x0c02490f, 0x87086809, 0x848886ca, 
+    0xbd10844a, 0x4a09b510, 0x4b0e6811, 0x8e8918c9, 0x04492400, 0x08487004, 0x18c96811, 0x43088ec9, 
+    0x0000bd10, 0x00008b80, 0x00002001, 0x20000084, 0x0000fdff, 0x20000090, 0x0001a040, 0x00007fff, 
+    0x20000100, 0x0001a180, 0x2003b510, 0x8a810700, 0x310421ff, 0x4aff8281, 0x68142100, 0x18e44bfe, 
+    0x8a848421, 0x68148281, 0x846118e4, 0x82818a84, 0x18e46814, 0x8a8484a1, 0x68108281, 0x84c118c0, 
+    0xb510e7ce, 0xf7ff4604, 0x2103ffdf, 0x8a880709, 0x43c0201f, 0x48ef8288, 0x680306e2, 0x240d0ed2, 
+    0x191b0364, 0x8a8a855a, 0x828a4aec, 0x140b6804, 0x18a44ae9, 0x8a8b8423, 0x828b23ff, 0x68042301, 
+    0x18a4029b, 0x8a8b84a3, 0x43db2303, 0x6800828b, 0x18802103, 0xe7a384c1, 0x201fb510, 0xffd1f7ff, 
+    0x07002003, 0x21308a81, 0x828143c9, 0x221049d9, 0x240d680b, 0x191b0364, 0x8a82845a, 0x82824ad8, 
+    0x68092001, 0x4ad70280, 0x84481889, 0xb5f8e788, 0x21264ed5, 0x5e416830, 0xb24d120c, 0x311f4629, 
+    0xd204293f, 0xdc022c1f, 0x42cc211f, 0x2201da09, 0x03d2b2e1, 0x82811889, 0x70443080, 0x20017085, 
+    0xf7ffbdf8, 0x6831fe04, 0x76483140, 0xf7ff4628, 0xf7fffe07, 0x6831ffc1, 0x5c402053, 0xd00e2800, 
+    0x27102003, 0x22ff0700, 0x42fc4bba, 0x0067da09, 0x84cf3740, 0x82828a87, 0x02522201, 0x84cce00a, 
+    0x2c0fe00f, 0x0067dd0b, 0x84cf3f3c, 0x82828a87, 0x02d22201, 0x48b0681b, 0x84821818, 0x0060e001, 
+    0x8cc884c8, 0xf7ffb240, 0x4668fd43, 0xff2af7ff, 0xff1df7ff, 0xfda9f7ff, 0x21016830, 0x30808281, 
+    0x70857044, 0xbdf82000, 0x4ca2b5f0, 0x230d6821, 0x18c9035b, 0x4aa48a89, 0x68151209, 0x5d522277, 
+    0x18511809, 0xb2490049, 0x22031049, 0x8a960712, 0x360c4e9a, 0x26018296, 0x03766827, 0x813e18ff, 
+    0x4e97060f, 0x82968a97, 0x6827d505, 0x18ff2600, 0x4249813e, 0x2601e004, 0x02b66827, 0x813e18ff, 
+    0x267f8a96, 0x829643f6, 0x26016827, 0x813e18ff, 0xe00a2600, 0x4c8d8a94, 0x4f868294, 0x683f2401, 
+    0x18ff0264, 0x1c76813c, 0x428eb276, 0x3540dbf2, 0xbdf07428, 0x4d7fb5f0, 0x260d6829, 0x19890376, 
+    0x24038a89, 0x00401808, 0x1040b240, 0x8aa10724, 0x310c497a, 0x210182a1, 0x0389682a, 0x81111992, 
+    0x21000603, 0x4a762b00, 0x82a28aa3, 0x682ada04, 0x81111992, 0xe0044240, 0x682b2201, 0x199b0292, 
+    0x4a71811a, 0x68124f71, 0x7b933240, 0x02522201, 0xd0132b00, 0x217f8aa1, 0x82a143c9, 0x2101682b, 
+    0x8119199b, 0xe0062100, 0x82a78aa3, 0x199b682b, 0x1c49811a, 0x4281b249, 0xbdf0dbf6, 0x4b648aa3, 
+    0x064082a3, 0x0e402301, 0x18c002db, 0x199b682b, 0x8aa08118, 0x682882a7, 0x81021980, 0x485c8aa0, 
+    0x82a0307f, 0x19806828, 0xbdf08101, 0x1040300f, 0xb5104770, 0x07092103, 0x138a8a8a, 0x05c0828a, 
+    0x0dc02211, 0x18830252, 0x68144a4a, 0x1824484a, 0x8a8b82e3, 0x828b4b4f, 0x1c596812, 0x82c11810, 
+    0xb510e66e, 0x07092103, 0x138a8a8a, 0x05c0828a, 0x0dc02209, 0x18830292, 0x68144a3e, 0x1824483e, 
+    0x8a8b82e3, 0x828b4b43, 0x1c596812, 0x82c11810, 0xb510e656, 0x68204c3c, 0x46017dc2, 0x31400753, 
+    0xda142b00, 0xd40d0792, 0x56412181, 0x1048310f, 0xffd7f7ff, 0x20826821, 0x300f5608, 0xf7ff1040, 
+    0xe00dffb8, 0x5608200f, 0xff54f7ff, 0x2019e008, 0xf7ff5608, 0x6821fcd5, 0x56082050, 0xff04f7ff, 
+    0x7dc06820, 0xd50c0700, 0x07002003, 0x21088a81, 0x828143c9, 0x2008491f, 0x4a1f6809, 0x18893240, 
+    0xe61d8008, 0x4606b570, 0xfc04f005, 0x46044d1e, 0x30226828, 0xff16f005, 0x20104601, 0x1a6041c1, 
+    0x682d6030, 0x30364628, 0xff0cf005, 0x20104601, 0x481941c1, 0x1a617c6a, 0x2a057c40, 0x0440d004, 
+    0xd2034288, 0xbd702001, 0xe7f901c0, 0xbd702000, 0x480db5f8, 0x8a806800, 0xd42f0400, 0x07362603, 
+    0x4f0e8ab0, 0x4c0382b7, 0x68222120, 0x0340200d, 0xe0151810, 0x20000084, 0x0001a040, 0x00008ff3, 
+    0x0000fbff, 0x0001a180, 0x20000090, 0x0000fdff, 0x0000f780, 0x00007fff, 0x20000200, 0x0000ffdf, 
+    0x46688441, 0xffaef7ff, 0x28012500, 0x8ab0d007, 0x682182b7, 0x0340200d, 0x84451808, 0xf7ffbdf8, 
+    0x48ffff68, 0x68002101, 0x21537441, 0x29005c09, 0x2281d00e, 0x4afb5611, 0x291f3110, 0xd80a6821, 
+    0x23281889, 0x02995ecb, 0x189a6823, 0xe0098d52, 0x83458305, 0x188be00b, 0x5e59212c, 0x02896823, 
+    0x8dd2189a, 0x4311b2d2, 0x83020c0a, 0x49ee8341, 0xbdf88281, 0x4feab5f8, 0x68394dec, 0x31a04eec, 
+    0x4cec7848, 0xd10707c0, 0x48eb8aa8, 0x200182a8, 0x02c06832, 0x81101912, 0x70c82000, 0xfc20f7ff, 
+    0x30a06838, 0x06407840, 0x28060f40, 0x2100d113, 0xf0022001, 0x2100fe14, 0xf0022002, 0x2100fe10, 
+    0xf0022003, 0x2100fe0c, 0xf0022004, 0x2100fe08, 0xf0022005, 0x6831fe04, 0x180848d6, 0xf7ff8b84, 
+    0x2c28fd73, 0x2c50d043, 0x2c78d043, 0x2ca0d043, 0x2cc8d043, 0x2cf0d043, 0x2000d043, 0x21838aa9, 
+    0x683282a9, 0x48c70201, 0x84d11812, 0x49cb8aa9, 0x49cb82a9, 0x18126832, 0x8aa98411, 0x82a921ff, 
+    0x68322101, 0x18120289, 0x8aa98491, 0x43c92180, 0x683382a9, 0x49bf2280, 0x841a185b, 0x43d38aab, 
+    0x683382ab, 0x84c21818, 0x201f8aa8, 0x82a843c0, 0x200c6832, 0x85481851, 0x21a16838, 0x22065c09, 
+    0x0f490709, 0x408c1a51, 0x84843080, 0x2001bdf8, 0x2003e7c4, 0x2005e7c2, 0x2007e7c0, 0x2009e7be, 
+    0x200be7bc, 0xb500e7ba, 0x230049a5, 0x43db6809, 0x32a0460a, 0x840b70d0, 0x70932302, 0x31402200, 
+    0xf7ff75ca, 0xf7fffb9d, 0xbd00fb70, 0x2100489c, 0x77016800, 0x82817581, 0x5c0921a1, 0x09ca3080, 
+    0x2a008c81, 0x0049d000, 0x200084c1, 0xb500e7db, 0x23004993, 0x43db6809, 0x32a0460a, 0x840b70d0, 
+    0x70932302, 0x31402200, 0xf7ff75ca, 0xf7fffb79, 0xbd00fb4c, 0x4614b510, 0xd0091a41, 0x1b1a0040, 
+    0xf0054350, 0x1c40fdea, 0x18201040, 0xe4c7b200, 0x0fc118d0, 0x10401808, 0xb5f1e7f8, 0x21a14f80, 
+    0x26016838, 0x25005c09, 0x0709468c, 0x46310f4a, 0xb24c4091, 0x7d827f01, 0x4291b082, 0x1a8bd301, 
+    0x23ffe002, 0x185b1a9b, 0x8283b29b, 0xd30129ff, 0xe0002700, 0xb2ff1c4f, 0x42ba9700, 0x2701d103, 
+    0x433b03bf, 0x42918283, 0x8a81d104, 0x03522201, 0x82814311, 0x9a02211f, 0x4f6e43c9, 0xd1232a01, 
+    0x8cc03080, 0xd11f2800, 0x09c04660, 0x4660d01c, 0xd00007c0, 0x46082120, 0xfa8af7ff, 0x8a814863, 
+    0x82814968, 0x2201485e, 0x02926800, 0x784130a0, 0x17c907c9, 0x188a0289, 0x6809495d, 0x810a19c9, 
+    0x06497841, 0x70410e49, 0x68014859, 0x18084859, 0x4b538f80, 0x68180ac2, 0x31804601, 0x8cc9728a, 
+    0xd0752900, 0xd1732a07, 0x29fb7d01, 0x4950d270, 0x494c680a, 0x27301851, 0x46025fcf, 0x789132a0, 
+    0xd80f2904, 0x56d32303, 0x2f002006, 0x1a41db03, 0x40884630, 0x1a41e003, 0x40884630, 0x18184240, 
+    0xe04370d0, 0x43db2300, 0xd00b2905, 0xdd112f00, 0x5e412120, 0xdb1f2900, 0x56512103, 0xda17291f, 
+    0xe0131c49, 0x56102003, 0xdb002f00, 0x18c02301, 0xe02870d0, 0xda0f2f00, 0x5e412120, 0xdc152900, 
+    0x56512103, 0x42d9231f, 0x1e49dd02, 0xe01a70d1, 0x75c63040, 0xe016014d, 0x56512103, 0x461a014b, 
+    0x25203220, 0x46395f45, 0xe0054628, 0x56102003, 0x46130142, 0x46383b20, 0xff2cf7ff, 0x48204605, 
+    0x30406800, 0x481e75c6, 0x84076800, 0x6800481c, 0x31a04601, 0x4607788a, 0x708a1c52, 0x7dfa3740, 
+    0xd0062a01, 0x56082003, 0xfa8af7ff, 0xfa5df7ff, 0x88babdfe, 0x18d37f03, 0x54d54a1b, 0x77029a00, 
+    0xd3012aff, 0xe0002300, 0x88bf1c53, 0x18bf042d, 0x0e2d4a15, 0x770355d5, 0x8cc23080, 0xb2931e52, 
+    0x220084c3, 0x9d0270ca, 0x2d014a10, 0x784dd032, 0xd02609ed, 0x42838c80, 0x4804d123, 0xe0178a83, 
+    0x20000090, 0x0001a040, 0x0000ec01, 0x30000000, 0x20000084, 0x0001a000, 0x0000f7ff, 0x00000ff3, 
+    0x0000b00c, 0x0000fbff, 0x20000100, 0x0000fdff, 0x43db237c, 0x48ff8283, 0x68052304, 0x182848fe, 
+    0x250384c3, 0x8aa8072d, 0x82a848fc, 0xdd1d2c00, 0xe01c2001, 0x250d2303, 0x071b2000, 0x2601036d, 
+    0xe0070276, 0x829a8a9c, 0x68244cf2, 0x81261964, 0xb2c01c40, 0x0764784c, 0x24010fa7, 0x428440bc, 
+    0x2003dcf0, 0xf7ff5608, 0xbdfefe92, 0x4bec2000, 0x43180280, 0x681e4be7, 0x037f270d, 0x813019f6, 
+    0x20002201, 0x42660252, 0x8aabe008, 0x82ab4be5, 0x681b4be0, 0x811a19db, 0xb2c01c40, 0xdb012c00, 
+    0xe0004623, 0x42834633, 0x2003dcef, 0xf7ff5608, 0xbdfefe4a, 0x4edcb5f0, 0x68302400, 0x82847584, 
+    0xfb62f7ff, 0x072d2503, 0x20038aa8, 0x4fd182a8, 0x49d16838, 0x84c41840, 0x30a06830, 0x462070c4, 
+    0xf9def7ff, 0x48cd8aa8, 0x683982a8, 0x0340200d, 0x810c1809, 0x49cd8aa9, 0x683982a9, 0x81041808, 
+    0xb500bdf0, 0x200049c8, 0x31a06809, 0xf7ff70c8, 0xbd00f9c7, 0x4cc4b510, 0x68202100, 0x75817701, 
+    0x21028281, 0x708130a0, 0x07c07840, 0x2020d001, 0x201fe001, 0xf7ff43c0, 0x2003f91b, 0x8a810700, 
+    0x828149bb, 0x23016820, 0x30a04602, 0x029b7841, 0x17c907c9, 0x18c90289, 0x681b4bae, 0x0364240d, 
+    0x8119191b, 0x23807841, 0x70414319, 0x0f810748, 0x40c82040, 0x84d03280, 0xf7ff2000, 0xe47ffe08, 
+    0xf7ffb530, 0x4da8f984, 0x31406829, 0x201f7648, 0xf986f7ff, 0x6828211e, 0x84c143c9, 0x7cc03040, 
+    0xd01d2800, 0xf7ff2002, 0x6828f8e3, 0x85042400, 0x75847704, 0xf7ff201f, 0x6828fb04, 0x5c092153, 
+    0xd00b2900, 0x07092103, 0x22ff8a8a, 0x4a91828a, 0x68122101, 0x4b900249, 0x849118d2, 0xbd308284, 
+    0x43c0201f, 0xf8c4f7ff, 0xe7dc2001, 0x4604b510, 0xfacaf7ff, 0x07092103, 0x201f8a88, 0x828843c0, 
+    0x06e24884, 0x0ed26803, 0x0364240d, 0x855a191b, 0x4a888a8a, 0x4b88828a, 0x4a7f6804, 0x842318a4, 
+    0x23ff8a8b, 0x2101828b, 0x02896800, 0x84811880, 0xb500e426, 0xf92bf7ff, 0x2259497b, 0x54506809, 
+    0x77082000, 0x201c7588, 0xffd0f7ff, 0xb510bd00, 0xfc2ff7ff, 0xfa98f7ff, 0x07092103, 0x20308a88, 
+    0x828843c0, 0x20004a6b, 0x240d6813, 0x191b0364, 0x8a8b8458, 0x828b4b6e, 0x4a706811, 0x84481889, 
+    0x68094969, 0x758875c8, 0xe4118288, 0x2300b510, 0xd01c2800, 0x22004c6a, 0xd90042a0, 0x1c524620, 
+    0xb2520040, 0xdafa2800, 0x0ee417d4, 0x096418a4, 0x1b120164, 0x1aa2241f, 0x700ab2d2, 0xd2092a08, 
+    0x06000e00, 0x40d01aa2, 0x700bb2c0, 0x700be429, 0xe4262000, 0x1fd20e00, 0xe422700a, 0x2403b5f0, 
+    0x8aa10724, 0x82a1494d, 0xdd012800, 0xe0002101, 0x4a542100, 0x4e470289, 0x68321889, 0x037f270d, 
+    0x811119d2, 0x21002301, 0x4245025b, 0x8aa2e007, 0x82a24a44, 0x19d26832, 0x1c498113, 0x2800b249, 
+    0x4602db01, 0x462ae000, 0xdcf0428a, 0xb5f0bdf0, 0x2200270e, 0x4e444d37, 0x4c3b43ff, 0x2900230f, 
+    0x2800d016, 0x4610d009, 0x6829e009, 0x88891989, 0x16890689, 0x84c11a79, 0x461fbdf0, 0xf7ff4618, 
+    0x6820fb90, 0x09097dc1, 0x078943c9, 0xbdf0d1ed, 0xd0012800, 0xe0014610, 0x4618461f, 0xfb69f7ff, 
+    0x19806828, 0x68218840, 0x16800680, 0x84c81a38, 0x0040bdf0, 0xb240380f, 0xb5304770, 0x20004c22, 
+    0x4a1c6821, 0x68108508, 0x18c04b27, 0x06808880, 0xf7ff1680, 0x6821ffee, 0x70483180, 0x18c06810, 
+    0x06808840, 0xf7ff1680, 0x6821ffe4, 0x460b2201, 0x70983380, 0x2a00569a, 0x4615db01, 0x4255e000, 
+    0xdb012800, 0xe0004603, 0x429d4243, 0x8d0bdd03, 0x432b2504, 0x2a00850b, 0x8d0add03, 0x431a2302, 
+    0x2800850a, 0x8d08dd03, 0x43102201, 0x7dca8508, 0xe01b0690, 0x20000084, 0x0001a040, 0x00008b80, 
+    0x00007001, 0x0000fdff, 0x20000090, 0x0000f7ff, 0x0000fbff, 0x00000ff3, 0x0000b00c, 0x0001a180, 
+    0x007fffff, 0x00004001, 0x0001a280, 0xd0130f80, 0xd0202801, 0xd0212802, 0xd10c2803, 0x21018d08, 
+    0x0fc00780, 0xff63f7ff, 0x8d006820, 0x0fc007c0, 0xf7ff2100, 0xbd30ff5c, 0x5e082028, 0xdb012804, 
+    0xe0002101, 0x28042100, 0x0780db02, 0xe7f00fc0, 0x0fc007c0, 0x07d0e7ed, 0xe7e90fc0, 0x0fc007d0, 
+    0xe7e62101, 0xf7feb5f8, 0x4cfefff2, 0x68212259, 0x54502700, 0x7dc8828f, 0x07034dfd, 0x4afb48fa, 
+    0x8aab4efc, 0xd50382a8, 0x18806830, 0xe0038007, 0x20086833, 0x8010189a, 0x07407dc8, 0x00030f40, 
+    0xfb28f005, 0x1b0e0508, 0x5e43432f, 0x201f4566, 0xffd6f7fe, 0x20506821, 0xf7ff5608, 0xe018fa05, 
+    0x43c0201e, 0xffccf7fe, 0x20506821, 0xf7ff5608, 0xe021f9fb, 0x84c86821, 0x2000e029, 0xffc0f7fe, 
+    0x30406820, 0x28007cc0, 0x2001d005, 0xf7fe43c0, 0x201fff1f, 0x2020e7ee, 0xff1af7fe, 0x43c02000, 
+    0x2000e7f5, 0xffacf7fe, 0x30406820, 0x28007cc0, 0x2002d005, 0xff0cf7fe, 0x43c0201e, 0x201fe7da, 
+    0xf7fe43c0, 0x2001ff05, 0xf7ffe7f4, 0x6820ff16, 0x07407dc0, 0xf7ffd42b, 0x6820f94f, 0x5c092153, 
+    0xd0222900, 0x07817dc0, 0x49c8d51f, 0x20ff07c2, 0x2a003940, 0x82a88aaa, 0x2001d012, 0xe0110240, 
+    0xf7ff2020, 0x2000fe9b, 0xf7ff43c0, 0xe7c0fe97, 0x43c0201f, 0xfe92f7ff, 0xf7ff2001, 0xe7cbfe8f, 
+    0x02c02001, 0x18516832, 0xf7fe8488, 0xf7ffff3e, 0x6820f8ae, 0xf7ff305e, 0x6820f8b5, 0x77077587, 
+    0x87878747, 0xb510bdf8, 0xfea4f004, 0x680949ad, 0x0c008488, 0xe5c28448, 0x4606b57c, 0x46696808, 
+    0xf7ff08c0, 0x4da7fe43, 0x68292244, 0x5a524caa, 0x18d27f0b, 0x7f0854a0, 0xd30128ff, 0xe00020ff, 
+    0x77081c40, 0x6830a901, 0xfe30f7ff, 0x78094669, 0x4669010a, 0x430a7909, 0x460b6829, 0x889d3340, 
+    0x19ad7f0e, 0x7f0a5562, 0xd3012aff, 0xe00022ff, 0xb2d21c52, 0x889b770a, 0x54a0189a, 0x28ff7f08, 
+    0x20ffd301, 0x1c40e000, 0xbd7c7708, 0x4a8db570, 0x6814230e, 0x84e32500, 0x4c904b8e, 0xd02b2900, 
+    0x68182800, 0x1900d011, 0x06808880, 0xf7ff1680, 0x6811fe80, 0x578e2681, 0xda1a42b0, 0x19006818, 
+    0x06808880, 0x1c401680, 0x1900e010, 0x06808880, 0xf7ff1680, 0x6811fe6e, 0x578e2681, 0xdd0842b0, 
+    0x19006818, 0x06808880, 0x1e401680, 0xf9d9f7ff, 0x6810bd70, 0xbd7084c5, 0x68182800, 0x1900d011, 
+    0x06808840, 0xf7ff1680, 0x6811fe54, 0x578e2682, 0xdaee42b0, 0x19006818, 0x06808840, 0x1c401680, 
+    0x1900e010, 0x06808840, 0xf7ff1680, 0x6811fe42, 0x578e2682, 0xdddc42b0, 0x19006818, 0x06808840, 
+    0x1e401680, 0xf995f7ff, 0xb5f0bd70, 0x2000b085, 0x4f5c4669, 0x68387208, 0x04098a81, 0x4d5cd47e, 
+    0x21208aa9, 0x82a943c9, 0x21204c5a, 0x260d6822, 0x19920376, 0x21538451, 0x29005c09, 0x2126d012, 
+    0x31105e41, 0xd902291f, 0x07807dc0, 0x6820d40e, 0x3940494e, 0x20281842, 0x68225e10, 0x18510280, 
+    0xe00d8d49, 0xf7fea802, 0xe00bffdd, 0x49476820, 0x18423940, 0x5e10202c, 0x02806822, 0x8dc91851, 
+    0x4308b2c9, 0xa8019000, 0xf9bcf7ff, 0x483d9003, 0x46386807, 0xf005303a, 0x2110f8d5, 0x990041c8, 
+    0x42881840, 0x2000d201, 0x990343c0, 0x29019000, 0x8cf9d021, 0xd01e2900, 0x7c894939, 0x42810109, 
+    0x2227d276, 0x02129901, 0xd8054291, 0x42914a35, 0x7df9d96e, 0xd56b0649, 0x4668a901, 0xfefcf7ff, 
+    0x68114a28, 0x07d87dcb, 0x5e08482f, 0x2800d020, 0x1c40da1c, 0xa901e01f, 0xf7ff4668, 0x4668feed, 
+    0x28007a00, 0x2000d010, 0x03802101, 0x184103c9, 0x03409803, 0x481b4301, 0xe0006800, 0x7f02e002, 
+    0x82814311, 0xbdf0b005, 0xe7ed2001, 0xe0022000, 0xddfb2800, 0x84c81e40, 0xd5590798, 0x5c472053, 
+    0x4a1a2001, 0x2f000240, 0x075fd001, 0x8aa9d505, 0x682182aa, 0x81081989, 0x07dbe07f, 0x2b0027ff, 
+    0x2326d02c, 0x33105ecb, 0x203ed12b, 0xf7fe43c0, 0x2001fd6f, 0xfd6cf7fe, 0x82af8aa8, 0x02892101, 
+    0xe0166822, 0x20000090, 0x0000fff7, 0x0001a080, 0x30000000, 0x20000084, 0x20000100, 0x0001a280, 
+    0x20000200, 0x000007cc, 0x00000026, 0x0000fdff, 0x48fee070, 0x18103840, 0xe04e8481, 0x290f8cc9, 
+    0x8aa9d005, 0x682182aa, 0x81081989, 0x203fe7bf, 0xfd3ef7fe, 0x43c02000, 0xfd3af7fe, 0x82af8aa8, 
+    0x68222001, 0x49f10280, 0x18513940, 0xe0348488, 0x07584fef, 0x0698d52d, 0xd0060f80, 0xd0152801, 
+    0xd0162802, 0xd1282803, 0x2028e017, 0x28045e08, 0x2101db01, 0x2100e000, 0xdb022803, 0x0fc00780, 
+    0x07c0e001, 0xf7ff0fc0, 0xe016fe91, 0x0fc007d8, 0x07d8e00d, 0x21010fc0, 0x8d08e7f5, 0x07802101, 
+    0xf7ff0fc0, 0x6838fe83, 0x07c08d00, 0x21000fc0, 0x8cc8e7e9, 0xf7feb240, 0xf7fffd93, 0x48d4fe34, 
+    0x68002700, 0x87878747, 0xfd5ff7fe, 0xf7fea802, 0x9000fed9, 0x20208aa8, 0x82a843c0, 0x19806820, 
+    0x48cb8447, 0x8cc16800, 0x06497f02, 0x430a0c49, 0xe7478282, 0x87790c01, 0xf7fe87b8, 0x8aa8fd46, 
+    0x43c02020, 0x682182a8, 0x19892000, 0xe7e88448, 0x2003b5f0, 0x8a810700, 0x828149be, 0x220049be, 
+    0x230d680c, 0x18e4035b, 0x8a848062, 0x82862601, 0x680d2469, 0x18ed0124, 0x8a8480ac, 0x82841e94, 
+    0x18e4680c, 0x8a8480e2, 0x82844cb4, 0x18e4680c, 0x8a848122, 0x82844cb2, 0x18e4680c, 0x8a848422, 
+    0x82854db0, 0x18e4680c, 0x8a848462, 0x82844cae, 0x10dc680f, 0x853c18ff, 0x241f8a84, 0x828443e4, 
+    0x240d680f, 0x857c18ff, 0x4ca88a84, 0x680c8284, 0x861e18e3, 0x4ba68a83, 0x680c8283, 0x3b404b9b, 
+    0x802218e4, 0x4ea38a84, 0x680c8286, 0x806218e4, 0x82868a84, 0x18e4680c, 0x8a8480a2, 0x82841cb4, 
+    0x18f6680e, 0x8a8680f2, 0x680e8284, 0x813218f6, 0x82848a86, 0x18e4680c, 0x8a848162, 0x82844c96, 
+    0x18e4680c, 0x8a8481a2, 0x43e424c0, 0x680e8284, 0x18f62440, 0x8a8481f4, 0x03a42401, 0x680c8284, 
+    0x82e218e4, 0x24ff8a84, 0x82843404, 0x18e4680c, 0x8a848422, 0x680c8282, 0x846218e4, 0x82828a84, 
+    0x18e4680c, 0x8a8484a2, 0x680c8282, 0x84da18e3, 0x23198a83, 0x828343db, 0x2310680e, 0x19364c73, 
+    0x8a838033, 0x33294b77, 0x680f8283, 0x193f2604, 0x8a86843e, 0x680e8283, 0x85221934, 0x82828a84, 
+    0x4c6a680e, 0x19363440, 0x8a868032, 0x680e8282, 0x80721936, 0x82838a86, 0x191b680b, 0x8a83809a, 
+    0x680b8285, 0x34804c61, 0x84da191b, 0x4b678a83, 0x82833bf1, 0x49696808, 0x84421840, 0x2103bdf0, 
+    0x8a8a0709, 0x828a2200, 0x0200495b, 0x220d6809, 0x18890352, 0x83483080, 0x22034770, 0x8a930712, 
+    0x8293233f, 0x01000709, 0x43080f09, 0x21800200, 0x43083040, 0x68094950, 0x0352220d, 0x83481889, 
+    0xb5104770, 0x46112200, 0xe0074c55, 0xd00207c3, 0x5ae3004b, 0x1c49405a, 0x0840b289, 0xd1f52800, 
+    0xe5184610, 0x4844b5f0, 0x68004d46, 0x210d3530, 0x18400349, 0x27008b86, 0xe009463c, 0x0a295d38, 
+    0xf7ff4048, 0x0229ffde, 0x1c644048, 0xb2a4b285, 0xd3f342b4, 0xbdf04628, 0x4e37b5fe, 0x270d6831, 
+    0x19c9037f, 0x4a3f8b49, 0x7d520a09, 0x00d22500, 0x4a2f9200, 0x46236814, 0x462233a0, 0x32409301, 
+    0xf0040003, 0x0e19ff87, 0x71181819, 0xf3f4f599, 0xeff0f1f2, 0xeced18ee, 0xe8e9eaeb, 0xe618e718, 
+    0x20030018, 0x8a810700, 0x43c921c0, 0x68318281, 0x19c92080, 0xbdfe8348, 0xd0052900, 0xd0092901, 
+    0xd0132902, 0xe2602101, 0x28007c90, 0x2001d0f3, 0xe2567460, 0x24082004, 0xff29f000, 0xf0004620, 
+    0x4913ff26, 0x68092001, 0xe24a7448, 0x72502001, 0xf7fd7465, 0x6830fba9, 0x8e8019c0, 0xd00907c0, 
+    0x07002003, 0x21208a81, 0x828143c9, 0x20206831, 0x840819c9, 0xf7ff2000, 0x2004ff52, 0xf0002408, 
+    0x4620fefc, 0xfef9f000, 0x0000bdfe, 0x0001a080, 0x20000090, 0x0000f87f, 0x20000084, 0x00008180, 
+    0x0000bf1f, 0x0000ffcf, 0x000083ff, 0x0000fcf0, 0x00003fff, 0x000013fd, 0x0000c0c0, 0x0001a180, 
+    0x00007afc, 0x20000200, 0xd0062900, 0xd00b2901, 0xd0132902, 0xd1ac2903, 0x2003e017, 0x8a810700, 
+    0xf0048285, 0xe005fb0e, 0x07002003, 0x82858a81, 0xfb03f004, 0x19c96831, 0xe1f28388, 0x07002003, 
+    0x82858a81, 0x7ca03480, 0x2003e7f4, 0x8a810700, 0xf0048285, 0xe7edfb20, 0x000b1e89, 0xfeeaf004, 
+    0x59312405, 0x0004056b, 0x7c61e7ae, 0xd2682902, 0x2b017cd3, 0x7c93d870, 0xd1012b00, 0xd0a32900, 
+    0x68307611, 0x8b8019c0, 0xf7fe84e0, 0x0001fd60, 0x2006d001, 0x48ffe05d, 0x68002105, 0x21037441, 
+    0x8a8a0709, 0xe115828d, 0x28007c90, 0x7c60d102, 0xd0892800, 0x76107c60, 0x74602001, 0xfa39f7ff, 
+    0x2001e1af, 0x7c607250, 0x28024ef2, 0x48f2d30a, 0x60054cf2, 0x816020ff, 0x1c418120, 0xf00448f0, 
+    0x7565fdbd, 0xfa33f7ff, 0x21586830, 0x74415c09, 0xe161e197, 0xe125e12d, 0xe105e0ee, 0xe0b3e0f0, 
+    0xe05fe069, 0xe04ae053, 0xe03ee044, 0xe034e03a, 0x7c60e031, 0xd2112802, 0x29017cd1, 0x7c91d81c, 
+    0xd1012900, 0xd09f2800, 0x200149dc, 0x7c607548, 0x20027610, 0x7c60e019, 0xd3032802, 0x43019900, 
+    0xe099b2c9, 0x29017cd1, 0x7c91d806, 0xd1062900, 0xf7ffe003, 0xbdfefe92, 0x2800e09b, 0x49cfd0fb, 
+    0x75482001, 0x76107c60, 0x74602003, 0xf988f7ff, 0xfaebf7fe, 0x5c60e155, 0x6830e01f, 0x8b8019c0, 
+    0xe14e5460, 0x5c4048c5, 0x6830e017, 0x8b8019c0, 0xe01e4ac2, 0x78401860, 0x5c600202, 0x6830e00c, 
+    0x8b8019c0, 0x0a005460, 0x70481861, 0x48bbe139, 0x78521842, 0x02125c40, 0x21034310, 0x8a8a0709, 
+    0xe737828d, 0x19c06830, 0x4ab48b80, 0x18540a03, 0x54507063, 0x7c60e125, 0xd2422802, 0xd00f2900, 
+    0xd0212901, 0xd1b62902, 0x49ab48ac, 0x600d7545, 0x814121ff, 0x1c498101, 0xf00448a9, 0xe02cfd2f, 
+    0x95002300, 0x2111461a, 0x95012002, 0xfc1df004, 0x200149a2, 0x89487548, 0x28ff8108, 0x1c40d002, 
+    0xe0fe8108, 0xe7fb2000, 0x489d4a9c, 0x89538911, 0x42995c40, 0x21ffd103, 0x43083101, 0x29ffe003, 
+    0x1c49d00d, 0x21038111, 0x8a8a0709, 0x6832828d, 0x19d2b2c1, 0x0a008391, 0x2001d055, 0x2100e06f, 
+    0x2100e7f0, 0xe7742005, 0x46847c60, 0xd3052802, 0x46619800, 0xb2c14308, 0xe76a200c, 0xd5050748, 
+    0x48886833, 0x8e5b181b, 0xd00507db, 0x28017cd0, 0x2102d909, 0xe75c200d, 0x18086831, 0x07c18e40, 
+    0x20080fc9, 0x7c90e755, 0xd1032800, 0x28004660, 0xe750d100, 0x20014b79, 0x7c607558, 0x20047610, 
+    0x75e17460, 0xfa6ef7ff, 0x07002003, 0x82858a81, 0x68004870, 0xe6ad8cc0, 0x4e6e2001, 0xe6f67250, 
+    0x7da18890, 0x486e1841, 0x21035c40, 0x8a8a0709, 0x6831828d, 0x838819c9, 0x28ff7da0, 0x2000d301, 
+    0x1c40e000, 0xe08c75a0, 0x7da08891, 0x180b4a64, 0x28ff5cd3, 0x2000d301, 0x1c40e000, 0x75a0b2c0, 
+    0x5c511809, 0xd30128ff, 0xe0002000, 0x75a01c40, 0x07002003, 0x82858a82, 0x43080218, 0xf7ffe67a, 
+    0xe708fd8e, 0x07002003, 0x82858a81, 0xfdbaf7ff, 0x9801e670, 0x70414e4f, 0x0f400648, 0xd0172801, 
+    0xd0032802, 0xd0352805, 0xd1ea2806, 0x28027c60, 0xe6e3d300, 0x29007c91, 0x2800d101, 0x4947d0e1, 
+    0x75482001, 0x76117c61, 0xf7fe7460, 0xe048fdd3, 0x28007c60, 0x2006d047, 0xf7fe7460, 0xe040fe67, 
+    0xf7ff82a5, 0x6830f807, 0x31404601, 0x74427e0a, 0x704530a0, 0xe034760d, 0x19c06830, 0x99018b40, 
+    0x70480a00, 0x06404e33, 0xd0120f40, 0xd0212801, 0xd1b62802, 0x28027c60, 0x482fd3e2, 0x60054f2f, 
+    0x817820ff, 0x1c418138, 0xf004482d, 0x757dfc37, 0x7c60e7d6, 0xd2bc2802, 0x29007c91, 0x2800d101, 
+    0x4926d09f, 0x75482001, 0x76117c61, 0xf7fe7460, 0xe006fff8, 0x28007c60, 0x2007d005, 0xf7fe7460, 
+    0x2000fff9, 0x9800e78b, 0x2001b2c1, 0xb570e691, 0xfa39f001, 0x20004917, 0x4918680a, 0x46138610, 
+    0x33808650, 0x46147298, 0x344072d8, 0x72607220, 0x72e072a0, 0x73d87320, 0x7f8973a0, 0x461173e1, 
+    0x31607420, 0x711875c8, 0x75207158, 0x710875a0, 0x72587148, 0x855077e0, 0x71c87188, 0x85907208, 
+    0x724885d0, 0x74c87508, 0x75887548, 0x76887648, 0xe00976c8, 0x20000090, 0x20000088, 0x20000200, 
+    0x20000100, 0x0001a180, 0x75987708, 0x25017618, 0x806075dd, 0x76987658, 0x825076d8, 0x73907350, 
+    0x741073d0, 0x77887748, 0x701877c8, 0x71987608, 0x74188690, 0x75908290, 0x831075d0, 0xbd708350, 
+    0xf7ffb510, 0xf7fffbf5, 0x48f7ffa2, 0x79806800, 0xd10b07c0, 0x07002003, 0x210f8a81, 0x828143c9, 
+    0x200049f2, 0x4af26809, 0x80481889, 0x20012100, 0xfb45f001, 0x20022100, 0xfb41f001, 0x20032100, 
+    0xfb3df001, 0x20042100, 0xfb39f001, 0x20052100, 0xfb35f001, 0x48e5e4c5, 0x49e56800, 0x184031c0, 
+    0x49e48a80, 0x0f020600, 0x1ed27c08, 0xd3022a0b, 0x43102210, 0x22efe001, 0x74084010, 0xb5104770, 
+    0x07002003, 0x49dc8a81, 0x49d88281, 0x680c2301, 0x4ad702db, 0x18a43280, 0x8a838523, 0x43db2340, 
+    0x680c8283, 0x18a42340, 0x4bd28423, 0x2b007bdb, 0x8a83d122, 0x82834bd1, 0x680c2301, 0x18a2035b, 
+    0x8a8284d3, 0x43d22278, 0x680c8282, 0x4ac82308, 0x18a432c0, 0x8a838023, 0x82834bc9, 0x680c2337, 
+    0x18a4019b, 0x8a8380e3, 0x33204bc4, 0x20198283, 0x01c06809, 0x81c81889, 0x4770e473, 0xf004b570, 
+    0x4abcf830, 0x290088d1, 0x08cbd014, 0x18081ac0, 0x7b1080d0, 0x28142101, 0x4bbad20e, 0x43434dba, 
+    0x129b195b, 0x1c5b88d4, 0x429c105b, 0x74d1dc04, 0xe00f1c40, 0xe7eb00c0, 0xd00d2800, 0x4db34bb1, 
+    0x195b4343, 0x88d4129b, 0x105b1c5b, 0xdb03429c, 0x1e4074d1, 0xbd707310, 0x74d02000, 0xb570bd70, 
+    0x48a42124, 0xfb0af004, 0x20264ca2, 0x48a88020, 0x200880a0, 0x200b73a0, 0x73202600, 0x752674e6, 
+    0xf0037566, 0x00c0ffee, 0x250080e0, 0xffb6f7ff, 0xb2ed1c6d, 0xd3f92d08, 0x68004894, 0x31c04994, 
+    0x8fc01840, 0x07002128, 0x73e00f00, 0x20017426, 0x75a17360, 0x75e12104, 0x76212110, 0x76a07666, 
+    0x76e02002, 0x77202003, 0x77602024, 0x77a02020, 0x77e62005, 0x842001c0, 0x0180200b, 0x21f88460, 
+    0xf004488c, 0x488cfacb, 0x20ff6006, 0x81208160, 0x48881c41, 0xfac2f004, 0xb510bd70, 0x2100487a, 
+    0x230a6800, 0x80014602, 0x71933240, 0x72c171d1, 0x73017281, 0x73817341, 0x73c17401, 0x74418241, 
+    0x71017491, 0x71c17181, 0x72417201, 0x22027741, 0x22017142, 0x30807082, 0xf7ff7201, 0xe709fe88, 
+    0x486cb530, 0x28007bc0, 0x4a68d123, 0x4b686810, 0x18c033c0, 0x210f8a80, 0x0f000600, 0x20031a09, 
+    0x8a840700, 0x82844c6d, 0x6815028c, 0x18ed430c, 0x8a8484ac, 0x43e4240f, 0x68148284, 0x859918e3, 
+    0x212a8a81, 0x828143c9, 0x202a6811, 0x18894a64, 0xbd308188, 0x4d55b5f8, 0x48616829, 0x180830c0, 
+    0x4f518ac0, 0x68380701, 0x30400f09, 0x485174c1, 0x7bc04e4f, 0x36802403, 0x28000724, 0x6828d12e, 
+    0x33c04b4b, 0x8a8018c0, 0x0600210f, 0x1a080f00, 0x49548aa1, 0x682a82a1, 0x19920301, 0x8aa18511, 
+    0x43c9210f, 0x682982a1, 0x85481989, 0x21038aa1, 0x82a143c9, 0x2103682a, 0x86111992, 0x21788aa1, 
+    0x82a143c9, 0x00c06829, 0x800818c9, 0x20028aa0, 0x82a043c0, 0x20026829, 0x824818c9, 0xff74f7fc, 
+    0x4b416838, 0x4a327801, 0x2100074f, 0xdb092f00, 0x5c3f2753, 0xd10b2f00, 0x783f4f2e, 0x0eff06bf, 
+    0xd3052f06, 0x82a38aa7, 0x189b682b, 0xe0058019, 0x82a38aa7, 0x2304682f, 0x803b18bf, 0x075b7803, 
+    0x2353d412, 0x2b005c1b, 0x4b22d10e, 0x069b781b, 0x2b0e0edb, 0x8aa3d908, 0x43db2380, 0x682f82a3, 
+    0x18ba2380, 0xe0068013, 0x23808aa3, 0x82a343db, 0x189a682b, 0x78028011, 0xd5470752, 0x32404602, 
+    0x2b007cd3, 0x4b13d142, 0x069b781b, 0x469c0edb, 0xd90d2b1a, 0x23078aa3, 0x82a343db, 0x2306682f, 
+    0x84bb19bf, 0x075b7803, 0x7cd2d530, 0xd12d2a00, 0x2a164662, 0x8aa2d92a, 0x43d22202, 0x682b82a2, 
+    0x199b2202, 0xe028859a, 0x20000090, 0x20000084, 0x0001a080, 0x20000200, 0x0000f7ff, 0x0000dfff, 
+    0x0000c03f, 0xfffc5699, 0x00d3f7e6, 0x00da605a, 0x0000d102, 0x20000100, 0x20000088, 0x0000c3f0, 
+    0x0001a240, 0x00000fff, 0x0000fffb, 0x22028aa2, 0x82a243d2, 0x1992682a, 0x78028591, 0x4afc0753, 
+    0x82a28aa3, 0x2201d505, 0x02d2682b, 0x855a199b, 0x682ae002, 0x85511992, 0x32ff682a, 0x8d923201, 
+    0x07924ef4, 0x46020fd3, 0x75533280, 0x4ff22b00, 0x82a68aa3, 0x231bd002, 0xe001015b, 0x015b2311, 
+    0x19f6682e, 0x7d528033, 0xd0092a00, 0x4aeb8aa2, 0x230782a2, 0x02db682e, 0x3a404ae7, 0x815318b2, 
+    0x4ae78aa2, 0x682f82a2, 0x260d2301, 0x19bf0376, 0x3040807b, 0x48df7cc7, 0x30e01ebf, 0xf004003b, 
+    0x0508fa49, 0x0a0a0505, 0x120a0505, 0x82a08aa3, 0x300120ff, 0x8aa3e003, 0x200182a0, 0x682b0240, 
+    0x80d8199b, 0x8aa3e004, 0x682882a0, 0x80c11980, 0x48d4682b, 0x8ec01818, 0x0f000700, 0xd00e2801, 
+    0x8aa02804, 0x82a048d0, 0x48d0682b, 0x181bd010, 0x8aa38019, 0x682a82a2, 0x80411810, 0x8aa0bdf8, 
+    0x82a048c9, 0x2380682e, 0x183648c8, 0xe7f08033, 0x8019181b, 0x82a28aa1, 0xe7ec2101, 0x201fb5f8, 
+    0xfd96f001, 0xfb1af001, 0x26034dc1, 0x31606829, 0x07367008, 0x20098ab0, 0x82b043c0, 0x210848bd, 
+    0x4cba6800, 0x19003cc0, 0x20008001, 0xfea8f7fd, 0x22006828, 0x31404601, 0x4db77ccf, 0xf004003b, 
+    0x0d09f9e9, 0x3406340b, 0x06340634, 0x232a0034, 0x231573cb, 0xe00d740b, 0xe00a73ca, 0x061f7903, 
+    0x065bd502, 0xe0030e5b, 0x075b7803, 0x7f6bd51d, 0x740a73cb, 0x75c23060, 0x4fa5200f, 0xf7fe5608, 
+    0x6839f8f9, 0x56082050, 0xf8aef7fe, 0x78006838, 0xd5170740, 0xfe02f001, 0x78016838, 0xd5110749, 
+    0x7cc03040, 0xd0022801, 0x7fabe00c, 0x8ab0e7e0, 0x43c02030, 0x489782b0, 0x68002130, 0x3a404a93, 
+    0x84c11880, 0x20208ab0, 0x82b043c0, 0x20204991, 0x230d680a, 0x18d2035b, 0x68388410, 0x46032201, 
+    0x739a3340, 0x469c7fef, 0x063b4a8c, 0x8ab0d507, 0x067882b2, 0x0e406809, 0x80481909, 0x8807bdf8, 
+    0xd4fb063b, 0x07db7983, 0x077fd1f8, 0x2f002307, 0x2795da0f, 0x2f005c3f, 0x782fd00b, 0x0eff06bf, 
+    0xd9062f16, 0x82b28ab3, 0x220a680b, 0x805a191b, 0x8ab7e004, 0x680a82b2, 0x80531912, 0x7cd24662, 
+    0xd1db2a01, 0x06807800, 0x28020f80, 0x7828d0d6, 0x0ec00680, 0xd9d12816, 0x20078ab0, 0x82b043c0, 
+    0x20046809, 0x80881909, 0xb510bdf8, 0x68204c68, 0x78003060, 0xfcdcf001, 0x20616821, 0xf7fd5608, 
+    0x6821fdff, 0x31402000, 0x200f7388, 0xf7fe5608, 0x6821f871, 0x56082050, 0xf826f7fe, 0x07002003, 
+    0x21208a81, 0x828143c9, 0x2020495a, 0x220d6809, 0x18890352, 0x68208408, 0x30402101, 0xe4a97381, 
+    0x4d54b570, 0x4e566828, 0x8ec11980, 0x19806828, 0x048a8f00, 0x0f52054b, 0x18d20f5b, 0x08520689, 
+    0x18510e89, 0x0f530482, 0x0ed206c2, 0x0984189b, 0xd00007e4, 0x0544425b, 0x18a20f64, 0x07c00940, 
+    0x4252d000, 0x10431898, 0x19806828, 0x06808f40, 0x68281684, 0x8f401980, 0x16c20540, 0x19856828, 
+    0x5e28203a, 0x290012c0, 0x4249da00, 0xda002b00, 0x18c9425b, 0xda002c00, 0x19094264, 0xda002a00, 
+    0x18894252, 0xda002800, 0x18084240, 0xbd70b280, 0x4d30b5f0, 0x4a326828, 0x8ec11880, 0x18806828, 
+    0x682b8f00, 0x8f5b189b, 0x12db055b, 0x682b0c1c, 0x223a189b, 0x048b5e9a, 0x0f5b054e, 0x199b0f76, 
+    0x085b0689, 0x185e0e89, 0x06c30481, 0x0f490152, 0x0c120edb, 0x098718c9, 0xd00007ff, 0x05474249, 
+    0x18fb0f7f, 0x07c00940, 0x425bd000, 0x682918c8, 0x481b1043, 0x8f401808, 0x16810680, 0x185d0048, 
+    0x19404684, 0x4c120065, 0x68241940, 0x88241880, 0x06a7b200, 0x2f020fbf, 0x0764d109, 0x0058d507, 
+    0x18411980, 0x18084660, 0x18801940, 0xbdf0b200, 0x0000f7ff, 0x0000fc1f, 0x0001a180, 0x0000c7ff, 
+    0x0000fffe, 0x0001a300, 0xffffff7f, 0x0001a140, 0x20000090, 0x20000084, 0x20000200, 0x0000fff0, 
+    0x0001a040, 0xf7ffb500, 0x0081ff4b, 0x18080040, 0xbd00b280, 0x2200b500, 0xfd19f7fd, 0xda012800, 
+    0x22014240, 0x6809491f, 0x18c94b1f, 0x08c98809, 0x0fc907c9, 0x0040d002, 0xe002491c, 0x0040491b, 
+    0x5e083940, 0xd0012a00, 0xb2004240, 0xb510bd00, 0x07092103, 0x138a8a8a, 0x4a12828a, 0x68140680, 
+    0x48110dc3, 0x18243840, 0x8a8b82e3, 0x828b4b10, 0x1c596812, 0x82c11810, 0x06c2e40e, 0x21010ed2, 
+    0x09404091, 0x00804a0b, 0x60011880, 0x06c24770, 0x21010ed2, 0x4a074091, 0x00800940, 0x18803280, 
+    0x47706001, 0x20000084, 0x0001a080, 0x00007b4c, 0x00007fff, 0xe000e100, 0x49fdb570, 0x680a2500, 
+    0x31404611, 0x33604613, 0x774d75cd, 0x83d5731d, 0x8415461c, 0xd0092800, 0x43e4240f, 0xd0082801, 
+    0x28022300, 0x2803d01a, 0xe005d017, 0x77e5230f, 0x3280e002, 0x70154623, 0x570c2410, 0xd00d2802, 
+    0xd00b2803, 0x76cd764b, 0x76887e48, 0xf7fd4618, 0x4620fca7, 0xfed8f7fd, 0x240fbd70, 0xe7f2764c, 
+    0x4ce3b570, 0x68212500, 0x3240460a, 0x3360460b, 0x280075d5, 0x2801d007, 0x76d5d00c, 0xd01d2802, 
+    0xd0222803, 0x7bc8e00f, 0x76d608c6, 0x02007fdb, 0xe00718c0, 0x08c37c08, 0x76d3425b, 0x20800203, 
+    0x18185c40, 0x76958488, 0x5610201b, 0xfc78f7fd, 0x205a6821, 0xf7fd5608, 0xbd70fea7, 0x08c57b48, 
+    0x7695426d, 0x7f5b0200, 0x7b88e004, 0x769508c5, 0x02007f9b, 0x848818c0, 0xb5f0e7e6, 0x46944cc4, 
+    0x9a086824, 0x9f052501, 0x34609e06, 0xd0032a01, 0xdb162900, 0xe00a2101, 0xd0062900, 0x2b00da02, 
+    0xe00edc03, 0xdaf52b00, 0x73254660, 0x9a07e005, 0x1a404351, 0xb2402100, 0x42b07321, 0x4630dd04, 
+    0x2100e005, 0xe7f243c9, 0xda0142b8, 0x73254638, 0xb5f0bdf0, 0x0005b085, 0x201ed04c, 0x2d0143c0, 
+    0x2d03d001, 0x2200d046, 0x231e49a9, 0x24206809, 0x5f0c5ecb, 0x4323029b, 0x3440460c, 0x3b0f7ce6, 
+    0x4ea42e01, 0x4fa46836, 0x19f6d037, 0x83ce8e36, 0x68364ea0, 0x8e7619f6, 0x0db605b6, 0x261e840e, 
+    0x27205f8e, 0x02b65fcf, 0x2119433e, 0x56613e0f, 0x1c4e46b4, 0xd9012e02, 0x76611049, 0x275a7f61, 
+    0xb2ce1c49, 0x77664992, 0x2e056809, 0xd81d57cf, 0x56612119, 0x92012600, 0x90009102, 0x221b9603, 
+    0x463856a2, 0xf7ff4661, 0x4989ff88, 0x31406809, 0xe02375ce, 0x2000221f, 0x19f6e7b6, 0x83ce8d36, 
+    0x68364e84, 0x8d7619f6, 0xe7c7b2f6, 0x2e072101, 0x2619d812, 0x920157a6, 0x90009103, 0x221b9602, 
+    0x463856a2, 0xf7ff4661, 0x4979ff68, 0x6809226c, 0x31405c52, 0xe00175ca, 0x75e14638, 0x68214c74, 
+    0x7e8a3140, 0x768876ca, 0xd00a2d00, 0xd0082d01, 0xfdeaf7fd, 0x46016820, 0x7dc23040, 0xd0032a01, 
+    0xf7fde00f, 0xe7f5fbad, 0xd00d2d00, 0xd0132d01, 0x2d024a6a, 0xd0175682, 0xda002a00, 0x00d04252, 
+    0x20007388, 0xbdf0b005, 0x5682221a, 0xda002a00, 0x00d04252, 0xe7f473c8, 0x5682221a, 0xda002a00, 
+    0x00d04252, 0xe7ec7408, 0xda002a00, 0x00d04252, 0xe7e67348, 0x4e56b5f8, 0x68304604, 0x5c0b2153, 
+    0x49542500, 0x4a542b01, 0xd017680b, 0x8e1b189b, 0x680983c3, 0x8e491889, 0x0d890589, 0xf7fd8401, 
+    0x6831fb66, 0x3340460b, 0x2c0276d8, 0x2c03d00e, 0x2c01d00f, 0x2c00d010, 0xe012d011, 0x8d1b189b, 
+    0x680983c3, 0x8d491889, 0xe7e7b2c9, 0x5c452079, 0x207ae007, 0xe0045c45, 0x5c45207b, 0x207ce001, 
+    0x8bca5c45, 0x2a002000, 0x200ad005, 0x1052e00c, 0x840a1c40, 0x2220b240, 0x2a005e8a, 0xe007dcf7, 
+    0x1c401052, 0xb24083ca, 0x5e8a221e, 0xdcf72a00, 0xb2401f00, 0x01c08c8a, 0x10c008d2, 0x1a10271f, 
+    0x2c02023f, 0x2c03d005, 0x2c01d003, 0x2c00d001, 0x42b8d102, 0x4638dd00, 0x0c1604c2, 0x181200ea, 
+    0x2c02848e, 0x2c03d005, 0x2c01d003, 0x2c00d001, 0x42bad102, 0x463add00, 0x0c0004d0, 0x271f0542, 
+    0x427d0e12, 0xd00a2c00, 0xd0082c03, 0x42400ac0, 0xd0072c01, 0xd0112c02, 0xd00f2c03, 0x0ac0e019, 
+    0xd1f52c00, 0xdd01281f, 0xe01276df, 0xda0142a8, 0xe00e76dd, 0xd00c2800, 0xe00a76d8, 0xdd01281f, 
+    0xe006769f, 0xda0142a8, 0xe002769d, 0xd0002800, 0x20017698, 0x2c0075d8, 0x2c01d012, 0x2c02d016, 
+    0x0a30d01b, 0x31607388, 0x768a778e, 0xbdf82000, 0x20000090, 0x20000084, 0x0001a040, 0x0000001a, 
+    0x73c80a30, 0x77ce3160, 0xe7ef770a, 0x74080a30, 0x54462080, 0x76ca3160, 0x0a30e7e8, 0x31607348, 
+    0x764a774e, 0x2103e7e2, 0x8a8a0709, 0x43d222c0, 0x07c0828a, 0x01c10fc0, 0x43010180, 0x680048fe, 
+    0x18804afe, 0x477081c1, 0x2103b510, 0x8a8a0709, 0x828a138a, 0x221505c0, 0x02520dc0, 0x4af61883, 
+    0x48f66814, 0x82e31824, 0x4bf58a8b, 0x6812828b, 0x18101c59, 0xbd1082c1, 0x2103b510, 0x8a8a0709, 
+    0x828a138a, 0x220b05c0, 0x02920dc0, 0x4aea1883, 0x48ea6814, 0x82e31824, 0x4be98a8b, 0x6812828b, 
+    0x18101c59, 0xbd1082c1, 0x2103b510, 0x8a8a0709, 0x828a138a, 0x221305c0, 0x02520dc0, 0x4ade1883, 
+    0x48de6814, 0x82e31824, 0x4bdd8a8b, 0x6812828b, 0x18101c59, 0xbd1082c1, 0x2103b510, 0x8a8a0709, 
+    0x828a138a, 0x220505c0, 0x02d20dc0, 0x4ad21883, 0x48d26814, 0x82e31824, 0x4bd18a8b, 0x6812828b, 
+    0x18101c59, 0xbd1082c1, 0x2400b510, 0xdd062800, 0xf7ff4620, 0x4620ffe1, 0xffc6f7ff, 0x2800bd10, 
+    0xda054620, 0xffa8f7ff, 0xf7ff4620, 0xbd10ff8d, 0xfd27f7fd, 0xf7fd4620, 0xbd10fd0c, 0x4bc1b510, 
+    0x681b408a, 0x8e1c4002, 0x43144384, 0xbd10861c, 0x4bbcb510, 0x681b408a, 0x8e5c4002, 0x43144384, 
+    0xbd10865c, 0x4604b510, 0xfb8ef7fd, 0x07092103, 0x201f8a88, 0x828843c0, 0x06e248af, 0x0ed26803, 
+    0x0364240d, 0x855a191b, 0x4aaf8a8a, 0x4baf828a, 0x4aaa6804, 0x842318a4, 0x23ff8a8b, 0x2101828b, 
+    0x02896800, 0x84811880, 0xb510bd10, 0xf7fd4604, 0x2103fb6b, 0x8a880709, 0x43c0201f, 0x489e8288, 
+    0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x828a4a9d, 0x68042309, 0x4a98031b, 0x842318a4, 
+    0x23ff8a8b, 0x2101828b, 0x02896800, 0x84811880, 0xb510bd10, 0xf7fd4604, 0x2103fb47, 0x8a880709, 
+    0x43c0201f, 0x488c8288, 0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x3a204a8b, 0x4b8b828a, 
+    0x33146804, 0x18a44a85, 0x8a8b8423, 0x828b2300, 0x68044b87, 0x846318a4, 0x23ff8a8b, 0x2101828b, 
+    0x02896800, 0x84811880, 0x2800bd10, 0x43c0da00, 0x4770b280, 0x4c7bb5ff, 0x68204607, 0x9e092200, 
+    0x30609d0a, 0x29004694, 0xda04d003, 0xdc042b00, 0x2101e014, 0x2b00e019, 0x4608da0e, 0xffe5f7ff, 
+    0x46184601, 0xffe1f7ff, 0xd3004281, 0x68219f02, 0x31602001, 0xe0097308, 0xe0012101, 0x43c92100, 
+    0x43599b0b, 0xb24f1a79, 0x73012100, 0xdd0142af, 0xe002462f, 0xda0442b7, 0x68214637, 0x31602201, 
+    0x42af730a, 0x42b7d001, 0x2001d101, 0x68204684, 0x30604661, 0x72c17282, 0xb0044638, 0xb5f0bdf0, 
+    0x46a62404, 0x9d062701, 0x9e052400, 0x42a846bc, 0x42aadc36, 0x42b0dc34, 0x42b2db32, 0x9f07db30, 
+    0x425e424d, 0xd10e4287, 0xd0292900, 0xdd014290, 0x46841e60, 0xda002900, 0xb2084629, 0xda002b00, 
+    0xb2194633, 0x4297e010, 0x2b00d11a, 0x4282d018, 0x2000dd02, 0x468443c0, 0xda002b00, 0xb2184633, 
+    0xda002900, 0xb2094629, 0x23012200, 0x428803db, 0x1a09da08, 0x03c90064, 0xb26418c9, 0xe0081409, 
+    0xbdf02000, 0x1c640064, 0x03c01a40, 0xb26418c0, 0x1c521400, 0x4572b2d2, 0x1c64d9e9, 0x46611060, 
+    0xd1ee1c49, 0xb2404240, 0xb5f0bdf0, 0xb0874604, 0x90052001, 0x4f28482f, 0xdd082c00, 0x18096839, 
+    0x06898909, 0x6839168e, 0x88c01808, 0x6839e011, 0xda072c00, 0x89891809, 0x168e0689, 0x18086839, 
+    0xe0068940, 0x88891809, 0x168e0689, 0x18086839, 0x06808840, 0x481b1685, 0x46016800, 0x468c3140, 
+    0x29007f49, 0x683ad176, 0x18524914, 0x5e512128, 0x9103221f, 0x42519b05, 0x92019302, 0x231e9100, 
+    0x46605ec3, 0x56822218, 0x99034630, 0xff22f7ff, 0x480c9004, 0x6800216c, 0x29005c09, 0x221fd02f, 
+    0x9b044251, 0x92019302, 0x231e9100, 0x5ec32258, 0x46305682, 0xe00f9903, 0x20000084, 0x0001a040, 
+    0x00007fff, 0x20000090, 0x00000ff3, 0x0000a00c, 0x00002020, 0x0001a280, 0xff41f7ff, 0x48fe4601, 
+    0x6800225b, 0x54112c00, 0x3060dd02, 0xe0067441, 0xda022c00, 0x73c13060, 0x3060e001, 0x48f67341, 
+    0x46016800, 0x760e3140, 0x83c29a03, 0x7b003060, 0x2c007748, 0x9804dd03, 0xfe1ef7ff, 0x9804e007, 
+    0xda022c00, 0xfde8f7ff, 0xf7fde001, 0x4eeafb6a, 0x30606830, 0x29007b01, 0x2c00d025, 0x7a82dd0b, 
+    0x20202105, 0xfe3af7ff, 0x21056830, 0x7ac23060, 0xe0162020, 0x7a82e017, 0xda092c00, 0x20022101, 
+    0xfe2cf7ff, 0x21016830, 0x7ac23060, 0xe0082002, 0x20082103, 0xfe22f7ff, 0x21036830, 0x7ac23060, 
+    0xf7ff2008, 0x4ed4fe25, 0x46086831, 0x7f823040, 0xd1772a00, 0x4ad1683b, 0x222c189b, 0x231f5e9a, 
+    0x425a9203, 0x93019f05, 0x97029200, 0x22192320, 0x56825ecb, 0x99034628, 0xfe8cf7ff, 0x68304607, 
+    0x5c09216c, 0xd01c2900, 0x424a211f, 0x91019200, 0x23209702, 0x5ec32259, 0x46285682, 0xf7ff9903, 
+    0x4601febe, 0x6830225a, 0x54112c00, 0x3060dd02, 0xe0067481, 0xda022c00, 0x74013060, 0x3060e001, 
+    0x68307381, 0x31404601, 0x9a03764d, 0x30608402, 0x77887b00, 0xdd032c00, 0xf7ff4638, 0xe007fd85, 
+    0x46382c00, 0xf7ffda02, 0xe001fd4f, 0xfad1f7fd, 0x30606830, 0x29007b01, 0x2c00d024, 0x7a82dd0a, 
+    0x20102104, 0xfdbaf7ff, 0x21046830, 0x7ac23060, 0xe0152010, 0x2c007a82, 0x2100da09, 0xf7ff2001, 
+    0x6830fdad, 0x30602100, 0x20017ac2, 0x2102e008, 0xf7ff2004, 0x6830fda3, 0x30602102, 0x20047ac2, 
+    0xfda6f7ff, 0x30406830, 0x29007f41, 0x7f81d004, 0xd0012900, 0xe0002101, 0x75c12100, 0xbdf0b007, 
+    0x488db5f0, 0x68032707, 0x336043ff, 0x7b597c58, 0x1a4010fa, 0x42b8b240, 0x2101dc01, 0x2808e004, 
+    0x4611db01, 0x2100e000, 0x68204c85, 0x19804e85, 0x251e8900, 0x16800680, 0x43ed1840, 0xda0142a8, 
+    0xe0024628, 0xdd00281f, 0x7c99201f, 0x1ac97b9b, 0x42b9b249, 0x2201dc01, 0x2908e002, 0x2200da00, 
+    0x19896821, 0x068988c9, 0x188c1689, 0xda0142ac, 0xe002462c, 0xdd002c1f, 0xf7ff241f, 0x4620fd1d, 
+    0xfd02f7ff, 0x486cbdf0, 0x68002200, 0x460183c2, 0x31408402, 0x75ca754a, 0x764a760a, 0x76ca768a, 
+    0x778a774a, 0x5c092184, 0xd0012901, 0x84c28442, 0x85028482, 0xb5704770, 0x68204c5f, 0x7a813040, 
+    0xd05a2903, 0x43ed2500, 0xd01f2904, 0xd0372905, 0xf7ff2001, 0x2103fc98, 0x8a880709, 0x43c02010, 
+    0x49578288, 0x68092010, 0x32404a54, 0x80081889, 0xf7ff4628, 0xf7fffcf9, 0x2009ffc6, 0xfd22f7ff, 
+    0xff13f7fc, 0x21046820, 0x72813040, 0xff55f7fc, 0xd0452800, 0xf7ff4628, 0x6820fe28, 0x7dc03040, 
+    0xd0ed2800, 0xf7ff2000, 0xf7fffcdf, 0x2009ffac, 0xfd2bf7ff, 0xfef9f7fc, 0x21056820, 0x72813040, 
+    0xff3bf7fc, 0xd02b2800, 0xf7ff2000, 0x6820fe0e, 0x7dc03040, 0xd0ed2800, 0xf7fc2000, 0x2001ff11, 
+    0xfcc2f7ff, 0xff8ff7ff, 0xf7fd2009, 0xf7fcfdaf, 0x6820fedc, 0x30402103, 0xf7fc7281, 0x2800ff1e, 
+    0x2001d00e, 0xfdf1f7ff, 0x30406820, 0x28007dc0, 0xf7ffd0ed, 0x2000ff35, 0xfc35f7ff, 0xbd702000, 
+    0xbd702002, 0x4a26b5f0, 0x43ff271e, 0x6810261f, 0x1179b085, 0x18c44b21, 0x5e202030, 0xdd01281f, 
+    0xe00c0c4c, 0x42e02420, 0x460cda01, 0x6812e007, 0x18d20280, 0x05928e52, 0x43100d92, 0x4816b204, 
+    0x68022310, 0x30404610, 0x930356c3, 0x97009102, 0x23209601, 0x22185ed3, 0x46215682, 0xf7ff9803, 
+    0x4605fd19, 0x216c480c, 0x5c096800, 0xd0122900, 0x86810129, 0x96019700, 0x23209502, 0x5ec32258, 
+    0x46215682, 0xf7ff9803, 0x4601fd4a, 0x68004802, 0x18898e82, 0xe0078681, 0x20000090, 0x0001a040, 
+    0x20000084, 0x0001a280, 0x9a0348f9, 0x46016800, 0x760a3140, 0x30608404, 0x75c87b00, 0xf7fd4628, 
+    0xb005f8c3, 0xb5f8bdf0, 0x25034cf1, 0x072d6820, 0x7a803040, 0x4ff04eef, 0xd021280c, 0xff03f7ff, 
+    0x30406820, 0x76417c01, 0xfe71f7fc, 0x31406821, 0x20007688, 0xf8a8f7fd, 0xf7fc2000, 0x8aa8fe71, 
+    0x683a82ae, 0x200d2101, 0x18100340, 0x200980c1, 0xfc8ff7ff, 0xfe39f7fc, 0x210c6820, 0x72813040, 
+    0xfe7bf7fc, 0xd0072800, 0xff6cf7ff, 0x31406821, 0x28007dc8, 0xe004d002, 0xbdf82002, 0x28207d48, 
+    0x8aa8d3e8, 0x683b82ae, 0x200d2200, 0x18180340, 0x201980c2, 0xf7fd5608, 0x6821f877, 0x5608205a, 
+    0xfe3ef7fc, 0xbdf82000, 0x460db570, 0xf0030003, 0x0e06f981, 0x0a080604, 0x24080e0c, 0x2410e008, 
+    0x2420e006, 0x2440e004, 0x2480e002, 0x2400e000, 0xff9af7fc, 0x07002003, 0x211f8a81, 0x828143c9, 
+    0x06ea49bd, 0x0ed2680b, 0x036d250d, 0x855a195b, 0x4aba8a82, 0x680d8282, 0x4ab92320, 0x842b18ad, 
+    0x23008a83, 0x4bb78283, 0x18ad680d, 0x8a83846b, 0x828323ff, 0x02206809, 0x84881889, 0xb5f0bd70, 
+    0x05cf2203, 0x0dff0712, 0x4cab1396, 0x00034dac, 0xf940f003, 0x45044406, 0x44bbb6b1, 0xdd012946, 
+    0xe0012146, 0xdd02293f, 0x383f4608, 0x2000e000, 0xb2408a93, 0x039b2303, 0x05c38293, 0x0ddb2601, 
+    0x682702b6, 0x197f199e, 0x8a9682fe, 0x82964e9e, 0x1c766827, 0x82fe197f, 0x27038a97, 0x829703bf, 
+    0x19db117f, 0x197f6827, 0x8a9382fb, 0x82931e73, 0x195b6823, 0x8a9382de, 0x039b2303, 0x1a088293, 
+    0x682105c0, 0x30ff0dc0, 0x30ff1949, 0x82c83002, 0x1e708a90, 0x68208290, 0x82c61940, 0x460bbdf0, 
+    0x4248331f, 0xd9062b3e, 0xdb012900, 0xe000460b, 0x3b1f4603, 0x2300e000, 0xb25b8a97, 0x03b62603, 
+    0x05de8296, 0x27050df6, 0x4c7b027f, 0x19f746b4, 0x19766826, 0x8a9782f7, 0x82974f7b, 0x1c7f6826, 
+    0x82f71976, 0x27038a97, 0x829703bf, 0x113f4666, 0x682719f6, 0x82fe197f, 0x4f738a97, 0x68248297, 
+    0x19641c7f, 0x8a9482e7, 0x03a42403, 0x29008294, 0x4608db00, 0x05c01ac0, 0x0dc02301, 0x18c302db, 
+    0x68044865, 0x82e31964, 0x4b678a93, 0x68078293, 0x197f1c5c, 0x8a9682fc, 0x03b62603, 0x26058296, 
+    0x02b60fc9, 0x198e6807, 0x82fe197f, 0x82938a96, 0x19766806, 0x8a9682f4, 0x03b62603, 0x260b8296, 
+    0x19890276, 0x19766806, 0x8a9182f1, 0x68008293, 0x82c41940, 0x8a90bdf0, 0x20078296, 0xe0080240, 
+    0x82968a90, 0x03002001, 0x8a90e003, 0x20098296, 0x68210240, 0x19491838, 0x8a9082c8, 0x8290484a, 
+    0x1c406821, 0x82c81949, 0xb40fbdf0, 0xae08b5fe, 0x7bb44684, 0x7c357bf3, 0x26007c70, 0x96004627, 
+    0x2a009601, 0x461cd101, 0x2901463b, 0x1c49d002, 0xe018d00c, 0xd2012c07, 0xe00a1c64, 0xd0012b00, 
+    0xb2db1e5b, 0xd20e4285, 0xe00b1c6d, 0xd0022c00, 0xb2e41e64, 0x2b07e007, 0x1c5bd201, 0x2d00b2db, 
+    0x1e6dd001, 0x4668b2ed, 0x2a007105, 0x7084d011, 0xa90870c3, 0x46697b08, 0xa9087008, 0x46697b48, 
+    0x22067048, 0xf0024660, 0xbcfefeec, 0xb004bc08, 0x70c44718, 0xe7ec7083, 0x1ad3b5fe, 0x4d204c1e, 
+    0x2801b25e, 0x2802d005, 0x4611d07b, 0xfed7f7ff, 0x6820bdfe, 0x8ec01940, 0x0480466a, 0x71900f40, 
+    0x19406820, 0x05408ec0, 0x71d00f40, 0x19406820, 0x06808ec0, 0x72100e80, 0x7250203f, 0xd0022900, 
+    0xd12b2901, 0x8910e022, 0x22018010, 0xa8014631, 0xf7ff9b01, 0x4806ff8a, 0x30806800, 0x06c97a01, 
+    0x7b80d502, 0xd5190680, 0x79884669, 0xe01571c8, 0x20000090, 0x0000fffe, 0x20000084, 0x00008bd3, 
+    0x0001a040, 0x00002020, 0x00007fff, 0x80108910, 0x46312200, 0x9b01a801, 0xff67f7ff, 0x07002003, 
+    0x13818a81, 0x466b8281, 0x230179da, 0x18d2029b, 0x195b6823, 0x8a8282da, 0x82824afe, 0x1c566823, 
+    0x82de195b, 0x82818a83, 0x799b466b, 0x19db14c7, 0x197f6827, 0x8a8382fb, 0x68238282, 0x82de195b, 
+    0x82818a83, 0x7a19466b, 0x31ff6823, 0x31ff195b, 0x82d93102, 0x82828a81, 0x19406820, 0xbdfe82c6, 
+    0x6822e7ff, 0x181248ec, 0x466d8f12, 0x0fd20652, 0x6822712a, 0x8f121812, 0x0fd20692, 0x6822716a, 
+    0x8f121812, 0x0f530492, 0x682271ab, 0x8f121812, 0x0f520552, 0x682571ea, 0x8f001828, 0x06c0466d, 
+    0x72280ec0, 0x726f271f, 0x29002500, 0x2901d002, 0xe028d144, 0xd10442c3, 0xd1021c70, 0x46692001, 
+    0x466a7108, 0x00407910, 0x1c404240, 0xb2414370, 0x80108910, 0xa8012201, 0xf7ff9b01, 0x466afef6, 
+    0x7a107991, 0xd10042c1, 0x48cc7115, 0x30806800, 0x06d27a02, 0x7b80d502, 0xd51f0640, 0x71d1466a, 
+    0x71507910, 0x42c2e01a, 0x1c70d104, 0x2001d102, 0x71484669, 0x7950466a, 0x42400040, 0x43701c40, 
+    0x8910b241, 0x22008010, 0x9b01a801, 0xfecdf7ff, 0x79d0466a, 0x42c87a11, 0x7155d100, 0x07002003, 
+    0x13828a81, 0x466e8282, 0x230579f1, 0x6825025b, 0x49b118cb, 0x82eb186d, 0x4bae8a83, 0x68268283, 
+    0x18761c5d, 0x8a8682f5, 0x466e8282, 0x148779b6, 0x682719f6, 0x82fe187f, 0x82838a86, 0x18766826, 
+    0x8a8682f5, 0x466e8282, 0x112f7a36, 0x682719f6, 0x82fe187f, 0x82838a86, 0x18766826, 0x8a8682f5, 
+    0x466e8282, 0x27057936, 0x19f602bf, 0x187f6827, 0x8a8682fe, 0x68268283, 0x82f51876, 0x82828a86, 
+    0x7972466e, 0x0276260b, 0x68261992, 0x82f21876, 0x82838a82, 0x18406820, 0xe74082c5, 0x68004890, 
+    0x1840498d, 0x06808e80, 0x47700e80, 0x488bb5f3, 0x6800b087, 0x30409005, 0x7cc09004, 0x28014e86, 
+    0x9805d01a, 0x7a013080, 0xd51b06c9, 0x29019907, 0x2902d002, 0xe015d003, 0x06807b80, 0x7b80e001, 
+    0x28000640, 0x9808db0e, 0xd0052800, 0x6800487c, 0x202c1981, 0xe00a5e08, 0x68004879, 0x20281981, 
+    0xe0045e08, 0x68004876, 0x20301981, 0x99075e08, 0x43ed250e, 0xf002000b, 0x7306fead, 0x645a2304, 
+    0x9908736b, 0xd00e2900, 0x680a496d, 0x8ed21992, 0x05526809, 0x19890f52, 0x06898ec9, 0x18540e89, 
+    0x27462500, 0x4a66e05f, 0x19896811, 0x68128ec9, 0x0f490489, 0x8ed21992, 0x0e920692, 0xe7ef188c, 
+    0x29009908, 0x680a495e, 0x1992d013, 0x09528f12, 0x0fd207d2, 0xd01b680a, 0x8f121992, 0x07520a12, 
+    0x0f526809, 0x8f091989, 0x0ec906c9, 0x424c1851, 0x1992e019, 0x09928f12, 0x0fd207d2, 0xd003680a, 
+    0x8f121992, 0xe7ea0ad2, 0x8f121992, 0xe0020ad2, 0x8f121992, 0x07520a12, 0x0f526809, 0x8f091989, 
+    0x0ec906c9, 0x25251854, 0x272643ed, 0x4944e01b, 0x19896809, 0x251e8f49, 0x168c0689, 0x271f43ed, 
+    0x493fe011, 0x19896809, 0x05498f49, 0xe00516cc, 0x6809493b, 0x223a1989, 0x12d45e8a, 0xe002270f, 
+    0x46252400, 0x99044627, 0x764c2c00, 0xdb03d002, 0xe0032101, 0xe0012100, 0x43c92100, 0xb2001a40, 
+    0x98049003, 0x28007d40, 0x2000d015, 0x950043c0, 0x98059002, 0x23209701, 0x98045ec3, 0x56822218, 
+    0x99034620, 0xf926f7ff, 0x48244604, 0x6800216c, 0x30405c09, 0x980775c1, 0xd10b2801, 0xd10442ac, 
+    0x1c419803, 0x2101da01, 0x2100e000, 0x6800481b, 0x71413080, 0x68004819, 0x7d813040, 0xd0022901, 
+    0x28037d00, 0x9807d106, 0xd0042801, 0xd0052802, 0xd0032803, 0x42bce096, 0xe093d004, 0xd00142bc, 
+    0xd17d42ac, 0x07002003, 0x21018a81, 0x828143c9, 0x20014d0b, 0x220d6829, 0x18890352, 0x46018648, 
+    0xf002201c, 0x9808fc58, 0x68282800, 0x1980d027, 0xe0078ec0, 0x00007fff, 0x0001a040, 0x20000090, 
+    0x20000084, 0x68290540, 0x19890f40, 0x06898ec9, 0x18410e89, 0x19806828, 0x09408f00, 0x0fc007c0, 
+    0xd0266828, 0x8f001980, 0x07400a00, 0x0f40682a, 0x8f121992, 0x0ed206d2, 0x42401880, 0x1980e024, 
+    0x68298ec0, 0x0f400480, 0x8ec91989, 0x0e890689, 0x68281841, 0x8f001980, 0x07c00980, 0x68280fc0, 
+    0x1980d003, 0x0ac08f00, 0x1980e7df, 0x0ac08f00, 0x1980e002, 0x0a008f00, 0x682a0740, 0x19920f40, 
+    0x06d28f12, 0x18800ed2, 0x0c000600, 0x68284301, 0x8f401980, 0x06802603, 0x06001680, 0x43010a00, 
+    0x23009101, 0x96004632, 0x20012112, 0xfb7df002, 0xfe84f7ff, 0x02006829, 0x18894afe, 0xe0008849, 
+    0x0709e010, 0x43080f09, 0x230049fb, 0x22036809, 0x7bc93140, 0x04099600, 0x90014308, 0x20012113, 
+    0xfb63f002, 0x68284df4, 0x7cc13040, 0xd0112901, 0x56c32319, 0x99084622, 0xf7ff9807, 0x6828fd1d, 
+    0x84019903, 0x7e413040, 0x7d417601, 0x75411c49, 0xbdf0b009, 0x98074621, 0xfbf1f7ff, 0xb510e7ef, 
+    0x07092103, 0x138a8a8a, 0x05c0828a, 0x0dc02217, 0x18830252, 0x68144ae1, 0x384048de, 0x82e31824, 
+    0x4bdf8a8b, 0x6812828b, 0x18101c59, 0xbd1082c1, 0x48d9b5fe, 0x68014fd7, 0x4608233e, 0x7cc43040, 
+    0x223f43db, 0x3f402501, 0x2c004ed4, 0x2c01d001, 0x6834d021, 0x243019e7, 0x68365f3c, 0x19f64fd1, 
+    0x950289f6, 0x92019300, 0x23200676, 0x16772218, 0x56825ecb, 0x46214dc8, 0xf7ff4638, 0x4606f80b, 
+    0x46016828, 0x760f3140, 0x30608404, 0x75ca7b02, 0xd0052a01, 0x6834e010, 0x242c19e7, 0xe7dc5f3c, 
+    0x21067a82, 0xf7fe2040, 0x6828ff69, 0x30602106, 0x20407ac2, 0xff6cf7fe, 0xf7ff4630, 0x363effa0, 
+    0x2e7c6828, 0x3040d904, 0x220279c1, 0xe0034311, 0x79c13040, 0x401122fd, 0xe52071c1, 0x4caeb510, 
+    0x6820214a, 0x290a5c09, 0x3080d016, 0x07807b40, 0x2000d41d, 0xff83f7ff, 0x30406820, 0x28017cc0, 
+    0xf7ffd815, 0x2010f9f0, 0xff4cf7fe, 0xf93df7fc, 0x210a6820, 0x72813040, 0xf97ff7fc, 0xd0082800, 
+    0xff86f7ff, 0x30406820, 0x28007dc0, 0x2000d0ee, 0x2002bd10, 0xb510bd10, 0x68204c97, 0x30404601, 
+    0x2a0e7a82, 0x3180d011, 0x07897b49, 0x7cc0d418, 0xd8152801, 0xf9c7f7ff, 0xf7fe2010, 0xf7fcff23, 
+    0x6820f914, 0x3040210e, 0xf7fc7281, 0x2800f956, 0xf7ffd00c, 0x6820ff5d, 0x7dc03040, 0xd0ee2800, 
+    0x212f6820, 0x72813040, 0xbd102000, 0xbd102002, 0x281fb510, 0x201fd901, 0xb241e003, 0xda002900, 
+    0xf7fe2000, 0xbd10fc14, 0x4604b510, 0xfa8cf7fc, 0x07092103, 0x201f8a88, 0x828843c0, 0x06e24877, 
+    0x0ed26803, 0x0364240d, 0x855a191b, 0x4a768a8a, 0x4b76828a, 0x4a6f6804, 0x18a43a40, 0x8a8b8423, 
+    0x828b2300, 0x68044b72, 0x846318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 0x84811880, 0xb510bd10, 
+    0xf7fc4604, 0x2103fa61, 0x8a880709, 0x43c0201f, 0x48628288, 0x680306e2, 0x240d0ed2, 0x191b0364, 
+    0x8a8a855a, 0x828a4a63, 0x68042309, 0x4a59029b, 0x18a43a40, 0x8a8b8423, 0x828b2300, 0x68044b5c, 
+    0x18a43340, 0x8a8b8463, 0x828b23ff, 0x68002107, 0x188002c9, 0xbd108481, 0x4604b570, 0xfa34f7fc, 
+    0x07092103, 0x201f8a88, 0x828843c0, 0x06e3484b, 0x0edb6804, 0x0352220d, 0x856318a4, 0x4b488a8b, 
+    0x6804828b, 0x4d431c5b, 0x19643d40, 0x8a8b8423, 0x43db2380, 0x6800828b, 0x18802180, 0xbd708401, 
+    0x4a3eb510, 0x4b3b6810, 0x18c03b40, 0x68118f00, 0x0f400480, 0x8f0918c9, 0x0ec906c9, 0x68101841, 
+    0x8f0018c0, 0x07c00980, 0xd0000fc0, 0x68104249, 0x8f0018c0, 0x05406814, 0x18e40f40, 0x68128f24, 
+    0x0ee406e4, 0x18d21900, 0x09528f12, 0x0fd207d2, 0x4240d000, 0x10401808, 0xbd103811, 0x2003b5f0, 
+    0x8a810700, 0x8281492c, 0x13814a24, 0x4b216814, 0x18e43b40, 0x8a818021, 0x82864e28, 0x6809491e, 
+    0x7a0c3180, 0xd50206e4, 0x06a47b8c, 0x2401d501, 0x2400e000, 0x00642501, 0x681702ad, 0x18ff1964, 
+    0x8a84807c, 0x7a0c8286, 0xd50206e4, 0x06497b89, 0x2101d501, 0x2100e000, 0x68140049, 0x18e41949, 
+    0x8a8180a1, 0x1c894915, 0x68148281, 0x80e518e4, 0x82818a84, 0x18e46814, 0x8a848125, 0x68118281, 
+    0x814d18c9, 0x490e8a81, 0x48098281, 0x18c96811, 0xbdf08188, 0x0001a080, 0x20000090, 0x20000084, 
+    0x00007fff, 0x0001a280, 0x00008ff3, 0x0000300c, 0x00002020, 0x00008bf3, 0x00003fff, 0x000093fd, 
+    0x0000c0c0, 0x2103b570, 0x8a8a0709, 0x828a4afb, 0x48fb0282, 0x230d6804, 0x18e4035b, 0x8a8a8522, 
+    0x828a4af8, 0x25006806, 0x19364cf7, 0x4df78075, 0x3580682d, 0x07ed7bad, 0x8a8dd10d, 0x6805828a, 
+    0x192c1c52, 0x8a8a8062, 0x43d22240, 0x6800828a, 0x18c02140, 0xbd708401, 0x2103b5f0, 0x8a8a0709, 
+    0x828a4ae6, 0x48e60282, 0x270d6803, 0x19db037f, 0x8a8a851a, 0x828a4ae3, 0x24006805, 0x18ed4be2, 
+    0x8a8d806c, 0x6805828a, 0x80ac18ed, 0x828a8a8d, 0x18ed6805, 0x8a8d80ec, 0x6805828a, 0x812c18ed, 
+    0x828a8a8d, 0x18ed6805, 0x4cd8816c, 0x34806824, 0x07ee7ba5, 0xd1044dd6, 0x828a8a8e, 0x18f66806, 
+    0x7ba68075, 0xd40407b6, 0x828a8a8e, 0x18f66806, 0x7ba480b5, 0xd4040764, 0x828a8a8c, 0x18d26802, 
+    0x8a8a80d5, 0x43d22240, 0x6800828a, 0x19c02140, 0xe76e8401, 0x4ec5b5fe, 0x68304ac1, 0x460449c2, 
+    0x7cc33040, 0x2b016812, 0x1851d028, 0x46258e09, 0x356083e1, 0x84a17829, 0x22018c61, 0xb249231f, 
+    0x92029301, 0x22189100, 0x23205682, 0x2000211e, 0x5e615ee3, 0xf7fe5628, 0x6831fdcd, 0x460ab2c0, 
+    0x70103260, 0x3a204613, 0x46148c8d, 0x7b1a7615, 0x8bca75e2, 0xf7ff840a, 0xe5defe3b, 0x8d091851, 
+    0xb5fee7d5, 0x4aa64ea9, 0x4ba76831, 0x3140460c, 0x68127ccd, 0xd02d2d01, 0x8e1218d2, 0x1810231f, 
+    0x226183e0, 0x85205710, 0x43d22200, 0x93012500, 0x95009202, 0x568a2218, 0x211e2320, 0x5e615ee3, 
+    0xfd98f7fe, 0x460a6831, 0x70503260, 0x3a204613, 0x46178d0c, 0x7b1a7614, 0x8bca75fa, 0xf7fb840a, 
+    0x6830ff2f, 0x5c09216a, 0xd0062900, 0x30802101, 0xe5a27241, 0x8d1218d2, 0x3080e7d0, 0xe59c7245, 
+    0x4887b5fe, 0x48886801, 0x18083040, 0x4c878840, 0x68200702, 0x46070f12, 0x70ba3760, 0x212a8482, 
+    0x25015e41, 0x2b081d0b, 0x2356d803, 0x2b015c1b, 0x2200d022, 0x230f43d2, 0x93012600, 0x96009202, 
+    0x5ec3232c, 0x20022204, 0x563856ba, 0xfd52f7fe, 0xb2c16822, 0x30604610, 0x8c927081, 0x7102b2d2, 
+    0x2b017b03, 0x7186d001, 0x4291e008, 0x7185d101, 0x2102e004, 0xe0017181, 0x71bd713a, 0x8d416820, 
+    0x21568581, 0x29015c09, 0x4601d106, 0x798a3160, 0xd0012a01, 0x718a2202, 0x07092103, 0x220f8a8a, 
+    0x828a43d2, 0x78813060, 0x6802485d, 0x3040485e, 0x80411810, 0xb5f8e541, 0x25014c5c, 0x46016820, 
+    0x7ccb3140, 0x32604602, 0xd0042b00, 0xd1062b01, 0x075b7803, 0x238dd503, 0x075b5c1b, 0x7215d501, 
+    0x7800e066, 0x20050742, 0x77482a00, 0xf7feda03, 0x6821f979, 0xf7fe8448, 0x4a4cf97d, 0x84c86811, 
+    0xfafcf7ff, 0x46046812, 0x31604611, 0x78107008, 0xd5400740, 0x33804613, 0x28007958, 0x2000d005, 
+    0x28005608, 0x1c60da01, 0x2026e01a, 0x5e108c56, 0x4f4046b4, 0x8c381986, 0x428646b6, 0x7a58da08, 
+    0xd1052800, 0x367626ff, 0xd20145b4, 0xd3ea2c1f, 0x45b68c7e, 0x7a58dc23, 0xd1202800, 0x1e60e001, 
+    0x4e327008, 0xf7ff7808, 0x6830fd43, 0x30604602, 0x42a17801, 0x7a03d01b, 0xd0182b01, 0x42a12502, 
+    0x2b04d91a, 0x3240d016, 0x2a017d92, 0x2203d012, 0x1b087202, 0x2089e01a, 0x28005c80, 0x3240d004, 
+    0x42947f52, 0xe7dcd8db, 0xd3bc2c1f, 0x7205e7d9, 0xbdf82000, 0xe7ec7205, 0xd0092b03, 0x7d923240, 
+    0xd0052a01, 0x72022204, 0x42401a60, 0xbdf8b240, 0xe7f97205, 0x4604b510, 0xffa6f7fb, 0x07092103, 
+    0x201f8a88, 0x828843c0, 0x06e2480d, 0x0ed26803, 0x0364240d, 0x855a191b, 0x4a0f8a8a, 0x2309828a, 
+    0x029b6804, 0x18a44a08, 0x8a8b8423, 0x828b2300, 0x6800490a, 0x84411880, 0x0000bd10, 0x000083ff, 
+    0x20000084, 0x00007fff, 0x0001a040, 0x20000090, 0x00008000, 0x20000200, 0x00008bff, 0x00002060, 
+    0x2101b530, 0xd804280d, 0x40811f80, 0x2001b2c9, 0x380ee003, 0xb2c94081, 0x22032002, 0x8a930712, 
+    0x829323ff, 0x020c4bfe, 0x49fe681d, 0x84ac186d, 0x240c8a94, 0x829443e4, 0x0080681a, 0x84081851, 
+    0xb5febd30, 0x68284df6, 0x36404ef6, 0x88801980, 0x07414ff5, 0x0f49683c, 0x30604620, 0x84a170c1, 
+    0x43db2300, 0x21002207, 0x92019302, 0x232e9100, 0x5ee32126, 0x5e612205, 0x46045682, 0x56202003, 
+    0xfc18f7fe, 0x4611683a, 0x70c83160, 0x71488c90, 0x71c87b08, 0x85d08cd0, 0x07002003, 0x22078a82, 
+    0x828243d2, 0x682978c8, 0x80881989, 0xb570e425, 0x25ff4cdd, 0x46016820, 0x7a8a3140, 0xd0172a17, 
+    0xd0222a18, 0x29007cc9, 0x7801d123, 0xd5200749, 0x7a403060, 0xd10f2800, 0xf7ff2009, 0x6820fd83, 
+    0x21692201, 0x2217540a, 0x540a214a, 0x72853080, 0xfda3f7fb, 0xd0122800, 0xf7ff2009, 0x6820fd9d, 
+    0x214a2218, 0x3080540a, 0xf7fb7285, 0x2800fd96, 0x6820d005, 0x30402119, 0x20007281, 0x2002bd70, 
+    0xb500bd70, 0x460249c0, 0x20006809, 0x00133180, 0xf8b0f002, 0x07041406, 0x14100d0a, 0x07c07b88, 
+    0x7b88e00a, 0xe0070780, 0x07407b88, 0x7b88e004, 0xe0010700, 0x06c07b88, 0x1c4017c0, 0xb5f8bd00, 
+    0x26014cb1, 0x25006820, 0x7a803040, 0xd0282820, 0xd0762821, 0xfdc7f7fe, 0x46016820, 0x7cc23040, 
+    0xd0022a00, 0xd04f2a01, 0x7809e082, 0xd57f0749, 0x76c57686, 0x30406820, 0xf7ff7e80, 0x2800ffc2, 
+    0x6820d01e, 0x30402106, 0xf7fe7e80, 0x6820feed, 0x75c53040, 0xf7fb7545, 0x6820fcf8, 0x30402120, 
+    0xf7fb7281, 0x2800fd3a, 0x6820d067, 0x7ec13040, 0xf7ff7e80, 0x6820f97b, 0x7dc03040, 0xd0ea2800, 
+    0x46026820, 0x7a113280, 0xd51006c9, 0x31404601, 0x56cb231a, 0xd1022b01, 0x06bf7b97, 0x2b02d504, 
+    0x7b92d105, 0xd4020652, 0x2a007eca, 0x4601d00a, 0x76cd3140, 0x1c527e8a, 0x215a768a, 0x29065641, 
+    0xe035dbb8, 0xe7f876ce, 0x07497809, 0x2102d530, 0x76c57681, 0x30406820, 0xf7ff7e80, 0x2800ff72, 
+    0x6820d01e, 0x30402106, 0xf7fe7e80, 0x6820fe9d, 0x75c53040, 0xf7fb7545, 0x6820fca8, 0x30402121, 
+    0xf7fb7281, 0x2800fcea, 0x6820d017, 0x7ec13040, 0xf7ff7e80, 0x6820f92b, 0x7dc03040, 0xd0ea2800, 
+    0x30406820, 0x1c897e81, 0x7681b249, 0xdbd12905, 0x30406820, 0x20007285, 0x2002bdf8, 0xb5f8bdf8, 
+    0x24004d61, 0x46026828, 0x7a813040, 0xd04d2910, 0x46287cc1, 0x30806800, 0xd0022900, 0xd0772901, 
+    0x7b40e079, 0xd17607c0, 0xfd1df7fe, 0x78006828, 0xd4060740, 0xf7ff200c, 0x6828fba2, 0x07407800, 
+    0x6828d52e, 0x31404601, 0x2a017d8a, 0x2185d00d, 0x29005c09, 0x2100d002, 0xe03643c9, 0xfee8f7fd, 
+    0x85486829, 0xfd5cf7ff, 0x7fc9e047, 0xd1002900, 0x21858544, 0x29005c09, 0x8d41d003, 0x85411e49, 
+    0xf7fde005, 0x6829fed5, 0x18808d4a, 0x68288548, 0x7fc13040, 0xb2c91c49, 0x290877c1, 0xe02cd028, 
+    0xfc33f7fb, 0x21106828, 0x72813040, 0xfc75f7fb, 0xd00c2800, 0x4b326828, 0x31404601, 0x4e317d8a, 
+    0xd0062a01, 0x19896819, 0x85418e09, 0x2002e7ca, 0x7fcabdf8, 0xd1002a00, 0x8d478544, 0x199b681b, 
+    0x1c528e1b, 0x854318fb, 0x77c8b2d0, 0xd1042808, 0xfd16f7ff, 0x30406828, 0x682877c4, 0x07497801, 
+    0x3060d40c, 0x28007980, 0xe007d097, 0xe002e000, 0x07c07b40, 0x2001d008, 0x71903260, 0x21336828, 
+    0x72813040, 0xbdf82000, 0xfc9df7fe, 0x46016828, 0x7d823040, 0xd0062a01, 0xfb72f7ff, 0x85486829, 
+    0xfceef7ff, 0x7fc0e015, 0xd1002800, 0xf7ff854c, 0x6829fb67, 0x18808d4a, 0x31408548, 0x1c407fc8, 
+    0x77c8b2c0, 0xd1042808, 0xfcdaf7ff, 0x30406828, 0x682877c4, 0x07497801, 0x3060d4d0, 0xe0057980, 
+    0x20000084, 0x0001a040, 0x20000090, 0xd0cd2800, 0xb510e7c4, 0x68204cfb, 0x31404601, 0x2a007cca, 
+    0x2a01d006, 0x7802d102, 0xd4010752, 0xe5c32000, 0x290f7a89, 0x3080d022, 0x06807b40, 0xf7fed42a, 
+    0x2000fc52, 0xfe00f7fb, 0xf7ff2009, 0x2003faad, 0x8a810700, 0x43c92120, 0x49eb8281, 0x68092020, 
+    0x18894aea, 0xf7fb8408, 0x6821fbb2, 0x70483160, 0xfb8bf7fb, 0x210f6820, 0x72813040, 0xfbcdf7fb, 
+    0xd00c2800, 0xf7ff203c, 0x6820fc4c, 0x7dc03040, 0xd0ed2800, 0x21326820, 0x72813040, 0x2002e7c6, 
+    0xb510e58a, 0x68204cd7, 0x31404601, 0x2a117a8a, 0x7cc9d021, 0xd1452900, 0x5c092188, 0xd14109c9, 
+    0x06897801, 0x29020f89, 0xf7fed03c, 0x200cfc0c, 0xfd50f7ff, 0x21006820, 0x210684c1, 0x75413040, 
+    0x30406820, 0xf7ff7d40, 0xf7fbfd7b, 0x6820fb4e, 0x30402111, 0xf7fb7281, 0x2800fb90, 0x49c2d011, 
+    0x4ac26808, 0x8e001880, 0xd0102800, 0x23266820, 0x68095ec3, 0x2130188a, 0x29005e51, 0x2101dd03, 
+    0x2002e003, 0x2100e548, 0x185943c9, 0x682084c1, 0x7d413040, 0xb2c91c49, 0x29167541, 0xf7ffd3d0, 
+    0xe002fd70, 0x30602101, 0x682071c1, 0x30402131, 0x20007281, 0xb5f8e530, 0x07002003, 0x49ac8a81, 
+    0x4ea98281, 0x68312001, 0x270d0240, 0x19c9037f, 0x68308048, 0x898019c0, 0xfa7ff001, 0xe0014605, 
+    0xd0082c00, 0x19c06830, 0x0a008980, 0x0fc007c0, 0x2401d001, 0x2400e000, 0xd0052c00, 0xfa6df001, 
+    0xb2801b40, 0xd3eb280b, 0x19c16830, 0x5e08200a, 0xd0032c00, 0xda012800, 0x43e42400, 0xbdf84620, 
+    0x4890b510, 0x30806800, 0x07807a00, 0x2000d501, 0xf7ffe4f2, 0x2800ffc0, 0x2003d0fa, 0x8a810700, 
+    0x43c92101, 0x49888281, 0x68092001, 0x0352220d, 0x86481889, 0x20174601, 0xfcbdf001, 0xe4db2001, 
+    0x4c80b5f0, 0x68202100, 0x78022503, 0x0752072d, 0x460f4e7d, 0xda2c2a00, 0x56822258, 0x68004620, 
+    0x30601dd3, 0xd8012b0e, 0xe0137087, 0x330f4613, 0xd8022b1e, 0x22042110, 0x4613e00b, 0x2b2e3317, 
+    0x2120d802, 0xe0042208, 0x2a3e321f, 0x2130d802, 0x7082220c, 0xf7fe2001, 0x8aa8fcc2, 0x43c0200f, 
+    0x682082a8, 0x30606831, 0x4a687880, 0x18893240, 0x68208048, 0x56412158, 0xda012900, 0xe0014865, 
+    0x03802003, 0x21018aa9, 0x683282a9, 0x200d0041, 0x18120340, 0x8aa98091, 0x82a9495f, 0x22806833, 
+    0x805a181b, 0x82a98aaa, 0x18086831, 0x20008047, 0xb570bdf0, 0x21884c53, 0x25006820, 0x30405c09, 
+    0x290007c9, 0x7605d003, 0x20007645, 0x7a81bd70, 0xd0012907, 0x76457605, 0xff3df7ff, 0xd0292800, 
+    0x31406821, 0x18107e0a, 0x7608b240, 0x301f7e4a, 0xb2521c52, 0x283e764a, 0x2a30d809, 0xf7ffda07, 
+    0x6820ff7f, 0x30402107, 0x20027281, 0x2003bd70, 0x8a810700, 0x43c92101, 0x493b8281, 0x68092001, 
+    0x0352220d, 0x86481889, 0x20174601, 0xfc23f001, 0xbd702001, 0x30406820, 0x4832e7c5, 0x68002153, 
+    0x7bc15c0a, 0x2a0008c9, 0x2901d007, 0x7c00d911, 0x280108c0, 0x2000d90d, 0x29014770, 0x7c01d909, 
+    0x290108c9, 0x7b41d905, 0x290108c9, 0x7b80d901, 0x2001e7ee, 0xb5f84770, 0x230f4d22, 0x4611682a, 
+    0x56cb3140, 0x7b90764b, 0x1b007b54, 0x84d01040, 0x24007d8e, 0xd0062e01, 0x05402601, 0x198005f6, 
+    0x1a181600, 0x4616e00d, 0x79b73680, 0xd3092f07, 0x280c71b4, 0x1e58dd01, 0x260ce003, 0xda0142f0, 
+    0x76481c58, 0x56082019, 0xda012818, 0xe0022018, 0xdd01282c, 0x7648202c, 0x56082019, 0xd02f4283, 
+    0x00db1ac3, 0x73c884d3, 0xfc74f7fb, 0x22266828, 0x5e827b81, 0x188923f8, 0x8501b209, 0xda0d2900, 
+    0xe00e8504, 0x20000090, 0x20000084, 0x0001a040, 0x0000f8ff, 0x00003fff, 0x0000ff7f, 0xdd0029f8, 
+    0x8d018503, 0x7b417381, 0xb2091a89, 0x29008501, 0x8504da01, 0x29f8e002, 0x8503dd00, 0x73418d01, 
+    0xbdf82000, 0x4cf8b510, 0x46016820, 0x7a823040, 0xd0232a12, 0x28007cc0, 0x2801d001, 0x3180d170, 
+    0x06407b48, 0xf7fed46c, 0xf7fbfa3e, 0x6821f9b0, 0x76083140, 0x77087c08, 0xf7fb200f, 0x6820fb42, 
+    0x30402100, 0x7d89e01d, 0xd0322901, 0xfcd4f7fd, 0xf97bf7fb, 0x21126820, 0x72813040, 0xf9bdf7fb, 
+    0xd0292800, 0x30406820, 0x7d407d81, 0xd0252901, 0xfd5ff7fd, 0x30406820, 0x29007dc1, 0x7d41d0e8, 
+    0x75411c49, 0x31406821, 0x7d487cca, 0xd0182a00, 0x42902202, 0x201cd3d7, 0xf7fb5608, 0x6821fbb5, 
+    0x56082058, 0xf97cf7fb, 0xff27f7ff, 0xd00a2801, 0xf7fde026, 0xe7cbfcd5, 0xe5982002, 0xfdeaf7fd, 
+    0x2204e7d8, 0x6820e7e5, 0x06407980, 0x2101d418, 0xf001201b, 0x6820fb30, 0x7a013080, 0x2101070a, 
+    0xdb0c2a00, 0x07002003, 0x1eca8a82, 0x48bf8282, 0x220d6800, 0x18800352, 0x20018641, 0x7401e577, 
+    0x23306820, 0x46024601, 0x728b3140, 0x79843080, 0x1c644603, 0x7cc87184, 0xd10a2800, 0x07418810, 
+    0x0600d407, 0x7b58d405, 0xd40206c0, 0xff03f7ff, 0x2000e55d, 0xb510e55b, 0xf7fb4604, 0x2103faa5, 
+    0x8a880709, 0x43c0201f, 0x48a88288, 0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x828a4aa4, 
+    0x68044ba4, 0x18a44aa4, 0x8a8b8423, 0x828b2300, 0x68044ba2, 0x846318a4, 0x23ff8a8b, 0x2101828b, 
+    0x02896800, 0x84811880, 0xb510e531, 0xf7fb4604, 0x2103fa7b, 0x8a880709, 0x43c0201f, 0x48938288, 
+    0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x828a4a8f, 0x68044b8f, 0x18a44a8f, 0x8a8b8423, 
+    0x828b2300, 0x68044b8e, 0x846318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 0x84811880, 0xb570e507, 
+    0x224d4c81, 0x25006820, 0x292d5611, 0x292ed02b, 0x2161d00e, 0x30805c09, 0x20147441, 0xff9bf7ff, 
+    0x84056820, 0xf8a1f7fb, 0x212e6820, 0x73413040, 0xf8e3f7fb, 0xd0312800, 0xf7ff2000, 0x6820f962, 
+    0x30404601, 0x2a007dc2, 0x3160d0ec, 0x77417849, 0xf7ff2014, 0x6820ffaa, 0xf7fb8405, 0x6820f886, 
+    0x3040212d, 0xf7fb7341, 0x2800f8c8, 0x2000d016, 0xf947f7ff, 0x46116822, 0x7dc83140, 0xd0ec2800, 
+    0x2461734d, 0x56a37f48, 0xdd004298, 0x77484618, 0x56102091, 0xf894f7fb, 0xbd702000, 0xbd702002, 
+    0x4860b5f8, 0x7f824c58, 0x46016820, 0x7a833040, 0xd02d2b23, 0xd03c2b24, 0x2b007cc3, 0x780bd102, 
+    0xd401075b, 0xbdf82000, 0x460b2500, 0x3380844d, 0x2e01791e, 0x7545d000, 0x2b00795b, 0x230fd00f, 
+    0x1a9d56c3, 0xdd012d00, 0x73c31e5b, 0x56c3230f, 0xd5011a9a, 0x73c31c5b, 0x84482001, 0x78c8e056, 
+    0xb2403808, 0xfa90f7fb, 0x21236820, 0x72813040, 0xff75f7ff, 0xd0d62802, 0x215d6820, 0x84c15c09, 
+    0x300878c0, 0xf7fbb240, 0x6820fa7f, 0x30402124, 0xf7ff7281, 0x2802ff64, 0x6822d0c5, 0x46102600, 
+    0x7f413040, 0x43f68cd3, 0xb2091ac9, 0x290084d1, 0x7d43d010, 0xd0312b00, 0xdb012900, 0xe0002301, 
+    0x251c4633, 0x2d005745, 0x2501db01, 0x4635e000, 0xd02342ab, 0x84532301, 0xdb012900, 0xe000460d, 
+    0x231c424d, 0x2b0056c3, 0x461fdb01, 0x425fe000, 0xdd0a42bd, 0x78d23280, 0xd01a2a01, 0x5682220f, 
+    0xdb002b00, 0x19922601, 0x770173c2, 0x200f6821, 0x56083140, 0xda0f2818, 0xe0102018, 0x78d23280, 
+    0xd0062a01, 0x5682220f, 0xdb002900, 0x1b922601, 0x220fe7ea, 0xe7e75682, 0xdd01282c, 0x73c8202c, 
+    0x5608200f, 0xfa66f7fb, 0x46016820, 0x7d423040, 0x1c524603, 0x7542b2d2, 0x28018c48, 0x2a10d014, 
+    0x2001d212, 0x0000e011, 0x20000090, 0x20000084, 0x00008ff3, 0x0000300c, 0x0001a040, 0x00006060, 
+    0x00002060, 0x20000200, 0x31802000, 0x20007108, 0xf7fb7298, 0xe745f9f9, 0x4efeb5fe, 0x30ff6830, 
+    0x8e453001, 0x80054668, 0x683006ac, 0x4ffa0ea4, 0x888019c0, 0x0fc00740, 0x0be8d10e, 0x05b8d00c, 
+    0x21048a81, 0x828143c9, 0x20046831, 0x808819c9, 0x20102101, 0xf96ff001, 0x680148f0, 0x30804608, 
+    0x42a27ec2, 0x2300d01b, 0x2c002201, 0x3142d00e, 0x7602800d, 0x07002003, 0x82838a81, 0x19c06830, 
+    0x23018003, 0x94019200, 0xe0042203, 0x930175c2, 0x23019200, 0x21092204, 0xf0012001, 0x48dff8d6, 
+    0x30806800, 0xbdfe76c4, 0x4cdab57c, 0x49da6820, 0x18403940, 0x23038cc0, 0x48d807c6, 0x6800071b, 
+    0x30802100, 0x4ad62e00, 0x8a9e4dd3, 0xd00b829a, 0x22026823, 0x809a195b, 0x75822201, 0x910075c2, 
+    0x46139101, 0xe019210b, 0x19526822, 0x68228091, 0x88921952, 0x0fd20752, 0x8a9ad10b, 0x68228299, 
+    0x88521952, 0x04526823, 0x195b0c52, 0x7581805a, 0x91007641, 0x22042301, 0x21219101, 0xf0012001, 
+    0xbd7cf894, 0x48bbb510, 0x49bb6800, 0x18403940, 0x08608d84, 0xd00107c0, 0xffb6f7ff, 0xd00107e0, 
+    0xff6af7ff, 0xb57cbd10, 0x46054eb4, 0x24016830, 0x7dc03080, 0xd1082800, 0x90012005, 0x22022300, 
+    0x94002115, 0xf0012001, 0x6831f870, 0x31802000, 0x22037608, 0x071275c8, 0x82908a93, 0x680048a5, 
+    0x18804aa5, 0x7e888005, 0xb2c21c40, 0xb2e8768a, 0x94002a01, 0xd0069001, 0x22022300, 0x2001210a, 
+    0xf853f001, 0x2300bd7c, 0x21202201, 0xb570e7f7, 0x68084998, 0x18804a98, 0x20018843, 0x430303c0, 
+    0x8a840590, 0x43e42401, 0x680d8284, 0x18ad2401, 0x8a8480ac, 0x82842400, 0x18806808, 0x21018043, 
+    0xf001200c, 0xbd70f8a8, 0xb510b40f, 0x07002003, 0x21ff8a81, 0x82810209, 0x8ee1466c, 0x0e0b07c9, 
+    0x07c98ea1, 0x430b0e49, 0x07c98e61, 0x430b0e89, 0x07c98e21, 0x430b0ec9, 0x07c98de1, 0x430b0f09, 
+    0x07c98da1, 0x430b0f49, 0x07c98d61, 0x430b0f89, 0x07c98d21, 0x430b0fc9, 0x680c4976, 0x025222d1, 
+    0x86e318a4, 0x23238a83, 0x8283029b, 0x8c63466c, 0x07db8c24, 0x0c5b07e4, 0x43230ca4, 0x8be4466c, 
+    0x0ce407e4, 0x466c4323, 0x07e48b64, 0x43230da4, 0x8b24466c, 0x0de407e4, 0x466c4323, 0x07e48ae4, 
+    0x43230e24, 0x8aa4466c, 0x0e6407e4, 0x466c4323, 0x07e48a64, 0x43230ea4, 0x8a24466c, 0x0ee407e4, 
+    0x466c4323, 0x07e489e4, 0x43230f24, 0x89a4466c, 0x0f6407e4, 0x466c4323, 0x07e48964, 0x43230fa4, 
+    0x8924466c, 0x0fe407e4, 0x680c4323, 0x872318a4, 0x23018a83, 0x828303db, 0x8ca3ac10, 0x07db8c64, 
+    0x0c5b07e4, 0x43230ca4, 0x8c24ac10, 0x0ce407e4, 0xac104323, 0x07e48be4, 0x43230d24, 0x8ba4ac10, 
+    0x0d6407e4, 0xac104323, 0x07e48b64, 0x43230da4, 0x8b24ac10, 0x0de407e4, 0xac104323, 0x07e48ae4, 
+    0x43230e24, 0x8aa4ac10, 0x0e6407e4, 0xac104323, 0x07e48a64, 0x43230ea4, 0x8a24ac10, 0x0ee407e4, 
+    0xac104323, 0x07e489e4, 0x43230f24, 0x89a4ac10, 0x0f6407e4, 0xac104323, 0x07e48964, 0x43230fa4, 
+    0x8924ac10, 0x0fe407e4, 0x680c4323, 0x876318a4, 0x230f8a83, 0x828343db, 0x8860ac10, 0x07c08823, 
+    0x0f0007db, 0x43180f5b, 0x8fe3466c, 0x07db6809, 0x43180f9b, 0x07db8fa3, 0x43180fdb, 0x87881889, 
+    0xbc08bc10, 0xb0042000, 0xb5ff4718, 0x001eb0ab, 0x46044615, 0x2700d018, 0xa8152120, 0xf850f001, 
+    0xa8262114, 0xf84cf001, 0x90002000, 0x90029001, 0xa81d2124, 0xf844f001, 0xd00a2f00, 0xdd052d12, 
+    0x1fad2006, 0xe006b2e9, 0xe7e52701, 0x2000b2e9, 0xb2e9e001, 0x9a2cb2f0, 0x1b1207c3, 0x1a121a52, 
+    0x2201b2d5, 0xd1012b00, 0xd3012806, 0x831aab20, 0xe0072802, 0x20000084, 0x0001a0c0, 0x20000090, 
+    0x0000fffd, 0xab20d301, 0x2804841a, 0xab20d304, 0x2806849a, 0x839ad300, 0x402048fe, 0xd0012801, 
+    0xdb012c0a, 0x8682a810, 0xdb012c02, 0x8182a820, 0xdb012c04, 0x80c2a820, 0xdb012c06, 0x8002a820, 
+    0xdb042c08, 0x8742a810, 0xdb002c0a, 0x07c88542, 0x2908d101, 0xa810d301, 0x29028282, 0xa810d301, 
+    0x29048382, 0xa810d301, 0x29068402, 0xa810d304, 0x29088482, 0x8302d300, 0x8d44a810, 0xd11f2c00, 
+    0xd00107c8, 0xd2192908, 0xd2172912, 0x8f40a810, 0xd1012801, 0xd211290a, 0x8800a820, 0xd1012801, 
+    0xd20b290c, 0x88c0a820, 0xd1012801, 0xd205290e, 0x8980a820, 0xd1032801, 0xd3012910, 0x8582a810, 
+    0x8f58ab10, 0x28009003, 0x290ad102, 0x879ad300, 0x8800a820, 0x28004684, 0x290cd103, 0xa820d301, 
+    0xa8208042, 0x2f0088c7, 0x290ed102, 0x8102d300, 0x2e008986, 0x2910d102, 0x81c2d300, 0x2b008e9b, 
+    0x2912d115, 0x9803d211, 0xd1012801, 0xd20c290a, 0x28014660, 0x290cd101, 0x2f01d207, 0x290ed101, 
+    0x2e01d203, 0x2910d103, 0xa810d301, 0x2d0086c2, 0x1e6dd07e, 0x07c1b2e8, 0x4669d001, 0x0840800a, 
+    0x07c1d0f6, 0x1e40d005, 0x06004669, 0x0e00804a, 0x4669d0ee, 0x29008889, 0x1e80d105, 0x06004669, 
+    0x0e00808a, 0x4669d0e4, 0x290088c9, 0x1e80d105, 0x06004669, 0x0e0080ca, 0x4669d0da, 0x29008849, 
+    0xa920d16f, 0x29008bc9, 0xa920d10d, 0x29008b89, 0x4669d109, 0x1e80804a, 0x0600a920, 0x0e0083ca, 
+    0x2a00d0c6, 0xa920d15d, 0x29008b49, 0xa920d10d, 0x29008b09, 0x4669d109, 0x1e80804a, 0x0600a920, 
+    0x0e00834a, 0x2a00d0b4, 0xa910d14b, 0x29008b49, 0xa910d10d, 0x29008b09, 0x4669d109, 0x1e80804a, 
+    0x0600a910, 0x0e00834a, 0x2a00d0a2, 0xa910d139, 0x29008ac9, 0xa910d10d, 0x29008a89, 0x4669d109, 
+    0x1e80804a, 0x0600a910, 0x0e0082ca, 0x2a00d090, 0xa910d127, 0x29008f09, 0x2b00d111, 0xa910d10f, 
+    0x29008ec9, 0x4669d10b, 0xa910804a, 0xe000870a, 0x1e80e11e, 0x0e000600, 0x2a00d08a, 0xa910d111, 
+    0x29008dc9, 0x2c00d10d, 0xa910d10b, 0x29008d89, 0x4669d107, 0x1e80804a, 0x0600a910, 0x0e0085ca, 
+    0xa920d08a, 0x29008cc9, 0xa920d109, 0x29008c89, 0x1e80d105, 0x0600a920, 0x0e0084ca, 0xa920d090, 
+    0x29008c49, 0xa920d109, 0x29008c09, 0x1e80d105, 0x0600a920, 0x0e00844a, 0xa910d094, 0x29008cc9, 
+    0xa910d109, 0x29008c89, 0x1e80d105, 0x0600a910, 0x0e0084ca, 0xa910d086, 0x29008c49, 0xa910d109, 
+    0x29008c09, 0x1e80d105, 0x0600a910, 0x0e00844a, 0xa910d08a, 0x29008bc9, 0xa910d109, 0x29008b89, 
+    0x1e80d105, 0x0600a910, 0x0e0083ca, 0xa920d08e, 0x29008a09, 0x2e00d10b, 0xa920d109, 0x290089c9, 
+    0x1e80d105, 0x0600a920, 0x0e00820a, 0xa920d094, 0x29008949, 0x2f00d10b, 0xa920d109, 0x29008909, 
+    0x1e80d105, 0x0600a920, 0x0e00814a, 0xa920d084, 0x29008889, 0x4661d10c, 0xd1092900, 0x8849a920, 
+    0xd1052900, 0xa9201e80, 0x808a0600, 0xd0870e00, 0x8fc9a910, 0xd10c2900, 0x29009903, 0xa910d109, 
+    0x29008f89, 0x1e80d105, 0x0600a910, 0x0e0087ca, 0xa920d07e, 0x29008bc9, 0xa920d13a, 0x29008b89, 
+    0xad20d136, 0x2d008b6d, 0xad20d10e, 0x2d008b2d, 0xad20d10a, 0x83ea1e80, 0x836a0600, 0xd0670e00, 
+    0xd1252a00, 0xd1232900, 0x8b6dad10, 0xd10f2d00, 0x8b2dad10, 0xd10b2d00, 0x83eaad20, 0xad101e80, 
+    0x836a0600, 0xd0530e00, 0xd1112a00, 0xd10f2900, 0x8ac9a910, 0xd10b2900, 0x8a89a910, 0xd1072900, 
+    0x83caa920, 0xa9101e80, 0x82ca0600, 0xd03f0e00, 0x8b49a920, 0xd12a2900, 0x8b09a920, 0xd1262900, 
+    0x8b6dad10, 0xd1122d00, 0x8b2dad10, 0xd10e2d00, 0xe001ad20, 0x80000001, 0x1e80836a, 0x0600ad10, 
+    0x0e00836a, 0x2a00d024, 0x2900d111, 0xa910d10f, 0x29008ac9, 0xa910d10b, 0x29008a89, 0xa920d107, 
+    0x1e80834a, 0x0600a910, 0x0e0082ca, 0xa910d010, 0x29008b49, 0xa910d114, 0x29008b09, 0xa910d110, 
+    0x29008ac9, 0xa910d10c, 0x29008a89, 0xe000d108, 0xa910e084, 0x834a1e80, 0x82ca0600, 0xd07d0e00, 
+    0x8bc9a920, 0xd12b2900, 0x8b89a920, 0xd1272900, 0x8f2dad10, 0xd1112d00, 0xd10f2b00, 0x8eedad10, 
+    0xd10b2d00, 0x83eaad20, 0xad101e80, 0x872a0600, 0xd0630e00, 0xd1132a00, 0xd1112900, 0x8dc9a910, 
+    0xd10d2900, 0xd10b2c00, 0x8d89a910, 0xd1072900, 0x83caa920, 0xa9101e80, 0x85ca0600, 0xd04d0e00, 
+    0x8b49a920, 0xd12b2900, 0x8b09a920, 0xd1272900, 0x8f2dad10, 0xd1112d00, 0xd10f2b00, 0x8eedad10, 
+    0xd10b2d00, 0x836aad20, 0xad101e80, 0x872a0600, 0xd0330e00, 0xd1132a00, 0xd1112900, 0x8dc9a910, 
+    0xd10d2900, 0xd10b2c00, 0x8d89a910, 0xd1072900, 0x834aa920, 0xa9101e80, 0x85ca0600, 0xd0740e00, 
+    0x8b49a910, 0xd12b2900, 0x8b09a910, 0xd1272900, 0x8f2dad10, 0xd1102d00, 0xd10e2b00, 0x8eedad10, 
+    0xd10a2d00, 0x1e80ad10, 0x0600836a, 0x0e00872a, 0x2a00d05b, 0x2900d114, 0xe000d112, 0xa910e055, 
+    0x29008dc9, 0x2c00d10c, 0xa910d10a, 0x29008d89, 0xa910d106, 0x834a1e80, 0x85ca0600, 0xd0440e00, 
+    0x8ac9a910, 0xd1292900, 0x8a89a910, 0xd1252900, 0x8f2dad10, 0xd1102d00, 0xd10e2b00, 0x8eedad10, 
+    0xd10a2d00, 0x1e80ad10, 0x060082ea, 0x0e00872a, 0x2a00d02b, 0x2900d112, 0xa910d110, 0x29008dc9, 
+    0x2c00d10c, 0xa910d10a, 0x29008d89, 0xa910d106, 0x82ca1e80, 0x85ca0600, 0xd0160e00, 0x8f00a810, 
+    0xd1122800, 0xd1102b00, 0x8ec0a810, 0xd10c2800, 0x8dc0a810, 0xd1082800, 0xd1062c00, 0x8d80a810, 
+    0xd1022800, 0x8702a810, 0x222285c2, 0xa80ca91d, 0xf9a6f7f9, 0xcb07466b, 0xc307ab09, 0xa9262214, 
+    0xf7f9a804, 0xac19f99d, 0x466ccc0f, 0xac15c40f, 0xf7ffcc0f, 0xb02ffbb9, 0xb5f8bdf0, 0x07242403, 
+    0x4dca8aa5, 0x070682a5, 0x06d50f36, 0x432e0ced, 0x682f4dc7, 0x197f4dc7, 0x8aa6813e, 0x43f6263f, 
+    0x4fc382a6, 0x683f068e, 0x197d0eb6, 0x8aa5816e, 0x82a54dc1, 0xd0052b00, 0x03652400, 0xdd032800, 
+    0xe0022401, 0xe7f82401, 0x03242400, 0x2a004325, 0x2401dd01, 0x2400e000, 0x432502e4, 0xdd012b00, 
+    0xe0002401, 0x02a42400, 0x4cb14325, 0x4fb16826, 0x19f63780, 0x25038175, 0x8aae072d, 0x43f6260f, 
+    0x071d82ae, 0x0f2d6824, 0x027626d1, 0x842519a4, 0xfc4bf7ff, 0xb5febdf8, 0x46692000, 0x48a48108, 
+    0x4aa46801, 0x18893a40, 0x68008d49, 0x300130ff, 0x46698e00, 0x20008008, 0x4684880d, 0x270c04a8, 
+    0x28002630, 0x2000da0a, 0x213c4602, 0xf7ff4663, 0x43b7ff94, 0x08b83710, 0xe0100080, 0xd51204e8, 
+    0x20174b96, 0x21162218, 0x569a5618, 0x46635659, 0xff83f7ff, 0x43b02004, 0x08803010, 0x46690080, 
+    0x81081c40, 0x06a8e0fe, 0x4a89d0fc, 0x4b896810, 0x894018c0, 0x68100681, 0x18c00e89, 0x68128900, 
+    0x0f000700, 0x891218d2, 0x04d2072b, 0x24000ed2, 0x2b010f9b, 0x2b02d002, 0xe031d018, 0x29211c49, 
+    0x293cdb07, 0x1843dc03, 0x2b3c189b, 0x1e49dd01, 0x2401e017, 0x2b211c4b, 0x2b3cdb06, 0x1843dc1e, 
+    0x1c5b189b, 0xdc192b3c, 0xe0172704, 0x1e492708, 0xdc08293c, 0xdb032921, 0x1a9b1a0b, 0xda022b06, 
+    0xb2491c49, 0x2401e00a, 0x2b3c1e4b, 0x2b21dcec, 0x1a0bdb04, 0x1e5b1a9b, 0xdae52b06, 0x811f466b, 
+    0x0f9b06ab, 0xd0022b01, 0xd01a2b02, 0x1e52e047, 0xdc072a18, 0xda052a00, 0x893b466f, 0x813b4333, 
+    0xe03c1c52, 0x1e532401, 0xdc052b18, 0xda032b00, 0x893b466f, 0xe0314333, 0x893b466f, 0x331043b3, 
+    0x1c52e02c, 0x2a18d413, 0x1843dc0a, 0x2b3c189b, 0x1a0bdc06, 0x2b061a9b, 0x1883db02, 0xdd062b18, 
+    0x893b466f, 0x332043b3, 0x1e52813b, 0x2401e017, 0xd4e11c53, 0xdc0d2b18, 0x189b1843, 0x2b3c1c5b, 
+    0x1a0bdc08, 0x1e5b1a9b, 0xdb032b06, 0x1c5b1883, 0xddd12b18, 0x893b466f, 0x332043b3, 0x07ab813b, 
+    0x2b010f9b, 0x2b02d002, 0xe04cd01d, 0x1e402603, 0xdc07280a, 0xda052800, 0x893b466f, 0x813b4333, 
+    0xe0401c40, 0x1e432401, 0xdc062b0a, 0xda042b00, 0x893b466f, 0x813b4333, 0x466ee035, 0x089b8933, 
+    0x1c5b009b, 0x1c40e02e, 0x280ad414, 0x1843dc0a, 0x2b3c189b, 0x1a0bdc06, 0x2b061a9b, 0x1883db02, 
+    0xdd072b18, 0x8933466e, 0x009b089b, 0x81331c9b, 0xe0181e40, 0x1c432401, 0x2b0ad4df, 0x1843dc0d, 
+    0x1c5b189b, 0xdc082b3c, 0x1a9b1a0b, 0x2b061e5b, 0x1883db03, 0x2b181c5b, 0x466eddcf, 0x089b8933, 
+    0x1c9b009b, 0x46638133, 0xfe87f7ff, 0xd0092c00, 0x0e8906a9, 0x91012001, 0x22044603, 0x211f9000, 
+    0xfa63f000, 0x68104a0a, 0x18c04b0a, 0x03c18980, 0x89004668, 0x0c400440, 0x05994308, 0x24008a8c, 
+    0x6811828c, 0x804818c9, 0x0000bdfe, 0x0000e0f0, 0x20000084, 0x0001a0c0, 0x0000c3ff, 0x20000200, 
+    0xb5304770, 0x6808490f, 0x18804a0f, 0x23038a02, 0x480f071b, 0x2a0f2504, 0x68004c0c, 0x829c8a9a, 
+    0x6809d008, 0x31ff2200, 0x858a3101, 0x43a98801, 0xbd308001, 0x22026809, 0x310131ff, 0x8801858a, 
+    0xe7f54329, 0x20000084, 0x0001a2c0, 0x0000fffd, 0x20000090, 0x7900482d, 0x0fc007c0, 0x482b4770, 
+    0x228f7801, 0x70014011, 0x78017901, 0x43112201, 0x47707001, 0x68804825, 0x48244770, 0xb2808900, 
+    0x20034770, 0x8a000700, 0x0d800580, 0x49204770, 0x31806809, 0x07097c89, 0x008a0e09, 0x3140491b, 
+    0x60881851, 0x228f7808, 0x30104010, 0x78087008, 0x43102201, 0x47707008, 0x68004815, 0x7c803080, 
+    0x0e000700, 0x48110081, 0x18083040, 0x22027801, 0x70014311, 0x480e4770, 0x6800490c, 0x30803140, 
+    0x07007c80, 0x00800e00, 0x68c01840, 0x48084770, 0x68004906, 0x30803140, 0x07007c80, 0x00800e00, 
+    0x79001840, 0x0fc007c0, 0x00004770, 0x300000c0, 0x20000090, 0xb672b510, 0x69c84959, 0x041222ff, 
+    0x22014390, 0x43100592, 0x485761c8, 0x60414955, 0x20006081, 0x21014a55, 0x0ee406c4, 0x40a3460b, 
+    0x00a40944, 0x602318a4, 0xb2401c40, 0xdbf3280c, 0x20044a4f, 0x0ee406c4, 0x40a3460b, 0x00a40944, 
+    0x602318a4, 0xb2401c40, 0xdbf3280c, 0xbd10b662, 0x4c48b5fe, 0x91006821, 0x4f484d47, 0x6839682e, 
+    0x02019101, 0x07804a46, 0x60291889, 0x12fa6821, 0x0b404391, 0x60214301, 0xfdddf7ff, 0x60209800, 
+    0x9801602e, 0xbdfe6038, 0x4c3ab5fe, 0x91006821, 0x4f3a4d39, 0x6839682e, 0x02019101, 0x07804a38, 
+    0x60291889, 0x12fa6821, 0x0b404391, 0x60214301, 0xf8c8f7ff, 0x60209800, 0x9801602e, 0xbdfe6038, 
+    0x2200b510, 0x98014611, 0xf8c6f000, 0xb510bd10, 0x46112200, 0xf0009801, 0xbd10f8bf, 0x2200b510, 
+    0x98014611, 0xf8b8f000, 0xb510bd10, 0x46112200, 0xf0009801, 0xbd10f8b1, 0x2200b510, 0x98014611, 
+    0xf8aaf000, 0xb510bd10, 0x46112200, 0xf0009801, 0xbd10f8a3, 0x2200b510, 0x98014611, 0xf89cf000, 
+    0x4818bd10, 0xe7937e40, 0x7e804816, 0x4815e790, 0xe78d7ec0, 0x7f004813, 0x4812e78a, 0xe7a37e40, 
+    0x7e804810, 0x480fe7a0, 0xe79d7ec0, 0x7f00480d, 0xb510e79a, 0x46112200, 0xf0009801, 0xbd10f87d, 
+    0xe000ed04, 0x80808080, 0xe000e400, 0xe000e280, 0xe000e100, 0x20000084, 0x20000090, 0x30000014, 
+    0x20000300, 0x20000200, 0x2140b510, 0xf000482b, 0xbd10f9f7, 0xb51008c1, 0x281f1d09, 0xb672d813, 
+    0x4b264a27, 0x32806812, 0x01927c92, 0x2c015c9c, 0x1d09d100, 0x074418d2, 0x0f645c53, 0x40a02001, 
+    0x54534303, 0xbd10b662, 0x491db5f0, 0x680b4e1b, 0x7c993380, 0x198d0189, 0x29ff78a9, 0x786ad02c, 
+    0xd00429fe, 0x42911a8f, 0x240dd803, 0x2402e002, 0x2400e002, 0x1e64193c, 0x0e240624, 0x2c01d01c, 
+    0x1ea0d100, 0x192c0094, 0x60e01c52, 0x280db2d0, 0x2000d300, 0x01927c9a, 0x70501992, 0xd10b29fe, 
+    0x01897c99, 0x78d1198a, 0xd1054281, 0xb2c81c49, 0xd300280d, 0x70d02000, 0x0000bdf0, 0x20000264, 
+    0x20000090, 0x2120b510, 0xf0004839, 0x2120f999, 0xf0004838, 0xbd10f995, 0xf3bfb672, 0x49368f40, 
+    0x7c0a2320, 0x740a431a, 0x8105f3ef, 0x06894a30, 0x78130e89, 0x2b007011, 0x7091d10d, 0xf3ef6090, 
+    0x60d08008, 0x8009f3ef, 0xf3ef6110, 0x61908006, 0x8003f3ef, 0x200161d0, 0xd3062910, 0x39104604, 
+    0x408c6953, 0x61534323, 0x4604e004, 0x408c6853, 0x60534323, 0x70512100, 0x8f40f3bf, 0x78d1b662, 
+    0x70d14301, 0xb5f0e7fe, 0xb6729d05, 0x8f40f3bf, 0x27404c19, 0x433e7c26, 0x4c167426, 0x70207826, 
+    0xd1092e00, 0x60a170a0, 0x8108f3ef, 0xf3ef60e1, 0x61e58109, 0x612161a3, 0x28202101, 0x460dd306, 
+    0x69633820, 0x432b4085, 0xe0046163, 0x6865460b, 0x431d4083, 0x20006065, 0xf3bf7060, 0xb6628f40, 
+    0xd0032a00, 0x430878e0, 0xe7fe70e0, 0x0000bdf0, 0x20000224, 0x20000244, 0x20000200, 0x4b4bb570, 
+    0x5e59210a, 0x4c4a2200, 0xe00a4d4a, 0x546e5ca6, 0x1c521e40, 0xb2091e49, 0xb2d2b2c0, 0xda002900, 
+    0x280021ff, 0x8159d1f2, 0xb5ffbd70, 0x4605b081, 0x9e0b9804, 0xd1002800, 0x493cb672, 0x28ff7b48, 
+    0x894bd102, 0xd3012b08, 0xe0002401, 0x9b022400, 0x2b341e5b, 0x2c00d252, 0x4934d050, 0x29007d49, 
+    0x2d01d14c, 0x2d00d002, 0xe004d003, 0x68004832, 0x42907940, 0xf7ffd342, 0x4607fdcd, 0x482f0c01, 
+    0x0c006800, 0x04001a08, 0xd0120c00, 0x22ff4928, 0x0a02708a, 0x7008704a, 0xf7ff2003, 0x4823ffaf, 
+    0x29ff7b41, 0x8940d104, 0xd2012808, 0xe0002400, 0x48222401, 0x60072c00, 0x2d01d020, 0x2d00d024, 
+    0x2408d027, 0x2800980a, 0x4819d008, 0x70060a31, 0x0c317041, 0x980a7081, 0xff90f7ff, 0x4914980a, 
+    0x01401d00, 0x70c84320, 0x88004814, 0x708a0a02, 0x98027048, 0x20047008, 0xff80f7ff, 0x28009804, 
+    0xb662d100, 0xbdf0b005, 0x6800480b, 0x7c843080, 0x240fe7d8, 0xb51ce7d6, 0x2100460a, 0x460b9100, 
+    0x46019101, 0xf7ff2001, 0xbd1cff80, 0x20000200, 0x2000008c, 0x20000100, 0x20000090, 0x20000088, 
+    0x490eb530, 0x78092000, 0x1e4c4d0b, 0x0202e011, 0x32801952, 0x28007490, 0x1e43d005, 0x42a07513, 
+    0x2300d103, 0x4623e002, 0x1c43e7f8, 0x74d31c40, 0x4288b2c0, 0xbd30d3eb, 0x20000300, 0x20000080, 
+    0xb5f84770, 0xd32c2a04, 0xd0120783, 0x1c49780b, 0x1c407003, 0x07831e52, 0x780bd00b, 0x70031c49, 
+    0x1e521c40, 0xd0040783, 0x1c49780b, 0x1c407003, 0x078b1e52, 0xd0050f9b, 0x00df1ac9, 0x1bde2320, 
+    0xe00ac908, 0xfcdcf7f8, 0x461dbdf8, 0x40fdc908, 0x40b4461c, 0xc010432c, 0x2a041f12, 0x08f3d2f5, 
+    0x1e521ac9, 0x780bd4f0, 0x70031c49, 0x1e521c40, 0x780bd4ea, 0x70031c49, 0x2a011c40, 0x7809d4e4, 
+    0xbdf87001, 0xc004e001, 0x29041f09, 0x078bd2fb, 0x8002d501, 0x07c91c80, 0x7002d000, 0x29004770, 
+    0x07c3d00b, 0x7002d002, 0x1e491c40, 0xd3042902, 0xd5020783, 0x1c808002, 0xe7e31e89, 0xe7ee2200, 
+    0xe7df2200, 0x78c27803, 0x78434619, 0x021b0612, 0x78834319, 0x041b78c0, 0x43114319, 0x0a090209, 
+    0x43080600, 0x22004770, 0x428b0903, 0x0a03d32c, 0xd311428b, 0x469c2300, 0x4603e04e, 0xd43c430b, 
+    0x08432200, 0xd331428b, 0x428b0903, 0x0a03d31c, 0xd301428b, 0xe03f4694, 0x428b09c3, 0x01cbd301, 
+    0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 
+    0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 
+    0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x41524601, 0x47704610, 0x0fcae05d, 0x4249d000, 
+    0xd3001003, 0x40534240, 0x469c2200, 0x428b0903, 0x0a03d32d, 0xd312428b, 0x018922fc, 0x0a03ba12, 
+    0xd30c428b, 0x11920189, 0xd308428b, 0x11920189, 0xd304428b, 0xd03a0189, 0xe0001192, 0x09c30989, 
+    0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, 
+    0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, 
+    0x1ac0008b, 0xd2d94152, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 0x46634601, 0x105b4152, 
+    0xd3014610, 0x2b004240, 0x4249d500, 0x46634770, 0xd300105b, 0xb5014240, 0x46c02000, 0xbd0246c0, 
+    0x46754770, 0xf822f000, 0x000546ae, 0x46534669, 0x00c008c0, 0xb0184685, 0xf7f8b520, 0xbc60fc01, 
+    0x08492700, 0x260046b6, 0xc5c0c5c0, 0xc5c0c5c0, 0xc5c0c5c0, 0xc5c0c5c0, 0x00493d40, 0x4770468d, 
+    0x46c04604, 0x462046c0, 0xfbb3f7f8, 0x47704800, 0x20000094, 0x4674b430, 0x78251e64, 0x42ab1c64, 
+    0x461dd200, 0x005b5d63, 0xbc3018e3, 0x19194718, 0x19191919, 0x18191919, 0x18181818, 0x19191818, 
+    0x221a1919, 0x25242322, 0x29282726, 0x2d2c2b2a, 0x30302f2e, 0x32323131, 0x20421021, 0x81084084, 
+    0x24621231, 0x918848c4, 0x000a0000, 0x001f0015, 0x00340029, 0x0049003e, 0x005d0053, 0x00720068, 
+    0x0087007c, 0x009b0091, 0x00b000a6, 0x00c500ba, 0x00da00cf, 0x00ee00e4, 0x010300f9, 0x0118010d, 
+    0x012c0122, 0x01410137, 0x00110000, 0x00340023, 0x00570046, 0x007a0069, 0x009d008c, 0x00c000af, 
+    0x00e300d2, 0x010600f5, 0x01290118, 0x014c013b, 0x016f015d, 0x01920180, 0x01b501a3, 0x01d801c6, 
+    0x01fb01e9, 0x021e020c, 0x00007bac, 0x20000080, 0x00000014, 0x000001c4, 0x00007bc0, 0x20000094, 
+    0x0000036c, 0x000001e0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000
+};
diff --git a/drivers/net/bcmbca/phy/blackfin_b0_firmware.h b/drivers/net/bcmbca/phy/blackfin_b0_firmware.h
new file mode 100644
index 0000000000..b0af168dca
--- /dev/null
+++ b/drivers/net/bcmbca/phy/blackfin_b0_firmware.h
@@ -0,0 +1,9231 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Aug 2018
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Firmware for external 2.5G/5G/10G phys: Blackfin BCM8489x, BCM5499x
+ */
+
+char blackfin_b0_version[] = "Blackfin B0 v02-02-05";
+
+uint32_t blackfin_b0_firmware[] = {
+    0xea000017, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe320f000, 0xe59ff018, 0xe59ff018, 
+    0x000004a4, 0x0002af3c, 0x0002ae90, 0x0002a1c4, 0x00029aa8, 0x00000000, 0x00029e6c, 0x00029c0c, 
+    0x0002ebb8, 0xc0de512e, 0x00000000, 0x00000000, 0x00000000, 0x0002ebb8, 0x00005102, 0x00000000, 
+    0x00000010, 0xe59f13b0, 0xe5910000, 0xe3800102, 0xe5810000, 0xe59f13a4, 0xe3040440, 0xe1c100b0, 
+    0xeb00013c, 0xe59f0398, 0xe5901000, 0xe3110010, 0x0a000006, 0xe7c0101f, 0xe7c4121f, 0xe59f0384, 
+    0xe5801000, 0xe59f0380, 0xe3a01000, 0xe1c010b0, 0xe3a00064, 0xe2500001, 0xe3500000, 0x1afffffc, 
+    0xe59f0368, 0xe3a01004, 0xe580102c, 0xe59f0360, 0xe1d090b0, 0xe3190001, 0x1a00008c, 0xe59f0354, 
+    0xe3a02010, 0xe3822020, 0xe1d010b0, 0xe0013002, 0xe1530002, 0x1afffffb, 0xe201300f, 0xe59f5338, 
+    0xe3a06055, 0xe1c560b0, 0xe59f0330, 0xe1d010b0, 0xe3c11d0f, 0xe1a02303, 0xe2022d0f, 0xe1811002, 
+    0xe59f0318, 0xe1c010b0, 0xe59f0314, 0xe1d010b0, 0xe3c11001, 0xe1a021a3, 0xe1a02002, 0xe2022001, 
+    0xe1811002, 0xe59f02f8, 0xe1c010b0, 0xe59f02f4, 0xe1d010b0, 0xe3c11a0e, 0xe1a02683, 0xe2022a0e, 
+    0xe1811002, 0xe59f02dc, 0xe1c010b0, 0xe59f02d8, 0xe1d010b0, 0xe3c11a0f, 0xe1a02603, 0xe2022a0f, 
+    0xe1811002, 0xe59f02c0, 0xe1c010b0, 0xe59f02bc, 0xe1d010b0, 0xe3c11b0f, 0xe3c1100f, 0xe1a02503, 
+    0xe2022b0f, 0xe1811002, 0xe1a02003, 0xe202200f, 0xe1811002, 0xe59f0294, 0xe1c010b0, 0xe59f0290, 
+    0xe1d010b0, 0xe3a02006, 0xe1813002, 0xe1c030b0, 0xe3c13006, 0xe1c030b0, 0xe59f0278, 0xe3a01000, 
+    0xe1c010b0, 0xe3a0100a, 0xe59f026c, 0xe1c010b0, 0xe59f0268, 0xe1d000b0, 0xe3100b01, 0x0a000017, 
+    0xe3100b02, 0x0a000015, 0xe59f0254, 0xe3a01dd2, 0xe1c010b0, 0xe59f024c, 0xe30210ef, 0xe1c010b0, 
+    0xe59f0228, 0xe30d1d67, 0xe1c010b0, 0xe59f0238, 0xe3041e63, 0xe1c010b0, 0xe59f0230, 0xe3a01b05, 
+    0xe1c010b0, 0xe59f0228, 0xe3011917, 0xe1c010b0, 0xe59f0220, 0xe3051510, 0xe1c010b0, 0xea00000b, 
+    0xe59f01fc, 0xe3091280, 0xe1c010b0, 0xe59f01f4, 0xe30210e9, 0xe1c010b0, 0xe59f01ec, 0xe3041e63, 
+    0xe1c010b0, 0xe59f01ec, 0xe3051508, 0xe1c010b0, 0xe59f01e4, 0xe30f140f, 0xe1c010b0, 0xe3a01004, 
+    0xe3811001, 0xe59f01d4, 0xe1d020b0, 0xe1510002, 0x1afffffc, 0xe3a00902, 0xe2500001, 0xe3500000, 
+    0x1afffffc, 0xe59f01b8, 0xe3a01000, 0xe1c010b0, 0xe59f01b0, 0xe3a01d06, 0xe1c010b0, 0xe3a060ff, 
+    0xe1c560b0, 0xe59f0138, 0xe5901000, 0xe7c0101f, 0xe7c4121f, 0xe59f0128, 0xe5801000, 0xe59f0130, 
+    0xe3899001, 0xe1c090b0, 0xe3a06000, 0xe1c560b0, 0xe59f0174, 0xe1d090b0, 0xe3190001, 0x1a000002, 
+    0xe3899001, 0xe1c090b0, 0xea00ff34, 0xe59f115c, 0xee091f11, 0xe59fa158, 0xe59fb158, 0xe51f0304, 
+    0xe51f1304, 0xe1a02000, 0xe1500001, 0x0a000024, 0xe51f0310, 0xe3500000, 0x1a000021, 0xe51f2310, 
+    0xe3a01000, 0xe59f0130, 0xe1c010b0, 0xe3e00000, 0xe59f7128, 0xe3a09008, 0xe4d13001, 0xe3510064, 
+    0xca000002, 0xe3510061, 0xba000000, 0xeafffff9, 0xe3a08000, 0xe7e043d3, 0xe7e05fd0, 0xe0346005, 
+    0xe1a00080, 0x0a000000, 0xe0200007, 0xe1a03083, 0xe2888001, 0xe1580009, 0xbafffff5, 0xe1510002, 
+    0xbaffffec, 0xe5912000, 0xe58a0000, 0xe58b2000, 0xe3e03000, 0xe1520003, 0x0a000001, 0xe1500002, 
+    0x1a000009, 0xe3a03901, 0xe59f00ac, 0xe1c030b0, 0xe59f5044, 0xe59f0028, 0xe5901000, 0xe3811040, 
+    0xe3811020, 0xe5801000, 0xe51ff3f0, 0xe3a03902, 0xe59f0084, 0xe1c030b0, 0xeafffffe, 0xf0002010, 
+    0xf23c808c, 0xf0003000, 0xc0003000, 0xc23c802c, 0xf0002000, 0xf23d014c, 0xf23d0206, 0xf23d0228, 
+    0xf203f01a, 0xf203f018, 0xf203f016, 0xf203f00a, 0xf203f004, 0xf203f042, 0xf2034000, 0xf2034002, 
+    0xf23c8038, 0xf203f000, 0xf203f002, 0xf203f006, 0xf203f00e, 0xf203f010, 0xf203f012, 0xf23c8308, 
+    0xf23d000c, 0xf23d0000, 0xf23d0004, 0xf2034020, 0x00040021, 0x00000048, 0x0000004c, 0xf23c801a, 
+    0x04c11db7, 0xebffffff, 0xebffffff, 0xebffffff, 0xebffffff, 0xe3a01401, 0xee110f10, 0xe1800001, 
+    0xe3c00a02, 0xee010f10, 0xee110f30, 0xe3800040, 0xe3800501, 0xee010f30, 0xe59f0080, 0xe3a010d1, 
+    0xe121f001, 0xe1a0d000, 0xe3a010d2, 0xe121f001, 0xe2400080, 0xe1a0d000, 0xe3a010d7, 0xe121f001, 
+    0xe2400c02, 0xe1a0d000, 0xe3a010db, 0xe121f001, 0xe2400080, 0xe1a0d000, 0xe3a010d3, 0xe121f001, 
+    0xe2400080, 0xe1a0d000, 0xe3a010df, 0xe121f001, 0xe2400c02, 0xe1a0d000, 0xe3a010d3, 0xe121f001, 
+    0xe59f0020, 0xe59f1014, 0xe59f2020, 0xe4802004, 0xe1500001, 0xbafffffc, 0xe59fc014, 0xe12fff1c, 
+    0x00057800, 0x00057000, 0x0004e99c, 0x0004ff9c, 0xa5a5a5a5, 0x000005a0, 0xe3a00701, 0xe3a02008, 
+    0xee191f11, 0xe2011d3e, 0xe1811000, 0xe1811102, 0xe3811001, 0xee091f11, 0xf57ff04f, 0xe12fff1e, 
+    0xfa000000, 0xfa000035, 0xe890a00a, 0x44820c00, 0xf1aa4483, 0x45da0701, 0xf000d101, 0xf2aff861, 
+    0xe8ba0e09, 0xf013000f, 0xbf180f01, 0xf0431afb, 0x47180301, 0x0002cc2c, 0x0002cc8c, 0xf04f440a, 
+    0xf8100c00, 0xf0133b01, 0xbf080407, 0x4b01f810, 0xbf08111d, 0x5b01f810, 0xd0051e64, 0x6b01f810, 
+    0xf8011e64, 0xd1f96b01, 0x0f08f013, 0xf810bf1e, 0x1cad4b01, 0xd1091b0c, 0xbf581e6d, 0xcb01f801, 
+    0xe005d5fa, 0x6b01f814, 0x6b01f801, 0xd5f91e6d, 0xd3d64291, 0x00004770, 0xbf243a10, 0xc178c878, 
+    0x0752d8fa, 0xc830bf24, 0xbf44c130, 0x600c6804, 0x00004770, 0x24002300, 0x26002500, 0xbf283a10, 
+    0xd8fbc178, 0xbf280752, 0xbf48c130, 0x4770600b, 0xe89db51f, 0xf0280003, 0xbd1fff4a, 0xbd10b510, 
+    0xf993f029, 0xf7ff4611, 0xf000fff3, 0xf029f8bd, 0xb403f9b1, 0xfff2f7ff, 0xf029bc03, 0x0000f9df, 
+    0x4ff8e92d, 0x0800f04f, 0x0005468a, 0x46464604, 0xd0184647, 0xf02b4608, 0x4602fcd7, 0x2000460b, 
+    0x4180f04f, 0xfd1cf02a, 0x9124f8df, 0x20004602, 0x4649460b, 0xfafcf02b, 0x464b2200, 0xfa3cf02b, 
+    0x91004683, 0x2000e00c, 0xe8bd4601, 0x4b408ff8, 0x22000864, 0x46394630, 0xfa2ef02b, 0x460f4606, 
+    0xd8f42c01, 0x46394630, 0xfc6af02b, 0x20014601, 0xf02b4088, 0x4604fc92, 0x46284689, 0xfca4f02b, 
+    0x4622464b, 0xfad4f02b, 0x9b00e035, 0x4620465a, 0xf02b4629, 0xd332fcad, 0xe0232000, 0x462b4622, 
+    0x46194610, 0xfce0f02b, 0x46042200, 0x0801f108, 0xf04f460d, 0xf02b4380, 0xd811fdd5, 0xfa002001, 
+    0xf02bf008, 0x4602fc6a, 0x4921460b, 0xf02b2000, 0x4632faaf, 0xf02b463b, 0x4606f9ef, 0xe004460f, 
+    0x0001f109, 0x46814550, 0xf04fd3d8, 0x462032ff, 0xf02c4629, 0x45d0fae0, 0x460d4604, 0x4630d3c5, 
+    0xe7a24639, 0x4606b570, 0x461d4614, 0x0104e9dd, 0xfc16f02b, 0x4630b2c1, 0xff72f7ff, 0x462b4622, 
+    0xfeaef02b, 0x4b0c4a0b, 0xfa82f02b, 0x22004b0b, 0xfc9af02b, 0xf04f4b0a, 0xf02b3233, 0x4b09fdc9, 
+    0xf02b2200, 0xf02bfc91, 0xb280fbfb, 0x0000bd70, 0x3ff00000, 0x4ea4a8c1, 0x400a9340, 0x40340000, 
+    0x40333333, 0x40240000, 0xbf6af002, 0xe28fc0bf, 0xe12fff1c, 0x68124afa, 0xd00b4210, 0x68104af9, 
+    0x6f00f5b0, 0x4bf8da06, 0xf843681b, 0x68101020, 0x60101c40, 0xb5104770, 0xf7ff4604, 0x2000ffeb, 
+    0xf812f007, 0x46204601, 0x4010e8bd, 0xb570e7e2, 0x4605460c, 0xf00948ed, 0x4621f85a, 0xf7ff4628, 
+    0x4ceaffea, 0x68214628, 0xffd4f7ff, 0x46286861, 0xffd0f7ff, 0x462868a1, 0xffccf7ff, 0x462868e1, 
+    0x4070e8bd, 0xb570e7c6, 0x4605460c, 0xf00948e0, 0x4621f8e0, 0xf7ff4628, 0x48deffce, 0xf2402200, 
+    0xf02971ff, 0x4601fbb4, 0xf7ff4628, 0x4cd8ffb3, 0xf9b48861, 0xeb000000, 0x46284101, 0xffaaf7ff, 
+    0xf9b488e1, 0xeb000004, 0x46284101, 0x4070e8bd, 0xb570e7a0, 0x48ca4605, 0x42056800, 0x188cd016, 
+    0x4621b152, 0xf7ff4628, 0x2000ff95, 0xffbcf006, 0x46284601, 0xff8ef7ff, 0x880849c7, 0xf3c01c40, 
+    0x60080009, 0x680949c5, 0x4020f841, 0x48c4bd70, 0xb5102100, 0xfb53f029, 0x212048c1, 0xf0293064, 
+    0x48c0fb4e, 0x22462100, 0x0400f640, 0x80428001, 0x80c18081, 0x48bc4621, 0xf02a6800, 0x48b2fb49, 
+    0x68004621, 0xfb34f02a, 0x00a148b8, 0xe8bd6800, 0xf02a4010, 0xb570bb3d, 0xf240b281, 0xf3c01500, 
+    0x2008040e, 0x52b8f04f, 0xffb3f7ff, 0xd8032cff, 0xb2e049ac, 0xe0043108, 0x4f50f5b4, 0x49acd205, 
+    0xf851b2e0, 0x47800020, 0x48a54605, 0x30644629, 0xfb15f029, 0x462148a2, 0xfb11f029, 0xf64f48a0, 
+    0x307471ff, 0xfb0bf029, 0xf248489d, 0xe8bd0100, 0x30704070, 0xbb03f029, 0xf2414899, 0xb5101122, 
+    0xf0293066, 0x4896fafc, 0x30642108, 0xfaf7f029, 0xbd102008, 0xf00cb510, 0xb2c1fe9a, 0x30684890, 
+    0xfaedf029, 0x88014893, 0x3066488d, 0xfae7f029, 0xbd102004, 0xb510488a, 0xf0293068, 0x498dfadd, 
+    0x20018008, 0xfffbf00c, 0xbd102004, 0xb510488a, 0x0000f990, 0x4882b281, 0xf0293066, 0x2004fad0, 
+    0x487fbd10, 0x3066b510, 0xfac6f029, 0x70084982, 0xbd102004, 0xb5104881, 0x48797801, 0xf0293066, 
+    0x487ffabe, 0x48767801, 0xf0293068, 0x487dfab8, 0x48737801, 0xf029306a, 0x2004fab2, 0x4870bd10, 
+    0x3066b510, 0xfaa8f029, 0xb2c04974, 0x28014c74, 0xd0037008, 0x70202000, 0xbd102004, 0x30684868, 
+    0xfa9af029, 0x4870e7f7, 0xb5104a70, 0x78127800, 0x010cf000, 0x0003f000, 0xeb010209, 0x4a6c1182, 
+    0xeb017812, 0xeb011102, 0x496a0080, 0x44087809, 0x485bb281, 0xf0293066, 0x4867fa82, 0xfa7cf029, 
+    0x48574601, 0xf0293068, 0x4863fa7a, 0xf0291c80, 0x4601fa73, 0x306a4852, 0xfa71f029, 0x1d00485e, 
+    0xfa6af029, 0x484e4601, 0xf029306c, 0x485bfa68, 0x01017800, 0x306e484a, 0xfa61f029, 0xbd102004, 
+    0xb5704847, 0xf0293066, 0x4604fa57, 0x306e4844, 0xfa52f029, 0xb205494f, 0x0003f004, 0x200c7008, 
+    0x2014ea00, 0x0181f3c4, 0x49474408, 0xf3c47008, 0x49471001, 0xf3c47008, 0x49441081, 0x48387008, 
+    0xf0293068, 0x4946fa39, 0x48358008, 0xf029306a, 0x4944fa33, 0x48328008, 0xf029306c, 0x4942fa2d, 
+    0x04208008, 0xf3c5d502, 0xe0001006, 0x493b2000, 0x20047008, 0xb510bd70, 0x22014c3c, 0x46202102, 
+    0xfa45f029, 0x48264601, 0xf0293066, 0x2206fa18, 0x21404620, 0xfa3bf029, 0x48214601, 0xf0293068, 
+    0x2205fa0e, 0x21204620, 0xfa31f029, 0x481c4601, 0xf029306a, 0x2004fa04, 0x4819bd10, 0x3066b510, 
+    0xf9faf029, 0x22014c29, 0x46032102, 0xf0294620, 0x4813fa10, 0xf0293068, 0x2206f9ef, 0x21404603, 
+    0xf0294620, 0x480efa06, 0xf029306a, 0x2205f9e5, 0x21204603, 0xf0294620, 0x2004f9fc, 0x0000bd10, 
+    0x00057ffc, 0x00057ff0, 0x0004022c, 0x00041458, 0x00040590, 0xf2030430, 0x00057ff4, 0x00057ff8, 
+    0xf23c800a, 0x00040020, 0x00040228, 0x00040224, 0x000401a0, 0x000402b8, 0x000405b4, 0x000402f4, 
+    0x000402f5, 0x0004033d, 0x000402c0, 0x00040316, 0x00040315, 0x000402bf, 0xf2035118, 0x000402c1, 
+    0x000402c4, 0x000402c6, 0x000402c8, 0xf38e0040, 0xb51048fe, 0xf9a0f029, 0x0101f000, 0x305448fb, 
+    0xf99df029, 0xe7b92004, 0xb51048f9, 0x48f77801, 0xf0293054, 0x2004f994, 0x48f4e7b0, 0x3054b510, 
+    0xf98af029, 0x780a49f2, 0xd0034290, 0x20017008, 0x700849f0, 0xe7a12004, 0x4cefb510, 0x22042300, 
+    0x46202110, 0xf995f029, 0x46202300, 0x21202205, 0xf98ff029, 0x48e52300, 0x461a2101, 0xf989f029, 
+    0xe78b2004, 0x4ce4b570, 0x2200230f, 0x46204619, 0xf97ff029, 0x7507f240, 0x46291ca0, 0xf95ff029, 
+    0x46291d20, 0xf95bf029, 0x46202301, 0x21102204, 0xf96ff029, 0x46202301, 0x21202205, 0xf969f029, 
+    0x48d22301, 0x46192200, 0xf963f029, 0xbd702004, 0xb51048d2, 0x48cd7801, 0xf0293054, 0x48d0f940, 
+    0x48ca7801, 0xf0293056, 0x2004f93a, 0x48c7e756, 0x3054b510, 0xf930f029, 0x700849c8, 0x305648c3, 
+    0xf92af029, 0x700849c6, 0xe7472004, 0xb51048c5, 0x28037800, 0x2100d012, 0x305448bc, 0xf91ff029, 
+    0x780148c1, 0x305648b9, 0xf919f029, 0x780148bf, 0x305848b6, 0xf913f029, 0xe72f2004, 0xe7eb2101, 
+    0xb51048b2, 0xf0293054, 0x49b7f907, 0x20047008, 0x48b7e724, 0xf990b510, 0x28040000, 0x2805d009, 
+    0x2803d007, 0x2802d005, 0x2801d024, 0x2008d022, 0x4ca9e714, 0x22002301, 0x3c824619, 0xf0294620, 
+    0x2301f908, 0x22034620, 0xf0292108, 0x2301f902, 0x22024620, 0xf0292104, 0x1ca0f8fc, 0xf8dcf029, 
+    0xf0291d20, 0x2300f8d9, 0x21014620, 0xf029461a, 0xe03bf8f0, 0x23014c9f, 0x03d9220f, 0xf0294620, 
+    0x2301f8e8, 0x220e4620, 0xf0290399, 0x2301f8e2, 0x21024620, 0xf029461a, 0x2300f8dc, 0x22014620, 
+    0xf0292102, 0x2301f8d6, 0x22004620, 0xf0294619, 0x4c90f8d0, 0x46203c0a, 0xf8aef029, 0xf0294620, 
+    0x1ca4f8ab, 0xf0294620, 0x4620f8a7, 0xf8a4f029, 0x46201ca4, 0xf8a0f029, 0xf0294620, 0x1ca4f89d, 
+    0xf0294620, 0x4620f899, 0xf896f029, 0xe6b52004, 0x47f0e92d, 0x30544875, 0xf88ef029, 0xb2c44d73, 
+    0x3556487b, 0xf1051cae, 0xf9900804, 0xf1050000, 0x28040906, 0x2805d008, 0x2803d006, 0x2802d004, 
+    0x2801d04e, 0xe080d04c, 0x23014f6b, 0x3f822203, 0x46382108, 0xf88df029, 0x46382301, 0x21042202, 
+    0xf887f029, 0x2c01b114, 0xe06ed01b, 0x387e4862, 0xf862f029, 0x46284601, 0xf861f029, 0x3880485e, 
+    0xf85af029, 0x46304601, 0xf859f029, 0x3876485a, 0xf852f029, 0x46404601, 0xf851f029, 0x38784856, 
+    0x4855e019, 0xf029387a, 0x4601f847, 0xf0294628, 0x4851f846, 0xf029387c, 0x4601f83f, 0xf0294630, 
+    0x484df83e, 0xf0293872, 0x4601f837, 0xf0294640, 0x4849f836, 0xf0293874, 0x4601f82f, 0xe0324648, 
+    0x2c01b114, 0xe030d012, 0x1fa44c4a, 0xf0294620, 0x4601f823, 0xf0294630, 0x4620f822, 0xf81cf029, 
+    0x46284601, 0xf81bf029, 0xe0101ca4, 0x3c084c41, 0xf0294620, 0x4601f811, 0xf0294630, 0x4620f810, 
+    0xf80af029, 0x46284601, 0xf809f029, 0x46201ea4, 0xf802f029, 0x46484601, 0xf801f029, 0xf0284620, 
+    0x4601fffb, 0xf0284640, 0x2004fffa, 0x87f0e8bd, 0xb5104826, 0xf0283056, 0x4c2fffef, 0x48237020, 
+    0xf0283054, 0x7821ffe9, 0xf00cb2c0, 0x2004fb3a, 0x482ae604, 0xf244220e, 0xb5100100, 0xf807f029, 
+    0x32544a1a, 0x2101b108, 0x2100e000, 0xf0284610, 0x4821ffd6, 0x48157801, 0xf0283056, 0x2004ffd0, 
+    0x2301e5ec, 0x2200481e, 0xb5104619, 0xffe1f028, 0x3044481b, 0xffc0f028, 0x480c4601, 0xf0283054, 
+    0x4817ffbe, 0xf0283046, 0x4601ffb7, 0x30564807, 0xffb5f028, 0x30484812, 0xffaef028, 0x48034601, 
+    0xf0283058, 0x480effac, 0xe01b304a, 0xf23c801c, 0x00040311, 0x0004036a, 0xf203526c, 0x00040312, 
+    0x00040313, 0x000405d9, 0x00040318, 0x000405ea, 0x00040244, 0xf38f215e, 0x00040369, 0xf38f2050, 
+    0xf2030406, 0xff88f028, 0x48fe4601, 0xff87f028, 0xe5a32004, 0xb51048fc, 0x48fa7801, 0xf0281f80, 
+    0x48faff7e, 0x48f77801, 0xf0281f00, 0x2004ff78, 0x48f4e594, 0x1f80b510, 0xff6ef028, 0x700849f2, 
+    0x1f0048f0, 0xff68f028, 0x700849f0, 0xe5852004, 0x4cefb510, 0x0000f994, 0x48eab281, 0xf0281f80, 
+    0x7820ff5e, 0xd1082802, 0x305c48e6, 0xff54f028, 0x48e44601, 0xf0281f00, 0x2004ff52, 0x48e1e56e, 
+    0x41f0e92d, 0xf0281f80, 0x49e1ff47, 0x4dddb240, 0xf8df4fe0, 0x35648370, 0x37104ede, 0x70082802, 
+    0x085cf108, 0x2801d040, 0xf019d07e, 0x2300fb55, 0x22034638, 0xf0282108, 0x2300ff35, 0x22014628, 
+    0xf0282102, 0x2301ff46, 0x220a4628, 0xf0280299, 0x2301ff40, 0x220b4628, 0xf02802d9, 0x2301ff3a, 
+    0x21024638, 0xf028461a, 0x2301ff1d, 0x21024630, 0xf028461a, 0x2300ff17, 0x22014638, 0xf0282102, 
+    0x2300ff11, 0x22014630, 0xf0282102, 0x2300ff0b, 0x21014628, 0xf028461a, 0x2100ff1c, 0xf0284640, 
+    0x2004fefe, 0x81f0e8bd, 0x1f0048b6, 0xfef4f028, 0x2c1ab2c4, 0x2c2ad00b, 0x2c3ad009, 0x2c0bd007, 
+    0x2c0cd005, 0x2c0dd003, 0x2c0ed001, 0x4621d1e9, 0xf0284640, 0x2208fee4, 0x23014628, 0xf0280151, 
+    0x2301fef8, 0x22094628, 0xf0280259, 0x2301fef2, 0x22004628, 0xf0284619, 0x48a6feec, 0x303049a6, 
+    0xfec7f028, 0x46302301, 0x21042202, 0xfecaf028, 0x46382301, 0x21042202, 0xfec4f028, 0x2200489f, 
+    0xf990b261, 0xe0000000, 0xf019e005, 0x499cfb3e, 0x70082001, 0xf019e7b5, 0xe778f97a, 0xb5104899, 
+    0x48907801, 0xf0281f80, 0x4897feaa, 0x488d7801, 0xf0281f00, 0x4895fea4, 0x488a7801, 0xf0281e80, 
+    0x2004fe9e, 0x4887e4ba, 0x1f80b510, 0xfe94f028, 0x7008498c, 0x1f004883, 0xfe8ef028, 0x7008498a, 
+    0x1e804880, 0xfe88f028, 0x70084988, 0xe4a52004, 0x4c87b570, 0x210f2200, 0xf0284620, 0x2200fea8, 
+    0x213f4605, 0xf0281ca0, 0xb206fea2, 0x7100f641, 0x46202208, 0xfe9bf028, 0x46042200, 0x210f487d, 
+    0xfe95f028, 0xf366b200, 0xf360251f, 0x486d241f, 0xb2a4b2a9, 0xf0281f00, 0x486afe62, 0x1e804621, 
+    0xfe5df028, 0x21004867, 0xfe59f028, 0x21004865, 0xf0281c80, 0x2004fe54, 0xe92dbd70, 0x486147f0, 
+    0xf0281f80, 0x4d5ffe49, 0x2910ea4f, 0x1f2d4c6a, 0xf0284628, 0xfa4ffe41, 0x4628f880, 0xfe3cf028, 
+    0xf3401cad, 0x46282707, 0xfe36f028, 0x4628b246, 0xfe32f028, 0x2507f340, 0xf0284852, 0x0a00fe2d, 
+    0xd900280f, 0xeb092000, 0x56630189, 0xd1104543, 0xf992190a, 0x42bb3001, 0xf992d10b, 0x42b33002, 
+    0xf992d107, 0x42aa2003, 0xf994d103, 0x42822020, 0x4b52d002, 0x701a2201, 0x0f00f1b9, 0x8001f804, 
+    0x704f4421, 0x70cd708e, 0x0020f884, 0xf884d10c, 0x2200800f, 0x46497427, 0x46207466, 0xf02774a5, 
+    0xb108fd78, 0xe6012008, 0xe5ff2004, 0x22004841, 0x385a2101, 0xf028b510, 0x4601fe1a, 0x1f004831, 
+    0xfdedf028, 0x2200483b, 0x387a2101, 0xfe0ff028, 0x482c4601, 0xf0281e80, 0x2004fde2, 0x4829e443, 
+    0x4c35b570, 0xf0281f00, 0x4605fdd7, 0x1e804825, 0xfdd2f028, 0xb2e84601, 0x0022f884, 0xb2c92200, 
+    0x1021f884, 0xfd6ef025, 0xbd702004, 0xb510482c, 0xfdc2f028, 0x481b4601, 0xf0281f80, 0x4828fdc0, 
+    0xf0281c80, 0x4601fdb9, 0x1f004816, 0xfdb7f028, 0x1d004823, 0xfdb0f028, 0x48124601, 0xf0281e80, 
+    0x481ffdae, 0xf0281d80, 0x4601fda7, 0xf028480d, 0x2004fda6, 0xe92de407, 0x491a5ffc, 0xf1054d1a, 
+    0xf9910608, 0x29031000, 0x2905d003, 0x2904d001, 0xb358d100, 0x21802000, 0x1010f825, 0x1010f826, 
+    0xe0241c40, 0xf23c8076, 0x0004033f, 0x00040340, 0x00040582, 0xf0008160, 0x00501bd0, 0x0004028a, 
+    0x00040341, 0x00040314, 0x000405d9, 0x000405d3, 0xf303a0c8, 0xf303a220, 0x0004e178, 0x0004036a, 
+    0xf23d0144, 0x00040244, 0x00040010, 0xb2c0e009, 0xd3d12804, 0x5ffce8bd, 0xf1a149fd, 0xf0070008, 
+    0x48fcbec0, 0xfa03f008, 0x93e8f8df, 0xf8df2400, 0xf06fb3e8, 0x4ff90aea, 0x087ef06f, 0x200049f8, 
+    0x465a4bf8, 0x0100e9cd, 0x0024f859, 0xf93af7ff, 0xf080fa0a, 0x287fb200, 0x0014f825, 0x207fdd03, 
+    0x0014f825, 0x4540e003, 0xf825da01, 0xf9368014, 0xf9351014, 0x42810014, 0x5d39dc02, 0xd1032901, 
+    0x0014f826, 0x55382000, 0xb2e41c64, 0xd3d52c04, 0xe92de7c0, 0x48e447ff, 0xfd1ef028, 0x70284de3, 
+    0xf00848dc, 0x4fdbf9c4, 0xf8df2400, 0xae02836c, 0x9370f8df, 0x49da2000, 0x464b4642, 0x0100e9cd, 
+    0x0024f857, 0xf8fef7ff, 0x0014f826, 0xb2641c64, 0xdbef2c04, 0xf8bd48d4, 0x1c801008, 0xfcfff028, 
+    0xf8bd48d1, 0x1d00100a, 0xfcf9f028, 0xf8bd48ce, 0x1d80100c, 0xfcf3f028, 0xf8bd48cb, 0x3008100e, 
+    0xfcedf028, 0xb1107828, 0xf7ff2000, 0x2004ff44, 0xe4ebb004, 0xb51048c6, 0xfcdef028, 0x48c24601, 
+    0xfcddf028, 0xe4422004, 0xb51048bf, 0xfcd4f028, 0x600849c0, 0x1c8048bc, 0xfccef028, 0x600849be, 
+    0x1d0048b9, 0xfcc8f028, 0x700849bc, 0xe42e2004, 0xb51048b8, 0xb2818800, 0xf02848b3, 0x48b6fcc0, 
+    0xb2818800, 0x1c8048b0, 0xfcb9f028, 0x780148b3, 0x1d0048ad, 0xfcb3f028, 0xe4182004, 0xb51048aa, 
+    0xfcaaf028, 0x600849ae, 0x1c8048a7, 0xfca4f028, 0x600849ac, 0x1d0048a4, 0xfc9ef028, 0x600849aa, 
+    0xe4042004, 0xb51048a6, 0xb2818800, 0xf028489e, 0x48a4fc96, 0xb2818800, 0x1c80489b, 0xfc8ff028, 
+    0x880048a1, 0x4898b281, 0xf0281d00, 0x2004fc88, 0x489ee49e, 0x7801b510, 0xf0284893, 0x2004fc80, 
+    0x4891e496, 0xf028b510, 0x4998fc77, 0x20047008, 0xe92de48e, 0x200841f0, 0x0144f248, 0x52b8f04f, 
+    0xf8f7f7ff, 0x26004c92, 0x78204f87, 0xd1092801, 0x46382200, 0xf0282103, 0xb918fc8a, 0x7006488d, 
+    0xff55f00b, 0x46382200, 0xf0282103, 0x2202fc80, 0x211c7020, 0xf0284638, 0x4987fc7a, 0x70082205, 
+    0x46382120, 0xfc73f028, 0x81dcf8df, 0x4c832801, 0x0802f108, 0x2208d10d, 0x7100f64f, 0xf0284640, 
+    0xf02afc66, 0xf06ffc91, 0xf02b0207, 0xe9c4fb04, 0x22060100, 0x21404638, 0xfc59f028, 0x28014d78, 
+    0x2200d10c, 0x21ff4640, 0xfc51f028, 0xfc7cf02a, 0x0204f06f, 0xfaeff02b, 0x0100e9c5, 0x46382207, 
+    0xf0282180, 0x2801fc44, 0x496fd103, 0xe9c4486d, 0x22080100, 0x01514638, 0xfc39f028, 0xd1032801, 
+    0x486a496b, 0x0100e9c5, 0xf2402209, 0x46382100, 0xfc2df028, 0xd1012801, 0x70064866, 0xf240220a, 
+    0x46384100, 0xfc23f028, 0xd1012801, 0x70064862, 0xe4f72004, 0x41f0e92d, 0xf2482008, 0xf04f0145, 
+    0xf7ff52b8, 0x485bf876, 0x7400f64f, 0x22084d46, 0x78034621, 0xf0284628, 0x4957fbfc, 0x46282200, 
+    0x21ff780b, 0xfbf5f028, 0x2208494c, 0x0100e9d1, 0xfaa1f02b, 0xfbe4f02a, 0x4621b283, 0x22081cad, 
+    0xf0284628, 0x4846fbe6, 0xe9d02205, 0xf02b0100, 0xf02afa92, 0xb283fbd5, 0x22004628, 0xf02821ff, 
+    0x483bfbd8, 0x22001cae, 0x78032103, 0xf0284630, 0x4838fbd0, 0x210c2202, 0x46307803, 0xfbc9f028, 
+    0x22044d35, 0x46302170, 0xf028782b, 0x2300fbc2, 0x7180f64f, 0x46302207, 0xfbbbf028, 0x1cb5782a, 
+    0xb1521cae, 0x2a014c35, 0x2a02d06c, 0x2100d06b, 0xf0284628, 0x2100fb94, 0x4f31e096, 0xe9d72203, 
+    0xf02b0100, 0xf02afa58, 0x28fffb6b, 0x20ffdb00, 0x4628b283, 0x21ff2200, 0xfb9bf028, 0xe9d72203, 
+    0xf02b0102, 0xf02afa48, 0x28fffb5b, 0x20ffdb00, 0xb2834621, 0x22084628, 0xfb8bf028, 0xe9d72203, 
+    0xf02b0104, 0xf02afa38, 0x28fffb4b, 0xe03bdb3d, 0x00040018, 0x00041458, 0xb573eab3, 0x00040547, 
+    0x40300000, 0x4030ab15, 0xf23c8070, 0x000402e1, 0xf23d0142, 0x000402fc, 0x00040300, 0x000402fb, 
+    0x00040308, 0x0004030c, 0x00040304, 0x000402f7, 0x00040360, 0x0004034c, 0x00040361, 0x00040350, 
+    0x00040358, 0xb71758e2, 0x3fae00d1, 0x538ef34d, 0x3ff42474, 0x0004034d, 0x0004034e, 0x0004e1a0, 
+    0x0004e1c0, 0xe022e018, 0xb28320ff, 0x22004630, 0xf02821ff, 0x2203fb3e, 0x0106e9d7, 0xf9ebf02b, 
+    0xfafef02a, 0xdb0028ff, 0x462120ff, 0x4630b283, 0xf0282208, 0xe01afb2e, 0x0100e9d4, 0xfb20f02a, 
+    0x4628b281, 0xfb0bf028, 0x0102e9d4, 0xe9d4e009, 0xf02a0104, 0xb281fb15, 0xf0284628, 0xe9d4fb00, 
+    0xf02a0106, 0xb281fb0d, 0xf0284630, 0x2004faf8, 0xe92de6ff, 0xf8df5ff0, 0x21008424, 0xf0284640, 
+    0xf108faee, 0x21000902, 0xf0284648, 0xf108fae8, 0x21000a04, 0xf0284650, 0xf108fae2, 0x21000b06, 
+    0xf0284658, 0x4cfefadc, 0x4dff4ffe, 0xf5a08820, 0x39ff417f, 0x7838d013, 0xd1102801, 0x46282204, 
+    0xf0282110, 0x2203faf4, 0x21084606, 0xf0284628, 0x4286faee, 0x2000d101, 0x2001e000, 0xf9978020, 
+    0xb2810000, 0xf0284640, 0x8821faba, 0xf0284648, 0x2204fab6, 0x21104628, 0xfad9f028, 0x46504601, 
+    0xfaadf028, 0x46282203, 0xf0282108, 0x4601fad0, 0xf0284658, 0x2004faa4, 0x9ff0e8bd, 0x5ff0e92d, 
+    0xf02848de, 0x4ddefa99, 0xf64f4604, 0x882970ff, 0xd1084281, 0xf2482008, 0xf04f1137, 0xf7fe52b8, 
+    0x2008ff18, 0x4ed7e7e8, 0x0a02f04f, 0x802849d3, 0x4fd61c89, 0x0000f996, 0x0b02f101, 0x8350f8df, 
+    0x9350f8df, 0xd02c4284, 0xd01a2c01, 0x48d22301, 0x46192200, 0xa000f8a5, 0xfa8bf028, 0x7034200a, 
+    0xffd5f005, 0x48cd2301, 0x029c220a, 0xf0284621, 0x48cafa69, 0x220a2301, 0x1d004621, 0xfa62f028, 
+    0x4608e024, 0xfa58f028, 0x46587038, 0xfa54f028, 0x0000f888, 0x1d8048b9, 0xfa4ef028, 0x0000f889, 
+    0x2c01e7dc, 0x4608d110, 0xfa46f028, 0x46587038, 0xfa42f028, 0x0000f888, 0x1d8048b0, 0xfa3cf028, 
+    0x0000f889, 0xfc99f00c, 0xa000f8a5, 0xe7932004, 0x48aab570, 0xfa30f028, 0x48a84604, 0xf0281c80, 
+    0xea40fa2b, 0x48a54404, 0xf0281d80, 0x4605fa25, 0x1d0048a2, 0xfa20f028, 0x4620b148, 0xfa1cf028, 
+    0x489e4601, 0xf0283008, 0x2004fa1a, 0x4629bd70, 0xe7f84620, 0xb51048a3, 0x68004ca1, 0x48a26020, 
+    0x48a26060, 0x48a260a0, 0x48a260e0, 0x48a26120, 0x48a26160, 0x48a261a0, 0x48a261e0, 0x48a26220, 
+    0x62606800, 0x62a048a1, 0x62e02000, 0x63606320, 0xf02363a0, 0x63e0ff1f, 0xb2814620, 0x1d804887, 
+    0xf9edf028, 0x0c014620, 0x1d004884, 0xf9e7f028, 0x21104882, 0xf9e3f028, 0xe43b2004, 0xb5104888, 
+    0x487eb281, 0xf0281d80, 0x4885f9da, 0x487b0c01, 0xf0281d00, 0x2004f9d4, 0x4878e42c, 0x1d80b510, 
+    0xf9caf028, 0x48754604, 0xf0281d00, 0xeb04f9c5, 0x88204400, 0x4871b281, 0xf0281c80, 0x6820f9c0, 
+    0x486e0c01, 0xf9bbf028, 0xe4132004, 0xb570486b, 0xf0281d80, 0x4604f9b1, 0x1d004868, 0xf9acf028, 
+    0x4400eb04, 0x1c804865, 0xf9a6f028, 0x48634605, 0xf9a2f028, 0x4000eb05, 0x20046020, 0xe92dbd70, 
+    0x4e6f41f0, 0x4f722500, 0xeb072400, 0xf0280044, 0xeb04f993, 0x1c6401c5, 0x2c08b224, 0x0011f826, 
+    0x1c6ddbf3, 0x2d40b22d, 0x2004dbee, 0x4853e591, 0x1d80b510, 0xf980f028, 0x60204c5e, 0x1d00484f, 
+    0xf97af028, 0xea416821, 0x60204000, 0xe49a2004, 0x4c58b510, 0xb2818820, 0x1d804848, 0xf96ff028, 
+    0x0c016820, 0x1d004845, 0xf969f028, 0xe48a2004, 0x4842b538, 0xf960f028, 0x4840b245, 0xf0281c80, 
+    0xb244f95b, 0x1d00483d, 0xf956f028, 0xf04fb242, 0x2d010000, 0x4b4ad006, 0x90004621, 0xf0042001, 
+    0xe00bfc43, 0x4a46494b, 0x1144eb01, 0x3010f931, 0x3020f842, 0xb2401c40, 0xdbf72810, 0xbd382004, 
+    0x2000493a, 0x6008b510, 0x0100f640, 0x68004835, 0xf92ef029, 0x21004829, 0xf931f028, 0xe4522004, 
+    0x22084829, 0x0151b570, 0xf0283854, 0x4c23f950, 0x21202205, 0x3c564603, 0xf0284620, 0x4e36f93a, 
+    0x21042202, 0xf0284630, 0xf242f942, 0x46030500, 0x4629220d, 0xf0284620, 0x2202f92c, 0x21044630, 
+    0xf935f028, 0x22004e15, 0x46032101, 0x46303e4e, 0xf91ff028, 0x220f4829, 0xf02800a9, 0x2205f928, 
+    0x21204603, 0xf0284630, 0x4825f914, 0x21022201, 0xf91df028, 0x46032206, 0x46302140, 0xf909f028, 
+    0x22064820, 0xf0282140, 0x220cf912, 0x10694603, 0xf0284630, 0x2201f8fe, 0xe0352102, 0xf23c8070, 
+    0x00040348, 0x00040283, 0xf38f2056, 0x00040344, 0x00040345, 0x00040346, 0xf38f0000, 0xf0001030, 
+    0x00041928, 0x0004022c, 0x00057ff8, 0x00057ff0, 0x00057ff4, 0x00057ffc, 0x00057c00, 0x00057c40, 
+    0x00057800, 0x00057c80, 0x00040228, 0x00041708, 0xf203612e, 0x000412c8, 0xf3074084, 0xf3078958, 
+    0xf302012c, 0xf3074190, 0x1e8048fe, 0xf8cff028, 0x4603220d, 0x46304629, 0xf8bbf028, 0x22024dfb, 
+    0xf99548f9, 0x5c431000, 0x4620211c, 0xf8b1f028, 0x220948f7, 0x6100f240, 0x46207803, 0xf8a9f028, 
+    0x220748f4, 0xf0282180, 0x2201f8b2, 0x21024603, 0xf0284620, 0x48f0f89e, 0x21f02204, 0xf8a7f028, 
+    0xd1022805, 0x780048ed, 0x2300b150, 0x22004620, 0xf0282101, 0x7828f88e, 0x4070e8bd, 0xbc8ff00b, 
+    0xe7f32301, 0xf027b510, 0xb281fe19, 0x48e44604, 0xf865f028, 0x0c2148e2, 0xf0281c80, 0x2004f860, 
+    0x48dfe67b, 0x2134f241, 0x1d00b510, 0xf857f028, 0x46204cdc, 0x48dab281, 0xf0281c80, 0x4620f850, 
+    0x48d70c01, 0xf84bf028, 0xfe08f027, 0xf0276020, 0x6060fe25, 0xfe12f027, 0xf02760a0, 0x60e0fe17, 
+    0xfe04f027, 0xf0276120, 0x6160fe21, 0x48cc2106, 0xf0281f00, 0x2004f834, 0xe92de64f, 0x48c85ff0, 
+    0x1f002700, 0xf828f028, 0x48c54604, 0xf0281e80, 0xf8dff823, 0xf0008314, 0xf3c00507, 0xf8df1602, 
+    0xf3c4b30c, 0xf3c43300, 0xf9982903, 0xf0040000, 0x2801041f, 0x2802d04a, 0x2803d00d, 0x0205f04f, 
+    0x0120f04f, 0xf8dfd004, 0xf1aaa2e4, 0xe0430a60, 0x465846da, 0xf8dfe006, 0x2205a2d4, 0xf1aa2120, 
+    0xe0390a20, 0xf815f028, 0x464b2200, 0x4650210f, 0xf80ff028, 0x48ae2300, 0xf643461a, 0xf02771ff, 
+    0xf8dffff1, 0x2c1aa2b0, 0xf1c5d228, 0xf64f0008, 0xeb0071ff, 0xea010040, 0xf04f2000, 0xeb0131ff, 
+    0x48a50150, 0xffd5f027, 0x211848a1, 0xf0271f00, 0x48a2ffd0, 0x5146ea44, 0x489f4301, 0xf0273808, 
+    0xf89affc8, 0xf44f1000, 0xe0421080, 0xa25cf8df, 0x21202205, 0x0a40f1aa, 0xe7c34650, 0xf04fd102, 
+    0xe023000b, 0xd01c2c1b, 0xd01c2c1c, 0xd01c2c1d, 0xf998200b, 0x05721000, 0x3181ea42, 0x4187ea41, 
+    0x1140ea41, 0x488c4301, 0xf0273808, 0x4888ffa2, 0x1f002119, 0xff9df027, 0x7800487c, 0xd0072804, 
+    0x200fe007, 0x2010e7e5, 0x2011e7e3, 0xe7e02701, 0x2e03006d, 0xf240d902, 0xe0044000, 0xeb062001, 
+    0x40880146, 0x2100b280, 0xeb054345, 0xebc01085, 0xf00500c0, 0xf1b9fc21, 0xd01f0f00, 0x0000f998, 
+    0xd0142801, 0xd00c2802, 0xf04f2803, 0xf04f0301, 0xf04f0204, 0xd0020110, 0x3860486c, 0x4658e00c, 
+    0x486ae00a, 0x22042301, 0x38202110, 0x4867e004, 0x22042301, 0x38402110, 0xff7bf027, 0xd2062c1a, 
+    0x23014865, 0x0719221c, 0xf0273808, 0xf89aff5b, 0xf44f1000, 0xf0051080, 0x2004fbef, 0x4860e4ac, 
+    0x7801b510, 0x1f004856, 0xff49f027, 0xe5642004, 0xb5104853, 0xf0271f00, 0x4959ff3f, 0x20047008, 
+    0x4858e55b, 0xf990b510, 0xb2810000, 0x1f00484c, 0xff35f027, 0x78014854, 0x1e804849, 0xff2ff027, 
+    0xe54a2004, 0xb5104846, 0xf0271f00, 0x494dff25, 0x48437008, 0xf0271e80, 0x494bff1f, 0x20077008, 
+    0xfce9f005, 0xe5382004, 0xb5104848, 0x483c7801, 0xf0271f00, 0x4846ff14, 0x48397801, 0xf0271e80, 
+    0x2004ff0e, 0x4836e529, 0x1f00b510, 0xff04f027, 0x7008493e, 0x1e804832, 0xfefef027, 0x7008493c, 
+    0xf0052007, 0x2004fcc8, 0xe92de517, 0xf8df47f0, 0xf24190e4, 0x220c0800, 0x46414604, 0xf0274648, 
+    0x4e35ff16, 0x4f352801, 0xd10c4d35, 0x683802c1, 0xfeeef028, 0x46412300, 0x4648220c, 0xfef9f027, 
+    0x70302000, 0xf9966028, 0x28040000, 0x6838da7e, 0xf8206829, 0x68284011, 0x60281c40, 0x382a4818, 
+    0xfecaf027, 0x682a6839, 0x8098f8df, 0xf1084c25, 0xf821080e, 0x68280012, 0x60281c40, 0xf0274620, 
+    0x6839febb, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4c1bd9f2, 0xf1043420, 0x46200802, 
+    0x0000e032, 0xf3074190, 0x0002ce46, 0x0004028a, 0x000405d9, 0xf38f20a2, 0xf38f0004, 0x00040244, 
+    0xf23c8074, 0x00041928, 0x00040290, 0xf20308e2, 0xf1000408, 0x0004028b, 0xf1000488, 0x00080400, 
+    0x000402e0, 0x00040242, 0x00040243, 0x000402ec, 0x000402ed, 0xf20351a4, 0x00040334, 0x000405f0, 
+    0x00040328, 0xf2034200, 0xfe76f027, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9be4544, 
+    0x83f8f8df, 0xf1084cfd, 0x4620080e, 0xfe64f027, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 
+    0xd9f24544, 0xf8df4cf6, 0xe00083d8, 0xf108e159, 0x46200814, 0xfe50f027, 0x1ca46839, 0xf821682a, 
+    0x68280012, 0x60281c40, 0xd9f24544, 0x341c4cec, 0x0802f104, 0xf0274620, 0x6839fe3f, 0x682a1ca4, 
+    0x0012f821, 0x1c406828, 0x45446028, 0xf8dfd9f2, 0x4ce48394, 0x0808f108, 0xf0274620, 0x6839fe2d, 
+    0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4cdcd9f2, 0x836cf8df, 0xf1083414, 0x4620081e, 
+    0xfe1af027, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0x834cf8df, 0xf1084cd2, 
+    0x462008d2, 0xfe08f027, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0xf8df4cc9, 
+    0x34608328, 0x0802f1a8, 0xf0274620, 0x6839fdf5, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 
+    0x48c0d9f2, 0xf027300a, 0x6839fde7, 0xf821682a, 0x68280012, 0x60281c40, 0x300c48ba, 0xfddcf027, 
+    0x682a6839, 0x82dcf8df, 0x0850f108, 0x0012f821, 0x1c406828, 0x24006028, 0x0044eb08, 0xfdccf027, 
+    0x1c646839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f12c07, 0x82acf8df, 0xf1082400, 0xeb080820, 
+    0xf0270044, 0x6839fdb9, 0x682a1c64, 0x0012f821, 0x1c406828, 0x2c1f6028, 0x48a4d9f1, 0xfdacf027, 
+    0x682a6839, 0x0012f821, 0x1c406828, 0x489f6028, 0xf0271c80, 0x6839fda1, 0xf821682a, 0x68280012, 
+    0x60281c40, 0x30204899, 0xfd96f027, 0x682a6839, 0x0012f821, 0x1c406828, 0x48946028, 0xf0273026, 
+    0x6839fd8b, 0xf821682a, 0x68280012, 0x60281c40, 0x3040488e, 0xfd80f027, 0x682a6839, 0x0012f821, 
+    0x1c406828, 0x48896028, 0xf0273042, 0x6839fd75, 0x4c86682a, 0x0012f821, 0x1c406828, 0x34786028, 
+    0x0806f104, 0xf0274620, 0x6839fd67, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4c7cd9f2, 
+    0x0804f104, 0xf0274620, 0x6839fd57, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4c74d9f2, 
+    0xf1043432, 0x46200804, 0xfd46f027, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 
+    0x34604c6b, 0x0804f104, 0xf0274620, 0x6839fd35, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 
+    0x4c63d9f2, 0xf104347a, 0x46200804, 0xfd24f027, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 
+    0xd9f24544, 0x34ac4c5a, 0x0804f104, 0xf0274620, 0x6839fd13, 0x682a1ca4, 0x0012f821, 0x1c406828, 
+    0x45446028, 0x484dd9f2, 0xf0271f00, 0x6839fd05, 0xf821682a, 0x68280012, 0x60281c40, 0x1c407830, 
+    0xe8bd7030, 0x4a4b87f0, 0x71fff640, 0x1c406810, 0xf3f1fb90, 0x0013fb01, 0x28006010, 0x4946d105, 
+    0x1c407808, 0x000ff000, 0x47708008, 0x5ff0e92d, 0x46304e42, 0xfce0f027, 0x88914a41, 0xd0484281, 
+    0xf64fd205, 0xeba373ff, 0x44010101, 0xeba0e001, 0x4f3d0101, 0xc0dcf8df, 0x0101f101, 0xb28d8090, 
+    0x68394838, 0x2000f8dc, 0x0000ea45, 0x0022f841, 0xffc9f7ff, 0xa0c4f8df, 0x46b12400, 0xf1aa46e0, 
+    0xf10a0a08, 0xe0220b02, 0xf0274650, 0x4606fcb5, 0xf0274658, 0x683afcb1, 0x4100ea46, 0x0000f8d8, 
+    0x1020f842, 0xffaff7ff, 0x1f004824, 0xfca4f027, 0x46484606, 0xfca0f027, 0xea46683a, 0xf8d84100, 
+    0xf8420000, 0xf7ff1020, 0x1c64ff9e, 0x42acb2a4, 0xe543d3da, 0x2005b570, 0xf8e6f005, 0x4d154c1a, 
+    0x682a6821, 0x0022f841, 0xff8df7ff, 0x68214817, 0x6800682a, 0x0022f841, 0xff85f7ff, 0x30144808, 
+    0xfc7af027, 0x48064606, 0xfc76f027, 0xea466821, 0x682a4000, 0x0022f841, 0x0000e01a, 0xf2039004, 
+    0xf38fffc0, 0xf38f2000, 0xf38f2200, 0xf38e0000, 0xf38f0000, 0x0004031c, 0x0004032c, 0xf23c826c, 
+    0x00040000, 0xeeee0000, 0x000405ec, 0x00040330, 0xff59f7ff, 0xf02748f7, 0x4ef7fc4f, 0x508df100, 
+    0x8831682a, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48f0ff4a, 0xf0271c80, 0x49f0fc3f, 0x4408682a, 
+    0xea408831, 0x68214001, 0x0022f841, 0xff3bf7ff, 0x1d0048e8, 0xfc30f027, 0xf1008831, 0x682a508e, 
+    0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48e1ff2c, 0xf0271d80, 0x49e2fc21, 0x4408682a, 0xea408831, 
+    0x68214001, 0x0022f841, 0xff1df7ff, 0x301048d9, 0xfc12f027, 0xf1008831, 0x682a5095, 0x4001ea40, 
+    0xf8416821, 0xf7ff0022, 0x48d2ff0e, 0xf0273012, 0x49d4fc03, 0x4408682a, 0xea408831, 0x68214001, 
+    0x0022f841, 0xfefff7ff, 0x301448ca, 0xfbf4f027, 0xf1008831, 0x682a5096, 0x4001ea40, 0xf8416821, 
+    0xf7ff0022, 0x48c3fef0, 0xf0273016, 0x49c6fbe5, 0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 
+    0xfee1f7ff, 0x302848bb, 0xfbd6f027, 0xf1008831, 0x682a509d, 0x4001ea40, 0xf8416821, 0xf7ff0022, 
+    0x48b4fed2, 0xf027302a, 0x49b8fbc7, 0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 0xfec3f7ff, 
+    0x302c48ac, 0xfbb8f027, 0xf1008831, 0x682a509e, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48a5feb4, 
+    0xf027302e, 0x49aafba9, 0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 0xfea5f7ff, 0x307a489d, 
+    0xfb9af027, 0xf1008831, 0x682a50a0, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x4896fe96, 0xf027307c, 
+    0x8831fb8b, 0x50a8f100, 0xea40682a, 0x68214001, 0x0022f841, 0xfe87f7ff, 0x307e488e, 0xfb7cf027, 
+    0xf1008831, 0x682a50b0, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x488ffe78, 0xfb6ef027, 0xf1008831, 
+    0x682a50b8, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x4889fe6a, 0xfb60f027, 0xf1008831, 0x682a50c0, 
+    0x4001ea40, 0xf8416821, 0xe8bd0022, 0xe65a4070, 0xb5102005, 0xffa8f004, 0x680a4980, 0xd2034282, 
+    0x681a4b7f, 0x601a1c52, 0xe4096008, 0x5ff0e92d, 0x48704604, 0xf027307a, 0x2204fb3f, 0xf00021f0, 
+    0x4875051f, 0xfb63f027, 0xf7ffb2c7, 0x4e75ffe1, 0xf8df2207, 0xf8df81d4, 0x6831b1d4, 0xf8c84658, 
+    0xf2401000, 0xf0271180, 0xf8dffb52, 0xf04f91c4, 0xb3000a01, 0x46582205, 0xf0272120, 0x2801fb48, 
+    0xf899d10c, 0x42850000, 0x2200d008, 0x211f4658, 0xfb3df027, 0x1000f899, 0xd00c4288, 0x46582205, 
+    0xf0272120, 0xb940fb34, 0x46582200, 0xf027211f, 0x42a8fb2e, 0xf8c6d101, 0x2206a000, 0x2140485b, 
+    0xfb25f027, 0xf899b148, 0x428d1000, 0xf899d105, 0x42870001, 0x2c00d101, 0xf889d073, 0x2c0a5000, 
+    0xb150f8df, 0xf8894d54, 0xd9057001, 0x0000f8db, 0xf8406829, 0xe0104021, 0xd1102c01, 0xf027484f, 
+    0x4607fadb, 0x1e80484d, 0xfad6f027, 0xea47682a, 0xf8db4100, 0xf8400000, 0xf7ff1022, 0x4843fdd4, 
+    0xf2402207, 0xf0271180, 0xb170faf2, 0x2207483f, 0x1180f240, 0xfaebf027, 0x68302801, 0x77fff640, 
+    0xb3e8d010, 0xd0242801, 0xf7ffe026, 0x4d37fe23, 0x46281dad, 0xfab0f027, 0xb2811c40, 0xf0274628, 
+    0xe078faae, 0xd1792801, 0x90c0f8df, 0x220e0381, 0xf0274648, 0xb318facc, 0x30106828, 0xdb2542b8, 
+    0x60302000, 0xf8c82301, 0x220a0000, 0x02994648, 0xf8d8e05f, 0xb1e00000, 0x000cf8d9, 0xd30c42b8, 
+    0xf1f7fbb0, 0x0311fb07, 0xf1016829, 0x45630c10, 0xf8d9d80c, 0x42912008, 0x42b8d808, 0xe001d241, 
+    0xe07ee004, 0x31106829, 0xd23a4281, 0xfde2f7ff, 0xf8dbe041, 0xf04f0000, 0x682a31ff, 0x1022f840, 
+    0xfd71f7ff, 0xf8c96828, 0xf2000008, 0xf8c970ff, 0xe7eb000c, 0xf38f2200, 0x0004032c, 0x11b00000, 
+    0x11d00000, 0x12b00000, 0x12d00000, 0x13b00000, 0x13d00000, 0xf38f2012, 0xf38f0004, 0x00040338, 
+    0x00040330, 0x00040320, 0x00040324, 0xf20351a4, 0x00040000, 0x000405ec, 0x0004031c, 0xf2039028, 
+    0x2000e00c, 0x23016030, 0x0000f8c8, 0x220a48ff, 0xf0270299, 0x6830fa4e, 0xd0072801, 0x220748fb, 
+    0x1180f240, 0xfa53f027, 0xd1202802, 0x220648f7, 0xf0272140, 0xb9d0fa4c, 0x4cf5b9cc, 0x210f2200, 
+    0xf0274620, 0xb190fa44, 0x46202200, 0xf027210f, 0xfa0afa3e, 0xb28cf100, 0x2500f240, 0x2100e005, 
+    0xf0044628, 0x1e64fea9, 0x2c00b2a4, 0x48e9d1f7, 0x21012200, 0xfa2bf027, 0xd1022801, 0x5ff0e8bd, 
+    0xe566e514, 0x200049e4, 0x6008b510, 0x800849e3, 0x600849e3, 0xf0042005, 0x49e2fe47, 0xe6a46008, 
+    0x4ff8e92d, 0xb364f8df, 0x2800f240, 0x46152700, 0x460e2209, 0x46414604, 0x97004658, 0xfa07f027, 
+    0xd1112801, 0x200049d8, 0x72fff640, 0xf8416809, 0x1c407020, 0xd3fa4290, 0x46412300, 0x46582209, 
+    0xf9e7f027, 0xffcef7ff, 0xf2482c01, 0xeb050900, 0xd0162606, 0xd02e2c02, 0xa330f8df, 0x4dcc2c03, 
+    0x0100f242, 0x0801f04f, 0x2cfed02b, 0x2c04d07e, 0x220dd125, 0x4658465c, 0xf9d9f027, 0xd0762801, 
+    0x220fe084, 0x465c4649, 0xf0274658, 0x2800f9d0, 0x220ed015, 0x0100f244, 0xf0274620, 0x2800f9c8, 
+    0x220ad10d, 0x4100f240, 0xf0274620, 0x2800f9c0, 0x48b8d105, 0x48b8e000, 0xf7ff4430, 0xe8bdfe47, 
+    0x220d8ff8, 0x46584654, 0x7002f88a, 0xf9aff027, 0xd1032801, 0x20aaf64a, 0xfa87f7ff, 0xf44f4faf, 
+    0x46ca0000, 0x900046d9, 0x4aa0e00d, 0x46682100, 0xf0043a2a, 0x2801fea6, 0x48a9d0e1, 0xf7ff4430, 
+    0xf884fe25, 0x220f8002, 0x46484651, 0xf98ff027, 0xd1d42801, 0x46280381, 0xf027220e, 0x2800f988, 
+    0x2204d1cd, 0x21104628, 0xf981f027, 0xd1c62800, 0x46282205, 0xf0272120, 0x2800f97a, 0x2203d1bf, 
+    0x21084638, 0xf973f027, 0xd1b82800, 0x46382204, 0xf0272110, 0x2800f96c, 0x2205d1b1, 0x21204638, 
+    0xf965f027, 0xd1aa2800, 0xe001220a, 0xe009e008, 0x4100f240, 0xf0274648, 0x2800f95a, 0xe79ed0b5, 
+    0xe79a4888, 0x30bbf64b, 0xfa2ff7ff, 0xf640220b, 0x46200100, 0xf94bf027, 0xf04f0001, 0x465630dd, 
+    0x7002f88a, 0x4647d007, 0xf04f4683, 0x46ca0802, 0x4900f240, 0xf8dfe056, 0xf44fa1b4, 0x46470100, 
+    0xf1aa4683, 0xf2400a2a, 0x91004800, 0x2101e00b, 0x46684652, 0xfe35f004, 0xd0d02801, 0xb33078b0, 
+    0xf7ff2000, 0x220ffdb3, 0x46204649, 0xf91ff027, 0xd1c42801, 0x46280381, 0xf027220e, 0x2800f918, 
+    0x2204d1bd, 0x21104628, 0xf911f027, 0xd1b62801, 0x22044865, 0xf02721f0, 0x2801f90a, 0x220ad0af, 
+    0x46204641, 0xf903f027, 0xd0d02800, 0x4658e747, 0xfd8cf7ff, 0xe7d670b7, 0xf244220e, 0x46280100, 
+    0xf8f5f027, 0x78b02800, 0x2802d008, 0xf04fd007, 0xf7ff30ee, 0xf886fd7b, 0xe0038002, 0x2000b1c0, 
+    0xfd74f7ff, 0x4651220f, 0xf0274620, 0x2801f8e0, 0x2204d185, 0x21104628, 0xf8d9f027, 0xd1d52801, 
+    0x4649220a, 0xf0274620, 0x2800f8d2, 0xe716d0d4, 0xf7ff4658, 0x70b7fd5b, 0x4844e7e4, 0xf027b510, 
+    0x2200f89b, 0x20014601, 0xfd23f7fd, 0x1c80483f, 0xf892f027, 0x46012200, 0xf7fd2001, 0x483bfd1a, 
+    0xf0271d00, 0x2200f889, 0xe8bd4601, 0x20014010, 0xbd0ff7fd, 0x460cb570, 0x22004615, 0x20014601, 
+    0xfd07f7fd, 0x46212200, 0xf7fd2001, 0x4629fd02, 0x4070e8bd, 0x20012200, 0xbcfbf7fd, 0x41f0e92d, 
+    0xf2482008, 0xf04f0125, 0xf7fd52b8, 0x4d28fcf2, 0xf242220d, 0x46280100, 0xf889f027, 0x4604220c, 
+    0x0100f241, 0xf0274628, 0x4d22f882, 0xf1054204, 0xf1050602, 0xf1050704, 0xd0450406, 0xf027481e, 
+    0x4601f84b, 0xf0274628, 0x481bf84a, 0xf0271c80, 0x4601f843, 0xf0274630, 0x4817f842, 0xf0271d00, 
+    0x4601f83b, 0xf0274638, 0xe027f83a, 0xf20351a4, 0xf23c802a, 0xf23c8260, 0x0004031c, 0x0004032c, 
+    0x00040330, 0x00040338, 0x000405ec, 0x00040000, 0xf2039026, 0xaaaa0000, 0xbbbb0000, 0xf2035040, 
+    0xcccc0000, 0xdddcdddd, 0xf38f0004, 0xf38e002c, 0xf38fffd4, 0xf23c8070, 0xf38f2210, 0x1d8048fe, 
+    0xf80af027, 0xe00c4601, 0x46282100, 0xf807f027, 0x46302100, 0xf803f027, 0x46382100, 0xfffff026, 
+    0x46202100, 0xfffbf026, 0xf02648f4, 0x4601fff5, 0xf02648f3, 0x2004fff4, 0x81f0e8bd, 0xb57048f0, 
+    0xf0261f80, 0x4605ffe9, 0xf02648ed, 0x4604ffe5, 0x380848eb, 0xffe0f026, 0x220149ea, 0x80084beb, 
+    0x880849e9, 0xd0014285, 0x800d701a, 0x780148e8, 0xd001428c, 0x7004701a, 0x1f0048e1, 0xffccf026, 
+    0x48e44601, 0xffcbf026, 0xbd702004, 0xb51048dd, 0x48db8801, 0xf0263808, 0x48dbffc2, 0x48d88801, 
+    0xf0261f80, 0x48dbffbc, 0xffb6f026, 0x48d44601, 0xf0261f00, 0x48d6ffb4, 0x48d17801, 0xffaff026, 
+    0xe4622004, 0x41f0e92d, 0x834cf8df, 0x21022201, 0xf0264640, 0xf108ffcc, 0x46050402, 0x46202201, 
+    0xf0262102, 0xea45ffc4, 0x48c50100, 0xf0263808, 0x4dcaff96, 0x21042202, 0xf0264628, 0x4ec7ffb8, 
+    0x21042202, 0x360a4607, 0xf0264630, 0xea47ffb0, 0x48bb0100, 0xf0261f80, 0x2201ff82, 0x21024620, 
+    0xffa5f026, 0x46042202, 0x46302104, 0xff9ff026, 0x0600ea44, 0x22014640, 0xf0262102, 0x2202ff98, 
+    0x21044604, 0xf0264628, 0x4304ff92, 0x0044ea46, 0x48abb281, 0xf0261f00, 0x2004ff62, 0xe92de76c, 
+    0x48a74ff8, 0xf0263808, 0xb2c4ff57, 0x1f8048a4, 0xff52f026, 0x9000b2c0, 0x1f0048a1, 0xff4cf026, 
+    0xf8dfb2c5, 0x4ea7829c, 0x07a84fa7, 0xf640d570, 0x46380900, 0x46492301, 0xf026220b, 0xf8dfff5a, 
+    0x2206a278, 0x46232140, 0xf0264650, 0xb184ff52, 0xf6412314, 0x22087100, 0x0004f1aa, 0xff49f026, 
+    0x23274895, 0xf2402204, 0x389a31f0, 0xff41f026, 0xf898e003, 0xf0060000, 0xf8dff9dd, 0x2308b23c, 
+    0xf10b2200, 0x211f0b14, 0xf0264658, 0x2324ff32, 0x7100f643, 0x46582208, 0xff2bf026, 0x46cb2300, 
+    0x4649220b, 0xf0264638, 0x2301ff24, 0x220b4659, 0xf0264630, 0x2201ff1e, 0x21024623, 0x465046d1, 
+    0xff17f026, 0x46232207, 0x46482180, 0xff11f026, 0x46592300, 0x4630220b, 0xff0bf026, 0x91dcf8df, 
+    0x21022301, 0x4648461a, 0xff03f026, 0x22009b00, 0x46482101, 0xfefdf026, 0x46482300, 0x21022201, 
+    0xfef7f026, 0x22029b00, 0x46482104, 0xfef1f026, 0xd06d07e8, 0x0900f241, 0x230146ba, 0x220c4649, 
+    0xf0264638, 0x4d64fee6, 0x21082203, 0x1cad4623, 0xf0264628, 0xb17cfede, 0xf6412310, 0x22087100, 
+    0xf0261f28, 0x485cfed6, 0x22042324, 0x31f0f240, 0xf0263898, 0xe003fece, 0x0000f898, 0xf96af006, 
+    0x23084f55, 0x37162200, 0x4638211f, 0xfec1f026, 0xf6432320, 0x22087100, 0xf0264638, 0x2300feba, 
+    0x220c464f, 0x46504649, 0xfeb3f026, 0x46392301, 0x4630220c, 0xfeadf026, 0x46232201, 0x46282102, 
+    0xfea7f026, 0x46232204, 0x46282110, 0xfea1f026, 0x46392300, 0x4630220c, 0xfe9bf026, 0x23014c3f, 
+    0x461a2102, 0x4620340a, 0xfe93f026, 0x22009b00, 0x46202101, 0xfe8df026, 0x46202300, 0x21022201, 
+    0xfe87f026, 0x22029b00, 0x46202104, 0xfe81f026, 0xe4d42004, 0xb5104835, 0x48297801, 0xf0263808, 
+    0x4833fe5e, 0xb2818800, 0x1f804825, 0xfe57f026, 0xe4642004, 0xb5104822, 0xf0263808, 0x492bfe4d, 
+    0x481f7008, 0xf0261f80, 0x4929fe47, 0x20046008, 0x4828e455, 0xf990b510, 0xb2810000, 0x38084818, 
+    0xfe3df026, 0xf9904824, 0xb2810000, 0x1f804814, 0xfe35f026, 0xe4422004, 0xb5104811, 0xf0263808, 
+    0x491cfe2b, 0x480e7008, 0xf0261f80, 0x491afe25, 0x20047008, 0x491ae433, 0xb5102200, 0xe9d14c17, 
+    0x46230100, 0xfec0f028, 0xfdfaf028, 0x4804b281, 0xf0263808, 0xe025fe14, 0xf38f2210, 0xf3cf2008, 
+    0xf23c8078, 0x00040364, 0x00040366, 0x0004036a, 0x00040546, 0xf23d014e, 0xf2035336, 0xf307409a, 
+    0x0004028a, 0xf23c8306, 0xf2035026, 0x00040536, 0x00040538, 0x00040362, 0x00040363, 0x40c38800, 
+    0x000402d0, 0x220049a6, 0xe9d14623, 0xf0280100, 0xf028fe8b, 0xb281fdc5, 0xf02648a2, 0x48a2fde0, 
+    0x48a07801, 0xf0261c80, 0x49a1fdda, 0x7809489f, 0xea407800, 0x489b2101, 0xf0261d00, 0x489dfdd0, 
+    0x48987801, 0xf0261d80, 0x2004fdca, 0x4895e619, 0x1e80b510, 0xfdc0f026, 0x4c97b200, 0xd0081c41, 
+    0xfdfbf028, 0x46232200, 0xfc42f028, 0xe9c24a93, 0x488c0100, 0xfdb0f026, 0x1c41b200, 0xf028d008, 
+    0x2200fdec, 0xf0284623, 0x4a85fc33, 0x0100e9c2, 0x1c804884, 0xfda0f026, 0x4c824983, 0x70081d24, 
+    0xf0264620, 0x4a82fd99, 0x29200a01, 0xd9017011, 0x70102020, 0xf0264620, 0x497cfd8f, 0x48797008, 
+    0xf0261d80, 0x497bfd89, 0x20047008, 0x487ce5d9, 0x7801b510, 0x1e804873, 0xfd81f026, 0x78014879, 
+    0xf0264870, 0x4878fd7c, 0x486e7801, 0xf0261c80, 0x4876fd76, 0x486b7801, 0xf0261d00, 0x4975fd70, 
+    0x78094873, 0xea407800, 0x48660141, 0xf0261d80, 0x2004fd66, 0x4863e5b5, 0x1d80b510, 0xfd5cf026, 
+    0x48604604, 0xf0261e80, 0x4965fd57, 0x485d7008, 0xfd52f026, 0xf0004963, 0x7008000f, 0x1c804859, 
+    0xfd4af026, 0xf0004960, 0x7008000f, 0x1d004855, 0xfd42f026, 0x7008495d, 0x0001f004, 0x7008495c, 
+    0x0040f3c4, 0x7008495b, 0xe58a2004, 0xb510485a, 0x484c7801, 0xf0261e80, 0x4858fd32, 0x48497801, 
+    0xfd2df026, 0xe57c2004, 0xb5104846, 0xf0261e80, 0x4951fd23, 0x48437008, 0xfd1ef026, 0x7008494f, 
+    0xe56e2004, 0xb510484e, 0x483e7801, 0xf0261e80, 0x2004fd16, 0x483be565, 0x1e80b510, 0xfd0cf026, 
+    0x70084947, 0xe55c2004, 0xb5104846, 0x48357801, 0xf0261e80, 0x2004fd04, 0x4832e553, 0x1e80b510, 
+    0xfcfaf026, 0x7008493f, 0xe54a2004, 0xb510483e, 0x482c7801, 0xf0261e80, 0x483cfcf2, 0x48297801, 
+    0xfcedf026, 0xe53c2004, 0xb5104826, 0xf0261e80, 0x4935fce3, 0x48237008, 0xfcdef026, 0x70084933, 
+    0xe52e2004, 0xb5104832, 0x481e7801, 0xf0261e80, 0x4830fcd6, 0x481b7801, 0xfcd1f026, 0xe5202004, 
+    0x2000492b, 0x20047008, 0x48164770, 0x1e80b510, 0xfcc2f026, 0xb2c04928, 0x70082801, 0x2000d102, 
+    0xfbe5f005, 0xe50c2004, 0xb5104823, 0x480d7801, 0xf0261e80, 0x2004fcb4, 0x4820e503, 0x7801b510, 
+    0x1e804808, 0xfcabf026, 0xe4fa2004, 0xb5104805, 0xf0261e80, 0x4919fca1, 0x20047008, 0x0000e4f1, 
+    0x000402d8, 0xf23c8072, 0x000402cf, 0x000405be, 0x000405bd, 0x000405bf, 0x40c38800, 0x000402d0, 
+    0x00040534, 0x000405fc, 0x000405fd, 0x00040535, 0x000405fe, 0x000405ff, 0x0004053c, 0x0004053d, 
+    0x0004053e, 0x000402f6, 0x00040544, 0x00040545, 0x000402f8, 0x000402fa, 0x00040556, 0x000402e2, 
+    0xf01db510, 0xf016f897, 0xf000fee5, 0xf000f88c, 0xf022fee3, 0x2001fad6, 0x0000bd10, 0x48ffb570, 
+    0x31b4f64b, 0xfc5bf026, 0x210048fd, 0xfc57f026, 0x240048fc, 0x70042501, 0x700548fb, 0x700448fb, 
+    0x600448fb, 0x600448fb, 0x700448fb, 0x800448fb, 0x800448fb, 0x700448fb, 0x700448fb, 0x700448fb, 
+    0xf0044620, 0x49faf8c9, 0x48fa7008, 0x48fa7004, 0xb1007800, 0x49f92020, 0x48f98008, 0x700449fd, 
+    0x700448f8, 0x700448f8, 0x700548f8, 0x700548f8, 0xf881203c, 0xf8814021, 0xf8814022, 0x73cc4020, 
+    0x744c7408, 0x74cc748c, 0x7548750c, 0x75cc758c, 0x764c760c, 0x76cc7688, 0x774c770c, 0x72c8728c, 
+    0x734c730c, 0x714c738c, 0x71cc7188, 0x724c720c, 0x48e949ea, 0x49eb6008, 0x600848e9, 0x880048ea, 
+    0xd0072801, 0x0001f04f, 0x700849e8, 0xf04fd105, 0xe0040002, 0x0002f04f, 0xf04fe7f6, 0x49e40001, 
+    0xf2407008, 0x48e32144, 0xfbe9f026, 0xf24149e2, 0x80084000, 0x49e248e1, 0x60086800, 0x20bef44f, 
+    0x600849e0, 0xb510bd70, 0xfc35f007, 0x1e942201, 0x46212005, 0xf83ef004, 0x46212201, 0xf0042000, 
+    0xf023f839, 0xf7fff974, 0xf7fdff69, 0xf009f870, 0xf016f8d7, 0x2001ffe1, 0xf940f00a, 0xfb8cf022, 
+    0xfdb1f024, 0xfac8f004, 0x210448ac, 0xf026384c, 0xe8bdfbb6, 0xf0054010, 0xe92db93f, 0xf8df47f0, 
+    0x28049328, 0x4617461e, 0xa020f8dd, 0x4604460d, 0x4800f640, 0x2c05d017, 0x2000d027, 0xfb3df005, 
+    0x4632462b, 0x46204639, 0xfb9cf005, 0x46202100, 0xfc09f005, 0x46412300, 0x4648220a, 0xfba9f026, 
+    0x46082100, 0x4608e027, 0xfb27f005, 0x4632462b, 0x46204639, 0xfb86f005, 0x2100b12f, 0xf0054620, 
+    0x2302fbf2, 0x4651e010, 0x4608e7f8, 0xfb15f005, 0x4632462b, 0x46204639, 0xfb74f005, 0x2100b1b6, 
+    0xf0054620, 0x2301fbe0, 0x220a4641, 0xf0264648, 0x2101fb80, 0xf01a4608, 0xf505f819, 0xe8bd7100, 
+    0xf04f47f0, 0x12505280, 0xbfe3f7fc, 0xe7e74651, 0x47f0e92d, 0x489d0005, 0x0400f04f, 0x7004468a, 
+    0x7004489b, 0x7004489b, 0x7004489b, 0x7004489b, 0x7004489b, 0x489bd124, 0x7004499e, 0x7004489a, 
+    0x7004489a, 0x7004489a, 0x70082004, 0x7008499a, 0x7008499a, 0x7008499a, 0x7004489a, 0x7004489a, 
+    0x7004489a, 0x7004489a, 0x7004489a, 0x7004489a, 0x7004489a, 0x7004489a, 0x7004489a, 0x7004489a, 
+    0x489a2701, 0x489a7007, 0x489a7007, 0x489a7007, 0x489a7007, 0x489a7007, 0x489a7007, 0x489a7007, 
+    0x489a7007, 0x489a7004, 0x489a7004, 0x489a7004, 0x489a7004, 0x489a7004, 0x489a7004, 0x489a7004, 
+    0x489a7004, 0x489a7004, 0x489a8004, 0x489a8004, 0x489a7004, 0x489a7004, 0x489a7004, 0x489a7004, 
+    0x489a7004, 0x20038004, 0xfcccf007, 0xf0072000, 0x2001fce5, 0xfcaaf007, 0x21004895, 0x4011f820, 
+    0xb2491c49, 0xdbf92904, 0xf0072001, 0x2000fcf5, 0xfcf2f007, 0x488fb935, 0x488f7801, 0xd0202903, 
+    0x70012103, 0xf1ba488d, 0x4a4b0f04, 0xc12cf8df, 0x812cf8df, 0x488a7004, 0x913cf8df, 0x4b8a4949, 
+    0x48887004, 0x4d8a4e89, 0xf8ccd00d, 0xf1ba2000, 0xf8c10f05, 0xd02e8000, 0x68124a86, 0xd04a2a12, 
+    0x7007e11b, 0xf8cce7de, 0xf6442000, 0xf8c172b8, 0xf8a98000, 0x78002000, 0xd0192803, 0x2801b1c8, 
+    0x2802d017, 0x701cd015, 0xeb007818, 0xeb010140, 0xeb061000, 0x602800c0, 0x79827901, 0x44117f04, 
+    0x7d877942, 0x7ec1440a, 0x7e441b09, 0xe020443c, 0x70182002, 0xf242e7e8, 0xf8a972dc, 0x78002000, 
+    0xd0192803, 0x2801b1b0, 0x2802d014, 0x701cd012, 0xeb007818, 0xeb010140, 0xeb061000, 0x602800c0, 
+    0x79827901, 0x44117f44, 0x440a7942, 0x1b097ec1, 0xe0c17d84, 0xe0cee0cd, 0x0000e0c9, 0xf23c80ba, 
+    0xf23c8322, 0x000402f8, 0x00040314, 0x000405d3, 0x00057f7c, 0x00057f80, 0x0004027d, 0x0004027e, 
+    0x00040280, 0x00040282, 0x00040283, 0x0004028a, 0x0004028b, 0x00040244, 0x00040583, 0x00040288, 
+    0x000402bf, 0x000402c0, 0x0004053e, 0x000405d5, 0x000405d7, 0x0004e178, 0x0003d090, 0x000405e0, 
+    0x1e8c2120, 0x000405e4, 0x00040364, 0x00040312, 0x00040313, 0xf23d014e, 0x000405e8, 0x00040224, 
+    0x000405ec, 0x000405f0, 0xf2030802, 0x00040247, 0x00040248, 0x00040249, 0x0004024a, 0x0004024b, 
+    0x0004024c, 0x0004024d, 0x0004024e, 0x0004024f, 0x00040250, 0x00040251, 0x00040252, 0x00040253, 
+    0x00040254, 0x00040255, 0x00040256, 0x00040257, 0x00040258, 0x00040259, 0x0004025a, 0x0004025b, 
+    0x000402cd, 0x00040f47, 0x00040f48, 0x0004025c, 0x0004025d, 0x0004025e, 0x0004025f, 0x00040260, 
+    0x00040261, 0x00040262, 0x00040263, 0x00040264, 0x00040265, 0x00040266, 0x00040267, 0x00040268, 
+    0x00040269, 0x0004026a, 0x0004026b, 0x0004026c, 0x0004026e, 0x00040270, 0x00040272, 0x00040273, 
+    0x00040274, 0x00040275, 0x00040246, 0x000405a4, 0x000405a6, 0x0004027c, 0x00040290, 0x0004028c, 
+    0x0004028d, 0x000402f6, 0x0004036b, 0x0004036c, 0x000405f8, 0x00040238, 0x83c14421, 0x44217c44, 
+    0x44217d04, 0x442279c4, 0x1c891a51, 0x701fe01f, 0x7018e71e, 0x4af8e71c, 0xf241600a, 0xf8a94200, 
+    0x78002000, 0xd0052803, 0xd07c2800, 0xd07a2801, 0xd0782802, 0x7818701c, 0x0140eb00, 0x1000eb01, 
+    0x00c0eb06, 0x7ec16028, 0x83c13114, 0xf6432178, 0x22007c80, 0x1044f8a0, 0xeb022705, 0xeb000042, 
+    0xeb061002, 0x602800c0, 0x79847901, 0xe01ef8b0, 0x79444421, 0x7c444421, 0xf8904474, 0xeba4e015, 
+    0x8444040e, 0x7c448487, 0xe01ef8b0, 0xf8904474, 0xeba4e015, 0xf890040e, 0xeba4e017, 0x85c4040e, 
+    0x85447b04, 0x86c47b44, 0xf8907ac4, 0x4474e00e, 0x87443440, 0x0448f101, 0x004c8784, 0xf8a01f24, 
+    0x79c44042, 0xe01ef8b0, 0xf8904474, 0x448ee011, 0xf8904474, 0x4474e014, 0xe000f8b0, 0x5400f5c4, 
+    0x049eeb04, 0x4048f8a0, 0xf89079c4, 0x4474e012, 0xe013f890, 0x4474448e, 0x5400f5c4, 0x7a848644, 
+    0xe009f890, 0xf5c44474, 0xf8a05400, 0x7bc4404a, 0xe010f890, 0xf8a04474, 0xebac404c, 0xf8a00444, 
+    0x3c10404e, 0xe020e000, 0x4050f8a0, 0xf8901c52, 0xb2524058, 0xe05bf890, 0xf8904474, 0x4471e05c, 
+    0xe059f890, 0xf8904421, 0x4474405a, 0xf8a01b09, 0x2a03105e, 0x7818db81, 0x0140eb00, 0x1000eb01, 
+    0x00c0eb06, 0xe8bd6028, 0x701887f0, 0xe92de763, 0x48a24ff1, 0xb0822100, 0xf8e1f026, 0x2100489f, 
+    0xf0261f80, 0x489ef8dc, 0x70062600, 0xf0044630, 0xf008fead, 0x9802fd9b, 0xf89cf007, 0x78004899, 
+    0xd0002801, 0xf0192000, 0x2300ff45, 0x461a200f, 0x90004619, 0xf0074618, 0x9902f8b7, 0xf7ff2000, 
+    0x9802fd67, 0x9240f8df, 0x28034d90, 0xd0254c90, 0x0000f899, 0x43087829, 0x488ed124, 0x488e7801, 
+    0xf00a7800, 0x498dfb06, 0x78094a8d, 0x40117812, 0x0100e9cd, 0x7803488b, 0x7800488b, 0x488b4003, 
+    0x488b7802, 0x40027800, 0x7801488a, 0x7800488a, 0x98024001, 0xfad7f00a, 0xe0037020, 0x20224987, 
+    0x80087026, 0x78004886, 0x48869000, 0x78037821, 0x78024885, 0xf7ff9802, 0x7823fcd0, 0xf8df2701, 
+    0x2b03820c, 0xf888d101, 0x48817000, 0x28126800, 0x2816d016, 0x487fd014, 0x96002100, 0x78009a02, 
+    0xb2400040, 0xfb3cf018, 0xff3df016, 0x4d7a7828, 0xd0252803, 0xd0082801, 0x0000f899, 0xe00fb9e0, 
+    0x9a022100, 0x96002004, 0xf016e7ec, 0x702ffcc4, 0x96002100, 0x78234608, 0xf0189a02, 0xe012fb21, 
+    0x7800486e, 0xd00b2802, 0xd0052801, 0x2200486c, 0xf0262101, 0xb118f86c, 0xfcadf016, 0xe002702f, 
+    0xfcb7f016, 0x2200702e, 0x9198f8df, 0x48662103, 0x3000f899, 0xf84df026, 0x0000f899, 0xf8df2200, 
+    0xeb00a190, 0xeb010140, 0x49601000, 0x00c0eb01, 0x0000f8ca, 0xf890210f, 0x485e3068, 0xf839f026, 
+    0xb174f8df, 0x39fff04f, 0x46584649, 0xf811f026, 0x28037820, 0x4859d108, 0x28017800, 0xf04fd06a, 
+    0x465821cc, 0xf805f026, 0x23004955, 0x9000f8c1, 0x260146b1, 0x46324619, 0x6900e9cd, 0xb2407828, 
+    0xfddcf004, 0xf0092002, 0x484efd1a, 0x494f4a4e, 0x808680c6, 0x80068046, 0xf0057823, 0x2172fd59, 
+    0xf7fc05b0, 0x0331fc50, 0x23004e49, 0x4630220c, 0xfffff025, 0xf2422300, 0x220d0100, 0xf0254630, 
+    0x2300fff8, 0x0100f244, 0x4630220e, 0xfff1f025, 0x0700f248, 0x23004630, 0x220f4639, 0xffe9f025, 
+    0x28037820, 0x4833d07e, 0x220f2301, 0x38364639, 0xffdff025, 0x0000f8da, 0x7f8046d3, 0xfda5f006, 
+    0x20004e34, 0xa0b4f8df, 0x88334f33, 0x2000f89a, 0x1000f997, 0xfe87f005, 0x20008833, 0x2000f89a, 
+    0x1000f997, 0xfba0f006, 0xfba6f002, 0x7800481a, 0xe072b108, 0xe06be053, 0x2245cdc0, 0xf23c80b8, 
+    0x00040dec, 0x000402fa, 0x000402ec, 0x0004027c, 0x000405d9, 0x00040317, 0x00040314, 0x00040318, 
+    0x000405ea, 0x000405d5, 0x000405d6, 0x000405d7, 0x000405d8, 0x000405d3, 0x000405d4, 0x00040342, 
+    0x0004033f, 0x00040313, 0x00040312, 0x00040290, 0x00040238, 0x00040251, 0x0004055c, 0x00040243, 
+    0xf2035040, 0x0004036b, 0xf203005e, 0x0004036c, 0x000405f8, 0xf2030448, 0xf1000048, 0x00040310, 
+    0x000402f0, 0x00040590, 0x00040578, 0x000405a6, 0xf20305c0, 0x000402b8, 0x00040234, 0xf04fe002, 
+    0xe73e1133, 0x208049f9, 0x3001f991, 0x0013f82d, 0x3000f991, 0x0013f82d, 0x3003f991, 0xf82d4668, 
+    0xf9919013, 0xf82d1002, 0xf0059011, 0xe771fc05, 0xf2407821, 0xf0021000, 0x2001fb39, 0xfd1ef006, 
+    0x46558833, 0x2000f89a, 0x1000f997, 0xf0057820, 0x8833fdfa, 0xf997782a, 0x78201000, 0xfb14f006, 
+    0x220048e3, 0x71fff240, 0xff41f025, 0xa384f8df, 0xf2402200, 0xf8aa71ff, 0x48dd0000, 0xf0251c80, 
+    0xb201ff36, 0x230048dc, 0x8001461a, 0x0000f9ba, 0xfd7ef004, 0x23022101, 0x22084608, 0xf867f004, 
+    0x0000f8db, 0xf9b046da, 0xf9b01064, 0xf0040066, 0xf8daf839, 0xf8900000, 0xf8902062, 0xf8901061, 
+    0xf0040060, 0xf8dff815, 0x2300b334, 0xf24f220c, 0x46580100, 0xfee6f025, 0xf6402300, 0x22087100, 
+    0xf0254658, 0x2300fedf, 0x22044658, 0xf02521f0, 0x2300fed9, 0x210f4658, 0xf025461a, 0xf8dffed3, 
+    0x230fb2f0, 0x46192200, 0x0b58f10b, 0xf0254658, 0x2300fee0, 0x22074658, 0xf0252180, 0x2300feda, 
+    0x22054658, 0xf0252120, 0x2001fed4, 0xfc8ef019, 0x90008830, 0x782b2000, 0x2000f997, 0xf0197821, 
+    0xf019fba4, 0x2000fb1f, 0xff60f003, 0xff64f003, 0xff7ff003, 0x78284daa, 0xd1012801, 0xfc76f004, 
+    0xfe05f002, 0x98027821, 0xf894f005, 0xf802f006, 0x2301489f, 0x46192200, 0xf0253824, 0x48a1feaa, 
+    0x20007801, 0xfcb5f004, 0x23014899, 0x461a2102, 0xf0253816, 0x2000fe9e, 0xfab6f019, 0x23004e9a, 
+    0x21022201, 0xf0254630, 0x4f98fe94, 0x22012300, 0x46382102, 0xfe8df025, 0x4b71f04f, 0x46582300, 
+    0xf44f2211, 0xf0253100, 0x2301fe6d, 0x22004658, 0xf0254619, 0x2100fe67, 0x0000f244, 0xfafcf003, 
+    0x46582300, 0x461a2101, 0xfe5cf025, 0x46302301, 0x461a2102, 0xfe6df025, 0x46382301, 0x461a2102, 
+    0xfe67f025, 0x20042100, 0xfed6f008, 0xfda9f008, 0x28007828, 0x2002d07e, 0xffa3f008, 0x6800487c, 
+    0xfe7bf027, 0x4b7c4a7b, 0xfedef027, 0xfe18f027, 0x2100b200, 0xfd84f008, 0xf0082000, 0x2001fd2b, 
+    0xfd28f008, 0xf0082002, 0x2003fd25, 0xfd22f008, 0xf9954d72, 0xf0080000, 0xf995fcd9, 0xf0080000, 
+    0x486ffd68, 0xf02521c0, 0x4d6efe1a, 0x0000f995, 0xf023b280, 0x2001fe41, 0xfc78f005, 0x2000f998, 
+    0x200c2100, 0xfbf4f005, 0xf0082000, 0x2001fcfc, 0x46039000, 0x46014602, 0xfd75f008, 0xf0032003, 
+    0x7829fb77, 0x78202200, 0xfe95f009, 0x485f495e, 0x78007809, 0x0100e9cd, 0x7803485d, 0x7802485d, 
+    0x7801485d, 0x7800485d, 0xff89f009, 0xfe73f002, 0xf64f485b, 0xf02571ff, 0x485afde2, 0xb2818800, 
+    0x1c804857, 0xfddbf025, 0x88004857, 0x4854b281, 0xf0253016, 0x4855fdd4, 0xb2818800, 0x1d004850, 
+    0xfdcdf025, 0x2100484e, 0xf0253018, 0x484cfdc8, 0xe0002100, 0x301ae02f, 0xfdc1f025, 0x21004848, 
+    0xf025301c, 0x4846fdbc, 0x301e2100, 0xfdb7f025, 0x23004847, 0x21102204, 0xfdcbf025, 0x0000f8da, 
+    0x106cf8b0, 0x206ef8b0, 0x0042f8b0, 0xeb004411, 0x49400051, 0x20028008, 0xf881493f, 0xf0149000, 
+    0x2300fb00, 0x210f483d, 0xf025461a, 0xe8bdfdb2, 0xf0134ffe, 0x2000bb99, 0xfef3f008, 0x46082100, 
+    0xfcdef008, 0x0000f998, 0xf0084645, 0xf995fc83, 0xf0080000, 0xe768fc3b, 0xf011b510, 0xf00af897, 
+    0xf00bfe61, 0xf00bfc32, 0xf00cfdea, 0xf00efa3c, 0xf00ff930, 0xf00ff8a0, 0xf00ffbe2, 0xf01bff7b, 
+    0xf01df8b5, 0xf01bfbaa, 0xf01cfa65, 0xf021fa53, 0xf01cf84a, 0xf021f842, 0xf022f808, 0xf020fa9f, 
+    0xe8bdfb3e, 0xf0194010, 0x0000bf3f, 0x00040578, 0xf203503a, 0x00040564, 0x00040566, 0xf100004c, 
+    0x0004055c, 0x0004028b, 0xf2031008, 0xf203000a, 0x000402a4, 0xeb851eb8, 0x4054f851, 0x00040291, 
+    0xf2030864, 0x0004028a, 0x000405cf, 0x000405d0, 0x000405db, 0x000405da, 0x000405dd, 0x000405dc, 
+    0xf203513c, 0x00040f60, 0x00040f8c, 0x00057f80, 0xf2035250, 0x00040560, 0x0004033d, 0xf23c8316, 
+    0xe92d500f, 0xe59f0994, 0xfb000d69, 0xe3a02103, 0xe3a01030, 0xe3a00010, 0xfbfff0cc, 0xe3a02103, 
+    0xe3a01031, 0xe3a00010, 0xfbfff0c8, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d4070, 0xe3a00003, 
+    0xfa000d3a, 0xe3a00002, 0xfa000d38, 0xe3a00001, 0xfa000d36, 0xe3a00011, 0xfa000d34, 0xe3a00012, 
+    0xfa000d32, 0xe3a00001, 0xfb000c96, 0xe3a00002, 0xfb000c94, 0xe3a00004, 0xfb000c92, 0xe59f0920, 
+    0xfb000d4b, 0xe59f091c, 0xe3a03001, 0xe3a0200c, 0xe3011000, 0xfb009675, 0xe59f090c, 0xe1d000d0, 
+    0xe3700001, 0x0a00000f, 0xe3a02000, 0xe3a01007, 0xe1a00002, 0xfb0014d8, 0xe59f18f0, 0xe3a00001, 
+    0xe59f28f0, 0xe1c100b6, 0xe1c100b4, 0xe1c100b2, 0xe1c100b0, 0xe59f08d8, 0xe59f18dc, 0xe5d03000, 
+    0xe59f08c8, 0xfa001509, 0xe59f18d0, 0xe3a00000, 0xe59f58cc, 0xe3a02000, 0xe5c10000, 0xe3a0000f, 
+    0xe1c500b0, 0xe2851000, 0xe59f08b8, 0xe5900000, 0xfa0084cc, 0xe59f48b0, 0xe3a02000, 0xe5941000, 
+    0xe0800001, 0xe5840000, 0xe59f08a0, 0xe2851000, 0xe5900000, 0xfa0084c3, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f0884, 0xe2851000, 0xe5900000, 0xfa0084bb, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f0868, 0xe2851000, 0xe5900000, 0xfa0084b3, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f084c, 0xe2851000, 0xe5900000, 0xfa0084ab, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f0830, 0xe2851000, 0xe5900000, 0xfa0084a3, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f0814, 0xe2851000, 0xe5900000, 0xfa00849b, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f07f8, 0xe2851000, 0xe5900000, 0xfa008493, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f07dc, 0xe2851000, 0xe5900000, 0xfa00848b, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe3a00007, 0xe1c500b0, 0xe59f07b8, 0xe2851000, 0xe5900000, 0xfa008481, 
+    0xe5941000, 0xe0800001, 0xe5840000, 0xe8bd8070, 0xe1a01000, 0xe59f0798, 0xe92d4010, 0xe1d000b0, 
+    0xe3500000, 0x13a02103, 0x13011101, 0x1a00001e, 0xe59f2780, 0xe59f0780, 0xe59f4780, 0xe1510002, 
+    0x1a000005, 0xe3a02004, 0xe3a01010, 0xfb0095fe, 0xe20000ff, 0xe3a01011, 0xea00000d, 0xe59f2760, 
+    0xe1510002, 0x1a000005, 0xe3a02005, 0xe3a01020, 0xfb0095f5, 0xe20000ff, 0xe3a01012, 0xea000004, 
+    0xe3a02003, 0xe3a01008, 0xfb0095ef, 0xe20000ff, 0xe3a01001, 0xe3500001, 0xe1c410b2, 0x0a000005, 
+    0xebffff54, 0xe3a02103, 0xe3a01001, 0xe8bd4010, 0xe3a00010, 0xeaffefe4, 0xe3a02103, 0xe3001101, 
+    0xe3a00010, 0xfbfff011, 0xe1d400f2, 0xe3a02103, 0xe2801090, 0xe3a00010, 0xfbfff00c, 0xe59f16e8, 
+    0xe3a02103, 0xe59f06dc, 0xe5d11000, 0xe5d00000, 0xe0800081, 0xe2801c02, 0xe3a00010, 0xfbfff003, 
+    0xe3a00005, 0xe1c400b0, 0xe59f06a0, 0xe3a02000, 0xe59f16a8, 0xe5900000, 0xfa00843a, 0xe59f1668, 
+    0xe5912000, 0xe0800002, 0xe5810000, 0xe3a00004, 0xfb000bd4, 0xe8bd4010, 0xe3a0000b, 0xea000c56, 
+    0xe92d503f, 0xe59f4618, 0xe1a00004, 0xfb000c88, 0xe3a02103, 0xe3a01032, 0xe3a00010, 0xfbffefeb, 
+    0xe1a00004, 0xebffffa9, 0xe3a02103, 0xe3a01033, 0xe3a00010, 0xfbffefe5, 0xf57ff05f, 0xe8bd503f, 
+    0xe25ef004, 0xe92d50ff, 0xe59f0640, 0xfb000c78, 0xe3a02103, 0xe3a01034, 0xe3a00010, 0xfbffefdb, 
+    0xe3a00002, 0xfa000c51, 0xe59f0624, 0xe3a03000, 0xe3a02008, 0xe3001100, 0xfb00959c, 0xe3a03000, 
+    0xe59f0610, 0xe1a02003, 0xe3a0100f, 0xfb009597, 0xe59f05dc, 0xe1d000b0, 0xe3500000, 0x13a02103, 
+    0x13011102, 0x1a000041, 0xe59f05ec, 0xe3a05000, 0xe59f75e8, 0xe59f4590, 0xe5d00000, 0xe3500000, 
+    0x0a000023, 0xe59f05d8, 0xe59f15d8, 0xe59f65d8, 0xe1d000d0, 0xe1d110d0, 0xe1800001, 0xe1d610d0, 
+    0xe1900001, 0x1a000033, 0xe3a00005, 0xfa000b9d, 0xe59f15b8, 0xe240093d, 0xe2400d09, 0xe3a02000, 
+    0xe5810000, 0xe3a00001, 0xe5c60000, 0xe3a0003e, 0xe1c700b0, 0xe2871000, 0xe59f0528, 0xe5900000, 
+    0xfa0083e8, 0xe5941000, 0xe0800001, 0xe5840000, 0xe59f057c, 0xe59f157c, 0xe5d00000, 0xe2800001, 
+    0xe2000007, 0xe0800200, 0xe0810100, 0xe5805008, 0xea000018, 0xe59f0560, 0xe5900000, 0xe3500000, 
+    0x0a000000, 0xeafffffe, 0xe59f0550, 0xe3a02000, 0xe59f1528, 0xe5d00000, 0xe3500003, 0x13500002, 
+    0x059f04b8, 0x05c05000, 0xe3a00009, 0xe1c700b0, 0xe59f04d8, 0xe5900000, 0xfa0083ca, 0xe5941000, 
+    0xe3a02103, 0xe0800001, 0xe3a01002, 0xe5840000, 0xe3a00010, 0xfbffef85, 0xe3a02103, 0xe3a01035, 
+    0xe3a00010, 0xfbffef81, 0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xe92d503f, 0xe59f04e4, 0xfb000c14, 
+    0xe3a02103, 0xe3a01036, 0xe3a00010, 0xfbffef77, 0xe59f047c, 0xe1d000b0, 0xe3500000, 0x0a00000a, 
+    0xe3a02103, 0xe3011103, 0xe3a00010, 0xfbffef6f, 0xe3a02103, 0xe3a01037, 0xe3a00010, 0xfbffef6b, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe59f0468, 0xe5d00000, 0xe3500000, 0x0afffff4, 0xe59f0460, 
+    0xe59f2460, 0xe1d010d0, 0xe1d220d0, 0xe1911002, 0x1affffee, 0xe3a04001, 0xe5c04000, 0xe59f0464, 
+    0xe3a03000, 0xe1a02004, 0xe3a01002, 0xfb00951f, 0xe3a00000, 0xfa000d8d, 0xe59f044c, 0xe5d00000, 
+    0xe3500000, 0x1a000003, 0xe3a00802, 0xe3001803, 0xfbffef27, 0xfa002074, 0xe3a00001, 0xfa006fa6, 
+    0xe59f040c, 0xe59f140c, 0xe5d00000, 0xe2800001, 0xe2000007, 0xe0800200, 0xe0810100, 0xe5804008, 
+    0xe3a00005, 0xfa000b27, 0xe59f13e0, 0xe240093d, 0xe2400d09, 0xe5810000, 0xe3a00000, 0xe59f135c, 
+    0xe5c10000, 0xe3a00002, 0xfa000bb0, 0xe3a00003, 0xfa000bae, 0xe59f0398, 0xe3a03000, 0xe3a02008, 
+    0xe3001100, 0xfb0094f9, 0xe3a02007, 0xe3a01000, 0xe3a00001, 0xfb0014b7, 0xe59f13b0, 0xe3a00043, 
+    0xe3a02000, 0xe1c100b0, 0xe59f0318, 0xe5900000, 0xfa008364, 0xe59f1310, 0xe5912000, 0xe0800002, 
+    0xe5810000, 0xeaffffb1, 0xe92d5fff, 0xe3a02103, 0xe3a01038, 0xe3a00010, 0xfbffef1c, 0xe59f0370, 
+    0xe3a0200e, 0xe3041000, 0xfb0094e7, 0xe59f4364, 0xe3500000, 0xe59fb360, 0x13a00000, 0x1a000003, 
+    0xe3a0200e, 0xe3041000, 0xe1a00004, 0xfb0094de, 0xe5cb0000, 0xe59f0344, 0xfa0094c6, 0xe1a08000, 
+    0xe3a0200c, 0xe3011000, 0xe1a00004, 0xfb0094d6, 0xe59f932c, 0xe5c90000, 0xe59f0328, 0xfa0094bd, 
+    0xe6bf6070, 0xe59f0320, 0xfa0094ba, 0xe6bf4070, 0xe3140080, 0x159f1314, 0x13a00001, 0x15c10000, 
+    0xe59f030c, 0xfa0094b3, 0xe6bf5070, 0xe59f0304, 0xfa0094b0, 0xe6bf7070, 0xe3a02000, 0xe1a01004, 
+    0xe3a00001, 0xfbffeef1, 0xe3a02000, 0xe1a01005, 0xe3a00001, 0xfbffeeed, 0xe3a02000, 0xe1a01006, 
+    0xe3a00001, 0xfbffeee9, 0xe59fa244, 0xe5da0000, 0xe3100018, 0x0a000006, 0xe3e00000, 0xfa0021fd, 
+    0xe59f22b4, 0xe3041004, 0xe3a00004, 0xfbffeedf, 0xea000042, 0xe5db1000, 0xe3a02000, 0xe3a00001, 
+    0xfbffeeda, 0xe5db1000, 0xe2053c01, 0xe1da00b0, 0xe3510000, 0x13800080, 0x03c00080, 0xe1ca00b0, 
+    0xe3150b01, 0x13510000, 0xe2040010, 0x03a02000, 0x13a02001, 0xe1900003, 0x13160010, 0x0a000003, 
+    0xe5d90000, 0xe3500000, 0x03a00001, 0x0a000000, 0xe3a00000, 0xe204c020, 0xe193300c, 0x13160020, 
+    0x0a000003, 0xe5d93000, 0xe3530000, 0x03a03001, 0x0a000000, 0xe3a03000, 0xe3520000, 0x1a000005, 
+    0xe59f2218, 0xe1d220d0, 0xe1911002, 0x1a000007, 0xe1900003, 0x0a000005, 0xe59f0204, 0xe1d010d0, 
+    0xe3510003, 0x13510004, 0x13510005, 0x0bfffde9, 0xe3180003, 0x0a000011, 0xe3e00000, 0xfa0021c5, 
+    0xe59f01e0, 0xe3a0106d, 0xe3a02000, 0xe1c040b2, 0xe1c060b4, 0xe1c050b6, 0xe1c070b8, 0xe1c010b0, 
+    0xe2801000, 0xe59f01c0, 0xe5900000, 0xfa0082dd, 0xe59f10f4, 0xe5912000, 0xe0800002, 0xe5810000, 
+    0xe3a02103, 0xe3a01039, 0xe3a00010, 0xfbffee97, 0xe59f0198, 0xfb000b2e, 0xf57ff05f, 0xe8bd5fff, 
+    0xe25ef004, 0xe92d500f, 0xe59f0184, 0xfb000b28, 0xe3a02103, 0xe3a0103a, 0xe3a00010, 0xfbffee8b, 
+    0xe3a02103, 0xe3a0103b, 0xe3a00010, 0xfbffee87, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 
+    0xe59f0150, 0xfb000b1a, 0xe3a02103, 0xe3a0103c, 0xe3a00010, 0xfbffee7d, 0xe59f113c, 0xe3a00008, 
+    0xe3a02000, 0xe1c100b0, 0xe59f0080, 0xe5900000, 0xfa0082b4, 0xe59f1050, 0xe5912000, 0xe0800002, 
+    0xe5810000, 0xe3a02103, 0xe3a0103d, 0xe3a00010, 0xfbffee6e, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xf0001104, 0xf0001114, 0xf203902c, 0x000402aa, 0x00040590, 0x000405d9, 0x00040578, 0x000405a6, 
+    0x000402ce, 0x0004065c, 0x00040f7c, 0x0004023c, 0x000406a4, 0x000406b4, 0x000406c4, 0x000406d4, 
+    0x000406f0, 0x00040704, 0x00040714, 0x00040724, 0x00040734, 0x00040288, 0xf0001214, 0xf2035040, 
+    0x00040664, 0xf0001224, 0x00040318, 0x000405ea, 0xf0001124, 0xf2035126, 0xf20352a0, 0x00040f44, 
+    0x00040614, 0x000402cd, 0x00040f47, 0x00040f48, 0x000402b4, 0x00040f60, 0x00041708, 0x00057f70, 
+    0x000405d2, 0xf0001134, 0xf2035114, 0x0004055c, 0x0004061c, 0xf2060000, 0xf38fffc0, 0x00040285, 
+    0xf2039048, 0x00040284, 0xf2039026, 0xf2039028, 0x00040286, 0xf2039018, 0xf2039016, 0xcccc0000, 
+    0x0004027d, 0x0004028a, 0x0004e1e0, 0x000411bc, 0xf0001144, 0xf0001154, 0xf0001164, 0x00040624, 
+    0xe92d500f, 0xe59f0c98, 0xfb000ac1, 0xe3a02103, 0xe3a0103e, 0xe3a00010, 0xfbffee24, 0xebfffd5d, 
+    0xe3a02103, 0xe3a01007, 0xe3a00402, 0xfbffee1f, 0xe3a02103, 0xe3a0103f, 0xe3a00010, 0xfbffee1b, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0c50, 0xfb000aae, 0xe3a02103, 0xe3a01040, 
+    0xe3a00010, 0xfbffee11, 0xe3a02103, 0xe3a01041, 0xe3a00010, 0xfbffee0d, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d50ff, 0xe59f0c1c, 0xfb000aa0, 0xe59f0c18, 0xfa0093bf, 0xe3500000, 0x0a00001c, 
+    0xe59f4c0c, 0xe3a01001, 0xe1a00004, 0xfb0093ba, 0xe284000c, 0xe3a01000, 0xfb0093b7, 0xe30b1bbb, 
+    0xe1a00004, 0xfb0093b4, 0xe59f4be8, 0xe3a00062, 0xe1c400b0, 0xe59f0be0, 0xfa0093ae, 0xe1c400b2, 
+    0xe2841000, 0xe59f0bd4, 0xe3a02000, 0xe5900000, 0xfa00822c, 0xe51f11d0, 0xe5912000, 0xe0800002, 
+    0xe5810000, 0xe59f0bb8, 0xe30f1fff, 0xfb0093a2, 0xea00003e, 0xe59f0bac, 0xfa00939e, 0xe3500000, 
+    0x0a00003a, 0xe59f6ba0, 0xe1a00006, 0xfa009399, 0xe51f122c, 0xe1b007a0, 0xe51f41ec, 0xe2865074, 
+    0xe5c10000, 0x0a00002b, 0xe3a03000, 0xe3a0200f, 0xe3081000, 0xe1a00006, 0xfb00939c, 0xe3a03001, 
+    0xe3a0200b, 0xe3001800, 0xe1a00006, 0xfb009397, 0xe59f0b58, 0xe5d00000, 0xe3500000, 0x1a000013, 
+    0xe1a00006, 0xfa009383, 0xe59f1b44, 0xe7e006d0, 0xe5c10000, 0xe1a00006, 0xfa00937e, 0xe59f1b34, 
+    0xe7e00550, 0xe5c10000, 0xe1a00006, 0xfa009379, 0xe59f1b24, 0xe7e203d0, 0xe5c10000, 0xe1a00006, 
+    0xfa009374, 0xe59f1b14, 0xe7e102d0, 0xe5c10000, 0xe3081000, 0xe1a00005, 0xfb00936f, 0xe1d400b0, 
+    0xe3800010, 0xe1c400b0, 0xe3a00004, 0xfa000a27, 0xebfffce8, 0xea000005, 0xe30f1fff, 0xe1a00005, 
+    0xfb009365, 0xe1d400b0, 0xe3c00010, 0xe1c400b0, 0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xe92d500f, 
+    0xe59f0abc, 0xfb000a3a, 0xe3a02103, 0xe3a01085, 0xe3a00010, 0xfbffed9d, 0xe3a0000a, 0xfa000a13, 
+    0xe59f0aa0, 0xe3a03000, 0xe3a0200a, 0xe3001400, 0xfa009353, 0xe59f0a90, 0xe3a03000, 0xe3a0200a, 
+    0xe3001400, 0xfa00934e, 0xe51f0290, 0xe5d00000, 0xe3500001, 0x151f02c0, 0x15d00000, 0x13500001, 
+    0x0a000007, 0xebfffcc3, 0xe3a02103, 0xe3a01086, 0xe3a00010, 0xfbffed85, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe59f1a44, 0xe3a00006, 0xe3a02000, 0xe1c100b0, 0xe51f036c, 0xe5900000, 0xfa0081b9, 
+    0xe51f139c, 0xe5912000, 0xe0800002, 0xe5810000, 0xeaffffec, 0xe92d50ff, 0xe59f0a14, 0xe3a04001, 
+    0xfb000a0b, 0xe51f634c, 0xe3a05001, 0xe5d60000, 0xe3500001, 0x0a000002, 0xe3500002, 0x0a00001e, 
+    0xea00003e, 0xe3a02103, 0xe3a01042, 0xe3a00010, 0xfbffed66, 0xe51f03c8, 0xe1d000b0, 0xe3500000, 
+    0x0a000008, 0xe3a02103, 0xe3001176, 0xe3a00010, 0xfbffed5e, 0xe3a02103, 0xe3a01043, 0xe3a00010, 
+    0xfbffed5a, 0xea00002d, 0xe59f09a8, 0xfa009311, 0xe1a01000, 0xe3a02000, 0xe3a00010, 0xfbffed53, 
+    0xe3a03001, 0xe59f0990, 0xe3a02000, 0xe1a01003, 0xfb009316, 0xebfffc87, 0xeaffffed, 0xe3a00001, 
+    0xfb00161b, 0xe59f0974, 0xfb001157, 0xe59f196c, 0xe3a00000, 0xe30a25bd, 0xe7913100, 0xe2800001, 
+    0xe20000ff, 0xe1530002, 0x83a04000, 0xe3500004, 0x3afffff8, 0xe59f0948, 0xe3540000, 0x15d01000, 
+    0xe5d00000, 0x11c51001, 0x03a01000, 0xe1c52220, 0xe51f042c, 0xe5d00000, 0xfb0006e7, 0xe59f0924, 
+    0xe5d00000, 0xe3500001, 0x9a000004, 0xe3a03001, 0xe51f0450, 0xe1a02003, 0xe3a01002, 0xfb0092f3, 
+    0xe59f0904, 0xe1d000d0, 0xe3500003, 0x13500005, 0x13500004, 0x1a000004, 0xe59f08f0, 0xe5d00000, 
+    0xe3500001, 0x051f050c, 0x05c05000, 0xe3a00000, 0xe5c60000, 0xe3a0000b, 0xfa000994, 0xf57ff05f, 
+    0xe8bd50ff, 0xe25ef004, 0xe92d500f, 0xe59f08c0, 0xfb0009af, 0xe3a02103, 0xe3a01087, 0xe3a00010, 
+    0xfbffed12, 0xe3a0000c, 0xfa000988, 0xe59f0874, 0xe3a03000, 0xe3a0200c, 0xe3011000, 0xfa0092c8, 
+    0xe59f0864, 0xe3a03000, 0xe3a0200c, 0xe3011000, 0xfa0092c3, 0xebfffc3f, 0xe3a02103, 0xe3a01088, 
+    0xe3a00010, 0xfbffed01, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0858, 0xfb000994, 
+    0xe3a02103, 0xe3a01044, 0xe3a00010, 0xfbffecf7, 0xe3a02103, 0xe3a01045, 0xe3a00010, 0xfbffecf3, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe3a02103, 0xe3a0107f, 0xe3a00010, 0xfbffeceb, 
+    0xe59f0814, 0xfb000982, 0xe3a02103, 0xe3a01080, 0xe3a00010, 0xfbffece5, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f07f0, 0xfb000978, 0xe3a02103, 0xe3a0104a, 0xe3a00010, 0xfbffecdb, 
+    0xe3a02103, 0xe3a0104b, 0xe3a00010, 0xfbffecd7, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 
+    0xe59f07bc, 0xfb00096a, 0xe3a02103, 0xe3a01083, 0xe3a00010, 0xfbffeccd, 0xe3a02103, 0xe3a01084, 
+    0xe3a00010, 0xfbffecc9, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe51f4648, 0xe1a00004, 
+    0xfb00095b, 0xe3a02103, 0xe3a01023, 0xe3a00010, 0xfbffecbe, 0xe1a00004, 0xebfffc7c, 0xe3a02103, 
+    0xe3a01024, 0xe3a00010, 0xfbffecb8, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d503f, 0xe51f4680, 
+    0xe1a00004, 0xfb00094a, 0xe3a02103, 0xe3a01025, 0xe3a00010, 0xfbffecad, 0xe1a00004, 0xebfffc6b, 
+    0xe3a02103, 0xe3a01026, 0xe3a00010, 0xfbffeca7, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d500f, 
+    0xe59f0700, 0xfb00093a, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f06ec, 0xfb000934, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f06d8, 0xfb00092e, 0xe3a02103, 0xe3a01085, 
+    0xe3a00010, 0xfbffec91, 0xe3a02103, 0xe3a01086, 0xe3a00010, 0xfbffec8d, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f06a4, 0xfb000920, 0xe3a02103, 0xe3a01058, 0xe3a00010, 0xfbffec83, 
+    0xe3a02103, 0xe3a01059, 0xe3a00010, 0xfbffec7f, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 
+    0xe59f0670, 0xfb000912, 0xe3a02103, 0xe3a0105e, 0xe3a00010, 0xfbffec75, 0xe59f065c, 0xfa00922a, 
+    0xe59f4658, 0xe584000c, 0xe59f0654, 0xfa009226, 0xe6ff2070, 0xe1c420b6, 0xe594000c, 0xe1b01fa0, 
+    0xe5c41002, 0x1a000057, 0xe7e11d50, 0xe5c41000, 0xe7e41850, 0xe5c41001, 0xe1a01800, 0xe1c400b8, 
+    0xe3a00010, 0xfbffec61, 0xe1d400d0, 0xe3500001, 0x0a000004, 0xe3500003, 0x05d40001, 0x03500001, 
+    0x0a000039, 0xea000047, 0xe1d410d1, 0xe3510007, 0x1a000024, 0xe1d420f8, 0xe30f3ff8, 0xe6ff0072, 
+    0xe1500003, 0x1309302a, 0x11500003, 0x1a00000f, 0xe1d400b6, 0xe3a01007, 0xe1d11000, 0x0a000039, 
+    0xe2001027, 0xe59f05bc, 0xe3510022, 0x03a03001, 0x0a000002, 0xe3510002, 0x03a03000, 0x1a000031, 
+    0xe3a02008, 0xe3001100, 0xfb009208, 0xea00002d, 0xe30f3fe0, 0xe1500003, 0x1a000007, 0xe1d400b6, 
+    0xe3100902, 0x0a000027, 0xe59f057c, 0xe3a03001, 0xe3a02002, 0xe3a01004, 0xeafffff2, 0xe1a00802, 
+    0xe1b00820, 0x0a000002, 0xe351001e, 0x1a00001d, 0xea000004, 0xe1d400b6, 0xe3100902, 0x13a00001, 
+    0x1b0095ce, 0xea000017, 0xe1d400b8, 0xe3041191, 0xe6ff0070, 0xe1500001, 0x1a000012, 0xe5d40006, 
+    0xe3100001, 0x0a00000f, 0xeafffffe, 0xe1d400b8, 0xe3a01001, 0xe59f2514, 0xe6ff0070, 0xe3500089, 
+    0x05c21000, 0x0a000007, 0xe350008a, 0x05c21001, 0x0a000004, 0xe350008b, 0x05c21002, 0x0a000001, 
+    0xe350008c, 0x05c21003, 0xe3a02103, 0xe3a0105f, 0xe3a00010, 0xfbffec0d, 0xf57ff05f, 0xe8bd503f, 
+    0xe25ef004, 0xe92d500f, 0xe3a02103, 0xe3a01060, 0xe3a00010, 0xfbffec05, 0xe59f04b4, 0xfb00089c, 
+    0xe3a02103, 0xe3a01061, 0xe3a00010, 0xfbffebff, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 
+    0xe3a02103, 0xe3a0107c, 0xe3a00010, 0xfbffebf7, 0xfb0011b6, 0xe59f047c, 0xfb00088d, 0xe3a01001, 
+    0xe3a00008, 0xfa00119a, 0xe3a00000, 0xfa0011bc, 0xe3a0001e, 0xfa000865, 0xe3a0001f, 0xfa000863, 
+    0xebfffb24, 0xe3a02103, 0xe3a0107d, 0xe3a00010, 0xfbffebe6, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f0430, 0xfb000879, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f041c, 
+    0xfb000873, 0xe3a0001f, 0xfb000858, 0xe59f1410, 0xe21000ff, 0xe5c10000, 0x1a000004, 0xe59f0404, 
+    0xe3a03000, 0xe3a0200a, 0xe3001400, 0xfb009197, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 
+    0xe59f03e4, 0xfb000862, 0xe3a02103, 0xe3a0106a, 0xe3a00010, 0xfbffebc5, 0xe3a02103, 0xe3a0106b, 
+    0xe3a00010, 0xfbffebc1, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe59f03b0, 0xfb000854, 
+    0xe3a02103, 0xe3a0104c, 0xe3a00010, 0xfbffebb7, 0xe3a00021, 0xfb000835, 0xe59f1394, 0xe6af0070, 
+    0xe51f4a94, 0xe3500000, 0xe5c10000, 0xe1d400b0, 0x0a00001a, 0xe3500000, 0x0a00001e, 0xe59f1374, 
+    0xe3a00023, 0xe3a02000, 0xe1c100b0, 0xe51f0ac4, 0xe5900000, 0xfa007fe3, 0xe51f1af4, 0xe5912000, 
+    0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3001110, 0xe3800002, 0xe1c400b0, 0xe3a00010, 
+    0xfbffeb9a, 0xe3a02103, 0xe3a0104d, 0xe3a00010, 0xfbffeb96, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 
+    0xe3d00002, 0xe1c400b0, 0x0bfffaca, 0xe3a02103, 0xe3a01010, 0xeafffff0, 0xebfffac6, 0xeaffffe9, 
+    0xe92d503f, 0xe59f02f0, 0xfb000821, 0xe3a02103, 0xe3a01068, 0xe3a00010, 0xfbffeb84, 0xe51f0af0, 
+    0xe3a0200e, 0xe3041000, 0xfb00914f, 0xe51f4ad4, 0xe3500000, 0x13a00022, 0x1b009522, 0xe5c40000, 
+    0xe31000ff, 0xe51f4b78, 0xe1d400b0, 0x0a00001a, 0xe3500000, 0x0a000022, 0xe59f12a0, 0xe3a00022, 
+    0xe3a02000, 0xe1c100b0, 0xe51f0ba0, 0xe5900000, 0xfa007fac, 0xe51f1bd0, 0xe5912000, 0xe0800002, 
+    0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3001111, 0xe3800001, 0xe1c400b0, 0xe3a00201, 0xfbffeb63, 
+    0xe3a02103, 0xe3a01069, 0xe3a00010, 0xfbffeb5f, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3c00001, 
+    0xe3a01011, 0xe3a02103, 0xe1c400b0, 0xe3a00201, 0xfbffeb56, 0xe1d400b0, 0xe3500000, 0x0bfffa8d, 
+    0xeaffffee, 0xebfffa8b, 0xeaffffe5, 0xe92d500f, 0xe59f020c, 0xfb0007e6, 0xe3a02103, 0xe3a01052, 
+    0xe3a00010, 0xfbffeb49, 0xe3a02103, 0xe3a01053, 0xe3a00010, 0xfbffeb45, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d50ff, 0xe3a02103, 0xe3a0105a, 0xe3a00010, 0xfbffeb3d, 0xe59f01c8, 0xfb0007d4, 
+    0xe59f61c4, 0xe3a03001, 0xe1a02003, 0xe3a01002, 0xe1a00006, 0xfb0090fd, 0xe59f51b0, 0xe3a00001, 
+    0xe5c50000, 0xfb005212, 0xe59f01a4, 0xe3a02000, 0xe1d010b0, 0xe3a00010, 0xfbffeb2c, 0xe59f0194, 
+    0xe3a02005, 0xe51f4cb8, 0xe3a01020, 0xe5d00000, 0xe3500000, 0xe1d400b0, 0x03a03000, 0x13a03001, 
+    0x03c00020, 0x13800020, 0xe1c400b0, 0xe59f0168, 0xfb0090e6, 0xe59f0164, 0xe5d00000, 0xe3500000, 
+    0xe1d400b0, 0x03c00040, 0x13800040, 0xe1c400b0, 0xe6ff0070, 0xe3d00060, 0x0a000051, 0xe3a02103, 
+    0xe3a01022, 0xe3a00010, 0xfbffeb10, 0xe3a03000, 0xe3a02001, 0xe3a01002, 0xe1a00006, 0xfb0090d3, 
+    0xe3a00000, 0xe5c50000, 0xe3a02103, 0xe3a0105b, 0xe3a00010, 0xfbffeb05, 0xf57ff05f, 0xe8bd50ff, 
+    0xe25ef004, 0xf0001174, 0xf0001184, 0xf0001194, 0xf23c8082, 0xf23c806e, 0x0004062c, 0xf23c800a, 
+    0x00040f38, 0xf23c807e, 0xf23c8084, 0xf23c800c, 0x000402ab, 0x000405a0, 0x000405a1, 0x000405a2, 
+    0x000405a3, 0xf00011a4, 0xf0001030, 0xf0001034, 0x00040634, 0xf00011b4, 0xf38f0004, 0xf38f20e0, 
+    0x00041458, 0x000402c1, 0x000402c3, 0x00040244, 0x000402cf, 0xf00011c4, 0xf00011d4, 0xf00011e4, 
+    0xf00011f4, 0xf0001204, 0xf0001234, 0xf0001244, 0xf0001254, 0xf0001274, 0xf00012a4, 0xf1000288, 
+    0x00040604, 0xf100028c, 0xf23c8038, 0xf23c830c, 0x00040547, 0xf00012b4, 0xf00012c4, 0xf00012e4, 
+    0xf00012f4, 0x000402ca, 0xf20350f6, 0xf0001304, 0xf0001314, 0x00040282, 0x0004063c, 0xf0001324, 
+    0x00040644, 0xf0001334, 0xf0001344, 0xf23c801c, 0x00040586, 0x00040584, 0x00040583, 0xf38f2054, 
+    0x00040581, 0xebfff9fb, 0xeaffffb6, 0xe92d503f, 0xe59f0478, 0xfb000756, 0xe3a02103, 0xe3a0104e, 
+    0xe3a00010, 0xfbffeab9, 0xe59f0464, 0xfa009071, 0xe59f1460, 0xe200001f, 0xe1c100b0, 0xe59f1458, 
+    0xe1d120f0, 0xe1500002, 0x0a000018, 0xe51f4ea0, 0xe3500000, 0xe1c100b0, 0xe1d400b0, 0x0a00001a, 
+    0xe3500000, 0x0a000022, 0xe59f1430, 0xe3a00021, 0xe3a02000, 0xe1c100b0, 0xe51f0ed0, 0xe5900000, 
+    0xfa007ee0, 0xe51f1f00, 0xe5912000, 0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3a01012, 
+    0xe3800004, 0xe1c400b0, 0xe3a00201, 0xfbffea97, 0xe3a02103, 0xe3a0104f, 0xe3a00010, 0xfbffea93, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3c00004, 0xe3001112, 0xe3a02103, 0xe1c400b0, 0xe3a00201, 
+    0xfbffea8a, 0xe1d400b0, 0xe3500000, 0x0bfff9c1, 0xeaffffee, 0xebfff9bf, 0xeaffffe5, 0xe92d5fff, 
+    0xe59f039c, 0xfb00071a, 0xe3a02103, 0xe3a01050, 0xe3a00010, 0xfbffea7d, 0xe59f4388, 0xe1a00004, 
+    0xfa009034, 0xe59f6380, 0xe1a006a0, 0xe5c60000, 0xe1a00004, 0xfa00902f, 0xe59f7370, 0xe7e22550, 
+    0xe51f51a8, 0xe51f4f98, 0xe5c72000, 0xe5d51003, 0xe5d60000, 0xe1510000, 0x1a000004, 0xe3500004, 
+    0x1a000023, 0xe5d53004, 0xe1530002, 0x0a000025, 0xe59f933c, 0xe3510000, 0xe51f8ff4, 0x03500007, 
+    0x0a00002a, 0xe59fa32c, 0xe3a03000, 0xe3a0200c, 0xe3011000, 0xe1a0000a, 0xfb009024, 0xe3a03000, 
+    0xe3a0200b, 0xe3001800, 0xe1a0000a, 0xfb00901f, 0xe1d400b0, 0xe3d00008, 0x0a000022, 0xe3a00006, 
+    0xe1c900b0, 0xe59f12e8, 0xe3a02000, 0xe59f02e8, 0xe5900000, 0xfa007e8b, 0xe5981000, 0xe0800001, 
+    0xe5880000, 0xe5d60000, 0xe5c50003, 0xe5d70000, 0xe5c50004, 0xe5d60000, 0xe3500000, 0x01d400b0, 
+    0x03c00008, 0x0a000001, 0xe1d400b0, 0xe3800008, 0xe3a01051, 0xe3a02103, 0xe1c400b0, 0xe3a00010, 
+    0xfbffea3a, 0xf57ff05f, 0xe8bd5fff, 0xe25ef004, 0xe3a0006e, 0xe1c900b0, 0xe59f1274, 0xe3a02000, 
+    0xe59f0278, 0xeaffffe1, 0xebfff96a, 0xeaffffe4, 0xe92d500f, 0xe59f0268, 0xfb0006c5, 0xe3a02103, 
+    0xe3a01074, 0xe3a00010, 0xfbffea28, 0xe3a02103, 0xe3a01075, 0xe3a00010, 0xfbffea24, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0234, 0xfb0006b7, 0xe3a02103, 0xe3a0106c, 0xe3a00010, 
+    0xfbffea1a, 0xe3a02103, 0xe3a0106d, 0xe3a00010, 0xfbffea16, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f0200, 0xfb0006a9, 0xe3a02103, 0xe3a01046, 0xe3a00010, 0xfbffea0c, 0xe3a02103, 
+    0xe3a01047, 0xe3a00010, 0xfbffea08, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe3a02103, 
+    0xe3a01081, 0xe3a00010, 0xfbffea00, 0xe59f01bc, 0xe1d010b0, 0xe3510001, 0x03a01002, 0x01c010b0, 
+    0xe3a00001, 0xfa001469, 0xe3a01000, 0xe3a00040, 0xfa000600, 0xe3a00000, 0xfa001464, 0xe59f0190, 
+    0xe3a0100f, 0xfb008fac, 0xe59f0188, 0xfb000688, 0xe59f0184, 0xe1d000d0, 0xe3500003, 0x13500005, 
+    0x13500004, 0x1a00001a, 0xe59f0170, 0xe3a05000, 0xe59f4170, 0xe5901000, 0xe2811001, 0xe5801000, 
+    0xe59f015c, 0xe5d00000, 0xe3500000, 0x0a000017, 0xe3a00501, 0xe3a01071, 0xfbffe9c9, 0xe1d400b0, 
+    0xe3500014, 0x9a00000a, 0xe3a02103, 0xe3a01081, 0xe3a00010, 0xfbffe9d5, 0xe3a03000, 0xe59f0128, 
+    0xe1a02003, 0xe3a01001, 0xfb008f98, 0xe1c450b0, 0xebfff908, 0xe3a02103, 0xe3a01082, 0xe3a00010, 
+    0xfbffe9ca, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3a00005, 0xfa0005ab, 0xe59f10f0, 0xe5911000, 
+    0xe0400001, 0xe3500000, 0xc1d400b0, 0xc2800001, 0xc1c400b0, 0xd1c450b0, 0xdaffffed, 0xeaffffde, 
+    0xe92d500f, 0xe59f00c8, 0xfb000651, 0xe3a02103, 0xe3a0105c, 0xe3a00010, 0xfbffe9b4, 0xe3a02103, 
+    0xe3a0105d, 0xe3a00010, 0xfbffe9b0, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0094, 
+    0xfb000643, 0xe3a02103, 0xe3a01062, 0xe3a00010, 0xfbffe9a6, 0xe3a02103, 0xe3a01063, 0xe3a00010, 
+    0xfbffe9a2, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xf0001354, 0xf2020012, 0x0004027e, 0x00040280, 
+    0x0004064c, 0xf0001364, 0xf2020108, 0x0004027c, 0x00040580, 0x00040654, 0xf38fffd2, 0x00040734, 
+    0x00040ecc, 0xf0001374, 0xf0001394, 0xf00013a4, 0x000402b0, 0xf20305c4, 0xf00013b4, 0x0004028a, 
+    0x000402ac, 0x00040dec, 0x000405a4, 0xf20305cc, 0x000402b4, 0xf00013c4, 0xf00013d4, 0x4ff0e92d, 
+    0x49ff468b, 0x469ab087, 0x22004690, 0xe9dd6809, 0x880f9510, 0xeb00e02c, 0xf1b80180, 0xeb020f00, 
+    0xdd010441, 0xe0002101, 0x28002100, 0x2302dd01, 0x2308e000, 0x4103fb11, 0xf9334bf2, 0x21006011, 
+    0xfb02e013, 0x42731c07, 0x401cf935, 0xdd01429c, 0xe00046a6, 0x45b6469e, 0x429cda03, 0x4623dd02, 
+    0x4633e000, 0xf8251c49, 0x42b9301c, 0x1c52d3e9, 0xd3d0454a, 0x4ee40079, 0x124aea4f, 0xf109fb01, 
+    0x02c8ea42, 0xea42b20c, 0x4301014b, 0xf0414630, 0x46390780, 0xfe2df023, 0x7100f447, 0xf0234630, 
+    0x2000fe28, 0x21019005, 0x1d33462a, 0xe9cd9004, 0x46211002, 0x90019000, 0xfbbaf000, 0x7180f447, 
+    0xf0234630, 0x0275fe16, 0x126f2400, 0x1c64e002, 0xd20642ac, 0x46392208, 0xf0234630, 0x2800fe21, 
+    0xb007d1f5, 0x8ff0e8bd, 0x4fffe92d, 0xb08348c4, 0x9318f8df, 0xa048f8dd, 0xe9dd6800, 0x88058b10, 
+    0x086fb22e, 0xe0102400, 0xf004fb05, 0x1000f8d9, 0xeb014632, 0xfb170340, 0xeb0af004, 0xeb0b0140, 
+    0xf0230040, 0x1c64fc35, 0x4544b224, 0xf8d9dbec, 0xac031000, 0x8100e9cd, 0x000fe894, 0xff5ef7ff, 
+    0xe92de7cf, 0xb0854fff, 0x90032000, 0x28019805, 0x9807d002, 0x2002b158, 0x92a4f8df, 0x26004683, 
+    0xf8d94634, 0x88070000, 0x0857ea4f, 0x2008e04b, 0xfb07e7f2, 0x48a7fa04, 0x900249a5, 0xeb019813, 
+    0xb970058a, 0x46394628, 0xfdb2f024, 0x0000f8d9, 0x46424629, 0x3080f9b0, 0xeb009812, 0xf0230046, 
+    0xf8d9fd76, 0x4b9c0000, 0x78814a9c, 0x0094f8d0, 0x0100e9cd, 0x46289903, 0xfecef023, 0x46424997, 
+    0x0028f851, 0x60084994, 0xf8d94629, 0xf9b00000, 0x48923084, 0xfd6cf023, 0x0000f8d9, 0x99024642, 
+    0x3084f9b0, 0xf023488c, 0x4988fd63, 0x4628b23a, 0xeb016809, 0x9902034a, 0xfbcaf023, 0xeb061c64, 
+    0xb2060008, 0x455cb224, 0x4880dbb3, 0x6801ac05, 0xb100e9cd, 0x000fe894, 0xfef0f7ff, 0xe761b009, 
+    0x47f0e92d, 0x00d24c76, 0x4f77b086, 0x0541ea42, 0x46384305, 0xf4456824, 0xf8dd7180, 0x8824a038, 
+    0x435c0064, 0xf884fa0f, 0xfd53f023, 0xf2402400, 0x027e1900, 0x1c64e002, 0xd20642b4, 0x46492208, 
+    0xf0234638, 0x2800fd5d, 0xf445d1f5, 0x46387100, 0xfd3ff023, 0x4a642000, 0x90052101, 0x46531d12, 
+    0xe9cd9004, 0x46410102, 0x90019000, 0xf0002001, 0xb006facf, 0x87f0e8bd, 0x4ff8e92d, 0x4b584698, 
+    0xe9dd4e5a, 0x681ba90a, 0x6833881d, 0x46439300, 0xf7ff086f, 0x2400ffb5, 0xb22e46b3, 0xfb17e010, 
+    0xf8dbf004, 0xeb091000, 0xeb0a0340, 0xfb050240, 0xeb01f004, 0x46310040, 0xfb9cf023, 0xb2241c64, 
+    0xdbec4544, 0x8ff8e8bd, 0x4fffe92d, 0x4615b085, 0x28012200, 0xd0159203, 0x2202b1b5, 0xa100f8df, 
+    0x9b029202, 0x2000f8da, 0x4a408816, 0x68120874, 0x462a9200, 0xff84f7ff, 0x0800f04f, 0xb0f0f8df, 
+    0xe05c4645, 0xe7e92201, 0xe7e72208, 0xfb064937, 0xf8dff005, 0x680990e0, 0x0780eb0b, 0xeb01464b, 
+    0x463a0040, 0xf023b231, 0xf8dafb65, 0x46220000, 0xf9b04932, 0x46383088, 0xfc99f023, 0x0000f8da, 
+    0x492d4622, 0x3088f9b0, 0xf0234648, 0x4a2afc90, 0x468c492a, 0xf8416810, 0x20000024, 0xf8426010, 
+    0x20010024, 0x1a31e00b, 0x3020f85c, 0x3021f84c, 0x3020f852, 0x1c40425b, 0xf842b200, 0x42a03021, 
+    0xf8dadbf1, 0x46d10000, 0x463a9b03, 0xf8d07881, 0xe9cd0094, 0x49180100, 0xf0244818, 0x9812f8b7, 
+    0xfb14b188, 0x4638f105, 0xeb0b4622, 0xf0230181, 0x1c6dfc0f, 0x0004eb08, 0xf880fa0f, 0x9802b22d, 
+    0xdba34285, 0xf8d9e71a, 0x46220000, 0x308cf9b0, 0xeb009808, 0x46380148, 0xfc5af023, 0x0000e7e9, 
+    0x000405f8, 0x0004066c, 0xf1000100, 0x00040224, 0x00049978, 0x0004b978, 0x0004d178, 0x0004c178, 
+    0x2801b570, 0xdc01460d, 0xe0004956, 0x24004956, 0x1640eb01, 0x42408828, 0xeb06b281, 0xf0230044, 
+    0x1c64fc5e, 0x1cadb224, 0xdbf32c10, 0xb570bd70, 0x460e2801, 0x494bdc01, 0x494be000, 0xeb012400, 
+    0xeb051540, 0xf0230044, 0xb200fc47, 0xf0242109, 0x4240fba3, 0x0014f826, 0xb2241c64, 0xdbf02c10, 
+    0xb570bd70, 0x21204d41, 0xf0246828, 0x2400fc41, 0xb2606829, 0xffc4f7ff, 0xb2241c64, 0xdbf72c04, 
+    0xe92dbd70, 0x460741fc, 0x4e384839, 0x71fff64f, 0x88006800, 0x01c0ea01, 0xf0246830, 0x2500fc29, 
+    0x2f012400, 0xb1acd014, 0x68312002, 0x46222300, 0x0100e9cd, 0x46384629, 0xfd90f7ff, 0xb2641c64, 
+    0xdbee2c04, 0xb26d1c6d, 0xdbe92d04, 0x81fce8bd, 0xe7ea2001, 0xe7e82008, 0xb5102000, 0xffd1f7ff, 
+    0xf7ff2001, 0xe8bdffce, 0xe7ba4010, 0x4a20b57c, 0x68124d1e, 0x8814682b, 0x46162200, 0xf823e007, 
+    0x1c526012, 0xf823b212, 0x1c520012, 0x42a2b212, 0x2601dbf5, 0x29038018, 0x2400d00e, 0x23006828, 
+    0xb261461a, 0x6000e9cd, 0xf7ff2001, 0x1c64fd57, 0x2c04b224, 0xbd7cdbf2, 0x20014c0e, 0x6300e9cd, 
+    0x461a2300, 0x1000f994, 0xfd48f7ff, 0x23006828, 0xe9cd461a, 0xf9946000, 0x20011001, 0xfd3ef7ff, 
+    0x0000bd7c, 0xf20304a2, 0xf20305a4, 0x00040224, 0x000405f8, 0x00040578, 0x4fffe92d, 0x4682b089, 
+    0x460f4897, 0xf64f4d98, 0x900671ff, 0x6080f500, 0xf5059005, 0x48936980, 0x90034690, 0x6080f500, 
+    0x48929002, 0x20009008, 0x48919004, 0xf8b06800, 0x9808b000, 0x045bea4f, 0x018bea01, 0xfb98f024, 
+    0x4659488c, 0xfb84f024, 0xf44f4e8a, 0x60303080, 0xeb062000, 0xf9370280, 0x1c401010, 0x60510289, 
+    0xdbf62810, 0x68384f82, 0xf8d07881, 0xe9cd0094, 0x48800100, 0xe9dd9a06, 0xf0231304, 0x487dfc9d, 
+    0xf0244659, 0xf44ffb65, 0x60303080, 0xeb062000, 0xf9380280, 0x1c401010, 0x60510289, 0xdbf62810, 
+    0x9b024873, 0x78816800, 0x0094f8d0, 0x0100e9cd, 0xe9dd4870, 0xf0232103, 0x2600fc7f, 0x90001c60, 
+    0x9803e02c, 0xf8509902, 0x98062026, 0x1026f851, 0x3026f850, 0xfb02469c, 0x9b05f003, 0x3026f853, 
+    0xf703fb02, 0xfb014352, 0xfb010003, 0xfb01781c, 0x120f2101, 0x4639d009, 0xfa88f024, 0x0026f845, 
+    0x46404639, 0xfa82f024, 0xf240e004, 0xf8451000, 0x20000026, 0x0026f849, 0x1c769800, 0xdbd04286, 
+    0xe096980c, 0xe08b9816, 0xd01d2801, 0xeb014952, 0x4952264a, 0xf04f2001, 0xeb010800, 0x9000224a, 
+    0xf004fb08, 0x6828b201, 0x3011f936, 0x4b4c4358, 0x0021f843, 0x0024f855, 0x7011f932, 0x4f494378, 
+    0x0021f847, 0xe0242001, 0xeb014947, 0x4947264a, 0x1843e7e0, 0x7020f855, 0xc013f936, 0xe013f932, 
+    0xf70cfb07, 0xc020f859, 0x7c1efb0c, 0xf8474f3c, 0xf855c023, 0xf9327020, 0xf936c013, 0xfb07e013, 
+    0xf859f70c, 0x1c40c020, 0x7c0efb0c, 0xf8474f35, 0x42a0c023, 0xf108dbdd, 0xfa4f0001, 0x9800f880, 
+    0xdbbd4580, 0x27004b2f, 0x68184a2d, 0x0024f842, 0x1c60601f, 0x7024f843, 0xebabe00b, 0xf8520100, 
+    0xf8426021, 0xf8536020, 0x42491021, 0x1020f843, 0x45581c40, 0x4e1edbf1, 0x9b044a1e, 0x78816830, 
+    0x0094f8d0, 0x0100e9cd, 0x481d491e, 0xfebef023, 0x46226830, 0xf9b09908, 0x4816308c, 0xfa78f023, 
+    0x46219808, 0x0044eb00, 0xfaa2f024, 0x23009908, 0x1700e9cd, 0x461a9802, 0xf7ff4651, 0x9803fcb2, 
+    0xb2401e40, 0x28009003, 0xf6bf9802, 0x1c40af6d, 0x9002b240, 0xf77f2801, 0xb00daf65, 0x8ff0e8bd, 
+    0x00042978, 0x00041978, 0x00042178, 0x00043178, 0x000405f8, 0x00049978, 0x00044978, 0x00045178, 
+    0x0004c178, 0x0004d178, 0x00043978, 0x00044178, 0x5ff0e92d, 0x461f4d53, 0x46902301, 0xb030f8dd, 
+    0xf8dd460c, 0x2102a038, 0x9028f8dd, 0x4628461a, 0xfa6ff023, 0x20042100, 0xfeeef000, 0x2c404e4a, 
+    0x7100f643, 0x0660dd08, 0x2310d406, 0x22084630, 0xfa48f023, 0xe01f2310, 0xdd012c1f, 0xd5f406a0, 
+    0xdd082c0f, 0xd40606e0, 0x46302304, 0xf0232208, 0x2304fa39, 0x2c07e010, 0x0720dd08, 0x2302d406, 
+    0x22084630, 0xfa2ef023, 0xe0052302, 0x46302301, 0xf0232208, 0x2301fa27, 0x22004630, 0xf023213f, 
+    0x4e31fa21, 0x21042202, 0x1d36464b, 0xf0234630, 0x2201fa19, 0x2102465b, 0xf0234630, 0x2200fa13, 
+    0x21014653, 0xf0234630, 0x4e27fa0d, 0x9b0b2202, 0x36142104, 0xf0234630, 0x9b0dfa05, 0x21022201, 
+    0xf0234630, 0x9b0ff9ff, 0x21012200, 0xf0234630, 0x481df9f9, 0x46232200, 0x71fff64f, 0xf0231f00, 
+    0x4819f9f1, 0x30084641, 0xf9e3f023, 0x46391d30, 0xf9dff023, 0x22002301, 0xf04f4619, 0xf0234070, 
+    0x04b4f9e1, 0x3e084e10, 0x4620e00e, 0xfe72f000, 0xdc091e04, 0x46204c0d, 0xf9cef023, 0x5180f440, 
+    0xf0234620, 0xe004f9cc, 0xf0234630, 0x2801f9bf, 0x4628d1eb, 0x5ff0e8bd, 0x22012300, 0xf0232102, 
+    0x0000b9d8, 0xf203529a, 0xf000000c, 0xf203517c, 0x220048a5, 0x31fff240, 0xf023b510, 0xb200f9c1, 
+    0xb5f8bd10, 0x20004605, 0xf7ff9000, 0x4c9ffff1, 0x80204e9f, 0x0000f44f, 0xe0099000, 0x46322108, 
+    0xf0004668, 0x2801fece, 0xf7ffd005, 0x8020ffe1, 0x42a88820, 0xbdf8dcf2, 0x5fffe92d, 0x9254f8df, 
+    0xf8df4607, 0x2202b254, 0x450ee9dd, 0x824cf8df, 0xf8992600, 0xf8df0000, 0xf000a248, 0xf89b0101, 
+    0xea020000, 0xf8980040, 0x43012000, 0xea002004, 0x43010082, 0x0000f89a, 0xea022208, 0x430100c0, 
+    0x22104888, 0xea027800, 0x43011000, 0x22204886, 0xea027800, 0x43011040, 0x78004884, 0xea410780, 
+    0x48796110, 0xf0233808, 0x4881f954, 0x780001f9, 0x1100ea41, 0x38144874, 0xf94bf023, 0x9801497d, 
+    0x01c07809, 0x1101ea40, 0x3810486f, 0xf941f023, 0x98024979, 0x01c07809, 0x1101ea40, 0x380c486a, 
+    0xf937f023, 0x1f004868, 0x210fb39f, 0xf931f023, 0xf8984f65, 0x4b640000, 0x28013708, 0xf899d02c, 
+    0x28010000, 0xf89bd06e, 0x28010000, 0xf89ad06a, 0x28010000, 0x4621d066, 0x1d00485b, 0xf919f023, 
+    0x46382300, 0x21062201, 0xf91cf023, 0x46382301, 0x46192200, 0xf916f023, 0x28009810, 0x4852d107, 
+    0x21042202, 0xf0233010, 0x2800f91b, 0xe8bdd067, 0xe7ff9fff, 0xe7c92100, 0x0e214858, 0x2105ea41, 
+    0xe000f890, 0xea400a20, 0xf1be6005, 0xd1100f01, 0x6200f3c5, 0xf3c500d6, 0xea462200, 0xf0010682, 
+    0x18920201, 0x0602ea46, 0x0201f000, 0x0602ea46, 0xf004b2f6, 0xf40008ff, 0xea48407f, 0xea4f0800, 
+    0xea404014, 0xf4004005, 0xea48007f, 0xf0010800, 0x4943407f, 0x0800ea48, 0x2006ea4f, 0xea407809, 
+    0x49401081, 0xea407809, 0x493f1001, 0xea407809, 0x483e0181, 0xea417800, 0x46180100, 0xf8b9f023, 
+    0xe7994641, 0x88014829, 0xf0234618, 0x4826f8b2, 0x1d004621, 0xf8adf023, 0xe7922301, 0xf0002002, 
+    0x2801fd09, 0x4c22d00b, 0xf0234620, 0xb004f8a5, 0x7100f440, 0xe8bd4620, 0xf0235ff0, 0x2200b8a0, 
+    0x21014638, 0xf8acf023, 0xd1e72800, 0xb5fee78f, 0x23012500, 0x4629462a, 0x95004628, 0xf884f004, 
+    0x24004e11, 0x46233610, 0x46302203, 0xf0232108, 0x2301f889, 0x22024630, 0xf0232104, 0x2100f883, 
+    0x460a9502, 0xe9cd4608, 0xf7ff1100, 0x1c64fee5, 0x2c02b264, 0xb003dbe7, 0x23004630, 0xe8bd2202, 
+    0x210440f0, 0xb86ef023, 0xf0008014, 0x0004026e, 0xf203517a, 0x0004026b, 0x00040269, 0x00040264, 
+    0x00040267, 0x0004024b, 0x00040249, 0x00040246, 0x00040251, 0x0004024f, 0x0004024d, 0x000402fa, 
+    0x0004025c, 0x0004025d, 0x0004025e, 0x0004025f, 0x41f0e92d, 0x4d262301, 0x4607220a, 0x4628029c, 
+    0xf0234621, 0x00a6f856, 0x46304639, 0xfcd4f000, 0x46212300, 0x4628220a, 0xf84bf023, 0x46304639, 
+    0xfccaf000, 0x22012300, 0x1f282102, 0x41f0e8bd, 0xb83ff023, 0xd0002800, 0xea404608, 0xd1020341, 
+    0x0000f04f, 0x4608e000, 0x0080ea43, 0x00c1ea40, 0x1002ea40, 0x6170f440, 0xf023480e, 0x0253b810, 
+    0xea432801, 0xd0102302, 0x4313460a, 0x0241ea43, 0x4608b100, 0x0080ea42, 0x00c1ea40, 0xf040b280, 
+    0x48040110, 0xf022380c, 0x2200bffa, 0x0000e7ed, 0xf20350f6, 0xf20352ac, 0x41f0e92d, 0x28014afa, 
+    0xd0094607, 0x2f0249f9, 0x880e48f9, 0xf6478805, 0xd0092012, 0xd0212f03, 0x46102100, 0xffdff022, 
+    0x46352600, 0xe0234634, 0x880c49f2, 0x4285b916, 0x4605d200, 0x4006eb05, 0xdc0142a0, 0xb2841e40, 
+    0x4080f240, 0xd2014284, 0xe0044604, 0x6f00f5b4, 0xf240d301, 0xf24074ff, 0xe0061105, 0xb9162400, 
+    0xd2004285, 0xf2404605, 0x46101101, 0xffb7f022, 0x463148dd, 0xf0221d00, 0x48dbffb2, 0x1d804629, 
+    0xffadf022, 0x462148d8, 0xf0223008, 0x48d6ffa8, 0xb10f3822, 0xe0002301, 0x22012300, 0xf0222102, 
+    0x48d5ffb8, 0xe8bd7007, 0x48d481f0, 0xf990b510, 0x48d31000, 0xd0052903, 0xd0122904, 0xd0082905, 
+    0xe0152000, 0x21202205, 0xffb1f022, 0x48cdb180, 0x2204e005, 0xf0222110, 0xb148ffaa, 0x780048ca, 
+    0x2203e006, 0xf0222108, 0xb108ffa2, 0xe7f648c7, 0x4010e8bd, 0x48bce780, 0x2112f240, 0x41f0e92d, 
+    0xf022381c, 0x48b8ff6c, 0x0115f647, 0xf022381a, 0x48bfff66, 0x2173f240, 0xff61f022, 0x210248b2, 
+    0xf0223818, 0x48bbff5c, 0x28007800, 0x48bad07e, 0x20047801, 0x1e4040c8, 0x75fff64f, 0x3100ea05, 
+    0x381448a9, 0xff4bf022, 0x212048a7, 0xf0223810, 0x48b2ff46, 0xf0222100, 0x48b0ff42, 0x11fef240, 
+    0xf0221c80, 0x48adff3c, 0x2300220c, 0x38160291, 0xff4ff022, 0x4eaa48a1, 0x78004caa, 0xd07d2803, 
+    0x70602001, 0x7030203c, 0x02017830, 0xf5a11e40, 0x43017180, 0xb2894894, 0xf022380e, 0x4892ff20, 
+    0x3103f240, 0xf022380c, 0x7830ff1a, 0xb2811e40, 0x1f80488d, 0xff13f022, 0x1e407830, 0x488ab281, 
+    0xf0223808, 0x4892ff0c, 0x7180f64f, 0xf0223808, 0x488fff06, 0x6170f64f, 0xf0221f80, 0x4882ff00, 
+    0x38222110, 0xfefbf022, 0xf64a487f, 0x3820210a, 0xfef5f022, 0x78304e8c, 0x00c0f3c0, 0xfd5df002, 
+    0x21287860, 0x40c12214, 0x488840c2, 0x2102ea41, 0xfee5f022, 0x21687860, 0x40c12254, 0x488340c2, 
+    0x2102ea41, 0xf0221c80, 0xe000feda, 0x486ee0da, 0x0120f244, 0xf022381e, 0x487cfed2, 0x1811f241, 
+    0x300a4641, 0xfecbf022, 0x21004878, 0xf022300c, 0x7830fec6, 0x0040f3c0, 0xfd81f002, 0x210c486c, 
+    0xf02230a4, 0x4e6afebc, 0x7400f641, 0x46212303, 0x22081cb6, 0xf0224630, 0xe000fecc, 0x2304e0de, 
+    0x22004630, 0xf022211f, 0x4e61fec4, 0x22082305, 0x36a04621, 0xf0224630, 0x230afebc, 0x22004630, 
+    0xf022211f, 0x1cb6feb6, 0x46302301, 0x21702204, 0xfeaff022, 0x46302300, 0x461a2107, 0xfea9f022, 
+    0x2100485a, 0xf02238aa, 0x4858fe8a, 0x38a82100, 0xfe85f022, 0x21024855, 0xf02238bc, 0x4853fe80, 
+    0x387e2100, 0xfe7bf022, 0xfedff7ff, 0x211b483e, 0xf0223844, 0x4f4ffe74, 0x4680f240, 0x2210494c, 
+    0x46384633, 0xfe6ef022, 0x46332200, 0x46384629, 0xfe68f022, 0x1d384948, 0xfe5bf022, 0x23004d43, 
+    0xf24c220e, 0x35100100, 0xf0224628, 0x2302fe72, 0x7100f643, 0x46282208, 0xfe6bf022, 0x46282300, 
+    0x21c02206, 0xfe65f022, 0x46282303, 0x213f2200, 0xfe5ff022, 0x23024837, 0x383c2218, 0x61e0f04f, 
+    0xfe40f022, 0x23084d2a, 0x4621461a, 0x462835a6, 0xfe4ff022, 0x46282302, 0x21302204, 0xfe49f022, 
+    0x46282307, 0x210f2200, 0xfe43f022, 0x21094827, 0xf022300e, 0x4821fe24, 0x310cf244, 0xf0221e80, 
+    0x4822fe1e, 0x1d004641, 0xfe19f022, 0x230e4d21, 0x3d302218, 0x46280421, 0xfe14f022, 0x4628230e, 
+    0x02212210, 0xfe0ef022, 0x4621230c, 0x46282208, 0xfe08f022, 0xe8bd4628, 0x230c41f0, 0x211f2200, 
+    0xbe00f022, 0xe6a72003, 0xf2035114, 0x000402c4, 0x000402c6, 0x000402c8, 0x000402c3, 0x0004028a, 
+    0xf38f007c, 0x000402bf, 0x00040316, 0x00040315, 0xf203050a, 0x000405d9, 0x0004036b, 0xf2030818, 
+    0x000402c2, 0x00040688, 0x000402c1, 0xf20352a6, 0xffff0000, 0xf1000040, 0x00080005, 0x7030207c, 
+    0x70602000, 0xe92de6a0, 0x48ec5ffc, 0x4ce92600, 0xf8df4637, 0x4bec83a4, 0x48e97802, 0x93acf8df, 
+    0x0180f3c2, 0x88006800, 0x48e60845, 0xb3287800, 0xc002f893, 0xc000f889, 0xc394f8df, 0xf3424be5, 
+    0x1c521200, 0x469b46e2, 0xfd84f7ff, 0x937cf8df, 0x90002000, 0x46434602, 0x0000f899, 0x2001b241, 
+    0xf892f7ff, 0xf00248dc, 0x49dbfae4, 0x0000f899, 0x1010f831, 0xf8a92001, 0xe0151006, 0xc000f893, 
+    0xc000f889, 0xc354f8df, 0xe7d84bd5, 0x1010f938, 0xda001e0a, 0x42b14251, 0x0011dd04, 0x4251d500, 
+    0xb20e4607, 0xb2001c40, 0xd9012d80, 0xe0002180, 0x42814629, 0x1fbfdcea, 0x2800b238, 0x2000da00, 
+    0x1a289000, 0x1700f240, 0xf5a79001, 0xb2067080, 0x46052000, 0x0026f844, 0x9800e016, 0x44284659, 
+    0xf980fa0f, 0xf3c01b78, 0x46500245, 0xfec5f021, 0xf85443c0, 0x07c02026, 0x0019f938, 0x4410d021, 
+    0xb22d1c6d, 0x0026f844, 0x42a89801, 0x1c7fdce5, 0xf5b7b23f, 0xdbd87fc0, 0xf06f2600, 0x46350804, 
+    0x077ff06f, 0x0025f854, 0xfa66f025, 0xf8d2f025, 0xf0254642, 0xf024fc00, 0x287ffd13, 0x217fdb03, 
+    0x1a10e002, 0x4601e7dc, 0xdc0042b9, 0xb2494639, 0x1025f844, 0xfb011c6d, 0xb22d6600, 0xdbe12d80, 
+    0x2500489a, 0x4e9f60c6, 0x00c5eb04, 0xf8346841, 0xf3610035, 0xb281201f, 0x0045eb06, 0xfd0ff022, 
+    0xb22d1c6d, 0xdbef2d40, 0x9ffce8bd, 0x47f0e92d, 0xf2404895, 0xf8df1890, 0x4e8c9254, 0x28007800, 
+    0x488dd164, 0xf00268f4, 0x488bfa44, 0xf8307831, 0x81300011, 0xf0254620, 0x498dfa37, 0xf0254607, 
+    0xf025fa47, 0x4c8bf887, 0x46232200, 0xfd8cf024, 0x050bf06f, 0xf025462a, 0xf024fbae, 0x1040fcc1, 
+    0x21018070, 0xf0254638, 0xf025fbd4, 0x2200f873, 0xf0244623, 0x462afd79, 0xfb9df025, 0xfcb0f024, 
+    0x80b01040, 0xfc88f002, 0xd2064540, 0x0000f8d9, 0xd8022811, 0xf0024640, 0x4f77fc7a, 0x462c2500, 
+    0x4620703d, 0xf86ef003, 0x428c7831, 0x4605d100, 0x42887839, 0xb2c1dd00, 0x1c647039, 0x2c04b2e4, 
+    0x495fd3ef, 0x22001c6d, 0x8e496809, 0x0065eba1, 0x1ec0b200, 0xeb0017c1, 0xf0216191, 0x1a40013f, 
+    0x4860b283, 0x380a213f, 0xfcb3f022, 0x424088b0, 0x485cb281, 0xf022380e, 0x8870fc92, 0xb2814240, 
+    0x380c4858, 0xfc8bf022, 0x42408870, 0x4855b281, 0xf0223090, 0x4859fc84, 0xb3587800, 0x0002f9b6, 
+    0x0040eb00, 0x004ff3c0, 0xfc31f002, 0x381c484d, 0xfc72f022, 0xd2064540, 0x0000f8d9, 0xd8022811, 
+    0xf0024640, 0x484efc24, 0x220a2300, 0x4100f240, 0xfc7ff022, 0x20082101, 0xfc3cf002, 0xf0022000, 
+    0xf002fc81, 0x4847fc66, 0x28027800, 0x2803d005, 0xe009d003, 0x70fff647, 0x4841e7d6, 0x22012300, 
+    0x301e2102, 0xfc65f022, 0xe8bd7830, 0xf24f87f0, 0xea401060, 0xb2810041, 0xb5104832, 0xf0223810, 
+    0x4830fc3e, 0x4100f240, 0xf0221e80, 0x2207fc38, 0xe8bd2101, 0x20004010, 0xbbcff002, 0x47704770, 
+    0xb570482d, 0xf6414e1e, 0x780075ff, 0x08411c40, 0x79c26830, 0x441a7943, 0x79007983, 0x44104418, 
+    0x5000f5c0, 0x48261a44, 0x46292200, 0xf02238ac, 0x6832fc3e, 0x8bd37c51, 0x44084419, 0xf5001b00, 
+    0xb2015000, 0xfb9178d0, 0xfb00f3f0, 0xb1791113, 0x7e111a40, 0x1a20b200, 0x46291a40, 0x5000f5c0, 
+    0x4817b283, 0x4070e8bd, 0x38162200, 0xbc11f022, 0xe7ee2000, 0x00043978, 0x00044178, 0x000402c1, 
+    0x000405f8, 0x0004055c, 0x00040570, 0x00040688, 0x8365f253, 0x7425eef5, 0x00040598, 0xaf77a42e, 
+    0xca4fa6c1, 0xf2030510, 0x00040f44, 0x00040238, 0x40e00000, 0x40220000, 0x000402cb, 0x00040f46, 
+    0xf20350f6, 0x000402bf, 0x460db570, 0xeb014929, 0x21001000, 0xf0224604, 0x2001fbbc, 0x0185eb00, 
+    0xe8bd4620, 0xf0224070, 0x4922bbb4, 0x1000eb01, 0xf0222102, 0x491fbbae, 0xeb01b510, 0xf0221000, 
+    0xf3c0fba5, 0xbd100040, 0x310c491a, 0x1000eb01, 0xbb9cf022, 0x4604b510, 0xd0091c40, 0xf7ff4620, 
+    0xb118fff3, 0xf7ff4620, 0xb108ffe6, 0xbd102000, 0xbd102001, 0x41f0e92d, 0x480e4605, 0x460f4616, 
+    0x1405eb00, 0x46202102, 0xfb83f022, 0x46394809, 0xeb003008, 0xf0221005, 0x2100fb7c, 0xf0224620, 
+    0x2001fb78, 0x0186eb00, 0xe8bd4620, 0xf02241f0, 0x0000bb70, 0xf0008100, 0xd0052801, 0xd0032802, 
+    0xd0032804, 0xd0032805, 0x47702000, 0x47702002, 0x47702001, 0x47701e40, 0xe0004088, 0x28001e40, 
+    0x4770d1fc, 0x41f0e92d, 0x460c4e51, 0x8140f8df, 0x1d374605, 0x080cf108, 0x2201e00d, 0x21024630, 
+    0xfb5ef022, 0xd00e2801, 0x46382200, 0xf0222101, 0x2801fb57, 0x4640d007, 0xfb38f022, 0x42a01a28, 
+    0xe8bdd3eb, 0x4c4381f0, 0xf0224620, 0xf440fb35, 0x46206180, 0x41f0e8bd, 0xbb31f022, 0x47f0e92d, 
+    0x460f4614, 0x46994605, 0xf0224618, 0xf242fb25, 0xb1387610, 0xd02f2c01, 0x44282000, 0x4648b281, 
+    0xfb1df022, 0x23014d34, 0x21802207, 0xf0224628, 0xf04ffb19, 0x46286880, 0x46412301, 0xf022221a, 
+    0x4648fb11, 0xfb08f022, 0xd1fa2800, 0x46282301, 0x21802207, 0xfb06f022, 0x46412301, 0x4628221a, 
+    0xfb00f022, 0xd0002c01, 0x19f02600, 0x4648b281, 0x47f0e8bd, 0xbaf3f022, 0xe7ce4630, 0x41f0e92d, 
+    0x4615461c, 0x4607460e, 0xf7ff2000, 0x1b04ff3d, 0x2000e010, 0xff38f7ff, 0x28001b00, 0x4c15dc0a, 
+    0xf0224620, 0xf440fad9, 0x46207100, 0x41f0e8bd, 0xbad5f022, 0xf0224638, 0x4030facf, 0xd1e842a8, 
+    0xb570e78f, 0x68004603, 0x4615460c, 0x28001e40, 0xdc0b6018, 0xf0224610, 0x2101fabf, 0x430840a1, 
+    0x4628b281, 0xfabbf022, 0xbd702001, 0xbd702000, 0xf0008120, 0xf203517e, 0xf0001000, 0xe28fc04d, 
+    0xe12fff1c, 0x2101e7fe, 0xd2042820, 0x23014081, 0x4853b242, 0x3820e004, 0x4081b242, 0x23014851, 
+    0xbaa0f022, 0xeb024a50, 0xf0221000, 0x2101ba92, 0xd2052820, 0xb2424081, 0x23004849, 0xe0053808, 
+    0xb2423820, 0x48474081, 0x38082300, 0xba8af022, 0x28202101, 0x4081d205, 0x4841b242, 0x38082301, 
+    0x3820e005, 0x4081b242, 0x2301483e, 0xf0223808, 0x2101ba79, 0xd2042820, 0xb2424081, 0x301c4838, 
+    0x3820e004, 0x4081b242, 0x300c4836, 0xba78f022, 0x41f0e92d, 0x4934460d, 0x4613461f, 0x9e063908, 
+    0x1400eb01, 0x46202204, 0xf0222130, 0x2203fa5b, 0x21084620, 0xf022462b, 0x2202fa55, 0x21044620, 
+    0xf022463b, 0x4620fa4f, 0xe8bd4633, 0x220041f0, 0xf0222103, 0xb570ba47, 0xe8bdb118, 0xf0224070, 
+    0x4c21ba35, 0x1f244d21, 0xf0224620, 0x3410fa2f, 0xd9f942ac, 0xe92dbd70, 0x240141f0, 0xd20e2820, 
+    0xb2424e17, 0x36284084, 0x23014615, 0x46304621, 0xfa28f022, 0x46212301, 0x462a1d37, 0x3820e00e, 
+    0xb2424e10, 0x36184084, 0x23014615, 0x46304621, 0xfa18f022, 0x46212301, 0x462a1d37, 0xf0224638, 
+    0x2300fa11, 0x462a4621, 0xf0224630, 0x4621fa0b, 0x4638462a, 0x41f0e8bd, 0xf0222300, 0x0000ba03, 
+    0xf0001008, 0xf0001508, 0xf0001108, 0xf00013f4, 0xf04fb510, 0x48ff34ff, 0xf0224621, 0x48fef9ea, 
+    0xf0224621, 0x48fbf9e6, 0x30084621, 0xf9e1f022, 0x462148f9, 0xf0223008, 0x49f8f9dc, 0xf02248f8, 
+    0x48f7f9d8, 0x301049f7, 0xf9d3f022, 0x49f648f4, 0xf0223020, 0x48f2f9ce, 0x303049f4, 0xf9c9f022, 
+    0x49f348ef, 0xf0223040, 0x48edf9c4, 0x305049f1, 0xf9bff022, 0x49f048ea, 0xf0223060, 0x48e8f9ba, 
+    0x307049ee, 0xf9b5f022, 0x49ed48e5, 0xf0223080, 0x48e3f9b0, 0x309049eb, 0xf9abf022, 0x49ea48e0, 
+    0xf02230a0, 0x48def9a6, 0x30b049e8, 0xf9a1f022, 0x49e748db, 0xf02230c0, 0x48d9f99c, 0x30d049e5, 
+    0xf997f022, 0x49e448d6, 0xf02230e0, 0x48d4f992, 0x30f049e2, 0xf98df022, 0x48e249e1, 0xf989f022, 
+    0x49e148e0, 0xf0223010, 0x48def984, 0x302049df, 0xf97ff022, 0x49de48db, 0xf0223030, 0x48d9f97a, 
+    0x304049dc, 0xf975f022, 0x49db48d6, 0xf0223050, 0x48d4f970, 0x306049d9, 0xf96bf022, 0x49d848d1, 
+    0xf0223070, 0x48cff966, 0x308049d4, 0xf961f022, 0x49d248cc, 0xf0223090, 0x48caf95c, 0x30a049d1, 
+    0xf957f022, 0x49d048c7, 0xf02230b0, 0x48c5f952, 0x30c049ce, 0xf94df022, 0x49c848c2, 0xf02230d0, 
+    0x48c0f948, 0x30e049ca, 0xf943f022, 0x49c948bd, 0xf02230f0, 0x49c8f93e, 0xf02248c8, 0x48c7f93a, 
+    0x301049c7, 0xf935f022, 0x49c648c4, 0xf0223020, 0x48c2f930, 0x303049c4, 0xf92bf022, 0x49c348bf, 
+    0xf0223040, 0x48bdf926, 0x305049c1, 0xf921f022, 0x49c048ba, 0xf0223060, 0x48b8f91c, 0x307049be, 
+    0xf917f022, 0x49ad48b5, 0xf0223080, 0x48b3f912, 0x309049ba, 0xf90df022, 0x49b948b0, 0xf02230a0, 
+    0x48aef908, 0x30b049b7, 0xf903f022, 0x49b648ab, 0xf02230c0, 0x48a9f8fe, 0x30d049b4, 0xf8f9f022, 
+    0x499e48a6, 0xf02230e0, 0x48a4f8f4, 0x4010e8bd, 0x30f0499a, 0xb8edf022, 0xf7ffb57c, 0x2000fef9, 
+    0xfea9f7ff, 0x2400b662, 0x22019400, 0x20064623, 0xf7ff4621, 0x2006fe7d, 0xfe49f7ff, 0x94002300, 
+    0x46192201, 0xf7ff2007, 0x2007fe73, 0xfe3ff7ff, 0x94002300, 0x46192203, 0xf7ff2001, 0x2300fe69, 
+    0x22039400, 0x20114619, 0xfe62f7ff, 0x94002300, 0x46192203, 0xf7ff2012, 0x2001fe5b, 0xfe27f7ff, 
+    0xf7ff2011, 0x2012fe24, 0xfe21f7ff, 0x94002300, 0x46192202, 0xf7ff4610, 0x2002fe4b, 0xfe28f7ff, 
+    0x94002300, 0x46192203, 0xf7ff201e, 0x201efe41, 0xfe0df7ff, 0x94002300, 0x46192203, 0xf7ff201f, 
+    0x201ffe37, 0xfe03f7ff, 0x94002201, 0x46112300, 0xf7ff201c, 0x4e7efe2d, 0x21022301, 0x4630461a, 
+    0xf8a7f022, 0xf64f487a, 0x462975ff, 0xf022382a, 0x4877f886, 0x382c4629, 0xf881f022, 0x46302300, 
+    0x21042202, 0xf895f022, 0x46294871, 0xf022380a, 0x486ff876, 0x380c4629, 0xf871f022, 0xfcacf005, 
+    0xf0051e60, 0x2301fb29, 0x22004630, 0xf0224619, 0x2201f880, 0x23009400, 0x20044611, 0xfdf8f7ff, 
+    0xf7ff2004, 0x2300fdc4, 0x22039400, 0x20224619, 0xfdeef7ff, 0xf7ff2022, 0x2300fdba, 0x22039400, 
+    0x20214619, 0xfde4f7ff, 0xf7ff2021, 0x2300fdb0, 0x22019400, 0x20254619, 0xfddaf7ff, 0xf7ff2025, 
+    0x2300fda6, 0x22019400, 0x20264619, 0xfdd0f7ff, 0xf7ff2026, 0x484ffd9c, 0x717ff647, 0xf82ff022, 
+    0x94002300, 0x46192201, 0xf7ff2024, 0x2024fdc1, 0xfd8df7ff, 0x94002300, 0x46192201, 0xf7ff2009, 
+    0x4844fdb7, 0x38164629, 0xf819f022, 0x46294841, 0xf0223814, 0x483ff814, 0x0500f248, 0x381a4629, 
+    0xf80df022, 0x4629483b, 0xf0223818, 0x2009f808, 0xfd6df7ff, 0xf64f2300, 0x220170e0, 0x21079000, 
+    0x46189001, 0xfaf2f01c, 0x94002201, 0x46102300, 0xe0612107, 0xf0001000, 0xf0001500, 0x00004580, 
+    0xf0001108, 0x00004900, 0x00004944, 0x00004ad4, 0x00004c48, 0x00004e84, 0x00004ebc, 0x00005020, 
+    0x0000506c, 0x000050a4, 0x0000523c, 0x000052f4, 0x00005468, 0x000054d4, 0x0000550c, 0x00005544, 
+    0x0000557c, 0xf0001208, 0x000055b4, 0x000055f8, 0x0000563c, 0x00005654, 0x0000566c, 0x00007a65, 
+    0x000056a4, 0x000056dc, 0x000058a4, 0x000058dc, 0x00005940, 0x00005958, 0x0000599c, 0xf0001308, 
+    0x000059d4, 0x00005aa0, 0x00005b8c, 0x00005bc4, 0x00005dcc, 0x00005ebc, 0x00006010, 0x00006048, 
+    0x00006080, 0x000060b8, 0x000061e0, 0x00006218, 0xf2039046, 0xf23c8094, 0xf01c9401, 0xf64ffa87, 
+    0x900070f8, 0x90012300, 0x21072201, 0xf01c2002, 0xf249fa7d, 0x9000002a, 0x90012300, 0x21072201, 
+    0xf01c2003, 0xf244fa73, 0x90001091, 0x90012300, 0x211e2201, 0xf01c2004, 0x2189fa69, 0x2301208c, 
+    0x0100e9cd, 0x46192200, 0xf01c2005, 0x2201fa5f, 0x23009400, 0x201a4611, 0xfcfaf7ff, 0xf7ff201a, 
+    0xf004fcc6, 0x2201fd2f, 0x23009400, 0x202b4611, 0xfceef7ff, 0xf7ff202b, 0xe8bdfcba, 0x4802407c, 
+    0x31bbf64b, 0xbf4bf021, 0xf23c80ba, 0x46032200, 0x2107481e, 0xbf46f021, 0x4c1cb510, 0x22042300, 
+    0x21103cc0, 0xf0214620, 0x2301ff3d, 0x22064620, 0xf0212140, 0x2300ff37, 0x22064620, 0xf0212140, 
+    0x2301ff31, 0x22044620, 0x4010e8bd, 0xf0212110, 0xb510bf29, 0x23004c0d, 0x3cc02205, 0x46202120, 
+    0xff20f021, 0x46202301, 0x21802207, 0xff1af021, 0x46202300, 0x21802207, 0xff14f021, 0x46202301, 
+    0xe8bd2205, 0x21204010, 0xbf0cf021, 0xf10008c0, 0xf04fb570, 0x46054671, 0xf6402200, 0x21010400, 
+    0x46304603, 0xfefef021, 0xd0172d01, 0x05264635, 0x221f4628, 0xf0214631, 0x2801ff03, 0x1e64d00e, 
+    0x2c00b224, 0x4c44dcf4, 0xf0214620, 0xf440fee5, 0x46204100, 0x4070e8bd, 0xbee1f021, 0x2200bd70, 
+    0xf04f2101, 0xb5104071, 0xfeeaf021, 0xbd10b240, 0x4c3ab570, 0x22104615, 0xf44f460e, 0x4603017f, 
+    0xf0214620, 0x2200fecf, 0x21ff4633, 0xf0214620, 0x462bfec9, 0xe8bd4620, 0x22084070, 0x7100f64f, 
+    0xbec0f021, 0x4c2db570, 0x460d2210, 0x341c492c, 0x46204603, 0xfeb6f021, 0x4620462b, 0x4070e8bd, 
+    0xf64f2200, 0xf02171ff, 0xb570bead, 0x22044c23, 0x4603460d, 0x21f03418, 0xf0214620, 0x462bfea3, 
+    0xe8bd4620, 0x22004070, 0xf021210f, 0xe92dbe9b, 0x4c1a41f0, 0x4615461f, 0x1d24460e, 0x220c4603, 
+    0x0100f241, 0xf0214620, 0x2208fe8d, 0x46204633, 0xf0210151, 0x2204fe87, 0x21f0462b, 0xf0214620, 
+    0x463bfe81, 0xe8bd4620, 0x220041f0, 0xf0212103, 0xb570be79, 0x461d4c09, 0x461321f0, 0x22043414, 
+    0xf0214620, 0x462bfe6f, 0xe8bd4620, 0x22004070, 0xf021210f, 0x0000be67, 0xf203517c, 0xf1000004, 
+    0xffff0000, 0x41f0e92d, 0x460e1e52, 0xb2541e5b, 0x4603b25d, 0xf04f2218, 0x4ffd51f8, 0xf0214638, 
+    0x2210fe51, 0xf44f4633, 0x463811f8, 0xfe4af021, 0x46232208, 0x7100f641, 0xf0214638, 0x462bfe43, 
+    0xe8bd4638, 0x220041f0, 0xf021211f, 0xe92dbe3b, 0xf44f4ff8, 0x46802780, 0x461d2000, 0xa028f8dd, 
+    0x460e4614, 0x0110f243, 0x46389000, 0xfa63f7f8, 0xf1041c70, 0xd0010001, 0xe011b188, 0x261ab108, 
+    0x2100e00e, 0xf7f84638, 0x2100fa45, 0xf7f84638, 0x2100fa41, 0xf7f84638, 0xe8bdfa3d, 0x241a8ff8, 
+    0x4971f04f, 0x46482300, 0x21102204, 0xfe0af021, 0x461a2300, 0xb270b261, 0xffa4f7ff, 0x461a2300, 
+    0x46184619, 0xff85f7ff, 0x20012100, 0xff4df7ff, 0x464148cf, 0xf0213018, 0x48cdfdec, 0x22002301, 
+    0x30244619, 0xfdeef021, 0x1f0048c9, 0xfddef021, 0x46384601, 0xfa0ef7f8, 0xf02148c5, 0x4601fdd7, 
+    0xf7f84638, 0x4641fa07, 0xf7f84638, 0x4ec1fa03, 0x2000f240, 0xf7ff7831, 0xf8dffa6f, 0x4cbf82fc, 
+    0x0000f898, 0xf994b948, 0xb1152000, 0x4629980b, 0x2100e001, 0xf0014608, 0x2301fbf1, 0x2211464f, 
+    0x04594648, 0xfdbef021, 0x46382301, 0x46192200, 0xfdb8f021, 0xb2c8f8df, 0x0000f44f, 0x4900f04f, 
+    0xe0069000, 0x465a2101, 0xf7ff4668, 0x2801fada, 0x221fd006, 0x46384649, 0xfdb2f021, 0xd0f12800, 
+    0x0000f898, 0xf1bab970, 0xd0040f00, 0x2000f994, 0x980b4629, 0xb12de004, 0xf9942100, 0x46082000, 
+    0xfbbcf001, 0x46382301, 0x03d9220f, 0xfd8af021, 0xf2407831, 0xf7ff2000, 0xe76efa1f, 0x43f8e92d, 
+    0x2680f44f, 0x20004680, 0x460d4614, 0x0120f243, 0x46309000, 0xf9aff7f8, 0xf1041c68, 0xd0010001, 
+    0xe011b188, 0x251ab108, 0x2100e00e, 0xf7f84630, 0x2100f991, 0xf7f84630, 0x2100f98d, 0xf7f84630, 
+    0xe8bdf989, 0x241a83f8, 0x4771f04f, 0x46382300, 0x21102204, 0xfd56f021, 0x46082100, 0xb26ab263, 
+    0xfef0f7ff, 0x461a2300, 0x46184619, 0xfed1f7ff, 0x20002101, 0xfe99f7ff, 0x46414875, 0xf0213018, 
+    0x4873fd38, 0x22002301, 0x30244619, 0xfd3af021, 0x1f00486f, 0xfd2af021, 0x46304601, 0xf95af7f8, 
+    0xf021486b, 0x4601fd23, 0xf7f84630, 0x4641f953, 0xf7f84630, 0x4c67f94f, 0x2800f240, 0x78214640, 
+    0xf9baf7ff, 0x46382301, 0x04592211, 0xfd1af021, 0x46382301, 0x46192200, 0xfd14f021, 0xf44f4d60, 
+    0x90000000, 0x02061ead, 0x210fe006, 0x4668462a, 0xfa37f7ff, 0xd0062801, 0x4631221f, 0xf0214638, 
+    0x2800fd0f, 0x2301d0f1, 0x220f4638, 0xf02103d9, 0x7821fcf9, 0xf7ff4640, 0xe792f98f, 0x4fffe92d, 
+    0x469bb081, 0x46162000, 0x2980f44f, 0xe9dd460f, 0xf8dd540e, 0xf2438044, 0x90000130, 0xf7f84648, 
+    0x1c78f91a, 0x1c70d101, 0x1c68d002, 0xe004d004, 0xd1021c68, 0xd0031c60, 0x1c60251a, 0xe010d010, 
+    0x464c2100, 0xf7f84648, 0x2100f8f5, 0xf7f84620, 0x2100f8f1, 0xf7f84620, 0xb005f8ed, 0x8ff0e8bd, 
+    0xf04f241a, 0x23014a71, 0x22044650, 0xf0212110, 0xb263fcb9, 0xb271b26a, 0xf7ffb278, 0x2300fe53, 
+    0x4619461a, 0xf7ff4618, 0x9810fe34, 0xfa4fb241, 0xf7fff08b, 0x4826fdfa, 0x30189901, 0xfc99f021, 
+    0x23014823, 0x46192200, 0xf0213024, 0x4820fc9b, 0xf0211f00, 0x4601fc8b, 0x4648464c, 0xf8baf7f8, 
+    0xf021481b, 0x4601fc83, 0xf7f84620, 0x9901f8b3, 0xf7f84620, 0x4d17f8af, 0x2b00f240, 0x78294658, 
+    0xf91af7ff, 0x4c154e14, 0xb9587830, 0x2000f994, 0x0008ea5f, 0x4601d002, 0xe0019813, 0x46082100, 
+    0xfa9cf001, 0x46572301, 0x46502211, 0xf0210459, 0x2301fc69, 0x22004638, 0xf0214619, 0xf8dffc63, 
+    0xf44fa020, 0xf04f0000, 0x90004900, 0x0000e011, 0xf100000c, 0x0004028b, 0x0004055c, 0x00040290, 
+    0xf203517c, 0x46522100, 0xf7ff4668, 0x2801f97a, 0x221fd006, 0x46384649, 0xfc52f021, 0xd0f12800, 
+    0xb9787830, 0xb1209812, 0x2000f994, 0x98134641, 0xf1b8e006, 0xd0050f00, 0xf9942100, 0x46082000, 
+    0xfa5cf001, 0x46382301, 0x03d9220f, 0xfc2af021, 0x46587829, 0xf8c0f7ff, 0xe92de75f, 0xf44f47f0, 
+    0x461e2480, 0x46894617, 0xf2434680, 0x46200160, 0xf851f7f8, 0x4571f04f, 0x46282301, 0x21102204, 
+    0xfc10f021, 0xfa4fb27b, 0x461af188, 0xf7ff4608, 0x2300fda9, 0x4619461a, 0xf7ff4618, 0xb271fd8a, 
+    0xf089fa4f, 0xfd51f7ff, 0x48c02300, 0x461a2101, 0xfbf8f021, 0x382848bd, 0xfbe8f021, 0x46204601, 
+    0xf818f7f8, 0x382448b9, 0xfbe0f021, 0x46204601, 0xf810f7f8, 0x46202100, 0xf80cf7f8, 0x46282300, 
+    0x10612211, 0xfbdef021, 0xe8bd4628, 0x230147f0, 0x46192200, 0xbbd6f021, 0xb51048ad, 0x7800b086, 
+    0x2000b188, 0x21019004, 0x22099005, 0xe9cd460b, 0x200b1002, 0x90004611, 0xf2409001, 0xf7ff2000, 
+    0xb006fecd, 0x4ca3bd10, 0x21012200, 0xf0214620, 0xb990fbde, 0x46202201, 0xf0212102, 0xb960fbd8, 
+    0x46202202, 0xf0212104, 0xb930fbd2, 0x46202203, 0xf0212108, 0x2800fbcc, 0x2001d0d4, 0x4894e7d2, 
+    0xb087b530, 0xb9d07800, 0x22004c92, 0x46202101, 0xfbbdf021, 0x2201b988, 0x21024620, 0xfbb7f021, 
+    0x2202b958, 0x21044620, 0xfbb1f021, 0x2203b928, 0x21084620, 0xfbabf021, 0x2401b108, 0x2400e000, 
+    0x25019404, 0x9000200b, 0x462b2209, 0x5402e9cd, 0x94054611, 0x02689001, 0xfe80f7ff, 0x9000200c, 
+    0x94042301, 0x9405220a, 0x5402e9cd, 0x90014611, 0xf7ff02d8, 0xb007fe73, 0x220bbd30, 0x2000f240, 
+    0xb5104611, 0xfddaf7ff, 0xf640220c, 0xe8bd0000, 0x46114010, 0x486ee5d2, 0x7800b51c, 0x4c6db9d0, 
+    0x21012200, 0xf0214620, 0xb988fb72, 0x46202201, 0xf0212102, 0xb958fb6c, 0x46202202, 0xf0212104, 
+    0xb928fb66, 0x46202203, 0xf0212108, 0xb108fb60, 0xe0002401, 0xf2402400, 0x22092000, 0x46114623, 
+    0x94019400, 0xfcf3f7ff, 0x4623220a, 0xf6404611, 0x94000000, 0xf7ff9401, 0xbd1cfcea, 0x41ffe92d, 
+    0x466c2300, 0x429a2200, 0x2108d101, 0x2102e000, 0x1542eb00, 0xeb051e49, 0xe00305c3, 0xb91e5c6e, 
+    0xb2491e49, 0xdaf92900, 0x0582eb04, 0x1c521c49, 0x2a04b252, 0xdbe654e9, 0xb25b1c5b, 0xdbe12b04, 
+    0x46182300, 0x0180eb04, 0x42995609, 0x460bdd00, 0xb2401c40, 0xdbf52804, 0x22044d3c, 0x3d2821f0, 
+    0xf0214628, 0x2300faef, 0x20004619, 0xd0054288, 0x0280eb04, 0x429a5652, 0x4613dd00, 0xb2401c40, 
+    0xdbf32804, 0xb2491c49, 0xdbee2904, 0x46282200, 0xf0212103, 0x4d2dfad7, 0x46283518, 0xfac6f021, 
+    0x4601230f, 0x27012200, 0xeb042000, 0x5cb60680, 0xfa07b916, 0x43b1f603, 0x1e5b1c40, 0x2804b240, 
+    0x1c52dbf3, 0x2a04b252, 0x4628dbee, 0xfab1f021, 0x81ffe8bd, 0x41f0e92d, 0x46042300, 0x20004619, 
+    0xd0054288, 0x0280eb04, 0x429a5652, 0x4613dd00, 0xb2401c40, 0xdbf32804, 0xb2491c49, 0xdbee2904, 
+    0x22084812, 0x38280151, 0xfa9cf021, 0x35184d0f, 0xf0214628, 0x231ffa8b, 0x22004601, 0x20002601, 
+    0x0780eb04, 0xb9175cbf, 0xf703fa06, 0x1c4043b9, 0xb2401e5b, 0xdbf32804, 0xb2521c52, 0xdbee2a04, 
+    0xe8bd4628, 0xf02141f0, 0x0000ba74, 0xf1000030, 0x0004055c, 0xf2030024, 0x22002301, 0xb5104619, 
+    0xf02148fe, 0x2300fa86, 0x210148fd, 0xf021461a, 0xe8bdfa80, 0x48fb4010, 0x0140f242, 0xba5ff021, 
+    0x4df7b570, 0x2203b28b, 0x1ead4604, 0x46282108, 0xfa6ff021, 0x4628b2a3, 0x4070e8bd, 0x21042202, 
+    0xba67f021, 0x4deeb570, 0x2201b28b, 0x1ead4604, 0x46282102, 0xfa5df021, 0x4628b2a3, 0x4070e8bd, 
+    0x21012200, 0xba55f021, 0x4de5b570, 0x2206b283, 0x1ead460c, 0x46282140, 0xfa4bf021, 0x4628b2a3, 
+    0x4070e8bd, 0x21202205, 0xba43f021, 0x48dcb283, 0xf2402208, 0x1e803100, 0xba3bf021, 0x41f0e92d, 
+    0x4690461f, 0x46084604, 0x5606e9dd, 0xffeef7ff, 0x462043e1, 0xffd8f7ff, 0x46404639, 0xffc2f7ff, 
+    0x46284631, 0x41f0e8bd, 0xb570e7aa, 0x23014dcc, 0x03de220f, 0x46311ead, 0xf0214628, 0x2301fa1a, 
+    0x22074628, 0xf0212180, 0x2001fa14, 0xffcef7ff, 0xe00f0234, 0xf7fe4620, 0x1e04fe8d, 0x4cc2dc0a, 
+    0xf0214620, 0xf040f9e9, 0x46200101, 0x4070e8bd, 0xb9e5f021, 0x4631220f, 0xf0214628, 0x2800fa08, 
+    0xbd70d1e8, 0x230148b6, 0x21102204, 0xf0211e80, 0xe92db9f0, 0x4db241f0, 0x4000f500, 0xb281460f, 
+    0x46283d14, 0xf9cbf021, 0x0400f44f, 0xe00e1226, 0xf7fe4620, 0x1e04fe5f, 0x4cabdc09, 0xf0214620, 
+    0xf040f9bb, 0x46200102, 0xf9b9f021, 0x220fe006, 0x46284631, 0xf9dbf021, 0xd1e92800, 0xf2424639, 
+    0xe8bd0000, 0xf7fe41f0, 0xb570be47, 0x46164d9e, 0x4604220f, 0x460b3d9a, 0x0100f248, 0xf0214628, 
+    0x220df9b8, 0xf2464633, 0x46280100, 0xf9b1f021, 0x4628b2a3, 0x4070e8bd, 0xf6412200, 0xf02171ff, 
+    0xb283b9a8, 0x2200488e, 0x30602101, 0xb9a1f021, 0x41f0e92d, 0x461e4d8a, 0xf248b293, 0x35200400, 
+    0x220f4688, 0x46214607, 0xf0214628, 0xb2bbf992, 0x77fff240, 0x46392200, 0xf0214628, 0x4621f98a, 
+    0xb2b31eac, 0x220f4620, 0xf983f021, 0xf388fa1f, 0x46204639, 0x41f0e8bd, 0xf0212200, 0xb570b97a, 
+    0x48794605, 0x46162301, 0x460c3892, 0x461a2102, 0xf96ff021, 0x0045ea44, 0xb2834c73, 0x71fff640, 
+    0x22003c8e, 0xf0214620, 0x2301f964, 0x220c4620, 0xf0210319, 0x4631f95e, 0x4070e8bd, 0xf7fe2004, 
+    0xb570bddb, 0x48684605, 0x46162301, 0x460c3898, 0x461a2102, 0xf94df021, 0x0045ea44, 0xb2834c62, 
+    0x71fff640, 0x22003c96, 0xf0214620, 0x2301f942, 0x220c4620, 0xf0210319, 0x4631f93c, 0x4070e8bd, 
+    0xf7fe2004, 0xe92dbdb9, 0x4d5847f0, 0x461f0004, 0x46894690, 0x0300f04f, 0xf240d418, 0x46282600, 
+    0x46312209, 0xf925f021, 0x2301e00d, 0x22094631, 0xf0214628, 0x2300f91e, 0x22094631, 0xf0214628, 
+    0x1e64f918, 0x2c00b224, 0xe016dcef, 0x46282208, 0x46310156, 0xf90df021, 0x2301e00d, 0x22084631, 
+    0xf0214628, 0x2300f906, 0x22084631, 0xf0214628, 0x1c64f900, 0x2c00b224, 0x2004dbef, 0xf7fe4639, 
+    0x463afd7b, 0x46484641, 0x47f0e8bd, 0xb570e777, 0xb2834d33, 0x4604220b, 0xf6401cad, 0x46280100, 
+    0xf8e7f021, 0x4628b2a3, 0x4070e8bd, 0xf241220c, 0xf0210100, 0xe92db8de, 0x4c2d41f0, 0x46062904, 
+    0x2800f240, 0x4500f240, 0x2905d002, 0xe009d004, 0x46032209, 0xe0024641, 0x4603220a, 0x46204629, 
+    0xf8c7f021, 0x220c4f1e, 0xf2414633, 0x1ebf0100, 0xf0214638, 0x220df8be, 0xf2424633, 0x46380100, 
+    0xf8b7f021, 0x4633220b, 0x0100f640, 0xf0214638, 0x2202f8b0, 0x21044633, 0xf0211cb8, 0x4811f8aa, 
+    0xf0213010, 0x220ff889, 0x1d384633, 0x0100f248, 0xf89ff021, 0x2300b98e, 0x220a4629, 0xf0214638, 
+    0x2209f898, 0x46414633, 0xf0214620, 0x220af892, 0x46294633, 0xf0214620, 0xe00bf88c, 0xf2020126, 
+    0xf2035024, 0xf2020000, 0xf203517e, 0xf2035092, 0xf2039000, 0xe8bd2001, 0xb57081f0, 0x46042300, 
+    0x21082203, 0x46284dfe, 0xf873f021, 0x46282300, 0x21042202, 0xf86df021, 0x46282300, 0x461a2101, 
+    0xf867f021, 0x1cae2300, 0x2101461a, 0xf0214630, 0xb374f860, 0xd0362c01, 0xd0342c02, 0xd1402c03, 
+    0x46282300, 0x21102204, 0xf853f021, 0x46302300, 0x21042202, 0xf84df021, 0x46282301, 0x21082203, 
+    0xf847f021, 0x46282301, 0x21042202, 0xf841f021, 0x46282301, 0x46192200, 0xf83bf021, 0x22002301, 
+    0x46304619, 0xf835f021, 0xe8bd2000, 0xf0144070, 0x2300bcaf, 0x22044628, 0xf0212110, 0x2300f82a, 
+    0x21042202, 0x2301e7ed, 0x22044628, 0xf0212110, 0x2301f820, 0x22024630, 0xf0212104, 0x2001f81a, 
+    0xbd70e7e3, 0x5ff0e92d, 0x48cd4604, 0x4693469a, 0x46892200, 0xf240387c, 0xf24033c2, 0xf02171ff, 
+    0xf8dff808, 0x2c04831c, 0x0500f247, 0x1600f240, 0x087ef1a8, 0x6700f240, 0x2c05d002, 0xe01cd01a, 
+    0x0f00f1b9, 0xf1bad119, 0xd0160f03, 0x46402301, 0x46192200, 0xffedf020, 0x46402302, 0x21062201, 
+    0xffe7f020, 0x46312301, 0x46402208, 0xffe1f020, 0xe02f2302, 0x0f00f1bb, 0x2300d019, 0x22014640, 
+    0xf0202106, 0x2300ffd6, 0x22094639, 0xf0204640, 0x2300ffd0, 0x22084631, 0xf0204640, 0x2300ffca, 
+    0x461a2101, 0xe8bd4640, 0xf0205ff0, 0x2301bfc2, 0x22004640, 0xf0204619, 0x2303ffbc, 0x22014640, 
+    0xf0202106, 0x2301ffb6, 0x22084631, 0xf0204640, 0x2303ffb0, 0x22094639, 0xf0204640, 0x2301ffaa, 
+    0x220c4629, 0xe92de7de, 0x4c955ff0, 0x4f944605, 0x3f503c5a, 0xf8dfb151, 0x29018248, 0x76fff64f, 
+    0x0836f1a8, 0x2902d00c, 0xe060d020, 0x46202300, 0x461a2101, 0xff8df020, 0x21012300, 0xe0cb461a, 
+    0x46202301, 0x21042202, 0xff83f020, 0x46202300, 0x21082203, 0xff7df020, 0x46402101, 0xff5ff020, 
+    0x4631487f, 0xf0203834, 0xe040ff5a, 0x46202300, 0x21042202, 0xff6df020, 0x46202301, 0x21082203, 
+    0xff67f020, 0x1101f240, 0xf0204640, 0x4874ff48, 0x38324631, 0xff43f020, 0x46314871, 0xf0203830, 
+    0x486fff3e, 0x382e4631, 0xff39f020, 0x4631486c, 0xf020382c, 0x486aff34, 0x382a4631, 0xff2ff020, 
+    0x46314867, 0xf0203828, 0x4865ff2a, 0x38264631, 0xff25f020, 0x46314862, 0xf0203824, 0x4861ff20, 
+    0xf2402208, 0x78037100, 0xf0204638, 0x4e5cff32, 0x78fff640, 0xb168f8df, 0x7afff240, 0x2d043e58, 
+    0x0902f106, 0x0b7cf1ab, 0x2d05d002, 0xe041d01f, 0xf6402200, 0x46413356, 0xf0204630, 0xf240ff1a, 
+    0x464135c2, 0x462b2200, 0xf0204648, 0x2200ff12, 0x4651462b, 0xf0204658, 0x2303ff0c, 0x0100f24f, 
+    0x4638220c, 0xff05f020, 0x7394f240, 0x2200e01d, 0x439af640, 0x46304641, 0xfefbf020, 0xf2402200, 
+    0x46415304, 0xf0204648, 0x2200fef4, 0x2382f240, 0x46584651, 0xfeedf020, 0xf24f2306, 0x220c0100, 
+    0xf0204638, 0xf240fee6, 0x46417396, 0x46302200, 0xfedff020, 0x46202300, 0x21102204, 0xfed9f020, 
+    0x46202301, 0x46192200, 0xfed3f020, 0x46382301, 0x46192200, 0xfecdf020, 0x23204829, 0x213f2200, 
+    0xf0203854, 0x2301fec6, 0x22024638, 0xf0202104, 0x2300fec0, 0x21102204, 0xe8bd4638, 0xf0205ff0, 
+    0xe92dbeb8, 0x460541f0, 0x460c8800, 0x4000f500, 0x481db281, 0xfe93f020, 0xf5008868, 0xb2814000, 
+    0x1c804819, 0xfe8bf020, 0xf50088a8, 0xb2814000, 0x1d004815, 0xfe83f020, 0xf50088e8, 0xb2814000, 
+    0x1d804811, 0xfe7bf020, 0x4d0f8820, 0x4000f500, 0x3508b281, 0xf0204628, 0x8860fe72, 0xf5001cae, 
+    0xb2814000, 0xf0204630, 0x88a0fe6a, 0xf5001d2f, 0xb2814000, 0xf0204638, 0x88e0fe62, 0x0000e006, 
+    0xf2035336, 0x00040340, 0xf20351ac, 0x4000f500, 0x1dacb281, 0xf0204620, 0x4628fe52, 0xfe4cf020, 
+    0xf0204630, 0x4638fe49, 0xfe46f020, 0xe8bd4620, 0xf02041f0, 0xe92dbe41, 0x4b1841f0, 0x4c182802, 
+    0x4e194d18, 0xd0044f19, 0xd01e2801, 0x1c408808, 0x2a008008, 0x8819d020, 0xf0204815, 0x4814fe30, 
+    0x1c808821, 0xfe2bf020, 0x88294811, 0xf0201d00, 0x480ffe26, 0x1d808831, 0xfe21f020, 0xe8bd8839, 
+    0x480b41f0, 0xf0203008, 0x2000be1a, 0x80208018, 0x80308028, 0xe7dc8038, 0x0000e5ad, 0x0004054c, 
+    0x0004054e, 0x00040550, 0x00040552, 0x00040554, 0xf2035164, 0x47f0e92d, 0x460c2301, 0x461a2102, 
+    0x46284dfe, 0xfe15f020, 0x780949fd, 0x2301b929, 0x22004628, 0xf0204619, 0xf8dffe0c, 0x230193e0, 
+    0x03de220f, 0x0902f109, 0x46484631, 0xfe01f020, 0xf2464df4, 0x220d0800, 0x68284641, 0x3020f890, 
+    0xf0204648, 0x6828fdf6, 0x77fff641, 0x46392200, 0x46488c43, 0xfdedf020, 0x0902f109, 0x23004631, 
+    0x220f4648, 0xfde5f020, 0x220d6828, 0xf8904641, 0x46483026, 0xfdddf020, 0x22006828, 0x8c834639, 
+    0xf0204648, 0xf109fdd6, 0x46310902, 0x46482301, 0xf020220f, 0x6828fdce, 0x4641220d, 0x302cf890, 
+    0xf0204648, 0x6828fdc6, 0x46392200, 0x46488dc3, 0xfdbff020, 0x0902f109, 0x23014631, 0x220f4648, 
+    0xfdb7f020, 0x2c01b134, 0x2c02d008, 0x2c03d006, 0xe00fd008, 0xf8906828, 0xe0063027, 0xf8906828, 
+    0xe0023028, 0xf8906828, 0x220d3029, 0x46484641, 0xfd9ff020, 0x22006828, 0x8d434639, 0xf0204648, 
+    0xf8dffd98, 0x230092f8, 0x4631220f, 0x090af109, 0xf0204648, 0x6828fd8e, 0x4644220d, 0xf8904641, 
+    0x46483034, 0xfd85f020, 0x22006828, 0x8ec34639, 0xf0204648, 0x4631fd7e, 0x0602f109, 0x46302300, 
+    0xf020220f, 0x6828fd76, 0x4621220d, 0x3030f890, 0xf0204630, 0x6828fd6e, 0x46392200, 0x3048f8b0, 
+    0x30f048a6, 0xfd65f020, 0x7e806828, 0x47f0e8bd, 0xbbe5f000, 0x47f0e92d, 0xf6414ca3, 0xf8df7100, 
+    0xf240c288, 0x3c9635f0, 0x0600f24f, 0xf04f1ca7, 0x28040306, 0x0208f04f, 0x0902f10c, 0x46604688, 
+    0xf020d02d, 0x2303fd46, 0x22004620, 0xf020210f, 0x230cfd40, 0x22044629, 0xf0204620, 0x2304fd3a, 
+    0x220c4631, 0xf0204620, 0x2303fd34, 0x22004638, 0xf020210f, 0x230dfd2e, 0x22044629, 0xf0204638, 
+    0x2302fd28, 0x22084641, 0xf0204648, 0x4631fd22, 0xe8bd4638, 0x230447f0, 0xf020220c, 0xf020bd1a, 
+    0x2303fd18, 0x22004620, 0xf020210f, 0x230bfd12, 0x22044629, 0xf0204620, 0x2304fd0c, 0x220c4631, 
+    0xf0204620, 0x2303fd06, 0x22004638, 0xf020210f, 0x230cfd00, 0xe92de7d0, 0x240041fc, 0x94012003, 
+    0xfa56f7fe, 0xf7fe2002, 0x2001fa53, 0xfa50f7fe, 0xf7fe2011, 0x2012fa4d, 0xfa4af7fe, 0xf7fe2001, 
+    0x2002f914, 0xf911f7fe, 0xf7fe2004, 0x2301f90e, 0x220c4866, 0xf0200319, 0x4865fcdc, 0x48657004, 
+    0x20007004, 0xfb36f014, 0x68004863, 0xd1072801, 0xf6404862, 0x60040100, 0x68004861, 0xfca8f021, 
+    0x88004860, 0x2301b128, 0x2200485f, 0xf0204619, 0xf004fcc0, 0x485dfc28, 0xb9107800, 0xf7ff2001, 
+    0x2200fbc6, 0x0300f641, 0x46112004, 0xf0019400, 0x4857fc8b, 0x28017800, 0x2000d102, 0xfc55f003, 
+    0x78014854, 0xf7ff2000, 0x2001fbc6, 0xff2cf010, 0xfbcaf011, 0x23004841, 0x21022201, 0xf02038b0, 
+    0x4c3efc98, 0x23002208, 0x01513452, 0xf0204620, 0x4d49fc90, 0x22032301, 0x46282108, 0xfc89f020, 
+    0x46282300, 0x21082203, 0xfc83f020, 0x78084943, 0xfc1ef7fd, 0x4e422301, 0x035d220d, 0x46294630, 
+    0xfc77f020, 0xf2481db7, 0x23010800, 0x220f4641, 0xf0204638, 0x2300fc6e, 0x220f4641, 0xf0204638, 
+    0x2300fc68, 0x220d4629, 0xf0204630, 0x2000fc62, 0xfa1cf7ff, 0xfb14f7f8, 0x23004d20, 0x461a2101, 
+    0x46283dbc, 0xfc55f020, 0x46282300, 0x21022201, 0xfc4ff020, 0x46282300, 0x21042202, 0xfc49f020, 
+    0x46282300, 0x21082203, 0xfc43f020, 0x7600f647, 0x46312300, 0x1d282208, 0xfc3bf020, 0x1daf2300, 
+    0x217f461a, 0xf0204638, 0x2300fc34, 0x22084631, 0xf0204638, 0x21d2fc2e, 0xf0201ca8, 0x2100fc10, 
+    0xf0204628, 0x4810fc0c, 0x220f2300, 0x38c44641, 0xfc1ff020, 0xf44f4d01, 0xe0230100, 0xf20350d4, 
+    0x0004055c, 0x000405f8, 0xf2035332, 0xf203902c, 0x00040244, 0x000402fa, 0x00057f74, 0x00057ff0, 
+    0x0004022c, 0x00040288, 0xf38f20e0, 0x00040556, 0x000402e2, 0x0004028a, 0xf2036100, 0x0004028b, 
+    0xf23c8306, 0x4f1535a8, 0x9101138e, 0x2103e00c, 0xa801462a, 0xf905f7fe, 0xd00c2801, 0x46312301, 
+    0x46202209, 0xfbe5f020, 0x46382206, 0xf0202140, 0x2800fbee, 0xe8bdd1eb, 0x210281fc, 0x422bf04f, 
+    0xb5100488, 0xf845f7f7, 0xf0022003, 0x2006ff1d, 0xff1af002, 0x4010e8bd, 0xbb4ff001, 0xf203502c, 
+    0x41f0e92d, 0x845cf8df, 0xb283461c, 0x22064615, 0x21c0460e, 0x46404607, 0xfbbbf020, 0x4640b2b3, 
+    0x21302204, 0xfbb5f020, 0x4640b2ab, 0x210c2202, 0xfbaff020, 0x4640b2a3, 0x21032200, 0xfba9f020, 
+    0x8420f8df, 0x2206b2bb, 0x081cf108, 0x464021c0, 0xfb9ff020, 0x4640b2b3, 0x21302204, 0xfb99f020, 
+    0x4640b2ab, 0x210c2202, 0xfb93f020, 0x4640b2a3, 0x21032200, 0xfb8df020, 0x4ffbb2bb, 0x21032200, 
+    0xf0204638, 0xb2b3fb86, 0x22024638, 0xf020210c, 0xb2abfb80, 0x22044638, 0xf0202130, 0xb2a3fb7a, 
+    0xe8bd4638, 0x220641f0, 0xf02021c0, 0xb570bb72, 0x23014cec, 0x46052200, 0x46193c40, 0xf0204620, 
+    0x4ae8fb68, 0x4620462b, 0x4070e8bd, 0x21013a2e, 0xba7ff021, 0x460db570, 0xf7ff4604, 0x2200ffe8, 
+    0x0022f854, 0xd90142a8, 0xbd702001, 0xb2521c52, 0xdbf52a04, 0xbd702000, 0x4605b570, 0x230048d9, 
+    0x0100f248, 0x3834220f, 0xfb43f020, 0x24004ed5, 0xf8353e12, 0xf3c00014, 0xf4400009, 0xeb066180, 
+    0xf0200044, 0x1c64fb1c, 0x2c04b264, 0xbd70dbf1, 0x48ccb283, 0x21012200, 0xf020383e, 0xe92dbb2a, 
+    0x4fc847f0, 0xf640b293, 0x46140800, 0x460d3f1e, 0x4606220b, 0x46384641, 0xfb1bf020, 0x0900f247, 
+    0xb2ab4638, 0x220c4649, 0xfb13f020, 0x0a00f248, 0xb2b34638, 0x220f4651, 0xfb0bf020, 0x46411cbf, 
+    0x4638b2a3, 0xf020220b, 0xb2abfb04, 0x220c4649, 0xf0204638, 0xb2b3fafe, 0x220f4651, 0xf0204638, 
+    0x1cbffaf8, 0xb2a34641, 0x220b4638, 0xfaf1f020, 0x4649b2ab, 0x4638220c, 0xfaebf020, 0x4651b2b3, 
+    0x4638220f, 0xfae5f020, 0x4641b2a3, 0x220b1cbc, 0xf0204620, 0xb2abfade, 0x220c4649, 0xf0204620, 
+    0xb2b3fad8, 0x46204651, 0x47f0e8bd, 0xf020220f, 0xb510bad0, 0x489b4604, 0xf020380a, 0xf000faad, 
+    0x8020001f, 0x38084897, 0xfaa6f020, 0x001ff000, 0x48948060, 0xf0201f80, 0xf000fa9f, 0x80a0001f, 
+    0x1f004890, 0xfa98f020, 0x001ff000, 0xbd1080e0, 0x2b03b570, 0x4605460c, 0xf992d108, 0x20011002, 
+    0x0011f825, 0x1003f992, 0x0011f825, 0x16e0f240, 0x22054886, 0xf0204631, 0x8821faaa, 0x44082205, 
+    0x48838020, 0xf0204631, 0x8861faa2, 0x44082205, 0x48808060, 0xf0204631, 0x88a1fa9a, 0x44082205, 
+    0x487d80a0, 0xf0204631, 0x88e1fa92, 0x80e04408, 0xf0012001, 0x2000fc81, 0xfc7ef001, 0x24004e71, 
+    0xf8153e0a, 0xf0000014, 0xf040001f, 0xeb060120, 0xf0200044, 0x1c64fa54, 0x2c04b264, 0xbd70dbf1, 
+    0x4605b5f0, 0xf5b52000, 0x46043f80, 0x210fd301, 0x2107e000, 0x2701004a, 0xf302fa07, 0xfa001c4a, 
+    0x4422f202, 0x42aa441a, 0xfa07d804, 0xea46f601, 0x46140000, 0xea4fd003, 0xf1a10393, 0x29000101, 
+    0x42aadb01, 0xbdf0d1ea, 0x460cb510, 0x48554601, 0xf0201e80, 0x4621fa24, 0xe8bd4858, 0xf0204010, 
+    0x4850ba1e, 0x21022301, 0x3840461a, 0xba31f020, 0x4d53b570, 0x4614b283, 0x220c460e, 0x0100f24f, 
+    0xf0204628, 0x2208fa26, 0xb2b34628, 0xf0200151, 0x2c03fa20, 0x2c02d013, 0x2c01d01b, 0x2c00d023, 
+    0x2300d12b, 0x22044628, 0xf0202110, 0x2300fa12, 0x461a2101, 0xe8bd4628, 0xf0204070, 0x2300ba0a, 
+    0x22074628, 0xf0202180, 0x2300fa04, 0x21082203, 0x2300e7f0, 0x22064628, 0xf0202140, 0x2300f9fa, 
+    0x21042202, 0x2300e7e6, 0x22054628, 0xf0202120, 0x2300f9f0, 0x21022201, 0xbd70e7dc, 0x4d30b570, 
+    0x460c2a03, 0x2a02d013, 0x2a01d01b, 0x2a00d023, 0xb283d12b, 0x22044628, 0xf0202110, 0x2200f9da, 
+    0x2101b2a3, 0xe8bd4628, 0xf0204070, 0xb283b9d2, 0x22074628, 0xf0202180, 0x2203f9cc, 0x2108b2a3, 
+    0xb283e7f0, 0x22064628, 0xf0202140, 0x2202f9c2, 0x2104b2a3, 0xb283e7e6, 0x22054628, 0xf0202120, 
+    0x2201f9b8, 0x2102b2a3, 0xbd70e7dc, 0x4814b283, 0x21012200, 0xf0201f00, 0xb570b9ac, 0x220c4c09, 
+    0x46034605, 0xf2413c46, 0x46200100, 0xf9a1f020, 0x4620462b, 0x4070e8bd, 0xf240220a, 0xf0204100, 
+    0x0000b998, 0xf2030446, 0xf2035124, 0xf203c65e, 0xf203ce5e, 0xf203d65e, 0xf203de5e, 0xf2031012, 
+    0xf2030024, 0x46032200, 0x210f48ca, 0xb981f020, 0xb51048c8, 0xf960f020, 0x000ff000, 0x4603bd10, 
+    0x220048c4, 0x31fff240, 0xf0203844, 0xb510b972, 0x46034604, 0x220748bf, 0x38482180, 0xf969f020, 
+    0x220048bc, 0x46232101, 0xf0201f00, 0x2200f962, 0xe8bd4623, 0x48b84010, 0xf0202101, 0xb570b95a, 
+    0x220d4cb4, 0x46034605, 0xf2423c48, 0x46200100, 0xf94ff020, 0x4620462b, 0x4070e8bd, 0xf640220b, 
+    0xf0200100, 0xe92db946, 0x4cac5ff0, 0x469b2140, 0x23014692, 0x22064681, 0xf0204620, 0x2301f93a, 
+    0x22024620, 0xf0202104, 0x2301f934, 0x21024620, 0xf020461a, 0x2301f92e, 0x22004620, 0xf0204619, 
+    0x1ca5f928, 0x46282301, 0x21402206, 0xf921f020, 0x46282301, 0x21042202, 0xf91bf020, 0x46282301, 
+    0x461a2102, 0xf915f020, 0x46282301, 0x46192200, 0xf90ff020, 0x23011d26, 0x22064630, 0xf0202140, 
+    0x2301f908, 0x22024630, 0xf0202104, 0x2301f902, 0x21024630, 0xf020461a, 0x2301f8fc, 0x22004630, 
+    0xf0204619, 0x1da7f8f6, 0x46382301, 0x21402206, 0xf8eff020, 0x46382301, 0x21042202, 0xf8e9f020, 
+    0x46382301, 0x461a2102, 0xf8e3f020, 0x46382301, 0x46192200, 0xf8ddf020, 0x0806f106, 0x46402301, 
+    0x21042202, 0xf8d5f020, 0x46402301, 0x461a2102, 0xf8cff020, 0x46402301, 0x46192200, 0xf8c9f020, 
+    0x0f03f1b9, 0xf1bad147, 0xd0250f01, 0x00fff00b, 0xd021281b, 0x46302100, 0xf8a1f020, 0x46382100, 
+    0xf89df020, 0x46202300, 0x21022201, 0xf8b1f020, 0x46202300, 0x461a2101, 0xf8abf020, 0x46282300, 
+    0x21022201, 0xf8a5f020, 0x46282300, 0x461a2101, 0x5ff0e8bd, 0xb89df020, 0x46202100, 0xf87ff020, 
+    0x46282100, 0xf87bf020, 0x46302300, 0x21042202, 0xf88ff020, 0x46302300, 0x21022201, 0xf889f020, 
+    0x46382300, 0x21042202, 0xf883f020, 0x46382300, 0x21022201, 0xe8bde7dc, 0xb5709ff0, 0x46144d45, 
+    0x460e2201, 0x460335aa, 0x46282102, 0xf871f020, 0x46281e64, 0x2204b2a3, 0xf0202170, 0x4633f86a, 
+    0xe8bd4628, 0x22004070, 0xf0202101, 0x4601b862, 0x30ac4838, 0xb843f020, 0x30ac4836, 0xb83cf020, 
+    0x4834b283, 0xf2402200, 0x381871ff, 0xb851f020, 0x4c30b510, 0x2200b283, 0x71fff643, 0x46203c32, 
+    0xf847f020, 0x46202301, 0xe8bd220e, 0x03994010, 0xb83ff020, 0x460b2203, 0x28012108, 0x2802d009, 
+    0x2804d004, 0x2202d107, 0xe0042104, 0x21022201, 0x2200e001, 0x48222101, 0xb82bf020, 0x460b220c, 
+    0xf2472801, 0xd0090100, 0xd0042802, 0xd1072804, 0x22081109, 0x2170e004, 0xe0012204, 0x22002107, 
+    0x1c804817, 0xb815f020, 0x48154601, 0xf01f1d00, 0x4813bff6, 0x1f00210f, 0xbff1f01f, 0x48104603, 
+    0x211f2200, 0xf0203828, 0x4601b804, 0x382a480c, 0xbfe5f01f, 0x480a4603, 0xf6402208, 0x382c7100, 
+    0xbff7f01f, 0x48064603, 0x21012200, 0xf01f382c, 0x0000bff0, 0xf2030448, 0xf2031012, 0xf2030000, 
+    0xf20305de, 0x41f0e92d, 0x48fe4604, 0xfc6ff7ff, 0x21004bfd, 0xf24a4dfd, 0x4afa0700, 0x2662f249, 
+    0xb9b05c60, 0x28126818, 0x2816d00d, 0xf995d00b, 0x28040000, 0x2805d007, 0xf852d005, 0x42b00021, 
+    0x2001d905, 0xf852e004, 0x42b80021, 0x2000d8f9, 0x1c495460, 0x2904b249, 0xe8bddbe2, 0x200181f0, 
+    0xf013b510, 0x2000fbd1, 0xfe41f7ff, 0xf2402100, 0xf7ff1000, 0x4ce6fd69, 0x68202100, 0x2038f890, 
+    0x003af9b0, 0xfde1f7fe, 0xf9b06820, 0xf7ff003e, 0x48e0ff4f, 0xf6407801, 0xe8bd0000, 0xf7fd4010, 
+    0xe92dbc1b, 0xb0874ff3, 0x90022000, 0x90049003, 0x48d79005, 0x88006800, 0x09d0ea4f, 0x90062004, 
+    0x780048d5, 0xd1012803, 0x90062002, 0xe0812700, 0x57c448d2, 0xb1f89808, 0xf930a802, 0xa8046014, 
+    0x5014f930, 0x12fff206, 0xf006fb16, 0x31fef240, 0x0005fb15, 0xd803428a, 0x12fff205, 0xd921428a, 
+    0xf7ff0100, 0xb200fcfd, 0xfb9104f1, 0x04e9f2f0, 0xf1f0fb91, 0xe0201080, 0x8304f8df, 0x4dc12301, 
+    0x46212200, 0xe9cd4618, 0xf7fc5800, 0xa802fa05, 0x6019f935, 0x5019f938, 0x6014f820, 0xf820a804, 
+    0xe7cf5014, 0xf7ff0280, 0xb200fcdb, 0xfb9105b1, 0x05a9f2f0, 0xf1f0fb91, 0x46801140, 0x3000f44f, 
+    0x1b62ea4f, 0x1a61ea4f, 0x0101f640, 0xfb53f7f6, 0x3000f44f, 0xf7f64631, 0xf44ffb3d, 0x46293000, 
+    0xfb38f7f6, 0x3000f44f, 0xf7f64651, 0xf44ffb33, 0x46593000, 0xfb2ef7f6, 0x3000f44f, 0xf7f64641, 
+    0x48a1fb29, 0xf18bfa1f, 0x0084eb00, 0xfef7f01f, 0xfa1f489d, 0x1c80f18a, 0x0084eb00, 0xfeeff01f, 
+    0xfa1f4899, 0x3810f188, 0x0044eb00, 0xfee7f01f, 0xb2ff1c7f, 0x42879806, 0xaf7af4ff, 0x23024c92, 
+    0xf64f2208, 0x3c1e7100, 0xf01f4620, 0x2201fef2, 0x210e4620, 0x234ff3c8, 0xfeebf01f, 0x22009807, 
+    0xb2832101, 0xf01f4620, 0xb009fee4, 0x8ff0e8bd, 0xb5102000, 0xfec8f7ff, 0x20082101, 0xfe9af7ff, 
+    0x20042101, 0xfe96f7ff, 0x20022101, 0xfe92f7ff, 0x46082101, 0xfe8ef7ff, 0x20082103, 0xfe9ef7ff, 
+    0x20042103, 0xfe9af7ff, 0x20022103, 0xfe96f7ff, 0x20012103, 0xfe92f7ff, 0x3000f240, 0xfeb5f7ff, 
+    0xf7ff2010, 0x2005feab, 0xfeb4f7ff, 0x4010e8bd, 0xbe9ff7ff, 0x2100486d, 0xf01fb510, 0xf7fffe90, 
+    0xe8bdffc7, 0x201c4010, 0xbbf1f7fd, 0x4ff0e92d, 0xb087485f, 0xb198f8df, 0x0814f10d, 0x0904f10d, 
+    0x88006800, 0x24000845, 0xf8cd46a2, 0xf8dba000, 0x22003000, 0x46562001, 0xb261465f, 0xf964f7fc, 
+    0x30fff04f, 0xf82846c4, 0xf8296014, 0x683a0014, 0x464b2000, 0xf932e011, 0x1e0f1010, 0x4279da00, 
+    0xe014f93c, 0xdd064571, 0xda002f00, 0xf82c427f, 0xf8237014, 0x1c400014, 0x42a8b200, 0xf933dbeb, 
+    0xf04f1014, 0x460f0c00, 0xf932e009, 0x28000011, 0x4240da00, 0x44601c49, 0xfc80fa0f, 0x42a9b209, 
+    0xa903dbf3, 0xea4f2000, 0xf8211cec, 0x46066014, 0xf932e00f, 0xf1bee010, 0xda010f00, 0x0e00f1ce, 
+    0xb2364476, 0xdd024566, 0x0014f821, 0x1c40e003, 0x4287b200, 0x1c64dced, 0x2c04b224, 0x2001dba5, 
+    0x46222400, 0x5010f933, 0x6014f933, 0xdd0042b5, 0xf9314604, 0xf9316010, 0x1bad7012, 0x6012f933, 
+    0x42b51bf6, 0x4602dd00, 0xb2001c40, 0xdbe92804, 0x0014f833, 0x3012f839, 0x1012f831, 0x0043ebc0, 
+    0x38081a40, 0x2c00b204, 0x07e0dd71, 0x1c64d001, 0x4d20b224, 0x88284e17, 0x0064eb00, 0x78318028, 
+    0xf7fe1060, 0x7833fc16, 0xf9b52201, 0x46201000, 0xfcc9f7fe, 0xf2407831, 0xf7fd1000, 0xf44ffa7d, 
+    0xf2400500, 0x462811f4, 0xfa15f7f6, 0x3134f04f, 0xf7f64628, 0xf9bdf9ff, 0x46281004, 0xf9faf7f6, 
+    0x0000e01a, 0x00041458, 0x00040238, 0x0004028a, 0x000405f8, 0x0004028b, 0x000405d9, 0x00040578, 
+    0x00049178, 0x00048978, 0xf2030040, 0xf2030400, 0x00040230, 0x00040560, 0x1006f9bd, 0xf7f64628, 
+    0xf9bdf9d9, 0x46281008, 0xf9d4f7f6, 0x100af9bd, 0xf7f64628, 0xf9bdf9cf, 0x4628100c, 0xf9caf7f6, 
+    0x100ef9bd, 0xf7f64628, 0xf9bdf9c5, 0x46281010, 0xf9c0f7f6, 0x1012f9bd, 0xf7f64628, 0x4621f9bb, 
+    0xf7f64628, 0x49bbf9b7, 0xf7f64628, 0xb007f9b3, 0xe92de6bc, 0x46065ffc, 0xf8df48b7, 0x250092e0, 
+    0x680046a8, 0xea4f8800, 0x24000b50, 0xd10242ac, 0x0000f04f, 0xda02e004, 0x0001f104, 0x4620e000, 
+    0x7000f8d9, 0xfa80fa4f, 0x463b4629, 0xf04f4652, 0xf8cd0001, 0xf7fc8000, 0xeb06f857, 0x5d400084, 
+    0x4659b958, 0xf0204638, 0x2300fd63, 0x20014652, 0xe9cd4629, 0xf7fb7800, 0x1c64ff74, 0x2c04b264, 
+    0x1c6ddbd4, 0x2d04b26d, 0x2400dbcf, 0x20004621, 0xd0044288, 0x0280eb06, 0xb1025c52, 0x1c402401, 
+    0x2804b240, 0x1c49dbf4, 0x2904b249, 0x4e94dbef, 0xf01f4630, 0xb200fd31, 0xf040b16c, 0x24000507, 
+    0xeb06b2a9, 0xf01f0044, 0x1c64fd2a, 0x2c04b264, 0xe8bddbf6, 0xf0209ffc, 0xe7f00507, 0x4ff0e92d, 
+    0x22004885, 0xf04f2101, 0xb087085a, 0x88006800, 0xf04f0847, 0xf01f4071, 0xb240fd23, 0x20009005, 
+    0xfe06f7fd, 0xa1f4f8df, 0x46b12600, 0x42b42400, 0xf04fd102, 0xe0040000, 0xf104da02, 0xe0000001, 
+    0xf8da4620, 0xb242b000, 0x465b4631, 0x0001f04f, 0x9000f8cd, 0xffe8f7fb, 0x463a2500, 0xfb074658, 
+    0xf014f105, 0x4540f882, 0x1e6ddc03, 0x2d00b26d, 0xa801daf3, 0x0084eb00, 0x42b41c6d, 0xd1015585, 
+    0x55812101, 0xb2641c64, 0xdbd02c04, 0xb2761c76, 0xdbcb2e04, 0xf7ffa801, 0xa801ff4c, 0xfa1af7fe, 
+    0xf7fd9805, 0xf44ffdc5, 0xf2400400, 0x462011f4, 0xf901f7f6, 0xf01f485a, 0x4601fcbf, 0xf7f64620, 
+    0x4857f8e9, 0xf01f1c80, 0x4601fcb7, 0xf7f64620, 0x4853f8e1, 0xf01f1d00, 0x4601fcaf, 0xf7f64620, 
+    0x484ff8d9, 0xf01f1d80, 0x4601fca7, 0xf7f64620, 0x484cf8d1, 0xfc9af01f, 0x46204601, 0xf8caf7f6, 
+    0x30404848, 0xfc92f01f, 0x46204601, 0xf8c2f7f6, 0x46204940, 0xf8bef7f6, 0xe92de709, 0x46074ff8, 
+    0xf8df483d, 0x240080f8, 0x460d4616, 0xf04f46a2, 0x68003bff, 0xea4f8800, 0xf8cd0950, 0xf8d8a000, 
+    0x22003000, 0xb2612001, 0xff6ef7fb, 0xa014f825, 0xb014f827, 0xf8262000, 0xe01bb014, 0x1000f8d8, 
+    0x1010f931, 0xda001e0b, 0xf9354259, 0x4561c014, 0x0019dd0e, 0x4259d500, 0x1014f825, 0x0014f827, 
+    0x1000f8d8, 0x1010f831, 0x31c0f3c1, 0x1014f826, 0xb2001c40, 0xdbe14548, 0xb2241c64, 0xdbcc2c04, 
+    0x8ff8e8bd, 0xe92d491c, 0x680943f8, 0x88094d1b, 0x0951ea4f, 0x91002100, 0x682b460a, 0x2001b241, 
+    0xff32f7fb, 0xf8d52200, 0x46138000, 0x46114610, 0xe0124614, 0x5014f838, 0xf505fb15, 0x195217ee, 
+    0xfba54173, 0x17e7ce04, 0xe604fb06, 0x6507fb05, 0x0000eb1c, 0x1c644169, 0x454cb224, 0xea52dbea, 
+    0xd0040403, 0xed9cf01e, 0xe8bdb200, 0x200083f8, 0x0000e7fb, 0xdcba01f5, 0x000405f8, 0x00040230, 
+    0xf2030000, 0xf1000008, 0x5fffe92d, 0x4cfa2301, 0x039f220e, 0x46394620, 0xfc1bf01f, 0x0800f241, 
+    0x23014620, 0x220c4641, 0xfc13f01f, 0x0900f640, 0x23014620, 0x220b4649, 0xfc0bf01f, 0x4a00f240, 
+    0x23014620, 0x220a4651, 0xfc03f01f, 0x2b00f240, 0x23014620, 0x22094659, 0xfbfbf01f, 0x46202208, 
+    0x01512301, 0xfbf5f01f, 0x46202301, 0x21802207, 0xfbeff01f, 0x46202301, 0x21402206, 0xfbe9f01f, 
+    0x46391ca5, 0x46282301, 0xf01f220e, 0x2301fbe2, 0x220c4641, 0xf01f4628, 0x2301fbdc, 0x220b4649, 
+    0xf01f4628, 0x2301fbd6, 0x220a4651, 0xf01f4628, 0x2301fbd0, 0x22094659, 0xf01f4628, 0x2208fbca, 
+    0x23014628, 0xf01f0151, 0x2301fbc4, 0x22074628, 0xf01f2180, 0x2301fbbe, 0x22064628, 0xf01f2140, 
+    0x1d26fbb8, 0x23014639, 0x220e4630, 0xfbb1f01f, 0x46412301, 0x4630220c, 0xfbabf01f, 0x46492301, 
+    0x4630220b, 0xfba5f01f, 0x46512301, 0x4630220a, 0xfb9ff01f, 0x46592301, 0x46302209, 0xfb99f01f, 
+    0x46302208, 0x01512301, 0xfb93f01f, 0x46302301, 0x21802207, 0xfb8df01f, 0x46302301, 0x21402206, 
+    0xfb87f01f, 0x1da74639, 0x46382301, 0xf01f220e, 0x2301fb80, 0x220c4641, 0xf01f4638, 0x2301fb7a, 
+    0x220b4649, 0xf01f4638, 0x2301fb74, 0x220a4651, 0xf01f4638, 0x2301fb6e, 0x22094659, 0xf01f4638, 
+    0x2208fb68, 0x23014638, 0xf01f0151, 0x2301fb62, 0x22074638, 0xf01f2180, 0x2301fb5c, 0x22064638, 
+    0xf01f2140, 0x2301fb56, 0x22054620, 0xf01f2120, 0x2301fb50, 0x22034620, 0xf01f2108, 0x2301fb4a, 
+    0x21024620, 0xf01f461a, 0x2301fb44, 0x22054628, 0xf01f2120, 0x2301fb3e, 0x22034628, 0xf01f2108, 
+    0x2301fb38, 0x21024628, 0xf01f461a, 0x2301fb32, 0x22054630, 0xf01f2120, 0x2301fb2c, 0x22034630, 
+    0xf01f2108, 0x2301fb26, 0x21024630, 0xf01f461a, 0x2301fb20, 0x22054638, 0xf01f2120, 0x2301fb1a, 
+    0x22034638, 0xf01f2108, 0x2301fb14, 0x21024638, 0xf01f461a, 0x2301fb0e, 0x22044620, 0xf01f2110, 
+    0x2301fb08, 0x22024620, 0xf01f2104, 0x2301fb02, 0x22004620, 0xf01f4619, 0x2301fafc, 0x22044628, 
+    0xf01f2110, 0x2301faf6, 0x22024628, 0xf01f2104, 0x2301faf0, 0x22004628, 0xf01f4619, 0x2301faea, 
+    0x22044630, 0xf01f2110, 0x2301fae4, 0x22024630, 0xf01f2104, 0x2301fade, 0x22004630, 0xf01f4619, 
+    0x2301fad8, 0x22044638, 0xf01f2110, 0x2301fad2, 0x22024638, 0xf01f2104, 0x2301facc, 0x22004638, 
+    0xf01f4619, 0x9800fac6, 0xd13e2803, 0x28019802, 0x9803d052, 0x281bb2c0, 0x2300d04e, 0x22034620, 
+    0xf01f2108, 0x2300fab6, 0x22024620, 0xf01f2104, 0x2300fab0, 0x22014620, 0xf01f2102, 0x2300faaa, 
+    0x21014620, 0xf01f461a, 0x2300faa4, 0x22034628, 0xf01f2108, 0x2300fa9e, 0x22024628, 0xf01f2104, 
+    0x2300fa98, 0x22014628, 0xf01f2102, 0x2300fa92, 0x21014628, 0xf01f461a, 0x2100fa8c, 0xf01f4630, 
+    0x2100fa6e, 0xf01f4638, 0x4c2bfa6a, 0x22022301, 0x21043408, 0xf01f4620, 0x2301fa7c, 0x21024620, 
+    0xf01f461a, 0xb004fa76, 0x23014620, 0x46192200, 0x5ff0e8bd, 0xba6df01f, 0x46202100, 0xfa4ff01f, 
+    0x46282100, 0xfa4bf01f, 0x46302300, 0x21202205, 0xfa5ff01f, 0x46302300, 0x21102204, 0xfa59f01f, 
+    0x46302300, 0x21082203, 0xfa53f01f, 0x46302300, 0x21042202, 0xfa4df01f, 0x46382300, 0x21202205, 
+    0xfa47f01f, 0x46382300, 0x21102204, 0xfa41f01f, 0x46382300, 0x21082203, 0xfa3bf01f, 0x46382300, 
+    0x21042202, 0xfa35f01f, 0x4603e7af, 0x22004802, 0x300e217f, 0xba2df01f, 0xf2031000, 0x4604b510, 
+    0xf64f4829, 0xf01f71ff, 0x4827fa0a, 0x1c802100, 0xfa05f01f, 0xb2a34824, 0x21012200, 0x4010e8bd, 
+    0xf01f1e80, 0xe92dba16, 0x4c1f41f0, 0xb283461d, 0x3c224616, 0x2206460f, 0x21c04620, 0xfa09f01f, 
+    0x4620b2bb, 0x21302204, 0xfa03f01f, 0x4620b2b3, 0x210c2202, 0xf9fdf01f, 0x4620b2ab, 0x41f0e8bd, 
+    0x21032200, 0xb9f5f01f, 0x480fb283, 0x21012200, 0xf01f3820, 0xb570b9ee, 0xd0130004, 0x4d0a2300, 
+    0x1ead2201, 0x46282102, 0xf9e3f01f, 0x4628b2a3, 0x21012200, 0xf9ddf01f, 0x1da82104, 0x4070e8bd, 
+    0xb9bdf01f, 0xe7ea2301, 0xf2031032, 0x5fffe92d, 0x48994681, 0xb264f8df, 0x68002500, 0xea4f8800, 
+    0x48970a50, 0x0045eb00, 0xf01f9003, 0xb207f9a5, 0x42ac2400, 0xf04fd102, 0xe0040000, 0xf104da02, 
+    0xe0000001, 0x42ac4620, 0x9002b240, 0xf04fd102, 0xe0010608, 0x0602f04f, 0xf04fd102, 0xe00b0106, 
+    0xf04fdd02, 0xe0010001, 0x0000f04f, 0x0000eba4, 0x0040ea4f, 0x0104f1c0, 0x0301f04f, 0x1244eb09, 
+    0x0001f1a6, 0x02c5eb02, 0x0c06eb01, 0x5c11e01e, 0xd01d2901, 0xdb102803, 0xd10e2c03, 0xd10c2d03, 
+    0x1000f819, 0xeb09b9a1, 0xf8910100, 0xf1bee028, 0xd10d0f00, 0x1050f891, 0xebacb951, 0x1e490100, 
+    0xf101fa03, 0x1e40438f, 0xb240b23f, 0xdade2800, 0x9a021c40, 0xf880fa4f, 0x20004629, 0xf8db9000, 
+    0xf7fb3000, 0x45b0fc41, 0xeba6da17, 0xf8db0108, 0x465e2000, 0xf00afb11, 0xfb18b281, 0xeb02f00a, 
+    0xf0200040, 0x2100f945, 0x9a026830, 0xe9cd460b, 0x20000100, 0xf7fb4629, 0x1c64fb54, 0x2c04b264, 
+    0xb2b9db87, 0xf01f9803, 0x1c6df92a, 0x2d04b26d, 0xaf77f6ff, 0x9fffe8bd, 0x4ff0e92d, 0xb0a3484e, 
+    0x88006800, 0x0850ea4f, 0x7800484e, 0xd2012850, 0xe0002020, 0x22002010, 0x21014681, 0x4071f04f, 
+    0xf91ef01f, 0x9021b240, 0xf7fd2000, 0xf8dffa01, 0x2600a10c, 0x240046b3, 0xd10242b4, 0x0000f04f, 
+    0xda02e004, 0x0001f104, 0x4620e000, 0xb24242b4, 0x2508d101, 0x2502e000, 0xb000f8cd, 0x3000f8da, 
+    0x46572000, 0xf7fb4631, 0xa801fbdf, 0xeb0046ba, 0x1e6d1044, 0x07c6eb00, 0xf8dae00e, 0x46420000, 
+    0xf105fb18, 0xfc71f013, 0xdd014548, 0xe0002001, 0x55782000, 0xb26d1e6d, 0xdaee2d00, 0xb2641c64, 
+    0xdbc92c04, 0xb2761c76, 0xdbc42e04, 0xf7ffa801, 0xa801ff0d, 0xfda2f7fd, 0xf7fd9821, 0xf44ff9b9, 
+    0xf2400400, 0x462011f4, 0xfcf5f7f5, 0xf01f481c, 0x4601f8b3, 0xf7f54620, 0x4819fcdd, 0xf01f1c80, 
+    0x4601f8ab, 0xf7f54620, 0x4815fcd5, 0xf01f1d00, 0x4601f8a3, 0xf7f54620, 0x4811fccd, 0xf01f1d80, 
+    0x4601f89b, 0xf7f54620, 0x480ffcc5, 0xf88ef01f, 0x46204601, 0xfcbef7f5, 0x3040480b, 0xf886f01f, 
+    0x46204601, 0xfcb6f7f5, 0x46204908, 0xfcb2f7f5, 0xe8bdb023, 0x00008ff0, 0x000405f8, 0x00040230, 
+    0xf2031000, 0x0004055e, 0xf1000008, 0xdcba01f5, 0x23004831, 0xf248220f, 0xb5100100, 0xf889f01f, 
+    0x7801482e, 0xf7fc2040, 0x2300fd07, 0x2201482c, 0x4010e8bd, 0xf01f2102, 0x210fb87c, 0x422bf04f, 
+    0x2000f44f, 0xf7f5b508, 0xf7fffce4, 0x2100ffe1, 0xf0004608, 0x2300f895, 0x21014822, 0xf01f461a, 
+    0x2000f868, 0x0200f242, 0x46014603, 0xf0009000, 0xbd08f83b, 0x481a4601, 0x29043022, 0x2905d006, 
+    0x2300d006, 0x21032200, 0xb853f01f, 0xe7f92303, 0xe7f72302, 0xf7ffb508, 0x2101ffed, 0xf0004608, 
+    0x2301f86f, 0x2102480e, 0xf01f461a, 0x2301f842, 0x2200480c, 0xf01f4619, 0x2000f83c, 0x7203f247, 
+    0xf6402317, 0x90004102, 0x1084f240, 0xf80cf000, 0x4008e8bd, 0xbde6f001, 0xf2035026, 0x0004028b, 
+    0xf23c8310, 0xf203529a, 0x47f0e92d, 0x460d4c6c, 0x461eb281, 0x8020f8dd, 0x46204617, 0xfffff01e, 
+    0x1ca5b2a9, 0xf01e4628, 0xf104fffa, 0xb2b90a04, 0xf01e4650, 0xb2b1fff4, 0x46301da6, 0xffeff01e, 
+    0xfa1f1daf, 0x4638f188, 0xffe9f01e, 0x2301b672, 0x916cf8df, 0x0800f248, 0x090cf109, 0x220f4641, 
+    0xf01e4648, 0x2300fff6, 0x220f4641, 0xf01e4648, 0xb662fff0, 0x46202100, 0xffd1f01e, 0x46282100, 
+    0xffcdf01e, 0x46502100, 0xffc9f01e, 0x46302100, 0xffc5f01e, 0xe8bd4638, 0x210047f0, 0xbfbff01e, 
+    0x4c47b570, 0x460d220a, 0x34104606, 0xf2404603, 0x46204100, 0xffcdf01e, 0x46332209, 0x2100f240, 
+    0xf01e4620, 0x462bffc6, 0xe8bd4620, 0x22024070, 0xf01e2104, 0xb510bfbe, 0x23014c39, 0x3410220e, 
+    0x46200399, 0xffb5f01e, 0x46202301, 0x21402206, 0xffaff01e, 0x48332301, 0x46192200, 0xffa9f01e, 
+    0x23014c31, 0x21102204, 0xf01e4620, 0x2301ffa2, 0x22024620, 0xf01e2104, 0x2301ff9c, 0x22034620, 
+    0xf01e2108, 0x2300ff96, 0x22044620, 0xf01e2110, 0x4c26ff90, 0x22042300, 0x46202110, 0xff89f01e, 
+    0x46202301, 0xe8bd2204, 0x21104010, 0xbf81f01e, 0x47f0e92d, 0x00054c1e, 0xe9dd4699, 0xd0098608, 
+    0xd00f2903, 0xd00d2905, 0xd00b2904, 0xd0092902, 0xd0072901, 0x46202300, 0x47f0e8bd, 0x21102204, 
+    0xbf67f01e, 0x210f4f13, 0x22004613, 0xf01e4638, 0x2204ff60, 0x21f0464b, 0xf01e4638, 0x220aff5a, 
+    0xf2404643, 0x46384100, 0xff53f01e, 0x4633220b, 0x0100f640, 0xf01e4638, 0x462bff4c, 0x0000e7db, 
+    0xf23c8300, 0xf23d0004, 0xf203529a, 0xf2039000, 0xf23c80a0, 0xf23d012a, 0x4cf9b570, 0x2801b398, 
+    0x2802d035, 0x2803d037, 0x2301d01f, 0x22004620, 0xf01e4619, 0xf44fff2e, 0x21003580, 0xf7fc4628, 
+    0x2301fbab, 0x21024620, 0xf01e461a, 0x2100ff22, 0xf7fc4628, 0x2301fba1, 0x22024620, 0xf01e2104, 
+    0x2100ff18, 0xf7fc4628, 0x2301fb97, 0x21082203, 0xf01e4620, 0x2300ff0e, 0xe8bd48e2, 0x21014070, 
+    0xf01e461a, 0x2301bf06, 0x46192200, 0x2301e7f0, 0x461a2102, 0x2301e7ec, 0x21042202, 0xb570e7e8, 
+    0xb3904cd7, 0xd0342801, 0xd0362802, 0xf04f2803, 0xd0360300, 0x46202200, 0xf01e2101, 0xf44ffeea, 
+    0x21003580, 0xf7fc4628, 0x2300fb67, 0x22014620, 0xf01e2102, 0x2100fede, 0xf7fc4628, 0x2300fb5d, 
+    0x22024620, 0xf01e2104, 0x2100fed4, 0xf7fc4628, 0x2300fb53, 0x22034620, 0xf01e2108, 0x4628feca, 
+    0x4070e8bd, 0xf7fc2100, 0x2300bb47, 0x461a2101, 0x2300e009, 0x21022201, 0x2300e005, 0x21042202, 
+    0x2203e001, 0x46202108, 0x4070e8bd, 0xbeb1f01e, 0x2202b510, 0x21044604, 0x48b34603, 0xfea9f01e, 
+    0x220248b2, 0x46232104, 0xfea3f01e, 0x220248b0, 0x46232104, 0xfe9df01e, 0x46232202, 0x4010e8bd, 
+    0x210448ac, 0xbe95f01e, 0x4604b510, 0x48a64603, 0x21102204, 0xf01e380c, 0x48a4fe8c, 0x21102204, 
+    0x380c4623, 0xfe85f01e, 0x220448a1, 0x46232110, 0xf01e380c, 0x489ffe7e, 0x21102204, 0xe8bd4623, 
+    0x380c4010, 0xbe75f01e, 0x4605b570, 0x48964603, 0x2400f240, 0x46212209, 0xf01e3814, 0x4893fe6a, 
+    0x462b2209, 0x38144621, 0xfe63f01e, 0x22094890, 0x4621462b, 0xf01e3814, 0x488efe5c, 0x4621462b, 
+    0x4070e8bd, 0x38142209, 0xbe53f01e, 0x2200b510, 0x21014604, 0x48844603, 0xfe4bf01e, 0x22004883, 
+    0x46232101, 0xfe45f01e, 0x22004881, 0x46232101, 0xfe3ff01e, 0x46232200, 0x4010e8bd, 0x2101487d, 
+    0xbe37f01e, 0x2204b510, 0x21304604, 0x48764603, 0xfe2ff01e, 0x22044875, 0x46232130, 0xfe29f01e, 
+    0x22044873, 0x46232130, 0xfe23f01e, 0x46232204, 0x4010e8bd, 0x2130486f, 0xbe1bf01e, 0xf240b570, 
+    0x460514c0, 0x46032206, 0x46214867, 0xfe11f01e, 0x22064866, 0x4621462b, 0xfe0bf01e, 0x22064864, 
+    0x4621462b, 0xfe05f01e, 0x4621462b, 0x4070e8bd, 0x22064860, 0xbdfdf01e, 0x2201b510, 0x21024604, 
+    0x48594603, 0xfdf5f01e, 0x22014858, 0x46232102, 0xfdeff01e, 0x22014856, 0x46232102, 0xfde9f01e, 
+    0x46232201, 0x4010e8bd, 0x21024852, 0xbde1f01e, 0x41f0e92d, 0x23004c4c, 0x46802101, 0x461a3c24, 
+    0xf01e4620, 0x4d49fdd6, 0x21012300, 0x3d24461a, 0xf01e4628, 0x4e46fdce, 0x21012300, 0x3e24461a, 
+    0xf01e4630, 0x4f43fdc6, 0x21012300, 0x3f24461a, 0xf01e4638, 0x2200fdbe, 0x21014643, 0xf01e4620, 
+    0x2200fdb8, 0x21014643, 0xf01e4628, 0x2200fdb2, 0x21014643, 0xf01e4630, 0x4643fdac, 0xe8bd4638, 
+    0x220041f0, 0xf01e2101, 0xb510bda4, 0x46034604, 0x2204482d, 0x38202170, 0xfd9bf01e, 0x2204482b, 
+    0x46232170, 0xf01e3820, 0x4829fd94, 0x21702204, 0x38204623, 0xfd8df01e, 0x22044826, 0x46232170, 
+    0x4010e8bd, 0xf01e3820, 0xb570bd84, 0x22004c1c, 0x46052101, 0x46031ca4, 0xf01e4620, 0x2201fd7a, 
+    0x2102462b, 0xf01e4620, 0x2202fd74, 0x2104462b, 0xf01e4620, 0x462bfd6e, 0xe8bd4620, 0x22034070, 
+    0xf01e2108, 0xb510bd66, 0x46042201, 0x46032106, 0xf01e4811, 0x4811fd5e, 0x21062201, 0xf01e4623, 
+    0x480ffd58, 0x21062201, 0xf01e4623, 0x2201fd52, 0xe8bd4623, 0x480b4010, 0xf01e2106, 0x0000bd4a, 
+    0xf2034222, 0xf20305cc, 0xf203c624, 0xf203ce24, 0xf203d624, 0xf203de24, 0xf203c186, 0xf203c986, 
+    0xf203d186, 0xf203d986, 0x47f0e92d, 0x460f4691, 0x46042204, 0x46032110, 0xf01e48f8, 0x48f8fd2a, 
+    0x21102204, 0xf01e4623, 0x48f6fd24, 0x21102204, 0xf01e4623, 0x48f4fd1e, 0x21102204, 0xf01e4623, 
+    0x4ceefd18, 0x0600f241, 0x463b220c, 0x46313486, 0xf01e4620, 0x4deafd0e, 0x463b220c, 0x35864631, 
+    0xf01e4628, 0xf8dffd06, 0x220c839c, 0x4631463b, 0x0886f108, 0xf01e4640, 0x4631fcfc, 0x220c4ee2, 
+    0x3686463b, 0xf01e4630, 0xf242fcf4, 0x464b0700, 0x4639220d, 0xf01e4620, 0x220dfcec, 0x4639464b, 
+    0xf01e4628, 0x220dfce6, 0x4639464b, 0xf01e4640, 0x464bfce0, 0x46304639, 0x47f0e8bd, 0xf01e220d, 
+    0xb570bcd8, 0x75e0f641, 0xb2834604, 0x220548cf, 0xf01e4629, 0xb2a3fcce, 0x220548cd, 0xf01e4629, 
+    0xb2a3fcc8, 0x220548cb, 0xf01e4629, 0xb2a3fcc2, 0xe8bd4629, 0x48c84070, 0xf01e2205, 0xb570bcba, 
+    0xf0004ec6, 0xf3c00503, 0x22020482, 0x211c4623, 0xf01e4630, 0x2200fcae, 0x2103462b, 0xf01e4630, 
+    0x4ebffca8, 0x211c2202, 0x46304623, 0xfca1f01e, 0x462b2200, 0x46302103, 0xfc9bf01e, 0x22024eb9, 
+    0x4623211c, 0xf01e4630, 0x2200fc94, 0x2103462b, 0xf01e4630, 0x4623fc8e, 0x22024cb3, 0x4620211c, 
+    0xfc87f01e, 0x4620462b, 0x4070e8bd, 0x21032200, 0xbc7ff01e, 0x4604b510, 0x48a04603, 0x21382203, 
+    0xf01e3008, 0x489efc76, 0x21382203, 0x30084623, 0xfc6ff01e, 0x2203489b, 0x46232138, 0xf01e3008, 
+    0x4899fc68, 0x21382203, 0xe8bd4623, 0x30084010, 0xbc5ff01e, 0x4ff7e92d, 0xa250f8df, 0x0601f002, 
+    0x09c0f3c2, 0xf1aa460c, 0x9b000a08, 0x0880f3c2, 0x0100f643, 0x0740f3c2, 0x220b4650, 0xfc49f01e, 
+    0x0503f004, 0x0100f24c, 0x462b220e, 0xf01e4650, 0xf3c4fc40, 0x22000380, 0x2101461c, 0x0002f10a, 
+    0xfc37f01e, 0x4b00f240, 0x23004650, 0x220a4659, 0xfc2ff01e, 0x46592301, 0x4650220a, 0xfc29f01e, 
+    0x46592300, 0x4650220a, 0xfc23f01e, 0xa1e0f8df, 0x9b00220b, 0x0100f643, 0x0a08f1aa, 0xf01e4650, 
+    0x220efc18, 0xf24c462b, 0x46500100, 0xfc11f01e, 0x46232200, 0xf10a2101, 0xf01e0002, 0x2300fc0a, 
+    0x220a4659, 0xf01e4650, 0x2301fc04, 0x220a4659, 0xf01e4650, 0x2300fbfe, 0x220a4659, 0xf01e4650, 
+    0xf8dffbf8, 0x220ba190, 0xf6439b00, 0xf1aa0100, 0x46500a08, 0xfbedf01e, 0x462b220e, 0x0100f24c, 
+    0xf01e4650, 0x2200fbe6, 0x21014623, 0x0002f10a, 0xfbdff01e, 0x46592300, 0x4650220a, 0xfbd9f01e, 
+    0x46592301, 0x4650220a, 0xfbd3f01e, 0x46592300, 0x4650220a, 0xfbcdf01e, 0xa13cf8df, 0x9b00220b, 
+    0x0100f643, 0x0a08f1aa, 0xf01e4650, 0x220efbc2, 0xf24c462b, 0x46500100, 0xfbbbf01e, 0x46232200, 
+    0xf10a2101, 0xf01e0002, 0x2300fbb4, 0x220a4659, 0xf01e4650, 0x2301fbae, 0x220a4659, 0xf01e4650, 
+    0x2300fba8, 0x220a4659, 0xf01e4650, 0x4c37fba2, 0x21012200, 0x4620463b, 0xfb9bf01e, 0x464b2201, 
+    0x46202102, 0xfb95f01e, 0x46432202, 0x46202104, 0xfb8ff01e, 0x46332203, 0x46202108, 0xfb89f01e, 
+    0x22004c2b, 0x463b2101, 0xf01e4620, 0x2201fb82, 0x2102464b, 0xf01e4620, 0x2202fb7c, 0x21044643, 
+    0xf01e4620, 0x2203fb76, 0x21084633, 0xf01e4620, 0x4c20fb70, 0x21012200, 0x4620463b, 0xfb69f01e, 
+    0x464b2201, 0x46202102, 0xfb63f01e, 0x46432202, 0x46202104, 0xfb5df01e, 0x46332203, 0x46202108, 
+    0xfb57f01e, 0x22004c14, 0x463b2101, 0xf01e4620, 0x2201fb50, 0x2102464b, 0xf01e4620, 0x2202fb4a, 
+    0x21044643, 0xf01e4620, 0xb003fb44, 0x46204633, 0xe8bd2203, 0x21084ff0, 0xbb3bf01e, 0xf203c104, 
+    0xf203c904, 0xf203d104, 0xf203d904, 0xf203c618, 0xf203ce18, 0xf203d618, 0xf203de18, 0xf203c208, 
+    0xf203ca08, 0xf203d208, 0xf203da08, 0xb283b570, 0x48fb4604, 0x21802207, 0xfb1bf01e, 0x48f9b2a3, 
+    0x21802207, 0xfb15f01e, 0x48f7b2a3, 0x21802207, 0xfb0ff01e, 0x48f5b2a3, 0x21802207, 0xfb09f01e, 
+    0xf24048ef, 0xb2a34500, 0x220a4629, 0xf01e1c80, 0x48ecfb00, 0x220ab2a3, 0x1c804629, 0xfaf9f01e, 
+    0xb2a348e9, 0x4629220a, 0xf01e1c80, 0xb2a3faf2, 0x462948e6, 0x4070e8bd, 0x1c80220a, 0xbae9f01e, 
+    0x41f0e92d, 0x22054cde, 0x46802120, 0x46031ea4, 0xf01e4620, 0x4ddbfade, 0x21202205, 0x1ead4643, 
+    0xf01e4628, 0x4ed8fad6, 0x21202205, 0x1eb64643, 0xf01e4630, 0x4fd5face, 0x21202205, 0x1ebf4643, 
+    0xf01e4638, 0x2204fac6, 0x21104643, 0xf01e4620, 0x2204fac0, 0x21104643, 0xf01e4628, 0x2204faba, 
+    0x21104643, 0xf01e4630, 0x2204fab4, 0x21104643, 0xf01e4638, 0xe8bdfaae, 0x210041f0, 0x1000f240, 
+    0xbf2af7fb, 0x41f0e92d, 0x22064cbd, 0x46802140, 0x46031ca4, 0xf01e4620, 0x4dbafa9c, 0x21402206, 
+    0x1cad4643, 0xf01e4628, 0x4eb7fa94, 0x21402206, 0x1cb64643, 0xf01e4630, 0x4fb4fa8c, 0x21402206, 
+    0x1cbf4643, 0xf01e4638, 0x2205fa84, 0x21204643, 0xf01e4620, 0x2205fa7e, 0x21204643, 0xf01e4628, 
+    0x2205fa78, 0x21204643, 0xf01e4630, 0x2205fa72, 0x21204643, 0xf01e4638, 0xe8bdfa6c, 0x210041f0, 
+    0x0000f241, 0xbee8f7fb, 0x2204b510, 0x21304604, 0x489f4603, 0xfa5df01e, 0x2204489e, 0x46232130, 
+    0xfa57f01e, 0x2204489c, 0x46232130, 0xfa51f01e, 0x46232204, 0x4010e8bd, 0x21304898, 0xba49f01e, 
+    0x4605b570, 0x488e4603, 0x14c0f240, 0x46212206, 0xf01e387c, 0x488bfa3e, 0x462b2206, 0x387c4621, 
+    0xfa37f01e, 0x22064888, 0x4621462b, 0xf01e387c, 0x4886fa30, 0x4621462b, 0x4070e8bd, 0x387c2206, 
+    0xba27f01e, 0x5fffe92d, 0xf6414d7d, 0x46170400, 0x1fad4689, 0x220b4680, 0xe9dd4603, 0x4621ba0f, 
+    0xf01e4628, 0x2208fa16, 0x4628464b, 0x46310156, 0xfa0ff01e, 0x463b2207, 0x46282180, 0xfa09f01e, 
+    0x22059b03, 0x46282160, 0xfa03f01e, 0x22039b0e, 0x46282108, 0xf9fdf01e, 0x465b2202, 0x46282104, 
+    0xf9f7f01e, 0x46532200, 0x46282103, 0xf9f1f01e, 0x220b4d64, 0x46214643, 0x46281fad, 0xf9e9f01e, 
+    0x464b2208, 0x46284631, 0xf9e3f01e, 0x463b2207, 0x46282180, 0xf9ddf01e, 0x22059b03, 0x46282160, 
+    0xf9d7f01e, 0x22039b0e, 0x46282108, 0xf9d1f01e, 0x465b2202, 0x46282104, 0xf9cbf01e, 0x46532200, 
+    0x46282103, 0xf9c5f01e, 0x220b4d4f, 0x46214643, 0x46281fad, 0xf9bdf01e, 0x464b2208, 0x46284631, 
+    0xf9b7f01e, 0x463b2207, 0x46282180, 0xf9b1f01e, 0x22059b03, 0x46282160, 0xf9abf01e, 0x22039b0e, 
+    0x46282108, 0xf9a5f01e, 0x465b2202, 0x46282104, 0xf99ff01e, 0x46532200, 0x46282103, 0xf999f01e, 
+    0x4c3a4621, 0x4643220b, 0x46201fa4, 0xf991f01e, 0x464b2208, 0x46204631, 0xf98bf01e, 0x463b2207, 
+    0x46202180, 0xf985f01e, 0x22059b03, 0x46202160, 0xf97ff01e, 0x22039b0e, 0x46202108, 0xf979f01e, 
+    0x465b2202, 0x46202104, 0xf973f01e, 0x4653b004, 0x22004620, 0x5ff0e8bd, 0xf01e2103, 0xe92db96a, 
+    0x4d1f41f0, 0x0400f244, 0x460e220e, 0x46071d2d, 0x46214603, 0xf01e4628, 0x2206f95c, 0x21404633, 
+    0xf01e4628, 0x4d17f956, 0x463b220e, 0x1d2d4621, 0xf01e4628, 0x2206f94e, 0x21404633, 0xf01e4628, 
+    0x4d11f948, 0x463b220e, 0x1d2d4621, 0xf01e4628, 0x2206f940, 0x21404633, 0xf01e4628, 0x4621f93a, 
+    0x220e4c0a, 0x1d24463b, 0xf01e4620, 0x4633f932, 0xe8bd4620, 0x220641f0, 0xf01e2140, 0x0000b92a, 
+    0xf203c188, 0xf203c988, 0xf203d188, 0xf203d988, 0xf203c600, 0xf203ce00, 0xf203d600, 0xf203de00, 
+    0x43fee92d, 0x48ff4686, 0x468c2600, 0x0f03f1be, 0x46324637, 0xf8804633, 0x46b0e000, 0x463448fa, 
+    0x70014635, 0x46304631, 0xf1bed00f, 0xd00c0f05, 0x0f04f1be, 0xf1bed009, 0xd0390f02, 0x0f00f1be, 
+    0xf1bed036, 0xd0330f01, 0xf1bce038, 0xd00f0f01, 0x0f02f1bc, 0xf1bcd010, 0xd00f0f03, 0x0f04f1bc, 
+    0xf1bcd011, 0xd0140f05, 0x0f06f1bc, 0xe025d018, 0x23022201, 0xe0214690, 0xe7f92701, 0x20032601, 
+    0x463146b0, 0x2701e00a, 0x463b463a, 0x46384639, 0x2601e004, 0x46322002, 0x46314633, 0xe00d2401, 
+    0x22012602, 0x46134630, 0x46144611, 0xe0054615, 0x46372601, 0x46334632, 0x46304631, 0x8000f8cd, 
+    0x1001e9cd, 0x46304639, 0xfe8cf7ff, 0x4629b003, 0xe8bd4620, 0xe74243f0, 0x47f0e92d, 0xea252501, 
+    0x43950401, 0xd1702801, 0x8320f8df, 0xd04a2b00, 0x2b014ec7, 0x4fc7d052, 0xd05a2b02, 0x9318f8df, 
+    0xd0312b03, 0x46232205, 0x46402120, 0xf891f01e, 0x462b2206, 0x46402140, 0xf88bf01e, 0x3800f44f, 
+    0x46402100, 0xfd08f7fb, 0x46232205, 0x46302120, 0xf87ff01e, 0x462b2206, 0x46302140, 0xf879f01e, 
+    0x46402100, 0xfcf8f7fb, 0x46232205, 0x46382120, 0xf86ff01e, 0x462b2206, 0x46382140, 0xf869f01e, 
+    0x46402100, 0xfce8f7fb, 0x46232205, 0x464c2120, 0xf01e4648, 0x2206f85e, 0x2140462b, 0xe8bd4620, 
+    0xf01e47f0, 0x2205b856, 0x21204623, 0xf01e4640, 0x2206f850, 0x2140462b, 0xe7f04640, 0x46232205, 
+    0x46302120, 0xf845f01e, 0x462b2206, 0x46302140, 0x2205e7e5, 0x21204623, 0xf01e4638, 0x2206f83a, 
+    0x2140462b, 0xe7da4638, 0xe8bde7ff, 0xb51087f0, 0x46034604, 0x2200488d, 0x1c802103, 0xf829f01e, 
+    0x2200488b, 0x46232103, 0xf01e1c80, 0x4889f822, 0x21032200, 0x1c804623, 0xf81bf01e, 0x22004886, 
+    0x46232103, 0x4010e8bd, 0xf01e1c80, 0x2208b812, 0xb5704603, 0x46050154, 0x46214880, 0xf809f01e, 
+    0x2208487f, 0x4621462b, 0xf803f01e, 0x2208487d, 0x4621462b, 0xfffdf01d, 0x4621462b, 0x4070e8bd, 
+    0x22084879, 0xbff5f01d, 0xb283b510, 0x486f4604, 0x21042202, 0xf01d387e, 0x486dffec, 0x2202b2a3, 
+    0x387e2104, 0xffe5f01d, 0xb2a3486a, 0x21042202, 0xf01d387e, 0x4868ffde, 0x2202b2a3, 0xe8bd2104, 
+    0x387e4010, 0xbfd5f01d, 0x41f0e92d, 0x23004c63, 0x46072206, 0x21403c42, 0xf01d4620, 0x4d60ffca, 
+    0x22062300, 0x21403d42, 0xf01d4628, 0x4e5dffc2, 0x22062300, 0x21403e42, 0xf01d4630, 0xf8dfffba, 
+    0x23008168, 0xf1a82206, 0x21400842, 0xf01d4640, 0x2207ffb0, 0x2180463b, 0xf01d4620, 0x2207ffaa, 
+    0x2180463b, 0xf01d4628, 0x2207ffa4, 0x2180463b, 0xf01d4630, 0x2207ff9e, 0x2180463b, 0xf01d4640, 
+    0x2208ff98, 0x23004620, 0x46390157, 0xff91f01d, 0x46392301, 0x46202208, 0xff8bf01d, 0x46392300, 
+    0x46282208, 0xff85f01d, 0x46392301, 0x46282208, 0xff7ff01d, 0x46392300, 0x46302208, 0xff79f01d, 
+    0x46392301, 0x46302208, 0xff73f01d, 0x46392300, 0x46402208, 0xff6df01d, 0x46404639, 0x41f0e8bd, 
+    0x22082301, 0xbf65f01d, 0x47f0e92d, 0x4e2b4d2f, 0xf8df4f2b, 0x361c90b0, 0xa0acf8df, 0x7828371c, 
+    0x091cf109, 0x0a1cf10a, 0x7868b1a8, 0x78a8b3b8, 0x4650b3b0, 0xff30f01d, 0x0006f000, 0xd0632806, 
+    0x0800f04f, 0xf01d4650, 0xf000ff27, 0x28050005, 0x2400d00f, 0x4630e00e, 0xff1ef01d, 0x0006f000, 
+    0xd0032806, 0x0800f04f, 0xe7ec4630, 0x0801f04f, 0x2401e7fa, 0xea447828, 0x28010408, 0x7868d047, 
+    0xd0512801, 0x280178a8, 0x4656d060, 0xf01d4650, 0xf000ff03, 0x28060006, 0x2500d05b, 0xe017e039, 
+    0x0000e024, 0x0004034a, 0x0004034b, 0xf203c18a, 0xf203c98a, 0xf203d18a, 0xf203d98a, 0xf203c642, 
+    0xf203ce42, 0xf203d642, 0xf203de42, 0x00040578, 0xf01d4638, 0xf000fee1, 0x28060006, 0xf04fd003, 
+    0x46380800, 0xf04fe7af, 0xe7fa0801, 0xf01d4648, 0xf000fed3, 0x28060006, 0xf04fd003, 0x46480800, 
+    0xf04fe7a1, 0xe7fa0801, 0x0801f04f, 0x4630e79a, 0x4630e7bd, 0x2001e011, 0x2000e000, 0x44204328, 
+    0xdb182802, 0xe6a02001, 0xf01d4638, 0xf000feb5, 0x28060006, 0x2500d008, 0xf01d4638, 0xf000fead, 
+    0x28050005, 0xe7e6d1e9, 0xe7f52501, 0x4648464e, 0x2501e79d, 0x2000e7dd, 0xb510e687, 0x46042207, 
+    0x46032180, 0xf01d480b, 0x480bfeb4, 0x21802207, 0xf01d4623, 0x4809feae, 0x21802207, 0xf01d4623, 
+    0x2207fea8, 0xe8bd4623, 0x48054010, 0xf01d2180, 0x0000bea0, 0xf203c186, 0xf203c986, 0xf203d186, 
+    0xf203d986, 0x5ff0e92d, 0x20004683, 0xf90df7ff, 0x23034cff, 0x21702204, 0xf01d4620, 0x4dfdfe8a, 
+    0x22042303, 0x46282170, 0xfe83f01d, 0x23034efa, 0x21702204, 0xf01d4630, 0x4ff8fe7c, 0x22042303, 
+    0x46382170, 0xfe75f01d, 0x46202304, 0x210e2201, 0xfe6ff01d, 0x46282304, 0x210e2201, 0xfe69f01d, 
+    0x46302304, 0x210e2201, 0xfe63f01d, 0x46382304, 0x210e2201, 0xfe5df01d, 0x23014de9, 0x21402206, 
+    0xf01d4628, 0x2208fe56, 0x23004628, 0x46210154, 0xfe4ff01d, 0x23004de3, 0x00612209, 0xf01d4628, 
+    0x2300fe48, 0x22084621, 0xf01d4628, 0x2300fe42, 0x22074628, 0xf01d2180, 0x2300fe3c, 0x22064628, 
+    0xf01d2140, 0x4ed8fe36, 0x22072300, 0x46302180, 0xfe2ff01d, 0x46212300, 0x46302208, 0xfe29f01d, 
+    0x46302301, 0x21402206, 0xfe23f01d, 0x46302301, 0x21082203, 0xfe1df01d, 0x46302300, 0x21022201, 
+    0xfe17f01d, 0x23014ec6, 0x46192200, 0x46303e0e, 0xfe0ff01d, 0x9308f8df, 0x220f2301, 0xf1a903df, 
+    0x46390902, 0xf01d4648, 0xf8dffe04, 0x2301a300, 0x46212208, 0xf01d4650, 0x2300fdfc, 0x22034650, 
+    0xf01d2108, 0x2301fdf6, 0x22034630, 0xf01d2108, 0xf1a9fdf0, 0x210f0804, 0xf01d4640, 0x2002fdd0, 
+    0xfdb5f7ff, 0xf7ff2001, 0x2301f803, 0x22054628, 0xf01d2120, 0x2301fdde, 0x22044628, 0xf01d2110, 
+    0x2301fdd8, 0x22034628, 0xf01d2108, 0x2301fdd2, 0x22024628, 0xf01d2104, 0x2100fdcc, 0xf01d4640, 
+    0x2300fdae, 0x22034630, 0xf01d2108, 0x2300fdc2, 0x220f4639, 0xf01d4648, 0x2300fdbc, 0x21014630, 
+    0xf01d461a, 0x2301fdb6, 0x22074628, 0xf01d2180, 0x2301fdb0, 0x22064628, 0xf01d2140, 0x2300fdaa, 
+    0x22084621, 0xf01d4650, 0x4891fda4, 0x46587801, 0xfc86f7ff, 0xf7ff2000, 0x488cfd8a, 0x5468f64a, 
+    0x30084621, 0xfd7bf01d, 0x46214888, 0xf01d300a, 0x4886fd76, 0x300c2100, 0xfd71f01d, 0xf00c2004, 
+    0x2100fad0, 0xf00d2001, 0x4650f8e5, 0x5ff0e8bd, 0x22032301, 0xf01d2108, 0xe92dbd7c, 0x46045ff0, 
+    0xf7fe2000, 0x2c04fff2, 0x2c05d005, 0x2200d003, 0x46112005, 0x4877e008, 0x28017800, 0x2c05d101, 
+    0x2100d07e, 0x4608220b, 0xf904f7ff, 0x23004d6c, 0x21402206, 0xf01d4628, 0xf240fd5c, 0x46281b00, 
+    0x46592301, 0xf01d2208, 0xf8dffd54, 0xf240a198, 0x23002500, 0x22094629, 0xf01d4650, 0x2300fd4a, 
+    0x22084659, 0xf01d4650, 0x2300fd44, 0x22074650, 0xf01d2180, 0x2300fd3e, 0x22064650, 0xf01d2140, 
+    0x4e59fd38, 0x22072300, 0x46302180, 0xfd31f01d, 0x46592300, 0x46302208, 0xfd2bf01d, 0x46302300, 
+    0x21402206, 0xfd25f01d, 0x46302300, 0x21082203, 0xfd1ff01d, 0x46302300, 0x21022201, 0xfd19f01d, 
+    0x23014e47, 0x46192200, 0x46303e0e, 0xfd11f01d, 0x910cf8df, 0x0800f248, 0x46412301, 0x0902f1a9, 
+    0x4648220f, 0xfd05f01d, 0x0704f1a9, 0x4638210f, 0xfce5f01d, 0xf7ff2000, 0x2000fcca, 0xff18f7fe, 
+    0x46502300, 0x21202205, 0xfcf3f01d, 0x46502300, 0x21102204, 0xfcedf01d, 0x22032300, 0xe0002108, 
+    0x4650e02e, 0xfce5f01d, 0x46502300, 0x21042202, 0xfcdff01d, 0x46382100, 0xfcc1f01d, 0x46412300, 
+    0x4648220f, 0xfcd5f01d, 0x46302300, 0x461a2101, 0xfccff01d, 0x46292301, 0x46502209, 0xfcc9f01d, 
+    0x46592301, 0x46502208, 0xfcc3f01d, 0x78014820, 0xf7ff4620, 0xe8bdfba5, 0x20015ff0, 0xbca7f7ff, 
+    0x2105220b, 0xe74f2006, 0x43f8e92d, 0x23004f1a, 0x46042204, 0x463821f0, 0xfcabf01d, 0x7900f640, 
+    0x23004638, 0x22084649, 0xfca3f01d, 0xd03f2c03, 0xd03d2c04, 0xd03b2c05, 0x2c022500, 0x2c01d04d, 
+    0x2c06d04b, 0x2c07d07e, 0x2c08d07d, 0xe015d07c, 0xf203c602, 0xf203ce02, 0xf203d602, 0xf203de02, 
+    0xf23c830e, 0xf23c804a, 0xf2034228, 0xf2039000, 0x0004033c, 0x000402fa, 0xf203e82c, 0xf7fe2000, 
+    0xb2e0ffa0, 0xfddef7ff, 0x23042101, 0x22004608, 0xfbc2f7ff, 0x780048fe, 0xd0762801, 0x200a2104, 
+    0xffc8f00f, 0x95002300, 0x46192201, 0xe0fc4618, 0xf7ffb2e0, 0x2030fee2, 0xff83f7fe, 0x20062100, 
+    0xffb8f00f, 0x23042201, 0x46104611, 0xfba4f7ff, 0x43f8e8bd, 0xf7ff2001, 0x4eeebd90, 0x21022201, 
+    0xf01d4630, 0xf8dffc54, 0xb10883b0, 0xd1042c02, 0xf7ffb2e0, 0x2c02fda7, 0x2200d02b, 0x210f4640, 
+    0xfc45f01d, 0x0100f04f, 0x200ab3f0, 0xff92f00f, 0x95002300, 0x46192201, 0xf00f4610, 0x2102fee1, 
+    0xf7ff2001, 0x2300fb0d, 0x210148dc, 0xf01d461a, 0x2001fc20, 0xfd6cf7fe, 0x46302201, 0xf01d2102, 
+    0xe002fc26, 0xe056e049, 0xb358e072, 0xd0292c02, 0x2200e02e, 0x210f4640, 0xfc19f01d, 0x2308b1e0, 
+    0x21f02204, 0xf01d4638, 0x2100fc04, 0xf00f2002, 0x2300ff61, 0x22029500, 0x21014618, 0xfeb0f00f, 
+    0x780148c7, 0xe0012002, 0xe07fe00a, 0xfad8f7ff, 0xf7fe2010, 0xe7c6ff16, 0x46492307, 0xe7e12208, 
+    0xe7b32006, 0x23042201, 0x46104611, 0xfb34f7ff, 0x46302201, 0xf01d2102, 0x2801fbea, 0x2202d006, 
+    0x21044630, 0xfbe3f01d, 0xd17d2801, 0xf7ff2000, 0x2200fd14, 0x46112001, 0x2200e06f, 0x46112304, 
+    0xf7ff2001, 0x2004fb19, 0xfc86f7fe, 0x43f8e8bd, 0xf7fe2001, 0x4ca8be3a, 0x22072301, 0x21803cb8, 
+    0xf01d4620, 0x2301fbb6, 0x22094620, 0xf01d0259, 0x2208fbb0, 0x23014620, 0xf01d0151, 0x2300fbaa, 
+    0x22044620, 0xf01d2110, 0x2304fba4, 0xe01a2200, 0x78204c9c, 0xfe21f7ff, 0xf7fe2030, 0x2100fec2, 
+    0xf00f2006, 0x4898fef7, 0xb19b7803, 0x21009500, 0x20007822, 0xfe44f00f, 0xf04f4894, 0x78000304, 
+    0xd0102803, 0x21012201, 0x2001b001, 0x43f0e8bd, 0xbad2f7ff, 0x462b488e, 0x95007800, 0xd1e62801, 
+    0x21017822, 0x2200e7e5, 0xe7ed4611, 0x46082100, 0xfed0f00f, 0xf04f4887, 0xf04f0201, 0x46110300, 
+    0x95007800, 0xd00c2803, 0xf00f2001, 0x2000fe19, 0xfca3f7ff, 0x46112200, 0xe8bd4610, 0xf7fe43f8, 
+    0x2002be23, 0xe7ffe7f1, 0x83f8e8bd, 0xf04f2109, 0xf44f422b, 0xb5102000, 0xffbbf7f3, 0xf2402001, 
+    0xf7f311f4, 0x4874ff68, 0x20017801, 0xff52f7f3, 0x20014972, 0xff4ef7f3, 0x23004871, 0xf2402208, 
+    0xf01d3100, 0x496ffb36, 0x4a6f2000, 0x808880c8, 0x80088048, 0x496d4864, 0x486a7803, 0xf878f7fd, 
+    0xf44f2172, 0xf7f30080, 0x2000ff6e, 0xfcacf7fe, 0x48672300, 0x461a210f, 0xfb1bf01d, 0xf7fe2000, 
+    0x2004fc83, 0xfc1bf7fe, 0xf7fe2001, 0x2100fc61, 0xf7fa2040, 0xe8bdff91, 0x20004010, 0xbc58f7fe, 
+    0xf64b484d, 0xb5f831b5, 0xf01d3848, 0x2301fae8, 0x220e4858, 0x4621039c, 0xfafbf01d, 0x23014846, 
+    0x46192200, 0xf01d38b8, 0x2200faf4, 0x46112304, 0xf7ff2001, 0xf7fffa41, 0xf46fff99, 0xf647607f, 
+    0xf2470395, 0xf6400202, 0x90000102, 0x1045f243, 0xfabaf7fe, 0x21004848, 0xfac1f01d, 0x4a384839, 
+    0x78117800, 0xf9bcf7ff, 0xf7fe2003, 0x2007fd2e, 0xfe67f00c, 0xf7fe2001, 0xf00bfd66, 0x2001ffd7, 
+    0xffa4f7fe, 0xf7ff2001, 0x2001facf, 0xfc05f7ff, 0xf7fe2001, 0x2000ffd5, 0xf814f7ff, 0xf7ff2001, 
+    0x2000f811, 0xf80ef7ff, 0xf7fe2000, 0x00e6ffc9, 0x15f4f240, 0x46304629, 0xfecdf7f3, 0x7100f241, 
+    0xf7f34630, 0x4f25feb7, 0x46394630, 0xfeb2f7f3, 0xf7ff2003, 0x2005fde9, 0xfe1cf7fe, 0xf7ff2000, 
+    0x2001f84f, 0xfc39f00d, 0xf7ff2000, 0x2003fddd, 0xfe10f7fe, 0xf7ff2007, 0x4629f843, 0xf7f34630, 
+    0xf241feaa, 0x46307101, 0xfe94f7f3, 0x46304639, 0xfe90f7f3, 0x23004816, 0x4621220e, 0xf01d1d80, 
+    0x4813fa78, 0x220a2300, 0x30081121, 0xe025b001, 0x00040544, 0xf38f007c, 0xf23c8102, 0xf20305cc, 
+    0x0004033c, 0x0004028a, 0x000405d9, 0x0004027c, 0x0004053e, 0x00040545, 0x0004055c, 0xdcba01f5, 
+    0xf2035022, 0x00040590, 0x00040578, 0x000405a6, 0xf203e804, 0xf23c830c, 0xf2034224, 0x40f0e8bd, 
+    0xba47f01d, 0x4c1db570, 0x21012300, 0x4620461a, 0xfa3ff01d, 0xf01d1fa0, 0x1ea5fa1f, 0x46282302, 
+    0x21072200, 0xfa35f01d, 0x46282302, 0x21702204, 0xfa2ff01d, 0xf2402302, 0x22087100, 0xf01d4628, 
+    0x2302fa28, 0x0100f247, 0x4628220c, 0xfa21f01d, 0x1f202100, 0xfa03f01d, 0x46202301, 0x46192200, 
+    0xfa17f01d, 0xf7fe2001, 0x2100fb63, 0xf7fa2040, 0xe8bdfe93, 0x20004070, 0xbb5af7fe, 0xf20305cc, 
+    0x41f0e92d, 0x461d4c4e, 0x4616b283, 0x460f2206, 0x462021c0, 0xf9fdf01d, 0x4620b2bb, 0x21302204, 
+    0xf9f7f01d, 0x4620b2b3, 0x210c2202, 0xf9f1f01d, 0x4620b2ab, 0x41f0e8bd, 0x21032200, 0xb9e9f01d, 
+    0x41f0e92d, 0x46144698, 0x460e2301, 0x46072102, 0x461a483c, 0xf9ddf01d, 0xf2412100, 0xf7fa0000, 
+    0x4d39fe5b, 0x220a2301, 0x46280299, 0xf9d1f01d, 0x463b2204, 0x11f0f240, 0xf01d4628, 0x2201f9ca, 
+    0x21024633, 0xf01d4628, 0x1d2ff9c4, 0x0100f640, 0x0600f24c, 0x2c01b134, 0x2c02d006, 0x2c03d004, 
+    0xe013d009, 0xe0002300, 0x46282301, 0xf01d220b, 0x2300f9b0, 0x2300e005, 0x220b4628, 0xf9a9f01d, 
+    0x46312301, 0x4638220e, 0xf9a3f01d, 0x4643220f, 0x0100f248, 0xf01d4628, 0x4628f99c, 0x41f0e8bd, 
+    0x22022301, 0xf01d2104, 0x4817b994, 0xb5102100, 0xf01d3016, 0x4814f974, 0x30182100, 0xf96ff01d, 
+    0x21004811, 0xf01d3012, 0x480ff96a, 0x30142100, 0xf965f01d, 0x2100480c, 0xf01d301a, 0x480af960, 
+    0x301c2100, 0xf95bf01d, 0x21004807, 0xf01d301e, 0x4805f956, 0xe8bd2100, 0x30204010, 0xb94ff01d, 
+    0xf2030484, 0xf23c8310, 0xf2036100, 0x2801b158, 0x2802d00f, 0x2803d013, 0x2301d117, 0x2102489f, 
+    0xf01d461a, 0x489db956, 0x21022301, 0x3860461a, 0x489ae7f7, 0x21022301, 0x3840461a, 0x4897e7f1, 
+    0x21022301, 0x3820461a, 0x4770e7eb, 0x4c93b510, 0x22002301, 0x3ce04619, 0xf01d4620, 0x2301f93a, 
+    0x21024620, 0xf01d461a, 0x2301f934, 0x22024620, 0xf01d2104, 0x2301f92e, 0x22034620, 0x4010e8bd, 
+    0xf01d2108, 0xb283b926, 0x22064884, 0x38de21c0, 0xb91ff01d, 0x2801b158, 0x2802d00f, 0x2803d013, 
+    0x2301d117, 0x2200487d, 0xf01d4619, 0x487bb912, 0x22002301, 0x38604619, 0x4878e7f7, 0x22002301, 
+    0x38404619, 0x4875e7f1, 0x22002301, 0x38204619, 0x4770e7eb, 0xf240b570, 0x461436ff, 0xb1a81c75, 
+    0xd0192801, 0xd01d2802, 0xd1212803, 0x4631b28b, 0x22004e6a, 0x4630360e, 0xf8ebf01d, 0x4629b2a3, 
+    0xe8bd4630, 0x220a4070, 0xb8e3f01d, 0x4631b28b, 0x22004e62, 0xe7ee3e52, 0x4631b28b, 0x22004e5f, 
+    0xe7e83e32, 0x4631b28b, 0x22004e5c, 0xe7e23e12, 0xb283bd70, 0x22004859, 0x38802103, 0xb8c9f01d, 
+    0x4856b283, 0x2200b510, 0x38d8460c, 0x71fff647, 0xf8bff01d, 0xb2a14851, 0x4010e8bd, 0xf01d38d6, 
+    0xb570b89e, 0x23014d4d, 0x03dc220f, 0x46213de0, 0xf01d4628, 0x4621f8ae, 0xe8bd4628, 0x23004070, 
+    0xf01d220f, 0xe92db8a6, 0x461f41f0, 0x48434603, 0x9e064614, 0x387c2209, 0xf240460d, 0xf01d2100, 
+    0x483ef898, 0x21802207, 0x385e462b, 0xf891f01d, 0x2207483a, 0x46232180, 0xf01d383e, 0x4837f88a, 
+    0x21802207, 0x381e463b, 0xf883f01d, 0x48334633, 0x41f0e8bd, 0x21802207, 0xf01d1c80, 0xb430b87a, 
+    0x0400f64f, 0x2801b168, 0x2802d011, 0x2803d015, 0x482ad119, 0x460b220b, 0x300e4621, 0xf01dbc30, 
+    0x4826b868, 0x460b220b, 0x38524621, 0x4823e7f6, 0x460b220b, 0x38324621, 0x4820e7f0, 0x460b220b, 
+    0x38124621, 0xbc30e7ea, 0xb5104770, 0x4604b283, 0x2200481b, 0xf01d2101, 0xb2a3f84c, 0x22004819, 
+    0xf01d2101, 0xb2a3f846, 0x22004817, 0xf01d2101, 0xb2a3f840, 0x22004815, 0x4010e8bd, 0xf01d2101, 
+    0xb158b838, 0xd00e2801, 0xd0112802, 0xd1142803, 0x480eb28b, 0x21062201, 0xb82bf01d, 0x4808b28b, 
+    0x21062201, 0xb28be7f8, 0x22014806, 0xe7f32106, 0x4805b28b, 0x21062201, 0x4770e7ee, 0xf20308e0, 
+    0xf203c604, 0xf203ce04, 0xf203d604, 0xf203de04, 0x2100b51c, 0x91019100, 0x1010f82d, 0x1000f8bd, 
+    0xf01c48fe, 0x48fdffec, 0x1002f8bd, 0xf01c3020, 0x48faffe6, 0x1004f8bd, 0xf01c3040, 0x48f7ffe0, 
+    0x1006f8bd, 0xf01c3060, 0xbd1cffda, 0x220448f4, 0x4cf2b510, 0xf9902130, 0x3c740000, 0x4620b283, 
+    0xffe7f01c, 0x46202304, 0x210f2200, 0xffe1f01c, 0x46202301, 0x21402206, 0xffdbf01c, 0xf01c1ca0, 
+    0x4604ffbb, 0x387048e5, 0xffb6f01c, 0x4000eb04, 0xbd101040, 0xb50848e3, 0xf2447801, 0xf7fa0000, 
+    0x48defc4b, 0x01c9f640, 0xf01c387e, 0x48dbffa8, 0x1101f241, 0xf01c387c, 0x2000ffa2, 0xfe9af7ff, 
+    0xf7ff2001, 0x2002fe97, 0xfe94f7ff, 0xf7ff2003, 0x48d2fe91, 0x22062301, 0xf01c2140, 0x48cfffaa, 
+    0x22062301, 0x30202140, 0xffa3f01c, 0x230148cb, 0x21402206, 0xf01c3040, 0x48c8ff9c, 0x22062301, 
+    0x30602140, 0xff95f01c, 0x90002001, 0x46024603, 0xf7ff4601, 0xbd08fee8, 0xd0102804, 0x40822201, 
+    0x000ff082, 0x2901b200, 0xea40d00b, 0xb2001000, 0x48bab283, 0x21ff2200, 0xf01c3882, 0x20ffbf7a, 
+    0x2102e7f6, 0x1000eb01, 0x000ff040, 0xb570e7ef, 0x3400f44f, 0x0102f640, 0xf7f34620, 0x48affb8c, 
+    0xf01c1d00, 0x4605ff49, 0x1c8048ac, 0xff44f01c, 0x4100eb05, 0xf7f34620, 0x48a8fb6d, 0xf01c3024, 
+    0x4605ff3b, 0x302248a5, 0xff36f01c, 0x4100eb05, 0xf7f34620, 0x48a1fb5f, 0xf01c3044, 0x4605ff2d, 
+    0x3042489e, 0xff28f01c, 0x4100eb05, 0xf7f34620, 0x489afb51, 0xf01c3064, 0x4605ff1f, 0x30624897, 
+    0xff1af01c, 0x4100eb05, 0xf7f34620, 0x4894fb43, 0xf9902100, 0xe8bd0000, 0xe79d4070, 0x41f0e92d, 
+    0x498e000c, 0x1040eb01, 0xd4014680, 0xe0002731, 0x22062711, 0xf01c2140, 0x2c00ff2a, 0xda00b246, 
+    0x48894264, 0xf990b224, 0x28040000, 0x2805d002, 0xe003d002, 0xe00000a0, 0xb2040060, 0x21004640, 
+    0xfeedf01c, 0xe0052500, 0x46404639, 0xfee7f01c, 0xb22d1c6d, 0xdbf742a5, 0x4640b2b3, 0x41f0e8bd, 
+    0x21402206, 0xbef5f01c, 0x4d74b570, 0x1cac3d7e, 0x2801b120, 0x2802d00a, 0xe02ad10f, 0x46282306, 
+    0x21f02204, 0xfee5f01c, 0xe0012303, 0xe0212307, 0x46202204, 0xf01c2170, 0x2305fedc, 0x22044628, 
+    0xf01c21f0, 0x2302fed6, 0x22044620, 0xf01c2170, 0x2305fed0, 0x0100f24f, 0x4628220c, 0xfec9f01c, 
+    0xf2474620, 0xe8bd0100, 0x23024070, 0xf01c220c, 0x2308bec0, 0x22044628, 0xf01c21f0, 0x2302feba, 
+    0x4601e7d6, 0xb5704855, 0xf242387e, 0x1c854424, 0x3613f241, 0xf2472908, 0xd22b4287, 0xf001e8df, 
+    0x160a0704, 0x1f181610, 0x2163f245, 0xf247e00a, 0xe0014185, 0x7187f247, 0xfe81f01c, 0xe0144631, 
+    0x418cf240, 0xfe7bf01c, 0xe00e4621, 0xe7f34611, 0x61a7f249, 0xfe73f01c, 0x2102f240, 0xf64be005, 
+    0xf01c01c9, 0xf240fe6c, 0x46281101, 0x4070e8bd, 0xbe65f01c, 0xb570bd70, 0x22004c38, 0x4605210f, 
+    0x46203c7e, 0xfe83f01c, 0xb2401b40, 0xdd01280f, 0xe002200f, 0xda002800, 0xb2832000, 0xe8bd4620, 
+    0x22004070, 0xf01c210f, 0xb430be64, 0xb1419902, 0x2408f245, 0x1aa42100, 0xda094199, 0x0109f06f, 
+    0x2b00e02d, 0x2101da01, 0xf04fe029, 0xe02631ff, 0x0100f244, 0xf1731a51, 0xdb020100, 0x0103f06f, 
+    0xf242e01d, 0x1b140400, 0x0400f173, 0x0101f06f, 0x2b00da15, 0x030cda13, 0x1aa41049, 0xdb044199, 
+    0x13a14c1a, 0x41991aa4, 0x2102da01, 0x4c18e007, 0x1aa213e1, 0xda014199, 0xe0002104, 0xbc30210a, 
+    0xf7ffb2c9, 0x480dbdac, 0x22082307, 0x7100f640, 0xb510387e, 0xfe1df01c, 0x23014808, 0x46192200, 
+    0xf01c1e80, 0x4805fe16, 0x22002301, 0x301e4619, 0xfe0ff01c, 0x22002301, 0xe00b4619, 0xf2030882, 
+    0x00040290, 0x0004028b, 0x0004028a, 0xffffc000, 0xffffadf8, 0x303e484b, 0xfdfbf01c, 0x23014849, 
+    0x46192200, 0x4010e8bd, 0xf01c305e, 0xb570bdf2, 0xf6404605, 0xf44f0103, 0xf7f33000, 0xf7fffa0c, 
+    0x4c41fca5, 0x46082100, 0x2000f994, 0xfbf6f7fc, 0xfdecf7ff, 0x7025b201, 0x46101402, 0xfd10f7ff, 
+    0x0000f994, 0xfc72f7ff, 0x0000f994, 0xfcb2f7ff, 0x0000f994, 0xfcfdf7ff, 0x20012100, 0xfe31f7fc, 
+    0x2000f994, 0x200c2100, 0xfb92f7fc, 0xf9942101, 0x46082000, 0xfbd2f7fc, 0x4070e8bd, 0xe92de647, 
+    0x46824ff8, 0xf8df4829, 0x250090a8, 0x462a46e8, 0xf8906800, 0xf88d1052, 0xf8901000, 0xf88d1054, 
+    0xf8901001, 0xf88d0056, 0xf9990002, 0xeb0d1000, 0x21ff0001, 0x3c03f810, 0x381c481a, 0xfd99f01c, 
+    0x26102704, 0x0f00f1ba, 0x2400d023, 0xfd9ef7ff, 0x1c644138, 0x42b4b2e4, 0xd3f74405, 0x3080f44f, 
+    0xf7f34629, 0xf999f997, 0x12682000, 0x0102eb08, 0xf8112200, 0x43481c03, 0x7809490e, 0x0115f1c1, 
+    0xf2404108, 0xf3c031ff, 0x48060309, 0xf01c381a, 0x4804fd70, 0x21042202, 0x38224653, 0xfd69f01c, 
+    0x8ff8e8bd, 0xf2030882, 0x00040290, 0x000405f8, 0x0004028a, 0x0004028b, 0x4cb4b510, 0x4620b281, 
+    0xfd3df01c, 0x46202100, 0xfd39f01c, 0xf64f4caf, 0x3c1071ff, 0xf01c4620, 0x4620fd32, 0x4010e8bd, 
+    0xf01c2100, 0xf04fbd2c, 0xb51030ff, 0xffe4f7ff, 0xf01c48a7, 0xe8bdfd1b, 0x20044010, 0xba87f7fa, 
+    0x9c02b510, 0x70427001, 0x70c47083, 0xb570bd10, 0x24004da0, 0x0600f647, 0x4631230f, 0xeb05220b, 
+    0xf01c0044, 0x1c64fd26, 0xdbf52c04, 0xb570bd70, 0x24004d98, 0x0600f647, 0x46312300, 0xeb05220b, 
+    0xf01c0044, 0x1c64fd16, 0xdbf52c04, 0xe92dbd70, 0x4f9141f0, 0x46052400, 0x1600f240, 0x0804f107, 
+    0x3044eb06, 0x4638b281, 0xfce9f01c, 0xf01c4640, 0xf825fce3, 0x1c640014, 0xdbf12c04, 0x81f0e8bd, 
+    0x41f0e92d, 0x24004e83, 0x070ef06f, 0x36104605, 0x0044eb06, 0xfcd0f01c, 0xfd26f01e, 0xf01f463a, 
+    0xeb05fb9a, 0x1c6402c4, 0xe9c22c04, 0xdbef0100, 0xb510e7e4, 0x46204c79, 0xfcbef01c, 0xf01c4620, 
+    0xf010fcbb, 0xd0000020, 0xbd102001, 0x220d4874, 0x0100f242, 0xf01cb510, 0x2800fcda, 0x2001d000, 
+    0xe92dbd10, 0xf24441f0, 0x460c0600, 0x4607220e, 0x486c4603, 0xf01c4631, 0x4866fcbc, 0x387e2100, 
+    0xfc9df01c, 0x4d674867, 0x3d443850, 0xd00e2c02, 0xd0132c01, 0x22002300, 0xf01c2101, 0x463bfcaa, 
+    0x46284631, 0x41f0e8bd, 0xf01c220e, 0x2200bca2, 0x2101463b, 0xfc9df01c, 0xe7f12300, 0xe7ea463b, 
+    0x41f0e92d, 0x461f4c57, 0x460e4615, 0x46033422, 0x46202200, 0xf01c2103, 0x2202fc8c, 0x210c4633, 
+    0xf01c4620, 0x2204fc86, 0x2130462b, 0xf01c4620, 0x2206fc80, 0x21c0463b, 0xf01c4620, 0x4620fc7a, 
+    0x41f0e8bd, 0x23012208, 0xf01c0151, 0xb570bc72, 0x22004d44, 0x35222103, 0xf01c4628, 0x2202fc78, 
+    0x210c4604, 0xf01c4628, 0xea44fc72, 0x46280480, 0x21302204, 0xfc6bf01c, 0x1400ea44, 0x22064628, 
+    0xf01c21c0, 0xea44fc64, 0xb2801080, 0xb570bd70, 0x4604460d, 0x46114834, 0xfc31f01c, 0x46294832, 
+    0xf01c1e80, 0x4830fc2c, 0xe8bd4621, 0x1f004070, 0xbc25f01c, 0xe9ddb5f0, 0xe9dd5408, 0xf8dd7606, 
+    0xb109c014, 0x0002f040, 0xf040b10a, 0xb10b0001, 0x0008f040, 0x0f00f1bc, 0xf040d001, 0xb10f0004, 
+    0x0010f040, 0xf040b10d, 0xb10e0020, 0x0040f040, 0xd0012c00, 0x0080f040, 0xb510bdf0, 0x28012403, 
+    0x2803d002, 0xe018d00b, 0x22024818, 0xf01c213c, 0xb2c0fc1e, 0xd00d2806, 0xd00d2807, 0x4814e00d, 
+    0x213c2202, 0xfc13f01c, 0x2807b2c0, 0x2808d002, 0xe002d002, 0xe0002404, 0x46202405, 0x2200bd10, 
+    0x480c4603, 0xf01c2107, 0x0000bbf4, 0xf203902a, 0xf0001144, 0xf38f2200, 0xf38f2360, 0xf3cfffc2, 
+    0xf38fffd4, 0xf38f2050, 0xf38e0030, 0xf2020000, 0xf2060000, 0xf2070000, 0x220c2301, 0x0319b570, 
+    0x46204cfe, 0xfbd5f01c, 0x46202301, 0x21402206, 0xfbcff01c, 0x46202300, 0x21202205, 0xfbc9f01c, 
+    0x46202300, 0x21102204, 0xfbc3f01c, 0x46202301, 0x21802207, 0xfbbdf01c, 0xf2442300, 0x220e0100, 
+    0xf01c4620, 0x2300fbb6, 0x22074620, 0xf01c2180, 0x4ceafbb0, 0x220a2300, 0x4100f240, 0x46203c10, 
+    0xfba7f01c, 0x46202208, 0x01512300, 0xfba1f01c, 0xf2404ee2, 0x230014c0, 0x1db64621, 0x46302206, 
+    0xfb97f01c, 0x46302306, 0x21382203, 0xfb91f01c, 0x46302306, 0x21072200, 0xfb8bf01c, 0x46212306, 
+    0x461a1cb5, 0xf01c4628, 0x2302fb84, 0x22094630, 0xf01c00e1, 0x1faefb7e, 0x46302302, 0x21072200, 
+    0xfb77f01c, 0x46282300, 0x461a2107, 0xfb71f01c, 0x46212306, 0x4630461a, 0xfb6bf01c, 0x4cc74621, 
+    0x3c0c2306, 0x4620461a, 0xfb63f01c, 0xe8bd4620, 0x23064070, 0x21072200, 0xbb5bf01c, 0x43f8e92d, 
+    0x92fcf8df, 0x49bf2500, 0x27032601, 0x0802f04f, 0x0000f899, 0x7080f440, 0x0000f8a9, 0x29017809, 
+    0xf3c0d038, 0x91001181, 0x0103f000, 0x1301f3c0, 0x0281f3c0, 0xf7ff48b4, 0xf365fe03, 0xf3660407, 
+    0xf368240f, 0xf3674417, 0xf899641f, 0xb0010000, 0xf3c00782, 0x0f520381, 0xf102fa04, 0x005b1222, 
+    0xf3c0409a, 0x43111301, 0x005b1422, 0x1081f3c0, 0x4311409a, 0x00401622, 0x43f0e8bd, 0x43114082, 
+    0x0003f001, 0x1381f3c1, 0x1201f3c1, 0x0181f3c1, 0xbe76f7ff, 0x0103f000, 0xf3c09100, 0xf3c00381, 
+    0xf3c01201, 0x48981181, 0xfdcaf7ff, 0x0407f367, 0x240ff368, 0x4417f366, 0x641ff365, 0xb538e7c5, 
+    0xd0042801, 0xb1282403, 0x8800488d, 0xf7ffb138, 0xe01dff95, 0x94002302, 0x21002201, 0x4889e015, 
+    0x28017800, 0x2303d006, 0x21012202, 0xf7ff2000, 0xe7effe47, 0x22012300, 0x20032102, 0xfe40f7ff, 
+    0x90002000, 0x22022301, 0x487f2103, 0xfd98f7ff, 0x4c7d487e, 0x1000f990, 0x70015c61, 0x3003f994, 
+    0x2002f994, 0x1001f994, 0x0000f994, 0xf8b8f7ff, 0x3003f994, 0x2002f994, 0x1001f994, 0x0000f994, 
+    0xfeeef7fb, 0x3003f994, 0x2002f994, 0x1001f994, 0x0000f994, 0xf897f7fd, 0x3003f994, 0x2002f994, 
+    0x1001f994, 0x0000f994, 0xf8cff010, 0xfe2ff7ff, 0x4038e8bd, 0x48664601, 0xba81f01c, 0x5ff0e92d, 
+    0x48634604, 0x31b8f64b, 0xf01c30a8, 0x4e61fa78, 0x220e2301, 0x46300399, 0xfa8bf01c, 0x23004d5e, 
+    0x21042202, 0xf01c4628, 0x485cfa84, 0x22032301, 0xf01c2108, 0x4f57fa7e, 0x22022301, 0x21043760, 
+    0xf01c4638, 0x4856fa76, 0x0800f241, 0x1900f240, 0x28988800, 0x2888d017, 0x28a8d015, 0x28b8d013, 
+    0x28c8d011, 0x2894d00f, 0x2884d02a, 0x28a4d028, 0x28b4d026, 0xb3ecd024, 0x46412301, 0x4628220c, 
+    0xfa57f01c, 0x2300e029, 0x220c4641, 0xf01c4628, 0x2300fa50, 0x22084649, 0xf01c4628, 0x2300fa4a, 
+    0x22014628, 0xf01c2102, 0x2300fa44, 0x22064628, 0xf01c2140, 0xb1ecfa3e, 0x22072301, 0xe01d2180, 
+    0x46412300, 0x4628220c, 0xfa33f01c, 0x46282300, 0x21022201, 0xfa2df01c, 0x2301b164, 0x22084649, 
+    0xf01c4628, 0x2301fa26, 0x22074628, 0xf01c2180, 0xe000fa20, 0x2301e00b, 0x21402206, 0xf01c4628, 
+    0x2301fa18, 0x22054628, 0xf01c2120, 0x4d22fa12, 0x220f2301, 0x03d93d20, 0xf01c4628, 0x2301fa0a, 
+    0x220c4644, 0x46284641, 0xfa03f01c, 0x46282300, 0x21402206, 0xf9fdf01c, 0x46282300, 0x21202205, 
+    0xf9f7f01c, 0x23004817, 0x21402206, 0xf9f1f01c, 0x4b00f240, 0x23004814, 0x220a4659, 0xf9e9f01c, 
+    0xf640480e, 0x23010a00, 0x220b4651, 0xf01c3820, 0x2002f9e0, 0xfee3f7ff, 0xe0172300, 0xf203902c, 
+    0x000402b8, 0x00040310, 0x00040578, 0x00040290, 0xf23c8012, 0xf38f0000, 0xf38e0040, 0xf38f2070, 
+    0x00040558, 0xf203507c, 0xf38fffc0, 0x220748ff, 0xf01c2180, 0x48fef9be, 0x20017801, 0xfcf1f7ff, 
+    0x83f0f8df, 0x22082301, 0x4649464d, 0xf01c4640, 0x2301f9b0, 0x22054640, 0xf01c2120, 0x2301f9aa, 
+    0x22044640, 0xf01c2110, 0x48f3f9a4, 0xf01c2100, 0x2301f986, 0x22004630, 0xf01c4619, 0x2301f99a, 
+    0x220c4621, 0xf01c4630, 0x2301f994, 0x220d4630, 0xf01c0359, 0x2300f98e, 0x22084629, 0xf01c4638, 
+    0x48e6f988, 0x11d4f240, 0xf969f01c, 0xf24048e3, 0x1c801129, 0xf963f01c, 0x46512301, 0x4638220b, 
+    0xf977f01c, 0x46592300, 0x4638220a, 0xf971f01c, 0x23014cda, 0x4651220b, 0x46203c40, 0xf969f01c, 
+    0x46592301, 0x4620220a, 0xf963f01c, 0x46202301, 0x461a2102, 0xf95df01c, 0x46202301, 0x46192200, 
+    0xf957f01c, 0x230048cb, 0x21302204, 0xf01c301c, 0xe8bdf950, 0x23015ff0, 0x220048c9, 0xf01c4619, 
+    0x4ac8b948, 0x2005210a, 0xf7f2b510, 0x2004fdb2, 0xfd6bf7f9, 0xf7f92002, 0x2002fd68, 0xf89ef00d, 
+    0x200249c1, 0x48c17008, 0xb9207800, 0x200422ff, 0xf7f44611, 0x48beff25, 0x22002301, 0xf01c210f, 
+    0x48b7f928, 0x2200230b, 0x385a210f, 0xf921f01c, 0x220248b2, 0x38282104, 0xf929f01c, 0xd1112801, 
+    0xf7fd2000, 0x4caefeb1, 0x220a2300, 0x4100f240, 0x46203c32, 0xf90df01c, 0x46202208, 0x01512301, 
+    0xf907f01c, 0x230148a3, 0x03d9220f, 0xf01c3818, 0x48a3f900, 0xe8bd2100, 0x38484010, 0xb8dff01c, 
+    0x41f0e92d, 0x210b4a9f, 0xf7f22005, 0x2004fd62, 0xfd1bf7f9, 0xf7f92002, 0x2001fd18, 0xf84ef00d, 
+    0x20014999, 0x46032200, 0x210f7008, 0xf01c4898, 0x4d93f8e0, 0x0400f241, 0x46212300, 0x220c3d50, 
+    0xf01c4628, 0x2303f8d6, 0x46191eae, 0x46302200, 0xf8cff01c, 0x46302301, 0x21042202, 0xf8c9f01c, 
+    0x46302301, 0x03df220f, 0xf01c4639, 0x2301f8c2, 0x220c4621, 0xf01c4628, 0x2300f8bc, 0x220c4621, 
+    0xf01c4628, 0x2300f8b6, 0x220f4639, 0xf01c4630, 0x2300f8b0, 0x21034630, 0xf01c461a, 0x2300f8aa, 
+    0x22024630, 0xf01c2104, 0x4870f8a4, 0x00a1220e, 0xf01c3026, 0x2800f8ac, 0xe8bdd003, 0xf00d41f0, 
+    0xe8bdb880, 0x497381f0, 0xb5102000, 0xf7ff7008, 0x4866fb6e, 0x220c2301, 0x302c0319, 0xf889f01c, 
+    0xf7fd2002, 0xf7fffe21, 0x4862fb3e, 0x30222100, 0xf865f01c, 0x23014c62, 0x3c32220a, 0x46200299, 
+    0xf877f01c, 0x46202301, 0x02592209, 0xf871f01c, 0x46202208, 0x01512301, 0xf86bf01c, 0xf81cf00d, 
+    0xff1ef7f3, 0x46082100, 0xfbc4f00b, 0x4a552109, 0x4010e8bd, 0xf7f22005, 0x4857bccc, 0x4d4eb570, 
+    0xb1087800, 0xe0002301, 0x46282300, 0x21082203, 0xf84ff01c, 0x78214c51, 0xd02d0788, 0xd5010708, 
+    0xd5010748, 0xe0002301, 0x46282300, 0x21022201, 0xf83ff01c, 0x07017820, 0x0740d401, 0x2301d401, 
+    0x2300e000, 0x22024628, 0xf01c2104, 0x7820f832, 0x0103f000, 0x30524835, 0xd9012901, 0xe0002301, 
+    0x22002300, 0xf01c2101, 0x483df824, 0x1d244c32, 0xb1617801, 0xe00b2301, 0x46282300, 0x21042202, 
+    0xf817f01c, 0x46282300, 0x21022201, 0x2300e7eb, 0x22004620, 0xf01c2101, 0x4932f80c, 0xb1097809, 
+    0xe0002301, 0x46202300, 0x21022201, 0xf801f01c, 0x22014d21, 0x3d382102, 0xf01c4628, 0x2206f808, 
+    0x21404604, 0xf01c4628, 0x4304f802, 0x22054628, 0xf01b2120, 0x4304fffc, 0xb2e34823, 0x22044c24, 
+    0x70032110, 0x70034821, 0xf01b4620, 0x2300ffe2, 0x22034620, 0xf01b2108, 0xe8bdffdc, 0x481d4070, 
+    0xf01b2100, 0x4a1cbfbc, 0x1100f3c0, 0xf3c07011, 0x4a1a11c0, 0x491a7011, 0x29017809, 0x4a19d14a, 
+    0x0180f3c0, 0xf3c07011, 0xe02d01c0, 0xf2039000, 0x00040369, 0xf38f2034, 0xf38e0078, 0xf38f00a4, 
+    0xf38f22d2, 0xcccc0000, 0x00040244, 0x00040285, 0xf23c8316, 0x0004034c, 0x000402bf, 0x000402c0, 
+    0x00040315, 0x00040316, 0x000405cc, 0x000405c0, 0xf2035256, 0xf23c8026, 0x000405ea, 0x00040317, 
+    0x000405d4, 0x000405db, 0x70114afe, 0x1140f3c0, 0x70114afd, 0x1180f3c0, 0x70114afc, 0x0201f000, 
+    0xf3c049fb, 0x780b0040, 0x700a431a, 0x780a49f9, 0x700a4302, 0xe92d4770, 0x4df75ff0, 0x4bf72400, 
+    0x4ff14ef2, 0xf8df702c, 0x781b93d8, 0xf8dfb318, 0x2801c3d4, 0xa3acf8df, 0x83ccf8df, 0xe00bf89c, 
+    0x1cdeea4f, 0x2802d01e, 0x2000d02c, 0x0000f888, 0x0000f88a, 0x70387030, 0x0000f889, 0xf8df2903, 
+    0xf8df83ac, 0xf8dfa3ac, 0xd024b3ac, 0xd0362905, 0xd0472904, 0x48e8e058, 0x28186800, 0xf889d318, 
+    0xe7eb3000, 0xd1e92a01, 0xc000f88a, 0x1040f3ce, 0xc000f888, 0x70387030, 0x1080f3ce, 0x3000f889, 
+    0xe7db7028, 0xd1032a01, 0xc000f88a, 0xc000f888, 0x703b7033, 0x2201e7e3, 0x21024640, 0xff37f01b, 
+    0xf88a2201, 0x21020000, 0xf01b4640, 0xf88bff30, 0x24050000, 0xf89948d1, 0x70011000, 0x2206e024, 
+    0x21404640, 0xff23f01b, 0xf88a2206, 0x21400000, 0xf01b4640, 0xf88bff1c, 0x24040000, 0x783948c7, 
+    0xe0117001, 0x46402205, 0xf01b2120, 0x2205ff10, 0x0000f88a, 0x46402120, 0xff09f01b, 0x0000f88b, 
+    0x48be2403, 0x70017831, 0xf89a2601, 0x48bc1000, 0x82f0f8df, 0x4fbc2901, 0x92f0f8df, 0x49b7d103, 
+    0x29017809, 0xf89bd004, 0x29011000, 0xe025d022, 0x680949b1, 0xd3082912, 0x70012102, 0xfa067829, 
+    0x4308f004, 0x403cf440, 0x2103e007, 0x78297001, 0xf004fa06, 0xf4404308, 0xb281406e, 0xf01b4640, 
+    0x4648feae, 0xe8bd703e, 0x23005ff0, 0x21082203, 0xbebff01b, 0x780949a6, 0xd00e2901, 0x70042400, 
+    0x46232203, 0x46482108, 0xfeb3f01b, 0x46402100, 0xfe95f01b, 0xe8bd703c, 0x21049ff0, 0x23017001, 
+    0x22034648, 0xf01b2108, 0x2301fea4, 0x22004899, 0xf01b4619, 0x7829fe9e, 0xf004fa06, 0xb2804308, 
+    0x414ff440, 0xf01b4640, 0x4893fe7a, 0x703e4993, 0x78004c96, 0x43087809, 0x70084991, 0x49924891, 
+    0x780a7800, 0x43104992, 0x20017020, 0xfaf1f7f2, 0x20017822, 0x5ff0e8bd, 0xf7f2498e, 0xe92dbaea, 
+    0x460447f0, 0x4699487f, 0x23014615, 0x2202460e, 0x38162104, 0x7808e9dd, 0xfe6bf01b, 0x4c794623, 
+    0x3c402208, 0x46200151, 0xfe63f01b, 0x46332207, 0x46202180, 0xfe5df01b, 0x462b220a, 0x4100f240, 
+    0xf01b4620, 0x2209fe56, 0xf240464b, 0x46202100, 0xfe4ff01b, 0x463b2206, 0x46202140, 0xfe49f01b, 
+    0x46204643, 0x47f0e8bd, 0x21202205, 0xbe41f01b, 0x2801b57c, 0x2802d001, 0x495ad164, 0x098a79c9, 
+    0x2a01496d, 0xd15d700a, 0x7809496c, 0xfeb3f7ff, 0x484e494d, 0x78007809, 0x0100e9cd, 0x78034852, 
+    0x78024848, 0x7801484a, 0x7800484a, 0xffa7f7ff, 0x220b4c4e, 0x0100f640, 0x46201ca4, 0xfe27f01b, 
+    0x22004d50, 0x46032101, 0x46283d40, 0xfe11f01b, 0xf240220a, 0x46204100, 0xfe19f01b, 0x46032201, 
+    0x46282102, 0xfe05f01b, 0x46282300, 0x21042202, 0xfdfff01b, 0xf2402209, 0x46202100, 0xfe07f01b, 
+    0x46032203, 0x46282108, 0xfdf3f01b, 0x46202201, 0xf01b2102, 0x2204fdfc, 0x21104603, 0xf01b4628, 
+    0x2301fde8, 0x46191f2c, 0x46202200, 0xfde1f01b, 0x46202300, 0x461a2101, 0xfddbf01b, 0x407ce8bd, 
+    0xbe23f7f8, 0xb530bd7c, 0x5403e9dd, 0x2804b10c, 0xb11dd002, 0xe004b95a, 0xbd302003, 0xb932b911, 
+    0xb109e002, 0xbd302000, 0x2002b10b, 0x2001bd30, 0x4308bd30, 0x2001d000, 0xb5704770, 0x21034c30, 
+    0xf01b4620, 0x2181fd9c, 0xf01b1f20, 0x481dfd98, 0x21012300, 0x3876461a, 0xfdabf01b, 0x220f4929, 
+    0x780b4620, 0x0100f248, 0xfda3f01b, 0x78284d26, 0x2301b130, 0x22064620, 0xf01b2140, 0xe045fd9a, 
+    0x0000e065, 0x000405da, 0x000405cf, 0x000405d0, 0x000405dd, 0x000405dc, 0x000405c2, 0x000405d1, 
+    0x000405ce, 0x00041448, 0x000405db, 0xf38e0040, 0x000405cc, 0x000405c0, 0x00040238, 0x000405cd, 
+    0x00040f46, 0xf38f0076, 0x00040f45, 0xf2035256, 0x000405c1, 0xf23c8024, 0x000405c9, 0x000405ca, 
+    0x000405cb, 0x000405c6, 0x000405c7, 0x000405c8, 0xfeda0000, 0xfedc0000, 0x0004055d, 0x0004028a, 
+    0xf38f2056, 0x00040344, 0x00040345, 0xf6477828, 0x1e404100, 0x220ab283, 0xf01b4620, 0x484efd4a, 
+    0x21802207, 0x46207803, 0xfd43f01b, 0x46202301, 0x21202205, 0xfd3df01b, 0xfd6bf011, 0x78004847, 
+    0xd0082801, 0x78004846, 0xd0042801, 0x2300e009, 0x21402206, 0x2301e7e0, 0x220c4842, 0xf01b0319, 
+    0x4841fd28, 0x22012300, 0xf01b213e, 0x2004fd22, 0xf94bf7f9, 0x4070e8bd, 0xf7f9200b, 0xe92dba79, 
+    0xf8df5ff0, 0xf24fb0e0, 0x23000a00, 0xf10b4688, 0x46810b4a, 0x4651220c, 0xf01b4658, 0xf10bfd0a, 
+    0xf6400402, 0x23004100, 0x220a4620, 0xfd01f01b, 0xf1b8482e, 0x4d2c0f03, 0x7100f240, 0x36fff240, 
+    0x77fff240, 0x2300d02e, 0xf01b2208, 0x230cfcf2, 0x22014628, 0xf01b213e, 0x2324fcec, 0x22004631, 
+    0xf01b4620, 0x2303fce6, 0x220c4651, 0xf01b4620, 0xf240fce0, 0x46393304, 0x46582200, 0xfcd9f01b, 
+    0x0f01f1b9, 0x2301d127, 0x4100f640, 0x4620220a, 0xfccff01b, 0x46584651, 0x5ff0e8bd, 0x220c230f, 
+    0xbcc7f01b, 0x22082303, 0xfcc3f01b, 0x4628230c, 0x213e2201, 0xfcbdf01b, 0x4631231b, 0x46202200, 
+    0xfcb7f01b, 0x46512304, 0x4620220c, 0xfcb1f01b, 0x4300f240, 0xe5fee7cf, 0x00040346, 0x0004027d, 
+    0x00040285, 0xf203902c, 0xf38f0002, 0xf38f20f0, 0x4ff0e92d, 0xb2bcf8df, 0xf8dfb087, 0xf8db92b4, 
+    0xf8d90000, 0x88008000, 0x20009004, 0xfb1ff7fb, 0x4000f240, 0x0a01f04f, 0xf8cd2205, 0x1044a00c, 
+    0xe9cd9400, 0xf8d92001, 0x1f920000, 0xf2402103, 0xf2406500, 0xf24016df, 0x465317a7, 0xf9bef00e, 
+    0xf04f489d, 0x78000100, 0x46082803, 0xf8d9d013, 0xf9333000, 0x2a002011, 0x4252da00, 0x42a11c49, 
+    0xdbf64410, 0x20001244, 0xdd1342b4, 0x1464eba4, 0x1165eba5, 0x4a91e014, 0x2001f992, 0x2382eb08, 
+    0x2011f933, 0xda002a00, 0x1c494252, 0x441042a1, 0xe7e7dbf6, 0xda0842bc, 0x1464eb04, 0x1165eb05, 
+    0xb2401c40, 0x2810b20d, 0xf44fdbde, 0xf2400800, 0x464011f4, 0xf85ff7f2, 0x46404981, 0xf84af7f2, 
+    0x46404639, 0xf846f7f2, 0x46404621, 0xf842f7f2, 0x46404631, 0xf83ef7f2, 0x46404629, 0xf83af7f2, 
+    0x46404978, 0xf836f7f2, 0xf7f92000, 0x4e76fd01, 0x4800f240, 0x78314640, 0xf89ef7f9, 0xf7f72001, 
+    0x4f72ffd0, 0x68389904, 0xfc02f01c, 0x0000f8db, 0x106cf8b0, 0xf8206838, 0xf8db5011, 0x10692000, 
+    0x01a5eb01, 0x24004249, 0x206cf8b2, 0xeb004625, 0x80410042, 0x68382300, 0xe9cd461a, 0x20010500, 
+    0xf7f7b261, 0x1c64fdfe, 0x2c04b2a4, 0x2000d3f2, 0xffa7f7f7, 0x78204c5e, 0xd0232801, 0xf00f2002, 
+    0x7831f803, 0xf7f92040, 0xf7fef867, 0x7831fc70, 0x0000f244, 0xf860f7f9, 0x4640220b, 0x46112300, 
+    0x95019500, 0xfd83f7f9, 0xf241220d, 0x23000000, 0x95004611, 0xf7f99501, 0x4f4efd7a, 0xb3d87838, 
+    0xe03e2001, 0xf00e2000, 0x220effdf, 0x0900f640, 0x46484611, 0xfe22f7f9, 0xf00e2002, 0x7831ffd5, 
+    0xf7f92040, 0x200cf839, 0x220d9000, 0x23014657, 0xe9cd4611, 0x9504a502, 0x90019505, 0xf7f94640, 
+    0x200dfe9d, 0x23019000, 0xe9cd4602, 0x46017502, 0x95059504, 0x46489001, 0xfe90f7f9, 0x9000200e, 
+    0x46022301, 0x7502e9cd, 0x95044601, 0x90019505, 0xf7f94648, 0xe7c0fe83, 0x7820e7ff, 0xd1bf2801, 
+    0xf00d2000, 0x4605fafa, 0xf7f92000, 0x7831fc61, 0x464046c1, 0xf800f7f9, 0xd0362d00, 0xd13407e8, 
+    0xf2464d25, 0xf8df0a00, 0x220d8094, 0xf9954651, 0xb2830000, 0xf01b4640, 0x2301fb6c, 0x220f4640, 
+    0xf01b03d9, 0x2001fb66, 0xff7ef00e, 0x46487831, 0xffe2f7f8, 0x481a7839, 0xf9952900, 0x5c411000, 
+    0x7820d102, 0xd0012801, 0xe0002001, 0xf00d2000, 0x2300f979, 0x220d4651, 0xf01b4640, 0xb007fb4a, 
+    0xe8bd2000, 0xf00e4ff0, 0xb007bf5f, 0x8ff0e8bd, 0x00040224, 0x000405f8, 0x000405d9, 0x00040578, 
+    0x99339933, 0xdcba01f5, 0x0004028b, 0x00040230, 0x0004055c, 0x000402ec, 0x00040276, 0xf2035092, 
+    0x0004057c, 0x41ffe92d, 0xf04f4eff, 0x15505200, 0x1000f996, 0xff8df7f1, 0xfe7af7ff, 0xf7f92000, 
+    0xf44ffbf7, 0xf2400500, 0x462811f4, 0xff33f7f1, 0x462849f6, 0xff1ef7f1, 0xf9944cf5, 0xb2810000, 
+    0xf7f14628, 0x49f3ff28, 0xf7f14628, 0x4668ff13, 0xff8df7fa, 0x0000f994, 0xd0011c40, 0xe0262007, 
+    0xf9954ded, 0x1c400000, 0xeb0017c1, 0xf0217191, 0x1a400103, 0x20007028, 0xfa97f7fe, 0x839cf8df, 
+    0xf2402400, 0x78282700, 0x4639b108, 0x4641e000, 0xf7fe4620, 0x1c64fbb3, 0x2c04b264, 0x7828dbf3, 
+    0xd1052800, 0x780048de, 0xf9d1f7f5, 0x70302003, 0x81ffe8bd, 0x5ffce92d, 0x46152400, 0xf01d46a2, 
+    0x4ed8ff9f, 0xf980fa0f, 0x835cf8df, 0xf44f2701, 0x4ad60b80, 0x466849d6, 0xf8ad8037, 0xf8ada006, 
+    0xf8ada002, 0xf8ada004, 0xf898a000, 0xf7fa3000, 0x2172ffff, 0xf7f14658, 0x2202fef6, 0x21074648, 
+    0xfec8f00e, 0xf7fa4668, 0x2000ffd4, 0xf9314669, 0x42aa2010, 0xf821db01, 0x1c405010, 0x2804b240, 
+    0x48c4dbf5, 0x28037800, 0x48c3d104, 0x0003f990, 0x7010f821, 0x3000f898, 0x4abc4668, 0xf7fa49bc, 
+    0x2172ffd7, 0xf7f14658, 0x8830fece, 0xd1032802, 0xb2641c64, 0xdbbc2c0a, 0xa000f8a6, 0x9ffce8bd, 
+    0x47f0e92d, 0xf04f4fa8, 0x20505200, 0x15506078, 0x1000f997, 0xfeddf7f1, 0x20004eb0, 0x82a8f8df, 
+    0x49ab4aaa, 0x80b080f0, 0x80308070, 0xf8984630, 0xf7fa3000, 0xf44fffad, 0x21720980, 0xf7f14648, 
+    0x2202fea2, 0x1048f240, 0xf00e2107, 0x251efe73, 0x24014630, 0xff7df7fa, 0xf9362000, 0x42a91010, 
+    0xf826db01, 0xf9365010, 0x42a11010, 0xf826dc01, 0x1c404010, 0x2804b240, 0xf898dbef, 0x4a933000, 
+    0x48964993, 0xff84f7fa, 0x46482172, 0xfe7bf7f1, 0x60782060, 0x87f0e8bd, 0x4c83b538, 0x90002000, 
+    0x60602030, 0xf7fb4668, 0x488afa3d, 0x46687801, 0xd1042903, 0x21014a88, 0x2003f992, 0x49825481, 
+    0x29037809, 0x4981d10c, 0x2000f991, 0x3002f991, 0x54c25c82, 0x2001f991, 0x1003f991, 0x54425c82, 
+    0x0000f89d, 0xb1b84d7e, 0x0001f89d, 0xf89db1e8, 0xb1880002, 0x0003f89d, 0x2040b170, 0x0110f242, 
+    0x06406060, 0xfe23f7f1, 0x70202003, 0x46282301, 0x46192200, 0xf9edf01b, 0x0001f89d, 0x2301b128, 
+    0x21024628, 0xf01b461a, 0xf89df9e4, 0xb1280002, 0x46282301, 0x21042202, 0xf9dbf01b, 0x0003f89d, 
+    0xd0052800, 0x46282301, 0x21082203, 0xf9d1f01b, 0xe92dbd38, 0x46045ff0, 0x4d538e80, 0xf5b02601, 
+    0xf2407f96, 0xf2401a05, 0xd07b1b61, 0x4550dc35, 0x1105f2a0, 0xdc18d069, 0xd07428f0, 0xb330dc06, 
+    0xd07528ce, 0xd17028cf, 0xe07c60ae, 0xd05c28f1, 0x7f82f5b0, 0x4944d169, 0x68e82200, 0xf0163110, 
+    0x60a8fe2e, 0xd07a1d40, 0x2910e050, 0xdc0fd04d, 0xd0752907, 0xd0482908, 0xd156290f, 0x2200493a, 
+    0x311068e8, 0xfe1bf016, 0x1d4060a8, 0xe03dd069, 0xd067291f, 0xd1482920, 0x4558e037, 0x1161f2a0, 
+    0xdc1bd033, 0x7fa6f5b0, 0xdc07d05d, 0x0034f111, 0x2813d02b, 0x2814d076, 0xe026d137, 0x7080f5a0, 
+    0xd022384d, 0xd1302813, 0x22004927, 0x311068e8, 0xfdf5f016, 0x1d4060a8, 0xe017d065, 0xd014291a, 
+    0x2911dc0f, 0x2912d07e, 0x2919d00f, 0x491ed11d, 0x68e82200, 0xf0163110, 0x60a8fde2, 0xd0721d40, 
+    0x2921e004, 0x2922d070, 0x60aed10f, 0x32fff04f, 0x68e84915, 0xf0163110, 0x60a8fe01, 0xd0051d00, 
+    0xe00c68a8, 0xe0a5e157, 0xe0d4e002, 0xe20720ce, 0x2200490d, 0x311068e8, 0xfdf0f016, 0x1d4160a8, 
+    0x2801d067, 0x4f08d1e2, 0x1000f240, 0xf9b73710, 0x2b0f3000, 0x0542d05f, 0x080af04f, 0xe0b8e024, 
+    0xe0f1e0cd, 0xe176e11b, 0x00040698, 0x99349934, 0x00040276, 0xdcba01f5, 0x00040562, 0xfffffa00, 
+    0x0004028a, 0x000402b0, 0x000405d9, 0x00040578, 0x000405a6, 0x0004027c, 0x00040570, 0x00040590, 
+    0xf2035018, 0xe17fe139, 0xf04f2b10, 0xd03a4c20, 0xd1ab2b0a, 0x1000f995, 0x9420f8df, 0x2903b391, 
+    0x2906d06f, 0x2902d06e, 0x2904d06d, 0x290cd06c, 0x2907d06b, 0x2905d06a, 0x2909d069, 0x290ad068, 
+    0xe002d067, 0xe19ae179, 0x290be19f, 0x4619d18e, 0xf7f14662, 0x200bfd4e, 0x48f98038, 0x32fff04f, 
+    0x68004639, 0xfd5bf016, 0x1d0060a8, 0x68a8d073, 0x20cfe192, 0xf04fe194, 0x46194222, 0xfd39f7f1, 
+    0xe773702e, 0x49efe030, 0x1000f991, 0xd0032903, 0xd0012905, 0xd1022904, 0x780949eb, 0x210fb121, 
+    0xf7f1702e, 0xe761fd26, 0x46624619, 0xfd21f7f1, 0xfa77f000, 0x70282000, 0x8000f8a7, 0x49e34602, 
+    0xf01668e8, 0x60a8fd2c, 0xd0011d00, 0xe00768a8, 0xe16520f0, 0x220049dd, 0xf01668e8, 0x60a8fd20, 
+    0xd1ce1d40, 0xe15b20f1, 0xfe66f7ff, 0xf7f82002, 0xb920fcd1, 0x0000f899, 0x28061e40, 0x200ad20a, 
+    0xe01ae009, 0xe052e036, 0xe09fe084, 0xe0dde0c0, 0xe11de0fd, 0x8038200f, 0x220049cc, 0xf01668e8, 
+    0x60a8fcfe, 0xd0011d00, 0xe6cb68a8, 0x1004f240, 0xf8a4e136, 0xe8bda034, 0xf7ff9ff0, 0x2006fdf1, 
+    0x49c27028, 0x68e82200, 0xfce9f016, 0x1d0060a8, 0x68a8d002, 0xe115e009, 0x100cf240, 0x49bbe120, 
+    0x68e82200, 0xfcdbf016, 0x1d4060a8, 0xf240d189, 0xe115100d, 0x606b2370, 0xfcbbf7f1, 0x221e49b4, 
+    0xf7ff48b4, 0x2080fd77, 0x20026068, 0x49af7028, 0x68e82200, 0xfcc3f016, 0x1d0060a8, 0x68a8d001, 
+    0xf240e6a3, 0xe0fb1014, 0x1015f240, 0x2390e0f8, 0xf7f1606b, 0x2100fc9e, 0xf00a2001, 0x2100fb8b, 
+    0x1080f44f, 0xfca8f7f8, 0x46082100, 0xfb82f00a, 0xfc78f00e, 0xf8c0f7f9, 0xf8dbf7f9, 0x606820a0, 
+    0x70282004, 0x22004999, 0xf01668e8, 0x60a8fc98, 0xd0011d00, 0xe00868a8, 0x1024f240, 0x4993e0d0, 
+    0x68e82200, 0xfc8bf016, 0x1d4060a8, 0xf240d1ae, 0xe0c51025, 0xf998f000, 0x7028200c, 0x2200498b, 
+    0xf01668e8, 0x60a8fc7c, 0xd0011d00, 0xe00868a8, 0x102cf240, 0x4985e0b4, 0x68e82200, 0xfc6ff016, 
+    0x1d4060a8, 0xf240d192, 0xe0a9102d, 0xfcbaf7ff, 0xf7f82002, 0xb108fc1f, 0xe000200a, 0x8038200f, 
+    0x2200497a, 0xf01668e8, 0x60a8fc5a, 0xd0011d00, 0xe00868a8, 0x1040f240, 0x4974e092, 0x68e82200, 
+    0xfc4df016, 0x1d4060a8, 0xf240d1c0, 0xe0871041, 0xfc2ff7f1, 0xfbabf007, 0x70282005, 0x2200496b, 
+    0xf01668e8, 0x60a8fc3c, 0xd0011d00, 0xe00868a8, 0x104cf240, 0x4965e074, 0x68e82200, 0xfc2ff016, 
+    0x1d4060a8, 0xf240d1a2, 0xe069104d, 0xf906f000, 0x0000f899, 0xd0052803, 0xf7f82002, 0xb120fbdb, 
+    0xe003200a, 0x8000f8a7, 0x200fe001, 0x49578038, 0x68e82200, 0xfc13f016, 0x1d0060a8, 0x68a8d001, 
+    0xf240e619, 0xe04b1060, 0xb034f8a4, 0xf000e713, 0xf899f8ad, 0x28030000, 0xadd6f43f, 0x8000f885, 
+    0x494a2200, 0xf01668e8, 0x60a8fbfa, 0xd0011d00, 0xe00868a8, 0x1072f240, 0x4944e032, 0x68e82200, 
+    0xfbedf016, 0x1d4060a8, 0xf240d19e, 0xe0271073, 0xf837f000, 0xf7f82002, 0xb108fb9d, 0xe000200a, 
+    0x8038200f, 0x22004939, 0xf01668e8, 0x60a8fbd8, 0xd0011d00, 0xe5f168a8, 0x107af240, 0xf240e010, 
+    0xe00d107b, 0x1082f240, 0x482de00a, 0x492f2200, 0xf0166800, 0x60a8fbc4, 0xd1931d40, 0x1083f240, 
+    0xe6c886a0, 0x21012200, 0xf2afb510, 0xf0165039, 0x2108fa01, 0xf0162003, 0x4924fb5f, 0x60c83910, 
+    0xb510bd10, 0xfbcaf00c, 0x48244923, 0xfcf6f01a, 0xf2402801, 0xd0191300, 0x461c21e2, 0xf7f14618, 
+    0x2100fb3a, 0xf7f14620, 0xf242fb25, 0x462001d0, 0xfb3df7f1, 0x7800481a, 0xd01b2801, 0x48192100, 
+    0x4010e8bd, 0x312bf201, 0xbee9f01a, 0x49164813, 0xf3c079c0, 0x70081000, 0xd00a2800, 0xf04f4c0b, 
+    0x46185200, 0xf9943c10, 0xf7f11000, 0x200bfb62, 0xbd107020, 0x7110f242, 0x0000e7e1, 0x0004027c, 
+    0x00040734, 0x0004028a, 0x000402ec, 0x000406a8, 0x44b861ec, 0x43a4170a, 0x0002d000, 0x00041448, 
+    0x0004055c, 0xf23c80ba, 0x0004024c, 0x4968b50e, 0x70082001, 0x78004867, 0x4967b178, 0x78094867, 
+    0xe9cd7800, 0x48660100, 0x48667801, 0x48667803, 0x48667802, 0xf7fb7800, 0x4865ff3b, 0xf9904965, 
+    0xf7f70000, 0x4a64fa44, 0x48622104, 0xfd6cf01a, 0xf04f4862, 0xf9905200, 0x15501000, 0xfb19f7f1, 
+    0xf00e2004, 0x495efd2d, 0x20007008, 0x46014602, 0xe9cd9002, 0xf7f70000, 0xbd0efcef, 0x4c57b510, 
+    0x5200f04f, 0xf9941550, 0xf7f11000, 0xf00cfb02, 0xb158fe9c, 0x78004853, 0xd0022803, 0x70202009, 
+    0x2004bd10, 0xfab1f7f8, 0xe7f8200b, 0xf7fa2000, 0x4843fd0e, 0xf7f47800, 0x484bfd7a, 0x70222203, 
+    0x49432300, 0x4000f990, 0xf990550b, 0x23014001, 0xf990550b, 0x23024002, 0xf990550b, 0x540a0003, 
+    0x4010e8bd, 0xbde1f00c, 0x4c3cb510, 0x5200f04f, 0x606020b0, 0xf9941550, 0xf7f11000, 0x20b1faca, 
+    0xf00e6060, 0xf7f8faaf, 0xf7f8fef7, 0x20bbff12, 0x48346060, 0xb1707800, 0xd00c2807, 0x606020e0, 
+    0x22004832, 0x20026801, 0xfa94f7f8, 0xfc1af00d, 0x606020f0, 0x20c0bd10, 0xf00d6060, 0x20d0fc13, 
+    0xb570e7f7, 0x20104c25, 0x01052101, 0x46286060, 0xfa51f7f1, 0x11f4f240, 0xf7f14628, 0x4824fa4c, 
+    0xf0406800, 0x462841d0, 0xfa34f7f1, 0x46284921, 0xfa30f7f1, 0xf7fa2000, 0xf7fafaeb, 0x2020fbe2, 
+    0x48196060, 0x49122400, 0x2000f990, 0xf990548c, 0x22013001, 0xf99054ca, 0x22023002, 0xf99054ca, 
+    0x22030003, 0xf00c540a, 0x4813fd80, 0xbd707004, 0x0004024b, 0x00040535, 0x000405ff, 0x000405fe, 
+    0x0004028a, 0x000405fd, 0x000405fc, 0x00040534, 0x00040570, 0x000412c8, 0x00041348, 0x00040698, 
+    0x0004024d, 0x0004027c, 0x00040578, 0x000405e4, 0x00057f78, 0xdcba01f5, 0x00040562, 0x4cffb510, 
+    0x4280f04f, 0xf9b41510, 0xf7f11000, 0xf00cfa42, 0xb168fddc, 0x22112300, 0x3100f44f, 0x4071f04f, 
+    0xfdb0f01a, 0xf7f82001, 0x200efea3, 0xbd108020, 0x80202007, 0x220048f2, 0xf99049f2, 0x54ca3000, 
+    0x3001f990, 0x54ca2201, 0x3002f990, 0x54ca2202, 0x0003f990, 0x540a2203, 0x4010e8bd, 0xbd25f00c, 
+    0xf04f48e6, 0xb5104280, 0x1000f9b0, 0xf7f11510, 0x48e5fa10, 0xfacdf7fa, 0x200049e3, 0x2301221e, 
+    0x4010f931, 0xdb012c1e, 0x2010f821, 0x4010f931, 0xdc012c01, 0x3010f821, 0xb2401c40, 0xdbef2804, 
+    0x4ad748da, 0x780349da, 0xf7fa48d7, 0x2172fad1, 0x0080f44f, 0xf9c7f7f1, 0x4010e8bd, 0xb967f007, 
+    0x41f0e92d, 0xf04f4ecd, 0x15104280, 0x1000f9b6, 0xf9dff7f1, 0xf8ccf7ff, 0xf7f82000, 0x48cdfe49, 
+    0x0000f990, 0xd0011c40, 0xe0222012, 0xf9954dca, 0x1c400000, 0xeb0017c1, 0xf0217191, 0x1a400103, 
+    0x20007028, 0xfd01f7fd, 0x8310f8df, 0xf2402400, 0x78282700, 0x4639b108, 0x4641e000, 0xf7fd4620, 
+    0x1c64fe1d, 0x2c04b264, 0x7828dbf3, 0xd1012800, 0x80302007, 0x81f0e8bd, 0x4ff0e92d, 0x4fbaa0b8, 
+    0xe9d0b08d, 0xe9cd1000, 0x48b8100b, 0x6800683d, 0xd3142812, 0x409cf648, 0xf6469004, 0x900530ad, 
+    0x707af242, 0xf2419006, 0x90071029, 0x3063f640, 0xf2409008, 0x900940e7, 0x20a9f240, 0xf244e013, 
+    0x900430a4, 0x401cf243, 0xf2419005, 0x90064016, 0x003df640, 0xf2409007, 0x9008505b, 0x207ff240, 
+    0xf2409009, 0xf8df104d, 0xf240b254, 0x900a4a00, 0x4280f04f, 0x46504656, 0x1000f9bb, 0xf969f7f1, 
+    0xf44f2100, 0xf7f82000, 0x2101f977, 0x02082405, 0xe9cd1e8a, 0xe9cd6102, 0x68380400, 0x21082300, 
+    0xfa2cf00d, 0x46132200, 0x20004611, 0x2741eb05, 0x6010f937, 0xb2801c40, 0xfbc628ff, 0xd9f72386, 
+    0xb2c91c49, 0xd3f02904, 0x0c959804, 0xea454e88, 0x42a83583, 0x7034d801, 0x2000e033, 0x46047030, 
+    0xeb00a804, 0x68490184, 0xd82242a9, 0x7024f850, 0x0084eb00, 0x1a386840, 0xfcf6f01c, 0x46894680, 
+    0xf01c1b78, 0x4605fcf1, 0xa80b460f, 0x5d041901, 0x1b087849, 0xfcd1f01c, 0x463b462a, 0xfd34f01c, 
+    0x464b4642, 0xfb14f01c, 0xfc9af01c, 0x70304420, 0x1c64e003, 0x2c06b2a4, 0x7830d3d3, 0x2064b908, 
+    0x78307030, 0x0100f640, 0x30234654, 0x46507030, 0xf8b1f7f1, 0x46207831, 0xf89cf7f1, 0x20012100, 
+    0xffe8f009, 0x25004c63, 0x4a554e58, 0x49584620, 0x80a580e5, 0x80258065, 0xf7fa7833, 0xf44ff9c9, 
+    0x21720880, 0xf7f14640, 0x4f5bf8be, 0x21012200, 0xf01a4638, 0xb988fc7c, 0x46382201, 0xf01a2102, 
+    0xb958fc76, 0x46382202, 0xf01a2104, 0xb928fc70, 0x46382203, 0xf01a2108, 0xb110fc6a, 0xf7fb2001, 
+    0x2202fda7, 0x10c3f240, 0xf00e2107, 0x4849f873, 0xf97ff7fa, 0x1002f9bb, 0xf9342000, 0x428a2010, 
+    0xf824db01, 0x1c401010, 0x2804b240, 0x7833dbf5, 0x49374a33, 0xf7fa483f, 0x2172f98b, 0xf7f14640, 
+    0x2002f882, 0xf850f00e, 0xf7fa2000, 0x2000fac0, 0xfa3af7fb, 0x20012100, 0xff8cf009, 0xf44f2100, 
+    0xf7f82000, 0x2004f8a9, 0xfaaaf00e, 0x70084933, 0x460a2100, 0x95024608, 0x1100e9cd, 0xfa6cf7f7, 
+    0x46082100, 0xff76f009, 0xe8bdb00d, 0x481b8ff0, 0x4280f04f, 0x1000f9b0, 0xf7f11510, 0x2101b87a, 
+    0x028cb510, 0xf7f14620, 0xf240f826, 0x462011f4, 0xf821f7f1, 0x68084922, 0x41f0f040, 0xf7f14620, 
+    0x4920f809, 0xf7f14620, 0x490cf805, 0x8048201e, 0xf7f92001, 0x480af9ab, 0x490a2400, 0x2000f990, 
+    0xf990548c, 0x22013001, 0xf99054ca, 0x22023002, 0xf99054ca, 0x22030003, 0xe025540a, 0x000406b0, 
+    0x00040578, 0x00040570, 0x00040598, 0x000405d9, 0x000405a6, 0x00040276, 0x00040562, 0xfffffa00, 
+    0x321e0a05, 0x0064503c, 0x00040224, 0x00040238, 0x0004055e, 0x00040590, 0xf20305c2, 0x0004024d, 
+    0x00057f78, 0xdcba01f5, 0xfb2ff00c, 0x700448f9, 0xe92dbd10, 0x46045ff0, 0x4df78e80, 0x1b4ef240, 
+    0xa3d8f8df, 0xf2404558, 0xf2401801, 0xd0741967, 0x4540dc32, 0x1101f2a0, 0xdc16d064, 0xd06d28e6, 
+    0xb318dc05, 0xd06c28c4, 0xd16928c5, 0x28e7e073, 0xf5b0d058, 0xd1637f80, 0x220049e7, 0x31086868, 
+    0xf80df016, 0xd07d1d40, 0x291ce04c, 0xdc0ed04a, 0xd0782909, 0xd045290a, 0xd151291b, 0x220049de, 
+    0x31086868, 0xfffbf015, 0xd06d1d40, 0x2943e03a, 0x2944d06b, 0xe035d144, 0xf2a04548, 0xd0311167, 
+    0xf5b0dc1a, 0xd07d7faf, 0xf111dc07, 0xd0290018, 0xd0782807, 0xd1332808, 0xf5a0e024, 0x385f7080, 
+    0x2807d020, 0x49ccd12c, 0x68682200, 0xf0153108, 0x1d40ffd6, 0xe015d068, 0xd0132910, 0x2907dc0e, 
+    0x2908d070, 0x290fd00e, 0x49c3d11a, 0x68682200, 0xf0153108, 0x1d40ffc4, 0xe003d07c, 0xd07a291b, 
+    0xd10d291c, 0xf04f49bc, 0x686832ff, 0xf0153108, 0x1d01ffe5, 0x20c4d10b, 0xe11de1c5, 0xe000e080, 
+    0x49b5e0aa, 0x68682200, 0xf0153108, 0x1d41ffd7, 0x2801d046, 0x4eb0d1e6, 0xf2402700, 0x36084000, 
+    0x1000f9b6, 0xd03e290f, 0x29110502, 0x290ad041, 0xf9b5d1d8, 0x4faa1000, 0xd06b2902, 0xd07d2901, 
+    0xe0032903, 0xe09de086, 0xe0dbe0be, 0x2904d077, 0x2905d076, 0x2906d075, 0x2907d074, 0x2910d073, 
+    0x2912d072, 0x2908d071, 0x290ed070, 0xf7f0d1ba, 0xf242ff60, 0x06c80170, 0xff19f7f0, 0x8030200b, 
+    0xe002200f, 0xe0f7e112, 0x8028e13d, 0x32fff04f, 0x0000f8da, 0xf0154631, 0x1d01ff62, 0xe16ed071, 
+    0xe17020c5, 0xf04fe140, 0xf7f04224, 0x802fff42, 0x4b8ce798, 0x3000f993, 0xd0032b03, 0xd0012b05, 
+    0xd1022b04, 0x781b4b88, 0x2113b133, 0xf7f0802f, 0xe787ff30, 0xe14ce147, 0x4220f04f, 0xff29f7f0, 
+    0xfeadf7ff, 0x2002497c, 0x200a8028, 0x22008030, 0x31086868, 0xff33f015, 0xd1071d01, 0xe14220e6, 
+    0x22004975, 0x31086868, 0xff29f015, 0xd1cf1d40, 0xe13820e7, 0x28017838, 0x2002d102, 0xfec5f7f7, 
+    0xfe85f7ff, 0x2001496c, 0x22008028, 0x31086868, 0xff15f015, 0xf47f1d01, 0xe008af05, 0xe02ce00e, 
+    0xe06ae045, 0xe0a2e083, 0xe0dfe0bb, 0xf240e0f6, 0xe1181000, 0x8034f8a4, 0x9ff0e8bd, 0xfee9f7f0, 
+    0x20012100, 0xfdd6f009, 0x2003495b, 0x22008028, 0x31086868, 0xfef3f015, 0xd1091d01, 0x100af240, 
+    0xe0f3e101, 0x22004954, 0x31086868, 0xfee7f015, 0xd18d1d40, 0x100bf240, 0xf7f0e0f5, 0x2100feca, 
+    0x1080f44f, 0xfed8f7f7, 0xf9fff006, 0x2004494a, 0x22008028, 0x31086868, 0xfed1f015, 0xf47f1d01, 
+    0xf240aed3, 0xe0de101c, 0x101df240, 0xf7f0e0db, 0x2100feb0, 0xf0094608, 0x7838fd9d, 0xd00a2801, 
+    0x2005493d, 0x22008028, 0x31086868, 0xfeb7f015, 0xd0041d01, 0x2002e00c, 0xfe57f7f7, 0xf240e6f2, 
+    0xe0c01044, 0x22004934, 0x31086868, 0xfea7f015, 0xd1f31d40, 0x1045f240, 0xf000e0b5, 0x492ef920, 
+    0x80282006, 0x68682200, 0xf0153108, 0x1d01fe98, 0xf8a4d108, 0xe78fb034, 0x22004927, 0x31086868, 
+    0xfe8df015, 0xd1d91d40, 0x104ff240, 0xf000e09b, 0x2002f8ab, 0xfe3ef7f7, 0x200ab108, 0x200fe000, 
+    0x8030491d, 0x68682200, 0xf0153108, 0x1d01fe78, 0xf240d108, 0xe0861056, 0x22004917, 0x31086868, 
+    0xfe6df015, 0xd1b91d40, 0x1057f240, 0xf7ffe07b, 0x4911fca3, 0x80282010, 0x68682200, 0xf0153108, 
+    0x1d01fe5e, 0xf240d108, 0xe06c105e, 0x2200490a, 0x31086868, 0xfe53f015, 0xd19f1d40, 0x105ff240, 
+    0xf7ffe061, 0x2002fc4d, 0xfe04f7f7, 0x200ab170, 0x0000e00d, 0x00040562, 0x000406b0, 0x00040734, 
+    0x0004027c, 0x0004028a, 0x000402ec, 0x8030200f, 0x22004975, 0xf0156868, 0x1d01fe32, 0xae59f47f, 
+    0x1066f240, 0xf8a4e03f, 0xe7259034, 0xfbf8f7ff, 0x80282008, 0x2200496c, 0xf0156868, 0x1d01fe20, 
+    0xf240d107, 0xe02e106e, 0x22004967, 0xf0156868, 0x1d40fe16, 0xf240d187, 0xe024106f, 0xfbaef7ff, 
+    0xf7f72002, 0xb108fdc7, 0xe000200a, 0x8030200f, 0x2200495d, 0xf0156868, 0x1d01fe02, 0xae3bf47f, 
+    0x1076f240, 0xf240e00f, 0xe00c1077, 0x1082f240, 0x4955e009, 0xf8da2200, 0xf0150000, 0x1d40fdf0, 
+    0xf240d19b, 0x86a01083, 0x2200e6e6, 0xb5102101, 0x40a1f2af, 0xfc2ef015, 0x20032108, 0xfd8cf015, 
+    0x39084949, 0xbd106048, 0x2000b5f8, 0x46689000, 0xf968f7fa, 0x78004845, 0xd1102803, 0xf9904844, 
+    0xf9902000, 0xf81d3002, 0xf80d2002, 0xf9902003, 0xf9902001, 0xf81d0003, 0xf80d2002, 0xf89d2000, 
+    0x28000000, 0xf89dd03a, 0x28000001, 0xf89dd036, 0x28000002, 0xf89dd032, 0x28000003, 0xf242d02e, 
+    0x46210410, 0x462806e5, 0xfd51f7f0, 0xf7f82000, 0x4b2df9ff, 0x4e2f2207, 0x46303b08, 0x2301801a, 
+    0x46192200, 0xf915f01a, 0x46302301, 0x461a2102, 0xf90ff01a, 0x46302301, 0x21042202, 0xf909f01a, 
+    0x46302301, 0x21082203, 0xf903f01a, 0x68004822, 0xd8032810, 0x46284621, 0xfd29f7f0, 0x481abdf8, 
+    0x3808b50e, 0x4280f04f, 0x1000f9b0, 0xf7f01510, 0x491afd60, 0x4a1d2000, 0x49197008, 0x49197008, 
+    0x49197008, 0x21017008, 0x46027011, 0x70084918, 0x70084918, 0xe9cd4601, 0x90020000, 0xf7f62001, 
+    0xf242ff2b, 0x06480140, 0xfd01f7f0, 0xfe99f7f9, 0xf7f82001, 0xb003f9ad, 0xf44f2100, 0xf85d2000, 
+    0xf7f7eb04, 0x0000bd49, 0x000406b8, 0x000405d9, 0x00040578, 0xf2035018, 0x00040238, 0x0004026b, 
+    0x00040269, 0x00040264, 0x00040267, 0x0004024b, 0x00040249, 0x00040246, 0x5ff0e92d, 0x46044da9, 
+    0x4ea98e80, 0x686b28c8, 0xdc15d070, 0xd0342893, 0xb300dc0d, 0xd16a2892, 0x46182200, 0x0108f105, 
+    0xfd4cf015, 0xd0261d41, 0xd1192801, 0x28b4e025, 0x28b5d06f, 0xe013d15b, 0xd01128d1, 0x28c9dc0c, 
+    0x28d0d00e, 0x4997d153, 0x46182200, 0xf0153108, 0x1d40fd06, 0xe003d07e, 0xd07c28da, 0xd14628db, 
+    0xf04f4990, 0x686832ff, 0xf0153108, 0x1d01fd27, 0x2092d1d8, 0x2093e0c0, 0xf8dfe0be, 0x27008228, 
+    0x2000f240, 0x0808f108, 0x1000f9b8, 0xd027290f, 0xf04f2912, 0xf04f090a, 0xf04f5240, 0xd0274b00, 
+    0xd1dd290a, 0x1000f9b5, 0xfcc3f7f0, 0x0000f9b5, 0xd06d2802, 0xd077280a, 0xd1d12806, 0x0170f242, 
+    0xf7f04658, 0x200bfc74, 0x0000f8a8, 0x80282007, 0x1e7a6830, 0xf0154641, 0x1d01fcc2, 0xe088d06f, 
+    0x4223f04f, 0xfca5f7f0, 0xe7b9802f, 0xe084e05d, 0xf9934b6e, 0x2b033000, 0x2b05d003, 0x2b04d001, 
+    0x4b6bd102, 0xb12b781b, 0x802f2109, 0xfc91f7f0, 0xe033e7a6, 0x4a20f04f, 0x46524607, 0xfc89f7f0, 
+    0x465221f1, 0xf7f04638, 0xf242fc84, 0x46580150, 0xfc3df7f0, 0xf7f82000, 0x485ef8eb, 0xf44f7801, 
+    0xf7f72080, 0xf44ffc89, 0xf6403000, 0xf7f00103, 0xe001fc22, 0xe046e043, 0xfeb8f7fc, 0xfdd5f7f8, 
+    0x20024950, 0x22008028, 0x9000f8a8, 0x68683108, 0xfc75f015, 0xd1071d01, 0xe03d20b4, 0x22004949, 
+    0x31084618, 0xfc6bf015, 0xd1ae1d40, 0xe03320b5, 0x22004944, 0x9000f8a5, 0x31086868, 0xfc5ff015, 
+    0xd1081d01, 0xe02720c8, 0x493ee00a, 0x46182200, 0xf0153108, 0x1d40fc54, 0x20c9d197, 0xe010e01c, 
+    0xf82bf000, 0x20064937, 0x22008028, 0x31086868, 0xfc45f015, 0xf47f1d01, 0x20d0af3c, 0x20d1e00c, 
+    0x20dae00a, 0x492fe008, 0x68302200, 0xf0153108, 0x1d40fc36, 0x20dbd18c, 0xe8bd86a0, 0x22009ff0, 
+    0xb5102101, 0x200ff2af, 0xfa74f015, 0x20032108, 0xfbd2f015, 0x60484923, 0xb570bd10, 0x20012100, 
+    0xfaf8f009, 0xf44f2100, 0xf7f72000, 0x2100fc15, 0xf0094608, 0x4c20faef, 0x46082100, 0x2000f994, 
+    0xfd9cf7f9, 0x0550f242, 0x06ee4629, 0xf7f04630, 0xf005fbae, 0x4629ff2a, 0xf7f04630, 0x2100fba8, 
+    0xf7f92001, 0xf994ffde, 0x21002000, 0xf7f9200c, 0x2101fd3f, 0x2000f994, 0xf7f94608, 0xf7fcfd7f, 
+    0x4629fff6, 0xf7f04630, 0x2300fb92, 0x0bb12211, 0x4071f04f, 0xff46f019, 0x4070e8bd, 0xf7f82001, 
+    0x0000b837, 0x000406c0, 0x00040734, 0x0004028a, 0x000402ec, 0x0004028b, 0x00040290, 0x43fee92d, 
+    0x4900f04f, 0x0870f242, 0x46412600, 0xf7f04648, 0x2000fb6e, 0xf81cf7f8, 0x270148fe, 0x463a4cfe, 
+    0x70074dfe, 0x80200278, 0x90022000, 0x0104e9d5, 0x0100e9cd, 0x46384639, 0xfd7ef7f6, 0x4af949f8, 
+    0x78084bfb, 0x48f87010, 0x70087800, 0x680a49f7, 0x2a1049f8, 0x4af8d906, 0x2a017812, 0x780ad102, 
+    0xd0032a05, 0x2a03780a, 0xe004d013, 0x78124af3, 0xd1002a01, 0x97001e96, 0xeb06780a, 0x781b0040, 
+    0xb2402100, 0xf9bcf00c, 0x46484641, 0xfb2ff7f0, 0x2203e015, 0x00409700, 0x2002e7f1, 0xfb3af7f7, 
+    0xd0092801, 0x46204ce6, 0xfed6f019, 0x7180f440, 0xf0194620, 0xe005fed4, 0xfd1af7f6, 0x88208020, 
+    0xd1ea2800, 0x1000f9b5, 0xf04fb003, 0xf64042a0, 0xe8bd0000, 0xf7f043f0, 0xe92dbb4c, 0x250043fe, 
+    0xfb7cf00b, 0x48d849d7, 0xfca8f019, 0xf6402801, 0xd01a0900, 0x464c21e2, 0xf7f04648, 0x2100faec, 
+    0xf7f04620, 0xf242fad7, 0x462001d0, 0xfaeff7f0, 0x780048ce, 0xd0702801, 0x48cd2100, 0xf201b003, 
+    0xe8bd312e, 0xf01943f0, 0x4ec1be9a, 0xf7fe7830, 0x4cc5f86f, 0x79e049c7, 0x00c0f3c0, 0x28007008, 
+    0xf242d06f, 0x06c80170, 0xfad1f7f0, 0xf7f72000, 0xf44fff7f, 0xf6403000, 0xf7f00103, 0xf7fcfabc, 
+    0x7a22fd55, 0x82f0f8df, 0xf0027a60, 0xea400203, 0x28402002, 0x0000f8a8, 0x2002d973, 0xfac4f7f7, 
+    0x48b64601, 0x68004cb7, 0x49b51a43, 0x2000f9b1, 0xf1f2fbb3, 0x60211cc9, 0x43511e89, 0xfb02f7f7, 
+    0x2701489c, 0x7007463a, 0x4c9b8821, 0x0000f8b8, 0x8268f8df, 0x80201a40, 0x90022000, 0x1004e9d8, 
+    0x1000e9cd, 0x46384639, 0xfcb6f7f6, 0x4a954994, 0x70107808, 0x78004894, 0x49947008, 0x4995680a, 
+    0xd9062a10, 0x78124a94, 0xd1022a01, 0x2a05780a, 0x780ad004, 0xd0102a03, 0xe034e005, 0x78124a8f, 
+    0xd1002a01, 0x97001e95, 0xeb05780a, 0x78330040, 0xb2402100, 0xf8f4f00c, 0x2203e016, 0x00409700, 
+    0xe01ee7f5, 0xf7f72002, 0x2801fa75, 0x4c84d009, 0xf0194620, 0xf040fe11, 0x46200180, 0xfe0ff019, 
+    0xf7f6e005, 0x8020fc55, 0x28008820, 0xf9b8d1ea, 0xf04f1000, 0x464442a0, 0xf7f04648, 0x2007fa8a, 
+    0xe8bd8020, 0xf24283fe, 0xe7567110, 0x41f0e92d, 0xfab4f00b, 0x48744973, 0xfbe0f019, 0x28014e73, 
+    0x0500f640, 0x21e2d017, 0xf7f04628, 0x2100fa24, 0xf7f04628, 0xf242fa0f, 0x462801d0, 0xfa27f7f0, 
+    0x28017830, 0x2100d03f, 0xe8bd4869, 0xf50141f0, 0xf019714b, 0x485ebdd4, 0xf7fd7800, 0x4c57ffa9, 
+    0x42a0f04f, 0xf9b44628, 0xf7f01000, 0x485efa52, 0x0702f04f, 0x4d654a64, 0x09c87901, 0xd0017010, 
+    0xb1387830, 0x28017830, 0x2004d11b, 0xfc58f00d, 0xe0157028, 0x1002f3c1, 0x7008495d, 0xf00d2004, 
+    0xb2c0fc4f, 0x78317028, 0x495ab951, 0x1c8a7809, 0xd9014290, 0xe003702a, 0x42881e89, 0x7029da00, 
+    0xe8bd8027, 0xf24281f0, 0xe7bd7110, 0x4ffee92d, 0x6800483e, 0xd3042812, 0xf44f2100, 0xf7f71080, 
+    0x484dfa2b, 0x4f4d2601, 0x0900f04f, 0x80e0f8df, 0x70064c32, 0x9000f887, 0x0000f898, 0xd0042801, 
+    0xd0022802, 0x46012000, 0x4d32e04a, 0xa110f8df, 0x28057828, 0x2201d105, 0x21024650, 0xfd97f019, 
+    0x7828b940, 0xd1072804, 0x46502200, 0xf0192101, 0xb108fd8e, 0xe0002001, 0x01c02000, 0xe9c417c1, 
+    0xf8980104, 0x28010000, 0x7828d124, 0x80d0f8df, 0xf1a82805, 0xd105083c, 0x46402206, 0xf0192140, 
+    0xb940fd76, 0x28047828, 0x2205d107, 0x21204640, 0xfd6df019, 0x2001b108, 0x2000e000, 0x2304e9d4, 
+    0x17c80141, 0x43184311, 0x1004e9c4, 0xf041703e, 0x61210140, 0x0104e9d4, 0xea410209, 0x02006110, 
+    0xe9c42200, 0xf8cd0104, 0xe9d49008, 0xe9cd0104, 0xe0370100, 0x00040267, 0x0004026e, 0x000406d0, 
+    0x00040251, 0x00040252, 0x0004024f, 0x00040238, 0x000405d9, 0x0004028a, 0x000402fa, 0x00040362, 
+    0xf203517c, 0x0002d000, 0x00041448, 0x0004055c, 0xf23c80ba, 0x00040268, 0x00040270, 0x00040278, 
+    0x000405e8, 0x0004056c, 0x0004025a, 0x0004024d, 0x00040253, 0x0004024e, 0x00040246, 0x000405c3, 
+    0xf38e007c, 0x46112001, 0xfb56f7f6, 0x49ff48fe, 0x70087800, 0x8ffee8bd, 0x4ffee92d, 0x8e804604, 
+    0xf2404dfb, 0xf5b01b1d, 0xd07d7f80, 0x28d3dc1b, 0xdc0fd038, 0x28a4b368, 0x28a5d03f, 0x28d2d047, 
+    0x6868d173, 0xf1052200, 0xf0150108, 0x1d40f968, 0xe027d06c, 0xd06a28e4, 0xd02328e5, 0xd06728ec, 
+    0xd16228ed, 0x4558e01e, 0x111df2a0, 0xdc11d01a, 0x001cf111, 0x2813d016, 0x2814d07c, 0x281bd012, 
+    0x49e3d153, 0x68682200, 0xf0153108, 0x1d40f948, 0xe007d071, 0xd06f2907, 0xd0032908, 0xd06c2911, 
+    0xd1422912, 0xf04f49da, 0x686832ff, 0xf0153108, 0x1d01f965, 0x20a4d107, 0x49d5e153, 0x68682200, 
+    0xf0153108, 0x1d41f95b, 0x2801d03b, 0x4ed0d1ea, 0xf6402700, 0x36080000, 0x1000f9b6, 0xd032290f, 
+    0x8330f8df, 0xf04f2913, 0xf04f42a0, 0xf04f0901, 0xd02e0a03, 0xd1d5290a, 0x1000f9b5, 0xd05a2901, 
+    0xd07b2903, 0xd0752902, 0xd0742904, 0xd0732905, 0xd0722906, 0xd1c52907, 0xf933f000, 0x8030200b, 
+    0x80282009, 0xe0041e7a, 0xe0f1e0ae, 0xe056e041, 0x48b9e079, 0x68004631, 0xf8f1f015, 0xd0711d01, 
+    0x20a5e10b, 0xf04fe10d, 0xf7f04225, 0x802ff8d2, 0x4bb2e7a8, 0x3000f993, 0xd0032b03, 0xd0012b05, 
+    0xd1022b04, 0x781b4bae, 0x210ab143, 0xf7f0802f, 0xe797f8c0, 0xe0c9e0a9, 0xe0e7e0da, 0x4220f04f, 
+    0xf8b7f7f0, 0xfe92f7ff, 0x0000f898, 0xf8a5b170, 0x200a9000, 0x2200499e, 0x68688030, 0xf0153108, 
+    0x1d01f8be, 0xaf53f47f, 0xe0da20d2, 0xa000f8a5, 0x20d3e7ef, 0xf7ffe0d5, 0x2002fe19, 0xf86af7f7, 
+    0x200ab108, 0x200fe000, 0x80304991, 0x68682200, 0xf0153108, 0x1d01f8a4, 0x20e4d107, 0x498ce0c1, 
+    0x68682200, 0xf0153108, 0x1d40f89a, 0x20e5d1b0, 0xe003e0b7, 0xe052e021, 0xe08ae072, 0xf94bf000, 
+    0xf7f72002, 0xb108f847, 0xe000200a, 0x4980200f, 0x22008030, 0x31086868, 0xf881f015, 0xd1081d01, 
+    0xe09e20ec, 0x497ae08f, 0x68682200, 0xf0153108, 0x1d40f876, 0x20edd18c, 0xf7f0e093, 0x4979f85a, 
+    0xf8812201, 0x49789000, 0x9000f881, 0xe9d59702, 0xe9cd0104, 0x21000100, 0xf7f64610, 0xf898fa2d, 
+    0x28010000, 0x2004d00a, 0x49698028, 0x68682200, 0xf0153108, 0x1d01f854, 0xe00bd003, 0xa000f8a5, 
+    0xf240e7f3, 0xe06c1000, 0x22004961, 0x31086868, 0xf845f015, 0xd1a91d40, 0x1001f240, 0xf000e061, 
+    0xf898f89b, 0x28010000, 0x2005d00a, 0x80284958, 0x68682200, 0xf0153108, 0x1d01f832, 0xe00ad002, 
+    0xe7f32006, 0x1014f240, 0x4951e04b, 0x68682200, 0xf0153108, 0x1d40f824, 0xf240d188, 0xe0401015, 
+    0xfcbbf7ff, 0xf7f62002, 0xb108ffd5, 0xe000200a, 0x4947200f, 0x22008030, 0x31086868, 0xf80ff015, 
+    0xf47f1d01, 0xf240aec4, 0xe02a101c, 0xb034f8a4, 0xf7ffe680, 0x493efc33, 0x80282007, 0x68682200, 
+    0xf0143108, 0x1d01fffc, 0xf240d108, 0xe0181024, 0x22004937, 0x31086868, 0xfff1f014, 0xd1aa1d40, 
+    0x1025f240, 0xf240e00d, 0xe00a102e, 0x22004832, 0x3108492f, 0xf0146800, 0x1d40ffe2, 0xf240d19b, 
+    0x86a0102f, 0x2200e656, 0xb5102101, 0x3057f2af, 0xfe20f014, 0x20032108, 0xff7ef014, 0x60484924, 
+    0x4823bd10, 0x42a0f04f, 0xf640b510, 0xf9b00400, 0x46201000, 0xffadf7ef, 0x2101f240, 0xf7ef4620, 
+    0x4822ff5a, 0x4a232400, 0x80c44923, 0x80448084, 0x481f8004, 0x481d7803, 0xf87af7f9, 0xf44f2172, 
+    0xf7ef0080, 0x481dff70, 0x70042100, 0x3080f44f, 0x4010e8bd, 0xbfa0f7f6, 0x4c0db5fe, 0x0600f640, 
+    0x42a0f04f, 0xf9b44630, 0xf7ef1000, 0x10b1ff82, 0xf7ef4630, 0x4912ff30, 0x4d132001, 0x48117008, 
+    0x70287800, 0xe0212000, 0x00040253, 0x00040254, 0x000406d0, 0x0004055c, 0x00040734, 0x0004028a, 
+    0x000402ec, 0x00040259, 0x00040255, 0x00040590, 0x000405d9, 0x00040578, 0x000405a6, 0x000405ae, 
+    0x00040257, 0x0004024e, 0x0004024f, 0x22019002, 0x0104e9d4, 0x0100e9cd, 0x46104611, 0xf92cf7f6, 
+    0x22034c30, 0x21384f30, 0x78234638, 0xfad1f019, 0x2200782b, 0x46382107, 0xfacbf019, 0x46307829, 
+    0xfed8f7ef, 0x46307821, 0xfed4f7ef, 0x40fee8bd, 0xf7f84826, 0xe92dbfee, 0xf00a41f0, 0x4924ff5f, 
+    0xf0194824, 0x4c24f88b, 0xf6402801, 0xd0170600, 0x463021e2, 0xfecff7ef, 0x46302100, 0xfebaf7ef, 
+    0x01d0f242, 0xf7ef4630, 0x7820fed2, 0xd0262801, 0x481a2100, 0x41f0e8bd, 0x312df201, 0xba7ff019, 
+    0x78004817, 0xfc54f7fd, 0x79a84d12, 0x481509c1, 0xd0117001, 0xf04f4f14, 0x463042a0, 0x1000f9b7, 
+    0xfef7f7ef, 0x79a84911, 0x1002f3c0, 0x78207008, 0xd0022801, 0x80382001, 0x2004e4c3, 0xf242e7fb, 
+    0xe7d67110, 0x0004024d, 0xf203501a, 0x00040588, 0x0002d000, 0x00041448, 0x0004055c, 0xf23c80ba, 
+    0x000405d9, 0x00040256, 0x000406d0, 0x0004024e, 0x4ff0e92d, 0xf649b087, 0xf04f4740, 0x48fe42c0, 
+    0x1002f9b0, 0x0000f241, 0xfec3f7ef, 0xa3ecf8df, 0x4900f04f, 0xf04f4cfa, 0x4dfa0800, 0x0000f89a, 
+    0xd1362804, 0xbba07820, 0xb9087828, 0xfacff7fc, 0xb3d4f8df, 0x21012600, 0x8010f8cd, 0x460b200e, 
+    0x1802e9cd, 0x46029000, 0xf8cd4601, 0x90018014, 0x1000f240, 0xfd22f7f7, 0x01c0f242, 0xf7ef4648, 
+    0x2e01fe56, 0x48e8dd11, 0xfeb1f7f8, 0x1000f8db, 0x42b94658, 0x6841d209, 0xd20642b9, 0x42b96881, 
+    0xf8dbd203, 0x42b8000c, 0x1c76d303, 0x2e10b236, 0x49dedbd1, 0x22012000, 0x8000f881, 0xe9cd4611, 
+    0x46100000, 0x8008f8cd, 0xf856f7f6, 0xf6404ed8, 0x46400800, 0xf7f67831, 0xf242fe7f, 0x46480b80, 
+    0xf7ef4659, 0xf99afe24, 0x46571000, 0xd01d2902, 0x48d0b1f9, 0xd00d2903, 0xd0142904, 0xd00c2903, 
+    0xd10d2904, 0x28017820, 0x2903d10a, 0x2904d03d, 0xe047d042, 0x2a017802, 0x7800d008, 0xd0f42800, 
+    0xe8bdb007, 0x78208ff0, 0xd1eb2800, 0xf0032007, 0x7831fc01, 0xf7f64640, 0x4659fe4f, 0xf7ef4648, 
+    0xf997fdf6, 0x29031000, 0x2902d012, 0x2904d010, 0x48b9d00e, 0x28116800, 0x7828d80a, 0xd1072801, 
+    0xf8ad2047, 0x48b50000, 0x46686802, 0xf977f013, 0x28007828, 0xf7fcd1d4, 0x48b1fb2e, 0x0000f990, 
+    0xe8bdb007, 0xf7fc4ff0, 0x204ab885, 0x0000f8ad, 0xf0124668, 0xe005ff54, 0xf8ad204d, 0x46680000, 
+    0xfb6af013, 0xf0032007, 0x7831fbc5, 0xf7f64640, 0xe7b5fe13, 0x4ffee92d, 0x250048a2, 0x4f97499b, 
+    0x20017005, 0xf9977008, 0xb1580000, 0x4c9e2120, 0x7680f04f, 0x1af4f240, 0x499c8021, 0x29047809, 
+    0xe012d003, 0x2100f240, 0xb170e7f1, 0x46512010, 0x46308020, 0xfd8ff7ef, 0x31baf64b, 0xf7ef4630, 
+    0x4993fd79, 0xf7ef4630, 0x4892fd75, 0x28027800, 0x01c0d101, 0xf8df8020, 0xf8dbb220, 0x28100000, 
+    0x2000d802, 0xfa34f7f7, 0x95022100, 0x46102201, 0x1100e9cd, 0xf7f54611, 0x2101ff9f, 0xf7f72000, 
+    0x7838fee1, 0x200fb910, 0xff7bf7f5, 0x0180f242, 0xf7ef0608, 0xf8dffd6c, 0xf8df81dc, 0x4c7e91c4, 
+    0xf7f62002, 0x4605fd71, 0x0000f997, 0xd0022803, 0xd0042804, 0xf898e007, 0xb1580000, 0xf899e003, 
+    0x28010000, 0x2000d006, 0xfa0ff00a, 0x28037838, 0xe021d004, 0xf00a2001, 0xe7f7fa80, 0x46304651, 
+    0xfd39f7ef, 0x41ccf64c, 0xf7ef4630, 0x7a61fd23, 0xf7ef4630, 0x7a21fd1f, 0xf7ef4630, 0x79e1fd1b, 
+    0xf7ef4630, 0x4962fd17, 0xf7ef4630, 0xf242fd13, 0x06080180, 0xfd2bf7ef, 0x289279e0, 0x2002d1c0, 
+    0xfd32f7f6, 0x1a287a22, 0xa12cf8df, 0xf0027a61, 0x4d5a0203, 0x2102ea41, 0x2004f8da, 0xeba11a80, 
+    0x80283010, 0xf7f72000, 0xe005f9c3, 0xf00a2000, 0x8828fa44, 0x80281e40, 0x28018828, 0xf242d8f6, 
+    0x060d0180, 0xf7ef4628, 0xf8dbfd02, 0x28110000, 0x2003d803, 0xfce8f00c, 0x2004e002, 0xfce6f00c, 
+    0x0180f242, 0x462846ab, 0xfcf1f7ef, 0xf7f52001, 0xf997fef8, 0x28030000, 0x2804d002, 0xe01dd004, 
+    0x0000f898, 0xe019b120, 0x0000f899, 0xd1152801, 0x25004f3b, 0xeb072400, 0x46211645, 0xf9364628, 
+    0xf00c2014, 0x1c64fe94, 0x2c10b2e4, 0x1c6dd3f5, 0x2d04b2ed, 0x2003d3ee, 0xfe9af00c, 0x0180f242, 
+    0xf7ef4658, 0xf9bafcc4, 0xb0031002, 0x42c0f04f, 0x0000f241, 0x4ff0e8bd, 0xbcfbf7ef, 0x4ffee92d, 
+    0xf9964e16, 0xb1380000, 0x49202410, 0x7580f04f, 0x29047809, 0xe011d002, 0xe7f62440, 0x2408b170, 
+    0x11f4f240, 0xf7ef4628, 0xf64bfc96, 0x462831ba, 0xfc80f7ef, 0x46284916, 0xfc7cf7ef, 0x78004815, 
+    0xd1002802, 0xf9962440, 0x4f0a0000, 0x8010f8df, 0xd0292803, 0xe0252804, 0x000406e8, 0x00040f44, 
+    0x000405c5, 0x0004055c, 0x00041458, 0x00040269, 0x0004028b, 0x000405c3, 0x00040238, 0x00040f64, 
+    0x00040290, 0x00040267, 0x0004026e, 0x0004028a, 0xdcba01f5, 0x000405ae, 0x00041448, 0x00040270, 
+    0x0004e1f0, 0xe006d003, 0xb1687838, 0xf898e003, 0x28010000, 0x2000d008, 0xf917f00a, 0x46b17830, 
+    0x28034efd, 0xe022d004, 0xf00a2001, 0xe7f5f986, 0x11f4f240, 0xf7ef4628, 0xf64cfc3e, 0x462841cc, 
+    0xfc28f7ef, 0x46287a71, 0xfc24f7ef, 0x46287a31, 0xfc20f7ef, 0x462879f1, 0xfc1cf7ef, 0x462849ef, 
+    0xfc18f7ef, 0x0180f242, 0xf7ef0608, 0x49ecfc30, 0xf01848e9, 0x2801fdd3, 0x4cead054, 0x0700f241, 
+    0x682021e2, 0x60201c40, 0xf7ef4638, 0x6821fc14, 0xf7ef4638, 0xf242fbff, 0x463801d0, 0xfc17f7ef, 
+    0x11f4f240, 0xf7ef4628, 0xf64ffc06, 0x46282111, 0xfbf0f7ef, 0x683178f0, 0x611ff360, 0xf7ef4628, 
+    0x79f0fbe9, 0xf3606871, 0x4628611f, 0xfbe2f7ef, 0x68b17af0, 0x611ff360, 0xf7ef4628, 0x7bf0fbdb, 
+    0xf36068f1, 0x4628611f, 0xfbd4f7ef, 0x462849cb, 0xfbd0f7ef, 0x780048cc, 0xd07d2801, 0x48cb2100, 
+    0x714cf501, 0xff9bf018, 0x49ca48c9, 0xf0007800, 0xeb000007, 0xf8511000, 0x1c522020, 0x2020f841, 
+    0x8ffee8bd, 0xb310f8df, 0x79f046ca, 0x0140f3c0, 0x1000f88b, 0x0000f899, 0xf240b188, 0x462811f4, 
+    0xfbb9f7ef, 0x21acf64a, 0xf7ef4628, 0x79f1fba3, 0xf7ef4628, 0x49b1fb9f, 0xf7ef4628, 0xf89bfb9b, 
+    0x28010000, 0x46b1d1dc, 0x4eb47a70, 0x1008f899, 0x0103f001, 0x2001ea40, 0xf89a8030, 0xb1a80000, 
+    0x11f4f240, 0xf7ef4628, 0xf64afb96, 0x462821ab, 0xfb80f7ef, 0x46288831, 0xfb7cf7ef, 0x46284621, 
+    0xfb78f7ef, 0x4628499d, 0xfb74f7ef, 0x42a08830, 0x2002ddb6, 0xfb98f7f6, 0x48a14601, 0x68004ca2, 
+    0x49a01a43, 0x2000f9b1, 0xf1f2fbb3, 0x60211cc9, 0x43511e89, 0xfbd6f7f6, 0x2001499c, 0x700846b3, 
+    0x88218830, 0x499a1a40, 0x20008008, 0x90022201, 0xe9cd4611, 0xe0000000, 0x4610e0e9, 0xfd8cf7f5, 
+    0x20002101, 0xfccef7f7, 0xfcfbf7f8, 0x0000f89a, 0xb9104656, 0xf7f5200f, 0xf242fd64, 0x06080180, 
+    0xfb55f7ef, 0xb9607830, 0x21004c8a, 0xf994200c, 0xf7f82000, 0x2101fced, 0x2000f994, 0xf7f84608, 
+    0x2002fd2d, 0xfb50f7f6, 0xf9964604, 0x46b20000, 0xd0022803, 0xd0032804, 0x7838e006, 0xe003b3f0, 
+    0x0000f898, 0xd0432801, 0xf0092000, 0x2002ffee, 0xfb3af7f6, 0x2008f899, 0xf8991a21, 0x464e0009, 
+    0x91d4f8df, 0x0203f002, 0xea40465c, 0xf8d92002, 0x1a892004, 0x3011eba0, 0x11f4f240, 0x0000f8ab, 
+    0xf7ef4628, 0xf64bfb08, 0x462831bb, 0xfaf2f7ef, 0x46287a71, 0xfaeef7ef, 0x46287a31, 0xfaeaf7ef, 
+    0x462879f1, 0xfae6f7ef, 0x46284954, 0xfae2f7ef, 0x0000f89a, 0x28044655, 0xe000d014, 0xf44fe008, 
+    0xf6403000, 0xf7ef0103, 0xf7fbfae6, 0xe009fd7f, 0xf00a2001, 0xe7baf822, 0xf00a2000, 0x8820f81e, 
+    0x80201e40, 0x28018820, 0x7828d8f6, 0xd1062804, 0xf64003c0, 0xf7ef0103, 0xf7fbface, 0xf04ffd67, 
+    0xf2424a00, 0x465c0b80, 0x46564659, 0xf7ef4650, 0x2004face, 0xfabaf00c, 0x46304621, 0xfac7f7ef, 
+    0xf7f52001, 0xf995fcce, 0x28030000, 0x2804d002, 0xe01cd003, 0xb1207838, 0xf898e019, 0x28010000, 
+    0x4f3ed115, 0x24002500, 0x1645eb07, 0x46284621, 0x2014f936, 0xfc6bf00c, 0xb2e41c64, 0xd3f52c10, 
+    0xb2ed1c6d, 0xd3ee2d04, 0xf00c2003, 0x4834fc71, 0x28027800, 0x0400d10b, 0x0103f640, 0xfa8bf7ef, 
+    0xfd24f7fb, 0xf018482f, 0x492ffe41, 0x46596008, 0xf7ef4650, 0xf9b9fa8c, 0xf04f1002, 0x464c42c0, 
+    0x0000f241, 0xfac5f7ef, 0x8060200b, 0xf242e6a8, 0xe6947110, 0x4820b53e, 0x0400f241, 0x42c0f04f, 
+    0x1002f9b0, 0xf7ef4620, 0x2104fab4, 0xf7ef4620, 0x491efa62, 0x78094620, 0xfabef7f6, 0xf00c2000, 
+    0x481bfbf5, 0x0000f990, 0x2802b3a0, 0x2803d03b, 0x2804d031, 0xe039d034, 0x00041448, 0xdcba01f5, 
+    0x0002d000, 0x000402e4, 0x0004055c, 0xf23c80ba, 0x00040f60, 0x00041708, 0x0004026a, 0x00040270, 
+    0x00040278, 0x000405e8, 0x0004056c, 0x00040269, 0x0004026e, 0x00040290, 0x000406e8, 0x0004e1f0, 
+    0x000405ae, 0xf000812c, 0x000405b0, 0x0004028b, 0x00040f44, 0x48fde007, 0x28017800, 0xe005d003, 
+    0x780048fb, 0x2003b910, 0xfbf2f00c, 0x0180f242, 0xf7ef0608, 0x48f7fa1c, 0x49f72400, 0x70044df7, 
+    0x70082001, 0x2002e00e, 0xfa24f7f6, 0xd0092801, 0x46284df3, 0xfdc0f018, 0x0140f040, 0xf0184628, 
+    0xe006fdbe, 0x46282200, 0xf0182101, 0x2800fdc9, 0x2100d1e9, 0x22019402, 0xe9cd4610, 0x46111100, 
+    0xfc1af7f5, 0x403ee8bd, 0xbe7af009, 0x5ff0e92d, 0x9390f8df, 0x0b00f04f, 0x465d465c, 0xf99946da, 
+    0x28030000, 0x2804d002, 0xe007d004, 0x780048d7, 0xe003b168, 0x780048d6, 0xd0082801, 0xf0092001, 
+    0x4fd9fe94, 0x78382601, 0xd0042801, 0x2001e02b, 0xff03f009, 0xf899e7f5, 0xbb200000, 0xf7f848d3, 
+    0x48d3fa26, 0x78004ad1, 0xd1102803, 0xf99048d1, 0xf9901000, 0xf8523002, 0xf8421021, 0xf9901023, 
+    0xf9901001, 0xf8520003, 0xf8421021, 0x49ca1020, 0xf8522000, 0x428b3020, 0x2600d900, 0xb2c01c40, 
+    0xd3f62804, 0x49c5b12e, 0xf01848c5, 0x2801fb47, 0x4cc4d008, 0x1c406820, 0xf3c06020, 0x28010008, 
+    0xe1c5d077, 0x82f8f8df, 0xf89849bf, 0xf3c00007, 0x70080080, 0xd06d2800, 0xf89849bc, 0xf8df0009, 
+    0xf8dfc2f4, 0x0982e2f4, 0x49b9700a, 0x1201f3c0, 0xf000700a, 0xf3c00103, 0x48b80281, 0x2000f88c, 
+    0x1000f88e, 0x2b017803, 0xf898d122, 0xf8980008, 0xf000600a, 0xf000000f, 0xea460701, 0xf3c02607, 
+    0xf3660740, 0xf898040f, 0xea46600b, 0xf3c02607, 0xf3660780, 0xf898441f, 0x08c0600c, 0x2607ea46, 
+    0x050ff366, 0x600df898, 0x2000ea46, 0x451ff360, 0x780048a3, 0xd1034282, 0x780048a2, 0xd07c4281, 
+    0x1e491e52, 0x0703f002, 0x0f060788, 0xf240b31b, 0xb2a21100, 0x428a1c48, 0xf360d101, 0x0c22040f, 
+    0xd101428a, 0x441ff360, 0x428ab2aa, 0xf360d101, 0x0c2a050f, 0xd101428a, 0x451ff360, 0x0000f999, 
+    0xd0722802, 0xd0702800, 0xd0712803, 0xd0742804, 0xe13ee076, 0xf898e134, 0x2081100a, 0xd1012980, 
+    0x000af888, 0x100bf898, 0xd1012980, 0x000bf888, 0x100cf898, 0xd1012980, 0x000cf888, 0x100df898, 
+    0xd1012980, 0x000df888, 0x0000f999, 0xd0252802, 0x2803b320, 0x4865d103, 0x28017800, 0xf898d01e, 
+    0x2108000a, 0xfc08f019, 0x48774241, 0x1447eb00, 0x1016f824, 0x000bf898, 0xf0192108, 0xeb04fbfd, 
+    0x42400446, 0x80602108, 0x000cf898, 0xfbf4f019, 0x80a04240, 0x000df898, 0xe04b2108, 0x000af898, 
+    0xf0192108, 0x4240fbe9, 0xb2024631, 0xf00c4638, 0xf898fa8e, 0x2108000b, 0xe04fe000, 0xfbdcf019, 
+    0xb2024240, 0x1c714638, 0xfa81f00c, 0x000cf898, 0xf0192108, 0x4240fbd1, 0x4638b202, 0xf00c1cb1, 
+    0xf898fa76, 0x2108000d, 0xe038e05a, 0xe004e000, 0x7800483e, 0xd0332801, 0x483de002, 0xb3707800, 
+    0x2109b220, 0xfbb8f019, 0x484f4241, 0x1747eb00, 0xf8271420, 0x21091016, 0xfbaef019, 0x0446eb07, 
+    0x21094240, 0xb2288060, 0xfba6f019, 0x80a04240, 0x21091428, 0xfba0f019, 0x80e04240, 0x78184b43, 
+    0xd0382801, 0xf04f483b, 0x493d0a01, 0x78004a3d, 0x49397008, 0x70117809, 0xd02a4308, 0xe7ffe02b, 
+    0x2109b220, 0xfb88f019, 0x46314240, 0x4638b202, 0xfa2df00c, 0x21091420, 0xfb7ef019, 0xb2024240, 
+    0x1c714638, 0xfa23f00c, 0x2109b228, 0xfb74f019, 0xb2024240, 0x1cb14638, 0xfa19f00c, 0x21091428, 
+    0xfb6af019, 0xb2024240, 0x1cf14638, 0xfa0ff00c, 0x2001e7c4, 0x4e267018, 0x28017830, 0x481bd05b, 
+    0x78004c24, 0x42887821, 0x4a19d155, 0x78134d22, 0x4293782a, 0x4318d14f, 0x1c52d040, 0x7028b2d0, 
+    0xd33e2804, 0xb000f885, 0x0000e048, 0x000405c3, 0x000405c5, 0x00040264, 0x00040266, 0xf000801c, 
+    0xf203517c, 0x00040f44, 0x0004055c, 0x00041458, 0x000405d9, 0x00040578, 0x0001a02b, 0x0002d000, 
+    0x00041448, 0x000402e4, 0x00040265, 0x00040260, 0x00040261, 0x00040262, 0x00040263, 0x000402fa, 
+    0x0004025c, 0x0004025d, 0x0004e1f0, 0x00040275, 0x00040274, 0x0004025e, 0x0004025f, 0x70302001, 
+    0x2801e00c, 0x1c49d10a, 0x7020b2c8, 0xd3052804, 0xb000f884, 0xf1bae002, 0xd0080f00, 0xe0042107, 
+    0x780048fd, 0xd0022800, 0x48fc2108, 0xe8bd8041, 0xf2419ff0, 0x21e20500, 0xf7ee4628, 0x6821ffcc, 
+    0xf7ee4628, 0xf242ffb7, 0x462801d0, 0xffcff7ee, 0x28017838, 0x2100d01d, 0xf20148f1, 0xf018312f, 
+    0x48f0fb7e, 0x780049f0, 0x0007f000, 0x1000eb00, 0x2020f851, 0xf8411c52, 0xf8992020, 0x28000000, 
+    0x6820d1d5, 0xdbd2280a, 0x28017838, 0x2110d1cf, 0xf242e7cb, 0xe7df7110, 0x48e0b5fe, 0x42c0f04f, 
+    0x1002f9b0, 0x0000f241, 0xffe3f7ee, 0x25004edf, 0xb1687830, 0x0180f242, 0xf7ee0608, 0x48d9ff98, 
+    0x780049d9, 0x0007f000, 0x1000eb00, 0x5020f841, 0x200149d7, 0x70084cdc, 0x700849d6, 0x700d49d6, 
+    0x700d49d6, 0x700849d6, 0x700849d6, 0x0000f996, 0xd0022803, 0xd0042804, 0x48d4e007, 0xb3e87800, 
+    0x48d3e003, 0x28017800, 0x2000d043, 0xf860f00a, 0xb24049cd, 0xfecbf7f4, 0xf00a2001, 0x49caf859, 
+    0x3120b240, 0xfec3f7f4, 0xf00a2002, 0x49c6f851, 0x3140b240, 0xfebbf7f4, 0xf00a2003, 0x49c2f849, 
+    0x3160b240, 0xfeb3f7f4, 0x88a088e1, 0x0108f3c1, 0x0008f3c0, 0x4101ea40, 0xf3c08860, 0x0fc20008, 
+    0x04030412, 0x4210ea42, 0x43118820, 0xf3c09502, 0x43030008, 0xea412201, 0xe00071d0, 0xe9cde009, 
+    0x46113100, 0xf7f54610, 0x7830f957, 0xb1a84cb1, 0xf8dfe01e, 0x2100c2c4, 0xeb0c2000, 0xeb041741, 
+    0xf8371241, 0xf8223010, 0x1c403010, 0x2810b200, 0x1c49dbf7, 0x2904b2c9, 0xe7c5d3ee, 0x0000f994, 
+    0xf7f449a1, 0x4aa5fe74, 0x489f2104, 0xf99cf018, 0x0000f994, 0x40fee8bd, 0xbb68f009, 0x43f0e92d, 
+    0xf241488e, 0xb0870900, 0x42c0f04f, 0x1002f9b0, 0xf7ee4648, 0xf7f8ff3e, 0xf242fb12, 0x06cf0150, 
+    0xf7ee4638, 0x4896fef4, 0xf2422600, 0x78000570, 0xd0132803, 0xf04f4c93, 0x4611020c, 0x28037820, 
+    0x0df8d01a, 0xfd1af7f6, 0x462946a8, 0x4638463d, 0xfeddf7ee, 0x78384f8c, 0xe012b188, 0xf2402300, 
+    0x1e5a2000, 0x210e9600, 0xf7f69601, 0xf7fbfc50, 0x4629fb2e, 0xe03b4638, 0x0000f640, 0xf7fbe7e2, 
+    0x2001fb26, 0xe9cd9604, 0x200c0602, 0x23019000, 0x220e9605, 0x03589001, 0xf7f64611, 0x4646fd7f, 
+    0x46284641, 0xfeb3f7ee, 0xb9c87838, 0x2000f994, 0xd0012a04, 0xd1132a05, 0x78004864, 0x2100b980, 
+    0xf7f82001, 0x4c71fade, 0x200c2100, 0x2000f994, 0xf83ef7f8, 0xf9942101, 0x46082000, 0xf87ef7f8, 
+    0x220c2301, 0x200e4619, 0xfe27f7f6, 0x46284631, 0xfe8df7ee, 0xf44f4866, 0xf7f731b8, 0x2800fefb, 
+    0xf240d010, 0x464c11f4, 0xf7ee4648, 0x4961fe74, 0xf7ee4620, 0xb007fe5f, 0x495f4620, 0x43f0e8bd, 
+    0xbe58f7ee, 0xe8bdb007, 0x484483f0, 0x42c0f04f, 0xf9b0b510, 0xf2411002, 0xf7ee0000, 0x4c52feaa, 
+    0xb9087820, 0xfb08f004, 0x28017820, 0xf004d101, 0xf7f8fb03, 0xe8bdfb8b, 0xf0044010, 0xe92dbb4c, 
+    0x4c364ff0, 0xf04fb087, 0xf24142c0, 0xf9b40000, 0xf7ee1002, 0x4d44fe8e, 0x28017828, 0x4847d110, 
+    0xf44f7801, 0xf7f52080, 0x2000fe97, 0xfaf0f7f6, 0x3000f44f, 0x0103f640, 0xfe2df7ee, 0xf8c6f7fb, 
+    0x4a00f04f, 0x0980f242, 0x46504649, 0xfe2ff7ee, 0x2701483b, 0xf04f260c, 0x68000800, 0xd2022811, 
+    0x28017828, 0x2301d111, 0x220d9600, 0x8010f8cd, 0x46110258, 0x7802e9cd, 0x8014f8cd, 0xf7f69601, 
+    0x4649fcdd, 0xf7ee4650, 0x2100fe12, 0xf0072001, 0x7828fd41, 0xb1f046ab, 0x0000f994, 0x220d2301, 
+    0x46119600, 0x96019004, 0x7002e9cd, 0x02989005, 0xfcc4f7f6, 0x46504649, 0xfdf9f7ee, 0x0000f994, 
+    0x220e2301, 0x46119600, 0x96019004, 0x7002e9cd, 0x03589005, 0xe035e087, 0x00040275, 0x000406e8, 
+    0xf23c80ba, 0x00040f60, 0x00041708, 0x00040f44, 0x00040247, 0x00040264, 0x0004025c, 0x0004025d, 
+    0x0004025e, 0x0004025f, 0x000412c8, 0x000405c3, 0x000405c5, 0x00040570, 0x000414f8, 0x00041348, 
+    0x0004027c, 0x0004028a, 0x0004055c, 0x00040290, 0x00041458, 0x77777771, 0xdcba01f5, 0x0004028b, 
+    0x00040238, 0xfa13f7fb, 0x780148fa, 0x3080f44f, 0xfe02f7f5, 0x96002301, 0x4645220d, 0x46110298, 
+    0x7802e9cd, 0x8010f8cd, 0x8014f8cd, 0xf7f69601, 0x4649fc65, 0xf7ee4650, 0x220efd9a, 0x0800f241, 
+    0x23019600, 0x7502e9cd, 0x46404611, 0x96019504, 0xf7f69505, 0x4649fc53, 0xf7ee4650, 0xf7fbfd88, 
+    0x48e5f9e6, 0xb9907800, 0xb1807820, 0x20012100, 0xf9b7f7f8, 0x21004de1, 0xf995200c, 0xf7f72000, 
+    0x2101ff17, 0x2000f995, 0xf7f74608, 0xf994ff57, 0x220e0000, 0x23019600, 0x90044611, 0xe9cd9601, 
+    0x90057002, 0xf7f64640, 0x46c8fc29, 0x46554649, 0xf7ee4650, 0x2100fd5c, 0xf0074608, 0x4641fc8b, 
+    0xf7ee4628, 0xf89bfd54, 0xf04f0000, 0x46d9020e, 0x0301f04f, 0xf9942800, 0x96000000, 0x90044611, 
+    0xe9cd9601, 0x90057002, 0x0358d030, 0xfc06f7f6, 0x46414644, 0xf7ee4628, 0x48c1fd3a, 0x3190f44f, 
+    0xfda8f7f7, 0xf241b170, 0xf2400600, 0x463011f4, 0xfd21f7ee, 0x463049bb, 0xfd0cf7ee, 0x463049ba, 
+    0xfd08f7ee, 0xf8992301, 0x220c0000, 0x200e4619, 0xfcb3f7f6, 0xf44f2100, 0xf7f51000, 0xb007fd6d, 
+    0x46284621, 0x4ff0e8bd, 0xbd11f7ee, 0x0000f244, 0xe92de7cc, 0x4ead5ff0, 0x42c0f04f, 0x0000f241, 
+    0x1002f9b6, 0xfd45f7ee, 0x4900f04f, 0x0470f242, 0x46484621, 0xfcfbf7ee, 0xf04f4fa5, 0x7838080e, 
+    0xd1792801, 0xfcd8f7f6, 0x22112300, 0x3100f44f, 0x4071f04f, 0xf8a6f018, 0xf7f62001, 0x489df999, 
+    0xf894f018, 0x6809499c, 0xd8012910, 0xe000499b, 0xf8df2100, 0x46a2b260, 0x1a454c8e, 0x0b0cf1ab, 
+    0x46484651, 0xfcd3f7ee, 0xf7f62000, 0xf00af981, 0xb1a0f845, 0x4080f500, 0x10407821, 0xfea9f7f6, 
+    0x2201488f, 0xf9b07823, 0x20001000, 0xff5bf7f6, 0xf7f62001, 0x7821f96d, 0x2080f44f, 0x2001e005, 
+    0xf966f7f6, 0xf44f7821, 0xf7f53080, 0x2201fd05, 0x21024658, 0xf874f018, 0xd0182801, 0x2200487d, 
+    0x38082101, 0xf86cf018, 0xd0102801, 0xf0184879, 0x42a8f84d, 0x2001d8c4, 0xf94af7f6, 0xf44f7821, 
+    0xf7f52080, 0x7838fce9, 0xd00a2801, 0x4d75e014, 0xf0184628, 0xf040f841, 0x46280110, 0xf83ff018, 
+    0xf009e7e9, 0x4970fcfb, 0xf0174870, 0x2801fe27, 0x2010d002, 0xe49a8070, 0x8002f8a6, 0xe92de497, 
+    0x486b47fc, 0x78014d6b, 0xb1097828, 0xd3022832, 0x78094969, 0x2101b101, 0x4c694e68, 0x7031282d, 
+    0x1000f994, 0x2904d201, 0x284bd023, 0x2905d201, 0x2700d01f, 0x918cf8df, 0x3800f240, 0x46412300, 
+    0x46482208, 0xf825f018, 0x28017830, 0x2f00d001, 0x484ed05e, 0x42c0f04f, 0x1002f9b0, 0x0000f241, 
+    0xfc87f7ee, 0xf7f62000, 0x4849f8f3, 0xb1107800, 0x2701e009, 0xf44fe7de, 0xf6403000, 0xf7ee0103, 
+    0xf7fafc2a, 0x7830fec3, 0xd0062801, 0x0000f994, 0xd0192804, 0xd0232805, 0x7820e031, 0xd12e2803, 
+    0x46412301, 0x46482208, 0xfff3f017, 0x1000f240, 0x0006f8ad, 0x0002f8ad, 0x0004f8ad, 0x0000f8ad, 
+    0xf7f74668, 0xe01afc99, 0x280f7828, 0x220dd203, 0x20062100, 0x380fe011, 0xd210281e, 0xe003220b, 
+    0x280f7828, 0x220dd203, 0x20032100, 0x380fe005, 0xd204285f, 0x2100220b, 0xf7f92002, 0x2100fb6b, 
+    0xf0072001, 0x2100fb27, 0x2080f44f, 0xfc44f7f5, 0x87fce8bd, 0x4c1db53e, 0x42c0f04f, 0x0000f241, 
+    0x1002f9b4, 0xfc25f7ee, 0x20004927, 0x70084a27, 0x70112102, 0xe9cd2201, 0x46110000, 0x46109002, 
+    0xfdfaf7f4, 0x490c4812, 0xf9917800, 0x43081000, 0x2000d03e, 0xf6407020, 0x60603040, 0xf9904818, 
+    0x28040000, 0x2805d036, 0xf241d102, 0x60606080, 0x0000bd3e, 0x0004028b, 0x00040f44, 0x00040290, 
+    0x00041458, 0x77777772, 0xdcba01f5, 0x000406e8, 0x0004055c, 0xf000812c, 0x00040238, 0x01e84800, 
+    0x00040560, 0xf203517c, 0x0002d000, 0x00041448, 0x000402f4, 0x0004055e, 0x000402f5, 0x0004033d, 
+    0x0004028a, 0xf203e800, 0x00040267, 0x00040246, 0xe7bf2001, 0x5000f642, 0xe92de7c9, 0x4dfa5ff0, 
+    0x1b4df240, 0x46048e81, 0xa3e0f8df, 0x68ab4559, 0x104df2a1, 0xdc4cd03d, 0x7f93f5b1, 0xdc20d075, 
+    0x1207f240, 0xf2a14291, 0xd0781007, 0xb381dc10, 0xd06b29d8, 0xd06a29d9, 0x7f83f5b1, 0x2200d168, 
+    0xf1054618, 0xf013010c, 0x1d40fbba, 0xe066d072, 0xd0702811, 0xd0622812, 0xd06d2819, 0xd157281a, 
+    0xf240e05d, 0x42911233, 0x1033f2a1, 0xdc11d057, 0x010cf110, 0x2905d053, 0x2906d07e, 0x290bd04f, 
+    0x49d9d146, 0x46182200, 0xf013310c, 0x1d40fb98, 0xe044d073, 0xd0712805, 0xd0402806, 0xd1372819, 
+    0x220049d1, 0x310c4618, 0xfb89f013, 0xd0661d40, 0x2846e035, 0xdc1cd033, 0xd07d2829, 0x2807dc08, 
+    0x2808d07b, 0x281fd02b, 0x2820d078, 0xe026d120, 0xd024282a, 0xd0722831, 0xd0202832, 0xd1172845, 
+    0x220049c1, 0x310c4618, 0xfb69f013, 0xd0671d40, 0x2869e015, 0xdc0cd07d, 0xd07b2859, 0xd00e285a, 
+    0xd0782861, 0xd1032862, 0xe0ffe009, 0xe01ee015, 0x286ae073, 0x2873d003, 0x2874d06e, 0x49b2d16d, 
+    0x32fff04f, 0x310c68a8, 0xfb78f013, 0xd10a1d01, 0xe25c20d8, 0xe0b6e096, 0x49abe0d0, 0x46182200, 
+    0xf013310c, 0x1d41fb6b, 0x2801d058, 0x4ea6d1e7, 0xf2412700, 0x360c0000, 0x1000f9b6, 0xd04f290f, 
+    0x29144ba3, 0x828cf8df, 0x42c0f04f, 0x090af04f, 0x290ad04c, 0xe003d1d3, 0xe0fce0e0, 0xe12fe10b, 
+    0x1002f9b5, 0xd0792913, 0xd06f2901, 0xd06e2902, 0xd06d2910, 0xd06c2911, 0xd06b2912, 0xd06a2903, 
+    0xd069290e, 0xd068290f, 0x29042706, 0x2906d075, 0x2907d074, 0xe004d073, 0xe12fe173, 0xe18ee15a, 
+    0x2908e1b0, 0x2909d06c, 0x270bd06b, 0xd069290a, 0xd1a4290b, 0xfc0cf7fe, 0x200c8037, 0xf04f8068, 
+    0xf8da32ff, 0x46310000, 0xfae9f013, 0xd0741d01, 0xe1e5e1f9, 0xe1cce1af, 0xe0f3e1ef, 0xe1f620d9, 
+    0x4226f04f, 0xfac5f7ee, 0xe788806f, 0x3000f993, 0xd0032b03, 0xd0012b05, 0xd1022b04, 0x781b4b76, 
+    0x210db123, 0xf7ee806f, 0xe778fab4, 0x4220f04f, 0xfaaff7ee, 0xfe7ef7ff, 0x0000f898, 0xd00f2803, 
+    0x49692013, 0x22008068, 0x9000f8a6, 0x68a8310c, 0xfab5f013, 0xf47f1d01, 0xf240aef8, 0xe1c61006, 
+    0xe7ee200e, 0x1007f240, 0xe007e1c1, 0xe040e026, 0xe06ee057, 0xe099e082, 0xe0d9e0c2, 0xfdcff7ff, 
+    0x20014959, 0x22008068, 0x310c68a8, 0xfa97f013, 0xd10e1d01, 0x1018f240, 0xe0f5e1a9, 0xe128e10b, 
+    0xe162e143, 0x4950e17f, 0x46182200, 0xf013310c, 0x1d40fa86, 0xf240d1a9, 0xe1981019, 0xfa4bf000, 
+    0x20024949, 0x22008068, 0x310c68a8, 0xfa77f013, 0xd1091d01, 0x1020f240, 0xe17be189, 0x22004942, 
+    0x310c4618, 0xfa6bf013, 0xd18e1d40, 0x1021f240, 0xf7ffe17d, 0x493cfcfe, 0x68a82200, 0xf013310c, 
+    0x1d01fa5e, 0xf240d108, 0xe1701026, 0x22004936, 0x310c4618, 0xfa53f013, 0xd1861d40, 0x1027f240, 
+    0xf000e165, 0x4930f9df, 0x68a82200, 0xf013310c, 0x1d01fa46, 0xf240d108, 0xe158102c, 0x2200492a, 
+    0x310c4618, 0xfa3bf013, 0xd1b31d40, 0x102df240, 0xf7eee14d, 0xf004fa1e, 0x4923f99a, 0x80682012, 
+    0x68a82200, 0xf013310c, 0x1d01fa2a, 0xae8ff47f, 0x1032f240, 0xf240e13b, 0xe1381033, 0xf991f000, 
+    0x22004919, 0x310c68a8, 0xfa19f013, 0xd1081d01, 0x1038f240, 0x4914e12b, 0x46182200, 0xf013310c, 
+    0x1d40fa0e, 0xf240d186, 0xe1201039, 0x0000f993, 0xd0052803, 0xd1052805, 0x68004810, 0xd8012810, 
+    0xfb4df7ff, 0x20044908, 0x22008068, 0x310c68a8, 0xf9f5f013, 0xf47f1d01, 0xf240ae69, 0xe106104c, 
+    0xb034f8a4, 0x0000e517, 0x000406e8, 0x00040734, 0x0004028a, 0x0004027c, 0x000402ec, 0x00040238, 
+    0xfb13f7ff, 0x8068200f, 0x220049fa, 0xf01368a8, 0x1d01f9d6, 0xf240d107, 0xe0e81054, 0x220049f5, 
+    0xf0134618, 0x1d40f9cc, 0xf240d18f, 0xe0de1055, 0xfa64f7ff, 0x0000f898, 0xd0092803, 0x80682003, 
+    0x220049ec, 0xf01368a8, 0x1d01f9ba, 0xe016d00f, 0xf7f52002, 0x48e8f95a, 0xf44f7801, 0xf7f51080, 
+    0x2000f9ab, 0xfe04f7f5, 0xfefcf00b, 0xf240e657, 0xe0bc106c, 0x220049df, 0xf0134618, 0x1d40f9a0, 
+    0xf240d1f4, 0xe0b2106d, 0xf996f7ff, 0x2200806f, 0x68a849d8, 0xf993f013, 0xd1071d01, 0x1076f240, 
+    0x49d4e0a5, 0x46182200, 0xf989f013, 0xd1dd1d40, 0x1077f240, 0xf7fee09b, 0x2002ff39, 0xf93af7f5, 
+    0x200ab108, 0x200fe000, 0x49ca8030, 0x68a82200, 0xf975f013, 0xd1071d01, 0x107ef240, 0x49c5e087, 
+    0x46182200, 0xf96bf013, 0xd1bf1d40, 0x107ff240, 0xf000e07d, 0x48c1f88d, 0x28017800, 0x48c0d103, 
+    0x28017800, 0x806fd00b, 0x49ba2200, 0xf01368a8, 0x1d01f956, 0xadeaf47f, 0x1092f240, 0x2008e067, 
+    0xe7f18068, 0x1093f240, 0xf7fee061, 0x48b5fe73, 0x28017800, 0x2009d009, 0x49ae8068, 0x68a82200, 
+    0xf93df013, 0xd0031d01, 0xf8a5e00a, 0xe7f49002, 0x10a6f240, 0x49a7e04b, 0x46182200, 0xf92ff013, 
+    0xd18d1d40, 0x10a7f240, 0xf7fee041, 0x2002fc17, 0xf8e0f7f5, 0x200ab108, 0x200fe000, 0x499d8030, 
+    0x68a82200, 0xf91bf013, 0xd1071d01, 0x10aef240, 0x4998e02d, 0x46182200, 0xf911f013, 0xd1861d40, 
+    0x10aff240, 0xf7fee023, 0x806ffaf5, 0x49912200, 0xf01368a8, 0x1d01f904, 0xf240d107, 0xe01610b6, 
+    0x2200498c, 0xf0134618, 0x1d40f8fa, 0xf240d18d, 0xe00c10b7, 0x10c0f240, 0x4986e009, 0xf8da2200, 
+    0xf0130000, 0x1d40f8ec, 0xf240d1bb, 0x86a010c1, 0x2200e411, 0xb5102101, 0x6001f2af, 0xff2af012, 
+    0x20032108, 0xf888f013, 0x390c497a, 0xbd106088, 0xb5fe487d, 0x4a7e7800, 0x4e7e1e40, 0x0103f000, 
+    0xeb02487a, 0x78001241, 0x07801e40, 0xeb020f00, 0xf8320140, 0x888b0010, 0xf3c088cc, 0x88490008, 
+    0x0308f3c3, 0x0408f3c4, 0x0108f3c1, 0x4404ea43, 0x041b0fcb, 0x4311ea43, 0x040d431c, 0xea444305, 
+    0xe00e74d0, 0xf7f52002, 0x2801f865, 0x4e6ad009, 0xf0174630, 0xf040fc01, 0x46300120, 0xfbfff017, 
+    0x2200e006, 0x21014630, 0xfc0af017, 0xd1e92800, 0x95002001, 0x46014602, 0x4001e9cd, 0xfa5cf7f4, 
+    0xb510bdfe, 0xf04f4c53, 0xf24142c0, 0x3c0c0000, 0x1002f9b4, 0xf86df7ee, 0xfc07f009, 0x200eb110, 
+    0xbd108060, 0x80602010, 0x49554854, 0x700a7802, 0x704a7842, 0x708a7882, 0x70c878c0, 0x4010e8bd, 
+    0xbb63f009, 0x41f0e92d, 0xf04f4c42, 0xf24142c0, 0x3c0c0000, 0x1002f9b4, 0xf84bf7ee, 0xff38f7fb, 
+    0xf7f52000, 0x4847fcb5, 0x0000f990, 0xd0031c40, 0x80602011, 0x81f0e8bd, 0xf9954d43, 0x1c400000, 
+    0xeb0017c1, 0xf0217191, 0x1a400103, 0x20007028, 0xfb6bf7fa, 0x24004f3d, 0x2600f240, 0xb1087828, 
+    0xe0004631, 0x46204639, 0xfc88f7fa, 0xb2641c64, 0xdbf32c04, 0x4827e7de, 0x380cb57c, 0x42c0f04f, 
+    0x1002f9b0, 0x0000f241, 0xf813f7ee, 0x0170f242, 0x462806cd, 0xffcbf7ed, 0x0be82100, 0xf81cf7f5, 
+    0x78214c20, 0xd1032901, 0x0ae82100, 0xf814f7f5, 0x0180f242, 0xf7ed4628, 0x4825ffba, 0x78024925, 
+    0x2a014825, 0x4a25d019, 0x2a057812, 0x2000d819, 0x0006f8ad, 0x0002f8ad, 0x0004f8ad, 0x0000f8ad, 
+    0x4a16481f, 0x7803491f, 0xf7f74668, 0x2172f8c1, 0x0080f44f, 0xffb7f7ed, 0x4a1be006, 0x2a037812, 
+    0x221ed034, 0xf896f7fc, 0x28007820, 0xf7fad101, 0xbd7cfbee, 0x000406f4, 0x0004028b, 0x00040274, 
+    0x00040275, 0x0004055c, 0x0004025e, 0x0004025f, 0x000412c8, 0xf000801c, 0xf203517c, 0x00040578, 
+    0x00040570, 0x00040276, 0x00040562, 0xfffffa00, 0x0004033d, 0x450f6429, 0x43e187ae, 0x0004055e, 
+    0x000405d9, 0x000405a6, 0x0004028a, 0x221e4801, 0x0000e7c8, 0x4361c7ae, 0x48ffb5fe, 0x0400f242, 
+    0x42e0f04f, 0x1006f9b0, 0xf7ed4620, 0x2107ff92, 0xf7ed4620, 0x04a6ff40, 0x05a0f242, 0x46304629, 
+    0xff45f7ed, 0x220048f5, 0x92007002, 0x2201e9cd, 0x46112201, 0xf7f44610, 0x4629f95f, 0xf7ed4630, 
+    0x4cefff36, 0x2000f994, 0x2a02b132, 0x2a03d00a, 0x2a04d008, 0xe010d006, 0xf7f52000, 0x2301fbd9, 
+    0xe006220c, 0xf7f52000, 0x48e6fbd3, 0x220d2301, 0x21017800, 0xf7f5200e, 0x4629feb0, 0xf7ed4630, 
+    0x7820ff16, 0x48e0b930, 0x220e2300, 0x0100f244, 0xfadff017, 0x200149dd, 0xbdfe7008, 0x4ffee92d, 
+    0xf2404cd7, 0xf24218f4, 0x78200b00, 0xd10d2803, 0x465d4641, 0xf7ed4658, 0xf243feee, 0x46283199, 
+    0xfed8f7ed, 0x462849d2, 0xfed4f7ed, 0x200149cb, 0x70082700, 0x700748cf, 0x0000f994, 0x2120b138, 
+    0x80114acd, 0x780949cd, 0xd0032904, 0xf240e005, 0xe7f52100, 0x2010b108, 0x48c98010, 0x28027800, 
+    0x01c0d101, 0x21008010, 0x22019702, 0xe9cd4610, 0x46111100, 0xf8f0f7f4, 0xf7f62002, 0xf04ff857, 
+    0xf2424900, 0x46510a90, 0xf7ed4648, 0xf7f4fec0, 0x4db1fd6d, 0x80a849bb, 0xb1097809, 0xfe3ff006, 
+    0xfe3ef7f4, 0x4eb87820, 0xd1222803, 0xf04f4641, 0x46407880, 0xfe9ff7ed, 0x41ccf64c, 0xf7ed4640, 
+    0x7a71fe89, 0xf7ed4640, 0x7a31fe85, 0xf7ed4640, 0x79f1fe81, 0xf7ed4640, 0x49a5fe7d, 0xf7ed4640, 
+    0xf242fe79, 0x46480180, 0xfe91f7ed, 0x28037820, 0xb2c0d006, 0xd10d2804, 0x780048a4, 0xd1092801, 
+    0xf00a2003, 0x4898fe71, 0x220e2300, 0x0100f244, 0xfa4ff017, 0xf7f42005, 0x4651f884, 0xf7ed4648, 
+    0x2001fe76, 0xfba9f008, 0x23017a31, 0x8260f8df, 0x7a70461a, 0x0103f001, 0xea404e96, 0x21022001, 
+    0x0000f8a8, 0xf0174630, 0x2300fa34, 0x22014630, 0xf0172102, 0x2301fa2e, 0x22004630, 0xf0174619, 
+    0xe007fa28, 0xf0082001, 0xf8b8fb88, 0x1e400000, 0x0000f8a8, 0x0000f8b8, 0xd8f32801, 0x78004886, 
+    0xd0072801, 0xd0052802, 0xf00a2005, 0x7820fe2f, 0xe00bb120, 0xf00a2006, 0xe7f8fe27, 0xb1287828, 
+    0x1e912201, 0xf7f42005, 0x702ffe55, 0x46514654, 0x4648464e, 0xfe2bf7ed, 0x23014876, 0x21102204, 
+    0xf01730aa, 0x4873f9f6, 0x220f2301, 0x30d403d9, 0xf9eff017, 0x1004f9b5, 0xf7f42000, 0xf9b5fd88, 
+    0xf04f1006, 0x465842e0, 0xfe53f7ed, 0x4621b003, 0xe8bd4630, 0xf7ed4ff0, 0xe92dbe0a, 0xf8df4ffe, 
+    0xf2428160, 0xf2400900, 0xf8981af4, 0x28030000, 0x4651d114, 0x4648464c, 0xfdedf7ed, 0x1199f241, 
+    0xf7ed4620, 0x485dfdd7, 0xf9a6f017, 0x46204601, 0xfdd0f7ed, 0x4620494e, 0xfdccf7ed, 0xf0082001, 
+    0x4957fb1c, 0xf0164850, 0x2801ff89, 0x4c55d029, 0x464d21e2, 0x1c406820, 0x46486020, 0xfdcbf7ed, 
+    0x46286821, 0xfdb6f7ed, 0x01d0f242, 0xf7ed4628, 0x483cfdce, 0x28017800, 0x2100d06c, 0xf201484a, 
+    0xf0173132, 0x4849f97c, 0xf0007800, 0xeb000007, 0x48471100, 0x0081eb00, 0x1c496841, 0xe8bd6041, 
+    0x4e398ffe, 0x7780f04f, 0x79f04c42, 0x0001f000, 0xf8987020, 0xb1800000, 0x46384651, 0xfd9bf7ed, 
+    0x21acf64a, 0xf7ed4638, 0x79f1fd85, 0xf7ed4638, 0x4927fd81, 0xf7ed4638, 0x7820fd7d, 0xd1de2801, 
+    0x0000f998, 0x2410b128, 0x78094924, 0xd0022904, 0x2440e003, 0xb100e7f8, 0x49212408, 0x29027809, 
+    0x2440d100, 0x7a324d22, 0x7a7146c3, 0x0203f002, 0x2102ea41, 0xb1a08029, 0x46384651, 0xfd6bf7ed, 
+    0x21abf64a, 0xf7ed4638, 0x8829fd55, 0xf7ed4638, 0x4621fd51, 0xf7ed4638, 0x490dfd4d, 0xf7ed4638, 
+    0x8828fd49, 0xddaa42a0, 0xf7f42002, 0x4601fd6d, 0xe0334819, 0x0000e0f6, 0x000406fc, 0x0004026b, 
+    0x00040f44, 0x0004055c, 0xf2030416, 0x00040249, 0xdcba01f5, 0x00040269, 0x0004026e, 0x0004028a, 
+    0x000405ae, 0x000402c3, 0x00041448, 0x000405c5, 0x00040270, 0xf203504c, 0x000405d9, 0xf203517e, 
+    0x0002d000, 0x000402e8, 0xf23c80ba, 0x00040f60, 0x00041708, 0x0004026c, 0x00040278, 0x1a436800, 
+    0xf9b149fe, 0xfbb32000, 0x4ffdf1f2, 0x60391cc9, 0x43511e89, 0xfd76f7f4, 0x200149fa, 0xf04f4afb, 
+    0x46440800, 0x48f87008, 0x8000f880, 0x88388829, 0x80111a09, 0x48f6b281, 0xf8c1f017, 0x94022100, 
+    0x46102201, 0x1100e9cd, 0xf7f34611, 0x2002ff25, 0xfe8cf7f5, 0x0a90f242, 0x4000f04f, 0xf7ed4651, 
+    0xf7f4fcf6, 0x4cebfba3, 0x806049eb, 0xb1097809, 0xfc75f006, 0xfc74f7f4, 0x0000f99b, 0x2803465f, 
+    0x2804d005, 0x48e5d10d, 0x28017800, 0x2003d109, 0xfccaf00a, 0x230048e2, 0xf244220e, 0xf0170100, 
+    0x2005f8a8, 0xfeddf7f3, 0x465146d3, 0x4a00f04f, 0xf7ed4650, 0x2001fccc, 0xf9fff008, 0x23017a31, 
+    0x461a7a70, 0x0103f001, 0xea404ed6, 0x80282001, 0x46302102, 0xf88df017, 0x46302300, 0x21022201, 
+    0xf887f017, 0x46302301, 0x46192200, 0xf881f017, 0x2001e005, 0xf9e1f008, 0x1e408828, 0x88288028, 
+    0xd8f62801, 0x780048c8, 0xd0072801, 0xd0052802, 0xf00a2005, 0x7838fc8b, 0xe00cb120, 0xf00a2006, 
+    0xe7f8fc83, 0xb1307820, 0x1e912201, 0xf7f42005, 0xf884fcb1, 0x465d8000, 0x46564659, 0xf7ed4650, 
+    0x48b3fc86, 0x22042301, 0x38a42110, 0xf851f017, 0x230148af, 0x03d9220f, 0xf017387a, 0xf9b4f84a, 
+    0x20011002, 0xfbe3f7f4, 0x1006f9b4, 0x42e0f04f, 0xf7ed4648, 0x4629fcae, 0xf7ed4630, 0x2006fc68, 
+    0xe6ac80e0, 0x7110f242, 0xb570e698, 0xf0082001, 0x49a6f994, 0xf01648a6, 0x4ea6fe01, 0xf2422801, 
+    0xd0260500, 0x21e24ca4, 0x1c406820, 0x46286020, 0xfc41f7ed, 0x46286821, 0xfc2cf7ed, 0x01d0f242, 
+    0xf7ed4628, 0x7830fc44, 0xd0322801, 0x489b2100, 0x3131f201, 0xfff3f016, 0x78004899, 0x0007f000, 
+    0x1100eb00, 0xeb004897, 0x68410081, 0x60411c49, 0x488fbd70, 0xf3c079c0, 0x48931140, 0x48937001, 
+    0x28017800, 0x2900d1f4, 0x4c82d0f2, 0x42e0f04f, 0xf9b44628, 0xf7ed1006, 0x2106fc5c, 0xf7ed4628, 
+    0x7830fc0a, 0xd0022801, 0x80e02004, 0x2005bd70, 0xf242e7fb, 0xe7ca7110, 0x4ff0e92d, 0xb0874f75, 
+    0x42e0f04f, 0x0000f242, 0x1006f9b7, 0xfc41f7ed, 0xf04f4c7f, 0x4d770b01, 0x78204e7e, 0x4878b1c8, 
+    0x4a782100, 0xf0007800, 0xeb000007, 0xeb021000, 0x60410080, 0xb9087828, 0xf849f7fa, 0x28027820, 
+    0x7828d02b, 0x7831b998, 0x3080f44f, 0xfc34f7f4, 0x7828e00d, 0xf7fab968, 0x7831f83a, 0x2000f44f, 
+    0xfc2af7f4, 0x0180f242, 0xf7ed0608, 0x7820fbd0, 0xf997b998, 0x23010001, 0x220e9004, 0x46119005, 
+    0xb002e9cd, 0x9000200c, 0x03989001, 0xfa86f7f5, 0x0190f242, 0xf7ed06c8, 0x7828fbba, 0xf99446a0, 
+    0x43081000, 0x485cd17e, 0xf7f62500, 0xf8dffc10, 0x4a59a138, 0x0000f89a, 0xd1092803, 0x48574958, 
+    0x3002f991, 0x0023f842, 0x1003f991, 0x0021f842, 0x24016811, 0x0024f852, 0xd2014288, 0x46254601, 
+    0xb2641c64, 0xdbf52c04, 0x3000f44f, 0x0103f640, 0xfb81f7ed, 0xfe1af7f9, 0x21004c4a, 0xf9944608, 
+    0xf7f62000, 0xf7f9fd6b, 0x2203ff61, 0x48464607, 0x70252138, 0xff5bf016, 0x9110f8df, 0xf899b158, 
+    0x07400000, 0xf89ad507, 0x28030000, 0x4840d003, 0x70207800, 0x7025e000, 0x1438b239, 0xfe70f7f9, 
+    0x2002493c, 0xb000f881, 0xf87bf7fa, 0x0000f994, 0xfdccf7f9, 0x0000f994, 0xfe0cf7f9, 0x0000f994, 
+    0xfe57f7f9, 0x22034830, 0xf0162138, 0xb128ff30, 0x0000f899, 0xd5010740, 0xf8f5f7fa, 0xffa7f7f9, 
+    0xf2427831, 0xf7f40000, 0x2100fb97, 0xf7f62001, 0xf994ff78, 0x21002000, 0xf7f6200c, 0xf994fcd9, 
+    0xe0002000, 0x2101e003, 0xf7f64608, 0xf998fd17, 0x46440000, 0xd0412803, 0xe03d2804, 0x000405e8, 
+    0x0004056c, 0x0004026b, 0x00040269, 0x0004026e, 0xf203519a, 0x000406fc, 0x000402c3, 0x000405c5, 
+    0xf2030416, 0xf203504c, 0x000405d9, 0x0002d000, 0x00041448, 0x0004055c, 0x000402e8, 0xf23c80ba, 
+    0x00040f60, 0x00041708, 0x0004024a, 0x00040249, 0x00040f44, 0x0004028b, 0x00041458, 0x00029395, 
+    0x00040578, 0x00040290, 0xf38f007c, 0x000402c1, 0x00040688, 0x0004028e, 0xe007d004, 0x780048fe, 
+    0xe003b188, 0x780048fd, 0xd00c2801, 0x220c2301, 0x200e4619, 0xfa71f7f5, 0xb9207820, 0xf44f2100, 
+    0xf7f40000, 0xb007fb29, 0x0190f242, 0xe8bd06c8, 0xf7ed4ff0, 0xe92dbacc, 0x4df14ffe, 0x8e804604, 
+    0x1b0ff240, 0x68ab28fe, 0xdc1bd07e, 0xd03928dd, 0xb370dc0f, 0xd04028b0, 0xd04828b1, 0xd17428dc, 
+    0x46182200, 0x010cf105, 0xfb09f012, 0xd06d1d40, 0x28eee028, 0x28efd06b, 0x28f6d024, 0x28f7d068, 
+    0xe01fd163, 0xf2a04558, 0xd01b110f, 0x28ffdc12, 0xf5b0d018, 0xd07d7f83, 0x0008f111, 0x2807d012, 
+    0x49d7d153, 0x46182200, 0xf012310c, 0x1d40fae8, 0xe007d071, 0xd06f2907, 0xd0032908, 0xd06c2911, 
+    0xd1422912, 0xf04f49ce, 0x68a832ff, 0xf012310c, 0x1d01fb05, 0x20b0d107, 0x49c9e15b, 0x46182200, 
+    0xf012310c, 0x1d41fafb, 0x2801d03b, 0x4fc4d1ea, 0xf2422600, 0x370c0000, 0x1000f9b7, 0xd032290f, 
+    0xf04f2915, 0xf04f0802, 0xf04f42e0, 0xf04f0a01, 0xd02e0903, 0xd1d5290a, 0x1006f9b5, 0xd07a2901, 
+    0xd0792909, 0xd0782902, 0xd0772903, 0xd0762904, 0xd0752905, 0xd1c52906, 0xfaeef7ff, 0x8038200b, 
+    0x80e82007, 0xe0041e72, 0xe0f9e0b8, 0xe079e069, 0x48ace090, 0x68004639, 0xfa91f012, 0xd0701d01, 
+    0x20b1e113, 0xf04fe115, 0xf7ed4227, 0x80eefa72, 0x4ba5e7a8, 0x3000f993, 0xd0032b03, 0xd0012b05, 
+    0xd1022b04, 0x781b4ba1, 0x2108b143, 0xf7ed80ee, 0xe797fa60, 0xe0d1e0b1, 0xe0efe0e2, 0x4220f04f, 
+    0xf7ed4607, 0x2105fa56, 0xf7ed4638, 0x2101fa04, 0xf7f52000, 0x2004fb65, 0xf9f6f00a, 0x4f954894, 
+    0xf9977800, 0x43081000, 0x2000d013, 0x70684992, 0x46102201, 0x9000f881, 0x96022100, 0x1100e9cd, 
+    0xf7f34611, 0xf8a5fc19, 0x7838a006, 0xd0022804, 0x2001e003, 0xf8a5e7ea, 0x210a8006, 0x22004880, 
+    0x8001300c, 0x68a84601, 0xfa39f012, 0xf47f1d01, 0x20dcaf2d, 0xe006e0bd, 0xe035e01e, 0xe077e058, 
+    0x20dde08f, 0xf7ffe0b5, 0x4975fdc7, 0x80e82009, 0x68a82200, 0xf012310c, 0x1d01fa22, 0x20eed108, 
+    0xe098e0a7, 0x2200496e, 0x310c4618, 0xfa17f012, 0xd18d1d40, 0xe09c20ef, 0xf8abf000, 0x22004968, 
+    0x8006f8a5, 0x310c68a8, 0xfa09f012, 0xd1071d01, 0xe08e20f6, 0x22004962, 0x310c4618, 0xf9fff012, 
+    0xd1861d40, 0xe08420f7, 0xf9e3f7ed, 0x22014963, 0xf8814610, 0x2100a000, 0xe9cd9602, 0x46111100, 
+    0xfbbaf7f3, 0x22004956, 0x9006f8a5, 0x310c68a8, 0xf9e5f012, 0xd1071d01, 0xe06a20fe, 0x22004950, 
+    0x310c4618, 0xf9dbf012, 0xd1c21d40, 0xe06020ff, 0xfd1bf7ff, 0xf7f42002, 0xb108f98d, 0xe000200a, 
+    0x4947200f, 0x22008038, 0x310c68a8, 0xf9c7f012, 0xd1081d01, 0x1006f240, 0x4941e04b, 0x46182200, 
+    0xf012310c, 0x1d40f9bc, 0xf240d1a3, 0xe0401007, 0xfb53f7ff, 0xf7f42002, 0xb108f96d, 0xe000200a, 
+    0x4937200f, 0x22008038, 0x310c68a8, 0xf9a7f012, 0xf47f1d01, 0xf240aebc, 0xe02a100e, 0xb034f8a4, 
+    0xf7ffe4df, 0x492efa3b, 0x80e82006, 0x68a82200, 0xf012310c, 0x1d01f994, 0xf240d108, 0xe0181016, 
+    0x22004927, 0x310c4618, 0xf989f012, 0xd1881d40, 0x1017f240, 0xf240e00d, 0xe00a1020, 0x22004821, 
+    0x310c491f, 0xf0126800, 0x1d40f97a, 0xf240d19d, 0x86a01021, 0x2200e4b5, 0xb5102101, 0x3069f2af, 
+    0xffb8f011, 0x20022108, 0xf916f012, 0x60884914, 0x481bbd10, 0x7800b510, 0x4816b3c0, 0xbba87800, 
+    0x78004818, 0xd03a2803, 0x7800480f, 0xd1022803, 0x78004815, 0x480ab350, 0x42e0f04f, 0x1006f9b0, 
+    0x0000f242, 0xf935f7ed, 0xf7f42000, 0xf7f7fda1, 0xf7f6fb83, 0xe01aff83, 0x000405c3, 0x000405c5, 
+    0x000406fc, 0x00040734, 0x0004028a, 0x000402ec, 0x0004055c, 0x00040f44, 0x00040246, 0x00040249, 
+    0x000402f7, 0x000405d9, 0x0004033d, 0x2001e007, 0xfd7ef7f4, 0xf44f2100, 0xf7f41000, 0xf242f91d, 
+    0xe8bd0190, 0x06c84010, 0xb8c1f7ed, 0x41f0e92d, 0x0800f244, 0x4640210a, 0xf8adf7ed, 0x23074cfc, 
+    0xf24f220c, 0x46200100, 0xfc6cf016, 0xf6402307, 0x22087100, 0xf0164620, 0x48f6fc65, 0x78014ef7, 
+    0x290148f5, 0x7831d102, 0xd00a2905, 0xf0162104, 0x48f3fc56, 0x78002400, 0x48f2b3a0, 0xb1107800, 
+    0x2108e012, 0x2100e7f3, 0xf7f62001, 0x4deefcca, 0x200c2100, 0x2000f995, 0xfa2af7f6, 0xf9952101, 
+    0x46082000, 0xfa6af7f6, 0x78284de8, 0xd1002801, 0xf2402401, 0xf04f11f4, 0x46387780, 0xf86bf7ed, 
+    0x2122f249, 0xf7ed4638, 0xf995f855, 0x46381000, 0xf850f7ed, 0x46384621, 0xf84cf7ed, 0x463849dc, 
+    0xf848f7ed, 0x200d7831, 0xd1032905, 0x780949d9, 0x200fb901, 0x23011902, 0x000ef104, 0xf7f44619, 
+    0xf242ffec, 0x06c801b0, 0xf851f7ed, 0xe8bd4640, 0x210b41f0, 0xb83ff7ed, 0x5ff0e92d, 0x46044dce, 
+    0xf5b08e80, 0x686b7fb6, 0xdc12d07d, 0xd07b28ec, 0xb318dc05, 0xd02c288c, 0xd176288d, 0x28ede033, 
+    0xf5b0d01c, 0xd0717f98, 0x7080f5a0, 0xd16c3831, 0xf5b0e014, 0xd06a7fbd, 0xf5a0dc08, 0x386d7080, 
+    0x2805d00c, 0x2806d07e, 0xe007d15f, 0x7080f5a0, 0xd003387b, 0xd076280d, 0xd156280e, 0xf04f49b6, 
+    0x686832ff, 0xf0123108, 0x1d01f899, 0x208cd107, 0x49b1e232, 0x46182200, 0xf0123108, 0x1d41f88f, 
+    0x2801d027, 0x4eacd1ea, 0xf2442700, 0x36080900, 0x1000f9b6, 0xd01e290f, 0xf2422916, 0xf04f0bb0, 
+    0xd01f4800, 0x1000f9b5, 0xd07d2901, 0xd1d52902, 0x46420388, 0xf82df7ed, 0xff28f7ff, 0x8030200b, 
+    0x1e7a489e, 0x68004631, 0xf839f012, 0xd06c1d01, 0x208de1fe, 0xf04fe200, 0x46484228, 0xf819f7ed, 
+    0xe7bb802f, 0xa234f8df, 0x0000f99a, 0xd00f2803, 0xd00d2805, 0xd00b2804, 0x46422103, 0x802f4648, 
+    0xf807f7ed, 0xe195e7aa, 0xe1e6e05b, 0xe1cce0f4, 0x4220f04f, 0x4648464e, 0xfffbf7ec, 0x46302109, 
+    0xffa9f7ec, 0x46404659, 0xffb1f7ec, 0x78304e84, 0xd0172801, 0xd0152802, 0xf0092005, 0x4881ff95, 
+    0xe0017800, 0xe1bde195, 0xd00d2801, 0x200a802f, 0x22004979, 0x80083108, 0xf0116868, 0x1d01fff0, 
+    0xe034d02d, 0xe7e82006, 0x48772301, 0x0299220a, 0xfb5ff016, 0xf7f42000, 0x4874fc3b, 0x28116800, 
+    0x2100d803, 0xf7f34648, 0xf89affd7, 0x20081000, 0x29042300, 0x7831d10c, 0xd1092901, 0x2010496c, 
+    0x29027809, 0xe001d104, 0xe188e015, 0x23012004, 0x21017832, 0xf954f7f9, 0x80282001, 0x20ece7c7, 
+    0x495de18a, 0x46182200, 0xf0113108, 0x1d40ffb8, 0x20edd187, 0xf242e180, 0x06c801b0, 0xff57f7ec, 
+    0x4f5c46b8, 0xf887485c, 0x78018000, 0x0000f242, 0xffa2f7f3, 0x22054854, 0x300a2120, 0xfb27f016, 
+    0xb158f8df, 0x2801b2c0, 0xd0497038, 0x2205484e, 0x300a2120, 0xfb1bf016, 0xa124f8df, 0x7038b2c0, 
+    0x1000f89a, 0xd1162903, 0xd0392801, 0xf6414846, 0x220071ff, 0x30ba460b, 0xfafbf016, 0x78014846, 
+    0x0000f248, 0xff78f7f3, 0x2205483f, 0x300a2120, 0xfafdf016, 0xb2c07038, 0xd0212801, 0x46482198, 
+    0xff09f7ec, 0x6800483e, 0x2000b188, 0xfbc0f7f4, 0x01b0f242, 0xf7ec06c8, 0x482aff0a, 0x3190f240, 
+    0x8000f8a5, 0x78024b37, 0xf7f31e48, 0x4836ff87, 0xff5df7f5, 0x1000f89a, 0x29034833, 0xe07dd06d, 
+    0x4200f04f, 0x1000f9b5, 0xf7ec0c10, 0x482fff32, 0xfa9cf016, 0x20024607, 0xfef6f7f3, 0xf89b1a39, 
+    0xf0000000, 0xeb000007, 0x48291200, 0x0082eb00, 0x62812200, 0x80282002, 0x68014826, 0x60011c49, 
+    0x200a4915, 0x68688030, 0xf0113108, 0x1d01ff28, 0xf240d108, 0xe0ef1030, 0x2200490f, 0x31084618, 
+    0xff1df011, 0xf47f1d40, 0xf240ae93, 0xe0e31031, 0xf100004c, 0x000402fa, 0xf2031034, 0x0004028a, 
+    0x00040f44, 0x0004055c, 0x00040290, 0x00040f88, 0xdcba01f5, 0x000402c3, 0x00040710, 0x00040734, 
+    0x000405d9, 0x00040249, 0xf2035022, 0x00040238, 0x0004036b, 0x00040273, 0x0004028b, 0x00040f60, 
+    0x00057f70, 0xf23c80ba, 0x00041458, 0xf0008128, 0x00041708, 0x00057f84, 0x4960e7ff, 0x2000f991, 
+    0x3002f991, 0x2022f850, 0x2023f840, 0x2001f991, 0x1003f991, 0x2022f850, 0x2021f840, 0x3200e9d0, 
+    0x1002e9d0, 0xeb01189f, 0x44670c00, 0x5ce8f64f, 0x0f97ebbc, 0x4293d917, 0x461fd901, 0x4617e000, 
+    0xd9014281, 0xe000468c, 0x45674684, 0x4293d905, 0x4618d901, 0x4610e004, 0x4281e002, 0x4608d900, 
+    0x42884947, 0x4847d94f, 0xb3787800, 0xf9b14946, 0x28140000, 0x1c40da2b, 0xf89b8008, 0x22000000, 
+    0xf0001c40, 0xeb000007, 0x48401100, 0x0081eb00, 0xf5016881, 0x60816180, 0x8000f8a5, 0x8030203f, 
+    0x493b483c, 0xf0116800, 0x1d01fe8a, 0xf240d108, 0xe051106c, 0x22004837, 0x68004935, 0xfe7ff011, 
+    0xf47f1d40, 0xf240adf5, 0xe045106d, 0x2002e7ff, 0xfe30f7f3, 0x200ab108, 0x200fe000, 0x492c8030, 
+    0x68682200, 0xfe6bf011, 0xd1071d01, 0x1072f240, 0x4927e032, 0x46182200, 0xfe61f011, 0xd1e01d40, 
+    0x1073f240, 0x2002e028, 0xfe14f7f3, 0x200ab108, 0x200fe000, 0x491e8030, 0x68682200, 0xfe4ff011, 
+    0xd1071d01, 0x107af240, 0x4919e016, 0x46182200, 0xfe45f011, 0xd1c41d40, 0x107bf240, 0xf240e00c, 
+    0xe0091088, 0x22004814, 0x68004911, 0xfe37f011, 0xd1b61d40, 0x1089f240, 0xe8bd86a0, 0x22009ff0, 
+    0xb5102101, 0x40eff2af, 0xfc74f011, 0x20032108, 0xfdd2f011, 0x39084906, 0xbd106048, 0x00040578, 
+    0x00013880, 0x00040f44, 0x00040f4a, 0x00041708, 0x00040718, 0x00040f7c, 0x00040734, 0x5ffce92d, 
+    0xf248210c, 0xf7ec0000, 0x48fafda6, 0x21042202, 0xf98df016, 0x2000b110, 0xf889f7f5, 0x93d8f8df, 
+    0xf899464c, 0xf7f50000, 0x7820fc15, 0xf84cf007, 0xf985f007, 0xf6404ff1, 0x78380a04, 0xf8dfbb78, 
+    0xf04fb3c0, 0x46410800, 0x0000f89b, 0x0007f000, 0x1200eb00, 0xeb0048eb, 0x22010082, 0x802cf8c0, 
+    0xf7f52002, 0x2200faf8, 0x46112001, 0xfaf3f7f5, 0x48e52400, 0x46212301, 0x2644eb00, 0x220048e3, 
+    0x2544eb00, 0xe9cd4618, 0xf7f25600, 0x48e0fbf5, 0x68022100, 0x0074f8b2, 0x3076f8b2, 0xe026e00b, 
+    0x2010f835, 0xfc02fb12, 0x2010f836, 0xb2801c40, 0xc202fb12, 0x42834411, 0x48d6d2f2, 0x23012200, 
+    0x1024f840, 0xf84048d4, 0x48d41024, 0xeb0049d4, 0xeb012044, 0xe9cd2144, 0x46211000, 0xf7f24610, 
+    0x1c64fbcb, 0x2c04b264, 0x7838dbc3, 0x4ccdb320, 0xf0164620, 0xea00f8f1, 0x4620050a, 0xf8ecf016, 
+    0x0680f000, 0xf0164620, 0xf400f8e7, 0x20045480, 0xfe47f004, 0x46b87838, 0x2100b318, 0xf0052001, 
+    0x2000fc59, 0xfa2cf005, 0xa2fcf8df, 0xf89a48bf, 0xb1e11000, 0xe01f2102, 0x8000f8cb, 0xf8df4641, 
+    0x268082f0, 0x465548bb, 0xf8c80174, 0xf0161000, 0xf8b8f8c6, 0xb2810000, 0x301448b6, 0xf8bff016, 
+    0x2101e7d5, 0xf0054608, 0x2001fc35, 0x49b2e7da, 0x29017809, 0x2103d10a, 0x49b07001, 0x20042200, 
+    0xfd18f7f3, 0xf7f3200b, 0x2400fe12, 0x78384fac, 0xf89ab920, 0xb1080000, 0xe0002001, 0xf7f92000, 
+    0x7838fafe, 0x48a7b920, 0xb1087800, 0xe0002008, 0x43352000, 0x489b4305, 0xf4454325, 0xf01661e0, 
+    0x48a1f88e, 0xf0162100, 0xf898f88a, 0xb9200000, 0x2001499e, 0x499e7008, 0xf9997008, 0x28030000, 
+    0x2805d004, 0x2804d006, 0xe00fd004, 0x78004899, 0xd20b2841, 0xf2474894, 0x386a7185, 0xf86ff016, 
+    0xf2414891, 0x38683114, 0xf869f016, 0xf7f92001, 0x4891f98b, 0x0000f990, 0xff5cf7f8, 0x28017838, 
+    0x2100d011, 0x8800488d, 0x0240eb00, 0x10c0ebc2, 0x5ffce8bd, 0x00c0eb01, 0x10e5f2a0, 0x4879b281, 
+    0xf0161c80, 0xf242b84c, 0xe7eb7110, 0x5ffce92d, 0x46044e83, 0xf04f4983, 0x8e800a00, 0xf5b06873, 
+    0x680d7f8f, 0xdc12d075, 0xd07328e2, 0xb318dc05, 0xd02c28b6, 0xd16e28b7, 0x28e3e033, 0xf5b0d01c, 
+    0xd0697f89, 0x7080f5a0, 0xd1643813, 0xf5b0e014, 0xd0727fd7, 0xf5a0dc08, 0x381f7080, 0x2869d00c, 
+    0x286ad06c, 0xe1c9d157, 0x7080f5a0, 0xd00338af, 0xd0782821, 0xd14e2822, 0xf04f4969, 0x687032ff, 
+    0xf0113108, 0x1d01fcdb, 0x20b6d107, 0x4964e20f, 0x46182200, 0xf0113108, 0x1d41fcd1, 0x2801d01f, 
+    0x4d5fd1ea, 0x35082700, 0x1000f9b5, 0xd018290f, 0xf04f2917, 0xd0304210, 0x1000f9b6, 0x0000f248, 
+    0xfc77f7ec, 0x0000f9b6, 0xb0f0f8df, 0xd0552801, 0xd1d12802, 0x7800484a, 0xd0682801, 0x20b7e1cf, 
+    0xf04fe1e5, 0xf2484229, 0xf7ec0000, 0x494efc62, 0x80374a4a, 0x68126808, 0xda014290, 0x60081c40, 
+    0xb2818808, 0x1c80483b, 0xffc9f015, 0x70074847, 0xe0fde7b2, 0xe1cbe028, 0x4827e0c7, 0x0000f990, 
+    0xd00c2803, 0xd00a2805, 0xd0082804, 0xf2482103, 0x80370000, 0xfc3df7ec, 0xe189e79e, 0xf04fe156, 
+    0xf2484220, 0xf7ec0000, 0x4935fc34, 0x80302001, 0x8028200a, 0x68702200, 0xf0113108, 0x1d01fc40, 
+    0x20e2d108, 0xe199e1a3, 0x2200492d, 0x31084618, 0xfc35f011, 0xd1cb1d40, 0xe19820e3, 0x80b0f8df, 
+    0x21022301, 0x4640461a, 0xffa3f015, 0x46402300, 0x21022201, 0xff9df015, 0xf7f32002, 0xf8dffd0a, 
+    0xb1289094, 0x78004824, 0xd07d2801, 0xe159e0f0, 0x0000e044, 0xf3074084, 0x0004028a, 0x00040f44, 
+    0x00040f60, 0x00041708, 0x00044178, 0x00043978, 0x000405f8, 0x000412a8, 0x000412b8, 0x00045178, 
+    0x00044978, 0xf23c80b8, 0x000402c3, 0x000405d2, 0x00040f8c, 0xf203513e, 0x000402cf, 0x0ee6b280, 
+    0x0004055c, 0x00040f88, 0xf203086e, 0x0004028e, 0x0004028f, 0x0004055e, 0x00040290, 0x00057f78, 
+    0x00040720, 0x00040f7c, 0x00057f80, 0x00040dec, 0xf23c8314, 0x00040f4a, 0x00040536, 0x0000f99b, 
+    0x8290f8df, 0xb290f8df, 0xd0032804, 0xd0012802, 0xd1352803, 0x0000f9b9, 0xda312804, 0x7801489f, 
+    0x0000f242, 0xfbb8f7f3, 0x1000f8b9, 0x1c492200, 0x1000f8a9, 0x0000f898, 0xf0001c40, 0xeb000007, 
+    0xeb0b1100, 0x68810081, 0x6180f501, 0x80376081, 0x8028203f, 0x49924893, 0xf0116800, 0x1d01fba0, 
+    0xf240d108, 0xe1021012, 0x498de03d, 0x46282200, 0xfb95f011, 0xf47f1d40, 0xf240aec9, 0xe0f61013, 
+    0x68004889, 0x488ab148, 0x319bf240, 0x4b878037, 0x1e487802, 0xfbb2f7f3, 0xf898e6ce, 0x22000000, 
+    0xf0001c40, 0xeb000007, 0xeb0b1100, 0x68810081, 0x7100f501, 0x80376081, 0x80282009, 0x4978487d, 
+    0xf0116800, 0x1d01fb6c, 0xf240d108, 0xe0ce101e, 0x22004878, 0x68004972, 0xfb61f011, 0xd1db1d40, 
+    0x101ff240, 0xf89be0c3, 0xbb880000, 0xf7f54872, 0xf8dffb5e, 0x220081c8, 0x0000f248, 0x1000f8d8, 
+    0xfb37f7ec, 0xf8df2500, 0x220081b0, 0x0000f248, 0x1025f858, 0xfb2df7ec, 0x20004969, 0x4b6a4a69, 
+    0x0100e9cd, 0x0025f858, 0xfa8cf7ec, 0x48634602, 0x42826800, 0x4965d208, 0x0000f248, 0xf7ec8037, 
+    0xf04ffb18, 0xe6770a01, 0xb2ed1c6d, 0xd3da2d04, 0x0f00f1ba, 0xf8a9d1a0, 0xf89b7000, 0xb1380000, 
+    0x6808495b, 0x60081c40, 0x485ab281, 0xfe77f015, 0xfcfbf7f8, 0x20014d58, 0xf7f47829, 0x4957fdac, 
+    0x0000f995, 0x49567008, 0xb1b98809, 0x22734955, 0x2201800a, 0x2200708a, 0x485370c8, 0xf0116800, 
+    0x1d01fafe, 0xf240d108, 0xe0601088, 0x2200484e, 0x6800494c, 0xfaf3f011, 0xd0231d40, 0xf015484b, 
+    0x2301fe4b, 0x220f484a, 0xf01503d9, 0xf7edfe62, 0x2002fd17, 0xfbabf7f3, 0x20082100, 0xfe1af7f5, 
+    0xf7f52001, 0x2001fe5f, 0xfe3ef7f5, 0x2002492c, 0x200a8030, 0x80082200, 0xf0116870, 0x1d01fad0, 
+    0xe00ad003, 0x1089f240, 0xf240e031, 0xe02e10ae, 0x22004923, 0xf0114618, 0x1d40fac2, 0xf240d193, 
+    0xe02410af, 0x0000f89b, 0xf7f8b948, 0xf44ffe63, 0xf6403000, 0xf7ec0103, 0xf7f8fa4e, 0xf7fffce7, 
+    0x203ffc9d, 0x48178028, 0x49152200, 0xf0116800, 0x1d01faa6, 0xf240d107, 0xe00810d0, 0x22004910, 
+    0xf0114628, 0x1d40fa9c, 0xf240d1d8, 0x86a010d1, 0x9ffce8bd, 0x21012200, 0xf2afb510, 0xf01140af, 
+    0x2108f8d9, 0xf0112003, 0x4905fa37, 0x60483908, 0x0000bd10, 0x00040f60, 0x00041708, 0x0004028b, 
+    0x00040728, 0x00040f7c, 0x00057f70, 0xf23c80ba, 0x0004055c, 0x00040734, 0x00041458, 0x00040538, 
+    0x40300000, 0xb573eab3, 0x4030ab15, 0xdead0000, 0x00040f8c, 0xf2035152, 0x0004028a, 0x00040244, 
+    0x00040364, 0x0004e270, 0x00040f10, 0xf2060010, 0xf203501a, 0x800849fe, 0xe92d4770, 0x49fd5ffc, 
+    0x8e804604, 0x0a00f04f, 0xf8df4df9, 0xf5b0b3ec, 0xf8df7f27, 0xf10593e8, 0x680b0608, 0xdc61d07e, 
+    0x7fd5f5b0, 0xdc2cd07b, 0x7fa6f5b0, 0xdc12d078, 0xd07628b4, 0xb3a8dc05, 0xd07328ac, 0xd17228ad, 
+    0x28b5e0e2, 0xf5b0d070, 0xd06e7f94, 0x7080f5a0, 0xd1f43829, 0xf5b0e0d8, 0xd0677fba, 0xf5a0dc08, 
+    0x384d7080, 0x2821d078, 0x2822d077, 0xe397d1e7, 0x7080f5a0, 0xd0fa3875, 0xd06f2827, 0xd1de2828, 
+    0xf5b0e286, 0xd06a7ff2, 0xf5b0dc16, 0xd0677fdf, 0xf5a0dc09, 0x38ab7080, 0x2809d079, 0x280ad078, 
+    0xe2abd1cd, 0xf5a0e098, 0x38bf7080, 0x281fd071, 0x2820d070, 0xe373d1c3, 0x7f12f5b0, 0xdc08d06b, 
+    0x7080f5a0, 0xd0d238e5, 0xd0762833, 0xd1b62834, 0xf5a0e366, 0x38497000, 0x2833d070, 0x2834d06f, 
+    0xe3a6d1ad, 0xf2404fc6, 0x42904204, 0x4104f2a0, 0xd06f683f, 0xf240dc3c, 0x429032a6, 0x31a6f2a0, 
+    0xdc1fd069, 0x7f43f5b0, 0xdc12d072, 0x7000f5a0, 0xd0e6389d, 0xd06c2867, 0xe0082868, 0xe24ce3f2, 
+    0xe07fe154, 0xe3eee066, 0xe126e086, 0xd186e1d1, 0xf5a0e3ea, 0x380d7040, 0x285bd066, 0x285cd06f, 
+    0xe061d187, 0xd06b294e, 0x2901dc0b, 0x2940d05c, 0x2941d067, 0xe057d18a, 0xe1ace13f, 0xe2aee211, 
+    0x294fe261, 0x2956d07e, 0x2957d07d, 0xe3eed187, 0x294248a4, 0xd0776800, 0x2912dc15, 0xdc0bd075, 
+    0xd0f42901, 0xd0712908, 0xd1892909, 0xe21be3fd, 0xe237e22d, 0xe2f8e27a, 0xd0352913, 0xd0662934, 
+    0xd1872935, 0x2952e030, 0xdc09d07e, 0xd07c2943, 0xd07b294a, 0xd18a294b, 0xe2bfe3e8, 0xe37be2ed, 
+    0xd0742953, 0x7f92f5b1, 0xf5a1d072, 0x39257180, 0xe019d186, 0xe3fee3fe, 0x20074985, 0x22008030, 
+    0x31086868, 0xf95bf011, 0xd1091d01, 0xe20d20ac, 0xe3f2e3f2, 0x2200497e, 0x31086868, 0xf94ff011, 
+    0xd1011d40, 0xe7f220ad, 0xf04f4979, 0x686832ff, 0xf0113108, 0x1d01f973, 0x20b4d10a, 0xe3fde7e7, 
+    0xe3fde3fd, 0x22004972, 0x31086868, 0xf966f011, 0xd0431d41, 0xd1e72801, 0x1000f9b6, 0x4220f04f, 
+    0x2000f44f, 0xf915f7ec, 0x0000f9b6, 0x81b8f8df, 0xd0352807, 0xd07d2806, 0x81b0f8df, 0xd07a2805, 
+    0xe0052870, 0xe3f0e3f0, 0xe3f0e3f0, 0xe3f0e3f0, 0x2871d072, 0x2808d071, 0x280bd070, 0x2809d06f, 
+    0x2821d06e, 0x2822d06d, 0x2823d06c, 0x2820d06b, 0x2002d1ba, 0xf8a9f7f3, 0x0000f899, 0xf7f3464f, 
+    0x495bf8eb, 0xe0047008, 0xe3fee3fe, 0xe3fee3fe, 0xf997e3fe, 0xf00a0000, 0xe7a5fe70, 0xe79620b5, 
+    0x8028200b, 0x464f4650, 0xa000f889, 0xf8d4f7f3, 0x2201494f, 0x21007008, 0xf7f42002, 0x484dfdfc, 
+    0xb1707800, 0x484d494c, 0x78007809, 0x0100e9cd, 0x7839484b, 0x484b7803, 0x484b7802, 0xf7f67800, 
+    0xf7f4fcc7, 0xf8b8ff48, 0xb9180000, 0x78004847, 0xffa4f012, 0xf861f7f5, 0x23004f45, 0x21802207, 
+    0xf0154638, 0x2301fc36, 0x22064638, 0xf0152140, 0x2300fc30, 0x22034638, 0xf0152108, 0x2300fc2a, 
+    0x22014638, 0xf0152102, 0x2006fc24, 0x22004928, 0xe0098030, 0xe234e01c, 0xe3e1e388, 0xe3fde3fd, 
+    0xe3fde3fd, 0xe3fde3fd, 0x31086868, 0xf897f011, 0xd1081d01, 0x1028f240, 0x491de739, 0x68682200, 
+    0xf0113108, 0x1d40f88c, 0xf240d197, 0xe72e1029, 0x0000f8b8, 0x4827b308, 0x28017800, 0x4826d01d, 
+    0x28017800, 0x4825d019, 0x22002173, 0xf8808001, 0xf899a002, 0x70c11000, 0x480e4601, 0xf0116800, 
+    0x1d01f86e, 0xf240d107, 0xe11f104c, 0x2200491b, 0xf0114618, 0x1d40f864, 0x200cd036, 0x48188028, 
+    0xf8804657, 0x4817a000, 0xb9008800, 0xe03be02f, 0x00040730, 0x00040f10, 0x000402ec, 0x0004028a, 
+    0x00040724, 0x000406f0, 0x00040364, 0x00040558, 0x0004028b, 0x00040535, 0x000405ff, 0x000405fe, 
+    0x000405fd, 0x000405fc, 0x00040534, 0x00040368, 0xf2034228, 0x0004027d, 0x00040285, 0x0004e27c, 
+    0x00040600, 0x00040288, 0x104df240, 0x48f9e0de, 0x28017800, 0x48f8d008, 0xb1287800, 0x780048f7, 
+    0xf89bb910, 0xb1200000, 0x21002201, 0xf7f44610, 0x2000fd32, 0xff93f7f8, 0x780048f1, 0xd00d2801, 
+    0x780048f0, 0x206eb380, 0x48f08030, 0x49ee2200, 0xf0116800, 0x1d01f804, 0xe020d018, 0x80302066, 
+    0x220048eb, 0x680049e8, 0xfff9f010, 0xd1081d01, 0x106ef240, 0x48e6e0aa, 0x49e32200, 0xf0106800, 
+    0x1d40ffee, 0xf240d169, 0xe09f106f, 0x1074f240, 0x48dee09c, 0x49dc2200, 0xf0106800, 0x1d40ffe0, 
+    0xf240d15b, 0xe0911075, 0x48d2e7ff, 0x0822f04f, 0x28017800, 0x48d7d01d, 0x28017800, 0x48d6d051, 
+    0x28018800, 0x48d5d063, 0x28017800, 0x48d4d05c, 0x28017800, 0x48d3d058, 0x28017800, 0x48d2d054, 
+    0x28017800, 0xf8dfd06f, 0xf8988310, 0xb3980000, 0x2000e0cf, 0xfe78f7f7, 0xf7f62003, 0x2007feab, 
+    0xf8def7f7, 0xf832f004, 0xf44f2100, 0xf7f23080, 0x2000ffa3, 0xf8b8f7f7, 0xfd5ff7f9, 0x200249c3, 
+    0x48bc8008, 0x28017800, 0xf8a6d112, 0x22008000, 0x686849b5, 0xff93f010, 0xd1071d01, 0x109cf240, 
+    0x49b1e044, 0x68682200, 0xff89f010, 0xd0051d40, 0xf04f211a, 0xe0655280, 0xe067e069, 0x109df240, 
+    0xf8a6e034, 0x22008000, 0x686849a7, 0xff77f010, 0xd1071d01, 0x10aaf240, 0x49a3e028, 0x68682200, 
+    0xff6df010, 0xd00c1d40, 0x880048a3, 0x2021b1b0, 0x499d8030, 0x68682200, 0xff61f010, 0xd0031d01, 
+    0xf240e00a, 0xe01110ab, 0x10b4f240, 0x4996e00e, 0x68682200, 0xff53f010, 0xd0051d40, 0x78004897, 
+    0xd0042801, 0xe02ae016, 0x10b5f240, 0x2023e20f, 0x498d8030, 0x68682200, 0xff41f010, 0xd1071d01, 
+    0x10bef240, 0x4988e203, 0x68682200, 0xff37f010, 0xd0041d40, 0x7800488a, 0xd0032801, 0xf240e008, 
+    0xe1f410bf, 0x5280f04f, 0x12502112, 0xff11f7eb, 0x78004884, 0xd1092801, 0x21130702, 0x2115e002, 
+    0x5280f04f, 0x2000f44f, 0xff03f7eb, 0x4880e098, 0xb1a87800, 0x80302070, 0x22004973, 0xf0106868, 
+    0x1d01ff0e, 0xf240d107, 0xe1d010de, 0x2200496e, 0xf0106868, 0x1d40ff04, 0xf240d176, 0xe1c610df, 
+    0x78004874, 0x2071b1a8, 0x49678030, 0x68682200, 0xfef5f010, 0xd1071d01, 0x10e4f240, 0x4962e1b7, 
+    0x68682200, 0xfeebf010, 0xd1691d40, 0x10e5f240, 0x485ae1ad, 0x1000f990, 0x0000f89b, 0xd0374301, 
+    0x22014965, 0x700f8072, 0x4864b1e0, 0x09037800, 0xebb2d018, 0xd1011f10, 0xe0042011, 0xebb32302, 
+    0xd1021f10, 0x80702012, 0x2303e00c, 0x1f10ebb3, 0x2011d101, 0x2304e004, 0x1f10ebb3, 0x2012d102, 
+    0x700a8070, 0x80302005, 0x49472200, 0xf0106868, 0x1d01feb6, 0xf240d107, 0xe1782018, 0x22004942, 
+    0xf0106868, 0x1d40feac, 0xf240d12a, 0xe16e2019, 0xf7f72000, 0x2003fd69, 0xfd9cf7f6, 0xf7f62007, 
+    0xf003ffcf, 0xf898ff23, 0x28010000, 0x203ad118, 0x48438030, 0x49342200, 0xf0106800, 0x1d01fe90, 
+    0xf240d109, 0xe1522048, 0x483de00a, 0x492e2200, 0xf0106800, 0x1d40fe84, 0x483ad010, 0x70012101, 
+    0x78014839, 0xf47f2901, 0xf880ac4b, 0x2300a000, 0x22014836, 0xf0152102, 0xe525f9ec, 0x2049f240, 
+    0x4930e135, 0x8028200d, 0xf881481e, 0x7800a000, 0xf9b6bb78, 0x482e1002, 0xd00c2901, 0xd07a2911, 
+    0xf8892004, 0x48150000, 0x1000f89b, 0x0000f990, 0xd06c4308, 0xf8b8e0b4, 0x29941000, 0x2998d04a, 
+    0x2984d048, 0x2988d046, 0x29a4d044, 0x29a8d042, 0x29b4d040, 0x29b8d03e, 0x29c8d03c, 0x4807d03a, 
+    0xf8892103, 0xf89b1000, 0xf9901000, 0x43080000, 0xe095d04e, 0x00040283, 0x00040284, 0x00040242, 
+    0x000402aa, 0x0004027c, 0x00040738, 0x00040ecc, 0x00041268, 0x0004027d, 0x0004027e, 0x00040282, 
+    0x00040581, 0x00040583, 0x00040285, 0x00040348, 0x00040241, 0x00040240, 0x000405d9, 0x000402ed, 
+    0x00040f1c, 0x00040600, 0x00040586, 0xf23c801c, 0xf38e0040, 0xf2412300, 0x220c0100, 0xf979f015, 
+    0x80302007, 0x220049f9, 0xf0106868, 0x1d01fdf8, 0xf240d107, 0xe0ba207c, 0x220049f4, 0xf0106868, 
+    0x1d40fdee, 0xf240d14c, 0xe0b0207d, 0xe042e003, 0x220049ef, 0xf8b8e041, 0x29981000, 0x2988d015, 
+    0x29a8d013, 0x29b8d011, 0x29c8d00f, 0x2005d00d, 0x0000f889, 0xf89b48e7, 0xf9901000, 0x43080000, 
+    0xe02dd026, 0xe3f0e019, 0x2208e07a, 0x23004607, 0xf0150151, 0x2300f93e, 0x22064638, 0xf0152140, 
+    0x2007f938, 0x49d98030, 0x68682200, 0xfdb7f010, 0xd1071d01, 0x209cf240, 0x49d4e079, 0x68682200, 
+    0xfdadf010, 0xd10b1d40, 0x209df240, 0xe21de06f, 0x220049d1, 0x49d1e001, 0x20002200, 0xfabbf7f4, 
+    0xffcef7ec, 0x0000f899, 0xfd86f7f2, 0x465749cc, 0x48cc7008, 0xa000f880, 0x0000f999, 0xfc54f7f7, 
+    0xf7f62005, 0x2000fc87, 0xe22ee001, 0xf7f6e2b2, 0xf7edfeb7, 0xf899fee7, 0xf7f80000, 0x48c2fd00, 
+    0x1c496801, 0x20026001, 0xfd2ef7f2, 0x600849bf, 0x0000f899, 0xffebf7ee, 0x220048bd, 0x20026801, 
+    0xfd38f7f2, 0xf89948bb, 0x70c11000, 0x71072126, 0xe0038001, 0xe0eae1e9, 0xe00ae03c, 0x48b64601, 
+    0x68002200, 0xfd5bf010, 0xd1071d01, 0x3004f240, 0x49b0e3c7, 0x46182200, 0xfd51f010, 0xd0141d40, 
+    0x0000f89b, 0xd0132801, 0x220048ac, 0x20016801, 0xfd10f7f2, 0x780048aa, 0xe0022801, 0xe190e076, 
+    0xd021e12a, 0x80282003, 0xf240e447, 0xe3a83005, 0x80302020, 0x22004995, 0xf0106868, 0x1d01fd30, 
+    0xf240d10d, 0xe39c300c, 0xe194e183, 0xe1d4e233, 0xe21ae1c3, 0x2200498d, 0xf0106868, 0x1d40fd20, 
+    0xf240d1e2, 0xe38c300d, 0xe7dc2002, 0x464f2002, 0x0000f889, 0xff44f7ec, 0x48934992, 0xa000f881, 
+    0xb9588800, 0x78004891, 0xd1072801, 0x78004890, 0x2200b920, 0x4610498f, 0xfa1df7f4, 0x8238f8df, 
+    0x0000f898, 0xe004b950, 0xe20ce236, 0xe23be21c, 0x22ffe35d, 0x461120fe, 0xfe62f7ed, 0xf7f72002, 
+    0x2005fbb3, 0xfbe6f7f6, 0xf7f62000, 0xf003fe19, 0xf898fd6d, 0xb9080000, 0xff13f7f8, 0x2100487f, 
+    0xf83df015, 0x22264973, 0x70c87838, 0xa004f881, 0xf7f8800a, 0x4870fc54, 0x496e2200, 0xf0106800, 
+    0x1d01fcce, 0xf240d107, 0xe33a3068, 0x22004969, 0xf0104618, 0x1d40fcc4, 0xf240d186, 0xe3303069, 
+    0x464f2001, 0x0000f889, 0xfeeaf7ec, 0x48664965, 0xa000f881, 0xb9588800, 0x78004864, 0xd1072801, 
+    0x78004863, 0x2200b920, 0x46104965, 0xf9c3f7f4, 0xf7f62005, 0x2000fb9f, 0xe032e005, 0xe1e8e158, 
+    0xe20fe1f4, 0xf7f6e310, 0x2001fdcb, 0xfb5cf7f7, 0xfd1cf003, 0x78004858, 0xf7f8b908, 0x4857ff11, 
+    0xf0142100, 0x494bffec, 0x78382226, 0xf88170c8, 0x800aa004, 0xfc03f7f8, 0x22004847, 0x68004945, 
+    0xfc7df010, 0xd1071d01, 0x30a6f240, 0x4941e2e9, 0x46182200, 0xfc73f010, 0xd1ad1d40, 0x30a7f240, 
+    0xf44fe2df, 0xf9b52800, 0xf04f1000, 0x46405280, 0xfc4ff7eb, 0x0000f9b5, 0x280a2717, 0x493ad005, 
+    0xf0318809, 0xd10c0108, 0x483ee086, 0xb9687800, 0xf7f22002, 0xb148fd3e, 0x88004833, 0x0008f030, 
+    0x2119d029, 0xf04f4640, 0xe1115280, 0xf7f32000, 0x4935fd7d, 0x4a242001, 0x49346008, 0x68086812, 
+    0xda014290, 0x60081c40, 0xb2818808, 0x3024482b, 0xff95f014, 0x1000f899, 0xf7f32000, 0xf005fecc, 
+    0x492bfed3, 0xf881201c, 0xf7f2a000, 0x2000fd01, 0xf94cf7f6, 0x2002e178, 0xfce9f7f2, 0x80282009, 
+    0x22004824, 0x49098037, 0xf0106800, 0x1d01fc18, 0xf240d107, 0xe28430e6, 0x22004904, 0xf0104638, 
+    0x1d40fc0e, 0xf240d199, 0xe27a30e7, 0x00040738, 0x0004054c, 0x00040242, 0x0004054e, 0x00040550, 
+    0x0004028b, 0x000402fa, 0x00057f78, 0x000405b0, 0x000405e4, 0x0004e27c, 0x00040f10, 0x000405e0, 
+    0x0004055c, 0x00040600, 0x00040288, 0x00040284, 0x00040283, 0x00040552, 0x00040285, 0xf203511c, 
+    0x00040554, 0x00040f46, 0x00057f7c, 0x00057f80, 0x00040244, 0x00040724, 0xd0152803, 0xd02d2804, 
+    0xd0452802, 0xd05b2808, 0xf47f2809, 0x2002af7a, 0xfb6bf7f2, 0x220048f6, 0x49f48037, 0xf0106800, 
+    0x1d01fbbe, 0xe06dd066, 0x80302010, 0x220048f1, 0x680049ee, 0xfbb3f010, 0xd1081d01, 0x30f4f240, 
+    0x48ece21f, 0x49e92200, 0xf0106800, 0x1d40fba8, 0x2004d001, 0xf240e667, 0xe21230f5, 0x80302012, 
+    0x220048e5, 0x680049e1, 0xfb99f010, 0xd1081d01, 0x30fcf240, 0x48e0e205, 0x49dc2200, 0xf0106800, 
+    0x1d40fb8e, 0xf240d102, 0xe1fa30fd, 0xe64a2005, 0x80302011, 0x220048d9, 0x680049d4, 0xfb7ff010, 
+    0xd1081d01, 0x4004f240, 0x48d4e1eb, 0x49cf2200, 0xf0106800, 0x1d40fb74, 0xf240d1e8, 0xe1e04005, 
+    0x80302016, 0x220048ce, 0x680049c8, 0xfb67f010, 0xd1081d01, 0x400cf240, 0x48c9e1d3, 0x49c32200, 
+    0xf0106800, 0x1d40fb5c, 0x2009d001, 0xf240e61b, 0xe1c6400d, 0x4016f240, 0x49bce1c3, 0x46382200, 
+    0xfb4df010, 0xf47f1d40, 0xf240acd8, 0xe1b84017, 0x5880f04f, 0x1000f9b5, 0x2700f44f, 0x46384642, 
+    0xfb27f7eb, 0x880048b7, 0x0008f030, 0xe002d112, 0xfb1ff7eb, 0xf9b5e4c1, 0x21140000, 0xd00d2804, 
+    0xd02b2805, 0xd0432806, 0xd0582807, 0xd0092808, 0xd0072809, 0x46422118, 0xe7e94638, 0x780048aa, 
+    0xd0062803, 0x220048a9, 0x20016801, 0xfae2f7f2, 0x48a7e4a3, 0x80312200, 0x6800499c, 0xfb0ff010, 
+    0xd1061d01, 0x4038f240, 0x4998e17b, 0xf0102200, 0x1d40fb06, 0xf240d1ce, 0xe1724039, 0x80302013, 
+    0x2200489c, 0x68004991, 0xfaf9f010, 0xd1081d01, 0x4046f240, 0x4897e165, 0x498c2200, 0xf0106800, 
+    0x1d40faee, 0x2006d001, 0xf240e5ad, 0xe1584047, 0x2200488f, 0x49858031, 0xf0106800, 0x1d01fae0, 
+    0xf240d106, 0xe14c404e, 0x22004980, 0xfad7f010, 0xd0011d40, 0xe5962007, 0x404ff240, 0x2015e141, 
+    0x48858030, 0x49792200, 0xf0106800, 0x1d01fac8, 0xf240d108, 0xe1344056, 0x2200487f, 0x68004973, 
+    0xfabdf010, 0xd0011d40, 0xe57c2008, 0x4057f240, 0x487ae127, 0x0200f04f, 0xb1087800, 0xe0004978, 
+    0x20014978, 0xfa76f7f2, 0xe56c200a, 0x81d8f8df, 0x8028200e, 0x0000f898, 0xd18907c0, 0xf7f52101, 
+    0x2000fe3f, 0x1000f9b8, 0x41391c47, 0xd10507c9, 0xb2c32201, 0x46104611, 0xfd5ef7f6, 0x2804b238, 
+    0xe41adbf0, 0xf7f82003, 0xf8dff9e8, 0xb240c1a0, 0x464f2803, 0x0000f889, 0x2805d002, 0xe023d019, 
+    0x0000f8b8, 0xd0052894, 0xd0032884, 0xd00128a4, 0xd10328b4, 0x70382005, 0xe0102308, 0xd00b2898, 
+    0xd0092888, 0xd00728a8, 0xd00528b8, 0xd00328c8, 0xf8b8e00a, 0xe7f10000, 0x70382004, 0x46602307, 
+    0x213c2202, 0xfdd5f014, 0x46b97838, 0xfa44f7f2, 0x813cf8df, 0x22062300, 0xf8882140, 0x200f0000, 
+    0x484c8028, 0xfdc5f014, 0x2300484a, 0x21022201, 0xfdbff014, 0x23014848, 0x21402206, 0xfdb9f014, 
+    0x23004845, 0x21042202, 0xfdb3f014, 0xf7f57838, 0x4942fd51, 0xa000f8cd, 0x780b7838, 0x780a4940, 
+    0x78094940, 0xf9d9f7ee, 0xf7f82000, 0xf898faa8, 0xf44f1000, 0x46402800, 0xfa1ef7f2, 0x21002700, 
+    0xf7f34608, 0x2200fb1d, 0x0300f647, 0x46104611, 0xa000f8cd, 0xfd68f7f5, 0x7801482d, 0xf7f24640, 
+    0xf240fa0b, 0x464011f4, 0xf9a5f7eb, 0x22004827, 0x304221ff, 0xfd8bf014, 0x46404601, 0xf98af7eb, 
+    0x46404929, 0xf986f7eb, 0xb23f1c7f, 0xd0512f40, 0x2200481e, 0x304221ff, 0xfd79f014, 0xd0ce28ff, 
+    0x0000f899, 0xf7f4464f, 0x4820f805, 0x78392200, 0x212670c1, 0xa004f880, 0x46018001, 0x6800481c, 
+    0xf9ddf010, 0xd03f1d01, 0xe04be046, 0x00040738, 0x00040724, 0x000406a4, 0x000406c4, 0x000406b4, 
+    0x00040714, 0x00040288, 0x0004027c, 0x000405e0, 0x000406f0, 0x000406d4, 0x00040704, 0x00040f45, 
+    0x0094c5f0, 0x00b71b00, 0x0004027e, 0xf2060000, 0x0004028b, 0xf2034228, 0xf23c8310, 0x00040313, 
+    0x00040312, 0x000405d9, 0xdcba01f5, 0x0004e27c, 0x00040f10, 0x46384f14, 0xfcfef014, 0x0104f040, 
+    0xf0144638, 0xe7abfcfc, 0x5028f240, 0x490fe009, 0x46182200, 0xf993f010, 0xf47f1d40, 0xf240ac55, 
+    0x86a05029, 0x9ffce8bd, 0xe44c2010, 0x22004808, 0xb5102101, 0xffcef00f, 0x20052108, 0xf92cf010, 
+    0x60484904, 0x0000bd10, 0xf203517c, 0x0004e27c, 0x0001445b, 0x00040730, 0x4ff1e92d, 0xb09448fb, 
+    0x83ecf8df, 0x27002404, 0xf8b06800, 0x91121078, 0xa07af8b0, 0x907cf8b0, 0xb07ef8b0, 0x4df52600, 
+    0x22002301, 0x46184631, 0x8500e9cd, 0xff84f7f0, 0xf8389912, 0xfb100011, 0x9812f100, 0x0010f835, 
+    0x1100fb10, 0x001af838, 0xf200fb10, 0x001af835, 0x2200fb10, 0x0019f838, 0xfb104411, 0xf835f300, 
+    0xfb100019, 0xf8383300, 0xfb10001b, 0xf835fc00, 0xad02001b, 0xc000fb10, 0x44084418, 0x1106eb05, 
+    0x0027f841, 0xf2412100, 0xf7f20000, 0x1c76f925, 0x2e04b276, 0x1c7fdbc3, 0x42a7b23f, 0x2700dbbe, 
+    0xe0142100, 0xb2001c48, 0x1207eb05, 0xe00b4684, 0x3021f852, 0x6020f852, 0xdd0342b3, 0x6021f842, 
+    0x3020f842, 0xb2001c40, 0xdbf142a0, 0x42a14661, 0x1c7fdbe8, 0x2f04b27f, 0xeb04dbe2, 0x200071d4, 
+    0xeb051049, 0xf8521200, 0x9a143021, 0x3020f842, 0xb2401c40, 0xdbf42804, 0xe8bdb015, 0xe92d8ff0, 
+    0x49ba4ff3, 0x2000b085, 0x9003468a, 0x88046808, 0x1c700866, 0xfa0f9002, 0x2500fb80, 0x0000f8da, 
+    0xfb059905, 0xf9b0f704, 0x9a023088, 0x0047eb01, 0x468149b1, 0xfbfbf014, 0x0000f8da, 0x9a0249af, 
+    0x3088f9b0, 0xeb009806, 0x46800047, 0xfbeff014, 0x46584aa9, 0xe00b4ba9, 0xf8521a21, 0xf8427021, 
+    0xf8537020, 0x42491021, 0x1020f843, 0xb2001c40, 0xdbf142a0, 0x0000f8da, 0x4aa14657, 0x78819b03, 
+    0x0094f8d0, 0x0100e9cd, 0x489b499c, 0xf81ef015, 0x4631489b, 0x0086eb00, 0xfbfaf015, 0x4b976838, 
+    0x78814a95, 0x0094f8d0, 0x0100e9cd, 0x99034894, 0xfd22f014, 0x46496838, 0xf9b09a02, 0x488e3084, 
+    0xfbc6f014, 0x46416838, 0xf9b09a02, 0x488b3084, 0xfbbef014, 0xb26d1c6d, 0xdb9f2d04, 0xe78cb007, 
+    0x41fce92d, 0x48814604, 0x4615460f, 0x88066800, 0xea4f4884, 0x78030856, 0x2b03487c, 0x88016800, 
+    0xf001fb04, 0x0140eb02, 0x0240eb07, 0x2301d005, 0x2100e9cd, 0x46212200, 0x4b7be018, 0x781bb2e0, 
+    0xd0082b01, 0x781b4b79, 0xd0042b1b, 0xd0072c02, 0xd0052c03, 0xb10ce005, 0xd1022c01, 0xe0002003, 
+    0xe9cd2000, 0x23012100, 0xb2412200, 0xf7f02001, 0xfb04fe73, 0xfb04f006, 0xf8358106, 0xf8272010, 
+    0x22002011, 0x2010f825, 0x2011f825, 0x81fce8bd, 0xe92d4868, 0xf99041f0, 0x48671000, 0x29044f64, 
+    0xd0057800, 0xd00e2905, 0xd212283c, 0xe0112001, 0xd90128be, 0xe00d2000, 0x2002495a, 0x29037809, 
+    0x2005d108, 0x284be006, 0x2006d201, 0x2008e002, 0x2004e000, 0xf8df4a59, 0x2100c148, 0x00c0ebc0, 
+    0x080cf06f, 0x0ec0eb02, 0xeb072000, 0xe9c404c1, 0x46400000, 0xd5001a0b, 0x28001a43, 0x4242da01, 
+    0x4602e000, 0x5023f85c, 0x280e1c40, 0x6022f85e, 0x2300e9d4, 0x2306fbc5, 0x2300e9c4, 0x1c49dbea, 
+    0xdbe12911, 0xeb072000, 0x680a01c0, 0x040b8889, 0x4112ea43, 0x1020f84c, 0x28111c40, 0xf04fdbf3, 
+    0xf8dc5100, 0x42880000, 0xb1c8dc14, 0xf85c2000, 0x00522020, 0x2020f84c, 0x28111c40, 0xe7f0dbf7, 
+    0xf85c2000, 0x10522020, 0x2020f84c, 0x28111c40, 0xe001dbf7, 0x4180f04f, 0x0000f8dc, 0xdcef4288, 
+    0xf85c2000, 0xf1011020, 0xf84c5100, 0x1c401020, 0xdbf62811, 0x81f0e8bd, 0x4ffee92d, 0xa06cf8df, 
+    0x2100468c, 0x39fff04f, 0x469b9102, 0x46134f1a, 0x1000f8da, 0x46484606, 0x2101880d, 0x0455eb01, 
+    0xe0112100, 0x1205fb06, 0xe012f83c, 0x2012f833, 0xfe0efb1e, 0xe202fb12, 0x2021f847, 0xdd014282, 
+    0x4610b101, 0xb2091c49, 0xdbeb42a1, 0xd07c2800, 0xf44f2200, 0xe0020100, 0xb2121c52, 0x42881040, 
+    0x2a00dafa, 0x2100dd25, 0x0000e021, 0x000405f8, 0x00048978, 0x00049178, 0x0004c178, 0x0004d178, 
+    0x00049978, 0x000405d9, 0x00040310, 0x000402b8, 0x0004a178, 0x0004028a, 0x0004055e, 0x00040748, 
+    0x3021f857, 0xf8474113, 0x1c493021, 0x42a1b209, 0x2100dbf6, 0x0280f44f, 0x1c49e002, 0x0040b209, 
+    0xdbfa4290, 0xdd0a2900, 0xe0062000, 0x2020f857, 0xf847408a, 0x1c402020, 0x42a0b200, 0x2000dbf6, 
+    0xe0072140, 0x2020f857, 0xda012a40, 0x1020f847, 0xb2001c40, 0xdbf542a0, 0xb2234aff, 0x46484698, 
+    0xf0154611, 0x4643fa2b, 0x1ae8e006, 0x0020f857, 0x0023f847, 0xb21b1c5b, 0xdbf642ab, 0xf005fb06, 
+    0xeb0b4622, 0x48f40180, 0xf9f2f014, 0xf04f980c, 0xf8406180, 0x48f11026, 0xf0154629, 0xf8dafa69, 
+    0x78810000, 0x0094f8d0, 0xe034e000, 0x0100e9cd, 0x49ea4aeb, 0x9b0248e8, 0xfe78f014, 0xf04f49e8, 
+    0xe00a5200, 0x2000b1e0, 0x3020f851, 0xf841005b, 0x1c403020, 0x281fb200, 0x6808dbf6, 0xddf14290, 
+    0x4280f04f, 0x42906808, 0x2000dd0a, 0x3020f851, 0xf841105b, 0x1c403020, 0x281fb200, 0xe7f1dbf6, 
+    0xf8512000, 0xf1022020, 0xf8415200, 0x1c402020, 0x281fb200, 0xe8bddbf5, 0xe92d8ffe, 0xf5004ff7, 
+    0x460776c8, 0x08c8f100, 0x507ef04f, 0x68386030, 0xff52f016, 0x68784604, 0xf0164240, 0x4621ff4d, 
+    0xfe4cf016, 0x46046070, 0xf0166838, 0xf016ff45, 0x4689fdb1, 0x46054621, 0xf0164608, 0xf016ff69, 
+    0x4bc0fda9, 0xf0162200, 0x464bfbe3, 0xf016462a, 0xf015faab, 0x4682ff9f, 0x24029802, 0x0b01f100, 
+    0x2501e057, 0x0900f04f, 0xf857e00e, 0xf0160025, 0x1b61ff23, 0x1021f856, 0xff4af016, 0xf0164649, 
+    0x1c6dfdb5, 0xb22d4681, 0xdbee42a5, 0x0024f857, 0xff12f016, 0xf0164649, 0xf080fda9, 0x46514000, 
+    0xfe0cf016, 0x46812501, 0x1b60e00d, 0x1020f856, 0xf0164648, 0xf856ff2d, 0xf0161025, 0xf848fd97, 
+    0x1c6d0025, 0x42a5b22d, 0x4649dbef, 0xf8484608, 0xf0169024, 0xf016ff1d, 0x4b9afd5d, 0xf0162200, 
+    0x4605fb97, 0x46504689, 0xfd54f016, 0x464b462a, 0xfa5af016, 0xff4ef015, 0x20014682, 0xe0051c64, 
+    0x1020f858, 0x1020f846, 0xb2001c40, 0xdbf742a0, 0x455cb224, 0x9d02dba5, 0x1cad2400, 0xf856e00b, 
+    0x210f0024, 0xf895f017, 0xfe8af016, 0xf8419901, 0x1c640024, 0x42acb224, 0xe75cdbf1, 0x4ff7e92d, 
+    0xa204f8df, 0x4680b084, 0x20004693, 0x21019003, 0x0000f8da, 0xeb018806, 0x91020156, 0xf8b0497b, 
+    0x88090072, 0x00401a08, 0x2d00b205, 0x2500da00, 0x0011f1a6, 0xdd004285, 0x2400b205, 0x46314870, 
+    0xf966f015, 0x20004a6e, 0x1104eb04, 0xf858180f, 0x19473027, 0xb2001c40, 0x2811029b, 0x3027f842, 
+    0xf8dadbf4, 0x4b650000, 0x78814a63, 0x0094f8d0, 0x0100e9cd, 0x99034862, 0xfa7ef014, 0xf706fb04, 
+    0xf06f9905, 0x485c0909, 0x9a02464b, 0x0187eb01, 0xf8cdf014, 0xeb0b4859, 0x9a020187, 0xf014464b, 
+    0x1c64f8c6, 0x2c04b264, 0xe557dbc8, 0x5fffe92d, 0x48554682, 0x88076800, 0x26002001, 0x0b57eb00, 
+    0xe02b2500, 0x5407fb06, 0xf9309802, 0x980e2014, 0xc024f850, 0xfb029803, 0xf930fe0c, 0x980f1014, 
+    0x3024f850, 0xe003fb01, 0xfe03fb02, 0xe31cfb01, 0xf202fb12, 0xfb110140, 0xea4f2101, 0x10c91943, 
+    0xf0154688, 0xf82af863, 0x46410014, 0xf0154648, 0x9901f85d, 0xb22d1c6d, 0x0014f821, 0xdbd1455d, 
+    0xb2761c76, 0xdbcb2e04, 0x46012000, 0xfb004652, 0x1c401307, 0x2804b240, 0x1013f82a, 0x9901dbf6, 
+    0x4610b004, 0x5ff0e8bd, 0xe92de499, 0xf8df4fff, 0xb08390b8, 0x90022000, 0x0000f8d9, 0x20018805, 
+    0x1c7c086f, 0xfcadf7f0, 0xf7f02000, 0xf8dffcaa, 0xfa0fa090, 0x2600fb84, 0x0000f8d9, 0x46229910, 
+    0xf805fb06, 0x3088f9b0, 0x0048eb01, 0xf014491a, 0xf8d9f88e, 0x46220000, 0xf9b09911, 0xeb013088, 
+    0x49160048, 0xf883f014, 0x46584a13, 0xe00b4b13, 0xf8521a29, 0xf842c021, 0xf853c020, 0x42491021, 
+    0x1020f843, 0xb2001c40, 0xdbf142a8, 0x0000f8d9, 0x9b024a0b, 0xf8d07881, 0xe9cd0094, 0x49070100, 
+    0xf0144805, 0x480afcb3, 0xb1e07800, 0xd01d2801, 0xe9dd2000, 0xe00d1203, 0x0004c178, 0x0004d178, 
+    0x00049978, 0x3ff00000, 0x000405f8, 0x00040560, 0x0004036b, 0x44081a89, 0x2900b241, 0xf04fdd15, 
+    0x46520000, 0xf04fe00e, 0xe7e20001, 0x30fff04f, 0xf852e7df, 0xfa433020, 0xf842f301, 0xf1003020, 
+    0xb2000001, 0xdbf442a0, 0xda0de00e, 0x46514248, 0x2000b243, 0xf851e006, 0x409a2020, 0x2020f841, 
+    0xb2001c40, 0xdbf642a0, 0x46d01e78, 0xeb0ab281, 0xf0150084, 0x2101f84d, 0x20012300, 0xe9cd461a, 
+    0x46318100, 0xfa6df7f0, 0xb2761c76, 0xf6ff2e04, 0xf8d9af73, 0xf8900000, 0x98031068, 0x1a08b007, 
+    0x4ff0e8bd, 0xf7f3b2c0, 0xb570becd, 0xf0072000, 0x2300fc6b, 0x21082203, 0x46284dfe, 0xf849f014, 
+    0x78204cfd, 0xd0282801, 0x46282300, 0x21042202, 0xf83ff014, 0x46282301, 0x46192200, 0xf839f014, 
+    0xf7f32001, 0x2301fec4, 0x220048f4, 0xf0144619, 0x48f3f830, 0x680049f3, 0x2101780a, 0x0044f9b0, 
+    0xfecff7f2, 0xf2402100, 0xf7f11000, 0x7820fca5, 0xe8bdb128, 0xf7f24070, 0x2301bca0, 0xe8bde7d5, 
+    0xf7f24070, 0xe92dbc5c, 0x48e74ff0, 0xc80fb089, 0x000fe88d, 0x466a2000, 0x90041e41, 0xf8424693, 
+    0x1c401020, 0x2804b240, 0x2000dbf8, 0xf8e0f7f2, 0x4edf4fde, 0x280a7838, 0x7830d202, 0xd0002801, 
+    0xf7f62000, 0xf8dfffa2, 0x24009350, 0xa364f8df, 0xf8df2500, 0xf8998364, 0x28010000, 0xf99ad003, 
+    0x42850000, 0x7838d00c, 0xd0692c00, 0xd202280a, 0x28017830, 0xf240d06b, 0x46282100, 0xf8aef7f7, 
+    0xb26d1c6d, 0xdbe62d04, 0xfbe6f7f2, 0x0130f242, 0xf7ea06c8, 0x2300fbfc, 0xf44f2211, 0xf04f3100, 
+    0xf0134071, 0x2001ffaf, 0xf8a2f7f2, 0xf7ffa805, 0x2000fad3, 0xf89cf7f2, 0x465d2000, 0xf10dab05, 
+    0xf8550810, 0xf8532020, 0x42911020, 0xf808dd03, 0xf8454000, 0x1c401020, 0x2804b240, 0xf242dbf1, 
+    0x06c80130, 0xfbd3f7ea, 0xb2641c64, 0xdbaf2c04, 0xf04f2000, 0xf8554480, 0x42a11020, 0x460cda00, 
+    0xb2401c40, 0xdbf62804, 0x46b946cb, 0xf8df4647, 0x250082ac, 0x0000f89b, 0xd0032801, 0x0000f99a, 
+    0xd0264285, 0x0000f899, 0xd202280a, 0x28017830, 0x5778d012, 0x2801b1a8, 0x2802d015, 0xe018d015, 
+    0xd202280a, 0x28017830, 0x4641d001, 0x4621e795, 0xf7f64628, 0xe793ff36, 0x46285779, 0xff31f7f6, 
+    0x4997e007, 0x4997e002, 0x4641e000, 0xf7f74628, 0x1c6df835, 0x2d04b26d, 0xf242dbcc, 0x06c80130, 
+    0xfb85f7ea, 0xf2432080, 0xf7ea01a0, 0xf89dfb74, 0xf99d1010, 0xf99d0013, 0xea402012, 0xf99d6101, 
+    0x04000011, 0x2002ea40, 0x20804301, 0xfb52f7ea, 0x20809900, 0xfb4ef7ea, 0x20809901, 0xfb4af7ea, 
+    0x20809902, 0xfb46f7ea, 0x20809903, 0xfb42f7ea, 0x4620b009, 0x8ff0e8bd, 0x4e6fb570, 0xb9087830, 
+    0xfb6df7f2, 0x20012100, 0xfa84f003, 0xf44f2100, 0xf7f12080, 0x2100fba1, 0xf0032001, 0x4d72fa7b, 
+    0xf424682c, 0x602820c0, 0xb9c07830, 0x4869496f, 0xf9907809, 0x29036000, 0x1cf1d022, 0xeb0117c8, 
+    0xf0207090, 0x1a080003, 0xf7f7b240, 0x2001f910, 0xfee9f7ff, 0xfb43f7f2, 0xf7f74630, 0x2001f908, 
+    0xfee1f7ff, 0xfb3bf7f2, 0x0140f242, 0xf7ea0648, 0x602cfb1e, 0xe8bd2100, 0x20014070, 0xba4af003, 
+    0x5788495b, 0xeb001c40, 0xf02272d0, 0x1a800201, 0x5608b240, 0xe92de7d9, 0xb0914ff0, 0x21002000, 
+    0x1e40900f, 0xe9cd2224, 0x900d100b, 0x49464851, 0x68043110, 0xf013a802, 0x484fe8a8, 0x28017800, 
+    0x257fd05b, 0xb134f8df, 0x900e2000, 0x46074681, 0x4a4b4680, 0x4638494b, 0xfac2f7ff, 0x4b4b484a, 
+    0x49484a47, 0x46389000, 0xfb86f7ff, 0x465a2000, 0xf8514947, 0x1c406020, 0xf108b200, 0xf8420101, 
+    0xfa0f6028, 0x281ff881, 0x4e42dbf2, 0x1007eb07, 0xeb062210, 0x483e0180, 0xf7ff468a, 0x2000fc4e, 
+    0xf85a426e, 0xf5011020, 0xf3417180, 0x42a9214f, 0x1010f824, 0x4629dd00, 0xf82442b1, 0xda001010, 
+    0xf8244631, 0x1c401010, 0x2810b200, 0x2000dde9, 0xf8344601, 0x1c402010, 0x4411b200, 0x2811b209, 
+    0x8c20dbf7, 0x84201a40, 0x78004818, 0xd210280a, 0x78004817, 0xd0022801, 0x25ffe00b, 0x2000e7a2, 
+    0xf831a902, 0xf8242010, 0x1c402010, 0x2811b200, 0x4921dbf7, 0x4a222000, 0x0e10f04f, 0x1347eb01, 
+    0xeb02491e, 0xeb011a47, 0xeb041147, 0xf9b20240, 0xe0372002, 0xf20350e6, 0x0004055c, 0xf2031012, 
+    0x000405f8, 0x0004028b, 0x0002ce60, 0x0004055e, 0x000402e2, 0x00040290, 0xfffffd00, 0xfffffe00, 
+    0xfffffa00, 0xfffffc00, 0x00057ffc, 0x000405d9, 0x00040578, 0x00040230, 0x000402fa, 0x00046978, 
+    0x00042178, 0x00041978, 0x00041968, 0x00045978, 0x00049978, 0x000415f8, 0x00041578, 0x000414f8, 
+    0x00041478, 0xdd0242aa, 0x5010f821, 0x42b2e006, 0xf821da02, 0xe0016010, 0x2010f821, 0x2010f931, 
+    0x0f40ebbe, 0x2010f82a, 0x2010f823, 0x454add03, 0xfa4fdd01, 0x1c40f982, 0x2810b200, 0xf8dfdba5, 
+    0x4638a404, 0xf96cf7f0, 0xb27f1c7f, 0xf6ff2f04, 0xf7f1af30, 0x48fcf808, 0x28007800, 0x48fbd17e, 
+    0x0000f990, 0xd0042803, 0xd0062804, 0xd0092805, 0x48f7e093, 0xb1487800, 0x48f6e08f, 0x28967800, 
+    0xe08ad304, 0x780048f3, 0xd2412882, 0x780048f2, 0x2700bbf0, 0x49f146b8, 0x465b2000, 0x2028f853, 
+    0x5200f1a2, 0x2020f841, 0xb2001c40, 0x0201f108, 0xf882fa0f, 0xdbf1281f, 0xfa0af7ff, 0xeb0748e8, 
+    0x22101107, 0x0181eb00, 0x468948e4, 0xfb65f7ff, 0xf8592000, 0xf5011020, 0xf3417180, 0x42a9214f, 
+    0x1010f824, 0x4629dd00, 0xf82442b1, 0xda001010, 0xf8244631, 0x1c401010, 0x2810b200, 0x2000dde9, 
+    0xf8344601, 0x1c402010, 0x4411b200, 0xe000b209, 0x2811e043, 0x8c20dbf5, 0x84201a40, 0x780048cd, 
+    0xd20d280a, 0x780048cf, 0xd1092801, 0xa9022000, 0x2010f831, 0x2010f824, 0xb2001c40, 0xdbf72811, 
+    0x200049c9, 0xeb014ac9, 0xeb0a1c47, 0xeb021147, 0xeb041347, 0xf9b20240, 0xe0002002, 0x42aae021, 
+    0xf821dd02, 0xe0065010, 0xda0242b2, 0x6010f821, 0xf821e001, 0xf8312010, 0xf8232010, 0xf82c2010, 
+    0x1c402010, 0x2810b200, 0x4638dbe3, 0xf8c8f7f0, 0xb27f1c7f, 0xf6ff2f04, 0x2100af7e, 0xf0034608, 
+    0x48b3f8a9, 0x28037800, 0x48aad006, 0x28fa7800, 0x48a9d802, 0xb3a07800, 0x900b2000, 0x46082100, 
+    0xf898f003, 0x4cab9a0b, 0xdd462a00, 0x230148aa, 0xf00c990c, 0x980cfd48, 0x31c8f44f, 0x0c014348, 
+    0xf0134620, 0x4da1fd0c, 0xf8df2400, 0x46568290, 0xeb082200, 0xeb061344, 0xeb051144, 0xf8311744, 
+    0xf8230012, 0xf8270012, 0x1c520012, 0x2a10b212, 0x4620dbf5, 0xf884f7f0, 0xb2641c64, 0xdbe72c04, 
+    0xe7ffe020, 0x20444994, 0x22102301, 0x46198008, 0xf7f24610, 0x4892f8c2, 0xf44f7801, 0xf7f12000, 
+    0xa80df97b, 0x488c9000, 0xaa0b2301, 0xf00ba90c, 0x2000fe10, 0xfdccf7f1, 0xf64fe7b0, 0x462071ff, 
+    0xfccdf013, 0x49884a87, 0xf7ff487d, 0x4985fb37, 0x4a874b86, 0xe9cd4888, 0x4986b100, 0xfb86f7ff, 
+    0x78004886, 0xf44fb938, 0xf6403000, 0xf7ea0103, 0xf7f6f8f2, 0x497ffb8b, 0x4b7c487f, 0xe9cd4a7c, 
+    0xe9dd0100, 0xf7ff100e, 0x2100fbc0, 0xf0034608, 0xb011f821, 0xe92de58e, 0x48794ff0, 0xac01b099, 
+    0x4f664d6c, 0x0838f10d, 0xf04f3580, 0xc80f0901, 0x000fe884, 0x68004873, 0x08468800, 0x4b5f2400, 
+    0xf8cd2200, 0x20019000, 0xf7efb261, 0x2000ff7d, 0x0cc4eb08, 0x0000e9cc, 0xf857e009, 0x1c401020, 
+    0x2300e9dc, 0xfbc1b200, 0xe9cc2301, 0x42b02300, 0x1c64dbf3, 0x2c04b2e4, 0xa816d3e1, 0xf9b9f7f3, 
+    0x46c22400, 0x0b58f10d, 0x46a14626, 0xf93b465f, 0x281e0014, 0x201edd02, 0x0014f827, 0x0014f937, 
+    0xda012800, 0x9014f827, 0x02c4eb0a, 0xca034690, 0x78124a55, 0xf0120052, 0xe9c8fdad, 0x46840100, 
+    0x46884852, 0x1014f937, 0x0011f830, 0x0c810382, 0x7e00fba2, 0xe000fb01, 0x0209fb02, 0x2100205d, 
+    0x3e00fba7, 0xe000fb02, 0x0001fb07, 0x46410d5a, 0xea421543, 0x466022c0, 0xedb2f012, 0xeb07af06, 
+    0x469002c4, 0xc2031986, 0x78004841, 0xd10c2801, 0x0034f857, 0xf9d4f7f3, 0xf248b280, 0x0fc20100, 
+    0x0200e9c8, 0xf8251840, 0xa9010b02, 0x0034f837, 0x1024f851, 0x0401f104, 0x2c04b2e4, 0xd3a58008, 
+    0x78004823, 0xd1002803, 0x463019b6, 0xf9b8f7f3, 0xb2804930, 0x6809305d, 0xd0012912, 0xd1022916, 
+    0x434821a2, 0x492c0a00, 0xb0196008, 0x4825e4e2, 0x41f0e92d, 0xf8906800, 0xf7f30068, 0x2000fa83, 
+    0xf822f007, 0x23004c13, 0x3c502203, 0x46202108, 0xfbfff013, 0x78304e19, 0x4807b110, 0xb3e87800, 
+    0xe03d2301, 0x000414f8, 0x000402fa, 0x0004028a, 0x0004033d, 0x0004055e, 0x000402ec, 0x00049978, 
+    0x000415f8, 0x000402e2, 0x00041578, 0x00041478, 0x000405d9, 0xf203513c, 0x00040740, 0x000412c8, 
+    0x0004028b, 0x00047978, 0x00046978, 0x00042178, 0x00041978, 0x00043178, 0x00042978, 0x0004055c, 
+    0x0002ce94, 0x000405f8, 0x0004036b, 0x00040dee, 0x000402e0, 0x00040238, 0x000405f4, 0x2300e7ff, 
+    0x22024620, 0xf0132104, 0x2301fbb4, 0x22004620, 0xf0134619, 0x2001fbae, 0xfa39f7f3, 0x23014c94, 
+    0xf2402208, 0x46203100, 0xfba3f013, 0x46202301, 0x46192200, 0xfb9df013, 0x488e2301, 0x46192200, 
+    0xfb97f013, 0x2101488c, 0x488c7802, 0x0000f9b0, 0xfa15f7f2, 0x1700f240, 0x46382100, 0xf80cf7f1, 
+    0x20012100, 0xfee6f002, 0x682c4d85, 0x20c0f424, 0x20016028, 0xff35f7ef, 0x46382100, 0xfffcf7f0, 
+    0x28017830, 0xf7f2d018, 0x2300f806, 0xf44f2211, 0xf04f3100, 0xf0134071, 0x2001fb55, 0xfc48f7f1, 
+    0x0130f242, 0xf7e906c8, 0x2100ff92, 0xf0024608, 0x602cfec1, 0x81f0e8bd, 0xf7ef2000, 0xf7f1ff12, 
+    0xe7e2ff9e, 0x5ff0e92d, 0xfe95f7ff, 0xf04f496e, 0x486c0891, 0x53aaf240, 0xf2404a73, 0x4e6b55dc, 
+    0x68007809, 0x29014f6a, 0xc1a8f8df, 0xe1a8f8df, 0x91a8f8df, 0xa1a8f8df, 0xb1a8f8df, 0xf9924c6b, 
+    0xd0021000, 0xd0592903, 0x2903e001, 0x2905d004, 0x2904d078, 0xe083d07a, 0x7faff5b0, 0xf240dd0b, 
+    0x428841e2, 0x4608dd00, 0xeb004b61, 0xf5a10140, 0x39ba5104, 0x287de00a, 0x207dda00, 0xeb004b5d, 
+    0xebc101c0, 0xf5a11180, 0x39aa4139, 0x3000fb01, 0x70200c00, 0x4298e05e, 0x4618dd00, 0x1140ebc0, 
+    0x0181eb06, 0x7000fb01, 0xe0170d40, 0x6151f240, 0xc100fb01, 0xe000fb01, 0x5047f3c0, 0x28917020, 
+    0xf884d94e, 0xe04b8000, 0xdd0042a8, 0xf2404628, 0xfb001151, 0xfb039301, 0x0d80a000, 0xe03f7020, 
+    0x7185f641, 0xb301fb00, 0xfb034943, 0xf3c01000, 0x70205087, 0xd93328fa, 0xe7ef20fa, 0x7fa1f5b0, 
+    0xf240db0d, 0x4288512c, 0x4608dd00, 0x21a94b3b, 0x44194341, 0xfb014b3a, 0x0d803000, 0xeba0e7b9, 
+    0x49381000, 0x0040eb00, 0x1000ebc0, 0x1040eb01, 0x4007f3c0, 0x287b7020, 0x207bd90c, 0xe00c7020, 
+    0xe003e000, 0x7fc3f5b0, 0xe7a4ddb0, 0x7f9bf5b0, 0xe7b9ddc6, 0x283cb2c0, 0xb2c0d902, 0xe7bd1dc0, 
+    0x78004829, 0xd0052801, 0xd0032802, 0x78094927, 0xd1104308, 0x0000f992, 0xd0022804, 0xd0052805, 
+    0x7820e009, 0xd9062814, 0xe003380a, 0x283c7820, 0x3008d901, 0xf6407020, 0x030d0100, 0xf7e94628, 
+    0x7821feaa, 0xe8bd4628, 0xf7e95ff0, 0x0000be93, 0xf2030444, 0xf2031012, 0x0004028b, 0x00040560, 
+    0x00057ffc, 0x000405f4, 0x000402cc, 0xfffa6eca, 0x10133079, 0xffe89b85, 0x1dcb8bb0, 0xfff063b3, 
+    0x2ec83679, 0xffa22500, 0x0004028a, 0x0004055e, 0x005d41c4, 0x00c96ba6, 0x61737224, 0xfff7c4ea, 
+    0x18e997a9, 0x00a84018, 0x000405d9, 0x0004053e, 0x5fffe92d, 0x4680f04f, 0x221e4693, 0x4681468a, 
+    0x46314603, 0x46204cfe, 0xfa2cf013, 0x464b1d25, 0x4631221e, 0xf0134628, 0xf105fa25, 0x464b0804, 
+    0x4631221e, 0xf0134640, 0x4631fa1d, 0xf108464b, 0x221e0604, 0xf0134630, 0xf04ffa15, 0x464b5700, 
+    0x4639221d, 0xf0134620, 0x221dfa0d, 0x4639464b, 0xf0134628, 0x221dfa07, 0x4639464b, 0xf0134640, 
+    0x221dfa01, 0x4639464b, 0xf0134630, 0x107ff9fb, 0x221c464b, 0x46204639, 0xf9f4f013, 0x464b221c, 
+    0x46284639, 0xf9eef013, 0x464b221c, 0x46404639, 0xf9e8f013, 0x464b221c, 0x46304639, 0xf9e2f013, 
+    0x4653123f, 0x46392214, 0xf0134620, 0x2214f9db, 0x46394653, 0xf0134628, 0x2214f9d5, 0x46394653, 
+    0xf0134640, 0x2214f9cf, 0x46394653, 0xf0134630, 0x2208f9c9, 0x4620465b, 0x46390157, 0xf9c2f013, 
+    0x465b2208, 0x46284639, 0xf9bcf013, 0x465b2208, 0x46404639, 0xf9b6f013, 0x465b2208, 0x46304639, 
+    0xf9b0f013, 0x9b03013f, 0x4639220c, 0xf0134620, 0x9b03f9a9, 0x4639220c, 0xf0134628, 0x9b03f9a3, 
+    0x4639220c, 0xf0134640, 0x9b03f99d, 0x4639b004, 0x220c4630, 0x5ff0e8bd, 0xb994f013, 0x2200b510, 
+    0x211f4604, 0x48af4603, 0xf9a3f013, 0x220048ae, 0x4623211f, 0xf99df013, 0x220048ac, 0x4623211f, 
+    0xf997f013, 0x46232200, 0x4010e8bd, 0x211f48a8, 0xb98ff013, 0x4605b570, 0x48a24603, 0x4400f647, 
+    0x4621220a, 0xf0131e80, 0x489ff984, 0x462b220a, 0x1e804621, 0xf97df013, 0x220a489c, 0x4621462b, 
+    0xf0131e80, 0x489af976, 0x4621462b, 0x4070e8bd, 0x1e80220a, 0xb96df013, 0x4604b510, 0x48914601, 
+    0xf0133810, 0x4890f94c, 0x38104621, 0xf947f013, 0x4621488e, 0xf0133810, 0x488df942, 0xe8bd4621, 
+    0x38104010, 0xb93bf013, 0x4604b510, 0x48854601, 0xf0133812, 0x4884f934, 0x38124621, 0xf92ff013, 
+    0x46214882, 0xf0133812, 0x4881f92a, 0xe8bd4621, 0x38124010, 0xb923f013, 0x4604b510, 0x48794601, 
+    0xf0133814, 0x4878f91c, 0x38144621, 0xf917f013, 0x46214876, 0xf0133814, 0x4875f912, 0xe8bd4621, 
+    0x38144010, 0xb90bf013, 0x4604b510, 0x486d4601, 0xf0133816, 0x486cf904, 0x38164621, 0xf8fff013, 
+    0x4621486a, 0xf0133816, 0x4869f8fa, 0xe8bd4621, 0x38164010, 0xb8f3f013, 0x4604b510, 0x48614601, 
+    0xf0133826, 0x4860f8ec, 0x38264621, 0xf8e7f013, 0x4621485e, 0xf0133826, 0x485df8e2, 0xe8bd4621, 
+    0x38264010, 0xb8dbf013, 0x5fffe92d, 0xf2484d59, 0x46920400, 0x220f468b, 0x46034681, 0x46284621, 
+    0xf8e7f013, 0x0600f247, 0x220c465b, 0x46284631, 0xf8dff013, 0x465310f7, 0x46392209, 0xf0134628, 
+    0xf240f8d8, 0x9b031880, 0x46412207, 0xf0134628, 0x9b0ef8d0, 0x21602205, 0xf0134628, 0x9b0ff8ca, 
+    0x21102204, 0xf0134628, 0x9b10f8c4, 0x21082203, 0xf0134628, 0x9b11f8be, 0x21072200, 0xf0134628, 
+    0x4d3df8b8, 0x464b220f, 0x46284621, 0xf8b1f013, 0x465b220c, 0x46284631, 0xf8abf013, 0x46532209, 
+    0x46284639, 0xf8a5f013, 0x22079b03, 0x46284641, 0xf89ff013, 0x22059b0e, 0x46282160, 0xf899f013, 
+    0x22049b0f, 0x46282110, 0xf893f013, 0x22039b10, 0x46282108, 0xf88df013, 0x22009b11, 0x46282107, 
+    0xf887f013, 0x220f4d25, 0x4621464b, 0xf0134628, 0x220cf880, 0x4631465b, 0xf0134628, 0x2209f87a, 
+    0x46394653, 0xf0134628, 0x9b03f874, 0x46412207, 0xf0134628, 0x9b0ef86e, 0x21602205, 0xf0134628, 
+    0x9b0ff868, 0x21102204, 0xf0134628, 0x9b10f862, 0x21082203, 0xf0134628, 0x9b11f85c, 0x21072200, 
+    0xf0134628, 0x4621f856, 0x220f4c0d, 0x4620464b, 0xf84ff013, 0x465b220c, 0x46204631, 0x0000e012, 
+    0xf10008b0, 0xf203c668, 0xf203ce68, 0xf203d668, 0xf203de68, 0xf203c486, 0xf203cc86, 0xf203d486, 
+    0xf203dc86, 0xf835f013, 0x46532209, 0x46204639, 0xf82ff013, 0x22079b03, 0x46204641, 0xf829f013, 
+    0x22059b0e, 0x46202160, 0xf823f013, 0x22049b0f, 0x46202110, 0xf81df013, 0x22039b10, 0x46202108, 
+    0xf817f013, 0xb0049b11, 0x22004620, 0x5ff0e8bd, 0xf0132107, 0xe92db80e, 0x460541f0, 0x36fff240, 
+    0x460f0044, 0xf8312200, 0x46313015, 0x442048fd, 0xfffff012, 0x0545eb07, 0x220048fb, 0x44204631, 
+    0xf01288eb, 0x48f9fff6, 0x89ab2200, 0x44204631, 0xffeff012, 0x463148f6, 0x22008a6b, 0xe8bd4420, 
+    0xf01241f0, 0xeb00bfe6, 0xb57000c0, 0x48ed0045, 0x76fff240, 0x3840460c, 0x22004631, 0xf0124428, 
+    0x8020ffe6, 0x48e82200, 0x38404631, 0xf0124428, 0x80a0ffde, 0x48e52200, 0x38404631, 0xf0124428, 
+    0x8120ffd6, 0x48e22200, 0x38404631, 0xf0124428, 0x81a0ffce, 0x48db2200, 0x383e4631, 0xf0124428, 
+    0x8060ffc6, 0x48d82200, 0x383e4631, 0xf0124428, 0x80e0ffbe, 0x48d52200, 0x383e4631, 0xf0124428, 
+    0x8160ffb6, 0x48d22200, 0x383e4631, 0xf0124428, 0x2100ffae, 0x4500f240, 0x200081e0, 0x0381eb04, 
+    0x2010f933, 0xdb0142aa, 0x6200f5a2, 0x2010f823, 0xb2401c40, 0xdbf32802, 0xb2491c49, 0xdbec2904, 
+    0xb510bd70, 0x46034604, 0x220048be, 0x30302101, 0xff7ff012, 0x220048bc, 0x46232101, 0xf0123030, 
+    0x48baff78, 0x21012200, 0x30304623, 0xff71f012, 0x220048b7, 0x46232101, 0x4010e8bd, 0xf0123030, 
+    0xe92dbf68, 0x4daf43f8, 0x0000f44f, 0x4faf4eae, 0xf8df3534, 0x363482bc, 0x37344cae, 0x0834f108, 
+    0xe0069000, 0x46222102, 0xf7f04668, 0x2801fc6a, 0x2200d01b, 0x21014628, 0xff59f012, 0xd0f12800, 
+    0x46302200, 0xf0122101, 0x2800ff52, 0x2200d0ea, 0x21014638, 0xff4bf012, 0xd0e32800, 0x46402200, 
+    0xf0122101, 0x2800ff44, 0xe8bdd0dc, 0xe92d83f8, 0xeb0041f0, 0xf24000c0, 0x880b77ff, 0x00444615, 
+    0x22004890, 0x3840460e, 0x44204639, 0xff21f012, 0x2200488d, 0x463988b3, 0x44203840, 0xff19f012, 
+    0x2200488a, 0x46398933, 0x44203840, 0xff11f012, 0x22004887, 0x463989b3, 0x44203840, 0xff09f012, 
+    0x22004880, 0x46398873, 0x4420383e, 0xff01f012, 0x2200487d, 0x463988f3, 0x4420383e, 0xfef9f012, 
+    0x2200487a, 0x46398973, 0x4420383e, 0xfef1f012, 0x22004877, 0x463989f3, 0x4420383e, 0xfee9f012, 
+    0x22004870, 0x4639882b, 0x4420383c, 0xfee1f012, 0x2200486d, 0x463989eb, 0x4420383c, 0xfed9f012, 
+    0x2200486a, 0x46398bab, 0x4420383c, 0xfed1f012, 0x22004867, 0x46398d6b, 0x4420383c, 0xfec9f012, 
+    0x22004860, 0x4639886b, 0x4420383a, 0xfec1f012, 0x2200485d, 0x46398a2b, 0x4420383a, 0xfeb9f012, 
+    0x2200485a, 0x46398beb, 0x4420383a, 0xfeb1f012, 0x22004857, 0x46398dab, 0x4420383a, 0xfea9f012, 
+    0x22004850, 0x463988ab, 0x44203838, 0xfea1f012, 0x2200484d, 0x46398a6b, 0x44203838, 0xfe99f012, 
+    0x2200484a, 0x46398c2b, 0x44203838, 0xfe91f012, 0x22004847, 0x46398deb, 0x44203838, 0xfe89f012, 
+    0x22004840, 0x463988eb, 0x44203836, 0xfe81f012, 0x2200483d, 0x46398aab, 0x44203836, 0xfe79f012, 
+    0x2200483a, 0x46398c6b, 0x44203836, 0xfe71f012, 0x22004837, 0x46398e2b, 0x44203836, 0xfe69f012, 
+    0x22004830, 0x4639892b, 0x44203834, 0xfe61f012, 0x2200482d, 0x46398aeb, 0x44203834, 0xfe59f012, 
+    0x2200482a, 0x46398cab, 0x44203834, 0xfe51f012, 0x22004827, 0x46398e6b, 0x44203834, 0xfe49f012, 
+    0x22004820, 0x4639896b, 0x44203832, 0xfe41f012, 0x2200481d, 0x46398b2b, 0x44203832, 0xfe39f012, 
+    0x2200481a, 0x46398ceb, 0x44203832, 0xfe31f012, 0x22004817, 0x46398eab, 0x44203832, 0xfe29f012, 
+    0x22004810, 0x463989ab, 0x44203830, 0xfe21f012, 0x2200480d, 0x46398b6b, 0x44203830, 0xfe19f012, 
+    0x2200480a, 0x46398d2b, 0x44203830, 0xfe11f012, 0x22004807, 0x46398eeb, 0x44203830, 0x41f0e8bd, 
+    0xbe07f012, 0xf203c450, 0xf203cc50, 0xf203d450, 0xf203dc50, 0xf203517a, 0x2200b510, 0x217f4604, 
+    0x48fd4603, 0xfdf5f012, 0x220048fc, 0x4623217f, 0xfdeff012, 0x220048fa, 0x4623217f, 0xfde9f012, 
+    0x46232200, 0x4010e8bd, 0x217f48f6, 0xbde1f012, 0x47f0e92d, 0x22004ff0, 0x213f8983, 0x46041ebf, 
+    0xf0124638, 0x4dedfdd6, 0x8ba32200, 0x1ead213f, 0xf0124628, 0xf8dffdce, 0x220083a8, 0x213f8da3, 
+    0x0802f1a8, 0xf0124640, 0xf8dffdc4, 0x22009398, 0x213f8fa3, 0x0902f1a9, 0xf0124648, 0xf643fdba, 
+    0x89e37600, 0x46312208, 0xf0124638, 0x8be3fdb2, 0x46312208, 0xf0124628, 0x8de3fdac, 0x46312208, 
+    0xf0124640, 0x8fe3fda6, 0x46484631, 0x47f0e8bd, 0xf0122208, 0xe92dbd9e, 0x4fcf47f0, 0x89032200, 
+    0x1f3f213f, 0x46384604, 0xfd93f012, 0x22004dcb, 0x213f8b23, 0x46281f2d, 0xfd8bf012, 0x8320f8df, 
+    0x8d232200, 0xf1a8213f, 0x46400804, 0xfd81f012, 0x9310f8df, 0x8f232200, 0xf1a9213f, 0x46480904, 
+    0xfd77f012, 0x7600f643, 0x22088963, 0x46384631, 0xfd6ff012, 0x22088b63, 0x46284631, 0xfd69f012, 
+    0x22088d63, 0x46404631, 0xfd63f012, 0x46318f63, 0xe8bd4648, 0x220847f0, 0xbd5bf012, 0x47f0e92d, 
+    0x22004fad, 0x213f8883, 0x46041fbf, 0xf0124638, 0x4daafd50, 0x8aa32200, 0x1fad213f, 0xf0124628, 
+    0xf8dffd48, 0x2200829c, 0x213f8ca3, 0x0806f1a8, 0xf0124640, 0xf8dffd3e, 0x2200928c, 0x213f8ea3, 
+    0x0906f1a9, 0xf0124648, 0xf643fd34, 0x88e37600, 0x46312208, 0xf0124638, 0x8ae3fd2c, 0x46312208, 
+    0xf0124628, 0x8ce3fd26, 0x46312208, 0xf0124640, 0x8ee3fd20, 0x46484631, 0x47f0e8bd, 0xf0122208, 
+    0xe92dbd18, 0x4f8c47f0, 0x88032200, 0x3f08213f, 0x46384604, 0xfd0df012, 0x22004d88, 0x213f8a23, 
+    0x46283d08, 0xfd05f012, 0x8214f8df, 0x8c232200, 0xf1a8213f, 0x46400808, 0xfcfbf012, 0x9204f8df, 
+    0x8e232200, 0xf1a9213f, 0x46480908, 0xfcf1f012, 0x7600f643, 0x22088863, 0x46384631, 0xfce9f012, 
+    0x22088a63, 0x46284631, 0xfce3f012, 0x22088c63, 0x46404631, 0xfcddf012, 0x46318e63, 0xe8bd4648, 
+    0x220847f0, 0xbcd5f012, 0x8803b510, 0x213e2201, 0x486d4604, 0xfccdf012, 0x22018863, 0x213e486b, 
+    0xfcc7f012, 0x220188a3, 0x213e4869, 0xfcc1f012, 0x220188e3, 0x4010e8bd, 0x213e4866, 0xbcb9f012, 
+    0x2201b510, 0x213e4604, 0x485f4603, 0xfcb1f012, 0x2201485e, 0x4623213e, 0xfcabf012, 0x2201485c, 
+    0x4623213e, 0xfca5f012, 0x46232201, 0x4010e8bd, 0x213e4858, 0xbc9df012, 0x4604b510, 0x48524601, 
+    0xf012301a, 0x4851fc7c, 0x301a4621, 0xfc77f012, 0x4621484f, 0xf012301a, 0x484efc72, 0xe8bd4621, 
+    0x301a4010, 0xbc6bf012, 0xb283b510, 0x48424604, 0x217f2200, 0xf01230a2, 0x483ffc7c, 0x2200b2a3, 
+    0x30b2217f, 0xfc75f012, 0xb2a3483b, 0x217f2200, 0xf01230c2, 0x4839fc6e, 0x2200b2a3, 0x30a2217f, 
+    0xfc67f012, 0xb2a34835, 0x217f2200, 0xf01230b2, 0x4832fc60, 0x2200b2a3, 0x30c2217f, 0xfc59f012, 
+    0xb2a3482f, 0x217f2200, 0xf01230a2, 0x482cfc52, 0x2200b2a3, 0x30b2217f, 0xfc4bf012, 0xb2a34828, 
+    0x217f2200, 0xf01230c2, 0x4826fc44, 0x2200b2a3, 0x30a2217f, 0xfc3df012, 0xb2a34822, 0x217f2200, 
+    0xf01230b2, 0x481ffc36, 0x2200b2a3, 0xe8bd217f, 0x30c24010, 0xbc2df012, 0x4604b510, 0x481a4601, 
+    0xf0123038, 0x4819fc0c, 0x30384621, 0xfc07f012, 0x46214817, 0xf0123038, 0x4816fc02, 0xe8bd4621, 
+    0x30384010, 0xbbfbf012, 0x4604b510, 0x480e4601, 0xf0123008, 0x480dfbf4, 0x30084621, 0xfbeff012, 
+    0x4621480b, 0xf0123008, 0x480afbea, 0xe8bd4621, 0x30084010, 0xbbe3f012, 0xf203c468, 0xf203cc68, 
+    0xf203d468, 0xf203dc68, 0xf203c640, 0xf203ce40, 0xf203d640, 0xf203de40, 0xf241b570, 0x46050400, 
+    0x4603220c, 0x462148fe, 0xfbe3f012, 0x220c48fd, 0x4621462b, 0xfbddf012, 0x220c48fb, 0x4621462b, 
+    0xfbd7f012, 0x4621462b, 0x4070e8bd, 0x220c48f7, 0xbbcff012, 0x4604b510, 0x48f14601, 0xf0123030, 
+    0x48f0fbae, 0x30304621, 0xfba9f012, 0x462148ee, 0xf0123030, 0x48edfba4, 0xe8bd4621, 0x30304010, 
+    0xbb9df012, 0xb283b510, 0x48e54604, 0x217f2200, 0xf01238be, 0x48e2fbae, 0x2200b2a3, 0x38ae217f, 
+    0xfba7f012, 0xb2a348de, 0x217f2200, 0xf012389e, 0x48dcfba0, 0x2200b2a3, 0x38be217f, 0xfb99f012, 
+    0xb2a348d8, 0x217f2200, 0xf01238ae, 0x48d5fb92, 0x2200b2a3, 0x389e217f, 0xfb8bf012, 0xb2a348d2, 
+    0x217f2200, 0xf01238be, 0x48cffb84, 0x2200b2a3, 0x38ae217f, 0xfb7df012, 0xb2a348cb, 0x217f2200, 
+    0xf012389e, 0x48c9fb76, 0x2200b2a3, 0x38be217f, 0xfb6ff012, 0xb2a348c5, 0x217f2200, 0xf01238ae, 
+    0x48c2fb68, 0x2200b2a3, 0xe8bd217f, 0x389e4010, 0xbb5ff012, 0xb283b510, 0x48bd4604, 0x217f2200, 
+    0xfb57f012, 0xb2a348ba, 0x217f2200, 0xf0123010, 0x48b7fb50, 0x2200b2a3, 0x3020217f, 0xfb49f012, 
+    0x48b4b2a3, 0x217f2200, 0xfb43f012, 0xb2a348b1, 0x217f2200, 0xf0123010, 0x48aefb3c, 0x2200b2a3, 
+    0x3020217f, 0xfb35f012, 0x48abb2a3, 0x217f2200, 0xfb2ff012, 0xb2a348a8, 0x217f2200, 0xf0123010, 
+    0x48a5fb28, 0x2200b2a3, 0x3020217f, 0xfb21f012, 0x48a2b2a3, 0x217f2200, 0xfb1bf012, 0xb2a3489f, 
+    0x217f2200, 0xf0123010, 0x489cfb14, 0x2200b2a3, 0xe8bd217f, 0x30204010, 0xbb0bf012, 0x4604b510, 
+    0x488f4603, 0x21402206, 0xf012300c, 0x488dfb02, 0x21402206, 0x300c4623, 0xfafbf012, 0x2206488a, 
+    0x46232140, 0xf012300c, 0x4888faf4, 0x21402206, 0xe8bd4623, 0x300c4010, 0xbaebf012, 0xb283b510, 
+    0x48834604, 0x217f2200, 0xf0121f00, 0x4880fae2, 0x2200b2a3, 0x300c217f, 0xfadbf012, 0xb2a3487c, 
+    0x217f2200, 0xf012301c, 0x487afad4, 0x2200b2a3, 0x1f00217f, 0xfacdf012, 0xb2a34876, 0x217f2200, 
+    0xf012300c, 0x4873fac6, 0x2200b2a3, 0x301c217f, 0xfabff012, 0xb2a34870, 0x217f2200, 0xf0121f00, 
+    0x486dfab8, 0x2200b2a3, 0x300c217f, 0xfab1f012, 0xb2a34869, 0x217f2200, 0xf012301c, 0x4867faaa, 
+    0x2200b2a3, 0x1f00217f, 0xfaa3f012, 0xb2a34863, 0x217f2200, 0xf012300c, 0x4860fa9c, 0x2200b2a3, 
+    0xe8bd217f, 0x301c4010, 0xba93f012, 0x4604b510, 0x48574603, 0x21012200, 0xf0123884, 0x4855fa8a, 
+    0x21012200, 0x38844623, 0xfa83f012, 0x22004852, 0x46232101, 0xf0123884, 0x4850fa7c, 0x21012200, 
+    0xe8bd4623, 0x38844010, 0xba73f012, 0x2200b510, 0x21014604, 0x48424603, 0xfa6bf012, 0x22004841, 
+    0x46232101, 0xfa65f012, 0x2200483f, 0x46232101, 0xfa5ff012, 0x46232200, 0x4010e8bd, 0x2101483b, 
+    0xba57f012, 0x4604b510, 0x48354603, 0x21012200, 0xf012300e, 0x4833fa4e, 0x21012200, 0x300e4623, 
+    0xfa47f012, 0x22004830, 0x46232101, 0xf012300e, 0x482efa40, 0x21012200, 0xe8bd4623, 0x300e4010, 
+    0xba37f012, 0x4605b570, 0x48254603, 0x0400f244, 0x4621220e, 0xf012300e, 0x4822fa2c, 0x462b220e, 
+    0x300e4621, 0xfa25f012, 0x220e481f, 0x4621462b, 0xf012300e, 0x481dfa1e, 0x4621462b, 0x4070e8bd, 
+    0x300e220e, 0xba15f012, 0x4ff0e92d, 0x11f4f240, 0x070cb0bb, 0xf7e84620, 0xf241fe2e, 0x462071a0, 
+    0xfe18f7e8, 0x46204e16, 0xf7e84631, 0x2001fe13, 0xffc8f7ff, 0xf7ff2001, 0x2000ffa5, 0xfa71f7ff, 
+    0x23064810, 0x211e2201, 0xf9f3f012, 0x21012300, 0x4608461a, 0xff9cf7fe, 0xf7ff2001, 0xe013ff77, 
+    0xf203c640, 0xf203ce40, 0xf203d640, 0xf203de40, 0xf203c506, 0xf203cd06, 0xf203d506, 0xf203dd06, 
+    0xdcba01f5, 0xf203e80c, 0xf7ff2000, 0x2001ff5f, 0xff5cf7ff, 0xf7ff2000, 0x2008ff39, 0xf83af7ff, 
+    0xf7ff2008, 0xf240f81b, 0xf7ff10e0, 0xf240f8b5, 0x462011f4, 0xfddff7e8, 0x71a1f241, 0xf7e84620, 
+    0x4631fdc9, 0xf7e84620, 0x2040fdc5, 0xfec6f7ff, 0xf7ff2001, 0x20fffea3, 0xf886f7ff, 0xf7ff20ff, 
+    0x1527f86b, 0xf7ff4638, 0x2000f84f, 0xf834f7ff, 0xf7ff2000, 0x2001fd01, 0xfcfef7ff, 0x20402100, 
+    0xfe1af7ef, 0xf7ff2000, 0x20fffcf7, 0xf86cf7ff, 0xf7ff20ff, 0x2000f851, 0xf836f7ff, 0xf7ff2000, 
+    0x2000f81b, 0xfe26f7ff, 0x11f4f240, 0xf7e84620, 0xf241fda2, 0x462071a3, 0xfd8cf7e8, 0x46204631, 
+    0xfd88f7e8, 0xf7ff2000, 0x14e0fdbd, 0xfd5cf7ff, 0xf7ff20ff, 0x20fff849, 0xf82ef7ff, 0xf7ff1420, 
+    0xf640f813, 0x46287500, 0xfff6f7fe, 0xf7ff2001, 0xf240fd73, 0x46401800, 0xfd8cf7ff, 0xf7ff1460, 
+    0xf642fd2b, 0xf7ff0000, 0x2100fd27, 0xf7ef4640, 0x2100fdd3, 0xf7ef4640, 0x2000fdcf, 0xfd5cf7ff, 
+    0xf7ff2000, 0x2000fd31, 0xfd16f7ff, 0xf7ff20ff, 0x20fff81b, 0xf800f7ff, 0xf7fe2000, 0x2000ffe5, 
+    0xffcaf7fe, 0x11f4f240, 0xf7e84620, 0xf241fd54, 0x462071a4, 0xfd3ef7e8, 0x46204631, 0xfd3af7e8, 
+    0xf7ff2040, 0x20fffca1, 0xfffef7fe, 0xf7fe20ff, 0x4638ffe3, 0xffc8f7fe, 0xf7fe4628, 0x2000ffad, 
+    0xfc7af7ff, 0xf7ff4640, 0x2100fc77, 0xf7ef2040, 0x2000fd93, 0xfc70f7ff, 0xf7fe20ff, 0x20ffffe5, 
+    0xffcaf7fe, 0xf7fe2000, 0x2000ffaf, 0xff94f7fe, 0x11f4f240, 0xf7e84620, 0xf241fd1e, 0x462071a5, 
+    0xfd08f7e8, 0x46204631, 0xfd04f7e8, 0xf7ff2000, 0x2003fc37, 0x94002400, 0x46212302, 0x4002e9cd, 
+    0x46202206, 0xf7fe9401, 0xf244ffef, 0xf7fe0080, 0x4628ff8b, 0xff70f7fe, 0x22012000, 0x540aa93a, 
+    0xf821a930, 0x1c404010, 0x2804b240, 0xf8dfdbf6, 0xf04f93fc, 0xf8df0800, 0xf8dfa3f8, 0x4efeb3f8, 
+    0x20002100, 0x02c1eb01, 0x0282eb06, 0xf8422300, 0x1c403020, 0x2802b240, 0x1c49dbf8, 0x2904b249, 
+    0x2700dbef, 0xe06b2400, 0xd0692c00, 0x10fff240, 0xff8af7fe, 0x10fef240, 0xff6ef7fe, 0x20402100, 
+    0xfd2af7ef, 0xf7ff2001, 0x2100f91c, 0xf7ef2040, 0xf7fffd23, 0x2100f936, 0xf7ef2040, 0x4648fd1d, 
+    0xf87af012, 0x1024f856, 0xf080fa01, 0x0024f846, 0xf0124650, 0xeb06f871, 0x6a690584, 0xf080fa01, 
+    0x46586268, 0xf868f012, 0xfa016ca9, 0x64a8f080, 0xf01248da, 0x6ee9f861, 0xf080fa01, 0x200066e8, 
+    0xf8eff7ff, 0xb2641c64, 0xdbbd2c02, 0xb27f1c7f, 0xdbb72f10, 0x20002100, 0x02c1eb01, 0x0282eb06, 
+    0x3020f852, 0x111b3308, 0x3020f842, 0xb2401c40, 0xdbf52802, 0xb2491c49, 0xdbec2904, 0xab3a2000, 
+    0x01c0eb00, 0x0281eb06, 0x1021f856, 0x1a616854, 0xd5006091, 0x60914249, 0x2a015c1a, 0xe018d005, 
+    0xf7fe20ff, 0x20ffff21, 0xf5b1e796, 0xda045fd0, 0xf831a930, 0x1c522010, 0xf5b1e006, 0xdd065ff0, 
+    0xf831a930, 0x1e522010, 0x2010f821, 0x2100e001, 0x1c405419, 0x2804b240, 0xa830dbd2, 0xfb54f7ff, 
+    0x0001f108, 0xf880fa0f, 0x0f0ff1b8, 0xaf58f6ff, 0x25002004, 0x23029500, 0xe9cd462a, 0x46295002, 
+    0x95014628, 0xff20f7fe, 0xf7fe20ff, 0x20fffeed, 0xfed2f7fe, 0xf7fe2000, 0x2000feb7, 0xfe9cf7fe, 
+    0x11f4f240, 0x4620070c, 0xfc25f7e8, 0x71a6f241, 0xf7e84620, 0x499afc0f, 0xf7e84620, 0x2100fc0b, 
+    0x2000ab04, 0x1201eb03, 0x5010f822, 0xb2401c40, 0xdbf92808, 0xb2491c49, 0xdbf22904, 0xf7ff4618, 
+    0xa804fad0, 0xfa8af7ff, 0xf7ffa804, 0xa804fa44, 0xf9fef7ff, 0xf7ff2000, 0x20fff9df, 0xfeb4f7fe, 
+    0xf7fe20ff, 0xf645fe99, 0xf7fe0080, 0xf640fe7d, 0xf7fe7000, 0x2002fe61, 0x21009500, 0x23019501, 
+    0x5002e9cd, 0x46082206, 0xfecef7fe, 0x46a82100, 0x46422000, 0x03c1eb01, 0x0383eb06, 0xf8434690, 
+    0x1c402020, 0x2804b240, 0x1c49dbf8, 0x2904b249, 0x2700dbee, 0xe0072400, 0x2c01b134, 0x2c02d007, 
+    0x2c03d008, 0xe008d10d, 0x7000f640, 0xf640e007, 0xe0047001, 0x7002f640, 0xf640e001, 0xf7fe7003, 
+    0x2100fe2b, 0xf7ef2040, 0x2001fc17, 0xf809f7ff, 0x20402100, 0xfc10f7ef, 0xf823f7ff, 0x20402100, 
+    0xfc0af7ef, 0xf0114859, 0xf856ff67, 0xfa011024, 0xf846f080, 0x48560024, 0xff5ef011, 0x0584eb06, 
+    0xfa016a69, 0x6268f080, 0xf0114852, 0x6ca9ff55, 0xf080fa01, 0x485164a8, 0xff4ef011, 0xfa016ee9, 
+    0x66e8f080, 0xf7fe2000, 0x1c64ffdc, 0x2c04b264, 0x1c7fdbb2, 0x2f80b23f, 0x2400dbac, 0x2900f44f, 
+    0xad2caf04, 0x02c4eb04, 0x0082eb06, 0x2022f856, 0x3102e9d0, 0x1acb6840, 0x18801a18, 0x0024f845, 
+    0x2000d401, 0x4240e000, 0xf8454548, 0xdb000024, 0xab2c483c, 0xf8431a89, 0x03400024, 0x11cff341, 
+    0xda002900, 0xb2094249, 0xd06d2900, 0xf101fb11, 0xf0120889, 0xa932fec5, 0x0200f242, 0x0024f841, 
+    0x01c0eb00, 0x1100eb01, 0x1181eb02, 0xeb070b8b, 0x800b1104, 0x1300eb00, 0x1340eb03, 0x1383eb02, 
+    0x804b0b9b, 0x1340eb00, 0x2300eb03, 0x1303eb02, 0x808b0b9b, 0x1369f240, 0xeb024343, 0x0b9b1303, 
+    0xebc080cb, 0xebc31380, 0xeb0203c3, 0x0b9b1303, 0xeb00810b, 0xeb031300, 0xeb022340, 0x0b9b1303, 
+    0xf240814b, 0x43432371, 0x1303eb02, 0x818b0b9b, 0x23d9f240, 0xeb024358, 0x0b801000, 0x200081c8, 
+    0x1204eb07, 0x1010f832, 0xd3002940, 0xf822213f, 0x1c401010, 0x2808b240, 0x1c64dbf4, 0x2c04b264, 
+    0xa804db80, 0xf9bdf7ff, 0xe00ea804, 0xf203c4a0, 0xf203cca0, 0xf203d4a0, 0x0004e288, 0xf203dca0, 
+    0xdcba01f5, 0x0007ffff, 0xf7ffe086, 0xa804f967, 0xf921f7ff, 0xf7ffa804, 0x2000f8db, 0xf8bcf7ff, 
+    0xf8cd2404, 0x22008000, 0x8004f8cd, 0x46112302, 0x8402e9cd, 0xf7fe4610, 0x20fffdb7, 0xfd84f7fe, 
+    0xf7fe20ff, 0x2000fd69, 0xfd4ef7fe, 0xf7fe2000, 0xf240fd33, 0x070d11f4, 0xf7e84628, 0xf241fabc, 
+    0x462871a7, 0xfaa6f7e8, 0x462849f8, 0xfaa2f7e8, 0xf7fe20ff, 0x20fffd69, 0xfd4ef7fe, 0x0080f244, 
+    0xfd32f7fe, 0x7000f640, 0xfd16f7fe, 0x0900f04f, 0xab142100, 0xad22460c, 0x02c1ebc1, 0xeb032000, 
+    0xf8220242, 0x1c404010, 0x2808b240, 0x2000dbf9, 0x0281eb05, 0x4010f822, 0xb2401c40, 0xdbf92802, 
+    0xb2491c49, 0xdbe72904, 0x4629461a, 0xf7fe4648, 0x2002ff2e, 0x01fff009, 0xe9cd4603, 0x21001400, 
+    0x4002e9cd, 0x46082206, 0xfd5ef7fe, 0x21004bd8, 0xeb012000, 0xeb0302c1, 0x46980282, 0x4020f842, 
+    0xb2401c40, 0xdbf82809, 0xb2491c49, 0xdbef2904, 0x25002700, 0xe02e462c, 0x46412000, 0x1204eb07, 
+    0x1010f822, 0xb2401c40, 0xdbf92808, 0xb314e747, 0xd0232c01, 0xd07d2c02, 0xd01f2c03, 0xd07a2c04, 
+    0xd01b2c05, 0xd0772c06, 0xd0172c07, 0xd0742c08, 0xd0132c09, 0xd0712c0a, 0xd00f2c0b, 0xd06e2c0c, 
+    0xd00b2c0d, 0xd06b2c0e, 0xd0072c0f, 0xd0682c10, 0xd1092c11, 0xf240e002, 0xe00010ff, 0xf7fe20ff, 
+    0x20fffce3, 0xfcc8f7fe, 0x20402100, 0xfa84f7ef, 0xf7fe2001, 0x2100fe76, 0xf7ef2040, 0xf7fefa7d, 
+    0x2100fe90, 0xf7ef2040, 0x07e0fa77, 0xd07c48a9, 0xfdd2f011, 0x1025f858, 0x4646b200, 0xf8481a08, 
+    0x48a50025, 0xfdc8f011, 0x0685eb06, 0x6a71b200, 0x62701a08, 0xf01148a1, 0x6cb1fdbf, 0x1a08b200, 
+    0x489f64b0, 0xfdb8f011, 0xb2006ef1, 0x66f01a08, 0xb26d1c6d, 0xf7fe2000, 0x1c64fe44, 0x2c12b264, 
+    0x1c7fdb95, 0x2f80b23f, 0x2100db83, 0x20004643, 0x02c1eb01, 0x0282eb03, 0x4020f852, 0x11e43440, 
+    0x4020f842, 0xb2401c40, 0xdbf52809, 0xb2491c49, 0xe0072904, 0xe0e6e0e1, 0xe0f2e0ec, 0xe0fee0f8, 
+    0xe124e11e, 0x2100dbe3, 0xab364a81, 0x00c1eb01, 0x4020f852, 0x0280eb02, 0x68509403, 0xf8434420, 
+    0x68960021, 0xe00cf8d2, 0x46f30333, 0xf7f0fb93, 0x030eeb06, 0xfb94031c, 0xf504f4f0, 0x69145800, 
+    0x032d191d, 0xf5f0fb95, 0x5500f505, 0x69559500, 0x0c05eb04, 0x0c43eb0c, 0x3c0cea4f, 0xfef0fb9c, 
+    0x4e80f50e, 0xe004f8cd, 0xe0f7e000, 0xe018f8d2, 0x1606ebc6, 0x160beb06, 0x0c0eeb05, 0xea4f46f2, 
+    0xeb0e0e83, 0x44f40e44, 0x0e84ea4f, 0x03c3eb0a, 0x0e45eb0e, 0xf8d24473, 0xeba6e01c, 0xf8cd060b, 
+    0xeb06e008, 0x6a1204c4, 0x0485eb04, 0x044aeb04, 0x44744473, 0x3c0cea4f, 0x9c034422, 0xfb9c031b, 
+    0x0312fcf0, 0xf3f0fb93, 0xf2f0fb92, 0xe9dd0324, 0xfb945e00, 0xf507faf0, 0xeb075780, 0xeb050008, 
+    0xf8df040e, 0x4420e144, 0x4c00f50c, 0xf5034460, 0x44183380, 0x32f0f502, 0xf5004410, 0x033c5080, 
+    0xfb941100, 0x4c47f5f0, 0xf5caaf14, 0xfa045b80, 0xebc1f685, 0xea4f05c1, 0xf8273408, 0xfb946015, 
+    0xeb07f6f0, 0xfa0e0445, 0x8066f686, 0x032d9d00, 0xf6f0fb95, 0xfa0e031b, 0x80a5f586, 0xe004f8dd, 
+    0x350eea4f, 0xf6f0fb95, 0xfa054d38, 0x80e5f586, 0x350cea4f, 0xf6f0fb95, 0xfa054d35, 0x8125f586, 
+    0xf5f0fb93, 0x03124b33, 0xf385fa03, 0xfb928163, 0x4a31f3f0, 0xf283fa02, 0xea4f81a2, 0xf240320a, 
+    0xfb923aff, 0x4a2df3f0, 0xf583fa02, 0xf823ab22, 0xea4f5021, 0xf240350b, 0xfb954b00, 0xfa02f0f0, 
+    0xeb03f080, 0x4b1f0281, 0x20008050, 0x2010f934, 0xdb75455a, 0xa010f824, 0x20ffe076, 0xfba4f7fe, 
+    0x10fef240, 0xf240e6be, 0xf7fe30fe, 0xf240fb9d, 0xe6b730fd, 0x70fcf240, 0xfb96f7fe, 0x70fbf240, 
+    0xf640e6b0, 0xf7fe40fb, 0xf640fb8f, 0xe6a940f7, 0x40f3f641, 0xfb88f7fe, 0x40eff641, 0xf643e6a2, 
+    0xf7fe40e3, 0xf643fb81, 0xe69b40df, 0xdcba01f5, 0x0004e288, 0xf203c4a0, 0xf203cca0, 0xf203d4a0, 
+    0xf203dca0, 0xfffffc00, 0xfffff800, 0xfffff000, 0xffffe000, 0xffffc000, 0xffff8800, 0xfffffe00, 
+    0x40c3f647, 0xfb60f7fe, 0x40bff647, 0xf64fe67a, 0xf7fe0087, 0xf64ffb59, 0xe673007f, 0xfc5cf011, 
+    0x1025f858, 0xfa014646, 0xf848f080, 0x48fe0025, 0xfc52f011, 0x0685eb06, 0xfa016a71, 0x6270f080, 
+    0xf01148fa, 0x6cb1fc49, 0xf080fa01, 0x48f864b0, 0xfc42f011, 0xfa016ef1, 0x66f0f080, 0xe7ffe68a, 
+    0xda01429a, 0x3010f824, 0xb2401c40, 0xf6ff2807, 0x1c49af7d, 0x2904b249, 0xaea6f6ff, 0x463aa922, 
+    0xf7fe4648, 0xf109fd14, 0xfa4f0001, 0xf1b9f980, 0xf6ff0f03, 0x2104adbd, 0x90002000, 0x46022302, 
+    0x0102e9cd, 0x90014601, 0xfb3ef7fe, 0xf7fe20ff, 0x20fffb0b, 0xfaf0f7fe, 0xf7fe2000, 0x2000fad5, 
+    0xfabaf7fe, 0x11f4f240, 0x4620070c, 0xf843f7e8, 0x71a8f241, 0xf7e84620, 0x49d6f82d, 0xf7e84620, 
+    0x2600f829, 0x0998f10d, 0x1123f240, 0x464a2000, 0x0340eb00, 0xeb021c40, 0xb2400343, 0xf8232804, 
+    0xdbf51016, 0x4630a926, 0xfbf5f7fe, 0xf7fe20ff, 0x20fffadb, 0xfac0f7fe, 0x0080f244, 0xfaa4f7fe, 
+    0x7000f640, 0xfa88f7fe, 0x24002105, 0xe9cdb2f0, 0xe9cd4102, 0x23020400, 0x22064621, 0xf7fe4620, 
+    0x4bbdfaf3, 0x20002100, 0x02c1eb01, 0x0282eb03, 0x4020f842, 0xb2401c40, 0xdbf92803, 0xb2491c49, 
+    0xdbf02904, 0x46982400, 0xb124e005, 0xd0052c01, 0xd10f2c02, 0xf240e007, 0xe00010ff, 0xf7fe20ff, 
+    0x20fffaa3, 0x20ffe004, 0xfa9ef7fe, 0x10fef240, 0xfa82f7fe, 0x20402100, 0xf83ef7ef, 0xeb082700, 
+    0x20010584, 0xfc2df7fe, 0x20402100, 0xf834f7ef, 0xfc47f7fe, 0x20402100, 0xf82ef7ef, 0xf011489f, 
+    0xf858fb8b, 0xfa022024, 0x4897f180, 0x1024f848, 0xfb82f011, 0xfa016a69, 0x6268f080, 0xf0114893, 
+    0x6ca9fb7b, 0xf080fa01, 0x489164a8, 0xfb74f011, 0xfa016ee9, 0x66e8f080, 0xf7fe2000, 0x1c7ffc02, 
+    0x2f10b23f, 0x1c64dbcd, 0x2c03b264, 0x2100dbad, 0x20004645, 0x02c1eb01, 0x0282eb05, 0x3020f852, 
+    0x111b3308, 0x3020f842, 0xb2401c40, 0xdbf52803, 0xb2491c49, 0xdbec2904, 0x4630a922, 0xfb83f7fe, 
+    0x46a82400, 0x465daf2c, 0x00c4eb04, 0x2020f858, 0x0080eb08, 0x68806841, 0x0141eba2, 0xf8471809, 
+    0xd5001024, 0xa8224249, 0x1024f847, 0x2024f930, 0x0084eb00, 0x0002f9b0, 0x01c04410, 0x3000f510, 
+    0x4240d500, 0xf0120100, 0xeb04fadb, 0xb2000244, 0x0142eb09, 0xf82142a8, 0xdb000016, 0x1c644650, 
+    0x2c04b264, 0x0016f821, 0xa926dbce, 0xf7fe4630, 0x1c76fb22, 0x2e03b276, 0xaf16f6ff, 0x20002104, 
+    0x23029000, 0xe9cd4602, 0x46010102, 0xf7fe9001, 0xf240fa2b, 0xf7fe1000, 0x2000fa0f, 0xf9f4f7fe, 
+    0xf7fe2000, 0x2000f9d9, 0xf9bef7fe, 0xf7fe2000, 0x2000f9a3, 0xf97ef7fe, 0xf7fe2000, 0xf240f95f, 
+    0x070c11f4, 0xf7e74620, 0x494dff26, 0xf7e74620, 0x4948ff11, 0xf7e74620, 0x484aff0d, 0x22012300, 
+    0xf011211e, 0xb03bfaf6, 0x8ff0e8bd, 0x23002201, 0x46104611, 0xf7feb510, 0x2001f89b, 0xf876f7ff, 
+    0xf7ff2000, 0x2001f873, 0xf870f7ff, 0xf7ff2000, 0xf240f84d, 0x46201400, 0xf9cef7fe, 0xf7fe2000, 
+    0x2000f949, 0xf92af7fe, 0xf7fe2000, 0x4836ff1b, 0x22082300, 0xf0114621, 0x4834facc, 0x22082300, 
+    0xf0114621, 0x4832fac6, 0x22082300, 0xf0114621, 0x2300fac0, 0xe8bd4621, 0x482e4010, 0xf0112208, 
+    0x492dbab8, 0x47707008, 0x5fffe92d, 0xf2484d23, 0x46920400, 0x3d0a468b, 0x220f4681, 0x46214603, 
+    0xf0114628, 0xf247faa6, 0x465b0600, 0x4631220c, 0xf0114628, 0x10f7fa9e, 0x22094653, 0x46284639, 
+    0xfa97f011, 0x1880f240, 0x22079b03, 0x46284641, 0xfa8ff011, 0x22059b0e, 0x46282160, 0xfa89f011, 
+    0x22049b0f, 0x46282110, 0xfa83f011, 0x22039b10, 0x46282108, 0xfa7df011, 0x22009b11, 0x46282107, 
+    0xfa77f011, 0xe019464b, 0xf203cca0, 0xf203d4a0, 0xf203dca0, 0xdcba01f5, 0x0004e288, 0xf203c4a0, 
+    0x0017adce, 0xf203e80c, 0xf203c670, 0xf203ce70, 0xf203d670, 0xf203de70, 0x0004033e, 0x220f4dff, 
+    0x46284621, 0xfa55f011, 0x465b220c, 0x46284631, 0xfa4ff011, 0x46532209, 0x46284639, 0xfa49f011, 
+    0x22079b03, 0x46284641, 0xfa43f011, 0x22059b0e, 0x46282160, 0xfa3df011, 0x22049b0f, 0x46282110, 
+    0xfa37f011, 0x22039b10, 0x46282108, 0xfa31f011, 0x22009b11, 0x46282107, 0xfa2bf011, 0x220f4de8, 
+    0x4621464b, 0xf0114628, 0x220cfa24, 0x4631465b, 0xf0114628, 0x2209fa1e, 0x46394653, 0xf0114628, 
+    0x9b03fa18, 0x46412207, 0xf0114628, 0x9b0efa12, 0x21602205, 0xf0114628, 0x9b0ffa0c, 0x21102204, 
+    0xf0114628, 0x9b10fa06, 0x21082203, 0xf0114628, 0x9b11fa00, 0x21072200, 0xf0114628, 0x4621f9fa, 
+    0x220f4cd0, 0x4620464b, 0xf9f3f011, 0x465b220c, 0x46204631, 0xf9edf011, 0x46532209, 0x46204639, 
+    0xf9e7f011, 0x22079b03, 0x46204641, 0xf9e1f011, 0x22059b0e, 0x46202160, 0xf9dbf011, 0x22049b0f, 
+    0x46202110, 0xf9d5f011, 0x22039b10, 0x46202108, 0xf9cff011, 0xb0049b11, 0x22004620, 0x5ff0e8bd, 
+    0xf0112107, 0xe92db9c6, 0x4db75fff, 0x0400f248, 0x468b4692, 0x4681220f, 0x46214603, 0xf0114628, 
+    0xf247f9b8, 0x465b0600, 0x4631220c, 0xf0114628, 0x10f7f9b0, 0x22094653, 0x46284639, 0xf9a9f011, 
+    0x1880f240, 0x22079b03, 0x46284641, 0xf9a1f011, 0x22059b0e, 0x46282160, 0xf99bf011, 0x22049b0f, 
+    0x46282110, 0xf995f011, 0x22039b10, 0x46282108, 0xf98ff011, 0x22009b11, 0x46282107, 0xf989f011, 
+    0x220f4d96, 0x4621464b, 0x46281ead, 0xf981f011, 0x465b220c, 0x46284631, 0xf97bf011, 0x46532209, 
+    0x46284639, 0xf975f011, 0x22079b03, 0x46284641, 0xf96ff011, 0x22059b0e, 0x46282160, 0xf969f011, 
+    0x22049b0f, 0x46282110, 0xf963f011, 0x22039b10, 0x46282108, 0xf95df011, 0x22009b11, 0x46282107, 
+    0xf957f011, 0x220f4d7e, 0x4621464b, 0x46281ead, 0xf94ff011, 0x465b220c, 0x46284631, 0xf949f011, 
+    0x46532209, 0x46284639, 0xf943f011, 0x22079b03, 0x46284641, 0xf93df011, 0x22059b0e, 0x46282160, 
+    0xf937f011, 0x22049b0f, 0x46282110, 0xf931f011, 0x22039b10, 0x46282108, 0xf92bf011, 0x22009b11, 
+    0x46282107, 0xf925f011, 0x4c664621, 0x464b220f, 0x46201ea4, 0xf91df011, 0x465b220c, 0x46204631, 
+    0xf917f011, 0x46532209, 0x46204639, 0xf911f011, 0x22079b03, 0x46204641, 0xf90bf011, 0x22059b0e, 
+    0x46202160, 0xf905f011, 0x22049b0f, 0x46202110, 0xf8fff011, 0x22039b10, 0x46202108, 0xf8f9f011, 
+    0xb0049b11, 0x22004620, 0x5ff0e8bd, 0xf0112107, 0xe92db8f0, 0x4d4c5fff, 0x0400f248, 0x468b4692, 
+    0x46811ead, 0x4603220f, 0x46284621, 0xf8e1f011, 0x0600f247, 0x220c465b, 0x46284631, 0xf8d9f011, 
+    0x465310f7, 0x46392209, 0xf0114628, 0xf240f8d2, 0x9b031880, 0x46412207, 0xf0114628, 0x9b0ef8ca, 
+    0x21602205, 0xf0114628, 0x9b0ff8c4, 0x21102204, 0xf0114628, 0x9b10f8be, 0x21082203, 0xf0114628, 
+    0x9b11f8b8, 0x21072200, 0xf0114628, 0x4d2bf8b2, 0x464b220f, 0x1f2d4621, 0xf0114628, 0x220cf8aa, 
+    0x4631465b, 0xf0114628, 0x2209f8a4, 0x46394653, 0xf0114628, 0x9b03f89e, 0x46412207, 0xf0114628, 
+    0x9b0ef898, 0x21602205, 0xf0114628, 0x9b0ff892, 0x21102204, 0xf0114628, 0x9b10f88c, 0x21082203, 
+    0xf0114628, 0x9b11f886, 0x21072200, 0xf0114628, 0x4d13f880, 0x464b220f, 0x1f2d4621, 0xf0114628, 
+    0x220cf878, 0x4631465b, 0xf0114628, 0x2209f872, 0x46394653, 0xf0114628, 0x9b03f86c, 0x46412207, 
+    0xf0114628, 0x9b0ef866, 0x21602205, 0xf0114628, 0x2204f860, 0x21109b0f, 0xe0074628, 0xf203cc96, 
+    0xf203d496, 0xf203dc96, 0xf203c494, 0xf851f011, 0x22039b10, 0x46282108, 0xf84bf011, 0x22009b11, 
+    0x46282107, 0xf845f011, 0x4cff4621, 0x464b220f, 0xf0114620, 0x220cf83e, 0x4631465b, 0xf0114620, 
+    0x2209f838, 0x46394653, 0xf0114620, 0x9b03f832, 0x46412207, 0xf0114620, 0x9b0ef82c, 0x21602205, 
+    0xf0114620, 0x9b0ff826, 0x21102204, 0xf0114620, 0x9b10f820, 0x21082203, 0xf0114620, 0x9b11f81a, 
+    0x4620b004, 0xe8bd2200, 0x21075ff0, 0xb811f011, 0x5fffe92d, 0xf2484de5, 0x46920400, 0x220f468b, 
+    0x46034681, 0x46284621, 0xf803f011, 0x0600f247, 0x220c465b, 0x46284631, 0xfffbf010, 0x465310f7, 
+    0x46392209, 0xf0104628, 0xf240fff4, 0x9b031800, 0x46412208, 0xf0104628, 0x9b0effec, 0x21802207, 
+    0xf0104628, 0x9b03ffe6, 0x21402206, 0xf0104628, 0x9b0effe0, 0x21202205, 0xf0104628, 0x9b03ffda, 
+    0x21102204, 0xf0104628, 0x9b0effd4, 0x21082203, 0xf0104628, 0x9b0fffce, 0x21042202, 0xf0104628, 
+    0x9b0fffc8, 0x21022201, 0xf0104628, 0x9b0fffc2, 0x21012200, 0xf0104628, 0x4dbdffbc, 0x464b220f, 
+    0x46284621, 0xffb5f010, 0x465b220c, 0x46284631, 0xffaff010, 0x46532209, 0x46284639, 0xffa9f010, 
+    0x22089b03, 0x46284641, 0xffa3f010, 0x22079b0e, 0x46282180, 0xff9df010, 0x22069b03, 0x46282140, 
+    0xff97f010, 0x22059b0e, 0x46282120, 0xff91f010, 0x22049b03, 0x46282110, 0xff8bf010, 0x22039b0e, 
+    0x46282108, 0xff85f010, 0x22029b0f, 0x46282104, 0xff7ff010, 0x22019b0f, 0x46282102, 0xff79f010, 
+    0x22009b0f, 0x46282101, 0xff73f010, 0x220f4d99, 0x4621464b, 0xf0104628, 0x220cff6c, 0x4631465b, 
+    0xf0104628, 0x2209ff66, 0x46394653, 0xf0104628, 0x9b03ff60, 0x46412208, 0xf0104628, 0x9b0eff5a, 
+    0x21802207, 0xf0104628, 0x9b03ff54, 0x21402206, 0xf0104628, 0x9b0eff4e, 0x21202205, 0xf0104628, 
+    0x9b03ff48, 0x21102204, 0xf0104628, 0x9b0eff42, 0x21082203, 0xf0104628, 0x9b0fff3c, 0x21042202, 
+    0xf0104628, 0x9b0fff36, 0x21022201, 0xf0104628, 0x9b0fff30, 0x21012200, 0xf0104628, 0x4621ff2a, 
+    0x220f4c71, 0x1ea4464b, 0xf0104620, 0x220cff22, 0x4631465b, 0xf0104620, 0x2209ff1c, 0x46394653, 
+    0xf0104620, 0x9b03ff16, 0x46412208, 0xf0104620, 0x9b0eff10, 0x21802207, 0xf0104620, 0x9b03ff0a, 
+    0x21402206, 0xf0104620, 0x9b0eff04, 0x21202205, 0xf0104620, 0x9b03fefe, 0x21102204, 0xf0104620, 
+    0x9b0efef8, 0x21082203, 0xf0104620, 0x9b0ffef2, 0x21042202, 0xf0104620, 0x9b0ffeec, 0x21022201, 
+    0xf0104620, 0x9b0ffee6, 0x4620b004, 0xe8bd2200, 0x21015ff0, 0xbeddf010, 0x4604b510, 0x484e4601, 
+    0xfebdf010, 0x4621484d, 0xfeb9f010, 0x4621484c, 0xfeb5f010, 0x484b4621, 0x4010e8bd, 0xbeaff010, 
+    0xf240b57f, 0x460611f4, 0x4620070c, 0xfae3f7e7, 0x71abf241, 0xf7e74620, 0x4943facd, 0xf7e74620, 
+    0x2001fac9, 0xfc22f7fe, 0xf7fe200a, 0xf640fa15, 0xf7ff0008, 0x2001ffd1, 0x46032400, 0xe9cd2202, 
+    0x46114000, 0xf7ff4620, 0x2506fe93, 0x21009400, 0x23029401, 0x22044608, 0x4502e9cd, 0xfda9f7ff, 
+    0x94002100, 0x46082302, 0x94012204, 0x4502e9cd, 0xfcc9f7ff, 0x94002100, 0x46082302, 0x94012204, 
+    0x4502e9cd, 0xfbd0f7ff, 0xf7fd4630, 0xb004fefa, 0xe8bd200b, 0xf7fe4070, 0xb510b9df, 0x46042200, 
+    0x46032101, 0xf0104821, 0x4820fe5d, 0x21012200, 0x1d004623, 0xfe56f010, 0x2200481c, 0x46232101, 
+    0xf0103008, 0x4819fe4f, 0x21012200, 0xe8bd4623, 0x300c4010, 0xbe46f010, 0x2201b510, 0x21024604, 
+    0x48124603, 0xfe3ef010, 0x22014810, 0x46232102, 0xf0101d00, 0x480dfe37, 0x21022201, 0x30084623, 
+    0xfe30f010, 0xe0134623, 0xf203dc92, 0xf203c490, 0xf203cc90, 0xf203d490, 0xf203c660, 0xf203ce60, 
+    0xf203d660, 0xf203de60, 0xdcba01f5, 0xf1000854, 0x48fd2201, 0x4010e8bd, 0xf0102102, 0xb510be13, 
+    0x46034604, 0x220448f8, 0x380c2130, 0xfe0af010, 0x220448f5, 0x46232130, 0xf0103808, 0x48f2fe03, 
+    0x21302204, 0x1f004623, 0xfdfcf010, 0x46232204, 0x4010e8bd, 0x213048ec, 0xbdf4f010, 0x2208b570, 
+    0x46034605, 0x015448e8, 0x4621380c, 0xfdeaf010, 0x220848e5, 0x4621462b, 0xf0103808, 0x48e2fde3, 
+    0x462b2208, 0x1f004621, 0xfddcf010, 0x4621462b, 0x4070e8bd, 0x220848dc, 0xbdd4f010, 0x4605b570, 
+    0x48d94603, 0x1470f44f, 0x46212212, 0xf010380c, 0x48d5fdc9, 0x462b2212, 0x38084621, 0xfdc2f010, 
+    0x221248d1, 0x4621462b, 0xf0101f00, 0x462bfdbb, 0xe8bd4621, 0x48cc4070, 0xf0102212, 0xb570bdb3, 
+    0x46034605, 0xf04f48c8, 0x221864e0, 0x380c4621, 0xfda8f010, 0x221848c4, 0x4621462b, 0xf0103808, 
+    0x48c1fda1, 0x462b2218, 0x1f004621, 0xfd9af010, 0x4621462b, 0x4070e8bd, 0x221848bb, 0xbd92f010, 
+    0x4604b510, 0x48b84603, 0x21012200, 0xf0103858, 0x48b5fd89, 0x21012200, 0x38544623, 0xfd82f010, 
+    0x220048b1, 0x46232101, 0xf0103850, 0x48aefd7b, 0x21012200, 0x38484623, 0xfd74f010, 0x220048aa, 
+    0x46232101, 0xf0103844, 0x48a7fd6d, 0x21012200, 0x38404623, 0xfd66f010, 0x220048a3, 0x46232101, 
+    0xf0103838, 0x48a0fd5f, 0x21012200, 0x38344623, 0xfd58f010, 0x2200489c, 0x46232101, 0xf0103830, 
+    0x4899fd51, 0x21012200, 0x38284623, 0xfd4af010, 0x22004895, 0x46232101, 0xf0103824, 0x4892fd43, 
+    0x21012200, 0xe8bd4623, 0x38204010, 0xbd3af010, 0x4604b510, 0x488c4603, 0x21102204, 0xf0103858, 
+    0x4889fd31, 0x21102204, 0x38544623, 0xfd2af010, 0x22044885, 0x46232110, 0xf0103850, 0x4882fd23, 
+    0x21102204, 0x38484623, 0xfd1cf010, 0x2204487e, 0x46232110, 0xf0103844, 0x487bfd15, 0x21102204, 
+    0x38404623, 0xfd0ef010, 0x22044877, 0x46232110, 0xf0103838, 0x4874fd07, 0x21102204, 0x38344623, 
+    0xfd00f010, 0x22044870, 0x46232110, 0xf0103830, 0x486dfcf9, 0x21102204, 0x38284623, 0xfcf2f010, 
+    0x22044869, 0x46232110, 0xf0103824, 0x4866fceb, 0x21102204, 0xe8bd4623, 0x38204010, 0xbce2f010, 
+    0x4605b570, 0x48604603, 0x7400f240, 0x46212208, 0xf0103858, 0x485cfcd7, 0x462b2208, 0x38544621, 
+    0xfcd0f010, 0x22084858, 0x4621462b, 0xf0103850, 0x4855fcc9, 0x462b2208, 0x38484621, 0xfcc2f010, 
+    0x22084851, 0x4621462b, 0xf0103844, 0x484efcbb, 0x462b2208, 0x38404621, 0xfcb4f010, 0x2208484a, 
+    0x4621462b, 0xf0103838, 0x4847fcad, 0x462b2208, 0x38344621, 0xfca6f010, 0x22084843, 0x4621462b, 
+    0xf0103830, 0x4840fc9f, 0x462b2208, 0x38284621, 0xfc98f010, 0x2208483c, 0x4621462b, 0xf0103824, 
+    0x4839fc91, 0x4621462b, 0x4070e8bd, 0x38202208, 0xbc88f010, 0x460eb570, 0x48344604, 0x2c012101, 
+    0x7001d100, 0x4d322e01, 0x7029d100, 0x78007829, 0x2101b24b, 0x4608b242, 0xfa3af7fd, 0x20042100, 
+    0xf90af7ee, 0x7800482b, 0xf7ffb240, 0x2001ff89, 0xff2ef7ff, 0xf7ffb2e0, 0x2003fed3, 0xfeaff7ff, 
+    0xf7ff200b, 0x2000fe8b, 0xfe68f7ff, 0xf7ff2001, 0x4630fe46, 0xfe10f7ff, 0xe8bd7828, 0xb2404070, 
+    0xb570e5eb, 0x0400f647, 0x220b4605, 0x481a4603, 0xf0104621, 0x4819fc5e, 0x462b220b, 0xf0104621, 
+    0x4817fc58, 0x462b220b, 0xf0104621, 0x462bfc52, 0xe8bd4621, 0x48134070, 0xf010220b, 0xe92dbc4a, 
+    0x4f0d41f0, 0x4e102400, 0x3f3cb2c5, 0xeb0642a5, 0xd11b20c4, 0x22042301, 0xf0102110, 0x2301fc3a, 
+    0x20c4eb07, 0x0000e01a, 0xf1000860, 0x0004028c, 0x0004028d, 0x0004033e, 0xf203c64c, 0xf203ce4c, 
+    0xf203d64c, 0xf203de4c, 0xf203c482, 0x22042300, 0xf0102110, 0x2300fc1e, 0x20c4eb07, 0x21022201, 
+    0xfc17f010, 0xb2e41c64, 0xd3cf2c04, 0x81f0e8bd, 0x46032208, 0x0154b570, 0x48ff4605, 0xf0104621, 
+    0x48fefc08, 0x462b2208, 0xf0104621, 0x48fcfc02, 0x462b2208, 0xf0104621, 0x462bfbfc, 0xe8bd4621, 
+    0x48f84070, 0xf0102208, 0xb510bbf4, 0x46042207, 0x46032180, 0xf01048f0, 0x48f0fbec, 0x21802207, 
+    0xf0104623, 0x48eefbe6, 0x21802207, 0xf0104623, 0x2207fbe0, 0xe8bd4623, 0x48ea4010, 0xf0102180, 
+    0x220cbbd8, 0xb5704603, 0x46050294, 0x462148e2, 0xfbcff010, 0x220c48e1, 0x4621462b, 0xfbc9f010, 
+    0x220c48df, 0x4621462b, 0xfbc3f010, 0x4621462b, 0x4070e8bd, 0x220c48db, 0xbbbbf010, 0x4605b570, 
+    0x48d54603, 0x2400f240, 0x46212209, 0xf0101c80, 0x48d2fbb0, 0x462b2209, 0x1c804621, 0xfba9f010, 
+    0x220948cf, 0x4621462b, 0xf0101c80, 0x48cdfba2, 0x4621462b, 0x4070e8bd, 0x1c802209, 0xbb99f010, 
+    0x4604b510, 0x48c44603, 0x21072200, 0xf0103008, 0x48c2fb90, 0x21072200, 0x30084623, 0xfb89f010, 
+    0x220048bf, 0x46232107, 0xf0103008, 0x48bdfb82, 0x21072200, 0xe8bd4623, 0x30084010, 0xbb79f010, 
+    0x4605b570, 0x48b44603, 0x0400f246, 0x4621220d, 0xf010387a, 0x48b1fb6e, 0x462b220d, 0x387a4621, 
+    0xfb67f010, 0x220d48ae, 0x4621462b, 0xf010387a, 0x48acfb60, 0x4621462b, 0x4070e8bd, 0x387a220d, 
+    0xbb57f010, 0x4604b510, 0x48a34603, 0x21012200, 0xf010387c, 0x48a1fb4e, 0x21012200, 0x387c4623, 
+    0xfb47f010, 0x2200489e, 0x46232101, 0xf010387c, 0x489cfb40, 0x21012200, 0xe8bd4623, 0x387c4010, 
+    0xbb37f010, 0x4605b570, 0x48934603, 0x0400f241, 0x4621220c, 0xf010387a, 0x4890fb2c, 0x462b220c, 
+    0x387a4621, 0xfb25f010, 0x220c488d, 0x4621462b, 0xf010387a, 0x488bfb1e, 0x4621462b, 0x4070e8bd, 
+    0x387a220c, 0xbb15f010, 0x4604b510, 0x48824603, 0x21022201, 0xf0103876, 0x4880fb0c, 0x21022201, 
+    0x38764623, 0xfb05f010, 0x2201487d, 0x46232102, 0xf0103876, 0x487bfafe, 0x21022201, 0xe8bd4623, 
+    0x38764010, 0xbaf5f010, 0x4605b570, 0x48724603, 0x0400f248, 0x4621220f, 0xf010387a, 0x486ffaea, 
+    0x462b220f, 0x387a4621, 0xfae3f010, 0x220f486c, 0x4621462b, 0xf010387a, 0x486afadc, 0x4621462b, 
+    0x4070e8bd, 0x387a220f, 0xbad3f010, 0x4604b510, 0x48614603, 0x21012200, 0xf0103876, 0x485ffaca, 
+    0x21012200, 0x38764623, 0xfac3f010, 0x2200485c, 0x46232101, 0xf0103876, 0x485afabc, 0x21012200, 
+    0xe8bd4623, 0x38764010, 0xbab3f010, 0x4ff7e92d, 0xf7ff2000, 0x2001ffdb, 0xffb6f7ff, 0x78204c52, 
+    0x2001b948, 0xff90f7ff, 0x20402100, 0xff24f7ed, 0xf7ff2000, 0x2001ff89, 0xff64f7ff, 0x20402100, 
+    0xff1af7ed, 0xf7ff2000, 0x2001ff5d, 0xff3af7ff, 0xf7ff2003, 0x7820ff15, 0x3900f44f, 0xd1792800, 
+    0x70202001, 0xfecaf7ff, 0xf7ff2007, 0xf8dffee9, 0xf241a0e8, 0xf8df0600, 0x2400b0e0, 0x0a76f1aa, 
+    0xf1aa1077, 0xf10b0804, 0x46550b84, 0x46502301, 0x21042202, 0xfa6df010, 0x46482100, 0xfeecf7ed, 
+    0x46282300, 0x21042202, 0xfa63f010, 0x46312301, 0x4640220c, 0xfa5df010, 0x46392301, 0x4640220b, 
+    0xfa57f010, 0x46582200, 0xf010217f, 0xb245fa60, 0x23004639, 0x220b4640, 0xfa4bf010, 0x46312300, 
+    0x4640220c, 0xfa45f010, 0x2d7e1e6d, 0x1c64d303, 0x2c0ab264, 0xf8dfdbc9, 0x2400a064, 0xb05cf8df, 
+    0x0a76f1aa, 0x0804f1aa, 0x0b84f10b, 0x23014655, 0x22024650, 0xf0102104, 0x2100fa2c, 0xf7ed4648, 
+    0x2300feab, 0x22024628, 0xf0102104, 0x2301fa22, 0x220c4631, 0xf0104640, 0x2301fa1c, 0x220b4639, 
+    0xf0104640, 0x2200fa16, 0x217f4658, 0xfa1ff010, 0xe00bb245, 0x0000e09e, 0xf203c280, 0xf203ca80, 
+    0xf203d280, 0xf203da80, 0x00040940, 0x46392300, 0x4640220b, 0xf9fdf010, 0x46312300, 0x4640220c, 
+    0xf9f7f010, 0x2d7e1e6d, 0x1c64d303, 0x2c0ab264, 0xf8dfdbbc, 0x2400a514, 0xb50cf8df, 0x0804f1aa, 
+    0x0bfaf10b, 0x23014655, 0x22024650, 0xf0102104, 0x2100f9e0, 0xf7ed4648, 0x2300fe5f, 0x22024628, 
+    0xf0102104, 0x2301f9d6, 0x220c4631, 0xf0104640, 0x2301f9d0, 0x220b4639, 0xf0104640, 0x2200f9ca, 
+    0x217f4658, 0xf9d3f010, 0x4639b245, 0x46402300, 0xf010220b, 0x2300f9be, 0x220c4631, 0xf0104640, 
+    0x1e6df9b8, 0xd3032d7e, 0xb2641c64, 0xdbc92c0a, 0xa498f8df, 0xf8df2400, 0xf1aab494, 0xf10b0804, 
+    0x46550bfa, 0x46502301, 0x21042202, 0xf9a1f010, 0x46482100, 0xfe20f7ed, 0x46282300, 0x21042202, 
+    0xf997f010, 0x46312301, 0x4640220c, 0xf991f010, 0x46392301, 0x4640220b, 0xf98bf010, 0x46582200, 
+    0xf010217f, 0xb245f994, 0x23004639, 0x220b4640, 0xf97ff010, 0x46312300, 0x4640220c, 0xf979f010, 
+    0x2d7e1e6d, 0x1c64d303, 0x2c0ab264, 0x2000dbc9, 0xfdb4f7ff, 0xf7ff9802, 0x9800fd94, 0xfd75f7ff, 
+    0xf7ff9801, 0x2100fd55, 0x4648464c, 0xfde4f7ed, 0x23014dff, 0x461a2102, 0xf0104628, 0x2100f95a, 
+    0xf7ed2040, 0x4efafdd9, 0x22063676, 0x21404630, 0xf95df010, 0x2900b241, 0x2300d1f7, 0x22014628, 
+    0xf0102102, 0x2100f946, 0xf7ed4620, 0x4df1fdc5, 0x21022301, 0x4628461a, 0xf93bf010, 0x20402100, 
+    0xfdbaf7ed, 0x36764eeb, 0x46302206, 0xf0102140, 0xb241f93e, 0xd1f72900, 0x46282300, 0x21022201, 
+    0xf927f010, 0x46202100, 0xfda6f7ed, 0x23014dde, 0x461a2102, 0x46283580, 0xf91bf010, 0x20402100, 
+    0xfd9af7ed, 0x36f64ed8, 0x46302206, 0xf0102140, 0xb241f91e, 0xd1f72900, 0x46282300, 0x21022201, 
+    0xf907f010, 0x46202100, 0xfd86f7ed, 0x23014ccf, 0x461a2102, 0x46203480, 0xf8fbf010, 0x20402100, 
+    0xfd7af7ed, 0x35f64dc9, 0x46282206, 0xf0102140, 0xb241f8fe, 0xd1f72900, 0x46202300, 0x21022201, 
+    0xf8e7f010, 0xf7ff2000, 0xe8bdfcf0, 0x20004ffe, 0xe92de4ce, 0x46804ff0, 0x460f48bf, 0xa2fcf8df, 
+    0xad10b099, 0xe885c81e, 0xc81e001e, 0xe88dad04, 0xc81e001e, 0x001ee885, 0xad14c81e, 0x001ee885, 
+    0xad0cc81e, 0x001ee885, 0xac08c80f, 0xe8842500, 0x2400000f, 0x29c5ea4f, 0x0144eb09, 0x060aeb01, 
+    0xf0104630, 0x0b03f899, 0x021ff000, 0x1145f3c0, 0xf1b84618, 0xd10d0f01, 0xc040f9bd, 0xdd02458c, 
+    0xb2801f18, 0xf9bde004, 0x458cc000, 0x1d18da02, 0x1010f8bd, 0xd10d2f01, 0xc050f9bd, 0xdd014594, 
+    0xe0041e40, 0xc030f9bd, 0xda034594, 0xf8bd1c40, 0xb2802020, 0xd0074298, 0xeb000300, 0x44101041, 
+    0x4630b281, 0xf86bf010, 0x2c421c64, 0x1c6ddbc4, 0x2d04b26d, 0x2500dbbd, 0x0a10f10d, 0x0b20f10d, 
+    0xea4f2402, 0x488d29c5, 0x0144eb09, 0x180e30a0, 0xf0104630, 0x0b03f851, 0x021ff000, 0x1145f3c0, 
+    0xf1b84618, 0xd1150f01, 0x0c40f10d, 0x0c44eb0c, 0xc002f9bc, 0xdd02458c, 0xb2801f18, 0x46ece007, 
+    0x0c44eb0c, 0xc002f9bc, 0xda03458c, 0xeb0a1d18, 0x88490144, 0xd1162f01, 0x0c50f10d, 0x0c44eb0c, 
+    0xc002f9bc, 0xdd014594, 0xe0081e40, 0x0c30f10d, 0x0c44eb0c, 0xc002f9bc, 0xda044594, 0xeb0b1c40, 
+    0xb2800244, 0x42988852, 0x0300d007, 0x1041eb00, 0xb2814410, 0xf0104630, 0x1c64f812, 0xdbb22c06, 
+    0xb26d1c6d, 0xdbab2d04, 0xe8bdb019, 0xe92d8ff0, 0x4c5f41f0, 0x22022300, 0x46202104, 0xf819f010, 
+    0x23004d5c, 0x21042202, 0xf0104628, 0x4e56f812, 0x22022300, 0x21043680, 0xf0104630, 0x4f53f80a, 
+    0x22022300, 0x21043780, 0xf0104638, 0x2100f802, 0xf7ed2040, 0x2301fc81, 0x22024620, 0xf00f2104, 
+    0x2301fff8, 0x22024628, 0xf00f2104, 0x2301fff2, 0x22024630, 0xf00f2104, 0x2301ffec, 0x22024638, 
+    0xf00f2104, 0x4845ffe6, 0x4410f24a, 0x30aa4621, 0xffc5f00f, 0x46214842, 0xffc1f00f, 0x46214841, 
+    0xffbdf00f, 0x46214840, 0xffb9f00f, 0xf24a483b, 0x4621240c, 0xf00f30a8, 0x4839ffb2, 0x1e804621, 
+    0xffadf00f, 0x46214837, 0xf00f1e80, 0x4836ffa8, 0x1e804621, 0xffa3f00f, 0x1f244830, 0x30a64621, 
+    0xff9df00f, 0x4621482e, 0xf00f1f00, 0x482dff98, 0x1f004621, 0xff93f00f, 0x4621482b, 0xf00f1f00, 
+    0x4826ff8e, 0x1406f24a, 0x30a44621, 0xff87f00f, 0x46214823, 0xf00f1f80, 0x4822ff82, 0x1f804621, 
+    0xff7df00f, 0x46214820, 0xf00f1f80, 0x481bff78, 0x1404f246, 0x30a24621, 0xff71f00f, 0x46214818, 
+    0xf00f3808, 0x4817ff6c, 0x38084621, 0xff67f00f, 0x46214815, 0xf00f3808, 0x4810ff62, 0x1404f242, 
+    0x30a04621, 0xff5bf00f, 0x4621480d, 0xf00f380a, 0x480cff56, 0x380a4621, 0xff51f00f, 0x4621480a, 
+    0xf00f380a, 0xe011ff4c, 0xf203d20a, 0xf203da0a, 0xf203c28a, 0xf203ca8a, 0x0002cea4, 0xf203c000, 
+    0xf203c8aa, 0xf203d0aa, 0xf203d8aa, 0x3480f240, 0x46214897, 0xff33f00f, 0x46214896, 0xff2ff00f, 
+    0x46214895, 0xff2bf00f, 0x48944621, 0x41f0e8bd, 0xbf25f00f, 0x47f0e92d, 0x4c914691, 0x468a220c, 
+    0x46034607, 0x46200296, 0xf00f4631, 0x4d8dff32, 0x463b220c, 0x46284631, 0xff2bf00f, 0x8228f8df, 
+    0x463b220c, 0x46404631, 0xff23f00f, 0x4e874631, 0x463b220c, 0xf00f4630, 0xf240ff1c, 0x46533700, 
+    0x46392208, 0xf00f4620, 0x2208ff14, 0x46394653, 0xf00f4628, 0x2208ff0e, 0x46394653, 0xf00f4640, 
+    0x2208ff08, 0x46394653, 0xf00f4630, 0x2206ff02, 0x21c0464b, 0xf00f4620, 0x2206fefc, 0x21c0464b, 
+    0xf00f4628, 0x2206fef6, 0x21c0464b, 0xf00f4640, 0x464bfef0, 0xe8bd4630, 0x220647f0, 0xf00f21c0, 
+    0xb51cbee8, 0xf7ff2000, 0x2202fc11, 0x20012103, 0xffa0f7ff, 0xf7f12000, 0x2001fc35, 0xfc32f7f1, 
+    0xf7f12000, 0x2202fc2f, 0x20002101, 0xfc1ef7ff, 0x74e0f240, 0x2205485e, 0xf00f4621, 0xf8adfed8, 
+    0x22050000, 0x4621485b, 0xfed1f00f, 0x0002f8ad, 0x48592205, 0xf00f4621, 0xf8adfeca, 0x22050004, 
+    0x46214856, 0xfec3f00f, 0x0006f8ad, 0x211c2000, 0xf933466b, 0xeba22010, 0x32600282, 0x02a2eb01, 
+    0x2010f823, 0xb2001c40, 0xdbf22804, 0xfe7ff7ff, 0x3000f8bd, 0x483e2205, 0xf00f4621, 0xf8bdfe9a, 
+    0x22053002, 0x4621483b, 0xfe93f00f, 0x3004f8bd, 0x48392205, 0xf00f4621, 0xf8bdfe8c, 0x22053006, 
+    0x46214836, 0xfe85f00f, 0x21012203, 0xf7ff2000, 0x2100fbcd, 0xf7ff2001, 0xf44ffd9c, 0x21003400, 
+    0xf7ed4620, 0x2203faf9, 0x20002101, 0xfbbef7ff, 0x21002203, 0xf7ff2001, 0x2101fbb9, 0xf7ff2000, 
+    0x2100fd88, 0xf7ed4620, 0xb002fae7, 0x21002203, 0x4010e8bd, 0xf7ff2001, 0xb5f8bba9, 0x14f4f240, 
+    0x07254621, 0xf7e64628, 0xf241fa76, 0x462871bb, 0xfa60f7e6, 0x46284e22, 0xf7e64631, 0x2000fa5b, 
+    0xf98df7f1, 0xf7f12030, 0x2001f96c, 0xfb58f7f1, 0x92002200, 0x46132100, 0x46082203, 0xf8f0f002, 
+    0xfe15f7ff, 0xf7ff2003, 0x2000ff4c, 0xfb48f7f1, 0x46284621, 0xfa4ff7e6, 0x71bcf241, 0xf7e64628, 
+    0x4631fa39, 0xe8bd4628, 0xf7e640f8, 0x0000ba33, 0xf203c0fe, 0xf203c8fe, 0xf203d0fe, 0xf203d8fe, 
+    0xf203c200, 0xf203ca00, 0xf203d200, 0xf203da00, 0xf203c302, 0xf203cb02, 0xf203d302, 0xf203db02, 
+    0xdcba01f5, 0x4c3cb570, 0x211f2300, 0x4620461a, 0xfdfff00f, 0xf2404838, 0x220535e0, 0x301a4629, 
+    0xfe05f00f, 0x46032205, 0x46204629, 0xfdf1f00f, 0x46202301, 0x0299220a, 0xfdebf00f, 0x23024c2e, 
+    0xf24f220c, 0x34200100, 0xf00f4620, 0x2304fde2, 0x22004620, 0xf00f210f, 0x2301fddc, 0x210f2200, 
+    0xf00f1f20, 0x2301fdd6, 0x210f2200, 0xe8bd1ea0, 0xf00f4070, 0x4821bdce, 0xf00fb510, 0x4920fdad, 
+    0x80084a20, 0x1140f3c0, 0xf3c07011, 0x4a1e1180, 0x4a1e7011, 0xf3c07011, 0x4a1d11c0, 0x1000f3c0, 
+    0x22087011, 0x7008491b, 0x48140151, 0xf00f1d00, 0x4919fdbe, 0x20007008, 0x70084918, 0x2100bd10, 
+    0x6e084a17, 0xd1014290, 0x66092000, 0x480bb281, 0xbd85f00f, 0xf64b4809, 0xb51031b3, 0xf00f3086, 
+    0xf7fffd7e, 0xf7ffffec, 0x490effc6, 0x70082000, 0x4010e8bd, 0x0000e786, 0xf23c8204, 0xf23c8034, 
+    0x00040584, 0x00040310, 0x000402f5, 0x000402f4, 0x00040581, 0x00040582, 0x00040583, 0x00040368, 
+    0xf1205a2d, 0x000405b4, 0x4db7b570, 0x2200b283, 0x21014604, 0xf00f4628, 0xb2a3fd6c, 0x22014628, 
+    0xf00f2102, 0xb2a3fd66, 0x22024628, 0xf00f2104, 0x2301fd60, 0x22034628, 0xf00f2108, 0xb2a3fd5a, 
+    0xe8bd4628, 0x22044070, 0xf00f2110, 0xe92dbd52, 0x48a641f0, 0xf00f2100, 0x48a4fd32, 0x1c802100, 
+    0xfd2df00f, 0x210048a1, 0xf00f1d00, 0x489ffd28, 0x1d802100, 0xfd23f00f, 0x2100489c, 0xf00f3008, 
+    0x489afd1e, 0x300a2100, 0xfd19f00f, 0x21004897, 0xf00f300c, 0x4895fd14, 0x300e2100, 0xfd0ff00f, 
+    0x21004892, 0xf00f3010, 0x4890fd0a, 0x30122140, 0xfd05f00f, 0x2100488d, 0xf00f3014, 0x488bfd00, 
+    0x30162104, 0xfcfbf00f, 0x21004888, 0xf00f3018, 0x4886fcf6, 0x301a2100, 0xfcf1f00f, 0x21004883, 
+    0xf00f301c, 0x4882fcec, 0xf00f2100, 0x4881fce8, 0x1cad4d7d, 0x487d7801, 0x1c843020, 0x29001e86, 
+    0x0100f04f, 0x4607d019, 0xfcd9f00f, 0x46382301, 0x21202205, 0xfcedf00f, 0x46202100, 0xfccff00f, 
+    0x46282100, 0xfccbf00f, 0x4100f240, 0xf00f4630, 0xe8bdfcc6, 0x200141f0, 0xf00fe766, 0x2100fcc0, 
+    0xf00f4620, 0x2100fcbc, 0xf00f4628, 0xf242fcb8, 0xe7eb4192, 0x460cb510, 0x78094966, 0xd1152900, 
+    0x4862b283, 0x21032200, 0xf00f301e, 0x485ffcc2, 0x2200b2a3, 0x1d00210f, 0xfcbbf00f, 0x485a2301, 
+    0xe8bd2205, 0x21204010, 0xbcb3f00f, 0x4859bd10, 0x28007800, 0x4855d106, 0x21032300, 0x301e461a, 
+    0xbca7f00f, 0xb5104770, 0x4952460c, 0x29007809, 0xb283d115, 0x2203484d, 0x301e2118, 0xfc99f00f, 
+    0xb2a3484a, 0x210f2200, 0xf00f300a, 0x2301fc92, 0x22064845, 0x4010e8bd, 0xf00f2140, 0xbd10bc8a, 
+    0x78004844, 0xd1062800, 0x23004840, 0x21182203, 0xf00f301e, 0x4770bc7e, 0x460cb510, 0x7809493d, 
+    0xd1152900, 0x4839b283, 0x21c02206, 0xf00f301e, 0x4836fc70, 0x2200b2a3, 0x3010210f, 0xfc69f00f, 
+    0x48312301, 0xe8bd2207, 0x21804010, 0xbc61f00f, 0x4830bd10, 0x28007800, 0x482cd106, 0x22062300, 
+    0x301e21c0, 0xbc55f00f, 0x48284770, 0x22062301, 0x30202140, 0xbc4df00f, 0x23004824, 0x21402206, 
+    0xf00f3020, 0xb510bc46, 0x4922460c, 0x29007809, 0xb283d115, 0x220c481d, 0x0291301e, 0xfc39f00f, 
+    0xb2a3481a, 0x210f2200, 0xf00f301c, 0x2301fc32, 0x22094815, 0x4010e8bd, 0xf00f0259, 0xbd10bc2a, 
+    0x78004814, 0xd1062800, 0x4810220c, 0x02912300, 0xf00f301e, 0x4770bc1e, 0xf000b510, 0x2100f81d, 
+    0xf7ff2001, 0x2100ff47, 0xf7ff2001, 0x2100ff6c, 0xf7ff2001, 0x2100ff91, 0xf7ff2001, 0x2100ffb6, 
+    0x4010e8bd, 0xe7be2001, 0xf20351d8, 0xf2035058, 0xf23d0122, 0x00040582, 0xf7ffb510, 0x2301fea8, 
+    0x220048ff, 0xf00f4619, 0x48fefbf4, 0x22042301, 0xf00f2110, 0x4cfafbee, 0x22022301, 0x21041ca4, 
+    0xf00f4620, 0x2301fbe6, 0x22034620, 0xf00f2108, 0x4cf4fbe0, 0x22022301, 0x21041da4, 0xf00f4620, 
+    0x2301fbd8, 0x21024620, 0xf00f461a, 0x2301fbd2, 0x21402206, 0xf00f1da0, 0x48eafbcc, 0x22072301, 
+    0x30122180, 0xfbc5f00f, 0x23014ce5, 0x34082202, 0x46202104, 0xfbbdf00f, 0x46202301, 0x21082203, 
+    0xfbb7f00f, 0x48df2301, 0x03d9220f, 0x4010e8bd, 0xf00f3018, 0x48dabbae, 0x22002301, 0x1f004619, 
+    0xf00fb510, 0x2100fba6, 0x4010e8bd, 0xf7ff2002, 0x48d3bed1, 0x21012300, 0x1f00461a, 0xf00fb510, 
+    0xe8bdfb98, 0xf7ff4010, 0xe92dbee2, 0x4dce5ff0, 0x080ff001, 0x46142300, 0xf04f2202, 0x21040901, 
+    0xf00f4628, 0x2301fb86, 0x22064628, 0xf00f2140, 0x2301fb80, 0x22074628, 0xf00f2180, 0x2300fb7a, 
+    0x22044628, 0xf00f2110, 0x2300fb74, 0x22054628, 0xf00f2120, 0x2300fb6e, 0x22014628, 0xf00f2102, 
+    0x2300fb68, 0x22034628, 0xf00f2108, 0x4fb7fb62, 0x080af1a8, 0xf8df4eb5, 0x3f18b2d4, 0xa2d0f8df, 
+    0xf1b83e08, 0xd2760f05, 0xf008e8df, 0xf6f7f903, 0xf8df00f5, 0x1c6082c0, 0x2300d011, 0x22064628, 
+    0xf00f2140, 0xb3ecfb46, 0x28091e60, 0x48a7d854, 0x0148ea4f, 0xf00f3810, 0x2130fb1c, 0x48a3e056, 
+    0x46414644, 0xf00f3810, 0x4621fb14, 0xf00f4658, 0x2300fb10, 0x22064628, 0xf00f2140, 0x2300fb2a, 
+    0x22074628, 0xf00f2180, 0x2301fb24, 0x21024628, 0xf00f461a, 0x4894fb1e, 0x1c802118, 0xfafff00f, 
+    0x21184891, 0xf00f3008, 0x2300fafa, 0x21022201, 0xf00f4628, 0x2301fb0e, 0x461a2102, 0xf00f4628, 
+    0xe1b0fb08, 0x2301e7ff, 0x21024638, 0xf00f461a, 0x2301fae9, 0x21024630, 0xf00f461a, 0x2300fae3, 
+    0x22014638, 0xf00f2102, 0x2300fadd, 0x22014630, 0xf00f2102, 0xe185fad7, 0x000bf1a4, 0xd80b2859, 
+    0x497d487a, 0xf00f3810, 0x212cfac4, 0x1c804876, 0xfac5f00f, 0xe183e187, 0x0065f1a4, 0x7fc8f5b0, 
+    0x4872d206, 0x38104975, 0xfab3f00f, 0xe7ed2128, 0x10f5f2a4, 0x7ffaf5b0, 0x486cd206, 0x38104970, 
+    0xfaa7f00f, 0xe7e12124, 0x30e9f2a4, 0x6f7af5b0, 0x4866d206, 0x3810496b, 0xfa9bf00f, 0xe7d52120, 
+    0x5098f5a4, 0x3187f241, 0x42883889, 0x485fd806, 0x38104965, 0xfa8df00f, 0xe7c7211c, 0x501cf5a4, 
+    0x413ff649, 0x42883811, 0x4858d806, 0x38104641, 0xfa7ff00f, 0xe7b92118, 0x4043f5a4, 0x314ff24c, 
+    0x42883851, 0x4851d806, 0x38104958, 0xfa71f00f, 0xe7ab2114, 0xf5a44956, 0x38a130c3, 0xd8064288, 
+    0x4954484a, 0xf00f3810, 0x2110fa64, 0x4852e79e, 0x44204952, 0xd8064288, 0x49514844, 0xf00f3810, 
+    0x210cfa58, 0x484fe792, 0x4420494f, 0xd8064288, 0x4651483e, 0xf00f3810, 0x2108fa4c, 0x484be786, 
+    0x4420494b, 0xd8854288, 0x494a4838, 0xf00f3810, 0x2104fa40, 0xe050e77a, 0xe01ee041, 0x4833e7ff, 
+    0x46514654, 0xf00f3810, 0x4621fa34, 0xf00f4658, 0x482dfa30, 0x1c802108, 0xfa31f00f, 0x2108482a, 
+    0xf00f3008, 0x2300fa2c, 0x22064628, 0xf00f2140, 0x2300fa40, 0x21802207, 0x2301e72a, 0x21024638, 
+    0xf00f461a, 0x2301fa1f, 0x21024630, 0xf00f461a, 0x2300fa19, 0x22014638, 0xf00f2102, 0x2300fa13, 
+    0x22014630, 0xf00f2102, 0x2300fa0d, 0x22074628, 0xf00f2180, 0x2301fa1e, 0x21202205, 0x2300e0b5, 
+    0x22074628, 0xf00f2180, 0x4923fa14, 0xf00f4658, 0x480df9f0, 0x30082102, 0x4820e72a, 0x0000f990, 
+    0xd03d2803, 0xd03b2805, 0xd0392804, 0xd0702802, 0xf04f2801, 0xd0780301, 0x21402206, 0x0000e6ee, 
+    0xf20351de, 0xf203505e, 0xf23c80da, 0xf0008178, 0x0501bd00, 0x0f053700, 0x1b898f80, 0x1908b100, 
+    0x1687d280, 0x1406f400, 0x11861580, 0x0c845880, 0x00061a7f, 0x0a037a00, 0xfff85edf, 0x0007a11f, 
+    0x07829b80, 0xfff0bdbf, 0x003d08ff, 0xffb3b4bf, 0x004c4b3f, 0x0280de80, 0x01406f40, 0x00040244, 
+    0x46382301, 0x461a2102, 0xf9acf00f, 0x46302301, 0x461a2102, 0xf9a6f00f, 0x48f949f8, 0xf999f00f, 
+    0x46282300, 0x21402206, 0xf9b3f00f, 0x210548f5, 0xf995f00f, 0x210a48f3, 0xf00f1c80, 0x48f1f990, 
+    0x1d002105, 0xf98bf00f, 0x46282301, 0x21042202, 0xf99ff00f, 0x46382300, 0x21022201, 0xf982f00f, 
+    0x46302300, 0x21022201, 0xf97cf00f, 0xe000e03b, 0x49e2e00b, 0xf00f48e2, 0x2300f96c, 0x22064628, 
+    0xf00f2140, 0x2105f986, 0x2201e6a0, 0x21024638, 0xf968f00f, 0x46302301, 0x461a2102, 0xf962f00f, 
+    0x46382300, 0x21022201, 0xf95cf00f, 0x46302300, 0x21022201, 0xf956f00f, 0x46282300, 0x21402206, 
+    0xf967f00f, 0x22042301, 0x46282110, 0xf961f00f, 0xe8bd4628, 0x23015ff0, 0x21082203, 0xb959f00f, 
+    0x0f00f1b9, 0x2300d00d, 0x22034630, 0xf00f2108, 0x4630f939, 0x5ff0e8bd, 0x22032301, 0xf00f2108, 
+    0xe8bdb931, 0xb5109ff0, 0x78204cbf, 0xd0052801, 0x230148be, 0x21102204, 0xf93bf00f, 0x20012100, 
+    0xfc91f7ff, 0x28027820, 0x48b6d10d, 0xf00f380a, 0x280ef913, 0x48b6d107, 0x210e2200, 0x0000f990, 
+    0x4010e8bd, 0xbd10e591, 0x4db2b570, 0x4caf2803, 0x2805d004, 0x2804d017, 0xe030d017, 0x46282300, 
+    0x210c2202, 0xf915f00f, 0x46202301, 0x21802207, 0xf90ff00f, 0x46202300, 0x21102204, 0xf909f00f, 
+    0xfc7ef7ff, 0x2302e017, 0x2301e000, 0x22024628, 0xf00f210c, 0x2300f8fe, 0x22074620, 0xf00f2180, 
+    0x2300f8f8, 0x22044620, 0xf00f2110, 0x2100f8f2, 0xf7ff2002, 0x2100fc48, 0xf7ff2002, 0x2100fca4, 
+    0xf7ff2002, 0x4890fc92, 0x28027800, 0x488dd10b, 0xf00f380a, 0xb241f8c1, 0x2200488d, 0x0000f990, 
+    0x4070e8bd, 0xbd70e541, 0xf7ffb510, 0xf7fffc20, 0xf7fffc47, 0xf7fffc6e, 0xf7fffc7f, 0x4c85fca1, 
+    0x21012300, 0x4620461a, 0xf8c3f00f, 0x46202300, 0x210c2202, 0xf8bdf00f, 0x23004c7c, 0x21802207, 
+    0xf00f4620, 0x2300f8b6, 0x22044620, 0xf00f2110, 0x4875f8b0, 0x28027800, 0x4c72d10f, 0x22062301, 
+    0x21401ea4, 0xf00f4620, 0x2301f8a4, 0x22074620, 0x4010e8bd, 0xf00f2180, 0xbd10b89c, 0xb510496a, 
+    0x1000f991, 0x2901b189, 0x2902d014, 0x4865d143, 0xf00f380a, 0x280ef871, 0x4865d13d, 0x210e2200, 
+    0x0000f990, 0x4010e8bd, 0xe8bde4ef, 0x20004010, 0xbb0af7ff, 0xb3004c5d, 0xd0202801, 0xd12a2802, 
+    0x46202301, 0x21102204, 0xf873f00f, 0x46202301, 0x21082203, 0xf86df00f, 0x220e4857, 0x0100f244, 
+    0xf875f00f, 0x28014c53, 0x2300d013, 0x21012200, 0xe8bd4620, 0xf00f4010, 0x2300b85c, 0x2301e000, 
+    0x22044620, 0xf00f2110, 0x2300f854, 0x21082203, 0x2301e7ee, 0xbd10e7ea, 0x4c43b570, 0x0000f994, 
+    0x2801b110, 0xe010d004, 0xf7ff2001, 0xe00cfacd, 0x23004d3e, 0x21102204, 0xf00f4628, 0x2300f83a, 
+    0x22034628, 0xf00f2108, 0xf7fff834, 0x2300fbe5, 0x21014838, 0xf00f461a, 0x7820f82c, 0xd10f2802, 
+    0x23014c30, 0x1ea42206, 0x46202140, 0xf821f00f, 0xe8bd4620, 0x23014070, 0x21802207, 0xb819f00f, 
+    0x2100bd70, 0xb5102002, 0xfbbff7ff, 0x78004826, 0xd10b2802, 0x380a4823, 0xffeef00e, 0x4824b241, 
+    0xf9902200, 0xe8bd0000, 0xe46e4010, 0xb510bd10, 0xfbb2f7ff, 0x7800481c, 0xd10f2802, 0x23014c19, 
+    0x1ea42206, 0x46202140, 0xfff3f00e, 0x46202301, 0xe8bd2207, 0x21804010, 0xbfebf00e, 0x2100bd10, 
+    0xf7ff2001, 0x2200bb69, 0x4614b510, 0x1e43b128, 0xd20a2b09, 0x700c2000, 0x20ffbd10, 0xbd10700c, 
+    0xf0f3fbb0, 0xb2d21c52, 0x230ae000, 0xd8f7280a, 0xd3132805, 0x70082001, 0x0000e011, 0x1e0a6e00, 
+    0xf0008168, 0xf23c80dc, 0x00040582, 0xf2035078, 0x0004028a, 0xf20351da, 0xf38fffd4, 0x4610700c, 
+    0x0fc2bd10, 0x7fd1ebb2, 0xf1c1d203, 0x440831ff, 0x1a404770, 0x48184770, 0xf990b510, 0x28030000, 
+    0x2805d010, 0x2804d00e, 0x4814d00c, 0xff84f00e, 0xd4050780, 0xf00e4812, 0xb2c0ff7f, 0xd0002800, 
+    0xbd102001, 0x22054c0f, 0x46202120, 0xff9ff00e, 0xd0f52800, 0x46202204, 0xf00e2110, 0x2801ff98, 
+    0x4809d0ee, 0xff68f00e, 0xd1e92800, 0x1c804806, 0xff62f00e, 0x0000e7e2, 0x00040244, 0xf3cfffc2, 
+    0xf3cf2002, 0xf203502c, 0xf23c80e8, 0x4604b570, 0x680048f7, 0x0050f8b0, 0x104030a6, 0xea400400, 
+    0xf0400044, 0x48f30138, 0xff43f00e, 0x210048f1, 0xf00e3084, 0x48f0ff3e, 0xea404dee, 0x357c3184, 
+    0xf00e4628, 0x48edff36, 0x20107801, 0xfbd4f7ec, 0xea4048eb, 0x46283184, 0xff2bf00e, 0xbd702001, 
+    0x210048e4, 0xf00eb510, 0xe8bdff24, 0xf0014010, 0xb510bc7e, 0x4604b086, 0xfac6f001, 0xd0222800, 
+    0x308048dc, 0xff12f00e, 0x010bf3c0, 0xda022953, 0x31adf601, 0x3953e000, 0x0c810508, 0x1d0048d5, 
+    0xff07f00e, 0x4ad32101, 0x90002000, 0x4623323c, 0x0102e9cd, 0x91059104, 0x5130f240, 0x20019001, 
+    0xfc96f7eb, 0xb0062001, 0xe92dbd10, 0x000741f0, 0xf8df48cc, 0x68058334, 0xf998d103, 0xf7ff0000, 
+    0xf505ff95, 0xf5057626, 0x463074a6, 0xffc1f7ff, 0xffb6f7ff, 0x46202200, 0x68334629, 0xc0081c52, 
+    0xb2126873, 0x2a533610, 0xdbf6c108, 0xd1032f01, 0x0000f998, 0xff7af7ff, 0x22012100, 0xf8344608, 
+    0xb10b3b02, 0xb2894311, 0x00521c40, 0xb212b200, 0xdbf42810, 0xf8df2200, 0xf8dfe2d4, 0x3520c2d4, 
+    0x20004690, 0x8002f80c, 0x030ff001, 0x1603f3c1, 0x0383eb0e, 0x0686eb0e, 0x30c0f8d3, 0x6080f8d6, 
+    0xf3c14433, 0xeb0e2603, 0x6c360686, 0x0b0e4433, 0x6026f85e, 0xf9354433, 0xeb036b02, 0x429e03c3, 
+    0x2301da01, 0x2300e000, 0x6002f81c, 0x7b02f814, 0x4087405f, 0x433e0849, 0xb2001c40, 0x31c3ea41, 
+    0x2808b289, 0x6002f80c, 0x4b9adbce, 0x1c52549e, 0x2a10b212, 0xe8bddbc5, 0xb5f081f0, 0x4607b085, 
+    0x2500488b, 0x21014e90, 0x462c9500, 0x6800462a, 0x304ef9b0, 0x0000f996, 0xfb44f001, 0x21802001, 
+    0xe9cd2305, 0x90004001, 0xe9cd4618, 0xf9961403, 0x21072000, 0xfaf7f001, 0xfa06f001, 0xf001b118, 
+    0x0005fa21, 0xb17fd110, 0x6480f04f, 0x11f4f240, 0xf7e54620, 0xf246fa90, 0x46206166, 0xfa7af7e5, 
+    0x4620497d, 0xfa76f7e5, 0xfba1f001, 0x24004e78, 0xf0014620, 0xf846fa0e, 0x1c640024, 0x2c04b264, 
+    0xb005dbf6, 0xbdf04628, 0x4ff3e92d, 0xb08b486d, 0x4c724689, 0xf640af04, 0x68000200, 0xf5009007, 
+    0x91095180, 0x88244962, 0xf8b16809, 0x1ae3305e, 0x005b2410, 0xfc83fa0f, 0x93082300, 0x461e1e5d, 
+    0x1028e887, 0x46989f0b, 0x104cf8b1, 0x6700f507, 0xeba74b5d, 0xeba7070c, 0x39100141, 0xf9932702, 
+    0xea4f3000, 0xeb017ce1, 0xf36f4c9c, 0xeba10c0d, 0xf04f010c, 0xb2090c05, 0x1702e9cd, 0x2c00e9cd, 
+    0x46612207, 0xfb5af001, 0x22004855, 0x46934613, 0x0000f990, 0x900a9202, 0x494d4610, 0x540f2700, 
+    0xb2001c40, 0xdbf82810, 0xeb094261, 0x30200004, 0xe12b9003, 0x44089806, 0x98091907, 0x7017f830, 
+    0x30fff04f, 0x0047eb00, 0xfa0f9f07, 0x980afa80, 0x44204408, 0xc010f837, 0x0040eb07, 0x0c02f830, 
+    0x0000ebac, 0xfa0f00c0, 0x2001f980, 0xea4f4f37, 0xeb070c80, 0xfa231780, 0xfa22fe0c, 0xf00efc0c, 
+    0xf00c0e0f, 0x1c400c0f, 0xe02ef837, 0xf837b200, 0x2803702c, 0x0c07ebae, 0x0709eb0c, 0xf987fa0f, 
+    0xf8dfdbe4, 0xf003e0a8, 0xf002070f, 0xf8cd0c0f, 0xf83e9000, 0xf83e7027, 0xf00b002c, 0x1a3f0c0f, 
+    0x0009eb07, 0xf980fa0f, 0xf0009802, 0xf83e070f, 0xf83e002c, 0x1a3f7027, 0x45469800, 0xb2004438, 
+    0xd9049000, 0x0008eba6, 0x0e00f04f, 0x2000e002, 0x0e06eba8, 0x88374e1b, 0xf60afb17, 0x9701b237, 
+    0x0707eba9, 0x0609fb19, 0x0807fb07, 0x0700e9dd, 0x1bc04691, 0xfb009f00, 0xfb17e000, 0x9f02ec07, 
+    0x4566469e, 0xea4fd220, 0xea4f034e, 0xe01f0249, 0x000405f8, 0xf1000404, 0x000c04e5, 0x0004028b, 
+    0x000c14e5, 0x00040224, 0x00040570, 0x00041348, 0x00041448, 0x00041468, 0xdcba01f5, 0x00040560, 
+    0x00040568, 0x0004056a, 0x4666007b, 0x024bea4f, 0xd2114540, 0x0f01f1ba, 0x46504680, 0x2000d000, 
+    0x3ffff1ba, 0x0047ea40, 0xd0039002, 0xea402000, 0xe00f004b, 0xe7fa2001, 0x0f01f1ba, 0xd0004650, 
+    0xf1ba2000, 0xea403fff, 0x9002004e, 0x2000d00a, 0x0049ea40, 0x46834546, 0xfa23d20e, 0x07c0f004, 
+    0xe001d105, 0xe7f32001, 0xf004fa22, 0x2001e00a, 0xf04fe00a, 0xe00730ff, 0x40e09802, 0xd1f607c0, 
+    0xf004fa2b, 0xd1f407c0, 0xda002800, 0x9f0b4240, 0x1b3f440f, 0x7ce7ea4f, 0x6c1ceb07, 0x0cfff02c, 
+    0x0e0ceba7, 0xc020f8dd, 0xd10145e6, 0x2000b178, 0xdb3842a1, 0xc010f8dd, 0x0c5cea4f, 0x2001b100, 
+    0x70c0ea4c, 0x98059004, 0xd0021c40, 0x2001e01b, 0x9804e7ee, 0x4c27f5a0, 0x0cbbf1bc, 0xf643d113, 
+    0x443870e1, 0x17c527bb, 0x4595eb00, 0x050df36f, 0xb2001b40, 0x48f79005, 0x7007251f, 0x704727a7, 
+    0x70872700, 0x1c6870c7, 0x2d80d00d, 0x48f2da09, 0x28074028, 0x9804d105, 0x48ee0e07, 0x00e5eb00, 
+    0x1c6d7007, 0x9803b22d, 0xb2091c49, 0xdd024288, 0xf6ff2d80, 0x9805aecf, 0xe8bdb00d, 0xe92d8ff0, 
+    0xf8df4ff8, 0xf04fa3a0, 0x4fe40800, 0x34fff04f, 0x46424de3, 0x6680f507, 0xf8da463b, 0x88000000, 
+    0x8000f8cd, 0x0950ea4f, 0xf99048df, 0x20011000, 0xff8af7ea, 0x1000f8da, 0xf9b74bdc, 0xf8910000, 
+    0x78192068, 0x44111fc9, 0x80304108, 0xe0212001, 0x0240eb07, 0x1010f937, 0x2c02f932, 0xf8da1a89, 
+    0xf8922000, 0x781ac068, 0x44621fd2, 0xb2094111, 0xf8261c62, 0xd0051010, 0x460a2900, 0x4252da00, 
+    0xdd054542, 0x46042900, 0x4249da00, 0xf881fa0f, 0xb2001c40, 0xdbdb4548, 0xda002c03, 0xea4f2403, 
+    0xeb0601e8, 0xf9320244, 0x28000c06, 0x4240da00, 0xdd014288, 0xe0101ee4, 0x0c04f932, 0xda002800, 
+    0x42884240, 0x1ea4dd01, 0xf932e007, 0x28000c02, 0x4240da00, 0xdd004288, 0x20001e64, 0x18c1b263, 
+    0x1011f836, 0x1010f825, 0xb2001c40, 0xdbf62811, 0x22004eaf, 0x00c2eb05, 0x1008f9b0, 0x4006f9b0, 
+    0x7002f9b0, 0xf9b04421, 0x443c4004, 0xeb014421, 0xeb0604c1, 0x600c1182, 0x4008f9b0, 0x7006f9b0, 
+    0xf9b0443c, 0x443c7004, 0x7002f9b0, 0xeb041be4, 0x604c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 
+    0x1be47004, 0x7002f9b0, 0xeb04443c, 0x608c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1be47004, 
+    0x7002f9b0, 0xeb041be4, 0x60cc04c4, 0x4008f9b0, 0x7006f9b0, 0xc002f9b0, 0xf9b01be4, 0x44677004, 
+    0xeb04443c, 0x610c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x443c7004, 0x7002f9b0, 0xeb041be4, 
+    0x614c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb04443c, 0x618c04c4, 
+    0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb041be4, 0x61cc04c4, 0x4006f9b0, 
+    0xf9b01c52, 0xb2127008, 0xc002f9b0, 0xf9b01be4, 0x44677004, 0xeb04443c, 0x620c04c4, 0x4006f9b0, 
+    0x7008f9b0, 0xf9b01be4, 0x443c7004, 0x7002f9b0, 0xeb041be4, 0x624c04c4, 0x4006f9b0, 0x7008f9b0, 
+    0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb04443c, 0x628c04c4, 0x4006f9b0, 0x7008f9b0, 0xf9b01be4, 
+    0x1be47004, 0x7002f9b0, 0xeb041be4, 0x62cc04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1b3c7004, 
+    0x7002f9b0, 0xeb04443c, 0x630c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1b3c7004, 0x7002f9b0, 
+    0xeb041be4, 0x634c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x443c7004, 0x7002f9b0, 0xeb041b3c, 
+    0x638c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0xf9b07004, 0x44380002, 0x42404420, 0xeb002a04, 
+    0x63c800c0, 0xaf16f6ff, 0x493a8828, 0x00c0eb00, 0x80080040, 0x70034838, 0x8ff8e8bd, 0xf7ffb510, 
+    0x2002fe8e, 0xff90f7eb, 0xf2404604, 0xf6431100, 0xf7ff7060, 0x2002fcf9, 0xff86f7eb, 0x1a20492f, 
+    0x1000f9b1, 0xf0f1fbb0, 0x6008492d, 0xe92dbd10, 0xf24041f0, 0xf7ff2500, 0x2400fe72, 0x36fff04f, 
+    0x6700f643, 0x0800f248, 0x4629e02e, 0xf7ff4638, 0x1c41fcdb, 0xf5a0d01e, 0xb200507e, 0x6480f04f, 
+    0xeb000fc1, 0xf2403081, 0xb20611f4, 0xf7e44620, 0x491cff42, 0xf7e44620, 0x491bff2d, 0xf7e44620, 
+    0x4631ff29, 0xf7e44620, 0x4918ff25, 0xf7e44620, 0xe00dff21, 0x1c641979, 0xb22417c8, 0x4090eb01, 
+    0x000df36f, 0xb2071a08, 0xf0f5fb98, 0xdccc42a0, 0xe4604630, 0x00041448, 0x80000007, 0x00043978, 
+    0x00044378, 0x000405f8, 0x00040570, 0x0004036b, 0x00041348, 0x0004056a, 0x00040568, 0x000405e8, 
+    0x0004056c, 0xa5a55a5a, 0xdde50000, 0xdcba01f5, 0x5c0849fe, 0xe92d4770, 0x4cfd47f0, 0xf248b283, 
+    0x26000700, 0x25074639, 0x220f4620, 0xfad1f00e, 0xf2402380, 0x220031ff, 0xf00e4620, 0x2306faca, 
+    0x21ff2200, 0xf00e1ca0, 0x48f2fac4, 0x217f2200, 0xf8b06800, 0x1d20304a, 0xfabbf00e, 0x0802f1a4, 
+    0x46444639, 0xf00e4640, 0xf248fa9a, 0x46200180, 0xfa95f00e, 0xa398f8df, 0xf8df2400, 0xf10a939c, 
+    0xf04f0a0e, 0xf04f0204, 0xf89901f0, 0x28030000, 0xd0054650, 0xfaabf00e, 0x070043c0, 0xe004d01b, 
+    0xfaa5f00e, 0x0000ea35, 0x1c64d013, 0xdbe842bc, 0x46442301, 0x4640220a, 0x4629029d, 0xfa89f00e, 
+    0x46292300, 0x4620220a, 0xfa83f00e, 0xe8bd4630, 0x260187f0, 0x2200e7ec, 0x210f4650, 0xfa87f00e, 
+    0xf00049ce, 0x700a0201, 0x0240f3c0, 0xf3c0704a, 0x708a0280, 0x00c0f3c0, 0xe7ea70c8, 0x220048c4, 
+    0x41f0e92d, 0xf6433030, 0xf00e71ff, 0xb204fa70, 0x07e04dc3, 0x2301d00e, 0x22094628, 0x4631025e, 
+    0xfa57f00e, 0x46312300, 0x46282209, 0xfa51f00e, 0xb2241e64, 0xf2404fb7, 0x68381600, 0x006af8b0, 
+    0xfa0f1a20, 0x2400f880, 0x2301e00c, 0x22084631, 0xf00e4628, 0x2300fa3e, 0x22084631, 0xf00e4628, 
+    0x1c64fa38, 0x7a016838, 0x44117a42, 0xf8b07a82, 0xeb02006a, 0x44080050, 0x0f40ebb4, 0x6838dbe5, 
+    0xeba87a01, 0x49a70041, 0xf3c03062, 0x7809004c, 0xf82ff7ed, 0xe8bd4640, 0xe92d81f0, 0x468943f0, 
+    0xb11ab143, 0xf1a44ca0, 0xe00d0584, 0xf1a44c9f, 0xe0090584, 0x4c9cb122, 0xf1a43ca8, 0xe0030584, 
+    0x34a84c99, 0x0584f1a4, 0xe004f890, 0xb9026807, 0xf04f2201, 0xe01f0c00, 0x46192300, 0xfa274618, 
+    0x07f6f600, 0xf1c0d007, 0xf8140820, 0x40736008, 0x6028f855, 0x1c404071, 0x2820b200, 0xea5fdbef, 
+    0xd00370ce, 0x40437820, 0x40416828, 0xf10c469e, 0x460f0c01, 0xfc8cfa0f, 0xdbdd4594, 0x7e00e9c9, 
+    0x83f0e8bd, 0x47fce92d, 0x48814682, 0x9204f8df, 0xf8df2501, 0x460f81ec, 0x7001464a, 0x464002a9, 
+    0xfa92f00e, 0x487c4606, 0x0000f990, 0xd0172803, 0xd0222802, 0xd02d2801, 0x3012486d, 0xf99cf00e, 
+    0x486b9001, 0xf00e3014, 0x9000f997, 0x30164868, 0xf992f00e, 0x24009900, 0x4001ea40, 0xe02c9000, 
+    0x30244863, 0xf988f00e, 0x48619001, 0xf00e3026, 0x9000f983, 0x3028485e, 0x485de7ea, 0xf00e301e, 
+    0x9001f97b, 0x3020485a, 0xf976f00e, 0x48589000, 0xe7dd3022, 0x30184856, 0xf96ef00e, 0x48549001, 
+    0xf00e301a, 0x9000f969, 0x301c4851, 0x4669e7d0, 0x46082200, 0xff61f7ff, 0x46531c64, 0xdbf642bc, 
+    0x462a4669, 0xf7ff4608, 0x9800ff58, 0x4848b281, 0xf00e300a, 0x9800f954, 0x48450c01, 0xf00e3008, 
+    0x9801f94e, 0x4842b281, 0xf00e1d80, 0xf246f948, 0x46440700, 0x46392300, 0x4640220d, 0xf959f00e, 
+    0xf2404846, 0xf9903120, 0x28040000, 0x2805d01e, 0xf44fd01f, 0x464b107a, 0x43452210, 0xf0f1fb95, 
+    0x1a304621, 0xf00e3020, 0x2300fa1f, 0x220d4639, 0xf00e4620, 0x4833f93e, 0x78032201, 0xf9b04838, 
+    0x20001000, 0xfffff7ec, 0x87fce8bd, 0x007af44f, 0xf44fe7e1, 0xe7de00fa, 0xb2834a2f, 0x4d24b570, 
+    0xf24821ff, 0x70110400, 0x4621220f, 0xf00e4628, 0x2380f920, 0x31fff240, 0x46282200, 0xf919f00e, 
+    0x22002306, 0x1ca821ff, 0xf913f00e, 0x22004819, 0x6800217f, 0x304af8b0, 0xf00e1d28, 0x4621f90a, 
+    0x23011eac, 0x220f4620, 0xf903f00e, 0x46202300, 0x21402206, 0xf8fdf00e, 0x46202300, 0x21202205, 
+    0xf8f7f00e, 0x46202300, 0x21102204, 0xf8f1f00e, 0x46202300, 0x461a210f, 0xf8ebf00e, 0x46202300, 
+    0x21802207, 0xf8e5f00e, 0xe01b2301, 0x00040570, 0xf2035094, 0x000405f8, 0x0004027c, 0x00040574, 
+    0xf2035092, 0x0004028b, 0x00040a70, 0x00040bc0, 0x00040277, 0xf000810c, 0x00040276, 0x0004028a, 
+    0x00040560, 0xe8bd4620, 0x22074070, 0xf00e2180, 0xe92db8c0, 0x4fff41f0, 0x46062400, 0x0500f248, 
+    0x46382204, 0xf00e21f0, 0xb240f8c2, 0x1c64b910, 0xdbf542ac, 0x46382204, 0xf00e21f0, 0xb204f8b8, 
+    0x072148f5, 0x2103d501, 0x0761e00c, 0x2102d501, 0x07a1e008, 0x2101d501, 0x07e1e004, 0x2100d001, 
+    0x21ffe000, 0xb2487001, 0xd0041c41, 0x5c0949eb, 0xf7ff4630, 0xb260feb7, 0xb510e66d, 0xf7ff4604, 
+    0x4620ff5b, 0x4010e8bd, 0xb510e7c3, 0x21004ce4, 0xf99448e2, 0x54812000, 0x2001f994, 0x54812101, 
+    0x2002f994, 0x54812102, 0x2003f994, 0x54812103, 0x3003f990, 0x2002f990, 0x1001f990, 0x0000f990, 
+    0xfc9ef7ed, 0x3003f994, 0x2002f994, 0x1001f994, 0x0000f994, 0x4010e8bd, 0xbe52f7f0, 0xb53048d1, 
+    0xe9d0b087, 0xe9cd1200, 0x21001200, 0x91039102, 0xe9d0aa04, 0xe9cd1002, 0xa9021004, 0xf7ee4668, 
+    0x48c9fb9c, 0x7800466b, 0xd1102803, 0xf99048c7, 0xf9901000, 0xf8332002, 0xf8231011, 0xf9901012, 
+    0xf9901001, 0xf8330003, 0xf8231011, 0x21001010, 0xf8334608, 0x1c402010, 0x4411b200, 0x2804b209, 
+    0x1c89dbf7, 0x49ba1088, 0xf8b5680d, 0x1a40106e, 0x1000f9bd, 0xf020b200, 0x20010401, 0x2010f933, 
+    0xdd00428a, 0x1c404611, 0x2804b200, 0xf8b5dbf6, 0x1c492042, 0x0070f8b5, 0x0101f021, 0x0342eb00, 
+    0x88104aac, 0xeb014245, 0x44190145, 0x1b61b20d, 0x0061eba0, 0x48a8b201, 0x22018011, 0x46287803, 
+    0xfec1f7ec, 0x4628b007, 0xe92dbd30, 0x489d4ff0, 0xf8dfb08b, 0x4e99928c, 0xa27cf8df, 0x1004e9d0, 
+    0x1005e9cd, 0x499d2000, 0x46059003, 0x90019000, 0x90089002, 0x1000f991, 0x49959107, 0x88096809, 
+    0xea4f9009, 0x46690851, 0xa805aa02, 0xfb25f7ee, 0xf890488d, 0xf1bcc000, 0xd1110f03, 0xa905488b, 
+    0x2000f990, 0x3002f990, 0x2012f831, 0x2013f821, 0x2001f990, 0x0003f990, 0x2012f831, 0x2010f821, 
+    0x7000f899, 0xab042000, 0x2f014683, 0xf8035632, 0xf93db002, 0xd009e010, 0x458e2140, 0xa905dd0b, 
+    0xe010f931, 0xda0445c6, 0xe0032101, 0x1100f240, 0x2102e7f3, 0x1c405499, 0x2804b2c0, 0x4879d3e5, 
+    0x28037800, 0x2001d102, 0x0013f88d, 0x0f03f1bc, 0xf89dd107, 0xf88d0010, 0xf89d0012, 0xf88d0011, 
+    0xf2420013, 0x06c80170, 0xfbb1f7e4, 0x0b00f44f, 0x11f4f240, 0xf7e44658, 0x496bfb9e, 0xf7e44658, 
+    0x4f5ffb89, 0x1003f997, 0x0000f997, 0x2001f997, 0x3001eb00, 0x1002f997, 0xeb010209, 0x44011102, 
+    0xf7e44658, 0x4861fb77, 0xff46f00d, 0x46584601, 0xfb70f7e4, 0xf00d485e, 0x4601ff39, 0xf7e44658, 
+    0xf89dfb69, 0xf89d1013, 0xf89d0010, 0xeb002011, 0xf89d3001, 0x02091012, 0x1102eb01, 0x46584401, 
+    0xfb58f7e4, 0x0010f89d, 0x1011f89d, 0x2900b158, 0x1012f89d, 0xb309d001, 0x2900e023, 0x1013f89d, 
+    0xb139d015, 0xb151e01d, 0x1012f89d, 0xf89db9d9, 0xb1680013, 0x78797838, 0x70787039, 0xf89de023, 
+    0x28000012, 0x0013f89d, 0xb908d01c, 0xb941e01b, 0x4000f997, 0x70387878, 0xe02b707c, 0x1013f89d, 
+    0x2802b189, 0xf89dd015, 0x29021011, 0xf89dd011, 0x2a022012, 0xf89dd00d, 0x2b023013, 0x2801d009, 
+    0xe011d118, 0xf997b1b0, 0x78f84002, 0x70fc70b8, 0x4828e010, 0xf89a2201, 0xf9b03000, 0xf06f1000, 
+    0xf7ec000f, 0xe005fdc0, 0xd1032901, 0xd1012a01, 0xd0132b01, 0x46584927, 0xfafcf7e4, 0xfe65f7ff, 
+    0x0000f899, 0x48142801, 0x0000f990, 0xd0035c31, 0x78004821, 0xd0092801, 0xe0082001, 0xf44f491d, 
+    0xf7e40000, 0x2001fae7, 0xe00d9009, 0xf7ff2000, 0xf89afcf9, 0xf44f1000, 0xf7eb2080, 0x1c6dfb4d, 
+    0x2d03b22d, 0xaeeff6ff, 0x0003f996, 0xf835ad02, 0xe0233010, 0xf20350a2, 0x00040276, 0x0004057c, 
+    0x00040570, 0x0002cf04, 0x000405d9, 0x00040578, 0x000405f8, 0x00040560, 0x0004028b, 0x00040290, 
+    0x000402ec, 0x0004027c, 0x77777776, 0xf2030446, 0xf100000c, 0xdcba01f5, 0x0004055c, 0xb280f8df, 
+    0xf640220b, 0x465f0100, 0xf00d4658, 0xf996fe92, 0x220a0002, 0x4100f240, 0x3010f835, 0xf00d4638, 
+    0xf996fe88, 0x22090001, 0x2100f240, 0x3010f835, 0xf00d4638, 0xf996fe7e, 0x22080000, 0xf8350151, 
+    0x46383010, 0xfe75f00d, 0x0001f996, 0x0914f10d, 0x3002f996, 0x7800f647, 0x2010f839, 0x0000f996, 
+    0x3013f839, 0x0010f839, 0xf9961a1f, 0x1a123003, 0x1013f839, 0x2208b293, 0x46411a0d, 0x0002f10b, 
+    0xfe57f00d, 0xf10bb2bb, 0x22000704, 0x217f4638, 0xfe4ff00d, 0x4641b2ab, 0x46382208, 0xfe49f00d, 
+    0x81e0f8df, 0x0000f998, 0x28005c30, 0x0002f998, 0xd0035c30, 0xd0052802, 0xe0062300, 0xd0032802, 
+    0xe0022301, 0xe0002302, 0x46582303, 0x21c02206, 0xfe2ff00d, 0x28009809, 0xf7ffd07e, 0x2000fdcf, 
+    0xff06f7eb, 0x78304e68, 0xd00b2801, 0xfab3f7ec, 0x4b00f04f, 0x0170f242, 0xf7e44658, 0x7830fa48, 
+    0xe015b118, 0xfa5bf7ec, 0x2100e7f2, 0xf7ed2001, 0x4d5efe78, 0x200c2100, 0x2000f995, 0xfbd8f7ed, 
+    0xf9952101, 0x46082000, 0xfc18f7ed, 0xfe8ff7f0, 0x0170f242, 0xf7e44658, 0x4855fa2a, 0x28057800, 
+    0x2701d002, 0xe0082500, 0xe7fb2703, 0xfaaff7ff, 0x2c00b204, 0x1c6dda03, 0x42bdb22d, 0x1c60dbf6, 
+    0x2001d03a, 0x20009008, 0xfec2f7eb, 0xd00a07e0, 0x22014848, 0x3000f89a, 0x1000f9b0, 0xf7ec4610, 
+    0x1c64fca2, 0xf89ab224, 0x10601000, 0xf7ec4654, 0x4d40fbe0, 0x78232201, 0xf9b52000, 0xf7ec1000, 
+    0xaa02fc92, 0xa8054669, 0xf917f7ee, 0x7800483a, 0xd10f2803, 0x2000f998, 0x3002f998, 0x2012f839, 
+    0x2013f829, 0x2001f998, 0x0003f998, 0x2012f839, 0x2010f829, 0xe0002001, 0xf9bde04e, 0x464b1014, 
+    0x2010f933, 0xda00428a, 0x1c404611, 0x2804b2c0, 0x4f2ad3f6, 0xb2083908, 0x794a6839, 0x441a798b, 
+    0xeb03790b, 0x882b0060, 0x8f4a4410, 0x1a10441a, 0x2038f891, 0x2100b200, 0xfbc7f7ec, 0xf9b06838, 
+    0xf7ed0040, 0x7821fd35, 0x0000f640, 0xfa04f7eb, 0x28017830, 0x4815d017, 0x0000f990, 0x1cc09007, 
+    0xeb0017c1, 0xf0217191, 0x1a400103, 0xf7f0b240, 0xf7ecff7e, 0xf242fa00, 0x46580170, 0xf997f7e4, 
+    0xb1187830, 0xf7ece005, 0xe7f4f977, 0xf7f09807, 0x2001ff6e, 0xfe3cf7eb, 0xb00b9808, 0x8ff0e8bd, 
+    0xf203501a, 0x00040578, 0x0004055c, 0x00040290, 0x0004028a, 0x00040560, 0x000405d9, 0x000405f8, 
+    0x2a05b570, 0xd0019e04, 0xd10d2a04, 0xd0092b01, 0xd0072b02, 0x4b4c4a4b, 0x781b7812, 0xd0014313, 
+    0xd1012a03, 0xb2401c80, 0x2101b119, 0x0040eb01, 0x0040e000, 0x280cb240, 0x2400da03, 0x050cf1c0, 
+    0xf1a0e014, 0x290c010c, 0x2401d203, 0x0518f1c0, 0xf1a0e00c, 0x290c0118, 0x2402d203, 0x0524f1c0, 
+    0x2824e004, 0x2403db02, 0x0530f1c0, 0x0200f04f, 0xf04fb2a3, 0x2e010103, 0x4834d040, 0xfd09f00d, 
+    0xb2a34832, 0x21032200, 0xf00d1c80, 0x482ffd02, 0x2200b2a3, 0x1d002103, 0xfcfbf00d, 0xb2a3482b, 
+    0x21032200, 0xf00d1d80, 0x4828fcf4, 0x2200b2ab, 0x302e210f, 0xfcedf00d, 0xb2a34e25, 0x210c2202, 
+    0xf00d4630, 0xb2a3fce6, 0x22004630, 0xf00d2103, 0x1cb6fce0, 0x4630b2a3, 0x210c2202, 0xfcd9f00d, 
+    0x4630b2a3, 0x21032200, 0xfcd3f00d, 0x210f2200, 0x1cb0b2ab, 0x4070e8bd, 0xbccbf00d, 0x30084813, 
+    0xfcc7f00d, 0xb2a34811, 0x21032200, 0xf00d300a, 0x480efcc0, 0x2200b2a3, 0x300c2103, 0xfcb9f00d, 
+    0xb2a3480a, 0x21032200, 0xf00d300e, 0x4807fcb2, 0x2200b2ab, 0x3030210f, 0xfcabf00d, 0x4070e8bd, 
+    0xbab0f7ec, 0x000405d9, 0x0004053e, 0xf2034200, 0xf203900e, 0x220e4912, 0x4d12b570, 0x18447809, 
+    0x0100f24c, 0x0303f004, 0xf00d4628, 0x2200fc92, 0x1ca82107, 0x0382f3c4, 0xfc8bf00d, 0x46282301, 
+    0x21202205, 0xfc85f00d, 0x20402100, 0xf904f7eb, 0xe8bd4628, 0x23004070, 0x21202205, 0xbc79f00d, 
+    0x00040363, 0xf203f042, 0x4cfeb510, 0xf7ebe002, 0xb160f8b1, 0xf00d4620, 0x0300fc49, 0x0002f04f, 
+    0xf7ebd4f5, 0x49f8f8a1, 0x20016008, 0x4cf7bd10, 0xf00d4620, 0xf040fc41, 0x46200110, 0xfc3ff00d, 
+    0xbd102000, 0xb51048ef, 0xf00d1d00, 0x0fc0fc2f, 0x49ecbd10, 0x0003f1c0, 0xeb01310c, 0xf00d0080, 
+    0xe92dbc25, 0xf8df41f0, 0x108d839c, 0x4604b086, 0x0840f1a8, 0x2b01b133, 0x2b02d014, 0x2b03d06e, 
+    0xe0a8d06f, 0x90052000, 0x90042201, 0x46239000, 0xe9cd9001, 0x00880202, 0xb2014642, 0xf7ea2001, 
+    0xe098f9a7, 0xf04f2a07, 0xd0540600, 0x0745eb05, 0x4640e019, 0xfbfaf00d, 0x0026f844, 0xf00d4640, 
+    0x1971fbf5, 0x0021f844, 0xf00d4640, 0xeb06fbef, 0xf8440145, 0x46400021, 0xfbe8f00d, 0x1c7619b9, 
+    0xf844b236, 0x42ae0021, 0xe074dbe3, 0x46404647, 0xfbdcf00d, 0x0202f000, 0x0101f000, 0x31c2ea41, 
+    0x1026f844, 0x0108f000, 0x0280f3c0, 0x3141ea42, 0xf8441972, 0xf0001022, 0xf3c00120, 0xea421200, 
+    0xeb0621c1, 0xf8440245, 0xf0001022, 0xf3c00180, 0xea401080, 0xeb052041, 0x44310145, 0x0021f844, 
+    0xf00d4638, 0x4638fbb3, 0xfbb0f00d, 0xf00d4638, 0x1c76fbad, 0x42aeb236, 0xe03cdbc8, 0x46472600, 
+    0xe015e013, 0xf00d4638, 0x1971fba1, 0x0021f844, 0xf00d4638, 0xf844fb9b, 0x46380026, 0xfb96f00d, 
+    0xf00d4638, 0x1c76fb93, 0x42aeb236, 0xe022dbea, 0x463e2700, 0x4640e01d, 0xfb88f00d, 0x0027f844, 
+    0x46401c7f, 0xf00db23f, 0xf844fb81, 0x1c7f0027, 0xb23f4640, 0xfb7af00d, 0x0027f844, 0x46401c7f, 
+    0xf00db23f, 0xf844fb73, 0x1c7f0027, 0xb23f1c76, 0x42aeb236, 0xb006dbdf, 0x2100488a, 0xe8bd387c, 
+    0xf00d41f0, 0xe92dbb66, 0x27005ff0, 0x2b0b4698, 0xe9dd4692, 0xf8dd6b0d, 0x460c902c, 0xd1044605, 
+    0x46494880, 0xf00d301c, 0x1c60fb54, 0x2c07d007, 0x2d05d106, 0x2d06d001, 0x2701d102, 0x2400e000, 
+    0xdd022e00, 0x1e401070, 0x4876b206, 0x30084631, 0xfb3ff00d, 0xea4f980c, 0xea41718b, 0xea417109, 
+    0x980a5100, 0x40c0ea41, 0x4187ea40, 0x318aea41, 0x2088ea41, 0x1144ea40, 0x4329486a, 0x5ff0e8bd, 
+    0xbb27f00d, 0x460db570, 0x9c041059, 0xea410409, 0xea411142, 0xea4101c5, 0xf0400040, 0x48610110, 
+    0xf00d387c, 0x2c00fb16, 0x485ed006, 0xe8bd4621, 0x38784070, 0xbb0df00d, 0xb570bd70, 0x48594606, 
+    0x460d4614, 0xf6402200, 0x1d0071ff, 0xfb18f00d, 0xb925b12e, 0x0064ebb0, 0xf500d501, 0xf6436040, 
+    0xe8bd71ff, 0x00834070, 0x2200484e, 0xf00d3878, 0xb5f0baf9, 0x56614c4e, 0x29013c10, 0x2910d011, 
+    0x2501da0f, 0x408d1e49, 0xf04f6065, 0x408d35ff, 0x6021b2a9, 0x040989a1, 0x892160e1, 0x60a10409, 
+    0x2100e001, 0x68676061, 0x2f00b132, 0x6826d01c, 0xe9d42100, 0xe0264502, 0xd0152f00, 0x21006826, 
+    0x4502e9d4, 0xf850e00d, 0x423a2021, 0x4332d002, 0x2021f840, 0xd002422a, 0xf8404322, 0x1c492021, 
+    0xebb1b209, 0xdbee0f43, 0xf850bdf0, 0x423a2021, 0x4332d002, 0x2021f840, 0xd002422a, 0xf8404322, 
+    0x1d092021, 0xebb1b209, 0xdbee0f43, 0x4825bdf0, 0x22032301, 0x30482108, 0xbaa4f00d, 0x4fffe92d, 
+    0xf04fb081, 0x46980900, 0x460d4614, 0x0a01f04f, 0x464f9e0e, 0xb00fe9dd, 0x7f80f5b6, 0x9000f8cd, 
+    0x4430dc01, 0xf1bbb200, 0xd0050f05, 0x1c612000, 0x2c07d00e, 0xe00cd006, 0xf04f1040, 0xf04f0901, 
+    0xe7f40a00, 0xd0012d05, 0xd1022d06, 0xe0072701, 0x490f2400, 0x5d49310b, 0xd1012901, 0x0800f04f, 
+    0xea410401, 0xea411149, 0xf0400048, 0x48050118, 0xf00d387c, 0x4803fa5e, 0x30089900, 0xfa59f00d, 
+    0xe00704b9, 0xf1000480, 0x00040278, 0xf203517e, 0x00040bf4, 0x3088ea41, 0x1144ea40, 0x4329481d, 
+    0x481d4301, 0xfa45f00d, 0x7801481c, 0x4000f240, 0xfee2f7ea, 0x700aea4f, 0x4187ea40, 0x3188ea41, 
+    0x208bea41, 0x1044ea40, 0xf4404328, 0x48122100, 0xfa2ff00d, 0xfdd8f7ff, 0xd0182800, 0xf00d4810, 
+    0xb204fa2b, 0x46329900, 0xf7ff4648, 0x0070ff16, 0xb2019b11, 0x462a9801, 0xfdf3f7ff, 0xff77f7ff, 
+    0x46339801, 0x4629463a, 0xff23f7ff, 0xb0054620, 0x8ff0e8bd, 0x00080400, 0xf1000480, 0x0004028b, 
+    0xf2035120, 0x4ff0e92d, 0x2000b089, 0x48fe9007, 0x20099005, 0x900449fd, 0xf8df48fd, 0x680cb3fc, 
+    0x48fc9006, 0x78009408, 0xd10a2804, 0x0000f89b, 0xd1062803, 0x784048f9, 0xd0022801, 0x1c8048f4, 
+    0xf8df9006, 0x22b183dc, 0x21014ff7, 0xf5044ef5, 0xf5045a80, 0xf8c859c0, 0x46352000, 0x0000f997, 
+    0xfa6af7f0, 0x0000f997, 0xf923f7f0, 0xf8c821b2, 0x20001000, 0xf8c7f7f0, 0xf7f02002, 0xf997fb32, 
+    0xf7f00000, 0x2100f8c7, 0x0000f244, 0xf918f7f0, 0x0000f997, 0xf87af7f0, 0xf44f2100, 0xf7ea2000, 
+    0x21b3fe5b, 0x23c048e1, 0x1000f8c8, 0xf2402200, 0xf00d11ff, 0xf997f9ce, 0xf7f00000, 0x4fdcf9b9, 
+    0xe00b2000, 0x780949db, 0x2901b3f1, 0x49dad050, 0x1010f831, 0x1010f825, 0xb2001c40, 0x88096839, 
+    0x0f51ebb0, 0x48ccdbee, 0x0800f04f, 0x28037800, 0x2300d041, 0x461a2101, 0x5800e9cd, 0xf7e94608, 
+    0x2101fbb0, 0x230548c1, 0x2b00f240, 0xf8cd028a, 0x9103b000, 0x3201e9cd, 0x68001e8a, 0x2105460b, 
+    0xfedcf7ff, 0xf04f48bc, 0x78000100, 0x46082803, 0x4ab6d02a, 0x681346dc, 0x2011f933, 0xda002a00, 
+    0x1c494252, 0xe0004410, 0xb209e010, 0xdbf34561, 0x21001240, 0xdd042810, 0x10401c49, 0x2906b249, 
+    0x48b6dbf8, 0x28037800, 0xe020d020, 0xe7af49b4, 0x398049b1, 0x48a9e7ac, 0xe9cd2300, 0x461a5800, 
+    0x1001f990, 0xe7ba2001, 0x46dc4aa4, 0xf9929b08, 0xeb032001, 0xf9332382, 0x2a002011, 0x4252da00, 
+    0xb2091c49, 0x44104561, 0xe7d1dbf5, 0xf8df2105, 0xf8dfe288, 0x2000c280, 0xf1ae4b9f, 0xe00c0e80, 
+    0x2000f89c, 0xd07d2a00, 0xd07c2a01, 0x2010f933, 0xf825410a, 0x1c402010, 0x683ab200, 0xebb08812, 
+    0xdbed0f52, 0x20b44f8e, 0x461a2300, 0x60384619, 0xe9cd2001, 0xf7e95800, 0x20b5fb34, 0x23006038, 
+    0x461a2101, 0x5800e9cd, 0xf7e94608, 0x20b6fb2a, 0x23006038, 0x461a2102, 0xe9cd2001, 0xf7e95800, 
+    0x20b7fb20, 0x23006038, 0x461a2103, 0xe9cd2001, 0xf7e95800, 0x20b8fb16, 0x60384641, 0xf8462000, 
+    0x1c401020, 0xf5b0b200, 0xdbf87f00, 0x46bb2500, 0xf7ea2002, 0x4f7afd39, 0x3f204623, 0x20b961f8, 
+    0x3105eb00, 0x1000f8cb, 0x0000f640, 0x48689000, 0x9a062101, 0xf00d3846, 0x2002fff5, 0xfd24f7ea, 
+    0xf64069f9, 0x1a080200, 0x486e61f8, 0xf1002100, 0xf8400814, 0x1e491025, 0x1015f828, 0x46082100, 
+    0x3020f854, 0xb2001c40, 0x44194290, 0x12c9dbf8, 0xf8542000, 0x1a5b3020, 0x3020f844, 0xb2001c40, 
+    0xe0014290, 0xe012e00f, 0x4852dbf3, 0x0000f990, 0xd00f2804, 0xd00f2805, 0x22042700, 0x40ba2000, 
+    0x6300f5c2, 0x4a56e019, 0x2010f932, 0xf93ee770, 0xe76d2010, 0xe7f02702, 0xe7ee2701, 0x0e01eb00, 
+    0xc020f854, 0xb2091c49, 0xe02ef854, 0xf84444f4, 0x428ac020, 0x1c40dcf2, 0xf04fb200, 0x42830100, 
+    0x2000dcf7, 0x0e06f1c7, 0xf854e009, 0x4411c021, 0xfa0cb209, 0xf844fc0e, 0x1c40c020, 0x428bb200, 
+    0x2100dcf3, 0x2200f240, 0xda044290, 0x1020f844, 0xb2001c40, 0x20bae7f8, 0xeb00464b, 0xf8cb3105, 
+    0xe9dd1000, 0x46521004, 0x0100e9cd, 0x46209907, 0xf982f00d, 0x4b3320bb, 0x3105eb00, 0x1000f8cb, 
+    0xf1c7200e, 0xf85a070c, 0xf8592020, 0x413a1020, 0x41394352, 0x2101fb01, 0x1020f844, 0x2020f856, 
+    0x01e1eb02, 0x1020f846, 0x1020f854, 0x2025f853, 0xdd034291, 0x1025f843, 0x0015f828, 0xb2001c40, 
+    0xdbe028c3, 0x1015f938, 0xeb041e48, 0xf8540c81, 0xf8543021, 0x44082020, 0xc004f8dc, 0x41c8f04f, 
+    0x0743eba2, 0x1ad24467, 0xfb9212bb, 0xeb02f2f3, 0x4a132040, 0x61903a20, 0xfb8069d2, 0x17d30101, 
+    0xe98ef00c, 0x0000e020, 0x0002d960, 0x00040224, 0xf203044c, 0x0004028a, 0x000405d9, 0x00040578, 
+    0x0004069c, 0x00043978, 0x00040290, 0xf2030864, 0x000405f8, 0x0004036b, 0x00040dac, 0x0004027c, 
+    0x00040c2c, 0x0004e6b0, 0x840cf8df, 0x4240f04f, 0xf1411880, 0xeb0831ff, 0xe9c707c5, 0x48ff0100, 
+    0x1035f858, 0x1025f840, 0x3000f44f, 0x1103f240, 0xfc11f7e3, 0x68397938, 0xea420402, 0xb2814011, 
+    0x3000f44f, 0xfbf6f7e3, 0x0035f838, 0xf44fb281, 0xf7e33000, 0x20bcfbef, 0x3105eb00, 0x1000f8cb, 
+    0xb26d1c6d, 0xf6ff2d05, 0xf108aed3, 0xf1020228, 0x25000314, 0x60151e68, 0x200e8018, 0x1020f856, 
+    0x1020f844, 0x1020f856, 0x7025f852, 0xdd0342b9, 0x1025f842, 0x0015f823, 0xb2001c40, 0xdbed28c3, 
+    0x1015f933, 0xeb041e48, 0xf8560481, 0xf8563021, 0x44082020, 0xf04f6864, 0xeba241c8, 0x44340643, 
+    0x12a31ad2, 0xf2f3fb92, 0x2040eb02, 0x61904ad4, 0xfb8069d2, 0x17d30101, 0xe902f00c, 0xf04f4ece, 
+    0x18824240, 0xf141465f, 0xeb0630ff, 0xf44f04c5, 0xe9c43800, 0x48c92000, 0x1035f856, 0x20bd6141, 
+    0x1103f240, 0x0000f8cb, 0xf7e34640, 0x7920fba4, 0x04026821, 0x4011ea42, 0x4640b281, 0xfb8af7e3, 
+    0x0035f836, 0x4640b281, 0xfb84f7e3, 0x0035f836, 0xb2017922, 0x0c006820, 0x4002ea40, 0xf7efb200, 
+    0x20befe9f, 0x48b76038, 0x0000f990, 0xfdfef7ef, 0x603820bf, 0x2001b009, 0x4ff0e8bd, 0xbb11f7e9, 
+    0x4ffee92d, 0x21012500, 0xf04f462c, 0x462a4071, 0xf00c9502, 0x4eabff45, 0xd0092801, 0xf2402301, 
+    0xf99631fe, 0x22000000, 0xfe44f7ef, 0x8ffee8bd, 0x48a52208, 0xf00c0151, 0x2208ff4a, 0x01512300, 
+    0xfb80fa4f, 0xf00c48a0, 0x48a0ff34, 0x090af04f, 0xf04f4f9f, 0xf8df0301, 0xf04f827c, 0x78000200, 
+    0xd04b2801, 0x8700e9cd, 0x1000f996, 0xf7e92001, 0xf8dff9d3, 0x2000c268, 0xa25cf8df, 0xf10c4643, 
+    0xf85c0850, 0xf93ae030, 0xf9371010, 0xf9332011, 0xfba21011, 0x19552e0e, 0x2030f858, 0x0001f100, 
+    0xfba1b2c0, 0x190c1202, 0xd3ea4548, 0x1b2c488c, 0x1000f996, 0x0500f04f, 0xf04f4f81, 0xf8400203, 
+    0x69784021, 0x0138f04f, 0x0001f100, 0x48856178, 0xfefdf00c, 0xd07d2800, 0x81ecf8df, 0x22022303, 
+    0x08c4f108, 0x4640210c, 0xfee3f00c, 0x91d8f8df, 0x0000f44f, 0xf1099002, 0xe09b0956, 0xe9cd4871, 
+    0xf9908700, 0x20011000, 0xf986f7e9, 0xf8df2400, 0x21c981cc, 0x0850f108, 0xfa01fb19, 0x4a6f486e, 
+    0xf9303a28, 0x486b1014, 0x0011f830, 0x0014f822, 0xf8324a67, 0x4a695011, 0xf10afb11, 0xf8223a14, 
+    0xfb105014, 0xfb15f200, 0xfb812205, 0x04c12302, 0x46162000, 0xf00c461f, 0x0c02e814, 0xea42485f, 
+    0x463b4201, 0xeb001409, 0xe9c000c4, 0x04e92100, 0x20004632, 0xe804f00c, 0xea420c02, 0xeb084201, 
+    0x140900c4, 0xb2e41c64, 0xe9c0454c, 0xd3c52100, 0x21004c4c, 0x0000f994, 0xfefef7ef, 0x2000494b, 
+    0x461a2301, 0x46017008, 0x0000f994, 0xfd82f7ef, 0x2203484c, 0xf00c2138, 0x2800fe8a, 0x4c42d032, 
+    0x22022303, 0x210c34c4, 0xf00c4620, 0xf44ffe72, 0xe0000100, 0x4d3ce06a, 0x35569102, 0x210ae006, 
+    0xa802462a, 0xfb7df7ea, 0xd0062801, 0x46202202, 0xf00c210c, 0x2800fe6c, 0x4833d1f1, 0xf00c30cc, 
+    0x4c2ffe3b, 0x48308160, 0xf00c30ca, 0x81a0fe35, 0x30d4482d, 0xfe30f00c, 0x482b81e0, 0xf00c30d2, 
+    0x8220fe2b, 0x210be08e, 0xa802464a, 0xfb59f7ea, 0xd0062801, 0x46402202, 0xf00c210c, 0x2800fe48, 
+    0x4821d1f1, 0xf00c30cc, 0x8078fe17, 0x30ca481e, 0xfe12f00c, 0x481c80b8, 0xf00c30d4, 0x80f8fe0d, 
+    0x30d24819, 0xfe08f00c, 0x8138b200, 0x1002f9b7, 0x200af9b7, 0xd10f4291, 0x2004f9b7, 0x300cf9b7, 
+    0xd109429a, 0x2006f9b7, 0x300ef9b7, 0xd103429a, 0x2010f9b7, 0xd0034290, 0x2501697a, 0x617a1e52, 
+    0x88b98179, 0x88f981b9, 0x823881f9, 0x950017e3, 0xf9964622, 0xe0170000, 0x0004e688, 0x00041290, 
+    0x00040c0c, 0x00040290, 0xf2035126, 0x0004028e, 0x00049178, 0x00048978, 0x0002ce4c, 0x0004e340, 
+    0x00041280, 0xf38f007c, 0xff7ff7ef, 0x0200f248, 0x10510055, 0xdd152c00, 0xdd0f4294, 0x220048c9, 
+    0xf00c213f, 0x281afde4, 0xf240d202, 0xe00111ff, 0x31fef240, 0xdc0f42ac, 0xe00d0849, 0xdd08428c, 
+    0xe0092103, 0x42904260, 0x42a8dd05, 0x2105dd01, 0x2102e002, 0x2100e000, 0x0000f996, 0x461a2301, 
+    0xfcb8f7ef, 0x48b82208, 0xf38bfa1f, 0xf00c0151, 0xe66bfdb0, 0x4ff0e92d, 0xf44fb089, 0x90023000, 
+    0x48b21084, 0xfd88f00c, 0xf00049b1, 0x78090003, 0xd203290a, 0x780949af, 0xd17c2900, 0x0100f241, 
+    0x2801b128, 0x2802d005, 0x2803d007, 0x9102d006, 0xf244e004, 0x90020000, 0x9402e000, 0x98022200, 
+    0xeb002101, 0x104070d0, 0xf04f9007, 0xf00c4071, 0x2801fd77, 0x48a0d177, 0x0b0af04f, 0x28017800, 
+    0x2400d005, 0x7800489d, 0xd1752800, 0xf8dfe06f, 0x2500a270, 0x21004895, 0xeb003014, 0xf00c1045, 
+    0x4998fd4e, 0x23012000, 0xf8212200, 0x48960015, 0x1015f830, 0xf8201c49, 0x49941015, 0xe9cd4618, 
+    0xb2691a00, 0xf808f7e9, 0xe0412400, 0x23c94890, 0xf9304a90, 0x488d1014, 0x0011f830, 0x0014f822, 
+    0xf83a3214, 0xf8226011, 0xfb1b6014, 0xfb11f203, 0xfb10f102, 0xfb16f200, 0xfb812206, 0x04c12302, 
+    0x46172000, 0xf00b4698, 0x4b82ee9c, 0xeb050c02, 0x33280985, 0x4201ea42, 0x1009eb03, 0x14094643, 
+    0x00c4eb00, 0x2100e9c0, 0x463a04f1, 0xf00b2000, 0x0c02ee88, 0xe016e000, 0xea424b77, 0x14094201, 
+    0x1009eb03, 0x00c4eb00, 0xb2e41c64, 0x2100e9c0, 0xd3bb455c, 0xb2ed1c6d, 0xd39b2d04, 0x20004966, 
+    0x496e7008, 0xb0097008, 0x8ff0e8bd, 0x486ce004, 0x0000f990, 0xd0784284, 0x7800486a, 0xd0f22801, 
+    0x78004869, 0xd0ee2801, 0x78004868, 0xd0ea2801, 0x23014e5b, 0xb2614d5d, 0x468a2200, 0xe9cd4618, 
+    0xf7e85600, 0x4d5bff99, 0xeb042000, 0x46010384, 0x46813528, 0x1503eb05, 0x4d579508, 0x46804602, 
+    0x1303eb05, 0xe02a9301, 0x4f4d9b08, 0x03c0eb03, 0x5600e9d3, 0xf9334b4e, 0x93003010, 0x3013f937, 
+    0xce03fba5, 0xfb0617df, 0xfb05e303, 0xeb1c3307, 0x4f460909, 0x9b014159, 0x03c0eb03, 0x5600e9d3, 
+    0xf9379b00, 0xfba53013, 0x17dfce03, 0xe303fb06, 0x3307fb05, 0x0808eb1c, 0x1c40415a, 0x4558b2c0, 
+    0xebb9d3d2, 0xeb610008, 0xf06f0102, 0x22004300, 0x418a1a1b, 0xf06fda02, 0xe0054000, 0x1a824a3c, 
+    0x31fff171, 0x483ada00, 0x2800ad03, 0xf8454601, 0xda000024, 0x9a024249, 0xdd0d4291, 0xda052800, 
+    0xf04f482e, 0x700101ff, 0xe034e014, 0x482bdd2e, 0x0101f04f, 0xe01b7001, 0xf9924a28, 0x00491000, 
+    0x2800d022, 0xda004601, 0x9b074249, 0xdd1b4299, 0xda0c2800, 0xf830481b, 0xf1a11014, 0xf8200102, 
+    0xf06f1014, 0x46500101, 0xfd38f7ef, 0xdd0de00e, 0x0102f04f, 0xf7ef4650, 0x4812fd31, 0x1014f830, 
+    0xf8201c89, 0xe0011014, 0x70102000, 0xf8554919, 0xf8410024, 0x1c640024, 0x2c04b2e4, 0xaed2f4ff, 
+    0x0000e741, 0xf2034202, 0xf2035126, 0xf203086e, 0x0004055e, 0x000402e2, 0x0004028f, 0x0004055c, 
+    0x00049178, 0x00040292, 0x0004029a, 0x00048978, 0x0002ce4c, 0x0004e3e0, 0x0004e548, 0x00040c0c, 
+    0x00040290, 0x000402cd, 0x00040f47, 0x00040f48, 0x80000001, 0x00041280, 0x41f0e92d, 0x460e2400, 
+    0x46252809, 0xe8dfd215, 0x0705f000, 0x140c0a15, 0x0012100e, 0xe00d2409, 0x25012408, 0x2401e00a, 
+    0x2404e008, 0x2402e006, 0x2405e004, 0x2406e002, 0x2403e000, 0xb12e4f0e, 0xf00c4638, 0xf000fbdd, 
+    0xe000000f, 0x02314620, 0x1104ea41, 0x46384301, 0xf00cb289, 0x462bfbd4, 0xe8bd4805, 0x220041f0, 
+    0x30402101, 0xbbe5f00c, 0xe7c52100, 0xe7c32101, 0xf2030460, 0x41f0e92d, 0x2a014e19, 0x0880f44f, 
+    0x46074614, 0xd001b24d, 0xd1112c02, 0x46402170, 0xfff1f7e2, 0xf7ec4638, 0x2000fb73, 0xf898f7ec, 
+    0x46292001, 0x70302200, 0xf899f7ec, 0xd0032c02, 0x2c02b13c, 0xe00fd005, 0xf44f2100, 0xf7ea2080, 
+    0x2200f83b, 0x46104629, 0xf889f7ec, 0x70302000, 0x46402171, 0xfff7f7e2, 0xe8bd2001, 0x000081f0, 
+    0x00040dec, 0x4cf9b510, 0xf00c4620, 0xf64efb85, 0x400861ee, 0x1111f241, 0x46204401, 0x4010e8bd, 
+    0xbb7df00c, 0x4cf1b510, 0xf00c4620, 0xf242fb75, 0x43012122, 0xf00c4620, 0x4620fb72, 0xfb6cf00c, 
+    0x51ddf64d, 0x46204001, 0x4010e8bd, 0xbb67f00c, 0xf241b570, 0x46050400, 0x4603220c, 0x462148e4, 
+    0xfb77f00c, 0x220c48e3, 0x4621462b, 0xfb71f00c, 0x220c48e1, 0x4621462b, 0xfb6bf00c, 0x4621462b, 
+    0x4070e8bd, 0x220c48dd, 0xbb63f00c, 0x47f0e92d, 0xf6404cd7, 0x220b0600, 0x46074689, 0x46314603, 
+    0xf00c4620, 0x4dd3fb56, 0x463b220b, 0x46284631, 0xfb4ff00c, 0x8340f8df, 0x463b220b, 0x46404631, 
+    0xfb47f00c, 0x4ecd4631, 0x463b220b, 0xf00c4630, 0xf240fb40, 0x464b4700, 0x4639220a, 0xf00c4620, 
+    0x220afb38, 0x4639464b, 0xf00c4628, 0x220afb32, 0x4639464b, 0xf00c4640, 0x464bfb2c, 0x46304639, 
+    0x47f0e8bd, 0xf00c220a, 0xe92dbb24, 0xf8df47f0, 0x461d82e0, 0x460c2205, 0x21e09e08, 0x46034607, 
+    0xf00c4640, 0xf8dffb16, 0x220592cc, 0x463b21e0, 0xf00c4648, 0xf8dffb0e, 0x2205a2c0, 0x463b21e0, 
+    0xf00c4650, 0x463bfb06, 0x22054fac, 0x463821e0, 0xfafff00c, 0xd11d2c03, 0xd0102d01, 0x281bb2f0, 
+    0x2304d00d, 0x22054650, 0xf00c21e0, 0x2304faf2, 0x22054638, 0xe8bd21e0, 0xf00c47f0, 0x2304baea, 
+    0x22054640, 0xf00c21e0, 0x2304fae4, 0x22054648, 0xe7f021e0, 0x87f0e8bd, 0x46032200, 0x21074898, 
+    0xbad7f00c, 0x4d96b570, 0x0400f248, 0x46212300, 0x4628220f, 0xfacdf00c, 0x46212301, 0x4628220f, 
+    0xfac7f00c, 0x46284621, 0x4070e8bd, 0x220f2300, 0xbabff00c, 0x2801b570, 0x460d4604, 0xb92cd000, 
+    0x22044888, 0x2130460b, 0xfab3f00c, 0xd0012c02, 0xd1082c00, 0x462b4883, 0x4070e8bd, 0x21302204, 
+    0xf00c3080, 0xbd70baa6, 0x41f0e92d, 0x46150c17, 0x460c2801, 0xd0004606, 0x2c01b9ce, 0xb94cd000, 
+    0x46394878, 0xf00c1d00, 0x4876fa7a, 0x1d80b2a9, 0xfa75f00c, 0xd0002c02, 0x4872b94c, 0x30084639, 
+    0xfa6df00c, 0xb2a9486f, 0xf00c300a, 0x2e02fa68, 0x2e00d001, 0x2c01d11c, 0xb94cd000, 0x46394869, 
+    0xf00c3084, 0x4867fa5c, 0x3086b2a9, 0xfa57f00c, 0xd0012c02, 0xd10b2c00, 0x46394862, 0xf00c3088, 
+    0xb2a9fa4e, 0xe8bd485f, 0x308a41f0, 0xba47f00c, 0x81f0e8bd, 0x21004b5c, 0xb130b510, 0xd0072801, 
+    0xd00d2802, 0xd1092803, 0x2200e00d, 0xe0012103, 0x210c2202, 0xf00c4618, 0xb241fa5a, 0xbd10b2c8, 
+    0x21302204, 0x2206e7f6, 0xe7f321c0, 0x4d48b570, 0x1cad4604, 0xf00c4628, 0x4e4cfa1f, 0x0000f364, 
+    0x46304601, 0xfa1bf00c, 0xd1092c00, 0xf00c4628, 0xf020fa13, 0x46300102, 0x4070e8bd, 0xba0ff00c, 
+    0xb570bd70, 0x1ca44c3a, 0xf00c4620, 0x4d3ffa05, 0x0102f040, 0xf00c4628, 0x4620fa02, 0xf9fcf00c, 
+    0x0102f020, 0xe8bd4628, 0xf00c4070, 0xb57fb9f8, 0x46144b37, 0xcb4e460d, 0x004ee88d, 0xffaaf7ff, 
+    0x0020f85d, 0xeb00b2a1, 0xf00c0045, 0xbd7ff9e8, 0x4604b510, 0x1c804826, 0xf9def00c, 0x7100f240, 
+    0x2104ea01, 0x60e2f420, 0xe8bd4308, 0xf0404010, 0x48260110, 0xb9d3f00c, 0x2801b510, 0xd0004604, 
+    0x2301b92c, 0x2200481f, 0xf00c4619, 0x2c02f9e2, 0x2c00d001, 0x481bd108, 0x22002301, 0xe8bd4619, 
+    0x30804010, 0xb9d5f00c, 0xe92dbd10, 0x4c1641f0, 0xb283461d, 0x22004616, 0x2103460f, 0xf00c4620, 
+    0xb2bbf9c8, 0x22024620, 0xf00c210c, 0xb2b3f9c2, 0x22044620, 0xf00c2130, 0xb2abf9bc, 0xe8bd4620, 
+    0x220641f0, 0xf00c21c0, 0x0000b9b4, 0xf23c8000, 0xf2033040, 0xf2033240, 0xf2033440, 0xf2033640, 
+    0xf2033a00, 0xf2033b00, 0xf2035026, 0xf2033842, 0x0002cf1c, 0xf641b570, 0x46040500, 0x480cb283, 
+    0x4629220b, 0xf995f00c, 0x480ab2a3, 0x4629220b, 0xf98ff00c, 0x4808b2a3, 0x4629220b, 0xf989f00c, 
+    0x4629b2a3, 0x4070e8bd, 0x220b4804, 0xb981f00c, 0xf2033042, 0xf2033242, 0xf2033442, 0xf2033642, 
+    0x41f0e92d, 0xf7f82400, 0x4867fe1d, 0xf8df4f67, 0x4e69c1a4, 0x48667801, 0x460d683a, 0x3000f990, 
+    0xd0062b03, 0xe194f8df, 0xd00e2b05, 0xd0202b04, 0x4863e02b, 0x28126800, 0xf64dd302, 0xe00160f7, 
+    0x60eaf64e, 0x14124342, 0x7830e01f, 0xd0092801, 0xd0072802, 0x4000f89c, 0xd0034304, 0xd0012803, 
+    0xe0122401, 0x0000f89e, 0x2404b108, 0x2403e00d, 0x7830e00b, 0xd02e2801, 0xd02c2802, 0x4000f89c, 
+    0xd0284304, 0xd0262803, 0xf6432402, 0x428270ff, 0x1e42db00, 0xe12cf8df, 0xeb0e2000, 0xf1c01404, 
+    0xf9340e07, 0x4596e01e, 0x1c40dc03, 0x2808b200, 0x2807dbf5, 0x4a43dc05, 0x0007f1c0, 0xf8123290, 
+    0x2b045010, 0xd00d4a40, 0xd02c2b05, 0xd2602d0c, 0xb3307810, 0xf89ee01f, 0xb1080000, 0xe7d42406, 
+    0xe7d22405, 0x28017830, 0x2802d008, 0xf89cd006, 0x43033000, 0x2803d002, 0xe007d051, 0xd2012d2d, 
+    0xe0202401, 0xe01e2400, 0xe01c2402, 0xd2462d0c, 0x28007810, 0x290fd0f8, 0x2407d238, 0x2406e017, 
+    0x2405e015, 0x7830e00f, 0xd0052801, 0xd0032802, 0x3000f89c, 0xd1e94318, 0xd2012d23, 0xe0022404, 
+    0xd21e2d2d, 0x48212403, 0x28017800, 0x2000d0e7, 0xda002c00, 0x481e4604, 0xf8b1f00c, 0xb2818838, 
+    0x3020481b, 0xf8abf00c, 0x03207831, 0x2001eb00, 0xb2814428, 0x30264816, 0xf8a1f00c, 0xe8bd4620, 
+    0x2d4181f0, 0x2d55d3c0, 0xe7b9d2bc, 0xd2c82919, 0x2d23e7c5, 0x2d2dd3c5, 0x2d37d3d0, 0x2d41d3d2, 
+    0x2d4bd3b2, 0xe7abd2ae, 0x0004055e, 0x000405f4, 0x0004028a, 0x0004053e, 0x000405d9, 0x0004055c, 
+    0x00040238, 0x00040e2c, 0x000402f4, 0x000402f5, 0xf2035182, 0xb50848fe, 0x90008800, 0x780348fd, 
+    0xf99048fd, 0x48fd2000, 0x20007801, 0xfd5df7ff, 0x4008e8bd, 0xf7ed2004, 0xb57cb982, 0xf7ef2001, 
+    0x4cf7fc5c, 0x4bf82204, 0x48f6b241, 0x70212903, 0x2905d002, 0xe024d018, 0x29948819, 0x2984d010, 
+    0x29a4d00e, 0x29b4d00c, 0x2998d00a, 0x29a8d013, 0x2988d011, 0x29b8d00f, 0x29c8d00d, 0xe010d00b, 
+    0x70212105, 0xe0082307, 0x29988819, 0x2988d003, 0x29a8d001, 0x2306d1ef, 0x22027022, 0xf00c213c, 
+    0x7820f848, 0xfcb8f7e9, 0x700849e0, 0xf7ee2008, 0x7820fb8b, 0xffdef7ec, 0xf7ed2005, 0x2000fbbb, 
+    0xfdeef7ed, 0x250049d5, 0x23019500, 0x461a7820, 0xf7e57809, 0x2101fc62, 0xf7ed4608, 0xf640f851, 
+    0xf6474100, 0x23177203, 0x00889500, 0xfffcf7ec, 0x210248cf, 0xf803f00c, 0xf64048ce, 0xf00b7131, 
+    0x2001fffe, 0x46022300, 0x0500e9cd, 0xf7ea4619, 0x49c9fdd5, 0x60082019, 0xe92dbd7c, 0x4fc75ffc, 
+    0x8e804606, 0xb318f8df, 0x8318f8df, 0x683b28e2, 0xdc05d075, 0x289ab170, 0x289bd018, 0xe020d170, 
+    0xd00628e3, 0x7f90f5b0, 0xf5a0d06b, 0x38217080, 0xe1afd166, 0xf04f49ba, 0xf8db32ff, 0x1d090000, 
+    0xfc9cf007, 0xd1081d01, 0xe0aa209a, 0x220049b4, 0x0000f8db, 0xf0071d09, 0x1d41fc91, 0x2801d02d, 
+    0x48afd1e8, 0xf9b01d00, 0x296e1000, 0xf04fd1e2, 0x46815580, 0x4220f04f, 0xf7e24628, 0xf898fc3a, 
+    0xf04f1000, 0x46445290, 0xf7e24628, 0x7820fc32, 0xd0772800, 0xf04f2500, 0x24010a05, 0xd00e2801, 
+    0xd0462802, 0xd0492803, 0xd07d2804, 0xd06b2805, 0xd06a2806, 0xd0692807, 0x209be173, 0xf7fce071, 
+    0xf7fffbfa, 0xf7ffff2a, 0x4892ff15, 0x220f2300, 0x0100f248, 0xf00b301a, 0x2201ff9c, 0x46112300, 
+    0x4500e9cd, 0xf7ea4610, 0x488ffd59, 0xff74f00b, 0x8008498e, 0x488e0701, 0x8004d004, 0xe00ee003, 
+    0xe044e050, 0x22008005, 0xf8a94985, 0x6838a000, 0xf0071d09, 0x1d01fc04, 0x20e2d107, 0x4980e041, 
+    0x46182200, 0xf0071d09, 0x1d40fbfa, 0x20e3d179, 0xf7ffe037, 0xf7fffef2, 0xe11ffedd, 0xfeedf7ff, 
+    0x23004d7c, 0xf640220b, 0x46280100, 0xff61f00b, 0x46282301, 0x0319220c, 0xff5bf00b, 0xf640486d, 
+    0xf00b1137, 0x4874ff3c, 0x496d2200, 0x70041d09, 0xa000f8a9, 0xf0076838, 0x1d01fbd2, 0xf240d10d, 
+    0xe00e1020, 0xe00fe104, 0xe0eee06f, 0x4964e0ff, 0x46182200, 0xf0071d09, 0x1d40fbc2, 0xf240d1c6, 
+    0x86b01021, 0x9ffce8bd, 0xfeb7f7ff, 0xfea2f7ff, 0xf9904853, 0x28050000, 0x2804d034, 0x2000d034, 
+    0x7809495e, 0xd0312901, 0xd0352902, 0xd0392904, 0xd03d2905, 0xd0412906, 0x462c2500, 0xfc42f7ff, 
+    0x88004843, 0x48439000, 0x48437803, 0x2000f990, 0x78014842, 0xf7ff2003, 0x2004fbe8, 0xfc2cf7ff, 
+    0x46082100, 0xfc46f7ff, 0x462a2101, 0xf7ff2000, 0x2102fc5b, 0x20004622, 0xfc56f7ff, 0xf7ff2000, 
+    0xe0b7fd0b, 0xe7cb2001, 0xe7c92002, 0x7580f241, 0x2480f641, 0xe01640c5, 0x2580f243, 0x3480f243, 
+    0xe01040c5, 0x1580f645, 0x2480f645, 0xe00a40c5, 0x2580f648, 0x4480f648, 0xe00440c5, 0x6580f24c, 
+    0x0480f64c, 0x40c440c5, 0xf7ffe7b8, 0xf7fffe56, 0xf7fffe41, 0x2100fca6, 0x46082240, 0xfcb7f7ff, 
+    0x2101220d, 0xf7ff2000, 0x2205fcb2, 0x20002102, 0xfcadf7ff, 0x21002240, 0xf7ff2001, 0x2101fca8, 
+    0x4608220d, 0xfca3f7ff, 0x21022205, 0xf7ff2001, 0x2240fc9e, 0x20022100, 0xfc99f7ff, 0x2101220d, 
+    0xf7ff2002, 0x2102fc94, 0x46082205, 0xfc8ff7ff, 0x21002240, 0xf7ff2003, 0x220dfc8a, 0x20032101, 
+    0xfc85f7ff, 0x21022205, 0xf7ff2003, 0xe027fc80, 0x000402b8, 0x00040310, 0x00040234, 0x000405d9, 
+    0x0004028a, 0xf2020000, 0x00040558, 0x0004028b, 0xf23c8304, 0xf203502a, 0x00040238, 0x00040734, 
+    0x00040ecc, 0x0004027c, 0xf2035136, 0x000402ba, 0x000402bc, 0xf38fffd2, 0x00040290, 0x00040580, 
+    0xf7ff2000, 0x2003fc23, 0xfc62f7ff, 0x22002301, 0xe9cd4619, 0x46185400, 0xfc20f7ea, 0x22002301, 
+    0x21024618, 0x5400e9cd, 0xf7ffe00e, 0xf7fffdd6, 0x4838fdc1, 0x7131f640, 0xfe31f00b, 0x22012300, 
+    0xe9cd4618, 0x46114500, 0xfc08f7ea, 0x2001e002, 0xfc97f7ea, 0x0000f898, 0xf43f2807, 0x2800ae4b, 
+    0xf7ffd0fb, 0xe645fa9f, 0x21012200, 0xf2afb510, 0xf00730b5, 0x2108f8ff, 0xf0072002, 0x4926fa5d, 
+    0xbd106008, 0x2000b57c, 0xff02f7e9, 0x20062100, 0xf980f7fe, 0x25004821, 0x46294c21, 0x78029500, 
+    0x78234628, 0xf8ccf7fe, 0xf7ee2004, 0x481dff5a, 0x90008800, 0x7821481c, 0x481c7803, 0x2000f990, 
+    0xf7ff2000, 0x2000fae2, 0xfbc0f7ea, 0x23002001, 0xe9cd4602, 0x46010500, 0xf7ea4618, 0x4814fbbf, 
+    0xf00b2100, 0x4c13fddc, 0x0000f241, 0xf7e97821, 0xf242fa73, 0x46290550, 0x463006ee, 0xfa17f7e2, 
+    0x0bf07821, 0xfa68f7e9, 0x46304629, 0x407ce8bd, 0xba0df7e2, 0xf203502a, 0x00040ecc, 0x0004028a, 
+    0x000405d9, 0x000402b8, 0x00040310, 0x00040234, 0xf2034220, 0x0004028b, 0x43f8e92d, 0x48ff4606, 
+    0x600149fd, 0xf00b48fe, 0x2000fda4, 0xfea0f7e9, 0xf9a2f7e8, 0x83ecf8df, 0x2400f240, 0xf8984620, 
+    0xf7e81000, 0x48f8f9a3, 0x71fff64f, 0xfd91f00b, 0x20022100, 0xf9c8f7e9, 0x230048f4, 0x21022201, 
+    0xfda7f00b, 0x93c8f8df, 0x22092300, 0x46484621, 0xfd9ff00b, 0x230148ee, 0x03d9220f, 0xf00b3012, 
+    0x4fe6fd98, 0x1d3f2500, 0xb2e12400, 0x0014f837, 0xb2024240, 0xf7ffb2e8, 0x1c64fb7a, 0xdbf42c10, 
+    0x2d041c6d, 0x2000dbf0, 0xfb40f7ff, 0xf7ff2003, 0x48dffb7f, 0x21012300, 0x30a0461a, 0xfd79f00b, 
+    0x46082100, 0xfb0ef7ea, 0x680048da, 0x38087f80, 0xf7ecb2c0, 0x2300fb3a, 0x22074648, 0xf00b2180, 
+    0x2300fd68, 0x210148d4, 0xf00b461a, 0x2000fd62, 0xf8989000, 0x22033000, 0x20084601, 0xf810f7fe, 
+    0x23004dce, 0x21e02205, 0xf00b4628, 0x4cccfd52, 0x22052300, 0x462021e0, 0xfd4bf00b, 0x8324f8df, 
+    0x22052300, 0x464021e0, 0xfd43f00b, 0x9318f8df, 0x22052300, 0x464821e0, 0xfd3bf00b, 0xf7ea2001, 
+    0x2100faf5, 0x2080f44f, 0xf9b6f7e9, 0x20012100, 0xf890f7fb, 0xf2402202, 0x210710c3, 0xf94af7ff, 
+    0xf7eb48ba, 0x2000fa56, 0xf93ef7ff, 0x23022100, 0x22084608, 0xfe6bf7e9, 0x2100230c, 0x4608461a, 
+    0xfea0f7e9, 0x461a2300, 0x46184619, 0xfe81f7e9, 0x20002101, 0xfe49f7e9, 0x22112300, 0x3100f44f, 
+    0x4071f04f, 0xfceef00b, 0xf7e92001, 0xf44ffde1, 0x21001700, 0xf7e94638, 0x230cf97f, 0x461a2100, 
+    0xf7e94608, 0x2100fe7f, 0xf7e94638, 0x230df975, 0x461a2100, 0xf7e94608, 0x2100fe75, 0xf7e94638, 
+    0x04f0f96b, 0x10c02205, 0x0f4321e0, 0xf00b4628, 0x04b0fce0, 0x10c02205, 0x0f4321e0, 0xf00b4620, 
+    0x0470fcd8, 0x10c02205, 0x0f4321e0, 0xf00b4640, 0x0430fcd0, 0x10c02205, 0x0f4321e0, 0xf00b4648, 
+    0xe8bdfcc8, 0x200243f8, 0xb8eff7e9, 0x47f0e92d, 0x4605b088, 0xae042000, 0xf8464601, 0x1c401020, 
+    0xdbfa2804, 0x91e8f8df, 0xf8df2400, 0xf248a1e4, 0xf1090800, 0x466f0918, 0x0a06f10a, 0x21004640, 
+    0xf92af7e9, 0x466b2101, 0x4650464a, 0xfbc1f00c, 0xf8562000, 0xf8571020, 0x44112020, 0x1020f846, 
+    0x28041c40, 0x1c64dbf5, 0xdbe72c40, 0xf8562000, 0x31201020, 0xf8451189, 0x1c401020, 0xdbf62804, 
+    0xf105b008, 0xe8bd0010, 0x460387f0, 0xb5102000, 0xe005188c, 0x2011f833, 0xfb121c49, 0x4410f202, 
+    0xdcf7428c, 0xe92dbd10, 0xf04f4ff8, 0x46044571, 0xf00b4628, 0x2300fc4b, 0x21014683, 0x4628461a, 
+    0xfc50f00b, 0x465046aa, 0xfc40f00b, 0xd1fa07c0, 0x25004857, 0xf8d046a9, 0x22008000, 0x4610b269, 
+    0x460e4643, 0x9000f8cd, 0xff2ef7e7, 0x46be2700, 0x463a46bc, 0x0012f938, 0xdb012800, 0xe0004603, 
+    0xb2194243, 0xdd0242b9, 0x4686460f, 0x1c524694, 0x2a80b212, 0x2280dbee, 0x21004640, 0xec00e9c4, 
+    0xffb3f7ff, 0x60a02280, 0x46404611, 0xffadf7ff, 0x60e02280, 0x00514640, 0xffa7f7ff, 0xf2402280, 
+    0x61201180, 0xf7ff4640, 0x2280ffa0, 0x46406160, 0xf7ff0091, 0x2280ff9a, 0x2180f240, 0x464061a0, 
+    0xff93f7ff, 0xf2402280, 0x61e03100, 0xf7ff4640, 0x2280ff8c, 0x3180f240, 0x46406220, 0xff85f7ff, 
+    0x62602701, 0x46433428, 0x46312000, 0xf8cdb27a, 0xf7e79000, 0x2280fed9, 0x21004640, 0xff75f7ff, 
+    0x60202280, 0x46404611, 0xff6ff7ff, 0x60601c7f, 0x3408b23f, 0xdbe62f04, 0xb22d1c6d, 0xdb8c2d04, 
+    0x46504659, 0xfbc5f00b, 0xe8bd4620, 0xe92d8ff8, 0xf5ad4ff0, 0xf7ff7d0b, 0x2000fe0f, 0x4601ad40, 
+    0x1020f845, 0x28401c40, 0x2000dbfa, 0x417ff06f, 0x4690aa86, 0x0000e01e, 0x00046978, 0x00040ed8, 
+    0xf0003088, 0x000405d9, 0xf1000048, 0xf23c8310, 0xf2030400, 0x000405f8, 0xf2031012, 0xf2033040, 
+    0xf2033240, 0xf2033440, 0xf2033640, 0x00040590, 0x00040230, 0x1020f842, 0x28041c40, 0x2400dbd9, 
+    0xf50d46eb, 0xf2407a00, 0x26004700, 0x0900f1c7, 0xd0642c00, 0xb2704649, 0xfc70f7ee, 0x2e041c76, 
+    0x2100dbf6, 0x0000f44f, 0xf816f7e9, 0xf7ff4668, 0xa880ff1a, 0xfecaf7ff, 0x46dc2000, 0xeb0c0101, 
+    0xeb050681, 0x68b30281, 0x42bb6897, 0xf85cdd06, 0xf8457021, 0x68767021, 0x6301e9c2, 0x188e2203, 
+    0x3026f85c, 0x7026f855, 0xdd0142bb, 0x3026f845, 0x2a0f1c52, 0xf858ddf3, 0x46423020, 0x1020f85a, 
+    0xdd01428b, 0x1020f842, 0x28041c40, 0x1c64dbd6, 0xdbb82c02, 0x680448fe, 0xf8522000, 0x1c401020, 
+    0xc4022804, 0xa884dbf9, 0xf883f7eb, 0xa9842000, 0x2010f931, 0x28041c40, 0xdbf9c404, 0xf8552000, 
+    0xf8441020, 0x1c401020, 0xdbf82840, 0xf44f2100, 0xf7e81080, 0xf50dffc1, 0xe8bd7d0b, 0x46398ff0, 
+    0xb510e799, 0x20004604, 0xe0074602, 0x3012f934, 0xda012b00, 0xe0001ac0, 0x1c524418, 0xdbf5428a, 
+    0xb5ffbd10, 0x466d2300, 0xf845461c, 0x1c5b4023, 0xdbfa2b04, 0xe0162300, 0x6013f930, 0x44349c00, 
+    0xeb009400, 0x9e010443, 0xf9b41d1b, 0x443e7002, 0xf9b49601, 0x9e027004, 0x9602443e, 0x4006f9b4, 
+    0x44349e03, 0x428b9403, 0x108bdbe6, 0xb2141e92, 0xf8552100, 0xeb022021, 0x41220263, 0x2021f845, 
+    0x29041c49, 0x2100dbf5, 0xf830e014, 0x9c002011, 0xf8201b12, 0xeb002011, 0x9d010241, 0x1b648854, 
+    0x88948054, 0x1b649d02, 0x88d48094, 0x1b649d03, 0x1d0980d4, 0xdbe84299, 0xe92dbdff, 0xb0934ff0, 
+    0xfd0af7ff, 0x9004200a, 0x4dba2300, 0x210148ba, 0x4400f240, 0xf00b461a, 0x2300fab5, 0x461a2101, 
+    0x4071f04f, 0xfaaef00b, 0xf7fe2000, 0x2140fedd, 0xf7e92000, 0x48aefbe7, 0x090df04f, 0x20006807, 
+    0x90094680, 0x49ad9012, 0x80c84aae, 0x80488088, 0x48ab8008, 0x780349ac, 0xf7ea48a8, 0xf44ffff9, 
+    0x21001680, 0xf7e84630, 0x2101ff27, 0x46082304, 0xf7ed2200, 0x2100f9f1, 0xf7e84630, 0x12b1ff1d, 
+    0x0b01f04f, 0x23009400, 0x46281e5a, 0xb101e9cd, 0xf8cd2103, 0xf7fdb00c, 0x2600ffd1, 0x0a38f10d, 
+    0xfb069a04, 0x4621f004, 0x0040eb05, 0xf7ff4684, 0x4660ff58, 0xf7ff4621, 0xf84aff44, 0x1c760026, 
+    0xdbed2e04, 0x4100f240, 0x23009400, 0x1e5a4628, 0xb101e9cd, 0xf8cd2103, 0xf7fdb00c, 0x2600ffaf, 
+    0x46219a04, 0xf004fb06, 0x0040eb05, 0xf7ff4684, 0x4660ff38, 0xf7ff4621, 0xf85aff24, 0x18812026, 
+    0x1026f84a, 0x2e041c76, 0xf240dbea, 0x94004100, 0x46282300, 0xe9cd1e5a, 0x2103b101, 0xb00cf8cd, 
+    0xff8cf7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 0x46840040, 0xff15f7ff, 0x46214660, 0xff01f7ff, 
+    0x2026f85a, 0xf84a1881, 0x1c761026, 0xdbea2e04, 0x94002001, 0x02811e82, 0xe9cd2300, 0x21030101, 
+    0x46289003, 0xff6af7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 0x46840040, 0xfef3f7ff, 0x46214660, 
+    0xfedff7ff, 0x2026f85a, 0x188146d3, 0x1026f84a, 0x2e041c76, 0x2201dbe9, 0x46112304, 0xf7ed4610, 
+    0x2100f95b, 0x1080f44f, 0xfe86f7e8, 0x48544953, 0xf8a14a54, 0xf8a19006, 0xf8a19004, 0xf8a19002, 
+    0x78039000, 0x484d4950, 0xff42f7ea, 0x23022101, 0x22084608, 0xfb3bf7e9, 0xf242220b, 0x46110600, 
+    0xf7e94630, 0x220cfc4b, 0x46114630, 0xfc46f7e9, 0x4630220d, 0xf7e94611, 0x2001fc41, 0x1e829400, 
+    0x23000281, 0x0101e9cd, 0x90032103, 0xf7fd4628, 0x2600ff15, 0x0a28f10d, 0xfb069a04, 0x4621f004, 
+    0x0040eb05, 0xf7ff4684, 0x4660fe9c, 0xf7ff4621, 0xf84afe88, 0x1c760026, 0xdbed2e04, 0x94002001, 
+    0x02811e82, 0xe9cd2300, 0x21030101, 0x46289003, 0xfef4f7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 
+    0x46840040, 0xfe7df7ff, 0x46214660, 0xfe69f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 0xdbea2e04, 
+    0x94002001, 0x02811e82, 0xe9cd2300, 0x21030101, 0x46289003, 0xfed2f7fd, 0x9a042600, 0xfb064621, 
+    0xeb05f004, 0x46840040, 0xfe5bf7ff, 0x46214660, 0xfe47f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 
+    0xdbea2e04, 0x94002001, 0x02811e82, 0xe9cd2300, 0x21030101, 0x46289003, 0xfeb0f7fd, 0x9a042600, 
+    0xfb064621, 0xeb05f004, 0x46840040, 0x0000e00e, 0x00040ed8, 0x00041978, 0xf1000030, 0x00040590, 
+    0x000405d9, 0x00040578, 0x000405a6, 0xfe29f7ff, 0x46214660, 0xfe15f7ff, 0x2026f85a, 0xf84a1881, 
+    0x1c761026, 0xdbda2e04, 0xf7ffa805, 0x2000fc7f, 0xab054651, 0xf852465a, 0x603e6020, 0x6020f851, 
+    0xf853607e, 0x1c406020, 0x370c60be, 0xdbf22804, 0x21402600, 0xf7eeb270, 0x1c76fa01, 0xdbf82e04, 
+    0x0801f108, 0x0f40f1b8, 0x9812da01, 0x2100e66b, 0x1080f44f, 0xfda0f7e8, 0xea409809, 0xea412100, 
+    0xea414100, 0x60386000, 0x2109ea49, 0x4109ea41, 0x6009ea41, 0xb0136078, 0xe92de5cf, 0x250041f0, 
+    0x4700f240, 0x21004efe, 0xf7e84638, 0x4630fd85, 0xf8e2f00b, 0x0720b204, 0x48f9d0f5, 0x1c80b2a1, 
+    0xf8ddf00b, 0x000ff004, 0xd00f2801, 0xd0112802, 0xd0132803, 0xf64f2501, 0xea0470f0, 0x46300100, 
+    0xf8cdf00b, 0xd0de2d00, 0x81f0e8bd, 0xf7ff4620, 0xe7f0fe04, 0xf7ff4620, 0xe7ecfcfa, 0xf7ff4620, 
+    0xe7e8fb0b, 0x4ff8e92d, 0xf64f48e6, 0xf8df71ff, 0x6800b398, 0x08478800, 0xf00b4658, 0x2100f8aa, 
+    0xf7e82002, 0xf7f0fce1, 0x4ee0fcba, 0x94002400, 0x21012203, 0x7833200a, 0xfb72f7fd, 0xfca7f7f0, 
+    0x20012100, 0xfc16f7fa, 0xf85ff7f7, 0x20012100, 0xfc10f7fa, 0x210048d6, 0x68052201, 0x94004608, 
+    0xf7e7462b, 0x2100fb81, 0x4628463a, 0xfc1df7ff, 0x46802201, 0x462b2000, 0x94004611, 0xfb74f7e7, 
+    0x463a2100, 0xf7ff4628, 0x2203fc10, 0x21024682, 0x2000462b, 0xf7e79400, 0x2100fb67, 0x4628463a, 
+    0xfc03f7ff, 0x46812203, 0x462b2000, 0x94004611, 0xfb5af7e7, 0x463a2100, 0xf7ff4628, 0x4cbdfbf6, 
+    0x0200f242, 0xda054590, 0xda034592, 0xda014591, 0xdb014290, 0xe0004db8, 0x46584db8, 0xf00b4629, 
+    0x2000f848, 0xf7e96025, 0xf7e7f943, 0xf7f0fc45, 0x4dabfb23, 0x35742400, 0xb2241c64, 0xfbb8f7ef, 
+    0xfc45f7f7, 0xf861f7fd, 0xf249b110, 0xe003010d, 0xddf12c05, 0x31adf640, 0xf00b4628, 0x2100f830, 
+    0xf7fa2001, 0xf7f2fba7, 0xf7f2ff64, 0xf7f2fdfe, 0xf7f2fd65, 0xf7f2fe14, 0x2000fcbf, 0xf918f7e9, 
+    0xf7fc2000, 0x499efd55, 0xf7e7b240, 0x2001fbc0, 0xfd4ef7fc, 0xb240499a, 0xf7e73120, 0x2002fbb8, 
+    0xfd46f7fc, 0xb2404996, 0xf7e73140, 0x2003fbb0, 0xfd3ef7fc, 0xb2404992, 0xf7e73160, 0xf8dffba8, 
+    0x25008240, 0xeb082400, 0x46211745, 0x0014f837, 0xb2024240, 0xf7fe4628, 0x1c64fdfa, 0x2c10b2e4, 
+    0x1c6dd3f3, 0x2d04b2ed, 0x2000d3ec, 0xfdbef7fe, 0xf7fe2003, 0x2300fdfd, 0x21014882, 0xf00a461a, 
+    0x2100fff8, 0xf7e94608, 0x4c7ffd8d, 0x0500f241, 0x78214628, 0xfc70f7e8, 0x20012100, 0xfb4af7fa, 
+    0xf7fe2004, 0x7821fc01, 0xf7e84628, 0x2001fc65, 0xf8bef7e9, 0x01e87821, 0xfc5ef7e8, 0xf7e92000, 
+    0x2002f8b7, 0xfd92f7e9, 0x23004d70, 0x210c2202, 0xf00a4628, 0x7830ffce, 0x2801b120, 0x2802d004, 
+    0xe004d002, 0xe0002005, 0xf7fe2006, 0x2301fbdf, 0x220a4628, 0x4639029f, 0xffbbf00a, 0x46387821, 
+    0xfc3af7e8, 0xf7e92001, 0x4855f893, 0x38160179, 0xff95f00a, 0x23007832, 0x20082101, 0xfdc0f7ed, 
+    0x485b2300, 0x461a2101, 0xffa3f00a, 0xfe0df7ed, 0x20014c58, 0xf7e97821, 0x4957febe, 0x70087820, 
+    0xfa38f7ea, 0xf7f92004, 0xe8bdfcdc, 0x21004ff8, 0xf7fa2001, 0xe92dbaef, 0x21005ff0, 0xf7e82002, 
+    0x4848fba3, 0x22092301, 0x38a00259, 0xff81f00a, 0xf7e92000, 0xf7e7f85d, 0x4842fb5f, 0x0a00f248, 
+    0x46512301, 0x388e220f, 0xff73f00a, 0xf7e92001, 0x483cfd2d, 0x38402100, 0xff51f00a, 0x23014839, 
+    0x21802207, 0xf00a38a0, 0x4c37ff64, 0x4500f240, 0x78214628, 0xfbe0f7e8, 0x23014e34, 0x3672220f, 
+    0x463003d9, 0xff55f00a, 0x46302380, 0x1e692200, 0xff4ff00a, 0x22002306, 0x1cb021ff, 0xff49f00a, 
+    0x8080f8df, 0x217f2200, 0x0000f8d8, 0x304af8b0, 0xf00a1d30, 0xf1a6ff3e, 0x01690b02, 0x4658465e, 
+    0xff1df00a, 0x0180f248, 0xf00a4630, 0x7821ff18, 0xf7e84628, 0xf44ffbb1, 0xf2400900, 0x464f11f4, 
+    0xf7e14648, 0x491dfb48, 0xf7e14638, 0x4817fb33, 0xff02f00a, 0x46384601, 0xfb2cf7e1, 0x30804813, 
+    0xfefaf00a, 0x46384601, 0xfb24f7e1, 0x46384914, 0xfb20f7e1, 0x3080480d, 0xfeeef00a, 0xe0214601, 
+    0xf2035136, 0x000405f8, 0xf1000048, 0x000405d9, 0x00040230, 0x000402f0, 0x8421b7ed, 0x84217bde, 
+    0x000412c8, 0xf20304a0, 0x0004028b, 0xf2035022, 0xf2036104, 0x0004028a, 0x00040244, 0x90010000, 
+    0xdcba01f5, 0x307448aa, 0xfec9f00a, 0x46292300, 0x4630220a, 0xfeddf00a, 0x46292301, 0x4630220a, 
+    0xfed7f00a, 0x46292300, 0x4630220a, 0xfed1f00a, 0x220d48a0, 0x0100f246, 0x0000f990, 0x4630b283, 
+    0xfec7f00a, 0x46302300, 0x21202205, 0xfec1f00a, 0x46302301, 0x21202205, 0xfebbf00a, 0x46572600, 
+    0x220f4893, 0x38724639, 0xfec1f00a, 0x1c76b918, 0x42beb236, 0xf7fcdbf4, 0x4682fc41, 0x11f4f240, 
+    0x4648464e, 0xfac7f7e1, 0x4630498b, 0xfab2f7e1, 0x38724887, 0xfe80f00a, 0x46304601, 0xfaaaf7e1, 
+    0x46304651, 0xfaa6f7e1, 0x46304984, 0xfaa2f7e1, 0x0000f8d8, 0x8f412201, 0x44088f80, 0x2100b200, 
+    0xfcc3f7e9, 0xf7ea2074, 0x2301fe33, 0x220f4639, 0xf00a4658, 0x4e7afe7e, 0x220b2300, 0x0100f640, 
+    0xf00a4630, 0x2300fe76, 0x220a4629, 0xf00a4630, 0x2300fe70, 0x2100f240, 0x46302209, 0xfe69f00a, 
+    0x46302208, 0x01512300, 0xfe63f00a, 0x46302303, 0x21c02206, 0xfe5df00a, 0xf6474869, 0x23007600, 
+    0x22084631, 0xf00a1c80, 0xf8dffe54, 0x23008194, 0x461a217f, 0x0804f108, 0xf00a4640, 0x2300fe4a, 
+    0x22084631, 0xf00a4640, 0x2002fe44, 0xfbfef7e9, 0x46082100, 0xfbc4f7e9, 0x78304e5a, 0x2801b120, 
+    0x2802d004, 0xe004d002, 0xe0002005, 0xf7fe2006, 0x4853fa4d, 0x220a2301, 0x30084629, 0xfe29f00a, 
+    0x46287821, 0xfaa8f7e8, 0x46394849, 0xf00a3816, 0x7832fe06, 0x21012300, 0xf7ed2008, 0x2300fc31, 
+    0x21014849, 0xf00a461a, 0x7821fe14, 0xf7e84628, 0xf7edfa93, 0x4c45fc7a, 0x78212001, 0xfd2bf7e9, 
+    0x78204943, 0xf7ea7008, 0x4638f8a5, 0x5ff0e8bd, 0xf04f2102, 0xf7e14210, 0xb570ba6c, 0xf7e24604, 
+    0x2000fc9f, 0xfbb2f7e9, 0x23004d35, 0xf240220a, 0x35084100, 0xf00a4628, 0x2100fdec, 0xf7e92001, 
+    0x2100fb6f, 0xf7e92001, 0x2301fb7d, 0x22064628, 0xf00a2140, 0x2301fdde, 0x22054628, 0xf00a2120, 
+    0x492cfdd8, 0x4a232019, 0x20006008, 0xf991492a, 0x54d03000, 0x3001f991, 0x54d02001, 0x3002f991, 
+    0x54d02002, 0x1003f991, 0x54502003, 0xfd3df7fc, 0xf0082000, 0x2300f923, 0x46192201, 0xf007b2e0, 
+    0x2300fd77, 0x4619461a, 0xf007b2e0, 0x481bffaf, 0x780006ea, 0x010ff000, 0x29011250, 0x2902d004, 
+    0x2903d008, 0xe00dd00c, 0xf7e12116, 0xf7fffa12, 0xe007fe12, 0xf7e12117, 0xf7fffa0c, 0xe001fcc3, 
+    0xfc8bf7ff, 0x4070e8bd, 0xf7e82002, 0x0000b9be, 0xf2035136, 0x00040570, 0x90010001, 0xdcba01f5, 
+    0xf203501a, 0x000405d9, 0xf2036104, 0x0004028a, 0x00040244, 0x00040238, 0x00040578, 0x000402ed, 
+    0x4ff8e92d, 0x46044d58, 0xb1208e80, 0xd00d287e, 0xd136287f, 0x4954e014, 0x32fff04f, 0x31086868, 
+    0xfa1cf006, 0xd1071d01, 0xe029207e, 0x2200494e, 0x31086868, 0xfa12f006, 0xd0201d41, 0xd1ea2801, 
+    0x30084849, 0x28298800, 0x4848d1e5, 0x21042202, 0xfd5df00a, 0xb2c04b46, 0x28014f46, 0xf04f4e46, 
+    0xf44f59a8, 0xf6400a00, 0xf04f0100, 0xf04f0800, 0x4618020b, 0xf00ad007, 0xb1e8fd4a, 0x207fe03c, 
+    0xe8bd86a0, 0xf00a8ff8, 0x2801fd42, 0xf996d134, 0x28030000, 0x2805d006, 0x2804d004, 0x7838d002, 
+    0xd1292801, 0xf240464a, 0x46501160, 0xf991f7e1, 0xf7e92000, 0xe01ffc2c, 0x0000f996, 0xd0062803, 
+    0xd0042805, 0xd0022804, 0x28017838, 0x464ad114, 0x1161f240, 0xf7e14650, 0x4828f97c, 0xb9107800, 
+    0xf7e92001, 0x2200fc14, 0x0300f641, 0x46104611, 0x8000f8cd, 0xfcd8f7eb, 0xfbb2f7e2, 0x22024820, 
+    0xf00a2104, 0x2201fd04, 0x481e4603, 0xf00a2102, 0xf996fcf0, 0x28030000, 0x2805d003, 0x2804d001, 
+    0xf001d101, 0x4818fa4d, 0xb1587800, 0x1c407828, 0x7028b2c0, 0xd187280a, 0xf7e12000, 0xf885ff1c, 
+    0xe7688000, 0xf7e12001, 0xe764ff16, 0x21012200, 0xf2afb510, 0xf0051053, 0x2108ff9d, 0xf0062003, 
+    0x4901f8fb, 0xbd106048, 0x00040efc, 0xf3074084, 0xf2035026, 0x0004027d, 0x00040244, 0x00040556, 
+    0xf2039026, 0xf23c801a, 0x000402e1, 0x4ff8e92d, 0x933cf8df, 0x8e804604, 0xf8d92887, 0xd0213004, 
+    0xb190dc0c, 0xd1732886, 0x220049ca, 0xf0064618, 0x1d41f955, 0x2801d014, 0xe013d107, 0x7fa2f5b0, 
+    0xf5a0d067, 0x38457080, 0x49c2d162, 0x32fff04f, 0x0004f8d9, 0xf942f006, 0xd1ea1d01, 0xe0f92086, 
+    0xe0f72087, 0xf04f4ebb, 0x17d54220, 0xf9b64628, 0xf7e11000, 0xf996f8ee, 0x46281004, 0xf7e14ab6, 
+    0xf9b6f8e8, 0xf8df0000, 0x4bb5a2d4, 0xd0172826, 0xd1da2873, 0x0002f996, 0xf999464a, 0x42881000, 
+    0xf99ad105, 0xf9921000, 0x42a95001, 0x7010d0cd, 0x1003f996, 0x1001f889, 0xf008781a, 0xe7c4f98e, 
+    0x46987818, 0xf806f008, 0xf8df48a6, 0x4da7b29c, 0x28018800, 0xf898d01e, 0x46470000, 0xffaef007, 
+    0xf6402300, 0x22087100, 0xf00a4628, 0xf996fc42, 0x29001003, 0xf04fdda9, 0x17504260, 0xf8a9f7e1, 
+    0x0003f996, 0x28044a9a, 0x2805d07d, 0xe0b7d07c, 0xe095e0a1, 0xf00a4897, 0x2301fc0f, 0x22084607, 
+    0x7100f640, 0x462846aa, 0xfc23f00a, 0x0707f007, 0xd01a2f01, 0xd01b2f02, 0x462b2503, 0x22014650, 
+    0xf00a211e, 0x4889fc16, 0x21382203, 0x301e463b, 0xfc0ff00a, 0x22024888, 0xf00a2104, 0x4f87fc18, 
+    0xf04f2801, 0xd0060a01, 0x2504e00a, 0xe7e52306, 0x23072505, 0xf008e7e2, 0xb2c0f9d7, 0xd0024285, 
+    0xa000f887, 0x7838e001, 0x2000b3e0, 0x21317038, 0xf04f1e40, 0xf7e14260, 0xf898f85c, 0x46470000, 
+    0xff4cf007, 0x23007839, 0x46282202, 0xfba0f007, 0x46287933, 0x2000f89b, 0xf0077839, 0xf7e2fdd7, 
+    0x486dfa8f, 0x21042201, 0xa000f8cd, 0x3380f44f, 0xf8c4f7e8, 0x0003f996, 0x1000f898, 0xf89bf008, 
+    0x78004867, 0xd0222801, 0x78004866, 0xd01e2801, 0xf0082000, 0x2208f9c1, 0x01514863, 0xfbc7f00a, 
+    0xe00270b0, 0xe028e00c, 0x2073e038, 0x49518030, 0xf8d92200, 0xf0060004, 0x1d01f832, 0xe014d00d, 
+    0x4260f04f, 0x17502130, 0xf813f7e1, 0x2001e7d2, 0xf9a2f008, 0xa002f886, 0xf240e7e3, 0xe0091044, 
+    0x22004944, 0xf0064618, 0x1d40f81a, 0xaf37f47f, 0x1045f240, 0xe8bd86a0, 0xf89b8ff8, 0x29031000, 
+    0x7839d10e, 0x22012300, 0xf0072002, 0x7839fb41, 0x22032300, 0xf0072004, 0xe057fd79, 0xb1617811, 
+    0x1000f99a, 0x29044b41, 0xf893d104, 0xf1bcc000, 0xd0020f00, 0xd00d2805, 0x7839e00f, 0x22022300, 
+    0xf0072003, 0x2300fb25, 0x20037839, 0xf007461a, 0xe01dfd5d, 0x28027810, 0x2904d021, 0x7818d102, 
+    0xd01c2802, 0x230078f0, 0x22017839, 0xfb10f007, 0x22007933, 0x783978f0, 0xfd48f007, 0x0003f996, 
+    0xd01f2805, 0xd01f2804, 0xd01f2802, 0xd01f2801, 0x46282303, 0x211e2201, 0xfb3bf00a, 0x78f0e6a5, 
+    0x78392300, 0xf0072202, 0x2300faf3, 0x783978f0, 0xf007461a, 0x78f0fd2b, 0xd0012805, 0xe7e82306, 
+    0xe7e62307, 0xe7e42305, 0xe7e22304, 0xe7e02302, 0xe7de2301, 0x21012200, 0xf2afb510, 0xf005302f, 
+    0x2108fde9, 0xf0052002, 0x4901ff47, 0xbd106048, 0x00040f0c, 0x0004e6d0, 0xe0000100, 0x0004028a, 
+    0x00040368, 0x00040364, 0x000405d9, 0xf23c8022, 0x00040313, 0xf23d014e, 0xf3074084, 0x0004036a, 
+    0x0004027d, 0x00040285, 0xf38f2002, 0x00040312, 0x4ff0e92d, 0xa408f8df, 0xb0852001, 0x5298f04f, 
+    0x1000f99a, 0xff55f7e0, 0xf8df48fe, 0x7800b3fc, 0x4ffeb3f0, 0x21402206, 0xf00a4638, 0xf000fae8, 
+    0x463809ff, 0x21202205, 0xfae1f00a, 0xf0004cf7, 0x220108ff, 0x2102343c, 0xf00a4620, 0xb2c6fad8, 
+    0x22004620, 0xf00a2101, 0x2208fad2, 0x4638b2c5, 0xf00a0151, 0x220cfacc, 0x48ed4604, 0x0100f241, 
+    0xfac5f00a, 0x46384384, 0x21802207, 0xf00ab2e4, 0x220bfabe, 0x48e64607, 0x0100f640, 0xfab7f00a, 
+    0x48e44387, 0xf89bb2f9, 0x78073000, 0xe000a801, 0x9704e006, 0x96004622, 0x0308e880, 0xe00b462b, 
+    0xf89b2201, 0x20001000, 0xe9cd4603, 0xe9cd1001, 0x46020203, 0x90004601, 0x0000f248, 0xfe4af7ed, 
+    0x46112200, 0xfe33f7ed, 0xf88a210f, 0xb0051000, 0x4ff0e8bd, 0xb9c1f7e3, 0x212c48c9, 0xf04fb570, 
+    0x46225498, 0x20017041, 0xfee3f7e0, 0x680048ca, 0xd01a2812, 0xd01b2813, 0xd01c2815, 0xd01d2816, 
+    0xd01e2817, 0xd01f2818, 0xd0202819, 0xd0212820, 0xd0222821, 0xd0232822, 0xd0242811, 0xd02528ff, 
+    0xd0262801, 0xd0272810, 0x2120e02b, 0xe0254622, 0x46222121, 0x2123e022, 0xe01f4622, 0x46222124, 
+    0x2133e01c, 0xe0194622, 0x46222136, 0x2137e016, 0xe0134622, 0x46222138, 0x2139e010, 0xe00d4622, 
+    0x4622213a, 0x211fe00a, 0xe0074622, 0x4622212f, 0x2130e004, 0xe0014622, 0x4622211e, 0xf7e02001, 
+    0x48a6fe98, 0xfa08f00a, 0x46012200, 0xf7e02001, 0x489efe90, 0xf00a380a, 0x4604f9ff, 0x380c489b, 
+    0xf9faf00a, 0x48994605, 0xf00a380e, 0x4622f9f5, 0xe8bd4629, 0xf7e34070, 0xe92db96d, 0x4e905ffc, 
+    0xf04f2001, 0xf9965298, 0xf7e01001, 0x488ffe72, 0xf00a380a, 0x4607f9e1, 0x380c488c, 0xf9dcf00a, 
+    0x8228f8df, 0xf1a84605, 0x4640080e, 0xf9d4f00a, 0x463a4604, 0xf7e34629, 0x220ff94d, 0x0100f248, 
+    0xf00a4640, 0xf996f9f4, 0xf0001002, 0xf8df08ff, 0xf8df9210, 0x2904a210, 0xb20cf8df, 0x2932d00e, 
+    0x2905d05b, 0x5298f04f, 0x211cd076, 0xf7e02001, 0xf1b8fe40, 0xd06e0f01, 0xe115202b, 0xf04f2001, 
+    0xf7e05298, 0x6970fe36, 0x2141f3c4, 0x61704308, 0x6f85f5b0, 0x4975d020, 0xd1ea4288, 0xd00007a8, 
+    0x49732001, 0x0240f3c5, 0xf0057008, 0xf8990001, 0x43111000, 0x1000f889, 0x3000f89a, 0x43184a6d, 
+    0x0000f88a, 0x3000f89b, 0xe9cd7812, 0x4a6a2300, 0x4a6a7813, 0xe03a7812, 0xf3c44969, 0x4a691082, 
+    0x4d692804, 0x4b6a4f69, 0x2000d009, 0x70107008, 0x70284601, 0x46187038, 0xf971f00a, 0x2001e7b9, 
+    0xf3c47008, 0x70100080, 0x0040f3c4, 0xf0047028, 0x70380001, 0x0c0105e0, 0x2001e7ed, 0x5298f04f, 
+    0xfde7f7e0, 0xf7ee4620, 0x485af99e, 0x28017800, 0x4850d19f, 0x1000f89b, 0xe9cd7800, 0x484e0100, 
+    0x1000f899, 0x484d7803, 0xf89a7802, 0xf7ee0000, 0xe78efae6, 0xe0a6e000, 0xf7e02001, 0x69b1fdca, 
+    0xf5a1483d, 0x3a974258, 0x2210d005, 0x4368f5a1, 0xd0433b6d, 0x4a48e049, 0x0103f005, 0x141ff361, 
+    0xf3c780b4, 0x70113100, 0xf3c521ff, 0xf5b2028b, 0xd0046f80, 0x7f60f415, 0x2111d000, 0x2c10e081, 
+    0x2c20d015, 0xb194d013, 0xd0152c01, 0xd0152c02, 0xd0152c03, 0xd0152c04, 0xd0152c05, 0xd0152c06, 
+    0xd0152c07, 0xd0152c08, 0xd0152c09, 0x2112e069, 0x200f6001, 0xe0197030, 0xe0622113, 0xe0602115, 
+    0xe05e2116, 0xe05c2117, 0xe05a2118, 0xe0582119, 0xe0562120, 0xe0542121, 0xe0522122, 0x1145f3c4, 
+    0xd1022902, 0x07090861, 0x6002d04a, 0x010bf3c7, 0xf00a4822, 0x4821f8e4, 0x1c802100, 0xf8dff00a, 
+    0xb2818b30, 0x1d00481d, 0xf8d9f00a, 0x220069b0, 0xf3c021ff, 0x48194307, 0xf00a1d80, 0xe718f8ea, 
+    0x00040f14, 0x000405d3, 0x00040318, 0xf38e0040, 0xf38f0008, 0x00040314, 0x00040238, 0xf38fffd0, 
+    0x000405dd, 0x000405dc, 0x000405cf, 0x00fa073e, 0x000405d6, 0x000405d0, 0x000405db, 0x000405da, 
+    0x000405c1, 0x000405c4, 0x000405c6, 0x000405c9, 0xf23c8026, 0x000405d4, 0x000402f9, 0xf203515c, 
+    0x60012101, 0x2002e7b2, 0xe8bd7070, 0xe92d9ffc, 0x4df947fc, 0x5a98f04f, 0x46522001, 0x1001f995, 
+    0xfd17f7e0, 0xf00a48f5, 0x4604f887, 0x1e8048f3, 0xf882f00a, 0x93c4f8df, 0xf1a94606, 0x46480904, 
+    0xf87af00a, 0x46314622, 0xfff4f7e2, 0xf248220f, 0x46480100, 0xf89bf00a, 0x08fff000, 0x0100f242, 
+    0x4648220d, 0xf893f00a, 0xf240b2c7, 0x220071ff, 0xf00a4648, 0x2f01f88c, 0xd108b2c0, 0xd0122809, 
+    0x280b2703, 0x2805d041, 0x2806d054, 0x2129d05e, 0x20014652, 0xfcddf7e0, 0x0f01f1b8, 0x202bd001, 
+    0xe8bd7068, 0x212787fc, 0x20014652, 0xfcd1f7e0, 0x463148d3, 0xf843f00a, 0x50c0f414, 0x2001d000, 
+    0x4ed149d0, 0x70084fd1, 0x20c0f3c4, 0x703049d0, 0x3000f3c4, 0xf3c47038, 0x700800c0, 0xea00200e, 
+    0x48cc1154, 0x48cc7001, 0xf829f00a, 0x48cc49cb, 0x78007809, 0x0100e9cd, 0x783148ca, 0x48ca7803, 
+    0x78387802, 0xf9bbf7ee, 0x2128e7c6, 0x20014652, 0xfc9ff7e0, 0x4ac5b2e0, 0xea4649c5, 0x61284000, 
+    0xd1024290, 0x2000f3c4, 0x2000e000, 0x20327008, 0xe015706f, 0x46522125, 0xf7e02001, 0x0370fc8a, 
+    0x0084ea40, 0x20046168, 0xe009706f, 0x46522126, 0xf7e02001, 0xea44fc7e, 0x61a820c6, 0x706f2005, 
+    0xe79970a8, 0xf04f49a4, 0x4ab230ff, 0x70487008, 0x20007088, 0x61486188, 0x21106108, 0x49ae6011, 
+    0x70084ab0, 0x700849ad, 0x700849ad, 0x70112101, 0x70114aad, 0x70114aad, 0x700849ad, 0x700849ad, 
+    0x7008499b, 0x700849ac, 0x7008499c, 0x7008499c, 0x7008499f, 0x700849a9, 0x70084992, 0x70084999, 
+    0x70084999, 0x70084991, 0x7008498f, 0x700849a4, 0xb57c4770, 0xffc6f7ff, 0x210848a2, 0xffaff009, 
+    0x780148a1, 0x780048a1, 0xfaa9f7ee, 0xf24148a0, 0x4c820500, 0x8802340a, 0xd0102a98, 0xd00e2a88, 
+    0xd00c2aa8, 0xd00a2ab8, 0xd0082ac8, 0xd01c2a94, 0xd01a2a84, 0xd0182aa4, 0xd0162ab4, 0x2300e021, 
+    0x220c4629, 0xf0094620, 0x2208ffa4, 0x23004620, 0xf0090151, 0x2300ff9e, 0x22014620, 0xf0092102, 
+    0x2300ff98, 0x21402206, 0x2300e008, 0x220c4629, 0xf0094620, 0x2300ff8e, 0x21022201, 0xf0094620, 
+    0x2300ff88, 0x22024620, 0xf0092104, 0x4863ff82, 0x21012300, 0x3042461a, 0xff7bf009, 0xff1df7ed, 
+    0x90002000, 0x46024603, 0x90014601, 0xf8f7f7ee, 0x2100485b, 0xf0093042, 0x485fff52, 0x304a2100, 
+    0xff4df009, 0x2100485c, 0xf009304c, 0x485aff48, 0x304e2100, 0xff43f009, 0x23004857, 0x461a21ff, 
+    0xf0093050, 0x2001ff56, 0xfca1f7e7, 0xf7e72011, 0x2012fc9e, 0xfc9bf7e7, 0xf7ed2002, 0x4865fc50, 
+    0x21042202, 0xff53f009, 0x28012401, 0x4862d109, 0x49622201, 0x20047004, 0xfb8cf7e7, 0xf7e7200b, 
+    0x495ffc86, 0x2300201b, 0x7008220c, 0x483a4629, 0x48587044, 0xf0091d80, 0xb002ff2c, 0x20012102, 
+    0x4070e8bd, 0x4270f04f, 0xbb93f7e0, 0x5ff0e92d, 0x46054c31, 0xf04f8e80, 0xb1300901, 0xd01428f0, 
+    0xd13428f1, 0x900cf8c4, 0xf7ffe01a, 0x492aff0b, 0x32fff04f, 0x311c68a0, 0xfbc0f005, 0x1d0060e0, 
+    0x68e0d001, 0x20f0e008, 0x4923e020, 0x68a02200, 0xf005311c, 0x60e0fbb3, 0xd0161d41, 0xd1e62801, 
+    0xf04f4f1d, 0x20014620, 0x371c4632, 0x1000f9b7, 0xfb5ff7e0, 0x1000f9b7, 0xd00a293a, 0xd00e293b, 
+    0x46322001, 0xfb55f7e0, 0x20f1e7d1, 0xe8bd86a8, 0xf7ff9ff0, 0x7862ff0e, 0x78212001, 0x4831e19a, 
+    0x0a00f04f, 0x29017801, 0xf994d00c, 0x28010001, 0x2802d00c, 0x2803d00d, 0x2806d056, 0x2807d057, 
+    0xe059d058, 0x9001f884, 0xa000f880, 0xfa7ef000, 0xf7ffe052, 0xe04ffe0c, 0x00040f14, 0xf38e0036, 
+    0xf38f0034, 0x000405d8, 0x000405dd, 0x000405dc, 0x000405d1, 0x000402be, 0xf2035112, 0x000405cf, 
+    0x000405d0, 0x000405db, 0x000405da, 0x002901d4, 0x000405d4, 0x00040238, 0x000405c4, 0x000405c6, 
+    0x000405c9, 0x000405c7, 0x000405c5, 0x000405ca, 0x000405c1, 0x000405cd, 0x000405ce, 0x000405d6, 
+    0x000405ea, 0xf38f228a, 0x00040545, 0x00040544, 0x00040558, 0xf2039026, 0x000405d2, 0x684ee180, 
+    0x00040245, 0x00040286, 0xfc67f7ff, 0xf000e004, 0xe001f9d9, 0xf99ff000, 0x282b7860, 0xf7ffd101, 
+    0xf994fbeb, 0x290d1000, 0x290ed021, 0x2931d02c, 0x2934d03d, 0x0605f24a, 0x2935d03c, 0xf8dfd048, 
+    0x290fb3f4, 0x2910d063, 0x4ffbd079, 0xf04f2919, 0xf242082d, 0xd0750601, 0xd06b291a, 0xd06a2911, 
+    0xd0692912, 0xd0682913, 0xd067292d, 0x2001e0f2, 0x5298f04f, 0xfaadf7e0, 0xf24a2200, 0x46110009, 
+    0xf9e5f7ed, 0xe0102034, 0xf04f2001, 0xf7e05298, 0x48eafaa0, 0x78002129, 0x2200ea41, 0x11d4f240, 
+    0x000bf24a, 0xf9d3f7ed, 0x70202031, 0xf7ffe02c, 0xe0c9fb2f, 0xf04f2001, 0xf7e05298, 0xf240fa8a, 
+    0xf24012cf, 0x463071d0, 0xf9c1f7ed, 0xe7ec2035, 0xf04f2001, 0xf7e05298, 0x4fd6fa7c, 0x22072019, 
+    0x37147020, 0x46382180, 0xfe11f009, 0x46062208, 0x01514638, 0xfe0bf009, 0x0040ea46, 0xf248b281, 
+    0x22004000, 0xf9a3f7ed, 0xfd37f7e2, 0x2001e09c, 0x5298f04f, 0xfa5df7e0, 0x46584631, 0xfdcff009, 
+    0xf2402100, 0x4630120a, 0xf991f7ed, 0xe7bc2010, 0xe007e005, 0xe042e026, 0xe050e044, 0xf000e068, 
+    0xe081f8d4, 0xf04f2001, 0xf7e05298, 0x7860fa42, 0xd103282c, 0x680048ba, 0xd0072801, 0xf24a2297, 
+    0x211b0006, 0xf973f7ed, 0xe79e201a, 0x46302200, 0xf7ed4611, 0x4631f96c, 0xf0094638, 0xf884fda0, 
+    0xe0648000, 0xf04f2001, 0xf7e05298, 0x48adfa22, 0x0109f248, 0x0800f241, 0xf4008800, 0xea41707e, 
+    0x48a90640, 0x48a97807, 0xfd86f009, 0x301ff367, 0xb2824641, 0xf7ed4630, 0x200ef94a, 0xf000e775, 
+    0xe041f86a, 0xf04f2001, 0xf7e05298, 0xf24afa02, 0x4638010a, 0xfd73f009, 0x70202013, 0x2001e00f, 
+    0x5298f04f, 0xf9f5f7e0, 0x304c4892, 0xfd64f009, 0x010ef000, 0xf0094638, 0xf884fd62, 0x46388000, 
+    0xfd5af009, 0x46012200, 0xf7e02001, 0xe01bf9e2, 0xf04f2001, 0xf7e05298, 0x2100f9dc, 0x2000f44f, 
+    0xf9eaf7e7, 0x21004883, 0xf0091c80, 0x4881fd48, 0x1d002100, 0xfd43f009, 0x46584631, 0xfd3ff009, 
+    0x46384631, 0xfd3bf009, 0x282d7820, 0x7860d102, 0xd003282c, 0x20027862, 0xe00b7821, 0x2001497c, 
+    0x5298f04f, 0xa000f881, 0xf7e0211d, 0x7862f9b2, 0x78212003, 0xfb34f7e2, 0x2200e629, 0xb5102101, 
+    0x30d7f2af, 0xf806f005, 0x20042108, 0xf964f005, 0x60884970, 0xb570bd10, 0x20014c6e, 0x5298f04f, 
+    0x1000f994, 0xf995f7e0, 0x4d6378e2, 0x2a01b132, 0x0100f248, 0x2a02d004, 0xe00ad006, 0x0108f24a, 
+    0xf0094628, 0xe004fcfc, 0xf0094628, 0x2012fcf8, 0x46287020, 0xfcf0f009, 0x46012200, 0xf7e02001, 
+    0x78e0f978, 0x70e01c40, 0xb570bd70, 0x20014c59, 0x5298f04f, 0x1000f994, 0xf96bf7e0, 0x4d534856, 
+    0x78001dad, 0xd00e2801, 0x46112200, 0xf7ed4610, 0x2100f89e, 0xf0094628, 0x202dfcd2, 0xe8bd7020, 
+    0xf7e24070, 0x484dbc2a, 0x494d2200, 0x78097800, 0xf00107c0, 0x0f400101, 0x0041ea40, 0x78094949, 
+    0x0101f001, 0x46114308, 0x7080f440, 0xf87ff7ed, 0x3180f248, 0xe92de7de, 0x4c3e41f0, 0x5698f04f, 
+    0x46322001, 0x1001f994, 0xf933f7e0, 0x220f4f32, 0x0100f248, 0x46381cbf, 0xfcc9f009, 0x46052200, 
+    0x71fff240, 0xf0094638, 0x4680fcc2, 0xf0094638, 0x2200fc93, 0x20014601, 0xf91bf7e0, 0x1002f994, 
+    0xd1092908, 0x46322001, 0xf913f7e0, 0x4641482e, 0xfc85f009, 0x70602006, 0xd1012d00, 0x7060202b, 
+    0x81f0e8bd, 0x41f0e92d, 0x20014c22, 0x5298f04f, 0x1001f994, 0xf8fdf7e0, 0x220f4f17, 0x0100f248, 
+    0x46381cbf, 0xfc93f009, 0x4680220d, 0x0100f242, 0xf0094638, 0x2200fc8c, 0xf2404606, 0x463871ff, 
+    0xfc85f009, 0x46384605, 0xfc56f009, 0x46012200, 0xf7e02001, 0x2e01f8de, 0x2d0ad105, 0x2008d103, 
+    0x200770a0, 0xf1b87060, 0xd1c90f00, 0x7060202b, 0x0000e7c6, 0xf38e002c, 0xf38fffce, 0x000405d3, 
+    0x00040238, 0x00040558, 0x000402f8, 0xf23c801e, 0x00040245, 0x00040f14, 0x000405c0, 0x000405c5, 
+    0x000405c7, 0x000405ca, 0xf2035112, 0x41f0e92d, 0xf04f4c23, 0x20015898, 0xf9944642, 0xf7e01001, 
+    0x4f20f8a8, 0xf0094638, 0x2200fc17, 0x46014605, 0xf7e02001, 0x481cf89e, 0x220c2600, 0x0100f241, 
+    0x46387006, 0xfc33f009, 0xf7edb130, 0x200dfbc6, 0x20027020, 0xe0167060, 0xf248220f, 0x46380100, 
+    0xfc25f009, 0x2011b128, 0x20067020, 0x70e67060, 0x202de009, 0x202b7020, 0xb9257060, 0x4642212e, 
+    0xf7e02001, 0x4909f876, 0x22002001, 0x20047008, 0xf7e74907, 0xe8bdf84f, 0x200b41f0, 0xb947f7e7, 
+    0x00040f14, 0xf38e0026, 0x00040600, 0x000405d2, 0x684ee180, 0x4840b570, 0xf009255c, 0x4604fbcd, 
+    0x1e80483d, 0xfbc8f009, 0xf4044a3c, 0x8011717f, 0x0103f004, 0x80114a3a, 0x5254f5a0, 0xf0243a90, 
+    0xd1200103, 0x40a0f5a1, 0xd02e3890, 0xd02c1f00, 0xd02a1f00, 0x4fa1f5b1, 0x3014d027, 0x1f00d025, 
+    0x3818d023, 0x1f00d021, 0x1f00d01f, 0x3808d01d, 0x3820d01b, 0x3820d019, 0x303cd017, 0x1f00d015, 
+    0x3810d013, 0x2000d011, 0x4826b188, 0x21e02205, 0xfbbdf009, 0x22004924, 0x70084c24, 0x46202101, 
+    0xfbb5f009, 0xd00b2801, 0x2001e010, 0xf7f9e7ec, 0x481cff83, 0x31b0f64b, 0xf0093082, 0xe7fefb80, 
+    0x46202301, 0x21102204, 0xfb93f009, 0xf64f4817, 0x300871ff, 0xfb73f009, 0x46202301, 0x21042202, 
+    0xfb87f009, 0x46202301, 0x461a2102, 0xfb81f009, 0x6828490f, 0xf2436008, 0x480a3164, 0xf0093818, 
+    0x4808fb5e, 0x1102f245, 0xf009381a, 0xe8bdfb58, 0xf7f94070, 0x0000be1c, 0xf2020006, 0x00040558, 
+    0x0004055a, 0xf23c8038, 0x00040234, 0xf23c8318, 0x00040540, 0x4d1eb570, 0x8e804604, 0x285eb120, 
+    0x285fd00d, 0xe014d125, 0xf04f4919, 0x682832ff, 0xf0051d09, 0x1d01f803, 0x205ed107, 0x4914e018, 
+    0x68282200, 0xf0041d09, 0x1d41fff9, 0x2801d00f, 0x4e0fd1ea, 0x88301d36, 0xd1e52862, 0x2102480d, 
+    0xfb1df009, 0x0002f9b6, 0xffe5f7df, 0x205fe7dc, 0xbd7086a0, 0x21012200, 0xf2afb510, 0xf0040067, 
+    0x2108fdf9, 0xf0042003, 0x4901ff57, 0xbd106008, 0x00040f38, 0xf23c806e, 0x41f0e92d, 0x22014dff, 
+    0x46282106, 0xfb23f009, 0x1cb74efd, 0xb3201eb4, 0x46282201, 0xf0092106, 0x2801fb1a, 0x2201d029, 
+    0x21064628, 0xfb13f009, 0xd1252802, 0x0100f243, 0xf0094630, 0x219cfae4, 0xf0094638, 0x2301fae0, 
+    0x22004620, 0xf009210f, 0x4620faf4, 0x41f0e8bd, 0x22042301, 0xf0092110, 0xf240baec, 0x46307507, 
+    0xf0094629, 0x4629facc, 0xf0094638, 0x230ffac8, 0xf240e7e6, 0xe7db1100, 0x81f0e8bd, 0x41f0e92d, 
+    0x48de4606, 0xfab8f009, 0xf3c00ac5, 0xf7ff1784, 0xf8dfffb3, 0x2400836c, 0x0824f1a8, 0x2301e007, 
+    0x21024640, 0xf009461a, 0x1c64fac4, 0x42bcb224, 0x2400dbf5, 0xe0074647, 0x46382301, 0x21042202, 
+    0xfab7f009, 0xb2241c64, 0xdbf542ac, 0x20012100, 0xf836f7e8, 0x4638b2b3, 0x21012200, 0xfaa9f009, 
+    0xf7e82003, 0xf04ff863, 0xb1360301, 0x21042202, 0xe8bd4638, 0xf00941f0, 0x2201ba9c, 0xe7f72102, 
+    0x2000b51f, 0x90019000, 0x90039002, 0xf7e84668, 0x9800ff1e, 0x48bbb281, 0xfa71f009, 0x0c019800, 
+    0x1c8048b8, 0xfa6bf009, 0xb2819801, 0x1d0048b5, 0xfa65f009, 0x0c019801, 0x1d8048b2, 0xfa5ff009, 
+    0xb2819802, 0x300848af, 0xfa59f009, 0x0c019802, 0x300a48ac, 0xfa53f009, 0xb2819803, 0x300c48a9, 
+    0xfa4df009, 0x0c019803, 0x300e48a6, 0xfa47f009, 0xb570bd1f, 0x20014ca4, 0x52a0f04f, 0x1103f240, 
+    0x70e00605, 0xf7df4628, 0xf240fec4, 0x462811f4, 0xfe71f7df, 0x61eef64e, 0xf7df4628, 0x499bfe5b, 
+    0xf7df4628, 0x2300fe57, 0x21014899, 0xf009461a, 0x4998fa40, 0x4a982000, 0x13697008, 0x1c407f20, 
+    0x0007f000, 0x1000eb00, 0x0080eb02, 0x20026081, 0xff8ef7e6, 0x4070e8bd, 0xf7e62003, 0xe92dbf89, 
+    0x46894ff0, 0x4690498d, 0x2201469b, 0x0a00f04f, 0x68094656, 0x88090253, 0xa000f8c8, 0x3000f8ab, 
+    0x0151eb02, 0xfa0f9a09, 0xf8a2fc81, 0xe055a000, 0xe02c2500, 0x0e05eb06, 0x0f02f1be, 0xeb00d404, 
+    0xf851018e, 0xe0007c08, 0x46522700, 0xf04f4654, 0x18e933ff, 0x4561d406, 0xeb0eda04, 0xf8500103, 
+    0xe0001021, 0x428f2100, 0x4614da03, 0x460f463a, 0x428ae007, 0x4614da02, 0xe002460a, 0xda00428c, 
+    0x1c5b460c, 0xdbe42b03, 0xf8491c6d, 0x4565402e, 0x2300dbd0, 0x18f1e01f, 0x5000f8d8, 0x4021f850, 
+    0x1021f859, 0x17ca1a61, 0xeb7a1a6d, 0xda110402, 0xda012a00, 0xe0072100, 0x4580f04f, 0x1a6d2400, 
+    0xda014194, 0x5100f04f, 0x1000f8c8, 0x3000f8ab, 0x800e9909, 0x45631c5b, 0x4466dbdd, 0x0f8cebb6, 
+    0xe8bddba6, 0xe92d8ff0, 0x240043f8, 0x461d460f, 0x94004616, 0x52a0f04f, 0x8020f8dd, 0x1000f9b0, 
+    0x7080f04f, 0xfe15f7df, 0x7004484d, 0x70c44846, 0x484c7104, 0xb1786800, 0x7800484b, 0xd0082801, 
+    0x48432100, 0x3102f201, 0xf0093008, 0xe8bdf978, 0xf24283f8, 0xe7f47110, 0xf04f703c, 0x603030ff, 
+    0x0000f8c8, 0x48370c01, 0x1f80602c, 0xf967f009, 0x22084c34, 0x3c1c2300, 0x46200151, 0xf979f009, 
+    0xf44f4d30, 0x4f390100, 0x91003538, 0xe00c138e, 0x462a2104, 0xf7e64668, 0x2801fe84, 0x2301d00c, 
+    0x22094631, 0xf0094620, 0x2206f964, 0x21404638, 0xf96df009, 0xd1eb2800, 0x23004821, 0x21102204, 
+    0xf0091e80, 0xe7c2f956, 0x4ff8e92d, 0x460c2500, 0x46904699, 0xab0ae9dd, 0xf04f9500, 0xf9b052a0, 
+    0xf04f1000, 0xf7df7080, 0x4821fdb4, 0x60054e16, 0x70054820, 0x0005f996, 0xd1141c40, 0xc078f8df, 
+    0xf8df2100, 0x2000e078, 0x1741eb0c, 0x1241eb0e, 0x3010f837, 0x3010f822, 0x28101c40, 0x1c49dbf8, 
+    0xdbf02904, 0x480e7175, 0x70f57005, 0xf8c87135, 0xf8c95000, 0xf8ca5000, 0xe0215000, 0xf2020126, 
+    0xf2035252, 0xf2035142, 0x00040f44, 0xdcba01f5, 0xf23c80b2, 0x000402ce, 0x00041708, 0x000405f8, 
+    0x000402cd, 0x00057f70, 0x0004055c, 0xf203502c, 0x000405b8, 0x000405bc, 0x00041478, 0x00041578, 
+    0x5000f8cb, 0x28007970, 0x7870d17e, 0xd07c2800, 0x780048fe, 0xd27928fa, 0x0002f996, 0x28007020, 
+    0x4dfbd072, 0x0000f44f, 0xf2404ff9, 0x35542800, 0x3ffa4cf7, 0xe00c9000, 0x462a2105, 0xf7e64668, 
+    0x2801fdf0, 0x2301d00c, 0x22094641, 0xf0094620, 0x2206f8d0, 0x21404638, 0xf8d9f009, 0xd1eb2800, 
+    0x35fff240, 0x230148eb, 0x22004629, 0xf8c1f009, 0x230f48e8, 0x46292200, 0xf0091e80, 0x88f0f8ba, 
+    0x2002bb08, 0xfe03f7e6, 0x46202208, 0x01512301, 0xf8aff009, 0x20402100, 0xfd2ef7e6, 0xf7e62003, 
+    0x2100fdf6, 0xf7e62040, 0x2100fd27, 0xf7e92008, 0x2001f861, 0xf8a6f7e9, 0x230048d6, 0x21102204, 
+    0xf0093832, 0x2101f896, 0x46082207, 0xf815f7e9, 0x218c48d1, 0xf873f009, 0x23ff48ce, 0x46292200, 
+    0xf0093818, 0x48cbf886, 0x2200233f, 0x11fff240, 0xf0091f00, 0x48c9f87e, 0x28017800, 0xf644d01e, 
+    0x48c76120, 0xe0028800, 0xe01ce016, 0xeb00e019, 0xebc20240, 0xeb0110c0, 0x8bb100c0, 0xf5a04408, 
+    0xb281707a, 0x301448bc, 0xf849f009, 0xb2818bb0, 0x301848b7, 0xf843f009, 0x8ff8e8bd, 0x5130f247, 
+    0x7025e7df, 0x2141e7f8, 0xf04f7025, 0xf04f52a0, 0xf7df7080, 0xe7effcbe, 0x4fffe92d, 0x4607b083, 
+    0xf04f2005, 0xf7e60b00, 0x4caefc7f, 0x48ae60e0, 0x28017800, 0x2802d037, 0x48acd035, 0xf81cf009, 
+    0x48aa4605, 0xf0091c80, 0xea45f817, 0x61604000, 0x70e02000, 0x46806360, 0x21009000, 0x4000f240, 
+    0xfcaaf7e6, 0x780048a2, 0x4c9eb328, 0xf04f2000, 0xf2407580, 0x70e011f4, 0xf7df4628, 0x499dfc3c, 
+    0xf7df4628, 0x499cfc27, 0xf7df4628, 0x7f20fc23, 0xf0001c40, 0xeb000007, 0x48981100, 0x0081eb00, 
+    0x31106881, 0x4891e184, 0xf0081f00, 0x4605ffe5, 0x1e80488e, 0x2005e7c7, 0xfc36f7e6, 0x61204c89, 
+    0x78004889, 0xd0132801, 0xd0112802, 0xf0084887, 0x4605ffd3, 0x1c804885, 0xffcef008, 0x4000ea45, 
+    0xe9d461a0, 0x42810103, 0x1a41d90a, 0xe0081c09, 0x1f00487e, 0xffc0f008, 0x487c4605, 0xe7eb1e80, 
+    0x4a7f1a41, 0x0004f04f, 0x0a14f04f, 0x091ef04f, 0x2000f992, 0xd0022a05, 0xd0052a04, 0x2005e009, 
+    0x0a0ff04f, 0xe0032214, 0xf04f2006, 0x220f0a0a, 0x40c14691, 0x9101486b, 0x0105e9d0, 0xd2024281, 
+    0x1c241a0c, 0x1a0ce000, 0x3f80f5b4, 0xf5a4d301, 0x98013480, 0xf00a44a0, 0x4605ffe7, 0x4620460e, 
+    0xffe2f00a, 0x22004b67, 0xf82ef00b, 0x4633462a, 0xfe0ef00a, 0x48644605, 0xe9d0460e, 0x46282300, 
+    0xf920f00b, 0x6b414857, 0x1c49d20d, 0x485f6341, 0xe9d04631, 0x46282300, 0xf914f00b, 0x4851d207, 
+    0x1c496b41, 0x2900e002, 0x2100da01, 0x484d6341, 0x6b404659, 0xdd004583, 0x46834608, 0x45d0b127, 
+    0x4948d302, 0x6348200b, 0xd0041c78, 0xd30245c8, 0x200b4944, 0x46316348, 0xe9d0484c, 0x46282300, 
+    0xf8f0f00b, 0x483fd303, 0x290a6b41, 0xf8dfdd6c, 0x210190f4, 0x0000f999, 0xd0082802, 0xd0062803, 
+    0x4836b3a7, 0x1003f889, 0xb3807800, 0xb36fe03b, 0xf04f9805, 0x70017a80, 0x11f4f240, 0xf7df4650, 
+    0xf64afb6a, 0x465041ca, 0xfb54f7df, 0x46504641, 0xfb50f7df, 0x22004b36, 0x46314628, 0xffc4f00a, 
+    0xff2ef00a, 0x46504601, 0xfb44f7df, 0x1034f8d9, 0xf7df4650, 0x9805fb3f, 0x1000f990, 0xf7df4650, 
+    0x4925fb39, 0xf7df4650, 0xe00cfb35, 0xe7ffe009, 0x3000f44f, 0x0103f640, 0xfb3df7df, 0xfdd6f7eb, 
+    0x9806e001, 0xf04f7001, 0xf2407a80, 0x46501bf4, 0xf7df4659, 0xf64afb30, 0x183920aa, 0xf7df4650, 
+    0x9805fb19, 0x1000f990, 0xf7df4650, 0x9806fb13, 0x1000f990, 0xf7df4650, 0x4805fb0d, 0xf00838fa, 
+    0x4601fedb, 0xe0254650, 0x0000e099, 0x0004055e, 0xf2035126, 0xf2035282, 0xf23c80a6, 0x0004055c, 
+    0x00057f78, 0x00040f44, 0x000405d9, 0xf2036116, 0x000402cd, 0x0bbbdead, 0xdcba01f5, 0x00041708, 
+    0x0004028a, 0x40140000, 0x000402d0, 0x000402d8, 0x40c38800, 0xfadef7df, 0x463148fa, 0x2300e9d0, 
+    0xf00b4628, 0xd208f84f, 0x46544621, 0xf7df4650, 0x9901fad1, 0xf7df4620, 0xf8d9facd, 0x464c1010, 
+    0x46504655, 0xfac6f7df, 0x462868e1, 0xfac2f7df, 0x46284eed, 0xf7df4631, 0xf242fabd, 0x064801c0, 
+    0xfad5f7df, 0x780048e9, 0x2100b350, 0xb13f70e1, 0x0000f994, 0xd0012802, 0xd1012803, 0x70019805, 
+    0x46284659, 0xfab7f7df, 0x21bbf64a, 0xf7df4628, 0x4631faa1, 0xf7df4628, 0x7f20fa9d, 0xf0001c40, 
+    0xeb000007, 0x48da1100, 0x0081eb00, 0x31206881, 0x49d86081, 0x60089804, 0x0003f994, 0xe4c0b007, 
+    0x0000f994, 0xd0042802, 0xd0022803, 0xf7e62003, 0x4659fbcf, 0xf7df4628, 0xf64bfa8e, 0x462831bb, 
+    0xfa78f7df, 0x46284641, 0xfa74f7df, 0x46286b61, 0xfa70f7df, 0x46284631, 0xfa6cf7df, 0x6981e009, 
+    0x69016141, 0x980060c1, 0x90001c40, 0xf4ff2832, 0xb1c7ae24, 0x7480f04f, 0x11f4f240, 0xf7df4620, 
+    0xf64bfa6a, 0x462031bd, 0xfa54f7df, 0x46204641, 0xfa50f7df, 0x462049b8, 0xf7df6b49, 0x49b2fa4b, 
+    0xf7df4620, 0x48b4fa47, 0x0003f990, 0xe92de7b6, 0x4cb04ffe, 0x0a00f04f, 0x52a0f04f, 0xf88d4680, 
+    0xf88da000, 0xf9b0a004, 0xf04f1000, 0x68267080, 0xfa8ff7df, 0x78e84da8, 0x2000b120, 0xa030f8c5, 
+    0x8ffee8bd, 0x20016821, 0xf42146a3, 0x602121c0, 0xf7e66328, 0x9002ff14, 0xf7e62000, 0x2000fee9, 
+    0xab01466a, 0xf7ff4631, 0x2002fdb7, 0x48976328, 0xb1907800, 0x7480f04f, 0x11f4f240, 0xf8c54620, 
+    0xf7dfa030, 0xf64ffa18, 0x462071ff, 0xfa02f7df, 0x4620498d, 0xf9fef7df, 0x2003e196, 0x20966328, 
+    0xf89d62e8, 0x28000004, 0x2005d07e, 0x78286328, 0xd07a2800, 0xf04f2006, 0xab01090a, 0x4631466a, 
+    0x20016328, 0xfd88f7ff, 0x78004880, 0xf8c5b110, 0xe179a030, 0x63282007, 0xf9904880, 0x28050000, 
+    0x2804d002, 0x2003d101, 0xf89d4681, 0x28000000, 0xf04fd07e, 0xf2407480, 0x462011f4, 0xf9dbf7df, 
+    0x0176f649, 0xf7df4620, 0x496ff9c5, 0xf7df4620, 0x2400f9c1, 0x4872e07e, 0x28017800, 0x2802d014, 
+    0x4870d012, 0xfd88f008, 0x486e4607, 0xf0081c80, 0xea47fd83, 0x61a84000, 0x1a416969, 0xd3134549, 
+    0x78004869, 0xe00fb140, 0x1f004866, 0xfd74f008, 0x48644607, 0xe7ea1e80, 0x3000f44f, 0x0103f640, 
+    0xf9a9f7df, 0xfc42f7eb, 0x1f406ae8, 0xd3174284, 0x7780f04f, 0x11f4f240, 0xf7df4638, 0xf246f99c, 
+    0x46387189, 0xf986f7df, 0x46384621, 0xf982f7df, 0x463869a9, 0xf97ef7df, 0x4638494b, 0xf97af7df, 
+    0x1e406ae8, 0xe0014284, 0xe059e057, 0x2001d101, 0x210070e8, 0x4000f240, 0xf9def7e6, 0x78004843, 
+    0xf04fb328, 0xf8857780, 0x4654a003, 0x11f4f240, 0xf88d4638, 0xf7dfa000, 0x4944f96e, 0xf7df4638, 
+    0x4939f959, 0xf7df4638, 0x7f28f955, 0xe0001c40, 0xf000e017, 0xeb000007, 0x48351100, 0x0081eb00, 
+    0x31306881, 0xf8cb6081, 0x632c6000, 0x69a8e0dc, 0x61681c64, 0x42846ae8, 0xaf7df4ff, 0xf7e62003, 
+    0x78e8fa87, 0xf04fb1e0, 0xf2407480, 0x462011f4, 0xf941f7df, 0x41ccf64c, 0xf7df4620, 0x4922f92b, 
+    0xf7df4620, 0x7828f927, 0x2143b118, 0x1000f8a8, 0x2009e006, 0x0000f8a8, 0x9802e002, 0xfde8f7e6, 
+    0x63282008, 0x280078e8, 0x7828d17e, 0xd07b2800, 0xf7e69802, 0x481cfddd, 0xb9087800, 0xfd87f7eb, 
+    0x46572002, 0xa004f885, 0xfa41f7e6, 0x9060f8df, 0x200a2208, 0x23016328, 0x01514648, 0xfce9f008, 
+    0x63282009, 0x0400f44f, 0x1e64e02c, 0xdc232c00, 0x46204c10, 0xfcbaf008, 0x0140f040, 0xf0084620, 
+    0xe026fcb8, 0x000402d8, 0xdcba01f5, 0x000402cd, 0x00041708, 0x00057ffc, 0x00040f44, 0x0004028a, 
+    0x000405d9, 0xf2036116, 0x0004055c, 0x0ddddead, 0xf2035126, 0xf000306c, 0x46482301, 0x02592209, 
+    0xfcb7f008, 0x220648f9, 0xf0082140, 0x2800fcc0, 0x48f7d1cb, 0xfc90f008, 0xf004b204, 0x1e490101, 
+    0x0002f004, 0xd0524308, 0x70e82001, 0xf7e62002, 0xf04ff9ff, 0xf2407980, 0x464811f4, 0xf8bbf7df, 
+    0x464849ec, 0xf8a6f7df, 0xf00848e8, 0xea40fc75, 0x46484104, 0xf89ef7df, 0x464849e7, 0xf89af7df, 
+    0x780048e6, 0xe000b1e8, 0xf240e031, 0x464c11f4, 0x70ef4648, 0xf89ff7df, 0x462049e1, 0xf88af7df, 
+    0x462049dd, 0xf886f7df, 0x1c407f28, 0x0007f000, 0x1100eb00, 0xeb0048db, 0x68810081, 0x60813130, 
+    0x78e8e00f, 0x7828b198, 0x2043b118, 0x0000f8a8, 0x2109e002, 0x1000f8a8, 0xf7e6200b, 0x48d2f9b9, 
+    0xf8cb7007, 0x632f6000, 0x0003f995, 0xf8cbe638, 0xe67c6000, 0x5ffce92d, 0xf2404dcc, 0x4ecc580b, 
+    0x8e814604, 0x4aeaf240, 0x9328f8df, 0x5b04f240, 0x45416bab, 0xf2a16837, 0xd06d500b, 0xf5b1dc31, 
+    0xd0756f9f, 0x4551dc13, 0x40eaf2a1, 0xdc07d071, 0xf5b1b331, 0xd0706f97, 0x0131f110, 0xe076d16b, 
+    0xd0592801, 0xd0672808, 0xd1642809, 0x4559e054, 0x5004f2a1, 0xdc07d07e, 0x010bf110, 0x2905d04c, 
+    0x2906d079, 0xe047d157, 0xd0452801, 0xd1522806, 0x220049ae, 0x313c4638, 0xf891f004, 0xd06b1d40, 
+    0x2818e03a, 0xdc20d038, 0xd035280c, 0x2805dc0e, 0x2806d07e, 0x280bd030, 0x49a4d13d, 0x46382200, 
+    0xf004313c, 0x1d40f87c, 0xe025d073, 0xd0712811, 0xd0212812, 0xd12e2817, 0x2200499c, 0x313c4638, 
+    0xf86df004, 0xd0661d40, 0x2826e016, 0xdc0fd014, 0xd075281d, 0xd00f281e, 0xd11c2825, 0x22004993, 
+    0x0000f8d9, 0xf004313c, 0x1d40f85a, 0xe003d069, 0xd0672829, 0xd10e282a, 0xf04f498c, 0x6ba832ff, 
+    0xf004313c, 0x1d01f87b, 0xf240d10d, 0xe1e240b8, 0xe09de0de, 0xe08fe001, 0x4984e0bb, 0x46182200, 
+    0xf004313c, 0x1d41f86b, 0x2801d03d, 0x4f7fd1e4, 0xf1a7373c, 0xf9b70114, 0x280f0000, 0x283fd036, 
+    0x2843d041, 0x2844d07a, 0x2845d079, 0x2846d078, 0xe002d077, 0xe0f1e10f, 0x2848e127, 0x2849d072, 
+    0x284ad071, 0x284cd070, 0x284dd06f, 0x2847d06e, 0x283ed06d, 0xf995d1c0, 0x46381000, 0xfd57f7ff, 
+    0xd0b92800, 0xf04f8838, 0x46390200, 0xe0032809, 0xe13ae121, 0xe168e14f, 0x6ba8d079, 0xfffff003, 
+    0xd0751d01, 0xf240e193, 0xe19440b9, 0x91004b5f, 0x3324495e, 0xf1011f1a, 0xf7ff003c, 0xe79bf9b4, 
+    0xe179e166, 0x4959e17e, 0x1f083118, 0xe9cd1f03, 0x1f1a0100, 0x30283918, 0xfa06f7ff, 0xb92088e8, 
+    0xf7e62002, 0x2800f8c6, 0x494cd186, 0x28007808, 0x8928d182, 0x81281c40, 0x70082001, 0x80382043, 
+    0x0000f995, 0xd0012802, 0xd10b2803, 0x1c408968, 0x48498168, 0xf2487801, 0xf7e50000, 0x2000ffbd, 
+    0xf85cf7ff, 0x22004941, 0x313c6ba8, 0xffb7f003, 0xd1131d01, 0xa034f8a4, 0x9ffce8bd, 0xe033e013, 
+    0xe085e051, 0xe0b3e0a1, 0xe0e1e0cf, 0xe10fe0fd, 0x22004936, 0x313c4618, 0xffa1f003, 0xd1ae1d40, 
+    0x40ebf240, 0x4b31e137, 0x49309100, 0x1f1a3324, 0x003cf101, 0xf942f000, 0x2200492c, 0x313c6ba8, 
+    0xff8df003, 0xd10a1d01, 0x40f2f240, 0xe109e123, 0x4926e115, 0x46182200, 0xf003313c, 0x1d40ff80, 
+    0xf240d18d, 0xe11640f3, 0x23004a20, 0x32249100, 0xf1011f11, 0xf000001c, 0x491cfc0c, 0x6ba82200, 
+    0xf003313c, 0x1d01ff6c, 0xf240d108, 0xe10240f8, 0x22004916, 0x313c4618, 0xff61f003, 0xd1871d40, 
+    0x40f9f240, 0x4811e0f7, 0xe9d52300, 0x303c1208, 0xfae9f001, 0x2200490d, 0x313c6ba8, 0xff4ff003, 
+    0xd1201d01, 0x40fef240, 0x0000e0e5, 0xf203502c, 0xf2060040, 0x00011104, 0xdcba01f5, 0x000402cd, 
+    0x0eeedead, 0x00041708, 0x000402ce, 0x00040f44, 0x000406f0, 0x00040734, 0x0004028b, 0x2200496e, 
+    0xf0034618, 0x1d40ff2c, 0xf240d189, 0xe0c240ff, 0xf9954b69, 0x3b141000, 0xf1a34867, 0xf0010208, 
+    0x4965fd04, 0x6ba82200, 0xff19f003, 0xd1071d01, 0xb034f8a4, 0x4960e760, 0x46182200, 0xff0ff003, 
+    0xd18d1d40, 0x5005f240, 0xf995e0a5, 0x485a1000, 0xffa7f001, 0x22004958, 0xf0036830, 0x1d01ff00, 
+    0xae6cf47f, 0x500af240, 0xf8a4e095, 0xe7438034, 0xf9954b51, 0x3b141000, 0xf1a3484f, 0xf0010208, 
+    0x494dffd5, 0x6ba82200, 0xfee9f003, 0xd1071d01, 0x5010f240, 0x4948e07f, 0x46182200, 0xfedff003, 
+    0xd1b11d40, 0x5011f240, 0xf995e075, 0x48421000, 0xf805f002, 0x22004940, 0xf0036830, 0x1d01fed0, 
+    0xae51f47f, 0x5016f240, 0xf240e065, 0xe0625017, 0xf9954b39, 0x3b141000, 0xf1a34837, 0xf0020208, 
+    0x4935f915, 0x6ba82200, 0xfeb9f003, 0xd1071d01, 0x501cf240, 0x4930e04f, 0x46182200, 0xfeaff003, 
+    0xd19e1d40, 0x501df240, 0xf995e045, 0x482a1000, 0xfbf2f002, 0x22004928, 0xf0036830, 0x1d01fea0, 
+    0xae30f47f, 0x5022f240, 0xf240e035, 0xe0325023, 0x1000f995, 0x6a2a4820, 0xf9d1f002, 0x2200491e, 
+    0xf0036ba8, 0x1d01fe8c, 0xf240d107, 0xe0225028, 0x22004919, 0xf0034618, 0x1d40fe82, 0xf240d1a1, 
+    0xe0185029, 0x0000f8d9, 0xfe79f003, 0xf47f1d01, 0xf240ae1c, 0xe00e5030, 0x5031f240, 0xf240e00b, 
+    0xe0085034, 0x2200490c, 0xf0034618, 0x1d40fe68, 0xf240d187, 0x86a05035, 0x2200e6ae, 0xb5102101, 
+    0x40eff2af, 0xfca6f003, 0x20042108, 0xfe04f003, 0x393c4901, 0xbd106388, 0x00040f80, 0x4fffe92d, 
+    0x4683b083, 0x250048fe, 0x52a0f04f, 0x9502460f, 0xf8d09c10, 0x48fba000, 0x1000f9bb, 0x5980f50a, 
+    0x88066800, 0x7080f04f, 0xfe23f7de, 0xf7e62000, 0xf8dffa8f, 0x230083d4, 0xf24f220c, 0x46400100, 
+    0xf990f008, 0xf6402300, 0x22087100, 0xf0084640, 0x2300f989, 0x22044640, 0xf00821f0, 0x2300f983, 
+    0x210f4640, 0xf008461a, 0x48e8f97d, 0xf0082100, 0x2200f976, 0x23109500, 0x46104611, 0xf964f7e9, 
+    0x700548e3, 0x780048e3, 0x7838b988, 0xd00e2803, 0x3000f44f, 0x0103f640, 0xfd9df7de, 0xf836f7eb, 
+    0x210048dd, 0x2000f990, 0xf7e74608, 0x4ddbff87, 0x23002208, 0x46280151, 0xf96bf008, 0x0000f44f, 
+    0x2800f240, 0xe00d9002, 0x21074ad4, 0x3254a802, 0xfe77f7e5, 0xd00d2801, 0x46412301, 0x46282209, 
+    0xf957f008, 0x220648cd, 0x38fa2140, 0xf95ff008, 0xd1e92800, 0x250148ca, 0x0000f990, 0xd0012805, 
+    0xd1002804, 0xf9972502, 0xf8df0000, 0x28038318, 0x2802d004, 0x2804d005, 0xe026d018, 0x220049c2, 
+    0x48c2e010, 0x0000f9b0, 0xda052801, 0x220348c0, 0xf0082138, 0xb108f93c, 0xe00048be, 0x220048be, 
+    0xf100fb05, 0xf7e52002, 0xe00efd75, 0x0000f898, 0x0200f04f, 0x49b9b3f0, 0xf7e52002, 0x4ab8fd6b, 
+    0xf04f2100, 0xf7de7080, 0x2100fd84, 0xf7e52002, 0x2002fd2b, 0xfd48f7e5, 0x4db349b2, 0x60084ab3, 
+    0x31fff04f, 0x60019805, 0x99062000, 0x68286008, 0x60281c40, 0x1c498811, 0xb2818011, 0x3018489f, 
+    0xf8ddf008, 0x21007828, 0x0007f000, 0x1200eb00, 0xeb0048a7, 0x63010082, 0xf7e52005, 0x682afd25, 
+    0x0107f002, 0x1301eb01, 0xeb0149a1, 0xe9c10183, 0xe000020d, 0x489fe010, 0x63c88800, 0x6800489e, 
+    0xf7e56408, 0x489df824, 0x213f2200, 0xf8dff008, 0xd3072811, 0xe0062001, 0x20024999, 0xfd1af7e5, 
+    0xe7ad4a98, 0x49892000, 0x220a2301, 0x8188029d, 0x48824629, 0xf0083830, 0x4880f8bc, 0x220a2300, 
+    0x38304629, 0xf8b5f008, 0x7800488f, 0x2000b910, 0xfdd4f7fe, 0x7801487a, 0x0000f997, 0xfd38f7e1, 
+    0x488a2301, 0x0399220e, 0xf8a3f008, 0x0000f997, 0x4d884f87, 0xd0042802, 0xd01f2803, 0xd0672804, 
+    0x2001e0c2, 0xfe52f7fb, 0x20012100, 0xfe2af7e6, 0x88004881, 0x48819000, 0x78037839, 0xf9904880, 
+    0x20072000, 0xfd61f7fb, 0x487e2301, 0x46192200, 0xf87ff008, 0xf7fb2000, 0xe088fc97, 0x89804863, 
+    0xd1142801, 0x22004878, 0xf9902308, 0x46106000, 0xa900e9cd, 0xf7e44631, 0x4974fb1f, 0x48742301, 
+    0xe9cd2200, 0x46310100, 0xf7e44618, 0x4871fb15, 0x28017800, 0xf7fbd105, 0x2100fe19, 0xf7e62001, 
+    0x486dfdf1, 0x28017800, 0xf8dfd17b, 0x2600a1b0, 0x91acf8df, 0x486b2200, 0x1346eb0a, 0x1146eb09, 
+    0x1746eb00, 0x1c406820, 0xf837d00f, 0xf8210012, 0x1c520012, 0x2a10b252, 0x4630dbf4, 0xfbb0f7e4, 
+    0xb2761c76, 0xdbe52e04, 0xf833e125, 0xe7ee0012, 0xf04f485d, 0xf8df0a02, 0x78009174, 0xd0012801, 
+    0xe051b3d8, 0x8800484c, 0x484c9000, 0x78037839, 0xf990484b, 0x20072000, 0xfcf7f7fb, 0x48492301, 
+    0x46192200, 0xf815f008, 0xf7fb2000, 0xf898fc2d, 0x28010000, 0xf889d101, 0x7828a000, 0xd1162801, 
+    0xa108f8df, 0xf8df2400, 0x23019108, 0xf006fb04, 0xeb0a2200, 0xeb090140, 0xe9cd0040, 0x46210100, 
+    0xf7e44618, 0x1c64faa9, 0x2c04b264, 0x7839dbed, 0x1000f240, 0xfbdaf7e4, 0xe000e016, 0xf898e011, 
+    0x28010000, 0xf889d101, 0x4839a000, 0xb9307800, 0xf7fb2001, 0x2100fd9b, 0xf7e62001, 0x7828fd73, 
+    0x2004b168, 0xfbf0f7fb, 0x7480f04f, 0x11f4f240, 0xf7de4620, 0xf243fbf0, 0x46203100, 0xe09be05a, 
+    0x00040230, 0x000405f8, 0xf100004c, 0xf2031034, 0x00040dec, 0x0004055c, 0x00040290, 0xf2035126, 
+    0x0004028a, 0x000405c8, 0x008583b0, 0x00040f98, 0xf38f007c, 0x017d7840, 0x0094c5f0, 0x03b9aca0, 
+    0xffee1234, 0x000405b0, 0x00040f60, 0x00040f90, 0x00041708, 0x000405a4, 0x000402ac, 0xf2034202, 
+    0x00bebc20, 0xffeeddcc, 0x000402cd, 0xf2030416, 0x000405d9, 0x000405c5, 0x000402b8, 0x00040310, 
+    0x00040234, 0xf20305ae, 0x00040570, 0x00049178, 0x00048978, 0x000405c2, 0x000405c3, 0x00041478, 
+    0x000412c8, 0x000414f8, 0x000405cb, 0x000405ae, 0x000405c4, 0xfb7ef7de, 0xf99048fe, 0x46201000, 
+    0xfb78f7de, 0x680148fc, 0xf7de4620, 0x2112fb73, 0xf7de4620, 0x49f9fb6f, 0x78094620, 0xfb6af7de, 
+    0x462049f7, 0xf7de7809, 0x48f6fb65, 0x46207801, 0xfb60f7de, 0x46207829, 0xfb5cf7de, 0x1000f898, 
+    0xf7de4620, 0x48f0fb57, 0x46207801, 0xfb52f7de, 0x780148ee, 0xf7de4620, 0x48edfb4d, 0x46207801, 
+    0xfb48f7de, 0x462049eb, 0xfb44f7de, 0xf8ab2144, 0xb0071000, 0x8ff0e8bd, 0xa39cf8df, 0xf8df2600, 
+    0x2200939c, 0xeb0a48e6, 0xeb091746, 0xeb001146, 0x68231046, 0xd0171c5b, 0x3012f837, 0x3012f821, 
+    0xb2521c52, 0xdbf42a10, 0xf7e44630, 0x1c76fa89, 0x2e04b276, 0x2001dbe5, 0xfb26f7fb, 0x01c0f242, 
+    0xf7de0648, 0xe72ffb34, 0x3012f830, 0xe92de7e6, 0x469041f0, 0x24014ad3, 0x88126812, 0x0e52eb04, 
+    0xeb081ea4, 0xfa0f0c04, 0x2200f78c, 0xfb026806, 0xf853c50e, 0x42b55025, 0x6005d301, 0x1c52800f, 
+    0x2a04b212, 0x1c64dbf2, 0x2c01b224, 0xe8bddde9, 0xe92d81f0, 0xb0914fff, 0x20004688, 0xf04f4dc2, 
+    0xf64952a0, 0x900f4940, 0x900b48c0, 0x680048bd, 0xf2408804, 0xfbb01000, 0x0867f0f4, 0x97099708, 
+    0xb2401c7f, 0x200a900d, 0xf0f0fbb4, 0x900ab200, 0xf9b09811, 0xf04f1000, 0xf7de7080, 0x2100fb2a, 
+    0x3080f44f, 0xfb38f7e5, 0xb288f8df, 0x0000f99b, 0xd00d2803, 0xd00b2804, 0xf99048ad, 0x28050000, 
+    0x2804d001, 0x2100d104, 0x3000f44f, 0xfb24f7e5, 0x21002000, 0x1020f845, 0xb2001c40, 0x6f80f5b0, 
+    0x9814dbf7, 0xd17d2800, 0x01c0f242, 0xf7de0648, 0xf99bfabe, 0x465e0000, 0xd0012803, 0xd11e2804, 
+    0xf2482100, 0xf7e50000, 0x489afb07, 0x0100f04f, 0x28018980, 0xf248d007, 0xf7e50000, 0x7830fafd, 
+    0xd0032804, 0xf244e006, 0xe7f60000, 0x78004888, 0xd0042801, 0x78004890, 0xf7eab908, 0xf242fef8, 
+    0x064801c0, 0xfa93f7de, 0x0000f996, 0x280346b3, 0x2802d003, 0x2804d001, 0x4888d161, 0xfe3cf007, 
+    0xf99bb206, 0x28030000, 0x2802d008, 0x2804d002, 0xe007d004, 0x68004870, 0xd2032812, 0xf44f2100, 
+    0xe0023080, 0xf44f2100, 0xf7e53000, 0x0770fac5, 0xf64fd512, 0xea0670fb, 0x48780100, 0xfe1ff007, 
+    0x78004873, 0xd1072803, 0x0000f89b, 0xd1032802, 0x04002100, 0xfab0f7e5, 0x46304e70, 0xfe0cf007, 
+    0x0608b201, 0xf64fd505, 0x4001707f, 0xf0074630, 0x4630fe06, 0xfe00f007, 0x04c8b201, 0xf64ed50e, 
+    0xe00070ff, 0x4001e00a, 0xf0074630, 0x2100fdf8, 0xf7f72001, 0x2000f96f, 0xff42f7f6, 0x0000f99b, 
+    0xd0052802, 0xd10a2804, 0x78004851, 0xd1062801, 0xfc7ef7e7, 0x900eb200, 0xf7e72008, 0xf242fc73, 
+    0x064801c0, 0xfa23f7de, 0x78004842, 0xd1202804, 0xb14cf8df, 0xe0182600, 0xdd162e00, 0xf7e74850, 
+    0xf8dbfa76, 0x46582000, 0xd209454a, 0x454a6842, 0x6882d206, 0xd203454a, 0x100cf8db, 0xd3084549, 
+    0xf44f2100, 0xf7e53080, 0x1c76fa57, 0x2e0ab236, 0xb220dbe2, 0x0b00f04f, 0xf04f9006, 0xf2420900, 
+    0x064801c0, 0xf9f3f7de, 0x98062301, 0x029a2105, 0x000fe88d, 0x1f8a483b, 0x21082300, 0xf7fa6800, 
+    0x2600fafd, 0x46224937, 0xf004fb06, 0xeb016809, 0x492c0040, 0xf9b16809, 0x49333080, 0xfd57f007, 
+    0x4b324828, 0x68004a32, 0xf8d07881, 0xe9cd0094, 0x482d0100, 0xf007990f, 0xf8dffeaf, 0x2000e098, 
+    0x492be017, 0x3020f851, 0xf8514928, 0xfb811020, 0xfbc31201, 0xfb061203, 0xe9ce0307, 0x0d891204, 
+    0xc023f855, 0x2182ea41, 0x44611c40, 0xf845b200, 0x42b81023, 0xfb06dbe5, 0x4906f007, 0xf8452200, 
+    0xf9912020, 0x29021000, 0x2905d001, 0xeb00d134, 0xe02f0154, 0x00040f44, 0x00040238, 0x000405c2, 
+    0x000405c3, 0x000405c4, 0x000405c9, 0x000405ca, 0x000405cb, 0xdcba01f5, 0x000414f8, 0x000412c8, 
+    0x00041478, 0x000405f8, 0x00046978, 0x00047978, 0x0004028a, 0x00040f98, 0x0004055c, 0xf23c80b8, 
+    0x00041458, 0x00040224, 0x00049978, 0x0004d178, 0x0004c178, 0x2021f845, 0x6809991e, 0x0f94ebb1, 
+    0xeb00d103, 0xf8450094, 0x1c762020, 0x2e04b276, 0xaf78f6ff, 0x0001f109, 0xf980fa0f, 0x0f02f1b9, 
+    0xaf5df6ff, 0x0f00f1bb, 0xa80cd10d, 0xab05990b, 0xaa079000, 0xf7fe4628, 0xf9bdfaf2, 0x49fd0030, 
+    0xf0f7fb90, 0xf10b8148, 0xfa0f0001, 0xf1bbfb80, 0xf6ff0f01, 0xf242af42, 0x064801c0, 0xf937f7de, 
+    0xf99048f5, 0x28020000, 0x2804d005, 0x48f3d107, 0x28017800, 0x980ed103, 0xf7e7b2c0, 0x4eedfb73, 
+    0xf04f2000, 0x90047980, 0xf2401e40, 0x80b011f4, 0xf7de4648, 0xf240f910, 0x46487171, 0xf8faf7de, 
+    0x1000f9b6, 0xf7de4648, 0x49e5f8f5, 0xf7de4648, 0x9814f8f1, 0x48e3bbf0, 0xbbd87800, 0xf99048de, 
+    0x28020000, 0x2804d006, 0x48dcd134, 0xb9087800, 0xfb8cf7ea, 0x7b80f04f, 0x11f4f240, 0xf7de4658, 
+    0xf641f8ea, 0x46581199, 0xf8d4f7de, 0x46584ed6, 0x1000f996, 0xf8cef7de, 0x1030f9bd, 0xf7de4658, 
+    0xf8dff8c9, 0x46589330, 0x100af9b9, 0xf8c2f7de, 0x1000f996, 0x000af9b9, 0xd1654281, 0xb01cf8dd, 
+    0x0900f04f, 0xf9bd464e, 0xfb060014, 0xf8550007, 0xe0001020, 0xf04fe05d, 0xf7de7080, 0xf9bdf8ab, 
+    0xfb060014, 0xf8550007, 0x45580020, 0x4683da01, 0x1c7646b1, 0x2e04b276, 0xf8dfdbe5, 0xf89bb2dc, 
+    0x28040000, 0xf1b9d10a, 0xd0030f00, 0x0f03f1b9, 0xe003d002, 0xe0002001, 0x46812002, 0x7080f04f, 
+    0xf7de4649, 0xf9bdf887, 0xf04f1014, 0xf7de7080, 0xf7eaf881, 0x4eacfc7b, 0x1402b201, 0xf8864610, 
+    0xf7ea9000, 0x49a9fb9d, 0x70082001, 0xf7ea2002, 0xf996fda8, 0xf7ea0000, 0xf996faf9, 0xf7ea0000, 
+    0xf996fb39, 0xf7ea0000, 0xf996fb84, 0xf04f1000, 0xf7de7080, 0xf89bf85f, 0x28040000, 0x4897d104, 
+    0xb9087800, 0xfcd3f7ea, 0xf04f4995, 0xf7de7080, 0xf8dff851, 0xf8b99240, 0xbbe80000, 0x0014f9bd, 
+    0xf1092603, 0x462b0104, 0xf0f6fb90, 0xa804b202, 0xfd2df7ff, 0x0014f9bd, 0x7b80f04f, 0x11f4f240, 
+    0xfb901a20, 0xfa0ff0f6, 0x4658fa80, 0xf843f7de, 0x4101f244, 0xf7de4658, 0x4651f82d, 0xf7de4658, 
+    0xf9b9f829, 0x464e1004, 0xf7de4658, 0x497cf823, 0xf7de4658, 0xf9bdf81f, 0xebaa1014, 0x1d000001, 
+    0xd9052808, 0x462b1d31, 0x4652a804, 0xfcfff7ff, 0xf8dd88b0, 0xe000a010, 0x8130e01c, 0xf9bd462b, 
+    0x496c0014, 0x70d0eb00, 0x10421d09, 0xf7ffa804, 0xf9bdfcee, 0x1a210014, 0x71d1eb01, 0xb20a1049, 
+    0x1d001a10, 0xd9052808, 0xa8044962, 0x1d09462b, 0xfcddf7ff, 0x1004f9b9, 0x4281980a, 0x2000da04, 
+    0x1e409004, 0x0004f8a9, 0x0014f9bd, 0x0b01f04f, 0xb20e0041, 0x0194eb0b, 0xdc034281, 0xeb044241, 
+    0xb20e0141, 0xdc06287d, 0xa8044952, 0x4632462b, 0xf7ff1d09, 0x9804fcbc, 0xf9bd9000, 0x96020014, 
+    0xeb00282b, 0xb20a0140, 0xeba0db03, 0x44210180, 0x2845b20a, 0xebb0dc08, 0xd0050f94, 0xa8044945, 
+    0x1d09462b, 0xfca3f7ff, 0x7080f04f, 0x11f4f240, 0xffc1f7dd, 0x7080f04f, 0x7177f240, 0xffaaf7dd, 
+    0x68014843, 0x7080f04f, 0xffa4f7dd, 0x1014f9bd, 0x7080f04f, 0xff9ef7dd, 0x0a019807, 0x7080f04f, 
+    0xff98f7dd, 0xf04f4e36, 0x46317080, 0xff92f7dd, 0x7080f04f, 0x11f4f240, 0xff9df7dd, 0x7080f04f, 
+    0x51ddf64d, 0xff86f7dd, 0x7801482e, 0x7080f04f, 0xff80f7dd, 0x7080f04f, 0xf7dd4631, 0x482cff7b, 
+    0x4e252100, 0xf0007800, 0xeb000007, 0x48291200, 0x0082eb00, 0x610160c1, 0xf9bd6141, 0xf8c0e014, 
+    0xf9bde01c, 0x62022030, 0x0a5a9b07, 0x62416182, 0x900108a0, 0x0000f8c8, 0x60019813, 0x1002f8a9, 
+    0x1006f8a9, 0x0000f996, 0xd0352803, 0xd0332804, 0x28032104, 0x2804d032, 0x260ad030, 0xc034f8dd, 
+    0xfc0cfb11, 0xebbc990d, 0xf8cd2f53, 0xfb16c018, 0xb209f101, 0xf8c8d22f, 0x2803e000, 0x601a9b13, 
+    0x2804d01f, 0x9804d01d, 0x2f10ebb1, 0xf8a9d87c, 0xe079b002, 0x00040f98, 0x00040f44, 0x000405cb, 
+    0xdcba01f5, 0x0004055c, 0x00040290, 0x0004028e, 0x00040f60, 0x00041708, 0xe7ca2132, 0x16f4f240, 
+    0x9804e7cc, 0x2f10ebb1, 0xf9b9d85e, 0x990a2004, 0xdadc428a, 0x2803e058, 0x2804d02d, 0xf04fd02b, 
+    0xf2407080, 0xf7dd11f4, 0xf04fff16, 0xf6487080, 0xf7dd0180, 0x4efefeff, 0x7080f04f, 0xf7dd6831, 
+    0x48fcfef9, 0xf04f7801, 0xf7dd7080, 0xf8d8fef3, 0xf04f1000, 0xf7dd7080, 0x49f7feed, 0x7080f04f, 
+    0xfee8f7dd, 0x28016830, 0x48f2db15, 0x28237800, 0x9808d811, 0x981ee011, 0x1c416800, 0x2880d007, 
+    0xf8c8d005, 0x99080000, 0x1004f8a9, 0x9908e79f, 0x1000f8c8, 0xf04fe018, 0xf24030ff, 0xf04f11f4, 
+    0xf8c87680, 0x46300000, 0xfed5f7dd, 0x1000f8d8, 0xf7dd4630, 0x49e0febf, 0xf7dd4630, 0x2100febb, 
+    0x1002f8a9, 0x1006f8a9, 0x680048dc, 0xd3752812, 0x1014f9bd, 0x0f94ebb1, 0xf8b9d107, 0x46482002, 
+    0x9a08b91a, 0xf8a98082, 0x48d5b002, 0x0000f990, 0xd0012803, 0xd1102804, 0x0f54ebb1, 0xf04fd005, 
+    0xeb0232ff, 0x428a0254, 0xf8b9d107, 0x464a3002, 0x9b01b91b, 0xf8a98093, 0x9a0ab002, 0xdc024291, 
+    0xf8a92100, 0x28031002, 0x2804d001, 0xf8b9d108, 0x46492002, 0x9a1eb922, 0x808a8812, 0xb002f8a9, 
+    0xf9b9464e, 0xf9b91008, 0x42912004, 0x8872d036, 0x2803bba2, 0x2804d060, 0xea5fd05e, 0xd02d205a, 
+    0x4281980a, 0xf04fdb2a, 0xf2407080, 0xf8a611f4, 0xf7ddb006, 0xf04ffe70, 0xf2457080, 0xf7dd5122, 
+    0xf9b6fe59, 0xf04f1006, 0xf7dd7080, 0xea4ffe53, 0xf04f215a, 0xf7dd7080, 0xf9b6fe4d, 0xf04f1004, 
+    0xf7dd7080, 0xf9b6fe47, 0xf04f1008, 0xf7dd7080, 0x49a1fe41, 0x7080f04f, 0xfe3cf7dd, 0xb3a89814, 
+    0x70d0f240, 0x26009001, 0xf04f1081, 0xf7dd7080, 0xf04ffe42, 0xf2437080, 0xf7dd3111, 0xf04ffe2b, 
+    0xf2407080, 0xf7dd71d0, 0x4892fe25, 0xf04f7801, 0xf7dd7080, 0xf04ffe1f, 0xf2407080, 0xf7dd71d0, 
+    0x498dfe19, 0x7080f04f, 0xfe14f7dd, 0x0014f9bd, 0xdb0c2819, 0xe00d9901, 0xebb22205, 0xd8cd2f5a, 
+    0x4281980a, 0xf8a9dbca, 0xe7c7b006, 0xf640e09a, 0x910171a0, 0xc01cf8dd, 0x2f5cebb1, 0x2103d225, 
+    0x0308f1a7, 0xdc0b4298, 0x200af9b9, 0x0e01eb00, 0xee07fb02, 0xf8529a0b, 0x42b2202e, 0x4616db00, 
+    0x0f54ebb0, 0xebb0d002, 0xd10a0f94, 0x200af9b9, 0x1e07fb02, 0xeb029a0b, 0x6c92028e, 0xdb0042b2, 
+    0x1c894616, 0x2907b209, 0x2100dddc, 0x0f54ebb0, 0xebb0d002, 0xd1000f94, 0xf9b92102, 0x1d49200a, 
+    0x0207fb02, 0x2022f855, 0x42b2410a, 0x9901db03, 0x2f5cebb1, 0x9a13d302, 0x60112100, 0x4c612100, 
+    0x9a137021, 0x2a006812, 0x381cdd07, 0xd8042808, 0x7800485d, 0xf884b908, 0x9804b000, 0x980d0a42, 
+    0x0340eb00, 0x10c0ebc3, 0x1f00ebb2, 0xf8a9d801, 0xea4f1002, 0xebb2225a, 0xd8011f00, 0x1006f8a9, 
+    0x7780f04f, 0x11f4f240, 0xf7dd4638, 0xf241fda4, 0x46381122, 0xfd8ef7dd, 0x1000f994, 0xf7dd4638, 
+    0x9901fd89, 0xf7dd4638, 0x9807fd85, 0x46380a41, 0xfd80f7dd, 0x1014f9bd, 0xf7dd4638, 0x4631fd7b, 
+    0xf7dd4638, 0xf9b9fd77, 0x464c1002, 0xf7dd4638, 0xf9b4fd71, 0x46381006, 0xfd6cf7dd, 0x46384936, 
+    0xfd68f7dd, 0x0106e9dd, 0x2f51ebb0, 0xf04fd342, 0xf2407480, 0x462011f4, 0xfd6df7dd, 0x0181f648, 
+    0xf7dd4620, 0x4e2afd57, 0x68314620, 0xfd52f7dd, 0x46204f28, 0xf7dd7839, 0xf8d8fd4d, 0x46201000, 
+    0xfd48f7dd, 0x46204924, 0xfd44f7dd, 0x28016830, 0x7838db04, 0xd8012823, 0xe0019808, 0x30fff04f, 
+    0x11f4f240, 0x0000f8c8, 0xf7dd4620, 0xf8d8fd44, 0x46201000, 0xfd2ef7dd, 0x6801981e, 0xf7dd4620, 
+    0x4915fd29, 0xf7dd4620, 0x2100fd25, 0x1002f8a9, 0x1006f8a9, 0x6801981e, 0x0000f8d8, 0xd1744281, 
+    0xd0721c40, 0x0000f8b9, 0x490a464c, 0xb2001c40, 0x0000f8a9, 0x29467809, 0x2802d320, 0x8863db1c, 
+    0xd1192b01, 0x2a0188e2, 0x9b04d116, 0xe00d4553, 0x00040f60, 0x0004055e, 0xdcba01f5, 0x00040238, 
+    0x00040f44, 0x00040f89, 0x0004055c, 0x0200f04f, 0x80e2d301, 0x8062e000, 0xd8492946, 0xdb472801, 
+    0x21329800, 0x2f50ebb1, 0x8862d20d, 0xf9b4b95a, 0x46203004, 0x42939a0a, 0xf8a0db05, 0x9a02b002, 
+    0x980080a2, 0x98009004, 0x2f50ebb1, 0x88e0d230, 0xf9b4bb48, 0x980a1004, 0xdb294281, 0xb006f8a4, 
+    0x7680f04f, 0xf2409802, 0x812011f4, 0xf8dd4630, 0xf7dda000, 0xf245fcd0, 0x46305111, 0xfcbaf7dd, 
+    0x1006f9b4, 0xf7dd4630, 0xea4ffcb5, 0x4630215a, 0xfcb0f7dd, 0x1008f9b4, 0xf7dd4630, 0x49f9fcab, 
+    0xf7dd4630, 0xe003fca7, 0x2000e7ff, 0x0000f8a9, 0xbbe09814, 0x90002000, 0xa8029001, 0xfdb9f7e6, 
+    0x0000f8d8, 0xd0281c40, 0x466f2600, 0xf8d84634, 0x9a0b0000, 0xf8551981, 0xf8520021, 0x42881021, 
+    0x1a40db10, 0x1080ebc0, 0xf7e60840, 0xa902fe09, 0xf9314ae5, 0xf1c11014, 0xf832011f, 0x43411011, 
+    0xe0000b88, 0xf8272000, 0x98090014, 0xb2241c64, 0x1c404430, 0x2c04b206, 0xf8bddbd9, 0x48db1000, 
+    0xf83df007, 0xf8bd48d9, 0x1c801002, 0xe00de000, 0xf835f007, 0xf8bd48d5, 0x1d001004, 0xf82ff007, 
+    0xf8bd48d2, 0x1d801006, 0xf829f007, 0x7680f04f, 0x15f4f240, 0x46304629, 0xfc5df7dd, 0x2122f240, 
+    0xf7dd4630, 0x981efc47, 0x46306801, 0xfc42f7dd, 0x1000f8d8, 0xf7dd4630, 0x9807fc3d, 0x46300a01, 
+    0xfc38f7dd, 0x1002f9b9, 0x4630464c, 0xfc32f7dd, 0x1004f9b4, 0xf7dd4630, 0x9804fc2d, 0x46300a01, 
+    0xfc28f7dd, 0x1006f9b4, 0xf7dd4630, 0xf9b4fc23, 0x46301008, 0xfc1ef7dd, 0x211aea4f, 0xf7dd4630, 
+    0x4cb0fc19, 0x46214630, 0xfc14f7dd, 0x46304629, 0xfc21f7dd, 0x51ddf64d, 0xf7dd4630, 0x48acfc0b, 
+    0x46307801, 0xfc06f7dd, 0x46304621, 0xfc02f7dd, 0x01c0f242, 0xf7dd0648, 0x9811fc1a, 0x80012145, 
+    0xe8bdb015, 0xe92d8ff0, 0xb0854ff0, 0x20004683, 0x4688461e, 0x489f9002, 0x489f6805, 0x28017800, 
+    0x247fd016, 0x2101489d, 0x52a0f04f, 0xf8b06800, 0xeb019000, 0x210a0a59, 0xf0f1fbb9, 0x9003b200, 
+    0x1000f9bb, 0x7080f04f, 0xfc33f7dd, 0xe028b116, 0xe7e724ff, 0xf9904892, 0x28030000, 0x2804d021, 
+    0x4890d103, 0x28017800, 0x488fd01b, 0x28166800, 0x2100d204, 0x3000f44f, 0xfc2ef7e4, 0x8800488b, 
+    0x488b9000, 0x488b7803, 0x2000f990, 0x7801488a, 0xf7fa2000, 0x2300fc7a, 0x21014888, 0xf006461a, 
+    0x4887ff98, 0xf0074649, 0x487dff73, 0x78002700, 0xd0052803, 0x49832004, 0xeb019004, 0xe1740688, 
+    0xe7f82001, 0x78004880, 0xf04f2806, 0xd3100000, 0x4a7c497e, 0x2187eb01, 0xf851e005, 0xf8423020, 
+    0x1c403020, 0x4550b200, 0x4879dbf7, 0x0027f850, 0x4978e00b, 0xe0054a73, 0x3020f851, 0x3020f842, 
+    0xb2001c40, 0xdbf74550, 0xf8566808, 0x4a6d1c08, 0x0fe0ebb1, 0x10c1dd00, 0x1c08f846, 0x1c04f856, 
+    0x0fa0ebb1, 0x1081dd00, 0x1c04f846, 0x0028f842, 0xebb16871, 0xdd000fa0, 0x60711081, 0xebb168b1, 
+    0xdd000fe0, 0x60b110c1, 0x68094957, 0xd3362912, 0x3b184b60, 0x29018859, 0xf9b3d117, 0xf8dfe004, 
+    0xeb0cc164, 0xf851018e, 0xebb22c04, 0xdd000fa0, 0xf8411082, 0x10822c04, 0x202ef84c, 0xc004f8d1, 
+    0x0fa0ebbc, 0x4662dc00, 0x88d9604a, 0xd1162901, 0x3008f9b3, 0xc12cf8df, 0x0183eb0c, 0x2c04f851, 
+    0x0fa0ebb2, 0x1082dd00, 0x2c04f841, 0xf84c1082, 0x684b2023, 0x0fa0ebb3, 0x461adc00, 0xf1a8604a, 
+    0x280a001a, 0x4843d918, 0xf9b03818, 0x391a1004, 0xd802290a, 0x29018841, 0xf9b0d00e, 0x391c1008, 
+    0xd8022908, 0x280188c0, 0x483bd006, 0x70012100, 0x3ffff1b8, 0xe006d004, 0x20014937, 0xe7f77008, 
+    0x21024835, 0xfa0f7001, 0x492ef08a, 0xeba9e007, 0xf8510200, 0xf8412022, 0x1c402020, 0x4548b200, 
+    0x481edbf5, 0x9b024a2d, 0x78816800, 0x0094f8d0, 0x0100e9cd, 0x48234922, 0xfac8f007, 0xf04f4927, 
+    0xe00a5200, 0x2000b1e0, 0x3020f851, 0xf841005b, 0x1c403020, 0x2811b200, 0x6808dbf6, 0xddf14290, 
+    0x4380f04f, 0x42986808, 0x2000dd3a, 0x2020f851, 0xf8411052, 0x1c402020, 0x2811b200, 0xe7f1dbf6, 
+    0x0000e02e, 0xdcba01f5, 0x00040dee, 0xf2035154, 0x0004055c, 0x00040230, 0x000402fa, 0x000405f8, 
+    0x00040f44, 0x000405cb, 0x00040238, 0x000402b8, 0x00040310, 0x00040234, 0x000405d9, 0xf20305ae, 
+    0x0004d178, 0x0004c178, 0x0004055e, 0x00045978, 0x00041968, 0x00040fb0, 0x00040f88, 0x00049978, 
+    0xf8512000, 0xf1022020, 0xf8415200, 0x1c402020, 0x2811b200, 0x48ffdbf5, 0x1107eb07, 0xeb002210, 
+    0x48fd0181, 0xf7f29100, 0x2000fc18, 0x99004262, 0x1020f851, 0x7180f501, 0x214ff341, 0xf82542a1, 
+    0xdd001010, 0x42914621, 0x1010f825, 0x4611da00, 0x1010f825, 0xb2001c40, 0xdde82810, 0x46012000, 
+    0x3010f835, 0xb2001c40, 0xb2094419, 0xdbf72811, 0x45989b03, 0x8c28db02, 0x84281a40, 0xfa0f49e7, 
+    0x2000fc82, 0x1147eb01, 0x0340eb05, 0x3002f9b3, 0xdd0242a3, 0x4010f821, 0x4293e006, 0xf821da02, 
+    0xe001c010, 0x3010f821, 0xb2001c40, 0xdbeb2810, 0x210148db, 0x1c7f4adb, 0x7800b27f, 0x0007f000, 
+    0x1000eb00, 0x0080eb02, 0x98046241, 0xf6ff4287, 0x48d5ae89, 0xb9a08800, 0xc350f8df, 0x4fcf2100, 
+    0xeb0c2000, 0xeb071241, 0xf8361641, 0xf8223010, 0x1c403010, 0x2810b200, 0x1c49dbf7, 0x2904b249, 
+    0xf8dfdbee, 0xf8df832c, 0xf998932c, 0x28030000, 0x2804d005, 0xf899d121, 0x28010000, 0x4fbfd11d, 
+    0x20002201, 0xeb074266, 0xeb051142, 0xf9b30340, 0x42a33002, 0xf821dd02, 0xe0064010, 0xda0242b3, 
+    0x6010f821, 0xf821e001, 0x1c403010, 0x2810b200, 0x1c52dbeb, 0x2a04b252, 0xf04fdbe3, 0xf2407480, 
+    0x462011f4, 0xf9e7f7dd, 0x51ddf64d, 0xf7dd4620, 0x49b1f9d1, 0x78094620, 0xf9ccf7dd, 0x462049af, 
+    0xf9c8f7dd, 0x01c0f242, 0xf7dd0648, 0xf998f9e0, 0x21460000, 0xd0042802, 0xd0062803, 0xd00a2804, 
+    0xf8abe00f, 0xb0051000, 0x48a5e5bb, 0x28007800, 0x2149d1f7, 0xf899e7f5, 0x28000000, 0x2801d0f1, 
+    0x210fd001, 0x214ce7ed, 0xe92de7eb, 0x489d4fff, 0x2600b087, 0x4615461f, 0x52a0f04f, 0x88046800, 
+    0xeb002001, 0x98070a54, 0x1000f9b0, 0x7080f04f, 0xf9eff7dd, 0x01c0f242, 0xf7dd0648, 0x6828f9a8, 
+    0x68296038, 0x1c4a4890, 0xf44fd004, 0x435132c8, 0xe0010c09, 0x71fff64f, 0xfd51f006, 0x7880f04f, 
+    0x11f4f240, 0xf7dd4640, 0xf243f986, 0x46403133, 0xf970f7dd, 0x46406839, 0xf96cf7dd, 0x46406829, 
+    0xf968f7dd, 0xf9b04878, 0x4640100c, 0xf962f7dd, 0x2200487e, 0xf006213f, 0x4601fd5a, 0xf7dd4640, 
+    0x487bf959, 0x46407801, 0xf954f7dd, 0x46404973, 0xf950f7dd, 0xb1b8f8df, 0x81bcf8df, 0x0000f89b, 
+    0xd1082802, 0x68004873, 0xd30d2812, 0x49724873, 0xf7e46800, 0xf89bf9b7, 0x28040000, 0xf898d104, 
+    0xb9080000, 0xfbe2f7e9, 0x9170f8df, 0x496c2500, 0xeb092000, 0xeb011245, 0x496a1345, 0x1145eb01, 
+    0xc000f8d7, 0x3ffff1bc, 0xf832d015, 0xf821c010, 0x1c40c010, 0x2810b240, 0x4628dbf2, 0xf880f7e3, 
+    0xb26d1c6d, 0xdbe22d04, 0xf8df4851, 0x7800b17c, 0xd0032804, 0xf833e006, 0xe7e8c010, 0x0000f89b, 
+    0xd0022801, 0xf7fa2001, 0xf242f90f, 0x064801c0, 0xf91df7dd, 0x23004855, 0x5000f990, 0x90002001, 
+    0xeb00484f, 0x484f1245, 0x1145eb00, 0xf7e34628, 0x4f4ff913, 0xeb092000, 0x464b1245, 0x1145eb07, 
+    0x5010f832, 0x5010f821, 0xb2401c40, 0xdbf72810, 0x78004837, 0xd1032804, 0x0000f89b, 0xd0042801, 
+    0x0000f898, 0xf7e9b908, 0x2500fd52, 0x483f2701, 0x0000f990, 0xd0184285, 0x23004839, 0xeb009700, 
+    0x48381245, 0x1145eb00, 0xf7e34628, 0x4938f8e5, 0xeb092000, 0xeb011245, 0xf8321145, 0xf8213010, 
+    0x1c403010, 0x2810b240, 0x1c6ddbf7, 0x2d04b26d, 0x4830dbdd, 0xf990492b, 0xf7e30000, 0x4a2ef828, 
+    0x48282104, 0xfb50f006, 0x78284d19, 0xd1032804, 0x0000f89b, 0xd0122801, 0x0000f898, 0x4827b918, 
+    0xf7f97007, 0x4826fd2d, 0xf7f97007, 0x4825fed3, 0x21382203, 0xfc8bf006, 0xf7e4b108, 0xf242f830, 
+    0xf04f09c0, 0x46494000, 0xf8a1f7dd, 0x28047828, 0xe039d17d, 0x000415f8, 0x00049978, 0x000414f8, 
+    0x00040f60, 0x00041708, 0x00040f98, 0x0004e6dc, 0x00040f44, 0x000405c5, 0x0004055c, 0xdcba01f5, 
+    0x000405c3, 0x000405f8, 0xf203513c, 0xf2034202, 0x0004055e, 0x00040238, 0x00167fc4, 0x000405b0, 
+    0x00041478, 0x000412c8, 0x000405cb, 0x00040290, 0x00041578, 0x00040570, 0x00041348, 0x0004028e, 
+    0x0004028f, 0xf38f007c, 0x0000f89b, 0xd15b2801, 0xf2400600, 0xf7dd11f4, 0xf04ff84e, 0xf64a7080, 
+    0xf7dd21aa, 0x49b0f837, 0x7080f04f, 0xf832f7dd, 0x4000f04f, 0xf7dd4649, 0x48adf84a, 0x680049ab, 
+    0xf8a0f7e4, 0x7080f04f, 0x11f4f240, 0xf833f7dd, 0x7080f04f, 0x21aaf64a, 0xf81cf7dd, 0xf04f49a2, 
+    0xf7dd7080, 0xf04ff817, 0x46494000, 0xf82ff7dd, 0xf7fa2001, 0x489ff819, 0x90008800, 0x7803489e, 
+    0xf990489e, 0x489e2000, 0x20007801, 0xe068e000, 0xf8cbf7fa, 0x489b2300, 0x461a2101, 0xfbe9f006, 
+    0x78004899, 0xd1022801, 0xf7fa2003, 0xf04ff9e1, 0x46494000, 0xf80bf7dd, 0x0000f898, 0xf7e9b908, 
+    0x7828fc66, 0xd14c2804, 0x0000f89b, 0x2100b9b0, 0x2000f44f, 0xf850f7e4, 0xf44f2100, 0xf7e42000, 
+    0x2100f84b, 0x2000f44f, 0xf846f7e4, 0xf44f2100, 0xf7e42000, 0x7828f841, 0xd1322804, 0x0000f89b, 
+    0xd12e2801, 0x04c02100, 0xf836f7e4, 0x4b00f04f, 0x46584649, 0xffdbf7dc, 0xf44f2100, 0xf7e42000, 
+    0x4649f82b, 0xf7dc4658, 0x2100ffd2, 0x2000f44f, 0xf822f7e4, 0x46584649, 0xffc9f7dc, 0x0000f898, 
+    0x4872b918, 0xf7f97007, 0x4871fc3b, 0xf7f97007, 0x4870fde1, 0x21382203, 0xfb99f006, 0xf7e3b108, 
+    0xf04fff3e, 0x46494b00, 0xf7dc4658, 0xf995ffb0, 0x210e0000, 0xd0162803, 0xd0142804, 0x91002301, 
+    0x9604220e, 0x96050218, 0x7602e9cd, 0x46119101, 0xfe64f7e4, 0x46584649, 0xff99f7dc, 0x7800485e, 
+    0xd00b2803, 0x220ee017, 0x23019100, 0x20809604, 0xe9cd9605, 0x91017602, 0xe7e94611, 0x9000200f, 
+    0x46022301, 0x7602e9cd, 0x96044601, 0x90019605, 0xf7e40258, 0x4649fe43, 0xf7dc4658, 0x484fff78, 
+    0xffd5f7e5, 0x494d484e, 0x0000f990, 0x0020f851, 0x3fc0f5b0, 0x4649d931, 0xf7dc4658, 0x4f49ff68, 
+    0xf8df2000, 0x4e49c124, 0xe0154a49, 0x1010f837, 0x1010f82c, 0x0140eb07, 0x3200f8b1, 0xf82c1901, 
+    0xf8363011, 0xf8223010, 0xeb063010, 0x1c400340, 0x3200f8b3, 0x3011f822, 0xdbe74550, 0x46584649, 
+    0xff45f7dc, 0x6800483b, 0xf240b138, 0x4b3a31a6, 0x2000f898, 0xf7e31e48, 0x2301ffc1, 0x4619220f, 
+    0xf7e44610, 0x4835feca, 0x0000f9b0, 0xdb1e2801, 0xb2462805, 0x2605db00, 0x0000f995, 0xd0162803, 
+    0xd0142804, 0x24004f2e, 0x3500f44f, 0x7839e00d, 0xf7e34628, 0x2100ff71, 0xf7e34628, 0x2100ff6d, 
+    0xf7e34628, 0x1c64ff69, 0x42b4b264, 0x4649dbef, 0xf7dc4658, 0x9807ff0c, 0x80012148, 0xe8bdb00b, 
+    0x4a208ff0, 0xb5102101, 0x70114604, 0xfb12f7ee, 0x2104481d, 0x200a8001, 0xf2428020, 0xe8bd01c0, 
+    0x07804010, 0xbef3f7dc, 0xdcba01f5, 0x00393870, 0x000405b0, 0x000402b8, 0x00040310, 0x00040234, 
+    0x000405d9, 0xf20305ae, 0x000405c4, 0x0004028e, 0x0004028f, 0xf38f007c, 0x0004028a, 0x00041458, 
+    0x00040570, 0x00044978, 0x00048978, 0x00045178, 0x00049178, 0x00057f70, 0xf23c80ba, 0x00040f98, 
+    0x0004028b, 0x0004024b, 0x000406ea, 0x47f0e92d, 0x7780f04f, 0x1000f9b0, 0x4614461d, 0x52a0f04f, 
+    0x46384606, 0xfef5f7dc, 0x4900f04f, 0x08c0f242, 0x46484641, 0xfeabf7dc, 0x60286820, 0x4a9c6820, 
+    0xd0041c41, 0x31c8f44f, 0x0c014348, 0xf64fe001, 0x461071ff, 0xfa53f006, 0x11f4f240, 0xf7dc4638, 
+    0xf243fe8a, 0x46383133, 0xfe74f7dc, 0x46386829, 0xfe70f7dc, 0x46386821, 0xfe6cf7dc, 0x4638498d, 
+    0xfe68f7dc, 0x498c488d, 0xf7e36800, 0x4641fedb, 0xf7dc4648, 0x2048fe7c, 0xe8bd8030, 0xe92d87f0, 
+    0xf04f4ff0, 0xf9b07580, 0x24001000, 0xb0874628, 0x52a0f04f, 0xfeadf7dc, 0x11f4f240, 0xf7dc4628, 
+    0xf649fe5a, 0x46280177, 0xfe44f7dc, 0x4628497c, 0x1000f9b1, 0xfe3ef7dc, 0x46284976, 0xfe3af7dc, 
+    0x91e0f8df, 0xf8994d78, 0xb9680000, 0x3000f44f, 0x0103f640, 0xfe3ff7dc, 0xf8d8f7e9, 0xf9952100, 
+    0x46082000, 0xf82af7e6, 0xf99546a8, 0xf8df5000, 0x2001a1bc, 0xb1b8f8df, 0xeb0a2300, 0x90001245, 
+    0x1145eb0b, 0xf7e24628, 0x4e6afe37, 0x4f6a2000, 0x1345eb06, 0x1145eb07, 0x2010f833, 0x2010f821, 
+    0xb2001c40, 0xdbf72810, 0x0000f899, 0xf7e9b908, 0x2500fa7e, 0x260146b2, 0x0000f998, 0xd0164285, 
+    0x2300485a, 0x1145eb0b, 0xeb009600, 0x46281245, 0xfe12f7e2, 0xeb0a2000, 0xeb071145, 0xf8311245, 
+    0xf8223010, 0x1c403010, 0x2810b200, 0x1c6ddbf7, 0x2d04b26d, 0xf04fdbe0, 0xf2424a00, 0x463907c0, 
+    0xf7dc4650, 0x250efdf4, 0x1b00f240, 0x23019500, 0x6402e9cd, 0x4629462a, 0x94044658, 0x94059501, 
+    0xfcacf7e4, 0x46504639, 0xfde1f7dc, 0x78004843, 0xd11f2804, 0x9500220e, 0x46112301, 0x6402e9cd, 
+    0x94044658, 0x94059501, 0xfc98f7e4, 0x46504639, 0xfdcdf7dc, 0x9500220e, 0x46112301, 0x6402e9cd, 
+    0x94044658, 0x94059501, 0xfc88f7e4, 0x46504639, 0xfdbdf7dc, 0x0000f899, 0x2100b9a0, 0xf7e62001, 
+    0xf998f9f0, 0x21002000, 0x4644200c, 0xff50f7e5, 0xf9942101, 0x46082000, 0xff90f7e5, 0x70064828, 
+    0xfa1ef7f9, 0x22034827, 0xf0062138, 0xb108f980, 0xfd25f7e3, 0x220f2301, 0x46104619, 0xfd2df7e4, 
+    0x46504639, 0xfd93f7dc, 0x88004815, 0xd11b2801, 0x491d4812, 0xf7e36800, 0xf04ffde5, 0xf2407480, 
+    0x462011f4, 0xfd66f7dc, 0x1100f241, 0xf7dc4620, 0x9906fd61, 0xf7dc4620, 0xb007fd5d, 0x49054620, 
+    0x4ff0e8bd, 0xbd56f7dc, 0xe8bdb007, 0x00008ff0, 0xf203513c, 0xdcba01f5, 0x001312d0, 0x000405b0, 
+    0x00040fa4, 0x0004055c, 0x00040290, 0x00041478, 0x000412c8, 0x000414f8, 0x00041578, 0x00040f44, 
+    0x0004028e, 0xf38f007c, 0x005a000a, 0x4ffee92d, 0x48fc4680, 0x7a80f04f, 0x4615461f, 0xf9b84654, 
+    0xf04f1000, 0x680052a0, 0x46508806, 0xfd81f7dc, 0x01c0f242, 0xf7dc0648, 0xf240fd3a, 0x462011f4, 
+    0xfd29f7dc, 0x51ddf64d, 0xf7dc4620, 0xf8dffd13, 0x462093b8, 0x1000f899, 0xfd0cf7dc, 0x462049eb, 
+    0xfd08f7dc, 0xb3a8f8df, 0x4aea2400, 0xfb042300, 0xeb0bf006, 0x91020140, 0x0040eb02, 0x22014621, 
+    0x2000e9cd, 0x461a2001, 0xfabef7e2, 0xb2641c64, 0xdbea2c04, 0x49e048e1, 0xf7e36800, 0x2000fd63, 
+    0x0100f640, 0x46024603, 0xf7e79000, 0x48dcf8ad, 0x90008800, 0x780348db, 0xf99048db, 0x48db2000, 
+    0x20007801, 0xfda1f7f9, 0x48d92300, 0x461a2101, 0xf8bff006, 0x780048d7, 0xd1022801, 0xf7f92003, 
+    0x2100feb7, 0xf7e44608, 0x2000fe4d, 0xfe6ef7f9, 0x60386828, 0x48d06829, 0xd0041c4a, 0x32c8f44f, 
+    0x0c094351, 0xf64fe001, 0xf00671ff, 0xf240f888, 0x465614f4, 0x46504621, 0xfcbdf7dc, 0x3133f243, 
+    0xf7dc4630, 0x6839fca7, 0xf7dc4630, 0x6829fca3, 0xf7dc4630, 0x4db5fc9f, 0x46294630, 0xfc9af7dc, 
+    0x46304621, 0xfca7f7dc, 0x51ddf64d, 0xf7dc4630, 0xf899fc91, 0x464c1000, 0xf7dc4630, 0x4629fc8b, 
+    0xf7dc4630, 0xf44ffc87, 0x21003500, 0xf7e34628, 0x2100fcf3, 0xf7e34628, 0x2003fcef, 0xfc84f7f9, 
+    0x01c0f242, 0xf7dc0648, 0x48acfc92, 0x0000f990, 0xd0082805, 0xd0062803, 0x78202505, 0x3680f44f, 
+    0x2400b118, 0x250fe014, 0xf7e9e7f7, 0x2400f8e0, 0x2100e005, 0xf7e34630, 0x1c64fccf, 0x42acb264, 
+    0xe007dbf7, 0x46302100, 0xfcc6f7e3, 0xb2641c64, 0xdbf742ac, 0xf8a82147, 0xe8bd1000, 0xe92d8ffe, 
+    0xf04f5ffc, 0xf9b07680, 0xf04f1000, 0x468152a0, 0xf7dc4630, 0xf242fc9e, 0x064801c0, 0xfc57f7dc, 
+    0xf2404880, 0x680011f4, 0x08448800, 0xf7dc4630, 0xf64dfc42, 0x463051dd, 0xfc2cf7dc, 0x46304d7a, 
+    0xf7dc7829, 0x4979fc27, 0xf7dc4630, 0x7828fc23, 0x4883b948, 0xb9307800, 0xf64011f0, 0xf7dc0103, 
+    0xf7e8fc2a, 0x2003fec3, 0xfc1ef7f9, 0x0800f04f, 0x250046ab, 0x7830465e, 0x2000b120, 0xfd1bf7f7, 
+    0xe001b978, 0xe7f92001, 0x2d641c6d, 0x4875dbf3, 0xb3586800, 0x21c2f240, 0x78324b73, 0xf7e31e48, 
+    0x4872fc9d, 0x4d6c220d, 0x0100f246, 0xf9903daa, 0xb2830000, 0xf0054628, 0x2300ffdc, 0x22054628, 
+    0xf0052120, 0x2301ffd6, 0x22054628, 0xf0052120, 0xf04fffd0, 0xf2480a00, 0x46550700, 0x220f485e, 
+    0x38784639, 0xffd3f005, 0xe001b940, 0xe18d210f, 0x42bd1c6d, 0xf1badbf2, 0xd0400f00, 0x22004856, 
+    0x71fff643, 0xf0053878, 0x07c0ffc2, 0xf242d07e, 0x064801c0, 0xfbdbf7dc, 0x7580f04f, 0x11f4f240, 
+    0xf7dc4628, 0xf241fbc8, 0x46281111, 0xfbb2f7dc, 0xa13cf8df, 0xf99a4628, 0xf7dc1000, 0x493bfbab, 
+    0xf7dc4628, 0x2500fba7, 0xf89b46b3, 0x28010000, 0x4848d004, 0x0000f990, 0xd04a4285, 0x27004e46, 
+    0x20019700, 0x4629463a, 0xf7e26833, 0xf89afa5d, 0x68310000, 0xd01a2801, 0x800f1e60, 0xf9b9e02e, 
+    0xf04f1000, 0xf04f52a0, 0xf7dc7080, 0x4834fbe2, 0x28047800, 0x4833d00a, 0x28006800, 0xf240d006, 
+    0x4b3121c4, 0x1e487832, 0xfc18f7e3, 0xeb01e0db, 0xf8200044, 0x20007c02, 0xe0051e62, 0x0340eb01, 
+    0xf821885b, 0x1c403010, 0xdbf74290, 0xeb01e008, 0xf8320240, 0xf8212c02, 0x1e402010, 0xdcf62800, 
+    0x23006830, 0x0700e9cd, 0x461a2001, 0xf7e24629, 0x1c6df948, 0x2d04b26d, 0x4e1fdba7, 0x462f2500, 
+    0x22009700, 0x46104629, 0xe0006833, 0xf7e2e0b1, 0xf89afa0b, 0x68310000, 0xd02f2801, 0x800f1e60, 
+    0x0000e043, 0x000405f8, 0x0004055c, 0xdcba01f5, 0x00049178, 0x00048978, 0x00393870, 0x000405b0, 
+    0x000402b8, 0x00040310, 0x00040234, 0x000405d9, 0xf20305ae, 0x000405c4, 0xf203513c, 0x0004028a, 
+    0x00040f44, 0x00057f70, 0xf23c80ba, 0x00040570, 0x00040f8a, 0x00040290, 0x00040230, 0x0044eb01, 
+    0x7c02f820, 0x1e632000, 0xeb01e005, 0x88520240, 0x2010f821, 0x42981c40, 0xe008dbf7, 0x0240eb01, 
+    0x2c02f832, 0x2010f821, 0x28001e40, 0x6830dcf6, 0xe9cd2300, 0x461a0700, 0x46184629, 0xf8e1f7e2, 
+    0xb26d1c6d, 0xdb9b2d04, 0x0000f89b, 0xf44fbbe0, 0xf6403000, 0xf7dc0103, 0xf7e8faee, 0x48c4fd87, 
+    0xf9902200, 0x97000000, 0x46056833, 0x20014601, 0xf99af7e2, 0x0000f89a, 0x28016831, 0x1e60d002, 
+    0xe016800f, 0x0044eb01, 0x7c02f820, 0x1e622000, 0xeb01e005, 0x885b0340, 0x3010f821, 0x42901c40, 
+    0xe008dbf7, 0x0240eb01, 0x2c02f832, 0x2010f821, 0x28001e40, 0x6830dcf6, 0xe9cd2300, 0x20010700, 
+    0x4629461a, 0xf89df7e2, 0x0000f89a, 0xf88a4240, 0xf89b0000, 0xb9080000, 0xff19f7e8, 0x01c0f242, 
+    0xf7dc0648, 0xf108fab4, 0xf1b80801, 0xf6ff0f04, 0xf7f7ae80, 0x4c9ffc13, 0x68202100, 0x2038f890, 
+    0x003af9b0, 0xfcb1f7e4, 0xf9b06820, 0xf7e5003e, 0x2301fe1f, 0x220f4898, 0x463103de, 0xfe69f005, 
+    0x78204c96, 0xd0052804, 0x0000f89b, 0x2801465d, 0xe01ad016, 0x2500f44f, 0x46282100, 0xfadcf7e3, 
+    0x46282100, 0xfad8f7e3, 0x7809498d, 0xd1032904, 0x46282100, 0xfad0f7e3, 0xf7f92004, 0xe011fa65, 
+    0xf2422100, 0xf7e30000, 0x2004fac7, 0xfa5cf7f9, 0x46302100, 0xfac0f7e3, 0xb9187828, 0xfc15f7e4, 
+    0xfec5f7e8, 0x28047820, 0x2149d004, 0x1000f8a9, 0x9ffce8bd, 0xe7f92148, 0x4ff0e92d, 0x1000f9b0, 
+    0xb0892600, 0x52a0f04f, 0x7080f04f, 0xfa91f7dc, 0x01c0f242, 0xf7dc0648, 0xf8dffa4a, 0xf649a1c8, 
+    0x4c6b4540, 0x0000f89a, 0xf44fb968, 0xf6403000, 0xf7dc0103, 0xf7e8fa30, 0x2100fcc9, 0x2000f994, 
+    0xf7e54608, 0x2003fc1b, 0xfa1ef7f9, 0xf99446a1, 0x48654000, 0xf04f2300, 0xf8cd0b04, 0xeb00b000, 
+    0x48621244, 0x1144eb00, 0xf7e24620, 0xf242fa25, 0x064801c0, 0xfa1bf7dc, 0x20004f5d, 0xc174f8df, 
+    0x1344eb07, 0x1144eb0c, 0xf83346e0, 0xf8212010, 0x1c402010, 0x2810b240, 0xf89adbf6, 0xb9080000, 
+    0xfe65f7e8, 0x46bb2400, 0xf9994647, 0x42840000, 0x2004d018, 0x484c9000, 0xeb002300, 0x484b1244, 
+    0x1144eb00, 0xf7e24620, 0x2000f9f7, 0x1144eb0b, 0x1244eb07, 0x3010f831, 0x3010f822, 0xb2401c40, 
+    0xdbf72810, 0xb2641c64, 0xdbde2c04, 0x01c0f242, 0xf7dc0648, 0x2047f9dc, 0x0018f8ad, 0x6802483e, 
+    0xf9904836, 0xa8061000, 0xfd69f7ff, 0x0000f89a, 0xb9a02701, 0x20012100, 0xfe03f7e5, 0x2000f999, 
+    0x200c2100, 0xf7e5464c, 0x2101fb63, 0x2000f994, 0xf7e54608, 0x4831fba3, 0xf7f87007, 0x4830fe31, 
+    0x21382203, 0xfd93f005, 0xf7e3b108, 0x46b9f938, 0x24004f2c, 0x080ef04f, 0x1a00f240, 0x8000f8cd, 
+    0x4650220e, 0x46112301, 0x9602e9cd, 0xf8cd9604, 0x96058004, 0xf862f7e4, 0xdd0e2c00, 0xf7e54821, 
+    0x6838f9f6, 0xd20842a8, 0x42a86878, 0x68b8d205, 0xd20242a8, 0x42a868f8, 0x1c64d303, 0x2c10b264, 
+    0x4818dbdc, 0xf9e3f7e5, 0x220f2301, 0x46104619, 0xf913f7e4, 0x68004814, 0xd8052811, 0x2000b009, 
+    0x4ff0e8bd, 0xbe24f7e3, 0xe8bdb009, 0x00008ff0, 0x00040290, 0x000405f8, 0xf2035092, 0x00040f44, 
+    0x0004028a, 0x0004055c, 0x00041478, 0x000412c8, 0x000414f8, 0x00041578, 0x00040f64, 0x0004028e, 
+    0xf38f007c, 0x00041458, 0x00040238, 0x47f0e92d, 0x35e0f240, 0x4617461e, 0x22054688, 0x48134604, 
+    0xe9dd4629, 0xf0059a08, 0xb2c0fd22, 0x011ff008, 0x1040ea05, 0xf2404301, 0xea004000, 0x43012087, 
+    0x0000f640, 0x20c6ea00, 0x48094301, 0x41a0f441, 0x00c4eb00, 0xfcddf005, 0xea4a4805, 0x1d004109, 
+    0x00c4eb00, 0x47f0e8bd, 0xbcd3f005, 0xf23c821e, 0xf1000200, 0x5ffce92d, 0xb400f8df, 0x8e804604, 
+    0x1215f240, 0xf04f4efe, 0x4dfe0800, 0xf8df4290, 0xf2a093f8, 0xf8df1115, 0xf8dba3f4, 0xd0123000, 
+    0x28dfdc23, 0xdc0fd0fb, 0x2880b3a0, 0x2881d03e, 0x28ded046, 0x48f6d17e, 0x46312200, 0xf0016800, 
+    0x1d40f94e, 0xe284d077, 0x7f80f5b0, 0xf5a0d074, 0x38017080, 0x2813d0f7, 0x49e9d16c, 0x46182200, 
+    0xf93df001, 0xd0681d40, 0x48eae273, 0x68002977, 0xdc08d07e, 0xd07c291f, 0xd0e42920, 0xd0792933, 
+    0xd1572934, 0x2978e265, 0x2997d0dd, 0x2998d073, 0xe25ed150, 0x49dae7ff, 0x32fff04f, 0x0008f8da, 
+    0xf94cf001, 0xd1071d01, 0xe21b2080, 0x220049d4, 0x0008f8da, 0xf942f001, 0xd01f1d41, 0xd1ea2801, 
+    0x1000f9b6, 0xd1e6296d, 0x17d0074a, 0xf8f1f7dc, 0x46528870, 0x0000f8aa, 0x1004f9b6, 0x1002f8aa, 
+    0x0006f9b6, 0x0004f8aa, 0x0543b1c0, 0x4bcad40a, 0xf993782f, 0x431f3000, 0xe00fd002, 0xe1f12081, 
+    0xd50b05c0, 0x46400689, 0x8000f8a2, 0xf040d502, 0xe0010020, 0x0010f040, 0x0000f8aa, 0x0000f899, 
+    0xd00b2801, 0x220648bd, 0xf0052140, 0xb150fc60, 0xe0092702, 0xe04ae1d7, 0xe0abe089, 0x464049b8, 
+    0x8000f881, 0x2700e011, 0x220d48b4, 0x0100f242, 0xfc4df005, 0x2001b100, 0x2f014307, 0x2000d01e, 
+    0x2f0249af, 0xd01b7008, 0x49ae2000, 0xe0037008, 0xe0cae187, 0xe1ade0ec, 0x0000f9ba, 0x04c24651, 
+    0xf420d52c, 0xf2415080, 0xf8aa0700, 0x220c0000, 0x463948a5, 0xfc2bf005, 0xe01ab120, 0xe7df2001, 
+    0xe7e22001, 0x780048a1, 0x4aa1b198, 0x46392005, 0xf87ff7dc, 0x8030203b, 0x22004895, 0x68004990, 
+    0xf88df001, 0xf47f1d01, 0x20deaf3c, 0x20dfe18a, 0x4a97e188, 0xf2412005, 0xe1b80101, 0x06824f95, 
+    0xf020d55b, 0x80080020, 0x0002f89a, 0x06804a90, 0x2005d537, 0x0120f242, 0xf85bf7dc, 0xf887488e, 
+    0x78008000, 0xd00f2801, 0x7800488c, 0xd00b2801, 0x8800488b, 0xd0072801, 0x7800488a, 0xd0032801, 
+    0x7800487d, 0xd1052801, 0xb9187828, 0x0000f899, 0xd0742800, 0x80302071, 0x22004971, 0x0000f8db, 
+    0xf84df001, 0xd1071d01, 0x1000f240, 0x496ce14a, 0x46182200, 0xf843f001, 0xd1601d40, 0x1001f240, 
+    0x2120e140, 0xf7dc2005, 0x7828f824, 0xd0e02801, 0x0000f899, 0xd0dc2800, 0x80302007, 0x22004960, 
+    0x0000f8db, 0xf82bf001, 0xf47f1d01, 0xf240aeeb, 0xe1271014, 0x1015f240, 0x06c2e124, 0xf020d562, 
+    0x80080010, 0x0002f89a, 0x06c04a61, 0x2005d538, 0x0110f242, 0xfffdf7db, 0xf887485f, 0x78008000, 
+    0xd00f2801, 0x7800485d, 0xd00b2801, 0x8800485c, 0xd0072801, 0x7800485b, 0xd0032801, 0x7800484e, 
+    0xd1052801, 0xb9187828, 0x0000f899, 0xd0162800, 0x80302070, 0x22004942, 0x0000f8db, 0xffeff000, 
+    0xd1071d01, 0x1034f240, 0x493de0ec, 0x46182200, 0xffe5f000, 0xd1021d40, 0x1035f240, 0xe06be0e2, 
+    0x20052110, 0xffc5f7db, 0x28017828, 0xf899d064, 0x28000000, 0x2007d060, 0x49318030, 0xf8db2200, 
+    0xf0000000, 0x1d01ffcc, 0xf240d107, 0xe0c91048, 0x2200492b, 0xf0004618, 0x1d40ffc2, 0xf240d14c, 
+    0xe0bf1049, 0xd5480442, 0x4080f420, 0xf8ba8008, 0x4a2f0002, 0xd5770440, 0x20052102, 0xff99f7db, 
+    0xf8872201, 0x21008000, 0xf7e42002, 0x2200fcc4, 0x46112001, 0xfcbff7e4, 0x7800482b, 0x492bb178, 
+    0x7809482b, 0xe9cd7800, 0x482a0100, 0x482a7801, 0x482a7803, 0x482a7802, 0xf7e67800, 0x481ffb89, 
+    0x7800491d, 0x1000f991, 0x49134308, 0x1000f991, 0xd1034308, 0xf9b4f7dd, 0xfae3f7f6, 0x88004821, 
+    0x7828b150, 0x4806b940, 0x30102173, 0x21018001, 0x49187081, 0xe0387809, 0xe076e089, 0x00040734, 
+    0x0004e75c, 0x00040285, 0x00040284, 0x000411b4, 0x00040f1c, 0x00040f10, 0x0004027d, 0xf38fffc0, 
+    0x00040240, 0x00040241, 0xf203902c, 0x00040245, 0xcccc0000, 0x00040600, 0x00040581, 0x00040583, 
+    0x0004027e, 0x00040282, 0x00040535, 0x000405ff, 0x000405fe, 0x0004028a, 0x000405fd, 0x000405fc, 
+    0x00040534, 0x00040364, 0x70c1e014, 0x48434601, 0x68002200, 0xff33f000, 0xd1061d01, 0x108cf240, 
+    0x493fe030, 0xf0002200, 0x1d40ff2a, 0xf240d161, 0xe027108d, 0x20052103, 0xff0bf7db, 0xf950f7dd, 
+    0xfa95f7f6, 0x88004837, 0x7828b388, 0x4834bb78, 0x22002173, 0x49348001, 0x8002f880, 0x70c17809, 
+    0x482e4601, 0xf0006800, 0x1d01ff0a, 0xf240d106, 0xe00710ac, 0x2200492a, 0xff01f000, 0xd1381d40, 
+    0x10adf240, 0xe8bd86a0, 0x07429ffc, 0xf020d526, 0xf8aa0004, 0xf8990000, 0x28010000, 0x4823d104, 
+    0xf0308800, 0xd0030040, 0x21084a21, 0xe020e01e, 0x21044f1f, 0x463a4608, 0xfecbf7db, 0x2202481d, 
+    0xf0052104, 0x2801fa64, 0x2004d005, 0xfe7df7e2, 0x463a2106, 0x2105e00a, 0xe007463a, 0xd5080602, 
+    0x210c4a13, 0x0080f020, 0x0000f8aa, 0xf7db2004, 0xf8bafeb0, 0x28000000, 0xae09f47f, 0x2200e59b, 
+    0xb5102101, 0x5073f2af, 0xfd04f000, 0x20042108, 0xfe62f000, 0x60884908, 0x0000bd10, 0x00040f10, 
+    0x0004e76c, 0x00040364, 0x0004028a, 0x00040288, 0xcccc0000, 0xf2039026, 0x000411b4, 0x4ff0e92d, 
+    0x4605b09f, 0xf8df2400, 0xf88da42c, 0x9418406c, 0x8e80941c, 0x7f62f5b0, 0xdc05d070, 0x28d0b160, 
+    0x28d1d016, 0xe01ed16b, 0x7040f5a0, 0xd0673889, 0xd07d28b7, 0xd16228b8, 0xf04f49fe, 0xf8da32ff, 
+    0x3124001c, 0xfeaaf000, 0xd1081d01, 0xe38220d0, 0x220049f8, 0x001cf8da, 0xf0003124, 0x1d41fe9f, 
+    0x2801d011, 0x48f3d1e8, 0x88003024, 0xd1e32865, 0x230148f1, 0x21042202, 0xf9dbf005, 0x780048ef, 
+    0xd0022802, 0x20d1e012, 0x48ede365, 0x28017800, 0xf8dfd10c, 0xf89bb3b0, 0xb1e00000, 0xd0242801, 
+    0xd02e2802, 0xd06d2803, 0x4000f88b, 0x48e62208, 0xf0050151, 0x2800f9cc, 0xf8bad065, 0x210a0008, 
+    0xb2801c40, 0x0008f8aa, 0xf2f1fbb0, 0x0012fb01, 0xd06e2800, 0xf7e8e1e3, 0x2001fc8a, 0x0000f88b, 
+    0x700448da, 0x700448da, 0xf7e8e7e0, 0xb118fcc2, 0xf88b2102, 0xe7d91000, 0xe05c2001, 0xe3f3e32c, 
+    0xf7e8e244, 0xb3e0fcc3, 0xfc61f7e8, 0xf44f2100, 0xf7e23080, 0x4bcffe11, 0x4acf2000, 0xeb022600, 
+    0xe9c101c0, 0xeb036600, 0xe9c101c0, 0xe0006600, 0x1c40e3fb, 0xdbf12804, 0xa8192700, 0xfc67f7e8, 
+    0xf7e84668, 0x2600fc7d, 0xf830a819, 0xf0070016, 0x4bc2f9ab, 0xf0062200, 0x4abeffdb, 0x03c6eb02, 
+    0xcb0c4699, 0xff18f006, 0x0100e9c9, 0x4bbb4668, 0x00c6eb00, 0xe9d02200, 0xf0060100, 0x4ab6ffc9, 
+    0xe017e002, 0xe181e01a, 0x03c6eb02, 0xcb0c4699, 0xff02f006, 0x2e041c76, 0x0100e9c9, 0x2100dbd4, 
+    0x2000f240, 0xfdc8f7e2, 0x2f641c7f, 0x2003dbc5, 0xe09ee001, 0xf88b2002, 0xe7770000, 0xab082000, 
+    0x2600aa10, 0x01c0eb02, 0x6600e9c1, 0x01c0eb03, 0x28041c40, 0x6600e9c1, 0x2700dbf3, 0xf7e8a819, 
+    0x4668fc16, 0xfc2cf7e8, 0xa8192600, 0x0016f830, 0xf95af007, 0x22004b99, 0xff8af006, 0xeb02aa08, 
+    0x469903c6, 0xf006cb0c, 0xe9c9fec7, 0x46680100, 0xeb004b92, 0x220000c6, 0x0100e9d0, 0xff78f006, 
+    0xeb02aa10, 0x469903c6, 0xf006cb0c, 0x1c76feb5, 0xe9c92e04, 0xdbd80100, 0xf2402100, 0xf7e22000, 
+    0x1c7ffd7b, 0xdbc92f64, 0x463e2700, 0xeb00a808, 0xe9d000c6, 0x487f2300, 0x01c6eb00, 0x0100e9d1, 
+    0x911d4681, 0xfb7cf007, 0xf8aaf007, 0xda002800, 0xf0074240, 0x9b1df902, 0xf006464a, 0x4684ff49, 
+    0xe9d04877, 0x46602300, 0xfa5cf007, 0x496fd206, 0x28ff7808, 0x1c40d001, 0x27017008, 0xeb00486e, 
+    0xe9d000c6, 0xa8102300, 0x01c6eb00, 0x0100e9d1, 0xff2ef006, 0x486b4684, 0x2300e9d0, 0xf0074660, 
+    0xd206fa41, 0x78084962, 0xd00128ff, 0x70081c40, 0x1c762701, 0xdbb92e04, 0xf43f2f00, 0xf7e8af68, 
+    0x2100fb86, 0x3000f44f, 0xfd26f7e2, 0xfb6ff7e8, 0x485de760, 0x28027800, 0x485cd17e, 0xf87cf005, 
+    0xf006b2c6, 0x280a000f, 0xf7f6d177, 0xf8dff8e4, 0x28019160, 0x4857d038, 0x37244f54, 0x0000f990, 
+    0xd0432803, 0xd0412805, 0xd03f2804, 0x46382300, 0x21102204, 0xf87df005, 0x301e484c, 0xf85cf005, 
+    0x484a4607, 0xf005301c, 0xea47f857, 0x48474b00, 0xf0053022, 0x4607f851, 0x30204844, 0xf84cf005, 
+    0x4000ea47, 0x20039000, 0x1f16ebb0, 0xf8dad120, 0x46581014, 0xf8a5f7f6, 0x1018f8da, 0x98004607, 
+    0xf89ff7f6, 0xe0244438, 0x406cf88d, 0xf89a27fe, 0x29fe1000, 0xf89ad107, 0x42860002, 0xf899d103, 
+    0x28010000, 0xf04fd13c, 0xe06632ff, 0xe7be2301, 0xebb02001, 0xd1031f16, 0x1014f8da, 0xe0064658, 
+    0xebb02002, 0xd1051f16, 0x1018f8da, 0xf7f69800, 0x9018f878, 0xf8caa91b, 0x9800b014, 0x0018f8ca, 
+    0xf7f69818, 0x4607f840, 0x0002f89a, 0xd14342b0, 0x0000f899, 0xe0012801, 0xe017e051, 0xf89ad03c, 
+    0x428f1000, 0xf89dd105, 0xf89a106c, 0x42810001, 0x480ad006, 0x9a18b271, 0x0000f990, 0xfc75f7f5, 
+    0x7000f88a, 0x106cf89d, 0x1001f88a, 0x6002f88a, 0x0000e035, 0x000411c0, 0xf23c8318, 0x0004028a, 
+    0x00040360, 0x0004034c, 0xf38f2002, 0x0004034d, 0x0004034e, 0x0004e1a0, 0x0004e1c0, 0x40590000, 
+    0x00040350, 0x00040358, 0x00040582, 0xf23c80d2, 0x00040341, 0x00040244, 0xb2719a18, 0xf99048f8, 
+    0xf7f50000, 0xf889fc42, 0xe7c94000, 0x4008f8aa, 0xf88a21fd, 0xf88a1002, 0xf88a1000, 0x220f1001, 
+    0xf24848f0, 0xf0040100, 0xbb88ffd2, 0x0010f8ba, 0x1c404656, 0xf8aab280, 0x07010010, 0xf000d00a, 
+    0x2801000f, 0x2802d00f, 0x2803d014, 0x2804d019, 0xe026d01f, 0xf0032000, 0xfa0ff821, 0x48e2f880, 
+    0xf188fa1f, 0x2001e01b, 0xf8b9f003, 0x48deb281, 0xe0141c80, 0xf0032004, 0xb281f811, 0x1d0048da, 
+    0x2005e00d, 0xf80af003, 0x48d7b281, 0xe0061d80, 0x2006e031, 0xf802f003, 0x48d3b281, 0xf0043008, 
+    0x48d2ff6e, 0x4fd349d2, 0x28017800, 0x680ad002, 0xd1142a01, 0x07127c32, 0x4bcfd11d, 0xd1022801, 
+    0x45b0681e, 0x6809da11, 0xd00a2901, 0x454149cb, 0x2801da11, 0xf647d028, 0x454070ff, 0x2300dd0b, 
+    0x49c7e004, 0x45886809, 0x2301dc1a, 0x22014638, 0xf0042102, 0x48c3ff5e, 0x0000f990, 0xd0182803, 
+    0xd0162805, 0xd0142804, 0x400ef8aa, 0x48be2723, 0x28017800, 0xf89ad07e, 0x29001003, 0xe1b4d17b, 
+    0x68124aba, 0xe7d24411, 0x681849b9, 0x1a406809, 0xf8bae7d3, 0x48b7100e, 0xf8aa1c49, 0xf004100e, 
+    0x4606ff1b, 0xd5210600, 0x780048b3, 0xd0052801, 0xf980f7f8, 0x780048b1, 0xe014b180, 0x220348b0, 
+    0xf0042138, 0xb108ff34, 0xe0002007, 0xf8ba201f, 0x4201100e, 0xf7f8d10a, 0xe007f96d, 0x780048a9, 
+    0x2001b108, 0x2000e000, 0xf959f7e8, 0xd50c0730, 0x780048a5, 0xd1062801, 0x780048a4, 0xf89ab918, 
+    0x06c0000e, 0xf7f7d101, 0x0430ffab, 0xf8bad515, 0x4657000e, 0xd1010580, 0xfab0f7e2, 0xf0107bb8, 
+    0xd10a0f05, 0x78384f9a, 0xf7e2b138, 0x4999faa8, 0x703c2001, 0xf7e27008, 0x4897faa1, 0x28017800, 
+    0x4896d158, 0x28017800, 0xf89ad154, 0x4a940005, 0xb2c01c40, 0x0005f88a, 0x42907812, 0x4891d94a, 
+    0xf88a46d1, 0x78004005, 0xd02a2801, 0xd0282802, 0xe001488d, 0xe06ee06b, 0xfeaef004, 0x488a4607, 
+    0xf0041c80, 0xf8d9fea9, 0xea471020, 0x4f874000, 0x42884b87, 0x783ad005, 0x40912101, 0x4311681a, 
+    0x78396019, 0x1c494a83, 0x7039b2c9, 0x42917812, 0x703cd300, 0xf8c92100, 0x27010020, 0x4608681b, 
+    0x4879e010, 0xf0041f00, 0x4607fe87, 0x1e804876, 0xfa07e7d7, 0xea1cfc00, 0xd0010f03, 0xb2c91c49, 
+    0xb2c01c40, 0xd3f44290, 0x78004873, 0xd9014281, 0x901c2001, 0xd5090570, 0x000ef89a, 0xd1050700, 
+    0x1f80485c, 0xfe68f004, 0xd10307c0, 0x2801981c, 0xaf2cf47f, 0x901c2000, 0xfc1bf7fb, 0x21434867, 
+    0x80012200, 0x48664601, 0xf0006800, 0x1d01faf8, 0xf240d108, 0xe0f43088, 0x22004861, 0x6800495f, 
+    0xfaedf000, 0xd1e31d40, 0x3089f240, 0xf89ae0e9, 0x46560003, 0xf89ab1a0, 0x46560003, 0xd0312801, 
+    0xfef2f7e6, 0x71b02121, 0x28002222, 0x000af9b6, 0x2823d051, 0x2822d02f, 0x2821d034, 0xe041d039, 
+    0x1c407930, 0x7130b2c0, 0xd3172828, 0x2205484d, 0xf0042120, 0xb928fe4c, 0x384e482e, 0xfe1cf004, 
+    0xd00c07c0, 0x28238970, 0x2300d007, 0x22018177, 0x46184619, 0xf7f79400, 0x7134f8e3, 0x2001e097, 
+    0xe7fa70f0, 0xf7e62003, 0x2001fbbf, 0xfe4cf7e6, 0x70f02002, 0x2300e08b, 0x22018172, 0x46104619, 
+    0xe00d9400, 0x81712300, 0x46192201, 0x94002002, 0x2020e006, 0x23008170, 0x22019400, 0x20034619, 
+    0xf8bef7f7, 0x1c4089b0, 0x4812b281, 0x384c81b1, 0xfde5f004, 0x2820e061, 0x2821d004, 0x2822d009, 
+    0xe05ad053, 0x81712300, 0x46192201, 0x94002002, 0x2300e051, 0x22018172, 0x46104619, 0xe04a9400, 
+    0x0004028a, 0xf2020000, 0xf23d0142, 0x000402fb, 0x00040304, 0xf20351da, 0x000402fc, 0xffff8001, 
+    0x00040308, 0x00040244, 0x00040600, 0x0004030c, 0x00040300, 0xf23c80b8, 0x0004028f, 0x0004055c, 
+    0xf38f007c, 0x000402c3, 0x0004028e, 0x00040f88, 0x000402a8, 0x000402a9, 0x000402cf, 0x000402ce, 
+    0x000405bf, 0x000405d9, 0xf2036116, 0x000405bc, 0x000405b8, 0x000405bd, 0x000405be, 0x000411e4, 
+    0x00040f7c, 0xf38f2034, 0x2300e02c, 0x22018177, 0x46184619, 0xf7f79400, 0x2002f853, 0xfb34f7e6, 
+    0xf7e62000, 0x70f4fdc1, 0xf88ae001, 0x21294004, 0x22004815, 0x46018001, 0x68004814, 0xfa0ff000, 
+    0xd1091d01, 0x4040f240, 0xe7ffe00b, 0x2200480f, 0x6800490d, 0xfa03f000, 0xf47f1d40, 0xf240ab7d, 
+    0x86a84041, 0xe8bdb01f, 0x22008ff0, 0xb5102101, 0x1057f6af, 0xf83ef000, 0x200a2108, 0xf99cf000, 
+    0x39244901, 0xbd1061c8, 0x000411e4, 0x00040f00, 0xb5082008, 0xfa97f7e2, 0x90002000, 0x46032201, 
+    0x20084601, 0xfad4f7e2, 0x20084908, 0xfa9af7e2, 0xf7e24807, 0x2008faf0, 0xfa99f7e2, 0xf2462201, 
+    0xe8bd11a8, 0x20034008, 0xb994f7e2, 0x00025ed0, 0xf0001184, 0xf8bcf000, 0x8e80e7fc, 0xd1012800, 
+    0xbcf6f005, 0x22004770, 0xf2af4611, 0xf0000011, 0x0000b801, 0x47f0e92d, 0x460e4691, 0x20384682, 
+    0xfc20f000, 0xd0440004, 0xf8df4f86, 0x6838821c, 0x2500b9d8, 0xeb05603c, 0xeb080185, 0xf0000081, 
+    0x1c6df905, 0xd3f62d02, 0x3028487f, 0xf8fef000, 0x303c487d, 0xf8faf000, 0x3050487b, 0xf8f6f000, 
+    0x30284879, 0x30146178, 0x2e0261b8, 0x2601d300, 0x86a02000, 0xa000f8c4, 0xe9c41d20, 0xf000690b, 
+    0xf104f8f0, 0xf0000018, 0x6124f8ec, 0x000af1c6, 0x61a06264, 0x68796ae0, 0xd9004288, 0xeb006078, 
+    0xeb080180, 0x1d210081, 0xf8def000, 0xe8bd2001, 0xf04f87f0, 0xe7fa30ff, 0x4d62b570, 0x68a9460e, 
+    0x6828180c, 0xf0001d00, 0x6829f8f5, 0x68a8604c, 0xd2014284, 0xe00069a8, 0x1d096968, 0xf8d2f000, 
+    0xd0062e00, 0x46306829, 0x4070e8bd, 0xf0003118, 0xbd70b8c9, 0xf000b570, 0x4d52fb2d, 0x1a4068e9, 
+    0xe02f6128, 0x0101f1a1, 0x1c406129, 0xd10360a8, 0x1005e9d5, 0x0105e9c5, 0x69684e4b, 0xb1f16801, 
+    0x68c468c0, 0x6860e01c, 0x428868a9, 0xb672d81a, 0xf0001d20, 0x6aa0f8bf, 0xf104b118, 0xf0000018, 
+    0xb662f8b9, 0x68696ae0, 0xd9004288, 0xeb006068, 0x1d210080, 0x0080eb06, 0xf886f000, 0x2400e7dd, 
+    0xd1e02c00, 0x68a86929, 0xd1cb2900, 0xbd7060e8, 0xf000b510, 0xf7fff840, 0x4932ffbd, 0x68484a32, 
+    0x2800e003, 0x1e40d01b, 0xeb006048, 0xf8520380, 0x2b003023, 0xeb00d0f5, 0xeb020080, 0x68420080, 
+    0xf1006852, 0x60420308, 0xd101429a, 0x60426852, 0x600868d0, 0x6b016802, 0x4010e8bd, 0xbd104710, 
+    0x6801b570, 0x68c0b111, 0xe00068c4, 0xf1042400, 0x46050018, 0xf86ef000, 0x4629481b, 0xf0003050, 
+    0x4918f843, 0x68096ae0, 0x42886ac9, 0x2001d301, 0x2000bd70, 0xe92dbd70, 0x4d1341f0, 0x4f124e11, 
+    0xe01a3550, 0x6828b672, 0x68e8b110, 0xe00068c4, 0xf1042400, 0xf0000018, 0xb662f84d, 0xf0001d20, 
+    0x6ae0f849, 0x42886871, 0x6070d900, 0x0080eb00, 0xeb071d21, 0xf0000080, 0x6828f817, 0xd1e12800, 
+    0x81f0e8bd, 0x000411ec, 0x0004e778, 0x32fff04f, 0x0108f100, 0x1201e9c0, 0x610160c1, 0x60012100, 
+    0x21004770, 0x47706101, 0x68536842, 0x6843604b, 0x6853608b, 0x60516099, 0x61086041, 0x1c496801, 
+    0x47706001, 0x680bb510, 0xd0021c5a, 0x0208f100, 0x6902e002, 0x6852e004, 0x68246854, 0xd9fa429c, 
+    0x604b6853, 0x608a6099, 0x61086051, 0x1c496801, 0xbd106001, 0x1201e9d0, 0xe9d0608a, 0x60511201, 
+    0x684a6901, 0xd1014282, 0x604a6882, 0x61022200, 0x1e406808, 0x47706008, 0x0005b570, 0xd028460e, 
+    0xf000204c, 0x0004fabf, 0xfb05d023, 0x1c40f006, 0xfab8f000, 0xb1c86020, 0x0106fb05, 0x21006061, 
+    0x1e6963a1, 0xfb0160a0, 0x63e50006, 0xf04f60e0, 0xe9c430ff, 0x64a06010, 0x0010f104, 0xff96f7ff, 
+    0x0024f104, 0xff92f7ff, 0xbd704620, 0xf0004620, 0x2000faa5, 0xb510bd70, 0x6c024613, 0xb16a4604, 
+    0x68e0b183, 0xed2cf003, 0x6c2068e1, 0x60e11a09, 0x42916822, 0x6861d202, 0x60e01a08, 0x1c406ba0, 
+    0xbd1063a0, 0xf00368a0, 0x6c21ed1c, 0x440868a0, 0x686160a0, 0xd3f14288, 0x60a06820, 0xb570e7ee, 
+    0x460e4615, 0xb6724604, 0xf875f000, 0xb145b160, 0x0110f104, 0xf7ff4628, 0xb662fe8f, 0x0003f06f, 
+    0xb662bd70, 0xbd702000, 0xbf00b662, 0x6ba0b672, 0x42886be1, 0x2200d20e, 0x46204631, 0xffbbf7ff, 
+    0x25016a60, 0xf104b138, 0xf7ff0024, 0xb110fef9, 0xe0001fad, 0xb6622500, 0xbd704628, 0x460bb570, 
+    0xb6724604, 0xb1f06b80, 0xbf00b662, 0x6ba0b672, 0x6c22b330, 0x441068e0, 0x686160e0, 0xd3014288, 
+    0x60e06820, 0x1e406ba0, 0x68e163a0, 0xf0034618, 0x6920ecc8, 0xb1a02501, 0x0010f104, 0xfed0f7ff, 
+    0x1fadb178, 0xb142e00d, 0x0124f104, 0xf7ff4610, 0xb662fe43, 0x0003f06f, 0xb662bd70, 0xbd702000, 
+    0xb6622500, 0xbd704628, 0x4604b570, 0x46156b80, 0x42906be2, 0x2200d20d, 0xf7ff4620, 0xb945ff6c, 
+    0xb1306a60, 0x0024f104, 0xfeaaf7ff, 0x2001b108, 0x4628bd70, 0xb510bd70, 0xf0004604, 0x6ba0fa54, 
+    0x42886be1, 0x2401d101, 0x2400e000, 0xfa51f000, 0xbd104620, 0x680148ed, 0x6800b111, 0x47706b00, 
+    0x47702000, 0x5ff0e92d, 0x4615469a, 0x46834689, 0xe9dd2058, 0xf000680a, 0x0004f9d5, 0x00afd009, 
+    0xf0004638, 0x6320f9cf, 0x22a5b3d8, 0xf0034639, 0x2c00fcdd, 0x6b21d07e, 0x0003f06f, 0x0085eb00, 
+    0x44084635, 0xf0204649, 0x22200707, 0x0034f104, 0xecfcf003, 0xf8842000, 0x2d0a0053, 0x2509d300, 
+    0x1d2062e5, 0xfeadf7ff, 0x0018f104, 0xfea9f7ff, 0xf1c56124, 0x6264010a, 0x46384652, 0x465961a1, 
+    0xf9baf000, 0xf0006020, 0x4fc8f9fe, 0x1c4068b8, 0x68b860b8, 0x9318f8df, 0xd0082801, 0xb35069b8, 
+    0xe7ffe02e, 0xf0004620, 0x2400f999, 0x603ce7c1, 0xeb052500, 0xeb090185, 0xf7ff0081, 0x1c6dfe77, 
+    0xd3f62d0a, 0x30c848ba, 0xfe70f7ff, 0x30dc48b8, 0xfe6cf7ff, 0x30f048b6, 0xfe68f7ff, 0xf7ff48b5, 
+    0x48b4fe65, 0xf7ff3014, 0x48b2fe61, 0x63b8383c, 0x63f83014, 0x6838e004, 0x42b06ac0, 0x603cd800, 
+    0x69396ae0, 0xd9004288, 0x6af96138, 0x1c496561, 0x697962f9, 0xd9004288, 0xeb006178, 0xeb090180, 
+    0x1d210081, 0xfe50f7ff, 0xf0002501, 0xf1b8f9b2, 0xe0000f00, 0xd001e00c, 0x4000f8c8, 0xb12069b8, 
+    0x6ac06838, 0xd20042b0, 0x4628df00, 0x9ff0e8bd, 0x35fff04f, 0xb570e7f9, 0x69e84d94, 0x6a28b118, 
+    0x62281c40, 0x68e8bd70, 0x60e81c40, 0xb93068e8, 0x6be96ba8, 0x63e863a9, 0x1c406aa8, 0x4e8c62a8, 
+    0x6860e018, 0x428868e9, 0x1d20d8ec, 0xfe42f7ff, 0xb1186aa0, 0x0018f104, 0xfe3cf7ff, 0x69696ae0, 
+    0xd9004288, 0xeb006168, 0x1d210080, 0x0080eb06, 0xfe0af7ff, 0x68006ba8, 0x6ba8b118, 0x68c468c0, 
+    0x2400e000, 0xd1dc2c00, 0xe92dbd70, 0x270047f0, 0xf959f000, 0x69f04e75, 0x61f01e40, 0xbb7869f0, 
+    0xb36868b0, 0x81ccf8df, 0xf8df2500, 0xf1a891c4, 0xe0180814, 0x0018f104, 0xfe0cf7ff, 0xf7ff1d20, 
+    0x6ae0fe09, 0x42886971, 0x6170d900, 0x0180eb00, 0x0081eb09, 0xf7ff1d21, 0x6ae0fdd7, 0x6ac96831, 
+    0xd3004288, 0xf8d82501, 0x46401000, 0x68c0b111, 0xe00068c4, 0x2c002400, 0x6a30d1dc, 0xe008b930, 
+    0xf7ffe00f, 0x6a30ff88, 0x62301e40, 0x28006a30, 0xb915d1f7, 0x28016a70, 0x2701d103, 0x62702000, 
+    0xf000df00, 0x4638f916, 0x87f0e8bd, 0x69c1484f, 0x61c11c49, 0xf0004770, 0xdf00f870, 0xfc6af7ff, 
+    0xb51fe7f9, 0x484e2400, 0x4623a14b, 0x2200f240, 0x94019400, 0x94039402, 0xfeb4f7ff, 0xd1082801, 
+    0x2101b672, 0x61814841, 0xe8bd60c4, 0xf000401f, 0xbd1fb8e3, 0xf000b510, 0x483cf8e6, 0xf00068c4, 
+    0x4620f8e8, 0x4939bd10, 0x4a3969c8, 0x2001b120, 0x47706248, 0x61481e40, 0xeb006948, 0xf8520080, 
+    0x28000020, 0xd0f56948, 0x0080eb00, 0x0080eb02, 0x68526842, 0x0308f100, 0x429a6042, 0x6852d101, 
+    0x68d06042, 0x6b086008, 0xd0e22800, 0x6b4a6808, 0x42906d40, 0x6c08d0dd, 0x30086c8a, 0xd20f4290, 
+    0x6d406808, 0x68c86348, 0x60106c0a, 0x1d006c08, 0x6c0a6408, 0x60106b48, 0x1d006c08, 0x47706408, 
+    0x63082000, 0xb5104770, 0x6b004604, 0xf846f000, 0xe8bd4620, 0xf0004010, 0xb570b841, 0x68684d13, 
+    0xd0222800, 0xff82f7ff, 0x68304e12, 0x2400b158, 0xff2bf7ff, 0xd1182c00, 0xf885f000, 0xb1206830, 
+    0x68c468f0, 0x2401e002, 0x2400e7f2, 0xf7ff1d20, 0x68a8fd41, 0x60a81e40, 0x1e406868, 0xf0006068, 
+    0x4620f878, 0x4070e8bd, 0xbd70e7cd, 0x00041208, 0x0004e7dc, 0x0004e8e0, 0x454c4449, 0x00000000, 
+    0x00025c97, 0x4604b510, 0xff50f7ff, 0xf0034620, 0x4604f9eb, 0xfef9f7ff, 0xbd104620, 0x0004b510, 
+    0xf7ffd008, 0x4620ff43, 0xfa0df003, 0x4010e8bd, 0xbeebf7ff, 0x0000bd10, 0x60011d09, 0xf04f1f01, 
+    0x600b33aa, 0xf04f1f09, 0x60083312, 0x600b1f09, 0xf04f1f09, 0x600b3311, 0xf04f1f09, 0x600b3310, 
+    0xf04f1f09, 0x600b3309, 0xf04f1f09, 0x600b3308, 0xf04f1f09, 0x600b3307, 0xf04f1f09, 0x600b3306, 
+    0xf04f1f09, 0x600b3305, 0xf04f1f09, 0x600b3304, 0xf04f1f09, 0x600b3303, 0xf04f1f09, 0x600b3302, 
+    0x105b1f09, 0x1f09600b, 0x1f09600a, 0x600a223f, 0xf8402100, 0x47701d44, 0xf7ffb510, 0xf004fb49, 
+    0x2000e8c0, 0xb672bd10, 0x68414808, 0x60411c49, 0x48064770, 0x29006841, 0x6841d006, 0x60411e49, 
+    0x28006840, 0xb662d100, 0x00004770, 0x00041254, 0xe92d503f, 0xe59f0068, 0xfa001036, 0xfbffff24, 
+    0xe59f4060, 0xe1d400b0, 0xe2800001, 0xe6ff0070, 0xe1c400b0, 0xe3500b01, 0x3a00000c, 0xe2841008, 
+    0xe3a00065, 0xe3a02000, 0xe1c100b0, 0xe59f0038, 0xe5900000, 0xfafffeab, 0xe59f1030, 0xe5912000, 
+    0xe0800002, 0xe5810000, 0xe3a00000, 0xe1c400b0, 0xe59f001c, 0xfbff86fe, 0xf57ff05f, 0xe8bd503f, 
+    0xe25ef004, 0xf23c824a, 0x00041254, 0x000411dc, 0x0004023c, 0xf0001184, 0x21012300, 0xb510461a, 
+    0xf00448fe, 0x48fdf846, 0x220e2300, 0x0100f244, 0x4010e8bd, 0xf0043010, 0xe92db83c, 0x48f75ff0, 
+    0x011af24a, 0xf004301e, 0x48f4f81a, 0x3100f240, 0xf0043020, 0x48f1f814, 0x01eff243, 0xf0043022, 
+    0x48eef80e, 0x3184f249, 0xf0043026, 0x48ebf808, 0x30282100, 0xf803f004, 0xf24448e8, 0x302c0100, 
+    0xfffdf003, 0xf24348e5, 0x302e0100, 0xfff7f003, 0xf24148e3, 0x4ce12712, 0x78003430, 0x1d261ca5, 
+    0xf241b110, 0xe0011115, 0x1114f241, 0xf0034620, 0x4639ffe6, 0xf0034628, 0x2113ffe2, 0xf0034630, 
+    0xf8dfffde, 0xf2408358, 0x46394700, 0x0836f108, 0xf0034640, 0xf108ffd4, 0xf2470902, 0x46484121, 
+    0xffcdf003, 0x0a04f108, 0x46502100, 0xffc7f003, 0x0b00f241, 0x0006f108, 0xf0034659, 0xf109ffc0, 
+    0xf64a0006, 0xf0032100, 0x48c4ffba, 0x01fff244, 0xf003304e, 0x48c1ffb4, 0x302a4659, 0xffaff003, 
+    0x210048be, 0xf003302a, 0x2100ffaa, 0xf0034620, 0x2100ffa6, 0xf0034628, 0x2100ffa2, 0xf0034630, 
+    0x2100ff9e, 0xf0034640, 0x2100ff9a, 0xf0034648, 0x2100ff96, 0xf0034650, 0x2100ff92, 0x0006f108, 
+    0xff8df003, 0xf1092100, 0xf0030006, 0x48abff88, 0x304e2100, 0xff83f003, 0x412df643, 0xf0034620, 
+    0xf642ff7e, 0x46281128, 0xff79f003, 0x46302174, 0xff75f003, 0xf24848a1, 0x304e0107, 0xff6ff003, 
+    0x4659489e, 0xf003302a, 0x489cff6a, 0x302a2100, 0xff65f003, 0x46202100, 0xff61f003, 0x46282100, 
+    0xff5df003, 0x46302100, 0xff59f003, 0x21004893, 0xf003304e, 0x2100ff54, 0xf0034620, 0xf240ff50, 
+    0x46285140, 0xff4bf003, 0x6140f640, 0xf0034630, 0xf640ff46, 0x46400141, 0xff41f003, 0x3144f241, 
+    0xf0034648, 0xf109ff3c, 0xf2450006, 0xf003011c, 0x2140ff36, 0x0006f10a, 0xff31f003, 0xf645487f, 
+    0x3042113b, 0xff2bf003, 0x4639487c, 0xf0033044, 0xe8bdff26, 0x48795ff0, 0x302a21d0, 0xbf1ff003, 
+    0x5ff0e92d, 0xf24a4875, 0x301e011a, 0xff17f003, 0xf2404872, 0x30203100, 0xff11f003, 0x21ef486f, 
+    0xf0033022, 0x486dff0c, 0x3104f241, 0xf0033026, 0x486aff06, 0x1180f240, 0xf0033028, 0x4867ff00, 
+    0x0100f244, 0xf003302c, 0x4864fefa, 0x0100f243, 0xf003302e, 0x4c61fef4, 0x0110f640, 0x46203430, 
+    0xfeedf003, 0xf6401ca5, 0x46280108, 0xfee7f003, 0x0904f104, 0x46482107, 0xfee1f003, 0x0a06f104, 
+    0x5100f240, 0xf0034650, 0xf105feda, 0xf2470b06, 0x4658318e, 0xfed3f003, 0x0606f109, 0x0800f241, 
+    0x46304641, 0xfecbf003, 0x46411cb7, 0xf0034638, 0x1d30fec6, 0x2100f64a, 0xfec1f003, 0xf2444847, 
+    0x304e01ff, 0xfebbf003, 0x46411fa0, 0xfeb7f003, 0x1fa02100, 0xfeb3f003, 0x46202100, 0xfeaff003, 
+    0x46282100, 0xfeabf003, 0x46482100, 0xfea7f003, 0x46502100, 0xfea3f003, 0x46582100, 0xfe9ff003, 
+    0x46302100, 0xfe9bf003, 0x46382100, 0xfe97f003, 0x1d302100, 0xfe93f003, 0x21004830, 0xf003304e, 
+    0xf643fe8e, 0x46201116, 0xfe89f003, 0x112ef242, 0xf0034628, 0x216afe84, 0xf0034648, 0x2100fe80, 
+    0xf0034630, 0x4825fe7c, 0x0127f248, 0xf003304e, 0x1fa0fe76, 0xf0034641, 0x2100fe72, 0xf0031fa0, 
+    0x2100fe6e, 0xf0034620, 0x2100fe6a, 0xf0034628, 0x2100fe66, 0xf0034648, 0x2100fe62, 0xf0034658, 
+    0x2100fe5e, 0xf0034630, 0x2100fe5a, 0xf0031d30, 0x1dbefe56, 0x46302100, 0xfe51f003, 0x2100480f, 
+    0xf003304e, 0x2101fe4c, 0xf0034620, 0xf240fe48, 0x46285140, 0xfe43f003, 0x6140f640, 0xf0034648, 
+    0xf640fe3e, 0x46500141, 0xfe39f003, 0x3144f241, 0xf0034658, 0xf248fe34, 0xe0030114, 0xf2039800, 
+    0x000405a0, 0xf0031f30, 0x1eb0fe2a, 0x7160f248, 0xfe25f003, 0x3133f644, 0xf0034630, 0x1cb0fe20, 
+    0x4100f240, 0xfe1bf003, 0x1fa021d0, 0x5ff0e8bd, 0xbe15f003, 0x4ff0e92d, 0xb09d48fe, 0xc84eaf03, 
+    0x004ee887, 0xaf07c84e, 0x004ee887, 0xaf0bc84e, 0x004ee887, 0xae0fc80f, 0x000fe886, 0xf7e62002, 
+    0x2000f963, 0xf996f7e5, 0xf7e52000, 0xf7f2fbc9, 0x2001fb1d, 0xf82cf7e5, 0x210048ef, 0xfdeff003, 
+    0xf00348ee, 0x4eeefde9, 0x46302101, 0xfde7f003, 0xf99048ec, 0x28030000, 0x2802d079, 0x2801d001, 
+    0xf7ffd075, 0x48e6fdba, 0x220a2300, 0x4100f240, 0xf0033010, 0xf8dffdee, 0x23018388, 0xf108220c, 
+    0x0319082e, 0xf0034640, 0x2301fde4, 0x220d4640, 0xf0030359, 0x48dcfdde, 0x71fff647, 0xfdbff003, 
+    0x46302301, 0x46192200, 0xfdd3f003, 0x46302301, 0x461a2102, 0xfdcdf003, 0x46304ed4, 0xfdacf003, 
+    0x800849d3, 0x1140f240, 0xf0034630, 0x2000fda8, 0x22029000, 0x46014603, 0xf872f7f6, 0x23014eca, 
+    0x46192200, 0x46303e10, 0xfdb3f003, 0x46302300, 0x461a2101, 0xfdadf003, 0x23004ebf, 0x3e0c2203, 
+    0x46302108, 0xfda5f003, 0x780148c2, 0x0080f44f, 0xfa22f7e1, 0x46302301, 0x21082203, 0xfd99f003, 
+    0x383848b6, 0xfd78f003, 0x28e4b2c0, 0x2003d012, 0x23029000, 0x21002201, 0xf7e748b7, 0xf04ff851, 
+    0xf10d0901, 0x46c80a64, 0xe016ae1b, 0xf7ffe7ff, 0xe788fe47, 0x90002000, 0x22022301, 0xe7eb2103, 
+    0xb2a0d10b, 0xd1082801, 0x28010c20, 0xb2a8d105, 0xd1022801, 0x28010c28, 0x48a8d071, 0xb280f8df, 
+    0x0b10f10b, 0xf2497801, 0xea400000, 0xb2813041, 0xf0034658, 0x4f9ffd44, 0x7839e004, 0x0080f44f, 
+    0xf9daf7e1, 0xf0034658, 0x0500fd37, 0x4894d4f5, 0xf0033012, 0xf8dffd31, 0xf10de260, 0x0b020b4c, 
+    0x2703f3c0, 0x0f01f1b9, 0x3003f99e, 0x2013f82b, 0x2002f99e, 0x7012f82b, 0x1001f99e, 0x1703f3c0, 
+    0x7011f82b, 0x070ff000, 0x0000f99e, 0x7010f82b, 0xf1b9d008, 0xd0270f02, 0xfc84fa1f, 0x0f00f1bc, 
+    0xe06ad05a, 0x0c04f10d, 0xe013f83b, 0xe013f82c, 0xe012f83b, 0xe012f82c, 0xe011f83b, 0xe011f82c, 
+    0x7010f82c, 0xf8262700, 0xf8267010, 0xf3677011, 0xf367040f, 0xf826050f, 0xf3677012, 0xf367441f, 
+    0xf826451f, 0xe0857013, 0x0c04f10d, 0xe010f83c, 0xd10545be, 0x7010f826, 0x040ff368, 0xe081e002, 
+    0x7010f82a, 0x7011f83c, 0xf83b46de, 0x42870011, 0xf368d104, 0xf826441f, 0xe0010011, 0x0011f82a, 
+    0x7012f83c, 0xf83e4671, 0x42870012, 0xf826d104, 0xf3680012, 0xe001050f, 0x0012f82a, 0x2013f83c, 
+    0x0013f831, 0xd1044282, 0x451ff368, 0x0013f826, 0xf82ae050, 0xe04d0013, 0xc010f83a, 0xd0054567, 
+    0x0c04f10d, 0xc010f83c, 0xd1044567, 0x7010f826, 0x040ff368, 0xf826e001, 0x0c20c010, 0xf83bd111, 
+    0xf83a0011, 0x42b87011, 0xaf01d004, 0x7011f837, 0xd10442b8, 0x441ff368, 0x0011f826, 0xf826e001, 
+    0x04287011, 0xd1110c00, 0x0012f83b, 0x1012f83a, 0xd0044288, 0xf831a901, 0x42881012, 0xf826d104, 
+    0xf3680012, 0xe001050f, 0x1012f826, 0xd1110c28, 0x0013f83b, 0x1013f83a, 0xd0044288, 0xf831a901, 
+    0x42881013, 0xf368d104, 0xf826451f, 0xe0010013, 0x1013f826, 0x0001f109, 0x09fff000, 0x0f03f1b9, 
+    0xaefef67f, 0x0000f04f, 0xf836465d, 0xf8251010, 0xf1001010, 0xb2c00001, 0xd9f62803, 0x8080f8df, 
+    0x4f252400, 0xf108ae15, 0xeb080814, 0xf0030044, 0xf1c4fc43, 0x1c640103, 0x5679b2e4, 0xf8262c03, 
+    0xd9f20011, 0x46a92400, 0xaf1746b8, 0x5004f918, 0x0015f839, 0xd05c2802, 0xd05a2803, 0xd0582804, 
+    0x0015f836, 0xf970f006, 0xf851a90b, 0xf0061025, 0xa90ff97f, 0x1025f851, 0xffe8f005, 0xf92cf006, 
+    0xb2e41c64, 0xf8272c03, 0xd9df0015, 0x24004d0c, 0x0000e018, 0x0002cf2c, 0xf203900c, 0xf23c804a, 
+    0xf2039800, 0x000405a2, 0xf23c8310, 0xf38fffc0, 0x00041264, 0x0004028b, 0x00040578, 0x000405a0, 
+    0x000405a1, 0xf04f4ea4, 0x78280864, 0x1014f837, 0xfbb1b108, 0xeb06f1f8, 0xf0030044, 0x1c64fbf0, 
+    0x2c03b2e4, 0xf8bdd9f1, 0xf8bd104c, 0xf8bd0052, 0xea402050, 0xf8bd3001, 0x0209104e, 0x1102ea41, 
+    0xb2814308, 0x1e804894, 0xfbd9f003, 0xe8bdb01d, 0xf8368ff0, 0xf0060015, 0xa903f917, 0x1025f851, 
+    0xf926f006, 0xe7a5a907, 0x5ff0e92d, 0x8e804604, 0x8228f8df, 0x566cf240, 0x42b04d89, 0x516cf2a0, 
+    0x5739f240, 0x5938f240, 0xdc17d073, 0xf2a042b8, 0xd0375139, 0xb300dc0d, 0xd12f4548, 0x22006868, 
+    0x0108f105, 0xf87af7ff, 0xd0291d41, 0xd11a2801, 0x2925e028, 0x2926d07e, 0xe014d120, 0xd012290d, 
+    0x2901dc0c, 0x290cd00f, 0x4975d118, 0x68682200, 0xf7ff3108, 0x1d40f834, 0xe004d06d, 0xd06b292a, 
+    0xd10b292b, 0x496ee0b8, 0x32fff04f, 0x31086868, 0xf854f7ff, 0xd1d71d01, 0x9034f8a4, 0x9ff0e8bd, 
+    0xe7fb86a7, 0xf04f4b66, 0xf04f52c0, 0x33085000, 0x1000f9b3, 0xd02d2966, 0xd05e2968, 0xd07a2969, 
+    0xd1e02967, 0xf7d9469a, 0x2300fff4, 0x2101485d, 0xf003461a, 0x495cfb7e, 0x23012000, 0x70082200, 
+    0x8801485a, 0x0110f021, 0x48598001, 0xf0034619, 0x2000fb70, 0xf8d2f7e7, 0xf8aa2107, 0x49501000, 
+    0xf8d82200, 0x31080000, 0xffe9f7fe, 0xd0671d01, 0xe045e070, 0xf7d9469a, 0xf8dfffcc, 0x4658b138, 
+    0xfb3af003, 0xb2811c40, 0xf0034658, 0x2004fb38, 0xf8aef7e1, 0x78014848, 0x2000f44f, 0xffccf7e0, 
+    0xf8aa2168, 0x493e1000, 0x68682200, 0xf7fe3108, 0xe002ffc6, 0xe040e006, 0x1d01e045, 0xf240d108, 
+    0xe059505e, 0x22004936, 0x31086868, 0xffb7f7fe, 0xd1881d40, 0x505ff240, 0x469ae04e, 0xff99f7d9, 
+    0xfcf8f7ff, 0xf8aa2169, 0x492d1000, 0x68682200, 0xf7fe3108, 0x1d01ffa4, 0x86a6d108, 0xe00ae77e, 
+    0x22004927, 0x31086868, 0xff99f7fe, 0xd1881d40, 0x506df240, 0x469ae030, 0xff7bf7d9, 0xf8aa2167, 
+    0x491f1000, 0x68682200, 0xf7fe3108, 0x1d01ff88, 0xaf51f47f, 0x5078f240, 0xf240e01e, 0xe01b5079, 
+    0x5096f240, 0x4916e018, 0xf8d82200, 0x31080000, 0xff75f7fe, 0xd00d1d40, 0xfda5f7e6, 0x48178829, 
+    0xfacdf003, 0x23004816, 0xf640220b, 0xf0030100, 0xe738fae0, 0x5097f240, 0xe73f86a0, 0x21012200, 
+    0xf2afb510, 0xf7fe201b, 0x2108fda5, 0xf7fe2002, 0x4903ff03, 0xbd106048, 0xf203512e, 0x00040734, 
+    0x00041264, 0xf2039800, 0x000402aa, 0x00040288, 0xf38f20e0, 0xf2039ffe, 0x0004028b, 0xf38fffc0, 
+    0xf23c800c, 0x22052301, 0xb5102120, 0x46204cfe, 0xfaaff003, 0x46202301, 0x21402206, 0xfaa9f003, 
+    0xe8bd2100, 0x20044010, 0xbf26f7e0, 0x4cf6b510, 0x22042301, 0x2110347e, 0xf0034620, 0x2303fa9a, 
+    0x22024620, 0xf003210c, 0x2302fa94, 0x22004620, 0x4010e8bd, 0xf0032103, 0xb510ba8c, 0x23014cea, 
+    0x21042202, 0xf0034620, 0x2301fa84, 0x21024620, 0xf003461a, 0x2301fa7e, 0x22004620, 0xf0034619, 
+    0x2100fa78, 0x4010e8bd, 0xf7e02004, 0x48dfbef5, 0x31b6f64b, 0xf003b510, 0x4cddfa52, 0xf7ff7820, 
+    0x7820ffdc, 0xffc2f7ff, 0xe8bd7820, 0xe7a94010, 0x41f0e92d, 0x48d74604, 0x0700f24f, 0x46394420, 
+    0x46052304, 0xf003220c, 0x2308fa54, 0x113e4628, 0x4631461a, 0xfa4df003, 0x46282308, 0x21f02204, 
+    0xfa47f003, 0x46282308, 0x210f2200, 0xfa41f003, 0x230948c8, 0x4639220c, 0x44201c80, 0xf0034605, 
+    0x2309fa38, 0x22084631, 0xf0034628, 0x2304fa32, 0x21f04628, 0xf003461a, 0x2300fa2c, 0x210f4628, 
+    0xf003461a, 0x48bbfa26, 0x76fff643, 0x46312319, 0x220030d2, 0xf0034420, 0x48b6fa1c, 0x78fff641, 
+    0x46412306, 0x220030d4, 0xf0034420, 0x48b1fa12, 0x7500f64f, 0x46292301, 0x442030d6, 0x46072208, 
+    0xfa07f003, 0x46382300, 0x461a21ff, 0xfa01f003, 0x230048a8, 0x461a213f, 0x442030d8, 0xf9f9f003, 
+    0x117748a4, 0x46392305, 0x22003062, 0xf0034420, 0x48a0f9f0, 0x2200237d, 0x30c84631, 0xf0034420, 
+    0x489cf9e8, 0x2200231f, 0x30604639, 0xf0034420, 0x4898f9e0, 0x22002332, 0x30cc4631, 0xf0034420, 
+    0x4894f9d8, 0x22002331, 0x30d04641, 0x46064420, 0xf9cff003, 0x2301488f, 0x46292208, 0x442030ca, 
+    0xf0034605, 0x2300f9c6, 0x21ff4628, 0xf003461a, 0x4888f9c0, 0x2200231f, 0x30ce4641, 0x46044420, 
+    0xf9b7f003, 0x0500f24e, 0x23004630, 0x220d4629, 0xf9aff003, 0x46204629, 0x41f0e8bd, 0x220d2300, 
+    0xb9a7f003, 0x4ff8e92d, 0x48784605, 0x46162400, 0xf640220b, 0x38820100, 0xf0039400, 0x4976f9a8, 
+    0x0ffff010, 0x2d03d006, 0x2d05d033, 0x2d04d011, 0xe010d00f, 0xd0142d03, 0xd0012d05, 0xd1012d04, 
+    0xd00e2e02, 0x28017808, 0x2d02d101, 0x2401d009, 0x2e02e007, 0x7808d01d, 0xd1012801, 0xd0182d02, 
+    0x4e672405, 0x9194f8df, 0x0500f24f, 0xf2441cb7, 0xf2400800, 0xf6433aff, 0xb1647bff, 0xd0252c01, 
+    0x817cf8df, 0xf1082c04, 0xd07b080c, 0xd16a2c05, 0x2404e080, 0x2305e7e5, 0x220c4629, 0xf0034648, 
+    0x2301f958, 0x220e4641, 0xf0034630, 0x2302f952, 0x22014638, 0xf0032106, 0x2319f94c, 0x22004651, 
+    0xf0034630, 0xf243f946, 0xe01c2300, 0xf7ff9800, 0x2305fedf, 0x220c4629, 0xf0034648, 0x2301f93a, 
+    0x220e4641, 0xf0034630, 0x2302f934, 0x22014638, 0xf0032106, 0x231ff92e, 0x22004651, 0xf0034630, 
+    0xf241f928, 0x483e0300, 0x46592200, 0xf0031e80, 0x483bf920, 0x220c2300, 0x1f004629, 0xf919f003, 
+    0x23004837, 0x21102204, 0xf003380c, 0x230ff912, 0x22034638, 0xf0032178, 0x4831f90c, 0x22002303, 
+    0x380e210f, 0xf905f003, 0x2300482d, 0xf6402209, 0x38106100, 0xf8fdf003, 0xf2482300, 0x220f0100, 
+    0xf0034630, 0x2300f8f6, 0x21014638, 0xf003461a, 0xb001f8f0, 0x23014638, 0x46192200, 0x4ff0e8bd, 
+    0xb8e7f003, 0x46292303, 0x4648220c, 0xf8e1f003, 0xe0092342, 0xf7ff9800, 0x2303fe7b, 0x220c4629, 
+    0xf0034648, 0x2350f8d6, 0x22004651, 0xf0034630, 0x4813f8d0, 0x461a2300, 0x1e804659, 0xf8c9f003, 
+    0x2300480f, 0x4629220c, 0xf0031f00, 0x480cf8c2, 0x22042300, 0x380c2110, 0xf8bbf003, 0x4638230f, 
+    0x21782203, 0x0000e00e, 0xf3074004, 0xf23c80ba, 0x00040368, 0xf3072402, 0x00040311, 0xf3072200, 
+    0xf303a170, 0xf8a5f003, 0x230d48ff, 0x210f2200, 0xf89ff003, 0x230248fc, 0xf6402209, 0x1e806100, 
+    0xf897f003, 0xf2482300, 0x220f0100, 0xf0034630, 0x2300f890, 0x22014640, 0xf0032102, 0x2300f88a, 
+    0x21014640, 0xe78c461a, 0xb149b430, 0x46034cef, 0x220048ed, 0x38602101, 0xbc304420, 0xb879f003, 
+    0xe7f42400, 0x460db570, 0x4ce8b19a, 0x460334c0, 0x220048e5, 0x30642101, 0xf0034420, 0x48e2f86a, 
+    0x21012200, 0x3044462b, 0xe8bd4420, 0xf0034070, 0x2400b860, 0xb430e7eb, 0x4cdcb149, 0x48da4603, 
+    0x21012200, 0x44203846, 0xf003bc30, 0x2400b852, 0xb430e7f4, 0x4cd6b151, 0x48d34603, 0xf242220d, 
+    0x30860100, 0xbc304420, 0xb843f003, 0xe7f32400, 0x5ffce92d, 0x4605000f, 0x4690469b, 0xf44fd012, 
+    0xf8df1400, 0xf2409330, 0x46282a00, 0xfe8af7ff, 0x21004ac9, 0x1c902362, 0x0f00f1bb, 0x80018011, 
+    0xe011d002, 0xe7ec2400, 0xd00b2d03, 0xd0012d05, 0xd1022d04, 0x0f02f1b8, 0x2138d004, 0x21a88011, 
+    0xe0028001, 0x80112126, 0x46238003, 0xf0218811, 0x80110101, 0xf4228802, 0xf04f7680, 0x80060202, 
+    0xb1074650, 0xf0014631, 0x2000fa15, 0xf7ff4639, 0x2001ff7b, 0xf7ff4639, 0x2000ffac, 0xf7ff4639, 
+    0x48aeff9a, 0x21012300, 0x4420461a, 0xf0029001, 0x48aafff0, 0x22012300, 0x44203848, 0x21024682, 
+    0xf0024656, 0x2300ffe6, 0x21014630, 0xf002461a, 0x2001ffe0, 0xf7ff4639, 0x2f01ff7e, 0x489ad004, 
+    0x30642102, 0xffbbf002, 0x0f00f1bb, 0x489cd17e, 0x28017800, 0x2d03d103, 0x2d02d02a, 0x4897d028, 
+    0x23002208, 0x01513052, 0xf0024420, 0x4895ffc2, 0x220b2300, 0x0100f640, 0x46064420, 0xffb9f002, 
+    0x46302301, 0x21402206, 0xffb3f002, 0xf2402300, 0x220a4100, 0xf0024630, 0x2d03ffac, 0x2d05d07e, 
+    0x2d04d07d, 0x2d02d07c, 0x2d01d07b, 0xe0eed07a, 0x220c4884, 0x44202302, 0x46800291, 0xff99f002, 
+    0xf2414881, 0x442001ee, 0xff79f002, 0xf24a487e, 0x1c800100, 0xf0024420, 0x487bff72, 0x31b8f640, 
+    0x44201d00, 0xff6bf002, 0xf6414877, 0x1d803100, 0xf0024420, 0x4874ff64, 0x2635f248, 0x30084631, 
+    0xf0024420, 0x4870ff5c, 0x300a4631, 0xf0024420, 0x486dff56, 0x300e4631, 0xf0024420, 0x486aff50, 
+    0x3012210f, 0xf0024420, 0x4864ff4a, 0x2205231c, 0x31e0f240, 0x4420305c, 0xf0029000, 0x4e5fff5a, 
+    0x2d03365e, 0x2d02d003, 0xe01cd010, 0xf04fe0a6, 0x210c4260, 0xf7d91750, 0x19a0fbbc, 0x46062301, 
+    0x21082203, 0xff45f002, 0xe0072300, 0x230019a0, 0x22034606, 0xf0022108, 0x2301ff3c, 0x22054630, 
+    0xf0022120, 0x9800ff36, 0x22002301, 0xf002211f, 0x2208ff30, 0x23014849, 0xe0040151, 0xe014e013, 
+    0xe0b3e043, 0x3052e0b4, 0xf0024420, 0x2300ff22, 0x0100f640, 0x4640220b, 0xff1bf002, 0x46402300, 
+    0x21402206, 0x230fe061, 0x4840e011, 0x0f01f1b8, 0xf1b8d003, 0xd00e0f02, 0x7800e059, 0xf04f2120, 
+    0xea414260, 0x17502100, 0xfb73f7d9, 0x46302320, 0x213f2200, 0x7800e049, 0xf04f2121, 0xea414260, 
+    0x17502100, 0xfb65f7d9, 0x46302329, 0x213f2200, 0xfeeff002, 0xd03a2f01, 0x2301482b, 0x210f2200, 
+    0xf00238a6, 0x2301fee6, 0x4829e02b, 0x0f01f1b8, 0xf1b8d003, 0xd00b0f02, 0x7800e029, 0xf04f2110, 
+    0xea414260, 0x17502100, 0xfb43f7d9, 0xe7ce2321, 0x21117800, 0x4260f04f, 0x2100ea41, 0xf7d91750, 
+    0x2328fb38, 0x22004630, 0xf002213f, 0x2f01fec2, 0x4815d00d, 0x22002304, 0x38a6210f, 0xfeb9f002, 
+    0x48112304, 0x210f2200, 0xf00238a2, 0x480dfeb2, 0x22072301, 0x44202180, 0xfeabf002, 0x23014802, 
+    0x461a2102, 0xe0153064, 0xf303a162, 0x00200060, 0x002001c0, 0x0004e178, 0x00041274, 0xf30788ae, 
+    0x00040311, 0xf3078616, 0xf30724a6, 0x00040313, 0x00040312, 0xf0024420, 0xf899fe8c, 0x463a1021, 
+    0x0022f899, 0xfe0ef7ff, 0x230048ff, 0x21022201, 0xf0024420, 0x49fdfe7e, 0x1c882200, 0x8002800a, 
+    0xf1bb2204, 0xd0050f00, 0xe0182224, 0xe76e2302, 0xe76c2301, 0x781b4bf6, 0xd1032b01, 0xd0602d03, 
+    0xd05e2d02, 0x800b2314, 0xd0042d04, 0xd0022d02, 0xd0002d01, 0x88028002, 0x0260f022, 0x80023220, 
+    0xb291b3f7, 0x3000f240, 0x46232202, 0xf862f001, 0x780048e7, 0x2d03b108, 0x463ad004, 0x46484629, 
+    0xfda7f001, 0x23004de3, 0xf244220e, 0x46280100, 0xfe3ff002, 0x46282301, 0x0359220d, 0xfe39f002, 
+    0x46282301, 0x0319220c, 0xfe33f002, 0x0020f999, 0x210f2200, 0x48d7b283, 0xf0023024, 0x2301fe2a, 
+    0x21024650, 0xf002461a, 0x2301fe24, 0x22004650, 0xf0024619, 0x2001fe1e, 0xf7ff4639, 0xe000fd95, 
+    0x2301e012, 0x22009801, 0xf0024619, 0x48cafe12, 0x2301b002, 0xe8bd4420, 0x22025ff0, 0xf0022104, 
+    0x2203be08, 0xe7aa800a, 0xe7ab8809, 0x5ff0e92d, 0x23014dc2, 0x46172120, 0x46042205, 0xf0024628, 
+    0x2c03fdf8, 0x0600f244, 0x41dff240, 0x2c05d008, 0x2c04d009, 0x2c02d011, 0x2c01d07f, 0xe021d07f, 
+    0x4310f240, 0xf240e001, 0x46284308, 0xf0022200, 0x2300fde0, 0x220e4631, 0x2200e011, 0x4304f240, 
+    0x46284688, 0xfdd5f002, 0x46312301, 0x4628220e, 0xfdcff002, 0xd1052f03, 0x46412382, 0x46282200, 
+    0xfdc7f002, 0x230148a5, 0x21202205, 0xf0021c80, 0xf8dffdc0, 0x2301a288, 0x46192200, 0x0a0af10a, 
+    0xf0024650, 0x2301fdb6, 0x0b04f10a, 0x22004619, 0xf0024658, 0x2301fdae, 0x0502f1aa, 0x22004619, 
+    0xf0024628, 0x2301fda6, 0x46191d2e, 0x46302200, 0xfd9ff002, 0xf6412c03, 0xf2406800, 0xd03019e0, 
+    0xd02e2c05, 0xd02c2c04, 0x2c024f8d, 0x2c01d058, 0xf64fd173, 0x46540500, 0x46292306, 0x4650220b, 
+    0xfd87f002, 0x46292306, 0x465d220b, 0xf0024658, 0x2300fd80, 0x22054620, 0xf0022120, 0x2300fd7a, 
+    0x22054628, 0xf0022120, 0x7839fd74, 0xd07d2901, 0xd07c2900, 0xe000e095, 0x2382e001, 0x2341e785, 
+    0x2302e783, 0x22094641, 0xf0024628, 0x2302fd62, 0x22094641, 0xf0024630, 0x2303fd5c, 0x2205464c, 
+    0x46284649, 0xfd55f002, 0x46212303, 0x46302205, 0xfd4ff002, 0x46282301, 0x21102204, 0xfd49f002, 
+    0x46302301, 0x21102204, 0xfd43f002, 0x46282303, 0x210e2201, 0xfd3df002, 0x22012303, 0xe03b210e, 
+    0x46412303, 0x46282209, 0xfd33f002, 0x46412303, 0x46302209, 0xfd2df002, 0x46282300, 0x21102204, 
+    0xfd27f002, 0x46302300, 0x21102204, 0xfd21f002, 0x28017838, 0xb148d002, 0xe05ee014, 0x46282302, 
+    0x210e2201, 0xfd15f002, 0xe0062304, 0x46282300, 0x210e2201, 0xfd0df002, 0x46302302, 0x210e2201, 
+    0xfd07f002, 0x464c2303, 0x46492205, 0xf0024628, 0x2303fd00, 0x22054621, 0xf0024630, 0x2300fcfa, 
+    0x21014628, 0xf002461a, 0xe001fcf4, 0xe00ce005, 0x46302300, 0x461a2101, 0x2304e02b, 0x22014620, 
+    0xf002211e, 0x2304fce6, 0x2302e006, 0x22014620, 0xf002211e, 0x2302fcde, 0x22014628, 0xf002211e, 
+    0x2306fcd8, 0x76c0f240, 0x4631461a, 0xf0024620, 0x2306fcd0, 0x461a4631, 0xf0024628, 0x2300fcca, 
+    0x21014620, 0xf002461a, 0x2300fcc4, 0x21014628, 0xe8bd461a, 0xf0025ff0, 0xe8bdbcbc, 0xb4309ff0, 
+    0xf04fb159, 0x46031420, 0x2200481a, 0x31fff240, 0x442030c8, 0xf002bc30, 0x2400bcac, 0xb430e7f3, 
+    0xf04fb151, 0x46031420, 0x22004812, 0x30c22101, 0xbc304420, 0xbc9df002, 0xe7f42400, 0x0005b570, 
+    0xf44fd046, 0x20011400, 0xf0004621, 0x2000fed1, 0xf7ff4629, 0x2001ffe4, 0xf7ff4629, 0x4629ffe0, 
+    0x10f4f240, 0x0000e00e, 0xf302012c, 0x00041278, 0x00040311, 0xf303a120, 0xf30788a0, 0xf3074080, 
+    0x00040369, 0xffbbf7ff, 0x46212000, 0xfeb0f000, 0xf44f2100, 0xf7e01080, 0x2100f8ef, 0x2080f44f, 
+    0xf8eaf7e0, 0x230148ff, 0x46192200, 0xf0024420, 0x4cfdfc60, 0x22042300, 0x46202110, 0xfc59f002, 
+    0xe8bd4620, 0x23014070, 0x21102204, 0xbc51f002, 0xe7b82400, 0x48f42300, 0x21082203, 0xbc49f002, 
+    0x41f0e92d, 0x4ef14cf1, 0x36081f25, 0xb1d91d27, 0x78e6f640, 0x46414638, 0xfc21f002, 0x46284641, 
+    0xfc1df002, 0x46304641, 0xfc19f002, 0x46204641, 0xfc15f002, 0x46282302, 0x21382203, 0xfc29f002, 
+    0x22032302, 0xe0772138, 0x0300f04f, 0x0101f04f, 0x461a2801, 0x4628d046, 0xfc1bf002, 0x46382300, 
+    0x461a2101, 0xfc15f002, 0x46282301, 0x461a2102, 0xfc0ff002, 0x46382301, 0x461a2102, 0xfc09f002, 
+    0x46382300, 0x21382203, 0xfc03f002, 0x46282304, 0x21382203, 0xfbfdf002, 0x46382300, 0x21042202, 
+    0xfbf7f002, 0x46282300, 0x21042202, 0xfbf1f002, 0x46202301, 0x46192200, 0xfbebf002, 0x46302301, 
+    0x46192200, 0xfbe5f002, 0x46282301, 0x46192200, 0xfbdff002, 0xe8bd4638, 0x230141f0, 0x46192200, 
+    0xbbd7f002, 0xf0024620, 0x2300fbd4, 0x21014630, 0xf002461a, 0x2301fbce, 0x21024620, 0xf002461a, 
+    0x2301fbc8, 0x21024630, 0xf002461a, 0x2300fbc2, 0x22034630, 0xf0022138, 0x2304fbbc, 0x22034620, 
+    0xf0022138, 0x2300fbb6, 0x22024630, 0xf0022104, 0x2300fbb0, 0x21042202, 0xe7b74620, 0x41f0e92d, 
+    0x460c2203, 0x46052138, 0xf00248a1, 0xf8dffbb0, 0x4f9ec27c, 0x0c3cf1ac, 0x0604f10c, 0xf1a63f14, 
+    0xb1550e06, 0xd0212d01, 0xd1622d02, 0xd0472c01, 0xd0562804, 0xd0542802, 0x2c01e005, 0x2804d006, 
+    0x2802d012, 0x2801d010, 0xe050d00e, 0xd0032804, 0xd0012802, 0xd1052801, 0x46602302, 0x211e2201, 
+    0xfb77f002, 0xe0172302, 0xe03b2302, 0xd0062c01, 0xd0152804, 0xd0132802, 0xd0132801, 0x2804e018, 
+    0x2802d003, 0x2801d001, 0x2304d105, 0x22014660, 0xf002211e, 0x2304fb5e, 0x22014630, 0xe00b211e, 
+    0xe0002303, 0x46702304, 0x210e2201, 0xfb51f002, 0x46382302, 0x210e2201, 0x41f0e8bd, 0xbb49f002, 
+    0xd0042804, 0xd0022802, 0xd0022801, 0x2301e007, 0x2302e000, 0x22014660, 0xf002211e, 0x2301fb3a, 
+    0x2301e7da, 0x22014670, 0xf002210e, 0x2301fb32, 0xe8bde7df, 0xb57081f0, 0x48634604, 0x0100f244, 
+    0x2c04307c, 0x2c05d01a, 0x2300d018, 0xf002220e, 0x4d5efb20, 0x220d2301, 0x03593d40, 0xf0024628, 
+    0x2c01fb18, 0x0100f241, 0x2c02d00a, 0x2c03d008, 0x2c05d008, 0x2c04d006, 0xe008d004, 0xe7e52301, 
+    0xe0002300, 0x46282301, 0xf002220c, 0x2300fb02, 0x22034628, 0xf0022108, 0x2301fafc, 0x22024628, 
+    0xf0022104, 0x2301faf6, 0x22004628, 0xf0024619, 0x4d46faf0, 0x22052301, 0x21203d3a, 0xf0024628, 
+    0x2301fae8, 0x22044628, 0xf0022110, 0x2c01fae2, 0x2c02d001, 0x483fd109, 0x78004621, 0xff2ef7ff, 
+    0x7801483d, 0xf7ff4620, 0xe8bdfe8b, 0x23014070, 0x22034835, 0xf0022108, 0xe92dbacc, 0x4d3347f0, 
+    0xf248460c, 0xf6400100, 0x3d366900, 0x1a00f240, 0xf04f10cf, 0x28000300, 0x020ff04f, 0x460ed06b, 
+    0xf0024628, 0xf8dffab6, 0x230080a0, 0xf1082205, 0x2120087e, 0xf0024640, 0x2301faac, 0x220c4639, 
+    0xf0024628, 0xb2a3faa6, 0x22094649, 0xf0024628, 0x2301faa0, 0x22084651, 0xf0024628, 0x2301fa9a, 
+    0x22004628, 0xf0024619, 0x2301fa94, 0x220f4631, 0xf0024628, 0x2301fa8e, 0x22054640, 0xf0022120, 
+    0x4c12fa88, 0x22092301, 0x02593c34, 0xf0024620, 0x2300fa80, 0x22084651, 0xf0024620, 0x2300fa7a, 
+    0x22034620, 0xf0022108, 0x480cfa74, 0xb3e08800, 0x4620230a, 0x21f02204, 0xfa6bf002, 0x22032301, 
+    0xe00d2108, 0xf3072200, 0xf3074004, 0xf30741c0, 0xf23c8040, 0x00040369, 0x00040546, 0x00040366, 
+    0xf0024620, 0x2301fa56, 0x22024620, 0xf0022104, 0x2301fa50, 0x4628e021, 0xfa4bf002, 0x46392301, 
+    0x4628220c, 0xfa45f002, 0x4649b2a3, 0x46282209, 0xfa3ff002, 0x46512301, 0x46282208, 0xfa39f002, 
+    0x46282301, 0x46192200, 0xe7ffe7a9, 0x46202300, 0x21042202, 0xfa2df002, 0x46202300, 0x47f0e8bd, 
+    0x21022201, 0xba25f002, 0x4c16b510, 0x21102204, 0xf0024620, 0x2801fa2c, 0x2203d016, 0x21084620, 
+    0xfa25f002, 0xd0112801, 0x46202202, 0xf0022104, 0x2801fa1e, 0x2201d00c, 0x21024620, 0xfa17f002, 
+    0xd0072801, 0xbd102001, 0xbd102003, 0xbd102005, 0xbd102004, 0xbd102002, 0x46032204, 0x21104802, 
+    0xb9f7f002, 0xf3074080, 0xf3074180, 0x47f0e92d, 0x23014cff, 0x46192200, 0xf0024620, 0x2301f9ea, 
+    0x21024620, 0xf002461a, 0x48f9f9e4, 0x5507f643, 0x76fff643, 0x2200462b, 0x30424631, 0xf9d9f002, 
+    0x1c7748f3, 0x463b2200, 0x46313044, 0xf9d1f002, 0xf64048ef, 0x22002888, 0x30464643, 0xf0024631, 
+    0x48ebf9c8, 0x09e2f241, 0x464b2200, 0x46313048, 0xf9bff002, 0x220048e6, 0x46314643, 0xf002304a, 
+    0x48e3f9b8, 0x461a2300, 0x304c4631, 0xf9b1f002, 0x220048df, 0x4631462b, 0xf002304e, 0x48dcf9aa, 
+    0x463b2200, 0x30504631, 0xf9a3f002, 0x220048d8, 0x4631462b, 0xf0023052, 0x48d5f99c, 0x463b2200, 
+    0x30544631, 0xf995f002, 0x220048d1, 0x46314643, 0xf0023056, 0x48cef98e, 0x464b2200, 0x30584631, 
+    0xf987f002, 0x220048ca, 0x46314643, 0xf002305a, 0x48c7f980, 0x461a2300, 0x305c4631, 0xf979f002, 
+    0x220048c3, 0x4631462b, 0xf002305e, 0x48c0f972, 0x463b2200, 0x30604631, 0xf96bf002, 0x220048bc, 
+    0x4631462b, 0xf0023062, 0x48b9f964, 0x463b2200, 0x30644631, 0xf95df002, 0x220048b5, 0x46314643, 
+    0xf0023066, 0x48b2f956, 0x464b2200, 0x30684631, 0xf94ff002, 0x220048ae, 0x46314643, 0xf002306a, 
+    0x48abf948, 0x461a2300, 0x306c4631, 0xf941f002, 0x220048a7, 0x4631462b, 0xf002306e, 0x48a4f93a, 
+    0x463b2200, 0x30704631, 0xf933f002, 0x220048a0, 0x4631462b, 0xf0023072, 0x489df92c, 0x463b2200, 
+    0x30744631, 0xf925f002, 0x22004899, 0x46314643, 0xf0023076, 0x4896f91e, 0x464b2200, 0x30784631, 
+    0xf917f002, 0x22004892, 0x46314643, 0xf002307a, 0x488ff910, 0x461a2300, 0x307c4631, 0xf909f002, 
+    0x2200488b, 0x4631462b, 0xf002307e, 0x4888f902, 0x463b2200, 0x30804631, 0xf8fbf002, 0xe8bd4620, 
+    0x230147f0, 0x21042202, 0xb8f3f002, 0x41f0e92d, 0x23014c7f, 0x1f242202, 0x46202104, 0xf8e9f002, 
+    0x46202301, 0x21082203, 0xf8e3f002, 0xf6434878, 0xf6435407, 0x462375ff, 0x46292200, 0xf0021c80, 
+    0x4873f8d8, 0x22001c6e, 0x1d004633, 0xf0024629, 0x486ff8d0, 0x2788f640, 0x463b2200, 0x46291d80, 
+    0xf8c7f002, 0xf241486a, 0x220008e2, 0x30084643, 0xf0024629, 0x4866f8be, 0x463b2200, 0x300a4629, 
+    0xf8b7f002, 0x23004862, 0x4629461a, 0xf002300c, 0x485ff8b0, 0x46232200, 0x300e4629, 0xf8a9f002, 
+    0x2200485b, 0x46294633, 0xf0023010, 0x4858f8a2, 0x46232200, 0x30124629, 0xf89bf002, 0x22004854, 
+    0x46294633, 0xf0023014, 0x4851f894, 0x463b2200, 0x30164629, 0xf88df002, 0x2200484d, 0x46294643, 
+    0xf0023018, 0x484af886, 0x463b2200, 0x301a4629, 0xf87ff002, 0x23004846, 0x4629461a, 0xf002301c, 
+    0x4843f878, 0x46232200, 0x301e4629, 0xf871f002, 0x2200483f, 0x46294633, 0xf0023020, 0x483cf86a, 
+    0x46232200, 0x30224629, 0xf863f002, 0x22004838, 0x46294633, 0xf0023024, 0x4835f85c, 0x463b2200, 
+    0x30264629, 0xf855f002, 0x22004831, 0x46294643, 0xf0023028, 0x482ef84e, 0x463b2200, 0x302a4629, 
+    0xf847f002, 0x2300482a, 0x4629461a, 0xf002302c, 0x4827f840, 0x46232200, 0x302e4629, 0xf839f002, 
+    0x22004823, 0x46294633, 0xf0023030, 0x4820f832, 0x46232200, 0x30324629, 0xf82bf002, 0x2200481c, 
+    0x46294633, 0xf0023034, 0x4819f824, 0x463b2200, 0x30364629, 0xf81df002, 0x22004815, 0x46294643, 
+    0xf0023038, 0x4812f816, 0x463b2200, 0x303a4629, 0xf80ff002, 0x2300480e, 0x4629461a, 0xf002303c, 
+    0x480bf808, 0x46232200, 0x303e4629, 0xf801f002, 0x22004807, 0x46294633, 0xf0013040, 0xe8bdfffa, 
+    0x480341f0, 0x22002301, 0x1e804619, 0x0000e002, 0xf2030a04, 0xbfedf001, 0x4c2fb570, 0xd0282803, 
+    0x28051d25, 0x2804d035, 0x2301d154, 0x22024620, 0xf0012104, 0x2301ffde, 0x22034620, 0xf0012108, 
+    0x2301ffd8, 0x21024628, 0xf001461a, 0x2301ffd2, 0x22004628, 0xf0014619, 0xf7ffffcc, 0xf7fffed7, 
+    0x2302fdd5, 0x21032200, 0xe8bd4620, 0xf0014070, 0x2300bfc0, 0x21034620, 0xf001461a, 0x2300ffba, 
+    0x22024620, 0xf0012104, 0x2300ffb4, 0x21082203, 0x2301e7ea, 0x22024620, 0xf0012104, 0x2301ffaa, 
+    0x22034620, 0xf0012108, 0x2300ffa4, 0x22014628, 0xf0012102, 0x2300ff9e, 0x21014628, 0xf001461a, 
+    0x2301ff98, 0x22004620, 0xf0012103, 0xe8bdff92, 0xe69b4070, 0x0000bd70, 0xf2030a00, 0x5ff0e92d, 
+    0x00044fbd, 0x0500f04f, 0x2301d005, 0x22044638, 0xf0012110, 0x48b8ff7e, 0x22002305, 0x1f802107, 
+    0xff77f001, 0x22024eb4, 0x4623211c, 0x46301eb6, 0xff6ff001, 0x46302301, 0x21202205, 0xff69f001, 
+    0x4800f240, 0x46402100, 0xfbe6f7df, 0x22072301, 0x1cb02180, 0xff5df001, 0x46402100, 0xfbdcf7df, 
+    0xf2402200, 0x1db031ff, 0xff61f001, 0xf8dfb194, 0x2c03828c, 0x9288f8df, 0x0709f06f, 0xa284f8df, 
+    0xb284f8df, 0x2c04d016, 0x2c05d014, 0x2c06d01e, 0xe033d049, 0xff78f003, 0x4b9d4a9c, 0xffc4f003, 
+    0x4b9d4a9c, 0xf8f4f004, 0xfcb4f003, 0xfc08f004, 0xe0354605, 0xff68f003, 0xf004463a, 0x4642fddc, 
+    0xf003464b, 0x4652ffb1, 0xe00a465b, 0xff5cf003, 0xf004463a, 0x4642fdd0, 0xf003464b, 0x4b8fffa5, 
+    0xf0034652, 0xf003fd85, 0x498dfc95, 0xfb26f004, 0xf004498c, 0xf004fc4d, 0x4605fbe3, 0x23004630, 
+    0x211c2202, 0xff05f001, 0x46302301, 0x21202205, 0xfefff001, 0x23004878, 0x21102204, 0xfef9f001, 
+    0xe8bd4628, 0xf0039ff0, 0x463aff2f, 0xfda3f004, 0x464b4642, 0xff78f003, 0x46524b7b, 0xe92de7d1, 
+    0x4e7a5ff0, 0x22032301, 0x21084605, 0xf0014630, 0x2302fee0, 0x22004630, 0xf0012103, 0xf1a6feda, 
+    0xf2480a02, 0x23000900, 0x220f4649, 0xf0014650, 0xf240fed0, 0x21004b00, 0xf7df4658, 0x2400fb4d, 
+    0x23004630, 0x21042202, 0xfec3f001, 0x46302301, 0x21042202, 0xfebdf001, 0xb2641c64, 0xdbef2c18, 
+    0x22004862, 0x31fff240, 0xf001300c, 0x4607fec0, 0x108bf2a0, 0xd3012822, 0x17a0f240, 0xd0022d01, 
+    0xd0022d05, 0x2300e00d, 0x2301e000, 0x22004630, 0xf0012103, 0x2300fe9e, 0x220f4649, 0xf0014650, 
+    0x2100fe98, 0xf7df4658, 0x2400fb17, 0x23004630, 0x21042202, 0xfe8df001, 0x46302301, 0x21042202, 
+    0xfe87f001, 0xb2641c64, 0xdbef2c18, 0x22004847, 0x31fff240, 0xf001300c, 0x2d01fe8a, 0xd0024604, 
+    0xd0082d05, 0x4638e018, 0xfeaef003, 0x460f4605, 0x70a0f640, 0x4638e006, 0xfea6f003, 0x460f4605, 
+    0x6080f643, 0xf0034360, 0x462afe9f, 0xf003463b, 0xf003fccf, 0x4680fbdf, 0xf0044640, 0x2300fb31, 
+    0x22034604, 0x21084630, 0xfe53f001, 0xe758b220, 0xb5102000, 0xfec2f7ff, 0x481fb281, 0xf00138ce, 
+    0x2001fe2e, 0xff5bf7ff, 0x481bb281, 0xf00138cc, 0x2004fe26, 0xfeb2f7ff, 0x4817b281, 0xf00138ca, 
+    0x2005fe1e, 0xfeaaf7ff, 0x4813b281, 0xf00138c8, 0x2006fe16, 0xfea2f7ff, 0x480fb281, 0x4010e8bd, 
+    0xf00138c6, 0x2301be0c, 0x22004819, 0xb5104619, 0xfe1ff001, 0x23014c08, 0x46192200, 0x46201ea4, 
+    0xfe17f001, 0x46202301, 0x461a2102, 0xfe11f001, 0x4010e8bd, 0x0000e7bc, 0xf23d0210, 0xcac08312, 
+    0x408d80a1, 0x9999999a, 0x3fe99999, 0x8bc169c2, 0x3fe182be, 0x5aee6320, 0x407c2142, 0x3fd99999, 
+    0x447a0000, 0x461c4000, 0x3fc99999, 0xf203f052, 0xf23d0004, 0x41f0e92d, 0x48a84607, 0x4616461c, 
+    0x46884420, 0xf2412300, 0x220c0100, 0xf0014605, 0x2e02fde0, 0x2300d01a, 0x22004628, 0xf0012103, 
+    0x489efdd8, 0x0100f242, 0x44201d80, 0xfdb7f001, 0x4639489a, 0x44201d00, 0xfdb1f001, 0x46414897, 
+    0x44203008, 0x41f0e8bd, 0xbda9f001, 0xe7e32301, 0x43f8e92d, 0x2100460c, 0x49909100, 0x1c8a1f09, 
+    0x1d0a18a7, 0x186518a6, 0xd07c2800, 0x46282300, 0x21022201, 0xfdadf001, 0x46282300, 0x461a2101, 
+    0xfda7f001, 0x46282100, 0xfd89f001, 0x46382100, 0xfd85f001, 0x46302100, 0xfd81f001, 0x2100487f, 
+    0x44201d00, 0xfd7bf001, 0x2100487c, 0x44201d80, 0xfd75f001, 0x21004879, 0x44203008, 0xfd6ff001, 
+    0x21004876, 0x4420300a, 0xfd69f001, 0x21004873, 0x4420300c, 0xfd63f001, 0x21004870, 0x4420300e, 
+    0xfd5df001, 0x2100486d, 0x44203010, 0xfd57f001, 0x2100486a, 0x44203012, 0xfd51f001, 0x21004867, 
+    0x44203014, 0xfd4bf001, 0x21004864, 0x44203016, 0xfd45f001, 0x21004861, 0x44203018, 0xfd3ff001, 
+    0x2100485e, 0x4420301e, 0xfd39f001, 0x2100485b, 0x44203020, 0xfd33f001, 0x21004858, 0x44203022, 
+    0xfd2df001, 0x21004855, 0x44203024, 0xfd27f001, 0x21004852, 0x44203026, 0xfd21f001, 0x2107484f, 
+    0x44203028, 0xe05ae000, 0xfd19f001, 0x2100484b, 0x4420302a, 0xfd13f001, 0x21004848, 0x4420302c, 
+    0xfd0df001, 0x21004845, 0x4420302e, 0xfd07f001, 0x21004842, 0x44203030, 0xfd01f001, 0x2100483f, 
+    0x44203032, 0xfcfbf001, 0x2100483c, 0x4420303c, 0xfcf5f001, 0x21004839, 0x4420303e, 0xfceff001, 
+    0x21004836, 0x44203044, 0xfce9f001, 0x30464833, 0x1f00f5b4, 0x4420d01f, 0x2101f248, 0xfcdff001, 
+    0x2100482e, 0x44203048, 0xfcd9f001, 0xf240482b, 0x304c1101, 0xf0014420, 0x4828fcd2, 0x304e2100, 
+    0xf0014420, 0x4825fccc, 0x30502100, 0xf0014420, 0xe8bdfcc6, 0x482283f8, 0x3101f248, 0x2301e7de, 
+    0x22004628, 0xf0014619, 0x2301fcd4, 0x22004638, 0xf0014619, 0xf240fcce, 0x46303900, 0x46492302, 
+    0xf0012208, 0xf44ffcc6, 0x90000080, 0xf8df4813, 0x1c808054, 0xe0064404, 0x4642210b, 0xf7df4668, 
+    0x2801f9d0, 0x2200d006, 0x21014620, 0xfcbff001, 0xd1f12801, 0x46492300, 0x46302208, 0xfca9f001, 
+    0x46282301, 0x461a2102, 0xfca3f001, 0x46382301, 0x461a2102, 0xfc9df001, 0x0000e7bb, 0xf303a404, 
+    0xf323a44a, 0xf203517e, 0x4605b5f0, 0xb1532000, 0x2d0b2400, 0xf240d301, 0x293d1001, 0xf440d301, 
+    0xb1147081, 0x2401e003, 0x2a12e7f3, 0x2a00dc01, 0xf440da01, 0xb10c7082, 0xdc012a18, 0xda012a00, 
+    0x7082f440, 0xd3012b07, 0x7084f440, 0x18f718ae, 0x428f1dbf, 0xf440dd01, 0x44297090, 0x44194411, 
+    0xdd01293c, 0x70a0f440, 0x2e18b124, 0xf440dd01, 0xbdf070c0, 0xdcfa2e12, 0xb40fbdf0, 0xa802b510, 
+    0xfc8ff000, 0xf000a80a, 0xf8bdfc5a, 0xf64f1042, 0xf00170ff, 0xea000101, 0xf8bd0241, 0xf0011040, 
+    0x43110101, 0x0241ea00, 0x103ef8bd, 0x0101f001, 0xea004311, 0xf8bd0141, 0xf000003c, 0x43080001, 
+    0x0046f8ad, 0xf000a812, 0xf8bdfcbe, 0x48fe1026, 0xfc15f001, 0xf8bd48fc, 0x1e80103a, 0xfc0ff001, 
+    0xf8bd48f9, 0x1d001046, 0xfc09f001, 0xf8bd48f6, 0x1c801068, 0xfc03f001, 0x2000bc10, 0xfb14f85d, 
+    0x4ff0e92d, 0x0903ea5f, 0xb0ab4690, 0x4607468b, 0x2000d01b, 0x46822120, 0xf000a815, 0x2114fe1f, 
+    0xf000a826, 0x2400fe1b, 0x21244625, 0xa81d462e, 0xfe14f000, 0x0f00f1ba, 0xf1b8d00d, 0xdd060f12, 
+    0x0006f1a8, 0xb2c02206, 0x2001e009, 0x2200e7e2, 0x00fff008, 0xf008e003, 0xf00900ff, 0xebab02ff, 
+    0x1a090107, 0xf0011a89, 0xf04f0cff, 0x07d30101, 0x2a06d101, 0xf8add301, 0x2a021098, 0xf8add301, 
+    0x2a0410a0, 0x2a06d305, 0x10a4f8ad, 0xf8add301, 0x4ace109c, 0x2a01403a, 0x2f0ad001, 0xf8addb01, 
+    0x2f021074, 0xf8addb01, 0x2f04108c, 0xf8addb01, 0x2f061086, 0xf8addb01, 0x2f081080, 0x2f0adb05, 
+    0x107af8ad, 0xf8addb01, 0x07c2106a, 0x2808d101, 0xf8add301, 0x28021054, 0xf8add301, 0x2804105c, 
+    0xf8add301, 0x28061060, 0x2808d305, 0x1064f8ad, 0xf8add301, 0xf8bd1058, 0xb9fb306a, 0xd00107c2, 
+    0xd2192808, 0xd2172812, 0x207af8bd, 0xd1012a01, 0xd211280a, 0x2080f8bd, 0xd1012a01, 0xd20b280c, 
+    0x2086f8bd, 0xd1012a01, 0xd205280e, 0x208cf8bd, 0xd1032a01, 0xd3012810, 0x106cf8ad, 0x207af8bd, 
+    0x0a02ea5f, 0x280ad103, 0xf8add301, 0xf8bd107c, 0xea5f2080, 0xd1030902, 0xd301280c, 0x1082f8ad, 
+    0x2086f8bd, 0x0802ea5f, 0x280ed103, 0xf8add301, 0xf8bd1088, 0xb91f708c, 0xd3012810, 0x108ef8ad, 
+    0x2074f8bd, 0x2812b9b2, 0xf1bad212, 0xd1010f01, 0xd20d280a, 0x0f01f1b9, 0x280cd101, 0xf1b8d208, 
+    0xd1010f01, 0xd203280e, 0xd1032f01, 0xd3012810, 0x1076f8ad, 0x0f00f1bc, 0xf1acd07d, 0xf00c0c01, 
+    0xea5f00ff, 0xd0017cc0, 0x040ff361, 0xd0f30840, 0x7cc0ea5f, 0x1e40d005, 0x441ff361, 0x00fff010, 
+    0xb92dd0ea, 0xf0101e80, 0xf36100ff, 0xd0e3050f, 0x4c15ea5f, 0x1e80d105, 0x451ff361, 0x00fff010, 
+    0xea5fd0da, 0xd17c4c14, 0xc09ef8bd, 0x0f00f1bc, 0xf8bdd10f, 0xf1bcc09c, 0xd10a0f00, 0xf8ad1e80, 
+    0xf361109e, 0xf010441f, 0xd0c500ff, 0x0c01ea5f, 0xf8bdd16b, 0xf1bcc09a, 0xd10f0f00, 0xc098f8bd, 
+    0x0f00f1bc, 0x1e80d10a, 0x109af8ad, 0x441ff361, 0x00fff010, 0xea5fd0b0, 0xd1560c01, 0xc05af8bd, 
+    0x0f00f1bc, 0xf8bdd10f, 0xf1bcc058, 0xd10a0f00, 0xf8ad1e80, 0xf361105a, 0xf010441f, 0xd09b00ff, 
+    0x0c01ea5f, 0xf8bdd141, 0xf1bcc056, 0xd10f0f00, 0xc054f8bd, 0x0f00f1bc, 0x1e80d10a, 0x1056f8ad, 
+    0x441ff361, 0x00fff010, 0xea5fd086, 0xd12c0c01, 0xc078f8bd, 0xe0d6e000, 0x0f00f1bc, 0xb97ad110, 
+    0xc076f8bd, 0x0f00f1bc, 0x1e80d10a, 0x1078f8ad, 0x441ff361, 0x00fff010, 0xea5fd089, 0xd1140c01, 
+    0xc06ef8bd, 0x0f00f1bc, 0xb953d10f, 0xc06cf8bd, 0x0f00f1bc, 0xf361d109, 0xf8ad441f, 0x1e80106e, 
+    0xe002e000, 0x00fff010, 0xf8bdd08f, 0xf1bcc0a6, 0xd10a0f00, 0xc0a4f8bd, 0x0f00f1bc, 0x1e80d105, 
+    0x10a6f8ad, 0x00fff010, 0xf8bdd094, 0xf1bcc0a2, 0xd10a0f00, 0xc0a0f8bd, 0x0f00f1bc, 0x1e80d105, 
+    0x10a2f8ad, 0x00fff010, 0xf8bdd084, 0xf1bcc066, 0xd10a0f00, 0xc064f8bd, 0x0f00f1bc, 0x1e80d105, 
+    0x1066f8ad, 0x00fff010, 0xf8bdd07d, 0xf1bcc062, 0xd10a0f00, 0xc060f8bd, 0x0f00f1bc, 0x1e80d105, 
+    0x1062f8ad, 0x00fff010, 0xf8bdd06d, 0xf1bcc05e, 0xd10a0f00, 0xc05cf8bd, 0x0f00f1bc, 0x1e80d105, 
+    0x105ef8ad, 0x00fff010, 0xf8bdd05d, 0xf1bcc090, 0xd10e0f00, 0xf8bdb96f, 0xb957708e, 0xf8ad1e80, 
+    0xf0101090, 0xe00300ff, 0xf303a238, 0x80000001, 0xf8bdd049, 0xb95f708a, 0x0f00f1b8, 0xf8bdd108, 
+    0xb92f7088, 0xf8ad1e80, 0xf010108a, 0xd03a00ff, 0x7084f8bd, 0xf1b9b95f, 0xd1080f00, 0x7082f8bd, 
+    0x1e80b92f, 0x1084f8ad, 0x00fff010, 0xf8bdd02b, 0xb95f707e, 0x0f00f1ba, 0xf8bdd108, 0xb92f707c, 
+    0xf8ad1e80, 0xf010107e, 0xd01c00ff, 0x709ef8bd, 0xf8bdbbf7, 0xbbdf709c, 0xc09af8bd, 0x0f00f1bc, 
+    0xf8bdd110, 0xf1bcc098, 0xd10b0f00, 0xf8ad1e80, 0xf010109e, 0xf8ad00ff, 0xd004109a, 0x0c01ea5f, 
+    0xbb2fd128, 0xe08fe000, 0xc05af8bd, 0x0f00f1bc, 0xf8bdd110, 0xf1bcc058, 0xd10b0f00, 0xf8ad1e80, 
+    0xf010109e, 0xf8ad00ff, 0xd07d105a, 0x0c01ea5f, 0xb96fd110, 0x7056f8bd, 0xf8bdb957, 0xb93f7054, 
+    0xf8ad1e80, 0xf010109e, 0xf8ad00ff, 0xe0001056, 0xd069e000, 0x709af8bd, 0xf8bdbb37, 0xbb1f7098, 
+    0xc05af8bd, 0x0f00f1bc, 0xf8bdd110, 0xf1bcc058, 0xd10b0f00, 0xf8ad1e80, 0xf010109a, 0xf8ad00ff, 
+    0xd051105a, 0x0c01ea5f, 0xb96fd10e, 0x7056f8bd, 0xf8bdb957, 0xb93f7054, 0xf8ad1e80, 0xf010109a, 
+    0xf8ad00ff, 0xd03f1056, 0x705af8bd, 0xf8bdb987, 0xb96f7058, 0x7056f8bd, 0xf8bdb957, 0xb93f7054, 
+    0xf8ad1e80, 0xf010105a, 0xf8ad00ff, 0xd02b1056, 0x709ef8bd, 0xf8bdbb4f, 0xbb37709c, 0xc078f8bd, 
+    0x0f00f1bc, 0xb982d111, 0xc076f8bd, 0x0f00f1bc, 0x1e80d10b, 0x109ef8ad, 0x00fff010, 0x1078f8ad, 
+    0xea5fd012, 0xd1120c01, 0xf8bdb97f, 0xb967706e, 0xf8bdb95b, 0xb947706c, 0xf8ad1e80, 0xf010109e, 
+    0xf8ad00ff, 0xe001106e, 0xe000e080, 0xf8bdd07e, 0xbb47709a, 0x7098f8bd, 0xf8bdbb2f, 0xf1bcc078, 
+    0xd1110f00, 0xf8bdb982, 0xf1bcc076, 0xd10b0f00, 0xf8ad1e80, 0xf010109a, 0xf8ad00ff, 0xd07e1078, 
+    0x0c01ea5f, 0xb977d10f, 0x706ef8bd, 0xb953b95f, 0x706cf8bd, 0x1e80b93f, 0x109af8ad, 0x00fff010, 
+    0x106ef8ad, 0xf8bdd06b, 0xbb47705a, 0x7058f8bd, 0xf8bdbb2f, 0xf1bcc078, 0xd1110f00, 0xf8bdb982, 
+    0xf1bcc076, 0xd10b0f00, 0xf8ad1e80, 0xf010105a, 0xf8ad00ff, 0xd0521078, 0x0c01ea5f, 0xb977d10f, 
+    0x706ef8bd, 0xb953b95f, 0x706cf8bd, 0x1e80b93f, 0x105af8ad, 0x00fff010, 0x106ef8ad, 0xf8bdd03f, 
+    0xbb577056, 0x7054f8bd, 0xf8bdbb3f, 0xf1bcc078, 0xd1110f00, 0xf8bdb982, 0xf1bcc076, 0xd10b0f00, 
+    0xf8ad1e80, 0xf0101056, 0xf8ad00ff, 0xd0261078, 0x0c01ea5f, 0xb987d111, 0x706ef8bd, 0xb963b96f, 
+    0x706cf8bd, 0xf8adb94f, 0xe0001056, 0x1e80e017, 0x106ef8ad, 0x0ffff010, 0xf8bdd011, 0xb9700078, 
+    0xf8bdb96a, 0xb9500076, 0x006ef8bd, 0xb933b938, 0x006cf8bd, 0xf8adb918, 0xf8ad1078, 0x2222106e, 
+    0xa80ca91d, 0xea90f000, 0x2214ab09, 0xe883a926, 0xa8040070, 0xea88f000, 0xe897af19, 0xaf15000f, 
+    0x000fe88d, 0x000fe897, 0xfc47f7ff, 0xe8bdb02b, 0xe92d8ff0, 0x460347f0, 0x0081eb01, 0x2a012500, 
+    0x4418561f, 0x1001f990, 0x6002f990, 0x4003f990, 0xd0704688, 0x46324623, 0xf7ff4638, 0x0005fbf5, 
+    0xb15cd169, 0x4db62300, 0xf242220d, 0x46280100, 0xf87ff001, 0xdd032f00, 0xe0022301, 0xe7f22301, 
+    0xf2412300, 0x220c0100, 0xf0014628, 0x2e00f872, 0x2301dd01, 0x2300e000, 0x0100f640, 0x4628220b, 
+    0xf867f001, 0xdd012c00, 0xe0002301, 0xf2402300, 0x220a4100, 0xf0014628, 0x4da1f85c, 0x210f2200, 
+    0x46283d82, 0xf001b2fb, 0x2200f854, 0x1ca8213f, 0x03fff008, 0xf84df001, 0xf6412208, 0x46287100, 
+    0xf001b2f3, 0x4896f846, 0x210f2200, 0xb2e330d6, 0xf83ff001, 0x46324623, 0x46384641, 0xfc20f7ff, 
+    0x488f4605, 0x210f2200, 0xf0013834, 0xf8dff840, 0xb240c230, 0xf1ac2801, 0xf10c0c0a, 0xd0020902, 
+    0xd0092804, 0x2301e014, 0x22074660, 0xf0012180, 0x2300f820, 0xe01be007, 0x46602300, 0x21802207, 
+    0xf817f001, 0x46482301, 0x21012200, 0xf811f001, 0x0008eb07, 0x44204430, 0x1f244c79, 0xdd01282d, 
+    0xe0002305, 0x46202304, 0x213c2202, 0xf801f001, 0x46294874, 0xffe3f000, 0xe8bd4628, 0x7b8287f0, 
+    0x71fff64f, 0x0201f002, 0x0342ea01, 0xf0027b02, 0x431a0201, 0x0342ea01, 0xf0027a82, 0x431a0201, 
+    0x0342ea01, 0xf0027a02, 0x431a0201, 0x0342ea01, 0xf0027982, 0x431a0201, 0x0342ea01, 0xf0027902, 
+    0x431a0201, 0x0342ea01, 0xf0027882, 0x431a0201, 0x0242ea01, 0xf0017801, 0x43110101, 0x20008241, 
+    0x7e824770, 0x71fff64f, 0x0201f002, 0x0342ea01, 0xf0027e02, 0x431a0201, 0x0342ea01, 0xf0027d82, 
+    0x431a0201, 0xea017c83, 0xf0030282, 0xea010301, 0x43130242, 0xea017c02, 0xf0020343, 0x431a0201, 
+    0x0342ea01, 0xf0027b82, 0x431a0201, 0x0342ea01, 0xf0027b02, 0x431a0201, 0x0342ea01, 0xf0027a82, 
+    0x431a0201, 0x0342ea01, 0xf0027a02, 0x431a0201, 0xea017983, 0xf0030242, 0x43130301, 0xea017902, 
+    0xf0020343, 0x431a0201, 0x0342ea01, 0xf0027882, 0x431a0201, 0x0242ea01, 0xf0017801, 0x43110101, 
+    0x200083c1, 0x7f024770, 0x71fff64f, 0x0201f002, 0x0342ea01, 0xf0027e82, 0x431a0201, 0x0342ea01, 
+    0xf0027e02, 0x431a0201, 0x0342ea01, 0xf0027d82, 0x431a0201, 0x0342ea01, 0xf0027d02, 0x431a0201, 
+    0x0342ea01, 0xf0027c82, 0x431a0201, 0x0342ea01, 0xf0027c02, 0x431a0201, 0x0342ea01, 0xf0027b82, 
+    0x431a0201, 0x0342ea01, 0xf0027b02, 0x431a0201, 0x0342ea01, 0xf0027a82, 0x431a0201, 0x0342ea01, 
+    0xf0027a02, 0x431a0201, 0x0342ea01, 0xf0027982, 0x431a0201, 0x0342ea01, 0xf0027902, 0x431a0201, 
+    0x0342ea01, 0xf0027882, 0x431a0201, 0x0242ea01, 0xf0017801, 0x43110101, 0x20008401, 0x00004770, 
+    0xf303a14a, 0xf203519e, 0x4606b570, 0xf984f000, 0xf1066805, 0xf020000b, 0x42b40407, 0x2000bf98, 
+    0x462bd915, 0xb1ba686a, 0x42a06810, 0xf104d310, 0x42880108, 0x6850bf3c, 0xd3076058, 0x19106851, 
+    0x68116041, 0x60011b09, 0x60146058, 0xbd701d10, 0x68524613, 0xd1e72a00, 0x46284621, 0xf964f000, 
+    0xd1de2800, 0xb570bd70, 0x1f054604, 0xf954f000, 0x2c006800, 0x6844bf18, 0x2c00d01b, 0x42acbf18, 
+    0x4620bf3c, 0xd3f86864, 0x180a6801, 0xbf1842aa, 0xd1036045, 0x4605682a, 0x60014411, 0x19416828, 
+    0xbf1842a1, 0xd104606c, 0x60696861, 0x44086821, 0xbd706028, 0x0320f1b2, 0xf1c2d50a, 0xfa010320, 
+    0xfa20f102, 0xfa00f303, 0xea41f002, 0x47700103, 0xf103fa00, 0x0000f04f, 0xf1b24770, 0xd50a0320, 
+    0x0320f1c2, 0xf002fa20, 0xf303fa01, 0xf102fa21, 0x0003ea40, 0xfa214770, 0xf04ff003, 0x47700100, 
+    0xe92d4010, 0xe1b040c1, 0xe02440a3, 0x5a000002, 0xe2700000, 0xe2611000, 0x32411001, 0xe1130003, 
+    0x5a000002, 0xe2722000, 0xe2633000, 0x32433001, 0xeb0000a1, 0xe3140101, 0x0a000002, 0xe2700000, 
+    0xe2611000, 0x32411001, 0xe3140102, 0x0a000002, 0xe2722000, 0xe2633000, 0x32433001, 0xe8bd8010, 
+    0xe3520003, 0x9a000017, 0xe210c003, 0x0a000008, 0xe4d13001, 0xe35c0002, 0xe082200c, 0x94d1c001, 
+    0xe4c03001, 0x34d13001, 0x94c0c001, 0xe2422004, 0x34c03001, 0xe2113003, 0x0a000012, 0xe2522008, 
+    0x3a000004, 0xe4913004, 0xe2522008, 0xe491c004, 0xe8a01008, 0xeafffff9, 0xe2922004, 0x54913004, 
+    0x54803004, 0xe1a00000, 0xe1b02f82, 0x24d13001, 0x24d1c001, 0x44d12001, 0x24c03001, 0x24c0c001, 
+    0x44c02001, 0xe12fff1e, 0xe92d4010, 0xe2522020, 0x3a000005, 0xe8b15018, 0xe2522020, 0xe8a05018, 
+    0xe8b15018, 0xe8a05018, 0x2afffff9, 0xe1b0ce02, 0x28b15018, 0x28a05018, 0x48b10018, 0x48a00018, 
+    0xe8bd4010, 0xe1b0cf02, 0x24913004, 0x24803004, 0x012fff1e, 0xe1b02f82, 0x20d130b2, 0x44d12001, 
+    0x20c030b2, 0x44c02001, 0xe12fff1e, 0x03fff002, 0x2203ea43, 0x4202ea42, 0xba55f000, 0x0200f04f, 
+    0x4613b500, 0x46964694, 0xbf223920, 0x500ce8a0, 0x500ce8a0, 0x0120f1b1, 0xaff7f4bf, 0xbf280709, 
+    0x500ce8a0, 0xc00cbf48, 0xeb04f85d, 0xbf280089, 0x2b04f840, 0x4770bf08, 0xf820bf48, 0xf0112b02, 
+    0xbf184f80, 0x2b01f800, 0x00004770, 0xe3100003, 0xe92d4010, 0xe1a04000, 0x03110003, 0x1a00000a, 
+    0xe59fe04c, 0xe2522004, 0xba000006, 0xe4913004, 0xe043c00e, 0xe1ccc003, 0xe01cc38e, 0x04803004, 
+    0x0afffff7, 0xe2411004, 0xe2822004, 0xe2522001, 0xba000005, 0xe4d13001, 0xe3530000, 0xe4c03001, 
+    0x1afffff9, 0xe1a01002, 0xfb0000fc, 0xe1a00004, 0xe8bd8010, 0x01010101, 0x47704800, 0x0004e944, 
+    0x47704770, 0x47704770, 0x4604b538, 0x2000460a, 0xf0004669, 0x2800fa3c, 0x4602d005, 0x99004620, 
+    0xfa0af000, 0xbd382001, 0xf0002001, 0xb5f8ba1d, 0xfa22f000, 0x20004605, 0x2010460c, 0x4606bf00, 
+    0x42a019a8, 0x4632d90d, 0x20004669, 0xfa1ff000, 0xbf080007, 0xfa08f000, 0x42a09800, 0x4605bf18, 
+    0xf7ff19c4, 0x6005ffc9, 0x1df04607, 0x0007f020, 0x46281946, 0xf80af000, 0xd00642b4, 0x68384631, 
+    0xe8bd1ba2, 0xf00040f8, 0xbdf8b9d7, 0x60012100, 0x1001e9c0, 0x20104770, 0x00004770, 0xe92d4070, 
+    0xe1a04003, 0xe1a05002, 0xe1a03001, 0xe1a02000, 0xe3540000, 0x11a0c004, 0x01a0c005, 0xe16fef1c, 
+    0xe28e0001, 0xe1a0c01c, 0x127ee03f, 0x027ee01f, 0x4a000094, 0xe3530000, 0x116f1f13, 0x016f1f12, 
+    0x1271103f, 0x0271101f, 0xe051600e, 0x4a000092, 0x52760004, 0x5a000093, 0xe24e0020, 0xe3500004, 
+    0xd1a01035, 0xd18cc001, 0xe28f1f9f, 0xe1a0ce2c, 0xe35e001f, 0xe791c10c, 0x824ee020, 0xe26e6020, 
+    0x8a000048, 0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 0xe2611000, 
+    0x32411001, 0xe081019c, 0xe08cc001, 0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 
+    0xe2700000, 0xe2611000, 0x32411001, 0xe3530000, 0xe081019c, 0xe08cc001, 0x0a000009, 0xe081059c, 
+    0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 0xe2611000, 0x32411001, 0xe081019c, 
+    0xe08cc001, 0xe080129c, 0xe3a01000, 0xe0a1039c, 0xe1a00e30, 0xe1a04611, 0xe1800004, 0xe1a01e31, 
+    0xe0846590, 0xe0522006, 0xe0244591, 0xe0c33004, 0xe3530001, 0x31520005, 0x38bd8070, 0xe086429c, 
+    0xe3a04000, 0xe0a4639c, 0xe26ec020, 0xe1a06e36, 0xe1a03c14, 0xe1866003, 0xe3a03000, 0xe1a04e34, 
+    0xe08ce596, 0xe0900006, 0xe0a11004, 0xe042200e, 0xe1520005, 0x38bd8070, 0xe2900001, 0xe2a11000, 
+    0xe0422005, 0xe052c005, 0x21a0200c, 0xe2b00000, 0xe2a11000, 0xe052c005, 0x21a0200c, 0xe2b00000, 
+    0xe2a11000, 0xe8bd8070, 0xe080159c, 0xe3a01000, 0xe0a1049c, 0xe1a01611, 0xe1a06e30, 0xe1811006, 
+    0xe26e6020, 0xe2611000, 0xe1a00610, 0xe2700000, 0x32411001, 0xe081019c, 0xe08cc001, 0xe080159c, 
+    0xe3a01000, 0xe0a1049c, 0xe1a01611, 0xe1a06e30, 0xe1811006, 0xe26e6020, 0xe2611000, 0xe1a00610, 
+    0xe2700000, 0x32411001, 0xe081019c, 0xe08cc001, 0xe24cc001, 0xe080129c, 0xe3a01000, 0xe0a1039c, 
+    0xe1a00e31, 0xe0816590, 0xe0522006, 0xe0211490, 0xe0c33001, 0xe1530004, 0x01520005, 0x33a01000, 
+    0x38bd8070, 0xe081629c, 0xe3a06000, 0xe0a6139c, 0xe3a01000, 0xe1a06e36, 0xe08ce596, 0xe0800006, 
+    0xe052200e, 0xe02ec496, 0xe0c3300e, 0xe1530004, 0x01520005, 0x38bd8070, 0xe2800001, 0xe0522005, 
+    0xe0c33004, 0xe8bd8070, 0xe92d000c, 0xe3a01000, 0xe3a00000, 0xe1a00000, 0xe8bd807c, 0xe3a01000, 
+    0xe3a00000, 0xe8bd8070, 0xe266e020, 0xe3a00000, 0xe3a01000, 0xe1a04614, 0xe1a0ce35, 0xe1a05615, 
+    0xe184400c, 0xe052e005, 0xe0d3c004, 0xe0a00000, 0x21a0300c, 0x21a0200e, 0xe2566001, 0x38bd8070, 
+    0xe1b040a4, 0xe1a05065, 0xeafffff5, 0xf0f0f0f0, 0xe38e38e3, 0xd79435e5, 0xcccccccc, 0xc30c30c3, 
+    0xba2e8ba2, 0xb21642c8, 0xaaaaaaaa, 0xa3d70a3d, 0x9d89d89d, 0x97b425ed, 0x92492492, 0x8d3dcb08, 
+    0x88888888, 0x84210842, 0x80000000, 0xf000b510, 0x6800f82f, 0xb510bd10, 0xf0004604, 0x6004f829, 
+    0xf04fbd10, 0x29040200, 0x8012f0c0, 0x0c03f010, 0xada6f43f, 0x0c04f1cc, 0x0f02f1bc, 0xf800bf18, 
+    0xbfa82b01, 0x2b02f820, 0x010ceba1, 0xbd98f7ff, 0x7cc1ea5f, 0xf800bf24, 0xf8002b01, 0xbf482b01, 
+    0x2b01f800, 0x00004770, 0x47704800, 0x0004e93c, 0x47704800, 0x0004e93c, 0x6843468c, 0xbf182b00, 
+    0xbf38428b, 0xd3f84618, 0x44186803, 0xd0074288, 0x0003f10c, 0x0007f020, 0x1a411d00, 0x46011a52, 
+    0x600a1d08, 0xbc6ff7ff, 0xf000b510, 0xe8bdf85f, 0xf0004010, 0x0000b855, 0x46694b12, 0x5280f500, 
+    0x601a428a, 0x4611d801, 0x60194770, 0xb5304770, 0x466b4d0c, 0x5380f5a3, 0x4422682c, 0xd80f429a, 
+    0xf5021a9b, 0xeb035080, 0xeb0273d3, 0x42980363, 0x4618d900, 0xf0201dc0, 0x600c0207, 0x602a1b10, 
+    0x0000bd30, 0x0004127c, 0x46754770, 0xffacf7ff, 0x000546ae, 0x46534669, 0x0007f020, 0xb0184685, 
+    0xf001b520, 0xe8bdeab8, 0xf04f4020, 0xf04f0600, 0xf04f0700, 0xf04f0800, 0xf0210b00, 0x46ac0107, 
+    0x09c0e8ac, 0x09c0e8ac, 0x09c0e8ac, 0x09c0e8ac, 0x4770468d, 0xf3af4604, 0x46208000, 0xfe49f7d6, 
+    0xd0012800, 0xb82af000, 0x00004770, 0x2801b510, 0x2100d005, 0xf000a003, 0x2001f827, 0xa109bd10, 
+    0x0000e7f8, 0x52474953, 0x4d454d54, 0x754f203a, 0x666f2074, 0x61656820, 0x656d2070, 0x79726f6d, 
+    0x00000000, 0x6548203a, 0x6d207061, 0x726f6d65, 0x6f632079, 0x70757272, 0x00646574, 0x20184901, 
+    0xe7fedfab, 0x00020026, 0x4605b570, 0x200a460c, 0x1c6de000, 0xf811f000, 0x7828b135, 0xd1f82800, 
+    0x1c64e002, 0xf809f000, 0x7820b114, 0xd1f82800, 0x4070e8bd, 0xf3af200a, 0xb5088000, 0xf88d4669, 
+    0x20030000, 0xbd08dfab, 0xe92d0003, 0xe59f0050, 0xe580e000, 0xe59f004c, 0xe5901000, 0xe3510000, 
+    0x1a000001, 0xe59f1040, 0xe5801000, 0xe2811001, 0xe5801000, 0xe59f0034, 0xee151f10, 0xe5801000, 
+    0xe59f002c, 0xee161f10, 0xe5801000, 0xe59f0024, 0xee151f11, 0xe5801000, 0xe8bd0003, 0xe25ef008, 
+    0xe320f000, 0xf000300c, 0xf0003010, 0xdead0000, 0xf0003020, 0xf0003024, 0xf0003028, 0xf04fb500, 
+    0xee116060, 0xea011f30, 0xee010100, 0xee111f30, 0xf3bf0f30, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 
+    0xf3bf0f10, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f30, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 
+    0xf3bf0f11, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f31, 0xf85d8f6f, 0x4770eb04, 0xee16b500, 
+    0xf3bf0f10, 0xf85d8f6f, 0x4770eb04, 0xee16b500, 0xf3bf0f50, 0xf85d8f6f, 0x4770eb04, 0x5ffce92d, 
+    0x4601468a, 0x0000f04f, 0x2b01f811, 0x03bbf04f, 0xd128429a, 0x2b01f811, 0x03a7f04f, 0xd122429a, 
+    0x2b01f811, 0xd11e4282, 0x2b01f811, 0xd11a4282, 0xf04f4650, 0xf04f0a00, 0x5c8c0200, 0x050aea84, 
+    0x06fff005, 0x5016f830, 0x261aea4f, 0x0a06ea85, 0x0201f102, 0xdbf02a0a, 0xf04f5a8c, 0x45540001, 
+    0xf04fd001, 0xe8bd0000, 0x00009ffc, 0xe92d500f, 0xe14fc000, 0xe92d1000, 0xe59f0028, 0xe5901000, 
+    0xe201103f, 0xe1a01201, 0xe59f201c, 0xe0822001, 0xe5920000, 0xe8bd1000, 0xe16ff00c, 0xe8bd500f, 
+    0xe25ef004, 0xe320f000, 0xf0001014, 0xf0001104, 0x5ff0e92d, 0x7f80f5b2, 0x2a80d003, 0x2a40d004, 
+    0xf8dfd005, 0xe00490f8, 0x90f4f8df, 0xf8dfe001, 0xea4f90f4, 0xea4f0a52, 0x880c0b92, 0x4b02f823, 
+    0xf8238804, 0xf8314b02, 0xf823401b, 0xf8304b02, 0xf823401b, 0xf04f4b02, 0xf8190701, 0xf8315007, 
+    0xf8234015, 0xf8304b02, 0xf8234015, 0xebaa4b02, 0xf8310505, 0xf1c44015, 0xf8230400, 0xf8304b02, 
+    0xf8234015, 0xf1074b02, 0x455f0701, 0xafe5f6ff, 0x9ff0e8bd, 0x5ff0e92d, 0x7f80f5b1, 0x2980d003, 
+    0x2940d004, 0xf8dfd005, 0xe0049074, 0x9070f8df, 0xf8dfe001, 0xea4f9070, 0xea4f0a51, 0xf04f0b91, 
+    0xf9300700, 0x801c4b02, 0x4b02f930, 0xf1078014, 0xf9300701, 0xf8234b02, 0xf930401b, 0xf8226b02, 
+    0xf819601b, 0xf9305007, 0xf8234b02, 0xf9304015, 0xf8226b02, 0xebaa6015, 0xf9300505, 0xf1c44b02, 
+    0xf8230400, 0xf9304015, 0xf8226b02, 0xf1076015, 0x455f0701, 0xafe5f6ff, 0x9ff0e8bd, 0x0002e160, 
+    0x0002e1a0, 0x0002e1c0, 0x5ff0e92d, 0x0a00f04f, 0x4694468b, 0x1000f9b0, 0x2002f9b0, 0x0302eb01, 
+    0x5004f9b0, 0x6006f9b0, 0x0706eb05, 0x0806eba5, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 
+    0x0800f1c7, 0x0705eba6, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0402eba1, 0x0706eb05, 
+    0x0806eba5, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb04, 
+    0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0301eba2, 0x0706eb05, 0x0806eba5, 0x0907eb03, 0x9b04f84c, 
+    0x0908eb03, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 
+    0x0302eb01, 0x0400f1c3, 0x0706eb05, 0x0806eba5, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 
+    0x0800f1c7, 0x0705eba6, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0008f100, 0x0a01f10a, 
+    0xf6ff45da, 0xe8bdaf87, 0x00009ff0, 0xe92d500f, 0xe14fc000, 0xe92d1000, 0xe59f0028, 0xe5901000, 
+    0xe201103f, 0xe1a01201, 0xe59f201c, 0xe0822001, 0xe5920000, 0xe8bd1000, 0xe16ff00c, 0xe8bd500f, 
+    0xe25ef004, 0xe320f000, 0xf000100c, 0xf0001104, 0x5ffce92d, 0x0300f04f, 0x4023f850, 0x4023f841, 
+    0x0301f103, 0xf6ff4293, 0xe8bdaff7, 0xe92d9ffc, 0xf04f5ffc, 0x2b000500, 0xf1c3da02, 0xe00b0300, 
+    0x4025f850, 0xf403fa04, 0x4025f841, 0x0501f105, 0xf6ff4295, 0xe00aaff5, 0x4025f850, 0xf403fa44, 
+    0x4025f841, 0x0501f105, 0xf6ff4295, 0xe8bdaff5, 0xe92d9ffc, 0xf04f5ffc, 0xf8300300, 0xf8214013, 
+    0xf1034013, 0x42930301, 0xaff7f6ff, 0x9ffce8bd, 0x5ffce92d, 0x0300f04f, 0x4013f930, 0x4023f841, 
+    0x0301f103, 0xf6ff4293, 0xe8bdaff7, 0xe92d9ffc, 0xf04f5ff0, 0xf9300500, 0xfa044b02, 0xf841f403, 
+    0xf1054b04, 0x42950501, 0xaff5f6ff, 0x9ff0e8bd, 0x5ffce92d, 0x0701f1a3, 0x0601f04f, 0xf607fa06, 
+    0x0500f04f, 0x4025f850, 0xfa444434, 0xf821f403, 0xf1054015, 0x42950501, 0xaff4f6ff, 0x9ffce8bd, 
+    0xe92d5ffc, 0xeafffffe, 0xe8bd9ffc, 0x6800b500, 0xb500bd00, 0xbd006001, 0x8800b500, 0xb500bd00, 
+    0xbd008001, 0x41f0e92d, 0xea246804, 0xfa030401, 0xea05f502, 0xea440501, 0x60040405, 0x81f0e8bd, 
+    0x41f0e92d, 0xea006800, 0xfa200001, 0xe8bdf002, 0xe92d81f0, 0x880441f0, 0x0401ea24, 0xf502fa03, 
+    0x0501ea05, 0x0405ea44, 0xe8bd8004, 0xe92d81f0, 0x880041f0, 0x0001ea00, 0xf002fa20, 0x81f0e8bd, 
+    0xe59f1150, 0xe5910000, 0xe590e000, 0xe59f0148, 0xe8be0002, 0xe5801000, 0xe8be0001, 0xe16ff000, 
+    0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 0xef000000, 0xe12fff1e, 0xe28ee004, 0xe92d0001, 
+    0xe94d2000, 0xe320f000, 0xe24dd004, 0xe8bd0001, 0xe9204000, 0xe1a0e000, 0xe8bd0001, 0xe94e7fff, 
+    0xe320f000, 0xe24ee03c, 0xe14f0000, 0xe92e0001, 0xe59f00e4, 0xe5900000, 0xe92e0001, 0xe59f10d4, 
+    0xe5910000, 0xe580e000, 0xe59f00d0, 0xe1a0e00f, 0xe12fff10, 0xe59f10bc, 0xe5910000, 0xe590e000, 
+    0xe59f00b4, 0xe8be0002, 0xe5801000, 0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 
+    0xe25ef004, 0xe92d0001, 0xe94d2000, 0xe320f000, 0xe24dd004, 0xe8bd0001, 0xe9204000, 0xe1a0e000, 
+    0xe8bd0001, 0xe94e7fff, 0xe320f000, 0xe24ee03c, 0xe14f0000, 0xe92e0001, 0xe59f005c, 0xe5900000, 
+    0xe92e0001, 0xe59f104c, 0xe5910000, 0xe580e000, 0xe59f004c, 0xe1a0e00f, 0xe12fff10, 0xe59f003c, 
+    0xe1a0e00f, 0xe12fff10, 0xe59f1028, 0xe5910000, 0xe590e000, 0xe59f0020, 0xe8be0002, 0xe5801000, 
+    0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 0x00041208, 0x00041258, 
+    0x00025ce7, 0x00025b77, 0x41f0e92d, 0x460c4603, 0xea218819, 0x80190104, 0x0104ea41, 0x42806810, 
+    0x8019dcfc, 0x81f0e8bd, 0x41f0e92d, 0xea45880d, 0x800d0502, 0x0502ea25, 0x4284681c, 0x800ddcfc, 
+    0x81f0e8bd, 0xe92d0003, 0xe59f0034, 0xe59f1034, 0xe5801000, 0xe59f0030, 0xee151f31, 0xe5801000, 
+    0xe59f0028, 0xee151f30, 0xe5801000, 0xe59f0020, 0xee161f50, 0xe5801000, 0xe8bd0003, 0xe25ef004, 
+    0xe320f000, 0xf0003010, 0xfec0dead, 0xf000302c, 0xf0003030, 0xf0003034, 0x5ffce92d, 0xf1a59d0d, 
+    0xf04f0c05, 0xfa0b0b01, 0xea4ffa05, 0xb40c0a9a, 0x9a10b403, 0xf1009800, 0xf04f0104, 0xf84d0e00, 
+    0xf04fcd04, 0xb4040900, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 
+    0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 
+    0xf8414413, 0xf840c03a, 0xeb02403a, 0xf84002cb, 0xf8417b08, 0xf1098b08, 0x45d10901, 0xafd4f6ff, 
+    0x00caeb00, 0x01caeb01, 0xf10ebc04, 0x45de0e01, 0xafc7f6ff, 0x0b4bea4f, 0x0a5aea4f, 0xcb04f85d, 
+    0x0c01f1ac, 0x0f00f1bc, 0x9800dcb4, 0x0104f100, 0x0e00f04f, 0x2982f645, 0x6803b404, 0x503af850, 
+    0xf851680c, 0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 0xf8400606, 0xf841503a, 0xf840603a, 
+    0xf8417b08, 0xeb028b08, 0x680302cb, 0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba30806, 
+    0xeba40505, 0x68130606, 0x0545ea4f, 0x0646ea4f, 0xfc13fb35, 0xf403fb35, 0xcc03fb36, 0x0600f1c6, 
+    0x4413fb36, 0xc03af841, 0x403af840, 0x120beb02, 0x7b08f840, 0x8b08f841, 0xf8506803, 0x680c503a, 
+    0x603af851, 0x0705eba3, 0x0806eba4, 0x4426441d, 0x0307eb08, 0x0807eba8, 0x0343ea4f, 0x0848ea4f, 
+    0xf309fb33, 0xf809fb38, 0x303af840, 0x803af841, 0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 
+    0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 
+    0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 0xf8414413, 0xf840c03a, 0xeb02403a, 0xf840120b, 
+    0xf8417b08, 0x68038b08, 0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba50806, 0xeba40503, 
+    0xf8410606, 0xf840503a, 0xf840603a, 0xf8417b08, 0x68038b08, 0x503af850, 0xf851680c, 0xeb03603a, 
+    0xeb040705, 0xeba30806, 0xeba40505, 0x68130606, 0x0545ea4f, 0x0646ea4f, 0xfc13fb35, 0xf403fb35, 
+    0xcc03fb36, 0x0600f1c6, 0x4413fb36, 0xc03af841, 0x403af840, 0x120beb02, 0x7b08f840, 0x8b08f841, 
+    0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0806eba4, 0x4426441d, 0x0307eb08, 0x0807eba8, 
+    0x0343ea4f, 0x0848ea4f, 0xf309fb33, 0xf809fb38, 0x0300f1c3, 0x803af840, 0x303af841, 0x5b08f840, 
+    0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 0x0606eba4, 
+    0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 0xf8414413, 
+    0xf840c03a, 0xeb02403a, 0xf84002cb, 0xf8417b08, 0xeb008b08, 0xeb0100ca, 0xbc0401ca, 0x0e01f10e, 
+    0xf6ff45de, 0xea4faee9, 0xea4f0b4b, 0x98000a5a, 0x0104f100, 0x0800f04f, 0x2982f645, 0xf8506803, 
+    0x680c503a, 0x603af851, 0x0705eb03, 0x0206eb04, 0x0505eba3, 0x0606eba4, 0x503af840, 0x603af841, 
+    0x7b08f840, 0x2b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0206eba4, 0x4426441d, 
+    0x0307eb02, 0x0207eba2, 0x0343ea4f, 0x0242ea4f, 0xf309fb33, 0xf209fb32, 0x303af840, 0x203af841, 
+    0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0206eb04, 0x0503eba5, 
+    0x0606eba4, 0x503af841, 0x603af840, 0x7b08f840, 0x2b08f841, 0xf8506803, 0x680c503a, 0x603af851, 
+    0x0705eba3, 0x0206eba4, 0x4426441d, 0x0307eb02, 0x0207eba2, 0x0343ea4f, 0x0242ea4f, 0xf309fb33, 
+    0xf209fb32, 0x0300f1c3, 0x203af840, 0x303af841, 0x5b08f840, 0x6b08f841, 0x00caeb00, 0x01caeb01, 
+    0x0801f108, 0xf6ff45d8, 0xea4faf89, 0x98000b4b, 0x0104f100, 0x0800f04f, 0x2b08f850, 0x3b08f850, 
+    0x4b08f850, 0xf8516805, 0xf8516b08, 0xf8517b08, 0xf8d19b08, 0xeb02a000, 0xeba20c04, 0xeb060204, 
+    0xeba60409, 0xeb030609, 0xeba30905, 0xeb070305, 0xeba7050a, 0xeb0c070a, 0xebac0a09, 0xeb040c09, 
+    0xeba40905, 0xeb020405, 0xeba20507, 0xeb060207, 0xeba60703, 0xf8400603, 0xf8402908, 0xf8405908, 
+    0xf840c908, 0xf841ab20, 0xf8417908, 0xf8416908, 0xf8414908, 0xf1089b20, 0x45d80801, 0xafbcf6ff, 
+    0x058bea4f, 0xf985fab5, 0x091ef1c9, 0x0c1ff1c9, 0x0b59ea4f, 0x0b01f10b, 0x0901f009, 0xbc0344cb, 
+    0xf850bc0c, 0xf8509b04, 0xf850ab04, 0xf8504b04, 0xeb09790c, 0xeba9060a, 0xf04f090a, 0xfa460800, 
+    0xfa49f60b, 0xfa44f90b, 0xfa47f40b, 0x6016f70b, 0x8000f8c3, 0x9025f842, 0x8025f843, 0x0655ea4f, 
+    0xf842442e, 0xf8434026, 0xf1c77026, 0xf8420700, 0xf8434015, 0xf8dd7015, 0xf04fe030, 0xb4200402, 
+    0x6034f850, 0x0004f100, 0x7034f850, 0x0004f100, 0xf90cfa04, 0xf9a9fa99, 0x0109eba5, 0xf1a1fa91, 
+    0xf10cfa21, 0x01fef001, 0x8031f850, 0x0004f100, 0x1031f850, 0x000cf1a0, 0x0a08eb06, 0x0608eba6, 
+    0x0801eb07, 0x0701eba7, 0x1029f85e, 0x0767ea4f, 0xf511fb36, 0x0600f1c6, 0x5501fb38, 0xf601fb36, 
+    0x0a6aea4f, 0x6611fb38, 0x0105eb0a, 0x0a05ebaa, 0x0806eb07, 0x0706eba7, 0xf10bfa41, 0xf80bfa48, 
+    0xfa0bfa4a, 0xf70bfa47, 0x1029f842, 0x8029f843, 0xeb09bc20, 0xf8420605, 0xf843a026, 0xeba57026, 
+    0xf1c70609, 0xf8420700, 0xf843a026, 0x442e7026, 0x0800f1c8, 0x1026f842, 0x8026f843, 0x0402f104, 
+    0xdb9c42ac, 0x5ffce8bd, 0x00004770, 0x5ffce92d, 0xf04f9e0d, 0xfa0b0b01, 0xea4ff506, 0xf1a60555, 
+    0xf1c90902, 0x68060c1f, 0x9025f850, 0x4015f850, 0x7015f851, 0x0700f1c7, 0x0a09eba6, 0xea4f44b1, 
+    0xea4f0a6a, 0xf8420969, 0xf8429b04, 0xf842ab04, 0xf8424b04, 0xf8dd790c, 0xf04fe030, 0xfa040402, 
+    0xfa99f90c, 0xf850f9a9, 0xf8513029, 0xeba58029, 0xf8500609, 0xf851a026, 0xeb037026, 0xeba3060a, 
+    0xeba8030a, 0x44b80a07, 0x7029f85e, 0x0a6aea4f, 0xfb07fb33, 0xf317fb33, 0xbb17fb38, 0x0800f1c8, 
+    0x0666ea4f, 0x3307fb38, 0x0806eb03, 0x0303eba6, 0x060aeb0b, 0x0b0aebab, 0x8034f842, 0x0204f102, 
+    0x6034f842, 0x0204f102, 0x0809eba5, 0xf8a8fa98, 0xf80cfa28, 0x08fef008, 0x3038f842, 0x0204f102, 
+    0xb038f842, 0x020cf1a2, 0x0402f104, 0xdbb642ac, 0xf1a59d0d, 0xf04f0c01, 0xfa0a0a01, 0xea4ffb05, 
+    0xb4040b9b, 0x98009a0d, 0x0e00f04f, 0x0b5bea4f, 0xcd04f84d, 0x1b08f850, 0x3b08f850, 0x4b08f850, 
+    0x5914f850, 0x6b08f850, 0x7b08f850, 0x8b08f850, 0x9904f850, 0x0c03eb01, 0x0103eba1, 0x0307eb06, 
+    0x0607eba6, 0x0705eb04, 0x0405eba4, 0x0509eb08, 0x0809eba8, 0x0907eb0c, 0x0c07ebac, 0x0705eb03, 
+    0x0305eba3, 0x0508eb01, 0x0108eba1, 0x0804eb06, 0x0604eba6, 0x5908f840, 0xc908f840, 0x1908f840, 
+    0x9b1cf840, 0x6908f840, 0x3908f840, 0x8908f840, 0x7b1cf840, 0x0e01f10e, 0xf6ff45de, 0xf85dafbb, 
+    0xea4fcb04, 0xea4f0b5b, 0xf1ac0a8a, 0x98000c02, 0x0104f100, 0x0e00f04f, 0x2982f645, 0xf8506803, 
+    0x680c503a, 0x603af851, 0x0805eb03, 0x0305eba3, 0x0506eb04, 0x0406eba4, 0x303af840, 0x403af841, 
+    0x8b08f840, 0x5b08f841, 0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0x680c6803, 0x0806eba5, 
+    0xfb384435, 0xfb35f809, 0xeb03f509, 0xeba30608, 0xeb040308, 0xeba40805, 0xf8400405, 0xf841303a, 
+    0xf840403a, 0xf8416b08, 0x680c8b08, 0x603af851, 0xf8506803, 0xeba3503a, 0x44330806, 0x0605eb04, 
+    0x0405eba4, 0x303af840, 0x403af841, 0x8b08f840, 0x6b08f841, 0x503af850, 0x603af851, 0x0545ea4f, 
+    0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 0x0506eba5, 0xf809fb38, 0xf509fb35, 0x0608eb03, 
+    0x0308eba3, 0x0805eb04, 0x0405eba4, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x00caeb00, 
+    0x01caeb01, 0x0e01f10e, 0xf6ff45de, 0xea4faf87, 0xea4f0b5b, 0xf1ac0a4a, 0x98000c01, 0x0104f100, 
+    0x0e00f04f, 0x6803b404, 0x503af850, 0xf851680c, 0xeb03603a, 0xeba30805, 0xeb040305, 0xeba40506, 
+    0xea4f0406, 0xea4f03e3, 0xea4f04e4, 0xea4f08e8, 0xf84005e5, 0xf841303a, 0xf840403a, 0xf8418b08, 
+    0xeb025b08, 0x680302cb, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 
+    0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 
+    0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 
+    0x02cbeb02, 0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0x680c6803, 0x0806eba5, 0xfb384435, 
+    0xfb35f809, 0xeb03f509, 0xeba30608, 0xeb040308, 0xeba40805, 0xea4f0405, 0xea4f03e3, 0xea4f04e4, 
+    0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8416b08, 0xeb028b08, 0x680302cb, 0x503af850, 
+    0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 
+    0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 
+    0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0xf851680c, 0x6803603a, 
+    0x503af850, 0x0806eba3, 0xeb044433, 0xeba40605, 0xea4f0405, 0xea4f03e3, 0xea4f04e4, 0xea4f06e6, 
+    0xf84008e8, 0xf841303a, 0xf840403a, 0xf8418b08, 0xeb026b08, 0x680302cb, 0x503af850, 0xf851680c, 
+    0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 
+    0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 
+    0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0x503af850, 0x603af851, 0x0545ea4f, 
+    0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 0x0506eba5, 0xf809fb38, 0xf509fb35, 0x0608eb03, 
+    0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 0x303af840, 
+    0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0xf8506803, 0x680c503a, 0x603af851, 0x0545ea4f, 
+    0xea4f6817, 0xfb350646, 0xf1c5f807, 0xfb350500, 0xfb36f517, 0xfb368817, 0xeb035507, 0xeba30608, 
+    0xeb040308, 0xeba40805, 0xea4f0405, 0xea4f03e3, 0xea4f04e4, 0xea4f06e6, 0xf84008e8, 0xf841303a, 
+    0xf840403a, 0xf8416b08, 0xeb028b08, 0xeb0002cb, 0xeb0100ca, 0xbc0401ca, 0x0e01f10e, 0xf6ff45de, 
+    0xea4faea1, 0xea4f0b5b, 0xf1ac0a4a, 0x98000c01, 0x0104f100, 0x0e00f04f, 0x0900f04f, 0x6803b404, 
+    0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 
+    0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x303af840, 0x403af841, 
+    0x02cbeb02, 0x6b08f840, 0x8b08f841, 0x0901f109, 0xf6ff45d1, 0xeb00afd4, 0xeb0100ca, 0xbc0401ca, 
+    0x0e01f10e, 0xf6ff45de, 0xea4fafc7, 0xea4f0b5b, 0xf1ac0a4a, 0xf1bc0c01, 0xdcb80f00, 0xe8bdbc04, 
+    0x47705ffc, 0x41f0e92d, 0x88079c06, 0x0701ea27, 0x0801ea47, 0x0500f04f, 0xf8a08007, 0x88168000, 
+    0x6025f843, 0x0501f105, 0xdbf542a5, 0xe8bdbf00, 0xe92d81f0, 0x880541f0, 0x0701ea25, 0x0801ea45, 
+    0xf8a08007, 0xf04f8000, 0xf04f0604, 0xf8320500, 0xf8327b02, 0xea488b02, 0xf8434707, 0xf1057b04, 
+    0x42b50501, 0xe8bddbf3, 0x000081f0, 0x5ffce92d, 0xf0f1fb90, 0x9ffce8bd, 0x5ffce92d, 0x0210f1c1, 
+    0xf102fa10, 0xfa51b209, 0xe8bdf002, 0x00009ffc, 0xe92d4001, 0xe14f0000, 0xe3100020, 0x115e00b2, 
+    0x13c00cff, 0x051e0004, 0x03c004ff, 0xe35000fe, 0x0a000007, 0xe35000ff, 0x0a000009, 0xe3500000, 
+    0x0a000001, 0xe8bd4001, 0xe1b0f00e, 0xe8bd4001, 0xeafffc60, 0xe14f0000, 0xe38000c0, 0xe16ff000, 
+    0xea000003, 0xe14f0000, 0xe3c000c0, 0xe16ff000, 0xeaffffff, 0xe8bd4001, 0xe1b0f00e, 0x5ffce92d, 
+    0x0400f04f, 0x5024f851, 0xf6f5fbb0, 0x6024f842, 0x0401f104, 0xf6ff429c, 0xe8bdaff5, 0x00009ffc, 
+    0x5ffce92d, 0xf0f1fbb0, 0x9ffce8bd, 0x0004e99c, 0x0004ff9c, 0xe51f0010, 0xe12fff1e, 0xe92d0003, 
+    0xe59f0010, 0xe59f1010, 0xe5801000, 0xe8bd0003, 0xe25ef004, 0xe320f000, 0xf0003010, 0xdef0dead, 
+    0xe51ff004, 0x0000dabd, 0xe51ff004, 0x00007ad3, 0x46c04778, 0xe92d41f0, 0xf10c0080, 0xe59f1028, 
+    0xe5910000, 0xe3500000, 0x0a000003, 0xe3a00000, 0xe5810000, 0xf1080080, 0xe8bd81f0, 0xf1080080, 
+    0xf57ff04f, 0xe320f003, 0xe8bd81f0, 0x0004023c, 0x5ff0e92d, 0x0200f04f, 0x0300f04f, 0x3022f840, 
+    0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0x00009ff0, 0x5ff0e92d, 0x0200f04f, 0x0300f04f, 0x3012f820, 
+    0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0x00499ff0, 0x20c1ea50, 0x2004bf18, 0xbf180d4a, 0x0001f040, 
+    0x72fff240, 0x5f51ebb2, 0xf040bf08, 0x28010002, 0x2005bf08, 0xe92d4770, 0x460441f0, 0x461e4615, 
+    0xf0371e4f, 0xeb000206, 0xe9d101c7, 0xd00d0100, 0x4633462a, 0xf868f001, 0xeb041e7f, 0xe9d303c7, 
+    0xf0002300, 0xf037fd89, 0xd1f10206, 0xd0232f02, 0xd0112f04, 0xd1312f06, 0x4633462a, 0xf854f001, 
+    0x230ae9d4, 0xfd78f000, 0x4633462a, 0xf84cf001, 0x2308e9d4, 0xfd70f000, 0x4633462a, 0xf844f001, 
+    0x2306e9d4, 0xfd68f000, 0x4633462a, 0xf83cf001, 0x2304e9d4, 0xfd60f000, 0x4633462a, 0xf834f001, 
+    0x2302e9d4, 0xfd58f000, 0x4633462a, 0xf82cf001, 0x2300e9d4, 0x41f0e8bd, 0xbd4ef000, 0x81f0e8bd, 
+    0x22004902, 0x46104613, 0xbe02f000, 0x3ff00000, 0xbd42f000, 0x46132200, 0x46114610, 0xbdf8f000, 
+    0xf2402000, 0xf04f3201, 0xf00141e0, 0x0000be34, 0x20004a02, 0xf0010711, 0x0000be2e, 0xfffffd01, 
+    0x4df0e92d, 0x461c4616, 0x2800460f, 0xf021b094, 0xf0234100, 0xbf144200, 0x25002501, 0xc410f8df, 
+    0x0547eb05, 0xea4f4465, 0x429d036c, 0x0035d32b, 0x2501bf18, 0x0544eb05, 0x44ac4bfe, 0xd322459c, 
+    0x0306ea52, 0xd0024bfc, 0xd105429f, 0xb014b948, 0x20004619, 0x8df0e8bd, 0xbf082800, 0x0c00f04f, 
+    0xf04fd001, 0xeb0c0c01, 0xf5130347, 0xd80a1f00, 0xbf142e00, 0x0c01f04f, 0x0c00f04f, 0x0344eb0c, 
+    0x1f00f513, 0x4632d907, 0x46394623, 0xe8bdb014, 0xf7ff4df0, 0xf8dfbf9d, 0xf04f83a4, 0x2f000a00, 
+    0x4542bfb8, 0x4be6da23, 0xbfa8429a, 0x0a02f04f, 0x4be1da1d, 0xdc1a4293, 0xeb034be2, 0x2b145322, 
+    0xf1c3dd08, 0xfa260c34, 0xfa03f30c, 0x45b4fc0c, 0xe008d10d, 0xf1c3b95e, 0xfa220c14, 0xfa03f30c, 
+    0x4594fc0c, 0xf003d103, 0xf1c30301, 0xea510a02, 0xd11b0300, 0xda192c00, 0xbf182f00, 0x0f02f1ba, 
+    0xf1bad002, 0xd0070f01, 0xf7fe2002, 0xb014fb54, 0x4df0e8bd, 0xbf54f7ff, 0xf7fe2002, 0xf7fffb4c, 
+    0xf081ff4f, 0xb0144100, 0x8df0e8bd, 0xd16b0033, 0xd1204542, 0x4280f107, 0x1280f512, 0x2800bf02, 
+    0x49bd2000, 0x48bcd0ef, 0xdc054288, 0xbfa42c00, 0x46214618, 0xe007dae7, 0xda051e20, 0xf080b014, 
+    0x46184100, 0x8df0e8bd, 0x447949b7, 0x0100e9d1, 0xe8bdb014, 0xf8df8df0, 0x4562c2c0, 0x2c00d12a, 
+    0xb139da24, 0xd1174541, 0xbf042800, 0x46022000, 0xe006d11c, 0x2002b140, 0xfb0df7fe, 0xff20f7ff, 
+    0x4639460a, 0xbad2f000, 0x46394aa4, 0x2000b014, 0x011ef362, 0x8df0e8bd, 0x463bda08, 0x46614602, 
+    0x2000b014, 0x4df0e8bd, 0xbd02f000, 0xb0144639, 0x8df0e8bd, 0xda174541, 0x4f80f1b4, 0xf1a4d00c, 
+    0xf1b35300, 0xd10f53ff, 0xdb0d1e3b, 0xb0144619, 0x4df0e8bd, 0xbbd8f000, 0x463bb014, 0x46194602, 
+    0x4df0e8bd, 0xbf00f000, 0xf0270005, 0xd1384300, 0x4541b1d1, 0x2f00d135, 0x2c00dd04, 0x2000bfa4, 
+    0xdad44641, 0xdd012f00, 0xdb1f2c00, 0xda162f00, 0xdb142c00, 0x0000f04f, 0x0f01f1ba, 0x497fbf14, 
+    0xb0144982, 0x8df0e8bd, 0x0f02f1ba, 0x2f00bf18, 0xf1bad00c, 0xd1090f01, 0xda072f00, 0x2f00e00b, 
+    0x2c00bfb8, 0xf1bada0d, 0xd0040f01, 0x2000b014, 0xe8bd4601, 0xb0148df0, 0xf04f2000, 0xe8bd4100, 
+    0xf04f8df0, 0x46b80c01, 0x7ce7eb0c, 0xc044f8cd, 0x0c0aea5c, 0xf8dfd00d, 0x4562c1b8, 0xf8dfdd7e, 
+    0x4b6dc1b4, 0xdd124562, 0xdb0a428b, 0xdb182c00, 0x2001e023, 0xfa7ff7fe, 0xe8bdb014, 0xf7ff4df0, 
+    0x4a5dbe89, 0xdc02428a, 0xdc0a2c00, 0x4299e015, 0x2c00da02, 0xe004da11, 0x42994b57, 0x2c00dd19, 
+    0x2002dd0b, 0xfa67f7fe, 0xfe7af7ff, 0xb0144a53, 0x021ef361, 0xe8bd4611, 0x20028df0, 0xfa5bf7fe, 
+    0xfe76f7ff, 0xb0144a4c, 0x021ef361, 0xe8bd4611, 0x22008df0, 0xf0014641, 0xf06ff883, 0x46050201, 
+    0xf001460f, 0x4b4dfc98, 0x3255f04f, 0xffa0f000, 0x463b462a, 0xfe68f000, 0x22004b49, 0xff98f000, 
+    0x463b462a, 0x468b4680, 0x46194610, 0xfe5cf000, 0x465b4642, 0xfe58f000, 0x46804b42, 0xf04f4628, 
+    0x910942c0, 0xf0004639, 0x9107fe4f, 0x46404683, 0x4b3c4a3d, 0xf0009909, 0x4a3cfe47, 0x46284680, 
+    0x91014b3b, 0xf0004639, 0x9b01fe3f, 0xf0014642, 0x900cf847, 0x4602460d, 0xe000460b, 0x9907e00e, 
+    0xf0004658, 0x9b07fb59, 0x465a4688, 0x46382700, 0xf836f001, 0x462b9a0c, 0xb976f000, 0x1f80f5b1, 
+    0x0000f04f, 0x4628da07, 0x22354619, 0xfc43f001, 0xf06f4605, 0xeb000034, 0xf3c15221, 0x4b250013, 
+    0x31fff2a2, 0x677ff040, 0xf0474298, 0x91015740, 0xf04fbfd8, 0xdd0c0b00, 0x4281491f, 0xf04fbfc8, 
+    0xdc060b01, 0x0b00f04f, 0xf5a79801, 0x1c401780, 0x481a9001, 0x46394478, 0x00cbeb00, 0xe9d09704, 
+    0x46282300, 0x93099212, 0xfffaf000, 0x0000e028, 0x001fffff, 0x000fffff, 0x3ff00000, 0x7ff00000, 
+    0x43400000, 0xfffffc01, 0x00001d8a, 0xfff00000, 0x41e00000, 0x43f00000, 0x3fefffff, 0x3fd55555, 
+    0x3fe00000, 0x3ff71547, 0x652b82fe, 0xf85ddf44, 0x3e54ae0b, 0x0003988e, 0x000bb67a, 0x00001a58, 
+    0x1007e9cd, 0x9b094628, 0x99049a12, 0xfae4f000, 0x20004602, 0x49fe460b, 0xfb9af000, 0x46029100, 
+    0x900c460b, 0x1007e9dd, 0xfdaef000, 0x46889006, 0x447848f8, 0x68009a12, 0xf04f900e, 0xea405000, 
+    0xeb000067, 0xf500408b, 0x9b092100, 0x2700980e, 0xf0009102, 0x9b04ffa5, 0xf000462a, 0x463afec9, 
+    0xf0004643, 0x9104fd91, 0x46384605, 0x9b024641, 0xf0009a0e, 0xe9ddfd89, 0xf0003207, 0x9b04feb9, 
+    0xf000462a, 0x9b00ff8d, 0xf0009a0c, 0x9a06fd7d, 0x91094643, 0x900c4619, 0xf0004610, 0x4605fd75, 
+    0x48dd4602, 0x9107460b, 0x44782106, 0xfcf3f7ff, 0x462a9b07, 0x90009102, 0x46194610, 0xfd64f000, 
+    0x9a009b02, 0xfd60f000, 0x46439a06, 0x46384605, 0x46199100, 0xfa80f000, 0x9a0c9b09, 0xfd54f000, 
+    0x462a9b00, 0xfa78f000, 0x4643463a, 0x90089100, 0x46194610, 0xfd48f000, 0x22004bc8, 0x90049107, 
+    0xfa6af000, 0x9a089b00, 0xfa66f000, 0x460d4bc3, 0x4638463a, 0xff44f000, 0x9a049b07, 0xff40f000, 
+    0x9a089b00, 0xfe64f000, 0x9104463a, 0x4641462b, 0x4610900a, 0xfd28f000, 0x1007e9cd, 0x9a064643, 
+    0x980a9904, 0xfd20f000, 0x4680462b, 0x460d980c, 0x9909463a, 0xfd18f000, 0x462b4642, 0xfa3cf000, 
+    0x46809100, 0x460b4602, 0x1007e9dd, 0xfa34f000, 0x3207e9dd, 0x2000460f, 0xf0004605, 0x9b00ff11, 
+    0xf0004642, 0x4ba6fe35, 0x46284680, 0x4260f04f, 0x46399109, 0xfcf8f000, 0x90049102, 0x4aa14640, 
+    0x99094b9f, 0xfcf0f000, 0x46804a9f, 0x4b9f4628, 0x46399103, 0xfce8f000, 0x46429b03, 0xfa0cf000, 
+    0x447a4a9b, 0x03cbeb02, 0x2300e9d3, 0xfa04f000, 0x98014605, 0xf0009105, 0x9000fc70, 0xe9dd462a, 
+    0x91030304, 0xf0009902, 0x4a92f9f7, 0xeb02447a, 0xe9d303cb, 0x46932300, 0xf0009301, 0x9b03f9ed, 
+    0xf0009a00, 0x9b03f9e9, 0x9a004688, 0x46382700, 0xfec6f000, 0x465a9b01, 0xfec2f000, 0x9a049b02, 
+    0xfebef000, 0x462a9b05, 0xfde2f000, 0x4d789b11, 0xf1aa2200, 0xea530c01, 0x9206030c, 0x4d7ed101, 
+    0xf04f9206, 0x46320a00, 0xf0004623, 0x4623fc9d, 0x46839103, 0x46304652, 0xf0004619, 0x463afea1, 
+    0xf0004643, 0x9b03fc91, 0xf000465a, 0x463af9b5, 0x46064643, 0x4650468b, 0xf0004621, 0x4604fc85, 
+    0x4632460f, 0xf000465b, 0x4a6cf9a7, 0x4291468a, 0xebaadb21, 0xea530302, 0xd1100200, 0x463b4622, 
+    0xfe7ef000, 0x46804a66, 0x4b664630, 0x46599101, 0xf992f000, 0x46429b01, 0xfd64f000, 0x2002d22b, 
+    0xf839f7fe, 0xfc4cf7ff, 0x4629460a, 0xf362b014, 0xe8bd011e, 0x4b5c8df0, 0x4200f02a, 0xd31a429a, 
+    0xeb0a4a5a, 0xea530302, 0xd1080200, 0x463b4622, 0xfe56f000, 0x465b4632, 0xfd44f000, 0x2002d80b, 
+    0xf819f7fe, 0xfc34f7ff, 0x5310ea4f, 0x4629460a, 0x5303ea4f, 0x494ee7da, 0x0800f04f, 0xf02a4a4d, 
+    0x42824000, 0x5120eb01, 0x484bda25, 0x1c80f44f, 0x1c494478, 0xfa2c6802, 0x4450f001, 0x0301f1ac, 
+    0x510af3c0, 0x31fff2a1, 0x0f00f1ba, 0xf301fa23, 0x0c13f3c0, 0x0114f1c1, 0x1c80f44c, 0xf801fa2c, 
+    0x0303ea20, 0xf1c8bfb8, 0x46200800, 0xf0004639, 0x4604fe17, 0x4630460f, 0x46224659, 0xf000463b, 
+    0x4b36f92b, 0x0a00f04f, 0x46529103, 0xf0004650, 0xe9cdfbfb, 0x46501007, 0x4b324a31, 0xf0009903, 
+    0x9102fbf3, 0x463b4622, 0x90049903, 0xf0004650, 0x4632fdf7, 0xf000465b, 0x4a2bfd1b, 0xf0004b2b, 
+    0x9b02fbe3, 0xf0009a04, 0x4607f907, 0x4602468a, 0xe9dd460b, 0xf0001007, 0xe9ddf8ff, 0x46043207, 
+    0xf000460e, 0x463afddd, 0xf0004653, 0x4622fd01, 0x900c4633, 0x4610460f, 0xf0004619, 0x4682fbc5, 
+    0x481b4602, 0x460b468b, 0x44782105, 0x0000e032, 0x3ff00000, 0x00001a42, 0x00001972, 0x40080000, 
+    0x3feec709, 0xdc3a03fd, 0x145b01f5, 0xbe3e2fe0, 0x0000184a, 0x00001810, 0xbff00000, 0x40900000, 
+    0x652b82fe, 0x3c971547, 0x4090cc00, 0x3f6f3400, 0xfffffc01, 0x3fe00000, 0x00001744, 0x3fe62e43, 
+    0x0ca86c39, 0xbe205c61, 0xfefa39ef, 0x3fe62e42, 0x00001642, 0xfb0ff7ff, 0x465b4652, 0xfb84f000, 
+    0x46334622, 0xfcb4f000, 0x46829a0c, 0x463b468b, 0x46314620, 0xfb78f000, 0x463b9a0c, 0xf89cf000, 
+    0x46072200, 0xf04f4650, 0x91004380, 0xf0004659, 0x9103fd77, 0x465b4652, 0x900a4631, 0xf0004620, 
+    0x9b03fb63, 0xf0009a0a, 0x9b00f943, 0xf000463a, 0x4622fd67, 0xf0004633, 0x4b12fd63, 0xf0002200, 
+    0x460efc87, 0x5108eb01, 0x15084604, 0xdc102800, 0x46204642, 0xf0014631, 0xf7fff96e, 0x2804fab8, 
+    0xf7ffbf08, 0x4642fb35, 0x46314620, 0xf963f001, 0x98064604, 0x4629460b, 0x4622b014, 0x4df0e8bd, 
+    0xbb32f000, 0x3ff00000, 0x41f0e92d, 0x460f4606, 0xfc6af000, 0x460d0004, 0x2001bf18, 0xf0204328, 
+    0xf1c04000, 0xf100607f, 0x0fc040e0, 0x1c30d00e, 0x2001bf18, 0xf0204338, 0xf1c04000, 0xf100607f, 
+    0x0fc040e0, 0x2001bf04, 0xfee5f7fd, 0x46294620, 0x81f0e8bd, 0x4200f021, 0x5260f1a2, 0x1f80f5b2, 
+    0x4300f001, 0xf1d2bf28, 0xd90b6c7f, 0x1c00ea5f, 0x02c2ea43, 0x7050eb42, 0x4770bf18, 0xf020bf28, 
+    0x47700001, 0x1f80f5b2, 0x4618bfbc, 0xea4f4770, 0xf51c0c41, 0xd2021f00, 0xf0014608, 0xb570b860, 
+    0xfb8cf000, 0x89000000, 0xbff6f7ff, 0x4000f04f, 0x0080f5a0, 0x00004770, 0xea91b510, 0xbf480f03, 
+    0x4300f083, 0x84e4f100, 0xeb711a84, 0xd2050c03, 0xeb431912, 0x1b00030c, 0x010ceb61, 0xe124f8df, 
+    0x5411ea4f, 0x5c13eba4, 0x0f43ea1e, 0xea9ebf18, 0xd0735f44, 0x030eea23, 0x0e20f1dc, 0x5104ea21, 
+    0x1380f443, 0xfa22d332, 0xeb10fe0c, 0xfa23000e, 0xeb41fe0c, 0xf1cc010e, 0xfa030e20, 0xeb10fe0e, 
+    0xf151000e, 0xf5b10100, 0xf1cc1f80, 0xd2320e20, 0x5104eb01, 0xf20efa12, 0x4010e8bd, 0x4770bf58, 
+    0xbf381c40, 0x0242ea5f, 0x4770bf18, 0xbf142800, 0x0001f020, 0x0100f141, 0x0341ea4f, 0x1f00f513, 
+    0x4770bf38, 0x41c0f1a1, 0xbb76f000, 0xeb432a01, 0xf1ac0203, 0xf1dc0c20, 0xbf320e1f, 0x0e00f04f, 
+    0xf30cfa23, 0x0003eb10, 0x5104eb41, 0x5f11ebb4, 0xeba1d0d0, 0xf5015104, 0x08491180, 0x0030ea5f, 
+    0x5104eb01, 0xf150d30e, 0xbf380000, 0xfe0efa12, 0xe8bdd108, 0xe7c94010, 0xbf381c40, 0x0242ea5f, 
+    0xe7c3d1ca, 0x4010e8bd, 0x0341ea4f, 0x1f00f513, 0x4770bf38, 0x41c0f1a1, 0xbb3ef000, 0x5f44ea9e, 
+    0xea11d008, 0xe8bd0f5e, 0xbf044010, 0x4100f001, 0x47702000, 0x4010e8bd, 0xf000b570, 0xbf00fadf, 
+    0x3ebefb64, 0xffe00000, 0xf04f4902, 0xf0010000, 0xbf00b820, 0x7ff80000, 0xbf581049, 0x4140f1c1, 
+    0xbf58105b, 0x4340f1c3, 0xf3ef428b, 0x47708000, 0x41c0e92d, 0xf8dfb430, 0xea3cc2a0, 0xbf181411, 
+    0x1413ea3c, 0x80ecf000, 0x0503ea81, 0x1411ea1c, 0x74d5ea44, 0xea1cbf18, 0xf0001513, 0xeba480c7, 
+    0xf04f0405, 0xea454500, 0xea4521c1, 0xea4123c3, 0xea435150, 0xf1045352, 0x4299747f, 0x3400f504, 
+    0x20c0ea4f, 0x22c2ea4f, 0x4290bf08, 0x809cf000, 0x6513ea4f, 0x1640f20f, 0xea4f5d76, 0xfb064513, 
+    0xf1c7f705, 0xfb067780, 0xea4ff707, 0xfba737d7, 0x42766803, 0x3880f5c8, 0xce06fba7, 0xf1a8bf38, 
+    0xfb070801, 0xf04fe608, 0xfba60e00, 0xfbe68c02, 0xf1dcce03, 0xf1ce0c00, 0xbf384e00, 0x0e01f1ae, 
+    0x580cfba6, 0x0700f04f, 0x0500f04f, 0x870efbe6, 0xc608fba1, 0xce07fba0, 0x060eeb16, 0x0500f145, 
+    0x6507fbe1, 0x4ee0f115, 0xf5a4bf7e, 0xea5f3480, 0x416d0646, 0x0780f116, 0x0500f145, 0x2717ea4f, 
+    0x6606ea4f, 0x6705ea47, 0x46def1a6, 0x5f80f1b6, 0x2515ea4f, 0x4638d91f, 0x0c01f024, 0x71c4eb05, 
+    0x6ffef1bc, 0x110ceb01, 0xbcf0d802, 0x8100e8bd, 0xbf5c4224, 0x1e80f501, 0x7fc4ea9e, 0xbcf0d402, 
+    0x8100e8bd, 0xd4384224, 0xf1a1bcf0, 0xe8bd41c0, 0xf0004100, 0xea4fba71, 0xea4222d2, 0xea4f5243, 
+    0xfba723d3, 0xea4f8602, 0xea4020d0, 0xfb075041, 0xea1e6603, 0xea4f0f0e, 0xfb0521d1, 0xbf586602, 
+    0x5600eba6, 0x5600ebb6, 0x0e52ea4f, 0x7ec3ea4e, 0x0e0eeb18, 0x0e53eb56, 0xeb18d5bd, 0x415e0802, 
+    0xf1551c7f, 0xe7b60500, 0x1580f44f, 0x0700f04f, 0x0600f04f, 0x0800f04f, 0xbcf0e7ad, 0x0000f04f, 
+    0x41c0f101, 0x4100f001, 0x8100e8bd, 0x1f0cea11, 0x1513ea0c, 0xe00cd000, 0x1f0cea13, 0x8025f000, 
+    0x0000f04f, 0xea81bcf0, 0xf0010103, 0xe8bd4100, 0xbcf08100, 0x4100e8bd, 0x0103ea81, 0xba1cf000, 
+    0xe8bdbcf0, 0xb5704100, 0xf9c8f000, 0x3efc7e09, 0xb807f000, 0x0103ea81, 0x0000f04f, 0x4100f001, 
+    0xea814770, 0xf0000103, 0xbcf0ba07, 0x4100e8bd, 0x0000f04f, 0x47704921, 0xf9fbfdff, 0xf2f4f5f7, 
+    0xebedeef0, 0xe4e6e8e9, 0xdee0e1e3, 0xd8dadbdd, 0xd3d4d5d7, 0xcdcfd0d1, 0xc8cacbcc, 0xc4c5c6c7, 
+    0xbfc0c1c2, 0xbbbcbdbe, 0xb7b8b9ba, 0xb3b4b5b6, 0xafb0b1b2, 0xabacadae, 0xa8a8a9aa, 0xa4a5a6a7, 
+    0xa1a2a3a3, 0x9e9f9fa0, 0x9b9c9c9d, 0x9899999a, 0x95969797, 0x93939495, 0x90919192, 0x8e8e8f8f, 
+    0x8b8c8c8d, 0x89898a8b, 0x87878888, 0x84858586, 0x82838384, 0x80818182, 0x07ff0000, 0x7ff80000, 
+    0x0341ea4f, 0x5353ea4f, 0x6380f5a3, 0x031ef1d3, 0xf1d3bfc8, 0xdd0c0c21, 0x4200f04f, 0x22c1ea42, 
+    0x5250ea42, 0xfc03fa32, 0x7ce1ea8c, 0x70e1ebac, 0x2b104770, 0x2000bfc4, 0xf5034770, 0xf1bc7c78, 
+    0xd0043fff, 0x4200f06f, 0x0021ea82, 0xb5704770, 0xf944f000, 0x80249249, 0x47702000, 0x0000e7f2, 
+    0x5311ea4f, 0x6380f5a3, 0x031ef1d3, 0xf1d3bfa8, 0xdb080c20, 0x4200f04f, 0x22c1ea42, 0x5250ea52, 
+    0xf003fa32, 0x42094770, 0x2b10d40b, 0x2000bfc4, 0xf5034770, 0xf1bc7c78, 0xd0053fff, 0x30fff04f, 
+    0xf04f4770, 0x47700000, 0xf000b570, 0xbf00f917, 0x80249249, 0x47702000, 0xf010e7f0, 0xbf484200, 
+    0xfab04240, 0xfa10f380, 0xd00af103, 0x031df1c3, 0x6380f503, 0x5041ea4f, 0x5203eb02, 0x21d1eb02, 
+    0xf04f4770, 0x47700000, 0xf380fab0, 0xf103fa10, 0xf1c3d00a, 0xf503031d, 0xea4f6380, 0xea4f5041, 
+    0xeb025203, 0x477021d1, 0x0000f04f, 0x00004770, 0x0c03ea51, 0xf51cd417, 0xbf581f80, 0x1f80f5bc, 
+    0x8006f100, 0xbf184299, 0xbf084770, 0x47704290, 0xf511d707, 0xbf581f80, 0x1f80f513, 0x4299d419, 
+    0x42894770, 0xf51c4770, 0xd5081f80, 0x1f80f5bc, 0x428bd5f7, 0x4770bf18, 0x4282bf08, 0xf44f4770, 
+    0xeb1c1c00, 0xbf380f41, 0x0f43eb1c, 0x428bd201, 0xb5704770, 0xf8b2f000, 0x00492492, 0x5100f04f, 
+    0x5380f04f, 0xbdd8f7ff, 0xc148f8df, 0xea1cb570, 0xbf1e1e11, 0x1513ea1c, 0x0f0cea9e, 0x0f0cea95, 
+    0x806ff000, 0x0403ea81, 0x134cea23, 0x7ed4ea4e, 0x114cea21, 0x1180f441, 0x1380f443, 0xfba144ae, 
+    0xfba04c02, 0xf1ae6503, 0x19367e7f, 0x050ceb55, 0x4c03fba1, 0x0300f14c, 0x1c02fba0, 0x060ceb16, 
+    0xf1534165, 0x42090300, 0xf046bf18, 0xf4130601, 0xd10b7f00, 0x3103ea4f, 0x3005ea4f, 0xea410334, 
+    0xea405115, 0xf06f5016, 0xe00a0203, 0x21c3ea4f, 0x20c5ea4f, 0xea4102f4, 0xea405155, 0xf06f5056, 
+    0xeb020202, 0xeb01422e, 0xea855502, 0xd00a71ce, 0x0c44ea5f, 0xf024bf18, 0xf1504400, 0xf1410000, 
+    0xea200100, 0xf24070d4, 0x45627cfe, 0xbd70d200, 0xbf1442a8, 0x4480f04f, 0x4440f04f, 0xbf082e00, 
+    0xf1be2400, 0xbfa86f80, 0x41c0f1a1, 0x4070e8bd, 0x8082f280, 0x0000f04f, 0x41c0f101, 0x4100f001, 
+    0xea9e4770, 0xea0c0f0c, 0xbf181513, 0x0f0cea95, 0xf04fd006, 0xea810000, 0xf00e0e03, 0xbd704100, 
+    0xf81cf000, 0x3e010089, 0xb807f000, 0xb809f000, 0x0c43ea4f, 0x5c5cea5f, 0xea81d008, 0xf0000103, 
+    0xea4fb85b, 0xea5f0c41, 0xd1f65c5c, 0x0000f04f, 0x47704901, 0x07ff0000, 0x7ff80000, 0x0e02f10e, 
+    0x0e03f02e, 0x6b04f85e, 0xd4054236, 0xeb432a01, 0xf5150503, 0xd8121f00, 0xeb412801, 0xf51c0c01, 
+    0xd80c1f00, 0xea4fd10e, 0xf5157cd1, 0xeb0c1f00, 0xf10c0c4c, 0xbf080c02, 0x7cd3eb4c, 0xf04fe004, 
+    0xe0010c08, 0x7cd3ea4f, 0x054ceb0c, 0xf605fa26, 0x0607f006, 0x0c04f1b6, 0xeb0ed206, 0xe8bd0c86, 
+    0xf04c4070, 0x47600c01, 0xf00ce8df, 0x02020b09, 0x4100f04f, 0x0000f04f, 0x2100f5a1, 0x4619bd70, 
+    0x28014610, 0x0401eb51, 0xf5d4bf18, 0xbf841400, 0xf0012000, 0xbd704100, 0xf5a00808, 0xea4f1100, 
+    0x47700131, 0x0c01ea53, 0xf51cd417, 0xbf581f80, 0x1f80f5bc, 0x8006f100, 0xbf18428b, 0xbf084770, 
+    0x47704282, 0xf513d707, 0xbf581f80, 0x1f80f511, 0x428bd419, 0x429b4770, 0xf51c4770, 0xd5081f80, 
+    0x1f80f5bc, 0x4299d5f7, 0x4770bf18, 0x4290bf08, 0xf44f4770, 0xeb1c1c00, 0xbf380f43, 0x0f41eb1c, 
+    0x4299d201, 0xb40f4770, 0xbc03bc0c, 0xbec1f7ff, 0x0f03ea91, 0xf081b510, 0xf53f4100, 0xf083abf5, 
+    0xf0004300, 0x0000b8d5, 0x41f0e92d, 0x1c80f501, 0x1f00f5bc, 0x80a9f2c0, 0x5c11ea4f, 0x510cea21, 
+    0x0cfdf10c, 0x1180f441, 0x0c5cea5f, 0x7cc0f50c, 0x0040d301, 0xa4304149, 0xea410289, 0x02875190, 
+    0x0c0a0e8e, 0xfb045da4, 0xfb02f604, 0xf1c6f606, 0xfba44640, 0x0df66206, 0x2642ea46, 0xf406fb06, 
+    0x2301fba4, 0xf1c34252, 0xbf384340, 0xfba61e5b, 0x24004202, 0x2403fbe6, 0xea420bd2, 0xfba64644, 
+    0xfba12306, 0xfba3e202, 0xfbe3e407, 0x42644261, 0x4e40f1c2, 0xf1aebf38, 0xfba60e01, 0xf04f2304, 
+    0xfbe60200, 0xfba2320e, 0x00344603, 0x6462fbe2, 0xe606fba1, 0xe807fba4, 0x6861fbe4, 0xf1c84276, 
+    0xbf385840, 0x0801f1a8, 0xe406fba2, 0xe508fba3, 0x5468fbe2, 0xe605fba1, 0xe804fba7, 0x8664fbe1, 
+    0x0520f118, 0x0600f156, 0xf1a809a8, 0x09b1081b, 0x083ff008, 0x0f0af1b8, 0x6086ea40, 0xeb01d91c, 
+    0xe8bd510c, 0xbf0081f0, 0xe8eef5fc, 0xd3d8dde2, 0xc3c7cbcf, 0xb6b9bdc0, 0xacaeb1b4, 0xa3a5a7a9, 
+    0x9b9d9fa1, 0x9596989a, 0x8f909293, 0x898b8c8d, 0x85868788, 0x81828384, 0x6800fba0, 0xf201fb00, 
+    0x0842eb08, 0x2887ebb8, 0x1834d507, 0x0401eb58, 0x1c40d5d5, 0x0100f151, 0x1a34e7d1, 0x0401eb78, 
+    0x1e40d4cd, 0x0100f171, 0xea5fe7c9, 0xea5f0c4c, 0xd10d5c9c, 0xf04fd305, 0xf0010000, 0xe8bd4100, 
+    0xe8bd81f0, 0xb57041f0, 0xfea8f7ff, 0xbeffdb6d, 0x41f0e8bd, 0x0000f04f, 0x47704900, 0x7ff80000, 
+    0xea91b510, 0xbf480f03, 0x4300f083, 0xab1cf53f, 0xeb711a84, 0xd2070c03, 0xf08c1912, 0xeb434c00, 
+    0x1b00030c, 0x010ceb61, 0xe1a4f8df, 0x5411ea4f, 0x5c13eba4, 0x0f43ea1e, 0xea9ebf18, 0xf0005f44, 
+    0xea2380b0, 0x4252036e, 0x5104ea21, 0x036eebc3, 0x1e5bbf38, 0x0e20f1dc, 0xfa22d325, 0xeb10fe0c, 
+    0xfa43000e, 0xeb41fe0c, 0xf1cc010e, 0xfa030e20, 0xeb10fe0e, 0xf151000e, 0xf1cc0100, 0xd4290e20, 
+    0xf20efa12, 0x5104eb01, 0x4010e8bd, 0x4770bf58, 0xbf1c1c40, 0x4f00f1b2, 0x28004770, 0x1c49bf0c, 
+    0x0001f020, 0xeb124770, 0xeb430e02, 0xbf180203, 0x0e01f04f, 0x0242ea4e, 0x0c20f1ac, 0x0e1ef1dc, 
+    0xfa43d954, 0xeb10fe0c, 0xf151000e, 0xf1cc31ff, 0xd5d50e1e, 0x0e01f10e, 0xfe0efa12, 0xeb414140, 
+    0xeb010101, 0xea5f5c44, 0xd9105c5c, 0x70deeb10, 0x5104eb01, 0xf1bebf38, 0xe8bd4f00, 0xbf184010, 
+    0x28004770, 0x1c49bf0c, 0x0001f020, 0xd2304770, 0x2cd4ea4f, 0x1100f511, 0x6400f424, 0xfab1d01b, 
+    0x3a0bf281, 0x1ea41aa4, 0x0320f1d2, 0xfa304091, 0x4319f303, 0xeb014090, 0x2c0071cc, 0x5104eb01, 
+    0x4010e8bd, 0x4770bfa8, 0x41c0f101, 0x0000f04f, 0x4100f001, 0xfab04770, 0xfa10f380, 0xd100f103, 
+    0x1ae4bd10, 0x05483c17, 0xe7e40ac9, 0x5104eb01, 0x1049bd10, 0x5104eb01, 0x4010e8bd, 0x0030ea4f, 
+    0xf04fe002, 0x47700100, 0xbf08004a, 0xd0f84200, 0x1f00f5b2, 0x4770bf28, 0x4100f001, 0x0000f04f, 
+    0xea9e4770, 0xd0075f44, 0x0f5eea11, 0x4010e8bd, 0x2100bf04, 0x47702000, 0x4010e8bd, 0xf7ffb570, 
+    0xbf00fdbd, 0x3ef6df40, 0x4100f083, 0x47704610, 0xffe00000, 0xea4f0043, 0xea4f0cd3, 0x40430c3c, 
+    0x0740bf1f, 0x5160f10c, 0x4ffef013, 0xf01c4770, 0xd1036f00, 0xf00c2000, 0x47704100, 0x4300f00c, 
+    0x7050ea43, 0xea40b510, 0xf00000cc, 0xbf00fa22, 0x92000000, 0x0100ea4f, 0xbddef7ff, 0x4100f04f, 
+    0x0000f04f, 0x2100f5a1, 0x00004770, 0x0f01ea90, 0xf081bf48, 0xf1004100, 0x1a42825e, 0x1a80bf3c, 
+    0xea4f1889, 0xf04f52d0, 0xea1c4c7f, 0xeba20f41, 0xbf1853d1, 0x6f02ea9c, 0x803bf000, 0x4c00f04f, 
+    0x2000ea4c, 0x2101ea4c, 0xfc03fa21, 0x0c0ceb10, 0xf102d21e, 0xea5f32ff, 0xeb40201c, 0xbf3850c2, 
+    0xf01c4770, 0xea4f0f7f, 0xbf180c40, 0x4f7ff1bc, 0x4770bf38, 0x0320f1c3, 0xbf084099, 0x0001f020, 
+    0x4f7ff1bc, 0x4770bf38, 0x40c0f1a0, 0xba17f000, 0x003cea4f, 0xeb400a00, 0xbf2850c2, 0x0ffff01c, 
+    0x0c40ea4f, 0xbf18d0e6, 0x4f7ff1bc, 0x4770bf38, 0xea9ce7ea, 0xd0056f02, 0x0f5cea10, 0xf000bf08, 
+    0x47704000, 0xf000b510, 0xbf00f9b4, 0x3ebefb64, 0xf0004801, 0xbf00ba6e, 0x7fc00000, 0x0c7ff44f, 
+    0x12d0ea1c, 0xea1cbf1e, 0xea9213d1, 0xea930f0c, 0xf0000f0c, 0xea908085, 0xbf480f01, 0x7280f442, 
+    0x0c00f440, 0x0000f441, 0x417ff02c, 0x407ff020, 0x4281b500, 0x0203eba2, 0x1c08f20f, 0x4e50ebac, 
+    0x0000f1c0, 0xe000f89e, 0x0e4eea4f, 0xfc0efb00, 0x0049bf38, 0x1c2cea4f, 0x02faf502, 0xf30efb0c, 
+    0x1eceea4f, 0x2c11ea4f, 0x21c1ea4f, 0x5e63eb0e, 0x4222eb42, 0xfc0cfb0e, 0x531cea4f, 0x1103fb00, 
+    0x2c11ea4f, 0x3101ea4f, 0xfc0cfb0e, 0x4cdcea4f, 0x110cfb00, 0xbf2842c1, 0xeb4c1809, 0xf85d3303, 
+    0xeb10eb04, 0xeb430141, 0xf5b250c2, 0xbf380f7c, 0xd5294770, 0x0ff0f012, 0xf100bf1c, 0xf00040c0, 
+    0x47704000, 0x83828100, 0x87868584, 0x8c8b8988, 0x918f8e8d, 0x96959392, 0x9c9a9997, 0xa2a09f9d, 
+    0xa8a7a5a3, 0xb0aeacaa, 0xb7b5b3b2, 0xc0bebcb9, 0xc9c7c5c2, 0xd4d1cecc, 0xdfdcd9d7, 0xece9e6e2, 
+    0xfaf7f3f0, 0x000000fe, 0x0c40ea4f, 0x7c80f10c, 0x4f7ef1bc, 0x4770bf28, 0x40c0f1b0, 0xb95ff000, 
+    0x0f01ea90, 0x13d1ea0c, 0xf442bf48, 0x45627280, 0x4563bf38, 0xf413d207, 0xd0160f7f, 0x0001ea80, 
+    0x4000f000, 0xb5104770, 0xf903f000, 0x3efc7e09, 0xb805f000, 0x0001ea80, 0x4000f000, 0xea804770, 
+    0xf0000001, 0xf0004000, 0xf412b93a, 0xbf040f7f, 0x47704802, 0x0001ea80, 0xb931f000, 0x7fc00000, 
+    0x0e0b0041, 0x029ef1d3, 0xf450d908, 0xea4f0300, 0xfa232303, 0xbf48f002, 0x47704240, 0xf000b510, 
+    0xbf00f8d8, 0x80249249, 0x47702000, 0x4200f06f, 0x0020ea82, 0x00004770, 0xf1d10dc1, 0xdb06029e, 
+    0x2300ea4f, 0x4300f043, 0xf002fa23, 0x42004770, 0xea4fd507, 0xf1b10140, 0xd2024ffe, 0x0000f04f, 
+    0xb5104770, 0xf8b5f000, 0x80249249, 0x47702000, 0x0020ea6f, 0x00004770, 0x4100f010, 0x4240bf48, 
+    0xf380fab0, 0xf203fa10, 0x039df1c3, 0xea51d00b, 0xeb0151c3, 0x06532012, 0x4770bf38, 0x0001f100, 
+    0xf020bf08, 0x47700001, 0xf380fab0, 0xf203fa10, 0x039df1c3, 0x05d9d00a, 0x2012eb01, 0xbf380653, 
+    0xf1004770, 0xbf080001, 0x0001f020, 0x00004770, 0x0c7ff44f, 0x12d0ea1c, 0xea1cbf1e, 0xea9213d1, 
+    0xea930f0c, 0xf0000f0c, 0xea908047, 0xbf480f01, 0x7280f442, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 
+    0x0203eb02, 0x1301fba0, 0x0200f5a2, 0xbf182900, 0x0301f043, 0xbf28005b, 0x0333ea4f, 0x4222eb42, 
+    0x2c13ea5f, 0x50c2eb4c, 0xebbcbf2e, 0xf5b26f43, 0x47700f7c, 0x6c03ea4f, 0x4f00f1bc, 0xf020bf08, 
+    0xf5b20001, 0xbf380f7c, 0xd50b4770, 0x02fff082, 0x3f80f512, 0x4770bfc8, 0x40c0f100, 0xf000bfd8, 
+    0x47704000, 0x0c00f500, 0x0c4cea5f, 0x4770bf48, 0x40c0f1b0, 0xb873f000, 0x0f01ea90, 0x13d1ea0c, 
+    0xf442bf48, 0x45627280, 0x4563bf38, 0xea80d204, 0xf0000001, 0x47704000, 0xf000b510, 0xbf00f81a, 
+    0x3e010089, 0xb807f000, 0xb809f000, 0x0c41ea5f, 0x6c1cea5f, 0xea80d008, 0xf0000001, 0xea5fb850, 
+    0xea5f0c40, 0xd1f66c1c, 0x4000f04f, 0x0080f5a0, 0xf10e4770, 0xf02e0e02, 0xf85e0e03, 0x42244b04, 
+    0xea4fd404, 0xf1b20241, 0xd8114f7f, 0x0340ea4f, 0x4f7ff1b3, 0xd10ed80c, 0x7cd0ea4f, 0x4f7ff1b2, 
+    0x0c4ceb0c, 0x0c02f10c, 0xeb4cbf08, 0xe0047cd1, 0x0c08f04f, 0xea4fe001, 0xeb0c7cd1, 0xfa24034c, 
+    0xf004f403, 0xf1b40407, 0xd2060c04, 0x0c84eb0e, 0x4010e8bd, 0x0c01f04c, 0xe8df4760, 0x0807f00c, 
+    0xf04f0202, 0xf5a04000, 0xbd100080, 0x00424608, 0xf1d2bf18, 0xbf887280, 0x4000f000, 0x21ffbd10, 
+    0x50d0ea41, 0x477005c0, 0x0f01ea90, 0xf081bf48, 0xf53f4100, 0x1a42ada2, 0xf082d804, 0xeba04200, 
+    0x44110002, 0x52d0ea4f, 0x4c7ff04f, 0x0f41ea1c, 0x53d1eba2, 0xea9cbf18, 0xd04a6f02, 0x4c00f04f, 
+    0x2000ea4c, 0x2101ea4c, 0xfc03fa21, 0x0c0cebb0, 0xf012d40f, 0xd0360ffe, 0x004cea5f, 0x1200d51d, 
+    0x50c2eb40, 0x4770bf38, 0x0f3ff01c, 0x4770bf18, 0xf1a2e00b, 0xea5f0201, 0xeb40201c, 0xbf3850c2, 
+    0xf01c4770, 0xbf180f7f, 0xf1c34770, 0x40990320, 0x1e40bf14, 0x0001f020, 0x08804770, 0x2312ea4f, 
+    0x4770bf08, 0xfc80fab0, 0x020ceba2, 0x0c28f1cc, 0xf00cfa60, 0x2f12ea93, 0xeb00bf04, 0x477050c2, 
+    0x70c3ea4f, 0x0a134770, 0x10dcea5f, 0x4770bf08, 0xea9ce7f6, 0xd0046f02, 0x0f5cea10, 0x2000bf08, 
+    0xb5104770, 0xff45f7ff, 0x3ef6df40, 0x4000f081, 0xf00c4770, 0x2b09030f, 0x2008bf08, 0x807ff000, 
+    0xd00b2b0a, 0xbf182b08, 0xbf084770, 0x0f40f01c, 0xf04fd00a, 0xf04f0000, 0x47700100, 0x0f40f01c, 
+    0xf04fbf18, 0x47704000, 0x0f10f01c, 0xf020d008, 0xf0004370, 0xea42427f, 0xea4f01d3, 0x47707043, 
+    0x4060f000, 0x427ff021, 0x0200ea42, 0x407ff001, 0x7072ea40, 0xf04f4770, 0xf44c0cff, 0xea1c6ce0, 
+    0xbf1c5311, 0x0c03ea9c, 0xbfc24594, 0xeb0142da, 0x47705102, 0xd00d2b00, 0x0f00f1bc, 0x2a00d00f, 
+    0x4100f001, 0xf041bfa4, 0xf04141e0, 0xf04f617f, 0x47700000, 0x4100f001, 0x0000f04f, 0xea504770, 
+    0xf04f3301, 0xbf180c9b, 0x6c80f04c, 0xaf7cf47e, 0xf04f4770, 0xea1202ff, 0xbf1c52d0, 0x03fff092, 
+    0xbfc2428b, 0xeb0042d1, 0x477050c1, 0xd00a2a00, 0xd00b2b00, 0xf0002900, 0xbfa44000, 0x40fef040, 
+    0x0000f440, 0xf0004770, 0x47704000, 0xf04f0243, 0xbf180c0b, 0x6c80f04c, 0xad0af47f, 0xf41c4770, 
+    0xd0111f80, 0x2fe0f41c, 0xea6fd003, 0x004931cc, 0xf04f4770, 0xf3ef5040, 0xf0228200, 0xea424270, 
+    0xf3820200, 0x47708800, 0x0000f04f, 0xfb904770, 0xfb02f2f1, 0x46100111, 0xfbb04770, 0xfb02f2f1, 
+    0x46100111, 0x02004770, 0x03010604, 0x00160011, 0x0020001b, 0x002a0025, 0x0034002f, 0x003c0039, 
+    0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x003c0040, 0xfff4fff4, 0xfff8fff8, 0xfff8fff8, 
+    0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0x0000fffc, 0xf2035190, 0xf2035192, 0xf2035194, 
+    0xf2035196, 0x00030008, 0x00030003, 0x00040004, 0x00000008, 0x00100034, 0x00100010, 0x001f001f, 
+    0x00000034, 0x00080020, 0x00080008, 0x00100010, 0x00000020, 0x00010004, 0x00030001, 0x00040003, 
+    0x00000004, 0x0006001c, 0x00080006, 0x0014000b, 0x0000001c, 0x00040010, 0x00060004, 0x000c0008, 
+    0x00000010, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0xf2033070, 
+    0xf2033270, 0xf2033470, 0xf2033670, 0x3f7ec56d, 0x3f700d1b, 0x3f7240b8, 0x3f833333, 0x41c55c29, 
+    0x41726666, 0x411c28f6, 0xc03f5c29, 0x3f7a8588, 0x3f6cb296, 0x3f6de69b, 0x3f822d0e, 0xc39030a4, 
+    0xc39eb99a, 0xc390651f, 0xc39cd852, 0x00000000, 0x00000000, 0x3ff00000, 0x00000000, 0x3ff80000, 
+    0x00000000, 0x00000000, 0x40000000, 0x3fe2b803, 0x00000000, 0x00000000, 0x43cfd006, 0x3e4cfdeb, 
+    0x33333303, 0x3fe33333, 0xdb6fabff, 0x3fdb6db6, 0x518f264d, 0x3fd55555, 0xa91d4101, 0x3fd17460, 
+    0x93c9db65, 0x3fcd864a, 0x4a454eef, 0x3fca7e28, 0x5555553e, 0x3fc55555, 0x16bebd93, 0xbf66c16c, 
+    0xaf25de2c, 0x3f11566a, 0xc5d26bf1, 0xbebbbd41, 0x72bea4d0, 0x3e663769, 0x00000000, 0x00000000, 
+    0xc0c10000, 0x0140c181, 0x03c0c301, 0xc2410280, 0x06c0c601, 0xc7410780, 0xc5c10500, 0x0440c481, 
+    0x0cc0cc01, 0xcd410d80, 0xcfc10f00, 0x0e40ce81, 0xcac10a00, 0x0b40cb81, 0x09c0c901, 0xc8410880, 
+    0x18c0d801, 0xd9411980, 0xdbc11b00, 0x1a40da81, 0xdec11e00, 0x1f40df81, 0x1dc0dd01, 0xdc411c80, 
+    0xd4c11400, 0x1540d581, 0x17c0d701, 0xd6411680, 0x12c0d201, 0xd3411380, 0xd1c11100, 0x1040d081, 
+    0x30c0f001, 0xf1413180, 0xf3c13300, 0x3240f281, 0xf6c13600, 0x3740f781, 0x35c0f501, 0xf4413480, 
+    0xfcc13c00, 0x3d40fd81, 0x3fc0ff01, 0xfe413e80, 0x3ac0fa01, 0xfb413b80, 0xf9c13900, 0x3840f881, 
+    0xe8c12800, 0x2940e981, 0x2bc0eb01, 0xea412a80, 0x2ec0ee01, 0xef412f80, 0xedc12d00, 0x2c40ec81, 
+    0x24c0e401, 0xe5412580, 0xe7c12700, 0x2640e681, 0xe2c12200, 0x2340e381, 0x21c0e101, 0xe0412080, 
+    0x60c0a001, 0xa1416180, 0xa3c16300, 0x6240a281, 0xa6c16600, 0x6740a781, 0x65c0a501, 0xa4416480, 
+    0xacc16c00, 0x6d40ad81, 0x6fc0af01, 0xae416e80, 0x6ac0aa01, 0xab416b80, 0xa9c16900, 0x6840a881, 
+    0xb8c17800, 0x7940b981, 0x7bc0bb01, 0xba417a80, 0x7ec0be01, 0xbf417f80, 0xbdc17d00, 0x7c40bc81, 
+    0x74c0b401, 0xb5417580, 0xb7c17700, 0x7640b681, 0xb2c17200, 0x7340b381, 0x71c0b101, 0xb0417080, 
+    0x90c15000, 0x51409181, 0x53c09301, 0x92415280, 0x56c09601, 0x97415780, 0x95c15500, 0x54409481, 
+    0x5cc09c01, 0x9d415d80, 0x9fc15f00, 0x5e409e81, 0x9ac15a00, 0x5b409b81, 0x59c09901, 0x98415880, 
+    0x48c08801, 0x89414980, 0x8bc14b00, 0x4a408a81, 0x8ec14e00, 0x4f408f81, 0x4dc08d01, 0x8c414c80, 
+    0x84c14400, 0x45408581, 0x47c08701, 0x86414680, 0x42c08201, 0x83414380, 0x81c14100, 0x40408081, 
+    0x0002e1d0, 0x00040000, 0x00001280, 0x000005dc, 0x0002eb8c, 0x00057f70, 0x00000018, 0x00000638, 
+    0x0002eba4, 0x00057ff0, 0x00000010, 0x00000638, 0x0002eb8c, 0x00041280, 0x0000d6bc, 0x00000654, 
+    0x0002eb8c, 0x0004e93c, 0x00000060, 0x00000654, 0x0002eb8c, 0x00057800, 0x00000490, 0x00000654, 
+    0x00007fff, 0xf3747f62, 0xe7077d8a, 0xdad87a7d, 0xcf047642, 0xc3a970e3, 0xb8e36a6e, 0xaecc62f2, 
+    0xa57e5a82, 0x9d0e5134, 0x9592471d, 0x8f1d3c57, 0x89be30fc, 0x85832528, 0x827618f9, 0x809e0c8c, 
+    0x80000000, 0x809ef374, 0x8276e707, 0x8583dad8, 0x89becf04, 0x8f1dc3a9, 0x9592b8e3, 0x9d0eaecc, 
+    0xa57ea57e, 0xaecc9d0e, 0xb8e39592, 0xc3a98f1d, 0xcf0489be, 0xdad88583, 0xe7078276, 0xf374809e, 
+    0x00008000, 0x0c8c809e, 0x18f98276, 0x25288583, 0x30fc89be, 0x3c578f1d, 0x471d9592, 0x51349d0e, 
+    0x5a82a57e, 0x62f2aecc, 0x6a6eb8e3, 0x70e3c3a9, 0x7642cf04, 0x7a7ddad8, 0x7d8ae707, 0x7f62f374, 
+    0x7fff0000, 0x7f620c8c, 0x7d8a18f9, 0x7a7d2528, 0x764230fc, 0x70e33c57, 0x6a6e471d, 0x62f25134, 
+    0x5a825a82, 0x513462f2, 0x471d6a6e, 0x3c5770e3, 0x30fc7642, 0x25287a7d, 0x18f97d8a, 0x0c8c7f62, 
+    0x00007fff, 0xf9b87fd9, 0xf3747f62, 0xed387e9d, 0xe7077d8a, 0xe0e67c2a, 0xdad87a7d, 0xd4e17885, 
+    0xcf047642, 0xc94673b6, 0xc3a970e3, 0xbe326dca, 0xb8e36a6e, 0xb3c066d0, 0xaecc62f2, 0xaa0a5ed7, 
+    0xa57e5a82, 0xa12955f6, 0x9d0e5134, 0x99304c40, 0x9592471d, 0x923641ce, 0x8f1d3c57, 0x8c4a36ba, 
+    0x89be30fc, 0x877b2b1f, 0x85832528, 0x83d61f1a, 0x827618f9, 0x816312c8, 0x809e0c8c, 0x80270648, 
+    0x80000000, 0x8027f9b8, 0x809ef374, 0x8163ed38, 0x8276e707, 0x83d6e0e6, 0x8583dad8, 0x877bd4e1, 
+    0x89becf04, 0x8c4ac946, 0x8f1dc3a9, 0x9236be32, 0x9592b8e3, 0x9930b3c0, 0x9d0eaecc, 0xa129aa0a, 
+    0xa57ea57e, 0xaa0aa129, 0xaecc9d0e, 0xb3c09930, 0xb8e39592, 0xbe329236, 0xc3a98f1d, 0xc9468c4a, 
+    0xcf0489be, 0xd4e1877b, 0xdad88583, 0xe0e683d6, 0xe7078276, 0xed388163, 0xf374809e, 0xf9b88027, 
+    0x00008000, 0x06488027, 0x0c8c809e, 0x12c88163, 0x18f98276, 0x1f1a83d6, 0x25288583, 0x2b1f877b, 
+    0x30fc89be, 0x36ba8c4a, 0x3c578f1d, 0x41ce9236, 0x471d9592, 0x4c409930, 0x51349d0e, 0x55f6a129, 
+    0x5a82a57e, 0x5ed7aa0a, 0x62f2aecc, 0x66d0b3c0, 0x6a6eb8e3, 0x6dcabe32, 0x70e3c3a9, 0x73b6c946, 
+    0x7642cf04, 0x7885d4e1, 0x7a7ddad8, 0x7c2ae0e6, 0x7d8ae707, 0x7e9ded38, 0x7f62f374, 0x7fd9f9b8, 
+    0x7fff0000, 0x7fd90648, 0x7f620c8c, 0x7e9d12c8, 0x7d8a18f9, 0x7c2a1f1a, 0x7a7d2528, 0x78852b1f, 
+    0x764230fc, 0x73b636ba, 0x70e33c57, 0x6dca41ce, 0x6a6e471d, 0x66d04c40, 0x62f25134, 0x5ed755f6, 
+    0x5a825a82, 0x55f65ed7, 0x513462f2, 0x4c4066d0, 0x471d6a6e, 0x41ce6dca, 0x3c5770e3, 0x36ba73b6, 
+    0x30fc7642, 0x2b1f7885, 0x25287a7d, 0x1f1a7c2a, 0x18f97d8a, 0x12c87e9d, 0x0c8c7f62, 0x06487fd9, 
+    0x00007fff, 0xfcdc7ff6, 0xf9b87fd9, 0xf6957fa7, 0xf3747f62, 0xf0557f0a, 0xed387e9d, 0xea1e7e1e, 
+    0xe7077d8a, 0xe3f47ce4, 0xe0e67c2a, 0xdddc7b5d, 0xdad87a7d, 0xd7d9798a, 0xd4e17885, 0xd1ef776c, 
+    0xcf047642, 0xcc217505, 0xc94673b6, 0xc6737255, 0xc3a970e3, 0xc0e96f5f, 0xbe326dca, 0xbb856c24, 
+    0xb8e36a6e, 0xb64c68a7, 0xb3c066d0, 0xb14064e9, 0xaecc62f2, 0xac6560ec, 0xaa0a5ed7, 0xa7bd5cb4, 
+    0xa57e5a82, 0xa34c5843, 0xa12955f6, 0x9f14539b, 0x9d0e5134, 0x9b174ec0, 0x99304c40, 0x975949b4, 
+    0x9592471d, 0x93dc447b, 0x923641ce, 0x90a13f17, 0x8f1d3c57, 0x8dab398d, 0x8c4a36ba, 0x8afb33df, 
+    0x89be30fc, 0x88942e11, 0x877b2b1f, 0x86762827, 0x85832528, 0x84a32224, 0x83d61f1a, 0x831c1c0c, 
+    0x827618f9, 0x81e215e2, 0x816312c8, 0x80f60fab, 0x809e0c8c, 0x8059096b, 0x80270648, 0x800a0324, 
+    0x80000000, 0x800afcdc, 0x8027f9b8, 0x8059f695, 0x809ef374, 0x80f6f055, 0x8163ed38, 0x81e2ea1e, 
+    0x8276e707, 0x831ce3f4, 0x83d6e0e6, 0x84a3dddc, 0x8583dad8, 0x8676d7d9, 0x877bd4e1, 0x8894d1ef, 
+    0x89becf04, 0x8afbcc21, 0x8c4ac946, 0x8dabc673, 0x8f1dc3a9, 0x90a1c0e9, 0x9236be32, 0x93dcbb85, 
+    0x9592b8e3, 0x9759b64c, 0x9930b3c0, 0x9b17b140, 0x9d0eaecc, 0x9f14ac65, 0xa129aa0a, 0xa34ca7bd, 
+    0xa57ea57e, 0xa7bda34c, 0xaa0aa129, 0xac659f14, 0xaecc9d0e, 0xb1409b17, 0xb3c09930, 0xb64c9759, 
+    0xb8e39592, 0xbb8593dc, 0xbe329236, 0xc0e990a1, 0xc3a98f1d, 0xc6738dab, 0xc9468c4a, 0xcc218afb, 
+    0xcf0489be, 0xd1ef8894, 0xd4e1877b, 0xd7d98676, 0xdad88583, 0xdddc84a3, 0xe0e683d6, 0xe3f4831c, 
+    0xe7078276, 0xea1e81e2, 0xed388163, 0xf05580f6, 0xf374809e, 0xf6958059, 0xf9b88027, 0xfcdc800a, 
+    0x00008000, 0x0324800a, 0x06488027, 0x096b8059, 0x0c8c809e, 0x0fab80f6, 0x12c88163, 0x15e281e2, 
+    0x18f98276, 0x1c0c831c, 0x1f1a83d6, 0x222484a3, 0x25288583, 0x28278676, 0x2b1f877b, 0x2e118894, 
+    0x30fc89be, 0x33df8afb, 0x36ba8c4a, 0x398d8dab, 0x3c578f1d, 0x3f1790a1, 0x41ce9236, 0x447b93dc, 
+    0x471d9592, 0x49b49759, 0x4c409930, 0x4ec09b17, 0x51349d0e, 0x539b9f14, 0x55f6a129, 0x5843a34c, 
+    0x5a82a57e, 0x5cb4a7bd, 0x5ed7aa0a, 0x60ecac65, 0x62f2aecc, 0x64e9b140, 0x66d0b3c0, 0x68a7b64c, 
+    0x6a6eb8e3, 0x6c24bb85, 0x6dcabe32, 0x6f5fc0e9, 0x70e3c3a9, 0x7255c673, 0x73b6c946, 0x7505cc21, 
+    0x7642cf04, 0x776cd1ef, 0x7885d4e1, 0x798ad7d9, 0x7a7ddad8, 0x7b5ddddc, 0x7c2ae0e6, 0x7ce4e3f4, 
+    0x7d8ae707, 0x7e1eea1e, 0x7e9ded38, 0x7f0af055, 0x7f62f374, 0x7fa7f695, 0x7fd9f9b8, 0x7ff6fcdc, 
+    0x7fff0000, 0x7ff60324, 0x7fd90648, 0x7fa7096b, 0x7f620c8c, 0x7f0a0fab, 0x7e9d12c8, 0x7e1e15e2, 
+    0x7d8a18f9, 0x7ce41c0c, 0x7c2a1f1a, 0x7b5d2224, 0x7a7d2528, 0x798a2827, 0x78852b1f, 0x776c2e11, 
+    0x764230fc, 0x750533df, 0x73b636ba, 0x7255398d, 0x70e33c57, 0x6f5f3f17, 0x6dca41ce, 0x6c24447b, 
+    0x6a6e471d, 0x68a749b4, 0x66d04c40, 0x64e94ec0, 0x62f25134, 0x60ec539b, 0x5ed755f6, 0x5cb45843, 
+    0x5a825a82, 0x58435cb4, 0x55f65ed7, 0x539b60ec, 0x513462f2, 0x4ec064e9, 0x4c4066d0, 0x49b468a7, 
+    0x471d6a6e, 0x447b6c24, 0x41ce6dca, 0x3f176f5f, 0x3c5770e3, 0x398d7255, 0x36ba73b6, 0x33df7505, 
+    0x30fc7642, 0x2e11776c, 0x2b1f7885, 0x2827798a, 0x25287a7d, 0x22247b5d, 0x1f1a7c2a, 0x1c0c7ce4, 
+    0x18f97d8a, 0x15e27e1e, 0x12c87e9d, 0x0fab7f0a, 0x0c8c7f62, 0x096b7fa7, 0x06487fd9, 0x03247ff6, 
+    0x00007fff, 0xfe6e7ffe, 0xfcdc7ff6, 0xfb4a7fea, 0xf9b87fd9, 0xf8277fc2, 0xf6957fa7, 0xf5057f87, 
+    0xf3747f62, 0xf1e47f38, 0xf0557f0a, 0xeec67ed6, 0xed387e9d, 0xebab7e60, 0xea1e7e1e, 0xe8927dd6, 
+    0xe7077d8a, 0xe57d7d3a, 0xe3f47ce4, 0xe26d7c89, 0xe0e67c2a, 0xdf617bc6, 0xdddc7b5d, 0xdc597aef, 
+    0xdad87a7d, 0xd9587a06, 0xd7d9798a, 0xd65c790a, 0xd4e17885, 0xd36777fb, 0xd1ef776c, 0xd07976d9, 
+    0xcf047642, 0xcd9275a6, 0xcc217505, 0xcab27460, 0xc94673b6, 0xc7db7308, 0xc6737255, 0xc50d719e, 
+    0xc3a970e3, 0xc2487023, 0xc0e96f5f, 0xbf8c6e97, 0xbe326dca, 0xbcda6cf9, 0xbb856c24, 0xba336b4b, 
+    0xb8e36a6e, 0xb796698c, 0xb64c68a7, 0xb50567bd, 0xb3c066d0, 0xb27f65de, 0xb14064e9, 0xb00563ef, 
+    0xaecc62f2, 0xad9761f1, 0xac6560ec, 0xab365fe4, 0xaa0a5ed7, 0xa8e25dc8, 0xa7bd5cb4, 0xa69c5b9d, 
+    0xa57e5a82, 0xa4635964, 0xa34c5843, 0xa238571e, 0xa12955f6, 0xa01c54ca, 0x9f14539b, 0x9e0f5269, 
+    0x9d0e5134, 0x9c114ffb, 0x9b174ec0, 0x9a224d81, 0x99304c40, 0x98434afb, 0x975949b4, 0x9674486a, 
+    0x9592471d, 0x94b545cd, 0x93dc447b, 0x93074326, 0x923641ce, 0x91694074, 0x90a13f17, 0x8fdd3db8, 
+    0x8f1d3c57, 0x8e623af3, 0x8dab398d, 0x8cf83825, 0x8c4a36ba, 0x8ba0354e, 0x8afb33df, 0x8a5a326e, 
+    0x89be30fc, 0x89272f87, 0x88942e11, 0x88052c99, 0x877b2b1f, 0x86f629a4, 0x86762827, 0x85fa26a8, 
+    0x85832528, 0x851123a7, 0x84a32224, 0x843a209f, 0x83d61f1a, 0x83771d93, 0x831c1c0c, 0x82c61a83, 
+    0x827618f9, 0x822a176e, 0x81e215e2, 0x81a01455, 0x816312c8, 0x812a113a, 0x80f60fab, 0x80c80e1c, 
+    0x809e0c8c, 0x80790afb, 0x8059096b, 0x803e07d9, 0x80270648, 0x801604b6, 0x800a0324, 0x80020192, 
+    0x80000000, 0x8002fe6e, 0x800afcdc, 0x8016fb4a, 0x8027f9b8, 0x803ef827, 0x8059f695, 0x8079f505, 
+    0x809ef374, 0x80c8f1e4, 0x80f6f055, 0x812aeec6, 0x8163ed38, 0x81a0ebab, 0x81e2ea1e, 0x822ae892, 
+    0x8276e707, 0x82c6e57d, 0x831ce3f4, 0x8377e26d, 0x83d6e0e6, 0x843adf61, 0x84a3dddc, 0x8511dc59, 
+    0x8583dad8, 0x85fad958, 0x8676d7d9, 0x86f6d65c, 0x877bd4e1, 0x8805d367, 0x8894d1ef, 0x8927d079, 
+    0x89becf04, 0x8a5acd92, 0x8afbcc21, 0x8ba0cab2, 0x8c4ac946, 0x8cf8c7db, 0x8dabc673, 0x8e62c50d, 
+    0x8f1dc3a9, 0x8fddc248, 0x90a1c0e9, 0x9169bf8c, 0x9236be32, 0x9307bcda, 0x93dcbb85, 0x94b5ba33, 
+    0x9592b8e3, 0x9674b796, 0x9759b64c, 0x9843b505, 0x9930b3c0, 0x9a22b27f, 0x9b17b140, 0x9c11b005, 
+    0x9d0eaecc, 0x9e0fad97, 0x9f14ac65, 0xa01cab36, 0xa129aa0a, 0xa238a8e2, 0xa34ca7bd, 0xa463a69c, 
+    0xa57ea57e, 0xa69ca463, 0xa7bda34c, 0xa8e2a238, 0xaa0aa129, 0xab36a01c, 0xac659f14, 0xad979e0f, 
+    0xaecc9d0e, 0xb0059c11, 0xb1409b17, 0xb27f9a22, 0xb3c09930, 0xb5059843, 0xb64c9759, 0xb7969674, 
+    0xb8e39592, 0xba3394b5, 0xbb8593dc, 0xbcda9307, 0xbe329236, 0xbf8c9169, 0xc0e990a1, 0xc2488fdd, 
+    0xc3a98f1d, 0xc50d8e62, 0xc6738dab, 0xc7db8cf8, 0xc9468c4a, 0xcab28ba0, 0xcc218afb, 0xcd928a5a, 
+    0xcf0489be, 0xd0798927, 0xd1ef8894, 0xd3678805, 0xd4e1877b, 0xd65c86f6, 0xd7d98676, 0xd95885fa, 
+    0xdad88583, 0xdc598511, 0xdddc84a3, 0xdf61843a, 0xe0e683d6, 0xe26d8377, 0xe3f4831c, 0xe57d82c6, 
+    0xe7078276, 0xe892822a, 0xea1e81e2, 0xebab81a0, 0xed388163, 0xeec6812a, 0xf05580f6, 0xf1e480c8, 
+    0xf374809e, 0xf5058079, 0xf6958059, 0xf827803e, 0xf9b88027, 0xfb4a8016, 0xfcdc800a, 0xfe6e8002, 
+    0x00008000, 0x01928002, 0x0324800a, 0x04b68016, 0x06488027, 0x07d9803e, 0x096b8059, 0x0afb8079, 
+    0x0c8c809e, 0x0e1c80c8, 0x0fab80f6, 0x113a812a, 0x12c88163, 0x145581a0, 0x15e281e2, 0x176e822a, 
+    0x18f98276, 0x1a8382c6, 0x1c0c831c, 0x1d938377, 0x1f1a83d6, 0x209f843a, 0x222484a3, 0x23a78511, 
+    0x25288583, 0x26a885fa, 0x28278676, 0x29a486f6, 0x2b1f877b, 0x2c998805, 0x2e118894, 0x2f878927, 
+    0x30fc89be, 0x326e8a5a, 0x33df8afb, 0x354e8ba0, 0x36ba8c4a, 0x38258cf8, 0x398d8dab, 0x3af38e62, 
+    0x3c578f1d, 0x3db88fdd, 0x3f1790a1, 0x40749169, 0x41ce9236, 0x43269307, 0x447b93dc, 0x45cd94b5, 
+    0x471d9592, 0x486a9674, 0x49b49759, 0x4afb9843, 0x4c409930, 0x4d819a22, 0x4ec09b17, 0x4ffb9c11, 
+    0x51349d0e, 0x52699e0f, 0x539b9f14, 0x54caa01c, 0x55f6a129, 0x571ea238, 0x5843a34c, 0x5964a463, 
+    0x5a82a57e, 0x5b9da69c, 0x5cb4a7bd, 0x5dc8a8e2, 0x5ed7aa0a, 0x5fe4ab36, 0x60ecac65, 0x61f1ad97, 
+    0x62f2aecc, 0x63efb005, 0x64e9b140, 0x65deb27f, 0x66d0b3c0, 0x67bdb505, 0x68a7b64c, 0x698cb796, 
+    0x6a6eb8e3, 0x6b4bba33, 0x6c24bb85, 0x6cf9bcda, 0x6dcabe32, 0x6e97bf8c, 0x6f5fc0e9, 0x7023c248, 
+    0x70e3c3a9, 0x719ec50d, 0x7255c673, 0x7308c7db, 0x73b6c946, 0x7460cab2, 0x7505cc21, 0x75a6cd92, 
+    0x7642cf04, 0x76d9d079, 0x776cd1ef, 0x77fbd367, 0x7885d4e1, 0x790ad65c, 0x798ad7d9, 0x7a06d958, 
+    0x7a7ddad8, 0x7aefdc59, 0x7b5ddddc, 0x7bc6df61, 0x7c2ae0e6, 0x7c89e26d, 0x7ce4e3f4, 0x7d3ae57d, 
+    0x7d8ae707, 0x7dd6e892, 0x7e1eea1e, 0x7e60ebab, 0x7e9ded38, 0x7ed6eec6, 0x7f0af055, 0x7f38f1e4, 
+    0x7f62f374, 0x7f87f505, 0x7fa7f695, 0x7fc2f827, 0x7fd9f9b8, 0x7feafb4a, 0x7ff6fcdc, 0x7ffefe6e, 
+    0x7fff0000, 0x7ffe0192, 0x7ff60324, 0x7fea04b6, 0x7fd90648, 0x7fc207d9, 0x7fa7096b, 0x7f870afb, 
+    0x7f620c8c, 0x7f380e1c, 0x7f0a0fab, 0x7ed6113a, 0x7e9d12c8, 0x7e601455, 0x7e1e15e2, 0x7dd6176e, 
+    0x7d8a18f9, 0x7d3a1a83, 0x7ce41c0c, 0x7c891d93, 0x7c2a1f1a, 0x7bc6209f, 0x7b5d2224, 0x7aef23a7, 
+    0x7a7d2528, 0x7a0626a8, 0x798a2827, 0x790a29a4, 0x78852b1f, 0x77fb2c99, 0x776c2e11, 0x76d92f87, 
+    0x764230fc, 0x75a6326e, 0x750533df, 0x7460354e, 0x73b636ba, 0x73083825, 0x7255398d, 0x719e3af3, 
+    0x70e33c57, 0x70233db8, 0x6f5f3f17, 0x6e974074, 0x6dca41ce, 0x6cf94326, 0x6c24447b, 0x6b4b45cd, 
+    0x6a6e471d, 0x698c486a, 0x68a749b4, 0x67bd4afb, 0x66d04c40, 0x65de4d81, 0x64e94ec0, 0x63ef4ffb, 
+    0x62f25134, 0x61f15269, 0x60ec539b, 0x5fe454ca, 0x5ed755f6, 0x5dc8571e, 0x5cb45843, 0x5b9d5964, 
+    0x5a825a82, 0x59645b9d, 0x58435cb4, 0x571e5dc8, 0x55f65ed7, 0x54ca5fe4, 0x539b60ec, 0x526961f1, 
+    0x513462f2, 0x4ffb63ef, 0x4ec064e9, 0x4d8165de, 0x4c4066d0, 0x4afb67bd, 0x49b468a7, 0x486a698c, 
+    0x471d6a6e, 0x45cd6b4b, 0x447b6c24, 0x43266cf9, 0x41ce6dca, 0x40746e97, 0x3f176f5f, 0x3db87023, 
+    0x3c5770e3, 0x3af3719e, 0x398d7255, 0x38257308, 0x36ba73b6, 0x354e7460, 0x33df7505, 0x326e75a6, 
+    0x30fc7642, 0x2f8776d9, 0x2e11776c, 0x2c9977fb, 0x2b1f7885, 0x29a4790a, 0x2827798a, 0x26a87a06, 
+    0x25287a7d, 0x23a77aef, 0x22247b5d, 0x209f7bc6, 0x1f1a7c2a, 0x1d937c89, 0x1c0c7ce4, 0x1a837d3a, 
+    0x18f97d8a, 0x176e7dd6, 0x15e27e1e, 0x14557e60, 0x12c87e9d, 0x113a7ed6, 0x0fab7f0a, 0x0e1c7f38, 
+    0x0c8c7f62, 0x0afb7f87, 0x096b7fa7, 0x07d97fc2, 0x06487fd9, 0x04b67fea, 0x03247ff6, 0x01927ffe, 
+    0x50102000, 0x68284808, 0x64244404, 0x74345414, 0x62224202, 0x72325212, 0x6a2a4a0a, 0x7a3a5a1a, 
+    0x61214101, 0x71315111, 0x69294909, 0x79395919, 0x65254505, 0x75355515, 0x6d2d4d0d, 0x7d3d5d1d, 
+    0x28081000, 0x34142404, 0x32122202, 0x3a1a2a0a, 0x31112101, 0x39192909, 0x35152505, 0x3d1d2d0d, 
+    0x14040800, 0x1a0a1202, 0x19091101, 0x1d0d1505, 0xffff1603, 0xd52380f2, 0x04f51a09, 0x2304b95a, 
+    0x231a0a0d, 0x04351a04, 0x1a045f1a, 0x01230487, 0x04771a0b, 0x2904bb1a, 0x0c712324, 0x1a04891a, 
+    0xb91a049b, 0x04e51a04, 0x1a34af23, 0x486904f7, 0x1a0d3123, 0x6d1a044f, 0x04a11a04, 0x2304b31a, 
+    0xd1230e91, 0x04f31a0f, 0x1a102323, 0xd31a04b5, 0x04f11a04, 0x1b111f23, 0x1970125d, 0x2edd1b04, 
+    0x8b2f2204, 0x2950302d, 0x1cb11a04, 0x1a131b23, 0xff1a04cd, 0x142d2304, 0xc015731b, 0x091b0419, 
+    0x04197416, 0x1a045d1a, 0xd3230485, 0x1a7d8b19, 0x32f5233c, 0x1a331523, 0x591a0433, 0x04771a04, 
+    0x1ab02f1a, 0xff1a6465, 0x34b31a04, 0x1938c32a, 0x17d52304, 0x1a354d23, 0x851a0469, 0x04971a04, 
+    0x1a04a91a, 0xcd1a04bb, 0x04e91a04, 0x1a360523, 0xa0a90421, 0x1a041a09, 0x491a2c2b, 0x046d1a04, 
+    0x23385b9a, 0xf11b1bfd, 0x0419d81c, 0x09044d1a, 0x04295026, 0x1a307f1a, 0xd11a04af, 0x21a72304, 
+    0x1a04891a, 0x41235095, 0x1ee5231d, 0x281f034b, 0x1a085b1a, 0x311a1c1f, 0x04431a04, 0x1a04651a, 
+    0x23112851, 0xc01a0580, 0x04d01a04, 0x3104f01a, 0x01821032, 0x041affb2, 0x015a7101, 0x3a120101, 
+    0x998101ff, 0x01310321, 0x3d7c8a03, 0x999a2b31, 0x3fa93c01, 0xd3d30133, 0xa921193f, 0x09160178, 
+    0x1309b113, 0x071241c2, 0x02722252, 0xe7041088, 0x0ded288c, 0xf34d3fae, 0x2474538e, 0x212980f4, 
+    0x08010c10, 0x054c4b40, 0x06020403, 0x04124801, 0x08010206, 0x02030201, 0x0f0a050c, 0x0e220f01, 
+    0x031c21c0, 0x292c0301, 0x3904790c, 0x024e1219, 0xb7127411, 0x4b04b11a, 0x14b40502, 0x1a150404, 
+    0x07320240, 0x1208301a, 0x01351414, 0x127f1276, 0x127b127e, 0x22751278, 0x0808130c, 0x04298012, 
+    0x60140c29, 0x601c02e1, 0x0d0e02d5, 0x2a200718, 0xdc49982b, 0xc7399849, 0x12981f09, 0x046a1a70, 
+    0x063c9869, 0x32981606, 0x12181206, 0xb60a1a20, 0x3f123b12, 0x3c123e12, 0x38ba3a12, 0xc70b1a98, 
+    0x2b98a02a, 0x0c3202d3, 0x1a191018, 0x98039a98, 0x20090c29, 0x1a4b1298, 0x98690446, 0x1708083c, 
+    0x12053298, 0x08101a0c, 0x1d126d12, 0x1e1a1f12, 0x3a1c1206, 0x98698c1b, 0x2afb0a1a, 0xd21a98c0, 
+    0xff1b316d, 0xff0242ff, 0x1f2f0107, 0x07ff3fff, 0x3a0203ff, 0x1b110201, 0x1a0c0fff, 0x16020a0f, 
+    0xae5e0303, 0x014c02ae, 0xda238022, 0x1a190814, 0xffffd475, 0xffffe80d, 0xfffff580, 0xfffffb0b, 
+    0xfffffe74, 0xffffffa2, 0x38851a38, 0xc75c1218, 0xe6caffff, 0xf8ceffff, 0xfdb2ffff, 0x9d4affff, 
+    0x1a021c23, 0x4f1a04e6, 0x483b1a04, 0xbb1a38e9, 0xcf2b1e2c, 0x684effff, 0x2304be1a, 0x5e1a0479, 
+    0x40361a38, 0x1a34641a, 0xf8327894, 0x1a18ae1a, 0x9b192055, 0x2338ff2a, 0x0a18082a, 0xffffc868, 
+    0xfffff10e, 0xe41a14b4, 0x244a1a2c, 0x1e3c581a, 0xfffffacf, 0x1d2340ed, 0x18b81a03, 0x2a0cc01a, 
+    0x38197cd1, 0x18160423, 0xfff6b70a, 0xfff499ff, 0x367c42ff, 0xfffffc7d, 0x28561ad0, 0x1a30971a, 
+    0x781a44c5, 0x0cc31a04, 0x1a4cd41a, 0x3829183e, 0x1e400a1a, 0xffffcc92, 0x22111871, 0x3c6a1a09, 
+    0xfff92527, 0x1a11a3ff, 0xa91e3077, 0xb7fffff7, 0x0b1c231c, 0x1a38ef1a, 0x3829acc1, 0x181a8f23, 
+    0xffd0490e, 0xffe845ff, 0xfff578ff, 0x1a7cf9ff, 0x341ab0e0, 0x28351ac0, 0xeb1a9732, 0x196dc238, 
+    0x3e342338, 0xe5ab0a18, 0xd3afffff, 0x3cbaffff, 0x1a60181a, 0xcf1a549b, 0x8c2e1acc, 0x1ab8bd1a, 
+    0x501a0cf2, 0x04f81a44, 0x23e0165a, 0x0a180e94, 0xffffd232, 0xfffff25e, 0x091aa0fe, 0x28281a18, 
+    0x3d328a32, 0x1a7c361a, 0x791a3cc9, 0x1ac63204, 0x18413c69, 0x7154c721, 0xb8aa63e7, 0xdc553173, 
+    0xee2a9839, 0x77154c1c, 0x3b8aa60e, 0x9dc55307, 0xcee2a983, 0x601a1fc1, 0x1fb01a1f, 0x1a1f581a, 
+    0x22181fac, 0x766f4d56, 0x3b37a64c, 0x1d9bd3a6, 0x8ecde953, 0xc766f4a9, 0x63b37a54, 0x31d9bdaa, 
+    0x98ecde55, 0x151a1f2a, 0x1f8a1a1f, 0x1a1fc51a, 0x711a1fe2, 0x1fb81a1f, 0x1a1fdc1a, 0x771a1fee, 
+    0x1f3b1a1f, 0x521f9d1a, 0x010113ce, 0x07490239, 0x0d291029, 0x05390a19, 0x0d202811, 0x06f6d9c4, 
+    0x037b6ce2, 0x81bdb671, 0x40dedb38, 0x206f6d9c, 0x1037b6ce, 0x881bdb67, 0x1a1fedb3, 0xc31a1f86, 
+    0x1f611a1f, 0x1a1fb01a, 0x2c1a1f58, 0x1f961a1f, 0x1a1fcb1a, 0x721a1fe5, 0x1f392a1f, 0xab601618, 
+    0xd5b03881, 0x6ad89c40, 0x356cce20, 0x1ab66710, 0x465bb388, 0x1a65ad1a, 0x1f196556, 0x1a1fdb1a, 
+    0xb61a1f6d, 0x1fdb1a1f, 0x699ded2a, 0x499c79aa, 0x29ac39b3, 0x250d181e, 0x12421084, 0x09210842, 
+    0x0b108421, 0x1a0b081a, 0x421a0b84, 0x0b211a0b, 0x041a1469, 0x0b021a0b, 0x1114011a, 0x94a12018, 
+    0x4a504252, 0xa5282129, 0x52941094, 0x294a084a, 0x94a58425, 0x4a524212, 0xa5292109, 0x421a1484, 
+    0x14211a14, 0x1b14101a, 0x1a1f2108, 0x081a1f10, 0x1f841a1f, 0x1a1f421a, 0x101a1f21, 0x1f081a1f, 
+    0xc1a4842a, 0x05c9b649, 0x1a2c801a, 0x100a2c40, 0xb0a99c20, 0x1a0b901a, 0xa41a0b48, 0x14521a14, 
+    0x1a14291a, 0x4a1a1494, 0x1fa51a14, 0x481a1419, 0x94a41414, 0x42101404, 0x21081402, 0x10842301, 
+    0x19084223, 0x11651988, 0x19116519, 0x1a1f1965, 0x841a1f08, 0x1f421a1f, 0x6a1f211a, 0x019a8e10, 
+    0x01a5b905, 0x100a1813, 0x0f100f0e, 0x10011010, 0x39353904, 0x143a0101, 0x1c01ffff, 0x0802fffe, 
+    0xfd144e29, 0xfb1a04ff, 0xfffe1604, 0x1406ffff, 0x1c0dfff6, 0x0e09fff3, 0x11fff914, 0x1dffe714, 
+    0x0fffe614, 0xea140212, 0xc8142aff, 0xd2143aff, 0x111214ff, 0x5effc514, 0x6dff8f14, 0x121cb51a, 
+    0xff6f143f, 0xff1014d3, 0xff8116d8, 0x10ecffe5, 0xdcfe1f18, 0x69fc4202, 0xc4fb3c04, 0xbefb9704, 
+    0xe1fd2403, 0x1bff1401, 0x28147f12, 0x2d14f0ff, 0xc11691ff, 0x4bfff1ff, 0x71ff9314, 0x3bffa214, 
+    0xecffef16, 0xc6142eff, 0xd61c38ff, 0x147816ff, 0x1c1afff1, 0x1819ffe3, 0x3a78071a, 0x0a1290f7, 
+    0x12b4fa1a, 0xfffc1c02, 0x035a0405, 0x02c449ba, 0x025a0119, 0x1c0332dc, 0x520cfffb, 0x1204131a, 
+    0x14061208, 0x1429ffe8, 0x1a34ffcc, 0x21120eda, 0x75ffb214, 0x7eff7714, 0x127cb41a, 0xda16188e, 
+    0xad01c3fe, 0x0402c1fd, 0x3f02fcfd, 0x3d0253fd, 0x720126fe, 0x144c12e8, 0x1489ff82, 0x3e4eff8b, 
+    0xfff8ffdf, 0xd71c4026, 0x149a18ff, 0x1a11fff8, 0xf41a04ed, 0xfd5a219e, 0x1cfe1aa4, 0x09ffea14, 
+    0x122a111a, 0xff921457, 0xffb9166c, 0x1e80fff7, 0x01b7feea, 0x121160b3, 0x030b18fd, 0x024dfd3f, 
+    0x0116fe49, 0x47122880, 0x6eff9414, 0x1a56a91a, 0x161a28ef, 0x1b1021a4, 0x20131e48, 0x23fd21fa, 
+    0x2862261f, 0x2d4f2ac6, 0x32d62ffe, 0x390a35d9, 0x20283c6b, 0xcf43cb40, 0x924c1047, 0x67555850, 
+    0x6f5fc25a, 0xcf6b7265, 0xb2788e71, 0x4787437f, 0x0297c58f, 0x3fff0c10, 0x016201a9, 0x01020128, 
+    0x12cb12e6, 0xff2018b7, 0xbd035f3f, 0xeb023602, 0x79018f01, 0xff015101, 0x9704343f, 0x7602e003, 
+    0xde01fe02, 0x1810a401, 0x3903ff0e, 0x1c029003, 0x9a01ae02, 0x18106b01, 0xd103730e, 0xf5024a02, 
+    0x9201a301, 0x08106a01, 0x048d210e, 0x03760410, 0x022302cb, 0x40b001f4, 0x122130c9, 0x122d1223, 
+    0x12411237, 0x0255124b, 0xdd165f11, 0x1e018002, 0x7d101b00, 0x71ff5eff, 0x6bff78ff, 0x80ff6aff, 
+    0x81ff93ff, 0x73ff66ff, 0xdfffa3ff, 0x12fffaff, 0x19092b01, 0x01ff1a3c, 0x19020869, 0x09cf1996, 
+    0xff176722, 0x026503ff, 0x48742301, 0x23233023, 0xd823157c, 0x0b1e230e, 0x2308c923, 0x1a23073c, 
+    0x054e2306, 0x1a04b323, 0xdb23043e, 0x048d1a03, 0x1a044f1a, 0xf4230423, 0x04d51a02, 0x1a04b91a, 
+    0x891a049c, 0x04781a04, 0x1a04691a, 0x5b1a0461, 0x044d1a04, 0x1a044e1a, 0x411a044b, 0x04461a04, 
+    0x5a04441a, 0x4c5a0840, 0x04581a04, 0x1a04631a, 0x831a0471, 0x048c1a04, 0x5a04931a, 0x0429609a, 
+    0x1a04b81a, 0xd31a04c7, 0x04ef1a04, 0x1a04f91a, 0x251a880a, 0x04481a04, 0x1a04541a, 0xa61a0483, 
+    0x04b71a04, 0x1a04df1a, 0x1b1a04fd, 0x04541abc, 0x1a04711a, 0xd01a04a3, 0x04f41a04, 0x1adc1f1a, 
+    0x931a045d, 0x04dc1a04, 0x1af02a1a, 0xe91a047f, 0x07472304, 0x1a04a01a, 0x5a2304f9, 0x04c41a08, 
+    0x1a092523, 0x1b23049e, 0x04c21a0a, 0x1a0b5923, 0x7e2304ce, 0x0d4f230c, 0x230e3d23, 0x26230f32, 
+    0x116c2310, 0x23128f23, 0x422313e0, 0x169c2315, 0x4017af1b, 0x222c191a, 0x1ca7231b, 0x231ea923, 
+    0x65232127, 0x262c2323, 0x23293723, 0xa5232c18, 0x3238232e, 0x23360423, 0x4c233939, 0x423c1b3e, 
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+    0xe12fff1e, 0xe1d040b0, 0xe1c44001, 0xe1a05213, 0xe0055001, 0xe1844005, 0xe1c040b0, 0xe12fff1e, 
+    0xe1d000b0, 0xe0000001, 0xe1a00230, 0xe12fff1e, 0xe1c010b0, 0xe12fff1e, 0xe1d000b0, 0xe12fff1e, 
+    0xf3074004, 0x000402bc, 0x00000000, 0xf303a1e2, 0xf303a44a, 0xf303a400, 0xf303a402, 0xf303a404, 
+    0xf303a406, 0xf303a40a, 0xf303a408, 0xf303a40c, 0xf303a412, 0xf303a410, 0xf303a414, 0x200007f0, 
+    0x0000027d, 0x00007495, 0x000074a3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x000074b1, 0x00000000, 0x00000000, 0x00000263, 0x000074bf, 0x000074cd, 
+    0x000074db, 0x00007519, 0x00007519, 0x000074e9, 0x000074ef, 0x000074f5, 0x000074fb, 0x00007501, 
+    0x00007507, 0x0000750d, 0x00007513, 0x00007519, 0x00007519, 0x00007519, 0x00007519, 0x00007519, 
+    0x00007519, 0x00007519, 0x00007519, 0x00007519, 0x00007519, 0x00007519, 0x00007519, 0x00007519, 
+    0x00007519, 0x00007519, 0x00007519, 0x00007519, 0x00007519, 0x00007519, 0x00007519, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x36666e49, 
+    0x00d10209, 0x01000100, 0x01002401, 0x20000100, 0x20000200, 0x00000000, 0x20000300, 0x00000008, 
+    0x00000080, 0x20000224, 0x20000600, 0x00000000, 0x00000010, 0x20000264, 0x20000244, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf802f000, 
+    0xf83ef000, 0xc830a00c, 0x18243808, 0x46a2182d, 0x46ab1e67, 0x465d4654, 0xd10142ac, 0xf830f000, 
+    0x3e0f467e, 0x46b6cc0f, 0x42332601, 0x1afbd000, 0x46ab46a2, 0x47184333, 0x00007a80, 0x00007aa0, 
+    0xd3023a10, 0xc178c878, 0x0752d8fa, 0xc830d301, 0xd501c130, 0x600c6804, 0x00004770, 0x24002300, 
+    0x26002500, 0xd3013a10, 0xd8fbc178, 0xd3000752, 0xd500c130, 0x4770600b, 0xbd1fb51f, 0xbd10b510, 
+    0xfc87f007, 0xf7ff4611, 0xf000fff7, 0xf007f83f, 0xb403fc9f, 0xfff2f7ff, 0xf000bc03, 0x0000f834, 
+    0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08, 
+    0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, 0x1e761c6d, 0xbd70d2f9, 0xe7fee7fe, 0xe7fee7fe, 
+    0xe7fee7fe, 0xe7fee7fe, 0xe7fee7fe, 0xe7fee7fe, 0xe7fee7fe, 0xe7fee7fe, 0xf7ffb510, 0xbd10ff7f, 
+    0x4603460a, 0xe7fe4770, 0x00004770, 0xfffcf7ff, 0xf982f007, 0xf9def007, 0x20004d2e, 0x6028462c, 
+    0x07092105, 0x60281840, 0xf892f007, 0xf835f007, 0x07002003, 0x49288a81, 0x68228281, 0x48271c49, 
+    0x85111812, 0x18086821, 0x1f2f8e80, 0x70380b00, 0xf845f003, 0xfadcf007, 0x4e214922, 0x2003600e, 
+    0x04406822, 0x60224382, 0x2400462f, 0xe019460d, 0x21926828, 0x30405c09, 0x80810209, 0xf87df003, 
+    0x22036828, 0x7cc03080, 0x02000452, 0x60281980, 0x7c803080, 0x07806839, 0x0b404391, 0x1c644301, 
+    0x6039b2e4, 0x1f00480b, 0x42847800, 0x2403d3e0, 0xf0000464, 0x6828f9de, 0x7cc03080, 0x19800200, 
+    0x30806028, 0x68397c80, 0x43a10780, 0x43010b40, 0xe7ee6039, 0x20000084, 0x00007fff, 0x0001a1c0, 
+    0x20000300, 0x20000090, 0x215648fe, 0x5c0a6800, 0x31804601, 0xd0042a01, 0x734a7982, 0x738879c0, 
+    0x7a024770, 0x7a40734a, 0x49f7e7f9, 0x47705c08, 0x2100b51c, 0x8011466a, 0x49f48090, 0x7b094af2, 
+    0x5c524cf0, 0x31606821, 0x429a780b, 0x2216d917, 0x2301568a, 0x429a07db, 0x0700d111, 0x28020f80, 
+    0x2008d00d, 0x8018466b, 0x758a1e52, 0x29017d09, 0xf006d001, 0x6820f936, 0x7d003060, 0x2001bd1c, 
+    0xe7f87508, 0x680248e2, 0x185249e2, 0x68038ed2, 0x0f520492, 0x8edb185b, 0x055b6800, 0x18d20f5b, 
+    0x18400852, 0x06808ec0, 0x18100e80, 0x49d64770, 0x5c083115, 0xb57c4770, 0x48d44605, 0x7b0049d2, 
+    0x5c0c3115, 0x46692000, 0x808d8008, 0xffdaf7ff, 0x0f8906a9, 0x42a04dcb, 0x682ad80a, 0x7d523260, 
+    0xd20542a2, 0xd0032903, 0x466a2110, 0xe0158011, 0x42a02601, 0x682ad90f, 0x7d533260, 0xd20a42a3, 
+    0x0064181b, 0xd90642a3, 0xd0042902, 0x466b2120, 0x74d68019, 0x6829e002, 0x74ce3160, 0x31606829, 
+    0x46687548, 0x06818800, 0xd0010f89, 0xf8d9f006, 0x30606828, 0xbd7c7cc0, 0x4cb2b5f8, 0x68202603, 
+    0x30400736, 0x27017ac0, 0x4db13825, 0xf0070003, 0x2107fb59, 0xa1818f6f, 0x0005bfb1, 0x20078ab0, 
+    0x82b043c0, 0x2107682a, 0x304048aa, 0x85111812, 0x21028ab1, 0x82b143c9, 0x2102682a, 0x84011810, 
+    0xf0072008, 0xf006f9c0, 0x6821ff54, 0x20008448, 0x76083140, 0x46016820, 0x7d8a3180, 0xd0092a00, 
+    0x07527f42, 0x222bd53c, 0x72823040, 0xf006764f, 0xbdf8f8cc, 0xff3df006, 0x6820b281, 0x1a518c42, 
+    0xdb2b2964, 0x5c092158, 0xd1022900, 0x05c08800, 0x2102d40d, 0xf007200f, 0x8ab0f996, 0x43c02001, 
+    0x682882b0, 0x0349210d, 0x86471840, 0x8ab0e016, 0x43c02001, 0x682882b0, 0x18404987, 0x463a8cc0, 
+    0x68284382, 0x84c21840, 0xff13f006, 0x84486821, 0x760f3140, 0x201d2102, 0xf975f007, 0xe07f2125, 
+    0x31ff6829, 0x8e493101, 0x0e890689, 0x80413040, 0x22266820, 0x31404601, 0x308072ca, 0x28007dc0, 
+    0x8848d0b7, 0xff37f7ff, 0xd00d2801, 0x21286820, 0x72c13040, 0x21986820, 0x29005c09, 0x2114d0a9, 
+    0x72813040, 0xe05d2126, 0x20006821, 0x80483140, 0x22276820, 0x31404601, 0x308072ca, 0x28007dc0, 
+    0x8848d097, 0xfed4f7ff, 0xd00d2801, 0x21296820, 0x72c13040, 0x21986820, 0x29005c09, 0x2114d089, 
+    0x72813040, 0xe03d2127, 0xf84ff006, 0x212a6820, 0x72c13040, 0x49576828, 0x18403180, 0x07408880, 
+    0xd0bd0fc0, 0x21996820, 0x212b540f, 0x72c13040, 0x30ff6828, 0x8dc03001, 0x07c008c0, 0xd0000fc0, 
+    0x6828e767, 0x300130ff, 0x07408dc0, 0xd1f70fc0, 0x30ff6828, 0x8dc03001, 0x0fc00780, 0x6828d1f0, 
+    0x300130ff, 0x07c08dc0, 0x8ab0d0ea, 0x43c02004, 0x682a82b0, 0x483f2104, 0x18103040, 0x212c8401, 
+    0x30406820, 0xbdf872c1, 0x4c39b5f8, 0x30ff6820, 0x8d803001, 0x07804a33, 0x4f360fc1, 0x68102395, 
+    0x072d2503, 0x37404e35, 0x29005419, 0x7f40d019, 0xd4090700, 0x22184b2d, 0x20172116, 0x5659569a, 
+    0x23005618, 0xfc57f006, 0x82ae8aa8, 0x20016821, 0x840819c9, 0x68004823, 0x07807800, 0x1c4017c0, 
+    0x8aa8bdf8, 0x682182ae, 0x19c92004, 0x20008408, 0xb5febdf8, 0x24004d1b, 0x30806828, 0x28007c80, 
+    0xf002d119, 0x270ffdfb, 0xf006033f, 0x4e1cfe11, 0x68310c00, 0x1a400c09, 0xdd0c42b8, 0x21ff4819, 
+    0x21f07081, 0x70047041, 0xf0072003, 0x6830f80f, 0x18400439, 0x4e0e6030, 0x480f6831, 0x18083040, 
+    0x0bc08d00, 0x2300d106, 0x461a9907, 0x94002001, 0xffc1f006, 0x31806829, 0x72c87a88, 0x68024804, 
+    0xe011200d, 0x20000090, 0x00007b82, 0x20000200, 0x20000084, 0x0001a040, 0x0001a180, 0x0000fffa, 
+    0x20000088, 0x2000008c, 0x18100340, 0x0ac28f80, 0x0601728a, 0xd1030fc9, 0x0e800680, 0xfa30f002, 
+    0x7c416828, 0xd0192900, 0xf007000b, 0x0708f9db, 0x0b080507, 0x0713110e, 0xfec3f000, 0xf000bdfe, 
+    0xbdfeff35, 0xffb5f001, 0xf001bdfe, 0xbdfef9d5, 0xe0002000, 0xf0012001, 0xbdfefb04, 0x22522100, 
+    0x88015411, 0x078a4dfe, 0x2a002401, 0x4efddb36, 0xd5330589, 0x7a813080, 0xd92f2903, 0xd02d2911, 
+    0x28007d40, 0x48f8d02a, 0x200d6801, 0x18080340, 0x07c08e80, 0xf006d122, 0x6836fdbc, 0x46304607, 
+    0xf0073036, 0x2110f8b7, 0x49f041c8, 0x42881bc0, 0x05c8d314, 0x82858a81, 0x680148eb, 0x0340200d, 
+    0x86441808, 0x0c388737, 0x364086f0, 0x21027a70, 0x72704308, 0xf007201e, 0xbdfef806, 0x68304ee1, 
+    0x7ac13080, 0xd1062900, 0x28007a80, 0x2101d013, 0xf0062003, 0x6830fff8, 0x7ac13080, 0xd9012903, 
+    0xd1082911, 0x28037a80, 0x2811d905, 0x2101d003, 0xf0062026, 0x48d3ffe8, 0x46016800, 0x7a8a3180, 
+    0xd01f2a00, 0xd07d2a01, 0xd07c2a02, 0xd07b2a03, 0x7a8f3940, 0x003b4ecb, 0xf954f007, 0xf0f1f125, 
+    0xeeefefef, 0xecedeeee, 0xe8e9eaeb, 0xe4e5e6e7, 0xe0e1e2e3, 0xdfdedfdf, 0xdfdfdfdf, 0xdedfdfde, 
+    0x00dedddd, 0x4ebf7ac8, 0xd0032800, 0x20012102, 0xffb9f006, 0x68394fbc, 0x180848bd, 0x07408a40, 
+    0xd0230f80, 0xd0292801, 0x30406830, 0x07c07a40, 0xf002d001, 0x6830fc75, 0x30402101, 0x68387481, 
+    0x4fb4463e, 0x8e0019c0, 0x0f800740, 0xd07d2801, 0x7d204cb1, 0xd1902800, 0x46039000, 0x21042201, 
+    0xf0069001, 0x2001ff1a, 0xbdfe7520, 0x30406830, 0x07c07a40, 0xf002d0f9, 0xbdfefc53, 0x48a56839, 
+    0x180838c0, 0x07c08980, 0xd0110fc0, 0x07002003, 0x82858a81, 0x2000683a, 0x39c0499e, 0x81881851, 
+    0xfc7df002, 0x22bf6830, 0x7a013080, 0x72014011, 0x07002003, 0x21028a81, 0x828143c9, 0x2002683a, 
+    0xe0024994, 0xe156e0b3, 0x39c0e24a, 0x81481851, 0xfc26f002, 0x78006830, 0xd00107c0, 0xfc7ff006, 
+    0x488b6839, 0x8ac01808, 0x07006839, 0x31ff0f00, 0x8d893101, 0x07892300, 0x01090fc9, 0x68304301, 
+    0x0a028800, 0x43110212, 0x0a000600, 0x20034301, 0x91012202, 0x46119000, 0xf0062001, 0xf002febe, 
+    0xf7fffd49, 0x2800fe41, 0x8a81487c, 0x2102d014, 0x828143c9, 0x2102683b, 0x189a4a79, 0x8a8180d1, 
+    0x82814978, 0x0189210d, 0xe000683a, 0x20d1e038, 0x18100240, 0xe01184c1, 0x82814972, 0x683b22ff, 
+    0x21d13241, 0x18590249, 0x8a8184ca, 0x43c92102, 0x683a8281, 0x496a2000, 0x80c81851, 0x8a814867, 
+    0x68398285, 0x30404866, 0x81441808, 0x7ac16830, 0x72c11c49, 0xe3abbdfe, 0xe33ee220, 0xe3fbe3c0, 
+    0xe23ce2a9, 0xe3cfe31a, 0xe332e358, 0xe304e30b, 0xe283e3a4, 0xe2ece257, 0xe231e24d, 0xe222e31e, 
+    0x8aa04c56, 0x43c02002, 0x683182a0, 0x19c92002, 0x68308548, 0x8d8019c0, 0x0fc007c0, 0x8aa0d007, 
+    0x683182a5, 0x19c92000, 0xf0028588, 0xf002fc16, 0x4849fbc2, 0x07c07800, 0xf006d001, 0x4846fbef, 
+    0x88002102, 0xba402300, 0x90019100, 0x21052201, 0xf0064618, 0x4840fe42, 0x75012100, 0xfca0f002, 
+    0x82a58aa0, 0x20016831, 0x854819c9, 0x4e36e7b2, 0x270d6831, 0x19c9037f, 0x07898f49, 0x4601d005, 
+    0x7a4a3140, 0x401a23fd, 0x4601724a, 0x7a4a3140, 0xd00507d2, 0x28007880, 0x7a08d124, 0xd0212800, 
+    0x72882000, 0x7800482c, 0xd5360640, 0x68004825, 0x07c07800, 0x6831d031, 0x18084825, 0x07008ac0, 
+    0x28080f00, 0x4825d186, 0x82858a81, 0x22006833, 0x31404923, 0x805a185b, 0x82858a82, 0x18406830, 
+    0xe7778044, 0xfb3cf002, 0xfd7ef7ff, 0xd0d92800, 0x8a81481a, 0x68328285, 0x024921d1, 0x84d41852, 
+    0x82858a82, 0x32ff6832, 0x85943201, 0x82858a82, 0x20006832, 0x84c81851, 0x6830e7c4, 0x8e4019c0, 
+    0x0fc00780, 0x480dd108, 0x490f8a81, 0x20018281, 0x03406831, 0x840819c9, 0x19c06830, 0xe0158f80, 
+    0x0000fffe, 0x20000090, 0x20000084, 0x0000ea60, 0x0001a300, 0x0001a1c0, 0x20000200, 0x30000000, 
+    0x0001a0c0, 0x0000fc0f, 0x0000dfff, 0x0ac24dfe, 0x46016828, 0x728a3180, 0xd00c2a01, 0x1c497a81, 
+    0x68307281, 0x8f4019c0, 0xb2c02300, 0x21072202, 0x90019400, 0x7ac8e00b, 0xd00b2801, 0x19c06830, 
+    0x23008f40, 0x2202b2c0, 0x94002106, 0x20019001, 0xfd93f006, 0x3040e12e, 0x4eeb7a81, 0x7a412900, 
+    0x4321d005, 0x20027241, 0x90019400, 0x4321e12b, 0x79c27241, 0x00520852, 0x078a71c2, 0x2000d40a, 
+    0xf00643c0, 0xf006fb62, 0x6830fb75, 0x870149df, 0xe00886c1, 0x401122fd, 0xf0067241, 0x6831fb7a, 
+    0x0c008708, 0x683086c8, 0x30404601, 0x07d27a42, 0x7889d005, 0xd1582900, 0x28007a00, 0x2003d055, 
+    0x8a810700, 0x43c92120, 0x49d18281, 0x680a2000, 0x0349210d, 0x84081851, 0xfdebf002, 0x682a4dcc, 
+    0x181048cc, 0x68298ac0, 0x0f000700, 0x310131ff, 0x23008d89, 0x0fc90789, 0x43010109, 0x88006830, 
+    0x02120a02, 0x06004311, 0x43010a00, 0x91012003, 0x22029000, 0x2001211a, 0xfd2ff006, 0x210248be, 
+    0x460a8800, 0x9100ba40, 0x23009001, 0x20012119, 0xfd23f006, 0x30806830, 0x7a004684, 0xd4740640, 
+    0x21032200, 0x8a880709, 0x43c02084, 0x07d08288, 0x0e00682e, 0x18f64bb1, 0x85b01d00, 0x21002000, 
+    0xd2052810, 0x1a1b231f, 0xf002e004, 0xe7b5fceb, 0x3b104603, 0xb2db4eaa, 0x2a008ab7, 0x271fd007, 
+    0x82b743ff, 0x4ea5682f, 0x85f319be, 0x4fa5e006, 0x682f82b7, 0x4ba1021e, 0x859e18fb, 0x682f2300, 
+    0x36804e9e, 0x8a3619be, 0x07f60a36, 0xd0010ff6, 0xb2c91c49, 0xb2db1c5b, 0xd3f02b0a, 0xd0042800, 
+    0xd81e2905, 0xd002281f, 0x2905e017, 0x4894d915, 0x8a812a00, 0x211fd008, 0x828143c9, 0x2010682b, 
+    0x1859498e, 0xe00c85c8, 0x8281498e, 0x682b2001, 0x498a0300, 0x85881859, 0x1c40e003, 0x2820b2c0, 
+    0x1c52d3ad, 0x2a02b2d2, 0x4885d39b, 0x21048a81, 0x828143c9, 0x2000682a, 0x18514980, 0x46608588, 
+    0x21407a00, 0x46614308, 0x487d7208, 0x497e8a81, 0x21018281, 0x0389682a, 0x0340200d, 0x84011810, 
+    0x68014873, 0x0340200d, 0x8f801808, 0x0ac04d6e, 0x31806829, 0x28037288, 0x7ac9d005, 0xd9082903, 
+    0xd0062911, 0x7ac8e00d, 0xd00a2803, 0x20252101, 0x2803e005, 0x2811d905, 0x2101d003, 0xf0062026, 
+    0x6829fcf2, 0x7a483140, 0xd40a0782, 0x43c02000, 0xfa5bf006, 0xfa6ef006, 0x495c6828, 0x86c18701, 
+    0x22fde008, 0x72484010, 0xfa73f006, 0x87086829, 0x86c80c00, 0x30406828, 0xe5db7484, 0x43207a48, 
+    0x94007248, 0x23009401, 0x21152202, 0xf0062001, 0x4853fc54, 0x82858a81, 0x6801484d, 0x0340200d, 
+    0x86441808, 0x2a07e5c6, 0x728cd001, 0x7880e5c2, 0xd1052800, 0x28007a08, 0x2013d002, 0xe0e57288, 
+    0xfb67f003, 0xd0d82802, 0x8a814845, 0x3b804b3f, 0x4c3f8283, 0x68252180, 0x0352220d, 0x806918ad, 
+    0x82838a81, 0x20006821, 0x80481889, 0x21066830, 0x72813040, 0xf005e59e, 0x2802f81a, 0xf005d0bd, 
+    0x2801f816, 0xf004d0b9, 0x2802f927, 0x6830d0b5, 0x5c092153, 0xd0042900, 0xd12a2901, 0x07497801, 
+    0x7800d527, 0xd4240600, 0xf0002017, 0xf003fa9d, 0x6830fb18, 0x84412105, 0xf0042009, 0x2104f973, 
+    0xf006202b, 0xf003fc70, 0x6831fee7, 0x70083160, 0xfa5ff000, 0x210b6830, 0x72813040, 0xfaa1f000, 
+    0xd08a2800, 0xfae4f004, 0x30406830, 0x28007dc0, 0x6830d0ee, 0x30602300, 0x78417802, 0x78800212, 
+    0x04004311, 0x20034301, 0x91012201, 0x21129000, 0xf0064610, 0x6830fbd2, 0x30402100, 0x75017481, 
+    0x46016830, 0x7aca3140, 0xd0012a28, 0xd1022a29, 0x2a017d0a, 0x7ccad07c, 0xd0042a00, 0xd11d2a01, 
+    0x075b7803, 0xe011d51a, 0x20000090, 0x0000ffff, 0x20000084, 0x0001a300, 0x20000200, 0x0001a100, 
+    0x30000000, 0x0000e0ff, 0x0000bfff, 0x061b7803, 0x2300d404, 0x71833060, 0xe0027203, 0x71843060, 
+    0x2a027204, 0x2003d329, 0x8a820700, 0x43d2220f, 0x4ab78282, 0x68152402, 0x035b230d, 0x862c18ed, 
+    0x4cb48a84, 0x68128284, 0x18d21500, 0x20098610, 0x2200e125, 0x728a2003, 0x8a810700, 0x43c9210f, 
+    0x4dab8281, 0x210d682b, 0x185b0349, 0x8a83861a, 0x82834ba8, 0x18406828, 0xf0048602, 0x2800feef, 
+    0xe4e7d000, 0xf004e05e, 0x2802f8a4, 0x6830d0f9, 0x7bc13080, 0xd01c2900, 0x73c12100, 0x202e2104, 
+    0xfbd1f006, 0xf81cf005, 0xd1ea2800, 0x68014898, 0x0340200d, 0x8e891809, 0xd07d07c9, 0x21886830, 
+    0x07495c09, 0x3040d579, 0x28007cc0, 0xe0ecd076, 0xf004e04c, 0x2802fdec, 0x2104d0d3, 0xf006202c, 
+    0x6830fbb2, 0x79813040, 0xd5050749, 0x28017d80, 0xf004d002, 0xe001fc1a, 0xfc6ff004, 0xd0c02802, 
+    0x21846830, 0x29005c09, 0x3060d152, 0x29027981, 0x2900d002, 0xe009d002, 0xe00c7184, 0x202d2104, 
+    0xfb91f006, 0xfcf9f004, 0xd0aa2802, 0x30606830, 0x28017980, 0x6830d1a7, 0x7a013060, 0xd01c2902, 
+    0xfad7f004, 0x30606830, 0x29017981, 0x7a00d19b, 0xd1982801, 0x30406830, 0x29017d81, 0x7d01d006, 
+    0xb2c91c49, 0x29047501, 0xe729d200, 0x460a6831, 0x7cd03240, 0xd0022800, 0x7204e027, 0x8808e7ea, 
+    0xd5220743, 0x061d790b, 0x0658d505, 0x73d00e40, 0xfbf4f000, 0x0683e019, 0x2b020f9b, 0x7992d015, 
+    0xd5120712, 0xd4100600, 0x7b483180, 0xd40c06c0, 0xf8d4f005, 0xe0022802, 0xe07ce033, 0xd08be071, 
+    0x30806830, 0x28007900, 0x6830d183, 0x5c092195, 0xd00d2900, 0x7ac13040, 0xd009292c, 0x72812116, 
+    0xf94af7ff, 0x30406830, 0x282c7ac0, 0xe431d000, 0x21566830, 0x29015c09, 0xe74fd100, 0x06097801, 
+    0x2100d4fb, 0x71c13060, 0xfd99f004, 0xd0ee2802, 0x30606830, 0x280079c0, 0x6830d0f6, 0x73c43080, 
+    0x2503e731, 0x8aa9072d, 0x82ab4b3b, 0x27004a38, 0x18096811, 0x8aa9840f, 0x681282ab, 0x18102120, 
+    0xf0068401, 0x1c40f896, 0x21014240, 0x040908c0, 0xd3024288, 0xe0011e49, 0xb281e045, 0x82416830, 
+    0x1c497b01, 0x30407301, 0x21027204, 0xf006200e, 0x6830faea, 0x30804601, 0x2a007d42, 0x7e42d00b, 
+    0xd0082a00, 0x22078aaa, 0x82aa43d2, 0x68124a20, 0x18d24b22, 0x73078517, 0x748c3140, 0x72882002, 
+    0xf003e424, 0x2802fa5e, 0x6830d0fa, 0x308022fb, 0x40117a01, 0x201f7201, 0xf81cf004, 0x21156830, 
+    0x72813040, 0x07002003, 0x21808a81, 0x828143c9, 0x2180480f, 0x200d6802, 0x18100340, 0x68318401, 
+    0x318020ff, 0x68307288, 0x74843040, 0xf8e9f000, 0xd0d52800, 0x7a016830, 0xd1e309c9, 0x5c092190, 
+    0xd1df2900, 0x75843040, 0xf81ef7ff, 0x0000e653, 0x20000084, 0x0000fcff, 0x0000ffdf, 0x0001a080, 
+    0xd0162800, 0xd0152801, 0x00402100, 0x1c490840, 0xb2490040, 0xdafa2800, 0x22e00dc0, 0x17ca4010, 
+    0x18520ed2, 0x01520952, 0x221f1a89, 0x18401a51, 0x4770b2c0, 0x477020e0, 0x2403b5f0, 0x8aa10724, 
+    0x82a149fa, 0xdd012800, 0xe0002101, 0x4af82100, 0x4ef80289, 0x68321889, 0x037f270d, 0x811119d2, 
+    0x21002301, 0x4245025b, 0x8aa2e007, 0x82a24af2, 0x19d26832, 0x1c498113, 0x2800b249, 0x4602db01, 
+    0x462ae000, 0xdcf0428a, 0xb5f0bdf0, 0x215348eb, 0x23016800, 0x270d5c09, 0x4ae72403, 0x037f025b, 
+    0x4de40724, 0xd00c2900, 0x5e412126, 0x46084ee4, 0xd00c3011, 0xd017290f, 0x82a28aa0, 0x19c06828, 
+    0x8aa08103, 0x682882a2, 0x810319c0, 0x203ee01b, 0xf7ff43c0, 0x2001ffb1, 0xffaef7ff, 0x20ff8aa0, 
+    0x200182a0, 0xe00b0280, 0x43c0203e, 0xffa4f7ff, 0xf7ff2001, 0x8aa0ffa1, 0x82a020ff, 0x02c02001, 
+    0x19896829, 0x48cd8488, 0x8cc16800, 0x84c11c49, 0xb530bdf0, 0x07002003, 0x4aca8a81, 0x49c58282, 
+    0x680d2400, 0x18ed4bc6, 0x8a84842c, 0x680c8282, 0x18e31c52, 0x8a82841a, 0x43d22280, 0x68098282, 
+    0x220d2080, 0x18890352, 0x48bc8408, 0x680021ff, 0x72813080, 0x48b7bd30, 0x49b96800, 0x8e801840, 
+    0x16800480, 0x47704240, 0x2103b530, 0x8a8a0709, 0x828a138a, 0x06924242, 0x0dd2230d, 0x18d4025b, 
+    0x681d4bac, 0x18ad4aae, 0x8a8c82ec, 0x828c4cad, 0x1c61681b, 0x82d1189a, 0x680949a8, 0x70483160, 
+    0x48a6bd30, 0x30806800, 0x28077a80, 0x2000d001, 0x20014770, 0xb5704770, 0x210048a0, 0x7f226804, 
+    0x429a7da3, 0x1ad0d301, 0x20ffe002, 0x18801ac0, 0x8ce0b2c5, 0xd1012863, 0x03c92101, 0xd3012aff, 
+    0xe0002000, 0xb2c01c50, 0xd1024283, 0x03b62601, 0x429a4331, 0x2201d102, 0x43110352, 0x82a14329, 
+    0xb570bd70, 0xffd7f7ff, 0xf7ff4605, 0x2800ffca, 0x4c8ad063, 0x7d086821, 0xd25e28fb, 0x5e8a2226, 
+    0xd05a2a63, 0x7cce3140, 0x49854882, 0x2e004b86, 0x3210d016, 0x68022a1f, 0x1856d81d, 0x5eb22228, 
+    0x02926800, 0x8d401840, 0x4310b2c0, 0xfed8f7ff, 0x68204602, 0x5a092144, 0x18087f00, 0xe01c541a, 
+    0x18566802, 0x5eb22230, 0x02926800, 0x8e401840, 0x0d800580, 0x1856e007, 0x5eb2222c, 0x02926800, 
+    0x8dc01840, 0x4310b2c0, 0xfebaf7ff, 0x68204601, 0x5a122244, 0x18107f00, 0x68205419, 0xf7ff7705, 
+    0x211fff5a, 0xdc1c42c8, 0x22446820, 0x7f045a12, 0x19122100, 0x7f015499, 0xd30129ff, 0xe0002100, 
+    0x77011c49, 0x5e412126, 0xda07291f, 0xfeddf7ff, 0xf7ff201f, 0xf7ffff49, 0xbd70ff1c, 0x84c12163, 
+    0xf7ffbd70, 0x1e40ff38, 0xe7f2b240, 0xf7ffb5f0, 0x4607ff62, 0xff55f7ff, 0xd06f2800, 0x68304e4f, 
+    0x29fb7d01, 0x2126d26a, 0x29635e41, 0x3040d066, 0x4c487cc0, 0x4b4c4d4a, 0xd00b2800, 0x68203110, 
+    0xd812291f, 0x20281941, 0x68215e08, 0x19490280, 0xe0118d49, 0x19416820, 0x5e082030, 0x02806821, 
+    0x8e491949, 0x0d890589, 0x1941e007, 0x5e08202c, 0x02806821, 0x8dc91949, 0x4308b2c9, 0xfe50f7ff, 
+    0x68304601, 0x5a122244, 0x18107f00, 0x68305419, 0x77072126, 0x291f5e41, 0xf7ffda02, 0xe02bfe86, 
+    0x5a122244, 0x19d22100, 0x7f015499, 0xd30129ff, 0xe0002100, 0x77011c49, 0xfeddf7ff, 0x43ff271e, 
+    0xdd2442b8, 0x30406830, 0x28007cc0, 0x2004d017, 0xfe42f7ff, 0x07002003, 0x21ff8a81, 0x20018281, 
+    0x02406821, 0x84881949, 0x84c76830, 0xfec3f7ff, 0xb2401e40, 0xfec8f7ff, 0xfe9bf7ff, 0x203ebdf0, 
+    0xf7ff43c0, 0x2001fe29, 0xfe26f7ff, 0x6831e7ec, 0x84c82063, 0xb510bdf0, 0xfdfaf005, 0x0c02490f, 
+    0x87086809, 0x848886ca, 0xbd10844a, 0x4a09b510, 0x4b0e6811, 0x8e8918c9, 0x04492400, 0x08487004, 
+    0x18c96811, 0x43088ec9, 0x0000bd10, 0x00008b80, 0x00002001, 0x20000084, 0x0000fdff, 0x20000090, 
+    0x0001a040, 0x00007fff, 0x20000100, 0x0001a180, 0x2003b510, 0x8a810700, 0x310421ff, 0x4aff8281, 
+    0x68142100, 0x18e44bfe, 0x8a848421, 0x68148281, 0x846118e4, 0x82818a84, 0x18e46814, 0x8a8484a1, 
+    0x68108281, 0x84c118c0, 0xb510e7ce, 0xf7ff4604, 0x2103ffdf, 0x8a880709, 0x43c0201f, 0x48ef8288, 
+    0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x828a4aec, 0x140b6804, 0x18a44ae9, 0x8a8b8423, 
+    0x828b23ff, 0x68042301, 0x18a4029b, 0x8a8b84a3, 0x43db2303, 0x6800828b, 0x18802103, 0xe7a384c1, 
+    0x201fb510, 0xffd1f7ff, 0x07002003, 0x21308a81, 0x828143c9, 0x221049d9, 0x240d680b, 0x191b0364, 
+    0x8a82845a, 0x82824ad8, 0x68092001, 0x4ad70280, 0x84481889, 0xb5f8e788, 0x21264ed5, 0x5e416830, 
+    0xb24d120c, 0x311f4629, 0xd204293f, 0xdc022c1f, 0x42cc211f, 0x2201da09, 0x03d2b2e1, 0x82811889, 
+    0x70443080, 0x20017085, 0xf7ffbdf8, 0x6831fe04, 0x76483140, 0xf7ff4628, 0xf7fffe07, 0x6831ffc1, 
+    0x5c402053, 0xd00e2800, 0x27102003, 0x22ff0700, 0x42fc4bba, 0x0067da09, 0x84cf3740, 0x82828a87, 
+    0x02522201, 0x84cce00a, 0x2c0fe00f, 0x0067dd0b, 0x84cf3f3c, 0x82828a87, 0x02d22201, 0x48b0681b, 
+    0x84821818, 0x0060e001, 0x8cc884c8, 0xf7ffb240, 0x4668fd43, 0xff2af7ff, 0xff1df7ff, 0xfda9f7ff, 
+    0x21016830, 0x30808281, 0x70857044, 0xbdf82000, 0x4ca2b5f0, 0x230d6821, 0x18c9035b, 0x4aa48a89, 
+    0x68151209, 0x5d522277, 0x18511809, 0xb2490049, 0x22031049, 0x8a960712, 0x360c4e9a, 0x26018296, 
+    0x03766827, 0x813e18ff, 0x4e97060f, 0x82968a97, 0x6827d505, 0x18ff2600, 0x4249813e, 0x2601e004, 
+    0x02b66827, 0x813e18ff, 0x267f8a96, 0x829643f6, 0x26016827, 0x813e18ff, 0xe00a2600, 0x4c8d8a94, 
+    0x4f868294, 0x683f2401, 0x18ff0264, 0x1c76813c, 0x428eb276, 0x3540dbf2, 0xbdf07428, 0x4d7fb5f0, 
+    0x260d6829, 0x19890376, 0x24038a89, 0x00401808, 0x1040b240, 0x8aa10724, 0x310c497a, 0x210182a1, 
+    0x0389682a, 0x81111992, 0x21000603, 0x4a762b00, 0x82a28aa3, 0x682ada04, 0x81111992, 0xe0044240, 
+    0x682b2201, 0x199b0292, 0x4a71811a, 0x68124f71, 0x7b933240, 0x02522201, 0xd0132b00, 0x217f8aa1, 
+    0x82a143c9, 0x2101682b, 0x8119199b, 0xe0062100, 0x82a78aa3, 0x199b682b, 0x1c49811a, 0x4281b249, 
+    0xbdf0dbf6, 0x4b648aa3, 0x064082a3, 0x0e402301, 0x18c002db, 0x199b682b, 0x8aa08118, 0x682882a7, 
+    0x81021980, 0x485c8aa0, 0x82a0307f, 0x19806828, 0xbdf08101, 0x1040300f, 0xb5104770, 0x07092103, 
+    0x138a8a8a, 0x05c0828a, 0x0dc02211, 0x18830252, 0x68144a4a, 0x1824484a, 0x8a8b82e3, 0x828b4b4f, 
+    0x1c596812, 0x82c11810, 0xb510e66e, 0x07092103, 0x138a8a8a, 0x05c0828a, 0x0dc02209, 0x18830292, 
+    0x68144a3e, 0x1824483e, 0x8a8b82e3, 0x828b4b43, 0x1c596812, 0x82c11810, 0xb510e656, 0x68204c3c, 
+    0x46017dc2, 0x31400753, 0xda142b00, 0xd40d0792, 0x56412181, 0x1048310f, 0xffd7f7ff, 0x20826821, 
+    0x300f5608, 0xf7ff1040, 0xe00dffb8, 0x5608200f, 0xff54f7ff, 0x2019e008, 0xf7ff5608, 0x6821fcd5, 
+    0x56082050, 0xff04f7ff, 0x7dc06820, 0xd50c0700, 0x07002003, 0x21088a81, 0x828143c9, 0x2008491f, 
+    0x4a1f6809, 0x18893240, 0xe61d8008, 0x4606b570, 0xfbfef005, 0x46044d1e, 0x30226828, 0xff2af005, 
+    0x20104601, 0x1a6041c1, 0x682d6030, 0x30364628, 0xff20f005, 0x20104601, 0x481941c1, 0x1a617c6a, 
+    0x2a057c40, 0x0440d004, 0xd2034288, 0xbd702001, 0xe7f901c0, 0xbd702000, 0x480db5f8, 0x8a806800, 
+    0xd42f0400, 0x07362603, 0x4f0e8ab0, 0x4c0382b7, 0x68222120, 0x0340200d, 0xe0151810, 0x20000084, 
+    0x0001a040, 0x00008ff3, 0x0000fbff, 0x0001a180, 0x20000090, 0x0000fdff, 0x0000f780, 0x00007fff, 
+    0x20000200, 0x0000ffdf, 0x46688441, 0xffaef7ff, 0x28012500, 0x8ab0d007, 0x682182b7, 0x0340200d, 
+    0x84451808, 0xf7ffbdf8, 0x48ffff68, 0x68002101, 0x21537441, 0x29005c09, 0x2281d00e, 0x4afb5611, 
+    0x291f3110, 0xd80a6821, 0x23281889, 0x02995ecb, 0x189a6823, 0xe0098d52, 0x83458305, 0x188be00b, 
+    0x5e59212c, 0x02896823, 0x8dd2189a, 0x4311b2d2, 0x83020c0a, 0x49ee8341, 0xbdf88281, 0x4feab5f8, 
+    0x68394dec, 0x31a04eec, 0x4cec7848, 0xd10707c0, 0x48eb8aa8, 0x200182a8, 0x02c06832, 0x81101912, 
+    0x70c82000, 0xfc20f7ff, 0x30a06838, 0x06407840, 0x28060f40, 0x2100d113, 0xf0022001, 0x2100fe0e, 
+    0xf0022002, 0x2100fe0a, 0xf0022003, 0x2100fe06, 0xf0022004, 0x2100fe02, 0xf0022005, 0x6831fdfe, 
+    0x180848d6, 0xf7ff8b84, 0x2c28fd73, 0x2c50d043, 0x2c78d043, 0x2ca0d043, 0x2cc8d043, 0x2cf0d043, 
+    0x2000d043, 0x21838aa9, 0x683282a9, 0x48c70201, 0x84d11812, 0x49cb8aa9, 0x49cb82a9, 0x18126832, 
+    0x8aa98411, 0x82a921ff, 0x68322101, 0x18120289, 0x8aa98491, 0x43c92180, 0x683382a9, 0x49bf2280, 
+    0x841a185b, 0x43d38aab, 0x683382ab, 0x84c21818, 0x201f8aa8, 0x82a843c0, 0x200c6832, 0x85481851, 
+    0x21a16838, 0x22065c09, 0x0f490709, 0x408c1a51, 0x84843080, 0x2001bdf8, 0x2003e7c4, 0x2005e7c2, 
+    0x2007e7c0, 0x2009e7be, 0x200be7bc, 0xb500e7ba, 0x230049a5, 0x43db6809, 0x32a0460a, 0x840b70d0, 
+    0x70932302, 0x31402200, 0xf7ff75ca, 0xf7fffb9d, 0xbd00fb70, 0x2100489c, 0x77016800, 0x82817581, 
+    0x5c0921a1, 0x09ca3080, 0x2a008c81, 0x0049d000, 0x200084c1, 0xb500e7db, 0x23004993, 0x43db6809, 
+    0x32a0460a, 0x840b70d0, 0x70932302, 0x31402200, 0xf7ff75ca, 0xf7fffb79, 0xbd00fb4c, 0x4614b510, 
+    0xd0091a41, 0x1b1a0040, 0xf0054350, 0x1c40fdfe, 0x18201040, 0xe4c7b200, 0x0fc118d0, 0x10401808, 
+    0xb5f1e7f8, 0x21a14f80, 0x26016838, 0x25005c09, 0x0709468c, 0x46310f4a, 0xb24c4091, 0x7d827f01, 
+    0x4291b082, 0x1a8bd301, 0x23ffe002, 0x185b1a9b, 0x8283b29b, 0xd30129ff, 0xe0002700, 0xb2ff1c4f, 
+    0x42ba9700, 0x2701d103, 0x433b03bf, 0x42918283, 0x8a81d104, 0x03522201, 0x82814311, 0x9a02211f, 
+    0x4f6e43c9, 0xd1232a01, 0x8cc03080, 0xd11f2800, 0x09c04660, 0x4660d01c, 0xd00007c0, 0x46082120, 
+    0xfa8af7ff, 0x8a814863, 0x82814968, 0x2201485e, 0x02926800, 0x784130a0, 0x17c907c9, 0x188a0289, 
+    0x6809495d, 0x810a19c9, 0x06497841, 0x70410e49, 0x68014859, 0x18084859, 0x4b538f80, 0x68180ac2, 
+    0x31804601, 0x8cc9728a, 0xd0752900, 0xd1732a07, 0x29fb7d01, 0x4950d270, 0x494c680a, 0x27301851, 
+    0x46025fcf, 0x789132a0, 0xd80f2904, 0x56d32303, 0x2f002006, 0x1a41db03, 0x40884630, 0x1a41e003, 
+    0x40884630, 0x18184240, 0xe04370d0, 0x43db2300, 0xd00b2905, 0xdd112f00, 0x5e412120, 0xdb1f2900, 
+    0x56512103, 0xda17291f, 0xe0131c49, 0x56102003, 0xdb002f00, 0x18c02301, 0xe02870d0, 0xda0f2f00, 
+    0x5e412120, 0xdc152900, 0x56512103, 0x42d9231f, 0x1e49dd02, 0xe01a70d1, 0x75c63040, 0xe016014d, 
+    0x56512103, 0x461a014b, 0x25203220, 0x46395f45, 0xe0054628, 0x56102003, 0x46130142, 0x46383b20, 
+    0xff2cf7ff, 0x48204605, 0x30406800, 0x481e75c6, 0x84076800, 0x6800481c, 0x31a04601, 0x4607788a, 
+    0x708a1c52, 0x7dfa3740, 0xd0062a01, 0x56082003, 0xfa8af7ff, 0xfa5df7ff, 0x88babdfe, 0x18d37f03, 
+    0x54d54a1b, 0x77029a00, 0xd3012aff, 0xe0002300, 0x88bf1c53, 0x18bf042d, 0x0e2d4a15, 0x770355d5, 
+    0x8cc23080, 0xb2931e52, 0x220084c3, 0x9d0270ca, 0x2d014a10, 0x784dd032, 0xd02609ed, 0x42838c80, 
+    0x4804d123, 0xe0178a83, 0x20000090, 0x0001a040, 0x0000ec01, 0x30000000, 0x20000084, 0x0001a000, 
+    0x0000f7ff, 0x00000ff3, 0x0000b00c, 0x0000fbff, 0x20000100, 0x0000fdff, 0x43db237c, 0x48ff8283, 
+    0x68052304, 0x182848fe, 0x250384c3, 0x8aa8072d, 0x82a848fc, 0xdd1d2c00, 0xe01c2001, 0x250d2303, 
+    0x071b2000, 0x2601036d, 0xe0070276, 0x829a8a9c, 0x68244cf2, 0x81261964, 0xb2c01c40, 0x0764784c, 
+    0x24010fa7, 0x428440bc, 0x2003dcf0, 0xf7ff5608, 0xbdfefe92, 0x4bec2000, 0x43180280, 0x681e4be7, 
+    0x037f270d, 0x813019f6, 0x20002201, 0x42660252, 0x8aabe008, 0x82ab4be5, 0x681b4be0, 0x811a19db, 
+    0xb2c01c40, 0xdb012c00, 0xe0004623, 0x42834633, 0x2003dcef, 0xf7ff5608, 0xbdfefe4a, 0x4edcb5f0, 
+    0x68302400, 0x82847584, 0xfb62f7ff, 0x072d2503, 0x20038aa8, 0x4fd182a8, 0x49d16838, 0x84c41840, 
+    0x30a06830, 0x462070c4, 0xf9def7ff, 0x48cd8aa8, 0x683982a8, 0x0340200d, 0x810c1809, 0x49cd8aa9, 
+    0x683982a9, 0x81041808, 0xb500bdf0, 0x200049c8, 0x31a06809, 0xf7ff70c8, 0xbd00f9c7, 0x4cc4b510, 
+    0x68202100, 0x75817701, 0x21028281, 0x708130a0, 0x07c07840, 0x2020d001, 0x201fe001, 0xf7ff43c0, 
+    0x2003f91b, 0x8a810700, 0x828149bb, 0x23016820, 0x30a04602, 0x029b7841, 0x17c907c9, 0x18c90289, 
+    0x681b4bae, 0x0364240d, 0x8119191b, 0x23807841, 0x70414319, 0x0f810748, 0x40c82040, 0x84d03280, 
+    0xf7ff2000, 0xe47ffe08, 0xf7ffb530, 0x4da8f984, 0x31406829, 0x201f7648, 0xf986f7ff, 0x6828211e, 
+    0x84c143c9, 0x7cc03040, 0xd01d2800, 0xf7ff2002, 0x6828f8e3, 0x85042400, 0x75847704, 0xf7ff201f, 
+    0x6828fb04, 0x5c092153, 0xd00b2900, 0x07092103, 0x22ff8a8a, 0x4a91828a, 0x68122101, 0x4b900249, 
+    0x849118d2, 0xbd308284, 0x43c0201f, 0xf8c4f7ff, 0xe7dc2001, 0x4604b510, 0xfacaf7ff, 0x07092103, 
+    0x201f8a88, 0x828843c0, 0x06e24884, 0x0ed26803, 0x0364240d, 0x855a191b, 0x4a888a8a, 0x4b88828a, 
+    0x4a7f6804, 0x842318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 0x84811880, 0xb500e426, 0xf92bf7ff, 
+    0x2259497b, 0x54506809, 0x77082000, 0x201c7588, 0xffd0f7ff, 0xb510bd00, 0xfc2ff7ff, 0xfa98f7ff, 
+    0x07092103, 0x20308a88, 0x828843c0, 0x20004a6b, 0x240d6813, 0x191b0364, 0x8a8b8458, 0x828b4b6e, 
+    0x4a706811, 0x84481889, 0x68094969, 0x758875c8, 0xe4118288, 0x2300b510, 0xd01c2800, 0x22004c6a, 
+    0xd90042a0, 0x1c524620, 0xb2520040, 0xdafa2800, 0x0ee417d4, 0x096418a4, 0x1b120164, 0x1aa2241f, 
+    0x700ab2d2, 0xd2092a08, 0x06000e00, 0x40d01aa2, 0x700bb2c0, 0x700be429, 0xe4262000, 0x1fd20e00, 
+    0xe422700a, 0x2403b5f0, 0x8aa10724, 0x82a1494d, 0xdd012800, 0xe0002101, 0x4a542100, 0x4e470289, 
+    0x68321889, 0x037f270d, 0x811119d2, 0x21002301, 0x4245025b, 0x8aa2e007, 0x82a24a44, 0x19d26832, 
+    0x1c498113, 0x2800b249, 0x4602db01, 0x462ae000, 0xdcf0428a, 0xb5f0bdf0, 0x2200270e, 0x4e444d37, 
+    0x4c3b43ff, 0x2900230f, 0x2800d016, 0x4610d009, 0x6829e009, 0x88891989, 0x16890689, 0x84c11a79, 
+    0x461fbdf0, 0xf7ff4618, 0x6820fb90, 0x09097dc1, 0x078943c9, 0xbdf0d1ed, 0xd0012800, 0xe0014610, 
+    0x4618461f, 0xfb69f7ff, 0x19806828, 0x68218840, 0x16800680, 0x84c81a38, 0x0040bdf0, 0xb240380f, 
+    0xb5304770, 0x20004c22, 0x4a1c6821, 0x68108508, 0x18c04b27, 0x06808880, 0xf7ff1680, 0x6821ffee, 
+    0x70483180, 0x18c06810, 0x06808840, 0xf7ff1680, 0x6821ffe4, 0x460b2201, 0x70983380, 0x2a00569a, 
+    0x4615db01, 0x4255e000, 0xdb012800, 0xe0004603, 0x429d4243, 0x8d0bdd03, 0x432b2504, 0x2a00850b, 
+    0x8d0add03, 0x431a2302, 0x2800850a, 0x8d08dd03, 0x43102201, 0x7dca8508, 0xe01b0690, 0x20000084, 
+    0x0001a040, 0x00008b80, 0x00007001, 0x0000fdff, 0x20000090, 0x0000f7ff, 0x0000fbff, 0x00000ff3, 
+    0x0000b00c, 0x0001a180, 0x007fffff, 0x00004001, 0x0001a280, 0xd0130f80, 0xd0202801, 0xd0212802, 
+    0xd10c2803, 0x21018d08, 0x0fc00780, 0xff63f7ff, 0x8d006820, 0x0fc007c0, 0xf7ff2100, 0xbd30ff5c, 
+    0x5e082028, 0xdb012804, 0xe0002101, 0x28042100, 0x0780db02, 0xe7f00fc0, 0x0fc007c0, 0x07d0e7ed, 
+    0xe7e90fc0, 0x0fc007d0, 0xe7e62101, 0xf7feb5f8, 0x4cfefff2, 0x68212259, 0x54502700, 0x7dc8828f, 
+    0x07034dfd, 0x4afb48fa, 0x8aab4efc, 0xd50382a8, 0x18806830, 0xe0038007, 0x20086833, 0x8010189a, 
+    0x07407dc8, 0x00030f40, 0xfb3cf005, 0x1b0e0508, 0x5e43432f, 0x201f4566, 0xffd6f7fe, 0x20506821, 
+    0xf7ff5608, 0xe018fa05, 0x43c0201e, 0xffccf7fe, 0x20506821, 0xf7ff5608, 0xe021f9fb, 0x84c86821, 
+    0x2000e029, 0xffc0f7fe, 0x30406820, 0x28007cc0, 0x2001d005, 0xf7fe43c0, 0x201fff1f, 0x2020e7ee, 
+    0xff1af7fe, 0x43c02000, 0x2000e7f5, 0xffacf7fe, 0x30406820, 0x28007cc0, 0x2002d005, 0xff0cf7fe, 
+    0x43c0201e, 0x201fe7da, 0xf7fe43c0, 0x2001ff05, 0xf7ffe7f4, 0x6820ff16, 0x07407dc0, 0xf7ffd42b, 
+    0x6820f94f, 0x5c092153, 0xd0222900, 0x07817dc0, 0x49c8d51f, 0x20ff07c2, 0x2a003940, 0x82a88aaa, 
+    0x2001d012, 0xe0110240, 0xf7ff2020, 0x2000fe9b, 0xf7ff43c0, 0xe7c0fe97, 0x43c0201f, 0xfe92f7ff, 
+    0xf7ff2001, 0xe7cbfe8f, 0x02c02001, 0x18516832, 0xf7fe8488, 0xf7ffff3e, 0x6820f8ae, 0xf7ff305e, 
+    0x6820f8b5, 0x77077587, 0x87878747, 0xb510bdf8, 0xfe9ef004, 0x680949ad, 0x0c008488, 0xe5c28448, 
+    0x4606b57c, 0x46696808, 0xf7ff08c0, 0x4da7fe43, 0x68292244, 0x5a524caa, 0x18d27f0b, 0x7f0854a0, 
+    0xd30128ff, 0xe00020ff, 0x77081c40, 0x6830a901, 0xfe30f7ff, 0x78094669, 0x4669010a, 0x430a7909, 
+    0x460b6829, 0x889d3340, 0x19ad7f0e, 0x7f0a5562, 0xd3012aff, 0xe00022ff, 0xb2d21c52, 0x889b770a, 
+    0x54a0189a, 0x28ff7f08, 0x20ffd301, 0x1c40e000, 0xbd7c7708, 0x4a8db570, 0x6814230e, 0x84e32500, 
+    0x4c904b8e, 0xd02b2900, 0x68182800, 0x1900d011, 0x06808880, 0xf7ff1680, 0x6811fe80, 0x578e2681, 
+    0xda1a42b0, 0x19006818, 0x06808880, 0x1c401680, 0x1900e010, 0x06808880, 0xf7ff1680, 0x6811fe6e, 
+    0x578e2681, 0xdd0842b0, 0x19006818, 0x06808880, 0x1e401680, 0xf9d9f7ff, 0x6810bd70, 0xbd7084c5, 
+    0x68182800, 0x1900d011, 0x06808840, 0xf7ff1680, 0x6811fe54, 0x578e2682, 0xdaee42b0, 0x19006818, 
+    0x06808840, 0x1c401680, 0x1900e010, 0x06808840, 0xf7ff1680, 0x6811fe42, 0x578e2682, 0xdddc42b0, 
+    0x19006818, 0x06808840, 0x1e401680, 0xf995f7ff, 0xb5f0bd70, 0x2000b085, 0x4f5c4669, 0x68387208, 
+    0x04098a81, 0x4d5cd47e, 0x21208aa9, 0x82a943c9, 0x21204c5a, 0x260d6822, 0x19920376, 0x21538451, 
+    0x29005c09, 0x2126d012, 0x31105e41, 0xd902291f, 0x07807dc0, 0x6820d40e, 0x3940494e, 0x20281842, 
+    0x68225e10, 0x18510280, 0xe00d8d49, 0xf7fea802, 0xe00bffdd, 0x49476820, 0x18423940, 0x5e10202c, 
+    0x02806822, 0x8dc91851, 0x4308b2c9, 0xa8019000, 0xf9bcf7ff, 0x483d9003, 0x46386807, 0xf005303a, 
+    0x2110f8e9, 0x990041c8, 0x42881840, 0x2000d201, 0x990343c0, 0x29019000, 0x8cf9d021, 0xd01e2900, 
+    0x7c894939, 0x42810109, 0x2227d276, 0x02129901, 0xd8054291, 0x42914a35, 0x7df9d96e, 0xd56b0649, 
+    0x4668a901, 0xfefcf7ff, 0x68114a28, 0x07d87dcb, 0x5e08482f, 0x2800d020, 0x1c40da1c, 0xa901e01f, 
+    0xf7ff4668, 0x4668feed, 0x28007a00, 0x2000d010, 0x03802101, 0x184103c9, 0x03409803, 0x481b4301, 
+    0xe0006800, 0x7f02e002, 0x82814311, 0xbdf0b005, 0xe7ed2001, 0xe0022000, 0xddfb2800, 0x84c81e40, 
+    0xd5590798, 0x5c472053, 0x4a1a2001, 0x2f000240, 0x075fd001, 0x8aa9d505, 0x682182aa, 0x81081989, 
+    0x07dbe07f, 0x2b0027ff, 0x2326d02c, 0x33105ecb, 0x203ed12b, 0xf7fe43c0, 0x2001fd6f, 0xfd6cf7fe, 
+    0x82af8aa8, 0x02892101, 0xe0166822, 0x20000090, 0x0000fff7, 0x0001a080, 0x30000000, 0x20000084, 
+    0x20000100, 0x0001a280, 0x20000200, 0x000007cc, 0x00000026, 0x0000fdff, 0x48fee070, 0x18103840, 
+    0xe04e8481, 0x290f8cc9, 0x8aa9d005, 0x682182aa, 0x81081989, 0x203fe7bf, 0xfd3ef7fe, 0x43c02000, 
+    0xfd3af7fe, 0x82af8aa8, 0x68222001, 0x49f10280, 0x18513940, 0xe0348488, 0x07584fef, 0x0698d52d, 
+    0xd0060f80, 0xd0152801, 0xd0162802, 0xd1282803, 0x2028e017, 0x28045e08, 0x2101db01, 0x2100e000, 
+    0xdb022803, 0x0fc00780, 0x07c0e001, 0xf7ff0fc0, 0xe016fe91, 0x0fc007d8, 0x07d8e00d, 0x21010fc0, 
+    0x8d08e7f5, 0x07802101, 0xf7ff0fc0, 0x6838fe83, 0x07c08d00, 0x21000fc0, 0x8cc8e7e9, 0xf7feb240, 
+    0xf7fffd93, 0x48d4fe34, 0x68002700, 0x87878747, 0xfd5ff7fe, 0xf7fea802, 0x9000fed9, 0x20208aa8, 
+    0x82a843c0, 0x19806820, 0x48cb8447, 0x8cc16800, 0x06497f02, 0x430a0c49, 0xe7478282, 0x87790c01, 
+    0xf7fe87b8, 0x8aa8fd46, 0x43c02020, 0x682182a8, 0x19892000, 0xe7e88448, 0x2003b5f0, 0x8a810700, 
+    0x828149be, 0x220049be, 0x230d680c, 0x18e4035b, 0x8a848062, 0x82862601, 0x680d2469, 0x18ed0124, 
+    0x8a8480ac, 0x82841e94, 0x18e4680c, 0x8a8480e2, 0x82844cb4, 0x18e4680c, 0x8a848122, 0x82844cb2, 
+    0x18e4680c, 0x8a848422, 0x82854db0, 0x18e4680c, 0x8a848462, 0x82844cae, 0x10dc680f, 0x853c18ff, 
+    0x241f8a84, 0x828443e4, 0x240d680f, 0x857c18ff, 0x4ca88a84, 0x680c8284, 0x861e18e3, 0x4ba68a83, 
+    0x680c8283, 0x3b404b9b, 0x802218e4, 0x4ea38a84, 0x680c8286, 0x806218e4, 0x82868a84, 0x18e4680c, 
+    0x8a8480a2, 0x82841cb4, 0x18f6680e, 0x8a8680f2, 0x680e8284, 0x813218f6, 0x82848a86, 0x18e4680c, 
+    0x8a848162, 0x82844c96, 0x18e4680c, 0x8a8481a2, 0x43e424c0, 0x680e8284, 0x18f62440, 0x8a8481f4, 
+    0x03a42401, 0x680c8284, 0x82e218e4, 0x24ff8a84, 0x82843404, 0x18e4680c, 0x8a848422, 0x680c8282, 
+    0x846218e4, 0x82828a84, 0x18e4680c, 0x8a8484a2, 0x680c8282, 0x84da18e3, 0x23198a83, 0x828343db, 
+    0x2310680e, 0x19364c73, 0x8a838033, 0x33294b77, 0x680f8283, 0x193f2604, 0x8a86843e, 0x680e8283, 
+    0x85221934, 0x82828a84, 0x4c6a680e, 0x19363440, 0x8a868032, 0x680e8282, 0x80721936, 0x82838a86, 
+    0x191b680b, 0x8a83809a, 0x680b8285, 0x34804c61, 0x84da191b, 0x4b678a83, 0x82833bf1, 0x49696808, 
+    0x84421840, 0x2103bdf0, 0x8a8a0709, 0x828a2200, 0x0200495b, 0x220d6809, 0x18890352, 0x83483080, 
+    0x22034770, 0x8a930712, 0x8293233f, 0x01000709, 0x43080f09, 0x21800200, 0x43083040, 0x68094950, 
+    0x0352220d, 0x83481889, 0xb5104770, 0x46112200, 0xe0074c55, 0xd00207c3, 0x5ae3004b, 0x1c49405a, 
+    0x0840b289, 0xd1f52800, 0xe5184610, 0x4844b5f0, 0x68004d46, 0x210d3530, 0x18400349, 0x27008b86, 
+    0xe009463c, 0x0a295d38, 0xf7ff4048, 0x0229ffde, 0x1c644048, 0xb2a4b285, 0xd3f342b4, 0xbdf04628, 
+    0x4e37b5fe, 0x270d6831, 0x19c9037f, 0x4a328b49, 0x68140a09, 0x46222500, 0x92013280, 0x00034a3b, 
+    0x00d27d52, 0x46229200, 0x920232a0, 0xf0043a60, 0x0e19ff99, 0x72181819, 0xf6f7f89a, 0xf2f3f4f5, 
+    0xeff018f1, 0xebecedee, 0xe918ea18, 0x20030018, 0x8a810700, 0x43c921c0, 0x68318281, 0x19c92080, 
+    0xbdfe8348, 0xd0052900, 0xd00c2901, 0xd0142902, 0xe2652101, 0x28007c90, 0x2001d0f3, 0x98017460, 
+    0x7c802101, 0x9801e024, 0x7c804c13, 0xf0042101, 0x6821fc48, 0x74482001, 0x7a50e24e, 0x43082101, 
+    0x74657250, 0xfb60f7fd, 0x19c06830, 0x07c08e80, 0x2003d009, 0x8a810700, 0x43c92120, 0x68318281, 
+    0x19c92020, 0x48048408, 0x30806800, 0x21007c80, 0x0000e01e, 0x0001a080, 0x20000090, 0x0000f87f, 
+    0x20000084, 0x00008180, 0x0000bf1f, 0x0000ffcf, 0x000083ff, 0x0000fcf0, 0x00003fff, 0x000013fd, 
+    0x0000c0c0, 0x0001a180, 0x00007bac, 0x20000200, 0xfc07f004, 0x2900e210, 0x2901d006, 0x2902d00b, 
+    0x2903d013, 0xe017d1b8, 0x07002003, 0x82858a81, 0xfb05f004, 0x2003e005, 0x8a810700, 0xf0048285, 
+    0x6831fafa, 0x838819c9, 0x2003e1f6, 0x8a810700, 0x98018285, 0xe7f47c80, 0x07002003, 0x82858a81, 
+    0xfb17f004, 0x1e89e7ed, 0xf004000b, 0x2405fefb, 0x056d5b31, 0xe7740004, 0x29027c61, 0x7cd3d26a, 
+    0xd86f2b01, 0x2b007c93, 0x2900d101, 0x7611d0f3, 0x19c06830, 0x84e08b80, 0xfd5df7fe, 0xd0010001, 
+    0xe0602006, 0x210548fe, 0x74416800, 0x07092103, 0x828d8a8a, 0x7c90e117, 0xd1022800, 0x28007c60, 
+    0x7c60d0d9, 0x20017610, 0xf7ff7460, 0xe1b3fa36, 0x21017a50, 0x72504308, 0x4ef17c60, 0xd30a2802, 
+    0x4cf148f0, 0x20ff6005, 0x81208160, 0x48ef1c41, 0xfdccf004, 0xf7ff7565, 0x6830fa2e, 0x5c092158, 
+    0xe1997441, 0xe12fe163, 0xe0eee127, 0xe0f2e107, 0xe069e0b3, 0xe053e05f, 0xe044e04a, 0xe03ae03e, 
+    0xe031e034, 0x28027c60, 0x7cd1d211, 0xd8192901, 0x29007c91, 0x2800d101, 0x49dbd09d, 0x75482001, 
+    0x76107c60, 0xe0192002, 0x28027c60, 0x9900d303, 0xb2c94301, 0x7cd1e099, 0xd8032901, 0x29007c91, 
+    0xe003d106, 0xf7ffe09e, 0xbdfefe8c, 0xd0fc2800, 0x210148cd, 0x7c607541, 0x20037610, 0xf7ff7460, 
+    0xf7fef983, 0xe157fae6, 0xe01f5c60, 0x19c06830, 0x54608b80, 0x48c4e150, 0xe0175c40, 0x19c06830, 
+    0x4ac18b80, 0x1860e01e, 0x02027840, 0xe00c5c60, 0x19c06830, 0x54608b80, 0x18610a00, 0xe13b7048, 
+    0x184248b9, 0x5c407852, 0x43100212, 0x07092103, 0x828d8a8a, 0x6830e735, 0x8b8019c0, 0x0a034ab2, 
+    0x70631854, 0xe1275450, 0x28027c60, 0x2900d242, 0x2901d00f, 0x2902d021, 0x48abd1b7, 0x754549a9, 
+    0x21ff600d, 0x81018141, 0x48a81c49, 0xfd3ef004, 0x2300e02c, 0x461a9500, 0x20022111, 0xf0049501, 
+    0x49a1fc2c, 0x75482001, 0x81088948, 0xd00228ff, 0x81081c40, 0x2000e100, 0x4a9be7fb, 0x8911489b, 
+    0x5c408953, 0xd1034299, 0x310121ff, 0xe0034308, 0xd00d29ff, 0x81111c49, 0x07092103, 0x828d8a8a, 
+    0xb2c16832, 0x839119d2, 0xd0570a00, 0xe0712001, 0xe7f02100, 0x20052100, 0x7c60e775, 0x28024684, 
+    0x9800d305, 0x43084661, 0x200cb2c1, 0x0748e76b, 0x6833d505, 0x181b4886, 0x07db8e5b, 0x7cd0d005, 
+    0xd9092801, 0x200d2102, 0x6831e75d, 0x8e401808, 0x0fc907c1, 0xe7562008, 0x28007c90, 0x4660d103, 
+    0xd1002800, 0x4b78e751, 0x75582001, 0x76107c60, 0x74602004, 0xf7ff75e1, 0x2003fa69, 0x8a810700, 
+    0x486f8285, 0x8cc06800, 0x7a50e6ab, 0x43082101, 0x72504e6b, 0x8890e6f4, 0x18417da1, 0x5c40486b, 
+    0x07092103, 0x828d8a8a, 0x19c96831, 0x7da08388, 0xd30128ff, 0xe0002000, 0x75a01c40, 0x8891e08c, 
+    0x4a627da0, 0x5cd3180b, 0xd30128ff, 0xe0002000, 0xb2c01c40, 0x180975a0, 0x28ff5c51, 0x2000d301, 
+    0x1c40e000, 0x200375a0, 0x8a820700, 0x02188285, 0xe6764308, 0xfd87f7ff, 0x2003bdfe, 0x8a810700, 
+    0xf7ff8285, 0xe66cfdb3, 0x4e4d9802, 0x06487041, 0x28010f40, 0x2802d017, 0x2805d003, 0x2806d035, 
+    0x7c60d1ea, 0xd3002802, 0x7c91e6e1, 0xd1012900, 0xd0e12800, 0x20014944, 0x7c617548, 0x74607611, 
+    0xfdccf7fe, 0x7c60e048, 0xd0472800, 0x74602006, 0xfe60f7fe, 0x82a5e040, 0xf800f7ff, 0x46016830, 
+    0x7e0a3140, 0x30a07442, 0x760d7045, 0x6830e034, 0x8b4019c0, 0x0a009902, 0x4e317048, 0x0f400640, 
+    0x2801d012, 0x2802d021, 0x7c60d1b6, 0xd3e22802, 0x4f2d482c, 0x20ff6005, 0x81388178, 0x482b1c41, 
+    0xfc44f004, 0xe7d6757d, 0x28027c60, 0x7c91d2bc, 0xd1012900, 0xd09f2800, 0x20014923, 0x7c617548, 
+    0x74607611, 0xfff1f7fe, 0x7c60e006, 0xd0052800, 0x74602007, 0xfff2f7fe, 0xe78b2000, 0xb2c19800, 
+    0xe6902001, 0xf001b570, 0x4915fa2c, 0x68092000, 0x460b8608, 0x33808648, 0x460c7298, 0x344072d8, 
+    0x7a627220, 0x00520852, 0x72a07262, 0x732072e0, 0x4a0d73d8, 0x7f9273a0, 0x460a73e2, 0x32607420, 
+    0x711875d0, 0x87087158, 0x752086c8, 0x711075a0, 0x72587150, 0x854877e0, 0x71d07190, 0xe0097210, 
+    0x20000090, 0x20000088, 0x20000200, 0x20000100, 0x0001a180, 0x85c88588, 0x75107250, 0x755074d0, 
+    0x76507590, 0x76d07690, 0x75987710, 0x25017618, 0x806075dd, 0x76987658, 0x824876d8, 0x73887348, 
+    0x740873c8, 0x77907750, 0x701877d0, 0x71987610, 0x74188688, 0x75888288, 0x830875c8, 0xbd708348, 
+    0xf7ffb510, 0xf7fffbe9, 0x48f9ff9d, 0x79806800, 0xd10b07c0, 0x07002003, 0x210f8a81, 0x828143c9, 
+    0x200049f4, 0x4af46809, 0x80481889, 0x20012100, 0xfb33f001, 0x20022100, 0xfb2ff001, 0x20032100, 
+    0xfb2bf001, 0x20042100, 0xfb27f001, 0x20052100, 0xfb23f001, 0x48e7e4b9, 0x49e76800, 0x184031c0, 
+    0x49e68a80, 0x0f020600, 0x1ed27c08, 0xd3022a0b, 0x43102210, 0x22efe001, 0x74084010, 0xb5104770, 
+    0x07002003, 0x49de8a81, 0x49da8281, 0x680c2301, 0x4ad902db, 0x18a43280, 0x8a838523, 0x43db2340, 
+    0x680c8283, 0x18a42340, 0x4bd48423, 0x2b007bdb, 0x8a83d122, 0x82834bd3, 0x680c2301, 0x18a2035b, 
+    0x8a8284d3, 0x43d22278, 0x680c8282, 0x4aca2308, 0x18a432c0, 0x8a838023, 0x82834bcb, 0x680c2337, 
+    0x18a4019b, 0x8a8380e3, 0x33204bc6, 0x20198283, 0x01c06809, 0x81c81889, 0x4770e467, 0xf004b570, 
+    0x4abef81e, 0x290088d1, 0x08cbd014, 0x18081ac0, 0x7b1080d0, 0x28142101, 0x4bbcd20e, 0x43434dbc, 
+    0x129b195b, 0x1c5b88d4, 0x429c105b, 0x74d1dc04, 0xe00f1c40, 0xe7eb00c0, 0xd00d2800, 0x4db54bb3, 
+    0x195b4343, 0x88d4129b, 0x105b1c5b, 0xdb03429c, 0x1e4074d1, 0xbd707310, 0x74d02000, 0xb570bd70, 
+    0x48a62124, 0xfb12f004, 0x20264ca4, 0x48aa8020, 0x200980a0, 0x200b73a0, 0x73202600, 0x752674e6, 
+    0xf0037566, 0x00c0ffdc, 0x250080e0, 0xffb6f7ff, 0xb2ed1c6d, 0xd3f92d08, 0x68004896, 0x31c04996, 
+    0x8fc01840, 0x07002128, 0x73e00f00, 0x20017426, 0x75a17360, 0x75e12104, 0x76212110, 0x76a07666, 
+    0x76e02002, 0x77202003, 0x77602024, 0x77a02020, 0x77e62005, 0x842001c0, 0x0180200b, 0x21f88460, 
+    0xf004488e, 0x488efad3, 0x20ff6006, 0x81208160, 0x488a1c41, 0xfacaf004, 0xb510bd70, 0x2100487c, 
+    0x230a6800, 0x80014602, 0x71933240, 0x72c171d1, 0x73017281, 0x73817341, 0x73c17401, 0x74418241, 
+    0x71017491, 0x71c17181, 0x72417201, 0x22027741, 0x22017142, 0x30807082, 0xf7ff7201, 0xe709fe83, 
+    0x486eb530, 0x28007bc0, 0x4a6ad123, 0x4b6a6810, 0x18c033c0, 0x210f8a80, 0x0f000600, 0x20031a09, 
+    0x8a840700, 0x82844c6f, 0x6815028c, 0x18ed430c, 0x8a8484ac, 0x43e4240f, 0x68148284, 0x859918e3, 
+    0x212a8a81, 0x828143c9, 0x202a6811, 0x18894a66, 0xbd308188, 0x4d57b5f8, 0x48636829, 0x180830c0, 
+    0x4f538ac0, 0x68380701, 0x30400f09, 0x7a4174c1, 0x401122fd, 0x48517241, 0x7bc04e4f, 0x36802403, 
+    0x28000724, 0x6828d12e, 0x33c04b4b, 0x8a8018c0, 0x0600210f, 0x1a080f00, 0x49548aa1, 0x682a82a1, 
+    0x19920301, 0x8aa18511, 0x43c9210f, 0x682982a1, 0x85481989, 0x21038aa1, 0x82a143c9, 0x2103682a, 
+    0x86111992, 0x21788aa1, 0x82a143c9, 0x00c06829, 0x800818c9, 0x20028aa0, 0x82a043c0, 0x20026829, 
+    0x824818c9, 0xff20f7fc, 0x4b416838, 0x4a327801, 0x2100074f, 0xdb092f00, 0x5c3f2753, 0xd10b2f00, 
+    0x783f4f2e, 0x0eff06bf, 0xd3052f06, 0x82a38aa7, 0x189b682b, 0xe0058019, 0x82a38aa7, 0x2304682f, 
+    0x803b18bf, 0x075b7803, 0x2353d412, 0x2b005c1b, 0x4b22d10e, 0x069b781b, 0x2b0e0edb, 0x8aa3d908, 
+    0x43db2380, 0x682f82a3, 0x18ba2380, 0xe0068013, 0x23808aa3, 0x82a343db, 0x189a682b, 0x78028011, 
+    0xd5470752, 0x32404602, 0x2b007cd3, 0x4b13d142, 0x069b781b, 0x469c0edb, 0xd90d2b1a, 0x23078aa3, 
+    0x82a343db, 0x2306682f, 0x84bb19bf, 0x075b7803, 0x7cd2d530, 0xd12d2a00, 0x2a164662, 0x8aa2d92a, 
+    0x43d22202, 0x682b82a2, 0x199b2202, 0xe028859a, 0x20000090, 0x20000084, 0x0001a080, 0x20000200, 
+    0x0000f7ff, 0x0000dfff, 0x0000c03f, 0xfffc5699, 0x00d3f7e6, 0x00da605a, 0x0000d102, 0x20000100, 
+    0x20000088, 0x0000c3f0, 0x0001a240, 0x00000fff, 0x0000fffb, 0x22028aa2, 0x82a243d2, 0x1992682a, 
+    0x78028591, 0x4afc0753, 0x82a28aa3, 0x2201d505, 0x02d2682b, 0x855a199b, 0x682ae002, 0x85511992, 
+    0x32ff682a, 0x8d923201, 0x07924ef4, 0x46020fd3, 0x75533280, 0x4ff22b00, 0x82a68aa3, 0x231bd002, 
+    0xe001015b, 0x015b2311, 0x19f6682e, 0x7d528033, 0xd0092a00, 0x4aeb8aa2, 0x230782a2, 0x02db682e, 
+    0x3a404ae7, 0x815318b2, 0x4ae78aa2, 0x682f82a2, 0x260d2301, 0x19bf0376, 0x3040807b, 0x48df7cc7, 
+    0x30e01ebf, 0xf004003b, 0x0508fa4d, 0x0a0a0505, 0x120a0505, 0x82a08aa3, 0x300120ff, 0x8aa3e003, 
+    0x200182a0, 0x682b0240, 0x80d8199b, 0x8aa3e004, 0x682882a0, 0x80c11980, 0x48d4682b, 0x8ec01818, 
+    0x0f000700, 0xd00e2801, 0x8aa02804, 0x82a048d0, 0x48d0682b, 0x181bd010, 0x8aa38019, 0x682a82a2, 
+    0x80411810, 0x8aa0bdf8, 0x82a048c9, 0x2380682e, 0x183648c8, 0xe7f08033, 0x8019181b, 0x82a28aa1, 
+    0xe7ec2101, 0x201fb5f8, 0xfd80f001, 0xfb04f001, 0x26034dc1, 0x31606829, 0x07367008, 0x20098ab0, 
+    0x82b043c0, 0x210848bd, 0x4cba6800, 0x19003cc0, 0x20008001, 0xfe98f7fd, 0x22006828, 0x31404601, 
+    0x4db77ccf, 0xf004003b, 0x0d09f9ed, 0x3406340b, 0x06340634, 0x232a0034, 0x231573cb, 0xe00d740b, 
+    0xe00a73ca, 0x061f7903, 0x065bd502, 0xe0030e5b, 0x075b7803, 0x7f6bd51d, 0x740a73cb, 0x75c23060, 
+    0x4fa5200f, 0xf7fe5608, 0x6839f8e9, 0x56082050, 0xf89ef7fe, 0x78006838, 0xd5170740, 0xfdecf001, 
+    0x78016838, 0xd5110749, 0x7cc03040, 0xd0022801, 0x7fabe00c, 0x8ab0e7e0, 0x43c02030, 0x489782b0, 
+    0x68002130, 0x3a404a93, 0x84c11880, 0x20208ab0, 0x82b043c0, 0x20204991, 0x230d680a, 0x18d2035b, 
+    0x68388410, 0x46032201, 0x739a3340, 0x469c7fef, 0x063b4a8c, 0x8ab0d507, 0x067882b2, 0x0e406809, 
+    0x80481909, 0x8807bdf8, 0xd4fb063b, 0x07db7983, 0x077fd1f8, 0x2f002307, 0x2795da0f, 0x2f005c3f, 
+    0x782fd00b, 0x0eff06bf, 0xd9062f16, 0x82b28ab3, 0x220a680b, 0x805a191b, 0x8ab7e004, 0x680a82b2, 
+    0x80531912, 0x7cd24662, 0xd1db2a01, 0x06807800, 0x28020f80, 0x7828d0d6, 0x0ec00680, 0xd9d12816, 
+    0x20078ab0, 0x82b043c0, 0x20046809, 0x80881909, 0xb510bdf8, 0x68204c68, 0x78003060, 0xfcc6f001, 
+    0x20616821, 0xf7fd5608, 0x6821fdef, 0x31402000, 0x200f7388, 0xf7fe5608, 0x6821f861, 0x56082050, 
+    0xf816f7fe, 0x07002003, 0x21208a81, 0x828143c9, 0x2020495a, 0x220d6809, 0x18890352, 0x68208408, 
+    0x30402101, 0xe4a57381, 0x4d54b570, 0x4e566828, 0x8ec11980, 0x19806828, 0x048a8f00, 0x0f52054b, 
+    0x18d20f5b, 0x08520689, 0x18510e89, 0x0f530482, 0x0ed206c2, 0x0984189b, 0xd00007e4, 0x0544425b, 
+    0x18a20f64, 0x07c00940, 0x4252d000, 0x10431898, 0x19806828, 0x06808f40, 0x68281684, 0x8f401980, 
+    0x16c20540, 0x19856828, 0x5e28203a, 0x290012c0, 0x4249da00, 0xda002b00, 0x18c9425b, 0xda002c00, 
+    0x19094264, 0xda002a00, 0x18894252, 0xda002800, 0x18084240, 0xbd70b280, 0x4d30b5f0, 0x4a326828, 
+    0x8ec11880, 0x18806828, 0x682b8f00, 0x8f5b189b, 0x12db055b, 0x682b0c1c, 0x223a189b, 0x048b5e9a, 
+    0x0f5b054e, 0x199b0f76, 0x085b0689, 0x185e0e89, 0x06c30481, 0x0f490152, 0x0c120edb, 0x098718c9, 
+    0xd00007ff, 0x05474249, 0x18fb0f7f, 0x07c00940, 0x425bd000, 0x682918c8, 0x481b1043, 0x8f401808, 
+    0x16810680, 0x185d0048, 0x19404684, 0x4c120065, 0x68241940, 0x88241880, 0x06a7b200, 0x2f020fbf, 
+    0x0764d109, 0x0058d507, 0x18411980, 0x18084660, 0x18801940, 0xbdf0b200, 0x0000f7ff, 0x0000fc1f, 
+    0x0001a180, 0x0000c7ff, 0x0000fffe, 0x0001a300, 0xffffff7f, 0x0001a140, 0x20000090, 0x20000084, 
+    0x20000200, 0x0000fff0, 0x0001a040, 0xf7ffb500, 0x0081ff4b, 0x18080040, 0xbd00b280, 0x2200b500, 
+    0xfd09f7fd, 0xda012800, 0x22014240, 0x68094915, 0x18c94b15, 0x08c98809, 0x0fc907c9, 0x0040d002, 
+    0xe0024912, 0x00404911, 0x5e083940, 0xd0012a00, 0xb2004240, 0xb510bd00, 0x07092103, 0x138a8a8a, 
+    0x4a08828a, 0x68140680, 0x48070dc3, 0x18243840, 0x8a8b82e3, 0x828b4b06, 0x1c596812, 0x82c11810, 
+    0x0000e40a, 0x20000084, 0x0001a080, 0x00007bfc, 0x00007fff, 0x49fdb570, 0x680a2500, 0x31404611, 
+    0x33604613, 0x774d75cd, 0x83d5731d, 0x8415461c, 0xd0092800, 0x43e4240f, 0xd0082801, 0x28022300, 
+    0x2803d01a, 0xe005d017, 0x77e5230f, 0x3280e002, 0x70154623, 0x570c2410, 0xd00d2802, 0xd00b2803, 
+    0x76cd764b, 0x76887e48, 0xf7fd4618, 0x4620fcad, 0xfedef7fd, 0x240fbd70, 0xe7f2764c, 0x4ce3b570, 
+    0x68212500, 0x3240460a, 0x3360460b, 0x280075d5, 0x2801d007, 0x76d5d00c, 0xd01d2802, 0xd0222803, 
+    0x7bc8e00f, 0x76d608c6, 0x02007fdb, 0xe00718c0, 0x08c37c08, 0x76d3425b, 0x20800203, 0x18185c40, 
+    0x76958488, 0x5610201b, 0xfc7ef7fd, 0x205a6821, 0xf7fd5608, 0xbd70fead, 0x08c57b48, 0x7695426d, 
+    0x7f5b0200, 0x7b88e004, 0x769508c5, 0x02007f9b, 0x848818c0, 0xb5f0e7e6, 0x46944cc4, 0x9a086824, 
+    0x9f052501, 0x34609e06, 0xd0032a01, 0xdb162900, 0xe00a2101, 0xd0062900, 0x2b00da02, 0xe00edc03, 
+    0xdaf52b00, 0x73254660, 0x9a07e005, 0x1a404351, 0xb2402100, 0x42b07321, 0x4630dd04, 0x2100e005, 
+    0xe7f243c9, 0xda0142b8, 0x73254638, 0xb5f0bdf0, 0x0005b085, 0x201ed04c, 0x2d0143c0, 0x2d03d001, 
+    0x2200d046, 0x231e49a9, 0x24206809, 0x5f0c5ecb, 0x4323029b, 0x3440460c, 0x3b0f7ce6, 0x4ea42e01, 
+    0x4fa46836, 0x19f6d037, 0x83ce8e36, 0x68364ea0, 0x8e7619f6, 0x0db605b6, 0x261e840e, 0x27205f8e, 
+    0x02b65fcf, 0x2119433e, 0x56613e0f, 0x1c4e46b4, 0xd9012e02, 0x76611049, 0x275a7f61, 0xb2ce1c49, 
+    0x77664992, 0x2e056809, 0xd81d57cf, 0x56612119, 0x92012600, 0x90009102, 0x221b9603, 0x463856a2, 
+    0xf7ff4661, 0x4989ff88, 0x31406809, 0xe02375ce, 0x2000221f, 0x19f6e7b6, 0x83ce8d36, 0x68364e84, 
+    0x8d7619f6, 0xe7c7b2f6, 0x2e072101, 0x2619d812, 0x920157a6, 0x90009103, 0x221b9602, 0x463856a2, 
+    0xf7ff4661, 0x4979ff68, 0x6809226c, 0x31405c52, 0xe00175ca, 0x75e14638, 0x68214c74, 0x7e8a3140, 
+    0x768876ca, 0xd00a2d00, 0xd0082d01, 0xfdf0f7fd, 0x46016820, 0x7dc23040, 0xd0032a01, 0xf7fde00f, 
+    0xe7f5fbb3, 0xd00d2d00, 0xd0132d01, 0x2d024a6a, 0xd0175682, 0xda002a00, 0x00d04252, 0x20007388, 
+    0xbdf0b005, 0x5682221a, 0xda002a00, 0x00d04252, 0xe7f473c8, 0x5682221a, 0xda002a00, 0x00d04252, 
+    0xe7ec7408, 0xda002a00, 0x00d04252, 0xe7e67348, 0x4e56b5f8, 0x68304604, 0x5c0b2153, 0x49542500, 
+    0x4a542b01, 0xd017680b, 0x8e1b189b, 0x680983c3, 0x8e491889, 0x0d890589, 0xf7fd8401, 0x6831fb6c, 
+    0x3340460b, 0x2c0276d8, 0x2c03d00e, 0x2c01d00f, 0x2c00d010, 0xe012d011, 0x8d1b189b, 0x680983c3, 
+    0x8d491889, 0xe7e7b2c9, 0x5c452079, 0x207ae007, 0xe0045c45, 0x5c45207b, 0x207ce001, 0x8bca5c45, 
+    0x2a002000, 0x200ad005, 0x1052e00c, 0x840a1c40, 0x2220b240, 0x2a005e8a, 0xe007dcf7, 0x1c401052, 
+    0xb24083ca, 0x5e8a221e, 0xdcf72a00, 0xb2401f00, 0x01c08c8a, 0x10c008d2, 0x1a10271f, 0x2c02023f, 
+    0x2c03d005, 0x2c01d003, 0x2c00d001, 0x42b8d102, 0x4638dd00, 0x0c1604c2, 0x181200ea, 0x2c02848e, 
+    0x2c03d005, 0x2c01d003, 0x2c00d001, 0x42bad102, 0x463add00, 0x0c0004d0, 0x271f0542, 0x427d0e12, 
+    0xd00a2c00, 0xd0082c03, 0x42400ac0, 0xd0072c01, 0xd0112c02, 0xd00f2c03, 0x0ac0e019, 0xd1f52c00, 
+    0xdd01281f, 0xe01276df, 0xda0142a8, 0xe00e76dd, 0xd00c2800, 0xe00a76d8, 0xdd01281f, 0xe006769f, 
+    0xda0142a8, 0xe002769d, 0xd0002800, 0x20017698, 0x2c0075d8, 0x2c01d012, 0x2c02d016, 0x0a30d01b, 
+    0x31607388, 0x768a778e, 0xbdf82000, 0x20000090, 0x20000084, 0x0001a040, 0x0000001a, 0x73c80a30, 
+    0x77ce3160, 0xe7ef770a, 0x74080a30, 0x54462080, 0x76ca3160, 0x0a30e7e8, 0x31607348, 0x764a774e, 
+    0x2103e7e2, 0x8a8a0709, 0x43d222c0, 0x07c0828a, 0x01c10fc0, 0x43010180, 0x680048fe, 0x18804afe, 
+    0x477081c1, 0x2103b510, 0x8a8a0709, 0x828a138a, 0x221505c0, 0x02520dc0, 0x4af61883, 0x48f66814, 
+    0x82e31824, 0x4bf58a8b, 0x6812828b, 0x18101c59, 0xbd1082c1, 0x2103b510, 0x8a8a0709, 0x828a138a, 
+    0x220b05c0, 0x02920dc0, 0x4aea1883, 0x48ea6814, 0x82e31824, 0x4be98a8b, 0x6812828b, 0x18101c59, 
+    0xbd1082c1, 0x2103b510, 0x8a8a0709, 0x828a138a, 0x221305c0, 0x02520dc0, 0x4ade1883, 0x48de6814, 
+    0x82e31824, 0x4bdd8a8b, 0x6812828b, 0x18101c59, 0xbd1082c1, 0x2103b510, 0x8a8a0709, 0x828a138a, 
+    0x220505c0, 0x02d20dc0, 0x4ad21883, 0x48d26814, 0x82e31824, 0x4bd18a8b, 0x6812828b, 0x18101c59, 
+    0xbd1082c1, 0x2400b510, 0xdd062800, 0xf7ff4620, 0x4620ffe1, 0xffc6f7ff, 0x2800bd10, 0xda054620, 
+    0xffa8f7ff, 0xf7ff4620, 0xbd10ff8d, 0xfd2df7fd, 0xf7fd4620, 0xbd10fd12, 0x4bc1b510, 0x681b408a, 
+    0x8e1c4002, 0x43144384, 0xbd10861c, 0x4bbcb510, 0x681b408a, 0x8e5c4002, 0x43144384, 0xbd10865c, 
+    0x4604b510, 0xfb94f7fd, 0x07092103, 0x201f8a88, 0x828843c0, 0x06e248af, 0x0ed26803, 0x0364240d, 
+    0x855a191b, 0x4aaf8a8a, 0x4baf828a, 0x4aaa6804, 0x842318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 
+    0x84811880, 0xb510bd10, 0xf7fd4604, 0x2103fb71, 0x8a880709, 0x43c0201f, 0x489e8288, 0x680306e2, 
+    0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x828a4a9d, 0x68042309, 0x4a98031b, 0x842318a4, 0x23ff8a8b, 
+    0x2101828b, 0x02896800, 0x84811880, 0xb510bd10, 0xf7fd4604, 0x2103fb4d, 0x8a880709, 0x43c0201f, 
+    0x488c8288, 0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x3a204a8b, 0x4b8b828a, 0x33146804, 
+    0x18a44a85, 0x8a8b8423, 0x828b2300, 0x68044b87, 0x846318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 
+    0x84811880, 0x2800bd10, 0x43c0da00, 0x4770b280, 0x4c7bb5ff, 0x68204607, 0x9e092200, 0x30609d0a, 
+    0x29004694, 0xda04d003, 0xdc042b00, 0x2101e014, 0x2b00e019, 0x4608da0e, 0xffe5f7ff, 0x46184601, 
+    0xffe1f7ff, 0xd3004281, 0x68219f02, 0x31602001, 0xe0097308, 0xe0012101, 0x43c92100, 0x43599b0b, 
+    0xb24f1a79, 0x73012100, 0xdd0142af, 0xe002462f, 0xda0442b7, 0x68214637, 0x31602201, 0x42af730a, 
+    0x42b7d001, 0x2001d101, 0x68204684, 0x30604661, 0x72c17282, 0xb0044638, 0xb5f0bdf0, 0x46a62404, 
+    0x9d062701, 0x9e052400, 0x42a846bc, 0x42aadc36, 0x42b0dc34, 0x42b2db32, 0x9f07db30, 0x425e424d, 
+    0xd10e4287, 0xd0292900, 0xdd014290, 0x46841e60, 0xda002900, 0xb2084629, 0xda002b00, 0xb2194633, 
+    0x4297e010, 0x2b00d11a, 0x4282d018, 0x2000dd02, 0x468443c0, 0xda002b00, 0xb2184633, 0xda002900, 
+    0xb2094629, 0x23012200, 0x428803db, 0x1a09da08, 0x03c90064, 0xb26418c9, 0xe0081409, 0xbdf02000, 
+    0x1c640064, 0x03c01a40, 0xb26418c0, 0x1c521400, 0x4572b2d2, 0x1c64d9e9, 0x46611060, 0xd1ee1c49, 
+    0xb2404240, 0xb5f0bdf0, 0xb0874604, 0x90052001, 0x4f28482f, 0xdd082c00, 0x18096839, 0x06898909, 
+    0x6839168e, 0x88c01808, 0x6839e011, 0xda072c00, 0x89891809, 0x168e0689, 0x18086839, 0xe0068940, 
+    0x88891809, 0x168e0689, 0x18086839, 0x06808840, 0x481b1685, 0x46016800, 0x468c3140, 0x29007f49, 
+    0x683ad176, 0x18524914, 0x5e512128, 0x9103221f, 0x42519b05, 0x92019302, 0x231e9100, 0x46605ec3, 
+    0x56822218, 0x99034630, 0xff22f7ff, 0x480c9004, 0x6800216c, 0x29005c09, 0x221fd02f, 0x9b044251, 
+    0x92019302, 0x231e9100, 0x5ec32258, 0x46305682, 0xe00f9903, 0x20000084, 0x0001a040, 0x00007fff, 
+    0x20000090, 0x00000ff3, 0x0000a00c, 0x00002020, 0x0001a280, 0xff41f7ff, 0x48fe4601, 0x6800225b, 
+    0x54112c00, 0x3060dd02, 0xe0067441, 0xda022c00, 0x73c13060, 0x3060e001, 0x48f67341, 0x46016800, 
+    0x760e3140, 0x83c29a03, 0x7b003060, 0x2c007748, 0x9804dd03, 0xfe1ef7ff, 0x9804e007, 0xda022c00, 
+    0xfde8f7ff, 0xf7fde001, 0x4eeafb70, 0x30606830, 0x29007b01, 0x2c00d025, 0x7a82dd0b, 0x20202105, 
+    0xfe3af7ff, 0x21056830, 0x7ac23060, 0xe0162020, 0x7a82e017, 0xda092c00, 0x20022101, 0xfe2cf7ff, 
+    0x21016830, 0x7ac23060, 0xe0082002, 0x20082103, 0xfe22f7ff, 0x21036830, 0x7ac23060, 0xf7ff2008, 
+    0x4ed4fe25, 0x46086831, 0x7f823040, 0xd1772a00, 0x4ad1683b, 0x222c189b, 0x231f5e9a, 0x425a9203, 
+    0x93019f05, 0x97029200, 0x22192320, 0x56825ecb, 0x99034628, 0xfe8cf7ff, 0x68304607, 0x5c09216c, 
+    0xd01c2900, 0x424a211f, 0x91019200, 0x23209702, 0x5ec32259, 0x46285682, 0xf7ff9903, 0x4601febe, 
+    0x6830225a, 0x54112c00, 0x3060dd02, 0xe0067481, 0xda022c00, 0x74013060, 0x3060e001, 0x68307381, 
+    0x31404601, 0x9a03764d, 0x30608402, 0x77887b00, 0xdd032c00, 0xf7ff4638, 0xe007fd85, 0x46382c00, 
+    0xf7ffda02, 0xe001fd4f, 0xfad7f7fd, 0x30606830, 0x29007b01, 0x2c00d024, 0x7a82dd0a, 0x20102104, 
+    0xfdbaf7ff, 0x21046830, 0x7ac23060, 0xe0152010, 0x2c007a82, 0x2100da09, 0xf7ff2001, 0x6830fdad, 
+    0x30602100, 0x20017ac2, 0x2102e008, 0xf7ff2004, 0x6830fda3, 0x30602102, 0x20047ac2, 0xfda6f7ff, 
+    0x30406830, 0x29007f41, 0x7f81d004, 0xd0012900, 0xe0002101, 0x75c12100, 0xbdf0b007, 0x488db5f0, 
+    0x68032707, 0x336043ff, 0x7b597c58, 0x1a4010fa, 0x42b8b240, 0x2101dc01, 0x2808e004, 0x4611db01, 
+    0x2100e000, 0x68204c85, 0x19804e85, 0x251e8900, 0x16800680, 0x43ed1840, 0xda0142a8, 0xe0024628, 
+    0xdd00281f, 0x7c99201f, 0x1ac97b9b, 0x42b9b249, 0x2201dc01, 0x2908e002, 0x2200da00, 0x19896821, 
+    0x068988c9, 0x188c1689, 0xda0142ac, 0xe002462c, 0xdd002c1f, 0xf7ff241f, 0x4620fd1d, 0xfd02f7ff, 
+    0x486cbdf0, 0x68002200, 0x460183c2, 0x31408402, 0x75ca754a, 0x764a760a, 0x76ca768a, 0x778a774a, 
+    0x5c092184, 0xd0012901, 0x84c28442, 0x85028482, 0xb5704770, 0x68204c5f, 0x7a813040, 0xd05a2903, 
+    0x43ed2500, 0xd01f2904, 0xd0372905, 0xf7ff2001, 0x2103fc98, 0x8a880709, 0x43c02010, 0x49578288, 
+    0x68092010, 0x32404a54, 0x80081889, 0xf7ff4628, 0xf7fffcf9, 0x2009ffc6, 0xfd22f7ff, 0xff19f7fc, 
+    0x21046820, 0x72813040, 0xff5bf7fc, 0xd0452800, 0xf7ff4628, 0x6820fe28, 0x7dc03040, 0xd0ed2800, 
+    0xf7ff2000, 0xf7fffcdf, 0x2009ffac, 0xfd2bf7ff, 0xfefff7fc, 0x21056820, 0x72813040, 0xff41f7fc, 
+    0xd02b2800, 0xf7ff2000, 0x6820fe0e, 0x7dc03040, 0xd0ed2800, 0xf7fc2000, 0x2001ff17, 0xfcc2f7ff, 
+    0xff8ff7ff, 0xf7fd2009, 0xf7fcfdb5, 0x6820fee2, 0x30402103, 0xf7fc7281, 0x2800ff24, 0x2001d00e, 
+    0xfdf1f7ff, 0x30406820, 0x28007dc0, 0xf7ffd0ed, 0x2000ff35, 0xfc35f7ff, 0xbd702000, 0xbd702002, 
+    0x4a26b5f0, 0x43ff271e, 0x6810261f, 0x1179b085, 0x18c44b21, 0x5e202030, 0xdd01281f, 0xe00c0c4c, 
+    0x42e02420, 0x460cda01, 0x6812e007, 0x18d20280, 0x05928e52, 0x43100d92, 0x4816b204, 0x68022310, 
+    0x30404610, 0x930356c3, 0x97009102, 0x23209601, 0x22185ed3, 0x46215682, 0xf7ff9803, 0x4605fd19, 
+    0x216c480c, 0x5c096800, 0xd0122900, 0x86810129, 0x96019700, 0x23209502, 0x5ec32258, 0x46215682, 
+    0xf7ff9803, 0x4601fd4a, 0x68004802, 0x18898e82, 0xe0078681, 0x20000090, 0x0001a040, 0x20000084, 
+    0x0001a280, 0x9a0348f9, 0x46016800, 0x760a3140, 0x30608404, 0x75c87b00, 0xf7fd4628, 0xb005f8c9, 
+    0xb5f8bdf0, 0x25034cf1, 0x072d6820, 0x7a803040, 0x4ff04eef, 0xd021280c, 0xff03f7ff, 0x30406820, 
+    0x76417c01, 0xfe77f7fc, 0x31406821, 0x20007688, 0xf8aef7fd, 0xf7fc2000, 0x8aa8fe77, 0x683a82ae, 
+    0x200d2101, 0x18100340, 0x200980c1, 0xfc8ff7ff, 0xfe3ff7fc, 0x210c6820, 0x72813040, 0xfe81f7fc, 
+    0xd0072800, 0xff6cf7ff, 0x31406821, 0x28007dc8, 0xe004d002, 0xbdf82002, 0x28207d48, 0x8aa8d3e8, 
+    0x683b82ae, 0x200d2200, 0x18180340, 0x201980c2, 0xf7fd5608, 0x6821f87d, 0x5608205a, 0xfe44f7fc, 
+    0xbdf82000, 0x460db570, 0xf0030003, 0x0e06f99b, 0x0a080604, 0x24080e0c, 0x2410e008, 0x2420e006, 
+    0x2440e004, 0x2480e002, 0x2400e000, 0xffa0f7fc, 0x07002003, 0x211f8a81, 0x828143c9, 0x06ea49bd, 
+    0x0ed2680b, 0x036d250d, 0x855a195b, 0x4aba8a82, 0x680d8282, 0x4ab92320, 0x842b18ad, 0x23008a83, 
+    0x4bb78283, 0x18ad680d, 0x8a83846b, 0x828323ff, 0x02206809, 0x84881889, 0xb5f0bd70, 0x05cf2203, 
+    0x0dff0712, 0x4cab1396, 0x00034dac, 0xf95af003, 0x45044406, 0x44bbb6b1, 0xdd012946, 0xe0012146, 
+    0xdd02293f, 0x383f4608, 0x2000e000, 0xb2408a93, 0x039b2303, 0x05c38293, 0x0ddb2601, 0x682702b6, 
+    0x197f199e, 0x8a9682fe, 0x82964e9e, 0x1c766827, 0x82fe197f, 0x27038a97, 0x829703bf, 0x19db117f, 
+    0x197f6827, 0x8a9382fb, 0x82931e73, 0x195b6823, 0x8a9382de, 0x039b2303, 0x1a088293, 0x682105c0, 
+    0x30ff0dc0, 0x30ff1949, 0x82c83002, 0x1e708a90, 0x68208290, 0x82c61940, 0x460bbdf0, 0x4248331f, 
+    0xd9062b3e, 0xdb012900, 0xe000460b, 0x3b1f4603, 0x2300e000, 0xb25b8a97, 0x03b62603, 0x05de8296, 
+    0x27050df6, 0x4c7b027f, 0x19f746b4, 0x19766826, 0x8a9782f7, 0x82974f7b, 0x1c7f6826, 0x82f71976, 
+    0x27038a97, 0x829703bf, 0x113f4666, 0x682719f6, 0x82fe197f, 0x4f738a97, 0x68248297, 0x19641c7f, 
+    0x8a9482e7, 0x03a42403, 0x29008294, 0x4608db00, 0x05c01ac0, 0x0dc02301, 0x18c302db, 0x68044865, 
+    0x82e31964, 0x4b678a93, 0x68078293, 0x197f1c5c, 0x8a9682fc, 0x03b62603, 0x26058296, 0x02b60fc9, 
+    0x198e6807, 0x82fe197f, 0x82938a96, 0x19766806, 0x8a9682f4, 0x03b62603, 0x260b8296, 0x19890276, 
+    0x19766806, 0x8a9182f1, 0x68008293, 0x82c41940, 0x8a90bdf0, 0x20078296, 0xe0080240, 0x82968a90, 
+    0x03002001, 0x8a90e003, 0x20098296, 0x68210240, 0x19491838, 0x8a9082c8, 0x8290484a, 0x1c406821, 
+    0x82c81949, 0xb40fbdf0, 0xae08b5fe, 0x7bb44684, 0x7c357bf3, 0x26007c70, 0x96004627, 0x2a009601, 
+    0x461cd101, 0x2901463b, 0x1c49d002, 0xe018d00c, 0xd2012c07, 0xe00a1c64, 0xd0012b00, 0xb2db1e5b, 
+    0xd20e4285, 0xe00b1c6d, 0xd0022c00, 0xb2e41e64, 0x2b07e007, 0x1c5bd201, 0x2d00b2db, 0x1e6dd001, 
+    0x4668b2ed, 0x2a007105, 0x7084d011, 0xa90870c3, 0x46697b08, 0xa9087008, 0x46697b48, 0x22067048, 
+    0xf0024660, 0xbcfeff06, 0xb004bc08, 0x70c44718, 0xe7ec7083, 0x1ad3b5fe, 0x4d204c1e, 0x2801b25e, 
+    0x2802d005, 0x4611d07b, 0xfed7f7ff, 0x6820bdfe, 0x8ec01940, 0x0480466a, 0x71900f40, 0x19406820, 
+    0x05408ec0, 0x71d00f40, 0x19406820, 0x06808ec0, 0x72100e80, 0x7250203f, 0xd0022900, 0xd12b2901, 
+    0x8910e022, 0x22018010, 0xa8014631, 0xf7ff9b01, 0x4806ff8a, 0x30806800, 0x06c97a01, 0x7b80d502, 
+    0xd5190680, 0x79884669, 0xe01571c8, 0x20000090, 0x0000fffe, 0x20000084, 0x00008bd3, 0x0001a040, 
+    0x00002020, 0x00007fff, 0x80108910, 0x46312200, 0x9b01a801, 0xff67f7ff, 0x07002003, 0x13818a81, 
+    0x466b8281, 0x230179da, 0x18d2029b, 0x195b6823, 0x8a8282da, 0x82824afe, 0x1c566823, 0x82de195b, 
+    0x82818a83, 0x799b466b, 0x19db14c7, 0x197f6827, 0x8a8382fb, 0x68238282, 0x82de195b, 0x82818a83, 
+    0x7a19466b, 0x31ff6823, 0x31ff195b, 0x82d93102, 0x82828a81, 0x19406820, 0xbdfe82c6, 0x6822e7ff, 
+    0x181248ec, 0x466d8f12, 0x0fd20652, 0x6822712a, 0x8f121812, 0x0fd20692, 0x6822716a, 0x8f121812, 
+    0x0f530492, 0x682271ab, 0x8f121812, 0x0f520552, 0x682571ea, 0x8f001828, 0x06c0466d, 0x72280ec0, 
+    0x726f271f, 0x29002500, 0x2901d002, 0xe028d144, 0xd10442c3, 0xd1021c70, 0x46692001, 0x466a7108, 
+    0x00407910, 0x1c404240, 0xb2414370, 0x80108910, 0xa8012201, 0xf7ff9b01, 0x466afef6, 0x7a107991, 
+    0xd10042c1, 0x48cc7115, 0x30806800, 0x06d27a02, 0x7b80d502, 0xd51f0640, 0x71d1466a, 0x71507910, 
+    0x42c2e01a, 0x1c70d104, 0x2001d102, 0x71484669, 0x7950466a, 0x42400040, 0x43701c40, 0x8910b241, 
+    0x22008010, 0x9b01a801, 0xfecdf7ff, 0x79d0466a, 0x42c87a11, 0x7155d100, 0x07002003, 0x13828a81, 
+    0x466e8282, 0x230579f1, 0x6825025b, 0x49b118cb, 0x82eb186d, 0x4bae8a83, 0x68268283, 0x18761c5d, 
+    0x8a8682f5, 0x466e8282, 0x148779b6, 0x682719f6, 0x82fe187f, 0x82838a86, 0x18766826, 0x8a8682f5, 
+    0x466e8282, 0x112f7a36, 0x682719f6, 0x82fe187f, 0x82838a86, 0x18766826, 0x8a8682f5, 0x466e8282, 
+    0x27057936, 0x19f602bf, 0x187f6827, 0x8a8682fe, 0x68268283, 0x82f51876, 0x82828a86, 0x7972466e, 
+    0x0276260b, 0x68261992, 0x82f21876, 0x82838a82, 0x18406820, 0xe74082c5, 0x68004890, 0x1840498d, 
+    0x06808e80, 0x47700e80, 0x488bb5f3, 0x6800b087, 0x30409005, 0x7cc09004, 0x28014e86, 0x9805d01a, 
+    0x7a013080, 0xd51b06c9, 0x29019907, 0x2902d002, 0xe015d003, 0x06807b80, 0x7b80e001, 0x28000640, 
+    0x9808db0e, 0xd0052800, 0x6800487c, 0x202c1981, 0xe00a5e08, 0x68004879, 0x20281981, 0xe0045e08, 
+    0x68004876, 0x20301981, 0x99075e08, 0x43ed250e, 0xf002000b, 0x7306fec7, 0x645a2304, 0x9908736b, 
+    0xd00e2900, 0x680a496d, 0x8ed21992, 0x05526809, 0x19890f52, 0x06898ec9, 0x18540e89, 0x27462500, 
+    0x4a66e05f, 0x19896811, 0x68128ec9, 0x0f490489, 0x8ed21992, 0x0e920692, 0xe7ef188c, 0x29009908, 
+    0x680a495e, 0x1992d013, 0x09528f12, 0x0fd207d2, 0xd01b680a, 0x8f121992, 0x07520a12, 0x0f526809, 
+    0x8f091989, 0x0ec906c9, 0x424c1851, 0x1992e019, 0x09928f12, 0x0fd207d2, 0xd003680a, 0x8f121992, 
+    0xe7ea0ad2, 0x8f121992, 0xe0020ad2, 0x8f121992, 0x07520a12, 0x0f526809, 0x8f091989, 0x0ec906c9, 
+    0x25251854, 0x272643ed, 0x4944e01b, 0x19896809, 0x251e8f49, 0x168c0689, 0x271f43ed, 0x493fe011, 
+    0x19896809, 0x05498f49, 0xe00516cc, 0x6809493b, 0x223a1989, 0x12d45e8a, 0xe002270f, 0x46252400, 
+    0x99044627, 0x764c2c00, 0xdb03d002, 0xe0032101, 0xe0012100, 0x43c92100, 0xb2001a40, 0x98049003, 
+    0x28007d40, 0x2000d015, 0x950043c0, 0x98059002, 0x23209701, 0x98045ec3, 0x56822218, 0x99034620, 
+    0xf926f7ff, 0x48244604, 0x6800216c, 0x30405c09, 0x980775c1, 0xd10b2801, 0xd10442ac, 0x1c419803, 
+    0x2101da01, 0x2100e000, 0x6800481b, 0x71413080, 0x68004819, 0x7d813040, 0xd0022901, 0x28037d00, 
+    0x9807d106, 0xd0042801, 0xd0052802, 0xd0032803, 0x42bce096, 0xe093d004, 0xd00142bc, 0xd17d42ac, 
+    0x07002003, 0x21018a81, 0x828143c9, 0x20014d0b, 0x220d6829, 0x18890352, 0x46018648, 0xf002201c, 
+    0x9808fc72, 0x68282800, 0x1980d027, 0xe0078ec0, 0x00007fff, 0x0001a040, 0x20000090, 0x20000084, 
+    0x68290540, 0x19890f40, 0x06898ec9, 0x18410e89, 0x19806828, 0x09408f00, 0x0fc007c0, 0xd0266828, 
+    0x8f001980, 0x07400a00, 0x0f40682a, 0x8f121992, 0x0ed206d2, 0x42401880, 0x1980e024, 0x68298ec0, 
+    0x0f400480, 0x8ec91989, 0x0e890689, 0x68281841, 0x8f001980, 0x07c00980, 0x68280fc0, 0x1980d003, 
+    0x0ac08f00, 0x1980e7df, 0x0ac08f00, 0x1980e002, 0x0a008f00, 0x682a0740, 0x19920f40, 0x06d28f12, 
+    0x18800ed2, 0x0c000600, 0x68284301, 0x8f401980, 0x06802603, 0x06001680, 0x43010a00, 0x23009101, 
+    0x96004632, 0x20012112, 0xfb97f002, 0xfe84f7ff, 0x02006829, 0x18894afe, 0xe0008849, 0x0709e010, 
+    0x43080f09, 0x230049fb, 0x22036809, 0x7bc93140, 0x04099600, 0x90014308, 0x20012113, 0xfb7df002, 
+    0x68284df4, 0x7cc13040, 0xd0112901, 0x56c32319, 0x99084622, 0xf7ff9807, 0x6828fd1d, 0x84019903, 
+    0x7e413040, 0x7d417601, 0x75411c49, 0xbdf0b009, 0x98074621, 0xfbf1f7ff, 0xb510e7ef, 0x07092103, 
+    0x138a8a8a, 0x05c0828a, 0x0dc02217, 0x18830252, 0x68144ae1, 0x384048de, 0x82e31824, 0x4bdf8a8b, 
+    0x6812828b, 0x18101c59, 0xbd1082c1, 0x48d9b5fe, 0x68014fd7, 0x4608233e, 0x7cc43040, 0x223f43db, 
+    0x3f402501, 0x2c004ed4, 0x2c01d001, 0x6834d021, 0x243019e7, 0x68365f3c, 0x19f64fd1, 0x950289f6, 
+    0x92019300, 0x23200676, 0x16772218, 0x56825ecb, 0x46214dc8, 0xf7ff4638, 0x4606f80b, 0x46016828, 
+    0x760f3140, 0x30608404, 0x75ca7b02, 0xd0052a01, 0x6834e010, 0x242c19e7, 0xe7dc5f3c, 0x21067a82, 
+    0xf7fe2040, 0x6828ff69, 0x30602106, 0x20407ac2, 0xff6cf7fe, 0xf7ff4630, 0x363effa0, 0x2e7c6828, 
+    0x3040d904, 0x220279c1, 0xe0034311, 0x79c13040, 0x401122fd, 0xe52071c1, 0x4caeb510, 0x6820214a, 
+    0x290a5c09, 0x3080d016, 0x07807b40, 0x2000d41d, 0xff83f7ff, 0x30406820, 0x28017cc0, 0xf7ffd815, 
+    0x2010f9f0, 0xff4cf7fe, 0xf943f7fc, 0x210a6820, 0x72813040, 0xf985f7fc, 0xd0082800, 0xff86f7ff, 
+    0x30406820, 0x28007dc0, 0x2000d0ee, 0x2002bd10, 0xb510bd10, 0x68204c97, 0x30404601, 0x2a0e7a82, 
+    0x3180d011, 0x07897b49, 0x7cc0d418, 0xd8152801, 0xf9c7f7ff, 0xf7fe2010, 0xf7fcff23, 0x6820f91a, 
+    0x3040210e, 0xf7fc7281, 0x2800f95c, 0xf7ffd00c, 0x6820ff5d, 0x7dc03040, 0xd0ee2800, 0x212f6820, 
+    0x72813040, 0xbd102000, 0xbd102002, 0x281fb510, 0x201fd901, 0xb241e003, 0xda002900, 0xf7fe2000, 
+    0xbd10fc2a, 0x4604b510, 0xfa92f7fc, 0x07092103, 0x201f8a88, 0x828843c0, 0x06e24877, 0x0ed26803, 
+    0x0364240d, 0x855a191b, 0x4a768a8a, 0x4b76828a, 0x4a6f6804, 0x18a43a40, 0x8a8b8423, 0x828b2300, 
+    0x68044b72, 0x846318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 0x84811880, 0xb510bd10, 0xf7fc4604, 
+    0x2103fa67, 0x8a880709, 0x43c0201f, 0x48628288, 0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 
+    0x828a4a63, 0x68042309, 0x4a59029b, 0x18a43a40, 0x8a8b8423, 0x828b2300, 0x68044b5c, 0x18a43340, 
+    0x8a8b8463, 0x828b23ff, 0x68002107, 0x188002c9, 0xbd108481, 0x4604b570, 0xfa3af7fc, 0x07092103, 
+    0x201f8a88, 0x828843c0, 0x06e3484b, 0x0edb6804, 0x0352220d, 0x856318a4, 0x4b488a8b, 0x6804828b, 
+    0x4d431c5b, 0x19643d40, 0x8a8b8423, 0x43db2380, 0x6800828b, 0x18802180, 0xbd708401, 0x4a3eb510, 
+    0x4b3b6810, 0x18c03b40, 0x68118f00, 0x0f400480, 0x8f0918c9, 0x0ec906c9, 0x68101841, 0x8f0018c0, 
+    0x07c00980, 0xd0000fc0, 0x68104249, 0x8f0018c0, 0x05406814, 0x18e40f40, 0x68128f24, 0x0ee406e4, 
+    0x18d21900, 0x09528f12, 0x0fd207d2, 0x4240d000, 0x10401808, 0xbd103811, 0x2003b5f0, 0x8a810700, 
+    0x8281492c, 0x13814a24, 0x4b216814, 0x18e43b40, 0x8a818021, 0x82864e28, 0x6809491e, 0x7a0c3180, 
+    0xd50206e4, 0x06a47b8c, 0x2401d501, 0x2400e000, 0x00642501, 0x681702ad, 0x18ff1964, 0x8a84807c, 
+    0x7a0c8286, 0xd50206e4, 0x06497b89, 0x2101d501, 0x2100e000, 0x68140049, 0x18e41949, 0x8a8180a1, 
+    0x1c894915, 0x68148281, 0x80e518e4, 0x82818a84, 0x18e46814, 0x8a848125, 0x68118281, 0x814d18c9, 
+    0x490e8a81, 0x48098281, 0x18c96811, 0xbdf08188, 0x0001a080, 0x20000090, 0x20000084, 0x00007fff, 
+    0x0001a280, 0x00008ff3, 0x0000300c, 0x00002020, 0x00008bf3, 0x00003fff, 0x000093fd, 0x0000c0c0, 
+    0x2103b570, 0x8a8a0709, 0x828a4afb, 0x48fb0282, 0x230d6804, 0x18e4035b, 0x8a8a8522, 0x828a4af8, 
+    0x25006806, 0x19364cf7, 0x4df78075, 0x3580682d, 0x07ed7bad, 0x8a8dd10d, 0x6805828a, 0x192c1c52, 
+    0x8a8a8062, 0x43d22240, 0x6800828a, 0x18c02140, 0xbd708401, 0x2103b5f0, 0x8a8a0709, 0x828a4ae6, 
+    0x48e60282, 0x270d6803, 0x19db037f, 0x8a8a851a, 0x828a4ae3, 0x24006805, 0x18ed4be2, 0x8a8d806c, 
+    0x6805828a, 0x80ac18ed, 0x828a8a8d, 0x18ed6805, 0x8a8d80ec, 0x6805828a, 0x812c18ed, 0x828a8a8d, 
+    0x18ed6805, 0x4cd8816c, 0x34806824, 0x07ee7ba5, 0xd1044dd6, 0x828a8a8e, 0x18f66806, 0x7ba68075, 
+    0xd40407b6, 0x828a8a8e, 0x18f66806, 0x7ba480b5, 0xd4040764, 0x828a8a8c, 0x18d26802, 0x8a8a80d5, 
+    0x43d22240, 0x6800828a, 0x19c02140, 0xe76e8401, 0x4ec5b5fe, 0x68304ac1, 0x460449c2, 0x7cc33040, 
+    0x2b016812, 0x1851d028, 0x46258e09, 0x356083e1, 0x84a17829, 0x22018c61, 0xb249231f, 0x92029301, 
+    0x22189100, 0x23205682, 0x2000211e, 0x5e615ee3, 0xf7fe5628, 0x6831fdcd, 0x460ab2c0, 0x70103260, 
+    0x3a204613, 0x46148c8d, 0x7b1a7615, 0x8bca75e2, 0xf7ff840a, 0xe5defe3b, 0x8d091851, 0xb5fee7d5, 
+    0x4aa64ea9, 0x4ba76831, 0x3140460c, 0x68127ccd, 0xd02d2d01, 0x8e1218d2, 0x1810231f, 0x226183e0, 
+    0x85205710, 0x43d22200, 0x93012500, 0x95009202, 0x568a2218, 0x211e2320, 0x5e615ee3, 0xfd98f7fe, 
+    0x460a6831, 0x70503260, 0x3a204613, 0x46178d0c, 0x7b1a7614, 0x8bca75fa, 0xf7fb840a, 0x6830ff35, 
+    0x5c09216a, 0xd0062900, 0x30802101, 0xe5a27241, 0x8d1218d2, 0x3080e7d0, 0xe59c7245, 0x4887b5fe, 
+    0x48886801, 0x18083040, 0x4c878840, 0x68200702, 0x46070f12, 0x70ba3760, 0x212a8482, 0x25015e41, 
+    0x2b081d0b, 0x2356d803, 0x2b015c1b, 0x2200d022, 0x230f43d2, 0x93012600, 0x96009202, 0x5ec3232c, 
+    0x20022204, 0x563856ba, 0xfd52f7fe, 0xb2c16822, 0x30604610, 0x8c927081, 0x7102b2d2, 0x2b017b03, 
+    0x7186d001, 0x4291e008, 0x7185d101, 0x2102e004, 0xe0017181, 0x71bd713a, 0x8d416820, 0x21568581, 
+    0x29015c09, 0x4601d106, 0x798a3160, 0xd0012a01, 0x718a2202, 0x07092103, 0x220f8a8a, 0x828a43d2, 
+    0x78813060, 0x6802485d, 0x3040485e, 0x80411810, 0xb5f8e541, 0x25014c5c, 0x46016820, 0x7ccb3140, 
+    0x32604602, 0xd0042b00, 0xd1062b01, 0x075b7803, 0x238dd503, 0x075b5c1b, 0x7215d501, 0x7800e066, 
+    0x20050742, 0x77482a00, 0xf7feda03, 0x6821f98f, 0xf7fe8448, 0x4a4cf993, 0x84c86811, 0xfafcf7ff, 
+    0x46046812, 0x31604611, 0x78107008, 0xd5400740, 0x33804613, 0x28007958, 0x2000d005, 0x28005608, 
+    0x1c60da01, 0x2026e01a, 0x5e108c56, 0x4f4046b4, 0x8c381986, 0x428646b6, 0x7a58da08, 0xd1052800, 
+    0x367626ff, 0xd20145b4, 0xd3ea2c1f, 0x45b68c7e, 0x7a58dc23, 0xd1202800, 0x1e60e001, 0x4e327008, 
+    0xf7ff7808, 0x6830fd43, 0x30604602, 0x42a17801, 0x7a03d01b, 0xd0182b01, 0x42a12502, 0x2b04d91a, 
+    0x3240d016, 0x2a017d92, 0x2203d012, 0x1b087202, 0x2089e01a, 0x28005c80, 0x3240d004, 0x42947f52, 
+    0xe7dcd8db, 0xd3bc2c1f, 0x7205e7d9, 0xbdf82000, 0xe7ec7205, 0xd0092b03, 0x7d923240, 0xd0052a01, 
+    0x72022204, 0x42401a60, 0xbdf8b240, 0xe7f97205, 0x4604b510, 0xffacf7fb, 0x07092103, 0x201f8a88, 
+    0x828843c0, 0x06e2480d, 0x0ed26803, 0x0364240d, 0x855a191b, 0x4a0f8a8a, 0x2309828a, 0x029b6804, 
+    0x18a44a08, 0x8a8b8423, 0x828b2300, 0x6800490a, 0x84411880, 0x0000bd10, 0x000083ff, 0x20000084, 
+    0x00007fff, 0x0001a040, 0x20000090, 0x00008000, 0x20000200, 0x00008bff, 0x00002060, 0x2101b530, 
+    0xd804280d, 0x40811f80, 0x2001b2c9, 0x380ee003, 0xb2c94081, 0x22032002, 0x8a930712, 0x829323ff, 
+    0x020c4bfe, 0x49fe681d, 0x84ac186d, 0x240c8a94, 0x829443e4, 0x0080681a, 0x84081851, 0xb5febd30, 
+    0x68284df6, 0x36404ef6, 0x88801980, 0x07414ff5, 0x0f49683c, 0x30604620, 0x84a170c1, 0x43db2300, 
+    0x21002207, 0x92019302, 0x232e9100, 0x5ee32126, 0x5e612205, 0x46045682, 0x56202003, 0xfc18f7fe, 
+    0x4611683a, 0x70c83160, 0x71488c90, 0x71c87b08, 0x85d08cd0, 0x07002003, 0x22078a82, 0x828243d2, 
+    0x682978c8, 0x80881989, 0xb570e425, 0x25ff4cdd, 0x46016820, 0x7a8a3140, 0xd0172a17, 0xd0222a18, 
+    0x29007cc9, 0x7801d123, 0xd5200749, 0x7a403060, 0xd10f2800, 0xf7ff2009, 0x6820fd83, 0x21692201, 
+    0x2217540a, 0x540a214a, 0x72853080, 0xfda9f7fb, 0xd0122800, 0xf7ff2009, 0x6820fd9d, 0x214a2218, 
+    0x3080540a, 0xf7fb7285, 0x2800fd9c, 0x6820d005, 0x30402119, 0x20007281, 0x2002bd70, 0xb500bd70, 
+    0x460249c0, 0x20006809, 0x00133180, 0xf8caf002, 0x07041406, 0x14100d0a, 0x07c07b88, 0x7b88e00a, 
+    0xe0070780, 0x07407b88, 0x7b88e004, 0xe0010700, 0x06c07b88, 0x1c4017c0, 0xb5f8bd00, 0x26014cb1, 
+    0x25006820, 0x7a803040, 0xd0282820, 0xd0762821, 0xfdc7f7fe, 0x46016820, 0x7cc23040, 0xd0022a00, 
+    0xd04f2a01, 0x7809e082, 0xd57f0749, 0x76c57686, 0x30406820, 0xf7ff7e80, 0x2800ffc2, 0x6820d01e, 
+    0x30402106, 0xf7fe7e80, 0x6820feed, 0x75c53040, 0xf7fb7545, 0x6820fcfe, 0x30402120, 0xf7fb7281, 
+    0x2800fd40, 0x6820d067, 0x7ec13040, 0xf7ff7e80, 0x6820f97b, 0x7dc03040, 0xd0ea2800, 0x46026820, 
+    0x7a113280, 0xd51006c9, 0x31404601, 0x56cb231a, 0xd1022b01, 0x06bf7b97, 0x2b02d504, 0x7b92d105, 
+    0xd4020652, 0x2a007eca, 0x4601d00a, 0x76cd3140, 0x1c527e8a, 0x215a768a, 0x29065641, 0xe035dbb8, 
+    0xe7f876ce, 0x07497809, 0x2102d530, 0x76c57681, 0x30406820, 0xf7ff7e80, 0x2800ff72, 0x6820d01e, 
+    0x30402106, 0xf7fe7e80, 0x6820fe9d, 0x75c53040, 0xf7fb7545, 0x6820fcae, 0x30402121, 0xf7fb7281, 
+    0x2800fcf0, 0x6820d017, 0x7ec13040, 0xf7ff7e80, 0x6820f92b, 0x7dc03040, 0xd0ea2800, 0x30406820, 
+    0x1c897e81, 0x7681b249, 0xdbd12905, 0x30406820, 0x20007285, 0x2002bdf8, 0xb5f8bdf8, 0x24004d61, 
+    0x46026828, 0x7a813040, 0xd04d2910, 0x46287cc1, 0x30806800, 0xd0022900, 0xd0772901, 0x7b40e079, 
+    0xd17607c0, 0xfd1df7fe, 0x78006828, 0xd4060740, 0xf7ff200c, 0x6828fba2, 0x07407800, 0x6828d52e, 
+    0x31404601, 0x2a017d8a, 0x2185d00d, 0x29005c09, 0x2100d002, 0xe03643c9, 0xfefef7fd, 0x85486829, 
+    0xfd5cf7ff, 0x7fc9e047, 0xd1002900, 0x21858544, 0x29005c09, 0x8d41d003, 0x85411e49, 0xf7fde005, 
+    0x6829feeb, 0x18808d4a, 0x68288548, 0x7fc13040, 0xb2c91c49, 0x290877c1, 0xe02cd028, 0xfc39f7fb, 
+    0x21106828, 0x72813040, 0xfc7bf7fb, 0xd00c2800, 0x4b326828, 0x31404601, 0x4e317d8a, 0xd0062a01, 
+    0x19896819, 0x85418e09, 0x2002e7ca, 0x7fcabdf8, 0xd1002a00, 0x8d478544, 0x199b681b, 0x1c528e1b, 
+    0x854318fb, 0x77c8b2d0, 0xd1042808, 0xfd16f7ff, 0x30406828, 0x682877c4, 0x07497801, 0x3060d40c, 
+    0x28007980, 0xe007d097, 0xe002e000, 0x07c07b40, 0x2001d008, 0x71903260, 0x21336828, 0x72813040, 
+    0xbdf82000, 0xfc9df7fe, 0x46016828, 0x7d823040, 0xd0062a01, 0xfb72f7ff, 0x85486829, 0xfceef7ff, 
+    0x7fc0e015, 0xd1002800, 0xf7ff854c, 0x6829fb67, 0x18808d4a, 0x31408548, 0x1c407fc8, 0x77c8b2c0, 
+    0xd1042808, 0xfcdaf7ff, 0x30406828, 0x682877c4, 0x07497801, 0x3060d4d0, 0xe0057980, 0x20000084, 
+    0x0001a040, 0x20000090, 0xd0cd2800, 0xb510e7c4, 0x68204cfb, 0x31404601, 0x2a007cca, 0x2a01d006, 
+    0x7802d102, 0xd4010752, 0xe5c32000, 0x290f7a89, 0x3080d022, 0x06807b40, 0xf7fed42a, 0x2000fc52, 
+    0xfe06f7fb, 0xf7ff2009, 0x2003faad, 0x8a810700, 0x43c92120, 0x49eb8281, 0x68092020, 0x18894aea, 
+    0xf7fb8408, 0x6821fbb8, 0x70483160, 0xfb91f7fb, 0x210f6820, 0x72813040, 0xfbd3f7fb, 0xd00c2800, 
+    0xf7ff203c, 0x6820fc4c, 0x7dc03040, 0xd0ed2800, 0x21326820, 0x72813040, 0x2002e7c6, 0xb510e58a, 
+    0x68204cd7, 0x31404601, 0x2a117a8a, 0x7cc9d021, 0xd1452900, 0x5c092188, 0xd14109c9, 0x06897801, 
+    0x29020f89, 0xf7fed03c, 0x200cfc0c, 0xfd50f7ff, 0x21006820, 0x210684c1, 0x75413040, 0x30406820, 
+    0xf7ff7d40, 0xf7fbfd7b, 0x6820fb54, 0x30402111, 0xf7fb7281, 0x2800fb96, 0x49c2d011, 0x4ac26808, 
+    0x8e001880, 0xd0102800, 0x23266820, 0x68095ec3, 0x2130188a, 0x29005e51, 0x2101dd03, 0x2002e003, 
+    0x2100e548, 0x185943c9, 0x682084c1, 0x7d413040, 0xb2c91c49, 0x29167541, 0xf7ffd3d0, 0xe002fd70, 
+    0x30602101, 0x682071c1, 0x30402131, 0x20007281, 0xb5f8e530, 0x07002003, 0x49ac8a81, 0x4ea98281, 
+    0x68312001, 0x270d0240, 0x19c9037f, 0x68308048, 0x898019c0, 0xfa7ff001, 0xe0014605, 0xd0082c00, 
+    0x19c06830, 0x0a008980, 0x0fc007c0, 0x2401d001, 0x2400e000, 0xd0052c00, 0xfa6df001, 0xb2801b40, 
+    0xd3eb280b, 0x19c16830, 0x5e08200a, 0xd0032c00, 0xda012800, 0x43e42400, 0xbdf84620, 0x4890b510, 
+    0x30806800, 0x07807a00, 0x2000d501, 0xf7ffe4f2, 0x2800ffc0, 0x2003d0fa, 0x8a810700, 0x43c92101, 
+    0x49888281, 0x68092001, 0x0352220d, 0x86481889, 0x20174601, 0xfcd7f001, 0xe4db2001, 0x4c80b5f0, 
+    0x68202100, 0x78022503, 0x0752072d, 0x460f4e7d, 0xda2c2a00, 0x56822258, 0x68004620, 0x30601dd3, 
+    0xd8012b0e, 0xe0137087, 0x330f4613, 0xd8022b1e, 0x22042110, 0x4613e00b, 0x2b2e3317, 0x2120d802, 
+    0xe0042208, 0x2a3e321f, 0x2130d802, 0x7082220c, 0xf7fe2001, 0x8aa8fcc2, 0x43c0200f, 0x682082a8, 
+    0x30606831, 0x4a687880, 0x18893240, 0x68208048, 0x56412158, 0xda012900, 0xe0014865, 0x03802003, 
+    0x21018aa9, 0x683282a9, 0x200d0041, 0x18120340, 0x8aa98091, 0x82a9495f, 0x22806833, 0x805a181b, 
+    0x82a98aaa, 0x18086831, 0x20008047, 0xb570bdf0, 0x21884c53, 0x25006820, 0x30405c09, 0x290007c9, 
+    0x7605d003, 0x20007645, 0x7a81bd70, 0xd0012907, 0x76457605, 0xff3df7ff, 0xd0292800, 0x31406821, 
+    0x18107e0a, 0x7608b240, 0x301f7e4a, 0xb2521c52, 0x283e764a, 0x2a30d809, 0xf7ffda07, 0x6820ff7f, 
+    0x30402107, 0x20027281, 0x2003bd70, 0x8a810700, 0x43c92101, 0x493b8281, 0x68092001, 0x0352220d, 
+    0x86481889, 0x20174601, 0xfc3df001, 0xbd702001, 0x30406820, 0x4832e7c5, 0x68002153, 0x7bc15c0a, 
+    0x2a0008c9, 0x2901d007, 0x7c00d911, 0x280108c0, 0x2000d90d, 0x29014770, 0x7c01d909, 0x290108c9, 
+    0x7b41d905, 0x290108c9, 0x7b80d901, 0x2001e7ee, 0xb5f84770, 0x230f4d22, 0x4611682a, 0x56cb3140, 
+    0x7b90764b, 0x1b007b54, 0x84d01040, 0x24007d8e, 0xd0062e01, 0x05402601, 0x198005f6, 0x1a181600, 
+    0x4616e00d, 0x79b73680, 0xd3092f07, 0x280c71b4, 0x1e58dd01, 0x260ce003, 0xda0142f0, 0x76481c58, 
+    0x56082019, 0xda012818, 0xe0022018, 0xdd01282c, 0x7648202c, 0x56082019, 0xd02f4283, 0x00db1ac3, 
+    0x73c884d3, 0xfc7af7fb, 0x22266828, 0x5e827b81, 0x188923f8, 0x8501b209, 0xda0d2900, 0xe00e8504, 
+    0x20000090, 0x20000084, 0x0001a040, 0x0000f8ff, 0x00003fff, 0x0000ff7f, 0xdd0029f8, 0x8d018503, 
+    0x7b417381, 0xb2091a89, 0x29008501, 0x8504da01, 0x29f8e002, 0x8503dd00, 0x73418d01, 0xbdf82000, 
+    0x4cf8b510, 0x46016820, 0x7a823040, 0xd0232a12, 0x28007cc0, 0x2801d001, 0x3180d170, 0x06407b48, 
+    0xf7fed46c, 0xf7fbfa3e, 0x6821f9b6, 0x76083140, 0x77087c08, 0xf7fb200f, 0x6820fb48, 0x30402100, 
+    0x7d89e01d, 0xd0322901, 0xfcd4f7fd, 0xf981f7fb, 0x21126820, 0x72813040, 0xf9c3f7fb, 0xd0292800, 
+    0x30406820, 0x7d407d81, 0xd0252901, 0xfd5ff7fd, 0x30406820, 0x29007dc1, 0x7d41d0e8, 0x75411c49, 
+    0x31406821, 0x7d487cca, 0xd0182a00, 0x42902202, 0x201cd3d7, 0xf7fb5608, 0x6821fbbb, 0x56082058, 
+    0xf982f7fb, 0xff27f7ff, 0xd00a2801, 0xf7fde026, 0xe7cbfcd5, 0xe5982002, 0xfdeaf7fd, 0x2204e7d8, 
+    0x6820e7e5, 0x06407980, 0x2101d418, 0xf001201b, 0x6820fb4a, 0x7a013080, 0x2101070a, 0xdb0c2a00, 
+    0x07002003, 0x1eca8a82, 0x48bf8282, 0x220d6800, 0x18800352, 0x20018641, 0x7401e577, 0x23306820, 
+    0x46024601, 0x728b3140, 0x79843080, 0x1c644603, 0x7cc87184, 0xd10a2800, 0x07418810, 0x0600d407, 
+    0x7b58d405, 0xd40206c0, 0xff03f7ff, 0x2000e55d, 0xb510e55b, 0xf7fb4604, 0x2103faab, 0x8a880709, 
+    0x43c0201f, 0x48a88288, 0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x828a4aa4, 0x68044ba4, 
+    0x18a44aa4, 0x8a8b8423, 0x828b2300, 0x68044ba2, 0x846318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 
+    0x84811880, 0xb510e531, 0xf7fb4604, 0x2103fa81, 0x8a880709, 0x43c0201f, 0x48938288, 0x680306e2, 
+    0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x828a4a8f, 0x68044b8f, 0x18a44a8f, 0x8a8b8423, 0x828b2300, 
+    0x68044b8e, 0x846318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 0x84811880, 0xb570e507, 0x224d4c81, 
+    0x25006820, 0x292d5611, 0x292ed02b, 0x2161d00e, 0x30805c09, 0x20147441, 0xff9bf7ff, 0x84056820, 
+    0xf8a7f7fb, 0x212e6820, 0x73413040, 0xf8e9f7fb, 0xd0312800, 0xf7ff2000, 0x6820f962, 0x30404601, 
+    0x2a007dc2, 0x3160d0ec, 0x77417849, 0xf7ff2014, 0x6820ffaa, 0xf7fb8405, 0x6820f88c, 0x3040212d, 
+    0xf7fb7341, 0x2800f8ce, 0x2000d016, 0xf947f7ff, 0x46116822, 0x7dc83140, 0xd0ec2800, 0x2461734d, 
+    0x56a37f48, 0xdd004298, 0x77484618, 0x56102091, 0xf89af7fb, 0xbd702000, 0xbd702002, 0x4860b5f8, 
+    0x7f824c58, 0x46016820, 0x7a833040, 0xd02d2b23, 0xd03c2b24, 0x2b007cc3, 0x780bd102, 0xd401075b, 
+    0xbdf82000, 0x460b2500, 0x3380844d, 0x2e01791e, 0x7545d000, 0x2b00795b, 0x230fd00f, 0x1a9d56c3, 
+    0xdd012d00, 0x73c31e5b, 0x56c3230f, 0xd5011a9a, 0x73c31c5b, 0x84482001, 0x78c8e056, 0xb2403808, 
+    0xfa96f7fb, 0x21236820, 0x72813040, 0xff75f7ff, 0xd0d62802, 0x215d6820, 0x84c15c09, 0x300878c0, 
+    0xf7fbb240, 0x6820fa85, 0x30402124, 0xf7ff7281, 0x2802ff64, 0x6822d0c5, 0x46102600, 0x7f413040, 
+    0x43f68cd3, 0xb2091ac9, 0x290084d1, 0x7d43d010, 0xd0312b00, 0xdb012900, 0xe0002301, 0x251c4633, 
+    0x2d005745, 0x2501db01, 0x4635e000, 0xd02342ab, 0x84532301, 0xdb012900, 0xe000460d, 0x231c424d, 
+    0x2b0056c3, 0x461fdb01, 0x425fe000, 0xdd0a42bd, 0x78d23280, 0xd01a2a01, 0x5682220f, 0xdb002b00, 
+    0x19922601, 0x770173c2, 0x200f6821, 0x56083140, 0xda0f2818, 0xe0102018, 0x78d23280, 0xd0062a01, 
+    0x5682220f, 0xdb002900, 0x1b922601, 0x220fe7ea, 0xe7e75682, 0xdd01282c, 0x73c8202c, 0x5608200f, 
+    0xfa6cf7fb, 0x46016820, 0x7d423040, 0x1c524603, 0x7542b2d2, 0x28018c48, 0x2a10d014, 0x2001d212, 
+    0x0000e011, 0x20000090, 0x20000084, 0x00008ff3, 0x0000300c, 0x0001a040, 0x00006060, 0x00002060, 
+    0x20000200, 0x31802000, 0x20007108, 0xf7fb7298, 0xe745f9ff, 0x4efeb5fe, 0x30ff6830, 0x8e453001, 
+    0x80054668, 0x683006ac, 0x4ffa0ea4, 0x888019c0, 0x0fc00740, 0x0be8d10e, 0x05b8d00c, 0x21048a81, 
+    0x828143c9, 0x20046831, 0x808819c9, 0x20102101, 0xf989f001, 0x680148f0, 0x30804608, 0x42a27ec2, 
+    0x2300d01b, 0x2c002201, 0x3142d00e, 0x7602800d, 0x07002003, 0x82838a81, 0x19c06830, 0x23018003, 
+    0x94019200, 0xe0042203, 0x930175c2, 0x23019200, 0x21092204, 0xf0012001, 0x48dff8f0, 0x30806800, 
+    0xbdfe76c4, 0x4cdab57c, 0x49da6820, 0x18403940, 0x23038cc0, 0x48d807c6, 0x6800071b, 0x30802100, 
+    0x4ad62e00, 0x8a9e4dd3, 0xd00b829a, 0x22026823, 0x809a195b, 0x75822201, 0x910075c2, 0x46139101, 
+    0xe019210b, 0x19526822, 0x68228091, 0x88921952, 0x0fd20752, 0x8a9ad10b, 0x68228299, 0x88521952, 
+    0x04526823, 0x195b0c52, 0x7581805a, 0x91007641, 0x22042301, 0x21219101, 0xf0012001, 0xbd7cf8ae, 
+    0x48bbb510, 0x49bb6800, 0x18403940, 0x08608d84, 0xd00107c0, 0xffb6f7ff, 0xd00107e0, 0xff6af7ff, 
+    0xb57cbd10, 0x46054eb4, 0x24016830, 0x7dc03080, 0xd1082800, 0x90012005, 0x22022300, 0x94002115, 
+    0xf0012001, 0x6831f88a, 0x31802000, 0x22037608, 0x071275c8, 0x82908a93, 0x680048a5, 0x18804aa5, 
+    0x7e888005, 0xb2c21c40, 0xb2e8768a, 0x94002a01, 0xd0069001, 0x22022300, 0x2001210a, 0xf86df001, 
+    0x2300bd7c, 0x21202201, 0xb570e7f7, 0x68084998, 0x18804a98, 0x20018843, 0x430303c0, 0x8a840590, 
+    0x43e42401, 0x680d8284, 0x18ad2401, 0x8a8480ac, 0x82842400, 0x18806808, 0x21018043, 0xf001200c, 
+    0xbd70f8c2, 0xb510b40f, 0x07002003, 0x21ff8a81, 0x82810209, 0x8ee1466c, 0x0e0b07c9, 0x07c98ea1, 
+    0x430b0e49, 0x07c98e61, 0x430b0e89, 0x07c98e21, 0x430b0ec9, 0x07c98de1, 0x430b0f09, 0x07c98da1, 
+    0x430b0f49, 0x07c98d61, 0x430b0f89, 0x07c98d21, 0x430b0fc9, 0x680c4976, 0x025222d1, 0x86e318a4, 
+    0x23238a83, 0x8283029b, 0x8c63466c, 0x07db8c24, 0x0c5b07e4, 0x43230ca4, 0x8be4466c, 0x0ce407e4, 
+    0x466c4323, 0x07e48b64, 0x43230da4, 0x8b24466c, 0x0de407e4, 0x466c4323, 0x07e48ae4, 0x43230e24, 
+    0x8aa4466c, 0x0e6407e4, 0x466c4323, 0x07e48a64, 0x43230ea4, 0x8a24466c, 0x0ee407e4, 0x466c4323, 
+    0x07e489e4, 0x43230f24, 0x89a4466c, 0x0f6407e4, 0x466c4323, 0x07e48964, 0x43230fa4, 0x8924466c, 
+    0x0fe407e4, 0x680c4323, 0x872318a4, 0x23018a83, 0x828303db, 0x8ca3ac10, 0x07db8c64, 0x0c5b07e4, 
+    0x43230ca4, 0x8c24ac10, 0x0ce407e4, 0xac104323, 0x07e48be4, 0x43230d24, 0x8ba4ac10, 0x0d6407e4, 
+    0xac104323, 0x07e48b64, 0x43230da4, 0x8b24ac10, 0x0de407e4, 0xac104323, 0x07e48ae4, 0x43230e24, 
+    0x8aa4ac10, 0x0e6407e4, 0xac104323, 0x07e48a64, 0x43230ea4, 0x8a24ac10, 0x0ee407e4, 0xac104323, 
+    0x07e489e4, 0x43230f24, 0x89a4ac10, 0x0f6407e4, 0xac104323, 0x07e48964, 0x43230fa4, 0x8924ac10, 
+    0x0fe407e4, 0x680c4323, 0x876318a4, 0x230f8a83, 0x828343db, 0x8860ac10, 0x07c08823, 0x0f0007db, 
+    0x43180f5b, 0x8fe3466c, 0x07db6809, 0x43180f9b, 0x07db8fa3, 0x43180fdb, 0x87881889, 0xbc08bc10, 
+    0xb0042000, 0xb5ff4718, 0x001eb0ab, 0x46044615, 0x2700d018, 0xa8152120, 0xf86af001, 0xa8262114, 
+    0xf866f001, 0x90002000, 0x90029001, 0xa81d2124, 0xf85ef001, 0xd00a2f00, 0xdd052d12, 0x1fad2006, 
+    0xe006b2e9, 0xe7e52701, 0x2000b2e9, 0xb2e9e001, 0x9a2cb2f0, 0x1b1207c3, 0x1a121a52, 0x2201b2d5, 
+    0xd1012b00, 0xd3012806, 0x831aab20, 0xe0072802, 0x20000084, 0x0001a0c0, 0x20000090, 0x0000fffd, 
+    0xab20d301, 0x2804841a, 0xab20d304, 0x2806849a, 0x839ad300, 0x402048fe, 0xd0012801, 0xdb012c0a, 
+    0x8682a810, 0xdb012c02, 0x8182a820, 0xdb012c04, 0x80c2a820, 0xdb012c06, 0x8002a820, 0xdb042c08, 
+    0x8742a810, 0xdb002c0a, 0x07c88542, 0x2908d101, 0xa810d301, 0x29028282, 0xa810d301, 0x29048382, 
+    0xa810d301, 0x29068402, 0xa810d304, 0x29088482, 0x8302d300, 0x8d44a810, 0xd11f2c00, 0xd00107c8, 
+    0xd2192908, 0xd2172912, 0x8f40a810, 0xd1012801, 0xd211290a, 0x8800a820, 0xd1012801, 0xd20b290c, 
+    0x88c0a820, 0xd1012801, 0xd205290e, 0x8980a820, 0xd1032801, 0xd3012910, 0x8582a810, 0x8f58ab10, 
+    0x28009003, 0x290ad102, 0x879ad300, 0x8800a820, 0x28004684, 0x290cd103, 0xa820d301, 0xa8208042, 
+    0x2f0088c7, 0x290ed102, 0x8102d300, 0x2e008986, 0x2910d102, 0x81c2d300, 0x2b008e9b, 0x2912d115, 
+    0x9803d211, 0xd1012801, 0xd20c290a, 0x28014660, 0x290cd101, 0x2f01d207, 0x290ed101, 0x2e01d203, 
+    0x2910d103, 0xa810d301, 0x2d0086c2, 0x1e6dd07e, 0x07c1b2e8, 0x4669d001, 0x0840800a, 0x07c1d0f6, 
+    0x1e40d005, 0x06004669, 0x0e00804a, 0x4669d0ee, 0x29008889, 0x1e80d105, 0x06004669, 0x0e00808a, 
+    0x4669d0e4, 0x290088c9, 0x1e80d105, 0x06004669, 0x0e0080ca, 0x4669d0da, 0x29008849, 0xa920d16f, 
+    0x29008bc9, 0xa920d10d, 0x29008b89, 0x4669d109, 0x1e80804a, 0x0600a920, 0x0e0083ca, 0x2a00d0c6, 
+    0xa920d15d, 0x29008b49, 0xa920d10d, 0x29008b09, 0x4669d109, 0x1e80804a, 0x0600a920, 0x0e00834a, 
+    0x2a00d0b4, 0xa910d14b, 0x29008b49, 0xa910d10d, 0x29008b09, 0x4669d109, 0x1e80804a, 0x0600a910, 
+    0x0e00834a, 0x2a00d0a2, 0xa910d139, 0x29008ac9, 0xa910d10d, 0x29008a89, 0x4669d109, 0x1e80804a, 
+    0x0600a910, 0x0e0082ca, 0x2a00d090, 0xa910d127, 0x29008f09, 0x2b00d111, 0xa910d10f, 0x29008ec9, 
+    0x4669d10b, 0xa910804a, 0xe000870a, 0x1e80e11e, 0x0e000600, 0x2a00d08a, 0xa910d111, 0x29008dc9, 
+    0x2c00d10d, 0xa910d10b, 0x29008d89, 0x4669d107, 0x1e80804a, 0x0600a910, 0x0e0085ca, 0xa920d08a, 
+    0x29008cc9, 0xa920d109, 0x29008c89, 0x1e80d105, 0x0600a920, 0x0e0084ca, 0xa920d090, 0x29008c49, 
+    0xa920d109, 0x29008c09, 0x1e80d105, 0x0600a920, 0x0e00844a, 0xa910d094, 0x29008cc9, 0xa910d109, 
+    0x29008c89, 0x1e80d105, 0x0600a910, 0x0e0084ca, 0xa910d086, 0x29008c49, 0xa910d109, 0x29008c09, 
+    0x1e80d105, 0x0600a910, 0x0e00844a, 0xa910d08a, 0x29008bc9, 0xa910d109, 0x29008b89, 0x1e80d105, 
+    0x0600a910, 0x0e0083ca, 0xa920d08e, 0x29008a09, 0x2e00d10b, 0xa920d109, 0x290089c9, 0x1e80d105, 
+    0x0600a920, 0x0e00820a, 0xa920d094, 0x29008949, 0x2f00d10b, 0xa920d109, 0x29008909, 0x1e80d105, 
+    0x0600a920, 0x0e00814a, 0xa920d084, 0x29008889, 0x4661d10c, 0xd1092900, 0x8849a920, 0xd1052900, 
+    0xa9201e80, 0x808a0600, 0xd0870e00, 0x8fc9a910, 0xd10c2900, 0x29009903, 0xa910d109, 0x29008f89, 
+    0x1e80d105, 0x0600a910, 0x0e0087ca, 0xa920d07e, 0x29008bc9, 0xa920d13a, 0x29008b89, 0xad20d136, 
+    0x2d008b6d, 0xad20d10e, 0x2d008b2d, 0xad20d10a, 0x83ea1e80, 0x836a0600, 0xd0670e00, 0xd1252a00, 
+    0xd1232900, 0x8b6dad10, 0xd10f2d00, 0x8b2dad10, 0xd10b2d00, 0x83eaad20, 0xad101e80, 0x836a0600, 
+    0xd0530e00, 0xd1112a00, 0xd10f2900, 0x8ac9a910, 0xd10b2900, 0x8a89a910, 0xd1072900, 0x83caa920, 
+    0xa9101e80, 0x82ca0600, 0xd03f0e00, 0x8b49a920, 0xd12a2900, 0x8b09a920, 0xd1262900, 0x8b6dad10, 
+    0xd1122d00, 0x8b2dad10, 0xd10e2d00, 0xe001ad20, 0x80000001, 0x1e80836a, 0x0600ad10, 0x0e00836a, 
+    0x2a00d024, 0x2900d111, 0xa910d10f, 0x29008ac9, 0xa910d10b, 0x29008a89, 0xa920d107, 0x1e80834a, 
+    0x0600a910, 0x0e0082ca, 0xa910d010, 0x29008b49, 0xa910d114, 0x29008b09, 0xa910d110, 0x29008ac9, 
+    0xa910d10c, 0x29008a89, 0xe000d108, 0xa910e084, 0x834a1e80, 0x82ca0600, 0xd07d0e00, 0x8bc9a920, 
+    0xd12b2900, 0x8b89a920, 0xd1272900, 0x8f2dad10, 0xd1112d00, 0xd10f2b00, 0x8eedad10, 0xd10b2d00, 
+    0x83eaad20, 0xad101e80, 0x872a0600, 0xd0630e00, 0xd1132a00, 0xd1112900, 0x8dc9a910, 0xd10d2900, 
+    0xd10b2c00, 0x8d89a910, 0xd1072900, 0x83caa920, 0xa9101e80, 0x85ca0600, 0xd04d0e00, 0x8b49a920, 
+    0xd12b2900, 0x8b09a920, 0xd1272900, 0x8f2dad10, 0xd1112d00, 0xd10f2b00, 0x8eedad10, 0xd10b2d00, 
+    0x836aad20, 0xad101e80, 0x872a0600, 0xd0330e00, 0xd1132a00, 0xd1112900, 0x8dc9a910, 0xd10d2900, 
+    0xd10b2c00, 0x8d89a910, 0xd1072900, 0x834aa920, 0xa9101e80, 0x85ca0600, 0xd0740e00, 0x8b49a910, 
+    0xd12b2900, 0x8b09a910, 0xd1272900, 0x8f2dad10, 0xd1102d00, 0xd10e2b00, 0x8eedad10, 0xd10a2d00, 
+    0x1e80ad10, 0x0600836a, 0x0e00872a, 0x2a00d05b, 0x2900d114, 0xe000d112, 0xa910e055, 0x29008dc9, 
+    0x2c00d10c, 0xa910d10a, 0x29008d89, 0xa910d106, 0x834a1e80, 0x85ca0600, 0xd0440e00, 0x8ac9a910, 
+    0xd1292900, 0x8a89a910, 0xd1252900, 0x8f2dad10, 0xd1102d00, 0xd10e2b00, 0x8eedad10, 0xd10a2d00, 
+    0x1e80ad10, 0x060082ea, 0x0e00872a, 0x2a00d02b, 0x2900d112, 0xa910d110, 0x29008dc9, 0x2c00d10c, 
+    0xa910d10a, 0x29008d89, 0xa910d106, 0x82ca1e80, 0x85ca0600, 0xd0160e00, 0x8f00a810, 0xd1122800, 
+    0xd1102b00, 0x8ec0a810, 0xd10c2800, 0x8dc0a810, 0xd1082800, 0xd1062c00, 0x8d80a810, 0xd1022800, 
+    0x8702a810, 0x222285c2, 0xa80ca91d, 0xf968f7f9, 0xcb07466b, 0xc307ab09, 0xa9262214, 0xf7f9a804, 
+    0xac19f95f, 0x466ccc0f, 0xac15c40f, 0xf7ffcc0f, 0xb02ffbb9, 0xb5f8bdf0, 0x07242403, 0x4dca8aa5, 
+    0x070682a5, 0x06d50f36, 0x432e0ced, 0x682f4dc7, 0x197f4dc7, 0x8aa6813e, 0x43f6263f, 0x4fc382a6, 
+    0x683f068e, 0x197d0eb6, 0x8aa5816e, 0x82a54dc1, 0xd0052b00, 0x03652400, 0xdd032800, 0xe0022401, 
+    0xe7f82401, 0x03242400, 0x2a004325, 0x2401dd01, 0x2400e000, 0x432502e4, 0xdd012b00, 0xe0002401, 
+    0x02a42400, 0x4cb14325, 0x4fb16826, 0x19f63780, 0x25038175, 0x8aae072d, 0x43f6260f, 0x071d82ae, 
+    0x0f2d6824, 0x027626d1, 0x842519a4, 0xfc4bf7ff, 0xb5febdf8, 0x46692000, 0x48a48108, 0x4aa46801, 
+    0x18893a40, 0x68008d49, 0x300130ff, 0x46698e00, 0x20008008, 0x4684880d, 0x270c04a8, 0x28002630, 
+    0x2000da0a, 0x213c4602, 0xf7ff4663, 0x43b7ff94, 0x08b83710, 0xe0100080, 0xd51204e8, 0x20174b96, 
+    0x21162218, 0x569a5618, 0x46635659, 0xff83f7ff, 0x43b02004, 0x08803010, 0x46690080, 0x81081c40, 
+    0x06a8e0fe, 0x4a89d0fc, 0x4b896810, 0x894018c0, 0x68100681, 0x18c00e89, 0x68128900, 0x0f000700, 
+    0x891218d2, 0x04d2072b, 0x24000ed2, 0x2b010f9b, 0x2b02d002, 0xe031d018, 0x29211c49, 0x293cdb07, 
+    0x1843dc03, 0x2b3c189b, 0x1e49dd01, 0x2401e017, 0x2b211c4b, 0x2b3cdb06, 0x1843dc1e, 0x1c5b189b, 
+    0xdc192b3c, 0xe0172704, 0x1e492708, 0xdc08293c, 0xdb032921, 0x1a9b1a0b, 0xda022b06, 0xb2491c49, 
+    0x2401e00a, 0x2b3c1e4b, 0x2b21dcec, 0x1a0bdb04, 0x1e5b1a9b, 0xdae52b06, 0x811f466b, 0x0f9b06ab, 
+    0xd0022b01, 0xd01a2b02, 0x1e52e047, 0xdc072a18, 0xda052a00, 0x893b466f, 0x813b4333, 0xe03c1c52, 
+    0x1e532401, 0xdc052b18, 0xda032b00, 0x893b466f, 0xe0314333, 0x893b466f, 0x331043b3, 0x1c52e02c, 
+    0x2a18d413, 0x1843dc0a, 0x2b3c189b, 0x1a0bdc06, 0x2b061a9b, 0x1883db02, 0xdd062b18, 0x893b466f, 
+    0x332043b3, 0x1e52813b, 0x2401e017, 0xd4e11c53, 0xdc0d2b18, 0x189b1843, 0x2b3c1c5b, 0x1a0bdc08, 
+    0x1e5b1a9b, 0xdb032b06, 0x1c5b1883, 0xddd12b18, 0x893b466f, 0x332043b3, 0x07ab813b, 0x2b010f9b, 
+    0x2b02d002, 0xe04cd01d, 0x1e402603, 0xdc07280a, 0xda052800, 0x893b466f, 0x813b4333, 0xe0401c40, 
+    0x1e432401, 0xdc062b0a, 0xda042b00, 0x893b466f, 0x813b4333, 0x466ee035, 0x089b8933, 0x1c5b009b, 
+    0x1c40e02e, 0x280ad414, 0x1843dc0a, 0x2b3c189b, 0x1a0bdc06, 0x2b061a9b, 0x1883db02, 0xdd072b18, 
+    0x8933466e, 0x009b089b, 0x81331c9b, 0xe0181e40, 0x1c432401, 0x2b0ad4df, 0x1843dc0d, 0x1c5b189b, 
+    0xdc082b3c, 0x1a9b1a0b, 0x2b061e5b, 0x1883db03, 0x2b181c5b, 0x466eddcf, 0x089b8933, 0x1c9b009b, 
+    0x46638133, 0xfe87f7ff, 0xd0092c00, 0x0e8906a9, 0x91012001, 0x22044603, 0x211f9000, 0xfa7df000, 
+    0x68104a0a, 0x18c04b0a, 0x03c18980, 0x89004668, 0x0c400440, 0x05994308, 0x24008a8c, 0x6811828c, 
+    0x804818c9, 0x0000bdfe, 0x0000e0f0, 0x20000084, 0x0001a0c0, 0x0000c3ff, 0x20000200, 0xb5304770, 
+    0x6808490f, 0x18804a0f, 0x23038a02, 0x480f071b, 0x2a0f2504, 0x68004c0c, 0x829c8a9a, 0x6809d008, 
+    0x31ff2200, 0x858a3101, 0x43a98801, 0xbd308001, 0x22026809, 0x310131ff, 0x8801858a, 0xe7f54329, 
+    0x20000084, 0x0001a2c0, 0x0000fffd, 0x20000090, 0x7900482d, 0x0fc007c0, 0x482b4770, 0x228f7801, 
+    0x70014011, 0x78017901, 0x43112201, 0x47707001, 0x68804825, 0x48244770, 0xb2808900, 0x20034770, 
+    0x8a000700, 0x0d800580, 0x49204770, 0x31806809, 0x07097c89, 0x008a0e09, 0x3140491b, 0x60881851, 
+    0x228f7808, 0x30104010, 0x78087008, 0x43102201, 0x47707008, 0x68004815, 0x7c803080, 0x0e000700, 
+    0x48110081, 0x18083040, 0x22027801, 0x70014311, 0x480e4770, 0x6800490c, 0x30803140, 0x07007c80, 
+    0x00800e00, 0x68c01840, 0x48084770, 0x68004906, 0x30803140, 0x07007c80, 0x00800e00, 0x79001840, 
+    0x0fc007c0, 0x00004770, 0x300000c0, 0x20000090, 0xb672b510, 0x69c84966, 0x041222ff, 0x22014390, 
+    0x43100592, 0x496461c8, 0x60484862, 0x20006088, 0x21014a62, 0x0ee406c4, 0x40a3460b, 0x00a40944, 
+    0x602318a4, 0xb2401c40, 0xdbf3280c, 0x46202404, 0xf898f000, 0xb2641c64, 0xdbf82c0c, 0xbd10b662, 
+    0x4c57b5fe, 0x91006821, 0x4f574d56, 0x6839682e, 0x02019101, 0x07804a55, 0x60291889, 0x12fa6821, 
+    0x0b404391, 0x60214301, 0xfde3f7ff, 0x60209800, 0x9801602e, 0xbdfe6038, 0x4c49b5fe, 0x91006821, 
+    0x4f494d48, 0x6839682e, 0x02019101, 0x07804a47, 0x60291889, 0x12fa6821, 0x0b404391, 0x60214301, 
+    0xf8cef7ff, 0x60209800, 0x9801602e, 0xbdfe6038, 0x2200b510, 0x98014611, 0xf8e6f000, 0xb510bd10, 
+    0x46112200, 0xf0009801, 0xbd10f8df, 0x2200b510, 0x98014611, 0xf8d8f000, 0xb510bd10, 0x46112200, 
+    0xf0009801, 0xbd10f8d1, 0x2200b510, 0x98014611, 0xf8caf000, 0xb510bd10, 0x46112200, 0xf0009801, 
+    0xbd10f8c3, 0x7e40482a, 0x4829e79a, 0xe7977e80, 0x7ec04827, 0x4826e794, 0xe7917f00, 0x7e404824, 
+    0x4823e7aa, 0xe7a77e80, 0x7ec04821, 0x4820e7a4, 0xe7a17f00, 0x2200b510, 0x98014611, 0xf8a4f000, 
+    0xb510bd10, 0x24082004, 0xd0052900, 0xf814f000, 0xf0004620, 0xbd10f811, 0xf804f000, 0xf0004620, 
+    0xbd10f801, 0x0ed206c2, 0x40912101, 0x4a110940, 0x18800080, 0x47706001, 0x0ed206c2, 0x40912101, 
+    0x09404a0c, 0x32800080, 0x60011880, 0x00004770, 0xe000ed04, 0x80808080, 0xe000e400, 0xe000e280, 
+    0x20000084, 0x20000090, 0x30000014, 0x20000300, 0x20000200, 0xe000e100, 0x2140b510, 0xf000482b, 
+    0xbd10f9f7, 0xb51008c1, 0x281f1d09, 0xb672d813, 0x4b264a27, 0x32806812, 0x01927c92, 0x2c015c9c, 
+    0x1d09d100, 0x074418d2, 0x0f645c53, 0x40a02001, 0x54534303, 0xbd10b662, 0x491db5f0, 0x680b4e1b, 
+    0x7c993380, 0x198d0189, 0x29ff78a9, 0x786ad02c, 0xd00429fe, 0x42911a8f, 0x240dd803, 0x2402e002, 
+    0x2400e002, 0x1e64193c, 0x0e240624, 0x2c01d01c, 0x1ea0d100, 0x192c0094, 0x60e01c52, 0x280db2d0, 
+    0x2000d300, 0x01927c9a, 0x70501992, 0xd10b29fe, 0x01897c99, 0x78d1198a, 0xd1054281, 0xb2c81c49, 
+    0xd300280d, 0x70d02000, 0x0000bdf0, 0x20000264, 0x20000090, 0x2120b510, 0xf0004839, 0x2120f999, 
+    0xf0004838, 0xbd10f995, 0xf3bfb672, 0x49368f40, 0x7c0a2320, 0x740a431a, 0x8105f3ef, 0x06894a30, 
+    0x78130e89, 0x2b007011, 0x7091d10d, 0xf3ef6090, 0x60d08008, 0x8009f3ef, 0xf3ef6110, 0x61908006, 
+    0x8003f3ef, 0x200161d0, 0xd3062910, 0x39104604, 0x408c6953, 0x61534323, 0x4604e004, 0x408c6853, 
+    0x60534323, 0x70512100, 0x8f40f3bf, 0x78d1b662, 0x70d14301, 0xb5f0e7fe, 0xb6729d05, 0x8f40f3bf, 
+    0x27404c19, 0x433e7c26, 0x4c167426, 0x70207826, 0xd1092e00, 0x60a170a0, 0x8108f3ef, 0xf3ef60e1, 
+    0x61e58109, 0x612161a3, 0x28202101, 0x460dd306, 0x69633820, 0x432b4085, 0xe0046163, 0x6865460b, 
+    0x431d4083, 0x20006065, 0xf3bf7060, 0xb6628f40, 0xd0032a00, 0x430878e0, 0xe7fe70e0, 0x0000bdf0, 
+    0x20000224, 0x20000244, 0x20000200, 0x4b4bb570, 0x5e59210a, 0x4c4a2200, 0xe00a4d4a, 0x546e5ca6, 
+    0x1c521e40, 0xb2091e49, 0xb2d2b2c0, 0xda002900, 0x280021ff, 0x8159d1f2, 0xb5ffbd70, 0x4605b081, 
+    0x9e0b9804, 0xd1002800, 0x493cb672, 0x28ff7b48, 0x894bd102, 0xd3012b08, 0xe0002401, 0x9b022400, 
+    0x2bfd1e5b, 0x2c00d252, 0x4934d050, 0x29007d49, 0x2d01d14c, 0x2d00d002, 0xe004d003, 0x68004832, 
+    0x42907940, 0xf7ffd342, 0x4607fdb3, 0x482f0c01, 0x0c006800, 0x04001a08, 0xd0120c00, 0x22ff4928, 
+    0x0a02708a, 0x7008704a, 0xf7ff2003, 0x4823ffaf, 0x29ff7b41, 0x8940d104, 0xd2012808, 0xe0002400, 
+    0x48222401, 0x60072c00, 0x2d01d020, 0x2d00d024, 0x2408d027, 0x2800980a, 0x4819d008, 0x70060a31, 
+    0x0c317041, 0x980a7081, 0xff90f7ff, 0x4914980a, 0x01401d00, 0x70c84320, 0x88004814, 0x708a0a02, 
+    0x98027048, 0x20047008, 0xff80f7ff, 0x28009804, 0xb662d100, 0xbdf0b005, 0x6800480b, 0x7c843080, 
+    0x240fe7d8, 0xb51ce7d6, 0x2100460a, 0x460b9100, 0x46019101, 0xf7ff2001, 0xbd1cff80, 0x20000200, 
+    0x2000008c, 0x20000100, 0x20000090, 0x20000088, 0x490eb530, 0x78092000, 0x1e4c4d0b, 0x0202e011, 
+    0x32801952, 0x28007490, 0x1e43d005, 0x42a07513, 0x2300d103, 0x4623e002, 0x1c43e7f8, 0x74d31c40, 
+    0x4288b2c0, 0xbd30d3eb, 0x20000300, 0x20000080, 0xb5f84770, 0xd32c2a04, 0xd0120783, 0x1c49780b, 
+    0x1c407003, 0x07831e52, 0x780bd00b, 0x70031c49, 0x1e521c40, 0xd0040783, 0x1c49780b, 0x1c407003, 
+    0x078b1e52, 0xd0050f9b, 0x00df1ac9, 0x1bde2320, 0xe00ac908, 0xfc84f7f8, 0x461dbdf8, 0x40fdc908, 
+    0x40b4461c, 0xc010432c, 0x2a041f12, 0x08f3d2f5, 0x1e521ac9, 0x780bd4f0, 0x70031c49, 0x1e521c40, 
+    0x780bd4ea, 0x70031c49, 0x2a011c40, 0x7809d4e4, 0xbdf87001, 0xc004e001, 0x29041f09, 0x078bd2fb, 
+    0x8002d501, 0x07c91c80, 0x7002d000, 0x29004770, 0x07c3d00b, 0x7002d002, 0x1e491c40, 0xd3042902, 
+    0xd5020783, 0x1c808002, 0xe7e31e89, 0xe7ee2200, 0xe7df2200, 0x78c27803, 0x78434619, 0x021b0612, 
+    0x78834319, 0x041b78c0, 0x43114319, 0x0a090209, 0x43080600, 0x22004770, 0x428b0903, 0x0a03d32c, 
+    0xd311428b, 0x469c2300, 0x4603e04e, 0xd43c430b, 0x08432200, 0xd331428b, 0x428b0903, 0x0a03d31c, 
+    0xd301428b, 0xe03f4694, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 
+    0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 
+    0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 
+    0x41524601, 0x47704610, 0x0fcae05d, 0x4249d000, 0xd3001003, 0x40534240, 0x469c2200, 0x428b0903, 
+    0x0a03d32d, 0xd312428b, 0x018922fc, 0x0a03ba12, 0xd30c428b, 0x11920189, 0xd308428b, 0x11920189, 
+    0xd304428b, 0xd03a0189, 0xe0001192, 0x09c30989, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 
+    0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 
+    0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, 0x1ac0008b, 0xd2d94152, 0x428b0843, 0x004bd301, 
+    0x41521ac0, 0xd2001a41, 0x46634601, 0x105b4152, 0xd3014610, 0x2b004240, 0x4249d500, 0x46634770, 
+    0xd300105b, 0xb5014240, 0x46c02000, 0xbd0246c0, 0x46754770, 0xf822f000, 0x000546ae, 0x46534669, 
+    0x00c008c0, 0xb0184685, 0xf7f8b520, 0xbc60fba9, 0x08492700, 0x260046b6, 0xc5c0c5c0, 0xc5c0c5c0, 
+    0xc5c0c5c0, 0xc5c0c5c0, 0x00493d40, 0x4770468d, 0x46c04604, 0x462046c0, 0xfb5bf7f8, 0x47704800, 
+    0x20000094, 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200, 0x005b5d63, 0xbc3018e3, 0x19194718, 
+    0x19191919, 0x18191919, 0x18181818, 0x19191818, 0x221a1919, 0x25242322, 0x29282726, 0x2d2c2b2a, 
+    0x30302f2e, 0x32323131, 0x20421021, 0x81084084, 0x24621231, 0x918848c4, 0x000a0000, 0x001f0015, 
+    0x00340029, 0x0049003e, 0x005d0053, 0x00720068, 0x0087007c, 0x009b0091, 0x00b000a6, 0x00c500ba, 
+    0x00da00cf, 0x00ee00e4, 0x010300f9, 0x0118010d, 0x012c0122, 0x01410137, 0x00110000, 0x00340023, 
+    0x00570046, 0x007a0069, 0x009d008c, 0x00c000af, 0x00e300d2, 0x010600f5, 0x01290118, 0x014c013b, 
+    0x016f015d, 0x01920180, 0x01b501a3, 0x01d801c6, 0x01fb01e9, 0x021e020c, 0x00007c5c, 0x20000080, 
+    0x00000014, 0x000001c4, 0x00007c70, 0x20000094, 0x0000036c, 0x000001e0, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
diff --git a/drivers/net/bcmbca/phy/brcm_rgmii.c b/drivers/net/bcmbca/phy/brcm_rgmii.c
new file mode 100644
index 0000000000..21cd839b44
--- /dev/null
+++ b/drivers/net/bcmbca/phy/brcm_rgmii.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2019 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#include "dt_access.h"
+#include "access_macros.h"
+
+#ifdef __UBOOT__
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <dm/read.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#else
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#endif
+
+static void __iomem *rgmii_base;
+static void __iomem *gpio_base;
+
+#define RGMII_CTRL_REG              (rgmii_base + 0x0000)
+#define RGMII_RX_CLOCK_DELAY_CNTRL  (rgmii_base + 0x0008)
+
+#define GPIO_PAD_CTRL               (gpio_base + 0x0040)
+#define GPIO_TestPortBlkDataMsb     (gpio_base + 0x0054)
+#define GPIO_TestPortBlkDataLsb     (gpio_base + 0x0058)
+#define GPIO_TestPortCommand        (gpio_base + 0x005c)
+
+#define LOAD_PAD_CTRL_CMD           0x22
+
+static void bcm_set_padctrl(unsigned int pin_num, unsigned int pad_ctrl)
+{
+    unsigned int tp_blk_data_msb, tp_blk_data_lsb, tp_cmd;
+
+    printk("set RGMII pad ctrl for GPIO %d to 0x%08x\n", pin_num, pad_ctrl);
+    tp_cmd = LOAD_PAD_CTRL_CMD;
+    tp_blk_data_msb = 0;
+    tp_blk_data_lsb = 0;
+    tp_blk_data_lsb |= pin_num;
+    tp_blk_data_lsb |= pad_ctrl;
+
+    WRITE_32(GPIO_TestPortBlkDataMsb, tp_blk_data_msb);
+    WRITE_32(GPIO_TestPortBlkDataLsb, tp_blk_data_lsb);
+    WRITE_32(GPIO_TestPortCommand, tp_cmd);
+}
+
+static void bcm_misc_hw_xmii_pads_init(int rgmii_pins[], int num_pins)
+{
+    int num;
+    uint32_t tp_data;
+    uint32_t pad_ctrl;
+    uint32_t pad_sel = 3; /* 8mA */
+
+    READ_32(GPIO_PAD_CTRL, pad_ctrl);
+    pad_ctrl |= (1 << 8); /* rgmii_0_pad_modehv = 1 */
+    WRITE_32(GPIO_PAD_CTRL, pad_ctrl);
+
+    for (num = 0; num < num_pins ;num++)
+    {
+        tp_data = 0;
+        tp_data |= (pad_sel << 12);
+        tp_data |= ((num < 6 ? 0 : 1) << 16);
+
+        bcm_set_padctrl(rgmii_pins[num], tp_data);
+    }
+}
+
+int rgmii_attach(uint32_t port, int delay_rx, int delay_tx, int is_1p8v, int rgmii_pins[], int num_pins)
+{
+    uint32_t val;
+
+    if (!rgmii_base || !gpio_base)
+        return -1;
+
+    READ_32(RGMII_CTRL_REG, val);
+    val |= (1 << 0); /* RGMII_MODE_EN=1 */
+    val &= ~(7 << 2); /* Clear PORT_MODE */
+    val |= (3 << 2); /* RGMII mode */
+
+    if (delay_tx)
+        val &= ~(1 << 1); /* ID_MODE_DIS=0 */
+    else
+        val |= (1 << 1); /* ID_MODE_DIS=1 */
+
+    WRITE_32(RGMII_CTRL_REG, val);
+
+    if (delay_rx)
+        val = 0x08;
+    else
+        val = 0x28;
+
+    WRITE_32(RGMII_RX_CLOCK_DELAY_CNTRL, val);
+
+    bcm_misc_hw_xmii_pads_init(rgmii_pins, num_pins);
+
+    return 0;
+}
+EXPORT_SYMBOL(rgmii_attach);
+ 
+static int rgmii_probe(dt_device_t *pdev)
+{
+    int ret;
+
+    rgmii_base = dt_dev_remap_resource(pdev, 0);
+    if (IS_ERR(rgmii_base))
+    {
+        ret = PTR_ERR(rgmii_base);
+        goto Exit;
+    }
+
+    gpio_base = dt_dev_remap(pdev, 1);
+    if (IS_ERR(gpio_base))
+    {
+        ret = PTR_ERR(gpio_base);
+        goto Exit;
+    }
+
+    dev_info(&pdev->dev, "registered\n");
+
+    return 0;
+
+Exit:
+    gpio_base = NULL;
+    rgmii_base = NULL;
+    return ret;
+}
+
+#ifdef __UBOOT__
+static const struct udevice_id rgmii_ids[] = {
+    { .compatible = "brcm,rgmii1" },
+    { /* end of list */ },
+};
+
+U_BOOT_DRIVER(brcm_rgmii) = {
+    .name	= "brcm-rgmii",
+    .id	= UCLASS_MISC,
+    .of_match = rgmii_ids,
+    .probe = rgmii_probe,
+};
+#else
+static const struct of_device_id of_platform_table[] = {
+    { .compatible = "brcm,rgmii1" },
+    { /* end of list */ },
+};
+
+static struct platform_driver of_platform_driver = {
+    .driver = {
+        .name = "brcm-rgmii",
+        .of_match_table = of_platform_table,
+    },
+    .probe = rgmii_probe,
+};
+
+module_platform_driver(of_platform_driver);
+#endif
+
diff --git a/drivers/net/bcmbca/phy/brcm_rgmii.h b/drivers/net/bcmbca/phy/brcm_rgmii.h
new file mode 100644
index 0000000000..a20d973a92
--- /dev/null
+++ b/drivers/net/bcmbca/phy/brcm_rgmii.h
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2019 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef _BRCM_RGMII_H_
+#define _BRCM_RGMII_H_
+
+#ifndef BRCM_RGMII
+static inline
+#endif
+int rgmii_attach(uint32_t port, int delay_rx, int delay_tx, int is_1p8v, int rgmii_pins[], int num_pins)
+#ifndef BRCM_RGMII
+{ return 0; }
+#endif
+;
+
+#endif
+
diff --git a/drivers/net/bcmbca/phy/bus_drv.c b/drivers/net/bcmbca/phy/bus_drv.c
new file mode 100644
index 0000000000..0d29219f62
--- /dev/null
+++ b/drivers/net/bcmbca/phy/bus_drv.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#include "bus_drv.h"
+
+extern bus_drv_t bus_6858_lport_drv;
+extern bus_drv_t bus_mdio_v1_int_drv;
+extern bus_drv_t bus_mdio_v1_ext_drv;
+extern bus_drv_t bus_47189_gmac0_drv;
+extern bus_drv_t bus_47189_gmac1_drv;
+extern bus_drv_t bus_i2c_drv;
+extern bus_drv_t bus_sf2_ethsw_drv;
+extern bus_drv_t bus_sf2_c45_drv;
+
+bus_drv_t *bus_drv_get(bus_type_t bus_type)
+{
+    bus_drv_t *bus_drv = NULL;
+
+    switch (bus_type)
+    {
+#ifdef CONFIG_BCM96858
+    case BUS_TYPE_6858_LPORT:
+        bus_drv = &bus_6858_lport_drv;
+        break;
+#endif
+#if defined(CONFIG_BCM96846) || defined(CONFIG_BCM96856) || defined(CONFIG_BCM96878) || defined(CONFIG_BCM63146) || defined(CONFIG_BCM4912)     
+#if defined(CONFIG_BCM63146) || defined(CONFIG_BCM4912) 
+    case BUS_TYPE_DSL_ETHSW: //FIXME! redirect to mdio_v1_int for now
+#endif
+    case BUS_TYPE_MDIO_V1_INT:
+        bus_drv = &bus_mdio_v1_int_drv;
+        break;
+    case BUS_TYPE_MDIO_V1_EXT:
+        bus_drv = &bus_mdio_v1_ext_drv;
+        break;
+#endif
+       
+#ifdef CONFIG_BCM947189
+    case BUS_TYPE_47189_GMAC0:
+        bus_drv = &bus_47189_gmac0_drv;
+        break;
+    case BUS_TYPE_47189_GMAC1:
+        bus_drv = &bus_47189_gmac1_drv;
+        break;
+#endif
+#if defined(DSL_DEVICES)
+#if defined(CONFIG_I2C) && !defined(CONFIG_I2C_GPIO)
+    case BUS_TYPE_DSL_I2C:
+        bus_drv = &bus_i2c_drv;
+        break;
+#endif
+    case BUS_TYPE_DSL_ETHSW:
+        bus_drv = &bus_sf2_ethsw_drv;
+        break;
+#endif
+    default:
+        break;
+    }
+
+    return bus_drv;
+}
+EXPORT_SYMBOL(bus_drv_get);
+
+#define str(x) #x
+#define match(x, _bus_type_str) do { \
+    if (!strcmp(str(x) + strlen("BUS_TYPE_"), _bus_type_str)) \
+        return bus_drv_get(x); \
+    } while (0);
+
+bus_drv_t *bus_drv_get_by_str(char *bus_type_str)
+{
+    match(BUS_TYPE_6858_LPORT, bus_type_str);
+    match(BUS_TYPE_MDIO_V1_INT, bus_type_str);
+    match(BUS_TYPE_MDIO_V1_EXT, bus_type_str);
+    match(BUS_TYPE_47189_GMAC0, bus_type_str);
+    match(BUS_TYPE_47189_GMAC1, bus_type_str);
+    match(BUS_TYPE_DSL_ETHSW, bus_type_str);
+    match(BUS_TYPE_DSL_I2C, bus_type_str);
+
+    return NULL;
+}
+
diff --git a/drivers/net/bcmbca/phy/bus_drv.h b/drivers/net/bcmbca/phy/bus_drv.h
new file mode 100644
index 0000000000..b85d5e897e
--- /dev/null
+++ b/drivers/net/bcmbca/phy/bus_drv.h
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#ifndef __BUS_DRV_H__
+#define __BUS_DRV_H__
+
+#include "os_dep.h"
+
+typedef enum
+{
+    BUS_TYPE_UNKNOWN,
+    BUS_TYPE_6858_LPORT,
+    BUS_TYPE_MDIO_V1_INT,
+    BUS_TYPE_MDIO_V1_EXT,
+    BUS_TYPE_47189_GMAC0,
+    BUS_TYPE_47189_GMAC1,
+    BUS_TYPE_DSL_ETHSW,
+    BUS_TYPE_DSL_I2C,
+} bus_type_t;
+
+typedef struct bus_drv_t
+{
+    int (*c22_read)(uint32_t addr, uint16_t reg, uint16_t *val);
+    int (*c22_write)(uint32_t addr, uint16_t reg, uint16_t val);
+    int (*c45_read)(uint32_t addr, uint16_t dev, uint16_t reg, uint16_t *val);
+    int (*c45_write)(uint32_t addr, uint16_t dev, uint16_t reg, uint16_t val);
+    bus_type_t bus_type;
+} bus_drv_t;
+
+bus_drv_t *bus_drv_get(bus_type_t bus_type);
+
+static inline int bus_read(bus_drv_t *bus_drv, uint32_t addr, uint16_t reg, uint16_t *val)
+{
+    return bus_drv->c22_read(addr, reg, val);
+}
+
+static inline int bus_write(bus_drv_t *bus_drv, uint32_t addr, uint16_t reg, uint16_t val)
+{
+    return bus_drv->c22_write(addr, reg, val);
+}
+
+static inline int bus_c45_read(bus_drv_t *bus_drv, uint32_t addr, uint16_t dev, uint16_t reg, uint16_t *val)
+{
+    return bus_drv->c45_read(addr, dev, reg, val);
+}
+
+static inline int bus_c45_write(bus_drv_t *bus_drv, uint32_t addr, uint16_t dev, uint16_t reg, uint16_t val)
+{
+    return bus_drv->c45_write(addr, dev, reg, val);
+}
+
+#endif
diff --git a/drivers/net/bcmbca/phy/bus_drv_6858.c b/drivers/net/bcmbca/phy/bus_drv_6858.c
new file mode 100644
index 0000000000..835eed9e5c
--- /dev/null
+++ b/drivers/net/bcmbca/phy/bus_drv_6858.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#include "bus_drv.h"
+#include "lport_mdio.h"
+
+/* LPORT MDIO bus */
+static int bus_6858_lport_c22_read(uint32_t addr, uint16_t reg, uint16_t *val)
+{
+    return lport_mdio22_rd(addr, reg, val);
+}
+
+static int bus_6858_lport_c22_write(uint32_t addr, uint16_t reg, uint16_t val)
+{
+    return lport_mdio22_wr(addr, reg, val);
+}
+
+static int bus_6858_lport_c45_read(uint32_t addr, uint16_t dev, uint16_t reg, uint16_t *val)
+{
+    return lport_mdio45_rd(addr, dev, reg, val);
+}
+
+static int bus_6858_lport_c45_write(uint32_t addr, uint16_t dev, uint16_t reg, uint16_t val)
+{
+    return lport_mdio45_wr(addr, dev, reg, val);
+}
+
+bus_drv_t bus_6858_lport_drv =
+{
+    .c22_read = bus_6858_lport_c22_read,
+    .c22_write = bus_6858_lport_c22_write,
+    .c45_read = bus_6858_lport_c45_read,
+    .c45_write = bus_6858_lport_c45_write,
+};
diff --git a/drivers/net/bcmbca/phy/bus_drv_mdio_v1.c b/drivers/net/bcmbca/phy/bus_drv_mdio_v1.c
new file mode 100644
index 0000000000..75ac8c8191
--- /dev/null
+++ b/drivers/net/bcmbca/phy/bus_drv_mdio_v1.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Aug 2017
+ *      Author: dima.mamut@broadcom.com
+ */
+
+#include "bus_drv.h"
+#include "mdio_drv_impl5.h"
+
+/* Internal MDIO bus */
+static int bus_mdio_v1_int_c22_read(uint32_t addr, uint16_t reg, uint16_t *val)
+{
+    return mdio_read_c22_register(MDIO_INT, addr, reg, val);
+}
+
+static int bus_mdio_v1_int_c22_write(uint32_t addr, uint16_t reg, uint16_t val)
+{
+    return mdio_write_c22_register(MDIO_INT, addr, reg, val);
+}
+
+static int bus_mdio_v1_int_c45_read(uint32_t addr, uint16_t dev, uint16_t reg, uint16_t *val)
+{
+    return mdio_read_c45_register(MDIO_INT, addr, dev, reg, val);
+}
+
+static int bus_mdio_v1_int_c45_write(uint32_t addr, uint16_t dev, uint16_t reg, uint16_t val)
+{
+    return mdio_write_c45_register(MDIO_INT, addr, dev, reg, val);
+}
+
+bus_drv_t bus_mdio_v1_int_drv =
+{
+    .c22_read = bus_mdio_v1_int_c22_read,
+    .c22_write = bus_mdio_v1_int_c22_write,
+    .c45_read = bus_mdio_v1_int_c45_read,
+    .c45_write = bus_mdio_v1_int_c45_write,
+};
+
+
+/* External MDIO bus */
+static int bus_mdio_v1_ext_c22_read(uint32_t addr, uint16_t reg, uint16_t *val)
+{
+    return mdio_read_c22_register(MDIO_EXT, addr, reg, val);
+}
+
+static int bus_mdio_v1_ext_c22_write(uint32_t addr, uint16_t reg, uint16_t val)
+{
+    return mdio_write_c22_register(MDIO_EXT, addr, reg, val);
+}
+
+static int bus_mdio_v1_ext_c45_read(uint32_t addr, uint16_t dev, uint16_t reg, uint16_t *val)
+{
+    return mdio_read_c45_register(MDIO_EXT, addr, dev, reg, val);
+}
+
+static int bus_mdio_v1_ext_c45_write(uint32_t addr, uint16_t dev, uint16_t reg, uint16_t val)
+{
+    return mdio_write_c45_register(MDIO_EXT, addr, dev, reg, val);
+}
+
+bus_drv_t bus_mdio_v1_ext_drv =
+{
+    .c22_read = bus_mdio_v1_ext_c22_read,
+    .c22_write = bus_mdio_v1_ext_c22_write,
+    .c45_read = bus_mdio_v1_ext_c45_read,
+    .c45_write = bus_mdio_v1_ext_c45_write,
+};
diff --git a/drivers/net/bcmbca/phy/dt_access.c b/drivers/net/bcmbca/phy/dt_access.c
new file mode 100644
index 0000000000..f632d121f0
--- /dev/null
+++ b/drivers/net/bcmbca/phy/dt_access.c
@@ -0,0 +1,215 @@
+#include "dt_access.h"
+
+const bool dt_is_available(const dt_handle_t handle)
+{
+#ifdef __UBOOT__
+    return ofnode_is_available(handle);
+#else
+    return of_device_is_available(handle);
+#endif
+}
+
+const bool dt_is_valid(const dt_handle_t handle)
+{
+#ifdef __UBOOT__
+    return ofnode_valid(handle);
+#else
+    return handle ? 1 : 0;
+#endif
+}
+
+const dt_handle_t dt_parent(const dt_handle_t handle)
+{
+#ifdef __UBOOT__
+    return ofnode_get_parent(handle);
+#else
+    return of_get_parent(handle);
+#endif
+}
+
+const bool dt_is_equal(const dt_handle_t handle1, const dt_handle_t handle2)
+{
+#ifdef __UBOOT__
+    return ofnode_equal(handle1, handle2);
+#else
+    return handle1 == handle2;
+#endif
+}
+
+const dt_handle_t dt_parse_phandle(const dt_handle_t handle, const char *phandle_name, int index)
+{
+#ifdef __UBOOT__
+    ofnode node = ofnode_null();
+    struct ofnode_phandle_args out_args;
+
+    if (ofnode_parse_phandle_with_args(handle, phandle_name, NULL, 0, index, &out_args) == 0)
+        node = out_args.node;
+
+    return node;
+#else
+    return of_parse_phandle(handle, phandle_name, index);
+#endif
+}
+
+const dt_handle_t dt_find_compatible_node(dt_handle_t handle, const char *compat)
+{
+#ifdef __UBOOT__
+    return ofnode_by_compatible(handle, compat);
+#else
+    return of_find_compatible_node(handle, NULL, compat);
+#endif
+}
+
+const void *dt_get_property(const dt_handle_t handle, const char *propname, int *lenp)
+{
+#ifdef __UBOOT__
+    return ofnode_get_property(handle, propname, lenp);
+#else
+    return of_get_property(handle, propname, lenp);
+#endif
+}
+
+const bool dt_property_read_bool(const dt_handle_t handle, const char *propname)
+{
+    return dt_get_property(handle, propname, NULL) ? 1 : 0;
+}
+
+const uint32_t dt_property_read_u32(const dt_handle_t handle, const char *propname)
+{
+    uint32_t *val = dt_get_property(handle, propname, NULL);
+
+    if (!val)
+        return -1;
+
+    return be32_to_cpup(val);
+}
+
+const uint32_t dt_property_read_u32_default(const dt_handle_t handle, const char *propname, uint32_t defval)
+{
+    uint32_t *val = dt_get_property(handle, propname, NULL);
+
+    if (!val)
+        return defval;
+
+    return be32_to_cpup(val);
+}
+
+const char *dt_property_read_string(const dt_handle_t handle, const char *propname)
+{
+    return dt_get_property(handle, propname, NULL);
+}
+
+const char *dt_get_name(const dt_handle_t handle)
+{
+#ifdef __UBOOT__
+    return ofnode_get_name(handle);
+#else
+    return of_node_full_name(handle);
+#endif
+}
+
+int dt_gpio_request_by_name_optional(const dt_handle_t handle, const char *propname, int index, const char *label, dt_gpio_desc *desc)
+{
+#ifdef __UBOOT__
+    int ret;
+
+    ret = gpio_request_by_name_nodev(handle, propname, index, desc, GPIOD_IS_OUT);
+    if (ret == -ENOENT)
+        return 0;
+
+    return ret;
+#else
+    /* XXX: Silently do not support Kernel 4.1 - remove after testing */
+#include <linux/version.h>
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,19,0))
+    *desc = gpiod_get_from_of_node(handle, propname, index, GPIOD_ASIS, label);
+    if (PTR_ERR(*desc) == -ENOENT || PTR_ERR(*desc) == -ENOSYS)
+    {
+        *desc = NULL;
+        return 0;
+    }
+
+    if (IS_ERR(desc))
+         return PTR_ERR(desc);
+
+    return 0;
+#else
+    *desc = NULL;
+    return 0;
+#endif
+#endif
+}
+
+void dt_gpio_set_value(dt_gpio_desc desc, int value)
+{
+#ifdef __UBOOT__
+    dm_gpio_set_value(&desc, value);
+#else
+    gpiod_set_value(desc, value);
+#endif
+}
+
+void dt_gpio_set_direction_output(dt_gpio_desc desc, int value)
+{
+#ifdef __UBOOT__
+    dm_gpio_set_dir_flags(&desc, value ? GPIOD_IS_OUT : GPIOD_IS_IN);
+#else
+    gpiod_direction_output(desc, value);
+#endif
+}
+
+int dt_gpio_exists(dt_gpio_desc desc)
+{
+#ifdef __UBOOT__
+    return !!desc.dev;
+#else
+    return !!desc;
+#endif
+}
+
+dt_handle_t dt_dev_get_handle(dt_device_t *pdev)
+{
+#ifdef __UBOOT__
+    return pdev->node;
+#else
+    return pdev->dev.of_node;
+#endif
+}
+
+void *dt_dev_read_addr(dt_device_t *pdev, int index)
+{
+#ifdef __UBOOT__
+    return dev_read_addr_index(pdev, index);
+#else
+    struct resource *res;
+
+    res = platform_get_resource(pdev, IORESOURCE_MEM, index);
+    return res->start;
+#endif
+}
+
+void *dt_dev_remap(dt_device_t *pdev, int index)
+{
+#ifdef __UBOOT__
+    return dev_remap_addr_index(pdev, index);
+#else
+    struct resource *res;
+    resource_size_t size;
+
+    res = platform_get_resource(pdev, IORESOURCE_MEM, index);
+    size = resource_size(res);
+    return devm_ioremap(&pdev->dev, res->start, size);
+#endif
+}
+
+void *dt_dev_remap_resource(dt_device_t *pdev, int index)
+{
+#ifdef __UBOOT__
+    return dev_remap_addr_index(pdev, index);
+#else
+    struct resource *res;
+
+    res = platform_get_resource(pdev, IORESOURCE_MEM, index);
+    return devm_ioremap_resource(&pdev->dev, res);
+#endif
+}
diff --git a/drivers/net/bcmbca/phy/dt_access.h b/drivers/net/bcmbca/phy/dt_access.h
new file mode 100644
index 0000000000..f641964424
--- /dev/null
+++ b/drivers/net/bcmbca/phy/dt_access.h
@@ -0,0 +1,59 @@
+#ifndef __DT_ACCESS_H__
+#define __DT_ACCESS_H__
+
+#ifdef __UBOOT__
+#include <dm/ofnode.h>
+#include <dm/of_access.h>
+#include <dm/device.h>
+#include <dm/read.h>
+#include <asm-generic/gpio.h>
+#include <linux/errno.h>
+typedef ofnode dt_handle_t;
+typedef struct udevice dt_device_t;
+typedef struct gpio_desc dt_gpio_desc;
+#else
+#include "linux/of.h"
+#include <linux/gpio/consumer.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/module.h>
+typedef struct device_node * dt_handle_t;
+typedef struct platform_device dt_device_t;
+extern struct gpio_desc *gpiod_get_from_of_node(struct device_node *node,
+        const char *propname, int index,
+        enum gpiod_flags dflags,
+        const char *label);
+typedef struct gpio_desc *dt_gpio_desc;
+#endif
+
+#ifdef __UBOOT__
+#define dt_for_each_child_of_node(parent, child)  ofnode_for_each_subnode(child, parent)
+#else
+#define dt_for_each_child_of_node(parent, child)  for_each_child_of_node(parent, child)
+#endif
+
+const bool dt_is_available(const dt_handle_t handle);
+const bool dt_is_valid(const dt_handle_t handle);
+const dt_handle_t dt_parent(const dt_handle_t handle);
+const bool dt_is_equal(const dt_handle_t handle1, const dt_handle_t handle2);
+const dt_handle_t dt_parse_phandle(const dt_handle_t handle, const char *phandle_name, int index);
+const dt_handle_t dt_find_compatible_node(dt_handle_t handle, const char *compat);
+const void *dt_get_property(const dt_handle_t handle, const char *propname, int *lenp);
+const bool dt_property_read_bool(const dt_handle_t handle, const char *propname);
+const char *dt_property_read_string(const dt_handle_t handle, const char *propname);
+/* Note that if property is not found, return value will be -1 (0xffffffff) */
+const uint32_t dt_property_read_u32(const dt_handle_t handle, const char *propname);
+const uint32_t dt_property_read_u32_default(const dt_handle_t handle, const char *propname, uint32_t defval);
+const char *dt_get_name(const dt_handle_t handle);
+int dt_gpio_request_by_name_optional(const dt_handle_t handle, const char *propname, int index, const char *label, dt_gpio_desc *desc);
+void dt_gpio_set_value(dt_gpio_desc desc, int value);
+void dt_gpio_set_direction_output(dt_gpio_desc desc, int value);
+int dt_gpio_exists(dt_gpio_desc desc);
+
+dt_handle_t dt_dev_get_handle(dt_device_t *pdev);
+void *dt_dev_read_addr(dt_device_t *pdev, int index);
+void *dt_dev_remap(dt_device_t *pdev, int index);
+void *dt_dev_remap_resource(dt_device_t *pdev, int index);
+
+#endif
+
diff --git a/drivers/net/bcmbca/phy/dt_parsing.c b/drivers/net/bcmbca/phy/dt_parsing.c
new file mode 100644
index 0000000000..c33c608437
--- /dev/null
+++ b/drivers/net/bcmbca/phy/dt_parsing.c
@@ -0,0 +1,571 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2019 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Oct 2019
+ *      Author: ido.brezel@broadcom.com
+ */
+
+#include "phy_drv.h"
+#include "mac_drv.h"
+#include "dt_access.h"
+
+#ifdef __UBOOT__
+#include <dm/device.h>
+#include <dm/uclass.h>
+#if defined(CONFIG_BCM_BCA_LED)
+#include "bcm_bca_leds.h"
+#endif
+#else
+#include <linux/of_platform.h>
+#endif
+#include "brcm_rgmii.h"
+
+extern phy_drv_t *phy_drivers[PHY_TYPE_MAX];
+
+static phy_type_t phy_type_get_by_str(const char *phy_type_str)
+{
+    phy_drv_t *phy_drv;
+    int i;
+
+    for (i = 0; i < PHY_TYPE_MAX; i++)
+    {
+        phy_drv = phy_drivers[i];
+        if (phy_drv && strstr(phy_drv->name, phy_type_str))
+            return i;
+    }
+
+    return PHY_TYPE_UNKNOWN;
+}
+
+static int phy_drv_dt_priv(phy_type_t phy_type, const dt_handle_t handle, uint32_t addr, uint32_t phy_mode, void **_priv)
+{
+    phy_drv_t *phy_drv = phy_drivers[phy_type];
+
+    if (!phy_drv)
+    {
+        printk("Failed to find phy driver: phy_type=%d\n", phy_type);
+        return -1;
+    }
+
+    if (!phy_drv->dt_priv)
+        return 0;
+
+    return phy_drv->dt_priv(handle, addr, phy_mode, _priv);
+}
+
+static int parse_caps_mask(phy_mii_type_t mii_type)
+{
+    int caps_mask = PHY_CAP_ALL;
+
+    if (mii_type < PHY_MII_TYPE_XFI)
+        caps_mask &= ~(PHY_CAP_10000 | PHY_CAP_5000);
+
+    if (mii_type < PHY_MII_TYPE_HSGMII)
+        caps_mask &= ~PHY_CAP_2500;
+
+    if (mii_type < PHY_MII_TYPE_GMII)
+        caps_mask &= ~(PHY_CAP_1000_HALF | PHY_CAP_1000_FULL);
+
+    return caps_mask;
+}
+
+static int parse_reset_gpio(const dt_handle_t handle, phy_dev_t *phy_dev)
+{
+    return dt_gpio_request_by_name_optional(handle, "phy-reset", 0, "PHY reset", &phy_dev->reset_gpiod);
+}
+
+phy_mii_type_t dt_get_phy_mode_mii_type(const dt_handle_t handle)
+{
+    int i;
+    const char *phy_mode_str = dt_property_read_string(handle, "phy-mode");
+
+    if (!phy_mode_str)
+        goto Exit;
+
+    for (i = PHY_MII_TYPE_UNKNOWN; i < PHY_MII_TYPE_LAST; i++)
+    {
+        if (!strcasecmp(phy_mode_str, phy_mii_type(i)))
+            return i;
+    }
+
+Exit:
+    return PHY_MII_TYPE_UNKNOWN;
+}
+EXPORT_SYMBOL(dt_get_phy_mode_mii_type);
+
+bus_drv_t *bus_drv_get_by_str(const char *bus_type_str);
+
+static phy_dev_t *phy_dev_dt_probe(const dt_handle_t handle)
+{
+    phy_dev_t *phy_dev = NULL, *phy_dev_next = NULL;
+    void *priv = NULL;
+    uint32_t addr;
+    const phy_type_t phy_type = phy_type_get_by_str(dt_property_read_string(handle, "phy-type"));
+    dt_handle_t phy;
+
+#if (defined(CONFIG_BCM63146) || defined(CONFIG_BCM4912))
+    // FIXME_DT: only support uboot on QGPHY & SGPHY for now
+    if (phy_type != PHY_TYPE_63146_EGPHY)
+        goto Exit; 
+#endif
+
+    if (phy_type == PHY_TYPE_UNKNOWN)
+    {
+        printk("Missing or wrong phy-type entry\n");
+        goto Exit;
+    }
+
+    addr = dt_property_read_u32(handle, "reg");
+    if (addr == (uint32_t)(-1))
+    {
+        printk("Missing reg entry\n");
+        goto Exit;
+    }
+
+    phy = dt_parse_phandle(handle, "phy-handle", 0);
+    if (dt_is_valid(phy))
+    {
+        if (!(phy_dev_next = phy_drv_find_device(phy)))
+        {
+            printk("phy_dev probe_defer: %s waiting for phy %s\n", dt_get_name(handle), dt_get_name(phy));
+            return ERR_PTR(-EPROBE_DEFER);
+        }
+    }
+
+    /* XXX: phy_drv_dt_priv API can probably be depricated after removing BP support. Should be
+     * called as part of probe, but no need to pass priv outside of phy_drv implementation */
+    if ((phy_drv_dt_priv(phy_type, handle, addr, 0, &priv)) == -EPROBE_DEFER)
+        return ERR_PTR(-EPROBE_DEFER);
+
+    phy_dev = phy_dev_add(phy_type, addr, priv);
+    if (!phy_dev)
+    {
+        printk("Failed to create phy device: %d:%d\n", phy_type, addr);
+        goto Exit;
+    }
+
+    phy_dev->bus_drv = bus_drv_get_by_str(dt_property_read_string(dt_parent(handle), "bus-type"));;
+    phy_dev->swap_pair = dt_property_read_bool(handle, "enet-phy-lane-swap");
+    phy_dev->idle_stuffing = dt_property_read_bool(handle, "idle-stuffing");
+
+    phy_dev->caps_mask = PHY_CAP_ALL;
+    if (dt_property_read_bool(handle, "caps-no-hdx"))
+        phy_dev->caps_mask &= ~(PHY_CAP_10_HALF | PHY_CAP_100_HALF | PHY_CAP_1000_HALF);
+    if (dt_property_read_bool(handle, "caps-no-10000"))
+        phy_dev->caps_mask &= ~(PHY_CAP_10000);
+    if (dt_property_read_bool(handle, "caps-no-5000"))
+        phy_dev->caps_mask &= ~(PHY_CAP_5000);
+    if (dt_property_read_bool(handle, "caps-no-1000"))
+        phy_dev->caps_mask &= ~(PHY_CAP_1000_HALF | PHY_CAP_1000_FULL);
+    if (dt_property_read_bool(handle, "caps-no-100"))
+        phy_dev->caps_mask &= ~(PHY_CAP_100_HALF | PHY_CAP_100_FULL);
+    if (dt_property_read_bool(handle, "caps-no-10"))
+        phy_dev->caps_mask &= ~(PHY_CAP_10_HALF | PHY_CAP_10_FULL);
+
+    parse_reset_gpio(handle, phy_dev);
+
+    if (phy_drv_dev_add(phy_dev))
+    {
+        printk("Failed to add phy device to the driver: %s:%d\n", phy_dev->phy_drv->name, addr);
+        phy_dev_del(phy_dev);
+        phy_dev = NULL;
+        goto Exit;
+    }
+
+    if (phy_dev_next)
+    {
+        phy_dev_next->cascade_prev = phy_dev;
+        phy_dev->cascade_next = phy_dev_next;
+    }
+
+    printk("Registered phy device: %s:0x%x\n", phy_dev->phy_drv->name, addr);
+
+Exit:
+    return phy_dev;
+}
+
+void phy_dev_attach(phy_dev_t *phy_dev, phy_mii_type_t mii_type, int delay_rx, int delay_tx)
+{
+    phy_dev->delay_rx = delay_rx;
+    phy_dev->delay_tx = delay_tx;
+
+    phy_dev->mii_type = mii_type;
+    phy_dev->caps_mask &= parse_caps_mask(phy_dev->mii_type);
+
+    if (phy_dev->cascade_next)
+        phy_dev_attach(phy_dev->cascade_next, mii_type, delay_rx, delay_tx);
+}
+EXPORT_SYMBOL(phy_dev_attach);
+
+void mac_dev_rgmii_attach(mac_dev_t *mac_dev, int delay_rx, int delay_tx, int is_1p8v, int rgmii_pins[], int num_pins)
+{
+    rgmii_attach(mac_dev->mac_id, delay_rx, delay_tx, is_1p8v, rgmii_pins, num_pins);
+}
+EXPORT_SYMBOL(mac_dev_rgmii_attach);
+
+extern mac_drv_t *mac_drivers[MAC_TYPE_MAX];
+
+static mac_type_t dt_get_mac_type(const dt_handle_t handle)
+{
+    int i;
+    mac_drv_t *mac_drv;
+    const char *mac_type_str = dt_property_read_string(handle, "mac-type");
+
+    if (!mac_type_str)
+        goto Exit;
+
+    for (i = 0; i < MAC_TYPE_MAX; i++)
+    {
+        mac_drv = mac_drivers[i];
+        if (mac_drv && !strcasecmp(mac_drv->name, mac_type_str))
+            return i;
+    }
+
+Exit:
+    return MAC_TYPE_UNKNOWN;
+}
+
+static int mac_drv_dt_priv(mac_type_t mac_type, const dt_handle_t handle, int mac_id, void **priv)
+{
+    mac_drv_t *mac_drv;
+
+    if (!(mac_drv = mac_drivers[mac_type]))
+    {
+        printk("Failed to find MAC driver: mac_type=%d\n", mac_type);
+        return -1;
+    }
+
+    if (!mac_drv->dt_priv)
+        return 0;
+
+    return mac_drv->dt_priv(handle, mac_id, priv);
+}
+
+mac_dev_t *mac_dev_dt_probe(const dt_handle_t handle, uint32_t port_index)
+{
+    int ret;
+    void *priv;
+    mac_dev_t *mac_dev = NULL;
+    const mac_type_t mac_type = dt_get_mac_type(handle);
+
+    if (mac_type == MAC_TYPE_UNKNOWN)
+        goto Exit;
+
+    ret = mac_drv_dt_priv(mac_type, handle, port_index, &priv);
+    if (ret)
+        goto Exit;
+
+    mac_dev = mac_dev_add(mac_type, port_index, priv);
+    if (!mac_dev)
+    {
+        printk("Failed to create mac device: %d:%d\n", mac_type, port_index);
+        goto Exit;
+    }
+
+    printk("Registered mac device: %s:0x%x\n", mac_dev->mac_drv->name, port_index);
+
+Exit:
+    return mac_dev;
+}
+EXPORT_SYMBOL(mac_dev_dt_probe);
+
+#ifdef __UBOOT__
+#define DT_NUM_OF_PORTS 8
+static phy_dev_t *phy_devices[DT_NUM_OF_PORTS];
+static mac_dev_t *mac_devices[DT_NUM_OF_PORTS];
+#if defined(CONFIG_BCM_BCA_LED)
+static bca_leds_info_t port_leds_info[DT_NUM_OF_PORTS];
+#endif
+
+uint32_t dt_get_ports_num(void)
+{
+    return DT_NUM_OF_PORTS;
+}
+
+phy_dev_t *dt_get_phy_dev(uint32_t port_index)
+{
+    if (port_index > DT_NUM_OF_PORTS)
+        return NULL;
+
+    return phy_devices[port_index];
+}
+
+mac_dev_t *dt_get_mac_dev(uint32_t port_index)
+{
+    if (port_index > DT_NUM_OF_PORTS)
+        return NULL;
+
+    return mac_devices[port_index];
+}
+
+static int port_add(uint32_t port_index, phy_dev_t *phy_dev, mac_dev_t *mac_dev)
+{
+    phy_devices[port_index] = phy_dev;
+    mac_devices[port_index] = mac_dev;
+
+    return 0;
+}
+
+#define RGMII_PINS_MAX 12
+
+/* TODO: read from dts */
+#if defined(CONFIG_BCM96846)
+#define RGMII_PIN 42
+#elif defined(CONFIG_BCM96856)
+#define RGMII_PIN 48
+#elif defined(CONFIG_BCM96878)
+#define RGMII_PIN 40
+#else
+#define RGMII_PIN 0
+#endif
+
+static int mii_pins_get(dt_handle_t port, int pins[], int *num_pins)
+{
+    int i;
+
+    for (i = 0; i < RGMII_PINS_MAX; i++)
+        pins[i] = RGMII_PIN + i;
+
+    return 0;
+}
+
+static int dt_port_probe(dt_handle_t sw, dt_handle_t port)
+{
+    dt_handle_t phy;
+    uint32_t port_index;
+    int delay_rx, delay_tx, is_1p8v;
+    phy_mii_type_t mii_type;
+    phy_dev_t *phy_dev = NULL;
+    mac_dev_t *mac_dev = NULL;
+    const char *status_str = dt_property_read_string(port, "status");
+
+    port_index = dt_property_read_u32(port, "reg");
+    if (port_index == (uint32_t)(-1))
+    {
+        printk("Missing reg entry\n");
+        return -1;
+    }
+
+    mii_type = dt_get_phy_mode_mii_type(port);
+    delay_rx = dt_property_read_bool(port, "rx-delay");
+    delay_tx = dt_property_read_bool(port, "tx-delay");
+    is_1p8v = dt_property_read_bool(port, "rgmii-1p8v");
+
+#if (defined(CONFIG_BCM63146) || defined(CONFIG_BCM4912))
+    // FIXME_DT: only support uboot on QGPHY & SGPHY for now
+    if (mii_type != PHY_MII_TYPE_GMII)
+        return -1; 
+#endif
+
+    if (mii_type == PHY_MII_TYPE_RGMII)
+    {
+        int rgmii_pins[RGMII_PINS_MAX], num_pins = RGMII_PINS_MAX;
+
+        if (mii_pins_get(port, rgmii_pins, &num_pins))
+            num_pins = 0;
+
+        rgmii_attach(port_index, delay_rx, delay_tx, is_1p8v, rgmii_pins, num_pins);
+    }
+
+    phy = dt_parse_phandle(port, "phy-handle", 0);
+    if (dt_is_valid(phy))
+    {
+        if (!(phy_dev = phy_drv_find_device(phy)))
+        {
+            printk("Failed to find phy for port %d\n", port_index);
+            return -1;
+        }
+
+        phy_dev_attach(phy_dev, mii_type, !delay_rx, !delay_tx);
+    }
+
+    if (!(mac_dev = mac_dev_dt_probe(port, port_index)))
+    {
+        printk("Failed to create mac for port %d\n", port_index);
+        return -1;
+    }
+
+    if (port_add(port_index, cascade_phy_get_last(phy_dev), mac_dev))
+    {
+        printk("Failed to create port %d\n", port_index);
+        return -1;
+    }
+
+#if defined(CONFIG_BCM_BCA_LED)
+    bca_led_request_network_leds(port, &port_leds_info[port_index]);
+#endif
+
+    return 0;
+}
+
+static int sw_probe(dt_handle_t sw)
+{
+    int ret = 0;
+    dt_handle_t child, port;
+    const char *sw_type_str = dt_property_read_string(sw, "sw-type");
+
+    if (!sw_type_str || strcasecmp(sw_type_str, "RUNNER_SW"))
+    {
+        printk("Unsupported switch type: %s\n", sw_type_str);
+        return -1;
+    }
+
+    dt_for_each_child_of_node(sw, child)
+    {
+        if (!dt_is_available(child))
+            continue;
+
+        dt_for_each_child_of_node(child, port)
+        {
+            if (!dt_is_available(port))
+                continue;
+
+            ret |= dt_port_probe(sw, port);
+        }
+    }
+
+    return 0;
+}
+
+int dt_probe(void)
+{
+    int i;
+    struct udevice *dev;
+    dt_handle_t root_switch;
+
+    root_switch = dt_find_compatible_node(ofnode_null(), "brcm,enet");
+    if (!dt_is_valid(root_switch))
+    {
+        printk("Failed to find the root switch node\n");
+        return -1;
+    }
+
+    printk("\nFound root switch, looking for ports:\n");
+
+    mac_drivers_set();
+    phy_drivers_set();
+
+    for (uclass_first_device_check(UCLASS_MISC, &dev); dev; uclass_next_device_check(&dev));
+
+    if (sw_probe(root_switch))
+    {
+        printk("Failed to probe device tree ports\n");
+        return -1;
+    }
+
+    mac_drivers_init();
+    phy_drivers_init();
+
+    for (i = 0; i < dt_get_ports_num(); i++)
+    {
+        mac_dev_t **mac_dev = &mac_devices[i];
+        phy_dev_t **phy_dev = &phy_devices[i];
+
+        if (*mac_dev)
+        {
+            mac_dev_init(*mac_dev);
+            if (!*phy_dev)
+                mac_dev_enable(*mac_dev);
+        }
+
+        if (*phy_dev)
+        {
+            if (phy_dev_init(*phy_dev))
+            {
+                phy_dev_del(*phy_dev);
+                *phy_dev = NULL;
+                printk("Failed to initialize phy for port: %d. ignoring...\n", i);
+                continue;
+            }
+
+#if defined(CONFIG_BCM_BCA_LED)
+            phy_dev_leds_init(*phy_dev, &port_leds_info[i]);
+#endif
+        }
+    }
+
+    return 0;
+}
+
+static int bcmbca_phy_probe(struct udevice *udev)
+{
+    ofnode node = udev->node;
+    phy_dev_t *phy_dev;
+
+    if (!ofnode_valid(node))
+        return -ENODEV;
+
+    phy_dev = phy_dev_dt_probe(node);
+    if (phy_dev == ERR_PTR(-EPROBE_DEFER))
+        return -EPROBE_DEFER;
+    if (!phy_dev)
+        return -EINVAL;
+
+    phy_dev->dt_handle = node;
+
+    return 0;
+}
+
+static const struct udevice_id bcmbca_phy_ids[] = {
+    { .compatible = "brcm,bcaphy" },
+    { /* end of list */ },
+};
+
+U_BOOT_DRIVER(bcmbca_phy) = {
+    .name	= "bcmbca_phy",
+    .id	= UCLASS_MISC,
+    .of_match = bcmbca_phy_ids,
+    .probe = bcmbca_phy_probe,
+};
+#else
+static int phy_probe(struct platform_device *pdev)
+{
+    struct device_node *node = pdev->dev.of_node;
+    phy_dev_t *phy_dev;
+
+    if (!node)
+        return -ENODEV;
+
+    phy_dev = phy_dev_dt_probe(node);
+    if (phy_dev == ERR_PTR(-EPROBE_DEFER))
+        return -EPROBE_DEFER;
+    if (!phy_dev)
+        return -EINVAL;
+
+    phy_dev->dt_handle = node;
+
+    return 0;
+}
+
+const struct of_device_id phy_of_platform_table[] = {
+    { .compatible = "brcm,bcaphy", .data = (void *)0, },
+    { /* end of list */ },
+};
+
+struct platform_driver phy_of_platform_driver = {
+    .driver = {
+        .name = "bcmbca_phy",
+        .of_match_table = phy_of_platform_table,
+    },
+    .probe = phy_probe,
+};
+
+static int __init phy_init(void)
+{
+    int rc;
+
+    rc = phy_drivers_set();
+    if (rc)
+        return rc;
+
+    return platform_driver_register(&phy_of_platform_driver);
+}
+
+subsys_initcall(phy_init);
+#endif
diff --git a/drivers/net/bcmbca/phy/ephy_led_init.c b/drivers/net/bcmbca/phy/ephy_led_init.c
new file mode 100644
index 0000000000..47c45017b8
--- /dev/null
+++ b/drivers/net/bcmbca/phy/ephy_led_init.c
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Apr 2019
+ *      Author: samyon.furman@broadcom.com
+ */
+
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include "os_dep.h"
+#include "bcm_bca_leds_dt_bindings.h"
+#include "bcm_bca_leds.h"
+#include "dt_access.h"
+
+typedef union {
+    struct {
+        uint32_t rx_act_en                 :1 ; // [00:00]
+        uint32_t tx_act_en                 :1 ; // [01:01]
+        uint32_t spdlnk_led0_act_sel       :1 ; // [02:02]
+        uint32_t spdlnk_led1_act_sel       :1 ; // [03:03]
+        uint32_t spdlnk_led2_act_sel       :1 ; // [04:04]
+        uint32_t act_led_act_sel           :1 ; // [05:05]
+        uint32_t spdlnk_led0_act_pol_sel   :1 ; // [06:06]
+        uint32_t spdlnk_led1_act_pol_sel   :1 ; // [07:07]
+        uint32_t spdlnk_led2_act_pol_sel   :1 ; // [08:08]
+        uint32_t act_led_pol_sel           :1 ; // [09:09]
+        uint32_t led_spd_ovrd              :3 ; // [12:10]
+        uint32_t lnk_status_ovrd           :1 ; // [13:13]
+        uint32_t spd_ovrd_en               :1 ; // [14:14]
+        uint32_t lnk_ovrd_en               :1 ; // [15:15]
+        uint32_t r1                        :16; // [31:16]
+    }Bits;
+    uint32_t Reg32;
+}EPHY_LED_CTRL;
+
+typedef union {
+    struct {
+        uint32_t sel_no_link_encode        :3 ; // [02:00] 
+        uint32_t sel_10m_encode            :3 ; // [05:03]
+        uint32_t sel_100m_encode           :3 ; // [08:06]
+        uint32_t sel_1000m_encode          :3 ; // [11:09]
+        uint32_t sel_2500m_encode          :3 ; // [14:12]
+        uint32_t sel_10g_encode            :3 ; // [17:15]
+        uint32_t r1                        :14; // [31:18]
+    }Bits;
+    uint32_t Reg32;
+}EPHY_LED_LINK_SPEED_ENC_SEL;
+
+typedef union {
+    struct {
+        uint32_t no_link_encode            :3 ; // [02:00]
+        uint32_t m10_encode                :3 ; // [05:03]
+        uint32_t m100_encode               :3 ; // [08:06]
+        uint32_t m1000_encode              :3 ; // [11:09]
+        uint32_t m2500_encode              :3 ; // [14:12]
+        uint32_t m10g_encode               :3 ; // [17:15]
+        uint32_t r1                        :14; // [31:18]
+    }Bits;
+    uint32_t Reg32;
+}EPHY_LED_LINK_SPEED_ENC;
+
+typedef union {
+    struct {
+        uint32_t port_en                   :16; // [15:00]
+        uint32_t act_sel                   :1 ; // [16:16]
+        uint32_t act_pol_sel               :1 ; // [17:17]
+        uint32_t lnk_pol_sel               :1 ; // [18:18]
+        uint32_t r1                        :13; // [31:19]
+    }Bits;
+    uint32_t Reg32;
+}EPHY_LED_AGGREGATE_CTRL;
+
+typedef struct led_reg
+{
+    EPHY_LED_CTRL                   led_ctrl;
+    EPHY_LED_LINK_SPEED_ENC_SEL     led_link_speed_enc_sel;
+    EPHY_LED_LINK_SPEED_ENC         led_link_speed_enc;
+}LED_REG;
+
+
+static int driver_init_done=0;
+struct EphyLedRegs {
+    int                               max_led_regs;
+    LED_REG                           **led_reg;
+    uint32_t                          *led_blink_rate_ctrl;
+    uint32_t                          *led_pwm_ctrl;
+    uint32_t                          *led_intensity_ctrl;
+    EPHY_LED_AGGREGATE_CTRL           *led_aggregate_ctrl;
+    uint32_t                          *led_aggregate_blink_rate_ctrl;
+    uint32_t                          *led_aggregate_pwm_ctrl;
+    uint32_t                          *led_aggregate_intensity_ctrl;
+    uint32_t                          *led_sw_init_ctrl;
+} EphyLedRegs;
+
+#define PEPHY_LED            ((volatile struct EphyLedRegs * const) &EphyLedRegs)
+
+
+static int ephyled_probe(dt_device_t *pdev)
+{
+    int ret;
+    struct resource res;
+    int index=0;
+    char led_reg_str[25];
+
+
+    PEPHY_LED->max_led_regs=dt_property_read_u32(dt_dev_get_handle(pdev), "led_reg_max");
+    // assume that there is only 1 led_reg if led_reg_max is not defined
+    if(PEPHY_LED->max_led_regs == -1)
+        PEPHY_LED->max_led_regs=1; 
+
+
+    PEPHY_LED->led_reg = calloc(sizeof(LED_REG*), PEPHY_LED->max_led_regs);
+    if(PEPHY_LED->led_reg == NULL)
+    {
+        dev_err(&pdev->dev, "memory allocation failed for led_reg\n");
+        return -ENOMEM;
+        
+    }
+    do
+    {
+        sprintf(led_reg_str, "led_reg_%d", index); 
+
+        ret = dev_read_resource_byname(pdev, led_reg_str, &res);
+        if (ret)
+        {
+            PEPHY_LED->led_reg[index]=NULL;
+            continue;
+        }
+        PEPHY_LED->led_reg[index] = devm_ioremap(pdev, res.start, resource_size(&res));
+
+    } while(++index < PEPHY_LED->max_led_regs);
+
+    ret = dev_read_resource_byname(pdev, "aggregate_ctrl", &res);
+    if (ret)
+    {
+        PEPHY_LED->led_aggregate_ctrl=NULL;
+        dev_err(&pdev->dev, "Missing ephyled_base entry, ignoring\n");
+    }
+    else
+    {
+        PEPHY_LED->led_aggregate_ctrl = devm_ioremap(pdev, res.start, resource_size(&res));
+        PEPHY_LED->led_aggregate_ctrl->Bits.act_sel = 1;
+        PEPHY_LED->led_aggregate_ctrl->Bits.act_pol_sel = 0;
+        PEPHY_LED->led_aggregate_ctrl->Bits.lnk_pol_sel = 1;
+    }
+
+    dev_info(&pdev->dev, "registered\n");
+    driver_init_done=1;
+
+    return 0;
+Exit:
+    return ret;
+}
+
+#ifdef __UBOOT__
+static const struct udevice_id ephyled_ids[] = {
+    { .compatible = "brcm,ephy-led" },
+    { /* end of list */ },
+};
+
+U_BOOT_DRIVER(brcm_ephyled) = {
+    .name	= "brcm-ephyled",
+    .id	= UCLASS_MISC,
+    .of_match = ephyled_ids,
+    .probe = ephyled_probe,
+};
+#else
+static const struct of_device_id of_platform_table[] = {
+    { .compatible = "brcm,ephy-led" },
+    { /* end of list */ },
+};
+
+static struct platform_driver of_platform_driver = {
+    .driver = {
+        .name = "brcm-ephyled",
+        .of_match_table = of_platform_table,
+    },
+    .probe = ephyled_probe,
+};
+module_platform_driver(of_platform_driver);
+#endif
+
+
+int ephy_leds_init(void *_leds_info)
+{
+    bca_leds_info_t *leds_info = (bca_leds_info_t *)_leds_info;
+    int ret = 0;
+    int j;
+    EPHY_LED_CTRL led_ctrl;
+    EPHY_LED_LINK_SPEED_ENC_SEL spdlnk_sel;
+    EPHY_LED_LINK_SPEED_ENC spdlnk;
+    uint32_t port = leds_info->port_id;
+
+    uint8_t activity;
+
+
+    if(driver_init_done == 0)
+        return -1;
+    if(port == 0xff || port >= PEPHY_LED->max_led_regs 
+        || PEPHY_LED->led_reg == NULL ||  PEPHY_LED->led_reg[port] == NULL )
+    {
+        /*No Led data provided */
+        return 0;
+    }
+
+    spdlnk_sel.Bits.sel_10g_encode = 0;
+    spdlnk_sel.Bits.sel_1000m_encode = 0;
+    spdlnk_sel.Bits.sel_100m_encode = 0;
+    spdlnk_sel.Bits.sel_2500m_encode = 0;
+    spdlnk_sel.Bits.sel_10m_encode = 0;
+    spdlnk_sel.Bits.sel_no_link_encode = 0;
+
+    spdlnk.Bits.m10g_encode = 7;
+    spdlnk.Bits.m2500_encode = 7;
+    spdlnk.Bits.m1000_encode = 7;
+    spdlnk.Bits.m100_encode = 7;
+    spdlnk.Bits.m10_encode = 7;
+    spdlnk.Bits.no_link_encode = 7;
+
+    led_ctrl.Reg32 = PEPHY_LED->led_reg[port]->led_ctrl.Reg32;
+
+
+    if ( PEPHY_LED->led_aggregate_ctrl != NULL )
+        if (!leds_info->skip_in_aggregate)
+            PEPHY_LED->led_aggregate_ctrl->Bits.port_en |= 1<<port;
+
+    for (j = 0; j < 3; j++)
+    {
+        uint32_t led_mux = leds_info->link[j];
+        uint32_t led_activity = leds_info->activity[j];
+        activity = 0;
+
+        if (led_mux & LED_SPEED_10G)
+            spdlnk.Bits.m10g_encode &= ~(1<<j);
+        if (led_mux & LED_SPEED_2500)
+            spdlnk.Bits.m2500_encode &= ~(1<<j);
+        if (led_mux & LED_SPEED_1G)
+            spdlnk.Bits.m1000_encode &= ~(1<<j);
+        if (led_mux & LED_SPEED_100)
+            spdlnk.Bits.m100_encode &= ~(1<<j);
+        if (led_mux & LED_SPEED_10)
+            spdlnk.Bits.m10_encode &= ~(1<<j);
+
+        if (led_activity & LED_SPEED_10G)
+            spdlnk_sel.Bits.sel_10g_encode |= (1<<j);
+        if (led_activity & LED_SPEED_2500)
+            spdlnk_sel.Bits.sel_2500m_encode |= (1<<j);
+        if (led_activity & LED_SPEED_1G)
+            spdlnk_sel.Bits.sel_1000m_encode |= (1<<j);
+        if (led_activity & LED_SPEED_100)
+            spdlnk_sel.Bits.sel_100m_encode |= (1<<j);
+        if (led_activity & LED_SPEED_10)
+            spdlnk_sel.Bits.sel_10m_encode |= (1<<j);
+
+        /* to configure the speed led to show activity only for specified
+           speeds */
+        if (led_activity && !(led_mux & led_activity))
+            activity = 1;
+
+        switch (j)
+        {
+        case 0:
+            led_ctrl.Bits.spdlnk_led0_act_sel = activity;
+            break;
+        case 1:
+            led_ctrl.Bits.spdlnk_led1_act_sel = activity;
+            break;
+        case 2:
+            led_ctrl.Bits.spdlnk_led2_act_sel = activity;
+            break;
+        }
+    }
+            
+    if (leds_info->activity[3] || leds_info->link[3])
+        led_ctrl.Bits.act_led_act_sel = leds_info->link[3] ? 0 : 1;
+
+    PEPHY_LED->led_reg[port]->led_link_speed_enc_sel.Reg32 = spdlnk_sel.Reg32;
+    PEPHY_LED->led_reg[port]->led_link_speed_enc.Reg32 = spdlnk.Reg32;
+    PEPHY_LED->led_reg[port]->led_ctrl.Reg32 = led_ctrl.Reg32;
+    printk("%s Port %d configured \n", __FUNCTION__, port);
+
+    return ret;
+}
diff --git a/drivers/net/bcmbca/phy/ephy_led_init.h b/drivers/net/bcmbca/phy/ephy_led_init.h
new file mode 100644
index 0000000000..55ec2fbd26
--- /dev/null
+++ b/drivers/net/bcmbca/phy/ephy_led_init.h
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+/*
+ * ephy_led_init.h
+ *
+ *  Created on: April 2019
+ *      Author: samyon.furman@broadcom.com
+ */
+
+#ifndef _EPHY_LED_INIT_H_
+#define _EPHY_LED_INIT_H_
+
+#if !defined(EPHY_LED)
+static inline
+#endif
+int ephy_leds_init(void * _leds_info)
+#if !defined(EPHY_LED)
+{ return 0; }
+#endif
+;
+
+#endif
diff --git a/drivers/net/bcmbca/phy/hwapi_mac.h b/drivers/net/bcmbca/phy/hwapi_mac.h
new file mode 100644
index 0000000000..518be7a91b
--- /dev/null
+++ b/drivers/net/bcmbca/phy/hwapi_mac.h
@@ -0,0 +1,1017 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2013 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This header file defines all datatypes and functions exported for the      */
+/* Ethernet MAC		                                                          */
+/*                                                                            */
+/******************************************************************************/
+
+
+#ifndef __UNIFIED_DRV_MAC_H
+#define __UNIFIED_DRV_MAC_H
+
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+#if !defined(CONFIG_BCM947622)
+#include "rdpa_types.h"
+#else //47622 - does not have runner, just include necessary definitions
+
+#define rdpa_emac   int
+
+/** EMAC rates */
+typedef enum
+{
+    rdpa_emac_rate_10m,     /**< 10 Mbps */
+    rdpa_emac_rate_100m,    /**< 100 Mbps */
+    rdpa_emac_rate_1g,      /**< 1 Gbps */
+    rdpa_emac_rate_2_5g,    /**< 2.5 Gbps */
+
+    rdpa_emac_rate__num_of, /* Number of rates */
+} rdpa_emac_rate;
+
+/** EMAC configuration */
+typedef struct
+{
+    char loopback;      /**< 1 = line loopback */
+    rdpa_emac_rate rate;       /**< EMAC rate */
+    char generate_crc;  /**< 1 = generate CRC */
+    char full_duplex;   /**< 1 = full duplex */
+    char pad_short;     /**< 1 = pad short frames */
+    char allow_too_long;/**< 1 = allow long frames */
+    char check_length;  /**< 1 = check frame length */
+    uint32_t preamble_length;   /**< Preamble length */
+    uint32_t back2back_gap;     /**< Back2Back inter-packet gap */
+    uint32_t non_back2back_gap; /**< Non Back2Back inter-packet gap */
+    uint32_t min_interframe_gap; /**< Min inter-frame gap */
+    char rx_flow_control;/**< 1 = enable RX flow control */
+    char tx_flow_control;/**< 1 = enable TX flow control */
+} rdpa_emac_cfg_t;
+
+/** RX RMON counters.
+ * Underlying type for emac_rx_stat aggregate type.
+ */
+typedef struct
+{
+    uint32_t byte;              /**< Receive Byte Counter */
+    uint32_t packet;            /**< Receive Packet Counter */
+    uint32_t frame_64;          /**< Receive 64 Byte Frame Counter */
+    uint32_t frame_65_127;      /**< Receive 65 to 127 Byte Frame Counter */
+    uint32_t frame_128_255;     /**< Receive 128 to 255 Byte Frame Counter */
+    uint32_t frame_256_511;     /**< Receive 256 to 511 Byte Frame Counter */
+    uint32_t frame_512_1023;    /**< Receive 512 to 1023 Byte Frame Counter */
+    uint32_t frame_1024_1518;   /**< Receive 1024 to 1518 Byte Frame Counter */
+    uint32_t frame_1519_mtu;    /**< Receive 1519 to MTU Frame Counter */
+    uint32_t multicast_packet;  /**< Receive Multicast Packet */
+    uint32_t broadcast_packet;  /**< Receive Broadcast Packet */
+    uint32_t unicast_packet;    /**< Receive Unicast Packet */
+    uint32_t alignment_error;   /**< Receive Alignment error */
+    uint32_t frame_length_error;/**< Receive Frame Length Error Counter */
+    uint32_t code_error;        /**< Receive Code Error Counter */
+    uint32_t carrier_sense_error;/**< Receive Carrier sense error */
+    uint32_t fcs_error;         /**< Receive FCS Error Counter */
+    uint32_t control_frame;     /**< Receive Control Frame Counter */
+    uint32_t pause_control_frame;/**< Receive Pause Control Frame */
+    uint32_t unknown_opcode;    /**< Receive Unknown opcode */
+    uint32_t undersize_packet;  /**< Receive Undersize Packet */
+    uint32_t oversize_packet;   /**< Receive Oversize Packet */
+    uint32_t fragments;         /**< Receive Fragments */
+    uint32_t jabber;            /**< Receive Jabber counter */
+    uint32_t overflow;          /**< Receive Overflow counter */
+} rdpa_emac_rx_stat_t;
+
+/** Tx RMON counters.
+ * Underlying type for emac_tx_stat aggregate type.
+ */
+typedef struct
+{
+    uint32_t byte;              /**< Transmit Byte Counter */
+    uint32_t packet;            /**< Transmit Packet Counter */
+    uint32_t frame_64;          /**< Transmit 64 Byte Frame Counter */
+    uint32_t frame_65_127;      /**< Transmit 65 to 127 Byte Frame Counter */
+    uint32_t frame_128_255;     /**< Transmit 128 to 255 Byte Frame Counter */
+    uint32_t frame_256_511;     /**< Transmit 256 to 511 Byte Frame Counter */
+    uint32_t frame_512_1023;    /**< Transmit 512 to 1023 Byte Frame Counter */
+    uint32_t frame_1024_1518;   /**< Transmit 1024 to 1518 Byte Frame Counter */
+    uint32_t frame_1519_mtu;    /**< Transmit 1519 to MTU Frame Counter */
+    uint32_t fcs_error;         /**< Transmit FCS Error */
+    uint32_t multicast_packet;  /**< Transmit Multicast Packet */
+    uint32_t broadcast_packet;  /**< Transmit Broadcast Packet */
+    uint32_t unicast_packet;    /**< Transmit Unicast Packet */
+    uint32_t excessive_collision; /**< Transmit Excessive collision counter */
+    uint32_t late_collision;    /**< Transmit Late collision counter */
+    uint32_t single_collision;  /**< Transmit Single collision frame counter */
+    uint32_t multiple_collision;/**< Transmit Multiple collision frame counter */
+    uint32_t total_collision;   /**< Transmit Total Collision Counter */
+    uint32_t pause_control_frame; /**< Transmit PAUSE Control Frame */
+    uint32_t deferral_packet;   /**< Transmit Deferral Packet */
+    uint32_t excessive_deferral_packet; /**< Transmit Excessive Deferral Packet */
+    uint32_t jabber_frame;      /**< Transmit Jabber Frame */
+    uint32_t control_frame;     /**< Transmit Control Frame */
+    uint32_t oversize_frame;    /**< Transmit Oversize Frame counter */
+    uint32_t undersize_frame;   /**< Transmit Undersize Frame */
+    uint32_t fragments_frame;   /**< Transmit Fragments Frame counter */
+    uint32_t error;             /**< Transmission errors*/
+    uint32_t underrun;          /**< Transmission underrun */
+} rdpa_emac_tx_stat_t;
+
+/** Emac statistics */
+typedef struct
+{
+    rdpa_emac_rx_stat_t rx; /**< Emac Receive Statistics */
+    rdpa_emac_tx_stat_t tx; /**< Emac Transmit Statistics */
+} rdpa_emac_stat_t;
+
+/** Ethernet address */
+typedef struct {
+    uint8_t b[6];  /**< Address bytes */
+} bdmf_mac_t;
+
+#endif //47622
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+
+typedef struct
+{
+	int32_t rxFlowEnable;
+	int32_t txFlowEnable;
+}S_MAC_HWAPI_FLOW_CTRL;
+
+typedef enum
+{
+	MAC_LPBK_NONE,
+	MAC_LPBK_LOCAL,
+	MAC_LPBK_REMOTE,
+	MAC_LPBK_BOTH
+}MAC_LPBK;
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct
+{
+	uint32_t    reserved:26;// Reserved bits must be written with 0.  A read returns an unknown value.
+	uint32_t    mac_link_stat:1;// Link status indication.Reset value is 0x0.
+	uint32_t    mac_tx_pause:1;// 1: MAC Tx pause enabled. 0: MAC Tx pause disabled. Reset value is 0x1.
+	uint32_t	mac_rx_pause:1;// 1: MAC Rx pause enabled. 0: MAC Rx pause disabled.	Reset value is 0x1.
+	uint32_t	mac_duplex:1;//1: Half duplex. 0: Full duplex. Reset value is 0x0.
+	uint32_t	mac_speed:2;// 00: 10Mbps, 01: 100Mbps, 10: 1Gbps, 11: 2.5Gbps	Reset value is 0x2.
+
+}S_HWAPI_MAC_STATUS;
+#else
+typedef struct
+{
+	uint32_t	mac_speed:2;// 00: 10Mbps, 01: 100Mbps, 10: 1Gbps, 11: 2.5Gbps	Reset value is 0x2.
+	uint32_t	mac_duplex:1;//1: Half duplex. 0: Full duplex. Reset value is 0x0.
+	uint32_t	mac_rx_pause:1;// 1: MAC Rx pause enabled. 0: MAC Rx pause disabled.	Reset value is 0x1.
+	uint32_t    mac_tx_pause:1;// 1: MAC Tx pause enabled. 0: MAC Tx pause disabled. Reset value is 0x1.
+	uint32_t    mac_link_stat:1;// Link status indication.Reset value is 0x0.
+	uint32_t    reserved:26;// Reserved bits must be written with 0.  A read returns an unknown value.
+
+}S_HWAPI_MAC_STATUS;
+#endif
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_configuration                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get configuration                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   get the configuratin of a mac port	,note that current status of emac	  */
+/*   might be different than configuration when working in autoneg			  */
+/*	to get the current status use mac_hwapi_get_mac_status API				  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    emac_cfg -  structure holds the current configuration of the mac  port  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_configuration(rdpa_emac emacNum,rdpa_emac_cfg_t *emac_cfg);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_configuration                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set configuration                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   set the configuratin of a mac port                                       */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   emac_cfg -  structure holds the current configuration of the mac  port   */
+/*                                                                            */
+/* Output:                                                                    */
+/*      																	  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_configuration(rdpa_emac emacNum,rdpa_emac_cfg_t *emac_cfg);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_duplex		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port duplex                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the dulplex of a port												  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    full_duples  :  1 = full dulplex,0 = half_duplex						  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_duplex(rdpa_emac emacNum,int32_t *full_duplex);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_duplex		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port duplex                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the dulplex of a port												  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    full_duples  :  1 = full dulplex,0 = half_duplex						  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_duplex(rdpa_emac emacNum,int32_t full_duplex);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_speed		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port speed rate                                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the speed of a port													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                              							                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*      rate -   enum of the speed                                            */
+/******************************************************************************/
+void mac_hwapi_get_speed(rdpa_emac emacNum,rdpa_emac_rate *rate);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_speed		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port speed rate                                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the speed of a port													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*      rate -   enum of the speed   						                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                   							              */
+/******************************************************************************/
+
+void mac_hwapi_set_speed(rdpa_emac emacNum,rdpa_emac_rate rate);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_external_conf                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - en/disable external speed configuration                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set port speed external configuration				      				  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    enable - boolean enable                                                 */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                   							              */
+/******************************************************************************/
+
+void mac_hwapi_set_external_conf(rdpa_emac emacNum, int enable);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rxtx_enable                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx and rx enable                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get tx and rx enable													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                             								  */
+/*                                                                            */
+/* Output:                                                                    */
+/*       rxtxEnable  - boolean enable   	                                  */
+/******************************************************************************/
+void mac_hwapi_get_rxtx_enable(rdpa_emac emacNum,int32_t *rxEnable,int32_t *txEnable);
+
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_rxtx_enable                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx and rx enable                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set tx and rx enable													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    rxtxEnable  - boolean enable                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_rxtx_enable(rdpa_emac emacNum,int32_t rxEnable,int32_t txEnable);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_sw_reset		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port software reset                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the sw reset bit of emac port										  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    swReset  :  1 = reset,0 = not reset									  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_sw_reset(rdpa_emac emacNum,int32_t *swReset);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_sw_reset		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port software reset                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the sw reset bit of emac port										  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   swReset  :  1 = reset,0 = not reset	                                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*    								  										  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_sw_reset(rdpa_emac emacNum,int32_t swReset);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_min_pkt_size                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get tx minimum packet size                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*  Get the unimac configuration for minimum tx packet size                   */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    min_pkt_size  :  14...125                                               */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_min_pkt_size(rdpa_emac emacNum,int32_t *min_pkt_size);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_min_pkt_size                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx minimum packet size                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*  Set the unimac configuration for minimum tx packet size                   */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*   min_pkt_size  :  14...125                                                */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_min_pkt_size(rdpa_emac emacNum,int32_t min_pkt_size);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port TX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the port maximum transmit unit size in bytes						  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                              										      */
+/*                                                                            */
+/* Output:                                                                    */
+/*    maxTxFrameLen - size of frame in bytes 								  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_max_frame_len(rdpa_emac emacNum,uint32_t *maxTxFrameLen );
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port TX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the port maximum transmit unit size in bytes						  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    maxTxFrameLen - size of frame in bytes                         	      */
+/*                                                                            */
+/* Output:                                                                    */
+/*   																		  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_max_frame_len(rdpa_emac emacNum,uint32_t maxTxFrameLen );
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port RX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the port maximum receive unit size in bytes							  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                           	     										  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   maxRxFrameLen - size of current MRU									  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_rx_max_frame_len(rdpa_emac emacNum,uint32_t *maxRxFrameLen );
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_rx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port RX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the port maximum receive unit size in bytes							  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    maxRxFrameLen - size of current MRU        							  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   									  									  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_rx_max_frame_len(rdpa_emac emacNum,uint32_t maxRxFrameLen );
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_igp_len	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port inter frame gap                                 	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the inter frame gap	size in bytes									  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   txIpgLen - length in bytes                                               */
+/*                                                                            */
+/* Output:                                                                    */
+/*    																		  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_igp_len(rdpa_emac emacNum,uint32_t txIpgLen );
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_igp_len	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port inter frame gap                                 	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the inter frame gap	size in bytes									  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                      							          */
+/*                                                                            */
+/* Output:                                                                    */
+/*    txIpgLen - length in bytes    										  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_igp_len(rdpa_emac emacNum,uint32_t *txIpgLen );
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_mac_status	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port status                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the status of mac													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    macStatus  :  														  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_mac_status(rdpa_emac emacNum,S_HWAPI_MAC_STATUS *macStatus);
+
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_flow_control                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*           																  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   flowControl - structure with parameters of tx and rx flow control		  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_flow_control                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   flowControl - structure with parameters of tx and rx flow control        */
+/*                                                                            */
+/* Output:                                                                    */
+/*   						  												  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_pause_params                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   flowControl - structure with parameters of tx and rx flow control        */
+/*                                                                            */
+/* Output:                                                                    */
+/*   						  												  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_pause_params(rdpa_emac emacNum,int32_t pauseCtrlEnable,uint32_t pauseTimer,uint32_t pauseQuanta);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rx_counters	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	get the rx counters of port                           	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the rx counters of port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    rxCounters  :  structure filled with counters							  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_rx_counters(rdpa_emac emacNum,rdpa_emac_rx_stat_t *rxCounters);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_counters	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	get the tx counters of port                           	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the tx counters of port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    txCounters  :  structure filled with counters							  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_counters(rdpa_emac emacNum,rdpa_emac_tx_stat_t *txCounters);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_init_emac	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_init_emac(rdpa_emac emacNum);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_loopback	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_loopback(rdpa_emac emacNum,MAC_LPBK *loopback);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_loopback	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_loopback(rdpa_emac emacNum,MAC_LPBK loopback);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_modify_flow_control_pause_pkt_addr                             */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - Modify the Flow Control pause pkt source address            */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   This function modifies the flow control pause pkt source address         */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - EMAC id (0-5)                                                 */
+/*                                                                            */
+/*   mac - Flow Control mac address                                   */
+/*                                                                            */
+/* Output:   N/A                                                              */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_modify_flow_control_pause_pkt_addr ( rdpa_emac emacNum,
+    bdmf_mac_t mac);
+void mac_hwapi_set_unimac_cfg(rdpa_emac emacNum, int32_t enabled);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_backpressure_ext                                           */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set/reset backpressure to external switch                   */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set/reset backpressure to external switch                                 */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*   enable  - boolean enable                                                 */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_backpressure_ext(rdpa_emac emacNum, int32_t enable);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_eee                                                        */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set eee configuration                                       */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set eee configuration                                                     */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*   enable  - boolean enable                                                 */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_eee(rdpa_emac emacNum, int32_t enable);
+
+#endif
diff --git a/drivers/net/bcmbca/phy/longfin_a0_firmware.h b/drivers/net/bcmbca/phy/longfin_a0_firmware.h
new file mode 100644
index 0000000000..aebe32e9af
--- /dev/null
+++ b/drivers/net/bcmbca/phy/longfin_a0_firmware.h
@@ -0,0 +1,9231 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Feb 2018
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Firmware for external 2.5G/5G/10G phys: Longfin BCM84891LM etc.
+ */
+
+char longfin_a0_version[] = "Longfin A0 v02-02-03-2020-04-17";
+
+uint32_t longfin_a0_firmware[] = {
+    0xea000017, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe320f000, 0xe59ff018, 0xe59ff018, 
+    0x000004b4, 0x0002cb2c, 0x0002ca80, 0x0002bdb4, 0x0002b698, 0x00000000, 0x0002ba5c, 0x0002b7fc, 
+    0x00031df0, 0xc0de512e, 0x00000000, 0x00000000, 0x00000000, 0x00031df0, 0x00003102, 0x00000000, 
+    0x00000010, 0xe59f13bc, 0xe5910000, 0xe3800102, 0xe5810000, 0xe59f13b0, 0xe3040440, 0xe1c100b0, 
+    0xeb000140, 0xe59f03a4, 0xe5901000, 0xe3110010, 0x0a000006, 0xe7c0101f, 0xe7c4121f, 0xe59f0390, 
+    0xe5801000, 0xe59f038c, 0xe3a01000, 0xe1c010b0, 0xe3a00064, 0xe2500001, 0xe3500000, 0x1afffffc, 
+    0xe59f0374, 0xe3a01004, 0xe580102c, 0xe59f036c, 0xe1d090b0, 0xe3190001, 0x1a00008f, 0xe59f0360, 
+    0xe3a02010, 0xe3822020, 0xe1d010b0, 0xe0013002, 0xe1530002, 0x1afffffb, 0xe201300f, 0xe59f5344, 
+    0xe3a06055, 0xe1c560b0, 0xe59f033c, 0xe1d010b0, 0xe3c11d0f, 0xe1a02303, 0xe2022d0f, 0xe1811002, 
+    0xe59f0324, 0xe1c010b0, 0xe59f0320, 0xe1d010b0, 0xe3c11001, 0xe1a021a3, 0xe1a02002, 0xe2022001, 
+    0xe1811002, 0xe59f0304, 0xe1c010b0, 0xe59f0300, 0xe1d010b0, 0xe3c11a0e, 0xe1a02683, 0xe2022a0e, 
+    0xe1811002, 0xe59f02e8, 0xe1c010b0, 0xe59f02e4, 0xe1d010b0, 0xe3c11a0f, 0xe1a02603, 0xe2022a0f, 
+    0xe1811002, 0xe59f02cc, 0xe1c010b0, 0xe59f02c8, 0xe1d010b0, 0xe3c11b0f, 0xe3c1100f, 0xe1a02503, 
+    0xe2022b0f, 0xe1811002, 0xe1a02003, 0xe202200f, 0xe1811002, 0xe59f02a0, 0xe1c010b0, 0xe59f029c, 
+    0xe1d010b0, 0xe3a02006, 0xe1813002, 0xe1c030b0, 0xe3c13006, 0xe1c030b0, 0xe59f0284, 0xe3a01000, 
+    0xe1c010b0, 0xe3a0100a, 0xe59f0278, 0xe1c010b0, 0xe59f0274, 0xe1d000b0, 0xe3100b01, 0x0a000017, 
+    0xe3100b02, 0x0a000015, 0xe59f0260, 0xe3a01dd2, 0xe1c010b0, 0xe59f0258, 0xe30210ef, 0xe1c010b0, 
+    0xe59f0234, 0xe30d1d67, 0xe1c010b0, 0xe59f0244, 0xe3041e63, 0xe1c010b0, 0xe59f023c, 0xe3a01b05, 
+    0xe1c010b0, 0xe59f0234, 0xe3011917, 0xe1c010b0, 0xe59f022c, 0xe3051510, 0xe1c010b0, 0xea00000b, 
+    0xe59f0208, 0xe3091280, 0xe1c010b0, 0xe59f0200, 0xe30210e9, 0xe1c010b0, 0xe59f01f8, 0xe3041e63, 
+    0xe1c010b0, 0xe59f01f8, 0xe3051508, 0xe1c010b0, 0xe59f01f0, 0xe30f140f, 0xe1c010b0, 0xe59f01e8, 
+    0xe3a01000, 0xe1c010b0, 0xe3a01004, 0xe3811001, 0xe59f01d8, 0xe1d020b0, 0xe1510002, 0x1afffffc, 
+    0xe3a00902, 0xe2500001, 0xe3500000, 0x1afffffc, 0xe59f01bc, 0xe3a01000, 0xe1c010b0, 0xe59f01b4, 
+    0xe3a01d06, 0xe1c010b0, 0xe3a060ff, 0xe1c560b0, 0xe59f0138, 0xe5901000, 0xe7c0101f, 0xe7c4121f, 
+    0xe59f0128, 0xe5801000, 0xe59f0130, 0xe3899001, 0xe1c090b0, 0xe3a06000, 0xe1c560b0, 0xe59f0178, 
+    0xe1d090b0, 0xe3190001, 0x1a000002, 0xe3899001, 0xe1c090b0, 0xea00ff31, 0xe59f1160, 0xee091f11, 
+    0xe59fa15c, 0xe59fb15c, 0xe51f0310, 0xe51f1310, 0xe1a02000, 0xe1500001, 0x0a000024, 0xe51f031c, 
+    0xe3500000, 0x1a000021, 0xe51f231c, 0xe3a01000, 0xe59f0134, 0xe1c010b0, 0xe3e00000, 0xe59f712c, 
+    0xe3a09008, 0xe4d13001, 0xe3510064, 0xca000002, 0xe3510061, 0xba000000, 0xeafffff9, 0xe3a08000, 
+    0xe7e043d3, 0xe7e05fd0, 0xe0346005, 0xe1a00080, 0x0a000000, 0xe0200007, 0xe1a03083, 0xe2888001, 
+    0xe1580009, 0xbafffff5, 0xe1510002, 0xbaffffec, 0xe5912000, 0xe58a0000, 0xe58b2000, 0xe3e03000, 
+    0xe1520003, 0x0a000001, 0xe1500002, 0x1a000009, 0xe3a03901, 0xe59f00b0, 0xe1c030b0, 0xe59f5044, 
+    0xe59f0028, 0xe5901000, 0xe3811040, 0xe3811020, 0xe5801000, 0xe51ff3fc, 0xe3a03902, 0xe59f0088, 
+    0xe1c030b0, 0xeafffffe, 0xf0002010, 0xf23c808c, 0xf0003000, 0xc0003000, 0xc23c802c, 0xf0002000, 
+    0xf23d014c, 0xf23d0206, 0xf23d0228, 0xf203f01a, 0xf203f018, 0xf203f016, 0xf203f00a, 0xf203f004, 
+    0xf203f042, 0xf2034000, 0xf2034002, 0xf23c8038, 0xf203f000, 0xf203f002, 0xf203f006, 0xf203f00e, 
+    0xf203f010, 0xf203f012, 0xf23c8308, 0xf23c830c, 0xf23d000c, 0xf23d0000, 0xf23d0004, 0xf2034020, 
+    0x00040021, 0x00000048, 0x0000004c, 0xf23c801a, 0x04c11db7, 0xebffffff, 0xebffffff, 0xebffffff, 
+    0xebffffff, 0xe3a01401, 0xee110f10, 0xe1800001, 0xe3c00a02, 0xee010f10, 0xee110f30, 0xe3800040, 
+    0xe3800501, 0xee010f30, 0xe59f0080, 0xe3a010d1, 0xe121f001, 0xe1a0d000, 0xe3a010d2, 0xe121f001, 
+    0xe2400080, 0xe1a0d000, 0xe3a010d7, 0xe121f001, 0xe2400c02, 0xe1a0d000, 0xe3a010db, 0xe121f001, 
+    0xe2400080, 0xe1a0d000, 0xe3a010d3, 0xe121f001, 0xe2400080, 0xe1a0d000, 0xe3a010df, 0xe121f001, 
+    0xe2400c02, 0xe1a0d000, 0xe3a010d3, 0xe121f001, 0xe59f0020, 0xe59f1014, 0xe59f2020, 0xe4802004, 
+    0xe1500001, 0xbafffffc, 0xe59fc014, 0xe12fff1c, 0x00057800, 0x00057000, 0x0004ec74, 0x00050274, 
+    0xa5a5a5a5, 0x000005b0, 0xe3a00701, 0xe3a02008, 0xee191f11, 0xe2011d3e, 0xe1811000, 0xe1811102, 
+    0xe3811001, 0xee091f11, 0xf57ff04f, 0xe12fff1e, 0xfa000000, 0xfa000035, 0xe890a00a, 0x44820c00, 
+    0xf1aa4483, 0x45da0701, 0xf000d101, 0xf2aff861, 0xe8ba0e09, 0xf013000f, 0xbf180f01, 0xf0431afb, 
+    0x47180301, 0x0002e84c, 0x0002e8ac, 0xf04f440a, 0xf8100c00, 0xf0133b01, 0xbf080407, 0x4b01f810, 
+    0xbf08111d, 0x5b01f810, 0xd0051e64, 0x6b01f810, 0xf8011e64, 0xd1f96b01, 0x0f08f013, 0xf810bf1e, 
+    0x1cad4b01, 0xd1091b0c, 0xbf581e6d, 0xcb01f801, 0xe005d5fa, 0x6b01f814, 0x6b01f801, 0xd5f91e6d, 
+    0xd3d64291, 0x00004770, 0xbf243a10, 0xc178c878, 0x0752d8fa, 0xc830bf24, 0xbf44c130, 0x600c6804, 
+    0x00004770, 0x24002300, 0x26002500, 0xbf283a10, 0xd8fbc178, 0xbf280752, 0xbf48c130, 0x4770600b, 
+    0xe89db51f, 0xf02a0003, 0xbd1ffd3a, 0xbd10b510, 0xff83f02a, 0xf7ff4611, 0xf000fff3, 0xf02af8bd, 
+    0xb403ffa1, 0xfff2f7ff, 0xf02abc03, 0x0000ffcf, 0x4ff8e92d, 0x0800f04f, 0x0005468a, 0x46464604, 
+    0xd0184647, 0xf02d4608, 0x4602fac7, 0x2000460b, 0x4180f04f, 0xfb0cf02c, 0x9124f8df, 0x20004602, 
+    0x4649460b, 0xf8ecf02d, 0x464b2200, 0xf82cf02d, 0x91004683, 0x2000e00c, 0xe8bd4601, 0x4b408ff8, 
+    0x22000864, 0x46394630, 0xf81ef02d, 0x460f4606, 0xd8f42c01, 0x46394630, 0xfa5af02d, 0x20014601, 
+    0xf02d4088, 0x4604fa82, 0x46284689, 0xfa94f02d, 0x4622464b, 0xf8c4f02d, 0x9b00e035, 0x4620465a, 
+    0xf02d4629, 0xd332fa9d, 0xe0232000, 0x462b4622, 0x46194610, 0xfad0f02d, 0x46042200, 0x0801f108, 
+    0xf04f460d, 0xf02d4380, 0xd811fbc5, 0xfa002001, 0xf02df008, 0x4602fa5a, 0x4921460b, 0xf02d2000, 
+    0x4632f89f, 0xf02c463b, 0x4606ffdf, 0xe004460f, 0x0001f109, 0x46814550, 0xf04fd3d8, 0x462032ff, 
+    0xf02e4629, 0x45d0f8d0, 0x460d4604, 0x4630d3c5, 0xe7a24639, 0x4606b570, 0x461d4614, 0x0104e9dd, 
+    0xfa06f02d, 0x4630b2c1, 0xff72f7ff, 0x462b4622, 0xfc9ef02d, 0x4b0c4a0b, 0xf872f02d, 0x22004b0b, 
+    0xfa8af02d, 0xf04f4b0a, 0xf02d3233, 0x4b09fbb9, 0xf02d2200, 0xf02dfa81, 0xb280f9eb, 0x0000bd70, 
+    0x3ff00000, 0x4ea4a8c1, 0x400a9340, 0x40340000, 0x40333333, 0x40240000, 0xbff4f002, 0xe28fc0bf, 
+    0xe12fff1c, 0x68124afa, 0xd00b4210, 0x68104af9, 0x6f00f5b0, 0x4bf8da06, 0xf843681b, 0x68101020, 
+    0x60101c40, 0xb5104770, 0xf7ff4604, 0x2000ffeb, 0xf85af007, 0x46204601, 0x4010e8bd, 0xb570e7e2, 
+    0x4605460c, 0xf00948ed, 0x4621f91c, 0xf7ff4628, 0x4ceaffea, 0x68214628, 0xffd4f7ff, 0x46286861, 
+    0xffd0f7ff, 0x462868a1, 0xffccf7ff, 0x462868e1, 0x4070e8bd, 0xb570e7c6, 0x4605460c, 0xf00948e0, 
+    0x4621f9a2, 0xf7ff4628, 0x48deffce, 0xf2402200, 0xf02b71ff, 0x4601f9a4, 0xf7ff4628, 0x4cd8ffb3, 
+    0xf9b48861, 0xeb000000, 0x46284101, 0xffaaf7ff, 0xf9b488e1, 0xeb000004, 0x46284101, 0x4070e8bd, 
+    0xb570e7a0, 0x48ca4605, 0x42056800, 0x188cd016, 0x4621b152, 0xf7ff4628, 0x2000ff95, 0xf804f007, 
+    0x46284601, 0xff8ef7ff, 0x880849c7, 0xf3c01c40, 0x60080009, 0x680949c5, 0x4020f841, 0x48c4bd70, 
+    0xb5102100, 0xf943f02b, 0x212048c1, 0xf02b3064, 0x48c0f93e, 0x22462100, 0x0400f640, 0x80428001, 
+    0x80c18081, 0x48bc4621, 0xf02c6800, 0x48b2f939, 0x68004621, 0xf924f02c, 0x00a148b8, 0xe8bd6800, 
+    0xf02c4010, 0xb570b92d, 0xf240b281, 0xf3c01500, 0x2008040e, 0x52b8f04f, 0xffb3f7ff, 0xd8032cff, 
+    0xb2e049ac, 0xe0043108, 0x4f50f5b4, 0x49acd205, 0xf851b2e0, 0x47800020, 0x48a54605, 0x30644629, 
+    0xf905f02b, 0x462148a2, 0xf901f02b, 0xf64f48a0, 0x307471ff, 0xf8fbf02b, 0xf248489d, 0xe8bd0100, 
+    0x30704070, 0xb8f3f02b, 0xf2414899, 0xb5101122, 0xf02b3066, 0x4896f8ec, 0x30642108, 0xf8e7f02b, 
+    0xbd102008, 0xf00db510, 0xb2c1f812, 0x30684890, 0xf8ddf02b, 0x88014893, 0x3066488d, 0xf8d7f02b, 
+    0xbd102004, 0xb510488a, 0xf02b3068, 0x498df8cd, 0x20018008, 0xf973f00d, 0xbd102004, 0xb510488a, 
+    0x0000f990, 0x4882b281, 0xf02b3066, 0x2004f8c0, 0x487fbd10, 0x3066b510, 0xf8b6f02b, 0x70084982, 
+    0xbd102004, 0xb5104881, 0x48797801, 0xf02b3066, 0x487ff8ae, 0x48767801, 0xf02b3068, 0x487df8a8, 
+    0x48737801, 0xf02b306a, 0x2004f8a2, 0x4870bd10, 0x3066b510, 0xf898f02b, 0xb2c04974, 0x28014c74, 
+    0xd0037008, 0x70202000, 0xbd102004, 0x30684868, 0xf88af02b, 0x4870e7f7, 0xb5104a70, 0x78127800, 
+    0x010cf000, 0x0003f000, 0xeb010209, 0x4a6c1182, 0xeb017812, 0xeb011102, 0x496a0080, 0x44087809, 
+    0x485bb281, 0xf02b3066, 0x4867f872, 0xf86cf02b, 0x48574601, 0xf02b3068, 0x4863f86a, 0xf02b1c80, 
+    0x4601f863, 0x306a4852, 0xf861f02b, 0x1d00485e, 0xf85af02b, 0x484e4601, 0xf02b306c, 0x485bf858, 
+    0x01017800, 0x306e484a, 0xf851f02b, 0xbd102004, 0xb5704847, 0xf02b3066, 0x4604f847, 0x306e4844, 
+    0xf842f02b, 0xb205494f, 0x0003f004, 0x200c7008, 0x2014ea00, 0x0181f3c4, 0x49474408, 0xf3c47008, 
+    0x49471001, 0xf3c47008, 0x49441081, 0x48387008, 0xf02b3068, 0x4946f829, 0x48358008, 0xf02b306a, 
+    0x4944f823, 0x48328008, 0xf02b306c, 0x4942f81d, 0x04208008, 0xf3c5d502, 0xe0001006, 0x493b2000, 
+    0x20047008, 0xb510bd70, 0x22014c3c, 0x46202102, 0xf835f02b, 0x48264601, 0xf02b3066, 0x2206f808, 
+    0x21404620, 0xf82bf02b, 0x48214601, 0xf02a3068, 0x2205fffe, 0x21204620, 0xf821f02b, 0x481c4601, 
+    0xf02a306a, 0x2004fff4, 0x4819bd10, 0x3066b510, 0xffeaf02a, 0x22014c29, 0x46032102, 0xf02b4620, 
+    0x4813f800, 0xf02a3068, 0x2206ffdf, 0x21404603, 0xf02a4620, 0x480efff6, 0xf02a306a, 0x2205ffd5, 
+    0x21204603, 0xf02a4620, 0x2004ffec, 0x0000bd10, 0x00057ffc, 0x00057ff0, 0x00040234, 0x000434e0, 
+    0x000425b0, 0xf2030430, 0x00057ff4, 0x00057ff8, 0xf23c800a, 0x00040020, 0x00040230, 0x0004022c, 
+    0x000401a8, 0x000402c4, 0x000425d4, 0x00042308, 0x00042309, 0x00042352, 0x000402cc, 0x0004232a, 
+    0x00042329, 0x000402cb, 0xf2035118, 0x000402cd, 0x000402d0, 0x000402d2, 0x000402d4, 0xf38e0040, 
+    0xb51048fe, 0xff90f02a, 0x0101f000, 0x305448fb, 0xff8df02a, 0xe7b92004, 0xb51048f9, 0x48f77801, 
+    0xf02a3054, 0x2004ff84, 0x48f4e7b0, 0x3054b510, 0xff7af02a, 0x780a49f2, 0xd0034290, 0x20017008, 
+    0x700849f0, 0xe7a12004, 0x4cefb510, 0x22042300, 0x46202110, 0xff85f02a, 0x46202300, 0x21202205, 
+    0xff7ff02a, 0x48e52300, 0x461a2101, 0xff79f02a, 0xe78b2004, 0x4ce4b570, 0x2200230f, 0x46204619, 
+    0xff6ff02a, 0x7507f240, 0x46291ca0, 0xff4ff02a, 0x46291d20, 0xff4bf02a, 0x46202301, 0x21102204, 
+    0xff5ff02a, 0x46202301, 0x21202205, 0xff59f02a, 0x48d22301, 0x46192200, 0xff53f02a, 0xbd702004, 
+    0xb51048d2, 0x48cd7801, 0xf02a3054, 0x48d0ff30, 0x48ca7801, 0xf02a3056, 0x2004ff2a, 0x48c7e756, 
+    0x3054b510, 0xff20f02a, 0x700849c8, 0x305648c3, 0xff1af02a, 0x700849c6, 0xe7472004, 0xb51048c5, 
+    0x48be7801, 0xf02a3054, 0x48c3ff12, 0x48bb7801, 0xf02a3056, 0x48c1ff0c, 0x48b87801, 0xf02a3058, 
+    0x2004ff06, 0x48b5e732, 0x3054b510, 0xfefcf02a, 0x700849b9, 0xe7292004, 0xb51048b9, 0x0000f990, 
+    0xd0092804, 0xd0072805, 0xd0052803, 0xd0242802, 0xd0222801, 0xe7192008, 0x23014cab, 0x46192200, 
+    0x46203c82, 0xfefdf02a, 0x46202301, 0x21082203, 0xfef7f02a, 0x46202301, 0x21042202, 0xfef1f02a, 
+    0xf02a1ca0, 0x1d20fed1, 0xfecef02a, 0x46202300, 0x461a2101, 0xfee5f02a, 0x4ca2e03b, 0x220f2301, 
+    0x462003d9, 0xfeddf02a, 0x46202301, 0x0399220e, 0xfed7f02a, 0x46202301, 0x461a2102, 0xfed1f02a, 
+    0x46202300, 0x21022201, 0xfecbf02a, 0x46202301, 0x46192200, 0xfec5f02a, 0x3c0a4c92, 0xf02a4620, 
+    0x4620fea3, 0xfea0f02a, 0x46201ca4, 0xfe9cf02a, 0xf02a4620, 0x1ca4fe99, 0xf02a4620, 0x4620fe95, 
+    0xfe92f02a, 0x46201ca4, 0xfe8ef02a, 0xf02a4620, 0x2004fe8b, 0xe92de6ba, 0x487847f0, 0xf02a3054, 
+    0x4d76fe83, 0x487eb2c4, 0x1cae3556, 0x0804f105, 0x0000f990, 0x0906f105, 0xd0082804, 0xd0062805, 
+    0xd0042803, 0xd04e2802, 0xd04c2801, 0x4f6ee080, 0x22032301, 0x21083f82, 0xf02a4638, 0x2301fe82, 
+    0x22024638, 0xf02a2104, 0xb114fe7c, 0xd01b2c01, 0x4865e06e, 0xf02a387e, 0x4601fe57, 0xf02a4628, 
+    0x4861fe56, 0xf02a3880, 0x4601fe4f, 0xf02a4630, 0x485dfe4e, 0xf02a3876, 0x4601fe47, 0xf02a4640, 
+    0x4859fe46, 0xe0193878, 0x387a4857, 0xfe3cf02a, 0x46284601, 0xfe3bf02a, 0x387c4853, 0xfe34f02a, 
+    0x46304601, 0xfe33f02a, 0x3872484f, 0xfe2cf02a, 0x46404601, 0xfe2bf02a, 0x3874484b, 0xfe24f02a, 
+    0x46484601, 0xb114e032, 0xd0122c01, 0x4c4de030, 0x46201fa4, 0xfe18f02a, 0x46304601, 0xfe17f02a, 
+    0xf02a4620, 0x4601fe11, 0xf02a4628, 0x1ca4fe10, 0x4c44e010, 0x46203c08, 0xfe06f02a, 0x46304601, 
+    0xfe05f02a, 0xf02a4620, 0x4601fdff, 0xf02a4628, 0x1ea4fdfe, 0xf02a4620, 0x4601fdf7, 0xf02a4648, 
+    0x4620fdf6, 0xfdf0f02a, 0x46404601, 0xfdeff02a, 0xe8bd2004, 0x482987f0, 0x3056b510, 0xfde4f02a, 
+    0x70204c31, 0x30544825, 0xfddef02a, 0xb2c07821, 0xfcb7f00c, 0xe6092004, 0x220e482c, 0x0100f244, 
+    0xf02ab510, 0x4a1dfdfc, 0xb1083254, 0xe0002101, 0x46102100, 0xfdcbf02a, 0x78014823, 0x30564817, 
+    0xfdc5f02a, 0xe5f12004, 0x48212301, 0x46192200, 0xf02ab510, 0x481efdd6, 0xf02a3044, 0x4601fdb5, 
+    0x3054480e, 0xfdb3f02a, 0x30464819, 0xfdacf02a, 0x480a4601, 0xf02a3056, 0x4815fdaa, 0xf02a3048, 
+    0x4601fda3, 0x30584805, 0xfda1f02a, 0x304a4810, 0xfd9af02a, 0x48014601, 0xe01b305a, 0xf23c801c, 
+    0x00042325, 0x00042382, 0xf203526c, 0x00042326, 0x00042327, 0x0004232e, 0x0004232c, 0x0004232d, 
+    0x0004024c, 0xf38f215e, 0x00042381, 0xf38f2050, 0xf2030406, 0xfd7bf02a, 0xe5a72004, 0xb51048fe, 
+    0x48fe7801, 0xfd73f02a, 0x780148fd, 0x1c8048fb, 0xfd6df02a, 0xe5992004, 0xb51048f8, 0xfd64f02a, 
+    0x700849f5, 0x1c8048f5, 0xfd5ef02a, 0x700849f4, 0xe58b2004, 0x4cf3b510, 0x0000f994, 0x48efb281, 
+    0xfd55f02a, 0x28027820, 0x48ecd108, 0xf02a3062, 0x4601fd4b, 0x1c8048e9, 0xfd49f02a, 0xe5752004, 
+    0x41f0e92d, 0xf02a48e5, 0x49e6fd3f, 0x4de3b240, 0xf8df4fe5, 0x356a8388, 0x37104ee3, 0x70082802, 
+    0x0862f108, 0x2801d040, 0xf01ad07e, 0x2300f831, 0x22034638, 0xf02a2108, 0x2300fd2d, 0x22014628, 
+    0xf02a2102, 0x2301fd3e, 0x220a4628, 0xf02a0299, 0x2301fd38, 0x220b4628, 0xf02a02d9, 0x2301fd32, 
+    0x21024638, 0xf02a461a, 0x2301fd15, 0x21024630, 0xf02a461a, 0x2300fd0f, 0x22014638, 0xf02a2102, 
+    0x2300fd09, 0x22014630, 0xf02a2102, 0x2300fd03, 0x21014628, 0xf02a461a, 0x2100fd14, 0xf02a4640, 
+    0x2004fcf6, 0x81f0e8bd, 0x1c8048bc, 0xfcecf02a, 0x2c1ab2c4, 0x2c2ad00b, 0x2c3ad009, 0x2c0bd007, 
+    0x2c0cd005, 0x2c0dd003, 0x2c0ed001, 0x4621d1e9, 0xf02a4640, 0x2208fcdc, 0x23014628, 0xf02a0151, 
+    0x2301fcf0, 0x22094628, 0xf02a0259, 0x2301fcea, 0x22004628, 0xf02a4619, 0x48abfce4, 0x303049ab, 
+    0xfcbff02a, 0x46302301, 0x21042202, 0xfcc2f02a, 0x46382301, 0x21042202, 0xfcbcf02a, 0x220048a4, 
+    0xf990b261, 0xe0000000, 0xf01ae005, 0x49a1f81a, 0x70082001, 0xf019e7b5, 0xe778fe56, 0xb510489e, 
+    0x48967801, 0xfca3f02a, 0x7801489c, 0x1c804893, 0xfc9df02a, 0x7801489a, 0x1d004890, 0xfc97f02a, 
+    0xe4c32004, 0xb510488d, 0xfc8ef02a, 0x70084992, 0x1c80488a, 0xfc88f02a, 0x70084990, 0x1d004887, 
+    0xfc82f02a, 0x7008498e, 0xe4af2004, 0x4c8db570, 0x210f2200, 0xf02a4620, 0x2200fca2, 0x213f4605, 
+    0xf02a1ca0, 0xb206fc9c, 0x7100f641, 0x46202208, 0xfc95f02a, 0x46042200, 0x210f4883, 0xfc8ff02a, 
+    0xf366b200, 0xf360251f, 0x4874241f, 0xb2a4b2a9, 0xf02a1c80, 0x4871fc5c, 0x1d004621, 0xfc57f02a, 
+    0x2100486e, 0xf02a1d80, 0x486cfc52, 0x30082100, 0xfc4df02a, 0xbd702004, 0x47f0e92d, 0xf02a4867, 
+    0x4d66fc43, 0x2910ea4f, 0x1cad4c70, 0xf02a4628, 0xfa4ffc3b, 0x4628f880, 0xfc36f02a, 0xf3401cad, 
+    0x46282707, 0xfc30f02a, 0x4628b246, 0xfc2cf02a, 0x2507f340, 0x1d804859, 0xfc26f02a, 0x280f0a00, 
+    0x2000d900, 0x0189eb09, 0x45435663, 0x190ad110, 0x3001f992, 0xd10b42bb, 0x3002f992, 0xd10742b3, 
+    0x2003f992, 0xd10342aa, 0x2020f994, 0xd0024282, 0x22014b57, 0xf1b9701a, 0xf8040f00, 0x44218001, 
+    0x708e704f, 0xf88470cd, 0xd10c0020, 0x800ff884, 0x74272200, 0x74664649, 0x74a54620, 0xf9ebf029, 
+    0x2008b108, 0x2004e605, 0x4847e603, 0x21012200, 0xb510385a, 0xfc13f02a, 0x48384601, 0xf02a1c80, 
+    0x4841fbe6, 0x21012200, 0xf02a387a, 0x4601fc08, 0x1d004832, 0xfbdbf02a, 0xe4072004, 0xb570482f, 
+    0x1c804c3a, 0xfbd0f02a, 0x482c4605, 0xf02a1d00, 0x4601fbcb, 0xf884b2e8, 0x22000022, 0xf884b2c9, 
+    0xf0271021, 0x2004f807, 0x4832bd70, 0xf02ab510, 0x4601fbbb, 0xf02a4821, 0x482efbba, 0xf02a1c80, 
+    0x4601fbb3, 0x1c80481d, 0xfbb1f02a, 0x1d004829, 0xfbaaf02a, 0x48194601, 0xf02a1d00, 0x4825fba8, 
+    0xf02a1d80, 0x4601fba1, 0x1d804814, 0xfb9ff02a, 0xe4102004, 0x5ffce92d, 0x4d20491f, 0x0608f105, 
+    0x1000f991, 0xd0032903, 0xd0012905, 0xd1002904, 0x2000b180, 0xf8252180, 0xf8261010, 0x1c401010, 
+    0x2804b2c0, 0xe8bdd3f7, 0x49145ffc, 0x31084813, 0xbf86f007, 0xe0254812, 0x00042354, 0xf23c8070, 
+    0x00042355, 0x000425a2, 0xf0008160, 0x00501bd0, 0x00040292, 0x00042356, 0x00042328, 0x000425f9, 
+    0x000425f3, 0xf303a0c8, 0xf303a220, 0x0004e200, 0x00042382, 0xf23d0144, 0x0004024c, 0x00040010, 
+    0x000434e0, 0xfacdf008, 0x9400f8df, 0xf8df2400, 0xf06fb400, 0x4fff0aea, 0x087ef06f, 0x200049fe, 
+    0x465a4bfe, 0x0100e9cd, 0x0024f859, 0xf942f7ff, 0xf080fa0a, 0x287fb200, 0x0014f825, 0x207fdd03, 
+    0x0014f825, 0x4540e003, 0xf825da01, 0xf9368014, 0xf9351014, 0x42810014, 0x5d39dc02, 0xd1032901, 
+    0x0014f826, 0x55382000, 0xb2e41c64, 0xd3d52c04, 0xe92de799, 0x48ea47ff, 0xfb16f02a, 0x70284de9, 
+    0xf00848e2, 0x4fe1fa8e, 0xf8df2400, 0xae028384, 0x9388f8df, 0x49e02000, 0x464b4642, 0x0100e9cd, 
+    0x0024f857, 0xf906f7ff, 0x0014f826, 0xb2641c64, 0xdbef2c04, 0xf8bd48da, 0x1c801008, 0xfaf7f02a, 
+    0xf8bd48d7, 0x1d00100a, 0xfaf1f02a, 0xf8bd48d4, 0x1d80100c, 0xfaebf02a, 0xf8bd48d1, 0x3008100e, 
+    0xfae5f02a, 0xb1107828, 0xf7ff2000, 0x2004ff43, 0xe4eeb004, 0xb51048cc, 0xfad6f02a, 0x48c84601, 
+    0xfad5f02a, 0xe4452004, 0xb51048c5, 0xfaccf02a, 0x600849c6, 0x1c8048c2, 0xfac6f02a, 0x600849c4, 
+    0x1d0048bf, 0xfac0f02a, 0x700849c2, 0xe4312004, 0xb51048be, 0xb2818800, 0xf02a48b9, 0x48bcfab8, 
+    0xb2818800, 0x1c8048b6, 0xfab1f02a, 0x780148b9, 0x1d0048b3, 0xfaabf02a, 0xe41b2004, 0xb51048b0, 
+    0xfaa2f02a, 0x600849b4, 0x1c8048ad, 0xfa9cf02a, 0x600849b2, 0x1d0048aa, 0xfa96f02a, 0x600849b0, 
+    0xe4072004, 0xb51048ac, 0xb2818800, 0xf02a48a4, 0x48aafa8e, 0xb2818800, 0x1c8048a1, 0xfa87f02a, 
+    0x880048a7, 0x489eb281, 0xf02a1d00, 0x2004fa80, 0x48a4e4a1, 0x7801b510, 0xf02a4899, 0x2004fa78, 
+    0x4897e499, 0xf02ab510, 0x499efa6f, 0x20047008, 0xe92de491, 0x200841f0, 0x0144f248, 0x52b8f04f, 
+    0xf8fff7ff, 0x26004c98, 0x78204f8d, 0xd1092801, 0x46382200, 0xf02a2103, 0xb918fa82, 0x70064893, 
+    0xf8d5f00c, 0x46382200, 0xf02a2103, 0x2202fa78, 0x211c7020, 0xf02a4638, 0x498dfa72, 0x70082205, 
+    0x46382120, 0xfa6bf02a, 0x81f4f8df, 0x4c892801, 0x0802f108, 0x2208d10d, 0x7100f64f, 0xf02a4640, 
+    0xf02cfa5e, 0xf06ffa89, 0xf02d0207, 0xe9c4f8fc, 0x22060100, 0x21404638, 0xfa51f02a, 0x28014d7e, 
+    0x2200d10c, 0x21ff4640, 0xfa49f02a, 0xfa74f02c, 0x0204f06f, 0xf8e7f02d, 0x0100e9c5, 0x46382207, 
+    0xf02a2180, 0x2801fa3c, 0x4975d103, 0xe9c44873, 0x22080100, 0x01514638, 0xfa31f02a, 0xd1032801, 
+    0x48704971, 0x0100e9c5, 0xf2402209, 0x46382100, 0xfa25f02a, 0xd1012801, 0x7006486c, 0xf240220a, 
+    0x46384100, 0xfa1bf02a, 0xd1012801, 0x70064868, 0xe4f72004, 0x41f0e92d, 0xf2482008, 0xf04f0145, 
+    0xf7ff52b8, 0x4861f87e, 0x7400f64f, 0x22084d4c, 0x78034621, 0xf02a4628, 0x495df9f4, 0x46282200, 
+    0x21ff780b, 0xf9edf02a, 0x22084952, 0x0100e9d1, 0xf899f02d, 0xf9dcf02c, 0x4621b283, 0x22081cad, 
+    0xf02a4628, 0x484cf9de, 0xe9d02205, 0xf02d0100, 0xf02cf88a, 0xb283f9cd, 0x22004628, 0xf02a21ff, 
+    0x4841f9d0, 0x22001cae, 0x78032103, 0xf02a4630, 0x483ef9c8, 0x210c2202, 0x46307803, 0xf9c1f02a, 
+    0x22044d3b, 0x46302170, 0xf02a782b, 0x2300f9ba, 0x7180f64f, 0x46302207, 0xf9b3f02a, 0x1cb5782a, 
+    0xb1521cae, 0x2a014c3b, 0x2a02d078, 0x2100d077, 0xf02a4628, 0x2100f98c, 0x4f37e094, 0xe9d72203, 
+    0xf02d0100, 0xf02cf850, 0x28fff963, 0x20ffdb00, 0x4628b283, 0x21ff2200, 0xf993f02a, 0xe9d72203, 
+    0xf02d0102, 0xf02cf840, 0x28fff953, 0x20ffdb00, 0xb2834621, 0x22084628, 0xf983f02a, 0xe9d72203, 
+    0xf02d0104, 0xf02cf830, 0x28fff943, 0x20ffdb00, 0x4630b283, 0x21ff2200, 0xf973f02a, 0xe9d72203, 
+    0xf02d0106, 0xf02cf820, 0xe039f933, 0x000434e0, 0xb573eab3, 0x0004255f, 0x40300000, 0x4030ab15, 
+    0xf23c8070, 0x000402f1, 0xf23d0142, 0x00042310, 0x00042314, 0x0004230f, 0x0004231c, 0x00042320, 
+    0x00042318, 0x0004230b, 0x00042378, 0x0004235e, 0x00042379, 0x00042368, 0x00042370, 0xb71758e2, 
+    0x3fae00d1, 0x538ef34d, 0x3ff42474, 0x0004235f, 0x00042360, 0x0004e228, 0x0004e248, 0xe014e00a, 
+    0xdb0028ff, 0x462120ff, 0x4630b283, 0xf02a2208, 0xe01af928, 0x0100e9d4, 0xf91af02c, 0x4628b281, 
+    0xf905f02a, 0x0102e9d4, 0xe9d4e009, 0xf02c0104, 0xb281f90f, 0xf02a4628, 0xe9d4f8fa, 0xf02c0106, 
+    0xb281f907, 0xf02a4630, 0x2004f8f2, 0xe92de701, 0xf8df5ff0, 0x21008424, 0xf02a4640, 0xf108f8e8, 
+    0x21000902, 0xf02a4648, 0xf108f8e2, 0x21000a04, 0xf02a4650, 0xf108f8dc, 0x21000b06, 0xf02a4658, 
+    0x4cfef8d6, 0x4dff4ffe, 0xf5a08820, 0x39ff417f, 0x7838d013, 0xd1102801, 0x46282204, 0xf02a2110, 
+    0x2203f8ee, 0x21084606, 0xf02a4628, 0x4286f8e8, 0x2000d101, 0x2001e000, 0xf9978020, 0xb2810000, 
+    0xf02a4640, 0x8821f8b4, 0xf02a4648, 0x2204f8b0, 0x21104628, 0xf8d3f02a, 0x46504601, 0xf8a7f02a, 
+    0x46282203, 0xf02a2108, 0x4601f8ca, 0xf02a4658, 0x2004f89e, 0x9ff0e8bd, 0x5ff0e92d, 0xf02a48de, 
+    0x4ddef893, 0xf64f4604, 0x882970ff, 0xd1084281, 0xf2482008, 0xf04f1137, 0xf7fe52b8, 0x2008ff22, 
+    0x4ed7e7e8, 0x0a02f04f, 0x802849d3, 0x4fd61c89, 0x0000f996, 0x0b02f101, 0x8350f8df, 0x9350f8df, 
+    0xd0264284, 0xd0142c01, 0xa000f8a5, 0x7034200a, 0xf82df006, 0x48cf2301, 0x029c220a, 0xf02a4621, 
+    0x48ccf869, 0x220a2301, 0x1d004621, 0xf862f02a, 0x4608e024, 0xf858f02a, 0x46587038, 0xf854f02a, 
+    0x0000f888, 0x1d8048bc, 0xf84ef02a, 0x0000f889, 0x2c01e7dc, 0x4608d110, 0xf846f02a, 0x46587038, 
+    0xf842f02a, 0x0000f888, 0x1d8048b3, 0xf83cf02a, 0x0000f889, 0xfdfff00c, 0xa000f8a5, 0xe7992004, 
+    0x48adb570, 0xf830f02a, 0x48ab4604, 0xf02a1c80, 0xea40f82b, 0x48a84404, 0xf02a1d80, 0x4605f825, 
+    0x1d0048a5, 0xf820f02a, 0x4620b148, 0xf81cf02a, 0x48a14601, 0xf02a3008, 0x2004f81a, 0x4629bd70, 
+    0xe7f84620, 0xb51048a5, 0x68004ca3, 0x48a46020, 0x48a46060, 0x48a460a0, 0x48a460e0, 0x48a46120, 
+    0x48a46160, 0x48a461a0, 0x48a461e0, 0x48a46220, 0x62606800, 0x62a048a3, 0x62e02000, 0x63606320, 
+    0xf02463a0, 0x63e0fe73, 0xb2814620, 0x1d80488a, 0xffedf029, 0x0c014620, 0x1d004887, 0xffe7f029, 
+    0x21104885, 0xffe3f029, 0xe4062004, 0xb510488a, 0x4881b281, 0xf0291d80, 0x4887ffda, 0x487e0c01, 
+    0xf0291d00, 0x2004ffd4, 0x487be433, 0x1d80b510, 0xffcaf029, 0x48784604, 0xf0291d00, 0xeb04ffc5, 
+    0x88204400, 0x4874b281, 0xf0291c80, 0x6820ffc0, 0x48710c01, 0xffbbf029, 0xe41a2004, 0xb570486e, 
+    0xf0291d80, 0x4604ffb1, 0x1d00486b, 0xffacf029, 0x4400eb04, 0x1c804868, 0xffa6f029, 0x48664605, 
+    0xffa2f029, 0x4000eb05, 0x20046020, 0xe92dbd70, 0x4e7141f0, 0x4f742500, 0xeb072400, 0xf0290044, 
+    0xeb04ff93, 0x1c6401c5, 0x2c08b224, 0x0011f826, 0x1c6ddbf3, 0x2d40b22d, 0x2004dbee, 0x4856e599, 
+    0x1d80b510, 0xff80f029, 0x60204c60, 0x1d004852, 0xff7af029, 0xea416821, 0x60204000, 0xe4a22004, 
+    0x4c5ab510, 0xb2818820, 0x1d80484b, 0xff6ff029, 0x0c016820, 0x1d004848, 0xff69f029, 0xe4922004, 
+    0x4845b538, 0xff60f029, 0x4843b245, 0xf0291c80, 0xb244ff5b, 0x1d004840, 0xff56f029, 0xf04fb242, 
+    0x2d010000, 0x4b4cd006, 0x90004621, 0xf0042001, 0xe00bfc9d, 0x4a48494d, 0x1144eb01, 0x3010f931, 
+    0x3020f842, 0xb2401c40, 0xdbf72810, 0xbd382004, 0x2000493c, 0x6008b510, 0x0100f640, 0x68004837, 
+    0xff2ef02a, 0x2100482c, 0xff31f029, 0xe45a2004, 0x2208482c, 0x0151b570, 0xf0293854, 0x4c26ff50, 
+    0x21202205, 0x3c564603, 0xf0294620, 0x4e38ff3a, 0x21042202, 0xf0294630, 0xf242ff42, 0x46030500, 
+    0x4629220d, 0xf0294620, 0x2202ff2c, 0x21044630, 0xff35f029, 0x22004e18, 0x46032101, 0x46303e4e, 
+    0xff1ff029, 0x220f482b, 0xf02900a9, 0x2205ff28, 0x21204603, 0xf0294630, 0x4827ff14, 0x21022201, 
+    0xff1df029, 0x46032206, 0x46302140, 0xff09f029, 0x22064822, 0xf0292140, 0x220cff12, 0x10694603, 
+    0xf0294630, 0x481dfefe, 0x21022201, 0xf0291e80, 0x220dff06, 0xe0334603, 0xf23c8070, 0x0004235a, 
+    0x0004028b, 0xf38f2056, 0x00042357, 0x00042358, 0x00042359, 0xf0001030, 0x000439b0, 0x00040234, 
+    0x00057ff8, 0x00057ff0, 0x00057ff4, 0x00057ffc, 0x00057c00, 0x00057c40, 0x00057800, 0x00057c80, 
+    0x00040230, 0x00043790, 0xf203612e, 0x00043350, 0xf3074084, 0xf3078958, 0xf302012c, 0xf3074190, 
+    0x46304629, 0xfebdf029, 0x22024dfe, 0xf99548fc, 0x5c431000, 0x4620211c, 0xfeb3f029, 0x220948fa, 
+    0x6100f240, 0x46207803, 0xfeabf029, 0x220748f7, 0xf0292180, 0x2201feb4, 0x21024603, 0xf0294620, 
+    0x7828fea0, 0x4070e8bd, 0xbe35f00b, 0xf029b510, 0xb281fc2d, 0x48ee4604, 0xfe79f029, 0x0c2148ec, 
+    0xf0291c80, 0x2004fe74, 0x48e9e68f, 0x2134f241, 0x1d00b510, 0xfe6bf029, 0x46204ce6, 0x48e4b281, 
+    0xf0291c80, 0x4620fe64, 0x48e10c01, 0xfe5ff029, 0xfc1cf029, 0xf0296020, 0x6060fc39, 0xfc26f029, 
+    0xf02960a0, 0x60e0fc2b, 0xfc18f029, 0xf0296120, 0x6160fc35, 0x48d62106, 0xf0291f00, 0x2004fe48, 
+    0xe92de663, 0x48d25ff0, 0x1f002700, 0xfe3cf029, 0x48cf4604, 0xf0291e80, 0xf8dffe37, 0xf000833c, 
+    0xf3c00507, 0xf8df1602, 0xf3c4b334, 0xf3c43300, 0xf9982903, 0xf0040000, 0x2801041f, 0x2802d04a, 
+    0x2803d00d, 0x0205f04f, 0x0120f04f, 0xf8dfd004, 0xf1aaa30c, 0xe0430a60, 0x465846da, 0xf8dfe006, 
+    0x2205a2fc, 0xf1aa2120, 0xe0390a20, 0xfe29f029, 0x464b2200, 0x4650210f, 0xfe23f029, 0x48b82300, 
+    0xf643461a, 0xf02971ff, 0xf8dffe05, 0x2c1aa2d8, 0xf1c5d228, 0xf64f0008, 0xeb0071ff, 0xea010040, 
+    0xf04f2000, 0xeb0131ff, 0x48af0150, 0xfde9f029, 0x211848ab, 0xf0291f00, 0x48acfde4, 0x5146ea44, 
+    0x48a94301, 0xf0293808, 0xf89afddc, 0xf44f1000, 0xe0421080, 0xa284f8df, 0x21202205, 0x0a40f1aa, 
+    0xe7c34650, 0xf04fd102, 0xe023000b, 0xd01c2c1b, 0xd01c2c1c, 0xd01c2c1d, 0xf998200b, 0x05721000, 
+    0x3181ea42, 0x4187ea41, 0x1140ea41, 0x48964301, 0xf0293808, 0x4892fdb6, 0x1f002119, 0xfdb1f029, 
+    0x78004888, 0xd0072804, 0x200fe007, 0x2010e7e5, 0x2011e7e3, 0xe7e02701, 0x2e03006d, 0xf240d902, 
+    0xe0044000, 0xeb062001, 0x40880146, 0x2100b280, 0xeb054345, 0xebc01085, 0xf00500c0, 0xf1b9fc8d, 
+    0xd01f0f00, 0x0000f998, 0xd0142801, 0xd00c2802, 0xf04f2803, 0xf04f0301, 0xf04f0204, 0xd0020110, 
+    0x38604876, 0x4658e00c, 0x4874e00a, 0x22042301, 0x38202110, 0x4871e004, 0x22042301, 0x38402110, 
+    0xfd8ff029, 0xd2062c1a, 0x2301486f, 0x0719221c, 0xf0293808, 0xf89afd6f, 0xf44f1000, 0xf0051080, 
+    0x2004fc5b, 0x486ae4c6, 0x7801b510, 0x1f004860, 0xfd5df029, 0xe5782004, 0xb510485d, 0xf0291f00, 
+    0x4963fd53, 0x20047008, 0x4862e56f, 0xf990b510, 0xb2810000, 0x1f004856, 0xfd49f029, 0x7801485e, 
+    0x1e804853, 0xfd43f029, 0xe55e2004, 0xb5104850, 0xf0291f00, 0x4957fd39, 0x484d7008, 0xf0291e80, 
+    0x4955fd33, 0x20077008, 0xfd55f005, 0xe54c2004, 0xb5104852, 0x48467801, 0xf0291f00, 0x4850fd28, 
+    0x48437801, 0xf0291e80, 0x2004fd22, 0x4840e53d, 0x1f00b510, 0xfd18f029, 0x70084948, 0x1e80483c, 
+    0xfd12f029, 0x70084946, 0xf0052007, 0x2004fd34, 0xe92de52b, 0xf8df47f0, 0xf241910c, 0x220c0800, 
+    0x46414604, 0xf0294648, 0x4e3ffd2a, 0x4f3f2801, 0xd10c4d3f, 0x683802c1, 0xfd02f02a, 0x46412300, 
+    0x4648220c, 0xfd0df029, 0x70302000, 0xf9966028, 0x28040000, 0x6838da72, 0xf8206829, 0x68284011, 
+    0x60281c40, 0x382a4822, 0xfcdef029, 0x682a6839, 0x80c0f8df, 0xf1084c2f, 0xf821080e, 0x68280012, 
+    0x60281c40, 0xf0294620, 0x6839fccf, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4c25d9f2, 
+    0xf1043420, 0x46200802, 0xfcbef029, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 
+    0x8074f8df, 0xf1084c1c, 0x4620080e, 0xfcacf029, 0x682a6839, 0x0012f821, 0x1c406828, 0xe02e1ca4, 
+    0x0002ea36, 0x00040292, 0x000425f9, 0xf38f20a2, 0xf23c8074, 0x000439b0, 0x00040298, 0xf20308e2, 
+    0xf1000408, 0x00040293, 0xf1000488, 0x00080400, 0x000402f0, 0x0004024a, 0x0004024b, 0x00042300, 
+    0x00042301, 0xf20351a4, 0x00042348, 0x00042610, 0x0004233c, 0xf2034200, 0xf2039004, 0x4544e14f, 
+    0xd9c26028, 0x83f8f8df, 0xf1084cfd, 0x46200814, 0xfc6af029, 0x1ca46839, 0xf821682a, 0x68280012, 
+    0x60281c40, 0xd9f24544, 0x341c4cf5, 0x0802f104, 0xf0294620, 0x6839fc59, 0x682a1ca4, 0x0012f821, 
+    0x1c406828, 0x45446028, 0xf8dfd9f2, 0x4ced83b8, 0x0808f108, 0xf0294620, 0x6839fc47, 0x682a1ca4, 
+    0x0012f821, 0x1c406828, 0x45446028, 0x4ce5d9f2, 0x8390f8df, 0xf1083414, 0x4620081e, 0xfc34f029, 
+    0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0x8370f8df, 0xf1084cdb, 0x462008d2, 
+    0xfc22f029, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0xf8df4cd2, 0x3460834c, 
+    0x0802f1a8, 0xf0294620, 0x6839fc0f, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x48c9d9f2, 
+    0xf029300a, 0x6839fc01, 0xf821682a, 0x68280012, 0x60281c40, 0x300c48c3, 0xfbf6f029, 0x682a6839, 
+    0x8300f8df, 0x0850f108, 0x0012f821, 0x1c406828, 0x24006028, 0x0044eb08, 0xfbe6f029, 0x1c646839, 
+    0xf821682a, 0x68280012, 0x60281c40, 0xd9f12c07, 0x82d0f8df, 0xf1082400, 0xeb080820, 0xf0290044, 
+    0x6839fbd3, 0x682a1c64, 0x0012f821, 0x1c406828, 0x2c1f6028, 0x48add9f1, 0xfbc6f029, 0x682a6839, 
+    0x0012f821, 0x1c406828, 0x48a86028, 0xf0291c80, 0x6839fbbb, 0xf821682a, 0x68280012, 0x60281c40, 
+    0x302048a2, 0xfbb0f029, 0x682a6839, 0x0012f821, 0x1c406828, 0x489d6028, 0xf0293026, 0x6839fba5, 
+    0xf821682a, 0x68280012, 0x60281c40, 0x30404897, 0xfb9af029, 0x682a6839, 0x0012f821, 0x1c406828, 
+    0x48926028, 0xf0293042, 0x6839fb8f, 0x4c8f682a, 0x0012f821, 0x1c406828, 0x34786028, 0x0806f104, 
+    0xf0294620, 0x6839fb81, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4c85d9f2, 0x0804f104, 
+    0xf0294620, 0x6839fb71, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4c7dd9f2, 0xf1043432, 
+    0x46200804, 0xfb60f029, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 0xd9f24544, 0x34604c74, 
+    0x0804f104, 0xf0294620, 0x6839fb4f, 0x682a1ca4, 0x0012f821, 0x1c406828, 0x45446028, 0x4c6cd9f2, 
+    0x81acf8df, 0xf108347a, 0x462008b2, 0xfb3cf029, 0x1ca46839, 0xf821682a, 0x68280012, 0x60281c40, 
+    0xd9f24544, 0xf0294863, 0x6839fb2f, 0xf821682a, 0x68280012, 0x60281c40, 0x1c407830, 0xe8bd7030, 
+    0x4a5d87f0, 0x71fff640, 0x1c406810, 0xf3f1fb90, 0x0013fb01, 0x28006010, 0x4958d105, 0x1c407808, 
+    0x000ff000, 0x47708008, 0x5ff0e92d, 0x46304e54, 0xfb0af029, 0x88914a53, 0xd0484281, 0xf64fd205, 
+    0xeba373ff, 0x44010101, 0xeba0e001, 0x4f4f0101, 0xc124f8df, 0x0101f101, 0xb28d8090, 0x6839484a, 
+    0x2000f8dc, 0x0000ea45, 0x0022f841, 0xffc9f7ff, 0xa10cf8df, 0x46b12400, 0xf1aa46e0, 0xf10a0a08, 
+    0xe0220b02, 0xf0294650, 0x4606fadf, 0xf0294658, 0x683afadb, 0x4100ea46, 0x0000f8d8, 0x1020f842, 
+    0xffaff7ff, 0x1f004836, 0xfacef029, 0x46484606, 0xfacaf029, 0xea46683a, 0xf8d84100, 0xf8420000, 
+    0xf7ff1020, 0x1c64ff9e, 0x42acb2a4, 0xe559d3da, 0x2005b570, 0xf968f005, 0x4d274c2c, 0x682a6821, 
+    0x0022f841, 0xff8df7ff, 0x68214829, 0x6800682a, 0x0022f841, 0xff85f7ff, 0x30144819, 0xfaa4f029, 
+    0x48174606, 0xfaa0f029, 0xea466821, 0x682a4000, 0x0022f841, 0xff75f7ff, 0xf0294813, 0x4e17fa95, 
+    0x508df100, 0x8831682a, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x480cff66, 0xf0291c80, 0x4915fa85, 
+    0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 0xff57f7ff, 0x1d004804, 0xfa76f029, 0xe01b8831, 
+    0xf38fffc0, 0xf38f2000, 0xf38f2200, 0xf38e0000, 0xf38f0000, 0xf2039000, 0x00042330, 0x00042340, 
+    0xf23c826c, 0x00040000, 0xeeee0000, 0x0004260c, 0x00042344, 0x11b00000, 0x508ef100, 0xea40682a, 
+    0x68214001, 0x0022f841, 0xff2bf7ff, 0xf02948f7, 0x49f7fa4b, 0x4408682a, 0xea408831, 0x68214001, 
+    0x0022f841, 0xff1df7ff, 0x300a48f0, 0xfa3cf029, 0xf1008831, 0x682a5095, 0x4001ea40, 0xf8416821, 
+    0xf7ff0022, 0x48e9ff0e, 0xf029300c, 0x49e9fa2d, 0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 
+    0xfefff7ff, 0x300e48e1, 0xfa1ef029, 0xf1008831, 0x682a5096, 0x4001ea40, 0xf8416821, 0xf7ff0022, 
+    0x48dafef0, 0xf0293010, 0x49dbfa0f, 0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 0xfee1f7ff, 
+    0x302248d2, 0xfa00f029, 0xf1008831, 0x682a509d, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48cbfed2, 
+    0xf0293024, 0x49cdf9f1, 0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 0xfec3f7ff, 0x302648c3, 
+    0xf9e2f029, 0xf1008831, 0x682a509e, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48bcfeb4, 0xf0293028, 
+    0x49bff9d3, 0x4408682a, 0xea408831, 0x68214001, 0x0022f841, 0xfea5f7ff, 0x307448b4, 0xf9c4f029, 
+    0xf1008831, 0x682a50a0, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48adfe96, 0xf0293076, 0x8831f9b5, 
+    0x50a8f100, 0xea40682a, 0x68214001, 0x0022f841, 0xfe87f7ff, 0x307848a5, 0xf9a6f029, 0xf1008831, 
+    0x682a50b0, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x48a4fe78, 0xf998f029, 0xf1008831, 0x682a50b8, 
+    0x4001ea40, 0xf8416821, 0xf7ff0022, 0x489efe6a, 0xf98af029, 0xf1008831, 0x682a50c0, 0x4001ea40, 
+    0xf8416821, 0xe8bd0022, 0xe65a4070, 0xb5102005, 0xf82af005, 0x680a4995, 0xd2034282, 0x681a4b94, 
+    0x601a1c52, 0xe4166008, 0x5ff0e92d, 0x48874604, 0xf0293074, 0x2204f969, 0xf00021f0, 0x488a051f, 
+    0xf98df029, 0xf7ffb2c7, 0x4e8affe1, 0xf8df2207, 0xf8df8228, 0x6831b228, 0xf8c84658, 0xf2401000, 
+    0xf0291180, 0xf8dff97c, 0xf04f9218, 0xb3000a01, 0x46582205, 0xf0292120, 0x2801f972, 0xf899d10c, 
+    0x42850000, 0x2200d008, 0x211f4658, 0xf967f029, 0x1000f899, 0xd00c4288, 0x46582205, 0xf0292120, 
+    0xb940f95e, 0x46582200, 0xf029211f, 0x42a8f958, 0xf8c6d101, 0x2206a000, 0x21404870, 0xf94ff029, 
+    0xf899b148, 0x428d1000, 0xf899d105, 0x42870001, 0x2c00d101, 0xf889d073, 0x2c0a5000, 0xb1a4f8df, 
+    0xf8894d69, 0xd9057001, 0x0000f8db, 0xf8406829, 0xe0104021, 0xd1102c01, 0xf0294864, 0x4607f905, 
+    0x1e804862, 0xf900f029, 0xea47682a, 0xf8db4100, 0xf8400000, 0xf7ff1022, 0x4858fdd4, 0xf2402207, 
+    0xf0291180, 0xb170f91c, 0x22074854, 0x1180f240, 0xf915f029, 0x68302801, 0x77fff640, 0xb3e8d010, 
+    0xd0242801, 0xf7ffe026, 0x4d4cfe23, 0x46281dad, 0xf8daf029, 0xb2811c40, 0xf0294628, 0xe051f8d8, 
+    0xd1522801, 0x9114f8df, 0x220e0381, 0xf0294648, 0xb318f8f6, 0x30106828, 0xdb2542b8, 0x60302000, 
+    0xf8c82301, 0x220a0000, 0x02994648, 0xf8d8e038, 0xb1e00000, 0x000cf8d9, 0xd30c42b8, 0xf1f7fbb0, 
+    0x0311fb07, 0xf1016829, 0x45630c10, 0xf8d9d80c, 0x42912008, 0x42b8d808, 0xe001d21a, 0xe07ce004, 
+    0x31106829, 0xd2134281, 0xfde2f7ff, 0xf8dbe01a, 0xf04f0000, 0x682a31ff, 0x1022f840, 0xfd71f7ff, 
+    0xf8c96828, 0xf2000008, 0xf8c970ff, 0xe7eb000c, 0x60302000, 0xf8c82301, 0x48200000, 0x0299220a, 
+    0xf89ff029, 0x28016830, 0x481cd007, 0xf2402207, 0xf0291180, 0x2802f8a4, 0x4818d145, 0x21402206, 
+    0xf89df029, 0xbbacbbb0, 0x22004c19, 0x4620210f, 0xf895f029, 0x2200b370, 0x210f4620, 0xf88ff029, 
+    0xf100fa0a, 0xf240b28c, 0xe02a2500, 0xf38f2206, 0x11d00000, 0x12b00000, 0x12d00000, 0x13b00000, 
+    0x13d00000, 0xf38f2012, 0xf38f0004, 0x0004234c, 0x00042344, 0x00042334, 0x00042338, 0xf20351a4, 
+    0x00040000, 0x0004260c, 0x00042330, 0xf2039028, 0xf23c802a, 0x2100e007, 0xf0044628, 0x1e64ff2d, 
+    0x2c00b2a4, 0x48f7d1f7, 0x21012200, 0xf857f029, 0xd1022801, 0x5ff0e8bd, 0xe568e516, 0x200049f2, 
+    0x6008b510, 0x800849f1, 0x600849f1, 0xf0042005, 0x49f0fecb, 0xe6a66008, 0x4ff8e92d, 0xb3b8f8df, 
+    0x2800f240, 0x46152700, 0x460e2209, 0x46414604, 0x97004658, 0xf833f029, 0xd1112801, 0x200049e7, 
+    0x72fff640, 0xf8416809, 0x1c407020, 0xd3fa4290, 0x46412300, 0x46582209, 0xf813f029, 0xffcef7ff, 
+    0xf2482c01, 0xeb050900, 0xd0162606, 0xd02e2c02, 0xa36cf8df, 0x4ddb2c03, 0x0100f242, 0x0801f04f, 
+    0x2cfed02b, 0x2c04d07e, 0x220dd125, 0x4658465c, 0xf805f029, 0xd0762801, 0x220fe084, 0x465c4649, 
+    0xf0284658, 0x2800fffc, 0x220ed015, 0x0100f244, 0xf0284620, 0x2800fff4, 0x220ad10d, 0x4100f240, 
+    0xf0284620, 0x2800ffec, 0x48c7d105, 0x48c7e000, 0xf7ff4430, 0xe8bdfe49, 0x220d8ff8, 0x46584654, 
+    0x7002f88a, 0xffdbf028, 0xd1032801, 0x20aaf64a, 0xfa9ff7ff, 0xf44f4fbe, 0x46ca0000, 0x900046d9, 
+    0x4ab5e00d, 0x46682100, 0xf0043a2a, 0x2801ff2a, 0x48b8d0e1, 0xf7ff4430, 0xf884fe27, 0x220f8002, 
+    0x46484651, 0xffbbf028, 0xd1d42801, 0x46280381, 0xf028220e, 0x2800ffb4, 0x2204d1cd, 0x21104628, 
+    0xffadf028, 0xd1c62800, 0x46282205, 0xf0282120, 0x2800ffa6, 0x2203d1bf, 0x21084638, 0xff9ff028, 
+    0xd1b82800, 0x46382204, 0xf0282110, 0x2800ff98, 0x2205d1b1, 0x21204638, 0xff91f028, 0xd1aa2800, 
+    0xe001220a, 0xe009e008, 0x4100f240, 0xf0284648, 0x2800ff86, 0xe79ed0b5, 0xe79a4897, 0x30bbf64b, 
+    0xfa47f7ff, 0xf640220b, 0x46200100, 0xff77f028, 0xf04f0001, 0x465630dd, 0x7002f88a, 0x4647d007, 
+    0xf04f4683, 0x46ca0802, 0x4900f240, 0xf8dfe056, 0xf44fa208, 0x46470100, 0xf1aa4683, 0xf2400a2a, 
+    0x91004800, 0x2101e00b, 0x46684652, 0xfeb9f004, 0xd0d02801, 0xb33078b0, 0xf7ff2000, 0x220ffdb5, 
+    0x46204649, 0xff4bf028, 0xd1c42801, 0x46280381, 0xf028220e, 0x2800ff44, 0x2204d1bd, 0x21104628, 
+    0xff3df028, 0xd1b62801, 0x22044874, 0xf02821f0, 0x2801ff36, 0x220ad0af, 0x46204641, 0xff2ff028, 
+    0xd0d02800, 0x4658e747, 0xfd8ef7ff, 0xe7d670b7, 0xf244220e, 0x46280100, 0xff21f028, 0x78b02800, 
+    0x2802d008, 0xf04fd007, 0xf7ff30ee, 0xf886fd7d, 0xe0038002, 0x2000b1c0, 0xfd76f7ff, 0x4651220f, 
+    0xf0284620, 0x2801ff0c, 0x2204d185, 0x21104628, 0xff05f028, 0xd1d52801, 0x4649220a, 0xf0284620, 
+    0x2800fefe, 0xe716d0d4, 0xf7ff4658, 0x70b7fd5d, 0x4853e7e4, 0xf028b510, 0x2200fec7, 0x20014601, 
+    0xfd5ff7fd, 0x1c80484e, 0xfebef028, 0x46012200, 0xf7fd2001, 0x484afd56, 0xf0281d00, 0x2200feb5, 
+    0xe8bd4601, 0x20014010, 0xbd4bf7fd, 0x460cb570, 0x22004615, 0x20014601, 0xfd43f7fd, 0x46212200, 
+    0xf7fd2001, 0x4629fd3e, 0x4070e8bd, 0x20012200, 0xbd37f7fd, 0x41f0e92d, 0xf2482008, 0xf04f0125, 
+    0xf7fd52b8, 0x4d37fd2e, 0xf242220d, 0x46280100, 0xfeb5f028, 0x4604220c, 0x0100f241, 0xf0284628, 
+    0x4d31feae, 0xf1054204, 0xf1050602, 0xf1050704, 0xd01c0406, 0xf028482d, 0x4601fe77, 0xf0284628, 
+    0x482afe76, 0xf0281c80, 0x4601fe6f, 0xf0284630, 0x4826fe6e, 0xf0281d00, 0x4601fe67, 0xf0284638, 
+    0x4822fe66, 0xf0281d80, 0x4601fe5f, 0x2100e00c, 0xf0284628, 0x2100fe5c, 0xf0284630, 0x2100fe58, 
+    0xf0284638, 0x2100fe54, 0xf0284620, 0x4818fe50, 0xfe4af028, 0x48144601, 0xf0283008, 0x2004fe48, 
+    0x81f0e8bd, 0xf23c8260, 0x00042330, 0x00042340, 0x00042344, 0x0004234c, 0xf20351a4, 0x0004260c, 
+    0x00040000, 0xf2039026, 0xaaaa0000, 0xbbbb0000, 0xf2035040, 0xcccc0000, 0xdddcdddd, 0xf38f0004, 
+    0xf38e002c, 0xf38fffd4, 0xf23c8070, 0xf38f2210, 0xf3cf2008, 0x48feb570, 0xfe16f028, 0x48fc4605, 
+    0xf0281d80, 0x4604fe11, 0x1e8048f9, 0xfe0cf028, 0x220149f8, 0x80084bf9, 0x880849f7, 0xd0014285, 
+    0x800d701a, 0x780148f6, 0xd001428c, 0x7004701a, 0x1c8048ef, 0xfdf8f028, 0x48f24601, 0xfdf7f028, 
+    0xbd702004, 0xb51048eb, 0x48e98801, 0xf0281e80, 0x48e9fdee, 0x48e68801, 0xfde9f028, 0xf02848e9, 
+    0x4601fde3, 0x1c8048e2, 0xfde1f028, 0x780148e4, 0x1d8048df, 0xfddbf028, 0xe4642004, 0x41f0e92d, 
+    0x8384f8df, 0x21022201, 0xf0284640, 0xf108fdf8, 0x46050402, 0x46202201, 0xf0282102, 0xea45fdf0, 
+    0x48d30100, 0xf0281e80, 0x4dd8fdc2, 0x21042202, 0xf0284628, 0x4ed5fde4, 0x21042202, 0x360a4607, 
+    0xf0284630, 0xea47fddc, 0x48c90100, 0xfdaff028, 0x46202201, 0xf0282102, 0x2202fdd2, 0x21044604, 
+    0xf0284630, 0xea44fdcc, 0x46400600, 0x21022201, 0xfdc5f028, 0x46042202, 0x46282104, 0xfdbff028, 
+    0xea464304, 0xb2810044, 0x1c8048b9, 0xfd8ff028, 0xe7452004, 0x4ff7e92d, 0x82f4f8df, 0x4ebd4615, 
+    0x4fbd4604, 0xd5700790, 0x0900f640, 0x23014638, 0x220b4649, 0xfd95f028, 0xa2ccf8df, 0x21402206, 
+    0x46504623, 0xfd8df028, 0x2314b184, 0x7100f641, 0xf1aa2208, 0xf0280004, 0x48abfd84, 0x22042327, 
+    0x31f0f240, 0xf028389a, 0xe003fd7c, 0x0000f898, 0xfacdf006, 0xb290f8df, 0x22002308, 0x0b14f10b, 
+    0x4658211f, 0xfd6df028, 0xf6432324, 0x22087100, 0xf0284658, 0x2300fd66, 0x220b46cb, 0x46384649, 
+    0xfd5ff028, 0x46592301, 0x4630220b, 0xfd59f028, 0x46232201, 0x46d12102, 0xf0284650, 0x2207fd52, 
+    0x21804623, 0xf0284648, 0x2300fd4c, 0x220b4659, 0xf0284630, 0xf8dffd46, 0x23019234, 0x461a2102, 
+    0xf0284648, 0x9b01fd3e, 0x21012200, 0xf0284648, 0x2300fd38, 0x22014648, 0xf0282102, 0x9b01fd32, 
+    0x21042202, 0xf0284648, 0x07e8fd2c, 0xf241d070, 0x46ba0900, 0x46492301, 0x4638220c, 0xfd21f028, 
+    0x22034d79, 0x46232108, 0x46281cad, 0xfd19f028, 0x2310b17c, 0x7100f641, 0x1f282208, 0xfd11f028, 
+    0x23244871, 0xf2402204, 0x389831f0, 0xfd09f028, 0xf898e003, 0xf0060000, 0x4f6bfa5a, 0x22002308, 
+    0x211f3716, 0xf0284638, 0x2320fcfc, 0x7100f643, 0x46382208, 0xfcf5f028, 0x464f2300, 0x4649220c, 
+    0xf0284650, 0x2301fcee, 0x220c4639, 0xf0284630, 0x2201fce8, 0x21024623, 0xf0284628, 0x2204fce2, 
+    0x21104623, 0xf0284628, 0x2300fcdc, 0x220c4639, 0xf0284630, 0x4c55fcd6, 0x21022301, 0x340a461a, 
+    0xf0284620, 0x9b01fcce, 0x21012200, 0xf0284620, 0x2300fcc8, 0x22014620, 0xf0282102, 0x9b01fcc2, 
+    0x4620b003, 0xe8bd2202, 0x21044ff0, 0xbcb9f028, 0x8ffee8bd, 0xb570483e, 0xf0281e80, 0xb2c5fc95, 
+    0xf028483b, 0xb2c4fc91, 0x1c804839, 0xfc8cf028, 0x4621b2c2, 0xf7ff4628, 0x2004fefd, 0x483fbd70, 
+    0x7801b510, 0x1e804832, 0xfc81f028, 0x8800483c, 0x482fb281, 0xfc7bf028, 0xe45c2004, 0xb510482c, 
+    0xf0281e80, 0x4935fc71, 0x48297008, 0xfc6cf028, 0x60084933, 0xe44e2004, 0xb5104832, 0x0000f990, 
+    0x4823b281, 0xf0281e80, 0x482ffc62, 0x0000f990, 0x481fb281, 0xfc5bf028, 0xe43c2004, 0xb510481c, 
+    0xf0281e80, 0x4927fc51, 0x48197008, 0xfc4cf028, 0x70084925, 0xe42e2004, 0x22004925, 0x4c23b510, 
+    0x0100e9d1, 0xf02a4623, 0xf02afce7, 0xb281fc21, 0x1e80480f, 0xfc3bf028, 0x2200491e, 0xe9d14623, 
+    0xf02a0100, 0xf02afcd9, 0xb281fc13, 0xf0284808, 0x4819fc2e, 0x48067801, 0xf0281c80, 0x4918fc28, 
+    0x78094816, 0xea407800, 0x48012101, 0xe0291d00, 0xf23c8072, 0x0004237c, 0x0004237e, 0x00042382, 
+    0x0004255e, 0xf23d014e, 0xf2035336, 0xf307409a, 0x00040292, 0xf23c8306, 0xf2035026, 0x0004254e, 
+    0x00042550, 0x0004237a, 0x0004237b, 0x40c38800, 0x000402e0, 0x000402e8, 0x000402db, 0x000425de, 
+    0x000425dd, 0xfbf3f028, 0x780148ec, 0xf02848ec, 0x2004fbee, 0x48eae611, 0x3808b510, 0xfbe4f028, 
+    0x4ce8b200, 0xd0081c41, 0xfc1ff02a, 0x46232200, 0xfa66f02a, 0xe9c24ae4, 0x48e10100, 0xf0281f80, 
+    0xb200fbd3, 0xd0081c41, 0xfc0ff02a, 0x46232200, 0xfa56f02a, 0xe9c24add, 0x48d90100, 0xf0281f00, 
+    0x49dbfbc3, 0x1ea44cd6, 0x46207008, 0xfbbcf028, 0x0a014ad8, 0x70112920, 0x2020d901, 0x46207010, 
+    0xfbb2f028, 0x700849d4, 0xf02848cd, 0x49cbfbad, 0x20047008, 0x48d1e5d1, 0x7801b510, 0x380848c8, 
+    0xfba5f028, 0x780148ce, 0x1f8048c5, 0xfb9ff028, 0x780148cc, 0x1f0048c2, 0xfb99f028, 0x780148ca, 
+    0x1e8048bf, 0xfb93f028, 0x48c849c9, 0x78007809, 0x0141ea40, 0xf02848ba, 0x2004fb8a, 0x48b8e5ad, 
+    0xf028b510, 0x4604fb81, 0x380848b5, 0xfb7cf028, 0x700849ba, 0x1f8048b2, 0xfb76f028, 0xf00049b8, 
+    0x7008000f, 0x1f0048ae, 0xfb6ef028, 0xf00049b5, 0x7008000f, 0x1e8048aa, 0xfb66f028, 0x700849b2, 
+    0x0001f004, 0x700849b1, 0x0040f3c4, 0x700849b0, 0xe5822004, 0xb51048af, 0x48a17801, 0xf0283808, 
+    0x48adfb56, 0x489e7801, 0xf0281f80, 0x2004fb50, 0x489be573, 0x3808b510, 0xfb46f028, 0x700849a5, 
+    0x1f804897, 0xfb40f028, 0x700849a3, 0xe5642004, 0xb51048a2, 0x48927801, 0xf0283808, 0x2004fb38, 
+    0x488fe55b, 0x3808b510, 0xfb2ef028, 0x7008499b, 0xe5522004, 0xb510489a, 0x48897801, 0xf0283808, 
+    0x2004fb26, 0x4886e549, 0x3808b510, 0xfb1cf028, 0x70084993, 0xe5402004, 0xb5104892, 0x48807801, 
+    0xf0283808, 0x4890fb14, 0x487d7801, 0xf0281f80, 0x2004fb0e, 0x487ae531, 0x3808b510, 0xfb04f028, 
+    0x70084988, 0x1f804876, 0xfafef028, 0x70084986, 0xe5222004, 0xb5104885, 0x48717801, 0xf0283808, 
+    0x4883faf6, 0x486e7801, 0xf0281f80, 0x2004faf0, 0x486be513, 0x3808b510, 0xfae6f028, 0x7008497b, 
+    0x1f804867, 0xfae0f028, 0x48654604, 0xf0281f00, 0x4978fadb, 0x4000ea44, 0x20046008, 0xb570e4fd, 
+    0x22024d75, 0x46282104, 0xfaf9f028, 0x46042201, 0x46282102, 0xfaf3f028, 0x48594004, 0x3808b2e1, 
+    0xfac5f028, 0xbd702004, 0xb5704855, 0xf0283808, 0x4d69fabb, 0x2202b2c4, 0x21044623, 0xf0284628, 
+    0x2201fad0, 0x21024623, 0xf0284628, 0x2004faca, 0x484bbd70, 0x3808b570, 0xfaa6f028, 0xb2c0495f, 
+    0x0401f04f, 0x0200f04f, 0x700807c3, 0xd001495c, 0xe000800c, 0x43c0800a, 0xf2444b5a, 0x07850100, 
+    0xd0174859, 0x2300701a, 0xf028220e, 0x200afaaa, 0xfa4df004, 0x48552301, 0x029c220a, 0xf0284621, 
+    0x4852fa89, 0x220a2301, 0x1d004621, 0xfa82f028, 0xbd702004, 0x2301701c, 0x4849e7e6, 0x8801b510, 
+    0x3808482f, 0xfa73f028, 0xe4962004, 0xb510482c, 0xf0283808, 0x4946fa69, 0x2801b2c0, 0xd1027008, 
+    0xf0052000, 0x2004fbf2, 0x4841e487, 0x7801b510, 0x38084823, 0xfa5bf028, 0xe47e2004, 0xb510483d, 
+    0x481f7801, 0xf0283808, 0x2004fa52, 0x481ce475, 0x3808b510, 0xfa48f028, 0x70084936, 0xe46c2004, 
+    0xb5104835, 0x48167801, 0xf0283808, 0x4833fa40, 0x48137801, 0xf0281f80, 0x2004fa3a, 0x4810e45d, 
+    0x3808b510, 0xfa30f028, 0x70204c2b, 0x1f80480c, 0xfa2af028, 0x70084929, 0x28017820, 0x4c28d10c, 
+    0x23010341, 0x4620220d, 0xfa3bf028, 0x46202301, 0x0319220c, 0xfa35f028, 0xe43e2004, 0x000425df, 
+    0xf23c8078, 0x40c38800, 0x000402e0, 0x000402e8, 0x000402db, 0x000425dd, 0x000425de, 0x0004254c, 
+    0x0004261c, 0x0004261d, 0x0004254d, 0x0004261e, 0x0004261f, 0x00042554, 0x00042555, 0x00042556, 
+    0x0004230a, 0x0004255c, 0x0004255d, 0x0004230c, 0x0004230e, 0x00042570, 0xf30740ca, 0x000402b4, 
+    0x000402b6, 0x000402b5, 0xf2035180, 0xf0001030, 0x00042574, 0x000402f2, 0x000402f3, 0x000402f4, 
+    0xf23c8310, 0xf01db510, 0xf017ff77, 0xf000fb2f, 0xf000f895, 0xf023fec4, 0x2001f990, 0x0000bd10, 
+    0x48fdb570, 0x31b4f64b, 0xf9c1f028, 0x210048fb, 0xf9bdf028, 0x250148fa, 0x240049fa, 0x88004afa, 
+    0x7fe8f5b0, 0xf5b0d05e, 0xd05b7ff8, 0x7014700c, 0x600448f6, 0x600448f6, 0x700448f6, 0x800448f6, 
+    0x800448f6, 0x700448f6, 0x700448f6, 0x700448f6, 0xf0044620, 0x49f5f881, 0x48f57008, 0x48f57004, 
+    0xb1007800, 0x49f42020, 0x48f48008, 0x700449f8, 0x700448f3, 0x700448f3, 0x700548f3, 0x700548f3, 
+    0xf881203c, 0xf8814021, 0xf8814022, 0x73cc4020, 0x744c7408, 0x74cc748c, 0x7548750c, 0x75cc758c, 
+    0x764c760c, 0x76cc7688, 0x774c770c, 0x72c8728c, 0x734c730c, 0x714c738c, 0x71cc7188, 0x724c720c, 
+    0x48e449e5, 0x49e66008, 0x600848e4, 0x880048e5, 0xd00a2801, 0x0001f04f, 0x700849e3, 0xf04fd108, 
+    0xe0070002, 0x7015700d, 0xf04fe7a2, 0xe7f30002, 0x0001f04f, 0x700849dd, 0x2144f240, 0xf02848dc, 
+    0x49dcf946, 0x4000f241, 0x48db8008, 0x680049db, 0xf44f6008, 0x49da20be, 0xbd706008, 0xf007b510, 
+    0x2201fc58, 0x20051e94, 0xf0034621, 0x2201fff3, 0x20004621, 0xffeef003, 0xfaebf024, 0xff60f7ff, 
+    0xffddf7fc, 0xf997f009, 0xfc22f017, 0xf00a2001, 0xf023fa25, 0xf026fa3d, 0xf025f988, 0xf004fc9b, 
+    0x48a5fa7b, 0x384c2104, 0xf911f028, 0x4010e8bd, 0xb900f005, 0x5ff0e92d, 0x46884cc3, 0xa304f8df, 
+    0xf8dd2804, 0x461eb028, 0x46054617, 0xf6407821, 0xd0164900, 0xd02b2d05, 0xf0052000, 0x7823fafc, 
+    0x46394632, 0xf0054628, 0x2100fb56, 0xf0054628, 0x2300fc04, 0x220a4649, 0xf0284650, 0x2100f902, 
+    0x4640e043, 0xfae7f005, 0x46327823, 0x46284639, 0xfb41f005, 0x2100b157, 0xf0054628, 0x2302fbee, 
+    0x220a4649, 0xf0284650, 0xe019f8ec, 0xe7f34659, 0xf0054640, 0x7823fad0, 0x46394632, 0xf0054628, 
+    0xb1fefb2a, 0x46282100, 0xfbd7f005, 0x46492301, 0x4650220a, 0xf8d5f028, 0x7800489c, 0xd0132801, 
+    0x46082101, 0xfd4ef01a, 0x46417822, 0xf0054628, 0xf508fb84, 0xe8bd7100, 0xf04f5ff0, 0x12505280, 
+    0xbf3ff7fc, 0xe7de4659, 0x20002101, 0xe92de7ea, 0x000547f0, 0xf04f488e, 0x468a0400, 0x488d7004, 
+    0x488d7004, 0x488d7004, 0x488d7004, 0x488d7004, 0xd1247004, 0x4990488c, 0x488c7004, 0x488c7004, 
+    0x488c7004, 0x20047004, 0x498c7008, 0x498c7008, 0x498c7008, 0x488c7008, 0x488c7004, 0x488c7004, 
+    0x488c7004, 0x488c7004, 0x488c7004, 0x488c7004, 0x488c7004, 0x488c7004, 0x488c7004, 0x27017004, 
+    0x7007488b, 0x7007488b, 0x7007488b, 0x7007488b, 0x7007488b, 0x7007488b, 0x7007488b, 0x7007488b, 
+    0x7004488b, 0x7004488b, 0x7004488b, 0x7004488b, 0x7004488b, 0x7004488b, 0x7004488b, 0x7004488b, 
+    0x7004488b, 0x8004488b, 0x8004488b, 0x7004488b, 0x7004488b, 0x7004488b, 0x7004488b, 0x7004488b, 
+    0x8004488b, 0xf0072003, 0x2000fcdb, 0xfcf4f007, 0xf0072001, 0x4887fcb9, 0xf8202100, 0x1c494011, 
+    0x2904b249, 0x2001dbf9, 0xfd04f007, 0xf0072000, 0xb935fd01, 0x78014880, 0x29034880, 0x2103d020, 
+    0x487f7001, 0x0f04f1ba, 0xf8df4a3a, 0xf8dfc0ec, 0x700480ec, 0xf8df487b, 0x493990fc, 0x70044b7b, 
+    0x4e7b4879, 0xd00d4d7b, 0x2000f8cc, 0x0f05f1ba, 0x8000f8c1, 0x4a78d02c, 0x2a126812, 0xe120d029, 
+    0xe7de7007, 0x2000f8cc, 0x72b8f644, 0x8000f8c1, 0x2000f8a9, 0x28037800, 0xb1c0d01c, 0xd0162801, 
+    0xd0142802, 0x7818701c, 0x0140eb00, 0x1000eb01, 0x00c0eb06, 0x79016028, 0x7f047982, 0x79424411, 
+    0x440a7d87, 0x1b097ec1, 0x443c7e44, 0xe0c6e0e8, 0xe0f4e0c7, 0x0000e0c2, 0xf23c80ba, 0xf23c8322, 
+    0x00042576, 0x0004230c, 0x000425f3, 0x00057f7c, 0x00057f80, 0x00040285, 0x00040286, 0x00040288, 
+    0x0004028a, 0x0004028b, 0x00040292, 0x00040293, 0x0004024c, 0x000425a3, 0x00040290, 0x000402cb, 
+    0x000402cc, 0x00042556, 0x000425f5, 0x000425f7, 0x0004e200, 0x0003d090, 0x00042600, 0x1e8c2120, 
+    0x00042604, 0x0004237c, 0x00042326, 0x00042327, 0xf23d014e, 0x00042608, 0x0004022c, 0x0004260c, 
+    0x00042610, 0xf2030802, 0x0004232e, 0x0004230e, 0x0004024f, 0x00040250, 0x00040251, 0x00040252, 
+    0x00040253, 0x00040254, 0x00040255, 0x00040256, 0x00040257, 0x00040258, 0x00040259, 0x0004025a, 
+    0x0004025b, 0x0004025c, 0x0004025d, 0x0004025e, 0x0004025f, 0x00040260, 0x00040261, 0x00040262, 
+    0x00040263, 0x000402d9, 0x00042fcf, 0x00042fd0, 0x00040264, 0x00040265, 0x00040266, 0x00040267, 
+    0x00040268, 0x00040269, 0x0004026a, 0x0004026b, 0x0004026c, 0x0004026d, 0x0004026e, 0x0004026f, 
+    0x00040270, 0x00040271, 0x00040272, 0x00040273, 0x00040274, 0x00040276, 0x00040278, 0x0004027a, 
+    0x0004027b, 0x0004027c, 0x0004027d, 0x0004024e, 0x000425c4, 0x000425c6, 0x00040284, 0x00040298, 
+    0x00040294, 0x00040295, 0x0004230a, 0x00042383, 0x00042384, 0x00042618, 0x00040240, 0x70182002, 
+    0xf242e721, 0xf8a972dc, 0x78002000, 0xd0222803, 0x2801b318, 0x2802d021, 0x701cd01f, 0xeb007818, 
+    0xeb010140, 0xeb061000, 0x602800c0, 0x79827901, 0x44117f44, 0x440a7942, 0x1b097ec1, 0x31147d84, 
+    0x83c14421, 0x44217c44, 0x44217d04, 0x442279c4, 0x1c891a51, 0x701fe01f, 0x7018e7e0, 0x4afee7de, 
+    0xf241600a, 0xf8a94200, 0x78002000, 0xd0052803, 0xd07c2800, 0xd07a2801, 0xd0782802, 0x7818701c, 
+    0x0140eb00, 0x1000eb01, 0x00c0eb06, 0x7ec16028, 0x83c13114, 0xf6432178, 0x22007c80, 0x1044f8a0, 
+    0xeb022705, 0xeb000042, 0xeb061002, 0x602800c0, 0x79847901, 0xe01ef8b0, 0x79444421, 0x7c444421, 
+    0xf8904474, 0xeba4e015, 0x8444040e, 0x7c448487, 0xe01ef8b0, 0xf8904474, 0xeba4e015, 0xf890040e, 
+    0xeba4e017, 0x85c4040e, 0x85447b04, 0x86c47b44, 0xf8907ac4, 0x4474e00e, 0x87443440, 0x0448f101, 
+    0x004c8784, 0xf8a01f24, 0x79c44042, 0xe01ef8b0, 0xf8904474, 0x448ee011, 0xf8904474, 0x4474e014, 
+    0xe000f8b0, 0x5400f5c4, 0x049eeb04, 0x4048f8a0, 0xf89079c4, 0x4474e012, 0xe013f890, 0x4474448e, 
+    0x5400f5c4, 0x7a848644, 0xe009f890, 0xf5c44474, 0xf8a05400, 0x7bc4404a, 0xe010f890, 0xf8a04474, 
+    0xebac404c, 0xf8a00444, 0x3c10404e, 0xe020e000, 0x4050f8a0, 0xf8901c52, 0xb2524058, 0xe05bf890, 
+    0xf8904474, 0x4471e05c, 0xe059f890, 0xf8904421, 0x4474405a, 0xf8a01b09, 0x2a03105e, 0x7818db81, 
+    0x0140eb00, 0x1000eb01, 0x00c0eb06, 0xe8bd6028, 0x701887f0, 0xe92de763, 0x48a84ff1, 0xb0822100, 
+    0xfe25f027, 0x210048a5, 0xf0271f80, 0x48a4fe20, 0x70042400, 0xf0044620, 0xf008fe57, 0x9802fe41, 
+    0xf8a6f007, 0x7800489f, 0xd0002801, 0xf01a2000, 0x2300fc67, 0x461a200f, 0x90004619, 0xf0074618, 
+    0x9902f8c1, 0xf7ff2000, 0x4897fd62, 0x78004e99, 0x48969000, 0x78037831, 0x78024895, 0xf7ff9802, 
+    0xf8dffce9, 0x2701b254, 0xa250f8df, 0x0000f89b, 0xf88ab108, 0x48927000, 0x28126800, 0x2816d018, 
+    0x4890d016, 0x94002100, 0x9a027833, 0x00407800, 0xf018b240, 0xf017ff71, 0x488bfb92, 0x78004d8b, 
+    0xd0262803, 0xd0092801, 0x78004889, 0xe010b9e8, 0x94002100, 0x20047833, 0xe7ea9a02, 0xf917f017, 
+    0x2100702f, 0x46089400, 0x9a027833, 0xff54f018, 0x4880e012, 0x28027800, 0x2801d00b, 0x487ed005, 
+    0x21012200, 0xfddbf027, 0xf017b118, 0x702ff900, 0xf017e002, 0x702cf90a, 0xf8df2200, 0x210381e0, 
+    0xf8984877, 0xf0273000, 0xf898fdbc, 0x22000000, 0x81d4f8df, 0x0140eb00, 0x1000eb01, 0xeb014971, 
+    0xf8c800c0, 0x210f0000, 0x3068f890, 0xf027486f, 0xf04ffda8, 0x486e39ff, 0xf0274649, 0xf89bfd82, 
+    0xb1500000, 0x7800486b, 0xf04fb110, 0xe0011133, 0x21ccf04f, 0xf0274866, 0x4967fd74, 0x462f2300, 
+    0x9000f8c1, 0x240146a1, 0x46224619, 0x4900e9cd, 0xb2407828, 0xfdb0f004, 0xf0092002, 0x485ffe10, 
+    0x4a5c465d, 0x80c4495e, 0x80448084, 0xf89b8004, 0xf0053000, 0x2172fd97, 0xf7fc05a0, 0x0321fbcc, 
+    0x23004c58, 0x4620220c, 0xfd6bf027, 0xf2422300, 0x220d0100, 0xf0274620, 0x2300fd64, 0x0100f244, 
+    0x4620220e, 0xfd5df027, 0x0b00f248, 0x23004620, 0x220f4659, 0xfd55f027, 0xb1a87828, 0x20804945, 
+    0x3001f991, 0x0013f82d, 0x3000f991, 0x0013f82d, 0x3003f991, 0xf82d4668, 0xf9919013, 0xf82d1002, 
+    0xf0059011, 0xe006fcc3, 0x23014838, 0x4659220f, 0xf0273836, 0x483cfd36, 0x28057800, 0x4821d103, 
+    0x28017800, 0xf8d8d018, 0x7f800000, 0xf006b2c0, 0x4c36fdb9, 0x4a2f2000, 0x1000f994, 0xfeabf005, 
+    0x20004a2c, 0x1000f994, 0xfbbef006, 0xfb56f002, 0x46bb7838, 0xe009b128, 0x0000f8d8, 0x1e807f80, 
+    0x7829e7e4, 0x1000f240, 0xfb52f002, 0xf0062001, 0x4a20fda3, 0x1000f994, 0xf0057828, 0x4a1dfe8c, 
+    0x1000f994, 0xf0067828, 0x4813fb9f, 0xf2402200, 0x1f8071ff, 0x0000e03c, 0x2245cdc0, 0xf23c80b8, 
+    0x00042e74, 0x0004230e, 0x00042354, 0x00042327, 0x00042326, 0x000425f9, 0x0004232e, 0x00040298, 
+    0x00040240, 0x00040259, 0x00040284, 0x0004257a, 0x00042300, 0x0004024b, 0xf2035040, 0x00042383, 
+    0xf203005e, 0x00042384, 0x00042618, 0xf2030448, 0xf1000048, 0x00042598, 0x00042304, 0x000425b0, 
+    0x000425c6, 0xf20305c0, 0x00040292, 0x0004023c, 0xfcc5f027, 0x22004fde, 0x71fff240, 0x48dd8038, 
+    0xfcbdf027, 0x48dcb201, 0x461a2300, 0xf9b78001, 0xf0040000, 0x2101fd6b, 0x46082302, 0xf0042208, 
+    0xf8d8f846, 0x46470000, 0x1064f9b0, 0x0066f9b0, 0xf818f004, 0xf8906838, 0xf8902062, 0xf8901061, 
+    0xf0030060, 0xf8dffff5, 0x23008334, 0xf24f220c, 0x46400100, 0xfc6ef027, 0xf6402300, 0x22087100, 
+    0xf0274640, 0x2300fc67, 0x22044640, 0xf02721f0, 0x2300fc61, 0x210f4640, 0xf027461a, 0xf8dffc5b, 
+    0x230f82f4, 0x46192200, 0x0856f108, 0xf0274640, 0x2300fc68, 0x22074640, 0xf0272180, 0x2300fc62, 
+    0x22054640, 0xf0272120, 0x2001fc5c, 0xf9f5f01a, 0x20004bb3, 0x2000f994, 0xf01a7829, 0xf01af912, 
+    0x2000f88d, 0xff42f003, 0xff46f003, 0xff61f003, 0x0000f89b, 0x2801465c, 0xf004d101, 0xf002fc65, 
+    0x782afde6, 0x98027831, 0xf8bcf005, 0xf853f006, 0x230148a0, 0x46192200, 0xf0273826, 0x48a1fc32, 
+    0x20007801, 0xfca3f004, 0x2301489a, 0x461a2102, 0xf0273818, 0x2000fc26, 0xf822f01a, 0x8268f8df, 
+    0x22012300, 0x46402102, 0xfc1bf027, 0xb25cf8df, 0x22012300, 0x46582102, 0xfc13f027, 0x22112300, 
+    0x3100f44f, 0x4071f04f, 0xfbf4f027, 0x22002301, 0xf04f4619, 0xf0274071, 0x2100fbed, 0x0000f244, 
+    0xfadaf003, 0x21012300, 0xf04f461a, 0xf0274071, 0x2301fbe1, 0x21024640, 0xf027461a, 0x2301fbf2, 
+    0x21024658, 0xf027461a, 0x2100fbec, 0xf0082004, 0xf008ffd1, 0x7820fea3, 0xd07d2800, 0xf0092002, 
+    0x487bf8b0, 0xf0296800, 0x4a7afc00, 0xf0294b7a, 0xf029fc63, 0xb200fb9d, 0xf0082100, 0x2000fe7e, 
+    0xfe1ef008, 0xf0082001, 0x2002fe1b, 0xfe18f008, 0xf0082003, 0x4c71fe15, 0x0000f994, 0xfdccf008, 
+    0x0000f994, 0xfe5bf008, 0x21c0486d, 0xfb9ff027, 0xf9944c6c, 0xb2800000, 0xf930f025, 0xf0052001, 
+    0xf99afcce, 0x21002000, 0xf005200c, 0x2000fc4a, 0xfdeff008, 0x90002001, 0x46024603, 0xf0084601, 
+    0x2003fe6f, 0xfb54f003, 0x22007821, 0x7830782b, 0xffa3f009, 0x485d495c, 0x78007809, 0x0100e9cd, 
+    0x7803485b, 0x7802485b, 0x7801485b, 0x7800485b, 0xf89ff00a, 0xfe4ff002, 0xf64f4859, 0xf02771ff, 
+    0x4858fb66, 0xb2818800, 0x1c804855, 0xfb5ff027, 0x88004855, 0x4852b281, 0xf0273016, 0x4853fb58, 
+    0xb2818800, 0x1d00484e, 0xfb51f027, 0x2100484c, 0xf0273018, 0xe000fb4c, 0x4849e030, 0x301a2100, 
+    0xfb45f027, 0x21004846, 0xf027301c, 0x4844fb40, 0x301e2100, 0xfb3bf027, 0x23004845, 0x21102204, 
+    0xfb4ff027, 0xf8b06838, 0xf8b0106c, 0xf8b0206e, 0x44110042, 0x0051eb00, 0x8008493e, 0x493e2002, 
+    0x9000f881, 0xff69f014, 0x483c2300, 0x461a210f, 0xfb37f027, 0x4ffee8bd, 0xb802f014, 0xf0092000, 
+    0x2100f800, 0xf0084608, 0xf99afdd8, 0x46540000, 0xfd76f008, 0x0000f994, 0xfd2ef008, 0xb510e768, 
+    0xfc88f011, 0xff37f00a, 0xfd43f00b, 0xfefdf00b, 0xfb95f00c, 0xfccaf00e, 0xfbebf00f, 0xff32f00f, 
+    0xfae2f010, 0xfe5cf01b, 0xfaabf01e, 0xf963f01c, 0xf954f01d, 0xff23f021, 0xff05f01c, 0xfee1f021, 
+    0xfc3af023, 0xfa1cf021, 0x4010e8bd, 0xbcbcf01a, 0x00042582, 0xf203503c, 0x00042584, 0xf100004c, 
+    0x00042598, 0x00040293, 0xf2031008, 0xf203000a, 0x000402ac, 0xeb851eb8, 0x4054f851, 0x00040299, 
+    0xf2030864, 0x00040292, 0x000425ef, 0x000425f0, 0x000425fb, 0x000425fa, 0x000425fd, 0x000425fc, 
+    0xf203513c, 0x00042fe8, 0x00043014, 0x00057f80, 0xf2035250, 0x0004257e, 0x00042352, 0xf23c8316, 
+    0xe92d500f, 0xe59f0990, 0xfb000d59, 0xe3a02103, 0xe3a01030, 0xe3a00010, 0xfbfff098, 0xe3a02103, 
+    0xe3a01031, 0xe3a00010, 0xfbfff094, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d4070, 0xe3a00003, 
+    0xfa000d2a, 0xe3a00002, 0xfa000d28, 0xe3a00001, 0xfa000d26, 0xe3a00011, 0xfa000d24, 0xe3a00012, 
+    0xfa000d22, 0xe3a00001, 0xfb000c86, 0xe3a00002, 0xfb000c84, 0xe3a00004, 0xfb000c82, 0xe59f091c, 
+    0xfb000d3b, 0xe59f0918, 0xe3a03001, 0xe3a0200c, 0xe3011000, 0xfb009d39, 0xe59f0908, 0xe1d000d0, 
+    0xe3700001, 0x0a00000f, 0xe3a02000, 0xe3a01007, 0xe1a00002, 0xfb001505, 0xe59f18ec, 0xe3a00001, 
+    0xe59f28ec, 0xe1c100b6, 0xe1c100b4, 0xe1c100b2, 0xe1c100b0, 0xe59f08d4, 0xe59f18d8, 0xe5d03000, 
+    0xe59f08c4, 0xfa001536, 0xe59f18cc, 0xe3a00000, 0xe59f58c8, 0xe3a02000, 0xe5c10000, 0xe3a0000f, 
+    0xe1c500b0, 0xe2851000, 0xe59f08b4, 0xe5900000, 0xfa00883a, 0xe59f48ac, 0xe3a02000, 0xe5941000, 
+    0xe0800001, 0xe5840000, 0xe59f089c, 0xe2851000, 0xe5900000, 0xfa008831, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f0880, 0xe2851000, 0xe5900000, 0xfa008829, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f0864, 0xe2851000, 0xe5900000, 0xfa008821, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f0848, 0xe2851000, 0xe5900000, 0xfa008819, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f082c, 0xe2851000, 0xe5900000, 0xfa008811, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f0810, 0xe2851000, 0xe5900000, 0xfa008809, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f07f4, 0xe2851000, 0xe5900000, 0xfa008801, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe59f07d8, 0xe2851000, 0xe5900000, 0xfa0087f9, 0xe5941000, 0xe3a02000, 
+    0xe0800001, 0xe5840000, 0xe3a00007, 0xe1c500b0, 0xe59f07b4, 0xe2851000, 0xe5900000, 0xfa0087ef, 
+    0xe5941000, 0xe0800001, 0xe5840000, 0xe8bd8070, 0xe1a01000, 0xe59f0794, 0xe92d4010, 0xe1d000b0, 
+    0xe3500000, 0x13a02103, 0x13011101, 0x1a00001e, 0xe59f277c, 0xe59f077c, 0xe59f477c, 0xe1510002, 
+    0x1a000005, 0xe3a02004, 0xe3a01010, 0xfb009cc2, 0xe20000ff, 0xe3a01011, 0xea00000d, 0xe59f275c, 
+    0xe1510002, 0x1a000005, 0xe3a02005, 0xe3a01020, 0xfb009cb9, 0xe20000ff, 0xe3a01012, 0xea000004, 
+    0xe3a02003, 0xe3a01008, 0xfb009cb3, 0xe20000ff, 0xe3a01001, 0xe3500001, 0xe1c410b2, 0x0a000005, 
+    0xebffff54, 0xe3a02103, 0xe3a01001, 0xe8bd4010, 0xe3a00010, 0xeaffefb0, 0xe3a02103, 0xe3001101, 
+    0xe3a00010, 0xfbffefdd, 0xe1d400f2, 0xe3a02103, 0xe2801090, 0xe3a00010, 0xfbffefd8, 0xe59f16e4, 
+    0xe3a02103, 0xe59f06d8, 0xe5d11000, 0xe5d00000, 0xe0800201, 0xe2801c02, 0xe3a00010, 0xfbffefcf, 
+    0xe3a00005, 0xe1c400b0, 0xe59f069c, 0xe3a02000, 0xe59f16a4, 0xe5900000, 0xfa0087a8, 0xe59f1664, 
+    0xe5912000, 0xe0800002, 0xe5810000, 0xe3a00004, 0xfb000bc4, 0xe8bd4010, 0xe3a0000b, 0xea000c46, 
+    0xe92d503f, 0xe59f4614, 0xe1a00004, 0xfb000c78, 0xe3a02103, 0xe3a01032, 0xe3a00010, 0xfbffefb7, 
+    0xe1a00004, 0xebffffa9, 0xe3a02103, 0xe3a01033, 0xe3a00010, 0xfbffefb1, 0xf57ff05f, 0xe8bd503f, 
+    0xe25ef004, 0xe92d50ff, 0xe59f063c, 0xfb000c68, 0xe3a02103, 0xe3a01034, 0xe3a00010, 0xfbffefa7, 
+    0xe3a00002, 0xfa000c41, 0xe59f0620, 0xe3a03000, 0xe3a02008, 0xe3001100, 0xfb009c60, 0xe3a03000, 
+    0xe59f060c, 0xe1a02003, 0xe3a0100f, 0xfb009c5b, 0xe59f05d8, 0xe1d000b0, 0xe3500000, 0x13a02103, 
+    0x13011102, 0x1a000041, 0xe59f05e8, 0xe3a05000, 0xe59f75e4, 0xe59f458c, 0xe5d00000, 0xe3500000, 
+    0x0a000023, 0xe59f05d4, 0xe59f15d4, 0xe59f65d4, 0xe1d000d0, 0xe1d110d0, 0xe1800001, 0xe1d610d0, 
+    0xe1900001, 0x1a000033, 0xe3a00005, 0xfa000b8d, 0xe59f15b4, 0xe240093d, 0xe2400d09, 0xe3a02000, 
+    0xe5810000, 0xe3a00001, 0xe5c60000, 0xe3a0003e, 0xe1c700b0, 0xe2871000, 0xe59f0524, 0xe5900000, 
+    0xfa008756, 0xe5941000, 0xe0800001, 0xe5840000, 0xe59f0578, 0xe59f1578, 0xe5d00000, 0xe2800001, 
+    0xe2000007, 0xe0800200, 0xe0810100, 0xe5805008, 0xea000018, 0xe59f055c, 0xe5900000, 0xe3500000, 
+    0x0a000000, 0xeafffffe, 0xe59f054c, 0xe3a02000, 0xe59f1524, 0xe5d00000, 0xe3500003, 0x13500002, 
+    0x059f04b4, 0x05c05000, 0xe3a00009, 0xe1c700b0, 0xe59f04d4, 0xe5900000, 0xfa008738, 0xe5941000, 
+    0xe3a02103, 0xe0800001, 0xe3a01002, 0xe5840000, 0xe3a00010, 0xfbffef51, 0xe3a02103, 0xe3a01035, 
+    0xe3a00010, 0xfbffef4d, 0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xe92d503f, 0xe59f04e0, 0xfb000c04, 
+    0xe3a02103, 0xe3a01036, 0xe3a00010, 0xfbffef43, 0xe59f0478, 0xe1d000b0, 0xe3500000, 0x0a00000a, 
+    0xe3a02103, 0xe3011103, 0xe3a00010, 0xfbffef3b, 0xe3a02103, 0xe3a01037, 0xe3a00010, 0xfbffef37, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe59f0464, 0xe5d00000, 0xe3500000, 0x0afffff4, 0xe59f045c, 
+    0xe59f245c, 0xe1d010d0, 0xe1d220d0, 0xe1911002, 0x1affffee, 0xe3a04001, 0xe5c04000, 0xe59f0460, 
+    0xe3a03000, 0xe1a02004, 0xe3a01002, 0xfb009be3, 0xe3a00000, 0xfa000d7d, 0xe59f0448, 0xe5d00000, 
+    0xe3500000, 0x1a000003, 0xe3a00802, 0xe3001803, 0xfbffeef3, 0xfa0020ef, 0xe3a00001, 0xfa007328, 
+    0xe59f0408, 0xe59f1408, 0xe5d00000, 0xe2800001, 0xe2000007, 0xe0800200, 0xe0810100, 0xe5804008, 
+    0xe3a00005, 0xfa000b17, 0xe59f13dc, 0xe240093d, 0xe2400d09, 0xe5810000, 0xe3a00000, 0xe59f1358, 
+    0xe5c10000, 0xe3a00002, 0xfa000ba0, 0xe3a00003, 0xfa000b9e, 0xe59f0394, 0xe3a03000, 0xe3a02008, 
+    0xe3001100, 0xfb009bbd, 0xe3a02007, 0xe3a01000, 0xe3a00001, 0xfa0014e1, 0xe59f13ac, 0xe3a00043, 
+    0xe3a02000, 0xe1c100b0, 0xe59f0314, 0xe5900000, 0xfa0086d2, 0xe59f130c, 0xe5912000, 0xe0800002, 
+    0xe5810000, 0xeaffffb1, 0xe92d5fff, 0xe3a02103, 0xe3a01038, 0xe3a00010, 0xfbffeee8, 0xe59f036c, 
+    0xe3a0200e, 0xe3041000, 0xfb009bab, 0xe59f4360, 0xe3500000, 0xe59fb35c, 0x13a00000, 0x1a000003, 
+    0xe3a0200e, 0xe3041000, 0xe1a00004, 0xfb009ba2, 0xe5cb0000, 0xe59f0340, 0xfa009b8a, 0xe1a08000, 
+    0xe3a0200c, 0xe3011000, 0xe1a00004, 0xfb009b9a, 0xe59f9328, 0xe5c90000, 0xe59f0324, 0xfa009b81, 
+    0xe59f1320, 0xe6bf4070, 0xe7e003d4, 0xe5c10000, 0xe59f0314, 0xfa009b7b, 0xe6bf6070, 0xe59f030c, 
+    0xfa009b78, 0xe6bf5070, 0xe59f0304, 0xfa009b75, 0xe6bf7070, 0xe3a02000, 0xe1a01006, 0xe3a00001, 
+    0xfbffeebe, 0xe3a02000, 0xe1a01005, 0xe3a00001, 0xfbffeeba, 0xe3a02000, 0xe1a01004, 0xe3a00001, 
+    0xfbffeeb6, 0xe59fa244, 0xe5da0000, 0xe3100018, 0x0a000006, 0xe3e00000, 0xfa002286, 0xe59f22b4, 
+    0xe3041004, 0xe3a00004, 0xfbffeeac, 0xea000042, 0xe5db1000, 0xe3a02000, 0xe3a00001, 0xfbffeea7, 
+    0xe5db1000, 0xe2053c01, 0xe1da00b0, 0xe3510000, 0x13800080, 0x03c00080, 0xe1ca00b0, 0xe3150b01, 
+    0x13510000, 0xe2060010, 0x03a02000, 0x13a02001, 0xe1900003, 0x13140010, 0x0a000003, 0xe5d90000, 
+    0xe3500000, 0x03a00001, 0x0a000000, 0xe3a00000, 0xe206c020, 0xe193300c, 0x13140020, 0x0a000003, 
+    0xe5d93000, 0xe3530000, 0x03a03001, 0x0a000000, 0xe3a03000, 0xe3520000, 0x1a000005, 0xe59f2218, 
+    0xe1d220d0, 0xe1911002, 0x1a000007, 0xe1900003, 0x0a000005, 0xe59f0204, 0xe1d010d0, 0xe3510003, 
+    0x13510004, 0x13510005, 0x0bfffdea, 0xe3180003, 0x0a000011, 0xe3e00000, 0xfa00224e, 0xe59f01e0, 
+    0xe3a0106d, 0xe3a02000, 0xe1c060b2, 0xe1c040b4, 0xe1c050b6, 0xe1c070b8, 0xe1c010b0, 0xe2801000, 
+    0xe59f01c0, 0xe5900000, 0xfa00864c, 0xe59f10f4, 0xe5912000, 0xe0800002, 0xe5810000, 0xe3a02103, 
+    0xe3a01039, 0xe3a00010, 0xfbffee64, 0xe59f0198, 0xfb000b1f, 0xf57ff05f, 0xe8bd5fff, 0xe25ef004, 
+    0xe92d500f, 0xe59f0184, 0xfb000b19, 0xe3a02103, 0xe3a0103a, 0xe3a00010, 0xfbffee58, 0xe3a02103, 
+    0xe3a0103b, 0xe3a00010, 0xfbffee54, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0150, 
+    0xfb000b0b, 0xe3a02103, 0xe3a0103c, 0xe3a00010, 0xfbffee4a, 0xe59f113c, 0xe3a00008, 0xe3a02000, 
+    0xe1c100b0, 0xe59f0080, 0xe5900000, 0xfa008623, 0xe59f1050, 0xe5912000, 0xe0800002, 0xe5810000, 
+    0xe3a02103, 0xe3a0103d, 0xe3a00010, 0xfbffee3b, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xf0001104, 
+    0xf0001114, 0xf203902c, 0x000402b2, 0x000425b0, 0x0004232e, 0x00042598, 0x000425c6, 0x000402da, 
+    0x00042674, 0x00043004, 0x00040244, 0x000426bc, 0x000426cc, 0x000426dc, 0x000426ec, 0x00042708, 
+    0x0004271c, 0x0004272c, 0x0004273c, 0x0004274c, 0x00040290, 0xf0001214, 0xf2035040, 0x0004267c, 
+    0xf0001224, 0x0004232c, 0x0004232d, 0xf0001124, 0xf2035126, 0xf20352a0, 0x00042fcc, 0x00042634, 
+    0x000402d9, 0x00042fcf, 0x00042fd0, 0x000402c0, 0x00042fe8, 0x00043790, 0x00057f70, 0x000425f2, 
+    0xf0001134, 0xf2035114, 0x0004257a, 0x0004263c, 0xf2060000, 0xf38fffc0, 0x0004028d, 0xf2039048, 
+    0x0004028c, 0xf2039026, 0x0004028e, 0xf2039028, 0xf2039018, 0xf2039016, 0xcccc0000, 0x00040285, 
+    0x00040292, 0x0004e268, 0x00043244, 0xf0001144, 0xf0001154, 0xf0001164, 0x00042644, 0xe92d500f, 
+    0xe59f0d2c, 0xfb000ab2, 0xe3a02103, 0xe3a0103e, 0xe3a00010, 0xfbffedf1, 0xebfffd5e, 0xe3a02103, 
+    0xe3a01007, 0xe3a00402, 0xfbffedec, 0xe3a02103, 0xe3a0103f, 0xe3a00010, 0xfbffede8, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0ce4, 0xfb000a9f, 0xe3a02103, 0xe3a01040, 0xe3a00010, 
+    0xfbffedde, 0xe3a02103, 0xe3a01041, 0xe3a00010, 0xfbffedda, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d50ff, 0xe59f0cb0, 0xfb000a91, 0xe59f0cac, 0xfa009a84, 0xe3500000, 0x0a00001c, 0xe59f4ca0, 
+    0xe3a01001, 0xe1a00004, 0xfb009a7f, 0xe284000c, 0xe3a01000, 0xfb009a7c, 0xe30b1bbb, 0xe1a00004, 
+    0xfb009a79, 0xe59f4c7c, 0xe3a00062, 0xe1c400b0, 0xe59f0c74, 0xfa009a73, 0xe1c400b2, 0xe2841000, 
+    0xe59f0c68, 0xe3a02000, 0xe5900000, 0xfa00859b, 0xe51f11d0, 0xe5912000, 0xe0800002, 0xe5810000, 
+    0xe59f0c4c, 0xe30f1fff, 0xfb009a67, 0xea00003e, 0xe59f0c40, 0xfa009a63, 0xe3500000, 0x0a00003a, 
+    0xe59f6c34, 0xe1a00006, 0xfa009a5e, 0xe51f122c, 0xe1b007a0, 0xe51f41ec, 0xe2865074, 0xe5c10000, 
+    0x0a00002b, 0xe3a03000, 0xe3a0200f, 0xe3081000, 0xe1a00006, 0xfb009a61, 0xe3a03001, 0xe3a0200b, 
+    0xe3001800, 0xe1a00006, 0xfb009a5c, 0xe59f0bec, 0xe5d00000, 0xe3500000, 0x1a000013, 0xe1a00006, 
+    0xfa009a48, 0xe59f1bd8, 0xe7e006d0, 0xe5c10000, 0xe1a00006, 0xfa009a43, 0xe59f1bc8, 0xe7e00550, 
+    0xe5c10000, 0xe1a00006, 0xfa009a3e, 0xe59f1bb8, 0xe7e203d0, 0xe5c10000, 0xe1a00006, 0xfa009a39, 
+    0xe59f1ba8, 0xe7e102d0, 0xe5c10000, 0xe3081000, 0xe1a00005, 0xfb009a34, 0xe1d400b0, 0xe3800010, 
+    0xe1c400b0, 0xe3a00004, 0xfa000a18, 0xebfffce9, 0xea000005, 0xe30f1fff, 0xe1a00005, 0xfb009a2a, 
+    0xe1d400b0, 0xe3c00010, 0xe1c400b0, 0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xe92d500f, 0xe59f0b50, 
+    0xfb000a2b, 0xe3a02103, 0xe3a01085, 0xe3a00010, 0xfbffed6a, 0xe3a0000a, 0xfa000a04, 0xe59f0b34, 
+    0xe3a03000, 0xe3a0200a, 0xe3001400, 0xfa009a18, 0xe59f0b24, 0xe3a03000, 0xe3a0200a, 0xe3001400, 
+    0xfa009a13, 0xebfffccb, 0xe3a02103, 0xe3a01086, 0xe3a00010, 0xfbffed59, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d50ff, 0xe59f0af0, 0xe3a04001, 0xfb000a0f, 0xe51f6300, 0xe3a05001, 0xe5d60000, 
+    0xe3500001, 0x0a000002, 0xe3500002, 0x0a00001e, 0xea000044, 0xe3a02103, 0xe3a01042, 0xe3a00010, 
+    0xfbffed46, 0xe51f037c, 0xe1d000b0, 0xe3500000, 0x0a000008, 0xe3a02103, 0xe3001176, 0xe3a00010, 
+    0xfbffed3e, 0xe3a02103, 0xe3a01043, 0xe3a00010, 0xfbffed3a, 0xea000033, 0xe59f0a84, 0xfa0099e9, 
+    0xe1a01000, 0xe3a02000, 0xe3a00010, 0xfbffed33, 0xe3a03001, 0xe59f0a6c, 0xe3a02000, 0xe1a01003, 
+    0xfb0099ee, 0xebfffc9b, 0xeaffffed, 0xe3a00001, 0xfb001656, 0xe59f0a50, 0xfb001198, 0xe59f1a48, 
+    0xe3a00000, 0xe30a25bd, 0xe7913100, 0xe2800001, 0xe20000ff, 0xe1530002, 0x83a04000, 0xe3500004, 
+    0x3afffff8, 0xe59f0a24, 0xe3540000, 0x15d01000, 0xe5d00000, 0x11c51001, 0x03a01000, 0xe1c52220, 
+    0xe51f03e0, 0xe5d00000, 0xfb0006eb, 0xe59f0a00, 0xe5d00000, 0xe3500001, 0x9a00000a, 0xe51f4400, 
+    0xe3a03001, 0xe3a02000, 0xe1a01003, 0xe1a00004, 0xfb0099ca, 0xe3a03001, 0xe3a01002, 0xe1a02003, 
+    0xe1a00004, 0xfb0099c5, 0xe59f09c8, 0xe1d000d0, 0xe3500003, 0x13500005, 0x13500004, 0x1a000004, 
+    0xe59f09b4, 0xe5d00000, 0xe3500001, 0x051f04d8, 0x05c05000, 0xe3a00000, 0xe5c60000, 0xe3a0000b, 
+    0xfa000992, 0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xe92d500f, 0xe59f0984, 0xfb0009ad, 0xe3a02103, 
+    0xe3a01087, 0xe3a00010, 0xfbffecec, 0xe3a0000c, 0xfa000986, 0xe59f093c, 0xe3a03000, 0xe3a0200c, 
+    0xe3011000, 0xfa00999a, 0xe59f092c, 0xe3a03000, 0xe3a0200c, 0xe3011000, 0xfa009995, 0xebfffc4d, 
+    0xe3a02103, 0xe3a01088, 0xe3a00010, 0xfbffecdb, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 
+    0xe59f091c, 0xfb000992, 0xe3a02103, 0xe3a01044, 0xe3a00010, 0xfbffecd1, 0xe3a02103, 0xe3a01045, 
+    0xe3a00010, 0xfbffeccd, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe3a02103, 0xe3a0107f, 
+    0xe3a00010, 0xfbffecc5, 0xe59f08d8, 0xfb000980, 0xe3a02103, 0xe3a01080, 0xe3a00010, 0xfbffecbf, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f08b4, 0xfb000976, 0xe3a02103, 0xe3a0104a, 
+    0xe3a00010, 0xfbffecb5, 0xe3a02103, 0xe3a0104b, 0xe3a00010, 0xfbffecb1, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f0880, 0xfb000968, 0xe3a02103, 0xe3a01083, 0xe3a00010, 0xfbffeca7, 
+    0xe3a02103, 0xe3a01084, 0xe3a00010, 0xfbffeca3, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 
+    0xe51f4614, 0xe1a00004, 0xfb000959, 0xe3a02103, 0xe3a01023, 0xe3a00010, 0xfbffec98, 0xe1a00004, 
+    0xebfffc8a, 0xe3a02103, 0xe3a01024, 0xe3a00010, 0xfbffec92, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 
+    0xe92d503f, 0xe51f464c, 0xe1a00004, 0xfb000948, 0xe3a02103, 0xe3a01025, 0xe3a00010, 0xfbffec87, 
+    0xe1a00004, 0xebfffc79, 0xe3a02103, 0xe3a01026, 0xe3a00010, 0xfbffec81, 0xf57ff05f, 0xe8bd503f, 
+    0xe25ef004, 0xe92d500f, 0xe59f07c4, 0xfb000938, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 
+    0xe59f07b0, 0xfb000932, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f079c, 0xfb00092c, 
+    0xe3a02103, 0xe3a01085, 0xe3a00010, 0xfbffec6b, 0xe3a02103, 0xe3a01086, 0xe3a00010, 0xfbffec67, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0768, 0xfb00091e, 0xe3a02103, 0xe3a01058, 
+    0xe3a00010, 0xfbffec5d, 0xe3a02103, 0xe3a01059, 0xe3a00010, 0xfbffec59, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d503f, 0xe59f0734, 0xfb000910, 0xe3a02103, 0xe3a0105e, 0xe3a00010, 0xfbffec4f, 
+    0xe59f0720, 0xfa0098fc, 0xe59f471c, 0xe584000c, 0xe59f0718, 0xfa0098f8, 0xe6ff2070, 0xe1c420b6, 
+    0xe594000c, 0xe1b01fa0, 0xe5c41002, 0x1a000057, 0xe7e11d50, 0xe5c41000, 0xe7e41850, 0xe5c41001, 
+    0xe1a01800, 0xe1c400b8, 0xe3a00010, 0xfbffec3b, 0xe1d400d0, 0xe3500001, 0x0a000004, 0xe3500003, 
+    0x05d40001, 0x03500001, 0x0a000039, 0xea000047, 0xe1d410d1, 0xe3510007, 0x1a000024, 0xe1d420f8, 
+    0xe30f3ff8, 0xe6ff0072, 0xe1500003, 0x1309302a, 0x11500003, 0x1a00000f, 0xe1d400b6, 0xe3a01007, 
+    0xe1d11000, 0x0a000039, 0xe2001027, 0xe59f0680, 0xe3510022, 0x03a03001, 0x0a000002, 0xe3510002, 
+    0x03a03000, 0x1a000031, 0xe3a02008, 0xe3001100, 0xfb0098da, 0xea00002d, 0xe30f3fe0, 0xe1500003, 
+    0x1a000007, 0xe1d400b6, 0xe3100902, 0x0a000027, 0xe59f0640, 0xe3a03001, 0xe3a02002, 0xe3a01004, 
+    0xeafffff2, 0xe1a00802, 0xe1b00820, 0x0a000002, 0xe351001e, 0x1a00001d, 0xea000004, 0xe1d400b6, 
+    0xe3100902, 0x13a00001, 0x1b009ca0, 0xea000017, 0xe1d400b8, 0xe3041191, 0xe6ff0070, 0xe1500001, 
+    0x1a000012, 0xe5d40006, 0xe3100001, 0x0a00000f, 0xeafffffe, 0xe1d400b8, 0xe3a01001, 0xe59f25d8, 
+    0xe6ff0070, 0xe3500089, 0x05c21000, 0x0a000007, 0xe350008a, 0x05c21001, 0x0a000004, 0xe350008b, 
+    0x05c21002, 0x0a000001, 0xe350008c, 0x05c21003, 0xe3a02103, 0xe3a0105f, 0xe3a00010, 0xfbffebe7, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d500f, 0xe3a02103, 0xe3a01060, 0xe3a00010, 0xfbffebdf, 
+    0xe59f0578, 0xfb00089a, 0xe3a02103, 0xe3a01061, 0xe3a00010, 0xfbffebd9, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe3a02103, 0xe3a0107c, 0xe3a00010, 0xfbffebd1, 0xfa0011ee, 0xe59f0540, 
+    0xfb00088b, 0xe3a01001, 0xe3a00008, 0xfb0011d1, 0xe3a00000, 0xfb0011f3, 0xe3a0001e, 0xfa000863, 
+    0xe3a0001f, 0xfa000861, 0xebfffb32, 0xe3a02103, 0xe3a0107d, 0xe3a00010, 0xfbffebc0, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f04f4, 0xfb000877, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f04e0, 0xfb000871, 0xe3a0001f, 0xfb000856, 0xe59f14d4, 0xe21000ff, 0xe5c10000, 
+    0x1a000004, 0xe59f04c8, 0xe3a03000, 0xe3a0200a, 0xe3001400, 0xfb009869, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f04a8, 0xfb000860, 0xe3a02103, 0xe3a0106a, 0xe3a00010, 0xfbffeb9f, 
+    0xe3a02103, 0xe3a0106b, 0xe3a00010, 0xfbffeb9b, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 
+    0xe59f0474, 0xfb000852, 0xe3a02103, 0xe3a0104c, 0xe3a00010, 0xfbffeb91, 0xe3a00021, 0xfb000833, 
+    0xe59f1458, 0xe6af0070, 0xe51f4a60, 0xe3500000, 0xe5c10000, 0xe1d400b0, 0x0a00001a, 0xe3500000, 
+    0x0a00001e, 0xe59f1438, 0xe3a00023, 0xe3a02000, 0xe1c100b0, 0xe51f0a90, 0xe5900000, 0xfa00835f, 
+    0xe51f1ac0, 0xe5912000, 0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3001110, 0xe3800002, 
+    0xe1c400b0, 0xe3a00010, 0xfbffeb74, 0xe3a02103, 0xe3a0104d, 0xe3a00010, 0xfbffeb70, 0xf57ff05f, 
+    0xe8bd503f, 0xe25ef004, 0xe3d00002, 0xe1c400b0, 0x0bfffad8, 0xe3a02103, 0xe3a01010, 0xeafffff0, 
+    0xebfffad4, 0xeaffffe9, 0xe92d503f, 0xe59f03b4, 0xfb00081f, 0xe3a02103, 0xe3a01068, 0xe3a00010, 
+    0xfbffeb5e, 0xe51f0abc, 0xe3a0200e, 0xe3041000, 0xfb009821, 0xe51f4aa0, 0xe3500000, 0x13a00022, 
+    0x1b009bf4, 0xe5c40000, 0xe31000ff, 0xe51f4b44, 0xe1d400b0, 0x0a00001a, 0xe3500000, 0x0a000022, 
+    0xe59f1364, 0xe3a00022, 0xe3a02000, 0xe1c100b0, 0xe51f0b6c, 0xe5900000, 0xfa008328, 0xe51f1b9c, 
+    0xe5912000, 0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3001111, 0xe3800001, 0xe1c400b0, 
+    0xe3a00201, 0xfbffeb3d, 0xe3a02103, 0xe3a01069, 0xe3a00010, 0xfbffeb39, 0xf57ff05f, 0xe8bd503f, 
+    0xe25ef004, 0xe3c00001, 0xe3a01011, 0xe3a02103, 0xe1c400b0, 0xe3a00201, 0xfbffeb30, 0xe1d400b0, 
+    0xe3500000, 0x0bfffa9b, 0xeaffffee, 0xebfffa99, 0xeaffffe5, 0xe92d500f, 0xe59f02d0, 0xfb0007e4, 
+    0xe3a02103, 0xe3a01052, 0xe3a00010, 0xfbffeb23, 0xe3a02103, 0xe3a01053, 0xe3a00010, 0xfbffeb1f, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d50ff, 0xe3a02103, 0xe3a0105a, 0xe3a00010, 0xfbffeb17, 
+    0xe59f028c, 0xfb0007d2, 0xe59f6288, 0xe3a03001, 0xe1a02003, 0xe3a01002, 0xe1a00006, 0xfb0097cf, 
+    0xe59f5274, 0xe3a00001, 0xe5c50000, 0xfb005456, 0xe59f0268, 0xe3a02000, 0xe1d010b0, 0xe3a00010, 
+    0xfbffeb06, 0xe59f0258, 0xe3a02005, 0xe51f4c84, 0xe3a01020, 0xe5d00000, 0xe3500000, 0xe1d400b0, 
+    0x03a03000, 0x13a03001, 0x03c00020, 0x13800020, 0xe1c400b0, 0xe59f022c, 0xfb0097b8, 0xe59f0228, 
+    0xe5d00000, 0xe3500000, 0xe1d400b0, 0x03c00040, 0x13800040, 0xe1c400b0, 0xe6ff0070, 0xe3d00060, 
+    0x0a000011, 0xe3a02103, 0xe3a01022, 0xe3a00010, 0xfbffeaea, 0xe3a03000, 0xe3a02001, 0xe3a01002, 
+    0xe1a00006, 0xfb0097a5, 0xe3a00000, 0xe5c50000, 0xe3a02103, 0xe3a0105b, 0xe3a00010, 0xfbffeadf, 
+    0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xebfffa49, 0xeafffff6, 0xe92d503f, 0xe59f01b0, 0xfb000794, 
+    0xe3a02103, 0xe3a0104e, 0xe3a00010, 0xfbffead3, 0xe59f019c, 0xfa009783, 0xe59f1198, 0xe200001f, 
+    0xe1c100b0, 0xe59f1190, 0xe1d120f0, 0xe1500002, 0x0a000018, 0xe51f4d6c, 0xe3500000, 0xe1c100b0, 
+    0xe1d400b0, 0x0a00005e, 0xe3500000, 0x0a000066, 0xe59f1168, 0xe3a00021, 0xe3a02000, 0xe1c100b0, 
+    0xe51f0d9c, 0xe5900000, 0xfa00829c, 0xe51f1dcc, 0xe5912000, 0xe0800002, 0xe5810000, 0xe1d400b0, 
+    0xe3a02103, 0xe3a01012, 0xe3800004, 0xe1c400b0, 0xe3a00201, 0xfbffeab1, 0xe3a02103, 0xe3a0104f, 
+    0xe3a00010, 0xfbffeaad, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xf0001174, 0xf0001184, 0xf0001194, 
+    0xf23c8082, 0xf23c806e, 0x0004264c, 0xf23c800a, 0x00042fc0, 0xf23c807e, 0xf23c8084, 0xf23c800c, 
+    0x000402b3, 0x000425c0, 0x000425c1, 0x000425c2, 0x000425c3, 0xf00011a4, 0xf0001030, 0xf0001034, 
+    0xf00011b4, 0xf38f0004, 0xf38f20e0, 0x000434e0, 0x000402cd, 0x000402cf, 0x0004024c, 0x000402db, 
+    0xf00011c4, 0xf00011d4, 0xf00011e4, 0xf00011f4, 0xf0001204, 0xf0001234, 0xf0001244, 0xf0001254, 
+    0xf0001274, 0xf00012a4, 0xf1000288, 0x00042624, 0xf100028c, 0xf23c8038, 0xf23c830c, 0x0004255f, 
+    0xf00012b4, 0xf00012c4, 0xf00012e4, 0xf00012f4, 0x000402d6, 0xf20350f6, 0xf0001304, 0xf0001314, 
+    0x0004028a, 0x00042654, 0xf0001324, 0x0004265c, 0xf0001334, 0xf0001344, 0xf23c801c, 0x000425a6, 
+    0x000425a4, 0x000425a3, 0xf38f2054, 0x000425a1, 0xf0001354, 0xf2020012, 0x00040286, 0x00040288, 
+    0x00042664, 0xe3c00004, 0xe3001112, 0xe3a02103, 0xe1c400b0, 0xe3a00201, 0xfbffea60, 0xe1d400b0, 
+    0xe3500000, 0x0bfff9cb, 0xeaffffaa, 0xebfff9c9, 0xeaffffa1, 0xe92d5fff, 0xe59f0388, 0xfb000714, 
+    0xe3a02103, 0xe3a01050, 0xe3a00010, 0xfbffea53, 0xe59f4374, 0xe1a00004, 0xfa009702, 0xe59f636c, 
+    0xe1a006a0, 0xe5c60000, 0xe1a00004, 0xfa0096fd, 0xe59f735c, 0xe7e22550, 0xe51f50f4, 0xe51f4f74, 
+    0xe5c72000, 0xe5d51003, 0xe5d60000, 0xe1510000, 0x1a000004, 0xe3500004, 0x1a000023, 0xe5d53004, 
+    0xe1530002, 0x0a000025, 0xe59f9328, 0xe3510000, 0xe51f8fd0, 0x03500007, 0x0a00002a, 0xe59fa318, 
+    0xe3a03000, 0xe3a0200c, 0xe3011000, 0xe1a0000a, 0xfb0096f2, 0xe3a03000, 0xe3a0200b, 0xe3001800, 
+    0xe1a0000a, 0xfb0096ed, 0xe1d400b0, 0xe3d00008, 0x0a000022, 0xe3a00006, 0xe1c900b0, 0xe59f12d4, 
+    0xe3a02000, 0xe59f02d4, 0xe5900000, 0xfa008203, 0xe5981000, 0xe0800001, 0xe5880000, 0xe5d60000, 
+    0xe5c50003, 0xe5d70000, 0xe5c50004, 0xe5d60000, 0xe3500000, 0x01d400b0, 0x03c00008, 0x0a000001, 
+    0xe1d400b0, 0xe3800008, 0xe3a01051, 0xe3a02103, 0xe1c400b0, 0xe3a00010, 0xfbffea10, 0xf57ff05f, 
+    0xe8bd5fff, 0xe25ef004, 0xe3a0006e, 0xe1c900b0, 0xe59f1260, 0xe3a02000, 0xe59f0264, 0xeaffffe1, 
+    0xebfff974, 0xeaffffe4, 0xe92d500f, 0xe59f0254, 0xfb0006bf, 0xe3a02103, 0xe3a01074, 0xe3a00010, 
+    0xfbffe9fe, 0xe3a02103, 0xe3a01075, 0xe3a00010, 0xfbffe9fa, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f0220, 0xfb0006b1, 0xe3a02103, 0xe3a0106c, 0xe3a00010, 0xfbffe9f0, 0xe3a02103, 
+    0xe3a0106d, 0xe3a00010, 0xfbffe9ec, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f01ec, 
+    0xfb0006a3, 0xe3a02103, 0xe3a01046, 0xe3a00010, 0xfbffe9e2, 0xe3a02103, 0xe3a01047, 0xe3a00010, 
+    0xfbffe9de, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe3a02103, 0xe3a01081, 0xe3a00010, 
+    0xfbffe9d6, 0xe59f01a8, 0xe1d010b0, 0xe3510001, 0x03a01002, 0x01c010b0, 0xe3a00001, 0xfa00149a, 
+    0xe3a01000, 0xe3a00040, 0xfa0005fa, 0xe3a00000, 0xfa001495, 0xe59f017c, 0xe3a0100f, 0xfb00967a, 
+    0xe59f0174, 0xfb000682, 0xe59f0170, 0xe1d000d0, 0xe3500003, 0x13500005, 0x13500004, 0x1a00001a, 
+    0xe59f015c, 0xe3a05000, 0xe59f415c, 0xe5901000, 0xe2811001, 0xe5801000, 0xe59f0148, 0xe5d00000, 
+    0xe3500000, 0x0a000017, 0xe3a00501, 0xe3a01071, 0xfbffe99f, 0xe1d400b0, 0xe3500014, 0x9a00000a, 
+    0xe3a02103, 0xe3a01081, 0xe3a00010, 0xfbffe9ab, 0xe3a03000, 0xe59f0114, 0xe1a02003, 0xe3a01001, 
+    0xfb009666, 0xe1c450b0, 0xebfff912, 0xe3a02103, 0xe3a01082, 0xe3a00010, 0xfbffe9a0, 0xf57ff05f, 
+    0xe8bd503f, 0xe25ef004, 0xe3a00005, 0xfa0005a5, 0xe59f10dc, 0xe5911000, 0xe0400001, 0xe3500000, 
+    0xc1d400b0, 0xc2800001, 0xc1c400b0, 0xd1c450b0, 0xdaffffed, 0xeaffffde, 0xe92d500f, 0xe59f00b4, 
+    0xfb00064b, 0xe3a02103, 0xe3a0105c, 0xe3a00010, 0xfbffe98a, 0xe3a02103, 0xe3a0105d, 0xe3a00010, 
+    0xfbffe986, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0080, 0xfb00063d, 0xe3a02103, 
+    0xe3a01062, 0xe3a00010, 0xfbffe97c, 0xe3a02103, 0xe3a01063, 0xe3a00010, 0xfbffe978, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xf0001364, 0xf2020108, 0x00040284, 0x000425a0, 0x0004266c, 0xf38fffd2, 
+    0x0004274c, 0x00042f54, 0xf0001374, 0xf0001394, 0xf00013a4, 0x000402bc, 0xf20305c4, 0xf00013b4, 
+    0x00040292, 0x000402b8, 0x00042e74, 0x000425c4, 0xf20305cc, 0x000402c0, 0xf00013c4, 0xf00013d4, 
+    0x4ff0e92d, 0x49ff468b, 0x469ab087, 0x22004690, 0xe9dd6809, 0x880f9510, 0xeb00e02c, 0xf1b80180, 
+    0xeb020f00, 0xdd010441, 0xe0002101, 0x28002100, 0x2302dd01, 0x2308e000, 0x4103fb11, 0xf9334bf2, 
+    0x21006011, 0xfb02e013, 0x42731c07, 0x401cf935, 0xdd01429c, 0xe00046a6, 0x45b6469e, 0x429cda03, 
+    0x4623dd02, 0x4633e000, 0xf8251c49, 0x42b9301c, 0x1c52d3e9, 0xd3d0454a, 0x4ee40079, 0x124aea4f, 
+    0xf109fb01, 0x02c8ea42, 0xea42b20c, 0x4301014b, 0xf0414630, 0x46390780, 0xfbd3f025, 0x7100f447, 
+    0xf0254630, 0x2000fbce, 0x21019005, 0x1d33462a, 0xe9cd9004, 0x46211002, 0x90019000, 0xfbb8f000, 
+    0x7180f447, 0xf0254630, 0x0275fbbc, 0x126f2400, 0x1c64e002, 0xd20642ac, 0x46392208, 0xf0254630, 
+    0x2800fbc7, 0xb007d1f5, 0x8ff0e8bd, 0x4fffe92d, 0xb08348c4, 0x9318f8df, 0xa048f8dd, 0xe9dd6800, 
+    0x88058b10, 0x086fb22e, 0xe0102400, 0xf004fb05, 0x1000f8d9, 0xeb014632, 0xfb170340, 0xeb0af004, 
+    0xeb0b0140, 0xf0250040, 0x1c64f9db, 0x4544b224, 0xf8d9dbec, 0xac031000, 0x8100e9cd, 0x000fe894, 
+    0xff5ef7ff, 0xe92de7cf, 0xb0854fff, 0x90032000, 0x28019805, 0x9807d002, 0x2002b158, 0x92a4f8df, 
+    0x26004683, 0xf8d94634, 0x88070000, 0x0857ea4f, 0x2008e04b, 0xfb07e7f2, 0x48a7fa04, 0x900249a5, 
+    0xeb019813, 0xb970058a, 0x46394628, 0xfb58f026, 0x0000f8d9, 0x46424629, 0x3080f9b0, 0xeb009812, 
+    0xf0250046, 0xf8d9fb1c, 0x4b9c0000, 0x78814a9c, 0x0094f8d0, 0x0100e9cd, 0x46289903, 0xfc74f025, 
+    0x46424997, 0x0028f851, 0x60084994, 0xf8d94629, 0xf9b00000, 0x48923084, 0xfb12f025, 0x0000f8d9, 
+    0x99024642, 0x3084f9b0, 0xf025488c, 0x4988fb09, 0x4628b23a, 0xeb016809, 0x9902034a, 0xf970f025, 
+    0xeb061c64, 0xb2060008, 0x455cb224, 0x4880dbb3, 0x6801ac05, 0xb100e9cd, 0x000fe894, 0xfef0f7ff, 
+    0xe761b009, 0x47f0e92d, 0x00d24c76, 0x4f77b086, 0x0541ea42, 0x46384305, 0xf4456824, 0xf8dd7180, 
+    0x8824a038, 0x435c0064, 0xf884fa0f, 0xfaf9f025, 0xf2402400, 0x027e1900, 0x1c64e002, 0xd20642b4, 
+    0x46492208, 0xf0254638, 0x2800fb03, 0xf445d1f5, 0x46387100, 0xfae5f025, 0x4a642000, 0x90052101, 
+    0x46531d12, 0xe9cd9004, 0x46410102, 0x90019000, 0xf0002001, 0xb006facd, 0x87f0e8bd, 0x4ff8e92d, 
+    0x4b584698, 0xe9dd4e5a, 0x681ba90a, 0x6833881d, 0x46439300, 0xf7ff086f, 0x2400ffb5, 0xb22e46b3, 
+    0xfb17e010, 0xf8dbf004, 0xeb091000, 0xeb0a0340, 0xfb050240, 0xeb01f004, 0x46310040, 0xf942f025, 
+    0xb2241c64, 0xdbec4544, 0x8ff8e8bd, 0x4fffe92d, 0x4615b085, 0x28012200, 0xd0159203, 0x2202b1b5, 
+    0xa100f8df, 0x9b029202, 0x2000f8da, 0x4a408816, 0x68120874, 0x462a9200, 0xff84f7ff, 0x0800f04f, 
+    0xb0f0f8df, 0xe05c4645, 0xe7e92201, 0xe7e72208, 0xfb064937, 0xf8dff005, 0x680990e0, 0x0780eb0b, 
+    0xeb01464b, 0x463a0040, 0xf025b231, 0xf8daf90b, 0x46220000, 0xf9b04932, 0x46383088, 0xfa3ff025, 
+    0x0000f8da, 0x492d4622, 0x3088f9b0, 0xf0254648, 0x4a2afa36, 0x468c492a, 0xf8416810, 0x20000024, 
+    0xf8426010, 0x20010024, 0x1a31e00b, 0x3020f85c, 0x3021f84c, 0x3020f852, 0x1c40425b, 0xf842b200, 
+    0x42a03021, 0xf8dadbf1, 0x46d10000, 0x463a9b03, 0xf8d07881, 0xe9cd0094, 0x49180100, 0xf0254818, 
+    0x9812fe5d, 0xfb14b188, 0x4638f105, 0xeb0b4622, 0xf0250181, 0x1c6df9b5, 0x0004eb08, 0xf880fa0f, 
+    0x9802b22d, 0xdba34285, 0xf8d9e71a, 0x46220000, 0x308cf9b0, 0xeb009808, 0x46380148, 0xfa00f025, 
+    0x0000e7e9, 0x00042618, 0x00042684, 0xf1000100, 0x0004022c, 0x00049a00, 0x0004ba00, 0x0004d200, 
+    0x0004c200, 0x2801b570, 0xdc01460d, 0xe0004955, 0x24004955, 0x1640eb01, 0x42408828, 0xeb06b281, 
+    0xf0250044, 0x1c64fa04, 0x1cadb224, 0xdbf32c10, 0xb570bd70, 0x460e2801, 0x494adc01, 0x494ae000, 
+    0xeb012400, 0xeb051540, 0xf0250044, 0xb200f9ed, 0xf0262109, 0x4240f949, 0x0014f826, 0xb2241c64, 
+    0xdbf02c10, 0xb570bd70, 0x21204d40, 0xf0266828, 0x2400f9e7, 0xb2606829, 0xffc4f7ff, 0xb2241c64, 
+    0xdbf72c04, 0xe92dbd70, 0x460741fc, 0x4e374838, 0x71fff64f, 0x88006800, 0x01c0ea01, 0xf0266830, 
+    0x2500f9cf, 0x2f012400, 0xb1acd014, 0x68312002, 0x46222300, 0x0100e9cd, 0x46384629, 0xfd90f7ff, 
+    0xb2641c64, 0xdbee2c04, 0xb26d1c6d, 0xdbe92d04, 0x81fce8bd, 0xe7ea2001, 0xe7e82008, 0xb5102000, 
+    0xffd1f7ff, 0xf7ff2001, 0xe8bdffce, 0xe7ba4010, 0x4a1fb57c, 0x68124d1d, 0x8814682b, 0x46162200, 
+    0xf823e007, 0x1c526012, 0xf823b212, 0x1c520012, 0x42a2b212, 0x2601dbf5, 0xb1a18018, 0x20014c15, 
+    0x6300e9cd, 0x461a2300, 0x1000f994, 0xfd58f7ff, 0x23006828, 0xe9cd461a, 0xf9946000, 0x20011001, 
+    0xfd4ef7ff, 0x2400bd7c, 0x23006828, 0xb261461a, 0x6000e9cd, 0xf7ff2001, 0x1c64fd43, 0x2c04b224, 
+    0xbd7cdbf2, 0xf20304a2, 0xf20305a4, 0x0004022c, 0x00042618, 0x00042598, 0x4fffe92d, 0x4682b089, 
+    0x460f4897, 0xf64f4d98, 0x900671ff, 0x6080f500, 0xf5059005, 0x48936980, 0x90034690, 0x6080f500, 
+    0x48929002, 0x20009008, 0x48919004, 0xf8b06800, 0x9808b000, 0x045bea4f, 0x018bea01, 0xf940f026, 
+    0x4659488c, 0xf92cf026, 0xf44f4e8a, 0x60303080, 0xeb062000, 0xf9370280, 0x1c401010, 0x60510289, 
+    0xdbf62810, 0x68384f82, 0xf8d07881, 0xe9cd0094, 0x48800100, 0xe9dd9a06, 0xf0251304, 0x487dfa45, 
+    0xf0264659, 0xf44ff90d, 0x60303080, 0xeb062000, 0xf9380280, 0x1c401010, 0x60510289, 0xdbf62810, 
+    0x9b024873, 0x78816800, 0x0094f8d0, 0x0100e9cd, 0xe9dd4870, 0xf0252103, 0x2600fa27, 0x90001c60, 
+    0x9803e02c, 0xf8509902, 0x98062026, 0x1026f851, 0x3026f850, 0xfb02469c, 0x9b05f003, 0x3026f853, 
+    0xf703fb02, 0xfb014352, 0xfb010003, 0xfb01781c, 0x120f2101, 0x4639d009, 0xf830f026, 0x0026f845, 
+    0x46404639, 0xf82af026, 0xf240e004, 0xf8451000, 0x20000026, 0x0026f849, 0x1c769800, 0xdbd04286, 
+    0xe096980c, 0xe08b9816, 0xd01d2801, 0xeb014952, 0x4952264a, 0xf04f2001, 0xeb010800, 0x9000224a, 
+    0xf004fb08, 0x6828b201, 0x3011f936, 0x4b4c4358, 0x0021f843, 0x0024f855, 0x7011f932, 0x4f494378, 
+    0x0021f847, 0xe0242001, 0xeb014947, 0x4947264a, 0x1843e7e0, 0x7020f855, 0xc013f936, 0xe013f932, 
+    0xf70cfb07, 0xc020f859, 0x7c1efb0c, 0xf8474f3c, 0xf855c023, 0xf9327020, 0xf936c013, 0xfb07e013, 
+    0xf859f70c, 0x1c40c020, 0x7c0efb0c, 0xf8474f35, 0x42a0c023, 0xf108dbdd, 0xfa4f0001, 0x9800f880, 
+    0xdbbd4580, 0x27004b2f, 0x68184a2d, 0x0024f842, 0x1c60601f, 0x7024f843, 0xebabe00b, 0xf8520100, 
+    0xf8426021, 0xf8536020, 0x42491021, 0x1020f843, 0x45581c40, 0x4e1edbf1, 0x9b044a1e, 0x78816830, 
+    0x0094f8d0, 0x0100e9cd, 0x481d491e, 0xfc66f025, 0x46226830, 0xf9b09908, 0x4816308c, 0xf820f025, 
+    0x46219808, 0x0044eb00, 0xf84af026, 0x23009908, 0x1700e9cd, 0x461a9802, 0xf7ff4651, 0x9803fcb4, 
+    0xb2401e40, 0x28009003, 0xf6bf9802, 0x1c40af6d, 0x9002b240, 0xf77f2801, 0xb00daf65, 0x8ff0e8bd, 
+    0x00044a00, 0x00043a00, 0x00044200, 0x00045200, 0x00042618, 0x00049a00, 0x00046a00, 0x00047200, 
+    0x0004c200, 0x0004d200, 0x00045a00, 0x00046200, 0x5ff0e92d, 0x461f4d53, 0x46902301, 0xb030f8dd, 
+    0xf8dd460c, 0x2102a038, 0x9028f8dd, 0x4628461a, 0xf817f025, 0x20042100, 0xfeeef000, 0x2c404e4a, 
+    0x7100f643, 0x0660dd08, 0x2310d406, 0x22084630, 0xfff0f024, 0xe01f2310, 0xdd012c1f, 0xd5f406a0, 
+    0xdd082c0f, 0xd40606e0, 0x46302304, 0xf0242208, 0x2304ffe1, 0x2c07e010, 0x0720dd08, 0x2302d406, 
+    0x22084630, 0xffd6f024, 0xe0052302, 0x46302301, 0xf0242208, 0x2301ffcf, 0x22004630, 0xf024213f, 
+    0x4e31ffc9, 0x21042202, 0x1d36464b, 0xf0244630, 0x2201ffc1, 0x2102465b, 0xf0244630, 0x2200ffbb, 
+    0x21014653, 0xf0244630, 0x4e27ffb5, 0x9b0b2202, 0x36142104, 0xf0244630, 0x9b0dffad, 0x21022201, 
+    0xf0244630, 0x9b0fffa7, 0x21012200, 0xf0244630, 0x481dffa1, 0x46232200, 0x71fff64f, 0xf0241f00, 
+    0x4819ff99, 0x30084641, 0xff8bf024, 0x46391d30, 0xff87f024, 0x22002301, 0xf04f4619, 0xf0244070, 
+    0x04b4ff89, 0x3e084e10, 0x4620e00e, 0xfe72f000, 0xdc091e04, 0x46204c0d, 0xff76f024, 0x5180f440, 
+    0xf0244620, 0xe004ff74, 0xf0244630, 0x2801ff67, 0x4628d1eb, 0x5ff0e8bd, 0x22012300, 0xf0242102, 
+    0x0000bf80, 0xf203529a, 0xf000000c, 0xf203517c, 0x220048a5, 0x31fff240, 0xf024b510, 0xb200ff69, 
+    0xb5f8bd10, 0x20004605, 0xf7ff9000, 0x4c9ffff1, 0x80204e9f, 0x0000f44f, 0xe0099000, 0x46322108, 
+    0xf0004668, 0x2801fece, 0xf7ffd005, 0x8020ffe1, 0x42a88820, 0xbdf8dcf2, 0x5fffe92d, 0x9254f8df, 
+    0xf8df4607, 0x2202b254, 0x450ee9dd, 0x824cf8df, 0xf8992600, 0xf8df0000, 0xf000a248, 0xf89b0101, 
+    0xea020000, 0xf8980040, 0x43012000, 0xea002004, 0x43010082, 0x0000f89a, 0xea022208, 0x430100c0, 
+    0x22104888, 0xea027800, 0x43011000, 0x22204886, 0xea027800, 0x43011040, 0x78004884, 0xea410780, 
+    0x48796110, 0xf0243808, 0x4881fefc, 0x780001f9, 0x1100ea41, 0x38144874, 0xfef3f024, 0x9801497d, 
+    0x01c07809, 0x1101ea40, 0x3810486f, 0xfee9f024, 0x98024979, 0x01c07809, 0x1101ea40, 0x380c486a, 
+    0xfedff024, 0x1f004868, 0x210fb39f, 0xfed9f024, 0xf8984f65, 0x4b640000, 0x28013708, 0xf899d02c, 
+    0x28010000, 0xf89bd06e, 0x28010000, 0xf89ad06a, 0x28010000, 0x4621d066, 0x1d00485b, 0xfec1f024, 
+    0x46382300, 0x21062201, 0xfec4f024, 0x46382301, 0x46192200, 0xfebef024, 0x28009810, 0x4852d107, 
+    0x21042202, 0xf0243010, 0x2800fec3, 0xe8bdd067, 0xe7ff9fff, 0xe7c92100, 0x0e214858, 0x2105ea41, 
+    0xe000f890, 0xea400a20, 0xf1be6005, 0xd1100f01, 0x6200f3c5, 0xf3c500d6, 0xea462200, 0xf0010682, 
+    0x18920201, 0x0602ea46, 0x0201f000, 0x0602ea46, 0xf004b2f6, 0xf40008ff, 0xea48407f, 0xea4f0800, 
+    0xea404014, 0xf4004005, 0xea48007f, 0xf0010800, 0x4943407f, 0x0800ea48, 0x2006ea4f, 0xea407809, 
+    0x49401081, 0xea407809, 0x493f1001, 0xea407809, 0x483e0181, 0xea417800, 0x46180100, 0xfe61f024, 
+    0xe7994641, 0x88014829, 0xf0244618, 0x4826fe5a, 0x1d004621, 0xfe55f024, 0xe7922301, 0xf0002002, 
+    0x2801fd09, 0x4c22d00b, 0xf0244620, 0xb004fe4d, 0x7100f440, 0xe8bd4620, 0xf0245ff0, 0x2200be48, 
+    0x21014638, 0xfe54f024, 0xd1e72800, 0xb5fee78f, 0x23012500, 0x4629462a, 0x95004628, 0xf8f2f004, 
+    0x24004e11, 0x46233610, 0x46302203, 0xf0242108, 0x2301fe31, 0x22024630, 0xf0242104, 0x2100fe2b, 
+    0x460a9502, 0xe9cd4608, 0xf7ff1100, 0x1c64fee5, 0x2c02b264, 0xb003dbe7, 0x23004630, 0xe8bd2202, 
+    0x210440f0, 0xbe16f024, 0xf0008014, 0x00040276, 0xf203517a, 0x00040273, 0x00040271, 0x0004026c, 
+    0x0004026f, 0x00040253, 0x00040251, 0x0004024e, 0x00040259, 0x00040257, 0x00040255, 0x0004230e, 
+    0x00040264, 0x00040265, 0x00040266, 0x00040267, 0x41f0e92d, 0x4d262301, 0x4607220a, 0x4628029c, 
+    0xf0244621, 0x00a6fdfe, 0x46304639, 0xfcd4f000, 0x46212300, 0x4628220a, 0xfdf3f024, 0x46304639, 
+    0xfccaf000, 0x22012300, 0x1f282102, 0x41f0e8bd, 0xbde7f024, 0xd0002800, 0xea404608, 0xd1020341, 
+    0x0000f04f, 0x4608e000, 0x0080ea43, 0x00c1ea40, 0x1002ea40, 0x6170f440, 0xf024480e, 0x0253bdb8, 
+    0xea432801, 0xd0102302, 0x4313460a, 0x0241ea43, 0x4608b100, 0x0080ea42, 0x00c1ea40, 0xf040b280, 
+    0x48040110, 0xf024380c, 0x2200bda2, 0x0000e7ed, 0xf20350f6, 0xf20352ac, 0x41f0e92d, 0x28014afa, 
+    0xd0094607, 0x2f0249f9, 0x880e48f9, 0xf6478805, 0xd0092012, 0xd0212f03, 0x46102100, 0xfd87f024, 
+    0x46352600, 0xe0234634, 0x880c49f2, 0x4285b916, 0x4605d200, 0x4006eb05, 0xdc0142a0, 0xb2841e40, 
+    0x4080f240, 0xd2014284, 0xe0044604, 0x6f00f5b4, 0xf240d301, 0xf24074ff, 0xe0061104, 0xb9162400, 
+    0xd2004285, 0xf2404605, 0x46101100, 0xfd5ff024, 0x463148dd, 0xf0241d00, 0x48dbfd5a, 0x1d804629, 
+    0xfd55f024, 0x462148d8, 0xf0243008, 0x48d6fd50, 0xb10f3822, 0xe0002301, 0x22012300, 0xf0242102, 
+    0x48d5fd60, 0xe8bd7007, 0x48d481f0, 0xf990b510, 0x48d31000, 0xd0052903, 0xd0122904, 0xd0082905, 
+    0xe0152000, 0x21202205, 0xfd59f024, 0x48cdb180, 0x2204e005, 0xf0242110, 0xb148fd52, 0x780048ca, 
+    0x2203e006, 0xf0242108, 0xb108fd4a, 0xe7f648c7, 0x4010e8bd, 0x48bce780, 0x2112f240, 0x41f0e92d, 
+    0xf024381c, 0x48b8fd14, 0x0115f647, 0xf024381a, 0x48bffd0e, 0x2173f240, 0xfd09f024, 0x210248b2, 
+    0xf0243818, 0x48bbfd04, 0x28007800, 0x48bad07e, 0x20047801, 0x1e4040c8, 0x75fff64f, 0x3100ea05, 
+    0x381448a9, 0xfcf3f024, 0x212048a7, 0xf0243810, 0x48b2fcee, 0xf0242100, 0x48b0fcea, 0x11fef240, 
+    0xf0241c80, 0x48adfce4, 0x2300220c, 0x38160291, 0xfcf7f024, 0x4eaa48a1, 0x78004caa, 0xd07d2803, 
+    0x70602001, 0x7030203c, 0x02017830, 0xf5a11e40, 0x43017180, 0xb2894894, 0xf024380e, 0x4892fcc8, 
+    0x3103f240, 0xf024380c, 0x7830fcc2, 0xb2811e40, 0x1f80488d, 0xfcbbf024, 0x1e407830, 0x488ab281, 
+    0xf0243808, 0x4892fcb4, 0x7180f64f, 0xf0243808, 0x488ffcae, 0x6170f64f, 0xf0241f80, 0x4882fca8, 
+    0x38222110, 0xfca3f024, 0xf64a487f, 0x3820210a, 0xfc9df024, 0x78304e8c, 0x00c0f3c0, 0xfdd6f002, 
+    0x21287860, 0x40c12214, 0x488840c2, 0x2102ea41, 0xfc8df024, 0x21687860, 0x40c12254, 0x488340c2, 
+    0x2102ea41, 0xf0241c80, 0xe000fc82, 0x486ee0da, 0x0120f244, 0xf024381e, 0x487cfc7a, 0x1811f241, 
+    0x300a4641, 0xfc73f024, 0x21004878, 0xf024300c, 0x7830fc6e, 0x0040f3c0, 0xfdf9f002, 0x210c486c, 
+    0xf02430a4, 0x4e6afc64, 0x7400f641, 0x46212303, 0x22081cb6, 0xf0244630, 0xe000fc74, 0x2304e0de, 
+    0x22004630, 0xf024211f, 0x4e61fc6c, 0x22082305, 0x36a04621, 0xf0244630, 0x230afc64, 0x22004630, 
+    0xf024211f, 0x1cb6fc5e, 0x46302301, 0x21702204, 0xfc57f024, 0x46302300, 0x461a2107, 0xfc51f024, 
+    0x2100485a, 0xf02438aa, 0x4858fc32, 0x38a82100, 0xfc2df024, 0x21024855, 0xf02438bc, 0x4853fc28, 
+    0x387e2100, 0xfc23f024, 0xfedff7ff, 0x211b483e, 0xf0243844, 0x4f4ffc1c, 0x4680f240, 0x2210494c, 
+    0x46384633, 0xfc16f024, 0x46332200, 0x46384629, 0xfc10f024, 0x1d384948, 0xfc03f024, 0x23004d43, 
+    0xf24c220e, 0x35100100, 0xf0244628, 0x2302fc1a, 0x7100f643, 0x46282208, 0xfc13f024, 0x46282300, 
+    0x21c02206, 0xfc0df024, 0x46282303, 0x213f2200, 0xfc07f024, 0x23024837, 0x383c2218, 0x61e0f04f, 
+    0xfbe8f024, 0x23084d2a, 0x4621461a, 0x462835a6, 0xfbf7f024, 0x46282302, 0x21302204, 0xfbf1f024, 
+    0x46282307, 0x210f2200, 0xfbebf024, 0x21094827, 0xf024300e, 0x4821fbcc, 0x310cf244, 0xf0241e80, 
+    0x4822fbc6, 0x1d004641, 0xfbc1f024, 0x230e4d21, 0x3d302218, 0x46280421, 0xfbbcf024, 0x4628230e, 
+    0x02212210, 0xfbb6f024, 0x4621230c, 0x46282208, 0xfbb0f024, 0xe8bd4628, 0x230c41f0, 0x211f2200, 
+    0xbba8f024, 0xe6a72003, 0xf2035114, 0x000402d0, 0x000402d2, 0x000402d4, 0x000402cf, 0x00040292, 
+    0xf38f007c, 0x000402cb, 0x0004232a, 0x00042329, 0xf203050a, 0x000425f9, 0x00042383, 0xf2030818, 
+    0x000402ce, 0x000426a0, 0x000402cd, 0xf20352a6, 0xffff0000, 0xf1000040, 0x00080005, 0x7030207c, 
+    0x70602000, 0xe92de6a0, 0x48ec5ffc, 0x4ce92600, 0xf8df4637, 0x4bec83a4, 0x48e97802, 0x93acf8df, 
+    0x0180f3c2, 0x88006800, 0x48e60845, 0xb3287800, 0xc002f893, 0xc000f889, 0xc394f8df, 0xf3424be5, 
+    0x1c521200, 0x469b46e2, 0xfd84f7ff, 0x937cf8df, 0x90002000, 0x46434602, 0x0000f899, 0x2001b241, 
+    0xf894f7ff, 0xf00248dc, 0x49dbfb5e, 0x0000f899, 0x1010f831, 0xf8a92001, 0xe0151006, 0xc000f893, 
+    0xc000f889, 0xc354f8df, 0xe7d84bd5, 0x1010f938, 0xda001e0a, 0x42b14251, 0x0011dd04, 0x4251d500, 
+    0xb20e4607, 0xb2001c40, 0xd9012d80, 0xe0002180, 0x42814629, 0x1fbfdcea, 0x2800b238, 0x2000da00, 
+    0x1a289000, 0x1700f240, 0xf5a79001, 0xb2067080, 0x46052000, 0x0026f844, 0x9800e016, 0x44284659, 
+    0xf980fa0f, 0xf3c01b78, 0x46500245, 0xfc6df023, 0xf85443c0, 0x07c02026, 0x0019f938, 0x4410d021, 
+    0xb22d1c6d, 0x0026f844, 0x42a89801, 0x1c7fdce5, 0xf5b7b23f, 0xdbd87fc0, 0xf06f2600, 0x46350804, 
+    0x077ff06f, 0x0025f854, 0xf80ef027, 0xfe7af026, 0xf0274642, 0xf026f9a8, 0x287ffabb, 0x217fdb03, 
+    0x1a10e002, 0x4601e7dc, 0xdc0042b9, 0xb2494639, 0x1025f844, 0xfb011c6d, 0xb22d6600, 0xdbe12d80, 
+    0x2500489a, 0x4e9f60c6, 0x00c5eb04, 0xf8346841, 0xf3610035, 0xb281201f, 0x0045eb06, 0xfab7f024, 
+    0xb22d1c6d, 0xdbef2d40, 0x9ffce8bd, 0x47f0e92d, 0xf2404895, 0xf8df1890, 0x4e8c9254, 0x28007800, 
+    0x488dd164, 0xf00268f4, 0x488bfabe, 0xf8307831, 0x81300011, 0xf0264620, 0x498dffdf, 0xf0264607, 
+    0xf026ffef, 0x4c8bfe2f, 0x46232200, 0xfb34f026, 0x050bf06f, 0xf027462a, 0xf026f956, 0x1040fa69, 
+    0x21018070, 0xf0274638, 0xf026f97c, 0x2200fe1b, 0xf0264623, 0x462afb21, 0xf945f027, 0xfa58f026, 
+    0x80b01040, 0xfcfbf002, 0xd2064540, 0x0000f8d9, 0xd8022811, 0xf0024640, 0x4f77fced, 0x462c2500, 
+    0x4620703d, 0xf8def003, 0x428c7831, 0x4605d100, 0x42887839, 0xb2c1dd00, 0x1c647039, 0x2c04b2e4, 
+    0x495fd3ef, 0x22001c6d, 0x8e496809, 0x0065eba1, 0x1ec0b200, 0xeb0017c1, 0xf0216191, 0x1a40013f, 
+    0x4860b283, 0x380a213f, 0xfa5bf024, 0x424088b0, 0x485cb281, 0xf024380e, 0x8870fa3a, 0xb2814240, 
+    0x380c4858, 0xfa33f024, 0x42408870, 0x4855b281, 0xf0243090, 0x4859fa2c, 0xb3587800, 0x0002f9b6, 
+    0x0040eb00, 0x004ff3c0, 0xfca4f002, 0x381c484d, 0xfa1af024, 0xd2064540, 0x0000f8d9, 0xd8022811, 
+    0xf0024640, 0x484efc97, 0x220a2300, 0x4100f240, 0xfa27f024, 0x20082101, 0xfcaff002, 0xf0022000, 
+    0xf002fcf4, 0x4847fcd9, 0x28027800, 0x2803d005, 0xe009d003, 0x70fff647, 0x4841e7d6, 0x22012300, 
+    0x301e2102, 0xfa0df024, 0xe8bd7830, 0xf24f87f0, 0xea401060, 0xb2810041, 0xb5104832, 0xf0243810, 
+    0x4830f9e6, 0x4100f240, 0xf0241e80, 0x2207f9e0, 0xe8bd2101, 0x20004010, 0xbc42f002, 0x47704770, 
+    0xb570482d, 0xf6414e1e, 0x780075ff, 0x08411c40, 0x79c26830, 0x441a7943, 0x79007983, 0x44104418, 
+    0x5000f5c0, 0x48261a44, 0x46292200, 0xf02438ac, 0x6832f9e6, 0x8bd37c51, 0x44084419, 0xf5001b00, 
+    0xb2015000, 0xfb9178d0, 0xfb00f3f0, 0xb1791113, 0x7e111a40, 0x1a20b200, 0x46291a40, 0x5000f5c0, 
+    0x4817b283, 0x4070e8bd, 0x38162200, 0xb9b9f024, 0xe7ee2000, 0x00045a00, 0x00046200, 0x000402cd, 
+    0x00042618, 0x0004257a, 0x00042590, 0x000426a0, 0x8365f253, 0x7425eef5, 0x000425b8, 0xaf77a42e, 
+    0xca4fa6c1, 0xf2030510, 0x00042fcc, 0x00040240, 0x40e00000, 0x40220000, 0x000402d7, 0x00042fce, 
+    0xf20350f6, 0x000402cb, 0x460db570, 0xeb014929, 0x21001000, 0xf0244604, 0x2001f964, 0x0185eb00, 
+    0xe8bd4620, 0xf0244070, 0x4922b95c, 0x1000eb01, 0xf0242102, 0x491fb956, 0xeb01b510, 0xf0241000, 
+    0xf3c0f94d, 0xbd100040, 0x310c491a, 0x1000eb01, 0xb944f024, 0x4604b510, 0xd0091c40, 0xf7ff4620, 
+    0xb118fff3, 0xf7ff4620, 0xb108ffe6, 0xbd102000, 0xbd102001, 0x41f0e92d, 0x480e4605, 0x460f4616, 
+    0x1405eb00, 0x46202102, 0xf92bf024, 0x46394809, 0xeb003008, 0xf0241005, 0x2100f924, 0xf0244620, 
+    0x2001f920, 0x0186eb00, 0xe8bd4620, 0xf02441f0, 0x0000b918, 0xf0008100, 0xd0052801, 0xd0032802, 
+    0xd0032804, 0xd0032805, 0x47702000, 0x47702002, 0x47702001, 0x47701e40, 0xe0004088, 0x28001e40, 
+    0x4770d1fc, 0x41f0e92d, 0x460c4e51, 0x8140f8df, 0x1d374605, 0x080cf108, 0x2201e00d, 0x21024630, 
+    0xf906f024, 0xd00e2801, 0x46382200, 0xf0242101, 0x2801f8ff, 0x4640d007, 0xf8e0f024, 0x42a01a28, 
+    0xe8bdd3eb, 0x4c4381f0, 0xf0244620, 0xf440f8dd, 0x46206180, 0x41f0e8bd, 0xb8d9f024, 0x47f0e92d, 
+    0x460f4614, 0x46994605, 0xf0244618, 0xf242f8cd, 0xb1387610, 0xd02f2c01, 0x44282000, 0x4648b281, 
+    0xf8c5f024, 0x23014d34, 0x21802207, 0xf0244628, 0xf04ff8c1, 0x46286880, 0x46412301, 0xf024221a, 
+    0x4648f8b9, 0xf8b0f024, 0xd1fa2800, 0x46282301, 0x21802207, 0xf8aef024, 0x46412301, 0x4628221a, 
+    0xf8a8f024, 0xd0002c01, 0x19f02600, 0x4648b281, 0x47f0e8bd, 0xb89bf024, 0xe7ce4630, 0x41f0e92d, 
+    0x4615461c, 0x4607460e, 0xf7ff2000, 0x1b04ff3d, 0x2000e010, 0xff38f7ff, 0x28001b00, 0x4c15dc0a, 
+    0xf0244620, 0xf440f881, 0x46207100, 0x41f0e8bd, 0xb87df024, 0xf0244638, 0x4030f877, 0xd1e842a8, 
+    0xb570e78f, 0x68004603, 0x4615460c, 0x28001e40, 0xdc0b6018, 0xf0244610, 0x2101f867, 0x430840a1, 
+    0x4628b281, 0xf863f024, 0xbd702001, 0xbd702000, 0xf0008120, 0xf203517e, 0xf0001000, 0xe28fc04d, 
+    0xe12fff1c, 0x2101e7fe, 0xd2042820, 0x23014081, 0x4853b242, 0x3820e004, 0x4081b242, 0x23014851, 
+    0xb848f024, 0xeb024a50, 0xf0241000, 0x2101b83a, 0xd2052820, 0xb2424081, 0x23004849, 0xe0053808, 
+    0xb2423820, 0x48474081, 0x38082300, 0xb832f024, 0x28202101, 0x4081d205, 0x4841b242, 0x38082301, 
+    0x3820e005, 0x4081b242, 0x2301483e, 0xf0243808, 0x2101b821, 0xd2042820, 0xb2424081, 0x301c4838, 
+    0x3820e004, 0x4081b242, 0x300c4836, 0xb820f024, 0x41f0e92d, 0x4934460d, 0x4613461f, 0x9e063908, 
+    0x1400eb01, 0x46202204, 0xf0242130, 0x2203f803, 0x21084620, 0xf023462b, 0x2202fffd, 0x21044620, 
+    0xf023463b, 0x4620fff7, 0xe8bd4633, 0x220041f0, 0xf0232103, 0xb570bfef, 0xe8bdb118, 0xf0234070, 
+    0x4c21bfdd, 0x1f244d21, 0xf0234620, 0x3410ffd7, 0xd9f942ac, 0xe92dbd70, 0x240141f0, 0xd20e2820, 
+    0xb2424e17, 0x36284084, 0x23014615, 0x46304621, 0xffd0f023, 0x46212301, 0x462a1d37, 0x3820e00e, 
+    0xb2424e10, 0x36184084, 0x23014615, 0x46304621, 0xffc0f023, 0x46212301, 0x462a1d37, 0xf0234638, 
+    0x2300ffb9, 0x462a4621, 0xf0234630, 0x4621ffb3, 0x4638462a, 0x41f0e8bd, 0xf0232300, 0x0000bfab, 
+    0xf0001008, 0xf0001508, 0xf0001108, 0xf00013f4, 0xf04fb510, 0x48ff34ff, 0xf0234621, 0x48feff92, 
+    0xf0234621, 0x48fbff8e, 0x30084621, 0xff89f023, 0x462148f9, 0xf0233008, 0x49f8ff84, 0xf02348f8, 
+    0x48f7ff80, 0x301049f7, 0xff7bf023, 0x49f648f4, 0xf0233020, 0x48f2ff76, 0x303049f4, 0xff71f023, 
+    0x49f348ef, 0xf0233040, 0x48edff6c, 0x305049f1, 0xff67f023, 0x49f048ea, 0xf0233060, 0x48e8ff62, 
+    0x307049ee, 0xff5df023, 0x49ed48e5, 0xf0233080, 0x48e3ff58, 0x309049eb, 0xff53f023, 0x49ea48e0, 
+    0xf02330a0, 0x48deff4e, 0x30b049e8, 0xff49f023, 0x49e748db, 0xf02330c0, 0x48d9ff44, 0x30d049e5, 
+    0xff3ff023, 0x49e448d6, 0xf02330e0, 0x48d4ff3a, 0x30f049e2, 0xff35f023, 0x48e249e1, 0xff31f023, 
+    0x49e148e0, 0xf0233010, 0x48deff2c, 0x302049df, 0xff27f023, 0x49de48db, 0xf0233030, 0x48d9ff22, 
+    0x304049dc, 0xff1df023, 0x49db48d6, 0xf0233050, 0x48d4ff18, 0x306049d9, 0xff13f023, 0x49d848d1, 
+    0xf0233070, 0x48cfff0e, 0x308049d4, 0xff09f023, 0x49d248cc, 0xf0233090, 0x48caff04, 0x30a049d1, 
+    0xfefff023, 0x49d048c7, 0xf02330b0, 0x48c5fefa, 0x30c049ce, 0xfef5f023, 0x49c848c2, 0xf02330d0, 
+    0x48c0fef0, 0x30e049ca, 0xfeebf023, 0x49c948bd, 0xf02330f0, 0x49c8fee6, 0xf02348c8, 0x48c7fee2, 
+    0x301049c7, 0xfeddf023, 0x49c648c4, 0xf0233020, 0x48c2fed8, 0x303049c4, 0xfed3f023, 0x49c348bf, 
+    0xf0233040, 0x48bdfece, 0x305049c1, 0xfec9f023, 0x49c048ba, 0xf0233060, 0x48b8fec4, 0x307049be, 
+    0xfebff023, 0x49ad48b5, 0xf0233080, 0x48b3feba, 0x309049ba, 0xfeb5f023, 0x49b948b0, 0xf02330a0, 
+    0x48aefeb0, 0x30b049b7, 0xfeabf023, 0x49b648ab, 0xf02330c0, 0x48a9fea6, 0x30d049b4, 0xfea1f023, 
+    0x499e48a6, 0xf02330e0, 0x48a4fe9c, 0x4010e8bd, 0x30f0499a, 0xbe95f023, 0xf7ffb57c, 0x2000fef9, 
+    0xfea9f7ff, 0x2400b662, 0x22019400, 0x20064623, 0xf7ff4621, 0x2006fe7d, 0xfe49f7ff, 0x94002300, 
+    0x46192201, 0xf7ff2007, 0x2007fe73, 0xfe3ff7ff, 0x94002300, 0x46192203, 0xf7ff2001, 0x2300fe69, 
+    0x22039400, 0x20114619, 0xfe62f7ff, 0x94002300, 0x46192203, 0xf7ff2012, 0x2001fe5b, 0xfe27f7ff, 
+    0xf7ff2011, 0x2012fe24, 0xfe21f7ff, 0x94002300, 0x46192202, 0xf7ff4610, 0x2002fe4b, 0xfe28f7ff, 
+    0x94002300, 0x46192203, 0xf7ff201e, 0x201efe41, 0xfe0df7ff, 0x94002300, 0x46192203, 0xf7ff201f, 
+    0x201ffe37, 0xfe03f7ff, 0x94002201, 0x46112300, 0xf7ff201c, 0x4e7efe2d, 0x21022301, 0x4630461a, 
+    0xfe4ff023, 0xf64f487a, 0x462975ff, 0xf023382a, 0x4877fe2e, 0x382c4629, 0xfe29f023, 0x46302300, 
+    0x21042202, 0xfe3df023, 0x46294871, 0xf023380a, 0x486ffe1e, 0x380c4629, 0xfe19f023, 0xfde8f005, 
+    0xf0051e60, 0x2301fc59, 0x22004630, 0xf0234619, 0x2201fe28, 0x23009400, 0x20044611, 0xfdf8f7ff, 
+    0xf7ff2004, 0x2300fdc4, 0x22039400, 0x20224619, 0xfdeef7ff, 0xf7ff2022, 0x2300fdba, 0x22039400, 
+    0x20214619, 0xfde4f7ff, 0xf7ff2021, 0x2300fdb0, 0x22019400, 0x20254619, 0xfddaf7ff, 0xf7ff2025, 
+    0x2300fda6, 0x22019400, 0x20264619, 0xfdd0f7ff, 0xf7ff2026, 0x484ffd9c, 0x717ff647, 0xfdd7f023, 
+    0x94002300, 0x46192201, 0xf7ff2024, 0x2024fdc1, 0xfd8df7ff, 0x94002300, 0x46192201, 0xf7ff2009, 
+    0x4844fdb7, 0x38164629, 0xfdc1f023, 0x46294841, 0xf0233814, 0x483ffdbc, 0x0500f248, 0x381a4629, 
+    0xfdb5f023, 0x4629483b, 0xf0233818, 0x2009fdb0, 0xfd6df7ff, 0xf64f2300, 0x220170e0, 0x21079000, 
+    0x46189001, 0xfa00f01d, 0x94002201, 0x46102300, 0xe0612107, 0xf0001000, 0xf0001500, 0x00004660, 
+    0xf0001108, 0x000049e0, 0x00004a24, 0x00004bb4, 0x00004d28, 0x00004f60, 0x00004f98, 0x000050fc, 
+    0x00005148, 0x00005180, 0x00005318, 0x00005384, 0x00005510, 0x0000557c, 0x000055b4, 0x000055ec, 
+    0x00005624, 0xf0001208, 0x0000565c, 0x000056a0, 0x000056e4, 0x000056fc, 0x00005714, 0x00007b05, 
+    0x0000574c, 0x00005784, 0x0000594c, 0x00005984, 0x000059e8, 0x00005a00, 0x00005a44, 0xf0001308, 
+    0x00005a7c, 0x00005b48, 0x00005c34, 0x00005c6c, 0x00005d74, 0x00005f74, 0x000060c8, 0x00006100, 
+    0x00006138, 0x00006170, 0x00006298, 0x000062d0, 0xf2039046, 0xf23c8094, 0xf01d9401, 0xf64ff995, 
+    0x900070f8, 0x90012300, 0x21072201, 0xf01d2002, 0xf249f98b, 0x9000002a, 0x90012300, 0x21072201, 
+    0xf01d2003, 0xf244f981, 0x90001091, 0x90012300, 0x211e2201, 0xf01d2004, 0x2189f977, 0x2301208c, 
+    0x0100e9cd, 0x46192200, 0xf01d2005, 0x2201f96d, 0x23009400, 0x201a4611, 0xfcfaf7ff, 0xf7ff201a, 
+    0xf004fcc6, 0x2201fe3f, 0x23009400, 0x202b4611, 0xfceef7ff, 0xf7ff202b, 0xe8bdfcba, 0x4802407c, 
+    0x31bbf64b, 0xbcf3f023, 0xf23c80ba, 0x46032200, 0x2107481e, 0xbceef023, 0x4c1cb510, 0x22042300, 
+    0x21103cc0, 0xf0234620, 0x2301fce5, 0x22064620, 0xf0232140, 0x2300fcdf, 0x22064620, 0xf0232140, 
+    0x2301fcd9, 0x22044620, 0x4010e8bd, 0xf0232110, 0xb510bcd1, 0x23004c0d, 0x3cc02205, 0x46202120, 
+    0xfcc8f023, 0x46202301, 0x21802207, 0xfcc2f023, 0x46202300, 0x21802207, 0xfcbcf023, 0x46202301, 
+    0xe8bd2205, 0x21204010, 0xbcb4f023, 0xf10008c0, 0xf04fb570, 0x46054671, 0xf6402200, 0x21010400, 
+    0x46304603, 0xfca6f023, 0xd0172d01, 0x05264635, 0x221f4628, 0xf0234631, 0x2801fcab, 0x1e64d00e, 
+    0x2c00b224, 0x4c44dcf4, 0xf0234620, 0xf440fc8d, 0x46204100, 0x4070e8bd, 0xbc89f023, 0x2200bd70, 
+    0xf04f2101, 0xb5104071, 0xfc92f023, 0xbd10b240, 0x4c3ab570, 0x22104615, 0xf44f460e, 0x4603017f, 
+    0xf0234620, 0x2200fc77, 0x21ff4633, 0xf0234620, 0x462bfc71, 0xe8bd4620, 0x22084070, 0x7100f64f, 
+    0xbc68f023, 0x4c2db570, 0x460d2210, 0x341c492c, 0x46204603, 0xfc5ef023, 0x4620462b, 0x4070e8bd, 
+    0xf64f2200, 0xf02371ff, 0xb570bc55, 0x22044c23, 0x4603460d, 0x21f03418, 0xf0234620, 0x462bfc4b, 
+    0xe8bd4620, 0x22004070, 0xf023210f, 0xe92dbc43, 0x4c1a41f0, 0x4615461f, 0x1d24460e, 0x220c4603, 
+    0x0100f241, 0xf0234620, 0x2208fc35, 0x46204633, 0xf0230151, 0x2204fc2f, 0x21f0462b, 0xf0234620, 
+    0x463bfc29, 0xe8bd4620, 0x220041f0, 0xf0232103, 0xb570bc21, 0x461d4c09, 0x461321f0, 0x22043414, 
+    0xf0234620, 0x462bfc17, 0xe8bd4620, 0x22004070, 0xf023210f, 0x0000bc0f, 0xf203517c, 0xf1000004, 
+    0xffff0000, 0x41f0e92d, 0x460e1e52, 0xb2541e5b, 0x4603b25d, 0xf04f2218, 0x4ffd51f8, 0xf0234638, 
+    0x2210fbf9, 0xf44f4633, 0x463811f8, 0xfbf2f023, 0x46232208, 0x7100f641, 0xf0234638, 0x462bfbeb, 
+    0xe8bd4638, 0x220041f0, 0xf023211f, 0xe92dbbe3, 0xf44f4ff8, 0x46802780, 0x461d2000, 0xa028f8dd, 
+    0x460e4614, 0x0110f243, 0x46389000, 0xfa1bf7f8, 0xf1041c70, 0xd0010001, 0xe011b188, 0x261ab108, 
+    0x2100e00e, 0xf7f84638, 0x2100f9fd, 0xf7f84638, 0x2100f9f9, 0xf7f84638, 0xe8bdf9f5, 0x241a8ff8, 
+    0x4971f04f, 0x46482300, 0x21102204, 0xfbb2f023, 0x461a2300, 0xb270b261, 0xffa4f7ff, 0x461a2300, 
+    0x46184619, 0xff85f7ff, 0x20012100, 0xff4df7ff, 0x464148cf, 0xf0233018, 0x48cdfb94, 0x22002301, 
+    0x30244619, 0xfb96f023, 0x1f0048c9, 0xfb86f023, 0x46384601, 0xf9c6f7f8, 0xf02348c5, 0x4601fb7f, 
+    0xf7f84638, 0x4641f9bf, 0xf7f84638, 0x4ec1f9bb, 0x2000f240, 0xf7ff7831, 0xf8dffa6f, 0x4cbf82fc, 
+    0x0000f898, 0xf994b948, 0xb1152000, 0x4629980b, 0x2100e001, 0xf0014608, 0x2301fc6a, 0x2211464f, 
+    0x04594648, 0xfb66f023, 0x46382301, 0x46192200, 0xfb60f023, 0xb2c8f8df, 0x0000f44f, 0x4900f04f, 
+    0xe0069000, 0x465a2101, 0xf7ff4668, 0x2801fada, 0x221fd006, 0x46384649, 0xfb5af023, 0xd0f12800, 
+    0x0000f898, 0xf1bab970, 0xd0040f00, 0x2000f994, 0x980b4629, 0xb12de004, 0xf9942100, 0x46082000, 
+    0xfc35f001, 0x46382301, 0x03d9220f, 0xfb32f023, 0xf2407831, 0xf7ff2000, 0xe76efa1f, 0x43f8e92d, 
+    0x2680f44f, 0x20004680, 0x460d4614, 0x0120f243, 0x46309000, 0xf967f7f8, 0xf1041c68, 0xd0010001, 
+    0xe011b188, 0x251ab108, 0x2100e00e, 0xf7f84630, 0x2100f949, 0xf7f84630, 0x2100f945, 0xf7f84630, 
+    0xe8bdf941, 0x241a83f8, 0x4771f04f, 0x46382300, 0x21102204, 0xfafef023, 0x46082100, 0xb26ab263, 
+    0xfef0f7ff, 0x461a2300, 0x46184619, 0xfed1f7ff, 0x20002101, 0xfe99f7ff, 0x46414875, 0xf0233018, 
+    0x4873fae0, 0x22002301, 0x30244619, 0xfae2f023, 0x1f00486f, 0xfad2f023, 0x46304601, 0xf912f7f8, 
+    0xf023486b, 0x4601facb, 0xf7f84630, 0x4641f90b, 0xf7f84630, 0x4c67f907, 0x2800f240, 0x78214640, 
+    0xf9baf7ff, 0x46382301, 0x04592211, 0xfac2f023, 0x46382301, 0x46192200, 0xfabcf023, 0xf44f4d60, 
+    0x90000000, 0x02061ead, 0x210fe006, 0x4668462a, 0xfa37f7ff, 0xd0062801, 0x4631221f, 0xf0234638, 
+    0x2800fab7, 0x2301d0f1, 0x220f4638, 0xf02303d9, 0x7821faa1, 0xf7ff4640, 0xe792f98f, 0x4fffe92d, 
+    0x469bb081, 0x46162000, 0x2980f44f, 0xe9dd460f, 0xf8dd540e, 0xf2438044, 0x90000130, 0xf7f84648, 
+    0x1c78f8d2, 0x1c70d101, 0x1c68d002, 0xe004d004, 0xd1021c68, 0xd0031c60, 0x1c60251a, 0xe010d010, 
+    0x464c2100, 0xf7f84648, 0x2100f8ad, 0xf7f84620, 0x2100f8a9, 0xf7f84620, 0xb005f8a5, 0x8ff0e8bd, 
+    0xf04f241a, 0x23014a71, 0x22044650, 0xf0232110, 0xb263fa61, 0xb271b26a, 0xf7ffb278, 0x2300fe53, 
+    0x4619461a, 0xf7ff4618, 0x9810fe34, 0xfa4fb241, 0xf7fff08b, 0x4826fdfa, 0x30189901, 0xfa41f023, 
+    0x23014823, 0x46192200, 0xf0233024, 0x4820fa43, 0xf0231f00, 0x4601fa33, 0x4648464c, 0xf872f7f8, 
+    0xf023481b, 0x4601fa2b, 0xf7f84620, 0x9901f86b, 0xf7f84620, 0x4d17f867, 0x2b00f240, 0x78294658, 
+    0xf91af7ff, 0x4c154e14, 0xb9587830, 0x2000f994, 0x0008ea5f, 0x4601d002, 0xe0019813, 0x46082100, 
+    0xfb15f001, 0x46572301, 0x46502211, 0xf0230459, 0x2301fa11, 0x22004638, 0xf0234619, 0xf8dffa0b, 
+    0xf44fa020, 0xf04f0000, 0x90004900, 0x0000e011, 0xf100000c, 0x00040293, 0x0004257a, 0x00040298, 
+    0xf203517c, 0x46522100, 0xf7ff4668, 0x2801f97a, 0x221fd006, 0x46384649, 0xf9faf023, 0xd0f12800, 
+    0xb9787830, 0xb1209812, 0x2000f994, 0x98134641, 0xf1b8e006, 0xd0050f00, 0xf9942100, 0x46082000, 
+    0xfad5f001, 0x46382301, 0x03d9220f, 0xf9d2f023, 0x46587829, 0xf8c0f7ff, 0xe92de75f, 0xf44f47f0, 
+    0x461e2480, 0x46894617, 0xf2434680, 0x46200160, 0xf809f7f8, 0x4571f04f, 0x46282301, 0x21102204, 
+    0xf9b8f023, 0xfa4fb27b, 0x461af188, 0xf7ff4608, 0x2300fda9, 0x4619461a, 0xf7ff4618, 0xb271fd8a, 
+    0xf089fa4f, 0xfd51f7ff, 0x48c72300, 0x461a2101, 0xf9a0f023, 0x382848c4, 0xf990f023, 0x46204601, 
+    0xffd0f7f7, 0x382448c0, 0xf988f023, 0x46204601, 0xffc8f7f7, 0x46202100, 0xffc4f7f7, 0x46282300, 
+    0x10612211, 0xf986f023, 0xe8bd4628, 0x230147f0, 0x46192200, 0xb97ef023, 0x4605b570, 0xb08648b3, 
+    0xb9d07800, 0x22004cb2, 0x46202101, 0xf997f023, 0x2201b988, 0x21024620, 0xf991f023, 0x2202b958, 
+    0x21044620, 0xf98bf023, 0x2203b928, 0x21084620, 0xf985f023, 0x2401b108, 0x2400e000, 0x26019404, 
+    0x9000200b, 0x46332209, 0x6402e9cd, 0x94054611, 0x02709001, 0xfeb2f7ff, 0xd10c2d01, 0x9000200c, 
+    0x94042301, 0x9405220a, 0x6402e9cd, 0x90014611, 0xf7ff0298, 0xb006fea3, 0x4894bd70, 0xb087b530, 
+    0xb9d07800, 0x22004c92, 0x46202101, 0xf957f023, 0x2201b988, 0x21024620, 0xf951f023, 0x2202b958, 
+    0x21044620, 0xf94bf023, 0x2203b928, 0x21084620, 0xf945f023, 0x2401b108, 0x2400e000, 0x25019404, 
+    0x9000200b, 0x462b2209, 0x5402e9cd, 0x94054611, 0x02689001, 0xfe72f7ff, 0x9000200c, 0x94042301, 
+    0x9405220a, 0x5402e9cd, 0x90014611, 0xf7ff02d8, 0xb007fe65, 0x220bbd30, 0x2000f240, 0xb5104611, 
+    0xfdccf7ff, 0xf640220c, 0xe8bd0000, 0x46114010, 0x486ee5c4, 0x7800b51c, 0x4c6db9d0, 0x21012200, 
+    0xf0234620, 0xb988f90c, 0x46202201, 0xf0232102, 0xb958f906, 0x46202202, 0xf0232104, 0xb928f900, 
+    0x46202203, 0xf0232108, 0xb108f8fa, 0xe0002401, 0xf2402400, 0x22092000, 0x46114623, 0x94019400, 
+    0xfce5f7ff, 0x4623220a, 0xf6404611, 0x94000000, 0xf7ff9401, 0xbd1cfcdc, 0x41ffe92d, 0x466c2300, 
+    0x429a2200, 0x2108d101, 0x2102e000, 0x1542eb00, 0xeb051e49, 0xe00305c3, 0xb91e5c6e, 0xb2491e49, 
+    0xdaf92900, 0x0582eb04, 0x1c521c49, 0x2a04b252, 0xdbe654e9, 0xb25b1c5b, 0xdbe12b04, 0x46182300, 
+    0x0180eb04, 0x42995609, 0x460bdd00, 0xb2401c40, 0xdbf52804, 0x22044d3c, 0x3d2821f0, 0xf0234628, 
+    0x2300f889, 0x20004619, 0xd0054288, 0x0280eb04, 0x429a5652, 0x4613dd00, 0xb2401c40, 0xdbf32804, 
+    0xb2491c49, 0xdbee2904, 0x46282200, 0xf0232103, 0x4d2df871, 0x46283518, 0xf860f023, 0x4601230f, 
+    0x27012200, 0xeb042000, 0x5cb60680, 0xfa07b916, 0x43b1f603, 0x1e5b1c40, 0x2804b240, 0x1c52dbf3, 
+    0x2a04b252, 0x4628dbee, 0xf84bf023, 0x81ffe8bd, 0x41f0e92d, 0x46042300, 0x20004619, 0xd0054288, 
+    0x0280eb04, 0x429a5652, 0x4613dd00, 0xb2401c40, 0xdbf32804, 0xb2491c49, 0xdbee2904, 0x22084812, 
+    0x38280151, 0xf836f023, 0x35184d0f, 0xf0234628, 0x231ff825, 0x22004601, 0x20002601, 0x0780eb04, 
+    0xb9175cbf, 0xf703fa06, 0x1c4043b9, 0xb2401e5b, 0xdbf32804, 0xb2521c52, 0xdbee2a04, 0xe8bd4628, 
+    0xf02341f0, 0x0000b80e, 0xf1000030, 0x0004257a, 0xf2030024, 0x22002301, 0xb5104619, 0xf02348fe, 
+    0x2300f820, 0x210148fd, 0xf023461a, 0xe8bdf81a, 0x48fb4010, 0x0140f242, 0xbff9f022, 0x4df7b570, 
+    0x2203b28b, 0x1ead4604, 0x46282108, 0xf809f023, 0x4628b2a3, 0x4070e8bd, 0x21042202, 0xb801f023, 
+    0x4deeb570, 0x2201b28b, 0x1ead4604, 0x46282102, 0xfff7f022, 0x4628b2a3, 0x4070e8bd, 0x21012200, 
+    0xbfeff022, 0x4de5b570, 0x2206b283, 0x1ead460c, 0x46282140, 0xffe5f022, 0x4628b2a3, 0x4070e8bd, 
+    0x21202205, 0xbfddf022, 0x48dcb283, 0xf2402208, 0x1e803100, 0xbfd5f022, 0x41f0e92d, 0x4690461f, 
+    0x46084604, 0x5606e9dd, 0xffeef7ff, 0x462043e1, 0xffd8f7ff, 0x46404639, 0xffc2f7ff, 0x46284631, 
+    0x41f0e8bd, 0xb570e7aa, 0x23014dcc, 0x03de220f, 0x46311ead, 0xf0224628, 0x2301ffb4, 0x22074628, 
+    0xf0222180, 0x2001ffae, 0xffcef7ff, 0xe00f0234, 0xf7fe4620, 0x1e04fe7f, 0x4cc2dc0a, 0xf0224620, 
+    0xf040ff83, 0x46200101, 0x4070e8bd, 0xbf7ff022, 0x4631220f, 0xf0224628, 0x2800ffa2, 0xbd70d1e8, 
+    0x230148b6, 0x21102204, 0xf0221e80, 0xe92dbf8a, 0x4db241f0, 0x4000f500, 0xb281460f, 0x46283d14, 
+    0xff65f022, 0x0400f44f, 0xe00e1226, 0xf7fe4620, 0x1e04fe51, 0x4cabdc09, 0xf0224620, 0xf040ff55, 
+    0x46200102, 0xff53f022, 0x220fe006, 0x46284631, 0xff75f022, 0xd1e92800, 0xf2424639, 0xe8bd0000, 
+    0xf7fe41f0, 0xb570be39, 0x46164d9e, 0x4604220f, 0x460b3d9a, 0x0100f248, 0xf0224628, 0x220dff52, 
+    0xf2464633, 0x46280100, 0xff4bf022, 0x4628b2a3, 0x4070e8bd, 0xf6412200, 0xf02271ff, 0xb283bf42, 
+    0x2200488e, 0x30602101, 0xbf3bf022, 0x41f0e92d, 0x461e4d8a, 0xf248b293, 0x35200400, 0x220f4688, 
+    0x46214607, 0xf0224628, 0xb2bbff2c, 0x77fff240, 0x46392200, 0xf0224628, 0x4621ff24, 0xb2b31eac, 
+    0x220f4620, 0xff1df022, 0xf388fa1f, 0x46204639, 0x41f0e8bd, 0xf0222200, 0xb570bf14, 0x48794605, 
+    0x46162301, 0x460c3892, 0x461a2102, 0xff09f022, 0x0045ea44, 0xb2834c73, 0x71fff640, 0x22003c8e, 
+    0xf0224620, 0x2301fefe, 0x220c4620, 0xf0220319, 0x4631fef8, 0x4070e8bd, 0xf7fe2004, 0xb570bdcd, 
+    0x48684605, 0x46162301, 0x460c3898, 0x461a2102, 0xfee7f022, 0x0045ea44, 0xb2834c62, 0x71fff640, 
+    0x22003c96, 0xf0224620, 0x2301fedc, 0x220c4620, 0xf0220319, 0x4631fed6, 0x4070e8bd, 0xf7fe2004, 
+    0xe92dbdab, 0x4d5847f0, 0x461f0004, 0x46894690, 0x0300f04f, 0xf240d418, 0x46282600, 0x46312209, 
+    0xfebff022, 0x2301e00d, 0x22094631, 0xf0224628, 0x2300feb8, 0x22094631, 0xf0224628, 0x1e64feb2, 
+    0x2c00b224, 0xe016dcef, 0x46282208, 0x46310156, 0xfea7f022, 0x2301e00d, 0x22084631, 0xf0224628, 
+    0x2300fea0, 0x22084631, 0xf0224628, 0x1c64fe9a, 0x2c00b224, 0x2004dbef, 0xf7fe4639, 0x463afd6d, 
+    0x46484641, 0x47f0e8bd, 0xb570e777, 0xb2834d33, 0x4604220b, 0xf6401cad, 0x46280100, 0xfe81f022, 
+    0x4628b2a3, 0x4070e8bd, 0xf241220c, 0xf0220100, 0xe92dbe78, 0x4c2d41f0, 0x46062904, 0x2800f240, 
+    0x4500f240, 0x2905d002, 0xe009d004, 0x46032209, 0xe0024641, 0x4603220a, 0x46204629, 0xfe61f022, 
+    0x220c4f1e, 0xf2414633, 0x1ebf0100, 0xf0224638, 0x220dfe58, 0xf2424633, 0x46380100, 0xfe51f022, 
+    0x4633220b, 0x0100f640, 0xf0224638, 0x2202fe4a, 0x21044633, 0xf0221cb8, 0x4811fe44, 0xf0223010, 
+    0x220ffe23, 0x1d384633, 0x0100f248, 0xfe39f022, 0x2300b98e, 0x220a4629, 0xf0224638, 0x2209fe32, 
+    0x46414633, 0xf0224620, 0x220afe2c, 0x46294633, 0xf0224620, 0xe00bfe26, 0xf2020126, 0xf2035024, 
+    0xf2020000, 0xf203517e, 0xf2035092, 0xf2039000, 0xe8bd2001, 0xe92d81f0, 0x4efe41f0, 0x22032300, 
+    0x2108460d, 0x46304604, 0xfe0bf022, 0x46302300, 0x21042202, 0xfe05f022, 0x46302300, 0x461a2101, 
+    0xfdfff022, 0x1cb72300, 0x2101461a, 0xf0224638, 0xb124fdf8, 0xd0102c01, 0xd00e2c02, 0x2300e01c, 
+    0x22044630, 0xf0222110, 0x2300fdec, 0x22024638, 0xf0222104, 0x2000fde6, 0x2301e00c, 0x22044630, 
+    0xf0222110, 0x2301fdde, 0x22024638, 0xf0222104, 0x2001fdd8, 0xfa38f015, 0xd0ba2d00, 0x46302301, 
+    0x21082203, 0xfdcdf022, 0x46302301, 0x21042202, 0xfdc7f022, 0xd1ac2d01, 0x46302301, 0x46192200, 
+    0xfdbff022, 0xe8bd4638, 0x230141f0, 0x46192200, 0xbdb7f022, 0xe92de79d, 0x46075ff0, 0x461c48cd, 
+    0x22004615, 0x387c460e, 0x33c2f240, 0x71fff240, 0xfda7f022, 0x831cf8df, 0xf2472f04, 0xf2400900, 
+    0xf1a81a00, 0xf240087e, 0xd1016b00, 0xb12cb906, 0xd1002c02, 0x2f05b116, 0xe015d014, 0x46402301, 
+    0x46192200, 0xfd8df022, 0x46402302, 0x21062201, 0xfd87f022, 0x46512301, 0x46402208, 0xfd81f022, 
+    0xe0312302, 0xb1e4b905, 0xd1002c03, 0x2300b1cd, 0x22014640, 0xf0222106, 0x2300fd74, 0x22094659, 
+    0xf0224640, 0x2300fd6e, 0x22084651, 0xf0224640, 0x2300fd68, 0x461a2101, 0xe8bd4640, 0xf0225ff0, 
+    0x2301bd60, 0x22004640, 0xf0224619, 0x2303fd5a, 0x22014640, 0xf0222106, 0x2301fd54, 0x22084651, 
+    0xf0224640, 0x2303fd4e, 0x22094659, 0xf0224640, 0x2301fd48, 0x220c4649, 0xb570e7de, 0x461c2300, 
+    0x2a03b161, 0x2a02d021, 0x2a01d021, 0x2803d01a, 0x2805d01f, 0x2804d019, 0xe01ad019, 0xd00a2a03, 
+    0xd00a2a02, 0xd00a2a01, 0xd0122803, 0xd0022805, 0xd0022804, 0x2302e00d, 0x2303e00a, 0x2301e003, 
+    0xe006461c, 0x24032301, 0x2302e003, 0x2303e001, 0x48812402, 0x28018800, 0x4d7ed10e, 0x21032200, 
+    0x46283d78, 0xfd0df022, 0x46284623, 0x4070e8bd, 0x21302204, 0xbd05f022, 0xe92dbd70, 0x4c755ff0, 
+    0x4f744605, 0x3f503c5a, 0xf8dfb151, 0x290181c8, 0x76fff64f, 0x0836f1a8, 0x2902d00c, 0xe060d020, 
+    0x46202300, 0x461a2101, 0xfcebf022, 0x21012300, 0xe0c9461a, 0x46202301, 0x21042202, 0xfce1f022, 
+    0x46202300, 0x21082203, 0xfcdbf022, 0x46402101, 0xfcbdf022, 0x4631485f, 0xf0223834, 0xe040fcb8, 
+    0x46202300, 0x21042202, 0xfccbf022, 0x46202301, 0x21082203, 0xfcc5f022, 0x1101f240, 0xf0224640, 
+    0x4854fca6, 0x38324631, 0xfca1f022, 0x46314851, 0xf0223830, 0x484ffc9c, 0x382e4631, 0xfc97f022, 
+    0x4631484c, 0xf022382c, 0x484afc92, 0x382a4631, 0xfc8df022, 0x46314847, 0xf0223828, 0x4845fc88, 
+    0x38264631, 0xfc83f022, 0x46314842, 0xf0223824, 0x4842fc7e, 0xf2402208, 0x78037100, 0xf0224638, 
+    0x4e3cfc90, 0x78fff640, 0xb0e8f8df, 0x7afff240, 0x2d043e58, 0x0902f106, 0x0b7cf1ab, 0x2d05d002, 
+    0xe041d01f, 0xf6402200, 0x46413356, 0xf0224630, 0xf240fc78, 0x464135c2, 0x462b2200, 0xf0224648, 
+    0x2200fc70, 0x4651462b, 0xf0224658, 0x2303fc6a, 0x0100f24f, 0x4638220c, 0xfc63f022, 0x7394f240, 
+    0x2200e01d, 0x439af640, 0x46304641, 0xfc59f022, 0xf2402200, 0x46415304, 0xf0224648, 0x2200fc52, 
+    0x2382f240, 0x46584651, 0xfc4bf022, 0xf24f2306, 0x220c0100, 0xf0224638, 0xf240fc44, 0x46417396, 
+    0x46302200, 0xfc3df022, 0x46202300, 0x21102204, 0xfc37f022, 0x46202301, 0x46192200, 0xfc31f022, 
+    0x46382301, 0x46192200, 0xfc2bf022, 0x21204809, 0xf0223854, 0x2301fc0c, 0x22024638, 0xf0222104, 
+    0x2300fc20, 0x21102204, 0xe8bd4638, 0xf0225ff0, 0x0000bc18, 0xf2035336, 0x00042578, 0x00042355, 
+    0x41f0e92d, 0x88004605, 0xf500460c, 0xb2814000, 0xf022483e, 0x8868fbec, 0x4000f500, 0x483bb281, 
+    0xf0221c80, 0x88a8fbe4, 0x4000f500, 0x4837b281, 0xf0221d00, 0x88e8fbdc, 0x4000f500, 0x4833b281, 
+    0xf0221d80, 0x8820fbd4, 0xf5004d30, 0xb2814000, 0x46283508, 0xfbcbf022, 0x1cae8860, 0x4000f500, 
+    0x4630b281, 0xfbc3f022, 0x1d2f88a0, 0x4000f500, 0x4638b281, 0xfbbbf022, 0x1dac88e0, 0x4000f500, 
+    0x4620b281, 0xfbb3f022, 0xf0224628, 0x4630fbad, 0xfbaaf022, 0xf0224638, 0x4620fba7, 0x41f0e8bd, 
+    0xbba2f022, 0x41f0e92d, 0x28024b19, 0x4d1a4c19, 0x4f1b4e1a, 0x2801d004, 0x8808d01f, 0x80081c40, 
+    0xd0212a00, 0x88194811, 0xf0223848, 0x480ffb90, 0x38468821, 0xfb8bf022, 0x8829480c, 0xf0223844, 
+    0x480afb86, 0x38428831, 0xfb81f022, 0xe8bd8839, 0x480641f0, 0xf0223840, 0x2000bb7a, 0x80208018, 
+    0x80308028, 0xe7db8038, 0x0000e573, 0xf20351ac, 0x00042564, 0x00042566, 0x00042568, 0x0004256a, 
+    0x0004256c, 0x5ff0e92d, 0x46922301, 0x4683460c, 0x461a2102, 0x46284dfe, 0xfb73f022, 0x780949fd, 
+    0x2301b929, 0x22004628, 0xf0224619, 0xf8dffb6a, 0xf24893e0, 0x23010800, 0xf1094641, 0x220f0902, 
+    0xf0224648, 0x4df4fb5e, 0x0600f246, 0x4631220d, 0xf8906828, 0x46483020, 0xfb53f022, 0xf6416828, 
+    0x220077ff, 0x8c434639, 0xf0224648, 0xf109fb4a, 0x46410902, 0x46482300, 0xf022220f, 0x6828fb42, 
+    0x4631220d, 0x3026f890, 0xf0224648, 0x6828fb3a, 0x46392200, 0x46488c83, 0xfb33f022, 0x0902f109, 
+    0x23014641, 0x220f4648, 0xfb2bf022, 0x220d6828, 0xf8904631, 0x4648302c, 0xfb23f022, 0x22006828, 
+    0x8dc34639, 0xf0224648, 0xf109fb1c, 0x46410902, 0x46482301, 0xf022220f, 0xb124fb14, 0xd0062c01, 
+    0xd0042c02, 0x6828e00b, 0x3027f890, 0x6828e002, 0x3028f890, 0x4631220d, 0xf0224648, 0xf1bafb02, 
+    0xd0140f00, 0x220d6828, 0xf8904631, 0x46483029, 0xfaf7f022, 0x0f05f1bb, 0x2c01d109, 0x2c02d001, 
+    0x2301d105, 0x220d4631, 0xf0224648, 0x6828faea, 0x46392200, 0x46488d43, 0xfae3f022, 0x46414644, 
+    0x82ccf8df, 0x220f2300, 0x080af108, 0xf0224640, 0x6828fad8, 0x4631220d, 0x3034f890, 0xf0224640, 
+    0x6828fad0, 0x46392200, 0x46408ec3, 0xfac9f022, 0xf1084621, 0x23000402, 0x220f4620, 0xfac1f022, 
+    0x220d6828, 0xf8904631, 0x46203030, 0xfab9f022, 0x22006828, 0xf8b04639, 0x489d3048, 0xf02230f0, 
+    0x6828fab0, 0xe8bd7e80, 0xf0005ff0, 0xe92dbc00, 0x4c9a47f0, 0x7100f641, 0xc260f8df, 0x35f0f240, 
+    0xf24f3c96, 0x1ca70600, 0x0306f04f, 0xf04f2804, 0xf10c0208, 0x46880902, 0xd02d4660, 0xfa91f022, 
+    0x46202303, 0x210f2200, 0xfa8bf022, 0x4629230c, 0x46202204, 0xfa85f022, 0x46312304, 0x4620220c, 
+    0xfa7ff022, 0x46382303, 0x210f2200, 0xfa79f022, 0x4629230d, 0x46382204, 0xfa73f022, 0x46412302, 
+    0x46482208, 0xfa6df022, 0x46384631, 0x47f0e8bd, 0x220c2304, 0xba65f022, 0xfa63f022, 0x46202303, 
+    0x210f2200, 0xfa5df022, 0x4629230b, 0x46202204, 0xfa57f022, 0x46312304, 0x4620220c, 0xfa51f022, 
+    0x46382303, 0x210f2200, 0xfa4bf022, 0xe7d0230c, 0x41fce92d, 0x20032400, 0xf7fe9401, 0x2002f9f9, 
+    0xf9f6f7fe, 0xf7fe2001, 0x2011f9f3, 0xf9f0f7fe, 0xf7fe2012, 0x2001f9ed, 0xf8b7f7fe, 0xf7fe2002, 
+    0x2004f8b4, 0xf8b1f7fe, 0x485d2301, 0x0319220c, 0xfa27f022, 0x7004485b, 0x7004485b, 0x7004485b, 
+    0xf0152000, 0x485af85d, 0x28016800, 0x4859d107, 0x0100f640, 0x48586004, 0xf0236800, 0x4857f9f1, 
+    0xb1288800, 0x48562301, 0x46192200, 0xfa09f022, 0xfce5f004, 0x78004853, 0x2001b910, 0xfb75f7ff, 
+    0xf6412200, 0x20040300, 0x94004611, 0xfc9af001, 0x7800484d, 0xd1022801, 0xf0032000, 0x484bfd13, 
+    0x20007801, 0xfb75f7ff, 0xfffaf011, 0x23004838, 0x21022201, 0xf02238b0, 0x4c35f9e4, 0x23002208, 
+    0x01513452, 0xf0224620, 0x4d41f9dc, 0x22032301, 0x46282108, 0xf9d5f022, 0x46282300, 0x21082203, 
+    0xf9cff022, 0x7808493b, 0xfbc2f7fd, 0x4e3a2301, 0x035d220d, 0x46294630, 0xf9c3f022, 0xf2481db7, 
+    0x23010800, 0x220f4641, 0xf0224638, 0x2300f9ba, 0x220f4641, 0xf0224638, 0x2300f9b4, 0x220d4629, 
+    0xf0224630, 0x2000f9ae, 0xf9cef7ff, 0xfa60f7f8, 0x23004d17, 0x461a2101, 0x46283dbc, 0xf9a1f022, 
+    0x46282300, 0x21022201, 0xf99bf022, 0x46282300, 0x21042202, 0xf995f022, 0x46282300, 0x21082203, 
+    0xf98ff022, 0x7600f647, 0x46312300, 0x1d282208, 0xf987f022, 0x1daf2300, 0x217f461a, 0xf0224638, 
+    0x2300f980, 0x22084631, 0xf0224638, 0xe025f97a, 0xf20350d4, 0x0004257a, 0x00042618, 0xf2035332, 
+    0xf203902c, 0x0004024c, 0x0004232e, 0x0004230e, 0x00057f74, 0x00057ff0, 0x00040234, 0x00040290, 
+    0xf38f20e0, 0x00042574, 0x000402f2, 0x00040292, 0xf2036100, 0x00040293, 0xf23c8306, 0x1ca821d2, 
+    0xf935f022, 0x46282100, 0xf931f022, 0x23004825, 0x4641220f, 0xf945f022, 0x22032100, 0xf7f94608, 
+    0x4d21fb99, 0x22022300, 0x46282104, 0xf939f022, 0x46282300, 0x21022201, 0xf933f022, 0x46282300, 
+    0x461a2101, 0xf92df022, 0x0100f44f, 0x4f184d17, 0x9101138e, 0x2103e00c, 0xa801462a, 0xf891f7fe, 
+    0xd00c2801, 0x46312301, 0x46202209, 0xf919f022, 0x46382206, 0xf0222140, 0x2800f922, 0xe8bdd1eb, 
+    0x210281fc, 0x422bf04f, 0xb5100488, 0xff89f7f6, 0xf0022003, 0x2006ffb0, 0xffadf002, 0x4010e8bd, 
+    0xbb49f001, 0xf38f201c, 0xf30740ca, 0xf203517c, 0xf203502c, 0x41f0e92d, 0x8458f8df, 0xb283461c, 
+    0x22064615, 0x21c0460e, 0x46404607, 0xf8e9f022, 0x4640b2b3, 0x21302204, 0xf8e3f022, 0x4640b2ab, 
+    0x210c2202, 0xf8ddf022, 0x4640b2a3, 0x21032200, 0xf8d7f022, 0x841cf8df, 0x2206b2bb, 0x081cf108, 
+    0x464021c0, 0xf8cdf022, 0x4640b2b3, 0x21302204, 0xf8c7f022, 0x4640b2ab, 0x210c2202, 0xf8c1f022, 
+    0x4640b2a3, 0x21032200, 0xf8bbf022, 0x4ffab2bb, 0x21032200, 0xf0224638, 0xb2b3f8b4, 0x22024638, 
+    0xf022210c, 0xb2abf8ae, 0x22044638, 0xf0222130, 0xb2a3f8a8, 0xe8bd4638, 0x220641f0, 0xf02221c0, 
+    0xb570b8a0, 0x23014ceb, 0x46052200, 0x46193c40, 0xf0224620, 0x4ae7f896, 0x4620462b, 0x4070e8bd, 
+    0x21013a2e, 0xbfadf022, 0x460db570, 0xf7ff4604, 0x2200ffe8, 0x0022f854, 0xd90142a8, 0xbd702001, 
+    0xb2521c52, 0xdbf52a04, 0xbd702000, 0x4605b570, 0x230048d8, 0x0100f248, 0x3834220f, 0xf871f022, 
+    0x24004ed4, 0xf8353e12, 0xf3c00014, 0xf4400009, 0xeb066180, 0xf0220044, 0x1c64f84a, 0x2c04b264, 
+    0xbd70dbf1, 0x48cbb283, 0x21012200, 0xf022383e, 0xe92db858, 0x4fc747f0, 0xf640b293, 0x46140800, 
+    0x460d3f1e, 0x4606220b, 0x46384641, 0xf849f022, 0x0900f247, 0xb2ab4638, 0x220c4649, 0xf841f022, 
+    0x0a00f248, 0xb2b34638, 0x220f4651, 0xf839f022, 0x46411cbf, 0x4638b2a3, 0xf022220b, 0xb2abf832, 
+    0x220c4649, 0xf0224638, 0xb2b3f82c, 0x220f4651, 0xf0224638, 0x1cbff826, 0xb2a34641, 0x220b4638, 
+    0xf81ff022, 0x4649b2ab, 0x4638220c, 0xf819f022, 0x4651b2b3, 0x4638220f, 0xf813f022, 0x4641b2a3, 
+    0x220b1cbc, 0xf0224620, 0xb2abf80c, 0x220c4649, 0xf0224620, 0xb2b3f806, 0x46204651, 0x47f0e8bd, 
+    0xf021220f, 0xb510bffe, 0x489a4604, 0xf021380a, 0xf000ffdb, 0x8020001f, 0x38084896, 0xffd4f021, 
+    0x001ff000, 0x48938060, 0xf0211f80, 0xf000ffcd, 0x80a0001f, 0x1f00488f, 0xffc6f021, 0x001ff000, 
+    0xbd1080e0, 0x460cb570, 0xb1434605, 0x1002f992, 0xf8252001, 0xf9920011, 0xf8251003, 0xf2400011, 
+    0x488616e0, 0x46312205, 0xffd9f021, 0x22058821, 0x80204408, 0x46314882, 0xffd1f021, 0x22058861, 
+    0x80604408, 0x4631487f, 0xffc9f021, 0x220588a1, 0x80a04408, 0x4631487c, 0xffc1f021, 0x440888e1, 
+    0x200180e0, 0xfc76f001, 0xf0012000, 0x4e71fc73, 0x3e0a2400, 0x0014f815, 0x001ff000, 0x0120f040, 
+    0x0044eb06, 0xff83f021, 0xb2641c64, 0xdbf12c04, 0xb5f0bd70, 0x20004605, 0x3f80f5b5, 0xd3014604, 
+    0xe000210f, 0x004a2107, 0xfa072701, 0x1c4af302, 0xf202fa00, 0x441a4422, 0xd80442aa, 0xf601fa07, 
+    0x0000ea46, 0xd0034614, 0x0393ea4f, 0x0101f1a1, 0xdb012900, 0xd1ea42aa, 0xb510bdf0, 0x4601460c, 
+    0x1e804854, 0xff53f021, 0x48584621, 0x4010e8bd, 0xbf4df021, 0x2301484f, 0x461a2102, 0xf0213840, 
+    0xb570bf60, 0xb2834d52, 0x460e4614, 0xf24f220c, 0x46280100, 0xff55f021, 0x46282208, 0x0151b2b3, 
+    0xff4ff021, 0xd0132c03, 0xd01b2c02, 0xd0232c01, 0xd12b2c00, 0x46282300, 0x21102204, 0xff41f021, 
+    0x21012300, 0x4628461a, 0x4070e8bd, 0xbf39f021, 0x46282300, 0x21802207, 0xff33f021, 0x22032300, 
+    0xe7f02108, 0x46282300, 0x21402206, 0xff29f021, 0x22022300, 0xe7e62104, 0x46282300, 0x21202205, 
+    0xff1ff021, 0x22012300, 0xe7dc2102, 0xb570bd70, 0x2a034d2f, 0xd013460c, 0xd01b2a02, 0xd0232a01, 
+    0xd12b2a00, 0x4628b283, 0x21102204, 0xff09f021, 0xb2a32200, 0x46282101, 0x4070e8bd, 0xbf01f021, 
+    0x4628b283, 0x21802207, 0xfefbf021, 0xb2a32203, 0xe7f02108, 0x4628b283, 0x21402206, 0xfef1f021, 
+    0xb2a32202, 0xe7e62104, 0x4628b283, 0x21202205, 0xfee7f021, 0xb2a32201, 0xe7dc2102, 0xb283bd70, 
+    0x22004813, 0x1f002101, 0xbedbf021, 0x4c09b570, 0x4605220c, 0x3c464603, 0x0100f241, 0xf0214620, 
+    0x462bfed0, 0xe8bd4620, 0x220a4070, 0x4100f240, 0xbec7f021, 0xf2030446, 0xf2035124, 0xf203c65e, 
+    0xf203ce5e, 0xf203d65e, 0xf203de5e, 0xf2031012, 0xf2030024, 0x46032200, 0x210f48c7, 0xbeb1f021, 
+    0xb51048c5, 0xfe90f021, 0x000ff000, 0x4603bd10, 0x220048c1, 0x31fff240, 0xf0213844, 0xb510bea2, 
+    0x46034604, 0x220748bc, 0x38482180, 0xfe99f021, 0x220048b9, 0x46232101, 0xf0211f00, 0x2200fe92, 
+    0xe8bd4623, 0x48b54010, 0xf0212101, 0xb570be8a, 0x220d4cb1, 0x46034605, 0xf2423c48, 0x46200100, 
+    0xfe7ff021, 0x4620462b, 0x4070e8bd, 0xf640220b, 0xf0210100, 0xe92dbe76, 0x4ca947f0, 0x21402301, 
+    0x22064692, 0x46204681, 0xfe6bf021, 0x46202301, 0x21042202, 0xfe65f021, 0x46202301, 0x461a2102, 
+    0xfe5ff021, 0x46202301, 0x46192200, 0xfe59f021, 0x23011ca5, 0x22064628, 0xf0212140, 0x2301fe52, 
+    0x22024628, 0xf0212104, 0x2301fe4c, 0x21024628, 0xf021461a, 0x2301fe46, 0x22004628, 0xf0214619, 
+    0x1d26fe40, 0x46302301, 0x21402206, 0xfe39f021, 0x46302301, 0x21042202, 0xfe33f021, 0x46302301, 
+    0x461a2102, 0xfe2df021, 0x46302301, 0x46192200, 0xfe27f021, 0x23011da7, 0x22064638, 0xf0212140, 
+    0x2301fe20, 0x22024638, 0xf0212104, 0x2301fe1a, 0x21024638, 0xf021461a, 0x2301fe14, 0x22004638, 
+    0xf0214619, 0xf106fe0e, 0x23010806, 0x22024640, 0xf0212104, 0x2301fe06, 0x21024640, 0xf021461a, 
+    0x2301fe00, 0x22004640, 0xf0214619, 0xf1b9fdfa, 0xd0430f00, 0x0000f89a, 0x0100f04f, 0x4620b1e8, 
+    0xfdd5f021, 0x46282100, 0xfdd1f021, 0x46302300, 0x21042202, 0xfde5f021, 0x46302300, 0x21022201, 
+    0xfddff021, 0x46382300, 0x21042202, 0xfdd9f021, 0x46382300, 0x21022201, 0x4630e01c, 0xfdb7f021, 
+    0x46382100, 0xfdb3f021, 0x46202300, 0x21022201, 0xfdc7f021, 0x46202300, 0x461a2101, 0xfdc1f021, 
+    0x46282300, 0x21022201, 0xfdbbf021, 0x46282300, 0x461a2101, 0x47f0e8bd, 0xbdb3f021, 0x87f0e8bd, 
+    0x4d45b570, 0x22014614, 0x35aa460e, 0x21024603, 0xf0214628, 0x1e64fda6, 0xb2a34628, 0x21f02204, 
+    0xfd9ff021, 0x46284633, 0x4070e8bd, 0x21012200, 0xbd97f021, 0x48384601, 0xf02130ac, 0x4836bd78, 
+    0xf02130ac, 0xb283bd71, 0x22004833, 0x71fff240, 0xf0213818, 0xb510bd86, 0xb2834c2f, 0xf6432200, 
+    0x3c3271ff, 0xf0214620, 0x2301fd7c, 0x220e4620, 0x4010e8bd, 0xf0210399, 0x2203bd74, 0x2108460b, 
+    0xd0092801, 0xd0042802, 0xd1072804, 0x21042202, 0x2201e004, 0xe0012102, 0x21012200, 0xf0214821, 
+    0x220cbd60, 0x2801460b, 0x0100f247, 0x2802d009, 0x2804d004, 0x1109d107, 0xe0042208, 0x22042170, 
+    0x2107e001, 0x48172200, 0xf0211c80, 0x4601bd4a, 0x1d004814, 0xbd2bf021, 0x210f4812, 0xf0211f00, 
+    0x4603bd26, 0x2200480f, 0x3828211f, 0xbd39f021, 0x480c4601, 0xf021382a, 0x4603bd1a, 0x22084809, 
+    0x7100f640, 0xf021382c, 0x4603bd2c, 0x22004805, 0x382c2101, 0xbd25f021, 0xf2030448, 0xf2031012, 
+    0xf2030000, 0xf20305de, 0x41f0e92d, 0x48fe4604, 0xfc77f7ff, 0x21004bfd, 0xf24a4dfd, 0x4afa0700, 
+    0x2662f249, 0xb9b05c60, 0x28126818, 0x2816d00d, 0xf995d00b, 0x28040000, 0x2805d007, 0xf852d005, 
+    0x42b00021, 0x2001d905, 0xf852e004, 0x42b80021, 0x2000d8f9, 0x1c495460, 0x2904b249, 0xe8bddbe2, 
+    0x200181f0, 0xf014b510, 0x2000f8eb, 0xfe47f7ff, 0xf2402100, 0xf7ff1000, 0x4ce6fd70, 0x68202100, 
+    0x2038f890, 0x003af9b0, 0xfd7df7fe, 0xf9b06820, 0xf7ff003e, 0x48e0ff50, 0xf6407801, 0xe8bd0000, 
+    0xf7fd4010, 0xe92dbba9, 0xb0874ff3, 0x90022000, 0x90049003, 0x48d79005, 0x88006800, 0x09d0ea4f, 
+    0x90062004, 0x780048d5, 0x2002b108, 0x27009006, 0x48d3e081, 0x980857c4, 0xa802b1f8, 0x6014f930, 
+    0xf930a804, 0xf2065014, 0xfb1612ff, 0xf240f006, 0xfb1531fe, 0x428a0005, 0xf205d803, 0x428a12ff, 
+    0x0100d921, 0xfd05f7ff, 0x04f1b200, 0xf2f0fb91, 0xfb9104e9, 0x1080f1f0, 0xf8dfe020, 0x23018308, 
+    0x22004dc1, 0x46184621, 0x5800e9cd, 0xf996f7fc, 0xf935a802, 0xf9386019, 0xf8205019, 0xa8046014, 
+    0x5014f820, 0x0280e7cf, 0xfce3f7ff, 0x05b1b200, 0xf2f0fb91, 0xfb9105a9, 0x1140f1f0, 0xf44f4680, 
+    0xea4f3000, 0xea4f1b62, 0xf6401a61, 0xf7f60101, 0xf44ffa9a, 0x46313000, 0xfa84f7f6, 0x3000f44f, 
+    0xf7f64629, 0xf44ffa7f, 0x46513000, 0xfa7af7f6, 0x3000f44f, 0xf7f64659, 0xf44ffa75, 0x46413000, 
+    0xfa70f7f6, 0xfa1f48a1, 0xeb00f18b, 0xf0210084, 0x489efc2e, 0xf18afa1f, 0xeb001c80, 0xf0210084, 
+    0x489afc26, 0xf188fa1f, 0xeb003810, 0xf0210044, 0x1c7ffc1e, 0x9806b2ff, 0xf4ff4287, 0x4c93af7a, 
+    0x22082302, 0x7100f64f, 0x46203c1e, 0xfc29f021, 0x46202201, 0xf3c8210e, 0xf021234f, 0x9807fc22, 
+    0x21012200, 0x4620b283, 0xfc1bf021, 0xe8bdb009, 0x20008ff0, 0xf7ffb510, 0x2101feca, 0xf7ff2008, 
+    0x2101fe9c, 0xf7ff2004, 0x2101fe98, 0xf7ff2002, 0x2101fe94, 0xf7ff4608, 0x2103fe90, 0xf7ff2008, 
+    0x2103fea0, 0xf7ff2004, 0x2103fe9c, 0xf7ff2002, 0x2103fe98, 0xf7ff2001, 0xf240fe94, 0xf7ff3000, 
+    0x2010feb7, 0xfeadf7ff, 0xf7ff2005, 0xe8bdfeb6, 0xf7ff4010, 0x486ebea1, 0xb5102100, 0xfbc7f021, 
+    0xffc7f7ff, 0x4010e8bd, 0xf7fd201c, 0xe92dbb80, 0x48604ff0, 0xf8dfb087, 0xf10db19c, 0xf10d0814, 
+    0x68000904, 0x08458800, 0x46a22400, 0xa000f8cd, 0x3000f8db, 0x20012200, 0x465f4656, 0xf7fcb261, 
+    0xf04ff8f5, 0x46c430ff, 0x6014f828, 0x0014f829, 0x2000683a, 0xe011464b, 0x1010f932, 0xda001e0f, 
+    0xf93c4279, 0x4571e014, 0x2f00dd06, 0x427fda00, 0x7014f82c, 0x0014f823, 0xb2001c40, 0xdbeb42a8, 
+    0x1014f933, 0x0c00f04f, 0xe009460f, 0x0011f932, 0xda002800, 0x1c494240, 0xfa0f4460, 0xb209fc80, 
+    0xdbf342a9, 0x2000a903, 0x1cecea4f, 0x6014f821, 0xe00f4606, 0xe010f932, 0x0f00f1be, 0xf1ceda01, 
+    0x44760e00, 0x4566b236, 0xf821dd02, 0xe0030014, 0xb2001c40, 0xdced4287, 0xb2241c64, 0xdba52c04, 
+    0x24002001, 0xf9334622, 0xf9335010, 0x42b56014, 0x4604dd00, 0x6010f931, 0x7012f931, 0xf9331bad, 
+    0x1bf66012, 0xdd0042b5, 0x1c404602, 0x2804b200, 0xf833dbe9, 0xf8390014, 0xf8313012, 0xebc01012, 
+    0x1a400043, 0xb2043808, 0xdd702c00, 0xd00107e0, 0xb2241c64, 0x4e184d20, 0xeb008828, 0x80280064, 
+    0x10607831, 0xfbb3f7fe, 0x22017833, 0x1000f9b5, 0xf7fe4620, 0x7831fc66, 0x1000f240, 0xfa0cf7fd, 
+    0x0500f44f, 0x11f4f240, 0xf7f64628, 0xf04ff95c, 0x46283134, 0xf946f7f6, 0x1004f9bd, 0xf7f64628, 
+    0xf9bdf941, 0xe0191006, 0x000434e0, 0x00040240, 0x00040292, 0x00042618, 0x00040293, 0x0004232e, 
+    0x00042598, 0x00049200, 0x00048a00, 0xf2030040, 0xf2030400, 0x00040238, 0x0004257e, 0xf7f64628, 
+    0xf9bdf921, 0x46281008, 0xf91cf7f6, 0x100af9bd, 0xf7f64628, 0xf9bdf917, 0x4628100c, 0xf912f7f6, 
+    0x100ef9bd, 0xf7f64628, 0xf9bdf90d, 0x46281010, 0xf908f7f6, 0x1012f9bd, 0xf7f64628, 0x4621f903, 
+    0xf7f64628, 0x49bbf8ff, 0xf7f64628, 0xb007f8fb, 0xe92de6bd, 0x46065ffc, 0xf8df48b7, 0x250092e0, 
+    0x680046a8, 0xea4f8800, 0x24000b50, 0xd10242ac, 0x0000f04f, 0xda02e004, 0x0001f104, 0x4620e000, 
+    0x7000f8d9, 0xfa80fa4f, 0x463b4629, 0xf04f4652, 0xf8cd0001, 0xf7fb8000, 0xeb06ffe9, 0x5d400084, 
+    0x4659b958, 0xf0224638, 0x2300fa9b, 0x20014652, 0xe9cd4629, 0xf7fb7800, 0x1c64ff06, 0x2c04b264, 
+    0x1c6ddbd4, 0x2d04b26d, 0x2400dbcf, 0x20004621, 0xd0044288, 0x0280eb06, 0xb1025c52, 0x1c402401, 
+    0x2804b240, 0x1c49dbf4, 0x2904b249, 0x4e94dbef, 0xf0214630, 0xb200fa69, 0xf040b16c, 0x24000507, 
+    0xeb06b2a9, 0xf0210044, 0x1c64fa62, 0x2c04b264, 0xe8bddbf6, 0xf0209ffc, 0xe7f00507, 0x4ff0e92d, 
+    0x22004885, 0xf04f2101, 0xb087085a, 0x88006800, 0xf04f0847, 0xf0214071, 0xb240fa5b, 0x20009005, 
+    0xfd96f7fd, 0xa1f4f8df, 0x46b12600, 0x42b42400, 0xf04fd102, 0xe0040000, 0xf104da02, 0xe0000001, 
+    0xf8da4620, 0xb242b000, 0x465b4631, 0x0001f04f, 0x9000f8cd, 0xff7af7fb, 0x463a2500, 0xfb074658, 
+    0xf014f105, 0x4540fdae, 0x1e6ddc03, 0x2d00b26d, 0xa801daf3, 0x0084eb00, 0x42b41c6d, 0xd1015585, 
+    0x55812101, 0xb2641c64, 0xdbd02c04, 0xb2761c76, 0xdbcb2e04, 0xf7ffa801, 0xa801ff4c, 0xf9b8f7fe, 
+    0xf7fd9805, 0xf44ffd55, 0xf2400400, 0x462011f4, 0xf849f7f6, 0xf021485a, 0x4601f9f7, 0xf7f64620, 
+    0x4857f831, 0xf0211c80, 0x4601f9ef, 0xf7f64620, 0x4853f829, 0xf0211d00, 0x4601f9e7, 0xf7f64620, 
+    0x484ff821, 0xf0211d80, 0x4601f9df, 0xf7f64620, 0x484cf819, 0xf9d2f021, 0x46204601, 0xf812f7f6, 
+    0x30404848, 0xf9caf021, 0x46204601, 0xf80af7f6, 0x46204940, 0xf806f7f6, 0xe92de709, 0x46074ff8, 
+    0xf8df483d, 0x240080f8, 0x460d4616, 0xf04f46a2, 0x68003bff, 0xea4f8800, 0xf8cd0950, 0xf8d8a000, 
+    0x22003000, 0xb2612001, 0xff00f7fb, 0xa014f825, 0xb014f827, 0xf8262000, 0xe01bb014, 0x1000f8d8, 
+    0x1010f931, 0xda001e0b, 0xf9354259, 0x4561c014, 0x0019dd0e, 0x4259d500, 0x1014f825, 0x0014f827, 
+    0x1000f8d8, 0x1010f831, 0x31c0f3c1, 0x1014f826, 0xb2001c40, 0xdbe14548, 0xb2241c64, 0xdbcc2c04, 
+    0x8ff8e8bd, 0xe92d491c, 0x680943f8, 0x88094d1b, 0x0951ea4f, 0x91002100, 0x682b460a, 0x2001b241, 
+    0xfec4f7fb, 0xf8d52200, 0x46138000, 0x46114610, 0xe0124614, 0x5014f838, 0xf505fb15, 0x195217ee, 
+    0xfba54173, 0x17e7ce04, 0xe604fb06, 0x6507fb05, 0x0000eb1c, 0x1c644169, 0x454cb224, 0xea52dbea, 
+    0xd0040403, 0xead4f020, 0xe8bdb200, 0x200083f8, 0x0000e7fb, 0xdcba01f5, 0x00042618, 0x00040238, 
+    0xf2030000, 0xf1000008, 0x4ff7e92d, 0x4cf92301, 0x039f220e, 0x46394620, 0xf953f021, 0x0800f241, 
+    0x23014620, 0x220c4641, 0xf94bf021, 0x0900f640, 0x23014620, 0x220b4649, 0xf943f021, 0x4a00f240, 
+    0x23014620, 0x220a4651, 0xf93bf021, 0x2b00f240, 0x23014620, 0x22094659, 0xf933f021, 0x46202208, 
+    0x01512301, 0xf92df021, 0x46202301, 0x21802207, 0xf927f021, 0x46202301, 0x21402206, 0xf921f021, 
+    0x46391ca5, 0x46282301, 0xf021220e, 0x2301f91a, 0x220c4641, 0xf0214628, 0x2301f914, 0x220b4649, 
+    0xf0214628, 0x2301f90e, 0x220a4651, 0xf0214628, 0x2301f908, 0x22094659, 0xf0214628, 0x2208f902, 
+    0x23014628, 0xf0210151, 0x2301f8fc, 0x22074628, 0xf0212180, 0x2301f8f6, 0x22064628, 0xf0212140, 
+    0x1d26f8f0, 0x23014639, 0x220e4630, 0xf8e9f021, 0x46412301, 0x4630220c, 0xf8e3f021, 0x46492301, 
+    0x4630220b, 0xf8ddf021, 0x46512301, 0x4630220a, 0xf8d7f021, 0x46592301, 0x46302209, 0xf8d1f021, 
+    0x46302208, 0x01512301, 0xf8cbf021, 0x46302301, 0x21802207, 0xf8c5f021, 0x46302301, 0x21402206, 
+    0xf8bff021, 0x1da74639, 0x46382301, 0xf021220e, 0x2301f8b8, 0x220c4641, 0xf0214638, 0x2301f8b2, 
+    0x220b4649, 0xf0214638, 0x2301f8ac, 0x220a4651, 0xf0214638, 0x2301f8a6, 0x22094659, 0xf0214638, 
+    0x2208f8a0, 0x23014638, 0xf0210151, 0x2301f89a, 0x22074638, 0xf0212180, 0x2301f894, 0x22064638, 
+    0xf0212140, 0x2301f88e, 0x22054620, 0xf0212120, 0x2301f888, 0x22034620, 0xf0212108, 0x2301f882, 
+    0x21024620, 0xf021461a, 0x2301f87c, 0x22054628, 0xf0212120, 0x2301f876, 0x22034628, 0xf0212108, 
+    0x2301f870, 0x21024628, 0xf021461a, 0x2301f86a, 0x22054630, 0xf0212120, 0x2301f864, 0x22034630, 
+    0xf0212108, 0x2301f85e, 0x21024630, 0xf021461a, 0x2301f858, 0x22054638, 0xf0212120, 0x2301f852, 
+    0x22034638, 0xf0212108, 0x2301f84c, 0x21024638, 0xf021461a, 0x2301f846, 0x22044620, 0xf0212110, 
+    0x2301f840, 0x22024620, 0xf0212104, 0x2301f83a, 0x22004620, 0xf0214619, 0x2301f834, 0x22044628, 
+    0xf0212110, 0x2301f82e, 0x22024628, 0xf0212104, 0x2301f828, 0x22004628, 0xf0214619, 0x2301f822, 
+    0x22044630, 0xf0212110, 0x2301f81c, 0x22024630, 0xf0212104, 0x2301f816, 0x22004630, 0xf0214619, 
+    0x2301f810, 0x22044638, 0xf0212110, 0x2301f80a, 0x22024638, 0xf0212104, 0x2301f804, 0x22004638, 
+    0xf0204619, 0x9800fffe, 0xd0742800, 0x78009802, 0x2100b3c0, 0xf0204620, 0x2100ffda, 0xf0204628, 
+    0x2300ffd6, 0x22054630, 0xf0202120, 0x2300ffea, 0x22044630, 0xf0202110, 0x2300ffe4, 0x22034630, 
+    0xf0202108, 0x2300ffde, 0x22024630, 0xf0202104, 0x2300ffd8, 0x22054638, 0xf0202120, 0x2300ffd2, 
+    0x22044638, 0xf0202110, 0x2300ffcc, 0x22034638, 0xf0202108, 0x2300ffc6, 0x22024638, 0xf0202104, 
+    0xe038ffc0, 0x2300e7ff, 0x22034620, 0xf0202108, 0x2300ffb8, 0x22024620, 0xf0202104, 0x2300ffb2, 
+    0x22014620, 0xf0202102, 0x2300ffac, 0x21014620, 0xf020461a, 0x2300ffa6, 0x22034628, 0xf0202108, 
+    0x2300ffa0, 0x22024628, 0xf0202104, 0x2300ff9a, 0x22014628, 0xf0202102, 0x2300ff94, 0x21014628, 
+    0xf020461a, 0x2100ff8e, 0xf0204630, 0x2100ff70, 0xf0204638, 0x4c0fff6c, 0x22022301, 0x21043408, 
+    0xf0204620, 0x2301ff7e, 0x21024620, 0xf020461a, 0xb003ff78, 0x23014620, 0x46192200, 0x4ff0e8bd, 
+    0xbf6ff020, 0x48034603, 0x217f2200, 0xf020300e, 0x0000bf68, 0xf2031000, 0x4604b510, 0xf64f4829, 
+    0xf02071ff, 0x4827ff44, 0x1c802100, 0xff3ff020, 0xb2a34824, 0x21012200, 0x4010e8bd, 0xf0201e80, 
+    0xe92dbf50, 0x4c1f41f0, 0xb283461d, 0x3c224616, 0x2206460f, 0x21c04620, 0xff43f020, 0x4620b2bb, 
+    0x21302204, 0xff3df020, 0x4620b2b3, 0x210c2202, 0xff37f020, 0x4620b2ab, 0x41f0e8bd, 0x21032200, 
+    0xbf2ff020, 0x480fb283, 0x21012200, 0xf0203820, 0xb570bf28, 0xd0130004, 0x4d0a2300, 0x1ead2201, 
+    0x46282102, 0xff1df020, 0x4628b2a3, 0x21012200, 0xff17f020, 0x1da82104, 0x4070e8bd, 0xbef7f020, 
+    0xe7ea2301, 0xf2031032, 0x5fffe92d, 0x48994681, 0xb264f8df, 0x68002500, 0xea4f8800, 0x48970a50, 
+    0x0045eb00, 0xf0209003, 0xb207fedf, 0x42ac2400, 0xf04fd102, 0xe0040000, 0xf104da02, 0xe0000001, 
+    0x42ac4620, 0x9002b240, 0xf04fd102, 0xe0010608, 0x0602f04f, 0xf04fd102, 0xe00b0106, 0xf04fdd02, 
+    0xe0010001, 0x0000f04f, 0x0000eba4, 0x0040ea4f, 0x0104f1c0, 0x0301f04f, 0x1244eb09, 0x0001f1a6, 
+    0x02c5eb02, 0x0c06eb01, 0x5c11e01e, 0xd01d2901, 0xdb102803, 0xd10e2c03, 0xd10c2d03, 0x1000f819, 
+    0xeb09b9a1, 0xf8910100, 0xf1bee028, 0xd10d0f00, 0x1050f891, 0xebacb951, 0x1e490100, 0xf101fa03, 
+    0x1e40438f, 0xb240b23f, 0xdade2800, 0x9a021c40, 0xf880fa4f, 0x20004629, 0xf8db9000, 0xf7fb3000, 
+    0x45b0fbd5, 0xeba6da17, 0xf8db0108, 0x465e2000, 0xf00afb11, 0xfb18b281, 0xeb02f00a, 0xf0210040, 
+    0x2100fe7f, 0x9a026830, 0xe9cd460b, 0x20000100, 0xf7fb4629, 0x1c64fae8, 0x2c04b264, 0xb2b9db87, 
+    0xf0209803, 0x1c6dfe64, 0x2d04b26d, 0xaf77f6ff, 0x9fffe8bd, 0x4ff0e92d, 0xb0a3484e, 0x88006800, 
+    0x0850ea4f, 0x7800484e, 0xd2012850, 0xe0002020, 0x22002010, 0x21014681, 0x4071f04f, 0xfe58f020, 
+    0x9021b240, 0xf7fd2000, 0xf8dff993, 0x2600a10c, 0x240046b3, 0xd10242b4, 0x0000f04f, 0xda02e004, 
+    0x0001f104, 0x4620e000, 0xb24242b4, 0x2508d101, 0x2502e000, 0xb000f8cd, 0x3000f8da, 0x46572000, 
+    0xf7fb4631, 0xa801fb73, 0xeb0046ba, 0x1e6d1044, 0x07c6eb00, 0xf8dae00e, 0x46420000, 0xf105fb18, 
+    0xf99ff014, 0xdd014548, 0xe0002001, 0x55782000, 0xb26d1e6d, 0xdaee2d00, 0xb2641c64, 0xdbc92c04, 
+    0xb2761c76, 0xdbc42e04, 0xf7ffa801, 0xa801ff0d, 0xfd42f7fd, 0xf7fd9821, 0xf44ff94b, 0xf2400400, 
+    0x462011f4, 0xfc3ff7f5, 0xf020481c, 0x4601fded, 0xf7f54620, 0x4819fc27, 0xf0201c80, 0x4601fde5, 
+    0xf7f54620, 0x4815fc1f, 0xf0201d00, 0x4601fddd, 0xf7f54620, 0x4811fc17, 0xf0201d80, 0x4601fdd5, 
+    0xf7f54620, 0x480ffc0f, 0xfdc8f020, 0x46204601, 0xfc08f7f5, 0x3040480b, 0xfdc0f020, 0x46204601, 
+    0xfc00f7f5, 0x46204908, 0xfbfcf7f5, 0xe8bdb023, 0x00008ff0, 0x00042618, 0x00040238, 0xf2031000, 
+    0x0004257c, 0xf1000008, 0xdcba01f5, 0x23004831, 0xf248220f, 0xb5100100, 0xfdc3f020, 0x7801482e, 
+    0xf7fc2040, 0x2300fc99, 0x2201482c, 0x4010e8bd, 0xf0202102, 0x210fbdb6, 0x422bf04f, 0x2000f44f, 
+    0xf7f5b508, 0xf7fffc2e, 0x2100ffe1, 0xf0004608, 0x2300f895, 0x21014822, 0xf020461a, 0x2000fda2, 
+    0x0200f242, 0x46014603, 0xf0009000, 0xbd08f83b, 0x481a4601, 0x29043022, 0x2905d006, 0x2300d006, 
+    0x21032200, 0xbd8df020, 0xe7f92303, 0xe7f72302, 0xf7ffb508, 0x2101ffed, 0xf0004608, 0x2301f86f, 
+    0x2102480e, 0xf020461a, 0x2301fd7c, 0x2200480c, 0xf0204619, 0x2000fd76, 0x7203f247, 0xf6402317, 
+    0x90004102, 0x1084f240, 0xf80cf000, 0x4008e8bd, 0xbe88f001, 0xf2035026, 0x00040293, 0xf23c8310, 
+    0xf203529a, 0x47f0e92d, 0x460d4c6c, 0x461eb281, 0x8020f8dd, 0x46204617, 0xfd39f020, 0x1ca5b2a9, 
+    0xf0204628, 0xf104fd34, 0xb2b90a04, 0xf0204650, 0xb2b1fd2e, 0x46301da6, 0xfd29f020, 0xfa1f1daf, 
+    0x4638f188, 0xfd23f020, 0x2301b672, 0x916cf8df, 0x0800f248, 0x090cf109, 0x220f4641, 0xf0204648, 
+    0x2300fd30, 0x220f4641, 0xf0204648, 0xb662fd2a, 0x46202100, 0xfd0bf020, 0x46282100, 0xfd07f020, 
+    0x46502100, 0xfd03f020, 0x46302100, 0xfcfff020, 0xe8bd4638, 0x210047f0, 0xbcf9f020, 0x4c47b570, 
+    0x460d220a, 0x34104606, 0xf2404603, 0x46204100, 0xfd07f020, 0x46332209, 0x2100f240, 0xf0204620, 
+    0x462bfd00, 0xe8bd4620, 0x22024070, 0xf0202104, 0xb510bcf8, 0x23014c39, 0x3410220e, 0x46200399, 
+    0xfceff020, 0x46202301, 0x21402206, 0xfce9f020, 0x48332301, 0x46192200, 0xfce3f020, 0x23014c31, 
+    0x21102204, 0xf0204620, 0x2301fcdc, 0x22024620, 0xf0202104, 0x2301fcd6, 0x22034620, 0xf0202108, 
+    0x2300fcd0, 0x22044620, 0xf0202110, 0x4c26fcca, 0x22042300, 0x46202110, 0xfcc3f020, 0x46202301, 
+    0xe8bd2204, 0x21104010, 0xbcbbf020, 0x47f0e92d, 0x00054c1e, 0xe9dd4699, 0xd0098608, 0xd00f2903, 
+    0xd00d2905, 0xd00b2904, 0xd0092902, 0xd0072901, 0x46202300, 0x47f0e8bd, 0x21102204, 0xbca1f020, 
+    0x210f4f13, 0x22004613, 0xf0204638, 0x2204fc9a, 0x21f0464b, 0xf0204638, 0x220afc94, 0xf2404643, 
+    0x46384100, 0xfc8df020, 0x4633220b, 0x0100f640, 0xf0204638, 0x462bfc86, 0x0000e7db, 0xf23c8300, 
+    0xf23d0004, 0xf203529a, 0xf2039000, 0xf23c80a0, 0xf23d012a, 0x4cf9b570, 0x2801b398, 0x2802d035, 
+    0x2803d037, 0x2301d01f, 0x22004620, 0xf0204619, 0xf44ffc68, 0x21003580, 0xf7fc4628, 0x2301fb3d, 
+    0x21024620, 0xf020461a, 0x2100fc5c, 0xf7fc4628, 0x2301fb33, 0x22024620, 0xf0202104, 0x2100fc52, 
+    0xf7fc4628, 0x2301fb29, 0x21082203, 0xf0204620, 0x2300fc48, 0xe8bd48e2, 0x21014070, 0xf020461a, 
+    0x2301bc40, 0x46192200, 0x2301e7f0, 0x461a2102, 0x2301e7ec, 0x21042202, 0xb570e7e8, 0xb3904cd7, 
+    0xd0342801, 0xd0362802, 0xf04f2803, 0xd0360300, 0x46202200, 0xf0202101, 0xf44ffc24, 0x21003580, 
+    0xf7fc4628, 0x2300faf9, 0x22014620, 0xf0202102, 0x2100fc18, 0xf7fc4628, 0x2300faef, 0x22024620, 
+    0xf0202104, 0x2100fc0e, 0xf7fc4628, 0x2300fae5, 0x22034620, 0xf0202108, 0x4628fc04, 0x4070e8bd, 
+    0xf7fc2100, 0x2300bad9, 0x461a2101, 0x2300e009, 0x21022201, 0x2300e005, 0x21042202, 0x2203e001, 
+    0x46202108, 0x4070e8bd, 0xbbebf020, 0x2202b510, 0x21044604, 0x48b34603, 0xfbe3f020, 0x220248b2, 
+    0x46232104, 0xfbddf020, 0x220248b0, 0x46232104, 0xfbd7f020, 0x46232202, 0x4010e8bd, 0x210448ac, 
+    0xbbcff020, 0x4604b510, 0x48a64603, 0x21102204, 0xf020380c, 0x48a4fbc6, 0x21102204, 0x380c4623, 
+    0xfbbff020, 0x220448a1, 0x46232110, 0xf020380c, 0x489ffbb8, 0x21102204, 0xe8bd4623, 0x380c4010, 
+    0xbbaff020, 0x4605b570, 0x48964603, 0x2400f240, 0x46212209, 0xf0203814, 0x4893fba4, 0x462b2209, 
+    0x38144621, 0xfb9df020, 0x22094890, 0x4621462b, 0xf0203814, 0x488efb96, 0x4621462b, 0x4070e8bd, 
+    0x38142209, 0xbb8df020, 0x2200b510, 0x21014604, 0x48844603, 0xfb85f020, 0x22004883, 0x46232101, 
+    0xfb7ff020, 0x22004881, 0x46232101, 0xfb79f020, 0x46232200, 0x4010e8bd, 0x2101487d, 0xbb71f020, 
+    0x2204b510, 0x21304604, 0x48764603, 0xfb69f020, 0x22044875, 0x46232130, 0xfb63f020, 0x22044873, 
+    0x46232130, 0xfb5df020, 0x46232204, 0x4010e8bd, 0x2130486f, 0xbb55f020, 0xf240b570, 0x460514c0, 
+    0x46032206, 0x46214867, 0xfb4bf020, 0x22064866, 0x4621462b, 0xfb45f020, 0x22064864, 0x4621462b, 
+    0xfb3ff020, 0x4621462b, 0x4070e8bd, 0x22064860, 0xbb37f020, 0x2201b510, 0x21024604, 0x48594603, 
+    0xfb2ff020, 0x22014858, 0x46232102, 0xfb29f020, 0x22014856, 0x46232102, 0xfb23f020, 0x46232201, 
+    0x4010e8bd, 0x21024852, 0xbb1bf020, 0x41f0e92d, 0x23004c4c, 0x46802101, 0x461a3c24, 0xf0204620, 
+    0x4d49fb10, 0x21012300, 0x3d24461a, 0xf0204628, 0x4e46fb08, 0x21012300, 0x3e24461a, 0xf0204630, 
+    0x4f43fb00, 0x21012300, 0x3f24461a, 0xf0204638, 0x2200faf8, 0x21014643, 0xf0204620, 0x2200faf2, 
+    0x21014643, 0xf0204628, 0x2200faec, 0x21014643, 0xf0204630, 0x4643fae6, 0xe8bd4638, 0x220041f0, 
+    0xf0202101, 0xb510bade, 0x46034604, 0x2204482d, 0x38202170, 0xfad5f020, 0x2204482b, 0x46232170, 
+    0xf0203820, 0x4829face, 0x21702204, 0x38204623, 0xfac7f020, 0x22044826, 0x46232170, 0x4010e8bd, 
+    0xf0203820, 0xb570babe, 0x22004c1c, 0x46052101, 0x46031ca4, 0xf0204620, 0x2201fab4, 0x2102462b, 
+    0xf0204620, 0x2202faae, 0x2104462b, 0xf0204620, 0x462bfaa8, 0xe8bd4620, 0x22034070, 0xf0202108, 
+    0xb510baa0, 0x46042201, 0x46032106, 0xf0204811, 0x4811fa98, 0x21062201, 0xf0204623, 0x480ffa92, 
+    0x21062201, 0xf0204623, 0x2201fa8c, 0xe8bd4623, 0x480b4010, 0xf0202106, 0x0000ba84, 0xf2034222, 
+    0xf20305cc, 0xf203c624, 0xf203ce24, 0xf203d624, 0xf203de24, 0xf203c186, 0xf203c986, 0xf203d186, 
+    0xf203d986, 0x47f0e92d, 0x460f4691, 0x46042204, 0x46032110, 0xf02048f8, 0x48f8fa64, 0x21102204, 
+    0xf0204623, 0x48f6fa5e, 0x21102204, 0xf0204623, 0x48f4fa58, 0x21102204, 0xf0204623, 0x4ceefa52, 
+    0x0600f241, 0x463b220c, 0x46313486, 0xf0204620, 0x4deafa48, 0x463b220c, 0x35864631, 0xf0204628, 
+    0xf8dffa40, 0x220c839c, 0x4631463b, 0x0886f108, 0xf0204640, 0x4631fa36, 0x220c4ee2, 0x3686463b, 
+    0xf0204630, 0xf242fa2e, 0x464b0700, 0x4639220d, 0xf0204620, 0x220dfa26, 0x4639464b, 0xf0204628, 
+    0x220dfa20, 0x4639464b, 0xf0204640, 0x464bfa1a, 0x46304639, 0x47f0e8bd, 0xf020220d, 0xb570ba12, 
+    0x75e0f641, 0xb2834604, 0x220548cf, 0xf0204629, 0xb2a3fa08, 0x220548cd, 0xf0204629, 0xb2a3fa02, 
+    0x220548cb, 0xf0204629, 0xb2a3f9fc, 0xe8bd4629, 0x48c84070, 0xf0202205, 0xb570b9f4, 0xf0004ec6, 
+    0xf3c00503, 0x22020482, 0x211c4623, 0xf0204630, 0x2200f9e8, 0x2103462b, 0xf0204630, 0x4ebff9e2, 
+    0x211c2202, 0x46304623, 0xf9dbf020, 0x462b2200, 0x46302103, 0xf9d5f020, 0x22024eb9, 0x4623211c, 
+    0xf0204630, 0x2200f9ce, 0x2103462b, 0xf0204630, 0x4623f9c8, 0x22024cb3, 0x4620211c, 0xf9c1f020, 
+    0x4620462b, 0x4070e8bd, 0x21032200, 0xb9b9f020, 0x4604b510, 0x48a04603, 0x21382203, 0xf0203008, 
+    0x489ef9b0, 0x21382203, 0x30084623, 0xf9a9f020, 0x2203489b, 0x46232138, 0xf0203008, 0x4899f9a2, 
+    0x21382203, 0xe8bd4623, 0x30084010, 0xb999f020, 0x4ff7e92d, 0xa250f8df, 0x0601f002, 0x09c0f3c2, 
+    0xf1aa460c, 0x9b000a08, 0x0880f3c2, 0x0100f643, 0x0740f3c2, 0x220b4650, 0xf983f020, 0x0503f004, 
+    0x0100f24c, 0x462b220e, 0xf0204650, 0xf3c4f97a, 0x22000380, 0x2101461c, 0x0002f10a, 0xf971f020, 
+    0x4b00f240, 0x23004650, 0x220a4659, 0xf969f020, 0x46592301, 0x4650220a, 0xf963f020, 0x46592300, 
+    0x4650220a, 0xf95df020, 0xa1e0f8df, 0x9b00220b, 0x0100f643, 0x0a08f1aa, 0xf0204650, 0x220ef952, 
+    0xf24c462b, 0x46500100, 0xf94bf020, 0x46232200, 0xf10a2101, 0xf0200002, 0x2300f944, 0x220a4659, 
+    0xf0204650, 0x2301f93e, 0x220a4659, 0xf0204650, 0x2300f938, 0x220a4659, 0xf0204650, 0xf8dff932, 
+    0x220ba190, 0xf6439b00, 0xf1aa0100, 0x46500a08, 0xf927f020, 0x462b220e, 0x0100f24c, 0xf0204650, 
+    0x2200f920, 0x21014623, 0x0002f10a, 0xf919f020, 0x46592300, 0x4650220a, 0xf913f020, 0x46592301, 
+    0x4650220a, 0xf90df020, 0x46592300, 0x4650220a, 0xf907f020, 0xa13cf8df, 0x9b00220b, 0x0100f643, 
+    0x0a08f1aa, 0xf0204650, 0x220ef8fc, 0xf24c462b, 0x46500100, 0xf8f5f020, 0x46232200, 0xf10a2101, 
+    0xf0200002, 0x2300f8ee, 0x220a4659, 0xf0204650, 0x2301f8e8, 0x220a4659, 0xf0204650, 0x2300f8e2, 
+    0x220a4659, 0xf0204650, 0x4c37f8dc, 0x21012200, 0x4620463b, 0xf8d5f020, 0x464b2201, 0x46202102, 
+    0xf8cff020, 0x46432202, 0x46202104, 0xf8c9f020, 0x46332203, 0x46202108, 0xf8c3f020, 0x22004c2b, 
+    0x463b2101, 0xf0204620, 0x2201f8bc, 0x2102464b, 0xf0204620, 0x2202f8b6, 0x21044643, 0xf0204620, 
+    0x2203f8b0, 0x21084633, 0xf0204620, 0x4c20f8aa, 0x21012200, 0x4620463b, 0xf8a3f020, 0x464b2201, 
+    0x46202102, 0xf89df020, 0x46432202, 0x46202104, 0xf897f020, 0x46332203, 0x46202108, 0xf891f020, 
+    0x22004c14, 0x463b2101, 0xf0204620, 0x2201f88a, 0x2102464b, 0xf0204620, 0x2202f884, 0x21044643, 
+    0xf0204620, 0xb003f87e, 0x46204633, 0xe8bd2203, 0x21084ff0, 0xb875f020, 0xf203c104, 0xf203c904, 
+    0xf203d104, 0xf203d904, 0xf203c618, 0xf203ce18, 0xf203d618, 0xf203de18, 0xf203c208, 0xf203ca08, 
+    0xf203d208, 0xf203da08, 0xb283b570, 0x48fb4604, 0x21802207, 0xf855f020, 0x48f9b2a3, 0x21802207, 
+    0xf84ff020, 0x48f7b2a3, 0x21802207, 0xf849f020, 0x48f5b2a3, 0x21802207, 0xf843f020, 0xf24048ef, 
+    0xb2a34500, 0x220a4629, 0xf0201c80, 0x48ecf83a, 0x220ab2a3, 0x1c804629, 0xf833f020, 0xb2a348e9, 
+    0x4629220a, 0xf0201c80, 0xb2a3f82c, 0x462948e6, 0x4070e8bd, 0x1c80220a, 0xb823f020, 0x41f0e92d, 
+    0x22054cde, 0x46802120, 0x46031ea4, 0xf0204620, 0x4ddbf818, 0x21202205, 0x1ead4643, 0xf0204628, 
+    0x4ed8f810, 0x21202205, 0x1eb64643, 0xf0204630, 0x4fd5f808, 0x21202205, 0x1ebf4643, 0xf0204638, 
+    0x2204f800, 0x21104643, 0xf01f4620, 0x2204fffa, 0x21104643, 0xf01f4628, 0x2204fff4, 0x21104643, 
+    0xf01f4630, 0x2204ffee, 0x21104643, 0xf01f4638, 0xe8bdffe8, 0x210041f0, 0x1000f240, 0xbebcf7fb, 
+    0x41f0e92d, 0x22064cbd, 0x46802140, 0x46031ca4, 0xf01f4620, 0x4dbaffd6, 0x21402206, 0x1cad4643, 
+    0xf01f4628, 0x4eb7ffce, 0x21402206, 0x1cb64643, 0xf01f4630, 0x4fb4ffc6, 0x21402206, 0x1cbf4643, 
+    0xf01f4638, 0x2205ffbe, 0x21204643, 0xf01f4620, 0x2205ffb8, 0x21204643, 0xf01f4628, 0x2205ffb2, 
+    0x21204643, 0xf01f4630, 0x2205ffac, 0x21204643, 0xf01f4638, 0xe8bdffa6, 0x210041f0, 0x0000f241, 
+    0xbe7af7fb, 0x2204b510, 0x21304604, 0x489f4603, 0xff97f01f, 0x2204489e, 0x46232130, 0xff91f01f, 
+    0x2204489c, 0x46232130, 0xff8bf01f, 0x46232204, 0x4010e8bd, 0x21304898, 0xbf83f01f, 0x4605b570, 
+    0x488e4603, 0x14c0f240, 0x46212206, 0xf01f387c, 0x488bff78, 0x462b2206, 0x387c4621, 0xff71f01f, 
+    0x22064888, 0x4621462b, 0xf01f387c, 0x4886ff6a, 0x4621462b, 0x4070e8bd, 0x387c2206, 0xbf61f01f, 
+    0x5fffe92d, 0xf6414d7d, 0x46170400, 0x1fad4689, 0x220b4680, 0xe9dd4603, 0x4621ba0f, 0xf01f4628, 
+    0x2208ff50, 0x4628464b, 0x46310156, 0xff49f01f, 0x463b2207, 0x46282180, 0xff43f01f, 0x22059b03, 
+    0x46282160, 0xff3df01f, 0x22039b0e, 0x46282108, 0xff37f01f, 0x465b2202, 0x46282104, 0xff31f01f, 
+    0x46532200, 0x46282103, 0xff2bf01f, 0x220b4d64, 0x46214643, 0x46281fad, 0xff23f01f, 0x464b2208, 
+    0x46284631, 0xff1df01f, 0x463b2207, 0x46282180, 0xff17f01f, 0x22059b03, 0x46282160, 0xff11f01f, 
+    0x22039b0e, 0x46282108, 0xff0bf01f, 0x465b2202, 0x46282104, 0xff05f01f, 0x46532200, 0x46282103, 
+    0xfefff01f, 0x220b4d4f, 0x46214643, 0x46281fad, 0xfef7f01f, 0x464b2208, 0x46284631, 0xfef1f01f, 
+    0x463b2207, 0x46282180, 0xfeebf01f, 0x22059b03, 0x46282160, 0xfee5f01f, 0x22039b0e, 0x46282108, 
+    0xfedff01f, 0x465b2202, 0x46282104, 0xfed9f01f, 0x46532200, 0x46282103, 0xfed3f01f, 0x4c3a4621, 
+    0x4643220b, 0x46201fa4, 0xfecbf01f, 0x464b2208, 0x46204631, 0xfec5f01f, 0x463b2207, 0x46202180, 
+    0xfebff01f, 0x22059b03, 0x46202160, 0xfeb9f01f, 0x22039b0e, 0x46202108, 0xfeb3f01f, 0x465b2202, 
+    0x46202104, 0xfeadf01f, 0x4653b004, 0x22004620, 0x5ff0e8bd, 0xf01f2103, 0xe92dbea4, 0x4d1f41f0, 
+    0x0400f244, 0x460e220e, 0x46071d2d, 0x46214603, 0xf01f4628, 0x2206fe96, 0x21404633, 0xf01f4628, 
+    0x4d17fe90, 0x463b220e, 0x1d2d4621, 0xf01f4628, 0x2206fe88, 0x21404633, 0xf01f4628, 0x4d11fe82, 
+    0x463b220e, 0x1d2d4621, 0xf01f4628, 0x2206fe7a, 0x21404633, 0xf01f4628, 0x4621fe74, 0x220e4c0a, 
+    0x1d24463b, 0xf01f4620, 0x4633fe6c, 0xe8bd4620, 0x220641f0, 0xf01f2140, 0x0000be64, 0xf203c188, 
+    0xf203c988, 0xf203d188, 0xf203d988, 0xf203c600, 0xf203ce00, 0xf203d600, 0xf203de00, 0x5fffe92d, 
+    0x49f7460e, 0x0900f04f, 0x46cb2805, 0x464c464d, 0x46c87008, 0x464f49f3, 0x700e46ca, 0x9000f8cd, 
+    0x900cf8cd, 0x2803d00b, 0x2805d015, 0x2804d013, 0x2802d011, 0xb380d044, 0xd0412801, 0x48eae047, 
+    0x28017800, 0x48e9d107, 0x21102204, 0xfe37f01f, 0x48e7b908, 0x2e017806, 0x2e02d00a, 0x2e03d00c, 
+    0x2e04d00d, 0x2e05d012, 0x2e06d018, 0xe02ed01f, 0x95002501, 0xe02a2402, 0x0b01f04f, 0xf04fe7f8, 
+    0xf8cd0901, 0x27039000, 0xe00d46c8, 0x0b01f04f, 0x465c465d, 0x465f46d8, 0xe011e006, 0x0901f04f, 
+    0x464d2702, 0x46c8464c, 0x0a01f04f, 0x2501e00f, 0x0902f04f, 0x46a8462c, 0x46aa464f, 0xe0069503, 
+    0x0901f04f, 0x464d46cb, 0x46c8464c, 0x4623464f, 0x4659462a, 0xe9cd4648, 0xf7ff8701, 0x9903fe81, 
+    0x4650b004, 0x5ff0e8bd, 0xe92de737, 0x250147f0, 0x0401ea25, 0x28014395, 0xf8dfd170, 0x2b0082f8, 
+    0x4ebdd04a, 0xd0522b01, 0x2b024fbc, 0xf8dfd05a, 0x2b0392f0, 0x2205d031, 0x21204623, 0xf01f4640, 
+    0x2206fdc0, 0x2140462b, 0xf01f4640, 0xf44ffdba, 0x21003800, 0xf7fb4640, 0x2205fc8f, 0x21204623, 
+    0xf01f4630, 0x2206fdae, 0x2140462b, 0xf01f4630, 0x2100fda8, 0xf7fb4640, 0x2205fc7f, 0x21204623, 
+    0xf01f4638, 0x2206fd9e, 0x2140462b, 0xf01f4638, 0x2100fd98, 0xf7fb4640, 0x2205fc6f, 0x21204623, 
+    0x4648464c, 0xfd8df01f, 0x462b2206, 0x46202140, 0x47f0e8bd, 0xbd85f01f, 0x46232205, 0x46402120, 
+    0xfd7ff01f, 0x462b2206, 0x46402140, 0x2205e7f0, 0x21204623, 0xf01f4630, 0x2206fd74, 0x2140462b, 
+    0xe7e54630, 0x46232205, 0x46382120, 0xfd69f01f, 0x462b2206, 0x46382140, 0xe7ffe7da, 0x87f0e8bd, 
+    0x4604b510, 0x48834603, 0x21032200, 0xf01f1c80, 0x4881fd58, 0x21032200, 0x1c804623, 0xfd51f01f, 
+    0x2200487e, 0x46232103, 0xf01f1c80, 0x487cfd4a, 0x21032200, 0xe8bd4623, 0x1c804010, 0xbd41f01f, 
+    0x46032208, 0x0154b570, 0x48764605, 0xf01f4621, 0x4875fd38, 0x462b2208, 0xf01f4621, 0x4873fd32, 
+    0x462b2208, 0xf01f4621, 0x462bfd2c, 0xe8bd4621, 0x486f4070, 0xf01f2208, 0xb510bd24, 0x4604b283, 
+    0x22024864, 0x387e2104, 0xfd1bf01f, 0xb2a34862, 0x21042202, 0xf01f387e, 0x4860fd14, 0x2202b2a3, 
+    0x387e2104, 0xfd0df01f, 0xb2a3485d, 0x21042202, 0x4010e8bd, 0xf01f387e, 0xe92dbd04, 0x4c5941f0, 
+    0x22062300, 0x3c424607, 0x46202140, 0xfcf9f01f, 0x23004d55, 0x3d422206, 0x46282140, 0xfcf1f01f, 
+    0x23004e52, 0x3e422206, 0x46302140, 0xfce9f01f, 0x813cf8df, 0x22062300, 0x0842f1a8, 0x46402140, 
+    0xfcdff01f, 0x463b2207, 0x46202180, 0xfcd9f01f, 0x463b2207, 0x46282180, 0xfcd3f01f, 0x463b2207, 
+    0x46302180, 0xfccdf01f, 0x463b2207, 0x46402180, 0xfcc7f01f, 0x46202208, 0x01572300, 0xf01f4639, 
+    0x2301fcc0, 0x22084639, 0xf01f4620, 0x2300fcba, 0x22084639, 0xf01f4628, 0x2301fcb4, 0x22084639, 
+    0xf01f4628, 0x2300fcae, 0x22084639, 0xf01f4630, 0x2301fca8, 0x22084639, 0xf01f4630, 0x2300fca2, 
+    0x22084639, 0xf01f4640, 0x4639fc9c, 0xe8bd4640, 0x230141f0, 0xf01f2208, 0xe92dbc94, 0x4d2547f0, 
+    0x4f214e20, 0x9084f8df, 0xf8df361c, 0x371ca084, 0xf1097828, 0xf10a091c, 0xb1a80a1c, 0xb1f07868, 
+    0xb3c878a8, 0xf01f4650, 0xf000fc5f, 0x28060006, 0xf04fd068, 0x46500800, 0xfc56f01f, 0x0005f000, 
+    0xd02d2805, 0xe02c2400, 0xf01f4630, 0xf000fc4d, 0x28060006, 0xf04fd021, 0x46300800, 0xe035e7ec, 
+    0x0004235c, 0x0004235d, 0x0004230e, 0xf38f007c, 0x00042351, 0xf203c18a, 0xf203c98a, 0xf203d18a, 
+    0xf203d98a, 0xf203c642, 0xf203ce42, 0xf203d642, 0xf203de42, 0x00042598, 0xf04fe026, 0xe7dc0801, 
+    0x78282401, 0x0408ea44, 0xd02e2801, 0x28017868, 0x78a8d038, 0xd0472801, 0x46504656, 0xfc14f01f, 
+    0x0006f000, 0xd0422806, 0xe0202500, 0xf01f4638, 0xf000fc0b, 0x28060006, 0xf04fd003, 0x46380800, 
+    0xf04fe7aa, 0xe7fa0801, 0xf01f4648, 0xf000fbfd, 0x28060006, 0xf04fd003, 0x46480800, 0xf04fe79c, 
+    0xe7fa0801, 0x0801f04f, 0x4630e795, 0x4630e7d6, 0x2001e011, 0x2000e000, 0x44204328, 0xdb182802, 
+    0xe69b2001, 0xf01f4638, 0xf000fbdf, 0x28060006, 0x2500d008, 0xf01f4638, 0xf000fbd7, 0x28050005, 
+    0xe7e6d1e9, 0xe7f52501, 0x4648464e, 0x2501e7b6, 0x2000e7dd, 0xb510e682, 0x46042207, 0x46032180, 
+    0xf01f4823, 0x4823fbde, 0x21802207, 0xf01f4623, 0x4821fbd8, 0x21802207, 0xf01f4623, 0x2207fbd2, 
+    0xe8bd4623, 0x481d4010, 0xf01f2180, 0xb570bbca, 0x460d2204, 0x46042110, 0x48194603, 0xfbc1f01f, 
+    0x22044818, 0x46232110, 0xfbbbf01f, 0x22044816, 0x46232110, 0xfbb5f01f, 0x22044814, 0x46232110, 
+    0xfbaff01f, 0x22044c12, 0x462b2130, 0xf01f4620, 0x2206fba8, 0x21c0462b, 0xf01f4620, 0x220afba2, 
+    0x1ca0462b, 0x4100f640, 0x4070e8bd, 0xbb99f01f, 0xf203c186, 0xf203c986, 0xf203d186, 0xf203d986, 
+    0xf203c622, 0xf203ce22, 0xf203d622, 0xf203de22, 0xf203e800, 0x5ff0e92d, 0x20004683, 0xf8c3f7ff, 
+    0x23034cff, 0x21702204, 0xf01f4620, 0x4dfdfb7a, 0x22042303, 0x46282170, 0xfb73f01f, 0x23034efa, 
+    0x21702204, 0xf01f4630, 0x4ff8fb6c, 0x22042303, 0x46382170, 0xfb65f01f, 0x46202304, 0x210e2201, 
+    0xfb5ff01f, 0x46282304, 0x210e2201, 0xfb59f01f, 0x46302304, 0x210e2201, 0xfb53f01f, 0x46382304, 
+    0x210e2201, 0xfb4df01f, 0x23014de9, 0x21402206, 0xf01f4628, 0x2208fb46, 0x23004628, 0x46210154, 
+    0xfb3ff01f, 0x23004de3, 0x00612209, 0xf01f4628, 0x2300fb38, 0x22084621, 0xf01f4628, 0x2300fb32, 
+    0x22074628, 0xf01f2180, 0x2300fb2c, 0x22064628, 0xf01f2140, 0x4ed8fb26, 0x22072300, 0x46302180, 
+    0xfb1ff01f, 0x46212300, 0x46302208, 0xfb19f01f, 0x46302301, 0x21402206, 0xfb13f01f, 0x46302301, 
+    0x21082203, 0xfb0df01f, 0x46302300, 0x21022201, 0xfb07f01f, 0x23014ec6, 0x46192200, 0x46303e0e, 
+    0xfafff01f, 0x9308f8df, 0x220f2301, 0xf1a903df, 0x46390902, 0xf01f4648, 0xf8dffaf4, 0x2301a300, 
+    0x46212208, 0xf01f4650, 0x2300faec, 0x22034650, 0xf01f2108, 0x2301fae6, 0x22034630, 0xf01f2108, 
+    0xf1a9fae0, 0x210f0804, 0xf01f4640, 0x2002fac0, 0xfd76f7ff, 0xf7fe2001, 0x2301ffb9, 0x22054628, 
+    0xf01f2120, 0x2301face, 0x22044628, 0xf01f2110, 0x2301fac8, 0x22034628, 0xf01f2108, 0x2301fac2, 
+    0x22024628, 0xf01f2104, 0x2100fabc, 0xf01f4640, 0x2300fa9e, 0x22034630, 0xf01f2108, 0x2300fab2, 
+    0x220f4639, 0xf01f4648, 0x2300faac, 0x21014630, 0xf01f461a, 0x2301faa6, 0x22074628, 0xf01f2180, 
+    0x2301faa0, 0x22064628, 0xf01f2140, 0x2300fa9a, 0x22084621, 0xf01f4650, 0x4891fa94, 0x46587801, 
+    0xfc3cf7ff, 0xf7ff2000, 0x488cfd4b, 0x5468f64a, 0x30084621, 0xfa6bf01f, 0x46214888, 0xf01f300a, 
+    0x4886fa66, 0x300c2100, 0xfa61f01f, 0xf00c2004, 0x2100fea4, 0xf00d2001, 0x4650fcb9, 0x5ff0e8bd, 
+    0x22032301, 0xf01f2108, 0xe92dba6c, 0x46045ff0, 0xf7fe2000, 0x487bffa8, 0x07c07800, 0x2c04d015, 
+    0x2c05d009, 0x2c03d00a, 0x4877d00c, 0xf4418801, 0x80014180, 0x2200e032, 0xe0014611, 0x21052200, 
+    0xe0202000, 0x21072200, 0x2c04e7fa, 0x2c05d005, 0x2200d003, 0x46112006, 0x486ce015, 0x28017800, 
+    0x2c05d101, 0x2100d00c, 0x4608220b, 0xf8a0f7ff, 0x68004867, 0xd3112823, 0x78004866, 0xe00db130, 
+    0x2107220b, 0xf7ff2005, 0xe007f893, 0x88004862, 0x7feaf5b0, 0xf5b0d07d, 0xd0fb7ffa, 0x23004d54, 
+    0x21402206, 0xf01f4628, 0xf240fa1c, 0x46281b00, 0x46592301, 0xf01f2208, 0xf8dffa14, 0xf240a138, 
+    0x23002500, 0x22094629, 0xf01f4650, 0x2300fa0a, 0x22084659, 0xf01f4650, 0x2300fa04, 0x22074650, 
+    0xf01f2180, 0x2300f9fe, 0x22064650, 0xf01f2140, 0x4e41f9f8, 0x22072300, 0x46302180, 0xf9f1f01f, 
+    0x46592300, 0x46302208, 0xf9ebf01f, 0x46302300, 0x21402206, 0xf9e5f01f, 0x46302300, 0x21082203, 
+    0xf9dff01f, 0x46302300, 0x21022201, 0xf9d9f01f, 0x23014e2f, 0x46192200, 0x46303e0e, 0xf9d1f01f, 
+    0x90acf8df, 0x0800f248, 0x46412301, 0x0902f1a9, 0x4648220f, 0xf9c5f01f, 0x0704f1a9, 0x4638210f, 
+    0xf9a5f01f, 0xf7ff2000, 0x2000fc5b, 0xfe9ef7fe, 0x46502300, 0x21202205, 0xf9b3f01f, 0x46502300, 
+    0x21102204, 0xf9adf01f, 0x46502300, 0x21082203, 0xe04ce000, 0xf9a5f01f, 0x46502300, 0x21042202, 
+    0xf99ff01f, 0x46382100, 0xf981f01f, 0x46412300, 0x4648220f, 0xf995f01f, 0x46302300, 0x461a2101, 
+    0xf98ff01f, 0x46292301, 0x46502209, 0xf989f01f, 0x46592301, 0x46502208, 0xf983f01f, 0xe01d4808, 
+    0xf203c602, 0xf203ce02, 0xf203d602, 0xf203de02, 0xf23c830e, 0xf23c804a, 0xf2034228, 0xf2039000, 
+    0x00042350, 0x000402b4, 0x000402b6, 0x0004230e, 0x00040240, 0x000425f9, 0x00042576, 0x46207801, 
+    0xfb0cf7ff, 0x5ff0e8bd, 0xf7ff2001, 0x220bbc19, 0x20012106, 0xe92de727, 0x23004ff8, 0x22044604, 
+    0x4ffe21f0, 0xf01f4638, 0xf640f94c, 0x46387a00, 0x46512300, 0xf01f2208, 0x2c03f944, 0x2c04d028, 
+    0x2c05d026, 0x2500d024, 0xd0442c02, 0xd0422c01, 0xd0772c06, 0xd0762c07, 0xd0752c08, 0xf7fe2000, 
+    0xb2e0ff1e, 0xfda6f7ff, 0x23042101, 0x22004608, 0xfb4bf7ff, 0x780048ea, 0xd07d2801, 0x200a2104, 
+    0xfb54f010, 0x95002300, 0x46192201, 0xe1164618, 0xf7ffb2e0, 0x4de3feaa, 0x20307828, 0xfefff7fe, 
+    0x20062100, 0xfb42f010, 0x23042201, 0x46104611, 0xfb2bf7ff, 0xf7ff2001, 0x2c05fd1e, 0x7828d102, 
+    0xd0052801, 0x46082101, 0x4ff8e8bd, 0xbd2ff7ff, 0x46082100, 0xf8dfe7f8, 0x22018350, 0x46402102, 
+    0xf8fdf01f, 0xf8df4ed1, 0xb1089348, 0xd1042c02, 0xf7ffb2e0, 0x2c02fd5f, 0x8830d002, 0xe02eb348, 
+    0xb9288830, 0x46482200, 0xf01f210f, 0xb1e0f8e8, 0x22042308, 0x463821f0, 0xf8d3f01f, 0x20022100, 
+    0xfb04f010, 0x95002300, 0x46182202, 0xf0102101, 0x48c0fa43, 0x20027801, 0xfa70f7ff, 0xf7fe2010, 
+    0xe01dfeae, 0xe060e053, 0x2307e07c, 0x22084651, 0x2200e7e1, 0x210f4648, 0xf8c1f01f, 0x2100b318, 
+    0xf010200a, 0x2300fae3, 0x22019500, 0x46104619, 0xfa22f010, 0xe0002102, 0x2001e092, 0xfa4ef7ff, 
+    0x48ad2300, 0x461a2101, 0xf89bf01f, 0xf7fe2001, 0x2201fcad, 0x21024645, 0xf01f4640, 0xb128f8a0, 
+    0xd0032c02, 0x2100e008, 0xe7da2005, 0x23042201, 0x46104611, 0xfaa9f7ff, 0x46282201, 0xf01f2102, 
+    0x2801f88e, 0x2202d006, 0x21044628, 0xf887f01f, 0xd1022801, 0xf7ff2000, 0x2202fc8e, 0x21044628, 
+    0xf87df01f, 0xd1792801, 0x21012200, 0x2200e06e, 0x46112304, 0xf7ff2001, 0x2004fa88, 0xfbeaf7fe, 
+    0x4ff8e8bd, 0xf7fe2001, 0x4c89bd9e, 0x22072301, 0x21803cb8, 0xf01f4620, 0x2301f854, 0x22094620, 
+    0xf01f0259, 0x2208f84e, 0x23014620, 0xf01f0151, 0x2300f848, 0x22044620, 0xf01f2110, 0x2304f842, 
+    0xe01a2200, 0x78204c7d, 0xfdcff7ff, 0xf7fe2030, 0x2100fe26, 0xf0102006, 0x4879fa69, 0xb19b7803, 
+    0x21009500, 0x20007822, 0xf9a6f010, 0xf04f4875, 0x78000304, 0xd0102803, 0x21012201, 0x2001b001, 
+    0x4ff0e8bd, 0xba41f7ff, 0x462b486f, 0x95007800, 0xd1e62801, 0x21017822, 0x2200e7e5, 0xe7ed4611, 
+    0x46082100, 0xfa42f010, 0xf04f4868, 0xf04f0201, 0x46110300, 0x95007800, 0xd00c2803, 0xf0102001, 
+    0x2000f97b, 0xfc17f7ff, 0x46112200, 0x4ff8e8bd, 0xf7fe2000, 0x2002bd87, 0xe7ffe7f1, 0x8ff8e8bd, 
+    0xf04f2109, 0xf44f422b, 0xb5102000, 0xfe69f7f3, 0xf2402001, 0xf7f311f4, 0x4855fe16, 0x20017801, 
+    0xfe00f7f3, 0x20014953, 0xfdfcf7f3, 0x23004852, 0xf2402208, 0xf01e3100, 0x4950ffd4, 0x4a512000, 
+    0x808880c8, 0x80088048, 0x494f484d, 0x484b7803, 0xffe8f7fc, 0xf44f2172, 0xf7f30080, 0x2000fe1c, 
+    0xfc10f7fe, 0x23004835, 0x461a210f, 0xf01e3828, 0x2000ffb8, 0xfbe6f7fe, 0xf7fe2004, 0x2001fb7e, 
+    0xfbc4f7fe, 0x20402100, 0xfe86f7fa, 0x4010e8bd, 0xf7fe2000, 0x482ebbbb, 0x31b5f64b, 0x3848b5f8, 
+    0xff85f01e, 0x48392301, 0x039c220e, 0xf01e4621, 0x4827ff98, 0x22002301, 0x38b84619, 0xff91f01e, 
+    0x23042200, 0x20014611, 0xf9aff7ff, 0xff98f7ff, 0x607ff46f, 0x0395f647, 0x0202f247, 0x0102f640, 
+    0xf2439000, 0xf7fe1045, 0x4829fa1d, 0xf01e2100, 0x481aff5e, 0x78004a17, 0xf7ff7811, 0x2003f91f, 
+    0xfc91f7fe, 0xf00d2007, 0x2001f9e8, 0xfcc9f7fe, 0xfb58f00c, 0xf7fe2001, 0x2001ff07, 0xfa3df7ff, 
+    0xf7ff2001, 0x2001fb78, 0xff38f7fe, 0xf7fe2000, 0x2001ff77, 0xff74f7fe, 0xe02b2000, 0xf203e82c, 
+    0x0004255c, 0x0004230e, 0xf38f007c, 0x00042578, 0xf23c8102, 0x00042350, 0xf20305cc, 0x00040292, 
+    0x000425f9, 0x00040284, 0x00042556, 0x0004255d, 0x0004257a, 0xdcba01f5, 0xf2035022, 0x000425b0, 
+    0x0004232e, 0x00042598, 0x000425c6, 0xf23c830c, 0xf2034224, 0xff44f7fe, 0xf7fe2000, 0x00e6feff, 
+    0x15f4f240, 0x46304629, 0xfd4df7f3, 0x7100f241, 0xf7f34630, 0x4f39fd37, 0x46394630, 0xfd32f7f3, 
+    0xf7ff2003, 0x2005fdb8, 0xfd52f7fe, 0xf7fe2000, 0x2001ff85, 0xff8df00d, 0xf7ff2000, 0x2003fdac, 
+    0xfd46f7fe, 0xf7fe2007, 0x4629ff79, 0xf7f34630, 0xf241fd2a, 0x46307101, 0xfd14f7f3, 0x46304639, 
+    0xfd10f7f3, 0x23004826, 0x4621220e, 0xfee9f01e, 0x4823b001, 0x23001121, 0x40f0e8bd, 0x1c80220a, 
+    0xbedff01e, 0x4c1fb570, 0x21012300, 0x4620461a, 0xfed7f01e, 0xf01e1fa0, 0x1ea5feb7, 0x46282302, 
+    0x21072200, 0xfecdf01e, 0x46282302, 0x21702204, 0xfec7f01e, 0xf2402302, 0x22087100, 0xf01e4628, 
+    0x2302fec0, 0x0100f247, 0x4628220c, 0xfeb9f01e, 0x1f202100, 0xfe9bf01e, 0x46202301, 0x46192200, 
+    0xfeaff01e, 0xf7fe2001, 0x2100fac1, 0xf7fa2040, 0xe8bdfd83, 0x20004070, 0xbab8f7fe, 0xdcba01f5, 
+    0xf203e80a, 0xf20305cc, 0x41f0e92d, 0x461d4c4f, 0x4616b283, 0x460f2206, 0x462021c0, 0xfe91f01e, 
+    0x4620b2bb, 0x21302204, 0xfe8bf01e, 0x4620b2b3, 0x210c2202, 0xfe85f01e, 0x4620b2ab, 0x41f0e8bd, 
+    0x21032200, 0xbe7df01e, 0x47f0e92d, 0x46144699, 0x460e2301, 0x8020f8dd, 0x46072102, 0x461a483c, 
+    0xfe6ff01e, 0xf2412100, 0xf7fa0000, 0x4d39fd45, 0x220a2301, 0x46280299, 0xfe63f01e, 0x463b2204, 
+    0x11f0f240, 0xf01e4628, 0x2201fe5c, 0x21024633, 0xf01e4628, 0x1d2ffe56, 0x0100f640, 0x0600f24c, 
+    0x2c01b124, 0x2c02d004, 0xe00cd002, 0xe0002300, 0x46282301, 0xf01e220b, 0x2300fe44, 0x220e4631, 
+    0xf01e4638, 0xf1b8fe3e, 0xd0050f00, 0x46312301, 0x4638220e, 0xfe35f01e, 0x464b220f, 0x0100f248, 
+    0xf01e4628, 0x4628fe2e, 0x47f0e8bd, 0x22022301, 0xf01e2104, 0x4817be26, 0xb5102100, 0xf01e3016, 
+    0x4814fe06, 0x30182100, 0xfe01f01e, 0x21004811, 0xf01e3012, 0x480ffdfc, 0x30142100, 0xfdf7f01e, 
+    0x2100480c, 0xf01e301a, 0x480afdf2, 0x301c2100, 0xfdedf01e, 0x21004807, 0xf01e301e, 0x4805fde8, 
+    0xe8bd2100, 0x30204010, 0xbde1f01e, 0xf2030484, 0xf23c8310, 0xf2036100, 0x2801b158, 0x2802d00f, 
+    0x2803d013, 0x2301d117, 0x210248a3, 0xf01e461a, 0x48a1bde8, 0x21022301, 0x3860461a, 0x489ee7f7, 
+    0x21022301, 0x3840461a, 0x489be7f1, 0x21022301, 0x3820461a, 0x4770e7eb, 0x4c97b510, 0x22002301, 
+    0x3ce04619, 0xf01e4620, 0x2301fdcc, 0x21024620, 0xf01e461a, 0x2301fdc6, 0x22024620, 0xf01e2104, 
+    0x2301fdc0, 0x22034620, 0x4010e8bd, 0xf01e2108, 0xb283bdb8, 0x22064888, 0x38de21c0, 0xbdb1f01e, 
+    0x2801b158, 0x2802d00f, 0x2803d013, 0x2301d117, 0x22004881, 0xf01e4619, 0x487fbda4, 0x22002301, 
+    0x38604619, 0x487ce7f7, 0x22002301, 0x38404619, 0x4879e7f1, 0x22002301, 0x38204619, 0x4770e7eb, 
+    0xf240b570, 0x461436ff, 0xb1a81c75, 0xd0192801, 0xd01d2802, 0xd1212803, 0x4631b28b, 0x22004e6e, 
+    0x4630360e, 0xfd7df01e, 0x4629b2a3, 0xe8bd4630, 0x220a4070, 0xbd75f01e, 0x4631b28b, 0x22004e66, 
+    0xe7ee3e52, 0x4631b28b, 0x22004e63, 0xe7e83e32, 0x4631b28b, 0x22004e60, 0xe7e23e12, 0xb510bd70, 
+    0x4604b283, 0x2200485c, 0x38802103, 0xfd59f01e, 0xe8bd4620, 0xf01c4010, 0xb283b9ce, 0xb5104856, 
+    0x460c2200, 0xf64738d8, 0xf01e71ff, 0x4852fd4a, 0xe8bdb2a1, 0x38d64010, 0xbd29f01e, 0x4d4eb570, 
+    0x220f2301, 0x3de003dc, 0x46284621, 0xfd39f01e, 0x46284621, 0x4070e8bd, 0x220f2300, 0xbd31f01e, 
+    0x41f0e92d, 0x4603461f, 0x46144843, 0x22099e06, 0x460d387c, 0x2100f240, 0xfd23f01e, 0x2207483e, 
+    0x462b2180, 0xf01e385e, 0x483bfd1c, 0x21802207, 0x383e4623, 0xfd15f01e, 0x22074837, 0x463b2180, 
+    0xf01e381e, 0x4633fd0e, 0xe8bd4833, 0x220741f0, 0x1c802180, 0xbd05f01e, 0xf64fb430, 0xb1680400, 
+    0xd0112801, 0xd0152802, 0xd1192803, 0x220b482a, 0x4621460b, 0xbc30300e, 0xbcf3f01e, 0x220b4826, 
+    0x4621460b, 0xe7f63852, 0x220b4823, 0x4621460b, 0xe7f03832, 0x220b4820, 0x4621460b, 0xe7ea3812, 
+    0x4770bc30, 0xb283b510, 0x481c4604, 0x21012200, 0xfcd7f01e, 0x481ab2a3, 0x21012200, 0xfcd1f01e, 
+    0x4818b2a3, 0x21012200, 0xfccbf01e, 0x4816b2a3, 0xe8bd2200, 0x21014010, 0xbcc3f01e, 0x2801b158, 
+    0x2802d00e, 0x2803d011, 0xb28bd114, 0x2201480e, 0xf01e2106, 0xb28bbcb6, 0x22014808, 0xe7f82106, 
+    0x4807b28b, 0x21062201, 0xb28be7f3, 0x22014805, 0xe7ee2106, 0x00004770, 0xf20308e0, 0xf203c604, 
+    0xf203ce04, 0xf203d604, 0xf203de04, 0x2100b51c, 0x91019100, 0x1010f82d, 0x1000f8bd, 0xf01e48f7, 
+    0x48f6fc76, 0x1002f8bd, 0xf01e3020, 0x48f3fc70, 0x1004f8bd, 0xf01e3040, 0x48f0fc6a, 0x1006f8bd, 
+    0xf01e3060, 0xbd1cfc64, 0x220448ed, 0x4cebb510, 0xf9902130, 0x3c740000, 0x4620b283, 0xfc71f01e, 
+    0x46202304, 0x210f2200, 0xfc6bf01e, 0x46202301, 0x21402206, 0xfc65f01e, 0xf01e1ca0, 0x4604fc45, 
+    0x387048de, 0xfc40f01e, 0x4000eb04, 0xbd101040, 0xb50848dc, 0xf2447801, 0xf7fa0000, 0x48d7fb2d, 
+    0x01c9f640, 0xf01e387e, 0x48d4fc32, 0x1101f241, 0xf01e387c, 0x2000fc2c, 0xfe92f7ff, 0xf7ff2001, 
+    0x2002fe8f, 0xfe8cf7ff, 0xf7ff2003, 0x48cbfe89, 0x22062301, 0xf01e2140, 0x48c8fc34, 0x22062301, 
+    0x30202140, 0xfc2df01e, 0x230148c4, 0x21402206, 0xf01e3040, 0x48c1fc26, 0x22062301, 0x30602140, 
+    0xfc1ff01e, 0x90002001, 0x46024603, 0xf7ff4601, 0xbd08fee7, 0xd0102804, 0x40822201, 0x000ff082, 
+    0x2901b200, 0xea40d00b, 0xb2001000, 0x48b3b283, 0x21ff2200, 0xf01e3882, 0x20ffbc04, 0x2102e7f6, 
+    0x1000eb01, 0x000ff040, 0xb570e7ef, 0x3400f44f, 0x0102f640, 0xf7f34620, 0x48a8fa26, 0xf01e1d00, 
+    0x4605fbd3, 0x1c8048a5, 0xfbcef01e, 0x4100eb05, 0xf7f34620, 0x48a1fa07, 0xf01e3024, 0x4605fbc5, 
+    0x3022489e, 0xfbc0f01e, 0x4100eb05, 0xf7f34620, 0x489af9f9, 0xf01e3044, 0x4605fbb7, 0x30424897, 
+    0xfbb2f01e, 0x4100eb05, 0xf7f34620, 0x4893f9eb, 0xf01e3064, 0x4605fba9, 0x30624890, 0xfba4f01e, 
+    0x4100eb05, 0xf7f34620, 0x488df9dd, 0xf9902100, 0xe8bd0000, 0xe79d4070, 0x41f0e92d, 0x4a874d8a, 
+    0x1840eb02, 0x28037828, 0x4888d003, 0x07c07800, 0x2900d00b, 0xf04fdb02, 0xe0010631, 0x0611f04f, 
+    0xf1c1da01, 0xb20c0100, 0x2900e007, 0x2631db01, 0x2611e000, 0xd500104c, 0x46404264, 0x21402206, 
+    0xfb9df01e, 0xf995b247, 0x28040000, 0x2805d002, 0xe003d002, 0xe00000a0, 0xb2040060, 0x21004640, 
+    0xfb65f01e, 0xe0052500, 0x46404631, 0xfb5ff01e, 0xb22d1c6d, 0xdbf742a5, 0x4640b2bb, 0x41f0e8bd, 
+    0x21402206, 0xbb6df01e, 0x4d64b570, 0x1cac3d7e, 0x2801b120, 0x2802d00a, 0xe02ad10f, 0x46282306, 
+    0x21f02204, 0xfb5df01e, 0xe0012303, 0xe0212307, 0x46202204, 0xf01e2170, 0x2305fb54, 0x22044628, 
+    0xf01e21f0, 0x2302fb4e, 0x22044620, 0xf01e2170, 0x2305fb48, 0x0100f24f, 0x4628220c, 0xfb41f01e, 
+    0xf2474620, 0xe8bd0100, 0x23024070, 0xf01e220c, 0x2308bb38, 0x22044628, 0xf01e21f0, 0x2302fb32, 
+    0x4601e7d6, 0xb5704845, 0xf242387e, 0x1c854424, 0x3613f241, 0xf2472908, 0xd22b4287, 0xf001e8df, 
+    0x160a0704, 0x1f181610, 0x2163f245, 0xf247e00a, 0xe0014185, 0x7187f247, 0xfaf9f01e, 0xe0144631, 
+    0x418cf240, 0xfaf3f01e, 0xe00e4621, 0xe7f34611, 0x61a7f249, 0xfaebf01e, 0x2102f240, 0xf64be005, 
+    0xf01e01c9, 0xf240fae4, 0x46281101, 0x4070e8bd, 0xbaddf01e, 0xb570bd70, 0x22004c28, 0x4605210f, 
+    0x46203c7e, 0xfafbf01e, 0xb2401b40, 0xdd01280f, 0xe002200f, 0xda002800, 0xb2832000, 0xe8bd4620, 
+    0x22004070, 0xf01e210f, 0xb430badc, 0xb1419902, 0x2408f245, 0x1aa42100, 0xda094199, 0x0109f06f, 
+    0x2b00e03b, 0x2101da01, 0xf04fe037, 0xe03431ff, 0x0100f244, 0xf1731a51, 0xdb020100, 0x0103f06f, 
+    0xf242e02b, 0x1b140400, 0x0400f173, 0x0101f06f, 0x2b00da23, 0x030cda21, 0x1aa41049, 0xdb044199, 
+    0x13a14c0b, 0x41991aa4, 0x2102da01, 0x4c09e015, 0x1aa213e1, 0xda0f4199, 0xe00e2104, 0xf2030882, 
+    0x00040298, 0x00040293, 0x00040292, 0x000402b4, 0xffffc000, 0xffffadf8, 0xbc30210a, 0xf7ffb2c9, 
+    0x4858bd8b, 0x22082307, 0x7100f640, 0xf01eb510, 0x4854fa88, 0x22002301, 0x307c4619, 0xfa81f01e, 
+    0x23014850, 0x46192200, 0xf01e309c, 0x484dfa7a, 0x22002301, 0x30bc4619, 0xfa73f01e, 0x23014849, 
+    0x46192200, 0x4010e8bd, 0xf01e30dc, 0xb570ba6a, 0xf6404605, 0xf44f0103, 0xf7f33000, 0xf7fff894, 
+    0x4c41fc8b, 0x46082100, 0x2000f994, 0xfb3ff7fc, 0xfddaf7ff, 0x7025b201, 0x46101402, 0xfcfdf7ff, 
+    0x0000f994, 0xfc58f7ff, 0x0000f994, 0xfc98f7ff, 0x0000f994, 0xfce3f7ff, 0x20012100, 0xfd73f7fc, 
+    0x2000f994, 0x200c2100, 0xfadbf7fc, 0xf9942101, 0x46082000, 0xfb1bf7fc, 0x4070e8bd, 0xe92de635, 
+    0x46824ff8, 0xf8df4829, 0x250090a8, 0x462a46e8, 0xf8906800, 0xf88d1052, 0xf8901000, 0xf88d1054, 
+    0xf8901001, 0xf88d0056, 0xf9990002, 0xeb0d1000, 0x21ff0001, 0x3c03f810, 0x3062481a, 0xfa11f01e, 
+    0x26102704, 0x0f00f1ba, 0x2400d023, 0xfd8cf7ff, 0x1c644138, 0x42b4b2e4, 0xd3f74405, 0x3080f44f, 
+    0xf7f34629, 0xf999f81f, 0x12682000, 0x0102eb08, 0xf8112200, 0x43481c03, 0x7809490e, 0x0115f1c1, 
+    0xf2404108, 0xf3c031ff, 0x48060309, 0xf01e3064, 0x4804f9e8, 0x21042202, 0x305c4653, 0xf9e1f01e, 
+    0x8ff8e8bd, 0xf2030804, 0x00040298, 0x00042618, 0x00040292, 0x00040293, 0x4cbab510, 0x4620b281, 
+    0xf9b5f01e, 0x46202100, 0xf9b1f01e, 0xf64f4cb5, 0x3c1071ff, 0xf01e4620, 0x4620f9aa, 0x4010e8bd, 
+    0xf01e2100, 0xf04fb9a4, 0xb51030ff, 0xffe4f7ff, 0xf01e48ad, 0xe8bdf993, 0x20044010, 0xb957f7fa, 
+    0x9c02b510, 0x70427001, 0x70c47083, 0xb570bd10, 0x24004da6, 0x0600f647, 0x4631230f, 0xeb05220b, 
+    0xf01e0044, 0x1c64f99e, 0xdbf52c04, 0xb570bd70, 0x24004d9e, 0x0600f647, 0x46312300, 0xeb05220b, 
+    0xf01e0044, 0x1c64f98e, 0xdbf52c04, 0xe92dbd70, 0x4f9741f0, 0x46052400, 0x1600f240, 0x0804f107, 
+    0x3044eb06, 0x4638b281, 0xf961f01e, 0xf01e4640, 0xf825f95b, 0x1c640014, 0xdbf12c04, 0x81f0e8bd, 
+    0x41f0e92d, 0x24004e89, 0x070ef06f, 0x36104605, 0x0044eb06, 0xf948f01e, 0xf99ef020, 0xf021463a, 
+    0xeb05f812, 0x1c6402c4, 0xe9c22c04, 0xdbef0100, 0xb510e7e4, 0x46204c7f, 0xf936f01e, 0xf01e4620, 
+    0xf010f933, 0xd0000020, 0xbd102001, 0x220d487a, 0x0100f242, 0xf01eb510, 0x2800f952, 0x2001d000, 
+    0xe92dbd10, 0xf24441f0, 0x460c0600, 0x4607220e, 0x48724603, 0xf01e4631, 0x486cf934, 0x387e2100, 
+    0xf915f01e, 0x4d6d486d, 0x3d443850, 0xd00e2c02, 0xd0132c01, 0x22002300, 0xf01e2101, 0x463bf922, 
+    0x46284631, 0x41f0e8bd, 0xf01e220e, 0x2200b91a, 0x2101463b, 0xf915f01e, 0xe7f12300, 0xe7ea463b, 
+    0x41f0e92d, 0x461f4c5d, 0x460e4615, 0x46033422, 0x46202200, 0xf01e2103, 0x2202f904, 0x210c4633, 
+    0xf01e4620, 0x2204f8fe, 0x2130462b, 0xf01e4620, 0x2206f8f8, 0x21c0463b, 0xf01e4620, 0x4620f8f2, 
+    0x41f0e8bd, 0x23012208, 0xf01e0151, 0xb570b8ea, 0x22004d4a, 0x35222103, 0xf01e4628, 0x2202f8f0, 
+    0x210c4604, 0xf01e4628, 0xea44f8ea, 0x46280480, 0x21302204, 0xf8e3f01e, 0x1400ea44, 0x22064628, 
+    0xf01e21c0, 0xea44f8dc, 0xb2801080, 0xb570bd70, 0x4604460d, 0x4611483a, 0xf8a9f01e, 0x46294838, 
+    0xf01e1e80, 0x4836f8a4, 0xe8bd4621, 0x1f004070, 0xb89df01e, 0x41f0e92d, 0x540ae9dd, 0x7608e9dd, 
+    0xec06e9dd, 0x8030f8dd, 0xf040b109, 0xb10a0002, 0x0001f040, 0xf040b10b, 0xf1be0008, 0xd0010f00, 
+    0x0004f040, 0x0f00f1bc, 0xf040d001, 0xb10e0010, 0x0020f040, 0xf040b10f, 0xb10d0040, 0x0080f040, 
+    0xf440b10c, 0xea5f7080, 0xd0010108, 0x7000f440, 0xb510e714, 0x28012403, 0x2803d002, 0xe018d00b, 
+    0x22024818, 0xf01e213c, 0xb2c0f88a, 0xd00d2806, 0xd00d2807, 0x4814e00d, 0x213c2202, 0xf87ff01e, 
+    0x2807b2c0, 0x2808d002, 0xe002d002, 0xe0002404, 0x46202405, 0x2200bd10, 0x480c4603, 0xf01e2107, 
+    0x0000b860, 0xf203902a, 0xf0001144, 0xf38f2200, 0xf38f2360, 0xf3cfffc2, 0xf38fffd4, 0xf38f2050, 
+    0xf38e0030, 0xf2020000, 0xf2060000, 0xf2070000, 0x220c2301, 0x0319b570, 0x46204cfe, 0xf841f01e, 
+    0x46202301, 0x21402206, 0xf83bf01e, 0x46202300, 0x21202205, 0xf835f01e, 0x46202300, 0x21102204, 
+    0xf82ff01e, 0x46202301, 0x21802207, 0xf829f01e, 0xf2442300, 0x220e0100, 0xf01e4620, 0x4cedf822, 
+    0x220a2300, 0x4100f240, 0x46203c10, 0xf819f01e, 0x46202208, 0x01512300, 0xf813f01e, 0xf2404de5, 
+    0x230014c0, 0x1dad4621, 0x46282206, 0xf809f01e, 0x46282306, 0x21382203, 0xf803f01e, 0x46282306, 
+    0x21072200, 0xfffdf01d, 0x46212306, 0x461a1cad, 0xf01d4628, 0x1faefff6, 0x46302302, 0x21072200, 
+    0xffeff01d, 0x46282300, 0x461a2107, 0xffe9f01d, 0x46212306, 0x4630461a, 0xffe3f01d, 0x4ccd4621, 
+    0x3c0c2306, 0x4620461a, 0xffdbf01d, 0xe8bd4620, 0x23064070, 0x21072200, 0xbfd3f01d, 0x43f8e92d, 
+    0x9314f8df, 0x49c52500, 0x27032601, 0x0802f04f, 0x0000f899, 0x7080f440, 0x0000f8a9, 0x29017809, 
+    0xf3c0d038, 0x91001181, 0x0103f000, 0x1301f3c0, 0x0281f3c0, 0xf7ff48ba, 0xf365fe03, 0xf3660407, 
+    0xf368240f, 0xf3674417, 0xf899641f, 0xb0010000, 0xf3c00782, 0x0f520381, 0xf102fa04, 0x005b1222, 
+    0xf3c0409a, 0x43111301, 0x005b1422, 0x1081f3c0, 0x4311409a, 0x00401622, 0x43f0e8bd, 0x43114082, 
+    0x0003f001, 0x1381f3c1, 0x1201f3c1, 0x0181f3c1, 0xbe76f7ff, 0x0103f000, 0xf3c09100, 0xf3c00381, 
+    0xf3c01201, 0x489e1181, 0xfdcaf7ff, 0x0407f367, 0x240ff368, 0x4417f366, 0x641ff365, 0xb538e7c5, 
+    0xd0042801, 0xb1282403, 0x88004893, 0xf7ffb138, 0xe01dff95, 0x94002302, 0x21002201, 0x488fe015, 
+    0x28017800, 0x2303d006, 0x21012202, 0xf7ff2000, 0xe7effe47, 0x22012300, 0x20032102, 0xfe40f7ff, 
+    0x90002000, 0x22022301, 0x48852103, 0xfd98f7ff, 0x4c834884, 0x1000f990, 0x70015c61, 0x3003f994, 
+    0x2002f994, 0x1001f994, 0x0000f994, 0xf89cf7ff, 0x3003f994, 0x2002f994, 0x1001f994, 0x0000f994, 
+    0xfe38f7fb, 0x3003f994, 0x2002f994, 0x1001f994, 0x0000f994, 0xffd5f7fc, 0x3003f994, 0x2002f994, 
+    0x1001f994, 0x0000f994, 0xfd26f010, 0xfe2ff7ff, 0x4038e8bd, 0x486c4601, 0xbef9f01d, 0x5ff0e92d, 
+    0x48694604, 0x31b8f64b, 0xf01d30a8, 0x4e67fef0, 0x220e2301, 0x46300399, 0xff03f01d, 0x23004d64, 
+    0x21042202, 0xf01d4628, 0x4862fefc, 0x22032301, 0xf01d2108, 0x4f5dfef6, 0x22022301, 0x21043760, 
+    0xf01d4638, 0x485cfeee, 0x0800f241, 0x1900f240, 0x28988800, 0x2888d015, 0x28a8d013, 0x28b8d011, 
+    0x2894d00f, 0x2884d01e, 0x28a4d01c, 0x28b4d01a, 0xb3b4d018, 0x46412301, 0x4628220c, 0xfed1f01d, 
+    0x2300e017, 0x220c4641, 0xf01d4628, 0x2300feca, 0x22084649, 0xf01d4628, 0xb314fec4, 0x22072301, 
+    0xe0152180, 0x46412300, 0x4628220c, 0xfeb9f01d, 0x2301b1bc, 0x22084649, 0xf01d4628, 0x2301feb2, 
+    0x22074628, 0xf01d2180, 0x2301feac, 0x21402206, 0xf01d4628, 0x2301fea6, 0x22054628, 0xf01d2120, 
+    0x4d33fea0, 0x220f2301, 0x03d93d20, 0xf01d4628, 0x2301fe98, 0x220c4644, 0x46284641, 0xfe91f01d, 
+    0x46282300, 0x21402206, 0xfe8bf01d, 0x46282300, 0x21202205, 0xfe85f01d, 0x23004828, 0x21402206, 
+    0xfe7ff01d, 0x4a00f240, 0x23004825, 0x220a4651, 0xfe77f01d, 0xf640481f, 0x23010b00, 0x220b4659, 
+    0xf01d3820, 0x2002fe6e, 0xfef9f7ff, 0x23004811, 0x21802207, 0xf01d382c, 0x481afe64, 0x20017801, 
+    0xfd1ff7ff, 0x804cf8df, 0x22082301, 0xf1a8464d, 0x4649083c, 0xf01d4640, 0x2301fe54, 0x22054640, 
+    0xf01d2120, 0x2301fe4e, 0x22044640, 0xf01d2110, 0xe019fe48, 0xf203902c, 0x000402c4, 0x00042324, 
+    0x00042598, 0x00040298, 0xf23c8012, 0xf38f0000, 0xf38e0040, 0xf38f2070, 0x00042576, 0xf203507c, 
+    0xf38fffc0, 0x00042381, 0x210048fe, 0xfe0ff01d, 0x46302301, 0x46192200, 0xfe23f01d, 0x46212301, 
+    0x4630220c, 0xfe1df01d, 0x46302301, 0x0359220d, 0xfe17f01d, 0x46292300, 0x46382208, 0xfe11f01d, 
+    0xf24048f1, 0xf01d11d4, 0x48effdf2, 0x1129f240, 0xf01d1c80, 0x2301fdec, 0x220b4659, 0xf01d4638, 
+    0x2300fe00, 0x220a4651, 0xf01d4638, 0x4ce6fdfa, 0x220b2301, 0x3c404659, 0xf01d4620, 0x2301fdf2, 
+    0x220a4651, 0xf01d4620, 0x2301fdec, 0x21024620, 0xf01d461a, 0x2301fde6, 0x22004620, 0xf01d4619, 
+    0x48dafde0, 0x22042300, 0xf01d2130, 0xe8bdfdda, 0x23015ff0, 0x220048d6, 0xf01d4619, 0x4ad5bdd2, 
+    0x2005210a, 0xf7f2b510, 0x2004fc4c, 0xfc4df7f9, 0xf7f92002, 0x2002fc4a, 0xfc12f00d, 0x200249ce, 
+    0x48ce7008, 0xb9207800, 0x200422ff, 0xf7f44611, 0x48cbfd83, 0x22002301, 0xf01d210f, 0x48c4fdb2, 
+    0x2200230b, 0x385a210f, 0xfdabf01d, 0x220248be, 0x38282104, 0xfdb3f01d, 0xd1102801, 0xf7fd2000, 
+    0x4cbbfe01, 0x220a2301, 0x02993c32, 0xf01d4620, 0x2208fd98, 0x23014620, 0xf01d0151, 0x48b3fd92, 
+    0x220f2301, 0x383403d9, 0xfd8bf01d, 0x210048b0, 0x4010e8bd, 0xf01d3848, 0xe92dbd6a, 0x4aad41f0, 
+    0x2005210b, 0xfbfdf7f2, 0xf7f92004, 0x2002fbfe, 0xfbfbf7f9, 0xf00d2001, 0x49a7fbc3, 0x22002001, 
+    0x70084603, 0x48a6210f, 0xfd6bf01d, 0xf2414da0, 0x23000400, 0x3d504621, 0x4628220c, 0xfd61f01d, 
+    0x1eae2303, 0x22004619, 0xf01d4630, 0x2301fd5a, 0x22024630, 0xf01d2104, 0x2301fd54, 0x220f4630, 
+    0x463903df, 0xfd4df01d, 0x46212301, 0x4628220c, 0xfd47f01d, 0x46212300, 0x4628220c, 0xfd41f01d, 
+    0x46392300, 0x4630220f, 0xfd3bf01d, 0x46302300, 0x461a2103, 0xfd35f01d, 0x46302300, 0x21042202, 
+    0xfd2ff01d, 0x220e4887, 0xf01d00a1, 0x2800fd38, 0xe8bdd003, 0xf00d41f0, 0xe8bdbbf6, 0x498281f0, 
+    0xb5102000, 0xf7ff7008, 0x487efb82, 0x220c2301, 0x1d800319, 0xfd15f01d, 0xf7fd2002, 0xf7fffd73, 
+    0x4872fb52, 0x1d802100, 0xfcf1f01d, 0x23014c70, 0x3c32220a, 0x46200299, 0xfd03f01d, 0x46202301, 
+    0x02592209, 0xfcfdf01d, 0x46202208, 0x01512301, 0xfcf7f01d, 0xfb92f00d, 0xfdaaf7f3, 0x46082100, 
+    0xff34f00b, 0x4a632109, 0x4010e8bd, 0xf7f22005, 0x4866bb68, 0x4d5bb570, 0xb1087800, 0xe0002301, 
+    0x46282300, 0x21082203, 0xfcdbf01d, 0x78214c60, 0xd02d0788, 0xd5010708, 0xd5010748, 0xe0002301, 
+    0x46282300, 0x21022201, 0xfccbf01d, 0x07017820, 0x0740d401, 0x2301d401, 0x2300e000, 0x22024628, 
+    0xf01d2104, 0x7820fcbe, 0x0103f000, 0x302c484d, 0xd9012901, 0xe0002301, 0x22002300, 0xf01d2101, 
+    0x484cfcb0, 0x1d244c3f, 0xb1617801, 0xe00b2301, 0x46282300, 0x21042202, 0xfca3f01d, 0x46282300, 
+    0x21022201, 0x2300e7eb, 0x22004620, 0xf01d2101, 0x4941fc98, 0xb1097809, 0xe0002301, 0x46202300, 
+    0x21022201, 0xfc8df01d, 0x22014d2e, 0x3d382102, 0xf01d4628, 0x2206fc94, 0x21404604, 0xf01d4628, 
+    0x4304fc8e, 0x22054628, 0xf01d2120, 0x4304fc88, 0xb2e34832, 0x22044c33, 0x70032110, 0x70034830, 
+    0xf01d4620, 0x2300fc6e, 0x22034620, 0xf01d2108, 0xe8bdfc68, 0x482c4070, 0xf01d2100, 0xb510bc48, 
+    0x2100f3c0, 0xea042402, 0xf3c00141, 0x43111200, 0x2340f3c0, 0xea022204, 0x43110283, 0x70114a23, 
+    0x11c0f3c0, 0x70114a22, 0x78094922, 0xd1532901, 0xf3c04a21, 0x70110180, 0x01c0f3c0, 0x70114a1f, 
+    0x1140f3c0, 0x70114a1e, 0x1180f3c0, 0x70114a1d, 0x0201f000, 0x780b491c, 0x700a431a, 0x780a491b, 
+    0x0000e036, 0xf38e0078, 0xf38f00a4, 0xf38f2050, 0xf38f22d2, 0xcccc0000, 0x0004024c, 0x0004028d, 
+    0xf23c8316, 0xf2039026, 0x0004235e, 0x000402cb, 0x000402cc, 0x00042329, 0x0004232a, 0x000425ec, 
+    0x000425e0, 0xf2035256, 0xf23c8026, 0x0004232d, 0x0004232b, 0x000425f4, 0x000425fb, 0x000425fa, 
+    0x000425ef, 0x000425f0, 0x000425fd, 0x000425fc, 0x0040f3c0, 0x700a4302, 0xe92dbd10, 0x4dff5ff0, 
+    0x4aff4692, 0xf8df2400, 0x469b83fc, 0xe3f8f8df, 0x4efe702c, 0xf8df4ffe, 0x781293fc, 0x4bfeb148, 
+    0xf8932801, 0xea4fc00b, 0xd00913dc, 0xd0322802, 0x48fae016, 0x28186800, 0xf889d334, 0xe00f2000, 
+    0x0f01f1ba, 0xf888d10c, 0xf3cc3000, 0xf88e1040, 0x70303000, 0xf3cc7038, 0xf8891080, 0x70282000, 
+    0x0f00f1bb, 0x2000d00a, 0x0000f88e, 0xf8884aec, 0x70300000, 0xf8897038, 0x70100000, 0xf8df2903, 
+    0xf8df83a4, 0xf8dfa3a4, 0xd00eb3a4, 0xd0202905, 0xd0312904, 0xf1bae042, 0xd1030f01, 0x3000f888, 
+    0x3000f88e, 0x703a7032, 0x2201e7c7, 0x21024640, 0xfba5f01d, 0xf88a2201, 0x21020000, 0xf01d4640, 
+    0xf88bfb9e, 0x24050000, 0xf89948d9, 0x70011000, 0x2206e024, 0x21404640, 0xfb91f01d, 0xf88a2206, 
+    0x21400000, 0xf01d4640, 0xf88bfb8a, 0x24040000, 0x783948cf, 0xe0117001, 0x46402205, 0xf01d2120, 
+    0x2205fb7e, 0x0000f88a, 0x46402120, 0xfb77f01d, 0x0000f88b, 0x48c62403, 0x70017831, 0xf89a2601, 
+    0x48c41000, 0x8310f8df, 0x4fc42901, 0x9310f8df, 0x49bfd103, 0x29017809, 0xf89bd004, 0x29011000, 
+    0xe025d022, 0x680949b5, 0xd3082912, 0x70012102, 0xfa067829, 0x4308f004, 0x403cf440, 0x2103e007, 
+    0x78297001, 0xf004fa06, 0xf4404308, 0xb281406e, 0xf01d4640, 0x4648fb1c, 0xe8bd703e, 0x23005ff0, 
+    0x21082203, 0xbb2df01d, 0x780949a5, 0xd00e2901, 0x70042400, 0x46232203, 0x46482108, 0xfb21f01d, 
+    0x46402100, 0xfb03f01d, 0xe8bd703c, 0x21049ff0, 0x23017001, 0x22034648, 0xf01d2108, 0x2301fb12, 
+    0x220048a0, 0xf01d4619, 0x7829fb0c, 0xf004fa06, 0xb2804308, 0x414ff440, 0xf01d4640, 0x489afae8, 
+    0x703e499a, 0x78004c9d, 0x43087809, 0x70084998, 0x49994898, 0x780a7800, 0x43104999, 0x20017020, 
+    0xf96ff7f2, 0x20017822, 0x5ff0e8bd, 0xf7f24995, 0xe92db968, 0x488841f0, 0x461f2104, 0x23014614, 
+    0x38162202, 0x5606e9dd, 0xfadbf01d, 0x4c824623, 0xf240220a, 0x3c404100, 0xf01d4620, 0x2209fad2, 
+    0xf240463b, 0x46202100, 0xfacbf01d, 0x462b2206, 0x46202140, 0xfac5f01d, 0x46332205, 0x46202120, 
+    0xfabff01d, 0x46202301, 0x03dd220f, 0xf01d4629, 0x4629fab8, 0xe8bd4620, 0x230041f0, 0xf01d220f, 
+    0xb51cbab0, 0xd1202801, 0x79c94963, 0x4976098a, 0x700a2a01, 0x4975d119, 0x78094b75, 0xf7ff781b, 
+    0x495bfeac, 0x78094859, 0xe9cd7800, 0x48560100, 0x48547803, 0x486f7802, 0x486f7801, 0xf7ff7800, 
+    0xe8bdffa8, 0xf7f8401c, 0xbd1cbd30, 0x0301f001, 0x0240f3c1, 0xf3c12803, 0xd0040180, 0xd0052805, 
+    0xd0062804, 0xb139e008, 0x47702003, 0x2002b122, 0xb10b4770, 0x47702001, 0x47702000, 0xe9ddb570, 
+    0x9e045405, 0xd1012c01, 0xd0092805, 0xd0072803, 0xb10eb935, 0xe002b94a, 0xb932b911, 0xb109e002, 
+    0xbd702000, 0x2002b10b, 0x2001bd70, 0x4308bd70, 0x2001d000, 0xb5704770, 0x21034c50, 0xf01d4620, 
+    0x2181fa36, 0xf01d1f20, 0x494dfa32, 0x4620220f, 0xf248780b, 0xf01d0100, 0x4d4afa44, 0xb3607828, 
+    0x46202301, 0x21402206, 0xfa3bf01d, 0xf6477828, 0x1e404100, 0x220ab283, 0xf01d4620, 0x4842fa32, 
+    0x21802207, 0x46207803, 0xfa2bf01d, 0x46202301, 0x21202205, 0xfa25f01d, 0xfbcef012, 0x23004826, 
+    0x213e2201, 0xf01d3874, 0x2004fa1c, 0xf89df7f9, 0x4070e8bd, 0xf7f9200b, 0x2300b9cb, 0x21402206, 
+    0xe92de7da, 0xf8df47f0, 0xf24fa0c4, 0x23000900, 0x220c4688, 0x46494607, 0xf01d4650, 0xf10afa02, 
+    0xf6400402, 0x23024100, 0x220a4620, 0xf9f9f01d, 0xf2404822, 0x309a7100, 0x0000e04a, 0x000425e2, 
+    0x000425f1, 0x000425fa, 0x000425fb, 0x000425f0, 0x000425ef, 0x000425ee, 0x000434d0, 0x00040240, 
+    0x000425e1, 0xf38e0040, 0x000425ec, 0x000425e0, 0x000425ed, 0x00042fce, 0xf38f0076, 0x00042fcd, 
+    0xf2035256, 0xf23c8024, 0x000425e9, 0x000425ea, 0x000425eb, 0x000425e6, 0x000425e7, 0x000425e8, 
+    0xfeda0000, 0xfedc0000, 0x0004257b, 0x00040292, 0x0004232e, 0x000425fd, 0x000425fc, 0xf38f2056, 
+    0x00042357, 0x00042358, 0x00042359, 0xf2039076, 0x0f03f1b8, 0x35fff240, 0x76fff240, 0x2300d02d, 
+    0xf01d2208, 0x2324f99e, 0x22004629, 0xf01d4620, 0x2303f998, 0x220c4649, 0xf01d4620, 0xf240f992, 
+    0x46313304, 0x46502200, 0xf98bf01d, 0x23004c15, 0x217e2201, 0xf01d4620, 0x2f01f984, 0x230cd120, 
+    0x22014620, 0xf01d217e, 0x4649f97c, 0xe8bd4650, 0x230f47f0, 0xf01d220c, 0x2303b974, 0xf01d2208, 
+    0x231bf970, 0x22004629, 0xf01d4620, 0x2304f96a, 0x220c4649, 0xf01d4620, 0xf240f964, 0xe7d04300, 
+    0x87f0e8bd, 0xf38f0002, 0x4ff0e92d, 0xb2b8f8df, 0xf8dfb087, 0xf8db92b0, 0xf8d90000, 0x88008000, 
+    0x20009004, 0xfaabf7fb, 0x4000f240, 0x0a01f04f, 0xf8cd2205, 0x1044a00c, 0xe9cd9400, 0xf8d92001, 
+    0x1f920000, 0xf2402103, 0xf2406500, 0xf24016df, 0x465317a7, 0xfd4ef00e, 0xf04f489c, 0x78000100, 
+    0x46082800, 0x4a9ad00e, 0x2001f992, 0x2382eb08, 0x2011f933, 0xda002a00, 0x1c494252, 0x441042a1, 
+    0xe00adbf6, 0x3000f8d9, 0x2011f933, 0xda002a00, 0x1c494252, 0x441042a1, 0x1244dbf6, 0x42b42000, 
+    0xeba4dd04, 0xeba51464, 0xe0051165, 0xda0842bc, 0x1464eb04, 0x1165eb05, 0xb2401c40, 0x2810b20d, 
+    0xf44fdbed, 0xf2400800, 0x464011f4, 0xff2bf7f1, 0x46404980, 0xff16f7f1, 0x46404639, 0xff12f7f1, 
+    0x46404621, 0xff0ef7f1, 0x46404631, 0xff0af7f1, 0x46404629, 0xff06f7f1, 0x46404977, 0xff02f7f1, 
+    0xf7f92000, 0x4e75fc15, 0x4800f240, 0x78314640, 0xffb2f7f8, 0xf7f72001, 0x4f71fee6, 0x68389904, 
+    0xf8bef01e, 0x0000f8db, 0x106cf8b0, 0xf8206838, 0xf8db5011, 0x10692000, 0x01a5eb01, 0x24004249, 
+    0x206cf8b2, 0xeb004625, 0x80410042, 0x68382300, 0xe9cd461a, 0x20010500, 0xf7f7b261, 0x1c64fd14, 
+    0x2c04b2a4, 0x2000d3f2, 0xfebdf7f7, 0x78204c5d, 0xd0232801, 0xf00f2002, 0x7831fca3, 0xf7f82040, 
+    0xf7feff7b, 0x7831fca2, 0x0000f244, 0xff74f7f8, 0x4640220b, 0x46112300, 0x95019500, 0xfc97f7f9, 
+    0xf241220d, 0x23000000, 0x95004611, 0xf7f99501, 0x4f4dfc8e, 0xb3d87838, 0xe03e2001, 0xf00f2000, 
+    0x220efc7f, 0x0900f640, 0x46484611, 0xfd36f7f9, 0xf00f2002, 0x7831fc75, 0xf7f82040, 0x200cff4d, 
+    0x220d9000, 0x23014657, 0xe9cd4611, 0x9504a502, 0x90019505, 0xf7f94640, 0x200dfdb1, 0x23019000, 
+    0xe9cd4602, 0x46017502, 0x95059504, 0x46489001, 0xfda4f7f9, 0x9000200e, 0x46022301, 0x7502e9cd, 
+    0x95044601, 0x90019505, 0xf7f94648, 0xe7c0fd97, 0x7820e7ff, 0xd1bf2801, 0xf00d2000, 0x4605fe7a, 
+    0xf7f92000, 0x7831fb75, 0x464046c1, 0xff14f7f8, 0xd0342d00, 0xf2464d25, 0xf8df0a00, 0x220d8094, 
+    0xf9954651, 0xb2830000, 0xf01d4640, 0x2301f82a, 0x220f4640, 0xf01d03d9, 0x2001f824, 0xfc20f00f, 
+    0x46487831, 0xfef8f7f8, 0x481a7839, 0xf9952900, 0x5c411000, 0x7820d102, 0xd0012801, 0xe0002001, 
+    0xf00d2000, 0x2300fd05, 0x220d4651, 0xf01d4640, 0xb007f808, 0xe8bd2000, 0xf00f4ff0, 0xb007bc01, 
+    0x8ff0e8bd, 0x0004022c, 0x00042618, 0x0004232e, 0x00042598, 0x99339933, 0xdcba01f5, 0x00040293, 
+    0x00040238, 0x0004257a, 0x00042300, 0x0004027e, 0xf2035092, 0x0004259c, 0x47ffe92d, 0xf04f4ef8, 
+    0x15505200, 0x1000f996, 0xfe5bf7f1, 0xfe7cf7ff, 0xf7f92000, 0xf44ffb0d, 0xf2400500, 0x462811f4, 
+    0xfe01f7f1, 0x462849ef, 0xfdecf7f1, 0xf9944cee, 0xb2810000, 0xf7f14628, 0x49ecfdf6, 0xf7f14628, 
+    0x4668fde1, 0xff1df7fa, 0x0000f994, 0xd0011c40, 0xe0362007, 0xf9954de6, 0x1c400000, 0xeb0017c1, 
+    0xf0217191, 0x1a400103, 0x20007028, 0xfacaf7fe, 0x8380f8df, 0xf8df2400, 0xf240a380, 0x4fdf2900, 
+    0x2000f997, 0xd0032a03, 0x0000f898, 0xd00807c0, 0xb1087828, 0xe0004649, 0x46204651, 0xfbdcf7fe, 
+    0xf995e004, 0x46201000, 0xfe1cf01a, 0xb2641c64, 0xdbe52c04, 0x28007828, 0x7838d104, 0xf93bf7f5, 
+    0x70302003, 0x87ffe8bd, 0x5ffce92d, 0x46152400, 0xf01f46a2, 0x4ecafc4d, 0xf980fa0f, 0x8324f8df, 
+    0xf44f2701, 0x4ac80b80, 0x466849c8, 0xf8ad8037, 0xf8ada006, 0xf8ada002, 0xf8ada004, 0xf898a000, 
+    0xf7fa3000, 0x2172ff7f, 0xf7f14658, 0x2202fdb4, 0x21074648, 0xfb5af00f, 0xf7fa4668, 0x2000ff54, 
+    0xf9314669, 0x42aa2010, 0xf821db01, 0x1c405010, 0x2804b240, 0x48b6dbf5, 0x28037800, 0x48b5d104, 
+    0x0003f990, 0x7010f821, 0x3000f898, 0x4aae4668, 0xf7fa49ae, 0x2172ff57, 0xf7f14658, 0x8830fd8c, 
+    0xd1032802, 0xb2641c64, 0xdbbc2c0a, 0xa000f8a6, 0x9ffce8bd, 0x47f0e92d, 0xf04f4f99, 0x20505200, 
+    0x15506078, 0x1000f997, 0xfd9bf7f1, 0x20004ea2, 0x8270f8df, 0x499d4a9c, 0x80b080f0, 0x80308070, 
+    0xf8984630, 0xf7fa3000, 0xf44fff2d, 0x21720980, 0xf7f14648, 0x2202fd60, 0x1048f240, 0xf00f2107, 
+    0x251efb05, 0x24014630, 0xfefdf7fa, 0xf9362000, 0x42a91010, 0xf826db01, 0xf9365010, 0x42a11010, 
+    0xf826dc01, 0x1c404010, 0x2804b240, 0xf898dbef, 0x4a853000, 0x48884985, 0xff04f7fa, 0x46482172, 
+    0xfd39f7f1, 0x60782060, 0x87f0e8bd, 0x4c74b538, 0x90002000, 0x60602030, 0xf7fb4668, 0x487cf9b5, 
+    0x46687801, 0xd1042903, 0x21014a7a, 0x2003f992, 0x49745481, 0xb1617809, 0xf9914973, 0xf9912000, 
+    0x5c823002, 0xf99154c2, 0xf9912001, 0x5c821003, 0xf89d5442, 0x4d710000, 0xf89db1b8, 0xb1e80001, 
+    0x0002f89d, 0xf89db188, 0xb1700003, 0xf2422040, 0x60600110, 0xf7f10640, 0x2003fce2, 0x23017020, 
+    0x22004628, 0xf01c4619, 0xf89dfe9c, 0xb1280001, 0x46282301, 0x461a2102, 0xfe93f01c, 0x0002f89d, 
+    0x2301b128, 0x22024628, 0xf01c2104, 0xf89dfe8a, 0x28000003, 0x2301d005, 0x22034628, 0xf01c2108, 
+    0xbd38fe80, 0x5ff0e92d, 0x8e804604, 0x26014d44, 0x7f96f5b0, 0x1a05f240, 0x1b61f240, 0xdc35d07b, 
+    0xf2a04550, 0xd0691105, 0x28f0dc18, 0xdc06d074, 0x28ceb330, 0x28cfd071, 0x60aed170, 0x28f1e09f, 
+    0xf5b0d05c, 0xd1697f82, 0x22004935, 0x311068e8, 0xfc31f017, 0x1d4060a8, 0xe050d061, 0xd04d2910, 
+    0x2907dc0f, 0x2908d07c, 0x290fd048, 0x492cd156, 0x68e82200, 0xf0173110, 0x60a8fc1e, 0xd0701d40, 
+    0x291fe03d, 0x2920d06e, 0xe037d148, 0xf2a04558, 0xd0331161, 0xf5b0dc1b, 0xd07d7fa6, 0xf111dc07, 
+    0xd02b0034, 0xd0782813, 0xd1372814, 0xf5a0e026, 0x384d7080, 0x2813d022, 0x4919d130, 0x68e82200, 
+    0xf0173110, 0x60a8fbf8, 0xd0671d40, 0x291ae017, 0xdc0fd014, 0xd07d2911, 0xd00f2912, 0xd11d2919, 
+    0x2200490f, 0x311068e8, 0xfbe5f017, 0x1d4060a8, 0xe004d071, 0xd06f2921, 0xd10f2922, 0xf04f60ae, 
+    0x490732ff, 0x311068e8, 0xfc04f017, 0x1d0060a8, 0x68a8d029, 0xe157e02f, 0xe026e0a5, 0xe0d1e0d4, 
+    0x000426b0, 0x99349934, 0x0004027e, 0xdcba01f5, 0x00042580, 0x000402b4, 0xfffffa00, 0x00040292, 
+    0x000402bc, 0x0004232e, 0x00042598, 0x000425c6, 0x00040284, 0x00042590, 0x000425b0, 0xf2035018, 
+    0xe0eae0c6, 0x20cee114, 0x49fae1e3, 0x68e82200, 0xfbd0f017, 0x1d4160a8, 0x2801d044, 0x4ff5d1bf, 
+    0x1000f240, 0x3000f9b7, 0xd03d2b0f, 0xf04f0542, 0xf04f080a, 0xe0024c20, 0xe137e156, 0x2b10e17d, 
+    0x2b0ad03a, 0xf995d1ab, 0xf8df1000, 0xb39193ac, 0xd06f2903, 0xd06e2906, 0xd06d2902, 0xd06c2904, 
+    0xd06b290c, 0xd06a2907, 0xd0692905, 0xd0682909, 0xe002290a, 0xe19be17a, 0xd06fe1a0, 0xd18e290b, 
+    0x46624619, 0xfc0df7f1, 0x8038200b, 0xf04f48db, 0x463932ff, 0xf0176800, 0x60a8fb5e, 0xd0731d00, 
+    0xe19268a8, 0xe19420cf, 0x4222f04f, 0xf7f14619, 0x702efbf8, 0xe030e773, 0xf99149d1, 0x29031000, 
+    0x2905d003, 0x2904d001, 0x49ced102, 0xb1217809, 0x702e210f, 0xfbe5f7f1, 0x4619e761, 0xf7f14662, 
+    0xf000fbe0, 0x2000fa6b, 0xf8a77028, 0x46028000, 0x68e849c0, 0xfb2ff017, 0x1d0060a8, 0x68a8d001, 
+    0x20f0e007, 0x49bbe165, 0x68e82200, 0xfb23f017, 0x1d4060a8, 0x20f1d1ce, 0xf7ffe15b, 0x2002fe67, 
+    0xfbd8f7f8, 0xf899b920, 0x1e400000, 0xd2092806, 0xe008200a, 0xe036e01a, 0xe084e052, 0xe0c0e09f, 
+    0xe0fde0dd, 0x8038200f, 0x220049aa, 0xf01768e8, 0x60a8fb02, 0xd0021d00, 0xe6cc68a8, 0xf240e111, 
+    0xe1361004, 0xa034f8a4, 0x9ff0e8bd, 0xfdf2f7ff, 0x70282006, 0x2200499f, 0xf01768e8, 0x60a8faec, 
+    0xd0021d00, 0xe00968a8, 0xf240e115, 0xe120100c, 0x22004998, 0xf01768e8, 0x60a8fade, 0xd1891d40, 
+    0x100df240, 0x2370e115, 0xf7f1606b, 0x4996fb7a, 0x4896221e, 0xfd78f7ff, 0x60682080, 0x70282002, 
+    0x2200498c, 0xf01768e8, 0x60a8fac6, 0xd0011d00, 0xe6a368a8, 0x1014f240, 0xf240e0fb, 0xe0f81015, 
+    0x606b2390, 0xfb5df7f1, 0x20012100, 0xff1ef00a, 0xf44f2100, 0xf7f81080, 0x2100fbaf, 0xf00a4608, 
+    0xf00fff15, 0xf7f8f90b, 0xf7f8ffc7, 0x20a0ffe2, 0x20046068, 0x49777028, 0x68e82200, 0xfa9bf017, 
+    0x1d0060a8, 0x68a8d001, 0xf240e008, 0xe0d01024, 0x22004970, 0xf01768e8, 0x60a8fa8e, 0xd1ae1d40, 
+    0x1025f240, 0xf000e0c5, 0x200cf98c, 0x49697028, 0x68e82200, 0xfa7ff017, 0x1d0060a8, 0x68a8d001, 
+    0xf240e008, 0xe0b4102c, 0x22004962, 0xf01768e8, 0x60a8fa72, 0xd1921d40, 0x102df240, 0xf7ffe0a9, 
+    0x2002fcab, 0xfb26f7f8, 0x200ab108, 0x200fe000, 0x49588038, 0x68e82200, 0xfa5df017, 0x1d0060a8, 
+    0x68a8d001, 0xf240e008, 0xe0921040, 0x22004951, 0xf01768e8, 0x60a8fa50, 0xd1c01d40, 0x1041f240, 
+    0xf7f1e087, 0xf007faee, 0x2005ff2b, 0x49497028, 0x68e82200, 0xfa3ff017, 0x1d0060a8, 0x68a8d001, 
+    0xf240e008, 0xe074104c, 0x22004942, 0xf01768e8, 0x60a8fa32, 0xd1a21d40, 0x104df240, 0xf000e069, 
+    0xf899f8fa, 0x28030000, 0x2002d005, 0xfae2f7f8, 0x200ab120, 0xf8a7e003, 0xe0018000, 0x8038200f, 
+    0x22004934, 0xf01768e8, 0x60a8fa16, 0xd0011d00, 0xe61968a8, 0x1060f240, 0xf8a4e04b, 0xe713b034, 
+    0xf8a1f000, 0x0000f899, 0xf43f2803, 0xf885add6, 0x22008000, 0x68e84927, 0xf9fdf017, 0x1d0060a8, 
+    0x68a8d001, 0xf240e008, 0xe0321072, 0x22004921, 0xf01768e8, 0x60a8f9f0, 0xd19e1d40, 0x1073f240, 
+    0xf000e027, 0x2002f845, 0xfaa4f7f8, 0x200ab108, 0x200fe000, 0x49178038, 0x68e82200, 0xf9dbf017, 
+    0x1d0060a8, 0x68a8d001, 0xf240e5f1, 0xe010107a, 0x107bf240, 0xf240e00d, 0xe00a1082, 0x2200480f, 
+    0x6800490c, 0xf9c7f017, 0x1d4060a8, 0xf240d193, 0x86a01083, 0x2200e6c8, 0xb5102101, 0x503bf2af, 
+    0xf804f017, 0x20032108, 0xf962f017, 0x39104901, 0xbd1060c8, 0x000426c0, 0x00040284, 0x0004274c, 
+    0x00040292, 0x00042300, 0x44b861ec, 0x43a4170a, 0xf00cb510, 0x4985ff39, 0xf01c4885, 0x2801f997, 
+    0x1300f240, 0x21e2d019, 0x4618461c, 0xf9ebf7f1, 0x46202100, 0xf9d6f7f1, 0x01d0f242, 0xf7f14620, 
+    0x487cf9ee, 0x28017800, 0x2100d01a, 0xe8bd487a, 0xf2014010, 0xf01c312b, 0x4875bb8a, 0x79c04977, 
+    0x1000f3c0, 0x28007008, 0x4c75d0c3, 0x5200f04f, 0xf9944618, 0xf7f11000, 0x200bfa14, 0xe7b87020, 
+    0x7110f242, 0xb50ee7e2, 0x2001496e, 0x486e7008, 0xb1787800, 0x486e496d, 0x78007809, 0x0100e9cd, 
+    0x7801486c, 0x7803486c, 0x7802486c, 0x7800486c, 0xfebcf7fb, 0x496c486b, 0x0000f990, 0xf959f7f7, 
+    0x21044a6a, 0xf01c4868, 0x485dfa27, 0x5200f04f, 0x1000f990, 0xf7f11550, 0x2004f9e4, 0xf9c6f00f, 
+    0x70084963, 0x46022000, 0x90024601, 0x0000e9cd, 0xfc02f7f7, 0xb510bd0e, 0xf04f4c51, 0x15505200, 
+    0x1000f994, 0xf9cdf7f1, 0xfa1af00d, 0x4859b158, 0x28037800, 0x2009d002, 0xe76a7020, 0xf7f82004, 
+    0x200bf9c4, 0x2000e7f8, 0xfc99f7fa, 0x78004849, 0xfcf1f7f4, 0x22034850, 0x23007022, 0xf9904949, 
+    0x550b4000, 0x4001f990, 0x550b2301, 0x4002f990, 0x550b2302, 0x0003f990, 0xe8bd540a, 0xf00d4010, 
+    0xb510b960, 0xf04f4c36, 0x20b05200, 0x15506060, 0x1000f994, 0xf995f7f1, 0x606020b1, 0xff4ef00e, 
+    0xfe0af7f8, 0xfe25f7f8, 0x606020bb, 0x78004839, 0x2807b170, 0x20e0d00c, 0x48386060, 0x68012200, 
+    0xf7f82002, 0xf00df9a7, 0x20f0ffa9, 0xe7206060, 0x606020c0, 0xffa2f00d, 0xe7f720d0, 0x4c20b570, 
+    0x21012010, 0x60600105, 0xf7f14628, 0xf240f91c, 0x462811f4, 0xf917f7f1, 0x68004829, 0x41d0f040, 
+    0xf7f14628, 0x4927f8ff, 0xf7f14628, 0x2000f8fb, 0xfa78f7fa, 0xfb6ef7fa, 0x60602020, 0x2400481e, 
+    0xf9904918, 0x548c2000, 0x3001f990, 0x54ca2201, 0x3002f990, 0x54ca2202, 0x0003f990, 0x540a2203, 
+    0xf8fff00d, 0x70044818, 0x0000bd70, 0x0002ec30, 0x000434d0, 0x0004257a, 0xf23c80ba, 0x00040254, 
+    0x000426b0, 0x00040253, 0x0004254d, 0x0004261f, 0x0004261e, 0x00040292, 0x0004261d, 0x0004261c, 
+    0x0004254c, 0x00042590, 0x00043350, 0x000433d0, 0x00040255, 0x00040284, 0x00042598, 0x00042604, 
+    0x00057f78, 0xdcba01f5, 0x00042580, 0x4cffb510, 0x4280f04f, 0xf9b41510, 0xf7f11000, 0xf00df902, 
+    0xb168f94f, 0x22112300, 0x3100f44f, 0x4071f04f, 0xfa60f01c, 0xf7f82001, 0x200efdab, 0xbd108020, 
+    0x80202007, 0x220048f2, 0xf99049f2, 0x54ca3000, 0x3001f990, 0x54ca2201, 0x3002f990, 0x54ca2202, 
+    0x0003f990, 0x540a2203, 0x4010e8bd, 0xb899f00d, 0xf04f48e6, 0xb5104280, 0x1000f9b0, 0xf7f11510, 
+    0x48e5f8d0, 0xfa4ff7fa, 0x200049e3, 0x2301221e, 0x4010f931, 0xdb012c1e, 0x2010f821, 0x4010f931, 
+    0xdc012c01, 0x3010f821, 0xb2401c40, 0xdbef2804, 0x4ad748da, 0x780349da, 0xf7fa48d7, 0x2172fa53, 
+    0x0080f44f, 0xf887f7f1, 0x4010e8bd, 0xbce8f007, 0x47f0e92d, 0xf04f4ecd, 0x15104280, 0x1000f9b6, 
+    0xf89ff7f1, 0xf8c0f7ff, 0xf7f82000, 0x48cdfd51, 0x0000f990, 0xd0011c40, 0xe0332012, 0xf9954dca, 
+    0x1c400000, 0xeb0017c1, 0xf0217191, 0x1a400103, 0x20007028, 0xfd26f7fd, 0x8310f8df, 0xf8df2400, 
+    0xf240a310, 0x4fc32900, 0x2000f997, 0xd0032a03, 0x0000f898, 0xd00807c0, 0xb1087828, 0xe0004649, 
+    0x46204651, 0xfe38f7fd, 0xf995e004, 0x46201000, 0xf878f01a, 0xb2641c64, 0xdbe52c04, 0x28007828, 
+    0x2007d101, 0xe8bd8030, 0xe92d87f0, 0xa0b24ff0, 0xb08d4fb3, 0x1000e9d0, 0x100be9cd, 0x683d48b1, 
+    0x28126800, 0xf648d314, 0x9004409c, 0x30adf646, 0xf2429005, 0x9006707a, 0x1029f241, 0xf6409007, 
+    0x90083063, 0x40e7f240, 0xf2409009, 0xe01320a9, 0x30a4f244, 0xf2439004, 0x9005401c, 0x4016f241, 
+    0xf6409006, 0x9007003d, 0x505bf240, 0xf2409008, 0x9009207f, 0x104df240, 0xb230f8df, 0x4a00f240, 
+    0xf04f900a, 0x46564280, 0xf9bb4650, 0xf7f11000, 0x2100f818, 0x2000f44f, 0xf86ef7f8, 0x24052101, 
+    0x1e8a0208, 0x6102e9cd, 0x0400e9cd, 0x23006838, 0xf00d2108, 0x2200fd9f, 0x46114613, 0xeb052000, 
+    0xf9372741, 0x1c406010, 0x28ffb280, 0x2386fbc6, 0x1c49d9f7, 0x2904b2c9, 0x9804d3f0, 0x4e820c95, 
+    0x3583ea45, 0xd80142a8, 0xe0337034, 0x70302000, 0xa8044604, 0x0184eb00, 0x42a96849, 0xf850d822, 
+    0xeb007024, 0x68400084, 0xf01e1a38, 0x4680f995, 0x1b784689, 0xf990f01e, 0x460f4605, 0x1901a80b, 
+    0x78495d04, 0xf01e1b08, 0x462af970, 0xf01e463b, 0x4642f9d3, 0xf01d464b, 0xf01effb3, 0x4420f939, 
+    0xe0037030, 0xb2a41c64, 0xd3d32c06, 0xb9087830, 0x70302064, 0xf6407830, 0x46540100, 0x70303023, 
+    0xf7f04650, 0x7831ff60, 0xf7f04620, 0x2100ff4b, 0xf00a2001, 0x4c5dfb6b, 0x4e502500, 0x46204a4c, 
+    0x80e5494f, 0x806580a5, 0x78338025, 0xf93af7fa, 0x0880f44f, 0x46402172, 0xff6df7f0, 0x22004f54, 
+    0x46382101, 0xf91bf01c, 0x2201b988, 0x21024638, 0xf915f01c, 0x2202b958, 0x21044638, 0xf90ff01c, 
+    0x2203b928, 0x21084638, 0xf909f01c, 0x2001b110, 0xfd0cf7fb, 0xf2402202, 0x210710c3, 0xfcf6f00e, 
+    0xf7fa4842, 0xf9bbf8f0, 0x20001002, 0x2010f934, 0xdb01428a, 0x1010f824, 0xb2401c40, 0xdbf52804, 
+    0x4a2b7833, 0x4839492e, 0xf8fcf7fa, 0x46402172, 0xff31f7f0, 0xf00e2002, 0x2000fcd3, 0xfa2ff7fa, 
+    0xf7fb2000, 0x2100f99f, 0xf00a2001, 0x2100fb0f, 0x2000f44f, 0xffa0f7f7, 0xf00e2004, 0x492dff27, 
+    0x21007008, 0x4608460a, 0xe9cd9502, 0xf7f71100, 0x2100f963, 0xf00a4608, 0xb00dfaf9, 0x8ff0e8bd, 
+    0xf04f4812, 0xf9b04280, 0x15101000, 0xbf29f7f0, 0xb5102101, 0x4620028c, 0xfed5f7f0, 0x11f4f240, 
+    0xf7f04620, 0x491cfed0, 0xf0406808, 0x462041f0, 0xfeb8f7f0, 0x46204919, 0xfeb4f7f0, 0x201e4903, 
+    0x20018048, 0xf8b0f7f9, 0xe0292400, 0x000426c8, 0x00042598, 0x00042590, 0x000425b8, 0x0004232e, 
+    0x000425c6, 0x0004027e, 0x00042580, 0x000402b4, 0xfffffa00, 0x00040292, 0x321e0a05, 0x0064503c, 
+    0x0004022c, 0x00040240, 0x0004257c, 0x000425b0, 0xf20305c2, 0x00040255, 0x00057f78, 0xdcba01f5, 
+    0x49fc48fb, 0x2000f990, 0xf990548c, 0x22013001, 0xf99054ca, 0x22023002, 0xf99054ca, 0x22030003, 
+    0xf00c540a, 0x48f4fe8e, 0xbd107004, 0x5ff0e92d, 0x8e804604, 0xf2404df1, 0xf8df1919, 0xf5b0b3c4, 
+    0xf2407fb3, 0xd0741aa1, 0x4548dc32, 0x1119f2a0, 0xdc16d064, 0xd06d28ec, 0xb318dc05, 0xd06c28c6, 
+    0xd16928c7, 0x28ede073, 0xf5b0d058, 0xd1637f8c, 0x220049e2, 0x31086868, 0xfdfdf016, 0xd07d1d40, 
+    0x291ce04c, 0xdc0ed04a, 0xd0782909, 0xd045290a, 0xd151291b, 0x220049d9, 0x31086868, 0xfdebf016, 
+    0xd06d1d40, 0x2943e03a, 0x2944d06b, 0xe035d144, 0xf2a04550, 0xd03111a1, 0xf5b0dc1a, 0xd07d7fbd, 
+    0xf111dc07, 0xd029003a, 0xd0782809, 0xd133280a, 0xf5a0e024, 0x387b7080, 0x2825d020, 0x49c7d12c, 
+    0x68682200, 0xf0163108, 0x1d40fdc6, 0xe015d068, 0xd0132916, 0x2909dc0e, 0x290ad071, 0x2915d00e, 
+    0x49bed11a, 0x68682200, 0xf0163108, 0x1d40fdb4, 0xe003d06f, 0xd06d2925, 0xd10d2926, 0xf04f49b7, 
+    0x686832ff, 0xf0163108, 0x1d01fdd5, 0x20c6d10b, 0xe122e1ed, 0xe000e084, 0x49b0e0ae, 0x68682200, 
+    0xf0163108, 0x1d41fdc7, 0x2801d04a, 0x4eabd1e6, 0x0800f04f, 0x4000f240, 0xf9b63608, 0x290f1000, 
+    0x4fa8d040, 0x29110502, 0x290ad045, 0xf9b5d1d6, 0xf8df1000, 0x29028294, 0xe003d06c, 0xe0a1e08a, 
+    0xe0e0e0c2, 0xd07c2901, 0xd07b2903, 0xd07a2904, 0xd0792905, 0xd0782906, 0xd0772907, 0xd0762910, 
+    0xd0752912, 0xd0742908, 0xd1b7290e, 0xfe09f7f0, 0x0170f242, 0xf7f006c8, 0xe002fdc2, 0xe0fce128, 
+    0x200be165, 0x200f8030, 0xf8db8028, 0xf04f0000, 0x463132ff, 0xfd4ff016, 0xd0721d01, 0xe167e193, 
+    0xe19420c7, 0x4224f04f, 0xfdebf7f0, 0x8000f8a5, 0xe17ce794, 0xf997e181, 0x2b033000, 0x2b05d003, 
+    0x2b04d001, 0x4b81d102, 0xb12b781b, 0xf8a52113, 0xf7f08000, 0xe781fdd6, 0x4220f04f, 0xfdd1f7f0, 
+    0xfea6f7ff, 0x20024975, 0x200a8028, 0x22008030, 0x31086868, 0xfd1ff016, 0xd1071d01, 0xe16620ec, 
+    0x2200496e, 0x31086868, 0xfd15f016, 0xd1cf1d40, 0xe15c20ed, 0x0000f898, 0xd1022801, 0xf7f72002, 
+    0xf7fffdb4, 0x4965fe7d, 0x80282001, 0x68682200, 0xf0163108, 0x1d01fd00, 0xaf00f47f, 0x1018f240, 
+    0xe00be145, 0xe042e029, 0xe081e068, 0xe0c9e0a0, 0xe117e100, 0x9034f8a4, 0x9ff0e8bd, 0xfd91f7f0, 
+    0x20012100, 0xf952f00a, 0x20034954, 0x22008028, 0x31086868, 0xfcdff016, 0xd1091d01, 0x1022f240, 
+    0xe117e125, 0x2200494d, 0x31086868, 0xfcd3f016, 0xd18d1d40, 0x1023f240, 0xf7f0e119, 0x2100fd72, 
+    0x1080f44f, 0xfdc8f7f7, 0xfd15f006, 0x20044943, 0x22008028, 0x31086868, 0xfcbdf016, 0xf47f1d01, 
+    0xf240aecf, 0xe1021034, 0x1035f240, 0xf7f0e0ff, 0x2100fd58, 0xf00a4608, 0xf898f919, 0x28010000, 
+    0x4936d00a, 0x80282005, 0x68682200, 0xf0163108, 0x1d01fca2, 0xe00cd004, 0xf7f72002, 0xe6edfd46, 
+    0x105cf240, 0x492de0e3, 0x68682200, 0xf0163108, 0x1d40fc92, 0xf240d1f3, 0xe0d8105d, 0xf942f000, 
+    0x20064926, 0x22008028, 0x31086868, 0xfc83f016, 0xd1081d01, 0x1066f240, 0x4920e0c9, 0x68682200, 
+    0xf0163108, 0x1d40fc78, 0xf240d1d9, 0xe0be1067, 0xf8cef000, 0xf7f72002, 0xb108fd2d, 0xe000200a, 
+    0x4916200f, 0x22008030, 0x31086868, 0xfc63f016, 0xd1081d01, 0x1070f240, 0x4910e0a9, 0x68682200, 
+    0xf0163108, 0x1d40fc58, 0xf240d1b9, 0xe09e1071, 0xfc9bf7ff, 0x20104909, 0x22008028, 0x31086868, 
+    0xfc49f016, 0xd1181d01, 0x107af240, 0x0000e08f, 0x00042598, 0x00042590, 0x00042580, 0x000426c8, 
+    0x0004274c, 0x00040292, 0x00040284, 0x00042300, 0x2200498e, 0xf0166868, 0x1d40fc2e, 0xf240d18f, 
+    0xe074107b, 0xfc24f7ff, 0x78004889, 0xd01007c0, 0xf7f72002, 0xb960fcdf, 0x0000f997, 0x28044985, 
+    0x2805d00d, 0x2803d00f, 0xd0108808, 0x4080f440, 0x20028008, 0xfccef7f7, 0x200ab160, 0x8808e00b, 
+    0x7000f440, 0x8808e7f4, 0x0040f040, 0xf040e7f0, 0xe7ed0008, 0x8030200f, 0x22004974, 0xf0166868, 
+    0x1d01fbfa, 0xae31f47f, 0x10a0f240, 0xf8a4e03f, 0xe701a034, 0xfbbcf7ff, 0x80282008, 0x2200496b, 
+    0xf0166868, 0x1d01fbe8, 0xf240d107, 0xe02e10aa, 0x22004966, 0xf0166868, 0x1d40fbde, 0xf240d184, 
+    0xe02410ab, 0xfb72f7ff, 0xf7f72002, 0xb108fc93, 0xe000200a, 0x8030200f, 0x2200495c, 0xf0166868, 
+    0x1d01fbca, 0xae13f47f, 0x10b6f240, 0xf240e00f, 0xe00c10b7, 0x10c6f240, 0x4954e009, 0xf8db2200, 
+    0xf0160000, 0x1d40fbb8, 0xf240d188, 0x86a010c7, 0x2200e6c2, 0xb5102101, 0x40eff2af, 0xf9f6f016, 
+    0x20032108, 0xfb54f016, 0x39084948, 0xbd106048, 0x2000b5f8, 0x46689000, 0xf8a6f7fa, 0x78004846, 
+    0x4846b180, 0x2000f990, 0x3002f990, 0x2002f81d, 0x2003f80d, 0x2001f990, 0x0003f990, 0x2002f81d, 
+    0x2000f80d, 0x0000f89d, 0xd03a2800, 0x0001f89d, 0xd0362800, 0x0002f89d, 0xd0322800, 0x0003f89d, 
+    0xd02e2800, 0x0410f242, 0x06e54621, 0xf7f04628, 0x2000fbd6, 0xf8ccf7f8, 0x22074b2c, 0x3b084e30, 
+    0x801a4630, 0x22002301, 0xf01b4619, 0x2301fd8a, 0x21024630, 0xf01b461a, 0x2301fd84, 0x22024630, 
+    0xf01b2104, 0x2301fd7e, 0x22034630, 0xf01b2108, 0x4824fd78, 0x28106800, 0x4621d803, 0xf7f04628, 
+    0xbdf8fbae, 0xb50e4819, 0xf04f3808, 0xf9b04280, 0x15101000, 0xfbe5f7f0, 0x2000491b, 0x70084a1e, 
+    0x7008491a, 0x7008491a, 0x7008491a, 0x70112101, 0x491a4602, 0x491a7008, 0x46017008, 0x0000e9cd, 
+    0x20019002, 0xfdf8f7f6, 0x0140f242, 0xf7f00648, 0xf7f9fb86, 0x2001fddf, 0xf87af7f8, 0x2100b003, 
+    0x2000f44f, 0xeb04f85d, 0xbc16f7f7, 0x000426d0, 0x000402b4, 0x000402b6, 0x0004232e, 0x00042598, 
+    0xf2035018, 0x00040240, 0x00040273, 0x00040271, 0x0004026c, 0x0004026f, 0x00040253, 0x00040251, 
+    0x0004024e, 0x5ff0e92d, 0x46044da9, 0x4ea98e80, 0x686b28c8, 0xdc15d070, 0xd0342893, 0xb300dc0d, 
+    0xd16a2892, 0x46182200, 0x0108f105, 0xfb12f016, 0xd0261d41, 0xd1192801, 0x28b4e025, 0x28b5d06f, 
+    0xe013d15b, 0xd01128d1, 0x28c9dc0c, 0x28d0d00e, 0x4997d153, 0x46182200, 0xf0163108, 0x1d40facc, 
+    0xe003d07e, 0xd07c28da, 0xd14628db, 0xf04f4990, 0x686832ff, 0xf0163108, 0x1d01faed, 0x2092d1d8, 
+    0x2093e0c0, 0xf8dfe0be, 0x27008228, 0x2000f240, 0x0808f108, 0x1000f9b8, 0xd027290f, 0xf04f2912, 
+    0xf04f090a, 0xf04f5240, 0xd0274b00, 0xd1dd290a, 0x1000f9b5, 0xfb45f7f0, 0x0000f9b5, 0xd06d2802, 
+    0xd077280a, 0xd1d12806, 0x0170f242, 0xf7f04658, 0x200bfaf6, 0x0000f8a8, 0x80282007, 0x1e7a6830, 
+    0xf0164641, 0x1d01fa88, 0xe088d06f, 0x4223f04f, 0xfb27f7f0, 0xe7b9802f, 0xe084e05d, 0xf9934b6e, 
+    0x2b033000, 0x2b05d003, 0x2b04d001, 0x4b6bd102, 0xb12b781b, 0x802f2109, 0xfb13f7f0, 0xe033e7a6, 
+    0x4a20f04f, 0x46524607, 0xfb0bf7f0, 0x465221f1, 0xf7f04638, 0xf242fb06, 0x46580150, 0xfabff7f0, 
+    0xf7f72000, 0x485effb5, 0xf44f7801, 0xf7f72080, 0xf44ffb53, 0xf6403000, 0xf7f00103, 0xe001faa4, 
+    0xe046e043, 0xfe98f7fc, 0xfcadf7f8, 0x20024950, 0x22008028, 0x9000f8a8, 0x68683108, 0xfa3bf016, 
+    0xd1071d01, 0xe03d20b4, 0x22004949, 0x31084618, 0xfa31f016, 0xd1ae1d40, 0xe03320b5, 0x22004944, 
+    0x9000f8a5, 0x31086868, 0xfa25f016, 0xd1081d01, 0xe02720c8, 0x493ee00a, 0x46182200, 0xf0163108, 
+    0x1d40fa1a, 0x20c9d197, 0xe010e01c, 0xf82bf000, 0x20064937, 0x22008028, 0x31086868, 0xfa0bf016, 
+    0xf47f1d01, 0x20d0af3c, 0x20d1e00c, 0x20dae00a, 0x492fe008, 0x68302200, 0xf0163108, 0x1d40f9fc, 
+    0x20dbd18c, 0xe8bd86a0, 0x22009ff0, 0xb5102101, 0x200ff2af, 0xf83af016, 0x20032108, 0xf998f016, 
+    0x60484923, 0xb570bd10, 0x20012100, 0xfe4ef009, 0xf44f2100, 0xf7f72000, 0x2100fadf, 0xf0094608, 
+    0x4c20fe45, 0x46082100, 0x2000f994, 0xfcdff7f9, 0x0550f242, 0x06ee4629, 0xf7f04630, 0xf006fa30, 
+    0x4629fa1a, 0xf7f04630, 0x2100fa2a, 0xf7f92001, 0xf994ff1a, 0x21002000, 0xf7f9200c, 0x2101fc82, 
+    0x2000f994, 0xf7f94608, 0xf7fcfcc2, 0x4629ffde, 0xf7f04630, 0x2300fa14, 0x0bb12211, 0x4071f04f, 
+    0xfbb8f01b, 0x4070e8bd, 0xf7f72001, 0x0000bf01, 0x000426d8, 0x0004274c, 0x00040292, 0x00042300, 
+    0x00040293, 0x00040298, 0x4ffee92d, 0x4a00f04f, 0x0970f242, 0x46492500, 0xf7f04650, 0x2000f9f0, 
+    0xfee6f7f7, 0x260148fe, 0x46324cfe, 0x83f8f8df, 0x02707006, 0x20008020, 0xe9d89002, 0xe9cd1004, 
+    0x46311000, 0xf7f64630, 0x49f8fc47, 0x3cfff04f, 0x4bfa4af7, 0x78084ffb, 0x48f67010, 0x78004af8, 
+    0x49f57008, 0x29106809, 0xf8dfd90b, 0xf89ee3dc, 0xf1bee000, 0xd1040f01, 0xe000f892, 0x0f05f1be, 
+    0xf892d008, 0xf1bee000, 0xd00c0f03, 0x2b01781b, 0xe014d004, 0x2b01781b, 0x4665d111, 0xd30e2923, 
+    0xb123783b, 0x2203e00b, 0x00409600, 0x49e7e00c, 0xf5b18809, 0xd0117fea, 0x7ffaf5b1, 0xf00ed00e, 
+    0x960002ff, 0x0040eb05, 0x2100783b, 0xf00cb240, 0x4649fcd3, 0xf7f04650, 0xe019f992, 0x0040eb0c, 
+    0x21019600, 0x02fff00e, 0xe7f0b240, 0xf7f72002, 0x2801f9e1, 0x4cd6d009, 0xf01b4620, 0xf440fb25, 
+    0x46207180, 0xfb23f01b, 0xf7f6e005, 0x8020fbc1, 0x28008820, 0xf9b8d1ea, 0xb0031000, 0x42a0f04f, 
+    0x0000f640, 0x4ff0e8bd, 0xb9abf7f0, 0x43fee92d, 0xf00b2400, 0x49c7fe99, 0xf01b48c7, 0x2801f8f7, 
+    0x0900f640, 0x21e2d01a, 0x4648464c, 0xf94bf7f0, 0x46202100, 0xf936f7f0, 0x01d0f242, 0xf7f04620, 
+    0x48bef94e, 0x28017800, 0x2100d07d, 0xb00348bc, 0x312ef201, 0x43f0e8bd, 0xbae9f01b, 0x78284db1, 
+    0xf84ff7fe, 0x49b74eb4, 0xf3c079f0, 0x700800c0, 0xd0692800, 0x0170f242, 0xf7f006c8, 0x2000f930, 
+    0xfe26f7f7, 0x3000f44f, 0x0103f640, 0xf91bf7f0, 0xfd12f7fc, 0x4fac7a31, 0xf0017a70, 0xea400103, 
+    0x28402001, 0xd94f8038, 0xf7f72002, 0x4601f96d, 0xf8df48a6, 0x680082a0, 0x49a51a43, 0x2000f9b1, 
+    0xf1f2fbb3, 0xf8c81cc9, 0x1e891000, 0xf7f74351, 0x488bf9a9, 0x46322601, 0x88397006, 0xf8b84f89, 
+    0xf8df0000, 0x1a088224, 0x20008038, 0xe9d89002, 0xe9cd1004, 0x46311000, 0xf7f64630, 0x4983fb5d, 
+    0x3cfff04f, 0x4b854a82, 0x70107808, 0x4a844881, 0x70087800, 0x68094980, 0xd90b2910, 0xe208f8df, 
+    0xe000f89e, 0x0f01f1be, 0xf892d104, 0xf1bee000, 0xd00a0f05, 0xe000f892, 0x0f03f1be, 0x781bd00e, 
+    0xd0062b01, 0xe049e016, 0x781be046, 0xd1112b01, 0x29234664, 0x782bd30e, 0xe00bb123, 0x96002203, 
+    0xe00c0040, 0x88094971, 0x7feaf5b1, 0xf5b1d00d, 0xd00a7ffa, 0x02fff00e, 0xeb049600, 0x782b0040, 
+    0xb2402100, 0xfbe8f00c, 0xeb0ce019, 0x96000040, 0xf00e2101, 0xb24002ff, 0x2002e7f4, 0xf8faf7f7, 
+    0xd0092801, 0x46204c62, 0xfa3ef01b, 0x0180f040, 0xf01b4620, 0xe005fa3c, 0xfadaf7f6, 0x88388038, 
+    0xd1ea2800, 0x1000f9b8, 0x42a0f04f, 0x46484644, 0xf8c7f7f0, 0x80202007, 0x83fee8bd, 0x7110f242, 
+    0xe92de734, 0xf00b41f0, 0x4952fdaf, 0xf01b4852, 0x4e52f80d, 0xf6402801, 0xd0170500, 0x462821e2, 
+    0xf861f7f0, 0x46282100, 0xf84cf7f0, 0x01d0f242, 0xf7f04628, 0x7830f864, 0xd03f2801, 0x48482100, 
+    0x41f0e8bd, 0x714bf501, 0xba01f01b, 0x7800483d, 0xff67f7fd, 0xf04f4c34, 0x462842a0, 0x1000f9b4, 
+    0xf88ff7f0, 0xf04f483c, 0x4a430702, 0x79014d43, 0x701009c8, 0x7830d001, 0x7830b138, 0xd11b2801, 
+    0xf00e2004, 0x7028f863, 0xf3c1e015, 0x493c1002, 0x20047008, 0xf85af00e, 0x7028b2c0, 0xb9517831, 
+    0x78094938, 0x42901c8a, 0x702ad901, 0x1e89e003, 0xda004288, 0x80277029, 0x81f0e8bd, 0x7110f242, 
+    0xe92de7bd, 0x481c4ffe, 0x28126800, 0x2100d304, 0x1080f44f, 0xf8b0f7f7, 0x2601482b, 0xf04f4f2b, 
+    0xf8df0900, 0x4c108060, 0xf8877006, 0xf8989000, 0x28010000, 0x2802d004, 0x2000d002, 0xe0844601, 
+    0xf8df4d0f, 0x7828a08c, 0xd1052805, 0x46502201, 0xf01b2102, 0xbbe8f9c4, 0x28047828, 0xe03ad143, 
+    0x0004026f, 0x00040276, 0x000426e8, 0x00040259, 0x0004025a, 0x00040257, 0x00040240, 0x0004237a, 
+    0x00040292, 0x000425f9, 0x0004230e, 0x00042576, 0xf203517c, 0x0002ec30, 0x000434d0, 0x0004257a, 
+    0xf23c80ba, 0x00040270, 0x00040278, 0x00040280, 0x00042608, 0x0004258c, 0x00040262, 0x00040255, 
+    0x0004025b, 0x00040256, 0x0004024e, 0x000425e3, 0xf38e007c, 0x2200e005, 0x21014650, 0xf97ff01b, 
+    0x2001b108, 0x2000e000, 0x17c101c0, 0x0104e9c4, 0x0000f898, 0xd1222801, 0xf8df7828, 0x2805844c, 
+    0x2206d105, 0x21404640, 0xf969f01b, 0x7828b940, 0xd1072804, 0x46402205, 0xf01b2120, 0xb108f960, 
+    0xe0002001, 0xe9d42000, 0x01412304, 0x431117c8, 0xe9c44318, 0x703e1004, 0x0140f041, 0xe9d46121, 
+    0x02090104, 0x6110ea41, 0x22000200, 0x0104e9c4, 0x9008f8cd, 0x0104e9d4, 0x0100e9cd, 0x46112001, 
+    0xf9daf7f6, 0x49fa48f9, 0x70087800, 0x8ffee8bd, 0x4ffee92d, 0x8e804604, 0xf2404df6, 0xf5b01b1f, 
+    0xd07d7f81, 0x28d5dc1b, 0xdc0fd038, 0x28a6b368, 0x28a7d03f, 0x28d4d047, 0x6868d173, 0xf1052200, 
+    0xf0150108, 0x1d40fee8, 0xe027d06c, 0xd06a28e6, 0xd02328e7, 0xd06728ee, 0xd16228ef, 0x4558e01e, 
+    0x111ff2a0, 0xdc11d01a, 0x001cf111, 0x2813d016, 0x2814d07c, 0x281bd012, 0x49ded153, 0x68682200, 
+    0xf0153108, 0x1d40fec8, 0xe007d071, 0xd06f2907, 0xd0032908, 0xd06c2911, 0xd1422912, 0xf04f49d5, 
+    0x686832ff, 0xf0153108, 0x1d01fee5, 0x20a6d107, 0x49d0e153, 0x68682200, 0xf0153108, 0x1d41fedb, 
+    0x2801d03b, 0x4ecbd1ea, 0xf6402700, 0x36080000, 0x1000f9b6, 0xd032290f, 0x831cf8df, 0xf04f2913, 
+    0xf04f42a0, 0xf04f0901, 0xd02e0a03, 0xd1d5290a, 0x1000f9b5, 0xd05a2901, 0xd07b2903, 0xd0752902, 
+    0xd0742904, 0xd0732905, 0xd0722906, 0xd1c52907, 0xf933f000, 0x8030200b, 0x80282009, 0xe0041e7a, 
+    0xe0f1e0ae, 0xe056e041, 0x48b4e079, 0x68004631, 0xfe71f015, 0xd0711d01, 0x20a7e10b, 0xf04fe10d, 
+    0xf7ef4225, 0x802fff0e, 0x4bade7a8, 0x3000f993, 0xd0032b03, 0xd0012b05, 0xd1022b04, 0x781b4ba9, 
+    0x210ab143, 0xf7ef802f, 0xe797fefc, 0xe0c9e0a9, 0xe0e7e0da, 0x4220f04f, 0xfef3f7ef, 0xfe91f7ff, 
+    0x0000f898, 0xf8a5b170, 0x200a9000, 0x22004999, 0x68688030, 0xf0153108, 0x1d01fe3e, 0xaf53f47f, 
+    0xe0da20d4, 0xa000f8a5, 0x20d5e7ef, 0xf7ffe0d5, 0x2002fe18, 0xfeeef7f6, 0x200ab108, 0x200fe000, 
+    0x8030498c, 0x68682200, 0xf0153108, 0x1d01fe24, 0x20e6d107, 0x4987e0c1, 0x68682200, 0xf0153108, 
+    0x1d40fe1a, 0x20e7d1b0, 0xe003e0b7, 0xe052e021, 0xe08ae072, 0xf954f000, 0xf7f62002, 0xb108fecb, 
+    0xe000200a, 0x497b200f, 0x22008030, 0x31086868, 0xfe01f015, 0xd1081d01, 0xe09e20ee, 0x4975e08f, 
+    0x68682200, 0xf0153108, 0x1d40fdf6, 0x20efd18c, 0xf7efe093, 0x4974fe96, 0xf8812201, 0x49739000, 
+    0x9000f881, 0xe9d59702, 0xe9cd0104, 0x21000100, 0xf7f64610, 0xf898f8b1, 0x28010000, 0x2004d00a, 
+    0x49648028, 0x68682200, 0xf0153108, 0x1d01fdd4, 0xe00bd003, 0xa000f8a5, 0xf240e7f3, 0xe06c1002, 
+    0x2200495c, 0x31086868, 0xfdc5f015, 0xd1a91d40, 0x1003f240, 0xf000e061, 0xf898f8c7, 0x28010000, 
+    0x2005d00a, 0x80284953, 0x68682200, 0xf0153108, 0x1d01fdb2, 0xe00ad002, 0xe7f32006, 0x1016f240, 
+    0x494ce04b, 0x68682200, 0xf0153108, 0x1d40fda4, 0xf240d188, 0xe0401017, 0xfc98f7ff, 0xf7f62002, 
+    0xb108fe59, 0xe000200a, 0x4942200f, 0x22008030, 0x31086868, 0xfd8ff015, 0xf47f1d01, 0xf240aec4, 
+    0xe02a101e, 0xb034f8a4, 0xf7ffe680, 0x4939fbed, 0x80282007, 0x68682200, 0xf0153108, 0x1d01fd7c, 
+    0xf240d108, 0xe0181026, 0x22004932, 0x31086868, 0xfd71f015, 0xd1aa1d40, 0x1027f240, 0xf240e00d, 
+    0xe00a1030, 0x2200482d, 0x3108492a, 0xf0156800, 0x1d40fd62, 0xf240d19b, 0x86a01031, 0x2200e656, 
+    0xb5102101, 0x3057f2af, 0xfba0f015, 0x20032108, 0xfcfef015, 0x6048491f, 0x481ebd10, 0x42a0f04f, 
+    0xf640b510, 0xf9b00400, 0x46201000, 0xfde9f7ef, 0x2101f240, 0xf7ef4620, 0x481dfd96, 0x4a1e2400, 
+    0x80c4491e, 0x80448084, 0x481a8004, 0x48187803, 0xff78f7f8, 0xf44f2172, 0xf7ef0080, 0x4810fdac, 
+    0x28057800, 0x4816d107, 0x28017800, 0x2101d103, 0xf00d4608, 0x4813fbc7, 0x70042100, 0x3080f44f, 
+    0x4010e8bd, 0xbe18f7f6, 0xf38e0040, 0x0004025b, 0x0004025c, 0x000426e8, 0x0004257a, 0x0004274c, 
+    0x00040292, 0x00042300, 0x00040261, 0x0004025d, 0x000425b0, 0x0004232e, 0x00042598, 0x000425c6, 
+    0x0004230e, 0x000425ce, 0x4c41b5fe, 0x0600f640, 0x42a0f04f, 0xf9b44630, 0xf7ef1000, 0x10b1fd92, 
+    0xf7ef4630, 0x493bfd40, 0x4d3c2001, 0x70082201, 0x78004839, 0x20007028, 0xe9d49002, 0xe9cd0104, 
+    0x46110100, 0xf7f54610, 0x4c35ffa7, 0x4f352203, 0x46382138, 0xf01a7823, 0x782bfef4, 0x21072200, 
+    0xf01a4638, 0x7829feee, 0xf7ef4630, 0x7821fd0b, 0xf7ef4630, 0xe8bdfd07, 0x482b40fe, 0xbee3f7f8, 
+    0x41f0e92d, 0xfa50f00b, 0x48294928, 0xfcaef01a, 0x28014c28, 0x0600f640, 0x21e2d017, 0xf7ef4630, 
+    0x2100fd02, 0xf7ef4630, 0xf242fced, 0x463001d0, 0xfd05f7ef, 0x28017820, 0x2100d026, 0xe8bd481e, 
+    0xf20141f0, 0xf01a312d, 0x481cbea2, 0xf7fd7800, 0x4d17fc08, 0x09c179a8, 0x70014819, 0x4f0cd011, 
+    0x42a0f04f, 0xf9b74630, 0xf7ef1000, 0x490afd2a, 0xf3c079a8, 0x70081002, 0x28017820, 0x2001d002, 
+    0xe4b98038, 0xe7fb2004, 0x7110f242, 0x0000e7d6, 0x000426e8, 0x0004025f, 0x00040256, 0x00040257, 
+    0x00040255, 0xf203501a, 0x000425a8, 0x0002ec30, 0x000434d0, 0x0004257a, 0xf23c80ba, 0x000425f9, 
+    0x0004025e, 0x4ff0e92d, 0xf649b087, 0xf04f4740, 0x48fe42c0, 0x1002f9b0, 0x0000f241, 0xfcf1f7ef, 
+    0xa3ecf8df, 0x4900f04f, 0xf04f4cfa, 0x4dfa0800, 0x0000f89a, 0xd1362804, 0xbba07820, 0xb9087828, 
+    0xfa63f7fc, 0xb3d4f8df, 0x21012600, 0x8010f8cd, 0x460b200e, 0x1802e9cd, 0x46029000, 0xf8cd4601, 
+    0x90018014, 0x1000f240, 0xfb98f7f7, 0x01c0f242, 0xf7ef4648, 0x2e01fc84, 0x48e8dd11, 0xfda1f7f8, 
+    0x1000f8db, 0x42b94658, 0x6841d209, 0xd20642b9, 0x42b96881, 0xf8dbd203, 0x42b8000c, 0x1c76d303, 
+    0x2e10b236, 0x49dedbd1, 0x22012000, 0x8000f881, 0xe9cd4611, 0x46100000, 0x8008f8cd, 0xfeccf7f5, 
+    0xf6404ed8, 0x46400800, 0xf7f67831, 0xf242fcf5, 0x46480b80, 0xf7ef4659, 0xf99afc52, 0x46571000, 
+    0xd01d2902, 0x48d0b1f9, 0xd00d2903, 0xd0142904, 0xd00c2903, 0xd10d2904, 0x28017820, 0x2903d10a, 
+    0x2904d03d, 0xe047d042, 0x2a017802, 0x7800d008, 0xd0f42800, 0xe8bdb007, 0x78208ff0, 0xd1eb2800, 
+    0xf0032007, 0x7831fe05, 0xf7f64640, 0x4659fcc5, 0xf7ef4648, 0xf997fc24, 0x29031000, 0x2902d012, 
+    0x2904d010, 0x48b9d00e, 0x28116800, 0x7828d80a, 0xd1072801, 0xf8ad2047, 0x48b50000, 0x46686802, 
+    0xfefdf013, 0x28007828, 0xf7fcd1d4, 0x48b1fad4, 0x0000f990, 0xe8bdb007, 0xf7fc4ff0, 0x204ab811, 
+    0x0000f8ad, 0xf0134668, 0xe005fcde, 0xf8ad204d, 0x46680000, 0xf8eef014, 0xf0032007, 0x7831fdc9, 
+    0xf7f64640, 0xe7b5fc89, 0x4ffee92d, 0x250048a2, 0x4f97499b, 0x20017005, 0xf9977008, 0xb1580000, 
+    0x4c9e2120, 0x7680f04f, 0x1af4f240, 0x499c8021, 0x29047809, 0xe012d003, 0x2100f240, 0xb170e7f1, 
+    0x46512010, 0x46308020, 0xfbbdf7ef, 0x31baf64b, 0xf7ef4630, 0x4993fba7, 0xf7ef4630, 0x4892fba3, 
+    0x28027800, 0x01c0d101, 0xf8df8020, 0xf8dbb220, 0x28100000, 0x2000d802, 0xf8aaf7f7, 0x95022100, 
+    0x46102201, 0x1100e9cd, 0xf7f54611, 0x2101fe15, 0xf7f72000, 0x7838fd65, 0x200fb910, 0xfdf1f7f5, 
+    0x0180f242, 0xf7ef0608, 0xf8dffb9a, 0xf8df81dc, 0x4c7e91c4, 0xf7f62002, 0x4605fbe7, 0x0000f997, 
+    0xd0022803, 0xd0042804, 0xf898e007, 0xb1580000, 0xf899e003, 0x28010000, 0x2000d006, 0xfcfef00a, 
+    0x28037838, 0xe021d004, 0xf00a2001, 0xe7f7fd6f, 0x46304651, 0xfb67f7ef, 0x41ccf64c, 0xf7ef4630, 
+    0x7a61fb51, 0xf7ef4630, 0x7a21fb4d, 0xf7ef4630, 0x79e1fb49, 0xf7ef4630, 0x4962fb45, 0xf7ef4630, 
+    0xf242fb41, 0x06080180, 0xfb59f7ef, 0x289279e0, 0x2002d1c0, 0xfba8f7f6, 0x1a287a22, 0xa12cf8df, 
+    0xf0027a61, 0x4d5a0203, 0x2102ea41, 0x2004f8da, 0xeba11a80, 0x80283010, 0xf7f72000, 0xe005f839, 
+    0xf00a2000, 0x8828fd33, 0x80281e40, 0x28018828, 0xf242d8f6, 0x060d0180, 0xf7ef4628, 0xf8dbfb30, 
+    0x28110000, 0x2003d803, 0xf8eaf00d, 0x2004e002, 0xf8e8f00d, 0x0180f242, 0x462846ab, 0xfb1ff7ef, 
+    0xf7f52001, 0xf997fd6e, 0x28030000, 0x2804d002, 0xe01dd004, 0x0000f898, 0xe019b120, 0x0000f899, 
+    0xd1152801, 0x25004f3b, 0xeb072400, 0x46211645, 0xf9364628, 0xf00d2014, 0x1c64fa91, 0x2c10b2e4, 
+    0x1c6dd3f5, 0x2d04b2ed, 0x2003d3ee, 0xfa97f00d, 0x0180f242, 0xf7ef4658, 0xf9bafaf2, 0xb0031002, 
+    0x42c0f04f, 0x0000f241, 0x4ff0e8bd, 0xbb29f7ef, 0x4ffee92d, 0xf9964e16, 0xb1380000, 0x49202410, 
+    0x7580f04f, 0x29047809, 0xe011d002, 0xe7f62440, 0x2408b170, 0x11f4f240, 0xf7ef4628, 0xf64bfac4, 
+    0x462831ba, 0xfaaef7ef, 0x46284916, 0xfaaaf7ef, 0x78004815, 0xd1002802, 0xf9962440, 0x4f0a0000, 
+    0x8010f8df, 0xd0292803, 0xe0252804, 0x00042700, 0x00042fcc, 0x000425e5, 0x0004257a, 0x000434e0, 
+    0x00040271, 0x00040293, 0x000425e3, 0x00040240, 0x00042fec, 0x00040298, 0x0004026f, 0x00040276, 
+    0x00040292, 0xdcba01f5, 0x000425ce, 0x000434d0, 0x00040278, 0x0004e278, 0xe006d003, 0xb1687838, 
+    0xf898e003, 0x28010000, 0x2000d008, 0xfc06f00a, 0x46b17830, 0x28034efd, 0xe022d004, 0xf00a2001, 
+    0xe7f5fc75, 0x11f4f240, 0xf7ef4628, 0xf64cfa6c, 0x462841cc, 0xfa56f7ef, 0x46287a71, 0xfa52f7ef, 
+    0x46287a31, 0xfa4ef7ef, 0x462879f1, 0xfa4af7ef, 0x462849ef, 0xfa46f7ef, 0x0180f242, 0xf7ef0608, 
+    0x49ecfa5e, 0xf01a48e9, 0x2801f9f1, 0x4cead054, 0x0700f241, 0x682021e2, 0x60201c40, 0xf7ef4638, 
+    0x6821fa42, 0xf7ef4638, 0xf242fa2d, 0x463801d0, 0xfa45f7ef, 0x11f4f240, 0xf7ef4628, 0xf64ffa34, 
+    0x46282111, 0xfa1ef7ef, 0x683178f0, 0x611ff360, 0xf7ef4628, 0x79f0fa17, 0xf3606871, 0x4628611f, 
+    0xfa10f7ef, 0x68b17af0, 0x611ff360, 0xf7ef4628, 0x7bf0fa09, 0xf36068f1, 0x4628611f, 0xfa02f7ef, 
+    0x462849cb, 0xf9fef7ef, 0x780048cc, 0xd07d2801, 0x48cb2100, 0x714cf501, 0xfbb9f01a, 0x49ca48c9, 
+    0xf0007800, 0xeb000007, 0xf8511000, 0x1c522020, 0x2020f841, 0x8ffee8bd, 0xb310f8df, 0x79f046ca, 
+    0x0140f3c0, 0x1000f88b, 0x0000f899, 0xf240b188, 0x462811f4, 0xf9e7f7ef, 0x21acf64a, 0xf7ef4628, 
+    0x79f1f9d1, 0xf7ef4628, 0x49b1f9cd, 0xf7ef4628, 0xf89bf9c9, 0x28010000, 0x46b1d1dc, 0x4eb47a70, 
+    0x1008f899, 0x0103f001, 0x2001ea40, 0xf89a8030, 0xb1a80000, 0x11f4f240, 0xf7ef4628, 0xf64af9c4, 
+    0x462821ab, 0xf9aef7ef, 0x46288831, 0xf9aaf7ef, 0x46284621, 0xf9a6f7ef, 0x4628499d, 0xf9a2f7ef, 
+    0x42a08830, 0x2002ddb6, 0xfa0ef7f6, 0x48a14601, 0x68004ca2, 0x49a01a43, 0x2000f9b1, 0xf1f2fbb3, 
+    0x60211cc9, 0x43511e89, 0xfa4cf7f6, 0x2001499c, 0x700846b3, 0x88218830, 0x499a1a40, 0x20008008, 
+    0x90022201, 0xe9cd4611, 0xe0000000, 0x4610e0e9, 0xfc02f7f5, 0x20002101, 0xfb52f7f7, 0xfbeaf7f8, 
+    0x0000f89a, 0xb9104656, 0xf7f5200f, 0xf242fbda, 0x06080180, 0xf983f7ef, 0xb9607830, 0x21004c8a, 
+    0xf994200c, 0xf7f82000, 0x2101fbdc, 0x2000f994, 0xf7f84608, 0x2002fc1c, 0xf9c6f7f6, 0xf9964604, 
+    0x46b20000, 0xd0022803, 0xd0032804, 0x7838e006, 0xe003b3f0, 0x0000f898, 0xd0432801, 0xf00a2000, 
+    0x2002fadd, 0xf9b0f7f6, 0x2008f899, 0xf8991a21, 0x464e0009, 0x91d4f8df, 0x0203f002, 0xea40465c, 
+    0xf8d92002, 0x1a892004, 0x3011eba0, 0x11f4f240, 0x0000f8ab, 0xf7ef4628, 0xf64bf936, 0x462831bb, 
+    0xf920f7ef, 0x46287a71, 0xf91cf7ef, 0x46287a31, 0xf918f7ef, 0x462879f1, 0xf914f7ef, 0x46284954, 
+    0xf910f7ef, 0x0000f89a, 0x28044655, 0xe000d014, 0xf44fe008, 0xf6403000, 0xf7ef0103, 0xf7fbf914, 
+    0xe009fd0b, 0xf00a2001, 0xe7bafb11, 0xf00a2000, 0x8820fb0d, 0x80201e40, 0x28018820, 0x7828d8f6, 
+    0xd1062804, 0xf64003c0, 0xf7ef0103, 0xf7fbf8fc, 0xf04ffcf3, 0xf2424a00, 0x465c0b80, 0x46564659, 
+    0xf7ef4650, 0x2004f8fc, 0xfebcf00c, 0x46304621, 0xf8f5f7ef, 0xf7f52001, 0xf995fb44, 0x28030000, 
+    0x2804d002, 0xe01cd003, 0xb1207838, 0xf898e019, 0x28010000, 0x4f3ed115, 0x24002500, 0x1645eb07, 
+    0x46284621, 0x2014f936, 0xf868f00d, 0xb2e41c64, 0xd3f52c10, 0xb2ed1c6d, 0xd3ee2d04, 0xf00d2003, 
+    0x4834f86e, 0x28027800, 0x0400d10b, 0x0103f640, 0xf8b9f7ef, 0xfcb0f7fb, 0xf01a482f, 0x492ffa5f, 
+    0x46596008, 0xf7ef4650, 0xf9b9f8ba, 0xf04f1002, 0x464c42c0, 0x0000f241, 0xf8f3f7ef, 0x8060200b, 
+    0xf242e6a8, 0xe6947110, 0x4820b53e, 0x0400f241, 0x42c0f04f, 0x1002f9b0, 0xf7ef4620, 0x2104f8e2, 
+    0xf7ef4620, 0x491ef890, 0x78094620, 0xf934f7f6, 0xf00c2000, 0x481bfff2, 0x0000f990, 0x2802b3a0, 
+    0x2803d03b, 0x2804d031, 0xe039d034, 0x000434d0, 0xdcba01f5, 0x0002ec30, 0x000402f8, 0x0004257a, 
+    0xf23c80ba, 0x00042fe8, 0x00043790, 0x00040272, 0x00040278, 0x00040280, 0x00042608, 0x0004258c, 
+    0x00040271, 0x00040276, 0x00040298, 0x00042700, 0x0004e278, 0x000425ce, 0xf000812c, 0x000425d0, 
+    0x00040293, 0x00042fcc, 0x48fce007, 0x28017800, 0xe005d003, 0x780048fa, 0x2003b910, 0xffeff00c, 
+    0x0180f242, 0xf7ef0608, 0x48f6f84a, 0x49f62400, 0x70044df6, 0x70082001, 0x2002e00e, 0xf89af7f6, 
+    0xd0092801, 0x46284df2, 0xf9def01a, 0x0140f040, 0xf01a4628, 0xe006f9dc, 0x46282200, 0xf01a2101, 
+    0x2800f9e7, 0x2100d1e9, 0x22019402, 0xe9cd4610, 0x46111100, 0xfa90f7f5, 0x403ee8bd, 0xb976f00a, 
+    0x5ff0e92d, 0x938cf8df, 0x0b00f04f, 0x465d465c, 0xf99946da, 0x28030000, 0x2804d002, 0xe007d004, 
+    0x780048d6, 0xe003b168, 0x780048d5, 0xd0082801, 0xf00a2001, 0x4fd8f983, 0x78382601, 0xd0042801, 
+    0x2001e02a, 0xf9f2f00a, 0xf899e7f5, 0xbb180000, 0xf7f848d2, 0x48d2f916, 0x78004ad0, 0x48d1b180, 
+    0x1000f990, 0x3002f990, 0x1021f852, 0x1023f842, 0x1001f990, 0x0003f990, 0x1021f852, 0x1020f842, 
+    0x200049c9, 0x3020f852, 0xd900428b, 0x1c402600, 0x2804b2c0, 0xb12ed3f6, 0x48c549c4, 0xff66f019, 
+    0xd0082801, 0x68204cc3, 0x60201c40, 0x0008f3c0, 0xd0772801, 0xf8dfe1c4, 0x49bf82f8, 0x0007f898, 
+    0x0080f3c0, 0x28007008, 0x49bcd06d, 0x0009f898, 0xc2f0f8df, 0xe2f0f8df, 0x700a0982, 0xf3c049b8, 
+    0x700a1201, 0x0103f000, 0x0281f3c0, 0xf88c48b7, 0xf88e2000, 0x78031000, 0xd1222b01, 0x0008f898, 
+    0x600af898, 0x000ff000, 0x0701f000, 0x2607ea46, 0x0740f3c0, 0x040ff366, 0x600bf898, 0x2607ea46, 
+    0x0780f3c0, 0x441ff366, 0x600cf898, 0xea4608c0, 0xf3662607, 0xf898050f, 0xea46600d, 0xf3602000, 
+    0x48a3451f, 0x42827800, 0x48a2d103, 0x42817800, 0x1e52d07e, 0xf0021e49, 0x07880703, 0xb31b0f06, 
+    0x1100f240, 0x1c48b2a2, 0xd101428a, 0x040ff360, 0x428a0c22, 0xf360d101, 0xb2aa441f, 0xd101428a, 
+    0x050ff360, 0x428a0c2a, 0xf360d101, 0xf999451f, 0x28020000, 0x2800d072, 0x2803d070, 0x2804d071, 
+    0xe076d074, 0xe133e13d, 0x100af898, 0x29802081, 0xf888d101, 0xf898000a, 0x2980100b, 0xf888d101, 
+    0xf898000b, 0x2980100c, 0xf888d101, 0xf898000c, 0x2980100d, 0xf888d101, 0xf999000d, 0x28020000, 
+    0xb320d025, 0xd1032803, 0x78004864, 0xd01e2801, 0x000af898, 0xf01b2108, 0x4241f827, 0xeb004876, 
+    0xf8241447, 0xf8981016, 0x2108000b, 0xf81cf01b, 0x0446eb04, 0x21084240, 0xf8988060, 0xf01b000c, 
+    0x4240f813, 0xf89880a0, 0x2108000d, 0xf898e04b, 0x2108000a, 0xf808f01b, 0x46314240, 0x4638b202, 
+    0xfe8cf00c, 0x000bf898, 0xf01a2108, 0xe000fffd, 0x4240e04d, 0x4638b202, 0xf00c1c71, 0xf898fe7f, 
+    0x2108000c, 0xfff0f01a, 0xb2024240, 0x1cb14638, 0xfe74f00c, 0x000df898, 0xe0592108, 0xe000e038, 
+    0x483ee004, 0x28017800, 0xe002d032, 0x7800483c, 0xb220b370, 0xf01a2109, 0x4241ffd7, 0xeb00484e, 
+    0x14201747, 0x1016f827, 0xf01a2109, 0xeb07ffcd, 0x42400446, 0x80602109, 0xf01ab228, 0x4240ffc5, 
+    0x142880a0, 0xf01a2109, 0x4240ffbf, 0x4b4380e0, 0x28017818, 0x483bd037, 0x0a01f04f, 0x4a3d493c, 
+    0x70087800, 0x78094938, 0x43087011, 0xe02ad029, 0x2109b220, 0xffa8f01a, 0x46314240, 0x4638b202, 
+    0xfe2cf00c, 0x21091420, 0xff9ef01a, 0xb2024240, 0x1c714638, 0xfe22f00c, 0x2109b228, 0xff94f01a, 
+    0xb2024240, 0x1cb14638, 0xfe18f00c, 0x21091428, 0xff8af01a, 0xb2024240, 0x1cf14638, 0xfe0ef00c, 
+    0x2001e7c5, 0x4e267018, 0x28017830, 0x481bd05b, 0x78004c24, 0x42887821, 0x4a19d155, 0x78134d22, 
+    0x4293782a, 0x4318d14f, 0x1c52d040, 0x7028b2d0, 0xd33e2804, 0xb000f885, 0x0000e048, 0x000425e3, 
+    0x000425e5, 0x0004026c, 0x0004026e, 0xf000801c, 0xf203517c, 0x00042fcc, 0x0004257a, 0x000434e0, 
+    0x0004232e, 0x00042598, 0x0001a02b, 0x0002ec30, 0x000434d0, 0x000402f8, 0x0004026d, 0x00040268, 
+    0x00040269, 0x0004026a, 0x0004026b, 0x0004230e, 0x00040264, 0x00040265, 0x0004e278, 0x0004027d, 
+    0x0004027c, 0x00040266, 0x00040267, 0x70302001, 0x2801e00c, 0x1c49d10a, 0x7020b2c8, 0xd3052804, 
+    0xb000f884, 0xf1bae002, 0xd0080f00, 0xe0042107, 0x780048fe, 0xd0022800, 0x48fd2108, 0xe8bd8041, 
+    0xf2419ff0, 0x21e20500, 0xf7ee4628, 0x6821fdfc, 0xf7ee4628, 0xf242fde7, 0x462801d0, 0xfdfff7ee, 
+    0x28017838, 0x2100d01d, 0xf20148f2, 0xf019312f, 0x48f1ff9e, 0x780049f1, 0x0007f000, 0x1000eb00, 
+    0x2020f851, 0xf8411c52, 0xf8992020, 0x28000000, 0x6820d1d5, 0xdbd2280a, 0x28017838, 0x2110d1cf, 
+    0xf242e7cb, 0xe7df7110, 0x48e1b5fe, 0x42c0f04f, 0x1002f9b0, 0x0000f241, 0xfe13f7ee, 0x25004ee0, 
+    0xb1687830, 0x0180f242, 0xf7ee0608, 0x48dafdc8, 0x780049da, 0x0007f000, 0x1000eb00, 0x5020f841, 
+    0x200149d8, 0x70084cdd, 0x700849d7, 0x700d49d7, 0x700d49d7, 0x700849d7, 0x700849d7, 0x0000f996, 
+    0xd0022803, 0xd0042804, 0x48d5e007, 0xb3e87800, 0x48d4e003, 0x28017800, 0x2000d043, 0xfb4ef00a, 
+    0xb24049ce, 0xfd45f7f4, 0xf00a2001, 0x49cbfb47, 0x3120b240, 0xfd3df7f4, 0xf00a2002, 0x49c7fb3f, 
+    0x3140b240, 0xfd35f7f4, 0xf00a2003, 0x49c3fb37, 0x3160b240, 0xfd2df7f4, 0x88a088e1, 0x0108f3c1, 
+    0x0008f3c0, 0x4101ea40, 0xf3c08860, 0x0fc20008, 0x04030412, 0x4210ea42, 0x43118820, 0xf3c09502, 
+    0x43030008, 0xea412201, 0xe00071d0, 0xe9cde009, 0x46113100, 0xf7f44610, 0x7830ffcf, 0xb1a84cb2, 
+    0xf8dfe01e, 0x2100c2c8, 0xeb0c2000, 0xeb041741, 0xf8371241, 0xf8223010, 0x1c403010, 0x2810b200, 
+    0x1c49dbf7, 0x2904b2c9, 0xe7c5d3ee, 0x0000f994, 0xf7f449a2, 0x4aa6fcee, 0x48a02104, 0xfdbcf019, 
+    0x0000f994, 0x40fee8bd, 0xbe72f009, 0x43f0e92d, 0xf241488f, 0xb0870900, 0x42c0f04f, 0x1002f9b0, 
+    0xf7ee4648, 0xf7f8fd6e, 0xf242f9fc, 0x06cf0150, 0xf7ee4638, 0x4897fd24, 0xf2422600, 0x78000570, 
+    0xd0132803, 0xf04f4c94, 0x4611020c, 0x28037820, 0x0df8d01a, 0xfb92f7f6, 0x462946a8, 0x4638463d, 
+    0xfd0df7ee, 0x78384f8d, 0xe012b188, 0xf2402300, 0x1e5a2000, 0x210e9600, 0xf7f69601, 0xf7fbfac8, 
+    0x4629fac4, 0xe03b4638, 0x0000f640, 0xf7fbe7e2, 0x2001fabc, 0xe9cd9604, 0x200c0602, 0x23019000, 
+    0x220e9605, 0x03589001, 0xf7f64611, 0x4646fbf7, 0x46284641, 0xfce3f7ee, 0xb9c87838, 0x2000f994, 
+    0xd0012a04, 0xd1132a05, 0x78004865, 0x2100b980, 0xf7f82001, 0x4c72f9c8, 0x200c2100, 0x2000f994, 
+    0xff2ff7f7, 0xf9942101, 0x46082000, 0xff6ff7f7, 0x220c2301, 0x200e4619, 0xfc9ff7f6, 0x46284631, 
+    0xfcbdf7ee, 0xf44f4867, 0xf7f731b8, 0x2800fded, 0xf240d010, 0x464c11f4, 0xf7ee4648, 0x4962fca4, 
+    0xf7ee4620, 0xb007fc8f, 0x49604620, 0x43f0e8bd, 0xbc88f7ee, 0xe8bdb007, 0x484583f0, 0x42c0f04f, 
+    0xf9b0b570, 0xf2411002, 0xf7ee0000, 0x4d53fcda, 0x78284c57, 0xf004b920, 0x7820fe33, 0xd10d07c0, 
+    0x28017828, 0xf004d104, 0x7820fe2b, 0xd10507c0, 0xfa6df7f8, 0x4070e8bd, 0xbea9f004, 0xe92dbd70, 
+    0x4c334ff0, 0xf04fb087, 0xf24142c0, 0xf9b40000, 0xf7ee1002, 0x4d41fcb6, 0x28017828, 0x4845d110, 
+    0xf44f7801, 0xf7f52080, 0x2000fd07, 0xf960f7f6, 0x3000f44f, 0x0103f640, 0xfc55f7ee, 0xf84cf7fb, 
+    0x4a00f04f, 0x0980f242, 0x46504649, 0xfc57f7ee, 0x27014839, 0xf04f260c, 0x68000800, 0xd2022811, 
+    0x28017828, 0x2301d111, 0x220d9600, 0x8010f8cd, 0x46110258, 0x7802e9cd, 0x8014f8cd, 0xf7f69601, 
+    0x4649fb4d, 0xf7ee4650, 0x2100fc3a, 0xf0082001, 0x7828f83d, 0xb1b846ab, 0x0000f994, 0x220d2301, 
+    0x46119600, 0x96019004, 0x7002e9cd, 0x02989005, 0xfb34f7f6, 0x46504649, 0xfc21f7ee, 0x0000f994, 
+    0xe9cd9004, 0xe0397002, 0x0000e040, 0x0004027d, 0x00042700, 0xf23c80ba, 0x00042fe8, 0x00043790, 
+    0x00042fcc, 0x0004024f, 0x0004026c, 0x00040264, 0x00040265, 0x00040266, 0x00040267, 0x00043350, 
+    0x000425e3, 0x000425e5, 0x00042590, 0x00043580, 0x000433d0, 0x00040284, 0x00040292, 0x0004257a, 
+    0x00040298, 0x000434e0, 0x77777771, 0xdcba01f5, 0x000402b4, 0x00040293, 0x00040240, 0x96002301, 
+    0x9601220e, 0x90054611, 0xe0500358, 0xf99df7fb, 0x780148f6, 0x3080f44f, 0xfc6ef7f5, 0x96002301, 
+    0x4645220d, 0x46110298, 0x7802e9cd, 0x8010f8cd, 0x8014f8cd, 0xf7f69601, 0x4649fad1, 0xf7ee4650, 
+    0x220efbbe, 0x0800f241, 0x23019600, 0x7502e9cd, 0x46404611, 0x96019504, 0xf7f69505, 0x4649fabf, 
+    0xf7ee4650, 0xf7fbfbac, 0x48e1f970, 0xb9907800, 0xb1807820, 0x20012100, 0xf895f7f8, 0x21004ddd, 
+    0xf995200c, 0xf7f72000, 0x2101fdfc, 0x2000f995, 0xf7f74608, 0xf994fe3c, 0x220e0000, 0x23019600, 
+    0x90044611, 0xe9cd9601, 0x90057002, 0xf7f64640, 0x46c8fa95, 0x46554649, 0xf7ee4650, 0x2100fb80, 
+    0xf0074608, 0x4641ff83, 0xf7ee4628, 0xf89bfb78, 0xf04f0000, 0x46d9020e, 0x0301f04f, 0xf9942800, 
+    0x96000000, 0x90044611, 0xe9cd9601, 0x90057002, 0x0358d030, 0xfa72f7f6, 0x46414644, 0xf7ee4628, 
+    0x48bdfb5e, 0x3190f44f, 0xfc8ef7f7, 0xf241b170, 0xf2400600, 0x463011f4, 0xfb45f7ee, 0x463049b7, 
+    0xfb30f7ee, 0x463049b6, 0xfb2cf7ee, 0xf8992301, 0x220c0000, 0x200e4619, 0xfb1ff7f6, 0xf44f2100, 
+    0xf7f51000, 0xb007fbd9, 0x46284621, 0x4ff0e8bd, 0xbb35f7ee, 0x0000f244, 0xe92de7cc, 0x4ea95ff0, 
+    0x42c0f04f, 0x0000f241, 0x1002f9b6, 0xfb69f7ee, 0x4900f04f, 0x0470f242, 0x46484621, 0xfb1ff7ee, 
+    0xf04f4fa1, 0x7838080e, 0xd17a2801, 0xf7f62000, 0x2300fb43, 0xf44f2211, 0xf04f3100, 0xf0194071, 
+    0x2001fcb9, 0xf804f7f6, 0xf0194898, 0x4998fca7, 0x29106809, 0x4997d801, 0x2100e000, 0xb24cf8df, 
+    0x4c8a46a2, 0xf1ab1a45, 0x46510b0c, 0xf7ee4648, 0x2000faf6, 0xffecf7f5, 0xfb1cf00a, 0xf500b1a0, 
+    0x78214080, 0xf7f61040, 0x488bfd22, 0x78232201, 0x1000f9b0, 0xf7f62000, 0x2001fdd4, 0xffd8f7f5, 
+    0xf44f7821, 0xe0052080, 0xf7f52001, 0x7821ffd1, 0x3080f44f, 0xfb70f7f5, 0x46582201, 0xf0192102, 
+    0x2801fc87, 0x4879d018, 0x21012200, 0xf0193808, 0x2801fc7f, 0x4875d010, 0xfc60f019, 0xd8c442a8, 
+    0xf7f52001, 0x7821ffb5, 0x2080f44f, 0xfb54f7f5, 0x28017838, 0xe014d00a, 0x46284d70, 0xfc54f019, 
+    0x0110f040, 0xf0194628, 0xe7e9fc52, 0xffdcf009, 0x486c496b, 0xfa3af019, 0xd0022801, 0x80702010, 
+    0xf8a6e48d, 0xe48a8002, 0x41ffe92d, 0x46204c66, 0xfc3af019, 0x46052300, 0x461a2101, 0xf0194620, 
+    0x2300fc50, 0x22074620, 0xf0192180, 0x4e5ffc4a, 0x4f5f221e, 0x46384631, 0xfcc6f7fc, 0xf7f74668, 
+    0x2301fc42, 0x22074620, 0xf0192180, 0x221efc3a, 0x46384631, 0xfcb8f7fc, 0xf7f7a802, 0x2000fc34, 
+    0xa902466e, 0x3010f936, 0x2010f931, 0xdd014293, 0x2010f826, 0xb2001c40, 0xdbf32804, 0x4a4e484d, 
+    0x7803494e, 0xf7f74630, 0x4629fc3d, 0xf0194620, 0xe8bdfbfe, 0xe92d81ff, 0x460c41f0, 0x22064948, 
+    0x1040eb01, 0x46802140, 0xfc19f019, 0x2c00b206, 0x2501db01, 0x2500e002, 0xb2044260, 0xea402010, 
+    0x46401145, 0xfbe3f019, 0xea402018, 0xe0051745, 0x46404639, 0xfbdbf019, 0xb2243c08, 0xdcf72c08, 
+    0x1045ea44, 0xf040b2c0, 0x46400110, 0xfbcff019, 0x4640b2b3, 0x41f0e8bd, 0x21402206, 0xbbe1f019, 
+    0x5fffe92d, 0x80bcf8df, 0x46052200, 0x4600f240, 0xf8454610, 0x1c520022, 0x2a04b212, 0x2700dbf9, 
+    0xf04f46b1, 0xf04f0a01, 0x23003bff, 0x2103465a, 0xe9cd4640, 0xe9cd6a00, 0xf00a9a02, 0x2400ffdb, 
+    0xfb044631, 0xeb08f006, 0xf00d0040, 0xf855f877, 0x44081024, 0x0024f845, 0xb2241c64, 0xdbef2c04, 
+    0xb23f1c7f, 0xdbe02f01, 0x9fffe8bd, 0x00040293, 0x00042fcc, 0x00040298, 0x000434e0, 0x77777772, 
+    0xdcba01f5, 0x00042700, 0x0004257a, 0xf000812c, 0x00040240, 0x01e84800, 0x0004257e, 0xf203517c, 
+    0x0002ec30, 0x000434d0, 0xf2030a00, 0x450f6429, 0x43e187ae, 0x0004232e, 0x00042598, 0x000425c6, 
+    0xf2030882, 0x00043a00, 0x4ff0e92d, 0xb0874cfa, 0x0b80f04f, 0xf0194620, 0x1ca6fb57, 0x46309006, 
+    0xfb52f019, 0x90054df5, 0xf0194628, 0x2300fb4d, 0x0100f248, 0x9004220f, 0xf0194630, 0x2300fb62, 
+    0x0100f244, 0x4620220e, 0xfb5bf019, 0x4620220c, 0x02912300, 0xfb55f019, 0x46282300, 0x461a2101, 
+    0xfb4ff019, 0x46282300, 0x21802207, 0xfb49f019, 0xf7ff48e3, 0x2301ff65, 0x22074628, 0xf0192180, 
+    0x48e0fb40, 0xff5cf7ff, 0x21004bdd, 0x460c4edd, 0x7c00f503, 0x46e0466f, 0x4021f84c, 0x2021f853, 
+    0x0021f856, 0xdb024282, 0x2021f847, 0xf847e001, 0x1c490021, 0x2904b209, 0x2401dbed, 0x46b1469a, 
+    0x23004dce, 0x46282207, 0xf0192180, 0xeb0afb1a, 0x46561004, 0xff34f7ff, 0x46282301, 0x21802207, 
+    0xfb0ff019, 0x1004eb09, 0xf7ff464f, 0x2500ff29, 0x46b946b2, 0x4646466f, 0xb2684659, 0xfeebf7ff, 
+    0x0184eb05, 0x0021f85a, 0x1021f859, 0xda004288, 0xf8574608, 0x42811025, 0xf847dd03, 0xf8460025, 
+    0x1c6d4025, 0x2d04b22d, 0x1c64dbe6, 0x2c10b224, 0x2400dbc6, 0x0024f836, 0xfb003810, 0xb201f00b, 
+    0xf7ffb260, 0x1c64fec8, 0x2c04b224, 0x48abdbf2, 0xf0199904, 0x48a8fabc, 0xf0199906, 0x48a6fab8, 
+    0x1c809905, 0xfab3f019, 0xe8bdb007, 0x48a68ff0, 0xf9b0b57c, 0xf04f1002, 0xf24142c0, 0xf7ee0000, 
+    0xf242f940, 0x06cd0170, 0xf7ee4628, 0x2100f8f8, 0xf7f50be8, 0x4c9df991, 0x29017821, 0x2100d103, 
+    0xf7f50ae8, 0xf242f989, 0x46280180, 0xf8e7f7ee, 0xf9904897, 0x2a052000, 0x4896d103, 0x28017800, 
+    0x4895d01f, 0x78034995, 0x2b014895, 0x4a95d01e, 0x2a057812, 0x2000d81c, 0x0006f8ad, 0x0002f8ad, 
+    0x0004f8ad, 0x0000f8ad, 0x4a90488f, 0x78034990, 0xf7f74668, 0x2172faa7, 0x0080f44f, 0xf8dbf7ee, 
+    0xf7ffe009, 0xf7ffff01, 0xe004fe1f, 0xd0082a03, 0xf7fc221e, 0x7820faf9, 0xd1012800, 0xfe75f7fa, 
+    0x4884bd7c, 0xe7f4221e, 0x47fce92d, 0x4d7d4882, 0x78287801, 0x2832b109, 0x4980d302, 0xb1017809, 
+    0x4e752101, 0x282d4c72, 0xf9947031, 0xd2011000, 0xd0232904, 0xd201284b, 0xd01f2905, 0xf8df2700, 
+    0xf24091e0, 0x23003800, 0x22084641, 0xf0194648, 0x7830fa48, 0xd0012801, 0xd05e2f00, 0xf04f4862, 
+    0xf9b042c0, 0xf2411002, 0xf7ee0000, 0x2000f8ba, 0xfd6ef7f5, 0x7800485d, 0xe009b110, 0xe7de2701, 
+    0x3000f44f, 0x0103f640, 0xf85df7ee, 0xfc54f7fa, 0x28017830, 0xf994d006, 0x28040000, 0x2805d019, 
+    0xe031d023, 0x28037820, 0x2301d12e, 0x22084641, 0xf0194648, 0xf240fa16, 0xf8ad1000, 0xf8ad0006, 
+    0xf8ad0002, 0xf8ad0004, 0x46680000, 0xf98ef7f7, 0x7828e01a, 0xd203280f, 0x2100220d, 0xe0112006, 
+    0x281e380f, 0x220bd210, 0x7828e003, 0xd203280f, 0x2100220d, 0xe0052003, 0x285f380f, 0x220bd204, 
+    0x20022100, 0xf854f7f9, 0x20012100, 0xfc2ef007, 0xf44f2100, 0xf7f52080, 0xe8bdf8bf, 0xb53e87fc, 
+    0xf04f4c31, 0xf24142c0, 0xf9b40000, 0xf7ee1002, 0x493cf858, 0x4a3c2000, 0x21027008, 0x22017011, 
+    0x0000e9cd, 0x90024611, 0xf7f44610, 0x4827fa75, 0x78004936, 0x1000f991, 0xd00f4308, 0x70202000, 
+    0x3040f640, 0x48226060, 0x0000f990, 0xd0072804, 0xd1022805, 0x6080f241, 0xbd3e6060, 0xe7ee2001, 
+    0x5000f642, 0xe92de7f8, 0x4d175ff0, 0x1265f240, 0x46048e81, 0x68ab4291, 0x1065f2a1, 0xdc7cd048, 
+    0x7f9bf5b1, 0xdc4dd075, 0x1211f240, 0xf2a14291, 0xd03d1011, 0xb3d9dc3d, 0xd06b29e0, 0xd06a29e1, 
+    0x7f88f5b1, 0x2200d168, 0xf1054618, 0xf013010c, 0x1d40ff62, 0xe092d070, 0xf2030800, 0xf2030a00, 
+    0x0004e2f8, 0x0004e3f8, 0x00042700, 0x0004257a, 0x00040292, 0x0004230e, 0x00042352, 0x450f6429, 
+    0x43e187ae, 0x0004257c, 0x0004232e, 0x00042598, 0x000425c6, 0x4361c7ae, 0x00042308, 0x00042309, 
+    0xf203e800, 0x0004026f, 0x0004024e, 0x00042fcc, 0x2813e007, 0x2814d07e, 0x281dd061, 0x281ed07b, 
+    0xe05cd12a, 0x1247f240, 0xf2a14291, 0xd0561047, 0xf110dc10, 0xd0520110, 0xd06d2907, 0xd04e2908, 
+    0xd119290f, 0x220049fb, 0xf0134618, 0x1d40ff14, 0xe044d07e, 0xd07c2807, 0xd0402808, 0xd10b281d, 
+    0x220049f4, 0xf0134618, 0x1d40ff06, 0xe036d072, 0xe126e003, 0xe045e03d, 0x2892e08b, 0xdc1cd02f, 
+    0xd0682871, 0x2845dc09, 0x2846d066, 0x2865d027, 0x2866d07e, 0xe022d17d, 0x2872e0ca, 0x287bd01f, 
+    0x287cd078, 0x2891d01b, 0x49e2d173, 0x46182200, 0xfee1f013, 0xd06e1d40, 0x28bbe011, 0xdc08d06c, 
+    0xd06a28a7, 0xd00a28a8, 0xd06728b1, 0xd16028b2, 0x28bce005, 0x28c7d003, 0x28c8d076, 0x49d5d159, 
+    0x32fff04f, 0xf01368a8, 0x1d01fef5, 0x20e0d106, 0x49d0e299, 0x46182200, 0xfeecf013, 0xd0591d41, 
+    0xd1ec2801, 0xf04f4fcb, 0xf2410800, 0xf9b70600, 0xe0021000, 0xe0bee0a6, 0x290fe0e9, 0xf8dfd04c, 
+    0x29149318, 0xa314f8df, 0x0b0af04f, 0x290ad04d, 0xf9b5d1d5, 0x29131002, 0x2901d07d, 0x2902d071, 
+    0x2910d070, 0x2911d06f, 0x2912d06e, 0xe004d06d, 0xe0f9e0eb, 0xe1c0e11b, 0x2903e17c, 0x290ed079, 
+    0x290fd078, 0x2606d077, 0xd0752904, 0xd0742906, 0xd0732907, 0xd0722908, 0xd0712909, 0x290a260b, 
+    0x290bd06f, 0xf7fed1ab, 0x200cfa1d, 0xe006803e, 0xe249e18c, 0xe1e1e1bf, 0xe1f8e22e, 0x8068e215, 
+    0x32fff04f, 0x463948a6, 0xf0136800, 0x1d01fe64, 0xe234d070, 0xe23620e1, 0x4226f04f, 0xf7ed4630, 
+    0xf8a5ff00, 0xe78a8002, 0xf999e223, 0x28030000, 0x2805d003, 0x2804d001, 0x489ad102, 0xb1287800, 
+    0xf8a5210d, 0xf04f8002, 0xe10742c0, 0x4220f04f, 0xf7ed4630, 0xf7fffee6, 0xf89afe82, 0x28030000, 
+    0x2013d014, 0xf8a78068, 0x2200b000, 0x68a84989, 0xfe31f013, 0xf47f1d01, 0xf240aecc, 0xe2021010, 
+    0xe029e009, 0xe056e041, 0xe081e06b, 0xe7e9200e, 0x1011f240, 0xf7ffe1f7, 0x2001fdd7, 0x497d8068, 
+    0x68a82200, 0xfe17f013, 0xd1101d01, 0x1024f240, 0xe083e1e9, 0xe107e09e, 0xe148e132, 0xe180e165, 
+    0xe1bce19f, 0x22004973, 0xf0134618, 0x1d40fe04, 0xf240d1a9, 0xe1d61025, 0xfd59f7ff, 0x80682002, 
+    0x2200496c, 0xf01368a8, 0x1d01fdf6, 0xf240d108, 0xe1c8102e, 0x4967e1ba, 0x46182200, 0xfdebf013, 
+    0xd1901d40, 0x102ff240, 0xf7ffe1bd, 0x4961fb16, 0x68a82200, 0xfddff013, 0xd1071d01, 0x1036f240, 
+    0x495ce1b1, 0x46182200, 0xfdd5f013, 0xd1cf1d40, 0x1037f240, 0xf000e1a7, 0x4956fa22, 0x68a82200, 
+    0xfdc9f013, 0xd1071d01, 0x103ef240, 0x4951e19b, 0x46182200, 0xfdbff013, 0xd1b91d40, 0x103ff240, 
+    0xf04fe191, 0x463042c0, 0xfe5bf7ed, 0xfa98f004, 0x80682012, 0x22004947, 0xf01368a8, 0x1d01fdac, 
+    0xae95f47f, 0x1046f240, 0xf240e17d, 0xe17a1047, 0xf9d4f000, 0x2200493f, 0xf01368a8, 0x1d01fd9c, 
+    0xf240d107, 0xe16e104e, 0x2200493a, 0xf0134618, 0x1d40fd92, 0xf240d18c, 0xe164104f, 0x0000f999, 
+    0xd0052803, 0xd1052805, 0x68004837, 0xd8012810, 0xf965f7ff, 0x80682004, 0x2200492e, 0xf01368a8, 
+    0x1d01fd7a, 0xae71f47f, 0x1064f240, 0xf240e14b, 0xe1481065, 0xf931f7ff, 0x7800482c, 0xd03c07c0, 
+    0xf7f42003, 0x2002ff45, 0xff42f7f4, 0xf7f42001, 0x2011ff3f, 0xff3cf7f4, 0xf7f42012, 0x2001ff39, 
+    0xfe03f7f4, 0xf7f42002, 0x2004fe00, 0xfdfdf7f4, 0xf7f52000, 0xf999ff99, 0x481d1000, 0xd0112904, 
+    0xd0132905, 0x88012903, 0xf441d014, 0xb2894180, 0x4100f441, 0x21148001, 0x42c0f04f, 0xf7ed4630, 
+    0xe66cfde0, 0xf4418801, 0xe7f07180, 0xf0418801, 0xe7ec0120, 0x0104f041, 0x200fe7e9, 0x49058068, 
+    0x68a82200, 0xfd27f013, 0xd1181d01, 0x10aaf240, 0x0000e0f9, 0x0004270c, 0x00040292, 0x00040284, 
+    0x0004274c, 0x00042300, 0x00040240, 0x000402b4, 0x000402b6, 0x220049d6, 0xf0134618, 0x1d40fd0c, 
+    0xf240d1cf, 0xe0de10ab, 0xf830f7ff, 0x0000f89a, 0xd0092803, 0x80682003, 0x220049cd, 0xf01368a8, 
+    0x1d01fcfa, 0xe016d00f, 0xf7f42002, 0x48c9fd9e, 0xf44f7801, 0xf7f41080, 0x2000fdef, 0xfa48f7f5, 
+    0xf8e0f00c, 0xf240e61b, 0xe0bc10ca, 0x220049c0, 0xf0134618, 0x1d40fce0, 0xf240d1a3, 0xe0b210cb, 
+    0xff62f7fe, 0x2200806e, 0x68a849b9, 0xfcd3f013, 0xd1071d01, 0x10d6f240, 0x49b5e0a5, 0x46182200, 
+    0xfcc9f013, 0xd18c1d40, 0x10d7f240, 0xf7fee09b, 0x2002fd07, 0xfd7ef7f4, 0x200ab108, 0x200fe000, 
+    0x49ab8038, 0x68a82200, 0xfcb5f013, 0xd1071d01, 0x10e0f240, 0x49a6e087, 0x46182200, 0xfcabf013, 
+    0xd1bf1d40, 0x10e1f240, 0xf000e07d, 0x48a2f88e, 0x28017800, 0x48a1d103, 0x28017800, 0x806ed00b, 
+    0x499b2200, 0xf01368a8, 0x1d01fc96, 0xadb2f47f, 0x10f6f240, 0x2008e067, 0xe7f18068, 0x10f7f240, 
+    0xf7fee061, 0x4896fc41, 0x28017800, 0x2009d009, 0x498f8068, 0x68a82200, 0xfc7df013, 0xd0031d01, 
+    0xf8a5e00a, 0xe7f4b002, 0x200cf240, 0x4988e04b, 0x46182200, 0xfc6ff013, 0xd18d1d40, 0x200df240, 
+    0xf7fee041, 0x2002f9e5, 0xfd24f7f4, 0x200ab108, 0x200fe000, 0x497e8038, 0x68a82200, 0xfc5bf013, 
+    0xd1071d01, 0x2016f240, 0x4979e02d, 0x46182200, 0xfc51f013, 0xd1861d40, 0x2017f240, 0xf7fee023, 
+    0x806ef8c3, 0x49722200, 0xf01368a8, 0x1d01fc44, 0xf240d107, 0xe0162020, 0x2200496d, 0xf0134618, 
+    0x1d40fc3a, 0xf240d18d, 0xe00c2021, 0x202cf240, 0x486ce009, 0x49662200, 0xf0136800, 0x1d40fc2c, 
+    0xf240d1bb, 0x86a0202d, 0x9ff0e8bd, 0x21012200, 0xf2afb510, 0xf01360cd, 0x2108fa69, 0xf0132003, 
+    0x495bfbc7, 0x6088390c, 0x485fbd10, 0x7800b5fe, 0x1e404a5f, 0xf0004e5f, 0x485c0103, 0x1241eb02, 
+    0x1e407800, 0x0f000780, 0x0140eb02, 0x0010f832, 0x88cc888b, 0x0008f3c0, 0xf3c38849, 0xf3c40308, 
+    0xf3c10408, 0xea430108, 0x0fcb4404, 0xea43041b, 0x431c4311, 0x4305040d, 0x74d0ea44, 0x2002e00e, 
+    0xfca8f7f4, 0xd0092801, 0x46304e4b, 0xfdecf018, 0x0120f040, 0xf0184630, 0xe006fdea, 0x46302200, 
+    0xf0182101, 0x2800fdf5, 0x2001d1e9, 0x46029500, 0xe9cd4601, 0xf7f34001, 0xbdfefe9f, 0x4c34b510, 
+    0x42c0f04f, 0x0000f241, 0xf9b43c0c, 0xf7ed1002, 0xf009fc68, 0xb110fcb5, 0x8060200e, 0x2010bd10, 
+    0x48368060, 0x78024936, 0x7842700a, 0x7882704a, 0x78c0708a, 0xe8bd70c8, 0xf0094010, 0xe92dbc12, 
+    0x4c2347f0, 0x42c0f04f, 0x0000f241, 0xf9b43c0c, 0xf7ed1002, 0xf7fbfc46, 0x2000fc67, 0xf8f8f7f5, 
+    0xf9904828, 0x1c400000, 0x2011d003, 0xe8bd8060, 0x4d2587f0, 0x0000f995, 0x17c11c40, 0x7191eb00, 
+    0x0103f021, 0x70281a40, 0xf7fa2000, 0x4f1ff8cb, 0xf8df2400, 0xf240907c, 0x4e1e2800, 0x2000f996, 
+    0xd0022a03, 0x07c07838, 0x7828d008, 0x4641b108, 0x4649e000, 0xf7fa4620, 0xe004f9df, 0x1000f995, 
+    0xf0164620, 0x1c64fc1f, 0x2c04b264, 0xe7cedbe6, 0x0004270c, 0x00040293, 0x0004027c, 0x0004027d, 
+    0x0004257a, 0x0004274c, 0x00040266, 0x00040267, 0x00043350, 0xf000801c, 0xf203517c, 0x00042598, 
+    0x00042590, 0x0004027e, 0x00042580, 0x000402b4, 0xfffffa00, 0x00040292, 0x48ffb5fe, 0x0400f242, 
+    0x42e0f04f, 0x1006f9b0, 0xf7ed4620, 0x2107fbda, 0xf7ed4620, 0x04a6fb88, 0x05a0f242, 0x46304629, 
+    0xfb8df7ed, 0x220048f5, 0x92007002, 0x2201e9cd, 0x46112201, 0xf7f34610, 0x4629fdef, 0xf7ed4630, 
+    0x4ceffb7e, 0x2000f994, 0x2a02b132, 0x2a03d00a, 0x2a04d008, 0xe010d006, 0xf7f52000, 0x2301f869, 
+    0xe006220c, 0xf7f52000, 0x48e6f863, 0x220d2301, 0x21017800, 0xf7f5200e, 0x4629fb40, 0xf7ed4630, 
+    0x7820fb5e, 0x48e0b930, 0x220e2300, 0x0100f244, 0xfd17f018, 0x200149dd, 0xbdfe7008, 0x4ffee92d, 
+    0xf2404cd7, 0xf24218f4, 0x78200b00, 0xd10d2803, 0x465d4641, 0xf7ed4658, 0xf243fb36, 0x46283199, 
+    0xfb20f7ed, 0x462849d2, 0xfb1cf7ed, 0x200149cb, 0x70082700, 0x700748cf, 0x0000f994, 0x2120b138, 
+    0x80114acd, 0x780949cd, 0xd0032904, 0xf240e005, 0xe7f52100, 0x2010b108, 0x48c98010, 0x28027800, 
+    0x01c0d101, 0x21008010, 0x22019702, 0xe9cd4610, 0x46111100, 0xfd80f7f3, 0xf7f52002, 0xf04ffcf5, 
+    0xf2424900, 0x46510a90, 0xf7ed4648, 0xf7f4fb08, 0x4db1f9fd, 0x80a849bb, 0xb1097809, 0xff5bf006, 
+    0xfacef7f4, 0x4eb87820, 0xd1222803, 0xf04f4641, 0x46407880, 0xfae7f7ed, 0x41ccf64c, 0xf7ed4640, 
+    0x7a71fad1, 0xf7ed4640, 0x7a31facd, 0xf7ed4640, 0x79f1fac9, 0xf7ed4640, 0x49a5fac5, 0xf7ed4640, 
+    0xf242fac1, 0x46480180, 0xfad9f7ed, 0x28037820, 0xb2c0d006, 0xd10d2804, 0x780048a4, 0xd1092801, 
+    0xf00b2003, 0x4898f88d, 0x220e2300, 0x0100f244, 0xfc87f018, 0xf7f32005, 0x4651fd14, 0xf7ed4648, 
+    0x2001fabe, 0xfcb2f008, 0x23017a31, 0x8260f8df, 0x7a70461a, 0x0103f001, 0xea404e96, 0x21022001, 
+    0x0000f8a8, 0xf0184630, 0x2300fc6c, 0x22014630, 0xf0182102, 0x2301fc66, 0x22004630, 0xf0184619, 
+    0xe007fc60, 0xf0082001, 0xf8b8fc91, 0x1e400000, 0x0000f8a8, 0x0000f8b8, 0xd8f32801, 0x78004886, 
+    0xd0072801, 0xd0052802, 0xf00b2005, 0x7820f84b, 0xe00bb120, 0xf00b2006, 0xe7f8f843, 0xb1287828, 
+    0x1e912201, 0xf7f42005, 0x702ffae5, 0x46514654, 0x4648464e, 0xfa73f7ed, 0x23014876, 0x21102204, 
+    0xf01830aa, 0x4873fc2e, 0x220f2301, 0x30d403d9, 0xfc27f018, 0x1004f9b5, 0xf7f42000, 0xf9b5fa18, 
+    0xf04f1006, 0x465842e0, 0xfa9bf7ed, 0x4621b003, 0xe8bd4630, 0xf7ed4ff0, 0xe92dba52, 0xf8df4ffe, 
+    0xf2428160, 0xf2400900, 0xf8981af4, 0x28030000, 0x4651d114, 0x4648464c, 0xfa35f7ed, 0x1199f241, 
+    0xf7ed4620, 0x485dfa1f, 0xfbdef018, 0x46204601, 0xfa18f7ed, 0x4620494e, 0xfa14f7ed, 0xf0082001, 
+    0x4957fc25, 0xf0184850, 0x2801f9c1, 0x4c55d029, 0x464d21e2, 0x1c406820, 0x46486020, 0xfa13f7ed, 
+    0x46286821, 0xf9fef7ed, 0x01d0f242, 0xf7ed4628, 0x483cfa16, 0x28017800, 0x2100d06c, 0xf201484a, 
+    0xf0183132, 0x4849fbb4, 0xf0007800, 0xeb000007, 0x48471100, 0x0081eb00, 0x1c496841, 0xe8bd6041, 
+    0x4e398ffe, 0x7780f04f, 0x79f04c42, 0x0001f000, 0xf8987020, 0xb1800000, 0x46384651, 0xf9e3f7ed, 
+    0x21acf64a, 0xf7ed4638, 0x79f1f9cd, 0xf7ed4638, 0x4927f9c9, 0xf7ed4638, 0x7820f9c5, 0xd1de2801, 
+    0x0000f998, 0x2410b128, 0x78094924, 0xd0022904, 0x2440e003, 0xb100e7f8, 0x49212408, 0x29027809, 
+    0x2440d100, 0x7a324d22, 0x7a7146c3, 0x0203f002, 0x2102ea41, 0xb1a08029, 0x46384651, 0xf9b3f7ed, 
+    0x21abf64a, 0xf7ed4638, 0x8829f99d, 0xf7ed4638, 0x4621f999, 0xf7ed4638, 0x490df995, 0xf7ed4638, 
+    0x8828f991, 0xddaa42a0, 0xf7f42002, 0x4601f9fd, 0xe0334819, 0x0000e0f6, 0x00042714, 0x00040273, 
+    0x00042fcc, 0x0004257a, 0xf2030416, 0x00040251, 0xdcba01f5, 0x00040271, 0x00040276, 0x00040292, 
+    0x000425ce, 0x000402cf, 0x000434d0, 0x000425e5, 0x00040278, 0xf203504c, 0x000425f9, 0xf203517e, 
+    0x0002ec30, 0x000402fc, 0xf23c80ba, 0x00042fe8, 0x00043790, 0x00040274, 0x00040280, 0x4ffe6800, 
+    0x49fc1a43, 0x2000f9b1, 0xf1f2fbb3, 0x60391cc9, 0x43511e89, 0xfa06f7f4, 0x200149f8, 0xf04f4af9, 
+    0x46440800, 0x48f67008, 0x8000f880, 0x88388829, 0x80111a09, 0x48f4b281, 0xfaf9f018, 0x94022100, 
+    0x46102201, 0x1100e9cd, 0xf7f34611, 0x2002fbb5, 0xfb2af7f5, 0x0a90f242, 0x4000f04f, 0xf7ed4651, 
+    0xf7f4f93e, 0x4ce9f833, 0x806049e9, 0xb1097809, 0xfd91f006, 0xf904f7f4, 0x0000f99b, 0x2803465f, 
+    0x2804d005, 0x48e3d10d, 0x28017800, 0x2003d109, 0xfee6f00a, 0x230048e0, 0xf244220e, 0xf0180100, 
+    0x2005fae0, 0xfb6df7f3, 0x465146d3, 0x4a00f04f, 0xf7ed4650, 0x2001f914, 0xfb08f008, 0x23017a31, 
+    0x461a7a70, 0x0103f001, 0xea404ed4, 0x80282001, 0x46302102, 0xfac5f018, 0x46302300, 0x21022201, 
+    0xfabff018, 0x46302301, 0x46192200, 0xfab9f018, 0x2001e005, 0xfaeaf008, 0x1e408828, 0x88288028, 
+    0xd8f62801, 0x780048c6, 0xd0072801, 0xd0052802, 0xf00a2005, 0x7838fea7, 0xe00cb120, 0xf00a2006, 
+    0xe7f8fe9f, 0xb1307820, 0x1e912201, 0xf7f42005, 0xf884f941, 0x465d8000, 0x46564659, 0xf7ed4650, 
+    0x48b1f8ce, 0x22042301, 0x38a42110, 0xfa89f018, 0x230148ad, 0x03d9220f, 0xf018387a, 0xf9b4fa82, 
+    0x20011002, 0xf873f7f4, 0x1006f9b4, 0x42e0f04f, 0xf7ed4648, 0x4629f8f6, 0xf7ed4630, 0x2006f8b0, 
+    0xe6ac80e0, 0x7110f242, 0xb570e698, 0xf0082001, 0x49a4fa9d, 0xf01848a4, 0x4ea4f839, 0xf2422801, 
+    0xd0260500, 0x21e24ca2, 0x1c406820, 0x46286020, 0xf889f7ed, 0x46286821, 0xf874f7ed, 0x01d0f242, 
+    0xf7ed4628, 0x7830f88c, 0xd0322801, 0x48992100, 0x3131f201, 0xfa2bf018, 0x78004897, 0x0007f000, 
+    0x1100eb00, 0xeb004895, 0x68410081, 0x60411c49, 0x488dbd70, 0xf3c079c0, 0x48911140, 0x48917001, 
+    0x28017800, 0x2900d1f4, 0x4c80d0f2, 0x42e0f04f, 0xf9b44628, 0xf7ed1006, 0x2106f8a4, 0xf7ed4628, 
+    0x7830f852, 0xd0022801, 0x80e02004, 0x2005bd70, 0xf242e7fb, 0xe7ca7110, 0x4ff0e92d, 0xb0874f73, 
+    0x42e0f04f, 0x0000f242, 0x1006f9b7, 0xf889f7ed, 0xf04f4c7d, 0x4d750b01, 0x78204e7c, 0x4876b1c8, 
+    0x4a762100, 0xf0007800, 0xeb000007, 0xeb021000, 0x60410080, 0xb9087828, 0xfdf7f7f9, 0x28027820, 
+    0x7828d02b, 0x7831b998, 0x3080f44f, 0xf8c4f7f4, 0x7828e00d, 0xf7f9b968, 0x7831fde8, 0x2000f44f, 
+    0xf8baf7f4, 0x0180f242, 0xf7ed0608, 0x7820f818, 0xf997b998, 0x23010001, 0x220e9004, 0x46119005, 
+    0xb002e9cd, 0x9000200c, 0x03989001, 0xff16f7f4, 0x0190f242, 0xf7ed06c8, 0x7828f802, 0xf99446a0, 
+    0x43081000, 0x485ad17b, 0xf7f62500, 0xf8dff91a, 0x4a57a164, 0x0000f89a, 0x4958b148, 0xf9914856, 
+    0xf8423002, 0xf9910023, 0xf8421003, 0x68110021, 0xf8522401, 0x42880024, 0x4601d201, 0x1c644625, 
+    0x2c04b264, 0xf44fdbf5, 0xf6403000, 0xf7ec0103, 0xf7f9ffca, 0x4c4afbc1, 0x46082100, 0x2000f994, 
+    0xfa75f7f6, 0xfd10f7f9, 0x46072203, 0x21384845, 0xf0187025, 0xf8dff994, 0xb1309110, 0x0000f899, 
+    0xd5020740, 0x0000f89a, 0x7025b3f0, 0x1438b239, 0xfc23f7f9, 0x2002493d, 0xb000f881, 0xfe41f7f9, 
+    0x0000f994, 0xfb78f7f9, 0x0000f994, 0xfbb8f7f9, 0x0000f994, 0xfc03f7f9, 0x22034832, 0xf0182138, 
+    0xb128f96e, 0x0000f899, 0xd5010740, 0xfec9f7f9, 0xfd5bf7f9, 0xf2427831, 0xf7f40000, 0x2100f82d, 
+    0xf7f62001, 0xf994fc80, 0x21002000, 0xf7f6200c, 0x2101f9e8, 0x2000f994, 0xf7f64608, 0xf998fa28, 
+    0x46440000, 0xe0002803, 0xd045e042, 0xd0472804, 0x0000e04a, 0x00042608, 0x0004258c, 0x00040273, 
+    0x00040271, 0x00040276, 0xf203519a, 0x00042714, 0x000402cf, 0x000425e5, 0xf2030416, 0xf203504c, 
+    0x000425f9, 0x0002ec30, 0x000434d0, 0x0004257a, 0x000402fc, 0xf23c80ba, 0x00042fe8, 0x00043790, 
+    0x00040252, 0x00040251, 0x00042fcc, 0x00040293, 0x000434e0, 0x0004232e, 0x00029395, 0x00042598, 
+    0x00040298, 0xf38f007c, 0x000402cd, 0x00040296, 0x780048fe, 0xe7797020, 0x780048fd, 0xe003b188, 
+    0x780048fc, 0xd00c2801, 0x220c2301, 0x200e4619, 0xff03f7f4, 0xb9207820, 0xf44f2100, 0xf7f30000, 
+    0xb007ffbb, 0x0190f242, 0xe8bd06c8, 0xf7ec4ff0, 0xe92dbf16, 0x4df04ffe, 0x8e804604, 0x1b0ff240, 
+    0x68ab28fe, 0xdc1bd07e, 0xd03928dd, 0xb370dc0f, 0xd04028b0, 0xd04828b1, 0xd17428dc, 0x46182200, 
+    0x010cf105, 0xfe97f012, 0xd06d1d40, 0x28eee028, 0x28efd06b, 0x28f6d024, 0x28f7d068, 0xe01fd163, 
+    0xf2a04558, 0xd01b110f, 0x28ffdc12, 0xf5b0d018, 0xd07d7f83, 0x0008f111, 0x2807d012, 0x49d6d153, 
+    0x46182200, 0xf012310c, 0x1d40fe76, 0xe007d071, 0xd06f2907, 0xd0032908, 0xd06c2911, 0xd1422912, 
+    0xf04f49cd, 0x68a832ff, 0xf012310c, 0x1d01fe93, 0x20b0d107, 0x49c8e15b, 0x46182200, 0xf012310c, 
+    0x1d41fe89, 0x2801d03b, 0x4fc3d1ea, 0xf2422600, 0x370c0000, 0x1000f9b7, 0xd032290f, 0xf04f2915, 
+    0xf04f0802, 0xf04f42e0, 0xf04f0a01, 0xd02e0903, 0xd1d5290a, 0x1006f9b5, 0xd07a2901, 0xd0792909, 
+    0xd0782902, 0xd0772903, 0xd0762904, 0xd0752905, 0xd1c52906, 0xfaf0f7ff, 0x8038200b, 0x80e82007, 
+    0xe0041e72, 0xe0f9e0b8, 0xe079e069, 0x48abe090, 0x68004639, 0xfe1ff012, 0xd0701d01, 0x20b1e113, 
+    0xf04fe115, 0xf7ec4227, 0x80eefebc, 0x4ba4e7a8, 0x3000f993, 0xd0032b03, 0xd0012b05, 0xd1022b04, 
+    0x781b4ba0, 0x2108b143, 0xf7ec80ee, 0xe797feaa, 0xe0d1e0b1, 0xe0efe0e2, 0x4220f04f, 0xf7ec4607, 
+    0x2105fea0, 0xf7ec4638, 0x2101fe4e, 0xf7f52000, 0x2004f805, 0xfc14f00a, 0x4f944893, 0xf9977800, 
+    0x43081000, 0x2000d013, 0x70684991, 0x46102201, 0x9000f881, 0x96022100, 0x1100e9cd, 0xf7f34611, 
+    0xf8a5f8ab, 0x7838a006, 0xd0022804, 0x2001e003, 0xf8a5e7ea, 0x210a8006, 0x2200487f, 0x8001300c, 
+    0x68a84601, 0xfdc7f012, 0xf47f1d01, 0x20dcaf2d, 0xe006e0bd, 0xe035e01e, 0xe077e058, 0x20dde08f, 
+    0xf7ffe0b5, 0x4974fdc9, 0x80e82009, 0x68a82200, 0xf012310c, 0x1d01fdb0, 0x20eed108, 0xe098e0a7, 
+    0x2200496d, 0x310c4618, 0xfda5f012, 0xd18d1d40, 0xe09c20ef, 0xf8abf000, 0x22004967, 0x8006f8a5, 
+    0x310c68a8, 0xfd97f012, 0xd1071d01, 0xe08e20f6, 0x22004961, 0x310c4618, 0xfd8df012, 0xd1861d40, 
+    0xe08420f7, 0xfe2df7ec, 0x22014962, 0xf8814610, 0x2100a000, 0xe9cd9602, 0x46111100, 0xf84cf7f3, 
+    0x22004955, 0x9006f8a5, 0x310c68a8, 0xfd73f012, 0xd1071d01, 0xe06a20fe, 0x2200494f, 0x310c4618, 
+    0xfd69f012, 0xd1c21d40, 0xe06020ff, 0xfd1df7ff, 0xf7f32002, 0xb108fe1f, 0xe000200a, 0x4946200f, 
+    0x22008038, 0x310c68a8, 0xfd55f012, 0xd1081d01, 0x1006f240, 0x4940e04b, 0x46182200, 0xf012310c, 
+    0x1d40fd4a, 0xf240d1a3, 0xe0401007, 0xfb55f7ff, 0xf7f32002, 0xb108fdff, 0xe000200a, 0x4936200f, 
+    0x22008038, 0x310c68a8, 0xfd35f012, 0xf47f1d01, 0xf240aebc, 0xe02a100e, 0xb034f8a4, 0xf7ffe4e1, 
+    0x492dfa3d, 0x80e82006, 0x68a82200, 0xf012310c, 0x1d01fd22, 0xf240d108, 0xe0181016, 0x22004926, 
+    0x310c4618, 0xfd17f012, 0xd1881d40, 0x1017f240, 0xf240e00d, 0xe00a1020, 0x22004820, 0x310c491e, 
+    0xf0126800, 0x1d40fd08, 0xf240d19d, 0x86a01021, 0x2200e4b7, 0xb5102101, 0x3069f2af, 0xfb46f012, 
+    0x20022108, 0xfca4f012, 0x60884913, 0x481abd10, 0x7800b510, 0x4815b1c8, 0xb9b07800, 0x78004817, 
+    0x480fb998, 0x28037800, 0x4815d102, 0xb1607800, 0xf04f4809, 0xf9b042e0, 0xf2421006, 0xf7ec0000, 
+    0x2000fd80, 0xfa34f7f4, 0xe027e01c, 0x000426a0, 0x000425e3, 0x000425e5, 0x00042714, 0x0004274c, 
+    0x00040292, 0x00042300, 0x0004257a, 0x00042fcc, 0x0004024e, 0x00040251, 0x0004230b, 0x0004232e, 
+    0x00042352, 0xf866f7f7, 0xfc68f7f6, 0xf7f42001, 0x2100fa0f, 0x1000f44f, 0xfdaef7f3, 0x0190f242, 
+    0x4010e8bd, 0xf7ec06c8, 0x0000bd0a, 0x41f0e92d, 0x0800f244, 0x4640210a, 0xfcf5f7ec, 0xf24f2307, 
+    0x220c0100, 0x46204cfe, 0xfea4f017, 0xf6402307, 0x22087100, 0xf0174620, 0x48fafe9d, 0x78014efb, 
+    0x290148f9, 0x7831d102, 0xd00a2905, 0xf0172104, 0x48f7fe8e, 0x78002400, 0x48f6b3a0, 0xb1107800, 
+    0x2108e012, 0x2100e7f3, 0xf7f62001, 0x4df2f9cc, 0x200c2100, 0x2000f995, 0xff33f7f5, 0xf9952101, 
+    0x46082000, 0xff73f7f5, 0x78284dec, 0xd1002801, 0xf2402401, 0xf04f11f4, 0x46387780, 0xfcb3f7ec, 
+    0x2122f249, 0xf7ec4638, 0xf995fc9d, 0x46381000, 0xfc98f7ec, 0x46384621, 0xfc94f7ec, 0x463849e0, 
+    0xfc90f7ec, 0x200d7831, 0xd1032905, 0x780949dd, 0x200fb901, 0x23011902, 0x000ef104, 0xf7f44619, 
+    0xf242fc7c, 0x06c801b0, 0xfc99f7ec, 0xe8bd4640, 0x210b41f0, 0xbc87f7ec, 0x4ff8e92d, 0x46044dd2, 
+    0xf5b08e80, 0x686b7fb5, 0xdc12d07d, 0xd07b28ec, 0xb318dc05, 0xd02c288c, 0xd176288d, 0x28ede033, 
+    0xf5b0d01c, 0xd0717f97, 0x7080f5a0, 0xd16c382f, 0xf5b0e014, 0xd06a7fbc, 0xf5a0dc08, 0x386b7080, 
+    0x2805d00c, 0x2806d07e, 0xe007d15f, 0x7080f5a0, 0xd0033879, 0xd076280d, 0xd156280e, 0xf04f49ba, 
+    0x686832ff, 0xf0123108, 0x1d01fc25, 0x208cd107, 0x49b5e235, 0x46182200, 0xf0123108, 0x1d41fc1b, 
+    0x2801d027, 0x4eb0d1ea, 0xf2442700, 0x36080900, 0x1000f9b6, 0xd01e290f, 0xf2422916, 0xf04f0ab0, 
+    0xd01f4800, 0x1000f9b5, 0xd07d2901, 0xd1d52902, 0x46420388, 0xfc75f7ec, 0xff28f7ff, 0x8030200b, 
+    0x1e7a48a2, 0x68004631, 0xfbc5f012, 0xd06c1d01, 0x208de201, 0xf04fe203, 0x46484228, 0xfc61f7ec, 
+    0xe7bb802f, 0xb244f8df, 0x0000f99b, 0xd00f2803, 0xd00d2805, 0xd00b2804, 0x46422103, 0x802f4648, 
+    0xfc4ff7ec, 0xe199e7aa, 0xe1e9e05e, 0xe1cfe14e, 0x4220f04f, 0x4648464e, 0xfc43f7ec, 0x46302109, 
+    0xfbf1f7ec, 0x46404651, 0xfbf9f7ec, 0x78304e88, 0xd0172801, 0xd0152802, 0xf00a2005, 0x4885f9b1, 
+    0xe0017800, 0xe1c0e198, 0xd00d2801, 0x200a802f, 0x2200497d, 0x80083108, 0xf0126868, 0x1d01fb7c, 
+    0xe037d030, 0xe7e82006, 0x487b2301, 0x0299220a, 0xfd97f017, 0xf7f42000, 0x4878f8cb, 0x28116800, 
+    0x2100d803, 0xf7f34648, 0xf89bfc67, 0x20081000, 0x29042300, 0x7831d10c, 0xd1092901, 0x20104970, 
+    0x29027809, 0xe001d104, 0xe18be018, 0x23012004, 0x7809496c, 0x21019100, 0xf7f87832, 0x2001fef5, 
+    0xe7c48028, 0xe18a20ec, 0x2200495f, 0x31084618, 0xfb41f012, 0xd1841d40, 0xe18020ed, 0x01b0f242, 
+    0xf7ec06c8, 0x46b8fb9c, 0x48604f5f, 0x8000f887, 0xf2427801, 0xf7f30000, 0x4857fc2f, 0x21202205, 
+    0xf017300a, 0xf8dffd5c, 0xb2c0b168, 0x70382801, 0x4851d068, 0x21202205, 0xf017300a, 0xf8dffd50, 
+    0xb2c0a144, 0xf89a7038, 0xb1b11000, 0xd0592801, 0xf6414849, 0x220071ff, 0x30ba460b, 0xfd31f017, 
+    0x7801484a, 0x0000f248, 0xfc06f7f3, 0x22054842, 0x300a2120, 0xfd33f017, 0xb2c07038, 0xd0412801, 
+    0x46482198, 0xfb4ff7ec, 0x68004842, 0x2000b188, 0xf84ef7f4, 0x01b0f242, 0xf7ec06c8, 0x482dfb50, 
+    0x3190f240, 0x8000f8a5, 0x78024b3b, 0xf7f31e48, 0x483afc15, 0xfc65f7f5, 0x1000f89a, 0xb1814837, 
+    0xf9914937, 0xf9912000, 0xf8503002, 0xf8402022, 0xf9912023, 0xf9912001, 0xf8501003, 0xf8402022, 
+    0xe9d02021, 0xe9d03200, 0x189f1002, 0x0c00eb01, 0xf64f4467, 0xebbc5ce8, 0xd9720f97, 0xd9724293, 
+    0xe071461f, 0x4200f04f, 0x1000f9b5, 0xf7ec0c10, 0x4824fb58, 0xfcb2f017, 0x20024607, 0xfb64f7f3, 
+    0xf89b1a39, 0xf0000000, 0xeb000007, 0x481e1200, 0x0082eb00, 0x20026281, 0x481c8028, 0xe0376801, 
+    0xf100004c, 0x0004230e, 0xf2031034, 0x00040292, 0x00042fcc, 0x0004257a, 0x00040298, 0x00043010, 
+    0xdcba01f5, 0x000402cf, 0x00042728, 0x0004274c, 0x000425f9, 0x00040251, 0xf2035022, 0x00040240, 
+    0x00042383, 0x0004232e, 0x0004027b, 0x00040293, 0x00042fe8, 0x00057f70, 0xf23c80ba, 0x000434e0, 
+    0x00042598, 0xf0008128, 0x00043790, 0x00057f84, 0x60011c49, 0x8030200a, 0x2200495a, 0xf0126868, 
+    0x1d01fa5a, 0xf240d107, 0xe098102e, 0x22004955, 0xf0124618, 0x1d40fa50, 0xae3af47f, 0x102ff240, 
+    0xe014e08d, 0x4617e7ff, 0xd9014281, 0xe000468c, 0x45674684, 0x4293d905, 0x4618d901, 0x4610e004, 
+    0x4281e002, 0x4608d900, 0x42884947, 0x4847d94e, 0xb3707800, 0xf9b14946, 0x28140000, 0x1c40da2a, 
+    0xf89b8008, 0x22000000, 0xf0001c40, 0xeb000007, 0x48401100, 0x0081eb00, 0xf5016881, 0x60816180, 
+    0x8000f8a5, 0x8030203f, 0x4936483b, 0xf0126800, 0x1d01fa12, 0xf240d108, 0xe050106a, 0x22004836, 
+    0x68004930, 0xfa07f012, 0xd1b51d40, 0x106bf240, 0xe7ffe045, 0xf7f32002, 0xb108fabd, 0xe000200a, 
+    0x8030200f, 0x22004927, 0xf0126868, 0x1d01f9f4, 0xf240d107, 0xe0321070, 0x22004922, 0xf0124618, 
+    0x1d40f9ea, 0xf240d198, 0xe0281071, 0xf7f32002, 0xb108faa1, 0xe000200a, 0x8030200f, 0x22004919, 
+    0xf0126868, 0x1d01f9d8, 0xf240d107, 0xe0161078, 0x22004914, 0xf0124618, 0x1d40f9ce, 0xf240d1c5, 
+    0xe00c1079, 0x1086f240, 0x4814e009, 0x490d2200, 0xf0126800, 0x1d40f9c0, 0xf240d1b7, 0x86a01087, 
+    0x8ff8e8bd, 0x21012200, 0xf2afb510, 0xf01140f3, 0x2108fffd, 0xf0122003, 0x4902f95b, 0x60483908, 
+    0x0000bd10, 0x00042730, 0x00013880, 0x00042fcc, 0x00042fd2, 0x00043790, 0x00043004, 0x0004274c, 
+    0x5ffce92d, 0xf248210c, 0xf7ec0000, 0x48faf9ec, 0x21042202, 0xfbc3f017, 0x2000b110, 0xfd25f7f4, 
+    0x93d8f8df, 0xf899464c, 0xf7f50000, 0x7820f900, 0xf966f007, 0xfaa5f007, 0xf6404ff1, 0x78380a04, 
+    0xf8dfbb78, 0xf04fb3c0, 0x46410800, 0x0000f89b, 0x0007f000, 0x1200eb00, 0xeb0048eb, 0x22010082, 
+    0x802cf8c0, 0xf7f42002, 0x2200ffcd, 0x46112001, 0xffc8f7f4, 0x48e52400, 0x46212301, 0x2644eb00, 
+    0x220048e3, 0x2544eb00, 0xe9cd4618, 0xf7f25600, 0x48e0f885, 0x68022100, 0x0074f8b2, 0x3076f8b2, 
+    0xe026e00b, 0x2010f835, 0xfc02fb12, 0x2010f836, 0xb2801c40, 0xc202fb12, 0x42834411, 0x48d6d2f2, 
+    0x23012200, 0x1024f840, 0xf84048d4, 0x48d41024, 0xeb0049d4, 0xeb012044, 0xe9cd2144, 0x46211000, 
+    0xf7f24610, 0x1c64f85b, 0x2c04b264, 0x7838dbc3, 0x4ccdb320, 0xf0174620, 0xea00fb27, 0x4620050a, 
+    0xfb22f017, 0x0680f000, 0xf0174620, 0xf400fb1d, 0x20045480, 0xff61f004, 0x46b87838, 0x2100b318, 
+    0xf0052001, 0x2000fd73, 0xfb46f005, 0xa2fcf8df, 0xf89a48bf, 0xb1e11000, 0xe01f2102, 0x8000f8cb, 
+    0xf8df4641, 0x268082f0, 0x465548bb, 0xf8c80174, 0xf0171000, 0xf8b8fafc, 0xb2810000, 0x301448b6, 
+    0xfaf5f017, 0x2101e7d5, 0xf0054608, 0x2001fd4f, 0x49b2e7da, 0x29017809, 0x2103d10a, 0x49b07001, 
+    0x20042200, 0xf9a6f7f3, 0xf7f3200b, 0x2400faa0, 0x78384fac, 0xf89ab920, 0xb1080000, 0xe0002001, 
+    0xf7f92000, 0x7838f8bc, 0x48a7b920, 0xb1087800, 0xe0002008, 0x43352000, 0x489b4305, 0xf4454325, 
+    0xf01761e0, 0x48a1fac4, 0xf0172100, 0xf898fac0, 0xb9200000, 0x2001499e, 0x499e7008, 0xf9997008, 
+    0x28030000, 0x2805d004, 0x2804d006, 0xe00fd004, 0x78004899, 0xd20b2841, 0xf2474894, 0x386a7185, 
+    0xfaa5f017, 0xf2414891, 0x38683114, 0xfa9ff017, 0xf7f82001, 0x4891ff49, 0x0000f990, 0xfd00f7f8, 
+    0x28017838, 0x2100d011, 0x8800488d, 0x0240eb00, 0x10c0ebc2, 0x5ffce8bd, 0x00c0eb01, 0x10e5f2a0, 
+    0x4879b281, 0xf0171c80, 0xf242ba82, 0xe7eb7110, 0x5ffce92d, 0x46044e83, 0xf04f4983, 0x8e800a00, 
+    0xf5b06873, 0x680d7f8f, 0xdc12d075, 0xd07328e2, 0xb318dc05, 0xd02c28b6, 0xd16e28b7, 0x28e3e033, 
+    0xf5b0d01c, 0xd0697f89, 0x7080f5a0, 0xd1643813, 0xf5b0e014, 0xd0727fdd, 0xf5a0dc08, 0x381f7080, 
+    0x2875d00c, 0x2876d06c, 0xe1e0d157, 0x7080f5a0, 0xd00338bb, 0xd0782821, 0xd14e2822, 0xf04f4969, 
+    0x687032ff, 0xf0123108, 0x1d01f865, 0x20b6d107, 0x4964e227, 0x46182200, 0xf0123108, 0x1d41f85b, 
+    0x2801d01f, 0x4d5fd1ea, 0x35082700, 0x1000f9b5, 0xd018290f, 0xf04f2917, 0xd0304210, 0x1000f9b6, 
+    0x0000f248, 0xf8bdf7ec, 0x0000f9b6, 0xb0f0f8df, 0xd0552801, 0xd1d12802, 0x7800484a, 0xd0682801, 
+    0x20b7e1e7, 0xf04fe1fd, 0xf2484229, 0xf7ec0000, 0x494ef8a8, 0x80374a4a, 0x68126808, 0xda014290, 
+    0x60081c40, 0xb2818808, 0x1c80483b, 0xf9fff017, 0x70074847, 0xe0fde7b2, 0xe1e3e028, 0x4827e0c7, 
+    0x0000f990, 0xd00c2803, 0xd00a2805, 0xd0082804, 0xf2482103, 0x80370000, 0xf883f7ec, 0xe1a1e79e, 
+    0xf04fe16d, 0xf2484220, 0xf7ec0000, 0x4935f87a, 0x80302001, 0x8028200a, 0x68702200, 0xf0113108, 
+    0x1d01ffca, 0x20e2d108, 0xe1b1e1bb, 0x2200492d, 0x31084618, 0xffbff011, 0xd1cb1d40, 0xe1b020e3, 
+    0x80b0f8df, 0x21022301, 0x4640461a, 0xf9d9f017, 0x46402300, 0x21022201, 0xf9d3f017, 0xf7f32002, 
+    0xf8dff998, 0xb1289094, 0x78004824, 0xd07d2801, 0xe171e107, 0x0000e044, 0xf3074084, 0x00040292, 
+    0x00042fcc, 0x00042fe8, 0x00043790, 0x00046200, 0x00045a00, 0x00042618, 0x00043330, 0x00043340, 
+    0x00047200, 0x00046a00, 0xf23c80b8, 0x000402cf, 0x000425f2, 0x00043014, 0xf203513e, 0x000402db, 
+    0x0ee6b280, 0x0004257a, 0x00043010, 0xf203086e, 0x00040296, 0x00040297, 0x0004257c, 0x00040298, 
+    0x00057f78, 0x00042738, 0x00043004, 0x00057f80, 0x00042e74, 0xf23c8314, 0x00042fd2, 0x0004254e, 
+    0x0000f99b, 0x82c0f8df, 0xb2c0f8df, 0xd0032804, 0xd0012802, 0xd1352803, 0x0000f9b9, 0xda312804, 
+    0x780148ab, 0x0000f242, 0xf846f7f3, 0x1000f8b9, 0x1c492200, 0x1000f8a9, 0x0000f898, 0xf0001c40, 
+    0xeb000007, 0xeb0b1100, 0x68810081, 0x6180f501, 0x80376081, 0x8028203f, 0x499e489f, 0xf0116800, 
+    0x1d01ff2a, 0xf240d108, 0xe11a1012, 0x4999e03d, 0x46282200, 0xff1ff011, 0xf47f1d40, 0xf240aec9, 
+    0xe10e1013, 0x68004895, 0x4896b148, 0x319bf240, 0x4b938037, 0x1e487802, 0xf840f7f3, 0xf898e6ce, 
+    0x22000000, 0xf0001c40, 0xeb000007, 0xeb0b1100, 0x68810081, 0x7100f501, 0x80376081, 0x80282009, 
+    0x49844889, 0xf0116800, 0x1d01fef6, 0xf240d108, 0xe0e6101e, 0x22004884, 0x6800497e, 0xfeebf011, 
+    0xd1db1d40, 0x101ff240, 0xf89be0db, 0xbbe00000, 0xf7f5487e, 0xf8dff866, 0x220081f8, 0x0000f248, 
+    0x1000f8d8, 0xff7df7eb, 0x7801487a, 0xb1814877, 0xf9914979, 0xf9912000, 0xf8503002, 0xf8402022, 
+    0xf9912023, 0xf9912001, 0xf8501003, 0xf8402022, 0x25002021, 0x81b4f8df, 0xf2482200, 0xf8580000, 
+    0xf7eb1025, 0x496dff5e, 0x4a6d2000, 0xe9cd4b6d, 0xf8580100, 0xf7eb0025, 0x4602febd, 0x68004864, 
+    0xd20a4282, 0x80374968, 0xe00ae000, 0x0000f248, 0xff47f7eb, 0x0a01f04f, 0x1c6de660, 0x2d04b2ed, 
+    0xf1bad3d8, 0xd1890f00, 0x7000f8a9, 0x0000f89b, 0x495eb138, 0x1c406808, 0xb2816008, 0xf017485c, 
+    0xf7f8f896, 0x4d5bfa88, 0x78292001, 0xfa31f7f4, 0xf9954959, 0x70080000, 0x88094958, 0x4958b1b9, 
+    0x800a2273, 0x708a2201, 0x70c82200, 0x68004855, 0xfe71f011, 0xd1081d01, 0x1094f240, 0x4851e061, 
+    0x494f2200, 0xf0116800, 0x1d40fe66, 0x484ed024, 0xf86af017, 0x484d2301, 0x03d9220f, 0xf881f017, 
+    0xf936f7ed, 0xf7f32002, 0x2100f822, 0xf7f52008, 0x2001fb04, 0xfb49f7f5, 0xf7f52001, 0x2002fb28, 
+    0x482c8030, 0x2200210a, 0x46018001, 0xf0116870, 0x1d01fe42, 0xe00ad003, 0x1095f240, 0xf240e031, 
+    0xe02e10ba, 0x22004923, 0xf0114618, 0x1d40fe34, 0xf240d192, 0xe02410bb, 0x0000f89b, 0xf7f8b948, 
+    0xf44ffbf7, 0xf6403000, 0xf7eb0103, 0xf7f8fe7c, 0xf7fffa73, 0x203ffc85, 0x48178028, 0x49152200, 
+    0xf0116800, 0x1d01fe18, 0xf240d107, 0xe00810dc, 0x22004910, 0xf0114628, 0x1d40fe0e, 0xf240d1d8, 
+    0x86a010dd, 0x9ffce8bd, 0x21012200, 0xf2afb510, 0xf01140df, 0x2108fc4b, 0xf0112003, 0x4905fda9, 
+    0x60483908, 0x0000bd10, 0x00042fe8, 0x00043790, 0x00040293, 0x00042740, 0x00043004, 0x00057f70, 
+    0xf23c80ba, 0x0004257a, 0x0004274c, 0x000434e0, 0x00042550, 0x0004232e, 0x00042598, 0x40300000, 
+    0xb573eab3, 0x4030ab15, 0xdead0000, 0x00043014, 0xf2035152, 0x00040292, 0x0004024c, 0x0004237c, 
+    0x0004e508, 0x00042f98, 0xf2060010, 0xf203501a, 0x800849fe, 0xe92d4770, 0x4afd4ffe, 0x8e804604, 
+    0x27bdf240, 0xf04f4df9, 0xf8df0a00, 0x42b8b3e8, 0x93e4f8df, 0x21bdf2a0, 0xf1056813, 0xd0670608, 
+    0xf5b0dc67, 0xd07c7fe0, 0xf5b0dc2d, 0xd0797fb0, 0x28b6dc13, 0xdc06d077, 0xd0752800, 0xd07428ae, 
+    0xd17328af, 0x28b7e129, 0xf5b0d071, 0xd06f7f9e, 0x7080f5a0, 0xd1f4383d, 0xf5b0e11f, 0xd0687fc4, 
+    0xf5a0dc08, 0x38617080, 0x2821d079, 0x2822d078, 0xe3bdd1e7, 0x7080f5a0, 0xd0fa3889, 0xd070282d, 
+    0xd1de282e, 0xf5b0e2c6, 0xd06b7f09, 0xf5b0dc15, 0xd0687ff5, 0xf5a0dc08, 0x38c17080, 0x2809d07b, 
+    0x280ad07a, 0xe2ecd1cd, 0x7080f5a0, 0xd0e038eb, 0xd0722805, 0xd1c42806, 0xf5b0e39a, 0xd06d7f28, 
+    0xf5a0dc08, 0x38257000, 0x282fd0d3, 0x2830d067, 0xe38ad1b7, 0x7000f5a0, 0xd0a038a1, 0xd1b0281b, 
+    0x220049c2, 0x31086868, 0xfd45f011, 0xd07d1d40, 0x48c2e3a8, 0x7fc4f5b1, 0xd0626800, 0xf5b1dc62, 
+    0xd01b7f91, 0x298cdc30, 0xdc18d018, 0xd06e2983, 0xd06d2984, 0xd194298b, 0x220049b4, 0x31086868, 
+    0xe28ce008, 0xe0c6e1c4, 0xe0ace09f, 0xe0cce3fe, 0xe213e199, 0xfd1ff011, 0xd0741d40, 0x29e5e0ad, 
+    0x29e6d072, 0xf5a1d00a, 0x39217180, 0x49acd190, 0x46182200, 0xfd0ff011, 0xd07d1d40, 0xe1aee09d, 
+    0xe250e1ee, 0xe2b9e312, 0x7fbaf5b1, 0xdc17d011, 0x7180f5a1, 0xd0703961, 0xd0402901, 0xd1912912, 
+    0x220048a0, 0x31084999, 0xf0116800, 0x1d40fcf4, 0x2004d077, 0xe259e3fe, 0xe2b8e26c, 0xe31ce3dc, 
+    0x7180f5a1, 0xd06d397d, 0xd0a62901, 0xd18f290a, 0x22004895, 0x3108498d, 0xf0116800, 0x1d40fcdc, 
+    0xe3e8d076, 0xf5b14a91, 0x68177fe9, 0xdc2cd029, 0x7fcff5b1, 0xdc13d061, 0x7180f5a1, 0xd0683991, 
+    0xd0672901, 0xd196290c, 0xe0022200, 0xe3f2e3f2, 0x497ee3f2, 0xf0113108, 0x1d40fcbe, 0xe04cd07e, 
+    0x7180f5a1, 0xd07a39c1, 0xd0462901, 0xd19d2910, 0x2200487f, 0x31084975, 0xf0116800, 0x1d40fcac, 
+    0x2006d06e, 0xe3fde3b6, 0xf5b1e3fd, 0xd0117ff3, 0xf5a1dc14, 0x39db7180, 0x2901d07d, 0x290ad07c, 
+    0x4874d184, 0x49692200, 0x68003108, 0xfc93f011, 0xd0721d40, 0xe39d2008, 0xe3e6e3e6, 0x7100f5a1, 
+    0xd06b39b9, 0xd18a2901, 0x4960e017, 0x80302007, 0x68682200, 0xf0113108, 0x1d01fc7e, 0x20aed109, 
+    0xe3fde207, 0x4959e3fd, 0x68682200, 0xf0113108, 0x1d40fc72, 0x20afd101, 0x4954e7f2, 0x32fff04f, 
+    0x31086868, 0xfc96f011, 0xd10a1d01, 0xe7e720b6, 0xe3e8e3e8, 0x494de3e8, 0x68682200, 0xf0113108, 
+    0x1d41fc89, 0x2801d03b, 0xf44fd1e7, 0xf9b62800, 0xf04f1000, 0x46404220, 0xfcf3f7eb, 0x0000f9b6, 
+    0xd02e2807, 0xd0772806, 0xd0762805, 0xd0752870, 0xd0742871, 0xd0732808, 0xe002280b, 0xe3fde3fd, 
+    0xd06ee3fd, 0xd06d2809, 0xd06c2821, 0xd06b2822, 0xd06a2823, 0xd1c02820, 0xf7f22002, 0xf899fcd6, 
+    0x464f0000, 0xfd18f7f2, 0x7008493b, 0x0000f997, 0xf846f00b, 0xe3fce7b1, 0xe3fce3fc, 0x20b7e3fc, 
+    0x200be79e, 0x46508028, 0xf889464f, 0xf7f2a000, 0x4931fd03, 0x70082201, 0x20022100, 0xfa72f7f4, 
+    0x7800482e, 0x492eb170, 0x7809482e, 0xe9cd7800, 0x482d0100, 0x78037839, 0x7802482c, 0x7800482c, 
+    0xf964f7f6, 0xfbd4f7f4, 0x8800482a, 0x2000b968, 0xf9baf00b, 0x78004828, 0xfe1af013, 0x23004827, 
+    0xf24c220e, 0xf0160100, 0xf7f4fe0c, 0x4f24fcfa, 0x22072300, 0x46382180, 0xfe03f016, 0x46382301, 
+    0x21402206, 0xfdfdf016, 0x46382300, 0x21082203, 0xfdf7f016, 0xe0352300, 0xe21ae050, 0xe3fce3e4, 
+    0xe3fce3fc, 0xe3fce3fc, 0xe3fce3fc, 0x00042748, 0x00042f98, 0x00042300, 0x00040292, 0x0004273c, 
+    0x0004e514, 0x000426bc, 0x000426cc, 0x00042708, 0x000426ec, 0x0004271c, 0x00040293, 0x0004254d, 
+    0x0004261f, 0x0004261e, 0x0004261d, 0x0004261c, 0x0004254c, 0x0004237c, 0x00042380, 0xf23c8022, 
+    0xf2034228, 0x46382201, 0xf0162102, 0x2006fdba, 0x49fd8030, 0x68682200, 0xfb8df011, 0xd1071d01, 
+    0x103cf240, 0x49f8e70c, 0x68682200, 0xfb83f011, 0xf47f1d40, 0xf240ade7, 0xe701103d, 0x880048f3, 
+    0x48f3b1e8, 0x28017800, 0x48f2d019, 0x22002173, 0xf8808001, 0xf899a002, 0x70c11000, 0x48ee4601, 
+    0xf0116800, 0x1d01fb68, 0xf240d107, 0xe6e71060, 0x220049e8, 0xf0114618, 0x1d40fb5e, 0x200cd009, 
+    0x48e68028, 0xf8804657, 0x48e5a000, 0xb9808800, 0xf240e002, 0xe0dc1061, 0x780048e2, 0xd0082801, 
+    0x780048e1, 0x48e1b128, 0xb9107800, 0x0000f89b, 0x2201b120, 0x46102100, 0xf9a4f7f4, 0xf7f82000, 
+    0x48dbfcfa, 0x28017800, 0x48dad00d, 0xb3807800, 0x8030206e, 0x220048d8, 0x680049cb, 0xfb2bf011, 
+    0xd0181d01, 0x2066e020, 0x48d48030, 0x49c62200, 0xf0116800, 0x1d01fb20, 0xf240d108, 0xe0a81082, 
+    0x220048ce, 0x680049c0, 0xfb15f011, 0xd16f1d40, 0x1083f240, 0xf240e09d, 0xe09a1088, 0x220048c6, 
+    0x680049b9, 0xfb07f011, 0xd1611d40, 0x1089f240, 0xe7ffe08f, 0x780048bb, 0xd01d2801, 0x780048b4, 
+    0xd0342801, 0x880048be, 0xd0462801, 0x780048bd, 0xd03f2801, 0x780048bc, 0xd03b2801, 0x780048bb, 
+    0xd0372801, 0x780048ba, 0xd06f2801, 0x82b8f8df, 0x0000f898, 0xe0b4b3d8, 0xf7f72000, 0x2003fbac, 
+    0xfb46f7f6, 0xf7f62007, 0xf004fd79, 0x2100f8eb, 0x3080f44f, 0xfbd0f7f2, 0xf7f62000, 0xf7f9fd53, 
+    0x49acfa9a, 0x06c22002, 0x211a8008, 0x2022e062, 0x49958030, 0x68682200, 0xfabdf011, 0xd1071d01, 
+    0x10b6f240, 0x4990e045, 0x68682200, 0xfab3f011, 0xd00e1d40, 0x8800489a, 0x2021b1c0, 0x498a8030, 
+    0x68682200, 0xfaa7f011, 0xd0051d01, 0xe046e00c, 0xf240e044, 0xe02c10b7, 0x10c0f240, 0x4982e029, 
+    0x68682200, 0xfa97f011, 0xd0041d40, 0x7800488d, 0xd0032801, 0xf240e015, 0xe01a10c1, 0x80302023, 
+    0x22004979, 0xf0116868, 0x1d01fa86, 0xf240d107, 0xe00e10ca, 0x22004974, 0xf0116868, 0x1d40fa7c, 
+    0x4881d005, 0x28017800, 0xe009d004, 0xf240e00f, 0xe25b10cb, 0x5280f04f, 0x12502112, 0xfb11f7eb, 
+    0x7800487a, 0xd1092801, 0x21130702, 0x2115e002, 0x5280f04f, 0x2000f44f, 0xfb03f7eb, 0x4876e098, 
+    0xb1a87800, 0x80302070, 0x2200495f, 0xf0116868, 0x1d01fa52, 0xf240d107, 0xe23710ea, 0x2200495a, 
+    0xf0116868, 0x1d40fa48, 0xf240d176, 0xe22d10eb, 0x7800486a, 0x2071b1a8, 0x49538030, 0x68682200, 
+    0xfa39f011, 0xd1071d01, 0x10f0f240, 0x494ee21e, 0x68682200, 0xfa2ff011, 0xd1691d40, 0x10f1f240, 
+    0x4852e214, 0x1000f990, 0x0000f89b, 0xd0374301, 0x2201495b, 0x700f8072, 0x485ab1e0, 0x09037800, 
+    0xebb2d018, 0xd1011f10, 0xe0042011, 0xebb32302, 0xd1021f10, 0x80702012, 0x2303e00c, 0x1f10ebb3, 
+    0x2011d101, 0x2304e004, 0x1f10ebb3, 0x2012d102, 0x700a8070, 0x80302005, 0x49332200, 0xf0116868, 
+    0x1d01f9fa, 0xf240d107, 0xe1df2024, 0x2200492e, 0xf0116868, 0x1d40f9f0, 0xf240d12a, 0xe1d52025, 
+    0xf7f72000, 0x2003fab8, 0xfa52f7f6, 0xf7f62007, 0xf003fc85, 0xf898fff7, 0x28010000, 0x203ad118, 
+    0x48398030, 0x49202200, 0xf0116800, 0x1d01f9d4, 0xf240d109, 0xe1b92054, 0x4833e00a, 0x491a2200, 
+    0xf0116800, 0x1d40f9c8, 0x491cd010, 0x70082001, 0x7801482e, 0xf47f2901, 0xf880ac25, 0x2300a000, 
+    0x2201482b, 0xf0162102, 0xe546fbdc, 0x2055f240, 0x4912e19c, 0x8028200d, 0xf8814826, 0x7800a000, 
+    0xd00c07c0, 0x0002f9b6, 0x28014923, 0x2811d046, 0x2812d048, 0xd0498808, 0x4080f440, 0x480d8008, 
+    0xb1007800, 0xe044e0d5, 0x00042750, 0x0004237c, 0x00040285, 0x0004e514, 0x00042f98, 0x00042620, 
+    0x00040290, 0x0004028b, 0x0004028c, 0x0004024a, 0x000402b2, 0x00040284, 0x00042f54, 0x000432f0, 
+    0x00040286, 0x0004028a, 0x000425a1, 0x000425a3, 0x0004028d, 0x0004235a, 0x00040249, 0x00040248, 
+    0x000425f9, 0x00042301, 0x00042fa4, 0x000425a6, 0xf23c801c, 0x000402b4, 0x000402b6, 0xf0408808, 
+    0xe7bb0002, 0xf0408808, 0xe7b70010, 0x0080f040, 0xf9b6e7b4, 0x48fe1002, 0xd00c2901, 0xd0482911, 
+    0xf8892004, 0x48fb0000, 0x1000f89b, 0x0000f990, 0xd0794308, 0x49f8e07d, 0x29948809, 0x2998d01a, 
+    0x2984d018, 0x2988d016, 0x29a4d014, 0x29a8d012, 0x29b4d010, 0x29b8d00e, 0x48eed00c, 0xf8892103, 
+    0xf89b1000, 0xf9901000, 0xe0000000, 0x4308e3fd, 0xe05ed01c, 0xf2412300, 0x220c0100, 0xfb41f016, 
+    0x80302007, 0x220049e5, 0xf0116868, 0x1d01f914, 0xf240d107, 0xe0f920a0, 0x220049e0, 0xf0116868, 
+    0x1d40f90a, 0xf240d145, 0xe0ef20a1, 0x220049dc, 0x49d9e03c, 0x29988809, 0x2988d013, 0x29a8d011, 
+    0x29b8d00f, 0x2005d00d, 0x0000f889, 0xf99048d1, 0xe0010000, 0xe29ae0f1, 0x1000f89b, 0xd0204308, 
+    0x2208e027, 0x23004607, 0xf0160151, 0x2300fb0a, 0x22064638, 0xf0162140, 0x2007fb04, 0x49c78030, 
+    0x68682200, 0xf8d7f011, 0xf47f1d01, 0xf240ab8f, 0xe0bb20bc, 0xe0bae002, 0xe005e0c0, 0x20bdf240, 
+    0x49c0e0b4, 0xe0012200, 0x220049bf, 0xf7f32000, 0xf899ff29, 0x46c80000, 0xf9aef7f2, 0x4fbd49bb, 
+    0x48bb7008, 0x28017800, 0x48bbd120, 0x28017800, 0x48bad11c, 0x28206800, 0xf898d318, 0x28050000, 
+    0xe003d114, 0xe10fe0bb, 0xe206e1ac, 0x880048aa, 0x7fe8f5b0, 0xf5b0d002, 0xd1077ff8, 0x49b148b0, 
+    0x42886800, 0x2001d102, 0xe0017038, 0xa000f887, 0x780148ad, 0x780048ad, 0xf8984001, 0xf7f90000, 
+    0x49abf825, 0x49ab7008, 0x0000f89b, 0x43087809, 0x48a9d125, 0x48a97801, 0xf7f97800, 0xe004f848, 
+    0xe21ce20d, 0xe245e236, 0x49a1e24c, 0x7809783a, 0x0007e88d, 0x780348a2, 0x780048a2, 0x48a24003, 
+    0x48a27802, 0x40027800, 0x780148a1, 0x780048a1, 0xf8984001, 0xf7f90000, 0x499ff811, 0xf9987008, 
+    0xf7f70000, 0x7838f928, 0xd1032801, 0x0000f898, 0xd0372805, 0xf7f62005, 0x2000f8bb, 0xfaeef7f6, 
+    0xfa2cf7ed, 0x0000f898, 0xf7f84647, 0x4893fa04, 0x1c496801, 0x20026001, 0xe218e002, 0xe26de256, 
+    0xf8f2f7f2, 0x6008498e, 0xf7ee7838, 0x488dfc14, 0x68012200, 0xf7f22002, 0x488bf8fd, 0x70c17839, 
+    0xf8802126, 0x2200a004, 0x46018001, 0x68004887, 0xe262e003, 0xe27ae268, 0xf011e39d, 0x1d01f81c, 
+    0xe009d002, 0xe7c62000, 0x3040f240, 0x497ee39d, 0x46182200, 0xf80ff011, 0xd0101d40, 0x0000f89b, 
+    0xd00f2801, 0x2200487a, 0x20016801, 0xf8d2f7f2, 0x78004878, 0xd0152801, 0x80282003, 0xf240e645, 
+    0xe3823041, 0x80302020, 0x22004954, 0xf0106868, 0x1d01fff2, 0xaad0f47f, 0x3048f240, 0xf240e375, 
+    0xe3723049, 0xe7e82002, 0x2002496b, 0x0000f889, 0x486a464f, 0xa000f881, 0xb9588800, 0x78004868, 
+    0xd1072801, 0x78004867, 0x2200b920, 0x46104966, 0xfe38f7f3, 0x8194f8df, 0xe03fe006, 0xe1a9e0d5, 
+    0xe234e228, 0xe353e24f, 0x0000f898, 0x22ffb920, 0x461120fe, 0xf9b0f7ed, 0xf7f72002, 0x2005f88c, 
+    0xf826f7f6, 0xf7f62000, 0xf003fa59, 0xf898fdcb, 0xb9080000, 0xfc03f7f8, 0x21004855, 0xf9b7f016, 
+    0x22264949, 0x70c87838, 0xa004f881, 0xf7f8800a, 0x4846f962, 0x49442200, 0xf0106800, 0x1d01ff9c, 
+    0xf240d107, 0xe32030a2, 0x2200493f, 0xf0104618, 0x1d40ff92, 0xf240d192, 0xe31630a3, 0x2001493e, 
+    0x0000f889, 0x483d464f, 0xa000f881, 0xb9588800, 0x7800483b, 0xd1072801, 0x7800483a, 0x2200b920, 
+    0x4610493c, 0xfddef7f3, 0xf7f52005, 0x2000ffe1, 0xfa14f7f6, 0xf7f72001, 0xf003f83e, 0x4833fd83, 
+    0xb9087800, 0xfc09f7f8, 0x21004831, 0xf96ff016, 0x22264925, 0x70c87838, 0xa004f881, 0xf7f8800a, 
+    0x4822f91a, 0x49202200, 0xf0106800, 0xe053ff54, 0xf38e0040, 0x0004024a, 0x00042576, 0x00042750, 
+    0x00042564, 0x00042566, 0x00042568, 0x00040293, 0x0004230c, 0x0004230e, 0x0004230d, 0x00040240, 
+    0x00042570, 0x4a9e1cee, 0x0004232c, 0x0004232d, 0x0004232e, 0x00040284, 0x0004232b, 0x00042328, 
+    0x000425f5, 0x000425f6, 0x000425f7, 0x000425f8, 0x000425f3, 0x000425f4, 0x000425f9, 0x00057f78, 
+    0x000425d0, 0x00042604, 0x0004e514, 0x00042f98, 0x00042600, 0x0004257a, 0x00042620, 0x00040290, 
+    0x0004028c, 0x0004028b, 0x0004256a, 0x0004028d, 0xf203511c, 0x0004256c, 0xf47f1d01, 0xf240a9ed, 
+    0xe28230de, 0x30dff240, 0xf9b5e27f, 0xf04f1000, 0x46405280, 0xff95f7ea, 0x0000f9b5, 0x280a2717, 
+    0x49fed005, 0xf0318809, 0xd10c0108, 0x48fce04f, 0xb9687800, 0xf7f22002, 0xb148f8cc, 0x880048f7, 
+    0x0008f030, 0x2119d028, 0xf04f4640, 0xe0bf5280, 0xf7f32000, 0x49f3f919, 0x4af42001, 0x49f26008, 
+    0x68086812, 0xda014290, 0x60081c40, 0xb2818808, 0xf01648ef, 0xf899f8cc, 0x20001000, 0xfa69f7f3, 
+    0xfeeef005, 0x201c49eb, 0xa000f881, 0xf890f7f2, 0xf7f52000, 0xe118fd49, 0xf7f22002, 0x2009f878, 
+    0x48e68028, 0x80372200, 0x680049e3, 0xfea3f010, 0xd1061d01, 0x401ef240, 0x49dfe227, 0xf0102200, 
+    0x1d40fe9a, 0xace1f47f, 0x401ff240, 0x2803e21d, 0x2804d017, 0x2802d026, 0x2808d03e, 0x2809d04d, 
+    0x2002d1b1, 0xff31f7f1, 0x220048d4, 0x49d28037, 0xf0106800, 0x1d01fe80, 0xa9bff47f, 0x405af240, 
+    0x2010e203, 0x48ce8030, 0x49cb2200, 0xf0106800, 0x1d01fe72, 0xa97bf47f, 0x4030f240, 0xf240e1f5, 
+    0xe1f24031, 0x80302012, 0x220048c6, 0x680049c2, 0xfe61f010, 0xd1081d01, 0x403af240, 0x48c1e1e5, 
+    0x49bd2200, 0xf0106800, 0x1d40fe56, 0x2005d001, 0xf240e653, 0xe1d8403b, 0x80302011, 0x220048ba, 
+    0x680049b5, 0xfe47f010, 0xf47f1d01, 0xf240a968, 0xe1ca4044, 0x4045f240, 0x2016e1c7, 0x48b38030, 
+    0x49ad2200, 0xf0106800, 0x1d01fe36, 0xf240d108, 0xe1ba404e, 0x220048ad, 0x680049a7, 0xfe2bf010, 
+    0xd0011d40, 0xe6282009, 0x404ff240, 0xf240e1ad, 0xe1aa405b, 0x1000f9b5, 0x5280f04f, 0x46404647, 
+    0xfebff7ea, 0x88004895, 0x0008f030, 0xe002d112, 0xfeb7f7ea, 0xf9b5e459, 0x21140000, 0xd00e2804, 
+    0xd02d2805, 0xd03c2806, 0xd0522807, 0xd00a2808, 0xd0082809, 0x46382118, 0x5280f04f, 0x4894e7e8, 
+    0x28037800, 0x4893d006, 0x68012200, 0xf7f12001, 0xe43afec1, 0x22004890, 0x49878031, 0xf0106800, 
+    0x1d01fdea, 0xf240d107, 0xe16e407e, 0x22004982, 0xf0104638, 0x1d40fde0, 0xf240d1cc, 0xe164407f, 
+    0x80302013, 0x22004885, 0x6800497b, 0xfdd3f010, 0xf47f1d01, 0xf240a924, 0xe156408e, 0x408ff240, 
+    0x487de153, 0x80312200, 0x68004973, 0xfdc3f010, 0xd1071d01, 0x4098f240, 0x496fe147, 0x46382200, 
+    0xfdb9f010, 0xd0011d40, 0xe5b62007, 0x4099f240, 0x2015e13b, 0x48728030, 0x49672200, 0xf0106800, 
+    0x1d01fdaa, 0xa914f47f, 0x40a2f240, 0xf240e12d, 0xe12a40a3, 0xf04f486b, 0x78000200, 0x496ab108, 
+    0x496ae000, 0xf7f12001, 0x200afe65, 0xf8dfe595, 0x200e81a0, 0xf8988028, 0x07c00000, 0x2101d199, 
+    0xfa9cf7f5, 0xf9b82000, 0x1c471000, 0x07c94139, 0x2201d105, 0x4611b2c3, 0xf7f64610, 0xb238f9c6, 
+    0xdbf02804, 0x2003e57a, 0xff13f7f7, 0xc164f8df, 0x2803b240, 0xf889464f, 0xd0020000, 0xd0172805, 
+    0x4855e021, 0x28948800, 0x2884d005, 0x28a4d003, 0x28b4d001, 0x2005d103, 0x23087038, 0x2898e00e, 
+    0x2888d009, 0x28a8d007, 0x28b8d005, 0xe00ad003, 0x88004849, 0x2004e7f3, 0x23077038, 0x22024660, 
+    0xf015213c, 0x7838ff6e, 0xf7f146b9, 0x4943fe35, 0x22062300, 0x200f7008, 0x21408028, 0xf0154840, 
+    0x483fff60, 0x22012300, 0xf0152102, 0x483dff5a, 0x22062301, 0xf0152140, 0x483aff54, 0x22022300, 
+    0xf0152104, 0x7838ff4e, 0xe0afe000, 0xf9b0f7f5, 0xf8cd4935, 0x7838a000, 0x4934780b, 0x4934780a, 
+    0xf7ed7809, 0x2000fe17, 0xffc9f7f7, 0x7801482b, 0xf7f14640, 0x2700fe11, 0x46082100, 0xff1ef7f2, 
+    0xf6472200, 0x46110300, 0xf8cd4610, 0xf7f5a000, 0x4822f9c9, 0x46407801, 0xfdfef7f1, 0x11f4f240, 
+    0xf7ea4640, 0x481bfd50, 0x21ff2200, 0xf0153042, 0x4601ff26, 0xf7ea4640, 0xe03bfd35, 0x00040290, 
+    0x00042fce, 0x00057f7c, 0x00057f80, 0x00057f78, 0xf2035140, 0x0004024c, 0x00042750, 0x0004273c, 
+    0x000426bc, 0x000426dc, 0x000426cc, 0x0004272c, 0x00040284, 0x00042600, 0x00042708, 0x000426ec, 
+    0x0004271c, 0x00042fcd, 0x0094c5f0, 0x00b71b00, 0x00040286, 0xf2060000, 0x00042576, 0x00040293, 
+    0xf2034228, 0xf23c8310, 0x00042327, 0x00042326, 0x000425f9, 0x46404926, 0xfcf4f7ea, 0xb23f1c7f, 
+    0xd01b2f40, 0x22004823, 0xf01521ff, 0x28fffed8, 0xf899d092, 0x464f0000, 0xfc19f7f3, 0x2200481e, 
+    0x70c17839, 0xf8802126, 0x8001a004, 0x481b4601, 0xf0106800, 0x1d01fc90, 0xe011d00a, 0x46384f18, 
+    0xfe92f015, 0x0104f040, 0xf0154638, 0xe7e0fe90, 0x5076f240, 0x4910e009, 0x46182200, 0xfc7bf010, 
+    0xf47f1d40, 0xf240ac7b, 0x86a05077, 0x8ffee8bd, 0xe4722010, 0x2200480b, 0xb5102101, 0xfab6f010, 
+    0x20052108, 0xfc14f010, 0x60484907, 0x0000bd10, 0xdcba01f5, 0xf2060042, 0x0004e514, 0x00042f98, 
+    0xf203517c, 0x00014c17, 0x00042748, 0x4ff1e92d, 0xb09448fa, 0x83e8f8df, 0x27002404, 0xf8b06800, 
+    0x91121078, 0xa07af8b0, 0x907cf8b0, 0xb07ef8b0, 0x4df42600, 0x22002301, 0x46184631, 0x8500e9cd, 
+    0xfb6cf7f0, 0xf8389912, 0xfb100011, 0x9812f100, 0x0010f835, 0x1100fb10, 0x001af838, 0xf200fb10, 
+    0x001af835, 0x2200fb10, 0x0019f838, 0xfb104411, 0xf835f300, 0xfb100019, 0xf8383300, 0xfb10001b, 
+    0xf835fc00, 0xad02001b, 0xc000fb10, 0x44084418, 0x1106eb05, 0x0027f841, 0xf2412100, 0xf7f10000, 
+    0x1c76fd0b, 0x2e04b276, 0x1c7fdbc3, 0x42a7b23f, 0x2700dbbe, 0xe0142100, 0xb2001c48, 0x1207eb05, 
+    0xe00b4684, 0x3021f852, 0x6020f852, 0xdd0342b3, 0x6021f842, 0x3020f842, 0xb2001c40, 0xdbf142a0, 
+    0x42a14661, 0x1c7fdbe8, 0x2f04b27f, 0xeb04dbe2, 0x200071d4, 0xeb051049, 0xf8521200, 0x9a143021, 
+    0x3020f842, 0xb2401c40, 0xdbf42804, 0xe8bdb015, 0xe92d8ff0, 0x49b94ff3, 0x2000b085, 0x9003468a, 
+    0x88046808, 0x1c700866, 0xfa0f9002, 0x2500fb80, 0x0000f8da, 0xfb059905, 0xf9b0f704, 0x9a023088, 
+    0x0047eb01, 0x468149b0, 0xfd89f015, 0x0000f8da, 0x9a0249ae, 0x3088f9b0, 0xeb009806, 0x46800047, 
+    0xfd7df015, 0x46584aa8, 0xe00b4ba8, 0xf8521a21, 0xf8427021, 0xf8537020, 0x42491021, 0x1020f843, 
+    0xb2001c40, 0xdbf142a0, 0x0000f8da, 0x4aa04657, 0x78819b03, 0x0094f8d0, 0x0100e9cd, 0x489a499b, 
+    0xf9acf016, 0x4631489a, 0x0086eb00, 0xfd88f016, 0x4b966838, 0x78814a94, 0x0094f8d0, 0x0100e9cd, 
+    0x99034893, 0xfeb0f015, 0x46496838, 0xf9b09a02, 0x488d3084, 0xfd54f015, 0x46416838, 0xf9b09a02, 
+    0x488a3084, 0xfd4cf015, 0xb26d1c6d, 0xdb9f2d04, 0xe78cb007, 0x41fce92d, 0x48804604, 0x4615460f, 
+    0x88066800, 0xea4f4883, 0x78030856, 0x6800487b, 0xfb048801, 0xeb02f001, 0xeb070140, 0xb3230240, 
+    0xb2e04b7d, 0xb123781b, 0x2c01b10c, 0x2003d106, 0x2c02e004, 0x2c03d001, 0x2000d100, 0x2100e9cd, 
+    0x22002301, 0x2001b241, 0xfa68f7f0, 0xf006fb04, 0x8106fb04, 0x2010f835, 0x2011f827, 0xf8252200, 
+    0xf8252010, 0xe8bd2011, 0x230181fc, 0x2100e9cd, 0x46212200, 0x486ae7e7, 0x41f0e92d, 0x1000f990, 
+    0x4f664868, 0x78002904, 0x2905d005, 0x283cd00d, 0x2001d221, 0x28bee020, 0x2000d901, 0x495de01c, 
+    0x78092002, 0x2005b1c1, 0x284be016, 0x2006d201, 0x495de012, 0x68092009, 0xd30d2923, 0x7809495b, 
+    0x495bb951, 0xf5b18809, 0xd0027fea, 0x7ffaf5b1, 0x2002d102, 0x2004e000, 0xf8df4a56, 0x2100c134, 
+    0x00c0ebc0, 0x080cf06f, 0x0ec0eb02, 0xeb072000, 0xe9c404c1, 0x46400000, 0xd5001a0b, 0x28001a43, 
+    0x4242da01, 0x4602e000, 0x5023f85c, 0x280e1c40, 0x6022f85e, 0x2300e9d4, 0x2306fbc5, 0x2300e9c4, 
+    0x1c49dbea, 0xdbe12911, 0xeb072000, 0x680a01c0, 0x040b8889, 0x4112ea43, 0x1020f84c, 0x28111c40, 
+    0xf04fdbf3, 0xf8dc5100, 0x42880000, 0xb1c8dc14, 0xf85c2000, 0x00522020, 0x2020f84c, 0x28111c40, 
+    0xe7f0dbf7, 0xf85c2000, 0x10522020, 0x2020f84c, 0x28111c40, 0xe001dbf7, 0x4180f04f, 0x0000f8dc, 
+    0xdcef4288, 0xf85c2000, 0xf1011020, 0xf84c5100, 0x1c401020, 0xdbf62811, 0x81f0e8bd, 0x4ffee92d, 
+    0xa058f8df, 0x2100468c, 0x39fff04f, 0x469b9102, 0x46134f15, 0x1000f8da, 0x46484606, 0x2101880d, 
+    0x0455eb01, 0xe0112100, 0x1205fb06, 0xe012f83c, 0x2012f833, 0xfe0efb1e, 0xe202fb12, 0x2021f847, 
+    0xdd014282, 0x4610b101, 0xb2091c49, 0xdbeb42a1, 0xd07d2800, 0xf44f2200, 0xe0200100, 0x00042618, 
+    0x00048a00, 0x00049200, 0x0004c200, 0x0004d200, 0x00049a00, 0x0004232e, 0x00042598, 0x0004a200, 
+    0x00040292, 0x0004257c, 0x00040240, 0x000425f9, 0x00042576, 0x00042760, 0xb2121c52, 0x42881040, 
+    0x2a00dafa, 0x2100dd0a, 0xf857e006, 0x41133021, 0x3021f847, 0xb2091c49, 0xdbf642a1, 0xf44f2100, 
+    0xe0020280, 0xb2091c49, 0x42900040, 0x2900dbfa, 0x2000dd0a, 0xf857e006, 0x408a2020, 0x2020f847, 
+    0xb2001c40, 0xdbf642a0, 0x21402000, 0xf857e007, 0x2a402020, 0xf847da01, 0x1c401020, 0x42a0b200, 
+    0x4affdbf5, 0x4698b223, 0x46114648, 0xfbaef016, 0xe0064643, 0xf8571ae8, 0xf8470020, 0x1c5b0023, 
+    0x42abb21b, 0xfb06dbf6, 0x4622f005, 0x0180eb0b, 0xf01548f3, 0x980cfb75, 0x6180f04f, 0x1026f840, 
+    0x462948f0, 0xfbecf016, 0x0000f8da, 0xe0007881, 0xf8d0e036, 0xe9cd0094, 0x4aeb0100, 0x48e849e9, 
+    0xf0159b02, 0x49e8fffb, 0x5200f04f, 0xb1e0e00a, 0xf8512000, 0x005b3020, 0x3020f841, 0xb2001c40, 
+    0xdbf6281f, 0x42906808, 0xf04fddf1, 0x68084280, 0xdd0a4290, 0xf8512000, 0x105b3020, 0x3020f841, 
+    0xb2001c40, 0xdbf6281f, 0x2000e7f1, 0x2020f851, 0x5200f102, 0x2020f841, 0xb2001c40, 0xdbf5281f, 
+    0x8ffee8bd, 0x4ff7e92d, 0x76c8f500, 0xf1004607, 0xf04f08c8, 0x6030507e, 0xf0186838, 0x4604f8d5, 
+    0x42406878, 0xf8d0f018, 0xf0174621, 0x6070ffcf, 0x68384604, 0xf8c8f018, 0xff34f017, 0x46214689, 
+    0x46084605, 0xf8ecf018, 0xff2cf017, 0x22004bbf, 0xfd66f017, 0x462a464b, 0xfc2ef017, 0xf922f017, 
+    0x98024682, 0xf1002402, 0xe0570b01, 0xf04f2501, 0xe00e0900, 0x0025f857, 0xf8a6f018, 0xf8561b61, 
+    0xf0181021, 0x4649f8cd, 0xff38f017, 0x46811c6d, 0x42a5b22d, 0xf857dbee, 0xf0180024, 0x4649f895, 
+    0xff2cf017, 0x4000f080, 0xf0174651, 0x2501ff8f, 0xe00d4681, 0xf8561b60, 0x46481020, 0xf8b0f018, 
+    0x1025f856, 0xff1af017, 0x0025f848, 0xb22d1c6d, 0xdbef42a5, 0x46084649, 0x9024f848, 0xf8a0f018, 
+    0xfee0f017, 0x22004b99, 0xfd1af017, 0x46894605, 0xf0174650, 0x462afed7, 0xf017464b, 0xf017fbdd, 
+    0x4682f8d1, 0x1c642001, 0xf858e005, 0xf8461020, 0x1c401020, 0x42a0b200, 0xb224dbf7, 0xdba5455c, 
+    0x24009d02, 0xe00b1cad, 0x0024f856, 0xf018210f, 0xf018fa18, 0x9901f80d, 0x0024f841, 0xb2241c64, 
+    0xdbf142ac, 0xe92de75c, 0xf8df4ff7, 0xb084a204, 0x46934680, 0x90032000, 0xf8da2101, 0x88060000, 
+    0x0156eb01, 0x497b9102, 0x0072f8b0, 0x1a088809, 0xb2050040, 0xda002d00, 0xf1a62500, 0x42850011, 
+    0xb205dd00, 0x48702400, 0xf0164631, 0x4a6efae9, 0xeb042000, 0x180f1104, 0x3027f858, 0x1c401947, 
+    0x029bb200, 0xf8422811, 0xdbf43027, 0x0000f8da, 0x4a634b64, 0xf8d07881, 0xe9cd0094, 0x48620100, 
+    0xf0159903, 0xfb04fc01, 0x9905f706, 0x0909f06f, 0x464b485b, 0xeb019a02, 0xf0150187, 0x4859fa50, 
+    0x0187eb0b, 0x464b9a02, 0xfa49f015, 0xb2641c64, 0xdbc82c04, 0xe92de54c, 0x46825fff, 0x68004854, 
+    0x20018807, 0xeb002600, 0x25000b57, 0xfb06e02b, 0x98025407, 0x2014f930, 0xf850980e, 0x9803c024, 
+    0xfe0cfb02, 0x1014f930, 0xf850980f, 0xfb013024, 0xfb02e003, 0xfb01fe03, 0xfb12e31c, 0x0140f202, 
+    0x2101fb11, 0x1943ea4f, 0x468810c9, 0xf9e6f016, 0x0014f82a, 0x46484641, 0xf9e0f016, 0x1c6d9901, 
+    0xf821b22d, 0x455d0014, 0x1c76dbd1, 0x2e04b276, 0x2000dbcb, 0x46524601, 0x1307fb00, 0xb2401c40, 
+    0xf82a2804, 0xdbf61013, 0xb0049901, 0xe8bd4610, 0xe48e5ff0, 0x4fffe92d, 0x90b4f8df, 0x2000b083, 
+    0xf8d99002, 0x88050000, 0x086f2001, 0xf7f01c7c, 0x2000f88a, 0xf887f7f0, 0xa08cf8df, 0xfb84fa0f, 
+    0xf8d92600, 0x99100000, 0xfb064622, 0xf9b0f805, 0xeb013088, 0x491a0048, 0xfa11f015, 0x0000f8d9, 
+    0x99114622, 0x3088f9b0, 0x0048eb01, 0xf0154915, 0x4a13fa06, 0x4b134658, 0x1a29e00b, 0xc021f852, 
+    0xc020f842, 0x1021f853, 0xf8434249, 0x1c401020, 0x42a8b200, 0xf8d9dbf1, 0x4a0b0000, 0x78819b02, 
+    0x0094f8d0, 0x0100e9cd, 0x48054906, 0xfe36f015, 0x78004809, 0x2801b1e8, 0x2000d01e, 0x0000e00e, 
+    0x0004c200, 0x0004d200, 0x00049a00, 0x3ff00000, 0x00042618, 0x0004257e, 0x00042383, 0x1203e9dd, 
+    0x44081a89, 0x2900b241, 0xf04fdd15, 0x46520000, 0xf04fe00e, 0xe7e10001, 0x30fff04f, 0xf852e7de, 
+    0xfa433020, 0xf842f301, 0xf1003020, 0xb2000001, 0xdbf442a0, 0xda0de00e, 0x46514248, 0x2000b243, 
+    0xf851e006, 0x409a2020, 0x2020f841, 0xb2001c40, 0xdbf642a0, 0x46d01e78, 0xeb0ab281, 0xf0160084, 
+    0x2101f9cf, 0x20012300, 0xe9cd461a, 0x46318100, 0xfe49f7ef, 0xb2761c76, 0xf6ff2e04, 0xf8d9af72, 
+    0xf8900000, 0x98031068, 0x1a08b007, 0x4ff0e8bd, 0xf7f3b2c0, 0xb570bb1f, 0xf0072000, 0x2300fdd1, 
+    0x21082203, 0x46284dfe, 0xf9cbf015, 0x78204cfd, 0xd0282801, 0x46282300, 0x21042202, 0xf9c1f015, 
+    0x46282301, 0x46192200, 0xf9bbf015, 0xf7f32001, 0x2301fb16, 0x220048f4, 0xf0154619, 0x48f3f9b2, 
+    0x680049f3, 0x2101780a, 0x0044f9b0, 0xfab7f7f2, 0xf2402100, 0xf7f11000, 0x7820f87f, 0xe8bdb128, 
+    0xf7f24070, 0x2301b888, 0xe8bde7d5, 0xf7f24070, 0xe92db844, 0x48e74ff0, 0xac02b08b, 0xe884c80f, 
+    0x2000000f, 0xaa029006, 0x31fff04f, 0xf8424693, 0x1c401020, 0x2804b240, 0x2000dbf6, 0xfcb8f7f1, 
+    0xf8df4fdd, 0x78388378, 0xd203280a, 0x0000f898, 0xd0002801, 0xf7f62000, 0x48d9fc95, 0x28007800, 
+    0x4dd8d04e, 0xf0154628, 0xf8dff949, 0x9001935c, 0x4648464c, 0xf942f015, 0xa350f8df, 0x22012300, 
+    0x21029000, 0xf0154650, 0x172ef95c, 0x46314628, 0xf937f015, 0x46204631, 0xf933f015, 0x23014cc0, 
+    0x461a2102, 0x4620349a, 0xf94bf015, 0xf0154620, 0x07c0f92b, 0x48c6d0fa, 0x461a2300, 0xf4218801, 
+    0x80016180, 0x46202101, 0xf93bf015, 0x46202300, 0x21022201, 0xf935f015, 0x46202301, 0x03d9220f, 
+    0xf92ff015, 0x46502301, 0x461a2102, 0xf929f015, 0x46289901, 0xf905f015, 0x46489900, 0xf901f015, 
+    0xa2a0f8df, 0xf8df2400, 0xae0692cc, 0xf89a2500, 0x28010000, 0x48b0d004, 0x0000f990, 0xd0274285, 
+    0xf99048ae, 0x2a032000, 0xf899d003, 0x07c00000, 0x7838d01a, 0x280ab15c, 0xf898d203, 0x28010000, 
+    0xf240d00d, 0x46282100, 0xfd46f7f6, 0x280ae010, 0xf898d203, 0x28010000, 0x49a1d001, 0x4621e7f3, 
+    0xf7f64628, 0xe003fc2b, 0x46284621, 0xff7af012, 0xb26d1c6d, 0xdbca2d04, 0xf7f12001, 0xf242ff4d, 
+    0x06c80130, 0xff1bf7e9, 0x0000f899, 0xd00e07c0, 0x2c02b114, 0xe00ad062, 0x20012100, 0xe9cd2208, 
+    0x23070100, 0xf2404611, 0xf0141090, 0x2300f82f, 0xf44f2211, 0xf04f3100, 0xf0154071, 0x2001f8ab, 
+    0xfbf6f7f1, 0xf7ffa807, 0x2000fa41, 0xfbf0f7f1, 0x465d2000, 0xf855ab07, 0xf8532020, 0x42911020, 
+    0x5434dd02, 0x1020f845, 0xb2401c40, 0xdbf22804, 0x0130f242, 0xf7e906c8, 0x1c64fee2, 0x2c04b264, 
+    0x2000db84, 0x4480f04f, 0x1020f855, 0xda0042a1, 0x1c40460c, 0x2804b240, 0x2500dbf6, 0x0000f89a, 
+    0xd0042801, 0xf990486c, 0x42850000, 0x486bd037, 0x2000f990, 0xd0032a03, 0x0000f899, 0xd02a07c0, 
+    0x280a7838, 0xf898d203, 0x28010000, 0x5770d015, 0x2801b1c0, 0x2802d018, 0xe020d01b, 0x90002001, 
+    0x90012208, 0x46112307, 0x3090f241, 0xffcef013, 0x30fff04f, 0xe8bdb00b, 0x57718ff0, 0xf7f64628, 
+    0xe00cfb9d, 0xe0004957, 0x46284957, 0xfca4f7f6, 0x4956e005, 0x5771e7f9, 0xf0124628, 0x1c6dfee3, 
+    0x2d04b26d, 0xf242dbba, 0x06c80130, 0xfe87f7e9, 0xf2432080, 0xf7e901a0, 0xf89dfe76, 0xf99d1018, 
+    0xf99d001b, 0xea40201a, 0xf99d6101, 0x04000019, 0x2002ea40, 0x20804301, 0xfe54f7e9, 0x20809902, 
+    0xfe50f7e9, 0x20809903, 0xfe4cf7e9, 0x20809904, 0xfe48f7e9, 0x20809905, 0xfe44f7e9, 0xe7b94620, 
+    0x41f0e92d, 0x78304e27, 0xf7f1b908, 0x2100fec6, 0xf0032001, 0x2100fa5b, 0x2080f44f, 0xfeecf7f0, 
+    0x20012100, 0xfa52f003, 0x682c4d31, 0x20c0f424, 0x78306028, 0xbb284e27, 0x492e4827, 0x7000f990, 
+    0xb1517809, 0x57c8492c, 0xeb001c40, 0xf02272d0, 0x1a800201, 0x5608b240, 0x1cf8e007, 0xeb0017c1, 
+    0xf0217191, 0x1a400103, 0xf7f6b240, 0x2001fd80, 0xfe4ff7ff, 0x07c07830, 0xf7f1d147, 0x4638fe8e, 
+    0xfd75f7f6, 0xf7ff2001, 0x7830fe44, 0xd13c07c0, 0xfe83f7f1, 0x0140f242, 0xf7e90648, 0xe02dfe10, 
+    0xf20350e6, 0x0004257a, 0xf2031012, 0x00042618, 0x00040293, 0x0002ea50, 0x0004257c, 0x000402f2, 
+    0x000402b5, 0xf0001000, 0xf0001500, 0xf23c8318, 0x000402b6, 0x000402b4, 0x00040298, 0x00040292, 
+    0xfffffd00, 0xfffffa00, 0xfffffc00, 0xfffffe00, 0x00057ffc, 0x0004232e, 0x00042598, 0x2100602c, 
+    0x41f0e8bd, 0xf0032001, 0xe8bdb9e1, 0xe92d81f0, 0xb0914ff0, 0x21002000, 0x1e40900f, 0xe9cd2224, 
+    0x900d100b, 0x49fe48fd, 0xa8026804, 0xe964f014, 0x78304efc, 0xd00e2801, 0xf7f0257f, 0x48fafbf4, 
+    0xb3e8f8df, 0x0000f990, 0xd0062803, 0xd0082804, 0xd00b2805, 0x25ffe011, 0x49f5e7ef, 0xb1497809, 
+    0xf89be00b, 0x29961000, 0xe006d304, 0x1000f89b, 0xd20229ff, 0x780949ef, 0x2100b121, 0x46892805, 
+    0xe006d002, 0xe7f92101, 0x28017830, 0xf04fd101, 0xf8df0900, 0x2000a3a4, 0x4606900e, 0x4ae74607, 
+    0x49e74630, 0xf9c6f7ff, 0x4be748e6, 0x49e44ae3, 0x46309000, 0xfa92f7ff, 0x20004ae4, 0xf85149e4, 
+    0x1c403020, 0x3027f842, 0xb2001c7f, 0x281fb23f, 0xf1b9dbf5, 0xd00c0f00, 0xf8512000, 0xf1a22020, 
+    0xf8415200, 0x1c402020, 0x281fb200, 0xf7ffdbf5, 0x48d8f9e2, 0x1106eb06, 0xeb002210, 0x48d40181, 
+    0xf7ff4688, 0x2000fb4f, 0xf858426a, 0xf5011020, 0xf3417180, 0x42a9214f, 0x1010f824, 0x4629dd00, 
+    0xf8244291, 0xda001010, 0xf8244611, 0x1c401010, 0x2810b200, 0x2000dde9, 0xf8344601, 0x1c403010, 
+    0x4419b200, 0x2811b209, 0x8c20dbf7, 0x84201a40, 0x0000f89b, 0xd20d280a, 0x780048bf, 0xd1092801, 
+    0xa9022000, 0x3010f831, 0x3010f824, 0xb2001c40, 0xdbf72811, 0x200049b9, 0x82e4f8df, 0x1c46eb01, 
+    0x1146eb0a, 0x1e46eb08, 0x0340eb04, 0x3002f9b3, 0xdd0242ab, 0x5010f821, 0x4293e006, 0xf821da02, 
+    0xe0012010, 0x3010f821, 0x3010f831, 0x3010f82e, 0x3010f82c, 0xb2001c40, 0xdbe52810, 0xf7ef4630, 
+    0x1c76fc91, 0x2e04b276, 0xaf69f6ff, 0x46082100, 0xf8fcf003, 0x780048a3, 0xf89bb930, 0x28fa0000, 
+    0x4894d802, 0xb3a07800, 0x900b2000, 0x46082100, 0xf8ecf003, 0x4c9c9a0b, 0xdd462a00, 0x2301489b, 
+    0xf00d990c, 0x980cf830, 0x31c8f44f, 0x0c014348, 0xf0144620, 0x4645fe7c, 0x8254f8df, 0x46562400, 
+    0xeb082200, 0xeb061744, 0xeb051144, 0xf8311344, 0xf8270012, 0xf8230012, 0x1c520012, 0x2a10b212, 
+    0x4620dbf5, 0xfc4ef7ef, 0xb2641c64, 0xdbe72c04, 0xe7ffe020, 0x20444985, 0x22102301, 0x46198008, 
+    0xf7f14610, 0x4883fc8a, 0xf44f7801, 0xf7f02000, 0xa80dfd43, 0x487d9000, 0xaa0b2301, 0xf00ca90c, 
+    0x2000f8f7, 0xf994f7f1, 0xf64fe7b0, 0x462071ff, 0xfe3df014, 0x496d4a78, 0xf7ff486e, 0x4976fb24, 
+    0x4b66486a, 0xe9cd4a66, 0x49740100, 0xf7ff4874, 0x4874fb72, 0xb9387800, 0x3000f44f, 0x0103f640, 
+    0xfc71f7e9, 0xf868f7f6, 0x486d496c, 0x4a5c4b5b, 0x0100e9cd, 0x100ee9dd, 0xfbacf7ff, 0x46082100, 
+    0xf874f003, 0xe5c6b011, 0x4ff0e92d, 0xb0994d5e, 0xac01484b, 0x4f563580, 0xf04f3024, 0xf10d0901, 
+    0xc80f0838, 0x000fe884, 0x6800485f, 0x08468800, 0x4b4f2400, 0xf8cd2200, 0x20019000, 0xf7efb261, 
+    0x2000fb45, 0x0cc4eb08, 0x0000e9cc, 0xf857e009, 0x1c401020, 0x2300e9dc, 0xfbc1b200, 0xe9cc2301, 
+    0x42b02300, 0x1c64dbf3, 0x2c04b2e4, 0xa816d3e1, 0xfdf9f7f2, 0x46c22400, 0x0b58f10d, 0x46a14626, 
+    0xf93b465f, 0x281e0014, 0x201edd02, 0x0014f827, 0x0014f937, 0xda012800, 0x9014f827, 0x02c4eb0a, 
+    0xca034690, 0x78124a41, 0xf0130052, 0xe9c8ff1b, 0x46840100, 0x4688483e, 0x1014f937, 0x0011f830, 
+    0x0c810382, 0x7e00fba2, 0xe000fb01, 0x0209fb02, 0x2100205d, 0x3e00fba7, 0xe000fb02, 0x0001fb07, 
+    0x46410d5a, 0xea421543, 0x466022c0, 0xef20f013, 0xeb07af06, 0x469002c4, 0xc2031986, 0x7800482d, 
+    0xd10c2801, 0x0034f857, 0xfe13f7f2, 0xf248b280, 0x0fc20100, 0x0200e9c8, 0xf8251840, 0xa9010b02, 
+    0x0034f837, 0x1024f851, 0x0401f104, 0x2c04b2e4, 0xd3a58008, 0x78004813, 0xe03eb3f0, 0x00040238, 
+    0x0002ea60, 0x0004230e, 0x00040292, 0x0004257c, 0x00042352, 0x00042300, 0x00043580, 0x00044200, 
+    0x00043a00, 0x000439f0, 0x00047a00, 0x00040300, 0x00049a00, 0x00043680, 0x000402f2, 0x00043600, 
+    0x00043500, 0x0004232e, 0xf203513c, 0x00042758, 0x00043350, 0x00040293, 0x00041300, 0x00045200, 
+    0x00044a00, 0x0004257a, 0x00042618, 0x00042383, 0x00042e76, 0x000402f0, 0x19b6e000, 0xf7f24630, 
+    0x49ccfdb8, 0x305db280, 0x29126809, 0x2916d001, 0x21a2d102, 0x0a004348, 0x600849c7, 0xe4dab019, 
+    0xe92d48c6, 0x680041f0, 0x0068f890, 0xfe82f7f2, 0xf0072000, 0x4cc2f935, 0x22032300, 0x46202108, 
+    0xfd2ff014, 0x78304ebf, 0x48bfb110, 0xb1087800, 0xe0002301, 0x46202300, 0x21042202, 0xfd21f014, 
+    0x46202301, 0x46192200, 0xfd1bf014, 0xf7f22001, 0x4cb6fe76, 0x22082301, 0x3100f240, 0xf0144620, 
+    0x2301fd10, 0x22004620, 0xf0144619, 0x2301fd0a, 0x220048af, 0xf0144619, 0x48aefd04, 0x78022101, 
+    0xf9b048ad, 0xf7f10000, 0xf240fde8, 0x21001700, 0xf7f04638, 0x2100fbd1, 0xf0022001, 0x4da7ff37, 
+    0xf424682c, 0x602820c0, 0xf7ef2001, 0x2100fafc, 0xf7f04638, 0x7830fbc1, 0xd0172801, 0xfbd9f7f1, 
+    0x22112300, 0x3100f44f, 0x4071f04f, 0xfcc2f014, 0xf7f12001, 0xf242f80d, 0x06c80130, 0xfb0ff7e9, 
+    0x46082100, 0xff12f002, 0xe52e602c, 0xf7ef2000, 0xf7f1fada, 0xe7e3fb72, 0xf7ffb570, 0x4990fe95, 
+    0x48852391, 0x55aaf240, 0x4c8f4a8e, 0x68007809, 0xf9922901, 0xd0061000, 0xd06b2903, 0xd07a2905, 
+    0xd0792904, 0x2903e0cf, 0x2905d004, 0x2904d021, 0xe0c8d03c, 0x7faff5b0, 0xf240dd0b, 0x428841e2, 
+    0x4608dd00, 0xeb004b81, 0xf5a10140, 0x39ba5104, 0x287de00a, 0x207dda00, 0xeb004b7d, 0xebc101c0, 
+    0xf5a11180, 0x39aa4139, 0x3000fb01, 0x70200c00, 0xf5b0e0a3, 0xdd0b7fe1, 0xdd0042a8, 0x4b754628, 
+    0x01c0ebc0, 0x1140eb01, 0x0181eb03, 0xe01b4b72, 0x4d7221f5, 0xeb054341, 0x4d710141, 0x5000fb01, 
+    0x40c7f3c0, 0xe0677020, 0xe08c7023, 0x7fbef5b0, 0xf240dd0f, 0x42886172, 0x4608dd00, 0x21e34b69, 
+    0xf5a14341, 0x39b4213b, 0x3000fb01, 0x70200d80, 0xebc0e079, 0x4b6401c0, 0x1100eb01, 0x1101eb03, 
+    0xfb014b62, 0xf3c03000, 0x70204047, 0xd96a28fe, 0xe7ec20fe, 0x7fa1f5b0, 0xf240db0f, 0x4288512c, 
+    0x4608dd00, 0x21a94b5a, 0x44194341, 0xfb014b59, 0x0d803000, 0xe011e7ab, 0xeba0e031, 0x49561000, 
+    0x0040eb00, 0x1000ebc0, 0x1040eb01, 0x4007f3c0, 0x287b7020, 0x207bd941, 0xe0417020, 0x7fc3f5b0, 
+    0x42a8dd0c, 0x4628dd00, 0xebc04b4c, 0xeb031140, 0x4b4b0181, 0x3000fb01, 0xe7b80d40, 0x6151f240, 
+    0x43414d48, 0x4d484429, 0x5000fb01, 0xf3c04947, 0x70205047, 0xb9097809, 0xd8952891, 0xf5b0e023, 
+    0xdd0b7f9b, 0x51dcf240, 0xdd004288, 0xf2404608, 0x4b3f1151, 0x44194341, 0xe7954b3e, 0x7185f641, 
+    0x43414b3d, 0x4b3d4419, 0x3000fb01, 0x5087f3c0, 0x28fa7020, 0x20fad907, 0xb2c0e789, 0xd902283c, 
+    0x1dc0b2c0, 0x4836e783, 0x28017800, 0x2802d005, 0x4934d003, 0x43087809, 0x7810d10f, 0xd10c2804, 
+    0xf1a07820, 0x29090115, 0x300ad201, 0xf1a0e004, 0x293c011e, 0x380fd201, 0xf6407020, 0x030d0100, 
+    0xf7e94628, 0x7821f9f0, 0xe8bd4628, 0xf7e94070, 0x0000b9d9, 0x00040240, 0x00042614, 0x00042618, 
+    0xf20350ec, 0x0004257a, 0x00042300, 0xf2030444, 0xf2031012, 0x00040293, 0x0004257e, 0x00057ffc, 
+    0x000402d8, 0x00040292, 0x0004257c, 0x005d41c4, 0x00c96ba6, 0xfff7a80e, 0x1d0e8b34, 0xfff85cee, 
+    0x0989d37f, 0x28a19798, 0xfffbcc98, 0x03ea329f, 0xfff7c4ea, 0x18e997a9, 0x00a84018, 0xfffa6eca, 
+    0x10133079, 0xffe89b85, 0x1dcb8bb0, 0x0004230e, 0xfff063b3, 0x2ec83679, 0xffa22500, 0x61737224, 
+    0x000425f9, 0x00042556, 0x5fffe92d, 0x4680f04f, 0x221e4693, 0x4681468a, 0x46314603, 0x46204cfe, 
+    0xfb48f014, 0x464b1d25, 0x4631221e, 0xf0144628, 0xf105fb41, 0x464b0804, 0x4631221e, 0xf0144640, 
+    0x4631fb39, 0xf108464b, 0x221e0604, 0xf0144630, 0xf04ffb31, 0x464b5700, 0x4639221d, 0xf0144620, 
+    0x221dfb29, 0x4639464b, 0xf0144628, 0x221dfb23, 0x4639464b, 0xf0144640, 0x221dfb1d, 0x4639464b, 
+    0xf0144630, 0x107ffb17, 0x221c464b, 0x46204639, 0xfb10f014, 0x464b221c, 0x46284639, 0xfb0af014, 
+    0x464b221c, 0x46404639, 0xfb04f014, 0x464b221c, 0x46304639, 0xfafef014, 0x4653123f, 0x46392214, 
+    0xf0144620, 0x2214faf7, 0x46394653, 0xf0144628, 0x2214faf1, 0x46394653, 0xf0144640, 0x2214faeb, 
+    0x46394653, 0xf0144630, 0x2208fae5, 0x4620465b, 0x46390157, 0xfadef014, 0x465b2208, 0x46284639, 
+    0xfad8f014, 0x465b2208, 0x46404639, 0xfad2f014, 0x465b2208, 0x46304639, 0xfaccf014, 0x9b03013f, 
+    0x4639220c, 0xf0144620, 0x9b03fac5, 0x4639220c, 0xf0144628, 0x9b03fabf, 0x4639220c, 0xf0144640, 
+    0x9b03fab9, 0x4639b004, 0x220c4630, 0x5ff0e8bd, 0xbab0f014, 0x2200b510, 0x211f4604, 0x48af4603, 
+    0xfabff014, 0x220048ae, 0x4623211f, 0xfab9f014, 0x220048ac, 0x4623211f, 0xfab3f014, 0x46232200, 
+    0x4010e8bd, 0x211f48a8, 0xbaabf014, 0x4605b570, 0x48a24603, 0x4400f647, 0x4621220a, 0xf0141e80, 
+    0x489ffaa0, 0x462b220a, 0x1e804621, 0xfa99f014, 0x220a489c, 0x4621462b, 0xf0141e80, 0x489afa92, 
+    0x4621462b, 0x4070e8bd, 0x1e80220a, 0xba89f014, 0x4604b510, 0x48914601, 0xf0143810, 0x4890fa68, 
+    0x38104621, 0xfa63f014, 0x4621488e, 0xf0143810, 0x488dfa5e, 0xe8bd4621, 0x38104010, 0xba57f014, 
+    0x4604b510, 0x48854601, 0xf0143812, 0x4884fa50, 0x38124621, 0xfa4bf014, 0x46214882, 0xf0143812, 
+    0x4881fa46, 0xe8bd4621, 0x38124010, 0xba3ff014, 0x4604b510, 0x48794601, 0xf0143814, 0x4878fa38, 
+    0x38144621, 0xfa33f014, 0x46214876, 0xf0143814, 0x4875fa2e, 0xe8bd4621, 0x38144010, 0xba27f014, 
+    0x4604b510, 0x486d4601, 0xf0143816, 0x486cfa20, 0x38164621, 0xfa1bf014, 0x4621486a, 0xf0143816, 
+    0x4869fa16, 0xe8bd4621, 0x38164010, 0xba0ff014, 0x4604b510, 0x48614601, 0xf0143826, 0x4860fa08, 
+    0x38264621, 0xfa03f014, 0x4621485e, 0xf0143826, 0x485df9fe, 0xe8bd4621, 0x38264010, 0xb9f7f014, 
+    0x5fffe92d, 0xf2484d59, 0x46920400, 0x220f468b, 0x46034681, 0x46284621, 0xfa03f014, 0x0600f247, 
+    0x220c465b, 0x46284631, 0xf9fbf014, 0x465310f7, 0x46392209, 0xf0144628, 0xf240f9f4, 0x9b031880, 
+    0x46412207, 0xf0144628, 0x9b0ef9ec, 0x21602205, 0xf0144628, 0x9b0ff9e6, 0x21102204, 0xf0144628, 
+    0x9b10f9e0, 0x21082203, 0xf0144628, 0x9b11f9da, 0x21072200, 0xf0144628, 0x4d3df9d4, 0x464b220f, 
+    0x46284621, 0xf9cdf014, 0x465b220c, 0x46284631, 0xf9c7f014, 0x46532209, 0x46284639, 0xf9c1f014, 
+    0x22079b03, 0x46284641, 0xf9bbf014, 0x22059b0e, 0x46282160, 0xf9b5f014, 0x22049b0f, 0x46282110, 
+    0xf9aff014, 0x22039b10, 0x46282108, 0xf9a9f014, 0x22009b11, 0x46282107, 0xf9a3f014, 0x220f4d25, 
+    0x4621464b, 0xf0144628, 0x220cf99c, 0x4631465b, 0xf0144628, 0x2209f996, 0x46394653, 0xf0144628, 
+    0x9b03f990, 0x46412207, 0xf0144628, 0x9b0ef98a, 0x21602205, 0xf0144628, 0x9b0ff984, 0x21102204, 
+    0xf0144628, 0x9b10f97e, 0x21082203, 0xf0144628, 0x9b11f978, 0x21072200, 0xf0144628, 0x4621f972, 
+    0x220f4c0d, 0x4620464b, 0xf96bf014, 0x465b220c, 0x46204631, 0x0000e012, 0xf10008b0, 0xf203c668, 
+    0xf203ce68, 0xf203d668, 0xf203de68, 0xf203c486, 0xf203cc86, 0xf203d486, 0xf203dc86, 0xf951f014, 
+    0x46532209, 0x46204639, 0xf94bf014, 0x22079b03, 0x46204641, 0xf945f014, 0x22059b0e, 0x46202160, 
+    0xf93ff014, 0x22049b0f, 0x46202110, 0xf939f014, 0x22039b10, 0x46202108, 0xf933f014, 0xb0049b11, 
+    0x22004620, 0x5ff0e8bd, 0xf0142107, 0xe92db92a, 0x460541f0, 0x36fff240, 0x460f0044, 0xf8312200, 
+    0x46313015, 0x442048fd, 0xf91bf014, 0x0545eb07, 0x220048fb, 0x44204631, 0xf01488eb, 0x48f9f912, 
+    0x89ab2200, 0x44204631, 0xf90bf014, 0x463148f6, 0x22008a6b, 0xe8bd4420, 0xf01441f0, 0xeb00b902, 
+    0xb57000c0, 0x48ed0045, 0x76fff240, 0x3840460c, 0x22004631, 0xf0144428, 0x8020f902, 0x48e82200, 
+    0x38404631, 0xf0144428, 0x80a0f8fa, 0x48e52200, 0x38404631, 0xf0144428, 0x8120f8f2, 0x48e22200, 
+    0x38404631, 0xf0144428, 0x81a0f8ea, 0x48db2200, 0x383e4631, 0xf0144428, 0x8060f8e2, 0x48d82200, 
+    0x383e4631, 0xf0144428, 0x80e0f8da, 0x48d52200, 0x383e4631, 0xf0144428, 0x8160f8d2, 0x48d22200, 
+    0x383e4631, 0xf0144428, 0x2100f8ca, 0x4500f240, 0x200081e0, 0x0381eb04, 0x2010f933, 0xdb0142aa, 
+    0x6200f5a2, 0x2010f823, 0xb2401c40, 0xdbf32802, 0xb2491c49, 0xdbec2904, 0xb510bd70, 0x46034604, 
+    0x220048be, 0x30302101, 0xf89bf014, 0x220048bc, 0x46232101, 0xf0143030, 0x48baf894, 0x21012200, 
+    0x30304623, 0xf88df014, 0x220048b7, 0x46232101, 0x4010e8bd, 0xf0143030, 0xe92db884, 0x4daf43f8, 
+    0x0000f44f, 0x4faf4eae, 0xf8df3534, 0x363482bc, 0x37344cae, 0x0834f108, 0xe0069000, 0x46222102, 
+    0xf7ef4668, 0x2801ffde, 0x2200d01b, 0x21014628, 0xf875f014, 0xd0f12800, 0x46302200, 0xf0142101, 
+    0x2800f86e, 0x2200d0ea, 0x21014638, 0xf867f014, 0xd0e32800, 0x46402200, 0xf0142101, 0x2800f860, 
+    0xe8bdd0dc, 0xe92d83f8, 0xeb0041f0, 0xf24000c0, 0x880b77ff, 0x00444615, 0x22004890, 0x3840460e, 
+    0x44204639, 0xf83df014, 0x2200488d, 0x463988b3, 0x44203840, 0xf835f014, 0x2200488a, 0x46398933, 
+    0x44203840, 0xf82df014, 0x22004887, 0x463989b3, 0x44203840, 0xf825f014, 0x22004880, 0x46398873, 
+    0x4420383e, 0xf81df014, 0x2200487d, 0x463988f3, 0x4420383e, 0xf815f014, 0x2200487a, 0x46398973, 
+    0x4420383e, 0xf80df014, 0x22004877, 0x463989f3, 0x4420383e, 0xf805f014, 0x22004870, 0x4639882b, 
+    0x4420383c, 0xfffdf013, 0x2200486d, 0x463989eb, 0x4420383c, 0xfff5f013, 0x2200486a, 0x46398bab, 
+    0x4420383c, 0xffedf013, 0x22004867, 0x46398d6b, 0x4420383c, 0xffe5f013, 0x22004860, 0x4639886b, 
+    0x4420383a, 0xffddf013, 0x2200485d, 0x46398a2b, 0x4420383a, 0xffd5f013, 0x2200485a, 0x46398beb, 
+    0x4420383a, 0xffcdf013, 0x22004857, 0x46398dab, 0x4420383a, 0xffc5f013, 0x22004850, 0x463988ab, 
+    0x44203838, 0xffbdf013, 0x2200484d, 0x46398a6b, 0x44203838, 0xffb5f013, 0x2200484a, 0x46398c2b, 
+    0x44203838, 0xffadf013, 0x22004847, 0x46398deb, 0x44203838, 0xffa5f013, 0x22004840, 0x463988eb, 
+    0x44203836, 0xff9df013, 0x2200483d, 0x46398aab, 0x44203836, 0xff95f013, 0x2200483a, 0x46398c6b, 
+    0x44203836, 0xff8df013, 0x22004837, 0x46398e2b, 0x44203836, 0xff85f013, 0x22004830, 0x4639892b, 
+    0x44203834, 0xff7df013, 0x2200482d, 0x46398aeb, 0x44203834, 0xff75f013, 0x2200482a, 0x46398cab, 
+    0x44203834, 0xff6df013, 0x22004827, 0x46398e6b, 0x44203834, 0xff65f013, 0x22004820, 0x4639896b, 
+    0x44203832, 0xff5df013, 0x2200481d, 0x46398b2b, 0x44203832, 0xff55f013, 0x2200481a, 0x46398ceb, 
+    0x44203832, 0xff4df013, 0x22004817, 0x46398eab, 0x44203832, 0xff45f013, 0x22004810, 0x463989ab, 
+    0x44203830, 0xff3df013, 0x2200480d, 0x46398b6b, 0x44203830, 0xff35f013, 0x2200480a, 0x46398d2b, 
+    0x44203830, 0xff2df013, 0x22004807, 0x46398eeb, 0x44203830, 0x41f0e8bd, 0xbf23f013, 0xf203c450, 
+    0xf203cc50, 0xf203d450, 0xf203dc50, 0xf203517a, 0x2200b510, 0x217f4604, 0x48fd4603, 0xff11f013, 
+    0x220048fc, 0x4623217f, 0xff0bf013, 0x220048fa, 0x4623217f, 0xff05f013, 0x46232200, 0x4010e8bd, 
+    0x217f48f6, 0xbefdf013, 0x47f0e92d, 0x22004ff0, 0x213f8983, 0x46041ebf, 0xf0134638, 0x4dedfef2, 
+    0x8ba32200, 0x1ead213f, 0xf0134628, 0xf8dffeea, 0x220083a8, 0x213f8da3, 0x0802f1a8, 0xf0134640, 
+    0xf8dffee0, 0x22009398, 0x213f8fa3, 0x0902f1a9, 0xf0134648, 0xf643fed6, 0x89e37600, 0x46312208, 
+    0xf0134638, 0x8be3fece, 0x46312208, 0xf0134628, 0x8de3fec8, 0x46312208, 0xf0134640, 0x8fe3fec2, 
+    0x46484631, 0x47f0e8bd, 0xf0132208, 0xe92dbeba, 0x4fcf47f0, 0x89032200, 0x1f3f213f, 0x46384604, 
+    0xfeaff013, 0x22004dcb, 0x213f8b23, 0x46281f2d, 0xfea7f013, 0x8320f8df, 0x8d232200, 0xf1a8213f, 
+    0x46400804, 0xfe9df013, 0x9310f8df, 0x8f232200, 0xf1a9213f, 0x46480904, 0xfe93f013, 0x7600f643, 
+    0x22088963, 0x46384631, 0xfe8bf013, 0x22088b63, 0x46284631, 0xfe85f013, 0x22088d63, 0x46404631, 
+    0xfe7ff013, 0x46318f63, 0xe8bd4648, 0x220847f0, 0xbe77f013, 0x47f0e92d, 0x22004fad, 0x213f8883, 
+    0x46041fbf, 0xf0134638, 0x4daafe6c, 0x8aa32200, 0x1fad213f, 0xf0134628, 0xf8dffe64, 0x2200829c, 
+    0x213f8ca3, 0x0806f1a8, 0xf0134640, 0xf8dffe5a, 0x2200928c, 0x213f8ea3, 0x0906f1a9, 0xf0134648, 
+    0xf643fe50, 0x88e37600, 0x46312208, 0xf0134638, 0x8ae3fe48, 0x46312208, 0xf0134628, 0x8ce3fe42, 
+    0x46312208, 0xf0134640, 0x8ee3fe3c, 0x46484631, 0x47f0e8bd, 0xf0132208, 0xe92dbe34, 0x4f8c47f0, 
+    0x88032200, 0x3f08213f, 0x46384604, 0xfe29f013, 0x22004d88, 0x213f8a23, 0x46283d08, 0xfe21f013, 
+    0x8214f8df, 0x8c232200, 0xf1a8213f, 0x46400808, 0xfe17f013, 0x9204f8df, 0x8e232200, 0xf1a9213f, 
+    0x46480908, 0xfe0df013, 0x7600f643, 0x22088863, 0x46384631, 0xfe05f013, 0x22088a63, 0x46284631, 
+    0xfdfff013, 0x22088c63, 0x46404631, 0xfdf9f013, 0x46318e63, 0xe8bd4648, 0x220847f0, 0xbdf1f013, 
+    0x8803b510, 0x213e2201, 0x486d4604, 0xfde9f013, 0x22018863, 0x213e486b, 0xfde3f013, 0x220188a3, 
+    0x213e4869, 0xfdddf013, 0x220188e3, 0x4010e8bd, 0x213e4866, 0xbdd5f013, 0x2201b510, 0x213e4604, 
+    0x485f4603, 0xfdcdf013, 0x2201485e, 0x4623213e, 0xfdc7f013, 0x2201485c, 0x4623213e, 0xfdc1f013, 
+    0x46232201, 0x4010e8bd, 0x213e4858, 0xbdb9f013, 0x4604b510, 0x48524601, 0xf013301a, 0x4851fd98, 
+    0x301a4621, 0xfd93f013, 0x4621484f, 0xf013301a, 0x484efd8e, 0xe8bd4621, 0x301a4010, 0xbd87f013, 
+    0xb283b510, 0x48424604, 0x217f2200, 0xf01330a2, 0x483ffd98, 0x2200b2a3, 0x30b2217f, 0xfd91f013, 
+    0xb2a3483b, 0x217f2200, 0xf01330c2, 0x4839fd8a, 0x2200b2a3, 0x30a2217f, 0xfd83f013, 0xb2a34835, 
+    0x217f2200, 0xf01330b2, 0x4832fd7c, 0x2200b2a3, 0x30c2217f, 0xfd75f013, 0xb2a3482f, 0x217f2200, 
+    0xf01330a2, 0x482cfd6e, 0x2200b2a3, 0x30b2217f, 0xfd67f013, 0xb2a34828, 0x217f2200, 0xf01330c2, 
+    0x4826fd60, 0x2200b2a3, 0x30a2217f, 0xfd59f013, 0xb2a34822, 0x217f2200, 0xf01330b2, 0x481ffd52, 
+    0x2200b2a3, 0xe8bd217f, 0x30c24010, 0xbd49f013, 0x4604b510, 0x481a4601, 0xf0133038, 0x4819fd28, 
+    0x30384621, 0xfd23f013, 0x46214817, 0xf0133038, 0x4816fd1e, 0xe8bd4621, 0x30384010, 0xbd17f013, 
+    0x4604b510, 0x480e4601, 0xf0133008, 0x480dfd10, 0x30084621, 0xfd0bf013, 0x4621480b, 0xf0133008, 
+    0x480afd06, 0xe8bd4621, 0x30084010, 0xbcfff013, 0xf203c468, 0xf203cc68, 0xf203d468, 0xf203dc68, 
+    0xf203c640, 0xf203ce40, 0xf203d640, 0xf203de40, 0xf241b570, 0x46050400, 0x4603220c, 0x462148fe, 
+    0xfcfff013, 0x220c48fd, 0x4621462b, 0xfcf9f013, 0x220c48fb, 0x4621462b, 0xfcf3f013, 0x4621462b, 
+    0x4070e8bd, 0x220c48f7, 0xbcebf013, 0x4604b510, 0x48f14601, 0xf0133030, 0x48f0fcca, 0x30304621, 
+    0xfcc5f013, 0x462148ee, 0xf0133030, 0x48edfcc0, 0xe8bd4621, 0x30304010, 0xbcb9f013, 0xb283b510, 
+    0x48e54604, 0x217f2200, 0xf01338be, 0x48e2fcca, 0x2200b2a3, 0x38ae217f, 0xfcc3f013, 0xb2a348de, 
+    0x217f2200, 0xf013389e, 0x48dcfcbc, 0x2200b2a3, 0x38be217f, 0xfcb5f013, 0xb2a348d8, 0x217f2200, 
+    0xf01338ae, 0x48d5fcae, 0x2200b2a3, 0x389e217f, 0xfca7f013, 0xb2a348d2, 0x217f2200, 0xf01338be, 
+    0x48cffca0, 0x2200b2a3, 0x38ae217f, 0xfc99f013, 0xb2a348cb, 0x217f2200, 0xf013389e, 0x48c9fc92, 
+    0x2200b2a3, 0x38be217f, 0xfc8bf013, 0xb2a348c5, 0x217f2200, 0xf01338ae, 0x48c2fc84, 0x2200b2a3, 
+    0xe8bd217f, 0x389e4010, 0xbc7bf013, 0xb283b510, 0x48bd4604, 0x217f2200, 0xfc73f013, 0xb2a348ba, 
+    0x217f2200, 0xf0133010, 0x48b7fc6c, 0x2200b2a3, 0x3020217f, 0xfc65f013, 0x48b4b2a3, 0x217f2200, 
+    0xfc5ff013, 0xb2a348b1, 0x217f2200, 0xf0133010, 0x48aefc58, 0x2200b2a3, 0x3020217f, 0xfc51f013, 
+    0x48abb2a3, 0x217f2200, 0xfc4bf013, 0xb2a348a8, 0x217f2200, 0xf0133010, 0x48a5fc44, 0x2200b2a3, 
+    0x3020217f, 0xfc3df013, 0x48a2b2a3, 0x217f2200, 0xfc37f013, 0xb2a3489f, 0x217f2200, 0xf0133010, 
+    0x489cfc30, 0x2200b2a3, 0xe8bd217f, 0x30204010, 0xbc27f013, 0x4604b510, 0x488f4603, 0x21402206, 
+    0xf013300c, 0x488dfc1e, 0x21402206, 0x300c4623, 0xfc17f013, 0x2206488a, 0x46232140, 0xf013300c, 
+    0x4888fc10, 0x21402206, 0xe8bd4623, 0x300c4010, 0xbc07f013, 0xb283b510, 0x48834604, 0x217f2200, 
+    0xf0131f00, 0x4880fbfe, 0x2200b2a3, 0x300c217f, 0xfbf7f013, 0xb2a3487c, 0x217f2200, 0xf013301c, 
+    0x487afbf0, 0x2200b2a3, 0x1f00217f, 0xfbe9f013, 0xb2a34876, 0x217f2200, 0xf013300c, 0x4873fbe2, 
+    0x2200b2a3, 0x301c217f, 0xfbdbf013, 0xb2a34870, 0x217f2200, 0xf0131f00, 0x486dfbd4, 0x2200b2a3, 
+    0x300c217f, 0xfbcdf013, 0xb2a34869, 0x217f2200, 0xf013301c, 0x4867fbc6, 0x2200b2a3, 0x1f00217f, 
+    0xfbbff013, 0xb2a34863, 0x217f2200, 0xf013300c, 0x4860fbb8, 0x2200b2a3, 0xe8bd217f, 0x301c4010, 
+    0xbbaff013, 0x4604b510, 0x48574603, 0x21012200, 0xf0133884, 0x4855fba6, 0x21012200, 0x38844623, 
+    0xfb9ff013, 0x22004852, 0x46232101, 0xf0133884, 0x4850fb98, 0x21012200, 0xe8bd4623, 0x38844010, 
+    0xbb8ff013, 0x2200b510, 0x21014604, 0x48424603, 0xfb87f013, 0x22004841, 0x46232101, 0xfb81f013, 
+    0x2200483f, 0x46232101, 0xfb7bf013, 0x46232200, 0x4010e8bd, 0x2101483b, 0xbb73f013, 0x4604b510, 
+    0x48354603, 0x21012200, 0xf013300e, 0x4833fb6a, 0x21012200, 0x300e4623, 0xfb63f013, 0x22004830, 
+    0x46232101, 0xf013300e, 0x482efb5c, 0x21012200, 0xe8bd4623, 0x300e4010, 0xbb53f013, 0x4605b570, 
+    0x48254603, 0x0400f244, 0x4621220e, 0xf013300e, 0x4822fb48, 0x462b220e, 0x300e4621, 0xfb41f013, 
+    0x220e481f, 0x4621462b, 0xf013300e, 0x481dfb3a, 0x4621462b, 0x4070e8bd, 0x300e220e, 0xbb31f013, 
+    0x4ff0e92d, 0x11f4f240, 0x070cb0bb, 0xf7e84620, 0xf241f95a, 0x462071a0, 0xf944f7e8, 0x46204e16, 
+    0xf7e84631, 0x2001f93f, 0xffc8f7ff, 0xf7ff2001, 0x2000ffa5, 0xfa71f7ff, 0x23064810, 0x211e2201, 
+    0xfb0ff013, 0x21012300, 0x4608461a, 0xff9cf7fe, 0xf7ff2001, 0xe013ff77, 0xf203c640, 0xf203ce40, 
+    0xf203d640, 0xf203de40, 0xf203c506, 0xf203cd06, 0xf203d506, 0xf203dd06, 0xdcba01f5, 0xf203e80c, 
+    0xf7ff2000, 0x2001ff5f, 0xff5cf7ff, 0xf7ff2000, 0x2008ff39, 0xf83af7ff, 0xf7ff2008, 0xf240f81b, 
+    0xf7ff10e0, 0xf240f8b5, 0x462011f4, 0xf90bf7e8, 0x71a1f241, 0xf7e84620, 0x4631f8f5, 0xf7e84620, 
+    0x2040f8f1, 0xfec6f7ff, 0xf7ff2001, 0x20fffea3, 0xf886f7ff, 0xf7ff20ff, 0x1527f86b, 0xf7ff4638, 
+    0x2000f84f, 0xf834f7ff, 0xf7ff2000, 0x2001fd01, 0xfcfef7ff, 0x20402100, 0xf98ef7ef, 0xf7ff2000, 
+    0x20fffcf7, 0xf86cf7ff, 0xf7ff20ff, 0x2000f851, 0xf836f7ff, 0xf7ff2000, 0x2000f81b, 0xfe26f7ff, 
+    0x11f4f240, 0xf7e84620, 0xf241f8ce, 0x462071a3, 0xf8b8f7e8, 0x46204631, 0xf8b4f7e8, 0xf7ff2000, 
+    0x14e0fdbd, 0xfd5cf7ff, 0xf7ff20ff, 0x20fff849, 0xf82ef7ff, 0xf7ff1420, 0xf640f813, 0x46287500, 
+    0xfff6f7fe, 0xf7ff2001, 0xf240fd73, 0x46401800, 0xfd8cf7ff, 0xf7ff1460, 0xf642fd2b, 0xf7ff0000, 
+    0x2100fd27, 0xf7ef4640, 0x2100f947, 0xf7ef4640, 0x2000f943, 0xfd5cf7ff, 0xf7ff2000, 0x2000fd31, 
+    0xfd16f7ff, 0xf7ff20ff, 0x20fff81b, 0xf800f7ff, 0xf7fe2000, 0x2000ffe5, 0xffcaf7fe, 0x11f4f240, 
+    0xf7e84620, 0xf241f880, 0x462071a4, 0xf86af7e8, 0x46204631, 0xf866f7e8, 0xf7ff2040, 0x20fffca1, 
+    0xfffef7fe, 0xf7fe20ff, 0x4638ffe3, 0xffc8f7fe, 0xf7fe4628, 0x2000ffad, 0xfc7af7ff, 0xf7ff4640, 
+    0x2100fc77, 0xf7ef2040, 0x2000f907, 0xfc70f7ff, 0xf7fe20ff, 0x20ffffe5, 0xffcaf7fe, 0xf7fe2000, 
+    0x2000ffaf, 0xff94f7fe, 0x11f4f240, 0xf7e84620, 0xf241f84a, 0x462071a5, 0xf834f7e8, 0x46204631, 
+    0xf830f7e8, 0xf7ff2000, 0x2003fc37, 0x94002400, 0x46212302, 0x4002e9cd, 0x46202206, 0xf7fe9401, 
+    0xf244ffef, 0xf7fe0080, 0x4628ff8b, 0xff70f7fe, 0x22012000, 0x540aa93a, 0xf821a930, 0x1c404010, 
+    0x2804b240, 0xf8dfdbf6, 0xf04f93fc, 0xf8df0800, 0xf8dfa3f8, 0x4efeb3f8, 0x20002100, 0x02c1eb01, 
+    0x0282eb06, 0xf8422300, 0x1c403020, 0x2802b240, 0x1c49dbf8, 0x2904b249, 0x2700dbef, 0xe06b2400, 
+    0xd0692c00, 0x10fff240, 0xff8af7fe, 0x10fef240, 0xff6ef7fe, 0x20402100, 0xf89ef7ef, 0xf7ff2001, 
+    0x2100f91c, 0xf7ef2040, 0xf7fff897, 0x2100f936, 0xf7ef2040, 0x4648f891, 0xf996f013, 0x1024f856, 
+    0xf080fa01, 0x0024f846, 0xf0134650, 0xeb06f98d, 0x6a690584, 0xf080fa01, 0x46586268, 0xf984f013, 
+    0xfa016ca9, 0x64a8f080, 0xf01348da, 0x6ee9f97d, 0xf080fa01, 0x200066e8, 0xf8eff7ff, 0xb2641c64, 
+    0xdbbd2c02, 0xb27f1c7f, 0xdbb72f10, 0x20002100, 0x02c1eb01, 0x0282eb06, 0x3020f852, 0x111b3308, 
+    0x3020f842, 0xb2401c40, 0xdbf52802, 0xb2491c49, 0xdbec2904, 0xab3a2000, 0x01c0eb00, 0x0281eb06, 
+    0x1021f856, 0x1a616854, 0xd5006091, 0x60914249, 0x2a015c1a, 0xe018d005, 0xf7fe20ff, 0x20ffff21, 
+    0xf5b1e796, 0xda045fd0, 0xf831a930, 0x1c522010, 0xf5b1e006, 0xdd065ff0, 0xf831a930, 0x1e522010, 
+    0x2010f821, 0x2100e001, 0x1c405419, 0x2804b240, 0xa830dbd2, 0xfb54f7ff, 0x0001f108, 0xf880fa0f, 
+    0x0f0ff1b8, 0xaf58f6ff, 0x25002004, 0x23029500, 0xe9cd462a, 0x46295002, 0x95014628, 0xff20f7fe, 
+    0xf7fe20ff, 0x20fffeed, 0xfed2f7fe, 0xf7fe2000, 0x2000feb7, 0xfe9cf7fe, 0x11f4f240, 0x4620070c, 
+    0xff51f7e7, 0x71a6f241, 0xf7e74620, 0x499aff3b, 0xf7e74620, 0x2100ff37, 0x2000ab04, 0x1201eb03, 
+    0x5010f822, 0xb2401c40, 0xdbf92808, 0xb2491c49, 0xdbf22904, 0xf7ff4618, 0xa804fad0, 0xfa8af7ff, 
+    0xf7ffa804, 0xa804fa44, 0xf9fef7ff, 0xf7ff2000, 0x20fff9df, 0xfeb4f7fe, 0xf7fe20ff, 0xf645fe99, 
+    0xf7fe0080, 0xf640fe7d, 0xf7fe7000, 0x2002fe61, 0x21009500, 0x23019501, 0x5002e9cd, 0x46082206, 
+    0xfecef7fe, 0x46a82100, 0x46422000, 0x03c1eb01, 0x0383eb06, 0xf8434690, 0x1c402020, 0x2804b240, 
+    0x1c49dbf8, 0x2904b249, 0x2700dbee, 0xe0072400, 0x2c01b134, 0x2c02d007, 0x2c03d008, 0xe008d10d, 
+    0x7000f640, 0xf640e007, 0xe0047001, 0x7002f640, 0xf640e001, 0xf7fe7003, 0x2100fe2b, 0xf7ee2040, 
+    0x2001ff8b, 0xf809f7ff, 0x20402100, 0xff84f7ee, 0xf823f7ff, 0x20402100, 0xff7ef7ee, 0xf0134859, 
+    0xf856f883, 0xfa011024, 0xf846f080, 0x48560024, 0xf87af013, 0x0584eb06, 0xfa016a69, 0x6268f080, 
+    0xf0134852, 0x6ca9f871, 0xf080fa01, 0x485164a8, 0xf86af013, 0xfa016ee9, 0x66e8f080, 0xf7fe2000, 
+    0x1c64ffdc, 0x2c04b264, 0x1c7fdbb2, 0x2f80b23f, 0x2400dbac, 0x2900f44f, 0xad2caf04, 0x02c4eb04, 
+    0x0082eb06, 0x2022f856, 0x3102e9d0, 0x1acb6840, 0x18801a18, 0x0024f845, 0x2000d401, 0x4240e000, 
+    0xf8454548, 0xdb000024, 0xab2c483c, 0xf8431a89, 0x03400024, 0x11cff341, 0xda002900, 0xb2094249, 
+    0xd06d2900, 0xf101fb11, 0xf0130889, 0xa932ffe1, 0x0200f242, 0x0024f841, 0x01c0eb00, 0x1100eb01, 
+    0x1181eb02, 0xeb070b8b, 0x800b1104, 0x1300eb00, 0x1340eb03, 0x1383eb02, 0x804b0b9b, 0x1340eb00, 
+    0x2300eb03, 0x1303eb02, 0x808b0b9b, 0x1369f240, 0xeb024343, 0x0b9b1303, 0xebc080cb, 0xebc31380, 
+    0xeb0203c3, 0x0b9b1303, 0xeb00810b, 0xeb031300, 0xeb022340, 0x0b9b1303, 0xf240814b, 0x43432371, 
+    0x1303eb02, 0x818b0b9b, 0x23d9f240, 0xeb024358, 0x0b801000, 0x200081c8, 0x1204eb07, 0x1010f832, 
+    0xd3002940, 0xf822213f, 0x1c401010, 0x2808b240, 0x1c64dbf4, 0x2c04b264, 0xa804db80, 0xf9bdf7ff, 
+    0xe00ea804, 0xf203c4a0, 0xf203cca0, 0xf203d4a0, 0x0004e520, 0xf203dca0, 0xdcba01f5, 0x0007ffff, 
+    0xf7ffe086, 0xa804f967, 0xf921f7ff, 0xf7ffa804, 0x2000f8db, 0xf8bcf7ff, 0xf8cd2404, 0x22008000, 
+    0x8004f8cd, 0x46112302, 0x8402e9cd, 0xf7fe4610, 0x20fffdb7, 0xfd84f7fe, 0xf7fe20ff, 0x2000fd69, 
+    0xfd4ef7fe, 0xf7fe2000, 0xf240fd33, 0x070d11f4, 0xf7e74628, 0xf241fde8, 0x462871a7, 0xfdd2f7e7, 
+    0x462849f8, 0xfdcef7e7, 0xf7fe20ff, 0x20fffd69, 0xfd4ef7fe, 0x0080f244, 0xfd32f7fe, 0x7000f640, 
+    0xfd16f7fe, 0x0900f04f, 0xab142100, 0xad22460c, 0x02c1ebc1, 0xeb032000, 0xf8220242, 0x1c404010, 
+    0x2808b240, 0x2000dbf9, 0x0281eb05, 0x4010f822, 0xb2401c40, 0xdbf92802, 0xb2491c49, 0xdbe72904, 
+    0x4629461a, 0xf7fe4648, 0x2002ff2e, 0x01fff009, 0xe9cd4603, 0x21001400, 0x4002e9cd, 0x46082206, 
+    0xfd5ef7fe, 0x21004bd8, 0xeb012000, 0xeb0302c1, 0x46980282, 0x4020f842, 0xb2401c40, 0xdbf82809, 
+    0xb2491c49, 0xdbef2904, 0x25002700, 0xe02e462c, 0x46412000, 0x1204eb07, 0x1010f822, 0xb2401c40, 
+    0xdbf92808, 0xb314e747, 0xd0232c01, 0xd07d2c02, 0xd01f2c03, 0xd07a2c04, 0xd01b2c05, 0xd0772c06, 
+    0xd0172c07, 0xd0742c08, 0xd0132c09, 0xd0712c0a, 0xd00f2c0b, 0xd06e2c0c, 0xd00b2c0d, 0xd06b2c0e, 
+    0xd0072c0f, 0xd0682c10, 0xd1092c11, 0xf240e002, 0xe00010ff, 0xf7fe20ff, 0x20fffce3, 0xfcc8f7fe, 
+    0x20402100, 0xfdf8f7ee, 0xf7fe2001, 0x2100fe76, 0xf7ee2040, 0xf7fefdf1, 0x2100fe90, 0xf7ee2040, 
+    0x07e0fdeb, 0xd07c48a9, 0xfeeef012, 0x1025f858, 0x4646b200, 0xf8481a08, 0x48a50025, 0xfee4f012, 
+    0x0685eb06, 0x6a71b200, 0x62701a08, 0xf01248a1, 0x6cb1fedb, 0x1a08b200, 0x489f64b0, 0xfed4f012, 
+    0xb2006ef1, 0x66f01a08, 0xb26d1c6d, 0xf7fe2000, 0x1c64fe44, 0x2c12b264, 0x1c7fdb95, 0x2f80b23f, 
+    0x2100db83, 0x20004643, 0x02c1eb01, 0x0282eb03, 0x4020f852, 0x11e43440, 0x4020f842, 0xb2401c40, 
+    0xdbf52809, 0xb2491c49, 0xe0072904, 0xe0e6e0e1, 0xe0f2e0ec, 0xe0fee0f8, 0xe124e11e, 0x2100dbe3, 
+    0xab364a81, 0x00c1eb01, 0x4020f852, 0x0280eb02, 0x68509403, 0xf8434420, 0x68960021, 0xe00cf8d2, 
+    0x46f30333, 0xf7f0fb93, 0x030eeb06, 0xfb94031c, 0xf504f4f0, 0x69145800, 0x032d191d, 0xf5f0fb95, 
+    0x5500f505, 0x69559500, 0x0c05eb04, 0x0c43eb0c, 0x3c0cea4f, 0xfef0fb9c, 0x4e80f50e, 0xe004f8cd, 
+    0xe0f7e000, 0xe018f8d2, 0x1606ebc6, 0x160beb06, 0x0c0eeb05, 0xea4f46f2, 0xeb0e0e83, 0x44f40e44, 
+    0x0e84ea4f, 0x03c3eb0a, 0x0e45eb0e, 0xf8d24473, 0xeba6e01c, 0xf8cd060b, 0xeb06e008, 0x6a1204c4, 
+    0x0485eb04, 0x044aeb04, 0x44744473, 0x3c0cea4f, 0x9c034422, 0xfb9c031b, 0x0312fcf0, 0xf3f0fb93, 
+    0xf2f0fb92, 0xe9dd0324, 0xfb945e00, 0xf507faf0, 0xeb075780, 0xeb050008, 0xf8df040e, 0x4420e144, 
+    0x4c00f50c, 0xf5034460, 0x44183380, 0x32f0f502, 0xf5004410, 0x033c5080, 0xfb941100, 0x4c47f5f0, 
+    0xf5caaf14, 0xfa045b80, 0xebc1f685, 0xea4f05c1, 0xf8273408, 0xfb946015, 0xeb07f6f0, 0xfa0e0445, 
+    0x8066f686, 0x032d9d00, 0xf6f0fb95, 0xfa0e031b, 0x80a5f586, 0xe004f8dd, 0x350eea4f, 0xf6f0fb95, 
+    0xfa054d38, 0x80e5f586, 0x350cea4f, 0xf6f0fb95, 0xfa054d35, 0x8125f586, 0xf5f0fb93, 0x03124b33, 
+    0xf385fa03, 0xfb928163, 0x4a31f3f0, 0xf283fa02, 0xea4f81a2, 0xf240320a, 0xfb923aff, 0x4a2df3f0, 
+    0xf583fa02, 0xf823ab22, 0xea4f5021, 0xf240350b, 0xfb954b00, 0xfa02f0f0, 0xeb03f080, 0x4b1f0281, 
+    0x20008050, 0x2010f934, 0xdb75455a, 0xa010f824, 0x20ffe076, 0xfba4f7fe, 0x10fef240, 0xf240e6be, 
+    0xf7fe30fe, 0xf240fb9d, 0xe6b730fd, 0x70fcf240, 0xfb96f7fe, 0x70fbf240, 0xf640e6b0, 0xf7fe40fb, 
+    0xf640fb8f, 0xe6a940f7, 0x40f3f641, 0xfb88f7fe, 0x40eff641, 0xf643e6a2, 0xf7fe40e3, 0xf643fb81, 
+    0xe69b40df, 0xdcba01f5, 0x0004e520, 0xf203c4a0, 0xf203cca0, 0xf203d4a0, 0xf203dca0, 0xfffffc00, 
+    0xfffff800, 0xfffff000, 0xffffe000, 0xffffc000, 0xffff8800, 0xfffffe00, 0x40c3f647, 0xfb60f7fe, 
+    0x40bff647, 0xf64fe67a, 0xf7fe0087, 0xf64ffb59, 0xe673007f, 0xfd78f012, 0x1025f858, 0xfa014646, 
+    0xf848f080, 0x48fe0025, 0xfd6ef012, 0x0685eb06, 0xfa016a71, 0x6270f080, 0xf01248fa, 0x6cb1fd65, 
+    0xf080fa01, 0x48f864b0, 0xfd5ef012, 0xfa016ef1, 0x66f0f080, 0xe7ffe68a, 0xda01429a, 0x3010f824, 
+    0xb2401c40, 0xf6ff2807, 0x1c49af7d, 0x2904b249, 0xaea6f6ff, 0x463aa922, 0xf7fe4648, 0xf109fd14, 
+    0xfa4f0001, 0xf1b9f980, 0xf6ff0f03, 0x2104adbd, 0x90002000, 0x46022302, 0x0102e9cd, 0x90014601, 
+    0xfb3ef7fe, 0xf7fe20ff, 0x20fffb0b, 0xfaf0f7fe, 0xf7fe2000, 0x2000fad5, 0xfabaf7fe, 0x11f4f240, 
+    0x4620070c, 0xfb6ff7e7, 0x71a8f241, 0xf7e74620, 0x49d6fb59, 0xf7e74620, 0x2600fb55, 0x0998f10d, 
+    0x1123f240, 0x464a2000, 0x0340eb00, 0xeb021c40, 0xb2400343, 0xf8232804, 0xdbf51016, 0x4630a926, 
+    0xfbf5f7fe, 0xf7fe20ff, 0x20fffadb, 0xfac0f7fe, 0x0080f244, 0xfaa4f7fe, 0x7000f640, 0xfa88f7fe, 
+    0x24002105, 0xe9cdb2f0, 0xe9cd4102, 0x23020400, 0x22064621, 0xf7fe4620, 0x4bbdfaf3, 0x20002100, 
+    0x02c1eb01, 0x0282eb03, 0x4020f842, 0xb2401c40, 0xdbf92803, 0xb2491c49, 0xdbf02904, 0x46982400, 
+    0xb124e005, 0xd0052c01, 0xd10f2c02, 0xf240e007, 0xe00010ff, 0xf7fe20ff, 0x20fffaa3, 0x20ffe004, 
+    0xfa9ef7fe, 0x10fef240, 0xfa82f7fe, 0x20402100, 0xfbb2f7ee, 0xeb082700, 0x20010584, 0xfc2df7fe, 
+    0x20402100, 0xfba8f7ee, 0xfc47f7fe, 0x20402100, 0xfba2f7ee, 0xf012489f, 0xf858fca7, 0xfa022024, 
+    0x4897f180, 0x1024f848, 0xfc9ef012, 0xfa016a69, 0x6268f080, 0xf0124893, 0x6ca9fc97, 0xf080fa01, 
+    0x489164a8, 0xfc90f012, 0xfa016ee9, 0x66e8f080, 0xf7fe2000, 0x1c7ffc02, 0x2f10b23f, 0x1c64dbcd, 
+    0x2c03b264, 0x2100dbad, 0x20004645, 0x02c1eb01, 0x0282eb05, 0x3020f852, 0x111b3308, 0x3020f842, 
+    0xb2401c40, 0xdbf52803, 0xb2491c49, 0xdbec2904, 0x4630a922, 0xfb83f7fe, 0x46a82400, 0x465daf2c, 
+    0x00c4eb04, 0x2020f858, 0x0080eb08, 0x68806841, 0x0141eba2, 0xf8471809, 0xd5001024, 0xa8224249, 
+    0x1024f847, 0x2024f930, 0x0084eb00, 0x0002f9b0, 0x01c04410, 0x3000f510, 0x4240d500, 0xf0130100, 
+    0xeb04fbf7, 0xb2000244, 0x0142eb09, 0xf82142a8, 0xdb000016, 0x1c644650, 0x2c04b264, 0x0016f821, 
+    0xa926dbce, 0xf7fe4630, 0x1c76fb22, 0x2e03b276, 0xaf16f6ff, 0x20002104, 0x23029000, 0xe9cd4602, 
+    0x46010102, 0xf7fe9001, 0xf240fa2b, 0xf7fe1000, 0x2000fa0f, 0xf9f4f7fe, 0xf7fe2000, 0x2000f9d9, 
+    0xf9bef7fe, 0xf7fe2000, 0x2000f9a3, 0xf97ef7fe, 0xf7fe2000, 0xf240f95f, 0x070c11f4, 0xf7e74620, 
+    0x494dfa52, 0xf7e74620, 0x4948fa3d, 0xf7e74620, 0x484afa39, 0x22012300, 0xf012211e, 0xb03bfc12, 
+    0x8ff0e8bd, 0x23002201, 0x46104611, 0xf7feb510, 0x2001f89b, 0xf876f7ff, 0xf7ff2000, 0x2001f873, 
+    0xf870f7ff, 0xf7ff2000, 0xf240f84d, 0x46201400, 0xf9cef7fe, 0xf7fe2000, 0x2000f949, 0xf92af7fe, 
+    0xf7fe2000, 0x4836ff1b, 0x22082300, 0xf0124621, 0x4834fbe8, 0x22082300, 0xf0124621, 0x4832fbe2, 
+    0x22082300, 0xf0124621, 0x2300fbdc, 0xe8bd4621, 0x482e4010, 0xf0122208, 0x492dbbd4, 0x47707008, 
+    0x5fffe92d, 0xf2484d23, 0x46920400, 0x3d0a468b, 0x220f4681, 0x46214603, 0xf0124628, 0xf247fbc2, 
+    0x465b0600, 0x4631220c, 0xf0124628, 0x10f7fbba, 0x22094653, 0x46284639, 0xfbb3f012, 0x1880f240, 
+    0x22079b03, 0x46284641, 0xfbabf012, 0x22059b0e, 0x46282160, 0xfba5f012, 0x22049b0f, 0x46282110, 
+    0xfb9ff012, 0x22039b10, 0x46282108, 0xfb99f012, 0x22009b11, 0x46282107, 0xfb93f012, 0xe019464b, 
+    0xf203cca0, 0xf203d4a0, 0xf203dca0, 0xdcba01f5, 0x0004e520, 0xf203c4a0, 0x0017adce, 0xf203e80c, 
+    0xf203c670, 0xf203ce70, 0xf203d670, 0xf203de70, 0x00042353, 0x220f4dff, 0x46284621, 0xfb71f012, 
+    0x465b220c, 0x46284631, 0xfb6bf012, 0x46532209, 0x46284639, 0xfb65f012, 0x22079b03, 0x46284641, 
+    0xfb5ff012, 0x22059b0e, 0x46282160, 0xfb59f012, 0x22049b0f, 0x46282110, 0xfb53f012, 0x22039b10, 
+    0x46282108, 0xfb4df012, 0x22009b11, 0x46282107, 0xfb47f012, 0x220f4de8, 0x4621464b, 0xf0124628, 
+    0x220cfb40, 0x4631465b, 0xf0124628, 0x2209fb3a, 0x46394653, 0xf0124628, 0x9b03fb34, 0x46412207, 
+    0xf0124628, 0x9b0efb2e, 0x21602205, 0xf0124628, 0x9b0ffb28, 0x21102204, 0xf0124628, 0x9b10fb22, 
+    0x21082203, 0xf0124628, 0x9b11fb1c, 0x21072200, 0xf0124628, 0x4621fb16, 0x220f4cd0, 0x4620464b, 
+    0xfb0ff012, 0x465b220c, 0x46204631, 0xfb09f012, 0x46532209, 0x46204639, 0xfb03f012, 0x22079b03, 
+    0x46204641, 0xfafdf012, 0x22059b0e, 0x46202160, 0xfaf7f012, 0x22049b0f, 0x46202110, 0xfaf1f012, 
+    0x22039b10, 0x46202108, 0xfaebf012, 0xb0049b11, 0x22004620, 0x5ff0e8bd, 0xf0122107, 0xe92dbae2, 
+    0x4db75fff, 0x0400f248, 0x468b4692, 0x4681220f, 0x46214603, 0xf0124628, 0xf247fad4, 0x465b0600, 
+    0x4631220c, 0xf0124628, 0x10f7facc, 0x22094653, 0x46284639, 0xfac5f012, 0x1880f240, 0x22079b03, 
+    0x46284641, 0xfabdf012, 0x22059b0e, 0x46282160, 0xfab7f012, 0x22049b0f, 0x46282110, 0xfab1f012, 
+    0x22039b10, 0x46282108, 0xfaabf012, 0x22009b11, 0x46282107, 0xfaa5f012, 0x220f4d96, 0x4621464b, 
+    0x46281ead, 0xfa9df012, 0x465b220c, 0x46284631, 0xfa97f012, 0x46532209, 0x46284639, 0xfa91f012, 
+    0x22079b03, 0x46284641, 0xfa8bf012, 0x22059b0e, 0x46282160, 0xfa85f012, 0x22049b0f, 0x46282110, 
+    0xfa7ff012, 0x22039b10, 0x46282108, 0xfa79f012, 0x22009b11, 0x46282107, 0xfa73f012, 0x220f4d7e, 
+    0x4621464b, 0x46281ead, 0xfa6bf012, 0x465b220c, 0x46284631, 0xfa65f012, 0x46532209, 0x46284639, 
+    0xfa5ff012, 0x22079b03, 0x46284641, 0xfa59f012, 0x22059b0e, 0x46282160, 0xfa53f012, 0x22049b0f, 
+    0x46282110, 0xfa4df012, 0x22039b10, 0x46282108, 0xfa47f012, 0x22009b11, 0x46282107, 0xfa41f012, 
+    0x4c664621, 0x464b220f, 0x46201ea4, 0xfa39f012, 0x465b220c, 0x46204631, 0xfa33f012, 0x46532209, 
+    0x46204639, 0xfa2df012, 0x22079b03, 0x46204641, 0xfa27f012, 0x22059b0e, 0x46202160, 0xfa21f012, 
+    0x22049b0f, 0x46202110, 0xfa1bf012, 0x22039b10, 0x46202108, 0xfa15f012, 0xb0049b11, 0x22004620, 
+    0x5ff0e8bd, 0xf0122107, 0xe92dba0c, 0x4d4c5fff, 0x0400f248, 0x468b4692, 0x46811ead, 0x4603220f, 
+    0x46284621, 0xf9fdf012, 0x0600f247, 0x220c465b, 0x46284631, 0xf9f5f012, 0x465310f7, 0x46392209, 
+    0xf0124628, 0xf240f9ee, 0x9b031880, 0x46412207, 0xf0124628, 0x9b0ef9e6, 0x21602205, 0xf0124628, 
+    0x9b0ff9e0, 0x21102204, 0xf0124628, 0x9b10f9da, 0x21082203, 0xf0124628, 0x9b11f9d4, 0x21072200, 
+    0xf0124628, 0x4d2bf9ce, 0x464b220f, 0x1f2d4621, 0xf0124628, 0x220cf9c6, 0x4631465b, 0xf0124628, 
+    0x2209f9c0, 0x46394653, 0xf0124628, 0x9b03f9ba, 0x46412207, 0xf0124628, 0x9b0ef9b4, 0x21602205, 
+    0xf0124628, 0x9b0ff9ae, 0x21102204, 0xf0124628, 0x9b10f9a8, 0x21082203, 0xf0124628, 0x9b11f9a2, 
+    0x21072200, 0xf0124628, 0x4d13f99c, 0x464b220f, 0x1f2d4621, 0xf0124628, 0x220cf994, 0x4631465b, 
+    0xf0124628, 0x2209f98e, 0x46394653, 0xf0124628, 0x9b03f988, 0x46412207, 0xf0124628, 0x9b0ef982, 
+    0x21602205, 0xf0124628, 0x2204f97c, 0x21109b0f, 0xe0074628, 0xf203cc96, 0xf203d496, 0xf203dc96, 
+    0xf203c494, 0xf96df012, 0x22039b10, 0x46282108, 0xf967f012, 0x22009b11, 0x46282107, 0xf961f012, 
+    0x4cff4621, 0x464b220f, 0xf0124620, 0x220cf95a, 0x4631465b, 0xf0124620, 0x2209f954, 0x46394653, 
+    0xf0124620, 0x9b03f94e, 0x46412207, 0xf0124620, 0x9b0ef948, 0x21602205, 0xf0124620, 0x9b0ff942, 
+    0x21102204, 0xf0124620, 0x9b10f93c, 0x21082203, 0xf0124620, 0x9b11f936, 0x4620b004, 0xe8bd2200, 
+    0x21075ff0, 0xb92df012, 0x5fffe92d, 0xf2484de5, 0x46920400, 0x220f468b, 0x46034681, 0x46284621, 
+    0xf91ff012, 0x0600f247, 0x220c465b, 0x46284631, 0xf917f012, 0x465310f7, 0x46392209, 0xf0124628, 
+    0xf240f910, 0x9b031800, 0x46412208, 0xf0124628, 0x9b0ef908, 0x21802207, 0xf0124628, 0x9b03f902, 
+    0x21402206, 0xf0124628, 0x9b0ef8fc, 0x21202205, 0xf0124628, 0x9b03f8f6, 0x21102204, 0xf0124628, 
+    0x9b0ef8f0, 0x21082203, 0xf0124628, 0x9b0ff8ea, 0x21042202, 0xf0124628, 0x9b0ff8e4, 0x21022201, 
+    0xf0124628, 0x9b0ff8de, 0x21012200, 0xf0124628, 0x4dbdf8d8, 0x464b220f, 0x46284621, 0xf8d1f012, 
+    0x465b220c, 0x46284631, 0xf8cbf012, 0x46532209, 0x46284639, 0xf8c5f012, 0x22089b03, 0x46284641, 
+    0xf8bff012, 0x22079b0e, 0x46282180, 0xf8b9f012, 0x22069b03, 0x46282140, 0xf8b3f012, 0x22059b0e, 
+    0x46282120, 0xf8adf012, 0x22049b03, 0x46282110, 0xf8a7f012, 0x22039b0e, 0x46282108, 0xf8a1f012, 
+    0x22029b0f, 0x46282104, 0xf89bf012, 0x22019b0f, 0x46282102, 0xf895f012, 0x22009b0f, 0x46282101, 
+    0xf88ff012, 0x220f4d99, 0x4621464b, 0xf0124628, 0x220cf888, 0x4631465b, 0xf0124628, 0x2209f882, 
+    0x46394653, 0xf0124628, 0x9b03f87c, 0x46412208, 0xf0124628, 0x9b0ef876, 0x21802207, 0xf0124628, 
+    0x9b03f870, 0x21402206, 0xf0124628, 0x9b0ef86a, 0x21202205, 0xf0124628, 0x9b03f864, 0x21102204, 
+    0xf0124628, 0x9b0ef85e, 0x21082203, 0xf0124628, 0x9b0ff858, 0x21042202, 0xf0124628, 0x9b0ff852, 
+    0x21022201, 0xf0124628, 0x9b0ff84c, 0x21012200, 0xf0124628, 0x4621f846, 0x220f4c71, 0x1ea4464b, 
+    0xf0124620, 0x220cf83e, 0x4631465b, 0xf0124620, 0x2209f838, 0x46394653, 0xf0124620, 0x9b03f832, 
+    0x46412208, 0xf0124620, 0x9b0ef82c, 0x21802207, 0xf0124620, 0x9b03f826, 0x21402206, 0xf0124620, 
+    0x9b0ef820, 0x21202205, 0xf0124620, 0x9b03f81a, 0x21102204, 0xf0124620, 0x9b0ef814, 0x21082203, 
+    0xf0124620, 0x9b0ff80e, 0x21042202, 0xf0124620, 0x9b0ff808, 0x21022201, 0xf0124620, 0x9b0ff802, 
+    0x4620b004, 0xe8bd2200, 0x21015ff0, 0xbff9f011, 0x4604b510, 0x484e4601, 0xffd9f011, 0x4621484d, 
+    0xffd5f011, 0x4621484c, 0xffd1f011, 0x484b4621, 0x4010e8bd, 0xbfcbf011, 0xf240b57f, 0x460611f4, 
+    0x4620070c, 0xfe0ff7e6, 0x71abf241, 0xf7e64620, 0x4943fdf9, 0xf7e64620, 0x2001fdf5, 0xfc22f7fe, 
+    0xf7fe200a, 0xf640fa15, 0xf7ff0008, 0x2001ffd1, 0x46032400, 0xe9cd2202, 0x46114000, 0xf7ff4620, 
+    0x2506fe93, 0x21009400, 0x23029401, 0x22044608, 0x4502e9cd, 0xfda9f7ff, 0x94002100, 0x46082302, 
+    0x94012204, 0x4502e9cd, 0xfcc9f7ff, 0x94002100, 0x46082302, 0x94012204, 0x4502e9cd, 0xfbd0f7ff, 
+    0xf7fd4630, 0xb004fefa, 0xe8bd200b, 0xf7fe4070, 0xb510b9df, 0x46042200, 0x46032101, 0xf0114821, 
+    0x4820ff79, 0x21012200, 0x1d004623, 0xff72f011, 0x2200481c, 0x46232101, 0xf0113008, 0x4819ff6b, 
+    0x21012200, 0xe8bd4623, 0x300c4010, 0xbf62f011, 0x2201b510, 0x21024604, 0x48124603, 0xff5af011, 
+    0x22014810, 0x46232102, 0xf0111d00, 0x480dff53, 0x21022201, 0x30084623, 0xff4cf011, 0xe0134623, 
+    0xf203dc92, 0xf203c490, 0xf203cc90, 0xf203d490, 0xf203c660, 0xf203ce60, 0xf203d660, 0xf203de60, 
+    0xdcba01f5, 0xf1000854, 0x48fd2201, 0x4010e8bd, 0xf0112102, 0xb510bf2f, 0x46034604, 0x220448f8, 
+    0x380c2130, 0xff26f011, 0x220448f5, 0x46232130, 0xf0113808, 0x48f2ff1f, 0x21302204, 0x1f004623, 
+    0xff18f011, 0x46232204, 0x4010e8bd, 0x213048ec, 0xbf10f011, 0x2208b570, 0x46034605, 0x015448e8, 
+    0x4621380c, 0xff06f011, 0x220848e5, 0x4621462b, 0xf0113808, 0x48e2feff, 0x462b2208, 0x1f004621, 
+    0xfef8f011, 0x4621462b, 0x4070e8bd, 0x220848dc, 0xbef0f011, 0x4605b570, 0x48d94603, 0x1470f44f, 
+    0x46212212, 0xf011380c, 0x48d5fee5, 0x462b2212, 0x38084621, 0xfedef011, 0x221248d1, 0x4621462b, 
+    0xf0111f00, 0x462bfed7, 0xe8bd4621, 0x48cc4070, 0xf0112212, 0xb570becf, 0x46034605, 0xf04f48c8, 
+    0x221864e0, 0x380c4621, 0xfec4f011, 0x221848c4, 0x4621462b, 0xf0113808, 0x48c1febd, 0x462b2218, 
+    0x1f004621, 0xfeb6f011, 0x4621462b, 0x4070e8bd, 0x221848bb, 0xbeaef011, 0x4604b510, 0x48b84603, 
+    0x21012200, 0xf0113858, 0x48b5fea5, 0x21012200, 0x38544623, 0xfe9ef011, 0x220048b1, 0x46232101, 
+    0xf0113850, 0x48aefe97, 0x21012200, 0x38484623, 0xfe90f011, 0x220048aa, 0x46232101, 0xf0113844, 
+    0x48a7fe89, 0x21012200, 0x38404623, 0xfe82f011, 0x220048a3, 0x46232101, 0xf0113838, 0x48a0fe7b, 
+    0x21012200, 0x38344623, 0xfe74f011, 0x2200489c, 0x46232101, 0xf0113830, 0x4899fe6d, 0x21012200, 
+    0x38284623, 0xfe66f011, 0x22004895, 0x46232101, 0xf0113824, 0x4892fe5f, 0x21012200, 0xe8bd4623, 
+    0x38204010, 0xbe56f011, 0x4604b510, 0x488c4603, 0x21102204, 0xf0113858, 0x4889fe4d, 0x21102204, 
+    0x38544623, 0xfe46f011, 0x22044885, 0x46232110, 0xf0113850, 0x4882fe3f, 0x21102204, 0x38484623, 
+    0xfe38f011, 0x2204487e, 0x46232110, 0xf0113844, 0x487bfe31, 0x21102204, 0x38404623, 0xfe2af011, 
+    0x22044877, 0x46232110, 0xf0113838, 0x4874fe23, 0x21102204, 0x38344623, 0xfe1cf011, 0x22044870, 
+    0x46232110, 0xf0113830, 0x486dfe15, 0x21102204, 0x38284623, 0xfe0ef011, 0x22044869, 0x46232110, 
+    0xf0113824, 0x4866fe07, 0x21102204, 0xe8bd4623, 0x38204010, 0xbdfef011, 0x4605b570, 0x48604603, 
+    0x7400f240, 0x46212208, 0xf0113858, 0x485cfdf3, 0x462b2208, 0x38544621, 0xfdecf011, 0x22084858, 
+    0x4621462b, 0xf0113850, 0x4855fde5, 0x462b2208, 0x38484621, 0xfddef011, 0x22084851, 0x4621462b, 
+    0xf0113844, 0x484efdd7, 0x462b2208, 0x38404621, 0xfdd0f011, 0x2208484a, 0x4621462b, 0xf0113838, 
+    0x4847fdc9, 0x462b2208, 0x38344621, 0xfdc2f011, 0x22084843, 0x4621462b, 0xf0113830, 0x4840fdbb, 
+    0x462b2208, 0x38284621, 0xfdb4f011, 0x2208483c, 0x4621462b, 0xf0113824, 0x4839fdad, 0x4621462b, 
+    0x4070e8bd, 0x38202208, 0xbda4f011, 0x460eb570, 0x48344604, 0x2c012101, 0x7001d100, 0x4d322e01, 
+    0x7029d100, 0x78007829, 0x2101b24b, 0x4608b242, 0xfa3af7fd, 0x20042100, 0xfc7ef7ed, 0x7800482b, 
+    0xf7ffb240, 0x2001ff89, 0xff2ef7ff, 0xf7ffb2e0, 0x2003fed3, 0xfeaff7ff, 0xf7ff200b, 0x2000fe8b, 
+    0xfe68f7ff, 0xf7ff2001, 0x4630fe46, 0xfe10f7ff, 0xe8bd7828, 0xb2404070, 0xb570e5eb, 0x0400f647, 
+    0x220b4605, 0x481a4603, 0xf0114621, 0x4819fd7a, 0x462b220b, 0xf0114621, 0x4817fd74, 0x462b220b, 
+    0xf0114621, 0x462bfd6e, 0xe8bd4621, 0x48134070, 0xf011220b, 0xe92dbd66, 0x4f0d41f0, 0x4e102400, 
+    0x3f3cb2c5, 0xeb0642a5, 0xd11b20c4, 0x22042301, 0xf0112110, 0x2301fd56, 0x20c4eb07, 0x0000e01a, 
+    0xf1000860, 0x00040294, 0x00040295, 0x00042353, 0xf203c64c, 0xf203ce4c, 0xf203d64c, 0xf203de4c, 
+    0xf203c482, 0x22042300, 0xf0112110, 0x2300fd3a, 0x20c4eb07, 0x21022201, 0xfd33f011, 0xb2e41c64, 
+    0xd3cf2c04, 0x81f0e8bd, 0x46032208, 0x0154b570, 0x48ff4605, 0xf0114621, 0x48fefd24, 0x462b2208, 
+    0xf0114621, 0x48fcfd1e, 0x462b2208, 0xf0114621, 0x462bfd18, 0xe8bd4621, 0x48f84070, 0xf0112208, 
+    0xb510bd10, 0x46042207, 0x46032180, 0xf01148f0, 0x48f0fd08, 0x21802207, 0xf0114623, 0x48eefd02, 
+    0x21802207, 0xf0114623, 0x2207fcfc, 0xe8bd4623, 0x48ea4010, 0xf0112180, 0x220cbcf4, 0xb5704603, 
+    0x46050294, 0x462148e2, 0xfcebf011, 0x220c48e1, 0x4621462b, 0xfce5f011, 0x220c48df, 0x4621462b, 
+    0xfcdff011, 0x4621462b, 0x4070e8bd, 0x220c48db, 0xbcd7f011, 0x4605b570, 0x48d54603, 0x2400f240, 
+    0x46212209, 0xf0111c80, 0x48d2fccc, 0x462b2209, 0x1c804621, 0xfcc5f011, 0x220948cf, 0x4621462b, 
+    0xf0111c80, 0x48cdfcbe, 0x4621462b, 0x4070e8bd, 0x1c802209, 0xbcb5f011, 0x4604b510, 0x48c44603, 
+    0x21072200, 0xf0113008, 0x48c2fcac, 0x21072200, 0x30084623, 0xfca5f011, 0x220048bf, 0x46232107, 
+    0xf0113008, 0x48bdfc9e, 0x21072200, 0xe8bd4623, 0x30084010, 0xbc95f011, 0x4605b570, 0x48b44603, 
+    0x0400f246, 0x4621220d, 0xf011387a, 0x48b1fc8a, 0x462b220d, 0x387a4621, 0xfc83f011, 0x220d48ae, 
+    0x4621462b, 0xf011387a, 0x48acfc7c, 0x4621462b, 0x4070e8bd, 0x387a220d, 0xbc73f011, 0x4604b510, 
+    0x48a34603, 0x21012200, 0xf011387c, 0x48a1fc6a, 0x21012200, 0x387c4623, 0xfc63f011, 0x2200489e, 
+    0x46232101, 0xf011387c, 0x489cfc5c, 0x21012200, 0xe8bd4623, 0x387c4010, 0xbc53f011, 0x4605b570, 
+    0x48934603, 0x0400f241, 0x4621220c, 0xf011387a, 0x4890fc48, 0x462b220c, 0x387a4621, 0xfc41f011, 
+    0x220c488d, 0x4621462b, 0xf011387a, 0x488bfc3a, 0x4621462b, 0x4070e8bd, 0x387a220c, 0xbc31f011, 
+    0x4604b510, 0x48824603, 0x21022201, 0xf0113876, 0x4880fc28, 0x21022201, 0x38764623, 0xfc21f011, 
+    0x2201487d, 0x46232102, 0xf0113876, 0x487bfc1a, 0x21022201, 0xe8bd4623, 0x38764010, 0xbc11f011, 
+    0x4605b570, 0x48724603, 0x0400f248, 0x4621220f, 0xf011387a, 0x486ffc06, 0x462b220f, 0x387a4621, 
+    0xfbfff011, 0x220f486c, 0x4621462b, 0xf011387a, 0x486afbf8, 0x4621462b, 0x4070e8bd, 0x387a220f, 
+    0xbbeff011, 0x4604b510, 0x48614603, 0x21012200, 0xf0113876, 0x485ffbe6, 0x21012200, 0x38764623, 
+    0xfbdff011, 0x2200485c, 0x46232101, 0xf0113876, 0x485afbd8, 0x21012200, 0xe8bd4623, 0x38764010, 
+    0xbbcff011, 0x4ff7e92d, 0xf7ff2000, 0x2001ffdb, 0xffb6f7ff, 0x78204c52, 0x2001b948, 0xff90f7ff, 
+    0x20402100, 0xfa98f7ed, 0xf7ff2000, 0x2001ff89, 0xff64f7ff, 0x20402100, 0xfa8ef7ed, 0xf7ff2000, 
+    0x2001ff5d, 0xff3af7ff, 0xf7ff2003, 0x7820ff15, 0x3900f44f, 0xd1792800, 0x70202001, 0xfecaf7ff, 
+    0xf7ff2007, 0xf8dffee9, 0xf241a0e8, 0xf8df0600, 0x2400b0e0, 0x0a76f1aa, 0xf1aa1077, 0xf10b0804, 
+    0x46550b84, 0x46502301, 0x21042202, 0xfb89f011, 0x46482100, 0xfa60f7ed, 0x46282300, 0x21042202, 
+    0xfb7ff011, 0x46312301, 0x4640220c, 0xfb79f011, 0x46392301, 0x4640220b, 0xfb73f011, 0x46582200, 
+    0xf011217f, 0xb245fb7c, 0x23004639, 0x220b4640, 0xfb67f011, 0x46312300, 0x4640220c, 0xfb61f011, 
+    0x2d7e1e6d, 0x1c64d303, 0x2c0ab264, 0xf8dfdbc9, 0x2400a064, 0xb05cf8df, 0x0a76f1aa, 0x0804f1aa, 
+    0x0b84f10b, 0x23014655, 0x22024650, 0xf0112104, 0x2100fb48, 0xf7ed4648, 0x2300fa1f, 0x22024628, 
+    0xf0112104, 0x2301fb3e, 0x220c4631, 0xf0114640, 0x2301fb38, 0x220b4639, 0xf0114640, 0x2200fb32, 
+    0x217f4658, 0xfb3bf011, 0xe00bb245, 0x0000e09e, 0xf203c280, 0xf203ca80, 0xf203d280, 0xf203da80, 
+    0x000429c8, 0x46392300, 0x4640220b, 0xfb19f011, 0x46312300, 0x4640220c, 0xfb13f011, 0x2d7e1e6d, 
+    0x1c64d303, 0x2c0ab264, 0xf8dfdbbc, 0x2400a514, 0xb50cf8df, 0x0804f1aa, 0x0bfaf10b, 0x23014655, 
+    0x22024650, 0xf0112104, 0x2100fafc, 0xf7ed4648, 0x2300f9d3, 0x22024628, 0xf0112104, 0x2301faf2, 
+    0x220c4631, 0xf0114640, 0x2301faec, 0x220b4639, 0xf0114640, 0x2200fae6, 0x217f4658, 0xfaeff011, 
+    0x4639b245, 0x46402300, 0xf011220b, 0x2300fada, 0x220c4631, 0xf0114640, 0x1e6dfad4, 0xd3032d7e, 
+    0xb2641c64, 0xdbc92c0a, 0xa498f8df, 0xf8df2400, 0xf1aab494, 0xf10b0804, 0x46550bfa, 0x46502301, 
+    0x21042202, 0xfabdf011, 0x46482100, 0xf994f7ed, 0x46282300, 0x21042202, 0xfab3f011, 0x46312301, 
+    0x4640220c, 0xfaadf011, 0x46392301, 0x4640220b, 0xfaa7f011, 0x46582200, 0xf011217f, 0xb245fab0, 
+    0x23004639, 0x220b4640, 0xfa9bf011, 0x46312300, 0x4640220c, 0xfa95f011, 0x2d7e1e6d, 0x1c64d303, 
+    0x2c0ab264, 0x2000dbc9, 0xfdb4f7ff, 0xf7ff9802, 0x9800fd94, 0xfd75f7ff, 0xf7ff9801, 0x2100fd55, 
+    0x4648464c, 0xf958f7ed, 0x23014dff, 0x461a2102, 0xf0114628, 0x2100fa76, 0xf7ed2040, 0x4efaf94d, 
+    0x22063676, 0x21404630, 0xfa79f011, 0x2900b241, 0x2300d1f7, 0x22014628, 0xf0112102, 0x2100fa62, 
+    0xf7ed4620, 0x4df1f939, 0x21022301, 0x4628461a, 0xfa57f011, 0x20402100, 0xf92ef7ed, 0x36764eeb, 
+    0x46302206, 0xf0112140, 0xb241fa5a, 0xd1f72900, 0x46282300, 0x21022201, 0xfa43f011, 0x46202100, 
+    0xf91af7ed, 0x23014dde, 0x461a2102, 0x46283580, 0xfa37f011, 0x20402100, 0xf90ef7ed, 0x36f64ed8, 
+    0x46302206, 0xf0112140, 0xb241fa3a, 0xd1f72900, 0x46282300, 0x21022201, 0xfa23f011, 0x46202100, 
+    0xf8faf7ed, 0x23014ccf, 0x461a2102, 0x46203480, 0xfa17f011, 0x20402100, 0xf8eef7ed, 0x35f64dc9, 
+    0x46282206, 0xf0112140, 0xb241fa1a, 0xd1f72900, 0x46202300, 0x21022201, 0xfa03f011, 0xf7ff2000, 
+    0xe8bdfcf0, 0x20004ffe, 0xe92de4ce, 0x46804ff0, 0x460f48bf, 0xa2fcf8df, 0xad10b099, 0xe885c81e, 
+    0xc81e001e, 0xe88dad04, 0xc81e001e, 0x001ee885, 0xad14c81e, 0x001ee885, 0xad0cc81e, 0x001ee885, 
+    0xac08c80f, 0xe8842500, 0x2400000f, 0x29c5ea4f, 0x0144eb09, 0x060aeb01, 0xf0114630, 0x0b03f9b5, 
+    0x021ff000, 0x1145f3c0, 0xf1b84618, 0xd10d0f01, 0xc040f9bd, 0xdd02458c, 0xb2801f18, 0xf9bde004, 
+    0x458cc000, 0x1d18da02, 0x1010f8bd, 0xd10d2f01, 0xc050f9bd, 0xdd014594, 0xe0041e40, 0xc030f9bd, 
+    0xda034594, 0xf8bd1c40, 0xb2802020, 0xd0074298, 0xeb000300, 0x44101041, 0x4630b281, 0xf987f011, 
+    0x2c421c64, 0x1c6ddbc4, 0x2d04b26d, 0x2500dbbd, 0x0a10f10d, 0x0b20f10d, 0xea4f2402, 0x488d29c5, 
+    0x0144eb09, 0x180e30a0, 0xf0114630, 0x0b03f96d, 0x021ff000, 0x1145f3c0, 0xf1b84618, 0xd1150f01, 
+    0x0c40f10d, 0x0c44eb0c, 0xc002f9bc, 0xdd02458c, 0xb2801f18, 0x46ece007, 0x0c44eb0c, 0xc002f9bc, 
+    0xda03458c, 0xeb0a1d18, 0x88490144, 0xd1162f01, 0x0c50f10d, 0x0c44eb0c, 0xc002f9bc, 0xdd014594, 
+    0xe0081e40, 0x0c30f10d, 0x0c44eb0c, 0xc002f9bc, 0xda044594, 0xeb0b1c40, 0xb2800244, 0x42988852, 
+    0x0300d007, 0x1041eb00, 0xb2814410, 0xf0114630, 0x1c64f92e, 0xdbb22c06, 0xb26d1c6d, 0xdbab2d04, 
+    0xe8bdb019, 0xe92d8ff0, 0x4c5f41f0, 0x22022300, 0x46202104, 0xf935f011, 0x23004d5c, 0x21042202, 
+    0xf0114628, 0x4e56f92e, 0x22022300, 0x21043680, 0xf0114630, 0x4f53f926, 0x22022300, 0x21043780, 
+    0xf0114638, 0x2100f91e, 0xf7ec2040, 0x2301fff5, 0x22024620, 0xf0112104, 0x2301f914, 0x22024628, 
+    0xf0112104, 0x2301f90e, 0x22024630, 0xf0112104, 0x2301f908, 0x22024638, 0xf0112104, 0x4845f902, 
+    0x4410f24a, 0x30aa4621, 0xf8e1f011, 0x46214842, 0xf8ddf011, 0x46214841, 0xf8d9f011, 0x46214840, 
+    0xf8d5f011, 0xf24a483b, 0x4621240c, 0xf01130a8, 0x4839f8ce, 0x1e804621, 0xf8c9f011, 0x46214837, 
+    0xf0111e80, 0x4836f8c4, 0x1e804621, 0xf8bff011, 0x1f244830, 0x30a64621, 0xf8b9f011, 0x4621482e, 
+    0xf0111f00, 0x482df8b4, 0x1f004621, 0xf8aff011, 0x4621482b, 0xf0111f00, 0x4826f8aa, 0x1406f24a, 
+    0x30a44621, 0xf8a3f011, 0x46214823, 0xf0111f80, 0x4822f89e, 0x1f804621, 0xf899f011, 0x46214820, 
+    0xf0111f80, 0x481bf894, 0x1404f246, 0x30a24621, 0xf88df011, 0x46214818, 0xf0113808, 0x4817f888, 
+    0x38084621, 0xf883f011, 0x46214815, 0xf0113808, 0x4810f87e, 0x1404f242, 0x30a04621, 0xf877f011, 
+    0x4621480d, 0xf011380a, 0x480cf872, 0x380a4621, 0xf86df011, 0x4621480a, 0xf011380a, 0xe011f868, 
+    0xf203d20a, 0xf203da0a, 0xf203c28a, 0xf203ca8a, 0x0002ea94, 0xf203c000, 0xf203c8aa, 0xf203d0aa, 
+    0xf203d8aa, 0x3480f240, 0x46214897, 0xf84ff011, 0x46214896, 0xf84bf011, 0x46214895, 0xf847f011, 
+    0x48944621, 0x41f0e8bd, 0xb841f011, 0x47f0e92d, 0x4c914691, 0x468a220c, 0x46034607, 0x46200296, 
+    0xf0114631, 0x4d8df84e, 0x463b220c, 0x46284631, 0xf847f011, 0x8228f8df, 0x463b220c, 0x46404631, 
+    0xf83ff011, 0x4e874631, 0x463b220c, 0xf0114630, 0xf240f838, 0x46533700, 0x46392208, 0xf0114620, 
+    0x2208f830, 0x46394653, 0xf0114628, 0x2208f82a, 0x46394653, 0xf0114640, 0x2208f824, 0x46394653, 
+    0xf0114630, 0x2206f81e, 0x21c0464b, 0xf0114620, 0x2206f818, 0x21c0464b, 0xf0114628, 0x2206f812, 
+    0x21c0464b, 0xf0114640, 0x464bf80c, 0xe8bd4630, 0x220647f0, 0xf01121c0, 0xb51cb804, 0xf7ff2000, 
+    0x2202fc11, 0x20012103, 0xffa0f7ff, 0xf7f12000, 0x2001f817, 0xf814f7f1, 0xf7f12000, 0x2202f811, 
+    0x20002101, 0xfc1ef7ff, 0x74e0f240, 0x2205485e, 0xf0104621, 0xf8adfff4, 0x22050000, 0x4621485b, 
+    0xffedf010, 0x0002f8ad, 0x48592205, 0xf0104621, 0xf8adffe6, 0x22050004, 0x46214856, 0xffdff010, 
+    0x0006f8ad, 0x211c2000, 0xf933466b, 0xeba22010, 0x32600282, 0x02a2eb01, 0x2010f823, 0xb2001c40, 
+    0xdbf22804, 0xfe7ff7ff, 0x3000f8bd, 0x483e2205, 0xf0104621, 0xf8bdffb6, 0x22053002, 0x4621483b, 
+    0xffaff010, 0x3004f8bd, 0x48392205, 0xf0104621, 0xf8bdffa8, 0x22053006, 0x46214836, 0xffa1f010, 
+    0x21012203, 0xf7ff2000, 0x2100fbcd, 0xf7ff2001, 0xf44ffd9c, 0x21003400, 0xf7ec4620, 0x2203fe6d, 
+    0x20002101, 0xfbbef7ff, 0x21002203, 0xf7ff2001, 0x2101fbb9, 0xf7ff2000, 0x2100fd88, 0xf7ec4620, 
+    0xb002fe5b, 0x21002203, 0x4010e8bd, 0xf7ff2001, 0xb5f8bba9, 0x14f4f240, 0x07254621, 0xf7e54628, 
+    0xf241fda2, 0x462871bb, 0xfd8cf7e5, 0x46284e22, 0xf7e54631, 0x2000fd87, 0xfd6ff7f0, 0xf7f02030, 
+    0x2001fd4e, 0xff3af7f0, 0x92002200, 0x46132100, 0x46082203, 0xf8d0f002, 0xfe15f7ff, 0xf7ff2003, 
+    0x2000ff4c, 0xff2af7f0, 0x46284621, 0xfd7bf7e5, 0x71bcf241, 0xf7e54628, 0x4631fd65, 0xe8bd4628, 
+    0xf7e540f8, 0x0000bd5f, 0xf203c0fe, 0xf203c8fe, 0xf203d0fe, 0xf203d8fe, 0xf203c200, 0xf203ca00, 
+    0xf203d200, 0xf203da00, 0xf203c302, 0xf203cb02, 0xf203d302, 0xf203db02, 0xdcba01f5, 0x4c3cb570, 
+    0x211f2300, 0x4620461a, 0xff1bf010, 0xf2404838, 0x220535e0, 0x301a4629, 0xff21f010, 0x46032205, 
+    0x46204629, 0xff0df010, 0x46202301, 0x0299220a, 0xff07f010, 0x23024c2e, 0xf24f220c, 0x34200100, 
+    0xf0104620, 0x2304fefe, 0x22004620, 0xf010210f, 0x2301fef8, 0x210f2200, 0xf0101f20, 0x2301fef2, 
+    0x210f2200, 0xe8bd1ea0, 0xf0104070, 0x4821beea, 0xf010b510, 0x4920fec9, 0x80084a20, 0x1140f3c0, 
+    0xf3c07011, 0x4a1e1180, 0x4a1e7011, 0xf3c07011, 0x4a1d11c0, 0x1000f3c0, 0x22087011, 0x7008491b, 
+    0x48140151, 0xf0101d00, 0x4919feda, 0x20007008, 0x70084918, 0x2100bd10, 0x6e084a17, 0xd1014290, 
+    0x66092000, 0x480bb281, 0xbea1f010, 0xf64b4809, 0xb51031b3, 0xf0103086, 0xf7fffe9a, 0xf7ffffec, 
+    0x490effc6, 0x70082000, 0x4010e8bd, 0x0000e786, 0xf23c8204, 0xf23c8034, 0x000425a4, 0x00042324, 
+    0x00042309, 0x00042308, 0x000425a1, 0x000425a2, 0x000425a3, 0x00042380, 0xf1205a2d, 0x000425d4, 
+    0x4db7b570, 0x2200b283, 0x21014604, 0xf0104628, 0xb2a3fe88, 0x22014628, 0xf0102102, 0xb2a3fe82, 
+    0x22024628, 0xf0102104, 0x2301fe7c, 0x22034628, 0xf0102108, 0xb2a3fe76, 0xe8bd4628, 0x22044070, 
+    0xf0102110, 0xe92dbe6e, 0x48a641f0, 0xf0102100, 0x48a4fe4e, 0x1c802100, 0xfe49f010, 0x210048a1, 
+    0xf0101d00, 0x489ffe44, 0x1d802100, 0xfe3ff010, 0x2100489c, 0xf0103008, 0x489afe3a, 0x300a2100, 
+    0xfe35f010, 0x21004897, 0xf010300c, 0x4895fe30, 0x300e2100, 0xfe2bf010, 0x21004892, 0xf0103010, 
+    0x4890fe26, 0x30122140, 0xfe21f010, 0x2100488d, 0xf0103014, 0x488bfe1c, 0x30162104, 0xfe17f010, 
+    0x21004888, 0xf0103018, 0x4886fe12, 0x301a2100, 0xfe0df010, 0x21004883, 0xf010301c, 0x4882fe08, 
+    0xf0102100, 0x4881fe04, 0x1cad4d7d, 0x487d7801, 0x1c843020, 0x29001e86, 0x0100f04f, 0x4607d019, 
+    0xfdf5f010, 0x46382301, 0x21202205, 0xfe09f010, 0x46202100, 0xfdebf010, 0x46282100, 0xfde7f010, 
+    0x4100f240, 0xf0104630, 0xe8bdfde2, 0x200141f0, 0xf010e766, 0x2100fddc, 0xf0104620, 0x2100fdd8, 
+    0xf0104628, 0xf242fdd4, 0xe7eb4192, 0x460cb510, 0x78094966, 0xd1152900, 0x4862b283, 0x21032200, 
+    0xf010301e, 0x485ffdde, 0x2200b2a3, 0x1d00210f, 0xfdd7f010, 0x485a2301, 0xe8bd2205, 0x21204010, 
+    0xbdcff010, 0x4859bd10, 0x28007800, 0x4855d106, 0x21032300, 0x301e461a, 0xbdc3f010, 0xb5104770, 
+    0x4952460c, 0x29007809, 0xb283d115, 0x2203484d, 0x301e2118, 0xfdb5f010, 0xb2a3484a, 0x210f2200, 
+    0xf010300a, 0x2301fdae, 0x22064845, 0x4010e8bd, 0xf0102140, 0xbd10bda6, 0x78004844, 0xd1062800, 
+    0x23004840, 0x21182203, 0xf010301e, 0x4770bd9a, 0x460cb510, 0x7809493d, 0xd1152900, 0x4839b283, 
+    0x21c02206, 0xf010301e, 0x4836fd8c, 0x2200b2a3, 0x3010210f, 0xfd85f010, 0x48312301, 0xe8bd2207, 
+    0x21804010, 0xbd7df010, 0x4830bd10, 0x28007800, 0x482cd106, 0x22062300, 0x301e21c0, 0xbd71f010, 
+    0x48284770, 0x22062301, 0x30202140, 0xbd69f010, 0x23004824, 0x21402206, 0xf0103020, 0xb510bd62, 
+    0x4922460c, 0x29007809, 0xb283d115, 0x220c481d, 0x0291301e, 0xfd55f010, 0xb2a3481a, 0x210f2200, 
+    0xf010301c, 0x2301fd4e, 0x22094815, 0x4010e8bd, 0xf0100259, 0xbd10bd46, 0x78004814, 0xd1062800, 
+    0x4810220c, 0x02912300, 0xf010301e, 0x4770bd3a, 0xf000b510, 0x2100f81d, 0xf7ff2001, 0x2100ff47, 
+    0xf7ff2001, 0x2100ff6c, 0xf7ff2001, 0x2100ff91, 0xf7ff2001, 0x2100ffb6, 0x4010e8bd, 0xe7be2001, 
+    0xf20351d8, 0xf2035058, 0xf23d0122, 0x000425a2, 0xf7ffb510, 0x2301fea8, 0x220048ff, 0xf0104619, 
+    0x48fefd10, 0x22042301, 0xf0102110, 0x4cfafd0a, 0x22022301, 0x21041ca4, 0xf0104620, 0x2301fd02, 
+    0x22034620, 0xf0102108, 0x4cf4fcfc, 0x22022301, 0x21041da4, 0xf0104620, 0x2301fcf4, 0x21024620, 
+    0xf010461a, 0x2301fcee, 0x21402206, 0xf0101da0, 0x48eafce8, 0x22072301, 0x30122180, 0xfce1f010, 
+    0x23014ce5, 0x34082202, 0x46202104, 0xfcd9f010, 0x46202301, 0x21082203, 0xfcd3f010, 0x48df2301, 
+    0x03d9220f, 0x4010e8bd, 0xf0103018, 0x48dabcca, 0x22002301, 0x1f004619, 0xf010b510, 0x2100fcc2, 
+    0x4010e8bd, 0xf7ff2002, 0x48d3bed1, 0x21012300, 0x1f00461a, 0xf010b510, 0xe8bdfcb4, 0xf7ff4010, 
+    0xe92dbee2, 0x4dce5ff0, 0x080ff001, 0x46142300, 0xf04f2202, 0x21040901, 0xf0104628, 0x2301fca2, 
+    0x22064628, 0xf0102140, 0x2301fc9c, 0x22074628, 0xf0102180, 0x2300fc96, 0x22044628, 0xf0102110, 
+    0x2300fc90, 0x22054628, 0xf0102120, 0x2300fc8a, 0x22014628, 0xf0102102, 0x2300fc84, 0x22034628, 
+    0xf0102108, 0x4fb7fc7e, 0x080af1a8, 0xf8df4eb5, 0x3f18b2d4, 0xa2d0f8df, 0xf1b83e08, 0xd2760f05, 
+    0xf008e8df, 0xf6f7f903, 0xf8df00f5, 0x1c6082c0, 0x2300d011, 0x22064628, 0xf0102140, 0xb3ecfc62, 
+    0x28091e60, 0x48a7d854, 0x0148ea4f, 0xf0103810, 0x2130fc38, 0x48a3e056, 0x46414644, 0xf0103810, 
+    0x4621fc30, 0xf0104658, 0x2300fc2c, 0x22064628, 0xf0102140, 0x2300fc46, 0x22074628, 0xf0102180, 
+    0x2301fc40, 0x21024628, 0xf010461a, 0x4894fc3a, 0x1c802118, 0xfc1bf010, 0x21184891, 0xf0103008, 
+    0x2300fc16, 0x21022201, 0xf0104628, 0x2301fc2a, 0x461a2102, 0xf0104628, 0xe1b0fc24, 0x2301e7ff, 
+    0x21024638, 0xf010461a, 0x2301fc05, 0x21024630, 0xf010461a, 0x2300fbff, 0x22014638, 0xf0102102, 
+    0x2300fbf9, 0x22014630, 0xf0102102, 0xe185fbf3, 0x000bf1a4, 0xd80b2859, 0x497d487a, 0xf0103810, 
+    0x212cfbe0, 0x1c804876, 0xfbe1f010, 0xe183e187, 0x0065f1a4, 0x7fc8f5b0, 0x4872d206, 0x38104975, 
+    0xfbcff010, 0xe7ed2128, 0x10f5f2a4, 0x7ffaf5b0, 0x486cd206, 0x38104970, 0xfbc3f010, 0xe7e12124, 
+    0x30e9f2a4, 0x6f7af5b0, 0x4866d206, 0x3810496b, 0xfbb7f010, 0xe7d52120, 0x5098f5a4, 0x3187f241, 
+    0x42883889, 0x485fd806, 0x38104965, 0xfba9f010, 0xe7c7211c, 0x501cf5a4, 0x413ff649, 0x42883811, 
+    0x4858d806, 0x38104641, 0xfb9bf010, 0xe7b92118, 0x4043f5a4, 0x314ff24c, 0x42883851, 0x4851d806, 
+    0x38104958, 0xfb8df010, 0xe7ab2114, 0xf5a44956, 0x38a130c3, 0xd8064288, 0x4954484a, 0xf0103810, 
+    0x2110fb80, 0x4852e79e, 0x44204952, 0xd8064288, 0x49514844, 0xf0103810, 0x210cfb74, 0x484fe792, 
+    0x4420494f, 0xd8064288, 0x4651483e, 0xf0103810, 0x2108fb68, 0x484be786, 0x4420494b, 0xd8854288, 
+    0x494a4838, 0xf0103810, 0x2104fb5c, 0xe050e77a, 0xe01ee041, 0x4833e7ff, 0x46514654, 0xf0103810, 
+    0x4621fb50, 0xf0104658, 0x482dfb4c, 0x1c802108, 0xfb4df010, 0x2108482a, 0xf0103008, 0x2300fb48, 
+    0x22064628, 0xf0102140, 0x2300fb5c, 0x21802207, 0x2301e72a, 0x21024638, 0xf010461a, 0x2301fb3b, 
+    0x21024630, 0xf010461a, 0x2300fb35, 0x22014638, 0xf0102102, 0x2300fb2f, 0x22014630, 0xf0102102, 
+    0x2300fb29, 0x22074628, 0xf0102180, 0x2301fb3a, 0x21202205, 0x2300e0b5, 0x22074628, 0xf0102180, 
+    0x4923fb30, 0xf0104658, 0x480dfb0c, 0x30082102, 0x4820e72a, 0x0000f990, 0xd03d2803, 0xd03b2805, 
+    0xd0392804, 0xd0702802, 0xf04f2801, 0xd0780301, 0x21402206, 0x0000e6ee, 0xf20351de, 0xf203505e, 
+    0xf23c80da, 0xf0008178, 0x0501bd00, 0x0f053700, 0x1b898f80, 0x1908b100, 0x1687d280, 0x1406f400, 
+    0x11861580, 0x0c845880, 0x00061a7f, 0x0a037a00, 0xfff85edf, 0x0007a11f, 0x07829b80, 0xfff0bdbf, 
+    0x003d08ff, 0xffb3b4bf, 0x004c4b3f, 0x0280de80, 0x01406f40, 0x0004024c, 0x46382301, 0x461a2102, 
+    0xfac8f010, 0x46302301, 0x461a2102, 0xfac2f010, 0x48f849f7, 0xfab5f010, 0x46282300, 0x21402206, 
+    0xfacff010, 0x210548f4, 0xfab1f010, 0x210a48f2, 0xf0101c80, 0x48f0faac, 0x1d002105, 0xfaa7f010, 
+    0x46282301, 0x21042202, 0xfabbf010, 0x46382300, 0x21022201, 0xfa9ef010, 0x46302300, 0x21022201, 
+    0xfa98f010, 0xe000e03b, 0x49e1e00b, 0xf01048e1, 0x2300fa88, 0x22064628, 0xf0102140, 0x2105faa2, 
+    0x2201e6a0, 0x21024638, 0xfa84f010, 0x46302301, 0x461a2102, 0xfa7ef010, 0x46382300, 0x21022201, 
+    0xfa78f010, 0x46302300, 0x21022201, 0xfa72f010, 0x46282300, 0x21402206, 0xfa83f010, 0x22042301, 
+    0x46282110, 0xfa7df010, 0xe8bd4628, 0x23015ff0, 0x21082203, 0xba75f010, 0x0f00f1b9, 0x2300d00d, 
+    0x22034630, 0xf0102108, 0x4630fa55, 0x5ff0e8bd, 0x22032301, 0xf0102108, 0xe8bdba4d, 0xb5109ff0, 
+    0x78204cbe, 0xd0052801, 0x230148bd, 0x21102204, 0xfa57f010, 0x20012100, 0xfc91f7ff, 0x28027820, 
+    0x48b5d10d, 0xf010380a, 0x280efa2f, 0x48b5d107, 0x210e2200, 0x0000f990, 0x4010e8bd, 0xbd10e591, 
+    0x4db1b570, 0x4cae2803, 0x2805d004, 0x2804d017, 0xe030d017, 0x46282300, 0x210c2202, 0xfa31f010, 
+    0x46202301, 0x21802207, 0xfa2bf010, 0x46202300, 0x21102204, 0xfa25f010, 0xfc7ef7ff, 0x2302e017, 
+    0x2301e000, 0x22024628, 0xf010210c, 0x2300fa1a, 0x22074620, 0xf0102180, 0x2300fa14, 0x22044620, 
+    0xf0102110, 0x2100fa0e, 0xf7ff2002, 0x2100fc48, 0xf7ff2002, 0x2100fca4, 0xf7ff2002, 0x488ffc92, 
+    0x28027800, 0x488cd10b, 0xf010380a, 0xb241f9dd, 0x2200488c, 0x0000f990, 0x4070e8bd, 0xbd70e541, 
+    0xb5104886, 0x0000f990, 0x2802b110, 0xe011d004, 0xf7ff2001, 0xe00dfb55, 0x23014c7f, 0x1ea42206, 
+    0x46202140, 0xf9ddf010, 0x46202301, 0x21802207, 0xf9d7f010, 0xfc07f7ff, 0xfc2ef7ff, 0xfc55f7ff, 
+    0xfc66f7ff, 0xfc88f7ff, 0x23004c77, 0x461a2101, 0xf0104620, 0x2300f9c6, 0x22024620, 0xf010210c, 
+    0x4c6ff9c0, 0x22072300, 0x46202180, 0xf9b9f010, 0x46202300, 0xe8bd2204, 0x21104010, 0xb9b1f010, 
+    0xb5104966, 0x1000f991, 0x2901b189, 0x2902d014, 0x4861d143, 0xf010380a, 0x280ef987, 0x4861d13d, 
+    0x210e2200, 0x0000f990, 0x4010e8bd, 0xe8bde4e9, 0x20004010, 0xbb04f7ff, 0xb3004c59, 0xd0202801, 
+    0xd12a2802, 0x46202301, 0x21102204, 0xf989f010, 0x46202301, 0x21082203, 0xf983f010, 0x220e4853, 
+    0x0100f244, 0xf98bf010, 0x28014c4f, 0x2300d013, 0x21012200, 0xe8bd4620, 0xf0104010, 0x2300b972, 
+    0x2301e000, 0x22044620, 0xf0102110, 0x2300f96a, 0x21082203, 0x2301e7ee, 0xbd10e7ea, 0x4c3fb570, 
+    0x0000f994, 0x2801b110, 0xe010d004, 0xf7ff2001, 0xe00cfac7, 0x23004d3a, 0x21102204, 0xf0104628, 
+    0x2300f950, 0x22034628, 0xf0102108, 0xf7fff94a, 0x2300fbdf, 0x21014834, 0xf010461a, 0x7820f942, 
+    0xd10f2802, 0x23014c2c, 0x1ea42206, 0x46202140, 0xf937f010, 0xe8bd4620, 0x23014070, 0x21802207, 
+    0xb92ff010, 0x2100bd70, 0xb5102002, 0xfbb9f7ff, 0x78004822, 0xd10b2802, 0x380a481f, 0xf904f010, 
+    0x4820b241, 0xf9902200, 0xe8bd0000, 0xe4684010, 0xb510bd10, 0xfbacf7ff, 0x78004818, 0xd10f2802, 
+    0x23014c15, 0x1ea42206, 0x46202140, 0xf909f010, 0x46202301, 0xe8bd2207, 0x21804010, 0xb901f010, 
+    0x2100bd10, 0xf7ff2001, 0x2200bb63, 0x4614b510, 0x1e43b128, 0xd21b2b09, 0x700c2000, 0x20ffbd10, 
+    0xbd10700c, 0xf0f3fbb0, 0xb2d21c52, 0x0000e011, 0x1e0a6e00, 0xf0008168, 0xf23c80dc, 0x000425a2, 
+    0xf2035078, 0x00040292, 0xf20351da, 0xf38fffd4, 0x280a230a, 0x2805d8e6, 0x2001d302, 0xe0007008, 
+    0x4610700c, 0x0fc2bd10, 0x7fd1ebb2, 0xf1c1d203, 0x440831ff, 0x1a404770, 0x48184770, 0xf990b510, 
+    0x28030000, 0x2805d010, 0x2804d00e, 0x4814d00c, 0xf89af010, 0xd4050780, 0xf0104812, 0xb2c0f895, 
+    0xd0002800, 0xbd102001, 0x22054c0f, 0x46202120, 0xf8b5f010, 0xd0f52800, 0x46202204, 0xf0102110, 
+    0x2801f8ae, 0x4809d0ee, 0xf87ef010, 0xd1e92800, 0x1c804806, 0xf878f010, 0x0000e7e2, 0x0004024c, 
+    0xf3cfffc2, 0xf3cf2002, 0xf203502c, 0xf23c80e8, 0x4604b510, 0x680048f7, 0x0050f8b0, 0x10401e40, 
+    0xea400400, 0xf0400044, 0x48f30138, 0xf859f010, 0x215348f1, 0xf0103084, 0x48f0f854, 0x3184ea40, 
+    0x307c48ed, 0xf84df010, 0xbd102001, 0x210048ea, 0xf010b510, 0xe8bdf846, 0xf0014010, 0xb510bc74, 
+    0x4604b086, 0xfabcf001, 0xd0152800, 0x210048e2, 0xf0101d00, 0x2201f836, 0x21009204, 0x92059100, 
+    0xe9cd2001, 0x4adc1202, 0x91014623, 0x5130f240, 0xf7eb323c, 0x2001f81d, 0xbd10b006, 0x41f0e92d, 
+    0x48d70007, 0x835cf8df, 0xd1036805, 0x0000f998, 0xffaef7ff, 0x7626f505, 0x74a6f505, 0xf7ff4630, 
+    0xf7ffffce, 0x2200ffc3, 0x46294620, 0x1c526833, 0x6873c008, 0x3610b212, 0xc1082a53, 0x2f01dbf6, 
+    0xf998d103, 0xf7ff0000, 0x2100ff93, 0x46082201, 0x3b02f834, 0x4311b10b, 0x1c40b289, 0xb2000052, 
+    0x2810b212, 0x2200dbf4, 0xe2fcf8df, 0xc2fcf8df, 0x46903520, 0xf80c2000, 0xf0018002, 0xf3c1030f, 
+    0xeb0e1603, 0xeb0e0383, 0xf8d30686, 0xf8d630c0, 0x44336080, 0x2603f3c1, 0x0686eb0e, 0x44336c36, 
+    0xf85e0b0e, 0x44336026, 0x6b02f935, 0x03c3eb03, 0xda01429e, 0xe0002301, 0xf81c2300, 0xf8146002, 
+    0x405f7b02, 0x08494087, 0x1c40433e, 0xea41b200, 0xb28931c3, 0xf80c2808, 0xdbce6002, 0x549e4ba4, 
+    0xb2121c52, 0xdbc52a10, 0x81f0e8bd, 0xb085b5f0, 0x48984607, 0x4e9b2500, 0x95002101, 0x462a462c, 
+    0xf9b06800, 0xf996304e, 0xf0010000, 0x2001fb47, 0x23052180, 0x4001e9cd, 0x46189000, 0x1403e9cd, 
+    0x2000f996, 0xf0012107, 0xf001fafa, 0xb118fa09, 0xfa24f001, 0xd1100005, 0xf04fb17f, 0xf2406480, 
+    0x462011f4, 0xfdcff7e4, 0x6166f246, 0xf7e44620, 0x4988fdb9, 0xf7e44620, 0xf001fdb5, 0x4e83fba4, 
+    0x46202400, 0xfa11f001, 0x0024f846, 0xb2641c64, 0xdbf62c04, 0x4628b005, 0xe92dbdf0, 0x48784ff3, 
+    0x4689b08b, 0xaf044c7c, 0x0200f640, 0x90076800, 0x5180f500, 0x496f9109, 0x68098824, 0x305ef8b1, 
+    0x24101ae3, 0xfa0f005b, 0x2300fc83, 0x1e5d9308, 0xe887461e, 0x9f0b1028, 0xf8b14698, 0xf507104c, 
+    0x4b686700, 0x070ceba7, 0x0141eba7, 0x27023910, 0x3000f993, 0x7ce1ea4f, 0x4c9ceb01, 0x0c0df36f, 
+    0x010ceba1, 0x0c05f04f, 0xe9cdb209, 0xe9cd1702, 0x22072c00, 0xf0014661, 0x4860fb5d, 0x46132200, 
+    0xf9904693, 0x92020000, 0x4610900a, 0x27004957, 0x1c40540f, 0x2810b200, 0x4261dbf8, 0x0004eb09, 
+    0x90033020, 0x9806e128, 0x19074408, 0xf8309809, 0xf04f7017, 0xeb0030ff, 0x9f070047, 0xfa80fa0f, 
+    0x4408980a, 0xf8374420, 0xeb07c010, 0xf8300040, 0xebac0c02, 0x00c00000, 0xf980fa0f, 0x4f422001, 
+    0x0c80ea4f, 0x1780eb07, 0xfe0cfa23, 0xfc0cfa22, 0x0e0ff00e, 0x0c0ff00c, 0xf8371c40, 0xb200e02e, 
+    0x702cf837, 0xebae2803, 0xeb0c0c07, 0xfa0f0709, 0xdbe4f987, 0xe0d0f8df, 0x070ff003, 0x0c0ff002, 
+    0x9000f8cd, 0x7027f83e, 0x002cf83e, 0x0c0ff00b, 0xeb071a3f, 0xfa0f0009, 0x9802f980, 0x070ff000, 
+    0x002cf83e, 0x7027f83e, 0x98001a3f, 0x44384546, 0x9000b200, 0xeba6d904, 0xf04f0008, 0xe0020e00, 
+    0xeba82000, 0x4e260e06, 0xfb178837, 0xb237f60a, 0xeba99701, 0xfb190707, 0xfb070609, 0xe9dd0807, 
+    0x46910700, 0x9f001bc0, 0xe000fb00, 0xec07fb17, 0x469e9f02, 0xd2044566, 0x034eea4f, 0x0249ea4f, 
+    0x007be003, 0xea4f4666, 0x4540024b, 0xf1bad22a, 0x46800f01, 0xd0004650, 0xf1ba2000, 0xea403fff, 
+    0x90020047, 0x2000d003, 0x004bea40, 0x2001e028, 0x0000e7fa, 0x00042618, 0xf1000404, 0x800c14e5, 
+    0x0004022c, 0x00042590, 0x000433d0, 0x000434d0, 0x000434f0, 0xdcba01f5, 0x0004257e, 0x00042586, 
+    0x00042588, 0x0f01f1ba, 0xd0004650, 0xf1ba2000, 0xea403fff, 0x9002004e, 0x2000d00a, 0x0049ea40, 
+    0x46834546, 0xfa23d20e, 0x07c0f004, 0xe001d105, 0xe7f32001, 0xf004fa22, 0x2001e00a, 0xf04fe00a, 
+    0xe00730ff, 0x40e09802, 0xd1f607c0, 0xf004fa2b, 0xd1f407c0, 0xda002800, 0x9f0b4240, 0x1b3f440f, 
+    0x7ce7ea4f, 0x6c1ceb07, 0x0cfff02c, 0x0e0ceba7, 0xc020f8dd, 0xd10145e6, 0x2000b178, 0xdb3842a1, 
+    0xc010f8dd, 0x0c5cea4f, 0x2001b100, 0x70c0ea4c, 0x98059004, 0xd0021c40, 0x2001e01b, 0x9804e7ee, 
+    0x4c27f5a0, 0x0cbbf1bc, 0xf643d113, 0x443870e1, 0x17c527bb, 0x4595eb00, 0x050df36f, 0xb2001b40, 
+    0x48f79005, 0x7007251f, 0x704727a7, 0x70872700, 0x1c6870c7, 0x2d80d00d, 0x48f2da09, 0x28074028, 
+    0x9804d105, 0x48ee0e07, 0x00e5eb00, 0x1c6d7007, 0x9803b22d, 0xb2091c49, 0xdd024288, 0xf6ff2d80, 
+    0x9805aed2, 0xe8bdb00d, 0xe92d8ff0, 0xf8df4ff8, 0xf04fa3a0, 0x4fe40800, 0x34fff04f, 0x46424de3, 
+    0x6680f507, 0xf8da463b, 0x88000000, 0x8000f8cd, 0x0950ea4f, 0xf99048df, 0x20011000, 0xfb16f7ea, 
+    0x1000f8da, 0xf9b74bdc, 0xf8910000, 0x78192068, 0x44111fc9, 0x80304108, 0xe0212001, 0x0240eb07, 
+    0x1010f937, 0x2c02f932, 0xf8da1a89, 0xf8922000, 0x781ac068, 0x44621fd2, 0xb2094111, 0xf8261c62, 
+    0xd0051010, 0x460a2900, 0x4252da00, 0xdd054542, 0x46042900, 0x4249da00, 0xf881fa0f, 0xb2001c40, 
+    0xdbdb4548, 0xda002c03, 0xea4f2403, 0xeb0601e8, 0xf9320244, 0x28000c06, 0x4240da00, 0xdd014288, 
+    0xe0101ee4, 0x0c04f932, 0xda002800, 0x42884240, 0x1ea4dd01, 0xf932e007, 0x28000c02, 0x4240da00, 
+    0xdd004288, 0x20001e64, 0x18c1b263, 0x1011f836, 0x1010f825, 0xb2001c40, 0xdbf62811, 0x22004eaf, 
+    0x00c2eb05, 0x1008f9b0, 0x4006f9b0, 0x7002f9b0, 0xf9b04421, 0x443c4004, 0xeb014421, 0xeb0604c1, 
+    0x600c1182, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x443c7004, 0x7002f9b0, 0xeb041be4, 0x604c04c4, 
+    0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1be47004, 0x7002f9b0, 0xeb04443c, 0x608c04c4, 0x4008f9b0, 
+    0x7006f9b0, 0xf9b0443c, 0x1be47004, 0x7002f9b0, 0xeb041be4, 0x60cc04c4, 0x4008f9b0, 0x7006f9b0, 
+    0xc002f9b0, 0xf9b01be4, 0x44677004, 0xeb04443c, 0x610c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 
+    0x443c7004, 0x7002f9b0, 0xeb041be4, 0x614c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x1be47004, 
+    0x7002f9b0, 0xeb04443c, 0x618c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x1be47004, 0x7002f9b0, 
+    0xeb041be4, 0x61cc04c4, 0x4006f9b0, 0xf9b01c52, 0xb2127008, 0xc002f9b0, 0xf9b01be4, 0x44677004, 
+    0xeb04443c, 0x620c04c4, 0x4006f9b0, 0x7008f9b0, 0xf9b01be4, 0x443c7004, 0x7002f9b0, 0xeb041be4, 
+    0x624c04c4, 0x4006f9b0, 0x7008f9b0, 0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb04443c, 0x628c04c4, 
+    0x4006f9b0, 0x7008f9b0, 0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb041be4, 0x62cc04c4, 0x4008f9b0, 
+    0x7006f9b0, 0xf9b0443c, 0x1b3c7004, 0x7002f9b0, 0xeb04443c, 0x630c04c4, 0x4008f9b0, 0x7006f9b0, 
+    0xf9b0443c, 0x1b3c7004, 0x7002f9b0, 0xeb041be4, 0x634c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 
+    0x443c7004, 0x7002f9b0, 0xeb041b3c, 0x638c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0xf9b07004, 
+    0x44380002, 0x42404420, 0xeb002a04, 0x63c800c0, 0xaf16f6ff, 0x493a8828, 0x00c0eb00, 0x80080040, 
+    0x70034838, 0x8ff8e8bd, 0xf7ffb510, 0x2002fe8e, 0xfb1af7eb, 0xf2404604, 0xf6431100, 0xf7ff7060, 
+    0x2002fcfc, 0xfb10f7eb, 0x1a20492f, 0x1000f9b1, 0xf0f1fbb0, 0x6008492d, 0xe92dbd10, 0xf24041f0, 
+    0xf7ff2500, 0x2400fe72, 0x36fff04f, 0x6700f643, 0x0800f248, 0x4629e02e, 0xf7ff4638, 0x1c41fcde, 
+    0xf5a0d01e, 0xb200507e, 0x6480f04f, 0xeb000fc1, 0xf2403081, 0xb20611f4, 0xf7e44620, 0x491cfa84, 
+    0xf7e44620, 0x491bfa6f, 0xf7e44620, 0x4631fa6b, 0xf7e44620, 0x4918fa67, 0xf7e44620, 0xe00dfa63, 
+    0x1c641979, 0xb22417c8, 0x4090eb01, 0x000df36f, 0xb2071a08, 0xf0f5fb98, 0xdccc42a0, 0xe4634630, 
+    0x000434d0, 0x80000007, 0x00045a00, 0x00046400, 0x00042618, 0x00042590, 0x00042383, 0x000433d0, 
+    0x00042588, 0x00042586, 0x00042608, 0x0004258c, 0xa5a55a5a, 0xdde50000, 0xdcba01f5, 0x5c0849fe, 
+    0xe92d4770, 0x4cfd47f0, 0xf248b283, 0x26000700, 0x25074639, 0x220f4620, 0xfc03f00f, 0xf2402380, 
+    0x220031ff, 0xf00f4620, 0x2306fbfc, 0x21ff2200, 0xf00f1ca0, 0x48f2fbf6, 0x217f2200, 0xf8b06800, 
+    0x1d20304a, 0xfbedf00f, 0x0802f1a4, 0x46444639, 0xf00f4640, 0xf248fbcc, 0x46200180, 0xfbc7f00f, 
+    0xa398f8df, 0xf8df2400, 0xf10a939c, 0xf04f0a0e, 0xf04f0204, 0xf89901f0, 0x28030000, 0xd0054650, 
+    0xfbddf00f, 0x070043c0, 0xe004d01b, 0xfbd7f00f, 0x0000ea35, 0x1c64d013, 0xdbe842bc, 0x46442301, 
+    0x4640220a, 0x4629029d, 0xfbbbf00f, 0x46292300, 0x4620220a, 0xfbb5f00f, 0xe8bd4630, 0x260187f0, 
+    0x2200e7ec, 0x210f4650, 0xfbb9f00f, 0xf00049ce, 0x700a0201, 0x0240f3c0, 0xf3c0704a, 0x708a0280, 
+    0x00c0f3c0, 0xe7ea70c8, 0x220048c4, 0x41f0e92d, 0xf6433030, 0xf00f71ff, 0xb204fba2, 0x07e04dc3, 
+    0x2301d00e, 0x22094628, 0x4631025e, 0xfb89f00f, 0x46312300, 0x46282209, 0xfb83f00f, 0xb2241e64, 
+    0xf2404fb7, 0x68381600, 0x006af8b0, 0xfa0f1a20, 0x2400f880, 0x2301e00c, 0x22084631, 0xf00f4628, 
+    0x2300fb70, 0x22084631, 0xf00f4628, 0x1c64fb6a, 0x7a016838, 0x44117a42, 0xf8b07a82, 0xeb02006a, 
+    0x44080050, 0x0f40ebb4, 0x6838dbe5, 0xeba87a01, 0x49a70041, 0xf3c03062, 0x7809004c, 0xfbc7f7ec, 
+    0xe8bd4640, 0xe92d81f0, 0x468943f0, 0xb11ab143, 0xf1a44ca0, 0xe00d0584, 0xf1a44c9f, 0xe0090584, 
+    0x4c9cb122, 0xf1a43ca8, 0xe0030584, 0x34a84c99, 0x0584f1a4, 0xe004f890, 0xb9026807, 0xf04f2201, 
+    0xe01f0c00, 0x46192300, 0xfa274618, 0x07f6f600, 0xf1c0d007, 0xf8140820, 0x40736008, 0x6028f855, 
+    0x1c404071, 0x2820b200, 0xea5fdbef, 0xd00370ce, 0x40437820, 0x40416828, 0xf10c469e, 0x460f0c01, 
+    0xfc8cfa0f, 0xdbdd4594, 0x7e00e9c9, 0x83f0e8bd, 0x47fce92d, 0x48814682, 0x9204f8df, 0xf8df2501, 
+    0x460f81ec, 0x7001464a, 0x464002a9, 0xfbc4f00f, 0x487c4606, 0x0000f990, 0xd0172803, 0xd0222802, 
+    0xd02d2801, 0x3012486d, 0xfacef00f, 0x486b9001, 0xf00f3014, 0x9000fac9, 0x30164868, 0xfac4f00f, 
+    0x24009900, 0x4001ea40, 0xe02c9000, 0x30244863, 0xfabaf00f, 0x48619001, 0xf00f3026, 0x9000fab5, 
+    0x3028485e, 0x485de7ea, 0xf00f301e, 0x9001faad, 0x3020485a, 0xfaa8f00f, 0x48589000, 0xe7dd3022, 
+    0x30184856, 0xfaa0f00f, 0x48549001, 0xf00f301a, 0x9000fa9b, 0x301c4851, 0x4669e7d0, 0x46082200, 
+    0xff61f7ff, 0x46531c64, 0xdbf642bc, 0x462a4669, 0xf7ff4608, 0x9800ff58, 0x4848b281, 0xf00f300a, 
+    0x9800fa86, 0x48450c01, 0xf00f3008, 0x9801fa80, 0x4842b281, 0xf00f1d80, 0xf246fa7a, 0x46440700, 
+    0x46392300, 0x4640220d, 0xfa8bf00f, 0xf2404846, 0xf9903120, 0x28040000, 0x2805d01e, 0xf44fd01f, 
+    0x464b107a, 0x43452210, 0xf0f1fb95, 0x1a304621, 0xf00f3020, 0x2300fb51, 0x220d4639, 0xf00f4620, 
+    0x4833fa70, 0x78032201, 0xf9b04838, 0x20001000, 0xfb97f7ec, 0x87fce8bd, 0x007af44f, 0xf44fe7e1, 
+    0xe7de00fa, 0xb2834a2f, 0x4d24b570, 0xf24821ff, 0x70110400, 0x4621220f, 0xf00f4628, 0x2380fa52, 
+    0x31fff240, 0x46282200, 0xfa4bf00f, 0x22002306, 0x1ca821ff, 0xfa45f00f, 0x22004819, 0x6800217f, 
+    0x304af8b0, 0xf00f1d28, 0x4621fa3c, 0x23011eac, 0x220f4620, 0xfa35f00f, 0x46202300, 0x21402206, 
+    0xfa2ff00f, 0x46202300, 0x21202205, 0xfa29f00f, 0x46202300, 0x21102204, 0xfa23f00f, 0x46202300, 
+    0x461a210f, 0xfa1df00f, 0x46202300, 0x21802207, 0xfa17f00f, 0xe01b2301, 0x00042590, 0xf2035094, 
+    0x00042618, 0x00040284, 0x00042594, 0xf2035092, 0x00040293, 0x00042af8, 0x00042c48, 0x0004027f, 
+    0xf000810c, 0x0004027e, 0x00040292, 0x0004257e, 0xe8bd4620, 0x22074070, 0xf00f2180, 0xb570b9f2, 
+    0x24004efe, 0x0500f248, 0x46302204, 0xf00f21f0, 0xb241f9f6, 0x1c64b911, 0xdbf542ac, 0x46302204, 
+    0xf00f21f0, 0xb200f9ec, 0x070249f5, 0x2203d501, 0x0742e00c, 0x2202d501, 0x0782e008, 0x2201d501, 
+    0x07c2e004, 0x2200d001, 0x22ffe000, 0xb240700a, 0xb510bd70, 0xf7ff4604, 0x4620ff65, 0x4010e8bd, 
+    0xb510e7cd, 0x21004ce7, 0xf99448e7, 0x54812000, 0x2001f994, 0x54812101, 0x2002f994, 0x54812102, 
+    0x2003f994, 0x54812103, 0x3003f990, 0x2002f990, 0x1001f990, 0x0000f990, 0xf8acf7ed, 0x3003f994, 
+    0x2002f994, 0x1001f994, 0x0000f994, 0x4010e8bd, 0xbafaf7f0, 0xb53048d5, 0xe9d0b087, 0xe9cd1200, 
+    0x21001200, 0x91039102, 0xe9d0aa04, 0xe9cd1002, 0xa9021004, 0xf7ed4668, 0x48cdffa0, 0x7800466b, 
+    0x48ccb180, 0x1000f990, 0x2002f990, 0x1011f833, 0x1012f823, 0x1001f990, 0x0003f990, 0x1011f833, 
+    0x1010f823, 0x46082100, 0x2010f833, 0xb2001c40, 0xb2094411, 0xdbf72804, 0x10881c89, 0x680d49be, 
+    0x106ef8b5, 0xf9bd1a40, 0xb2001000, 0x0401f020, 0xf9332001, 0x428a2010, 0x4611dd00, 0xb2001c40, 
+    0xdbf62804, 0x2042f8b5, 0xf8b51c49, 0xf0210070, 0xeb000101, 0x4ab10342, 0x42458810, 0x0145eb01, 
+    0xb20d4419, 0xeba01b61, 0xb2010061, 0x801148ac, 0x78032201, 0xf7ec4628, 0xb007fa64, 0xbd304628, 
+    0x4ff0e92d, 0xb08b48a1, 0x929cf8df, 0xf8df4e9e, 0xe9d0a290, 0xe9cd1004, 0x20001005, 0x900349a1, 
+    0x90004605, 0x90029001, 0xf9919008, 0x91071000, 0x68094999, 0x90098809, 0x0851ea4f, 0xaa024669, 
+    0xf7eda805, 0x4892ff2a, 0xc000f890, 0x0f00f1bc, 0x4890d011, 0xf990a905, 0xf9902000, 0xf8313002, 
+    0xf8212012, 0xf9902013, 0xf9902001, 0xf8310003, 0xf8212012, 0xf8992010, 0x20007000, 0x4683ab04, 
+    0x56322f01, 0xb002f803, 0xe010f93d, 0x2140d009, 0xdd0b458e, 0xf931a905, 0x45c6e010, 0x2101da04, 
+    0xf240e003, 0xe7f31100, 0x54992102, 0xb2c01c40, 0xd3e52804, 0x7800487d, 0xd1022803, 0xf88d2001, 
+    0xf1bc0013, 0xd0070f00, 0x0010f89d, 0x0012f88d, 0x0011f89d, 0x0013f88d, 0x0170f242, 0xf7e306c8, 
+    0xf44ffefe, 0xf2400b00, 0x465811f4, 0xfeebf7e3, 0x4658496f, 0xfed6f7e3, 0xf9974f62, 0xf9971003, 
+    0xf9970000, 0xeb002001, 0xf9973001, 0x02091002, 0x1102eb01, 0x46584401, 0xfec4f7e3, 0xf00f4865, 
+    0x4601f883, 0xf7e34658, 0x4863febd, 0xf876f00f, 0x46584601, 0xfeb6f7e3, 0x1013f89d, 0x0010f89d, 
+    0x2011f89d, 0x3001eb00, 0x1012f89d, 0xeb010209, 0x44011102, 0xf7e34658, 0xf89dfea5, 0xf89d0010, 
+    0xb1581011, 0xf89d2900, 0xd0011012, 0xe023b309, 0xf89d2900, 0xd0151013, 0xe01db139, 0xf89db151, 
+    0xb9d91012, 0x0013f89d, 0x7838b168, 0x70397879, 0xe0237078, 0x0012f89d, 0xf89d2800, 0xd01c0013, 
+    0xe01bb908, 0xf997b941, 0x78784000, 0x707c7038, 0xf89de02b, 0xb1891013, 0xd0152802, 0x1011f89d, 
+    0xd0112902, 0x2012f89d, 0xd00d2a02, 0x3013f89d, 0xd0092b02, 0xd1182801, 0xb1b0e011, 0x4002f997, 
+    0x70b878f8, 0xe01070fc, 0x2201482c, 0x3000f89a, 0x1000f9b0, 0x000ff06f, 0xf963f7ec, 0x2901e005, 
+    0x2a01d103, 0x2b01d101, 0x492cd013, 0xf7e34658, 0xf7fffe49, 0xf899fe66, 0x28010000, 0xf9904818, 
+    0x5c310000, 0x4826d003, 0x28017800, 0x2001d009, 0x4922e008, 0x0000f44f, 0xfe34f7e3, 0x90092001, 
+    0x2000e00d, 0xfd04f7ff, 0x1000f89a, 0x2080f44f, 0xfee2f7ea, 0xb22d1c6d, 0xf6ff2d03, 0xf996aeef, 
+    0xad020003, 0xb014f8df, 0xf640220b, 0xf1ab0100, 0xf8350b88, 0x465f3010, 0xe0234658, 0xf20350a2, 
+    0x0004027e, 0x00042590, 0x0004259c, 0x0002eaf4, 0x0004232e, 0x00042598, 0x00042618, 0x0004257e, 
+    0x00040293, 0x00040298, 0x00042300, 0x00040284, 0x77777776, 0xf2030446, 0xf100000c, 0xdcba01f5, 
+    0x0004257a, 0xffcdf00e, 0x0002f996, 0xf240220a, 0xf8354100, 0x46383010, 0xffc3f00e, 0x0001f996, 
+    0xf2402209, 0xf8352100, 0x46383010, 0xffb9f00e, 0x0000f996, 0x01512208, 0x3010f835, 0xf00e4638, 
+    0xf996ffb0, 0xf10d0001, 0xf9960914, 0xf6473002, 0xf8397800, 0xf9962010, 0xf8390000, 0xf8393013, 
+    0x1a1f0010, 0x3003f996, 0xf8391a12, 0xb2931013, 0x1a0d2208, 0xf10b4641, 0xf00e0002, 0xb2bbff92, 
+    0x0704f10b, 0x46382200, 0xf00e217f, 0xb2abff8a, 0x22084641, 0xf00e4638, 0xf8dfff84, 0xf99881e0, 
+    0x5c300000, 0xf9982800, 0x5c300002, 0x2802d003, 0x2300d005, 0x2802e006, 0x2301d003, 0x2302e002, 
+    0x2303e000, 0x22064658, 0xf00e21c0, 0x9809ff6a, 0xd07d2800, 0xfdcef7ff, 0xf7eb2000, 0x4e68fa99, 
+    0x28017830, 0xf7ebd00b, 0xf04ffe54, 0xf2424b00, 0x46580170, 0xfd93f7e3, 0xb1187830, 0xf7ebe015, 
+    0xe7f2fdfc, 0x20012100, 0xfa7df7ed, 0x21004d5d, 0xf995200c, 0xf7ec2000, 0x2101ffe4, 0x2000f995, 
+    0xf7ed4608, 0xf7f0f824, 0xf242fb40, 0x46580170, 0xfd75f7e3, 0x78004854, 0xd0022805, 0x25002701, 
+    0x2703e008, 0xf7ffe7fb, 0xb204fab8, 0xda032c00, 0xb22d1c6d, 0xdbf642bd, 0xd0391c60, 0x90082001, 
+    0xf7eb2000, 0x07e0fa55, 0x4848d00a, 0xf89a2201, 0xf9b03000, 0x46101000, 0xf843f7ec, 0xb2241c64, 
+    0x1000f89a, 0x46541060, 0xff81f7eb, 0x22014d3f, 0x20007823, 0x1000f9b5, 0xf833f7ec, 0x4669aa02, 
+    0xf7eda805, 0x483afd1a, 0xb1787800, 0x2000f998, 0x3002f998, 0x2012f839, 0x2013f829, 0x2001f998, 
+    0x0003f998, 0x2012f839, 0x2010f829, 0xe0002001, 0xf9bde04f, 0x464b1014, 0x2010f933, 0xda00428a, 
+    0x1c404611, 0x2804b2c0, 0x4f2ad3f6, 0xb2083908, 0x794a6839, 0x441a798b, 0xeb03790b, 0x882b0060, 
+    0x8f4a4410, 0x1a10441a, 0x2038f891, 0x2100b200, 0xff69f7eb, 0xf9b06838, 0xf7ed0040, 0x7821f93c, 
+    0x0000f640, 0xfd98f7ea, 0x28017830, 0x4815d017, 0x0000f990, 0x1cc09007, 0xeb0017c1, 0xf0217191, 
+    0x1a400103, 0xf7f0b240, 0xf7ebfc42, 0xf242fda2, 0x46580170, 0xfce3f7e3, 0xb1207830, 0x2000e006, 
+    0xfd0af7eb, 0x9807e7f3, 0xfc31f7f0, 0xf7eb2001, 0x9808f9cf, 0xe8bdb00b, 0x00008ff0, 0x00042598, 
+    0x0004257a, 0x00040298, 0x00040292, 0x0004257e, 0x0004232e, 0x00042618, 0x41f0e92d, 0x9e062a05, 
+    0x2a04d001, 0x2b01d115, 0x2b02d00a, 0x4b51d008, 0x781b4f51, 0x433b783f, 0x4b50d002, 0xb143781b, 
+    0x781b4b4f, 0xd1022b01, 0xd1002a05, 0x1c80b130, 0xb131b240, 0xeb012101, 0xe0030040, 0x30fff04f, 
+    0x0040e7f8, 0x280cb240, 0x2400da03, 0x050cf1c0, 0xf1a0e014, 0x290c010c, 0x2401d203, 0x0518f1c0, 
+    0xf1a0e00c, 0x290c0118, 0x2402d203, 0x0524f1c0, 0x2824e004, 0x2403db02, 0x0530f1c0, 0x0200f04f, 
+    0xf04fb2a3, 0x2e010103, 0x4836d040, 0xfe39f00e, 0xb2a34834, 0x21032200, 0xf00e1c80, 0x4831fe32, 
+    0x2200b2a3, 0x1d002103, 0xfe2bf00e, 0xb2a3482d, 0x21032200, 0xf00e1d80, 0x482afe24, 0x2200b2ab, 
+    0x302e210f, 0xfe1df00e, 0xb2a34e27, 0x210c2202, 0xf00e4630, 0xb2a3fe16, 0x22004630, 0xf00e2103, 
+    0x1cb6fe10, 0x4630b2a3, 0x210c2202, 0xfe09f00e, 0x4630b2a3, 0x21032200, 0xfe03f00e, 0x210f2200, 
+    0x1cb0b2ab, 0x41f0e8bd, 0xbdfbf00e, 0x30084815, 0xfdf7f00e, 0xb2a34813, 0x21032200, 0xf00e300a, 
+    0x4810fdf0, 0x2200b2a3, 0x300c2103, 0xfde9f00e, 0xb2a3480c, 0x21032200, 0xf00e300e, 0x4809fde2, 
+    0x2200b2ab, 0x3030210f, 0xfddbf00e, 0x41f0e8bd, 0xbe46f7eb, 0x000425f9, 0x00042556, 0x0004232e, 
+    0x0004230e, 0xf2034200, 0xf203900e, 0x220e4912, 0x4d12b570, 0x18447809, 0x0100f24c, 0x0303f004, 
+    0xf00e4628, 0x2200fdbe, 0x1ca82107, 0x0382f3c4, 0xfdb7f00e, 0x46282301, 0x21202205, 0xfdb1f00e, 
+    0x20402100, 0xfc88f7ea, 0xe8bd4628, 0x23004070, 0x21202205, 0xbda5f00e, 0x0004237b, 0xf203f042, 
+    0x4cfeb510, 0xf7eae002, 0xb160fc35, 0xf00e4620, 0x0300fd75, 0x0002f04f, 0xf7ead4f5, 0x49f8fc25, 
+    0x20016008, 0x4cf7bd10, 0xf00e4620, 0xf040fd6d, 0x46200110, 0xfd6bf00e, 0xbd102000, 0xb51048ef, 
+    0xf00e1d00, 0x0fc0fd5b, 0x49ecbd10, 0x0003f1c0, 0xeb01310c, 0xf00e0080, 0xe92dbd51, 0xf8df41f0, 
+    0x108d839c, 0x4604b086, 0x0840f1a8, 0x2b01b133, 0x2b02d014, 0x2b03d06e, 0xe0a8d06f, 0x90052000, 
+    0x90042201, 0x46239000, 0xe9cd9001, 0x00880202, 0xb2014642, 0xf7e92001, 0xe098fd2b, 0xf04f2a07, 
+    0xd0540600, 0x0745eb05, 0x4640e019, 0xfd26f00e, 0x0026f844, 0xf00e4640, 0x1971fd21, 0x0021f844, 
+    0xf00e4640, 0xeb06fd1b, 0xf8440145, 0x46400021, 0xfd14f00e, 0x1c7619b9, 0xf844b236, 0x42ae0021, 
+    0xe074dbe3, 0x46404647, 0xfd08f00e, 0x0202f000, 0x0101f000, 0x31c2ea41, 0x1026f844, 0x0108f000, 
+    0x0280f3c0, 0x3141ea42, 0xf8441972, 0xf0001022, 0xf3c00120, 0xea421200, 0xeb0621c1, 0xf8440245, 
+    0xf0001022, 0xf3c00180, 0xea401080, 0xeb052041, 0x44310145, 0x0021f844, 0xf00e4638, 0x4638fcdf, 
+    0xfcdcf00e, 0xf00e4638, 0x1c76fcd9, 0x42aeb236, 0xe03cdbc8, 0x46472600, 0xe015e013, 0xf00e4638, 
+    0x1971fccd, 0x0021f844, 0xf00e4638, 0xf844fcc7, 0x46380026, 0xfcc2f00e, 0xf00e4638, 0x1c76fcbf, 
+    0x42aeb236, 0xe022dbea, 0x463e2700, 0x4640e01d, 0xfcb4f00e, 0x0027f844, 0x46401c7f, 0xf00eb23f, 
+    0xf844fcad, 0x1c7f0027, 0xb23f4640, 0xfca6f00e, 0x0027f844, 0x46401c7f, 0xf00eb23f, 0xf844fc9f, 
+    0x1c7f0027, 0xb23f1c76, 0x42aeb236, 0xb006dbdf, 0x2100488a, 0xe8bd387c, 0xf00e41f0, 0xe92dbc92, 
+    0x27005ff0, 0x2b0b4698, 0xe9dd4692, 0xf8dd6b0d, 0x460c902c, 0xd1044605, 0x46494880, 0xf00e301c, 
+    0x1c60fc80, 0x2c07d007, 0x2d05d106, 0x2d06d001, 0x2701d102, 0x2400e000, 0xdd022e00, 0x1e401070, 
+    0x4876b206, 0x30084631, 0xfc6bf00e, 0xea4f980c, 0xea41718b, 0xea417109, 0x980a5100, 0x40c0ea41, 
+    0x4187ea40, 0x318aea41, 0x2088ea41, 0x1144ea40, 0x4329486a, 0x5ff0e8bd, 0xbc53f00e, 0x460db570, 
+    0x9c041059, 0xea410409, 0xea411142, 0xea4101c5, 0xf0400040, 0x48610110, 0xf00e387c, 0x2c00fc42, 
+    0x485ed006, 0xe8bd4621, 0x38784070, 0xbc39f00e, 0xb570bd70, 0x48594606, 0x460d4614, 0xf6402200, 
+    0x1d0071ff, 0xfc44f00e, 0xb925b12e, 0x0064ebb0, 0xf500d501, 0xf6436040, 0xe8bd71ff, 0x00834070, 
+    0x2200484e, 0xf00e3878, 0xb5f0bc25, 0x56614c4e, 0x29013c10, 0x2910d011, 0x2501da0f, 0x408d1e49, 
+    0xf04f6065, 0x408d35ff, 0x6021b2a9, 0x040989a1, 0x892160e1, 0x60a10409, 0x2100e001, 0x68676061, 
+    0x2f00b132, 0x6826d01c, 0xe9d42100, 0xe0264502, 0xd0152f00, 0x21006826, 0x4502e9d4, 0xf850e00d, 
+    0x423a2021, 0x4332d002, 0x2021f840, 0xd002422a, 0xf8404322, 0x1c492021, 0xebb1b209, 0xdbee0f43, 
+    0xf850bdf0, 0x423a2021, 0x4332d002, 0x2021f840, 0xd002422a, 0xf8404322, 0x1d092021, 0xebb1b209, 
+    0xdbee0f43, 0x4825bdf0, 0x22032301, 0x30482108, 0xbbd0f00e, 0x4fffe92d, 0xf04fb081, 0x46980900, 
+    0x460d4614, 0x0a01f04f, 0x464f9e0e, 0xb00fe9dd, 0x7f80f5b6, 0x9000f8cd, 0x4430dc01, 0xf1bbb200, 
+    0xd0050f05, 0x1c612000, 0x2c07d00e, 0xe00cd006, 0xf04f1040, 0xf04f0901, 0xe7f40a00, 0xd0012d05, 
+    0xd1022d06, 0xe0072701, 0x490f2400, 0x5d49310b, 0xd1012901, 0x0800f04f, 0xea410401, 0xea411149, 
+    0xf0400048, 0x48050118, 0xf00e387c, 0x4803fb8a, 0x30089900, 0xfb85f00e, 0xe00704b9, 0xf1000480, 
+    0x00040280, 0xf203517e, 0x00042c7c, 0x3088ea41, 0x1144ea40, 0x4329481d, 0x481d4301, 0xfb71f00e, 
+    0x7801481c, 0x4000f240, 0xfa66f7ea, 0x700aea4f, 0x4187ea40, 0x3188ea41, 0x208bea41, 0x1044ea40, 
+    0xf4404328, 0x48122100, 0xfb5bf00e, 0xfdd8f7ff, 0xd0182800, 0xf00e4810, 0xb204fb57, 0x46329900, 
+    0xf7ff4648, 0x0070ff16, 0xb2019b11, 0x462a9801, 0xfdf3f7ff, 0xff77f7ff, 0x46339801, 0x4629463a, 
+    0xff23f7ff, 0xb0054620, 0x8ff0e8bd, 0x00080400, 0xf1000480, 0x00040293, 0xf2035120, 0x4ff0e92d, 
+    0xf8dfb08b, 0x2000b408, 0xf8df49ff, 0x9006a404, 0x900848fb, 0x90072009, 0x680448fa, 0xf89b9109, 
+    0x46a01000, 0xf89ab131, 0x29011001, 0x49f6d002, 0x91091c89, 0x93dcf8df, 0x4ff822b1, 0x5080f504, 
+    0x21014ef5, 0x2000f8c9, 0x90054635, 0x50c0f504, 0xf9979004, 0xf7ef0000, 0xf997ff0d, 0xf7ef0000, 
+    0x21b2fdbe, 0x1000f8c9, 0xf7ef2000, 0x2002fd62, 0xffe7f7ef, 0x0000f997, 0xfd62f7ef, 0xf2442100, 
+    0xf7ef0000, 0xf997fdba, 0xf7ef0000, 0x2100fd15, 0x2000f44f, 0xf9e0f7ea, 0x48e121b3, 0xf8c923c0, 
+    0x22001000, 0x11fff240, 0xfafbf00e, 0x0000f997, 0xfe5cf7ef, 0xe00b2000, 0x780949da, 0x2901b1d9, 
+    0x49d9d01b, 0x1010f831, 0x1010f825, 0xb2001c40, 0x680949d6, 0xebb08809, 0xdbed0f51, 0x780048cb, 
+    0xf04f2800, 0xd00b0000, 0xe9cd2300, 0xf99a5000, 0x461a1001, 0x49cee009, 0x49cbe7e4, 0xe7e13980, 
+    0x21012300, 0xe9cd461a, 0x20015000, 0xff2bf7e8, 0xf24048c8, 0x78002b00, 0xd1032805, 0x780048c6, 
+    0xd0272801, 0xf8df2101, 0x200592dc, 0xb000f8cd, 0x9103028a, 0x465f460b, 0xe9cd4601, 0x1f820201, 
+    0x0000f8d9, 0xfec6f7ff, 0xf04f48b0, 0x78000100, 0x46082800, 0xf99ad07e, 0xeb082001, 0xf9332382, 
+    0x2a002011, 0x4252da00, 0xb2091c49, 0x441042b9, 0xe0d9dbf5, 0x46384fb1, 0xfa76f00e, 0x900a2300, 
+    0x461a2101, 0xf00e4638, 0x4badfa8c, 0x20002100, 0x0781eb00, 0x2200469a, 0xb2001c40, 0xf8432804, 
+    0xdbf52027, 0xb2091c49, 0xdbf02902, 0x27004691, 0xb2bb48a2, 0x21802207, 0xfa73f00e, 0xf8cd2001, 
+    0x2205b000, 0x02819003, 0xe9cd4603, 0x1e822101, 0x2103488c, 0xf7ff6800, 0x2100fe7d, 0x220046dc, 
+    0x2381eb08, 0xf9334610, 0x4472e010, 0x0e40eb03, 0xb2001c80, 0xe002f9be, 0xeba24560, 0xdbf2020e, 
+    0xda002a00, 0x46d64252, 0x0087eb01, 0xb2091c49, 0x3020f85a, 0x441a2904, 0x2020f84a, 0x1c7fdbdf, 
+    0x2f02b23f, 0xf109dbc4, 0xfa0f0001, 0xf1b9f980, 0xdbbc0f10, 0x9208f8df, 0x46732000, 0xf1094607, 
+    0xf04f0930, 0xf1a90a01, 0xf8530e10, 0xeb031020, 0xe0000280, 0x6912e05c, 0xda044291, 0x7020f849, 
+    0x1020f84e, 0xf849e003, 0xf84ea020, 0x1c402020, 0x2804b200, 0xe9dedbe9, 0x42880100, 0x2100da02, 
+    0xe0012701, 0x27002101, 0xf85e2002, 0xf85ec021, 0xf85e3027, 0x45622020, 0x460fda02, 0xe0024601, 
+    0xda00429a, 0xf85e4607, 0x1c40c021, 0xf85eb200, 0x28043027, 0xf839dbed, 0x22070027, 0xb2832180, 
+    0xf00e485e, 0x4850f9ee, 0x4100f240, 0xf8cd2205, 0x1e80b000, 0xa00cf8cd, 0x0047eb00, 0x48499009, 
+    0xe9cd2301, 0x1f922101, 0x68002105, 0xfdf2f7ff, 0xeb082100, 0x46082387, 0xf933465f, 0x2a002011, 
+    0x4252da00, 0xb2091c49, 0x441042b9, 0xe00bdbf5, 0x3000f8d9, 0x2011f933, 0xda002a00, 0x1c494252, 
+    0x42b9b209, 0xdbf54410, 0x21001240, 0xdd052810, 0x1c491c40, 0xb2491040, 0xdbf72906, 0x78004841, 
+    0xd0012803, 0xe000b141, 0x1e4a2105, 0x40902001, 0x4f36b202, 0xe0102000, 0xe7f92000, 0x781b4b31, 
+    0xd04c2b00, 0xd06f2b01, 0xf9334b2f, 0x44133010, 0xf825410b, 0x1c403010, 0x683bb200, 0xebb0881b, 
+    0xdbeb0f53, 0xf04f4f23, 0x20b40800, 0x46424643, 0x60384641, 0xe9cd2001, 0xf7e85800, 0x20b5fde4, 
+    0x23006038, 0x461a2101, 0x5800e9cd, 0xf7e84608, 0x20b6fdda, 0x23006038, 0x461a2102, 0xe9cd2001, 
+    0xf7e85800, 0x20b7fdd0, 0x23006038, 0x461a2103, 0xe9cd2001, 0xf7e85800, 0x20b8fdc6, 0x60384641, 
+    0xf8462000, 0x1c401020, 0xf5b0b200, 0xdbf87f00, 0xf6402500, 0x20020b00, 0xffe6f7e9, 0xe06ce025, 
+    0x0002f590, 0x0004022c, 0xf203044c, 0x0004232e, 0x00042598, 0x000426b4, 0x00045a00, 0x00040298, 
+    0xf2030864, 0x00042383, 0x00042e34, 0x00042618, 0x00042cb4, 0x00040292, 0x0004230e, 0xf2030a00, 
+    0x0004e968, 0x00040284, 0xf8dfe04a, 0x4623a404, 0xf8ca4657, 0x20b9001c, 0x3105eb00, 0x600148fd, 
+    0x48fd2101, 0xf8cd9a09, 0xf00fb000, 0x2002f823, 0xffaaf7e9, 0xf04f69f9, 0xf8df0900, 0x465a83e0, 
+    0x49f61a08, 0x0814f108, 0x464861f8, 0x9025f841, 0x31fff04f, 0x1015f828, 0xf8544649, 0x1c403020, 
+    0x4290b200, 0xdbf84419, 0x200012c9, 0x3020f854, 0xf8441a5b, 0x1c403020, 0x4290b200, 0x48e8dbf6, 
+    0x0000f990, 0xd00d2804, 0xd00d2805, 0x22042700, 0x40ba2000, 0x6300f5c2, 0x4bdde019, 0xe7443320, 
+    0xe7424be0, 0xe7f22702, 0xe7f02701, 0xe00a2101, 0x0e01eb00, 0xc020f854, 0xb2091c49, 0xe02ef854, 
+    0xf84444f4, 0x428ac020, 0x1c40dcf2, 0x4283b200, 0x2100dcec, 0x0e06f1c7, 0xe0094608, 0xc021f854, 
+    0xb2094411, 0xfc0efa0c, 0xc020f844, 0xb2001c40, 0xdcf3428b, 0xf2404649, 0x42902200, 0xf844da04, 
+    0x1c401020, 0xe7f8b200, 0x9308f8df, 0xeb0020ba, 0xf8c93105, 0xe9dd1000, 0x9b041007, 0x0100e9cd, 
+    0x2105e9dd, 0xf00e4620, 0x20bbf9af, 0xc2ecf8df, 0x3105eb00, 0x1000f8c9, 0xf1c72001, 0xf1c7010b, 
+    0x4088070c, 0x200eb203, 0xf8519905, 0x18ca1020, 0x413a9904, 0x1020f851, 0x44194352, 0xfb014139, 
+    0xf8442101, 0xf8561020, 0x1d092020, 0x01e1eb02, 0x1020f846, 0x1020f854, 0x2025f85c, 0xdd034291, 
+    0x1025f84c, 0x0015f828, 0xb2001c40, 0xdbdb28c3, 0x1015f938, 0xeb041e48, 0xf8540c81, 0xf8542021, 
+    0x44083020, 0xc004f8dc, 0x41c8f04f, 0x0742eba3, 0xf5074467, 0x1a9a7700, 0xfb9212bb, 0xeb02f2f3, 
+    0xf8ca2040, 0xf8da0018, 0xfb80201c, 0x17d30101, 0xe9aef00d, 0x8244f8df, 0x4240f04f, 0xf1a81882, 
+    0xf1410828, 0xeb0830ff, 0xf44f07c5, 0xe9c73a00, 0x488d2000, 0x1035f858, 0x1025f840, 0x1103f240, 
+    0xf7e24650, 0x6838fe60, 0x0c007939, 0x4001ea40, 0x4650b281, 0xfe46f7e2, 0x0035f838, 0x4650b281, 
+    0xfe40f7e2, 0xeb0020bc, 0xf8c93105, 0x1c6d1000, 0x2d05b26d, 0xaebff6ff, 0x25004a78, 0xf1021e68, 
+    0x60150314, 0x200e8018, 0x1020f856, 0x1020f844, 0x1020f856, 0x7025f852, 0xdd0342b9, 0x1025f842, 
+    0x0015f823, 0xb2001c40, 0xdbed28c3, 0x0015f933, 0xeb041e41, 0xf8560480, 0x44083020, 0x2021f856, 
+    0x41c8f04f, 0xeba26864, 0x44340643, 0x7400f504, 0x12a31ad2, 0xf2f3fb92, 0x2040eb02, 0x61904a5c, 
+    0xfb8069d2, 0x17d30101, 0xe942f00d, 0x4240f04f, 0x18824e5a, 0xf1414f57, 0x3e2830ff, 0x04c5eb06, 
+    0x3800f44f, 0x2000e9c4, 0xf8564857, 0x61411035, 0xf24020bd, 0x60381103, 0xf7e24640, 0x6820fdf4, 
+    0x0c007921, 0x4001ea40, 0x4640b281, 0xfddaf7e2, 0x0035f836, 0x4640b281, 0xfdd4f7e2, 0x0035f836, 
+    0xb2017922, 0x0c006820, 0x4002ea40, 0xf7efb200, 0x20befa54, 0x48456038, 0x0000f990, 0xf9acf7ef, 
+    0x603820bf, 0xf7e82001, 0x483dfdae, 0x28057800, 0x483fd10a, 0x28017800, 0x990ad106, 0x483db00b, 
+    0x4ff0e8bd, 0xbf73f00d, 0xe8bdb00b, 0xe92d8ff0, 0x25004ffe, 0x462c2101, 0x4071f04f, 0x9502462a, 
+    0xff76f00d, 0x28014e31, 0x2301d009, 0x31fef240, 0x0000f996, 0xf7ef2200, 0xe8bdf9e3, 0x22088ffe, 
+    0x0151482d, 0xff7bf00d, 0x23002208, 0xfa4f0151, 0x4829fb80, 0xff65f00d, 0xf04f4828, 0x4f28090a, 
+    0x0301f04f, 0x809cf8df, 0x0200f04f, 0x28017800, 0xe9cdd06c, 0xf9968700, 0x20011000, 0xfc5ef7e8, 
+    0xc088f8df, 0xf8df2000, 0x4643a080, 0x0850f10c, 0xe030f85c, 0x1010f93a, 0x2011f937, 0x1011f933, 
+    0x2e0efba2, 0xf8581955, 0xf1002030, 0xb2c00001, 0x1202fba1, 0x4548190c, 0x4815d3ea, 0xf9961b2c, 
+    0xf04f1000, 0x4f020500, 0x4021f840, 0xe0216978, 0x00042c94, 0x000426b4, 0xf2030406, 0x0004e948, 
+    0x00040292, 0x00042db4, 0x00043318, 0x00040298, 0x0004230e, 0xf2030a00, 0xf2035126, 0x00040296, 
+    0x00049200, 0x00048a00, 0x0002ea3c, 0x0004e5d8, 0x00043308, 0x0001f100, 0x0203f04f, 0x0138f04f, 
+    0x48fe6178, 0xff0bf00d, 0xd07c2800, 0x83f0f8df, 0x22022303, 0x4640210c, 0xfef3f00d, 0x93e0f8df, 
+    0x0000f44f, 0xf1a99002, 0xe098096e, 0xe9cd48f5, 0xf9908700, 0x20011000, 0xfbf0f7e8, 0xf8df2400, 
+    0x21c983c8, 0xfa01fb19, 0x4aef48f0, 0xf9303a78, 0x48ef1014, 0x0011f830, 0x0014f822, 0xf8324aed, 
+    0x4ae95011, 0xf10afb11, 0xf8223a64, 0xfb105014, 0xfb15f200, 0xfb812205, 0x04c12302, 0x46162000, 
+    0xf00d461f, 0x0c02e826, 0xea4248df, 0x463b4201, 0x14093850, 0x00c4eb00, 0x2100e9c0, 0x463204e9, 
+    0xf00d2000, 0x0c02e816, 0x4201ea42, 0x00c4eb08, 0x1c641409, 0x454cb2e4, 0x2100e9c0, 0x4cd1d3c4, 
+    0xf9942100, 0xf7ef0000, 0x49d3fa85, 0x23012000, 0x7008461a, 0xf9944601, 0xf7ef0000, 0x48c7f901, 
+    0x21382203, 0xfe9bf00d, 0xd0302800, 0x23034cc4, 0x210c2202, 0xf00d4620, 0x4dc1fe84, 0x0100f44f, 
+    0x3d6e9102, 0xe066e007, 0x462a210a, 0xf7e9a802, 0x2801fde8, 0x2202d006, 0x210c4620, 0xfe7ff00d, 
+    0xd1f12800, 0x300848b6, 0xfe4ef00d, 0x81604cbb, 0x1d8048b3, 0xfe48f00d, 0x48b181a0, 0xf00d3010, 
+    0x81e0fe43, 0x300e48ae, 0xfe3ef00d, 0xe0758220, 0x464a210b, 0xf7e9a802, 0x2801fdc4, 0x2202d006, 
+    0x210c4640, 0xfe5bf00d, 0xd1f12800, 0x300848a4, 0xfe2af00d, 0x48a28078, 0xf00d1d80, 0x80b8fe25, 
+    0x3010489f, 0xfe20f00d, 0x489d80f8, 0xf00d300e, 0xb200fe1b, 0xf9b78138, 0xf9b71002, 0x4291200a, 
+    0xf9b7d10f, 0xf9b72004, 0x429a300c, 0xf9b7d109, 0xf9b72006, 0x429a300e, 0xf9b7d103, 0x42902010, 
+    0x697ad003, 0x1e522501, 0x8179617a, 0x81b988b9, 0x81f988f9, 0x17e38238, 0x46229500, 0x0000f996, 
+    0xfb33f7ef, 0x0200f248, 0x10510055, 0xdd152c00, 0xdd0f4294, 0x2200488a, 0xf00d213f, 0x281afe10, 
+    0xf240d202, 0xe00111ff, 0x31fef240, 0xdc0f42ac, 0xe00d0849, 0xdd08428c, 0xe0092103, 0x42904260, 
+    0x42a8dd05, 0x2105dd01, 0x2102e002, 0x2100e000, 0x0000f996, 0x461a2301, 0xf852f7ef, 0x22084870, 
+    0xf38bfa1f, 0x38c40151, 0xfddbf00d, 0xe92de665, 0xb0894ff0, 0x3000f44f, 0x10849002, 0xf00d4871, 
+    0x4971fdb3, 0x0003f000, 0x290a7809, 0x496fd203, 0x29007809, 0xf241d17d, 0xb1280100, 0xd0052801, 
+    0xd0072802, 0xd0062803, 0xe0049102, 0x0000f244, 0xe0009002, 0x22009402, 0x21019802, 0x70d0eb00, 
+    0x90071040, 0x4071f04f, 0xfda2f00d, 0xd1782801, 0xf04f485f, 0x78000b0a, 0xd0052801, 0x485d2400, 
+    0x28007800, 0xe06fd175, 0xa148f8df, 0x48552500, 0x30142100, 0x1045eb00, 0xfd79f00d, 0x20004956, 
+    0x22002301, 0x0015f821, 0xf8304854, 0x1c491015, 0x1015f820, 0x46184946, 0x1a00e9cd, 0xf7e8b269, 
+    0x2400fa8d, 0x4841e042, 0x4a3f23c9, 0xf9303250, 0x483f1014, 0x0011f830, 0x0014f822, 0xf83a3214, 
+    0xf8226011, 0xfb1b6014, 0xfb11f203, 0xfb10f102, 0xfb16f200, 0xfb812206, 0x04c12302, 0x46172000, 
+    0xf00c4698, 0x4b30eec6, 0xeb050c02, 0x33780985, 0x4201ea42, 0x1009eb03, 0x14094643, 0x00c4eb00, 
+    0x2100e9c0, 0x463a04f1, 0xf00c2000, 0x0c02eeb2, 0xe016e000, 0xea424b32, 0x14094201, 0x1009eb03, 
+    0x00c4eb00, 0xb2e41c64, 0x2100e9c0, 0xd3ba455c, 0xb2ed1c6d, 0xd39a2d04, 0x20004925, 0x491f7008, 
+    0xb0097008, 0xe004e5a1, 0xf9904816, 0x42840000, 0x4824d07e, 0x28017800, 0x4823d0f3, 0x28017800, 
+    0x4822d0ef, 0x28017800, 0x4e12d0eb, 0x4d102301, 0x2200b261, 0x4618468a, 0x5600e9cd, 0xfa1ef7e8, 
+    0x4d092000, 0x0384eb04, 0x35784601, 0xeb054681, 0x95081503, 0x46024d12, 0xe0294680, 0xf38f007c, 
+    0xf20351ea, 0x00040298, 0x0004e628, 0x0002ea3c, 0x00048a00, 0x00049200, 0x00040296, 0x00042c94, 
+    0xf2034202, 0xf203086e, 0x0004257c, 0x000402f2, 0x00040297, 0x0004257a, 0x0004029a, 0x000402a2, 
+    0x0004e7e0, 0x000402d9, 0x00042fcf, 0x00042fd0, 0x1303eb05, 0xe02a9301, 0x4f479b08, 0x03c0eb03, 
+    0x5600e9d3, 0xf9334b43, 0x93003010, 0x3013f937, 0xce03fba5, 0xfb0617df, 0xfb05e303, 0xeb1c3307, 
+    0x4f3e0909, 0x9b014159, 0x03c0eb03, 0x5600e9d3, 0xf9379b00, 0xfba53013, 0x17dfce03, 0xe303fb06, 
+    0x3307fb05, 0x0808eb1c, 0x1c40415a, 0xe000b2c0, 0x4558e05a, 0xebb9d3d0, 0xeb610008, 0xf06f0102, 
+    0x22004300, 0x418a1a1b, 0xf06fda02, 0xe0054000, 0x1a824a2b, 0x31fff171, 0x4829da00, 0x2800ad03, 
+    0xf8454601, 0xda000024, 0x9a024249, 0xdd0c4291, 0xda042800, 0xf04f4823, 0x700101ff, 0xdd2ee013, 
+    0xf04f4820, 0x70010101, 0x4a1ee01b, 0x1000f992, 0xd0220049, 0x46012800, 0x4249da00, 0x42999b07, 
+    0x2800dd1b, 0x4818da0c, 0x1014f830, 0x0102f1a1, 0x1014f820, 0x0101f06f, 0xf7ef4650, 0xe00ef8ad, 
+    0xf04fdd0d, 0x46500102, 0xf8a6f7ef, 0xf830480e, 0x1c891014, 0x1014f820, 0x2000e001, 0x490b7010, 
+    0x0024f855, 0x0024f841, 0xb2e41c64, 0xf4ff2c04, 0xe716aea6, 0x0002ea3c, 0x00049200, 0x00048a00, 
+    0x80000001, 0x00042c94, 0x0004029a, 0x00043308, 0x41f0e92d, 0x460e2400, 0x46252809, 0xe8dfd215, 
+    0x0705f000, 0x140c0a15, 0x0012100e, 0xe00d2409, 0x25012408, 0x2401e00a, 0x2404e008, 0x2402e006, 
+    0x2405e004, 0x2406e002, 0x2403e000, 0xb12e4f0e, 0xf00d4638, 0xf000fbf9, 0xe000000f, 0x02314620, 
+    0x1104ea41, 0x46384301, 0xf00db289, 0x462bfbf0, 0xe8bd4805, 0x220041f0, 0x30402101, 0xbc01f00d, 
+    0xe7c52100, 0xe7c32101, 0xf2030460, 0x41f0e92d, 0x2a014e19, 0x0880f44f, 0x46074614, 0xd001b24d, 
+    0xd1112c02, 0x46402170, 0xfa1df7e2, 0xf7eb4638, 0x2000fe5a, 0xfb86f7eb, 0x46292001, 0x70302200, 
+    0xfb87f7eb, 0xd0032c02, 0x2c02b13c, 0xe00fd005, 0xf44f2100, 0xf7e92080, 0x2200faaf, 0x46104629, 
+    0xfb77f7eb, 0x70302000, 0x46402171, 0xfa23f7e2, 0xe8bd2001, 0x000081f0, 0x00042e74, 0x4cf6b510, 
+    0xf00d4620, 0xf64efba1, 0x400861ee, 0x1111f241, 0x46204401, 0x4010e8bd, 0xbb99f00d, 0x4ceeb510, 
+    0xf00d4620, 0xf242fb91, 0x43012122, 0xf00d4620, 0x4620fb8e, 0xfb88f00d, 0x51ddf64d, 0x46204001, 
+    0x4010e8bd, 0xbb83f00d, 0xf241b570, 0x46050400, 0x4603220c, 0x462148e1, 0xfb93f00d, 0x220c48e0, 
+    0x4621462b, 0xfb8df00d, 0x220c48de, 0x4621462b, 0xfb87f00d, 0x4621462b, 0x4070e8bd, 0x220c48da, 
+    0xbb7ff00d, 0x47f0e92d, 0xf6404cd4, 0x220b0600, 0x46074689, 0x46314603, 0xf00d4620, 0x4dd0fb72, 
+    0x463b220b, 0x46284631, 0xfb6bf00d, 0x8334f8df, 0x463b220b, 0x46404631, 0xfb63f00d, 0x4eca4631, 
+    0x463b220b, 0xf00d4630, 0xf240fb5c, 0x464b4700, 0x4639220a, 0xf00d4620, 0x220afb54, 0x4639464b, 
+    0xf00d4628, 0x220afb4e, 0x4639464b, 0xf00d4640, 0x464bfb48, 0x46304639, 0x47f0e8bd, 0xf00d220a, 
+    0xe92dbb40, 0x4eb547f0, 0x2205461d, 0x21e0460c, 0x46034607, 0xf00d4630, 0xf8dffb34, 0x220582c4, 
+    0x463b21e0, 0xf00d4640, 0xf8dffb2c, 0x220592b8, 0x463b21e0, 0xf00d4648, 0x463bfb24, 0x22054faa, 
+    0x463821e0, 0xfb1df00d, 0xd01a2c00, 0xf04f7828, 0xf04f0304, 0xf04f0205, 0xb13801e0, 0xf00d4630, 
+    0x2304fb10, 0x22054640, 0xe00621e0, 0xf00d4648, 0x2304fb08, 0x22054638, 0xe8bd21e0, 0xf00d47f0, 
+    0xe8bdbb00, 0x220087f0, 0x48984603, 0xf00d2107, 0xb570baf8, 0xf2484d95, 0x23000400, 0x220f4621, 
+    0xf00d4628, 0x2301faee, 0x220f4621, 0xf00d4628, 0x4621fae8, 0xe8bd4628, 0x23004070, 0xf00d220f, 
+    0xb570bae0, 0x46042801, 0xd000460d, 0x4888b92c, 0x460b2204, 0xf00d2130, 0x2c02fad4, 0x2c00d001, 
+    0x4883d108, 0xe8bd462b, 0x22044070, 0x30802130, 0xbac7f00d, 0xe92dbd70, 0x0c1741f0, 0x28014615, 
+    0x4606460c, 0xb9ced000, 0xd0002c01, 0x4878b94c, 0x1d004639, 0xfa9bf00d, 0xb2a94875, 0xf00d1d80, 
+    0x2c02fa96, 0xb94cd000, 0x46394871, 0xf00d3008, 0x486ffa8e, 0x300ab2a9, 0xfa89f00d, 0xd0012e02, 
+    0xd11c2e00, 0xd0002c01, 0x4869b94c, 0x30844639, 0xfa7df00d, 0xb2a94866, 0xf00d3086, 0x2c02fa78, 
+    0x2c00d001, 0x4862d10b, 0x30884639, 0xfa6ff00d, 0x485fb2a9, 0x41f0e8bd, 0xf00d308a, 0xe8bdba68, 
+    0x4b5c81f0, 0xb5102100, 0x2801b130, 0x2802d007, 0x2803d00d, 0xe00dd109, 0x21032200, 0x2202e001, 
+    0x4618210c, 0xfa7bf00d, 0xb2c8b241, 0x2204bd10, 0xe7f62130, 0x21c02206, 0xb570e7f3, 0x46044d47, 
+    0x46281cad, 0xfa40f00d, 0xf3644e4b, 0x46010000, 0xf00d4630, 0x2c00fa3c, 0x4628d109, 0xfa34f00d, 
+    0x0102f020, 0xe8bd4630, 0xf00d4070, 0xbd70ba30, 0x4c3ab570, 0x46201ca4, 0xfa26f00d, 0xf0404d3e, 
+    0x46280102, 0xfa23f00d, 0xf00d4620, 0xf020fa1d, 0x46280102, 0x4070e8bd, 0xba19f00d, 0x4b37b57f, 
+    0x460d4614, 0xe88dcb4e, 0xf7ff004e, 0xf85dffaa, 0xb2a10020, 0x0045eb00, 0xfa09f00d, 0xb510bd7f, 
+    0x48264604, 0xf00d1c80, 0xf240f9ff, 0xea017100, 0xf4202104, 0x430860e2, 0x4010e8bd, 0x0110f040, 
+    0xf00d4825, 0xb510b9f4, 0x46042801, 0xb92cd000, 0x481f2301, 0x46192200, 0xfa03f00d, 0xd0012c02, 
+    0xd1082c00, 0x2301481a, 0x46192200, 0x4010e8bd, 0xf00d3080, 0xbd10b9f6, 0x41f0e92d, 0x461d4c15, 
+    0x4616b283, 0x460f2200, 0x46202103, 0xf9e9f00d, 0x4620b2bb, 0x210c2202, 0xf9e3f00d, 0x4620b2b3, 
+    0x21302204, 0xf9ddf00d, 0x4620b2ab, 0x41f0e8bd, 0x21c02206, 0xb9d5f00d, 0xf23c8000, 0xf2033040, 
+    0xf2033240, 0xf2033440, 0xf2033640, 0xf2033a00, 0xf2033b00, 0xf2035026, 0xf2033842, 0x0002eb0c, 
+    0xf641b570, 0x46040500, 0x480cb283, 0x4629220b, 0xf9b7f00d, 0x480ab2a3, 0x4629220b, 0xf9b1f00d, 
+    0x4808b2a3, 0x4629220b, 0xf9abf00d, 0x4629b2a3, 0x4070e8bd, 0x220b4804, 0xb9a3f00d, 0xf2033042, 
+    0xf2033242, 0xf2033442, 0xf2033642, 0x41f0e92d, 0xf7f82400, 0x4878fcd1, 0x81e0f8df, 0xc1e4f8df, 
+    0x78014f79, 0x4e794876, 0xf8d8460d, 0xf9902000, 0x2b033000, 0xf8dfd006, 0x2b05e1d8, 0x2b04d00e, 
+    0xe032d020, 0x68004873, 0xd3022812, 0x60f7f64d, 0xf64ee001, 0x434260ea, 0xe0261412, 0x28017830, 
+    0x2802d007, 0xf89cd005, 0x43204000, 0x7838d001, 0xf89eb130, 0xb1080000, 0xe0162404, 0xe0142403, 
+    0xe0122401, 0x28017830, 0x2802d007, 0xf89cd005, 0x43204000, 0x7838d001, 0xf89eb130, 0xb1080000, 
+    0xe0022406, 0xe0002405, 0xf6432402, 0x428270ff, 0x1e42db00, 0xe160f8df, 0xeb0e2000, 0xf1c01404, 
+    0xf9340e07, 0x4596e01e, 0x1c40dc03, 0x2808b200, 0x2807dbf5, 0x4a50dc05, 0x0007f1c0, 0xf8123290, 
+    0x2b045010, 0xd0064a4d, 0xd0312b05, 0xd2582d0c, 0xb3e87810, 0x7830e03a, 0xd00d2801, 0xd00b2802, 
+    0x3000f89c, 0xd0074318, 0xd20e2d0c, 0xb1707810, 0xd204290f, 0xe0112407, 0xd30c2d2d, 0x2919e00d, 
+    0x2406d201, 0x2405e00a, 0x2d41e008, 0x2402d201, 0x2d4be004, 0x2401d201, 0x2400e000, 0xb3787838, 
+    0xd2352d41, 0xe0382402, 0xe0362401, 0xe0342400, 0x28017830, 0x2802d010, 0xf89cd00e, 0x43183000, 
+    0x2d0cd00a, 0x7810d2ec, 0xd0eb2800, 0xe000290f, 0xd212e011, 0xe0242407, 0xd2012d23, 0xe01c2404, 
+    0xd2012d2d, 0xe0182403, 0xd3db2d41, 0xd2dd2d55, 0x2406e7da, 0x2405e015, 0x2919e00f, 0xe7f8d2fb, 
+    0x2d23e009, 0x2d2dd3f7, 0x2d37d3e8, 0xe7c7d3ea, 0xd2cb2d4b, 0x2c06e7c8, 0x4819da03, 0x28017800, 
+    0x2000d0e7, 0xda002c00, 0x48164604, 0xf89ff00d, 0x0000f8b8, 0x4813b281, 0xf00d3020, 0x7831f898, 
+    0xeb000320, 0x44282001, 0x480eb281, 0xf00d3026, 0x4620f88e, 0x81f0e8bd, 0x0004257c, 0x00042614, 
+    0x00040292, 0x00042556, 0x0004232e, 0x000425f9, 0x0004257a, 0x00040240, 0x00042eb4, 0x00042308, 
+    0x00042309, 0xf2035182, 0xb51048ff, 0xf9904bfd, 0x48fe2000, 0x20007801, 0xfd43f7ff, 0x4010e8bd, 
+    0xf7ec2004, 0xb57cbc4a, 0xf7ee2001, 0x4cf8fff2, 0x4bf92204, 0x48f7b241, 0x70212903, 0x2905d002, 
+    0xe022d014, 0x29948819, 0x2984d00c, 0x29a4d00a, 0x29b4d008, 0x2998d006, 0x29a8d011, 0x2988d00f, 
+    0xe00ad00d, 0x70212105, 0xe00a2307, 0x29988819, 0x2988d005, 0x29a8d003, 0x29b8d001, 0x2306d105, 
+    0x22027022, 0xf00d213c, 0x7820f84c, 0xff14f7e8, 0x700849e2, 0xf7ed2008, 0x7820feee, 0xfaa8f7ec, 
+    0xf7ec2005, 0x2000fe85, 0xf8b8f7ed, 0x250049dc, 0x23019500, 0x461a7820, 0xf7e47809, 0x2101ff0b, 
+    0xf7ec4608, 0xf640fb1b, 0xf6474100, 0x23177203, 0x00889500, 0xfac6f7ec, 0x210248d2, 0xf807f00d, 
+    0xf64048d1, 0xf00d7131, 0x2001f802, 0x46022300, 0x0500e9cd, 0xf7ea4619, 0x49ccf83f, 0x60082019, 
+    0xe92dbd7c, 0x4fca5ffc, 0x8e804606, 0xb324f8df, 0x8324f8df, 0x683b28e2, 0xdc05d075, 0x289ab170, 
+    0x289bd018, 0xe020d170, 0xd00628e3, 0x7f90f5b0, 0xf5a0d06b, 0x38217080, 0xe1abd166, 0xf04f49bd, 
+    0xf8db32ff, 0x1d090000, 0xfdf4f007, 0xd1081d01, 0xe0aa209a, 0x220049b7, 0x0000f8db, 0xf0071d09, 
+    0x1d41fde9, 0x2801d02d, 0x48b2d1e8, 0xf9b01d00, 0x296e1000, 0xf04fd1e2, 0x46815580, 0x4220f04f, 
+    0xf7e14628, 0xf898fe4e, 0xf04f1000, 0x46445290, 0xf7e14628, 0x7820fe46, 0xd0772800, 0xf04f2500, 
+    0x24010a05, 0xd00e2801, 0xd0462802, 0xd0492803, 0xd07d2804, 0xd06b2805, 0xd06a2806, 0xd0692807, 
+    0x209be16f, 0xf7fce071, 0xf7fffae2, 0xf7ffff2c, 0x4895ff1b, 0x220f2300, 0x0100f248, 0xf00c301a, 
+    0x2201ffa0, 0x46112300, 0x4500e9cd, 0xf7e94610, 0x4892ffc3, 0xff78f00c, 0x80084991, 0x48910701, 
+    0x8004d004, 0xe00ee003, 0xe044e050, 0x22008005, 0xf8a94988, 0x6838a000, 0xf0071d09, 0x1d01fd5c, 
+    0x20e2d107, 0x4983e041, 0x46182200, 0xf0071d09, 0x1d40fd52, 0x20e3d175, 0xf7ffe037, 0xf7fffef4, 
+    0xe11bfee3, 0xfeeff7ff, 0x23004d7f, 0xf640220b, 0x46280100, 0xff65f00c, 0x46282301, 0x0319220c, 
+    0xff5ff00c, 0xf6404870, 0xf00c1137, 0x4877ff40, 0x49702200, 0x70041d09, 0xa000f8a9, 0xf0076838, 
+    0x1d01fd2a, 0xf240d10d, 0xe00e1020, 0xe00fe100, 0xe0eae06b, 0x4967e0fb, 0x46182200, 0xf0071d09, 
+    0x1d40fd1a, 0xf240d1c6, 0x86b01021, 0x9ffce8bd, 0xfeb9f7ff, 0xfea8f7ff, 0xf9904855, 0x28050000, 
+    0x2804d030, 0x2000d030, 0x78094961, 0xd02d2901, 0xd0312902, 0xd0352904, 0xd0392905, 0xd03d2906, 
+    0x462c2500, 0xfc25f7ff, 0x4b464847, 0x2000f990, 0x78014846, 0xf7ff2003, 0x2004fbd4, 0xfc13f7ff, 
+    0x46082100, 0xfc2df7ff, 0x462a2101, 0xf7ff2000, 0x2102fc42, 0x20004622, 0xfc3df7ff, 0xf7ff2000, 
+    0xe0b7fcf2, 0xe7cf2001, 0xe7cd2002, 0x7580f241, 0x2480f641, 0xe01640c5, 0x2580f243, 0x3480f243, 
+    0xe01040c5, 0x1580f645, 0x2480f645, 0xe00a40c5, 0x2580f648, 0x4480f648, 0xe00440c5, 0x6580f24c, 
+    0x0480f64c, 0x40c440c5, 0xf7ffe7bc, 0xf7fffe5c, 0xf7fffe4b, 0x2100fc8d, 0x46082240, 0xfc9ef7ff, 
+    0x2101220d, 0xf7ff2000, 0x2205fc99, 0x20002102, 0xfc94f7ff, 0x21002240, 0xf7ff2001, 0x2101fc8f, 
+    0x4608220d, 0xfc8af7ff, 0x21022205, 0xf7ff2001, 0x2240fc85, 0x20022100, 0xfc80f7ff, 0x2101220d, 
+    0xf7ff2002, 0x2102fc7b, 0x46082205, 0xfc76f7ff, 0x21002240, 0xf7ff2003, 0x220dfc71, 0x20032101, 
+    0xfc6cf7ff, 0x21022205, 0xf7ff2003, 0x2000fc67, 0xfc33f7ff, 0xf7ff2003, 0x2301fc72, 0x46192200, 
+    0xe0274618, 0x00042598, 0x0004023c, 0x0004232e, 0x00040292, 0xf2020000, 0x00042576, 0x00040293, 
+    0x000425f9, 0xf23c8304, 0xf203502a, 0x00040240, 0x0004274c, 0x00042f54, 0x00040284, 0xf2035136, 
+    0x000402c6, 0x000402c8, 0xf38fffd2, 0x00040298, 0x000425a0, 0x5400e9cd, 0xfe8ef7e9, 0x22002301, 
+    0x21024618, 0x5400e9cd, 0xf7ffe00e, 0xf7fffddc, 0x4837fdcb, 0x7131f640, 0xfe39f00c, 0x22012300, 
+    0xe9cd4618, 0x46114500, 0xfe76f7e9, 0x2001e002, 0xff05f7e9, 0x0000f898, 0xf43f2807, 0x2800ae4f, 
+    0xf7ffd0fb, 0xe649fa8b, 0x21012200, 0xf2afb510, 0xf00730ad, 0x2108fa5b, 0xf0072002, 0x4925fbb9, 
+    0xbd106008, 0x2000b57c, 0xf962f7e9, 0x20062100, 0xf85cf7fe, 0x24004820, 0x46219400, 0x481f7802, 
+    0x46207803, 0xff98f7fd, 0xf7ee2004, 0x481dfaea, 0xf9904b1b, 0x481c2000, 0x20007801, 0xfad1f7ff, 
+    0xf7e92000, 0x2001fe31, 0x46022300, 0x0400e9cd, 0x46184601, 0xfe30f7e9, 0x21004814, 0xfde7f00c, 
+    0xf2414c13, 0x78210000, 0xfcd6f7e8, 0x0550f242, 0x06ee4629, 0xf7e14630, 0x7821fc32, 0xf7e80bf0, 
+    0x4629fccb, 0xe8bd4630, 0xf7e1407c, 0x0000bc28, 0xf203502a, 0x00042f54, 0x00040292, 0x000425f9, 
+    0x00042598, 0x0004023c, 0x0004232e, 0xf2034220, 0x00040293, 0x43f8e92d, 0x48ff4606, 0x600149fd, 
+    0xf00c48fe, 0x2000fdae, 0xf902f7e9, 0xfc06f7e7, 0xf24048fb, 0x78012400, 0xf7e74620, 0x48f9fc09, 
+    0x71fff64f, 0xfd9df00c, 0x20022100, 0xfc2cf7e8, 0x230048f5, 0x21022201, 0xfdb3f00c, 0x83ccf8df, 
+    0x22092300, 0x46404621, 0xfdabf00c, 0x230148ef, 0x03d9220f, 0xf00c3012, 0x4fe7fda4, 0x1d3f2500, 
+    0xb2e12400, 0x0014f837, 0xb2024240, 0xf7ffb2e8, 0x1c64fb65, 0xdbf42c10, 0x2d041c6d, 0x2000dbf0, 
+    0xfb2bf7ff, 0xf7ff2003, 0x48e0fb6a, 0x21012300, 0x30a0461a, 0xfd85f00c, 0x46082100, 0xfd80f7e9, 
+    0x680048db, 0x1ec07f80, 0xf7ebb2c0, 0x2300fe0b, 0x22074640, 0xf00c2180, 0x2300fd74, 0x210148d5, 
+    0xf00c461a, 0x2000fd6e, 0x48d39000, 0x21002203, 0x20087803, 0xfee0f7fd, 0x23004dd0, 0x21e02205, 
+    0xf00c4628, 0x4ccefd5e, 0x22052300, 0x462021e0, 0xfd57f00c, 0x832cf8df, 0x22052300, 0x464021e0, 
+    0xfd4ff00c, 0x9320f8df, 0x22052300, 0x464821e0, 0xfd47f00c, 0xf7e92001, 0x2100fd67, 0x2080f44f, 
+    0xfc1af7e8, 0x20012100, 0xff80f7fa, 0xf2402202, 0x210710c3, 0xf93af7ff, 0xf7ea48bc, 0x2000fd34, 
+    0xf92ef7ff, 0x23022100, 0x22084608, 0xf8cff7e9, 0x2100230c, 0x4608461a, 0xf904f7e9, 0x461a2300, 
+    0x46184619, 0xf8e5f7e9, 0x20002101, 0xf8adf7e9, 0x22112300, 0x3100f44f, 0x4071f04f, 0xfcfaf00c, 
+    0xf7e92001, 0xf44ff845, 0x21001700, 0xf7e84638, 0x230cfbe3, 0x461a2100, 0xf7e94608, 0x2100f8e3, 
+    0xf7e84638, 0x230dfbd9, 0x461a2100, 0xf7e94608, 0x2100f8d9, 0xf7e84638, 0x04f0fbcf, 0x10c02205, 
+    0x0f4321e0, 0xf00c4628, 0x04b0fcec, 0x10c02205, 0x0f4321e0, 0xf00c4620, 0x0470fce4, 0x10c02205, 
+    0x0f4321e0, 0xf00c4640, 0x0430fcdc, 0x10c02205, 0x0f4321e0, 0xf00c4648, 0xe8bdfcd4, 0x200243f8, 
+    0xbb53f7e8, 0x47f0e92d, 0x4605b088, 0xae042000, 0xf8464601, 0x1c401020, 0xdbfa2804, 0x91ecf8df, 
+    0xf8df2400, 0xf248a1e8, 0xf1090800, 0x466f0918, 0x0a06f10a, 0x21004640, 0xfb8ef7e8, 0x466b2101, 
+    0x4650464a, 0xfbcdf00d, 0xf8562000, 0xf8571020, 0x44112020, 0x1020f846, 0x28041c40, 0x1c64dbf5, 
+    0xdbe72c40, 0xf8562000, 0x31201020, 0xf8451189, 0x1c401020, 0xdbf62804, 0xf105b008, 0xe8bd0010, 
+    0x460387f0, 0xb5102000, 0xe005188c, 0x2011f833, 0xfb121c49, 0x4410f202, 0xdcf7428c, 0xe92dbd10, 
+    0xf04f4ff8, 0x46044571, 0xf00c4628, 0x2300fc57, 0x21014683, 0x4628461a, 0xfc5cf00c, 0x465046aa, 
+    0xfc4cf00c, 0xd1fa07c0, 0x25004859, 0xf8d046a9, 0x22008000, 0x4610b269, 0x460e4643, 0x9000f8cd, 
+    0xf994f7e7, 0x46be2700, 0x463a46bc, 0x0012f938, 0xdb012800, 0xe0004603, 0xb2194243, 0xdd0242b9, 
+    0x4686460f, 0x1c524694, 0x2a80b212, 0x2280dbee, 0x21004640, 0xec00e9c4, 0xffb3f7ff, 0x60a02280, 
+    0x46404611, 0xffadf7ff, 0x60e02280, 0x00514640, 0xffa7f7ff, 0xf2402280, 0x61201180, 0xf7ff4640, 
+    0x2280ffa0, 0x46406160, 0xf7ff0091, 0x2280ff9a, 0x2180f240, 0x464061a0, 0xff93f7ff, 0xf2402280, 
+    0x61e03100, 0xf7ff4640, 0x2280ff8c, 0x3180f240, 0x46406220, 0xff85f7ff, 0x62602701, 0x46433428, 
+    0x46312000, 0xf8cdb27a, 0xf7e79000, 0x2280f93f, 0x21004640, 0xff75f7ff, 0x60202280, 0x46404611, 
+    0xff6ff7ff, 0x60601c7f, 0x3408b23f, 0xdbe62f04, 0xb22d1c6d, 0xdb8c2d04, 0x46504659, 0xfbd1f00c, 
+    0xe8bd4620, 0xe92d8ff8, 0xf5ad4ff0, 0xf7ff7d0b, 0x2000fe11, 0x4601ad40, 0x1020f845, 0x28401c40, 
+    0x2000dbfa, 0x417ff06f, 0x4690aa86, 0x1020f842, 0xe01f1c40, 0x00040300, 0x00042f60, 0xf0003088, 
+    0x0004232e, 0xf1000048, 0xf23c8310, 0xf2030400, 0x00042618, 0xf2031012, 0x000425f9, 0xf2033040, 
+    0xf2033240, 0xf2033440, 0xf2033640, 0x000425b0, 0x00040238, 0xdbd82804, 0x46eb2400, 0x7a00f50d, 
+    0x4700f240, 0xf1c72600, 0x2c000900, 0x4649d064, 0xf7edb270, 0x1c76fff1, 0xdbf62e04, 0xf44f2100, 
+    0xf7e80000, 0x4668fa79, 0xff19f7ff, 0xf7ffa880, 0x2000fec9, 0x010146dc, 0x0681eb0c, 0x0281eb05, 
+    0x689768b3, 0xdd0642bb, 0x7021f85c, 0x7021f845, 0xe9c26876, 0x22036301, 0xf85c188e, 0xf8553026, 
+    0x42bb7026, 0xf845dd01, 0x1c523026, 0xddf32a0f, 0x3020f858, 0xf85a4642, 0x428b1020, 0xf842dd01, 
+    0x1c401020, 0xdbd62804, 0x2c021c64, 0x48fedbb8, 0x20006804, 0x1020f852, 0x28041c40, 0xdbf9c402, 
+    0xf7eaa884, 0x2000fb60, 0xf931a984, 0x1c402010, 0xc4042804, 0x2000dbf9, 0x1020f855, 0x1020f844, 
+    0x28401c40, 0x2100dbf8, 0x1080f44f, 0xfa24f7e8, 0x7d0bf50d, 0x8ff0e8bd, 0xe7994639, 0x4604b510, 
+    0x46022000, 0xf934e007, 0x2b003012, 0x1ac0da01, 0x4418e000, 0x428a1c52, 0xbd10dbf5, 0x2300b5ff, 
+    0x461c466d, 0x4023f845, 0x2b041c5b, 0x2300dbfa, 0xf930e016, 0x9c006013, 0x94004434, 0x0443eb00, 
+    0x1d1b9e01, 0x7002f9b4, 0x9601443e, 0x7004f9b4, 0x443e9e02, 0xf9b49602, 0x9e034006, 0x94034434, 
+    0xdbe6428b, 0x1e92108b, 0x2100b214, 0x2021f855, 0x0263eb02, 0xf8454122, 0x1c492021, 0xdbf52904, 
+    0xe0142100, 0x2011f830, 0x1b129c00, 0x2011f820, 0x0241eb00, 0x88549d01, 0x80541b64, 0x9d028894, 
+    0x80941b64, 0x9d0388d4, 0x80d41b64, 0x42991d09, 0xbdffdbe8, 0x4ff0e92d, 0xf7ffb093, 0x200afd0b, 
+    0x23009004, 0x48ba4db9, 0xf2402101, 0x461a4400, 0xfac0f00c, 0x21012300, 0xf04f461a, 0xf00c4071, 
+    0x2000fab9, 0xfeccf7fe, 0x20002140, 0xfe4af7e8, 0xf04f48ad, 0x6807090d, 0x46802000, 0x90129009, 
+    0x4aae49ac, 0x808880c8, 0x80088048, 0x49ac48aa, 0x48a87803, 0xfad6f7ea, 0x1680f44f, 0x46302100, 
+    0xf98af7e8, 0x23042101, 0x22004608, 0xfccdf7ec, 0x46302100, 0xf980f7e8, 0xf04f12b1, 0x94000b01, 
+    0x1e5a2300, 0xe9cd4628, 0x2103b101, 0xb00cf8cd, 0xfeb0f7fd, 0xf10d2600, 0x9a040a38, 0xf004fb06, 
+    0xeb054621, 0x46840040, 0xff58f7ff, 0x46214660, 0xff44f7ff, 0x0026f84a, 0x2e041c76, 0xf240dbed, 
+    0x94004100, 0x46282300, 0xe9cd1e5a, 0x2103b101, 0xb00cf8cd, 0xfe8ef7fd, 0x9a042600, 0xfb064621, 
+    0xeb05f004, 0x46840040, 0xff38f7ff, 0x46214660, 0xff24f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 
+    0xdbea2e04, 0x4100f240, 0x23009400, 0x1e5a4628, 0xb101e9cd, 0xf8cd2103, 0xf7fdb00c, 0x2600fe6b, 
+    0x46219a04, 0xf004fb06, 0x0040eb05, 0xf7ff4684, 0x4660ff15, 0xf7ff4621, 0xf85aff01, 0x18812026, 
+    0x1026f84a, 0x2e041c76, 0x2001dbea, 0x1e829400, 0x23000281, 0x0101e9cd, 0x90032103, 0xf7fd4628, 
+    0x2600fe49, 0x46219a04, 0xf004fb06, 0x0040eb05, 0xf7ff4684, 0x4660fef3, 0xf7ff4621, 0xf85afedf, 
+    0x46d32026, 0xf84a1881, 0x1c761026, 0xdbe92e04, 0x23042201, 0x46104611, 0xfc37f7ec, 0xf44f2100, 
+    0xf7e81080, 0x4953f8e9, 0x4a544853, 0x9006f8a1, 0x9004f8a1, 0x9002f8a1, 0x9000f8a1, 0x49507803, 
+    0xf7ea484c, 0x2101fa1f, 0x46082302, 0xf7e82208, 0x220bfd9e, 0x0600f242, 0x46304611, 0xfeaef7e8, 
+    0x4630220c, 0xf7e84611, 0x220dfea9, 0x46114630, 0xfea4f7e8, 0x94002001, 0x02811e82, 0xe9cd2300, 
+    0x21030101, 0x46289003, 0xfdf4f7fd, 0xf10d2600, 0x9a040a28, 0xf004fb06, 0xeb054621, 0x46840040, 
+    0xfe9cf7ff, 0x46214660, 0xfe88f7ff, 0x0026f84a, 0x2e041c76, 0x2001dbed, 0x1e829400, 0x23000281, 
+    0x0101e9cd, 0x90032103, 0xf7fd4628, 0x2600fdd3, 0x46219a04, 0xf004fb06, 0x0040eb05, 0xf7ff4684, 
+    0x4660fe7d, 0xf7ff4621, 0xf85afe69, 0x18812026, 0x1026f84a, 0x2e041c76, 0x2001dbea, 0x1e829400, 
+    0x23000281, 0x0101e9cd, 0x90032103, 0xf7fd4628, 0x2600fdb1, 0x46219a04, 0xf004fb06, 0x0040eb05, 
+    0xf7ff4684, 0x4660fe5b, 0xf7ff4621, 0xf85afe47, 0x18812026, 0x1026f84a, 0x2e041c76, 0x2001dbea, 
+    0x1e829400, 0x23000281, 0x0101e9cd, 0x90032103, 0xf7fd4628, 0x2600fd8f, 0x46219a04, 0xf004fb06, 
+    0x0040eb05, 0xe00d4684, 0x00042f60, 0x00043a00, 0xf1000030, 0x000425b0, 0x0004232e, 0x00042598, 
+    0x000425c6, 0xfe2af7ff, 0x46214660, 0xfe16f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 0xdbdb2e04, 
+    0xf7ffa805, 0x2000fc7f, 0xab054651, 0xf852465a, 0x603e6020, 0x6020f851, 0xf853607e, 0x1c406020, 
+    0x370c60be, 0xdbf22804, 0x21402600, 0xf7edb270, 0x1c76fd83, 0xdbf82e04, 0x0801f108, 0x0f40f1b8, 
+    0x9812da01, 0x2100e66c, 0x1080f44f, 0xf804f7e8, 0xea409809, 0xea412100, 0xea414100, 0x60386000, 
+    0x2109ea49, 0x4109ea41, 0x6009ea41, 0xb0136078, 0xe92de5d0, 0x250041f0, 0x4700f240, 0x21004efe, 
+    0xf7e74638, 0x4630ffe9, 0xf8eef00c, 0x0720b204, 0x48f9d0f5, 0x1c80b2a1, 0xf8e9f00c, 0x000ff004, 
+    0xd00f2801, 0xd0112802, 0xd0132803, 0xf64f2501, 0xea0470f0, 0x46300100, 0xf8d9f00c, 0xd0de2d00, 
+    0x81f0e8bd, 0xf7ff4620, 0xe7f0fe05, 0xf7ff4620, 0xe7ecfcfa, 0xf7ff4620, 0xe7e8fb0d, 0x4ff8e92d, 
+    0xf64f48e6, 0xf8df71ff, 0x6800b398, 0x08478800, 0xf00c4658, 0x2100f8b6, 0xf7e72002, 0xf7f0ff45, 
+    0x4ee0f827, 0x94002400, 0x21012203, 0x7833200a, 0xfa42f7fd, 0xf814f7f0, 0x20012100, 0xfb06f7fa, 
+    0xfee9f7f6, 0x20012100, 0xfb00f7fa, 0x210048d6, 0x68052201, 0x94004608, 0xf7e6462b, 0x2100fde7, 
+    0x4628463a, 0xfc1df7ff, 0x46802201, 0x462b2000, 0x94004611, 0xfddaf7e6, 0x463a2100, 0xf7ff4628, 
+    0x2203fc10, 0x21024682, 0x2000462b, 0xf7e69400, 0x2100fdcd, 0x4628463a, 0xfc03f7ff, 0x46812203, 
+    0x462b2000, 0x94004611, 0xfdc0f7e6, 0x463a2100, 0xf7ff4628, 0x4cbdfbf6, 0x0200f242, 0xda054590, 
+    0xda034592, 0xda014591, 0xdb014290, 0xe0004db8, 0x46584db8, 0xf00c4629, 0x2000f854, 0xf7e86025, 
+    0xf7e6fba7, 0xf7effeab, 0x4dabfe90, 0x35742400, 0xb2241c64, 0xff08f7ee, 0xfb22f7f7, 0xff30f7fc, 
+    0xf249b110, 0xe003010d, 0xddf12c05, 0x31adf640, 0xf00c4628, 0x2100f83c, 0xf7fa2001, 0xf7f2fa97, 
+    0xf7f2fb5c, 0xf7f2f9ea, 0xf7f2f951, 0xf7f2fa08, 0x2000f8ab, 0xfb7cf7e8, 0xf7fc2000, 0x499efc2f, 
+    0xf7e6b240, 0x2001fe26, 0xfc28f7fc, 0xb240499a, 0xf7e63120, 0x2002fe1e, 0xfc20f7fc, 0xb2404996, 
+    0xf7e63140, 0x2003fe16, 0xfc18f7fc, 0xb2404992, 0xf7e63160, 0xf8dffe0e, 0x25008240, 0xeb082400, 
+    0x46211745, 0x0014f837, 0xb2024240, 0xf7fe4628, 0x1c64fde5, 0x2c10b2e4, 0x1c6dd3f3, 0x2d04b2ed, 
+    0x2000d3ec, 0xfda9f7fe, 0xf7fe2003, 0x2300fde8, 0x21014882, 0xf00c461a, 0x2100f804, 0xf7e84608, 
+    0x4c7fffff, 0x0500f241, 0x78214628, 0xfed4f7e7, 0x20012100, 0xfa3af7fa, 0xf7fe2004, 0x7821fbf1, 
+    0xf7e74628, 0x2001fec9, 0xfb22f7e8, 0x01e87821, 0xfec2f7e7, 0xf7e82000, 0x2002fb1b, 0xf804f7e9, 
+    0x23004d70, 0x210c2202, 0xf00b4628, 0x7830ffda, 0x2801b120, 0x2802d004, 0xe004d002, 0xe0002005, 
+    0xf7fe2006, 0x2301fbcf, 0x220a4628, 0x4639029f, 0xffc7f00b, 0x46387821, 0xfe9ef7e7, 0xf7e82001, 
+    0x4855faf7, 0x38160179, 0xffa1f00b, 0x2300485e, 0x78002101, 0x20089000, 0xf7ed7832, 0x2300f935, 
+    0x2101485a, 0xf00b461a, 0xf7edffac, 0x4c58f984, 0x78212001, 0xf92df7e9, 0x78204956, 0xf7e97008, 
+    0x2004fcf6, 0xfbc9f7f9, 0x4ff8e8bd, 0x20012100, 0xb9dcf7fa, 0x4ff8e92d, 0x20022100, 0xfe04f7e7, 
+    0x23014846, 0x02592209, 0xf00b38a0, 0x2000ff8a, 0xfabef7e8, 0xfdc2f7e6, 0xf2484840, 0x23010a00, 
+    0x220f4651, 0xf00b388e, 0x2001ff7c, 0xff9cf7e8, 0x2100483a, 0xf00b3840, 0x4838ff5a, 0x22072301, 
+    0x38a02180, 0xff6df00b, 0xf2404c35, 0x46284500, 0xf7e77821, 0x4e33fe41, 0x220f2301, 0x03d93672, 
+    0xf00b4630, 0x2380ff5e, 0x22004630, 0xf00b1e69, 0x2306ff58, 0x21ff2200, 0xf00b1cb0, 0xf8dfff52, 
+    0x2200807c, 0xf8d8217f, 0xf8b00000, 0x1d30304a, 0xff47f00b, 0x0b02f1a6, 0x465e0169, 0xf00b4658, 
+    0xf248ff26, 0x46300180, 0xff21f00b, 0x46287821, 0xfe12f7e7, 0x0900f44f, 0x11f4f240, 0x4648464f, 
+    0xfd61f7e0, 0x4638491c, 0xfd4cf7e0, 0xf00b4815, 0x4601ff0b, 0xf7e04638, 0x4812fd45, 0xf00b3080, 
+    0x4601ff03, 0xf7e04638, 0x4914fd3d, 0xf7e04638, 0x480cfd39, 0xe0233080, 0xf2035136, 0x00042618, 
+    0xf1000048, 0x000425f9, 0x00040238, 0x00042304, 0x8421b7ed, 0x84217bde, 0x00043350, 0xf20304a0, 
+    0x00040293, 0xf2035022, 0x0004232e, 0xf2036104, 0x00040292, 0x0004024c, 0x90010000, 0xdcba01f5, 
+    0xfed2f00b, 0x48ab4601, 0xfed1f00b, 0x46292300, 0x4630220a, 0xfee5f00b, 0x46292301, 0x4630220a, 
+    0xfedff00b, 0x46292300, 0x4630220a, 0xfed9f00b, 0x220d48a1, 0x0100f246, 0x0000f990, 0x4630b283, 
+    0xfecff00b, 0x46302300, 0x21202205, 0xfec9f00b, 0x46302301, 0x21202205, 0xfec3f00b, 0x46572600, 
+    0x220f4894, 0x38e64639, 0xfec9f00b, 0x1c76b918, 0x42beb236, 0xf7fcdbf4, 0x4682fb17, 0x11f4f240, 
+    0x4648464e, 0xfcdff7e0, 0x4630498c, 0xfccaf7e0, 0x38e64888, 0xfe88f00b, 0x46304601, 0xfcc2f7e0, 
+    0x46304651, 0xfcbef7e0, 0x46304985, 0xfcbaf7e0, 0x0000f8d8, 0x8f412201, 0x44088f80, 0x2100b200, 
+    0xff31f7e8, 0xf7ea2074, 0x2301f906, 0x220f4639, 0xf00b4658, 0x4e7bfe86, 0x220b2300, 0x0100f640, 
+    0xf00b4630, 0x2300fe7e, 0x220a4629, 0xf00b4630, 0x2300fe78, 0x2100f240, 0x46302209, 0xfe71f00b, 
+    0x46302208, 0x01512300, 0xfe6bf00b, 0x46302303, 0x21c02206, 0xfe65f00b, 0xf647486a, 0x23007600, 
+    0x22084631, 0xf00b1c80, 0xf8dffe5c, 0x23008198, 0x461a217f, 0x0804f108, 0xf00b4640, 0x2300fe52, 
+    0x22084631, 0xf00b4640, 0x2002fe4c, 0xfe6cf7e8, 0x46082100, 0xfe32f7e8, 0x78304e5b, 0x2801b120, 
+    0x2802d004, 0xe004d002, 0xe0002005, 0xf7fe2006, 0x4854fa39, 0x220a2301, 0x30084629, 0xfe31f00b, 
+    0x46287821, 0xfd08f7e7, 0x4639484a, 0xf00b388a, 0x484efe0e, 0x21012300, 0x90007800, 0x78322008, 
+    0xffa2f7ec, 0x484a2300, 0x461a2101, 0xfe19f00b, 0x46287821, 0xfcf0f7e7, 0xffedf7ec, 0x20014c45, 
+    0xf7e87821, 0x4944ff96, 0x70087820, 0xfb5ff7e9, 0xe8bd4638, 0x21024ff8, 0x4210f04f, 0xbc81f7e0, 
+    0x4604b570, 0xfea4f7e1, 0xf7e82000, 0x4d35fe1d, 0x220a2300, 0x4100f240, 0x46283508, 0xfdf1f00b, 
+    0x20012100, 0xfddaf7e8, 0x20012100, 0xfde8f7e8, 0x46282301, 0x21402206, 0xfde3f00b, 0x46282301, 
+    0x21202205, 0xfdddf00b, 0x2019492c, 0x60084a22, 0x492b2000, 0x3000f991, 0xf99154d0, 0x20013001, 
+    0xf99154d0, 0x20023002, 0xf99154d0, 0x20031003, 0xf7fc5450, 0x2000fc06, 0xfdcaf008, 0x22012300, 
+    0xb2e04619, 0xfa1cf008, 0x46112200, 0xf008b2e0, 0x481cfc4f, 0x780006ea, 0x010ff000, 0x29011250, 
+    0x2902d004, 0x2903d008, 0xe00dd00c, 0xf7e02116, 0xf7fffc28, 0xe007fe0f, 0xf7e02117, 0xf7fffc22, 
+    0xe001fcbd, 0xfc85f7ff, 0x4070e8bd, 0xf7e72002, 0x0000bc1c, 0xf20351aa, 0x00042590, 0x90010001, 
+    0xdcba01f5, 0xf203501a, 0x000425f9, 0x0004232e, 0xf2036104, 0x00040292, 0x0004024c, 0x00040240, 
+    0x00042598, 0x00042301, 0x4ff8e92d, 0x46054c6b, 0xb1208e80, 0xd00d2880, 0xd1362881, 0x4967e014, 
+    0x32fff04f, 0x31086860, 0xfb74f006, 0xd1071d01, 0xe0292080, 0x22004961, 0x31086860, 0xfb6af006, 
+    0xd0201d41, 0xd1ea2801, 0x3008485c, 0x28298800, 0x485bd1e5, 0x21042202, 0xfd61f00b, 0x27004b59, 
+    0x8164f8df, 0x4e59b2c0, 0xf04f2801, 0xf64059a8, 0xf44f0100, 0xd00a0a00, 0x4618220b, 0xf00b7067, 
+    0xb3d8fd4e, 0x2081e061, 0xe8bd86a8, 0x220b8ff8, 0xf00b4618, 0x2801fd44, 0xf996d114, 0x28030000, 
+    0x2805d007, 0x2804d005, 0xf898d003, 0x28010000, 0x464ad108, 0x1160f240, 0xf7e04650, 0x2000fba2, 
+    0xfe93f7e8, 0xbbe87860, 0x22014841, 0xf00b211e, 0xb2c0fd26, 0xd0122806, 0xd0102804, 0xd0102807, 
+    0xd00e2805, 0xd0042802, 0xd0022801, 0xd0002803, 0xf0002000, 0x2001f8a9, 0xe0267060, 0x2004e003, 
+    0x2005e7f7, 0xf996e7f5, 0x28030000, 0x2805d007, 0x2804d005, 0xf898d003, 0x28010000, 0x464ad115, 
+    0x1161f240, 0xf7e04650, 0x482afb6c, 0xb9107800, 0xf7e82001, 0x2200fe5a, 0x0300f641, 0x46104611, 
+    0xe0009700, 0xf7eae001, 0xf7e1ff7d, 0x4822fd91, 0x21042202, 0xfce3f00b, 0x481d4603, 0x21022201, 
+    0xf00b3808, 0xf996fcce, 0x28030000, 0x2805d003, 0x2804d001, 0xf001d101, 0x4818fba7, 0xb1587800, 
+    0x1c407820, 0x7020b2c0, 0xf47f280a, 0x2000af48, 0xf900f7e1, 0xe7427027, 0xf7e12001, 0xe73ef8fb, 
+    0x21012200, 0xf2afb510, 0xf006109f, 0x2108f8cf, 0xf0062003, 0x4901fa2d, 0xbd106048, 0x00042f84, 
+    0xf3074084, 0xf2035026, 0x00040285, 0x0004024c, 0xf23c8022, 0x00042574, 0xf2039026, 0x000402f1, 
+    0xd0052803, 0xd0052805, 0xd1002804, 0x47702002, 0x47702005, 0x47702004, 0x4605b570, 0x880048fb, 
+    0xd1202801, 0x23014cfa, 0x21042202, 0xf00b4620, 0x2203fc61, 0x2108462b, 0xf00b4620, 0x2200fc5b, 
+    0x2101462b, 0xf00b4620, 0x2201fc55, 0x2102462b, 0xf00b4620, 0x4620fc4f, 0x4070e8bd, 0x22022300, 
+    0xf00b2104, 0xbd70bc47, 0x5ff0e92d, 0xb3a4f8df, 0xf8df2400, 0x4626839c, 0x939cf8df, 0x0702f10b, 
+    0x0874f1a8, 0xf6414625, 0xb1706a00, 0x1000f899, 0xd1752901, 0xd0342803, 0xd0342805, 0xd0342804, 
+    0xd0352802, 0xd0352801, 0x48dce035, 0x22042301, 0xf00b2110, 0x2300fc36, 0x22094651, 0xf00b4658, 
+    0xf899fc30, 0xb9680000, 0xf2422300, 0x220d0100, 0xf00b4638, 0x2300fc26, 0x0100f241, 0x4638220c, 
+    0xfc1ff00b, 0x46442300, 0x46402202, 0xf00b2104, 0x4620fc01, 0x5ff0e8bd, 0x21032300, 0xf00b461a, 
+    0x2404bbf9, 0x2403e002, 0x2402e000, 0xe0022501, 0xe0002401, 0x48c22601, 0xf24c220e, 0xf00b0100, 
+    0x2801fc0e, 0xf044d101, 0x46510408, 0x46232209, 0xf00b4658, 0x2301fbf6, 0x220d4638, 0xf00b0359, 
+    0x2301fbf0, 0x220c4638, 0xf00b0319, 0x2202fbea, 0x21044633, 0x46404644, 0xfbccf00b, 0x462b2200, 
+    0x46202103, 0xfbc6f00b, 0x780048ae, 0xd1072800, 0x5ff0e8bd, 0x48a92300, 0x21102204, 0xbbd1f00b, 
+    0x9ff0e8bd, 0x4ff8e92d, 0x929cf8df, 0x8e804604, 0xf8d92887, 0xd0213004, 0xb190dc0c, 0xd17d2886, 
+    0x220049a2, 0xf0064618, 0x1d41f9c5, 0x2801d014, 0xe013d107, 0x7fb8f5b0, 0xf5a0d071, 0x38717080, 
+    0x499ad16c, 0x32fff04f, 0x0004f8d9, 0xf9b2f006, 0xd1ea1d01, 0xe1162086, 0xe1142087, 0xf04f4e93, 
+    0x17d54220, 0xf9b64628, 0xf7e01000, 0xf996fa1a, 0x46281004, 0xf7e04a8e, 0xf9b6fa14, 0xf8df0000, 
+    0x4a8db234, 0xd0222826, 0xd1da2873, 0x0002f996, 0xf9994649, 0x42983000, 0x4b88d106, 0x5001f991, 
+    0x3000f993, 0xd0cc42ab, 0xf9967008, 0xf8890003, 0xf89b0001, 0xb1111000, 0xfee2f7ff, 0xf99670f0, 
+    0xf9961003, 0x78120002, 0xfd31f008, 0x7810e7b9, 0xf0084690, 0x2000fba9, 0xfedef7ff, 0x4f704878, 
+    0x28018800, 0xf898d023, 0x46450000, 0xfb60f008, 0xf24c46ba, 0x23000100, 0x220e4650, 0xfb51f00b, 
+    0xf6402300, 0x22087100, 0xf00b4638, 0xf996fb4a, 0x29001003, 0xf04fdd95, 0xe0014260, 0xe0a8e0b4, 
+    0xf7e01750, 0x78f0f9be, 0xd06e2805, 0x4865e0e9, 0xfb1af00b, 0x46052301, 0xf6402208, 0x46ba7100, 
+    0xf00b4638, 0xf005fb2e, 0x2f010707, 0x2f02d01a, 0x2503d01b, 0x4650462b, 0x211e2201, 0xfb21f00b, 
+    0x2203484f, 0x463b2138, 0xf00b301e, 0x4856fb1a, 0x21042202, 0xfb23f00b, 0x28014f54, 0x0a01f04f, 
+    0xe00ad006, 0x23062504, 0x2505e7e5, 0xe7e22307, 0xfd9bf008, 0x4285b2c0, 0xf887d002, 0xe001a000, 
+    0xb3587838, 0x70382000, 0x1e402131, 0x4260f04f, 0xf977f7e0, 0xf7ff2000, 0xf898fe97, 0x46470000, 
+    0xfaf6f008, 0x23007839, 0x46282202, 0xff48f007, 0x46287932, 0xf0087839, 0xf7e1f97b, 0x483afb99, 
+    0x21042201, 0xa000f8cd, 0x3380f44f, 0xfa26f7e7, 0x0000f89b, 0x2801b190, 0xe00ad008, 0x4260f04f, 
+    0x17502130, 0xf94df7e0, 0xe067e7f2, 0xf7ff2001, 0xf996fe43, 0xf7ff0003, 0x70f0fe33, 0x0003f996, 
+    0x1000f898, 0xfc21f008, 0x78004829, 0xd0172801, 0x78004828, 0xd0132801, 0xf0082000, 0x2208fd6e, 
+    0x01514825, 0xfabbf00b, 0x207370b0, 0x22008030, 0xf8d94916, 0xf0060004, 0x1d01f87e, 0xe00dd006, 
+    0xf0082001, 0xf886fd5a, 0xe7eea002, 0x1070f240, 0x490ee009, 0x46182200, 0xf86df006, 0xf47f1d40, 
+    0xf240af25, 0x86a01071, 0x8ff8e8bd, 0x00042578, 0xf1001080, 0xf23c830e, 0x000402f3, 0xf23d0278, 
+    0xf23c8022, 0x000402f4, 0x00042f94, 0x0004e9a8, 0xe0000100, 0x0004232e, 0x00042380, 0x00040292, 
+    0x0004237c, 0xf23d014e, 0xf3074084, 0x00042382, 0x00040285, 0x0004028d, 0xf38f2002, 0x88004865, 
+    0x7fe8f5b0, 0xf5b0d002, 0xd10a7ff8, 0x49634862, 0x42886800, 0x2301d105, 0x22004861, 0xf00b4619, 
+    0xf89bfa50, 0x4f5f0000, 0x817cf8df, 0xf897b380, 0xf1bcc000, 0xd1010f00, 0xd01d2803, 0x2000f898, 
+    0x2802b90a, 0xf996d018, 0x29041003, 0x2905d021, 0x2903d030, 0x2803d1a3, 0x7829d1a1, 0x20052300, 
+    0xf0074662, 0x7829fe8d, 0x20052200, 0xf8c0f008, 0x28017838, 0xe033d032, 0x23007829, 0x20032202, 
+    0xfe7ef007, 0x22007829, 0xf0082003, 0xe051f8b1, 0x2801e028, 0x7829d1de, 0x22012300, 0xf0072002, 
+    0x7829fe6f, 0x20022200, 0xf8a2f008, 0xf7ff2001, 0xe05cfd83, 0xd1cd2802, 0x23007829, 0xf0072004, 
+    0x7829fe5f, 0x20042200, 0xf892f008, 0x0000f898, 0xd1012801, 0xe02e2304, 0xe02c2306, 0xe02a2305, 
+    0xe0282307, 0x0003f996, 0xd0062805, 0xd0282804, 0xd0052805, 0xd0282804, 0x7838e007, 0xd0bb2800, 
+    0x28037838, 0x2802d0b8, 0x78f0d022, 0x78292300, 0xf0072201, 0x7932fe35, 0x782978f0, 0xf868f008, 
+    0x0003f996, 0xd0d92805, 0xd0d32804, 0xd01e2802, 0xd01e2801, 0x46502303, 0x211e2201, 0xf9c1f00b, 
+    0xf898e60f, 0x28000000, 0xf898d096, 0xe7da0000, 0x230078f0, 0x22027829, 0xfe12f007, 0x220078f0, 
+    0xf0087829, 0x78f0f845, 0xd0b92805, 0x2302e7b4, 0x2301e7e1, 0x2200e7df, 0xb5102101, 0x405bf2af, 
+    0xfdc4f005, 0x20022108, 0xff22f005, 0x60484907, 0x0000bd10, 0x00042576, 0x00042570, 0x4a9e1cee, 
+    0xf30740ca, 0x00042327, 0x00042326, 0x00042f94, 0x4ff0e92d, 0xb3e8f8df, 0xb0872001, 0x5298f04f, 
+    0x1000f99b, 0xfffdf7df, 0xf8df48f6, 0x7800a3dc, 0xd04c2800, 0x22064ff5, 0x46382140, 0xf97ff00b, 
+    0x09fff000, 0x22054638, 0xf00b2120, 0x4ceff978, 0x08fff000, 0x343c2201, 0x46202102, 0xf96ff00b, 
+    0x4620b2c6, 0x21012200, 0xf969f00b, 0xb2c52208, 0x01514638, 0xf963f00b, 0x4604220c, 0xf24148e4, 
+    0xf00b0100, 0x4384f95c, 0x22074638, 0xb2e42180, 0xf955f00b, 0x4607220b, 0xf64048dd, 0xf00b0100, 
+    0x4adcf94e, 0xf89a4387, 0xb2f90000, 0xc000f892, 0x0380f3c0, 0x0740f3c0, 0xac014622, 0xe9cd9600, 
+    0xf0007305, 0x462b0001, 0x1301e884, 0xf89ae012, 0x24010000, 0xf3c02100, 0xf3c00280, 0xf0000340, 
+    0xe9cd0001, 0x91021403, 0x1000e9cd, 0x3205e9cd, 0x460a460b, 0x0000f248, 0xf85cf7ed, 0x46112200, 
+    0xf845f7ed, 0xf88b210f, 0xb0071000, 0x4ff0e8bd, 0xba1ff7e2, 0x212c48ba, 0xf04fb570, 0x46225498, 
+    0x20017041, 0xff7df7df, 0x680048bb, 0xd01c2812, 0xd01d2813, 0xd01e2815, 0xd01f2816, 0xd0202817, 
+    0xd0212818, 0xd0222819, 0xd0232820, 0xd0242821, 0xd0252822, 0xd0262823, 0xd0272811, 0xd02828ff, 
+    0xd0292801, 0xd02a2810, 0x2120e02e, 0xe0284622, 0x46222121, 0x2123e025, 0xe0224622, 0x46222124, 
+    0x2133e01f, 0xe01c4622, 0x46222136, 0x2137e019, 0xe0164622, 0x46222138, 0x2139e013, 0xe0104622, 
+    0x4622213a, 0x213be00d, 0xe00a4622, 0x4622211f, 0x212fe007, 0xe0044622, 0x46222130, 0x211ee001, 
+    0x20014622, 0xff2df7df, 0xf00b4894, 0x2200f88d, 0x20014601, 0xff25f7df, 0x380a488c, 0xf884f00b, 
+    0x488a4604, 0xf00b380c, 0x4605f87f, 0x380e4887, 0xf87af00b, 0x46294622, 0x4070e8bd, 0xb9c6f7e2, 
+    0x5ffce92d, 0x20014e7e, 0x5298f04f, 0x1001f996, 0xff07f7df, 0x380a487d, 0xf866f00b, 0x487b4607, 
+    0xf00b380c, 0xf8dff861, 0x460581e4, 0x080ef1a8, 0xf00b4640, 0x4604f859, 0x4629463a, 0xf9a6f7e2, 
+    0xf248220f, 0x46400100, 0xf879f00b, 0x1002f996, 0x08fff000, 0x91c8f8df, 0xa1c8f8df, 0xf8df2904, 
+    0xd00eb1c8, 0xd05b2932, 0xf04f2905, 0xd0765298, 0x2001211c, 0xfed5f7df, 0x0f01f1b8, 0x202bd06e, 
+    0x2001e118, 0x5298f04f, 0xfecbf7df, 0xf3c46970, 0x43082141, 0xf5b06170, 0xd0206f85, 0x42884963, 
+    0x07a8d1ea, 0x2001d000, 0xf3c54961, 0x70080240, 0x0001f005, 0x1000f899, 0xf8894311, 0xf89a1000, 
+    0x4a5c3000, 0xf88a4318, 0xf89b0000, 0x78123000, 0x2300e9cd, 0x78134a58, 0x78124a58, 0x4958e03a, 
+    0x1082f3c4, 0x28044a57, 0x4f584d57, 0xd0094b58, 0x70082000, 0x46017010, 0x70387028, 0xf00a4618, 
+    0xe7b9fff6, 0x70082001, 0x0080f3c4, 0xf3c47010, 0x70280040, 0x0001f004, 0x05e07038, 0xe7ed0c01, 
+    0xf04f2001, 0xf7df5298, 0x4620fe7c, 0xfb97f7ed, 0x78004848, 0xd19f2801, 0xf89b483e, 0x78001000, 
+    0x0100e9cd, 0xf899483c, 0x78031000, 0x7802483b, 0x0000f89a, 0xfcfdf7ed, 0xe000e78e, 0x2001e0a9, 
+    0xfe5ff7df, 0x482c69b1, 0x4258f5a1, 0xd0053a97, 0xf5a12210, 0x3b6d4368, 0xe07cd076, 0xf0054a36, 
+    0xf3610103, 0x80b4141f, 0x3100f3c7, 0x21ff7011, 0x028bf3c5, 0x6f80f5b2, 0xf415d004, 0xd0007f60, 
+    0xe0842111, 0xd0172c10, 0xd0152c20, 0x2c01b1a4, 0x2c02d017, 0x2c03d017, 0x2c04d017, 0x2c05d017, 
+    0x2c06d017, 0x2c07d017, 0x2c08d017, 0x2c09d046, 0x2c0ad046, 0xe06ad046, 0x60012112, 0x7030200f, 
+    0x2113e04a, 0x2115e063, 0x2116e061, 0x2117e05f, 0x2118e05d, 0x2119e05b, 0x2120e059, 0xe033e057, 
+    0x00042f9c, 0x000425f3, 0x0004232c, 0xf38e0040, 0xf38f0008, 0x00042328, 0x00040240, 0xf38fffd0, 
+    0x000425fd, 0x000425fc, 0x000425ef, 0x00fa073e, 0x000425f6, 0x000425f0, 0x000425fb, 0x000425fa, 
+    0x000425e1, 0x000425e4, 0x000425e6, 0x000425e9, 0xf23c8026, 0x000425f4, 0x0004230d, 0xe0262121, 
+    0xe0242122, 0xe0222123, 0x1145f3c4, 0xd1022902, 0x07090861, 0x6002d01a, 0x010bf3c7, 0xf00a48f7, 
+    0x48f6ff36, 0x1c802100, 0xff31f00a, 0xb2818b30, 0x1d0048f2, 0xff2bf00a, 0x220069b0, 0xf3c021ff, 
+    0x48ee4307, 0xf00a1d80, 0xe6e5ff3c, 0x60012101, 0x2002e7e2, 0xe8bd7070, 0xe92d9ffc, 0x4de847fc, 
+    0x5a98f04f, 0x46522001, 0x1001f995, 0xfda9f7df, 0xf00a48e4, 0x4604ff09, 0x1e8048e2, 0xff04f00a, 
+    0x9380f8df, 0xf1a94606, 0x46480904, 0xfefcf00a, 0x46314622, 0xf84af7e2, 0xf248220f, 0x46480100, 
+    0xff1df00a, 0x08fff000, 0x0100f242, 0x4648220d, 0xff15f00a, 0xf240b2c7, 0x220071ff, 0xf00a4648, 
+    0x2f01ff0e, 0xd108b2c0, 0xd0122809, 0x280b2703, 0x2805d03e, 0x2806d051, 0x2129d05b, 0x20014652, 
+    0xfd6ff7df, 0x0f01f1b8, 0x202bd001, 0xe8bd7068, 0x212787fc, 0x20014652, 0xfd63f7df, 0x50c0f414, 
+    0x2001d000, 0x4ec149c0, 0x70084fc1, 0x20c0f3c4, 0x703049c0, 0x3000f3c4, 0xf3c47038, 0x700800c0, 
+    0xea00200e, 0x48bc1154, 0x48b47001, 0xf00a384a, 0x49bafeae, 0x780948ba, 0xe9cd7800, 0x48b90100, 
+    0x78037831, 0x780248b8, 0xf7ed7838, 0xe7c9fbd2, 0x46522128, 0xf7df2001, 0xb2e0fd34, 0x49b44ab3, 
+    0x4000ea46, 0x42906128, 0xf3c4d102, 0xe0002000, 0x70082000, 0x706f2032, 0x2125e015, 0x20014652, 
+    0xfd1ff7df, 0xea400370, 0x61680084, 0x706f2004, 0x2126e009, 0x20014652, 0xfd13f7df, 0x20c6ea44, 
+    0x200561a8, 0x70a8706f, 0x4995e79c, 0x30fff04f, 0x70084aa0, 0x70887048, 0x61882000, 0x61086148, 
+    0x60112110, 0x4a9f499c, 0x499c7008, 0x499c7008, 0x21017008, 0x4a9c7011, 0x4a9c7011, 0x499c7011, 
+    0x499c7008, 0x498b7008, 0x499b7008, 0x498b7008, 0x498b7008, 0x498e7008, 0x49987008, 0x49827008, 
+    0x49887008, 0x49887008, 0x49817008, 0x497f7008, 0x49937008, 0x47707008, 0xf7ffb57c, 0x4891ffc6, 
+    0xf00a2108, 0x4890fe34, 0x48907801, 0xf7ed7800, 0x488ffc38, 0x0500f241, 0x340a4c72, 0x2a988802, 
+    0x2a88d00e, 0x2aa8d00c, 0x2ab8d00a, 0x2a94d008, 0x2a84d010, 0x2aa4d00e, 0x2ab4d00c, 0xe00fd00a, 
+    0x46292300, 0x4620220c, 0xfe2bf00a, 0x23002208, 0xe0020151, 0x46292300, 0x4620220c, 0xfe21f00a, 
+    0x46202300, 0x21042202, 0xfe1bf00a, 0x2300485d, 0x461a2101, 0xf00a3042, 0xf7edfe14, 0x2000f92a, 
+    0x46039000, 0x46014602, 0xf7ed9001, 0x4871fb22, 0xf00a2100, 0x4851fdec, 0xf00a2100, 0x484ffde8, 
+    0x1c802100, 0xfde3f00a, 0x2100484c, 0xf00a1d00, 0x484afdde, 0x21ff2300, 0x1d80461a, 0xfdf1f00a, 
+    0xf7e62001, 0x2011fd94, 0xfd91f7e6, 0xf7e62012, 0x2002fd8e, 0xfe73f7ec, 0x2202485f, 0xf00a2104, 
+    0x2401fdee, 0xd1092801, 0x2201485c, 0x7004495c, 0xf7e62004, 0x200bfc7f, 0xfd79f7e6, 0x201b4959, 
+    0x220c2300, 0x46297008, 0x70444835, 0x1d804852, 0xfdc7f00a, 0x2102b002, 0xe8bd2001, 0xf04f4070, 
+    0xf7df4270, 0xe92dbc3e, 0x4c2d5ff0, 0x8e804605, 0x0901f04f, 0x28f0b130, 0x28f1d014, 0xf8c4d134, 
+    0xe01a900c, 0xff21f7ff, 0xf04f4925, 0x68a032ff, 0xf005311c, 0x60e0fbaf, 0xd0011d00, 0xe00868e0, 
+    0xe02020f0, 0x2200491e, 0x311c68a0, 0xfba2f005, 0x1d4160e0, 0x2801d016, 0x4f19d1e6, 0x4620f04f, 
+    0x46322001, 0xf9b7371c, 0xf7df1000, 0xf9b7fc0a, 0x293a1000, 0x293bd00a, 0x2001d00e, 0xf7df4632, 
+    0xe7d1fc00, 0x86a820f1, 0x9ff0e8bd, 0xff24f7ff, 0x20017862, 0xe1737821, 0x7800482b, 0xd0552801, 
+    0x0001f994, 0xd0532801, 0xd0542802, 0xd0552803, 0xd0562806, 0xd0572807, 0x0000e058, 0xf203515c, 
+    0x00042f9c, 0xf38e0036, 0x000425f8, 0x000425fd, 0x000425fc, 0x000425f1, 0x000402ca, 0x000425ef, 
+    0x000425f0, 0x000425fb, 0x000425fa, 0x002901d4, 0x000425f4, 0x00040240, 0x000425e4, 0x000425e6, 
+    0x000425e9, 0x000425e7, 0x000425e5, 0x000425ea, 0x000425e1, 0x000425ed, 0x000425ee, 0x000425f6, 
+    0x0004232d, 0xf38f228a, 0x0004255d, 0x0004255c, 0x00042576, 0xf38f0076, 0xf2039026, 0x000425f2, 
+    0x684ee180, 0x0004024d, 0x0004028e, 0x9001f884, 0xfa4ef000, 0xf7ffe00a, 0xe007fde0, 0xfc80f7ff, 
+    0xf000e004, 0xe001f9ed, 0xf9b3f000, 0x282b7860, 0xf7ffd101, 0xf994fbff, 0xf04f1000, 0x290d5b98, 
+    0x290ed021, 0x2931d02b, 0x2934d03b, 0x0605f24a, 0x2935d03a, 0xf8dfd045, 0x290fa408, 0x2910d05f, 
+    0xf04fd06d, 0xf242082d, 0x4ffe0601, 0xd0692919, 0xd07a291a, 0xd0792911, 0xd0782912, 0xd0772913, 
+    0xd076292d, 0x2001e0cd, 0xf7df465a, 0x2200fb5a, 0x0009f24a, 0xf7ec4611, 0x2034fc0a, 0x2001e00f, 
+    0xf7df465a, 0x48f0fb4e, 0x78002129, 0x2200ea41, 0x11d4f240, 0x000bf24a, 0xfbf9f7ec, 0x70202031, 
+    0xf7ffe02a, 0xe0a6fb35, 0x465a2001, 0xfb39f7df, 0x12cff240, 0x71d0f240, 0xf7ec4630, 0x2035fbe8, 
+    0x2001e7ed, 0xf7df465a, 0x4fddfb2c, 0x22072019, 0x37147020, 0x46382180, 0xfcb1f00a, 0x46062208, 
+    0x01514638, 0xfcabf00a, 0x0040ea46, 0xf248b281, 0x22004000, 0xfbcbf7ec, 0xfdabf7e1, 0x2001e07b, 
+    0xf7df465a, 0x4631fb0e, 0xf00a4650, 0x2100fc70, 0x120af240, 0xf7ec4630, 0x2010fbba, 0xf000e7bf, 
+    0xe068f8f2, 0x465a2001, 0xfafbf7df, 0x282c7860, 0x48c6d103, 0x28016800, 0x2297d00c, 0x0006f24a, 
+    0xf7ec211b, 0x201afba4, 0xe00fe7a9, 0xe013e011, 0xe035e01e, 0x46302200, 0xf7ec4611, 0x4631fb98, 
+    0xf00a4638, 0xf884fc44, 0xe0478000, 0xf893f000, 0xf000e041, 0xe03ef866, 0x465a2001, 0xfad1f7df, 
+    0x010af24a, 0xf00a4638, 0x2013fc32, 0xe00e7020, 0x465a2001, 0xfac5f7df, 0x304c48a9, 0xfc24f00a, 
+    0x010ef000, 0xf00a4638, 0xf884fc22, 0x46388000, 0xfc1af00a, 0x46012200, 0xf7df2001, 0xe01afab2, 
+    0x465a2001, 0xfaadf7df, 0xf44f2100, 0xf7e62000, 0x489bfb03, 0x1c802100, 0xfc09f00a, 0x21004898, 
+    0xf00a1d00, 0x4631fc04, 0xf00a4650, 0x4631fc00, 0xf00a4638, 0x7820fbfc, 0xd102282d, 0x282c7860, 
+    0x7862d003, 0x78212002, 0x4991e00a, 0x465a2000, 0x211d7008, 0xf7df2001, 0x7862fa84, 0x78212003, 
+    0xfbcaf7e1, 0x2200e650, 0xb5102101, 0x3089f2af, 0xf81cf005, 0x20042108, 0xf97af005, 0x60884985, 
+    0xb570bd10, 0x20014c83, 0x5298f04f, 0x1000f994, 0xfa67f7df, 0x4d7b78e2, 0x2a01b132, 0x0100f248, 
+    0x2a02d004, 0xe00ad006, 0x0108f24a, 0xf00a4628, 0xe004fbbe, 0xf00a4628, 0x2012fbba, 0x46287020, 
+    0xfbb2f00a, 0x46012200, 0xf7df2001, 0x78e0fa4a, 0x70e01c40, 0xe92dbd70, 0x4c6e41f0, 0xf04f2001, 
+    0xf9945298, 0xf7df1000, 0x486bfa3c, 0x010af248, 0x0500f241, 0xf4028802, 0xf5b2707e, 0xea417fe8, 
+    0x48660640, 0xf5b2d002, 0xd10e7ff8, 0x780f4964, 0xd10a2f01, 0x4a644963, 0x42916809, 0xf00ad105, 
+    0xf367fb83, 0xb282301f, 0xf00ae003, 0xf3c0fb7d, 0x4629020b, 0xf7ec4630, 0x200efaca, 0xe8bd7020, 
+    0xf7e141f0, 0xb570bca6, 0x20014c52, 0x5298f04f, 0x1000f994, 0xfa05f7df, 0x4d504854, 0x78001dad, 
+    0xd00e2801, 0x46112200, 0xf7ec4610, 0x2100fab0, 0xf00a4628, 0x202dfb5c, 0xe8bd7020, 0xf7e14070, 
+    0x484bbc88, 0x494b2200, 0x78097800, 0xf00107c0, 0x0f400101, 0x0041ea40, 0x78094947, 0x0101f001, 
+    0x46114308, 0x7080f440, 0xfa91f7ec, 0x3180f248, 0xe92de7de, 0x4c3741f0, 0x5698f04f, 0x46322001, 
+    0x1001f994, 0xf9cdf7df, 0x220f4f2e, 0x0100f248, 0x46381cbf, 0xfb53f00a, 0x46052200, 0x71fff240, 
+    0xf00a4638, 0x4680fb4c, 0xf00a4638, 0x2200fb1d, 0x20014601, 0xf9b5f7df, 0x1002f994, 0xd1092908, 
+    0x46322001, 0xf9adf7df, 0x4641482c, 0xfb0ff00a, 0x70602006, 0xd1012d00, 0x7060202b, 0x81f0e8bd, 
+    0x41f0e92d, 0x20014c1b, 0x5298f04f, 0x1001f994, 0xf997f7df, 0x220f4f13, 0x0100f248, 0x46381cbf, 
+    0xfb1df00a, 0x4680220d, 0x0100f242, 0xf00a4638, 0x2200fb16, 0xf2404606, 0x463871ff, 0xfb0ff00a, 
+    0x46384605, 0xfae0f00a, 0x46012200, 0xf7df2001, 0x2e01f978, 0x2d0ad126, 0x2008d124, 0xe01f70a0, 
+    0xf38e002c, 0xf38fffce, 0x000425f3, 0x00040240, 0x0004024d, 0x00042f9c, 0x00042576, 0xf23c801e, 
+    0x0004230c, 0x00042570, 0x4a9e1cee, 0x000425e0, 0x000425e5, 0x000425e7, 0x000425ea, 0xf2035112, 
+    0x70602007, 0x0f00f1b8, 0x202bd1a8, 0xe7a57060, 0x41f0e92d, 0xf04f4c23, 0x20015898, 0xf9944642, 
+    0xf7df1001, 0x4f20f93e, 0xf00a4638, 0x2200fa9d, 0x46014605, 0xf7df2001, 0x481cf934, 0x220c2600, 
+    0x0100f241, 0x46387006, 0xfab9f00a, 0xf7ecb130, 0x200dfdc0, 0x20027020, 0xe0167060, 0xf248220f, 
+    0x46380100, 0xfaabf00a, 0x2011b128, 0x20067020, 0x70e67060, 0x202de009, 0x202b7020, 0xb9257060, 
+    0x4642212e, 0xf7df2001, 0x4909f90c, 0x22002001, 0x20047008, 0xf7e64907, 0xe8bdf92d, 0x200b41f0, 
+    0xba25f7e6, 0x00042f9c, 0xf38e0026, 0x00042620, 0x000425f2, 0x684ee180, 0x4841b570, 0xf00a255c, 
+    0x4604fa53, 0x1e80483e, 0xfa4ef00a, 0xf4044a3d, 0x8011717f, 0x0103f004, 0x80114a3b, 0x5254f5a0, 
+    0xf0243a90, 0xd1220103, 0x4fa3f5b1, 0xf5a1d031, 0x388440a2, 0x1f00d02d, 0x3808d02b, 0x1f00d029, 
+    0x1f00d027, 0x3808d025, 0x1f00d023, 0x1f00d021, 0x3808d01f, 0x1f00d01d, 0x1f00d01b, 0x3818d019, 
+    0x3820d017, 0x301cd015, 0x3820d013, 0x2000d011, 0x4826b188, 0x21e02205, 0xfa41f00a, 0x22004924, 
+    0x70084c24, 0x46202101, 0xfa39f00a, 0xd00b2801, 0x2001e010, 0xf7f9e7ec, 0x481cfceb, 0x31b0f64b, 
+    0xf00a3082, 0xe7fefa04, 0x46202301, 0x21102204, 0xfa17f00a, 0xf64f4817, 0x300871ff, 0xf9f7f00a, 
+    0x46202301, 0x21042202, 0xfa0bf00a, 0x46202301, 0x461a2102, 0xfa05f00a, 0x6828490f, 0xf6426008, 
+    0x480a1114, 0xf00a3818, 0x4808f9e2, 0x1102f243, 0xf00a381a, 0xe8bdf9dc, 0xf7f94070, 0x0000bb84, 
+    0xf2020006, 0x00042576, 0x00042578, 0xf23c8038, 0x0004023c, 0xf23c8318, 0x00042558, 0x4d1eb570, 
+    0x8e804604, 0x285eb120, 0x285fd00d, 0xe014d125, 0xf04f4919, 0x682832ff, 0xf0041d09, 0x1d01ffdb, 
+    0x205ed107, 0x4914e018, 0x68282200, 0xf0041d09, 0x1d41ffd1, 0x2801d00f, 0x4e0fd1ea, 0x88301d36, 
+    0xd1e52862, 0x2102480d, 0xf9a1f00a, 0x0002f9b6, 0xf879f7df, 0x205fe7dc, 0xbd7086a0, 0x21012200, 
+    0xf2afb510, 0xf0040067, 0x2108fdd1, 0xf0042003, 0x4901ff2f, 0xbd106008, 0x00042fc0, 0xf23c806e, 
+    0x41f0e92d, 0x22014dff, 0x46282106, 0xf9a7f00a, 0x1cb74efd, 0xb3201eb4, 0x46282201, 0xf00a2106, 
+    0x2801f99e, 0x2201d029, 0x21064628, 0xf997f00a, 0xd1252802, 0x0100f243, 0xf00a4630, 0x219cf968, 
+    0xf00a4638, 0x2301f964, 0x22004620, 0xf00a210f, 0x4620f978, 0x41f0e8bd, 0x22042301, 0xf00a2110, 
+    0xf240b970, 0x46307507, 0xf00a4629, 0x4629f950, 0xf00a4638, 0x230ff94c, 0xf240e7e6, 0xe7db1100, 
+    0x81f0e8bd, 0x41f0e92d, 0x48de4606, 0xf93cf00a, 0xf3c00ac5, 0xf7ff1784, 0xf8dfffb3, 0x2400836c, 
+    0x0824f1a8, 0x2301e007, 0x21024640, 0xf00a461a, 0x1c64f948, 0x42bcb224, 0x2400dbf5, 0xe0074647, 
+    0x46382301, 0x21042202, 0xf93bf00a, 0xb2241c64, 0xdbf542ac, 0x20012100, 0xf920f7e7, 0x4638b2b3, 
+    0x21012200, 0xf92df00a, 0xf7e72003, 0xf04ff94d, 0xb1360301, 0x21042202, 0xe8bd4638, 0xf00a41f0, 
+    0x2201b920, 0xe7f72102, 0x2000b51f, 0x90019000, 0x90039002, 0xf7e84668, 0x9800f874, 0x48bbb281, 
+    0xf8f5f00a, 0x0c019800, 0x1c8048b8, 0xf8eff00a, 0xb2819801, 0x1d0048b5, 0xf8e9f00a, 0x0c019801, 
+    0x1d8048b2, 0xf8e3f00a, 0xb2819802, 0x300848af, 0xf8ddf00a, 0x0c019802, 0x300a48ac, 0xf8d7f00a, 
+    0xb2819803, 0x300c48a9, 0xf8d1f00a, 0x0c019803, 0x300e48a6, 0xf8cbf00a, 0xb570bd1f, 0x20014ca4, 
+    0x52a0f04f, 0x1103f240, 0x70e00605, 0xf7de4628, 0xf240ff58, 0x462811f4, 0xff05f7de, 0x61eef64e, 
+    0xf7de4628, 0x499bfeef, 0xf7de4628, 0x2300feeb, 0x21014899, 0xf00a461a, 0x4998f8c4, 0x4a982000, 
+    0x13697008, 0x1c407f20, 0x0007f000, 0x1000eb00, 0x0080eb02, 0x20026081, 0xf86af7e6, 0x4070e8bd, 
+    0xf7e62003, 0xe92db865, 0x46894ff0, 0x4690498d, 0x2201469b, 0x0a00f04f, 0x68094656, 0x88090253, 
+    0xa000f8c8, 0x3000f8ab, 0x0151eb02, 0xfa0f9a09, 0xf8a2fc81, 0xe055a000, 0xe02c2500, 0x0e05eb06, 
+    0x0f02f1be, 0xeb00d404, 0xf851018e, 0xe0007c08, 0x46522700, 0xf04f4654, 0x18e933ff, 0x4561d406, 
+    0xeb0eda04, 0xf8500103, 0xe0001021, 0x428f2100, 0x4614da03, 0x460f463a, 0x428ae007, 0x4614da02, 
+    0xe002460a, 0xda00428c, 0x1c5b460c, 0xdbe42b03, 0xf8491c6d, 0x4565402e, 0x2300dbd0, 0x18f1e01f, 
+    0x5000f8d8, 0x4021f850, 0x1021f859, 0x17ca1a61, 0xeb7a1a6d, 0xda110402, 0xda012a00, 0xe0072100, 
+    0x4580f04f, 0x1a6d2400, 0xda014194, 0x5100f04f, 0x1000f8c8, 0x3000f8ab, 0x800e9909, 0x45631c5b, 
+    0x4466dbdd, 0x0f8cebb6, 0xe8bddba6, 0xe92d8ff0, 0x240043f8, 0x461d460f, 0x94004616, 0x52a0f04f, 
+    0x8020f8dd, 0x1000f9b0, 0x7080f04f, 0xfea9f7de, 0x7004484d, 0x70c44846, 0x484c7104, 0xb1786800, 
+    0x7800484b, 0xd0082801, 0x48432100, 0x3102f201, 0xf0093008, 0xe8bdfffc, 0xf24283f8, 0xe7f47110, 
+    0xf04f703c, 0x603030ff, 0x0000f8c8, 0x48370c01, 0x1f80602c, 0xffebf009, 0x22084c34, 0x3c1c2300, 
+    0x46200151, 0xfffdf009, 0xf44f4d30, 0x4f390100, 0x91003538, 0xe00c138e, 0x462a2104, 0xf7e54668, 
+    0x2801ff60, 0x2301d00c, 0x22094631, 0xf0094620, 0x2206ffe8, 0x21404638, 0xfff1f009, 0xd1eb2800, 
+    0x23004821, 0x21102204, 0xf0091e80, 0xe7c2ffda, 0x4ff8e92d, 0x460c2500, 0x46904699, 0xab0ae9dd, 
+    0xf04f9500, 0xf9b052a0, 0xf04f1000, 0xf7de7080, 0x4821fe48, 0x60054e16, 0x70054820, 0x0005f996, 
+    0xd1141c40, 0xc078f8df, 0xf8df2100, 0x2000e078, 0x1741eb0c, 0x1241eb0e, 0x3010f837, 0x3010f822, 
+    0x28101c40, 0x1c49dbf8, 0xdbf02904, 0x480e7175, 0x70f57005, 0xf8c87135, 0xf8c95000, 0xf8ca5000, 
+    0xe0215000, 0xf2020126, 0xf2035252, 0xf2035142, 0x00042fcc, 0xdcba01f5, 0xf23c80b2, 0x000402da, 
+    0x00043790, 0x00042618, 0x000402d9, 0x00057f70, 0x0004257a, 0xf203502c, 0x000425d8, 0x000425dc, 
+    0x00043500, 0x00043600, 0x5000f8cb, 0x28007970, 0x7870d17e, 0xd07c2800, 0x780048fe, 0xd27928fa, 
+    0x0002f996, 0x28007020, 0x4dfbd072, 0x0000f44f, 0xf2404ff9, 0x35542800, 0x3ffa4cf7, 0xe00c9000, 
+    0x462a2105, 0xf7e54668, 0x2801fecc, 0x2301d00c, 0x22094641, 0xf0094620, 0x2206ff54, 0x21404638, 
+    0xff5df009, 0xd1eb2800, 0x35fff240, 0x230148eb, 0x22004629, 0xff45f009, 0x230f48e8, 0x46292200, 
+    0xf0091e80, 0x88f0ff3e, 0x2002bb08, 0xfedff7e5, 0x46202208, 0x01512301, 0xff33f009, 0x20402100, 
+    0xfe0af7e5, 0xf7e52003, 0x2100fed2, 0xf7e52040, 0x2100fe03, 0xf7e82008, 0x2001f9b0, 0xf9f5f7e8, 
+    0x230048d6, 0x21102204, 0xf0093832, 0x2101ff1a, 0x46082207, 0xf964f7e8, 0x218c48d1, 0xfef7f009, 
+    0x23ff48ce, 0x46292200, 0xf0093818, 0x48cbff0a, 0x2200233f, 0x11fff240, 0xf0091f00, 0x48c9ff02, 
+    0x28017800, 0xf644d01e, 0x48c76120, 0xe0028800, 0xe01ce016, 0xeb00e019, 0xebc20240, 0xeb0110c0, 
+    0x8bb100c0, 0xf5a04408, 0xb281707a, 0x301448bc, 0xfecdf009, 0xb2818bb0, 0x301848b7, 0xfec7f009, 
+    0x8ff8e8bd, 0x5130f247, 0x7025e7df, 0x2141e7f8, 0xf04f7025, 0xf04f52a0, 0xf7de7080, 0xe7effd52, 
+    0x4fffe92d, 0x4607b083, 0xf04f2005, 0xf7e50b00, 0x4caefd5b, 0x48ae60e0, 0x28017800, 0x2802d037, 
+    0x48acd035, 0xfea0f009, 0x48aa4605, 0xf0091c80, 0xea45fe9b, 0x61604000, 0x70e02000, 0x46806360, 
+    0x21009000, 0x4000f240, 0xfd86f7e5, 0x780048a2, 0x4c9eb328, 0xf04f2000, 0xf2407580, 0x70e011f4, 
+    0xf7de4628, 0x499dfcd0, 0xf7de4628, 0x499cfcbb, 0xf7de4628, 0x7f20fcb7, 0xf0001c40, 0xeb000007, 
+    0x48981100, 0x0081eb00, 0x31106881, 0x4891e184, 0xf0091f00, 0x4605fe69, 0x1e80488e, 0x2005e7c7, 
+    0xfd12f7e5, 0x61204c89, 0x78004889, 0xd0132801, 0xd0112802, 0xf0094887, 0x4605fe57, 0x1c804885, 
+    0xfe52f009, 0x4000ea45, 0xe9d461a0, 0x42810103, 0x1a41d90a, 0xe0081c09, 0x1f00487e, 0xfe44f009, 
+    0x487c4605, 0xe7eb1e80, 0x4a7f1a41, 0x0004f04f, 0x0a14f04f, 0x091ef04f, 0x2000f992, 0xd0022a05, 
+    0xd0052a04, 0x2005e009, 0x0a0ff04f, 0xe0032214, 0xf04f2006, 0x220f0a0a, 0x40c14691, 0x9101486b, 
+    0x0105e9d0, 0xd2024281, 0x1c241a0c, 0x1a0ce000, 0x3f80f5b4, 0xf5a4d301, 0x98013480, 0xf00b44a0, 
+    0x4605fe6b, 0x4620460e, 0xfe66f00b, 0x22004b67, 0xfeb2f00b, 0x4633462a, 0xfc92f00b, 0x48644605, 
+    0xe9d0460e, 0x46282300, 0xffa4f00b, 0x6b414857, 0x1c49d20d, 0x485f6341, 0xe9d04631, 0x46282300, 
+    0xff98f00b, 0x4851d207, 0x1c496b41, 0x2900e002, 0x2100da01, 0x484d6341, 0x6b404659, 0xdd004583, 
+    0x46834608, 0x45d0b127, 0x4948d302, 0x6348200b, 0xd0041c78, 0xd30245c8, 0x200b4944, 0x46316348, 
+    0xe9d0484c, 0x46282300, 0xff74f00b, 0x483fd303, 0x290a6b41, 0xf8dfdd6c, 0x210190f4, 0x0000f999, 
+    0xd0082802, 0xd0062803, 0x4836b3a7, 0x1003f889, 0xb3807800, 0xb36fe03b, 0xf04f9805, 0x70017a80, 
+    0x11f4f240, 0xf7de4650, 0xf64afbfe, 0x465041ca, 0xfbe8f7de, 0x46504641, 0xfbe4f7de, 0x22004b36, 
+    0x46314628, 0xfe48f00b, 0xfdb2f00b, 0x46504601, 0xfbd8f7de, 0x1034f8d9, 0xf7de4650, 0x9805fbd3, 
+    0x1000f990, 0xf7de4650, 0x4925fbcd, 0xf7de4650, 0xe00cfbc9, 0xe7ffe009, 0x3000f44f, 0x0103f640, 
+    0xfbd1f7de, 0xffc8f7ea, 0x9806e001, 0xf04f7001, 0xf2407a80, 0x46501bf4, 0xf7de4659, 0xf64afbc4, 
+    0x183920aa, 0xf7de4650, 0x9805fbad, 0x1000f990, 0xf7de4650, 0x9806fba7, 0x1000f990, 0xf7de4650, 
+    0x4805fba1, 0xf00938fa, 0x4601fd5f, 0xe0254650, 0x0000e099, 0x0004257c, 0xf2035126, 0xf2035282, 
+    0xf23c80a6, 0x0004257a, 0x00057f78, 0x00042fcc, 0x000425f9, 0xf2036116, 0x000402d9, 0x0bbbdead, 
+    0xdcba01f5, 0x00043790, 0x00040292, 0x40140000, 0x000402e0, 0x000402e8, 0x40c38800, 0xfb72f7de, 
+    0x463148fa, 0x2300e9d0, 0xf00b4628, 0xd208fed3, 0x46544621, 0xf7de4650, 0x9901fb65, 0xf7de4620, 
+    0xf8d9fb61, 0x464c1010, 0x46504655, 0xfb5af7de, 0x462868e1, 0xfb56f7de, 0x46284eed, 0xf7de4631, 
+    0xf242fb51, 0x064801c0, 0xfb69f7de, 0x780048e9, 0x2100b350, 0xb13f70e1, 0x0000f994, 0xd0012802, 
+    0xd1012803, 0x70019805, 0x46284659, 0xfb4bf7de, 0x21bbf64a, 0xf7de4628, 0x4631fb35, 0xf7de4628, 
+    0x7f20fb31, 0xf0001c40, 0xeb000007, 0x48da1100, 0x0081eb00, 0x31206881, 0x49d86081, 0x60089804, 
+    0x0003f994, 0xe4c0b007, 0x0000f994, 0xd0042802, 0xd0022803, 0xf7e52003, 0x4659fcab, 0xf7de4628, 
+    0xf64bfb22, 0x462831bb, 0xfb0cf7de, 0x46284641, 0xfb08f7de, 0x46286b61, 0xfb04f7de, 0x46284631, 
+    0xfb00f7de, 0x6981e009, 0x69016141, 0x980060c1, 0x90001c40, 0xf4ff2832, 0xb1c7ae24, 0x7480f04f, 
+    0x11f4f240, 0xf7de4620, 0xf64bfafe, 0x462031bd, 0xfae8f7de, 0x46204641, 0xfae4f7de, 0x462049b8, 
+    0xf7de6b49, 0x49b2fadf, 0xf7de4620, 0x48b4fadb, 0x0003f990, 0xe92de7b6, 0x4cb04ffe, 0x0a00f04f, 
+    0x52a0f04f, 0xf88d4680, 0xf88da000, 0xf9b0a004, 0xf04f1000, 0x68267080, 0xfb23f7de, 0x78e84da8, 
+    0x2000b120, 0xa030f8c5, 0x8ffee8bd, 0x20016821, 0xf42146a3, 0x602121c0, 0xf7e56328, 0x9002fff0, 
+    0xf7e52000, 0x2000ffc5, 0xab01466a, 0xf7ff4631, 0x2002fdb7, 0x48976328, 0xb1907800, 0x7480f04f, 
+    0x11f4f240, 0xf8c54620, 0xf7dea030, 0xf64ffaac, 0x462071ff, 0xfa96f7de, 0x4620498d, 0xfa92f7de, 
+    0x2003e196, 0x20966328, 0xf89d62e8, 0x28000004, 0x2005d07e, 0x78286328, 0xd07a2800, 0xf04f2006, 
+    0xab01090a, 0x4631466a, 0x20016328, 0xfd88f7ff, 0x78004880, 0xf8c5b110, 0xe179a030, 0x63282007, 
+    0xf9904880, 0x28050000, 0x2804d002, 0x2003d101, 0xf89d4681, 0x28000000, 0xf04fd07e, 0xf2407480, 
+    0x462011f4, 0xfa6ff7de, 0x0176f649, 0xf7de4620, 0x496ffa59, 0xf7de4620, 0x2400fa55, 0x4872e07e, 
+    0x28017800, 0x2802d014, 0x4870d012, 0xfc0cf009, 0x486e4607, 0xf0091c80, 0xea47fc07, 0x61a84000, 
+    0x1a416969, 0xd3134549, 0x78004869, 0xe00fb140, 0x1f004866, 0xfbf8f009, 0x48644607, 0xe7ea1e80, 
+    0x3000f44f, 0x0103f640, 0xfa3df7de, 0xfe34f7ea, 0x1f406ae8, 0xd3174284, 0x7780f04f, 0x11f4f240, 
+    0xf7de4638, 0xf246fa30, 0x46387189, 0xfa1af7de, 0x46384621, 0xfa16f7de, 0x463869a9, 0xfa12f7de, 
+    0x4638494b, 0xfa0ef7de, 0x1e406ae8, 0xe0014284, 0xe059e057, 0x2001d101, 0x210070e8, 0x4000f240, 
+    0xfabaf7e5, 0x78004843, 0xf04fb328, 0xf8857780, 0x4654a003, 0x11f4f240, 0xf88d4638, 0xf7dea000, 
+    0x4944fa02, 0xf7de4638, 0x4939f9ed, 0xf7de4638, 0x7f28f9e9, 0xe0001c40, 0xf000e017, 0xeb000007, 
+    0x48351100, 0x0081eb00, 0x31306881, 0xf8cb6081, 0x632c6000, 0x69a8e0dc, 0x61681c64, 0x42846ae8, 
+    0xaf7df4ff, 0xf7e52003, 0x78e8fb63, 0xf04fb1e0, 0xf2407480, 0x462011f4, 0xf9d5f7de, 0x41ccf64c, 
+    0xf7de4620, 0x4922f9bf, 0xf7de4620, 0x7828f9bb, 0x2143b118, 0x1000f8a8, 0x2009e006, 0x0000f8a8, 
+    0x9802e002, 0xfec4f7e5, 0x63282008, 0x280078e8, 0x7828d17e, 0xd07b2800, 0xf7e59802, 0x481cfeb9, 
+    0xb9087800, 0xff81f7ea, 0x46572002, 0xa004f885, 0xfb1df7e5, 0x9060f8df, 0x200a2208, 0x23016328, 
+    0x01514648, 0xfb6df009, 0x63282009, 0x0400f44f, 0x1e64e02c, 0xdc232c00, 0x46204c10, 0xfb3ef009, 
+    0x0140f040, 0xf0094620, 0xe026fb3c, 0x000402e8, 0xdcba01f5, 0x000402d9, 0x00043790, 0x00057ffc, 
+    0x00042fcc, 0x00040292, 0x000425f9, 0xf2036116, 0x0004257a, 0x0ddddead, 0xf2035126, 0xf000306c, 
+    0x46482301, 0x02592209, 0xfb3bf009, 0x220648f9, 0xf0092140, 0x2800fb44, 0x48f7d1cb, 0xfb14f009, 
+    0xf004b204, 0x1e490101, 0x0002f004, 0xd0524308, 0x70e82001, 0xf7e52002, 0xf04ffadb, 0xf2407980, 
+    0x464811f4, 0xf94ff7de, 0x464849ec, 0xf93af7de, 0xf00948e8, 0xea40faf9, 0x46484104, 0xf932f7de, 
+    0x464849e7, 0xf92ef7de, 0x780048e6, 0xe000b1e8, 0xf240e031, 0x464c11f4, 0x70ef4648, 0xf933f7de, 
+    0x462049e1, 0xf91ef7de, 0x462049dd, 0xf91af7de, 0x1c407f28, 0x0007f000, 0x1100eb00, 0xeb0048db, 
+    0x68810081, 0x60813130, 0x78e8e00f, 0x7828b198, 0x2043b118, 0x0000f8a8, 0x2109e002, 0x1000f8a8, 
+    0xf7e5200b, 0x48d2fa95, 0xf8cb7007, 0x632f6000, 0x0003f995, 0xf8cbe638, 0xe67c6000, 0x5ffce92d, 
+    0xf2404dcc, 0x4ecc580b, 0x8e814604, 0x4aeaf240, 0x9328f8df, 0x5b04f240, 0x45416bab, 0xf2a16837, 
+    0xd06d500b, 0xf5b1dc31, 0xd0756f9f, 0x4551dc13, 0x40eaf2a1, 0xdc07d071, 0xf5b1b331, 0xd0706f97, 
+    0x0131f110, 0xe076d16b, 0xd0592801, 0xd0672808, 0xd1642809, 0x4559e054, 0x5004f2a1, 0xdc07d07e, 
+    0x010bf110, 0x2905d04c, 0x2906d079, 0xe047d157, 0xd0452801, 0xd1522806, 0x220049ae, 0x313c4638, 
+    0xf869f004, 0xd06b1d40, 0x2818e03a, 0xdc20d038, 0xd035280c, 0x2805dc0e, 0x2806d07e, 0x280bd030, 
+    0x49a4d13d, 0x46382200, 0xf004313c, 0x1d40f854, 0xe025d073, 0xd0712811, 0xd0212812, 0xd12e2817, 
+    0x2200499c, 0x313c4638, 0xf845f004, 0xd0661d40, 0x2826e016, 0xdc0fd014, 0xd075281d, 0xd00f281e, 
+    0xd11c2825, 0x22004993, 0x0000f8d9, 0xf004313c, 0x1d40f832, 0xe003d069, 0xd0672829, 0xd10e282a, 
+    0xf04f498c, 0x6ba832ff, 0xf004313c, 0x1d01f853, 0xf240d10d, 0xe1e240b8, 0xe09de0de, 0xe08fe001, 
+    0x4984e0bb, 0x46182200, 0xf004313c, 0x1d41f843, 0x2801d03d, 0x4f7fd1e4, 0xf1a7373c, 0xf9b70114, 
+    0x280f0000, 0x283fd036, 0x2843d041, 0x2844d07a, 0x2845d079, 0x2846d078, 0xe002d077, 0xe0f1e10f, 
+    0x2848e127, 0x2849d072, 0x284ad071, 0x284cd070, 0x284dd06f, 0x2847d06e, 0x283ed06d, 0xf995d1c0, 
+    0x46381000, 0xfd57f7ff, 0xd0b92800, 0xf04f8838, 0x46390200, 0xe0032809, 0xe13ae121, 0xe168e14f, 
+    0x6ba8d079, 0xffd7f003, 0xd0751d01, 0xf240e193, 0xe19440b9, 0x91004b5f, 0x3324495e, 0xf1011f1a, 
+    0xf7ff003c, 0xe79bf9b4, 0xe179e166, 0x4959e17e, 0x1f083118, 0xe9cd1f03, 0x1f1a0100, 0x30283918, 
+    0xfa06f7ff, 0xb92088e8, 0xf7e52002, 0x2800f9a2, 0x494cd186, 0x28007808, 0x8928d182, 0x81281c40, 
+    0x70082001, 0x80382043, 0x0000f995, 0xd0012802, 0xd10b2803, 0x1c408968, 0x48498168, 0xf2487801, 
+    0xf7e50000, 0x2000f899, 0xf85cf7ff, 0x22004941, 0x313c6ba8, 0xff8ff003, 0xd1131d01, 0xa034f8a4, 
+    0x9ffce8bd, 0xe033e013, 0xe085e051, 0xe0b3e0a1, 0xe0e1e0cf, 0xe10fe0fd, 0x22004936, 0x313c4618, 
+    0xff79f003, 0xd1ae1d40, 0x40ebf240, 0x4b31e137, 0x49309100, 0x1f1a3324, 0x003cf101, 0xf942f000, 
+    0x2200492c, 0x313c6ba8, 0xff65f003, 0xd10a1d01, 0x40f2f240, 0xe109e123, 0x4926e115, 0x46182200, 
+    0xf003313c, 0x1d40ff58, 0xf240d18d, 0xe11640f3, 0x23004a20, 0x32249100, 0xf1011f11, 0xf000001c, 
+    0x491cfc07, 0x6ba82200, 0xf003313c, 0x1d01ff44, 0xf240d108, 0xe10240f8, 0x22004916, 0x313c4618, 
+    0xff39f003, 0xd1871d40, 0x40f9f240, 0x4811e0f7, 0xe9d52300, 0x303c1208, 0xfae5f001, 0x2200490d, 
+    0x313c6ba8, 0xff27f003, 0xd1201d01, 0x40fef240, 0x0000e0e5, 0xf203502c, 0xf2060040, 0x00011104, 
+    0xdcba01f5, 0x000402d9, 0x0eeedead, 0x00043790, 0x000402da, 0x00042fcc, 0x00042708, 0x0004274c, 
+    0x00040293, 0x2200496e, 0xf0034618, 0x1d40ff04, 0xf240d189, 0xe0c240ff, 0xf9954b69, 0x3b141000, 
+    0xf1a34867, 0xf0010208, 0x4965fcf9, 0x6ba82200, 0xfef1f003, 0xd1071d01, 0xb034f8a4, 0x4960e760, 
+    0x46182200, 0xfee7f003, 0xd18d1d40, 0x5005f240, 0xf995e0a5, 0x485a1000, 0xff99f001, 0x22004958, 
+    0xf0036830, 0x1d01fed8, 0xae6cf47f, 0x500af240, 0xf8a4e095, 0xe7438034, 0xf9954b51, 0x3b141000, 
+    0xf1a3484f, 0xf0010208, 0x494dffc5, 0x6ba82200, 0xfec1f003, 0xd1071d01, 0x5010f240, 0x4948e07f, 
+    0x46182200, 0xfeb7f003, 0xd1b11d40, 0x5011f240, 0xf995e075, 0x48421000, 0xfff5f001, 0x22004940, 
+    0xf0036830, 0x1d01fea8, 0xae51f47f, 0x5016f240, 0xf240e065, 0xe0625017, 0xf9954b39, 0x3b141000, 
+    0xf1a34837, 0xf0020208, 0x4935f905, 0x6ba82200, 0xfe91f003, 0xd1071d01, 0x501cf240, 0x4930e04f, 
+    0x46182200, 0xfe87f003, 0xd19e1d40, 0x501df240, 0xf995e045, 0x482a1000, 0xfbdcf002, 0x22004928, 
+    0xf0036830, 0x1d01fe78, 0xae30f47f, 0x5022f240, 0xf240e035, 0xe0325023, 0x1000f995, 0x6a2a4820, 
+    0xf9bdf002, 0x2200491e, 0xf0036ba8, 0x1d01fe64, 0xf240d107, 0xe0225028, 0x22004919, 0xf0034618, 
+    0x1d40fe5a, 0xf240d1a1, 0xe0185029, 0x0000f8d9, 0xfe51f003, 0xf47f1d01, 0xf240ae1c, 0xe00e5030, 
+    0x5031f240, 0xf240e00b, 0xe0085034, 0x2200490c, 0xf0034618, 0x1d40fe40, 0xf240d187, 0x86a05035, 
+    0x2200e6ae, 0xb5102101, 0x40eff2af, 0xfc7ef003, 0x20042108, 0xfddcf003, 0x393c4901, 0xbd106388, 
+    0x00043008, 0x4fffe92d, 0x4683b083, 0x250048ff, 0x52a0f04f, 0x9502460f, 0xf8d09c10, 0x48fca000, 
+    0x1000f9bb, 0x5980f50a, 0x88066800, 0x7080f04f, 0xfeb7f7dd, 0xf7e52000, 0xf8dffb6b, 0x230083d8, 
+    0xf24f220c, 0x46400100, 0xf814f009, 0xf6402300, 0x22087100, 0xf0094640, 0x2300f80d, 0x22044640, 
+    0xf00921f0, 0x2300f807, 0x210f4640, 0xf009461a, 0x48e9f801, 0xf0082100, 0x2200fffa, 0x23109500, 
+    0x46104611, 0xfaaef7e8, 0x700548e4, 0x780048e4, 0x7838b988, 0xd00e2803, 0x3000f44f, 0x0103f640, 
+    0xfe31f7dd, 0xfa28f7ea, 0x210048de, 0x2000f990, 0xf7e74608, 0x4ddcf8dc, 0x23002208, 0x46280151, 
+    0xffeff008, 0x0000f44f, 0x2800f240, 0xe00d9002, 0x21074ad5, 0x3254a802, 0xff53f7e4, 0xd00d2801, 
+    0x46412301, 0x46282209, 0xffdbf008, 0x220648ce, 0x38fa2140, 0xffe3f008, 0xd1e92800, 0x250148cb, 
+    0x0000f990, 0xd0012805, 0xd1002804, 0xf9972502, 0xf8df0000, 0x2803831c, 0x2802d004, 0x2804d005, 
+    0xe027d019, 0x220049c3, 0x48c3e011, 0x0000f9b0, 0xda052801, 0x220348c1, 0xf0082138, 0xb110ffc0, 
+    0x220049bf, 0x48bfe003, 0xfb052200, 0x2002f100, 0xfe50f7e4, 0xf898e00e, 0xf04f0000, 0xb3e00200, 
+    0x200249b9, 0xfe46f7e4, 0x21004ab8, 0x7080f04f, 0xfe17f7dd, 0x20022100, 0xfe06f7e4, 0xf7e42002, 
+    0x49b3fe23, 0x60084db3, 0x31fff04f, 0x60019805, 0x99062000, 0x49b06008, 0x1c406828, 0x880a6028, 
+    0x800a1c52, 0x48a0b281, 0xf0083018, 0x7828ff60, 0xf0002100, 0xeb000007, 0x48a81200, 0x0082eb00, 
+    0x20056301, 0xfe00f7e4, 0xf002682a, 0xeb010107, 0x49a21301, 0x0183eb01, 0xe012e000, 0x020de9c1, 
+    0x8800489f, 0x489f63c8, 0x64086800, 0xf8fff7e4, 0x2200489d, 0xf008213f, 0x2811ff62, 0x2001d307, 
+    0x499ae006, 0xf7e42002, 0x4a99fdf5, 0x2000e7ad, 0x23014989, 0x029d220a, 0x46298188, 0x38304882, 
+    0xff3ff008, 0x23004880, 0x4629220a, 0xf0083830, 0x4890ff38, 0xb9107800, 0xf7fe2000, 0x487bfdd3, 
+    0xf9977801, 0xf7e00000, 0x2301fe72, 0x220e488a, 0xf0080399, 0xf997ff26, 0x4f880000, 0x28024d88, 
+    0x2803d004, 0x2804d01b, 0xe0b9d063, 0xf7fb2001, 0x2100fcb4, 0xf7e52001, 0x4883ff13, 0x78394b81, 
+    0x2000f990, 0xf7fb2007, 0x2301fbcc, 0x2200487f, 0xf0084619, 0x2000ff06, 0xfb02f7fb, 0x4866e084, 
+    0x28018980, 0x487ad114, 0x23082200, 0x6000f990, 0xe9cd4610, 0x4631a900, 0xfc00f7e3, 0x23014975, 
+    0x22004875, 0x0100e9cd, 0x46184631, 0xfbf6f7e3, 0x78004872, 0xd1052801, 0xfc7ff7fb, 0x20012100, 
+    0xfedef7e5, 0x7800486e, 0xd1762801, 0xa1b4f8df, 0xf8df2600, 0x220091b4, 0xeb0a486c, 0xeb091746, 
+    0xeb001146, 0x68201346, 0xd00f1c40, 0x0012f837, 0x0012f821, 0xb2521c52, 0xdbf42a10, 0xf7e34630, 
+    0x1c76fc91, 0x2e04b276, 0xe123dbe5, 0x0012f833, 0x485fe7ee, 0x0902f04f, 0xa178f8df, 0x28017800, 
+    0xb3b8d001, 0x4850e04c, 0x78394b4e, 0x2000f990, 0xf7fb2007, 0x2301fb66, 0x2200484c, 0xf0084619, 
+    0x2000fea0, 0xfa9cf7fb, 0x0000f898, 0xd1012801, 0x9000f88a, 0x28017828, 0xf8dfd116, 0x2400a118, 
+    0x9114f8df, 0xfb042301, 0x2200f006, 0x0140eb0a, 0x0040eb09, 0x0100e9cd, 0x46184621, 0xfb8ef7e3, 
+    0xb2641c64, 0xdbed2c04, 0xf2407839, 0xf7e31000, 0xe015fcbf, 0xf898e7ff, 0x28010000, 0xf88ad101, 
+    0x483d9000, 0xb9307800, 0xf7fb2001, 0x2100fc06, 0xf7e52001, 0x7828fe65, 0x2004b1b0, 0xfa60f7fb, 
+    0x7480f04f, 0x11f4f240, 0xf7dd4620, 0xf243fc8c, 0x46203100, 0xfc76f7dd, 0xf9904830, 0x46201000, 
+    0xfc70f7dd, 0xe05d482e, 0x0000e095, 0x00040238, 0x00042618, 0xf100004c, 0xf2031034, 0x00042e74, 
+    0x0004257a, 0x00040298, 0xf2035126, 0x00040292, 0x000425e8, 0x008583b0, 0x00043020, 0xf38f007c, 
+    0x017d7840, 0x0094c5f0, 0x03b9aca0, 0xffee1234, 0x000425d0, 0x00042fe8, 0x00043018, 0x00043790, 
+    0x000425c4, 0x000402b8, 0xf2034202, 0x00bebc20, 0xffeeddcc, 0x000402d9, 0xf2030416, 0x0004232e, 
+    0x000425e5, 0x00042598, 0x0004023c, 0xf20305ae, 0x00042590, 0x00049200, 0x00048a00, 0x000425e2, 
+    0x000425e3, 0x00043580, 0x00043350, 0x00043500, 0x000425eb, 0x000425ce, 0x000425e4, 0x00042fcc, 
+    0x00040240, 0x46206801, 0xfc0cf7dd, 0x46202112, 0xfc08f7dd, 0x462049fe, 0xf7dd7809, 0x49fdfc03, 
+    0x78094620, 0xfbfef7dd, 0x780148fb, 0xf7dd4620, 0x7829fbf9, 0xf7dd4620, 0xf898fbf5, 0x46201000, 
+    0xfbf0f7dd, 0x780148f5, 0xf7dd4620, 0x48f4fbeb, 0x46207801, 0xfbe6f7dd, 0x780148f2, 0xf7dd4620, 
+    0x49f1fbe1, 0xf7dd4620, 0x2144fbdd, 0x1000f8ab, 0xe8bdb007, 0xf8df8ff0, 0x2600a3b4, 0x93b0f8df, 
+    0x48ec2200, 0x1346eb0a, 0x1146eb09, 0x1746eb00, 0x1c406820, 0xf833d017, 0xf8210012, 0x1c520012, 
+    0x2a10b252, 0x4630dbf4, 0xfb6cf7e3, 0xb2761c76, 0xdbe52e04, 0xf7fb2001, 0xf242f993, 0x064801c0, 
+    0xfbcdf7dd, 0xf837e72c, 0xe7e60012, 0x41f0e92d, 0x4ad94690, 0x68122401, 0xeb048812, 0x1ea40e52, 
+    0x0c04eb08, 0xf78cfa0f, 0x68062200, 0xc50efb02, 0x5025f853, 0xd30142b5, 0x800f6005, 0xb2121c52, 
+    0xdbf22a04, 0xb2241c64, 0xdde92c01, 0x81f0e8bd, 0x4fffe92d, 0x4688b091, 0x4dc82000, 0x52a0f04f, 
+    0x4940f649, 0x48c6900f, 0x48c3900b, 0x88046800, 0x1000f240, 0xf0f4fbb0, 0x97080867, 0x1c7f9709, 
+    0x900db240, 0xfbb4200a, 0xb200f0f0, 0x9811900a, 0x1000f9b0, 0x7080f04f, 0xfbc3f7dd, 0xf44f2100, 
+    0xf7e43080, 0xf8dffc19, 0xf99bb2dc, 0x28030000, 0x2804d00d, 0x48b4d00b, 0x0000f990, 0xd0012805, 
+    0xd1042804, 0xf44f2100, 0xf7e43000, 0x2000fc05, 0xf8452100, 0x1c401020, 0xf5b0b200, 0xdbf76f80, 
+    0x28009814, 0xf242d17e, 0x064801c0, 0xfb57f7dd, 0x0000f99b, 0x2803465e, 0x2804d001, 0x2100d11e, 
+    0x0000f248, 0xfbe8f7e4, 0xf04f48a0, 0x89800100, 0xd0072801, 0x0000f248, 0xfbdef7e4, 0x28047830, 
+    0xe006d003, 0x0000f244, 0x488ee7f6, 0x28017800, 0x4897d004, 0xb9087800, 0xf8f7f7ea, 0x01c0f242, 
+    0xf7dd0648, 0xf996fb2c, 0x46b30000, 0xd0032803, 0xd0012802, 0xd1612804, 0xf008488e, 0xb206fcc5, 
+    0x0000f99b, 0xd0082803, 0xd0022802, 0xd0042804, 0x4889e007, 0x28126800, 0x2100d203, 0x3080f44f, 
+    0x2100e002, 0x3000f44f, 0xfba6f7e4, 0xd5120770, 0x70fbf64f, 0x0100ea06, 0xf008487e, 0x487afca8, 
+    0x28037800, 0xf89bd107, 0x28020000, 0x2100d103, 0xf7e40400, 0x4e77fb91, 0xf0084630, 0xb201fc95, 
+    0xd5050608, 0x707ff64f, 0x46304001, 0xfc8ff008, 0xf0084630, 0xb201fc89, 0xd50e04c8, 0x70fff64e, 
+    0xe0004001, 0x4630e009, 0xfc81f008, 0x20012100, 0xfedcf7f6, 0xf7f62000, 0xf99bfcaf, 0x28020000, 
+    0x2804d005, 0x4857d10a, 0x28017800, 0xf7e6d106, 0xb200fdd7, 0x2008900e, 0xfdccf7e6, 0x01c0f242, 
+    0xf7dd0648, 0x4857fabc, 0x28047800, 0xf8dfd120, 0x2600b16c, 0x2e00e018, 0x4858dd16, 0xfbd1f7e6, 
+    0x2000f8db, 0x454a4658, 0x6842d209, 0xd206454a, 0x454a6882, 0xf8dbd203, 0x4549100c, 0x2100d308, 
+    0x3080f44f, 0xfb38f7e4, 0xb2361c76, 0xdbe22e0a, 0xf04fb220, 0x90060b00, 0x0900f04f, 0x01c0f242, 
+    0xf7dd0648, 0x2301fa8c, 0x21059806, 0xe88d029a, 0x4843000f, 0x23001f8a, 0x68002108, 0xf85af7fa, 
+    0x493f2600, 0xfb064622, 0x6809f004, 0x0040eb01, 0x68094931, 0x3080f9b1, 0xf008493a, 0x482efbe0, 
+    0x4a3a4b39, 0x78816800, 0x0094f8d0, 0x0100e9cd, 0x990f4834, 0xfd38f008, 0xe0b0f8df, 0xe0172000, 
+    0xf8514932, 0x49303020, 0x1020f851, 0x1201fb81, 0x1203fbc3, 0x0307fb06, 0x1204e9ce, 0xf8550d89, 
+    0xea41c023, 0x1c402182, 0xb2004461, 0x1023f845, 0xdbe542b8, 0xf007fb06, 0x2200491a, 0x2020f845, 
+    0x1000f991, 0xd0012902, 0xd1032905, 0x0154eb00, 0x2021f845, 0x6809991e, 0x0f94ebb1, 0xeb00d103, 
+    0xf8450094, 0x1c762020, 0x2e04b276, 0xe02fdba9, 0x000425e2, 0x000425e3, 0x000425e4, 0x000425e9, 
+    0x000425ea, 0x000425eb, 0xdcba01f5, 0x00043580, 0x00043350, 0x00043500, 0x00042618, 0x00040300, 
+    0x00041300, 0x00042fcc, 0x00040292, 0x00043020, 0x0004257a, 0xf23c80b8, 0x00040240, 0x000434e0, 
+    0x0004022c, 0x00049a00, 0x0004d200, 0x0004c200, 0x0001f109, 0xf980fa0f, 0x0f02f1b9, 0xaf5ef6ff, 
+    0x0f00f1bb, 0xa80cd10d, 0xab05990b, 0xaa079000, 0xf7fe4628, 0xf9bdfaf8, 0x49fd0030, 0xf0f7fb90, 
+    0xf10b8148, 0xfa0f0001, 0xf1bbfb80, 0xf6ff0f01, 0xf242af43, 0x064801c0, 0xf9d1f7dd, 0xf99048f5, 
+    0x28020000, 0x2804d005, 0x48f3d107, 0x28017800, 0x980ed103, 0xf7e6b2c0, 0x4eedfccd, 0xf04f2000, 
+    0x90047980, 0xf2401e40, 0x80b011f4, 0xf7dd4648, 0xf240f9aa, 0x46487171, 0xf994f7dd, 0x1000f9b6, 
+    0xf7dd4648, 0x49e5f98f, 0xf7dd4648, 0x9814f98b, 0x48e3bbf0, 0xbbd87800, 0xf99048de, 0x28020000, 
+    0x2804d006, 0x48dcd134, 0xb9087800, 0xfd84f7e9, 0x7b80f04f, 0x11f4f240, 0xf7dd4658, 0xf641f984, 
+    0x46581199, 0xf96ef7dd, 0x46584ed6, 0x1000f996, 0xf968f7dd, 0x1030f9bd, 0xf7dd4658, 0xf8dff963, 
+    0x46589330, 0x100af9b9, 0xf95cf7dd, 0x1000f996, 0x000af9b9, 0xd1654281, 0xb01cf8dd, 0x0900f04f, 
+    0xf9bd464e, 0xfb060014, 0xf8550007, 0xe0001020, 0xf04fe05d, 0xf7dd7080, 0xf9bdf945, 0xfb060014, 
+    0xf8550007, 0x45580020, 0x4683da01, 0x1c7646b1, 0x2e04b276, 0xf8dfdbe5, 0xf89bb2dc, 0x28040000, 
+    0xf1b9d10a, 0xd0030f00, 0x0f03f1b9, 0xe003d002, 0xe0002001, 0x46812002, 0x7080f04f, 0xf7dd4649, 
+    0xf9bdf921, 0xf04f1014, 0xf7dd7080, 0xf7e9f91b, 0x4eacfe7b, 0x1402b201, 0xf8864610, 0xf7e99000, 
+    0x49a9fd9c, 0x70082001, 0xf7e92002, 0xf996ffba, 0xf7e90000, 0xf996fcf1, 0xf7e90000, 0xf996fd31, 
+    0xf7e90000, 0xf996fd7c, 0xf04f1000, 0xf7dd7080, 0xf89bf8f9, 0x28040000, 0x4897d104, 0xb9087800, 
+    0xfed3f7e9, 0xf04f4995, 0xf7dd7080, 0xf8dff8eb, 0xf8b99240, 0xbbe80000, 0x0014f9bd, 0xf1092603, 
+    0x462b0104, 0xf0f6fb90, 0xa804b202, 0xfd2ef7ff, 0x0014f9bd, 0x7b80f04f, 0x11f4f240, 0xfb901a20, 
+    0xfa0ff0f6, 0x4658fa80, 0xf8ddf7dd, 0x4101f244, 0xf7dd4658, 0x4651f8c7, 0xf7dd4658, 0xf9b9f8c3, 
+    0x464e1004, 0xf7dd4658, 0x497cf8bd, 0xf7dd4658, 0xf9bdf8b9, 0xebaa1014, 0x1d000001, 0xd9052808, 
+    0x462b1d31, 0x4652a804, 0xfd00f7ff, 0xf8dd88b0, 0xe000a010, 0x8130e01c, 0xf9bd462b, 0x496c0014, 
+    0x70d0eb00, 0x10421d09, 0xf7ffa804, 0xf9bdfcef, 0x1a601014, 0x70d0eb00, 0xb2021040, 0x1d001a50, 
+    0xd9052808, 0xa8044962, 0x1d09462b, 0xfcdef7ff, 0x1004f9b9, 0x4281980a, 0x2000da04, 0x1e409004, 
+    0x0004f8a9, 0x0014f9bd, 0x0b01f04f, 0xb20e0041, 0x0194eb0b, 0xdc034281, 0xeb044241, 0xb20e0141, 
+    0xdc06287d, 0xa8044952, 0x4632462b, 0xf7ff1d09, 0x9804fcbd, 0xf9bd9000, 0x96020014, 0xeb00282b, 
+    0xb20a0140, 0xeba0db03, 0x44210180, 0x2845b20a, 0xebb0dc08, 0xd0050f94, 0xa8044945, 0x1d09462b, 
+    0xfca4f7ff, 0x7080f04f, 0x11f4f240, 0xf85bf7dd, 0x7080f04f, 0x7177f240, 0xf844f7dd, 0x68014843, 
+    0x7080f04f, 0xf83ef7dd, 0x1014f9bd, 0x7080f04f, 0xf838f7dd, 0x0a019807, 0x7080f04f, 0xf832f7dd, 
+    0xf04f4e36, 0x46317080, 0xf82cf7dd, 0x7080f04f, 0x11f4f240, 0xf837f7dd, 0x7080f04f, 0x51ddf64d, 
+    0xf820f7dd, 0x7801482e, 0x7080f04f, 0xf81af7dd, 0x7080f04f, 0xf7dd4631, 0x482cf815, 0x4e252100, 
+    0xf0007800, 0xeb000007, 0x48291200, 0x0082eb00, 0x610160c1, 0xf9bd6141, 0xf8c0e014, 0xf9bde01c, 
+    0x62022030, 0x0a5a9b07, 0x62416182, 0x900108a0, 0x0000f8c8, 0x60019813, 0x1002f8a9, 0x1006f8a9, 
+    0x0000f996, 0xd0352803, 0xd0332804, 0x28032104, 0x2804d032, 0x260ad030, 0xc034f8dd, 0xfc0cfb11, 
+    0xebbc990d, 0xf8cd2f53, 0xfb16c018, 0xb209f101, 0xf8c8d22f, 0x2803e000, 0x601a9b13, 0x2804d01f, 
+    0x9804d01d, 0x2f10ebb1, 0xf8a9d87c, 0xe079b002, 0x00043020, 0x00042fcc, 0x000425eb, 0xdcba01f5, 
+    0x0004257a, 0x00040298, 0x00040296, 0x00042fe8, 0x00043790, 0xe7ca2132, 0x16f4f240, 0x9804e7cc, 
+    0x2f10ebb1, 0xf9b9d85e, 0x990a2004, 0xdadc428a, 0x2803e058, 0x2804d02d, 0xf04fd02b, 0xf2407080, 
+    0xf7dc11f4, 0xf04fffb0, 0xf6487080, 0xf7dc0180, 0x4efeff99, 0x7080f04f, 0xf7dc6831, 0x48fcff93, 
+    0xf04f7801, 0xf7dc7080, 0xf8d8ff8d, 0xf04f1000, 0xf7dc7080, 0x49f7ff87, 0x7080f04f, 0xff82f7dc, 
+    0x28016830, 0x48f2db15, 0x282b7800, 0x9808d811, 0x981ee011, 0x1c416800, 0x2880d007, 0xf8c8d005, 
+    0x99080000, 0x1004f8a9, 0x9908e79f, 0x1000f8c8, 0xf04fe018, 0xf24030ff, 0xf04f11f4, 0xf8c87680, 
+    0x46300000, 0xff6ff7dc, 0x1000f8d8, 0xf7dc4630, 0x49e0ff59, 0xf7dc4630, 0x2100ff55, 0x1002f8a9, 
+    0x1006f8a9, 0x680048dc, 0xd3752812, 0x1014f9bd, 0x0f94ebb1, 0xf8b9d107, 0x46482002, 0x9a08b91a, 
+    0xf8a98082, 0x48d5b002, 0x0000f990, 0xd0012803, 0xd1102804, 0x0f54ebb1, 0xf04fd005, 0xeb0232ff, 
+    0x428a0254, 0xf8b9d107, 0x464a3002, 0x9b01b91b, 0xf8a98093, 0x9a0ab002, 0xdc024291, 0xf8a92100, 
+    0x28031002, 0x2804d001, 0xf8b9d108, 0x46492002, 0x9a1eb922, 0x808a8812, 0xb002f8a9, 0xf9b9464e, 
+    0xf9b91008, 0x42912004, 0x8872d036, 0x2803bba2, 0x2804d060, 0xea5fd05e, 0xd02d205a, 0x4281980a, 
+    0xf04fdb2a, 0xf2407080, 0xf8a611f4, 0xf7dcb006, 0xf04fff0a, 0xf2457080, 0xf7dc5122, 0xf9b6fef3, 
+    0xf04f1006, 0xf7dc7080, 0xea4ffeed, 0xf04f215a, 0xf7dc7080, 0xf9b6fee7, 0xf04f1004, 0xf7dc7080, 
+    0xf9b6fee1, 0xf04f1008, 0xf7dc7080, 0x49a1fedb, 0x7080f04f, 0xfed6f7dc, 0xb3a89814, 0x70d0f240, 
+    0x26009001, 0xf04f1081, 0xf7dc7080, 0xf04ffedc, 0xf2437080, 0xf7dc3111, 0xf04ffec5, 0xf2407080, 
+    0xf7dc71d0, 0x4892febf, 0xf04f7801, 0xf7dc7080, 0xf04ffeb9, 0xf2407080, 0xf7dc71d0, 0x498dfeb3, 
+    0x7080f04f, 0xfeaef7dc, 0x0014f9bd, 0xdb0c2819, 0xe00d9901, 0xebb22205, 0xd8cd2f5a, 0x4281980a, 
+    0xf8a9dbca, 0xe7c7b006, 0xf640e09a, 0x910171a0, 0xc01cf8dd, 0x2f5cebb1, 0x2103d225, 0x0308f1a7, 
+    0xdc0b4298, 0x200af9b9, 0x0e01eb00, 0xee07fb02, 0xf8529a0b, 0x42b2202e, 0x4616db00, 0x0f54ebb0, 
+    0xebb0d002, 0xd10a0f94, 0x200af9b9, 0x1e07fb02, 0xeb029a0b, 0x6c92028e, 0xdb0042b2, 0x1c894616, 
+    0x2907b209, 0x2100dddc, 0x0f54ebb0, 0xebb0d002, 0xd1000f94, 0xf9b92102, 0x1d49200a, 0x0207fb02, 
+    0x2022f855, 0x42b2410a, 0x9901db03, 0x2f5cebb1, 0x9a13d302, 0x60112100, 0x4c612100, 0x9a137021, 
+    0x2a006812, 0x381cdd07, 0xd8042808, 0x7800485d, 0xf884b908, 0x9804b000, 0x980d0a42, 0x0340eb00, 
+    0x10c0ebc3, 0x1f00ebb2, 0xf8a9d801, 0xea4f1002, 0xebb2225a, 0xd8011f00, 0x1006f8a9, 0x7780f04f, 
+    0x11f4f240, 0xf7dc4638, 0xf241fe3e, 0x46381122, 0xfe28f7dc, 0x1000f994, 0xf7dc4638, 0x9901fe23, 
+    0xf7dc4638, 0x9807fe1f, 0x46380a41, 0xfe1af7dc, 0x1014f9bd, 0xf7dc4638, 0x4631fe15, 0xf7dc4638, 
+    0xf9b9fe11, 0x464c1002, 0xf7dc4638, 0xf9b4fe0b, 0x46381006, 0xfe06f7dc, 0x46384936, 0xfe02f7dc, 
+    0x0106e9dd, 0x2f51ebb0, 0xf04fd342, 0xf2407480, 0x462011f4, 0xfe07f7dc, 0x0181f648, 0xf7dc4620, 
+    0x4e2afdf1, 0x68314620, 0xfdecf7dc, 0x46204f28, 0xf7dc7839, 0xf8d8fde7, 0x46201000, 0xfde2f7dc, 
+    0x46204924, 0xfddef7dc, 0x28016830, 0x7838db04, 0xd801282b, 0xe0019808, 0x30fff04f, 0x11f4f240, 
+    0x0000f8c8, 0xf7dc4620, 0xf8d8fdde, 0x46201000, 0xfdc8f7dc, 0x6801981e, 0xf7dc4620, 0x4915fdc3, 
+    0xf7dc4620, 0x2000fdbf, 0x0002f8a9, 0x0006f8a9, 0x6801981e, 0x0000f8d8, 0xd1764281, 0xd0741c41, 
+    0xd0722880, 0x0000f8b9, 0x4909464c, 0xb2001c40, 0x0000f8a9, 0x29467809, 0x2802d320, 0x8863db1c, 
+    0xd1192b01, 0x2a0188e2, 0xe00dd116, 0x00042fe8, 0x0004257c, 0xdcba01f5, 0x00040240, 0x00042fcc, 
+    0x00043011, 0x0004257a, 0xf04f9b04, 0x45530200, 0x80e2d301, 0x8062e000, 0xd8492946, 0xdb472801, 
+    0x22329800, 0x2f50ebb2, 0x8861d20d, 0xf9b4b959, 0x46203004, 0x428b990a, 0xf8a0db05, 0x9902b002, 
+    0x980080a1, 0x98009004, 0x2f50ebb2, 0x88e0d230, 0xf9b4bb48, 0x980a1004, 0xdb294281, 0xb006f8a4, 
+    0x7680f04f, 0xf2409802, 0x812011f4, 0xf8dd4630, 0xf7dca000, 0xf245fd68, 0x46305111, 0xfd52f7dc, 
+    0x1006f9b4, 0xf7dc4630, 0xea4ffd4d, 0x4630215a, 0xfd48f7dc, 0x1008f9b4, 0xf7dc4630, 0x49f7fd43, 
+    0xf7dc4630, 0xe003fd3f, 0x2000e7ff, 0x0000f8a9, 0xbbe09814, 0x90002000, 0xa8029001, 0xff13f7e5, 
+    0x0000f8d8, 0xd0281c40, 0x466f2600, 0xf8d84634, 0x9a0b0000, 0xf8551981, 0xf8520021, 0x42881021, 
+    0x1a40db10, 0x1080ebc0, 0xf7e50840, 0xa902ff62, 0xf9314ae3, 0xf1c11014, 0xf832011f, 0x43411011, 
+    0xe0000b88, 0xf8272000, 0x98090014, 0xb2241c64, 0x1c404430, 0x2c04b206, 0xf8bddbd9, 0x48d91000, 
+    0xfec5f007, 0xf8bd48d7, 0x1c801002, 0xe00de000, 0xfebdf007, 0xf8bd48d3, 0x1d001004, 0xfeb7f007, 
+    0xf8bd48d0, 0x1d801006, 0xfeb1f007, 0x7680f04f, 0x15f4f240, 0x46304629, 0xfcf5f7dc, 0x2122f240, 
+    0xf7dc4630, 0x981efcdf, 0x46306801, 0xfcdaf7dc, 0x1000f8d8, 0xf7dc4630, 0x9807fcd5, 0x46300a01, 
+    0xfcd0f7dc, 0x1002f9b9, 0x4630464c, 0xfccaf7dc, 0x1004f9b4, 0xf7dc4630, 0x9804fcc5, 0x46300a01, 
+    0xfcc0f7dc, 0x1006f9b4, 0xf7dc4630, 0xf9b4fcbb, 0x46301008, 0xfcb6f7dc, 0x211aea4f, 0xf7dc4630, 
+    0x4caefcb1, 0x46214630, 0xfcacf7dc, 0x46304629, 0xfcb9f7dc, 0x51ddf64d, 0xf7dc4630, 0x48aafca3, 
+    0x46307801, 0xfc9ef7dc, 0x46304621, 0xfc9af7dc, 0x01c0f242, 0xf7dc0648, 0x9811fcb2, 0x80012145, 
+    0xe8bdb015, 0xe92d8ff0, 0xb0854ff0, 0x20004683, 0x4688461e, 0x489d9002, 0x489d6805, 0x28017800, 
+    0x247fd016, 0x2101489b, 0x52a0f04f, 0xf8b06800, 0xeb019000, 0x210a0a59, 0xf0f1fbb9, 0x9003b200, 
+    0x1000f9bb, 0x7080f04f, 0xfccbf7dc, 0xe024b116, 0xe7e724ff, 0xf9904890, 0x28030000, 0x2804d01d, 
+    0x488ed103, 0x28017800, 0x488dd017, 0x28166800, 0x2100d204, 0x3000f44f, 0xfd0ef7e3, 0x4b89488a, 
+    0x2000f990, 0x78014889, 0xf7fa2000, 0x2300faea, 0x21014887, 0xf007461a, 0x4886fe24, 0xf0084649, 
+    0x487dfdff, 0x78002700, 0xd0052803, 0x49822004, 0xeb019004, 0xe1720688, 0xe7f82001, 0x7800487f, 
+    0xf04f2806, 0xd3100000, 0x4b7b497d, 0x2287eb01, 0xf852e005, 0xf8431020, 0x1c401020, 0x4550b200, 
+    0x4878dbf7, 0x0027f850, 0x4977e00b, 0xe0054b72, 0x2020f851, 0x2020f843, 0xb2001c40, 0xdbf74550, 
+    0xf8566808, 0x4a6c1c08, 0x0fe0ebb1, 0x10c1dd00, 0x1c08f846, 0x1c04f856, 0x0fa0ebb1, 0x1081dd00, 
+    0x1c04f846, 0x0028f842, 0xebb16871, 0xdd000fa0, 0x60711081, 0xebb168b1, 0xdd000fe0, 0x60b110c1, 
+    0x68094957, 0xd3362912, 0x3b184b5f, 0x29018859, 0xf9b3d117, 0xf8dfe004, 0xeb0cc160, 0xf851018e, 
+    0xebb22c04, 0xdd000fa0, 0xf8411082, 0x10822c04, 0x202ef84c, 0xc004f8d1, 0x0fa0ebbc, 0x4662dc00, 
+    0x88d9604a, 0xd1162901, 0x3008f9b3, 0xc128f8df, 0x0183eb0c, 0x2c04f851, 0x0fa0ebb2, 0x1082dd00, 
+    0x2c04f841, 0xf84c1082, 0x684b2023, 0x0fa0ebb3, 0x461adc00, 0xf1a8604a, 0x280a001a, 0x4842d918, 
+    0xf9b03818, 0x391a1004, 0xd802290a, 0x29018841, 0xf9b0d00e, 0x391c1008, 0xd8022908, 0x280188c0, 
+    0x483ad006, 0x70012100, 0x3ffff1b8, 0xe006d004, 0x20014936, 0xe7f77008, 0x21024834, 0xfa0f7001, 
+    0x492df08a, 0xeba9e007, 0xf8510200, 0xf8412022, 0x1c402020, 0x4548b200, 0x481edbf5, 0x9b024a2c, 
+    0x78816800, 0x0094f8d0, 0x0100e9cd, 0x48224921, 0xf954f008, 0xf04f4926, 0xe00a5200, 0x2000b1e0, 
+    0x3020f851, 0xf841005b, 0x1c403020, 0x2811b200, 0x6808dbf6, 0xddf14290, 0x4380f04f, 0x42986808, 
+    0x2000dd38, 0x2020f851, 0xf8411052, 0x1c402020, 0x2811b200, 0xe7f1dbf6, 0x0000e02c, 0xdcba01f5, 
+    0x00042e76, 0xf2035154, 0x0004257a, 0x00040238, 0x0004230e, 0x00042618, 0x00042fcc, 0x000425eb, 
+    0x00040240, 0x00042598, 0x0004023c, 0x0004232e, 0xf20305ae, 0x0004d200, 0x0004c200, 0x0004257c, 
+    0x00047a00, 0x000439f0, 0x00043038, 0x00043010, 0x00049a00, 0xf8512000, 0xf1022020, 0xf8415200, 
+    0x1c402020, 0x2811b200, 0x48ffdbf5, 0x1107eb07, 0xeb002210, 0x48fd0181, 0xf7f29100, 0x2000f923, 
+    0x99004262, 0x1020f851, 0x7180f501, 0x214ff341, 0xf82542a1, 0xdd001010, 0x42914621, 0x1010f825, 
+    0x4611da00, 0x1010f825, 0xb2001c40, 0xdde82810, 0x46012000, 0x3010f835, 0xb2001c40, 0xb2094419, 
+    0xdbf72811, 0x45989b03, 0x8c28db02, 0x84281a40, 0xfa0f49e7, 0x2000fc82, 0x1147eb01, 0x0340eb05, 
+    0x3002f9b3, 0xdd0242a3, 0x4010f821, 0x4293e006, 0xf821da02, 0xe001c010, 0x3010f821, 0xb2001c40, 
+    0xdbeb2810, 0x210148db, 0x1c7f4adb, 0x7800b27f, 0x0007f000, 0x1000eb00, 0x0080eb02, 0x98046241, 
+    0xf6ff4287, 0x48d5ae8b, 0xb9988800, 0x21004fd4, 0x20004ecf, 0x1341eb07, 0x1241eb06, 0xc010f832, 
+    0xc010f823, 0xb2001c40, 0xdbf72810, 0xb2491c49, 0xdbee2904, 0x832cf8df, 0x932cf8df, 0x0000f998, 
+    0xd0052803, 0xd1212804, 0x0000f899, 0xd11d2801, 0x22014fbf, 0x42662000, 0x1142eb07, 0x0340eb05, 
+    0x3002f9b3, 0xdd0242a3, 0x4010f821, 0x42b3e006, 0xf821da02, 0xe0016010, 0x3010f821, 0xb2001c40, 
+    0xdbeb2810, 0xb2521c52, 0xdbe32a04, 0x7480f04f, 0x11f4f240, 0xf7dc4620, 0xf64dfa86, 0x462051dd, 
+    0xfa70f7dc, 0x462049b1, 0xf7dc7809, 0x49b0fa6b, 0xf7dc4620, 0xf242fa67, 0x064801c0, 0xfa7ff7dc, 
+    0x0000f998, 0x28022146, 0x2803d004, 0x2804d006, 0xe00fd00a, 0x1000f8ab, 0xe5c2b005, 0x780048a5, 
+    0xd1f72800, 0xe7f52149, 0x0000f899, 0xd0f12800, 0xd0012801, 0xe7ed210f, 0xe7eb214c, 0x4fffe92d, 
+    0xb087489d, 0x461f2600, 0xf04f4615, 0x680052a0, 0x20018804, 0x0a54eb00, 0xf9b09807, 0xf04f1000, 
+    0xf7dc7080, 0xf242fa8e, 0x064801c0, 0xfa47f7dc, 0x60386828, 0x48916829, 0xd0041c4a, 0x32c8f44f, 
+    0x0c094351, 0xf64fe001, 0xf00771ff, 0xf04ffbe0, 0xf2407880, 0x464011f4, 0xfa25f7dc, 0x3133f243, 
+    0xf7dc4640, 0x6839fa0f, 0xf7dc4640, 0x6829fa0b, 0xf7dc4640, 0x4879fa07, 0x100cf9b0, 0xf7dc4640, 
+    0x487ffa01, 0x213f2200, 0xfbe9f007, 0x46404601, 0xf9f8f7dc, 0x7801487b, 0xf7dc4640, 0x4974f9f3, 
+    0xf7dc4640, 0xf8dff9ef, 0xf8dfb1bc, 0xf89b81c0, 0x28020000, 0x4874d108, 0x28126800, 0x4874d30d, 
+    0x68004972, 0xfa9ef7e3, 0x0000f89b, 0xd1042804, 0x0000f898, 0xf7e8b908, 0xf8dffddf, 0x25009174, 
+    0x2000496c, 0x1245eb09, 0x1345eb01, 0xeb01496a, 0xf8d71145, 0xf1bcc000, 0xd0153fff, 0xc010f832, 
+    0xc010f821, 0xb2401c40, 0xdbf22810, 0xf7e24628, 0x1c6df969, 0x2d04b26d, 0x4852dbe2, 0xb17cf8df, 
+    0x28047800, 0xe006d003, 0xc010f833, 0xf89be7e8, 0x28010000, 0x2001d002, 0xff82f7f9, 0x01c0f242, 
+    0xf7dc0648, 0x4856f9bc, 0xf9902300, 0x20015000, 0x48509000, 0x1245eb00, 0xeb00484f, 0x46281145, 
+    0xf9faf7e2, 0x20004f4f, 0x1245eb09, 0xeb07464b, 0xf8321145, 0xf8215010, 0x1c405010, 0x2810b240, 
+    0x4838dbf7, 0x28047800, 0xf89bd103, 0x28010000, 0xf898d004, 0xb9080000, 0xff57f7e8, 0x27012500, 
+    0xf990483f, 0x42850000, 0x483ad018, 0x97002300, 0x1245eb00, 0xeb004838, 0x46281145, 0xf9ccf7e2, 
+    0x20004a38, 0x1145eb09, 0x1245eb02, 0x3010f831, 0x3010f822, 0xb2401c40, 0xdbf72810, 0xb26d1c6d, 
+    0xdbdd2d04, 0x492c4830, 0x0000f990, 0xf911f7e2, 0x21044a2e, 0xf0074828, 0x4d1af9df, 0x28047828, 
+    0xf89bd103, 0x28010000, 0xf898d012, 0xb9180000, 0x70074827, 0xfb8bf7f9, 0x70074826, 0xfd37f7f9, 
+    0x22034825, 0xf0072138, 0xb108fb1a, 0xf917f7e3, 0x09c0f242, 0x4000f04f, 0xf7dc4649, 0x7828f940, 
+    0xd17d2804, 0x0000e03a, 0x00043680, 0x00049a00, 0x00043580, 0x00042fe8, 0x00043790, 0x00043020, 
+    0x0004e9b4, 0x00042fcc, 0x000425e5, 0x0004257a, 0xdcba01f5, 0x000425e3, 0x00042618, 0xf203513c, 
+    0xf2034202, 0x0004257c, 0x00040240, 0x00167fc4, 0x000425d0, 0x00043500, 0x00043350, 0x000425eb, 
+    0x00040298, 0x00043600, 0x00042590, 0x000433d0, 0x00040296, 0x00040297, 0xf38f007c, 0x0000f89b, 
+    0xd1572801, 0xf2400600, 0xf7dc11f4, 0xf04ff8ec, 0xf64a7080, 0xf7dc21aa, 0x49aef8d5, 0x7080f04f, 
+    0xf8d0f7dc, 0x4000f04f, 0xf7dc4649, 0x48abf8e8, 0x680049a9, 0xf986f7e3, 0x7080f04f, 0x11f4f240, 
+    0xf8d1f7dc, 0x7080f04f, 0x21aaf64a, 0xf8baf7dc, 0xf04f49a0, 0xf7dc7080, 0xf04ff8b5, 0x46494000, 
+    0xf8cdf7dc, 0xf7f92001, 0x489efe8b, 0xf9904b9c, 0x489d2000, 0x20007801, 0xff43f7f9, 0xe0002300, 
+    0x489ae065, 0x461a2101, 0xfa7bf007, 0x78004898, 0xd1022801, 0xf7fa2003, 0xf04ff852, 0x46494000, 
+    0xf8adf7dc, 0x0000f898, 0xf7e8b908, 0x7828fe6e, 0xd14c2804, 0x0000f89b, 0x2100b9b0, 0x2000f44f, 
+    0xf93af7e3, 0xf44f2100, 0xf7e32000, 0x2100f935, 0x2000f44f, 0xf930f7e3, 0xf44f2100, 0xf7e32000, 
+    0x7828f92b, 0xd1322804, 0x0000f89b, 0xd12e2801, 0x04c02100, 0xf920f7e3, 0x4b00f04f, 0x46584649, 
+    0xf87df7dc, 0xf44f2100, 0xf7e32000, 0x4649f915, 0xf7dc4658, 0x2100f874, 0x2000f44f, 0xf90cf7e3, 
+    0x46584649, 0xf86bf7dc, 0x0000f898, 0x4871b918, 0xf7f97007, 0x4870fa9c, 0xf7f97007, 0x486ffc48, 
+    0x21382203, 0xfa2bf007, 0xf7e3b108, 0xf04ff828, 0x46494b00, 0xf7dc4658, 0xf995f852, 0x210e0000, 
+    0xd0162803, 0xd0142804, 0x91002301, 0x9604220e, 0x96050218, 0x7602e9cd, 0x46119101, 0xff4ef7e3, 
+    0x46584649, 0xf83bf7dc, 0x7800485d, 0xd00b2803, 0x220ee017, 0x23019100, 0x20809604, 0xe9cd9605, 
+    0x91017602, 0xe7e94611, 0x9000200f, 0x46022301, 0x7602e9cd, 0x96044601, 0x90019605, 0xf7e30258, 
+    0x4649ff2d, 0xf7dc4658, 0x484ef81a, 0xf939f7e5, 0x494c484d, 0x0000f990, 0x0020f851, 0x3fc0f5b0, 
+    0x4649d931, 0xf7dc4658, 0x4f48f80a, 0xf8df2000, 0x4e48c120, 0xe0154a48, 0x1010f837, 0x1010f82c, 
+    0x0140eb07, 0x3200f8b1, 0xf82c1901, 0xf8363011, 0xf8223010, 0xeb063010, 0x1c400340, 0x3200f8b3, 
+    0x3011f822, 0xdbe74550, 0x46584649, 0xffe7f7db, 0x6800483a, 0xf240b138, 0x4b3931a6, 0x2000f898, 
+    0xf7e31e48, 0x2301f8ab, 0x4619220f, 0xf7e34610, 0x4834ffb4, 0x0000f9b0, 0xdb1e2801, 0xb2462805, 
+    0x2605db00, 0x0000f995, 0xd0162803, 0xd0142804, 0x24004f2d, 0x3500f44f, 0x7839e00d, 0xf7e34628, 
+    0x2100f85b, 0xf7e34628, 0x2100f857, 0xf7e34628, 0x1c64f853, 0x42b4b264, 0x4649dbef, 0xf7db4658, 
+    0x9807ffae, 0x80012148, 0xe8bdb00b, 0x4a1f8ff0, 0xb5102101, 0x70114604, 0xff81f7ed, 0x2104481c, 
+    0x200a8001, 0xf2428020, 0xe8bd01c0, 0x07804010, 0xbf95f7db, 0xdcba01f5, 0x00393870, 0x000425d0, 
+    0x00042598, 0x0004023c, 0x0004232e, 0xf20305ae, 0x000425e4, 0x00040296, 0x00040297, 0xf38f007c, 
+    0x00040292, 0x000434e0, 0x00042590, 0x00046a00, 0x00048a00, 0x00047200, 0x00049200, 0x00057f70, 
+    0xf23c80ba, 0x00043020, 0x00040293, 0x00040253, 0x00042702, 0x47f0e92d, 0x7780f04f, 0x1000f9b0, 
+    0x4614461d, 0x52a0f04f, 0x46384606, 0xff99f7db, 0x4900f04f, 0x08c0f242, 0x46484641, 0xff4ff7db, 
+    0x60286820, 0x4a9c6820, 0xd0041c41, 0x31c8f44f, 0x0c014348, 0xf64fe001, 0x461071ff, 0xf8e7f007, 
+    0x11f4f240, 0xf7db4638, 0xf243ff2e, 0x46383133, 0xff18f7db, 0x46386829, 0xff14f7db, 0x46386821, 
+    0xff10f7db, 0x4638498d, 0xff0cf7db, 0x498c488d, 0xf7e26800, 0x4641ffc7, 0xf7db4648, 0x2048ff20, 
+    0xe8bd8030, 0xe92d87f0, 0xf04f4ff0, 0xf9b07580, 0x24001000, 0xb0874628, 0x52a0f04f, 0xff51f7db, 
+    0x11f4f240, 0xf7db4628, 0xf649fefe, 0x46280177, 0xfee8f7db, 0x4628497c, 0x1000f9b1, 0xfee2f7db, 
+    0x46284976, 0xfedef7db, 0x91e0f8df, 0xf8994d78, 0xb9680000, 0x3000f44f, 0x0103f640, 0xfee3f7db, 
+    0xfadaf7e8, 0xf9952100, 0x46082000, 0xf98ff7e5, 0xf99546a8, 0xf8df5000, 0x2001a1bc, 0xb1b8f8df, 
+    0xeb0a2300, 0x90001245, 0x1145eb0b, 0xf7e14628, 0x4e6aff23, 0x4f6a2000, 0x1345eb06, 0x1145eb07, 
+    0x2010f833, 0x2010f821, 0xb2001c40, 0xdbf72810, 0x0000f899, 0xf7e8b908, 0x2500fc88, 0x260146b2, 
+    0x0000f998, 0xd0164285, 0x2300485a, 0x1145eb0b, 0xeb009600, 0x46281245, 0xfefef7e1, 0xeb0a2000, 
+    0xeb071145, 0xf8311245, 0xf8223010, 0x1c403010, 0x2810b200, 0x1c6ddbf7, 0x2d04b26d, 0xf04fdbe0, 
+    0xf2424a00, 0x463907c0, 0xf7db4650, 0x250efe98, 0x1b00f240, 0x23019500, 0x6402e9cd, 0x4629462a, 
+    0x94044658, 0x94059501, 0xfd98f7e3, 0x46504639, 0xfe85f7db, 0x78004843, 0xd11f2804, 0x9500220e, 
+    0x46112301, 0x6402e9cd, 0x94044658, 0x94059501, 0xfd84f7e3, 0x46504639, 0xfe71f7db, 0x9500220e, 
+    0x46112301, 0x6402e9cd, 0x94044658, 0x94059501, 0xfd74f7e3, 0x46504639, 0xfe61f7db, 0x0000f899, 
+    0x2100b9a0, 0xf7e52001, 0xf998fb4e, 0x21002000, 0x4644200c, 0xf8b5f7e5, 0xf9942101, 0x46082000, 
+    0xf8f5f7e5, 0x70064828, 0xf881f7f9, 0x22034827, 0xf0072138, 0xb108f814, 0xfe11f7e2, 0x220f2301, 
+    0x46104619, 0xfe19f7e3, 0x46504639, 0xfe37f7db, 0x88004815, 0xd11b2801, 0x491d4812, 0xf7e26800, 
+    0xf04ffed1, 0xf2407480, 0x462011f4, 0xfe0af7db, 0x1100f241, 0xf7db4620, 0x9906fe05, 0xf7db4620, 
+    0xb007fe01, 0x49054620, 0x4ff0e8bd, 0xbdfaf7db, 0xe8bdb007, 0x00008ff0, 0xf203513c, 0xdcba01f5, 
+    0x001312d0, 0x000425d0, 0x0004302c, 0x0004257a, 0x00040298, 0x00043500, 0x00043350, 0x00043580, 
+    0x00043600, 0x00042fcc, 0x00040296, 0xf38f007c, 0x005a000a, 0x4ffee92d, 0x48fa4680, 0x7a80f04f, 
+    0x4615461f, 0xf9b84654, 0xf04f1000, 0x680052a0, 0x46508806, 0xfe25f7db, 0x01c0f242, 0xf7db0648, 
+    0xf240fdde, 0x462011f4, 0xfdcdf7db, 0x51ddf64d, 0xf7db4620, 0xf8dffdb7, 0x462093b0, 0x1000f899, 
+    0xfdb0f7db, 0x462049e9, 0xfdacf7db, 0xb3a0f8df, 0x4ae82400, 0xfb042300, 0xeb0bf006, 0x91020140, 
+    0x0040eb02, 0x22014621, 0x2000e9cd, 0x461a2001, 0xfbacf7e1, 0xb2641c64, 0xdbea2c04, 0x49de48df, 
+    0xf7e26800, 0x2000fe4f, 0x0100f640, 0x46024603, 0xf7e69000, 0x48dbfa07, 0xf9904bd9, 0x48da2000, 
+    0x20007801, 0xfc1df7f9, 0x48d82300, 0x461a2101, 0xff57f006, 0x780048d6, 0xd1022801, 0xf7f92003, 
+    0x2100fd2e, 0xf7e34608, 0x2000ff4b, 0xfce5f7f9, 0x60386828, 0x48cf6829, 0xd0041c4a, 0x32c8f44f, 
+    0x0c094351, 0xf64fe001, 0xf00671ff, 0xf240ff20, 0x465614f4, 0x46504621, 0xfd65f7db, 0x3133f243, 
+    0xf7db4630, 0x6839fd4f, 0xf7db4630, 0x6829fd4b, 0xf7db4630, 0x4db5fd47, 0x46294630, 0xfd42f7db, 
+    0x46304621, 0xfd4ff7db, 0x51ddf64d, 0xf7db4630, 0xf899fd39, 0x464c1000, 0xf7db4630, 0x4629fd33, 
+    0xf7db4630, 0xf44ffd2f, 0x21003500, 0xf7e24628, 0x2100fde3, 0xf7e24628, 0x2003fddf, 0xfb00f7f9, 
+    0x01c0f242, 0xf7db0648, 0x48abfd3a, 0x0000f990, 0xd0082805, 0xd0062803, 0x78202505, 0x3680f44f, 
+    0x2400b118, 0x250fe014, 0xf7e8e7f7, 0x2400faee, 0x2100e005, 0xf7e24630, 0x1c64fdbf, 0x42acb264, 
+    0xe007dbf7, 0x46302100, 0xfdb6f7e2, 0xb2641c64, 0xdbf742ac, 0xf8a82147, 0xe8bd1000, 0xe92d8ffe, 
+    0xf04f5ffc, 0xf9b07680, 0xf04f1000, 0x468152a0, 0xf7db4630, 0xf242fd46, 0x064801c0, 0xfcfff7db, 
+    0xf2404880, 0x680011f4, 0x08448800, 0xf7db4630, 0xf64dfcea, 0x463051dd, 0xfcd4f7db, 0x46304d7a, 
+    0xf7db7829, 0x4979fccf, 0xf7db4630, 0x7828fccb, 0x4882b948, 0xb9307800, 0xf64011f0, 0xf7db0103, 
+    0xf7e8fcd2, 0x2003f8c9, 0xfa9af7f9, 0x0800f04f, 0x250046ab, 0x7830465e, 0x2000b120, 0xfa81f7f7, 
+    0xe001b978, 0xe7f92001, 0x2d641c6d, 0x4874dbf3, 0xb3586800, 0x21c2f240, 0x78324b72, 0xf7e21e48, 
+    0x4871fd8d, 0x4d6b220d, 0x0100f246, 0xf9903daa, 0xb2830000, 0xf0064628, 0x2300fe74, 0x22054628, 
+    0xf0062120, 0x2301fe6e, 0x22054628, 0xf0062120, 0xf04ffe68, 0xf2480a00, 0x46550700, 0x220f485d, 
+    0x38784639, 0xfe6bf006, 0xe001b940, 0xe18b210f, 0x42bd1c6d, 0xf1badbf2, 0xd0400f00, 0x22004855, 
+    0x71fff643, 0xf0063878, 0x07c0fe5a, 0xf242d07e, 0x064801c0, 0xfc83f7db, 0x7580f04f, 0x11f4f240, 
+    0xf7db4628, 0xf241fc70, 0x46281111, 0xfc5af7db, 0xa138f8df, 0xf99a4628, 0xf7db1000, 0x493bfc53, 
+    0xf7db4628, 0x2500fc4f, 0xf89b46b3, 0x28010000, 0x4847d004, 0x0000f990, 0xd04a4285, 0x27004e45, 
+    0x20019700, 0x4629463a, 0xf7e16833, 0xf89afb4f, 0x68310000, 0xd01a2801, 0x800f1e60, 0xf9b9e02e, 
+    0xf04f1000, 0xf04f52a0, 0xf7db7080, 0x4833fc8a, 0x28047800, 0x4832d00a, 0x28006800, 0xf240d006, 
+    0x4b3021c4, 0x1e487832, 0xfd08f7e2, 0xeb01e0d9, 0xf8200044, 0x20007c02, 0xe0051e62, 0x0340eb01, 
+    0xf821885b, 0x1c403010, 0xdbf74290, 0xeb01e008, 0xf8320240, 0xf8212c02, 0x1e402010, 0xdcf62800, 
+    0x23006830, 0x0700e9cd, 0x461a2001, 0xf7e14629, 0x1c6dfa3a, 0x2d04b26d, 0x4e1edba7, 0x462f2500, 
+    0x22009700, 0x46104629, 0xe0006833, 0xf7e1e0af, 0xf89afafd, 0x68310000, 0xd02d2801, 0x800f1e60, 
+    0x0000e041, 0x00042618, 0x0004257a, 0xdcba01f5, 0x00049200, 0x00048a00, 0x00393870, 0x000425d0, 
+    0x00042598, 0x0004023c, 0x0004232e, 0xf20305ae, 0x000425e4, 0xf203513c, 0x00040292, 0x00042fcc, 
+    0x00057f70, 0xf23c80ba, 0x00042590, 0x00043012, 0x00040298, 0x00040238, 0x0044eb01, 0x7c02f820, 
+    0x1e632000, 0xeb01e005, 0x88520240, 0x2010f821, 0x42981c40, 0xe008dbf7, 0x0240eb01, 0x2c02f832, 
+    0x2010f821, 0x28001e40, 0x6830dcf6, 0xe9cd2300, 0x461a0700, 0x46184629, 0xf9d5f7e1, 0xb26d1c6d, 
+    0xdb9d2d04, 0x0000f89b, 0xf44fbbe0, 0xf6403000, 0xf7db0103, 0xf7e7fb98, 0x48c4ff8f, 0xf9902200, 
+    0x97000000, 0x46056833, 0x20014601, 0xfa8ef7e1, 0x0000f89a, 0x28016831, 0x1e60d002, 0xe016800f, 
+    0x0044eb01, 0x7c02f820, 0x1e622000, 0xeb01e005, 0x885b0340, 0x3010f821, 0x42901c40, 0xe008dbf7, 
+    0x0240eb01, 0x2c02f832, 0x2010f821, 0x28001e40, 0x6830dcf6, 0xe9cd2300, 0x20010700, 0x4629461a, 
+    0xf991f7e1, 0x0000f89a, 0xf88a4240, 0xf89b0000, 0xb9080000, 0xf929f7e8, 0x01c0f242, 0xf7db0648, 
+    0xf108fb5e, 0xf1b80801, 0xf6ff0f04, 0xf7f7ae82, 0x4c9ff97b, 0x68202100, 0x2038f890, 0x003af9b0, 
+    0xfdb1f7e3, 0xf9b06820, 0xf7e4003e, 0x2301ff84, 0x220f4898, 0x463103de, 0xfd03f006, 0x78204c96, 
+    0xd0052804, 0x0000f89b, 0x2801465d, 0xe01ad016, 0x2500f44f, 0x46282100, 0xfbcef7e2, 0x46282100, 
+    0xfbcaf7e2, 0x7809498d, 0xd1032904, 0x46282100, 0xfbc2f7e2, 0xf7f92004, 0xe011f8e3, 0xf2422100, 
+    0xf7e20000, 0x2004fbb9, 0xf8daf7f9, 0x46302100, 0xfbb2f7e2, 0xb9187828, 0xfd15f7e3, 0xf8d5f7e8, 
+    0x28047820, 0x2149d004, 0x1000f8a9, 0x9ffce8bd, 0xe7f92148, 0x4ff0e92d, 0x1000f9b0, 0xb0892600, 
+    0x52a0f04f, 0x7080f04f, 0xfb3bf7db, 0x01c0f242, 0xf7db0648, 0xf8dffaf4, 0xf649a1c8, 0x4c6b4540, 
+    0x0000f89a, 0xf44fb968, 0xf6403000, 0xf7db0103, 0xf7e7fada, 0x2100fed1, 0x2000f994, 0xf7e44608, 
+    0x2003fd86, 0xf89cf7f9, 0xf99446a1, 0x48654000, 0xf04f2300, 0xf8cd0b04, 0xeb00b000, 0x48621244, 
+    0x1144eb00, 0xf7e14620, 0xf242fb17, 0x064801c0, 0xfac5f7db, 0x20004f5d, 0xc174f8df, 0x1344eb07, 
+    0x1144eb0c, 0xf83346e0, 0xf8212010, 0x1c402010, 0x2810b240, 0xf89adbf6, 0xb9080000, 0xf875f7e8, 
+    0x46bb2400, 0xf9994647, 0x42840000, 0x2004d018, 0x484c9000, 0xeb002300, 0x484b1244, 0x1144eb00, 
+    0xf7e14620, 0x2000fae9, 0x1144eb0b, 0x1244eb07, 0x3010f831, 0x3010f822, 0xb2401c40, 0xdbf72810, 
+    0xb2641c64, 0xdbde2c04, 0x01c0f242, 0xf7db0648, 0x2047fa86, 0x0018f8ad, 0x6802483e, 0xf9904836, 
+    0xa8061000, 0xfd6bf7ff, 0x0000f89a, 0xb9a02701, 0x20012100, 0xff67f7e4, 0x2000f999, 0x200c2100, 
+    0xf7e4464c, 0x2101fcce, 0x2000f994, 0xf7e44608, 0x4831fd0e, 0xf7f87007, 0x4830fc9a, 0x21382203, 
+    0xfc2df006, 0xf7e2b108, 0x46b9fa2a, 0x24004f2c, 0x080ef04f, 0x1a00f240, 0x8000f8cd, 0x4650220e, 
+    0x46112301, 0x9602e9cd, 0xf8cd9604, 0x96058004, 0xf954f7e3, 0xdd0e2c00, 0xf7e44821, 0x6838fb62, 
+    0xd20842a8, 0x42a86878, 0x68b8d205, 0xd20242a8, 0x42a868f8, 0x1c64d303, 0x2c10b264, 0x4818dbdc, 
+    0xfb4ff7e4, 0x220f2301, 0x46104619, 0xfa05f7e3, 0x68004814, 0xd8052811, 0x2000b009, 0x4ff0e8bd, 
+    0xbf16f7e2, 0xe8bdb009, 0x00008ff0, 0x00040298, 0x00042618, 0xf2035092, 0x00042fcc, 0x00040292, 
+    0x0004257a, 0x00043500, 0x00043350, 0x00043580, 0x00043600, 0x00042fec, 0x00040296, 0xf38f007c, 
+    0x000434e0, 0x00040240, 0x47f0e92d, 0x35e0f240, 0x4617461e, 0x22054688, 0x48134604, 0xe9dd4629, 
+    0xf0069a08, 0xb2c0fbbc, 0x011ff008, 0x1040ea05, 0xf2404301, 0xea004000, 0x43012087, 0x0000f640, 
+    0x20c6ea00, 0x48094301, 0x41a0f441, 0x00c4eb00, 0xfb77f006, 0xea4a4805, 0x1d004109, 0x00c4eb00, 
+    0x47f0e8bd, 0xbb6df006, 0xf23c821e, 0xf1000200, 0x5ffce92d, 0xb404f8df, 0x8e804604, 0xf8df2600, 
+    0xf240a400, 0x4dff1215, 0xf8df4290, 0xf2a083fc, 0xf8df1115, 0xf8db93f8, 0xd0123000, 0x28dfdc23, 
+    0xdc0fd0fb, 0x2880b3a0, 0x2881d03e, 0x28ded046, 0x48f7d17e, 0x46292200, 0xf0016800, 0x1d40f93c, 
+    0xe274d077, 0x7f80f5b0, 0xf5a0d074, 0x38017080, 0x2813d0f7, 0x49ebd16c, 0x46182200, 0xf92bf001, 
+    0xd0681d40, 0x48ebe263, 0x68002971, 0xdc08d07e, 0xd07c291f, 0xd0e42920, 0xd0792933, 0xd1572934, 
+    0x2972e255, 0x298bd0dd, 0x298cd073, 0xe24ed150, 0x49dce7ff, 0x32fff04f, 0x0008f8d9, 0xf93af001, 
+    0xd1071d01, 0xe2172080, 0x220049d6, 0x0008f8d9, 0xf930f001, 0xd0201d41, 0xd1ea2801, 0x1000f9b5, 
+    0xd1e6296d, 0x17d0074a, 0xf99bf7db, 0x464a8868, 0x0000f8a9, 0x1004f9b5, 0x1002f8a9, 0x0006f9b5, 
+    0x0004f8a9, 0x0543b1c0, 0x4fcbd40b, 0x3000f89a, 0x7000f997, 0xd002433b, 0x2081e00e, 0x05c0e1ec, 
+    0x0688d50a, 0x80164630, 0xf040d502, 0xe0010020, 0x0010f040, 0x0000f8a9, 0x0000f898, 0xd00b2801, 
+    0x220648be, 0xf0062140, 0xb150fafa, 0xe0092702, 0xe04ae1d3, 0xe0ace089, 0x700648b9, 0x700648b9, 
+    0x2700e013, 0x220d48b5, 0x0100f242, 0xfae7f006, 0x2001b100, 0x2f014307, 0x2000d01e, 0x2f0249b0, 
+    0xd01b7008, 0x49af2000, 0xe0037008, 0xe0cbe186, 0xe1a9e0ee, 0x0000f9b9, 0x04c24649, 0xf420d52c, 
+    0xf2415080, 0xf8a90700, 0x220c0000, 0x463948a6, 0xfac5f006, 0xe01ab120, 0xe7df2001, 0xe7e22001, 
+    0x780048a2, 0x4aa2b198, 0x46392005, 0xf929f7db, 0x8028203b, 0x22004896, 0x68004992, 0xf87bf001, 
+    0xf47f1d01, 0x20deaf3c, 0x20dfe186, 0x4a98e184, 0xf2412005, 0xe1a80101, 0x06824f96, 0xf020d55c, 
+    0x80080020, 0x0002f899, 0x06804a91, 0x2005d537, 0x0120f242, 0xf905f7db, 0x703e488f, 0x28017800, 
+    0x488ed00f, 0x28017800, 0x488dd00b, 0x28018800, 0x488cd007, 0x28017800, 0x487fd003, 0x28017800, 
+    0xf89ad106, 0xb9180000, 0x0000f898, 0xd0752800, 0x80282071, 0x22004973, 0x0000f8db, 0xf83bf001, 
+    0xd1071d01, 0x1000f240, 0x496ee146, 0x46182200, 0xf831f001, 0xd1611d40, 0x1001f240, 0x2120e13c, 
+    0xf7db2005, 0xf89af8ce, 0x28010000, 0xf898d0df, 0x28000000, 0x2007d0db, 0x49628028, 0xf8db2200, 
+    0xf0010000, 0x1d01f818, 0xaeeaf47f, 0x1014f240, 0xf240e122, 0xe11f1015, 0xd56306c2, 0x0010f020, 
+    0xf8998008, 0x4a620002, 0xd53806c0, 0xf2422005, 0xf7db0110, 0x4860f8a6, 0x7800703e, 0xd00f2801, 
+    0x7800485e, 0xd00b2801, 0x8800485d, 0xd0072801, 0x7800485c, 0xd0032801, 0x7800484f, 0xd1062801, 
+    0x0000f89a, 0xf898b918, 0x28000000, 0x2070d016, 0x49448028, 0xf8db2200, 0xf0000000, 0x1d01ffdc, 
+    0xf240d107, 0xe0e71034, 0x2200493e, 0xf0004618, 0x1d40ffd2, 0xf240d102, 0xe0dd1035, 0x2110e06c, 
+    0xf7db2005, 0xf89af86e, 0x28010000, 0xf898d064, 0x28000000, 0x2007d060, 0x49328028, 0xf8db2200, 
+    0xf0000000, 0x1d01ffb8, 0xf240d107, 0xe0c31048, 0x2200492c, 0xf0004618, 0x1d40ffae, 0xf240d14c, 
+    0xe0b91049, 0xd5480442, 0x4080f420, 0xf8b98008, 0x4a2f0002, 0xd5770440, 0x20052102, 0xf841f7db, 
+    0x703e2201, 0x20022100, 0xfdfcf7e3, 0x20012200, 0xf7e34611, 0x482cfdf7, 0xb1787800, 0x482c492b, 
+    0x78007809, 0x0100e9cd, 0x7801482a, 0x7803482a, 0x7802482a, 0x7800482a, 0xfce8f7e5, 0x491e481f, 
+    0xf9917800, 0x43081000, 0xf9914913, 0x43081000, 0xf7dcd103, 0xf7f6fa4d, 0x4822f866, 0xb1588800, 
+    0x21734808, 0x80013010, 0x70812101, 0x49192200, 0x70c17809, 0xe0384601, 0xe070e083, 0x0004274c, 
+    0x0004028d, 0x0004ea34, 0x0004028c, 0x0004323c, 0x00042fa4, 0x00042f98, 0x00040285, 0xf38fffc0, 
+    0x00040248, 0x00040249, 0xf203902c, 0x0004024d, 0xcccc0000, 0x00042620, 0x000425a1, 0x000425a3, 
+    0x00040286, 0x0004028a, 0x0004254d, 0x0004261f, 0x0004261e, 0x00040292, 0x0004261d, 0x0004261c, 
+    0x0004254c, 0x0004237c, 0x483ce011, 0xf0006800, 0x1d01ff22, 0xf240d106, 0xe02d1086, 0x22004938, 
+    0xff19f000, 0xd1521d40, 0x1087f240, 0x2103e024, 0xf7da2005, 0xf7dcffb6, 0xf7f6f9eb, 0x4831f81a, 
+    0xb3708800, 0x2173482e, 0x80012200, 0x7086492e, 0x70c17809, 0x48294601, 0xf0006800, 0x1d01fefc, 
+    0xf240d106, 0xe00710a0, 0x22004925, 0xfef3f000, 0xd12c1d40, 0x10a1f240, 0xe8bd86a0, 0x07429ffc, 
+    0xf020d525, 0xf8a90004, 0xf8980000, 0x28010000, 0x481ed104, 0xf0308800, 0xd0030040, 0x21084a1c, 
+    0xe014e012, 0x21044f1a, 0x463a4608, 0xff79f7da, 0x22024818, 0xf0062104, 0x2801f902, 0x2004d00d, 
+    0xff73f7e1, 0x463a2106, 0xf7da2004, 0xf8b9ff6a, 0x28000000, 0xae04f47f, 0x2105e5ab, 0xe7f3463a, 
+    0x21012200, 0xf2afb510, 0xf0005057, 0x2108fcff, 0xf0002004, 0x4908fe5d, 0xbd106088, 0x00042f98, 
+    0x0004ea44, 0x0004237c, 0x00040292, 0x00040290, 0xcccc0000, 0xf2039026, 0x0004323c, 0x4ff0e92d, 
+    0x4605b09f, 0xf8df2400, 0xf240a424, 0xf88d327a, 0x9418406c, 0x8e80941c, 0xf2a04290, 0xd07c317a, 
+    0xb150dc05, 0xd01428d0, 0xd17728d1, 0x2901e01c, 0x29b8d075, 0x29b9d074, 0x49fcd170, 0x32fff04f, 
+    0x001cf8da, 0xf0003124, 0x1d01fea5, 0x20d0d108, 0x49f6e37d, 0xf8da2200, 0x3124001c, 0xfe9af000, 
+    0xd0111d41, 0xd1e82801, 0x302448f0, 0x28658800, 0x48efd1e3, 0x22022301, 0xf0062104, 0x48edf882, 
+    0x28027800, 0xe012d002, 0xe36020d1, 0x780048ea, 0xd10c2801, 0xb3a4f8df, 0x0000f89b, 0x2801b1e0, 
+    0x2802d024, 0x2803d029, 0xf88bd07e, 0x22084000, 0x015148e3, 0xf873f006, 0xd0762800, 0x0008f8ba, 
+    0x1c40210a, 0xf8aab280, 0xfbb00008, 0xfb01f2f1, 0x28000012, 0xe1ded06a, 0xfeb9f7e7, 0xf88b2001, 
+    0x48d80000, 0x48d87004, 0xe7e07004, 0xfef1f7e7, 0x2002b108, 0x2001e05c, 0xf7e7e05a, 0x2800fef7, 
+    0xf7e7d0f7, 0x2100fe94, 0x3080f44f, 0xff14f7e1, 0x20004bce, 0x26004ace, 0xe319e003, 0xe231e3f0, 
+    0xeb02e3ef, 0xe9c101c0, 0xeb036600, 0x1c4001c0, 0xe9c12804, 0xdbee6600, 0xa8192700, 0xfe97f7e7, 
+    0xf7e74668, 0x2600fead, 0xf830a819, 0xf0080016, 0x4bc0f853, 0xf0072200, 0x4abcfe83, 0x03c6eb02, 
+    0xcb0c4699, 0xfdc0f007, 0x0100e9c9, 0x4bb94668, 0x00c6eb00, 0xe9d02200, 0xf0070100, 0x4ab4fe71, 
+    0x03c6eb02, 0xcb0c4699, 0xfdaef007, 0x2e041c76, 0x0100e9c9, 0x2100dbd8, 0x2000f240, 0xfeccf7e1, 
+    0x2f641c7f, 0xe002dbc9, 0xe16be005, 0x2003e09e, 0x0000f88b, 0x2000e77b, 0xaa10ab08, 0xeb022600, 
+    0xe9c101c0, 0xeb036600, 0x1c4001c0, 0xe9c12804, 0xdbf36600, 0xa8192700, 0xfe49f7e7, 0xf7e74668, 
+    0x2600fe5f, 0xf830a819, 0xf0080016, 0x4b99f805, 0xf0072200, 0xaa08fe35, 0x03c6eb02, 0xcb0c4699, 
+    0xfd72f007, 0x0100e9c9, 0x4b924668, 0x00c6eb00, 0xe9d02200, 0xf0070100, 0xaa10fe23, 0x03c6eb02, 
+    0xcb0c4699, 0xfd60f007, 0x2e041c76, 0x0100e9c9, 0x2100dbd8, 0x2000f240, 0xfe7ef7e1, 0x2f641c7f, 
+    0x2700dbc9, 0xa808463e, 0x00c6eb00, 0x2300e9d0, 0xeb00487e, 0xe9d101c6, 0x46810100, 0xf008911d, 
+    0xf007fa27, 0x2800ff55, 0x4240da00, 0xffadf007, 0x464a9b1d, 0xfdf4f007, 0x48774684, 0x2300e9d0, 
+    0xf0084660, 0xd206f907, 0x7808496e, 0xd00128ff, 0x70081c40, 0x486e2701, 0x00c6eb00, 0x2300e9d0, 
+    0xeb00a810, 0xe9d101c6, 0xf0070100, 0x4684fdd9, 0xe9d0486a, 0x46602300, 0xf8ecf008, 0x4962d206, 
+    0x28ff7808, 0x1c40d001, 0x27017008, 0x2e041c76, 0x2f00dbb9, 0xaf67f43f, 0xfdb9f7e7, 0xf44f2100, 
+    0xf7e13000, 0xf7e7fe29, 0xe702fda2, 0x7800485c, 0xd17d2802, 0xf005485b, 0xb2c6ff27, 0x000ff006, 
+    0xd176280a, 0xfe79f7f5, 0x915cf8df, 0xd0382801, 0x4f544856, 0xf9903724, 0x28030000, 0x2805d043, 
+    0x2804d041, 0x2300d03f, 0x22044638, 0xf0052110, 0x484cff28, 0xf005301e, 0x4607ff07, 0x301c4849, 
+    0xff02f005, 0x4b00ea47, 0x30224846, 0xfefcf005, 0x48444607, 0xf0053020, 0xea47fef7, 0x90004000, 
+    0xebb02003, 0xd1201f16, 0x1014f8da, 0xf7f54658, 0xf8dafe3a, 0x46071018, 0xf7f59800, 0x4438fe34, 
+    0xf88de024, 0x27fe406c, 0x1000f89a, 0xd10729fe, 0x0002f89a, 0xd1034286, 0x0000f899, 0xd13c2801, 
+    0x32fff04f, 0x2301e065, 0x2001e7be, 0x1f16ebb0, 0xf8dad103, 0x46581014, 0x2002e006, 0x1f16ebb0, 
+    0xf8dad105, 0x98001018, 0xfe0df7f5, 0xf8ca9018, 0x9900b014, 0x1018f8ca, 0x9818a91b, 0xfdd5f7f5, 
+    0xf89a4607, 0x42b00002, 0xf899d142, 0xe0010000, 0xe018e051, 0xd03b2801, 0x1000f89a, 0xd105428f, 
+    0x106cf89d, 0x0001f89a, 0xd0064281, 0xb2714809, 0xf9909a18, 0xf7f50000, 0xf88afa04, 0xf89d7000, 
+    0xf88a106c, 0xf88a1001, 0xe0346002, 0x00043248, 0xf23c8318, 0x00040292, 0x00042378, 0x0004235e, 
+    0xf38f2002, 0x0004235f, 0x00042360, 0x0004e228, 0x0004e248, 0x40590000, 0x00042368, 0x00042370, 
+    0x000425a2, 0xf23c80d2, 0x00042356, 0x0004024c, 0xb2719a18, 0xf99048f8, 0xf7f50000, 0xf889f9d2, 
+    0xe7ca4000, 0x4008f8aa, 0xf88a21fd, 0xf88a1002, 0xf88a1000, 0x220f1001, 0xf24848f0, 0xf0050100, 
+    0xbb88fe7e, 0x0010f8ba, 0x1c404656, 0xf8aab280, 0x07010010, 0xf000d00a, 0x2801000f, 0x2802d00f, 
+    0x2803d014, 0x2804d019, 0xe026d01f, 0xf0032000, 0xfa0ffd47, 0x48e2f880, 0xf188fa1f, 0x2001e01b, 
+    0xfddff003, 0x48deb281, 0xe0141c80, 0xf0032004, 0xb281fd37, 0x1d0048da, 0x2005e00d, 0xfd30f003, 
+    0x48d7b281, 0xe0061d80, 0x2006e031, 0xfd28f003, 0x48d3b281, 0xf0053008, 0x48d2fe1a, 0x4fd34bd2, 
+    0x28017800, 0x6819d002, 0xd1142901, 0x07097c31, 0x4acfd11d, 0xd1022801, 0x45b06816, 0x6819da11, 
+    0xd00a2901, 0x454149cb, 0x2801da11, 0xf647d028, 0x454070ff, 0x2300dd0b, 0x49c7e004, 0x45886809, 
+    0x2301dc1a, 0x22014638, 0xf0052102, 0x48c3fe0a, 0x0000f990, 0xd0182803, 0xd0162805, 0xd0142804, 
+    0x400ef8aa, 0x48be2723, 0x28017800, 0xf89ad07e, 0x29001003, 0xe1b5d17b, 0x681b4bba, 0xe7d24419, 
+    0x681049b9, 0x1a406809, 0xf8bae7d3, 0x1c40000e, 0x000ef8aa, 0xf00548b5, 0x4606fdc7, 0xd5210600, 
+    0x780048b3, 0xd0052801, 0xf801f7f8, 0x780048b1, 0xe014b180, 0x220348b0, 0xf0052138, 0xb108fde0, 
+    0xe0002007, 0xf8ba201f, 0x4201100e, 0xf7f7d10a, 0xe007ffee, 0x780048a9, 0x2001b108, 0x2000e000, 
+    0xfb8df7e7, 0xd50c0730, 0x780048a5, 0xd1062801, 0x780048a4, 0xf89ab918, 0x06c0000e, 0xf7f7d101, 
+    0x0430fe26, 0xf8bad515, 0x4657000e, 0xd1010580, 0xfbb4f7e1, 0xf0107bb8, 0xd10a0f05, 0x78384f9a, 
+    0xf7e1b138, 0x4999fbac, 0x703c2001, 0xf7e17008, 0x4897fba5, 0x28017800, 0x4896d158, 0x28017800, 
+    0xf89ad154, 0x4a940005, 0xb2c01c40, 0x0005f88a, 0x42907812, 0x4891d94a, 0xf88a46d1, 0x78004005, 
+    0xd02b2801, 0xd0292802, 0xe001488d, 0xe06ee06b, 0xfd5af005, 0x488a4607, 0xf0051c80, 0xf8d9fd55, 
+    0xea471020, 0x4f874000, 0x42884a87, 0x783bd005, 0x40992101, 0x43196813, 0x78396011, 0x1c494b83, 
+    0x7039b2c9, 0x4299781b, 0x703cd300, 0xf8c92100, 0x46080020, 0xf04f6817, 0xe00f0c01, 0x1f004878, 
+    0xfd32f005, 0x48764607, 0xe7d61e80, 0xf200fa0c, 0xd001423a, 0xb2c91c49, 0xb2c01c40, 0xd3f54298, 
+    0x78004873, 0xd9014281, 0x901c2001, 0xd5090570, 0x000ef89a, 0xd1050700, 0x1f80485c, 0xfd14f005, 
+    0xd10307c0, 0x2801981c, 0xaf2cf47f, 0x901c2000, 0xfc43f7fb, 0x21434867, 0x80012200, 0x48664601, 
+    0xf0006800, 0x1d01faf8, 0xf240d108, 0xe0f4307a, 0x22004861, 0x6800495f, 0xfaedf000, 0xd1e31d40, 
+    0x307bf240, 0xf89ae0e9, 0x46560003, 0xf89ab1a0, 0x46560003, 0xd0312801, 0xf86ff7e6, 0x71b02121, 
+    0x28002222, 0x000af9b6, 0x2823d051, 0x2822d02f, 0x2821d034, 0xe041d039, 0x1c407930, 0x7130b2c0, 
+    0xd3172828, 0x2205484d, 0xf0052120, 0xb928fcf8, 0x384e482e, 0xfcc8f005, 0xd00c07c0, 0x28238970, 
+    0x2300d007, 0x22018177, 0x46184619, 0xf7f69400, 0x7134fe53, 0x2001e098, 0xe7fa70f0, 0xf7e52003, 
+    0x2001fd31, 0xffc9f7e5, 0x70f02002, 0x2300e08c, 0x22018172, 0x46104619, 0xe00d9400, 0x81712300, 
+    0x46192201, 0x94002002, 0x2020e006, 0x23008170, 0x22019400, 0x20034619, 0xfe2ef7f6, 0x1c4089b0, 
+    0x4812b281, 0x384c81b1, 0xfc91f005, 0x2820e060, 0x2821d004, 0x2822d009, 0xe059d052, 0x81712300, 
+    0x46192201, 0x94002002, 0x2300e050, 0x22018172, 0x46104619, 0xe0499400, 0x00040292, 0xf2020000, 
+    0xf23d0142, 0x0004230f, 0x00042318, 0xf20351da, 0x00042310, 0xffff8001, 0x0004231c, 0x0004024c, 
+    0x00042620, 0x00042320, 0x00042314, 0xf23c80b8, 0x00040297, 0x0004257a, 0xf38f007c, 0x000402cf, 
+    0x00040296, 0x00043010, 0x000402b0, 0x000402b1, 0x000402db, 0x000402da, 0x000425df, 0x000425f9, 
+    0xf2036116, 0x000425dc, 0x000425d8, 0x000425dd, 0x000425de, 0x0004326c, 0x00043004, 0xf38f2034, 
+    0x81772300, 0x46192201, 0x94004618, 0xfdc4f7f6, 0xf7e52002, 0x2000fca7, 0xff3ff7e5, 0xe00370f4, 
+    0xe00fe01c, 0x4004f88a, 0x48152129, 0x80012200, 0x48144601, 0xf0006800, 0x1d01fa0e, 0xf240d108, 
+    0xe00a4032, 0x2200480f, 0x6800490d, 0xfa03f000, 0xf47f1d40, 0xf240ab82, 0x86a84033, 0xe8bdb01f, 
+    0x22008ff0, 0xb5102101, 0x104ff6af, 0xf83ef000, 0x200a2108, 0xf99cf000, 0x39244901, 0xbd1061c8, 
+    0x0004326c, 0x00042f88, 0xb5082008, 0xfb9bf7e1, 0x90002000, 0x46032201, 0x20084601, 0xfbd8f7e1, 
+    0x20084908, 0xfb9ef7e1, 0xf7e14807, 0x2008fbf4, 0xfb9df7e1, 0xf2462201, 0xe8bd11a8, 0x20034008, 
+    0xba98f7e1, 0x00026d68, 0xf0001184, 0xf8bcf000, 0x8e80e7fc, 0xd1012800, 0xbba2f006, 0x22004770, 
+    0xf2af4611, 0xf0000011, 0x0000b801, 0x47f0e92d, 0x460e4691, 0x20384682, 0xfc20f000, 0xd0440004, 
+    0xf8df4f86, 0x6838821c, 0x2500b9d8, 0xeb05603c, 0xeb080185, 0xf0000081, 0x1c6df905, 0xd3f62d02, 
+    0x3028487f, 0xf8fef000, 0x303c487d, 0xf8faf000, 0x3050487b, 0xf8f6f000, 0x30284879, 0x30146178, 
+    0x2e0261b8, 0x2601d300, 0x86a02000, 0xa000f8c4, 0xe9c41d20, 0xf000690b, 0xf104f8f0, 0xf0000018, 
+    0x6124f8ec, 0x000af1c6, 0x61a06264, 0x68796ae0, 0xd9004288, 0xeb006078, 0xeb080180, 0x1d210081, 
+    0xf8def000, 0xe8bd2001, 0xf04f87f0, 0xe7fa30ff, 0x4d62b570, 0x68a9460e, 0x6828180c, 0xf0001d00, 
+    0x6829f8f5, 0x68a8604c, 0xd2014284, 0xe00069a8, 0x1d096968, 0xf8d2f000, 0xd0062e00, 0x46306829, 
+    0x4070e8bd, 0xf0003118, 0xbd70b8c9, 0xf000b570, 0x4d52fb2d, 0x1a4068e9, 0xe02f6128, 0x0101f1a1, 
+    0x1c406129, 0xd10360a8, 0x1005e9d5, 0x0105e9c5, 0x69684e4b, 0xb1f16801, 0x68c468c0, 0x6860e01c, 
+    0x428868a9, 0xb672d81a, 0xf0001d20, 0x6aa0f8bf, 0xf104b118, 0xf0000018, 0xb662f8b9, 0x68696ae0, 
+    0xd9004288, 0xeb006068, 0x1d210080, 0x0080eb06, 0xf886f000, 0x2400e7dd, 0xd1e02c00, 0x68a86929, 
+    0xd1cb2900, 0xbd7060e8, 0xf000b510, 0xf7fff840, 0x4932ffbd, 0x68484a32, 0x2800e003, 0x1e40d01b, 
+    0xeb006048, 0xf8520380, 0x2b003023, 0xeb00d0f5, 0xeb020080, 0x68420080, 0xf1006852, 0x60420308, 
+    0xd101429a, 0x60426852, 0x600868d0, 0x6b016802, 0x4010e8bd, 0xbd104710, 0x6801b570, 0x68c0b111, 
+    0xe00068c4, 0xf1042400, 0x46050018, 0xf86ef000, 0x4629481b, 0xf0003050, 0x4918f843, 0x68096ae0, 
+    0x42886ac9, 0x2001d301, 0x2000bd70, 0xe92dbd70, 0x4d1341f0, 0x4f124e11, 0xe01a3550, 0x6828b672, 
+    0x68e8b110, 0xe00068c4, 0xf1042400, 0xf0000018, 0xb662f84d, 0xf0001d20, 0x6ae0f849, 0x42886871, 
+    0x6070d900, 0x0080eb00, 0xeb071d21, 0xf0000080, 0x6828f817, 0xd1e12800, 0x81f0e8bd, 0x00043274, 
+    0x0004ea50, 0x32fff04f, 0x0108f100, 0x1201e9c0, 0x610160c1, 0x60012100, 0x21004770, 0x47706101, 
+    0x68536842, 0x6843604b, 0x6853608b, 0x60516099, 0x61086041, 0x1c496801, 0x47706001, 0x680bb510, 
+    0xd0021c5a, 0x0208f100, 0x6902e002, 0x6852e004, 0x68246854, 0xd9fa429c, 0x604b6853, 0x608a6099, 
+    0x61086051, 0x1c496801, 0xbd106001, 0x1201e9d0, 0xe9d0608a, 0x60511201, 0x684a6901, 0xd1014282, 
+    0x604a6882, 0x61022200, 0x1e406808, 0x47706008, 0x0005b570, 0xd028460e, 0xf000204c, 0x0004fabf, 
+    0xfb05d023, 0x1c40f006, 0xfab8f000, 0xb1c86020, 0x0106fb05, 0x21006061, 0x1e6963a1, 0xfb0160a0, 
+    0x63e50006, 0xf04f60e0, 0xe9c430ff, 0x64a06010, 0x0010f104, 0xff96f7ff, 0x0024f104, 0xff92f7ff, 
+    0xbd704620, 0xf0004620, 0x2000faa5, 0xb510bd70, 0x6c024613, 0xb16a4604, 0x68e0b183, 0xebd8f004, 
+    0x6c2068e1, 0x60e11a09, 0x42916822, 0x6861d202, 0x60e01a08, 0x1c406ba0, 0xbd1063a0, 0xf00468a0, 
+    0x6c21ebc8, 0x440868a0, 0x686160a0, 0xd3f14288, 0x60a06820, 0xb570e7ee, 0x460e4615, 0xb6724604, 
+    0xf875f000, 0xb145b160, 0x0110f104, 0xf7ff4628, 0xb662fe8f, 0x0003f06f, 0xb662bd70, 0xbd702000, 
+    0xbf00b662, 0x6ba0b672, 0x42886be1, 0x2200d20e, 0x46204631, 0xffbbf7ff, 0x25016a60, 0xf104b138, 
+    0xf7ff0024, 0xb110fef9, 0xe0001fad, 0xb6622500, 0xbd704628, 0x460bb570, 0xb6724604, 0xb1f06b80, 
+    0xbf00b662, 0x6ba0b672, 0x6c22b330, 0x441068e0, 0x686160e0, 0xd3014288, 0x60e06820, 0x1e406ba0, 
+    0x68e163a0, 0xf0044618, 0x6920eb74, 0xb1a02501, 0x0010f104, 0xfed0f7ff, 0x1fadb178, 0xb142e00d, 
+    0x0124f104, 0xf7ff4610, 0xb662fe43, 0x0003f06f, 0xb662bd70, 0xbd702000, 0xb6622500, 0xbd704628, 
+    0x4604b570, 0x46156b80, 0x42906be2, 0x2200d20d, 0xf7ff4620, 0xb945ff6c, 0xb1306a60, 0x0024f104, 
+    0xfeaaf7ff, 0x2001b108, 0x4628bd70, 0xb510bd70, 0xf0004604, 0x6ba0fa54, 0x42886be1, 0x2401d101, 
+    0x2400e000, 0xfa51f000, 0xbd104620, 0x680148ed, 0x6800b111, 0x47706b00, 0x47702000, 0x5ff0e92d, 
+    0x4615469a, 0x46834689, 0xe9dd2058, 0xf000680a, 0x0004f9d5, 0x00afd009, 0xf0004638, 0x6320f9cf, 
+    0x22a5b3d8, 0xf0044639, 0x2c00fb89, 0x6b21d07e, 0x0003f06f, 0x0085eb00, 0x44084635, 0xf0204649, 
+    0x22200707, 0x0034f104, 0xeba8f004, 0xf8842000, 0x2d0a0053, 0x2509d300, 0x1d2062e5, 0xfeadf7ff, 
+    0x0018f104, 0xfea9f7ff, 0xf1c56124, 0x6264010a, 0x46384652, 0x465961a1, 0xf9baf000, 0xf0006020, 
+    0x4fc8f9fe, 0x1c4068b8, 0x68b860b8, 0x9318f8df, 0xd0082801, 0xb35069b8, 0xe7ffe02e, 0xf0004620, 
+    0x2400f999, 0x603ce7c1, 0xeb052500, 0xeb090185, 0xf7ff0081, 0x1c6dfe77, 0xd3f62d0a, 0x30c848ba, 
+    0xfe70f7ff, 0x30dc48b8, 0xfe6cf7ff, 0x30f048b6, 0xfe68f7ff, 0xf7ff48b5, 0x48b4fe65, 0xf7ff3014, 
+    0x48b2fe61, 0x63b8383c, 0x63f83014, 0x6838e004, 0x42b06ac0, 0x603cd800, 0x69396ae0, 0xd9004288, 
+    0x6af96138, 0x1c496561, 0x697962f9, 0xd9004288, 0xeb006178, 0xeb090180, 0x1d210081, 0xfe50f7ff, 
+    0xf0002501, 0xf1b8f9b2, 0xe0000f00, 0xd001e00c, 0x4000f8c8, 0xb12069b8, 0x6ac06838, 0xd20042b0, 
+    0x4628df00, 0x9ff0e8bd, 0x35fff04f, 0xb570e7f9, 0x69e84d94, 0x6a28b118, 0x62281c40, 0x68e8bd70, 
+    0x60e81c40, 0xb93068e8, 0x6be96ba8, 0x63e863a9, 0x1c406aa8, 0x4e8c62a8, 0x6860e018, 0x428868e9, 
+    0x1d20d8ec, 0xfe42f7ff, 0xb1186aa0, 0x0018f104, 0xfe3cf7ff, 0x69696ae0, 0xd9004288, 0xeb006168, 
+    0x1d210080, 0x0080eb06, 0xfe0af7ff, 0x68006ba8, 0x6ba8b118, 0x68c468c0, 0x2400e000, 0xd1dc2c00, 
+    0xe92dbd70, 0x270047f0, 0xf959f000, 0x69f04e75, 0x61f01e40, 0xbb7869f0, 0xb36868b0, 0x81ccf8df, 
+    0xf8df2500, 0xf1a891c4, 0xe0180814, 0x0018f104, 0xfe0cf7ff, 0xf7ff1d20, 0x6ae0fe09, 0x42886971, 
+    0x6170d900, 0x0180eb00, 0x0081eb09, 0xf7ff1d21, 0x6ae0fdd7, 0x6ac96831, 0xd3004288, 0xf8d82501, 
+    0x46401000, 0x68c0b111, 0xe00068c4, 0x2c002400, 0x6a30d1dc, 0xe008b930, 0xf7ffe00f, 0x6a30ff88, 
+    0x62301e40, 0x28006a30, 0xb915d1f7, 0x28016a70, 0x2701d103, 0x62702000, 0xf000df00, 0x4638f916, 
+    0x87f0e8bd, 0x69c1484f, 0x61c11c49, 0xf0004770, 0xdf00f870, 0xfc6af7ff, 0xb51fe7f9, 0x484e2400, 
+    0x4623a14b, 0x2200f240, 0x94019400, 0x94039402, 0xfeb4f7ff, 0xd1082801, 0x2101b672, 0x61814841, 
+    0xe8bd60c4, 0xf000401f, 0xbd1fb8e3, 0xf000b510, 0x483cf8e6, 0xf00068c4, 0x4620f8e8, 0x4939bd10, 
+    0x4a3969c8, 0x2001b120, 0x47706248, 0x61481e40, 0xeb006948, 0xf8520080, 0x28000020, 0xd0f56948, 
+    0x0080eb00, 0x0080eb02, 0x68526842, 0x0308f100, 0x429a6042, 0x6852d101, 0x68d06042, 0x6b086008, 
+    0xd0e22800, 0x6b4a6808, 0x42906d40, 0x6c08d0dd, 0x30086c8a, 0xd20f4290, 0x6d406808, 0x68c86348, 
+    0x60106c0a, 0x1d006c08, 0x6c0a6408, 0x60106b48, 0x1d006c08, 0x47706408, 0x63082000, 0xb5104770, 
+    0x6b004604, 0xf846f000, 0xe8bd4620, 0xf0004010, 0xb570b841, 0x68684d13, 0xd0222800, 0xff82f7ff, 
+    0x68304e12, 0x2400b158, 0xff2bf7ff, 0xd1182c00, 0xf885f000, 0xb1206830, 0x68c468f0, 0x2401e002, 
+    0x2400e7f2, 0xf7ff1d20, 0x68a8fd41, 0x60a81e40, 0x1e406868, 0xf0006068, 0x4620f878, 0x4070e8bd, 
+    0xbd70e7cd, 0x00043290, 0x0004eab4, 0x0004ebb8, 0x454c4449, 0x00000000, 0x00026b2f, 0x4604b510, 
+    0xff50f7ff, 0xf0044620, 0x4604f897, 0xfef9f7ff, 0xbd104620, 0x0004b510, 0xf7ffd008, 0x4620ff43, 
+    0xf8b9f004, 0x4010e8bd, 0xbeebf7ff, 0x0000bd10, 0x60011d09, 0xf04f1f01, 0x600b33aa, 0xf04f1f09, 
+    0x60083312, 0x600b1f09, 0xf04f1f09, 0x600b3311, 0xf04f1f09, 0x600b3310, 0xf04f1f09, 0x600b3309, 
+    0xf04f1f09, 0x600b3308, 0xf04f1f09, 0x600b3307, 0xf04f1f09, 0x600b3306, 0xf04f1f09, 0x600b3305, 
+    0xf04f1f09, 0x600b3304, 0xf04f1f09, 0x600b3303, 0xf04f1f09, 0x600b3302, 0x105b1f09, 0x1f09600b, 
+    0x1f09600a, 0x600a223f, 0xf8402100, 0x47701d44, 0xf7ffb510, 0xf004fb49, 0x2000ef6c, 0xb672bd10, 
+    0x68414808, 0x60411c49, 0x48064770, 0x29006841, 0x6841d006, 0x60411e49, 0x28006840, 0xb662d100, 
+    0x00004770, 0x000432dc, 0xe92d503f, 0xe59f0068, 0xfa00138c, 0xfbffff24, 0xe59f4060, 0xe1d400b0, 
+    0xe2800001, 0xe6ff0070, 0xe1c400b0, 0xe3500b01, 0x3a00000c, 0xe2841008, 0xe3a00065, 0xe3a02000, 
+    0xe1c100b0, 0xe59f0038, 0xe5900000, 0xfafffeab, 0xe59f1030, 0xe5912000, 0xe0800002, 0xe5810000, 
+    0xe3a00000, 0xe1c400b0, 0xe59f001c, 0xfbff8380, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xf23c824a, 
+    0x000432dc, 0x00043264, 0x00040244, 0xf0001184, 0x21012300, 0xb510461a, 0xf00448fe, 0x48fdfef2, 
+    0x220e2300, 0x0100f244, 0x4010e8bd, 0xf0043010, 0xe92dbee8, 0x48f75ff0, 0x011af24a, 0xf004301e, 
+    0x48f4fec6, 0x3100f240, 0xf0043020, 0x48f1fec0, 0x302221ef, 0xfebbf004, 0xf24148ee, 0x30263104, 
+    0xfeb5f004, 0x210048eb, 0xf0043028, 0x48e9feb0, 0x0100f244, 0xf004302c, 0x48e6feaa, 0x0100f243, 
+    0xf004302e, 0x48e4fea4, 0x2712f241, 0x34304ce1, 0x1ca57800, 0xb1101d26, 0x1115f241, 0xf241e001, 
+    0x46201116, 0xfe93f004, 0x46284639, 0xfe8ff004, 0x46302113, 0xfe8bf004, 0x8358f8df, 0x4700f240, 
+    0xf1084639, 0x46400836, 0xfe81f004, 0x0902f108, 0x4121f247, 0xf0044648, 0xf108fe7a, 0x21000a04, 
+    0xf0044650, 0xf241fe74, 0xf1080b00, 0x46590006, 0xfe6df004, 0x0006f109, 0x2100f64a, 0xfe67f004, 
+    0xf24448c4, 0x304e01ff, 0xfe61f004, 0x465948c1, 0xf004302a, 0x48bffe5c, 0x302a2100, 0xfe57f004, 
+    0x46202100, 0xfe53f004, 0x46282100, 0xfe4ff004, 0x46302100, 0xfe4bf004, 0x46402100, 0xfe47f004, 
+    0x46482100, 0xfe43f004, 0x46502100, 0xfe3ff004, 0xf1082100, 0xf0040006, 0x2100fe3a, 0x0006f109, 
+    0xfe35f004, 0x210048ab, 0xf004304e, 0xf643fe30, 0x46204111, 0xfe2bf004, 0x1128f642, 0xf0044628, 
+    0x2174fe26, 0xf0044630, 0x48a2fe22, 0x0107f248, 0xf004304e, 0x489ffe1c, 0x302a4659, 0xfe17f004, 
+    0x2100489c, 0xf004302a, 0x2100fe12, 0xf0044620, 0x2100fe0e, 0xf0044628, 0x2100fe0a, 0xf0044630, 
+    0x4894fe06, 0x304e2100, 0xfe01f004, 0x46202100, 0xfdfdf004, 0x5140f240, 0xf0044628, 0xf640fdf8, 
+    0x46306140, 0xfdf3f004, 0x0141f640, 0xf0044640, 0xf241fdee, 0x46483144, 0xfde9f004, 0x0006f109, 
+    0x011cf245, 0xfde3f004, 0xf10a2140, 0xf0040006, 0x4880fdde, 0x113bf645, 0xf0043042, 0x487dfdd8, 
+    0x30444639, 0xfdd3f004, 0x5ff0e8bd, 0x21d04879, 0xf004302a, 0xe92dbdcc, 0x48765ff0, 0x011af24a, 
+    0xf004301e, 0x4873fdc4, 0x3100f240, 0xf0043020, 0x4870fdbe, 0x302221ef, 0xfdb9f004, 0xf241486d, 
+    0x30263104, 0xfdb3f004, 0x2100486a, 0xf0043028, 0x4868fdae, 0x0100f244, 0xf004302c, 0x4865fda8, 
+    0x0100f243, 0xf004302e, 0x4863fda2, 0x34304c61, 0x1ca57801, 0xb1591d26, 0x1115f241, 0xf0044620, 
+    0xf241fd96, 0x46282112, 0xfd91f004, 0xe00a2113, 0x0110f640, 0xf0044620, 0xf640fd8a, 0x46280108, 
+    0xfd85f004, 0x46302107, 0xfd81f004, 0x8144f8df, 0x4700f240, 0xf1084639, 0x46400836, 0xfd77f004, 
+    0x0902f108, 0x4121f247, 0xf0044648, 0xf108fd70, 0x21000a04, 0xf0044650, 0xf241fd6a, 0xf1080b00, 
+    0x46590006, 0xfd63f004, 0x0006f109, 0x2100f64a, 0xfd5df004, 0xf244483f, 0x304e01ff, 0xfd57f004, 
+    0x4659483c, 0xf004302a, 0x483afd52, 0x302a2100, 0xfd4df004, 0x46202100, 0xfd49f004, 0x46282100, 
+    0xfd45f004, 0x46302100, 0xfd41f004, 0x46402100, 0xfd3df004, 0x46482100, 0xfd39f004, 0x46502100, 
+    0xfd35f004, 0xf1082100, 0xf0040006, 0x2100fd30, 0x0006f109, 0xfd2bf004, 0x21004826, 0xf004304e, 
+    0xf643fd26, 0x46204111, 0xfd21f004, 0x1128f642, 0xf0044628, 0x2174fd1c, 0xf0044630, 0x481dfd18, 
+    0x0107f248, 0xf004304e, 0x481afd12, 0x302a4659, 0xfd0df004, 0x21004817, 0xf004302a, 0x2100fd08, 
+    0xf0044620, 0x2100fd04, 0xf0044628, 0x2100fd00, 0xf0044630, 0x480ffcfc, 0x304e2100, 0xfcf7f004, 
+    0x46202100, 0xfcf3f004, 0x5140f240, 0xf0044628, 0xf640fcee, 0x46306140, 0xfce9f004, 0x0141f640, 
+    0xf0044640, 0xf241fce4, 0x46483144, 0xfcdff004, 0x0000e004, 0xf2039800, 0x000425c0, 0x0006f109, 
+    0x011cf245, 0xfcd3f004, 0xf10a2140, 0xf0040006, 0x48fffcce, 0x113bf645, 0xfcc9f004, 0x463948fc, 
+    0xf0041c80, 0xe8bdfcc4, 0x48f95ff0, 0x381821d0, 0xbcbdf004, 0x5ff0e92d, 0xf24a48f5, 0x3824011a, 
+    0xfcb5f004, 0xf24048f2, 0x38223100, 0xfcaff004, 0x21ef48ef, 0xf0043820, 0x48edfcaa, 0x3104f241, 
+    0xf004381c, 0x48eafca4, 0x1180f240, 0xf004381a, 0x48e7fc9e, 0x0100f244, 0xf0043816, 0x48e4fc98, 
+    0x0100f243, 0xf0043814, 0x4ce1fc92, 0x0107f640, 0x46203c12, 0xfc8bf004, 0xf2401ca5, 0x46282108, 
+    0xfc85f004, 0x0904f104, 0x46482100, 0xfc7ff004, 0x0a06f104, 0x5100f240, 0xf0044650, 0xf105fc78, 
+    0xf2470b06, 0x4658318e, 0xfc71f004, 0x0606f109, 0x0800f241, 0x46304641, 0xfc69f004, 0x46411cb7, 
+    0xf0044638, 0x1d30fc64, 0x2100f64a, 0xfc5ff004, 0xf24448c7, 0x300c01ff, 0xfc59f004, 0x46411fa0, 
+    0xfc55f004, 0x1fa02100, 0xfc51f004, 0x46202100, 0xfc4df004, 0x46282100, 0xfc49f004, 0x46482100, 
+    0xfc45f004, 0x46502100, 0xfc41f004, 0x46582100, 0xfc3df004, 0x46302100, 0xfc39f004, 0x46382100, 
+    0xfc35f004, 0x1d302100, 0xfc31f004, 0x210048b0, 0xf004300c, 0xf643fc2c, 0x46201116, 0xfc27f004, 
+    0x112ef242, 0xf0044628, 0x216afc22, 0xf0044648, 0x2100fc1e, 0xf0044630, 0x48a5fc1a, 0x0127f248, 
+    0xf004300c, 0x1fa0fc14, 0xf0044641, 0x2100fc10, 0xf0041fa0, 0x2100fc0c, 0xf0044620, 0x2100fc08, 
+    0xf0044628, 0x2100fc04, 0xf0044648, 0x2100fc00, 0xf0044658, 0x2100fbfc, 0xf0044630, 0x2100fbf8, 
+    0xf0041d30, 0x1dbefbf4, 0x46302100, 0xfbeff004, 0x2100488f, 0xf004300c, 0x2101fbea, 0xf0044620, 
+    0xf240fbe6, 0x46285140, 0xfbe1f004, 0x6140f640, 0xf0044648, 0xf640fbdc, 0x46500141, 0xfbd7f004, 
+    0x3144f241, 0xf0044658, 0x1f30fbd2, 0x0114f248, 0xfbcdf004, 0xf2481eb0, 0xf0047160, 0xf644fbc8, 
+    0x46303133, 0xfbc3f004, 0xf2401cb0, 0xf0044100, 0x21d0fbbe, 0xe8bd1fa0, 0xf0045ff0, 0xe92dbbb8, 
+    0x48735ff0, 0x011af24a, 0xf0043824, 0x4870fbb0, 0x3100f240, 0xf0043822, 0x486dfbaa, 0x382021ef, 
+    0xfba5f004, 0xf241486a, 0x381c3104, 0xfb9ff004, 0xf2404867, 0x381a1180, 0xfb99f004, 0xf2444864, 
+    0x38160100, 0xfb93f004, 0xf2434861, 0x38140100, 0xfb8df004, 0xf2404c5e, 0x3c121105, 0xf0044620, 
+    0x1ca5fb86, 0x2102f240, 0xf0044628, 0xf104fb80, 0x210f0904, 0xf0044648, 0xf104fb7a, 0xf2400a06, 
+    0x46505100, 0xfb73f004, 0x0b06f105, 0x318ef247, 0xf0044658, 0xf109fb6c, 0xf2410606, 0x46410800, 
+    0xf0044630, 0x1cb7fb64, 0x46384641, 0xfb5ff004, 0xf64a1d30, 0xf0042100, 0x4845fb5a, 0x01fff244, 
+    0xf004300c, 0x1fa0fb54, 0xf0044641, 0x2100fb50, 0xf0041fa0, 0x2100fb4c, 0xf0044620, 0x2100fb48, 
+    0xf0044628, 0x2100fb44, 0xf0044648, 0x2100fb40, 0xf0044650, 0x2100fb3c, 0xf0044658, 0x2100fb38, 
+    0xf0044630, 0x2100fb34, 0xf0044638, 0x2100fb30, 0xf0041d30, 0x482efb2c, 0x300c2100, 0xfb27f004, 
+    0x1116f643, 0xf0044620, 0xf242fb22, 0x4628112e, 0xfb1df004, 0x4648216a, 0xfb19f004, 0x46302100, 
+    0xfb15f004, 0xf2484822, 0x300c0127, 0xfb0ff004, 0x46411fa0, 0xfb0bf004, 0x1fa02100, 0xfb07f004, 
+    0x46202100, 0xfb03f004, 0x46282100, 0xfafff004, 0x46482100, 0xfafbf004, 0x46582100, 0xfaf7f004, 
+    0x46302100, 0xfaf3f004, 0x1d302100, 0xfaeff004, 0x21001dbe, 0xf0044630, 0x480dfaea, 0x300c2100, 
+    0xfae5f004, 0x46202101, 0xfae1f004, 0x5140f240, 0xf0044628, 0xf640fadc, 0x46486140, 0xfad7f004, 
+    0x0141f640, 0xf0044650, 0xf241fad2, 0xe0013144, 0xf2039842, 0xf0044658, 0x1f30faca, 0x0114f248, 
+    0xfac5f004, 0xf2481eb0, 0xf0047160, 0xf644fac0, 0x46303133, 0xfabbf004, 0xf2401cb0, 0xf0044100, 
+    0x21d0fab6, 0xe8bd1fa0, 0xf0045ff0, 0xe92dbab0, 0x48fc4ff0, 0xaf1bb0bd, 0xe887c84e, 0xc84e004e, 
+    0xe887af1f, 0xc84e004e, 0xe887af23, 0xc84e004e, 0xe887af27, 0xc84e004e, 0xe887af2b, 0xc84e004e, 
+    0xe887af13, 0xc84e004e, 0xe887af2f, 0xc80f004e, 0xe886ae17, 0x2002000f, 0xf94df7e5, 0xf7e42000, 
+    0x2000f8e7, 0xfb1af7e4, 0xfe8cf7f1, 0xf7e32001, 0x48e5ff7d, 0xf0042100, 0x48e4fa7a, 0xfa74f004, 
+    0x210148e3, 0xfa73f004, 0xf10d48e2, 0x46bb0aac, 0x0000f990, 0xd07d2801, 0xae1b2803, 0xf10daf1f, 
+    0xf10d088c, 0xd076099c, 0xd0752804, 0xd0742802, 0xfb8ff7ff, 0x46c22000, 0x0804f10d, 0xaa09a905, 
+    0xf856ab0d, 0xf848e020, 0xf857e020, 0xf841c020, 0xf85ac020, 0xf842c020, 0xf859c020, 0xf843c020, 
+    0x1c40c020, 0x2803b2c0, 0x48c9d9eb, 0x220a2300, 0x4100f240, 0xf0043010, 0x4ec5fa54, 0x220c2301, 
+    0x0319362e, 0xf0044630, 0x2301fa4c, 0x220d4630, 0xf0040359, 0x48c0fa46, 0x71fff647, 0xfa27f004, 
+    0x23014ebb, 0x46192200, 0xf0044630, 0x2301fa3a, 0x21024630, 0xf004461a, 0x4eb8fa34, 0xf0044630, 
+    0x49b7fa13, 0xf2408008, 0x46301140, 0xfa0ff004, 0x90002000, 0x46032202, 0xf7f54601, 0x4eaefb9d, 
+    0x22002301, 0x3e104619, 0xf0044630, 0x2300fa1a, 0x21014630, 0xf004461a, 0x4ea3fa14, 0x22032300, 
+    0x21083e0c, 0xf0044630, 0x48a6fa0c, 0xf44f7801, 0xe0030080, 0xe041e020, 0xe081e05f, 0xf8dcf7e0, 
+    0x46302301, 0x21082203, 0xf9fbf004, 0x38384897, 0xf9daf004, 0x28e4b2c0, 0x2003d071, 0x23029000, 
+    0x21002201, 0xf7e64898, 0xf04ff83b, 0xf10d0901, 0x46c80ae4, 0xe094ae3b, 0xfe11f7ff, 0x46522000, 
+    0xf10dab13, 0xf10d095c, 0xae050804, 0xf10daf09, 0xf8520c34, 0xf848e020, 0xf853e020, 0xf8461020, 
+    0xf85b1020, 0xf8471020, 0xf8591020, 0xf84c1020, 0x1c401020, 0x2803b2c0, 0xe766d9eb, 0xfbdbf7ff, 
+    0x46c22000, 0xab05a901, 0x0824f10d, 0x0c34f10d, 0x2020f856, 0x2020f841, 0x2020f857, 0x2020f843, 
+    0xe020f85a, 0xe020f848, 0x2020f859, 0x2020f84c, 0xb2c01c40, 0xd9eb2803, 0xf7ffe747, 0x2000fccb, 
+    0xab134652, 0x095cf10d, 0x0804f10d, 0xaf09ae05, 0x0c34f10d, 0xe020f852, 0xe020f848, 0x1020f853, 
+    0x1020f846, 0x1020f85b, 0x1020f847, 0x1020f859, 0x1020f84c, 0xb2c01c40, 0xd9eb2803, 0xe01de725, 
+    0xfa97f7ff, 0x46c22000, 0xaa05a901, 0x0824f10d, 0xf856ab0d, 0xf841c020, 0xf857c020, 0xf842c020, 
+    0xf85ac020, 0xf848e020, 0xf859e020, 0xf843c020, 0x1c40c020, 0x2803b2c0, 0xe706d9eb, 0x90002000, 
+    0x22022301, 0xe76d2103, 0xb2a0d10b, 0xd1082801, 0x28010c20, 0xb2a8d105, 0xd1022801, 0x28010c28, 
+    0x484ad071, 0xb108f8df, 0x0b10f10b, 0xf2497801, 0xea400000, 0xb2813041, 0xf0044658, 0x4f41f928, 
+    0x7839e004, 0x0080f44f, 0xf816f7e0, 0xf0044658, 0x0500f91b, 0x4836d4f5, 0xf0043012, 0xf8dff915, 
+    0xf10de0e8, 0x0b020bcc, 0x2103f3c0, 0x1703f3c0, 0x3003f99e, 0x0f01f1b9, 0x2013f82b, 0x2002f99e, 
+    0x1012f82b, 0x1001f99e, 0x7011f82b, 0x070ff000, 0x0000f99e, 0x7010f82b, 0xf1b9d008, 0xd0270f02, 
+    0xfc84fa1f, 0x0f00f1bc, 0xe081d071, 0x0c44f10d, 0xe013f83b, 0xe013f82c, 0xe012f83b, 0xe012f82c, 
+    0xe011f83b, 0xe011f82c, 0x7010f82c, 0xf8262700, 0xf8267010, 0xf3677011, 0xf367040f, 0xf826050f, 
+    0xf3677012, 0xf367441f, 0xf826451f, 0xe09c7013, 0x0c44f10d, 0xe010f83c, 0xd10545be, 0x7010f826, 
+    0x040ff368, 0xe098e002, 0x7010f82a, 0x7011f83c, 0xf83b46de, 0x42870011, 0xf368d11a, 0xf826441f, 
+    0xe0170011, 0x0002eb1c, 0xf203900c, 0xf23c804a, 0xf2039800, 0x000425c2, 0xf23c8310, 0xf38fffc0, 
+    0x000432ec, 0x00040293, 0x00042598, 0x000425c0, 0x0011f82a, 0x7012f83c, 0xf83e4671, 0x42870012, 
+    0xf826d104, 0xf3680012, 0xe001050f, 0x0012f82a, 0x2013f83c, 0x0013f831, 0xd1044282, 0x451ff368, 
+    0x0013f826, 0xf82ae051, 0xe04e0013, 0xf83ae7ff, 0x4567c010, 0xf10dd005, 0xf83c0c44, 0x4567c010, 
+    0xf826d104, 0xf3687010, 0xe001040f, 0xc010f826, 0xd1110c20, 0x0011f83b, 0x7011f83a, 0xd00442b8, 
+    0xf837af11, 0x42b87011, 0xf368d104, 0xf826441f, 0xe0010011, 0x7011f826, 0x0c000428, 0xf83bd111, 
+    0xf83a0012, 0x42881012, 0xa911d004, 0x1012f831, 0xd1044288, 0x0012f826, 0x050ff368, 0xf826e001, 
+    0x0c281012, 0xf83bd111, 0xf83a0013, 0x42881013, 0xa911d004, 0x1013f831, 0xd1044288, 0x451ff368, 
+    0x0013f826, 0xf826e001, 0xf1091013, 0xf0000001, 0xf1b909ff, 0xf67f0f03, 0xf04faee7, 0x465d0000, 
+    0x1010f836, 0x1010f825, 0x0001f100, 0x2803b2c0, 0xf8dfd9f6, 0x24008300, 0xae354fbf, 0x0044eb08, 
+    0xf812f004, 0x0103f1c4, 0xb2e41c64, 0x2c035679, 0x0011f826, 0x2400d9f2, 0x46b846a9, 0xf918af37, 
+    0xf8395004, 0x28020015, 0x2803d042, 0x2804d040, 0xf836d03e, 0xf0060015, 0xa909fd3f, 0x1025f851, 
+    0xfd4ef006, 0xf851a90d, 0xf0061025, 0xf006fbb7, 0x1c64fcfb, 0x2c03b2e4, 0x0015f827, 0x4da7d9df, 
+    0x4ea72400, 0x0864f04f, 0x1014f837, 0xb1087828, 0xf1f8fbb1, 0x0044eb06, 0xffd9f003, 0xb2e41c64, 
+    0xd9f12c03, 0x10ccf8bd, 0x00d2f8bd, 0x20d0f8bd, 0x3001ea40, 0x10cef8bd, 0xea410209, 0x43081102, 
+    0x4897b281, 0xf0031e80, 0xb03dffc2, 0x8ff0e8bd, 0x0015f836, 0xfd00f006, 0xf851a901, 0xf0061025, 
+    0xa905fd0f, 0xe92de7bf, 0x460447f0, 0xf8df8e80, 0xf2408234, 0x4d8c6676, 0xf2a042b0, 0xf2406176, 
+    0xd0746743, 0x42b8dc17, 0x6143f2a0, 0xdc0dd037, 0x1c48b300, 0x6868d131, 0xf1052200, 0xf7fe0108, 
+    0x1d41fdb9, 0x2801d028, 0xe028d11a, 0xd07d2925, 0xd1222926, 0x290de014, 0xdc0cd012, 0xd00f2901, 
+    0xd11a290c, 0x22004978, 0x31086868, 0xfd73f7fe, 0xd06c1d40, 0x292ae004, 0x292bd06a, 0xe0b9d10d, 
+    0xf04f4971, 0x686832ff, 0xf7fe3108, 0x1d01fd93, 0xf240d1d7, 0xe0bd6042, 0xe8bd86a7, 0x4b6a87f0, 
+    0x52c0f04f, 0x5000f04f, 0xf9b33308, 0x29661000, 0x2968d02e, 0x2969d05f, 0x2967d07b, 0x4699d1e0, 
+    0xfdeff7d8, 0x2300485b, 0x461a2101, 0xf0033814, 0x495eff68, 0x23012000, 0x70082200, 0x8801485c, 
+    0x0110f021, 0x485b8001, 0xf0034619, 0x2000ff5a, 0xf844f7e6, 0xf8a92107, 0x49531000, 0xf8d82200, 
+    0x31080000, 0xfd27f7fe, 0xd0671d01, 0xe045e070, 0xf7d84699, 0xf8dffdc6, 0x4650a140, 0xff24f003, 
+    0xb2811c40, 0xf0034650, 0x2004ff22, 0xfef0f7df, 0x7801484a, 0x2000f44f, 0xfe0ef7df, 0xf8a92168, 
+    0x49411000, 0x68682200, 0xe0023108, 0xe042e008, 0xf7fee047, 0x1d01fd00, 0xf240d108, 0xe0596068, 
+    0x22004939, 0x31086868, 0xfcf5f7fe, 0xd1871d40, 0x6069f240, 0x4699e04e, 0xfd93f7d8, 0xfc47f7ff, 
+    0xf8a92169, 0x49301000, 0x68682200, 0xf7fe3108, 0x1d01fce2, 0x86a6d108, 0xe00ae77f, 0x2200492a, 
+    0x31086868, 0xfcd7f7fe, 0xd1871d40, 0x6077f240, 0x4699e030, 0xfd75f7d8, 0xf8a92167, 0x49221000, 
+    0x68682200, 0xf7fe3108, 0x1d01fcc6, 0xaf50f47f, 0x6082f240, 0xf240e01e, 0xe01b6083, 0x60a0f240, 
+    0x4919e018, 0xf8d82200, 0x31080000, 0xfcb3f7fe, 0xd00d1d40, 0xfd17f7e5, 0x48198829, 0xfeb7f003, 
+    0x23004818, 0xf640220b, 0xf0030100, 0xe737feca, 0x60a1f240, 0xe74086a0, 0x21012200, 0xf2afb510, 
+    0xf7fe2019, 0x2108fae3, 0xf7fe2002, 0x4906fc41, 0xbd106048, 0xf2039814, 0x00042598, 0x000425c1, 
+    0xf203512e, 0x0004274c, 0x000432ec, 0x000402b2, 0x00040290, 0xf38f20e0, 0xf2039ffe, 0x00040293, 
+    0xf38fffc0, 0xf23c800c, 0x4cfeb510, 0x22052301, 0x46202120, 0xfe95f003, 0x46202301, 0x21402206, 
+    0xfe8ff003, 0xe8bd2100, 0x20044010, 0xbd64f7df, 0x4cf4b510, 0x22042301, 0x2110347e, 0xf0034620, 
+    0x2303fe80, 0x22024620, 0xf003210c, 0x2302fe7a, 0x22004620, 0x4010e8bd, 0xf0032103, 0xb510be72, 
+    0x23014ce8, 0x21042202, 0xf0034620, 0x2301fe6a, 0x21024620, 0xf003461a, 0x2301fe64, 0x22004620, 
+    0xf0034619, 0x2100fe5e, 0x4010e8bd, 0xf7df2004, 0x48ddbd33, 0x31b6f64b, 0xf003b510, 0x4cdbfe38, 
+    0xf7ff7820, 0x7820ffdc, 0xffc2f7ff, 0xf7ff7820, 0x48d4ffab, 0x0145f64a, 0xf00330c8, 0x48d1fe28, 
+    0x015cf64a, 0x4010e8bd, 0xf00330cc, 0xe92dbe20, 0x460441f0, 0xf24f48ce, 0x44200700, 0x23044639, 
+    0x220c4605, 0xfe2df003, 0x46282308, 0x461a113e, 0xf0034631, 0x2308fe26, 0x22044628, 0xf00321f0, 
+    0x2308fe20, 0x22004628, 0xf003210f, 0x48c0fe1a, 0x220c2309, 0x1c804639, 0x46054420, 0xfe11f003, 
+    0x46312309, 0x46282208, 0xfe0bf003, 0x46282304, 0x461a21f0, 0xfe05f003, 0x46282300, 0x461a210f, 
+    0xfdfff003, 0xf64348b2, 0x231976ff, 0x30d24631, 0x44202200, 0xfdf5f003, 0xf64148ad, 0x230678ff, 
+    0x30d44641, 0x44202200, 0xfdebf003, 0xf64f48a8, 0x23017500, 0x30d64629, 0x22084420, 0xf0034607, 
+    0x2300fde0, 0x21ff4638, 0xf003461a, 0x48a0fdda, 0x213f2300, 0x30d8461a, 0xf0034420, 0x489cfdd2, 
+    0x23051177, 0x30624639, 0x44202200, 0xfdc9f003, 0x237d4897, 0x46312200, 0x442030c8, 0xfdc1f003, 
+    0x231f4893, 0x46392200, 0x44203060, 0xfdb9f003, 0x2332488f, 0x46312200, 0x442030cc, 0xfdb1f003, 
+    0x2331488b, 0x46412200, 0x442030d0, 0xf0034606, 0x4887fda8, 0x22082301, 0x30ca4629, 0x46054420, 
+    0xfd9ff003, 0x46282300, 0x461a21ff, 0xfd99f003, 0x231f487f, 0x46412200, 0x442030ce, 0xf0034604, 
+    0xf24efd90, 0x46300500, 0x46292300, 0xf003220d, 0x4629fd88, 0xe8bd4620, 0x230041f0, 0xf003220d, 
+    0xe92dbd80, 0x46054ff8, 0x2400486f, 0x220b4616, 0x0100f640, 0x94003882, 0xfd81f003, 0xf010496d, 
+    0xd0060fff, 0xd0332d03, 0xd0112d05, 0xd00f2d04, 0x2d03e010, 0x2d05d014, 0x2d04d001, 0x2e02d101, 
+    0x7808d00e, 0xd1012801, 0xd0092d02, 0xe0072401, 0xd01d2e02, 0x28017808, 0x2d02d101, 0x2405d018, 
+    0xf8df4e5e, 0xf24f9174, 0x1cb70500, 0x0800f244, 0x3afff240, 0x7bfff643, 0x2c01b164, 0xf8dfd053, 
+    0x2c04815c, 0x080cf108, 0x2c05d07d, 0xe106d17c, 0xe7e52404, 0x46292305, 0x4648220c, 0xfd31f003, 
+    0x46412301, 0x4630220e, 0xfd2bf003, 0x46382302, 0x21062201, 0xfd25f003, 0x46512319, 0x46302200, 
+    0xfd1ff003, 0x22004845, 0x2300f243, 0x1e804659, 0xfd17f003, 0x23004841, 0x4629220c, 0xf0031f00, 
+    0x483efd10, 0x22042300, 0x380c2110, 0xfd09f003, 0x4638230f, 0x21782203, 0xfd03f003, 0x23034837, 
+    0x210f2200, 0xf003380e, 0x4834fcfc, 0x22092300, 0x6100f640, 0xf0033810, 0x2300fcf4, 0x0100f248, 
+    0x4630220f, 0x9800e0b7, 0xfeb1f7ff, 0x46292305, 0x4648220c, 0xfce5f003, 0x46412301, 0x4630220e, 
+    0xfcdff003, 0x46382302, 0x21062201, 0xfcd9f003, 0x4651231f, 0x46302200, 0xfcd3f003, 0x2200481f, 
+    0x0300f241, 0x1e804659, 0xfccbf003, 0x2300481b, 0x4629220c, 0xf0031f00, 0x4818fcc4, 0x22042300, 
+    0x380c2110, 0xe040e001, 0xf003e030, 0x230ffcba, 0x22034638, 0xf0032178, 0x4810fcb4, 0x22002303, 
+    0x380e210f, 0xfcadf003, 0x2300480c, 0xf6402209, 0x38106100, 0xfca5f003, 0xf2482300, 0x220f0100, 
+    0xe0b54630, 0xf3074004, 0xf23c80ba, 0x00042380, 0xf3072402, 0x00042325, 0xf3072200, 0xf303a170, 
+    0x220e48f6, 0x0100f24c, 0xfc8bf003, 0x46382300, 0x461a2101, 0xfc85f003, 0x4638b001, 0x22002301, 
+    0xe8bd4619, 0xf0034ff0, 0x2303bc7c, 0x220c4629, 0xf0034648, 0x2342fc76, 0x22004651, 0xf0034630, 
+    0x2300fc70, 0x461a48e6, 0xf0034659, 0x48e4fc6a, 0x220c2300, 0x1e804629, 0xfc63f003, 0x230048e0, 
+    0x21102204, 0xf003380a, 0x230ffc5c, 0x22034638, 0xf0032178, 0x48dafc56, 0x2200230d, 0x380c210f, 
+    0xfc4ff003, 0x230248d6, 0xf6402209, 0x380e6100, 0xfc47f003, 0xf2482300, 0x220f0100, 0xf0034630, 
+    0x2300fc40, 0x22014640, 0xf0032102, 0x2300fc3a, 0x21014640, 0xf003461a, 0x2302fc34, 0x9800e7a0, 
+    0xfdf5f7ff, 0x46292303, 0x4648220c, 0xfc29f003, 0x46512350, 0x46302200, 0xfc23f003, 0x48c02300, 
+    0x4659461a, 0xfc1df003, 0x230048bd, 0x4629220c, 0xf0031e80, 0x48bafc16, 0x22042300, 0x380a2110, 
+    0xfc0ff003, 0x4638230f, 0x21782203, 0xfc09f003, 0x230d48b3, 0x210f2200, 0xf003380c, 0x48b0fc02, 
+    0x22092302, 0x6100f640, 0xf003380e, 0x2300fbfa, 0x0100f248, 0x4630220f, 0xfbf3f003, 0x46402300, 
+    0x21022201, 0xfbedf003, 0x46402300, 0x461a2101, 0xfbe7f003, 0xe7532301, 0xb149b430, 0x46034ca1, 
+    0x2200489f, 0x386c2101, 0xbc304420, 0xbbd9f003, 0xe7f42400, 0x460db570, 0x4c9ab19a, 0x460334c0, 
+    0x22004897, 0x30582101, 0xf0034420, 0x4894fbca, 0x21012200, 0x3038462b, 0xe8bd4420, 0xf0034070, 
+    0x2400bbc0, 0xb430e7eb, 0x4c8eb149, 0x488c4603, 0x21012200, 0x44203852, 0xf003bc30, 0x2400bbb2, 
+    0xb430e7f4, 0x4c88b151, 0x48854603, 0xf242220d, 0x307a0100, 0xbc304420, 0xbba3f003, 0xe7f32400, 
+    0x5ffce92d, 0x4605000f, 0x4690469b, 0xf44fd012, 0xf8df1400, 0xf24091f8, 0x46282a00, 0xfe11f7ff, 
+    0x21004a7b, 0x1c902362, 0x0f00f1bb, 0x80018011, 0xe011d002, 0xe7ec2400, 0xd00b2d03, 0xd0012d05, 
+    0xd1022d04, 0x0f02f1b8, 0x2138d004, 0x21a88011, 0xe0028001, 0x80112126, 0x46238003, 0xf0218811, 
+    0x80110101, 0xf4228802, 0xf04f7680, 0x80060202, 0xb1074650, 0xf0014631, 0x2000fbef, 0xf7ff4639, 
+    0x2001ff7b, 0xf7ff4639, 0x2000ffac, 0xf7ff4639, 0x4860ff9a, 0x21012300, 0x4420461a, 0xf0039001, 
+    0x485cfb50, 0x22012300, 0x44203848, 0x21024682, 0xf0034656, 0x2300fb46, 0x21014630, 0xf003461a, 
+    0x2001fb40, 0xf7ff4639, 0x2f01ff7e, 0x484cd004, 0x30582102, 0xfb1bf003, 0x0f00f1bb, 0x484ed17e, 
+    0x28017800, 0x2d03d103, 0x2d02d02a, 0x4849d028, 0x23002208, 0x01513052, 0xf0034420, 0x4847fb22, 
+    0x220b2300, 0x0100f640, 0x46064420, 0xfb19f003, 0x46302301, 0x21402206, 0xfb13f003, 0xf2402300, 
+    0x220a4100, 0xf0034630, 0x2d03fb0c, 0x2d05d07a, 0x2d04d079, 0x2d02d078, 0x2d01d077, 0xe0fed076, 
+    0x220c4836, 0x44202302, 0x46800291, 0xfaf9f003, 0xf2414833, 0x442001ee, 0xfad9f003, 0xf24a4830, 
+    0x1c800100, 0xf0034420, 0x482dfad2, 0x31b8f640, 0x44201d00, 0xfacbf003, 0xf6414829, 0x1d803100, 
+    0xf0034420, 0x4826fac4, 0x2635f248, 0x30084631, 0xf0034420, 0x4822fabc, 0x300a4631, 0xf0034420, 
+    0x481ffab6, 0x300e4631, 0xf0034420, 0x481cfab0, 0x3012210f, 0xf0034420, 0x4816faaa, 0x2205231c, 
+    0x31e0f240, 0x4420305c, 0xf0039000, 0x4e11faba, 0x2d03365e, 0x2d02d003, 0xe035d029, 0xf04fe0b6, 
+    0x210c4260, 0xf7d81750, 0x19a0f92c, 0x46062301, 0x21082203, 0xfaa5f003, 0xe0202300, 0xf23c8022, 
+    0xf303a16e, 0x00200060, 0x002001c0, 0x0004e200, 0x000432fc, 0xf30788ae, 0x00042325, 0xf3078616, 
+    0xf30724a6, 0xe02ae029, 0xe0afe058, 0x19a0e0b0, 0x46062300, 0x21082203, 0xfa83f003, 0x46302301, 
+    0x21202205, 0xfa7df003, 0x23019800, 0x211f2200, 0xfa77f003, 0x220848f8, 0x01512301, 0xf0034420, 
+    0x2300fa70, 0x0100f640, 0x4640220b, 0xfa69f003, 0x46402300, 0x21402206, 0x230fe05f, 0x48efe011, 
+    0x0f01f1b8, 0xf1b8d003, 0xd00e0f02, 0x7800e057, 0xf04f2120, 0xea414260, 0x17502100, 0xf8d1f7d8, 
+    0x46302320, 0x213f2200, 0x7800e047, 0xf04f2121, 0xea414260, 0x17502100, 0xf8c3f7d8, 0x46302329, 
+    0x213f2200, 0xfa3df003, 0xd0382f01, 0x230148dc, 0x210f2200, 0xfa35f003, 0xe02a2301, 0xf1b848d9, 
+    0xd0030f01, 0x0f02f1b8, 0xe028d00b, 0x21107800, 0x4260f04f, 0x2100ea41, 0xf7d81750, 0x2321f8a2, 
+    0x7800e7cf, 0xf04f2111, 0xea414260, 0x17502100, 0xf897f7d8, 0x46302328, 0x213f2200, 0xfa11f003, 
+    0xd00c2f01, 0x230448c6, 0x210f2200, 0xfa09f003, 0x48c32304, 0x210f2200, 0xf0031d00, 0x48c2fa02, 
+    0x22072301, 0x44202180, 0xf9fbf003, 0x230148bf, 0x461a2102, 0xf0034420, 0xf899f9f4, 0x463a1021, 
+    0x0022f899, 0xfe16f7ff, 0x230048b9, 0x21022201, 0xf0034420, 0x49b7f9e6, 0x1c882200, 0x8002800a, 
+    0xf1bb2204, 0xd0050f00, 0xe0182224, 0xe7882302, 0xe7862301, 0x781b4bb0, 0xd1032b01, 0xd0622d03, 
+    0xd0602d02, 0x800b2314, 0xd0042d04, 0xd0022d02, 0xd0002d01, 0x88028002, 0x0260f022, 0x80023220, 
+    0xb291b3ef, 0x3000f240, 0x46232202, 0xfa44f001, 0x780048a1, 0x2d03b108, 0x463ad004, 0x46484629, 
+    0xff89f001, 0x23004d99, 0xf244220e, 0x3da60100, 0xf0034628, 0x2301f9a6, 0x220d4628, 0xf0030359, 
+    0x2301f9a0, 0x220c4628, 0xf0030319, 0xf999f99a, 0x22000020, 0xb283210f, 0x3882488c, 0xf991f003, 
+    0x46502301, 0x461a2102, 0xf98bf003, 0x46502301, 0x46192200, 0xf985f003, 0x46392001, 0xe015e000, 
+    0xfd9af7ff, 0x98012301, 0x46192200, 0xf979f003, 0x23014879, 0x21042202, 0x3860b002, 0xe8bd4420, 
+    0xf0035ff0, 0x2203b96e, 0xe7a8800a, 0xe7a98809, 0x5ff0e92d, 0x23014d79, 0x46042205, 0x46282120, 
+    0xf95ff003, 0xf2402c03, 0xf24441df, 0xd0080600, 0xd0092c05, 0xd00f2c04, 0xd0742c02, 0xd0742c01, 
+    0xf240e016, 0xe0014310, 0x4308f240, 0x22004628, 0xf947f003, 0xe0062300, 0xf2402200, 0x46284304, 
+    0xf93ff003, 0x46312301, 0x4628220e, 0xf939f003, 0x23014862, 0x21202205, 0xf0031c80, 0xf8dff932, 
+    0x2301a17c, 0x46192200, 0x0a0af10a, 0xf0034650, 0x2301f928, 0x0b04f10a, 0x22004619, 0xf0034658, 
+    0x2301f920, 0x0502f1aa, 0x22004619, 0xf0034628, 0x2301f918, 0x46191d2e, 0x46302200, 0xf911f003, 
+    0xf6412c03, 0xf2406800, 0xd03019e0, 0xd02e2c05, 0xd02c2c04, 0x2c024f4a, 0x2c01d058, 0xf64fd173, 
+    0x46540500, 0x46292306, 0x4650220b, 0xf8f9f003, 0x46292306, 0x465d220b, 0xf0034658, 0x2300f8f2, 
+    0x22054620, 0xf0032120, 0x2300f8ec, 0x22054628, 0xf0032120, 0x7839f8e6, 0xd0732901, 0xd0722900, 
+    0xe000e0aa, 0x2382e001, 0x2341e790, 0x2302e78e, 0x22094641, 0xf0034628, 0x2302f8d4, 0x22094641, 
+    0xf0034630, 0x2303f8ce, 0x2205464c, 0x46284649, 0xf8c7f003, 0x46212303, 0x46302205, 0xf8c1f003, 
+    0x46282301, 0x21102204, 0xf8bbf003, 0x46302301, 0x21102204, 0xf8b5f003, 0x46282303, 0x210e2201, 
+    0xf8aff003, 0x22012303, 0xe053210e, 0x46412303, 0x46282209, 0xf8a5f003, 0x46412303, 0x46302209, 
+    0xf89ff003, 0x46282300, 0x21102204, 0xf899f003, 0x46302300, 0x21102204, 0xf893f003, 0x28017838, 
+    0xb308d002, 0xe073e02c, 0x46282302, 0x210e2201, 0xf887f003, 0xe01e2304, 0xf3078900, 0x00042327, 
+    0xf3072400, 0x00042326, 0xf3078616, 0xf303a1c6, 0xf302012c, 0x00043300, 0x00042325, 0xf3074080, 
+    0x00042381, 0xe02be024, 0x46282300, 0x210e2201, 0xf867f003, 0x46302302, 0x210e2201, 0xf861f003, 
+    0x464c2303, 0x46492205, 0xf0034628, 0x2303f85a, 0x22054621, 0xf0034630, 0x2300f854, 0x21014628, 
+    0xf003461a, 0x2300f84e, 0x21014630, 0xe02b461a, 0x46202304, 0x211e2201, 0xf843f003, 0xe0062304, 
+    0x46202302, 0x211e2201, 0xf83bf003, 0x46282302, 0x211e2201, 0xf835f003, 0xf2402306, 0x461a76c0, 
+    0x46204631, 0xf82df003, 0x46312306, 0x4628461a, 0xf827f003, 0x46202300, 0x461a2101, 0xf821f003, 
+    0x46282300, 0x461a2101, 0x5ff0e8bd, 0xb819f003, 0x9ff0e8bd, 0xb151b430, 0x1420f04f, 0x22004603, 
+    0x31fff240, 0x442048fe, 0xf003bc30, 0x2400b80a, 0xb430e7f4, 0xf04fb151, 0x46031420, 0x220048f8, 
+    0x1f802101, 0xbc304420, 0xbffbf002, 0xe7f42400, 0x0005b570, 0xf44fd036, 0x20011400, 0xf0014621, 
+    0x2000f8a9, 0xf7ff4629, 0x2001ffe4, 0xf7ff4629, 0x4629ffe0, 0x10f4f240, 0xffccf7ff, 0x46212000, 
+    0xf898f001, 0xf44f2100, 0xf7de1080, 0x2100feb5, 0x2080f44f, 0xfeb0f7de, 0x230148e2, 0x46192200, 
+    0xf0024420, 0x4ce0ffce, 0x22042300, 0x46202110, 0xffc7f002, 0xe8bd4620, 0x23014070, 0x21102204, 
+    0xbfbff002, 0xe7c82400, 0x48d72300, 0x21082203, 0xbfb7f002, 0x41f0e92d, 0x4ed44cd4, 0x36081f25, 
+    0xb1d91d27, 0x78e6f640, 0x46414638, 0xff8ff002, 0x46284641, 0xff8bf002, 0x46304641, 0xff87f002, 
+    0x46204641, 0xff83f002, 0x46282302, 0x21382203, 0xff97f002, 0x22032302, 0xe0772138, 0x0300f04f, 
+    0x0101f04f, 0x461a2801, 0x4628d046, 0xff89f002, 0x46382300, 0x461a2101, 0xff83f002, 0x46282301, 
+    0x461a2102, 0xff7df002, 0x46382301, 0x461a2102, 0xff77f002, 0x46382300, 0x21382203, 0xff71f002, 
+    0x46282304, 0x21382203, 0xff6bf002, 0x46382300, 0x21042202, 0xff65f002, 0x46282300, 0x21042202, 
+    0xff5ff002, 0x46202301, 0x46192200, 0xff59f002, 0x46302301, 0x46192200, 0xff53f002, 0x46282301, 
+    0x46192200, 0xff4df002, 0xe8bd4638, 0x230141f0, 0x46192200, 0xbf45f002, 0xf0024620, 0x2300ff42, 
+    0x21014630, 0xf002461a, 0x2301ff3c, 0x21024620, 0xf002461a, 0x2301ff36, 0x21024630, 0xf002461a, 
+    0x2300ff30, 0x22034630, 0xf0022138, 0x2304ff2a, 0x22034620, 0xf0022138, 0x2300ff24, 0x22024630, 
+    0xf0022104, 0x2300ff1e, 0x21042202, 0xe7b74620, 0x41f0e92d, 0x460c2203, 0x46052138, 0xf0024884, 
+    0xf8dfff1e, 0x4f81c208, 0x0c3cf1ac, 0x0604f10c, 0xf1a63f14, 0xb1550e06, 0xd0212d01, 0xd1622d02, 
+    0xd0472c01, 0xd0562804, 0xd0542802, 0x2c01e005, 0x2804d006, 0x2802d012, 0x2801d010, 0xe050d00e, 
+    0xd0032804, 0xd0012802, 0xd1052801, 0x46602302, 0x211e2201, 0xfee5f002, 0xe0172302, 0xe03b2302, 
+    0xd0062c01, 0xd0152804, 0xd0132802, 0xd0132801, 0x2804e018, 0x2802d003, 0x2801d001, 0x2304d105, 
+    0x22014660, 0xf002211e, 0x2304fecc, 0x22014630, 0xe00b211e, 0xe0002303, 0x46702304, 0x210e2201, 
+    0xfebff002, 0x46382302, 0x210e2201, 0x41f0e8bd, 0xbeb7f002, 0xd0042804, 0xd0022802, 0xd0022801, 
+    0x2301e007, 0x2302e000, 0x22014660, 0xf002211e, 0x2301fea8, 0x2301e7da, 0x22014670, 0xf002210e, 
+    0x2301fea0, 0xe8bde7df, 0xb57081f0, 0x48464604, 0x0100f244, 0x2c04307c, 0x2c05d01a, 0x2300d018, 
+    0xf002220e, 0x4d41fe8e, 0x220d2301, 0x03593d40, 0xf0024628, 0x2c01fe86, 0x0100f241, 0x2c02d00a, 
+    0x2c03d008, 0x2c05d008, 0x2c04d006, 0xe008d004, 0xe7e52301, 0xe0002300, 0x46282301, 0xf002220c, 
+    0x2300fe70, 0x22034628, 0xf0022108, 0x2301fe6a, 0x22024628, 0xf0022104, 0x2301fe64, 0x22004628, 
+    0xf0024619, 0x4d29fe5e, 0x22052301, 0x21203d3a, 0xf0024628, 0x2301fe56, 0x22044628, 0xf0022110, 
+    0x2c01fe50, 0x2c02d001, 0x4822d109, 0x78004621, 0xff2ef7ff, 0x78014820, 0xf7ff4620, 0xe8bdfe8b, 
+    0x23014070, 0x22034818, 0xf0022108, 0xe92dbe3a, 0x4d1647f0, 0xf248460c, 0xf6400100, 0x3d366900, 
+    0x1a00f240, 0xf04f10cf, 0x28000300, 0x020ff04f, 0x460ed07e, 0xf0024628, 0xf8dffe24, 0x2300802c, 
+    0xf1082205, 0x2120087e, 0xf0024640, 0x2301fe1a, 0x220c4639, 0xf0024628, 0xb2a3fe14, 0xe00d2209, 
+    0xf303a1e8, 0xf3072200, 0xf3074004, 0xf30741c0, 0xf23c8040, 0x00042381, 0x0004255e, 0x46284649, 
+    0xfdfff002, 0x46512301, 0x46282208, 0xfdf9f002, 0x46282301, 0x46192200, 0xfdf3f002, 0x46312301, 
+    0x4628220f, 0xfdedf002, 0x46402301, 0x21202205, 0xfde7f002, 0x23014c54, 0x02592209, 0xf0024620, 
+    0x2300fde0, 0x22084651, 0xf0024620, 0xf244fdda, 0x46200500, 0x46292300, 0xf002220e, 0x484bfdd2, 
+    0x28008800, 0x484ad059, 0xb3e88800, 0xf2404846, 0x46311687, 0xf0023040, 0x4843fdaa, 0x30424631, 
+    0xfda5f002, 0x46314840, 0xf0023044, 0x483efda0, 0x30462165, 0xfd9bf002, 0x00b1483b, 0xf0023048, 
+    0x2301fd96, 0x220e4629, 0xf0024620, 0xe000fdaa, 0x2301e00d, 0x22024620, 0xf0022104, 0x2301fda2, 
+    0xe8bd4620, 0x220147f0, 0xf0022102, 0x4628bd9a, 0xfd97f002, 0x46392301, 0x4628220c, 0xfd91f002, 
+    0x4649b2a3, 0xe0002209, 0x4628e00d, 0xfd89f002, 0x46512301, 0x46282208, 0xfd83f002, 0x46282301, 
+    0x46192200, 0x230ae794, 0x22044620, 0xf00221f0, 0x2301fd78, 0x21082203, 0x2300e7c6, 0x22024620, 
+    0xf0022104, 0x2300fd6e, 0xb510e7ca, 0x22044c19, 0x46202110, 0xfd73f002, 0xd0162801, 0x46202203, 
+    0xf0022108, 0x2801fd6c, 0x2202d011, 0x21044620, 0xfd65f002, 0xd00c2801, 0x46202201, 0xf0022102, 
+    0x2801fd5e, 0x2001d007, 0x2003bd10, 0x2005bd10, 0x2004bd10, 0x2002bd10, 0x4603bd10, 0x22044802, 
+    0x380c2110, 0xbd3df002, 0xf307418c, 0x0004237e, 0x00042578, 0xf3074080, 0x5ff0e92d, 0xf7e32003, 
+    0x2301fbda, 0x220948fb, 0xf0020259, 0x4cfafd2a, 0x21022301, 0x4620461a, 0xfd23f002, 0x46202301, 
+    0x21042202, 0xfd1df002, 0x83ccf8df, 0xf2402500, 0xf6434700, 0xf1087bff, 0xf240080e, 0xf6407aff, 
+    0x24000900, 0x23014639, 0x220a4640, 0xfd09f002, 0xeb0448ea, 0x220006c5, 0xf8304659, 0xb2830026, 
+    0x301448e5, 0xfcfdf002, 0x4ee3b2b3, 0x46512200, 0x46303612, 0xfcf5f002, 0x46392300, 0x4640220a, 
+    0xfceff002, 0x46492301, 0x4630220b, 0xfce9f002, 0xb2a41c64, 0xd3d52c08, 0xb2ad1c6d, 0xd3d02d80, 
+    0xa35cf8df, 0xf8df2580, 0x24009350, 0x0912f109, 0x23014639, 0x220a4640, 0xfcd3f002, 0x06c5eb04, 
+    0x22004659, 0x0086eb0a, 0x5080f5a0, 0xb2838800, 0x301448c9, 0xfcc5f002, 0xf240b2b3, 0x220071ff, 
+    0x4648464e, 0xfcbdf002, 0x46392300, 0x4640220a, 0xfcb7f002, 0x46302301, 0x02d9220b, 0xfcb1f002, 
+    0xb2a41c64, 0xd3d32c08, 0xb2ad1c6d, 0xd9ca2dff, 0x46392301, 0x4640220a, 0xfca3f002, 0x230048b5, 
+    0xf2402209, 0xf0022100, 0xe8bdfc9c, 0x200c5ff0, 0xbb41f7e3, 0x4cb3b510, 0x21022201, 0xf0024620, 
+    0x2800fc9e, 0xf7ffd109, 0x2301ff57, 0xe8bd4620, 0x21024010, 0xf002461a, 0xbd10bc84, 0x41f0e92d, 
+    0x23014ca5, 0x461a2102, 0x46203430, 0xfc79f002, 0x46202301, 0x21042202, 0xfc73f002, 0x5507f643, 
+    0x76fff643, 0x462b2200, 0x46311ca0, 0xfc69f002, 0x46312300, 0x461a1d20, 0xfc63f002, 0x2788f640, 
+    0x22004631, 0x1da0463b, 0xfc5bf002, 0xf2414892, 0x220008e2, 0x30384643, 0xf0024631, 0x488efc52, 
+    0x463b2200, 0x303a4631, 0xfc4bf002, 0x2300488a, 0x4631461a, 0xf002303c, 0x4887fc44, 0x462b2200, 
+    0x303e4631, 0xfc3df002, 0x23004883, 0x4631461a, 0xf0023040, 0x4880fc36, 0x462b2200, 0x30424631, 
+    0xfc2ff002, 0x2300487c, 0x4631461a, 0xf0023044, 0x4879fc28, 0x463b2200, 0x30464631, 0xfc21f002, 
+    0x22004875, 0x46314643, 0xf0023048, 0x4872fc1a, 0x463b2200, 0x304a4631, 0xfc13f002, 0x2300486e, 
+    0x4631461a, 0xf002304c, 0x486bfc0c, 0x462b2200, 0x304e4631, 0xfc05f002, 0x23004867, 0x4631461a, 
+    0xf0023050, 0x4864fbfe, 0x462b2200, 0x30524631, 0xfbf7f002, 0x23004860, 0x4631461a, 0xf0023054, 
+    0x485dfbf0, 0x463b2200, 0x30564631, 0xfbe9f002, 0x22004859, 0x46314643, 0xf0023058, 0x4856fbe2, 
+    0x463b2200, 0x305a4631, 0xfbdbf002, 0x23004852, 0x4631461a, 0xf002305c, 0x484ffbd4, 0x462b2200, 
+    0x305e4631, 0xfbcdf002, 0x2300484b, 0x4631461a, 0xf0023060, 0x4848fbc6, 0x462b2200, 0x30624631, 
+    0xfbbff002, 0x23004844, 0x4631461a, 0xf0023064, 0x4841fbb8, 0x463b2200, 0x30664631, 0xfbb1f002, 
+    0x2200483d, 0x46314643, 0xf0023068, 0x483afbaa, 0x463b2200, 0x306a4631, 0xfba3f002, 0x23004836, 
+    0x4631461a, 0xf002306c, 0x4833fb9c, 0x462b2200, 0x306e4631, 0xfb95f002, 0x2300482f, 0x4631461a, 
+    0xf0023070, 0x4620fb8e, 0x41f0e8bd, 0x22032301, 0xf0022108, 0x492cbb86, 0x7809b510, 0xd1552900, 
+    0x1d244c25, 0x2801b1f8, 0x2802d025, 0xf04f460b, 0xf04f0204, 0x46200110, 0xf002d031, 0x2300fb72, 
+    0x22054620, 0xf0022120, 0x2300fb6c, 0x22064620, 0xf0022140, 0x2301fb66, 0x22074620, 0x4010e8bd, 
+    0xf0022180, 0x2301bb5e, 0x22044620, 0xf0022110, 0x2300fb58, 0x2300e006, 0x22044620, 0xf0022110, 
+    0x2301fb50, 0x22054620, 0xf0022120, 0x2300fb4a, 0x22064620, 0xf0022140, 0x2300fb44, 0xf002e7dc, 
+    0x2300fb40, 0x22054620, 0xf0022120, 0x2301fb3a, 0x0000e7ee, 0xf23c8310, 0xf2030a00, 0x00040300, 
+    0x00041300, 0xf23d0008, 0x0004257a, 0xb570bd10, 0x23014cff, 0x461a2102, 0xf0024620, 0x2301fb22, 
+    0x22024620, 0xf0022104, 0x2301fb1c, 0x22004620, 0xf0024619, 0x210ffb16, 0xf0021ca0, 0x1d24faf8, 
+    0x4620210f, 0xfaf3f002, 0x48f12301, 0x029d220a, 0x4629300e, 0xfb05f002, 0xf9924aee, 0xf7ff0000, 
+    0x48ebff7a, 0x16fff240, 0x46312301, 0x30202200, 0xfaf7f002, 0x230148e6, 0x46312200, 0xf0023022, 
+    0x48e3faf0, 0x22002301, 0x30244631, 0xfae9f002, 0x230148df, 0x46312200, 0xf0023028, 0x2208fae2, 
+    0x23014620, 0x46310156, 0xfadbf002, 0x46312300, 0x46202208, 0xfad5f002, 0x46202301, 0x025e2209, 
+    0xf0024631, 0x2300face, 0x22094631, 0xf0024620, 0x2301fac8, 0x220a4629, 0xf0024620, 0x2300fac2, 
+    0x220a4629, 0xf0024620, 0x2301fabc, 0x220b4620, 0x462902dd, 0xfab5f002, 0x46204629, 0x4070e8bd, 
+    0x220b2300, 0xbaadf002, 0x4cc1b510, 0x21012300, 0x4620461a, 0xfaa5f002, 0x46202300, 0x21022201, 
+    0xfa9ff002, 0x46202300, 0x21042202, 0xfa99f002, 0x23004cb7, 0x34302201, 0x46202102, 0xfa91f002, 
+    0x46202300, 0x21042202, 0xfa8bf002, 0x46202300, 0x4010e8bd, 0x461a2101, 0xba83f002, 0x5ff0e92d, 
+    0xd0172803, 0x28054aac, 0xc2b0f8df, 0x0100f248, 0x92acf8df, 0x0a00f244, 0xf1ac4caa, 0x4daa0802, 
+    0x0b00f243, 0x4faa4ea9, 0xd0067812, 0xd1792804, 0xd07907d0, 0x5ff0e8bd, 0x07d0e7b6, 0x2301d1fa, 
+    0x220f4660, 0xfa5df002, 0x46512301, 0x4640220e, 0xfa57f002, 0x46592301, 0x4640220c, 0xfa51f002, 
+    0x0000f899, 0x0300f04f, 0xf04f461a, 0x28030101, 0xd02f4620, 0xfa45f002, 0x46282300, 0x461a2101, 
+    0xfa3ff002, 0x46302300, 0x461a2101, 0xfa39f002, 0x46382300, 0x461a2101, 0xfa33f002, 0x46202303, 
+    0x21062201, 0xfa2df002, 0x46282303, 0x21062201, 0xfa27f002, 0x46302303, 0x21062201, 0xfa21f002, 
+    0x46382303, 0x21062201, 0xfa1bf002, 0xfeeff7ff, 0xe0752300, 0xfa15f002, 0x46282300, 0x461a2101, 
+    0xfa0ff002, 0x46302300, 0x461a2101, 0xfa09f002, 0x46382300, 0x461a2101, 0xfa03f002, 0x46202300, 
+    0x21062201, 0xf9fdf002, 0x46282300, 0x21062201, 0xf9f7f002, 0x46302300, 0x21062201, 0xf9f1f002, 
+    0xe7ce2300, 0xe7ffe07c, 0x46602301, 0xf002220f, 0x2301f9e8, 0x220e4651, 0xf0024640, 0x2301f9e2, 
+    0x220c4659, 0xf0024640, 0xf899f9dc, 0xf04f0000, 0x461a0300, 0x0101f04f, 0x46202803, 0xf002d038, 
+    0x2300f9d0, 0x21014628, 0xf002461a, 0x2300f9ca, 0x21014630, 0xf002461a, 0x2300f9c4, 0x21014638, 
+    0xf002461a, 0x2303f9be, 0x22014620, 0xf0022106, 0x2303f9b8, 0x22014628, 0xf0022106, 0x2303f9b2, 
+    0x22014630, 0xf0022106, 0x2303f9ac, 0x22014638, 0xf0022106, 0xf7fff9a6, 0xf7fffe7a, 0x2301fd1f, 
+    0xe8bd483b, 0x22005ff0, 0x30302101, 0xb999f002, 0xf997f002, 0x46282300, 0x461a2101, 0xf991f002, 
+    0x46302300, 0x461a2101, 0xf98bf002, 0x46382300, 0x461a2101, 0xf985f002, 0x46202300, 0x21062201, 
+    0xf97ff002, 0x46282300, 0x21062201, 0xf979f002, 0x46302300, 0x21062201, 0xf973f002, 0xe7c52300, 
+    0x9ff0e8bd, 0xb5702300, 0x46042a04, 0xd007461d, 0x2901b1a9, 0x2902d010, 0x2903d010, 0xe00ed01e, 
+    0x2901b169, 0x2902d00a, 0x2903d002, 0xe006d002, 0xe0042302, 0xe0022303, 0xe00025ff, 0x48142301, 
+    0x1d802200, 0xeb00213f, 0xf0020044, 0x4810f94a, 0x2c033020, 0x0044eb00, 0xe002d002, 0xe7eb2301, 
+    0x462b1c80, 0xf2402200, 0xf00211ff, 0xf640f93a, 0x23010500, 0x340b40a5, 0x4c05b262, 0x4616b2a9, 
+    0x46201ca4, 0xf92df002, 0x4632b2a9, 0xe0112300, 0xf2030a00, 0x00040298, 0x000402b4, 0xf2030802, 
+    0x00040292, 0xf203c604, 0xf203ce04, 0xf203d604, 0xf203de04, 0xe8bd4620, 0xf0024070, 0x0000b912, 
+    0x5ff0e92d, 0x00044fbd, 0x0500f04f, 0x2301d005, 0x22044638, 0xf0022110, 0x48b8f904, 0x22002305, 
+    0x1f802107, 0xf8fdf002, 0x22024eb4, 0x4623211c, 0x46301eb6, 0xf8f5f002, 0x46302301, 0x21202205, 
+    0xf8eff002, 0x4800f240, 0x46402100, 0xffc4f7dd, 0x22072301, 0x1cb02180, 0xf8e3f002, 0x46402100, 
+    0xffbaf7dd, 0xf2402200, 0x1db031ff, 0xf8e7f002, 0xf8dfb194, 0x2c03828c, 0x9288f8df, 0x0709f06f, 
+    0xa284f8df, 0xb284f8df, 0x2c04d016, 0x2c05d014, 0x2c06d01e, 0xe033d049, 0xf8fef004, 0x4b9d4a9c, 
+    0xf94af004, 0x4b9d4a9c, 0xfa7af004, 0xfe3af003, 0xfd8ef004, 0xe0354605, 0xf8eef004, 0xf004463a, 
+    0x4642ff62, 0xf004464b, 0x4652f937, 0xe00a465b, 0xf8e2f004, 0xf004463a, 0x4642ff56, 0xf004464b, 
+    0x4b8ff92b, 0xf0034652, 0xf003ff0b, 0x498dfe1b, 0xfcacf004, 0xf004498c, 0xf004fdd3, 0x4605fd69, 
+    0x23004630, 0x211c2202, 0xf88bf002, 0x46302301, 0x21202205, 0xf885f002, 0x23004878, 0x21102204, 
+    0xf87ff002, 0xe8bd4628, 0xf0049ff0, 0x463af8b5, 0xff29f004, 0x464b4642, 0xf8fef004, 0x46524b7b, 
+    0xe92de7d1, 0x4e7a5ff0, 0x22032301, 0x21084605, 0xf0024630, 0x2302f866, 0x22004630, 0xf0022103, 
+    0xf1a6f860, 0xf2480a02, 0x23000900, 0x220f4649, 0xf0024650, 0xf240f856, 0x21004b00, 0xf7dd4658, 
+    0x2400ff2b, 0x23004630, 0x21042202, 0xf849f002, 0x46302301, 0x21042202, 0xf843f002, 0xb2641c64, 
+    0xdbef2c18, 0x22004862, 0x31fff240, 0xf002300c, 0x4607f846, 0x108bf2a0, 0xd3012822, 0x17a0f240, 
+    0xd0022d01, 0xd0022d05, 0x2300e00d, 0x2301e000, 0x22004630, 0xf0022103, 0x2300f824, 0x220f4649, 
+    0xf0024650, 0x2100f81e, 0xf7dd4658, 0x2400fef5, 0x23004630, 0x21042202, 0xf813f002, 0x46302301, 
+    0x21042202, 0xf80df002, 0xb2641c64, 0xdbef2c18, 0x22004847, 0x31fff240, 0xf002300c, 0x2d01f810, 
+    0xd0024604, 0xd0082d05, 0x4638e018, 0xf834f004, 0x460f4605, 0x70a0f640, 0x4638e006, 0xf82cf004, 
+    0x460f4605, 0x6080f643, 0xf0044360, 0x462af825, 0xf003463b, 0xf003fe55, 0x4680fd65, 0xf0044640, 
+    0x2300fcb7, 0x22034604, 0x21084630, 0xffd9f001, 0xe758b220, 0xb5102000, 0xfec2f7ff, 0x481fb281, 
+    0xf00138ce, 0x2001ffb4, 0xff5bf7ff, 0x481bb281, 0xf00138cc, 0x2004ffac, 0xfeb2f7ff, 0x4817b281, 
+    0xf00138ca, 0x2005ffa4, 0xfeaaf7ff, 0x4813b281, 0xf00138c8, 0x2006ff9c, 0xfea2f7ff, 0x480fb281, 
+    0x4010e8bd, 0xf00138c6, 0x2301bf92, 0x22004819, 0xb5104619, 0xffa5f001, 0x23014c08, 0x46192200, 
+    0x46201ea4, 0xff9df001, 0x46202301, 0x461a2102, 0xff97f001, 0x4010e8bd, 0x0000e7bc, 0xf23d0210, 
+    0xcac08312, 0x408d80a1, 0x9999999a, 0x3fe99999, 0x8bc169c2, 0x3fe182be, 0x5aee6320, 0x407c2142, 
+    0x3fd99999, 0x447a0000, 0x461c4000, 0x3fc99999, 0xf203f052, 0xf23d0004, 0x41f0e92d, 0x48a84607, 
+    0x4616461c, 0x46884420, 0xf2412300, 0x220c0100, 0xf0014605, 0x2e02ff66, 0x2300d01a, 0x22004628, 
+    0xf0012103, 0x489eff5e, 0x0100f242, 0x44201d80, 0xff3df001, 0x4639489a, 0x44201d00, 0xff37f001, 
+    0x46414897, 0x44203008, 0x41f0e8bd, 0xbf2ff001, 0xe7e32301, 0x43f8e92d, 0x2100460c, 0x49909100, 
+    0x1c8a1f09, 0x1d0a18a7, 0x186518a6, 0xd07c2800, 0x46282300, 0x21022201, 0xff33f001, 0x46282300, 
+    0x461a2101, 0xff2df001, 0x46282100, 0xff0ff001, 0x46382100, 0xff0bf001, 0x46302100, 0xff07f001, 
+    0x2100487f, 0x44201d00, 0xff01f001, 0x2100487c, 0x44201d80, 0xfefbf001, 0x21004879, 0x44203008, 
+    0xfef5f001, 0x21004876, 0x4420300a, 0xfeeff001, 0x21004873, 0x4420300c, 0xfee9f001, 0x21004870, 
+    0x4420300e, 0xfee3f001, 0x2100486d, 0x44203010, 0xfeddf001, 0x2100486a, 0x44203012, 0xfed7f001, 
+    0x21004867, 0x44203014, 0xfed1f001, 0x21004864, 0x44203016, 0xfecbf001, 0x21004861, 0x44203018, 
+    0xfec5f001, 0x2100485e, 0x4420301e, 0xfebff001, 0x2100485b, 0x44203020, 0xfeb9f001, 0x21004858, 
+    0x44203022, 0xfeb3f001, 0x21004855, 0x44203024, 0xfeadf001, 0x21004852, 0x44203026, 0xfea7f001, 
+    0x2107484f, 0x44203028, 0xe05ae000, 0xfe9ff001, 0x2100484b, 0x4420302a, 0xfe99f001, 0x21004848, 
+    0x4420302c, 0xfe93f001, 0x21004845, 0x4420302e, 0xfe8df001, 0x21004842, 0x44203030, 0xfe87f001, 
+    0x2100483f, 0x44203032, 0xfe81f001, 0x2100483c, 0x4420303c, 0xfe7bf001, 0x21004839, 0x4420303e, 
+    0xfe75f001, 0x21004836, 0x44203044, 0xfe6ff001, 0x30464833, 0x1f00f5b4, 0x4420d01f, 0x2101f248, 
+    0xfe65f001, 0x2100482e, 0x44203048, 0xfe5ff001, 0xf240482b, 0x304c1101, 0xf0014420, 0x4828fe58, 
+    0x304e2100, 0xf0014420, 0x4825fe52, 0x30502100, 0xf0014420, 0xe8bdfe4c, 0x482283f8, 0x3101f248, 
+    0x2301e7de, 0x22004628, 0xf0014619, 0x2301fe5a, 0x22004638, 0xf0014619, 0xf240fe54, 0x46303900, 
+    0x46492302, 0xf0012208, 0xf44ffe4c, 0x90000080, 0xf8df4813, 0x1c808054, 0xe0064404, 0x4642210b, 
+    0xf7dd4668, 0x2801fdae, 0x2200d006, 0x21014620, 0xfe45f001, 0xd1f12801, 0x46492300, 0x46302208, 
+    0xfe2ff001, 0x46282301, 0x461a2102, 0xfe29f001, 0x46382301, 0x461a2102, 0xfe23f001, 0x0000e7bb, 
+    0xf303a404, 0xf323a44a, 0xf203517e, 0x4605b5f0, 0xb1532000, 0x2d0b2400, 0xf240d301, 0x293d1001, 
+    0xf440d301, 0xb1147081, 0x2401e003, 0x2a12e7f3, 0x2a00dc01, 0xf440da01, 0xb10c7082, 0xdc012a18, 
+    0xda012a00, 0x7082f440, 0xd3012b07, 0x7084f440, 0x18f718ae, 0x428f1dbf, 0xf440dd01, 0x44297090, 
+    0x44194411, 0xdd01293c, 0x70a0f440, 0x2e18b124, 0xf440dd01, 0xbdf070c0, 0xdcfa2e12, 0xb40fbdf0, 
+    0xa802b510, 0xfc8ff000, 0xf000a80a, 0xf8bdfc5a, 0xf64f1042, 0xf00170ff, 0xea000101, 0xf8bd0241, 
+    0xf0011040, 0x43110101, 0x0241ea00, 0x103ef8bd, 0x0101f001, 0xea004311, 0xf8bd0141, 0xf000003c, 
+    0x43080001, 0x0046f8ad, 0xf000a812, 0xf8bdfcbe, 0x48fe1026, 0xfd9bf001, 0xf8bd48fc, 0x1e80103a, 
+    0xfd95f001, 0xf8bd48f9, 0x1d001046, 0xfd8ff001, 0xf8bd48f6, 0x1c801068, 0xfd89f001, 0x2000bc10, 
+    0xfb14f85d, 0x4ff0e92d, 0x0903ea5f, 0xb0ab4690, 0x4607468b, 0x2000d01b, 0x46822120, 0xf000a815, 
+    0x2114ffa5, 0xf000a826, 0x2400ffa1, 0x21244625, 0xa81d462e, 0xff9af000, 0x0f00f1ba, 0xf1b8d00d, 
+    0xdd060f12, 0x0006f1a8, 0xb2c02206, 0x2001e009, 0x2200e7e2, 0x00fff008, 0xf008e003, 0xf00900ff, 
+    0xebab02ff, 0x1a090107, 0xf0011a89, 0xf04f0cff, 0x07d30101, 0x2a06d101, 0xf8add301, 0x2a021098, 
+    0xf8add301, 0x2a0410a0, 0x2a06d305, 0x10a4f8ad, 0xf8add301, 0x4ace109c, 0x2a01403a, 0x2f0ad001, 
+    0xf8addb01, 0x2f021074, 0xf8addb01, 0x2f04108c, 0xf8addb01, 0x2f061086, 0xf8addb01, 0x2f081080, 
+    0x2f0adb05, 0x107af8ad, 0xf8addb01, 0x07c2106a, 0x2808d101, 0xf8add301, 0x28021054, 0xf8add301, 
+    0x2804105c, 0xf8add301, 0x28061060, 0x2808d305, 0x1064f8ad, 0xf8add301, 0xf8bd1058, 0xb9fb306a, 
+    0xd00107c2, 0xd2192808, 0xd2172812, 0x207af8bd, 0xd1012a01, 0xd211280a, 0x2080f8bd, 0xd1012a01, 
+    0xd20b280c, 0x2086f8bd, 0xd1012a01, 0xd205280e, 0x208cf8bd, 0xd1032a01, 0xd3012810, 0x106cf8ad, 
+    0x207af8bd, 0x0a02ea5f, 0x280ad103, 0xf8add301, 0xf8bd107c, 0xea5f2080, 0xd1030902, 0xd301280c, 
+    0x1082f8ad, 0x2086f8bd, 0x0802ea5f, 0x280ed103, 0xf8add301, 0xf8bd1088, 0xb91f708c, 0xd3012810, 
+    0x108ef8ad, 0x2074f8bd, 0x2812b9b2, 0xf1bad212, 0xd1010f01, 0xd20d280a, 0x0f01f1b9, 0x280cd101, 
+    0xf1b8d208, 0xd1010f01, 0xd203280e, 0xd1032f01, 0xd3012810, 0x1076f8ad, 0x0f00f1bc, 0xf1acd07d, 
+    0xf00c0c01, 0xea5f00ff, 0xd0017cc0, 0x040ff361, 0xd0f30840, 0x7cc0ea5f, 0x1e40d005, 0x441ff361, 
+    0x00fff010, 0xb92dd0ea, 0xf0101e80, 0xf36100ff, 0xd0e3050f, 0x4c15ea5f, 0x1e80d105, 0x451ff361, 
+    0x00fff010, 0xea5fd0da, 0xd17c4c14, 0xc09ef8bd, 0x0f00f1bc, 0xf8bdd10f, 0xf1bcc09c, 0xd10a0f00, 
+    0xf8ad1e80, 0xf361109e, 0xf010441f, 0xd0c500ff, 0x0c01ea5f, 0xf8bdd16b, 0xf1bcc09a, 0xd10f0f00, 
+    0xc098f8bd, 0x0f00f1bc, 0x1e80d10a, 0x109af8ad, 0x441ff361, 0x00fff010, 0xea5fd0b0, 0xd1560c01, 
+    0xc05af8bd, 0x0f00f1bc, 0xf8bdd10f, 0xf1bcc058, 0xd10a0f00, 0xf8ad1e80, 0xf361105a, 0xf010441f, 
+    0xd09b00ff, 0x0c01ea5f, 0xf8bdd141, 0xf1bcc056, 0xd10f0f00, 0xc054f8bd, 0x0f00f1bc, 0x1e80d10a, 
+    0x1056f8ad, 0x441ff361, 0x00fff010, 0xea5fd086, 0xd12c0c01, 0xc078f8bd, 0xe0d6e000, 0x0f00f1bc, 
+    0xb97ad110, 0xc076f8bd, 0x0f00f1bc, 0x1e80d10a, 0x1078f8ad, 0x441ff361, 0x00fff010, 0xea5fd089, 
+    0xd1140c01, 0xc06ef8bd, 0x0f00f1bc, 0xb953d10f, 0xc06cf8bd, 0x0f00f1bc, 0xf361d109, 0xf8ad441f, 
+    0x1e80106e, 0xe002e000, 0x00fff010, 0xf8bdd08f, 0xf1bcc0a6, 0xd10a0f00, 0xc0a4f8bd, 0x0f00f1bc, 
+    0x1e80d105, 0x10a6f8ad, 0x00fff010, 0xf8bdd094, 0xf1bcc0a2, 0xd10a0f00, 0xc0a0f8bd, 0x0f00f1bc, 
+    0x1e80d105, 0x10a2f8ad, 0x00fff010, 0xf8bdd084, 0xf1bcc066, 0xd10a0f00, 0xc064f8bd, 0x0f00f1bc, 
+    0x1e80d105, 0x1066f8ad, 0x00fff010, 0xf8bdd07d, 0xf1bcc062, 0xd10a0f00, 0xc060f8bd, 0x0f00f1bc, 
+    0x1e80d105, 0x1062f8ad, 0x00fff010, 0xf8bdd06d, 0xf1bcc05e, 0xd10a0f00, 0xc05cf8bd, 0x0f00f1bc, 
+    0x1e80d105, 0x105ef8ad, 0x00fff010, 0xf8bdd05d, 0xf1bcc090, 0xd10e0f00, 0xf8bdb96f, 0xb957708e, 
+    0xf8ad1e80, 0xf0101090, 0xe00300ff, 0xf303a238, 0x80000001, 0xf8bdd049, 0xb95f708a, 0x0f00f1b8, 
+    0xf8bdd108, 0xb92f7088, 0xf8ad1e80, 0xf010108a, 0xd03a00ff, 0x7084f8bd, 0xf1b9b95f, 0xd1080f00, 
+    0x7082f8bd, 0x1e80b92f, 0x1084f8ad, 0x00fff010, 0xf8bdd02b, 0xb95f707e, 0x0f00f1ba, 0xf8bdd108, 
+    0xb92f707c, 0xf8ad1e80, 0xf010107e, 0xd01c00ff, 0x709ef8bd, 0xf8bdbbf7, 0xbbdf709c, 0xc09af8bd, 
+    0x0f00f1bc, 0xf8bdd110, 0xf1bcc098, 0xd10b0f00, 0xf8ad1e80, 0xf010109e, 0xf8ad00ff, 0xd004109a, 
+    0x0c01ea5f, 0xbb2fd128, 0xe08fe000, 0xc05af8bd, 0x0f00f1bc, 0xf8bdd110, 0xf1bcc058, 0xd10b0f00, 
+    0xf8ad1e80, 0xf010109e, 0xf8ad00ff, 0xd07d105a, 0x0c01ea5f, 0xb96fd110, 0x7056f8bd, 0xf8bdb957, 
+    0xb93f7054, 0xf8ad1e80, 0xf010109e, 0xf8ad00ff, 0xe0001056, 0xd069e000, 0x709af8bd, 0xf8bdbb37, 
+    0xbb1f7098, 0xc05af8bd, 0x0f00f1bc, 0xf8bdd110, 0xf1bcc058, 0xd10b0f00, 0xf8ad1e80, 0xf010109a, 
+    0xf8ad00ff, 0xd051105a, 0x0c01ea5f, 0xb96fd10e, 0x7056f8bd, 0xf8bdb957, 0xb93f7054, 0xf8ad1e80, 
+    0xf010109a, 0xf8ad00ff, 0xd03f1056, 0x705af8bd, 0xf8bdb987, 0xb96f7058, 0x7056f8bd, 0xf8bdb957, 
+    0xb93f7054, 0xf8ad1e80, 0xf010105a, 0xf8ad00ff, 0xd02b1056, 0x709ef8bd, 0xf8bdbb4f, 0xbb37709c, 
+    0xc078f8bd, 0x0f00f1bc, 0xb982d111, 0xc076f8bd, 0x0f00f1bc, 0x1e80d10b, 0x109ef8ad, 0x00fff010, 
+    0x1078f8ad, 0xea5fd012, 0xd1120c01, 0xf8bdb97f, 0xb967706e, 0xf8bdb95b, 0xb947706c, 0xf8ad1e80, 
+    0xf010109e, 0xf8ad00ff, 0xe001106e, 0xe000e080, 0xf8bdd07e, 0xbb47709a, 0x7098f8bd, 0xf8bdbb2f, 
+    0xf1bcc078, 0xd1110f00, 0xf8bdb982, 0xf1bcc076, 0xd10b0f00, 0xf8ad1e80, 0xf010109a, 0xf8ad00ff, 
+    0xd07e1078, 0x0c01ea5f, 0xb977d10f, 0x706ef8bd, 0xb953b95f, 0x706cf8bd, 0x1e80b93f, 0x109af8ad, 
+    0x00fff010, 0x106ef8ad, 0xf8bdd06b, 0xbb47705a, 0x7058f8bd, 0xf8bdbb2f, 0xf1bcc078, 0xd1110f00, 
+    0xf8bdb982, 0xf1bcc076, 0xd10b0f00, 0xf8ad1e80, 0xf010105a, 0xf8ad00ff, 0xd0521078, 0x0c01ea5f, 
+    0xb977d10f, 0x706ef8bd, 0xb953b95f, 0x706cf8bd, 0x1e80b93f, 0x105af8ad, 0x00fff010, 0x106ef8ad, 
+    0xf8bdd03f, 0xbb577056, 0x7054f8bd, 0xf8bdbb3f, 0xf1bcc078, 0xd1110f00, 0xf8bdb982, 0xf1bcc076, 
+    0xd10b0f00, 0xf8ad1e80, 0xf0101056, 0xf8ad00ff, 0xd0261078, 0x0c01ea5f, 0xb987d111, 0x706ef8bd, 
+    0xb963b96f, 0x706cf8bd, 0xf8adb94f, 0xe0001056, 0x1e80e017, 0x106ef8ad, 0x0ffff010, 0xf8bdd011, 
+    0xb9700078, 0xf8bdb96a, 0xb9500076, 0x006ef8bd, 0xb933b938, 0x006cf8bd, 0xf8adb918, 0xf8ad1078, 
+    0x2222106e, 0xa80ca91d, 0xec16f000, 0x2214ab09, 0xe883a926, 0xa8040070, 0xec0ef000, 0xe897af19, 
+    0xaf15000f, 0x000fe88d, 0x000fe897, 0xfc47f7ff, 0xe8bdb02b, 0xe92d8ff0, 0x460347f0, 0x0081eb01, 
+    0x2a012500, 0x4418561f, 0x1001f990, 0x6002f990, 0x4003f990, 0xd0704688, 0x46324623, 0xf7ff4638, 
+    0x0005fbf5, 0xb15cd169, 0x4db62300, 0xf242220d, 0x46280100, 0xfa05f001, 0xdd032f00, 0xe0022301, 
+    0xe7f22301, 0xf2412300, 0x220c0100, 0xf0014628, 0x2e00f9f8, 0x2301dd01, 0x2300e000, 0x0100f640, 
+    0x4628220b, 0xf9edf001, 0xdd012c00, 0xe0002301, 0xf2402300, 0x220a4100, 0xf0014628, 0x4da1f9e2, 
+    0x210f2200, 0x46283d82, 0xf001b2fb, 0x2200f9da, 0x1ca8213f, 0x03fff008, 0xf9d3f001, 0xf6412208, 
+    0x46287100, 0xf001b2f3, 0x4896f9cc, 0x210f2200, 0xb2e330d6, 0xf9c5f001, 0x46324623, 0x46384641, 
+    0xfc20f7ff, 0x488f4605, 0x210f2200, 0xf0013834, 0xf8dff9c6, 0xb240c230, 0xf1ac2801, 0xf10c0c0a, 
+    0xd0020902, 0xd0092804, 0x2301e014, 0x22074660, 0xf0012180, 0x2300f9a6, 0xe01be007, 0x46602300, 
+    0x21802207, 0xf99df001, 0x46482301, 0x21012200, 0xf997f001, 0x0008eb07, 0x44204430, 0x1f244c79, 
+    0xdd01282d, 0xe0002305, 0x46202304, 0x213c2202, 0xf987f001, 0x46294874, 0xf969f001, 0xe8bd4628, 
+    0x7b8287f0, 0x71fff64f, 0x0201f002, 0x0342ea01, 0xf0027b02, 0x431a0201, 0x0342ea01, 0xf0027a82, 
+    0x431a0201, 0x0342ea01, 0xf0027a02, 0x431a0201, 0x0342ea01, 0xf0027982, 0x431a0201, 0x0342ea01, 
+    0xf0027902, 0x431a0201, 0x0342ea01, 0xf0027882, 0x431a0201, 0x0242ea01, 0xf0017801, 0x43110101, 
+    0x20008241, 0x7e824770, 0x71fff64f, 0x0201f002, 0x0342ea01, 0xf0027e02, 0x431a0201, 0x0342ea01, 
+    0xf0027d82, 0x431a0201, 0xea017c83, 0xf0030282, 0xea010301, 0x43130242, 0xea017c02, 0xf0020343, 
+    0x431a0201, 0x0342ea01, 0xf0027b82, 0x431a0201, 0x0342ea01, 0xf0027b02, 0x431a0201, 0x0342ea01, 
+    0xf0027a82, 0x431a0201, 0x0342ea01, 0xf0027a02, 0x431a0201, 0xea017983, 0xf0030242, 0x43130301, 
+    0xea017902, 0xf0020343, 0x431a0201, 0x0342ea01, 0xf0027882, 0x431a0201, 0x0242ea01, 0xf0017801, 
+    0x43110101, 0x200083c1, 0x7f024770, 0x71fff64f, 0x0201f002, 0x0342ea01, 0xf0027e82, 0x431a0201, 
+    0x0342ea01, 0xf0027e02, 0x431a0201, 0x0342ea01, 0xf0027d82, 0x431a0201, 0x0342ea01, 0xf0027d02, 
+    0x431a0201, 0x0342ea01, 0xf0027c82, 0x431a0201, 0x0342ea01, 0xf0027c02, 0x431a0201, 0x0342ea01, 
+    0xf0027b82, 0x431a0201, 0x0342ea01, 0xf0027b02, 0x431a0201, 0x0342ea01, 0xf0027a82, 0x431a0201, 
+    0x0342ea01, 0xf0027a02, 0x431a0201, 0x0342ea01, 0xf0027982, 0x431a0201, 0x0342ea01, 0xf0027902, 
+    0x431a0201, 0x0342ea01, 0xf0027882, 0x431a0201, 0x0242ea01, 0xf0017801, 0x43110101, 0x20008401, 
+    0x00004770, 0xf303a14a, 0xf203519e, 0x4fffe92d, 0x4605b083, 0xf7dc2000, 0x4601ff27, 0xf00148b4, 
+    0x48b4f870, 0x22142300, 0x1180f44f, 0xf872f001, 0x23014cb0, 0x3c7c2204, 0x46202110, 0xf86af001, 
+    0x46202301, 0x21082203, 0xf864f001, 0x462b2200, 0xf6431d20, 0xf00171ff, 0xf04ff85d, 0xf04f0a00, 
+    0xf04f0901, 0x26000800, 0xfb88fa4f, 0x0f00f1b8, 0xf04fd00d, 0xb18e0701, 0xab019c10, 0x46584651, 
+    0xf8cdb272, 0xf7db9000, 0x2500fd91, 0xb116e032, 0x27029c06, 0x9c05e7f1, 0xe7ee2708, 0xe7ec9c04, 
+    0xf8514995, 0xeb010025, 0x68490185, 0x1e63b134, 0xf203fa09, 0x44114410, 0x41214120, 0x0200f248, 
+    0xdb014290, 0xe0031e50, 0x42984b8c, 0x4618da00, 0xdb024291, 0x71fff647, 0x4a88e003, 0xda004291, 
+    0xb2804611, 0x4101ea40, 0x38404882, 0xf809f001, 0xb2ad1cad, 0x1fc7ebb5, 0x1c76d3d2, 0x2e04b2f6, 
+    0xf108d3b4, 0xf0000001, 0xf1b808ff, 0xd3aa0f02, 0x0001f10a, 0xfa80fa4f, 0x0f04f1ba, 0x9811dba1, 
+    0xd07d2800, 0x81ccf8df, 0x31aaf04f, 0x0840f1a8, 0xf0004640, 0x4872ffe6, 0x211f2200, 0xf80ff001, 
+    0x041ff000, 0x2200486e, 0x1c80211f, 0xf807f001, 0x31e0f240, 0x1040ea01, 0x48694304, 0x211f2200, 
+    0xf0001d00, 0xf647fffc, 0xea014100, 0x43042080, 0x22004863, 0x1d80211f, 0xfff1f000, 0x2178f44f, 
+    0x30c0ea01, 0x0100ea44, 0xf0004640, 0x485dffba, 0x210f2200, 0xffe3f000, 0x485ab2c7, 0x21032200, 
+    0xf000382e, 0xb2c6ffdc, 0x22004856, 0x382c2103, 0xffd5f000, 0x4853b2c5, 0x21032200, 0xf000382a, 
+    0xb2c4ffce, 0x2200484f, 0x38282103, 0xffc7f000, 0x1106ea47, 0x1185ea41, 0xea41b2c0, 0xea412104, 
+    0x46402180, 0xff8df000, 0xf6434f47, 0x220b0500, 0x46384629, 0xffb3f000, 0x0600f24c, 0x220e4604, 
+    0x46384631, 0xffabf000, 0x04c0ea44, 0x21012200, 0xf0001cb8, 0x220bffa4, 0xea444629, 0xe0001440, 
+    0x4f3ae05b, 0xf0004638, 0xea44ff9a, 0x46311480, 0x4638220e, 0xff93f000, 0x2440ea44, 0x21012200, 
+    0xf0001cb8, 0x4f32ff8c, 0x24c0ea44, 0x4629220b, 0xf0004638, 0xea44ff84, 0x46313400, 0x4638220e, 
+    0xff7df000, 0x34c0ea44, 0x21012200, 0xf0001cb8, 0x4629ff76, 0xea444d27, 0x220b4440, 0xf0004628, 
+    0xea44ff6e, 0x46314480, 0x4628220e, 0xff67f000, 0x5440ea44, 0x21012200, 0xf0001ca8, 0xea44ff60, 
+    0x464051c0, 0xff2df000, 0x0104e9dd, 0x2101ea40, 0xea419806, 0x98104100, 0x6100ea41, 0xf0004640, 
+    0x2100ff20, 0xf0004640, 0x2100ff1c, 0xf0004640, 0x2100ff18, 0xf0004640, 0x2000ff14, 0xfdc4f7dc, 
+    0x48034601, 0xf0001d00, 0xb007ff0c, 0x8ff0e8bd, 0xf0003084, 0xf1000480, 0x00049a00, 0xffff8000, 
+    0xf203043c, 0xf203422e, 0xf203c610, 0xf203ce10, 0xf203d610, 0xf203de10, 0x4606b570, 0xf984f000, 
+    0xf1066805, 0xf020000b, 0x42b40407, 0x2000bf98, 0x462bd915, 0xb1ba686a, 0x42a06810, 0xf104d310, 
+    0x42880108, 0x6850bf3c, 0xd3076058, 0x19106851, 0x68116041, 0x60011b09, 0x60146058, 0xbd701d10, 
+    0x68524613, 0xd1e72a00, 0x46284621, 0xf964f000, 0xd1de2800, 0xb570bd70, 0x1f054604, 0xf954f000, 
+    0x2c006800, 0x6844bf18, 0x2c00d01b, 0x42acbf18, 0x4620bf3c, 0xd3f86864, 0x180a6801, 0xbf1842aa, 
+    0xd1036045, 0x4605682a, 0x60014411, 0x19416828, 0xbf1842a1, 0xd104606c, 0x60696861, 0x44086821, 
+    0xbd706028, 0x0320f1b2, 0xf1c2d50a, 0xfa010320, 0xfa20f102, 0xfa00f303, 0xea41f002, 0x47700103, 
+    0xf103fa00, 0x0000f04f, 0xf1b24770, 0xd50a0320, 0x0320f1c2, 0xf002fa20, 0xf303fa01, 0xf102fa21, 
+    0x0003ea40, 0xfa214770, 0xf04ff003, 0x47700100, 0xe92d4010, 0xe1b040c1, 0xe02440a3, 0x5a000002, 
+    0xe2700000, 0xe2611000, 0x32411001, 0xe1130003, 0x5a000002, 0xe2722000, 0xe2633000, 0x32433001, 
+    0xeb0000a1, 0xe3140101, 0x0a000002, 0xe2700000, 0xe2611000, 0x32411001, 0xe3140102, 0x0a000002, 
+    0xe2722000, 0xe2633000, 0x32433001, 0xe8bd8010, 0xe3520003, 0x9a000017, 0xe210c003, 0x0a000008, 
+    0xe4d13001, 0xe35c0002, 0xe082200c, 0x94d1c001, 0xe4c03001, 0x34d13001, 0x94c0c001, 0xe2422004, 
+    0x34c03001, 0xe2113003, 0x0a000012, 0xe2522008, 0x3a000004, 0xe4913004, 0xe2522008, 0xe491c004, 
+    0xe8a01008, 0xeafffff9, 0xe2922004, 0x54913004, 0x54803004, 0xe1a00000, 0xe1b02f82, 0x24d13001, 
+    0x24d1c001, 0x44d12001, 0x24c03001, 0x24c0c001, 0x44c02001, 0xe12fff1e, 0xe92d4010, 0xe2522020, 
+    0x3a000005, 0xe8b15018, 0xe2522020, 0xe8a05018, 0xe8b15018, 0xe8a05018, 0x2afffff9, 0xe1b0ce02, 
+    0x28b15018, 0x28a05018, 0x48b10018, 0x48a00018, 0xe8bd4010, 0xe1b0cf02, 0x24913004, 0x24803004, 
+    0x012fff1e, 0xe1b02f82, 0x20d130b2, 0x44d12001, 0x20c030b2, 0x44c02001, 0xe12fff1e, 0x03fff002, 
+    0x2203ea43, 0x4202ea42, 0xba55f000, 0x0200f04f, 0x4613b500, 0x46964694, 0xbf223920, 0x500ce8a0, 
+    0x500ce8a0, 0x0120f1b1, 0xaff7f4bf, 0xbf280709, 0x500ce8a0, 0xc00cbf48, 0xeb04f85d, 0xbf280089, 
+    0x2b04f840, 0x4770bf08, 0xf820bf48, 0xf0112b02, 0xbf184f80, 0x2b01f800, 0x00004770, 0xe3100003, 
+    0xe92d4010, 0xe1a04000, 0x03110003, 0x1a00000a, 0xe59fe04c, 0xe2522004, 0xba000006, 0xe4913004, 
+    0xe043c00e, 0xe1ccc003, 0xe01cc38e, 0x04803004, 0x0afffff7, 0xe2411004, 0xe2822004, 0xe2522001, 
+    0xba000005, 0xe4d13001, 0xe3530000, 0xe4c03001, 0x1afffff9, 0xe1a01002, 0xfb0000fc, 0xe1a00004, 
+    0xe8bd8010, 0x01010101, 0x47704800, 0x0004ec1c, 0x47704770, 0x47704770, 0x4604b538, 0x2000460a, 
+    0xf0004669, 0x2800fa3c, 0x4602d005, 0x99004620, 0xfa0af000, 0xbd382001, 0xf0002001, 0xb5f8ba1d, 
+    0xfa22f000, 0x20004605, 0x2010460c, 0x4606bf00, 0x42a019a8, 0x4632d90d, 0x20004669, 0xfa1ff000, 
+    0xbf080007, 0xfa08f000, 0x42a09800, 0x4605bf18, 0xf7ff19c4, 0x6005ffc9, 0x1df04607, 0x0007f020, 
+    0x46281946, 0xf80af000, 0xd00642b4, 0x68384631, 0xe8bd1ba2, 0xf00040f8, 0xbdf8b9d7, 0x60012100, 
+    0x1001e9c0, 0x20104770, 0x00004770, 0xe92d4070, 0xe1a04003, 0xe1a05002, 0xe1a03001, 0xe1a02000, 
+    0xe3540000, 0x11a0c004, 0x01a0c005, 0xe16fef1c, 0xe28e0001, 0xe1a0c01c, 0x127ee03f, 0x027ee01f, 
+    0x4a000094, 0xe3530000, 0x116f1f13, 0x016f1f12, 0x1271103f, 0x0271101f, 0xe051600e, 0x4a000092, 
+    0x52760004, 0x5a000093, 0xe24e0020, 0xe3500004, 0xd1a01035, 0xd18cc001, 0xe28f1f9f, 0xe1a0ce2c, 
+    0xe35e001f, 0xe791c10c, 0x824ee020, 0xe26e6020, 0x8a000048, 0xe081059c, 0xe1a04e30, 0xe1a01611, 
+    0xe1a00610, 0xe1811004, 0xe2700000, 0xe2611000, 0x32411001, 0xe081019c, 0xe08cc001, 0xe081059c, 
+    0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 0xe2611000, 0x32411001, 0xe3530000, 
+    0xe081019c, 0xe08cc001, 0x0a000009, 0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 
+    0xe2700000, 0xe2611000, 0x32411001, 0xe081019c, 0xe08cc001, 0xe080129c, 0xe3a01000, 0xe0a1039c, 
+    0xe1a00e30, 0xe1a04611, 0xe1800004, 0xe1a01e31, 0xe0846590, 0xe0522006, 0xe0244591, 0xe0c33004, 
+    0xe3530001, 0x31520005, 0x38bd8070, 0xe086429c, 0xe3a04000, 0xe0a4639c, 0xe26ec020, 0xe1a06e36, 
+    0xe1a03c14, 0xe1866003, 0xe3a03000, 0xe1a04e34, 0xe08ce596, 0xe0900006, 0xe0a11004, 0xe042200e, 
+    0xe1520005, 0x38bd8070, 0xe2900001, 0xe2a11000, 0xe0422005, 0xe052c005, 0x21a0200c, 0xe2b00000, 
+    0xe2a11000, 0xe052c005, 0x21a0200c, 0xe2b00000, 0xe2a11000, 0xe8bd8070, 0xe080159c, 0xe3a01000, 
+    0xe0a1049c, 0xe1a01611, 0xe1a06e30, 0xe1811006, 0xe26e6020, 0xe2611000, 0xe1a00610, 0xe2700000, 
+    0x32411001, 0xe081019c, 0xe08cc001, 0xe080159c, 0xe3a01000, 0xe0a1049c, 0xe1a01611, 0xe1a06e30, 
+    0xe1811006, 0xe26e6020, 0xe2611000, 0xe1a00610, 0xe2700000, 0x32411001, 0xe081019c, 0xe08cc001, 
+    0xe24cc001, 0xe080129c, 0xe3a01000, 0xe0a1039c, 0xe1a00e31, 0xe0816590, 0xe0522006, 0xe0211490, 
+    0xe0c33001, 0xe1530004, 0x01520005, 0x33a01000, 0x38bd8070, 0xe081629c, 0xe3a06000, 0xe0a6139c, 
+    0xe3a01000, 0xe1a06e36, 0xe08ce596, 0xe0800006, 0xe052200e, 0xe02ec496, 0xe0c3300e, 0xe1530004, 
+    0x01520005, 0x38bd8070, 0xe2800001, 0xe0522005, 0xe0c33004, 0xe8bd8070, 0xe92d000c, 0xe3a01000, 
+    0xe3a00000, 0xe1a00000, 0xe8bd807c, 0xe3a01000, 0xe3a00000, 0xe8bd8070, 0xe266e020, 0xe3a00000, 
+    0xe3a01000, 0xe1a04614, 0xe1a0ce35, 0xe1a05615, 0xe184400c, 0xe052e005, 0xe0d3c004, 0xe0a00000, 
+    0x21a0300c, 0x21a0200e, 0xe2566001, 0x38bd8070, 0xe1b040a4, 0xe1a05065, 0xeafffff5, 0xf0f0f0f0, 
+    0xe38e38e3, 0xd79435e5, 0xcccccccc, 0xc30c30c3, 0xba2e8ba2, 0xb21642c8, 0xaaaaaaaa, 0xa3d70a3d, 
+    0x9d89d89d, 0x97b425ed, 0x92492492, 0x8d3dcb08, 0x88888888, 0x84210842, 0x80000000, 0xf000b510, 
+    0x6800f82f, 0xb510bd10, 0xf0004604, 0x6004f829, 0xf04fbd10, 0x29040200, 0x8012f0c0, 0x0c03f010, 
+    0xada6f43f, 0x0c04f1cc, 0x0f02f1bc, 0xf800bf18, 0xbfa82b01, 0x2b02f820, 0x010ceba1, 0xbd98f7ff, 
+    0x7cc1ea5f, 0xf800bf24, 0xf8002b01, 0xbf482b01, 0x2b01f800, 0x00004770, 0x47704800, 0x0004ec14, 
+    0x47704800, 0x0004ec14, 0x6843468c, 0xbf182b00, 0xbf38428b, 0xd3f84618, 0x44186803, 0xd0074288, 
+    0x0003f10c, 0x0007f020, 0x1a411d00, 0x46011a52, 0x600a1d08, 0xbc6ff7ff, 0xf000b510, 0xe8bdf85f, 
+    0xf0004010, 0x0000b855, 0x46694b12, 0x5280f500, 0x601a428a, 0x4611d801, 0x60194770, 0xb5304770, 
+    0x466b4d0c, 0x5380f5a3, 0x4422682c, 0xd80f429a, 0xf5021a9b, 0xeb035080, 0xeb0273d3, 0x42980363, 
+    0x4618d900, 0xf0201dc0, 0x600c0207, 0x602a1b10, 0x0000bd30, 0x00043304, 0x46754770, 0xffacf7ff, 
+    0x000546ae, 0x46534669, 0x0007f020, 0xb0184685, 0xf001b520, 0xe8bdeab8, 0xf04f4020, 0xf04f0600, 
+    0xf04f0700, 0xf04f0800, 0xf0210b00, 0x46ac0107, 0x09c0e8ac, 0x09c0e8ac, 0x09c0e8ac, 0x09c0e8ac, 
+    0x4770468d, 0xf3af4604, 0x46208000, 0xf859f7d5, 0xd0012800, 0xb82af000, 0x00004770, 0x2801b510, 
+    0x2100d005, 0xf000a003, 0x2001f827, 0xa109bd10, 0x0000e7f8, 0x52474953, 0x4d454d54, 0x754f203a, 
+    0x666f2074, 0x61656820, 0x656d2070, 0x79726f6d, 0x00000000, 0x6548203a, 0x6d207061, 0x726f6d65, 
+    0x6f632079, 0x70757272, 0x00646574, 0x20184901, 0xe7fedfab, 0x00020026, 0x4605b570, 0x200a460c, 
+    0x1c6de000, 0xf811f000, 0x7828b135, 0xd1f82800, 0x1c64e002, 0xf809f000, 0x7820b114, 0xd1f82800, 
+    0x4070e8bd, 0xf3af200a, 0xb5088000, 0xf88d4669, 0x20030000, 0xbd08dfab, 0xe92d0003, 0xe59f0050, 
+    0xe580e000, 0xe59f004c, 0xe5901000, 0xe3510000, 0x1a000001, 0xe59f1040, 0xe5801000, 0xe2811001, 
+    0xe5801000, 0xe59f0034, 0xee151f10, 0xe5801000, 0xe59f002c, 0xee161f10, 0xe5801000, 0xe59f0024, 
+    0xee151f11, 0xe5801000, 0xe8bd0003, 0xe25ef008, 0xe320f000, 0xf000300c, 0xf0003010, 0xdead0000, 
+    0xf0003020, 0xf0003024, 0xf0003028, 0xf04fb500, 0xee116060, 0xea011f30, 0xee010100, 0xee111f30, 
+    0xf3bf0f30, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f10, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 
+    0xf3bf0f30, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f11, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 
+    0xf3bf0f31, 0xf85d8f6f, 0x4770eb04, 0xee16b500, 0xf3bf0f10, 0xf85d8f6f, 0x4770eb04, 0xee16b500, 
+    0xf3bf0f50, 0xf85d8f6f, 0x4770eb04, 0x5ffce92d, 0x4601468a, 0x0000f04f, 0x2b01f811, 0x03bbf04f, 
+    0xd128429a, 0x2b01f811, 0x03a7f04f, 0xd122429a, 0x2b01f811, 0xd11e4282, 0x2b01f811, 0xd11a4282, 
+    0xf04f4650, 0xf04f0a00, 0x5c8c0200, 0x050aea84, 0x06fff005, 0x5016f830, 0x261aea4f, 0x0a06ea85, 
+    0x0201f102, 0xdbf02a0a, 0xf04f5a8c, 0x45540001, 0xf04fd001, 0xe8bd0000, 0x00009ffc, 0xe92d500f, 
+    0xe14fc000, 0xe92d1000, 0xe59f0028, 0xe5901000, 0xe201103f, 0xe1a01201, 0xe59f201c, 0xe0822001, 
+    0xe5920000, 0xe8bd1000, 0xe16ff00c, 0xe8bd500f, 0xe25ef004, 0xe320f000, 0xf0001014, 0xf0001104, 
+    0x5ff0e92d, 0x7f80f5b2, 0x2a80d003, 0x2a40d004, 0xf8dfd005, 0xe00490f8, 0x90f4f8df, 0xf8dfe001, 
+    0xea4f90f4, 0xea4f0a52, 0x880c0b92, 0x4b02f823, 0xf8238804, 0xf8314b02, 0xf823401b, 0xf8304b02, 
+    0xf823401b, 0xf04f4b02, 0xf8190701, 0xf8315007, 0xf8234015, 0xf8304b02, 0xf8234015, 0xebaa4b02, 
+    0xf8310505, 0xf1c44015, 0xf8230400, 0xf8304b02, 0xf8234015, 0xf1074b02, 0x455f0701, 0xafe5f6ff, 
+    0x9ff0e8bd, 0x5ff0e92d, 0x7f80f5b1, 0x2980d003, 0x2940d004, 0xf8dfd005, 0xe0049074, 0x9070f8df, 
+    0xf8dfe001, 0xea4f9070, 0xea4f0a51, 0xf04f0b91, 0xf9300700, 0x801c4b02, 0x4b02f930, 0xf1078014, 
+    0xf9300701, 0xf8234b02, 0xf930401b, 0xf8226b02, 0xf819601b, 0xf9305007, 0xf8234b02, 0xf9304015, 
+    0xf8226b02, 0xebaa6015, 0xf9300505, 0xf1c44b02, 0xf8230400, 0xf9304015, 0xf8226b02, 0xf1076015, 
+    0x455f0701, 0xafe5f6ff, 0x9ff0e8bd, 0x0002fd90, 0x0002fdd0, 0x0002fdf0, 0x5ff0e92d, 0x0a00f04f, 
+    0x4694468b, 0x1000f9b0, 0x2002f9b0, 0x0302eb01, 0x5004f9b0, 0x6006f9b0, 0x0706eb05, 0x0806eba5, 
+    0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb03, 0x9b04f84c, 
+    0x0908eb03, 0x9b04f84c, 0x0402eba1, 0x0706eb05, 0x0806eba5, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 
+    0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0301eba2, 
+    0x0706eb05, 0x0806eba5, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 
+    0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0302eb01, 0x0400f1c3, 0x0706eb05, 0x0806eba5, 
+    0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb04, 0x9b04f84c, 
+    0x0908eb04, 0x9b04f84c, 0x0008f100, 0x0a01f10a, 0xf6ff45da, 0xe8bdaf87, 0x00009ff0, 0xe92d500f, 
+    0xe14fc000, 0xe92d1000, 0xe59f0028, 0xe5901000, 0xe201103f, 0xe1a01201, 0xe59f201c, 0xe0822001, 
+    0xe5920000, 0xe8bd1000, 0xe16ff00c, 0xe8bd500f, 0xe25ef004, 0xe320f000, 0xf000100c, 0xf0001104, 
+    0x5ffce92d, 0x0300f04f, 0x4023f850, 0x4023f841, 0x0301f103, 0xf6ff4293, 0xe8bdaff7, 0xe92d9ffc, 
+    0xf04f5ffc, 0x2b000500, 0xf1c3da02, 0xe00b0300, 0x4025f850, 0xf403fa04, 0x4025f841, 0x0501f105, 
+    0xf6ff4295, 0xe00aaff5, 0x4025f850, 0xf403fa44, 0x4025f841, 0x0501f105, 0xf6ff4295, 0xe8bdaff5, 
+    0xe92d9ffc, 0xf04f5ffc, 0xf8300300, 0xf8214013, 0xf1034013, 0x42930301, 0xaff7f6ff, 0x9ffce8bd, 
+    0x5ffce92d, 0x0300f04f, 0x4013f930, 0x4023f841, 0x0301f103, 0xf6ff4293, 0xe8bdaff7, 0xe92d9ffc, 
+    0xf04f5ff0, 0xf9300500, 0xfa044b02, 0xf841f403, 0xf1054b04, 0x42950501, 0xaff5f6ff, 0x9ff0e8bd, 
+    0x5ffce92d, 0x0701f1a3, 0x0601f04f, 0xf607fa06, 0x0500f04f, 0x4025f850, 0xfa444434, 0xf821f403, 
+    0xf1054015, 0x42950501, 0xaff4f6ff, 0x9ffce8bd, 0xe92d5ffc, 0xeafffffe, 0xe8bd9ffc, 0x6800b500, 
+    0xb500bd00, 0xbd006001, 0x8800b500, 0xb500bd00, 0xbd008001, 0x41f0e92d, 0xea246804, 0xfa030401, 
+    0xea05f502, 0xea440501, 0x60040405, 0x81f0e8bd, 0x41f0e92d, 0xea006800, 0xfa200001, 0xe8bdf002, 
+    0xe92d81f0, 0x880441f0, 0x0401ea24, 0xf502fa03, 0x0501ea05, 0x0405ea44, 0xe8bd8004, 0xe92d81f0, 
+    0x880041f0, 0x0001ea00, 0xf002fa20, 0x81f0e8bd, 0xe59f1150, 0xe5910000, 0xe590e000, 0xe59f0148, 
+    0xe8be0002, 0xe5801000, 0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 
+    0xef000000, 0xe12fff1e, 0xe28ee004, 0xe92d0001, 0xe94d2000, 0xe320f000, 0xe24dd004, 0xe8bd0001, 
+    0xe9204000, 0xe1a0e000, 0xe8bd0001, 0xe94e7fff, 0xe320f000, 0xe24ee03c, 0xe14f0000, 0xe92e0001, 
+    0xe59f00e4, 0xe5900000, 0xe92e0001, 0xe59f10d4, 0xe5910000, 0xe580e000, 0xe59f00d0, 0xe1a0e00f, 
+    0xe12fff10, 0xe59f10bc, 0xe5910000, 0xe590e000, 0xe59f00b4, 0xe8be0002, 0xe5801000, 0xe8be0001, 
+    0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 0xe92d0001, 0xe94d2000, 0xe320f000, 
+    0xe24dd004, 0xe8bd0001, 0xe9204000, 0xe1a0e000, 0xe8bd0001, 0xe94e7fff, 0xe320f000, 0xe24ee03c, 
+    0xe14f0000, 0xe92e0001, 0xe59f005c, 0xe5900000, 0xe92e0001, 0xe59f104c, 0xe5910000, 0xe580e000, 
+    0xe59f004c, 0xe1a0e00f, 0xe12fff10, 0xe59f003c, 0xe1a0e00f, 0xe12fff10, 0xe59f1028, 0xe5910000, 
+    0xe590e000, 0xe59f0020, 0xe8be0002, 0xe5801000, 0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 
+    0xe59ee03c, 0xe25ef004, 0x00043290, 0x000432e0, 0x00026b7f, 0x00026a0f, 0x41f0e92d, 0x460c4603, 
+    0xea218819, 0x80190104, 0x0104ea41, 0x42806810, 0x8019dcfc, 0x81f0e8bd, 0x41f0e92d, 0xea45880d, 
+    0x800d0502, 0x0502ea25, 0x4284681c, 0x800ddcfc, 0x81f0e8bd, 0xe92d0003, 0xe59f0034, 0xe59f1034, 
+    0xe5801000, 0xe59f0030, 0xee151f31, 0xe5801000, 0xe59f0028, 0xee151f30, 0xe5801000, 0xe59f0020, 
+    0xee161f50, 0xe5801000, 0xe8bd0003, 0xe25ef004, 0xe320f000, 0xf0003010, 0xfec0dead, 0xf000302c, 
+    0xf0003030, 0xf0003034, 0x5ffce92d, 0xf1a59d0d, 0xf04f0c05, 0xfa0b0b01, 0xea4ffa05, 0xb40c0a9a, 
+    0x9a10b403, 0xf1009800, 0xf04f0104, 0xf84d0e00, 0xf04fcd04, 0xb4040900, 0xf8506803, 0x680c503a, 
+    0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 
+    0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 0xf8414413, 0xf840c03a, 0xeb02403a, 0xf84002cb, 
+    0xf8417b08, 0xf1098b08, 0x45d10901, 0xafd4f6ff, 0x00caeb00, 0x01caeb01, 0xf10ebc04, 0x45de0e01, 
+    0xafc7f6ff, 0x0b4bea4f, 0x0a5aea4f, 0xcb04f85d, 0x0c01f1ac, 0x0f00f1bc, 0x9800dcb4, 0x0104f100, 
+    0x0e00f04f, 0x2982f645, 0x6803b404, 0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba30806, 
+    0xeba40505, 0xf8400606, 0xf841503a, 0xf840603a, 0xf8417b08, 0xeb028b08, 0x680302cb, 0x503af850, 
+    0xf851680c, 0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 0x68130606, 0x0545ea4f, 0x0646ea4f, 
+    0xfc13fb35, 0xf403fb35, 0xcc03fb36, 0x0600f1c6, 0x4413fb36, 0xc03af841, 0x403af840, 0x120beb02, 
+    0x7b08f840, 0x8b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0806eba4, 0x4426441d, 
+    0x0307eb08, 0x0807eba8, 0x0343ea4f, 0x0848ea4f, 0xf309fb33, 0xf809fb38, 0x303af840, 0x803af841, 
+    0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 
+    0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 
+    0xf8414413, 0xf840c03a, 0xeb02403a, 0xf840120b, 0xf8417b08, 0x68038b08, 0x503af850, 0xf851680c, 
+    0xeb03603a, 0xeb040705, 0xeba50806, 0xeba40503, 0xf8410606, 0xf840503a, 0xf840603a, 0xf8417b08, 
+    0x68038b08, 0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 0x68130606, 
+    0x0545ea4f, 0x0646ea4f, 0xfc13fb35, 0xf403fb35, 0xcc03fb36, 0x0600f1c6, 0x4413fb36, 0xc03af841, 
+    0x403af840, 0x120beb02, 0x7b08f840, 0x8b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 
+    0x0806eba4, 0x4426441d, 0x0307eb08, 0x0807eba8, 0x0343ea4f, 0x0848ea4f, 0xf309fb33, 0xf809fb38, 
+    0x0300f1c3, 0x803af840, 0x303af841, 0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 
+    0x0705eb03, 0x0806eb04, 0x0505eba3, 0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 
+    0xfb36f403, 0xf1c6cc03, 0xfb360600, 0xf8414413, 0xf840c03a, 0xeb02403a, 0xf84002cb, 0xf8417b08, 
+    0xeb008b08, 0xeb0100ca, 0xbc0401ca, 0x0e01f10e, 0xf6ff45de, 0xea4faee9, 0xea4f0b4b, 0x98000a5a, 
+    0x0104f100, 0x0800f04f, 0x2982f645, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0206eb04, 
+    0x0505eba3, 0x0606eba4, 0x503af840, 0x603af841, 0x7b08f840, 0x2b08f841, 0xf8506803, 0x680c503a, 
+    0x603af851, 0x0705eba3, 0x0206eba4, 0x4426441d, 0x0307eb02, 0x0207eba2, 0x0343ea4f, 0x0242ea4f, 
+    0xf309fb33, 0xf209fb32, 0x303af840, 0x203af841, 0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 
+    0x603af851, 0x0705eb03, 0x0206eb04, 0x0503eba5, 0x0606eba4, 0x503af841, 0x603af840, 0x7b08f840, 
+    0x2b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0206eba4, 0x4426441d, 0x0307eb02, 
+    0x0207eba2, 0x0343ea4f, 0x0242ea4f, 0xf309fb33, 0xf209fb32, 0x0300f1c3, 0x203af840, 0x303af841, 
+    0x5b08f840, 0x6b08f841, 0x00caeb00, 0x01caeb01, 0x0801f108, 0xf6ff45d8, 0xea4faf89, 0x98000b4b, 
+    0x0104f100, 0x0800f04f, 0x2b08f850, 0x3b08f850, 0x4b08f850, 0xf8516805, 0xf8516b08, 0xf8517b08, 
+    0xf8d19b08, 0xeb02a000, 0xeba20c04, 0xeb060204, 0xeba60409, 0xeb030609, 0xeba30905, 0xeb070305, 
+    0xeba7050a, 0xeb0c070a, 0xebac0a09, 0xeb040c09, 0xeba40905, 0xeb020405, 0xeba20507, 0xeb060207, 
+    0xeba60703, 0xf8400603, 0xf8402908, 0xf8405908, 0xf840c908, 0xf841ab20, 0xf8417908, 0xf8416908, 
+    0xf8414908, 0xf1089b20, 0x45d80801, 0xafbcf6ff, 0x058bea4f, 0xf985fab5, 0x091ef1c9, 0x0c1ff1c9, 
+    0x0b59ea4f, 0x0b01f10b, 0x0901f009, 0xbc0344cb, 0xf850bc0c, 0xf8509b04, 0xf850ab04, 0xf8504b04, 
+    0xeb09790c, 0xeba9060a, 0xf04f090a, 0xfa460800, 0xfa49f60b, 0xfa44f90b, 0xfa47f40b, 0x6016f70b, 
+    0x8000f8c3, 0x9025f842, 0x8025f843, 0x0655ea4f, 0xf842442e, 0xf8434026, 0xf1c77026, 0xf8420700, 
+    0xf8434015, 0xf8dd7015, 0xf04fe030, 0xb4200402, 0x6034f850, 0x0004f100, 0x7034f850, 0x0004f100, 
+    0xf90cfa04, 0xf9a9fa99, 0x0109eba5, 0xf1a1fa91, 0xf10cfa21, 0x01fef001, 0x8031f850, 0x0004f100, 
+    0x1031f850, 0x000cf1a0, 0x0a08eb06, 0x0608eba6, 0x0801eb07, 0x0701eba7, 0x1029f85e, 0x0767ea4f, 
+    0xf511fb36, 0x0600f1c6, 0x5501fb38, 0xf601fb36, 0x0a6aea4f, 0x6611fb38, 0x0105eb0a, 0x0a05ebaa, 
+    0x0806eb07, 0x0706eba7, 0xf10bfa41, 0xf80bfa48, 0xfa0bfa4a, 0xf70bfa47, 0x1029f842, 0x8029f843, 
+    0xeb09bc20, 0xf8420605, 0xf843a026, 0xeba57026, 0xf1c70609, 0xf8420700, 0xf843a026, 0x442e7026, 
+    0x0800f1c8, 0x1026f842, 0x8026f843, 0x0402f104, 0xdb9c42ac, 0x5ffce8bd, 0x00004770, 0x5ffce92d, 
+    0xf04f9e0d, 0xfa0b0b01, 0xea4ff506, 0xf1a60555, 0xf1c90902, 0x68060c1f, 0x9025f850, 0x4015f850, 
+    0x7015f851, 0x0700f1c7, 0x0a09eba6, 0xea4f44b1, 0xea4f0a6a, 0xf8420969, 0xf8429b04, 0xf842ab04, 
+    0xf8424b04, 0xf8dd790c, 0xf04fe030, 0xfa040402, 0xfa99f90c, 0xf850f9a9, 0xf8513029, 0xeba58029, 
+    0xf8500609, 0xf851a026, 0xeb037026, 0xeba3060a, 0xeba8030a, 0x44b80a07, 0x7029f85e, 0x0a6aea4f, 
+    0xfb07fb33, 0xf317fb33, 0xbb17fb38, 0x0800f1c8, 0x0666ea4f, 0x3307fb38, 0x0806eb03, 0x0303eba6, 
+    0x060aeb0b, 0x0b0aebab, 0x8034f842, 0x0204f102, 0x6034f842, 0x0204f102, 0x0809eba5, 0xf8a8fa98, 
+    0xf80cfa28, 0x08fef008, 0x3038f842, 0x0204f102, 0xb038f842, 0x020cf1a2, 0x0402f104, 0xdbb642ac, 
+    0xf1a59d0d, 0xf04f0c01, 0xfa0a0a01, 0xea4ffb05, 0xb4040b9b, 0x98009a0d, 0x0e00f04f, 0x0b5bea4f, 
+    0xcd04f84d, 0x1b08f850, 0x3b08f850, 0x4b08f850, 0x5914f850, 0x6b08f850, 0x7b08f850, 0x8b08f850, 
+    0x9904f850, 0x0c03eb01, 0x0103eba1, 0x0307eb06, 0x0607eba6, 0x0705eb04, 0x0405eba4, 0x0509eb08, 
+    0x0809eba8, 0x0907eb0c, 0x0c07ebac, 0x0705eb03, 0x0305eba3, 0x0508eb01, 0x0108eba1, 0x0804eb06, 
+    0x0604eba6, 0x5908f840, 0xc908f840, 0x1908f840, 0x9b1cf840, 0x6908f840, 0x3908f840, 0x8908f840, 
+    0x7b1cf840, 0x0e01f10e, 0xf6ff45de, 0xf85dafbb, 0xea4fcb04, 0xea4f0b5b, 0xf1ac0a8a, 0x98000c02, 
+    0x0104f100, 0x0e00f04f, 0x2982f645, 0xf8506803, 0x680c503a, 0x603af851, 0x0805eb03, 0x0305eba3, 
+    0x0506eb04, 0x0406eba4, 0x303af840, 0x403af841, 0x8b08f840, 0x5b08f841, 0x503af850, 0x603af851, 
+    0x0545ea4f, 0x0646ea4f, 0x680c6803, 0x0806eba5, 0xfb384435, 0xfb35f809, 0xeb03f509, 0xeba30608, 
+    0xeb040308, 0xeba40805, 0xf8400405, 0xf841303a, 0xf840403a, 0xf8416b08, 0x680c8b08, 0x603af851, 
+    0xf8506803, 0xeba3503a, 0x44330806, 0x0605eb04, 0x0405eba4, 0x303af840, 0x403af841, 0x8b08f840, 
+    0x6b08f841, 0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 
+    0x0506eba5, 0xf809fb38, 0xf509fb35, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x303af840, 
+    0x403af841, 0x6b08f840, 0x8b08f841, 0x00caeb00, 0x01caeb01, 0x0e01f10e, 0xf6ff45de, 0xea4faf87, 
+    0xea4f0b5b, 0xf1ac0a4a, 0x98000c01, 0x0104f100, 0x0e00f04f, 0x6803b404, 0x503af850, 0xf851680c, 
+    0xeb03603a, 0xeba30805, 0xeb040305, 0xeba40506, 0xea4f0406, 0xea4f03e3, 0xea4f04e4, 0xea4f08e8, 
+    0xf84005e5, 0xf841303a, 0xf840403a, 0xf8418b08, 0xeb025b08, 0x680302cb, 0x503af850, 0xf851680c, 
+    0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 
+    0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 
+    0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0x503af850, 0x603af851, 0x0545ea4f, 
+    0x0646ea4f, 0x680c6803, 0x0806eba5, 0xfb384435, 0xfb35f809, 0xeb03f509, 0xeba30608, 0xeb040308, 
+    0xeba40805, 0xea4f0405, 0xea4f03e3, 0xea4f04e4, 0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 
+    0xf8416b08, 0xeb028b08, 0x680302cb, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 
+    0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 
+    0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 
+    0x8b08f841, 0x02cbeb02, 0xf851680c, 0x6803603a, 0x503af850, 0x0806eba3, 0xeb044433, 0xeba40605, 
+    0xea4f0405, 0xea4f03e3, 0xea4f04e4, 0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8418b08, 
+    0xeb026b08, 0x680302cb, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 
+    0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 
+    0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 
+    0x02cbeb02, 0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 
+    0x0506eba5, 0xf809fb38, 0xf509fb35, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 
+    0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 
+    0xf8506803, 0x680c503a, 0x603af851, 0x0545ea4f, 0xea4f6817, 0xfb350646, 0xf1c5f807, 0xfb350500, 
+    0xfb36f517, 0xfb368817, 0xeb035507, 0xeba30608, 0xeb040308, 0xeba40805, 0xea4f0405, 0xea4f03e3, 
+    0xea4f04e4, 0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8416b08, 0xeb028b08, 0xeb0002cb, 
+    0xeb0100ca, 0xbc0401ca, 0x0e01f10e, 0xf6ff45de, 0xea4faea1, 0xea4f0b5b, 0xf1ac0a4a, 0x98000c01, 
+    0x0104f100, 0x0e00f04f, 0x0900f04f, 0x6803b404, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 
+    0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 
+    0x0805eb04, 0x0405eba4, 0x303af840, 0x403af841, 0x02cbeb02, 0x6b08f840, 0x8b08f841, 0x0901f109, 
+    0xf6ff45d1, 0xeb00afd4, 0xeb0100ca, 0xbc0401ca, 0x0e01f10e, 0xf6ff45de, 0xea4fafc7, 0xea4f0b5b, 
+    0xf1ac0a4a, 0xf1bc0c01, 0xdcb80f00, 0xe8bdbc04, 0x47705ffc, 0x41f0e92d, 0x88079c06, 0x0701ea27, 
+    0x0801ea47, 0x0500f04f, 0xf8a08007, 0x88168000, 0x6025f843, 0x0501f105, 0xdbf542a5, 0xe8bdbf00, 
+    0xe92d81f0, 0x880541f0, 0x0701ea25, 0x0801ea45, 0xf8a08007, 0xf04f8000, 0xf04f0604, 0xf8320500, 
+    0xf8327b02, 0xea488b02, 0xf8434707, 0xf1057b04, 0x42b50501, 0xe8bddbf3, 0x000081f0, 0x5ffce92d, 
+    0xf0f1fb90, 0x9ffce8bd, 0x5ffce92d, 0x0210f1c1, 0xf102fa10, 0xfa51b209, 0xe8bdf002, 0x00009ffc, 
+    0xe92d4001, 0xe14f0000, 0xe3100020, 0x115e00b2, 0x13c00cff, 0x051e0004, 0x03c004ff, 0xe35000fe, 
+    0x0a000007, 0xe35000ff, 0x0a000009, 0xe3500000, 0x0a000001, 0xe8bd4001, 0xe1b0f00e, 0xe8bd4001, 
+    0xeafffc60, 0xe14f0000, 0xe38000c0, 0xe16ff000, 0xea000003, 0xe14f0000, 0xe3c000c0, 0xe16ff000, 
+    0xeaffffff, 0xe8bd4001, 0xe1b0f00e, 0x5ffce92d, 0x0400f04f, 0x5024f851, 0xf6f5fbb0, 0x6024f842, 
+    0x0401f104, 0xf6ff429c, 0xe8bdaff5, 0x00009ffc, 0x5ffce92d, 0xf0f1fbb0, 0x9ffce8bd, 0x0004ec74, 
+    0x00050274, 0xe51f0010, 0xe12fff1e, 0xe92d0003, 0xe59f0010, 0xe59f1010, 0xe5801000, 0xe8bd0003, 
+    0xe25ef004, 0xe320f000, 0xf0003010, 0xdef0dead, 0xe51ff004, 0x0000ddbd, 0xe51ff004, 0x00007b73, 
+    0x46c04778, 0xe92d41f0, 0xf10c0080, 0xe59f1028, 0xe5910000, 0xe3500000, 0x0a000003, 0xe3a00000, 
+    0xe5810000, 0xf1080080, 0xe8bd81f0, 0xf1080080, 0xf57ff04f, 0xe320f003, 0xe8bd81f0, 0x00040244, 
+    0x5ff0e92d, 0x0200f04f, 0x0300f04f, 0x3022f840, 0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0x00009ff0, 
+    0x5ff0e92d, 0x0200f04f, 0x0300f04f, 0x3012f820, 0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0x00499ff0, 
+    0x20c1ea50, 0x2004bf18, 0xbf180d4a, 0x0001f040, 0x72fff240, 0x5f51ebb2, 0xf040bf08, 0x28010002, 
+    0x2005bf08, 0xe92d4770, 0x460441f0, 0x461e4615, 0xf0371e4f, 0xeb000206, 0xe9d101c7, 0xd00d0100, 
+    0x4633462a, 0xf868f001, 0xeb041e7f, 0xe9d303c7, 0xf0002300, 0xf037fd89, 0xd1f10206, 0xd0232f02, 
+    0xd0112f04, 0xd1312f06, 0x4633462a, 0xf854f001, 0x230ae9d4, 0xfd78f000, 0x4633462a, 0xf84cf001, 
+    0x2308e9d4, 0xfd70f000, 0x4633462a, 0xf844f001, 0x2306e9d4, 0xfd68f000, 0x4633462a, 0xf83cf001, 
+    0x2304e9d4, 0xfd60f000, 0x4633462a, 0xf834f001, 0x2302e9d4, 0xfd58f000, 0x4633462a, 0xf82cf001, 
+    0x2300e9d4, 0x41f0e8bd, 0xbd4ef000, 0x81f0e8bd, 0x22004902, 0x46104613, 0xbe02f000, 0x3ff00000, 
+    0xbd42f000, 0x46132200, 0x46114610, 0xbdf8f000, 0xf2402000, 0xf04f3201, 0xf00141e0, 0x0000be34, 
+    0x20004a02, 0xf0010711, 0x0000be2e, 0xfffffd01, 0x4df0e92d, 0x461c4616, 0x2800460f, 0xf021b094, 
+    0xf0234100, 0xbf144200, 0x25002501, 0xc410f8df, 0x0547eb05, 0xea4f4465, 0x429d036c, 0x0035d32b, 
+    0x2501bf18, 0x0544eb05, 0x44ac4bfe, 0xd322459c, 0x0306ea52, 0xd0024bfc, 0xd105429f, 0xb014b948, 
+    0x20004619, 0x8df0e8bd, 0xbf082800, 0x0c00f04f, 0xf04fd001, 0xeb0c0c01, 0xf5130347, 0xd80a1f00, 
+    0xbf142e00, 0x0c01f04f, 0x0c00f04f, 0x0344eb0c, 0x1f00f513, 0x4632d907, 0x46394623, 0xe8bdb014, 
+    0xf7ff4df0, 0xf8dfbf9d, 0xf04f83a4, 0x2f000a00, 0x4542bfb8, 0x4be6da23, 0xbfa8429a, 0x0a02f04f, 
+    0x4be1da1d, 0xdc1a4293, 0xeb034be2, 0x2b145322, 0xf1c3dd08, 0xfa260c34, 0xfa03f30c, 0x45b4fc0c, 
+    0xe008d10d, 0xf1c3b95e, 0xfa220c14, 0xfa03f30c, 0x4594fc0c, 0xf003d103, 0xf1c30301, 0xea510a02, 
+    0xd11b0300, 0xda192c00, 0xbf182f00, 0x0f02f1ba, 0xf1bad002, 0xd0070f01, 0xf7fe2002, 0xb014fb54, 
+    0x4df0e8bd, 0xbf54f7ff, 0xf7fe2002, 0xf7fffb4c, 0xf081ff4f, 0xb0144100, 0x8df0e8bd, 0xd16b0033, 
+    0xd1204542, 0x4280f107, 0x1280f512, 0x2800bf02, 0x49bd2000, 0x48bcd0ef, 0xdc054288, 0xbfa42c00, 
+    0x46214618, 0xe007dae7, 0xda051e20, 0xf080b014, 0x46184100, 0x8df0e8bd, 0x447949b7, 0x0100e9d1, 
+    0xe8bdb014, 0xf8df8df0, 0x4562c2c0, 0x2c00d12a, 0xb139da24, 0xd1174541, 0xbf042800, 0x46022000, 
+    0xe006d11c, 0x2002b140, 0xfb0df7fe, 0xff20f7ff, 0x4639460a, 0xbad2f000, 0x46394aa4, 0x2000b014, 
+    0x011ef362, 0x8df0e8bd, 0x463bda08, 0x46614602, 0x2000b014, 0x4df0e8bd, 0xbd02f000, 0xb0144639, 
+    0x8df0e8bd, 0xda174541, 0x4f80f1b4, 0xf1a4d00c, 0xf1b35300, 0xd10f53ff, 0xdb0d1e3b, 0xb0144619, 
+    0x4df0e8bd, 0xbbd8f000, 0x463bb014, 0x46194602, 0x4df0e8bd, 0xbf00f000, 0xf0270005, 0xd1384300, 
+    0x4541b1d1, 0x2f00d135, 0x2c00dd04, 0x2000bfa4, 0xdad44641, 0xdd012f00, 0xdb1f2c00, 0xda162f00, 
+    0xdb142c00, 0x0000f04f, 0x0f01f1ba, 0x497fbf14, 0xb0144982, 0x8df0e8bd, 0x0f02f1ba, 0x2f00bf18, 
+    0xf1bad00c, 0xd1090f01, 0xda072f00, 0x2f00e00b, 0x2c00bfb8, 0xf1bada0d, 0xd0040f01, 0x2000b014, 
+    0xe8bd4601, 0xb0148df0, 0xf04f2000, 0xe8bd4100, 0xf04f8df0, 0x46b80c01, 0x7ce7eb0c, 0xc044f8cd, 
+    0x0c0aea5c, 0xf8dfd00d, 0x4562c1b8, 0xf8dfdd7e, 0x4b6dc1b4, 0xdd124562, 0xdb0a428b, 0xdb182c00, 
+    0x2001e023, 0xfa7ff7fe, 0xe8bdb014, 0xf7ff4df0, 0x4a5dbe89, 0xdc02428a, 0xdc0a2c00, 0x4299e015, 
+    0x2c00da02, 0xe004da11, 0x42994b57, 0x2c00dd19, 0x2002dd0b, 0xfa67f7fe, 0xfe7af7ff, 0xb0144a53, 
+    0x021ef361, 0xe8bd4611, 0x20028df0, 0xfa5bf7fe, 0xfe76f7ff, 0xb0144a4c, 0x021ef361, 0xe8bd4611, 
+    0x22008df0, 0xf0014641, 0xf06ff883, 0x46050201, 0xf001460f, 0x4b4dfc98, 0x3255f04f, 0xffa0f000, 
+    0x463b462a, 0xfe68f000, 0x22004b49, 0xff98f000, 0x463b462a, 0x468b4680, 0x46194610, 0xfe5cf000, 
+    0x465b4642, 0xfe58f000, 0x46804b42, 0xf04f4628, 0x910942c0, 0xf0004639, 0x9107fe4f, 0x46404683, 
+    0x4b3c4a3d, 0xf0009909, 0x4a3cfe47, 0x46284680, 0x91014b3b, 0xf0004639, 0x9b01fe3f, 0xf0014642, 
+    0x900cf847, 0x4602460d, 0xe000460b, 0x9907e00e, 0xf0004658, 0x9b07fb59, 0x465a4688, 0x46382700, 
+    0xf836f001, 0x462b9a0c, 0xb976f000, 0x1f80f5b1, 0x0000f04f, 0x4628da07, 0x22354619, 0xfc43f001, 
+    0xf06f4605, 0xeb000034, 0xf3c15221, 0x4b250013, 0x31fff2a2, 0x677ff040, 0xf0474298, 0x91015740, 
+    0xf04fbfd8, 0xdd0c0b00, 0x4281491f, 0xf04fbfc8, 0xdc060b01, 0x0b00f04f, 0xf5a79801, 0x1c401780, 
+    0x481a9001, 0x46394478, 0x00cbeb00, 0xe9d09704, 0x46282300, 0x93099212, 0xfffaf000, 0x0000e028, 
+    0x001fffff, 0x000fffff, 0x3ff00000, 0x7ff00000, 0x43400000, 0xfffffc01, 0x00001dca, 0xfff00000, 
+    0x41e00000, 0x43f00000, 0x3fefffff, 0x3fd55555, 0x3fe00000, 0x3ff71547, 0x652b82fe, 0xf85ddf44, 
+    0x3e54ae0b, 0x0003988e, 0x000bb67a, 0x00001a98, 0x1007e9cd, 0x9b094628, 0x99049a12, 0xfae4f000, 
+    0x20004602, 0x49fe460b, 0xfb9af000, 0x46029100, 0x900c460b, 0x1007e9dd, 0xfdaef000, 0x46889006, 
+    0x447848f8, 0x68009a12, 0xf04f900e, 0xea405000, 0xeb000067, 0xf500408b, 0x9b092100, 0x2700980e, 
+    0xf0009102, 0x9b04ffa5, 0xf000462a, 0x463afec9, 0xf0004643, 0x9104fd91, 0x46384605, 0x9b024641, 
+    0xf0009a0e, 0xe9ddfd89, 0xf0003207, 0x9b04feb9, 0xf000462a, 0x9b00ff8d, 0xf0009a0c, 0x9a06fd7d, 
+    0x91094643, 0x900c4619, 0xf0004610, 0x4605fd75, 0x48dd4602, 0x9107460b, 0x44782106, 0xfcf3f7ff, 
+    0x462a9b07, 0x90009102, 0x46194610, 0xfd64f000, 0x9a009b02, 0xfd60f000, 0x46439a06, 0x46384605, 
+    0x46199100, 0xfa80f000, 0x9a0c9b09, 0xfd54f000, 0x462a9b00, 0xfa78f000, 0x4643463a, 0x90089100, 
+    0x46194610, 0xfd48f000, 0x22004bc8, 0x90049107, 0xfa6af000, 0x9a089b00, 0xfa66f000, 0x460d4bc3, 
+    0x4638463a, 0xff44f000, 0x9a049b07, 0xff40f000, 0x9a089b00, 0xfe64f000, 0x9104463a, 0x4641462b, 
+    0x4610900a, 0xfd28f000, 0x1007e9cd, 0x9a064643, 0x980a9904, 0xfd20f000, 0x4680462b, 0x460d980c, 
+    0x9909463a, 0xfd18f000, 0x462b4642, 0xfa3cf000, 0x46809100, 0x460b4602, 0x1007e9dd, 0xfa34f000, 
+    0x3207e9dd, 0x2000460f, 0xf0004605, 0x9b00ff11, 0xf0004642, 0x4ba6fe35, 0x46284680, 0x4260f04f, 
+    0x46399109, 0xfcf8f000, 0x90049102, 0x4aa14640, 0x99094b9f, 0xfcf0f000, 0x46804a9f, 0x4b9f4628, 
+    0x46399103, 0xfce8f000, 0x46429b03, 0xfa0cf000, 0x447a4a9b, 0x03cbeb02, 0x2300e9d3, 0xfa04f000, 
+    0x98014605, 0xf0009105, 0x9000fc70, 0xe9dd462a, 0x91030304, 0xf0009902, 0x4a92f9f7, 0xeb02447a, 
+    0xe9d303cb, 0x46932300, 0xf0009301, 0x9b03f9ed, 0xf0009a00, 0x9b03f9e9, 0x9a004688, 0x46382700, 
+    0xfec6f000, 0x465a9b01, 0xfec2f000, 0x9a049b02, 0xfebef000, 0x462a9b05, 0xfde2f000, 0x4d789b11, 
+    0xf1aa2200, 0xea530c01, 0x9206030c, 0x4d7ed101, 0xf04f9206, 0x46320a00, 0xf0004623, 0x4623fc9d, 
+    0x46839103, 0x46304652, 0xf0004619, 0x463afea1, 0xf0004643, 0x9b03fc91, 0xf000465a, 0x463af9b5, 
+    0x46064643, 0x4650468b, 0xf0004621, 0x4604fc85, 0x4632460f, 0xf000465b, 0x4a6cf9a7, 0x4291468a, 
+    0xebaadb21, 0xea530302, 0xd1100200, 0x463b4622, 0xfe7ef000, 0x46804a66, 0x4b664630, 0x46599101, 
+    0xf992f000, 0x46429b01, 0xfd64f000, 0x2002d22b, 0xf839f7fe, 0xfc4cf7ff, 0x4629460a, 0xf362b014, 
+    0xe8bd011e, 0x4b5c8df0, 0x4200f02a, 0xd31a429a, 0xeb0a4a5a, 0xea530302, 0xd1080200, 0x463b4622, 
+    0xfe56f000, 0x465b4632, 0xfd44f000, 0x2002d80b, 0xf819f7fe, 0xfc34f7ff, 0x5310ea4f, 0x4629460a, 
+    0x5303ea4f, 0x494ee7da, 0x0800f04f, 0xf02a4a4d, 0x42824000, 0x5120eb01, 0x484bda25, 0x1c80f44f, 
+    0x1c494478, 0xfa2c6802, 0x4450f001, 0x0301f1ac, 0x510af3c0, 0x31fff2a1, 0x0f00f1ba, 0xf301fa23, 
+    0x0c13f3c0, 0x0114f1c1, 0x1c80f44c, 0xf801fa2c, 0x0303ea20, 0xf1c8bfb8, 0x46200800, 0xf0004639, 
+    0x4604fe17, 0x4630460f, 0x46224659, 0xf000463b, 0x4b36f92b, 0x0a00f04f, 0x46529103, 0xf0004650, 
+    0xe9cdfbfb, 0x46501007, 0x4b324a31, 0xf0009903, 0x9102fbf3, 0x463b4622, 0x90049903, 0xf0004650, 
+    0x4632fdf7, 0xf000465b, 0x4a2bfd1b, 0xf0004b2b, 0x9b02fbe3, 0xf0009a04, 0x4607f907, 0x4602468a, 
+    0xe9dd460b, 0xf0001007, 0xe9ddf8ff, 0x46043207, 0xf000460e, 0x463afddd, 0xf0004653, 0x4622fd01, 
+    0x900c4633, 0x4610460f, 0xf0004619, 0x4682fbc5, 0x481b4602, 0x460b468b, 0x44782105, 0x0000e032, 
+    0x3ff00000, 0x00001a82, 0x000019b2, 0x40080000, 0x3feec709, 0xdc3a03fd, 0x145b01f5, 0xbe3e2fe0, 
+    0x0000188a, 0x00001850, 0xbff00000, 0x40900000, 0x652b82fe, 0x3c971547, 0x4090cc00, 0x3f6f3400, 
+    0xfffffc01, 0x3fe00000, 0x00001784, 0x3fe62e43, 0x0ca86c39, 0xbe205c61, 0xfefa39ef, 0x3fe62e42, 
+    0x00001682, 0xfb0ff7ff, 0x465b4652, 0xfb84f000, 0x46334622, 0xfcb4f000, 0x46829a0c, 0x463b468b, 
+    0x46314620, 0xfb78f000, 0x463b9a0c, 0xf89cf000, 0x46072200, 0xf04f4650, 0x91004380, 0xf0004659, 
+    0x9103fd77, 0x465b4652, 0x900a4631, 0xf0004620, 0x9b03fb63, 0xf0009a0a, 0x9b00f943, 0xf000463a, 
+    0x4622fd67, 0xf0004633, 0x4b12fd63, 0xf0002200, 0x460efc87, 0x5108eb01, 0x15084604, 0xdc102800, 
+    0x46204642, 0xf0014631, 0xf7fff96e, 0x2804fab8, 0xf7ffbf08, 0x4642fb35, 0x46314620, 0xf963f001, 
+    0x98064604, 0x4629460b, 0x4622b014, 0x4df0e8bd, 0xbb32f000, 0x3ff00000, 0x41f0e92d, 0x460f4606, 
+    0xfc6af000, 0x460d0004, 0x2001bf18, 0xf0204328, 0xf1c04000, 0xf100607f, 0x0fc040e0, 0x1c30d00e, 
+    0x2001bf18, 0xf0204338, 0xf1c04000, 0xf100607f, 0x0fc040e0, 0x2001bf04, 0xfee5f7fd, 0x46294620, 
+    0x81f0e8bd, 0x4200f021, 0x5260f1a2, 0x1f80f5b2, 0x4300f001, 0xf1d2bf28, 0xd90b6c7f, 0x1c00ea5f, 
+    0x02c2ea43, 0x7050eb42, 0x4770bf18, 0xf020bf28, 0x47700001, 0x1f80f5b2, 0x4618bfbc, 0xea4f4770, 
+    0xf51c0c41, 0xd2021f00, 0xf0014608, 0xb570b860, 0xfb8cf000, 0x89000000, 0xbff6f7ff, 0x4000f04f, 
+    0x0080f5a0, 0x00004770, 0xea91b510, 0xbf480f03, 0x4300f083, 0x84e4f100, 0xeb711a84, 0xd2050c03, 
+    0xeb431912, 0x1b00030c, 0x010ceb61, 0xe124f8df, 0x5411ea4f, 0x5c13eba4, 0x0f43ea1e, 0xea9ebf18, 
+    0xd0735f44, 0x030eea23, 0x0e20f1dc, 0x5104ea21, 0x1380f443, 0xfa22d332, 0xeb10fe0c, 0xfa23000e, 
+    0xeb41fe0c, 0xf1cc010e, 0xfa030e20, 0xeb10fe0e, 0xf151000e, 0xf5b10100, 0xf1cc1f80, 0xd2320e20, 
+    0x5104eb01, 0xf20efa12, 0x4010e8bd, 0x4770bf58, 0xbf381c40, 0x0242ea5f, 0x4770bf18, 0xbf142800, 
+    0x0001f020, 0x0100f141, 0x0341ea4f, 0x1f00f513, 0x4770bf38, 0x41c0f1a1, 0xbb76f000, 0xeb432a01, 
+    0xf1ac0203, 0xf1dc0c20, 0xbf320e1f, 0x0e00f04f, 0xf30cfa23, 0x0003eb10, 0x5104eb41, 0x5f11ebb4, 
+    0xeba1d0d0, 0xf5015104, 0x08491180, 0x0030ea5f, 0x5104eb01, 0xf150d30e, 0xbf380000, 0xfe0efa12, 
+    0xe8bdd108, 0xe7c94010, 0xbf381c40, 0x0242ea5f, 0xe7c3d1ca, 0x4010e8bd, 0x0341ea4f, 0x1f00f513, 
+    0x4770bf38, 0x41c0f1a1, 0xbb3ef000, 0x5f44ea9e, 0xea11d008, 0xe8bd0f5e, 0xbf044010, 0x4100f001, 
+    0x47702000, 0x4010e8bd, 0xf000b570, 0xbf00fadf, 0x3ebefb64, 0xffe00000, 0xf04f4902, 0xf0010000, 
+    0xbf00b820, 0x7ff80000, 0xbf581049, 0x4140f1c1, 0xbf58105b, 0x4340f1c3, 0xf3ef428b, 0x47708000, 
+    0x41c0e92d, 0xf8dfb430, 0xea3cc2a0, 0xbf181411, 0x1413ea3c, 0x80ecf000, 0x0503ea81, 0x1411ea1c, 
+    0x74d5ea44, 0xea1cbf18, 0xf0001513, 0xeba480c7, 0xf04f0405, 0xea454500, 0xea4521c1, 0xea4123c3, 
+    0xea435150, 0xf1045352, 0x4299747f, 0x3400f504, 0x20c0ea4f, 0x22c2ea4f, 0x4290bf08, 0x809cf000, 
+    0x6513ea4f, 0x1640f20f, 0xea4f5d76, 0xfb064513, 0xf1c7f705, 0xfb067780, 0xea4ff707, 0xfba737d7, 
+    0x42766803, 0x3880f5c8, 0xce06fba7, 0xf1a8bf38, 0xfb070801, 0xf04fe608, 0xfba60e00, 0xfbe68c02, 
+    0xf1dcce03, 0xf1ce0c00, 0xbf384e00, 0x0e01f1ae, 0x580cfba6, 0x0700f04f, 0x0500f04f, 0x870efbe6, 
+    0xc608fba1, 0xce07fba0, 0x060eeb16, 0x0500f145, 0x6507fbe1, 0x4ee0f115, 0xf5a4bf7e, 0xea5f3480, 
+    0x416d0646, 0x0780f116, 0x0500f145, 0x2717ea4f, 0x6606ea4f, 0x6705ea47, 0x46def1a6, 0x5f80f1b6, 
+    0x2515ea4f, 0x4638d91f, 0x0c01f024, 0x71c4eb05, 0x6ffef1bc, 0x110ceb01, 0xbcf0d802, 0x8100e8bd, 
+    0xbf5c4224, 0x1e80f501, 0x7fc4ea9e, 0xbcf0d402, 0x8100e8bd, 0xd4384224, 0xf1a1bcf0, 0xe8bd41c0, 
+    0xf0004100, 0xea4fba71, 0xea4222d2, 0xea4f5243, 0xfba723d3, 0xea4f8602, 0xea4020d0, 0xfb075041, 
+    0xea1e6603, 0xea4f0f0e, 0xfb0521d1, 0xbf586602, 0x5600eba6, 0x5600ebb6, 0x0e52ea4f, 0x7ec3ea4e, 
+    0x0e0eeb18, 0x0e53eb56, 0xeb18d5bd, 0x415e0802, 0xf1551c7f, 0xe7b60500, 0x1580f44f, 0x0700f04f, 
+    0x0600f04f, 0x0800f04f, 0xbcf0e7ad, 0x0000f04f, 0x41c0f101, 0x4100f001, 0x8100e8bd, 0x1f0cea11, 
+    0x1513ea0c, 0xe00cd000, 0x1f0cea13, 0x8025f000, 0x0000f04f, 0xea81bcf0, 0xf0010103, 0xe8bd4100, 
+    0xbcf08100, 0x4100e8bd, 0x0103ea81, 0xba1cf000, 0xe8bdbcf0, 0xb5704100, 0xf9c8f000, 0x3efc7e09, 
+    0xb807f000, 0x0103ea81, 0x0000f04f, 0x4100f001, 0xea814770, 0xf0000103, 0xbcf0ba07, 0x4100e8bd, 
+    0x0000f04f, 0x47704921, 0xf9fbfdff, 0xf2f4f5f7, 0xebedeef0, 0xe4e6e8e9, 0xdee0e1e3, 0xd8dadbdd, 
+    0xd3d4d5d7, 0xcdcfd0d1, 0xc8cacbcc, 0xc4c5c6c7, 0xbfc0c1c2, 0xbbbcbdbe, 0xb7b8b9ba, 0xb3b4b5b6, 
+    0xafb0b1b2, 0xabacadae, 0xa8a8a9aa, 0xa4a5a6a7, 0xa1a2a3a3, 0x9e9f9fa0, 0x9b9c9c9d, 0x9899999a, 
+    0x95969797, 0x93939495, 0x90919192, 0x8e8e8f8f, 0x8b8c8c8d, 0x89898a8b, 0x87878888, 0x84858586, 
+    0x82838384, 0x80818182, 0x07ff0000, 0x7ff80000, 0x0341ea4f, 0x5353ea4f, 0x6380f5a3, 0x031ef1d3, 
+    0xf1d3bfc8, 0xdd0c0c21, 0x4200f04f, 0x22c1ea42, 0x5250ea42, 0xfc03fa32, 0x7ce1ea8c, 0x70e1ebac, 
+    0x2b104770, 0x2000bfc4, 0xf5034770, 0xf1bc7c78, 0xd0043fff, 0x4200f06f, 0x0021ea82, 0xb5704770, 
+    0xf944f000, 0x80249249, 0x47702000, 0x0000e7f2, 0x5311ea4f, 0x6380f5a3, 0x031ef1d3, 0xf1d3bfa8, 
+    0xdb080c20, 0x4200f04f, 0x22c1ea42, 0x5250ea52, 0xf003fa32, 0x42094770, 0x2b10d40b, 0x2000bfc4, 
+    0xf5034770, 0xf1bc7c78, 0xd0053fff, 0x30fff04f, 0xf04f4770, 0x47700000, 0xf000b570, 0xbf00f917, 
+    0x80249249, 0x47702000, 0xf010e7f0, 0xbf484200, 0xfab04240, 0xfa10f380, 0xd00af103, 0x031df1c3, 
+    0x6380f503, 0x5041ea4f, 0x5203eb02, 0x21d1eb02, 0xf04f4770, 0x47700000, 0xf380fab0, 0xf103fa10, 
+    0xf1c3d00a, 0xf503031d, 0xea4f6380, 0xea4f5041, 0xeb025203, 0x477021d1, 0x0000f04f, 0x00004770, 
+    0x0c03ea51, 0xf51cd417, 0xbf581f80, 0x1f80f5bc, 0x8006f100, 0xbf184299, 0xbf084770, 0x47704290, 
+    0xf511d707, 0xbf581f80, 0x1f80f513, 0x4299d419, 0x42894770, 0xf51c4770, 0xd5081f80, 0x1f80f5bc, 
+    0x428bd5f7, 0x4770bf18, 0x4282bf08, 0xf44f4770, 0xeb1c1c00, 0xbf380f41, 0x0f43eb1c, 0x428bd201, 
+    0xb5704770, 0xf8b2f000, 0x00492492, 0x5100f04f, 0x5380f04f, 0xbdd8f7ff, 0xc148f8df, 0xea1cb570, 
+    0xbf1e1e11, 0x1513ea1c, 0x0f0cea9e, 0x0f0cea95, 0x806ff000, 0x0403ea81, 0x134cea23, 0x7ed4ea4e, 
+    0x114cea21, 0x1180f441, 0x1380f443, 0xfba144ae, 0xfba04c02, 0xf1ae6503, 0x19367e7f, 0x050ceb55, 
+    0x4c03fba1, 0x0300f14c, 0x1c02fba0, 0x060ceb16, 0xf1534165, 0x42090300, 0xf046bf18, 0xf4130601, 
+    0xd10b7f00, 0x3103ea4f, 0x3005ea4f, 0xea410334, 0xea405115, 0xf06f5016, 0xe00a0203, 0x21c3ea4f, 
+    0x20c5ea4f, 0xea4102f4, 0xea405155, 0xf06f5056, 0xeb020202, 0xeb01422e, 0xea855502, 0xd00a71ce, 
+    0x0c44ea5f, 0xf024bf18, 0xf1504400, 0xf1410000, 0xea200100, 0xf24070d4, 0x45627cfe, 0xbd70d200, 
+    0xbf1442a8, 0x4480f04f, 0x4440f04f, 0xbf082e00, 0xf1be2400, 0xbfa86f80, 0x41c0f1a1, 0x4070e8bd, 
+    0x8082f280, 0x0000f04f, 0x41c0f101, 0x4100f001, 0xea9e4770, 0xea0c0f0c, 0xbf181513, 0x0f0cea95, 
+    0xf04fd006, 0xea810000, 0xf00e0e03, 0xbd704100, 0xf81cf000, 0x3e010089, 0xb807f000, 0xb809f000, 
+    0x0c43ea4f, 0x5c5cea5f, 0xea81d008, 0xf0000103, 0xea4fb85b, 0xea5f0c41, 0xd1f65c5c, 0x0000f04f, 
+    0x47704901, 0x07ff0000, 0x7ff80000, 0x0e02f10e, 0x0e03f02e, 0x6b04f85e, 0xd4054236, 0xeb432a01, 
+    0xf5150503, 0xd8121f00, 0xeb412801, 0xf51c0c01, 0xd80c1f00, 0xea4fd10e, 0xf5157cd1, 0xeb0c1f00, 
+    0xf10c0c4c, 0xbf080c02, 0x7cd3eb4c, 0xf04fe004, 0xe0010c08, 0x7cd3ea4f, 0x054ceb0c, 0xf605fa26, 
+    0x0607f006, 0x0c04f1b6, 0xeb0ed206, 0xe8bd0c86, 0xf04c4070, 0x47600c01, 0xf00ce8df, 0x02020b09, 
+    0x4100f04f, 0x0000f04f, 0x2100f5a1, 0x4619bd70, 0x28014610, 0x0401eb51, 0xf5d4bf18, 0xbf841400, 
+    0xf0012000, 0xbd704100, 0xf5a00808, 0xea4f1100, 0x47700131, 0x0c01ea53, 0xf51cd417, 0xbf581f80, 
+    0x1f80f5bc, 0x8006f100, 0xbf18428b, 0xbf084770, 0x47704282, 0xf513d707, 0xbf581f80, 0x1f80f511, 
+    0x428bd419, 0x429b4770, 0xf51c4770, 0xd5081f80, 0x1f80f5bc, 0x4299d5f7, 0x4770bf18, 0x4290bf08, 
+    0xf44f4770, 0xeb1c1c00, 0xbf380f43, 0x0f41eb1c, 0x4299d201, 0xb40f4770, 0xbc03bc0c, 0xbec1f7ff, 
+    0x0f03ea91, 0xf081b510, 0xf53f4100, 0xf083abf5, 0xf0004300, 0x0000b8d5, 0x41f0e92d, 0x1c80f501, 
+    0x1f00f5bc, 0x80a9f2c0, 0x5c11ea4f, 0x510cea21, 0x0cfdf10c, 0x1180f441, 0x0c5cea5f, 0x7cc0f50c, 
+    0x0040d301, 0xa4304149, 0xea410289, 0x02875190, 0x0c0a0e8e, 0xfb045da4, 0xfb02f604, 0xf1c6f606, 
+    0xfba44640, 0x0df66206, 0x2642ea46, 0xf406fb06, 0x2301fba4, 0xf1c34252, 0xbf384340, 0xfba61e5b, 
+    0x24004202, 0x2403fbe6, 0xea420bd2, 0xfba64644, 0xfba12306, 0xfba3e202, 0xfbe3e407, 0x42644261, 
+    0x4e40f1c2, 0xf1aebf38, 0xfba60e01, 0xf04f2304, 0xfbe60200, 0xfba2320e, 0x00344603, 0x6462fbe2, 
+    0xe606fba1, 0xe807fba4, 0x6861fbe4, 0xf1c84276, 0xbf385840, 0x0801f1a8, 0xe406fba2, 0xe508fba3, 
+    0x5468fbe2, 0xe605fba1, 0xe804fba7, 0x8664fbe1, 0x0520f118, 0x0600f156, 0xf1a809a8, 0x09b1081b, 
+    0x083ff008, 0x0f0af1b8, 0x6086ea40, 0xeb01d91c, 0xe8bd510c, 0xbf0081f0, 0xe8eef5fc, 0xd3d8dde2, 
+    0xc3c7cbcf, 0xb6b9bdc0, 0xacaeb1b4, 0xa3a5a7a9, 0x9b9d9fa1, 0x9596989a, 0x8f909293, 0x898b8c8d, 
+    0x85868788, 0x81828384, 0x6800fba0, 0xf201fb00, 0x0842eb08, 0x2887ebb8, 0x1834d507, 0x0401eb58, 
+    0x1c40d5d5, 0x0100f151, 0x1a34e7d1, 0x0401eb78, 0x1e40d4cd, 0x0100f171, 0xea5fe7c9, 0xea5f0c4c, 
+    0xd10d5c9c, 0xf04fd305, 0xf0010000, 0xe8bd4100, 0xe8bd81f0, 0xb57041f0, 0xfea8f7ff, 0xbeffdb6d, 
+    0x41f0e8bd, 0x0000f04f, 0x47704900, 0x7ff80000, 0xea91b510, 0xbf480f03, 0x4300f083, 0xab1cf53f, 
+    0xeb711a84, 0xd2070c03, 0xf08c1912, 0xeb434c00, 0x1b00030c, 0x010ceb61, 0xe1a4f8df, 0x5411ea4f, 
+    0x5c13eba4, 0x0f43ea1e, 0xea9ebf18, 0xf0005f44, 0xea2380b0, 0x4252036e, 0x5104ea21, 0x036eebc3, 
+    0x1e5bbf38, 0x0e20f1dc, 0xfa22d325, 0xeb10fe0c, 0xfa43000e, 0xeb41fe0c, 0xf1cc010e, 0xfa030e20, 
+    0xeb10fe0e, 0xf151000e, 0xf1cc0100, 0xd4290e20, 0xf20efa12, 0x5104eb01, 0x4010e8bd, 0x4770bf58, 
+    0xbf1c1c40, 0x4f00f1b2, 0x28004770, 0x1c49bf0c, 0x0001f020, 0xeb124770, 0xeb430e02, 0xbf180203, 
+    0x0e01f04f, 0x0242ea4e, 0x0c20f1ac, 0x0e1ef1dc, 0xfa43d954, 0xeb10fe0c, 0xf151000e, 0xf1cc31ff, 
+    0xd5d50e1e, 0x0e01f10e, 0xfe0efa12, 0xeb414140, 0xeb010101, 0xea5f5c44, 0xd9105c5c, 0x70deeb10, 
+    0x5104eb01, 0xf1bebf38, 0xe8bd4f00, 0xbf184010, 0x28004770, 0x1c49bf0c, 0x0001f020, 0xd2304770, 
+    0x2cd4ea4f, 0x1100f511, 0x6400f424, 0xfab1d01b, 0x3a0bf281, 0x1ea41aa4, 0x0320f1d2, 0xfa304091, 
+    0x4319f303, 0xeb014090, 0x2c0071cc, 0x5104eb01, 0x4010e8bd, 0x4770bfa8, 0x41c0f101, 0x0000f04f, 
+    0x4100f001, 0xfab04770, 0xfa10f380, 0xd100f103, 0x1ae4bd10, 0x05483c17, 0xe7e40ac9, 0x5104eb01, 
+    0x1049bd10, 0x5104eb01, 0x4010e8bd, 0x0030ea4f, 0xf04fe002, 0x47700100, 0xbf08004a, 0xd0f84200, 
+    0x1f00f5b2, 0x4770bf28, 0x4100f001, 0x0000f04f, 0xea9e4770, 0xd0075f44, 0x0f5eea11, 0x4010e8bd, 
+    0x2100bf04, 0x47702000, 0x4010e8bd, 0xf7ffb570, 0xbf00fdbd, 0x3ef6df40, 0x4100f083, 0x47704610, 
+    0xffe00000, 0xea4f0043, 0xea4f0cd3, 0x40430c3c, 0x0740bf1f, 0x5160f10c, 0x4ffef013, 0xf01c4770, 
+    0xd1036f00, 0xf00c2000, 0x47704100, 0x4300f00c, 0x7050ea43, 0xea40b510, 0xf00000cc, 0xbf00fa22, 
+    0x92000000, 0x0100ea4f, 0xbddef7ff, 0x4100f04f, 0x0000f04f, 0x2100f5a1, 0x00004770, 0x0f01ea90, 
+    0xf081bf48, 0xf1004100, 0x1a42825e, 0x1a80bf3c, 0xea4f1889, 0xf04f52d0, 0xea1c4c7f, 0xeba20f41, 
+    0xbf1853d1, 0x6f02ea9c, 0x803bf000, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 0xfc03fa21, 0x0c0ceb10, 
+    0xf102d21e, 0xea5f32ff, 0xeb40201c, 0xbf3850c2, 0xf01c4770, 0xea4f0f7f, 0xbf180c40, 0x4f7ff1bc, 
+    0x4770bf38, 0x0320f1c3, 0xbf084099, 0x0001f020, 0x4f7ff1bc, 0x4770bf38, 0x40c0f1a0, 0xba17f000, 
+    0x003cea4f, 0xeb400a00, 0xbf2850c2, 0x0ffff01c, 0x0c40ea4f, 0xbf18d0e6, 0x4f7ff1bc, 0x4770bf38, 
+    0xea9ce7ea, 0xd0056f02, 0x0f5cea10, 0xf000bf08, 0x47704000, 0xf000b510, 0xbf00f9b4, 0x3ebefb64, 
+    0xf0004801, 0xbf00ba6e, 0x7fc00000, 0x0c7ff44f, 0x12d0ea1c, 0xea1cbf1e, 0xea9213d1, 0xea930f0c, 
+    0xf0000f0c, 0xea908085, 0xbf480f01, 0x7280f442, 0x0c00f440, 0x0000f441, 0x417ff02c, 0x407ff020, 
+    0x4281b500, 0x0203eba2, 0x1c08f20f, 0x4e50ebac, 0x0000f1c0, 0xe000f89e, 0x0e4eea4f, 0xfc0efb00, 
+    0x0049bf38, 0x1c2cea4f, 0x02faf502, 0xf30efb0c, 0x1eceea4f, 0x2c11ea4f, 0x21c1ea4f, 0x5e63eb0e, 
+    0x4222eb42, 0xfc0cfb0e, 0x531cea4f, 0x1103fb00, 0x2c11ea4f, 0x3101ea4f, 0xfc0cfb0e, 0x4cdcea4f, 
+    0x110cfb00, 0xbf2842c1, 0xeb4c1809, 0xf85d3303, 0xeb10eb04, 0xeb430141, 0xf5b250c2, 0xbf380f7c, 
+    0xd5294770, 0x0ff0f012, 0xf100bf1c, 0xf00040c0, 0x47704000, 0x83828100, 0x87868584, 0x8c8b8988, 
+    0x918f8e8d, 0x96959392, 0x9c9a9997, 0xa2a09f9d, 0xa8a7a5a3, 0xb0aeacaa, 0xb7b5b3b2, 0xc0bebcb9, 
+    0xc9c7c5c2, 0xd4d1cecc, 0xdfdcd9d7, 0xece9e6e2, 0xfaf7f3f0, 0x000000fe, 0x0c40ea4f, 0x7c80f10c, 
+    0x4f7ef1bc, 0x4770bf28, 0x40c0f1b0, 0xb95ff000, 0x0f01ea90, 0x13d1ea0c, 0xf442bf48, 0x45627280, 
+    0x4563bf38, 0xf413d207, 0xd0160f7f, 0x0001ea80, 0x4000f000, 0xb5104770, 0xf903f000, 0x3efc7e09, 
+    0xb805f000, 0x0001ea80, 0x4000f000, 0xea804770, 0xf0000001, 0xf0004000, 0xf412b93a, 0xbf040f7f, 
+    0x47704802, 0x0001ea80, 0xb931f000, 0x7fc00000, 0x0e0b0041, 0x029ef1d3, 0xf450d908, 0xea4f0300, 
+    0xfa232303, 0xbf48f002, 0x47704240, 0xf000b510, 0xbf00f8d8, 0x80249249, 0x47702000, 0x4200f06f, 
+    0x0020ea82, 0x00004770, 0xf1d10dc1, 0xdb06029e, 0x2300ea4f, 0x4300f043, 0xf002fa23, 0x42004770, 
+    0xea4fd507, 0xf1b10140, 0xd2024ffe, 0x0000f04f, 0xb5104770, 0xf8b5f000, 0x80249249, 0x47702000, 
+    0x0020ea6f, 0x00004770, 0x4100f010, 0x4240bf48, 0xf380fab0, 0xf203fa10, 0x039df1c3, 0xea51d00b, 
+    0xeb0151c3, 0x06532012, 0x4770bf38, 0x0001f100, 0xf020bf08, 0x47700001, 0xf380fab0, 0xf203fa10, 
+    0x039df1c3, 0x05d9d00a, 0x2012eb01, 0xbf380653, 0xf1004770, 0xbf080001, 0x0001f020, 0x00004770, 
+    0x0c7ff44f, 0x12d0ea1c, 0xea1cbf1e, 0xea9213d1, 0xea930f0c, 0xf0000f0c, 0xea908047, 0xbf480f01, 
+    0x7280f442, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 0x0203eb02, 0x1301fba0, 0x0200f5a2, 0xbf182900, 
+    0x0301f043, 0xbf28005b, 0x0333ea4f, 0x4222eb42, 0x2c13ea5f, 0x50c2eb4c, 0xebbcbf2e, 0xf5b26f43, 
+    0x47700f7c, 0x6c03ea4f, 0x4f00f1bc, 0xf020bf08, 0xf5b20001, 0xbf380f7c, 0xd50b4770, 0x02fff082, 
+    0x3f80f512, 0x4770bfc8, 0x40c0f100, 0xf000bfd8, 0x47704000, 0x0c00f500, 0x0c4cea5f, 0x4770bf48, 
+    0x40c0f1b0, 0xb873f000, 0x0f01ea90, 0x13d1ea0c, 0xf442bf48, 0x45627280, 0x4563bf38, 0xea80d204, 
+    0xf0000001, 0x47704000, 0xf000b510, 0xbf00f81a, 0x3e010089, 0xb807f000, 0xb809f000, 0x0c41ea5f, 
+    0x6c1cea5f, 0xea80d008, 0xf0000001, 0xea5fb850, 0xea5f0c40, 0xd1f66c1c, 0x4000f04f, 0x0080f5a0, 
+    0xf10e4770, 0xf02e0e02, 0xf85e0e03, 0x42244b04, 0xea4fd404, 0xf1b20241, 0xd8114f7f, 0x0340ea4f, 
+    0x4f7ff1b3, 0xd10ed80c, 0x7cd0ea4f, 0x4f7ff1b2, 0x0c4ceb0c, 0x0c02f10c, 0xeb4cbf08, 0xe0047cd1, 
+    0x0c08f04f, 0xea4fe001, 0xeb0c7cd1, 0xfa24034c, 0xf004f403, 0xf1b40407, 0xd2060c04, 0x0c84eb0e, 
+    0x4010e8bd, 0x0c01f04c, 0xe8df4760, 0x0807f00c, 0xf04f0202, 0xf5a04000, 0xbd100080, 0x00424608, 
+    0xf1d2bf18, 0xbf887280, 0x4000f000, 0x21ffbd10, 0x50d0ea41, 0x477005c0, 0x0f01ea90, 0xf081bf48, 
+    0xf53f4100, 0x1a42ada2, 0xf082d804, 0xeba04200, 0x44110002, 0x52d0ea4f, 0x4c7ff04f, 0x0f41ea1c, 
+    0x53d1eba2, 0xea9cbf18, 0xd04a6f02, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 0xfc03fa21, 0x0c0cebb0, 
+    0xf012d40f, 0xd0360ffe, 0x004cea5f, 0x1200d51d, 0x50c2eb40, 0x4770bf38, 0x0f3ff01c, 0x4770bf18, 
+    0xf1a2e00b, 0xea5f0201, 0xeb40201c, 0xbf3850c2, 0xf01c4770, 0xbf180f7f, 0xf1c34770, 0x40990320, 
+    0x1e40bf14, 0x0001f020, 0x08804770, 0x2312ea4f, 0x4770bf08, 0xfc80fab0, 0x020ceba2, 0x0c28f1cc, 
+    0xf00cfa60, 0x2f12ea93, 0xeb00bf04, 0x477050c2, 0x70c3ea4f, 0x0a134770, 0x10dcea5f, 0x4770bf08, 
+    0xea9ce7f6, 0xd0046f02, 0x0f5cea10, 0x2000bf08, 0xb5104770, 0xff45f7ff, 0x3ef6df40, 0x4000f081, 
+    0xf00c4770, 0x2b09030f, 0x2008bf08, 0x807ff000, 0xd00b2b0a, 0xbf182b08, 0xbf084770, 0x0f40f01c, 
+    0xf04fd00a, 0xf04f0000, 0x47700100, 0x0f40f01c, 0xf04fbf18, 0x47704000, 0x0f10f01c, 0xf020d008, 
+    0xf0004370, 0xea42427f, 0xea4f01d3, 0x47707043, 0x4060f000, 0x427ff021, 0x0200ea42, 0x407ff001, 
+    0x7072ea40, 0xf04f4770, 0xf44c0cff, 0xea1c6ce0, 0xbf1c5311, 0x0c03ea9c, 0xbfc24594, 0xeb0142da, 
+    0x47705102, 0xd00d2b00, 0x0f00f1bc, 0x2a00d00f, 0x4100f001, 0xf041bfa4, 0xf04141e0, 0xf04f617f, 
+    0x47700000, 0x4100f001, 0x0000f04f, 0xea504770, 0xf04f3301, 0xbf180c9b, 0x6c80f04c, 0xaf7cf47e, 
+    0xf04f4770, 0xea1202ff, 0xbf1c52d0, 0x03fff092, 0xbfc2428b, 0xeb0042d1, 0x477050c1, 0xd00a2a00, 
+    0xd00b2b00, 0xf0002900, 0xbfa44000, 0x40fef040, 0x0000f440, 0xf0004770, 0x47704000, 0xf04f0243, 
+    0xbf180c0b, 0x6c80f04c, 0xad0af47f, 0xf41c4770, 0xd0111f80, 0x2fe0f41c, 0xea6fd003, 0x004931cc, 
+    0xf04f4770, 0xf3ef5040, 0xf0228200, 0xea424270, 0xf3820200, 0x47708800, 0x0000f04f, 0xfb904770, 
+    0xfb02f2f1, 0x46100111, 0xfbb04770, 0xfb02f2f1, 0x46100111, 0x02004770, 0x03010604, 0x00160011, 
+    0x0020001b, 0x002a0025, 0x0034002f, 0x003c0039, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 
+    0x00380040, 0xfff80014, 0xfff8fff4, 0xfff8fff4, 0xfff8fff4, 0xfff8fff4, 0xfff8fff4, 0xfff8fff4, 
+    0x0000fff4, 0xf2035190, 0xf2035192, 0xf2035194, 0xf2035196, 0x00030008, 0x00030003, 0x00040004, 
+    0x00000008, 0x00100034, 0x00100010, 0x001f001f, 0x00000034, 0x00080020, 0x00080008, 0x00100010, 
+    0x00000020, 0x00010004, 0x00030001, 0x00040003, 0x00000004, 0x0006001c, 0x00080006, 0x0014000b, 
+    0x0000001c, 0x00040010, 0x00060004, 0x000c0008, 0x00000010, 0x0000ffff, 0x00000000, 0x0000ffff, 
+    0x00000000, 0x0000ffff, 0x00000000, 0xf2033070, 0xf2033270, 0xf2033470, 0xf2033670, 0x3f83da51, 
+    0x3f71b08a, 0x3f6edfa4, 0x3f80068e, 0x3f6e147b, 0x424ae148, 0x42617ae1, 0x42bfae14, 0x3f7c9eed, 
+    0x3f6765fe, 0x3f655326, 0x3f7487fd, 0xc400a7ae, 0xc3b79852, 0xc3c0f1ec, 0xc3c69852, 0x3f7e9100, 
+    0x3f7c01a3, 0x3f7ecbfb, 0x3f7eecc0, 0xc269cccd, 0xc155999a, 0xc21151ec, 0xc1633333, 0x3f75c91d, 
+    0x3f785f07, 0x3f7fb15b, 0x3f806f69, 0xc2a06b85, 0xc29cb333, 0x43180f5c, 0x4095c28f, 0x00000000, 
+    0x00000000, 0x3ff00000, 0x00000000, 0x3ff80000, 0x00000000, 0x00000000, 0x40000000, 0x3fe2b803, 
+    0x00000000, 0x00000000, 0x43cfd006, 0x3e4cfdeb, 0x33333303, 0x3fe33333, 0xdb6fabff, 0x3fdb6db6, 
+    0x518f264d, 0x3fd55555, 0xa91d4101, 0x3fd17460, 0x93c9db65, 0x3fcd864a, 0x4a454eef, 0x3fca7e28, 
+    0x5555553e, 0x3fc55555, 0x16bebd93, 0xbf66c16c, 0xaf25de2c, 0x3f11566a, 0xc5d26bf1, 0xbebbbd41, 
+    0x72bea4d0, 0x3e663769, 0x00000000, 0x00000000, 0xc0c10000, 0x0140c181, 0x03c0c301, 0xc2410280, 
+    0x06c0c601, 0xc7410780, 0xc5c10500, 0x0440c481, 0x0cc0cc01, 0xcd410d80, 0xcfc10f00, 0x0e40ce81, 
+    0xcac10a00, 0x0b40cb81, 0x09c0c901, 0xc8410880, 0x18c0d801, 0xd9411980, 0xdbc11b00, 0x1a40da81, 
+    0xdec11e00, 0x1f40df81, 0x1dc0dd01, 0xdc411c80, 0xd4c11400, 0x1540d581, 0x17c0d701, 0xd6411680, 
+    0x12c0d201, 0xd3411380, 0xd1c11100, 0x1040d081, 0x30c0f001, 0xf1413180, 0xf3c13300, 0x3240f281, 
+    0xf6c13600, 0x3740f781, 0x35c0f501, 0xf4413480, 0xfcc13c00, 0x3d40fd81, 0x3fc0ff01, 0xfe413e80, 
+    0x3ac0fa01, 0xfb413b80, 0xf9c13900, 0x3840f881, 0xe8c12800, 0x2940e981, 0x2bc0eb01, 0xea412a80, 
+    0x2ec0ee01, 0xef412f80, 0xedc12d00, 0x2c40ec81, 0x24c0e401, 0xe5412580, 0xe7c12700, 0x2640e681, 
+    0xe2c12200, 0x2340e381, 0x21c0e101, 0xe0412080, 0x60c0a001, 0xa1416180, 0xa3c16300, 0x6240a281, 
+    0xa6c16600, 0x6740a781, 0x65c0a501, 0xa4416480, 0xacc16c00, 0x6d40ad81, 0x6fc0af01, 0xae416e80, 
+    0x6ac0aa01, 0xab416b80, 0xa9c16900, 0x6840a881, 0xb8c17800, 0x7940b981, 0x7bc0bb01, 0xba417a80, 
+    0x7ec0be01, 0xbf417f80, 0xbdc17d00, 0x7c40bc81, 0x74c0b401, 0xb5417580, 0xb7c17700, 0x7640b681, 
+    0xb2c17200, 0x7340b381, 0x71c0b101, 0xb0417080, 0x90c15000, 0x51409181, 0x53c09301, 0x92415280, 
+    0x56c09601, 0x97415780, 0x95c15500, 0x54409481, 0x5cc09c01, 0x9d415d80, 0x9fc15f00, 0x5e409e81, 
+    0x9ac15a00, 0x5b409b81, 0x59c09901, 0x98415880, 0x48c08801, 0x89414980, 0x8bc14b00, 0x4a408a81, 
+    0x8ec14e00, 0x4f408f81, 0x4dc08d01, 0x8c414c80, 0x84c14400, 0x45408581, 0x47c08701, 0x86414680, 
+    0x42c08201, 0x83414380, 0x81c14100, 0x40408081, 0x0002fe00, 0x00040000, 0x00003308, 0x000005ec, 
+    0x00031dc8, 0x00057f70, 0x00000018, 0x00000648, 0x00031de0, 0x00057ff0, 0x00000010, 0x00000648, 
+    0x00031dc8, 0x00043308, 0x0000b90c, 0x00000664, 0x00031dc8, 0x0004ec14, 0x00000060, 0x00000664, 
+    0x00031dc8, 0x00057800, 0x00000490, 0x00000664, 0x00007fff, 0xf3747f62, 0xe7077d8a, 0xdad87a7d, 
+    0xcf047642, 0xc3a970e3, 0xb8e36a6e, 0xaecc62f2, 0xa57e5a82, 0x9d0e5134, 0x9592471d, 0x8f1d3c57, 
+    0x89be30fc, 0x85832528, 0x827618f9, 0x809e0c8c, 0x80000000, 0x809ef374, 0x8276e707, 0x8583dad8, 
+    0x89becf04, 0x8f1dc3a9, 0x9592b8e3, 0x9d0eaecc, 0xa57ea57e, 0xaecc9d0e, 0xb8e39592, 0xc3a98f1d, 
+    0xcf0489be, 0xdad88583, 0xe7078276, 0xf374809e, 0x00008000, 0x0c8c809e, 0x18f98276, 0x25288583, 
+    0x30fc89be, 0x3c578f1d, 0x471d9592, 0x51349d0e, 0x5a82a57e, 0x62f2aecc, 0x6a6eb8e3, 0x70e3c3a9, 
+    0x7642cf04, 0x7a7ddad8, 0x7d8ae707, 0x7f62f374, 0x7fff0000, 0x7f620c8c, 0x7d8a18f9, 0x7a7d2528, 
+    0x764230fc, 0x70e33c57, 0x6a6e471d, 0x62f25134, 0x5a825a82, 0x513462f2, 0x471d6a6e, 0x3c5770e3, 
+    0x30fc7642, 0x25287a7d, 0x18f97d8a, 0x0c8c7f62, 0x00007fff, 0xf9b87fd9, 0xf3747f62, 0xed387e9d, 
+    0xe7077d8a, 0xe0e67c2a, 0xdad87a7d, 0xd4e17885, 0xcf047642, 0xc94673b6, 0xc3a970e3, 0xbe326dca, 
+    0xb8e36a6e, 0xb3c066d0, 0xaecc62f2, 0xaa0a5ed7, 0xa57e5a82, 0xa12955f6, 0x9d0e5134, 0x99304c40, 
+    0x9592471d, 0x923641ce, 0x8f1d3c57, 0x8c4a36ba, 0x89be30fc, 0x877b2b1f, 0x85832528, 0x83d61f1a, 
+    0x827618f9, 0x816312c8, 0x809e0c8c, 0x80270648, 0x80000000, 0x8027f9b8, 0x809ef374, 0x8163ed38, 
+    0x8276e707, 0x83d6e0e6, 0x8583dad8, 0x877bd4e1, 0x89becf04, 0x8c4ac946, 0x8f1dc3a9, 0x9236be32, 
+    0x9592b8e3, 0x9930b3c0, 0x9d0eaecc, 0xa129aa0a, 0xa57ea57e, 0xaa0aa129, 0xaecc9d0e, 0xb3c09930, 
+    0xb8e39592, 0xbe329236, 0xc3a98f1d, 0xc9468c4a, 0xcf0489be, 0xd4e1877b, 0xdad88583, 0xe0e683d6, 
+    0xe7078276, 0xed388163, 0xf374809e, 0xf9b88027, 0x00008000, 0x06488027, 0x0c8c809e, 0x12c88163, 
+    0x18f98276, 0x1f1a83d6, 0x25288583, 0x2b1f877b, 0x30fc89be, 0x36ba8c4a, 0x3c578f1d, 0x41ce9236, 
+    0x471d9592, 0x4c409930, 0x51349d0e, 0x55f6a129, 0x5a82a57e, 0x5ed7aa0a, 0x62f2aecc, 0x66d0b3c0, 
+    0x6a6eb8e3, 0x6dcabe32, 0x70e3c3a9, 0x73b6c946, 0x7642cf04, 0x7885d4e1, 0x7a7ddad8, 0x7c2ae0e6, 
+    0x7d8ae707, 0x7e9ded38, 0x7f62f374, 0x7fd9f9b8, 0x7fff0000, 0x7fd90648, 0x7f620c8c, 0x7e9d12c8, 
+    0x7d8a18f9, 0x7c2a1f1a, 0x7a7d2528, 0x78852b1f, 0x764230fc, 0x73b636ba, 0x70e33c57, 0x6dca41ce, 
+    0x6a6e471d, 0x66d04c40, 0x62f25134, 0x5ed755f6, 0x5a825a82, 0x55f65ed7, 0x513462f2, 0x4c4066d0, 
+    0x471d6a6e, 0x41ce6dca, 0x3c5770e3, 0x36ba73b6, 0x30fc7642, 0x2b1f7885, 0x25287a7d, 0x1f1a7c2a, 
+    0x18f97d8a, 0x12c87e9d, 0x0c8c7f62, 0x06487fd9, 0x00007fff, 0xfcdc7ff6, 0xf9b87fd9, 0xf6957fa7, 
+    0xf3747f62, 0xf0557f0a, 0xed387e9d, 0xea1e7e1e, 0xe7077d8a, 0xe3f47ce4, 0xe0e67c2a, 0xdddc7b5d, 
+    0xdad87a7d, 0xd7d9798a, 0xd4e17885, 0xd1ef776c, 0xcf047642, 0xcc217505, 0xc94673b6, 0xc6737255, 
+    0xc3a970e3, 0xc0e96f5f, 0xbe326dca, 0xbb856c24, 0xb8e36a6e, 0xb64c68a7, 0xb3c066d0, 0xb14064e9, 
+    0xaecc62f2, 0xac6560ec, 0xaa0a5ed7, 0xa7bd5cb4, 0xa57e5a82, 0xa34c5843, 0xa12955f6, 0x9f14539b, 
+    0x9d0e5134, 0x9b174ec0, 0x99304c40, 0x975949b4, 0x9592471d, 0x93dc447b, 0x923641ce, 0x90a13f17, 
+    0x8f1d3c57, 0x8dab398d, 0x8c4a36ba, 0x8afb33df, 0x89be30fc, 0x88942e11, 0x877b2b1f, 0x86762827, 
+    0x85832528, 0x84a32224, 0x83d61f1a, 0x831c1c0c, 0x827618f9, 0x81e215e2, 0x816312c8, 0x80f60fab, 
+    0x809e0c8c, 0x8059096b, 0x80270648, 0x800a0324, 0x80000000, 0x800afcdc, 0x8027f9b8, 0x8059f695, 
+    0x809ef374, 0x80f6f055, 0x8163ed38, 0x81e2ea1e, 0x8276e707, 0x831ce3f4, 0x83d6e0e6, 0x84a3dddc, 
+    0x8583dad8, 0x8676d7d9, 0x877bd4e1, 0x8894d1ef, 0x89becf04, 0x8afbcc21, 0x8c4ac946, 0x8dabc673, 
+    0x8f1dc3a9, 0x90a1c0e9, 0x9236be32, 0x93dcbb85, 0x9592b8e3, 0x9759b64c, 0x9930b3c0, 0x9b17b140, 
+    0x9d0eaecc, 0x9f14ac65, 0xa129aa0a, 0xa34ca7bd, 0xa57ea57e, 0xa7bda34c, 0xaa0aa129, 0xac659f14, 
+    0xaecc9d0e, 0xb1409b17, 0xb3c09930, 0xb64c9759, 0xb8e39592, 0xbb8593dc, 0xbe329236, 0xc0e990a1, 
+    0xc3a98f1d, 0xc6738dab, 0xc9468c4a, 0xcc218afb, 0xcf0489be, 0xd1ef8894, 0xd4e1877b, 0xd7d98676, 
+    0xdad88583, 0xdddc84a3, 0xe0e683d6, 0xe3f4831c, 0xe7078276, 0xea1e81e2, 0xed388163, 0xf05580f6, 
+    0xf374809e, 0xf6958059, 0xf9b88027, 0xfcdc800a, 0x00008000, 0x0324800a, 0x06488027, 0x096b8059, 
+    0x0c8c809e, 0x0fab80f6, 0x12c88163, 0x15e281e2, 0x18f98276, 0x1c0c831c, 0x1f1a83d6, 0x222484a3, 
+    0x25288583, 0x28278676, 0x2b1f877b, 0x2e118894, 0x30fc89be, 0x33df8afb, 0x36ba8c4a, 0x398d8dab, 
+    0x3c578f1d, 0x3f1790a1, 0x41ce9236, 0x447b93dc, 0x471d9592, 0x49b49759, 0x4c409930, 0x4ec09b17, 
+    0x51349d0e, 0x539b9f14, 0x55f6a129, 0x5843a34c, 0x5a82a57e, 0x5cb4a7bd, 0x5ed7aa0a, 0x60ecac65, 
+    0x62f2aecc, 0x64e9b140, 0x66d0b3c0, 0x68a7b64c, 0x6a6eb8e3, 0x6c24bb85, 0x6dcabe32, 0x6f5fc0e9, 
+    0x70e3c3a9, 0x7255c673, 0x73b6c946, 0x7505cc21, 0x7642cf04, 0x776cd1ef, 0x7885d4e1, 0x798ad7d9, 
+    0x7a7ddad8, 0x7b5ddddc, 0x7c2ae0e6, 0x7ce4e3f4, 0x7d8ae707, 0x7e1eea1e, 0x7e9ded38, 0x7f0af055, 
+    0x7f62f374, 0x7fa7f695, 0x7fd9f9b8, 0x7ff6fcdc, 0x7fff0000, 0x7ff60324, 0x7fd90648, 0x7fa7096b, 
+    0x7f620c8c, 0x7f0a0fab, 0x7e9d12c8, 0x7e1e15e2, 0x7d8a18f9, 0x7ce41c0c, 0x7c2a1f1a, 0x7b5d2224, 
+    0x7a7d2528, 0x798a2827, 0x78852b1f, 0x776c2e11, 0x764230fc, 0x750533df, 0x73b636ba, 0x7255398d, 
+    0x70e33c57, 0x6f5f3f17, 0x6dca41ce, 0x6c24447b, 0x6a6e471d, 0x68a749b4, 0x66d04c40, 0x64e94ec0, 
+    0x62f25134, 0x60ec539b, 0x5ed755f6, 0x5cb45843, 0x5a825a82, 0x58435cb4, 0x55f65ed7, 0x539b60ec, 
+    0x513462f2, 0x4ec064e9, 0x4c4066d0, 0x49b468a7, 0x471d6a6e, 0x447b6c24, 0x41ce6dca, 0x3f176f5f, 
+    0x3c5770e3, 0x398d7255, 0x36ba73b6, 0x33df7505, 0x30fc7642, 0x2e11776c, 0x2b1f7885, 0x2827798a, 
+    0x25287a7d, 0x22247b5d, 0x1f1a7c2a, 0x1c0c7ce4, 0x18f97d8a, 0x15e27e1e, 0x12c87e9d, 0x0fab7f0a, 
+    0x0c8c7f62, 0x096b7fa7, 0x06487fd9, 0x03247ff6, 0x00007fff, 0xfe6e7ffe, 0xfcdc7ff6, 0xfb4a7fea, 
+    0xf9b87fd9, 0xf8277fc2, 0xf6957fa7, 0xf5057f87, 0xf3747f62, 0xf1e47f38, 0xf0557f0a, 0xeec67ed6, 
+    0xed387e9d, 0xebab7e60, 0xea1e7e1e, 0xe8927dd6, 0xe7077d8a, 0xe57d7d3a, 0xe3f47ce4, 0xe26d7c89, 
+    0xe0e67c2a, 0xdf617bc6, 0xdddc7b5d, 0xdc597aef, 0xdad87a7d, 0xd9587a06, 0xd7d9798a, 0xd65c790a, 
+    0xd4e17885, 0xd36777fb, 0xd1ef776c, 0xd07976d9, 0xcf047642, 0xcd9275a6, 0xcc217505, 0xcab27460, 
+    0xc94673b6, 0xc7db7308, 0xc6737255, 0xc50d719e, 0xc3a970e3, 0xc2487023, 0xc0e96f5f, 0xbf8c6e97, 
+    0xbe326dca, 0xbcda6cf9, 0xbb856c24, 0xba336b4b, 0xb8e36a6e, 0xb796698c, 0xb64c68a7, 0xb50567bd, 
+    0xb3c066d0, 0xb27f65de, 0xb14064e9, 0xb00563ef, 0xaecc62f2, 0xad9761f1, 0xac6560ec, 0xab365fe4, 
+    0xaa0a5ed7, 0xa8e25dc8, 0xa7bd5cb4, 0xa69c5b9d, 0xa57e5a82, 0xa4635964, 0xa34c5843, 0xa238571e, 
+    0xa12955f6, 0xa01c54ca, 0x9f14539b, 0x9e0f5269, 0x9d0e5134, 0x9c114ffb, 0x9b174ec0, 0x9a224d81, 
+    0x99304c40, 0x98434afb, 0x975949b4, 0x9674486a, 0x9592471d, 0x94b545cd, 0x93dc447b, 0x93074326, 
+    0x923641ce, 0x91694074, 0x90a13f17, 0x8fdd3db8, 0x8f1d3c57, 0x8e623af3, 0x8dab398d, 0x8cf83825, 
+    0x8c4a36ba, 0x8ba0354e, 0x8afb33df, 0x8a5a326e, 0x89be30fc, 0x89272f87, 0x88942e11, 0x88052c99, 
+    0x877b2b1f, 0x86f629a4, 0x86762827, 0x85fa26a8, 0x85832528, 0x851123a7, 0x84a32224, 0x843a209f, 
+    0x83d61f1a, 0x83771d93, 0x831c1c0c, 0x82c61a83, 0x827618f9, 0x822a176e, 0x81e215e2, 0x81a01455, 
+    0x816312c8, 0x812a113a, 0x80f60fab, 0x80c80e1c, 0x809e0c8c, 0x80790afb, 0x8059096b, 0x803e07d9, 
+    0x80270648, 0x801604b6, 0x800a0324, 0x80020192, 0x80000000, 0x8002fe6e, 0x800afcdc, 0x8016fb4a, 
+    0x8027f9b8, 0x803ef827, 0x8059f695, 0x8079f505, 0x809ef374, 0x80c8f1e4, 0x80f6f055, 0x812aeec6, 
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+    0x83d6e0e6, 0x843adf61, 0x84a3dddc, 0x8511dc59, 0x8583dad8, 0x85fad958, 0x8676d7d9, 0x86f6d65c, 
+    0x877bd4e1, 0x8805d367, 0x8894d1ef, 0x8927d079, 0x89becf04, 0x8a5acd92, 0x8afbcc21, 0x8ba0cab2, 
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+    0x9236be32, 0x9307bcda, 0x93dcbb85, 0x94b5ba33, 0x9592b8e3, 0x9674b796, 0x9759b64c, 0x9843b505, 
+    0x9930b3c0, 0x9a22b27f, 0x9b17b140, 0x9c11b005, 0x9d0eaecc, 0x9e0fad97, 0x9f14ac65, 0xa01cab36, 
+    0xa129aa0a, 0xa238a8e2, 0xa34ca7bd, 0xa463a69c, 0xa57ea57e, 0xa69ca463, 0xa7bda34c, 0xa8e2a238, 
+    0xaa0aa129, 0xab36a01c, 0xac659f14, 0xad979e0f, 0xaecc9d0e, 0xb0059c11, 0xb1409b17, 0xb27f9a22, 
+    0xb3c09930, 0xb5059843, 0xb64c9759, 0xb7969674, 0xb8e39592, 0xba3394b5, 0xbb8593dc, 0xbcda9307, 
+    0xbe329236, 0xbf8c9169, 0xc0e990a1, 0xc2488fdd, 0xc3a98f1d, 0xc50d8e62, 0xc6738dab, 0xc7db8cf8, 
+    0xc9468c4a, 0xcab28ba0, 0xcc218afb, 0xcd928a5a, 0xcf0489be, 0xd0798927, 0xd1ef8894, 0xd3678805, 
+    0xd4e1877b, 0xd65c86f6, 0xd7d98676, 0xd95885fa, 0xdad88583, 0xdc598511, 0xdddc84a3, 0xdf61843a, 
+    0xe0e683d6, 0xe26d8377, 0xe3f4831c, 0xe57d82c6, 0xe7078276, 0xe892822a, 0xea1e81e2, 0xebab81a0, 
+    0xed388163, 0xeec6812a, 0xf05580f6, 0xf1e480c8, 0xf374809e, 0xf5058079, 0xf6958059, 0xf827803e, 
+    0xf9b88027, 0xfb4a8016, 0xfcdc800a, 0xfe6e8002, 0x00008000, 0x01928002, 0x0324800a, 0x04b68016, 
+    0x06488027, 0x07d9803e, 0x096b8059, 0x0afb8079, 0x0c8c809e, 0x0e1c80c8, 0x0fab80f6, 0x113a812a, 
+    0x12c88163, 0x145581a0, 0x15e281e2, 0x176e822a, 0x18f98276, 0x1a8382c6, 0x1c0c831c, 0x1d938377, 
+    0x1f1a83d6, 0x209f843a, 0x222484a3, 0x23a78511, 0x25288583, 0x26a885fa, 0x28278676, 0x29a486f6, 
+    0x2b1f877b, 0x2c998805, 0x2e118894, 0x2f878927, 0x30fc89be, 0x326e8a5a, 0x33df8afb, 0x354e8ba0, 
+    0x36ba8c4a, 0x38258cf8, 0x398d8dab, 0x3af38e62, 0x3c578f1d, 0x3db88fdd, 0x3f1790a1, 0x40749169, 
+    0x41ce9236, 0x43269307, 0x447b93dc, 0x45cd94b5, 0x471d9592, 0x486a9674, 0x49b49759, 0x4afb9843, 
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+    0x7885d4e1, 0x790ad65c, 0x798ad7d9, 0x7a06d958, 0x7a7ddad8, 0x7aefdc59, 0x7b5ddddc, 0x7bc6df61, 
+    0x7c2ae0e6, 0x7c89e26d, 0x7ce4e3f4, 0x7d3ae57d, 0x7d8ae707, 0x7dd6e892, 0x7e1eea1e, 0x7e60ebab, 
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+    0x7fd9f9b8, 0x7feafb4a, 0x7ff6fcdc, 0x7ffefe6e, 0x7fff0000, 0x7ffe0192, 0x7ff60324, 0x7fea04b6, 
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+    0x66d04c40, 0x65de4d81, 0x64e94ec0, 0x63ef4ffb, 0x62f25134, 0x61f15269, 0x60ec539b, 0x5fe454ca, 
+    0x5ed755f6, 0x5dc8571e, 0x5cb45843, 0x5b9d5964, 0x5a825a82, 0x59645b9d, 0x58435cb4, 0x571e5dc8, 
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+    0x06487fd9, 0x04b67fea, 0x03247ff6, 0x01927ffe, 0x50102000, 0x68284808, 0x64244404, 0x74345414, 
+    0x62224202, 0x72325212, 0x6a2a4a0a, 0x7a3a5a1a, 0x61214101, 0x71315111, 0x69294909, 0x79395919, 
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+    0x31112101, 0x39192909, 0x35152505, 0x3d1d2d0d, 0x14040800, 0x1a0a1202, 0x19091101, 0x1d0d1505, 
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+    0x19881319, 0x04fd1a04, 0x1b142b23, 0x19401573, 0x16092304, 0x1a04311a, 0x851a045d, 0x19cf2304, 
+    0x3c1a798b, 0x70329f1b, 0xd91a0419, 0x04fd1a04, 0x8c33191b, 0xfd1a0419, 0x10751a64, 0x1a34b31a, 
+    0xd31a04c3, 0x17d51b04, 0x1bcc1954, 0x19543513, 0x04431a04, 0x1a04551a, 0x791a0467, 0x04971a04, 
+    0x1a04b51a, 0xa0a904d3, 0xff1a04a9, 0x3629231c, 0x1a04531a, 0xcd1a04bb, 0x04eb1a04, 0x74370f1b, 
+    0x3f1a0819, 0x04211a08, 0xed233069, 0x1ce1231b, 0x1a040b1a, 0x1609043d, 0x04120958, 0x1a306f1a, 
+    0xc11a049f, 0x216f2304, 0x1a04511a, 0x31235085, 0x1ead231d, 0x2904cb1a, 0x1f232328, 0x1a20e723, 
+    0x0b1a04f9, 0x042d1a24, 0x1128411a, 0x1a058023, 0xd01a04c0, 0x04f01a04, 0x82103231, 0x1affb201, 
+    0x5a710104, 0x12010101, 0x8101ff3a, 0x35032199, 0x7c8a0301, 0x9a2b7141, 0xa93c0199, 0x0301333f, 
+    0x4b3fd310, 0x2380fd07, 0xe21a0a88, 0xa90829cd, 0x1a082918, 0x831aa4fc, 0x20e31a18, 0x29088e1a, 
+    0x18061ad8, 0x1a18fe1a, 0xf81a0808, 0x187e1a08, 0x1a20e41a, 0x08320894, 0x1918051a, 0x1a203903, 
+    0x791a08f4, 0x20e51a18, 0x32089a1a, 0x18041a0c, 0x1a18fb1a, 0xf01a0809, 0x20745a08, 0x1908a01a, 
+    0x031a1107, 0x20fa5a18, 0x1a08ed1a, 0xe61a186f, 0x08a61a19, 0x025a1432, 0x080a1a78, 0x1a08e91a, 
+    0xe71a186a, 0x08ac1a20, 0x1a20185a, 0x0b1a18f7, 0x08e51a08, 0x1a18651a, 0xb21a20e8, 0x1a1c3208, 
+    0xf55a1801, 0x08e11a20, 0x1a20605a, 0x204208b8, 0x0c1ab859, 0x08dd1a08, 0x1a185b1a, 0xbe1a20e9, 
+    0x5e243208, 0xfffffcff, 0xd91a20f2, 0x18561a08, 0x1a20ea1a, 0x285a08c4, 0x18f11a20, 0x1a200d1a, 
+    0x515a08d6, 0x08ca1a20, 0xfe1a2c32, 0x18ef1a20, 0x1a200e1a, 0x4c1a08d2, 0x20eb1a18, 0x2a08d01a, 
+    0x20197f30, 0x1a20ee5a, 0x475a08ce, 0x08d61a20, 0xfc1a3432, 0x18ec1a20, 0x1a200f1a, 0x411a08ca, 
+    0x20ec1a18, 0x5a08dc1a, 0xeb5a2038, 0x08c61a20, 0x1a203c5a, 0x3c3208e2, 0x1a20fb1a, 0x101a18e9, 
+    0x08c21a20, 0x1a18371a, 0xe81a20ed, 0x1a403208, 0xe71a20fa, 0x20111a18, 0x1a08bf1a, 0xee1a1832, 
+    0x08ee1a20, 0xf91a4432, 0x20e65a20, 0x5a08bb1a, 0xf41a202d, 0x20485a08, 0x1a18e41a, 0xb71a2012, 
+    0x18281a08, 0x1a20ef1a, 0x4c3208fa, 0x1a20f81a, 0x131a18e3, 0x08b31a20, 0x1a20235a, 0x503208ff, 
+    0x1a20f71a, 0x141a18e1, 0x08b01a20, 0x23201e5a, 0x545a0b05, 0x20e05a20, 0x1a08ac1a, 0xf01a2018, 
+    0x200b1a20, 0xf61a5832, 0x18de1a20, 0x2a20151a, 0x205968a8, 0x3220111a, 0x20f51a5d, 0x1a18dc1a, 
+    0xa41a2016, 0x200e1a08, 0x1a20f11a, 0x615a2017, 0x20db5a20, 0x5a08a11a, 0x1d1a2009, 0x1a653220, 
+    0xd91a20f4, 0x20171a18, 0x5a089d1a, 0x231a2004, 0x1a693220, 0xd82a20f3, 0x1a201998, 0xfe230899, 
+    0x20f21a09, 0x5a20291a, 0xd61a206d, 0x20191a18, 0x5a08961a, 0x2f1a20f9, 0x1a713220, 0xd45a20f2, 
+    0x08921a20, 0x1a20f45a, 0x76322035, 0x1a20f11a, 0x1a1a18d3, 0x088e1a20, 0x1a20ef1a, 0x3a1a20f3, 
+    0x207a5a20, 0x1a18d11a, 0x8b1a201b, 0x20ea5a08, 0x3220401a, 0x20f01a7e, 0x1a18d01a, 0x871a201c, 
+    0x20e45a08, 0x5a20461a, 0xce5a2082, 0x08831a20, 0x1a20df1a, 0x4c1a20f4, 0x1a863220, 0xcc1a20ef, 
+    0x201d1a18, 0x5a08801a, 0x521a20da, 0x1a8b3220, 0xcb1a20ee, 0x201e1a18, 0x5a087c1a, 0x581a20d5, 
+    0x208f5a20, 0x1a18c91a, 0x781a201f, 0x20cf5a08, 0x32205d1a, 0x20ed1a93, 0x1a20c85a, 0xca5a0875, 
+    0x20631a20, 0x1a20975a, 0x201a18c6, 0x08711a20, 0x1a20c51a, 0x691a20f5, 0x1a9c3220, 0xc41a20ec, 
+    0x20211a18, 0x5a086e1a, 0x6f1a20bf, 0x1aa03220, 0xc31a20eb, 0x20221a18, 0x5a086a1a, 0x751a20ba, 
+    0x20a45a20, 0x1a18c11a, 0x661a2023, 0x20b55a08, 0x32207b1a, 0x20ea1aa9, 0x1a18bf1a, 0x631a2024, 
+    0x20b05a08, 0x5a20801a, 0xbe5a20ad, 0x085f1a20, 0x1a20aa5a, 0xb1322086, 0x1a20e91a, 0x251a18bc, 
+    0x085c1a20, 0x1a20a55a, 0xb65a208c, 0x18bb1a20, 0x1a20261a, 0xa05a0858, 0x20921a20, 0xe81aba32, 
+    0x18b91a20, 0x1a20271a, 0x9a5a0855, 0x20971a20, 0x1a20be5a, 0x281a18b7, 0x08511a20, 0x1a20955a, 
+    0xc332209d, 0x1a20e71a, 0x291a18b6, 0x084e1a20, 0x1a20905a, 0xc75a20a3, 0x20b45a20, 0x5a084a1a, 
+    0xa91a208a, 0x1acb3220, 0xb21a20e6, 0x202a1a18, 0x5a08471a, 0xaf1a2085, 0x20d05a20, 0x1a18b11a, 
+    0x431a202b, 0x20805a08, 0x3220b41a, 0x20e51ad4, 0x1a18af1a, 0x401a202c, 0x207a5a08, 0x5a20ba1a, 
+    0xad1a20d9, 0x202d1a18, 0x5a083c1a, 0xc01a2075, 0x1add3220, 0xac1a20e4, 0x202e1a18, 0x5a08391a, 
+    0xc51a206f, 0x20e25a20, 0x1a18aa1a, 0x351a202f, 0x206a5a08, 0x5a20cb1a, 0xa81a20e6, 0x20301a18, 
+    0x5a08321a, 0xd11a2065, 0x1aea3220, 0xa71a20e3, 0x20311a18, 0x1a082e1a, 0xf41a205f, 0x20d71a20, 
+    0x1a20ef5a, 0x321a18a5, 0x082b1a20, 0x1a205a5a, 0xf33220dc, 0x1a20e21a, 0x331a18a3, 0x08271a20, 
+    0x1a20555a, 0xf85a20e2, 0x20a25a20, 0x5a08241a, 0xe81a204f, 0x20fc5a20, 0x1a18a01a, 0x211a2034, 
+    0x204a5a08, 0x2320ed1a, 0xe11a0101, 0x189e1a20, 0x1a20351a, 0x441a081d, 0x20f31a20, 0x5a20f31a, 
+    0x9d1a2005, 0x20361a18, 0x5a081a1a, 0xf91a203f, 0x200a1a20, 0x1a20e01a, 0x371a189b, 0x08161a20, 
+    0x1a20395a, 0x0e5a20fe, 0x18991a20, 0x2a20381a, 0x20198813, 0x2320f21a, 0x135a0c04, 0x38982a20, 
+    0x101a2019, 0x202f5a08, 0x1a200a1a, 0xdf1a2017, 0x18961a20, 0x1a203a1a, 0x295a080c, 0x200f1a20, 
+    0x1a201c5a, 0x3b1a1894, 0x08091a20, 0x1a20241a, 0x151a20f1, 0x20215a20, 0x1a18931a, 0x061a203c, 
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+    0x1c661a14, 0x1a04291a, 0x581a0c5d, 0x1cba1a20, 0x1a04431a, 0x2b1a2095, 0x1c641a14, 0x1a042b1a, 
+    0x521a0c5b, 0x1cb71a20, 0x1a04471a, 0x2c1a209b, 0x1c621a14, 0x1a042d1a, 0x4c1a0c5a, 0x1cb41a20, 
+    0x1a044b1a, 0x2e1a20a1, 0x1c611a14, 0x1a042e1a, 0x471a0c58, 0x1cb11a20, 0x1a044f1a, 0x2f1a20a6, 
+    0x1c5f1a14, 0x1a04301a, 0x411a0c56, 0x1cad1a20, 0x1a04521a, 0x301a20ac, 0x1c5d1a14, 0x1a04321a, 
+    0x3b1a0c55, 0x1caa1a20, 0x1a04561a, 0x311a20b2, 0x1c5b1a14, 0x1a04331a, 0x351a0c53, 0x1ca71a20, 
+    0x1a045a1a, 0x331a20b7, 0x1c5a1a14, 0x1a04351a, 0x301a0c52, 0x1ca31a20, 0x1a045d1a, 0x342a20bd, 
+    0x1a1c19f4, 0x501a0437, 0x202a1a0c, 0x1a1ca01a, 0xc31a0461, 0x14361a20, 0x1a1c561a, 0x4e1a0439, 
+    0x20241a0c, 0x1a1c9d1a, 0xc81a0465, 0x14371a20, 0x1a1c541a, 0x4d1a043a, 0x201e1a0c, 0x1a1c991a, 
+    0xce1a0468, 0x14381a20, 0x1a1c531a, 0x4b1a043c, 0x20191a0c, 0x1a1c961a, 0xd41a046c, 0x143a1a20, 
+    0x1a1c511a, 0x4a1a043e, 0x20131a0c, 0x1a1c921a, 0xda1a046f, 0x143b1a20, 0x1a1c4f1a, 0x481a043f, 
+    0x200d1a0c, 0x1a1c8f1a, 0xdf1a0473, 0x143d1a20, 0x1a1c4d1a, 0x471a0441, 0x20071a0c, 0x1a1c8c1a, 
+    0xe51a0477, 0x143e1a20, 0x1a1c4c1a, 0x451a0443, 0x20021a0c, 0x1a1c881a, 0xeb1a047a, 0x143f1a20, 
+    0x191c4a2a, 0x0c441a04, 0x1a14fc1a, 0x7e1a1c85, 0x0cf01a04, 0x1a14411a, 0x461a1c48, 0x0c421a04, 
+    0x1a14f61a, 0x04291c81, 0x14290c29, 0x22111c29, 0x01ff1a01, 0x011b1e01, 0x21012701, 0x06324839, 
+    0x02d20742, 0xe7041190, 0x0ded288c, 0xf34d3fae, 0x2474538e, 0x27293ff4, 0x08010c10, 0x054c4b40, 
+    0x06020403, 0x04121801, 0x08010206, 0x02030201, 0x050a050a, 0x0a150a01, 0x031c511f, 0x292c0301, 
+    0x3904790c, 0x024e1219, 0xb7127411, 0x4b04b11a, 0x14b80502, 0x1a150404, 0x97290240, 0x1208301a, 
+    0x01351414, 0x127f1276, 0x127b127e, 0x22751278, 0x0808130c, 0x04298012, 0x90140c29, 0x901c02fd, 
+    0x0d0e02f1, 0x2a200718, 0xe249982b, 0xc7399849, 0x12981f09, 0x046a1a70, 0x063c9869, 0x32981606, 
+    0x12181206, 0xb60a1a20, 0x3f123b12, 0x3c123e12, 0x38ba3a12, 0xc70b1a98, 0x2b98d02a, 0x0c3202ef, 
+    0x1a191018, 0x98039a98, 0x20090c29, 0x1a4b1298, 0x98690446, 0x1708083c, 0x12053298, 0x08101a0c, 
+    0x1d126d12, 0x1e1a1f12, 0x3a1c1206, 0x98698c1b, 0x022b6f19, 0xee1a98f0, 0xff1b316d, 0xff0242ff, 
+    0x1f2f0107, 0x07ff3fff, 0x3a0203ff, 0x1b110201, 0x1a0c0fff, 0x16020a0f, 0xae5e0303, 0x014c02ae, 
+    0xda238022, 0x1a190814, 0xffffd475, 0xffffe80d, 0xfffff580, 0xfffffb0b, 0xfffffe74, 0xffffffa2, 
+    0x38851a38, 0xc75c1218, 0xe6caffff, 0xf8ceffff, 0xfdb2ffff, 0x9d4affff, 0x1a021c23, 0x4f1a04e6, 
+    0x483b1a04, 0xbb1a38e9, 0xcf2b1e2c, 0x684effff, 0x2304be1a, 0x5e1a0479, 0x40361a38, 0x1a34641a, 
+    0xf8327894, 0x1a18ae1a, 0x9b192055, 0x2338ff2a, 0x0a18082a, 0xffffc868, 0xfffff10e, 0xe41a14b4, 
+    0x244a1a2c, 0x1e3c581a, 0xfffffacf, 0x1d2340ed, 0x18b81a03, 0x2a0cc01a, 0x38197cd1, 0x18160423, 
+    0xfff6b70a, 0xfff499ff, 0x367c42ff, 0xfffffc7d, 0x28561ad0, 0x1a30971a, 0x781a44c5, 0x0cc31a04, 
+    0x1a4cd41a, 0x3829183e, 0x1e400a1a, 0xffffcc92, 0x22111871, 0x3c6a1a09, 0xfff92527, 0x1a11a3ff, 
+    0xa91e3077, 0xb7fffff7, 0x0b1c231c, 0x1a38ef1a, 0x3829acc1, 0x181a8f23, 0xffd0490e, 0xffe845ff, 
+    0xfff578ff, 0x1a7cf9ff, 0x341ab0e0, 0x28351ac0, 0xeb1a9732, 0x196dc238, 0x3e342338, 0xe5ab0a18, 
+    0xd3afffff, 0x3cbaffff, 0x1a60181a, 0xcf1a549b, 0x8c2e1acc, 0x1ab8bd1a, 0x501a0cf2, 0x04f81a44, 
+    0x23e0165a, 0x0a180e94, 0xffffd232, 0xfffff25e, 0x091aa0fe, 0x28281a18, 0x3d328a32, 0x1a7c361a, 
+    0x791a3cc9, 0x1ac63204, 0x38293c69, 0x30059623, 0xffeddd0a, 0xfff3b1ff, 0x1f1ab4ff, 0x1a78326c, 
+    0x1b320829, 0xfffaff36, 0x431aa0ff, 0x44a91a10, 0x23581a1a, 0x42237fff, 0xe0401a0f, 0x1edc791a, 
+    0xfffff808, 0x3e23189c, 0x28221a02, 0x1a78b41a, 0xed1a68be, 0x07712314, 0x1a0c2d23, 0x18411495, 
+    0x7154c721, 0xb8aa63e7, 0xdc553173, 0xee2a9839, 0x77154c1c, 0x3b8aa60e, 0x9dc55307, 0xcee2a983, 
+    0x601a1fc1, 0x1fb01a1f, 0x1a1f581a, 0x22181fac, 0x766f4d56, 0x3b37a64c, 0x1d9bd3a6, 0x8ecde953, 
+    0xc766f4a9, 0x63b37a54, 0x31d9bdaa, 0x98ecde55, 0x151a1f2a, 0x1f8a1a1f, 0x1a1fc51a, 0x711a1fe2, 
+    0x1fb81a1f, 0x1a1fdc1a, 0x771a1fee, 0x1f3b1a1f, 0x521f9d1a, 0x010113ce, 0x07490239, 0x0d291029, 
+    0x05390a19, 0x0d202811, 0x06f6d9c4, 0x037b6ce2, 0x81bdb671, 0x40dedb38, 0x206f6d9c, 0x1037b6ce, 
+    0x881bdb67, 0x1a1fedb3, 0xc31a1f86, 0x1f611a1f, 0x1a1fb01a, 0x2c1a1f58, 0x1f961a1f, 0x1a1fcb1a, 
+    0x721a1fe5, 0x1f392a1f, 0xab601618, 0xd5b03881, 0x6ad89c40, 0x356cce20, 0x1ab66710, 0x465bb388, 
+    0x1a65ad1a, 0x1f196556, 0x1a1fdb1a, 0xb61a1f6d, 0x1fdb1a1f, 0x699ded2a, 0x499c79aa, 0x29ac39b3, 
+    0x250d181e, 0x12421084, 0x09210842, 0x0b108421, 0x1a0b081a, 0x421a0b84, 0x0b211a0b, 0x041a1469, 
+    0x0b021a0b, 0x1114011a, 0x94a12018, 0x4a504252, 0xa5282129, 0x52941094, 0x294a084a, 0x94a58425, 
+    0x4a524212, 0xa5292109, 0x421a1484, 0x14211a14, 0x1b14101a, 0x1a1f2108, 0x081a1f10, 0x1f841a1f, 
+    0x1a1f421a, 0x101a1f21, 0x1f081a1f, 0xc1a4842a, 0x05c9b649, 0x1a2c801a, 0x100a2c40, 0xb0a99c20, 
+    0x1a0b901a, 0xa41a0b48, 0x14521a14, 0x1a14291a, 0x4a1a1494, 0x1fa51a14, 0x481a1419, 0x94a41414, 
+    0x42101404, 0x21081402, 0x10842301, 0x19084223, 0x11651988, 0x19116519, 0x1a1f1965, 0x841a1f08, 
+    0x1f421a1f, 0x6a1f211a, 0x019a8e10, 0x01a5b905, 0x100a1813, 0x0f100f0e, 0x10011010, 0x39353904, 
+    0x143a0101, 0x1c01ffff, 0x0802fffe, 0xfd144e29, 0xfb1a04ff, 0xfffe1604, 0x1406ffff, 0x1c0dfff6, 
+    0x0e09fff3, 0x11fff914, 0x1dffe714, 0x0fffe614, 0xea140212, 0xc8142aff, 0xd2143aff, 0x111214ff, 
+    0x5effc514, 0x6dff8f14, 0x121cb51a, 0xff6f143f, 0xff1014d3, 0xff8116d8, 0x10ecffe5, 0xdcfe1f18, 
+    0x69fc4202, 0xc4fb3c04, 0xbefb9704, 0xe1fd2403, 0x1bff1401, 0x28147f12, 0x2d14f0ff, 0xc11691ff, 
+    0x4bfff1ff, 0x71ff9314, 0x3bffa214, 0xecffef16, 0xc6142eff, 0xd61c38ff, 0x147816ff, 0x1c1afff1, 
+    0x1819ffe3, 0x3a78071a, 0x0a1290f7, 0x12b4fa1a, 0xfffc1c02, 0x035a0405, 0x02c449ba, 0x025a0119, 
+    0x1c0332dc, 0x520cfffb, 0x1204131a, 0x14061208, 0x1429ffe8, 0x1a34ffcc, 0x21120eda, 0x75ffb214, 
+    0x7eff7714, 0x127cb41a, 0xda16188e, 0xad01c3fe, 0x0402c1fd, 0x3f02fcfd, 0x3d0253fd, 0x720126fe, 
+    0x144c12e8, 0x1489ff82, 0x3e4eff8b, 0xfff8ffdf, 0xd71c4026, 0x149a18ff, 0x1a11fff8, 0xf41a04ed, 
+    0xfd5a219e, 0x1cfe1aa4, 0x09ffea14, 0x122a111a, 0xff921457, 0xffb9166c, 0x1e80fff7, 0x01b7feea, 
+    0x121160b3, 0x030b18fd, 0x024dfd3f, 0x0116fe49, 0x47122880, 0x6eff9414, 0x1a56a91a, 0x161a28ef, 
+    0x1b1021a4, 0x20131e48, 0x23fd21fa, 0x2862261f, 0x2d4f2ac6, 0x32d62ffe, 0x390a35d9, 0x20283c6b, 
+    0xcf43cb40, 0x924c1047, 0x67555850, 0x6f5fc25a, 0xcf6b7265, 0xb2788e71, 0x4787437f, 0x0297c58f, 
+    0x3fff0c10, 0x016201a9, 0x01020128, 0x12cb12e6, 0xff2018b7, 0xbd035f3f, 0xeb023602, 0x79018f01, 
+    0xff015101, 0x9704343f, 0x7602e003, 0xde01fe02, 0x1810a401, 0x4903dd0e, 0x0802e603, 0xdb01f802, 
+    0x18108d01, 0x0703840e, 0xe001fe03, 0xb801c201, 0x08108b01, 0x048d110e, 0x03760410, 0x022302cb, 
+    0x40b001f4, 0x03ff0ef8, 0x02900339, 0x01ae021c, 0x306b019a, 0x12231221, 0x1237122d, 0x124b1241, 
+    0x5f110255, 0x8002dd16, 0x1b001e01, 0x5eff7d10, 0x78ff71ff, 0x6aff6bff, 0x93ff80ff, 0x66ff81ff, 
+    0xa3ff73ff, 0xfaffdfff, 0x2b0112ff, 0x1a3c1909, 0x086901ff, 0x19961902, 0x672209cf, 0x03ffff17, 
+    0x23010265, 0x30234874, 0x157c2323, 0x230ed823, 0xc9230b1e, 0x073c2308, 0x23061a23, 0xb323054e, 
+    0x043e1a04, 0x1a03db23, 0x4f1a048d, 0x04231a04, 0x1a02f423, 0xb91a04d5, 0x049c1a04, 0x1a04891a, 
+    0x691a0478, 0x04611a04, 0x1a045b1a, 0x4e1a044d, 0x044b1a04, 0x1a04411a, 0x441a0446, 0x08405a04, 
+    0x1a044c5a, 0x631a0458, 0x04711a04, 0x1a04831a, 0x931a048c, 0x609a5a04, 0xb81a0429, 0x04c71a04, 
+    0x1a04d31a, 0xf91a04ef, 0x880a1a04, 0x1a04251a, 0x541a0448, 0x04831a04, 0x1a04a61a, 0xdf1a04b7, 
+    0x04fd1a04, 0x1abc1b1a, 0x711a0454, 0x04a31a04, 0x1a04d01a, 0x1f1a04f4, 0x045d1adc, 0x1a04931a, 
+    0x2a1a04dc, 0x047f1af0, 0x2304e91a, 0xa01a0747, 0x04f91a04, 0x1a085a23, 0x252304c4, 0x049e1a09, 
+    0x1a0a1b23, 0x592304c2, 0x04ce1a0b, 0x230c7e23, 0x3d230d4f, 0x0f32230e, 0x23102623, 0x8f23116c, 
+    0x13e02312, 0x23154223, 0xaf1b169c, 0x191a4017, 0x231b222c, 0xa9231ca7, 0x2127231e, 0x23236523, 
+    0x3723262c, 0x2c182329, 0x232ea523, 0x04233238, 0x39392336, 0x1b3e4c23, 0x22c0423c, 0x4acc2347, 
+    0x23507523, 0x03235568, 0x6102235b, 0xcc64971b, 0xfb236b22, 0x778e2370, 0x1b7dd823, 0x1a7c83b0, 
+    0x8e22a887, 0x2391ab23, 0xd92397e5, 0x9e142398, 0xe39f7223, 0xfd749ddd, 0x8d19fdfd, 0x1b026f01, 
+    0x0f2603ff, 0x00000027, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x0005c000, 0xffffffff, 0x4da24ce9, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
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+    0x4605b570, 0x4616460c, 0xcc0fe002, 0x3e10c50f, 0xd2fa2e10, 0xd3022e08, 0xc503cc03, 0x2e043e08, 
+    0xcc01d307, 0x1f36c501, 0x7821e003, 0x1c647029, 0x1e761c6d, 0xbd70d2f9, 0xe7fee7fe, 0xe7fee7fe, 
+    0xe7fee7fe, 0xe7fee7fe, 0xe7fee7fe, 0xe7fee7fe, 0xe7fee7fe, 0xe7fee7fe, 0xf7ffb510, 0xbd10ff7f, 
+    0x4603460a, 0xe7fe4770, 0x00004770, 0xfffcf7ff, 0xf982f007, 0xf9def007, 0x20004d2e, 0x6028462c, 
+    0x07092105, 0x60281840, 0xf892f007, 0xf835f007, 0x07002003, 0x49288a81, 0x68228281, 0x48271c49, 
+    0x85111812, 0x18086821, 0x1f2f8e80, 0x70380b00, 0xf845f003, 0xfadcf007, 0x4e214922, 0x2003600e, 
+    0x04406822, 0x60224382, 0x2400462f, 0xe019460d, 0x21926828, 0x30405c09, 0x80810209, 0xf87df003, 
+    0x22036828, 0x7cc03080, 0x02000452, 0x60281980, 0x7c803080, 0x07806839, 0x0b404391, 0x1c644301, 
+    0x6039b2e4, 0x1f00480b, 0x42847800, 0x2403d3e0, 0xf0000464, 0x6828f9de, 0x7cc03080, 0x19800200, 
+    0x30806028, 0x68397c80, 0x43a10780, 0x43010b40, 0xe7ee6039, 0x20000084, 0x00007fff, 0x0001a1c0, 
+    0x20000300, 0x20000090, 0x215648fe, 0x5c0a6800, 0x31804601, 0xd0042a01, 0x734a7982, 0x738879c0, 
+    0x7a024770, 0x7a40734a, 0x49f7e7f9, 0x47705c08, 0x2100b51c, 0x8011466a, 0x49f48090, 0x7b094af2, 
+    0x5c524cf0, 0x31606821, 0x429a780b, 0x2216d917, 0x2301568a, 0x429a07db, 0x0700d111, 0x28020f80, 
+    0x2008d00d, 0x8018466b, 0x758a1e52, 0x29017d09, 0xf006d001, 0x6820f936, 0x7d003060, 0x2001bd1c, 
+    0xe7f87508, 0x680248e2, 0x185249e2, 0x68038ed2, 0x0f520492, 0x8edb185b, 0x055b6800, 0x18d20f5b, 
+    0x18400852, 0x06808ec0, 0x18100e80, 0x49d64770, 0x5c083115, 0xb57c4770, 0x48d44605, 0x7b0049d2, 
+    0x5c0c3115, 0x46692000, 0x808d8008, 0xffdaf7ff, 0x0f8906a9, 0x42a04dcb, 0x682ad80a, 0x7d523260, 
+    0xd20542a2, 0xd0032903, 0x466a2110, 0xe0158011, 0x42a02601, 0x682ad90f, 0x7d533260, 0xd20a42a3, 
+    0x0064181b, 0xd90642a3, 0xd0042902, 0x466b2120, 0x74d68019, 0x6829e002, 0x74ce3160, 0x31606829, 
+    0x46687548, 0x06818800, 0xd0010f89, 0xf8d9f006, 0x30606828, 0xbd7c7cc0, 0x4cb2b5f8, 0x68202603, 
+    0x30400736, 0x27017ac0, 0x4db13825, 0xf0070003, 0x2107fb59, 0xa1818f6f, 0x0005bfb1, 0x20078ab0, 
+    0x82b043c0, 0x2107682a, 0x304048aa, 0x85111812, 0x21028ab1, 0x82b143c9, 0x2102682a, 0x84011810, 
+    0xf0072008, 0xf006f9c0, 0x6821ff54, 0x20008448, 0x76083140, 0x46016820, 0x7d8a3180, 0xd0092a00, 
+    0x07527f42, 0x222bd53c, 0x72823040, 0xf006764f, 0xbdf8f8cc, 0xff3df006, 0x6820b281, 0x1a518c42, 
+    0xdb2b2964, 0x5c092158, 0xd1022900, 0x05c08800, 0x2102d40d, 0xf007200f, 0x8ab0f996, 0x43c02001, 
+    0x682882b0, 0x0349210d, 0x86471840, 0x8ab0e016, 0x43c02001, 0x682882b0, 0x18404987, 0x463a8cc0, 
+    0x68284382, 0x84c21840, 0xff13f006, 0x84486821, 0x760f3140, 0x201d2102, 0xf975f007, 0xe07f2125, 
+    0x31ff6829, 0x8e493101, 0x0e890689, 0x80413040, 0x22266820, 0x31404601, 0x308072ca, 0x28007dc0, 
+    0x8848d0b7, 0xff37f7ff, 0xd00d2801, 0x21286820, 0x72c13040, 0x21986820, 0x29005c09, 0x2114d0a9, 
+    0x72813040, 0xe05d2126, 0x20006821, 0x80483140, 0x22276820, 0x31404601, 0x308072ca, 0x28007dc0, 
+    0x8848d097, 0xfed4f7ff, 0xd00d2801, 0x21296820, 0x72c13040, 0x21986820, 0x29005c09, 0x2114d089, 
+    0x72813040, 0xe03d2127, 0xf84ff006, 0x212a6820, 0x72c13040, 0x49576828, 0x18403180, 0x07408880, 
+    0xd0bd0fc0, 0x21996820, 0x212b540f, 0x72c13040, 0x30ff6828, 0x8dc03001, 0x07c008c0, 0xd0000fc0, 
+    0x6828e767, 0x300130ff, 0x07408dc0, 0xd1f70fc0, 0x30ff6828, 0x8dc03001, 0x0fc00780, 0x6828d1f0, 
+    0x300130ff, 0x07c08dc0, 0x8ab0d0ea, 0x43c02004, 0x682a82b0, 0x483f2104, 0x18103040, 0x212c8401, 
+    0x30406820, 0xbdf872c1, 0x4c39b5f8, 0x30ff6820, 0x8d803001, 0x07804a33, 0x4f360fc1, 0x68102395, 
+    0x072d2503, 0x37404e35, 0x29005419, 0x7f40d019, 0xd4090700, 0x22184b2d, 0x20172116, 0x5659569a, 
+    0x23005618, 0xfc57f006, 0x82ae8aa8, 0x20016821, 0x840819c9, 0x68004823, 0x07807800, 0x1c4017c0, 
+    0x8aa8bdf8, 0x682182ae, 0x19c92004, 0x20008408, 0xb5febdf8, 0x24004d1b, 0x30806828, 0x28007c80, 
+    0xf002d119, 0x270ffdfb, 0xf006033f, 0x4e1cfe11, 0x68310c00, 0x1a400c09, 0xdd0c42b8, 0x21ff4819, 
+    0x21f07081, 0x70047041, 0xf0072003, 0x6830f80f, 0x18400439, 0x4e0e6030, 0x480f6831, 0x18083040, 
+    0x0bc08d00, 0x2300d106, 0x461a9907, 0x94002001, 0xffc1f006, 0x31806829, 0x72c87a88, 0x68024804, 
+    0xe011200d, 0x20000090, 0x00007b82, 0x20000200, 0x20000084, 0x0001a040, 0x0001a180, 0x0000fffa, 
+    0x20000088, 0x2000008c, 0x18100340, 0x0ac28f80, 0x0601728a, 0xd1030fc9, 0x0e800680, 0xfa30f002, 
+    0x7c416828, 0xd0192900, 0xf007000b, 0x0708f9db, 0x0b080507, 0x0713110e, 0xfec3f000, 0xf000bdfe, 
+    0xbdfeff35, 0xffb5f001, 0xf001bdfe, 0xbdfef9d5, 0xe0002000, 0xf0012001, 0xbdfefb04, 0x22522100, 
+    0x88015411, 0x078a4dfe, 0x2a002401, 0x4efddb36, 0xd5330589, 0x7a813080, 0xd92f2903, 0xd02d2911, 
+    0x28007d40, 0x48f8d02a, 0x200d6801, 0x18080340, 0x07c08e80, 0xf006d122, 0x6836fdbc, 0x46304607, 
+    0xf0073036, 0x2110f8b7, 0x49f041c8, 0x42881bc0, 0x05c8d314, 0x82858a81, 0x680148eb, 0x0340200d, 
+    0x86441808, 0x0c388737, 0x364086f0, 0x21027a70, 0x72704308, 0xf007201e, 0xbdfef806, 0x68304ee1, 
+    0x7ac13080, 0xd1062900, 0x28007a80, 0x2101d013, 0xf0062003, 0x6830fff8, 0x7ac13080, 0xd9012903, 
+    0xd1082911, 0x28037a80, 0x2811d905, 0x2101d003, 0xf0062026, 0x48d3ffe8, 0x46016800, 0x7a8a3180, 
+    0xd01f2a00, 0xd07d2a01, 0xd07c2a02, 0xd07b2a03, 0x7a8f3940, 0x003b4ecb, 0xf954f007, 0xf0f1f125, 
+    0xeeefefef, 0xecedeeee, 0xe8e9eaeb, 0xe4e5e6e7, 0xe0e1e2e3, 0xdfdedfdf, 0xdfdfdfdf, 0xdedfdfde, 
+    0x00dedddd, 0x4ebf7ac8, 0xd0032800, 0x20012102, 0xffb9f006, 0x68394fbc, 0x180848bd, 0x07408a40, 
+    0xd0230f80, 0xd0292801, 0x30406830, 0x07c07a40, 0xf002d001, 0x6830fc75, 0x30402101, 0x68387481, 
+    0x4fb4463e, 0x8e0019c0, 0x0f800740, 0xd07d2801, 0x7d204cb1, 0xd1902800, 0x46039000, 0x21042201, 
+    0xf0069001, 0x2001ff1a, 0xbdfe7520, 0x30406830, 0x07c07a40, 0xf002d0f9, 0xbdfefc53, 0x48a56839, 
+    0x180838c0, 0x07c08980, 0xd0110fc0, 0x07002003, 0x82858a81, 0x2000683a, 0x39c0499e, 0x81881851, 
+    0xfc7df002, 0x22bf6830, 0x7a013080, 0x72014011, 0x07002003, 0x21028a81, 0x828143c9, 0x2002683a, 
+    0xe0024994, 0xe156e0b3, 0x39c0e24a, 0x81481851, 0xfc26f002, 0x78006830, 0xd00107c0, 0xfc7ff006, 
+    0x488b6839, 0x8ac01808, 0x07006839, 0x31ff0f00, 0x8d893101, 0x07892300, 0x01090fc9, 0x68304301, 
+    0x0a028800, 0x43110212, 0x0a000600, 0x20034301, 0x91012202, 0x46119000, 0xf0062001, 0xf002febe, 
+    0xf7fffd49, 0x2800fe41, 0x8a81487c, 0x2102d014, 0x828143c9, 0x2102683b, 0x189a4a79, 0x8a8180d1, 
+    0x82814978, 0x0189210d, 0xe000683a, 0x20d1e038, 0x18100240, 0xe01184c1, 0x82814972, 0x683b22ff, 
+    0x21d13241, 0x18590249, 0x8a8184ca, 0x43c92102, 0x683a8281, 0x496a2000, 0x80c81851, 0x8a814867, 
+    0x68398285, 0x30404866, 0x81441808, 0x7ac16830, 0x72c11c49, 0xe3abbdfe, 0xe33ee220, 0xe3fbe3c0, 
+    0xe23ce2a9, 0xe3cfe31a, 0xe332e358, 0xe304e30b, 0xe283e3a4, 0xe2ece257, 0xe231e24d, 0xe222e31e, 
+    0x8aa04c56, 0x43c02002, 0x683182a0, 0x19c92002, 0x68308548, 0x8d8019c0, 0x0fc007c0, 0x8aa0d007, 
+    0x683182a5, 0x19c92000, 0xf0028588, 0xf002fc16, 0x4849fbc2, 0x07c07800, 0xf006d001, 0x4846fbef, 
+    0x88002102, 0xba402300, 0x90019100, 0x21052201, 0xf0064618, 0x4840fe42, 0x75012100, 0xfca0f002, 
+    0x82a58aa0, 0x20016831, 0x854819c9, 0x4e36e7b2, 0x270d6831, 0x19c9037f, 0x07898f49, 0x4601d005, 
+    0x7a4a3140, 0x401a23fd, 0x4601724a, 0x7a4a3140, 0xd00507d2, 0x28007880, 0x7a08d124, 0xd0212800, 
+    0x72882000, 0x7800482c, 0xd5360640, 0x68004825, 0x07c07800, 0x6831d031, 0x18084825, 0x07008ac0, 
+    0x28080f00, 0x4825d186, 0x82858a81, 0x22006833, 0x31404923, 0x805a185b, 0x82858a82, 0x18406830, 
+    0xe7778044, 0xfb3cf002, 0xfd7ef7ff, 0xd0d92800, 0x8a81481a, 0x68328285, 0x024921d1, 0x84d41852, 
+    0x82858a82, 0x32ff6832, 0x85943201, 0x82858a82, 0x20006832, 0x84c81851, 0x6830e7c4, 0x8e4019c0, 
+    0x0fc00780, 0x480dd108, 0x490f8a81, 0x20018281, 0x03406831, 0x840819c9, 0x19c06830, 0xe0158f80, 
+    0x0000fffe, 0x20000090, 0x20000084, 0x0000ea60, 0x0001a300, 0x0001a1c0, 0x20000200, 0x30000000, 
+    0x0001a0c0, 0x0000fc0f, 0x0000dfff, 0x0ac24dfe, 0x46016828, 0x728a3180, 0xd00c2a01, 0x1c497a81, 
+    0x68307281, 0x8f4019c0, 0xb2c02300, 0x21072202, 0x90019400, 0x7ac8e00b, 0xd00b2801, 0x19c06830, 
+    0x23008f40, 0x2202b2c0, 0x94002106, 0x20019001, 0xfd93f006, 0x3040e12e, 0x4eeb7a81, 0x7a412900, 
+    0x4321d005, 0x20027241, 0x90019400, 0x4321e12b, 0x79c27241, 0x00520852, 0x078a71c2, 0x2000d40a, 
+    0xf00643c0, 0xf006fb62, 0x6830fb75, 0x870149df, 0xe00886c1, 0x401122fd, 0xf0067241, 0x6831fb7a, 
+    0x0c008708, 0x683086c8, 0x30404601, 0x07d27a42, 0x7889d005, 0xd1582900, 0x28007a00, 0x2003d055, 
+    0x8a810700, 0x43c92120, 0x49d18281, 0x680a2000, 0x0349210d, 0x84081851, 0xfdebf002, 0x682a4dcc, 
+    0x181048cc, 0x68298ac0, 0x0f000700, 0x310131ff, 0x23008d89, 0x0fc90789, 0x43010109, 0x88006830, 
+    0x02120a02, 0x06004311, 0x43010a00, 0x91012003, 0x22029000, 0x2001211a, 0xfd2ff006, 0x210248be, 
+    0x460a8800, 0x9100ba40, 0x23009001, 0x20012119, 0xfd23f006, 0x30806830, 0x7a004684, 0xd4740640, 
+    0x21032200, 0x8a880709, 0x43c02084, 0x07d08288, 0x0e00682e, 0x18f64bb1, 0x85b01d00, 0x21002000, 
+    0xd2052810, 0x1a1b231f, 0xf002e004, 0xe7b5fceb, 0x3b104603, 0xb2db4eaa, 0x2a008ab7, 0x271fd007, 
+    0x82b743ff, 0x4ea5682f, 0x85f319be, 0x4fa5e006, 0x682f82b7, 0x4ba1021e, 0x859e18fb, 0x682f2300, 
+    0x36804e9e, 0x8a3619be, 0x07f60a36, 0xd0010ff6, 0xb2c91c49, 0xb2db1c5b, 0xd3f02b0a, 0xd0042800, 
+    0xd81e2905, 0xd002281f, 0x2905e017, 0x4894d915, 0x8a812a00, 0x211fd008, 0x828143c9, 0x2010682b, 
+    0x1859498e, 0xe00c85c8, 0x8281498e, 0x682b2001, 0x498a0300, 0x85881859, 0x1c40e003, 0x2820b2c0, 
+    0x1c52d3ad, 0x2a02b2d2, 0x4885d39b, 0x21048a81, 0x828143c9, 0x2000682a, 0x18514980, 0x46608588, 
+    0x21407a00, 0x46614308, 0x487d7208, 0x497e8a81, 0x21018281, 0x0389682a, 0x0340200d, 0x84011810, 
+    0x68014873, 0x0340200d, 0x8f801808, 0x0ac04d6e, 0x31806829, 0x28037288, 0x7ac9d005, 0xd9082903, 
+    0xd0062911, 0x7ac8e00d, 0xd00a2803, 0x20252101, 0x2803e005, 0x2811d905, 0x2101d003, 0xf0062026, 
+    0x6829fcf2, 0x7a483140, 0xd40a0782, 0x43c02000, 0xfa5bf006, 0xfa6ef006, 0x495c6828, 0x86c18701, 
+    0x22fde008, 0x72484010, 0xfa73f006, 0x87086829, 0x86c80c00, 0x30406828, 0xe5db7484, 0x43207a48, 
+    0x94007248, 0x23009401, 0x21152202, 0xf0062001, 0x4853fc54, 0x82858a81, 0x6801484d, 0x0340200d, 
+    0x86441808, 0x2a07e5c6, 0x728cd001, 0x7880e5c2, 0xd1052800, 0x28007a08, 0x2013d002, 0xe0e57288, 
+    0xfb67f003, 0xd0d82802, 0x8a814845, 0x3b804b3f, 0x4c3f8283, 0x68252180, 0x0352220d, 0x806918ad, 
+    0x82838a81, 0x20006821, 0x80481889, 0x21066830, 0x72813040, 0xf005e59e, 0x2802f81a, 0xf005d0bd, 
+    0x2801f816, 0xf004d0b9, 0x2802f927, 0x6830d0b5, 0x5c092153, 0xd0042900, 0xd12a2901, 0x07497801, 
+    0x7800d527, 0xd4240600, 0xf0002017, 0xf003fa9d, 0x6830fb18, 0x84412105, 0xf0042009, 0x2104f973, 
+    0xf006202b, 0xf003fc70, 0x6831fee7, 0x70083160, 0xfa5ff000, 0x210b6830, 0x72813040, 0xfaa1f000, 
+    0xd08a2800, 0xfae4f004, 0x30406830, 0x28007dc0, 0x6830d0ee, 0x30602300, 0x78417802, 0x78800212, 
+    0x04004311, 0x20034301, 0x91012201, 0x21129000, 0xf0064610, 0x6830fbd2, 0x30402100, 0x75017481, 
+    0x46016830, 0x7aca3140, 0xd0012a28, 0xd1022a29, 0x2a017d0a, 0x7ccad07c, 0xd0042a00, 0xd11d2a01, 
+    0x075b7803, 0xe011d51a, 0x20000090, 0x0000ffff, 0x20000084, 0x0001a300, 0x20000200, 0x0001a100, 
+    0x30000000, 0x0000e0ff, 0x0000bfff, 0x061b7803, 0x2300d404, 0x71833060, 0xe0027203, 0x71843060, 
+    0x2a027204, 0x2003d329, 0x8a820700, 0x43d2220f, 0x4ab78282, 0x68152402, 0x035b230d, 0x862c18ed, 
+    0x4cb48a84, 0x68128284, 0x18d21500, 0x20098610, 0x2200e125, 0x728a2003, 0x8a810700, 0x43c9210f, 
+    0x4dab8281, 0x210d682b, 0x185b0349, 0x8a83861a, 0x82834ba8, 0x18406828, 0xf0048602, 0x2800feef, 
+    0xe4e7d000, 0xf004e05e, 0x2802f8a4, 0x6830d0f9, 0x7bc13080, 0xd01c2900, 0x73c12100, 0x202e2104, 
+    0xfbd1f006, 0xf81cf005, 0xd1ea2800, 0x68014898, 0x0340200d, 0x8e891809, 0xd07d07c9, 0x21886830, 
+    0x07495c09, 0x3040d579, 0x28007cc0, 0xe0ecd076, 0xf004e04c, 0x2802fdec, 0x2104d0d3, 0xf006202c, 
+    0x6830fbb2, 0x79813040, 0xd5050749, 0x28017d80, 0xf004d002, 0xe001fc1a, 0xfc6ff004, 0xd0c02802, 
+    0x21846830, 0x29005c09, 0x3060d152, 0x29027981, 0x2900d002, 0xe009d002, 0xe00c7184, 0x202d2104, 
+    0xfb91f006, 0xfcf9f004, 0xd0aa2802, 0x30606830, 0x28017980, 0x6830d1a7, 0x7a013060, 0xd01c2902, 
+    0xfad7f004, 0x30606830, 0x29017981, 0x7a00d19b, 0xd1982801, 0x30406830, 0x29017d81, 0x7d01d006, 
+    0xb2c91c49, 0x29047501, 0xe729d200, 0x460a6831, 0x7cd03240, 0xd0022800, 0x7204e027, 0x8808e7ea, 
+    0xd5220743, 0x061d790b, 0x0658d505, 0x73d00e40, 0xfbf4f000, 0x0683e019, 0x2b020f9b, 0x7992d015, 
+    0xd5120712, 0xd4100600, 0x7b483180, 0xd40c06c0, 0xf8d4f005, 0xe0022802, 0xe07ce033, 0xd08be071, 
+    0x30806830, 0x28007900, 0x6830d183, 0x5c092195, 0xd00d2900, 0x7ac13040, 0xd009292c, 0x72812116, 
+    0xf94af7ff, 0x30406830, 0x282c7ac0, 0xe431d000, 0x21566830, 0x29015c09, 0xe74fd100, 0x06097801, 
+    0x2100d4fb, 0x71c13060, 0xfd99f004, 0xd0ee2802, 0x30606830, 0x280079c0, 0x6830d0f6, 0x73c43080, 
+    0x2503e731, 0x8aa9072d, 0x82ab4b3b, 0x27004a38, 0x18096811, 0x8aa9840f, 0x681282ab, 0x18102120, 
+    0xf0068401, 0x1c40f896, 0x21014240, 0x040908c0, 0xd3024288, 0xe0011e49, 0xb281e045, 0x82416830, 
+    0x1c497b01, 0x30407301, 0x21027204, 0xf006200e, 0x6830faea, 0x30804601, 0x2a007d42, 0x7e42d00b, 
+    0xd0082a00, 0x22078aaa, 0x82aa43d2, 0x68124a20, 0x18d24b22, 0x73078517, 0x748c3140, 0x72882002, 
+    0xf003e424, 0x2802fa5e, 0x6830d0fa, 0x308022fb, 0x40117a01, 0x201f7201, 0xf81cf004, 0x21156830, 
+    0x72813040, 0x07002003, 0x21808a81, 0x828143c9, 0x2180480f, 0x200d6802, 0x18100340, 0x68318401, 
+    0x318020ff, 0x68307288, 0x74843040, 0xf8e9f000, 0xd0d52800, 0x7a016830, 0xd1e309c9, 0x5c092190, 
+    0xd1df2900, 0x75843040, 0xf81ef7ff, 0x0000e653, 0x20000084, 0x0000fcff, 0x0000ffdf, 0x0001a080, 
+    0xd0162800, 0xd0152801, 0x00402100, 0x1c490840, 0xb2490040, 0xdafa2800, 0x22e00dc0, 0x17ca4010, 
+    0x18520ed2, 0x01520952, 0x221f1a89, 0x18401a51, 0x4770b2c0, 0x477020e0, 0x2403b5f0, 0x8aa10724, 
+    0x82a149fa, 0xdd012800, 0xe0002101, 0x4af82100, 0x4ef80289, 0x68321889, 0x037f270d, 0x811119d2, 
+    0x21002301, 0x4245025b, 0x8aa2e007, 0x82a24af2, 0x19d26832, 0x1c498113, 0x2800b249, 0x4602db01, 
+    0x462ae000, 0xdcf0428a, 0xb5f0bdf0, 0x215348eb, 0x23016800, 0x270d5c09, 0x4ae72403, 0x037f025b, 
+    0x4de40724, 0xd00c2900, 0x5e412126, 0x46084ee4, 0xd00c3011, 0xd017290f, 0x82a28aa0, 0x19c06828, 
+    0x8aa08103, 0x682882a2, 0x810319c0, 0x203ee01b, 0xf7ff43c0, 0x2001ffb1, 0xffaef7ff, 0x20ff8aa0, 
+    0x200182a0, 0xe00b0280, 0x43c0203e, 0xffa4f7ff, 0xf7ff2001, 0x8aa0ffa1, 0x82a020ff, 0x02c02001, 
+    0x19896829, 0x48cd8488, 0x8cc16800, 0x84c11c49, 0xb530bdf0, 0x07002003, 0x4aca8a81, 0x49c58282, 
+    0x680d2400, 0x18ed4bc6, 0x8a84842c, 0x680c8282, 0x18e31c52, 0x8a82841a, 0x43d22280, 0x68098282, 
+    0x220d2080, 0x18890352, 0x48bc8408, 0x680021ff, 0x72813080, 0x48b7bd30, 0x49b96800, 0x8e801840, 
+    0x16800480, 0x47704240, 0x2103b530, 0x8a8a0709, 0x828a138a, 0x06924242, 0x0dd2230d, 0x18d4025b, 
+    0x681d4bac, 0x18ad4aae, 0x8a8c82ec, 0x828c4cad, 0x1c61681b, 0x82d1189a, 0x680949a8, 0x70483160, 
+    0x48a6bd30, 0x30806800, 0x28077a80, 0x2000d001, 0x20014770, 0xb5704770, 0x210048a0, 0x7f226804, 
+    0x429a7da3, 0x1ad0d301, 0x20ffe002, 0x18801ac0, 0x8ce0b2c5, 0xd1012863, 0x03c92101, 0xd3012aff, 
+    0xe0002000, 0xb2c01c50, 0xd1024283, 0x03b62601, 0x429a4331, 0x2201d102, 0x43110352, 0x82a14329, 
+    0xb570bd70, 0xffd7f7ff, 0xf7ff4605, 0x2800ffca, 0x4c8ad063, 0x7d086821, 0xd25e28fb, 0x5e8a2226, 
+    0xd05a2a63, 0x7cce3140, 0x49854882, 0x2e004b86, 0x3210d016, 0x68022a1f, 0x1856d81d, 0x5eb22228, 
+    0x02926800, 0x8d401840, 0x4310b2c0, 0xfed8f7ff, 0x68204602, 0x5a092144, 0x18087f00, 0xe01c541a, 
+    0x18566802, 0x5eb22230, 0x02926800, 0x8e401840, 0x0d800580, 0x1856e007, 0x5eb2222c, 0x02926800, 
+    0x8dc01840, 0x4310b2c0, 0xfebaf7ff, 0x68204601, 0x5a122244, 0x18107f00, 0x68205419, 0xf7ff7705, 
+    0x211fff5a, 0xdc1c42c8, 0x22446820, 0x7f045a12, 0x19122100, 0x7f015499, 0xd30129ff, 0xe0002100, 
+    0x77011c49, 0x5e412126, 0xda07291f, 0xfeddf7ff, 0xf7ff201f, 0xf7ffff49, 0xbd70ff1c, 0x84c12163, 
+    0xf7ffbd70, 0x1e40ff38, 0xe7f2b240, 0xf7ffb5f0, 0x4607ff62, 0xff55f7ff, 0xd06f2800, 0x68304e4f, 
+    0x29fb7d01, 0x2126d26a, 0x29635e41, 0x3040d066, 0x4c487cc0, 0x4b4c4d4a, 0xd00b2800, 0x68203110, 
+    0xd812291f, 0x20281941, 0x68215e08, 0x19490280, 0xe0118d49, 0x19416820, 0x5e082030, 0x02806821, 
+    0x8e491949, 0x0d890589, 0x1941e007, 0x5e08202c, 0x02806821, 0x8dc91949, 0x4308b2c9, 0xfe50f7ff, 
+    0x68304601, 0x5a122244, 0x18107f00, 0x68305419, 0x77072126, 0x291f5e41, 0xf7ffda02, 0xe02bfe86, 
+    0x5a122244, 0x19d22100, 0x7f015499, 0xd30129ff, 0xe0002100, 0x77011c49, 0xfeddf7ff, 0x43ff271e, 
+    0xdd2442b8, 0x30406830, 0x28007cc0, 0x2004d017, 0xfe42f7ff, 0x07002003, 0x21ff8a81, 0x20018281, 
+    0x02406821, 0x84881949, 0x84c76830, 0xfec3f7ff, 0xb2401e40, 0xfec8f7ff, 0xfe9bf7ff, 0x203ebdf0, 
+    0xf7ff43c0, 0x2001fe29, 0xfe26f7ff, 0x6831e7ec, 0x84c82063, 0xb510bdf0, 0xfdfaf005, 0x0c02490f, 
+    0x87086809, 0x848886ca, 0xbd10844a, 0x4a09b510, 0x4b0e6811, 0x8e8918c9, 0x04492400, 0x08487004, 
+    0x18c96811, 0x43088ec9, 0x0000bd10, 0x00008b80, 0x00002001, 0x20000084, 0x0000fdff, 0x20000090, 
+    0x0001a040, 0x00007fff, 0x20000100, 0x0001a180, 0x2003b510, 0x8a810700, 0x310421ff, 0x4aff8281, 
+    0x68142100, 0x18e44bfe, 0x8a848421, 0x68148281, 0x846118e4, 0x82818a84, 0x18e46814, 0x8a8484a1, 
+    0x68108281, 0x84c118c0, 0xb510e7ce, 0xf7ff4604, 0x2103ffdf, 0x8a880709, 0x43c0201f, 0x48ef8288, 
+    0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x828a4aec, 0x140b6804, 0x18a44ae9, 0x8a8b8423, 
+    0x828b23ff, 0x68042301, 0x18a4029b, 0x8a8b84a3, 0x43db2303, 0x6800828b, 0x18802103, 0xe7a384c1, 
+    0x201fb510, 0xffd1f7ff, 0x07002003, 0x21308a81, 0x828143c9, 0x221049d9, 0x240d680b, 0x191b0364, 
+    0x8a82845a, 0x82824ad8, 0x68092001, 0x4ad70280, 0x84481889, 0xb5f8e788, 0x21264ed5, 0x5e416830, 
+    0xb24d120c, 0x311f4629, 0xd204293f, 0xdc022c1f, 0x42cc211f, 0x2201da09, 0x03d2b2e1, 0x82811889, 
+    0x70443080, 0x20017085, 0xf7ffbdf8, 0x6831fe04, 0x76483140, 0xf7ff4628, 0xf7fffe07, 0x6831ffc1, 
+    0x5c402053, 0xd00e2800, 0x27102003, 0x22ff0700, 0x42fc4bba, 0x0067da09, 0x84cf3740, 0x82828a87, 
+    0x02522201, 0x84cce00a, 0x2c0fe00f, 0x0067dd0b, 0x84cf3f3c, 0x82828a87, 0x02d22201, 0x48b0681b, 
+    0x84821818, 0x0060e001, 0x8cc884c8, 0xf7ffb240, 0x4668fd43, 0xff2af7ff, 0xff1df7ff, 0xfda9f7ff, 
+    0x21016830, 0x30808281, 0x70857044, 0xbdf82000, 0x4ca2b5f0, 0x230d6821, 0x18c9035b, 0x4aa48a89, 
+    0x68151209, 0x5d522277, 0x18511809, 0xb2490049, 0x22031049, 0x8a960712, 0x360c4e9a, 0x26018296, 
+    0x03766827, 0x813e18ff, 0x4e97060f, 0x82968a97, 0x6827d505, 0x18ff2600, 0x4249813e, 0x2601e004, 
+    0x02b66827, 0x813e18ff, 0x267f8a96, 0x829643f6, 0x26016827, 0x813e18ff, 0xe00a2600, 0x4c8d8a94, 
+    0x4f868294, 0x683f2401, 0x18ff0264, 0x1c76813c, 0x428eb276, 0x3540dbf2, 0xbdf07428, 0x4d7fb5f0, 
+    0x260d6829, 0x19890376, 0x24038a89, 0x00401808, 0x1040b240, 0x8aa10724, 0x310c497a, 0x210182a1, 
+    0x0389682a, 0x81111992, 0x21000603, 0x4a762b00, 0x82a28aa3, 0x682ada04, 0x81111992, 0xe0044240, 
+    0x682b2201, 0x199b0292, 0x4a71811a, 0x68124f71, 0x7b933240, 0x02522201, 0xd0132b00, 0x217f8aa1, 
+    0x82a143c9, 0x2101682b, 0x8119199b, 0xe0062100, 0x82a78aa3, 0x199b682b, 0x1c49811a, 0x4281b249, 
+    0xbdf0dbf6, 0x4b648aa3, 0x064082a3, 0x0e402301, 0x18c002db, 0x199b682b, 0x8aa08118, 0x682882a7, 
+    0x81021980, 0x485c8aa0, 0x82a0307f, 0x19806828, 0xbdf08101, 0x1040300f, 0xb5104770, 0x07092103, 
+    0x138a8a8a, 0x05c0828a, 0x0dc02211, 0x18830252, 0x68144a4a, 0x1824484a, 0x8a8b82e3, 0x828b4b4f, 
+    0x1c596812, 0x82c11810, 0xb510e66e, 0x07092103, 0x138a8a8a, 0x05c0828a, 0x0dc02209, 0x18830292, 
+    0x68144a3e, 0x1824483e, 0x8a8b82e3, 0x828b4b43, 0x1c596812, 0x82c11810, 0xb510e656, 0x68204c3c, 
+    0x46017dc2, 0x31400753, 0xda142b00, 0xd40d0792, 0x56412181, 0x1048310f, 0xffd7f7ff, 0x20826821, 
+    0x300f5608, 0xf7ff1040, 0xe00dffb8, 0x5608200f, 0xff54f7ff, 0x2019e008, 0xf7ff5608, 0x6821fcd5, 
+    0x56082050, 0xff04f7ff, 0x7dc06820, 0xd50c0700, 0x07002003, 0x21088a81, 0x828143c9, 0x2008491f, 
+    0x4a1f6809, 0x18893240, 0xe61d8008, 0x4606b570, 0xfbfef005, 0x46044d1e, 0x30226828, 0xff2af005, 
+    0x20104601, 0x1a6041c1, 0x682d6030, 0x30364628, 0xff20f005, 0x20104601, 0x481941c1, 0x1a617c6a, 
+    0x2a057c40, 0x0440d004, 0xd2034288, 0xbd702001, 0xe7f901c0, 0xbd702000, 0x480db5f8, 0x8a806800, 
+    0xd42f0400, 0x07362603, 0x4f0e8ab0, 0x4c0382b7, 0x68222120, 0x0340200d, 0xe0151810, 0x20000084, 
+    0x0001a040, 0x00008ff3, 0x0000fbff, 0x0001a180, 0x20000090, 0x0000fdff, 0x0000f780, 0x00007fff, 
+    0x20000200, 0x0000ffdf, 0x46688441, 0xffaef7ff, 0x28012500, 0x8ab0d007, 0x682182b7, 0x0340200d, 
+    0x84451808, 0xf7ffbdf8, 0x48ffff68, 0x68002101, 0x21537441, 0x29005c09, 0x2281d00e, 0x4afb5611, 
+    0x291f3110, 0xd80a6821, 0x23281889, 0x02995ecb, 0x189a6823, 0xe0098d52, 0x83458305, 0x188be00b, 
+    0x5e59212c, 0x02896823, 0x8dd2189a, 0x4311b2d2, 0x83020c0a, 0x49ee8341, 0xbdf88281, 0x4feab5f8, 
+    0x68394dec, 0x31a04eec, 0x4cec7848, 0xd10707c0, 0x48eb8aa8, 0x200182a8, 0x02c06832, 0x81101912, 
+    0x70c82000, 0xfc20f7ff, 0x30a06838, 0x06407840, 0x28060f40, 0x2100d113, 0xf0022001, 0x2100fe0e, 
+    0xf0022002, 0x2100fe0a, 0xf0022003, 0x2100fe06, 0xf0022004, 0x2100fe02, 0xf0022005, 0x6831fdfe, 
+    0x180848d6, 0xf7ff8b84, 0x2c28fd73, 0x2c50d043, 0x2c78d043, 0x2ca0d043, 0x2cc8d043, 0x2cf0d043, 
+    0x2000d043, 0x21838aa9, 0x683282a9, 0x48c70201, 0x84d11812, 0x49cb8aa9, 0x49cb82a9, 0x18126832, 
+    0x8aa98411, 0x82a921ff, 0x68322101, 0x18120289, 0x8aa98491, 0x43c92180, 0x683382a9, 0x49bf2280, 
+    0x841a185b, 0x43d38aab, 0x683382ab, 0x84c21818, 0x201f8aa8, 0x82a843c0, 0x200c6832, 0x85481851, 
+    0x21a16838, 0x22065c09, 0x0f490709, 0x408c1a51, 0x84843080, 0x2001bdf8, 0x2003e7c4, 0x2005e7c2, 
+    0x2007e7c0, 0x2009e7be, 0x200be7bc, 0xb500e7ba, 0x230049a5, 0x43db6809, 0x32a0460a, 0x840b70d0, 
+    0x70932302, 0x31402200, 0xf7ff75ca, 0xf7fffb9d, 0xbd00fb70, 0x2100489c, 0x77016800, 0x82817581, 
+    0x5c0921a1, 0x09ca3080, 0x2a008c81, 0x0049d000, 0x200084c1, 0xb500e7db, 0x23004993, 0x43db6809, 
+    0x32a0460a, 0x840b70d0, 0x70932302, 0x31402200, 0xf7ff75ca, 0xf7fffb79, 0xbd00fb4c, 0x4614b510, 
+    0xd0091a41, 0x1b1a0040, 0xf0054350, 0x1c40fdfe, 0x18201040, 0xe4c7b200, 0x0fc118d0, 0x10401808, 
+    0xb5f1e7f8, 0x21a14f80, 0x26016838, 0x25005c09, 0x0709468c, 0x46310f4a, 0xb24c4091, 0x7d827f01, 
+    0x4291b082, 0x1a8bd301, 0x23ffe002, 0x185b1a9b, 0x8283b29b, 0xd30129ff, 0xe0002700, 0xb2ff1c4f, 
+    0x42ba9700, 0x2701d103, 0x433b03bf, 0x42918283, 0x8a81d104, 0x03522201, 0x82814311, 0x9a02211f, 
+    0x4f6e43c9, 0xd1232a01, 0x8cc03080, 0xd11f2800, 0x09c04660, 0x4660d01c, 0xd00007c0, 0x46082120, 
+    0xfa8af7ff, 0x8a814863, 0x82814968, 0x2201485e, 0x02926800, 0x784130a0, 0x17c907c9, 0x188a0289, 
+    0x6809495d, 0x810a19c9, 0x06497841, 0x70410e49, 0x68014859, 0x18084859, 0x4b538f80, 0x68180ac2, 
+    0x31804601, 0x8cc9728a, 0xd0752900, 0xd1732a07, 0x29fb7d01, 0x4950d270, 0x494c680a, 0x27301851, 
+    0x46025fcf, 0x789132a0, 0xd80f2904, 0x56d32303, 0x2f002006, 0x1a41db03, 0x40884630, 0x1a41e003, 
+    0x40884630, 0x18184240, 0xe04370d0, 0x43db2300, 0xd00b2905, 0xdd112f00, 0x5e412120, 0xdb1f2900, 
+    0x56512103, 0xda17291f, 0xe0131c49, 0x56102003, 0xdb002f00, 0x18c02301, 0xe02870d0, 0xda0f2f00, 
+    0x5e412120, 0xdc152900, 0x56512103, 0x42d9231f, 0x1e49dd02, 0xe01a70d1, 0x75c63040, 0xe016014d, 
+    0x56512103, 0x461a014b, 0x25203220, 0x46395f45, 0xe0054628, 0x56102003, 0x46130142, 0x46383b20, 
+    0xff2cf7ff, 0x48204605, 0x30406800, 0x481e75c6, 0x84076800, 0x6800481c, 0x31a04601, 0x4607788a, 
+    0x708a1c52, 0x7dfa3740, 0xd0062a01, 0x56082003, 0xfa8af7ff, 0xfa5df7ff, 0x88babdfe, 0x18d37f03, 
+    0x54d54a1b, 0x77029a00, 0xd3012aff, 0xe0002300, 0x88bf1c53, 0x18bf042d, 0x0e2d4a15, 0x770355d5, 
+    0x8cc23080, 0xb2931e52, 0x220084c3, 0x9d0270ca, 0x2d014a10, 0x784dd032, 0xd02609ed, 0x42838c80, 
+    0x4804d123, 0xe0178a83, 0x20000090, 0x0001a040, 0x0000ec01, 0x30000000, 0x20000084, 0x0001a000, 
+    0x0000f7ff, 0x00000ff3, 0x0000b00c, 0x0000fbff, 0x20000100, 0x0000fdff, 0x43db237c, 0x48ff8283, 
+    0x68052304, 0x182848fe, 0x250384c3, 0x8aa8072d, 0x82a848fc, 0xdd1d2c00, 0xe01c2001, 0x250d2303, 
+    0x071b2000, 0x2601036d, 0xe0070276, 0x829a8a9c, 0x68244cf2, 0x81261964, 0xb2c01c40, 0x0764784c, 
+    0x24010fa7, 0x428440bc, 0x2003dcf0, 0xf7ff5608, 0xbdfefe92, 0x4bec2000, 0x43180280, 0x681e4be7, 
+    0x037f270d, 0x813019f6, 0x20002201, 0x42660252, 0x8aabe008, 0x82ab4be5, 0x681b4be0, 0x811a19db, 
+    0xb2c01c40, 0xdb012c00, 0xe0004623, 0x42834633, 0x2003dcef, 0xf7ff5608, 0xbdfefe4a, 0x4edcb5f0, 
+    0x68302400, 0x82847584, 0xfb62f7ff, 0x072d2503, 0x20038aa8, 0x4fd182a8, 0x49d16838, 0x84c41840, 
+    0x30a06830, 0x462070c4, 0xf9def7ff, 0x48cd8aa8, 0x683982a8, 0x0340200d, 0x810c1809, 0x49cd8aa9, 
+    0x683982a9, 0x81041808, 0xb500bdf0, 0x200049c8, 0x31a06809, 0xf7ff70c8, 0xbd00f9c7, 0x4cc4b510, 
+    0x68202100, 0x75817701, 0x21028281, 0x708130a0, 0x07c07840, 0x2020d001, 0x201fe001, 0xf7ff43c0, 
+    0x2003f91b, 0x8a810700, 0x828149bb, 0x23016820, 0x30a04602, 0x029b7841, 0x17c907c9, 0x18c90289, 
+    0x681b4bae, 0x0364240d, 0x8119191b, 0x23807841, 0x70414319, 0x0f810748, 0x40c82040, 0x84d03280, 
+    0xf7ff2000, 0xe47ffe08, 0xf7ffb530, 0x4da8f984, 0x31406829, 0x201f7648, 0xf986f7ff, 0x6828211e, 
+    0x84c143c9, 0x7cc03040, 0xd01d2800, 0xf7ff2002, 0x6828f8e3, 0x85042400, 0x75847704, 0xf7ff201f, 
+    0x6828fb04, 0x5c092153, 0xd00b2900, 0x07092103, 0x22ff8a8a, 0x4a91828a, 0x68122101, 0x4b900249, 
+    0x849118d2, 0xbd308284, 0x43c0201f, 0xf8c4f7ff, 0xe7dc2001, 0x4604b510, 0xfacaf7ff, 0x07092103, 
+    0x201f8a88, 0x828843c0, 0x06e24884, 0x0ed26803, 0x0364240d, 0x855a191b, 0x4a888a8a, 0x4b88828a, 
+    0x4a7f6804, 0x842318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 0x84811880, 0xb500e426, 0xf92bf7ff, 
+    0x2259497b, 0x54506809, 0x77082000, 0x201c7588, 0xffd0f7ff, 0xb510bd00, 0xfc2ff7ff, 0xfa98f7ff, 
+    0x07092103, 0x20308a88, 0x828843c0, 0x20004a6b, 0x240d6813, 0x191b0364, 0x8a8b8458, 0x828b4b6e, 
+    0x4a706811, 0x84481889, 0x68094969, 0x758875c8, 0xe4118288, 0x2300b510, 0xd01c2800, 0x22004c6a, 
+    0xd90042a0, 0x1c524620, 0xb2520040, 0xdafa2800, 0x0ee417d4, 0x096418a4, 0x1b120164, 0x1aa2241f, 
+    0x700ab2d2, 0xd2092a08, 0x06000e00, 0x40d01aa2, 0x700bb2c0, 0x700be429, 0xe4262000, 0x1fd20e00, 
+    0xe422700a, 0x2403b5f0, 0x8aa10724, 0x82a1494d, 0xdd012800, 0xe0002101, 0x4a542100, 0x4e470289, 
+    0x68321889, 0x037f270d, 0x811119d2, 0x21002301, 0x4245025b, 0x8aa2e007, 0x82a24a44, 0x19d26832, 
+    0x1c498113, 0x2800b249, 0x4602db01, 0x462ae000, 0xdcf0428a, 0xb5f0bdf0, 0x2200270e, 0x4e444d37, 
+    0x4c3b43ff, 0x2900230f, 0x2800d016, 0x4610d009, 0x6829e009, 0x88891989, 0x16890689, 0x84c11a79, 
+    0x461fbdf0, 0xf7ff4618, 0x6820fb90, 0x09097dc1, 0x078943c9, 0xbdf0d1ed, 0xd0012800, 0xe0014610, 
+    0x4618461f, 0xfb69f7ff, 0x19806828, 0x68218840, 0x16800680, 0x84c81a38, 0x0040bdf0, 0xb240380f, 
+    0xb5304770, 0x20004c22, 0x4a1c6821, 0x68108508, 0x18c04b27, 0x06808880, 0xf7ff1680, 0x6821ffee, 
+    0x70483180, 0x18c06810, 0x06808840, 0xf7ff1680, 0x6821ffe4, 0x460b2201, 0x70983380, 0x2a00569a, 
+    0x4615db01, 0x4255e000, 0xdb012800, 0xe0004603, 0x429d4243, 0x8d0bdd03, 0x432b2504, 0x2a00850b, 
+    0x8d0add03, 0x431a2302, 0x2800850a, 0x8d08dd03, 0x43102201, 0x7dca8508, 0xe01b0690, 0x20000084, 
+    0x0001a040, 0x00008b80, 0x00007001, 0x0000fdff, 0x20000090, 0x0000f7ff, 0x0000fbff, 0x00000ff3, 
+    0x0000b00c, 0x0001a180, 0x007fffff, 0x00004001, 0x0001a280, 0xd0130f80, 0xd0202801, 0xd0212802, 
+    0xd10c2803, 0x21018d08, 0x0fc00780, 0xff63f7ff, 0x8d006820, 0x0fc007c0, 0xf7ff2100, 0xbd30ff5c, 
+    0x5e082028, 0xdb012804, 0xe0002101, 0x28042100, 0x0780db02, 0xe7f00fc0, 0x0fc007c0, 0x07d0e7ed, 
+    0xe7e90fc0, 0x0fc007d0, 0xe7e62101, 0xf7feb5f8, 0x4cfefff2, 0x68212259, 0x54502700, 0x7dc8828f, 
+    0x07034dfd, 0x4afb48fa, 0x8aab4efc, 0xd50382a8, 0x18806830, 0xe0038007, 0x20086833, 0x8010189a, 
+    0x07407dc8, 0x00030f40, 0xfb3cf005, 0x1b0e0508, 0x5e43432f, 0x201f4566, 0xffd6f7fe, 0x20506821, 
+    0xf7ff5608, 0xe018fa05, 0x43c0201e, 0xffccf7fe, 0x20506821, 0xf7ff5608, 0xe021f9fb, 0x84c86821, 
+    0x2000e029, 0xffc0f7fe, 0x30406820, 0x28007cc0, 0x2001d005, 0xf7fe43c0, 0x201fff1f, 0x2020e7ee, 
+    0xff1af7fe, 0x43c02000, 0x2000e7f5, 0xffacf7fe, 0x30406820, 0x28007cc0, 0x2002d005, 0xff0cf7fe, 
+    0x43c0201e, 0x201fe7da, 0xf7fe43c0, 0x2001ff05, 0xf7ffe7f4, 0x6820ff16, 0x07407dc0, 0xf7ffd42b, 
+    0x6820f94f, 0x5c092153, 0xd0222900, 0x07817dc0, 0x49c8d51f, 0x20ff07c2, 0x2a003940, 0x82a88aaa, 
+    0x2001d012, 0xe0110240, 0xf7ff2020, 0x2000fe9b, 0xf7ff43c0, 0xe7c0fe97, 0x43c0201f, 0xfe92f7ff, 
+    0xf7ff2001, 0xe7cbfe8f, 0x02c02001, 0x18516832, 0xf7fe8488, 0xf7ffff3e, 0x6820f8ae, 0xf7ff305e, 
+    0x6820f8b5, 0x77077587, 0x87878747, 0xb510bdf8, 0xfe9ef004, 0x680949ad, 0x0c008488, 0xe5c28448, 
+    0x4606b57c, 0x46696808, 0xf7ff08c0, 0x4da7fe43, 0x68292244, 0x5a524caa, 0x18d27f0b, 0x7f0854a0, 
+    0xd30128ff, 0xe00020ff, 0x77081c40, 0x6830a901, 0xfe30f7ff, 0x78094669, 0x4669010a, 0x430a7909, 
+    0x460b6829, 0x889d3340, 0x19ad7f0e, 0x7f0a5562, 0xd3012aff, 0xe00022ff, 0xb2d21c52, 0x889b770a, 
+    0x54a0189a, 0x28ff7f08, 0x20ffd301, 0x1c40e000, 0xbd7c7708, 0x4a8db570, 0x6814230e, 0x84e32500, 
+    0x4c904b8e, 0xd02b2900, 0x68182800, 0x1900d011, 0x06808880, 0xf7ff1680, 0x6811fe80, 0x578e2681, 
+    0xda1a42b0, 0x19006818, 0x06808880, 0x1c401680, 0x1900e010, 0x06808880, 0xf7ff1680, 0x6811fe6e, 
+    0x578e2681, 0xdd0842b0, 0x19006818, 0x06808880, 0x1e401680, 0xf9d9f7ff, 0x6810bd70, 0xbd7084c5, 
+    0x68182800, 0x1900d011, 0x06808840, 0xf7ff1680, 0x6811fe54, 0x578e2682, 0xdaee42b0, 0x19006818, 
+    0x06808840, 0x1c401680, 0x1900e010, 0x06808840, 0xf7ff1680, 0x6811fe42, 0x578e2682, 0xdddc42b0, 
+    0x19006818, 0x06808840, 0x1e401680, 0xf995f7ff, 0xb5f0bd70, 0x2000b085, 0x4f5c4669, 0x68387208, 
+    0x04098a81, 0x4d5cd47e, 0x21208aa9, 0x82a943c9, 0x21204c5a, 0x260d6822, 0x19920376, 0x21538451, 
+    0x29005c09, 0x2126d012, 0x31105e41, 0xd902291f, 0x07807dc0, 0x6820d40e, 0x3940494e, 0x20281842, 
+    0x68225e10, 0x18510280, 0xe00d8d49, 0xf7fea802, 0xe00bffdd, 0x49476820, 0x18423940, 0x5e10202c, 
+    0x02806822, 0x8dc91851, 0x4308b2c9, 0xa8019000, 0xf9bcf7ff, 0x483d9003, 0x46386807, 0xf005303a, 
+    0x2110f8e9, 0x990041c8, 0x42881840, 0x2000d201, 0x990343c0, 0x29019000, 0x8cf9d021, 0xd01e2900, 
+    0x7c894939, 0x42810109, 0x2227d276, 0x02129901, 0xd8054291, 0x42914a35, 0x7df9d96e, 0xd56b0649, 
+    0x4668a901, 0xfefcf7ff, 0x68114a28, 0x07d87dcb, 0x5e08482f, 0x2800d020, 0x1c40da1c, 0xa901e01f, 
+    0xf7ff4668, 0x4668feed, 0x28007a00, 0x2000d010, 0x03802101, 0x184103c9, 0x03409803, 0x481b4301, 
+    0xe0006800, 0x7f02e002, 0x82814311, 0xbdf0b005, 0xe7ed2001, 0xe0022000, 0xddfb2800, 0x84c81e40, 
+    0xd5590798, 0x5c472053, 0x4a1a2001, 0x2f000240, 0x075fd001, 0x8aa9d505, 0x682182aa, 0x81081989, 
+    0x07dbe07f, 0x2b0027ff, 0x2326d02c, 0x33105ecb, 0x203ed12b, 0xf7fe43c0, 0x2001fd6f, 0xfd6cf7fe, 
+    0x82af8aa8, 0x02892101, 0xe0166822, 0x20000090, 0x0000fff7, 0x0001a080, 0x30000000, 0x20000084, 
+    0x20000100, 0x0001a280, 0x20000200, 0x000007cc, 0x00000026, 0x0000fdff, 0x48fee070, 0x18103840, 
+    0xe04e8481, 0x290f8cc9, 0x8aa9d005, 0x682182aa, 0x81081989, 0x203fe7bf, 0xfd3ef7fe, 0x43c02000, 
+    0xfd3af7fe, 0x82af8aa8, 0x68222001, 0x49f10280, 0x18513940, 0xe0348488, 0x07584fef, 0x0698d52d, 
+    0xd0060f80, 0xd0152801, 0xd0162802, 0xd1282803, 0x2028e017, 0x28045e08, 0x2101db01, 0x2100e000, 
+    0xdb022803, 0x0fc00780, 0x07c0e001, 0xf7ff0fc0, 0xe016fe91, 0x0fc007d8, 0x07d8e00d, 0x21010fc0, 
+    0x8d08e7f5, 0x07802101, 0xf7ff0fc0, 0x6838fe83, 0x07c08d00, 0x21000fc0, 0x8cc8e7e9, 0xf7feb240, 
+    0xf7fffd93, 0x48d4fe34, 0x68002700, 0x87878747, 0xfd5ff7fe, 0xf7fea802, 0x9000fed9, 0x20208aa8, 
+    0x82a843c0, 0x19806820, 0x48cb8447, 0x8cc16800, 0x06497f02, 0x430a0c49, 0xe7478282, 0x87790c01, 
+    0xf7fe87b8, 0x8aa8fd46, 0x43c02020, 0x682182a8, 0x19892000, 0xe7e88448, 0x2003b5f0, 0x8a810700, 
+    0x828149be, 0x220049be, 0x230d680c, 0x18e4035b, 0x8a848062, 0x82862601, 0x680d2469, 0x18ed0124, 
+    0x8a8480ac, 0x82841e94, 0x18e4680c, 0x8a8480e2, 0x82844cb4, 0x18e4680c, 0x8a848122, 0x82844cb2, 
+    0x18e4680c, 0x8a848422, 0x82854db0, 0x18e4680c, 0x8a848462, 0x82844cae, 0x10dc680f, 0x853c18ff, 
+    0x241f8a84, 0x828443e4, 0x240d680f, 0x857c18ff, 0x4ca88a84, 0x680c8284, 0x861e18e3, 0x4ba68a83, 
+    0x680c8283, 0x3b404b9b, 0x802218e4, 0x4ea38a84, 0x680c8286, 0x806218e4, 0x82868a84, 0x18e4680c, 
+    0x8a8480a2, 0x82841cb4, 0x18f6680e, 0x8a8680f2, 0x680e8284, 0x813218f6, 0x82848a86, 0x18e4680c, 
+    0x8a848162, 0x82844c96, 0x18e4680c, 0x8a8481a2, 0x43e424c0, 0x680e8284, 0x18f62440, 0x8a8481f4, 
+    0x03a42401, 0x680c8284, 0x82e218e4, 0x24ff8a84, 0x82843404, 0x18e4680c, 0x8a848422, 0x680c8282, 
+    0x846218e4, 0x82828a84, 0x18e4680c, 0x8a8484a2, 0x680c8282, 0x84da18e3, 0x23198a83, 0x828343db, 
+    0x2310680e, 0x19364c73, 0x8a838033, 0x33294b77, 0x680f8283, 0x193f2604, 0x8a86843e, 0x680e8283, 
+    0x85221934, 0x82828a84, 0x4c6a680e, 0x19363440, 0x8a868032, 0x680e8282, 0x80721936, 0x82838a86, 
+    0x191b680b, 0x8a83809a, 0x680b8285, 0x34804c61, 0x84da191b, 0x4b678a83, 0x82833bf1, 0x49696808, 
+    0x84421840, 0x2103bdf0, 0x8a8a0709, 0x828a2200, 0x0200495b, 0x220d6809, 0x18890352, 0x83483080, 
+    0x22034770, 0x8a930712, 0x8293233f, 0x01000709, 0x43080f09, 0x21800200, 0x43083040, 0x68094950, 
+    0x0352220d, 0x83481889, 0xb5104770, 0x46112200, 0xe0074c55, 0xd00207c3, 0x5ae3004b, 0x1c49405a, 
+    0x0840b289, 0xd1f52800, 0xe5184610, 0x4844b5f0, 0x68004d46, 0x210d3530, 0x18400349, 0x27008b86, 
+    0xe009463c, 0x0a295d38, 0xf7ff4048, 0x0229ffde, 0x1c644048, 0xb2a4b285, 0xd3f342b4, 0xbdf04628, 
+    0x4e37b5fe, 0x270d6831, 0x19c9037f, 0x4a328b49, 0x68140a09, 0x46222500, 0x92013280, 0x00034a3b, 
+    0x00d27d52, 0x46229200, 0x920232a0, 0xf0043a60, 0x0e19ff99, 0x72181819, 0xf6f7f89a, 0xf2f3f4f5, 
+    0xeff018f1, 0xebecedee, 0xe918ea18, 0x20030018, 0x8a810700, 0x43c921c0, 0x68318281, 0x19c92080, 
+    0xbdfe8348, 0xd0052900, 0xd00c2901, 0xd0142902, 0xe2652101, 0x28007c90, 0x2001d0f3, 0x98017460, 
+    0x7c802101, 0x9801e024, 0x7c804c13, 0xf0042101, 0x6821fc48, 0x74482001, 0x7a50e24e, 0x43082101, 
+    0x74657250, 0xfb60f7fd, 0x19c06830, 0x07c08e80, 0x2003d009, 0x8a810700, 0x43c92120, 0x68318281, 
+    0x19c92020, 0x48048408, 0x30806800, 0x21007c80, 0x0000e01e, 0x0001a080, 0x20000090, 0x0000f87f, 
+    0x20000084, 0x00008180, 0x0000bf1f, 0x0000ffcf, 0x000083ff, 0x0000fcf0, 0x00003fff, 0x000013fd, 
+    0x0000c0c0, 0x0001a180, 0x00007bac, 0x20000200, 0xfc07f004, 0x2900e210, 0x2901d006, 0x2902d00b, 
+    0x2903d013, 0xe017d1b8, 0x07002003, 0x82858a81, 0xfb05f004, 0x2003e005, 0x8a810700, 0xf0048285, 
+    0x6831fafa, 0x838819c9, 0x2003e1f6, 0x8a810700, 0x98018285, 0xe7f47c80, 0x07002003, 0x82858a81, 
+    0xfb17f004, 0x1e89e7ed, 0xf004000b, 0x2405fefb, 0x056d5b31, 0xe7740004, 0x29027c61, 0x7cd3d26a, 
+    0xd86f2b01, 0x2b007c93, 0x2900d101, 0x7611d0f3, 0x19c06830, 0x84e08b80, 0xfd5df7fe, 0xd0010001, 
+    0xe0602006, 0x210548fe, 0x74416800, 0x07092103, 0x828d8a8a, 0x7c90e117, 0xd1022800, 0x28007c60, 
+    0x7c60d0d9, 0x20017610, 0xf7ff7460, 0xe1b3fa36, 0x21017a50, 0x72504308, 0x4ef17c60, 0xd30a2802, 
+    0x4cf148f0, 0x20ff6005, 0x81208160, 0x48ef1c41, 0xfdccf004, 0xf7ff7565, 0x6830fa2e, 0x5c092158, 
+    0xe1997441, 0xe12fe163, 0xe0eee127, 0xe0f2e107, 0xe069e0b3, 0xe053e05f, 0xe044e04a, 0xe03ae03e, 
+    0xe031e034, 0x28027c60, 0x7cd1d211, 0xd8192901, 0x29007c91, 0x2800d101, 0x49dbd09d, 0x75482001, 
+    0x76107c60, 0xe0192002, 0x28027c60, 0x9900d303, 0xb2c94301, 0x7cd1e099, 0xd8032901, 0x29007c91, 
+    0xe003d106, 0xf7ffe09e, 0xbdfefe8c, 0xd0fc2800, 0x210148cd, 0x7c607541, 0x20037610, 0xf7ff7460, 
+    0xf7fef983, 0xe157fae6, 0xe01f5c60, 0x19c06830, 0x54608b80, 0x48c4e150, 0xe0175c40, 0x19c06830, 
+    0x4ac18b80, 0x1860e01e, 0x02027840, 0xe00c5c60, 0x19c06830, 0x54608b80, 0x18610a00, 0xe13b7048, 
+    0x184248b9, 0x5c407852, 0x43100212, 0x07092103, 0x828d8a8a, 0x6830e735, 0x8b8019c0, 0x0a034ab2, 
+    0x70631854, 0xe1275450, 0x28027c60, 0x2900d242, 0x2901d00f, 0x2902d021, 0x48abd1b7, 0x754549a9, 
+    0x21ff600d, 0x81018141, 0x48a81c49, 0xfd3ef004, 0x2300e02c, 0x461a9500, 0x20022111, 0xf0049501, 
+    0x49a1fc2c, 0x75482001, 0x81088948, 0xd00228ff, 0x81081c40, 0x2000e100, 0x4a9be7fb, 0x8911489b, 
+    0x5c408953, 0xd1034299, 0x310121ff, 0xe0034308, 0xd00d29ff, 0x81111c49, 0x07092103, 0x828d8a8a, 
+    0xb2c16832, 0x839119d2, 0xd0570a00, 0xe0712001, 0xe7f02100, 0x20052100, 0x7c60e775, 0x28024684, 
+    0x9800d305, 0x43084661, 0x200cb2c1, 0x0748e76b, 0x6833d505, 0x181b4886, 0x07db8e5b, 0x7cd0d005, 
+    0xd9092801, 0x200d2102, 0x6831e75d, 0x8e401808, 0x0fc907c1, 0xe7562008, 0x28007c90, 0x4660d103, 
+    0xd1002800, 0x4b78e751, 0x75582001, 0x76107c60, 0x74602004, 0xf7ff75e1, 0x2003fa69, 0x8a810700, 
+    0x486f8285, 0x8cc06800, 0x7a50e6ab, 0x43082101, 0x72504e6b, 0x8890e6f4, 0x18417da1, 0x5c40486b, 
+    0x07092103, 0x828d8a8a, 0x19c96831, 0x7da08388, 0xd30128ff, 0xe0002000, 0x75a01c40, 0x8891e08c, 
+    0x4a627da0, 0x5cd3180b, 0xd30128ff, 0xe0002000, 0xb2c01c40, 0x180975a0, 0x28ff5c51, 0x2000d301, 
+    0x1c40e000, 0x200375a0, 0x8a820700, 0x02188285, 0xe6764308, 0xfd87f7ff, 0x2003bdfe, 0x8a810700, 
+    0xf7ff8285, 0xe66cfdb3, 0x4e4d9802, 0x06487041, 0x28010f40, 0x2802d017, 0x2805d003, 0x2806d035, 
+    0x7c60d1ea, 0xd3002802, 0x7c91e6e1, 0xd1012900, 0xd0e12800, 0x20014944, 0x7c617548, 0x74607611, 
+    0xfdccf7fe, 0x7c60e048, 0xd0472800, 0x74602006, 0xfe60f7fe, 0x82a5e040, 0xf800f7ff, 0x46016830, 
+    0x7e0a3140, 0x30a07442, 0x760d7045, 0x6830e034, 0x8b4019c0, 0x0a009902, 0x4e317048, 0x0f400640, 
+    0x2801d012, 0x2802d021, 0x7c60d1b6, 0xd3e22802, 0x4f2d482c, 0x20ff6005, 0x81388178, 0x482b1c41, 
+    0xfc44f004, 0xe7d6757d, 0x28027c60, 0x7c91d2bc, 0xd1012900, 0xd09f2800, 0x20014923, 0x7c617548, 
+    0x74607611, 0xfff1f7fe, 0x7c60e006, 0xd0052800, 0x74602007, 0xfff2f7fe, 0xe78b2000, 0xb2c19800, 
+    0xe6902001, 0xf001b570, 0x4915fa2c, 0x68092000, 0x460b8608, 0x33808648, 0x460c7298, 0x344072d8, 
+    0x7a627220, 0x00520852, 0x72a07262, 0x732072e0, 0x4a0d73d8, 0x7f9273a0, 0x460a73e2, 0x32607420, 
+    0x711875d0, 0x87087158, 0x752086c8, 0x711075a0, 0x72587150, 0x854877e0, 0x71d07190, 0xe0097210, 
+    0x20000090, 0x20000088, 0x20000200, 0x20000100, 0x0001a180, 0x85c88588, 0x75107250, 0x755074d0, 
+    0x76507590, 0x76d07690, 0x75987710, 0x25017618, 0x806075dd, 0x76987658, 0x824876d8, 0x73887348, 
+    0x740873c8, 0x77907750, 0x701877d0, 0x71987610, 0x74188688, 0x75888288, 0x830875c8, 0xbd708348, 
+    0xf7ffb510, 0xf7fffbe9, 0x48f9ff9d, 0x79806800, 0xd10b07c0, 0x07002003, 0x210f8a81, 0x828143c9, 
+    0x200049f4, 0x4af46809, 0x80481889, 0x20012100, 0xfb33f001, 0x20022100, 0xfb2ff001, 0x20032100, 
+    0xfb2bf001, 0x20042100, 0xfb27f001, 0x20052100, 0xfb23f001, 0x48e7e4b9, 0x49e76800, 0x184031c0, 
+    0x49e68a80, 0x0f020600, 0x1ed27c08, 0xd3022a0b, 0x43102210, 0x22efe001, 0x74084010, 0xb5104770, 
+    0x07002003, 0x49de8a81, 0x49da8281, 0x680c2301, 0x4ad902db, 0x18a43280, 0x8a838523, 0x43db2340, 
+    0x680c8283, 0x18a42340, 0x4bd48423, 0x2b007bdb, 0x8a83d122, 0x82834bd3, 0x680c2301, 0x18a2035b, 
+    0x8a8284d3, 0x43d22278, 0x680c8282, 0x4aca2308, 0x18a432c0, 0x8a838023, 0x82834bcb, 0x680c2337, 
+    0x18a4019b, 0x8a8380e3, 0x33204bc6, 0x20198283, 0x01c06809, 0x81c81889, 0x4770e467, 0xf004b570, 
+    0x4abef81e, 0x290088d1, 0x08cbd014, 0x18081ac0, 0x7b1080d0, 0x28142101, 0x4bbcd20e, 0x43434dbc, 
+    0x129b195b, 0x1c5b88d4, 0x429c105b, 0x74d1dc04, 0xe00f1c40, 0xe7eb00c0, 0xd00d2800, 0x4db54bb3, 
+    0x195b4343, 0x88d4129b, 0x105b1c5b, 0xdb03429c, 0x1e4074d1, 0xbd707310, 0x74d02000, 0xb570bd70, 
+    0x48a62124, 0xfb12f004, 0x20264ca4, 0x48aa8020, 0x200980a0, 0x200b73a0, 0x73202600, 0x752674e6, 
+    0xf0037566, 0x00c0ffdc, 0x250080e0, 0xffb6f7ff, 0xb2ed1c6d, 0xd3f92d08, 0x68004896, 0x31c04996, 
+    0x8fc01840, 0x07002128, 0x73e00f00, 0x20017426, 0x75a17360, 0x75e12104, 0x76212110, 0x76a07666, 
+    0x76e02002, 0x77202003, 0x77602024, 0x77a02020, 0x77e62005, 0x842001c0, 0x0180200b, 0x21f88460, 
+    0xf004488e, 0x488efad3, 0x20ff6006, 0x81208160, 0x488a1c41, 0xfacaf004, 0xb510bd70, 0x2100487c, 
+    0x230a6800, 0x80014602, 0x71933240, 0x72c171d1, 0x73017281, 0x73817341, 0x73c17401, 0x74418241, 
+    0x71017491, 0x71c17181, 0x72417201, 0x22027741, 0x22017142, 0x30807082, 0xf7ff7201, 0xe709fe83, 
+    0x486eb530, 0x28007bc0, 0x4a6ad123, 0x4b6a6810, 0x18c033c0, 0x210f8a80, 0x0f000600, 0x20031a09, 
+    0x8a840700, 0x82844c6f, 0x6815028c, 0x18ed430c, 0x8a8484ac, 0x43e4240f, 0x68148284, 0x859918e3, 
+    0x212a8a81, 0x828143c9, 0x202a6811, 0x18894a66, 0xbd308188, 0x4d57b5f8, 0x48636829, 0x180830c0, 
+    0x4f538ac0, 0x68380701, 0x30400f09, 0x7a4174c1, 0x401122fd, 0x48517241, 0x7bc04e4f, 0x36802403, 
+    0x28000724, 0x6828d12e, 0x33c04b4b, 0x8a8018c0, 0x0600210f, 0x1a080f00, 0x49548aa1, 0x682a82a1, 
+    0x19920301, 0x8aa18511, 0x43c9210f, 0x682982a1, 0x85481989, 0x21038aa1, 0x82a143c9, 0x2103682a, 
+    0x86111992, 0x21788aa1, 0x82a143c9, 0x00c06829, 0x800818c9, 0x20028aa0, 0x82a043c0, 0x20026829, 
+    0x824818c9, 0xff20f7fc, 0x4b416838, 0x4a327801, 0x2100074f, 0xdb092f00, 0x5c3f2753, 0xd10b2f00, 
+    0x783f4f2e, 0x0eff06bf, 0xd3052f06, 0x82a38aa7, 0x189b682b, 0xe0058019, 0x82a38aa7, 0x2304682f, 
+    0x803b18bf, 0x075b7803, 0x2353d412, 0x2b005c1b, 0x4b22d10e, 0x069b781b, 0x2b0e0edb, 0x8aa3d908, 
+    0x43db2380, 0x682f82a3, 0x18ba2380, 0xe0068013, 0x23808aa3, 0x82a343db, 0x189a682b, 0x78028011, 
+    0xd5470752, 0x32404602, 0x2b007cd3, 0x4b13d142, 0x069b781b, 0x469c0edb, 0xd90d2b1a, 0x23078aa3, 
+    0x82a343db, 0x2306682f, 0x84bb19bf, 0x075b7803, 0x7cd2d530, 0xd12d2a00, 0x2a164662, 0x8aa2d92a, 
+    0x43d22202, 0x682b82a2, 0x199b2202, 0xe028859a, 0x20000090, 0x20000084, 0x0001a080, 0x20000200, 
+    0x0000f7ff, 0x0000dfff, 0x0000c03f, 0xfffc5699, 0x00d3f7e6, 0x00da605a, 0x0000d102, 0x20000100, 
+    0x20000088, 0x0000c3f0, 0x0001a240, 0x00000fff, 0x0000fffb, 0x22028aa2, 0x82a243d2, 0x1992682a, 
+    0x78028591, 0x4afc0753, 0x82a28aa3, 0x2201d505, 0x02d2682b, 0x855a199b, 0x682ae002, 0x85511992, 
+    0x32ff682a, 0x8d923201, 0x07924ef4, 0x46020fd3, 0x75533280, 0x4ff22b00, 0x82a68aa3, 0x231bd002, 
+    0xe001015b, 0x015b2311, 0x19f6682e, 0x7d528033, 0xd0092a00, 0x4aeb8aa2, 0x230782a2, 0x02db682e, 
+    0x3a404ae7, 0x815318b2, 0x4ae78aa2, 0x682f82a2, 0x260d2301, 0x19bf0376, 0x3040807b, 0x48df7cc7, 
+    0x30e01ebf, 0xf004003b, 0x0508fa4d, 0x0a0a0505, 0x120a0505, 0x82a08aa3, 0x300120ff, 0x8aa3e003, 
+    0x200182a0, 0x682b0240, 0x80d8199b, 0x8aa3e004, 0x682882a0, 0x80c11980, 0x48d4682b, 0x8ec01818, 
+    0x0f000700, 0xd00e2801, 0x8aa02804, 0x82a048d0, 0x48d0682b, 0x181bd010, 0x8aa38019, 0x682a82a2, 
+    0x80411810, 0x8aa0bdf8, 0x82a048c9, 0x2380682e, 0x183648c8, 0xe7f08033, 0x8019181b, 0x82a28aa1, 
+    0xe7ec2101, 0x201fb5f8, 0xfd80f001, 0xfb04f001, 0x26034dc1, 0x31606829, 0x07367008, 0x20098ab0, 
+    0x82b043c0, 0x210848bd, 0x4cba6800, 0x19003cc0, 0x20008001, 0xfe98f7fd, 0x22006828, 0x31404601, 
+    0x4db77ccf, 0xf004003b, 0x0d09f9ed, 0x3406340b, 0x06340634, 0x232a0034, 0x231573cb, 0xe00d740b, 
+    0xe00a73ca, 0x061f7903, 0x065bd502, 0xe0030e5b, 0x075b7803, 0x7f6bd51d, 0x740a73cb, 0x75c23060, 
+    0x4fa5200f, 0xf7fe5608, 0x6839f8e9, 0x56082050, 0xf89ef7fe, 0x78006838, 0xd5170740, 0xfdecf001, 
+    0x78016838, 0xd5110749, 0x7cc03040, 0xd0022801, 0x7fabe00c, 0x8ab0e7e0, 0x43c02030, 0x489782b0, 
+    0x68002130, 0x3a404a93, 0x84c11880, 0x20208ab0, 0x82b043c0, 0x20204991, 0x230d680a, 0x18d2035b, 
+    0x68388410, 0x46032201, 0x739a3340, 0x469c7fef, 0x063b4a8c, 0x8ab0d507, 0x067882b2, 0x0e406809, 
+    0x80481909, 0x8807bdf8, 0xd4fb063b, 0x07db7983, 0x077fd1f8, 0x2f002307, 0x2795da0f, 0x2f005c3f, 
+    0x782fd00b, 0x0eff06bf, 0xd9062f16, 0x82b28ab3, 0x220a680b, 0x805a191b, 0x8ab7e004, 0x680a82b2, 
+    0x80531912, 0x7cd24662, 0xd1db2a01, 0x06807800, 0x28020f80, 0x7828d0d6, 0x0ec00680, 0xd9d12816, 
+    0x20078ab0, 0x82b043c0, 0x20046809, 0x80881909, 0xb510bdf8, 0x68204c68, 0x78003060, 0xfcc6f001, 
+    0x20616821, 0xf7fd5608, 0x6821fdef, 0x31402000, 0x200f7388, 0xf7fe5608, 0x6821f861, 0x56082050, 
+    0xf816f7fe, 0x07002003, 0x21208a81, 0x828143c9, 0x2020495a, 0x220d6809, 0x18890352, 0x68208408, 
+    0x30402101, 0xe4a57381, 0x4d54b570, 0x4e566828, 0x8ec11980, 0x19806828, 0x048a8f00, 0x0f52054b, 
+    0x18d20f5b, 0x08520689, 0x18510e89, 0x0f530482, 0x0ed206c2, 0x0984189b, 0xd00007e4, 0x0544425b, 
+    0x18a20f64, 0x07c00940, 0x4252d000, 0x10431898, 0x19806828, 0x06808f40, 0x68281684, 0x8f401980, 
+    0x16c20540, 0x19856828, 0x5e28203a, 0x290012c0, 0x4249da00, 0xda002b00, 0x18c9425b, 0xda002c00, 
+    0x19094264, 0xda002a00, 0x18894252, 0xda002800, 0x18084240, 0xbd70b280, 0x4d30b5f0, 0x4a326828, 
+    0x8ec11880, 0x18806828, 0x682b8f00, 0x8f5b189b, 0x12db055b, 0x682b0c1c, 0x223a189b, 0x048b5e9a, 
+    0x0f5b054e, 0x199b0f76, 0x085b0689, 0x185e0e89, 0x06c30481, 0x0f490152, 0x0c120edb, 0x098718c9, 
+    0xd00007ff, 0x05474249, 0x18fb0f7f, 0x07c00940, 0x425bd000, 0x682918c8, 0x481b1043, 0x8f401808, 
+    0x16810680, 0x185d0048, 0x19404684, 0x4c120065, 0x68241940, 0x88241880, 0x06a7b200, 0x2f020fbf, 
+    0x0764d109, 0x0058d507, 0x18411980, 0x18084660, 0x18801940, 0xbdf0b200, 0x0000f7ff, 0x0000fc1f, 
+    0x0001a180, 0x0000c7ff, 0x0000fffe, 0x0001a300, 0xffffff7f, 0x0001a140, 0x20000090, 0x20000084, 
+    0x20000200, 0x0000fff0, 0x0001a040, 0xf7ffb500, 0x0081ff4b, 0x18080040, 0xbd00b280, 0x2200b500, 
+    0xfd09f7fd, 0xda012800, 0x22014240, 0x68094915, 0x18c94b15, 0x08c98809, 0x0fc907c9, 0x0040d002, 
+    0xe0024912, 0x00404911, 0x5e083940, 0xd0012a00, 0xb2004240, 0xb510bd00, 0x07092103, 0x138a8a8a, 
+    0x4a08828a, 0x68140680, 0x48070dc3, 0x18243840, 0x8a8b82e3, 0x828b4b06, 0x1c596812, 0x82c11810, 
+    0x0000e40a, 0x20000084, 0x0001a080, 0x00007bfc, 0x00007fff, 0x49fdb570, 0x680a2500, 0x31404611, 
+    0x33604613, 0x774d75cd, 0x83d5731d, 0x8415461c, 0xd0092800, 0x43e4240f, 0xd0082801, 0x28022300, 
+    0x2803d01a, 0xe005d017, 0x77e5230f, 0x3280e002, 0x70154623, 0x570c2410, 0xd00d2802, 0xd00b2803, 
+    0x76cd764b, 0x76887e48, 0xf7fd4618, 0x4620fcad, 0xfedef7fd, 0x240fbd70, 0xe7f2764c, 0x4ce3b570, 
+    0x68212500, 0x3240460a, 0x3360460b, 0x280075d5, 0x2801d007, 0x76d5d00c, 0xd01d2802, 0xd0222803, 
+    0x7bc8e00f, 0x76d608c6, 0x02007fdb, 0xe00718c0, 0x08c37c08, 0x76d3425b, 0x20800203, 0x18185c40, 
+    0x76958488, 0x5610201b, 0xfc7ef7fd, 0x205a6821, 0xf7fd5608, 0xbd70fead, 0x08c57b48, 0x7695426d, 
+    0x7f5b0200, 0x7b88e004, 0x769508c5, 0x02007f9b, 0x848818c0, 0xb5f0e7e6, 0x46944cc4, 0x9a086824, 
+    0x9f052501, 0x34609e06, 0xd0032a01, 0xdb162900, 0xe00a2101, 0xd0062900, 0x2b00da02, 0xe00edc03, 
+    0xdaf52b00, 0x73254660, 0x9a07e005, 0x1a404351, 0xb2402100, 0x42b07321, 0x4630dd04, 0x2100e005, 
+    0xe7f243c9, 0xda0142b8, 0x73254638, 0xb5f0bdf0, 0x0005b085, 0x201ed04c, 0x2d0143c0, 0x2d03d001, 
+    0x2200d046, 0x231e49a9, 0x24206809, 0x5f0c5ecb, 0x4323029b, 0x3440460c, 0x3b0f7ce6, 0x4ea42e01, 
+    0x4fa46836, 0x19f6d037, 0x83ce8e36, 0x68364ea0, 0x8e7619f6, 0x0db605b6, 0x261e840e, 0x27205f8e, 
+    0x02b65fcf, 0x2119433e, 0x56613e0f, 0x1c4e46b4, 0xd9012e02, 0x76611049, 0x275a7f61, 0xb2ce1c49, 
+    0x77664992, 0x2e056809, 0xd81d57cf, 0x56612119, 0x92012600, 0x90009102, 0x221b9603, 0x463856a2, 
+    0xf7ff4661, 0x4989ff88, 0x31406809, 0xe02375ce, 0x2000221f, 0x19f6e7b6, 0x83ce8d36, 0x68364e84, 
+    0x8d7619f6, 0xe7c7b2f6, 0x2e072101, 0x2619d812, 0x920157a6, 0x90009103, 0x221b9602, 0x463856a2, 
+    0xf7ff4661, 0x4979ff68, 0x6809226c, 0x31405c52, 0xe00175ca, 0x75e14638, 0x68214c74, 0x7e8a3140, 
+    0x768876ca, 0xd00a2d00, 0xd0082d01, 0xfdf0f7fd, 0x46016820, 0x7dc23040, 0xd0032a01, 0xf7fde00f, 
+    0xe7f5fbb3, 0xd00d2d00, 0xd0132d01, 0x2d024a6a, 0xd0175682, 0xda002a00, 0x00d04252, 0x20007388, 
+    0xbdf0b005, 0x5682221a, 0xda002a00, 0x00d04252, 0xe7f473c8, 0x5682221a, 0xda002a00, 0x00d04252, 
+    0xe7ec7408, 0xda002a00, 0x00d04252, 0xe7e67348, 0x4e56b5f8, 0x68304604, 0x5c0b2153, 0x49542500, 
+    0x4a542b01, 0xd017680b, 0x8e1b189b, 0x680983c3, 0x8e491889, 0x0d890589, 0xf7fd8401, 0x6831fb6c, 
+    0x3340460b, 0x2c0276d8, 0x2c03d00e, 0x2c01d00f, 0x2c00d010, 0xe012d011, 0x8d1b189b, 0x680983c3, 
+    0x8d491889, 0xe7e7b2c9, 0x5c452079, 0x207ae007, 0xe0045c45, 0x5c45207b, 0x207ce001, 0x8bca5c45, 
+    0x2a002000, 0x200ad005, 0x1052e00c, 0x840a1c40, 0x2220b240, 0x2a005e8a, 0xe007dcf7, 0x1c401052, 
+    0xb24083ca, 0x5e8a221e, 0xdcf72a00, 0xb2401f00, 0x01c08c8a, 0x10c008d2, 0x1a10271f, 0x2c02023f, 
+    0x2c03d005, 0x2c01d003, 0x2c00d001, 0x42b8d102, 0x4638dd00, 0x0c1604c2, 0x181200ea, 0x2c02848e, 
+    0x2c03d005, 0x2c01d003, 0x2c00d001, 0x42bad102, 0x463add00, 0x0c0004d0, 0x271f0542, 0x427d0e12, 
+    0xd00a2c00, 0xd0082c03, 0x42400ac0, 0xd0072c01, 0xd0112c02, 0xd00f2c03, 0x0ac0e019, 0xd1f52c00, 
+    0xdd01281f, 0xe01276df, 0xda0142a8, 0xe00e76dd, 0xd00c2800, 0xe00a76d8, 0xdd01281f, 0xe006769f, 
+    0xda0142a8, 0xe002769d, 0xd0002800, 0x20017698, 0x2c0075d8, 0x2c01d012, 0x2c02d016, 0x0a30d01b, 
+    0x31607388, 0x768a778e, 0xbdf82000, 0x20000090, 0x20000084, 0x0001a040, 0x0000001a, 0x73c80a30, 
+    0x77ce3160, 0xe7ef770a, 0x74080a30, 0x54462080, 0x76ca3160, 0x0a30e7e8, 0x31607348, 0x764a774e, 
+    0x2103e7e2, 0x8a8a0709, 0x43d222c0, 0x07c0828a, 0x01c10fc0, 0x43010180, 0x680048fe, 0x18804afe, 
+    0x477081c1, 0x2103b510, 0x8a8a0709, 0x828a138a, 0x221505c0, 0x02520dc0, 0x4af61883, 0x48f66814, 
+    0x82e31824, 0x4bf58a8b, 0x6812828b, 0x18101c59, 0xbd1082c1, 0x2103b510, 0x8a8a0709, 0x828a138a, 
+    0x220b05c0, 0x02920dc0, 0x4aea1883, 0x48ea6814, 0x82e31824, 0x4be98a8b, 0x6812828b, 0x18101c59, 
+    0xbd1082c1, 0x2103b510, 0x8a8a0709, 0x828a138a, 0x221305c0, 0x02520dc0, 0x4ade1883, 0x48de6814, 
+    0x82e31824, 0x4bdd8a8b, 0x6812828b, 0x18101c59, 0xbd1082c1, 0x2103b510, 0x8a8a0709, 0x828a138a, 
+    0x220505c0, 0x02d20dc0, 0x4ad21883, 0x48d26814, 0x82e31824, 0x4bd18a8b, 0x6812828b, 0x18101c59, 
+    0xbd1082c1, 0x2400b510, 0xdd062800, 0xf7ff4620, 0x4620ffe1, 0xffc6f7ff, 0x2800bd10, 0xda054620, 
+    0xffa8f7ff, 0xf7ff4620, 0xbd10ff8d, 0xfd2df7fd, 0xf7fd4620, 0xbd10fd12, 0x4bc1b510, 0x681b408a, 
+    0x8e1c4002, 0x43144384, 0xbd10861c, 0x4bbcb510, 0x681b408a, 0x8e5c4002, 0x43144384, 0xbd10865c, 
+    0x4604b510, 0xfb94f7fd, 0x07092103, 0x201f8a88, 0x828843c0, 0x06e248af, 0x0ed26803, 0x0364240d, 
+    0x855a191b, 0x4aaf8a8a, 0x4baf828a, 0x4aaa6804, 0x842318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 
+    0x84811880, 0xb510bd10, 0xf7fd4604, 0x2103fb71, 0x8a880709, 0x43c0201f, 0x489e8288, 0x680306e2, 
+    0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x828a4a9d, 0x68042309, 0x4a98031b, 0x842318a4, 0x23ff8a8b, 
+    0x2101828b, 0x02896800, 0x84811880, 0xb510bd10, 0xf7fd4604, 0x2103fb4d, 0x8a880709, 0x43c0201f, 
+    0x488c8288, 0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x3a204a8b, 0x4b8b828a, 0x33146804, 
+    0x18a44a85, 0x8a8b8423, 0x828b2300, 0x68044b87, 0x846318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 
+    0x84811880, 0x2800bd10, 0x43c0da00, 0x4770b280, 0x4c7bb5ff, 0x68204607, 0x9e092200, 0x30609d0a, 
+    0x29004694, 0xda04d003, 0xdc042b00, 0x2101e014, 0x2b00e019, 0x4608da0e, 0xffe5f7ff, 0x46184601, 
+    0xffe1f7ff, 0xd3004281, 0x68219f02, 0x31602001, 0xe0097308, 0xe0012101, 0x43c92100, 0x43599b0b, 
+    0xb24f1a79, 0x73012100, 0xdd0142af, 0xe002462f, 0xda0442b7, 0x68214637, 0x31602201, 0x42af730a, 
+    0x42b7d001, 0x2001d101, 0x68204684, 0x30604661, 0x72c17282, 0xb0044638, 0xb5f0bdf0, 0x46a62404, 
+    0x9d062701, 0x9e052400, 0x42a846bc, 0x42aadc36, 0x42b0dc34, 0x42b2db32, 0x9f07db30, 0x425e424d, 
+    0xd10e4287, 0xd0292900, 0xdd014290, 0x46841e60, 0xda002900, 0xb2084629, 0xda002b00, 0xb2194633, 
+    0x4297e010, 0x2b00d11a, 0x4282d018, 0x2000dd02, 0x468443c0, 0xda002b00, 0xb2184633, 0xda002900, 
+    0xb2094629, 0x23012200, 0x428803db, 0x1a09da08, 0x03c90064, 0xb26418c9, 0xe0081409, 0xbdf02000, 
+    0x1c640064, 0x03c01a40, 0xb26418c0, 0x1c521400, 0x4572b2d2, 0x1c64d9e9, 0x46611060, 0xd1ee1c49, 
+    0xb2404240, 0xb5f0bdf0, 0xb0874604, 0x90052001, 0x4f28482f, 0xdd082c00, 0x18096839, 0x06898909, 
+    0x6839168e, 0x88c01808, 0x6839e011, 0xda072c00, 0x89891809, 0x168e0689, 0x18086839, 0xe0068940, 
+    0x88891809, 0x168e0689, 0x18086839, 0x06808840, 0x481b1685, 0x46016800, 0x468c3140, 0x29007f49, 
+    0x683ad176, 0x18524914, 0x5e512128, 0x9103221f, 0x42519b05, 0x92019302, 0x231e9100, 0x46605ec3, 
+    0x56822218, 0x99034630, 0xff22f7ff, 0x480c9004, 0x6800216c, 0x29005c09, 0x221fd02f, 0x9b044251, 
+    0x92019302, 0x231e9100, 0x5ec32258, 0x46305682, 0xe00f9903, 0x20000084, 0x0001a040, 0x00007fff, 
+    0x20000090, 0x00000ff3, 0x0000a00c, 0x00002020, 0x0001a280, 0xff41f7ff, 0x48fe4601, 0x6800225b, 
+    0x54112c00, 0x3060dd02, 0xe0067441, 0xda022c00, 0x73c13060, 0x3060e001, 0x48f67341, 0x46016800, 
+    0x760e3140, 0x83c29a03, 0x7b003060, 0x2c007748, 0x9804dd03, 0xfe1ef7ff, 0x9804e007, 0xda022c00, 
+    0xfde8f7ff, 0xf7fde001, 0x4eeafb70, 0x30606830, 0x29007b01, 0x2c00d025, 0x7a82dd0b, 0x20202105, 
+    0xfe3af7ff, 0x21056830, 0x7ac23060, 0xe0162020, 0x7a82e017, 0xda092c00, 0x20022101, 0xfe2cf7ff, 
+    0x21016830, 0x7ac23060, 0xe0082002, 0x20082103, 0xfe22f7ff, 0x21036830, 0x7ac23060, 0xf7ff2008, 
+    0x4ed4fe25, 0x46086831, 0x7f823040, 0xd1772a00, 0x4ad1683b, 0x222c189b, 0x231f5e9a, 0x425a9203, 
+    0x93019f05, 0x97029200, 0x22192320, 0x56825ecb, 0x99034628, 0xfe8cf7ff, 0x68304607, 0x5c09216c, 
+    0xd01c2900, 0x424a211f, 0x91019200, 0x23209702, 0x5ec32259, 0x46285682, 0xf7ff9903, 0x4601febe, 
+    0x6830225a, 0x54112c00, 0x3060dd02, 0xe0067481, 0xda022c00, 0x74013060, 0x3060e001, 0x68307381, 
+    0x31404601, 0x9a03764d, 0x30608402, 0x77887b00, 0xdd032c00, 0xf7ff4638, 0xe007fd85, 0x46382c00, 
+    0xf7ffda02, 0xe001fd4f, 0xfad7f7fd, 0x30606830, 0x29007b01, 0x2c00d024, 0x7a82dd0a, 0x20102104, 
+    0xfdbaf7ff, 0x21046830, 0x7ac23060, 0xe0152010, 0x2c007a82, 0x2100da09, 0xf7ff2001, 0x6830fdad, 
+    0x30602100, 0x20017ac2, 0x2102e008, 0xf7ff2004, 0x6830fda3, 0x30602102, 0x20047ac2, 0xfda6f7ff, 
+    0x30406830, 0x29007f41, 0x7f81d004, 0xd0012900, 0xe0002101, 0x75c12100, 0xbdf0b007, 0x488db5f0, 
+    0x68032707, 0x336043ff, 0x7b597c58, 0x1a4010fa, 0x42b8b240, 0x2101dc01, 0x2808e004, 0x4611db01, 
+    0x2100e000, 0x68204c85, 0x19804e85, 0x251e8900, 0x16800680, 0x43ed1840, 0xda0142a8, 0xe0024628, 
+    0xdd00281f, 0x7c99201f, 0x1ac97b9b, 0x42b9b249, 0x2201dc01, 0x2908e002, 0x2200da00, 0x19896821, 
+    0x068988c9, 0x188c1689, 0xda0142ac, 0xe002462c, 0xdd002c1f, 0xf7ff241f, 0x4620fd1d, 0xfd02f7ff, 
+    0x486cbdf0, 0x68002200, 0x460183c2, 0x31408402, 0x75ca754a, 0x764a760a, 0x76ca768a, 0x778a774a, 
+    0x5c092184, 0xd0012901, 0x84c28442, 0x85028482, 0xb5704770, 0x68204c5f, 0x7a813040, 0xd05a2903, 
+    0x43ed2500, 0xd01f2904, 0xd0372905, 0xf7ff2001, 0x2103fc98, 0x8a880709, 0x43c02010, 0x49578288, 
+    0x68092010, 0x32404a54, 0x80081889, 0xf7ff4628, 0xf7fffcf9, 0x2009ffc6, 0xfd22f7ff, 0xff19f7fc, 
+    0x21046820, 0x72813040, 0xff5bf7fc, 0xd0452800, 0xf7ff4628, 0x6820fe28, 0x7dc03040, 0xd0ed2800, 
+    0xf7ff2000, 0xf7fffcdf, 0x2009ffac, 0xfd2bf7ff, 0xfefff7fc, 0x21056820, 0x72813040, 0xff41f7fc, 
+    0xd02b2800, 0xf7ff2000, 0x6820fe0e, 0x7dc03040, 0xd0ed2800, 0xf7fc2000, 0x2001ff17, 0xfcc2f7ff, 
+    0xff8ff7ff, 0xf7fd2009, 0xf7fcfdb5, 0x6820fee2, 0x30402103, 0xf7fc7281, 0x2800ff24, 0x2001d00e, 
+    0xfdf1f7ff, 0x30406820, 0x28007dc0, 0xf7ffd0ed, 0x2000ff35, 0xfc35f7ff, 0xbd702000, 0xbd702002, 
+    0x4a26b5f0, 0x43ff271e, 0x6810261f, 0x1179b085, 0x18c44b21, 0x5e202030, 0xdd01281f, 0xe00c0c4c, 
+    0x42e02420, 0x460cda01, 0x6812e007, 0x18d20280, 0x05928e52, 0x43100d92, 0x4816b204, 0x68022310, 
+    0x30404610, 0x930356c3, 0x97009102, 0x23209601, 0x22185ed3, 0x46215682, 0xf7ff9803, 0x4605fd19, 
+    0x216c480c, 0x5c096800, 0xd0122900, 0x86810129, 0x96019700, 0x23209502, 0x5ec32258, 0x46215682, 
+    0xf7ff9803, 0x4601fd4a, 0x68004802, 0x18898e82, 0xe0078681, 0x20000090, 0x0001a040, 0x20000084, 
+    0x0001a280, 0x9a0348f9, 0x46016800, 0x760a3140, 0x30608404, 0x75c87b00, 0xf7fd4628, 0xb005f8c9, 
+    0xb5f8bdf0, 0x25034cf1, 0x072d6820, 0x7a803040, 0x4ff04eef, 0xd021280c, 0xff03f7ff, 0x30406820, 
+    0x76417c01, 0xfe77f7fc, 0x31406821, 0x20007688, 0xf8aef7fd, 0xf7fc2000, 0x8aa8fe77, 0x683a82ae, 
+    0x200d2101, 0x18100340, 0x200980c1, 0xfc8ff7ff, 0xfe3ff7fc, 0x210c6820, 0x72813040, 0xfe81f7fc, 
+    0xd0072800, 0xff6cf7ff, 0x31406821, 0x28007dc8, 0xe004d002, 0xbdf82002, 0x28207d48, 0x8aa8d3e8, 
+    0x683b82ae, 0x200d2200, 0x18180340, 0x201980c2, 0xf7fd5608, 0x6821f87d, 0x5608205a, 0xfe44f7fc, 
+    0xbdf82000, 0x460db570, 0xf0030003, 0x0e06f99b, 0x0a080604, 0x24080e0c, 0x2410e008, 0x2420e006, 
+    0x2440e004, 0x2480e002, 0x2400e000, 0xffa0f7fc, 0x07002003, 0x211f8a81, 0x828143c9, 0x06ea49bd, 
+    0x0ed2680b, 0x036d250d, 0x855a195b, 0x4aba8a82, 0x680d8282, 0x4ab92320, 0x842b18ad, 0x23008a83, 
+    0x4bb78283, 0x18ad680d, 0x8a83846b, 0x828323ff, 0x02206809, 0x84881889, 0xb5f0bd70, 0x05cf2203, 
+    0x0dff0712, 0x4cab1396, 0x00034dac, 0xf95af003, 0x45044406, 0x44bbb6b1, 0xdd012946, 0xe0012146, 
+    0xdd02293f, 0x383f4608, 0x2000e000, 0xb2408a93, 0x039b2303, 0x05c38293, 0x0ddb2601, 0x682702b6, 
+    0x197f199e, 0x8a9682fe, 0x82964e9e, 0x1c766827, 0x82fe197f, 0x27038a97, 0x829703bf, 0x19db117f, 
+    0x197f6827, 0x8a9382fb, 0x82931e73, 0x195b6823, 0x8a9382de, 0x039b2303, 0x1a088293, 0x682105c0, 
+    0x30ff0dc0, 0x30ff1949, 0x82c83002, 0x1e708a90, 0x68208290, 0x82c61940, 0x460bbdf0, 0x4248331f, 
+    0xd9062b3e, 0xdb012900, 0xe000460b, 0x3b1f4603, 0x2300e000, 0xb25b8a97, 0x03b62603, 0x05de8296, 
+    0x27050df6, 0x4c7b027f, 0x19f746b4, 0x19766826, 0x8a9782f7, 0x82974f7b, 0x1c7f6826, 0x82f71976, 
+    0x27038a97, 0x829703bf, 0x113f4666, 0x682719f6, 0x82fe197f, 0x4f738a97, 0x68248297, 0x19641c7f, 
+    0x8a9482e7, 0x03a42403, 0x29008294, 0x4608db00, 0x05c01ac0, 0x0dc02301, 0x18c302db, 0x68044865, 
+    0x82e31964, 0x4b678a93, 0x68078293, 0x197f1c5c, 0x8a9682fc, 0x03b62603, 0x26058296, 0x02b60fc9, 
+    0x198e6807, 0x82fe197f, 0x82938a96, 0x19766806, 0x8a9682f4, 0x03b62603, 0x260b8296, 0x19890276, 
+    0x19766806, 0x8a9182f1, 0x68008293, 0x82c41940, 0x8a90bdf0, 0x20078296, 0xe0080240, 0x82968a90, 
+    0x03002001, 0x8a90e003, 0x20098296, 0x68210240, 0x19491838, 0x8a9082c8, 0x8290484a, 0x1c406821, 
+    0x82c81949, 0xb40fbdf0, 0xae08b5fe, 0x7bb44684, 0x7c357bf3, 0x26007c70, 0x96004627, 0x2a009601, 
+    0x461cd101, 0x2901463b, 0x1c49d002, 0xe018d00c, 0xd2012c07, 0xe00a1c64, 0xd0012b00, 0xb2db1e5b, 
+    0xd20e4285, 0xe00b1c6d, 0xd0022c00, 0xb2e41e64, 0x2b07e007, 0x1c5bd201, 0x2d00b2db, 0x1e6dd001, 
+    0x4668b2ed, 0x2a007105, 0x7084d011, 0xa90870c3, 0x46697b08, 0xa9087008, 0x46697b48, 0x22067048, 
+    0xf0024660, 0xbcfeff06, 0xb004bc08, 0x70c44718, 0xe7ec7083, 0x1ad3b5fe, 0x4d204c1e, 0x2801b25e, 
+    0x2802d005, 0x4611d07b, 0xfed7f7ff, 0x6820bdfe, 0x8ec01940, 0x0480466a, 0x71900f40, 0x19406820, 
+    0x05408ec0, 0x71d00f40, 0x19406820, 0x06808ec0, 0x72100e80, 0x7250203f, 0xd0022900, 0xd12b2901, 
+    0x8910e022, 0x22018010, 0xa8014631, 0xf7ff9b01, 0x4806ff8a, 0x30806800, 0x06c97a01, 0x7b80d502, 
+    0xd5190680, 0x79884669, 0xe01571c8, 0x20000090, 0x0000fffe, 0x20000084, 0x00008bd3, 0x0001a040, 
+    0x00002020, 0x00007fff, 0x80108910, 0x46312200, 0x9b01a801, 0xff67f7ff, 0x07002003, 0x13818a81, 
+    0x466b8281, 0x230179da, 0x18d2029b, 0x195b6823, 0x8a8282da, 0x82824afe, 0x1c566823, 0x82de195b, 
+    0x82818a83, 0x799b466b, 0x19db14c7, 0x197f6827, 0x8a8382fb, 0x68238282, 0x82de195b, 0x82818a83, 
+    0x7a19466b, 0x31ff6823, 0x31ff195b, 0x82d93102, 0x82828a81, 0x19406820, 0xbdfe82c6, 0x6822e7ff, 
+    0x181248ec, 0x466d8f12, 0x0fd20652, 0x6822712a, 0x8f121812, 0x0fd20692, 0x6822716a, 0x8f121812, 
+    0x0f530492, 0x682271ab, 0x8f121812, 0x0f520552, 0x682571ea, 0x8f001828, 0x06c0466d, 0x72280ec0, 
+    0x726f271f, 0x29002500, 0x2901d002, 0xe028d144, 0xd10442c3, 0xd1021c70, 0x46692001, 0x466a7108, 
+    0x00407910, 0x1c404240, 0xb2414370, 0x80108910, 0xa8012201, 0xf7ff9b01, 0x466afef6, 0x7a107991, 
+    0xd10042c1, 0x48cc7115, 0x30806800, 0x06d27a02, 0x7b80d502, 0xd51f0640, 0x71d1466a, 0x71507910, 
+    0x42c2e01a, 0x1c70d104, 0x2001d102, 0x71484669, 0x7950466a, 0x42400040, 0x43701c40, 0x8910b241, 
+    0x22008010, 0x9b01a801, 0xfecdf7ff, 0x79d0466a, 0x42c87a11, 0x7155d100, 0x07002003, 0x13828a81, 
+    0x466e8282, 0x230579f1, 0x6825025b, 0x49b118cb, 0x82eb186d, 0x4bae8a83, 0x68268283, 0x18761c5d, 
+    0x8a8682f5, 0x466e8282, 0x148779b6, 0x682719f6, 0x82fe187f, 0x82838a86, 0x18766826, 0x8a8682f5, 
+    0x466e8282, 0x112f7a36, 0x682719f6, 0x82fe187f, 0x82838a86, 0x18766826, 0x8a8682f5, 0x466e8282, 
+    0x27057936, 0x19f602bf, 0x187f6827, 0x8a8682fe, 0x68268283, 0x82f51876, 0x82828a86, 0x7972466e, 
+    0x0276260b, 0x68261992, 0x82f21876, 0x82838a82, 0x18406820, 0xe74082c5, 0x68004890, 0x1840498d, 
+    0x06808e80, 0x47700e80, 0x488bb5f3, 0x6800b087, 0x30409005, 0x7cc09004, 0x28014e86, 0x9805d01a, 
+    0x7a013080, 0xd51b06c9, 0x29019907, 0x2902d002, 0xe015d003, 0x06807b80, 0x7b80e001, 0x28000640, 
+    0x9808db0e, 0xd0052800, 0x6800487c, 0x202c1981, 0xe00a5e08, 0x68004879, 0x20281981, 0xe0045e08, 
+    0x68004876, 0x20301981, 0x99075e08, 0x43ed250e, 0xf002000b, 0x7306fec7, 0x645a2304, 0x9908736b, 
+    0xd00e2900, 0x680a496d, 0x8ed21992, 0x05526809, 0x19890f52, 0x06898ec9, 0x18540e89, 0x27462500, 
+    0x4a66e05f, 0x19896811, 0x68128ec9, 0x0f490489, 0x8ed21992, 0x0e920692, 0xe7ef188c, 0x29009908, 
+    0x680a495e, 0x1992d013, 0x09528f12, 0x0fd207d2, 0xd01b680a, 0x8f121992, 0x07520a12, 0x0f526809, 
+    0x8f091989, 0x0ec906c9, 0x424c1851, 0x1992e019, 0x09928f12, 0x0fd207d2, 0xd003680a, 0x8f121992, 
+    0xe7ea0ad2, 0x8f121992, 0xe0020ad2, 0x8f121992, 0x07520a12, 0x0f526809, 0x8f091989, 0x0ec906c9, 
+    0x25251854, 0x272643ed, 0x4944e01b, 0x19896809, 0x251e8f49, 0x168c0689, 0x271f43ed, 0x493fe011, 
+    0x19896809, 0x05498f49, 0xe00516cc, 0x6809493b, 0x223a1989, 0x12d45e8a, 0xe002270f, 0x46252400, 
+    0x99044627, 0x764c2c00, 0xdb03d002, 0xe0032101, 0xe0012100, 0x43c92100, 0xb2001a40, 0x98049003, 
+    0x28007d40, 0x2000d015, 0x950043c0, 0x98059002, 0x23209701, 0x98045ec3, 0x56822218, 0x99034620, 
+    0xf926f7ff, 0x48244604, 0x6800216c, 0x30405c09, 0x980775c1, 0xd10b2801, 0xd10442ac, 0x1c419803, 
+    0x2101da01, 0x2100e000, 0x6800481b, 0x71413080, 0x68004819, 0x7d813040, 0xd0022901, 0x28037d00, 
+    0x9807d106, 0xd0042801, 0xd0052802, 0xd0032803, 0x42bce096, 0xe093d004, 0xd00142bc, 0xd17d42ac, 
+    0x07002003, 0x21018a81, 0x828143c9, 0x20014d0b, 0x220d6829, 0x18890352, 0x46018648, 0xf002201c, 
+    0x9808fc72, 0x68282800, 0x1980d027, 0xe0078ec0, 0x00007fff, 0x0001a040, 0x20000090, 0x20000084, 
+    0x68290540, 0x19890f40, 0x06898ec9, 0x18410e89, 0x19806828, 0x09408f00, 0x0fc007c0, 0xd0266828, 
+    0x8f001980, 0x07400a00, 0x0f40682a, 0x8f121992, 0x0ed206d2, 0x42401880, 0x1980e024, 0x68298ec0, 
+    0x0f400480, 0x8ec91989, 0x0e890689, 0x68281841, 0x8f001980, 0x07c00980, 0x68280fc0, 0x1980d003, 
+    0x0ac08f00, 0x1980e7df, 0x0ac08f00, 0x1980e002, 0x0a008f00, 0x682a0740, 0x19920f40, 0x06d28f12, 
+    0x18800ed2, 0x0c000600, 0x68284301, 0x8f401980, 0x06802603, 0x06001680, 0x43010a00, 0x23009101, 
+    0x96004632, 0x20012112, 0xfb97f002, 0xfe84f7ff, 0x02006829, 0x18894afe, 0xe0008849, 0x0709e010, 
+    0x43080f09, 0x230049fb, 0x22036809, 0x7bc93140, 0x04099600, 0x90014308, 0x20012113, 0xfb7df002, 
+    0x68284df4, 0x7cc13040, 0xd0112901, 0x56c32319, 0x99084622, 0xf7ff9807, 0x6828fd1d, 0x84019903, 
+    0x7e413040, 0x7d417601, 0x75411c49, 0xbdf0b009, 0x98074621, 0xfbf1f7ff, 0xb510e7ef, 0x07092103, 
+    0x138a8a8a, 0x05c0828a, 0x0dc02217, 0x18830252, 0x68144ae1, 0x384048de, 0x82e31824, 0x4bdf8a8b, 
+    0x6812828b, 0x18101c59, 0xbd1082c1, 0x48d9b5fe, 0x68014fd7, 0x4608233e, 0x7cc43040, 0x223f43db, 
+    0x3f402501, 0x2c004ed4, 0x2c01d001, 0x6834d021, 0x243019e7, 0x68365f3c, 0x19f64fd1, 0x950289f6, 
+    0x92019300, 0x23200676, 0x16772218, 0x56825ecb, 0x46214dc8, 0xf7ff4638, 0x4606f80b, 0x46016828, 
+    0x760f3140, 0x30608404, 0x75ca7b02, 0xd0052a01, 0x6834e010, 0x242c19e7, 0xe7dc5f3c, 0x21067a82, 
+    0xf7fe2040, 0x6828ff69, 0x30602106, 0x20407ac2, 0xff6cf7fe, 0xf7ff4630, 0x363effa0, 0x2e7c6828, 
+    0x3040d904, 0x220279c1, 0xe0034311, 0x79c13040, 0x401122fd, 0xe52071c1, 0x4caeb510, 0x6820214a, 
+    0x290a5c09, 0x3080d016, 0x07807b40, 0x2000d41d, 0xff83f7ff, 0x30406820, 0x28017cc0, 0xf7ffd815, 
+    0x2010f9f0, 0xff4cf7fe, 0xf943f7fc, 0x210a6820, 0x72813040, 0xf985f7fc, 0xd0082800, 0xff86f7ff, 
+    0x30406820, 0x28007dc0, 0x2000d0ee, 0x2002bd10, 0xb510bd10, 0x68204c97, 0x30404601, 0x2a0e7a82, 
+    0x3180d011, 0x07897b49, 0x7cc0d418, 0xd8152801, 0xf9c7f7ff, 0xf7fe2010, 0xf7fcff23, 0x6820f91a, 
+    0x3040210e, 0xf7fc7281, 0x2800f95c, 0xf7ffd00c, 0x6820ff5d, 0x7dc03040, 0xd0ee2800, 0x212f6820, 
+    0x72813040, 0xbd102000, 0xbd102002, 0x281fb510, 0x201fd901, 0xb241e003, 0xda002900, 0xf7fe2000, 
+    0xbd10fc2a, 0x4604b510, 0xfa92f7fc, 0x07092103, 0x201f8a88, 0x828843c0, 0x06e24877, 0x0ed26803, 
+    0x0364240d, 0x855a191b, 0x4a768a8a, 0x4b76828a, 0x4a6f6804, 0x18a43a40, 0x8a8b8423, 0x828b2300, 
+    0x68044b72, 0x846318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 0x84811880, 0xb510bd10, 0xf7fc4604, 
+    0x2103fa67, 0x8a880709, 0x43c0201f, 0x48628288, 0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 
+    0x828a4a63, 0x68042309, 0x4a59029b, 0x18a43a40, 0x8a8b8423, 0x828b2300, 0x68044b5c, 0x18a43340, 
+    0x8a8b8463, 0x828b23ff, 0x68002107, 0x188002c9, 0xbd108481, 0x4604b570, 0xfa3af7fc, 0x07092103, 
+    0x201f8a88, 0x828843c0, 0x06e3484b, 0x0edb6804, 0x0352220d, 0x856318a4, 0x4b488a8b, 0x6804828b, 
+    0x4d431c5b, 0x19643d40, 0x8a8b8423, 0x43db2380, 0x6800828b, 0x18802180, 0xbd708401, 0x4a3eb510, 
+    0x4b3b6810, 0x18c03b40, 0x68118f00, 0x0f400480, 0x8f0918c9, 0x0ec906c9, 0x68101841, 0x8f0018c0, 
+    0x07c00980, 0xd0000fc0, 0x68104249, 0x8f0018c0, 0x05406814, 0x18e40f40, 0x68128f24, 0x0ee406e4, 
+    0x18d21900, 0x09528f12, 0x0fd207d2, 0x4240d000, 0x10401808, 0xbd103811, 0x2003b5f0, 0x8a810700, 
+    0x8281492c, 0x13814a24, 0x4b216814, 0x18e43b40, 0x8a818021, 0x82864e28, 0x6809491e, 0x7a0c3180, 
+    0xd50206e4, 0x06a47b8c, 0x2401d501, 0x2400e000, 0x00642501, 0x681702ad, 0x18ff1964, 0x8a84807c, 
+    0x7a0c8286, 0xd50206e4, 0x06497b89, 0x2101d501, 0x2100e000, 0x68140049, 0x18e41949, 0x8a8180a1, 
+    0x1c894915, 0x68148281, 0x80e518e4, 0x82818a84, 0x18e46814, 0x8a848125, 0x68118281, 0x814d18c9, 
+    0x490e8a81, 0x48098281, 0x18c96811, 0xbdf08188, 0x0001a080, 0x20000090, 0x20000084, 0x00007fff, 
+    0x0001a280, 0x00008ff3, 0x0000300c, 0x00002020, 0x00008bf3, 0x00003fff, 0x000093fd, 0x0000c0c0, 
+    0x2103b570, 0x8a8a0709, 0x828a4afb, 0x48fb0282, 0x230d6804, 0x18e4035b, 0x8a8a8522, 0x828a4af8, 
+    0x25006806, 0x19364cf7, 0x4df78075, 0x3580682d, 0x07ed7bad, 0x8a8dd10d, 0x6805828a, 0x192c1c52, 
+    0x8a8a8062, 0x43d22240, 0x6800828a, 0x18c02140, 0xbd708401, 0x2103b5f0, 0x8a8a0709, 0x828a4ae6, 
+    0x48e60282, 0x270d6803, 0x19db037f, 0x8a8a851a, 0x828a4ae3, 0x24006805, 0x18ed4be2, 0x8a8d806c, 
+    0x6805828a, 0x80ac18ed, 0x828a8a8d, 0x18ed6805, 0x8a8d80ec, 0x6805828a, 0x812c18ed, 0x828a8a8d, 
+    0x18ed6805, 0x4cd8816c, 0x34806824, 0x07ee7ba5, 0xd1044dd6, 0x828a8a8e, 0x18f66806, 0x7ba68075, 
+    0xd40407b6, 0x828a8a8e, 0x18f66806, 0x7ba480b5, 0xd4040764, 0x828a8a8c, 0x18d26802, 0x8a8a80d5, 
+    0x43d22240, 0x6800828a, 0x19c02140, 0xe76e8401, 0x4ec5b5fe, 0x68304ac1, 0x460449c2, 0x7cc33040, 
+    0x2b016812, 0x1851d028, 0x46258e09, 0x356083e1, 0x84a17829, 0x22018c61, 0xb249231f, 0x92029301, 
+    0x22189100, 0x23205682, 0x2000211e, 0x5e615ee3, 0xf7fe5628, 0x6831fdcd, 0x460ab2c0, 0x70103260, 
+    0x3a204613, 0x46148c8d, 0x7b1a7615, 0x8bca75e2, 0xf7ff840a, 0xe5defe3b, 0x8d091851, 0xb5fee7d5, 
+    0x4aa64ea9, 0x4ba76831, 0x3140460c, 0x68127ccd, 0xd02d2d01, 0x8e1218d2, 0x1810231f, 0x226183e0, 
+    0x85205710, 0x43d22200, 0x93012500, 0x95009202, 0x568a2218, 0x211e2320, 0x5e615ee3, 0xfd98f7fe, 
+    0x460a6831, 0x70503260, 0x3a204613, 0x46178d0c, 0x7b1a7614, 0x8bca75fa, 0xf7fb840a, 0x6830ff35, 
+    0x5c09216a, 0xd0062900, 0x30802101, 0xe5a27241, 0x8d1218d2, 0x3080e7d0, 0xe59c7245, 0x4887b5fe, 
+    0x48886801, 0x18083040, 0x4c878840, 0x68200702, 0x46070f12, 0x70ba3760, 0x212a8482, 0x25015e41, 
+    0x2b081d0b, 0x2356d803, 0x2b015c1b, 0x2200d022, 0x230f43d2, 0x93012600, 0x96009202, 0x5ec3232c, 
+    0x20022204, 0x563856ba, 0xfd52f7fe, 0xb2c16822, 0x30604610, 0x8c927081, 0x7102b2d2, 0x2b017b03, 
+    0x7186d001, 0x4291e008, 0x7185d101, 0x2102e004, 0xe0017181, 0x71bd713a, 0x8d416820, 0x21568581, 
+    0x29015c09, 0x4601d106, 0x798a3160, 0xd0012a01, 0x718a2202, 0x07092103, 0x220f8a8a, 0x828a43d2, 
+    0x78813060, 0x6802485d, 0x3040485e, 0x80411810, 0xb5f8e541, 0x25014c5c, 0x46016820, 0x7ccb3140, 
+    0x32604602, 0xd0042b00, 0xd1062b01, 0x075b7803, 0x238dd503, 0x075b5c1b, 0x7215d501, 0x7800e066, 
+    0x20050742, 0x77482a00, 0xf7feda03, 0x6821f98f, 0xf7fe8448, 0x4a4cf993, 0x84c86811, 0xfafcf7ff, 
+    0x46046812, 0x31604611, 0x78107008, 0xd5400740, 0x33804613, 0x28007958, 0x2000d005, 0x28005608, 
+    0x1c60da01, 0x2026e01a, 0x5e108c56, 0x4f4046b4, 0x8c381986, 0x428646b6, 0x7a58da08, 0xd1052800, 
+    0x367626ff, 0xd20145b4, 0xd3ea2c1f, 0x45b68c7e, 0x7a58dc23, 0xd1202800, 0x1e60e001, 0x4e327008, 
+    0xf7ff7808, 0x6830fd43, 0x30604602, 0x42a17801, 0x7a03d01b, 0xd0182b01, 0x42a12502, 0x2b04d91a, 
+    0x3240d016, 0x2a017d92, 0x2203d012, 0x1b087202, 0x2089e01a, 0x28005c80, 0x3240d004, 0x42947f52, 
+    0xe7dcd8db, 0xd3bc2c1f, 0x7205e7d9, 0xbdf82000, 0xe7ec7205, 0xd0092b03, 0x7d923240, 0xd0052a01, 
+    0x72022204, 0x42401a60, 0xbdf8b240, 0xe7f97205, 0x4604b510, 0xffacf7fb, 0x07092103, 0x201f8a88, 
+    0x828843c0, 0x06e2480d, 0x0ed26803, 0x0364240d, 0x855a191b, 0x4a0f8a8a, 0x2309828a, 0x029b6804, 
+    0x18a44a08, 0x8a8b8423, 0x828b2300, 0x6800490a, 0x84411880, 0x0000bd10, 0x000083ff, 0x20000084, 
+    0x00007fff, 0x0001a040, 0x20000090, 0x00008000, 0x20000200, 0x00008bff, 0x00002060, 0x2101b530, 
+    0xd804280d, 0x40811f80, 0x2001b2c9, 0x380ee003, 0xb2c94081, 0x22032002, 0x8a930712, 0x829323ff, 
+    0x020c4bfe, 0x49fe681d, 0x84ac186d, 0x240c8a94, 0x829443e4, 0x0080681a, 0x84081851, 0xb5febd30, 
+    0x68284df6, 0x36404ef6, 0x88801980, 0x07414ff5, 0x0f49683c, 0x30604620, 0x84a170c1, 0x43db2300, 
+    0x21002207, 0x92019302, 0x232e9100, 0x5ee32126, 0x5e612205, 0x46045682, 0x56202003, 0xfc18f7fe, 
+    0x4611683a, 0x70c83160, 0x71488c90, 0x71c87b08, 0x85d08cd0, 0x07002003, 0x22078a82, 0x828243d2, 
+    0x682978c8, 0x80881989, 0xb570e425, 0x25ff4cdd, 0x46016820, 0x7a8a3140, 0xd0172a17, 0xd0222a18, 
+    0x29007cc9, 0x7801d123, 0xd5200749, 0x7a403060, 0xd10f2800, 0xf7ff2009, 0x6820fd83, 0x21692201, 
+    0x2217540a, 0x540a214a, 0x72853080, 0xfda9f7fb, 0xd0122800, 0xf7ff2009, 0x6820fd9d, 0x214a2218, 
+    0x3080540a, 0xf7fb7285, 0x2800fd9c, 0x6820d005, 0x30402119, 0x20007281, 0x2002bd70, 0xb500bd70, 
+    0x460249c0, 0x20006809, 0x00133180, 0xf8caf002, 0x07041406, 0x14100d0a, 0x07c07b88, 0x7b88e00a, 
+    0xe0070780, 0x07407b88, 0x7b88e004, 0xe0010700, 0x06c07b88, 0x1c4017c0, 0xb5f8bd00, 0x26014cb1, 
+    0x25006820, 0x7a803040, 0xd0282820, 0xd0762821, 0xfdc7f7fe, 0x46016820, 0x7cc23040, 0xd0022a00, 
+    0xd04f2a01, 0x7809e082, 0xd57f0749, 0x76c57686, 0x30406820, 0xf7ff7e80, 0x2800ffc2, 0x6820d01e, 
+    0x30402106, 0xf7fe7e80, 0x6820feed, 0x75c53040, 0xf7fb7545, 0x6820fcfe, 0x30402120, 0xf7fb7281, 
+    0x2800fd40, 0x6820d067, 0x7ec13040, 0xf7ff7e80, 0x6820f97b, 0x7dc03040, 0xd0ea2800, 0x46026820, 
+    0x7a113280, 0xd51006c9, 0x31404601, 0x56cb231a, 0xd1022b01, 0x06bf7b97, 0x2b02d504, 0x7b92d105, 
+    0xd4020652, 0x2a007eca, 0x4601d00a, 0x76cd3140, 0x1c527e8a, 0x215a768a, 0x29065641, 0xe035dbb8, 
+    0xe7f876ce, 0x07497809, 0x2102d530, 0x76c57681, 0x30406820, 0xf7ff7e80, 0x2800ff72, 0x6820d01e, 
+    0x30402106, 0xf7fe7e80, 0x6820fe9d, 0x75c53040, 0xf7fb7545, 0x6820fcae, 0x30402121, 0xf7fb7281, 
+    0x2800fcf0, 0x6820d017, 0x7ec13040, 0xf7ff7e80, 0x6820f92b, 0x7dc03040, 0xd0ea2800, 0x30406820, 
+    0x1c897e81, 0x7681b249, 0xdbd12905, 0x30406820, 0x20007285, 0x2002bdf8, 0xb5f8bdf8, 0x24004d61, 
+    0x46026828, 0x7a813040, 0xd04d2910, 0x46287cc1, 0x30806800, 0xd0022900, 0xd0772901, 0x7b40e079, 
+    0xd17607c0, 0xfd1df7fe, 0x78006828, 0xd4060740, 0xf7ff200c, 0x6828fba2, 0x07407800, 0x6828d52e, 
+    0x31404601, 0x2a017d8a, 0x2185d00d, 0x29005c09, 0x2100d002, 0xe03643c9, 0xfefef7fd, 0x85486829, 
+    0xfd5cf7ff, 0x7fc9e047, 0xd1002900, 0x21858544, 0x29005c09, 0x8d41d003, 0x85411e49, 0xf7fde005, 
+    0x6829feeb, 0x18808d4a, 0x68288548, 0x7fc13040, 0xb2c91c49, 0x290877c1, 0xe02cd028, 0xfc39f7fb, 
+    0x21106828, 0x72813040, 0xfc7bf7fb, 0xd00c2800, 0x4b326828, 0x31404601, 0x4e317d8a, 0xd0062a01, 
+    0x19896819, 0x85418e09, 0x2002e7ca, 0x7fcabdf8, 0xd1002a00, 0x8d478544, 0x199b681b, 0x1c528e1b, 
+    0x854318fb, 0x77c8b2d0, 0xd1042808, 0xfd16f7ff, 0x30406828, 0x682877c4, 0x07497801, 0x3060d40c, 
+    0x28007980, 0xe007d097, 0xe002e000, 0x07c07b40, 0x2001d008, 0x71903260, 0x21336828, 0x72813040, 
+    0xbdf82000, 0xfc9df7fe, 0x46016828, 0x7d823040, 0xd0062a01, 0xfb72f7ff, 0x85486829, 0xfceef7ff, 
+    0x7fc0e015, 0xd1002800, 0xf7ff854c, 0x6829fb67, 0x18808d4a, 0x31408548, 0x1c407fc8, 0x77c8b2c0, 
+    0xd1042808, 0xfcdaf7ff, 0x30406828, 0x682877c4, 0x07497801, 0x3060d4d0, 0xe0057980, 0x20000084, 
+    0x0001a040, 0x20000090, 0xd0cd2800, 0xb510e7c4, 0x68204cfb, 0x31404601, 0x2a007cca, 0x2a01d006, 
+    0x7802d102, 0xd4010752, 0xe5c32000, 0x290f7a89, 0x3080d022, 0x06807b40, 0xf7fed42a, 0x2000fc52, 
+    0xfe06f7fb, 0xf7ff2009, 0x2003faad, 0x8a810700, 0x43c92120, 0x49eb8281, 0x68092020, 0x18894aea, 
+    0xf7fb8408, 0x6821fbb8, 0x70483160, 0xfb91f7fb, 0x210f6820, 0x72813040, 0xfbd3f7fb, 0xd00c2800, 
+    0xf7ff203c, 0x6820fc4c, 0x7dc03040, 0xd0ed2800, 0x21326820, 0x72813040, 0x2002e7c6, 0xb510e58a, 
+    0x68204cd7, 0x31404601, 0x2a117a8a, 0x7cc9d021, 0xd1452900, 0x5c092188, 0xd14109c9, 0x06897801, 
+    0x29020f89, 0xf7fed03c, 0x200cfc0c, 0xfd50f7ff, 0x21006820, 0x210684c1, 0x75413040, 0x30406820, 
+    0xf7ff7d40, 0xf7fbfd7b, 0x6820fb54, 0x30402111, 0xf7fb7281, 0x2800fb96, 0x49c2d011, 0x4ac26808, 
+    0x8e001880, 0xd0102800, 0x23266820, 0x68095ec3, 0x2130188a, 0x29005e51, 0x2101dd03, 0x2002e003, 
+    0x2100e548, 0x185943c9, 0x682084c1, 0x7d413040, 0xb2c91c49, 0x29167541, 0xf7ffd3d0, 0xe002fd70, 
+    0x30602101, 0x682071c1, 0x30402131, 0x20007281, 0xb5f8e530, 0x07002003, 0x49ac8a81, 0x4ea98281, 
+    0x68312001, 0x270d0240, 0x19c9037f, 0x68308048, 0x898019c0, 0xfa7ff001, 0xe0014605, 0xd0082c00, 
+    0x19c06830, 0x0a008980, 0x0fc007c0, 0x2401d001, 0x2400e000, 0xd0052c00, 0xfa6df001, 0xb2801b40, 
+    0xd3eb280b, 0x19c16830, 0x5e08200a, 0xd0032c00, 0xda012800, 0x43e42400, 0xbdf84620, 0x4890b510, 
+    0x30806800, 0x07807a00, 0x2000d501, 0xf7ffe4f2, 0x2800ffc0, 0x2003d0fa, 0x8a810700, 0x43c92101, 
+    0x49888281, 0x68092001, 0x0352220d, 0x86481889, 0x20174601, 0xfcd7f001, 0xe4db2001, 0x4c80b5f0, 
+    0x68202100, 0x78022503, 0x0752072d, 0x460f4e7d, 0xda2c2a00, 0x56822258, 0x68004620, 0x30601dd3, 
+    0xd8012b0e, 0xe0137087, 0x330f4613, 0xd8022b1e, 0x22042110, 0x4613e00b, 0x2b2e3317, 0x2120d802, 
+    0xe0042208, 0x2a3e321f, 0x2130d802, 0x7082220c, 0xf7fe2001, 0x8aa8fcc2, 0x43c0200f, 0x682082a8, 
+    0x30606831, 0x4a687880, 0x18893240, 0x68208048, 0x56412158, 0xda012900, 0xe0014865, 0x03802003, 
+    0x21018aa9, 0x683282a9, 0x200d0041, 0x18120340, 0x8aa98091, 0x82a9495f, 0x22806833, 0x805a181b, 
+    0x82a98aaa, 0x18086831, 0x20008047, 0xb570bdf0, 0x21884c53, 0x25006820, 0x30405c09, 0x290007c9, 
+    0x7605d003, 0x20007645, 0x7a81bd70, 0xd0012907, 0x76457605, 0xff3df7ff, 0xd0292800, 0x31406821, 
+    0x18107e0a, 0x7608b240, 0x301f7e4a, 0xb2521c52, 0x283e764a, 0x2a30d809, 0xf7ffda07, 0x6820ff7f, 
+    0x30402107, 0x20027281, 0x2003bd70, 0x8a810700, 0x43c92101, 0x493b8281, 0x68092001, 0x0352220d, 
+    0x86481889, 0x20174601, 0xfc3df001, 0xbd702001, 0x30406820, 0x4832e7c5, 0x68002153, 0x7bc15c0a, 
+    0x2a0008c9, 0x2901d007, 0x7c00d911, 0x280108c0, 0x2000d90d, 0x29014770, 0x7c01d909, 0x290108c9, 
+    0x7b41d905, 0x290108c9, 0x7b80d901, 0x2001e7ee, 0xb5f84770, 0x230f4d22, 0x4611682a, 0x56cb3140, 
+    0x7b90764b, 0x1b007b54, 0x84d01040, 0x24007d8e, 0xd0062e01, 0x05402601, 0x198005f6, 0x1a181600, 
+    0x4616e00d, 0x79b73680, 0xd3092f07, 0x280c71b4, 0x1e58dd01, 0x260ce003, 0xda0142f0, 0x76481c58, 
+    0x56082019, 0xda012818, 0xe0022018, 0xdd01282c, 0x7648202c, 0x56082019, 0xd02f4283, 0x00db1ac3, 
+    0x73c884d3, 0xfc7af7fb, 0x22266828, 0x5e827b81, 0x188923f8, 0x8501b209, 0xda0d2900, 0xe00e8504, 
+    0x20000090, 0x20000084, 0x0001a040, 0x0000f8ff, 0x00003fff, 0x0000ff7f, 0xdd0029f8, 0x8d018503, 
+    0x7b417381, 0xb2091a89, 0x29008501, 0x8504da01, 0x29f8e002, 0x8503dd00, 0x73418d01, 0xbdf82000, 
+    0x4cf8b510, 0x46016820, 0x7a823040, 0xd0232a12, 0x28007cc0, 0x2801d001, 0x3180d170, 0x06407b48, 
+    0xf7fed46c, 0xf7fbfa3e, 0x6821f9b6, 0x76083140, 0x77087c08, 0xf7fb200f, 0x6820fb48, 0x30402100, 
+    0x7d89e01d, 0xd0322901, 0xfcd4f7fd, 0xf981f7fb, 0x21126820, 0x72813040, 0xf9c3f7fb, 0xd0292800, 
+    0x30406820, 0x7d407d81, 0xd0252901, 0xfd5ff7fd, 0x30406820, 0x29007dc1, 0x7d41d0e8, 0x75411c49, 
+    0x31406821, 0x7d487cca, 0xd0182a00, 0x42902202, 0x201cd3d7, 0xf7fb5608, 0x6821fbbb, 0x56082058, 
+    0xf982f7fb, 0xff27f7ff, 0xd00a2801, 0xf7fde026, 0xe7cbfcd5, 0xe5982002, 0xfdeaf7fd, 0x2204e7d8, 
+    0x6820e7e5, 0x06407980, 0x2101d418, 0xf001201b, 0x6820fb4a, 0x7a013080, 0x2101070a, 0xdb0c2a00, 
+    0x07002003, 0x1eca8a82, 0x48bf8282, 0x220d6800, 0x18800352, 0x20018641, 0x7401e577, 0x23306820, 
+    0x46024601, 0x728b3140, 0x79843080, 0x1c644603, 0x7cc87184, 0xd10a2800, 0x07418810, 0x0600d407, 
+    0x7b58d405, 0xd40206c0, 0xff03f7ff, 0x2000e55d, 0xb510e55b, 0xf7fb4604, 0x2103faab, 0x8a880709, 
+    0x43c0201f, 0x48a88288, 0x680306e2, 0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x828a4aa4, 0x68044ba4, 
+    0x18a44aa4, 0x8a8b8423, 0x828b2300, 0x68044ba2, 0x846318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 
+    0x84811880, 0xb510e531, 0xf7fb4604, 0x2103fa81, 0x8a880709, 0x43c0201f, 0x48938288, 0x680306e2, 
+    0x240d0ed2, 0x191b0364, 0x8a8a855a, 0x828a4a8f, 0x68044b8f, 0x18a44a8f, 0x8a8b8423, 0x828b2300, 
+    0x68044b8e, 0x846318a4, 0x23ff8a8b, 0x2101828b, 0x02896800, 0x84811880, 0xb570e507, 0x224d4c81, 
+    0x25006820, 0x292d5611, 0x292ed02b, 0x2161d00e, 0x30805c09, 0x20147441, 0xff9bf7ff, 0x84056820, 
+    0xf8a7f7fb, 0x212e6820, 0x73413040, 0xf8e9f7fb, 0xd0312800, 0xf7ff2000, 0x6820f962, 0x30404601, 
+    0x2a007dc2, 0x3160d0ec, 0x77417849, 0xf7ff2014, 0x6820ffaa, 0xf7fb8405, 0x6820f88c, 0x3040212d, 
+    0xf7fb7341, 0x2800f8ce, 0x2000d016, 0xf947f7ff, 0x46116822, 0x7dc83140, 0xd0ec2800, 0x2461734d, 
+    0x56a37f48, 0xdd004298, 0x77484618, 0x56102091, 0xf89af7fb, 0xbd702000, 0xbd702002, 0x4860b5f8, 
+    0x7f824c58, 0x46016820, 0x7a833040, 0xd02d2b23, 0xd03c2b24, 0x2b007cc3, 0x780bd102, 0xd401075b, 
+    0xbdf82000, 0x460b2500, 0x3380844d, 0x2e01791e, 0x7545d000, 0x2b00795b, 0x230fd00f, 0x1a9d56c3, 
+    0xdd012d00, 0x73c31e5b, 0x56c3230f, 0xd5011a9a, 0x73c31c5b, 0x84482001, 0x78c8e056, 0xb2403808, 
+    0xfa96f7fb, 0x21236820, 0x72813040, 0xff75f7ff, 0xd0d62802, 0x215d6820, 0x84c15c09, 0x300878c0, 
+    0xf7fbb240, 0x6820fa85, 0x30402124, 0xf7ff7281, 0x2802ff64, 0x6822d0c5, 0x46102600, 0x7f413040, 
+    0x43f68cd3, 0xb2091ac9, 0x290084d1, 0x7d43d010, 0xd0312b00, 0xdb012900, 0xe0002301, 0x251c4633, 
+    0x2d005745, 0x2501db01, 0x4635e000, 0xd02342ab, 0x84532301, 0xdb012900, 0xe000460d, 0x231c424d, 
+    0x2b0056c3, 0x461fdb01, 0x425fe000, 0xdd0a42bd, 0x78d23280, 0xd01a2a01, 0x5682220f, 0xdb002b00, 
+    0x19922601, 0x770173c2, 0x200f6821, 0x56083140, 0xda0f2818, 0xe0102018, 0x78d23280, 0xd0062a01, 
+    0x5682220f, 0xdb002900, 0x1b922601, 0x220fe7ea, 0xe7e75682, 0xdd01282c, 0x73c8202c, 0x5608200f, 
+    0xfa6cf7fb, 0x46016820, 0x7d423040, 0x1c524603, 0x7542b2d2, 0x28018c48, 0x2a10d014, 0x2001d212, 
+    0x0000e011, 0x20000090, 0x20000084, 0x00008ff3, 0x0000300c, 0x0001a040, 0x00006060, 0x00002060, 
+    0x20000200, 0x31802000, 0x20007108, 0xf7fb7298, 0xe745f9ff, 0x4efeb5fe, 0x30ff6830, 0x8e453001, 
+    0x80054668, 0x683006ac, 0x4ffa0ea4, 0x888019c0, 0x0fc00740, 0x0be8d10e, 0x05b8d00c, 0x21048a81, 
+    0x828143c9, 0x20046831, 0x808819c9, 0x20102101, 0xf989f001, 0x680148f0, 0x30804608, 0x42a27ec2, 
+    0x2300d01b, 0x2c002201, 0x3142d00e, 0x7602800d, 0x07002003, 0x82838a81, 0x19c06830, 0x23018003, 
+    0x94019200, 0xe0042203, 0x930175c2, 0x23019200, 0x21092204, 0xf0012001, 0x48dff8f0, 0x30806800, 
+    0xbdfe76c4, 0x4cdab57c, 0x49da6820, 0x18403940, 0x23038cc0, 0x48d807c6, 0x6800071b, 0x30802100, 
+    0x4ad62e00, 0x8a9e4dd3, 0xd00b829a, 0x22026823, 0x809a195b, 0x75822201, 0x910075c2, 0x46139101, 
+    0xe019210b, 0x19526822, 0x68228091, 0x88921952, 0x0fd20752, 0x8a9ad10b, 0x68228299, 0x88521952, 
+    0x04526823, 0x195b0c52, 0x7581805a, 0x91007641, 0x22042301, 0x21219101, 0xf0012001, 0xbd7cf8ae, 
+    0x48bbb510, 0x49bb6800, 0x18403940, 0x08608d84, 0xd00107c0, 0xffb6f7ff, 0xd00107e0, 0xff6af7ff, 
+    0xb57cbd10, 0x46054eb4, 0x24016830, 0x7dc03080, 0xd1082800, 0x90012005, 0x22022300, 0x94002115, 
+    0xf0012001, 0x6831f88a, 0x31802000, 0x22037608, 0x071275c8, 0x82908a93, 0x680048a5, 0x18804aa5, 
+    0x7e888005, 0xb2c21c40, 0xb2e8768a, 0x94002a01, 0xd0069001, 0x22022300, 0x2001210a, 0xf86df001, 
+    0x2300bd7c, 0x21202201, 0xb570e7f7, 0x68084998, 0x18804a98, 0x20018843, 0x430303c0, 0x8a840590, 
+    0x43e42401, 0x680d8284, 0x18ad2401, 0x8a8480ac, 0x82842400, 0x18806808, 0x21018043, 0xf001200c, 
+    0xbd70f8c2, 0xb510b40f, 0x07002003, 0x21ff8a81, 0x82810209, 0x8ee1466c, 0x0e0b07c9, 0x07c98ea1, 
+    0x430b0e49, 0x07c98e61, 0x430b0e89, 0x07c98e21, 0x430b0ec9, 0x07c98de1, 0x430b0f09, 0x07c98da1, 
+    0x430b0f49, 0x07c98d61, 0x430b0f89, 0x07c98d21, 0x430b0fc9, 0x680c4976, 0x025222d1, 0x86e318a4, 
+    0x23238a83, 0x8283029b, 0x8c63466c, 0x07db8c24, 0x0c5b07e4, 0x43230ca4, 0x8be4466c, 0x0ce407e4, 
+    0x466c4323, 0x07e48b64, 0x43230da4, 0x8b24466c, 0x0de407e4, 0x466c4323, 0x07e48ae4, 0x43230e24, 
+    0x8aa4466c, 0x0e6407e4, 0x466c4323, 0x07e48a64, 0x43230ea4, 0x8a24466c, 0x0ee407e4, 0x466c4323, 
+    0x07e489e4, 0x43230f24, 0x89a4466c, 0x0f6407e4, 0x466c4323, 0x07e48964, 0x43230fa4, 0x8924466c, 
+    0x0fe407e4, 0x680c4323, 0x872318a4, 0x23018a83, 0x828303db, 0x8ca3ac10, 0x07db8c64, 0x0c5b07e4, 
+    0x43230ca4, 0x8c24ac10, 0x0ce407e4, 0xac104323, 0x07e48be4, 0x43230d24, 0x8ba4ac10, 0x0d6407e4, 
+    0xac104323, 0x07e48b64, 0x43230da4, 0x8b24ac10, 0x0de407e4, 0xac104323, 0x07e48ae4, 0x43230e24, 
+    0x8aa4ac10, 0x0e6407e4, 0xac104323, 0x07e48a64, 0x43230ea4, 0x8a24ac10, 0x0ee407e4, 0xac104323, 
+    0x07e489e4, 0x43230f24, 0x89a4ac10, 0x0f6407e4, 0xac104323, 0x07e48964, 0x43230fa4, 0x8924ac10, 
+    0x0fe407e4, 0x680c4323, 0x876318a4, 0x230f8a83, 0x828343db, 0x8860ac10, 0x07c08823, 0x0f0007db, 
+    0x43180f5b, 0x8fe3466c, 0x07db6809, 0x43180f9b, 0x07db8fa3, 0x43180fdb, 0x87881889, 0xbc08bc10, 
+    0xb0042000, 0xb5ff4718, 0x001eb0ab, 0x46044615, 0x2700d018, 0xa8152120, 0xf86af001, 0xa8262114, 
+    0xf866f001, 0x90002000, 0x90029001, 0xa81d2124, 0xf85ef001, 0xd00a2f00, 0xdd052d12, 0x1fad2006, 
+    0xe006b2e9, 0xe7e52701, 0x2000b2e9, 0xb2e9e001, 0x9a2cb2f0, 0x1b1207c3, 0x1a121a52, 0x2201b2d5, 
+    0xd1012b00, 0xd3012806, 0x831aab20, 0xe0072802, 0x20000084, 0x0001a0c0, 0x20000090, 0x0000fffd, 
+    0xab20d301, 0x2804841a, 0xab20d304, 0x2806849a, 0x839ad300, 0x402048fe, 0xd0012801, 0xdb012c0a, 
+    0x8682a810, 0xdb012c02, 0x8182a820, 0xdb012c04, 0x80c2a820, 0xdb012c06, 0x8002a820, 0xdb042c08, 
+    0x8742a810, 0xdb002c0a, 0x07c88542, 0x2908d101, 0xa810d301, 0x29028282, 0xa810d301, 0x29048382, 
+    0xa810d301, 0x29068402, 0xa810d304, 0x29088482, 0x8302d300, 0x8d44a810, 0xd11f2c00, 0xd00107c8, 
+    0xd2192908, 0xd2172912, 0x8f40a810, 0xd1012801, 0xd211290a, 0x8800a820, 0xd1012801, 0xd20b290c, 
+    0x88c0a820, 0xd1012801, 0xd205290e, 0x8980a820, 0xd1032801, 0xd3012910, 0x8582a810, 0x8f58ab10, 
+    0x28009003, 0x290ad102, 0x879ad300, 0x8800a820, 0x28004684, 0x290cd103, 0xa820d301, 0xa8208042, 
+    0x2f0088c7, 0x290ed102, 0x8102d300, 0x2e008986, 0x2910d102, 0x81c2d300, 0x2b008e9b, 0x2912d115, 
+    0x9803d211, 0xd1012801, 0xd20c290a, 0x28014660, 0x290cd101, 0x2f01d207, 0x290ed101, 0x2e01d203, 
+    0x2910d103, 0xa810d301, 0x2d0086c2, 0x1e6dd07e, 0x07c1b2e8, 0x4669d001, 0x0840800a, 0x07c1d0f6, 
+    0x1e40d005, 0x06004669, 0x0e00804a, 0x4669d0ee, 0x29008889, 0x1e80d105, 0x06004669, 0x0e00808a, 
+    0x4669d0e4, 0x290088c9, 0x1e80d105, 0x06004669, 0x0e0080ca, 0x4669d0da, 0x29008849, 0xa920d16f, 
+    0x29008bc9, 0xa920d10d, 0x29008b89, 0x4669d109, 0x1e80804a, 0x0600a920, 0x0e0083ca, 0x2a00d0c6, 
+    0xa920d15d, 0x29008b49, 0xa920d10d, 0x29008b09, 0x4669d109, 0x1e80804a, 0x0600a920, 0x0e00834a, 
+    0x2a00d0b4, 0xa910d14b, 0x29008b49, 0xa910d10d, 0x29008b09, 0x4669d109, 0x1e80804a, 0x0600a910, 
+    0x0e00834a, 0x2a00d0a2, 0xa910d139, 0x29008ac9, 0xa910d10d, 0x29008a89, 0x4669d109, 0x1e80804a, 
+    0x0600a910, 0x0e0082ca, 0x2a00d090, 0xa910d127, 0x29008f09, 0x2b00d111, 0xa910d10f, 0x29008ec9, 
+    0x4669d10b, 0xa910804a, 0xe000870a, 0x1e80e11e, 0x0e000600, 0x2a00d08a, 0xa910d111, 0x29008dc9, 
+    0x2c00d10d, 0xa910d10b, 0x29008d89, 0x4669d107, 0x1e80804a, 0x0600a910, 0x0e0085ca, 0xa920d08a, 
+    0x29008cc9, 0xa920d109, 0x29008c89, 0x1e80d105, 0x0600a920, 0x0e0084ca, 0xa920d090, 0x29008c49, 
+    0xa920d109, 0x29008c09, 0x1e80d105, 0x0600a920, 0x0e00844a, 0xa910d094, 0x29008cc9, 0xa910d109, 
+    0x29008c89, 0x1e80d105, 0x0600a910, 0x0e0084ca, 0xa910d086, 0x29008c49, 0xa910d109, 0x29008c09, 
+    0x1e80d105, 0x0600a910, 0x0e00844a, 0xa910d08a, 0x29008bc9, 0xa910d109, 0x29008b89, 0x1e80d105, 
+    0x0600a910, 0x0e0083ca, 0xa920d08e, 0x29008a09, 0x2e00d10b, 0xa920d109, 0x290089c9, 0x1e80d105, 
+    0x0600a920, 0x0e00820a, 0xa920d094, 0x29008949, 0x2f00d10b, 0xa920d109, 0x29008909, 0x1e80d105, 
+    0x0600a920, 0x0e00814a, 0xa920d084, 0x29008889, 0x4661d10c, 0xd1092900, 0x8849a920, 0xd1052900, 
+    0xa9201e80, 0x808a0600, 0xd0870e00, 0x8fc9a910, 0xd10c2900, 0x29009903, 0xa910d109, 0x29008f89, 
+    0x1e80d105, 0x0600a910, 0x0e0087ca, 0xa920d07e, 0x29008bc9, 0xa920d13a, 0x29008b89, 0xad20d136, 
+    0x2d008b6d, 0xad20d10e, 0x2d008b2d, 0xad20d10a, 0x83ea1e80, 0x836a0600, 0xd0670e00, 0xd1252a00, 
+    0xd1232900, 0x8b6dad10, 0xd10f2d00, 0x8b2dad10, 0xd10b2d00, 0x83eaad20, 0xad101e80, 0x836a0600, 
+    0xd0530e00, 0xd1112a00, 0xd10f2900, 0x8ac9a910, 0xd10b2900, 0x8a89a910, 0xd1072900, 0x83caa920, 
+    0xa9101e80, 0x82ca0600, 0xd03f0e00, 0x8b49a920, 0xd12a2900, 0x8b09a920, 0xd1262900, 0x8b6dad10, 
+    0xd1122d00, 0x8b2dad10, 0xd10e2d00, 0xe001ad20, 0x80000001, 0x1e80836a, 0x0600ad10, 0x0e00836a, 
+    0x2a00d024, 0x2900d111, 0xa910d10f, 0x29008ac9, 0xa910d10b, 0x29008a89, 0xa920d107, 0x1e80834a, 
+    0x0600a910, 0x0e0082ca, 0xa910d010, 0x29008b49, 0xa910d114, 0x29008b09, 0xa910d110, 0x29008ac9, 
+    0xa910d10c, 0x29008a89, 0xe000d108, 0xa910e084, 0x834a1e80, 0x82ca0600, 0xd07d0e00, 0x8bc9a920, 
+    0xd12b2900, 0x8b89a920, 0xd1272900, 0x8f2dad10, 0xd1112d00, 0xd10f2b00, 0x8eedad10, 0xd10b2d00, 
+    0x83eaad20, 0xad101e80, 0x872a0600, 0xd0630e00, 0xd1132a00, 0xd1112900, 0x8dc9a910, 0xd10d2900, 
+    0xd10b2c00, 0x8d89a910, 0xd1072900, 0x83caa920, 0xa9101e80, 0x85ca0600, 0xd04d0e00, 0x8b49a920, 
+    0xd12b2900, 0x8b09a920, 0xd1272900, 0x8f2dad10, 0xd1112d00, 0xd10f2b00, 0x8eedad10, 0xd10b2d00, 
+    0x836aad20, 0xad101e80, 0x872a0600, 0xd0330e00, 0xd1132a00, 0xd1112900, 0x8dc9a910, 0xd10d2900, 
+    0xd10b2c00, 0x8d89a910, 0xd1072900, 0x834aa920, 0xa9101e80, 0x85ca0600, 0xd0740e00, 0x8b49a910, 
+    0xd12b2900, 0x8b09a910, 0xd1272900, 0x8f2dad10, 0xd1102d00, 0xd10e2b00, 0x8eedad10, 0xd10a2d00, 
+    0x1e80ad10, 0x0600836a, 0x0e00872a, 0x2a00d05b, 0x2900d114, 0xe000d112, 0xa910e055, 0x29008dc9, 
+    0x2c00d10c, 0xa910d10a, 0x29008d89, 0xa910d106, 0x834a1e80, 0x85ca0600, 0xd0440e00, 0x8ac9a910, 
+    0xd1292900, 0x8a89a910, 0xd1252900, 0x8f2dad10, 0xd1102d00, 0xd10e2b00, 0x8eedad10, 0xd10a2d00, 
+    0x1e80ad10, 0x060082ea, 0x0e00872a, 0x2a00d02b, 0x2900d112, 0xa910d110, 0x29008dc9, 0x2c00d10c, 
+    0xa910d10a, 0x29008d89, 0xa910d106, 0x82ca1e80, 0x85ca0600, 0xd0160e00, 0x8f00a810, 0xd1122800, 
+    0xd1102b00, 0x8ec0a810, 0xd10c2800, 0x8dc0a810, 0xd1082800, 0xd1062c00, 0x8d80a810, 0xd1022800, 
+    0x8702a810, 0x222285c2, 0xa80ca91d, 0xf968f7f9, 0xcb07466b, 0xc307ab09, 0xa9262214, 0xf7f9a804, 
+    0xac19f95f, 0x466ccc0f, 0xac15c40f, 0xf7ffcc0f, 0xb02ffbb9, 0xb5f8bdf0, 0x07242403, 0x4dca8aa5, 
+    0x070682a5, 0x06d50f36, 0x432e0ced, 0x682f4dc7, 0x197f4dc7, 0x8aa6813e, 0x43f6263f, 0x4fc382a6, 
+    0x683f068e, 0x197d0eb6, 0x8aa5816e, 0x82a54dc1, 0xd0052b00, 0x03652400, 0xdd032800, 0xe0022401, 
+    0xe7f82401, 0x03242400, 0x2a004325, 0x2401dd01, 0x2400e000, 0x432502e4, 0xdd012b00, 0xe0002401, 
+    0x02a42400, 0x4cb14325, 0x4fb16826, 0x19f63780, 0x25038175, 0x8aae072d, 0x43f6260f, 0x071d82ae, 
+    0x0f2d6824, 0x027626d1, 0x842519a4, 0xfc4bf7ff, 0xb5febdf8, 0x46692000, 0x48a48108, 0x4aa46801, 
+    0x18893a40, 0x68008d49, 0x300130ff, 0x46698e00, 0x20008008, 0x4684880d, 0x270c04a8, 0x28002630, 
+    0x2000da0a, 0x213c4602, 0xf7ff4663, 0x43b7ff94, 0x08b83710, 0xe0100080, 0xd51204e8, 0x20174b96, 
+    0x21162218, 0x569a5618, 0x46635659, 0xff83f7ff, 0x43b02004, 0x08803010, 0x46690080, 0x81081c40, 
+    0x06a8e0fe, 0x4a89d0fc, 0x4b896810, 0x894018c0, 0x68100681, 0x18c00e89, 0x68128900, 0x0f000700, 
+    0x891218d2, 0x04d2072b, 0x24000ed2, 0x2b010f9b, 0x2b02d002, 0xe031d018, 0x29211c49, 0x293cdb07, 
+    0x1843dc03, 0x2b3c189b, 0x1e49dd01, 0x2401e017, 0x2b211c4b, 0x2b3cdb06, 0x1843dc1e, 0x1c5b189b, 
+    0xdc192b3c, 0xe0172704, 0x1e492708, 0xdc08293c, 0xdb032921, 0x1a9b1a0b, 0xda022b06, 0xb2491c49, 
+    0x2401e00a, 0x2b3c1e4b, 0x2b21dcec, 0x1a0bdb04, 0x1e5b1a9b, 0xdae52b06, 0x811f466b, 0x0f9b06ab, 
+    0xd0022b01, 0xd01a2b02, 0x1e52e047, 0xdc072a18, 0xda052a00, 0x893b466f, 0x813b4333, 0xe03c1c52, 
+    0x1e532401, 0xdc052b18, 0xda032b00, 0x893b466f, 0xe0314333, 0x893b466f, 0x331043b3, 0x1c52e02c, 
+    0x2a18d413, 0x1843dc0a, 0x2b3c189b, 0x1a0bdc06, 0x2b061a9b, 0x1883db02, 0xdd062b18, 0x893b466f, 
+    0x332043b3, 0x1e52813b, 0x2401e017, 0xd4e11c53, 0xdc0d2b18, 0x189b1843, 0x2b3c1c5b, 0x1a0bdc08, 
+    0x1e5b1a9b, 0xdb032b06, 0x1c5b1883, 0xddd12b18, 0x893b466f, 0x332043b3, 0x07ab813b, 0x2b010f9b, 
+    0x2b02d002, 0xe04cd01d, 0x1e402603, 0xdc07280a, 0xda052800, 0x893b466f, 0x813b4333, 0xe0401c40, 
+    0x1e432401, 0xdc062b0a, 0xda042b00, 0x893b466f, 0x813b4333, 0x466ee035, 0x089b8933, 0x1c5b009b, 
+    0x1c40e02e, 0x280ad414, 0x1843dc0a, 0x2b3c189b, 0x1a0bdc06, 0x2b061a9b, 0x1883db02, 0xdd072b18, 
+    0x8933466e, 0x009b089b, 0x81331c9b, 0xe0181e40, 0x1c432401, 0x2b0ad4df, 0x1843dc0d, 0x1c5b189b, 
+    0xdc082b3c, 0x1a9b1a0b, 0x2b061e5b, 0x1883db03, 0x2b181c5b, 0x466eddcf, 0x089b8933, 0x1c9b009b, 
+    0x46638133, 0xfe87f7ff, 0xd0092c00, 0x0e8906a9, 0x91012001, 0x22044603, 0x211f9000, 0xfa7df000, 
+    0x68104a0a, 0x18c04b0a, 0x03c18980, 0x89004668, 0x0c400440, 0x05994308, 0x24008a8c, 0x6811828c, 
+    0x804818c9, 0x0000bdfe, 0x0000e0f0, 0x20000084, 0x0001a0c0, 0x0000c3ff, 0x20000200, 0xb5304770, 
+    0x6808490f, 0x18804a0f, 0x23038a02, 0x480f071b, 0x2a0f2504, 0x68004c0c, 0x829c8a9a, 0x6809d008, 
+    0x31ff2200, 0x858a3101, 0x43a98801, 0xbd308001, 0x22026809, 0x310131ff, 0x8801858a, 0xe7f54329, 
+    0x20000084, 0x0001a2c0, 0x0000fffd, 0x20000090, 0x7900482d, 0x0fc007c0, 0x482b4770, 0x228f7801, 
+    0x70014011, 0x78017901, 0x43112201, 0x47707001, 0x68804825, 0x48244770, 0xb2808900, 0x20034770, 
+    0x8a000700, 0x0d800580, 0x49204770, 0x31806809, 0x07097c89, 0x008a0e09, 0x3140491b, 0x60881851, 
+    0x228f7808, 0x30104010, 0x78087008, 0x43102201, 0x47707008, 0x68004815, 0x7c803080, 0x0e000700, 
+    0x48110081, 0x18083040, 0x22027801, 0x70014311, 0x480e4770, 0x6800490c, 0x30803140, 0x07007c80, 
+    0x00800e00, 0x68c01840, 0x48084770, 0x68004906, 0x30803140, 0x07007c80, 0x00800e00, 0x79001840, 
+    0x0fc007c0, 0x00004770, 0x300000c0, 0x20000090, 0xb672b510, 0x69c84966, 0x041222ff, 0x22014390, 
+    0x43100592, 0x496461c8, 0x60484862, 0x20006088, 0x21014a62, 0x0ee406c4, 0x40a3460b, 0x00a40944, 
+    0x602318a4, 0xb2401c40, 0xdbf3280c, 0x46202404, 0xf898f000, 0xb2641c64, 0xdbf82c0c, 0xbd10b662, 
+    0x4c57b5fe, 0x91006821, 0x4f574d56, 0x6839682e, 0x02019101, 0x07804a55, 0x60291889, 0x12fa6821, 
+    0x0b404391, 0x60214301, 0xfde3f7ff, 0x60209800, 0x9801602e, 0xbdfe6038, 0x4c49b5fe, 0x91006821, 
+    0x4f494d48, 0x6839682e, 0x02019101, 0x07804a47, 0x60291889, 0x12fa6821, 0x0b404391, 0x60214301, 
+    0xf8cef7ff, 0x60209800, 0x9801602e, 0xbdfe6038, 0x2200b510, 0x98014611, 0xf8e6f000, 0xb510bd10, 
+    0x46112200, 0xf0009801, 0xbd10f8df, 0x2200b510, 0x98014611, 0xf8d8f000, 0xb510bd10, 0x46112200, 
+    0xf0009801, 0xbd10f8d1, 0x2200b510, 0x98014611, 0xf8caf000, 0xb510bd10, 0x46112200, 0xf0009801, 
+    0xbd10f8c3, 0x7e40482a, 0x4829e79a, 0xe7977e80, 0x7ec04827, 0x4826e794, 0xe7917f00, 0x7e404824, 
+    0x4823e7aa, 0xe7a77e80, 0x7ec04821, 0x4820e7a4, 0xe7a17f00, 0x2200b510, 0x98014611, 0xf8a4f000, 
+    0xb510bd10, 0x24082004, 0xd0052900, 0xf814f000, 0xf0004620, 0xbd10f811, 0xf804f000, 0xf0004620, 
+    0xbd10f801, 0x0ed206c2, 0x40912101, 0x4a110940, 0x18800080, 0x47706001, 0x0ed206c2, 0x40912101, 
+    0x09404a0c, 0x32800080, 0x60011880, 0x00004770, 0xe000ed04, 0x80808080, 0xe000e400, 0xe000e280, 
+    0x20000084, 0x20000090, 0x30000014, 0x20000300, 0x20000200, 0xe000e100, 0x2140b510, 0xf000482b, 
+    0xbd10f9f7, 0xb51008c1, 0x281f1d09, 0xb672d813, 0x4b264a27, 0x32806812, 0x01927c92, 0x2c015c9c, 
+    0x1d09d100, 0x074418d2, 0x0f645c53, 0x40a02001, 0x54534303, 0xbd10b662, 0x491db5f0, 0x680b4e1b, 
+    0x7c993380, 0x198d0189, 0x29ff78a9, 0x786ad02c, 0xd00429fe, 0x42911a8f, 0x240dd803, 0x2402e002, 
+    0x2400e002, 0x1e64193c, 0x0e240624, 0x2c01d01c, 0x1ea0d100, 0x192c0094, 0x60e01c52, 0x280db2d0, 
+    0x2000d300, 0x01927c9a, 0x70501992, 0xd10b29fe, 0x01897c99, 0x78d1198a, 0xd1054281, 0xb2c81c49, 
+    0xd300280d, 0x70d02000, 0x0000bdf0, 0x20000264, 0x20000090, 0x2120b510, 0xf0004839, 0x2120f999, 
+    0xf0004838, 0xbd10f995, 0xf3bfb672, 0x49368f40, 0x7c0a2320, 0x740a431a, 0x8105f3ef, 0x06894a30, 
+    0x78130e89, 0x2b007011, 0x7091d10d, 0xf3ef6090, 0x60d08008, 0x8009f3ef, 0xf3ef6110, 0x61908006, 
+    0x8003f3ef, 0x200161d0, 0xd3062910, 0x39104604, 0x408c6953, 0x61534323, 0x4604e004, 0x408c6853, 
+    0x60534323, 0x70512100, 0x8f40f3bf, 0x78d1b662, 0x70d14301, 0xb5f0e7fe, 0xb6729d05, 0x8f40f3bf, 
+    0x27404c19, 0x433e7c26, 0x4c167426, 0x70207826, 0xd1092e00, 0x60a170a0, 0x8108f3ef, 0xf3ef60e1, 
+    0x61e58109, 0x612161a3, 0x28202101, 0x460dd306, 0x69633820, 0x432b4085, 0xe0046163, 0x6865460b, 
+    0x431d4083, 0x20006065, 0xf3bf7060, 0xb6628f40, 0xd0032a00, 0x430878e0, 0xe7fe70e0, 0x0000bdf0, 
+    0x20000224, 0x20000244, 0x20000200, 0x4b4bb570, 0x5e59210a, 0x4c4a2200, 0xe00a4d4a, 0x546e5ca6, 
+    0x1c521e40, 0xb2091e49, 0xb2d2b2c0, 0xda002900, 0x280021ff, 0x8159d1f2, 0xb5ffbd70, 0x4605b081, 
+    0x9e0b9804, 0xd1002800, 0x493cb672, 0x28ff7b48, 0x894bd102, 0xd3012b08, 0xe0002401, 0x9b022400, 
+    0x2bfd1e5b, 0x2c00d252, 0x4934d050, 0x29007d49, 0x2d01d14c, 0x2d00d002, 0xe004d003, 0x68004832, 
+    0x42907940, 0xf7ffd342, 0x4607fdb3, 0x482f0c01, 0x0c006800, 0x04001a08, 0xd0120c00, 0x22ff4928, 
+    0x0a02708a, 0x7008704a, 0xf7ff2003, 0x4823ffaf, 0x29ff7b41, 0x8940d104, 0xd2012808, 0xe0002400, 
+    0x48222401, 0x60072c00, 0x2d01d020, 0x2d00d024, 0x2408d027, 0x2800980a, 0x4819d008, 0x70060a31, 
+    0x0c317041, 0x980a7081, 0xff90f7ff, 0x4914980a, 0x01401d00, 0x70c84320, 0x88004814, 0x708a0a02, 
+    0x98027048, 0x20047008, 0xff80f7ff, 0x28009804, 0xb662d100, 0xbdf0b005, 0x6800480b, 0x7c843080, 
+    0x240fe7d8, 0xb51ce7d6, 0x2100460a, 0x460b9100, 0x46019101, 0xf7ff2001, 0xbd1cff80, 0x20000200, 
+    0x2000008c, 0x20000100, 0x20000090, 0x20000088, 0x490eb530, 0x78092000, 0x1e4c4d0b, 0x0202e011, 
+    0x32801952, 0x28007490, 0x1e43d005, 0x42a07513, 0x2300d103, 0x4623e002, 0x1c43e7f8, 0x74d31c40, 
+    0x4288b2c0, 0xbd30d3eb, 0x20000300, 0x20000080, 0xb5f84770, 0xd32c2a04, 0xd0120783, 0x1c49780b, 
+    0x1c407003, 0x07831e52, 0x780bd00b, 0x70031c49, 0x1e521c40, 0xd0040783, 0x1c49780b, 0x1c407003, 
+    0x078b1e52, 0xd0050f9b, 0x00df1ac9, 0x1bde2320, 0xe00ac908, 0xfc84f7f8, 0x461dbdf8, 0x40fdc908, 
+    0x40b4461c, 0xc010432c, 0x2a041f12, 0x08f3d2f5, 0x1e521ac9, 0x780bd4f0, 0x70031c49, 0x1e521c40, 
+    0x780bd4ea, 0x70031c49, 0x2a011c40, 0x7809d4e4, 0xbdf87001, 0xc004e001, 0x29041f09, 0x078bd2fb, 
+    0x8002d501, 0x07c91c80, 0x7002d000, 0x29004770, 0x07c3d00b, 0x7002d002, 0x1e491c40, 0xd3042902, 
+    0xd5020783, 0x1c808002, 0xe7e31e89, 0xe7ee2200, 0xe7df2200, 0x78c27803, 0x78434619, 0x021b0612, 
+    0x78834319, 0x041b78c0, 0x43114319, 0x0a090209, 0x43080600, 0x22004770, 0x428b0903, 0x0a03d32c, 
+    0xd311428b, 0x469c2300, 0x4603e04e, 0xd43c430b, 0x08432200, 0xd331428b, 0x428b0903, 0x0a03d31c, 
+    0xd301428b, 0xe03f4694, 0x428b09c3, 0x01cbd301, 0x41521ac0, 0x428b0983, 0x018bd301, 0x41521ac0, 
+    0x428b0943, 0x014bd301, 0x41521ac0, 0x428b0903, 0x010bd301, 0x41521ac0, 0x428b08c3, 0x00cbd301, 
+    0x41521ac0, 0x428b0883, 0x008bd301, 0x41521ac0, 0x428b0843, 0x004bd301, 0x41521ac0, 0xd2001a41, 
+    0x41524601, 0x47704610, 0x0fcae05d, 0x4249d000, 0xd3001003, 0x40534240, 0x469c2200, 0x428b0903, 
+    0x0a03d32d, 0xd312428b, 0x018922fc, 0x0a03ba12, 0xd30c428b, 0x11920189, 0xd308428b, 0x11920189, 
+    0xd304428b, 0xd03a0189, 0xe0001192, 0x09c30989, 0xd301428b, 0x1ac001cb, 0x09834152, 0xd301428b, 
+    0x1ac0018b, 0x09434152, 0xd301428b, 0x1ac0014b, 0x09034152, 0xd301428b, 0x1ac0010b, 0x08c34152, 
+    0xd301428b, 0x1ac000cb, 0x08834152, 0xd301428b, 0x1ac0008b, 0xd2d94152, 0x428b0843, 0x004bd301, 
+    0x41521ac0, 0xd2001a41, 0x46634601, 0x105b4152, 0xd3014610, 0x2b004240, 0x4249d500, 0x46634770, 
+    0xd300105b, 0xb5014240, 0x46c02000, 0xbd0246c0, 0x46754770, 0xf822f000, 0x000546ae, 0x46534669, 
+    0x00c008c0, 0xb0184685, 0xf7f8b520, 0xbc60fba9, 0x08492700, 0x260046b6, 0xc5c0c5c0, 0xc5c0c5c0, 
+    0xc5c0c5c0, 0xc5c0c5c0, 0x00493d40, 0x4770468d, 0x46c04604, 0x462046c0, 0xfb5bf7f8, 0x47704800, 
+    0x20000094, 0x4674b430, 0x78251e64, 0x42ab1c64, 0x461dd200, 0x005b5d63, 0xbc3018e3, 0x19194718, 
+    0x19191919, 0x18191919, 0x18181818, 0x19191818, 0x221a1919, 0x25242322, 0x29282726, 0x2d2c2b2a, 
+    0x30302f2e, 0x32323131, 0x20421021, 0x81084084, 0x24621231, 0x918848c4, 0x000a0000, 0x001f0015, 
+    0x00340029, 0x0049003e, 0x005d0053, 0x00720068, 0x0087007c, 0x009b0091, 0x00b000a6, 0x00c500ba, 
+    0x00da00cf, 0x00ee00e4, 0x010300f9, 0x0118010d, 0x012c0122, 0x01410137, 0x00110000, 0x00340023, 
+    0x00570046, 0x007a0069, 0x009d008c, 0x00c000af, 0x00e300d2, 0x010600f5, 0x01290118, 0x014c013b, 
+    0x016f015d, 0x01920180, 0x01b501a3, 0x01d801c6, 0x01fb01e9, 0x021e020c, 0x00007c5c, 0x20000080, 
+    0x00000014, 0x000001c4, 0x00007c70, 0x20000094, 0x0000036c, 0x000001e0, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
+};
diff --git a/drivers/net/bcmbca/phy/mac_drv.c b/drivers/net/bcmbca/phy/mac_drv.c
new file mode 100644
index 0000000000..c7c431e397
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mac_drv.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Jan 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#include "mac_drv.h"
+
+#define MAX_MAC_DEVS 16
+
+extern mac_drv_t mac_drv_unimac;
+extern mac_drv_t mac_drv_lport;
+extern mac_drv_t mac_drv_gmac;
+extern mac_drv_t mac_drv_sf2;
+extern mac_drv_t mac_drv_53125;
+#ifdef MAC_XPORT
+extern mac_drv_t mac_drv_xport;
+#endif
+mac_drv_t *mac_drivers[MAC_TYPE_MAX] = {};
+
+int mac_driver_set(mac_drv_t *mac_drv)
+{
+    if (mac_drivers[mac_drv->mac_type])
+    {
+        printk("Failed adding mac driver %s: already set\n", mac_drv->name);
+        return -1;
+    }
+    else
+    {
+        mac_drivers[mac_drv->mac_type] = mac_drv;
+        return 0;
+    }
+}
+EXPORT_SYMBOL(mac_driver_set);
+
+int mac_driver_init(mac_type_t mac_type)
+{
+    mac_drv_t *mac_drv;
+
+    if (!(mac_drv = mac_drivers[mac_type]))
+        return 0;
+
+    return mac_drv_init(mac_drv);
+}
+EXPORT_SYMBOL(mac_driver_init);
+
+int mac_drivers_set(void)
+{
+    int ret = 0;
+
+#ifdef MAC_UNIMAC
+    ret |= mac_driver_set(&mac_drv_unimac);
+#endif
+#ifdef MAC_LPORT
+    ret |= mac_driver_set(&mac_drv_lport);
+#endif
+#ifdef MAC_GMAC
+    ret |= mac_driver_set(&mac_drv_gmac);
+#endif
+#ifdef MAC_53125
+    ret |= mac_driver_set(&mac_drv_53125);
+#endif
+#if defined(MAC_SF2) || defined(MAC_SF2_EXTERNAL)
+    ret |= mac_driver_set(&mac_drv_sf2);
+#endif
+#ifdef MAC_XPORT
+    ret |= mac_driver_set(&mac_drv_xport);
+#endif
+
+    return ret;
+}
+EXPORT_SYMBOL(mac_drivers_set);
+
+int mac_drivers_init(void)
+{
+    int ret = 0;
+
+    ret |= mac_driver_init(MAC_TYPE_UNIMAC);
+    ret |= mac_driver_init(MAC_TYPE_LPORT);
+    ret |= mac_driver_init(MAC_TYPE_GMAC);
+    ret |= mac_driver_init(MAC_TYPE_SF2);
+    ret |= mac_driver_init(MAC_TYPE_XPORT);
+    ret |= mac_driver_init(MAC_TYPE_53125);
+
+    return ret;
+}
+EXPORT_SYMBOL(mac_drivers_init);
+
+static mac_dev_t mac_devices[MAX_MAC_DEVS] = {};
+
+#ifdef __KERNEL__
+/* For internal use only by proc interface */
+int mac_devices_internal_index(mac_dev_t *mac_dev)
+{
+    uint32_t i;
+
+    for (i = 0; i < MAX_MAC_DEVS; i++)
+    {
+        if (&mac_devices[i] == mac_dev)
+            return i;
+    }
+
+    return -1;
+}
+EXPORT_SYMBOL(mac_devices_internal_index);
+#endif
+
+static mac_dev_t *mac_dev_get(mac_type_t mac_type, int mac_id)
+{
+    int i;
+    mac_dev_t *mac_dev = NULL;
+
+    for (i = 0; i < MAX_MAC_DEVS; i++)
+    {
+        if (!mac_devices[i].mac_drv)
+            continue;
+
+        if (mac_devices[i].mac_drv->mac_type != mac_type)
+            continue;
+
+        if (mac_devices[i].mac_id != mac_id)
+            continue;
+
+        mac_dev = &mac_devices[i];
+        break;
+    }
+
+    return mac_dev;
+}
+
+mac_dev_t *mac_dev_add(mac_type_t mac_type, int mac_id, void *priv)
+{
+    uint32_t i;
+    mac_drv_t *mac_drv = NULL;
+    mac_dev_t *mac_dev = NULL;
+
+    if (!(mac_drv = mac_drivers[mac_type]))
+    {
+        printk("Failed to find MAC driver: mac_type=%d\n", mac_type);
+        return NULL;
+    }
+
+    if ((mac_dev = mac_dev_get(mac_type, mac_id)))
+    {
+        printk("Mac device already exists: %s:%d\n", mac_drv->name, mac_id);
+        return NULL;
+    }
+
+    for (i = 0; i < MAX_MAC_DEVS && mac_devices[i].mac_drv != NULL; i++);
+
+    if (i ==  MAX_MAC_DEVS)
+    {
+        printk("Failed adding mac device: %s:%d\n", mac_drv->name, mac_id);
+        return NULL;
+    }
+
+    mac_dev = &mac_devices[i];
+    
+    mac_dev->mac_drv = mac_drv;
+    mac_dev->mac_id = mac_id;
+    mac_dev->priv = priv;
+
+    if (mac_drv_dev_add(mac_dev))
+    {
+        printk("Failed to add MAC device to the driver: %s:%d\n", mac_drv->name, mac_id);
+        mac_dev_del(mac_dev);
+        return NULL;
+    }
+
+    return mac_dev;
+}
+EXPORT_SYMBOL(mac_dev_add);
+
+int mac_dev_del(mac_dev_t *mac_dev)
+{
+    mac_drv_dev_del(mac_dev);
+    memset(mac_dev, 0, sizeof(mac_dev_t));
+
+    return 0;
+}
+EXPORT_SYMBOL(mac_dev_del);
diff --git a/drivers/net/bcmbca/phy/mac_drv.h b/drivers/net/bcmbca/phy/mac_drv.h
new file mode 100644
index 0000000000..db4387bcb8
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mac_drv.h
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#ifndef __MAC_DRV_H__
+#define __MAC_DRV_H__
+
+#include "os_dep.h"
+#include "dt_access.h"
+
+extern int eee_enabled;
+
+typedef struct
+{
+    uint64_t rx_byte; /**< Receive Byte Counter */
+    uint64_t rx_packet; /**< Receive Packet Counter */
+    uint64_t rx_frame_64; /**< Receive 64 Byte Frame Counter */
+    uint64_t rx_frame_65_127; /**< Receive 65 to 127 Byte Frame Counter */
+    uint64_t rx_frame_128_255; /**< Receive 128 to 255 Byte Frame Counter */
+    uint64_t rx_frame_256_511; /**< Receive 256 to 511 Byte Frame Counter */
+    uint64_t rx_frame_512_1023; /**< Receive 512 to 1023 Byte Frame Counter */
+    uint64_t rx_frame_1024_1518; /**< Receive 1024 to 1518 Byte Frame Counter */
+    uint64_t rx_frame_1519_mtu; /**< Receive 1519 to MTU  Frame Counter */
+    uint64_t rx_multicast_packet; /**< Receive Multicast Packet */
+    uint64_t rx_broadcast_packet; /**< Receive Broadcast Packet */
+    uint64_t rx_unicast_packet; /**< Receive Unicast Packet */
+    uint64_t rx_alignment_error; /**< Receive Alignment error */
+    uint64_t rx_frame_length_error; /**< Receive Frame Length Error Counter */
+    uint64_t rx_code_error; /**< Receive Code Error Counter */
+    uint64_t rx_carrier_sense_error; /**< Receive Carrier sense error */
+    uint64_t rx_fcs_error; /**< Receive FCS Error Counter */
+    uint64_t rx_undersize_packet; /**< Receive Undersize Packet */
+    uint64_t rx_oversize_packet; /**< Receive Oversize Packet */
+    uint64_t rx_fragments; /**< Receive Fragments */
+    uint64_t rx_jabber; /**< Receive Jabber counter */
+    uint64_t rx_overflow; /**< Receive Overflow counter */
+    uint64_t rx_control_frame; /**< Receive Control Frame Counter */
+    uint64_t rx_pause_control_frame; /**< Receive Pause Control Frame */
+    uint64_t rx_unknown_opcode; /**< Receive Unknown opcode */
+    uint64_t rx_fifo_errors; /**< Receive fifo errors */
+    uint64_t rx_dropped;
+
+    uint64_t tx_byte; /**< Transmit Byte Counter */
+    uint64_t tx_packet; /**< Transmit Packet Counter */
+    uint64_t tx_frame_64; /**< Transmit 64 Byte Frame Counter */
+    uint64_t tx_frame_65_127; /**< Transmit 65 to 127 Byte Frame Counter */
+    uint64_t tx_frame_128_255; /**< Transmit 128 to 255 Byte Frame Counter */
+    uint64_t tx_frame_256_511; /**< Transmit 256 to 511 Byte Frame Counter */
+    uint64_t tx_frame_512_1023; /**< Transmit 512 to 1023 Byte Frame Counter */
+    uint64_t tx_frame_1024_1518; /**< Transmit 1024 to 1518 Byte Frame Counter */
+    uint64_t tx_frame_1519_mtu; /**< Transmit 1519 to MTU Frame Counter */
+    uint64_t tx_fcs_error; /**< Transmit FCS Error */
+    uint64_t tx_multicast_packet; /**< Transmit Multicast Packet */
+    uint64_t tx_broadcast_packet; /**< Transmit Broadcast Packet */
+    uint64_t tx_unicast_packet; /**< Transmit Unicast Packet */
+    uint64_t tx_total_collision; /**< Transmit Total Collision Counter */
+    uint64_t tx_jabber_frame; /**< Transmit Jabber Frame */
+    uint64_t tx_oversize_frame; /**< Transmit Oversize Frame counter */
+    uint64_t tx_undersize_frame; /**< Transmit Undersize Frame */
+    uint64_t tx_fragments_frame; /**< Transmit Fragments Frame counter */
+    uint64_t tx_error; /**< Transmission errors*/
+    uint64_t tx_underrun; /**< Transmission underrun */
+    uint64_t tx_excessive_collision; /**< Transmit Excessive collision counter */
+    uint64_t tx_late_collision; /**< Transmit Late collision counter */
+    uint64_t tx_single_collision; /**< Transmit Single collision frame counter */
+    uint64_t tx_multiple_collision; /**< Transmit Multiple collision frame counter */
+    uint64_t tx_pause_control_frame; /**< Transmit PAUSE Control Frame */
+    uint64_t tx_deferral_packet; /**< Transmit Deferral Packet */
+    uint64_t tx_excessive_deferral_packet; /**< Transmit Excessive Deferral Packet */
+    uint64_t tx_control_frame; /**< Transmit Control Frame */
+    uint64_t tx_fifo_errors; /**< Transmit fifo errors */
+    uint64_t tx_dropped;
+} mac_stats_t;
+
+typedef enum
+{
+    MAC_SPEED_UNKNOWN,
+    MAC_SPEED_10,
+    MAC_SPEED_100,
+    MAC_SPEED_1000,
+    MAC_SPEED_2500,
+    MAC_SPEED_5000,
+    MAC_SPEED_10000,
+} mac_speed_t;
+
+typedef enum
+{
+    MAC_DUPLEX_UNKNOWN,
+    MAC_DUPLEX_HALF,
+    MAC_DUPLEX_FULL,
+} mac_duplex_t;
+
+typedef enum
+{
+    MAC_TYPE_UNKNOWN,
+    MAC_TYPE_UNIMAC,
+    MAC_TYPE_LPORT,
+    MAC_TYPE_GMAC,
+    MAC_TYPE_xEPON,
+    MAC_TYPE_EPON_AE,
+    MAC_TYPE_SF2,
+    MAC_TYPE_XPORT,
+    MAC_TYPE_xGPON,
+    MAC_TYPE_53125,
+    MAC_TYPE_MAX,
+} mac_type_t;
+
+typedef enum
+{
+    MAC_LOOPBACK_NONE,
+    MAC_LOOPBACK_LOCAL,
+    MAC_LOOPBACK_REMOTE,
+    MAC_LOOPBACK_BOTH,
+} mac_loopback_t;
+
+typedef struct
+{
+    mac_speed_t speed;
+    mac_duplex_t duplex;
+} mac_cfg_t;
+
+typedef struct mac_dev_s
+{
+    struct mac_drv_s *mac_drv;
+    int mac_id;
+    int enabled;
+    void *priv;
+} mac_dev_t;
+
+typedef struct mac_drv_s
+{
+    mac_type_t mac_type;
+    char *name;
+    int initialized;
+    int (*init)(mac_dev_t *self);
+    int (*enable)(mac_dev_t *self);
+    int (*disable)(mac_dev_t *self);
+    int (*cfg_get)(mac_dev_t *self, mac_cfg_t *mac_cfg);
+    int (*cfg_set)(mac_dev_t *self, mac_cfg_t *mac_cfg);
+    int (*pause_set)(mac_dev_t *self, int rx_enable, int tx_enable, char *src_addr);
+    int (*pause_get)(mac_dev_t *self, int *rx_enable, int *tx_enable);
+    int (*pfc_set)(mac_dev_t *self, int rx_enable, int tx_enable, char *src_addr);
+    int (*pfc_get)(mac_dev_t *self, int *rx_enable, int *tx_enable);
+    int (*stats_get)(mac_dev_t *self, mac_stats_t *mac_stats);
+    int (*stats_clear)(mac_dev_t *self);
+    int (*mtu_set)(mac_dev_t *self, int mtu);
+    int (*eee_set)(mac_dev_t *self, int enable);
+    int (*dev_add)(mac_dev_t *self);
+    int (*dev_del)(mac_dev_t *self);
+    int (*drv_init)(struct mac_drv_s *mac_drv);
+    int (*loopback_set)(mac_dev_t *self, mac_loopback_t loopback_set);
+    int (*dt_priv)(const dt_handle_t handle, int mac_id, void **priv);
+} mac_drv_t;
+
+mac_dev_t *mac_dev_add(mac_type_t mac_type, int mac_id, void *priv);
+int mac_dev_del(mac_dev_t *mac_dev);
+
+int mac_drivers_set(void);
+int mac_drivers_init(void);
+int mac_driver_set(mac_drv_t *mac_drv);
+int mac_driver_init(mac_type_t mac_type);
+mac_dev_t *mac_dev_dt_probe(const dt_handle_t handle, uint32_t port_index);
+
+static inline int mac_dev_init(mac_dev_t *mac_dev)
+{
+    if (!mac_dev->mac_drv->init)
+        return 0;
+
+    return mac_dev->mac_drv->init(mac_dev);
+}
+
+static inline int mac_dev_enable(mac_dev_t *mac_dev)
+{
+    mac_dev->enabled = 1;
+
+    if (!mac_dev->mac_drv->enable)
+        return 0;
+
+    return mac_dev->mac_drv->enable(mac_dev);
+}
+
+static inline int mac_dev_disable(mac_dev_t *mac_dev)
+{
+    mac_dev->enabled = 0;
+
+    if (!mac_dev->mac_drv->disable)
+        return 0;
+
+    return mac_dev->mac_drv->disable(mac_dev);
+}
+
+static inline int mac_dev_cfg_get(mac_dev_t *mac_dev, mac_cfg_t *mac_cfg)
+{
+    if (!mac_dev->mac_drv->cfg_get)
+        return 0;
+
+    return mac_dev->mac_drv->cfg_get(mac_dev, mac_cfg);
+}
+
+static inline int mac_dev_cfg_set(mac_dev_t *mac_dev, mac_cfg_t *mac_cfg)
+{
+    if (!mac_dev->mac_drv->cfg_set)
+        return 0;
+
+    return mac_dev->mac_drv->cfg_set(mac_dev, mac_cfg);
+}
+
+static inline int mac_dev_pause_get(mac_dev_t *mac_dev, int *rx_enable, int *tx_enable)
+{
+    if (!mac_dev->mac_drv->pause_get)
+        return 0;
+
+    return mac_dev->mac_drv->pause_get(mac_dev, rx_enable, tx_enable);
+}
+
+static inline int mac_dev_pfc_set(mac_dev_t *mac_dev, int rx_enable, int tx_enable, char *src_addr)
+{
+    if (!mac_dev->mac_drv->pfc_set)
+        return 0;
+
+    return mac_dev->mac_drv->pfc_set(mac_dev, rx_enable, tx_enable, src_addr);
+}
+
+static inline int mac_dev_pfc_get(mac_dev_t *mac_dev, int *rx_enable, int *tx_enable)
+{
+    if (!mac_dev->mac_drv->pfc_get)
+        return 0;
+
+    return mac_dev->mac_drv->pfc_get(mac_dev, rx_enable, tx_enable);
+}
+
+static inline int mac_dev_pause_set(mac_dev_t *mac_dev, int rx_enable, int tx_enable, char *src_addr)
+{
+    if (!mac_dev->mac_drv->pause_set)
+        return 0;
+
+    return mac_dev->mac_drv->pause_set(mac_dev, rx_enable, tx_enable, src_addr);
+}
+
+static inline int mac_dev_stats_get(mac_dev_t *mac_dev, mac_stats_t *mac_stats)
+{
+    if (!mac_dev->mac_drv->stats_get)
+        return 0;
+
+    return mac_dev->mac_drv->stats_get(mac_dev, mac_stats);
+}
+
+static inline int mac_dev_stats_clear(mac_dev_t *mac_dev)
+{
+    if (!mac_dev->mac_drv->stats_clear)
+        return 0;
+
+    return mac_dev->mac_drv->stats_clear(mac_dev);
+}
+
+static inline int mac_dev_mtu_set(mac_dev_t *mac_dev, int mtu)
+{
+    if (!mac_dev->mac_drv->mtu_set)
+        return 0;
+
+    return mac_dev->mac_drv->mtu_set(mac_dev, mtu);
+}
+
+static inline int mac_dev_eee_set(mac_dev_t *mac_dev, int enable)
+{
+    if (!mac_dev->mac_drv->eee_set)
+        return 0;
+
+    if (!eee_enabled)
+        enable = 0;
+
+    return mac_dev->mac_drv->eee_set(mac_dev, enable);
+}
+
+static inline int mac_dev_loopback_set(mac_dev_t *mac_dev, mac_loopback_t loopback_set)
+{
+    if (!mac_dev->mac_drv->loopback_set)
+        return 0;
+    
+    return mac_dev->mac_drv->loopback_set(mac_dev, loopback_set);
+}
+
+static inline int mac_drv_dev_add(mac_dev_t *mac_dev)
+{
+    if (mac_dev->mac_drv->initialized)
+        return 0;
+
+    if (!mac_dev->mac_drv->dev_add)
+        return 0;
+
+    return mac_dev->mac_drv->dev_add(mac_dev);
+}
+
+static inline int mac_drv_dev_del(mac_dev_t *mac_dev)
+{
+    if (mac_dev->mac_drv->initialized)
+        return 0;
+
+    if (!mac_dev->mac_drv->dev_del)
+        return 0;
+
+    return mac_dev->mac_drv->dev_del(mac_dev);
+}
+
+static inline int mac_drv_init(mac_drv_t *mac_drv)
+{
+    if (mac_drv->initialized)
+        return 0;
+
+    if (!mac_drv->drv_init)
+        return 0;
+
+    return mac_drv->drv_init(mac_drv);
+}
+
+void mac_dev_rgmii_attach(mac_dev_t *mac_dev, int delay_rx, int delay_tx, int is_1p8v, int rgmii_pins[], int num_pins);
+
+#endif
+
diff --git a/drivers/net/bcmbca/phy/mac_drv_lport.c b/drivers/net/bcmbca/phy/mac_drv_lport.c
new file mode 100644
index 0000000000..4973ef3161
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mac_drv_lport.c
@@ -0,0 +1,443 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Jan 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#include "mac_drv.h"
+#include "phy_drv.h"
+#include "lport_drv.h"
+#include "lport_stats.h"
+#include "dt_access.h"
+
+phy_mii_type_t dt_get_phy_mode_mii_type(const dt_handle_t handle);
+
+static lport_init_s lport_init = {};
+
+static int port_lport_init(mac_dev_t *mac_dev)
+{
+    uint32_t port_id = mac_dev->mac_id;
+    lport_stats_cfg_s stats_cfg = {};
+
+    if (lport_stats_cfg_set(port_id, &stats_cfg))
+    {
+        printk("Failed to initialize stats configuration for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    return 0;
+}
+
+static int port_lport_enable(mac_dev_t *mac_dev)
+{
+    uint32_t port_id = mac_dev->mac_id;
+
+    if (lport_set_port_rxtx_enable(port_id, 1, 1))
+    {
+        printk("Failed to enable rx/tx for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    return 0;
+}
+
+static int port_lport_disable(mac_dev_t *mac_dev)
+{
+    uint32_t port_id = mac_dev->mac_id;
+
+    if (lport_set_port_rxtx_enable(port_id, 0, 0))
+    {
+        printk("Failed to disable rx/tx for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    return 0;
+}
+
+static int port_lport_cfg_get(mac_dev_t *mac_dev, mac_cfg_t *mac_cfg)
+{
+    uint32_t port_id = mac_dev->mac_id;
+    lport_port_cfg_s port_cfg = {};
+    lport_flow_ctrl_cfg_s flow_ctrl = {};
+    memset(mac_cfg, 0, sizeof(mac_cfg_t));
+
+    if (lport_get_port_configuration(port_id, &port_cfg))
+    {
+        printk("Failed to get configuration for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    if (lport_get_pause_configuration(port_id, &flow_ctrl))
+    {
+        printk("Failed to get flow ctrl for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    if (port_cfg.speed == LPORT_RATE_10MB)
+        mac_cfg->speed = MAC_SPEED_10;
+    else if (port_cfg.speed== LPORT_RATE_100MB)
+        mac_cfg->speed = MAC_SPEED_100;
+    else if (port_cfg.speed== LPORT_RATE_1000MB)
+        mac_cfg->speed = MAC_SPEED_1000;
+    else if (port_cfg.speed== LPORT_RATE_2500MB)
+        mac_cfg->speed = MAC_SPEED_2500;
+    else if (port_cfg.speed== LPORT_RATE_10G)
+        mac_cfg->speed = MAC_SPEED_10000;
+    else
+        mac_cfg->speed = MAC_SPEED_UNKNOWN;
+
+    if (mac_cfg->speed != MAC_SPEED_UNKNOWN)
+        mac_cfg->duplex = MAC_DUPLEX_FULL;
+
+    return 0;
+}
+
+static int port_lport_cfg_set(mac_dev_t *mac_dev, mac_cfg_t *mac_cfg)
+{
+    uint32_t port_id = mac_dev->mac_id;
+    lport_port_cfg_s port_cfg = {};
+
+    if (lport_get_port_configuration(port_id, &port_cfg))
+    {
+        printk("Failed to get configuration for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    if (mac_cfg->speed == MAC_SPEED_10)
+        port_cfg.speed = LPORT_RATE_10MB;
+    else if (mac_cfg->speed == MAC_SPEED_100)
+        port_cfg.speed = LPORT_RATE_100MB;
+    else if (mac_cfg->speed == MAC_SPEED_1000)
+        port_cfg.speed = LPORT_RATE_1000MB;
+    else if (mac_cfg->speed == MAC_SPEED_2500)
+        port_cfg.speed = LPORT_RATE_2500MB;
+    else if (mac_cfg->speed == MAC_SPEED_10000)
+        port_cfg.speed = LPORT_RATE_10G;
+    else
+        port_cfg.speed = LPORT_RATE_UNKNOWN;
+
+    port_cfg.throt_num = 0x00;
+    port_cfg.throt_denom = 0x00;
+
+    if (mac_cfg->speed == MAC_SPEED_5000)
+    {
+        port_cfg.throt_num = 0x3f;
+        port_cfg.throt_denom = 0x3f;
+        port_cfg.speed = LPORT_RATE_10G;
+    }
+
+    if (lport_set_port_configuration(port_id, &port_cfg))
+    {
+        printk("Failed to set configuration for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    return 0;
+}
+
+static int port_lport_pause_get(mac_dev_t *mac_dev, int *rx_enable, int *tx_enable)
+{
+    uint32_t port_id = mac_dev->mac_id;
+    lport_flow_ctrl_cfg_s flow_ctrl = {};
+
+    if (lport_get_pause_configuration(port_id, &flow_ctrl))
+    {
+        printk("Failed to get flow ctrl for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    *rx_enable = flow_ctrl.rx_pause_en ? 1 : 0;
+    *tx_enable = flow_ctrl.tx_pause_en ? 1 : 0;
+
+    return 0;
+}
+
+static int port_lport_pause_set(mac_dev_t *mac_dev, int rx_enable, int tx_enable, char *src_addr)
+{
+    uint32_t port_id = mac_dev->mac_id;
+    lport_flow_ctrl_cfg_s flow_ctrl = {};
+    char mac_addr[8] = {};
+    int i;
+
+    if (lport_get_pause_configuration(port_id, &flow_ctrl))
+    {
+        printk("Failed to get flow ctrl for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    flow_ctrl.rx_pause_en = rx_enable ? 1 : 0;
+    flow_ctrl.tx_pause_en = tx_enable ? 1 : 0;
+
+    if (src_addr)
+    {
+        for (i = 0; i < 6 ;i++)
+            mac_addr[5 - i] = src_addr[i];
+
+        flow_ctrl.tx_ctrl_sa = *(uint64_t *)mac_addr;
+    }
+
+    if (lport_set_pause_configuration(port_id, &flow_ctrl))
+    {
+        printk("Failed to set flow ctrl for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    return 0;
+}
+
+static int port_lport_stats_get(mac_dev_t *mac_dev, mac_stats_t *mac_stats)
+{
+    uint32_t port_id = mac_dev->mac_id;
+    lport_rx_stats_s rx_stats;
+    lport_tx_stats_s tx_stats;
+
+    if (lport_stats_get_rx(port_id, &rx_stats))
+    {
+        printk("Failed to get rx counters for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    if (lport_stats_get_tx(port_id, &tx_stats))
+    {
+        printk("Failed to get tx counters for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    mac_stats->rx_byte = rx_stats.GRXBYT + rx_stats.GRXRBYT;
+    mac_stats->rx_packet = rx_stats.GRXPOK;
+    mac_stats->rx_frame_64 = rx_stats.GRX64;
+    mac_stats->rx_frame_65_127 = rx_stats.GRX127;
+    mac_stats->rx_frame_128_255 = rx_stats.GRX255;
+    mac_stats->rx_frame_256_511 = rx_stats.GRX511;
+    mac_stats->rx_frame_512_1023 = rx_stats.GRX1023;
+    mac_stats->rx_frame_1024_1518 = rx_stats.GRX1518;
+    mac_stats->rx_frame_1519_mtu = rx_stats.GRX2047 + rx_stats.GRX4095 +
+        rx_stats.GRX9216 + rx_stats.GRX16383;
+    mac_stats->rx_multicast_packet = rx_stats.GRXMCA;
+    mac_stats->rx_broadcast_packet = rx_stats.GRXBCA;
+    mac_stats->rx_unicast_packet = rx_stats.GRXUCA;
+    mac_stats->rx_alignment_error = rx_stats.GRXALN;
+    mac_stats->rx_frame_length_error = rx_stats.GRXFLR;
+    mac_stats->rx_code_error = rx_stats.GRXFRERR;
+    mac_stats->rx_carrier_sense_error = rx_stats.GRXFCR;
+    mac_stats->rx_fcs_error = rx_stats.GRXFCS;
+    mac_stats->rx_undersize_packet = rx_stats.GRXUND;
+    mac_stats->rx_oversize_packet = rx_stats.GRXOVR;
+    mac_stats->rx_fragments = rx_stats.GRXFRG;
+    mac_stats->rx_jabber = rx_stats.GRXJBR;
+    mac_stats->rx_overflow = rx_stats.GRXTRFU;
+    mac_stats->rx_control_frame = rx_stats.GRXCF;
+    mac_stats->rx_pause_control_frame = rx_stats.GRXPF;
+    mac_stats->rx_unknown_opcode = rx_stats.GRXUO;
+    mac_stats->tx_byte = tx_stats.GTXBYT;
+    mac_stats->tx_packet = tx_stats.GTXPOK;
+    mac_stats->tx_frame_64 = tx_stats.GTX64;
+    mac_stats->tx_frame_65_127 = tx_stats.GTX127;
+    mac_stats->tx_frame_128_255 = tx_stats.GTX255;
+    mac_stats->tx_frame_256_511 = tx_stats.GTX511;
+    mac_stats->tx_frame_512_1023 = tx_stats.GTX1023;
+    mac_stats->tx_frame_1024_1518 = tx_stats.GTX1518;
+    mac_stats->tx_frame_1519_mtu = tx_stats.GTX2047 + tx_stats.GTX4095 +
+        tx_stats.GTX9216 + tx_stats.GTX16383;
+    mac_stats->tx_fcs_error = tx_stats.GTXFCS;
+    mac_stats->tx_multicast_packet = tx_stats.GTXMCA;
+    mac_stats->tx_broadcast_packet = tx_stats.GTXBCA;
+    mac_stats->tx_unicast_packet = tx_stats.GTXUCA;
+    mac_stats->tx_total_collision = tx_stats.GTXNCL;
+    mac_stats->tx_jabber_frame = tx_stats.GTXJBR;
+    mac_stats->tx_oversize_frame = tx_stats.GTXOVR;
+    mac_stats->tx_undersize_frame = tx_stats.GTXRPKT;
+    mac_stats->tx_fragments_frame = tx_stats.GTXFRG;
+    mac_stats->tx_error = tx_stats.GTXERR;
+    mac_stats->tx_underrun = tx_stats.GTXUFL;
+    mac_stats->tx_excessive_collision = tx_stats.GTXXCL;
+    mac_stats->tx_late_collision = tx_stats.GTXLCL;
+    mac_stats->tx_single_collision = tx_stats.GTXSCL;
+    mac_stats->tx_multiple_collision = tx_stats.GTXMCL;
+    mac_stats->tx_pause_control_frame = tx_stats.GTXPF;
+    mac_stats->tx_deferral_packet = tx_stats.GTXDFR;
+    mac_stats->tx_excessive_deferral_packet = tx_stats.GTXEDF;
+    mac_stats->tx_control_frame = tx_stats.GTXCF;
+    mac_stats->tx_fifo_errors = tx_stats.GTXUFL;
+
+    return 0;
+}
+
+static int port_lport_mtu_set(mac_dev_t *mac_dev, int mtu)
+{
+    uint32_t port_id = mac_dev->mac_id;
+
+    if (lport_port_mtu_set(port_id, mtu))
+    {
+        printk("Failed to set mtu to %d for lport mac %d\n", mtu, port_id);
+        return -1;
+    }
+
+    return 0;
+}
+
+static int port_lport_eee_set(mac_dev_t *mac_dev, int enable)
+{
+    uint32_t port_id = mac_dev->mac_id;
+
+    if (lport_port_eee_set(port_id, enable))
+    {
+        printk("Failed to set eee to %d for lport mac %d\n", enable, port_id);
+        return -1;
+    }
+
+    return 0;
+}
+
+static int port_lport_stats_clear(mac_dev_t *mac_dev)
+{
+    uint32_t port_id = mac_dev->mac_id;
+
+    if (lport_stats_reset(port_id))
+    {
+        printk("Failed to clear stats for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    return 0;
+}
+
+static int port_lport_dev_add(mac_dev_t *mac_dev)
+{
+    uint32_t port_id = mac_dev->mac_id;
+
+    lport_init.prt_mux_sel[port_id] = (LPORT_PORT_MUX_SELECT)mac_dev->priv;
+
+    return 0;
+}
+
+static int port_lport_dev_del(mac_dev_t *mac_dev)
+{
+    uint32_t port_id = mac_dev->mac_id;
+
+    lport_init.prt_mux_sel[port_id] = PORT_UNAVAIL;
+
+    return 0;
+}
+
+static int port_lport_drv_init(mac_drv_t *mac_drv)
+{
+    if (lport_init_driver(&lport_init))
+    {
+        printk("Failed to initialize the lport driver\n");
+        return -1;
+    }
+
+    mac_drv->initialized = 1;
+
+    return 0;
+}
+
+static int port_lport_loopback_set(mac_dev_t *mac_dev, mac_loopback_t loopback_set)
+{
+    uint32_t port_id = mac_dev->mac_id;
+    lport_port_cfg_s port_cfg = {};
+
+    if (lport_get_port_configuration(port_id, &port_cfg))
+    {
+        printk("Failed to get configuration for lport mac %d\n", port_id);
+        return -1;
+    }
+    
+    if (loopback_set == MAC_LOOPBACK_NONE)
+    {
+        port_cfg.local_loopback = 0;
+    }
+    else if (loopback_set == MAC_LOOPBACK_LOCAL)
+    {
+        port_cfg.local_loopback = 1;
+    }
+    else
+    {
+        printk("Not support the loopback setting %d\n", loopback_set);
+        return -1;
+    }
+    
+    if (lport_set_port_configuration(port_id, &port_cfg))
+    {
+        printk("Failed to set configuration for lport mac %d\n", port_id);
+        return -1;
+    }
+
+    return 0;
+}
+
+static int port_lport_dt_priv(const dt_handle_t handle, int mac_id, void **priv)
+{
+    uint32_t mux_sel = PORT_UNAVAIL;
+    phy_mii_type_t mii_type;
+    const dt_handle_t phy_handle = dt_parse_phandle(handle, "phy-handle", 0);
+
+    mii_type = dt_get_phy_mode_mii_type(handle);
+    switch (mii_type)
+    {
+        case PHY_MII_TYPE_GMII:
+            mux_sel = PORT_GPHY;
+            break;
+        case PHY_MII_TYPE_RGMII:
+            mux_sel = PORT_RGMII;
+            lport_init.rgmii_cfg[mac_id - LPORT_FIRST_RGMII_PORT].is_1p8v = dt_property_read_bool(handle, "rgmii-1p8v");
+            lport_init.rgmii_cfg[mac_id - LPORT_FIRST_RGMII_PORT].delay_rx = dt_property_read_bool(handle, "rx-delay");
+            lport_init.rgmii_cfg[mac_id - LPORT_FIRST_RGMII_PORT].delay_tx = dt_property_read_bool(handle, "tx-delay");
+            lport_init.rgmii_cfg[mac_id - LPORT_FIRST_RGMII_PORT].phy_attached = dt_is_valid(phy_handle) ? 1 : 0;
+            lport_init.has_rgmii_cfg = 1;
+            break;
+        case PHY_MII_TYPE_HSGMII:
+            mux_sel = PORT_HSGMII;
+            break;
+        case PHY_MII_TYPE_XFI:
+            mux_sel = PORT_XFI;
+            break;
+        case PHY_MII_TYPE_SGMII:
+#ifdef CONFIG_BCM_FTTDP_G9991
+                mux_sel = PORT_SGMII;
+#else
+            if (dt_is_valid(phy_handle))
+                mux_sel = PORT_SGMII_AN_SLAVE;
+            else
+                mux_sel = PORT_SGMII_AN_IEEE_CL37;
+#endif
+            break;
+        default:
+            break;
+    }
+
+    *priv = (void *)(unsigned long)mux_sel;
+
+    return 0;
+}
+
+mac_drv_t mac_drv_lport =
+{
+    .mac_type = MAC_TYPE_LPORT,
+    .name = "LPORT",
+    .init = port_lport_init,
+    .enable = port_lport_enable,
+    .disable = port_lport_disable,
+    .cfg_get = port_lport_cfg_get,
+    .cfg_set = port_lport_cfg_set,
+    .pause_get = port_lport_pause_get,
+    .pause_set = port_lport_pause_set,
+    .stats_get = port_lport_stats_get,
+    .stats_clear = port_lport_stats_clear,
+    .mtu_set = port_lport_mtu_set,
+    .eee_set = port_lport_eee_set,
+    .dev_add = port_lport_dev_add,
+    .dev_del = port_lport_dev_del,
+    .drv_init = port_lport_drv_init,
+    .loopback_set = port_lport_loopback_set,
+    .dt_priv = port_lport_dt_priv,
+};
+
diff --git a/drivers/net/bcmbca/phy/mac_drv_unimac.c b/drivers/net/bcmbca/phy/mac_drv_unimac.c
new file mode 100644
index 0000000000..c78c7bc459
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mac_drv_unimac.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Jan 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#include "mac_drv.h"
+#include "mac_drv_unimac.h"
+#include "unimac_drv.h"         // for MAX_NUM_OF_EMACS
+#include "dt_access.h"
+
+static mac_stats_t cached_stats[MAX_NUM_OF_EMACS];
+
+static int port_unimac_init(mac_dev_t *mac_dev)
+{
+    rdpa_emac emac = mac_dev->mac_id;
+    unsigned long flags = (unsigned long)(mac_dev->priv);
+
+    mac_hwapi_init_emac(emac);
+    mac_hwapi_set_external_conf(emac, 0);
+    mac_hwapi_set_unimac_cfg(emac, flags & UNIMAC_DRV_PRIV_FLAG_GMII_DIRECT);
+
+    if (flags & UNIMAC_DRV_PRIV_FLAG_EXTSW_CONNECTED)
+    {
+        mac_hwapi_set_tx_min_pkt_size(emac, 64);
+#if defined(CONFIG_BCM947622)
+        // turn on rx fc by default to accept pause from external switch
+        mac_dev->mac_drv->pause_set(mac_dev, 1, 0, NULL);
+#else
+        mac_hwapi_set_backpressure_ext(emac, 1);
+#endif //!47622
+    }
+    if (flags & UNIMAC_DRV_PRIV_FLAG_SHRINK_IPG)
+    {
+        mac_hwapi_set_tx_igp_len(emac, 8);
+    }
+
+    return 0;
+}
+
+static int port_unimac_enable(mac_dev_t *mac_dev)
+{
+    rdpa_emac emac = mac_dev->mac_id;
+
+    mac_hwapi_set_rxtx_enable(emac, 1, 1);
+
+    return 0;
+}
+
+static int port_unimac_disable(mac_dev_t *mac_dev)
+{
+    rdpa_emac emac = mac_dev->mac_id;
+
+    mac_hwapi_set_rxtx_enable(emac, 0, 0);
+
+    return 0;
+}
+
+static int port_unimac_cfg_get(mac_dev_t *mac_dev, mac_cfg_t *mac_cfg)
+{
+    rdpa_emac emac = mac_dev->mac_id;
+    rdpa_emac_cfg_t emac_cfg = {};
+    memset(mac_cfg, 0, sizeof(mac_cfg_t));
+
+    mac_hwapi_get_configuration(emac, &emac_cfg);
+
+    if (emac_cfg.rate == rdpa_emac_rate_10m)
+        mac_cfg->speed = MAC_SPEED_10;
+    else if (emac_cfg.rate == rdpa_emac_rate_100m)
+        mac_cfg->speed = MAC_SPEED_100;
+    else if (emac_cfg.rate == rdpa_emac_rate_1g)
+        mac_cfg->speed = MAC_SPEED_1000;
+    else if (emac_cfg.rate == rdpa_emac_rate_2_5g)
+        mac_cfg->speed = MAC_SPEED_2500;
+    else
+        mac_cfg->speed = MAC_SPEED_UNKNOWN;
+
+    if (mac_cfg->speed != MAC_SPEED_UNKNOWN)
+        mac_cfg->duplex = emac_cfg.full_duplex ? MAC_DUPLEX_FULL : MAC_DUPLEX_HALF;
+
+    return 0;
+}
+
+static int port_unimac_cfg_set(mac_dev_t *mac_dev, mac_cfg_t *mac_cfg)
+{
+    rdpa_emac emac = mac_dev->mac_id;
+    rdpa_emac_cfg_t emac_cfg = {};
+
+    mac_hwapi_get_configuration(emac, &emac_cfg);
+
+    if (mac_cfg->speed == MAC_SPEED_10)
+        emac_cfg.rate = rdpa_emac_rate_10m;
+    else if (mac_cfg->speed == MAC_SPEED_100)
+        emac_cfg.rate = rdpa_emac_rate_100m;
+    else if (mac_cfg->speed == MAC_SPEED_1000)
+        emac_cfg.rate = rdpa_emac_rate_1g;
+    else if (mac_cfg->speed == MAC_SPEED_2500)
+        emac_cfg.rate = rdpa_emac_rate_2_5g;
+    else
+        return -1;
+
+    emac_cfg.full_duplex = mac_cfg->duplex == MAC_DUPLEX_FULL ? 1 : 0;
+
+    mac_hwapi_set_configuration(emac, &emac_cfg);
+
+    return 0;
+}
+
+static int port_unimac_pause_get(mac_dev_t *mac_dev, int *rx_enable, int *tx_enable)
+{
+    S_MAC_HWAPI_FLOW_CTRL flowControl;
+
+    mac_hwapi_get_flow_control(mac_dev->mac_id, &flowControl);
+    *rx_enable = flowControl.rxFlowEnable ? 1 : 0;
+    *tx_enable = flowControl.txFlowEnable ? 1 : 0;
+
+    return 0;
+}
+
+static int port_unimac_pause_set(mac_dev_t *mac_dev, int rx_enable, int tx_enable, char *src_addr)
+{
+    S_MAC_HWAPI_FLOW_CTRL flowControl;
+    bdmf_mac_t addr = {};
+
+    mac_hwapi_get_flow_control(mac_dev->mac_id, &flowControl);
+
+    flowControl.rxFlowEnable = rx_enable ? 1 : 0;
+    flowControl.txFlowEnable = tx_enable ? 1 : 0;
+
+    if (src_addr)
+        memcpy(addr.b, src_addr, sizeof(bdmf_mac_t));
+
+    mac_hwapi_set_flow_control(mac_dev->mac_id, &flowControl);
+    mac_hwapi_modify_flow_control_pause_pkt_addr(mac_dev->mac_id, addr);
+
+    return 0;
+}
+
+static int port_unimac_stats_get(mac_dev_t *mac_dev, mac_stats_t *mac_stats)
+{
+    rdpa_emac_stat_t stats;
+    rdpa_emac emac = mac_dev->mac_id;
+
+    /* TODO: lock */
+    /* rdpa counters are read and clear, need to store data into local cache */
+    mac_hwapi_get_rx_counters(emac, &stats.rx);
+    mac_hwapi_get_tx_counters(emac, &stats.tx);
+
+    cached_stats[emac].rx_byte += stats.rx.byte;
+    cached_stats[emac].rx_packet += stats.rx.packet;
+    cached_stats[emac].rx_frame_64 += stats.rx.frame_64;
+    cached_stats[emac].rx_frame_65_127 += stats.rx.frame_65_127;
+    cached_stats[emac].rx_frame_128_255 += stats.rx.frame_128_255;
+    cached_stats[emac].rx_frame_256_511 += stats.rx.frame_256_511;
+    cached_stats[emac].rx_frame_512_1023 += stats.rx.frame_512_1023;
+    cached_stats[emac].rx_frame_1024_1518 += stats.rx.frame_1024_1518;
+    cached_stats[emac].rx_frame_1519_mtu += stats.rx.frame_1519_mtu;
+    cached_stats[emac].rx_multicast_packet += stats.rx.multicast_packet;
+    cached_stats[emac].rx_broadcast_packet += stats.rx.broadcast_packet;
+    cached_stats[emac].rx_unicast_packet += stats.rx.unicast_packet;
+    cached_stats[emac].rx_alignment_error += stats.rx.alignment_error;
+    cached_stats[emac].rx_frame_length_error += stats.rx.frame_length_error;
+    cached_stats[emac].rx_code_error += stats.rx.code_error;
+    cached_stats[emac].rx_carrier_sense_error += stats.rx.carrier_sense_error;
+    cached_stats[emac].rx_fcs_error += stats.rx.fcs_error;
+    cached_stats[emac].rx_undersize_packet += stats.rx.undersize_packet;
+    cached_stats[emac].rx_oversize_packet += stats.rx.oversize_packet;
+    cached_stats[emac].rx_fragments += stats.rx.fragments;
+    cached_stats[emac].rx_jabber += stats.rx.jabber;
+    cached_stats[emac].rx_overflow += stats.rx.overflow;
+    cached_stats[emac].rx_control_frame += stats.rx.control_frame;
+    cached_stats[emac].rx_pause_control_frame += stats.rx.pause_control_frame;
+    cached_stats[emac].rx_unknown_opcode += stats.rx.unknown_opcode;
+    cached_stats[emac].tx_byte += stats.tx.byte;
+    cached_stats[emac].tx_packet += stats.tx.packet;
+    cached_stats[emac].tx_frame_64 += stats.tx.frame_64;
+    cached_stats[emac].tx_frame_65_127 += stats.tx.frame_65_127;
+    cached_stats[emac].tx_frame_128_255 += stats.tx.frame_128_255;
+    cached_stats[emac].tx_frame_256_511 += stats.tx.frame_256_511;
+    cached_stats[emac].tx_frame_512_1023 += stats.tx.frame_512_1023;
+    cached_stats[emac].tx_frame_1024_1518 += stats.tx.frame_1024_1518;
+    cached_stats[emac].tx_frame_1519_mtu += stats.tx.frame_1519_mtu;
+    cached_stats[emac].tx_fcs_error += stats.tx.fcs_error;
+    cached_stats[emac].tx_multicast_packet += stats.tx.multicast_packet;
+    cached_stats[emac].tx_broadcast_packet += stats.tx.broadcast_packet;
+    cached_stats[emac].tx_unicast_packet += stats.tx.unicast_packet;
+    cached_stats[emac].tx_total_collision += stats.tx.total_collision;
+    cached_stats[emac].tx_jabber_frame += stats.tx.jabber_frame;
+    cached_stats[emac].tx_oversize_frame += stats.tx.oversize_frame;
+    cached_stats[emac].tx_undersize_frame += stats.tx.undersize_frame;
+    cached_stats[emac].tx_fragments_frame += stats.tx.fragments_frame;
+    cached_stats[emac].tx_error += stats.tx.error;
+    cached_stats[emac].tx_underrun += stats.tx.underrun;
+    cached_stats[emac].tx_excessive_collision += stats.tx.excessive_collision;
+    cached_stats[emac].tx_late_collision += stats.tx.late_collision;
+    cached_stats[emac].tx_single_collision += stats.tx.single_collision;
+    cached_stats[emac].tx_multiple_collision += stats.tx.multiple_collision;
+    cached_stats[emac].tx_pause_control_frame += stats.tx.pause_control_frame;
+    cached_stats[emac].tx_deferral_packet += stats.tx.deferral_packet;
+    cached_stats[emac].tx_excessive_deferral_packet += stats.tx.excessive_deferral_packet;
+    cached_stats[emac].tx_control_frame += stats.tx.control_frame;
+
+    memcpy(mac_stats, &cached_stats[emac], sizeof(mac_stats_t));
+
+    /* TODO: unlock */
+
+    return 0;
+}
+
+static int port_unimac_stats_clear(mac_dev_t *mac_dev)
+{
+    rdpa_emac emac = mac_dev->mac_id;
+    rdpa_emac_stat_t stats;
+    
+    mac_hwapi_get_rx_counters(emac, &stats.rx);
+    mac_hwapi_get_tx_counters(emac, &stats.tx);
+
+    memset(&cached_stats[emac], 0, sizeof(cached_stats[0]));
+
+    return 0;
+}
+
+static int port_unimac_mtu_set(mac_dev_t *mac_dev, int mtu)
+{
+    rdpa_emac emac = mac_dev->mac_id;
+
+    mac_hwapi_set_rx_max_frame_len(emac, mtu);
+
+    return 0;
+}
+
+static int port_unimac_eee_set(mac_dev_t *mac_dev, int enable)
+{
+    rdpa_emac emac = mac_dev->mac_id;
+
+    mac_hwapi_set_eee(emac, enable);
+
+    return 0;
+}
+
+static int port_unimac_loopback_set(mac_dev_t *mac_dev, mac_loopback_t loopback_set)
+{
+    rdpa_emac emac = mac_dev->mac_id;
+    MAC_LPBK loopback;
+
+    switch (loopback_set)
+    {
+        case MAC_LOOPBACK_NONE:
+            loopback = MAC_LPBK_NONE;
+            break;
+
+        case MAC_LOOPBACK_LOCAL:
+            loopback = MAC_LPBK_LOCAL;
+            break;
+
+        case MAC_LOOPBACK_REMOTE:
+            loopback = MAC_LPBK_REMOTE;
+            break;
+
+        case MAC_LOOPBACK_BOTH:
+            loopback = MAC_LPBK_BOTH;
+            break;
+
+        default:
+            return -1;
+    }
+
+    mac_hwapi_set_loopback(emac, loopback);
+
+    return 0;
+}
+
+static int port_unimac_dt_priv(const dt_handle_t handle, int mac_id, void **priv)
+{
+    unsigned long unimac_flags = 0;
+
+    if (dt_property_read_bool(handle, "gmii-direct"))
+        unimac_flags |= UNIMAC_DRV_PRIV_FLAG_GMII_DIRECT;
+
+    *priv = (void *)(unsigned long)unimac_flags;
+
+    return 0;
+}
+
+mac_drv_t mac_drv_unimac =
+{
+    .mac_type = MAC_TYPE_UNIMAC,
+    .name = "UNIMAC",
+    .init = port_unimac_init,
+    .enable = port_unimac_enable,
+    .disable = port_unimac_disable,
+    .cfg_get = port_unimac_cfg_get,
+    .cfg_set = port_unimac_cfg_set,
+    .pause_get = port_unimac_pause_get,
+    .pause_set = port_unimac_pause_set,
+    .stats_get = port_unimac_stats_get,
+    .stats_clear = port_unimac_stats_clear,
+    .mtu_set = port_unimac_mtu_set,
+    .eee_set = port_unimac_eee_set,
+    .loopback_set = port_unimac_loopback_set,
+    .dt_priv = port_unimac_dt_priv,
+};
+
diff --git a/drivers/net/bcmbca/phy/mac_drv_unimac.h b/drivers/net/bcmbca/phy/mac_drv_unimac.h
new file mode 100644
index 0000000000..e7a469b25d
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mac_drv_unimac.h
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2017 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Jun 2017
+ *      Author: steven.hsieh@broadcom.com
+ */
+
+#ifndef __MAC_DRV_UNIMAC_H__
+#define __MAC_DRV_UNIMAC_H__
+
+/* definition for mac_drv priv flags */
+#define UNIMAC_DRV_PRIV_FLAG_GMII_DIRECT        (1<<0)
+#define UNIMAC_DRV_PRIV_FLAG_EXTSW_CONNECTED    (1<<1)
+#define UNIMAC_DRV_PRIV_FLAG_SHRINK_IPG         (1<<2)  // for IMP port with clock speed can't support full line rate due to brcm tag
+
+#endif
+
diff --git a/drivers/net/bcmbca/phy/mako_a0_firmware.h b/drivers/net/bcmbca/phy/mako_a0_firmware.h
new file mode 100644
index 0000000000..64d056af02
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mako_a0_firmware.h
@@ -0,0 +1,7331 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Aug 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Firmware for external 2.5G/5G/10G phys: Mako BCM84860, BCM84861
+ */
+
+char mako_a0_version[] = "Mako A0 v01-00-03-2017-02-10";
+
+uint32_t mako_a0_firmware[] = {
+    0xea000016, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe320f000, 0xe59ff018, 0xe59ff018, 
+    0x00000200, 0x0002e194, 0x0002e0f4, 0x0002d4a8, 0x0002cefc, 0x00000000, 0x0002d204, 0x0002cfe4, 
+    0x00032588, 0xc0de512e, 0x00000000, 0x00000000, 0x00006430, 0x000007f8, 0x000391b0, 0xd03c801a, 
+    0xe59f0170, 0xe5901000, 0xe3510000, 0x0a000004, 0xe3a01000, 0xe5801000, 0xe59f015c, 0xe5801000, 
+    0xea000006, 0xe59f0154, 0xe580e000, 0xe59f0148, 0xe5901000, 0xe2811001, 0xe5801000, 0xe25ef004, 
+    0xe59f113c, 0xe3a0011a, 0xe5810000, 0xe59f1134, 0xee091f11, 0xe59fa130, 0xe59fb130, 0xe59fc130, 
+    0xe51f0088, 0xe51f1088, 0xe1a02000, 0xe1500001, 0x1a000003, 0xee110f30, 0xe3c0040e, 0xee010f30, 
+    0xea000036, 0xe3a01806, 0xe51f2098, 0xe2820004, 0xe8a00002, 0xe1500001, 0x3afffffc, 0xe51f00bc, 
+    0xe3500000, 0x1a00002d, 0xe51f20b8, 0xe3a01000, 0xe1cc10b0, 0xe3e00000, 0xe59f70d8, 0xe3a09008, 
+    0xe4d13001, 0xe3a08000, 0xe7e043d3, 0xe7e05fd0, 0xe0346005, 0xe1a00080, 0x0a000000, 0xe0200007, 
+    0xe1a03083, 0xe2888001, 0xe1580009, 0xbafffff5, 0xe1510002, 0xbafffff1, 0xe5912000, 0xe58a0000, 
+    0xe58b2000, 0xe3e03000, 0xe1520003, 0x0a000001, 0xe1500002, 0x1a000014, 0xe3a02916, 0xe51f3134, 
+    0xe0821003, 0xe51f314c, 0xe8b30030, 0xe8a20030, 0xe1520001, 0x1afffffb, 0xe59f205c, 0xe51f3150, 
+    0xe0821003, 0xe51f316c, 0xe51f4160, 0xe0833004, 0xe8b30010, 0xe8a20010, 0xe1520001, 0x1afffffb, 
+    0xe3a03901, 0xe1cc30b0, 0xe51ff1b0, 0xe3a03902, 0xe1cc30b0, 0xeafffffe, 0xc300003c, 0xc3000038, 
+    0xc300000c, 0xc2000010, 0x00040021, 0x00000048, 0x0000004c, 0xd03c801a, 0x04c11db7, 0x0005f600, 
+    0xebffffff, 0xebffffff, 0xebffffff, 0xebffffff, 0xe3a01401, 0xee110f10, 0xe1800001, 0xe3c00a02, 
+    0xee010f10, 0xee110f30, 0xe3800040, 0xe3800501, 0xee010f30, 0xe59f0084, 0xe3a010d1, 0xe121f001, 
+    0xe1a0d000, 0xe3a010d2, 0xe121f001, 0xe2400080, 0xe1a0d000, 0xe3a010d7, 0xe121f001, 0xe2400c02, 
+    0xe1a0d000, 0xe3a010db, 0xe121f001, 0xe2400080, 0xe1a0d000, 0xe3a010d3, 0xe121f001, 0xe2400080, 
+    0xe1a0d000, 0xe3a010df, 0xe121f001, 0xe2400c02, 0xe1a0d000, 0xe3a010d3, 0xe121f001, 0xe59f0024, 
+    0xe59f1018, 0xe59f2024, 0xe4802004, 0xe1500001, 0xbafffffc, 0xeb000007, 0xe59fc014, 0xe12fff1c, 
+    0x00050800, 0x00050000, 0x0004cfec, 0x0004e5ec, 0xa5a5a5a5, 0x00000500, 0xe3a00701, 0xe3a02008, 
+    0xee191f11, 0xe2011d3e, 0xe1811000, 0xe1811102, 0xe3811001, 0xee091f11, 0xf57ff04f, 0xe12fff1e, 
+    0xc0c10000, 0x0140c181, 0x03c0c301, 0xc2410280, 0x06c0c601, 0xc7410780, 0xc5c10500, 0x0440c481, 
+    0x0cc0cc01, 0xcd410d80, 0xcfc10f00, 0x0e40ce81, 0xcac10a00, 0x0b40cb81, 0x09c0c901, 0xc8410880, 
+    0x18c0d801, 0xd9411980, 0xdbc11b00, 0x1a40da81, 0xdec11e00, 0x1f40df81, 0x1dc0dd01, 0xdc411c80, 
+    0xd4c11400, 0x1540d581, 0x17c0d701, 0xd6411680, 0x12c0d201, 0xd3411380, 0xd1c11100, 0x1040d081, 
+    0x30c0f001, 0xf1413180, 0xf3c13300, 0x3240f281, 0xf6c13600, 0x3740f781, 0x35c0f501, 0xf4413480, 
+    0xfcc13c00, 0x3d40fd81, 0x3fc0ff01, 0xfe413e80, 0x3ac0fa01, 0xfb413b80, 0xf9c13900, 0x3840f881, 
+    0xe8c12800, 0x2940e981, 0x2bc0eb01, 0xea412a80, 0x2ec0ee01, 0xef412f80, 0xedc12d00, 0x2c40ec81, 
+    0x24c0e401, 0xe5412580, 0xe7c12700, 0x2640e681, 0xe2c12200, 0x2340e381, 0x21c0e101, 0xe0412080, 
+    0x60c0a001, 0xa1416180, 0xa3c16300, 0x6240a281, 0xa6c16600, 0x6740a781, 0x65c0a501, 0xa4416480, 
+    0xacc16c00, 0x6d40ad81, 0x6fc0af01, 0xae416e80, 0x6ac0aa01, 0xab416b80, 0xa9c16900, 0x6840a881, 
+    0xb8c17800, 0x7940b981, 0x7bc0bb01, 0xba417a80, 0x7ec0be01, 0xbf417f80, 0xbdc17d00, 0x7c40bc81, 
+    0x74c0b401, 0xb5417580, 0xb7c17700, 0x7640b681, 0xb2c17200, 0x7340b381, 0x71c0b101, 0xb0417080, 
+    0x90c15000, 0x51409181, 0x53c09301, 0x92415280, 0x56c09601, 0x97415780, 0x95c15500, 0x54409481, 
+    0x5cc09c01, 0x9d415d80, 0x9fc15f00, 0x5e409e81, 0x9ac15a00, 0x5b409b81, 0x59c09901, 0x98415880, 
+    0x48c08801, 0x89414980, 0x8bc14b00, 0x4a408a81, 0x8ec14e00, 0x4f408f81, 0x4dc08d01, 0x8c414c80, 
+    0x84c14400, 0x45408581, 0x47c08701, 0x86414680, 0x42c08201, 0x83414380, 0x81c14100, 0x40408081, 
+    0xfa000000, 0xfb00003b, 0xe890a00a, 0x44820c00, 0xf1aa4483, 0x45da0701, 0xf000d101, 0xf2aff86e, 
+    0xe8ba0e09, 0xf013000f, 0xbf180f01, 0xf0431afb, 0x47180301, 0x0002f70c, 0x0002f79c, 0xf04f440a, 
+    0xf8100c00, 0xf0133b01, 0xbf080407, 0x4b01f810, 0xbf08111d, 0x5b01f810, 0xd0051e64, 0x6b01f810, 
+    0xf8011e64, 0xd1f96b01, 0x0f08f013, 0xf810bf1e, 0x1cad4b01, 0xd1091b0c, 0xbf581e6d, 0xcb01f801, 
+    0xe005d5fa, 0x6b01f814, 0x6b01f801, 0xd5f91e6d, 0xd3d64291, 0x00004770, 0xbf243a10, 0xc178c878, 
+    0x0752d8fa, 0xc830bf24, 0xbf44c130, 0x600c6804, 0x00004770, 0x24002300, 0x26002500, 0xbf283a10, 
+    0xd8fbc178, 0xbf280752, 0xbf48c130, 0x4770600b, 0xf02b2975, 0x296387c7, 0x8355f02c, 0xf02c2973, 
+    0x2000835a, 0xb51f4770, 0x0003e89d, 0xf8f1f02c, 0xf805f02c, 0xb510bd1f, 0xf02cbd10, 0x4611fc00, 
+    0xfff1f7ff, 0xf90af000, 0xfc1ef02c, 0xf7ffb403, 0xbc03fff2, 0xfc4cf02c, 0x6060f04f, 0x1f30ee11, 
+    0x0100ea41, 0x1f30ee01, 0x0f30ee11, 0x8f6ff3bf, 0x6060f04f, 0x1f30ee11, 0x0100ea01, 0x1f30ee01, 
+    0x0f30ee11, 0x8f6ff3bf, 0xee15b500, 0xf3bf0f10, 0xf85d8f6f, 0x4770eb04, 0xee16b500, 0xf3bf0f10, 
+    0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f11, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f31, 
+    0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f30, 0xf85d8f6f, 0x4770eb04, 0xee16b500, 0xf3bf0f50, 
+    0xf85d8f6f, 0x4770eb04, 0xee1fb500, 0xf3bf0f13, 0xf85d8f6f, 0x4770eb04, 0xe52de004, 0xe16f0f10, 
+    0xe49de004, 0xe12fff1e, 0x6800b500, 0xeb04f85d, 0xb5004770, 0xf85d6001, 0x4770eb04, 0xf9b0b500, 
+    0xf85d0000, 0x4770eb04, 0x8001b500, 0xeb04f85d, 0x00004770, 0x41f0e92d, 0xf04f480a, 0xf04f0100, 
+    0xf04f0201, 0xf44f0300, 0x4d076400, 0x80014f07, 0x883e8002, 0x6023f845, 0x0301f103, 0xdbf642a3, 
+    0x81f0e8bd, 0xd0030406, 0x00054000, 0xd003044c, 0x41f0e92d, 0x4f0c4b0b, 0x0100f04f, 0x0201f04f, 
+    0x0604f04f, 0x801a8019, 0x3b02f837, 0x4b02f837, 0x4303ea44, 0x3b04f840, 0x0101f101, 0xdbf342b1, 
+    0x81f0e8bd, 0xd0030406, 0xd0030418, 0x41f0e92d, 0x4a074b06, 0xf36f8819, 0x8019218a, 0x6180f441, 
+    0x42806810, 0x8019dcfc, 0x81f0e8bd, 0xd0035092, 0xc800010c, 0x41f0e92d, 0x4a074906, 0xf043880b, 
+    0x800b0310, 0x1304f36f, 0x42846814, 0x800bdcfc, 0x81f0e8bd, 0xd0035092, 0xc800010c, 0x41f0e92d, 
+    0x4908b672, 0xf1b06808, 0xd0050f00, 0x0000f04f, 0xb6626008, 0x81f0e8bd, 0xf3bfb662, 0xbf308f4f, 
+    0x81f0e8bd, 0x000361e4, 0xf8d1490b, 0x684ac000, 0x3b04f85c, 0x44186810, 0x0b04f842, 0xbf28458c, 
+    0x0cdcf1a1, 0xbf28428a, 0x02dcf1a1, 0xc000f8c1, 0xf020604a, 0x47704000, 0x0004cf84, 0xf003b510, 
+    0xbd10f803, 0x4afeb510, 0xb98a6812, 0x68124afd, 0xb16a4002, 0x68124afc, 0x6f00f5b2, 0x4afada08, 
+    0x68126813, 0x4cf81c52, 0x4af86022, 0x1023f842, 0xe92dbd10, 0x460641f0, 0x4615460c, 0x680048f1, 
+    0xb1c84030, 0x46301961, 0xffdcf7ff, 0xf0082000, 0x4607f837, 0x46304639, 0xffd4f7ff, 0x880048ec, 
+    0xf3c01c40, 0x49ea0009, 0x19606008, 0x680949e9, 0x68124ae7, 0x0022f841, 0x81f0e8bd, 0x4be1b530, 
+    0x4003681b, 0x4be2b16b, 0x1c5b881b, 0x0309f3c3, 0x60234cdf, 0x4cdf188b, 0x4ddd6824, 0xf844682d, 
+    0xbd303025, 0x4604b570, 0x4629460d, 0xf7ff4620, 0x2000ffa9, 0xf804f008, 0x46314606, 0xf7ff4620, 
+    0xbd70ffa1, 0xf008b510, 0xf040f816, 0x4621443a, 0x7000f04f, 0xff96f7ff, 0xf0072007, 0x4604fff1, 
+    0xf04f4621, 0xf7ff7000, 0xbd10ff8d, 0x4604b510, 0xf00948c9, 0x4621fc75, 0x4000f04f, 0xffd2f7ff, 
+    0x680148c5, 0x4000f04f, 0xff7cf7ff, 0x684148c2, 0x4000f04f, 0xff76f7ff, 0x688148bf, 0x4000f04f, 
+    0xff70f7ff, 0x68c148bc, 0x4000f04f, 0xff6af7ff, 0xe92dbd10, 0x460447f0, 0x4616460d, 0xe9dd461f, 
+    0x48af9a08, 0x28006800, 0x48afd051, 0xb9106800, 0x49ad2008, 0x48ac6008, 0x10c06800, 0x49aa00c0, 
+    0x48ae6008, 0x48a96801, 0x68124aa7, 0x1022f840, 0x48a54601, 0x1c406800, 0x4020f841, 0xf7ff48a8, 
+    0x4aa2fe93, 0x680949a0, 0xf8421c89, 0x46110021, 0x6800489d, 0xf8411cc0, 0x489b5020, 0x1d006800, 
+    0x6020f841, 0x68004898, 0xf8411d40, 0x48967020, 0x1d806800, 0x9020f841, 0x68004893, 0xf8411dc0, 
+    0x4891a020, 0x30086800, 0x31e8f240, 0xf2f1fb90, 0x0812fb01, 0x0f00f1b8, 0x4640dd01, 0x2008e000, 
+    0x60084989, 0x6800488d, 0x498c1c40, 0xe8bd6008, 0xe92d87f0, 0x460641f0, 0x1700f240, 0x040ef3c6, 
+    0xdc062cff, 0x4887b2e6, 0x5026f850, 0x460747a8, 0xf5b4e012, 0xda067f00, 0x4883b2e6, 0x5026f850, 
+    0x460747a8, 0xf5b4e008, 0xda054f50, 0x487fb2e6, 0x5026f850, 0x460747a8, 0x487db239, 0xfe44f7ff, 
+    0x487bb221, 0xf7ff3864, 0xf04ffe3f, 0x487831ff, 0xf7ff3010, 0x4977fe39, 0x300c4875, 0xfe34f7ff, 
+    0x81f0e8bd, 0x2102b510, 0xf7ff4871, 0x2108fe2d, 0xf7ff486f, 0xf241fe29, 0x486d1122, 0xf7ff1c80, 
+    0x2008fe23, 0xb510bd10, 0x48692102, 0xfe1cf7ff, 0x22042300, 0x48682110, 0xfc11f006, 0x22052300, 
+    0x48652120, 0xfc0bf006, 0x461a2300, 0x48602101, 0xf0063852, 0x2004fc04, 0xb510bd10, 0x485c2102, 
+    0xfe02f7ff, 0x2200230f, 0x485b4619, 0xfbf7f006, 0x7107f240, 0x1c804858, 0xfdf6f7ff, 0x7107f240, 
+    0x1d004855, 0xfdf0f7ff, 0x22042301, 0x48522110, 0xfbe5f006, 0x22052301, 0x484f2120, 0xfbdff006, 
+    0x22002301, 0x484a4619, 0xf0063852, 0x2004fbd8, 0xb510bd10, 0x38524846, 0xfdd0f7ff, 0x0401f000, 
+    0x48434621, 0xf7ff1c80, 0x2004fdcf, 0xb510bd10, 0x483f2102, 0xfdc8f7ff, 0x52b8f04f, 0x20082102, 
+    0xfe77f7ff, 0x1d00483a, 0xfdb8f7ff, 0x8008493b, 0xfc89f007, 0x20402101, 0xfe36f007, 0xf00d2001, 
+    0x4836fff7, 0x22028800, 0x2100ea42, 0x52b8f04f, 0xf7ff2008, 0x2004fe5e, 0xb510bd10, 0x482c2102, 
+    0xfda2f7ff, 0x52b8f04f, 0x0100f248, 0xf7ff2008, 0x2100fe50, 0xf0062009, 0xb284fd28, 0x4621b2e4, 
+    0x1d004823, 0xfd90f7ff, 0x88004824, 0x4820b201, 0xf7ff1c80, 0x4821fd89, 0xf2488800, 0xea420200, 
+    0xf04f2100, 0x200852b8, 0xfe33f7ff, 0xbd102004, 0xf04fb510, 0xf24c52b8, 0x20080116, 0xfe29f7ff, 
+    0x48132102, 0xfd70f7ff, 0x48084c15, 0x48096020, 0x48056060, 0x480660a0, 0x480260e0, 0xe0216120, 
+    0x000362f4, 0x0005280c, 0x00052800, 0x00050800, 0x00052804, 0x00052808, 0x00038fe0, 0x000362f8, 
+    0xc800017c, 0x00036008, 0x00036120, 0x00036140, 0xd03c806e, 0xffff8000, 0xd003526c, 0x00036316, 
+    0x00048e38, 0x616048fc, 0x61a048fc, 0x61e048fc, 0x622048fc, 0x62602000, 0x62e062a0, 0x632048fa, 
+    0x63602000, 0x63a048f9, 0x63e048f9, 0x642048f9, 0x646048f9, 0x64a048f9, 0x64e02000, 0x48f86520, 
+    0x48f86560, 0x200065a0, 0x662065e0, 0x666048f6, 0x66a048f6, 0x66e048f6, 0x672048f6, 0x676048f6, 
+    0x67a02000, 0x48f567e0, 0x0080f8c4, 0xf8c448f4, 0x20000084, 0x0088f8c4, 0x008cf8c4, 0xf8c448f1, 
+    0x48f10090, 0x0094f8c4, 0xf8c42000, 0xf8c40098, 0xf8c4009c, 0xf8c400a0, 0xf8c400a4, 0xf8c400a8, 
+    0x48ea00ac, 0x00b0f8c4, 0xf8c448e9, 0x48e900b4, 0x00b8f8c4, 0xf826f027, 0x00bcf8c4, 0xf8c448e6, 
+    0x48e600c0, 0x00c4f8c4, 0xf8c448e5, 0x48e500c8, 0x00ccf8c4, 0xf8c448e4, 0x462000d0, 0x48e3b201, 
+    0xfcd2f7ff, 0x0c004620, 0x48e0b201, 0xf7ff1e80, 0x2135fccb, 0x1f8048dd, 0xfcc6f7ff, 0xbd102004, 
+    0xf04fb510, 0xf24852b8, 0x20080131, 0xfd71f7ff, 0x48d62102, 0xf7ff3808, 0x2000fcb7, 0xf833f02b, 
+    0x46214604, 0x1f8048d1, 0xfcaef7ff, 0xbd102004, 0xf04fb510, 0xf24852b8, 0x2008012f, 0xfd59f7ff, 
+    0x48ca2102, 0xf7ff3808, 0x2003fc9f, 0xf81bf02b, 0x46214604, 0x1f8048c5, 0xfc96f7ff, 0xf02b2004, 
+    0x4604f812, 0x48c14621, 0xf7ff1f00, 0x2005fc8d, 0xf809f02b, 0x46214604, 0x1e8048bc, 0xfc84f7ff, 
+    0xf02b2006, 0x4604f800, 0x48b84621, 0xfc7cf7ff, 0xbd102004, 0x2100b510, 0x386c48b4, 0xfc74f7ff, 
+    0x48b22120, 0xf7ff3808, 0x48b1fc6f, 0xf0408800, 0x49af0010, 0x20008008, 0x800849ae, 0x80482046, 
+    0x80882000, 0xf64080c8, 0x48a50100, 0xf9d4f02d, 0x0100f640, 0xf02d48a8, 0xbd10f9bf, 0xf04fb510, 
+    0xf24c52b8, 0x20080102, 0xfd03f7ff, 0x489f2102, 0xf7ff3808, 0x48a1fc49, 0x489cb201, 0xfc44f7ff, 
+    0x0c00489e, 0x4899b201, 0xf7ff1e80, 0x2004fc3d, 0xb570bd10, 0x52b8f04f, 0x0100f24c, 0xf7ff2008, 
+    0x2102fce8, 0x38084891, 0xfc2ef7ff, 0xf7ff488f, 0xb285fc25, 0x1e80488d, 0xfc20f7ff, 0xeb05b286, 
+    0x88204406, 0x4889b201, 0xf7ff1f80, 0x2004fc1d, 0xb570bd70, 0x52b8f04f, 0x0101f24c, 0xf7ff2008, 
+    0x2102fcc8, 0x38084881, 0xfc0ef7ff, 0xf7ff487f, 0xb285fc05, 0x1e80487d, 0xfc00f7ff, 0xeb05b286, 
+    0x487a4406, 0xf7ff1f80, 0x8020fbf9, 0xbd702004, 0x2500b570, 0xf04f2600, 0xf24c52b8, 0x20080100, 
+    0xfca7f7ff, 0x48712102, 0xf7ff3808, 0x486ffbed, 0xfbe4f7ff, 0x486d4605, 0xf7ff1e80, 0x4606fbdf, 
+    0x4406eb05, 0xb2018820, 0x1f004868, 0xfbdcf7ff, 0x0c006820, 0x4865b201, 0xf7ff1f80, 0x2004fbd5, 
+    0xe92dbd70, 0xf04f41f0, 0xf24c52b8, 0x20080101, 0xfc7ff7ff, 0x485d2102, 0xf7ff3808, 0x485bfbc5, 
+    0xfbbcf7ff, 0x48594605, 0xf7ff1e80, 0x4606fbb7, 0x4406eb05, 0x1f004855, 0xfbb0f7ff, 0x48534607, 
+    0xf7ff1f80, 0xeb07fbab, 0x60204000, 0xe8bd2004, 0xb57081f0, 0x52b8f04f, 0x0111f24c, 0xf7ff2008, 
+    0x2102fc58, 0x38084849, 0xfb9ef7ff, 0x24004e2c, 0x2500e011, 0x494ae00b, 0xfb022202, 0xf7ff1005, 
+    0xeb05fb8d, 0xf82601c4, 0x1c680011, 0x2d08b205, 0x1c60dbf1, 0x2c40b204, 0x2004dbeb, 0xb510bd70, 
+    0x52b8f04f, 0x0112f24c, 0xf7ff2008, 0x2102fc32, 0x38084836, 0xfb78f7ff, 0xf7ff4834, 0xb280fb6f, 
+    0x60084938, 0x1e804831, 0xfb68f7ff, 0x4835b284, 0xea406800, 0x49334004, 0x20046008, 0xb510bd10, 
+    0x52b8f04f, 0x0113f24c, 0xf7ff2008, 0x2102fc12, 0x38084826, 0xfb58f7ff, 0x8800482a, 0x4823b201, 
+    0xfb52f7ff, 0x68004827, 0xb2010c00, 0x1e80481f, 0xfb4af7ff, 0xbd102004, 0x00052810, 0x00052850, 
+    0x00052890, 0x00052c90, 0x00043058, 0x00043078, 0x00044078, 0x00044088, 0x00044288, 0x000442c8, 
+    0x00044308, 0x00044b08, 0x00045308, 0x00047308, 0x00047b08, 0x00048308, 0x00048b08, 0xd0033070, 
+    0x00052f88, 0x00036354, 0x00037354, 0x000362d8, 0x000362e4, 0x00048c18, 0x0003634c, 0x00036350, 
+    0x00053000, 0x00054000, 0x000385aa, 0xd03c8076, 0x000362f0, 0x00036000, 0x00050800, 0x00048e38, 
+    0xd003612e, 0x0005280c, 0xf04fb510, 0xf24852b8, 0x20080104, 0xfbadf7ff, 0x48f82102, 0xfaf4f7ff, 
+    0xf99048f7, 0x48f51000, 0xf7ff1c80, 0x2004faed, 0xb510bd10, 0x52b8f04f, 0x0105f248, 0xf7ff2008, 
+    0x2102fb98, 0xf7ff48ed, 0x48ecfadf, 0xf7ff1c80, 0xb240fad5, 0x700849ea, 0xbd102004, 0xf04fb510, 
+    0xf24852b8, 0x20080107, 0xfb83f7ff, 0x48e32102, 0xfacaf7ff, 0x1c8048e1, 0xfac0f7ff, 0x700849e1, 
+    0x78004608, 0xd1062801, 0x1d0048dc, 0xfab6f7ff, 0x700849dd, 0x2000e002, 0x700849db, 0xbd102004, 
+    0xf04fb510, 0xf24852b8, 0x20080106, 0xfb61f7ff, 0x48d22102, 0xfaa8f7ff, 0x780148d2, 0x1c8048cf, 
+    0xfaa2f7ff, 0x780148d0, 0x1d0048cc, 0xfa9cf7ff, 0x780148ce, 0x1d8048c9, 0xfa96f7ff, 0xbd102004, 
+    0xf04fb510, 0xf24852b8, 0x20080109, 0xfb41f7ff, 0x48c22102, 0xfa88f7ff, 0x1c8048c0, 0xfa7ef7ff, 
+    0xf0044604, 0x49c20003, 0xf3c47008, 0x49c10081, 0xf3c47008, 0x49c01006, 0xf3c47008, 0x49bf20c1, 
+    0x48b67008, 0xf7ff1d00, 0x49bdfa69, 0x48b38008, 0xf7ff1d80, 0x49bbfa63, 0x48b08008, 0xf7ff3008, 
+    0x49b9fa5d, 0x48b58008, 0xf1c07800, 0x20200102, 0x1f004088, 0x700849b5, 0x780048ad, 0xdd0b2801, 
+    0x880048af, 0x48afb940, 0xf6408800, 0x42884135, 0x4608da02, 0x800849ab, 0x30c0f3c4, 0x2000b118, 
+    0x700849ab, 0x2001e002, 0x700849a9, 0x780048a0, 0xdd032800, 0x49a72001, 0xe0027008, 0x49a52000, 
+    0x489b7008, 0x28037800, 0x2000d102, 0x8008499e, 0xbd102004, 0xf04fb510, 0xf24852b8, 0x20080108, 
+    0xfad7f7ff, 0x488d2102, 0xfa1ef7ff, 0x78004893, 0x4a9102c0, 0xeb007812, 0x4a8e1002, 0xeb007812, 
+    0x4a8b0082, 0x44107812, 0x4884b201, 0xf7ff1c80, 0x488bfa0b, 0xb2018800, 0x1d004880, 0xfa04f7ff, 
+    0x88004888, 0x487db201, 0xf7ff1d80, 0x4886f9fd, 0xb2018800, 0x30084879, 0xf9f6f7ff, 0xbd102004, 
+    0xf04fb510, 0xf24852b8, 0x2008010b, 0xfaa1f7ff, 0x48722102, 0xf9e8f7ff, 0x1c804870, 0xf9def7ff, 
+    0x7008497d, 0xbd102004, 0xf04fb510, 0xf24852b8, 0x2008010a, 0xfa8df7ff, 0x48682102, 0xf9d4f7ff, 
+    0x78014875, 0x1c804865, 0xf9cef7ff, 0xbd102004, 0xf04fb510, 0xf24852b8, 0x2008013b, 0xfa79f7ff, 
+    0x485e2102, 0xf9c0f7ff, 0x1c80485c, 0xf9b6f7ff, 0x496ab240, 0x46087008, 0xb9087800, 0xfa41f025, 
+    0x52b8f04f, 0xf9904865, 0x20081000, 0xfa61f7ff, 0xbd102004, 0xf04fb510, 0xf24852b8, 0x2008013a, 
+    0xfa57f7ff, 0x484d2102, 0xf99ef7ff, 0xf990485b, 0x484a1000, 0xf7ff1c80, 0x2004f997, 0xb510bd10, 
+    0x52b8f04f, 0x010ff248, 0xf7ff2008, 0x2102fa42, 0xf7ff4842, 0x4841f989, 0xf7ff1c80, 0x4950f97f, 
+    0x20047008, 0xb510bd10, 0x52b8f04f, 0x010ef248, 0xf7ff2008, 0x2102fa2e, 0xf7ff4838, 0x4848f975, 
+    0x48367801, 0xf7ff1c80, 0x2004f96f, 0xb510bd10, 0x52b8f04f, 0x012bf248, 0xf7ff2008, 0x2102fa1a, 
+    0xf7ff482e, 0x483ff961, 0x482c7801, 0xf7ff1c80, 0x483df95b, 0x48297801, 0xf7ff1d00, 0x483bf955, 
+    0x48267801, 0xf7ff1d80, 0x4839f94f, 0x48237801, 0xf7ff3008, 0x4837f949, 0x48207801, 0xf7ff300a, 
+    0x2004f943, 0xb510bd10, 0x52b8f04f, 0x012cf248, 0xf7ff2008, 0x2102f9ee, 0xf7ff4818, 0x4817f935, 
+    0xf7ff1c80, 0x4927f92b, 0x48147008, 0xf7ff1d00, 0x4925f925, 0x48117008, 0xf7ff1d80, 0x4923f91f, 
+    0x480e7008, 0xf7ff3008, 0x4921f919, 0x480b7008, 0xf7ff300a, 0x491ff913, 0x481d7008, 0x481b7803, 
+    0x48197802, 0x48177801, 0xf02a7800, 0x4819fe81, 0xf02a7800, 0x2004ff00, 0x0000bd10, 0xd03c806e, 
+    0x00036318, 0x00038464, 0x00038465, 0x000384d7, 0x00036324, 0x00036325, 0x00036326, 0x00036340, 
+    0x0003632a, 0x0003632c, 0x0003632e, 0x00036327, 0x00036329, 0x00036320, 0x00038b1d, 0x00038db0, 
+    0x00038489, 0x0003848c, 0x0003848d, 0x0003848e, 0x0003848f, 0x00038490, 0x2102b5f8, 0xf7ff48fe, 
+    0x48fdf8d3, 0xf7ff1c80, 0xb246f8c9, 0x1d0048fa, 0xf8c4f7ff, 0x48f8b245, 0xf7ff1d80, 0xb247f8bf, 
+    0xd0082e01, 0x4bf52000, 0x4629463a, 0x20019000, 0xfb6bf005, 0x2400e00c, 0x48f1e008, 0x1005eb00, 
+    0x49ee5700, 0x0024f841, 0xb2441c60, 0xdbf42c10, 0xbdf82004, 0x4ff0e92d, 0x4680b087, 0xf04f46c1, 
+    0xbf000a00, 0x460e2100, 0xf1b8460f, 0xd1040f00, 0x46012000, 0xe8bdb007, 0xe0098ff0, 0x0959ea4f, 
+    0x4be02200, 0x46394630, 0xf934f02d, 0x460f4606, 0x0f01f1b9, 0x4630d8f2, 0xf02d4639, 0x2101fbab, 
+    0x46084081, 0xf02d9101, 0xe9cdfbd2, 0x46400104, 0xfbe4f02d, 0x0102e9cd, 0x2304e9dd, 0xf9d6f02d, 
+    0x460d4604, 0x2200e042, 0x33104bce, 0x46294620, 0xfbe8f02d, 0xe03cd200, 0x0b00f04f, 0x4622e029, 
+    0x4620462b, 0xf02d4629, 0x4604fc19, 0xf10a460d, 0x22000a01, 0x4380f04f, 0x46294620, 0xfd0cf02d, 
+    0x2101d815, 0xf00afa01, 0xfba1f02d, 0x460b4602, 0x0102e9cd, 0x49bb2000, 0xf9a8f02d, 0x463b4632, 
+    0x0104e9cd, 0xf8e6f02d, 0x460f4606, 0xf10be004, 0xf1bb0b01, 0xd3d20f10, 0x2200bf00, 0x4380f04f, 
+    0x46294620, 0xf992f02d, 0x460d4604, 0x0f10f1ba, 0xbf00d3b9, 0x46394630, 0xe92de78c, 0xb0844ff1, 
+    0xf7ff9804, 0x4680ff77, 0x4ba84aa7, 0xfd16f02d, 0x4ba84aa7, 0x0100e9cd, 0xf978f02d, 0x22004606, 
+    0xf02d4ba5, 0x4604fbcb, 0x3233f04f, 0xf02d4ba3, 0x2200fcf9, 0xe9cd4ba2, 0xf02d0102, 0x4682fbbf, 
+    0xfb28f02d, 0xb005b280, 0x8ff0e8bd, 0xf04fb51c, 0xf24852b8, 0x20080130, 0xf8abf7ff, 0x488e2102, 
+    0xfff2f7fe, 0x1c80488c, 0xffe8f7fe, 0x70084995, 0xf0084895, 0x2400fd75, 0x4993e008, 0x0024f851, 
+    0xffbbf7ff, 0x0014f82d, 0xb2441c60, 0xdbf42c04, 0x0000f8bd, 0x4880b201, 0xf7fe1d00, 0xf8bdffd5, 
+    0xb2010002, 0x1d80487c, 0xffcef7fe, 0x0004f8bd, 0x4879b201, 0xf7fe3008, 0xf8bdffc7, 0xb2010006, 
+    0x300a4875, 0xffc0f7fe, 0xbd1c2004, 0xf04fb510, 0xf24852b8, 0x2008011e, 0xf86bf7ff, 0x486e2102, 
+    0xffb2f7fe, 0x49772000, 0x23017008, 0x46192200, 0xf0054876, 0x4875fda4, 0xf7fe3044, 0x4604ff9f, 
+    0x48654621, 0xf7fe1c80, 0x4870ff9f, 0xf7fe3046, 0x4604ff95, 0x48604621, 0xf7fe1d00, 0x486bff95, 
+    0xf7fe3048, 0x4604ff8b, 0x485b4621, 0xf7fe1d80, 0x4866ff8b, 0xf7fe304a, 0x4604ff81, 0x48564621, 
+    0xf7fe3008, 0x2004ff81, 0xb510bd10, 0x52b8f04f, 0x0117f24c, 0xf7ff2008, 0x2102f82c, 0xf7fe484e, 
+    0x2000ff73, 0x6008495a, 0x0100f640, 0xf02c4859, 0x2100fcd3, 0x1c804848, 0xff66f7fe, 0xbd102004, 
+    0x4604b570, 0x4616460d, 0x22054623, 0x48422120, 0xf0053854, 0x462bfd54, 0xf242220d, 0x483e0100, 
+    0xf0053854, 0x484cfd4c, 0x22025d83, 0x483a211c, 0xf0053854, 0x2c01fd44, 0x4848d115, 0x28037800, 
+    0x4846d007, 0x28047800, 0x4844d003, 0x28057800, 0x4843d109, 0x22067803, 0x11c0f240, 0x3854482e, 
+    0xfd2df005, 0x2300e007, 0xf2402206, 0x482a11c0, 0xf0053854, 0xbd70fd24, 0xf04fb570, 0xf24c52b8, 
+    0x20080118, 0xffd5f7fe, 0x48232102, 0xff1cf7fe, 0x1c804821, 0xff12f7fe, 0x2d01b2c5, 0xf7fed103, 
+    0x4604feab, 0xf7fee002, 0x4604feb3, 0x481ab221, 0xf7fe1d80, 0x0c20ff09, 0x4817b201, 0xf7fe3008, 
+    0x2004ff03, 0xb510bd70, 0x52b8f04f, 0x012df248, 0xf7fe2008, 0x4823ffae, 0x480f7801, 0xf7fe1c80, 
+    0x4821fef3, 0x480c7801, 0xf7fe1d00, 0x2004feed, 0xb510bd10, 0x52b8f04f, 0x012ef248, 0xf7fe2008, 
+    0x4805ff98, 0xf7fe1c80, 0x4916fed9, 0x48027008, 0xf7fe1d00, 0xe029fed3, 0xd03c806e, 0x00052890, 
+    0x00038e90, 0x3ff00000, 0xb573eab3, 0x4030ab15, 0x4ea4a8c1, 0x400a9340, 0x40340000, 0x40333333, 
+    0x40240000, 0x00036349, 0x00038fe0, 0xd0030406, 0x00052800, 0x00050800, 0x0002f9aa, 0x000361ec, 
+    0x000384e3, 0x0003848b, 0x0003848a, 0x700849fc, 0x78014608, 0x780048fb, 0xf8eff028, 0xbd102004, 
+    0xf04fb510, 0xf24c52b8, 0x20080119, 0xff51f7fe, 0x2134f241, 0xf7fe48f4, 0x2102fe97, 0x380a48f2, 
+    0xfe92f7fe, 0x46204cf1, 0x48efb201, 0xf7fe1e80, 0x4620fe8b, 0xb2010c00, 0x1f0048eb, 0xfe84f7fe, 
+    0xfe32f7fe, 0xf7fe6020, 0x6060fe37, 0xfe3cf7fe, 0xf7fe60a0, 0x60e0fe41, 0xfe46f7fe, 0xf7fe6120, 
+    0x6160fe4b, 0xfe50f7fe, 0x210761a0, 0x380848de, 0xfe6af7fe, 0xbd102004, 0x5ffce92d, 0x52b8f04f, 
+    0x011bf24c, 0xf7fe2008, 0x2102ff14, 0x380a48d6, 0xfe5af7fe, 0x90012000, 0x380848d3, 0xfe4ef7fe, 
+    0x48d14607, 0xf7fe1f80, 0x4683fe49, 0x3800f3c7, 0x2903f3c7, 0x051ff007, 0x1602f3cb, 0x0a07f00b, 
+    0x11f4f240, 0x3000f44f, 0xff2cf7fe, 0xf44f4641, 0xf7fe3000, 0x4649fed7, 0x3000f44f, 0xfed2f7fe, 
+    0xf44f4629, 0xf7fe3000, 0x4631fecd, 0x3000f44f, 0xfec8f7fe, 0xf44f4651, 0xf7fe3000, 0x48bcfec3, 
+    0x1000f990, 0x3000f44f, 0xfebcf7fe, 0xf44f49b9, 0xf7fe3000, 0x48b6feb7, 0xb9307800, 0x22054643, 
+    0x48b52120, 0xfc0bf005, 0x48b1e01e, 0x28017800, 0x4643d107, 0x21202205, 0x302048af, 0xfbfff005, 
+    0x48abe012, 0x28027800, 0x4643d107, 0x21202205, 0x304048a9, 0xfbf3f005, 0x4643e006, 0x21202205, 
+    0x306048a5, 0xfbebf005, 0x780048a1, 0x464bb930, 0x210f2200, 0xf00548a0, 0xe01efbe2, 0x7800489c, 
+    0xd1072801, 0x2200464b, 0x489b210f, 0xf0053020, 0xe012fbd6, 0x78004896, 0xd1072802, 0x2200464b, 
+    0x4895210f, 0xf0053040, 0xe006fbca, 0x2200464b, 0x4891210f, 0xf0053060, 0x2300fbc2, 0x21f02204, 
+    0xf005488e, 0x2300fbbc, 0xf643461a, 0x488c71ff, 0xfb8ef005, 0xda262d1a, 0x0008f1ca, 0x0040eb00, 
+    0x71fff64f, 0x2000ea01, 0x22019000, 0xebc29800, 0x48830160, 0xf7fe3080, 0x2118fd9c, 0x1f004880, 
+    0xfd97f7fe, 0x2000f44f, 0x5046ea40, 0x6080f440, 0x0105ea40, 0x3078487a, 0xfd8bf7fe, 0x05082101, 
+    0xfe12f006, 0x2d1ae02d, 0x2d1bd006, 0x2d1cd008, 0x2d1dd008, 0xe007d10c, 0x2001240b, 0xe0099001, 
+    0xe007240f, 0xe0052410, 0x20012411, 0xe0019001, 0xbf00240b, 0x0570bf00, 0xf9924a65, 0xea402000, 
+    0x98013282, 0x4080ea42, 0x1044ea40, 0x0104ea40, 0x30784863, 0xfd5df7fe, 0x48612119, 0xf7fe1f00, 
+    0x485bfd58, 0xb9307800, 0x22042301, 0x485a2110, 0xfb55f005, 0x4856e01e, 0x28017800, 0x2301d107, 
+    0x21102204, 0x30204854, 0xfb49f005, 0x4850e012, 0x28027800, 0x2301d107, 0x21102204, 0x3040484e, 
+    0xfb3df005, 0x2301e006, 0x21102204, 0x3060484a, 0xfb35f005, 0xda062d1a, 0x221c2301, 0x48480719, 
+    0xf0053078, 0x2101fb05, 0xf0060508, 0xf240fdad, 0xf44f11f4, 0xf7fe3000, 0xf44ffe15, 0x99013000, 
+    0xfdc0f7fe, 0xf44f4621, 0xf7fe3000, 0x4939fdbb, 0x3000f44f, 0xfdb6f7fe, 0xe8bd2004, 0xb5109ffc, 
+    0x48312102, 0xf7fe380a, 0xf04ffd0f, 0xf24c52b8, 0x2008011c, 0xfdbdf7fe, 0x78014832, 0x3808482a, 
+    0xfd02f7fe, 0xbd102004, 0x2102b510, 0x380a4826, 0xfcfaf7fe, 0x52b8f04f, 0x011df24c, 0xf7fe2008, 
+    0x4821fda8, 0xf7fe3808, 0x4926fce9, 0x20047008, 0xb510bd10, 0x52b8f04f, 0x013ff248, 0xf7fe2008, 
+    0x2102fd98, 0x380a4818, 0xfcdef7fe, 0x38084816, 0xfcd4f7fe, 0x7008491c, 0x1f804813, 0xfccef7fe, 
+    0x7008491a, 0xbd102004, 0xf04fb510, 0xf24852b8, 0x2008013e, 0xfd7df7fe, 0x480b2102, 0xf7fe380a, 
+    0x4811fcc3, 0x48087801, 0xf7fe3808, 0x480ffcbd, 0x48057801, 0xf7fe1f80, 0x2004fcb7, 0x0000bd10, 
+    0x0003848a, 0x0003848b, 0xd03c8078, 0x00048e38, 0x000362b1, 0xdcba01f5, 0xd0030882, 0xd0030a04, 
+    0xd1800308, 0x00036348, 0x00036343, 0x00036342, 0xf04fb510, 0xf24852b8, 0x20080143, 0xfd49f7fe, 
+    0x48fe2102, 0xfc90f7fe, 0x1c8048fc, 0xfc86f7fe, 0x700849fb, 0xbd102004, 0xf04fb510, 0xf24852b8, 
+    0x20080142, 0xfd35f7fe, 0x48f42102, 0xfc7cf7fe, 0x780148f3, 0x1c8048f1, 0xfc76f7fe, 0xbd102004, 
+    0xf04fb570, 0xf24852b8, 0x20080144, 0xfd21f7fe, 0x48ea2102, 0xfc68f7fe, 0x780048ea, 0xd10b2801, 
+    0x21032200, 0x1c8048e5, 0xfa70f005, 0x2000b920, 0x700849e5, 0xf868f00d, 0x21032200, 0x1c8048df, 
+    0xfa64f005, 0x700849df, 0x211c2202, 0x1c8048db, 0xfa5cf005, 0x700849dd, 0x21202205, 0x1c8048d7, 
+    0xfa54f005, 0xd1102801, 0xf06f2208, 0x48d301ff, 0xf0051d00, 0x4606fa4b, 0xffa0f02c, 0x22004604, 
+    0xf02c4bd3, 0x4ad3fd93, 0x2206c203, 0x48cb2140, 0xf0051c80, 0x2801fa3b, 0x2200d10f, 0x48c721ff, 
+    0xf0051d00, 0x4606fa33, 0xff88f02c, 0x22004604, 0xf02c4bc9, 0x4ac9fd7b, 0x2207c203, 0x48bf2180, 
+    0xf0051c80, 0x2801fa23, 0x49c5d104, 0x4ac148c5, 0x1000e9c2, 0x01512208, 0x1c8048b8, 0xfa16f005, 
+    0xd1032801, 0x49c02000, 0xc2034abc, 0xf2402209, 0x48b22100, 0xf0051c80, 0x2801fa09, 0x2000d102, 
+    0x700849ba, 0xf240220a, 0x48ac4100, 0xf0051c80, 0x2801f9fd, 0x2000d102, 0x700849b5, 0xbd702004, 
+    0x41f0e92d, 0x52b8f04f, 0x0145f248, 0xf7fe2008, 0x2102fc90, 0xf7fe48a1, 0x48acfbd7, 0x22087803, 
+    0x01fff06f, 0x1c80489d, 0xf9c9f005, 0x780348a8, 0x21ff2200, 0x1c804899, 0xf9c1f005, 0x4b9c2200, 
+    0xc903499c, 0xff7af02c, 0xf02c4605, 0xb284fee3, 0x22084623, 0x01fff06f, 0x1d004890, 0xf9aff005, 
+    0x4b952200, 0xc9034995, 0xff68f02c, 0xf02c4605, 0xb284fed1, 0x22004623, 0x488821ff, 0xf0051d00, 
+    0x4888f99e, 0x22007803, 0x48842103, 0xf0051d80, 0x4885f996, 0x22027803, 0x4880210c, 0xf0051d80, 
+    0x4882f98e, 0x22047803, 0x487c2170, 0xf0051d80, 0x2300f986, 0xf06f2207, 0x4878017f, 0xf0051d80, 
+    0x487af97e, 0xb1207800, 0xd07d2801, 0xd17c2802, 0x4880e0a6, 0x4b802200, 0x5100e9d0, 0xf02c4628, 
+    0x4607ff2d, 0xfe66f02c, 0xda0b28ff, 0x22004879, 0xe9d04b79, 0x46285100, 0xff20f02c, 0xf02c4607, 
+    0xe000fe59, 0xb28420ff, 0x22004623, 0x486321ff, 0xf0053008, 0x486ff954, 0x4b6f2200, 0x5102e9d0, 
+    0xf02c4628, 0x4607ff0b, 0xfe44f02c, 0xda0b28ff, 0x22004868, 0xe9d04b68, 0x46285102, 0xfefef02c, 
+    0xf02c4607, 0xe000fe37, 0xb28420ff, 0x22084623, 0x01fff06f, 0x30084851, 0xf931f005, 0xe9d1495d, 
+    0x22005104, 0x46284b5c, 0xfee8f02c, 0xf02c4607, 0x28fffe21, 0x4857da0b, 0x4b572200, 0x5104e9d0, 
+    0xf02c4628, 0x4607fedb, 0xfe14f02c, 0x20ffe000, 0x4623b284, 0x21ff2200, 0x300a4840, 0xf90ff005, 
+    0x2200484c, 0xe9d04b4c, 0x46285106, 0xfec6f02c, 0xf02c4607, 0x28fffdff, 0x4846da0e, 0x4b462200, 
+    0x5106e9d0, 0xe0014628, 0xe042e011, 0xfeb6f02c, 0xf02c4607, 0xe000fdef, 0xb28420ff, 0x22084623, 
+    0x01fff06f, 0x300a482d, 0xf8e9f005, 0x493be03c, 0x2100e9d1, 0xf02c4610, 0xb204fe0d, 0x48274621, 
+    0xf7fe3008, 0x4835fae1, 0x2102e9d0, 0xf02c4610, 0xb204fe01, 0x48214621, 0xf7fe300a, 0xe023fad5, 
+    0xe9d0482e, 0x46102104, 0xfdf4f02c, 0x4621b204, 0x3008481a, 0xfac8f7fe, 0xe9d04828, 0x46102106, 
+    0xfde8f02c, 0x4621b204, 0x300a4814, 0xfabcf7fe, 0x2100e00a, 0x30084811, 0xfab6f7fe, 0x480f2100, 
+    0xf7fe300a, 0xbf00fab1, 0x2004bf00, 0x81f0e8bd, 0x481bb510, 0x28037800, 0x4819d007, 0x28057800, 
+    0x4817d003, 0x28047800, 0x4816d15a, 0xf828f008, 0x68084914, 0xfa71f7ff, 0x0000e026, 0xd03c806e, 
+    0x00038466, 0x000384f8, 0x000384e5, 0x000384f9, 0x40700000, 0x000384e8, 0x40400000, 0x000384f0, 
+    0xb71758e2, 0x3fae00d1, 0x3ff00000, 0x000384e6, 0x000384e7, 0x0004c800, 0x40200000, 0x0004c7e0, 
+    0x000361ec, 0x00038fe0, 0x4000f500, 0x4621b204, 0xf7fe48fe, 0x49fefa69, 0xf7ff6848, 0xf500fa3e, 
+    0xb2044000, 0x48f94621, 0xf7fe1c80, 0x49f8fa5d, 0xf7ff6888, 0xf500fa32, 0xb2044000, 0x48f34621, 
+    0xf7fe1d00, 0x49f2fa51, 0xf7ff68c8, 0xf500fa26, 0xb2044000, 0x48ed4621, 0xf7fe1d80, 0xe012fa45, 
+    0x48ea49ec, 0xfa40f7fe, 0x48e849ea, 0xf7fe1c80, 0x49e8fa3b, 0x1d0048e5, 0xfa36f7fe, 0x48e349e5, 
+    0xf7fe1d80, 0x2000fa31, 0xb510bd10, 0x52b8f04f, 0x011ef24c, 0xf7fe2008, 0x2102fadc, 0xf7fe48de, 
+    0x48defa23, 0x1000f990, 0x1c8048db, 0xfa1cf7fe, 0x780148db, 0x1d0048d8, 0xfa16f7fe, 0xbd102004, 
+    0xf04fb510, 0xf24c52b8, 0x2008011f, 0xfac1f7fe, 0x48d12102, 0xfa08f7fe, 0x1c8048cf, 0xf9fef7fe, 
+    0x49ceb240, 0x48cc7008, 0xf7fe1d00, 0x49ccf9f7, 0x20077008, 0xfbfdf006, 0xbd102004, 0xf04fb510, 
+    0xf24c52b8, 0x20080115, 0xfaa3f7fe, 0x48c22102, 0xf9eaf7fe, 0x780148c3, 0x1c8048bf, 0xf9e4f7fe, 
+    0x780148c1, 0x1d0048bc, 0xf9def7fe, 0xbd102004, 0xf04fb510, 0xf24c52b8, 0x20080114, 0xfa89f7fe, 
+    0x48b52102, 0xf9d0f7fe, 0x1c8048b3, 0xf9c6f7fe, 0x700849b4, 0x1d0048b0, 0xf9c0f7fe, 0x700849b2, 
+    0xf0062007, 0x2004fbc6, 0xe92dbd10, 0xf04f41f0, 0xf24852b8, 0x20080114, 0xfa6bf7fe, 0x48a62102, 
+    0xf9b2f7fe, 0x1c8048a4, 0xf9a8f7fe, 0x48a2b286, 0xf7fe1d00, 0xb285f9a3, 0x1d80489f, 0xf99ef7fe, 
+    0x489db287, 0xf7fe3008, 0xfa1ff999, 0x2e18f880, 0xb672d106, 0xf005b2e8, 0xb284f8a3, 0xe020b662, 
+    0xd1062e1c, 0xb2e8b672, 0xf8def005, 0xb662b284, 0x2e0fe017, 0xb672d107, 0x2101b2e8, 0xf915f005, 
+    0xb662b284, 0x2e17e00d, 0xb672d10a, 0xf3c5b2ea, 0xf3c52103, 0xf0053041, 0xb284f969, 0xe000b662, 
+    0xea042400, 0xfa400007, 0xb221f408, 0x300a4882, 0xf96af7fe, 0xe8bd2004, 0xe92d81f0, 0xf04f41fc, 
+    0xf24852b8, 0x20080115, 0xfa13f7fe, 0x487a2102, 0xf95af7fe, 0x1c804878, 0xf950f7fe, 0x4876b287, 
+    0xf7fe1d00, 0xb284f94b, 0x1d804873, 0xf946f7fe, 0x4871b285, 0xf7fe3008, 0xb286f941, 0x300a486e, 
+    0xf93cf7fe, 0xf880fa1f, 0xd1172f18, 0xb2e0b672, 0xb2724643, 0xf005b229, 0xb662f85a, 0xd1322c02, 
+    0x0020f005, 0xf1c6b1f8, 0xfa480005, 0x220ff300, 0x48614960, 0xf004383a, 0xe024ff22, 0xd1082f1c, 
+    0xb2e0b672, 0xb2724643, 0xf005b229, 0xb662f882, 0x2f0fe019, 0xb672d108, 0x4643b2e0, 0xb229b272, 
+    0xf8c1f005, 0xe00eb662, 0xd10c2f17, 0xb270b672, 0xb22bb2e2, 0x2103f3c4, 0x0800e9cd, 0x3041f3c4, 
+    0xf91ef005, 0x2004b662, 0x81fce8bd, 0xf04fb510, 0xf24852b8, 0x20080116, 0xf9abf7fe, 0x48462102, 
+    0xf8f2f7fe, 0x78014849, 0x1c804843, 0xf8ecf7fe, 0xbd102004, 0xf04fb510, 0xf24852b8, 0x20080117, 
+    0xf997f7fe, 0x483c2102, 0xf8def7fe, 0x1c80483a, 0xf8d4f7fe, 0x7008493d, 0xbd102004, 0xf04fb510, 
+    0xf24852b8, 0x20080118, 0xf983f7fe, 0x48322102, 0xf8caf7fe, 0x78014836, 0x1c80482f, 0xf8c4f7fe, 
+    0xbd102004, 0xf04fb510, 0xf24852b8, 0x20080119, 0xf96ff7fe, 0x48282102, 0xf8b6f7fe, 0x8800482d, 
+    0xd10d2808, 0x7804482a, 0x1c804823, 0xf8a6f7fe, 0x70084927, 0x78004608, 0xd0014284, 0xe926f002, 
+    0xbd102004, 0xf04fb510, 0xf24852b8, 0x20080132, 0xf94ff7fe, 0x1c804818, 0xf890f7fe, 0x6008491e, 
+    0x1d004815, 0xf88af7fe, 0x6008491c, 0x1d804812, 0xf884f7fe, 0x7008491a, 0xbd102004, 0xf04fb510, 
+    0xf24852b8, 0x20080133, 0xf933f7fe, 0x88004812, 0x4809b201, 0xf7fe1c80, 0x4810f877, 0xb2018800, 
+    0x1d004805, 0xf870f7fe, 0xe01b480d, 0xd00351ac, 0x00038fe0, 0xffff8000, 0xd03c806e, 0x000361ea, 
+    0x000361eb, 0x0003845c, 0x0003845d, 0x00038491, 0x00038492, 0x000361ce, 0x00038474, 0x00038478, 
+    0x00038471, 0x48fc7801, 0xf84ef7fe, 0xbd102004, 0xf04fb510, 0xf24852b8, 0x20080134, 0xf8f9f7fe, 
+    0x1f0048f5, 0xf83af7fe, 0x600849f4, 0x1e8048f2, 0xf834f7fe, 0x600849f2, 0xf7fe48ef, 0x49f1f82f, 
+    0x20046008, 0xb510bd10, 0x52b8f04f, 0x0135f248, 0xf7fe2008, 0x48e9f8de, 0xb2018800, 0x1f0048e6, 
+    0xf822f7fe, 0x880048e6, 0x48e3b201, 0xf7fe1e80, 0x48e4f81b, 0xb2018800, 0xf7fe48df, 0x2004f815, 
+    0xb510bd10, 0x52b8f04f, 0x011af248, 0xf7fe2008, 0x48ddf8c0, 0x28037800, 0x2301d120, 0x46192200, 
+    0xf00448da, 0x2301fdfc, 0x21082203, 0xf00448d7, 0x2301fdf6, 0x21042202, 0xf00448d4, 0x48d3fdf0, 
+    0xf7fd1c80, 0x48d1ffeb, 0xf7fd1d00, 0x2300ffe7, 0x2101461a, 0xf00448cd, 0xe035fde2, 0x780048ca, 
+    0xd12f2802, 0x0103f24c, 0xf00420af, 0xf24cff58, 0x20af0100, 0xff53f004, 0x0101f24c, 0xf00420af, 
+    0x2101ff4e, 0xf00420aa, 0x2101ff60, 0xf00420aa, 0x2101ff5c, 0xf00420ab, 0x2101ff58, 0xf00420ab, 
+    0x2101ff54, 0xf00420ac, 0x2101ff50, 0xf00420ac, 0x2101ff4c, 0xf00420ad, 0x2101ff48, 0xf00420ad, 
+    0xe001ff44, 0xbd102008, 0xe7fc2004, 0xf04fb570, 0xf24852b8, 0x2008011b, 0xf85bf7fe, 0x1f0048a6, 
+    0xff9cf7fd, 0x48a8b2c4, 0x28037800, 0x2301d15e, 0x21082203, 0xf00448a5, 0x2301fd92, 0x21042202, 
+    0xf00448a2, 0xbb3cfd8c, 0x1d0048a0, 0xff86f7fd, 0x46294605, 0x1e804898, 0xff86f7fd, 0x1c80489b, 
+    0xff7cf7fd, 0x46294605, 0xf7fd4893, 0x4897ff7d, 0xf7fd300c, 0x4605ff73, 0x488f4629, 0xf7fd1c80, 
+    0x4892ff73, 0xf7fd300a, 0x4605ff69, 0x488a4629, 0xf7fd1d00, 0xe07fff69, 0xd17d2c01, 0x3008488b, 
+    0xff5cf7fd, 0x46294605, 0x1e804883, 0xff5cf7fd, 0x1d804886, 0xff52f7fd, 0x46294605, 0xf7fd487e, 
+    0x4882ff53, 0xf7fd3010, 0x4605ff49, 0x487a4629, 0xf7fd1c80, 0x487dff49, 0xf7fd300e, 0x4605ff3f, 
+    0x48754629, 0xf7fd1d00, 0xe055ff3f, 0x78004876, 0xd1512802, 0x2101bb3c, 0xf00420ac, 0x4605fec6, 
+    0x486d4629, 0xff30f7fd, 0x20ac2101, 0xfebdf004, 0x46294605, 0x1e804868, 0xff26f7fd, 0x20ad2101, 
+    0xfeb3f004, 0x46294605, 0x1d004863, 0xff1cf7fd, 0x20ad2101, 0xfea9f004, 0x46294605, 0x1c80485e, 
+    0xff12f7fd, 0x2c01e028, 0x2101d126, 0xf00420ab, 0x4605fe9c, 0x48584629, 0xff06f7fd, 0x20ab2101, 
+    0xfe93f004, 0x46294605, 0x1e804853, 0xfefcf7fd, 0x20aa2101, 0xfe89f004, 0x46294605, 0x1d00484e, 
+    0xfef2f7fd, 0x20aa2101, 0xfe7ff004, 0x46294605, 0x1c804849, 0xfee8f7fd, 0xbd702004, 0xf04fb510, 
+    0xf24852b8, 0x2008011c, 0xff93f7fd, 0x1f004842, 0xfed4f7fd, 0x4620b2c4, 0xf874f00c, 0xbd102004, 
+    0xf04fb510, 0xf24852b8, 0x2008011d, 0xff81f7fd, 0xf0042000, 0xf400fdd5, 0xb1904080, 0x20462100, 
+    0xfe53f004, 0x4080f400, 0x2200b158, 0x48382101, 0xfcccf004, 0x2101b128, 0x1f00482f, 0xfeb4f7fd, 
+    0x2100e004, 0x1f00482c, 0xfeaef7fd, 0xbd102004, 0xf04fb510, 0xf24c52b8, 0x2008011e, 0xff59f7fd, 
+    0x48252102, 0xf7fd1f80, 0x482afe9f, 0x48227801, 0xf7fd1f00, 0x2004fe99, 0xb510bd10, 0x52b8f04f, 
+    0x012af248, 0xf7fd2008, 0x2102ff44, 0x1f80481a, 0xfe8af7fd, 0x1f004818, 0xfe80f7fd, 0x7008491d, 
+    0xbd102004, 0xf04fb510, 0xf24852b8, 0x20080116, 0xff2ff7fd, 0x48102102, 0xf7fd1f80, 0x4816fe75, 
+    0x480d7801, 0xf7fd1f00, 0x2004fe6f, 0xb510bd10, 0x52b8f04f, 0x0117f248, 0xf7fd2008, 0x2102ff1a, 
+    0x1f804805, 0xfe60f7fd, 0x1f004803, 0xfe56f7fd, 0x70084909, 0xbd102004, 0xd03c8074, 0x00038480, 
+    0x00038484, 0x0003847c, 0x000361ec, 0xd00351ea, 0xd28fffe0, 0x000384e1, 0x000384e4, 0x4606b570, 
+    0xf241220c, 0x48fb0100, 0xfc50f004, 0xd1162801, 0xe0052400, 0x49f82000, 0xf8216809, 0x1c640014, 
+    0x6f00f5b4, 0x2300d3f6, 0xf241220c, 0x48f10100, 0xfc25f004, 0x49f12000, 0x49f17008, 0x48ef6008, 
+    0x0000f990, 0xda7d2804, 0x48edb231, 0x68006802, 0x4beb1c40, 0x48e86018, 0xf8206800, 0x48e91012, 
+    0xfe0cf7fd, 0x680a49e6, 0x1c496809, 0x60194be4, 0x680949e1, 0x0012f821, 0xe00d4ce3, 0xf7fd4620, 
+    0x49dffdfd, 0x6809680a, 0x4bdd1c49, 0x49da6019, 0xf8216809, 0x1ca40012, 0x302248db, 0xd9ed4284, 
+    0xf7fd48da, 0x49d6fdeb, 0x6809680a, 0x4bd41c49, 0x49d16019, 0xf8216809, 0x48d40012, 0xf7fd1c80, 
+    0x49cffddd, 0x6809680a, 0x4bcd1c49, 0x49ca6019, 0xf8216809, 0x48cd0012, 0xf7fd1d00, 0x49c8fdcf, 
+    0x6809680a, 0x4bc61c49, 0x49c36019, 0xf8216809, 0x48c60012, 0xf7fd1d80, 0x49c1fdc1, 0x6809680a, 
+    0x4bbf1c49, 0x49bc6019, 0xf8216809, 0x48bf0012, 0xf7fd3008, 0x49bafdb3, 0x6809680a, 0x4bb81c49, 
+    0x49b56019, 0xf8216809, 0x48b80012, 0xf7fd306c, 0x49b3fda5, 0x6809680a, 0x4bb11c49, 0x49ae6019, 
+    0xe0006809, 0xf821e0a3, 0x48b00012, 0xf7fd300a, 0x49abfd95, 0x6809680a, 0x4ba91c49, 0x49a66019, 
+    0xf8216809, 0x48a90012, 0xf7fd300c, 0x49a4fd87, 0x6809680a, 0x4ba21c49, 0x499f6019, 0xf8216809, 
+    0x48a20012, 0xf7fd300e, 0x499dfd79, 0x6809680a, 0x4b9b1c49, 0x49986019, 0xf8216809, 0x489b0012, 
+    0xf7fd3010, 0x4996fd6b, 0x6809680a, 0x4b941c49, 0x49916019, 0xf8216809, 0x4c950012, 0x4620e00d, 
+    0xfd5cf7fd, 0x680a498e, 0x1c496809, 0x60194b8c, 0x68094989, 0x0012f821, 0x488d1ca4, 0x4284303e, 
+    0x2400d9ed, 0x2500e014, 0xb2e2e00f, 0x2100b2e8, 0xfd3cf004, 0x680a4982, 0x1c496809, 0x60194b80, 
+    0x6809497d, 0x0012f821, 0x2d041c6d, 0x1c64d3ed, 0xd9e82c24, 0xe00e2400, 0x2100b2e0, 0xfcc5f004, 
+    0x680a4977, 0x1c496809, 0x60194b75, 0x68094972, 0x0012f821, 0x2cff1c64, 0x2400d9ee, 0xb2e0e00d, 
+    0xfc2ef004, 0x680a496e, 0x1c496809, 0x60194b6c, 0x68094969, 0x0012f821, 0x2c071c64, 0x2400d9ef, 
+    0xb2e0e00d, 0xfc60f004, 0x680a4965, 0x1c496809, 0x60194b63, 0x68094960, 0x0012f821, 0x2c1f1c64, 
+    0x485ed9ef, 0x1c407800, 0x495cb240, 0xbd707008, 0x68004860, 0xf6421c40, 0xfb904100, 0xfb01f2f1, 
+    0x495c0012, 0x46086008, 0xb9306800, 0x7800485a, 0xf0001c40, 0x4958000f, 0x47708008, 0x41f0e92d, 
+    0xf7fd4856, 0xb284fcdb, 0x88004855, 0xd10142a0, 0x81f0e8bd, 0x88004852, 0xda0a42a0, 0x88004850, 
+    0x71fff64f, 0x1c401a08, 0xb2854420, 0x8004484c, 0x484be006, 0x1a208800, 0xb2851c40, 0x80044848, 
+    0x78004848, 0xf7ffbbb0, 0xb2a8ffc3, 0x43084946, 0x68094946, 0x68124a3f, 0x0022f841, 0xe0262600, 
+    0xffb6f7ff, 0x1f80483d, 0xfca8f7fd, 0x483b4607, 0xf7fd3808, 0xf367fca3, 0x493c401f, 0x4a356809, 
+    0xf8416812, 0xf7ff0022, 0x4834ffa3, 0xfc96f7fd, 0x48324607, 0xf7fd1f00, 0xf367fc91, 0x4933401f, 
+    0x4a2c6809, 0xf8416812, 0x1c700022, 0x42aeb286, 0xe03cdbd6, 0xb2a8e7ff, 0x4308492b, 0x680a492c, 
+    0x1c496809, 0x60194b2a, 0x6809492a, 0x0022f841, 0xe02a2600, 0x1f804821, 0xfc70f7fd, 0x481f4607, 
+    0xf7fd3808, 0xf367fc6b, 0x4921401f, 0x6809680a, 0x4b1f1c49, 0x491f6019, 0xf8416809, 0x48170022, 
+    0xfc5cf7fd, 0x48154607, 0xf7fd1f00, 0xf367fc57, 0x4917401f, 0x6809680a, 0x4b151c49, 0x49156019, 
+    0xf8416809, 0x1c700022, 0x42aeb286, 0xbf00dbd2, 0x0000e76e, 0xd00351a4, 0x000384c8, 0x000384d2, 
+    0x000384cc, 0xd03c804a, 0xd0034200, 0xd0039004, 0xd28fffc0, 0x000384b0, 0x000384d0, 0xd03c826c, 
+    0x000361c2, 0x000384d3, 0xeeee0000, 0x000384ac, 0x000384b8, 0x000384b4, 0x41f0e92d, 0x20004604, 
+    0x600849fe, 0x21002215, 0xf0044608, 0xb285fc0f, 0x061ff005, 0xd10442a6, 0x49f92001, 0x49f96008, 
+    0x48f77008, 0x28016800, 0x48f7d17e, 0x30106800, 0x5f30f5b0, 0x2007da79, 0xfd02f005, 0x680a49f2, 
+    0x1c496809, 0x60194bf0, 0x680949f0, 0x0022f841, 0xf7fd48ef, 0x4607fbf3, 0x301448ed, 0xfbeef7fd, 
+    0x401ff367, 0x680a49e8, 0x1c496809, 0x60194be6, 0x680949e6, 0x0022f841, 0x46112200, 0xf0044610, 
+    0xb280fbd5, 0x440149e3, 0x680248df, 0x1c406800, 0x60184bdd, 0x680048dd, 0x1022f840, 0x46112200, 
+    0xf0042001, 0xb280fbc3, 0x184249db, 0x680148d6, 0x1c406800, 0x60184bd4, 0x680048d4, 0x2021f840, 
+    0x46112200, 0xf0042002, 0xb280fbb1, 0x5007f100, 0x680a49cd, 0x1c496809, 0x60194bcb, 0x680949cb, 
+    0x0022f841, 0x46112200, 0xf0042003, 0xb280fb9f, 0x440149ca, 0x680248c4, 0x1c406800, 0x60184bc2, 
+    0x680048c2, 0x1022f840, 0x21002202, 0xf0044608, 0xb280fb8d, 0x440149c2, 0x680248bb, 0x1c406800, 
+    0x60184bb9, 0xe00148b9, 0xe0c0e0c0, 0xf8406800, 0x22021022, 0x20012100, 0xfb78f004, 0x49b9b280, 
+    0x48b14401, 0x68006802, 0x4baf1c40, 0x48af6018, 0xf8406800, 0x22021022, 0x46102100, 0xfb66f004, 
+    0xf100b280, 0x49a8500b, 0x6809680a, 0x4ba61c49, 0x49a66019, 0xf8416809, 0x22020022, 0x20032100, 
+    0xfb54f004, 0x49a8b280, 0x489f4401, 0x68006802, 0x4b9d1c40, 0x489d6018, 0xf8406800, 0x22051022, 
+    0x46082100, 0xfb42f004, 0x49a0b280, 0x48961842, 0x68006801, 0x4b941c40, 0x48946018, 0xf8406800, 
+    0x22052021, 0x20012100, 0xfb30f004, 0x4998b280, 0x488d4401, 0x68006802, 0x4b8b1c40, 0x488b6018, 
+    0xf8406800, 0x22051022, 0x20022100, 0xfb1ef004, 0xf100b280, 0x4984500f, 0x6809680a, 0x4b821c49, 
+    0x49826019, 0xf8416809, 0x22050022, 0x20032100, 0xfb0cf004, 0x4987b280, 0x487b4401, 0x68006802, 
+    0x4b791c40, 0x48796018, 0xf8406800, 0x22151022, 0x46082100, 0xfafaf004, 0xf100b280, 0x49725010, 
+    0x6809680a, 0x4b701c49, 0x49706019, 0xf8416809, 0x22160022, 0x46082100, 0xfae8f004, 0xf100b280, 
+    0x49695014, 0x6809680a, 0x4b671c49, 0x49676019, 0xf8416809, 0x22170022, 0x46082100, 0xfad6f004, 
+    0xf100b280, 0x49605018, 0x6809680a, 0x4b5e1c49, 0x495e6019, 0xf8416809, 0x22000022, 0x48662101, 
+    0xf8e4f004, 0xd10b2801, 0xfde8f7ff, 0x2000e008, 0x60084953, 0x220a2301, 0x48600299, 0xf8bff004, 
+    0x81f0e8bd, 0x41f0e92d, 0x20004604, 0x6008494e, 0x21002215, 0xf0044608, 0xb286faa9, 0x051ff006, 
+    0x88004857, 0xd1054285, 0xf1b4b114, 0xd1013fbb, 0x81f0e8bd, 0x80054852, 0x38084850, 0xfa9ef7fd, 
+    0x483eb138, 0xb2018800, 0x380a484c, 0xfa9cf7fd, 0xf7ffe19d, 0x2c0afd9d, 0x484ad908, 0x49376800, 
+    0xf8406809, 0xf7ff4021, 0xe013fd93, 0xd1112c01, 0xf7fd4845, 0x4607fa83, 0x1c804843, 0xfa7ef7fd, 
+    0x401ff367, 0x6809493f, 0x68124a2c, 0x0022f841, 0xfd7ef7ff, 0xf0052007, 0x493afb73, 0x4a276809, 
+    0xf8416812, 0xf7ff0022, 0x4829fd73, 0xfa66f7fd, 0x48274607, 0xf7fd3014, 0xf367fa61, 0x4931401f, 
+    0x4a1e6809, 0xf8416812, 0xf7ff0022, 0x2200fd61, 0x46104611, 0xfa4af004, 0xf100b280, 0x492b508d, 
+    0xea408809, 0x49274001, 0x4a146809, 0xf8416812, 0xf7ff0022, 0x2200fd4d, 0x20014611, 0xfa36f004, 
+    0x4923b280, 0x49214408, 0xea408809, 0x481d4101, 0x4a0a6800, 0xf8406812, 0xf7ff1022, 0x2200fd39, 
+    0x20024611, 0xfa22f004, 0xf100b280, 0x4917508e, 0xea408809, 0x49134001, 0xe02b6809, 0x000384b0, 
+    0x000384c0, 0x000384c4, 0x000384b8, 0x000384b4, 0xd28fffc0, 0x21a00000, 0x21b00000, 0x21d00000, 
+    0x22a00000, 0x22b00000, 0x22d00000, 0x23a00000, 0x23b00000, 0x23d00000, 0xd03c8260, 0xd00351a4, 
+    0x000361c0, 0x000384ac, 0xd0039026, 0x000384d0, 0x11b00000, 0x68124afe, 0x0022f841, 0xfcf8f7ff, 
+    0x46112200, 0xf0042003, 0xb280f9e1, 0x440849f9, 0x880949f9, 0x4101ea40, 0x680048f8, 0x68124af4, 
+    0x1022f840, 0xfce4f7ff, 0x21002202, 0xf0044608, 0xb280f9cd, 0x5095f100, 0x880949ef, 0x4001ea40, 
+    0x680949ee, 0x68124aea, 0x0022f841, 0xfcd0f7ff, 0x21002202, 0xf0042001, 0xb280f9b9, 0x440849e8, 
+    0x880949e5, 0x4101ea40, 0x680048e4, 0x68124ae0, 0x1022f840, 0xfcbcf7ff, 0x21002202, 0xf0044610, 
+    0xb280f9a5, 0x5096f100, 0x880949db, 0x4101ea40, 0x680048da, 0x68124ad6, 0x1022f840, 0xfca8f7ff, 
+    0x21002202, 0xf0042003, 0xb280f991, 0x440849d5, 0x880949d1, 0x4101ea40, 0x680048d0, 0x68124acc, 
+    0x1022f840, 0xfc94f7ff, 0x21002205, 0xf0044608, 0xb280f97d, 0x509df100, 0x880949c7, 0x4001ea40, 
+    0x680949c6, 0x68124ac2, 0x0022f841, 0xfc80f7ff, 0x21002205, 0xf0042001, 0xb280f969, 0x440849c2, 
+    0x880949bd, 0x4001ea40, 0x680949bc, 0x68124ab8, 0x0022f841, 0xfc6cf7ff, 0x21002205, 0xf0042002, 
+    0xb280f955, 0x509ef100, 0x880949b3, 0x4101ea40, 0x680048b2, 0x68124aae, 0x1022f840, 0xfc58f7ff, 
+    0x21002205, 0xf0042003, 0xb280f941, 0x440849af, 0x880949a9, 0x4101ea40, 0x680048a8, 0x68124aa4, 
+    0x1022f840, 0xfc44f7ff, 0x21002215, 0xf0044608, 0xb280f92d, 0x50a0f100, 0x8809499f, 0x4001ea40, 
+    0x6809499e, 0x68124a9a, 0x0022f841, 0xfc30f7ff, 0x21002216, 0xf0044608, 0xb280f919, 0x50a8f100, 
+    0x88094995, 0x4001ea40, 0x68094994, 0x68124a90, 0x0022f841, 0xfc1cf7ff, 0x21002217, 0xf0044608, 
+    0xb280f905, 0x50b0f100, 0x8809498b, 0x4001ea40, 0x6809498a, 0x68124a86, 0x0022f841, 0x21012200, 
+    0xf003488b, 0x2801ff13, 0xf7ffd101, 0xbf00fc17, 0x2000e64e, 0x6008497e, 0x60084986, 0x8008497e, 
+    0xb5704770, 0x2c014604, 0x2000d120, 0x60084981, 0x03a1220e, 0xf0034880, 0x4980fef9, 0x220f7008, 
+    0x487d497f, 0xfef2f003, 0xd10e2801, 0x7800487b, 0xd1fa2800, 0x02a1220a, 0xf0034877, 0x2800fee7, 
+    0xf04fd1f3, 0xf7ff30aa, 0xe0aefe0d, 0xd14d2c02, 0x0321220d, 0xf0034870, 0x2801fed9, 0xf64ad103, 
+    0xf7ff20aa, 0xe015fa7b, 0x7800486c, 0xf04fb920, 0xf7ff30bb, 0xe00dfdf7, 0x211f2200, 0xf0034866, 
+    0xb138fec5, 0x211f2200, 0xf0034863, 0x4605febf, 0xfc82f7ff, 0x4962220f, 0xf003485f, 0x2801feb7, 
+    0x220ed1d3, 0x485f0381, 0xfeb0f003, 0xd17c2800, 0x21102204, 0xf003485b, 0x2800fea9, 0x2205d175, 
+    0x48582120, 0xfea2f003, 0xd16e2800, 0x21082203, 0xf0034855, 0x2800fe9b, 0x220ad167, 0x4100f240, 
+    0xf003484d, 0x2800fe93, 0xe05ed0be, 0xd15c2c03, 0xf242220d, 0x48480100, 0xfe88f003, 0xd1032801, 
+    0x30bbf64b, 0xfa2af7ff, 0x4844e014, 0xb9187800, 0xf7ff2000, 0xe00dfda7, 0x211f2200, 0xf003483e, 
+    0xb138fe75, 0x211f2200, 0xf003483b, 0x4605fe6f, 0xfc32f7ff, 0x493a220f, 0xf0034837, 0x2801fe67, 
+    0x220ed11b, 0x48370381, 0xfe60f003, 0x2204b9a8, 0x48342110, 0xfe5af003, 0xd10e2801, 0x21f02204, 
+    0xf0034832, 0x2801fe53, 0x220ad007, 0x4100f240, 0xf0034829, 0x2800fe4b, 0x220fd0c7, 0x48264928, 
+    0xfe44f003, 0xd1102801, 0x78004824, 0xd10c2801, 0x78004827, 0xd1082801, 0x49262000, 0x23016008, 
+    0x0299220a, 0xf003481c, 0xbd70fe1a, 0xf04fb510, 0xf24852b8, 0x20080125, 0xf8cbf7fd, 0x481e2102, 
+    0xf812f7fd, 0xf242220d, 0x481c0100, 0xfe1ef003, 0x220c4604, 0x0100f241, 0xf0034818, 0x4004fe17, 
+    0x2202b374, 0x46082100, 0xfff0f003, 0xe0284604, 0x000384b0, 0x11d00000, 0x000384d0, 0x000384ac, 
+    0x12b00000, 0x12d00000, 0x13b00000, 0x13d00000, 0xd03c8260, 0x000384b8, 0xd00351a4, 0x000384d3, 
+    0xffff8000, 0xd0039026, 0xd0035040, 0xd28f0004, 0x000384c4, 0x000384c0, 0xd03c806e, 0xd28fffd4, 
+    0x4621e025, 0xf7fc4836, 0x2202ffcf, 0x20012100, 0xffbcf003, 0x46214604, 0x1c804831, 0xffc4f7fc, 
+    0x21002202, 0xf0034610, 0x4604ffb1, 0x482c4621, 0xf7fc1d00, 0x2202ffb9, 0x20032100, 0xffa6f003, 
+    0x46214604, 0x1d804826, 0xffaef7fc, 0x2100e012, 0xf7fc4823, 0x2100ffa9, 0x1c804821, 0xffa4f7fc, 
+    0x481f2100, 0xf7fc1d00, 0x2100ff9f, 0x1d80481c, 0xff9af7fc, 0x20142101, 0xfe7af003, 0x46214604, 
+    0x30084817, 0xff90f7fc, 0xbd102004, 0xf04fb510, 0xf24852b8, 0x2008013c, 0xf83bf7fd, 0x48102102, 
+    0xf7fc1e80, 0x480fff81, 0x1000f990, 0xf7fc480c, 0x2004ff7b, 0xb510bd10, 0x52b8f04f, 0x013df248, 
+    0xf7fd2008, 0x2102f826, 0x1e804805, 0xff6cf7fc, 0xf7fc4803, 0xb240ff63, 0x70084902, 0xbd102004, 
+    0xd03c8070, 0x000384fa, 0xf01eb510, 0xf01bfd77, 0xf7fdfb4b, 0xf01bfadf, 0xf016fc47, 0xf000fc39, 
+    0xf000f87b, 0xf024ff76, 0x2001fc67, 0x0000bd10, 0x4604b570, 0x4623460d, 0x21022201, 0xf00348fe, 
+    0x462bfd3e, 0x21042202, 0xf00348fb, 0xea44fd38, 0x22000305, 0x48f82101, 0xfd31f003, 0xb510bd70, 
+    0x48f749f6, 0xff30f7fc, 0x0100f242, 0xf02a48f5, 0x2000fca3, 0x600849f4, 0x600849f4, 0x700849f4, 
+    0x800849f4, 0x800849f4, 0x700849f4, 0x700849f4, 0xf0047808, 0x2000ff7f, 0x700849f2, 0x780048f2, 
+    0x2020b108, 0x2000e000, 0x800849f0, 0x49f02000, 0x49f07008, 0x20017008, 0x700849ef, 0x880048ef, 
+    0xd003280d, 0x880048ed, 0xd105280c, 0x49ec2001, 0x49ec7008, 0xe0047008, 0x49e92000, 0x49e97008, 
+    0x20007008, 0x700849e8, 0x49e82024, 0x20007008, 0x700849e7, 0x700849e7, 0x700849e7, 0x49e848e7, 
+    0x48e86008, 0x600849e8, 0x49e82001, 0xf2417008, 0x49e74000, 0xbd108008, 0xf008b510, 0x2201f9e3, 
+    0x20071e91, 0xfff0f004, 0x1e912201, 0xf0042000, 0xf7ffffeb, 0xf009ff94, 0x2100ff48, 0xf7ff2001, 
+    0xf016ff77, 0xf025fc73, 0xf026ffc1, 0xf00bfcc7, 0xf024f99e, 0xf025fdf3, 0xf028fd5f, 0xf005f9a3, 
+    0x2104fa6e, 0x384a48b6, 0xfeaef7fc, 0xf89cf006, 0xb570bd10, 0x460e4605, 0x49ce2000, 0x49ce7008, 
+    0x49ce7008, 0x49ce7008, 0x49ce7008, 0x49ce7008, 0x49ce7008, 0x49ce7008, 0x2d007008, 0x49cdd125, 
+    0x49cd7008, 0x49cd7008, 0x49cd7008, 0x20047008, 0x700849cc, 0x700849cc, 0x700849cc, 0x700849cc, 
+    0x49cc2000, 0x49cc7008, 0x49cc7008, 0x49cc7008, 0x49cc7008, 0x49cc7008, 0x49cc7008, 0x49cc7008, 
+    0x49cc7008, 0x49cc7008, 0x20017008, 0x700849cb, 0x700849cb, 0x700849cb, 0x700849cb, 0x700849cb, 
+    0x700849cb, 0x700849cb, 0x700849cb, 0x49cb2000, 0x49cb7008, 0x49cb7008, 0x49cb7008, 0x49cb7008, 
+    0x49cb7008, 0x49cb7008, 0x49cb7008, 0x49cb7008, 0x49cb7008, 0x49cb8008, 0x49cb8008, 0x49cb8008, 
+    0x49cb8008, 0x49cb7008, 0x49cb7008, 0x49cb7008, 0x49cb7008, 0x49cb7008, 0x20018008, 0xf80ff00a, 
+    0xf00a2005, 0x2400f84d, 0x2000e005, 0xf82149c6, 0x1c600014, 0x2c04b244, 0x2301dbf7, 0x21202205, 
+    0xf00348c2, 0x2301fc1c, 0x21202205, 0xf00348c0, 0x2301fc16, 0x21202205, 0xf00348be, 0x2301fc10, 
+    0x21202205, 0xf00348bc, 0x2300fc0a, 0x21202205, 0xf00348b6, 0x2300fc04, 0x21202205, 0xf00348b4, 
+    0x2300fbfe, 0x21202205, 0xf00348b2, 0x2300fbf8, 0x21202205, 0xf00348b0, 0xb955fbf2, 0x780048af, 
+    0xd1032803, 0x49ae2001, 0xe0027008, 0x49ac2003, 0x20017008, 0x700849ab, 0xd10a2e04, 0x49684867, 
+    0x48686008, 0x60084968, 0x70b8f644, 0x80084968, 0x2e05e016, 0x4861d10a, 0x60084961, 0x49624861, 
+    0xf2426008, 0x496270dc, 0xe0098008, 0x495c485b, 0x485c6008, 0x6008495c, 0x4000f241, 0x8008495c, 
+    0xb510bd70, 0x23004604, 0x21022201, 0xf0034896, 0x2300fbb6, 0x2101461a, 0xf0034893, 0x2300fbb0, 
+    0x2101461a, 0x30084890, 0xfba9f003, 0x2200239c, 0x31fff240, 0x1c80488c, 0xfba1f003, 0x1338f240, 
+    0xf2402200, 0x488831ff, 0xf0031d00, 0x2397fb98, 0x21ff2200, 0x1d804884, 0xfb91f003, 0x22082397, 
+    0x01fff06f, 0x1d804880, 0xfb89f003, 0xd1412c04, 0x22002303, 0x487d4619, 0xfb81f003, 0x7800487c, 
+    0xd1382801, 0x461a2301, 0x48772106, 0xf0033824, 0x2301fb76, 0xf2402209, 0x48736100, 0xf0033824, 
+    0x2301fb6e, 0x01512208, 0x3824486f, 0xfb67f003, 0x22002301, 0x486c4619, 0xf0033824, 0x2300fb60, 
+    0x21102204, 0x38204868, 0xfb59f003, 0x220c2300, 0x486502a1, 0xf0033820, 0x2300fb52, 0x21042202, 
+    0x381e4861, 0xfb4bf003, 0x461a2301, 0x485e2102, 0xe0bf381e, 0xe0c6e160, 0xd03c0000, 0xffffbbb4, 
+    0xd03c80b8, 0x00054000, 0x00052f8c, 0x00052f90, 0x0003625e, 0x00036260, 0x00036262, 0x00036264, 
+    0x0003626a, 0x000361ec, 0x0003626d, 0x00036268, 0x00036324, 0x00036325, 0x000384d6, 0x000361ce, 
+    0x0003848a, 0x0003848b, 0x0003848c, 0x0003848d, 0x0003848e, 0x0003848f, 0x00038490, 0x0003d090, 
+    0x000384a0, 0x1e8c2120, 0x000384a4, 0x00038491, 0x000384a8, 0x000361f1, 0x000361f2, 0x000361f3, 
+    0x000361f4, 0x000361f5, 0x000361f6, 0x000361f7, 0x000361f8, 0x000361f9, 0x000361fa, 0x000361fb, 
+    0x000361fc, 0x000361fd, 0x000361fe, 0x000361ff, 0x00036200, 0x00036201, 0x00036202, 0x00036203, 
+    0x00036204, 0x00036205, 0x00036206, 0x00036207, 0x00036344, 0x00038b56, 0x00038b57, 0x00036208, 
+    0x00036209, 0x0003620a, 0x0003620b, 0x0003620c, 0x0003620d, 0x0003620e, 0x0003620f, 0x00036210, 
+    0x00036211, 0x00036212, 0x00036213, 0x00036214, 0x00036215, 0x00036216, 0x00036217, 0x00036218, 
+    0x0003621a, 0x0003621c, 0x0003621e, 0x00036220, 0x00036222, 0x00036223, 0x00036224, 0x00036225, 
+    0x000361ef, 0x000362d8, 0x000362da, 0xd003c2a4, 0xd003caa4, 0xd003d2a4, 0xd003daa4, 0x0003625c, 
+    0x000362b1, 0x000362ae, 0xd00352dc, 0xd03c8332, 0x00038492, 0xfa83f003, 0x22002301, 0x48fc4619, 
+    0xfa7df003, 0x48fbe081, 0xbba87800, 0x22012302, 0x48f72106, 0xf0031f80, 0x2302fa72, 0xf2402209, 
+    0x48f36100, 0xf0031f80, 0x2301fa6a, 0x01512208, 0x1f8048ef, 0xfa63f003, 0x22002301, 0x48ec4619, 
+    0xf0031f80, 0x48ecfa5c, 0x22017803, 0x48e82102, 0xf003301e, 0x48e8fa54, 0x22007803, 0x48e42101, 
+    0xf003301e, 0x48e4fa4c, 0x22007803, 0x48e02101, 0xf0033026, 0xe01dfa44, 0x2300e7ff, 0x21062201, 
+    0x1f8048db, 0xfa3bf003, 0x22092300, 0x6100f240, 0x1f8048d7, 0xfa33f003, 0x22082300, 0x48d40151, 
+    0xf0031f80, 0x2300fa2c, 0x2101461a, 0x1f8048d0, 0xfa25f003, 0x22042301, 0x48cd2110, 0xf0031e80, 
+    0x2301fa1e, 0x0319220c, 0x1e8048c9, 0xfa17f003, 0x22022301, 0x48c62104, 0xfa11f003, 0x22012300, 
+    0x48c32102, 0xfa0bf003, 0x461a2300, 0x48c02101, 0xfa05f003, 0x48be2152, 0xf7fc3042, 0xf240fc05, 
+    0x48bb113a, 0xf7fc3044, 0x2301fbff, 0x21702204, 0x1f8048b7, 0xf9f3f003, 0x220c2301, 0x0100f247, 
+    0x1f8048b3, 0xf9ebf003, 0x220a2302, 0x4100f640, 0xf00348b2, 0xe0c7f9e4, 0xd17b2c05, 0x22002302, 
+    0x48af2103, 0xf9dbf003, 0x22092303, 0x48a80259, 0xf0031f80, 0x2303f9d4, 0x21062201, 0x1f8048a4, 
+    0xf9cdf003, 0x22042301, 0x48a12170, 0xf0031f80, 0x2301f9c6, 0xf247220c, 0x489d0100, 0xf0031f80, 
+    0x2301f9be, 0x01512208, 0x1f804899, 0xf9b7f003, 0x22002301, 0x48964619, 0xf0031f80, 0x2301f9b0, 
+    0x21102204, 0x1e804892, 0xf9a9f003, 0x220c2301, 0x488f0319, 0xf0031e80, 0x2301f9a2, 0x21042202, 
+    0xf003488b, 0x2300f99c, 0x21022201, 0xf0034888, 0x2300f996, 0x2101461a, 0xf0034885, 0x2301f990, 
+    0xf640220a, 0x48854100, 0xf989f003, 0x48802129, 0xf7fc3042, 0x219efb89, 0x3044487d, 0xfb84f7fc, 
+    0x7803487d, 0x21022201, 0x301e4879, 0xf977f003, 0x78034879, 0x21012200, 0x301e4875, 0xf96ff003, 
+    0x78034875, 0x21012200, 0x30264871, 0xf967f003, 0xe7ffe04a, 0x461a2300, 0x48712103, 0xf95ff003, 
+    0x22092300, 0x6100f240, 0x1f804869, 0xf957f003, 0x22012300, 0x48662106, 0xf0031f80, 0x2300f950, 
+    0x01512208, 0x1f804862, 0xf949f003, 0x461a2300, 0x485f2101, 0xf0031f80, 0x2301f942, 0x21102204, 
+    0x1e80485b, 0xf93bf003, 0x220c2301, 0x48580319, 0xf0031e80, 0x2301f934, 0x21042202, 0xf0034854, 
+    0x2300f92e, 0x21022201, 0xf0034851, 0x2300f928, 0x2101461a, 0xf003484e, 0x2300f922, 0xf640220a, 
+    0x484e4100, 0xf91bf003, 0xb57cbd10, 0x21004604, 0xf7fc484c, 0x2100fb19, 0x1f80484a, 0xfb14f7fc, 
+    0x49492000, 0x20077008, 0xfcabf009, 0xf0052000, 0xf009fd44, 0xb260f967, 0xfeecf008, 0xfcbbf007, 
+    0x2300200f, 0x4619461a, 0x46189000, 0xfd9ef007, 0x8800483e, 0xd1052801, 0x22002301, 0x483c4619, 
+    0xf8c6f003, 0xffc8f014, 0xf7ff4620, 0x4621fd2a, 0xf7ff2000, 0x4837fc3e, 0x28126800, 0x4835d003, 
+    0x28166800, 0x2002d103, 0xfb6bf018, 0x4832e004, 0xb2407800, 0xfb65f018, 0xf99ff016, 0x7800482f, 
+    0xd1052803, 0xf98ff016, 0x492d2000, 0xe0677008, 0x7800482a, 0xd1052801, 0xf979f016, 0x49282001, 
+    0xe05d7008, 0x78004825, 0xd1082805, 0x88004825, 0xf016b128, 0x2001f96c, 0x70084921, 0x4822e050, 
+    0xb1287800, 0xf963f016, 0x491d2001, 0xe0477008, 0x7800481e, 0xd1052802, 0xf965f016, 0x49182000, 
+    0xe03d7008, 0x78004819, 0xd1052801, 0xf94ff016, 0x49132001, 0xe0337008, 0xf7fc4815, 0xf000fa8f, 
+    0xb3380001, 0xf943f016, 0x490d2001, 0xe0277008, 0xd00352be, 0x00038491, 0x000384e4, 0xd0030802, 
+    0xd03c8332, 0xd03c80b6, 0x00038a5a, 0x000361cc, 0xd18007fc, 0x000361dc, 0x000361fd, 0x0003625c, 
+    0x000361ee, 0x0003631e, 0x0003845c, 0x000361eb, 0xd0035040, 0xf016e7ff, 0x2000f926, 0x700849fe, 
+    0x31fff04f, 0xf7fc48fd, 0xf04ffa54, 0x49fc30ff, 0x48fc6008, 0xf0097800, 0x2000fbd6, 0xfb64f009, 
+    0x21012000, 0x460a4603, 0x1000e9cd, 0x48f24601, 0xb2407800, 0xfc8cf005, 0x22082300, 0x7100f647, 
+    0xf00348f1, 0x2300f83c, 0x217f461a, 0x1c8048ee, 0xf835f003, 0x22082300, 0x7100f647, 0x1c8048ea, 
+    0xf82df003, 0x48e821d2, 0xf7fc1e80, 0x2100fa2d, 0x1f0048e5, 0xfa28f7fc, 0xf00a2002, 0x2001fc69, 
+    0x80c849e2, 0x80488088, 0x46088008, 0xf8e8f006, 0x220c2300, 0x0100f241, 0xf00348dd, 0x2300f810, 
+    0xf242220d, 0x48da0100, 0xf809f003, 0x220e2300, 0x0100f244, 0xf00348d6, 0x2300f802, 0x49d5220f, 
+    0xf00248d3, 0x2301fffc, 0x49d2220f, 0xf00248d2, 0x2028fff6, 0xf9dff007, 0xd1032c04, 0xf0072013, 
+    0xe004f9da, 0xd1022c05, 0xf007201c, 0xf006f9d4, 0xf007fc44, 0xf002f83f, 0x48bffdc8, 0xb9187800, 
+    0x1000f240, 0xfdcbf002, 0xf0072001, 0x48bef9ce, 0xf7fc3020, 0x4605f9d3, 0x301e48bb, 0xf9cef7fc, 
+    0x000af3c0, 0x800849bd, 0x000af3c5, 0x800849bc, 0x461a2300, 0xf9b04608, 0x48b81000, 0x0000f9b0, 
+    0xfd9cf005, 0x22082302, 0x46082101, 0xf9f1f005, 0x46082140, 0xf9daf005, 0x21032214, 0xf0054608, 
+    0x2300f9b9, 0xf24f220c, 0x48a40100, 0xf0021d00, 0x2300ff7f, 0xf6402208, 0x48a07100, 0xf0021d00, 
+    0x2300ff77, 0x21f02204, 0x1d00489c, 0xff70f002, 0x461a2300, 0x4899210f, 0xf0021d00, 0x2301ff69, 
+    0x01512208, 0x38484895, 0xff62f002, 0x2200230f, 0x48954619, 0xf0023076, 0x2300ff82, 0x21802207, 
+    0x30764891, 0xff7bf002, 0x22052300, 0x488e2120, 0xf0023076, 0x2001ff74, 0xf923f01a, 0xf01a2000, 
+    0xf01af872, 0xf004f82b, 0xf004fe7d, 0xf003fe95, 0x4620fb30, 0xfbeaf005, 0xfb75f006, 0x22002301, 
+    0x48814619, 0xf0021f80, 0x2000ff5a, 0xfcfbf005, 0x461a2301, 0x487c2102, 0xf0023008, 0x2000ff50, 
+    0xff96f019, 0x20042100, 0xfe0ef009, 0xf95af00a, 0x78004871, 0x2000b988, 0xff90f009, 0xf9904879, 
+    0xf0090000, 0x2100fd4f, 0xf00a4608, 0x4875f93a, 0x0000f990, 0xfcd0f009, 0x2002e024, 0xff7ef009, 
+    0xf0092000, 0x2001fd3f, 0xfd3cf009, 0xf0092002, 0x2003fd39, 0xfd36f009, 0x8809496b, 0x43512286, 
+    0x2100b208, 0xf91df00a, 0xf9904868, 0xf0090000, 0x4866fcb3, 0x0000f990, 0xf906f00a, 0x486421c0, 
+    0xf912f7fc, 0x88004863, 0xd1062801, 0x220f2301, 0x485f4958, 0xf0023862, 0xf026ff02, 0x2001f9cd, 
+    0xf99ff006, 0x200c2100, 0xf903f006, 0xf0092000, 0x2301ffd1, 0x21042202, 0x38624855, 0xfeeff002, 
+    0xf0042003, 0xf003fa7f, 0xf022fb45, 0x2309f855, 0x21ff2200, 0xf0024850, 0x2111fee2, 0x1f00484e, 
+    0xf8e2f7fc, 0x7800484d, 0xd11728bc, 0x6800484c, 0xd3092812, 0x494b2002, 0x23017008, 0x21082203, 
+    0xf0024849, 0xe060fecc, 0x49462000, 0x23007008, 0x21082203, 0xf0024844, 0xe056fec2, 0x7800483f, 
+    0xd10928ee, 0x493f2003, 0x23017008, 0x21082203, 0xf002483d, 0xe048feb4, 0x78004838, 0xd10928cf, 
+    0x49382005, 0x23007008, 0x21082203, 0xf0024836, 0xe03afea6, 0x78004835, 0xd1152801, 0x78004834, 
+    0xd1112801, 0x6800482e, 0xd3032812, 0x492d2002, 0xe0027008, 0x492b2003, 0x23017008, 0x21082203, 
+    0xf0024829, 0xe020fe8c, 0x7800482a, 0xd1132801, 0x78004829, 0xd10f2801, 0x49222005, 0x23007008, 
+    0x21082203, 0xf0024820, 0x2301fe7a, 0x46192200, 0xf0024822, 0xe008fe74, 0x491a2000, 0x23007008, 
+    0x21082203, 0xf0024818, 0xf04ffe6a, 0x481c31ff, 0xf86af7fc, 0xe037481b, 0x000361ee, 0xd1800048, 
+    0x00038460, 0x00036342, 0xd003501c, 0x00036296, 0xd00305c0, 0xffff8000, 0xd0030412, 0x00036234, 
+    0x00036236, 0x000362b1, 0x000362c8, 0x000362b2, 0xd0030864, 0x000361cc, 0xd0031408, 0x00038b1d, 
+    0x000361dc, 0x00038b1e, 0xd0035256, 0x00038459, 0x0003845a, 0x00038454, 0x00038455, 0xd03c8024, 
+    0xd003513c, 0x00038b38, 0xb2018800, 0xf7fc483e, 0x483ef82b, 0xb2018800, 0x3014483b, 0xf824f7fc, 
+    0x8800483b, 0x4838b201, 0xf7fc1c80, 0x2100f81d, 0x30164835, 0xf818f7fc, 0x48332100, 0xf7fc3018, 
+    0x2100f813, 0x301a4830, 0xf80ef7fc, 0x482e2100, 0xf7fc301c, 0x482ff809, 0x28017800, 0x2300d118, 
+    0x02012208, 0xf002482c, 0x482cfdfa, 0x492c7800, 0x42887809, 0x4829da04, 0x492a7800, 0xe0037008, 
+    0x78004827, 0x70084927, 0xf831f01a, 0xfdc0f006, 0x106cf240, 0x80084924, 0x49242000, 0x23007008, 
+    0x210f461a, 0xf0024822, 0x2000fdda, 0xfc40f015, 0xb510bd7c, 0xfc0ef012, 0xfe51f024, 0xfdd2f00b, 
+    0xfc5cf00c, 0xfde3f00c, 0xfb93f00d, 0xfbeef00f, 0xfb61f010, 0xfed7f010, 0xfaf9f011, 0xf99ef01c, 
+    0xf9a1f01f, 0xfa66f01c, 0xfeadf01d, 0xffe2f022, 0xfd05f01d, 0xff59f022, 0xfda8f024, 0xfb27f022, 
+    0xffe1f01a, 0x0000bd10, 0xd003513e, 0x00038b3c, 0x00052f90, 0x000384e0, 0xd0030480, 0x000384e1, 
+    0x000384e2, 0x000384e3, 0x0003622a, 0x000384d7, 0xd03c8316, 0xe92d500f, 0xe59f0bd8, 0xfb0010c2, 
+    0xe3a02103, 0xe3a01030, 0xe3a00010, 0xfbfff01f, 0xe3a02103, 0xe3a01031, 0xe3a00010, 0xfbfff01b, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d4010, 0xe3a00003, 0xfa001082, 0xe3a00002, 0xfa001080, 
+    0xe3a00001, 0xfa00107e, 0xe3a0000a, 0xfa00107c, 0xe3a00001, 0xfb001026, 0xe3a00002, 0xfb001024, 
+    0xe3a00004, 0xfb001022, 0xe59f0b6c, 0xfb0010a6, 0xe3a00001, 0xe59f1b64, 0xe5c10000, 0xe2810000, 
+    0xe1d000d0, 0xe6ff3070, 0xe3a0200c, 0xe3011000, 0xe59f0b4c, 0xfb000aa0, 0xe59f0b48, 0xe1d000d0, 
+    0xe1e00000, 0xe3500000, 0x0a00000b, 0xe3a02000, 0xe3a01007, 0xe1a00002, 0xfa0016c0, 0xe3a00001, 
+    0xe59f1b24, 0xe1c100b6, 0xe1c100b4, 0xe1c100b2, 0xe1c100b0, 0xe2810000, 0xfa0016f8, 0xe3a0000f, 
+    0xe59f1b08, 0xe1c100b0, 0xe3a02000, 0xe59f0b00, 0xe5900000, 0xfb008d1d, 0xe59f1af8, 0xe5911000, 
+    0xe0800001, 0xe59f1aec, 0xe5810000, 0xe3a02000, 0xe59f1ad8, 0xe59f0ae0, 0xe5900000, 0xfb008d13, 
+    0xe59f1ad0, 0xe5911000, 0xe0800001, 0xe59f1ac4, 0xe5810000, 0xe3a02000, 0xe59f1ab0, 0xe59f0abc, 
+    0xe5900000, 0xfb008d09, 0xe59f1aa8, 0xe5911000, 0xe0800001, 0xe59f1a9c, 0xe5810000, 0xe3a02000, 
+    0xe59f1a88, 0xe59f0a98, 0xe5900000, 0xfb008cff, 0xe59f1a80, 0xe5911000, 0xe0800001, 0xe59f1a74, 
+    0xe5810000, 0xe3a02000, 0xe59f1a60, 0xe59f0a74, 0xe5900000, 0xfb008cf5, 0xe59f1a58, 0xe5911000, 
+    0xe0800001, 0xe59f1a4c, 0xe5810000, 0xe3a02000, 0xe59f1a38, 0xe59f0a50, 0xe5900000, 0xfb008ceb, 
+    0xe59f1a30, 0xe5911000, 0xe0800001, 0xe59f1a24, 0xe5810000, 0xe3a02000, 0xe59f1a10, 0xe59f0a2c, 
+    0xe5900000, 0xfb008ce1, 0xe59f1a08, 0xe5911000, 0xe0800001, 0xe59f19fc, 0xe5810000, 0xe3a02000, 
+    0xe59f19e8, 0xe59f0a08, 0xe5900000, 0xfb008cd7, 0xe59f19e0, 0xe5911000, 0xe0800001, 0xe59f19d4, 
+    0xe5810000, 0xe3a02000, 0xe59f19c0, 0xe59f09e4, 0xe5900000, 0xfb008ccd, 0xe59f19b8, 0xe5911000, 
+    0xe0800001, 0xe59f19ac, 0xe5810000, 0xe3a00007, 0xe59f1998, 0xe1c100b0, 0xe3a02000, 0xe59f09b8, 
+    0xe5900000, 0xfb008cc1, 0xe59f1988, 0xe5911000, 0xe0800001, 0xe59f197c, 0xe5810000, 0xe8bd8010, 
+    0xe92d500f, 0xe59f0950, 0xfb00101f, 0xe3a02103, 0xe3a01032, 0xe3a00010, 0xfbffef7c, 0xe59f097c, 
+    0xe1d000b0, 0xe3500000, 0x1a000036, 0xe3a02003, 0xe3a01008, 0xe59f0968, 0xfa000a23, 0xe3500000, 
+    0x0a000024, 0xe3a02103, 0xe3001101, 0xe3a00010, 0xfbffef6e, 0xfb0075bf, 0xe6af0070, 0xe59f1944, 
+    0xe5c10000, 0xe2810000, 0xe1d000d0, 0xe2801090, 0xe3a02103, 0xe3a00010, 0xfbffef64, 0xe59f0924, 
+    0xe5d00000, 0xe3500000, 0x0a00000c, 0xe3a00005, 0xe59f1914, 0xe1c100b0, 0xe3a02000, 0xe59f08f8, 
+    0xe5900000, 0xfb008c91, 0xe59f18c8, 0xe5911000, 0xe0800001, 0xe59f18bc, 0xe5810000, 0xea000000, 
+    0xebffff39, 0xe3a00004, 0xfb000f69, 0xe3a0000b, 0xfa000fbb, 0xea000007, 0xe3a00000, 0xe59f18c4, 
+    0xe5c10000, 0xebffff30, 0xe3a02103, 0xe3a01001, 0xe3a00010, 0xfbffef45, 0xe59f18a8, 0xe5d10000, 
+    0xfa000f1b, 0xea000003, 0xe3a02103, 0xe3011101, 0xe3a00010, 0xfbffef3d, 0xe3a02103, 0xe3a01033, 
+    0xe3a00010, 0xfbffef39, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe59f0870, 0xfaffeed6, 
+    0xe6ff4070, 0xe59f0868, 0xfb000fcf, 0xe3a02103, 0xe3a01034, 0xe3a00010, 0xfbffef2c, 0xe3a00002, 
+    0xfa000f97, 0xe3a03000, 0xe3a02008, 0xe3001100, 0xe59f0840, 0xfb0009c8, 0xe59f0820, 0xe1d000b0, 
+    0xe3500000, 0x1a00004a, 0xe59f082c, 0xe5d00000, 0xe3500000, 0x1a000003, 0xe59f0820, 0xe1d000b0, 
+    0xe3500001, 0x1a00002a, 0xe59f0814, 0xe5d00000, 0xe3500000, 0x1a000042, 0xe59f0808, 0xe5d00000, 
+    0xe3500000, 0x1a00003e, 0xe59f07fc, 0xe5d00000, 0xe3500000, 0x1a00003a, 0xe3a00007, 0xfa000f2f, 
+    0xe240093d, 0xe2400d09, 0xe59f17e0, 0xe5810000, 0xe3a00001, 0xe59f17d0, 0xe5c10000, 0xe3a0003e, 
+    0xe59f17cc, 0xe1c100b0, 0xe3a02000, 0xe59f0760, 0xe5900000, 0xfb008c35, 0xe59f1758, 0xe5911000, 
+    0xe0800001, 0xe59f174c, 0xe5810000, 0xe3a00000, 0xe59f17a0, 0xe5d11000, 0xe2811001, 0xe2011007, 
+    0xe0811201, 0xe59f2790, 0xe0821101, 0xe5810008, 0xea00001b, 0xe59f0784, 0xe5900000, 0xe3500000, 
+    0x1a00000c, 0xe3a00009, 0xe59f1764, 0xe1c100b0, 0xe3a02000, 0xe59f0720, 0xe5900000, 0xfb008c1b, 
+    0xe59f16f0, 0xe5911000, 0xe0800001, 0xe59f16e4, 0xe5810000, 0xea000001, 0xe320f000, 0xeafffffe, 
+    0xe3a02103, 0xe3a01002, 0xe3a00010, 0xfbffeed7, 0xea000003, 0xe3a02103, 0xe3011102, 0xe3a00010, 
+    0xfbffeed2, 0xe3a02103, 0xe3a01035, 0xe3a00010, 0xfbffeece, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 
+    0xe92d500f, 0xe59f06f8, 0xfb000f67, 0xe3a02103, 0xe3a01036, 0xe3a00010, 0xfbffeec4, 0xe59f069c, 
+    0xe1d000b0, 0xe3500000, 0x1a000052, 0xe59f06a8, 0xe5d00000, 0xe3500000, 0x0a000052, 0xe59f06a0, 
+    0xe5d00000, 0xe3500000, 0x1a00004e, 0xe59f0694, 0xe5d00000, 0xe3500000, 0x1a00004a, 0xe3a00001, 
+    0xe59f167c, 0xe5c10000, 0xe3a03000, 0xe3a02001, 0xe3a01002, 0xe59f068c, 0xfb00094f, 0xe3a00000, 
+    0xfb001242, 0xe59f0680, 0xe5d00000, 0xe3500000, 0x1a000000, 0xfa0024e2, 0xe3a00001, 0xfa0075d8, 
+    0xe3a00001, 0xe59f164c, 0xe5d11000, 0xe2811001, 0xe2011007, 0xe0811201, 0xe59f263c, 0xe0821101, 
+    0xe5810008, 0xe3a00007, 0xfa000ebc, 0xe240093d, 0xe2400d09, 0xe59f1614, 0xe5810000, 0xe3a0000a, 
+    0xfa000eff, 0xe3a00000, 0xe59f15f0, 0xe1c100b0, 0xe3a00002, 0xfa000efa, 0xe3a00003, 0xfa000ef8, 
+    0xe3a03000, 0xe3a02008, 0xe3001100, 0xe59f05c4, 0xfb000929, 0xe3a01000, 0xe3a00001, 0xfb0017a4, 
+    0xe30011f4, 0xe3a00401, 0xfaffee9d, 0xe30d1ddd, 0xe3a00401, 0xfaffee72, 0xe59f15d0, 0xe3a00401, 
+    0xfaffee6f, 0xe3a00043, 0xe59f15c4, 0xe1c100b0, 0xe3a02000, 0xe59f0538, 0xe5900000, 0xfb008bab, 
+    0xe59f1530, 0xe5911000, 0xe0800001, 0xe59f1524, 0xe5810000, 0xea000003, 0xe3a02103, 0xe3011103, 
+    0xe3a00010, 0xfbffee69, 0xe3a02103, 0xe3a01037, 0xe3a00010, 0xfbffee65, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d5fff, 0xe24dd008, 0xe3a02103, 0xe3a01038, 0xe3a00010, 0xfbffee5c, 0xe59f0554, 
+    0xfaffedfd, 0xe6ff9070, 0xe3a0200e, 0xe3041000, 0xe59f0544, 0xfa000904, 0xe3500000, 0x0a000003, 
+    0xe3a00000, 0xe59f1534, 0xe5c10000, 0xea000002, 0xe7e00759, 0xe59f1524, 0xe5c10000, 0xe59f0520, 
+    0xfaffeded, 0xe6ff7070, 0xe7e00659, 0xe59f1514, 0xe5c10000, 0xe59f0510, 0xfaffede7, 0xe1a04000, 
+    0xe7e003d4, 0xe59f1504, 0xe5c10000, 0xe59f0500, 0xfaffede1, 0xe1a06000, 0xe59f04f8, 0xfaffedde, 
+    0xe1a05000, 0xe59f04f0, 0xfaffeddb, 0xe1a08000, 0xe3a02000, 0xe1a01006, 0xe3a00001, 0xfaffee46, 
+    0xe3a02000, 0xe1a01005, 0xe3a00001, 0xfaffee42, 0xe3a02000, 0xe1a01004, 0xe3a00001, 0xfaffee3e, 
+    0xe59f0438, 0xe1d000b0, 0xe3c000e1, 0xe3500000, 0x0a000006, 0xe3e00000, 0xfa002626, 0xe59f249c, 
+    0xe3041004, 0xe3a00004, 0xfbffee20, 0xea000076, 0xe3a02000, 0xe59f0464, 0xe5d01000, 0xe3a00001, 
+    0xfaffee2d, 0xe59f0454, 0xe5d00000, 0xe3500000, 0x0a000005, 0xe59f03e4, 0xe1d000b0, 0xe3800080, 
+    0xe59f13d8, 0xe1c100b0, 0xea000004, 0xe59f03cc, 0xe1d000b0, 0xe3c00080, 0xe59f13c0, 0xe1c100b0, 
+    0xe2050b01, 0xe3500000, 0x0a000005, 0xe59f040c, 0xe5d00000, 0xe3500000, 0x0a000001, 0xe3a00001, 
+    0xea000000, 0xe3a00000, 0xe1a0a000, 0xe2060010, 0xe3500000, 0x1a000002, 0xe2050c01, 0xe3500000, 
+    0x0a000008, 0xe2040010, 0xe3500000, 0x0a000005, 0xe59f03d0, 0xe5d00000, 0xe3500000, 0x1a000001, 
+    0xe3a00001, 0xea000000, 0xe3a00000, 0xe1a0b000, 0xe2060020, 0xe3500000, 0x1a000002, 0xe2050c01, 
+    0xe3500000, 0x0a000008, 0xe2040020, 0xe3500000, 0x0a000005, 0xe59f038c, 0xe5d00000, 0xe3500000, 
+    0x1a000001, 0xe3a00001, 0xea000000, 0xe3a00000, 0xe58d0004, 0xe35a0000, 0x1a00000c, 0xe59f0380, 
+    0xe5d00000, 0xe3500000, 0x1a000015, 0xe59f034c, 0xe5d00000, 0xe3500000, 0x1a000011, 0xe35b0000, 
+    0x1a000002, 0xe59d0004, 0xe3500000, 0x0a00000c, 0xe59f02d0, 0xe5d00000, 0xe3500003, 0x0a000007, 
+    0xe59f02c0, 0xe5d00000, 0xe3500004, 0x0a000003, 0xe59f02b0, 0xe5d00000, 0xe3500005, 0x1a000000, 
+    0xebfffda9, 0xe2070001, 0xe3500000, 0x1a000002, 0xe2070002, 0xe3500000, 0x0a000012, 0xe3e00000, 
+    0xfa0025bc, 0xe59f12fc, 0xe1c160b2, 0xe1c140b4, 0xe1c150b6, 0xe1c180b8, 0xe3a0006d, 0xe1c100b0, 
+    0xe3a02000, 0xe59f02e0, 0xe5900000, 0xfb008ae7, 0xe59f1220, 0xe5911000, 0xe0800001, 0xe59f1214, 
+    0xe5810000, 0xea000000, 0xe320f000, 0xe3a02103, 0xe3a01039, 0xe3a00010, 0xfbffeda4, 0xe59f02ac, 
+    0xfb000e41, 0xf57ff05f, 0xe28dd008, 0xe8bd5fff, 0xe25ef004, 0xe92d500f, 0xe59f0294, 0xfb000e3a, 
+    0xe3a02103, 0xe3a0103a, 0xe3a00010, 0xfbffed97, 0xe3a02103, 0xe3a0103b, 0xe3a00010, 0xfbffed93, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0260, 0xfb000e2c, 0xe3a02103, 0xe3a0103c, 
+    0xe3a00010, 0xfbffed89, 0xe3a00008, 0xe59f1248, 0xe1c100b0, 0xe3a02000, 0xe59f019c, 0xe5900000, 
+    0xfb008aba, 0xe59f116c, 0xe5911000, 0xe0800001, 0xe59f1160, 0xe5810000, 0xe3a02103, 0xe3a0103d, 
+    0xe3a00010, 0xfbffed79, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0200, 0xfb000e12, 
+    0xe3a02103, 0xe3a0103e, 0xe3a00010, 0xfbffed6f, 0xebfffd55, 0xe3a02103, 0xe3a01007, 0xe3a00402, 
+    0xfbffed6a, 0xe3a02103, 0xe3a0103f, 0xe3a00010, 0xfbffed66, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f01b8, 0xfb000dff, 0xe3a02103, 0xe3a01040, 0xe3a00010, 0xfbffed5c, 0xe3a02103, 
+    0xe3a01041, 0xe3a00010, 0xfbffed58, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe3a02103, 
+    0xe3a0107a, 0xe3a00010, 0xfbffed50, 0xe59f0174, 0xfb000ded, 0xe59f0170, 0xfaffecef, 0xe3500000, 
+    0x0a000061, 0xe3a01001, 0xe59f0160, 0xfaffeced, 0xe3a01000, 0xe59f0158, 0xfaffecea, 0xe59f1154, 
+    0xe59f0148, 0xfaffece7, 0xe3a00062, 0xe59f1148, 0xe1c100b0, 0xe59f0144, 0xfaffecdf, 0xe59f1138, 
+    0xe1c100b2, 0xe3a02000, 0xe59f0134, 0xe5900000, 0xfb008a6e, 0xe59f103c, 0xe5911000, 0xe0800001, 
+    0xe59f1030, 0xe5810000, 0xe3e01000, 0xe59f0114, 0xfaffecd4, 0xea000087, 0xc1000104, 0xc1000114, 
+    0x00036277, 0xd003902c, 0x000362ce, 0x00036296, 0x0003854c, 0x00038b18, 0x000361e4, 0x000385b4, 
+    0x000385cc, 0x000385dc, 0x000385ec, 0x0003860c, 0x00038620, 0x00038634, 0x00038644, 0x00038654, 
+    0x00036268, 0xd0035040, 0x0003626a, 0x000384fc, 0xd03c80b6, 0xc1000124, 0xd0035126, 0x00038b1c, 
+    0x00038dc2, 0x00036344, 0x00038b56, 0x00038b57, 0x000362ec, 0x00038504, 0x00038b38, 0x00048c18, 
+    0x00052f80, 0xc1000134, 0xd0035114, 0x000361ee, 0xdcba01f5, 0x0003850c, 0xd28fffc0, 0xd0060000, 
+    0x00036266, 0xd0039048, 0x00036265, 0xd0039026, 0x00036267, 0xd0039028, 0xd0039018, 0xd0039016, 
+    0xcccc0000, 0x0003625e, 0x0004c820, 0x00038dc4, 0xc1000144, 0xc1000154, 0xc1000164, 0x00038514, 
+    0xc1000174, 0xc1000184, 0xc1000194, 0xd03c8082, 0xd03c806e, 0xd03c807a, 0xffffbbbb, 0x0003851c, 
+    0xd03c800a, 0x00038b0c, 0xd03c807e, 0xe59f0db8, 0xfaffec89, 0xe3500000, 0x0a00003e, 0xe59f0dac, 
+    0xfaffec85, 0xe7e007d0, 0xe51f1128, 0xe5c10000, 0xe2810000, 0xe5d00000, 0xe3500001, 0x1a00002d, 
+    0xe3a03000, 0xe3a0200f, 0xe2431902, 0xe59f0d7c, 0xfb000779, 0xe3a03001, 0xe3a0200b, 0xe3001800, 
+    0xe59f0d68, 0xfb000774, 0xe59f0d64, 0xe5d00000, 0xe3500000, 0x1a000013, 0xe59f0d50, 0xfaffec6e, 
+    0xe7e006d0, 0xe59f1d4c, 0xe5c10000, 0xe59f0d3c, 0xfaffec69, 0xe7e00550, 0xe59f1d3c, 0xe5c10000, 
+    0xe59f0d28, 0xfaffec64, 0xe7e203d0, 0xe59f1d2c, 0xe5c10000, 0xe59f0d14, 0xfaffec5f, 0xe7e102d0, 
+    0xe59f1d1c, 0xe5c10000, 0xe59f1d18, 0xe59f0d18, 0xfaffec5c, 0xe51f019c, 0xe1d000b0, 0xe3800010, 
+    0xe51f11a8, 0xe1c100b0, 0xe3a00004, 0xfa000d1c, 0xebfffc95, 0xea000007, 0xe3e01000, 0xe59f0ce8, 
+    0xfaffec50, 0xe51f01cc, 0xe1d000b0, 0xe3c00010, 0xe51f11d8, 0xe1c100b0, 0xe3a02103, 0xe3a0107b, 
+    0xe3a00010, 0xfbffeca1, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe3a02103, 0xe3a01076, 
+    0xe3a00010, 0xfbffec99, 0xe59f0ca0, 0xfaffec3a, 0xe59f1c9c, 0xe1c100b0, 0xe51f0220, 0xe1d000b0, 
+    0xe3500000, 0x1a00004b, 0xe30011f4, 0xe3a00401, 0xfaffecab, 0xe59f0c78, 0xe1d000f0, 0xe2801903, 
+    0xe3a00401, 0xfaffec7e, 0xe51f1200, 0xe3a00401, 0xfaffec7b, 0xe59f0c58, 0xe5d00000, 0xe2000008, 
+    0xe3500000, 0x0a00000b, 0xe51f0260, 0xfaffec22, 0xe1a04000, 0xe2040a01, 0xe3500000, 0x0a000004, 
+    0xe30e0fff, 0xe0000004, 0xe6bf1070, 0xe51f0284, 0xfaffec1c, 0xe320f000, 0xe51f0280, 0xe1d000b0, 
+    0xe3500000, 0x0a000015, 0xe59f0c04, 0xe5d00000, 0xe2000004, 0xe3500000, 0x1a000004, 0xe59f0bf0, 
+    0xe5d00000, 0xe2000002, 0xe3500000, 0x0a00000b, 0xe3a00001, 0xe59f1bdc, 0xe5c10000, 0xe3a01014, 
+    0xe59f0bd4, 0xfaffec07, 0xe3a01011, 0xe59f0bcc, 0xfaffec04, 0xe3a01012, 0xe59f0bc0, 0xfaffec01, 
+    0xe51f02e8, 0xe1d000b0, 0xe3500000, 0x0a000015, 0xe59f0b9c, 0xe5d00000, 0xe2000040, 0xe3500000, 
+    0x0a000010, 0xe3a00001, 0xe59f1b94, 0xe5c10000, 0xe3a01012, 0xe59f0b80, 0xfaffebf2, 0xe3a01011, 
+    0xe59f0b78, 0xfaffebef, 0xe3a01012, 0xe59f0b6c, 0xfaffebec, 0xea000003, 0xe3a02103, 0xe3001176, 
+    0xe3a00010, 0xfbffec41, 0xe3a02103, 0xe3a01077, 0xe3a00010, 0xfbffec3d, 0xe59f0b48, 0xfb000cda, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d503f, 0xe59f0b34, 0xfb000cd4, 0xe59f0b30, 0xe5d00000, 
+    0xe3500001, 0x1a000018, 0xe3a02103, 0xe3a01042, 0xe3a00010, 0xfbffec2d, 0xe59f0b14, 0xfaffebce, 
+    0xe1a04000, 0xe3a02000, 0xe1a01004, 0xe3a00010, 0xfbffec26, 0xe3a01000, 0xe3a00070, 0xfb000791, 
+    0xe6ff0070, 0xe3804001, 0xe1a01004, 0xe3a00070, 0xfb000781, 0xebfffc04, 0xe3a02103, 0xe3a01043, 
+    0xe3a00010, 0xfaffec2c, 0xea00000f, 0xe59f0abc, 0xe5d00000, 0xe3500002, 0x1a00000b, 0xe3a00001, 
+    0xfa0017d2, 0xe3a03001, 0xe3a02000, 0xe1a01003, 0xe51f03f0, 0xfb0006b0, 0xe3a03001, 0xe1a02003, 
+    0xe3a01002, 0xe51f0404, 0xfb0006ab, 0xe3a00000, 0xe59f1a78, 0xe5c10000, 0xe3a0000b, 0xfa000c70, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d500f, 0xe59f0a60, 0xfb000c9c, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f0a4c, 0xfb000c96, 0xe3a02103, 0xe3a01044, 0xe3a00010, 0xfbffebf3, 
+    0xe3a02103, 0xe3a01045, 0xe3a00010, 0xfbffebef, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 
+    0xe3a01001, 0xe59f0a14, 0xfaffeb8e, 0xe3a02103, 0xe3a0107f, 0xe3a00010, 0xfbffebe4, 0xe3a0006f, 
+    0xe59f19fc, 0xe1c100b0, 0xe59f09f8, 0xfaffeb82, 0xe1a04000, 0xe59f09f0, 0xfaffeb7f, 0xe0840800, 
+    0xe59f19dc, 0xe5810004, 0xe3a00001, 0xfb008ec1, 0xe3a02000, 0xe59f19c8, 0xe59f09d0, 0xe5900000, 
+    0xfb00890a, 0xe51f1554, 0xe5911000, 0xe0800001, 0xe51f1560, 0xe5810000, 0xe59f09b4, 0xfb000c6a, 
+    0xe3a02103, 0xe3a01080, 0xe3a00010, 0xfbffebc7, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d500f, 
+    0xe59f0990, 0xfb000c60, 0xe3a02103, 0xe3a0104a, 0xe3a00010, 0xfbffebbd, 0xe3a02103, 0xe3a0104b, 
+    0xe3a00010, 0xfbffebb9, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f095c, 0xfb000c52, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xfa000be1, 0xe59f0944, 0xfb000c4b, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0930, 0xfb000c45, 0xe3a02103, 0xe3a01058, 0xe3a00010, 
+    0xfbffeba2, 0xe3a02103, 0xe3a01059, 0xe3a00010, 0xfbffeb9e, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f08fc, 0xfb000c37, 0xe3a02103, 0xe3a0105e, 0xe3a00010, 0xfbffeb94, 0xe59f08e8, 
+    0xfaffeb30, 0xe59f18e4, 0xe5810000, 0xe59f08e0, 0xfaffeb2c, 0xe6bf0070, 0xe59f18d8, 0xe1c100b0, 
+    0xe59f08c8, 0xe5900000, 0xe3a01001, 0xe0010fa0, 0xe59f18c4, 0xe5c10000, 0xe2810000, 0xe5d00000, 
+    0xe3500001, 0x0a00005b, 0xe59f08a0, 0xe5900000, 0xe7e10d50, 0xe59f18a4, 0xe5c10000, 0xe59f088c, 
+    0xe5900000, 0xe7e40850, 0xe59f1894, 0xe5c10000, 0xe59f0878, 0xe1d000b0, 0xe6bf0070, 0xe59f1884, 
+    0xe1c100b0, 0xe59f0874, 0xe5d00000, 0xe3500001, 0x1a000048, 0xe59f0868, 0xe5d00000, 0xe3500007, 
+    0x1a000020, 0xe2810000, 0xe1d000b0, 0xe6ff0070, 0xe30f1ff8, 0xe1500001, 0x1a00001a, 0xe59f0834, 
+    0xe5d00000, 0xe2000007, 0xe3500007, 0x0a000039, 0xe59f0820, 0xe5d00000, 0xe2000022, 0xe3500022, 
+    0x1a000005, 0xe3a03001, 0xe3a0200f, 0xe59f1794, 0xe59f0814, 0xfb0005f8, 0xea00002e, 0xe59f07f4, 
+    0xe5d00000, 0xe2000022, 0xe3500002, 0x1a000029, 0xe3a03000, 0xe3a0200f, 0xe2431902, 0xe59f07e8, 
+    0xfb0005ed, 0xea000023, 0xe59f07d4, 0xe5d00000, 0xe3500007, 0x1a000010, 0xe59f07c8, 0xe1d000b0, 
+    0xe6ff0070, 0xe30f1fe0, 0xe1500001, 0x1a00000a, 0xe59f07a0, 0xe1d000b0, 0xe2000902, 0xe3500000, 
+    0x0a000014, 0xe3a03001, 0xe3a02002, 0xe3a01004, 0xe59f0798, 0xfb0005d8, 0xea00000e, 0xe59f0780, 
+    0xe5d00000, 0xe3500007, 0x1a00000a, 0xe59f0774, 0xe1d000b0, 0xe6ff0070, 0xe3500000, 0x1a000005, 
+    0xe59f0750, 0xe1d000b0, 0xe2000902, 0xe3500000, 0x0a000000, 0xfb00243c, 0xe3a02103, 0xe3a0105f, 
+    0xe3a00010, 0xfbffeb21, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe3a02103, 0xe3a01060, 
+    0xe3a00010, 0xfbffeb19, 0xe3a01003, 0xe59f0720, 0xfaffeabc, 0xe59f071c, 0xfb000bb3, 0xe3a02103, 
+    0xe3a01061, 0xe3a00010, 0xfbffeb10, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d4070, 0xe1a04000, 
+    0xe1a05004, 0xe1a00005, 0xebffeaa2, 0xe6ff5070, 0xe265001f, 0xe3a01001, 0xe1a00011, 0xe6ff0070, 
+    0xe8bd8070, 0xe92d503f, 0xe59f06cc, 0xfb000b9e, 0xe3a02103, 0xe3a0107c, 0xe3a00010, 0xfbffeafb, 
+    0xfb0014f8, 0xe1a05000, 0xe320f000, 0xe1a00005, 0xebffffe8, 0xe1a04000, 0xe3540008, 0x1a00000f, 
+    0xe3a02103, 0xe3051000, 0xe3a00010, 0xfbffeaef, 0xe3a01001, 0xe3a00008, 0xfb00136b, 0xe3a00000, 
+    0xfa0014e4, 0xe3a0001e, 0xfa000b55, 0xe3a0001f, 0xfa000b53, 0xebfffacc, 0xfb00133f, 0xea000005, 
+    0xe320f000, 0xe3a02103, 0xe3a0107c, 0xe3a00010, 0xfbffeade, 0xe320f000, 0xe320f000, 0xfb0014d9, 
+    0xe1a05000, 0xe3550000, 0x1affffdf, 0xe3a02103, 0xe3a0107d, 0xe3a00010, 0xfbffead4, 0xf57ff05f, 
+    0xe8bd503f, 0xe25ef004, 0xe92d500f, 0xe59f060c, 0xfb000b6d, 0xe3a02103, 0xe3a01064, 0xe3a00010, 
+    0xfbffeaca, 0xe3a0001e, 0xfb000b42, 0xe59f15f0, 0xe5c10000, 0xe2810000, 0xe5d00000, 0xe3500000, 
+    0x1a000004, 0xe3a02103, 0xe3a0101f, 0xe3a00801, 0xfbffeabe, 0xea000003, 0xe3a02103, 0xe3a0101e, 
+    0xe3a00801, 0xfbffeab9, 0xe3a02103, 0xe3a01065, 0xe3a00010, 0xfbffeab5, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f0598, 0xfb000b4e, 0xe3a02103, 0xe3a01066, 0xe3a00010, 0xfbffeaab, 
+    0xe3a0001f, 0xfb000b23, 0xe59f157c, 0xe5c10000, 0xe2810000, 0xe5d00000, 0xe3500000, 0x1a00000b, 
+    0xe3a02103, 0xe3a01021, 0xe3a00801, 0xfbffea9f, 0xe3a03000, 0xe3a0200a, 0xe3001400, 0xe59f054c, 
+    0xfb00053d, 0xe3a00001, 0xfb004ec5, 0xea000005, 0xe3a02103, 0xe3a01020, 0xe3a00801, 0xfbffea93, 
+    0xe3a00000, 0xfb004ebe, 0xe3a02103, 0xe3a01067, 0xe3a00010, 0xfbffea8d, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f0504, 0xfb000b26, 0xe3a02103, 0xe3a0106a, 0xe3a00010, 0xfbffea83, 
+    0xe3a02103, 0xe3a0106b, 0xe3a00010, 0xfbffea7f, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 
+    0xe59f04d0, 0xfb000b18, 0xe3a02103, 0xe3a0104c, 0xe3a00010, 0xfbffea75, 0xe3a00021, 0xfb000aed, 
+    0xe6af0070, 0xe59f14b0, 0xe5c10000, 0xe2810000, 0xe5d00000, 0xe3500000, 0x1a000009, 0xe51f0ac4, 
+    0xe1d000b0, 0xe3c00002, 0xe51f1ad0, 0xe1c100b0, 0xe3a02103, 0xe3a01010, 0xe1a00001, 0xfbffea63, 
+    0xea000008, 0xe51f0aec, 0xe1d000b0, 0xe3800002, 0xe51f1af8, 0xe1c100b0, 0xe3a02103, 0xe3001110, 
+    0xe3a00010, 0xfbffea59, 0xebfffa3f, 0xe3a02103, 0xe3a0104d, 0xe3a00010, 0xfbffea54, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f042c, 0xfb000aed, 0xe3a02103, 0xe3a01068, 0xe3a00010, 
+    0xfbffea4a, 0xe3a0200e, 0xe3041000, 0xe51f0af8, 0xfa0004f5, 0xe3500000, 0x0a000005, 0xe3a00022, 
+    0xfb000abc, 0xe6af0070, 0xe51f1aec, 0xe5c10000, 0xea000002, 0xe3a00000, 0xe51f1afc, 0xe5c10000, 
+    0xe51f0b04, 0xe5d00000, 0xe3500000, 0x1a00000e, 0xe51f0b98, 0xe1d000b0, 0xe3c00001, 0xe51f1ba4, 
+    0xe1c100b0, 0xe3a02103, 0xe3a01011, 0xe3a00201, 0xfbffea2e, 0xe51f0bbc, 0xe1d000b0, 0xe3500000, 
+    0x1a00001c, 0xebfffa10, 0xea00001a, 0xe51f0bd4, 0xe1d000b0, 0xe3500000, 0x1a000001, 0xebfffa0a, 
+    0xea00000b, 0xe3a00022, 0xe59f1374, 0xe1c100b0, 0xe3a02000, 0xe51f0c00, 0xe5900000, 0xfb008753, 
+    0xe51f1c30, 0xe5911000, 0xe0800001, 0xe51f1c3c, 0xe5810000, 0xe51f0c1c, 0xe1d000b0, 0xe3800001, 
+    0xe51f1c28, 0xe1c100b0, 0xe3a02103, 0xe3001111, 0xe3a00201, 0xfbffea0d, 0xe3a02103, 0xe3a01069, 
+    0xe3a00010, 0xfbffea09, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0308, 0xfb000aa2, 
+    0xe3a02103, 0xe3a01052, 0xe3a00010, 0xfbffe9ff, 0xe3a02103, 0xe3a01053, 0xe3a00010, 0xfbffe9fb, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe3a02103, 0xe3a0105a, 0xe3a00010, 0xfbffe9f3, 
+    0xe59f02c4, 0xfb000a90, 0xe3a03001, 0xe1a02003, 0xe3a01002, 0xe59f02b4, 0xfb00048f, 0xe3a00001, 
+    0xe59f12ac, 0xe5c10000, 0xfb004fe2, 0xe3a02000, 0xe59f02a0, 0xe1d010b0, 0xe3a00010, 0xfbffe9e3, 
+    0xe3a00002, 0xfa00050d, 0xe6ff4070, 0xe59f0288, 0xe5d00000, 0xe3500000, 0x1a000006, 0xe3c44020, 
+    0xe51f0d08, 0xe1d000b0, 0xe3c00020, 0xe51f1d14, 0xe1c100b0, 0xea000005, 0xe3844020, 0xe51f0d24, 
+    0xe1d000b0, 0xe3800020, 0xe51f1d30, 0xe1c100b0, 0xe59f0248, 0xe5d00000, 0xe3500000, 0x1a000006, 
+    0xe3c44020, 0xe51f0d4c, 0xe1d000b0, 0xe3c00040, 0xe51f1d58, 0xe1c100b0, 0xea000005, 0xe3844020, 
+    0xe51f0d68, 0xe1d000b0, 0xe3800040, 0xe51f1d74, 0xe1c100b0, 0xe1a01004, 0xe3a00002, 0xfb0004dc, 
+    0xe51f0d88, 0xe1d000b0, 0xe3c00060, 0xe3500000, 0x1a000001, 0xebfff99c, 0xea00000b, 0xe3a02103, 
+    0xe3a01022, 0xe3a00010, 0xfbffe9b0, 0xe3a03000, 0xe3a02001, 0xe3a01002, 0xe59f01b0, 0xfb00044e, 
+    0xe3a00000, 0xe59f11a8, 0xe5c10000, 0xe3a02103, 0xe3a0105b, 0xe3a00010, 0xfbffe9a4, 0xf57ff05f, 
+    0xe8bd503f, 0xe25ef004, 0xe92d500f, 0xe59f0190, 0xfb000a3d, 0xe3a02103, 0xe3a0104e, 0xe3a00010, 
+    0xfbffe99a, 0xe59f017c, 0xfaffe93b, 0xe200001f, 0xe59f1174, 0xe1c100b0, 0xe2810000, 0xe1d000f0, 
+    0xe59f1168, 0xe1d110f0, 0xe1500001, 0x0a000073, 0xe59f0154, 0xe1d000f0, 0xe59f1150, 0xe1c100b0, 
+    0xe59f0144, 0xe1d000b0, 0xe3500000, 0x1a000050, 0xe51f0e58, 0xe1d000b0, 0xe3c00004, 0xe51f1e64, 
+    0xe1c100b0, 0xe3a02103, 0xe3001112, 0xe3a00201, 0xfbffe97e, 0xe51f0e7c, 0xe1d000b0, 0xe3500000, 
+    0x1a00005e, 0xebfff960, 0xea00005c, 0xd03c8084, 0xd03c800c, 0x000362d4, 0x000362cf, 0x000362d0, 
+    0x000362d1, 0x000362d2, 0xffff8000, 0xd03c8080, 0xd00314ce, 0x00038b54, 0x00038db2, 0xd0031408, 
+    0xd0031404, 0x00038db4, 0xc10001a4, 0xc10001b4, 0x0003845b, 0xd28f0004, 0xc10001c4, 0xc10001d4, 
+    0xd03d101a, 0x0004c830, 0xd03d1028, 0xd03d102a, 0x00038e74, 0xc10001e4, 0xc10001f4, 0xc1000234, 
+    0xc1000244, 0xc1000274, 0xc10002a4, 0xd1800288, 0x00038524, 0xd180028c, 0x0003852c, 0x0003852a, 
+    0x00038528, 0x00038529, 0x0003852e, 0xd03c8034, 0xd03c830c, 0xd03d104e, 0xc10002b4, 0xc10002c4, 
+    0xc10002e4, 0x00036334, 0xc10002f4, 0x00036333, 0xd00350f6, 0xc1000304, 0xc1000314, 0x00036264, 
+    0xc1000324, 0x00038530, 0xc1000334, 0xc1000344, 0xd03c801c, 0x00036270, 0x0003626e, 0x0003626d, 
+    0x0003626b, 0xc1000354, 0xd0020012, 0x00036260, 0x00036262, 0xe51f0f9c, 0xe1d000b0, 0xe3500000, 
+    0x1a000001, 0xebfff918, 0xea00000b, 0xe3a00021, 0xe59f1544, 0xe1c100b0, 0xe3a02000, 0xe51f0fc8, 
+    0xe5900000, 0xfb008661, 0xe51f1ff8, 0xe5911000, 0xe0800001, 0xe59f1524, 0xe5810000, 0xe51f0fe4, 
+    0xe1d000b0, 0xe3800004, 0xe51f1ff0, 0xe1c100b0, 0xe3a02103, 0xe3a01012, 0xe3a00201, 0xfbffe91b, 
+    0xe3a02103, 0xe3a0104f, 0xe3a00010, 0xfbffe917, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 
+    0xe59f04dc, 0xfb0009b0, 0xe3a02103, 0xe3a01050, 0xe3a00010, 0xfbffe90d, 0xe59f04c8, 0xfaffe8ae, 
+    0xe7e206d0, 0xe59f14c0, 0xe5c10000, 0xe59f04b4, 0xfaffe8a9, 0xe7e20550, 0xe59f14b0, 0xe5c10000, 
+    0xe59f04ac, 0xe5d00000, 0xe59f149c, 0xe5d11000, 0xe1500001, 0x1a000009, 0xe59f048c, 0xe5d00000, 
+    0xe3500004, 0x1a00003f, 0xe59f0488, 0xe5d00000, 0xe59f1478, 0xe5d11000, 0xe1500001, 0x0a000039, 
+    0xe59f046c, 0xe5d00000, 0xe3500000, 0x1a000010, 0xe59f0454, 0xe5d00000, 0xe3500007, 0x1a00000c, 
+    0xe3a0006e, 0xe59f1450, 0xe1c100b0, 0xe3a02000, 0xe59f0448, 0xe5900000, 0xfb00861c, 0xe59f141c, 
+    0xe5911000, 0xe0800001, 0xe59f1410, 0xe5810000, 0xea00001c, 0xe3a03000, 0xe3a0200c, 0xe3011000, 
+    0xe59f041c, 0xfb00037c, 0xe3a03000, 0xe3a0200b, 0xe3001800, 0xe59f0408, 0xfb000377, 0xe59f0404, 
+    0xe1d000b0, 0xe3c00008, 0xe3500000, 0x1a000001, 0xebfff8b5, 0xea00000b, 0xe3a00006, 0xe59f13d8, 
+    0xe1c100b0, 0xe3a02000, 0xe59f03dc, 0xe5900000, 0xfb0085fe, 0xe59f13a4, 0xe5911000, 0xe0800001, 
+    0xe59f1398, 0xe5810000, 0xe59f039c, 0xe5d00000, 0xe59f139c, 0xe5c10000, 0xe59f0390, 0xe5d00000, 
+    0xe59f1390, 0xe5c10000, 0xe59f037c, 0xe5d00000, 0xe3500000, 0x1a000005, 0xe59f0388, 0xe1d000b0, 
+    0xe3c00008, 0xe59f137c, 0xe1c100b0, 0xea000004, 0xe59f0370, 0xe1d000b0, 0xe3800008, 0xe59f1364, 
+    0xe1c100b0, 0xe3a02103, 0xe3a01051, 0xe3a00010, 0xfbffe8a6, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f0344, 0xfb00093f, 0xe3a02103, 0xe3a01074, 0xe3a00010, 0xfbffe89c, 0xe3a02103, 
+    0xe3a01075, 0xe3a00010, 0xfbffe898, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0310, 
+    0xfb000931, 0xe3a02103, 0xe3a0106c, 0xe3a00010, 0xfbffe88e, 0xe3a02103, 0xe3a0106d, 0xe3a00010, 
+    0xfbffe88a, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f02dc, 0xfb000923, 0xe3a02103, 
+    0xe3a01046, 0xe3a00010, 0xfbffe880, 0xe3a02103, 0xe3a01047, 0xe3a00010, 0xfbffe87c, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe3a02103, 0xe3a01081, 0xe3a00010, 0xfbffe874, 0xe59f0298, 
+    0xe1d000b0, 0xe3500001, 0x1a000002, 0xe3a00002, 0xe59f1284, 0xe1c100b0, 0xe3a00000, 0xe59f127c, 
+    0xe1c100b6, 0xe1c100b4, 0xe1c100b2, 0xe1c100b0, 0xe2810000, 0xfa000f71, 0xe3a00001, 0xfb001b2a, 
+    0xe3a01000, 0xe3a00040, 0xfa000846, 0xe3a00000, 0xfb001b25, 0xe3a0100f, 0xe59f0244, 0xfaffe801, 
+    0xe59f0240, 0xfb0008f8, 0xe59f023c, 0xe5d00000, 0xe3500003, 0x0a000007, 0xe59f022c, 0xe5d00000, 
+    0xe3500005, 0x0a000003, 0xe59f021c, 0xe5d00000, 0xe3500004, 0x1a00004d, 0xe59f0210, 0xe5900000, 
+    0xe2800001, 0xe59f1204, 0xe5810000, 0xe59f0200, 0xe5d00000, 0xe3500000, 0x1a000010, 0xe3a00007, 
+    0xfa000866, 0xe59f11ec, 0xe5911000, 0xe0400001, 0xe3500000, 0xda000005, 0xe59f01dc, 0xe1d000b0, 
+    0xe2800001, 0xe59f11d0, 0xe1c100b0, 0xea000026, 0xe3a00000, 0xe59f11c0, 0xe1c100b0, 0xea000022, 
+    0xe3a01071, 0xe3a00501, 0xfaffe84d, 0xe3a02000, 0xe30017ff, 0xe59f01a4, 0xfa0002db, 0xe1a04000, 
+    0xe1a01004, 0xe3a00501, 0xfaffe81d, 0xe59f0190, 0xe5900000, 0xe2000501, 0xe3500000, 0x0a000012, 
+    0xe59f0180, 0xe5900000, 0xe3500000, 0x1a00000e, 0xe59f0174, 0xe5900000, 0xe30017fe, 0xe1500001, 
+    0xaa000009, 0xe59f1164, 0xe59f215c, 0xe5922000, 0xe0810102, 0xfb000f11, 0xe59f014c, 0xe5900000, 
+    0xe2800002, 0xe59f1140, 0xe5810000, 0xe59f0128, 0xe1d000b0, 0xe3500014, 0xda00000c, 0xe3a02103, 
+    0xe3a01081, 0xe3a00010, 0xfbffe808, 0xe3a03000, 0xe1a02003, 0xe3a01001, 0xe59f0114, 0xfb0002a6, 
+    0xe3a00000, 0xe59f10f0, 0xe1c100b0, 0xebfff7e6, 0xe3a02103, 0xe3a01082, 0xe3a00010, 0xfbffe7fb, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d500f, 0xe59f00e0, 0xfb000894, 0xe3a02103, 0xe3a0105c, 
+    0xe3a00010, 0xfbffe7f1, 0xe3a02103, 0xe3a0105d, 0xe3a00010, 0xfbffe7ed, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f00ac, 0xfb000886, 0xe3a02103, 0xe3a01062, 0xe3a00010, 0xfbffe7e3, 
+    0xe3a02103, 0xe3a01063, 0xe3a00010, 0xfbffe7df, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0x00038538, 
+    0x000361e4, 0xc1000364, 0xd0020108, 0x0003625c, 0x0003625d, 0x00038540, 0x00038541, 0x00038544, 
+    0x00038a9c, 0xd28fffd2, 0x00036268, 0x00038654, 0xc1000374, 0xc1000394, 0xc10003a4, 0x000362e8, 
+    0x00036296, 0xd00305c4, 0xc10003b4, 0x0003626a, 0x000362e4, 0x00038a5a, 0x000362ec, 0x000362d8, 
+    0xd0030430, 0x0005280c, 0x000362f4, 0x00052800, 0x00050800, 0xd00305cc, 0xc10003c4, 0xc10003d4, 
+    0x4fffe92d, 0x4680b087, 0xe9dd4692, 0x2400b614, 0xf1bae03d, 0xdd010f00, 0xe0002001, 0xf1b82000, 
+    0xdd010f00, 0xe0002102, 0x43482108, 0x0188eb08, 0x0041eb00, 0x49f94420, 0x7010f931, 0xe0232500, 
+    0x2004eb05, 0x0010f936, 0x42884279, 0xeb05dd04, 0xf9362004, 0xe0000010, 0x42b84278, 0xeb05da0d, 
+    0xf9362004, 0x42790010, 0xdd044288, 0x2004eb05, 0x0010f936, 0x4278e002, 0x4638e000, 0xeb05b200, 
+    0xf8262104, 0x1c6d0011, 0xd9d92dff, 0x455c1c64, 0xea4fd3bf, 0xb200204b, 0x21809006, 0xea41980a, 
+    0xea401040, 0x980801ca, 0x0040ea41, 0x0908ea40, 0x48db4649, 0xfe5df7f9, 0x7100f449, 0xf7f948d8, 
+    0x2000fe58, 0xe9cd2301, 0x90043002, 0x90009005, 0x1d1b4bd3, 0x90014632, 0xf0009906, 0xf449fe93, 
+    0x48cf7180, 0xfe45f7f9, 0xe0002400, 0xf5b41c64, 0xd2063f00, 0x01512208, 0xf00048c9, 0x2800fc30, 
+    0xb00bd1f4, 0x8ff0e8bd, 0x5ffce92d, 0x460f4606, 0x46994690, 0xab0de9dd, 0x24009d0c, 0xf8dfe00d, 
+    0xeb0cc304, 0xeb0b2344, 0xeb0a2104, 0xf2402004, 0xf0261200, 0x1c60fac7, 0x42acb204, 0x48b9dbef, 
+    0x4642464b, 0xe9cd4639, 0x46305000, 0xff58f7ff, 0x9ffce8bd, 0x4fffe92d, 0x4680b083, 0xf8dd4615, 
+    0x2000b040, 0xf1b89002, 0xd1040f01, 0x2002b90d, 0x2001e005, 0xb90de003, 0xe0002008, 0x46822002, 
+    0x24002700, 0x49a8e041, 0x2684eb01, 0x929cf8df, 0xb9789811, 0xeb02460a, 0xf2402084, 0xf0271100, 
+    0x4ba1fb5b, 0x2184eb03, 0x0047eb0b, 0x2280230c, 0xfbe7f026, 0x499e2008, 0xe9cd4a9b, 0xeb021000, 
+    0x4b9c2084, 0x99024a9c, 0xfce8f026, 0xf8d0489a, 0x49980200, 0x23086008, 0x46312280, 0xf0264896, 
+    0x2308fbe1, 0x46492280, 0xf0264892, 0x498dfbdb, 0x2344eb01, 0x1200f240, 0x46304649, 0xfa62f026, 
+    0x0080f107, 0x1c60b207, 0x4554b204, 0x4885dbbb, 0xa000e9cd, 0x4640462a, 0x99049b06, 0xfef0f7ff, 
+    0xe8bdb007, 0xe92d8ff0, 0xb0874ff0, 0x460d4604, 0x461f4616, 0xa040f8dd, 0xfa0f0278, 0x2000fb80, 
+    0x00c6ea40, 0x0045ea40, 0x0904ea40, 0x7180f449, 0xf7f94873, 0xf04ffd8e, 0xe0010800, 0x0801f108, 
+    0x3f00f5b8, 0x2208d206, 0x486d0151, 0xfb77f000, 0xd1f32800, 0x7100f449, 0xf7f94869, 0x2000fd7a, 
+    0xe9cd2201, 0x90040202, 0x90009005, 0x4a644653, 0x46591d12, 0x20019001, 0xfdb4f000, 0xe8bdb007, 
+    0xe92d8ff0, 0x46064ff8, 0x4690460f, 0xe9dd461d, 0x485c9a0a, 0x4642462b, 0x90004639, 0xf7ff4630, 
+    0x2400ffb2, 0xeb0ae00d, 0xeb092304, 0xf8df2204, 0xeb0cc154, 0xf2402044, 0xf0261100, 0x1c60fa28, 
+    0x42acb204, 0xe8bddbef, 0xe92d8ff8, 0xb0854fff, 0x46164682, 0x2000469b, 0xf1ba9004, 0xd1040f01, 
+    0x2002b90e, 0x2001e005, 0xb90ee003, 0xe0002008, 0x90032002, 0x90004843, 0x46504632, 0x99069b03, 
+    0xff81f7ff, 0x0900f04f, 0xe0602400, 0xeb01493e, 0xf8df2784, 0x4a3b80f8, 0x2044eb02, 0x463a4643, 
+    0x1100f240, 0xf9f3f026, 0x22802308, 0x4638493a, 0xfb17f026, 0x22802308, 0x46404936, 0xfb11f026, 
+    0x68004834, 0xf8c14934, 0x20000200, 0x60084931, 0x0200f8c1, 0xe0122501, 0xf850482f, 0xf5c50025, 
+    0x4a2d7180, 0x0021f842, 0xf850482a, 0x42400025, 0x7180f5c5, 0xf8424a27, 0x1c680021, 0x2d80b205, 
+    0x2008dbea, 0xe9cd4922, 0x491f1000, 0x2284eb01, 0x48214920, 0xf0269b04, 0x9812fedb, 0xeb0bb948, 
+    0x4b190149, 0x2084eb03, 0x2280230c, 0xfaeaf026, 0x4b15e007, 0x2144eb03, 0x2084eb03, 0xf0262280, 
+    0xf109fa81, 0xfa0f0080, 0x1c60f980, 0x9803b204, 0xdb9b4284, 0xe8bdb009, 0xe92d8ff0, 0x460643f8, 
+    0x480e460f, 0x1806eb00, 0x463c2500, 0xf994e033, 0x28800000, 0x207fd114, 0x0000e015, 0x00038554, 
+    0xd1800100, 0x00054000, 0x00045308, 0x00047308, 0x0002fcd0, 0x00048308, 0x00047b08, 0xd00304a2, 
+    0x0000f994, 0xb2404240, 0x0000f88d, 0x0001f994, 0xd1012880, 0xe002207f, 0x0001f994, 0xb2404240, 
+    0x0001f88d, 0x1000f9bd, 0x0045eb08, 0xfc8cf7f9, 0xb2051c68, 0x2d081ca4, 0xe8bddbc9, 0xb5f883f8, 
+    0x460d4606, 0xeb0048fe, 0x24001706, 0xeb07e01f, 0xf7f90044, 0x9000fc73, 0x0000f99d, 0xd1012880, 
+    0xe002207f, 0x0000f99d, 0xb2404240, 0x0014f805, 0x0001f99d, 0xd1012880, 0xe002207f, 0x0001f99d, 
+    0xb2414240, 0x1c400060, 0x1c605429, 0x2c08b204, 0xbdf8dbdd, 0x2120b510, 0xf02748ea, 0x2400f9cd, 
+    0x49e8e005, 0xf7ffb260, 0x1c60ff88, 0x2c04b204, 0xbd10dbf7, 0x41fce92d, 0xf6404606, 0x48e10100, 
+    0xf9baf027, 0xe01c2500, 0xe0162400, 0xd1042e01, 0x2002b90c, 0x2001e005, 0xb90ce003, 0xe0002008, 
+    0x46072002, 0x230048d7, 0x46294622, 0x7000e9cd, 0xf7ff4630, 0x1c60fd65, 0x2c04b244, 0x1c68dbe6, 
+    0x2d04b245, 0xe8bddbe0, 0xb51081fc, 0xf7ff2000, 0x2001ffd1, 0xffcef7ff, 0xffbcf7ff, 0xb57cbd10, 
+    0x26004605, 0x2200e00c, 0x1c704631, 0x48c5b206, 0x2011f820, 0x1c714630, 0x49c2b20e, 0x5010f821, 
+    0xddf02eff, 0x800548bf, 0xe00b2400, 0x210148bd, 0x461a2300, 0x1000e9cd, 0x2001b261, 0xfd30f7ff, 
+    0xb2041c60, 0xdbf12c04, 0xe92dbd7c, 0xb08f4fff, 0x48b54606, 0xf500900e, 0x900d5080, 0x900c48b3, 
+    0x5b80f500, 0xf5074fb2, 0x900b5080, 0x900a48b1, 0x90032000, 0x4100f240, 0xf027980a, 0xf240f94d, 
+    0x48ad1100, 0xf938f027, 0x3080f44f, 0x600849aa, 0xe0072400, 0x57009810, 0x4aa70281, 0xf8421c60, 
+    0x1c641020, 0xdbf52c10, 0x49a42008, 0x1000e9cd, 0xe9dd48a1, 0x9903320d, 0xfac0f026, 0x1100f240, 
+    0xf027489d, 0xf44ff919, 0x499b3080, 0x24006008, 0x9811e007, 0x02815700, 0x1c604a97, 0x1020f842, 
+    0x2c101c64, 0x2008dbf5, 0x465b4994, 0x1000e9cd, 0x9a0c4891, 0xf0269903, 0x2400faa1, 0x980ce042, 
+    0x0024f850, 0xf851990e, 0x43481024, 0x2024f85b, 0xf851990d, 0xfb021024, 0x90090001, 0xf850980c, 
+    0x980d1024, 0x0024f850, 0xf85b4341, 0x980e2024, 0x0024f850, 0x1010fb02, 0x980c9008, 0x0024f850, 
+    0xf85b4340, 0xf85b1024, 0xfb012024, 0x12000002, 0x98079007, 0x9907b168, 0xf0279809, 0xf847f865, 
+    0xe9dd0024, 0xf0271007, 0x990bf85f, 0x0024f841, 0xf240e007, 0xf8471000, 0x21000024, 0xf840980b, 
+    0x1c641024, 0xdbba2c81, 0xa048f8dd, 0x981ce112, 0xb2401e40, 0xe1059006, 0x78004869, 0xd11b2805, 
+    0x81a0f8df, 0x91a0f8df, 0x0f01f1ba, 0x9806d105, 0x2002b908, 0x2001e006, 0x9806e004, 0x2008b908, 
+    0x2002e000, 0xe9cd9005, 0x46318900, 0xe9dd4650, 0xf7ff3205, 0xe011fdb6, 0x0f01f1ba, 0x485bd106, 
+    0x2846eb00, 0xeb00485a, 0xe0052946, 0xeb004859, 0x48592846, 0x2946eb00, 0x90052001, 0x90042000, 
+    0x9804e059, 0xb20501c0, 0x1015f938, 0x43486838, 0xf8414952, 0xf9390025, 0xf8d71015, 0x43480200, 
+    0xf841494f, 0x24010025, 0xf857e024, 0x19610024, 0x1011f938, 0x990b4348, 0x1024f851, 0xf9391962, 
+    0xfb012012, 0x19610012, 0xf8424a44, 0xf8570021, 0x19610024, 0x1011f939, 0x990b4348, 0x1024f851, 
+    0xf9381962, 0xfb012012, 0x19610002, 0xf8424a3c, 0x1c640021, 0xdbd82c80, 0x78004831, 0xd1162805, 
+    0xe0122400, 0x49351960, 0x0020f851, 0xb2001200, 0xf8281961, 0x19600011, 0xf8514931, 0x12000020, 
+    0x1961b200, 0x0011f829, 0x2c801c64, 0x9804dbea, 0xb2401c40, 0xe9dd9004, 0x42880104, 0x4820dba1, 
+    0x28057800, 0x9805d109, 0xe88d2300, 0x46310301, 0x9a064650, 0xfc68f7ff, 0x4821e060, 0x491f6800, 
+    0x0200f8c1, 0x491e2000, 0xf8c16008, 0x24810200, 0xf5c4e00f, 0x49197080, 0x0020f851, 0x0024f841, 
+    0x7080f5c4, 0xf8514916, 0x42400020, 0x0024f841, 0x2cff1c64, 0x2008dded, 0xe9cd4908, 0xe0211000, 
+    0xd00304a2, 0x00054000, 0x0003cff0, 0x00038ff0, 0x0003aff0, 0x0003eff0, 0x00045308, 0x0002fcd0, 
+    0x00038b1c, 0x00044308, 0x00044b08, 0x0004a648, 0x0004ae48, 0x0004b648, 0x0004be48, 0x00047b08, 
+    0x00048308, 0x49184a17, 0x9b034818, 0xfc50f026, 0x2280230c, 0x990a4813, 0xf864f026, 0x980a2180, 
+    0x7080f500, 0xffc8f026, 0x980a2100, 0x460a460b, 0x0100e9cd, 0x46504631, 0xfc2cf7ff, 0x1e409806, 
+    0x9006b240, 0x28009806, 0xaef6f6bf, 0x0001f10a, 0xfa80fa4f, 0x0f01f1ba, 0xaee9f77f, 0xe8bdb013, 
+    0x00008ff0, 0x00045308, 0x00048308, 0x00047b08, 0x41f0e92d, 0x460c4680, 0x461e4615, 0xf7f94640, 
+    0x4607fa13, 0x0004ea27, 0xf105fa06, 0xea404021, 0x46390701, 0xf7f94640, 0xe8bdfa0c, 0xe92d81f0, 
+    0x460741f0, 0x4615460c, 0xf7f94638, 0x4606f9fd, 0x0004ea06, 0xf605fa20, 0xe8bd4630, 0xe92d81f0, 
+    0x468041f0, 0x4615460c, 0x4640461e, 0xf9f6f7f9, 0xea27b287, 0xfa060004, 0x4021f105, 0xb2874308, 
+    0x4640b239, 0xf9f0f7f9, 0x81f0e8bd, 0x41f0e92d, 0x460c4607, 0x46384615, 0xf9e0f7f9, 0xea06b286, 
+    0xfa400004, 0x4630f605, 0x81f0e8bd, 0x47f0e92d, 0x460e4604, 0xf884fa1f, 0x70fff64f, 0x4924ea00, 
+    0x0a00f04f, 0xfa0f2500, 0x4857f188, 0xf9ccf7f9, 0xf189fa0f, 0x1c804854, 0xf9c6f7f9, 0x4852b231, 
+    0xf7f91d00, 0x2100f9c1, 0x1d80484f, 0xf9bcf7f9, 0xb2abe02e, 0x21f02204, 0xf7ff484c, 0x1c68ffb0, 
+    0x2d0fb245, 0x2500dd00, 0x22022301, 0x4846210c, 0xf7ff1f00, 0x2301ffa4, 0x46192200, 0x1f004842, 
+    0xff9df7ff, 0xe00b2700, 0x21012200, 0x1f00483e, 0xffacf7ff, 0xf04fb910, 0xe0030a01, 0xb2071c78, 
+    0xdbf12f04, 0x2100bf00, 0x1f004837, 0xf98cf7f9, 0x0f00f1ba, 0xe8bdd0cd, 0xe92d87f0, 0x460447f0, 
+    0xf64fb2a7, 0xea0070ff, 0xf04f4824, 0x25000900, 0x482db239, 0xf978f7f9, 0xf188fa0f, 0x1c80482a, 
+    0xf972f7f9, 0xb2abe02e, 0x210f2200, 0xf7ff4827, 0x1c68ff66, 0x2d0fb245, 0x2500dd00, 0x22022301, 
+    0x4821210c, 0xf7ff1f00, 0x2301ff5a, 0x2102461a, 0x1f00481d, 0xff53f7ff, 0xe00b2600, 0x21022201, 
+    0x1f004819, 0xff62f7ff, 0xf04fb910, 0xe0030901, 0xb2061c70, 0xdbf12e04, 0x2100bf00, 0x1f004812, 
+    0xf942f7f9, 0x0f00f1b9, 0x480fd0cd, 0xf7f91d00, 0xb280f935, 0x87f0e8bd, 0x41f0e92d, 0x460c4680, 
+    0x461e4615, 0xf7ff4640, 0x4607ffa8, 0x0004ea27, 0xf105fa06, 0x43084021, 0x4639b287, 0xf7ff4640, 
+    0xe8bdff45, 0x000081f0, 0xd03d1004, 0xd03c80c0, 0x41f0e92d, 0x460d4604, 0xea4048a8, 0xea405085, 
+    0x46300644, 0xf90af7f9, 0x48a54607, 0xf906f7f9, 0xe8bd4638, 0xe92d81f0, 0x460441f0, 0x4e9f460d, 
+    0xf64f3630, 0xea0571f8, 0x43200001, 0x4639b207, 0xf7f94630, 0x489af8f9, 0xf8f0f7f9, 0x81f0e8bd, 
+    0x41f0e92d, 0x4d954604, 0x20073530, 0x3004eb00, 0x4631b206, 0xf7f94628, 0x4628f8e7, 0xf8def7f9, 
+    0x488f4607, 0xf8daf7f9, 0xe8bd4638, 0xe92d81f0, 0x460741f0, 0x4615460c, 0x4638461e, 0xffe0f7ff, 
+    0xfa0643a0, 0x4021f105, 0xfa1f4308, 0x4641f880, 0xf7ff4638, 0xe8bdffc0, 0xe92d81f0, 0x460441f0, 
+    0x4e7e460d, 0xf2483638, 0xea400000, 0xf3c52084, 0x43080109, 0x4639b207, 0xf7f94630, 0x4878f8b5, 
+    0xf8acf7f9, 0x81f0e8bd, 0x41f0e92d, 0x4d734604, 0x02a03538, 0x4631b206, 0xf7f94628, 0x4628f8a5, 
+    0xf89cf7f9, 0x486e4607, 0xf898f7f9, 0xe8bd4638, 0xe92d81f0, 0x460741f0, 0x4615460c, 0x4638461e, 
+    0xffe2f7ff, 0xfa0643a0, 0x4021f105, 0xfa1f4308, 0x4641f880, 0xf7ff4638, 0xe8bdffc0, 0xe92d81f0, 
+    0x460441f0, 0x4e5d460d, 0xf444362e, 0x46396770, 0xf7f94630, 0x1f36f879, 0x4630b229, 0xf874f7f9, 
+    0xf7f94857, 0xe8bdf86b, 0xe92d81f0, 0x460541f0, 0x4852460c, 0x5084ea40, 0x062ef040, 0x6770f445, 
+    0x46304639, 0xf860f7f9, 0xea40484c, 0xf0405084, 0x4630062a, 0xf852f7f9, 0x48494680, 0xf84ef7f9, 
+    0xe8bd4640, 0xe92d81f0, 0x460741f0, 0x4615460c, 0x2101461e, 0xf7ff4638, 0x43a0ffd8, 0xf105fa06, 
+    0x43084021, 0xf880fa1f, 0x46384641, 0xffb7f7ff, 0x81f0e8bd, 0x41f0e92d, 0x460d4604, 0x461f4616, 
+    0xf7ff2000, 0x4680ff3d, 0xf088fa1f, 0x6140f440, 0xf7ff2000, 0x07a0ff20, 0xf0050c40, 0xea40020f, 
+    0xea402002, 0x482d0106, 0xf7f9302e, 0xb239f81d, 0x302a482a, 0xf818f7f9, 0xf188fa1f, 0xf7ff2000, 
+    0x4827ff0a, 0xf80af7f9, 0x81f0e8bd, 0x41f0e92d, 0x460d4604, 0x20004616, 0xff12f7ff, 0xb2b84607, 
+    0x6140f440, 0xf7ff2000, 0x07a0fef6, 0xf0050c40, 0xea40020f, 0xea402002, 0x48180106, 0xf7f8302e, 
+    0x4816fff3, 0xf7f8302a, 0x4680ffe9, 0x2000b2b9, 0xfee1f7ff, 0xf7f84812, 0x4640ffe1, 0x81f0e8bd, 
+    0x47f0e92d, 0x460f4606, 0x461c4690, 0x9a08e9dd, 0x46394642, 0xf7ff4630, 0xb285ffc9, 0x0004ea25, 
+    0xf109fa0a, 0x43084021, 0x462bb285, 0x46394642, 0xf7ff4630, 0xe8bdff8f, 0x000087f0, 0xd28fffc0, 
+    0xd03c824a, 0x5ff0e92d, 0x4615460c, 0xaf0a461e, 0x0f80e897, 0x461a2301, 0x48592102, 0xfdaff7ff, 
+    0x20042101, 0xf830f001, 0xdd102c40, 0x0040f004, 0x2310b968, 0xf6432208, 0x48527100, 0xfd78f7ff, 
+    0x22002310, 0x484f213f, 0xfd72f7ff, 0x2c1fe045, 0xf004dd10, 0xb9680020, 0x22082310, 0x7100f643, 
+    0xf7ff4848, 0x2310fd65, 0x213f2200, 0xf7ff4845, 0xe032fd5f, 0xdd102c0f, 0x0010f004, 0x2304b968, 
+    0xf6432208, 0x483f7100, 0xfd52f7ff, 0x22002304, 0x483c213f, 0xfd4cf7ff, 0x2c07e01f, 0xf004dd10, 
+    0xb9680008, 0x22082302, 0x7100f643, 0xf7ff4835, 0x2302fd3f, 0x213f2200, 0xf7ff4832, 0xe00cfd39, 
+    0x22082301, 0x7100f643, 0xf7ff482e, 0x2301fd31, 0x213f2200, 0xf7ff482b, 0x463bfd2b, 0x21042202, 
+    0x1d004828, 0xfd24f7ff, 0x2201464b, 0x48252102, 0xf7ff1d00, 0x465bfd1d, 0x21012200, 0x1d004821, 
+    0xfd16f7ff, 0x22024643, 0x481e2104, 0xf7ff3014, 0x4653fd0f, 0x21022201, 0x3014481a, 0xfd08f7ff, 
+    0x21012200, 0x30144817, 0xf7ff9b0f, 0x4623fd01, 0xf64f2200, 0x481371ff, 0xf7ff1f00, 0x4629fcf9, 
+    0x30084810, 0xff15f7f8, 0x480e4631, 0xf7f83018, 0x2301ff10, 0x46192200, 0x4040f04f, 0xfce8f7ff, 
+    0x4808bf00, 0xf7f83808, 0x2801feff, 0x2300d1f9, 0x21022201, 0xf7ff4802, 0xe8bdfd02, 0x00009ff0, 
+    0xd003529a, 0xc000000c, 0x2200b510, 0x31fff240, 0xf7ff489c, 0xb200fce4, 0xb510bd10, 0xf7ff4604, 
+    0x4999fff3, 0xe0038008, 0xffeef7ff, 0x80084996, 0x88004895, 0xdcf742a0, 0xb570bd10, 0x460d4604, 
+    0xea4001e8, 0xf04f1104, 0xf7f84048, 0xbd70fed2, 0x4604b570, 0x01e8460d, 0x1104ea40, 0x38104889, 
+    0xfec7f7f8, 0xb570bd70, 0x460d4604, 0xea4001e8, 0x48841104, 0xf7f8380c, 0xbd70febc, 0x47f0e92d, 
+    0x460d4604, 0x461f4616, 0x9a09e9dd, 0x8020f8dd, 0x0001f004, 0xea022202, 0x43100245, 0xea022204, 
+    0x43100286, 0xea022208, 0x431002c7, 0xea022210, 0x43101208, 0xea022220, 0x43101249, 0xea0222c0, 
+    0xea40128a, 0x486f0102, 0xf7f83808, 0xe8bdfe92, 0xb51087f0, 0x46214604, 0x1f00486a, 0xfe89f7f8, 
+    0xb510bd10, 0x46214604, 0xf7f84866, 0xbd10fe82, 0x41f0e92d, 0x460d4604, 0x461f4616, 0xea4001b0, 
+    0xea401007, 0xea400084, 0x485e0105, 0xfe71f7f8, 0x81f0e8bd, 0x4604b510, 0x485a4621, 0xf7f81d00, 
+    0xbd10fe68, 0x4604b510, 0xea002006, 0xf0400044, 0x48540101, 0xf7f83008, 0xbd10fe5c, 0x4604b510, 
+    0x21012200, 0x3008484f, 0xfc49f7ff, 0x4620b128, 0xff5ff000, 0x2001b108, 0x2000bd10, 0xb510e7fc, 
+    0x46234604, 0x21082203, 0x30104846, 0xfc20f7ff, 0x22022301, 0x48432104, 0xf7ff3010, 0xbd10fc19, 
+    0x2300b510, 0x21042202, 0x3010483e, 0xfc10f7ff, 0xb50ebd10, 0x23012000, 0x46014602, 0xf0049000, 
+    0x2000f8d5, 0xffdbf7ff, 0x78004838, 0x4938b240, 0xb2497809, 0x78124a37, 0xe9cdb252, 0x90022100, 
+    0x78004835, 0x4835b243, 0xb2427800, 0x78004834, 0x4834b241, 0xb2407800, 0xff50f7ff, 0x48322100, 
+    0xb2407800, 0xff29f7ff, 0x48302100, 0xb2407800, 0xff2ef7ff, 0x482e2100, 0xb2407800, 0xff33f7ff, 
+    0xf7ff2000, 0x2100ff66, 0x3008481e, 0xfdf1f7f8, 0xf7ff2001, 0x481dffa4, 0xb2417800, 0x7800481c, 
+    0x4a1cb240, 0xb2527812, 0x2000e9cd, 0x481a9102, 0xb2437800, 0x78004819, 0x4819b242, 0xb2417800, 
+    0x78004818, 0xf7ffb240, 0x2100ff19, 0x78004816, 0xf7ffb240, 0x2100fef2, 0x78004814, 0xf7ffb240, 
+    0x2100fef7, 0x78004812, 0xf7ffb240, 0x2000fefc, 0xff2ff7ff, 0x48032100, 0xf7f83008, 0xf7fffdba, 
+    0xbd0eff7f, 0xc8000014, 0x0003621a, 0x000361ef, 0x000361f5, 0x000361f7, 0x00036213, 0x00036210, 
+    0x00036215, 0x00036217, 0x000361fd, 0x000361fb, 0x000361f9, 0xf240b510, 0x48f72112, 0xfda4f7f8, 
+    0x011cf647, 0x1c8048f4, 0xfd9ef7f8, 0x2173f240, 0xf7f848f2, 0x2102fd99, 0x1d0048ef, 0xfd94f7f8, 
+    0x0100f243, 0x300848ec, 0xfd8ef7f8, 0x48ea2120, 0xf7f8300c, 0x2100fd89, 0xf7f848e9, 0xf240fd85, 
+    0x48e711fe, 0xf7f81c80, 0x2300fd7f, 0x0291220c, 0x381648e3, 0xfb73f7ff, 0x780048e2, 0xea401e40, 
+    0xb2012000, 0x300e48dc, 0xfd6ef7f8, 0x3103f240, 0x301048d9, 0xfd68f7f8, 0x017ff06f, 0x380848d7, 
+    0xfd62f7f8, 0x48d549d8, 0xf7f81f80, 0x2110fd5d, 0x1f8048d1, 0xfd58f7f8, 0x48cf49d4, 0xf7f81f00, 
+    0x48d3fd53, 0xf3c07800, 0xf0801000, 0x22090301, 0x2100f240, 0xf7ff48cf, 0x48cdfb42, 0xf3c07800, 
+    0xf0801000, 0x22080301, 0x48ca0151, 0xfb37f7ff, 0x22042300, 0x48c72110, 0xfb31f7ff, 0x461a2300, 
+    0x48c42101, 0xfb2bf7ff, 0x22012300, 0x48c12102, 0xfb25f7ff, 0x22022300, 0x48be2104, 0xfb1ff7ff, 
+    0x22032300, 0x48bb2108, 0xfb19f7ff, 0x780048b8, 0x00c0f3c0, 0xff32f002, 0x4128f241, 0x1d8048b5, 
+    0xfd12f7f8, 0x4168f245, 0x300848b2, 0xfd0cf7f8, 0x0120f244, 0x1e8048a8, 0xfd06f7f8, 0x48ad49ae, 
+    0xf7f83010, 0x2100fd01, 0x301248aa, 0xfcfcf7f8, 0x780048a7, 0x0040f3c0, 0xff3ef002, 0x880048a7, 
+    0x489db201, 0xf7f83020, 0x48a5fcef, 0xb2018800, 0x30224899, 0xfce8f7f8, 0x4898210c, 0xf7f830a4, 
+    0x2303fce3, 0xf6412208, 0x48947100, 0xf7ff1c80, 0x2304fad6, 0x211f2200, 0x1c804890, 0xfacff7ff, 
+    0x22082305, 0x7100f641, 0x30a0488c, 0xfac7f7ff, 0x2200230a, 0x4889211f, 0xf7ff30a0, 0x2301fac0, 
+    0x21702204, 0x30a24885, 0xfab9f7ff, 0x461a2300, 0x48822107, 0xf7ff30a2, 0x2100fab2, 0x38a44885, 
+    0xfcb2f7f8, 0x48832100, 0xf7f838a2, 0x2102fcad, 0x38b64880, 0xfca8f7f8, 0x487e2100, 0xf7f83878, 
+    0x4880fca3, 0xb2018800, 0x30244873, 0xfc9cf7f8, 0x21082203, 0xf7ff487c, 0x2801faa9, 0x2203d147, 
+    0x48792108, 0xf7ff1c80, 0x2801faa1, 0x2301d13f, 0x2102461a, 0x1f804868, 0xfa81f7ff, 0x49732001, 
+    0x48737008, 0x28027800, 0x486dd120, 0x496b8800, 0xeb008809, 0x496b4001, 0x42888809, 0x4868dc0f, 
+    0x49668800, 0xeb007809, 0x1e404001, 0x80084965, 0x88004608, 0x4858b201, 0xf7f83024, 0xf240fc65, 
+    0x48551104, 0xf7f8301c, 0xe01ffc5f, 0x78004860, 0xd1062803, 0x1100f240, 0x301c484f, 0xfc54f7f8, 
+    0x2100e014, 0x301c484c, 0xfc4ef7f8, 0x2300e00e, 0x21022201, 0x1f804848, 0xfa41f7ff, 0x48462100, 
+    0xf7f8301c, 0x2000fc41, 0x70084950, 0x49512000, 0x484f8008, 0x49507800, 0x211b7008, 0x3828483e, 
+    0xfc32f7f8, 0x4380f240, 0x494c2210, 0xf7ff484c, 0xf240f9ff, 0x22004380, 0x71fff64f, 0xf7ff4848, 
+    0x4948f9f7, 0x1d004846, 0xfc13f7f8, 0x220e2300, 0x48384945, 0xf7ff3016, 0x2303fa12, 0xf6432208, 
+    0x48347100, 0xf7ff3016, 0x2300fa0a, 0x21c02206, 0x30164830, 0xfa03f7ff, 0x22002303, 0x482d213f, 
+    0xf7ff3016, 0x2302f9fc, 0xf04f2218, 0x483461e0, 0xf7ff383c, 0x2308f9cd, 0xf641461a, 0x481f7100, 
+    0xf7ff30a6, 0x2302f9ec, 0x21302204, 0x30a6481b, 0xf9e5f7ff, 0x22002307, 0x4818210f, 0xf7ff30a6, 
+    0xf640f9de, 0x481b710f, 0xf7f83014, 0xf244fbdd, 0x4813310f, 0xf7f81e80, 0xf241fbd7, 0x48151111, 
+    0xf7f8300a, 0xbd10fbd1, 0x4605b570, 0xf24f460c, 0xea401060, 0xb2010044, 0x380a4808, 0xfbc4f7f8, 
+    0x4100f240, 0x1d004805, 0xfbbef7f8, 0x20002101, 0xfeb1f002, 0x0000bd70, 0xd00350f8, 0xd003050a, 
+    0xd0030818, 0x00036327, 0xfffffe70, 0xffffaa0a, 0x00036326, 0xd00352a0, 0xffff8888, 0x0003632a, 
+    0x0003632c, 0x0003632e, 0xd28e0078, 0x00036328, 0x00036324, 0x00036330, 0x00036332, 0xffff0000, 
+    0xd1800040, 0x00080005, 0xffffc000, 0x4605b570, 0xb995460c, 0x780048fe, 0x1000f3c0, 0x0001f080, 
+    0xea422200, 0xea401000, 0xea400044, 0xea400084, 0x48f801c4, 0xfb78f7f8, 0x48f5e00e, 0xf3c07800, 
+    0xf0801000, 0xea440001, 0xea401000, 0xea400044, 0x48f001c4, 0xfb68f7f8, 0xe92dbd70, 0xb08f4ff0, 
+    0x900b2000, 0x4dec900a, 0x48e94fec, 0xf3c07800, 0x90060080, 0x780048ea, 0x48eab948, 0x49ea7800, 
+    0x49ea7008, 0x4aeb48ea, 0x1000e9c2, 0x48e5e008, 0x49e57880, 0x49e87008, 0x4ae648e8, 0x1000e9c2, 
+    0x780048df, 0xf7ff9906, 0x2000ffb1, 0x4602463b, 0x48dd9000, 0xb2417800, 0xf7fe2001, 0x48e0fde6, 
+    0xf9dff002, 0xf00248df, 0x48ddf910, 0x780949d6, 0x0011f830, 0x800849dc, 0x49d348da, 0xf8307809, 
+    0x49da0011, 0x24018008, 0xf937e015, 0x28000014, 0x4601db01, 0x4241e000, 0x42919a0b, 0xf937dd09, 
+    0x28000014, 0x4601db01, 0x4241e000, 0x910bb209, 0x1c60940a, 0x2c80b204, 0x980adbe7, 0xfa0f1f80, 
+    0xf240fb80, 0xe03a1400, 0x7080f5a4, 0x2000b206, 0x0026f845, 0xe02c4680, 0x000beb08, 0xfa80fa0f, 
+    0x0008eba4, 0x0245f3c0, 0x48ba9209, 0x1000e9d0, 0xe9cd9a09, 0x4608010c, 0xf024990c, 0x2301f96d, 
+    0x21004018, 0x40494058, 0xd1074308, 0x0026f855, 0x101af937, 0xf8451a40, 0xe0060026, 0x0026f855, 
+    0x101af937, 0xf8454408, 0xf1080026, 0xfa0f0001, 0xf1cbf880, 0x4540007f, 0x1c60dace, 0xf5b4b204, 
+    0xdbc17fc0, 0x90072000, 0xe02b2400, 0x0024f855, 0xfa2af027, 0xf0279001, 0x2200f89b, 0xe9cd4ba4, 
+    0xf0260102, 0xe9cdfc13, 0xf0260104, 0x4681fda3, 0x0f7ff1b9, 0x207fdb01, 0x4648e000, 0x98089008, 
+    0x0f80f110, 0xf06fdc02, 0xe000007f, 0xb2409808, 0x0024f845, 0x1024f855, 0xfb019807, 0x90070009, 
+    0xb2041c60, 0xdbd12c80, 0x98074992, 0x24006008, 0x0062e011, 0xf8551c52, 0x00623022, 0x2022f835, 
+    0x221ff363, 0x4a8cb211, 0xfb032302, 0xf7f82004, 0x1c60fa7b, 0x2c40b204, 0xb00fdbeb, 0x8ff0e8bd, 
+    0x4ff0e92d, 0x4885b087, 0x28007800, 0x4881d174, 0xb000f8d0, 0xf002487a, 0x487af914, 0xf845f002, 
+    0x49714877, 0xf8307809, 0x497d0011, 0x48758008, 0x7809496d, 0x0011f830, 0x8008497a, 0xf0274658, 
+    0x4979f9db, 0xf0279000, 0x9001f9eb, 0xf830f027, 0x22004607, 0xf0264b75, 0x2200fe01, 0xe9cd4b74, 
+    0xf0260102, 0xe9cdfba3, 0xf0260104, 0x1040fd33, 0x4970b200, 0x46588008, 0xf9bef027, 0x4180f04f, 
+    0xf0279000, 0x9001f9cd, 0xf812f027, 0x22004607, 0xf0264b66, 0x2200fde3, 0xe9cd4b65, 0xf0260102, 
+    0xe9cdfb85, 0xf0260104, 0x1040fd15, 0x4962b200, 0xf0028008, 0xf5b0fd31, 0xda077fc8, 0x6800485f, 
+    0xd8032811, 0x1090f240, 0xfd1ef002, 0x0a00f04f, 0x495b2000, 0x25007008, 0x4628e015, 0xfd6ef002, 
+    0x48414604, 0x42857800, 0x46a2d100, 0x78004854, 0xdd024284, 0xe002b2e0, 0x4851e026, 0x49507800, 
+    0x1c687008, 0x2d04b2c5, 0xf10adbe7, 0x10440001, 0x705ef641, 0xb2061b00, 0x17c11ef0, 0x6191eb00, 
+    0xeba01189, 0xfa0f1181, 0xfa1ff981, 0x2200f389, 0x4839213f, 0xf7fe380a, 0x2303ffd2, 0xf247220c, 
+    0x48400100, 0xffcbf7fe, 0x8800483b, 0xb2014240, 0x380e4831, 0xf9c8f7f8, 0x88004836, 0xb2014240, 
+    0x380c482d, 0xf9c0f7f8, 0x88004832, 0xb2014240, 0x30904829, 0xf9b8f7f8, 0x78004833, 0xf647b920, 
+    0xf00270ff, 0xe009fcc1, 0xf9b1492a, 0xeb011000, 0x00890141, 0x00cff3c1, 0xfcb6f002, 0x381c481e, 
+    0xf99cf7f8, 0x7fc8f5b0, 0x4824da07, 0x28116800, 0xf240d803, 0xf0021090, 0x2300fca7, 0xf240220a, 
+    0x48204100, 0xf7fe380a, 0x2101ff8a, 0xe03d2008, 0x00036326, 0xd00352ac, 0x0004a648, 0x0004ae48, 
+    0x000361ee, 0x00036240, 0x00038578, 0xaf77a42e, 0xca4fa6c1, 0x00038590, 0x8365f253, 0x7425eef5, 
+    0x0003629e, 0x000362a6, 0x00038570, 0x00038572, 0x40400000, 0x0003857c, 0xd0030510, 0x00038b1c, 
+    0x00038574, 0x00038576, 0x40e00000, 0x40220000, 0x40b00000, 0x00038598, 0x0003859a, 0x000361dc, 
+    0x00036341, 0xd0035100, 0x00038b1e, 0xfafff002, 0xf0022000, 0xf002fdf1, 0x2000fab2, 0x800849c0, 
+    0x780048c0, 0xd0032802, 0x780048be, 0xd1052803, 0x22012300, 0x48bc2102, 0xff31f7fe, 0x780048bb, 
+    0xe8bdb007, 0xb5108ff0, 0x220a2301, 0x48b60299, 0xf7fe381e, 0x2101ff24, 0xf0000308, 0x2300f9a5, 
+    0xf240220a, 0x48b04100, 0xf7fe381e, 0x2101ff18, 0xf0000308, 0x2300f999, 0x21022201, 0x382248aa, 
+    0xff0df7fe, 0x283cbd10, 0xf64edd07, 0x4aa82160, 0x49a86011, 0x60114aa8, 0xf24ce006, 0x4aa43150, 
+    0x49a66011, 0x60114aa4, 0xb57c4770, 0x780048a4, 0x0680f3c0, 0x49a448a3, 0x22002302, 0x1000e9cd, 
+    0x780048a2, 0x2001b241, 0xfb7bf7fe, 0x24762500, 0x489de00f, 0x0014f830, 0xf000fb10, 0xf8314999, 
+    0x4a981014, 0x2014f832, 0x0002fb11, 0x1c604405, 0x2c7fb284, 0x4896dded, 0x78094994, 0x5021f840, 
+    0xf0014894, 0x4994fe5d, 0x78124a90, 0x1022f851, 0x28001b48, 0x4601db01, 0x4241e000, 0x4b8b4a8e, 
+    0xf852781b, 0xebb12023, 0xdb210fa2, 0x4a87498a, 0xf8517812, 0x1b481022, 0xdb012800, 0xe0004601, 
+    0x4a854241, 0x781b4b81, 0x2023f852, 0x0f62ebb1, 0x4980da08, 0x78124a7d, 0x1022f851, 0x12f6f64b, 
+    0xd9264291, 0x497d2000, 0x78124a78, 0xe0205488, 0x4a764979, 0xf8517812, 0x1b481022, 0xdb012800, 
+    0xe0004601, 0x4a744241, 0x781b4b70, 0x2023f852, 0x0fe2ebb1, 0x496fdb08, 0x78124a6c, 0x1022f851, 
+    0x52bdf24a, 0xd2044291, 0x496c2001, 0x78124a67, 0x486b5488, 0xb3107800, 0x78004868, 0x4867b300, 
+    0xb1e87840, 0x78804865, 0x4864b1d0, 0xb1b878c0, 0x7800485b, 0x0001f000, 0x230fb130, 0x46192200, 
+    0xf7fe4860, 0xe005fe5c, 0x461a2300, 0x485d210f, 0xfe55f7fe, 0x485c4631, 0xf7ff7800, 0xe00afcc7, 
+    0x461a2300, 0x4857210f, 0xfe49f7fe, 0x48562100, 0xf7ff7800, 0x484dfcbb, 0x1c407800, 0x494bb2c0, 
+    0x28047008, 0x2000db01, 0xbd7c7008, 0x2500b57c, 0x4844e026, 0x23024944, 0xe9cd2200, 0xb2691000, 
+    0xf7fe2001, 0x2600fabe, 0xe00f2476, 0xf830483e, 0xfb100014, 0x493bf000, 0x1014f831, 0xf8324a39, 
+    0xfb112014, 0x44060002, 0xb2841c60, 0xdded2c7f, 0xf8404839, 0x48366025, 0x6025f840, 0xb2c51c68, 
+    0xdbd62d04, 0xe92dbd7c, 0x20285ffc, 0x48379000, 0x28047800, 0x2013d102, 0xe0059000, 0x78004833, 
+    0xd1012805, 0x9000201c, 0x78004831, 0xea4f1c40, 0xf6410960, 0xeba07061, 0x22000509, 0x71fff641, 
+    0x38ca4819, 0xfe02f7fe, 0x99003008, 0xfa0f4408, 0xebaafa80, 0xfa0f0005, 0xf50bfb80, 0xb2045000, 
+    0x17e14620, 0x6191eb04, 0xeba41189, 0xb90e1681, 0xe0012000, 0x0040f1c6, 0x9001b200, 0x1a289801, 
+    0xf5c0380a, 0xfa0f5000, 0x4647f880, 0x2200b2bb, 0x71fff641, 0x38344804, 0xfdc1f7fe, 0x9ffce8bd, 
+    0x00038588, 0x00036324, 0xd0035114, 0x00038578, 0x00036338, 0x00015f90, 0x0003633c, 0x00017318, 
+    0x00036326, 0x00044b08, 0x00044308, 0x0003859c, 0x00043038, 0x00038fe0, 0x00043028, 0x0003859d, 
+    0x000362cd, 0xd00352a0, 0x000361ee, 0x0003626a, 0x00036341, 0xd20c2806, 0xf000e8df, 0x0c0d0e0b, 
+    0x21020703, 0x80114a6a, 0x2101e00a, 0x80114a68, 0xbf00e006, 0xbf00bf00, 0x4a652100, 0xbf008011, 
+    0x4770bf00, 0x47701e40, 0xb112460a, 0x781b4b60, 0x46014098, 0x1e49e000, 0xd1fc2900, 0xb5704770, 
+    0x460d4604, 0x2201e00f, 0x485a2102, 0xfd57f7fe, 0xd0072801, 0x21012200, 0x1d004856, 0xfd4ff7fe, 
+    0xd1002801, 0x4853e006, 0xf7f7300c, 0x1a20ff4d, 0xd3e842a8, 0xbd70bf00, 0x4604b570, 0x484e460d, 
+    0xbb186800, 0xf7f7484d, 0xb160ff49, 0x7800484c, 0xd1022801, 0x7010f242, 0x2000e000, 0xb2014420, 
+    0xf7f74846, 0xbf00ff41, 0xf7f74844, 0x2800ff37, 0x4843d1fa, 0x28017800, 0xf242d102, 0xe0007010, 
+    0x44282000, 0x483db201, 0xff2ef7f7, 0xb570bd70, 0x460d4604, 0x39204937, 0x1004eb01, 0xf7f72100, 
+    0x2201ff18, 0x0185eb02, 0x3a204a32, 0x1004eb02, 0xff0ff7f7, 0xb510bd70, 0x492e4604, 0xeb013920, 
+    0x21021004, 0xff05f7f7, 0xb510bd10, 0x49294604, 0xeb013920, 0xf7f71004, 0xf3c0fef7, 0xbd100040, 
+    0x4604b510, 0x39144923, 0x1004eb01, 0xfeecf7f7, 0xb510bd10, 0x1c604604, 0x2001b908, 0x4620bd10, 
+    0xffeef7ff, 0x4620b128, 0xffdff7ff, 0x2001b908, 0x2000e7f4, 0x481be7f2, 0x47706800, 0x68004819, 
+    0x49181c40, 0x47706008, 0x4604b570, 0x4615460e, 0x39204910, 0x1004eb01, 0xf7f72102, 0x490dfeca, 
+    0xeb013918, 0x46311004, 0xfec3f7f7, 0x39204909, 0x1004eb01, 0xf7f72100, 0x2201febc, 0x0185eb02, 
+    0x3a204a04, 0x1004eb02, 0xfeb3f7f7, 0x0000bd70, 0x000385a8, 0xc8000120, 0x000362f4, 0xd03c80b8, 
+    0x000361ee, 0x000385a4, 0xe7febf00, 0x4604b510, 0xd2082c20, 0xfa002001, 0x4603f104, 0x48feb262, 
+    0xfc76f7fe, 0x3c20e008, 0xfa002001, 0x4603f104, 0x48fab262, 0xfc6cf7fe, 0xb570bd10, 0x460d4604, 
+    0xeb0149f7, 0x46291004, 0xfe83f7f7, 0xb510bd70, 0x2c204604, 0x2001da09, 0xf104fa00, 0xb2622300, 
+    0x4041f04f, 0xfc54f7fe, 0xf1a4e00b, 0xb2c40020, 0xfa002001, 0x2300f104, 0x48e8b262, 0xf7fe3808, 
+    0xbd10fc47, 0x4604b510, 0xda092c20, 0xfa002001, 0x4603f104, 0xf04fb262, 0xf7fe4041, 0xe00bfc39, 
+    0x0020f1a4, 0x2001b2c4, 0xf104fa00, 0xb2624603, 0x380848da, 0xfc2cf7fe, 0xb570bd10, 0x2c204604, 
+    0x2001da09, 0xf104fa00, 0x48d3b262, 0xf7fe301c, 0x4605fc36, 0xf1a4e00b, 0xb2c40020, 0xfa002001, 
+    0xb262f104, 0x300c48cd, 0xfc29f7fe, 0x46284605, 0xe92dbd70, 0x460441f0, 0x4616460d, 0xf8dd461f, 
+    0x49c78018, 0xeb013908, 0x46331004, 0x21302204, 0xfbfef7fe, 0x390849c2, 0x1004eb01, 0x2203462b, 
+    0xf7fe2108, 0x49befbf5, 0xeb013908, 0x463b1004, 0x21042202, 0xfbecf7fe, 0x390849b9, 0x1004eb01, 
+    0x22004643, 0xf7fe2103, 0xe8bdfbe3, 0xb57081f0, 0xb9554605, 0x1f244cb2, 0x4620e003, 0xfdf4f7f7, 
+    0x48b03410, 0xd9f84284, 0x4628e002, 0xfdecf7f7, 0xb510bd70, 0x2c204604, 0x2001da24, 0xf104fa00, 
+    0xb2624603, 0x302848a4, 0xfbc2f7fe, 0xfa002001, 0x4603f104, 0x48a0b262, 0xf7fe302c, 0x2001fbb9, 
+    0xf104fa00, 0xb2622300, 0x3028489b, 0xfbb0f7fe, 0xfa002001, 0x2300f104, 0x4897b262, 0xf7fe302c, 
+    0xe026fba7, 0x0020f1a4, 0x2001b2c4, 0xf104fa00, 0xb2624603, 0x30184891, 0xfb9af7fe, 0xfa002001, 
+    0x4603f104, 0x488db262, 0xf7fe301c, 0x2001fb91, 0xf104fa00, 0xb2622300, 0x30184888, 0xfb88f7fe, 
+    0xfa002001, 0x2300f104, 0x4884b262, 0xf7fe301c, 0xbd10fb7f, 0xf04fb510, 0xf04f31ff, 0xf7f74041, 
+    0xf04ffd98, 0x487d31ff, 0xf7f73808, 0xf04ffd92, 0x487931ff, 0xfd8df7f7, 0x31fff04f, 0xf7f74877, 
+    0x4979fd88, 0xf7f74876, 0x4978fd84, 0x30104874, 0xfd7ff7f7, 0x48724976, 0xf7f73020, 0x4975fd7a, 
+    0x3030486f, 0xfd75f7f7, 0x486d4973, 0xf7f73040, 0x4972fd70, 0x3050486a, 0xfd6bf7f7, 0x48684970, 
+    0xf7f73060, 0x496ffd66, 0x30704865, 0xfd61f7f7, 0x4863496d, 0xf7f73080, 0x496cfd5c, 0x30904860, 
+    0xfd57f7f7, 0x485e496a, 0xf7f730a0, 0x4969fd52, 0x30b0485b, 0xfd4df7f7, 0x48594967, 0xf7f730c0, 
+    0x4966fd48, 0x30d04856, 0xfd43f7f7, 0x48544964, 0xf7f730e0, 0x4963fd3e, 0x30f04851, 0xfd39f7f7, 
+    0x21dbf2af, 0xf7f74860, 0xf2affd34, 0x485e21e3, 0xf7f73010, 0xf2affd2e, 0x485b21ef, 0xf7f73020, 
+    0x495afd28, 0x30304858, 0xfd23f7f7, 0x48564958, 0xf7f73040, 0xf2affd1e, 0x4853310f, 0xf7f73050, 
+    0xf2affd18, 0x4850311b, 0xf7f73060, 0x4951fd12, 0x3070484d, 0xfd0df7f7, 0x3133f2af, 0x3080484a, 
+    0xfd07f7f7, 0x313ff2af, 0x30904847, 0xfd01f7f7, 0x48454949, 0xf7f730a0, 0x4948fcfc, 0x30b04842, 
+    0xfcf7f7f7, 0x48404946, 0xf7f730c0, 0xf2affcf2, 0x483d3167, 0xf7f730d0, 0x4942fcec, 0x30e0483a, 
+    0xfce7f7f7, 0x48384940, 0xf7f730f0, 0x493ffce2, 0x38ec4824, 0xfcddf7f7, 0x4822493d, 0xf7f738dc, 
+    0x493cfcd8, 0x38cc481f, 0xfcd3f7f7, 0x481d493a, 0xf7f738bc, 0x4939fcce, 0x38ac481a, 0xfcc9f7f7, 
+    0x48184937, 0xf7f7389c, 0x4936fcc4, 0x388c4815, 0xfcbff7f7, 0x48134934, 0xf7f7387c, 0xf2affcba, 
+    0x481031d7, 0xf7f7386c, 0x4930fcb4, 0x385c480d, 0xfcaff7f7, 0x480b492e, 0xf7f7384c, 0x492dfcaa, 
+    0x383c4808, 0xfca5f7f7, 0x4806492b, 0xf7f7382c, 0x492afca0, 0xe0534803, 0xc1000008, 0xc1000508, 
+    0xc1000108, 0xc10003f4, 0x000047b4, 0x00004a40, 0x00004b74, 0x00004d20, 0x00004ec4, 0x000051d4, 
+    0x0000520c, 0x00005274, 0x000052c0, 0x000052f8, 0x000055d4, 0x0000576c, 0x0000584c, 0x00005864, 
+    0x0000589c, 0x0000593c, 0xc1000208, 0x00005974, 0x0000598c, 0x000059a8, 0x000059e0, 0x00005bd4, 
+    0x00005c44, 0x00005d08, 0x00005d84, 0x00005e24, 0x00005e5c, 0x00005f08, 0x00006034, 0x0000606c, 
+    0x000061c8, 0x000063fc, 0x000065c0, 0x000065f8, 0x00006630, 0x00006668, 0x0000686c, 0x000068a4, 
+    0xf7f7381c, 0xf2affc46, 0x48a941bf, 0xfc41f7f7, 0x41cbf2af, 0x301048a6, 0xfc3bf7f7, 0xb51cbd10, 
+    0xfe98f7ff, 0xf7ff2000, 0xb662fe32, 0x46032000, 0x46012201, 0x20069000, 0xfdfbf7ff, 0xf7ff2006, 
+    0x2000fda6, 0x22014603, 0x90004601, 0xf7ff2007, 0x2007fdf0, 0xfd9bf7ff, 0x46032000, 0x46012201, 
+    0x20149000, 0xfde5f7ff, 0xf7ff2014, 0x2000fd90, 0x22034603, 0x90004601, 0xf7ff2001, 0x2001fdda, 
+    0xfd85f7ff, 0x46032000, 0x46012202, 0x46109000, 0xfdcff7ff, 0xf7ff2002, 0x2000fd95, 0x22034603, 
+    0x90004601, 0xf7ff201e, 0x201efdc4, 0xfd6ff7ff, 0x46032000, 0x46012203, 0x201f9000, 0xfdb9f7ff, 
+    0xf7ff201f, 0x2000fd64, 0x22014603, 0x90004611, 0xf7ff201c, 0x2301fdae, 0x2102461a, 0xf7fe4875, 
+    0xf04ff9de, 0x487331ff, 0xf7f7382a, 0xf04ffbdd, 0x487031ff, 0xf7f7382c, 0x2300fbd7, 0x21042202, 
+    0xf7fe486c, 0xf04ff9cc, 0x486a31ff, 0xf7f7380a, 0xf04ffbcb, 0x486731ff, 0xf7f7380c, 0xf005fbc5, 
+    0xf04ffcb2, 0xf00530ff, 0x2301fc77, 0x46192200, 0xf7fe4860, 0x2000f9b4, 0x22014603, 0x90004611, 
+    0xf7ff2004, 0x2004fd76, 0xfd21f7ff, 0x46032000, 0x46012201, 0x200a9000, 0xfd6bf7ff, 0xf7ff200a, 
+    0x2000fd31, 0x22034603, 0x90004601, 0xf7ff2022, 0x2022fd60, 0xfd0bf7ff, 0x46032000, 0x46012203, 
+    0x20219000, 0xfd55f7ff, 0xf7ff2021, 0x2000fd00, 0x22014603, 0x90004601, 0xf7ff2025, 0x2025fd4a, 
+    0xfcf5f7ff, 0x46032000, 0x46012201, 0x20269000, 0xfd3ff7ff, 0xf7ff2026, 0xf647fcea, 0x483e717f, 
+    0xfb72f7f7, 0x46032000, 0x46012201, 0x20249000, 0xfd2ff7ff, 0xf7ff2024, 0x2000fcda, 0x22014603, 
+    0x90004601, 0xf7ff2009, 0xf04ffd24, 0x483231ff, 0xf7f73814, 0xf04ffb59, 0x482f31ff, 0xf7f73812, 
+    0xf04ffb53, 0x482c31ff, 0xf7f73818, 0x492bfb4d, 0x38164829, 0xfb48f7f7, 0xf7ff2009, 0xf64ffcb8, 
+    0x900070f8, 0x22012300, 0x90012107, 0xf01d2002, 0x2000fbf9, 0x22014603, 0x90004611, 0xf7ff201a, 
+    0x201afcf8, 0xfca3f7ff, 0xf9d5f004, 0x46032000, 0x46112201, 0x202b9000, 0xfcebf7ff, 0xf7ff202b, 
+    0xf021fc96, 0x207ff970, 0xf9acf021, 0x46032000, 0x46112201, 0x200a9000, 0xfcdbf7ff, 0xf7ff200a, 
+    0xf020fca1, 0xf04ff9b2, 0xf02030ff, 0x2000f996, 0x22014603, 0x90004601, 0xf7ff200e, 0x200efcca, 
+    0xfc75f7ff, 0x48044906, 0xf7f73026, 0xbd1cfafd, 0xc10003e8, 0xd0039046, 0xd03c8092, 0xffff8000, 
+    0xffffbbbb, 0x2300b510, 0x21102204, 0xf7fe4817, 0x2301f8bf, 0x21402206, 0xf7fe4814, 0x2300f8b9, 
+    0x21402206, 0xf7fe4811, 0x2301f8b3, 0x21102204, 0xf7fe480e, 0xbd10f8ad, 0x2300b510, 0x21202205, 
+    0xf7fe480a, 0x2301f8a5, 0x21802207, 0xf7fe4807, 0x2300f89f, 0x21802207, 0xf7fe4804, 0x2301f899, 
+    0x21202205, 0xf7fe4801, 0xbd10f893, 0xd1800400, 0x4604b570, 0x4623460d, 0x21f02204, 0xf7fe48fe, 
+    0x462bf887, 0x210f2200, 0xf7fe48fb, 0xbd70f881, 0x41f0e92d, 0x460d4604, 0x461f4616, 0x22144623, 
+    0x0170f44f, 0x380848f4, 0xf872f7fe, 0x2210462b, 0x2170f44f, 0x380848f0, 0xf86af7fe, 0x22044633, 
+    0x48ed21f0, 0xf7fe3808, 0x463bf863, 0x210f2200, 0x380848e9, 0xf85cf7fe, 0x81f0e8bd, 0x41f0e92d, 
+    0x460d4604, 0x461f4616, 0xb26db264, 0xb2461e70, 0xb2471e78, 0x22184623, 0x51f8f04f, 0x381048de, 
+    0xf846f7fe, 0x2210462b, 0x11f8f44f, 0x381048da, 0xf83ef7fe, 0x22084633, 0x7100f641, 0x381048d6, 
+    0xf836f7fe, 0x2200463b, 0x48d3211f, 0xf7fe3810, 0xe8bdf82f, 0xe92d81f0, 0x460747f0, 0x4615460c, 
+    0xe9dd461e, 0xf2438908, 0xf44f0110, 0xf7f72080, 0x1c60fb39, 0x1c68b990, 0x2100b980, 0x2080f44f, 
+    0xfae0f7f7, 0xf44f2100, 0xf7f72080, 0x2100fadb, 0x2080f44f, 0xfad6f7f7, 0x87f0e8bd, 0xb9081c60, 
+    0xe002241a, 0xb9001c68, 0x2300251a, 0x21102204, 0x381c48b9, 0xfffcf7fd, 0x461a2300, 0xb260b269, 
+    0xff9cf7ff, 0x461a2300, 0x46184619, 0xff70f7ff, 0x20012100, 0xff5cf7ff, 0x48af4639, 0xf7f73008, 
+    0x2301fa08, 0x46192200, 0x301448ab, 0xffe0f7fd, 0x381448a9, 0xf9f8f7f7, 0x46514682, 0x2080f44f, 
+    0xfaa0f7f7, 0x381048a4, 0xf9eef7f7, 0x46514682, 0x2080f44f, 0xfa96f7f7, 0xf44f4639, 0xf7f72080, 
+    0x2101fa91, 0xf7ff0248, 0x489cfa6f, 0xb9487800, 0x4631b126, 0xf0014648, 0xe003fa3e, 0x46082100, 
+    0xfa39f001, 0x22112301, 0x48930459, 0xf7fd381c, 0x2301ffaf, 0x46192200, 0x381c488f, 0xffa8f7fd, 
+    0x221fbf00, 0x488c07d1, 0xf7fd381c, 0x2800ffb8, 0x488ad0f7, 0xb9607800, 0x0f00f1b8, 0x4631d004, 
+    0xf0014648, 0xe004fa18, 0x2100b11e, 0xf0014608, 0x2301fa12, 0x03d9220f, 0x381c487f, 0xff88f7fd, 
+    0x02482101, 0xfa30f7ff, 0xe775bf00, 0x41f0e92d, 0x460c4606, 0xf2434615, 0xf44f0120, 0xf7f72080, 
+    0x1c60fa91, 0x1c68b990, 0x2100b980, 0x2080f44f, 0xfa38f7f7, 0xf44f2100, 0xf7f72080, 0x2100fa33, 
+    0x2080f44f, 0xfa2ef7f7, 0x81f0e8bd, 0xb9081c60, 0xe002241a, 0xb9001c68, 0x2300251a, 0x21102204, 
+    0x381c4865, 0xff54f7fd, 0xb262b26b, 0x46082100, 0xfef4f7ff, 0x461a2300, 0x46184619, 0xfec8f7ff, 
+    0x20002101, 0xfeb4f7ff, 0x485b4631, 0xf7f73008, 0x2301f960, 0x46192200, 0x30144857, 0xff38f7fd, 
+    0x38144855, 0xf950f7f7, 0x46394607, 0x2080f44f, 0xf9f8f7f7, 0x38104850, 0xf946f7f7, 0x46394607, 
+    0x2080f44f, 0xf9eef7f7, 0xf44f4631, 0xf7f72080, 0x2101f9e9, 0xf7ff0248, 0x2301f9c7, 0x04592211, 
+    0x381c4845, 0xff14f7fd, 0x22002301, 0x48424619, 0xf7fd381c, 0xbf00ff0d, 0x07d1221f, 0x381c483e, 
+    0xff1df7fd, 0xd0f72800, 0x220f2301, 0x483a03d9, 0xf7fd381c, 0x2101fefd, 0xf7ff0248, 0xbf00f9a5, 
+    0xe92de792, 0x46814ff8, 0x4615460c, 0xe9dd469a, 0xe9ddb80c, 0xf243670a, 0xf44f0130, 0xf7f72080, 
+    0x1c60fa01, 0x1c68b9b0, 0x1c70b9a0, 0x1c78b990, 0x2100b980, 0x2080f44f, 0xf9a4f7f7, 0xf44f2100, 
+    0xf7f72080, 0x2100f99f, 0x2080f44f, 0xf99af7f7, 0x8ff8e8bd, 0xb9001c70, 0x1c78261a, 0x271ab900, 
+    0x22042301, 0x481c2110, 0xf7fd381c, 0xb27bfec1, 0xb269b272, 0xf7ffb260, 0x2300fe61, 0x4619461a, 
+    0xf7ff4618, 0xfa4ffe35, 0xfa4ff18b, 0xf7fff08a, 0x4649fe1f, 0x30084810, 0xf8cbf7f7, 0x22002301, 
+    0x480d4619, 0xf7fd3014, 0x480bfea3, 0xf7f73814, 0x4601f8bb, 0xf44f9000, 0xf7f72080, 0x4806f963, 
+    0xf7f73810, 0x4601f8b1, 0xf44f9000, 0xf7f72080, 0x4649f959, 0x0000e004, 0xd180001c, 0x000361ee, 
+    0x2080f44f, 0xf94ef7f7, 0x02482101, 0xf92cf7ff, 0x780048fe, 0xf1b8b958, 0xd0040f00, 0x980f4641, 
+    0xf8f9f001, 0x2100e003, 0xf0014608, 0x2301f8f4, 0x04592211, 0xf7fd48f6, 0x2301fe6b, 0x46192200, 
+    0xf7fd48f3, 0xbf00fe65, 0x07d1221f, 0xf7fd48f0, 0x2800fe76, 0x48edd0f8, 0xb9687800, 0xb120980e, 
+    0x980f4641, 0xf8d7f001, 0xf1b8e006, 0xd0030f00, 0x46082100, 0xf8cff001, 0x220f2301, 0x48e403d9, 
+    0xfe46f7fd, 0x02482101, 0xf8eef7ff, 0xe76fbf00, 0x41f0e92d, 0x460e4604, 0x461f4615, 0x0160f243, 
+    0x2080f44f, 0xf94ef7f7, 0x22042301, 0x48d82110, 0xfe2ef7fd, 0xb26ab26b, 0xb260b261, 0xfdcef7ff, 
+    0x461a2300, 0x46184619, 0xfda2f7ff, 0xb270b279, 0xfd8ef7ff, 0x461a2300, 0x48cd2101, 0xf7fd3030, 
+    0x48cbfe17, 0xf7f73008, 0x4680f82f, 0xf44f4641, 0xf7f72080, 0x48c6f8d7, 0xf7f7300c, 0x4680f825, 
+    0xf44f4641, 0xf7f72080, 0x2100f8cd, 0x2080f44f, 0xf8c8f7f7, 0x22112300, 0x3100f44f, 0xf7fd48bc, 
+    0x2301fdf7, 0x46192200, 0xf7fd48b9, 0xe8bdfdf1, 0xb57081f0, 0xf6404604, 0x46230500, 0x21012200, 
+    0xf7fd48b3, 0x2c01fde5, 0xbf00d00b, 0x07d1221f, 0xf7fd48af, 0x2801fdf4, 0x1e68d003, 0x1e05b280, 
+    0xbd70dcf4, 0x2200b510, 0x48a92101, 0xfde7f7fd, 0xbd10b240, 0x4604b570, 0x4616460d, 0x22104623, 
+    0x017ff44f, 0x1d0048a2, 0xfdc2f7fd, 0x2200462b, 0x489f21ff, 0xf7fd1d00, 0x4633fdbb, 0xf64f2208, 
+    0x489b7100, 0xf7fd1d00, 0xbd70fdb3, 0x4604b570, 0x4623460d, 0x49972210, 0x30204895, 0xfda8f7fd, 
+    0x2200462b, 0x71fff64f, 0x30204891, 0xfda0f7fd, 0xe92dbd70, 0x460441f0, 0x4616460d, 0x4623461f, 
+    0x0291220c, 0x3008488a, 0xfd92f7fd, 0x2208462b, 0x48870151, 0xf7fd3008, 0x4633fd8b, 0x21f02204, 
+    0x30084883, 0xfd84f7fd, 0x2200463b, 0x48802103, 0xf7fd3008, 0xe8bdfd7d, 0xb51081f0, 0x487bb086, 
+    0xb9e07800, 0x21012200, 0xf7fd487b, 0xb988fdaf, 0x21022201, 0xf7fd4878, 0xb958fda9, 0x21042202, 
+    0xf7fd4875, 0xb928fda3, 0x21082203, 0xf7fd4872, 0xb108fd9d, 0xe0002001, 0x46042000, 0x2400e000, 
+    0xe9cd2001, 0x94040402, 0x9000200b, 0x22092301, 0x94054611, 0x02589001, 0xfe53f7ff, 0xbd10b006, 
+    0xb086b510, 0x78004861, 0x2200b9e0, 0x48622101, 0xfd7cf7fd, 0x2201b988, 0x485f2102, 0xfd76f7fd, 
+    0x2202b958, 0x485c2104, 0xfd70f7fd, 0x2203b928, 0x48592108, 0xfd6af7fd, 0x2001b108, 0x2000e000, 
+    0xe0004604, 0x20012400, 0x0402e9cd, 0x200b9404, 0x23019000, 0x46112209, 0x90019405, 0xf7ff0258, 
+    0x2001fe20, 0x0402e9cd, 0x200c9404, 0x23019000, 0x4611220a, 0x90019405, 0xf7ff02d8, 0xb006fe12, 
+    0xb510bd10, 0x4611220b, 0x2000f240, 0xfd7ef7ff, 0x4611220c, 0x0000f640, 0xfd78f7ff, 0xb51cbd10, 
+    0x7800483a, 0x2200b9e0, 0x483b2101, 0xfd2ef7fd, 0x2201b988, 0x48382102, 0xfd28f7fd, 0x2202b958, 
+    0x48352104, 0xfd22f7fd, 0x2203b928, 0x48322108, 0xfd1cf7fd, 0x2001b108, 0x2000e000, 0xe0004604, 
+    0x94002400, 0x22094623, 0xf2404611, 0x94012000, 0xfca1f7ff, 0x46239400, 0x4611220a, 0x0000f640, 
+    0xf7ff9401, 0xbd1cfc98, 0x5fffe92d, 0x24004682, 0x2500e023, 0x42a5e01d, 0x2008d101, 0x2002e000, 
+    0xf1ab4683, 0xb2460001, 0xeb0ae008, 0xeb001045, 0x5d8000c4, 0xe003b100, 0xb2461e70, 0xdaf42e00, 
+    0x1c70bf00, 0x4669b240, 0x0185eb01, 0x1c685508, 0x2d04b245, 0x1c60dbdf, 0x2c04b244, 0xf04fdbd9, 
+    0x24000800, 0x4625e00d, 0xeb004668, 0x57000085, 0xdd044540, 0xeb004668, 0xf9100085, 0x1c608004, 
+    0x2c04b244, 0x4643dbef, 0xe0072204, 0x000361ee, 0xd1800000, 0xffff0000, 0xd0030024, 0x484921f0, 
+    0xfc76f7fd, 0x0800f04f, 0xe0162400, 0xe0102500, 0xd10042a5, 0x4668e00b, 0x0085eb00, 0x45405700, 
+    0x4668dd04, 0x0085eb00, 0x8004f910, 0x1c68bf00, 0x2d04b245, 0x1c60dbec, 0x2c04b244, 0x4643dbe6, 
+    0x21032200, 0xf7fd4837, 0x4836fc53, 0xf7f63040, 0x4607fe6b, 0x090ff04f, 0xe0122400, 0xe00c2500, 
+    0xeb004668, 0x5d000085, 0x2001b918, 0xf009fa00, 0xf1a94387, 0x1c680901, 0x2d04b245, 0x1c60dbf0, 
+    0x2c04b244, 0x4639dbea, 0x30404826, 0xfe51f7f6, 0x9fffe8bd, 0x47f0e92d, 0xf04f4606, 0x25000900, 
+    0x2400e014, 0x42ace00e, 0xe009d100, 0x0084eb06, 0x45485740, 0xeb06dd03, 0xf9100084, 0xbf009005, 
+    0xb2441c60, 0xdbee2c04, 0xb2451c68, 0xdbe82d04, 0x2208464b, 0x48130151, 0xfc0af7fd, 0x30404811, 
+    0xfe22f7f6, 0xf04f4607, 0x2500081f, 0x2400e011, 0xeb06e00b, 0x5d400084, 0x2001b918, 0xf008fa00, 
+    0xf1a84387, 0x1c600801, 0x2c04b244, 0x1c68dbf1, 0x2d04b245, 0x4639dbeb, 0x30404802, 0xfe09f7f6, 
+    0x87f0e8bd, 0xd1800008, 0x2301b510, 0x46192200, 0xf7fd48fe, 0x2300fc04, 0x2101461a, 0xf7fd48fc, 
+    0xf242fbfe, 0x48fb0140, 0xfdfef7f6, 0xb570bd10, 0x460d4604, 0x2203b2ab, 0x48f52108, 0xf7fd1e80, 
+    0xb2a3fbee, 0x21042202, 0x1e8048f1, 0xfbe7f7fd, 0xb570bd70, 0x460d4604, 0x2201b2ab, 0x48ec2102, 
+    0xf7fd1e80, 0xb2a3fbdc, 0x21012200, 0x1e8048e8, 0xfbd5f7fd, 0xb570bd70, 0x460d4604, 0x2206b2a3, 
+    0x48e32140, 0xf7fd1e80, 0xb2abfbca, 0x21202205, 0x1e8048df, 0xfbc3f7fd, 0xb510bd70, 0xb2a34604, 
+    0xf2402208, 0x48da3100, 0xf7fd1e80, 0xbd10fbb8, 0x47f0e92d, 0x460d4604, 0x461f4616, 0x8908e9dd, 
+    0xf7ff4628, 0x43e1ffea, 0xf7ff4620, 0x4639ffd4, 0xf7ff4630, 0x4649ffbe, 0xf7ff4640, 0xe8bdffa8, 
+    0xb51087f0, 0x220f2301, 0x48c949cb, 0xf7fd1e80, 0x2301fb96, 0x21802207, 0x1e8048c5, 0xfb8ff7fd, 
+    0xf7ff2001, 0xbf00ffca, 0x49c3220f, 0x1e8048c0, 0xfb9cf7fd, 0xd1f72800, 0xb510bd10, 0x22042301, 
+    0x48bb2110, 0xf7fd1e80, 0xbd10fb7a, 0x4604b510, 0x461a2301, 0x48b62102, 0xf7fd30b0, 0x48b7fb70, 
+    0xb9307800, 0x22002301, 0x48b14619, 0xf7fd30b0, 0x2301fb66, 0x49b0220f, 0x30b248ad, 0xfb5ff7fd, 
+    0x220d2301, 0x0100f246, 0x30b248a9, 0xfb57f7fd, 0x2200232e, 0x71fff641, 0x30b248a5, 0xfb4ff7fd, 
+    0x220f2300, 0x48a249a4, 0xf7fd30b4, 0x2303fb48, 0x0359220d, 0x30b4489e, 0xfb41f7fd, 0x22002305, 
+    0x71fff641, 0x30b4489a, 0xfb39f7fd, 0x220f2301, 0x48974999, 0xf7fd30b6, 0x2301fb32, 0xf246220d, 
+    0x48930100, 0xf7fd30b6, 0x2329fb2a, 0xf6412200, 0x488f71ff, 0xf7fd30b6, 0x2301fb22, 0x498e220f, 
+    0x30b8488b, 0xfb1bf7fd, 0x220d2301, 0x0100f246, 0x30b84887, 0xfb13f7fd, 0x461a2300, 0x71fff641, 
+    0x30b84883, 0xfb0bf7fd, 0x220f2300, 0x48804982, 0xf7fd30ba, 0x2301fb04, 0xf246220d, 0x487c0100, 
+    0xf7fd30ba, 0x2304fafc, 0xf6412200, 0x487871ff, 0xf7fd30ba, 0x2300faf4, 0x4977220f, 0x30bc4874, 
+    0xfaedf7fd, 0x220d2301, 0x0100f246, 0x30bc4870, 0xfae5f7fd, 0x736ef641, 0xf6412200, 0x487071ff, 
+    0xfaddf7fd, 0xd1102c04, 0x22002319, 0x71fff641, 0x30b24867, 0xfad3f7fd, 0x7383f641, 0xf6412200, 
+    0x486771ff, 0xfacbf7fd, 0x2c05e011, 0x2322d10f, 0xf6412200, 0x485e71ff, 0xf7fd30b2, 0xf641fac0, 
+    0x2200737a, 0x71fff641, 0xf7fd485d, 0x485dfab8, 0x28017800, 0x2300d114, 0x217f461a, 0xf7fd485a, 
+    0x23c8faae, 0xf06f2208, 0x485701ff, 0xf7fd1c80, 0x2310faa6, 0x21ff2200, 0x1c804853, 0xfa9ff7fd, 
+    0xf0002001, 0xbd10fede, 0x4604b510, 0x220c4623, 0x0100f241, 0x1e804846, 0xfa91f7fd, 0x220d4623, 
+    0x0100f242, 0x1e804842, 0xfa89f7fd, 0x220b4623, 0x0100f640, 0x1e80483e, 0xfa81f7fd, 0x22024623, 
+    0x483b2104, 0xfa7bf7fd, 0x3010483a, 0xfc76f7f6, 0x220f4623, 0x48364938, 0xf7fd1c80, 0xb93cfa70, 
+    0x220a2300, 0x4100f240, 0x1e804831, 0xfa67f7fd, 0xbd102001, 0x2200b510, 0x482d217f, 0xf7fd3080, 
+    0xb2c0fa75, 0xb510bd10, 0xf5044604, 0xb2014000, 0x38144827, 0xfc58f7f6, 0x4825bf00, 0xf7f63814, 
+    0xf400fc4d, 0x28004000, 0x2101d1f7, 0xf7fe0348, 0xbd10fccb, 0x4604b510, 0x220f2300, 0x481c491e, 
+    0xf7fd30c0, 0x2301fa3c, 0xf246220d, 0x48180100, 0xf7fd30c0, 0xb2a3fa34, 0xf6412200, 0x481471ff, 
+    0xf7fd30c0, 0xbd10fa2c, 0x4604b510, 0x2200b2a3, 0x480f2101, 0xf7fd3060, 0xbd10fa22, 0x41f0e92d, 
+    0x460d4604, 0x461f4616, 0x220fb2b3, 0x4808490a, 0xf7fd3020, 0xb2a3fa14, 0xf2402200, 0x480471ff, 
+    0xf7fd3020, 0xb2bbfa0c, 0xe00f220f, 0xd0020126, 0xd0035024, 0xd0020000, 0xffff8000, 0x000361ee, 
+    0xd00351c4, 0x000384e0, 0xd0030480, 0x48964995, 0xf9f5f7fd, 0x2200b2ab, 0x71fff240, 0xf7fd4892, 
+    0xe8bdf9ee, 0xb51081f0, 0x23014604, 0x2102461a, 0x30aa488d, 0xf9e3f7fd, 0xeb002001, 0xb2830044, 
+    0xf6402200, 0x488871ff, 0xf7fd30ae, 0x2301f9d8, 0x0319220c, 0x30ae4884, 0xf9d1f7fd, 0x20042101, 
+    0xfc52f7fe, 0xb510bd10, 0x23014604, 0x2102461a, 0x30a4487d, 0xf9c3f7fd, 0xeb002001, 0xb2830044, 
+    0xf6402200, 0x487871ff, 0xf7fd30a6, 0x2301f9b8, 0x0319220c, 0x30a64874, 0xf9b1f7fd, 0x20042101, 
+    0xfc32f7fe, 0xb570bd10, 0x2d004605, 0x2300db1d, 0xf2402209, 0x486c2100, 0xf7fd3050, 0x462cf9a0, 
+    0x2301e010, 0x02592209, 0x30504867, 0xf997f7fd, 0x22092300, 0x2100f240, 0x30504863, 0xf98ff7fd, 
+    0xb2041e60, 0xdcec2c00, 0x2d00e01c, 0x2300da1a, 0x01512208, 0x3050485c, 0xf981f7fd, 0xe00f462c, 
+    0x22082301, 0x48580151, 0xf7fd3050, 0x2300f978, 0x01512208, 0x30504854, 0xf971f7fd, 0xb2041c60, 
+    0xdbed2c00, 0x20042101, 0xfbeef7fe, 0xf9b0484f, 0xf7ff0000, 0xbd70ff78, 0x4604b510, 0x220bb2a3, 
+    0x0100f640, 0x381c4848, 0xf959f7fd, 0x220cb2a3, 0x0100f241, 0x381c4844, 0xf951f7fd, 0xd1072c01, 
+    0x4240f04f, 0x1161f240, 0xf7f62010, 0xe006fc02, 0x4240f04f, 0x1160f240, 0xf7f62010, 0xbd10fbfa, 
+    0x4604b510, 0xd1362c04, 0x22002306, 0x4838210f, 0xf935f7fd, 0x22042303, 0x483521f0, 0xf92ff7fd, 
+    0x2208230b, 0x7100f640, 0xf7fd4831, 0x2304f928, 0x4930220c, 0xf7fd482e, 0x2303f922, 0x210f2200, 
+    0x1c80482b, 0xf91bf7fd, 0x2204230c, 0x482821f0, 0xf7fd1c80, 0x2302f914, 0xf6402208, 0x48247100, 
+    0xf7fd1c80, 0x2304f90c, 0x4922220c, 0x1c804820, 0xf905f7fd, 0x2306e035, 0x210f2200, 0xf7fd481c, 
+    0x2303f8fe, 0x21f02204, 0xf7fd4819, 0x230cf8f8, 0xf6402208, 0x48167100, 0xf8f1f7fd, 0x220c2304, 
+    0x48134914, 0xf8ebf7fd, 0x22002303, 0x4810210f, 0xf7fd1c80, 0x230df8e4, 0x21f02204, 0x1c80480c, 
+    0xf8ddf7fd, 0x22082302, 0x7100f640, 0x1c804808, 0xf8d5f7fd, 0x220c2304, 0x48054906, 0xf7fd1c80, 
+    0xbd10f8ce, 0xffff8000, 0xd0035042, 0x0003622a, 0xd003529c, 0xfffff000, 0x41f0e92d, 0x460d4604, 
+    0x461f4616, 0x2206b2a3, 0x48f721c0, 0xf8b7f7fd, 0x2204b2ab, 0x48f42130, 0xf8b1f7fd, 0x2202b2b3, 
+    0x48f1210c, 0xf8abf7fd, 0x2200b2bb, 0x48ee2103, 0xf8a5f7fd, 0x2206b2a3, 0x48eb21c0, 0xf7fd301c, 
+    0xb2abf89e, 0x21302204, 0x301c48e7, 0xf897f7fd, 0x2202b2b3, 0x48e4210c, 0xf7fd301c, 0xb2bbf890, 
+    0x21032200, 0x301c48e0, 0xf889f7fd, 0x2200b2a3, 0x48de2103, 0xf883f7fd, 0x2202b2ab, 0x48db210c, 
+    0xf87df7fd, 0x2204b2b3, 0x48d82130, 0xf877f7fd, 0x2206b2bb, 0x48d521c0, 0xf871f7fd, 0x81f0e8bd, 
+    0x4604b510, 0x22002301, 0x48cf4619, 0xf7fd3840, 0x4620f866, 0xfa8cf7f6, 0xb570bd10, 0x48cc4605, 
+    0xffeef7ff, 0xe0292400, 0xbb285d28, 0x680048c9, 0xd00b2812, 0x680048c7, 0xd0072816, 0x780048c6, 
+    0xd0032804, 0x780048c4, 0xd10a2805, 0xf85048c0, 0xf5b00024, 0xd9014f20, 0xe0002001, 0x55282000, 
+    0x48bbe00a, 0x0024f850, 0x2162f249, 0xd9014288, 0xe0002001, 0x55282000, 0xb2441c60, 0xdbd32c04, 
+    0xb570bd70, 0x48b24605, 0xffbaf7ff, 0xe0082400, 0xf85048af, 0x42a80024, 0x2001d901, 0x1c60bd70, 
+    0x2c04b244, 0x2000dbf4, 0xb510e7f8, 0x48a64604, 0xf7f63812, 0xf3c0fa13, 0x80200009, 0x381048a2, 
+    0xfa0cf7f6, 0x0009f3c0, 0x489f8060, 0xf7f6380e, 0xf3c0fa05, 0x80a00009, 0x380c489b, 0xf9fef7f6, 
+    0x0009f3c0, 0xbd1080e0, 0x4605b570, 0xe00d2400, 0x2014f835, 0x0209f3c2, 0x6180f442, 0x3a124a92, 
+    0x0044eb02, 0xf9f0f7f6, 0xb2441c60, 0xdbef2c04, 0x2106f240, 0x0080f44f, 0xfad4f7f6, 0xf6472200, 
+    0x488971ff, 0xf7fc3834, 0x4606fff1, 0xf44f4631, 0xf7f60080, 0x4889fa77, 0xf4006800, 0xb1a00080, 
+    0x68004887, 0x4887b988, 0xf2406800, 0x428871fe, 0x4985da0b, 0x68124a83, 0x0082eb01, 0xffa5f7ff, 
+    0x68004880, 0x497f1c80, 0xbd706008, 0x4604b510, 0x2200b2a3, 0x48742101, 0xf7fc383e, 0xbd10ffb0, 
+    0x4604b570, 0x4616460d, 0x220bb2b3, 0x0100f640, 0x381e486d, 0xffa3f7fc, 0x220cb2ab, 0x0100f247, 
+    0x381e4869, 0xff9bf7fc, 0x220fb2a3, 0x4866496f, 0xf7fc381e, 0xb2b3ff94, 0xf640220b, 0x48620100, 
+    0xf7fc381c, 0xb2abff8c, 0xf247220c, 0x485e0100, 0xf7fc381c, 0xb2a3ff84, 0x4964220f, 0x381c485a, 
+    0xff7df7fc, 0x220bb2b3, 0x0100f640, 0x381a4856, 0xff75f7fc, 0x220cb2ab, 0x0100f247, 0x381a4852, 
+    0xff6df7fc, 0x220fb2a3, 0x484f4958, 0xf7fc381a, 0xb2b3ff66, 0xf640220b, 0x484b0100, 0xf7fc3818, 
+    0xb2abff5e, 0xf247220c, 0x48470100, 0xf7fc3818, 0xb2a3ff56, 0x494d220f, 0x38184843, 0xff4ff7fc, 
+    0xb510bd70, 0x48404604, 0xf7f6380a, 0xf000f947, 0x8020001f, 0x3808483c, 0xf940f7f6, 0x001ff000, 
+    0x48398060, 0xf7f61f80, 0xf000f939, 0x80a0001f, 0x1f004835, 0xf932f7f6, 0x001ff000, 0xbd1080e0, 
+    0x4605b570, 0x210f2200, 0xf7fc4839, 0x4939ff3f, 0x44088809, 0x80084937, 0x210f2200, 0xf7fc4836, 
+    0x4934ff35, 0x44088849, 0x80484932, 0x210f2200, 0xf7fc4832, 0x492fff2b, 0x44088889, 0x8088492d, 
+    0x210f2200, 0xf7fc482e, 0x492aff21, 0x440888c9, 0x80c84928, 0x22052301, 0x48252120, 0xf7fc3812, 
+    0x2301fefe, 0x21202205, 0x38124823, 0xfef7f7fc, 0x22052301, 0x48212120, 0xf7fc3812, 0x2301fef0, 
+    0x21202205, 0x3812481e, 0xfee9f7fc, 0x22052300, 0x48172120, 0xf7fc3812, 0x2300fee2, 0x21202205, 
+    0x38124815, 0xfedbf7fc, 0x22052300, 0x48132120, 0xf7fc3812, 0x2300fed4, 0x21202205, 0x38124810, 
+    0xfecdf7fc, 0xe02a2400, 0xd0030446, 0xd0035124, 0x00038fe0, 0x000361dc, 0x0003626a, 0x0005280c, 
+    0x000362f4, 0x00052800, 0x00050800, 0xffff8000, 0xd003c2b6, 0x000362da, 0xd003cab6, 0xd003d2b6, 
+    0xd003dab6, 0x2014f815, 0x021ff002, 0x0120f042, 0xeb024afe, 0xf7f60044, 0x1c60f8a7, 0x2c04b244, 
+    0x2172dbf0, 0x0080f44f, 0xf98cf7f6, 0xf2402200, 0x48f671ff, 0xf7fc380c, 0x4606fea9, 0xf44f4631, 
+    0xf7f60080, 0x48f2f92f, 0xf4006800, 0xb1a00080, 0x680048f0, 0x48f0b988, 0xf2406800, 0x428871fe, 
+    0x49eeda0b, 0x68124aec, 0x0082eb01, 0xff29f7ff, 0x680048e9, 0x49e81c80, 0xbd706008, 0x4602b5f0, 
+    0x26002000, 0x3f80f5b2, 0x240fd301, 0x2407e000, 0x0c44ea4f, 0xfa072701, 0x4621f50c, 0x1c4fbf00, 
+    0xf707fa00, 0x197b4437, 0xd8034293, 0x2701461e, 0x4338408f, 0xd0014293, 0x1e4908ad, 0xdb012900, 
+    0xd1ec4293, 0xb570bdf0, 0x460d4604, 0x48cfb221, 0xf7f63008, 0xb229f849, 0xf7f648d1, 0xbd70f845, 
+    0x4604b510, 0x2200b2a3, 0x71fff643, 0x382648c7, 0xfe35f7fc, 0x220e2301, 0x48c40399, 0xf7fc3826, 
+    0xbd10fe2e, 0x4604b510, 0x22074623, 0x48bf2180, 0xf7fc383c, 0x4623fe24, 0x21012200, 0x300848bb, 
+    0xfe1df7fc, 0x22004623, 0x48bd2101, 0xfe17f7fc, 0xb510bd10, 0xf0132001, 0x2000fe5b, 0xffe2f7ff, 
+    0xf2402100, 0xf7ff1000, 0x2047ffbe, 0xfbc2f7ff, 0xf7ff204e, 0x2101ffc5, 0xf7fe02c8, 0xbd10f885, 
+    0x2301b510, 0x2102461a, 0x383648a8, 0xfdf7f7fc, 0xb570bd10, 0x460d4604, 0x220cb2a3, 0x48aa49a9, 
+    0xfdedf7fc, 0x2208b2ab, 0x48a70151, 0xfde7f7fc, 0x780048a6, 0xd10c2803, 0x22072300, 0x48a22180, 
+    0xfdddf7fc, 0x22032300, 0x489f2108, 0xfdd7f7fc, 0x489ee030, 0x28027800, 0x2300d10c, 0x21402206, 
+    0xf7fc4899, 0x2300fdcc, 0x21042202, 0xf7fc4896, 0xe01ffdc6, 0x78004895, 0xd10c2801, 0x22052300, 
+    0x48912120, 0xfdbbf7fc, 0x22012300, 0x488e2102, 0xfdb5f7fc, 0x488de00e, 0xb9587800, 0x22042300, 
+    0x48892110, 0xfdabf7fc, 0x461a2300, 0x48862101, 0xfda5f7fc, 0xb570bd70, 0x460d4604, 0x78004883, 
+    0xd10c2803, 0x2207b2a3, 0x487f2180, 0xfd97f7fc, 0x2203b2ab, 0x487c2108, 0xfd91f7fc, 0x487be030, 
+    0x28027800, 0xb2a3d10c, 0x21402206, 0xf7fc4876, 0xb2abfd86, 0x21042202, 0xf7fc4873, 0xe01ffd80, 
+    0x78004872, 0xd10c2801, 0x2205b2a3, 0x486e2120, 0xfd75f7fc, 0x2201b2ab, 0x486b2102, 0xfd6ff7fc, 
+    0x486ae00e, 0xb9587800, 0x2204b2a3, 0x48662110, 0xfd65f7fc, 0x2200b2ab, 0x48632101, 0xfd5ff7fc, 
+    0xb510bd70, 0xb2a34604, 0x21012200, 0x1f00485e, 0xfd55f7fc, 0xe92dbd10, 0xb0874ff3, 0x24004683, 
+    0x9808e088, 0x485ab9b0, 0x2301495a, 0xe9cd2200, 0xb2611000, 0xf7fc4618, 0x4856f9d4, 0x7040f9b0, 
+    0xf9b04853, 0xa8055040, 0x7014f820, 0xf820a803, 0xe0065014, 0xf930a805, 0xa8037014, 0x5014f930, 
+    0xbf00bf00, 0xf007fb07, 0x0a05fb05, 0xdb011e39, 0xe000460a, 0xf5b2424a, 0xda077f00, 0xdb011e28, 
+    0xe0004602, 0xf5b24242, 0xdb0c7f00, 0x100aea4f, 0xfea4f7ff, 0x04f8b206, 0xf9f6fb90, 0xfb9004e8, 
+    0x10b6f8f6, 0xea4fe00b, 0xf7ff208a, 0xb206fe97, 0xfb9005b8, 0x05a8f9f6, 0xf8f6fb90, 0xea4f1176, 
+    0xea4f1868, 0xf6401969, 0xf44f0101, 0xf7f53000, 0x4639ffe9, 0x3000f44f, 0xff94f7f5, 0xf44f4629, 
+    0xf7f53000, 0x4641ff8f, 0x3000f44f, 0xff8af7f5, 0xf44f4649, 0xf7f53000, 0x4631ff85, 0x3000f44f, 
+    0xff80f7f5, 0x311c4920, 0x0084eb01, 0xf189fa0f, 0xfedaf7f5, 0x311e491c, 0x0084eb01, 0xf188fa0f, 
+    0xfed2f7f5, 0x310c4918, 0x0044eb01, 0xf7f54631, 0x1c64fecb, 0xf6ff2c04, 0x2302af74, 0xf06f2208, 
+    0x481101ff, 0xf7fc1e80, 0xf3c6fcba, 0x2201234f, 0x480d210e, 0xf7fc1e80, 0xfa1ffcb2, 0x2200f38b, 
+    0x48092101, 0xf7fc1e80, 0xe015fcaa, 0xd003043c, 0x0005280c, 0x000362f4, 0x00052800, 0x00050800, 
+    0xd0031012, 0xfffff000, 0xd0030024, 0x000362b1, 0x00044b08, 0x00044308, 0xe8bdb009, 0xb5108ff0, 
+    0x48fa210f, 0xfe90f7f5, 0xb510bd10, 0x46234604, 0xf6402208, 0x48f57100, 0xf7fc3828, 0xbd10fc80, 
+    0x4604b510, 0x22004623, 0x48f0211f, 0xf7fc3824, 0xbd10fc76, 0x4604b510, 0x48ecb221, 0xf7f53826, 
+    0xbd10fe73, 0x41f0e92d, 0x460f4606, 0xd0102e01, 0xd00b2e02, 0xd0052e04, 0xd10d2e08, 0x0500f247, 
+    0xe00a240c, 0x7500f240, 0xe0062408, 0x24042570, 0x2507e003, 0xe0002400, 0xbf00bf00, 0xb262463b, 
+    0x48dab229, 0xf7fc1d80, 0xe8bdfc4a, 0xe92d81f0, 0x460641f0, 0x2e01460f, 0x2e02d00e, 0x2e04d009, 
+    0x2e08d004, 0x2403d10b, 0xe0092508, 0x25042402, 0x2401e006, 0xe0032502, 0x25012400, 0xbf00e000, 
+    0x463bbf00, 0xb229b262, 0x1d0048c8, 0xfc27f7fc, 0x81f0e8bd, 0x4604b510, 0x48c44621, 0xf7f53008, 
+    0xbd10fe23, 0x2000b510, 0xfff4f7ff, 0x20082101, 0xffcdf7ff, 0x20042101, 0xffc9f7ff, 0x20022101, 
+    0xffc5f7ff, 0x46082101, 0xffc1f7ff, 0x20082103, 0xff98f7ff, 0x20042103, 0xff94f7ff, 0x20022103, 
+    0xff90f7ff, 0x20012103, 0xff8cf7ff, 0x3000f240, 0xff80f7ff, 0xf7ff2010, 0x2005ff73, 0xff65f7ff, 
+    0xff5df7ff, 0xb510bd10, 0x48a92100, 0xfdecf7f5, 0xffc8f7ff, 0xf7fd201c, 0xbd10ff5a, 0x4604b510, 
+    0x220c4623, 0x0100f241, 0xf7fc48a1, 0x4623fbd8, 0xf240220a, 0x489e4100, 0xfbd1f7fc, 0xb510bd10, 
+    0x46234604, 0x210f2200, 0x30484899, 0xfbc7f7fc, 0xb510bd10, 0x30484896, 0xfdc0f7f5, 0x000ff000, 
+    0xb510bd10, 0x46234604, 0xf2402200, 0x489031ff, 0xf7fc1d00, 0xbd10fbb4, 0x4604b510, 0x220d4623, 
+    0x0100f242, 0xf7fc488a, 0x4623fbaa, 0xf640220b, 0x48870100, 0xfba3f7fc, 0xb510bd10, 0x22062301, 
+    0x48842140, 0xfb9bf7fc, 0x22032300, 0x48812108, 0xfb95f7fc, 0x22022301, 0x487e2104, 0xfb8ff7fc, 
+    0x461a2301, 0x487b2102, 0xfb89f7fc, 0x22002301, 0x48784619, 0xfb83f7fc, 0x22062301, 0x48752140, 
+    0xf7fc1c80, 0x2300fb7c, 0x21082203, 0x1c804871, 0xfb75f7fc, 0x22022301, 0x486e2104, 0xf7fc1c80, 
+    0x2301fb6e, 0x2102461a, 0x1c80486a, 0xfb67f7fc, 0x22002301, 0x48674619, 0xf7fc1c80, 0x2301fb60, 
+    0x21402206, 0x1d004863, 0xfb59f7fc, 0x22032300, 0x48602108, 0xf7fc1d00, 0x2301fb52, 0x21042202, 
+    0x1d00485c, 0xfb4bf7fc, 0x461a2301, 0x48592102, 0xf7fc1d00, 0x2301fb44, 0x46192200, 0x1d004855, 
+    0xfb3df7fc, 0x22062301, 0x48522140, 0xf7fc1d80, 0x2300fb36, 0x21082203, 0x1d80484e, 0xfb2ff7fc, 
+    0x22022301, 0x484b2104, 0xf7fc1d80, 0x2301fb28, 0x2102461a, 0x1d804847, 0xfb21f7fc, 0x22002301, 
+    0x48444619, 0xf7fc1d80, 0x2301fb1a, 0x21042202, 0x300a4840, 0xfb13f7fc, 0x461a2301, 0x483d2102, 
+    0xf7fc300a, 0x2301fb0c, 0x46192200, 0x300a4839, 0xfb05f7fc, 0xb570bd10, 0x460d4604, 0x22014623, 
+    0x48322102, 0xf7fc38e8, 0x2306fafa, 0x21702204, 0x38e8482e, 0xfaf3f7fc, 0x2200462b, 0x482b2101, 
+    0xf7fc38e8, 0xbd70faec, 0x4604b510, 0x4827b221, 0xf7f538e6, 0xbd10fce9, 0x4824b510, 0xf7f538e6, 
+    0xb280fcdd, 0xb510bd10, 0xb2a34604, 0xf2402200, 0x481f71ff, 0xf7fc3030, 0xbd10fad2, 0x4607b5f8, 
+    0x2400460e, 0x2000e02e, 0x46024b1b, 0x9000b261, 0xf7fb2001, 0x2000ff7a, 0x0014f826, 0xf8271e40, 
+    0x25000014, 0x4914e01a, 0x0015f931, 0xdb012800, 0xe0004601, 0xf9364241, 0x42912014, 0x490edd0c, 
+    0x0015f931, 0xdb012800, 0xe0004601, 0xb2094241, 0x1014f826, 0x5014f827, 0xb2051c68, 0xdbe22d80, 
+    0xb2041c60, 0xdbce2c04, 0x0000bdf8, 0xd00305da, 0xd0030400, 0xd0030000, 0x00043078, 0x5ffce92d, 
+    0x20004683, 0x46024bfe, 0xf18bfa4f, 0x20019000, 0xff3bf7fb, 0x460e2100, 0x4688460f, 0x468a4689, 
+    0x48f7e017, 0x001af830, 0xf400fb10, 0x193617e5, 0xea4f416f, 0xfba471ea, 0xfb05020a, 0xfb04220a, 
+    0xeb102201, 0xeb420808, 0xf10a0909, 0xfa0f0001, 0xf1bafa80, 0xdbe40f80, 0x463b4632, 0x46494640, 
+    0xeafef021, 0x9001b200, 0xe8bd9801, 0xe92d9ffc, 0xb08743f0, 0xe0672500, 0x4be12000, 0xb2694602, 
+    0x20019000, 0xff01f7fb, 0xa9052000, 0x0015f821, 0xa9031e40, 0x0015f821, 0xe01d2400, 0xf93149d8, 
+    0x28000014, 0x4601db01, 0x4241e000, 0xf932aa05, 0x42912015, 0x49d2dd0e, 0x0014f931, 0xdb012800, 
+    0xe0004601, 0xb2094241, 0xf822aa05, 0xa8031015, 0x4015f820, 0xb2041c60, 0xdbdf2c80, 0xf930a803, 
+    0x27004015, 0x49c6e00b, 0x0014f931, 0xdb012800, 0xe0004601, 0x44394241, 0x1c60b20f, 0x2c80b204, 
+    0x11ffdbf1, 0x20002400, 0xf821a901, 0x46810015, 0x49bbe012, 0x0014f931, 0xdb012800, 0xe0004601, 
+    0x44494241, 0xf981fa0f, 0xdd0345b9, 0xf820a801, 0xe0064015, 0xb2041c60, 0xf930a803, 0x42a00015, 
+    0xbf00dce7, 0xb2051c68, 0xdb952d04, 0xf04f2501, 0x26000800, 0xa803e01b, 0x0015f930, 0xf931a903, 
+    0x42881018, 0x46a8dd00, 0xf930a803, 0xa9010015, 0x1015f931, 0xa9031a40, 0x1016f931, 0xf932aa01, 
+    0x1a892016, 0xdd004288, 0x1c68462e, 0x2d04b205, 0xa803dbe1, 0x0016f830, 0xf831a903, 0xebc11018, 
+    0xa9010040, 0x1016f831, 0x38081a40, 0x2c00b204, 0x4620dd5f, 0x71d0eb04, 0xeba41049, 0xb1090141, 
+    0xb2041c60, 0x8800488f, 0x0064eb00, 0x498db200, 0x10608008, 0xff47f7fe, 0xf7fe4620, 0x2101fff4, 
+    0xf7fd0208, 0xf240fc21, 0xf44f11f4, 0xf7f50000, 0xf04ffc89, 0xf44f3134, 0xf7f50000, 0xf9bdfc33, 
+    0xf44f100c, 0xf7f50000, 0xf9bdfc2d, 0xf44f100e, 0xf7f50000, 0xf9bdfc27, 0xf44f1010, 0xf7f50000, 
+    0xf9bdfc21, 0xf44f1012, 0xf7f50000, 0xf9bdfc1b, 0xf44f1004, 0xf7f50000, 0xf9bdfc15, 0xf44f1006, 
+    0xf7f50000, 0xf9bdfc0f, 0xf44f1008, 0xf7f50000, 0xf9bdfc09, 0xf44f100a, 0xf7f50000, 0x4621fc03, 
+    0x0000f44f, 0xfbfef7f5, 0xf44f4967, 0xf7f50000, 0xb007fbf9, 0x83f0e8bd, 0x4604b510, 0x22004623, 
+    0x48622101, 0xf94bf7fc, 0xb510bd10, 0x302a485f, 0xfb44f7f5, 0xbd10b280, 0x47fce92d, 0x24004680, 
+    0x2500e02c, 0x42a5e026, 0x2000d101, 0x42a5e004, 0x1c68da01, 0x4628e000, 0xf980fa4f, 0x20004f50, 
+    0x464a463b, 0x90004621, 0xf7fb2001, 0xeb08fdde, 0x5d000085, 0x2180b960, 0xf0234638, 0x2000f89d, 
+    0x464a4603, 0xe9cd4621, 0x20017000, 0xfd02f7fb, 0xb2451c68, 0xdbd62d04, 0xb2441c60, 0xdbd02c04, 
+    0x0a00f04f, 0xe0112400, 0xe00b2500, 0xd10042a5, 0xeb08e006, 0x5d000085, 0xf04fb108, 0xbf000a01, 
+    0xb2451c68, 0xdbf12d04, 0xb2441c60, 0xdbeb2c04, 0xf7f54837, 0x4606faf3, 0x0f00f1ba, 0xf026d102, 
+    0xe0010607, 0x0607f046, 0xe0082400, 0x22024930, 0x1004fb02, 0xf7f54631, 0x1c60fae7, 0x2c04b244, 
+    0xe8bddbf4, 0xe92d87fc, 0xb0874ff0, 0x9002205a, 0x21012200, 0xf7fc4827, 0xfa4ff8c2, 0x2000fb80, 
+    0xfab7f7fe, 0xe0502500, 0xe04a2400, 0xd10142ac, 0xe0042000, 0xda0142ac, 0xe0001c60, 0xfa4f4620, 
+    0x42acf980, 0x2001d101, 0x2001e000, 0xf8df4682, 0x20008050, 0x464a4643, 0x90004629, 0xf7fb2001, 
+    0xf1aafd64, 0xb2460001, 0x01f1e00b, 0x46402280, 0xfc77f014, 0x99024607, 0xdd00428f, 0x1e70e003, 
+    0x2e00b246, 0xbf00daf1, 0xb2401c70, 0xeb01a903, 0x55480184, 0xd11242ac, 0xa9032001, 0x0000e00c, 
+    0x00043078, 0x0003622a, 0xdcba01f5, 0xd00305b2, 0xd0030000, 0xd1800000, 0x0184eb01, 0x1c605548, 
+    0x2c04b244, 0x1c68dbb2, 0x2d04b245, 0xa803dbac, 0xff32f7ff, 0xf7fea803, 0x4658fc1d, 0xfa59f7fe, 
+    0x11f4f240, 0x0000f44f, 0xfb5cf7f5, 0xf7f5485c, 0x4601fa65, 0xf44f9001, 0xf7f50000, 0x4858fb03, 
+    0xf7f51c80, 0x4601fa5b, 0xf44f9001, 0xf7f50000, 0x4853faf9, 0xf7f51d00, 0x4601fa51, 0xf44f9001, 
+    0xf7f50000, 0x484efaef, 0xf7f51d80, 0x4601fa47, 0xf44f9001, 0xf7f50000, 0x484afae5, 0xfa34f7f5, 
+    0x90014601, 0x0000f44f, 0xfadcf7f5, 0x30404845, 0xfa2af7f5, 0x90014601, 0x0000f44f, 0xfad2f7f5, 
+    0xf44f4941, 0xf7f50000, 0xb007facd, 0x8ff0e8bd, 0x2301b510, 0x46192200, 0xf7fc483c, 0x2301f820, 
+    0x2102461a, 0xf7fc4839, 0x2300f81a, 0x21042202, 0xf7fc4836, 0x4836f814, 0x1e407800, 0x2204b283, 
+    0x48322170, 0xf80bf7fc, 0x2208231e, 0x7100f643, 0x1c80482e, 0xf803f7fc, 0x22002303, 0x482b4619, 
+    0xf7fb1d00, 0x2302fffc, 0x210c461a, 0x1d004827, 0xfff5f7fb, 0x22042301, 0x48242130, 0xf7fb1d00, 
+    0x2300ffee, 0x21c02206, 0x1d004820, 0xffe7f7fb, 0x22082302, 0x7100f640, 0xf7fb481c, 0x235effe0, 
+    0x217f2200, 0x1c804819, 0xffd9f7fb, 0x22032301, 0x48162108, 0xffd3f7fb, 0x22032300, 0x48132108, 
+    0xffcdf7fb, 0xb510bd10, 0x48102100, 0xf9ccf7f5, 0x0100f242, 0x1c80480d, 0xf9c6f7f5, 0x480b2100, 
+    0xf7f51d00, 0x2301f9c1, 0x21082203, 0xf7fb4807, 0x2300ffb6, 0x21082203, 0xf7fb4804, 0xbd10ffb0, 
+    0xd0030000, 0xd1800008, 0xdcba01f5, 0xd0036146, 0x000384e3, 0x2301b510, 0x0399220e, 0xf7fb48f9, 
+    0x2301ff9e, 0x0319220c, 0xf7fb48f6, 0x2301ff98, 0x02d9220b, 0xf7fb48f3, 0x2301ff92, 0x0299220a, 
+    0xf7fb48f0, 0x2301ff8c, 0x02592209, 0xf7fb48ed, 0x2301ff86, 0x01512208, 0xf7fb48ea, 0x2301ff80, 
+    0x21802207, 0xf7fb48e7, 0x2301ff7a, 0x21402206, 0xf7fb48e4, 0x2301ff74, 0x0399220e, 0x1c8048e1, 
+    0xff6df7fb, 0x220c2301, 0x48de0319, 0xf7fb1c80, 0x2301ff66, 0x02d9220b, 0x1c8048da, 0xff5ff7fb, 
+    0x220a2301, 0x48d70299, 0xf7fb1c80, 0x2301ff58, 0x02592209, 0x1c8048d3, 0xff51f7fb, 0x22082301, 
+    0x48d00151, 0xf7fb1c80, 0x2301ff4a, 0x21802207, 0x1c8048cc, 0xff43f7fb, 0x22062301, 0x48c92140, 
+    0xf7fb1c80, 0x2301ff3c, 0x0399220e, 0x1d0048c5, 0xff35f7fb, 0x220c2301, 0x48c20319, 0xf7fb1d00, 
+    0x2301ff2e, 0x02d9220b, 0x1d0048be, 0xff27f7fb, 0x220a2301, 0x48bb0299, 0xf7fb1d00, 0x2301ff20, 
+    0x02592209, 0x1d0048b7, 0xff19f7fb, 0x22082301, 0x48b40151, 0xf7fb1d00, 0x2301ff12, 0x21802207, 
+    0x1d0048b0, 0xff0bf7fb, 0x22062301, 0x48ad2140, 0xf7fb1d00, 0x2301ff04, 0x0399220e, 0x1d8048a9, 
+    0xfefdf7fb, 0x220c2301, 0x48a60319, 0xf7fb1d80, 0x2301fef6, 0x02d9220b, 0x1d8048a2, 0xfeeff7fb, 
+    0x220a2301, 0x489f0299, 0xf7fb1d80, 0x2301fee8, 0x02592209, 0x1d80489b, 0xfee1f7fb, 0x22082301, 
+    0x48980151, 0xf7fb1d80, 0x2301feda, 0x21802207, 0x1d804894, 0xfed3f7fb, 0x22062301, 0x48912140, 
+    0xf7fb1d80, 0x2301fecc, 0x21202205, 0xf7fb488d, 0x2301fec6, 0x21082203, 0xf7fb488a, 0x2301fec0, 
+    0x2102461a, 0xf7fb4887, 0x2301feba, 0x21202205, 0x1c804884, 0xfeb3f7fb, 0x22032301, 0x48812108, 
+    0xf7fb1c80, 0x2301feac, 0x2102461a, 0x1c80487d, 0xfea5f7fb, 0x22052301, 0x487a2120, 0xf7fb1d00, 
+    0x2301fe9e, 0x21082203, 0x1d004876, 0xfe97f7fb, 0x461a2301, 0x48732102, 0xf7fb1d00, 0x2301fe90, 
+    0x21202205, 0x1d80486f, 0xfe89f7fb, 0x22032301, 0x486c2108, 0xf7fb1d80, 0x2301fe82, 0x2102461a, 
+    0x1d804868, 0xfe7bf7fb, 0x22042301, 0x48652110, 0xfe75f7fb, 0x22022301, 0x48622104, 0xfe6ff7fb, 
+    0x22002301, 0x485f4619, 0xfe69f7fb, 0x22042301, 0x485c2110, 0xf7fb1c80, 0x2301fe62, 0x21042202, 
+    0x1c804858, 0xfe5bf7fb, 0x22002301, 0x48554619, 0xf7fb1c80, 0x2301fe54, 0x21102204, 0x1d004851, 
+    0xfe4df7fb, 0x22022301, 0x484e2104, 0xf7fb1d00, 0x2301fe46, 0x46192200, 0x1d00484a, 0xfe3ff7fb, 
+    0x22042301, 0x48472110, 0xf7fb1d80, 0x2301fe38, 0x21042202, 0x1d804843, 0xfe31f7fb, 0x22002301, 
+    0x48404619, 0xf7fb1d80, 0x2301fe2a, 0x21042202, 0x3008483c, 0xfe23f7fb, 0x461a2301, 0x48392102, 
+    0xf7fb3008, 0x2301fe1c, 0x46192200, 0x30084835, 0xfe15f7fb, 0xb510bd10, 0x46234604, 0x217f2200, 
+    0x300e4830, 0xfe0bf7fb, 0xb510bd10, 0xf04f4604, 0x482c31ff, 0xf7f53032, 0x2100f807, 0x30344829, 
+    0xf802f7f5, 0x2200b2a3, 0x48262101, 0xf7fb3030, 0xbd10fdf6, 0x41f0e92d, 0x460d4604, 0x461f4616, 
+    0x2206b2a3, 0x481f21c0, 0xf7fb3010, 0xb2abfde8, 0x21302204, 0x3010481b, 0xfde1f7fb, 0x2202b2b3, 
+    0x4818210c, 0xf7fb3010, 0xb2bbfdda, 0x21032200, 0x30104814, 0xfdd3f7fb, 0x81f0e8bd, 0x4604b510, 
+    0x2200b2a3, 0x480f2101, 0xf7fb3012, 0xbd10fdc8, 0x4604b510, 0x2001b90c, 0x2000e000, 0x22014603, 
+    0x48082102, 0xf7fb3030, 0xb2a3fdba, 0x21012200, 0x30304804, 0xfdb3f7fb, 0x48022100, 0xf7f43036, 
+    0xbd10ffb3, 0xd0031000, 0x4ffee92d, 0x24004607, 0x4994e07d, 0xfb022202, 0xf7f41004, 0x4683ff9f, 
+    0xe0692600, 0xd10142a6, 0xe0042000, 0xda0142a6, 0xe0001c70, 0xfa4f4630, 0x42a6fa80, 0x2008d101, 
+    0x2002e000, 0x42a64680, 0x2006d101, 0x42a6e008, 0x2001dd01, 0x2000e000, 0x00401a30, 0x0004f1c0, 
+    0xf1a89002, 0xb2450001, 0xeb07e024, 0xeb001046, 0x5d4000c4, 0xd1002801, 0x2d03e01e, 0x2e03db0e, 
+    0x2c03d10c, 0x5d78d10a, 0xf107b938, 0x5d400028, 0xf107b918, 0x5d400050, 0xe00db100, 0x44409802, 
+    0x1b411e40, 0x40882001, 0x0000ea2b, 0xfb80fa0f, 0xb2451e68, 0xdad82d00, 0x1c68bf00, 0xf8dfb245, 
+    0x200091a8, 0x4652464b, 0x90004621, 0xf9fdf7fb, 0xda0f4545, 0x0205eba8, 0xb21101d2, 0x2005eb09, 
+    0xfcbaf022, 0x46032000, 0x46214652, 0x9000e9cd, 0xf920f7fb, 0xb2461c70, 0xdb932e04, 0x22024959, 
+    0x1004fb02, 0xf7f44659, 0x1c60ff2f, 0x2c04b244, 0xaf7ff6ff, 0x8ffee8bd, 0x4ff0e92d, 0x4853b0a3, 
+    0x28507800, 0x2020da01, 0x2010e000, 0x22009002, 0x484f2101, 0xfd03f7fb, 0xfa80fa4f, 0xf7fd2000, 
+    0x2400fef8, 0x2500e03a, 0x42a5e034, 0x2000d101, 0x42a5e004, 0x1c68da01, 0x4628e000, 0xf980fa4f, 
+    0xd10142a5, 0xe0002008, 0x46832002, 0x20004f3e, 0x464a463b, 0x90004621, 0xf9a7f7fb, 0x0001f1ab, 
+    0xe013b246, 0x228001f1, 0xf0144638, 0x4680f8ba, 0x45889902, 0x2001dd01, 0x2000e000, 0xeb01a903, 
+    0xeb011145, 0x558801c4, 0xb2461e70, 0xdae92e00, 0xb2451c68, 0xdbc82d04, 0xb2441c60, 0xdbc22c04, 
+    0xf7ffa803, 0xa803ff21, 0xffdef7fd, 0xf7fd4650, 0xf240feb0, 0xf44f11f4, 0xf7f40000, 0x4821ffb3, 
+    0xfebcf7f4, 0x90014601, 0x0000f44f, 0xff5af7f4, 0x1c80481c, 0xfeb2f7f4, 0x90014601, 0x0000f44f, 
+    0xff50f7f4, 0x1d004817, 0xfea8f7f4, 0x90014601, 0x0000f44f, 0xff46f7f4, 0x1d804812, 0xfe9ef7f4, 
+    0x90014601, 0x0000f44f, 0xff3cf7f4, 0x30084810, 0xfe8af7f4, 0x90014601, 0x0000f44f, 0xff32f7f4, 
+    0x3048480b, 0xfe80f7f4, 0x90014601, 0x0000f44f, 0xff28f7f4, 0xf44f4907, 0xf7f40000, 0xb023ff23, 
+    0x8ff0e8bd, 0xd0031000, 0x00043078, 0x00036226, 0xd1800000, 0xdcba01f5, 0x2300b510, 0x497e220f, 
+    0xf7fb487e, 0x2101fc6c, 0xf7fc2040, 0x2300feed, 0x21022201, 0xf7fb487a, 0xbd10fc62, 0xf04fb508, 
+    0x210f422b, 0x2000f44f, 0xff13f7f4, 0xffe4f7ff, 0x46082100, 0xf944f000, 0x461a2300, 0x48712101, 
+    0xfc4df7fb, 0x46032000, 0x0200f242, 0x90004601, 0xf8ecf000, 0xb508bd08, 0x46082101, 0xf930f000, 
+    0x461a2301, 0x48662102, 0xfc39f7fb, 0x22002301, 0x48644619, 0xfc33f7fb, 0x23172000, 0x7203f247, 
+    0x4102f640, 0xf2409000, 0xf0001084, 0xf001f8cf, 0xbd08fcd2, 0x485cb538, 0x28016800, 0x2000d107, 
+    0x6008495a, 0x0100f640, 0xf0224859, 0x4859fb85, 0xb1508800, 0x20702100, 0xfda7f7fb, 0xf040b280, 
+    0x46210401, 0xf7fb2070, 0xf003fd8a, 0x2001fbdb, 0xfaa2f7fe, 0xf6412000, 0x46020300, 0x90004601, 
+    0xf0002004, 0x2000f8a3, 0xf95ef7fe, 0x494a2000, 0x23007008, 0x21022201, 0x1e804840, 0xfbeff7fb, 
+    0x22082300, 0x48450151, 0xfbe9f7fb, 0x2301e005, 0x02592209, 0xf7fb4841, 0x2206fbe2, 0x48372140, 
+    0xf7fb1d80, 0x2800fbf3, 0x483dd1f1, 0xb1087800, 0xfe67f01a, 0xff3df012, 0xfc05f7ff, 0x22032301, 
+    0x48382108, 0xfbcbf7fb, 0x22032300, 0x48352108, 0xfbc5f7fb, 0xfc97f7fc, 0x220d2301, 0x48280359, 
+    0xf7fb380a, 0x2301fbbc, 0x4923220f, 0x1f004824, 0xfbb5f7fb, 0x220f2300, 0x4821491f, 0xf7fb1f00, 
+    0x2300fbae, 0xf242220d, 0x481d0100, 0xf7fb380a, 0x2000fba6, 0xffe1f7fd, 0xff40f7ff, 0xf00e2001, 
+    0xf00efdbc, 0x2200fcdd, 0x46104611, 0xfe38f7f5, 0x491d2000, 0x78087008, 0xfdfcf7fc, 0x461a2300, 
+    0x480e2101, 0xf7fb380e, 0x2300fb8a, 0x21022201, 0x380e480a, 0xfb83f7fb, 0x22022300, 0x48072104, 
+    0xf7fb380e, 0x2300fb7c, 0x21082203, 0x380e4803, 0xfb75f7fb, 0x0000bd38, 0xffff8000, 0xd0035026, 
+    0xd03c8310, 0xd003529a, 0x00052f84, 0x00052800, 0x00050800, 0x00036268, 0x000361ec, 0xd0035126, 
+    0x00038db0, 0xd0036100, 0x0003626a, 0x41f0e92d, 0x460f4604, 0x461e4615, 0x8018f8dd, 0x485a4621, 
+    0xfd52f7f4, 0x48584639, 0xf7f41c80, 0x4629fd4d, 0x1d004855, 0xfd48f7f4, 0x48534631, 0xf7f41d80, 
+    0x4641fd43, 0x30084850, 0xfd3ef7f4, 0x2301b672, 0x494e220f, 0x300c484c, 0xfb31f7fb, 0x220f2300, 
+    0x4849494a, 0xf7fb300c, 0xb662fb2a, 0x48462100, 0xfd2af7f4, 0x48442100, 0xf7f41c80, 0x2100fd25, 
+    0x1d004841, 0xfd20f7f4, 0x483f2100, 0xf7f41d80, 0x2100fd1b, 0x3008483c, 0xfd16f7f4, 0x81f0e8bd, 
+    0x4604b570, 0x4623460d, 0xf240220a, 0x48364100, 0xf7fb3010, 0x4623fb04, 0xf2402209, 0x48322100, 
+    0xf7fb3010, 0x4623fafc, 0x01512208, 0x3010482e, 0xfaf5f7fb, 0x2202462b, 0x482b2104, 0xf7fb3010, 
+    0xbd70faee, 0x2300b510, 0x21102204, 0xf7fb4828, 0x2301fae6, 0x0399220e, 0x30104823, 0xfadff7fb, 
+    0x22062301, 0x48202140, 0xf7fb3010, 0x2301fad8, 0x46192200, 0xf7fb481f, 0x2301fad2, 0x21102204, 
+    0xf7fb481d, 0x2301facc, 0x21042202, 0xf7fb481a, 0x2301fac6, 0x21082203, 0xf7fb4817, 0x2300fac0, 
+    0x21102204, 0xf7fb4814, 0x2301faba, 0x210f2200, 0x308a480f, 0xfab3f7fb, 0x22042303, 0x480c21f0, 
+    0xf7fb308a, 0x2302faac, 0xf6402208, 0x48087100, 0xf7fb308a, 0x2302faa4, 0x4908220c, 0x308a4804, 
+    0xfa9df7fb, 0x0000bd10, 0xd03c8300, 0xffff8000, 0xd03c8004, 0xd03d0004, 0xd003529a, 0xfffff000, 
+    0x4604b510, 0x2301b934, 0x46192200, 0xf7fb48fe, 0xe041fa86, 0xd1062c01, 0x461a2301, 0x48fa2102, 
+    0xfa7df7fb, 0x2c02e038, 0x2301d106, 0x21042202, 0xf7fb48f5, 0xe02ffa74, 0xd1062c03, 0x22032301, 
+    0x48f12108, 0xfa6bf7fb, 0x2301e026, 0x46192200, 0xf7fb48ed, 0x2100fa64, 0x3000f44f, 0xfce4f7fc, 
+    0x461a2301, 0x48e82102, 0xfa59f7fb, 0xf44f2100, 0xf7fc3000, 0x2301fcd9, 0x21042202, 0xf7fb48e2, 
+    0x2100fa4e, 0x3000f44f, 0xfccef7fc, 0x22032301, 0x48dd2108, 0xfa43f7fb, 0xb510bd10, 0xb9344604, 
+    0x461a2300, 0x48d82101, 0xfa39f7fb, 0x2c01e041, 0x2300d106, 0x21022201, 0xf7fb48d3, 0xe038fa30, 
+    0xd1062c02, 0x22022300, 0x48cf2104, 0xfa27f7fb, 0x2c03e02f, 0x2300d106, 0x21082203, 0xf7fb48ca, 
+    0xe026fa1e, 0x461a2300, 0x48c72101, 0xfa17f7fb, 0xf44f2100, 0xf7fc3000, 0x2300fc97, 0x21022201, 
+    0xf7fb48c1, 0x2100fa0c, 0x3000f44f, 0xfc8cf7fc, 0x22022300, 0x48bc2104, 0xfa01f7fb, 0xf44f2100, 
+    0xf7fc3000, 0x2300fc81, 0x21082203, 0xf7fb48b6, 0xbd10f9f6, 0x4604b510, 0x2301b934, 0x21102204, 
+    0xf7fb48b1, 0xe041f9ec, 0xd1062c01, 0x22052301, 0x48ad2120, 0xf9e3f7fb, 0x2c02e038, 0x2301d106, 
+    0x21402206, 0xf7fb48a8, 0xe02ff9da, 0xd1062c03, 0x22072301, 0x48a42180, 0xf9d1f7fb, 0x2301e026, 
+    0x21102204, 0xf7fb48a0, 0x2100f9ca, 0x3000f44f, 0xfc4af7fc, 0x22052301, 0x489b2120, 0xf9bff7fb, 
+    0xf44f2100, 0xf7fc3000, 0x2301fc3f, 0x21402206, 0xf7fb4895, 0x2100f9b4, 0x3000f44f, 0xfc34f7fc, 
+    0x22072301, 0x48902180, 0xf9a9f7fb, 0xb510bd10, 0xb9344604, 0x22042300, 0x488b2110, 0xf99ff7fb, 
+    0x2c01e041, 0x2300d106, 0x21202205, 0xf7fb4886, 0xe038f996, 0xd1062c02, 0x22062300, 0x48822140, 
+    0xf98df7fb, 0x2c03e02f, 0x2300d106, 0x21802207, 0xf7fb487d, 0xe026f984, 0x22042300, 0x487a2110, 
+    0xf97df7fb, 0xf44f2100, 0xf7fc3000, 0x2300fbfd, 0x21202205, 0xf7fb4874, 0x2100f972, 0x3000f44f, 
+    0xfbf2f7fc, 0x22062300, 0x486f2140, 0xf967f7fb, 0xf44f2100, 0xf7fc3000, 0x2300fbe7, 0x21802207, 
+    0xf7fb4869, 0xbd10f95c, 0x4604b510, 0x2301b93c, 0x46192200, 0x1c804864, 0xf951f7fb, 0x2c01e048, 
+    0x2301d107, 0x2102461a, 0x1c80485f, 0xf947f7fb, 0x2c02e03e, 0x2301d107, 0x21042202, 0x1c80485a, 
+    0xf93df7fb, 0x2c03e034, 0x2301d107, 0x21082203, 0x1c804855, 0xf933f7fb, 0x2301e02a, 0x46192200, 
+    0x1c804851, 0xf92bf7fb, 0xf44f2100, 0xf7fc3080, 0x2301fbab, 0x2102461a, 0x1c80484b, 0xf91ff7fb, 
+    0xf44f2100, 0xf7fc3080, 0x2301fb9f, 0x21042202, 0x1c804845, 0xf913f7fb, 0xf44f2100, 0xf7fc3080, 
+    0x2301fb93, 0x21082203, 0x1c80483f, 0xf907f7fb, 0x461a2300, 0x483d2101, 0xf901f7fb, 0xb510bd10, 
+    0xb93c4604, 0x461a2300, 0x48372101, 0xf7fb1c80, 0xe04df8f6, 0xd1072c01, 0x22012300, 0x48322102, 
+    0xf7fb1c80, 0xe043f8ec, 0xd1072c02, 0x22022300, 0x482d2104, 0xf7fb1c80, 0xe039f8e2, 0xd1072c03, 
+    0x22032300, 0x48282108, 0xf7fb1c80, 0xe02ff8d8, 0x461a2300, 0x48242101, 0xf7fb1c80, 0x2100f8d0, 
+    0x3080f44f, 0xfb50f7fc, 0x22012300, 0x481e2102, 0xf7fb1c80, 0x2100f8c4, 0x3080f44f, 0xfb44f7fc, 
+    0x22022300, 0x48182104, 0xf7fb1c80, 0x2100f8b8, 0x3080f44f, 0xfb38f7fc, 0x22032300, 0x48122108, 
+    0xf7fb1c80, 0x2100f8ac, 0x3080f44f, 0xfb2cf7fc, 0xb510bd10, 0x46234604, 0x21182203, 0xf7fb480c, 
+    0x4623f89e, 0x21182203, 0xf7fb480a, 0x4623f898, 0x21182203, 0xf7fb4808, 0x4623f892, 0x21182203, 
+    0xf7fb4806, 0xbd10f88c, 0xd0034220, 0xd00305cc, 0xd003c016, 0xd003c816, 0xd003d016, 0xd003d816, 
+    0x4604b510, 0x22084623, 0x48f90151, 0xf877f7fb, 0x22084623, 0x48f70151, 0xf871f7fb, 0x22084623, 
+    0x48f50151, 0xf86bf7fb, 0x22084623, 0x48f30151, 0xf865f7fb, 0xb510bd10, 0x46234604, 0xf06f2203, 
+    0x48eb0107, 0xf7fb307c, 0x4623f85a, 0xf06f2203, 0x48e80107, 0xf7fb307c, 0x4623f852, 0xf06f2203, 
+    0x48e50107, 0xf7fb307c, 0x4623f84a, 0xf06f2203, 0x48e20107, 0xf7fb307c, 0xbd10f842, 0x4604b510, 
+    0x220d4623, 0x0100f246, 0x307848d9, 0xf837f7fb, 0x220d4623, 0x0100f246, 0x307848d6, 0xf82ff7fb, 
+    0x220d4623, 0x0100f246, 0x307848d3, 0xf827f7fb, 0x220d4623, 0x0100f246, 0x307848d0, 0xf81ff7fb, 
+    0xb510bd10, 0x46234604, 0xf641220a, 0x48c84100, 0xf7fb3078, 0x4623f814, 0xf641220a, 0x48c54100, 
+    0xf7fb3078, 0x4623f80c, 0xf641220a, 0x48c24100, 0xf7fb3078, 0x4623f804, 0xf641220a, 0x48bf4100, 
+    0xf7fa3078, 0xbd10fffc, 0x4604b510, 0x22074623, 0x48b701d1, 0xf7fa3078, 0x4623fff2, 0x01d12207, 
+    0x307848b4, 0xffebf7fa, 0x22074623, 0x48b201d1, 0xf7fa3078, 0x4623ffe4, 0x01d12207, 0x307848af, 
+    0xffddf7fa, 0xb510bd10, 0x46234604, 0xf247220c, 0x48a70100, 0xf7fa1d00, 0x4623ffd2, 0xf247220c, 
+    0x48a40100, 0xf7fa1d00, 0x4623ffca, 0xf247220c, 0x48a10100, 0xf7fa1d00, 0x4623ffc2, 0xf247220c, 
+    0x489e0100, 0xf7fa1d00, 0xbd10ffba, 0x4604b510, 0x22044623, 0x48962170, 0xf7fa307a, 0x4623ffb0, 
+    0x21702204, 0x307a4893, 0xffa9f7fa, 0x22044623, 0x48912170, 0xf7fa307a, 0x4623ffa2, 0x21702204, 
+    0x307a488e, 0xff9bf7fa, 0xb510bd10, 0x46234604, 0x21072200, 0x307a4886, 0xff91f7fa, 0x22004623, 
+    0x48842107, 0xf7fa307a, 0x4623ff8a, 0x21072200, 0x307a4881, 0xff83f7fa, 0x22004623, 0x487f2107, 
+    0xf7fa307a, 0xbd10ff7c, 0x4604b510, 0x22014623, 0x48772102, 0xf7fa3098, 0x4623ff72, 0x21022201, 
+    0x30984874, 0xff6bf7fa, 0x22014623, 0x48722102, 0xf7fa3098, 0x4623ff64, 0x21022201, 0x3098486f, 
+    0xff5df7fa, 0xb510bd10, 0x46234604, 0x21012200, 0x30984867, 0xff53f7fa, 0x22004623, 0x48652101, 
+    0xf7fa3098, 0x4623ff4c, 0x21012200, 0x30984862, 0xff45f7fa, 0x22004623, 0x48602101, 0xf7fa3098, 
+    0xbd10ff3e, 0x2301b510, 0x21082203, 0xf7fa485c, 0x2000ff0f, 0xffd7f7ff, 0xf7ff2001, 0x2003ffb5, 
+    0xff93f7ff, 0xf7ff2003, 0x2005ff71, 0xff4bf7ff, 0xf7ff2003, 0x2003ff29, 0xff03f7ff, 0xf7ff2000, 
+    0x2003fedd, 0xfeb7f7ff, 0xf7ff2000, 0x2000fe99, 0xfe6ff7ff, 0x22142300, 0x1180f44f, 0x30b44848, 
+    0xfee6f7fa, 0xe92dbd10, 0x460441f0, 0x4616460d, 0xeb004844, 0xeb0020c4, 0x46311705, 0xf7f44638, 
+    0xe8bdf903, 0xb51081f0, 0x46234604, 0xf2402205, 0x483711e0, 0xf7fa3008, 0x4623fef2, 0xf2402205, 
+    0x483411e0, 0xf7fa3008, 0x4623feea, 0xf2402205, 0x483111e0, 0xf7fa3008, 0x4623fee2, 0xf2402205, 
+    0x482e11e0, 0xf7fa3008, 0xbd10feda, 0x2000b570, 0xffd9f7ff, 0xe00d2400, 0xe0072500, 0x1200f240, 
+    0x46204629, 0xffbff7ff, 0xb2c51c68, 0xdbf52d04, 0xb2c41c60, 0xdbef2c04, 0xb510bd70, 0x46234604, 
+    0x21202205, 0xf7fa4820, 0x4623feba, 0x21202205, 0xf7fa481e, 0x4623feb4, 0x21202205, 0xf7fa481c, 
+    0x4623feae, 0x21202205, 0xf7fa481a, 0xbd10fea8, 0x4604b510, 0x220a4623, 0x4100f640, 0xf7fa4812, 
+    0x4623fe9e, 0xf640220a, 0x48104100, 0xfe97f7fa, 0x220a4623, 0x4100f640, 0xf7fa480d, 0x4623fe90, 
+    0xf640220a, 0x480b4100, 0xfe89f7fa, 0x0000bd10, 0xd003c208, 0xd003ca08, 0xd003d208, 0xd003da08, 
+    0xd1800400, 0xd003c3e8, 0xd003c014, 0xd003c814, 0xd003d014, 0xd003d814, 0x4604b510, 0x2001b934, 
+    0xffc6f7ff, 0xf7ff2001, 0xe007ffa8, 0xd1052c01, 0xf7ff2000, 0x2001ffbd, 0xff9ff7ff, 0xb510bd10, 
+    0x46234604, 0xf241220c, 0x48fe0100, 0xfe57f7fa, 0x220c4623, 0x0100f241, 0xf7fa48fb, 0x4623fe50, 
+    0xf241220c, 0x48f90100, 0xfe49f7fa, 0x220c4623, 0x0100f241, 0xf7fa48f6, 0xbd10fe42, 0x4604b510, 
+    0x22054623, 0x48ef2120, 0xf7fa1f00, 0x4623fe38, 0x21202205, 0x1f0048ec, 0xfe31f7fa, 0x22054623, 
+    0x48ea2120, 0xf7fa1f00, 0x4623fe2a, 0x21202205, 0x1f0048e7, 0xfe23f7fa, 0xb510bd10, 0x46234604, 
+    0x21802207, 0x380848df, 0xfe19f7fa, 0x22074623, 0x48dd2180, 0xf7fa3808, 0x4623fe12, 0x21802207, 
+    0x380848da, 0xfe0bf7fa, 0x22074623, 0x48d82180, 0xf7fa3808, 0xbd10fe04, 0x4604b510, 0x22004623, 
+    0x48d02101, 0xf7fa3814, 0x4623fdfa, 0x21012200, 0x381448cd, 0xfdf3f7fa, 0x22004623, 0x48cb2101, 
+    0xf7fa3814, 0x4623fdec, 0x21012200, 0x381448c8, 0xfde5f7fa, 0xb510bd10, 0x46234604, 0x21022201, 
+    0x381448c0, 0xfddbf7fa, 0xf2412100, 0xf7fc0000, 0x4623f85b, 0x21022201, 0x381448bb, 0xfdcff7fa, 
+    0xf2412100, 0xf7fc0000, 0x4623f84f, 0x21022201, 0x381448b6, 0xfdc3f7fa, 0xf2412100, 0xf7fc0000, 
+    0x4623f843, 0x21022201, 0x381448b1, 0xfdb7f7fa, 0xb510bd10, 0x46234604, 0x21042202, 0x381448a9, 
+    0xfdadf7fa, 0xf2412100, 0xf7fc0000, 0x4623f82d, 0x21042202, 0x381448a4, 0xfda1f7fa, 0xf2412100, 
+    0xf7fc0000, 0x4623f821, 0x21042202, 0x3814489f, 0xfd95f7fa, 0xf2412100, 0xf7fc0000, 0x4623f815, 
+    0x21042202, 0x3814489a, 0xfd89f7fa, 0xb510bd10, 0x46234604, 0x21082203, 0x38144892, 0xfd7ff7fa, 
+    0x22034623, 0x48902108, 0xf7fa3814, 0x4623fd78, 0x21082203, 0x3814488d, 0xfd71f7fa, 0x22034623, 
+    0x488b2108, 0xf7fa3814, 0xbd10fd6a, 0x4605b570, 0x2d01460c, 0x2c02d137, 0x2301d118, 0x02412209, 
+    0xf7fa4884, 0x2301fd5c, 0x02592209, 0xf7fa4882, 0x2301fd56, 0x02592209, 0xf7fa4880, 0x2301fd50, 
+    0x02592209, 0xf7fa487e, 0xe036fd4a, 0x22092300, 0x2100f240, 0xf7fa4877, 0x2300fd42, 0xf2402209, 
+    0x48752100, 0xfd3bf7fa, 0x22092300, 0x2100f240, 0xf7fa4872, 0x2300fd34, 0xf2402209, 0x48702100, 
+    0xfd2df7fa, 0x2300e019, 0xf2402209, 0x48692100, 0xfd25f7fa, 0x22092301, 0x48670259, 0xfd1ff7fa, 
+    0x22092300, 0x2100f240, 0xf7fa4864, 0x2301fd18, 0x02592209, 0xf7fa4862, 0xbd70fd12, 0x4604b510, 
+    0x220e4623, 0x0100f244, 0x3010485a, 0xfd07f7fa, 0x220e4623, 0x0100f244, 0x30104857, 0xfcfff7fa, 
+    0x220e4623, 0x0100f244, 0x30104854, 0xfcf7f7fa, 0x220e4623, 0x0100f244, 0x30104851, 0xfceff7fa, 
+    0xb510bd10, 0x46234604, 0x494e220f, 0x30104849, 0xfce5f7fa, 0x220f4623, 0x4847494a, 0xf7fa3010, 
+    0x4623fcde, 0x4947220f, 0x30104844, 0xfcd7f7fa, 0x220f4623, 0x48424943, 0xf7fa3010, 0xbd10fcd0, 
+    0x4604b510, 0x22004623, 0x483f2101, 0xfcc7f7fa, 0x22014623, 0x483c2102, 0xfcc1f7fa, 0x22024623, 
+    0x48392104, 0xfcbbf7fa, 0x22034623, 0x48362108, 0xfcb5f7fa, 0xb510bd10, 0x46234604, 0xf640220a, 
+    0x482c4100, 0xf7fa3818, 0x4623fcaa, 0xf640220a, 0x48294100, 0xf7fa3818, 0x4623fca2, 0xf640220a, 
+    0x48264100, 0xf7fa3818, 0x4623fc9a, 0xf640220a, 0x48234100, 0xf7fa3818, 0xbd10fc92, 0x4604b510, 
+    0xd17d2c00, 0x22092300, 0x2100f240, 0x1f004815, 0xfc85f7fa, 0x220c2301, 0x48120319, 0xf7fa1f00, 
+    0x2301fc7e, 0x0399220e, 0x1f00480e, 0xfc77f7fa, 0x22042300, 0x480f21f0, 0xf7fa1c80, 0x2300fc70, 
+    0xf643220b, 0x48070100, 0xf7fa1e80, 0x2300fc68, 0xf2402209, 0x48042100, 0xf7fa1f00, 0x2300fc60, 
+    0xe013220c, 0xd003c014, 0xd003c814, 0xd003d014, 0xd003d814, 0xd003c2a0, 0xd003caa0, 0xd003d2a0, 
+    0xd003daa0, 0xffff8000, 0xd0034224, 0x0100f241, 0xf7fa48fe, 0x2300fc44, 0xf244220e, 0x48fb0100, 
+    0xfc3df7fa, 0x2204230c, 0x48f921f0, 0xfc37f7fa, 0x22092300, 0x2100f240, 0xf7fa48f6, 0x2301fc30, 
+    0x0319220c, 0xf7fa48f3, 0x2301fc2a, 0x0399220e, 0xf7fa48f0, 0x2300fc24, 0x21f02204, 0xf7fa48ee, 
+    0x2300fc1e, 0xf2402209, 0x48ec2100, 0xfc17f7fa, 0x220c2300, 0x0100f241, 0xf7fa48e8, 0xe000fc10, 
+    0x2300e00d, 0xf244220e, 0x48e40100, 0xfc07f7fa, 0x2204230c, 0x48e221f0, 0xfc01f7fa, 0x2c01e069, 
+    0x2301d167, 0x02592209, 0xf7fa48de, 0x2301fbf8, 0x0319220c, 0xf7fa48db, 0x2300fbf2, 0x03a1220e, 
+    0xf7fa48d8, 0x2300fbec, 0x21f02204, 0xf7fa48d6, 0x2301fbe6, 0xf643220b, 0x48d20100, 0xf7fa1c80, 
+    0x2300fbde, 0x02612209, 0xf7fa48c8, 0x2300fbd8, 0x0321220c, 0xf7fa48c5, 0x2300fbd2, 0x03a1220e, 
+    0xf7fa48c2, 0x2308fbcc, 0x21f02204, 0xf7fa48c0, 0x2301fbc6, 0x02592209, 0xf7fa48be, 0x2301fbc0, 
+    0x0319220c, 0xf7fa48bb, 0x2300fbba, 0x03a1220e, 0xf7fa48b8, 0x2300fbb4, 0x21f02204, 0xf7fa48b6, 
+    0x2300fbae, 0x02612209, 0xf7fa48b4, 0x2300fba8, 0x0321220c, 0xf7fa48b1, 0x2300fba2, 0x03a1220e, 
+    0xf7fa48ae, 0x2308fb9c, 0x21f02204, 0xf7fa48ac, 0xbd10fb96, 0x4604b510, 0x22004623, 0x48a92101, 
+    0xf7fa1c80, 0x4623fb8c, 0x21012200, 0x1c80489f, 0xfb85f7fa, 0x22004623, 0x489e2101, 0xf7fa1c80, 
+    0x4623fb7e, 0x21012200, 0x1c80489c, 0xfb77f7fa, 0xb510bd10, 0x46234604, 0xf242220d, 0x48990100, 
+    0xfb6df7fa, 0x220d4623, 0x0100f242, 0xf7fa488f, 0x4623fb66, 0xf242220d, 0x488e0100, 0xfb5ff7fa, 
+    0x220d4623, 0x0100f242, 0xf7fa488c, 0xbd10fb58, 0x4604b510, 0x2001b964, 0xffdbf7ff, 0xf7ff2001, 
+    0x4620ffb9, 0xfebaf7ff, 0xf7ff2003, 0xe00dfe94, 0xd10b2c01, 0xf7ff2000, 0x2000ffcc, 0xffaaf7ff, 
+    0xf7ff4620, 0x2000feab, 0xfe85f7ff, 0xb570bd10, 0x460d4604, 0x22084623, 0x7100f240, 0x3814487a, 
+    0xfb2df7fa, 0x2204462b, 0x48772170, 0xf7fa3814, 0x2300fb26, 0x2101461a, 0x38144873, 0xfb1ff7fa, 
+    0x22002301, 0x48704619, 0xf7fa3814, 0x2300fb18, 0x2101461a, 0x3814486c, 0xfb11f7fa, 0x22084623, 
+    0x7100f240, 0x38144862, 0xfb09f7fa, 0x2204462b, 0x485f2170, 0xf7fa3814, 0x2300fb02, 0x2101461a, 
+    0x3814485b, 0xfafbf7fa, 0x22002301, 0x48584619, 0xf7fa3814, 0x2300faf4, 0x2101461a, 0x38144854, 
+    0xfaedf7fa, 0x22084623, 0x7100f240, 0x38144852, 0xfae5f7fa, 0x2204462b, 0x484f2170, 0xf7fa3814, 
+    0x2300fade, 0x2101461a, 0x3814484b, 0xfad7f7fa, 0x22002301, 0x48484619, 0xf7fa3814, 0x2300fad0, 
+    0x2101461a, 0x38144844, 0xfac9f7fa, 0x22084623, 0x7100f240, 0x38144842, 0xfac1f7fa, 0x2204462b, 
+    0x483f2170, 0xf7fa3814, 0x2300faba, 0x2101461a, 0x3814483b, 0xfab3f7fa, 0x22002301, 0x48384619, 
+    0xf7fa3814, 0x2300faac, 0x2101461a, 0x38144834, 0xfaa5f7fa, 0xb510bd70, 0x46234604, 0xf04f221d, 
+    0x48325100, 0xfa74f7fa, 0x221d4623, 0x5100f04f, 0x1d00482e, 0xfa6cf7fa, 0x221d4623, 0x5100f04f, 
+    0x3008482a, 0xfa64f7fa, 0x221d4623, 0x5100f04f, 0x300c4826, 0xfa5cf7fa, 0x221f4623, 0x482307d1, 
+    0xfa56f7fa, 0x221f4623, 0x482007d1, 0xf7fa1d00, 0x4623fa4f, 0x07d1221f, 0x3008481c, 0xfa48f7fa, 
+    0x221f4623, 0x481907d1, 0xf7fa300c, 0xbd10fa41, 0x4604b510, 0x220e4623, 0x0100f244, 0x38944812, 
+    0xfa5df7fa, 0x220e4623, 0x0100f244, 0x38944808, 0xfa55f7fa, 0x220e4623, 0x0100f244, 0x38944806, 
+    0xfa4df7fa, 0x220e4623, 0x0000e012, 0xd003c810, 0xd003caa2, 0xd003d010, 0xd003d2a2, 0xd003d810, 
+    0xd003daa2, 0xd003c010, 0xd003c2a2, 0xd18005bc, 0x0100f244, 0xf7fa48fe, 0xbd10fa32, 0x4604b510, 
+    0x22084623, 0x48fb0151, 0xfa29f7fa, 0x22084623, 0x48f90151, 0xfa23f7fa, 0x22084623, 0x48f70151, 
+    0xfa1df7fa, 0x22084623, 0x48f10151, 0xf7fa3094, 0xbd10fa16, 0x4604b510, 0x780048f1, 0x2001b118, 
+    0x700849f0, 0x48f0e003, 0x49ee7800, 0x2c037008, 0x2c04d003, 0x2c05d001, 0x48ead17d, 0xf7ff7800, 
+    0x2000fea7, 0xfd2cf7ff, 0xf7ff2000, 0x2000fd0a, 0xfce4f7ff, 0x48e3b2e1, 0xf7ff7800, 0x2c04fc87, 
+    0x2c05d001, 0x48e1d126, 0xb9788800, 0x22002302, 0x48df2103, 0xf9bcf7fa, 0xf7ff2001, 0x2000ffaf, 
+    0xff76f7ff, 0xf7ff2001, 0xe00eff36, 0x22002301, 0x48d72103, 0xf9acf7fa, 0xf7ff2000, 0x2001ff9f, 
+    0xff66f7ff, 0xf7ff2000, 0x2102ff26, 0xf7ff2003, 0xe01afe8e, 0x461a2300, 0x48cd2103, 0xf998f7fa, 
+    0xf7ff2000, 0x2000ff8b, 0xff52f7ff, 0xf7ff2001, 0x48c4ff12, 0xb9207800, 0x20032102, 0xfe77f7ff, 
+    0x2100e003, 0xf7ff4608, 0x2300fe72, 0x21082203, 0xf7fa48bf, 0x2000f97d, 0xfa45f7ff, 0xf7ff2000, 
+    0x2000fa23, 0xf9bff7ff, 0xf7ff2000, 0x2000f99d, 0xf977f7ff, 0xf7ff2000, 0x2000f9f8, 0xf94ef7ff, 
+    0xf7ff2000, 0x2000f928, 0xf9d0f7ff, 0xf7ff2001, 0x2003f907, 0xe09ce000, 0xf8dbf7ff, 0xf7ff2000, 
+    0x2000fbf6, 0xfbc5f7ff, 0xf7ff2000, 0x2000fb94, 0xfb72f7ff, 0xf7ff2000, 0x2000fb50, 0xfb2ef7ff, 
+    0xf7ff2001, 0x489ffb0c, 0xf7ff7800, 0x2300faf5, 0x21402206, 0xf7fa489f, 0x2301f962, 0x21202205, 
+    0xf7fa489c, 0x2300f95c, 0x21102204, 0xf7fa4899, 0x2300f956, 0x21082203, 0xf7fa4896, 0x2300f950, 
+    0x21042202, 0xf7fa4893, 0x2300f94a, 0x21022201, 0xf7fa4890, 0x2300f944, 0x2101461a, 0xf7fa488d, 
+    0x2300f93e, 0x21402206, 0xf7fa488b, 0x2301f938, 0x01512208, 0xf7fa4888, 0x2301f932, 0x46192200, 
+    0xf7fa4885, 0x2300f92c, 0xf2402209, 0x48832100, 0xf925f7fa, 0x22082300, 0x48800151, 0xf91ff7fa, 
+    0x22072300, 0x487d2180, 0xf919f7fa, 0x22062300, 0x487a2140, 0xf913f7fa, 0x22052300, 0x48772120, 
+    0xf90df7fa, 0x22042300, 0x48742110, 0xf907f7fa, 0x22032300, 0x48712108, 0xf901f7fa, 0x22022300, 
+    0x486e2104, 0xf8fbf7fa, 0x461a2300, 0x486b2101, 0xf8f5f7fa, 0x22092301, 0x48680259, 0xf8eff7fa, 
+    0x22082301, 0x48650151, 0xf8e9f7fa, 0xfa0ef7ff, 0x2c02e12c, 0x485bd1fc, 0xf7ff7800, 0x2000fd89, 
+    0xfc0ef7ff, 0x220c2301, 0x48520319, 0xf7fa3820, 0x2301f8d6, 0x0319220c, 0x3820484f, 0xf8cff7fa, 
+    0x220c2301, 0x484d0319, 0xf7fa3820, 0x2301f8c8, 0x0319220c, 0x30744846, 0xf8c1f7fa, 0xf7ff2003, 
+    0x2000f924, 0xf902f7ff, 0x22032300, 0x48482108, 0xf88ef7fa, 0xf7ff2000, 0x2000f80c, 0xfbc1f7ff, 
+    0xf7ff2001, 0x2001fb9b, 0xf94df7ff, 0xf7ff2000, 0xb2e1f92b, 0x7800483b, 0xfb38f7ff, 0xf7ff2001, 
+    0x2001fb16, 0xfae5f7ff, 0xf7ff2001, 0x2001fab4, 0xfa92f7ff, 0xf7ff2001, 0x2001fa70, 0xfa4ef7ff, 
+    0xf7ff2001, 0x482ffa2c, 0xf7ff7800, 0x2000fa15, 0xf806f7ff, 0x22062301, 0x482f2140, 0xf87ff7fa, 
+    0x22082300, 0x482c0151, 0xf879f7fa, 0x22002301, 0x48294619, 0xf873f7fa, 0x22092300, 0x48270221, 
+    0xf86df7fa, 0x22082300, 0x48240151, 0xf867f7fa, 0x22072300, 0x48212180, 0xf861f7fa, 0x22062300, 
+    0x481e2140, 0xf85bf7fa, 0x22062301, 0x48192140, 0xf855f7fa, 0x22052300, 0x48162120, 0xf84ff7fa, 
+    0x22042300, 0x48132110, 0xf849f7fa, 0x22032301, 0x48102108, 0xf843f7fa, 0x22022300, 0x480d2104, 
+    0xf83df7fa, 0x22012300, 0x480a2102, 0x0000e018, 0xd003da0e, 0xd003c2a2, 0xd003caa2, 0xd003d2a2, 
+    0x0003625c, 0x000384d5, 0x000384d4, 0x000361cc, 0xd1800400, 0xd0034228, 0xd03c830e, 0xd03c804a, 
+    0xf81df7fa, 0x22002301, 0x48fe4619, 0xf817f7fa, 0x22002301, 0x48fc4619, 0xf811f7fa, 0x220f2301, 
+    0x48f949fa, 0xf7fa300c, 0x2301f80a, 0x01512208, 0xf7fa48f7, 0x2300f804, 0x21082203, 0xf7f948f4, 
+    0x2301fffe, 0x21202205, 0xf7f948f2, 0x2301fff8, 0x21102204, 0xf7f948ef, 0x2301fff2, 0x21082203, 
+    0xf7f948ec, 0x2301ffec, 0x21042202, 0xf7f948e9, 0x2301ffe6, 0x46192200, 0xf7f948e6, 0x2300ffe0, 
+    0x49e2220f, 0x300c48e0, 0xffd9f7f9, 0x461a2300, 0x48dd2101, 0xffd3f7f9, 0x22072301, 0x48dd2180, 
+    0xffcdf7f9, 0x22062301, 0x48da2140, 0xffc7f7f9, 0x22082300, 0x48d60151, 0xffc1f7f9, 0x22032301, 
+    0x48d32108, 0xffbbf7f9, 0xf8e0f7ff, 0xb510bd10, 0x46234604, 0x21102204, 0xf7f948cf, 0x4623ffb0, 
+    0x21102204, 0xf7f948cd, 0x4623ffaa, 0x21102204, 0xf7f948cb, 0x4623ffa4, 0x21102204, 0xf7f948c9, 
+    0xbd10ff9e, 0xf04fb510, 0x2109422b, 0x2000f44f, 0xfa4ff7f3, 0xfa96f7f3, 0x11f4f240, 0xf7f32001, 
+    0x48c1fa81, 0x20017801, 0xfa2cf7f3, 0x200149bf, 0xfa28f7f3, 0x22082300, 0x3100f240, 0xf7f948bc, 
+    0x2000ff7e, 0x80c849bb, 0x80488088, 0x46088008, 0xf846f7fd, 0xf7f348b0, 0xf020f971, 0x46210420, 
+    0xf7f348b5, 0x48acf971, 0xf7f31c80, 0x4604f967, 0x48b14621, 0xf7f31c80, 0x2004f967, 0xfe5ff7fe, 
+    0xf7ff2001, 0x2100ffa4, 0xf7fb2040, 0x2000f9dd, 0xff9df7ff, 0xb510bd10, 0x461a2300, 0x48a72101, 
+    0xff4df7f9, 0x1f8048a5, 0xf948f7f3, 0x22002302, 0x48a22107, 0xf7f91e80, 0x2302ff42, 0x21702204, 
+    0x1e80489e, 0xff3bf7f9, 0x22082302, 0x7100f240, 0x1e80489a, 0xff33f7f9, 0x220c2302, 0x0100f247, 
+    0x1e804896, 0xff2bf7f9, 0x48942100, 0xf7f31f00, 0x2301f92b, 0x46192200, 0xf7f94890, 0x2001ff20, 
+    0xff65f7ff, 0x20402100, 0xf99ef7fb, 0xf7ff2000, 0xbd10ff5e, 0x2300b510, 0xf241220c, 0x487e0100, 
+    0xf7f9385c, 0x2300ff0c, 0xf241220c, 0x487b0100, 0xf7f9385c, 0x2300ff04, 0xf241220c, 0x48780100, 
+    0xf7f9385c, 0x2300fefc, 0xf241220c, 0x48750100, 0xf7f9385c, 0x2300fef4, 0xf240220a, 0x486e4100, 
+    0xf7f93838, 0x2300feec, 0xf240220a, 0x486b4100, 0xf7f93838, 0x2300fee4, 0xf240220a, 0x48684100, 
+    0xf7f93838, 0x2300fedc, 0xf240220a, 0x48654100, 0xf7f93838, 0x2300fed4, 0xf242220d, 0x485e0100, 
+    0xf7f91f00, 0x2300fecc, 0xf242220d, 0x485b0100, 0xf7f91f00, 0x2300fec4, 0xf242220d, 0x48580100, 
+    0xf7f91f00, 0x2300febc, 0xf242220d, 0x48550100, 0xf7f91f00, 0x2300feb4, 0x2101461a, 0xf7f9484e, 
+    0x2300feae, 0x2101461a, 0xf7f9484c, 0x2300fea8, 0x2101461a, 0xf7f9484a, 0x2300fea2, 0x2101461a, 
+    0xf7f94848, 0x2300fe9c, 0x21202205, 0xf7f94842, 0x2300fe96, 0x21202205, 0xf7f94840, 0x2300fe90, 
+    0x21202205, 0xf7f9483e, 0x2300fe8a, 0x21202205, 0xf7f9483c, 0x2300fe84, 0x2107461a, 0x1c804836, 
+    0xfe7df7f9, 0x461a2300, 0x48342107, 0xf7f91c80, 0x2300fe76, 0x2107461a, 0x1c804831, 0xfe6ff7f9, 
+    0x461a2300, 0x482f2107, 0xf7f91c80, 0xbd10fe68, 0x2300b510, 0xf2402208, 0x48313100, 0xfe5ff7f9, 
+    0x22082300, 0x3100f240, 0xf7f9482e, 0x2300fe58, 0xf2402208, 0x482c3100, 0xfe51f7f9, 0x22082300, 
+    0x3100f240, 0xf7f94829, 0x2000fe4a, 0xf825f7ff, 0x22052300, 0x48222160, 0xf7f91d00, 0x2300fe40, 
+    0x21602205, 0x1d00481f, 0xfe39f7f9, 0x22052300, 0x481d2160, 0xf7f91d00, 0x2300fe32, 0x21602205, 
+    0x1d00481a, 0xfe2bf7f9, 0x22042300, 0x48142110, 0xf7f91d00, 0x2300fe24, 0x21102204, 0x1d004811, 
+    0x0000e026, 0xd0034228, 0xd03c8300, 0xffff8000, 0xd0039000, 0xd03c804a, 0xd003c286, 0xd003ca86, 
+    0xd003d286, 0xd003da86, 0x000361ee, 0xdcba01f5, 0xd0035022, 0x00036296, 0xd003e286, 0xd00305cc, 
+    0xd003c008, 0xd003c808, 0xd003d008, 0xd003d808, 0xfdf5f7f9, 0x22042300, 0x48f82110, 0xfdeff7f9, 
+    0x22042300, 0x48f62110, 0xfde9f7f9, 0x22062300, 0x48f42140, 0xfde3f7f9, 0x22062300, 0x48f22140, 
+    0xfdddf7f9, 0x22062300, 0x48ec2140, 0xf7f91d00, 0x2300fdd6, 0x21402206, 0x1d0048e9, 0xfdcff7f9, 
+    0x22042300, 0x48e72110, 0xf7f93008, 0x2300fdc8, 0x21102204, 0x300848e4, 0xfdc1f7f9, 0x22042300, 
+    0x48de2110, 0xf7f9300c, 0x2300fdba, 0x21102204, 0x300c48db, 0xfdb3f7f9, 0x22052300, 0x48d92120, 
+    0xf7f93008, 0x2300fdac, 0x21202205, 0x300848d6, 0xfda5f7f9, 0x22052300, 0x48d02120, 0xf7f9300c, 
+    0x2300fd9e, 0x21202205, 0x300c48cd, 0xfd97f7f9, 0x22062300, 0x48cb2140, 0xf7f93008, 0x2300fd90, 
+    0x21402206, 0x300848c8, 0xfd89f7f9, 0x22062300, 0x48c22140, 0xf7f9300c, 0x2300fd82, 0x21402206, 
+    0x300c48bf, 0xfd7bf7f9, 0xb508bd10, 0x48c049bf, 0xff7af7f2, 0x220e2301, 0x48be0399, 0xfd6ff7f9, 
+    0xf7fe2004, 0x2004fadd, 0xfb74f7fe, 0xfdcaf7ff, 0xf647200f, 0xf2470395, 0xf6400202, 0x90000102, 
+    0x1045f243, 0xfa02f7fe, 0x48b32100, 0xff5cf7f2, 0x461a2300, 0x48b12103, 0xfd2af7f9, 0xf7ff2000, 
+    0x2300fb1d, 0x21042202, 0xf7f948ad, 0x2300fd48, 0x21042202, 0xf7f948ab, 0x2300fd42, 0x21042202, 
+    0xf7f948a9, 0x2300fd3c, 0x21042202, 0xf7f948a7, 0x48a7fd36, 0x28017800, 0x2301d107, 0xf643220b, 
+    0x48980100, 0xf7f91c80, 0x2303fd2a, 0x2118461a, 0xf7f94894, 0x2303fd24, 0x2118461a, 0xf7f94892, 
+    0x2303fd1e, 0x2118461a, 0x1d00488c, 0xfd17f7f9, 0x461a2303, 0x488a2118, 0xf7f91d00, 0x2303fd10, 
+    0x2118461a, 0x3044488e, 0xfd09f7f9, 0x461a2303, 0x488c2118, 0xf7f93044, 0x2303fd02, 0x2118461a, 
+    0x30444889, 0xfcfbf7f9, 0x461a2303, 0x48872118, 0xf7f93044, 0x4887fcf4, 0xf7ff7800, 0xf7fff999, 
+    0xf7fffe87, 0xbd08fdd7, 0x4604b570, 0x302e487c, 0xfee4f7f2, 0x300ff364, 0x4629b205, 0xf7f2487e, 
+    0xbd70fee3, 0x4604b510, 0x220d4623, 0x486d497b, 0xf7f91e80, 0x4623fcd4, 0x4978220d, 0x1e80486a, 
+    0xfccdf7f9, 0x220d4623, 0x48644974, 0xf7f91c80, 0x4623fcc6, 0x4971220d, 0x1c804861, 0xfcbff7f9, 
+    0xb510bd10, 0x46234604, 0x496c220d, 0x380c485d, 0xfcb5f7f9, 0x220d4623, 0x485b4968, 0xf7f9380c, 
+    0x4623fcae, 0x4965220d, 0x38084854, 0xfca7f7f9, 0x220d4623, 0x48524961, 0xf7f93808, 0xbd10fca0, 
+    0x4604b510, 0x220a4623, 0x4100f641, 0x380c484d, 0xfc95f7f9, 0x220a4623, 0x4100f641, 0x380c484a, 
+    0xfc8df7f9, 0x220a4623, 0x4100f641, 0x38084843, 0xfc85f7f9, 0x220a4623, 0x4100f641, 0x38084840, 
+    0xfc7df7f9, 0xb510bd10, 0x2c014604, 0x2004d10c, 0xffd6f7ff, 0xf7ff2004, 0x2005ffb4, 0xff92f7ff, 
+    0xf7fe2003, 0xe00bfbc6, 0xf7ff2004, 0x2000ffc9, 0xffa7f7ff, 0xf7ff2000, 0x2000ff85, 0xfbb9f7fe, 
+    0xb510bd10, 0x46234604, 0x21e02205, 0x1d80482d, 0xfc55f7f9, 0x22054623, 0x482b21e0, 0xf7f91d80, 
+    0x4623fc4e, 0x21e02205, 0x300a4824, 0xfc47f7f9, 0x22054623, 0x482221e0, 0xf7f9300a, 0xbd10fc40, 
+    0x4604b510, 0x22004623, 0x48252103, 0xf7f9304a, 0x4623fc36, 0x21032200, 0x304a4822, 0xfc2ff7f9, 
+    0x22004623, 0x48202103, 0xf7f9304a, 0x4623fc28, 0x21032200, 0x304a481d, 0xfc21f7f9, 0xb510bd10, 
+    0x46234604, 0x21102204, 0x30484815, 0xfc17f7f9, 0x22044623, 0x48132110, 0xf7f93048, 0x4623fc10, 
+    0x21102204, 0x30484810, 0xfc09f7f9, 0x22044623, 0x480e2110, 0xf7f93048, 0xbd10fc02, 0xd003d00c, 
+    0xd003d80c, 0xd003c010, 0xd003c810, 0xffffbbb5, 0xd03c80b8, 0xd03c830c, 0xd0034224, 0xd1800400, 
+    0xd003c25c, 0xd003ca5c, 0xd003d25c, 0xd003da5c, 0x000384d5, 0x000384d4, 0xd003e28a, 0xffffe000, 
+    0x4604b510, 0x22094623, 0x6100f640, 0xf7f9487b, 0x4623fbd6, 0xf6402209, 0x48796100, 0xfbcff7f9, 
+    0x22094623, 0x6100f640, 0xf7f94876, 0x4623fbc8, 0xf6402209, 0x48746100, 0xfbc1f7f9, 0xb510bd10, 
+    0x46234604, 0x4971220e, 0x300a486c, 0xfbb7f7f9, 0x220e4623, 0x486a496d, 0xf7f9300a, 0x4623fbb0, 
+    0x496a220e, 0x300a4867, 0xfba9f7f9, 0x220e4623, 0x48654966, 0xf7f9300a, 0x2300fba2, 0x2103461a, 
+    0x300e485e, 0xfb9bf7f9, 0x22002301, 0x485b2103, 0xf7f9300e, 0x2300fb94, 0x2103461a, 0x300e4858, 
+    0xfb8df7f9, 0x22002301, 0x48552103, 0xf7f9300e, 0x2300fb86, 0x2103461a, 0x300e4852, 0xfb7ff7f9, 
+    0x22002301, 0x484f2103, 0xf7f9300e, 0x2300fb78, 0x2103461a, 0x300e484c, 0xfb71f7f9, 0x22002301, 
+    0x48492103, 0xf7f9300e, 0xbd10fb6a, 0x4604b570, 0x4847460d, 0x20c4eb00, 0x1605eb00, 0xf7f24630, 
+    0xb280fd5d, 0xb570bd70, 0x78004842, 0x220eb958, 0x483a493e, 0xf7f93010, 0xb108fb69, 0xe0002001, 
+    0x46042000, 0x483be028, 0xb9587840, 0x4937220e, 0x30104833, 0xfb5af7f9, 0x2001b108, 0x2000e000, 
+    0xe0194604, 0x78804833, 0x220eb958, 0x482d492f, 0xf7f93010, 0xb108fb4b, 0xe0002001, 0x46042000, 
+    0x220ee00a, 0x48284929, 0xf7f93010, 0xb108fb3f, 0xe0002001, 0x46042000, 0x78004826, 0xd10b2801, 
+    0x4922220e, 0x3010481d, 0xfb30f7f9, 0x2001b108, 0x2000e000, 0xe02a4605, 0x7840481e, 0xd10b2801, 
+    0x491a220e, 0x30104816, 0xfb20f7f9, 0x2001b108, 0x2000e000, 0xe01a4605, 0x78804816, 0xd10b2801, 
+    0x4912220e, 0x3010480f, 0xfb10f7f9, 0x2001b108, 0x2000e000, 0xe00a4605, 0x490c220e, 0x3010480a, 
+    0xfb04f7f9, 0x2001b108, 0x2000e000, 0x19604605, 0xdb012802, 0xbd702001, 0xe7fc2000, 0xd003c2a4, 
+    0xd003caa4, 0xd003d2a4, 0xd003daa4, 0xffffc000, 0xd003c3e8, 0x00036254, 0x41f0e92d, 0x460d4604, 
+    0x461f4616, 0x2206b2a3, 0x483021c0, 0xfac7f7f9, 0x2204b2ab, 0x482d2130, 0xfac1f7f9, 0x2202b2b3, 
+    0x482a210c, 0xfabbf7f9, 0x2200b2bb, 0x48272103, 0xfab5f7f9, 0x81f0e8bd, 0x2301b510, 0x0299220a, 
+    0xf7f94823, 0x2308faac, 0xf2402204, 0x482011f0, 0xfaa5f7f9, 0x461a2301, 0x481d2102, 0xfa9ff7f9, 
+    0x22022301, 0x481a2104, 0xfa99f7f9, 0xb510bd10, 0x461a2301, 0x48172102, 0xfa91f7f9, 0x03082101, 
+    0xfd12f7fa, 0xffd8f7ff, 0xb510bd10, 0x48102100, 0xf7f23016, 0x2100fc89, 0x3018480d, 0xfc84f7f2, 
+    0x480b2100, 0xf7f23012, 0x2100fc7f, 0x30144808, 0xfc7af7f2, 0x48062100, 0xf7f2301a, 0x2100fc75, 
+    0x301c4803, 0xfc70f7f2, 0x0000bd10, 0xd0030484, 0xd0036100, 0xd03c8310, 0x4604b510, 0x2301b934, 
+    0x2102461a, 0xf7f948f9, 0xe01afa5a, 0xd1072c01, 0x461a2301, 0x48f52102, 0xf7f93020, 0xe010fa50, 
+    0xd1072c02, 0x461a2301, 0x48f02102, 0xf7f93040, 0xe006fa46, 0x461a2301, 0x48ec2102, 0xf7f93060, 
+    0xbd10fa3e, 0x4604b51c, 0x90002000, 0xf82d9001, 0xf9bd0014, 0x48e51000, 0xf7f21c80, 0xf9bdfc35, 
+    0x48e21002, 0xf7f23022, 0xf9bdfc2f, 0x48df1004, 0xf7f23042, 0xf9bdfc29, 0x48dc1006, 0xf7f23062, 
+    0xbd1cfc23, 0x48dab570, 0x0000f990, 0x2204b283, 0x48d62130, 0xf7f93872, 0x2304fa12, 0x210f2200, 
+    0x387248d2, 0xfa0bf7f9, 0x22062301, 0x48cf2140, 0xf7f93872, 0x48cdfa04, 0xf7f2386e, 0x4605fbff, 
+    0x387048ca, 0xfbfaf7f2, 0x401ff365, 0x10644604, 0xbd704620, 0x4604b510, 0x48c44621, 0xf7f23880, 
+    0xbd10fbf3, 0x4604b510, 0x2301b934, 0x46192200, 0xf7f948be, 0xe01af9e4, 0xd1072c01, 0x22002301, 
+    0x48ba4619, 0xf7f93020, 0xe010f9da, 0xd1072c02, 0x22002301, 0x48b54619, 0xf7f93040, 0xe006f9d0, 
+    0x22002301, 0x48b14619, 0xf7f93060, 0xbd10f9c8, 0x2101b510, 0xf7fa0388, 0xf640fc47, 0x48ab01c9, 
+    0xf7f2387c, 0xf241fbc1, 0x48a81101, 0xf7f2387a, 0x2000fbbb, 0xffc6f7ff, 0xf7ff2001, 0x2002ffc3, 
+    0xffc0f7ff, 0xf7ff2003, 0x2301ffbd, 0x21402206, 0x1c80489e, 0xf9a3f7f9, 0x22062301, 0x489b2140, 
+    0xf7f93022, 0x2301f99c, 0x21402206, 0x30424897, 0xf995f7f9, 0x22062301, 0x48942140, 0xf7f93062, 
+    0x2301f98e, 0x21042202, 0x387e4890, 0xf987f7f9, 0xb570bd10, 0x0102f640, 0x3000f44f, 0xfc72f7f2, 
+    0x1d80488a, 0xfb7af7f2, 0x48884605, 0xf7f21d00, 0xeb05fb75, 0x46214400, 0x3000f44f, 0xfc12f7f2, 
+    0x30264882, 0xfb6af7f2, 0x48804605, 0xf7f23024, 0xeb05fb65, 0x46214400, 0x3000f44f, 0xfc02f7f2, 
+    0x3046487a, 0xfb5af7f2, 0x48784605, 0xf7f23044, 0xeb05fb55, 0x46214400, 0x3000f44f, 0xfbf2f7f2, 
+    0x30664872, 0xfb4af7f2, 0x48704605, 0xf7f23064, 0xeb05fb45, 0x46214400, 0x3000f44f, 0xfbe2f7f2, 
+    0xf7ff20f0, 0xbd70ff47, 0x4605b570, 0x2d04460e, 0x24ffd101, 0x2001e010, 0xf08040a8, 0xb204000f, 
+    0xd1062e01, 0xeb002001, 0xf0401004, 0xb204000e, 0xea44e002, 0xb2041004, 0x2200b2a3, 0x485b21ff, 
+    0xf7f93880, 0xbd70f91c, 0xf640b570, 0xf44f0102, 0xf7f23000, 0x4855fc07, 0xf7f21d80, 0x4605fb0f, 
+    0x1d004852, 0xfb0af7f2, 0x4400eb05, 0xf44f4621, 0xf7f23000, 0x484dfba7, 0xf7f23026, 0x4605faff, 
+    0x3024484a, 0xfafaf7f2, 0x4400eb05, 0xf44f4621, 0xf7f23000, 0x4845fb97, 0xf7f23046, 0x4605faef, 
+    0x30444842, 0xfaeaf7f2, 0x4400eb05, 0xf44f4621, 0xf7f23000, 0x483dfb87, 0xf7f23066, 0x4605fadf, 
+    0x3064483a, 0xfadaf7f2, 0x4400eb05, 0xf44f4621, 0xf7f23000, 0x2100fb77, 0xf9904835, 0xf7ff0000, 
+    0xbd70ff93, 0xf640b510, 0xf44f0103, 0xf7f23000, 0x2301fbb9, 0x46192200, 0x3880482c, 0xf8bff7f9, 
+    0x461a2301, 0x48292102, 0xf7f93880, 0x2301f8b8, 0x21042202, 0x38804825, 0xf8b1f7f9, 0x22032301, 
+    0x48222108, 0xf7f93880, 0xbd10f8aa, 0x47f0e92d, 0x460c4605, 0x1c80481d, 0x1845eb00, 0xeb001e80, 
+    0x2c001945, 0x2031db01, 0x2011e000, 0x48194682, 0x28037800, 0x4818d003, 0x28018800, 0x2c00d106, 
+    0x2011db01, 0x2031e000, 0xe0144682, 0x78004811, 0xd0032805, 0x7800480f, 0xd1062804, 0xdb012c00, 
+    0xe0002031, 0x46822011, 0x2c00e005, 0x2031db01, 0x2011e000, 0x48084682, 0xb9b08800, 0x78004805, 
+    0xd10b2804, 0xb20400a0, 0x0000e024, 0xd0030880, 0x000362b1, 0x0003626a, 0x000361cc, 0x780048fa, 
+    0xd1172805, 0xb2040060, 0x48f7e014, 0x28047800, 0x0060d102, 0xe005b204, 0x780048f3, 0xd1012805, 
+    0xb2040060, 0xdb022c00, 0x0000f24c, 0xf244e001, 0xb2070000, 0x28001060, 0x4601db01, 0x4241e000, 
+    0x48eab20c, 0xb9708800, 0x46402100, 0xfa3cf7f2, 0xe0052600, 0x46404651, 0xfa36f7f2, 0xb2061c70, 
+    0xdbf742a6, 0x48e2e024, 0xb9207800, 0xf99048e1, 0x42850000, 0x2301d005, 0x21402206, 0xf7f94640, 
+    0x0060f81e, 0x2100b204, 0xf7f248db, 0x4639fa1d, 0x1c8048d9, 0xfa18f7f2, 0xe0072600, 0x22022301, 
+    0x46482104, 0xf80bf7f9, 0xb2061c70, 0xdbf542a6, 0x87f0e8bd, 0x4604b510, 0x2c01b124, 0x2c02d011, 
+    0xe01dd12d, 0x22042306, 0x48cb21f0, 0xf7f81f00, 0x2303fff6, 0x21702204, 0x1e8048c7, 0xffeff7f8, 
+    0x2307e01d, 0x21f02204, 0x1f0048c3, 0xffe7f7f8, 0x22042302, 0x48c02170, 0xf7f81e80, 0xe00effe0, 
+    0x22042308, 0x48bc21f0, 0xf7f81f00, 0x2302ffd8, 0x21702204, 0x1e8048b8, 0xffd1f7f8, 0xbf00bf00, 
+    0x22042305, 0x48b421f0, 0xf7f81f00, 0x2302ffc8, 0x21702204, 0x1e8048b0, 0xffc1f7f8, 0x220c2305, 
+    0x48ad49ae, 0xf7f81f00, 0x2302ffba, 0xf247220c, 0x48a90100, 0xf7f81e80, 0xbd10ffb2, 0x4604b510, 
+    0xd26b2c08, 0xf004e8df, 0x2b1e1104, 0x5e524538, 0x2163f245, 0x1f0048a0, 0xf9a6f7f2, 0x4124f242, 
+    0x1e80489d, 0xf9a0f7f2, 0xf247e058, 0x489a4185, 0xf7f21f00, 0xf241f999, 0x48973113, 0xf7f21e80, 
+    0xe04bf993, 0x7187f247, 0x1f004893, 0xf98cf7f2, 0x3113f241, 0x1e804890, 0xf986f7f2, 0xf247e03e, 
+    0x488d4187, 0xf7f21f00, 0xf241f97f, 0x488a3113, 0xf7f21e80, 0xe031f979, 0x418cf240, 0x1f004886, 
+    0xf972f7f2, 0x4124f242, 0x1e804883, 0xf96cf7f2, 0xf247e024, 0x48804187, 0xf7f21f00, 0xf241f965, 
+    0x487d3113, 0xf7f21e80, 0xe017f95f, 0x487a497c, 0xf7f21f00, 0xf240f959, 0x48772102, 0xf7f21e80, 
+    0xe00bf953, 0x48744977, 0xf7f21f00, 0xf240f94d, 0x48711101, 0xf7f21e80, 0xbf00f947, 0xbd10bf00, 
+    0x4605b570, 0x210f2200, 0x1f00486b, 0xff4ef7f8, 0x1b60b244, 0x2c0fb244, 0x240fdd01, 0x2c00e002, 
+    0x2400da00, 0x2200b2a3, 0x4863210f, 0xf7f81f00, 0xbd70ff26, 0x4604b510, 0x2206b2a3, 0x485e21c0, 
+    0xf7f81f80, 0xbd10ff1c, 0x41f0e92d, 0x460d4604, 0x461f4616, 0xb2abb944, 0xf2402200, 0x485631ff, 
+    0xf7f83086, 0xe01dff0c, 0xd1082c01, 0x2200b2ab, 0x31fff240, 0x30a64850, 0xff01f7f8, 0x2c02e012, 
+    0xb2abd108, 0xf2402200, 0x484b31ff, 0xf7f830c6, 0xe007fef6, 0x2200b2ab, 0x31fff240, 0x30e64846, 
+    0xfeedf7f8, 0xb2b3b944, 0xf240220a, 0x48424100, 0xf7f83086, 0xe01bfee4, 0xd1072c01, 0x220ab2b3, 
+    0x483d02a1, 0xf7f830a6, 0xe011feda, 0xd1072c02, 0x220ab2b3, 0x48380261, 0xf7f830c6, 0xe007fed0, 
+    0x220ab2b3, 0x4100f240, 0x30e64833, 0xfec7f7f8, 0x81f0e8bd, 0x41f0e92d, 0x46144607, 0xf8dd461d, 
+    0xf1b88018, 0xd10b0f00, 0x46082100, 0xeb751a61, 0xda010000, 0xe0012001, 0x30fff04f, 0xe0394606, 
+    0x2108f245, 0x1b092000, 0xda0241a8, 0x0609f06f, 0xf244e030, 0x1a610100, 0x0000f175, 0xf06fdb02, 
+    0xe0270603, 0x0100f242, 0xf1751a61, 0xdb020000, 0x0601f06f, 0x2100e01e, 0x1a614608, 0x0000eb75, 
+    0xf06fdb02, 0xe0150601, 0x13484917, 0x41a81b09, 0x2602da01, 0x4915e00e, 0x1b091388, 0xda0141a8, 
+    0xe0072602, 0x13c84912, 0x41a81b09, 0x2604da01, 0x260ae000, 0xb2b3b93f, 0x490e220b, 0x30864806, 
+    0xfe6df7f8, 0xe017e032, 0x0003626a, 0x000361cc, 0x000361ee, 0x000362b1, 0xd0030808, 0xfffff000, 
+    0xffff96a7, 0xffffb8c9, 0xffffe000, 0xffffc000, 0xffffadf8, 0xfffff800, 0xd1062f01, 0x220bb2b3, 
+    0x4880497f, 0xfe4bf7f8, 0x2f02e010, 0xb2b3d107, 0x497b220b, 0x3020487b, 0xfe41f7f8, 0xb2b3e006, 
+    0x4977220b, 0x30404877, 0xfe39f7f8, 0x81f0e8bd, 0xf244b510, 0x4873310f, 0xf7f23898, 0x2307f835, 
+    0xf6402208, 0x486f7100, 0xf7f838aa, 0x2301fe28, 0x46192200, 0x382e486b, 0xfe21f7f8, 0x22002301, 
+    0x48684619, 0xf7f8380e, 0x2301fe1a, 0x46192200, 0x30124864, 0xfe13f7f8, 0x22002301, 0x48614619, 
+    0xf7f83032, 0xbd10fe0c, 0x4604b510, 0x2200b2a3, 0x485c2103, 0xf7f8384e, 0x4620fe02, 0xfea4f01b, 
+    0xb570bd10, 0x460d4604, 0x2200b2a3, 0x71fff647, 0x38a64854, 0xfdf3f7f8, 0x48524629, 0xf7f138a4, 
+    0xbd70fff3, 0x2301b510, 0x494f220f, 0x38ae484d, 0xfde5f7f8, 0x220f2300, 0x484a494b, 0xf7f838ae, 
+    0xbd10fdde, 0x4604b570, 0xfd0cf7ff, 0x46082100, 0xf831f7fc, 0xfbb6f7ff, 0x48444605, 0x14287004, 
+    0xf7ffb229, 0x4841ffce, 0x0000f990, 0xfb64f7ff, 0xf990483e, 0xf7ff0000, 0x483cfbd5, 0x0000f990, 
+    0xffb2f7ff, 0x20012100, 0xf865f7fc, 0x200c2100, 0xffbff7fb, 0x46082101, 0xf80df7fc, 0xfc94f7ff, 
+    0xe92dbd70, 0x460543f8, 0xa0312400, 0x90006800, 0x483046a1, 0x0000f990, 0xf81d1ec0, 0x22003000, 
+    0x482821ff, 0xf7f83848, 0x2704fd9a, 0x40b82001, 0x08fff000, 0xd03a2d00, 0xe0052600, 0xfb72f7ff, 
+    0x44044138, 0xb2c61c70, 0xdbf74546, 0xf44f4621, 0xf7f23080, 0x481ff827, 0x0000f990, 0xd20a2806, 
+    0xf000e8df, 0x0a0b0c09, 0xf04f0603, 0xe0080902, 0x0901f04f, 0xbf00e005, 0xbf00bf00, 0x0900f04f, 
+    0xbf00bf00, 0x49131220, 0x1000f991, 0xf81d1ec9, 0x43481001, 0x0117f1c9, 0xf3c04108, 0x46230409, 
+    0xf2402200, 0x480731ff, 0xf7f83846, 0x462bfd58, 0x21042202, 0x384e4803, 0xfd51f7f8, 0x83f8e8bd, 
+    0xfffff800, 0xd00308ae, 0xffff8000, 0x000362b1, 0x00b1afb7, 0x0003626a, 0x4604b510, 0x48fe4621, 
+    0xff42f7f1, 0x48fc2100, 0xff3ef7f1, 0x31fff04f, 0x381048f9, 0xff38f7f1, 0x48f72100, 0xf7f13810, 
+    0xbd10ff33, 0xf04fb510, 0xf7ff30ff, 0x48f3ffe5, 0xff1af7f1, 0xf7fa2004, 0xbd10f89a, 0x4604b510, 
+    0x49efb260, 0xf04f7008, 0xf7ff30ff, 0x48ecffd5, 0x0000f990, 0x220cb283, 0x0100f241, 0x1c8048e6, 
+    0xfd0df7f8, 0xb510bd10, 0x49e62000, 0x49e67008, 0x20017008, 0x700849e5, 0x700849e1, 0x700849e4, 
+    0x700849e4, 0x700849e4, 0x49e42000, 0x48df7008, 0x0000f990, 0x2206b283, 0x48d72140, 0xf7f81c80, 
+    0x48d9fcee, 0x0000f990, 0x2205b283, 0x48d22120, 0xf7f81c80, 0x48d3fce4, 0x0000f990, 0x2204b283, 
+    0x48cd2110, 0xf7f81c80, 0x48cdfcda, 0x0000f990, 0x220cb283, 0x0100f241, 0x1c8048c7, 0xfccff7f8, 
+    0xf99048cb, 0xb2830000, 0x21802207, 0x1c8048c2, 0xfcc5f7f8, 0xf99048c8, 0xb2830000, 0x21042202, 
+    0x1c8048bd, 0xfcbbf7f8, 0xf99048c4, 0xb2830000, 0xf244220e, 0x48b80100, 0xf7f81c80, 0x2300fcb0, 
+    0xf240220a, 0x48b44100, 0xf7f8380e, 0x2300fca8, 0x01512208, 0x380e48b0, 0xfca1f7f8, 0x22062300, 
+    0x11c0f240, 0x300848ac, 0xfc99f7f8, 0x22032306, 0x48a92138, 0xf7f83008, 0x2306fc92, 0x21072200, 
+    0x300848a5, 0xfc8bf7f8, 0x461a2306, 0x11c0f240, 0x300a48a1, 0xfc83f7f8, 0x22002302, 0x489e2107, 
+    0xf7f81d00, 0x2300fc7c, 0x2107461a, 0x300a489a, 0xfc75f7f8, 0x461a2306, 0x11c0f240, 0x1d004896, 
+    0xfc6df7f8, 0x461a2306, 0x11c0f240, 0x380a4892, 0xfc65f7f8, 0x22002306, 0x488f2107, 0xf7f8380a, 
+    0xbd10fc5e, 0x4604b510, 0x220e4623, 0x0100f244, 0xf7f82000, 0x4623fd7c, 0xf244220e, 0x20460100, 
+    0xfe01f7f8, 0x22004623, 0x488d2101, 0xfc47f7f8, 0xb530bd10, 0x4d8bb244, 0xb24c702c, 0xb254706c, 
+    0xb25c70ac, 0xbd3070ec, 0x4887b538, 0x49867800, 0x46088008, 0xf4408800, 0x80087080, 0x78004883, 
+    0x4882b118, 0x28027800, 0x4881d122, 0x28017800, 0x487dd11e, 0xf0007800, 0x487b0303, 0xf3c07800, 
+    0x48790281, 0xf3c07800, 0x48771101, 0xf3c07800, 0xf7ff1081, 0x2003ffce, 0x0000f88d, 0xf88d2002, 
+    0x20010001, 0x0002f88d, 0xf88d2000, 0xe01d0003, 0x7809496d, 0x0003f001, 0x7809496b, 0x1381f3c1, 
+    0x78094969, 0x1201f3c1, 0x78094967, 0x0181f3c1, 0xffaff7ff, 0xf88d2000, 0x20010000, 0x0001f88d, 
+    0xf88d2002, 0x20030002, 0x0003f88d, 0x20092100, 0xfd7bf7f8, 0xf404b284, 0xf99d447f, 0x495a0000, 
+    0x07897809, 0x40880f49, 0x1001f99d, 0x78124a56, 0x0281f3c2, 0x40910052, 0xf99d4308, 0x4a521002, 
+    0xf3c27812, 0x00521201, 0x43084091, 0x1003f99d, 0x78124a4d, 0x1281f3c2, 0x40910052, 0x43204308, 
+    0xf444b284, 0x46217480, 0xf7f82009, 0xbd38fd38, 0x4604b570, 0xd1022c01, 0xff76f7ff, 0xb934e03b, 
+    0x22022303, 0x20002101, 0xff63f7ff, 0x483ee033, 0xb1108800, 0xff68f7ff, 0x483de02d, 0x28017800, 
+    0x483ad11e, 0xb1187800, 0x78004838, 0xd10b2802, 0x111bf240, 0xf7f82009, 0x2300fd12, 0x21022201, 
+    0xf7ff2003, 0xe016ff46, 0x11e4f240, 0xf7f82009, 0x2303fd06, 0x21012202, 0xf7ff2000, 0xe00aff3a, 
+    0x11e4f240, 0xf7f82009, 0x2303fcfa, 0x21012202, 0xf7ff2000, 0x4823ff2e, 0xf9914926, 0x5c401000, 
+    0x70084924, 0xf9964e1f, 0xf9963003, 0xf9962002, 0xf9961001, 0xf7ff0000, 0xf996f88f, 0xf9963003, 
+    0xf9962002, 0xf9961001, 0xf7fb0000, 0xf996fa95, 0xf9963003, 0xf9962002, 0xf9961001, 0xf7fc0000, 
+    0xf996fd59, 0xf9963003, 0xf9962002, 0xf9961001, 0xf00f0000, 0xe01ffd6c, 0xd003902a, 0xc1000144, 
+    0x00036277, 0x00036271, 0x00036272, 0x00036273, 0x00036279, 0x00036278, 0x00036276, 0x0003627b, 
+    0xd28fffe0, 0x00036254, 0x00036316, 0x000361d8, 0x00038488, 0x000362b1, 0x20092100, 0xfcb5f7f8, 
+    0xb2edb285, 0x48fe4629, 0xfd1ef7f1, 0xb510bd70, 0x48fb49fc, 0xf7f130a6, 0x2301fd17, 0x0399220e, 
+    0xf7f848f9, 0x2300fb0c, 0x21042202, 0xf7f848f7, 0x48f7fb06, 0x28098800, 0x48f5d003, 0x280d8800, 
+    0x2300d106, 0xf241220c, 0x48f00100, 0xfaf7f7f8, 0x220f2301, 0x48ed49ef, 0xf7f83820, 0x2301faf0, 
+    0x0319220c, 0x382048e9, 0xfae9f7f8, 0x22062300, 0x48e62140, 0xf7f83820, 0x2300fae2, 0x21202205, 
+    0x382048e2, 0xfadbf7f8, 0x22042300, 0x48e22110, 0xfad5f7f8, 0x220a2300, 0x4100f240, 0xf7f848df, 
+    0xf640face, 0x20004100, 0xfbc5f7f8, 0x0167f648, 0xf7f82007, 0x2100fbc0, 0xf7f82074, 0xf244fc40, 
+    0x20040104, 0xfbb7f7f8, 0xf7ff2002, 0x2300ff01, 0x21802207, 0xf7f848d2, 0x2001fab2, 0xfe52f7ff, 
+    0xf7f8200a, 0xb280fc01, 0x7480f440, 0x200a4621, 0xfbe3f7f8, 0xf7f8200a, 0xb280fbf7, 0x0410f040, 
+    0x200a4621, 0xfbd9f7f8, 0x48c02100, 0xf7f13038, 0x2301fc9b, 0x46192200, 0xf7f848bb, 0x2301fa90, 
+    0x0319220c, 0xf7f848b8, 0x2301fa8a, 0x0359220d, 0xf7f848b5, 0x2300fa84, 0x01512208, 0x306048b2, 
+    0xfa7df7f8, 0xb570bd10, 0x460d4604, 0x22064623, 0x71c0f640, 0x300e48b2, 0xfa71f7f8, 0x22004623, 
+    0x48af213f, 0xf7f8300e, 0x4623fa6a, 0xf6402206, 0x48ab71c0, 0xf7f83010, 0x4623fa62, 0x213f2200, 
+    0x301048a7, 0xfa5bf7f8, 0x22064623, 0x71c0f640, 0x301248a3, 0xfa53f7f8, 0x22004623, 0x48a0213f, 
+    0xf7f83012, 0x4623fa4c, 0xf6402206, 0x489c71c0, 0xf7f83014, 0x4623fa44, 0x213f2200, 0x30144898, 
+    0xfa3df7f8, 0x2208462b, 0x7100f643, 0xf7f84895, 0x462bfa36, 0xf6432208, 0x48927100, 0xf7f81c80, 
+    0x462bfa2e, 0xf6432208, 0x488e7100, 0xf7f81d00, 0x462bfa26, 0xf6432208, 0x488a7100, 0xf7f81d80, 
+    0x462bfa1e, 0xf6432208, 0x48867100, 0xf7f83010, 0x462bfa16, 0xf6432208, 0x48827100, 0xf7f83012, 
+    0x462bfa0e, 0xf6432208, 0x487e7100, 0xf7f83014, 0x462bfa06, 0xf6432208, 0x487a7100, 0xf7f83016, 
+    0xbd70f9fe, 0x2400b51c, 0x200fe00b, 0xe9cd210b, 0xb2e01000, 0x0300f647, 0x46112200, 0xfc10f7f8, 
+    0x2c041c64, 0xbd1cdbf1, 0x2400b51c, 0x2000e00b, 0xe9cd210b, 0xb2e01000, 0x0300f647, 0x46112200, 
+    0xfbfef7f8, 0x2c041c64, 0xbd1cdbf1, 0x4605b570, 0xe0072400, 0x2200b2e0, 0xf7f82101, 0xf825fbc7, 
+    0x1c640014, 0xdbf52c04, 0xe92dbd70, 0x46834ff8, 0x0a00f04f, 0xf00ae01a, 0x220200ff, 0xf7f82100, 
+    0x9000fbb5, 0xff13f01f, 0x22004680, 0xf01f4b56, 0x4606fd1d, 0xfbbaf01f, 0x22004604, 0xf01f4b53, 
+    0xeb0bff6d, 0xc20302ca, 0x0a01f10a, 0x0f04f1ba, 0xe8bddbe1, 0xb5108ff8, 0x21042202, 0x1c804847, 
+    0xf9b4f7f8, 0x2001b108, 0x2000bd10, 0xb510e7fc, 0xf242220d, 0x48410100, 0xf7f83014, 0xb108f9a7, 
+    0xbd102001, 0xe7fc2000, 0x4a41b51c, 0x2005210a, 0xfc3ff7f1, 0xf7f92004, 0x2002fc6e, 0xfc6bf7f9, 
+    0xf00b2002, 0x2002fae1, 0x7008493a, 0xf7fe2000, 0x2100fd18, 0xf7ff2022, 0x2301fef6, 0x21102204, 
+    0x30384827, 0xf96bf7f8, 0xf7fe2004, 0x2000fcc9, 0xfb81f7fd, 0x22082300, 0x7100f640, 0x300c4828, 
+    0xf95df7f8, 0x20fb2100, 0xfad9f7f8, 0x034df24a, 0x2100220f, 0xf7f84608, 0xf240fb1d, 0x220e3352, 
+    0x46082100, 0xfb16f7f8, 0x20d82120, 0xfac7f7f8, 0x21012200, 0xf00a4608, 0x2300fb35, 0x2101461a, 
+    0xf7f8481d, 0x2001f93c, 0xf981f7fe, 0x2100200c, 0x2214230f, 0x1000e9cd, 0xf7f84608, 0x2202fb51, 
+    0x480a2104, 0xf7f83038, 0x2801f941, 0x2202d132, 0x48062104, 0xf7f8303a, 0x2801f939, 0xe01dd12a, 
+    0xd03c8012, 0xffffbbb8, 0xd28f0000, 0xd28e0040, 0x000361ce, 0xffff8000, 0xd003507c, 0xd28fffc0, 
+    0xd0039000, 0xd0034200, 0x40e00000, 0x40240000, 0xcccc0000, 0x000361ec, 0xd00305cc, 0xf7fe2003, 
+    0x2000fcbf, 0x014b2108, 0xe9cd2221, 0x46011000, 0xfb16f7f8, 0x78004882, 0x2003b910, 0xfa01f7f4, 
+    0x22002301, 0x487f210f, 0xf8e9f7f8, 0x220f2301, 0x487e497d, 0xf8e3f7f8, 0xe92dbd1c, 0x4a7c41f0, 
+    0x2005210b, 0xfb95f7f1, 0xf7f92004, 0x2002fbc4, 0xfbc1f7f9, 0xf00b2001, 0x2001fa37, 0x70084975, 
+    0xf7fe2000, 0x220dfc6e, 0x0100f242, 0x381a486f, 0xf8dcf7f8, 0x2601b108, 0x2600e000, 0x5780486e, 
+    0xd0112801, 0xd0082802, 0xd1142803, 0x22022301, 0x486a2104, 0xf8b3f7f8, 0x2301e014, 0x21042202, 
+    0xf7f84867, 0xe00df8ac, 0x22022301, 0x48652104, 0xf8a5f7f8, 0x2301e006, 0x21042202, 0xf7f84862, 
+    0xbf00f89e, 0x2103bf00, 0xf7ff2021, 0x2301fe1c, 0x21102204, 0xf7f8485d, 0x2004f892, 0xfbf0f7fe, 
+    0x20092100, 0xfa21f7f8, 0x250fb287, 0xe00b2400, 0xfa470060, 0xf000f000, 0x20010103, 0xf0804088, 
+    0x4005000f, 0xb2c41c60, 0xdbf12c02, 0x2208462b, 0x7100f640, 0xf7f8484e, 0xf247f872, 0x20fb0100, 
+    0xf9edf7f8, 0x22192300, 0x46184619, 0xfa32f7f8, 0x0307f248, 0x21002218, 0xf7f84608, 0xf241fa2b, 
+    0x22190300, 0x46082100, 0xfa24f7f8, 0x22192300, 0x46184619, 0xfa1ef7f8, 0x22182300, 0x46184619, 
+    0xfa18f7f8, 0x21012200, 0xf00a4608, 0x2300fa3b, 0x2101461a, 0xf7f84837, 0x2001f842, 0xf887f7fe, 
+    0xf244220e, 0x48320100, 0xf7f8301a, 0xb108f84f, 0xfa37f00b, 0x22002301, 0x4822210f, 0xf82ff7f8, 
+    0x81f0e8bd, 0x2000b51c, 0x7008492b, 0xfe3cf7ff, 0x492a2001, 0x46087008, 0x0000f990, 0x220cb283, 
+    0x0100f241, 0x30204822, 0xf819f7f8, 0x22082300, 0x7100f640, 0xf7f8481e, 0x2100f812, 0xf7f820fb, 
+    0x2002f98e, 0xfbccf7fe, 0x21082001, 0x22210203, 0x1000e9cd, 0x46082100, 0xfa22f7f8, 0xf9cbf00b, 
+    0x46112200, 0xf7f24610, 0x2200fa9b, 0x46104611, 0xf9e8f00a, 0x21094a06, 0xf7f12005, 0xbd1cfaaa, 
+    0x00036266, 0xd03c8316, 0xffff8000, 0xd28ffffc, 0xcccc0000, 0x000361ec, 0x00036254, 0xd003d800, 
+    0xd003d000, 0xd003c800, 0xd003c000, 0xd03c804a, 0xd003900c, 0xd00305cc, 0x000384e5, 0x00036277, 
+    0x4ff0e92d, 0x2000b087, 0xf99cf7fb, 0x6500f240, 0x10c3f240, 0x46834680, 0x1b2beb0b, 0x1828eba8, 
+    0x02812001, 0x02432205, 0x3200e9cd, 0x1002e9cd, 0x1e824603, 0x489a2103, 0xfdd6f00d, 0x0a00f04f, 
+    0xe00a2400, 0xf9314996, 0x2800001a, 0x4601db01, 0x4241e000, 0xf10a440c, 0xf5ba0a01, 0xdbf17f00, 
+    0xf04f1264, 0xe0140900, 0xdd05455c, 0x1464eba4, 0x1065eba5, 0xe008b205, 0xda054544, 0x1464eb04, 
+    0x1065eb05, 0xe000b205, 0xf109e006, 0xfa4f0001, 0xf1b9f980, 0xdbe70f10, 0xf240bf00, 0xf44f11f4, 
+    0xf7f10000, 0x497ffa6f, 0x0000f44f, 0xfa1af7f1, 0xf44f4641, 0xf7f10000, 0x4621fa15, 0x0000f44f, 
+    0xfa10f7f1, 0xf44f4659, 0xf7f10000, 0x4629fa0b, 0x0000f44f, 0xfa06f7f1, 0xf44f4973, 0xf7f10000, 
+    0x2000fa01, 0xf945f7fa, 0x02882101, 0xf9dcf7f9, 0xf7f72001, 0xf240fd0f, 0x486c1100, 0xfeccf01e, 
+    0xf8a0486a, 0x10685060, 0x00a5eb00, 0xb2004240, 0xf8a14966, 0x27000062, 0x2000e00b, 0x46034963, 
+    0xe9cd4602, 0xb2791000, 0xf7f72001, 0x1c78fb23, 0x2f04b287, 0x2000dbf1, 0xfcecf7f7, 0x7800485c, 
+    0xd13a2801, 0xf00e2000, 0x220eff73, 0xf6404611, 0xf7f90000, 0x2002ff7b, 0xff6af00e, 0x20402101, 
+    0xf9a2f7f9, 0x23012000, 0x3002e9cd, 0x90059004, 0x9000200c, 0x4611220d, 0x02989001, 0xfff1f7f9, 
+    0x23012000, 0x3002e9cd, 0x90059004, 0x9000200d, 0x46014602, 0x02d89001, 0xffe3f7f9, 0x23012000, 
+    0x3002e9cd, 0x90059004, 0x9000200e, 0x46014602, 0x02d89001, 0xffd5f7f9, 0x2002e020, 0xff38f00e, 
+    0x20402101, 0xf970f7f9, 0xfdcef7fe, 0x03882101, 0xf96af7f9, 0x90002000, 0x220b4603, 0x90014611, 
+    0x4000f240, 0xfe87f7f9, 0x90002000, 0x220d4603, 0x90014611, 0x0000f241, 0xfe7df7f9, 0x7800482d, 
+    0x2001b120, 0xfd86f00c, 0xe00a4606, 0x78094928, 0xd0012901, 0xe0002101, 0x46082100, 0xfd7af00c, 
+    0x20004606, 0xf8a5f7fa, 0x02882101, 0xf93cf7f9, 0xf006b396, 0xbb780001, 0xf990481f, 0xb2830000, 
+    0xf246220d, 0x481d0100, 0xfea9f7f7, 0x220f2301, 0x481a491b, 0xfea3f7f7, 0xf00e2001, 0x2101fee9, 
+    0xf7f90288, 0x4a17f921, 0xf9934b13, 0x5cd13000, 0x78124a0f, 0xd0012a01, 0xe0002201, 0x46102200, 
+    0xfbbef00c, 0x220d2300, 0x0100f246, 0xf7f7480b, 0x2000fe86, 0xfeccf00e, 0xe8bdb007, 0x00008ff0, 
+    0x00054000, 0x99339933, 0xdcba01f5, 0x00043078, 0x000361ee, 0x0003845c, 0x00036227, 0xd0035092, 
+    0xffff8000, 0x00036258, 0xf00bb510, 0xf01dfe38, 0x2801fcaf, 0x48fed114, 0xf3c079c0, 0x49fd1000, 
+    0x46087008, 0x28017800, 0x0742d13b, 0xf99048fa, 0x15501000, 0xf90df7f1, 0x49f7200b, 0xe0307008, 
+    0xf24021e2, 0xf7f11000, 0x2100f93d, 0x1000f240, 0xf8e8f7f1, 0x880048f1, 0x7080f400, 0x48f0b1a0, 
+    0xb9886800, 0x680048ef, 0x71fcf240, 0xda0b4288, 0x4aec49ed, 0xeb016812, 0xf7f10082, 0x48e9f859, 
+    0x1d006800, 0x600849e7, 0x780048e8, 0xd1022801, 0x7010f242, 0x2000e000, 0x312bf200, 0xf7f148e4, 
+    0xbd10f823, 0x2001b510, 0x700849e2, 0xf99149e2, 0x49e20000, 0xfb93f7f7, 0x21044ae1, 0xf01d48df, 
+    0xf04ffd1f, 0x48d45200, 0x1000f990, 0xf7f11550, 0x2004f8c0, 0xfd04f00f, 0x700849da, 0xf7f82000, 
+    0x2100f9ae, 0x780048d7, 0xf7f8b240, 0x2001f92c, 0xf9a5f7f8, 0x48d32100, 0xb2407800, 0xf923f7f8, 
+    0xf9aef7f8, 0xb510bd10, 0x5200f04f, 0xf99048c2, 0x15501000, 0xf89df7f1, 0xfd20f00c, 0x48cab170, 
+    0x28037800, 0x2004d106, 0xf8c5f7f9, 0x49ba200b, 0xe0247008, 0x49b82009, 0xe0207008, 0xf7fa2000, 
+    0x49c2ffa1, 0xf7f47808, 0x2003fcb0, 0x700849b2, 0x49bf2000, 0x1000f991, 0x54504ab7, 0x49bc2001, 
+    0x1001f991, 0x20025450, 0xf99149b9, 0x54501002, 0x49b72003, 0x1003f991, 0xf00c5450, 0xbd10fc76, 
+    0xf04fb510, 0x48a45200, 0x1000f990, 0xf7f11550, 0xf008f860, 0xbd10fe0b, 0xf04fb51f, 0x489e5200, 
+    0x1000f990, 0xf7f11550, 0xf7fff854, 0x2000fdc9, 0xff7ff7f9, 0xf7fa4668, 0x48a6fd23, 0x0000f990, 
+    0xb1181c40, 0x49942007, 0xe0877008, 0xf99149a2, 0x1c481000, 0xeb0017c1, 0x10897191, 0x0181eba0, 
+    0x4a9db249, 0x24007011, 0x4898e06c, 0x28057800, 0x4896d003, 0x28047800, 0x4898d110, 0xb9688800, 
+    0x78004895, 0xf240b128, 0x46202100, 0xfcbef7fe, 0x4993e056, 0xf7fe4620, 0xe051fcb9, 0x7800488b, 
+    0xd1262804, 0x7800488c, 0x2200b928, 0x46204611, 0xfa30f01b, 0x4888e044, 0x28017800, 0x2200d105, 
+    0x46202101, 0xfa26f01b, 0x4883e03a, 0x28027800, 0x2200d105, 0x46202102, 0xfa1cf01b, 0x487ee030, 
+    0x28037800, 0x2200d12c, 0x46202103, 0xfa12f01b, 0x4879e026, 0xb9287800, 0x46112200, 0xf01b4620, 
+    0xe01dfa09, 0x78004874, 0xd1052801, 0x21000202, 0xf01b4620, 0xe013f9ff, 0x7800486f, 0xd1052802, 
+    0x21012200, 0xf01b4620, 0xe009f9f5, 0x7800486a, 0xd1052803, 0x1200f240, 0x46202101, 0xf9eaf01b, 
+    0xb2441c60, 0xdb902c04, 0x78004863, 0x495fb930, 0xf7f47808, 0x2003fbea, 0x7008494f, 0xb510bd1f, 
+    0x496020b0, 0xf04f6008, 0x484b5200, 0x1000f990, 0xf7f01550, 0x20b1ffae, 0x6008495a, 0xfdaef00e, 
+    0xfc00f7f9, 0xfc18f7f9, 0x495620ba, 0x20bb6008, 0x484d6008, 0xb1187800, 0x7800484b, 0xd1082807, 
+    0x495020c0, 0xf00d6008, 0x20d0fc77, 0x6008494d, 0x20e0e00d, 0x6008494b, 0x484b2200, 0x20026801, 
+    0xfff2f7f8, 0xfc68f00d, 0x494620f0, 0xbd106008, 0x2090b510, 0x60084943, 0x482f0642, 0x1000f990, 
+    0xf7f01550, 0x2200ff76, 0x46082101, 0xfeaaf009, 0xf44f2100, 0xf7f81080, 0x2200ff37, 0x20014611, 
+    0xfea0f009, 0xfd6af00e, 0xfbbcf7f9, 0xfbd4f7f9, 0x493420a0, 0xbd106008, 0x47fce92d, 0x46894607, 
+    0x26004615, 0x2001e06d, 0x80084930, 0xf8ad2000, 0xf8ad0006, 0xf8ad0004, 0xf8ad0002, 0x46680000, 
+    0xfd5ef7fa, 0xf01f4638, 0xfa0ffdc3, 0x2202f880, 0x46402107, 0xfcdcf00e, 0xf7fa4668, 0x2400fd32, 
+    0xf93de007, 0x42a80014, 0xf82ddb01, 0x1c605014, 0x2c04b244, 0x4814dbf5, 0x28037800, 0x2001d105, 
+    0xf991490d, 0xf82d1003, 0x46680011, 0x0000e030, 0x00038fd0, 0x000361f8, 0x000385b8, 0x0005280c, 
+    0x000362f4, 0x00052800, 0x00050800, 0x000361ee, 0xd03c80b8, 0x000361f7, 0x00036240, 0x00038e90, 
+    0x00038ed0, 0x000361f9, 0x0003625c, 0x0003626a, 0x00036254, 0x00036227, 0x0003622c, 0x000361cc, 
+    0xfffffa00, 0x000385b0, 0x000384a4, 0x000362e8, 0xfd06f7fa, 0x880048f9, 0xd0002802, 0x1c70e003, 
+    0x2e0ab246, 0xbf00db8f, 0x49f42000, 0xe8bd8008, 0xb51087fc, 0x49f22070, 0xf04f6008, 0x48f15200, 
+    0x1000f990, 0xf7f01550, 0x221efed4, 0x48ef49ee, 0xff72f7ff, 0x49ea2080, 0xbd106008, 0x2050b570, 
+    0x600849e7, 0x5200f04f, 0xf99048e6, 0x15501000, 0xfebff7f0, 0x49e62000, 0x808880c8, 0x80088048, 
+    0xf7fa4608, 0x2202fccd, 0xf2402107, 0xf00e1048, 0x251efc4f, 0x48de2601, 0xfca3f7fa, 0xe0112400, 
+    0xf93048db, 0x42a80014, 0x48d9db02, 0x5014f820, 0xf93048d7, 0x42b00014, 0x48d5dc02, 0x6014f820, 
+    0xb2441c60, 0xdbeb2c04, 0xf7fa48d1, 0x2060fca9, 0x600849cb, 0xb508bd70, 0x90002000, 0x49c82030, 
+    0x46686008, 0xfb69f7fa, 0x780048ca, 0xd1052803, 0x49c92001, 0x1003f991, 0x0001f80d, 0x0000f89d, 
+    0xf89db1c0, 0xb1a80001, 0x0002f89d, 0xf89db190, 0xb1780003, 0x49ba2040, 0xf2426008, 0xf7f00010, 
+    0x2003fec5, 0x700849b7, 0x22002301, 0x48bb4619, 0xfba5f7f7, 0x0001f89d, 0x2301b128, 0x2102461a, 
+    0xf7f748b6, 0xf89dfb9c, 0xb1280002, 0x22022301, 0x48b22104, 0xfb93f7f7, 0x0003f89d, 0x2301b128, 
+    0x21082203, 0xf7f748ad, 0xbd08fb8a, 0x2010b510, 0x600849a3, 0x01002101, 0xfe74f7f0, 0x11f4f240, 
+    0x1000f240, 0xfe6ef7f0, 0x680048a5, 0x41d0f040, 0x1000f240, 0xfe16f7f0, 0xf24049a2, 0xf7f01000, 
+    0x2000fe11, 0xfbb2f7fa, 0xfd6af7fa, 0x49942020, 0x20006008, 0xf991499c, 0x4a971000, 0x20015450, 
+    0xf9914999, 0x54501001, 0x49972002, 0x1002f991, 0x20035450, 0xf9914994, 0x54501003, 0xfa15f00c, 
+    0x49922000, 0xbd107008, 0x4604b570, 0x8ea0460d, 0x7f86f5b0, 0xdc22d075, 0xd07328e5, 0x28d0dc0d, 
+    0xdc05d071, 0x28aeb3a8, 0x28afd054, 0xe060d16c, 0xd06a28d1, 0xd1f928e4, 0x28f5e125, 0xdc06d077, 
+    0xd07528ec, 0xd07428ed, 0xd1ef28f4, 0xf5b0e173, 0xd06f7f82, 0x1005f2a0, 0xd1e72800, 0xf240e1a9, 
+    0x1a81123d, 0xd07d4290, 0xf5b0dc14, 0xd07a7f96, 0xf2a0dc08, 0x2800100d, 0x2813d076, 0x2814d075, 
+    0xe1f7d1d4, 0x102df2a0, 0xd06f2800, 0xd1cd280f, 0xe00ee249, 0xd06a2916, 0x290ddc06, 0x290ed068, 
+    0x2915d067, 0xe2a3d1c2, 0xd07d291d, 0xd1bd291e, 0xe2f3e2f0, 0x32fff04f, 0x48664965, 0xf0176800, 
+    0x4965ffdd, 0x46086008, 0x1d006800, 0x20aeb950, 0xbd7086a0, 0x495e2200, 0x6800485e, 0xffcef017, 
+    0x6008495d, 0x6800485c, 0xb9281d40, 0x86a020af, 0x2001e7ef, 0x60084958, 0x68004857, 0xd0052801, 
+    0xe173e2cc, 0xe054e0cf, 0xe062e2c9, 0x88004850, 0xd110280f, 0xf9b0484e, 0xf04f1000, 0xf2404222, 
+    0xf7f01000, 0x2001fd76, 0x7008493e, 0xe112e2b5, 0xe0e4e0d5, 0x4846e12c, 0x28108800, 0x4847d156, 
+    0x28037800, 0x4845d007, 0x28057800, 0x4843d003, 0x28047800, 0x4842d141, 0xbb307800, 0xf9b0483c, 
+    0xe0071000, 0xe1a2e1f0, 0xe172e151, 0xe250e1b0, 0xe21be20c, 0x4220f04f, 0x1000f240, 0xfd49f7f0, 
+    0xff04f7ff, 0x49272000, 0x200a7008, 0x80084930, 0x48302200, 0xf0176800, 0x492fff3f, 0x46086008, 
+    0x1d006800, 0xe001b968, 0xe016e264, 0x86a020d0, 0x2200e78f, 0x48274926, 0xf0176800, 0x4926ff2d, 
+    0x48256008, 0x1d406800, 0xd1af2800, 0x86a020d1, 0x2001e77f, 0x60084920, 0x2001e25f, 0x70084911, 
+    0x210f0742, 0xf7f00200, 0xe256fd14, 0x88004818, 0xd19b280a, 0x7800480b, 0xf7ffb978, 0x2002fe7c, 
+    0xfd57f7f8, 0x480bb938, 0x28007800, 0x4809dd2a, 0x28077800, 0x200ada26, 0xe048e025, 0x000362e8, 
+    0x000385b0, 0x000385b8, 0x44b861ec, 0x43a4170a, 0x00036296, 0x0003625c, 0x00036240, 0xd0035018, 
+    0x00052f88, 0xdcba01f5, 0x00036254, 0x0003622c, 0x000385bc, 0x000385b4, 0x000385c4, 0x0003626a, 
+    0x0003845c, 0x49fd200f, 0x22008008, 0x680048fc, 0xfed2f017, 0x600849fb, 0x68004608, 0xb9501d00, 
+    0x86a020e4, 0x2200e725, 0x48f549f4, 0xf0176800, 0x49f4fec3, 0x48f36008, 0x1d406800, 0xd19b2800, 
+    0x86a020e5, 0x2001e715, 0x600849ee, 0x48eee1f5, 0x28037800, 0xf7ffd127, 0x2006fde1, 0x700849ea, 
+    0x49e62200, 0x680048e6, 0xfea6f017, 0x600849e5, 0x68004608, 0xb9501d00, 0x86a020ec, 0x2200e6f9, 
+    0x48df49de, 0xf0176800, 0x49defe97, 0x48dd6008, 0x1d406800, 0xd1d92800, 0x86a020ed, 0x2001e6e9, 
+    0x600849d8, 0x48d8e1c9, 0x28067800, 0xf7ffd127, 0x2002fda0, 0x700849d4, 0x49d02200, 0x680048d0, 
+    0xfe7af017, 0x600849cf, 0x68004608, 0xb9501d00, 0x86a020f4, 0x2200e6cd, 0x48c949c8, 0xf0176800, 
+    0x49c8fe6b, 0x48c76008, 0x1d406800, 0xd1ad2800, 0x86a020f5, 0x2001e6bd, 0x600849c2, 0x48c2e19d, 
+    0x28027800, 0xf7ffd129, 0x2004fcd3, 0x700849be, 0x49ba2200, 0x680048ba, 0xfe4ef017, 0x600849b9, 
+    0x68004608, 0xb9581d00, 0x1004f240, 0xe6a086a0, 0x49b22200, 0x680048b2, 0xfe3ef017, 0x600849b1, 
+    0x680048b0, 0x28001d40, 0xf240d1ac, 0x86a01005, 0x2001e68f, 0x600849ab, 0x48abe16f, 0x28047800, 
+    0xf7ffd129, 0x200cfc6c, 0x700849a7, 0x49a32200, 0x680048a3, 0xfe20f017, 0x600849a2, 0x68004608, 
+    0xb9581d00, 0x100cf240, 0xe67286a0, 0x499b2200, 0x6800489b, 0xfe10f017, 0x6008499a, 0x68004899, 
+    0x28001d40, 0xf240d1aa, 0x86a0100d, 0x2001e661, 0x60084994, 0x4894e141, 0x280c7800, 0xf7ffd12e, 
+    0x2002fb9b, 0xfc45f7f8, 0x200ab108, 0x200fe000, 0x8008498a, 0x488a2200, 0xf0176800, 0x4989fded, 
+    0x46086008, 0x1d006800, 0xf240b958, 0x86a01020, 0x2200e63f, 0x48824981, 0xf0176800, 0x4981fddd, 
+    0x48806008, 0x1d406800, 0xd1a52800, 0x1021f240, 0xe62e86a0, 0x497b2001, 0xe10e6008, 0x7800487a, 
+    0xd1292807, 0xfb5cf7ff, 0x49772005, 0x22007008, 0x48734972, 0xf0176800, 0x4972fdbf, 0x46086008, 
+    0x1d006800, 0xf240b958, 0x86a0102c, 0x2200e611, 0x486b496a, 0xf0176800, 0x496afdaf, 0x48696008, 
+    0x1d406800, 0xd1a52800, 0x102df240, 0xe60086a0, 0x49642001, 0xe0e06008, 0x78004863, 0xd1372805, 
+    0xfaf1f7ff, 0x78004861, 0xd1032803, 0x495b200a, 0xe0088008, 0xf7f82002, 0xb108fbdc, 0xe000200a, 
+    0x4956200f, 0x22008008, 0x48554954, 0xf0176800, 0x4954fd83, 0x46086008, 0x1d006800, 0xf240b958, 
+    0x86a0103c, 0x2200e5d5, 0x484d494c, 0xf0176800, 0x494cfd73, 0x484b6008, 0x1d406800, 0xd1062800, 
+    0x103df240, 0xe5c486a0, 0x49462001, 0xe0a46008, 0x78004845, 0xd12d2809, 0xfa84f7ff, 0x78004843, 
+    0xd1002803, 0x200ae09a, 0x7008493f, 0x493b2200, 0x6800483b, 0xfd50f017, 0x6008493a, 0x68004608, 
+    0xb9581d00, 0x104af240, 0xe5a286a0, 0x49332200, 0x68004833, 0xfd40f017, 0x60084932, 0x68004831, 
+    0xbba81d40, 0x104bf240, 0xe59286a0, 0x492d2001, 0xe0726008, 0x7800482c, 0xd12e280a, 0xfa04f7ff, 
+    0xf7f82002, 0xb108fb76, 0xe000200a, 0x4923200f, 0x22008008, 0x68004822, 0xfd1ef017, 0x60084921, 
+    0x68004608, 0xb9581d00, 0x1052f240, 0xe57086a0, 0x491a2200, 0x6800481a, 0xfd0ef017, 0x60084919, 
+    0x68004818, 0xb9181d40, 0x1053f240, 0xe56086a0, 0x2001e043, 0x60084913, 0x4813e03f, 0x280b7800, 
+    0x480ed13b, 0x1000f9b0, 0x4220f04f, 0x1000f240, 0xfaeff7f0, 0x4909200b, 0xf04f8008, 0x480c32ff, 
+    0xf0176800, 0x4907fce9, 0x46086008, 0x1d006800, 0xf240b9c0, 0x86a0105a, 0x0000e53b, 0x000385bc, 
+    0x000385b4, 0x000385c4, 0x000385b8, 0x0003625c, 0x00038654, 0x49122200, 0x68004812, 0xfcccf017, 
+    0x60084911, 0x68004810, 0xb9301d40, 0x105bf240, 0xe51e86a0, 0x490c2001, 0xbf006008, 0xbf00e50a, 
+    0xe516bf00, 0x2200b510, 0xf2af2101, 0xf01760a3, 0x2108fa46, 0xf0172003, 0x4904fbe3, 0xbd106008, 
+    0x000385bc, 0x00038654, 0x000385c4, 0x000385b4, 0xf04fb510, 0x48fe4280, 0x1000f9b0, 0xf7f01510, 
+    0xf00bfa98, 0xb168ff1b, 0x22112300, 0x3100f44f, 0xf7f648f8, 0x2001ffad, 0xf9bbf7f9, 0x49f4200e, 
+    0xe0198008, 0x49f22007, 0x20008008, 0xf99149f2, 0x4af21000, 0x20015450, 0xf99149ef, 0x54501001, 
+    0x49ed2002, 0x1002f991, 0x20035450, 0xf99149ea, 0x54501003, 0xfe79f00b, 0xb510bd10, 0x4280f04f, 
+    0xf9b048e3, 0x15101000, 0xfa63f7f0, 0xf7fa48e4, 0x2400f858, 0x48e2e013, 0x0014f930, 0xdb03281e, 
+    0x49df201e, 0x0014f821, 0xf93048dd, 0x28010014, 0x2001dc03, 0xf82149da, 0x1c600014, 0x2c04b244, 
+    0x48d7dbe9, 0xf85cf7fa, 0xfff0f007, 0xb510bd10, 0x4280f04f, 0xf9b048ce, 0x15101000, 0xfa39f7f0, 
+    0xffaef7fe, 0xf7f92000, 0x48cef964, 0x0000f990, 0xb1181c40, 0x49c62012, 0xe0838008, 0xf99149ca, 
+    0x1c481000, 0xeb0017c1, 0x10897191, 0x0181eba0, 0x4ac5b249, 0x24007011, 0x48c4e06c, 0x28057800, 
+    0x48c2d003, 0x28047800, 0x48c1d110, 0xb9688800, 0x780048bd, 0xf240b128, 0x46202100, 0xfea6f7fd, 
+    0x49bce056, 0xf7fd4620, 0xe051fea1, 0x780048b7, 0xd1262804, 0x780048b4, 0x2200b928, 0x46204611, 
+    0xfc18f01a, 0x48b0e044, 0x28017800, 0x2200d105, 0x46202101, 0xfc0ef01a, 0x48abe03a, 0x28027800, 
+    0x2200d105, 0x46202102, 0xfc04f01a, 0x48a6e030, 0x28037800, 0x2200d12c, 0x46202103, 0xfbfaf01a, 
+    0x48a1e026, 0xb9287800, 0x46112200, 0xf01a4620, 0xe01dfbf1, 0x7800489c, 0xd1052801, 0x21000202, 
+    0xf01a4620, 0xe013fbe7, 0x78004897, 0xd1052802, 0x21012200, 0xf01a4620, 0xe009fbdd, 0x78004892, 
+    0xd1052803, 0x1200f240, 0x46202101, 0xfbd2f01a, 0xb2441c60, 0xdb902c04, 0x7800488b, 0x2007b910, 
+    0x80084983, 0xe92dbd10, 0xb0934ff0, 0xc903a18a, 0x0110e9cd, 0x9008488a, 0x6800488a, 0xd3152812, 
+    0x409cf648, 0xf6469009, 0x900a30ad, 0x707af242, 0xf241900b, 0x900c1029, 0x3063f640, 0xf240900d, 
+    0x900e40e7, 0x20a9f240, 0xe014900f, 0x30a4f244, 0xf2439009, 0x900a401c, 0x4016f241, 0xf640900b, 
+    0x900c003d, 0x505bf240, 0xf240900d, 0x900e207f, 0x104df240, 0xf04f900f, 0x48654280, 0x1000f9b0, 
+    0xf7f01510, 0x2100f966, 0x2000f44f, 0xf92cf7f8, 0x02812001, 0x02032205, 0x3200e9cd, 0x1002e9cd, 
+    0x1e822300, 0x48662108, 0xfcbef00c, 0x462e2500, 0xe01446ab, 0xe00c2400, 0xeb009808, 0xf830204b, 
+    0xfb100014, 0x1945f000, 0x76e0eb46, 0x0001f104, 0x2cffb284, 0xf10bddf0, 0xf0000001, 0xf1bb0bff, 
+    0xdbe70f04, 0xea400ca8, 0x98093a86, 0xd8034550, 0x49552005, 0xe03f7008, 0x49532000, 0x24007008, 
+    0xa909e037, 0xf8511c60, 0x45500020, 0xf851d82f, 0xab092024, 0xf8531c61, 0x1a501021, 0xfbcef01e, 
+    0x0104e9cd, 0xf851a909, 0xeba11024, 0xf01e000a, 0xaa10fbc5, 0x0100e9cd, 0x5c511c61, 0x1a885d12, 
+    0xfba5f01e, 0xe9dd4607, 0xf01e2300, 0xe9cdfc07, 0xe9dd0102, 0xf01e2304, 0xe9cdf9a9, 0xf01e0106, 
+    0xa910fb69, 0x44085d09, 0x70084937, 0x1c60e003, 0x2c06b284, 0xbf00dbc5, 0x78004833, 0x2064b910, 
+    0x70084931, 0x78004830, 0x492f3023, 0xf6407008, 0x10480100, 0xf916f7f0, 0x7801482b, 0x4000f240, 
+    0xf8c0f7f0, 0x21012200, 0xf0094608, 0x2000f80b, 0x80c84926, 0x80488088, 0x46088008, 0xfee0f7f9, 
+    0x21012200, 0xf7f64822, 0xb988fe21, 0x21022201, 0xf7f6481f, 0xb958fe1b, 0x21042202, 0xf7f6481c, 
+    0xb928fe15, 0x21082203, 0xf7f64819, 0xb110fe0f, 0xf7fc2001, 0x2202fe3c, 0xf2402107, 0xf00d10c3, 
+    0x4812fe47, 0xfe9df7f9, 0x0900f04f, 0x0000e034, 0x000385d0, 0xd1800000, 0x00036254, 0x00036240, 
+    0x0003629e, 0x00036227, 0x0003622c, 0x0003626a, 0x000361cc, 0xfffffa00, 0x321e0a05, 0x0064503c, 
+    0x00054000, 0x000361dc, 0x00036226, 0x00036296, 0xd00305c2, 0xf93048f7, 0x49f70019, 0x1000f9b1, 
+    0xdb054288, 0xf9b048f4, 0x49f20000, 0x0019f821, 0x0001f109, 0xf980fa4f, 0x0f04f1b9, 0x48eddbea, 
+    0xfe7ef7f9, 0xf00d2002, 0x2000fdf3, 0xff7af7f9, 0xf7fa2000, 0x2200ffd3, 0x46082101, 0xff92f008, 
+    0xf44f2100, 0xf7f82000, 0x2004f81f, 0xfc98f00e, 0x700849e2, 0xf7f72000, 0x2100f942, 0x780048df, 
+    0xf7f7b240, 0x2100f8c0, 0xf7ef48dd, 0x2001ff82, 0xf935f7f7, 0x48d92100, 0xb2407800, 0xf8b3f7f7, 
+    0x48d72100, 0xff75f7ef, 0xf93af7f7, 0x46112200, 0xf0082001, 0xb013ff67, 0x8ff0e8bd, 0x2000b508, 
+    0x46689000, 0xfd09f7f9, 0x0000f89d, 0xf89db390, 0xb3780001, 0x0002f89d, 0xf89db360, 0xb3480003, 
+    0x0010f242, 0xf872f7f0, 0xf7f82000, 0x2007ff42, 0x800849c4, 0x22002301, 0x48c34619, 0xfd4ff7f6, 
+    0x461a2301, 0x48c02102, 0xfd49f7f6, 0x22022301, 0x48bd2104, 0xfd43f7f6, 0x22032301, 0x48ba2108, 
+    0xfd3df7f6, 0x680048b9, 0xd8032810, 0x0010f242, 0xf84cf7f0, 0xb50ebd08, 0x4280f04f, 0xf9b048b1, 
+    0x15101000, 0xffe5f7ef, 0x49b12000, 0x49b17008, 0x49b17008, 0x49b17008, 0x20017008, 0x700849b0, 
+    0x49b02000, 0x49b07008, 0x46087008, 0xb2407800, 0x780949ac, 0x4aaab249, 0xb2527812, 0x2100e9cd, 
+    0x48a69002, 0xb2437800, 0x780048a3, 0x48a1b242, 0xb2417800, 0x7800489e, 0xf7f7b240, 0x2101f83f, 
+    0x780048a2, 0xf7f7b240, 0x200ff818, 0xf861f7f7, 0xf7f72000, 0xbf00f887, 0xf7f72002, 0x2800f88f, 
+    0xf242d1fa, 0xf7f00040, 0xf7f9f801, 0x2001fee9, 0xfecff7f8, 0xf44f2100, 0xf7f72000, 0xbd0eff65, 
+    0xf04fb510, 0x48874280, 0x1000f9b0, 0xf7ef1510, 0xbd10ff90, 0x2101b510, 0xf7ef0288, 0x2000ffc3, 
+    0x6008498b, 0x11f4f240, 0x4000f240, 0xffbaf7ef, 0x68004888, 0x41f0f040, 0x4000f240, 0xff62f7ef, 
+    0xf2404985, 0xf7ef4000, 0x201eff5d, 0x80084972, 0xf7f92001, 0x2000f8f2, 0xf9914980, 0x4a801000, 
+    0x20015450, 0xf991497d, 0x54501001, 0x497b2002, 0x1002f991, 0x20035450, 0xf9914978, 0x54501003, 
+    0xfb63f00b, 0x49772000, 0xbd107008, 0x4605b570, 0x8ea8460e, 0x7f96f5b0, 0xdc23d07d, 0xd07b28e7, 
+    0x28d2dc0d, 0xdc05d079, 0x28a6b378, 0x28a7d052, 0xe05bd174, 0xd07228d3, 0xd1f928e6, 0xf240e127, 
+    0x1a811203, 0xd06b4290, 0x28f0dc07, 0x28f1d069, 0xf5b0d068, 0xd1eb7f81, 0x291fe179, 0x2920d07e, 
+    0xe1c8d1e6, 0x1245f240, 0x42901a81, 0xdc14d077, 0x7f9ef5b0, 0xdc09d074, 0x102df2a0, 0xd0702800, 
+    0xd06f2807, 0xd1d32808, 0xe015e206, 0x103df2a0, 0xd0682800, 0xd1cb2807, 0x2910e241, 0xdc06d073, 
+    0xd0712907, 0xd0702908, 0xd1c1290f, 0x291be286, 0x291cd06c, 0xe2cbd1bc, 0xf04fe2cc, 0x494a32ff, 
+    0x6800484a, 0xf92af017, 0x1d204604, 0x20a6b948, 0xbd7086a8, 0x49442200, 0x68004844, 0xf91ef017, 
+    0x1d604604, 0x20a7b918, 0xe7f286a8, 0x2c012401, 0xe2afd000, 0x8800483c, 0xd114280f, 0xf9b0483a, 
+    0xf04f1000, 0xf2404224, 0xf7ef4000, 0x2000fed2, 0x80084924, 0xe186e29d, 0xe086e0c6, 0xe091e29b, 
+    0xe0e2e123, 0x4830e0ee, 0x28118800, 0x4830d131, 0x28037800, 0x482ed007, 0x28057800, 0x482cd003, 
+    0x28047800, 0x482bd123, 0xbb007800, 0xf9b04826, 0xf04f1000, 0xf2404220, 0xe0054000, 0xe1ebe13d, 
+    0xe16ee1b2, 0xe1bde18a, 0xfea3f7ef, 0x78004822, 0xd1472801, 0x88004821, 0x4821b150, 0xb2008800, 
+    0xfc27f00f, 0xe226e265, 0xe1fae1ee, 0xe05be253, 0xe063e038, 0x00036296, 0x000385d2, 0x000361f9, 
+    0xc800001c, 0x000385d0, 0xd0035018, 0x000361dc, 0x00036217, 0x00036215, 0x00036210, 0x00036213, 
+    0x000361f7, 0x000361f5, 0x000361ef, 0x000361fd, 0x00036300, 0x00052f88, 0xdcba01f5, 0x00036254, 
+    0x00036240, 0x0003622c, 0x000385d4, 0x000385cc, 0x0003626a, 0x0003845c, 0x0003625c, 0x0003631e, 
+    0x0003631a, 0xfec6f7ff, 0x49fe2002, 0x200a8008, 0x800849fd, 0x48fd2200, 0xf0176800, 0x4604f84d, 
+    0xb9481d20, 0x86a820d2, 0x2200e753, 0x48f749f6, 0xf0176800, 0x4604f841, 0x28001d60, 0x20d3d1a2, 
+    0xe74686a8, 0xe2042401, 0x49ee2000, 0xf04f8008, 0x21134280, 0xf7ef1510, 0xe1fafe2c, 0x880048ea, 
+    0xd18f280a, 0x880048e7, 0xd11f2802, 0xfe88f7ff, 0x49e42001, 0x22008008, 0x48e449e3, 0xf0176800, 
+    0x4604f81b, 0xb9481d20, 0x86a820e6, 0x2200e721, 0x48de49dd, 0xf0176800, 0x4604f80f, 0x28001d60, 
+    0x20e7d1d1, 0xe71486a8, 0xe1d22401, 0x880048d5, 0xd1292801, 0x48d30782, 0x1000f9b0, 0xf7ef1510, 
+    0x2200fdf8, 0x46082101, 0xfd2cf008, 0x49cd2003, 0x22008008, 0x48cd49cc, 0xf0166800, 0x4604ffed, 
+    0xb9481d20, 0x86a820f0, 0x2200e6f3, 0x48c749c6, 0xf0166800, 0x4604ffe1, 0x28001d60, 0x20f1d1a3, 
+    0xe6e686a8, 0xe1a42401, 0x880048be, 0xd12e2803, 0x4280f04f, 0xf9b048bb, 0x15101000, 0xfdc9f7ef, 
+    0xf44f2100, 0xf7f71080, 0xf006fd8f, 0x2004fe54, 0x800849b4, 0x49b42200, 0x680048b4, 0xffbcf016, 
+    0x1d204604, 0xf240b950, 0x86a81002, 0x2200e6c1, 0x48ae49ad, 0xf0166800, 0x4604ffaf, 0x28001d60, 
+    0xf240d1a3, 0x86a81003, 0x2401e6b3, 0x48a5e171, 0x28048800, 0x0702d141, 0xf9b048a2, 0x15101000, 
+    0xfd97f7ef, 0x46112200, 0xf0082001, 0x48a0fccb, 0x28017800, 0xf00bd111, 0x2001fe8f, 0xff0df7f8, 
+    0x20002101, 0xfed3f7f8, 0x20012100, 0xfef3f7f8, 0x46082101, 0xfeddf7f8, 0x2005e14c, 0x80084991, 
+    0x49912200, 0x68004891, 0xff76f016, 0x1d204604, 0xf240b950, 0x86a81022, 0x2200e67b, 0x488b498a, 
+    0xf0166800, 0x4604ff69, 0x28001d60, 0xf240d18b, 0x86a81023, 0x2401e66d, 0x4882e12b, 0x28058800, 
+    0xf7ffd121, 0x2006fd68, 0x8008497e, 0x497e2200, 0x6800487e, 0xff50f016, 0x1d204604, 0xf240b950, 
+    0x86a8102c, 0x2200e655, 0x48784977, 0xf0166800, 0x4604ff43, 0x28001d60, 0xf240d198, 0x86a8102d, 
+    0x2401e647, 0x486fe105, 0x28068800, 0xf7ffd126, 0x2002fd05, 0xfd7df7f7, 0x200ab108, 0x200fe000, 
+    0x80084969, 0x48692200, 0xf0166800, 0x4604ff25, 0xb9501d20, 0x1034f240, 0xe62a86a8, 0x49622200, 
+    0x68004862, 0xff18f016, 0x1d604604, 0xd1b32800, 0x1035f240, 0xe61c86a8, 0xe0da2401, 0x88004859, 
+    0xd1212807, 0xfb5ff7ff, 0x49562010, 0x22008008, 0x48564955, 0xf0166800, 0x4604feff, 0xb9501d20, 
+    0x103cf240, 0xe60486a8, 0x494f2200, 0x6800484f, 0xfef2f016, 0x1d604604, 0xd1042800, 0x103df240, 
+    0xe5f686a8, 0xe0b42401, 0x88004846, 0xd1252810, 0xfa9df7ff, 0xf7f72002, 0xb108fd2c, 0xe000200a, 
+    0x4941200f, 0x22008008, 0x68004840, 0xfed4f016, 0x1d204604, 0xf240b950, 0x86a81044, 0x2200e5d9, 
+    0x483a4939, 0xf0166800, 0x4604fec7, 0xbb481d60, 0x1045f240, 0xe5cc86a8, 0xe08a2401, 0x88004831, 
+    0xd1202812, 0xfa49f7ff, 0x492e2008, 0x22008008, 0x482e492d, 0xf0166800, 0x4604feaf, 0xb9501d20, 
+    0x104cf240, 0xe5b486a8, 0x49272200, 0x68004827, 0xfea2f016, 0x1d604604, 0xf240b920, 0x86a8104d, 
+    0x2401e5a7, 0x481fe065, 0x28088800, 0xf7ffd125, 0x2002f9ef, 0xfcddf7f7, 0x200ab108, 0x200fe000, 
+    0x80084919, 0x48192200, 0xf0166800, 0x4604fe85, 0xb9501d20, 0x1054f240, 0xe58a86a8, 0x49122200, 
+    0x68004812, 0xfe78f016, 0x1d604604, 0xf240bb90, 0x86a81055, 0x2401e57d, 0x480ae03b, 0x280e8800, 
+    0xf04fd137, 0x48074280, 0x1000f9b0, 0xf7ef1510, 0xf242fc60, 0xf7ef0070, 0x200bfcb9, 0x80084902, 
+    0xe007200f, 0x000385d0, 0x000385d4, 0x000385cc, 0x0003625c, 0x80084918, 0x32fff04f, 0x48184917, 
+    0xf0166800, 0x4604fe49, 0xb9581d20, 0x1060f240, 0xe54e86a8, 0x2200e00d, 0x48114910, 0xf0166800, 
+    0x4604fe3b, 0xb9201d60, 0x1061f240, 0xe54086a8, 0xbf002401, 0xbf00e531, 0xe53abf00, 0x2200b510, 
+    0xf2af2101, 0xf0166057, 0x2108fbba, 0xf0162003, 0x4904fd57, 0xbd106008, 0x000385d0, 0x000385d4, 
+    0x00038654, 0x000385cc, 0x2200b510, 0x46082101, 0xfb48f008, 0xf44f2100, 0xf7f72000, 0x2200fbd5, 
+    0x20014611, 0xfb3ef008, 0x46082100, 0xfba3f7f9, 0x0050f242, 0xfc5af7ef, 0xfc8df006, 0x0050f242, 
+    0xfc54f7ef, 0x20012100, 0xfbe5f7f9, 0x200c2100, 0xfb3ff7f9, 0x46082101, 0xfb8df7f9, 0xf814f7fd, 
+    0x0050f242, 0xfc42f7ef, 0x22112300, 0x3100f44f, 0xf7f648a6, 0x2001f8fd, 0xfb0bf7f8, 0xb510bd10, 
+    0x49a32000, 0xf04f6008, 0x21f14220, 0x2000f240, 0xfbcff7ef, 0x0050f242, 0xfc28f7ef, 0xf7f82000, 
+    0x2101faf8, 0xf7f70488, 0xf7fdfb8f, 0xf7f8f83b, 0xbd10fd68, 0x4605b570, 0x8ea8460e, 0xd07728a4, 
+    0x286fdc0b, 0xdc03d030, 0x286eb1a0, 0xe01fd171, 0xd0722890, 0xd1f92891, 0x28ade07e, 0xdc04d06b, 
+    0xd06928a5, 0xd1f128ac, 0x28b6e0c6, 0x28b7d072, 0xe0f6d1ec, 0xf04fe0f7, 0x498632ff, 0x68004886, 
+    0xfdccf016, 0x1d204604, 0x206eb948, 0xbd7086a8, 0x49802200, 0x68004880, 0xfdc0f016, 0x1d604604, 
+    0x206fb918, 0xe7f286a8, 0x2c012401, 0xe0dad000, 0x88004878, 0xd10c280f, 0xf9b04876, 0xf04f1000, 
+    0xf2404223, 0xf7ef2000, 0x2000fb74, 0x80084973, 0x4870e0c8, 0x28128800, 0x4871d14b, 0x28037800, 
+    0x486fd007, 0x28057800, 0x486dd003, 0x28047800, 0x486cd134, 0xbb707800, 0xf9b04866, 0xf04f1000, 
+    0xf2404220, 0xf7ef2000, 0xf7fffb54, 0x2002ff78, 0x80084962, 0x495f200a, 0x22008008, 0x6800485e, 
+    0xfd4af016, 0x1d204604, 0x2090b970, 0xe7ae86a8, 0xe099e03f, 0xe06be001, 0x2200e047, 0x48564955, 
+    0xf0166800, 0x4604fd39, 0x28001d60, 0x2091d1c0, 0xe79c86a8, 0xe001e079, 0xe0832401, 0x494f2000, 
+    0xf04f8008, 0x21095240, 0x2000f240, 0xfb21f7ef, 0x4848e078, 0x280a8800, 0xf04fd174, 0x48475240, 
+    0x1000f9b0, 0x2000f240, 0xfb13f7ef, 0x88004843, 0xd11c2802, 0x4941200a, 0x22008008, 0x483e493d, 
+    0xf0166800, 0x4604fd09, 0xb9481d20, 0x86a820a4, 0x2200e76d, 0x48384937, 0xf0166800, 0x4604fcfd, 
+    0xbb301d60, 0x86a820a5, 0x2401e761, 0x4833e04a, 0x280a8800, 0xf7ffd11e, 0x2006fed7, 0x8008492f, 
+    0x492c2200, 0x6800482c, 0xfce6f016, 0x1d204604, 0x20acb948, 0xe74a86a8, 0x49262200, 0x68004826, 
+    0xfcdaf016, 0x1d604604, 0x20adb918, 0xe73e86a8, 0xe0272401, 0x88004821, 0xd1232806, 0x0070f242, 
+    0xfb24f7ef, 0x491b200b, 0x20078008, 0x8008491b, 0x32fff04f, 0x481c4917, 0xf0166800, 0x4604fcbd, 
+    0xb9481d20, 0x86a820b6, 0x2200e721, 0x48164911, 0xf0166800, 0x4604fcb1, 0xb9181d60, 0x86a820b7, 
+    0x2401e715, 0xe706bf00, 0xbf00bf00, 0xb510e70f, 0x21012200, 0x2043f2af, 0xfa31f016, 0x20032108, 
+    0xfbcef016, 0x60084904, 0x0000bd10, 0xd1800000, 0x00036300, 0x000385e4, 0x000385dc, 0x000385e0, 
+    0x0003626a, 0x0003845c, 0x00038654, 0xf04fb510, 0x48fd42a0, 0x1000f9b0, 0x0000f640, 0xfa79f7ef, 
+    0x2101f240, 0x0000f640, 0xfaacf7ef, 0x49f72000, 0x808880c8, 0x80088048, 0xf7f94608, 0x2000f881, 
+    0x700849f3, 0xf44f2100, 0xf7f73080, 0x2000fa2d, 0x600849f0, 0x600849f0, 0xb50ebd10, 0x0070f242, 
+    0xfab4f7ef, 0xf7f82000, 0x2101f984, 0x780048eb, 0xf7f6b240, 0x2101fab2, 0x780048e9, 0xf7f6b240, 
+    0x2101fab7, 0x780048e7, 0xf7f6b240, 0x2001fabc, 0x700849e5, 0x49e50240, 0x48e58008, 0xb2407800, 
+    0x780949e4, 0x4ae4b249, 0xb2527812, 0x2100e9cd, 0x48dd9002, 0xb2437800, 0x780048e0, 0x48e0b242, 
+    0xb2417800, 0x780048df, 0xf7f6b240, 0x48d7faa7, 0xb2008800, 0xfad5f7f6, 0xf7f62001, 0xbf00faf3, 
+    0xf7f62002, 0x2800fafb, 0x48ccd1fa, 0x49d67800, 0x48cb7008, 0x49c97800, 0x46087008, 0xb2407800, 
+    0xfa30f00b, 0x0070f242, 0xfa60f7ef, 0xf7f6e003, 0x49c6fa4b, 0x48c58008, 0x28008800, 0x2002dd04, 
+    0xfa47f7f7, 0xd1f22800, 0x42a0f04f, 0xf9b048b6, 0xf6401000, 0xf7ef0000, 0xbd0ef9ec, 0xf009b50e, 
+    0xf01bfefe, 0x2801fd75, 0x48c0d17e, 0xf3c079c0, 0x49bf00c0, 0x46087008, 0x28017800, 0xf242d175, 
+    0xf7ef0070, 0x2000fa33, 0xf903f7f8, 0xfe4af7fc, 0x7a4048b6, 0x800849b7, 0x7a0048b4, 0x0003f000, 
+    0xea418809, 0x49b32000, 0x46088008, 0x28408800, 0x2002dd5b, 0xfa04f7f7, 0x680949af, 0x49af1a08, 
+    0x1000f9b1, 0xf0f1fbb0, 0x600849ad, 0x68004608, 0x60081cc0, 0x68004608, 0x4aa81e80, 0x2000f9b2, 
+    0xf102fb00, 0x680048a4, 0xf979f7f7, 0x49962001, 0x48a07008, 0x49a28800, 0x1a408809, 0x80084993, 
+    0x78004893, 0x4993b240, 0xb2497809, 0x78124a92, 0xe9cdb252, 0x90022100, 0x7800488b, 0x488fb243, 
+    0xb2427800, 0x7800488e, 0x488eb241, 0xb2407800, 0xfa04f7f6, 0x88004885, 0xf7f6b200, 0x2001fa32, 
+    0xfa50f7f6, 0x2002bf00, 0xfa58f7f6, 0xd1fa2800, 0x7800487a, 0x70084984, 0x78004879, 0x70084977, 
+    0x78004608, 0xe001b240, 0xe04de01d, 0xf98af00b, 0xf7f6e003, 0x4975f9a9, 0x48748008, 0x28008800, 
+    0x2002dd04, 0xf9a5f7f7, 0xd1f22800, 0x42a0f04f, 0xf9b04865, 0xf6401000, 0xf7ef0000, 0x2007f94a, 
+    0x80084961, 0x21e2e030, 0x0000f640, 0xf97af7ef, 0xf6402100, 0xf7ef0000, 0x4872f925, 0xf4008800, 
+    0xb1a06000, 0x68004870, 0x4870b988, 0xf2406800, 0x428871fc, 0x496eda0b, 0x68124a6c, 0x0082eb01, 
+    0xf896f7ef, 0x68004869, 0x49681d00, 0x48696008, 0x28017800, 0xf242d102, 0xe0007010, 0xf2002000, 
+    0x4865312e, 0xf860f7ef, 0xb510bd0e, 0x42a0f04f, 0xf9b04845, 0xf6401000, 0xf7ef0000, 0xf240f90a, 
+    0x00882100, 0xf93ef7ef, 0x495c2001, 0x485c7008, 0x49437800, 0x21017008, 0x78004840, 0xf7f6b240, 
+    0x2101f95c, 0x7800483e, 0xf7f6b240, 0x2101f961, 0x7800483c, 0xf7f6b240, 0x2000f966, 0xf9c2f7f6, 
+    0x2002bf00, 0xf9caf7f6, 0xd1fa2800, 0x78034835, 0x21382203, 0xf7f5484b, 0x4831fe22, 0x22007803, 
+    0x48482107, 0xfe1bf7f5, 0x7801482d, 0x0000f640, 0xf8b8f7ef, 0x7801482b, 0x0000f640, 0xf8b2f7ef, 
+    0xf7f84841, 0xbd10febe, 0xf04fb50e, 0x481e42a0, 0x1000f9b0, 0x0000f640, 0xf8bbf7ef, 0x493b2001, 
+    0x493b7008, 0x48227008, 0xb2407800, 0x78094921, 0x4a21b249, 0xb2527812, 0x2100e9cd, 0x481a9002, 
+    0xb2437800, 0x7800481d, 0x481db242, 0xb2417800, 0x7800481c, 0xf7f6b240, 0x2101f921, 0x7800480f, 
+    0xf7f6b240, 0x2101f8fa, 0x7800480e, 0xf7f6b240, 0x2000f90a, 0xf966f7f6, 0x2002bf00, 0xf96ef7f6, 
+    0xd1fa2800, 0x0000bd0e, 0x000385f0, 0x00036296, 0x0003630c, 0x00036304, 0x00036308, 0x000361fd, 
+    0x000361fb, 0x000361f9, 0x00036213, 0x0003621a, 0x000361ef, 0x000361f5, 0x000361f7, 0x00036210, 
+    0x00036215, 0x00036217, 0x000361fe, 0x00038fd0, 0x00036214, 0x0003621c, 0x00036230, 0x000384a8, 
+    0x0003623c, 0x0005280c, 0x000362f4, 0x00052800, 0x00050800, 0x000361ee, 0xd03c80b8, 0x00036203, 
+    0x000361fa, 0xd003501a, 0x0003627e, 0x00036205, 0x00036201, 0xf009b510, 0xf01bfd52, 0x2801fbc9, 
+    0x48fad123, 0x09c07980, 0x700849f9, 0x78004608, 0xd14b2801, 0x42a0f04f, 0xf9b048f6, 0xf6401000, 
+    0xf7ef0000, 0x48f1f826, 0xf3c07980, 0x49f21002, 0x48f27008, 0x28017800, 0x2004d103, 0x800849ed, 
+    0x2001e034, 0x800849eb, 0x21e2e030, 0x0000f640, 0xf848f7ef, 0xf6402100, 0xf7ee0000, 0x48e8fff3, 
+    0xf4008800, 0xb1a06000, 0x680048e6, 0x48e6b988, 0xf2406800, 0x428871fc, 0x49e4da0b, 0x68124ae2, 
+    0x0082eb01, 0xff64f7ee, 0x680048df, 0x49de1d00, 0x48da6008, 0x28017800, 0xf242d102, 0xe0007010, 
+    0xf2002000, 0x48da312d, 0xff2ef7ee, 0xb510bd10, 0xfcf5f009, 0xfb6cf01b, 0xd14c2801, 0x42a0f04f, 
+    0xf9b048cc, 0xf6401000, 0xf7ee0000, 0x48c7ffd2, 0x09c07900, 0x700849cf, 0x78004608, 0xd12d2801, 
+    0x780048c6, 0x48c1bb50, 0xf3c07900, 0x49ca1002, 0x20047008, 0xfc04f00d, 0x700849c8, 0x780048bf, 
+    0x4608b9c0, 0x48bc7801, 0x1c807800, 0xdd054281, 0x780048b9, 0x49c11c80, 0xe00b7008, 0x780048b6, 
+    0x49be1e80, 0x42887809, 0x48b3dd04, 0x1e807800, 0x700849ba, 0x49af2002, 0xe03d8008, 0x780048af, 
+    0xd1392801, 0xf00d2004, 0x49b4fbdb, 0x20027008, 0x800849a8, 0x21e2e030, 0x0000f640, 0xffc2f7ee, 
+    0xf6402100, 0xf7ee0000, 0x48a5ff6d, 0xf4008800, 0xb1a06000, 0x680048a3, 0x48a3b988, 0xf2406800, 
+    0x428871fc, 0x49a1da0b, 0x68124a9f, 0x0082eb01, 0xfedef7ee, 0x6800489c, 0x499b1d00, 0x48976008, 
+    0x28017800, 0xf242d102, 0xe0007010, 0xf5002000, 0x4897714b, 0xfea8f7ee, 0xb50ebd10, 0x68004898, 
+    0xd3082812, 0x49972000, 0x21006008, 0x1080f44f, 0xff1af7f6, 0x2040e004, 0xfa08f001, 0x60084991, 
+    0x49912001, 0x21017008, 0x78004890, 0xf7f5b240, 0x488dffa4, 0xb2407800, 0x7809498d, 0x4a8db249, 
+    0xb2527812, 0x2100e9cd, 0x488b9002, 0xb2437800, 0x7800488a, 0x488ab242, 0xb2417800, 0x78004889, 
+    0xf7f5b240, 0x200fffab, 0xffd3f7f5, 0xf7f52000, 0xbf00fff9, 0xf7f62002, 0x2800f801, 0x4876d1fa, 
+    0x49817800, 0xbd0e7008, 0x4605b570, 0x8ea8460e, 0xd07d28e6, 0x28b9dc13, 0xdc07d07b, 0x288ab340, 
+    0x288bd034, 0x28b8d03e, 0xe095d174, 0xd07228ca, 0xd07128cb, 0xd07028d2, 0xd1f528d3, 0xf240e133, 
+    0x1a811203, 0xd0694290, 0x28e7dc09, 0x28fad067, 0x28fbd066, 0xf5b0d07b, 0xd1e57f81, 0x2907e198, 
+    0x2908d076, 0x2911d075, 0x2912d074, 0xe1ead1dc, 0xf04fe1eb, 0x496532ff, 0x68004865, 0xf90ef016, 
+    0x1d204604, 0x208ab948, 0xbd7086a8, 0x495f2200, 0x6800485f, 0xf902f016, 0x1d604604, 0x208bb918, 
+    0xe7f286a8, 0x2c012401, 0xe1ced000, 0x88004857, 0xd10c280f, 0xf9b04855, 0xf04f1000, 0xf6404225, 
+    0xf7ee0000, 0x2000feb6, 0x8008493a, 0x484fe1bc, 0x28138800, 0x484fd15a, 0x28037800, 0x484dd007, 
+    0x28057800, 0x484bd003, 0x28047800, 0x484ad143, 0xbb807800, 0xf9b04845, 0xf04f1000, 0xf6404220, 
+    0xf7ee0000, 0xf7fffe96, 0x482cff38, 0xe0087800, 0xe02ee0e8, 0xe090e19a, 0xe0b7e09c, 0xe0eee145, 
+    0xb918e10c, 0x49232003, 0xe0028008, 0x49212001, 0x200a8008, 0x80084935, 0x48352200, 0xf0166800, 
+    0x4604f87b, 0xb9701d20, 0x86a820b8, 0xe102e79d, 0xe14fe143, 0xe00ee16a, 0x492c2200, 0x6800482c, 
+    0xf86af016, 0x1d604604, 0xd1af2800, 0x86a820b9, 0x2401e78b, 0x2000e168, 0x8008490e, 0x42a0f04f, 
+    0xf640210a, 0xf7ee0000, 0xe15dfe54, 0x8800481f, 0xd19b280a, 0x88004807, 0xd15d2801, 0xfe67f7ff, 
+    0xf7f62002, 0xb3c8fe96, 0xe039200a, 0x00038fd0, 0x00036202, 0x000385f0, 0x000361fa, 0x000361ee, 
+    0x0005280c, 0x000362f4, 0x00052800, 0x00050800, 0xd03c80b8, 0x00036206, 0x000361ff, 0x000361f9, 
+    0x000361dc, 0x000385fc, 0x000361ef, 0x000361fd, 0x000361f5, 0x000361f7, 0x00036213, 0x00036210, 
+    0x00036215, 0x00036217, 0x00036200, 0x000385f4, 0x000385ec, 0x0003626a, 0x0003845c, 0x200fe7ff, 
+    0x80084993, 0x48932200, 0xf0166800, 0x4604f805, 0xb9481d20, 0x86a820ca, 0x2200e727, 0x488d498c, 
+    0xf0156800, 0x4604fff9, 0x28001d60, 0x20cbd192, 0xe71a86a8, 0xe0f72401, 0x88004887, 0xd1242803, 
+    0xfda8f7ff, 0xf7f62002, 0xb108fe34, 0xe000200a, 0x497f200f, 0x22008008, 0x6800487e, 0xffdcf015, 
+    0x1d204604, 0x20d2b948, 0xe6fe86a8, 0x49782200, 0x68004878, 0xffd0f015, 0x1d604604, 0xd1da2800, 
+    0x86a820d3, 0x2401e6f1, 0x4873e0ce, 0x28028800, 0xf7ffd127, 0x4871fcf9, 0x28017800, 0x2003d103, 
+    0x8008496d, 0x2004e002, 0x8008496b, 0x49682200, 0x68004868, 0xffb0f015, 0x1d204604, 0x20e6b948, 
+    0xe6d286a8, 0x49622200, 0x68004862, 0xffa4f015, 0x1d604604, 0xd1ae2800, 0x86a820e7, 0x2401e6c5, 
+    0x485de0a2, 0x28048800, 0xf7ffd127, 0x485bfc7e, 0x28017800, 0x2006d103, 0x80084957, 0x2005e002, 
+    0x80084955, 0x49522200, 0x68004852, 0xff84f015, 0x1d204604, 0x20fab948, 0xe6a686a8, 0x494c2200, 
+    0x6800484c, 0xff78f015, 0x1d604604, 0xd17b2800, 0x86a820fb, 0x2401e699, 0x4847e076, 0x28058800, 
+    0xf7ffd125, 0x2002fb7b, 0xfdb3f7f6, 0x200ab108, 0x200fe000, 0x8008493e, 0x483e2200, 0xf0156800, 
+    0x4604ff5b, 0xb9501d20, 0x1002f240, 0xe67c86a8, 0x49372200, 0x68004837, 0xff4ef015, 0x1d604604, 
+    0xf240bb48, 0x86a81003, 0x2401e66f, 0x4832e04c, 0x28068800, 0xf7ffd120, 0x2007fae0, 0x8008492e, 
+    0x492b2200, 0x6800482b, 0xff36f015, 0x1d204604, 0xf240b950, 0x86a8100a, 0x2200e657, 0x48254924, 
+    0xf0156800, 0x4604ff29, 0xb9201d60, 0x100bf240, 0xe64a86a8, 0xe0272401, 0x8800481f, 0xd1232807, 
+    0xfa94f7ff, 0x491a200b, 0x20098008, 0x8008491a, 0x32fff04f, 0x481a4916, 0xf0156800, 0x4604ff0d, 
+    0xb9501d20, 0x1014f240, 0xe62e86a8, 0x49102200, 0x68004813, 0xff00f015, 0x1d604604, 0xf240b920, 
+    0x86a81015, 0x2401e621, 0xe612bf00, 0xbf00bf00, 0xb510e61b, 0x21012200, 0x4053f2af, 0xfc7ff015, 
+    0x20032108, 0xfe1cf015, 0x60084902, 0x0000bd10, 0x000385f4, 0x000385ec, 0x000385f0, 0x000361ee, 
+    0x00038654, 0xf04fb50e, 0x48fe42c0, 0x1000f9b0, 0x0000f241, 0xfccdf7ee, 0x49fb2000, 0x48fb7008, 
+    0xb2407800, 0x780949fa, 0x4afab249, 0xb2527812, 0x2100e9cd, 0x48f89002, 0xb2437800, 0x780048f7, 
+    0x48f1b242, 0xb2417800, 0x780048f5, 0xf7f5b240, 0x2000fd35, 0xfd86f7f5, 0x2002bf00, 0xfd8ef7f5, 
+    0xd1fa2800, 0x02c82101, 0xfc6ef7f6, 0x0080f242, 0xfcfcf7ee, 0x780048eb, 0xd0312805, 0x780048e9, 
+    0xd02d2803, 0x780048e7, 0x2007b110, 0xff46f003, 0x02c82101, 0xfc58f7f6, 0x0080f242, 0xfce6f7ee, 
+    0x680048e1, 0xd80f2811, 0x780048e0, 0xd10b2801, 0xf8ad2047, 0x48de0004, 0x48da6802, 0x1000f990, 
+    0xf014a801, 0xbf00f82d, 0x780048d8, 0x2000bb98, 0xfa76f7fc, 0xf99048d7, 0xf7fb0000, 0xe02affc3, 
+    0x780048d0, 0xd0032805, 0x780048ce, 0xd1222803, 0x780048cc, 0xd1092805, 0xf8ad204d, 0x48c90004, 
+    0x1000f990, 0xf014a801, 0xe00cf9ea, 0x780048c5, 0xd1082803, 0xf8ad204a, 0x48c20004, 0x1000f990, 
+    0xf013a801, 0x2007fe35, 0xfef8f003, 0x02c82101, 0xfc0af7f6, 0xbd0ebf00, 0x2000b5fe, 0x700849b6, 
+    0x49b12001, 0x48b77008, 0xb9107800, 0x2000f240, 0x2040e000, 0x800849b8, 0x780048b8, 0xd1182804, 
+    0xf99048b0, 0x49af0000, 0xb1907008, 0x49b22020, 0xf2408008, 0x04c011f4, 0xfc54f7ee, 0x31baf64b, 
+    0x7080f04f, 0xfbfef7ee, 0xf04f49ad, 0xf7ee7080, 0x48acfbf9, 0x28027800, 0x01c0d102, 0x800849a6, 
+    0x680048a1, 0xd8022810, 0xf7f72000, 0x4897fb32, 0xb2407800, 0x78094996, 0x4a96b249, 0xb2527812, 
+    0x2100e9cd, 0x48949002, 0xb2437800, 0x78004893, 0x488db242, 0xb2417800, 0x78004891, 0xf7f5b240, 
+    0x4895fc6d, 0xb2008800, 0xfc9bf7f5, 0xf7f52001, 0xbf00fcb9, 0xf7f52002, 0x2800fcc1, 0x2101d1fa, 
+    0xfd37f7f7, 0xf7f5200f, 0xf242fc28, 0xf7ee0080, 0x2002fc2d, 0xfc14f7f6, 0x48824604, 0x28057800, 
+    0x4880d003, 0x28037800, 0x2001d103, 0xfc41f008, 0x2000e002, 0xfbaef008, 0xf7f62002, 0x1a24fc01, 
+    0x7a404881, 0x80084981, 0x7a00487f, 0x0003f000, 0xea418809, 0x497d2000, 0x487d8008, 0x1a246800, 
+    0x88004608, 0x3014eba0, 0x20008008, 0xfad1f7f7, 0x2000e007, 0xfc1df008, 0x88004874, 0x49731e40, 
+    0x48728008, 0x28018800, 0xf242dcf3, 0xf7ee0080, 0x4865fbed, 0x28116800, 0x2003d803, 0xf918f00c, 
+    0x2004e002, 0xf91bf00c, 0x0080f242, 0xfbdef7ee, 0xf7f52001, 0x485bfbd2, 0x28057800, 0x4859d003, 
+    0x28037800, 0x2500d116, 0x2600e00f, 0x4861e009, 0x1005eb00, 0x46315782, 0xf00c4628, 0x1c70fa96, 
+    0x2e10b2c6, 0x1c68dbf3, 0x2d04b2c5, 0x2003dbed, 0xfaa1f00c, 0x0080f242, 0xfbb8f7ee, 0x42c0f04f, 
+    0xf9b04840, 0xf2411000, 0xf7ee0000, 0xbdfefb52, 0x4844b5fe, 0xb9087800, 0xe0002040, 0x46072020, 
+    0x78004846, 0xd1112804, 0x7800483e, 0x2710b170, 0x11f4f240, 0xf7ee0538, 0xf64bfb75, 0x053831ba, 
+    0xfb20f7ee, 0x0538493e, 0xfb1cf7ee, 0x7800483d, 0xd1002802, 0x48332740, 0x28057800, 0x4831d003, 
+    0x28037800, 0x2001d103, 0xfba3f008, 0x2000e002, 0xfb10f008, 0xfeacf01a, 0xd1752801, 0x79c04832, 
+    0x0040f3c0, 0x70084934, 0x78004608, 0xd16c2801, 0x7a40482d, 0x8008492d, 0x7a00482b, 0x0003f000, 
+    0xea418809, 0x49292000, 0x46088008, 0x42b88800, 0x2002dd5b, 0xfb44f7f6, 0x68094928, 0x49281a08, 
+    0x1000f9b1, 0xf0f1fbb0, 0x60084926, 0x68004608, 0x60081cc0, 0x68004608, 0x4a211e80, 0x2000f9b2, 
+    0xf102fb00, 0x6800481d, 0xfab9f7f6, 0x49062001, 0x48167008, 0x491b8800, 0x1a408809, 0x8008490e, 
+    0xe0334802, 0x00038610, 0x00036215, 0x000361ef, 0x000361f5, 0x000361f7, 0x00036213, 0x00036210, 
+    0x00036217, 0x00038b1c, 0x000361dc, 0x000361ee, 0x00038b40, 0x000362b1, 0x0003621a, 0x0003626a, 
+    0xdcba01f5, 0x0003630c, 0x00038fd0, 0x0003621c, 0x00038604, 0x0004c83c, 0x00036216, 0x00036230, 
+    0x000384a8, 0x0003623c, 0xe10be0c2, 0xb2407800, 0x780949fe, 0x4afeb249, 0xb2527812, 0x2100e9cd, 
+    0x48fc9002, 0xb2437800, 0x780048fb, 0x48fbb242, 0xb2417800, 0x780048fa, 0xf7f5b240, 0x48f9fb0f, 
+    0xb2008800, 0xfb3df7f5, 0xf7f52001, 0xbf00fb5b, 0xf7f52002, 0x2800fb63, 0x2101d1fa, 0xfbd9f7f7, 
+    0xf9bef7f8, 0xf7f5200f, 0xf242fac8, 0xf7ee0080, 0x48edfacd, 0xb9387800, 0x200c2100, 0xf9b9f7f8, 
+    0x46082101, 0xfa07f7f8, 0xf7f62002, 0x4604faa9, 0x780048e5, 0xd0032805, 0x780048e3, 0xd1032803, 
+    0xf0082001, 0xe002fad6, 0xf0082000, 0x2002fa43, 0xfa96f7f6, 0x48dd1a24, 0x49dd7a40, 0x48db8008, 
+    0xf0007a00, 0x88090003, 0x2000ea41, 0x800849d8, 0x680048d8, 0x46081a24, 0xeba08800, 0x80083014, 
+    0xfeb0f7fb, 0x2000e007, 0xfab3f008, 0x880048d0, 0x49cf1e40, 0x48ce8008, 0x28018800, 0xf242dcf3, 
+    0xf7ee0080, 0x2004fa83, 0xffb9f00b, 0x0080f242, 0xfa7cf7ee, 0xf7f52001, 0x48c3fa70, 0x28057800, 
+    0x48c1d003, 0x28037800, 0x2500d116, 0x2600e00f, 0x48c1e009, 0x1005eb00, 0x46315782, 0xf00c4628, 
+    0x1c70f934, 0x2e10b2c6, 0x1c68dbf3, 0x2d04b2c5, 0x2003dbed, 0xf93ff00c, 0x780048b8, 0xd1062802, 
+    0xfe70f7fb, 0xf7ee48b6, 0x49b6f92f, 0xf2426008, 0xf7ee0080, 0xf04ffa4b, 0x48b342c0, 0x1000f9b0, 
+    0x0000f241, 0xf9e5f7ee, 0x49af200b, 0xe0498008, 0x680048ae, 0x49ad1c40, 0x21e26008, 0x0000f241, 
+    0xfa10f7ee, 0x680148a9, 0x0000f241, 0xf9baf7ee, 0x880048a7, 0x5080f400, 0x48a6b1a0, 0xb9886800, 
+    0x680048a5, 0x71fcf240, 0xda0b4288, 0x4aa249a3, 0xeb016812, 0xf7ee0082, 0x489ff92b, 0x1d006800, 
+    0x6008499d, 0x7800489e, 0xd1022801, 0x7010f242, 0x2000e000, 0x714cf500, 0xf7ee489a, 0x489af8f5, 
+    0xf0007800, 0xeb000007, 0x49981000, 0x0020f851, 0x49951c40, 0xf0017809, 0xeb010107, 0x4a931101, 
+    0x0021f842, 0xb50ebdfe, 0x42c0f04f, 0xf9b04886, 0xf2411000, 0xf7ee0000, 0x2104f98c, 0xf7ee0288, 
+    0x2101f9c1, 0xf7f60308, 0x2000f94f, 0xf879f00c, 0x78004875, 0xd0062805, 0x78004873, 0xd0022803, 
+    0xf00c2003, 0xf242f8b8, 0xf7ee0080, 0x2000f9cf, 0x70084969, 0x497e2001, 0xbf007008, 0xf7f52002, 
+    0x2800fa4d, 0x487bd1fa, 0xb2407800, 0x7809495f, 0x4a5fb249, 0xb2527812, 0x2100e9cd, 0x485d9002, 
+    0xb2437800, 0x7800485c, 0x485cb242, 0xb2417800, 0x7800485b, 0xf7f5b240, 0x2000f9d1, 0xfa22f7f5, 
+    0xf7ee486d, 0xf008f88b, 0xbf00f900, 0xf7f52002, 0x2800fa25, 0xbd0ed1fa, 0x4868b5fe, 0x1e407800, 
+    0x0503f000, 0x78004866, 0x07801e40, 0x48650f04, 0x1105eb00, 0x5c081ce0, 0x48620601, 0x1205eb00, 
+    0x5c101ca0, 0x4100ea41, 0xeb00485e, 0x1c601205, 0xea415c10, 0x495b2000, 0x1105eb01, 0xea405d09, 
+    0xbf000601, 0xf7f52002, 0x2800f9f9, 0x4856d1fa, 0xb2437800, 0x78004855, 0x4851b242, 0xb2417800, 
+    0x7800484e, 0xf7f5b240, 0x4630f9c3, 0xf9d2f7f5, 0x78004848, 0x492db240, 0xb2497809, 0x78124a2c, 
+    0xe9cdb252, 0x90022100, 0x7800482a, 0x482ab243, 0xb2427800, 0x78004829, 0x4829b241, 0xb2407800, 
+    0xf96cf7f5, 0xf7f52000, 0xf04ff9bd, 0x482e42c0, 0x1000f9b0, 0x0000f241, 0xf900f7ee, 0xe92dbdfe, 
+    0x270041f0, 0x78004820, 0xd0032805, 0x7800481e, 0xd1032803, 0xf0082001, 0xe002f94c, 0xf0082001, 
+    0x2601f8b9, 0x78004826, 0xd1122801, 0x78004816, 0x482fb978, 0xfd94f7f7, 0xe0082500, 0xf850482c, 
+    0x492c0025, 0xd9004288, 0x1c682600, 0x2d04b2c5, 0x2e00dbf4, 0xf01ad07d, 0x2801fc3b, 0x480bd179, 
+    0xf3c079c0, 0x49240080, 0xe0477008, 0x000361f5, 0x000361f7, 0x00036213, 0x00036210, 0x00036215, 
+    0x00036217, 0x0003621a, 0x00038b1c, 0x00038fd0, 0x0003621c, 0x00038604, 0x0004c83c, 0x0003630c, 
+    0xc800012c, 0x00036310, 0x00038610, 0x0003634c, 0x0005280c, 0x000362f4, 0x00052800, 0x00050800, 
+    0x000361ee, 0xd03c80b8, 0x00038b38, 0x00048c18, 0x00036212, 0x000361ef, 0xd0035120, 0x0003620a, 
+    0x0003620b, 0x00038e90, 0x00036209, 0x00036208, 0x00038fe0, 0x0001a02b, 0x00036211, 0x78004608, 
+    0xd1762801, 0x7a4048fe, 0x49fe0980, 0x48fc7008, 0xf3c07a40, 0x49fc1001, 0x48f97008, 0xf3c07a40, 
+    0x49fa0081, 0x48f67008, 0xf0007a40, 0x49f80003, 0x48f67008, 0x49f77800, 0x42887809, 0x48f4d105, 
+    0x49f57800, 0x42887809, 0x48f0d07e, 0x1e407800, 0xe0d6e000, 0x0503f000, 0x780048ed, 0x07801e40, 
+    0x48e70f04, 0x28807a80, 0x2081d102, 0x728849e4, 0x7ac048e3, 0xd1022880, 0x49e12081, 0x48e072c8, 
+    0x28807b00, 0x2081d102, 0x730849dd, 0x7b4048dc, 0xd1022880, 0x49da2081, 0x48e07348, 0x28057800, 
+    0x48ded028, 0x28037800, 0x48d5d024, 0x42407a80, 0x4621b242, 0xf00b4628, 0x48d1ff28, 0x42407ac0, 
+    0x1c60b242, 0x4628b2c1, 0xff1ff00b, 0x7b0048cc, 0xb2424240, 0xb2c11ca0, 0xf00b4628, 0x48c8ff16, 
+    0x42407b40, 0x1ce0b242, 0x4628b2c1, 0xff0df00b, 0xe07ee023, 0x7a8048c2, 0xb2404240, 0xeb0149c8, 
+    0x55081105, 0x7ac048be, 0xb2414240, 0xeb0048c4, 0x1c601205, 0x48ba5411, 0x42407b00, 0x48c0b241, 
+    0x1205eb00, 0x54111ca0, 0x7b4048b5, 0xb2414240, 0xeb0048bb, 0x1ce01205, 0x48ba5411, 0x28017800, 
+    0x2701d013, 0xe00048b1, 0x7800e00f, 0x700849b1, 0x780048af, 0x700849b0, 0x780048ae, 0x4608b928, 
+    0xb9107800, 0x49af2001, 0x48af7008, 0x28017800, 0x48a4d030, 0x49ad7800, 0x42887809, 0x48a2d12a, 
+    0x49ab7800, 0x42887809, 0x2701d124, 0x7800489d, 0x489db930, 0xb9187800, 0x49a32001, 0xe0197008, 
+    0x780048a3, 0x49a21c40, 0x46087008, 0x28047800, 0x2000db01, 0x489e7008, 0x28017800, 0x489bd10a, 
+    0x1c407800, 0x70084999, 0x78004608, 0xdb012804, 0x70082000, 0x42c0f04f, 0xf9b04896, 0xf2411000, 
+    0xf7ed0000, 0x2f00ff8b, 0x2007d068, 0x80084991, 0x488ce064, 0x28007800, 0x2008d060, 0x8008498d, 
+    0x488de05c, 0x1c406800, 0x6008498b, 0x88004608, 0x0008f3c0, 0xd1232801, 0x030021e2, 0xff82f7ed, 
+    0x68014885, 0x0000f241, 0xff2cf7ed, 0x88004883, 0x5080f400, 0x4882b1a0, 0xb9886800, 0x68004881, 
+    0x71fcf240, 0xda0b4288, 0x4a7e497f, 0xeb016812, 0xf7ed0082, 0x487bfe9d, 0x1d006800, 0x60084979, 
+    0x7800487a, 0xd1022801, 0x7010f242, 0x2000e000, 0x312ff200, 0xf7ed4876, 0x4876fe67, 0xf0007800, 
+    0xeb000007, 0x49741000, 0x0020f851, 0x49711c40, 0xf0017809, 0xeb010107, 0x4a6f1101, 0x0021f842, 
+    0x7800485e, 0x4864b950, 0x280a6800, 0x4867db06, 0x28017800, 0x2010d102, 0x8008495e, 0x81f0e8bd, 
+    0xf04fb53e, 0x485b42c0, 0x1000f9b0, 0x0000f241, 0xfeeff7ed, 0x78004851, 0xf242b168, 0xf7ed0080, 
+    0x2000ff45, 0x7809495b, 0x0107f001, 0x1101eb01, 0xf8424a59, 0x20010021, 0x70084958, 0x70084958, 
+    0x78004858, 0x4958b240, 0xb2497809, 0x78124a57, 0xe9cdb252, 0x90022100, 0x78004855, 0x4850b243, 
+    0xb2427800, 0x78004853, 0x4853b241, 0xb2407800, 0xff44f7f4, 0x49372000, 0x49377008, 0x20017008, 
+    0x7008493a, 0x7008493a, 0x78004834, 0xd0032805, 0x78004832, 0xd1142803, 0xe00f2100, 0xe0092000, 
+    0xeb024a46, 0x5c121201, 0xeb034b45, 0x541a1301, 0xb2101c42, 0xdbf32810, 0xb2d11c4a, 0xdbed2904, 
+    0x2000e022, 0xfc20f008, 0x493db245, 0xf7f44628, 0x2001f956, 0xfc18f008, 0x4939b245, 0x46283110, 
+    0xf94df7f4, 0xf0082002, 0xb245fc0f, 0x31204934, 0xf7f44628, 0x2003f944, 0xfc06f008, 0x4930b245, 
+    0x46283130, 0xf93bf7f4, 0x78c0482d, 0x492c0600, 0xea407889, 0x492a4001, 0xea407849, 0x49282001, 
+    0xea407809, 0x480c0401, 0xb2437800, 0x78004809, 0x480fb242, 0xb2417800, 0x7800480c, 0xe041b240, 
+    0x00038fd0, 0x0003620c, 0x0003620d, 0x0003620e, 0x0003620f, 0x00036208, 0x00036209, 0x00038b1c, 
+    0x0004c83c, 0x00036225, 0x00036224, 0x0003620a, 0x0003620b, 0x00038610, 0x0003634c, 0x0005280c, 
+    0x000362f4, 0x00052800, 0x00050800, 0x000361ee, 0xd03c80b8, 0x00038b38, 0x00048c18, 0x000361f1, 
+    0x00036210, 0x000361ef, 0x000361f5, 0x000361f7, 0x00036213, 0x00036215, 0x00036217, 0x000442c8, 
+    0x00038e90, 0xfed4f7f4, 0xf7f44620, 0x2000fee3, 0xfee8f7f4, 0x2002bf00, 0xfef0f7f4, 0xd1fa2800, 
+    0x780048fe, 0x49feb950, 0x0000f991, 0xf7f449fd, 0x4afdf8c6, 0x48fb2104, 0xfa52f01a, 0xf99149f8, 
+    0xf0070000, 0xbd3efd83, 0xb087b500, 0x42c0f04f, 0xf9b048f6, 0xf2411000, 0xf7ed0000, 0xf7f7fdea, 
+    0xf242fd18, 0xf7ed0050, 0x48f1fe41, 0x28037800, 0x2000d110, 0x46039000, 0x210e1e42, 0xf2409001, 
+    0xf7f62000, 0xf7fbfac8, 0xf242f9ff, 0xf7ed0070, 0xe04ffe2d, 0x780048e7, 0xd1062803, 0x4611220c, 
+    0x4000f240, 0xfb62f7f6, 0x220ce005, 0xf2404611, 0xf7f61000, 0xf242fb5b, 0xf7ed0070, 0x48defe17, 
+    0xb9087800, 0xf9e0f7fb, 0x23012000, 0x3002e9cd, 0x90059004, 0x9000200c, 0x4611220e, 0x03189001, 
+    0xfbcff7f6, 0x0070f242, 0xfe00f7ed, 0x780048d2, 0x48d0b9b0, 0x28047800, 0x48ced003, 0x28057800, 
+    0x48c6d10e, 0xb9587800, 0x20012100, 0xfd83f7f7, 0x200c2100, 0xfcddf7f7, 0x46082101, 0xfd2bf7f7, 
+    0x220c2301, 0x200e4619, 0xfc62f7f6, 0x0070f242, 0xfddcf7ed, 0x30b8f44f, 0xfa93f7f7, 0xf240b178, 
+    0xf24111f4, 0xf7ed0000, 0x49bcfdad, 0x0000f241, 0xfd58f7ed, 0xf24149ba, 0xf7ed0000, 0xb007fd53, 
+    0xb510bd00, 0x42c0f04f, 0xf9b048b0, 0xf2411000, 0xf7ed0000, 0x48b0fd5e, 0xb9087800, 0xfff9f004, 
+    0x780048ac, 0xd0032803, 0x880048ae, 0xd1022801, 0xfdc4f006, 0xf006e001, 0x48a7ffa2, 0x28017800, 
+    0xf004d101, 0xf005ffe6, 0xbd10f83a, 0x4ff0e92d, 0x4605b085, 0xb290f8df, 0x5780f50b, 0x6000f5a7, 
+    0x20029004, 0x22052100, 0xe9cd0243, 0xe9cd3200, 0x23011002, 0x21052207, 0xf00a4658, 0x2001f895, 
+    0x0065eba0, 0xe036b206, 0x0800f04f, 0xebc02001, 0xfa0f0065, 0xe020f980, 0x0019f93b, 0xdd052800, 
+    0x0106eb09, 0xf8309804, 0xb1480011, 0x0019f93b, 0xdc0a2800, 0x0106eb09, 0xf8309804, 0xb1200011, 
+    0x0001f108, 0xf880fa0f, 0xf1a8e003, 0xfa0f0001, 0xf109f880, 0xfa0f0001, 0xf240f980, 0xeba04000, 
+    0x45480065, 0x2001dcd8, 0x0065ebc0, 0xf8271b80, 0x1c708010, 0xebb6b206, 0xdbc50f65, 0x26002400, 
+    0xf937e012, 0xf9370016, 0x29001014, 0x460adb01, 0x424ae000, 0xdb012800, 0xe0004603, 0x429a4243, 
+    0x4634da00, 0xb2061c70, 0x42b01e68, 0x1e60dce9, 0x0010f837, 0x1014f837, 0x1c604401, 0x0010f837, 
+    0xfa0f4408, 0x1e60f880, 0x0010f837, 0x1c604241, 0x0010f837, 0xfa0f4408, 0xf240fa80, 0xf24111f4, 
+    0xf7ed0000, 0x4621fcef, 0x0000f241, 0xfc9af7ed, 0xf2414651, 0xf7ed0000, 0x4641fc95, 0x0000f241, 
+    0xfc90f7ed, 0xf2414629, 0xf7ed0000, 0x0221fc8b, 0x0000f241, 0xfc86f7ed, 0x210aea4f, 0x0000f241, 
+    0xfc80f7ed, 0x200aea4f, 0xf0f8fb90, 0x2004eb00, 0x90034601, 0x0000f241, 0xfc74f7ed, 0x200aea4f, 
+    0xf0f8fb90, 0x2004eb00, 0xeba01069, 0x46012001, 0xf2419003, 0xf7ed0000, 0x4941fc65, 0x0000f241, 
+    0xfc60f7ed, 0x200aea4f, 0xf0f8fb90, 0x2004eb00, 0xeba01069, 0xb0052001, 0x8ff0e8bd, 0xb087b530, 
+    0x42c0f04f, 0xf9b04831, 0xf2411000, 0xf7ed0000, 0x4831fc60, 0x28017800, 0x2101d108, 0xf7f50480, 
+    0x2000fc23, 0xfb85f7f6, 0xf8ccf7fb, 0x0080f242, 0xfcacf7ed, 0x6800482d, 0xd2032811, 0x78004826, 
+    0xd1112801, 0x23012000, 0x3002e9cd, 0x90059004, 0x9000200c, 0x4611220d, 0x02589001, 0xfa61f7f6, 
+    0x0080f242, 0xfc92f7ed, 0x21012200, 0xf0064608, 0x4819fb69, 0x28007800, 0xf7fbd170, 0x2101f855, 
+    0xf7f50408, 0x2000fbf1, 0xe9cd2301, 0x90043002, 0x200c9005, 0x220d9000, 0x90014611, 0xf7f60298, 
+    0xf242fa40, 0xf7ed0080, 0x2000fc71, 0xe9cd2301, 0x90043002, 0x200c9005, 0xe0199000, 0x00038b1c, 
+    0x00036240, 0x00038e90, 0x00038ed0, 0x00038610, 0x0003625c, 0x0003626a, 0x000361ee, 0x77777771, 
+    0xdcba01f5, 0x000361cc, 0x00054000, 0x000361dc, 0x4611220e, 0x03189001, 0xfa13f7f6, 0x0080f242, 
+    0xfc44f7ed, 0xf810f7fb, 0x780048fe, 0x48feb970, 0xb1587800, 0x20012100, 0xfbcdf7f7, 0x200c2100, 
+    0xfb27f7f7, 0x46082101, 0xfb75f7f7, 0xf99048f6, 0x49f50000, 0x1000f991, 0xf9924af3, 0x23012000, 
+    0x3202e9cd, 0x1004e9cd, 0x9000200c, 0x4611220e, 0x03189001, 0xf9e5f7f6, 0xe7ffe030, 0xf99048ea, 
+    0x49e90000, 0x1000f991, 0xf9924ae7, 0x23012000, 0x3202e9cd, 0x1004e9cd, 0x9000200c, 0x4611220d, 
+    0x02989001, 0xf9cdf7f6, 0x0080f242, 0xfbfef7ed, 0xf99048dd, 0x49dc0000, 0x1000f991, 0xf9924ada, 
+    0x23012000, 0x3202e9cd, 0x1004e9cd, 0x9000200c, 0x4611220e, 0x03589001, 0xf9b3f7f6, 0x0080f242, 
+    0xfbe4f7ed, 0x46112200, 0xf0062001, 0xf242fabb, 0xf7ed0080, 0x48cdfbdb, 0xb9b07800, 0xf99048ca, 
+    0x49c90000, 0x1000f991, 0xf9924ac7, 0x23012000, 0x3202e9cd, 0x1004e9cd, 0x9000200c, 0x4611220e, 
+    0x03989001, 0xf98df7f6, 0x48bfe015, 0x0000f990, 0xf99149bd, 0x4abc1000, 0x2000f992, 0xe9cd2301, 
+    0xe9cd3202, 0x200c1004, 0x220e9000, 0x90014611, 0xf7f60358, 0xf242f976, 0xf7ed0080, 0xf44ffba7, 
+    0xf7f73090, 0xb178f85e, 0x11f4f240, 0x0000f241, 0xfb78f7ed, 0xf24149ae, 0xf7ed0000, 0x49adfb23, 
+    0x0000f241, 0xfb1ef7ed, 0x680048ab, 0xd3012812, 0xe0042400, 0x2000f240, 0xfde8f7ff, 0xf2404604, 
+    0xf24111f4, 0xf7ed0000, 0x4625fb5d, 0xeb0417e0, 0x12016010, 0x0000f241, 0xfb04f7ed, 0xf2414621, 
+    0xf7ed0000, 0x499bfaff, 0x0000f241, 0xfafaf7ed, 0x78004896, 0x2301b930, 0x4619220c, 0xf7f6200e, 
+    0xe005f9e7, 0x220c2301, 0x200e4619, 0xf9e0f7f6, 0xf44f2100, 0xf7f51000, 0xf242fac7, 0xf7ed0080, 
+    0xb007fb55, 0xb510bd30, 0x42c0f04f, 0xf9b0488b, 0xf2411000, 0xf7ed0000, 0xf008faec, 0xb118ff6f, 
+    0x4986200e, 0xe0118008, 0x49842010, 0x48848008, 0x49847800, 0x48827008, 0x70487840, 0x78804880, 
+    0x487f7088, 0x70c878c0, 0xfedff008, 0xb510bd10, 0x42c0f04f, 0xf9b04879, 0xf2411000, 0xf7ed0000, 
+    0xf005fac8, 0x2012f873, 0x80084974, 0xb510bd10, 0x42c0f04f, 0xf9b04871, 0xf2411000, 0xf7ed0000, 
+    0xf7fcfab8, 0x2000f82d, 0xf9e3f7f6, 0xf990486e, 0x1c400000, 0x2011b118, 0x80084968, 0x496be082, 
+    0x1000f991, 0x17c11c48, 0x7191eb00, 0xeba01089, 0xb2490181, 0x70114a65, 0xe0712400, 0x78004864, 
+    0xd0032803, 0x88004863, 0xd1522801, 0x78004860, 0xd1262804, 0x7800485d, 0x2200b928, 0x46204611, 
+    0xfca8f017, 0x4859e05a, 0x28017800, 0x2200d105, 0x46202101, 0xfc9ef017, 0x4854e050, 0x28027800, 
+    0x2200d105, 0x46202102, 0xfc94f017, 0x484fe046, 0x28037800, 0x2200d142, 0x46202103, 0xfc8af017, 
+    0x484ae03c, 0xb9287800, 0x46112200, 0xf0174620, 0xe033fc81, 0x78004845, 0xd1052801, 0x21000202, 
+    0xf0174620, 0xe029fc77, 0x78004840, 0xd1052802, 0x21012200, 0xf0174620, 0xe01ffc6d, 0x7800483b, 
+    0xd11b2803, 0x1200f240, 0x46202101, 0xfc62f017, 0x4837e014, 0x28057800, 0x4835d003, 0x28047800, 
+    0x4832d10c, 0xb1287800, 0x2100f240, 0xf7fa4620, 0xe003fecd, 0x46204930, 0xfec8f7fa, 0xb2441c60, 
+    0xdb8b2c04, 0xb570bd10, 0x42c0f04f, 0xf9b04823, 0xf2411000, 0xf7ed0000, 0xf242fa1c, 0xf7ed0070, 
+    0x481afa75, 0x28017800, 0xf7f6d17c, 0x2300f9b6, 0xf44f2211, 0x48213100, 0xff2af7f3, 0xf7f62001, 
+    0x481ff938, 0xf940f7ed, 0x48134605, 0x28106800, 0x481cd801, 0x2000e000, 0xbf001a2d, 0x0070f242, 
+    0xfa54f7ed, 0xf7f62000, 0xf008f924, 0x4604fe2b, 0xf504b354, 0x10484180, 0xfcd5f7f6, 0xf7f62000, 
+    0xe022fd82, 0x00038b1c, 0x00038612, 0x000361ee, 0x77777772, 0xdcba01f5, 0x000361dc, 0x00038610, 
+    0x00036254, 0x00036240, 0x00036227, 0x0003622c, 0x0003626a, 0x000361cc, 0xfffffa00, 0xd1800000, 
+    0xc800012c, 0x01e84800, 0x2001e007, 0xf8f1f7f6, 0x04882101, 0xf988f7f5, 0x2001e006, 0xf8e9f7f6, 
+    0x04082101, 0xf980f7f5, 0x21022201, 0xf7f348ef, 0x2801fee6, 0x2200d007, 0x48ec2101, 0xf7f31d00, 
+    0x2801fede, 0xe005d100, 0x300c48e8, 0xf8dcf7ed, 0xd8a342a8, 0x2001bf00, 0xf8cbf7f6, 0x04882101, 
+    0xf962f7f5, 0x780048e2, 0xd10d2801, 0xfea7f007, 0xfd1ef019, 0xd1032801, 0x49de200e, 0xe0068008, 
+    0x49dc2010, 0xe0028008, 0x49da200e, 0xbd708008, 0x4668b57c, 0xff75f7f6, 0x25002400, 0xf93de02e, 
+    0x28010014, 0x2501dc28, 0x780048d3, 0x2003b170, 0xfe0ff7f8, 0x780048d1, 0xda03280a, 0xf7f82005, 
+    0xe00afef5, 0xf7f82000, 0xe006fef1, 0xf7f82005, 0x2102feca, 0xf7f92004, 0x2100fb6a, 0x3080f44f, 
+    0xf922f7f5, 0x49c6221e, 0xf7fc48c6, 0x2100f9f5, 0xf7f52080, 0xe003f919, 0xb2441c60, 0xdbce2c04, 
+    0x2d01bf00, 0x48bcd003, 0x28017800, 0x48b8d126, 0xb9e87800, 0x46082100, 0xf8ddf7f7, 0xf9cbf004, 
+    0x20012100, 0xf927f7f7, 0x200c2100, 0xf881f7f7, 0x46082101, 0xf8cff7f7, 0xfd56f7fa, 0x22112300, 
+    0x3100f44f, 0xf7f348b0, 0x2001fe43, 0xf851f7f6, 0xf8c3f7f6, 0x0050f242, 0xf978f7ed, 0xb510bd7c, 
+    0x42c0f04f, 0xf9b048a3, 0xf2411000, 0xf7ed0000, 0xf242f910, 0xf7ed0070, 0x2100f969, 0x3080f44f, 
+    0xf8d2f7f5, 0x7800489a, 0xd1032801, 0x05002100, 0xf8caf7f5, 0x0080f242, 0xf958f7ed, 0x4998221e, 
+    0xf7fc4898, 0x4899f999, 0xb9087800, 0xff70f7ff, 0x7800488f, 0xf7fab908, 0xbd10fd17, 0x4894b510, 
+    0xb1187800, 0x7800488d, 0xdb032832, 0x78004891, 0xd1012801, 0xe0002001, 0x49872000, 0x46087008, 
+    0xb1e07800, 0x42c0f04f, 0xf9b04882, 0xf2411000, 0xf7ed0000, 0x2000f8ce, 0xfffbf7f5, 0x7800487c, 
+    0xf7fab908, 0xf7f8fd3f, 0x2200fecd, 0x46082101, 0xfff8f005, 0xf44f2100, 0xf7f52080, 0xbd10f885, 
+    0xf04fb50e, 0x487342c0, 0x1000f9b0, 0x0000f241, 0xf8aff7ed, 0x49782000, 0x20027008, 0x70084977, 
+    0x78004608, 0x4976b240, 0xb2497809, 0x78124a75, 0xe9cdb252, 0x90022100, 0x7800486f, 0x4872b243, 
+    0xb2427800, 0x78004871, 0x4871b241, 0xb2407800, 0xf914f7f4, 0xf7f42000, 0xbf00f965, 0xf7f42002, 
+    0x2800f96d, 0x485ad1fa, 0xb9207800, 0x7800485f, 0x2001b908, 0x2000e000, 0x70084966, 0x3040f640, 
+    0x60084965, 0x78004865, 0xd1042804, 0x68004608, 0x60080080, 0x4861e008, 0x28057800, 0x485ed104, 
+    0x00406800, 0x6008495c, 0xb570bd0e, 0x460e4605, 0xf2408ea8, 0x1a811237, 0xd0794290, 0xf5b0dc32, 
+    0xd0767f87, 0x28efdc16, 0xdc07d074, 0x28c4b3c8, 0x28c5d062, 0x28eed06f, 0xe100d16e, 0x7f80f5b0, 
+    0xf2a0d06b, 0x28001001, 0x2807d068, 0x2808d067, 0xe15dd1f2, 0x121bf240, 0x42901a81, 0xdc0ad060, 
+    0x100ff2a0, 0xd05c2800, 0xd05b2805, 0xd05a2806, 0xd1e1280b, 0x2905e1a7, 0x2906d056, 0x291bd055, 
+    0xe1edd1da, 0xd07f2944, 0x2927dc15, 0xdc09d07e, 0xd07c2907, 0xd07b2908, 0xd07a291d, 0xd1cb291e, 
+    0xe01be249, 0xd0752928, 0xd074292f, 0xd0732930, 0xd1c12943, 0x2967e2c1, 0xdc08d06f, 0xd06d2957, 
+    0xd06c2958, 0xd06b295f, 0xd1b52960, 0x2968e31a, 0x2971d067, 0x2972d07b, 0xe361d1ae, 0xf04fe362, 
+    0x492732ff, 0x68004827, 0xfa28f014, 0x1d204604, 0x20c4b948, 0xbd7086a8, 0x49212200, 0x68004821, 
+    0xfa1cf014, 0x1d604604, 0x20c5bbf8, 0xe7f286a8, 0xe112e1b4, 0xe045e0a1, 0xe0c5e345, 0xe0e9e0d2, 
+    0xe118e15f, 0xe139e12c, 0xe17de170, 0xc8000120, 0x000361ee, 0x00038610, 0x000384d7, 0x00036226, 
+    0x450f6429, 0x43e187ae, 0xd1800000, 0x00038b1c, 0x00038464, 0x00038465, 0x00036213, 0x000361ef, 
+    0x000361f5, 0x000361f7, 0x00036210, 0x00036215, 0x00036217, 0x00038612, 0x00038604, 0x0003626a, 
+    0x00038618, 0x0003860c, 0xe00ce265, 0xe18de1eb, 0xe1c2e19a, 0xe21ee1f5, 0xe2cbe22b, 0xe287e27b, 
+    0xe2d4e2a3, 0x2c012401, 0xe2fbd000, 0x880048fc, 0xd10d280f, 0xf9b048fa, 0xf04f1000, 0xf2414226, 
+    0xf7ec0000, 0x2000ff86, 0x800849f6, 0xe2dae2e9, 0x880048f3, 0xd14d2814, 0x780048f3, 0xd0072803, 
+    0x780048f1, 0xd0032805, 0x780048ef, 0xd1362804, 0x780048ee, 0x48eabb80, 0x1000f9b0, 0x4220f04f, 
+    0x0000f241, 0xff65f7ec, 0xfeaaf7ff, 0x780048e8, 0xd1032803, 0x49e3200e, 0xe0028008, 0x49e12013, 
+    0x200a8008, 0x800849de, 0x48e22200, 0xf0146800, 0x4604f953, 0xb9481d20, 0x86a820ee, 0x2200e75b, 
+    0x48dc49d7, 0xf0146800, 0x4604f947, 0x28001d60, 0x20efd1bc, 0xe74e86a8, 0x2401e001, 0x2000e2a1, 
+    0x800849d0, 0x42c0f04f, 0xf241210d, 0xf7ec0000, 0xe296ff30, 0x880048ca, 0xd1a7280a, 0x880048c9, 
+    0xd1212813, 0xfe3af7ff, 0x49c62001, 0x22008008, 0x48c849c3, 0xf0146800, 0x4604f91f, 0xb9501d20, 
+    0x1000f240, 0xe72686a8, 0x49bd2200, 0x680048c1, 0xf912f014, 0x1d604604, 0xd1872800, 0x1001f240, 
+    0xe71886a8, 0xe26c2401, 0x880048b6, 0xd1212801, 0xfde5f7ff, 0x49b32002, 0x22008008, 0x48b549b0, 
+    0xf0146800, 0x4604f8f9, 0xb9501d20, 0x1008f240, 0xe70086a8, 0x49aa2200, 0x680048ae, 0xf8ecf014, 
+    0x1d604604, 0xd1a92800, 0x1009f240, 0xe6f286a8, 0xe2462401, 0x880048a3, 0xd11e2802, 0xfcb3f7ff, 
+    0x499f2200, 0x680048a3, 0xf8d6f014, 0x1d204604, 0xf240b950, 0x86a8100e, 0x2200e6dd, 0x489d4998, 
+    0xf0146800, 0x4604f8c9, 0x28001d60, 0xf240d186, 0x86a8100f, 0x2401e6cf, 0x4892e223, 0x28108800, 
+    0xf7ffd11e, 0x2200fbf4, 0x4892498d, 0xf0146800, 0x4604f8b3, 0xb9501d20, 0x1014f240, 0xe6ba86a8, 
+    0x49872200, 0x6800488b, 0xf8a6f014, 0x1d604604, 0xd1982800, 0x1015f240, 0xe6ac86a8, 0xe2002401, 
+    0x88004880, 0xd11e2811, 0xfbc1f7ff, 0x497c2200, 0x68004880, 0xf890f014, 0x1d204604, 0xf240b950, 
+    0x86a8101a, 0x2200e697, 0x487a4975, 0xf0146800, 0x4604f883, 0x28001d60, 0xf240d19b, 0x86a8101b, 
+    0x2401e689, 0x486fe1dd, 0x28128800, 0xf7ffd11e, 0x2200fb7a, 0x486f496a, 0xf0146800, 0x4604f86d, 
+    0xb9501d20, 0x1020f240, 0xe67486a8, 0x49642200, 0x68004868, 0xf860f014, 0x1d604604, 0xd19b2800, 
+    0x1021f240, 0xe66686a8, 0xe1ba2401, 0x8800485d, 0xd1252803, 0x7800485c, 0xd1012803, 0xf9def7ff, 
+    0x49582004, 0x22008008, 0x485a4955, 0xf0146800, 0x4604f843, 0xb9501d20, 0x1036f240, 0xe64a86a8, 
+    0x494f2200, 0x68004853, 0xf836f014, 0x1d604604, 0xd1942800, 0x1037f240, 0xe63c86a8, 0xe1902401, 
+    0x88004848, 0xd121280e, 0xf8bbf7ff, 0x4945200f, 0x22008008, 0x48474942, 0xf0146800, 0x4604f81d, 
+    0xb9501d20, 0x103ef240, 0xe62486a8, 0x493c2200, 0x68004840, 0xf810f014, 0x1d604604, 0xd1912800, 
+    0x103ff240, 0xe61686a8, 0xe16a2401, 0x88004835, 0xd132280f, 0xf808f7ff, 0x78004835, 0xd10c2803, 
+    0xf7f42002, 0x2101fe28, 0xf7f40508, 0x2000fdbd, 0xfd1ff7f5, 0xfd75f00b, 0x2003e154, 0x80084929, 
+    0x49272200, 0x6800482b, 0xffe6f013, 0x1d204604, 0xf240b950, 0x86a81054, 0x2200e5ed, 0x48254920, 
+    0xf0136800, 0x4604ffd9, 0x28001d60, 0xf240d1a7, 0x86a81055, 0x2401e5df, 0x481ae133, 0x28048800, 
+    0xf7fed121, 0x2006fecd, 0x80084916, 0x49142200, 0x68004818, 0xffc0f013, 0x1d204604, 0xf240b950, 
+    0x86a8105e, 0x2200e5c7, 0x4812490d, 0xf0136800, 0x4604ffb3, 0x28001d60, 0xf240d1a7, 0x86a8105f, 
+    0x2401e5b9, 0x4807e10d, 0x28068800, 0xf7fed133, 0x2002fcc6, 0xfdedf7f4, 0x200ab170, 0x0000e00d, 
+    0x00038618, 0x00038610, 0x0003626a, 0x0003845c, 0x0003625c, 0x0003860c, 0x4983200f, 0x22008008, 
+    0x68004882, 0xff88f013, 0x1d204604, 0xf240b950, 0x86a81066, 0x2200e58f, 0x487c497b, 0xf0136800, 
+    0x4604ff7b, 0x28001d60, 0xf240d1a6, 0x86a81067, 0x2401e581, 0x4876e0d5, 0x28078800, 0xf7fed12d, 
+    0x4874fc2b, 0x28017800, 0x4873d107, 0x28017800, 0x2008d103, 0x8008496e, 0x2006e002, 0x8008496c, 
+    0x49692200, 0x68004869, 0xff56f013, 0x1d204604, 0xf240b950, 0x86a8107a, 0x2200e55d, 0x48634962, 
+    0xf0136800, 0x4604ff49, 0x28001d60, 0xf240d104, 0x86a8107b, 0x2401e54f, 0x485de0a3, 0x28088800, 
+    0xf7fed128, 0x485dfba0, 0x28017800, 0x200ad103, 0x80084957, 0x2009e002, 0x80084955, 0x49522200, 
+    0x68004852, 0xff28f013, 0x1d204604, 0xf240b950, 0x86a8108e, 0x2200e52f, 0x484c494b, 0xf0136800, 
+    0x4604ff1b, 0xbb701d60, 0x108ff240, 0xe52286a8, 0xe0762401, 0x88004846, 0xd1252809, 0xf9b8f7fe, 
+    0xf7f42002, 0xb108fd56, 0xe000200a, 0x493e200f, 0x22008008, 0x6800483d, 0xfefef013, 0x1d204604, 
+    0xf240b950, 0x86a81096, 0x2200e505, 0x48374936, 0xf0136800, 0x4604fef1, 0xb9201d60, 0x1097f240, 
+    0xe4f886a8, 0xe04c2401, 0x88004831, 0xd120280a, 0xf8a2f7fe, 0x492e200b, 0x22008008, 0x482b492a, 
+    0xf0136800, 0x4604fed9, 0xb9501d20, 0x109ef240, 0xe4e086a8, 0x49242200, 0x68004824, 0xfeccf013, 
+    0x1d604604, 0xf240bb68, 0x86a8109f, 0x2401e4d3, 0x481fe027, 0x280b8800, 0xf7fdd123, 0x200bffe3, 
+    0x80084919, 0x491a200c, 0xf04f8008, 0x491632ff, 0x6800481b, 0xfeb0f013, 0x1d204604, 0xf240b950, 
+    0x86a810a8, 0x2200e4b7, 0x4815490f, 0xf0136800, 0x4604fea3, 0xb9201d60, 0x10a9f240, 0xe4aa86a8, 
+    0xbf002401, 0xbf00e49b, 0xe4a4bf00, 0x2200b510, 0xf2af2101, 0xf01370a9, 0x2108fc22, 0xf0132003, 
+    0x4902fdbf, 0xbd106008, 0x00038618, 0x0003860c, 0x00038610, 0x00036224, 0x00036225, 0x000361ee, 
+    0x00038654, 0xf04fb50e, 0x48fd42e0, 0x1000f9b0, 0x0000f242, 0xfc6df7ec, 0xf2422107, 0xf7ec0000, 
+    0xf242fca1, 0xf7ec00a0, 0x2000fcc1, 0x700849f5, 0x780048f5, 0x49f5b240, 0xb2497809, 0x78124af4, 
+    0xe9cdb252, 0x90022100, 0x780048f2, 0x48f2b243, 0xb2427800, 0x780048f1, 0x48eab241, 0xb2407800, 
+    0xfcccf7f3, 0xf7f32000, 0xbf00fd1d, 0xf7f32002, 0x2800fd25, 0xf242d1fa, 0xf7ec00a0, 0x48e8fc97, 
+    0xb9487800, 0xf7f52000, 0x2301fb64, 0x4619220c, 0xf7f5200e, 0xe01afb0d, 0x780048e1, 0xd0032802, 
+    0x780048df, 0xd1122803, 0xf7f52000, 0x48ddfb52, 0xb9307800, 0x220d2301, 0x200e4619, 0xfaf8f7f5, 
+    0x2301e005, 0x4619220d, 0xf7f5200e, 0xf242faf1, 0xf7ec00a0, 0x48d2fc6b, 0xb9307800, 0x220e2300, 
+    0x0100f244, 0xf7f348d0, 0x2001f94a, 0x700849c7, 0xb50ebd0e, 0x780048ca, 0xd1152803, 0x11f4f240, 
+    0x0000f242, 0xfc2ef7ec, 0x3199f243, 0x0000f242, 0xfbd8f7ec, 0xf24249c5, 0xf7ec0000, 0x49c4fbd3, 
+    0x680048c4, 0xfbbbf7f4, 0x49b62001, 0x20007008, 0x700849ba, 0x780048ba, 0xf240b910, 0xe0002000, 
+    0x49bd2040, 0x48bd8008, 0x28047800, 0x48b4d104, 0xb1087800, 0x80082020, 0x780048b9, 0xd1022802, 
+    0x49b501c0, 0x48a88008, 0xb2407800, 0x780949a7, 0x4aa7b249, 0xb2527812, 0x2100e9cd, 0x48a59002, 
+    0xb2437800, 0x780048a4, 0x48a4b242, 0xb2417800, 0x7800489c, 0xf7f3b240, 0x48a7fc31, 0xb2008800, 
+    0xfc5ff7f3, 0xf7f32001, 0xbf00fc7d, 0xf7f32002, 0x2800fc85, 0x2002d1fa, 0xfd1ff7f5, 0x0090f242, 
+    0xfbf4f7ec, 0xf86cf7f4, 0x8008499e, 0xfacbf7f4, 0x78004893, 0xd10c2803, 0xf7f3201e, 0x2003fbde, 
+    0xf916f00a, 0x220e2300, 0x0100f244, 0xf7f3488e, 0x2005f8c6, 0xfbd1f7f3, 0x0090f242, 0xfbd6f7ec, 
+    0xf0062001, 0x4890fbf6, 0x49907a40, 0x488e8008, 0xf0007a00, 0x88090003, 0x2000ea41, 0x8008498b, 
+    0x2001e007, 0xfbe5f006, 0x88004888, 0x49871e40, 0x48868008, 0x28018800, 0x4885dcf3, 0x28017800, 
+    0x2006d103, 0xf8e4f00a, 0x2005e002, 0xf8e7f00a, 0x68004880, 0x4872b968, 0xb9507800, 0x7800487e, 
+    0x2201b138, 0x20071e91, 0xfbaef7f4, 0x497a2000, 0xf2427008, 0xf7ec0090, 0x2301fb99, 0x21102204, 
+    0xf7f34876, 0x2301f87c, 0x4975220f, 0x302a4873, 0xf875f7f3, 0xf9b0486b, 0x20001000, 0xfea4f7f3, 
+    0x42e0f04f, 0xf9b04856, 0xf2421000, 0xf7ec0000, 0xf242fb20, 0xf7ec0090, 0xbd0efb79, 0x4858b53e, 
+    0x28037800, 0xf240d115, 0xf24211f4, 0xf7ec0000, 0xf241fb49, 0xf2421199, 0xf7ec0000, 0x4953faf3, 
+    0x0000f242, 0xfaeef7ec, 0x48524951, 0xf7f46800, 0x2001fad6, 0xfb7df006, 0xfe8af018, 0xd17d2801, 
+    0x79c04851, 0x0001f000, 0x70084956, 0x78004608, 0xd1742801, 0x78004842, 0x2040b908, 0x2020e000, 
+    0x48464604, 0x28047800, 0x483dd103, 0xb1007800, 0x48432410, 0x28027800, 0x2440d100, 0x7a404842, 
+    0x80084942, 0x7a004840, 0x0003f000, 0xea418809, 0x493e2000, 0x46088008, 0x42a08800, 0x2002dd4f, 
+    0xfb0ef7f4, 0x68094940, 0x49401a08, 0x1000f9b1, 0xf0f1fbb0, 0x6008493e, 0x68004608, 0x60081cc0, 
+    0x68004608, 0x4a391e80, 0x2000f9b2, 0xf102fb00, 0x68004835, 0xfa83f7f4, 0x491a2001, 0x20007008, 
+    0x7008491e, 0x88004829, 0x88094931, 0x49221a40, 0x482f8008, 0xb2018800, 0x30a44828, 0xf9e4f7ec, 
+    0x78004811, 0x4911b240, 0xb2497809, 0x78124a10, 0xe9cdb252, 0x90022100, 0x7800480e, 0x480eb243, 
+    0xb2427800, 0x7800480d, 0x4806b241, 0xb2407800, 0xfb04f7f3, 0x88004810, 0xe03bb200, 0xe11ae0cf, 
+    0x00038624, 0x00036217, 0x000361ef, 0x000361f5, 0x000361f7, 0x00036213, 0x00036210, 0x00036215, 
+    0x00038b1c, 0x000361ee, 0xd0030416, 0xdcba01f5, 0x0066ff30, 0x00036310, 0x0003621a, 0x0003626a, 
+    0x0003630c, 0x00038632, 0x00038fd0, 0x0003621c, 0x000384e0, 0x000362f4, 0x00038626, 0xd00350f6, 
+    0xffff8000, 0x00036218, 0x00036230, 0x000384a8, 0x0003623c, 0xfaf5f7f3, 0xf7f32001, 0xbf00fb13, 
+    0xf7f32002, 0x2800fb1b, 0x2002d1fa, 0xfbb5f7f5, 0x0090f242, 0xfa8af7ec, 0xff02f7f3, 0x800849fe, 
+    0xf961f7f4, 0x780048fd, 0xd10c2803, 0xf7f3201e, 0x2003fa74, 0xffacf009, 0x220e2300, 0x0100f244, 
+    0xf7f248f7, 0x2005ff5c, 0xfa67f7f3, 0x0090f242, 0xfa6cf7ec, 0xf0062001, 0x48f2fa8c, 0x49f27a40, 
+    0x48f08008, 0xf0007a00, 0x88090003, 0x2000ea41, 0x800849ed, 0x2001e007, 0xfa7bf006, 0x880048ea, 
+    0x49e91e40, 0x48e88008, 0x28018800, 0x48e7dcf3, 0x28017800, 0x2006d103, 0xff7af009, 0x2005e002, 
+    0xff7df009, 0x680048e2, 0x48dcb988, 0xb9707800, 0x780048e0, 0x2201b158, 0x20071e91, 0xfa44f7f4, 
+    0x49dc2000, 0x49dc7008, 0x49dc6008, 0xf2426008, 0xf7ec0090, 0x2301fa2b, 0x21102204, 0xf7f248d8, 
+    0x2301ff0e, 0x49d7220f, 0x302a48d5, 0xff07f7f2, 0xf9b048c9, 0x20011000, 0xfd36f7f3, 0x42e0f04f, 
+    0xf9b048d1, 0xf2421000, 0xf7ec0000, 0xf242f9b2, 0xf7ec0090, 0x2006fa0b, 0x800849cb, 0x48cbe04b, 
+    0x1c406800, 0x600849c9, 0xf24221e2, 0xf7ec0000, 0x48c6f9d9, 0xf2426801, 0xf7ec0000, 0x48c4f983, 
+    0xf4008800, 0xb1a05000, 0x680048b9, 0x48c1b988, 0xf2406800, 0x428871fc, 0x49bfda0b, 0x68124abd, 
+    0x0082eb01, 0xf8f4f7ec, 0x680048ba, 0x49b91d00, 0x48ba6008, 0x28017800, 0xf242d102, 0xe0007010, 
+    0xf2002000, 0x48b63132, 0xf8bef7ec, 0x780048b5, 0x0007f000, 0x1000eb00, 0xeb0149b3, 0x68400080, 
+    0x49b01c40, 0xf0017809, 0xeb010107, 0x4aae1101, 0x0181eb02, 0xbd3e6048, 0x2001b510, 0xf9d9f006, 
+    0xfce6f018, 0xd12b2801, 0x79c04896, 0x1040f3c0, 0x700849a6, 0x780048a6, 0xd16d2801, 0x78004608, 
+    0xd1692801, 0x42e0f04f, 0xf9b04897, 0xf2421000, 0xf7ec0000, 0x2106f93e, 0x0000f242, 0xf972f7ec, 
+    0x7800489c, 0xff6ff7f3, 0x78004894, 0xd1032801, 0x498d2005, 0xe04f8008, 0x498b2004, 0xe04b8008, 
+    0x6800488a, 0x49891c40, 0x21e26008, 0x0000f242, 0xf958f7ec, 0x68014885, 0x0000f242, 0xf902f7ec, 
+    0x88004883, 0x5000f400, 0x4879b1a0, 0xb9886800, 0x68004880, 0x71fcf240, 0xda0b4288, 0x4a7d497e, 
+    0xeb016812, 0xf7ec0082, 0x487af873, 0x1d006800, 0x60084978, 0x78004879, 0xd1022801, 0x7010f242, 
+    0x2000e000, 0x3131f200, 0xf7ec4875, 0x4875f83d, 0xf0007800, 0xeb000007, 0x49731000, 0x0080eb01, 
+    0x1c406840, 0x7809496f, 0x0107f001, 0x1101eb01, 0xeb024a6d, 0x60480181, 0xb50ebd10, 0x42e0f04f, 
+    0xf9b04861, 0xf2421000, 0xf7ec0000, 0x2001f8d2, 0x70084967, 0x78004868, 0x7809b240, 0x4a67b249, 
+    0xb2527812, 0x2100e9cd, 0x48659002, 0xb2437800, 0x78004864, 0x4864b242, 0xb2417800, 0x78004863, 
+    0xf7f3b240, 0x2000f93b, 0xf98cf7f3, 0x2002bf00, 0xf994f7f3, 0xd1fa2800, 0xb510bd0e, 0x7800485c, 
+    0x483eb1d0, 0xb9b87800, 0x42e0f04f, 0xf9b04846, 0xf2421000, 0xf7ec0000, 0x2000f89c, 0xffc9f7f4, 
+    0xf8baf7f7, 0xfcfff7f6, 0xf7f42001, 0x2100ffc2, 0x1000f44f, 0xf858f7f4, 0x0090f242, 0xf8e6f7ec, 
+    0xe92dbd10, 0xb08641f0, 0x42e0f04f, 0xf9b04836, 0xf2421000, 0xf7ec0000, 0x4828f87c, 0xb1d87800, 
+    0x49382000, 0xf0017809, 0xeb010107, 0x4a361101, 0x0181eb02, 0x48316048, 0xb9087800, 0xfc94f7f9, 
+    0x7800481e, 0xd0142802, 0x7800482c, 0x2101b988, 0xf7f40408, 0xe00cf829, 0x78004828, 0xf7f9b948, 
+    0x2101fc83, 0xf7f404c8, 0xf242f81f, 0xf7ec0080, 0x4812f8ad, 0xb9c87800, 0xf990482e, 0x492d0000, 
+    0x1000f991, 0xf9924a2b, 0x23012000, 0x3202e9cd, 0x1004e9cd, 0x9000200c, 0x4611220e, 0x03989001, 
+    0xfe5ff7f4, 0x0090f242, 0xf890f7ec, 0x78004813, 0xd17d2800, 0xe03f4801, 0x00038630, 0x00038b1c, 
+    0xd0030416, 0x00038fd0, 0x0003621c, 0x000384e0, 0x000362f4, 0x00038626, 0x00038b8c, 0x00038b90, 
+    0xd00350f6, 0xffff8000, 0x00038624, 0x00036350, 0x0005280c, 0x00052800, 0x00050800, 0x000361ee, 
+    0xd03c80b8, 0x00038b38, 0x00048c18, 0x000361f6, 0x000361f5, 0x00036226, 0x000361ef, 0x000361f7, 
+    0x00036213, 0x00036210, 0x00036215, 0x00036217, 0x00038466, 0x00038627, 0x28007800, 0x2500d17c, 
+    0xf7f548f7, 0x48f6fcbd, 0x8000f8d0, 0xe0082401, 0xf85048f3, 0x45477024, 0x46b8d201, 0x1c604625, 
+    0x2c04b244, 0xf7f9dbf4, 0x2100fc4d, 0xf7f54608, 0xf7f9ff72, 0x4606faf7, 0x700548ea, 0x21082203, 
+    0xf7f248e9, 0x2801fd23, 0x2203d113, 0x48e62108, 0xf7f21c80, 0x2801fd1b, 0x48e4d10b, 0xf3c07800, 
+    0xb1300080, 0x780048e2, 0x49deb240, 0xe0027008, 0x48dce042, 0x14307005, 0xf7f9b231, 0x48d9fef2, 
+    0x0000f990, 0xfa88f7f9, 0x49da2001, 0x20027008, 0xfd34f7f9, 0xf99048d3, 0xf7f90000, 0x48d1faf3, 
+    0x0000f990, 0xfed0f7f9, 0x21082203, 0xf7f248ce, 0x2801fced, 0x2203d10e, 0x48cb2108, 0xf7f21c80, 
+    0x2801fce5, 0x48c9d106, 0xf3c07800, 0xb1080080, 0xfe8ef7f9, 0xfba8f7f9, 0x03482101, 0xff44f7f3, 
+    0x20012100, 0xff67f7f5, 0x200c2100, 0xfec1f7f5, 0x46082101, 0xff0ff7f5, 0x780048bf, 0xd0052803, 
+    0x220c2301, 0x200e4619, 0xfe42f7f4, 0x780048ba, 0x2100b920, 0x0000f44f, 0xff26f7f3, 0x0090f242, 
+    0xffb4f7eb, 0xe8bdb006, 0xb50e81f0, 0xf2422105, 0xf7eb0000, 0x2101ff87, 0xf7f52000, 0x2004f898, 
+    0xfcd6f009, 0x780048ad, 0x48abb920, 0xb9087800, 0xe0002001, 0x49aa2000, 0x20037008, 0x700849a9, 
+    0x78004608, 0x49a8b240, 0xb2497809, 0x78124aa7, 0xe9cdb252, 0x90022100, 0x780048a5, 0x48a5b243, 
+    0xb2427800, 0x780048a4, 0x48a4b241, 0xb2407800, 0xffa4f7f2, 0xf7f22000, 0xbf00fff5, 0xf7f22002, 
+    0x2800fffd, 0xbd0ed1fa, 0x4605b570, 0x8ea8460e, 0xd07d28d6, 0x28b5dc13, 0xdc07d07b, 0x2888b320, 
+    0x2889d030, 0x28b4d03a, 0xe08fd174, 0xd07228c6, 0xd07128c7, 0xd07028ce, 0xd1f528cf, 0x28e7e0e9, 
+    0xdc08d06c, 0xd06a28d7, 0xd06928de, 0xd06828df, 0xd1e928e6, 0x28eee173, 0x28efd074, 0x28f8d073, 
+    0x28f9d072, 0xe1c0d1e0, 0xf04fe1c1, 0x498432ff, 0x68004884, 0xf912f013, 0x1d204604, 0x2088b948, 
+    0xbd7086a8, 0x497e2200, 0x6800487e, 0xf906f013, 0x1d604604, 0x2089b918, 0xe7f286a8, 0x2c012401, 
+    0xe1a4d000, 0x88004876, 0xd10c280f, 0xf9b04874, 0xf04f1000, 0xf2424227, 0xf7eb0000, 0x2000feba, 
+    0x80084971, 0x486ee192, 0x28158800, 0x486fd157, 0x28037800, 0x486dd007, 0x28057800, 0x486bd003, 
+    0x28047800, 0x486ad141, 0xbb707800, 0xf9b04864, 0xf04f1000, 0xf2424220, 0xf7eb0000, 0xf7fffe9a, 
+    0x2001ff44, 0x80084960, 0x78004862, 0xe0092802, 0xe028e0c3, 0xe04be16c, 0xe06de057, 0xe0c9e11b, 
+    0xe0f0e0e4, 0x8008d100, 0x4955200a, 0x22008008, 0x68004854, 0xf880f013, 0x1d204604, 0x20b4b968, 
+    0xe79e86a8, 0xe129e11e, 0xe00ee143, 0x494c2200, 0x6800484c, 0xf870f013, 0x1d604604, 0xd1b12800, 
+    0x86a820b5, 0x2401e78d, 0x2000e140, 0x80084946, 0x42e0f04f, 0x02882108, 0xfe5bf7eb, 0x4840e136, 
+    0x280a8800, 0x4840d19e, 0x28018800, 0xf7ffd11f, 0x2009fdc8, 0x8008493c, 0x49392200, 0x68004839, 
+    0xf84af013, 0x1d204604, 0x20c6b948, 0xe76886a8, 0x49332200, 0x68004833, 0xf83ef013, 0x1d604604, 
+    0xd1d12800, 0x86a820c7, 0x2401e75b, 0x482ee10e, 0x28098800, 0xf7ffd11f, 0x2002fd80, 0x8008492a, 
+    0x49272200, 0x68004827, 0xf826f013, 0x1d204604, 0x20ceb948, 0xe74486a8, 0x49212200, 0x68004821, 
+    0xf81af013, 0x1d604604, 0xd1ad2800, 0x86a820cf, 0x2401e737, 0x481ce0ea, 0x28028800, 0xf7ffd14c, 
+    0x2003fd2c, 0x80084918, 0x49152200, 0x68004815, 0xf802f013, 0x1d204604, 0x20d6bb70, 0xe72086a8, 
+    0x00038fe0, 0x000362b1, 0xd28e0078, 0x00036326, 0x00038578, 0x000362af, 0x00038b1c, 0x000361ee, 
+    0x00038627, 0x000361ef, 0x000361f5, 0x000361f7, 0x00036213, 0x00036210, 0x00036215, 0x00036217, 
+    0x00038628, 0x00038620, 0x00038624, 0x0003626a, 0x0003845c, 0x0003630c, 0x2200e006, 0x485e495d, 
+    0xf0126800, 0x4604ffc9, 0x28001d60, 0x20d7d18e, 0xe6e686a8, 0xe0992401, 0x88004858, 0xd1242803, 
+    0xfc5af7ff, 0xf7f32002, 0xb108fe04, 0xe000200a, 0x4950200f, 0x22008008, 0x6800484f, 0xffacf012, 
+    0x1d204604, 0x20deb948, 0xe6ca86a8, 0x49492200, 0x68004849, 0xffa0f012, 0x1d604604, 0xd1752800, 
+    0x86a820df, 0x2401e6bd, 0x4844e070, 0x28048800, 0xf7ffd123, 0x2002fa73, 0xfddbf7f3, 0x200ab108, 
+    0x200fe000, 0x8008493b, 0x483b2200, 0xf0126800, 0x4604ff83, 0xb9481d20, 0x86a820e6, 0x2200e6a1, 
+    0x48354934, 0xf0126800, 0x4604ff77, 0xbb301d60, 0x86a820e7, 0x2401e695, 0x4830e048, 0x28058800, 
+    0xf7ffd11e, 0x2006f966, 0x8008492c, 0x49292200, 0x68004829, 0xff60f012, 0x1d204604, 0x20eeb948, 
+    0xe67e86a8, 0x49232200, 0x68004823, 0xff54f012, 0x1d604604, 0x20efb918, 0xe67286a8, 0xe0252401, 
+    0x8800481e, 0xd1212806, 0xf8ccf7ff, 0x4919200b, 0x20078008, 0x80084919, 0x32fff04f, 0x48184915, 
+    0xf0126800, 0x4604ff39, 0xb9481d20, 0x86a820f8, 0x2200e657, 0x4812490f, 0xf0126800, 0x4604ff2d, 
+    0xb9181d60, 0x86a820f9, 0x2401e64b, 0xe63cbf00, 0xbf00bf00, 0xb510e645, 0x21012200, 0x30f7f2af, 
+    0xfcadf012, 0x20022108, 0xfe4af012, 0x60084902, 0x0000bd10, 0x00038628, 0x00038620, 0x00038624, 
+    0x00038654, 0x210ab570, 0x0000f244, 0xfd3af7eb, 0x780048fd, 0x48fdb130, 0x28027800, 0x48fad115, 
+    0xb1907800, 0x48fa2104, 0xfc3ef7eb, 0x220c2307, 0x0100f24f, 0xf7f248f7, 0x2307fa0b, 0xf6402208, 
+    0x48f47100, 0xfa04f7f2, 0x2300e022, 0x2101461a, 0x1f0048ef, 0xfa23f7f2, 0x220d2301, 0x48ec0359, 
+    0xf7f23834, 0x2301fa1c, 0x0359220d, 0x383248e8, 0xfa15f7f2, 0x220d2301, 0x48e50359, 0xf7f23830, 
+    0x2301fa0e, 0x0359220d, 0x382e48e1, 0xfa07f7f2, 0x48dd2400, 0xb3887800, 0x780048df, 0x2100b958, 
+    0xf7f52001, 0x2100fca8, 0xf7f5200c, 0x2101fc02, 0xf7f54608, 0x48d5fc50, 0x28017800, 0x1c60d101, 
+    0xf240b244, 0xf04f11f4, 0xf7eb7080, 0xf249fcdb, 0xf04f2122, 0xf7eb7080, 0x48ccfc85, 0x1000f990, 
+    0x7080f04f, 0xfc7ef7eb, 0xf04f4621, 0xf7eb7080, 0x49cafc79, 0x7080f04f, 0xfc74f7eb, 0x48c8250d, 
+    0x28057800, 0x1ca8d101, 0x48c6b245, 0x28017800, 0x1c60d101, 0x192ab244, 0x000ef104, 0x46192301, 
+    0xfb56f7f4, 0x00b0f242, 0xfcd0f7eb, 0xf244210b, 0xf7eb0000, 0xf64dfca7, 0xf7f55003, 0xb118f982, 
+    0x49b92000, 0xe0027008, 0x49b72001, 0xbd707008, 0x41f0e92d, 0x460f4605, 0xf5b08ea8, 0xd07d7f97, 
+    0x28b4dc12, 0xdc05d07b, 0x2868b320, 0x2869d031, 0xe03ad176, 0xd07428b5, 0x7f81f5b0, 0xf2a0d072, 
+    0x28001003, 0xe180d1f4, 0x7f9ef5b0, 0xdc08d06b, 0x102ff2a0, 0xd0672800, 0xd0662805, 0xd1e72806, 
+    0xf2a0e23b, 0x2800103d, 0x280dd07d, 0x280ed07c, 0xe282d1de, 0xf04fe283, 0x499c32ff, 0x6800489c, 
+    0xfe5cf012, 0x1d204604, 0x2068b950, 0xe8bd86a8, 0x220081f0, 0x48964995, 0xf0126800, 0x4604fe4f, 
+    0xb9181d60, 0x86a82069, 0x2401e7f1, 0xd0002c01, 0x488ee265, 0x280f8800, 0x488cd10c, 0x1000f9b0, 
+    0x4228f04f, 0x0000f244, 0xfc03f7eb, 0x49892000, 0xe2538008, 0x88004885, 0xd17b2816, 0x78004880, 
+    0xd0072803, 0x7800487e, 0xd0032805, 0x7800487c, 0xd1652804, 0xf9b0487d, 0xf04f1000, 0xf2444220, 
+    0xf7eb0000, 0x2109fbe6, 0x0000f244, 0xfc1af7eb, 0x00b0f242, 0xfc3af7eb, 0xe0074872, 0xe03fe1ac, 
+    0xe04be22e, 0xe1efe103, 0xe1c9e1b3, 0x28017800, 0x2006d103, 0xf95cf009, 0x2005e002, 0xf958f009, 
+    0x7800486d, 0xd11a2801, 0x220a2301, 0x486b0281, 0xf905f7f2, 0xf7f42000, 0x4869faec, 0x28116800, 
+    0x2100d807, 0xe1dce001, 0xf244e1fa, 0xf7f30000, 0xf7f8fb7b, 0x2001fe5c, 0x8008495e, 0x2000e002, 
+    0x8008495c, 0x4959200a, 0x22008008, 0x68004858, 0xfda2f012, 0x1d204604, 0x20b4b948, 0xe77686a8, 
+    0x49522200, 0x68004852, 0xfd96f012, 0x1d604604, 0xd18e2800, 0x86a820b5, 0xe00be769, 0xe1dd2401, 
+    0x494c2000, 0xf04f8008, 0x21034200, 0xf7eb0c50, 0xe1d3fb80, 0x88004847, 0xd1742801, 0x00b0f242, 
+    0xfbd4f7eb, 0x49472000, 0x21017008, 0xf7f30348, 0x2205fb3b, 0x48412120, 0xf7f2300a, 0x4941f8c7, 
+    0x46087008, 0x28017800, 0x2205d030, 0x483b2120, 0xf7f2300a, 0x493bf8bb, 0x48327008, 0x28017800, 
+    0x2600d124, 0x2310e01f, 0x21ff2200, 0xf7f24836, 0x2301f896, 0x01512208, 0x1e804833, 0xf88ff7f2, 
+    0xf2422100, 0xf7f30000, 0x2205fb0f, 0x482b2120, 0xf7f2300a, 0x492bf89b, 0x46087008, 0x28017800, 
+    0xe002d100, 0x2e101c76, 0xbf00dbdd, 0x78004825, 0xd16c2801, 0x481f07c2, 0x1000f9b0, 0xf7eb0c10, 
+    0x4822fb28, 0xfa60f7eb, 0x20024680, 0xfb68f7f3, 0x0000eba8, 0x7809491e, 0x0107f001, 0x1101eb01, 
+    0xeb024a1c, 0x62880181, 0x49122002, 0x481a8008, 0x1c406800, 0x60084918, 0x490c200a, 0x22008008, 
+    0x6800480b, 0xe12ee02a, 0x00038b1c, 0x00038b22, 0xd0031034, 0xd180004c, 0x000361ee, 0xdcba01f5, 
+    0x0003626a, 0x000384e0, 0x00036345, 0x0003863c, 0x00038634, 0x00038638, 0x000361f5, 0xd0035022, 
+    0x000361dc, 0x00036223, 0xd0030482, 0xc8000128, 0x00038b38, 0x00048c18, 0x00052f94, 0xfcdcf012, 
+    0x1d204604, 0xf240b950, 0x86a81002, 0x2200e6af, 0x489d499c, 0xf0126800, 0x4604fccf, 0x28001d60, 
+    0xf240d104, 0x86a81003, 0x2401e6a1, 0x2198e0ea, 0x0000f244, 0xfaf6f7eb, 0x68004894, 0x2000b170, 
+    0xf9e7f7f4, 0x00b0f242, 0xfb10f7eb, 0x49902000, 0xf2408008, 0x1e483190, 0xfa9ef7f3, 0xf7f4488d, 
+    0x488cff7f, 0x498b6800, 0x44086849, 0x68894989, 0x49884408, 0x440868c9, 0x51e8f64f, 0x0f90ebb1, 
+    0x4884d931, 0x49836800, 0x42886849, 0x4881d902, 0xe0016800, 0x6840487f, 0x6889497e, 0x68d24a7d, 
+    0xd9024291, 0x6889497b, 0x497ae001, 0x428868c9, 0x4878d90b, 0x49776800, 0x42886849, 0x4875d902, 
+    0xe00d6800, 0x68404873, 0x4872e00a, 0x49716880, 0x428868c9, 0x486fd902, 0xe0016880, 0x68c0486d, 
+    0x4288496d, 0x486dd96b, 0xb3a07800, 0xf9b0486c, 0x28140000, 0x486ada3f, 0x1c408800, 0x4968b200, 
+    0x48688008, 0x1c407800, 0x0007f000, 0x1000eb00, 0xeb014965, 0x68800080, 0x6080f500, 0x78094961, 
+    0xf0011c49, 0xeb010107, 0x4a5f1101, 0x0181eb02, 0x20006088, 0x80084956, 0x4952203f, 0x22008008, 
+    0x6800485a, 0xfc38f012, 0x1d204604, 0xf240b958, 0x86a8102e, 0xe00ee60b, 0x494a2200, 0x68004853, 
+    0xfc2af012, 0x1d604604, 0xf240bb40, 0x86a8102f, 0x2401e5fd, 0x2002e046, 0xfa6bf7f3, 0x200ab108, 
+    0x200fe000, 0x8008493f, 0x483f2200, 0xf0126800, 0x4604fc13, 0xb9501d20, 0x1034f240, 0xe5e686a8, 
+    0x49382200, 0x68004838, 0xfc06f012, 0x1d604604, 0xf240b920, 0x86a81035, 0x2401e5d9, 0x2002e022, 
+    0xfa47f7f3, 0x200ab108, 0x200fe000, 0x8008492d, 0x482d2200, 0xf0126800, 0x4604fbef, 0xb9501d20, 
+    0x103cf240, 0xe5c286a8, 0x49262200, 0x68004826, 0xfbe2f012, 0x1d604604, 0xf240b920, 0x86a8103d, 
+    0x2401e5b5, 0x4822e02a, 0x28028800, 0x0782d126, 0xf9b0481f, 0x0c101000, 0xf9cbf7eb, 0xfcc2f7ff, 
+    0x4918200b, 0xf04f8008, 0x482132ff, 0xf0126800, 0x4604fbc3, 0xb9501d20, 0x104af240, 0xe59686a8, 
+    0x49102200, 0x6800481a, 0xfbb6f012, 0x1d604604, 0xf240b920, 0x86a8104b, 0x2401e589, 0xe57abf00, 
+    0xbf00bf00, 0xb510e583, 0x21012200, 0x507ff2af, 0xf935f012, 0x20032108, 0xfad2f012, 0x60084902, 
+    0x0000bd10, 0x0003863c, 0x00038634, 0x00052f80, 0x00038638, 0x00038fe0, 0x00013880, 0x00038b1c, 
+    0x00038b20, 0x00038b38, 0x00048c18, 0x00038b18, 0x00038654, 0x47fce92d, 0x0900f04f, 0xf248210c, 
+    0xf7eb0000, 0x2201f9af, 0x48fc2102, 0xfecef7f1, 0x2000b110, 0xfd50f7f4, 0x780849f9, 0xfd70f7f4, 
+    0x780849f7, 0xff86f004, 0xf8b5f005, 0xf7eb48f5, 0x49f5f89b, 0x20006008, 0x800849f4, 0x780048f4, 
+    0xd13a2801, 0x780048f3, 0xda36284b, 0x80082001, 0x48f12114, 0xf898f7eb, 0x48ef2110, 0xf894f7eb, 
+    0x48ed2101, 0xf7eb1f00, 0x210af88f, 0x1d0048ea, 0xf88af7eb, 0x48e82110, 0xf886f7eb, 0x48e62112, 
+    0xf882f7eb, 0x48e42101, 0xf7eb30be, 0x2100f87d, 0x30c048e1, 0xf878f7eb, 0x4192f242, 0x30c248de, 
+    0xf872f7eb, 0x48dc2112, 0xf7eb30c4, 0x207ff86d, 0xfef8f014, 0xf7f3200a, 0x48d8f9da, 0x28007800, 
+    0x49d7d14e, 0xf0017809, 0xeb010107, 0x4ad51101, 0x0181eb02, 0x240062c8, 0x48d3e03f, 0x2044eb00, 
+    0xeb0149d2, 0x23012144, 0xe9cd2200, 0x46211000, 0xf7f14618, 0x2100fad6, 0xe0162076, 0xeb024acb, 
+    0xf8322244, 0xfb122010, 0x4bc7f202, 0x2344eb03, 0x3010f833, 0xc310f8df, 0x2c44eb0c, 0xc010f83c, 
+    0x220cfb13, 0x1c424411, 0x287fb290, 0x4ac0dde6, 0x1024f842, 0xf8424abf, 0x48bf1024, 0x2044eb00, 
+    0xeb0149be, 0x23012144, 0xe9cd2200, 0x46211000, 0xf7f14610, 0x1c60faa6, 0x2c04b244, 0xbf00dbbd, 
+    0x780048ae, 0xf640bb10, 0x48b50504, 0xb9a08800, 0x780048a3, 0xd00b2803, 0x780048a1, 0xd0072805, 
+    0x7800489f, 0xd1052804, 0x780048a2, 0xdd012828, 0xe0002080, 0x46062000, 0x2680e000, 0x0700f241, 
+    0x499f2000, 0x49a76008, 0xe0106008, 0xf7ea48a6, 0xf640ffe5, 0xea000104, 0x48a30501, 0xffdef7ea, 
+    0x0680f000, 0xf7ea48a0, 0xf400ffd9, 0x20025780, 0xfc3ef004, 0x46112201, 0xf0034610, 0x489bffc3, 
+    0xb1707800, 0x707ff64f, 0xb2064030, 0x78004898, 0x1040f3c0, 0xf24fb918, 0x402870ff, 0xf8dfb205, 
+    0x48929254, 0xb1707800, 0x78004893, 0xdb0a2802, 0x49922002, 0x22007008, 0x20044991, 0xf8d4f7f3, 
+    0xf7f3200b, 0x498ff924, 0xb9217809, 0x78094987, 0x2101b109, 0x2100e000, 0xf7f84608, 0x4889fff2, 
+    0xb9207800, 0x78004888, 0x2008b108, 0x2000e000, 0xf4454680, 0x43307040, 0x0008ea40, 0x0009ea40, 
+    0x6080f440, 0x0107ea40, 0xf7ea4877, 0x4864ff8d, 0x28037800, 0x2100d104, 0xf7ea487c, 0xe003ff85, 
+    0x487a2101, 0xff80f7ea, 0x78004864, 0x2001b948, 0x70084977, 0x70084977, 0x70084977, 0x49772000, 
+    0x20017008, 0xfd66f7f8, 0xf9904875, 0xf7f80000, 0x486cfb79, 0x28017800, 0xf242d102, 0xe0007210, 
+    0x48702200, 0x1e406800, 0x33e8f240, 0x2000fb03, 0x2003f200, 0x485cb201, 0xf7ea1c80, 0xe8bdff55, 
+    0xb5f887fc, 0x460f4605, 0x28fb8ea8, 0xdc0dd07e, 0xd07c28b2, 0xb1f0dc05, 0xd02a2886, 0xd1772887, 
+    0x28b3e033, 0x28fad075, 0xe184d1f9, 0x125df240, 0x42901a81, 0xdc09d06e, 0x7f83f5b0, 0xf2a0d06b, 
+    0x28001007, 0x2855d068, 0xe21dd1e9, 0xd0642919, 0xd1e4291a, 0xe256e255, 0x32fff04f, 0x48534952, 
+    0xf0126800, 0x4604fa0b, 0xb9481d20, 0x86a82086, 0x2200bdf8, 0x484d494c, 0xf0126800, 0x4604f9ff, 
+    0xb9181d60, 0x86a82087, 0x2401e7f2, 0xd0002c01, 0x4845e239, 0x280f8800, 0x4843d120, 0x1000f9b0, 
+    0x4229f04f, 0x0000f248, 0xffb3f7ea, 0x49402000, 0x48408008, 0x493b6800, 0x42886809, 0x483dda04, 
+    0x1c406800, 0x6008493b, 0x8800483a, 0x483ab201, 0xfeeaf7ea, 0x49392000, 0xe2137008, 0x88004832, 
+    0xd16d2817, 0x7800480e, 0xd0072803, 0x7800480c, 0xd0032805, 0x7800480a, 0xd1752804, 0xf9b0482a, 
+    0xf04f1000, 0xf2484220, 0xe05a0000, 0xe06ce120, 0xe077e1fa, 0xe14ce1c5, 0xe1e4e15a, 0xd03d104a, 
+    0x0003626a, 0xc800017c, 0x000362fc, 0x00038dc2, 0x00038db0, 0x00036226, 0xd0031404, 0x00038b1c, 
+    0x00038b38, 0x00048c18, 0x0004ae48, 0x0004a648, 0x00043028, 0x00043038, 0x0004be48, 0x0004b648, 
+    0x000361cc, 0x00038b3c, 0xd03c80b6, 0x00036328, 0x00036326, 0xffff8000, 0x00036324, 0x0003845b, 
+    0x0ee6b280, 0x000361ee, 0x00038b22, 0xd003086e, 0x000362af, 0x000362b0, 0x000362cc, 0x000362cd, 
+    0x000362b1, 0x00052f88, 0x0003864c, 0x00038644, 0x00038648, 0x00052f90, 0xd0035140, 0x00038a5a, 
+    0xf7eae02d, 0x2001ff26, 0x800849d8, 0x49d8200a, 0x22008008, 0x680048d7, 0xf91ef012, 0x1d204604, 
+    0x20b2b950, 0xe74386a8, 0x2200e00e, 0x48d149d0, 0xf0126800, 0x4604f911, 0x28001d60, 0x20b3d103, 
+    0xe73586a8, 0xe17d2401, 0x49c82000, 0xf04f8008, 0x21034210, 0x0000f248, 0xfefbf7ea, 0xf04fe172, 
+    0x48c24210, 0x1000f9b0, 0x0000f248, 0xfef1f7ea, 0x880048be, 0xd17d2801, 0x461a2301, 0x48be2102, 
+    0xfc2df7f1, 0x22012300, 0x48bb2102, 0xfc27f7f1, 0x780048ba, 0x2300b168, 0xf241220c, 0x48b80100, 
+    0xfc1df7f1, 0x22042300, 0x48b62110, 0xfc17f7f1, 0x2000e00d, 0x0300f641, 0x46014602, 0xf7f69000, 
+    0x2300f8b5, 0x21102204, 0xf7f148ae, 0x2002fc08, 0xffb3f7f2, 0xd17d2800, 0x780048a8, 0xd1042805, 
+    0xf9b048a9, 0x28140000, 0x48a4db11, 0x28027800, 0x48a5d104, 0x0000f9b0, 0xdb082804, 0x7800489f, 
+    0xd1472803, 0xf9b048a0, 0x28040000, 0x2101da42, 0xf7f20348, 0x489cfe69, 0x1c408800, 0x499ab200, 
+    0x489a8008, 0x1c407800, 0x0007f000, 0x1000eb00, 0xeb014997, 0x68800080, 0x6080f500, 0x78094993, 
+    0xf0011c49, 0xeb010107, 0x4a911101, 0x0181eb02, 0x20006088, 0x80084985, 0x4985203f, 0x22008008, 
+    0x6800488c, 0xf878f012, 0x1d204604, 0x20fab950, 0xe69d86a8, 0x2200e0b7, 0x4886497d, 0xf0126800, 
+    0x4604f86b, 0x28001d60, 0x20fbd103, 0xe68f86a8, 0xe0d72401, 0x68004880, 0x487cbbc8, 0x1c407800, 
+    0x0007f000, 0x1000eb00, 0xeb014979, 0x68800080, 0x7000f500, 0x78094975, 0xf0011c49, 0xeb010107, 
+    0x4a731101, 0x0181eb02, 0x20006088, 0x80084967, 0xe0002009, 0x4966e027, 0x22008008, 0x6800486f, 
+    0xf83af012, 0x1d204604, 0xf240b950, 0x86a81006, 0x2200e65e, 0x4869495e, 0xf0126800, 0x4604f82d, 
+    0x28001d60, 0xf240d1c5, 0x86a81007, 0xe001e650, 0xe0972401, 0x49552000, 0xf2408008, 0x1e48319b, 
+    0xfe0af7f2, 0x2000e08e, 0x80084957, 0x78004853, 0x485bb158, 0x1c406800, 0x60084959, 0x88004608, 
+    0x4850b201, 0xf7ea38fe, 0xf7f8fd4f, 0x2001f8be, 0xf8aaf7f4, 0xf9904853, 0x49530000, 0x48537008, 
+    0xfd3cf7ea, 0x220f2301, 0x48454951, 0xf7f1380c, 0x2202fb36, 0x484f2104, 0xfb48f7f1, 0x4849b2c6, 
+    0x46317802, 0xf7eb2001, 0x2002fdcb, 0xfe9ff7f2, 0x20082100, 0xfedbf7f4, 0xf7f52001, 0x2001f9cd, 
+    0xfef8f7f4, 0x49312002, 0x200a8008, 0x80084930, 0x48302200, 0xf0116800, 0x4604ffcf, 0xb9501d20, 
+    0x105cf240, 0xe5f386a8, 0x49292200, 0x68004829, 0xffc2f011, 0x1d604604, 0xf240bb90, 0x86a8105d, 
+    0x2401e5e6, 0x4821e02e, 0x28028800, 0x4832d12a, 0x28017800, 0x4821d106, 0xb9187800, 0xf928f7f8, 
+    0xfa20f7f8, 0xfc26f7ff, 0x4919203f, 0x22008008, 0x68004820, 0xffa0f011, 0x1d204604, 0xf240b950, 
+    0x86a81076, 0x2200e5c4, 0x481a4911, 0xf0116800, 0x4604ff93, 0xb9181d60, 0x1077f240, 0xe5b786a8, 
+    0x2401e000, 0xe5a7bf00, 0xbf00bf00, 0xb510e5b0, 0x21012200, 0x5015f2af, 0xfd11f011, 0x20032108, 
+    0xfeaef011, 0x60084903, 0x0000bd10, 0x00038648, 0x0003864c, 0x00038644, 0xd03c8314, 0x00038b1c, 
+    0xd0035026, 0xd0035250, 0x00038b20, 0x00038b38, 0x00048c18, 0x00038b18, 0x00052f80, 0x00038654, 
+    0x00038b3c, 0x0003626a, 0x000361ec, 0xd0060010, 0xffff8000, 0xd03c8c04, 0x000361ee, 0x800849fe, 
+    0xe92d4770, 0x460543f8, 0x8ea84688, 0x2233f240, 0x42901a81, 0xdc54d076, 0x127ff240, 0x0102eba0, 
+    0xd0704290, 0xf5b0dc2b, 0xd06d7f8e, 0x2888dc13, 0xdc06d06b, 0x2880b380, 0x2881d068, 0x80a7f041, 
+    0x2889e0c6, 0xf5b0d075, 0xd0737f8a, 0x1015f2a0, 0xd1f32800, 0xf5b0e17c, 0xd06c7fac, 0xf2a0dc08, 
+    0x2800101d, 0x2823d068, 0x2824d067, 0xe1f6d1e6, 0x1059f2a0, 0xd0732800, 0xd1df2825, 0x293be276, 
+    0xdc0fd06f, 0xd06d2910, 0x2907dc07, 0x2908d06b, 0x290fd06a, 0xe2abd1d2, 0x2935e070, 0x2936d07d, 
+    0xe30bd1cc, 0xd079297b, 0x293cdc06, 0x294bd077, 0x294cd076, 0xe358d1c2, 0xd072297c, 0xd1bd29b3, 
+    0x29bbe3f0, 0xdc27d06e, 0xd06c2996, 0x292cdc10, 0xdc06d06a, 0xd0682907, 0xd0672908, 0xd1ad292b, 
+    0x2955e3ee, 0x2956d06f, 0x2995d06e, 0xe3e8d1a6, 0xd06a29ac, 0x29a3dc0b, 0x29a4d068, 0x29abd067, 
+    0xe3edd19c, 0xe23ee3ed, 0xe071e133, 0x29b3e04f, 0x29b4d07a, 0xe3f9d192, 0xd07629f6, 0x29e7dc13, 
+    0xdc0bd074, 0xd07229bc, 0xd07129c5, 0xd18529c6, 0xe06fe3ed, 0xe1bee0fe, 0xe183e129, 0xd06829e8, 
+    0xd18629f5, 0xf5b1e3f2, 0xd07c7f83, 0x29fddc0d, 0x29fed07a, 0xf2a1d079, 0x29001105, 0xe3f6d186, 
+    0xe2c2e1b8, 0xe221e251, 0xf2a1e22d, 0x290011a3, 0x87a2f000, 0xd18d2901, 0xbfabf000, 0x499f2007, 
+    0x22008008, 0x6800489e, 0xfe86f011, 0x1d204604, 0x2080b9a0, 0xe8bd86a8, 0xe28283f8, 0xe2b1e308, 
+    0xe313e2d6, 0xe3f5e3f5, 0xe3b1e3f5, 0x2200e3bf, 0x48934992, 0xf0116800, 0x4604fe6f, 0xb9401d60, 
+    0x86a82081, 0xe3e7e7e7, 0xe3e7e3e7, 0xe3e7e3e7, 0xf0002401, 0xf04fbfda, 0x498832ff, 0x68004888, 
+    0xfe8cf011, 0x1d204604, 0x2088b948, 0xe7d286a8, 0x49822200, 0x68004882, 0xfe80f011, 0x1d604604, 
+    0x2089b948, 0xe7c686a8, 0xe3fee3fe, 0xe3fee3fe, 0xe3fee3fe, 0x2c012401, 0xe7dad000, 0xf9b04877, 
+    0xf04f1000, 0xf44f4220, 0xf7ea2000, 0x4873fc32, 0x28078800, 0x200bd17d, 0x8008496f, 0xfd4af7f5, 
+    0xf937f014, 0xe3f2e002, 0xe3f2e3f2, 0xf9caf7f7, 0x46112200, 0xf0034610, 0x2003fb55, 0xff4af7f6, 
+    0x20012100, 0xfe4cf7f5, 0x88004866, 0xd10b2801, 0x22002301, 0x48644619, 0xf92af7f1, 0x461a2300, 
+    0x48622103, 0xf94bf7f1, 0xf826f003, 0xf7f52004, 0x2004feb7, 0xff4ef7f5, 0xf7f52004, 0x2001ffe5, 
+    0xfc6ef7f6, 0x22062301, 0x48592140, 0xf937f7f1, 0x22052301, 0x48562120, 0xf931f7f1, 0x22042301, 
+    0x48532110, 0xf92bf7f1, 0x22032300, 0x48502108, 0xf925f7f1, 0x22022301, 0x484d2104, 0xf91ff7f1, 
+    0x22012300, 0x484a2102, 0xf919f7f1, 0x22002301, 0x48474619, 0xf913f7f1, 0xfcb0f7f5, 0x78004845, 
+    0xd1272801, 0x78004844, 0x0001f000, 0x2002b310, 0x70084942, 0x49392026, 0x22008008, 0x68004840, 
+    0xfdbaf011, 0x1d204604, 0xf240b958, 0x86a81014, 0xe02ee731, 0x49312200, 0x68004839, 0xfdacf011, 
+    0x1d604604, 0xd1042800, 0x1015f240, 0xe72286a8, 0xe2b42401, 0x49292006, 0x22008008, 0x68004828, 
+    0xfd9af011, 0x1d204604, 0xf240b950, 0x86a8101c, 0x2200e711, 0x48224921, 0xf0116800, 0x4604fd8d, 
+    0x28001d60, 0xf240d1e5, 0x86a8101d, 0x2401e703, 0x481ae7df, 0x28068800, 0x200cd17e, 0x80084916, 
+    0x49202000, 0x23007008, 0x491f220f, 0xf7f1481f, 0x200cf8b6, 0xf8a8f00c, 0x7800481d, 0xd14f2801, 
+    0xf7f52004, 0x2004fe6a, 0xff01f7f5, 0xf7ea4819, 0x1c40faa5, 0x4639b207, 0xf7ea4816, 0x2066faa5, 
+    0x80084906, 0x48142200, 0xf0116800, 0x4604fd55, 0xb9001d20, 0xe02ce022, 0x00038658, 0x0003865c, 
+    0x00038654, 0x000361cc, 0xd18007fc, 0xd03c8332, 0xd0034228, 0x00038492, 0x000361d8, 0x0003626a, 
+    0x00038ad8, 0x000384d6, 0xffff8000, 0xd28ffffc, 0x000362ce, 0xd0039ffe, 0x00038e64, 0x1040f240, 
+    0xe6a886a8, 0x49fe2200, 0x680048fe, 0xfd24f011, 0x1d604604, 0xf240b920, 0x86a81041, 0x2401e69b, 
+    0x780048f9, 0xf00cb3a8, 0xb240f82b, 0x700849f7, 0xf7f27808, 0x2004fabf, 0xfe0ff7f5, 0xf7f52004, 
+    0x48f2fea6, 0x0000f990, 0xfe34f7f6, 0x780849ef, 0xfc87f7ed, 0xe000206e, 0x49e9e1aa, 0x22008008, 
+    0x680048eb, 0xfcf8f011, 0x1d204604, 0xf240b950, 0x86a81058, 0x2200e66f, 0x48e549e1, 0xf0116800, 
+    0x4604fceb, 0x28001d60, 0xf240d105, 0x86a81059, 0xe001e661, 0xe17d2401, 0x780048de, 0xd00e2801, 
+    0x880048dd, 0x48ddb958, 0x28017800, 0x48dcd007, 0x28017800, 0x48dbd003, 0x28017800, 0xf00bd177, 
+    0xb240ffdf, 0x700849d1, 0xf9904608, 0xf7f60000, 0x49cefdf1, 0xf7ed7808, 0x2004fc44, 0xfd70f7f5, 
+    0xf7f52004, 0x48cffe07, 0x28017800, 0x48ccd003, 0x28017800, 0x2004d107, 0xfe96f7f5, 0xf7f62001, 
+    0xf7f5fb1f, 0x48c3fb8b, 0x28017800, 0x2022d11c, 0x800849bb, 0x48c42200, 0xf0116800, 0x4604fc9d, 
+    0xb9501d20, 0x107ef240, 0xe61486a8, 0x49b42200, 0x680048bd, 0xfc90f011, 0x1d604604, 0xf240b920, 
+    0x86a8107f, 0x2401e607, 0x880048b3, 0x2021b1e0, 0x800849ab, 0x48b42200, 0xf0116800, 0x4604fc7d, 
+    0xb9501d20, 0x1086f240, 0xe5f486a8, 0x49a42200, 0x680048ad, 0xfc70f011, 0x1d604604, 0xf240b920, 
+    0x86a81087, 0x2401e5e7, 0x780048a4, 0xd11d2801, 0x499b2023, 0x22008008, 0x680048a3, 0xfc5cf011, 
+    0x1d204604, 0xf240b958, 0x86a8108e, 0xe026e5d3, 0x49932200, 0x6800489c, 0xfc4ef011, 0x1d604604, 
+    0xf240b920, 0x86a8108f, 0x2401e5c5, 0x78004894, 0xd0032801, 0x78004893, 0xd1082801, 0x78004890, 
+    0xd1052801, 0x21120702, 0xf7ea04c0, 0xe0d1fa32, 0x5280f04f, 0x12502113, 0xfa2bf7ea, 0x488be0ca, 
+    0x28017800, 0x2002d10c, 0xfd54f7f6, 0xf7ed2002, 0xf04ffba8, 0x21155280, 0xf7ea1250, 0xe0b9fa1a, 
+    0x78004883, 0x4883bb60, 0xb3487800, 0xf7f52004, 0x2004fd14, 0xfdabf7f5, 0xf7f62002, 0x2002fd3b, 
+    0xfb8ff7ed, 0x496e2070, 0x22008008, 0x68004876, 0xfc02f011, 0x1d204604, 0xf240b950, 0x86a810b4, 
+    0x2200e579, 0x48704966, 0xf0116800, 0x4604fbf5, 0xbb401d60, 0x10b5f240, 0xe56c86a8, 0xe0892401, 
+    0x7800486b, 0x486cbb00, 0xb1e87800, 0x495c2071, 0x22008008, 0x68004864, 0xfbdef011, 0x1d204604, 
+    0xf240b950, 0x86a810ba, 0x2200e555, 0x485e4954, 0xf0116800, 0x4604fbd1, 0xb9201d60, 0x10bbf240, 
+    0xe54886a8, 0xe0652401, 0x7800485c, 0x485cb910, 0xb3607800, 0xf7f52004, 0x2004fcc0, 0xfd57f7f5, 
+    0xf7f62003, 0x2003fce7, 0xfb3bf7ed, 0x49472003, 0x20057008, 0x80084942, 0x484b2200, 0xf0116800, 
+    0x4604fbab, 0xb9501d20, 0x10caf240, 0xe52286a8, 0x493b2200, 0x68004844, 0xfb9ef011, 0x1d604604, 
+    0xf240bb98, 0x86a810cb, 0x2401e515, 0x2004e032, 0xfc93f7f5, 0xf7f52004, 0x2002fd2a, 0xfcbaf7f6, 
+    0xf7ed2002, 0xf7f8fb0e, 0x4839f99d, 0x28017800, 0x203ad120, 0x8008492a, 0x483a2200, 0xf0116800, 
+    0x4604fb7b, 0xb9501d20, 0x10faf240, 0xe4f286a8, 0x49232200, 0x68004833, 0xfb6ef011, 0x1d604604, 
+    0xf240b928, 0x86a810fb, 0xe003e4e5, 0x20012401, 0x7008492d, 0x7800482d, 0xd1702801, 0x492b2000, 
+    0x23007008, 0x21022201, 0xf7f04829, 0xe5b0fe98, 0x88004813, 0xd1722805, 0x4926200d, 0x20008008, 
+    0x70084921, 0xff95f7ec, 0x78084910, 0xfe7cf00b, 0x48212200, 0x20026801, 0xf9a6f7f2, 0x6800481f, 
+    0x491e1c40, 0x20026008, 0xf97af7f2, 0x6008491c, 0x78084906, 0xfd59f7ed, 0x49012026, 0xe0328008, 
+    0x0003865c, 0x00038e64, 0x0003625c, 0x0003626a, 0x00038a9c, 0x0003625e, 0x00036260, 0x00036264, 
+    0x0003626b, 0x0003626d, 0x00038654, 0x00036266, 0x00036265, 0x000361e9, 0x000361e8, 0x000361ea, 
+    0x0003845c, 0x00038ae4, 0x000384d6, 0x00036270, 0xd03c801c, 0x00038658, 0x000384a4, 0x00052f88, 
+    0x00036310, 0x2200e00e, 0x680048fe, 0xfaf4f011, 0x1d204604, 0xf240b968, 0x86a82032, 0xe037e46b, 
+    0xe127e06f, 0x49f82200, 0x680048f6, 0xfae4f011, 0x1d604604, 0xf240b938, 0x86a82033, 0xe03be45b, 
+    0xe7ffe16d, 0x48f12401, 0x28017800, 0x2020d121, 0x800849ed, 0x48ee2200, 0xf0116800, 0x4604facd, 
+    0xb9601d20, 0x203af240, 0xe44486a8, 0xe203e189, 0x49e52200, 0x680048e6, 0xfabef011, 0x1d604604, 
+    0xd1052800, 0x203bf240, 0xe43486a8, 0x2401e256, 0x2200e239, 0x680148df, 0xf7f22001, 0x48def915, 
+    0x28017800, 0x2002d104, 0x800849dc, 0xe290e22b, 0x49da2003, 0xe2268008, 0x880048d3, 0xd1302870, 
+    0xfc52f7f8, 0x49d62002, 0x20267008, 0x800849ce, 0x780849d3, 0xfdc8f00b, 0x49cb2200, 0x680048c9, 
+    0xfa8af011, 0x1d204604, 0xf240b990, 0x86a8205e, 0xe15ee401, 0xe012e0cc, 0xe059e04c, 0xe0e9e11c, 
+    0x2200e0f5, 0x48bf49c0, 0xf0116800, 0x4604fa75, 0x28001d60, 0xf240d1bc, 0x86a8205f, 0x2401e417, 
+    0x48b9e3e2, 0x28718800, 0x2201d144, 0x48bd2102, 0xfdbcf7f0, 0x2002b910, 0xfb8cf7f6, 0xf7ed2002, 
+    0xf7f8f9e0, 0x48b8fcba, 0x28017800, 0xf003d101, 0x2001ff98, 0x700849b2, 0x49ab2026, 0x49b08008, 
+    0xf00b7808, 0xe005fd81, 0xe1f4e0fe, 0xe12de1bc, 0xe1c7e174, 0x49a42200, 0x680048a2, 0xfa3cf011, 
+    0x1d204604, 0xf240b968, 0x86a82088, 0xe22de480, 0xe206e1fa, 0x499c2200, 0x6800489a, 0xfa2cf011, 
+    0x1d604604, 0xd1862800, 0x2089f240, 0xe46f86a8, 0xe3992401, 0x88004894, 0xd1772808, 0x48970642, 
+    0x1000f9b0, 0xf7ea1250, 0x4894f814, 0x280a8800, 0x4896d160, 0xb9187800, 0xf7f22002, 0xbb40f8fe, 
+    0xfe8ef003, 0xf7f32000, 0x2001f988, 0x60084990, 0x68004890, 0x68094990, 0xda044288, 0x6800488d, 
+    0x498c1c40, 0x488b6008, 0xb2018800, 0xf7e9488b, 0x2000ff3b, 0xfa98f7f3, 0x49892000, 0x201c7008, 
+    0xf8c0f7f2, 0xf7f72000, 0x200af90a, 0x8008497b, 0x4884e35a, 0xf0208800, 0xb1300008, 0x5280f04f, 
+    0x12502119, 0xffd5f7e9, 0x2002e34f, 0xf88ff7f2, 0x49722009, 0x20178008, 0x8008496b, 0x487a2200, 
+    0xf0116800, 0x4604f9c9, 0xb9501d20, 0x20c8f240, 0xe40d86a8, 0x49642200, 0x68004873, 0xf9bcf011, 
+    0x1d604604, 0xd1942800, 0x20c9f240, 0xe40e86a8, 0xe3292401, 0x8800486b, 0x0008f020, 0xf04fb138, 
+    0x21195280, 0xf7e91250, 0xe31effa4, 0x485be0ed, 0x28038800, 0x2010d120, 0x80084953, 0x48632200, 
+    0xf0116800, 0x4604f999, 0xb9501d20, 0x20d6f240, 0xe40b86a8, 0x494c2200, 0x6800485c, 0xf98cf011, 
+    0x1d604604, 0xf240b920, 0x86a820d7, 0x2401e459, 0x494a2004, 0xe2f78008, 0x88004848, 0xd1202804, 
+    0x49412012, 0x22008008, 0x68004851, 0xf974f011, 0x1d204604, 0xf240b950, 0x86a820de, 0x2200e441, 
+    0x484b4939, 0xf0116800, 0x4604f967, 0xb9201d60, 0x20dff240, 0xe43486a8, 0x20052401, 0x80084937, 
+    0x4836e2d2, 0x28028800, 0x2011d120, 0x8008492e, 0x48402200, 0xf0116800, 0x4604f94f, 0xb9501d20, 
+    0x20e6f240, 0xe41c86a8, 0x49272200, 0x68004839, 0xf942f011, 0x1d604604, 0xf240b920, 0x86a820e7, 
+    0x2401e40f, 0x49252005, 0xe2ad8008, 0x88004823, 0xd1202808, 0x491c2016, 0x22008008, 0x6800482e, 
+    0xf92af011, 0x1d204604, 0xf240b950, 0x86a820ee, 0x2200e404, 0x48284914, 0xf0116800, 0x4604f91d, 
+    0xb9201d60, 0x20eff240, 0xe42386a8, 0x20092401, 0x80084912, 0x4811e288, 0x28098800, 0x2002d14e, 
+    0xff39f7f1, 0x49082017, 0x22008008, 0x68004816, 0xf902f011, 0x1d204604, 0xf240b918, 0x86a820f8, 
+    0xe032e408, 0x00038ad8, 0x0003865c, 0x0003845c, 0x00038654, 0x000384a0, 0x000361ee, 0x00038658, 
+    0x0003626a, 0xd28f007c, 0x00036266, 0x00038b1e, 0x00052f8c, 0x00052f90, 0x00052f88, 0xd0035140, 
+    0x000361ec, 0x00036268, 0x00038644, 0x000385b4, 0x000385dc, 0x000385cc, 0x00038634, 0x49fe2200, 
+    0x680048fe, 0xf8c8f011, 0x1d604604, 0xd18c2800, 0x20f9f240, 0xe42886a8, 0xe2352401, 0x5280f04f, 
+    0x12502119, 0xfeb5f7e9, 0x48f3e22f, 0x280b8800, 0xf04fd179, 0x48f25280, 0x1000f9b0, 0xf7e91250, 
+    0x48f0fea8, 0xf0208800, 0xb1300008, 0x5280f04f, 0x12502118, 0xfe9df7e9, 0x48e9e217, 0x28048800, 
+    0x48e9d129, 0x28037800, 0x2014d11e, 0x800849e2, 0x48e62200, 0xf0116800, 0x4604f88f, 0xb9501d20, 
+    0x301af240, 0xe41086a8, 0x49db2200, 0x680048df, 0xf882f011, 0x1d604604, 0xd1be2800, 0x301bf240, 
+    0xe40f86a8, 0xe1ef2401, 0x48d92200, 0x20016801, 0xfedaf7f1, 0x48d2e1e8, 0x28058800, 0x2013d120, 
+    0x800849cd, 0x48d32200, 0xf0116800, 0x4604f865, 0xb9501d20, 0x3028f240, 0xe40786a8, 0x49c62200, 
+    0x680048cc, 0xf858f011, 0x1d604604, 0xf240b920, 0x86a83029, 0x2401e408, 0x49c12006, 0xe1c38008, 
+    0x880048bf, 0xd1212806, 0x49bb2014, 0x22008008, 0x680048be, 0xf840f011, 0x1d204604, 0xf240b958, 
+    0x86a83030, 0xe053e43c, 0x49b32200, 0x680048b7, 0xf832f011, 0x1d604604, 0xf240b920, 0x86a83031, 
+    0x2401e42e, 0x49ae2007, 0xe19d8008, 0x880048ac, 0xd1202807, 0x49a82015, 0x22008008, 0x680048ae, 
+    0xf81af011, 0x1d204604, 0xf240b950, 0x86a83038, 0x2200e416, 0x48a849a0, 0xf0116800, 0x4604f80d, 
+    0xb9201d60, 0x3039f240, 0xe40986a8, 0x20082401, 0x8008499b, 0x489ae178, 0x28088800, 0x2200d106, 
+    0x6801489b, 0xf7f12001, 0xe16dfe5f, 0x88004894, 0xd1062809, 0x48962200, 0x20016801, 0xfe54f7f1, 
+    0xf04fe162, 0x21185280, 0xf7e91250, 0xe15cfde2, 0x88004889, 0xd1112809, 0x78004890, 0x2200b128, 
+    0x2001498f, 0xfe40f7f1, 0x2200e004, 0x2001498d, 0xfe3af7f1, 0x4982200a, 0xe1458008, 0x8800487e, 
+    0xd15f2821, 0x497e200e, 0x48878008, 0x0000f990, 0xf8f0f7f6, 0x78084984, 0xff43f7ec, 0x78004883, 
+    0x0001f000, 0x2101bbf0, 0xf7f42000, 0x487fffe9, 0xf3c07800, 0x22000340, 0x487d2101, 0xfaeff7f0, 
+    0x7800487a, 0x0340f3c0, 0x21102204, 0xf7f04878, 0x4876fae6, 0xf3c07800, 0x22010380, 0x48742102, 
+    0xfaddf7f0, 0x78004871, 0x0380f3c0, 0x21202205, 0xf7f0486f, 0x486dfad4, 0xf3c07800, 0x220203c0, 
+    0x486b2104, 0xfacbf7f0, 0x78004868, 0x03c0f3c0, 0x21402206, 0xf7f04866, 0x4864fac2, 0xf3c07800, 
+    0xe0001300, 0x2203e0a7, 0x48612108, 0xfab7f7f0, 0x7800485e, 0x1300f3c0, 0x21802207, 0xf7f0485c, 
+    0xe0e1faae, 0x8800484c, 0xd1742822, 0x494c200f, 0x23008008, 0x21402206, 0x30084855, 0xfa9ff7f0, 
+    0x22012300, 0x48522102, 0xf7f03008, 0x2300fa98, 0x2101461a, 0x3008484e, 0xfa91f7f0, 0x22062301, 
+    0x484c2140, 0xfa8bf7f0, 0x22022300, 0x48492104, 0xfa85f7f0, 0xf7f72000, 0x2101fecb, 0xf7f104c8, 
+    0x2600fd03, 0x2100bf00, 0xf7f24608, 0x2000fe80, 0x0300f647, 0x46014602, 0xf7f49000, 0x2101ff17, 
+    0xf7f104c8, 0x1c70fcf1, 0xf240b206, 0xf44f11f4, 0xf7e92000, 0x2200fd57, 0x483721ff, 0xfa76f7f0, 
+    0x46394607, 0x2000f44f, 0xfcfcf7e9, 0xf44f4933, 0xf7e92000, 0x2200fcf7, 0x482f21ff, 0xfa66f7f0, 
+    0xd10128ff, 0xdbce2e40, 0x78084927, 0xf908f7f3, 0x78084925, 0xfcaef7f1, 0x49172026, 0x22008008, 
+    0x68004827, 0xfef8f010, 0x1d204604, 0xf240b958, 0x86a830d6, 0xe00ee412, 0x490f2200, 0x68004820, 
+    0xfeeaf010, 0x1d604604, 0xf240b9a8, 0x86a830d7, 0x2401e404, 0x4808e058, 0x28238800, 0x2010d132, 
+    0x80084907, 0xf7f62003, 0x2003f805, 0xfe59f7ec, 0xfdb4f7f4, 0xe045e048, 0x0003865c, 0x00038644, 
+    0x00038658, 0x00036268, 0x0003625c, 0x0003860c, 0x000384a0, 0x000385ec, 0x00038620, 0x00038b1d, 
+    0x0094c5f0, 0x00b71b00, 0x0003626a, 0x00036260, 0xd0034220, 0xd03c8310, 0xd0060042, 0xdcba01f5, 
+    0x00038ad8, 0x8800481a, 0xd11c2820, 0xf7f12002, 0xf009fcd2, 0x4817fa85, 0x28017800, 0x0702d107, 
+    0x04c02116, 0xfc95f7e9, 0xfa97f009, 0x4811e00c, 0x28027800, 0x06c2d108, 0x04802117, 0xfc89f7e9, 
+    0xfb39f009, 0xe000e000, 0xf7ffbf00, 0xbf00b824, 0xe413bf00, 0x2200b510, 0x48072101, 0xfc0ff010, 
+    0x20052108, 0xfdacf010, 0x60084904, 0x0000bd10, 0x0003865c, 0x0003845d, 0x00015dc3, 0x00038654, 
+    0x43f0e92d, 0x4680b0c3, 0x25002710, 0x2400e01f, 0x48f7e019, 0x230149f7, 0xe9cd2200, 0x46211000, 
+    0xf7ef4618, 0x48f2fe2e, 0xfb108800, 0xa903f000, 0x1184eb01, 0x0025f841, 0xf2412100, 0xf7f10000, 
+    0x1c60fc13, 0x2c04b244, 0x1c68dbe3, 0x42bdb205, 0x2400dbdd, 0x2600e02e, 0x1c70e028, 0xe021b205, 
+    0xeb00a803, 0xf8501084, 0xa9030026, 0x1184eb01, 0x1025f851, 0xdd134288, 0xeb00a803, 0xf8501084, 
+    0xa8039026, 0x1084eb00, 0x0025f850, 0xeb01a903, 0xf8411184, 0xa8030026, 0x1084eb00, 0x9025f840, 
+    0xb2051c68, 0xdbdb42bd, 0xb2061c70, 0xdbd442be, 0xb2441c60, 0xdbce2c04, 0xe00c2400, 0xeb074638, 
+    0x104971d0, 0xeb02aa03, 0xf8521284, 0xf8481021, 0x1c601024, 0x2c04b244, 0xb043dbf0, 0x83f0e8bd, 
+    0x47fce92d, 0x46884607, 0x0900f04f, 0xe05a2400, 0xe0542500, 0xd15042ac, 0x21c4eb07, 0x2045eb01, 
+    0x22812308, 0xf01649bc, 0xeb08f92c, 0xeb0121c4, 0x23082045, 0x49b92281, 0xf923f016, 0xe0102681, 
+    0x7080f5c6, 0xf85149b4, 0xf8410020, 0xf5c60026, 0x49b27080, 0x0020f851, 0xf8414240, 0x1c700026, 
+    0x2effb206, 0x2008ddec, 0x464b49ad, 0xe9cd4aad, 0x49aa1000, 0xf01648a8, 0x2180fcfb, 0xf01748aa, 
+    0x2008f86b, 0x4ba549a6, 0xe9cd4aa3, 0x46491000, 0xf01648a4, 0xeb07fa03, 0xeb0020c4, 0x23082145, 
+    0x489d2281, 0xf8fef016, 0x20c4eb08, 0x2145eb00, 0x22812308, 0xf0164899, 0x1c68f8f5, 0x2d04b245, 
+    0x1c60dba8, 0x2c04b244, 0xe8bddba2, 0xb57c87fc, 0x460e4604, 0xeb054615, 0xeb0020c4, 0xeb062044, 
+    0xeb0121c4, 0x23012144, 0xe9cd2200, 0x46211000, 0xf7ef4618, 0xeb05fd56, 0xeb0020c4, 0x88002044, 
+    0x21c4eb06, 0x2144eb01, 0x0100f8a1, 0xeb052000, 0xeb0121c4, 0x80082144, 0x21c4eb05, 0x2144eb01, 
+    0x0100f8a1, 0xe92dbd7c, 0xb0da41f0, 0x497f22e0, 0xf015a822, 0x487eea94, 0x28047800, 0x487dd107, 
+    0x28be7800, 0x2600dd01, 0x2602e00e, 0x4878e00c, 0x28057800, 0x2603d101, 0x4876e006, 0x28417800, 
+    0x2601da01, 0x2600e000, 0xe0302400, 0x466a2100, 0x02c4eb02, 0x60516011, 0x050cf06f, 0x1b60e024, 
+    0x1b28d501, 0x1b60e000, 0x2d004607, 0x4268da01, 0x4628e000, 0x48634680, 0x0027f850, 0x01c6ebc6, 
+    0xeb02aa22, 0xf85101c1, 0xfb801028, 0x466a1001, 0x02c4eb02, 0x3200e9d2, 0x415018c9, 0xeb02466a, 
+    0xe9c202c4, 0x1c6d1000, 0xdbd82d0e, 0x2c111c64, 0x2400dbcc, 0x4668e00b, 0x00c4eb00, 0x88806801, 
+    0xea420402, 0x494f4011, 0x0024f841, 0x2c111c64, 0xe00bdbf1, 0xe0072400, 0xf850484a, 0x00400024, 
+    0xf8414948, 0x1c640024, 0xdbf52c11, 0x68004845, 0x5f00f1b0, 0xe00bddee, 0xe0072400, 0xf8504841, 
+    0x10400024, 0xf841493f, 0x1c640024, 0xdbf52c11, 0x6800483c, 0x4f80f1b0, 0x2400dcee, 0x4839e008, 
+    0x0024f850, 0x5000f100, 0xf8414936, 0x1c640024, 0xdbf42c11, 0xe8bdb05a, 0xe92d81f0, 0x46054ffe, 
+    0x46904689, 0xf8dd469a, 0x2600b030, 0x20001e77, 0x24009002, 0xeb09e023, 0xeb0020c5, 0xf8302045, 
+    0xfb100014, 0xeb08f000, 0xeb0121c5, 0xf8312145, 0xeb081014, 0xeb0222c5, 0xf8322245, 0xfb112014, 
+    0x491d0002, 0x0024f841, 0xf8504608, 0x42b80024, 0xb114dd03, 0xf8504608, 0x1c607024, 0x2c81b204, 
+    0xb90fdbd9, 0x8ffee8bd, 0xe0022600, 0xb2061c70, 0xf5b7107f, 0xdaf90f00, 0xdd0c2e00, 0xe0082400, 
+    0xf850480d, 0x41300024, 0xf841490b, 0x1c600024, 0x2c81b204, 0x2600dbf4, 0x1c70e002, 0x007fb206, 
+    0x0f80f5b7, 0x2e00dbf9, 0x2400dd21, 0x0000e01d, 0x00044b08, 0x00044308, 0x00047b08, 0x00048308, 
+    0x0002fcd0, 0x00045308, 0x00045508, 0x0002f9c4, 0x0003626a, 0x00036226, 0xf85048fb, 0x40b00024, 
+    0xf84149f9, 0x1c600024, 0x2c81b204, 0x2400dbf4, 0x48f5e00a, 0x0024f850, 0xda032840, 0x49f22040, 
+    0x0024f841, 0xb2041c60, 0xdbf22c81, 0x4aee2381, 0xf04f4611, 0xf01630ff, 0x2481fec3, 0xf5c4e008, 
+    0x49e97080, 0x0020f851, 0x0024f841, 0xb2041c60, 0xddf42cff, 0x2185eb0a, 0x48e32281, 0xff22f015, 
+    0x6080f04f, 0x0025f84b, 0x48e01481, 0xfed4f016, 0x49df2008, 0x1000e9cd, 0x49dc4ade, 0x9b0248da, 
+    0xfb56f016, 0x2400e00c, 0x48dae008, 0x0024f850, 0x49d80040, 0x0024f841, 0xb2041c60, 0xdbf42c1f, 
+    0x680048d4, 0x5f00f1b0, 0xe00cdded, 0xe0082400, 0xf85048d0, 0x10400024, 0xf84149ce, 0x1c600024, 
+    0x2c1fb204, 0x48cbdbf4, 0xf1b06800, 0xdced4f80, 0xe0092400, 0xf85048c7, 0xf1000024, 0x49c55000, 
+    0x0024f841, 0xb2041c60, 0xdbf32c1f, 0xe749bf00, 0x4ff0e92d, 0x4606b08d, 0x4691468b, 0x0ac8f106, 
+    0x77c8f506, 0x507ef04f, 0x68306038, 0xf88cf018, 0x68719009, 0xf0184248, 0x9008f887, 0xf0179909, 
+    0x4680ff85, 0x8004f8c7, 0xf0186830, 0x9003f87d, 0xfeeef017, 0x0106e9cd, 0x46404641, 0xf8a0f018, 
+    0xf0179001, 0x2200fee5, 0xe9cd4bab, 0xf0170102, 0xe9cdfde9, 0xe9dd0104, 0xf0172306, 0xe9cdfcaf, 
+    0xf0170108, 0x900bf965, 0xe0662402, 0x900a2000, 0xe0112501, 0x0025f856, 0xf856f018, 0x1b609008, 
+    0x1020f857, 0xf0189808, 0x9009f87b, 0xf017990a, 0x900afeeb, 0xb2051c68, 0xdbeb42a5, 0x0024f856, 
+    0xf842f018, 0x990a9009, 0xfedef017, 0x980a900a, 0x4000f080, 0x990b9009, 0xff38f017, 0x25014680, 
+    0x1b60e00e, 0x1020f857, 0xf0184640, 0x9009f859, 0x1025f857, 0xfec8f017, 0x0025f84a, 0xb2051c68, 
+    0xdbee42a5, 0x8024f84a, 0x46404641, 0xf848f018, 0xf0179001, 0x2200fe8d, 0xe9cd4b7f, 0xf0170102, 
+    0xe9cdfd91, 0x980b0106, 0xfe82f017, 0x0104e9cd, 0x2306e9dd, 0xfc52f017, 0x0108e9cd, 0xf908f017, 
+    0x2501900b, 0xf85ae005, 0xf8470025, 0x1c680025, 0x1c60b205, 0xdbf64285, 0xf109b204, 0x42840001, 
+    0x2400db94, 0xf857e00c, 0xf04f0024, 0xf018418e, 0x9009f817, 0xffacf017, 0x0024f84b, 0xb2041c60, 
+    0x0002f109, 0xdbee4284, 0xe8bdb00d, 0xe92d8ff0, 0xb0924ff7, 0x460e4607, 0x0000f248, 0x683a6030, 
+    0x687a13d1, 0xf0164250, 0x4680fd5f, 0x8004f8c6, 0xf008fb08, 0x0100f248, 0x3be0eba1, 0x13c06838, 
+    0xfa0bfb00, 0xe0422502, 0x0900f04f, 0xe0082401, 0x0024f857, 0x1b2913c0, 0x1021f856, 0x9901fb00, 
+    0x42ac1c64, 0xf857dbf4, 0x44810025, 0x31eaea4f, 0x0000f1c9, 0xfd38f016, 0x24014680, 0xf856e00c, 
+    0x1b281024, 0x0020f856, 0xf008fb00, 0x30e0eb01, 0xf841a901, 0x1c640024, 0xdbf042ac, 0xf840a801, 
+    0xfb088025, 0xf248f008, 0xeba10100, 0xea4f3be0, 0xfb0030ea, 0x2401fa0b, 0xa801e005, 0x0024f850, 
+    0x0024f846, 0x1c681c64, 0xdbf64284, 0x98141c6d, 0x42851c40, 0xb015dbb8, 0x8ff0e8bd, 0x47fce92d, 
+    0x46884607, 0xf04f4691, 0x482c0a00, 0xf2a08800, 0x00401035, 0x2e00b206, 0x2600da00, 0xdd002eef, 
+    0x240026ef, 0xf240e031, 0x48221100, 0xfd54f016, 0xe00c2500, 0x1004eb04, 0x0080eb07, 0x0025f850, 
+    0x19a90280, 0xf8424a1b, 0x1c680021, 0x2d11b205, 0x2008dbf0, 0x4b154916, 0xe9cd4a13, 0x46511000, 
+    0xf0154814, 0xeb08fedb, 0xf06f2184, 0x22810309, 0xf015480d, 0xeb09fd86, 0xf06f2184, 0x22810309, 
+    0xf015480a, 0x1c60fd7e, 0x2c04b244, 0xe8bddbcb, 0xe92d87fc, 0x46804ffe, 0x46174689, 0xe9dd461e, 
+    0x2400ab0c, 0x0000e074, 0x00047b08, 0x00048308, 0x0002fcd0, 0x00045308, 0x3ff00000, 0x0003622a, 
+    0xe0612500, 0x20c4eb07, 0x2044eb00, 0x0015f930, 0x2184eb0a, 0x1025f851, 0xeb064348, 0xeb0121c4, 
+    0xf9312144, 0xeb0b1015, 0xf8522284, 0xfb012025, 0x01400002, 0xeb079002, 0xeb0020c4, 0xf9302044, 
+    0xeb0b0015, 0xf8512184, 0x43481025, 0x21c4eb06, 0x2144eb01, 0x1015f931, 0x2284eb0a, 0x2025f852, 
+    0x0012fb01, 0x90010140, 0x20c4eb07, 0x2044eb00, 0x0015f830, 0xf000fb10, 0x21c4eb06, 0x2144eb01, 
+    0x1015f831, 0x22c4eb06, 0x2244eb02, 0x2015f832, 0x0002fb11, 0x900010c0, 0x98029900, 0xfc54f016, 
+    0xeb08b200, 0xeb0121c4, 0xf8212144, 0xe9dd0015, 0xf0161000, 0xb200fc49, 0x21c4eb09, 0x2144eb01, 
+    0x0015f821, 0xb2051c68, 0xdb9b2d81, 0xb2441c60, 0xdb952c04, 0xe0092400, 0x20002500, 0x21c4eb08, 
+    0x2144eb01, 0x0015f821, 0xb2441c60, 0xdbf32c04, 0x46404649, 0xfbe4f7ff, 0x8ffee8bd, 0x5ffce92d, 
+    0x460f4606, 0xe9dd4693, 0xf04f890c, 0x20010a00, 0xfad0f7ef, 0xf7ef2000, 0x2500facd, 0xeb08e04e, 
+    0xeb0121c5, 0x23082045, 0x49fd2281, 0xfd09f015, 0x21c5eb09, 0x2045eb01, 0x22812308, 0xf01549f9, 
+    0x2481fd00, 0xf5c4e010, 0x49f57080, 0x0020f851, 0x0024f841, 0x7080f5c4, 0xf85149f2, 0x42400020, 
+    0x0024f841, 0xb2041c60, 0xddec2cff, 0x49ee2008, 0x4aee4653, 0x1000e9cd, 0x48e949ea, 0xf8d8f016, 
+    0xe00a2400, 0xf85048e9, 0x1bf10024, 0x41081c49, 0xf84149e6, 0x1c600024, 0x2c81b204, 0x217fdbf2, 
+    0xf01648e3, 0x2001fc39, 0x230049e0, 0xe9cd461a, 0x46291000, 0xf8aef7ef, 0xb2451c68, 0xdbae2d04, 
+    0xd1032e01, 0xf7f32006, 0xe002f8ea, 0xf7f32007, 0xe8bdf8e6, 0xb5109ffc, 0xf0062000, 0x2300fcf9, 
+    0x21082203, 0xf7ef48d3, 0x48d3fcaa, 0x28017800, 0xe000d100, 0x46032000, 0x21042202, 0xf7ef48cd, 
+    0x2301fc9e, 0x46192200, 0xf7ef48ca, 0x2001fc98, 0xfe68f7f2, 0x22002301, 0x48c84619, 0xfc8ff7ef, 
+    0x780048c7, 0xd1032805, 0xf7f2207a, 0xe00afabc, 0x780048c3, 0xd1032804, 0xf7f22083, 0xe002fab4, 
+    0xf7f2206e, 0x2100fab0, 0x1000f240, 0xfefcf7f0, 0x780048b9, 0xf7f1b910, 0xe001ff03, 0xff41f7f1, 
+    0xb5f0bd10, 0x4607b089, 0xcb0f4bb6, 0xc40fac05, 0x90002000, 0xe0062400, 0x30fff04f, 0xf841a905, 
+    0x1c600024, 0x2c04b244, 0x2000dbf6, 0xfe41f7f1, 0xe0bc2500, 0x780048aa, 0xd0032803, 0x880048aa, 
+    0xd1632801, 0x780048a6, 0xd12d2804, 0xe0282400, 0x780048a1, 0xd0042801, 0xf99048a4, 0x42840000, 
+    0xb92dd01d, 0x46112200, 0xf0134620, 0xe016f913, 0xd1052d01, 0x21012200, 0xf0134620, 0xe00ef90b, 
+    0xd1052d02, 0x21022200, 0xf0134620, 0xe006f903, 0xd1042d03, 0x21032200, 0xf0134620, 0x1c60f8fb, 
+    0x2c04b244, 0xe02ddbd4, 0xe0292400, 0x7800488a, 0xd0042801, 0xf990488d, 0x42840000, 0xb92dd01e, 
+    0x46112200, 0xf0134620, 0xe017f8e5, 0xd1052d01, 0x2100022a, 0xf0134620, 0xe00ff8dd, 0xd1052d02, 
+    0x21012200, 0xf0134620, 0xe007f8d5, 0xd1052d03, 0x1200f240, 0x46202101, 0xf8ccf013, 0xb2441c60, 
+    0xdbd32c04, 0x0030f242, 0xff00f7e8, 0xfe45f7f1, 0x0030f242, 0xfefaf7e8, 0x22112300, 0x3100f44f, 
+    0xf7ef4873, 0x2001fbb5, 0xfdc3f7f1, 0xf7ffa801, 0x2000fa27, 0xfdbdf7f1, 0xe0112400, 0xf850a801, 
+    0xa9050024, 0x1024f851, 0xdd074288, 0x5004f80d, 0xf850a801, 0xa9050024, 0x0024f841, 0xb2441c60, 
+    0xdbeb2c04, 0x7800485e, 0xd0032805, 0x7800485c, 0xd11a2804, 0x8800485c, 0x2400b9b8, 0x4856e00f, 
+    0x28017800, 0x4859d004, 0x0000f990, 0xd0044284, 0x2100f240, 0xf7f64620, 0x1c60faf9, 0x2c04b244, 
+    0xf242dbed, 0xf7e80030, 0x1c68feb1, 0x2d04b245, 0xaf40f6ff, 0x4680f04f, 0xe0092400, 0xf850a805, 
+    0x42b00024, 0xa805da02, 0x6024f850, 0xb2441c60, 0xdbf32c04, 0xe0ab2400, 0x7800483f, 0xd0042801, 
+    0xf9904842, 0x42840000, 0x483dd013, 0x28037800, 0x483dd003, 0x28018800, 0x4839d152, 0x28047800, 
+    0xf81dd126, 0xb9280004, 0x46112200, 0xf0134620, 0xe08bf841, 0x0004f81d, 0xd1052801, 0x21012200, 
+    0xf0134620, 0xe081f837, 0x0004f81d, 0xd1052802, 0x21022200, 0xf0134620, 0xe077f82d, 0x0004f81d, 
+    0xd1732803, 0x21032200, 0xf0134620, 0xe06df823, 0x0004f81d, 0x2200b928, 0x46204611, 0xf81af013, 
+    0xf81de064, 0x28010004, 0x0202d105, 0x46202100, 0xf810f013, 0xf81de05a, 0x28020004, 0x2200d105, 
+    0x46202101, 0xf806f013, 0xf81de050, 0x28030004, 0xf240d14c, 0x21011200, 0xf0124620, 0xe045fffb, 
+    0x7800480f, 0xd0032805, 0x7800480d, 0xd13d2804, 0x0004f81d, 0x490fbb00, 0xf7f64620, 0xe035fa67, 
+    0x00047b08, 0x00048308, 0x0002fcd0, 0x00045308, 0x0004550c, 0xd00350e6, 0x000361ee, 0xd0031012, 
+    0x0003626a, 0x0002faa4, 0x000361cc, 0x000362b1, 0xd1800000, 0xfffff800, 0x0004f81d, 0xd1042801, 
+    0x462049fb, 0xfa42f7f6, 0xf81de010, 0x28020004, 0x49f8d104, 0xf7f64620, 0xe007fa39, 0x0004f81d, 
+    0xd1032803, 0x462049f4, 0xfa30f7f6, 0xb2441c60, 0xf6ff2c04, 0xf242af51, 0xf7e80030, 0xf243fde7, 
+    0x208001a0, 0xfdbef7e8, 0x0000f89d, 0xf99d0600, 0xea402001, 0xf99d4002, 0xea402002, 0xf99d2002, 
+    0xea402003, 0x20800102, 0xfd5cf7e8, 0x99052080, 0xfd58f7e8, 0x99062080, 0xfd54f7e8, 0x99072080, 
+    0xfd50f7e8, 0x99082080, 0xfd4cf7e8, 0xb0094630, 0xb570bdf0, 0x780048d9, 0xf7f1b908, 0x2200fd31, 
+    0x46082101, 0xfc8ef001, 0xf44f2100, 0xf7f02080, 0x2200fd1b, 0x20014611, 0xfc84f001, 0x780048d0, 
+    0x2001b138, 0xf800f002, 0x46112200, 0xf0012001, 0x48ccfc79, 0x68006805, 0x20c0f420, 0x600849c9, 
+    0x780048c6, 0x48c8b9c0, 0x6000f990, 0xf9914601, 0x1ccc1000, 0xeb0417e1, 0x10897191, 0x0181eba4, 
+    0xf7f6b248, 0x2001fc8f, 0xfdfbf7ff, 0xfcf8f7f1, 0xf7f64630, 0xbf00fc87, 0xf7ff2001, 0xf7f1fdf2, 
+    0xf242fcef, 0xf7e80040, 0xf7f3fd71, 0x48b5f800, 0x22006005, 0x46082101, 0xfc44f001, 0xe92dbd70, 
+    0xb0854ff0, 0x0900f04f, 0x30fff04f, 0x20009004, 0x1e409003, 0x4ead9002, 0x0a00f04f, 0xf04fbf00, 
+    0x25000b00, 0x0800f04f, 0x4aa9e092, 0x462849a9, 0xf95df7ff, 0x4ba948a8, 0x49a64aa5, 0x46289000, 
+    0xfa1bf7ff, 0xe00b2400, 0xf85048a5, 0x49a50024, 0x0028f841, 0xb2041c60, 0x0001f108, 0xf880fa0f, 
+    0xdbf12c1f, 0x1005eb05, 0xeb024a9f, 0x22100180, 0xf7ff489b, 0x2400fbac, 0xeb05e024, 0x499a1005, 
+    0x0080eb01, 0x0024f850, 0x7080f500, 0xb2001240, 0x0014f826, 0x0014f936, 0xdd01287f, 0xe001207f, 
+    0x0014f936, 0x0014f826, 0x0014f936, 0x0f7ff110, 0xf06fda02, 0xe001007e, 0x0014f936, 0x0014f826, 
+    0xb2041c60, 0xddd82c10, 0x27002400, 0xf836e005, 0x44380014, 0x1c60b207, 0x2c11b204, 0x8c30dbf7, 
+    0xb2001bc0, 0x24008430, 0x1c60e028, 0x0010f816, 0x497eb240, 0x1105eb01, 0x487c5508, 0x1005eb00, 
+    0x497b5d00, 0x1105eb01, 0x48795508, 0x1005eb00, 0x49785d00, 0x1105eb01, 0x20105508, 0x0f44ebb0, 
+    0x4872dd0a, 0x1005eb00, 0x45585700, 0x486fdd04, 0x1005eb00, 0xb004f910, 0xb2041c60, 0xdbd42c10, 
+    0xeb00486a, 0x46281105, 0xfee7f7ee, 0xb2451c68, 0xf6ff2d04, 0xf7f0af6a, 0x2500f840, 0xe07a46a8, 
+    0xe00d2400, 0xf850485f, 0xf1a00028, 0x495c5000, 0x0024f841, 0xb2041c60, 0x0001f108, 0xf880fa0f, 
+    0xdbef2c1f, 0xf8dff7ff, 0x1005eb05, 0xeb024a56, 0x22100180, 0xf7ff4852, 0x2400fb1a, 0xeb05e024, 
+    0x49511005, 0x0080eb01, 0x0024f850, 0x7080f500, 0xb2001240, 0x0014f826, 0x0014f936, 0xdd01287f, 
+    0xe001207f, 0x0014f936, 0x0014f826, 0x0014f936, 0x0f7ff110, 0xf06fda02, 0xe001007e, 0x0014f936, 
+    0x0014f826, 0xb2041c60, 0xddd82c10, 0x27002400, 0xf836e005, 0x44380014, 0x1c60b207, 0x2c11b204, 
+    0x8c30dbf7, 0xb2001bc0, 0x24008430, 0x1c60e019, 0x0010f816, 0x4935b240, 0x1105eb01, 0x48335508, 
+    0x1005eb00, 0x49325d00, 0x1105eb01, 0x48305508, 0x1005eb00, 0x492f5d00, 0x1105eb01, 0x1c605508, 
+    0x2c10b204, 0x4829dbe3, 0x1105eb00, 0xf7ee4628, 0x1c68fe64, 0x2d04b245, 0x2200db82, 0x20014611, 
+    0xfb10f001, 0x78004824, 0x4824b300, 0xf5b07800, 0xdc497f96, 0x78004822, 0x2044b9c0, 0x80084921, 
+    0x22102301, 0x46104619, 0xfaa2f7f1, 0x04c82101, 0xfb8af7f0, 0x2301a802, 0xa904aa03, 0x48199000, 
+    0xff6ef00b, 0xf7f12000, 0xe02ffae4, 0x0000e02c, 0xfffffa00, 0xfffffc00, 0xfffffe00, 0x000361ee, 
+    0x000384d7, 0x0005280c, 0x000362b1, 0x00043078, 0x0003aff0, 0x00038ff0, 0x0004a638, 0x00049638, 
+    0x00045308, 0x00036354, 0x00048b08, 0x000442c8, 0x00044288, 0x0004cc48, 0x00038b1d, 0x00036226, 
+    0x0003845c, 0x00038664, 0x90032000, 0x46112200, 0xf0012001, 0x9803fab7, 0xdd312800, 0x48f92301, 
+    0x2103e9dd, 0xff6ef00c, 0x3220f240, 0x43509804, 0xb2011240, 0xf7e848f4, 0x2500fab7, 0x2400e01d, 
+    0x48f2e011, 0x1005eb00, 0x49f15d00, 0x1105eb01, 0x48ee5508, 0x1005eb00, 0x49ee5d00, 0x1105eb01, 
+    0x1c605508, 0x2c10b204, 0x48e8dbeb, 0x1105eb00, 0xf7ee4628, 0x1c68fdd2, 0x2d04b245, 0xe004dbdf, 
+    0x31fff04f, 0xf7e848e0, 0x4ae3fa8f, 0x48e449e3, 0xfa84f7ff, 0x49e148e0, 0x4ae34be2, 0x1000e9cd, 
+    0x48e349e2, 0xfac5f7ff, 0x780048e2, 0xf7f5b908, 0x48deffa9, 0x4bdb49de, 0xe9cd4adb, 0x46511000, 
+    0xf7ff4648, 0x2200fb4b, 0x20014611, 0xfa5af001, 0xe8bdb005, 0xe92d8ff0, 0xb0964fb0, 0xa328f8df, 
+    0x0a80f10a, 0xb320f8df, 0x0b54f10b, 0xe0282400, 0x4bd12001, 0xb2612200, 0xf7ee9000, 0x2700fd06, 
+    0xaa042100, 0x02c4eb02, 0x60516011, 0x48cae015, 0x0027f850, 0xf85149c8, 0xfb801027, 0xaa041001, 
+    0x02c4eb02, 0x3200e9d2, 0x415018c9, 0xeb02aa04, 0xe9c202c4, 0x1c781000, 0x2f80b207, 0x1c60dbe7, 
+    0x2c04b2c4, 0xa80cdbd4, 0xf8dbf7f2, 0x25002400, 0xa80ce06b, 0x0014f930, 0xdd03281e, 0xa90c201e, 
+    0x0014f821, 0xf930a80c, 0x28000014, 0x2000da03, 0xf821a90c, 0xf04f0014, 0xf2440900, 0xa90c0000, 
+    0x1014f931, 0x0209eb01, 0xf83149ac, 0xfba01012, 0xa80c3101, 0x0014f930, 0x4aa84448, 0x0010f832, 
+    0xfba346cc, 0xfb012e00, 0xfb03e000, 0x215d030c, 0x0e01fba2, 0xe101fb03, 0x110cfb02, 0xea400d40, 
+    0x154920c1, 0x0102e9cd, 0xeb00a804, 0xc90301c4, 0x0100e9cd, 0x2302e9dd, 0xe882f014, 0xeb02aa0e, 
+    0xc20302c4, 0xf850a80e, 0x19450034, 0x78004894, 0xd1122801, 0xf851a90e, 0xf7f20034, 0xb280f95f, 
+    0xaa0e17c1, 0x02c4eb02, 0xa80ec203, 0x0034f850, 0x0100f248, 0xf82a1840, 0xa80e0b02, 0x0034f830, 
+    0x0b02f82b, 0x0001f104, 0x2c04b2c4, 0x4628db91, 0xf944f7f2, 0xf100b280, 0x4882085d, 0x28126800, 
+    0x4880d003, 0x28166800, 0x20a2d104, 0xf000fb08, 0x2810ea4f, 0xf188fa0f, 0x3066486b, 0xf9a4f7e8, 
+    0xf8c04879, 0xb0168000, 0x8fb0e8bd, 0x2007b510, 0xfbc5f7f2, 0xf0052000, 0x2300ffdb, 0x21082203, 
+    0x38504861, 0xff8bf7ee, 0x7800486a, 0x486fb110, 0xb1087800, 0xe0002001, 0x46032000, 0x21042202, 
+    0x38504859, 0xff7bf7ee, 0x22002301, 0x48564619, 0xf7ee3850, 0x2001ff74, 0xf944f7f2, 0x22082301, 
+    0x3100f240, 0xf7ee4862, 0x2301ff6a, 0x46192200, 0xf7ee485f, 0x2301ff64, 0x46192200, 0xf7ee485d, 
+    0x485dff5e, 0x0000f9b0, 0xfd6df7f1, 0xf2402100, 0xf7f01000, 0x2200f9d9, 0x46082101, 0xf942f001, 
+    0x68044856, 0xf4206800, 0x495420c0, 0x20016008, 0xfd00f7ee, 0xf2402100, 0xf7f01000, 0x4845f9c5, 
+    0x28017800, 0x2000d105, 0xfcf4f7ee, 0xf9c8f7f1, 0xf7f1e001, 0x2300fa14, 0xf44f2211, 0x48483100, 
+    0xff06f7ee, 0xf7f12001, 0xf242f914, 0xf7e80030, 0x2200fa3d, 0x20014611, 0xf914f001, 0x6004483f, 
+    0xb510bd10, 0xfeb7f7ff, 0x68044837, 0x7800483d, 0xd1452801, 0x7800483c, 0xd1272803, 0x7ff5f5b4, 
+    0xf240dd12, 0x4284505a, 0x4604dd00, 0xfb042195, 0x4360f001, 0xfb014935, 0x49350014, 0xf3c04408, 
+    0x49345087, 0xe13b7008, 0xda002cd9, 0xf24024d9, 0xfb041149, 0x4360f001, 0xfb01492f, 0x492f0014, 
+    0xf3c04408, 0x492b40c7, 0xe1297008, 0x78004826, 0xd16f2805, 0x7fc3f5b4, 0xf240dd56, 0x428450aa, 
+    0x4604dd00, 0x1044ebc4, 0x43600080, 0xfb014924, 0x49240014, 0xf3c04408, 0x491e5047, 0xe10f7008, 
+    0x0000e088, 0x00038664, 0xd003513c, 0x000442c8, 0x00038e90, 0x00044288, 0x00041ff0, 0x00040ff0, 
+    0x00048b08, 0x0003aff0, 0x00038ff0, 0x0003eff0, 0x0003cff0, 0x000361ee, 0x00045308, 0x00038a5c, 
+    0x00036348, 0x000361dc, 0x000384dc, 0x0003845c, 0xd0030444, 0xd0031012, 0x0003622a, 0x0005280c, 
+    0xd1800000, 0x00036342, 0x0003626a, 0x00076f2a, 0x17b83f3e, 0x00036226, 0x00055d10, 0x070181d0, 
+    0x00059136, 0x10133079, 0x6151f240, 0xf001fb04, 0x496c4360, 0x0014fb01, 0x4408496b, 0x5047f3c0, 
+    0x7008496a, 0x78004608, 0xdd8e2891, 0x70082091, 0xe7ffe0b6, 0x78004866, 0xd1862804, 0x7fa3f5b4, 
+    0xf5b4db13, 0xdd016f8c, 0x4460f240, 0x1044eb04, 0x00c0ebc0, 0x495f4360, 0x0014fb01, 0x4408495e, 
+    0x5047f3c0, 0x70084959, 0xf240e09a, 0xfb04311b, 0x4360f001, 0xfb014959, 0x49590014, 0xf3c04408, 
+    0x49524087, 0x46087008, 0x28f57800, 0x20f5dd01, 0xe0857008, 0x7800484e, 0xd1232803, 0x7fa1f5b4, 
+    0xf240db12, 0x4284502c, 0x4604dd00, 0xfb0421a9, 0x4360f001, 0xfb01494b, 0x494b0014, 0xf3c04408, 
+    0x49425087, 0xe06b7008, 0x49494848, 0x0004fb01, 0x493e0c00, 0x46087008, 0x287b7800, 0x207bdd60, 
+    0xe05d7008, 0x7800483a, 0xd12a2805, 0x7fc3f5b4, 0xf240dd12, 0x428450aa, 0x4604dd00, 0x1044ebc4, 
+    0x43600080, 0xfb01493b, 0x493b0014, 0xf3c04408, 0x492e5047, 0xe0437008, 0x6151f240, 0xf001fb04, 
+    0x49284360, 0x0014fb01, 0x44084927, 0x5047f3c0, 0x70084926, 0x78004608, 0xdd312891, 0x70082091, 
+    0x4823e02e, 0x28047800, 0xf5b4d12a, 0xdd137f9b, 0x50dcf240, 0xdd004284, 0xf2404604, 0xfb041151, 
+    0x4360f001, 0xfb014925, 0x49250014, 0xf3c04408, 0x49165087, 0xe0137008, 0x7185f641, 0xf001fb04, 
+    0x49204360, 0x0014fb01, 0x4408491f, 0x5087f3c0, 0x7008490e, 0x78004608, 0xdd0128fa, 0x700820fa, 
+    0x0100f640, 0xf7e80308, 0x4808f8ad, 0xf44f7801, 0xf7e80000, 0x4805f857, 0x48147801, 0xffb4f7e7, 
+    0x0000bd10, 0x0017647b, 0x1dcb8bb0, 0x00036226, 0x0003626a, 0x00088b19, 0x1502dd5d, 0x00086510, 
+    0x0728cd11, 0x00083b16, 0x18e997a9, 0x00a84018, 0xffffaba0, 0x00059136, 0x10133079, 0x000f9c4d, 
+    0x2ec83679, 0x005ddb00, 0x61737224, 0xd0035182, 0x41f0e92d, 0x460d4604, 0x461f4616, 0x8018f8dd, 
+    0x22004623, 0x48fd2101, 0xfd52f7ee, 0x22004623, 0x48fa2101, 0xf7ee1d00, 0x4623fd4b, 0x21012200, 
+    0x300848f6, 0xfd44f7ee, 0x22004623, 0x48f32101, 0xf7ee300c, 0x462bfd3d, 0x01512208, 0xf7ee48ef, 
+    0x462bfd37, 0x01512208, 0x1d0048ec, 0xfd30f7ee, 0x2208462b, 0x48e90151, 0xf7ee3008, 0x462bfd29, 
+    0x01512208, 0x300c48e5, 0xfd22f7ee, 0x220c4633, 0x0100f241, 0xf7ee48e1, 0x4633fd1b, 0xf241220c, 
+    0x48de0100, 0xf7ee1d00, 0x4633fd13, 0xf241220c, 0x48da0100, 0xf7ee3008, 0x4633fd0b, 0xf241220c, 
+    0x48d60100, 0xf7ee300c, 0x463bfd03, 0x21102204, 0xf7ee48d2, 0x463bfcfd, 0x21102204, 0x1d0048cf, 
+    0xfcf6f7ee, 0x2204463b, 0x48cc2110, 0xf7ee3008, 0x463bfcef, 0x21102204, 0x300c48c8, 0xfce8f7ee, 
+    0x22104643, 0x48c50311, 0xfce2f7ee, 0x22104643, 0x48c20311, 0xf7ee1d00, 0x4643fcdb, 0x03112210, 
+    0x300848be, 0xfcd4f7ee, 0x22104643, 0x48bb0311, 0xf7ee300c, 0xe8bdfccd, 0xe92d81f0, 0x240041f0, 
+    0x49b7e0b0, 0x21401860, 0xfeeef7e7, 0x318049b4, 0x21401860, 0xfee8f7e7, 0x186049b2, 0xf7e72140, 
+    0x49b0fee3, 0x18603180, 0xf7e72140, 0x49aefedd, 0x21401860, 0xfed8f7e7, 0x318049ab, 0x21401860, 
+    0xfed2f7e7, 0x186049a9, 0xf7e72140, 0x49a7fecd, 0x18603180, 0xf7e72140, 0x49a5fec7, 0x21401860, 
+    0xfec2f7e7, 0x318049a2, 0x21401860, 0xfebcf7e7, 0x186049a0, 0xf7e72140, 0x499efeb7, 0x18603180, 
+    0xf7e72140, 0x499cfeb1, 0x21401860, 0xfeacf7e7, 0x31804999, 0x21401860, 0xfea6f7e7, 0x18604997, 
+    0xf7e72140, 0x4995fea1, 0x18603180, 0xf7e72140, 0x4993fe9b, 0x21401860, 0xfe96f7e7, 0x31804990, 
+    0x21401860, 0xfe90f7e7, 0x1860498e, 0xf7e72140, 0x498cfe8b, 0x18603180, 0xf7e72140, 0x498afe85, 
+    0x21401860, 0xfe80f7e7, 0x31804987, 0x21401860, 0xfe7af7e7, 0x18604985, 0xf7e72140, 0x4983fe75, 
+    0x18603180, 0xf7e72140, 0x4981fe6f, 0x21401860, 0xfe6af7e7, 0x3180497e, 0x21401860, 0xfe64f7e7, 
+    0x1860497c, 0xf7e72140, 0x497afe5f, 0x18603180, 0xf7e72140, 0x4978fe59, 0x21401860, 0xfe54f7e7, 
+    0x31804975, 0x21401860, 0xfe4ef7e7, 0x18604973, 0xf7e72140, 0x4971fe49, 0x18603180, 0xf7e72140, 
+    0x1ca4fe43, 0xf4ff2c20, 0x2400af4c, 0x495ce038, 0x1860391c, 0x1100f240, 0xfe36f7e7, 0x390c4958, 
+    0xf2401860, 0xf7e71100, 0x4959fe2f, 0x1860391c, 0x1100f240, 0xfe28f7e7, 0x390c4955, 0xf2401860, 
+    0xf7e71100, 0x4956fe21, 0x1860391c, 0x1100f240, 0xfe1af7e7, 0x390c4952, 0xf2401860, 0xf7e71100, 
+    0x4953fe13, 0x1860391c, 0x1100f240, 0xfe0cf7e7, 0x390c494f, 0xf2401860, 0xf7e71100, 0x1ca4fe05, 
+    0xd3c42c08, 0x0800f04f, 0x2700e021, 0x2600e01b, 0x0330e016, 0x2007ea40, 0x1108ea40, 0x38f84837, 
+    0xfde7f7e7, 0x20402101, 0xfe6ef7ef, 0x48332100, 0xf7e738f4, 0x2101fdde, 0xf7ef2040, 0x1c76fe65, 
+    0xd3e62e04, 0x2f041c7f, 0xf108d3e1, 0xf1b80801, 0xd3da0f02, 0xe0b32500, 0x2300b93d, 0x21102204, 
+    0x38f04826, 0xfba4f7ee, 0x2d01e01a, 0x2300d107, 0x21102204, 0x38e04821, 0xfb9af7ee, 0x2d02e010, 
+    0x2300d107, 0x21102204, 0x38d0481c, 0xfb90f7ee, 0x2300e006, 0x21102204, 0x38c04818, 0xfb88f7ee, 
+    0x2300b93d, 0x21102204, 0x38ec4814, 0xfb80f7ee, 0x2d01e01a, 0x2300d107, 0x21102204, 0x38dc480f, 
+    0xfb76f7ee, 0x2d02e010, 0x2300d107, 0x21102204, 0x38cc480a, 0xfb6cf7ee, 0x2300e006, 0x21102204, 
+    0x38bc4806, 0xfb64f7ee, 0x2300b93d, 0x21102204, 0x38e84802, 0xfb5cf7ee, 0xe021e03c, 0xd18005bc, 
+    0xd003c400, 0xd003c500, 0xd003c600, 0xd003c700, 0xd003cc00, 0xd003cd00, 0xd003ce00, 0xd003cf00, 
+    0xd003d400, 0xd003d500, 0xd003d600, 0xd003d700, 0xd003dc00, 0xd003dd00, 0xd003de00, 0xd003df00, 
+    0xd1062d01, 0x22042300, 0x48f72110, 0xfb30f7ee, 0x2d02e010, 0x2300d107, 0x21102204, 0x301048f2, 
+    0xfb26f7ee, 0x2300e006, 0x21102204, 0x302048ee, 0xfb1ef7ee, 0x2300b93d, 0x21102204, 0x380c48ea, 
+    0xfb16f7ee, 0x2d01e01a, 0x2300d107, 0x21102204, 0x1d0048e5, 0xfb0cf7ee, 0x2d02e010, 0x2300d107, 
+    0x21102204, 0x301448e0, 0xfb02f7ee, 0x2300e006, 0x21102204, 0x302448dc, 0xfafaf7ee, 0xb2c51c68, 
+    0xf6ff2d04, 0x2700af49, 0x2600e019, 0x0330e014, 0x2107ea40, 0x303048d4, 0xfd0bf7e7, 0x20402101, 
+    0xfd92f7ef, 0x48d02100, 0xf7e73034, 0x2101fd02, 0xf7ef2040, 0x1c76fd89, 0xd3e82e04, 0x2f041c7f, 
+    0x2500d3e3, 0xb93de090, 0x22042301, 0x48c62110, 0xf7ee3818, 0xe01afacd, 0xd1072d01, 0x22042301, 
+    0x48c12110, 0xf7ee3808, 0xe010fac3, 0xd1072d02, 0x22042301, 0x48bc2110, 0xf7ee3008, 0xe006fab9, 
+    0x22042301, 0x48b82110, 0xf7ee3018, 0xb93dfab1, 0x22042301, 0x48b42110, 0xf7ee3814, 0xe01afaa9, 
+    0xd1072d01, 0x22042301, 0x48af2110, 0xf7ee1f00, 0xe010fa9f, 0xd1072d02, 0x22042301, 0x48aa2110, 
+    0xf7ee300c, 0xe006fa95, 0x22042301, 0x48a62110, 0xf7ee301c, 0xb93dfa8d, 0x22042301, 0x48a22110, 
+    0xf7ee3810, 0xe019fa85, 0xd1062d01, 0x22042301, 0x489d2110, 0xfa7cf7ee, 0x2d02e010, 0x2301d107, 
+    0x21102204, 0x30104898, 0xfa72f7ee, 0x2301e006, 0x21102204, 0x30204894, 0xfa6af7ee, 0x2301b93d, 
+    0x21102204, 0x380c4890, 0xfa62f7ee, 0x2d01e01a, 0x2301d107, 0x21102204, 0x1d00488b, 0xfa58f7ee, 
+    0x2d02e010, 0x2301d107, 0x21102204, 0x30144886, 0xfa4ef7ee, 0x2301e006, 0x21102204, 0x30244882, 
+    0xfa46f7ee, 0xb2c51c68, 0xf6ff2d04, 0xe8bdaf6c, 0xe92d81f0, 0x460747f0, 0x4615460c, 0xf8dd461e, 
+    0x487a8020, 0x20c4eb00, 0x2045eb00, 0x10c6eb00, 0xfb012102, 0x48760908, 0xb9187800, 0x46484639, 
+    0xfc52f7e7, 0x87f0e8bd, 0x47f0e92d, 0x460c4607, 0x461e4615, 0x8020f8dd, 0xeb00486c, 0xeb0020c4, 
+    0xeb002045, 0x210210c6, 0x0908fb01, 0xf7e74648, 0x4648fc35, 0xfc32f7e7, 0xe8bd8038, 0xe92d87f0, 
+    0xb0a14ff0, 0x0a5ef04f, 0x0b22f04f, 0x901f201e, 0x4960223c, 0xf013a810, 0xa05fec12, 0x900f6800, 
+    0xe0f32600, 0xe0ec2700, 0xe0e52500, 0xda3f2d02, 0xb26b2007, 0xb271b27a, 0xa8069000, 0xffc4f7ff, 
+    0x0018f9bd, 0xda084550, 0x0018f9bd, 0xdd024558, 0x0018f9bd, 0x4658e002, 0x4650e000, 0x20079006, 
+    0xb27ab26b, 0x9000b271, 0x0018f9bd, 0xff91f7ff, 0xb26b2009, 0xb271b27a, 0xa8069000, 0xffa4f7ff, 
+    0x0018f9bd, 0xda084550, 0x0018f9bd, 0xdd024558, 0x0018f9bd, 0x4658e002, 0x4650e000, 0x20099006, 
+    0xb27ab26b, 0x9000b271, 0x0018f9bd, 0xff71f7ff, 0xf910a80f, 0x24009005, 0xebc5e021, 0xa9101005, 
+    0x57004408, 0xb27ab26b, 0x9000b271, 0xf7ffa806, 0xf9bdff7b, 0x45500018, 0xf9bdda08, 0x45580018, 
+    0xf9bddd02, 0xe0020018, 0xe0004658, 0x90064650, 0x0018f9bd, 0xf821a907, 0x1c600014, 0x454cb2c4, 
+    0x2400dbdb, 0xaa07e05e, 0xf9321c61, 0xf9321011, 0x1a882014, 0xdb012800, 0xe0004601, 0xb2094241, 
+    0x99059105, 0x4281981f, 0x991fdd4a, 0x1a409805, 0x71d0eb00, 0x10489004, 0xfee9f015, 0x0100e9cd, 
+    0xf980f015, 0x0102e9cd, 0xfe84f015, 0xf880fa0f, 0xf930a807, 0xaa071014, 0xf9321c60, 0x42810010, 
+    0xa807da1c, 0x0014f830, 0xb2004440, 0xf821a907, 0x1c600014, 0x0010f831, 0x0008eba0, 0x1c60b201, 
+    0x1010f822, 0x0000e01c, 0xd18004e4, 0xd003c400, 0x00038b1c, 0x0002fab4, 0x0d0f0f0f, 0xf830a807, 
+    0xeba00014, 0xb2000008, 0xf821a907, 0x1c600014, 0x0010f831, 0xb2014440, 0x1c60aa07, 0x1010f822, 
+    0xb2c41c60, 0x0001f1a9, 0xdc9c42a0, 0xe00f2400, 0x1005ebc5, 0x4408a910, 0xa9075700, 0xf9319000, 
+    0xb26b0014, 0xb271b27a, 0xfed3f7ff, 0xb2c41c60, 0xdbed454c, 0xb2c51c68, 0xf6ff2d04, 0x1c78af17, 
+    0x2f02b2c7, 0xaf10f6ff, 0xb2c61c70, 0xf6ff2e04, 0xb021af09, 0x8ff0e8bd, 0x2000b538, 0x800849fc, 
+    0xe2402400, 0x48fab944, 0xb2838800, 0x0291220c, 0xf7ee48f8, 0xe01df914, 0xd1082c01, 0x880048f4, 
+    0x220cb283, 0x48f40291, 0xf909f7ee, 0x2c02e012, 0x48efd108, 0xb2838800, 0x0291220c, 0xf7ee48ef, 
+    0xe007f8fe, 0x880048ea, 0x220cb283, 0x48ec0291, 0xf8f5f7ee, 0x2303b944, 0xf247220c, 0x48e50100, 
+    0xf7ee307a, 0xe01df8ec, 0xd1082c01, 0x220c2303, 0x0100f247, 0x307a48e0, 0xf8e1f7ee, 0x2c02e012, 
+    0x2303d108, 0xf247220c, 0x48dc0100, 0xf7ee307a, 0xe007f8d6, 0x220c2303, 0x0100f247, 0x307a48d8, 
+    0xf8cdf7ee, 0x2301b93c, 0x02592209, 0x307c48d1, 0xf8c5f7ee, 0x2c01e01a, 0x2301d107, 0x02592209, 
+    0x307c48cd, 0xf8bbf7ee, 0x2c02e010, 0x2301d107, 0x02592209, 0x307c48c9, 0xf8b1f7ee, 0x2301e006, 
+    0x02592209, 0x307c48c6, 0xf8a9f7ee, 0x2300b944, 0xf2402206, 0x48bf11c0, 0xf7ee3082, 0xe01df8a0, 
+    0xd1082c01, 0x22062300, 0x11c0f240, 0x308248ba, 0xf895f7ee, 0x2c02e012, 0x2300d108, 0xf2402206, 
+    0x48b611c0, 0xf7ee3082, 0xe007f88a, 0x22062300, 0x11c0f240, 0x308248b2, 0xf881f7ee, 0x2300b93c, 
+    0x49b0220f, 0x308248ab, 0xf879f7ee, 0x2c01e01a, 0x2300d107, 0x49ab220f, 0x308248a7, 0xf86ff7ee, 
+    0x2c02e010, 0x2300d107, 0x49a6220f, 0x308248a3, 0xf865f7ee, 0x2300e006, 0x49a2220f, 0x308248a0, 
+    0xf85df7ee, 0x2300b93c, 0x2103461a, 0x30844899, 0xf855f7ee, 0x2c01e01a, 0x2300d107, 0x2103461a, 
+    0x30844895, 0xf84bf7ee, 0x2c02e010, 0x2300d107, 0x2103461a, 0x30844891, 0xf841f7ee, 0x2300e006, 
+    0x2103461a, 0x3084488e, 0xf839f7ee, 0x2300b93c, 0x211c2202, 0x30844887, 0xf831f7ee, 0x2c01e01a, 
+    0x2300d107, 0x211c2202, 0x30844883, 0xf827f7ee, 0x2c02e010, 0x2300d107, 0x211c2202, 0x3084487f, 
+    0xf81df7ee, 0x2300e006, 0x211c2202, 0x3084487c, 0xf815f7ee, 0x2300b944, 0xf2402205, 0x487511e0, 
+    0xf7ee3084, 0xe01df80c, 0xd1082c01, 0x22052300, 0x11e0f240, 0x30844870, 0xf801f7ee, 0x2c02e012, 
+    0x2300d108, 0xf2402205, 0x486c11e0, 0xf7ed3084, 0xe007fff6, 0x22052300, 0x11e0f240, 0x30844868, 
+    0xffedf7ed, 0x2300b944, 0xf6412209, 0x48616100, 0xf7ed3084, 0xe01dffe4, 0xd1082c01, 0x22092300, 
+    0x6100f641, 0x3084485c, 0xffd9f7ed, 0x2c02e012, 0x2300d108, 0xf6412209, 0x48586100, 0xf7ed3084, 
+    0xe007ffce, 0x22092300, 0x6100f641, 0x30844854, 0xffc5f7ed, 0x2300b93c, 0x4953220d, 0x3084484d, 
+    0xffbdf7ed, 0x2c01e01a, 0x2300d107, 0x494e220d, 0x30844849, 0xffb3f7ed, 0x2c02e010, 0x2300d107, 
+    0x4949220d, 0x30844845, 0xffa9f7ed, 0x2300e006, 0x4945220d, 0x30844842, 0xffa1f7ed, 0x2300b93c, 
+    0x01d12207, 0x3088483b, 0xff99f7ed, 0x2c01e01a, 0x2300d107, 0x01d12207, 0x30884837, 0xff8ff7ed, 
+    0x2c02e010, 0x2300d107, 0x01d12207, 0x30884833, 0xff85f7ed, 0x2300e006, 0x01d12207, 0x30884830, 
+    0xff7df7ed, 0x2305b93c, 0x21702204, 0x307a4829, 0xff75f7ed, 0x2c01e01a, 0x2305d107, 0x21702204, 
+    0x307a4825, 0xff6bf7ed, 0x2c02e010, 0x2305d107, 0x21702204, 0x307a4821, 0xff61f7ed, 0x2305e006, 
+    0x21702204, 0x307a481e, 0xff59f7ed, 0x2301b944, 0xf640220a, 0x48174100, 0xf7ed3008, 0xe01dff50, 
+    0xd1082c01, 0x220a2301, 0x4100f640, 0x30084812, 0xff45f7ed, 0x2c02e012, 0x2301d108, 0xf640220a, 
+    0x480e4100, 0xf7ed3008, 0xe007ff3a, 0x220a2301, 0x4100f640, 0x3008480a, 0xff31f7ed, 0x2302b9b4, 
+    0x210c461a, 0x30324803, 0xff29f7ed, 0x0000e026, 0x0003866c, 0xd003c20e, 0xd003ca0e, 0xd003d20e, 
+    0xd003da0e, 0xffff8000, 0xffffe000, 0xd1062c01, 0x461a2302, 0x48f9210c, 0xff11f7ed, 0x2c02e00e, 
+    0x2302d106, 0x210c461a, 0xf7ed48f5, 0xe005ff08, 0x461a2302, 0x48f3210c, 0xff01f7ed, 0x2301b934, 
+    0x0359220d, 0xf7ed48f0, 0xe01afefa, 0xd1072c01, 0x220d2301, 0x48e90359, 0xf7ed300e, 0xe010fef0, 
+    0xd1072c02, 0x220d2301, 0x48e50359, 0xf7ed300e, 0xe006fee6, 0x220d2301, 0x48e20359, 0xf7ed300e, 
+    0x1c60fede, 0x2c04b244, 0xadbcf6ff, 0x23012000, 0x46194602, 0x46189000, 0xf94af7ff, 0x22142300, 
+    0x1180f44f, 0xf7ed48d9, 0xf7fffea3, 0x2300f9d6, 0x03112210, 0x380848d5, 0xfe9af7ed, 0xe0252400, 
+    0x2300b93c, 0x21042202, 0x300e48cf, 0xfeb7f7ed, 0x2c01e01a, 0x2300d107, 0x21042202, 0x301c48c7, 
+    0xfeadf7ed, 0x2c02e010, 0x2300d107, 0x21042202, 0x301c48c3, 0xfea3f7ed, 0x2300e006, 0x21042202, 
+    0x301c48c0, 0xfe9bf7ed, 0xb2441c60, 0xdbd72c04, 0x48bf2140, 0xf898f7e7, 0xe0252400, 0x2301b93c, 
+    0x46192200, 0x38b048b9, 0xfe62f7ed, 0x2c01e01a, 0x2301d107, 0x46192200, 0x38a848b4, 0xfe58f7ed, 
+    0x2c02e010, 0x2301d107, 0x46192200, 0x38a048af, 0xfe4ef7ed, 0x2301e006, 0x46192200, 0x389848ab, 
+    0xfe46f7ed, 0xb2441c60, 0xdbd72c04, 0x221fbf00, 0x48a607d1, 0xf7ed38b0, 0x2800fe52, 0x221fd0f7, 
+    0x48a207d1, 0xf7ed38a8, 0x2800fe4a, 0x221fd0ef, 0x489e07d1, 0xf7ed38a0, 0x2800fe42, 0x221fd0e7, 
+    0x489a07d1, 0xf7ed3898, 0x2800fe3a, 0xf7ffd0df, 0x2301fc16, 0x03112210, 0x38084894, 0xfe18f7ed, 
+    0xe0252400, 0x2301b93c, 0x21042202, 0x300e488e, 0xfe35f7ed, 0x2c01e01a, 0x2301d107, 0x21042202, 
+    0x301c4886, 0xfe2bf7ed, 0x2c02e010, 0x2301d107, 0x21042202, 0x301c4882, 0xfe21f7ed, 0x2301e006, 
+    0x21042202, 0x301c487f, 0xfe19f7ed, 0xb2441c60, 0xdbd72c04, 0x46032000, 0x46014602, 0xf7ff9000, 
+    0xbd38f887, 0x43f8e92d, 0x460f4606, 0x48794690, 0x28047800, 0xf04fd101, 0x20000800, 0x46424603, 
+    0x90004639, 0xf7ff4630, 0x2400f873, 0x2500e035, 0x4a6ee02f, 0xeb023a90, 0xeb021244, 0xf00600c5, 
+    0x4b6d0201, 0x0103ea42, 0xffe3f7e6, 0x3a8c4a67, 0x1244eb02, 0x00c5eb02, 0x0201f006, 0xea424b67, 
+    0xf7e60103, 0x4a66ffd6, 0xf2407812, 0xea037300, 0xf0422202, 0xf0070210, 0xea420301, 0x4a5b0103, 
+    0xeb023218, 0xeb021204, 0xf7e60085, 0x1c68ffc2, 0x2d04b2c5, 0x1c60dbcd, 0x2c04b2c4, 0x2400dbc7, 
+    0xb944e0cc, 0x22182309, 0x51f8f04f, 0x3068484f, 0xfd8ef7ed, 0x2c01e01d, 0x2309d108, 0xf04f2218, 
+    0x484a51f8, 0xf7ed306c, 0xe012fd83, 0xd1082c02, 0x22182309, 0x51f8f04f, 0x30704844, 0xfd78f7ed, 
+    0x2309e007, 0xf04f2218, 0x484051f8, 0xf7ed3074, 0xb93cfd6f, 0x2212230f, 0x483c0499, 0xf7ed3068, 
+    0xe01afd67, 0xd1072c01, 0x2212230f, 0x48370499, 0xf7ed306c, 0xe010fd5d, 0xd1072c02, 0x2212230f, 
+    0x48320499, 0xf7ed3070, 0xe006fd53, 0x2212230f, 0x482e0499, 0xf7ed3074, 0xb93cfd4b, 0x22042305, 
+    0x482a2170, 0xf7ed3068, 0xe01afd43, 0xd1072c01, 0x22042305, 0x48252170, 0xf7ed306c, 0xe010fd39, 
+    0xd1072c02, 0x22042305, 0x48202170, 0xf7ed3070, 0xe006fd2f, 0x22042305, 0x481c2170, 0xf7ed3074, 
+    0xb93cfd27, 0x461a2301, 0x48182102, 0xf7ed3068, 0xe01afd1f, 0xd1072c01, 0x461a2301, 0x48132102, 
+    0xf7ed306c, 0xe010fd15, 0xd1072c02, 0x461a2301, 0x480e2102, 0xf7ed3070, 0xe006fd0b, 0x461a2301, 
+    0x480a2102, 0xf7ed3074, 0xb9dcfd03, 0x22004643, 0x48062101, 0xf7ed3068, 0xe02dfcfb, 0xd003ca40, 
+    0xd003d240, 0xd003da40, 0xd003c24e, 0xd18004b4, 0xd003c424, 0x0003626a, 0x147c8002, 0x127c1002, 
+    0x000384d8, 0xd1062c01, 0x22004643, 0x48fe2101, 0xfcdef7ed, 0x2c02e010, 0x4643d107, 0x21012200, 
+    0x1d0048f9, 0xfcd4f7ed, 0x4643e006, 0x21012200, 0x300848f5, 0xfcccf7ed, 0xb2c41c60, 0xf6ff2c04, 
+    0xe8bdaf30, 0xb57083f8, 0x24004606, 0x2500e013, 0x4aede00d, 0xeb023a54, 0xeb021204, 0xf0060085, 
+    0xf4420201, 0xf7e661a2, 0x1c68fed4, 0x2d04b2c5, 0x1c60dbef, 0x2c04b2c4, 0xbd70dbe9, 0x4ff0e92d, 
+    0x48e2b0bf, 0x48e2903d, 0xf8df903c, 0xf8dfa388, 0x48e2b388, 0x4ae2903b, 0xab1eca07, 0x48e0c307, 
+    0xe9d0300c, 0x68801200, 0x121be9cd, 0x4adc901d, 0xca073218, 0xc307ab18, 0x32244ad9, 0xab15ca07, 
+    0x2230c307, 0x313049d6, 0xf012a809, 0x48d5ee98, 0x28017800, 0x2008d107, 0x20049022, 0x20009021, 
+    0x700849d0, 0x2001e006, 0x90219022, 0x90222008, 0x90212004, 0x903e2002, 0x0900f04f, 0x2000e181, 
+    0xf821a905, 0x46800019, 0x2001e175, 0x48c69024, 0xb9988800, 0x013be9dd, 0xab02e9cd, 0x90049101, 
+    0xf240983d, 0x22004300, 0xf188fa4f, 0x983e9000, 0xf003b240, 0x2002fb31, 0xe00b9025, 0x90252004, 
+    0x780048ba, 0xd0032804, 0x780048b8, 0xd1012805, 0x90242002, 0xe1462500, 0x880048b3, 0xd1102801, 
+    0x103be9dd, 0xab02e9cd, 0x90019104, 0xf240983d, 0xb26a1300, 0xf188fa4f, 0x983e9000, 0xf003b240, 
+    0x2600fb0b, 0xb126e129, 0xd0072e01, 0xd10f2e02, 0x983ce009, 0xf8cd903a, 0xe00aa0e4, 0xa0e8f8cd, 
+    0xb0e4f8cd, 0xf8cde005, 0x983bb0e8, 0xe0009039, 0xbf00e111, 0xe0092400, 0xa92f2010, 0x0014f821, 
+    0x30fff04f, 0xf821a926, 0x1c640014, 0xddf32c10, 0x88004895, 0x2700bb88, 0x2002e036, 0x5107fb00, 
+    0xf930983a, 0x20024011, 0x5107fb00, 0xf9309839, 0x90230011, 0xf850a81e, 0x42a00026, 0xa81bda23, 
+    0x0026f850, 0xdd1e42a0, 0xf930a82f, 0x98231014, 0xda034281, 0xf930a82f, 0xe0000014, 0xb2009823, 
+    0xf821a92f, 0xa8260014, 0x1014f930, 0x42819823, 0xa826dd04, 0x0014f930, 0xe008e001, 0xb2009823, 
+    0xf821a926, 0x1c7f0014, 0xdbc62f80, 0x2700e033, 0x983ae02f, 0x4017f930, 0xf9309839, 0x90230017, 
+    0xf850a81e, 0x42a00026, 0xa81bda22, 0x0026f850, 0xdd1d42a0, 0xf930a82f, 0x98231014, 0xda034281, 
+    0xf930a82f, 0xe0000014, 0xb2009823, 0xf821a92f, 0xa8260014, 0x1014f930, 0x42819823, 0xa826dd03, 
+    0x0014f930, 0x9823e000, 0xa926b200, 0x0014f821, 0x2fff1c7f, 0xa81eddcd, 0x0026f850, 0xe0831c47, 
+    0xf930a82f, 0xa9180017, 0x1026f851, 0xdc394288, 0x1006ebc6, 0x4401a909, 0x560c1e78, 0x70d5eb05, 
+    0xeba51040, 0xb2420040, 0xfa4fb273, 0xa838f188, 0x94009504, 0xf948f7ff, 0x10e0f8bd, 0x44089821, 
+    0x9038b200, 0x00e0f9bd, 0xda02287f, 0x00e0f9bd, 0x207fe000, 0xeb059038, 0x104070d5, 0x0040eba5, 
+    0xb273b242, 0xf188fa4f, 0x94009504, 0x00e0f9bd, 0xf90ff7ff, 0xf830a805, 0x1c400019, 0xa905b200, 
+    0x0019f821, 0xf930a826, 0xa9150017, 0x1026f851, 0xdb384288, 0x1006ebc6, 0x4408a909, 0xeb0557c4, 
+    0x104070d5, 0x0040eba5, 0xb273b242, 0xf188fa4f, 0x9504a838, 0xf7ff9400, 0xf8bdf907, 0x982110e0, 
+    0xb2001a08, 0xf9bd9038, 0x280000e0, 0xf9bddd02, 0xe00000e0, 0x90382000, 0x70d5eb05, 0xeba51040, 
+    0xb2420040, 0xfa4fb273, 0x9504f188, 0xf9bd9400, 0xf7ff00e0, 0xa805f8ce, 0x0019f830, 0xb2001c40, 
+    0xf821a905, 0x1c7f0019, 0xf850a81b, 0x42b80026, 0xaf76f73f, 0x1c70bf00, 0x2e03b2c6, 0xaed3f6ff, 
+    0x44289824, 0x9825b2c5, 0xf6ff4285, 0xf108aeb5, 0xf0000001, 0xf1b808ff, 0xf6ff0f04, 0xf109ae86, 
+    0x98220901, 0xe0134581, 0xd1800520, 0x00045308, 0x00044308, 0x00044b08, 0x00047b08, 0x00048308, 
+    0x0002faf0, 0x000362ae, 0x000361cc, 0x0003626a, 0xae65f6ff, 0xf8c3f7ff, 0xe8bdb03f, 0xe92d8ff0, 
+    0x270141fc, 0xe0352600, 0xe02f2500, 0xe0292400, 0x4632463b, 0xa8014629, 0xf7ff9400, 0x00a0f895, 
+    0x0020f1c0, 0x1004f8bd, 0xb2004408, 0xf9bd9001, 0x287f0004, 0xf9bdda02, 0xe0000004, 0x9001207f, 
+    0x0004f9bd, 0xdb022800, 0x0004f9bd, 0x2000e000, 0x463b9001, 0x46294632, 0xf9bd9400, 0xf7ff0004, 
+    0x1c64f858, 0xddd32c10, 0xb2451c68, 0xdbcd2d04, 0xb2461c70, 0xdbc72e02, 0x81fce8bd, 0x4605b570, 
+    0x462b460e, 0x0291220c, 0xf7ed488b, 0x4633fa81, 0xf2402208, 0x48883100, 0xfa7af7ed, 0x20402100, 
+    0xfd22f7ee, 0xf6402200, 0x488371ff, 0xf7ed1d00, 0xb204fa86, 0x040af3c4, 0x6f80f5b4, 0xf5a4db02, 
+    0xb2046000, 0xbd704620, 0x5ffce92d, 0xf1b94681, 0xd0550f00, 0x11f4f240, 0x0000f44f, 0xfd72f7e6, 
+    0xf7f22003, 0x2200fb80, 0x46082101, 0xfc6af7ff, 0x0800f04f, 0x2001e040, 0x25009000, 0x2400e02e, 
+    0x4621e028, 0xf7ff4628, 0x4682ffb9, 0xb2411ca0, 0xf7ff4628, 0x4606ffb3, 0x0100f1ba, 0x460adb01, 
+    0x424ae000, 0x7f40f5b2, 0x1e30dc07, 0x4602db01, 0x4242e000, 0x7f40f5b2, 0xb2e1dd0a, 0x4642b2e8, 
+    0xfb41f7f2, 0x485d2140, 0xfc4ef7e6, 0x90002000, 0xb2441c60, 0xdbd42c02, 0xb2451c68, 0xdbce2d04, 
+    0xb1009800, 0x2100e00b, 0x3080f44f, 0xfcbcf7ee, 0x003ff108, 0xf880fa0f, 0x7f00f5b8, 0xbf00dbbb, 
+    0x90012000, 0x2001e07a, 0x25009000, 0x2400e068, 0x4621e062, 0xf7ff4628, 0x4682ff71, 0xb2411ca0, 
+    0xf7ff4628, 0x4606ff6b, 0x6f80f51a, 0xf240d102, 0xe00030ff, 0x46824650, 0x6f80f516, 0xf240d102, 
+    0xe00030ff, 0x46064630, 0x0006eb0a, 0x107fb207, 0x0f00f1b9, 0x2f80d00c, 0xf117dc02, 0xda040f80, 
+    0x08e7ea4f, 0x90002000, 0xf04fe00f, 0xe00c0800, 0xdd022f80, 0x0801f04f, 0xf117e007, 0xda020f80, 
+    0x38fff04f, 0xf04fe001, 0xf1b80800, 0xd0210f00, 0xb2e8b2e1, 0xfe7af7f3, 0xfb80fa0f, 0x0008eb0b, 
+    0xfb80fa0f, 0x0f00f1bb, 0x2000da01, 0x4658e000, 0xf5bb4683, 0xdb027f00, 0x10fff240, 0x4658e000, 
+    0xb2e14683, 0x465ab2e8, 0xfabdf7f2, 0x481b2140, 0xfbcaf7e6, 0xb2441c60, 0xdb9a2c02, 0xb2451c68, 
+    0xdb942d04, 0xb1009800, 0x2100e012, 0x3080f44f, 0xfc3af7ee, 0x1c409801, 0x9001b200, 0x0f00f1b9, 
+    0x2108d001, 0x2101e000, 0x42819801, 0xaf7bf73f, 0xf1b9bf00, 0xd0090f00, 0x46112200, 0xf7ff2001, 
+    0x4907fb91, 0x0000f44f, 0xfc3cf7e6, 0x9ffce8bd, 0x70104a04, 0x00004770, 0xd1800514, 0xd003c424, 
+    0xdcba01f5, 0x000384d8, 0x2300b510, 0x211f461a, 0xf7ed483e, 0x2205f984, 0x31e0f240, 0x301a483b, 
+    0xf994f7ed, 0x46234604, 0xf2402205, 0x483731e0, 0xf975f7ed, 0x220a2301, 0x48340299, 0xf96ff7ed, 
+    0x220c2302, 0x48314932, 0xf7ed3020, 0x2304f968, 0x210f2200, 0x3020482d, 0xf961f7ed, 0x22002301, 
+    0x482a210f, 0xf7ed301c, 0x2301f95a, 0x210f2200, 0x301e4826, 0xf953f7ed, 0xb510bd10, 0xf7e64825, 
+    0x4925fb4d, 0x20018008, 0x70084924, 0x78004822, 0x10c0f3c0, 0x70084922, 0x7800481f, 0x1040f3c0, 
+    0x70084920, 0x7800481c, 0x1080f3c0, 0x7008491e, 0x78004819, 0x1080f3c0, 0x7008491c, 0x88004816, 
+    0x20c0f3c0, 0x7008491a, 0x88004813, 0x49190bc0, 0x48197008, 0x28088800, 0x480fd106, 0xf3c07800, 
+    0x491600c0, 0xe0027008, 0x49142000, 0xbd107008, 0x4913b510, 0x30844807, 0xfb16f7e6, 0xffbdf7ff, 
+    0x49102000, 0xf7ff7008, 0xbd10ff7f, 0xd03c8204, 0xfffff000, 0xd03c8034, 0x0003626e, 0x00038470, 
+    0x0003626b, 0x00038488, 0x00038465, 0x00038464, 0x0003626c, 0x0003626d, 0x000361ce, 0x00038492, 
+    0xffffbbb3, 0x00036318, 0x2100b510, 0xf7e648fe, 0x2100faeb, 0x1c8048fc, 0xfae6f7e6, 0x48fa2104, 
+    0xf7e61d00, 0x2100fae1, 0x1d8048f7, 0xfadcf7e6, 0x48f52100, 0xf7e63008, 0x2104fad7, 0x300a48f2, 
+    0xfad2f7e6, 0x48f02100, 0xf7e6300c, 0x2100facd, 0x300e48ed, 0xfac8f7e6, 0x48eb2100, 0xf7e63010, 
+    0x2140fac3, 0x301248e8, 0xfabef7e6, 0x48e62100, 0xf7e63014, 0x2104fab9, 0x301648e3, 0xfab4f7e6, 
+    0x48e12100, 0xf7e63018, 0x2100faaf, 0x301a48de, 0xfaaaf7e6, 0x48dc2104, 0xf7e6301c, 0x48dbfaa5, 
+    0xb9a07800, 0x48d82100, 0xf7e63020, 0x2100fa9d, 0x302248d5, 0xfa98f7e6, 0x48d52100, 0xfa94f7e6, 
+    0x4192f242, 0x301e48d0, 0xfa8ef7e6, 0x2100e01a, 0x302048cd, 0xfa88f7e6, 0x22052301, 0x48ca2120, 
+    0xf7ed3020, 0x2100f87c, 0x302248c7, 0xfa7cf7e6, 0x48c72100, 0xfa78f7e6, 0x4100f240, 0x301e48c2, 
+    0xfa72f7e6, 0x22002301, 0x48c14619, 0xf7ed1e80, 0x2301f866, 0x2102461a, 0x1e8048bd, 0xf85ff7ed, 
+    0x22022301, 0x48ba2104, 0xf7ed1e80, 0x2301f858, 0x21082203, 0x1e8048b6, 0xf851f7ed, 0x22042301, 
+    0x48b32110, 0xf7ed1e80, 0xbd10f84a, 0xf7ffb510, 0x2301ff5b, 0x46192200, 0x1d0048ad, 0xf83ff7ed, 
+    0x22042301, 0x48a82110, 0xf7ed1d80, 0x2301f838, 0x21042202, 0x1d8048a6, 0xf831f7ed, 0x22032301, 
+    0x48a32108, 0xf7ed1d80, 0x2301f82a, 0x21042202, 0x300c489d, 0xf823f7ed, 0x461a2301, 0x489a2102, 
+    0xf7ed300c, 0x2301f81c, 0x21402206, 0x30124896, 0xf815f7ed, 0x22072301, 0x48932180, 0xf7ed3018, 
+    0x2301f80e, 0x21042202, 0x300c4891, 0xf807f7ed, 0x22032301, 0x488e2108, 0xf7ed300c, 0xbd10f800, 
+    0x4604b570, 0x4889460d, 0xb9687800, 0x2200b2a3, 0x48852103, 0xf7ec301e, 0xb2abfff2, 0x210f2200, 
+    0x1d004881, 0xffebf7ec, 0xb510bd70, 0x7800487f, 0x2300b930, 0x2103461a, 0x301e487b, 0xffdff7ec, 
+    0xb570bd10, 0x460d4604, 0x78004878, 0xb2a3b968, 0x21182203, 0x301e4874, 0xffd1f7ec, 0x2200b2ab, 
+    0x4871210f, 0xf7ec300a, 0xbd70ffca, 0x486fb510, 0xb9307800, 0x22032300, 0x486b2118, 0xf7ec301e, 
+    0xbd10ffbe, 0x4604b570, 0x4868460d, 0xb9a07800, 0x2206b2a3, 0x486421c0, 0xf7ec301e, 0xb2abffb0, 
+    0x210f2200, 0x30104860, 0xffa9f7ec, 0x22072301, 0x485f2180, 0xf7ec1e80, 0xbd70ffa2, 0x485bb510, 
+    0xb9307800, 0x22062300, 0x485721c0, 0xf7ec301e, 0xbd10ff96, 0x4604b570, 0x2301460d, 0x21402206, 
+    0x30204851, 0xff8bf7ec, 0xb510bd70, 0x22062300, 0x484d2140, 0xf7ec3020, 0xbd10ff82, 0x4604b570, 
+    0x484a460d, 0xb9687800, 0x220cb2a3, 0x48460291, 0xf7ec301e, 0xb2abff74, 0x210f2200, 0x301c4842, 
+    0xff6df7ec, 0xb510bd70, 0x78004840, 0x2300b930, 0x0291220c, 0x301e483c, 0xff61f7ec, 0xb510bd10, 
+    0xff14f7ff, 0x20012100, 0xff5af7ff, 0x20012100, 0xff77f7ff, 0x20012100, 0xff94f7ff, 0x20012100, 
+    0xffb8f7ff, 0x20012100, 0xffc8f7ff, 0xb510bd10, 0x22002301, 0x482e4619, 0xff41f7ec, 0x20022100, 
+    0xff3ef7ff, 0xb510bd10, 0x461a2300, 0x48282101, 0xff35f7ec, 0xff49f7ff, 0xb510bd10, 0x22042301, 
+    0x48212110, 0xf7ec3020, 0x2100ff2a, 0xf7ff2001, 0xbd10ff48, 0x4604b510, 0xd11a2c03, 0x22022300, 
+    0x481b210c, 0xff1bf7ec, 0x22072301, 0x48162180, 0xf7ec3020, 0x2300ff14, 0x21102204, 0x30204812, 
+    0xff0df7ec, 0xff42f7ff, 0x20022100, 0xff86f7ff, 0x2c05e041, 0x2302d123, 0x210c461a, 0xf7ec480c, 
+    0x2300fefe, 0x21802207, 0x30204807, 0xfef7f7ec, 0x22042300, 0x48042110, 0xf7ec3020, 0x2100fef0, 
+    0xf7ff2002, 0xe005ff0e, 0xd0035058, 0x0003626c, 0xd00351da, 0x20022100, 0xff60f7ff, 0x2c04e01b, 
+    0x2301d119, 0x210c2202, 0xf7ec488b, 0x2300fed8, 0x21802207, 0xf7ec4889, 0x2300fed2, 0x21102204, 
+    0xf7ec4886, 0x2100fecc, 0xf7ff2002, 0x2100feea, 0xf7ff2002, 0x2100ff43, 0xf7ff2002, 0xbd10ff2b, 
+    0xf7ffb510, 0xf7fffed2, 0xf7fffef1, 0xf7ffff17, 0xf7ffff2c, 0x2300ff48, 0x2101461a, 0xf7ec4876, 
+    0x2300feae, 0x210c2202, 0xf7ec4873, 0x2300fea8, 0x21802207, 0xf7ec4871, 0x2300fea2, 0x21102204, 
+    0xf7ec486e, 0xbd10fe9c, 0x4604b510, 0x7800486c, 0x2300b9e0, 0x2101461a, 0x1e804867, 0xfe8ff7ec, 
+    0x22012300, 0x48642102, 0xf7ec1e80, 0x2300fe88, 0x21042202, 0x1e804860, 0xfe81f7ec, 0x22042300, 
+    0x485d2110, 0xf7ec1e80, 0xe043fe7a, 0x2c01b124, 0x2c02d00f, 0xe019d13c, 0x22042300, 0x48572110, 
+    0xfe6df7ec, 0x22032300, 0x48542108, 0xfe67f7ec, 0x2301e02f, 0x21102204, 0xf7ec4850, 0x2300fe60, 
+    0x21082203, 0xf7ec484d, 0xe022fe5a, 0x22042301, 0x484a2110, 0xfe53f7ec, 0x22032301, 0x48472108, 
+    0xfe4df7ec, 0xf244220e, 0x48460100, 0xfe5ef7ec, 0xd1062801, 0x22002301, 0x483f4619, 0xfe3ff7ec, 
+    0x2300e005, 0x2101461a, 0xf7ec483b, 0xe000fe38, 0xbf00bf00, 0xb510bd10, 0x78004839, 0x2301b9e0, 
+    0x46192200, 0x1e804834, 0xfe29f7ec, 0x461a2301, 0x48312102, 0xf7ec1e80, 0x2301fe22, 0x21042202, 
+    0x1e80482d, 0xfe1bf7ec, 0x22042301, 0x482a2110, 0xf7ec1e80, 0xe00bfe14, 0x22042300, 0x48272110, 
+    0xfe0df7ec, 0x22032300, 0x48242108, 0xfe07f7ec, 0xfe7bf7ff, 0x461a2300, 0x481f2101, 0xfdfff7ec, 
+    0xb510bd10, 0x20022100, 0xfe64f7ff, 0xb510bd10, 0xfe6bf7ff, 0xb510bd10, 0x7800481b, 0xd1072801, 
+    0x22022300, 0x48142104, 0xf7ec1e80, 0xe003fde8, 0x20012100, 0xfe26f7ff, 0xb510bd10, 0xb2a34604, 
+    0x21012200, 0x1e80480c, 0xfdd9f7ec, 0x2201b2a3, 0x48092102, 0xf7ec1e80, 0xb2a3fdd2, 0x21042202, 
+    0x1e804805, 0xfdcbf7ec, 0x2204b2a3, 0x48022110, 0xf7ec1e80, 0xbd10fdc4, 0xd00351da, 0xd0035078, 
+    0x0003626c, 0xd28fffd4, 0x00038492, 0x4604b570, 0x0508f242, 0xea402020, 0xf0404005, 0xea400018, 
+    0x48f80144, 0xffa5f7e5, 0x48f62100, 0xf7e53084, 0xf44fffa0, 0xea402040, 0xf4403084, 0x1d41609c, 
+    0x307c48f0, 0xff95f7e5, 0x20102101, 0xf81cf7ee, 0x2040f44f, 0x3084ea40, 0x50a7f440, 0x48e91d41, 
+    0xf7e5307c, 0x2001ff86, 0xb510bd70, 0x48e52100, 0xff7ff7e5, 0xfba0f002, 0xb530bd10, 0x4605b087, 
+    0xf980f002, 0x2000b910, 0xbd30b007, 0x308048dd, 0xff6af7e5, 0x040bf3c0, 0xda022c53, 0x34adf604, 
+    0x3c53e000, 0xf3c400a4, 0x48d6010d, 0xf7e51d00, 0x2001ff60, 0xe9cd2300, 0x90043002, 0x93019300, 
+    0x462b9005, 0x323c4acf, 0x5130f240, 0xff9af7ec, 0xe7d92001, 0x4ff1e92d, 0xf8dfb082, 0x9802932c, 
+    0x49cab920, 0x0000f991, 0xff90f7ff, 0x76a6f509, 0x77a6f506, 0xf7ff4638, 0xf7ffffc0, 0x46b2ffb6, 
+    0x9000f8cd, 0xe00b2400, 0xf84acf01, 0xcf020b04, 0x60019800, 0x1d009800, 0x37089000, 0xb2041c60, 
+    0xdbf12c53, 0x28019802, 0x49b8d104, 0x0000f991, 0xff6cf7ff, 0x24002500, 0x0801f04f, 0xf836e00b, 
+    0xb1111b02, 0x0008ea45, 0x1c60b285, 0xea4fb204, 0xfa0f0048, 0x2c10f880, 0xf109dbf1, 0x24000920, 
+    0x2000e043, 0x550849aa, 0xe0354680, 0x010ff005, 0xf85048a8, 0x3840b021, 0x1103f3c5, 0x0021f850, 
+    0x48a44483, 0xf3c53880, 0xf8502103, 0x44830021, 0x49a00b28, 0xf85139c0, 0x44830020, 0x1b02f939, 
+    0x00cbeb0b, 0xda014281, 0xe0002001, 0x90012000, 0x1b02f816, 0x40489801, 0xf008fa00, 0x5d094994, 
+    0x49934308, 0x10695508, 0xea419801, 0xb28530c0, 0x0001f108, 0xf880fa0f, 0x0f08f1b8, 0x488cdbc6, 
+    0x498d5d00, 0x1c605508, 0x2c10b204, 0xe8bddbb9, 0xb5708ffe, 0x4605b086, 0x20002600, 0x90004983, 
+    0x0000f991, 0x737af643, 0x21012200, 0xfa0ef002, 0x21802000, 0xe9cd2201, 0x92000201, 0x1003e9cd, 
+    0xf990487a, 0x23052000, 0x46182107, 0xf9baf002, 0xf8a8f002, 0xe002b900, 0xf8bcf002, 0xb98e4606, 
+    0xf240b185, 0xf04f11f4, 0xf7e56080, 0xf246ff8b, 0xf04f6166, 0xf7e56080, 0x4970ff35, 0x6080f04f, 
+    0xff30f7e5, 0xfaa8f002, 0xe0072400, 0xf0024620, 0x4967f8a8, 0x0024f841, 0xb2441c60, 0xdbf52c04, 
+    0xb0064630, 0xe92dbd70, 0xb09f4ff3, 0x0000f640, 0x485d901e, 0x4601901d, 0xeb01981e, 0x901c0040, 
+    0x8800485f, 0x0040389a, 0x9010b200, 0x900e2000, 0x46824681, 0x24109006, 0x1e401e47, 0x48539005, 
+    0x0000f990, 0x22029011, 0x101ee9dd, 0x98104401, 0x1f801a08, 0x17c11b00, 0xeb009004, 0x13814091, 
+    0xeba09804, 0xb2003081, 0x991e2305, 0x1300e9cd, 0x0202e9cd, 0x21052207, 0x9b114843, 0xfa64f002, 
+    0xf9904848, 0x901b0000, 0x900f981b, 0x90192000, 0x9017901a, 0xbf009018, 0x1e40bf00, 0x25009005, 
+    0x2000e004, 0x5548493a, 0xb2051c68, 0xdbf82d10, 0xb2064260, 0x9810e176, 0x19014430, 0xf830981c, 
+    0x00400011, 0xb2001e40, 0x980f9007, 0x19014430, 0xf830981d, 0x980f2011, 0x44204430, 0x991d1e40, 
+    0x0010f831, 0x00c01a10, 0x9008b200, 0x8020f8dd, 0xe01b2501, 0x38c04827, 0x1185eb00, 0x981a00aa, 
+    0xf00040d0, 0xf831000f, 0x48221020, 0xeb0038c0, 0x00ab1285, 0x40d89819, 0x000ff000, 0x0020f832, 
+    0x44401a08, 0xf880fa0f, 0xb2051c68, 0xdbe12d03, 0x981a46c3, 0x000ff000, 0x39c04916, 0x1020f831, 
+    0xf0009819, 0x4a13000f, 0xf8323ac0, 0x1a080020, 0xfa0f4440, 0x9818f880, 0x000ff000, 0xf8314611, 
+    0x98171020, 0x000ff000, 0x0020f832, 0x44581a08, 0xfb80fa0f, 0xd91745d1, 0x090aeba9, 0x0a00f04f, 
+    0x0000e016, 0xd1800304, 0x00054000, 0x00036240, 0x00038fd0, 0x00038f90, 0x00044078, 0xdcba01f5, 
+    0x0003622a, 0x00036238, 0x0a09ebaa, 0x0900f04f, 0x880048fe, 0x43489907, 0x9009b200, 0x9008fb08, 
+    0x9809900d, 0x0100eba8, 0x0000eba8, 0x9000fb01, 0x9809900c, 0x0100ebab, 0x0000ebab, 0xa000fb01, 
+    0xfb0b900a, 0x910ba10b, 0x9016981a, 0x90159819, 0x90149818, 0x90139817, 0x980d990b, 0xd2084288, 
+    0x9034f8dd, 0x00409816, 0x9815901a, 0x90190040, 0xf8dde007, 0x9814902c, 0x901a0040, 0x00409813, 
+    0x990c9019, 0x4288980a, 0xf8ddd216, 0x9807a028, 0xd1012801, 0xe0002101, 0x98142100, 0x0040ea41, 
+    0x98079018, 0xb9081c40, 0xe0002101, 0x98132100, 0x0040ea41, 0xe0159017, 0xa030f8dd, 0x28019807, 
+    0x2101d101, 0x2100e000, 0xea419816, 0x90180040, 0x1c409807, 0x2101b908, 0x2100e000, 0xea419815, 
+    0x90170040, 0xd21c45d1, 0x40e1991a, 0x0101f001, 0x9919b921, 0xf00140e1, 0xb1490101, 0x40e1991a, 
+    0x0101f001, 0x2101b109, 0xf04fe003, 0xe00031ff, 0x1e082100, 0x4601db01, 0x4241e000, 0x9112b249, 
+    0x9918e01b, 0xf00140e1, 0xb9210101, 0x40e19917, 0x0101f001, 0x9918b149, 0xf00140e1, 0xb1090101, 
+    0xe0032101, 0x31fff04f, 0x2100e000, 0xdb011e08, 0xe0004601, 0xb2494241, 0x991f9112, 0x1b084431, 
+    0xeb0017c1, 0x12096111, 0x2201eba0, 0x428a990e, 0x9812d105, 0x2001b908, 0x2000e000, 0x42a69012, 
+    0x9806db3e, 0x90060840, 0xb1089812, 0xe0002101, 0x98062100, 0x70c1ea40, 0x98059006, 0xb9d81c40, 
+    0x71bbf24a, 0x42889806, 0x991fd116, 0x4180f501, 0x391f4431, 0x17c11b08, 0x4191eb00, 0xeba01389, 
+    0xb2093181, 0x271f9105, 0x499120bb, 0x20a77008, 0x20007048, 0x70c87088, 0xb1881c78, 0xda0d2f80, 
+    0xeb0717f9, 0x10c97151, 0x01c1eba7, 0xd1052907, 0x0e009806, 0xeb014986, 0x700801e7, 0xb2071c78, 
+    0xb2061c70, 0x44209820, 0x42b03020, 0x2f80dd02, 0xae81f6ff, 0xb0219805, 0x8ff0e8bd, 0x4ff8e92d, 
+    0x36fff04f, 0x91ecf8df, 0x6780f509, 0x20004d7a, 0x487a9000, 0x1000f990, 0x2200464b, 0xf7eb2001, 
+    0xf8b9ff44, 0x80380000, 0x0a00f04f, 0xe01f2401, 0x1014f839, 0xf8391e60, 0x1a080010, 0xf827b200, 
+    0x1c710014, 0xf937b141, 0x28000014, 0x4601db01, 0x4241e000, 0xdd094541, 0xf9374626, 0x28000014, 
+    0x4601db01, 0x4241e000, 0xf881fa0f, 0xb2041c60, 0xdbdd2c80, 0xda002e03, 0xea4f2603, 0x1ef108e8, 
+    0x0011f937, 0xdb012800, 0xe0004601, 0x45414241, 0x1ef0dd03, 0xfa80fa4f, 0x1eb1e01d, 0x0011f937, 
+    0xdb012800, 0xe0004601, 0x45414241, 0x1eb0dd03, 0xfa80fa4f, 0x1e71e00f, 0x0011f937, 0xdb012800, 
+    0xe0004601, 0x45414241, 0x1e70dd03, 0xfa80fa4f, 0xfa4fe001, 0x2400fa86, 0xeb04e007, 0xf837000a, 
+    0xf8250010, 0x1c600014, 0x2c11b204, 0x2400dbf5, 0x2004e1e6, 0x0084eb00, 0x0010f935, 0xeb012103, 
+    0xf9350184, 0x44081011, 0xeb012102, 0xf9350184, 0x44081011, 0xeb012101, 0xf9350184, 0x44081011, 
+    0x00c0eb00, 0xeb014936, 0x60081184, 0xeb002004, 0xf9350084, 0x21030010, 0x0184eb01, 0x1011f935, 
+    0x21024408, 0x0184eb01, 0x1011f935, 0x21014408, 0x0184eb01, 0x1011f935, 0xeb001a40, 0x492800c0, 
+    0x1184eb01, 0x20046048, 0x0084eb00, 0x0010f935, 0xeb012103, 0xf9350184, 0x44081011, 0xeb012102, 
+    0xf9350184, 0x1a401011, 0xeb012101, 0xf9350184, 0x44081011, 0x00c0eb00, 0xeb014919, 0x60881184, 
+    0xeb002004, 0xf9350084, 0x21030010, 0x0184eb01, 0x1011f935, 0x21024408, 0x0184eb01, 0x1011f935, 
+    0x21011a40, 0x0184eb01, 0x1011f935, 0xeb001a40, 0x490b00c0, 0x1184eb01, 0x200460c8, 0x0084eb00, 
+    0x0010f935, 0xeb012103, 0xe00b0184, 0x0003623a, 0x00038fd0, 0x0004a648, 0x0004b048, 0x00036240, 
+    0x00038ed0, 0x1011f935, 0x21021a40, 0x0184eb01, 0x1011f935, 0x21014408, 0x0184eb01, 0x1011f935, 
+    0xeb004408, 0x49e000c0, 0x1184eb01, 0x20046108, 0x0084eb00, 0x0010f935, 0xeb012103, 0xf9350184, 
+    0x1a401011, 0xeb012102, 0xf9350184, 0x44081011, 0xeb012101, 0xf9350184, 0x1a401011, 0x00c0eb00, 
+    0xeb0149d1, 0x61481184, 0xeb002004, 0xf9350084, 0x21030010, 0x0184eb01, 0x1011f935, 0x21021a40, 
+    0x0184eb01, 0x1011f935, 0x21011a40, 0x0184eb01, 0x1011f935, 0xeb004408, 0x49c300c0, 0x1184eb01, 
+    0x20046188, 0x0084eb00, 0x0010f935, 0xeb012103, 0xf9350184, 0x1a401011, 0xeb012102, 0xf9350184, 
+    0x1a401011, 0xeb012101, 0xf9350184, 0x1a401011, 0x00c0eb00, 0xeb0149b4, 0x61c81184, 0xeb002004, 
+    0xf9350084, 0x42400010, 0xeb012103, 0xf9350184, 0x44081011, 0xeb012102, 0xf9350184, 0x44081011, 
+    0xeb012101, 0xf9350184, 0x44081011, 0x00c0eb00, 0xeb0149a5, 0x62081184, 0xeb002004, 0xf9350084, 
+    0x42400010, 0xeb012103, 0xf9350184, 0x44081011, 0xeb012102, 0xf9350184, 0x44081011, 0xeb012101, 
+    0xf9350184, 0x1a401011, 0x00c0eb00, 0xeb014996, 0x62481184, 0xeb002004, 0xf9350084, 0x42400010, 
+    0xeb012103, 0xf9350184, 0x44081011, 0xeb012102, 0xf9350184, 0x1a401011, 0xeb012101, 0xf9350184, 
+    0x44081011, 0x00c0eb00, 0xeb014987, 0x62881184, 0xeb002004, 0xf9350084, 0x42400010, 0xeb012103, 
+    0xf9350184, 0x44081011, 0xeb012102, 0xf9350184, 0x1a401011, 0xeb012101, 0xf9350184, 0x1a401011, 
+    0x00c0eb00, 0xeb014978, 0x62c81184, 0xeb002004, 0xf9350084, 0x42400010, 0xeb012103, 0xf9350184, 
+    0x1a401011, 0xeb012102, 0xf9350184, 0x44081011, 0xeb012101, 0xf9350184, 0x44081011, 0x00c0eb00, 
+    0xeb014969, 0x63081184, 0xeb002004, 0xf9350084, 0x42400010, 0xeb012103, 0xf9350184, 0x1a401011, 
+    0xeb012102, 0xf9350184, 0x44081011, 0xeb012101, 0xf9350184, 0x1a401011, 0x00c0eb00, 0xeb01495a, 
+    0x63481184, 0xeb002004, 0xf9350084, 0x42400010, 0xeb012103, 0xf9350184, 0x1a401011, 0xeb012102, 
+    0xf9350184, 0x1a401011, 0xeb012101, 0xf9350184, 0x44081011, 0x00c0eb00, 0xeb01494b, 0x63881184, 
+    0xeb002004, 0xf9350084, 0x42400010, 0xeb012103, 0xf9350184, 0x1a401011, 0xeb012102, 0xf9350184, 
+    0x1a401011, 0xeb012101, 0xf9350184, 0x1a401011, 0x00c0eb00, 0xeb01493c, 0x63c81184, 0xb2041c60, 
+    0xf6ff2c04, 0x8828ae16, 0x00c0eb00, 0xb2000040, 0x80084936, 0xf8804836, 0xe8bda000, 0xb5108ff8, 
+    0xfd8cf7ff, 0xf7ed2002, 0x4604fb2b, 0x1100f240, 0x7060f643, 0xfba7f7ff, 0xf7ed2002, 0x1a24fb21, 
+    0xf9b0482c, 0xfbb40000, 0x492bf0f0, 0xbd106008, 0x41f0e92d, 0x2600f240, 0xfd70f7ff, 0x35fff04f, 
+    0x0800f04f, 0x4780f5c6, 0x4631e034, 0xf7ff4638, 0x4604fb8a, 0xb3081c60, 0x507ef5a4, 0x0fe8b205, 
+    0x3080eb05, 0xf240b205, 0xf04f11f4, 0xf7e56080, 0x491afae9, 0x6080f04f, 0xfa94f7e5, 0xf04f4918, 
+    0xf7e56080, 0x4629fa8f, 0x6080f04f, 0xfa8af7e5, 0xf04f4914, 0xf7e56080, 0xe011fa85, 0x0101f108, 
+    0xf881fa0f, 0x17c119b8, 0x4191eb00, 0xeba01389, 0xb20f3181, 0x0000f248, 0xf0f6fb90, 0xdcc44540, 
+    0x4628bf00, 0x81f0e8bd, 0x00038ed0, 0x0003623a, 0x00036238, 0x000384a8, 0x0003623c, 0xa5a55a5a, 
+    0xdde50000, 0xdcba01f5, 0x4afb4601, 0x47705c50, 0x41f0e92d, 0xf04f4606, 0x48f80800, 0xb1187800, 
+    0x780048f6, 0xd1012802, 0xe000200e, 0x46072007, 0x220fb2b3, 0x48f349f2, 0xffa1f7eb, 0x22002380, 
+    0x31fff240, 0xf7eb48ef, 0x2306ff9a, 0x21ff2200, 0x1c8048ec, 0xff93f7eb, 0x73f8f641, 0x217f2200, 
+    0x1d0048e8, 0xff8bf7eb, 0x48e649e5, 0xf7e51e80, 0x49e3f98b, 0x48e33180, 0xf7e51e80, 0x2500f985, 
+    0x48e1e031, 0x28037800, 0x2204d10b, 0x48dd21f0, 0xf7eb300e, 0x4038ff8b, 0xd12342b8, 0x0801f04f, 
+    0x2204e024, 0x48d721f0, 0xf7eb300e, 0xf000ff7f, 0x280f000f, 0x2200d116, 0x48d2210f, 0xf7eb300e, 
+    0xb204ff75, 0x0001f004, 0x700849d0, 0x0040f3c4, 0xf3c47048, 0x70880080, 0x00c0f3c4, 0xf04f70c8, 
+    0xe0030801, 0xf5b51c6d, 0xdbca4f00, 0x2301bf00, 0x0299220a, 0x1e8048c3, 0xff41f7eb, 0x220a2300, 
+    0x4100f240, 0x1e8048bf, 0xff39f7eb, 0xe8bd4640, 0xb57081f0, 0xf6432200, 0x48ba71ff, 0xf7eb3030, 
+    0xb204ff45, 0x0001f004, 0x2301b180, 0x02592209, 0x1e8048b4, 0xff23f7eb, 0x22092300, 0x2100f240, 
+    0x1e8048b0, 0xff1bf7eb, 0xb2041e60, 0xb2044620, 0xe00e2500, 0x22082301, 0x48aa0151, 0xf7eb1e80, 
+    0x2300ff0e, 0x01512208, 0x1e8048a6, 0xff07f7eb, 0x2d181c6d, 0xf104dbee, 0xf3c0005a, 0x1070060d, 
+    0xfca1f7ee, 0xbd704620, 0x4ff0e92d, 0x4682b085, 0x7800489a, 0x4899b118, 0x28027800, 0x200ed101, 
+    0x2007e000, 0x46509000, 0xff32f7ff, 0xb93d4605, 0x68004897, 0xf240b120, 0x1e4831a4, 0xf98cf7ed, 
+    0xf9904894, 0xb2830000, 0xf246220d, 0x488d0100, 0xf7eb1e80, 0x488ffed4, 0x0001f990, 0x220bb283, 
+    0x0100f641, 0x1e804887, 0xfec9f7eb, 0x22062300, 0x48842140, 0xf7eb1e80, 0x2301fec2, 0x21402206, 
+    0x1e804880, 0xfebbf7eb, 0x22062300, 0x487d2140, 0xf7eb1e80, 0x2101feb4, 0xf7ed02c8, 0x2208f935, 
+    0x48780151, 0xf7eb300e, 0x2800fec1, 0x4879d149, 0x0001f990, 0x220db283, 0x0100f246, 0x1e804871, 
+    0xfe9df7eb, 0xf9904873, 0xb2830000, 0xf641220b, 0x486c0100, 0xf7eb1e80, 0x2300fe92, 0x21402206, 
+    0x1e804868, 0xfe8bf7eb, 0x22062301, 0x48652140, 0xf7eb1e80, 0x2300fe84, 0x21402206, 0x1e804861, 
+    0xfe7df7eb, 0x02c82101, 0xf8fef7ed, 0x01512208, 0x300e485c, 0xfe8af7eb, 0x485eb138, 0x49567840, 
+    0x485c7008, 0x70487800, 0x4859e012, 0xb1206800, 0x31a6f240, 0xf7ed1e48, 0x2000f90f, 0xe8bdb005, 
+    0x48548ff0, 0x494c7800, 0x48527008, 0x70487840, 0xfbf0f7ee, 0x0740f1a0, 0x7800484b, 0xd1742800, 
+    0xf990484c, 0xb2830002, 0xf246220d, 0x48450100, 0xf7eb1e80, 0x4847fe44, 0x0003f990, 0x220bb283, 
+    0x0100f641, 0x1e80483f, 0xfe39f7eb, 0x22062300, 0x483c2140, 0xf7eb1e80, 0x2301fe32, 0x21402206, 
+    0x1e804838, 0xfe2bf7eb, 0x22062300, 0x48352140, 0xf7eb1e80, 0x2101fe24, 0xf7ed02c8, 0x2208f8a5, 
+    0x48300151, 0xf7eb300e, 0x2800fe31, 0x4831d148, 0x0003f990, 0x220db283, 0x0100f246, 0x1e804829, 
+    0xfe0df7eb, 0xf990482b, 0xb2830002, 0xf641220b, 0x48240100, 0xf7eb1e80, 0x2300fe02, 0x21402206, 
+    0x1e804820, 0xfdfbf7eb, 0x22062301, 0x481d2140, 0xf7eb1e80, 0x2300fdf4, 0x21402206, 0x1e804819, 
+    0xfdedf7eb, 0x02c82101, 0xf86ef7ed, 0x01512208, 0x300e4814, 0xfdfaf7eb, 0x4816b140, 0x490e78c0, 
+    0x48147088, 0x70c87880, 0xe025e011, 0x68004810, 0xf240b120, 0x1e4831a8, 0xf87ef7ed, 0xe76d2000, 
+    0x7880480c, 0x70884904, 0x78c0480a, 0xf7ee70c8, 0xf1a0fb61, 0xe0180940, 0x00036240, 0x000361d8, 
+    0xffff8000, 0xd0035094, 0x0003625c, 0x00036244, 0x00052f80, 0x00036254, 0x788048fc, 0x708849fc, 
+    0x78c048fa, 0xf04f70c8, 0x48f90900, 0x0001f990, 0x220db283, 0x0100f246, 0xf7eb48f6, 0x48f4fda0, 
+    0x0002f990, 0x220bb283, 0x0100f641, 0xf7eb48f1, 0x2300fd96, 0x21402206, 0xf7eb48ee, 0x2301fd90, 
+    0x21402206, 0xf7eb48eb, 0x2300fd8a, 0x21402206, 0xf7eb48e8, 0x2101fd84, 0xf7ed02c8, 0x2208f805, 
+    0x48e40151, 0xf7eb3010, 0xb938fd91, 0x680048e2, 0xf240b120, 0x1e4831aa, 0xf81ef7ed, 0xfb0af7ee, 
+    0x0840f1a0, 0xf99048da, 0xb2830000, 0xf246220d, 0x48d80100, 0xfd63f7eb, 0x22052300, 0x48d52120, 
+    0xfd5df7eb, 0x22052301, 0x48d22120, 0xfd57f7eb, 0x24002500, 0x220fe009, 0x48ce49d0, 0xf7eb3032, 
+    0xb108fd65, 0xe0032501, 0xf5b41c64, 0xdbf24f00, 0x2d00bf00, 0xfa1fd17d, 0x220ff38a, 0x48c549c7, 
+    0xf7eb1c80, 0x2380fd3c, 0xf2402200, 0x48c131ff, 0xf7eb1c80, 0x2306fd34, 0x21ff2200, 0x1d0048bd, 
+    0xfd2df7eb, 0x461a2300, 0x48ba210f, 0xfd27f7eb, 0x22072300, 0x48b72180, 0xfd21f7eb, 0x22072301, 
+    0x48b42180, 0xfd1bf7eb, 0x48b1bf00, 0x20017801, 0xb2064088, 0xe01c2400, 0x780048b1, 0xd10c2803, 
+    0x21f02204, 0x301048ab, 0xfd20f7eb, 0x40089900, 0x42b04030, 0x2501d10c, 0x2204e00e, 0x48a521f0, 
+    0xf7eb3010, 0x4030fd13, 0xd10142b0, 0xe0032501, 0xf5b41c64, 0xdbdf4f00, 0xb325bf00, 0x220a2301, 
+    0x489c0299, 0xfcebf7eb, 0x220a2300, 0x4100f240, 0xf7eb4898, 0x2500fce4, 0x22052300, 0x48952120, 
+    0xfcddf7eb, 0x22052301, 0x48922120, 0xfcd7f7eb, 0xe00a2400, 0x4991220f, 0x3032488e, 0xfce6f7eb, 
+    0x2501b110, 0xe004e004, 0xf5b41c64, 0xdbf14f00, 0xbbe5bf00, 0x68004888, 0xf240b128, 0x1e4831ac, 
+    0xff6af7ec, 0xf240e038, 0xf44f11f4, 0xf7e40000, 0x487effa9, 0x060078c0, 0xf9924a7c, 0xea402002, 
+    0x4a7a4002, 0x2001f992, 0x2002ea40, 0xf9924a77, 0xea402000, 0xf44f0102, 0xf7e40000, 0x4874ff43, 
+    0x060078c0, 0xf9924a72, 0xea402002, 0x4a704002, 0x2001f992, 0x2002ea40, 0xf9924a6d, 0xea402000, 
+    0xf44f0102, 0xf7e40000, 0x496eff2d, 0xe005e000, 0x0000f44f, 0xff26f7e4, 0xe61f2000, 0xfd49f7ff, 
+    0xf2424683, 0xf7e400c0, 0x2000ff91, 0x97029001, 0x0008eb07, 0xeb079003, 0x44480008, 0xe9dd9004, 
+    0x44080101, 0x44089903, 0x44089904, 0x90011080, 0xf0009801, 0x44080101, 0xf2429001, 0xf7e400c0, 
+    0xf240ff75, 0xf7ee102b, 0x2074fa15, 0xfe18f7ee, 0x220f2301, 0x484f4951, 0xfc51f7eb, 0x0080f10b, 
+    0x000df3c0, 0xf1ab9001, 0xfa0f001c, 0x2000fb80, 0xf9914947, 0x4a4c1000, 0x20015450, 0xf9914944, 
+    0x54501001, 0x49422002, 0x1002f991, 0x20035450, 0xf991493f, 0x54501003, 0xf99c4694, 0xf99c3003, 
+    0xf99c2002, 0xf99c1001, 0xf7ee0000, 0xf8dffb65, 0xf99cc0e0, 0xf99c3003, 0xf99c2002, 0xf99c1001, 
+    0xf7f20000, 0x4838f949, 0x0003f990, 0x56084937, 0x220bb283, 0x0100f640, 0x3878482e, 0xfc0ff7eb, 
+    0xf9904831, 0x49310002, 0xb2835608, 0xf240220a, 0x48284100, 0xf7eb3878, 0x482bfc02, 0x0001f990, 
+    0x5608492a, 0x2209b283, 0x2100f240, 0x38784821, 0xfbf5f7eb, 0xf9904824, 0x49240000, 0xb2835608, 
+    0x01512208, 0x3878481b, 0xfbe9f7eb, 0xf990481e, 0x49160000, 0x1000f991, 0xd00f4288, 0xf990481a, 
+    0x49120002, 0x1002f991, 0xd0074288, 0x22062300, 0x481021c0, 0xf7eb3878, 0xe046fbd2, 0xf9904812, 
+    0x490a0000, 0x1000f991, 0xd1214288, 0xf990480e, 0x49060002, 0x1002f991, 0xd0194288, 0x22062301, 
+    0x480421c0, 0xf7eb3878, 0xe02efbba, 0x00036254, 0x00036240, 0xd0035092, 0x00052f80, 0xffff8000, 
+    0x0003625c, 0xdcba01f5, 0x00036258, 0x00036244, 0xf99048fb, 0x49fb0000, 0x1000f991, 0xd00e4288, 
+    0xf99048f7, 0x49f70002, 0x1002f991, 0xd1064288, 0x22062302, 0x48f421c0, 0xfb91f7eb, 0x2303e005, 
+    0x21c02206, 0xf7eb48f0, 0xf64ffb8a, 0x980271ff, 0x0340ea01, 0xf6472208, 0x48eb7100, 0xf7eb1c80, 
+    0xf64ffb7e, 0x980371ff, 0x0340ea01, 0x217f2200, 0x1d0048e5, 0xfb73f7eb, 0x71fff64f, 0xea019804, 
+    0x22080340, 0x7100f647, 0x1d0048df, 0xfb67f7eb, 0xf99048db, 0x49dd0000, 0xf2406008, 0xf44f1104, 
+    0xf7e40000, 0x48dafe4f, 0x06007800, 0xf9924ad8, 0xea402001, 0x4ad64002, 0x2002f992, 0x2002ea40, 
+    0xf9924ad3, 0xea402003, 0xf44f0102, 0xf7e40000, 0x2100fde9, 0x0000f44f, 0xfde4f7e4, 0xf44f2100, 
+    0xf7e40000, 0xe9ddfddf, 0xf3622001, 0x4601401f, 0x0000f44f, 0xfdd6f7e4, 0x2003e9dd, 0x401ff362, 
+    0xf44f4601, 0xf7e40000, 0x2001fdcd, 0xe92de4c6, 0x460447f0, 0x4698460d, 0x0f00f1b8, 0xb112d006, 
+    0x48bd49bc, 0x49bde008, 0xe00548bd, 0x49bdb112, 0xe00148bd, 0x48be49bd, 0xe000f8d4, 0x9004f894, 
+    0xf102b91a, 0xfa0f0a01, 0x2600f28a, 0xf04fe030, 0x27000c00, 0xe0162300, 0xfa03fa2e, 0x0a01f00a, 
+    0x0f00f1ba, 0xf1c3d00b, 0xf8110a20, 0xea8aa00a, 0xf1c30c0c, 0xf8500a20, 0xea8aa02a, 0xf1030707, 
+    0xfa0f0a01, 0x2b20f38a, 0xf009dbe6, 0xf1ba0a01, 0xd0070f00, 0xa000f891, 0x0c0cea8a, 0xa000f8d0, 
+    0x0707ea8a, 0x46be46e1, 0x0a01f106, 0xf68afa0f, 0xdbcc4296, 0x9004f8c5, 0xe000f8c5, 0x87f0e8bd, 
+    0x47fce92d, 0x460e4680, 0xb2702501, 0x70084999, 0xfd0cf7e4, 0x48984604, 0x28037800, 0x488ad114, 
+    0xf7e4309e, 0x9001fcbb, 0x30a04887, 0xfcb6f7e4, 0x9000b280, 0x30a24884, 0x9000f8dd, 0xfcaef7e4, 
+    0x401ff369, 0xe0459000, 0x7800488b, 0xd1142802, 0x3098487d, 0xfca2f7e4, 0x487b9001, 0xf7e4309a, 
+    0xb280fc9d, 0x48789000, 0xf8dd309c, 0xf7e49000, 0xf369fc95, 0x9000401f, 0x487fe02c, 0x28017800, 
+    0x4871d114, 0xf7e43092, 0x9001fc89, 0x3094486e, 0xfc84f7e4, 0x9000b280, 0x3096486b, 0x9000f8dd, 
+    0xfc7cf7e4, 0x401ff369, 0xe0139000, 0x308c4866, 0xfc74f7e4, 0x48649001, 0xf7e4308e, 0xb280fc6f, 
+    0x48619000, 0xf8dd3090, 0xf7e49000, 0xf369fc67, 0x9000401f, 0xe0062700, 0x22004643, 0x46684669, 
+    0xff35f7ff, 0x42b71c7f, 0x4643dbf6, 0x4669462a, 0xf7ff4668, 0x9800ff2c, 0x4853b201, 0xf7e43084, 
+    0x9800fc53, 0xb2010c00, 0x3082484f, 0xfc4cf7e4, 0xb2019801, 0x3080484c, 0xfc46f7e4, 0x220d2300, 
+    0x0100f246, 0x30784848, 0xfa39f7eb, 0x78004853, 0xd1092804, 0x21fa0428, 0xf2404348, 0xfb903120, 
+    0x3820f0f1, 0xe0161a24, 0x7800484c, 0xd1092805, 0x21fa03e8, 0xf2404348, 0xfb903120, 0x3820f0f1, 
+    0xe0081a24, 0x21fa03a8, 0xf2404348, 0xfb903120, 0x3820f0f1, 0x46201a24, 0xfc6cf7e4, 0x220d2300, 
+    0x0100f246, 0x30784830, 0xfa09f7eb, 0xf7ee2000, 0xe8bdf85a, 0xb51087fc, 0x20ff4604, 0x70084936, 
+    0x220fb2a3, 0x48284936, 0xf7eb307a, 0x2380f9f8, 0xf2402200, 0x482431ff, 0xf7eb307a, 0x2306f9f0, 
+    0x21ff2200, 0x307c4820, 0xf9e9f7eb, 0x73f8f641, 0x217f2200, 0x307e481c, 0xf9e1f7eb, 0x220f2301, 
+    0x48194927, 0xf7eb3078, 0x2300f9da, 0x21402206, 0x30784815, 0xf9d3f7eb, 0x22052300, 0x48122120, 
+    0xf7eb3078, 0x2300f9cc, 0x21102204, 0x3078480e, 0xf9c5f7eb, 0x461a2300, 0x480b210f, 0xf7eb3078, 
+    0x2300f9be, 0x21802207, 0x30784807, 0xf9b7f7eb, 0x22072301, 0x48042180, 0xf7eb3078, 0xbd10f9b0, 
+    0x00036258, 0x00036254, 0xd003501a, 0x00036250, 0x00036240, 0x0003879c, 0x00038718, 0x000388ec, 
+    0x00038868, 0x000386f4, 0x00038670, 0x00038844, 0x000387c0, 0x00036228, 0x00036227, 0x0003626a, 
+    0xffff8000, 0x41f0e92d, 0x27004606, 0xe0082500, 0x21f02204, 0xf7eb48fe, 0xb247f999, 0xe003b107, 
+    0xf5b51c6d, 0xdbf34f00, 0x2204bf00, 0x48f821f0, 0xf98cf7eb, 0xf004b204, 0xb1180008, 0x49f52003, 
+    0xe0177008, 0x0004f004, 0x2002b118, 0x700849f1, 0xf004e010, 0xb1180002, 0x49ee2001, 0xe0097008, 
+    0x0001f004, 0x2000b118, 0x700849ea, 0x20ffe002, 0x700849e8, 0xf99048e7, 0x1c400000, 0x48e6b138, 
+    0xf9924ae4, 0x5c812000, 0xf7ff4630, 0xb260fe79, 0x81f0e8bd, 0x4605b570, 0xf7ff4628, 0x4628ff3c, 
+    0xffb0f7ff, 0x46204604, 0xb510bd70, 0x49db2000, 0x1000f991, 0x54504ad8, 0x49d82001, 0x1001f991, 
+    0x20025450, 0xf99149d5, 0x54501002, 0x49d32003, 0x1003f991, 0x46145450, 0x3003f994, 0x2002f994, 
+    0x1001f994, 0x0000f994, 0xf856f7ee, 0xf9944ccb, 0xf9943003, 0xf9942002, 0xf9941001, 0xf7f10000, 
+    0xbd10fe3b, 0x41ffe92d, 0xa8024669, 0xfe36f7ee, 0x24002600, 0xa802e006, 0x0014f830, 0xb2064430, 
+    0xb2041c60, 0xdbf62c04, 0x10861cb0, 0x0040f1a6, 0xf880fa0f, 0x0068ea4f, 0x0840ea4f, 0x5008f9bd, 
+    0xe00c2401, 0xf930a802, 0x42a80014, 0xa802dd03, 0x0014f930, 0x4628e000, 0x1c604605, 0x2c04b204, 
+    0x1c68dbf0, 0x00401040, 0xf505b205, 0x49ac701f, 0x1000f9b1, 0xfb022202, 0xb2070011, 0x0007eba8, 
+    0x880949a7, 0x0060eba1, 0x49a5b200, 0x46388008, 0xff19f7ed, 0xb0044638, 0x81f0e8bd, 0x4ff0e92d, 
+    0xf04fb085, 0x489f0a00, 0xb000f990, 0x46c846d1, 0x4669e160, 0xf7eea802, 0x2500fde1, 0x2000e016, 
+    0x57494995, 0x5450aa04, 0x0015f93d, 0xdd0b2840, 0xf930a802, 0x28800015, 0x2001da01, 0x2002e000, 
+    0x5749498d, 0x5450aa04, 0xb2c51c68, 0xdbe62d04, 0x7800488d, 0xd1022803, 0xf88d2001, 0xf2420013, 
+    0xf7e40070, 0xf240fba3, 0xf44f11f4, 0xf7e40000, 0x4986fb79, 0x0000f44f, 0xfb24f7e4, 0xf990487f, 
+    0x03000003, 0xf9924a7d, 0xeb002002, 0x4a7b2002, 0x2001f992, 0x1002eb00, 0xf9924a78, 0x18812000, 
+    0x0000f44f, 0xfb0ef7e4, 0xf7e44879, 0x4607fa67, 0xf44f4639, 0xf7e40000, 0x4876fb05, 0xfa54f7e4, 
+    0x46394607, 0x0000f44f, 0xfafcf7e4, 0x0013f89d, 0xf89d0300, 0xeb002012, 0xf89d2002, 0xeb002011, 
+    0xf89d1002, 0x18812010, 0x0000f44f, 0xfaeaf7e4, 0x0010f89d, 0xf89db140, 0xb9280011, 0x0012f89d, 
+    0xf89db110, 0xb1580013, 0x0010f89d, 0xf89db9b8, 0xb1a00011, 0x0012f89d, 0xf89db988, 0xb1700013, 
+    0xf9904856, 0x78404000, 0x70084954, 0x70444608, 0x4002f990, 0x708878c0, 0x70c44608, 0xf89de085, 
+    0xb9400010, 0x0011f89d, 0xf89db928, 0xb1100012, 0x0013f89d, 0xf89db9b8, 0xb1400010, 0x0011f89d, 
+    0xf89db928, 0xb9100012, 0x0013f89d, 0xf89db158, 0xb9880010, 0x0011f89d, 0xf89db170, 0xb9580012, 
+    0x0013f89d, 0x483db940, 0x4000f990, 0x493b7840, 0x46087008, 0xe0587044, 0x0010f89d, 0xf89db140, 
+    0xb1280011, 0x0012f89d, 0xf89db910, 0xb1b80013, 0x0010f89d, 0xf89db940, 0xb9280011, 0x0012f89d, 
+    0xf89db110, 0xb1580013, 0x0010f89d, 0xf89db988, 0xb9700011, 0x0012f89d, 0xf89db958, 0xb1400013, 
+    0xf9904826, 0x78c04002, 0x70884924, 0x70c44608, 0xf89de02b, 0x28020010, 0xf89dd00b, 0x28020011, 
+    0xf89dd007, 0x28020012, 0xf89dd003, 0x28020013, 0xf06fd104, 0xf7ed000f, 0xe016fe06, 0x0010f89d, 
+    0xd1122801, 0x0011f89d, 0xd10e2801, 0x0012f89d, 0xd10a2801, 0x0013f89d, 0xd1062801, 0x05c04916, 
+    0xfa40f7e4, 0x0901f04f, 0x4913e048, 0x0000f44f, 0xfa38f7e4, 0xfe59f7ff, 0x78004810, 0xd1222801, 
+    0x4a044805, 0x2000f992, 0x20015c81, 0x0000e018, 0xd00350a2, 0x00036227, 0x00036258, 0x00036240, 
+    0x0003622a, 0x000362b1, 0x0003625c, 0x77777776, 0xd0030446, 0xd180000c, 0xdcba01f5, 0x0003845c, 
+    0xfc9ef7ff, 0x4a5be00e, 0xf9934b5b, 0x5cd13000, 0x78124a5a, 0xd0012a01, 0xe0002201, 0x46102200, 
+    0xfc8ef7ff, 0x04882101, 0xf9def7ec, 0x0001f108, 0xf880fa0f, 0x0f03f1b8, 0xae9bf6ff, 0xf1b9bf00, 
+    0xd0720f00, 0xfe3ef7ff, 0xf7ed2000, 0x484bf932, 0x28017800, 0xf7edd102, 0xe001f9d3, 0xfa1ff7ed, 
+    0x0070f242, 0xfa52f7e4, 0x78004844, 0x2100b968, 0xf7ee2001, 0x2100f9e0, 0xf7ee200c, 0x2101f93a, 
+    0xf7ee4608, 0xf7f1f988, 0xf242fe0f, 0xf7e40070, 0xf7fefa3d, 0xb204ff0d, 0x28001c60, 0xf04fd065, 
+    0x20000a01, 0xf905f7ed, 0xeb044620, 0x104971d0, 0x0141eba4, 0x2001b121, 0xfd65f7ed, 0xb2041c60, 
+    0xf7ed1060, 0x2000fcb0, 0xfd5df7ed, 0xa8024669, 0xfc34f7ee, 0xf9bd2501, 0xe0096008, 0xf930a802, 
+    0x42b00015, 0xa802da02, 0x6015f930, 0xb2c51c68, 0xdbf32d04, 0x0008f1a6, 0x1076b206, 0x88094920, 
+    0xf1063147, 0x1a89029c, 0xf7edb208, 0x2074fca3, 0xf8a6f7ee, 0x02c82101, 0xf966f7ec, 0x78004817, 
+    0xd1032801, 0xf939f7ed, 0xe01ee012, 0xf9904815, 0x4601b000, 0x1000f991, 0x17f91ccf, 0x7191eb07, 
+    0xeba71089, 0xb2480181, 0xf8ecf7f2, 0xf9a7f7ed, 0x0070f242, 0xf9daf7e4, 0x78004808, 0x4658b910, 
+    0xf8e0f7f2, 0xf7ed2001, 0x4650f8a4, 0xe8bdb005, 0x00008ff0, 0x00036258, 0x00036227, 0x000361ee, 
+    0x0003622a, 0x000362b1, 0x2400b570, 0x220d2402, 0x48fe49fd, 0xfebaf7ea, 0xb224b920, 0x49fc2000, 
+    0xe0038008, 0x2000b224, 0x800849f9, 0xf9b048f9, 0x28000000, 0x48f7dd08, 0x0000f9b0, 0xda032880, 
+    0x880048f4, 0xb2044420, 0xdd082c07, 0x880048f0, 0xb2001c40, 0x800849ee, 0x000af1a4, 0xf114b204, 
+    0xda080f07, 0x880048ea, 0xb2001e40, 0x800849e8, 0x000af104, 0xb2a3b204, 0xf6432208, 0x48e67100, 
+    0xfe6df7ea, 0x2208b2a3, 0x7100f643, 0x1c8048e2, 0xfe65f7ea, 0x2208b2a3, 0x7100f643, 0x1d0048de, 
+    0xfe5df7ea, 0x2208b2a3, 0x7100f643, 0x1d8048da, 0xfe55f7ea, 0x2208b2a3, 0x7100f643, 0x301048d6, 
+    0xfe4df7ea, 0x2208b2a3, 0x7100f643, 0x301248d2, 0xfe45f7ea, 0x2208b2a3, 0x7100f643, 0x301448ce, 
+    0xfe3df7ea, 0x2208b2a3, 0x7100f643, 0x301648ca, 0xfe35f7ea, 0x2208b2a3, 0x7100f643, 0x300848c6, 
+    0xfe2df7ea, 0x2208b2a3, 0x7100f643, 0x300a48c2, 0xfe25f7ea, 0x2208b2a3, 0x7100f643, 0x300c48be, 
+    0xfe1df7ea, 0x2208b2a3, 0x7100f643, 0x300e48ba, 0xfe15f7ea, 0x2208b2a3, 0x7100f643, 0x301848b6, 
+    0xfe0df7ea, 0x2208b2a3, 0x7100f643, 0x301a48b2, 0xfe05f7ea, 0x2208b2a3, 0x7100f643, 0x301c48ae, 
+    0xfdfdf7ea, 0x2208b2a3, 0x7100f643, 0x301e48aa, 0xfdf5f7ea, 0x213f2200, 0xf7ea48a7, 0x49a4fe07, 
+    0x44088809, 0xb2abb205, 0x213f2200, 0xf7ea48a2, 0x2200fde6, 0x48a0213f, 0xf7ea1c80, 0x499cfdf7, 
+    0x44088809, 0xb2abb205, 0x213f2200, 0x1c80489a, 0xfdd5f7ea, 0x213f2200, 0x1d004897, 0xfde6f7ea, 
+    0x88094993, 0xb2054408, 0x2200b2ab, 0x4892213f, 0xf7ea1d00, 0x2200fdc4, 0x488f213f, 0xf7ea1d80, 
+    0x498bfdd5, 0x44088809, 0xb2abb205, 0x213f2200, 0x1d804889, 0xfdb3f7ea, 0x213f2200, 0x30104886, 
+    0xfdc4f7ea, 0x88094982, 0xb2054408, 0x2200b2ab, 0x4881213f, 0xf7ea3010, 0x2200fda2, 0x487e213f, 
+    0xf7ea3012, 0x497afdb3, 0x44088809, 0xb2abb205, 0x213f2200, 0x30124878, 0xfd91f7ea, 0x213f2200, 
+    0x30144875, 0xfda2f7ea, 0x88094971, 0xb2054408, 0x2200b2ab, 0x4870213f, 0xf7ea3014, 0x2200fd80, 
+    0x486d213f, 0xf7ea3016, 0x4969fd91, 0x44088809, 0xb2abb205, 0x213f2200, 0x30164867, 0xfd6ff7ea, 
+    0xb570bd70, 0x2d004605, 0x2500da00, 0x78004863, 0x2621b908, 0x2622e000, 0x0045eba6, 0x2c00b204, 
+    0x4620dd01, 0x2000e000, 0xb2a34604, 0x213f2200, 0xf7ea4859, 0xb2a3fd54, 0x213f2200, 0x1c804856, 
+    0xfd4df7ea, 0x2200b2a3, 0x4853213f, 0xf7ea1d00, 0xb2a3fd46, 0x213f2200, 0x1d80484f, 0xfd3ff7ea, 
+    0x2200b2a3, 0x484c213f, 0xf7ea3010, 0xb2a3fd38, 0x213f2200, 0x30124848, 0xfd31f7ea, 0x2200b2a3, 
+    0x4845213f, 0xf7ea3014, 0xb2a3fd2a, 0x213f2200, 0x30164841, 0xfd23f7ea, 0x493d2000, 0xf7ff8008, 
+    0xbd70fe73, 0x41f0e92d, 0x2e004606, 0x2600da00, 0xda042e06, 0x7800483a, 0xd1002801, 0x48372606, 
+    0xb9087800, 0xe0002721, 0xeba72722, 0xb2050046, 0x48342402, 0x28047800, 0x4832d003, 0x28057800, 
+    0xb916d103, 0x000af1a4, 0x482eb204, 0x28047800, 0x482cd003, 0x28057800, 0x482bd10d, 0x28106800, 
+    0x482ad909, 0x280f7800, 0x4829da05, 0x28017800, 0x1c68d101, 0x2c07b205, 0x1c68dd04, 0xf1a4b205, 
+    0xb204000a, 0x0f07f114, 0x1e68da04, 0xf104b205, 0xb204000a, 0x2200b2ab, 0x4817213f, 0xf7ea3008, 
+    0xb2abfcce, 0x213f2200, 0x300a4813, 0xfcc7f7ea, 0x2200b2ab, 0x4810213f, 0xf7ea300c, 0xb2abfcc0, 
+    0x213f2200, 0x300e480c, 0xfcb9f7ea, 0x2200b2ab, 0x4809213f, 0xf7ea3018, 0xb2abfcb2, 0x213f2200, 
+    0x301a4805, 0x0000e016, 0xffffe000, 0xd0020108, 0x0003890e, 0x00036346, 0xd0034200, 0x000384d5, 
+    0x00038465, 0x0003626a, 0x000361dc, 0x00036226, 0x000384fa, 0xfc93f7ea, 0x2200b2ab, 0x4847213f, 
+    0xfc8df7ea, 0x2200b2ab, 0x4844213f, 0xf7ea1c80, 0xb2a3fc86, 0xf6432208, 0x48407100, 0xf7ea3814, 
+    0xb2a3fc7e, 0xf6432208, 0x483c7100, 0xf7ea3812, 0xb2a3fc76, 0xf6432208, 0x48387100, 0xf7ea3810, 
+    0xb2a3fc6e, 0xf6432208, 0x48347100, 0xf7ea380e, 0xb2a3fc66, 0xf6432208, 0x48307100, 0xf7ea1f00, 
+    0xb2a3fc5e, 0xf6432208, 0x482c7100, 0xf7ea1e80, 0xb2a3fc56, 0xf6432208, 0x48287100, 0xfc4ff7ea, 
+    0x2208b2a3, 0x7100f643, 0x1c804824, 0xfc47f7ea, 0xf8c3f7ed, 0x81f0e8bd, 0x4821b510, 0xb9087800, 
+    0xe0002421, 0x46232422, 0x213f2200, 0x381c481b, 0xfc35f7ea, 0x22004623, 0x4818213f, 0xf7ea381a, 
+    0x4623fc2e, 0x213f2200, 0x38184814, 0xfc27f7ea, 0x22004623, 0x4811213f, 0xf7ea3816, 0x4623fc20, 
+    0x213f2200, 0x380c480d, 0xfc19f7ea, 0x22004623, 0x480a213f, 0xf7ea380a, 0x4623fc12, 0x213f2200, 
+    0x38084806, 0xfc0bf7ea, 0x22004623, 0x4803213f, 0xf7ea1f80, 0xf7fffc04, 0xbd10fd57, 0xd003421c, 
+    0x000384d5, 0xe007b510, 0xf99048fe, 0xf7eb0000, 0xb908ff00, 0xbd102000, 0xf7e348fb, 0xf400fde5, 
+    0x28002000, 0x2002d1f0, 0xfeeaf7eb, 0x600849f7, 0xe7f02001, 0x48f4b510, 0xf7e31d00, 0x0fc0fdd5, 
+    0xb510bd10, 0xf1c44604, 0x4aef0103, 0xeb02320c, 0xf7e30081, 0xbd10fdc9, 0x4ff0e92d, 0x4605b087, 
+    0x4693468a, 0xea4f4698, 0xf1b806aa, 0xd1110f00, 0x22012000, 0x0202e9cd, 0x90059004, 0x90019000, 
+    0x008aea4f, 0x462bb201, 0x3a404adf, 0xf7ea2001, 0xe0bffdf9, 0x0f01f1b8, 0xf1bbd168, 0xd0240f07, 
+    0xe01f2400, 0x384048d8, 0xfd9ef7e3, 0x0024f845, 0x384048d5, 0xfd98f7e3, 0xf84519a1, 0x48d20021, 
+    0xf7e33840, 0xeb04fd91, 0xf8450146, 0x48ce0021, 0xf7e33840, 0xeb06fd89, 0x44210146, 0x0021f845, 
+    0xb2041c60, 0xdbdd42b4, 0x2400e094, 0x48c6e03b, 0xf7e33840, 0x4607fd79, 0x0001f007, 0x0102f007, 
+    0x30c1ea40, 0x0024f845, 0x0008f007, 0x0180f3c7, 0x3040ea41, 0xf84519a1, 0xf0070021, 0xf3c70020, 
+    0xea411100, 0xeb0420c0, 0xf8450146, 0xf0070021, 0xf3c70080, 0xea411180, 0xeb062040, 0x44210146, 
+    0x0021f845, 0x384048b0, 0xfd4ef7e3, 0x48ae4607, 0xf7e33840, 0x4607fd49, 0x384048ab, 0xfd44f7e3, 
+    0x1c604607, 0x42b4b204, 0xe053dbc1, 0x0f02f1b8, 0x2400d11d, 0x48a4e018, 0xf7e33840, 0x19a1fd35, 
+    0x0021f845, 0x384048a0, 0xfd2ef7e3, 0x0024f845, 0x3840489d, 0xfd28f7e3, 0x489b4607, 0xf7e33840, 
+    0x4607fd23, 0xb2041c60, 0xdbe442b4, 0xf1b8e032, 0xd12f0f03, 0x0900f04f, 0xe0292400, 0x38404892, 
+    0xfd12f7e3, 0x1c4a4649, 0xf982fa0f, 0x0021f845, 0x3840488d, 0xfd08f7e3, 0x1c4a4649, 0xf982fa0f, 
+    0x0021f845, 0x38404888, 0xfcfef7e3, 0x1c4a4649, 0xf982fa0f, 0x0021f845, 0x38404883, 0xfcf4f7e3, 
+    0x1c4a4649, 0xf982fa0f, 0x0021f845, 0xb2041c60, 0xdbd342b4, 0x487c2100, 0xf7e3387c, 0xb007fcea, 
+    0x8ff0e8bd, 0x4ff8e92d, 0x460d4604, 0x461f4690, 0x9b0be9dd, 0xa028f8dd, 0x20009e0d, 0x2f0b9000, 
+    0x4649d104, 0x301c4870, 0xfcd3f7e3, 0xb1401c68, 0xd1072d07, 0xd0012c05, 0xd1032c06, 0x90002001, 
+    0x2500e000, 0xdd022e00, 0x1e701076, 0x4631b206, 0x30084865, 0xfcbdf7e3, 0x980e2200, 0x7080ea42, 
+    0x7009ea40, 0x500bea40, 0x42caea40, 0xea429800, 0xea404080, 0xea403088, 0xea402087, 0xea401045, 
+    0x48590104, 0xfca5f7e3, 0x8ff8e8bd, 0x41f0e92d, 0x460e4605, 0x461c4617, 0x8018f8dd, 0x04201064, 
+    0x1047ea40, 0x0010f040, 0x00c6ea40, 0x0145ea40, 0x387c484d, 0xfc8df7e3, 0x0f00f1b8, 0x4641d004, 
+    0x38784849, 0xfc85f7e3, 0x81f0e8bd, 0x41f0e92d, 0x460f4606, 0x48444615, 0xf7e31d00, 0x4604fc75, 
+    0x040bf3c4, 0xb977b17e, 0x0f65ebb4, 0xf640da05, 0xeba04000, 0x44040065, 0xeba4e001, 0x2c000465, 
+    0xf504da01, 0x00a46440, 0x010df3c4, 0x38784836, 0xfc5ff7e3, 0x81f0e8bd, 0x4604b5f0, 0x4e34460d, 
+    0x29015771, 0x2910d018, 0x1e4eda16, 0x40b72701, 0x60374e30, 0xf04f1e4e, 0x40b737ff, 0x4f2eb2be, 
+    0x4e2e603e, 0x04368836, 0x603e4f2c, 0x88364e2c, 0x4f2b0436, 0xe002603e, 0x4f262600, 0xbb22603e, 
+    0x68364e24, 0x2000b30e, 0xf854e01b, 0x4f216020, 0x403e683f, 0xf854b136, 0x4f1f6020, 0x433e683f, 
+    0x6020f844, 0x6020f854, 0x683f4f1c, 0xb136403e, 0x6020f854, 0x683f4f1a, 0xf844433e, 0x1c466020, 
+    0xebb0b230, 0xdbe00f43, 0x4e12e035, 0xb34e6836, 0xe02d2000, 0x6020f854, 0x683f4f0e, 0xb136403e, 
+    0x6020f854, 0x683f4f0c, 0xf844433e, 0xf8546020, 0x4f0a6020, 0x403e683f, 0xf854b1c6, 0x4f086020, 
+    0xe010683f, 0x00038910, 0xd1800380, 0x00036230, 0x00038911, 0x0003892c, 0x00038928, 0x00038934, 
+    0x00038930, 0x433ee007, 0x6020f844, 0xb2301d06, 0x0f43ebb0, 0xbdf0dbce, 0x2301b510, 0x21082203, 
+    0xf7ea48b9, 0xbd10f9b5, 0x4fffe92d, 0x460cb083, 0x461f4616, 0xa911e9dd, 0x20019d10, 0xf04f9002, 
+    0xf04f0b00, 0x20000800, 0xf5b59001, 0xdc037f80, 0x0005eb09, 0xf980fa0f, 0xdc012d02, 0x90012000, 
+    0x0f05f1ba, 0xf04fd106, 0x20000b01, 0xea4f9002, 0xe0010969, 0x0900f04f, 0xb1401c70, 0xd1072e07, 
+    0xd0012c05, 0xd1032c06, 0x0801f04f, 0x2600e000, 0x0f00f1b8, 0x489dd104, 0x28015d00, 0x2700d100, 
+    0x4009ea4f, 0x104bea40, 0x0018f040, 0x0147ea40, 0x38c44895, 0xfb8df7e3, 0x38404893, 0xf7e39901, 
+    0x9801fb88, 0xf44fb998, 0xea402000, 0xea404088, 0xf4403087, 0xea406080, 0xea401046, 0x488a0104, 
+    0xf7e33848, 0x2101fb76, 0xf7eb0288, 0x2200fbfd, 0xea429802, 0xf4407000, 0xea402000, 0xea404088, 
+    0xea403087, 0xea40208a, 0xea401046, 0x487e0104, 0xf7e33848, 0xf7fffb5e, 0xb918fd65, 0xb0072000, 
+    0x8ff0e8bd, 0xf7e3487a, 0x9000fb59, 0x4658462a, 0xf7ff9901, 0x0068fecb, 0x4622b201, 0x98039b13, 
+    0xfd7af7ff, 0xff68f7ff, 0x4642462b, 0x98034621, 0xfee2f7ff, 0xe7e29800, 0x5fffe92d, 0x468b4607, 
+    0x486c4698, 0xb9208800, 0x0905f04f, 0x0a00f04f, 0xf04fe003, 0xf04f0900, 0x463b0a05, 0xf04f221d, 
+    0x48614160, 0xf7ea3038, 0x465bf903, 0x0291220c, 0x3038485d, 0xf8fcf7ea, 0x2218464b, 0x51f8f04f, 
+    0x30384859, 0xf8f4f7ea, 0x22104653, 0x017ff44f, 0x30384855, 0xf8ecf7ea, 0xd0072f07, 0xf2402208, 
+    0x48513100, 0x9b023038, 0xf8e2f7ea, 0x22052301, 0x484d2120, 0xf7ea3038, 0x2301f8db, 0x21102204, 
+    0x30384849, 0xf8d4f7ea, 0x4847211f, 0xfaf1f7e3, 0x38444845, 0xfae8f7e3, 0x48432100, 0xf7e338c8, 
+    0x2100fae8, 0x38c04840, 0xfae3f7e3, 0x5640f5c8, 0x483d4631, 0xf7e338c0, 0xf240fadc, 0x483a11ad, 
+    0xf7e33848, 0x2118fad6, 0x38c44837, 0xfad1f7e3, 0x48352119, 0xf7e338c4, 0xbf00facc, 0x38c44832, 
+    0xfac2f7e3, 0x0001f000, 0xd1f72800, 0x38c0482e, 0xfabaf7e3, 0xebc84606, 0xe0010686, 0x5640f506, 
+    0xdbfb2e00, 0xf5a6e001, 0xf5b65640, 0xdafa5f40, 0x48254631, 0xf7e338c0, 0x211ffaac, 0xf7e34822, 
+    0x4821faa8, 0xf7e33844, 0x2300fa9f, 0xf04f221d, 0x481d4160, 0xf7ea3038, 0x2300f87b, 0x0291220c, 
+    0x30384819, 0xf874f7ea, 0xd0072f07, 0x22082300, 0x3100f240, 0x30384814, 0xf86af7ea, 0xe01e2400, 
+    0x38884811, 0xfa80f7e3, 0xf3c54605, 0x980e5101, 0x1014f820, 0x3103f3c5, 0xf820980f, 0xf3c51014, 
+    0x98102103, 0x1014f820, 0x1103f3c5, 0xf8209811, 0xf0051014, 0x9812010f, 0x1014f820, 0x45441c64, 
+    0xe8bdd3de, 0x00009fff, 0xd18003c8, 0x0003891c, 0xd0035120, 0x000361cc, 0x4ff0e92d, 0x2000b091, 
+    0x90099010, 0x900848fe, 0x90072009, 0x0900f04f, 0x49fc20b1, 0x4efc6008, 0x5080f506, 0xf506900e, 
+    0x900d50c0, 0x83e4f8df, 0x90064640, 0x48f82101, 0x0000f990, 0xff08f7f0, 0xf99048f5, 0xf7f10000, 
+    0x20b2fa33, 0x600849ef, 0xf7f12000, 0x2002f913, 0xf884f7f1, 0xf99048ee, 0xf7f00000, 0x2100fe43, 
+    0x0000f244, 0xfa2df7f1, 0xf99048e9, 0xf7f00000, 0x2100fdc3, 0x2000f44f, 0xfaa6f7eb, 0x49e120b3, 
+    0x21c06008, 0xf7e348e3, 0x48e1fa1f, 0x0000f990, 0xfdd8f7f0, 0x49e02000, 0x46024603, 0x1000e9cd, 
+    0x46082101, 0xfbf6f7e9, 0x02812001, 0x02432205, 0x3200e9cd, 0x1002e9cd, 0x1e824603, 0x46302105, 
+    0xfe22f7ff, 0x20002400, 0xe00c9004, 0xf93149ce, 0x28000014, 0x4601db01, 0x4241e000, 0x44119a04, 
+    0x1c609104, 0xf5b4b204, 0xdbef7f00, 0x12409804, 0x20009004, 0xe00b9005, 0x28109804, 0x9804dd03, 
+    0x90041040, 0xe006e000, 0x1c409805, 0x9005b240, 0x28069805, 0xbf00dbf0, 0x780048c0, 0xd1012803, 
+    0x90052005, 0xe0092400, 0xf93048bb, 0x98051014, 0x98064101, 0x1014f820, 0xb2041c60, 0xdbf32c80, 
+    0x49b020b4, 0x21006008, 0x460b9806, 0xe9cd460a, 0x20010100, 0xfb9ef7e9, 0x49aa20b5, 0x21006008, 
+    0x460b9806, 0xe9cd460a, 0x21010100, 0xf7e94608, 0x20b6fb91, 0x600849a3, 0x98062100, 0x460a460b, 
+    0x0100e9cd, 0x20012102, 0xfb84f7e9, 0x499d20b7, 0x21006008, 0x460b9806, 0xe9cd460a, 0x21030100, 
+    0xf7e92001, 0x20b8fb77, 0x60084996, 0xe0042400, 0xf8482000, 0x1c600024, 0xf5b4b204, 0xdbf77f00, 
+    0xe1752500, 0xf7eb2002, 0x4995fa7b, 0x20b96008, 0x3005eb00, 0x6008498b, 0xf97cf7e3, 0xf7eb2002, 
+    0x498ffa6f, 0x1a086809, 0x6008498d, 0x498d2000, 0x0025f841, 0x498c1e40, 0x0015f821, 0x900f2000, 
+    0xe0062400, 0x1024f856, 0x4408980f, 0x1c60900f, 0xf5b4b204, 0xdbf56f00, 0x12c0980f, 0x2400900f, 
+    0xf856e007, 0x980f1024, 0xf8461a08, 0x1c600024, 0xf5b4b204, 0xdbf46f00, 0x7800487c, 0xd1022804, 
+    0x0902f04f, 0x4879e008, 0x28057800, 0xf04fd102, 0xe0010901, 0x0900f04f, 0xe0122400, 0xe0092700, 
+    0x0024f856, 0xf85619e1, 0x44081021, 0x0024f846, 0xb2071c78, 0xfa002004, 0x42b8f009, 0x1c60dcf0, 
+    0x2004b204, 0xf009fa00, 0x6000f5c0, 0xdce542a0, 0x27002400, 0xf856e00d, 0xf1c90024, 0x40880106, 
+    0x0027f846, 0xfa002004, 0x4420f009, 0x1c78b204, 0x2004b207, 0xf009fa00, 0x6000f5c0, 0xdcea42a0, 
+    0x2000e004, 0x0027f846, 0xb2071c78, 0x7f00f5b7, 0x20badbf7, 0x3005eb00, 0x6008494a, 0x1007e9dd, 
+    0x0100e9cd, 0xe9dd4630, 0x9909320d, 0xfff6f00f, 0xeb0020bb, 0x49433005, 0x240e6008, 0x980ee02f, 
+    0x0024f850, 0x010cf1c9, 0x43404108, 0xf851990d, 0xf1c91024, 0x4111020c, 0xf8529a0d, 0xf1c92024, 
+    0x411a030c, 0x0002fb01, 0x0024f846, 0x0024f858, 0x1024f856, 0x00e1eb00, 0x0024f848, 0x0024f856, 
+    0xf8514938, 0x42881025, 0xf856dd07, 0x49350024, 0x0025f841, 0xf8204834, 0x1c604015, 0x2cc3b204, 
+    0x4831dbcd, 0x0015f930, 0x0a01f1a0, 0xf930482e, 0xf856b015, 0x900c002a, 0x002bf856, 0xe9dd900b, 
+    0xeba0100b, 0x48280141, 0x0015f930, 0xf8561c40, 0x44080020, 0xe9dd900a, 0x1a41100b, 0x1280980a, 
+    0xf0f0fb91, 0x010beb0a, 0x2041eb00, 0x60084920, 0x68004608, 0xfb802105, 0x07401001, 0x00d1ea40, 
+    0xe9cd0749, 0x48161002, 0x17d36802, 0x99034608, 0xef16f00e, 0x4380f04f, 0xf1611ac0, 0x4a150100, 
+    0x02c5eb02, 0x4813c203, 0x0035f850, 0xf8414912, 0xf2400025, 0x13581103, 0xf954f7e3, 0xe01d480d, 
+    0x000300d0, 0x000385b0, 0x00054000, 0x0004a648, 0x000362b1, 0xd0030864, 0x0003893a, 0x0003625c, 
+    0x00038a40, 0x0004c8a8, 0x0004c8bc, 0x0003626a, 0x00038a3c, 0x0004c880, 0x00043010, 0x00c5eb00, 
+    0x88806802, 0xea430403, 0xb2814012, 0x3000f44f, 0xf8d8f7e3, 0xf85048fe, 0xb2810035, 0x3000f44f, 
+    0xf8d0f7e3, 0x680048fb, 0x434849fb, 0x440849fb, 0x4af717c1, 0x03c5eb02, 0x1a80cb0c, 0xdb0e4199, 
+    0xeb0048f3, 0xe9d000c5, 0x49f23000, 0x4af26809, 0x4af24351, 0x17ca1a89, 0x41901a59, 0x2001da01, 
+    0x20bc9010, 0x3005eb00, 0x600849ed, 0xb2451c68, 0xf6ff2d05, 0x2500ae87, 0x49ea2000, 0x0025f841, 
+    0x49e91e40, 0x0015f821, 0xe014240e, 0x0024f858, 0x0024f846, 0x0024f858, 0xf85149e2, 0x42881025, 
+    0xf858dd07, 0x49df0024, 0x0025f841, 0xf82048de, 0x1c604015, 0x2cc3b204, 0x48dbdbe8, 0x0015f930, 
+    0x0a01f1a0, 0xf93048d8, 0xf858b015, 0x900c002a, 0x002bf858, 0xe9dd900b, 0xeba0100b, 0x48d20141, 
+    0x0015f930, 0xf8561c40, 0x44080020, 0xe9dd900a, 0x1a41100b, 0x1280980a, 0xf0f0fb91, 0x010beb0a, 
+    0x2041eb00, 0x600849c9, 0x68004608, 0xfb802105, 0x07401001, 0x00d1ea40, 0xe9cd0749, 0x48c41002, 
+    0x17d36802, 0x99034608, 0xee4af00e, 0x4380f04f, 0x46084684, 0x0103ebbc, 0x0000f160, 0xeb024ab4, 
+    0xe9c202c5, 0x48b21000, 0x0035f850, 0x614849b9, 0x49b320bd, 0xf2406008, 0x13581103, 0xf882f7e3, 
+    0xeb0048ab, 0x681002c5, 0x0c008892, 0x4002ea40, 0xf44fb281, 0xf7e33000, 0x48a5f825, 0x0035f850, 
+    0xf44fb281, 0xf7e33000, 0x9810f81d, 0xbf00b100, 0xf8324a9f, 0xb2922035, 0x4a9db211, 0x02c5eb02, 
+    0x79126813, 0x4c02ea4f, 0x4213ea4c, 0xb210b292, 0xff67f7f0, 0x499a20be, 0x489f6008, 0x0000f990, 
+    0xfafaf7f0, 0x499620bf, 0x20016008, 0xfb12f7e9, 0xe8bdb011, 0xe92d8ff0, 0xb08b4f50, 0x90092003, 
+    0x90072000, 0xbf00bf00, 0x21012200, 0xf7e94893, 0x2801fd36, 0x2208d17d, 0x48910201, 0xfd56f7e9, 
+    0x9003b240, 0x22082300, 0x488d0151, 0xfd37f7e9, 0x9009200a, 0x7800488b, 0xd16b2801, 0x498b488a, 
+    0x22002301, 0x1000e9cd, 0xf9904883, 0x46181000, 0xf9b7f7e9, 0x0a00f04f, 0x4885e055, 0x001af930, 
+    0xf8314982, 0x49830010, 0x001af821, 0xf9304880, 0x497d001a, 0x0010f831, 0xf821497f, 0x21c9001a, 
+    0x43489809, 0xf931497a, 0x4348101a, 0xf8314979, 0xfb11101a, 0x4a78f101, 0x201af832, 0xf8334b76, 
+    0xfb12301a, 0xfb801103, 0x48728901, 0x001af830, 0x200004c1, 0x0104e9cd, 0x464b4642, 0x0104e9dd, 
+    0xed8ef00e, 0xea400c00, 0x14094001, 0xeb024a6b, 0xc20302ca, 0xf8304868, 0x04c1001a, 0xe9cd2000, 
+    0x46420104, 0xe9dd464b, 0xf00e0104, 0x0c00ed7a, 0x4001ea40, 0x4a621409, 0x02caeb02, 0xf10ac203, 
+    0xf0000001, 0x98090aff, 0xdba64582, 0x48522100, 0xe18ce001, 0xf990e046, 0xf7f00000, 0x2000fb85, 
+    0x70084950, 0x461a2301, 0x484b2100, 0x0000f990, 0xfd9af7f0, 0xf7e24853, 0xf000feb1, 0x28000008, 
+    0x4850d02f, 0xf7e21c80, 0xf000fea9, 0x28000008, 0x2303d0f6, 0x210c2202, 0x30c44841, 0xfc9ff7e9, 
+    0x2202bf00, 0x483e210c, 0xf7e930c4, 0x2800fcaf, 0x483bd1f7, 0xf7e230cc, 0x4943fe91, 0x48388008, 
+    0xf7e230ca, 0x4941fe8b, 0x48358008, 0xf7e230d4, 0x493ffe85, 0x48328008, 0xf7e230d2, 0x493dfe7f, 
+    0xe13b8008, 0x49314830, 0x22002301, 0x1000e9cd, 0xf9904829, 0x46181000, 0xf903f7e9, 0x26002400, 
+    0xe01b46a2, 0xf930482a, 0x4927001a, 0x0010f931, 0xf851492a, 0xfba0103a, 0x19040101, 0xf9304824, 
+    0x4922001a, 0x0010f931, 0xf8514925, 0xfba0103a, 0x19860101, 0x0001f10a, 0x0afff000, 0x45829809, 
+    0xebb4dbe0, 0x48240b06, 0xf9914913, 0xf8401000, 0xf04fb021, 0x90080000, 0x68004820, 0x0001f100, 
+    0x6008491e, 0xf7e24817, 0xf000fe39, 0xe0370008, 0x0004c880, 0x000362c8, 0x008637bd, 0x01312d00, 
+    0x000385b0, 0x0004c8a8, 0x0004c8bc, 0x00038a3c, 0x00038a40, 0x00043010, 0x000362b1, 0xd1800000, 
+    0xd0035126, 0x000362af, 0x00044b08, 0x00044308, 0x0002f9b0, 0x0004c8c6, 0x0004c8da, 0x0004c8f0, 
+    0x0004c940, 0xd28e0078, 0x00038a4c, 0x00038a4e, 0x00038a50, 0x00038a52, 0x00043000, 0x00038a54, 
+    0xd0672800, 0xf7e248f7, 0xf000fdf9, 0x28000008, 0x2303d060, 0x210c2202, 0xf7e948f3, 0xbf00fbf0, 
+    0x210c2202, 0xf7e948f0, 0x2800fc01, 0x48eed1f8, 0xf7e23008, 0x49edfde3, 0x48eb8008, 0xf7e21d80, 
+    0x49ebfddd, 0x48e88008, 0xf7e23010, 0x49e9fdd7, 0x48e58008, 0xf7e2300e, 0x49e7fdd1, 0x48e38008, 
+    0x0000f9b0, 0xf9b149e5, 0x42881000, 0x48e0d117, 0x0000f9b0, 0xf9b149e2, 0x42881000, 0x48ddd10f, 
+    0x0000f9b0, 0xf9b149df, 0x42881000, 0x48dad107, 0x0000f9b0, 0xf9b149dc, 0x42881000, 0x2001d006, 
+    0x48da9008, 0x1e406800, 0x600849d8, 0xf9b048cf, 0x49d20000, 0x48ce8008, 0x0000f9b0, 0x800849d0, 
+    0xf9b048cc, 0x49cf0000, 0x48cb8008, 0x0000f9b0, 0x800849cd, 0x465a9808, 0x73ebea4f, 0x48cc9000, 
+    0x0000f990, 0xfcc6f7f0, 0x0f00f1bb, 0xf5bbdd24, 0xdd184f00, 0x213f2200, 0xf7e948c6, 0x281afb97, 
+    0xf240da02, 0xe00110ff, 0x30fef240, 0xf5bb9006, 0xdd013f80, 0xe0039906, 0xeb009806, 0x104971d0, 
+    0x9107b289, 0xf5bbe021, 0xdd024f80, 0x90072003, 0x2002e01b, 0xe0189007, 0x0000f1cb, 0x4f00f5b0, 
+    0xf1cbdd09, 0xf5b00000, 0xdd013f80, 0xe0002005, 0x90072002, 0xf1cbe009, 0xf5b00000, 0xdd024f80, 
+    0x90072000, 0x2000e001, 0x23019007, 0x9807461a, 0x48a7b201, 0x0000f990, 0xfc26f7f0, 0xb2839803, 
+    0x01512208, 0x38c44898, 0xfb39f7e9, 0x2301e008, 0xf2402200, 0x489e31fe, 0x0000f990, 0xfc14f7f0, 
+    0xe8bdb00b, 0xe92d8f50, 0xb08d4ff0, 0x3000f44f, 0x10809008, 0x20039007, 0xbf009006, 0x4896bf00, 
+    0xfd1cf7e2, 0x0003f000, 0x98039003, 0x2801b130, 0x2802d008, 0x2803d00a, 0xe00bd110, 0x0000f241, 
+    0xe00f9008, 0x0000f244, 0xe00b9008, 0x0000f248, 0xe0079008, 0x3000f44f, 0xe0039008, 0x0000f241, 
+    0xbf009008, 0x9808bf00, 0x71d0eb00, 0x91071049, 0x21012200, 0xf7e94881, 0x2801fae2, 0x200ad17e, 
+    0x487f9006, 0x28017800, 0xf04fd179, 0xe0960a00, 0xa9092000, 0x002af841, 0x8800487a, 0x487ab968, 
+    0x28037800, 0x2000d104, 0xf8214978, 0xe008001a, 0x497620ff, 0x001af821, 0x2000e003, 0xf8214973, 
+    0x4873001a, 0x001af830, 0xb2001c40, 0xf8214970, 0x4870001a, 0x23014970, 0xe9cd2200, 0xfa4f1000, 
+    0x4618f18a, 0xff4df7e8, 0x0b00f04f, 0x486be060, 0x001bf930, 0xf8314968, 0x49690010, 0x001bf821, 
+    0xf9304866, 0x4963001b, 0x0010f831, 0xf8214965, 0x21c9001b, 0x43489806, 0xf9314960, 0x4348101b, 
+    0xf831495f, 0xfb11101b, 0x4a5ef101, 0x201bf832, 0xf8334b5c, 0xfb12301b, 0xfb801103, 0x48588901, 
+    0x001bf830, 0x210004c0, 0x1004e9cd, 0x464b4642, 0x0104e9dd, 0xeb24f00e, 0xea400c00, 0x14094001, 
+    0x028aeb0a, 0xeb034b50, 0xeb021202, 0xc20302cb, 0xf830484c, 0x04c0001b, 0xe0012100, 0xe055e055, 
+    0x1004e9cd, 0x464b4642, 0x0104e9dd, 0xeb08f00e, 0xea400c00, 0x14094001, 0x028aeb0a, 0xeb034b43, 
+    0xeb021202, 0xc20302cb, 0x0001f10b, 0x0bfff000, 0x45839806, 0xf10adb9b, 0xf0000001, 0xf1ba0aff, 
+    0xf6ff0f04, 0x2000af65, 0x7008492d, 0x70084938, 0x8800482c, 0xd1282801, 0x48272100, 0xf7e23866, 
+    0x2100fc43, 0x38644824, 0xfc3ef7e2, 0x0a00f04f, 0x4830e018, 0xb9207800, 0xf990481d, 0x45820000, 
+    0xfa4fd00c, 0xf7eff08a, 0x491bffc7, 0xeb013114, 0x2301104a, 0x21402206, 0xfa21f7e9, 0x0001f10a, 
+    0x0afff000, 0x0f04f1ba, 0xe1f1dbe3, 0x88004815, 0x2300b928, 0x4920220c, 0xf7e94820, 0xf04ffa10, 
+    0xe1e10a00, 0xd28e007a, 0xd00351ea, 0x00038a44, 0x00038a46, 0x00038a48, 0x00038a4a, 0x00038a4c, 
+    0x00038a4e, 0x00038a50, 0x00038a52, 0x00038a54, 0x000362b1, 0xd0034200, 0xd003086e, 0xd1800000, 
+    0x000362b0, 0x000361cc, 0x0003626a, 0x000362b4, 0x000362bc, 0x00044b08, 0x00044308, 0x0002f9b0, 
+    0x0004c990, 0x0004c9a4, 0x0004c9b8, 0x0004caf8, 0x00038a58, 0x000361ee, 0xfffff000, 0xd0030a04, 
+    0x780048d4, 0x48d4b920, 0x0000f990, 0xd0734582, 0x780048d2, 0xd0072801, 0x780048d1, 0xd0032801, 
+    0x780048d0, 0xd1022801, 0xe8bdb00d, 0x48ce8ff0, 0x230149ce, 0xe9cd2200, 0xfa4f1000, 0x4618f18a, 
+    0xfe3ff7e8, 0x46252400, 0x46372600, 0xe03446a3, 0x008aeb0a, 0xeb0149c6, 0xeb001000, 0xc80600cb, 
+    0xf93048c4, 0x4bc0001b, 0x0010f933, 0x7ce0ea4f, 0x3e00fba1, 0xe000fb02, 0x000cfb01, 0x4145191c, 
+    0x008aeb0a, 0xeb0149bc, 0xeb001000, 0xe9d000cb, 0x48b82100, 0x001bf930, 0xf9334bb4, 0xea4f0010, 
+    0xfba27ce0, 0xfb013e00, 0xfb02e000, 0x199e000c, 0xf10b4147, 0xf0000001, 0x98060bff, 0xdbc74583, 
+    0xeb651ba4, 0xf06f0507, 0x20004100, 0x41a81b09, 0xf06fda02, 0xe0054400, 0x1a6149a8, 0x30fff175, 
+    0x4ca6da00, 0xf840a809, 0xa909402a, 0x002af851, 0xdb022800, 0xe0014601, 0x4241e122, 0x42919a08, 
+    0xa809dd71, 0x002af850, 0xda3b2800, 0x499c20ff, 0x489c7008, 0xbb308800, 0x7800489b, 0xd0032805, 
+    0x78004899, 0xd10f2804, 0xf8304898, 0x1c40001a, 0x4996b200, 0x001af821, 0xf9304608, 0xfa4f101a, 
+    0xf00cf08a, 0xe0f5fee1, 0xf8304890, 0x1e40001a, 0x498eb200, 0x001af821, 0x0101f06f, 0xf08afa4f, 
+    0xf874f7f0, 0x4889e0e6, 0x001af830, 0xb2001e40, 0xf8214986, 0xf06f001a, 0xfa4f0101, 0xf7f0f08a, 
+    0xe0d7f865, 0xf850a809, 0x2800002a, 0x2001dddb, 0x7008497b, 0x8800487b, 0x487bbb30, 0x28057800, 
+    0x4879d003, 0x28047800, 0x4878d10f, 0x001af830, 0xb2001e40, 0xf8214975, 0x4608001a, 0x101af930, 
+    0xf08afa4f, 0xfea0f00c, 0x4870e0b4, 0x001af830, 0xb2001c40, 0xf821496d, 0x2102001a, 0xf08afa4f, 
+    0xf834f7f0, 0xe00de0a6, 0xf8304868, 0x1c40001a, 0x4966b200, 0x001af821, 0xfa4f2102, 0xf7f0f08a, 
+    0xe097f825, 0xf9924a5e, 0x29001000, 0x460adb01, 0x424ae000, 0xdd7b2a00, 0xf852aa09, 0x2800002a, 
+    0x4602db01, 0x4242e000, 0x429a9b07, 0xa809dd7f, 0x002af850, 0xda382800, 0x88004852, 0x4852bb30, 
+    0x28057800, 0x4850d003, 0x28047800, 0x484fd10f, 0x001af830, 0xb2001c40, 0xf821494c, 0x4608001a, 
+    0x101af930, 0xf08afa4f, 0xfe4ef00c, 0x4847e062, 0x001af830, 0xb2001e40, 0xf8214944, 0xf06f001a, 
+    0xfa4f0101, 0xf7eff08a, 0xe053ffe1, 0xf830483f, 0x1e40001a, 0x493db200, 0x001af821, 0x0101f06f, 
+    0xf08afa4f, 0xffd2f7ef, 0xa809e044, 0x002af850, 0xdc3f2800, 0xf850a809, 0x2800002a, 0x4831dd3a, 
+    0xbb308800, 0x78004830, 0xd0032805, 0x7800482e, 0xd10f2804, 0xf830482d, 0x1e40001a, 0x492bb200, 
+    0x001af821, 0xf9304608, 0xfa4f101a, 0xf00cf08a, 0xe01ffe0b, 0xf8304825, 0x1c40001a, 0x4923b200, 
+    0x001af821, 0xfa4f2102, 0xf7eff08a, 0xe011ff9f, 0x481ee00d, 0x001af830, 0xb2001c40, 0xf821491b, 
+    0x2102001a, 0xf08afa4f, 0xff90f7ef, 0x2000e002, 0x70084913, 0xf850a809, 0x4915002a, 0x002af841, 
+    0x0001f10a, 0x0afff000, 0x0f04f1ba, 0xae58f6ff, 0xe669bf00, 0x000361ee, 0x000362b1, 0x00036344, 
+    0x00038b56, 0x00038b57, 0x00044b08, 0x00044308, 0x0004c9b8, 0x0002f9b0, 0x0004caf8, 0x80000001, 
+    0x00038a58, 0x000361cc, 0x0003626a, 0x000362b4, 0x00043000, 0x41f0e92d, 0x460d4604, 0x46b82700, 
+    0xd2252c09, 0xf004e8df, 0x100d0905, 0x1c182514, 0x27090020, 0x0800f04f, 0x2708e01f, 0x0801f04f, 
+    0x2700e01b, 0xe01846b8, 0xf04f2701, 0xe0140800, 0xf04f2704, 0xe0100800, 0xf04f2702, 0xe00c0800, 
+    0xf04f2705, 0xe0080800, 0xf04f2706, 0xe0040800, 0x2703bf00, 0x0800f04f, 0xbf00bf00, 0x4813b12d, 
+    0xf9ccf7e2, 0x060ff000, 0x463ee000, 0xea400228, 0xea401007, 0x480d0106, 0xf9c6f7e2, 0xf388fa1f, 
+    0x21012200, 0x30404809, 0xffb9f7e8, 0x81f0e8bd, 0x4604b510, 0x46202100, 0xffacf7ff, 0xb510bd10, 
+    0x21014604, 0xf7ff4620, 0xbd10ffa5, 0xd0030460, 0x41f0e92d, 0x460d4606, 0x2c014614, 0x2c02d001, 
+    0x2170d111, 0x0080f44f, 0xfa8cf7e2, 0xf7ec4630, 0x2000fcba, 0xffdaf7eb, 0x49222001, 0x22007008, 
+    0xf7ebb269, 0x2c02ffdd, 0x2100d103, 0xf7ea0460, 0xb10cfa0b, 0xd1322c02, 0xb2692200, 0xf7eb4610, 
+    0x2000ffcf, 0x70084917, 0xf44f2171, 0xf7e20080, 0x2200fa69, 0x71fff240, 0xf7e84813, 0x4607ff87, 
+    0xf44f4639, 0xf7e20080, 0x4810fa0d, 0xf4006800, 0xb1a00080, 0x6800480e, 0x480eb988, 0xf2406800, 
+    0x428871fe, 0x490cda0b, 0x68124a0a, 0x0082eb01, 0xf807f7ec, 0x68004807, 0x49061c80, 0x20016008, 
+    0x81f0e8bd, 0x00038a5a, 0xd0030430, 0x0005280c, 0x000362f4, 0x00052800, 0x00050800, 0x48feb510, 
+    0xf93cf7e2, 0x1111f241, 0xf4404388, 0xf0405088, 0x1c440010, 0x48f84621, 0xf936f7e2, 0xb510bd10, 
+    0x461a2301, 0x48f42102, 0xff29f7e8, 0x22052301, 0x48f12120, 0xff23f7e8, 0x22092301, 0x48ee0259, 
+    0xff1df7e8, 0x220d2301, 0x48eb0359, 0xff17f7e8, 0x22012300, 0x48e82102, 0xff11f7e8, 0x22052300, 
+    0x48e52120, 0xff0bf7e8, 0x22092300, 0x2100f240, 0xf7e848e1, 0x2300ff04, 0xf242220d, 0x48de0100, 
+    0xfefdf7e8, 0xb570bd10, 0x48dc4604, 0xf8f6f7e2, 0x00e0f020, 0x1544ea40, 0x48d94629, 0xf8f4f7e2, 
+    0xb510bd70, 0x46234604, 0x21072200, 0xf7e848d5, 0xbd10fee6, 0x2300b510, 0x49d3220f, 0xf7e848d1, 
+    0x2301fede, 0x49d0220f, 0xf7e848ce, 0x2300fed8, 0x49cd220f, 0xf7e848cb, 0xbd10fed2, 0x4604b570, 
+    0x2c01460d, 0xb92cd000, 0x2204462b, 0x48c72130, 0xfec5f7e8, 0xd0002c02, 0x462bb934, 0x21302204, 
+    0x308048c2, 0xfebbf7e8, 0xb570bd70, 0x460c4606, 0x2e014615, 0xb9ded000, 0xd0002c01, 0x0c28b954, 
+    0x48bab201, 0xf7e21d00, 0xb229f8af, 0x1d8048b7, 0xf8aaf7e2, 0xd0002c02, 0x0c28b954, 0x48b3b201, 
+    0xf7e23008, 0xb229f8a1, 0x300a48b0, 0xf89cf7e2, 0xd0002e02, 0x2c01b9de, 0xb954d000, 0xb2010c28, 
+    0x308448aa, 0xf890f7e2, 0x48a8b229, 0xf7e23086, 0x2c02f88b, 0xb954d000, 0xb2010c28, 0x308848a3, 
+    0xf882f7e2, 0x48a1b229, 0xf7e2308a, 0xbd70f87d, 0x4605b570, 0x2d01b135, 0x2d02d00b, 0x2d03d010, 
+    0xe014d11c, 0x21032200, 0xf7e84899, 0xb244fe7f, 0x2202e014, 0x4896210c, 0xfe78f7e8, 0xe00db244, 
+    0x21302204, 0xf7e84892, 0xb244fe71, 0x2206e006, 0x488f21c0, 0xfe6af7e8, 0xbf00b244, 0xb2e0bf00, 
+    0xb570bd70, 0x48854604, 0xf7e21c80, 0xf364f847, 0x46050000, 0x48824629, 0xf7e21c80, 0xb954f845, 
+    0x1c80487e, 0xf83af7e2, 0x0502f020, 0x487c4629, 0xf7e21c80, 0xbd70f839, 0x4878b510, 0xf7e21c80, 
+    0xf020f82d, 0x1c840002, 0x48754621, 0xf7e21c80, 0x4872f82b, 0xf7e21c80, 0xf020f821, 0x46210402, 
+    0x1c80486f, 0xf820f7e2, 0xe92dbd10, 0x460641ff, 0x4615460c, 0xcb0f4b6f, 0x000fe88d, 0xf7ff4630, 
+    0x4607ff97, 0x1027f85d, 0x0044eb01, 0xf7e24629, 0xe8bdf80b, 0xb57081ff, 0x48604604, 0xf7e11c80, 
+    0xf420fffd, 0xf04060e2, 0xf2400010, 0xea017100, 0xea402104, 0x46290501, 0x1c804859, 0xfff4f7e1, 
+    0xb510bd70, 0x2c014604, 0xb92cd000, 0x22002301, 0x48564619, 0xfde3f7e8, 0xd0002c02, 0x2301b934, 
+    0x46192200, 0x30804851, 0xfdd9f7e8, 0xe92dbd10, 0x460441f0, 0x4616460d, 0xb2a3461f, 0x21032200, 
+    0xf7e8484b, 0xb2abfdcc, 0x210c2202, 0xf7e84848, 0xb2b3fdc6, 0x21302204, 0xf7e84845, 0xb2bbfdc0, 
+    0x21c02206, 0xf7e84842, 0xe8bdfdba, 0xb51081f0, 0x22002301, 0x48404619, 0xfdb1f7e8, 0x22002301, 
+    0x483e4619, 0xfdabf7e8, 0x22002301, 0x483c4619, 0xfda5f7e8, 0x22002301, 0x48314619, 0xf7e838c0, 
+    0x2301fd9e, 0x2102461a, 0xf7e84833, 0x2301fd98, 0x2102461a, 0xf7e84831, 0x2301fd92, 0x2102461a, 
+    0xf7e8482f, 0x2301fd8c, 0x2102461a, 0x38c04824, 0xfd85f7e8, 0x220c2301, 0x4827492a, 0xfd7ff7e8, 
+    0x220c2301, 0x48254927, 0xfd79f7e8, 0x220c2301, 0x48234924, 0xfd73f7e8, 0x220c2301, 0x48184921, 
+    0xf7e838c0, 0x2300fd6c, 0x21042202, 0xf7e8481a, 0x2300fd66, 0x21042202, 0xf7e84818, 0x2300fd60, 
+    0x21042202, 0xf7e84816, 0x2300fd5a, 0x21042202, 0x38c0480b, 0xfd53f7e8, 0x78004813, 0xb2831e40, 
+    0x21702204, 0xf7e8480c, 0x480ffd4a, 0x1e407800, 0x2204b283, 0xe0192170, 0xd03c8000, 0xd0033040, 
+    0xd0033840, 0xd0033a00, 0xffff8000, 0xd0033b00, 0xd0035026, 0x0002fb50, 0xd0033180, 0xd0033380, 
+    0xd0033580, 0xfffff000, 0x000384e3, 0xf7e84881, 0x4881fd26, 0x1e407800, 0x2204b283, 0x487f2170, 
+    0xfd1df7e8, 0x7800487c, 0xb2831e40, 0x21702204, 0xf7e8487b, 0x231efd14, 0xf6432208, 0x48797100, 
+    0xfd0df7e8, 0x2208231e, 0x7100f643, 0x1c804871, 0xfd05f7e8, 0x2208231e, 0x7100f643, 0x1c80486f, 
+    0xfcfdf7e8, 0x2208231e, 0x7100f643, 0x1c80486c, 0xfcf5f7e8, 0xf7ff2000, 0x4604fe7b, 0x22004623, 
+    0x48682103, 0xf7e81c80, 0x2001fcea, 0xfe70f7ff, 0x46234604, 0x21032200, 0x1d00485e, 0xfcdff7e8, 
+    0xf7ff2002, 0x4604fe65, 0x22004623, 0x485b2103, 0xf7e81d00, 0x2003fcd4, 0xfe5af7ff, 0x46234604, 
+    0x21032200, 0x1d004856, 0xfcc9f7e8, 0x22032301, 0x48542108, 0xf7e81e80, 0x2301fcc2, 0x21082203, 
+    0xf7e8484c, 0x2301fcbc, 0x21082203, 0xf7e8484b, 0x2301fcb6, 0x21082203, 0xf7e84849, 0x2300fcb0, 
+    0x21082203, 0x1e804847, 0xfca9f7e8, 0x22032300, 0x48402108, 0xfca3f7e8, 0x22032300, 0x483f2108, 
+    0xfc9df7e8, 0x22032300, 0x483d2108, 0xfc97f7e8, 0xb510bd10, 0x483b2100, 0xf7e11e80, 0x2100fe95, 
+    0xf7e14834, 0x2100fe91, 0xf7e14834, 0x2100fe8d, 0xf7e14833, 0xf242fe89, 0x48320100, 0xfe84f7e1, 
+    0x0100f242, 0x1c80482b, 0xfe7ef7e1, 0x0100f242, 0x1c80482a, 0xfe78f7e1, 0x0100f242, 0x1c804828, 
+    0xfe72f7e1, 0x48272100, 0xf7e11c80, 0x2100fe6d, 0x1d004820, 0xfe68f7e1, 0x48202100, 0xf7e11d00, 
+    0x2100fe63, 0x1d00481e, 0xfe5ef7e1, 0x22032301, 0x481c2108, 0xf7e81e80, 0x2301fc52, 0x21082203, 
+    0xf7e84814, 0x2301fc4c, 0x21082203, 0xf7e84813, 0x2301fc46, 0x21082203, 0xf7e84811, 0x2300fc40, 
+    0x21082203, 0x1e80480f, 0xfc39f7e8, 0x22032300, 0x48082108, 0xfc33f7e8, 0x22032300, 0x48072108, 
+    0xfc2df7e8, 0x22032300, 0x48052108, 0xfc27f7e8, 0x0000bd10, 0xd0033380, 0x000384e3, 0xd0033580, 
+    0xd0033780, 0xd0033182, 0x2102b510, 0xf7e148fd, 0xf240fe1b, 0x48fb1103, 0xf7e11c80, 0xbd10fe15, 
+    0x2300b570, 0x2107461a, 0xf7e848f7, 0x2300fc08, 0x21782203, 0xf7e848f4, 0x2300fc02, 0xf2402207, 
+    0x48f17180, 0xfbfbf7e8, 0x7100f240, 0xf7e148ef, 0x49effdfb, 0x1d0048ed, 0xfdf6f7e1, 0x220e2300, 
+    0x48e949ec, 0xf7e83816, 0x2309fbea, 0xf6432208, 0x48e57100, 0xf7e8381e, 0x2303fbe2, 0x46192200, 
+    0x381448e1, 0xfbdbf7e8, 0xf7e148e3, 0xb286fdd7, 0x22002303, 0x48dc4619, 0xf7e83830, 0x2303fbd0, 
+    0x2118461a, 0x383048d8, 0xfbc9f7e8, 0x5000f406, 0xd07d2800, 0x220e2303, 0x48d349d6, 0xf7e8382a, 
+    0x230cfbbe, 0x21ff2200, 0x382848cf, 0xfbb7f7e8, 0x22082302, 0x7100f640, 0x382848cb, 0xfbaff7e8, 
+    0x220f2301, 0x48c849ca, 0xf7e83826, 0x2300fba8, 0xf643220a, 0x48c44100, 0xf7e83816, 0xf640fba0, 
+    0x220043cc, 0x71fff643, 0x382a48bf, 0xfb97f7e8, 0x220a2333, 0x48bc49c1, 0xf7e8382c, 0x2300fb90, 
+    0x21402206, 0x381e48b8, 0xfb89f7e8, 0x220e2301, 0x48b549b8, 0xf7e83830, 0x2342fb82, 0x217f2200, 
+    0x381a48b1, 0xfb7bf7e8, 0x220c2301, 0x48ae49b4, 0xf7e83818, 0x2310fb74, 0xf6402202, 0x48aa71fc, 
+    0xf7e83818, 0x230bfb6c, 0xf643220a, 0x48a64100, 0xf7e8381a, 0x2303fb64, 0x01d12207, 0x381a48a2, 
+    0xfb5df7e8, 0x220e2303, 0x489f49a2, 0xf7e8381e, 0x2300fb56, 0x210c2202, 0x381c489b, 0xfb4ff7e8, 
+    0x22002301, 0x48982103, 0xf7e8381c, 0xe000fb48, 0x2303e00e, 0x21302204, 0x381c4893, 0xfb3ff7e8, 
+    0x22022300, 0x4890210c, 0xf7e83824, 0xe09ffb38, 0x2206230a, 0x31c0f240, 0x382e488b, 0xfb2ff7e8, 
+    0x22032305, 0x48882138, 0xf7e8382e, 0x2300fb28, 0x4988220e, 0x382a4884, 0xfb21f7e8, 0x2200230a, 
+    0x488121ff, 0xf7e83828, 0x2300fb1a, 0xf6402208, 0x487d7100, 0xf7e83828, 0x2301fb12, 0x497c220f, 
+    0x38264879, 0xfb0bf7e8, 0x220a2300, 0x4100f643, 0x38164875, 0xfb03f7e8, 0x461a2300, 0x71fff643, 
+    0x382a4871, 0xfafbf7e8, 0x220a2300, 0x486e4973, 0xf7e8382c, 0x2300faf4, 0x21402206, 0x381e486a, 
+    0xfaedf7e8, 0x220e2301, 0x4867496a, 0xf7e83830, 0x2342fae6, 0x217f2200, 0x381a4863, 0xfadff7e8, 
+    0x220c2301, 0x48604966, 0xf7e83818, 0x2310fad8, 0xf6402202, 0x485c71fc, 0xf7e83818, 0x230bfad0, 
+    0xf643220a, 0x48584100, 0xf7e8381a, 0x2303fac8, 0x01d12207, 0x381a4854, 0xfac1f7e8, 0x220e2303, 
+    0x48514954, 0xf7e8381e, 0x2300faba, 0x210c2202, 0x381c484d, 0xfab3f7e8, 0x22002301, 0x484a2103, 
+    0xf7e8381c, 0x2303faac, 0x21302204, 0x381c4846, 0xfaa5f7e8, 0x22022300, 0x4843210c, 0xf7e83824, 
+    0x2301fa9e, 0x21042202, 0x381e483f, 0xfa97f7e8, 0x1103f240, 0x1c80483b, 0xfc96f7e1, 0x48412100, 
+    0xfc92f7e1, 0x461a2300, 0x48362101, 0xfa87f7e8, 0x04082101, 0xfd08f7e9, 0x48342100, 0xfc84f7e1, 
+    0x48322100, 0xf7e11d00, 0x2101fc7f, 0xf7e90348, 0x2300fcfb, 0x2101461a, 0x3816482b, 0xfa6ff7e8, 
+    0x20042101, 0xfcf0f7e9, 0x22002301, 0x48264619, 0xf7e83816, 0x2300fa64, 0x21022201, 0xf7e84821, 
+    0x2101fa5e, 0xf7e90348, 0x2301fcdf, 0x2102461a, 0xf7e8481c, 0x2101fa54, 0xf7e90408, 0x2501fcd5, 
+    0xe00706ac, 0xf7e94620, 0x4604fccd, 0xdc012c00, 0xe0232500, 0xf241220c, 0x48130100, 0xf7e83010, 
+    0x2800fa55, 0x220cd0ee, 0x0100f241, 0x3012480e, 0xfa4cf7e8, 0xd0e52800, 0xf242220d, 0x480a0100, 
+    0xf7e83010, 0x2800fa43, 0x220ed0dc, 0x0100f244, 0x30104805, 0xfa3af7e8, 0xd0d32800, 0x4628bf00, 
+    0x0000bd70, 0xd0034000, 0xd003e830, 0xd03c8308, 0xffff8000, 0xffffc000, 0xd03c8038, 0xfffffc00, 
+    0xfffff000, 0xd0039004, 0x496cb538, 0xf7e1486c, 0x2100fc0b, 0xf7e1486b, 0x220cfc07, 0x0100f241, 
+    0x38804867, 0xfa12f7e8, 0x0001f000, 0x2301b138, 0x2102461a, 0x1f804863, 0xf9f1f7e8, 0x2300e006, 
+    0x21022201, 0x1f80485f, 0xf9e9f7e8, 0x7800485e, 0x0401f000, 0x2101e07f, 0xf7e1485a, 0x4859fbe5, 
+    0xf7e13008, 0xf000fbdb, 0xb1880001, 0x48552100, 0xfbdaf7e1, 0xd10a2c01, 0xfc56f7e1, 0x010ff000, 
+    0xfa002001, 0x4601f501, 0xf7e94628, 0xe062fc4d, 0x21012200, 0x1f00484b, 0xf9d8f7e8, 0xd01d42a0, 
+    0xfda2f7ff, 0x2200b964, 0x48462101, 0xf7e81d80, 0xb205f9cd, 0x48434629, 0xf7e11f00, 0xe00dfbb5, 
+    0x21012200, 0x1d80483f, 0xf9c0f7e8, 0xea212101, 0x46290500, 0x1f00483b, 0xfba6f7e1, 0xf241220c, 
+    0x483a0100, 0xf9b2f7e8, 0x220cb170, 0x0100f241, 0x1c804836, 0xf9aaf7e8, 0x220db130, 0x0100f242, 
+    0xf7e84832, 0xb9e0f9a3, 0x4931e004, 0x3808482d, 0xfb8af7e1, 0xfd74f7ff, 0xd0f62800, 0x21012200, 
+    0x1f004828, 0xf992f7e8, 0x492ab928, 0x1d004825, 0xfb7af7e1, 0x4927e005, 0x48221c49, 0xf7e11d00, 
+    0x2103fb73, 0x3808481f, 0xfb6ef7e1, 0x481d2100, 0xfb6af7e1, 0xe77ee000, 0x4918bf00, 0x48181c49, 
+    0xfb62f7e1, 0x22062301, 0x481b2140, 0xf957f7e8, 0x22052300, 0x48192120, 0xf951f7e8, 0xf647200f, 
+    0xf2473395, 0x49160202, 0x48169000, 0xfdeef7ec, 0x05082101, 0xfbc8f7e9, 0x22042300, 0x48122110, 
+    0xf93df7e8, 0x22042301, 0x480f2110, 0xf937f7e8, 0x02482101, 0xfbb8f7e9, 0x0000bd38, 0xffffbbb1, 
+    0xd03c80b8, 0xd003400e, 0x000361d8, 0xd003e840, 0xffffdead, 0xffffd1e0, 0xd03c830e, 0xd0034228, 
+    0xffffaa02, 0xffffa14d, 0xd0039000, 0x2400b510, 0x490ae007, 0xfb022202, 0x21001004, 0xfb14f7e1, 
+    0x2c301c64, 0xbd10dbf5, 0xf7ffb510, 0x2000ffef, 0xfc89f7ee, 0xf7ee2000, 0xbd10fc17, 0xd003e200, 
+    0x47f0e92d, 0x4682b090, 0x496b2230, 0xf00da804, 0x4b69eae6, 0xcb0f3330, 0x000fe88d, 0x0900f04f, 
+    0xf9cff7f9, 0x78054865, 0x68074865, 0x78004865, 0xd1132803, 0x68004864, 0xd3062812, 0x68004860, 
+    0x61f7f64d, 0x14074348, 0x485de005, 0xf64e6800, 0x434861ea, 0xf04f1407, 0xe00f0900, 0x78004859, 
+    0xd1022805, 0x0901f04f, 0x4856e008, 0x28047800, 0xf04fd102, 0xe0010902, 0x0900f04f, 0x70fff643, 
+    0xdb004287, 0x26001e47, 0xa804e00b, 0x1009eb00, 0x0107f1c6, 0x0011f930, 0xdd0042b8, 0x1c70e003, 
+    0x2e08b206, 0xbf00dbf1, 0x0007f1c6, 0x5010f81d, 0x78004844, 0xd11e2804, 0xda122d0c, 0x78004843, 
+    0x483eb168, 0x280f7800, 0x2407da01, 0x483be060, 0x28197800, 0x2406da01, 0x2405e05a, 0x2402e058, 
+    0x2d41e056, 0x2402da01, 0x2d4be052, 0x2401da01, 0x2400e04e, 0x4833e04c, 0x28057800, 0x2d0cd11e, 
+    0x4832da12, 0xb1687800, 0x7800482c, 0xda01280f, 0xe03d2407, 0x78004829, 0xda012819, 0xe0372406, 
+    0xe0352405, 0xe0332402, 0xda012d41, 0xe02f2402, 0xda012d4b, 0xe02b2401, 0xe0292400, 0xda122d0c, 
+    0x78004822, 0x481db168, 0x280f7800, 0x2407da01, 0x481ae01e, 0x28197800, 0x2406da01, 0x2405e018, 
+    0x2405e016, 0x2d23e014, 0x2405da01, 0x2d2de010, 0x2404da01, 0x2d37e00c, 0x2403da01, 0x2d41e008, 
+    0x2402da01, 0x2d4be004, 0x2401da01, 0x2400e000, 0xda042c06, 0x7800480e, 0xd1002801, 0xf04f2406, 
+    0x45440800, 0x4640da01, 0x4620e000, 0x4620b244, 0xe8bdb010, 0x000087f0, 0x0002fb60, 0x00036226, 
+    0x000384dc, 0x0003626a, 0x000361dc, 0x00038464, 0x00038465, 0x2004b510, 0xfdcff7ec, 0xf7ec2004, 
+    0xf7fdfe66, 0x2000fbc9, 0xf90df7ff, 0xb51cbd10, 0xf7ee2007, 0x48f6fba6, 0x0000f990, 0xfdeaf7ed, 
+    0x46082101, 0xfcecf7ec, 0x23172000, 0x7203f647, 0x4100f640, 0x00889000, 0xfc98f7ec, 0x48ed2102, 
+    0xf9f2f7e1, 0x7131f640, 0xf7e148eb, 0x2000f9ed, 0x46032101, 0xe9cd460a, 0x46011000, 0xf7ea2001, 
+    0x2016fc27, 0x600849e5, 0xe92dbd1c, 0x460647fc, 0x8eb04689, 0xd07d28b2, 0xb158dc05, 0xd0182876, 
+    0xd1782877, 0x28b3e021, 0x28f8d076, 0x28f9d075, 0xe0d7d1f7, 0xf04fe1f3, 0x49d932ff, 0x680048d9, 
+    0xfcacf008, 0x1d204604, 0x2076b950, 0xe8bd86b0, 0x220087fc, 0x48d349d2, 0xf0086800, 0x4604fc9f, 
+    0xb9181d60, 0x86b02077, 0x2401e7f1, 0xd0002c01, 0x48cbe1d5, 0x286e8800, 0x48c9d174, 0x1000f9b0, 
+    0x4220f04f, 0x5080f04f, 0xfa53f7e1, 0x5290f04f, 0x780148c5, 0x5080f04f, 0xfa4bf7e1, 0x780048c2, 
+    0x2000b918, 0xfd60f7ea, 0x48bfe1ad, 0x28017800, 0xf7fbd147, 0xf7fff83c, 0xf7ffff7a, 0x2300ff6b, 
+    0x49ba220f, 0x301a48b4, 0xff79f7e7, 0x21012000, 0x460a4603, 0x1000e9cd, 0xf7ea4608, 0x48b4fbb9, 
+    0xf96cf7e1, 0x800849b3, 0x78004608, 0x000ff000, 0x2001b318, 0x800849b0, 0x49a92005, 0x22008008, 
+    0x680048ae, 0xfc18f008, 0x1d204604, 0x20b2b968, 0xe79c86b0, 0xe183e002, 0xe056e00d, 0x49a02200, 
+    0x680048a6, 0xfc08f008, 0x1d604604, 0xd1bb2800, 0x86b020b3, 0x2401e78b, 0x2000e165, 0x8008499e, 
+    0x4899e161, 0x28027800, 0xf7ffd10d, 0xf7ffff30, 0x2000ff21, 0x46032101, 0xe9cd460a, 0xf7ea1000, 
+    0xe150fb77, 0x4890e159, 0x28037800, 0xf7ffd13c, 0x2300ff1e, 0xf640220b, 0x48910100, 0xff1ff7e7, 
+    0x220c2301, 0x488e0319, 0xff19f7e7, 0xf7ec2004, 0x2004fc87, 0xfd1ef7ec, 0x1137f640, 0xf7e1487e, 
+    0x2000f913, 0xf99df7fd, 0x49862001, 0x20057008, 0x8008497b, 0x48812200, 0xf0086800, 0x4604fbbd, 
+    0xb9481d20, 0x86b020f8, 0x2200e741, 0x487b4974, 0xf0086800, 0x4604fbb1, 0x28001d60, 0x20f9d1ac, 
+    0xe73486b0, 0xe10e2401, 0x7800486f, 0xd16d2804, 0xfeddf7ff, 0xfecef7ff, 0x78004865, 0xd1012805, 
+    0xe0062501, 0x78004862, 0xd1012804, 0xe0002502, 0x486d2500, 0x28017800, 0xf241d108, 0xfa407080, 
+    0xf641f705, 0xfa402080, 0xe035f805, 0x78004866, 0xd1082802, 0x2080f243, 0xf705fa40, 0x3080f243, 
+    0xf805fa40, 0x4860e028, 0x28047800, 0xf645d108, 0xfa401080, 0xf645f705, 0xfa402080, 0xe01bf805, 
+    0x78004859, 0xd1082805, 0x2080f648, 0xf705fa40, 0x4080f648, 0xf805fa40, 0x4853e00e, 0x28067800, 
+    0xf24cd108, 0xfa406080, 0xf64cf705, 0xfa400080, 0xe001f805, 0x46b82700, 0xffacf7fe, 0xf7fe2003, 
+    0x2004ff92, 0xff9df7fe, 0x46082100, 0xffb6f7fe, 0x2101463a, 0xf7fe2000, 0x4642ffc8, 0x20002102, 
+    0xffc3f7fe, 0xf7ff2000, 0xe09cf88c, 0x78004836, 0xd17b2805, 0xfe6bf7ff, 0xfe5cf7ff, 0xf83cf7ff, 
+    0x21002240, 0xf7ff4608, 0x220df850, 0x20002101, 0xf84bf7ff, 0x21022205, 0xf7ff2000, 0x2240f846, 
+    0x20012100, 0xf841f7ff, 0x2101220d, 0xf7ff4608, 0x2205f83c, 0x20012102, 0xf837f7ff, 0x21002240, 
+    0xf7ff2002, 0x220df832, 0x20022101, 0xf82df7ff, 0x21022205, 0xf7ff4608, 0x2240f828, 0x20032100, 
+    0xf823f7ff, 0x2101220d, 0xf7ff2003, 0x2205f81e, 0x20032102, 0xf819f7ff, 0xf7fe2000, 0x2003ffe2, 
+    0xf829f7ff, 0x21002001, 0x460a4603, 0x1000e9cd, 0xf7ea4601, 0x2001fa6d, 0x46032100, 0xe9cd460a, 
+    0x21021000, 0xfa64f7ea, 0xff6ef7fc, 0xe01de03b, 0x0003626a, 0xd03c8304, 0xd003502a, 0x000361dc, 
+    0x00038aa0, 0x00038a9c, 0x0003625c, 0xffff8000, 0xd0035136, 0x0003631a, 0x0003631e, 0x00038654, 
+    0xd28fffd2, 0x000362b1, 0x0003625d, 0x7800483e, 0xd1112806, 0xfdebf7ff, 0xfddcf7ff, 0x7131f640, 
+    0xf7e0483a, 0x2000fff1, 0x46032101, 0xe9cd460a, 0xf7ea1000, 0xe006fa2d, 0x78004833, 0xd1022807, 
+    0xf7ea2001, 0x4830fbb1, 0x28077800, 0x482ed006, 0xb1187800, 0xfea3f7fe, 0xe000e000, 0xe60abf00, 
+    0xbf00bf00, 0xb510e613, 0x21012200, 0x4025f2af, 0xf815f008, 0x20022108, 0xf9b2f008, 0x60084924, 
+    0xb51cbd10, 0xf7e92000, 0x2000ffa4, 0xf849f7fd, 0xf7ee2004, 0x2000fe03, 0xfeb5f7fe, 0xf7ea2000, 
+    0x2000f9ec, 0x46032101, 0xe9cd460a, 0xf7ea1000, 0x4818f9ef, 0xb9207800, 0x48172177, 0xffa4f7e0, 
+    0x4816e010, 0x28017800, 0x4814d003, 0x28037800, 0x2177d104, 0xf7e04810, 0xe003ff97, 0x480e21ee, 
+    0xff92f7e0, 0x03082101, 0xf80ef7e9, 0x0050f242, 0xf89cf7e1, 0x04082101, 0xf806f7e9, 0x0050f242, 
+    0xf894f7e1, 0x0000bd1c, 0x0003625c, 0xd003502a, 0x00038a9c, 0x00038488, 0xd0034220, 0x000361d8, 
+    0xb5704770, 0x48fa4604, 0x600849fa, 0xfb4df7e7, 0x1000f240, 0xfb53f7e7, 0x22072300, 0x48f62180, 
+    0xfd5df7e7, 0x461a2300, 0x48f42101, 0xfd57f7e7, 0x46112201, 0xf7f94610, 0x2300ff45, 0x21082203, 
+    0xf7e748ef, 0x2300fd4c, 0x21082203, 0x1c8048ec, 0xfd45f7e7, 0x22032300, 0x48e92108, 0xf7e71d00, 
+    0x2300fd3e, 0x21082203, 0x1d8048e5, 0xfd37f7e7, 0x22022300, 0x48e22104, 0xfd31f7e7, 0x22012300, 
+    0x48df2102, 0xfd2bf7e7, 0x461a2300, 0x48dc2101, 0xfd25f7e7, 0x22022300, 0x48d92104, 0xf7e71c80, 
+    0x2300fd1e, 0x21022201, 0x1c8048d5, 0xfd17f7e7, 0x461a2300, 0x48d22101, 0xf7e71c80, 0x2300fd10, 
+    0x21042202, 0x1d0048ce, 0xfd09f7e7, 0x22012300, 0x48cb2102, 0xf7e71d00, 0x2300fd02, 0x2101461a, 
+    0x1d0048c7, 0xfcfbf7e7, 0x22022300, 0x48c42104, 0xf7e71d80, 0x2300fcf4, 0x21022201, 0x1d8048c0, 
+    0xfcedf7e7, 0x461a2300, 0x48bd2101, 0xf7e71d80, 0x2300fce6, 0x01512208, 0xf7e748ba, 0x2600fcb9, 
+    0x2500e00e, 0x4bb8e009, 0x3015f813, 0xb25a425b, 0xb2f0b2e9, 0xfeb9f7fe, 0x2d101c6d, 0x1c76dbf3, 
+    0xdbee2e04, 0xf7fe2000, 0x2003fe7c, 0xfec3f7fe, 0x461a2300, 0x48a82101, 0xf7e730a0, 0x2000fcc0, 
+    0x80c849aa, 0x80488088, 0x46088008, 0xfd88f7ea, 0x1000f240, 0x80c849a6, 0x80488088, 0x46088008, 
+    0xfcb2f7ea, 0x46082100, 0xf8c3f7ea, 0x20012100, 0xf8adf7ea, 0xf7ea2001, 0x2300f8e0, 0xf240461a, 
+    0x46085174, 0xfa7af7ea, 0x5080f404, 0x2007b108, 0x2000e000, 0x22054603, 0x489621e0, 0xfc8ff7e7, 
+    0x5000f404, 0x2007b108, 0x2000e000, 0x22054603, 0x489121e0, 0xfc83f7e7, 0x4080f404, 0x2007b108, 
+    0x2000e000, 0x22054603, 0x488c21e0, 0xfc77f7e7, 0x4000f404, 0x2007b108, 0x2000e000, 0x22054603, 
+    0x488721e0, 0xfc6bf7e7, 0xb510bd70, 0x46204604, 0xfef7f7ff, 0xb570bd10, 0x4605b088, 0xe0042400, 
+    0xa9042000, 0x0024f841, 0x2c041c64, 0x2600dbf8, 0x2101e015, 0xf7e803c8, 0x4668fed7, 0xfe78f7e0, 
+    0xe0092400, 0xf850a804, 0xf85d0024, 0x44081024, 0xf841a904, 0x1c640024, 0xdbf32c04, 0x2e401c76, 
+    0x2400dbe7, 0xa804e007, 0x0024f850, 0x11803020, 0x0024f845, 0x2c041c64, 0xf105dbf5, 0xb0080010, 
+    0xb5f0bd70, 0x46144603, 0x460a2000, 0xf933e005, 0xfb166012, 0x4428f506, 0x190f1c52, 0xdcf64297, 
+    0xe92dbdf0, 0x46044ffe, 0x38084856, 0xfe0cf7e0, 0x23009002, 0x2101461a, 0x38084852, 0xfbe8f7e7, 
+    0x4850bf00, 0xf7e03808, 0xf000fdff, 0x28000001, 0x4f54d1f7, 0xe0752600, 0x463b2000, 0xb2714602, 
+    0xf7e79000, 0x2000f8b2, 0x46829001, 0x25004683, 0xf937e013, 0xf1b88015, 0xdb010f00, 0xe0014640, 
+    0x0000f1c8, 0xf980fa0f, 0x45819801, 0xf8cddd03, 0x46c29004, 0x1c6846ab, 0x2d80b205, 0xf844dbe9, 
+    0xf844ab04, 0x2280bb04, 0x46382100, 0xffa9f7ff, 0x2280c401, 0x46384611, 0xffa3f7ff, 0x2280c401, 
+    0x46380051, 0xff9df7ff, 0x2280c401, 0x1180f240, 0xf7ff4638, 0xc401ff96, 0x00912280, 0xf7ff4638, 
+    0xc401ff90, 0xf2402280, 0x46382180, 0xff89f7ff, 0x2280c401, 0x3100f240, 0xf7ff4638, 0xc401ff82, 
+    0xf2402280, 0x46383180, 0xff7bf7ff, 0x2501c401, 0x2000e014, 0xb26a463b, 0x9000b271, 0xf855f7e7, 
+    0x21002280, 0xf7ff4638, 0xc401ff6c, 0x46112280, 0xf7ff4638, 0xc401ff66, 0xb2051c68, 0xdbe82d04, 
+    0xb2061c70, 0xdb872e04, 0x3808480e, 0xf7e09902, 0x4620fd80, 0x8ffee8bd, 0x41f0e92d, 0x460c4605, 
+    0xeb004811, 0x2c001845, 0x2018db20, 0x0000e01f, 0x00054000, 0x00038ac8, 0xd0030400, 0xd0031012, 
+    0xd0030000, 0xd1800008, 0x00038aa8, 0x00036296, 0x0003628e, 0xd0033040, 0xd0033240, 0xd0033440, 
+    0xd0033640, 0x00043078, 0xd0030882, 0x46072038, 0xda012c00, 0xb2044260, 0x70eff64f, 0x0100ea07, 
+    0xf7e04640, 0x2600fd51, 0x4639e005, 0xf7e04640, 0x1c70fd4b, 0x42a6b206, 0xe8bddbf7, 0xe92d81f0, 
+    0xf5ad47f0, 0x46827d0a, 0xf7ff4650, 0x2001fdca, 0x80c849fe, 0x80488088, 0x46088008, 0xfc00f7ea, 
+    0x04c82101, 0xfdb0f7e8, 0x21072202, 0x10c3f240, 0xfb7ef7fe, 0x461a2300, 0x48f52101, 0xfaf8f7e7, 
+    0x461a2300, 0x48f22101, 0xf7e73830, 0x2000faf1, 0xfb5ef7fe, 0x20002140, 0xfd38f7e9, 0xe0042400, 
+    0xa9402000, 0x0024f841, 0x2c401c64, 0x2400dbf8, 0xf06fe005, 0xa984407f, 0x0024f841, 0x2c041c64, 
+    0xf04fdbf7, 0xe06e0900, 0xe00b2500, 0x0f00f1b9, 0x2040d101, 0xf06fe001, 0x4601003f, 0xf7ffb268, 
+    0x1c6dff6b, 0xdbf12d04, 0x22082302, 0x46082101, 0xfd1ff7e9, 0x4611220b, 0x0000f242, 0xfb36f7e9, 
+    0x4611220c, 0x0000f244, 0xfb30f7e9, 0x4611220d, 0x0000f248, 0xfb2af7e9, 0xf7ff4668, 0xa880feb2, 
+    0xfe69f7ff, 0xe03a2500, 0x1ca0012c, 0x1020f85d, 0xf852aa40, 0x42810020, 0xf85ddd0e, 0xa9400024, 
+    0x0024f841, 0xf85d1c60, 0xf8421020, 0x1ca01020, 0x1020f85d, 0x1020f842, 0xe00f2603, 0xf85d19a0, 
+    0x19a10020, 0xf852aa40, 0x42881021, 0x19a0dd05, 0x0020f85d, 0xf84219a1, 0x1c760021, 0xdded2e0f, 
+    0xf850a884, 0xa9800025, 0x1025f851, 0xdd054288, 0xf850a880, 0xa9840025, 0x0025f841, 0x2d041c6d, 
+    0xf109dbc2, 0xf1b90901, 0xdb8d0f02, 0x680748a9, 0xe0042500, 0xf850a884, 0xc7010025, 0x2d041c6d, 
+    0xa888dbf8, 0xfb2df7ea, 0x0800f04f, 0xa888e005, 0x0018f930, 0xf108c701, 0xf1b80801, 0xdbf60f04, 
+    0xe0052600, 0xf850a840, 0xf8470026, 0x1c760026, 0xdbf72e40, 0x05082101, 0xfce6f7e8, 0x7d0af50d, 
+    0x87f0e8bd, 0x4602b510, 0x2000460b, 0xe00b2100, 0x4011f932, 0xda032c00, 0x4011f932, 0xe0021b00, 
+    0x4011f932, 0x1c494420, 0xdbf14299, 0xb53fbd10, 0x20004603, 0x2400e003, 0x4020f84d, 0x28041c40, 
+    0x2000dbf9, 0xf933e017, 0x9c005010, 0x9400442c, 0xf9331c44, 0x9d014014, 0x9401442c, 0xf9331c84, 
+    0x9d024014, 0x9402442c, 0xf9331cc4, 0x9d034014, 0x9403442c, 0x42881d00, 0x1089dbe5, 0xb2221e94, 
+    0xe0072000, 0x4020f85d, 0x0461eb04, 0xf84d4114, 0x1c404020, 0xdbf52804, 0xe0222000, 0x4010f833, 
+    0x1b649d00, 0xf823b224, 0x1c444010, 0x4014f833, 0x1b649d01, 0x1c44b225, 0x5014f823, 0xf8331c84, 
+    0x9d024014, 0xb2251b64, 0xf8231c84, 0x1cc45014, 0x4014f833, 0x1b649d03, 0x1cc4b225, 0x5014f823, 
+    0x42881d00, 0xbd3fdbda, 0x4ff0e92d, 0x4683b091, 0xf7ff4658, 0x4e58fc76, 0x4500f240, 0x9004200a, 
+    0x461a2300, 0x48522101, 0xf9b2f7e7, 0x461a2300, 0x484f2101, 0xf7e73830, 0x2000f9ab, 0xfa18f7fe, 
+    0x20002140, 0xfbf2f7e9, 0x6807484a, 0x0900f04f, 0x080df04f, 0x0a00f04f, 0xfa0fe195, 0x4943f089, 
+    0x808880c8, 0x80088048, 0xf7ea4608, 0x2101fa89, 0xf7e80508, 0x2004fc39, 0xffbcf7eb, 0x05082101, 
+    0xfc32f7e8, 0x02812001, 0x5000e9cd, 0x1e822300, 0x1002e9cd, 0x46302103, 0xffc6f7fc, 0xe0122400, 
+    0xf105fb04, 0x0041eb06, 0x9a044629, 0xff4ff7ff, 0xf105fb04, 0x0041eb06, 0xf7ff4629, 0xa909ff33, 
+    0x0024f841, 0x2c041c64, 0x2001dbea, 0xe9cd0281, 0x23005000, 0xe9cd1e82, 0x21031002, 0xf7fc4630, 
+    0x2400ffa3, 0xfb04e016, 0xeb06f105, 0x46290041, 0xf7ff9a04, 0xfb04ff2c, 0xeb06f105, 0x46290041, 
+    0xff10f7ff, 0xf851a909, 0x44081024, 0xf841a909, 0x1c640024, 0xdbe62c04, 0x02812001, 0x5000e9cd, 
+    0x1e822300, 0x1002e9cd, 0x46302103, 0xff7cf7fc, 0xe0162400, 0xf105fb04, 0x0041eb06, 0x9a044629, 
+    0xff05f7ff, 0xf105fb04, 0x0041eb06, 0xf7ff4629, 0xa909fee9, 0x1024f851, 0xa9094408, 0x0024f841, 
+    0x2c041c64, 0x2001dbe6, 0xe0070281, 0x00036296, 0xd1800030, 0x00038ac8, 0x00038ff0, 0x5000e9cd, 
+    0x1e822300, 0x1002e9cd, 0x46302103, 0xff4cf7fc, 0xe0162400, 0xf105fb04, 0x0041eb06, 0x9a044629, 
+    0xfed5f7ff, 0xf105fb04, 0x0041eb06, 0xf7ff4629, 0xa909feb9, 0x1024f851, 0xa9094408, 0x0024f841, 
+    0x2c041c64, 0x2004dbe6, 0xff61f7eb, 0x05082101, 0xfb8af7e8, 0xf088fa0f, 0x80c849c6, 0x80488088, 
+    0x46088008, 0xf9ccf7ea, 0x22082302, 0x46082101, 0xfb2ff7e9, 0x4611220b, 0x0000f242, 0xf946f7e9, 
+    0x4611220c, 0x0000f242, 0xf940f7e9, 0x4611220d, 0x0000f242, 0xf93af7e9, 0x02812001, 0x5000e9cd, 
+    0x1e822300, 0x1002e9cd, 0x46302103, 0xfefcf7fc, 0xe0122400, 0xf105fb04, 0x0041eb06, 0x9a044629, 
+    0xfe85f7ff, 0xf105fb04, 0x0041eb06, 0xf7ff4629, 0xa90dfe69, 0x0024f841, 0x2c041c64, 0x2001dbea, 
+    0xe9cd0281, 0x23005000, 0xe9cd1e82, 0x21031002, 0xf7fc4630, 0x2400fed9, 0xfb04e016, 0xeb06f105, 
+    0x46290041, 0xf7ff9a04, 0xfb04fe62, 0xeb06f105, 0x46290041, 0xfe46f7ff, 0xf851a90d, 0x44081024, 
+    0xf841a90d, 0x1c640024, 0xdbe62c04, 0x02812001, 0x5000e9cd, 0x1e822300, 0x1002e9cd, 0x46302103, 
+    0xfeb2f7fc, 0xe0162400, 0xf105fb04, 0x0041eb06, 0x9a044629, 0xfe3bf7ff, 0xf105fb04, 0x0041eb06, 
+    0xf7ff4629, 0xa90dfe1f, 0x1024f851, 0xa90d4408, 0x0024f841, 0x2c041c64, 0x2001dbe6, 0xe9cd0281, 
+    0x23005000, 0xe9cd1e82, 0x21031002, 0xf7fc4630, 0x2400fe8b, 0xfb04e016, 0xeb06f105, 0x46290041, 
+    0xf7ff9a04, 0xfb04fe14, 0xeb06f105, 0x46290041, 0xfdf8f7ff, 0xf851a90d, 0x44081024, 0xf841a90d, 
+    0x1c640024, 0xdbe62c04, 0xf7ffa805, 0x2400fbe4, 0xa809e00c, 0x0024f850, 0xa80dc701, 0x0024f850, 
+    0xa805c701, 0x0024f850, 0x1c64c701, 0xdbf02c04, 0xe0042400, 0xb2602104, 0xfcaef7ff, 0x2c041c64, 
+    0xf10adbf8, 0xf1ba0a01, 0xf6ff0f40, 0x2101ae66, 0xf7e80508, 0xea49faa9, 0xea402009, 0xea404009, 
+    0xc7016009, 0x2008ea48, 0x4008ea40, 0x6008ea40, 0xb011c701, 0x8ff0e8bd, 0x2100b510, 0xf7e82002, 
+    0x2100fae6, 0xf7e0484c, 0xf7eafa0f, 0xf7ebfc66, 0x2140f861, 0xf7e94608, 0x2100fa29, 0xf7e04847, 
+    0x2302fa03, 0x21032200, 0xf7e64845, 0x2001ffd1, 0xfdc4f7ec, 0xf7eb201c, 0xf7eaf9de, 0x2301fc04, 
+    0x46192200, 0xf7e6483f, 0x2004ffea, 0xfda5f7eb, 0xf7eb2004, 0x2001fe3c, 0xf9fff7fa, 0xf7e82002, 
+    0x2001faca, 0x70084938, 0x46082101, 0xfc03f7e9, 0x5074f240, 0x80084935, 0x80084935, 0x461a2300, 
+    0xf9b04608, 0x48311000, 0x0000f9b0, 0xfda6f7e9, 0x220f2300, 0x482b492f, 0xf7e6307c, 0x2002ffc0, 
+    0xfa4ff7fc, 0xf87af7fe, 0xfeccf7e8, 0xfee4f7e8, 0xb570bd10, 0xf7ff4606, 0x2500ff9f, 0xbf00e036, 
+    0x02882101, 0xfa30f7e8, 0xf7e04823, 0x4604f9a7, 0x000ff004, 0x4821b918, 0x28007800, 0x4621d1f0, 
+    0x1c80481d, 0xf9a0f7e0, 0x000ff004, 0xd0042801, 0xd0062802, 0xd10c2803, 0x4620e007, 0xfda4f7ff, 
+    0x4620e00c, 0xfc4bf7ff, 0x4620e008, 0xfb1df7ff, 0x4620e004, 0xfa14f7ff, 0xbf002501, 0xf64fbf00, 
+    0x402070f0, 0x480cb201, 0xf97ef7e0, 0xd0c62d00, 0x0000bd70, 0x00036296, 0xd00314c2, 0xd0030a00, 
+    0xd1800400, 0xd0035016, 0x000361ee, 0x00036234, 0x00036236, 0xffff8000, 0xd0035136, 0x0003625c, 
+    0x4af9b510, 0xf0027812, 0x4af80101, 0xf0097810, 0x49f6fbb6, 0xf0097808, 0x2301fdbb, 0x21402206, 
+    0xf7e648f3, 0x2301ff4c, 0x21202205, 0xf7e648f0, 0x2016ff46, 0x600849ef, 0xb51cbd10, 0x22092301, 
+    0x48ed0259, 0xff3bf7e6, 0xf7e92000, 0x2301f922, 0x46192200, 0xf7e648e6, 0x2300ff32, 0x21022201, 
+    0xf7e648e3, 0x4ee5ff2c, 0xe0042700, 0xf8262000, 0x1c780017, 0xf5b7b207, 0xdbf76f00, 0xe0182500, 
+    0xe0122400, 0x46032000, 0xb261b26a, 0x6000e9cd, 0xf7e62001, 0x2000faff, 0xb26a4603, 0xe9cdb261, 
+    0xf7e66000, 0x1c60faf7, 0x2c04b204, 0x1c68dbea, 0x2d04b205, 0xf240dbe4, 0x80302000, 0xe00a2400, 
+    0x46032000, 0xb2614602, 0x6000e9cd, 0xf7e62001, 0x1c60fae1, 0x2c04b204, 0x2307dbf2, 0x210f2200, 
+    0x304848c5, 0xfeebf7e6, 0x46112200, 0xf7f92001, 0x2080f8d9, 0x80c849c2, 0x80488088, 0x46088008, 
+    0xfee2f7e9, 0xf7e92001, 0x2100fb18, 0x306048ba, 0xf8daf7e0, 0x02882101, 0xf956f7e8, 0xf7fa2001, 
+    0x2801ffd3, 0x49b7d104, 0xf7e048b7, 0xe004f8cd, 0x31adf640, 0xf7e048b4, 0x2002f8c7, 0xfafdf7e9, 
+    0x22022300, 0x48aa2104, 0xfeb9f7e6, 0x22032300, 0x48a72108, 0xfeb3f7e6, 0xf7fd2005, 0x2301ff00, 
+    0x0299220a, 0xf7e648a2, 0x2101feaa, 0xf7e80288, 0x49a6f92b, 0x388a48a4, 0xf8a6f7e0, 0xfc07f7ed, 
+    0x4210f04f, 0x03882102, 0xf953f7e0, 0xf7e82002, 0xbf00f982, 0xe92de7fe, 0xf64f4ff8, 0x489c71ff, 
+    0xf887f7e0, 0x20022100, 0xf961f7e8, 0xf9b2f7f0, 0xf7fc2004, 0xf7f0f916, 0x2200f9a3, 0x46082101, 
+    0xf870f7f9, 0xf9c7f7f7, 0x46112200, 0xf7f92001, 0x4f8af869, 0x463b2000, 0x46012201, 0xf7e69000, 
+    0xf240fb24, 0x21001200, 0xf7ff4638, 0x4680fa3a, 0x463b2000, 0x46112201, 0xf7e69000, 0xf240fb16, 
+    0x21001200, 0xf7ff4638, 0x4606fa2c, 0x463b2000, 0x21022203, 0xf7e69000, 0xf240fb08, 0x21001200, 
+    0xf7ff4638, 0x4681fa1e, 0x463b2000, 0x46112203, 0xf7e69000, 0xf240fafa, 0x21001200, 0xf7ff4638, 
+    0x4683fa10, 0x48734641, 0xf833f7e0, 0x48714631, 0xf7e03008, 0x4649f82e, 0x3010486e, 0xf829f7e0, 
+    0x486c4659, 0xf7e03018, 0xf5b8f824, 0xda085f00, 0x5f00f5b6, 0xf5b9da05, 0xda025f00, 0x5f00f5b6, 
+    0x4965db07, 0xf7e04862, 0x4863f814, 0x60084963, 0x4963e006, 0xf7e0485e, 0x4861f80c, 0x6008495f, 
+    0x22032301, 0x485f2108, 0xfe09f7e6, 0xff1bf7ef, 0xfe7df7ef, 0xfe51f7ef, 0xfe1af7ef, 0xfe93f7f2, 
+    0xfb4ff7f2, 0xfac0f7f2, 0xfc48f7f2, 0xf9b8f7f2, 0xf7e82000, 0x2000ffde, 0xfe36f7fa, 0xfa80fa4f, 
+    0x46504951, 0xfb6bf7e6, 0xf7fa2001, 0xfa4ffe2d, 0x494dfa80, 0x46503110, 0xfb61f7e6, 0xf7fa2002, 
+    0xfa4ffe23, 0x4948fa80, 0x46503120, 0xfb57f7e6, 0xf7fa2003, 0xfa4ffe19, 0x4943fa80, 0x46503130, 
+    0xfb4df7e6, 0xe0112400, 0xe00b2500, 0xeb00483e, 0x5d401004, 0xb2424240, 0x46204629, 0xffa5f7fd, 
+    0xb2c51c68, 0xdbf12d10, 0xb2c41c60, 0xdbeb2c04, 0xf7fd2000, 0x2003ff66, 0xffadf7fd, 0x461a2300, 
+    0x48252101, 0xf7e630a0, 0x2100fdaa, 0xf7e94608, 0x2101f9c0, 0xf7e80308, 0x2004f827, 0xfde8f7fd, 
+    0x03082101, 0xf820f7e8, 0xf7e82001, 0x2101ff82, 0xf7e804c8, 0x2000f819, 0xff7bf7e8, 0xf7e92002, 
+    0x2300f9cc, 0x210c2202, 0xf7e64811, 0x2005fd88, 0xfdcef7fd, 0x220a2301, 0x480d0299, 0xfd7ff7e6, 
+    0x02882101, 0xf800f7e8, 0xf7e82001, 0x490fff62, 0x388a480d, 0xff78f7df, 0xfad9f7ed, 0xf7e82002, 
+    0xe8bdf85a, 0x00008ff8, 0x000361d8, 0x0003626a, 0xd0035022, 0x000361dc, 0xd0030400, 0x00043078, 
+    0x0003628e, 0xffff900d, 0xd00351aa, 0xffff8000, 0xd1800048, 0xd1800264, 0x8421b7ed, 0x00038460, 
+    0x84217bde, 0xd0031008, 0x00038e90, 0x489ab57f, 0xff44f7df, 0xf8adb280, 0x4897000c, 0xf7df1c80, 
+    0xb280ff3d, 0x000ef8ad, 0x1d004893, 0xff36f7df, 0xf8adb280, 0x48900008, 0xf7df1d80, 0xb280ff2f, 
+    0x000af8ad, 0x000cf8bd, 0x100ef8bd, 0x4001ea40, 0xf8bdb284, 0xf8bd0008, 0xea40100a, 0xb2854001, 
+    0xe9cd2000, 0x48855000, 0x1a2a6800, 0x68004884, 0x46231a21, 0xf7e0200a, 0x4881f84c, 0x487f6004, 
+    0xbd7f6005, 0x41fce92d, 0x46884605, 0xb1208ea8, 0xd011285a, 0xd17c285b, 0xe0dbe01a, 0x32fff04f, 
+    0x48794978, 0xf0076800, 0x4604f9e9, 0xb9501d20, 0x86a8205a, 0x81fce8bd, 0x49722200, 0x68004872, 
+    0xf9dcf007, 0x1d604604, 0x205bb918, 0xe7f186a8, 0x2c012401, 0xe0bdd000, 0x8800486a, 0xd17d2829, 
+    0x21042202, 0xf7e64869, 0xb2c6fcf1, 0xd1222e01, 0x02f1220b, 0xf7e64866, 0x2801fce9, 0x4865d145, 
+    0x28037800, 0x4863d00b, 0x28057800, 0x4861d007, 0x28047800, 0x4860d003, 0x28017800, 0xf04fd135, 
+    0xf24052a8, 0xf44f1160, 0xf7df0000, 0x2000ff72, 0xfb52f7e9, 0x220be029, 0x0100f640, 0xf7e64854, 
+    0xbb10fcc5, 0x78004853, 0xd00b2803, 0x78004851, 0xd0072805, 0x7800484f, 0xd0032804, 0x7800484e, 
+    0xd1122801, 0x52a8f04f, 0x1161f240, 0x0000f44f, 0xff4ff7df, 0xf7e92001, 0x2000fb2f, 0x0300f641, 
+    0x46014602, 0xf7eb9000, 0x2208f931, 0x48430151, 0xe060e000, 0xfc9af7e6, 0x4841b2c7, 0x46317802, 
+    0xf7e04638, 0x2202ff1d, 0x483e2104, 0xfc8ef7e6, 0x463b4607, 0x21022201, 0xf7e6483b, 0x4835fc70, 
+    0x28037800, 0x4833d007, 0x28057800, 0x4831d003, 0x28047800, 0xf001d101, 0xe000fd96, 0x4833e038, 
+    0x28017800, 0xf7e1d101, 0x4831fbb3, 0xb3706800, 0xf7df4830, 0x4607fe49, 0x6809492f, 0x28001a78, 
+    0x4601db01, 0x4241e000, 0x42914a2c, 0x482cd91f, 0x1d406800, 0x6008492a, 0x60074827, 0xf7e94829, 
+    0x4828fbcf, 0x492768c0, 0xe9cd6889, 0x49251000, 0x680a684b, 0x78094924, 0x2108b109, 0x2109e000, 
+    0x491f4608, 0xf7df6809, 0xf7ffff64, 0xe000fedf, 0xbf00e000, 0xbf00e722, 0xe72bbf00, 0x2200b510, 
+    0xf2af2101, 0xf00610df, 0x2108fe6a, 0xf0072003, 0x4905f807, 0xbd106008, 0xd0036112, 0x00036308, 
+    0x00036304, 0x00038ad0, 0x00038acc, 0xd03c8c04, 0xd0035026, 0x000361ec, 0x0003625e, 0xd28fffe2, 
+    0x0003626a, 0xd0039026, 0xd03c801a, 0x00036349, 0x000362f4, 0xc800017c, 0x000362fc, 0x4a817c80, 
+    0x00036300, 0x00038fe0, 0x000361ee, 0x41f0e92d, 0x460f4605, 0xb1208ea8, 0xd0112858, 0xd17d2859, 
+    0xe083e01a, 0x32fff04f, 0x484a4949, 0xf0076800, 0x4604f8c5, 0xb9501d20, 0x86a82058, 0x81f0e8bd, 
+    0x49432200, 0x68004843, 0xf8b8f007, 0x1d604604, 0x2059b918, 0xe7f186a8, 0x2c012401, 0xe065d000, 
+    0x8800483b, 0xd10f282d, 0xf9b04839, 0xf04f1000, 0x17d04220, 0xfe6df7df, 0xfb7bf009, 0x46112200, 
+    0xf7e04610, 0xe050fe4d, 0x88004831, 0xd14b2826, 0xf9904831, 0x28000000, 0xf04fdd37, 0x482e4260, 
+    0x1000f990, 0xf7df1750, 0x4a2cfe54, 0xf0027812, 0x4a290101, 0xf0087810, 0x4927fff2, 0xf0097808, 
+    0x4825f9f7, 0x1000f990, 0xf9904825, 0xf0090000, 0x4824fb58, 0x28088800, 0x4823d117, 0x28017800, 
+    0x2301d113, 0xf2402200, 0x482071ff, 0xfb77f7e6, 0x20022101, 0xffd3f008, 0x461a2300, 0x71fff240, 
+    0xf7e6481a, 0xf009fb6c, 0x2208fad6, 0x48180151, 0xfb7cf7e6, 0x4810b2c6, 0xe0007802, 0x2100e007, 
+    0xf7e04630, 0xe000fdfd, 0xbf00e000, 0xbf00e77a, 0xe783bf00, 0x2200b510, 0xf2af2101, 0xf006102f, 
+    0x2108fd9e, 0xf0062002, 0x4902ff3b, 0xbd106008, 0x00038adc, 0x00038ad8, 0x0003626a, 0x000361d8, 
+    0x00036318, 0x000361ce, 0x00038492, 0xd03c8c10, 0xd28fffe2, 0xf04fb510, 0x48fe5298, 0x1000f990, 
+    0xf7df2001, 0x2100fde6, 0x2000f44f, 0xfdacf7e7, 0x48f92100, 0xfd28f7df, 0x48f72100, 0xf7df1e80, 
+    0x48f6fd23, 0x28017800, 0xf242d106, 0x48f20101, 0xf7df1f00, 0xe004fd19, 0x48ef49f1, 0xf7df1f00, 
+    0xf242fd13, 0x48ef0101, 0xfd0ef7df, 0xb570bd10, 0x5298f04f, 0xf99048e7, 0x20011000, 0xfdb9f7df, 
+    0x304848e5, 0xfcfaf7df, 0xf004b284, 0x48e5017f, 0xfcfaf7df, 0x49df202d, 0x48e27008, 0xfceef7df, 
+    0x22004605, 0x20014629, 0xfdc8f7df, 0xb510bd70, 0x5298f04f, 0xf99048d7, 0x20011000, 0xfd99f7df, 
+    0x310949d7, 0xf7df48d7, 0x2013fcdf, 0x700849d1, 0xf7df48d4, 0x4604fcd3, 0x46212200, 0xf7df2001, 
+    0xbd10fdad, 0xf04fb510, 0x48ca5298, 0x1000f990, 0xf7df2001, 0x48ccfd7e, 0xb9287800, 0x1dc949c8, 
+    0xf7df48c8, 0xe013fcc1, 0x780048c7, 0xd1042801, 0x48c449c6, 0xfcb8f7df, 0x48c3e00a, 0x28027800, 
+    0x49c2d106, 0xf7df48bf, 0x2012fcaf, 0x700849b9, 0xf7df48bc, 0x4604fca3, 0x46212200, 0xf7df2001, 
+    0x48b9fd7d, 0x1c407800, 0x700849b7, 0xe92dbd10, 0x48b741f0, 0x21048800, 0x1000eb01, 0x028cb285, 
+    0xf7df48b4, 0xf3c0fc8b, 0x49b3000b, 0xf24e7809, 0xea020200, 0xea403141, 0xf04f0601, 0x48a55298, 
+    0x1000f990, 0xf7df2001, 0x4621fd34, 0x1e8048a2, 0xfc7af7df, 0x48a0b231, 0xfc76f7df, 0x489eb229, 
+    0xf7df1f00, 0x202dfc71, 0x7008499a, 0x1f00489a, 0xfc64f7df, 0x22004607, 0x20014639, 0xfd3ef7df, 
+    0x1e804895, 0xfc5af7df, 0x22004607, 0x20014639, 0xfd34f7df, 0xf7df4890, 0x4607fc51, 0x46392200, 
+    0xf7df2001, 0xe8bdfd2b, 0xb51081f0, 0x5298f04f, 0xf9904888, 0x20011000, 0xfcfbf7df, 0x7800488f, 
+    0xd11b282c, 0x6800488e, 0xd1172801, 0x48822100, 0xfc3af7df, 0x48802100, 0xf7df1e80, 0xf242fc35, 
+    0x48800101, 0xfc30f7df, 0x0101f242, 0x1f00487a, 0xfc2af7df, 0x4977202d, 0xe02e7008, 0x4876211b, 
+    0xf7df1e80, 0x2197fc21, 0xf7df4873, 0x4974fc1d, 0x48711d49, 0xf7df1f00, 0x201afc17, 0x7008496d, 
+    0x1f00486d, 0xfc0af7df, 0x22004604, 0x20014621, 0xfce4f7df, 0x1e804868, 0xfc00f7df, 0x22004604, 
+    0x20014621, 0xfcdaf7df, 0xf7df4863, 0x4604fbf7, 0x46212200, 0xf7df2001, 0xbd10fcd1, 0xf04fb510, 
+    0x485c5298, 0x1000f990, 0xf7df2001, 0x2100fca2, 0x1e804859, 0xfbe8f7df, 0x48572100, 0xfbe4f7df, 
+    0x78004860, 0xd10a2801, 0x4853495f, 0xf7df1f00, 0x495efbdb, 0x1d804857, 0xfbd6f7df, 0x4953e009, 
+    0x1f00484d, 0xfbd0f7df, 0x48522100, 0xf7df1d80, 0x2019fbcb, 0x70084947, 0x1f004847, 0xfbbef7df, 
+    0x22004604, 0x20014621, 0xfc98f7df, 0x1e804842, 0xfbb4f7df, 0x22004604, 0x20014621, 0xfc8ef7df, 
+    0xf7df483d, 0x4604fbab, 0x46212200, 0xf7df2001, 0xbd10fc85, 0xf04fb510, 0x48365298, 0x1000f990, 
+    0xf7df2001, 0x2100fc56, 0x1e804833, 0xfb9cf7df, 0x110af240, 0xf7df4830, 0x4931fb97, 0x482e1d09, 
+    0xf7df1f00, 0x2010fb91, 0x7008492a, 0x1f00482a, 0xfb84f7df, 0x22004604, 0x20014621, 0xfc5ef7df, 
+    0x1e804825, 0xfb7af7df, 0x22004604, 0x20014621, 0xfc54f7df, 0xf7df4820, 0x4604fb71, 0x46212200, 
+    0xf7df2001, 0xbd10fc4b, 0xf04fb570, 0x48195298, 0x1000f990, 0xf7df2001, 0x2100fc1c, 0x1e804816, 
+    0xfb62f7df, 0x48142100, 0xfb5ef7df, 0x78004820, 0x4916b928, 0x1f004810, 0xfb56f7df, 0xf248e044, 
+    0x481c0400, 0xb1087800, 0x0402f044, 0x7800481a, 0xf044b108, 0x48190401, 0xb1087800, 0x0408f044, 
+    0x78004817, 0xf044b108, 0xb2210404, 0x1f004802, 0x0000e028, 0x00038ae8, 0xd28e0030, 0x0003849e, 
+    0xffffa001, 0xd28fffce, 0x00038af8, 0xffff8000, 0x000361ce, 0xd03c801e, 0x000384e1, 0x00038ae9, 
+    0x000361dc, 0x00038454, 0xffff8107, 0xffff8380, 0x00038493, 0x00038495, 0x00038497, 0x00038499, 
+    0x0003849b, 0xfb10f7df, 0x49fe200f, 0x48fe7008, 0xfb04f7df, 0x22004605, 0x20014629, 0xfbdef7df, 
+    0x1c8048f9, 0xfafaf7df, 0x22004605, 0x20014629, 0xfbd4f7df, 0x1d0048f4, 0xfaf0f7df, 0x22004605, 
+    0x20014629, 0xfbcaf7df, 0xb510bd70, 0x5298f04f, 0xf99048ec, 0x20011000, 0xfb9bf7df, 0x1129f240, 
+    0x1d0048e9, 0xfae0f7df, 0x11d4f240, 0x1c8048e6, 0xfadaf7df, 0x48e449e5, 0xfad6f7df, 0x49e12031, 
+    0x48e17008, 0xfacaf7df, 0x22004604, 0x20014621, 0xfba4f7df, 0x1c8048dc, 0xfac0f7df, 0x22004604, 
+    0x20014621, 0xfb9af7df, 0x1d0048d7, 0xfab6f7df, 0x22004604, 0x20014621, 0xfb90f7df, 0xb510bd10, 
+    0xf7df48d3, 0xb284faab, 0x0001f004, 0x700849d1, 0x0040f3c4, 0x700849d0, 0x0080f3c4, 0x700849cf, 
+    0x00c0f3c4, 0x700849ce, 0x1000f3c4, 0x700849cd, 0x780348c8, 0x49cc220f, 0xf7e648cc, 0xbd10f890, 
+    0xf04fb510, 0x48bf5298, 0x1000f990, 0xf7df2001, 0x2100fb40, 0x1d0048bc, 0xfa86f7df, 0x48ba2100, 
+    0xf7df1c80, 0x49b9fa81, 0x48b71e89, 0xfa7cf7df, 0xffc5f7ff, 0x780048b7, 0x200eb118, 0x700849b1, 
+    0x200fe002, 0x700849af, 0xf7df48af, 0x4604fa67, 0x46212200, 0xf7df2001, 0x48abfb41, 0xf7df1c80, 
+    0x4604fa5d, 0x46212200, 0xf7df2001, 0x48a6fb37, 0xf7df1d00, 0x4604fa53, 0x46212200, 0xf7df2001, 
+    0xbd10fb2d, 0x202cb510, 0x700849a9, 0x5298f04f, 0xf9904608, 0x20011000, 0xfafbf7df, 0x680048a5, 
+    0xd1062812, 0x5298f04f, 0x20012120, 0xfaf1f7df, 0x48a0e054, 0x28136800, 0x0602d105, 0x20012121, 
+    0xfae7f7df, 0x489be04a, 0x28156800, 0xf04fd106, 0x21235298, 0xf7df2001, 0xe03ffadc, 0x68004895, 
+    0xd1062816, 0x5298f04f, 0x20012124, 0xfad1f7df, 0x4890e034, 0x28176800, 0xf04fd106, 0x21335298, 
+    0xf7df2001, 0xe029fac6, 0x6800488a, 0xd1062811, 0x5298f04f, 0x2001211f, 0xfabbf7df, 0x4885e01e, 
+    0x28ff6800, 0xf04fd106, 0x212f5298, 0xf7df2001, 0xe013fab0, 0x6800487f, 0xd1052801, 0x5298f04f, 
+    0xf7df2130, 0xe009faa6, 0x6800487a, 0xd1052810, 0x5298f04f, 0x2001211e, 0xfa9bf7df, 0x78004876, 
+    0x2001b910, 0x70084974, 0xf7df4874, 0x4604f9d7, 0x46212200, 0xf7df2001, 0x4863fab1, 0xf7df1d80, 
+    0x4604f9cd, 0x46212200, 0xf7df2001, 0x485efaa7, 0xf7df3008, 0x4604f9c3, 0x46212200, 0xf7df2001, 
+    0x4859fa9d, 0xf7df300a, 0x4604f9b9, 0x46212200, 0xf7df2001, 0xbd10fa93, 0x41f0e92d, 0x5298f04f, 
+    0xf990485b, 0x20011000, 0xfa63f7df, 0xf7df485b, 0xb284f9a5, 0xf3c40be5, 0x4858060a, 0xf99ef7df, 
+    0x22004607, 0x20014639, 0xfa78f7df, 0x78004854, 0xd10e2808, 0x5298f04f, 0xf9904851, 0x20011000, 
+    0xfa47f7df, 0x484fb231, 0xf98ef7df, 0x49482006, 0xb9157008, 0x4946202b, 0xe8bd7008, 0xe92d81f0, 
+    0xf04f41f0, 0x48425298, 0x1000f990, 0xf7df2001, 0x4842fa30, 0xf972f7df, 0x0be5b284, 0x3640f3c4, 
+    0x070af3c4, 0xf7df483d, 0x4680f969, 0x46412200, 0xf7df2001, 0xb13efa43, 0xd1052f0a, 0x49382008, 
+    0x20077008, 0x70084932, 0x202bb915, 0x70084930, 0x81f0e8bd, 0x4604b570, 0x462b460d, 0x21ff2200, 
+    0xf7e5482a, 0x4623ff4c, 0xf244220e, 0x48270100, 0xff45f7e5, 0xe92dbd70, 0xf04f47f0, 0x48245298, 
+    0x1000f990, 0xf7df2001, 0x4817f9f4, 0xf7df300a, 0xb286f935, 0x30084814, 0xf930f7df, 0x4812b285, 
+    0xf7df1d80, 0xb284f92b, 0x46212200, 0xf7df2001, 0x2200fa05, 0x20014629, 0xfa00f7df, 0x46312200, 
+    0xf7df2001, 0xea4ff9fb, 0x481538d4, 0x28047800, 0xf04fd15d, 0x48125298, 0x1000f990, 0xf7df2001, 
+    0xe021f9c8, 0x00038ae8, 0xd28e002c, 0xffffa00b, 0xd03c0000, 0x00038493, 0x00038495, 0x00038497, 
+    0x00038499, 0x0003849b, 0xffff8000, 0xd0039080, 0x00038ae9, 0x000361dc, 0x0003849e, 0xd28fffd0, 
+    0x00038aea, 0xd0035112, 0x680048f8, 0x2141f3c4, 0x49f64308, 0x46086008, 0xf5b06800, 0xd1176f85, 
+    0x1082f3c4, 0xd1142804, 0x49f12001, 0xf3c47008, 0x49f00080, 0xf3c47008, 0x49ef0040, 0xf0047008, 
+    0x49ee0001, 0x01e07008, 0x48edb201, 0xf8ccf7df, 0x2000e268, 0x700849e6, 0x700849e6, 0x700849e6, 
+    0x700849e6, 0x48e62100, 0xf8bef7df, 0x48e5e25a, 0x28327800, 0xf04fd174, 0x48e25298, 0x1000f990, 
+    0xf7df2001, 0x48e0f966, 0x28017800, 0xf004d120, 0x49de0001, 0xf3c47008, 0x49dd0040, 0xf3c47008, 
+    0x49dc0080, 0xf3c47008, 0x49db00c0, 0x48d87008, 0x4ad67800, 0xea407812, 0x460a0042, 0xea407812, 
+    0x4ad40082, 0xea407812, 0x48d401c2, 0xf88cf7df, 0x880048d3, 0xd0032809, 0x880048d1, 0xd101280d, 
+    0xe0112700, 0xf241220c, 0x48ce0100, 0xfe8ef7e5, 0x220b4681, 0x0100f640, 0x1c8048ca, 0xfe86f7e5, 
+    0x0900ea09, 0x07fff009, 0x780048c7, 0xd1162801, 0x780048bf, 0xd1122801, 0x780048c4, 0xd10e2801, 
+    0x49c32002, 0x23047008, 0x21072200, 0x1f0048bb, 0xfe55f7e5, 0x2001214e, 0xfefcf7ff, 0x2f01e03e, 
+    0x2020d10f, 0x700849ba, 0x461a2300, 0x48b32107, 0xf7e51f00, 0x2134fe44, 0xf7ff2000, 0xe02dfeeb, 
+    0x48aae030, 0x28017800, 0x48b2d112, 0x28017800, 0x2004d10e, 0x700849ae, 0x22002305, 0x48a72107, 
+    0xf7e51f00, 0x214efe2c, 0xf7ff2001, 0xe015fed3, 0x7800489f, 0xd1112801, 0x780048a4, 0xd10d2801, 
+    0x49a32002, 0x23047008, 0x21072200, 0x1f00489b, 0xfe15f7e5, 0x2001214e, 0xfebcf7ff, 0x499e2001, 
+    0xe1af7008, 0x7800488f, 0xd16e2805, 0x5298f04f, 0xf990488c, 0x20011000, 0xf8bbf7df, 0x1006f3c4, 
+    0x80084996, 0x0103f005, 0xf3614620, 0x4994101f, 0xf2408008, 0x200111f4, 0xf8e4f7df, 0x68014891, 
+    0xf7df2001, 0x488df88f, 0x20018801, 0xf88af7df, 0x2001498d, 0xf886f7df, 0x5298f04f, 0xf9904879, 
+    0x20011000, 0xf895f7df, 0x68004886, 0x0197f64d, 0xd1734288, 0x008bf3c5, 0x6f80f5b0, 0x4880d16f, 
+    0x28108800, 0x487ed006, 0x28208800, 0x487cd002, 0xb9188800, 0x497d2012, 0xe1226008, 0x88004878, 
+    0xd1652801, 0x49792013, 0x48746008, 0x28128800, 0x2001d103, 0x60084976, 0x4870e113, 0x28168800, 
+    0x2002d103, 0x60084972, 0x486ce10b, 0x28068800, 0x2003d103, 0x6008496e, 0x4868e103, 0x280e8800, 
+    0x2004d104, 0x6008496a, 0xe135e0fb, 0x88004863, 0xd1032814, 0x49662005, 0xe0f26008, 0x8800485f, 
+    0xd1032810, 0x49622006, 0xe0ea6008, 0x8800485b, 0xd1032813, 0x495e2001, 0xe0e26008, 0x88004857, 
+    0xd1032817, 0x495a2002, 0xe0da6008, 0x88004853, 0xd1032807, 0x49562003, 0xe0d26008, 0x8800484f, 
+    0xd103280f, 0x49522004, 0xe0ca6008, 0x8800484b, 0xd1052815, 0x494e2005, 0xe0c26008, 0xe09de0a9, 
+    0x88004846, 0xd1022811, 0x49492006, 0xe0b86008, 0x88004843, 0xd12a2802, 0x49442015, 0x483f6008, 
+    0x281d8800, 0x200dd103, 0x60084941, 0x483be0a9, 0x281b8800, 0x200ed103, 0x6008493d, 0x4837e0a1, 
+    0x28198800, 0x200fd103, 0x60084939, 0x4833e099, 0x281c8800, 0x2010d103, 0x60084935, 0x482fe091, 
+    0x281f8800, 0x2011d102, 0x60084931, 0x482ce089, 0x28038800, 0x2016d112, 0x6008492c, 0x88004827, 
+    0xd103282a, 0x492a2012, 0xe07a6008, 0x88004823, 0xd176282a, 0x49262012, 0xe0726008, 0x88004820, 
+    0xd1472804, 0x49212017, 0x481c6008, 0x28088800, 0x2014d103, 0x6008491e, 0x4818e063, 0x280c8800, 
+    0x2015d15f, 0x6008491a, 0x0000e05b, 0x00038b00, 0x00038455, 0x00038456, 0x00038457, 0x00038458, 
+    0xd03c8026, 0x00038aea, 0x00038494, 0x00038498, 0x00038496, 0x0003849c, 0x0003849a, 0xd0070004, 
+    0x000361ce, 0xd28e0040, 0x00038492, 0x00038495, 0x0003849d, 0x00038497, 0x0003849e, 0x00038b08, 
+    0x00038b0a, 0x00038b04, 0xdcba01f5, 0x000361dc, 0x000361e0, 0x49f920ff, 0xe0226008, 0x10c2f3c5, 
+    0x2011b118, 0x600849f5, 0x20ffe01b, 0x600849f3, 0x48f3e017, 0xf64e6800, 0x4288016d, 0xf3c4d10e, 
+    0x28021045, 0xf3c4d106, 0xb9180043, 0x49eb2001, 0xe0066008, 0x49e92010, 0xe0026008, 0x49e72010, 
+    0x48e66008, 0x28166800, 0xf406d906, 0xb1184060, 0x49e40b70, 0xe0027008, 0x49e22000, 0x48e27008, 
+    0xb1207800, 0x780048df, 0x2001b108, 0x2000e000, 0x700849de, 0x880048de, 0x48deb201, 0xfe84f7de, 
+    0x680048db, 0x410cf3c0, 0x1c8048da, 0xfe7cf7de, 0x880048d3, 0x48d7b201, 0xf7de1d00, 0x48d0fe75, 
+    0xf64f6800, 0xea0171ff, 0x22004310, 0x48d121ff, 0xf7e51d80, 0xe005fc64, 0x5298f04f, 0x2001211c, 
+    0xff17f7de, 0x0f01f1b8, 0x202bd003, 0x700849ca, 0x2002e002, 0x700849c8, 0x87f0e8bd, 0x47f0e92d, 
+    0x5298f04f, 0xf99048c4, 0x20011000, 0xff01f7de, 0xf7de48c2, 0xb284fe43, 0x1e8048c0, 0xfe3ef7de, 
+    0x48beb286, 0xf7de1f00, 0xb285fe39, 0x46292200, 0xf7de2001, 0x2200ff13, 0x20014631, 0xff0ef7de, 
+    0x46212200, 0xf7de2001, 0xea4fff09, 0xf3c539d5, 0xf0053740, 0xb3bf08ff, 0x0f09f1b8, 0xf04fd135, 
+    0x21275298, 0xf7de2001, 0xf3c4fed4, 0x49ac00c0, 0xf4047008, 0x114070e0, 0x700849aa, 0x78014608, 
+    0x384a48a4, 0xfe10f7de, 0x880048a7, 0xd07d2809, 0x880048a5, 0xd079280d, 0xf241220c, 0x489f0100, 
+    0xf7e5300a, 0x4682fc13, 0xf640220b, 0x489b0100, 0xf7e5300c, 0xea0afc0b, 0xf1ba0a00, 0xd1650f01, 
+    0x499a2020, 0xe0617008, 0x2f01e7ff, 0xf1b8d125, 0xd1220f0b, 0x5298f04f, 0x20012128, 0xfe99f7de, 
+    0x60064893, 0x4992b2e0, 0xea416809, 0x49904000, 0x46086008, 0x498f6800, 0xd1044288, 0x2000f3c4, 
+    0x7008498d, 0x2000e002, 0x7008498b, 0x49822003, 0x20327008, 0x70084989, 0x2f01e038, 0xf1b8d117, 
+    0xd1140f05, 0x5298f04f, 0x20012125, 0xfe71f7de, 0x49830370, 0x46086008, 0xea406800, 0x60080084, 
+    0x49752003, 0x20047008, 0x7008497c, 0x2f01e01e, 0xf1b8d116, 0xd1130f06, 0x5298f04f, 0x20012126, 
+    0xfe57f7de, 0x60044866, 0xea406800, 0x496420c6, 0x20036008, 0x70084968, 0x49702005, 0xe0057008, 
+    0x5298f04f, 0x20012129, 0xfe43f7de, 0x0f01f1b9, 0x202bd002, 0x70084960, 0x87f0e8bd, 0xf04fb570, 
+    0x485d5298, 0x1000f990, 0xf7de2001, 0x485bfe32, 0xf7de3810, 0xb284fd73, 0x38104858, 0xfd6ef7de, 
+    0x22004605, 0x20014629, 0xfe48f7de, 0x5080f404, 0x200db130, 0x7008495b, 0x494f2002, 0xe0197008, 
+    0x4000f404, 0x2011b148, 0x70084956, 0x494a2006, 0x20007008, 0x70084954, 0x202de00c, 0x70084951, 
+    0x4945202b, 0xb92c7008, 0x5298f04f, 0x2001212e, 0xfdfff7de, 0x494d2000, 0x21007008, 0xf7ed2025, 
+    0x2001f8c2, 0x7008494a, 0x494a2200, 0xf7e62004, 0x200bfe5b, 0xfeabf7e6, 0xb510bd70, 0x494120ff, 
+    0x49357008, 0x493d7008, 0x20007008, 0x6008492c, 0x6008493b, 0x49292010, 0x20006008, 0x8008493e, 
+    0x7008493e, 0x7008493e, 0x7008493e, 0x7008493e, 0x7008493e, 0x7008493e, 0x70084929, 0x7008493d, 
+    0x7008493d, 0x7008493d, 0x7008492b, 0x7008493c, 0x7008493c, 0x7008491d, 0x7008491a, 0x7008493a, 
+    0x481c2100, 0xfd00f7de, 0x481a2100, 0xf7de1c80, 0x2100fcfb, 0x1d004817, 0xfcf6f7de, 0x461a2300, 
+    0x481421ff, 0xf7e51d80, 0x2000faea, 0x7008492f, 0xf7e67808, 0x2300fd4f, 0x21022201, 0xf7e5482c, 
+    0x2300fade, 0x2101461a, 0xf7e54829, 0x2000fad8, 0x70084928, 0xf8e8f7ed, 0x0000bd10, 0x000361dc, 
+    0x00038b04, 0x000384e2, 0x000384e1, 0x000384e0, 0x000361d4, 0xd003515c, 0x00038ae9, 0xd28e0036, 
+    0x0003845a, 0x00036322, 0x000361ce, 0x0003849d, 0x00038afc, 0x002901d4, 0x00038494, 0x00038aea, 
+    0x00038b00, 0x00038ae8, 0x00038af8, 0x000384d6, 0x0003845b, 0x684ee180, 0x00038b08, 0x00038456, 
+    0x00038457, 0x00038458, 0x00038454, 0x00038455, 0x00038459, 0x00038493, 0x00038495, 0x00038497, 
+    0x00038496, 0x00038498, 0x000384e3, 0x0003626a, 0xd0039084, 0x000384e5, 0xf7ffb510, 0x2001ff4e, 
+    0xfb8ff7e1, 0x22022300, 0x48f72104, 0xfa77f7e5, 0x780048f6, 0xdd0f2800, 0x780048f5, 0xd0032801, 
+    0x780048f4, 0xd1072801, 0x22032301, 0x48ee2108, 0xf7e53038, 0xe006fa64, 0x22032300, 0x48ea2108, 
+    0xf7e53038, 0x48ecfa5c, 0x28007800, 0x2301dd1f, 0x21042202, 0x303848e4, 0xfa51f7e5, 0x461a2301, 
+    0x48e12102, 0xf7e53038, 0x48e3fa4a, 0x28017800, 0x2301dd06, 0x46192200, 0xf7e548e0, 0xe014fa40, 
+    0x461a2300, 0x48dd2101, 0xfa39f7e5, 0x2300e00d, 0x21042202, 0x303848d4, 0xfa31f7e5, 0x22012300, 
+    0x48d12102, 0xf7e53038, 0x48d5fa2a, 0xb1907800, 0x461a2301, 0x48cc2102, 0xfa21f7e5, 0x49d12001, 
+    0x23017008, 0x21102204, 0xf7e548cf, 0x2001fa18, 0x700849ce, 0x2300e011, 0x21022201, 0xf7e548c2, 
+    0x2000fa0e, 0x700849c7, 0x22042300, 0x48c62110, 0xfa05f7e5, 0x49c52000, 0x20007008, 0x700849c4, 
+    0x700849c4, 0x22032300, 0x48bf2108, 0xf9f7f7e5, 0x48c12100, 0xfbf8f7de, 0xf941f7ff, 0x461a2300, 
+    0x48be2107, 0xf9ebf7e5, 0x48bc2100, 0xf7de1d00, 0x2000fbeb, 0x700849ba, 0x700849ba, 0xf7ff2134, 
+    0x2001fa89, 0xfd53f7e6, 0x48ac49b7, 0xf7de384a, 0x49b5fbdb, 0x384848a9, 0xfbd6f7de, 0x48a72100, 
+    0xf7de3846, 0x2002fbd1, 0xfe12f7ec, 0xf7eb2007, 0x2100fd68, 0xf7ec2025, 0x2301ff46, 0x21102204, 
+    0x302448a5, 0xf9bbf7e5, 0xf7eb2003, 0x2202fd19, 0x489a2104, 0xf7e5382c, 0x2801f9c9, 0x49a3d109, 
+    0x22017008, 0x200449a2, 0xfccef7e6, 0xf7e6200b, 0x201bfd1e, 0x7008499f, 0x499f2001, 0x20007008, 
+    0xfc7cf7ec, 0x4270f04f, 0x20012102, 0xfc51f7de, 0xb570bd10, 0x460d4604, 0xb1208ea0, 0xd01528ca, 
+    0xd17228cb, 0xf7ffe021, 0xe0d4fe58, 0x32fff04f, 0x48934992, 0xf0056800, 0x4992fe71, 0x46086008, 
+    0x1d006800, 0x20cab950, 0xbd7086a0, 0x498b2200, 0x6800488b, 0xfe62f005, 0x6008498a, 0x68004889, 
+    0xb9281d40, 0x86a020cb, 0x2001e7ef, 0x60084985, 0x68004884, 0xd0002801, 0x4880e0ad, 0x1000f9b0, 
+    0x4220f04f, 0xf7de2001, 0x487cfc14, 0x283a8800, 0xf7ffd102, 0xe09dfed1, 0x88004878, 0xd174283b, 
+    0x78004879, 0xd1012801, 0x70084973, 0x78004872, 0xd1022801, 0xfdc2f7ff, 0x486fe01a, 0x28027800, 
+    0xf7ffd102, 0xe013fceb, 0x7800486b, 0xd1022803, 0xf9f1f7ff, 0x4868e00c, 0x28067800, 0xf7ffd102, 
+    0xe005f9ae, 0x78004864, 0xd1012807, 0xf974f7ff, 0x78004861, 0xd101282b, 0xf8d4f7ff, 0x78004863, 
+    0xd103280d, 0xf88cf7ff, 0xe065e046, 0x7800485f, 0xd102280e, 0xf829f7ff, 0x485ce03e, 0x28317800, 
+    0xf7fed102, 0xe037ffa1, 0x78004858, 0xd102280f, 0xff60f7fe, 0x4855e030, 0x28107800, 0xf7fed102, 
+    0xe029ff0d, 0x78004851, 0xd1022819, 0xfeadf7fe, 0x484ee022, 0x281a7800, 0xf7fed102, 0xe01bfe58, 
+    0x7800484a, 0xd1022811, 0xfe1cf7fe, 0x4847e014, 0x28127800, 0xf7fed102, 0xe00dfdfa, 0x78004843, 
+    0xd1032813, 0xfdd3f7fe, 0xe01ae006, 0x7800483f, 0xd101282d, 0xfd9ef7fe, 0x7800483c, 0xd119282d, 
+    0x78004835, 0xd115282c, 0x49322000, 0xf04f7008, 0x211d5298, 0xf7de2001, 0x2002fb7c, 0xf9d1f7e1, 
+    0x482ee008, 0x1000f9b0, 0x4220f04f, 0xf7de2001, 0xe000fb70, 0xe729bf00, 0xbf00bf00, 0xb510e735, 
+    0x21012200, 0x10d5f2af, 0xfaf9f005, 0x20042108, 0xfc96f005, 0x60084922, 0xb510bd10, 0x78004819, 
+    0xd1472820, 0x49222003, 0x23007008, 0x21022201, 0x3032480a, 0xf893f7e5, 0x461a2300, 0x48072101, 
+    0xf7e53032, 0xe054f88c, 0xd28e0040, 0x00036324, 0x00036321, 0x00036329, 0x00036325, 0xd0039052, 
+    0x00038b1d, 0x00038459, 0xd0035256, 0x00038454, 0x00038455, 0x0003845a, 0xd03c8026, 0xd0070000, 
+    0x0003849e, 0x0003849d, 0xffffad68, 0x0003845b, 0x684ee180, 0x000361ed, 0x00038ae9, 0x00038aec, 
+    0x00038ae4, 0x00038af4, 0x00036267, 0x00038ae8, 0x0003626a, 0x78004833, 0xd1092804, 0x49322005, 
+    0x23017008, 0x2102461a, 0xf7e54830, 0xe010f848, 0x7800482c, 0xd1092802, 0x492b2004, 0x23017008, 
+    0x46192200, 0xf7e54829, 0xe002f83a, 0x49262000, 0x49257008, 0xf7e67808, 0x4823fa9d, 0xbd107800, 
+    0x4823b510, 0xb1187800, 0x491f2002, 0xe0147008, 0x21602205, 0xf7e5481f, 0xb2c4f839, 0xd1032c01, 
+    0x49192004, 0xe0087008, 0xd1032c02, 0x49162005, 0xe0027008, 0x49142003, 0x49137008, 0xf7e67808, 
+    0x4811fa79, 0xbd107800, 0x4605b570, 0xd1012d03, 0xe0102403, 0xd1012d05, 0xe00c2405, 0xd1012d04, 
+    0xe0082404, 0xd1012d02, 0xe0042402, 0xd1012d01, 0xe0002401, 0x46232400, 0x21072200, 0xf7e44806, 
+    0xbd70ffee, 0x0003849d, 0x0003626a, 0xd0039084, 0x00036266, 0xd03c0000, 0xd0070000, 0x4841b570, 
+    0xf9dcf7de, 0xf3c4b284, 0x493f00c6, 0x483d8008, 0xf7de1e80, 0xb285f9d3, 0x6002f64a, 0xd1134285, 
+    0x88004839, 0xd00b280d, 0x88004837, 0xd0072809, 0x88004835, 0xd0032808, 0x88004833, 0xd101280c, 
+    0xe0022001, 0xe0002000, 0x46062000, 0xf7f8b93e, 0x492ef856, 0xf7de482e, 0xbf00f9b7, 0x482de7fe, 
+    0xf9acf7de, 0x0001f000, 0x8008492b, 0xf2402208, 0x48273100, 0xf7e43880, 0xb240ffb9, 0x70084927, 
+    0x88004821, 0xd10b2808, 0x78004608, 0x0001f000, 0xbf30b108, 0xf640e004, 0x48210100, 0xffb6f7e4, 
+    0x21012200, 0x3008481e, 0xffa0f7e4, 0xd1062801, 0x22042301, 0x481a2110, 0xf7e43008, 0xf04fff80, 
+    0x481731ff, 0xf7de3010, 0x2301f97f, 0x21042202, 0x30084813, 0xff73f7e4, 0x461a2301, 0x48102102, 
+    0xf7e43008, 0xf242ff6c, 0x480941a1, 0xf7de3898, 0xf243f96b, 0x48060180, 0xf7de389a, 0xf7f7f965, 
+    0xbd70fe73, 0xd0020006, 0x000361ce, 0xffffbbb0, 0xd03c80b8, 0xd03c81fe, 0x000361cc, 0x000361d8, 
+    0xd03c8310, 0x4605b570, 0x8ea8460e, 0x285eb120, 0x285fd010, 0xe019d134, 0xf04fe031, 0x492132ff, 
+    0x68004821, 0xfc2af005, 0x1d204604, 0x205eb948, 0xbd7086a8, 0x491b2200, 0x6800481b, 0xfc1ef005, 
+    0x1d604604, 0x205fb918, 0xe7f286a8, 0x2c012401, 0xe014d000, 0x88004813, 0xd10e2862, 0xf9b04811, 
+    0xf04f1000, 0xf44f4220, 0xf7de0000, 0x490df9d2, 0x0002f9b1, 0xfaadf7de, 0xe000e000, 0xe7ccbf00, 
+    0xbf00bf00, 0xb510e7d5, 0x21012200, 0x008bf2af, 0xf955f005, 0x20032108, 0xfaf2f005, 0x60084902, 
+    0x0000bd10, 0x00038b10, 0x00038b0c, 0x2201b510, 0x48fe2106, 0xff0af7e4, 0x2301b930, 0x21102204, 
+    0xf7e448fb, 0xe00cfeec, 0x21062201, 0xf7e448f7, 0x2801fefd, 0x2300d105, 0x21102204, 0xf7e448f4, 
+    0xbd10fede, 0x4604b510, 0x20012100, 0xfadff7e7, 0x2200b2a3, 0x48ee2101, 0xf7e43822, 0x2003fed0, 
+    0xfb0bf7e7, 0xb51fbd10, 0xf7e74668, 0x9800fe59, 0x48e8b201, 0xf8c8f7de, 0x0c009800, 0x48e5b201, 
+    0xf7de1c80, 0x9801f8c1, 0x48e2b201, 0xf7de1d00, 0x9801f8bb, 0xb2010c00, 0x1d8048de, 0xf8b4f7de, 
+    0xb2019802, 0x300848db, 0xf8aef7de, 0x0c009802, 0x48d8b201, 0xf7de300a, 0x9803f8a7, 0x48d5b201, 
+    0xf7de300c, 0x9803f8a1, 0xb2010c00, 0x300e48d1, 0xf89af7de, 0xb510bd1f, 0x49cf2001, 0xf04f7008, 
+    0xf24052a0, 0x06001103, 0xf943f7de, 0x11f4f240, 0x7080f04f, 0xf976f7de, 0x61eef64e, 0x7080f04f, 
+    0xf920f7de, 0xf04f49c5, 0xf7de7080, 0x2300f91b, 0x2101461a, 0xf7e448c2, 0xf640fe72, 0x48c10100, 
+    0x1c407800, 0x0007f000, 0x1000eb00, 0xeb024abe, 0x60810080, 0xf7e62002, 0x2003f9f5, 0xf9f2f7e6, 
+    0xe92dbd10, 0x46064ffe, 0x46904689, 0xf8dd469a, 0xf04fb030, 0x23000e81, 0x3000f8c8, 0x2300f240, 
+    0x3000f8aa, 0xf8ab2300, 0x25003000, 0x2000e072, 0x182be03d, 0x2b001e9b, 0x182bd404, 0xf8561e9b, 
+    0xe0003023, 0x93002300, 0x93012300, 0xf04f9302, 0xe0243cff, 0x030ceb00, 0xdb082b00, 0x030ceb00, 
+    0xda044573, 0x4463182b, 0x3023f856, 0x2300e000, 0x9b00461f, 0xda0542bb, 0x93029b01, 0x93019b00, 
+    0xe00a9700, 0x42bb9b01, 0x9b01da03, 0x97019302, 0x9b02e003, 0xda0042bb, 0xf10c9702, 0xf1bc0c01, 
+    0xdbd70f03, 0x9b02182c, 0x3024f849, 0x45701c40, 0x2000dbbf, 0x182be02b, 0x3023f856, 0xf859182c, 
+    0x1b194024, 0x240017ca, 0x3000f8d8, 0x41941a5b, 0x2400da1c, 0x1b0c4623, 0x0303eb72, 0x2300da02, 
+    0xe00b461c, 0x4480f04f, 0x1a642300, 0xda034193, 0x5300f04f, 0xe0012400, 0x4614460b, 0x3000f8c8, 
+    0xf8aab203, 0xb22b3000, 0x3000f8ab, 0x45701c40, 0x4475dbd1, 0x038eea4f, 0xdc8842ab, 0x8ffee8bd, 
+    0x43f8e92d, 0x460d4604, 0x461f4616, 0x8020f8dd, 0x1000f9b4, 0x52a0f04f, 0x7080f04f, 0xf879f7de, 
+    0x496a2000, 0x49647008, 0x49697008, 0x48697008, 0xb1706800, 0x78004868, 0xd1022801, 0x7010f242, 
+    0x2000e000, 0x3102f200, 0x3008485d, 0xffacf7dd, 0x2000e034, 0x1e407028, 0xf8c86030, 0x20000000, 
+    0x1e416038, 0x1f804853, 0xff9ef7dd, 0x7800485b, 0xf004b108, 0x2300f826, 0x01512208, 0x381c484d, 
+    0xfd8df7e4, 0x2301e006, 0x02592209, 0x381c4849, 0xfd85f7e4, 0x21402206, 0xf7e44851, 0x2800fd97, 
+    0xf641d1f1, 0x46020300, 0x90004601, 0xfa1ef7e9, 0x22042300, 0x483e2110, 0xfd71f7e4, 0x83f8e8bd, 
+    0x5ff0e92d, 0x460c4607, 0x46994690, 0xab0ae9dd, 0x1000f9b7, 0x52a0f04f, 0x7080f04f, 0xf819f7de, 
+    0xf9904840, 0x1c400000, 0x2500b9a0, 0x2600e00d, 0x483de008, 0x1005eb00, 0x493c5d80, 0x1105eb01, 
+    0x1c765588, 0xdbf42e10, 0x2d041c6d, 0x2000dbef, 0x70084934, 0x492d2000, 0x49277008, 0x492c7008, 
+    0xf8c87008, 0xf8c90000, 0xf8ca0000, 0xf8cb0000, 0x482c0000, 0x28007800, 0x482dd17e, 0x28007800, 
+    0x482cd07b, 0xf5b07800, 0xda777f96, 0xf990482a, 0x70200000, 0x28007820, 0xe006d06e, 0x22092301, 
+    0x48140259, 0xf7e4381c, 0x2206fd1a, 0x481c2140, 0xfd2cf7e4, 0xd1f12800, 0x22002301, 0x31fff240, 
+    0x3032480b, 0xfd0bf7e4, 0x2200230f, 0x31fff240, 0x30304807, 0xfd03f7e4, 0x88004818, 0x2002bb80, 
+    0xf875f7e6, 0x22082301, 0xe02a0151, 0xd0020126, 0xd0035250, 0xd0035142, 0x00038b56, 0xdcba01f5, 
+    0xd03c80b0, 0x00038b38, 0x00048c18, 0x00036344, 0x00038b57, 0x00052f80, 0x000361ee, 0x00038db0, 
+    0xd003502c, 0x00038b76, 0x00044288, 0x0004cc48, 0x00038b1d, 0x00036226, 0x00038b1e, 0x00038b20, 
+    0x48fee015, 0xf7e4381c, 0x2100fcca, 0xf7e52040, 0x2003ff4b, 0xf83bf7e6, 0x20402100, 0xff44f7e5, 
+    0x20082100, 0xf873f7e8, 0xf7e82001, 0x2101fb65, 0xf7e84608, 0xe002f9b0, 0xe02fe039, 0x218ce02b, 
+    0xf7dd48ef, 0x23fffeb1, 0xf2402200, 0x48ed31ff, 0xfca5f7e4, 0x2200233f, 0x11fff240, 0x301448e9, 
+    0xfc9df7e4, 0x780048e8, 0xd1022801, 0x5230f247, 0xf644e001, 0x48e56220, 0x1e406800, 0x33e8f240, 
+    0x2000fb03, 0x88124ae2, 0xb2014410, 0x301448dc, 0xfe8af7dd, 0x2000e00b, 0xe0087020, 0x70202000, 
+    0x52a0f04f, 0xf04f2141, 0xf7dd7080, 0xe8bdff32, 0xe92d9ff0, 0xb08d4fff, 0x46174604, 0x20004699, 
+    0x2004900c, 0x2014900b, 0x201e900a, 0x20079009, 0xff66f7e5, 0x600849cf, 0xf7dd48cf, 0x4683fe5f, 
+    0x1e8048cd, 0xfe5af7dd, 0x401ff36b, 0x600849cb, 0x49cb2000, 0x49cb7008, 0x46826008, 0xe23c9007, 
+    0xf2402100, 0xf7e54000, 0x48c7fecf, 0xb3907800, 0x49c32000, 0xf2407008, 0xf04f11f4, 0xf7dd7080, 
+    0x49c2ff31, 0x7080f04f, 0xfedcf7dd, 0xf04f49c0, 0xf7dd7080, 0x48b6fed7, 0x1c407800, 0x0007f000, 
+    0x1000eb00, 0xeb0149bb, 0x68800080, 0x49b03010, 0x1c497809, 0x0107f001, 0x1101eb01, 0xeb024ab5, 
+    0x60880181, 0x980e49b4, 0x48ad6008, 0x0000f990, 0xe8bdb011, 0xe7ff8ff0, 0xf7e52007, 0x49afff11, 
+    0x48a56008, 0xfe0af7dd, 0x48a34683, 0xf7dd1e80, 0xf36bfe05, 0x49aa401f, 0x48a86008, 0x499d6800, 
+    0x42886809, 0x48a5d907, 0x1e016800, 0x68004899, 0x90081a40, 0x4897e005, 0x49a06800, 0x1a406809, 
+    0xf04f9008, 0x900b0004, 0x0014f04f, 0xf04f900a, 0x9009001e, 0x7800489b, 0xd1052805, 0x200f900b, 
+    0x2014900a, 0xe0099009, 0x78004896, 0xd1052804, 0x900b2006, 0x900a200a, 0x9009200f, 0x9808990b, 
+    0x900640c8, 0x6800488e, 0x68094984, 0xd2074288, 0x68004882, 0x488a1e01, 0xebb06800, 0xe0050801, 
+    0x68014887, 0x6800487d, 0x0800ebb1, 0x3f80f5b8, 0xf5a8d301, 0x44c23880, 0xf00c9806, 0xe9cdf91f, 
+    0x46400104, 0xf91af00c, 0x4b7f2200, 0x0100e9cd, 0xf964f00c, 0x0102e9cd, 0x2304e9dd, 0xff06f00b, 
+    0x460e4605, 0x4b7a4a79, 0x46314628, 0xfa54f00c, 0x486cd212, 0x1c406800, 0x6008496a, 0x3233f04f, 
+    0x46284b74, 0xf00c4631, 0xd20cfa47, 0x68004865, 0x49641c40, 0xe0066008, 0x68004862, 0xda022800, 
+    0x49602000, 0x495f6008, 0x6809980c, 0xdd014288, 0xe001980c, 0x6800485b, 0xb12c900c, 0x4582980a, 
+    0x200bd302, 0x60084957, 0xb12843e0, 0x45829809, 0x200bd302, 0x60084953, 0x3233f04f, 0x46284b5d, 
+    0xf00c4631, 0xd303fa19, 0x6800484e, 0xdd7c280a, 0x78004859, 0xd0032802, 0x78004857, 0xd1392803, 
+    0x2001b39c, 0xf2407038, 0x060011f4, 0xfe3af7dd, 0x41caf64a, 0x7080f04f, 0xfde4f7dd, 0xf04f4651, 
+    0xf7dd7080, 0x2200fddf, 0x46284b4c, 0xf00c4631, 0xe9cdf8f5, 0xf00c0104, 0x4683f85d, 0xf04f4659, 
+    0xf7dd7080, 0x4837fdcf, 0xf04f6801, 0xf7dd7080, 0xf997fdc9, 0xf04f1000, 0xf7dd7080, 0x4934fdc3, 
+    0x7080f04f, 0xfdbef7dd, 0xe7ffe011, 0xf8892001, 0xe00c0000, 0x2001b144, 0x70084929, 0x78004822, 
+    0xf7ebb928, 0xe002fa3f, 0xf8892001, 0xf7dd0000, 0xf240fe09, 0xf04f11f4, 0xf7dd7080, 0xf64afdf3, 
+    0x182120aa, 0x7080f04f, 0xfd9cf7dd, 0x1000f997, 0x7080f04f, 0xfd96f7dd, 0x1000f999, 0x7080f04f, 
+    0xfd90f7dd, 0xf7dd4826, 0x4683fce9, 0xf04f4659, 0xf7dd7080, 0xf04ffd87, 0x4b1e3233, 0x46314628, 
+    0xf99af00c, 0x4641d240, 0xe0bbe000, 0x7080f04f, 0xfd78f7dd, 0x7080f04f, 0xe0339906, 0xd0035142, 
+    0xd03c80a4, 0xd003526a, 0x000361ee, 0x00052f88, 0x00038b38, 0x00038b28, 0xd0036118, 0x00038b30, 
+    0x00038b56, 0x00038b80, 0x00036344, 0x0bbbdead, 0xdcba01f5, 0x00048c18, 0x0005280c, 0x00038b2c, 
+    0x00038b34, 0x0003626a, 0x40140000, 0x9999999a, 0x3fa99999, 0x3fd33333, 0x00038b1c, 0x40c38800, 
+    0xd003502c, 0xfd3ef7dd, 0x680148fe, 0x7080f04f, 0xfd38f7dd, 0x680148fc, 0x7080f04f, 0xfd32f7dd, 
+    0xf04f49fa, 0xf7dd7080, 0xf242fd2d, 0xf7dd00c0, 0x48f7fd9d, 0xb3e07800, 0x49f62000, 0xb14c7008, 
+    0x780048f5, 0xd0032802, 0x780048f3, 0xd1012803, 0x70382000, 0x11f4f240, 0x7080f04f, 0xfd62f7dd, 
+    0x21bbf64a, 0x7080f04f, 0xfd0cf7dd, 0xf04f49e7, 0xf7dd7080, 0x48e9fd07, 0x1c407800, 0x0007f000, 
+    0x1000eb00, 0xeb0149e6, 0x68800080, 0x49e33020, 0x1c497809, 0x0107f001, 0x1101eb01, 0xeb024ae0, 
+    0x60880181, 0x980e49df, 0x48da6008, 0x0000f990, 0xe7ffe62e, 0x780048d8, 0xd0062802, 0x780048d6, 
+    0xd0022803, 0xf7e52003, 0xf240fdcd, 0xf04f11f4, 0xf7dd7080, 0xf64bfd27, 0xf04f31bb, 0xf7dd7080, 
+    0x4651fcd1, 0x7080f04f, 0xfcccf7dd, 0x680148ce, 0x7080f04f, 0xfcc6f7dd, 0xf04f49c4, 0xf7dd7080, 
+    0xe00efcc1, 0x680048c9, 0x600849c9, 0x680048bd, 0x600849bd, 0x1c409807, 0x98079007, 0xf4ff2832, 
+    0xbf00adbf, 0xf240b1dc, 0xf04f11f4, 0xf7dd7080, 0xf64bfcf9, 0xf04f31bd, 0xf7dd7080, 0x4651fca3, 
+    0x7080f04f, 0xfc9ef7dd, 0x680148b7, 0x7080f04f, 0xfc98f7dd, 0xf04f49ad, 0xf7dd7080, 0x48adfc93, 
+    0x0000f990, 0xe92de5d4, 0x460447fc, 0x20004689, 0x90009001, 0x48ab2700, 0xf9b46805, 0xf04f1000, 
+    0xf04f52a0, 0xf7dd7080, 0x48a2fc94, 0xb1207800, 0x49a82000, 0xe8bd6008, 0x48a287fc, 0xf4206800, 
+    0x49a020c0, 0x20016008, 0x600849a2, 0xfbcaf7e6, 0x48a14607, 0xb9108800, 0xf7e62000, 0x466bfbaa, 
+    0x4629aa01, 0xf7ff2000, 0x2002fd44, 0x60084999, 0x7800488f, 0x2000b1b0, 0xf2406008, 0xf04f11f4, 
+    0xf7dd7080, 0xf64ffc9f, 0xf04f71ff, 0xf7dd7080, 0x4986fc49, 0x7080f04f, 0xfc44f7dd, 0xf9904885, 
+    0xe7c80000, 0x498b2003, 0x20966008, 0x6008498b, 0x0000f89d, 0xd0772800, 0x49862004, 0x48866008, 
+    0x28008800, 0x2001d046, 0x60084984, 0xe03e2600, 0xf2402100, 0xf7e54000, 0x4875fc07, 0xb3987800, 
+    0x49742000, 0x90017008, 0x11f4f240, 0x7080f04f, 0xfc68f7dd, 0xf04f497a, 0xf7dd7080, 0x496bfc13, 
+    0x7080f04f, 0xfc0ef7dd, 0x7800486c, 0xf0001c40, 0xeb000007, 0x496a1000, 0x0080eb01, 0x30306880, 
+    0x78094966, 0xf0011c49, 0xeb010107, 0x4a641101, 0x0181eb02, 0x48636088, 0x20006005, 0x60084965, 
+    0xf990485c, 0xe7760000, 0x1c70e7ff, 0x2e96b206, 0xbf00dbbe, 0x495f2005, 0x48576008, 0xb9187800, 
+    0x8800485d, 0xd17d2801, 0x080af04f, 0x49592006, 0x466b6008, 0x4629aa01, 0xf7ff2001, 0x484cfcba, 
+    0xb1307800, 0x49532000, 0x484a6008, 0x0000f990, 0x2007e751, 0x6008494f, 0x080af04f, 0x78004851, 
+    0xd1022805, 0xe0064680, 0x484ee114, 0x28047800, 0xf04fd101, 0xf89d0803, 0x28000004, 0x484ad070, 
+    0xb1c07800, 0xfb9df003, 0x11f4f240, 0x7080f04f, 0xfbf8f7dd, 0x1123f24e, 0x7080f04f, 0xfba2f7dd, 
+    0xf04f4932, 0xf7dd7080, 0xf7e6fb9d, 0x4607fafb, 0xf7e62000, 0xf240fade, 0xf04f11f4, 0xf7dd7080, 
+    0xf649fbe1, 0xf04f0176, 0xf7dd7080, 0x4927fb8b, 0x7080f04f, 0xfb86f7dd, 0xe0af2600, 0xf7dd4833, 
+    0x4682fadd, 0x1e804831, 0xfad8f7dd, 0x401ff36a, 0x60084926, 0x68004608, 0x68094925, 0x45401a40, 
+    0x482bd304, 0xb9087800, 0xfffcf7ea, 0x68004823, 0x42b01f40, 0xf240d81d, 0xf04f11f4, 0xf7dd7080, 
+    0xe000fbb1, 0xf246e0bc, 0xf04f7189, 0xf7dd7080, 0x4631fb59, 0x7080f04f, 0xfb54f7dd, 0x68014813, 
+    0x7080f04f, 0xfb4ef7dd, 0xf04f4908, 0xf7dd7080, 0x4812fb49, 0x1e406800, 0xd12d42b0, 0xe0292001, 
+    0x0000e074, 0x00038b2c, 0x00038b28, 0xdcba01f5, 0x00036344, 0x00038b56, 0x00038b1c, 0x00038b38, 
+    0x00048c18, 0x0005280c, 0x00038b80, 0x00038b34, 0x00038b30, 0x00038b5c, 0x00038dc2, 0x00038b58, 
+    0x0ddddead, 0x0003626a, 0x00038db0, 0xd0036118, 0x000361ee, 0x700849fe, 0xf2402100, 0xf7e54000, 
+    0x48fcfaf3, 0xb3987800, 0x49f92000, 0x90017008, 0x11f4f240, 0x7080f04f, 0xfb54f7dd, 0xf04f49f6, 
+    0xf7dd7080, 0x49f5faff, 0x7080f04f, 0xfafaf7dd, 0x780048f3, 0xf0001c40, 0xeb000007, 0x49f11000, 
+    0x0080eb01, 0x30306880, 0x780949ed, 0xf0011c49, 0xeb010107, 0x4aeb1101, 0x0181eb02, 0x48ea6088, 
+    0x20006005, 0x600849e9, 0xf99048e1, 0xe6620000, 0x48e7e7ff, 0x49e76800, 0x1c766008, 0x680048e6, 
+    0xf4ff4286, 0x2003af4b, 0xfbbcf7e5, 0x780048d8, 0x48e2b1f8, 0xb1087800, 0xfab3f003, 0xfb22f7dd, 
+    0x11f4f240, 0x7080f04f, 0xfb0cf7dd, 0x41ccf64c, 0x7080f04f, 0xfab6f7dd, 0xf04f49d0, 0xf7dd7080, 
+    0x48d7fab1, 0xb1107800, 0x80202043, 0x2009e001, 0xe0058020, 0x880048d3, 0x4638b910, 0xf9e9f7e6, 
+    0x49ca2008, 0x48c26008, 0x28007800, 0x48ccd17d, 0xb9187800, 0x880048cb, 0xd1f72801, 0x46382600, 
+    0xf9d7f7e6, 0x780048c8, 0xf7eab908, 0x2000fecd, 0x700849c6, 0xf7e52002, 0x200afb5a, 0x600849bb, 
+    0x22082301, 0x48c20151, 0xffd9f7e3, 0x49b72009, 0xe0056008, 0x22092301, 0x48bd0259, 0xffcff7e3, 
+    0x21402206, 0x38fa48ba, 0xffe0f7e3, 0xd1f12800, 0xf7dd48b8, 0x4606f9c3, 0x0002f006, 0xf006b918, 
+    0x28000001, 0x2001d173, 0x700849a1, 0xf7e52002, 0x48aafb49, 0xb1087800, 0xfa43f003, 0x11f4f240, 
+    0x7080f04f, 0xfa9ef7dd, 0xf04f49ab, 0xf7dd7080, 0x48a7fa49, 0xf7dd38fa, 0xea40f9a1, 0x46414806, 
+    0x7080f04f, 0xfa3ef7dd, 0xf04f4994, 0xf7dd7080, 0x4890fa39, 0xb3a07800, 0x498d2000, 0xf2407008, 
+    0xf04f11f4, 0xf7dd7080, 0x499cfa7d, 0x7080f04f, 0xfa28f7dd, 0xf04f4989, 0xf7dd7080, 0x4888fa23, 
+    0x1c407800, 0x0007f000, 0xe031e000, 0x1000eb00, 0xeb014984, 0x68800080, 0x49813030, 0x1c497809, 
+    0x0107f001, 0x1101eb01, 0xeb024a7e, 0x60880181, 0x6005487d, 0x497d2000, 0x48756008, 0x0000f990, 
+    0xe7ffe589, 0x78004872, 0x487db180, 0xb1107800, 0x80202043, 0x2009e001, 0x48738020, 0x20006005, 
+    0x60084972, 0xf990486a, 0xe5740000, 0xbf00e7ff, 0x6005486d, 0x496d2000, 0x48656008, 0x0000f990, 
+    0xb57ce569, 0x460e4605, 0xf2408ea8, 0x1a815219, 0xd06f4290, 0xf240dc29, 0xeba05206, 0x42900102, 
+    0xdc13d069, 0x6f9ff5b0, 0xdc06d073, 0xf2a0b388, 0xb3784064, 0xd16d2801, 0xf2a0e058, 0x280040f9, 
+    0x2807d069, 0x2808d068, 0xe131d1f5, 0xd07d290c, 0x2901dc06, 0x2906d07b, 0x2907d07a, 0xe179d1eb, 
+    0xd076290d, 0xd1e62912, 0x2918e1b6, 0xdc12d072, 0xd070290c, 0x2905dc06, 0x2906d06e, 0x290bd06d, 
+    0xe1f9d1d9, 0xd0692911, 0xd0682912, 0xd1d22917, 0xe00fe242, 0x2926e01d, 0xdc06d076, 0xd074291d, 
+    0xd073291e, 0xd1c62925, 0x2929e289, 0x292ad06f, 0xe2c0d1c1, 0xf04fe2c3, 0x494932ff, 0x68004849, 
+    0xfbccf004, 0x1d204604, 0xf240b950, 0x86a84064, 0x2200bd7c, 0x48434942, 0xf0046800, 0x4604fbbf, 
+    0xb9201d60, 0x4065f240, 0xe7f186a8, 0x2c012401, 0xe2a4d002, 0xe0f6e17e, 0x88004839, 0xd10c280f, 
+    0x4b3a4839, 0x492e4a3a, 0x48359000, 0xf8e8f7ff, 0xe096e295, 0xe0a2e294, 0x4831e0bc, 0x283f8800, 
+    0x4823d170, 0x4b334923, 0xe9cd4a33, 0x49241000, 0xf7ff482b, 0x4831f935, 0xb9208800, 0xf7e52002, 
+    0x2800fa4c, 0x4813d17c, 0xe0097800, 0xe0d8e11d, 0xe128e0f2, 0xe19de1ed, 0xe174e167, 0xe1c2e1b5, 
+    0xd1ef2800, 0x88004826, 0xb2001c40, 0x80084924, 0x49082001, 0x20437008, 0x80084919, 0x78004810, 
+    0xd0432802, 0xe03e480e, 0xe1ede226, 0xe245e1f9, 0x00038b56, 0x00036344, 0x0ddddead, 0xdcba01f5, 
+    0x00038b38, 0x00048c18, 0x0005280c, 0x00038b5c, 0x00038b34, 0x00038b30, 0x00038b58, 0x00038db0, 
+    0x00038b1c, 0x00038dc2, 0x000361ee, 0x00038b57, 0xd0035126, 0xd0060040, 0x00011104, 0x0eeedead, 
+    0x00038b78, 0x00038b18, 0x00038b48, 0x00038b44, 0x00038b40, 0x00038b2c, 0x00038b28, 0x00038b20, 
+    0x00038b70, 0x7800e02d, 0xd10c2803, 0x880048fa, 0xb2001c40, 0x800849f8, 0x03c82101, 0xf8b4f7e5, 
+    0xf7fe2000, 0x2200ff4f, 0x48f549f4, 0xf0046800, 0x4604fae3, 0xb9581d20, 0x40f8f240, 0xe74786a8, 
+    0x2200e152, 0x48ee49ed, 0xf0046800, 0x4604fad5, 0x28001d60, 0xf240d185, 0x86a840f9, 0x2401e738, 
+    0x48e6e1ec, 0x28438800, 0x48e6d124, 0x4ae74be6, 0x900049e7, 0xf00048e1, 0x2200f9f9, 0x48e049df, 
+    0xf0046800, 0x4604fab9, 0xb9501d20, 0x5000f240, 0xe71d86a8, 0x49d92200, 0x680048d9, 0xfaacf004, 
+    0x1d604604, 0xd1db2800, 0x5001f240, 0xe70f86a8, 0xe1c32401, 0x880048d1, 0xd1242844, 0x230048d1, 
+    0x49d24ad1, 0x48cd9000, 0xfc4af000, 0x49cb2200, 0x680048cb, 0xfa90f004, 0x1d204604, 0xf240b950, 
+    0x86a85006, 0x2200e6f4, 0x48c549c4, 0xf0046800, 0x4604fa83, 0x28001d60, 0xf240d1b2, 0x86a85007, 
+    0x2401e6e6, 0x48bde19a, 0x28458800, 0x2300d124, 0x680248bd, 0x680148bd, 0xf00148b8, 0x2200fc63, 
+    0x48b749b6, 0xf0046800, 0x4604fa67, 0xb9501d20, 0x500cf240, 0xe6cb86a8, 0x49b02200, 0x680048b0, 
+    0xfa5af004, 0x1d604604, 0xd1892800, 0x500df240, 0xe6bd86a8, 0xe1712401, 0x880048a8, 0xd1242846, 
+    0x4aaa4ba8, 0xf99048aa, 0x48a41000, 0xffbef001, 0x49a22200, 0x680048a2, 0xfa3ef004, 0x1d204604, 
+    0xf240b950, 0x86a85012, 0x2200e6a2, 0x489c499b, 0xf0046800, 0x4604fa31, 0x28001d60, 0xf240d189, 
+    0x86a85013, 0x2401e694, 0x4894e148, 0x28488800, 0x4897d122, 0x1000f990, 0xf0024890, 0x2200f97a, 
+    0x4894498e, 0xf0046800, 0x4604fa17, 0xb9501d20, 0x5018f240, 0xe67b86a8, 0x49882200, 0x6800488d, 
+    0xfa0af004, 0x1d604604, 0xd18b2800, 0x5019f240, 0xe66d86a8, 0xe1212401, 0x88004880, 0xd1242849, 
+    0x4a824b80, 0xf9904882, 0x487c1000, 0xf992f002, 0x497a2200, 0x6800487a, 0xf9eef004, 0x1d204604, 
+    0xf240b950, 0x86a8501e, 0x2200e652, 0x48744973, 0xf0046800, 0x4604f9e1, 0x28001d60, 0xf240d18b, 
+    0x86a8501f, 0x2401e644, 0x486ce0f8, 0x284a8800, 0x486fd122, 0x1000f990, 0xf0024868, 0x2200f9b9, 
+    0x486c4966, 0xf0046800, 0x4604f9c7, 0xb9501d20, 0x5024f240, 0xe62b86a8, 0x49602200, 0x68004865, 
+    0xf9baf004, 0x1d604604, 0xd18d2800, 0x5025f240, 0xe61d86a8, 0xe0d12401, 0x88004858, 0xd124284c, 
+    0x4a5a4b58, 0xf990485a, 0x48541000, 0xfaaaf002, 0x49522200, 0x68004852, 0xf99ef004, 0x1d204604, 
+    0xf240b950, 0x86a8502a, 0x2200e602, 0x484c494b, 0xf0046800, 0x4604f991, 0x28001d60, 0xf240d104, 
+    0x86a8502b, 0x2401e5f4, 0x4844e0a8, 0x284d8800, 0x4847d121, 0x1000f990, 0xf0024840, 0x2200fd10, 
+    0x4844493e, 0xf0046800, 0x4604f977, 0xb9501d20, 0x5030f240, 0xe5db86a8, 0x49382200, 0x6800483d, 
+    0xf96af004, 0x1d604604, 0xf240bb60, 0x86a85031, 0x2401e5ce, 0x4831e082, 0x28478800, 0x4833d123, 
+    0x48336802, 0x1000f990, 0xf002482c, 0x2200fb09, 0x482b492a, 0xf0046800, 0x4604f94f, 0xb9501d20, 
+    0x5036f240, 0xe5b386a8, 0x49242200, 0x68004824, 0xf942f004, 0x1d604604, 0xf240b920, 0x86a85037, 
+    0x2401e5a6, 0x481de05a, 0x283e8800, 0x4820d155, 0x1000f990, 0xf7ff4819, 0xb360fa86, 0x88004817, 
+    0xd11b2809, 0x49152200, 0x6800481b, 0xf924f004, 0x1d204604, 0xf240b950, 0x86a8503e, 0x2200e588, 
+    0x4815490e, 0xf0046800, 0x4604f917, 0xb9901d60, 0x503ff240, 0xe57b86a8, 0xe02f2401, 0x49072200, 
+    0x68004807, 0xf908f004, 0x1d204604, 0xf240b9e8, 0x86a85042, 0xe021e56c, 0x00038b72, 0x00038b78, 
+    0x00038b18, 0x00038b48, 0x00038b44, 0x00038b40, 0x00038b1c, 0x0003860c, 0x00038654, 0x49112200, 
+    0x68004811, 0xf8e8f004, 0x1d604604, 0xf240b930, 0x86a85043, 0x2401e54c, 0xe000e000, 0xe53abf00, 
+    0xbf00bf00, 0xb510e544, 0x21012200, 0x604df2af, 0xfe65f003, 0x20042108, 0xf802f004, 0x60084902, 
+    0x0000bd10, 0x00038b78, 0x00038b18, 0x5ffce92d, 0x460c4607, 0x46994690, 0xa3f4f8df, 0x6b00f50a, 
+    0x780048fc, 0xf002b108, 0xf9b7fe8c, 0xf04f1000, 0xf04f52a0, 0xf7dc7080, 0x2000feac, 0xfdd9f7e5, 
+    0x220c2300, 0x0100f24f, 0xf7e348f3, 0x2300fbc1, 0xf6402208, 0x48f07100, 0xfbbaf7e3, 0x22042300, 
+    0x48ed21f0, 0xfbb4f7e3, 0x461a2300, 0x48ea210f, 0xfbaef7e3, 0x48e92100, 0xfdd6f7dc, 0x23102000, 
+    0x46014602, 0xf7e89000, 0x2000f871, 0x700849e4, 0xfec8f7dc, 0x680048e3, 0x600849e3, 0xfedbf7e4, 
+    0x600849e0, 0x780048e1, 0x7820b940, 0xd0052803, 0xfae8f7ea, 0x46082100, 0xfe0df7e6, 0x22082300, 
+    0x48db0151, 0xfbabf7e3, 0x2301e005, 0x02592209, 0xf7e348d7, 0x2206fba4, 0x48d52140, 0xf7e338fa, 
+    0x2800fbb5, 0x2601d1f1, 0x780048d2, 0xd1012805, 0xe0042602, 0x780048cf, 0xd1002804, 0x78202604, 
+    0xd1212803, 0xf9b048cc, 0x28010000, 0x2203da0c, 0x48ca2108, 0xfb9af7e3, 0x2203b170, 0x48c72108, 
+    0xf7e31c80, 0xb138fb93, 0xfb0648c5, 0x2200f100, 0xf7e42002, 0xe036fe99, 0xfb0648c2, 0x2200f100, 
+    0xf7e42002, 0xe02efe91, 0x28027820, 0x48bad121, 0x0000f9b0, 0xda0c2801, 0x21082203, 0xf7e348b7, 
+    0xb170fb75, 0x21082203, 0x1c8048b4, 0xfb6ef7e3, 0x48b3b138, 0xf100fb06, 0x20022200, 0xfe74f7e4, 
+    0x48b1e011, 0xf100fb06, 0x20022200, 0xfe6cf7e4, 0x7820e009, 0xd1062805, 0xfb0648ac, 0x2200f100, 
+    0xf7e42002, 0x2100fe61, 0xf7e42002, 0xf04ffe10, 0xf8c830ff, 0x20000000, 0x0000f8c9, 0x680048a4, 
+    0x49a31c40, 0x48a36008, 0x1c408800, 0x49a1b200, 0x489f8008, 0xb2018800, 0x30184895, 0xfd24f7dc, 
+    0x1000f240, 0x8008499c, 0x499c2081, 0xf7e48008, 0x4997fe32, 0xf0017809, 0xeb010107, 0x4a981101, 
+    0x0181eb02, 0x20076308, 0xfe0af7e4, 0x78094990, 0x0107f001, 0x1101eb01, 0xeb024a91, 0x63480181, 
+    0x6800488b, 0x7809498a, 0x0107f001, 0x1101eb01, 0x0181eb02, 0x488b6388, 0x49858800, 0xf0017809, 
+    0xeb010107, 0xeb021101, 0x63c80181, 0x68004886, 0x7809497f, 0x0107f001, 0x1101eb01, 0x0181eb02, 
+    0xf7e36408, 0x2200fea6, 0x4880213f, 0xfaeef7e3, 0xdb012811, 0xe0002001, 0x497d2000, 0x23018008, 
+    0x0299220a, 0x3830486a, 0xfac9f7e3, 0x220a2300, 0x4100f240, 0x38304866, 0xfac1f7e3, 0x78004875, 
+    0x2000b910, 0xfbdef7fe, 0x78114a62, 0x0000f994, 0xfe0ff7df, 0xfbbaf7fe, 0x220f2300, 0x486f496e, 
+    0xfaadf7e3, 0xf6402000, 0x46020300, 0x90004601, 0xff4cf7e7, 0x220c2301, 0x48680319, 0xfa9ff7e3, 
+    0x220e2301, 0x48660399, 0xfa99f7e3, 0x28027820, 0x2001d117, 0xfc45f7fa, 0x20012100, 0xfea9f7e5, 
+    0xf7fa2007, 0x2301fb90, 0x46192200, 0xf7e3485d, 0x2000fa86, 0xfaccf7fa, 0x1000f240, 0xf86ff7e3, 
+    0x7820e053, 0xd11c2803, 0x88004851, 0xd1142801, 0xf9904855, 0x23085000, 0x46292200, 0xe9cd4610, 
+    0xf7e2ab00, 0x4851fefe, 0x23024951, 0xe9cd2200, 0x46291000, 0xf7e22001, 0x2004fef4, 0xfaa8f7fa, 
+    0x7820e033, 0xd1302805, 0xf7fa2007, 0x2301fb5c, 0x46192200, 0xf7e34843, 0x2002fa52, 0xfd50f7e4, 
+    0x60084944, 0x49442002, 0x20007008, 0xfa90f7fa, 0x49422220, 0xf0094842, 0x2500fa26, 0x493be00f, 
+    0x2045eb01, 0xeb024a3a, 0x23022145, 0xe9cd2200, 0x46291000, 0xf7e22001, 0x1c68fec4, 0x2d04b245, 
+    0xf240dbed, 0xf7e31000, 0xf240f81a, 0xf04f11f4, 0xf7dc7080, 0xf243fd17, 0xf04f3100, 0xf7dc7080, 
+    0x4830fcc1, 0x1000f990, 0x7080f04f, 0xfcbaf7dc, 0x6801482d, 0x7080f04f, 0xfcb4f7dc, 0xf04f492b, 
+    0xf7dc7080, 0x2044fcaf, 0xe8bd8038, 0x00009ffc, 0x00043078, 0x00038db0, 0xd180004c, 0xd0031034, 
+    0x00038a5a, 0x00038b90, 0x00038b8c, 0x000361ee, 0xd0035126, 0x0003626a, 0x00038b8a, 0xd28e0078, 
+    0x017d7840, 0x00aba950, 0x0094c5f0, 0x03b9aca0, 0x00038b38, 0x00038b74, 0x00038d98, 0x00038d9a, 
+    0x00048c18, 0x000362d8, 0x000362e4, 0xd0034200, 0x00038b88, 0x00036344, 0xffff8000, 0xd0035026, 
+    0xd0030416, 0xd00305ae, 0x00036240, 0x00044b08, 0x00044308, 0x00036310, 0x0003630c, 0x0004cc48, 
+    0x00038e90, 0x00038b1c, 0x000361dc, 0xdcba01f5, 0x4604b5f0, 0xf04f460d, 0xe01e30ff, 0xe0182100, 
+    0x4ffa1816, 0x7000f9b7, 0x6607fb01, 0x6026f853, 0x42be6827, 0x1816d30b, 0xf9b74ff4, 0xfb017000, 
+    0xf8536607, 0x60266026, 0xb2361816, 0x1c4e802e, 0x2904b231, 0x1c46dbe4, 0x2801b230, 0xbdf0ddde, 
+    0x4fffe92d, 0x460db09f, 0x90192000, 0x83a0f8df, 0x93a0f8df, 0x900d2019, 0x900c48e7, 0x6000f500, 
+    0x48e6900b, 0x981f900a, 0x1000f9b0, 0x52a0f04f, 0x7080f04f, 0xfc2df7dc, 0x1000f240, 0x800849e0, 
+    0x49da2081, 0x48df8008, 0x28057800, 0x48ddd003, 0x28047800, 0x2100d104, 0x3000f44f, 0xfbe4f7e4, 
+    0xe0042400, 0xf8482000, 0x1c600024, 0xf5b4b204, 0xdbf76f80, 0x28009822, 0x48d3d17b, 0x28037800, 
+    0x2101d116, 0xf7e403c8, 0x48d0fbcf, 0xb9087800, 0xf82af7ea, 0x880048ce, 0xd1042801, 0x03802100, 
+    0xfbc2f7e4, 0x2100e004, 0x0000f248, 0xfbbcf7e4, 0x780048c5, 0xd0072803, 0x780048c3, 0xd0032802, 
+    0x780048c1, 0xd1412805, 0xf7dc48c2, 0x9009fb27, 0xf44f2100, 0xf7e43000, 0x9809fba7, 0x0004f000, 
+    0xf64fb198, 0x980972fb, 0xb2014010, 0xf7dc48b9, 0x48b4fb1b, 0x28037800, 0x48b3d107, 0x28027800, 
+    0x2100d103, 0xf7e40400, 0x48b2fb8f, 0xfb06f7dc, 0x98099009, 0x0080f000, 0xf64fb138, 0x9809727f, 
+    0xb2014010, 0xf7dc48ab, 0x48aafaff, 0xfaf6f7dc, 0x98099009, 0x5080f400, 0xf64eb138, 0x980972ff, 
+    0xb2014010, 0xf7dc48a3, 0xbf00faef, 0x7800489e, 0xd10e2805, 0xf44f2100, 0xf7e43000, 0x2100fb65, 
+    0x3000f44f, 0xfb60f7e4, 0xf44f2100, 0xf7e43000, 0x4895fb5b, 0x28027800, 0x4893d003, 0x28057800, 
+    0xf7e6d106, 0xb200fd06, 0x20089018, 0xfcf7f7e6, 0x00c0f242, 0xfbdaf7dc, 0xe0b32700, 0xdb002f00, 
+    0x2000bf00, 0xe094901e, 0x00c0f242, 0xfbcef7dc, 0x02822001, 0x4b822105, 0x3000f9b3, 0x3100e9cd, 
+    0x2002e9cd, 0x1e822300, 0x487c2108, 0xfeccf7f8, 0xe0782600, 0xeb01990a, 0x230c2046, 0xf9b14978, 
+    0x497d2000, 0xf89df009, 0x497c2008, 0x4a7d4b7c, 0x1000e9cd, 0x99194878, 0xf9a0f009, 0xe02b2400, 
+    0xf8504878, 0x49770024, 0x1024f851, 0x3001fb80, 0xf8514973, 0x4a721024, 0x2024f852, 0x1202fb81, 
+    0x41501859, 0xe9c24a70, 0x48601000, 0x0000f9b0, 0x4000fb06, 0x2020f858, 0xe9d0486b, 0x02831000, 
+    0x5091ea43, 0x49594410, 0x1000f9b1, 0x4101fb06, 0x0021f848, 0xb2041c60, 0xf9b04854, 0x42840000, 
+    0x2100dbce, 0xf9b24a51, 0xfb062000, 0xf848f002, 0x48551020, 0x28027800, 0x4853d003, 0x28057800, 
+    0x2100d10b, 0xf9b04849, 0x43700000, 0xf9b24a4c, 0xeb002000, 0xf8480062, 0x982c1020, 0x49486800, 
+    0x1000f9b1, 0x0fa1ebb0, 0x2100d10b, 0xf9b0483f, 0x43700000, 0xf9b24a42, 0xeb002000, 0xf84800a2, 
+    0x1c701020, 0x2e04b246, 0x981edb84, 0xb2001c40, 0x981e901e, 0xf6ff2802, 0xb98faf67, 0xab0fa80e, 
+    0x4649aa14, 0x46409000, 0xf9bbf7fe, 0x0038f9bd, 0xf9b1492e, 0xfb901000, 0xb200f0f1, 0x8008493b, 
+    0xb2071c78, 0xf6ff2f01, 0xf242af49, 0xf7dc00c0, 0x482dfb1d, 0x28027800, 0x482bd003, 0x28057800, 
+    0x9918d103, 0xf7e6b2c8, 0x2000fc2a, 0x1e409013, 0x8008492f, 0x6800482f, 0xd3362812, 0x28009822, 
+    0x4822d17e, 0x28007800, 0x481fd17a, 0x28027800, 0xf240d176, 0x05c011f4, 0xfad4f7dc, 0x1199f641, 
+    0x7080f04f, 0xfa7ef7dc, 0xf9904823, 0xf04f1000, 0xf7dc7080, 0xf9bdfa77, 0xf04f1038, 0xf7dc7080, 
+    0x481afa71, 0x1000f9b0, 0x7080f04f, 0xfa6af7dc, 0xf9904819, 0x49150000, 0x1000f9b1, 0xd17d4288, 
+    0xf8dd2400, 0x2600a050, 0xe13de04e, 0x00038d9a, 0x00036354, 0x00037354, 0x00043078, 0x00054000, 
+    0x00038d98, 0x0003626a, 0x00038b1c, 0x000361ee, 0x00038b88, 0xd03c80b6, 0x00045308, 0x0002fcd0, 
+    0x00048308, 0x00047b08, 0x00038da8, 0x00038da4, 0x00038d9e, 0x000361dc, 0x000362b1, 0x003cf9bd, 
+    0xf9b24af9, 0xfb062000, 0xf8580002, 0xf04f1020, 0xf7dc7080, 0xf9bdfa27, 0x49f3003c, 0x1000f9b1, 
+    0x0001fb06, 0x0020f858, 0xda0b4550, 0x003cf9bd, 0xf9b149ed, 0xfb061000, 0xf8580001, 0xe000a020, 
+    0x4634e03d, 0xb2461c70, 0xdbd72e04, 0xf04f4621, 0xf7dc7080, 0xf9bdfa07, 0xf04f103c, 0xf7dc7080, 
+    0xf7e9fa01, 0x901bfd3f, 0x49e0b260, 0x991b7008, 0xb2091408, 0xf955f7ea, 0xf99048dc, 0xf7e90000, 
+    0x2001fceb, 0x700849da, 0xf7e92002, 0x48d7ff97, 0x0000f990, 0xfd56f7e9, 0xe00048d4, 0xf990e00a, 
+    0xf7ea0000, 0x48d1f931, 0x1000f990, 0x7080f04f, 0xf9d8f7dc, 0xf04f49cf, 0xf7dc7080, 0x48cef9d3, 
+    0xbbe88800, 0x003cf9bd, 0xfb902103, 0xb200f0f1, 0x4643901d, 0xa81349c9, 0xf7ff9a1d, 0x48c8fd69, 
+    0x0000f9b0, 0x103cf9bd, 0x21031a40, 0xf0f1fb90, 0x901db200, 0x203cf9bd, 0x1a88991d, 0xdb012800, 
+    0xe0004601, 0x29054241, 0x4643db05, 0xa81349bb, 0xf7ff9a1d, 0xf8ddfd4d, 0x48b8b04c, 0x0000f9b0, 
+    0x800849b8, 0x003cf9bd, 0x71d0eb00, 0x911d1049, 0x49b24643, 0x9a1da813, 0xfd3af7ff, 0xe00049b0, 
+    0xf9b1e01a, 0xf9bd1000, 0x1a88203c, 0x71d0eb00, 0xb2091049, 0xf9bd911d, 0x991d203c, 0x28001a88, 
+    0x4601db01, 0x4241e000, 0xdb052905, 0x49a34643, 0x9a1da813, 0xfd1cf7ff, 0xf9b048a0, 0x980d1000, 
+    0xda044281, 0x90132000, 0x499c1e40, 0xf8bd8008, 0x0040003c, 0x901db200, 0xf9b04899, 0x21010000, 
+    0x00a0eb01, 0x103cf9bd, 0xdc094288, 0xf9b04894, 0xf9bd0000, 0x2202103c, 0x0011fb02, 0x901db200, 
+    0x003cf9bd, 0xdc05287d, 0x498c4643, 0x9a1da813, 0xfceef7ff, 0x901c981d, 0x90129813, 0x003cf8bd, 
+    0x0040eb00, 0x901db200, 0x003cf9bd, 0xdb09282b, 0xf9b04883, 0xf9bd0000, 0x2203103c, 0x0011fb02, 
+    0x901db200, 0x003cf9bd, 0xdc0d2845, 0x003cf9bd, 0xf9b1497b, 0xebb01000, 0xd0050fa1, 0x49774643, 
+    0x9a1da813, 0xfcc4f7ff, 0xb2019815, 0xf7dc4876, 0x4875f87b, 0x99111c80, 0xf876f7dc, 0x1c409810, 
+    0x4871b201, 0xf7dc1d00, 0x9814f86f, 0xb2010a40, 0x1d80486d, 0xf868f7dc, 0x103cf9bd, 0x300a486a, 
+    0xf862f7dc, 0x11f4f240, 0x7080f04f, 0xf94af7dc, 0x7177f240, 0x7080f04f, 0xf8f4f7dc, 0x68014863, 
+    0x7080f04f, 0xf8eef7dc, 0x103cf9bd, 0x7080f04f, 0xf8e8f7dc, 0x0a019814, 0x7080f04f, 0xf8e2f7dc, 
+    0xf04f4954, 0xf7dc7080, 0x4958f8dd, 0xf0017809, 0xeb010107, 0x4a561101, 0x0181eb02, 0x60c89815, 
+    0x78094952, 0x0107f001, 0x1101eb01, 0x0181eb02, 0x61089811, 0x7809494d, 0x0107f001, 0x1101eb01, 
+    0x0181eb02, 0x61489810, 0x003cf9bd, 0x78094947, 0x0107f001, 0x1101eb01, 0x0181eb02, 0xf9bd61c8, 
+    0x49420038, 0xf0017809, 0xeb010107, 0xeb021101, 0x62080181, 0x0a409814, 0x7809493c, 0x0107f001, 
+    0x1101eb01, 0x0181eb02, 0x20006188, 0x78094937, 0x0107f001, 0x1101eb01, 0x0181eb02, 0x48306248, 
+    0x0000f9b0, 0x60281080, 0x98212100, 0x20006001, 0x80084930, 0x80084930, 0x78004830, 0xd1012803, 
+    0xe0002032, 0x90172004, 0x7800482c, 0xd1022803, 0x10f4f240, 0x200ae000, 0x99149016, 0xebb09817, 
+    0xd24d2f51, 0x003cf9bd, 0xf9bd9011, 0x6028003c, 0x0a419814, 0x60019821, 0x0038f9bd, 0x98109010, 
+    0x42401c40, 0x4818b201, 0xf7db1d00, 0x481bffbd, 0x28037800, 0x9913d10e, 0xebb09816, 0xd8632f11, 
+    0xf9b0480e, 0x980d1000, 0xdb5d4281, 0x49112001, 0xe0598008, 0x98169913, 0x2f11ebb0, 0x2001d854, 
+    0x8008490c, 0x0000e050, 0x00038d9a, 0x000362b1, 0x000362af, 0xdcba01f5, 0x00038b8a, 0x00038d9e, 
+    0x00038d98, 0x00038da2, 0xd03c80a8, 0x00038b38, 0x00048c18, 0x00038d9c, 0x00038da0, 0x00038b1c, 
+    0x780048fe, 0xd1192803, 0x6800982c, 0xb9401c40, 0xf9b048fb, 0x10400000, 0x20006028, 0x800849f9, 
+    0x982ce01b, 0x60286800, 0xf9b048f5, 0x10400000, 0x800849f5, 0x49f32001, 0xe00e8008, 0x680048f3, 
+    0xdb022801, 0x60282080, 0xf04fe002, 0x602830ff, 0x49ec2000, 0x49ee8008, 0x98108008, 0x30b8f600, 
+    0x48ecb201, 0xff50f7db, 0x680048eb, 0xd37d2812, 0x003cf9bd, 0xf9b149e2, 0xebb01000, 0xd10b0fa1, 
+    0x880048e0, 0x48deb940, 0x0000f9b0, 0x49de1040, 0x20018008, 0x800849db, 0x780048d8, 0xd11d2803, 
+    0x003cf9bd, 0xf9b149d6, 0xebb01000, 0xd0090f61, 0xf9b048d3, 0x21010000, 0x0060ebc1, 0x103cf9bd, 
+    0xd10b4288, 0x880048cf, 0x48cdb940, 0x0000f9b0, 0x49cd1080, 0x20018008, 0x800849ca, 0x103cf9bd, 
+    0x4281980d, 0x2000dc04, 0x800849c6, 0x800849c8, 0x780048c2, 0xd1592803, 0x880048c2, 0x982cb938, 
+    0xb2008800, 0x800849c0, 0x49be2001, 0x48c38008, 0x28018800, 0x48c2d14a, 0x6000f990, 0xb2048828, 
+    0xd10b2c80, 0xe0062700, 0x01fa2100, 0xf820980b, 0x1c781012, 0x2f08b207, 0xe010dbf6, 0xe00c2700, 
+    0xeb042100, 0x980c12c7, 0x1012f820, 0x12c7eb04, 0xf820980b, 0x1c781012, 0x2f08b207, 0x2208dbf0, 
+    0x010be9dd, 0xe9cd2300, 0xe0002100, 0x9002e068, 0x4631461a, 0xf7e24618, 0x2c80f887, 0x2000d103, 
+    0x800849a8, 0x2000e006, 0xf82149a7, 0x49a50014, 0x0014f821, 0x49a448a3, 0x23002202, 0x2100e9cd, 
+    0x461a9002, 0x20014631, 0xf86ef7e2, 0xf9b0489f, 0x49950000, 0x1000f9b1, 0xd04d4288, 0x88004891, 
+    0x488ebbf0, 0x28037800, 0x2005d10d, 0x2f5bebb0, 0x4896d842, 0x1000f9b0, 0x4281980d, 0x2001db3c, 
+    0x8008498b, 0xea4fe038, 0xb348205b, 0xf9b0488f, 0x980d1000, 0xdb2f4281, 0x49852001, 0xf2408008, 
+    0x060011f4, 0xff6ef7db, 0x5122f245, 0x7080f04f, 0xff18f7db, 0xf9b0487e, 0xf04f1000, 0xf7db7080, 
+    0xea4fff11, 0xf04f215b, 0xf7db7080, 0x4876ff0b, 0x1000f9b0, 0x7080f04f, 0xff04f7db, 0xe000487b, 
+    0xf9b0e00a, 0xf04f1000, 0xf7db7080, 0x4978fefb, 0x7080f04f, 0xfef6f7db, 0x28009822, 0xf04fd07e, 
+    0xf2400a00, 0x901a70d0, 0xf04f1081, 0xf7db7080, 0xf243ff39, 0xf04f3111, 0xf7db7080, 0xf04ffee3, 
+    0x991a7080, 0xfedef7db, 0x7801486a, 0x7080f04f, 0xfed8f7db, 0x71d0f240, 0x7080f04f, 0xfed2f7db, 
+    0xf04f4963, 0xf7db7080, 0xf9bdfecd, 0x2819003c, 0x981ada02, 0x901a0040, 0x981a9914, 0x2f51ebb0, 
+    0x2403d27d, 0x485ce047, 0x0000f9b0, 0xf9bd3808, 0x4288103c, 0xf9bddb17, 0x4958003c, 0x4a568809, 
+    0xfb118812, 0x44200002, 0x0020f859, 0xdb0a4550, 0x103cf9bd, 0x88004851, 0x88124a4f, 0x1002fb10, 
+    0xf8594420, 0xf9bda020, 0x493d003c, 0x1000f9b1, 0x0f61ebb0, 0xf9bdd007, 0x4939003c, 0x1000f9b1, 
+    0x0fa1ebb0, 0x4845d115, 0x49438800, 0xfb108809, 0x3012f001, 0xf8594420, 0x45500020, 0x483fdb09, 
+    0x493d8800, 0xfb108809, 0x3012f001, 0xf8594420, 0x1ca0a020, 0x2c07b204, 0xe000ddb5, 0xf06fe0fc, 
+    0xe0490402, 0x003cf9bd, 0xdc172807, 0x103cf9bd, 0x88004832, 0x88124a30, 0x1002fb10, 0xf8594420, 
+    0x45500020, 0xf9bddb0a, 0x482c103c, 0x4a2a8800, 0xfb108812, 0x44201002, 0xa020f859, 0x003cf9bd, 
+    0xf9b14917, 0xebb01000, 0xd00d0f61, 0x003cf9bd, 0xf9b14913, 0xebb01000, 0xd0050fa1, 0xe042e000, 
+    0x003cf9bd, 0xdc152802, 0x8800481c, 0x8809491a, 0xf001fb10, 0x44203017, 0x0020f859, 0xdb094550, 
+    0x88004816, 0x88094914, 0xf001fb10, 0x44203017, 0xa020f859, 0xb2041ca0, 0x0000e022, 0x00038b1c, 
+    0x00038d98, 0x00038d9c, 0x00038d9e, 0x00038b38, 0x00038da0, 0xd03c80ac, 0x000361dc, 0x00038b88, 
+    0x00036240, 0x00044b08, 0x00044308, 0x00038da2, 0xdcba01f5, 0x00036226, 0x00038d9a, 0x00038da4, 
+    0x0f07f114, 0x2400dd8e, 0x003cf9bd, 0xf9b149f6, 0xebb01000, 0xd0070f61, 0x003cf9bd, 0xf9b149f2, 
+    0xebb01000, 0xd1000fa1, 0xf9bd2402, 0x48ef103c, 0x4aef8800, 0xfb108812, 0xf8581002, 0x1d610020, 
+    0x45504108, 0x9914db04, 0xebb0981a, 0xd3022f51, 0x98212100, 0x20006001, 0x700849e6, 0x68009821, 
+    0xdd0c2800, 0x003cf9bd, 0xdb08281c, 0x003cf9bd, 0xdc042824, 0x780048e0, 0x2001b908, 0xf2407008, 
+    0x981371d0, 0x2f50ebb1, 0x2000d302, 0x800849db, 0x70d0f240, 0x2f5bebb0, 0x2000d302, 0x800849d8, 
+    0x11f4f240, 0x7080f04f, 0xfdfcf7db, 0x1122f241, 0x7080f04f, 0xfda6f7db, 0xf99048ce, 0xf04f1000, 
+    0xf7db7080, 0xf04ffd9f, 0x991a7080, 0xfd9af7db, 0x0a419814, 0x7080f04f, 0xfd94f7db, 0x103cf9bd, 
+    0x7080f04f, 0xfd8ef7db, 0xf04f4651, 0xf7db7080, 0x48c2fd89, 0x1000f9b0, 0x7080f04f, 0xfd82f7db, 
+    0xf9b048bf, 0xf04f1000, 0xf7db7080, 0x49bdfd7b, 0x7080f04f, 0xfd76f7db, 0x98179914, 0x2f51ebb0, 
+    0x48b9d30e, 0x28016800, 0x2080db02, 0xe0026028, 0x30fff04f, 0x20006028, 0x800849b0, 0x800849b0, 
+    0x6800982c, 0x42886829, 0x48b0d17c, 0x1c408800, 0x49aeb200, 0x48ae8008, 0x28467800, 0x4608db16, 
+    0x0000f9b0, 0xdb112802, 0x880048a4, 0xd10d2801, 0x880048a3, 0xd1092801, 0x45589813, 0x2000d303, 
+    0x8008499f, 0x2000e002, 0x8008499c, 0x780048a0, 0xdc5a2846, 0xf9b0489d, 0x28010000, 0x2132db55, 
+    0xebb19812, 0xd2102f50, 0x88004894, 0x4899b968, 0x1000f9b0, 0x4281980d, 0x2001db07, 0x8008498f, 
+    0x981c4994, 0x98128008, 0x21329013, 0xebb19812, 0xd23a2f50, 0x8800488a, 0x488ebb90, 0x1000f9b0, 
+    0x4281980d, 0x2001db31, 0x80084985, 0x981c498a, 0xf8dd8008, 0xf240b048, 0xf04f11f4, 0xf7db7080, 
+    0xf245fd51, 0xf04f5111, 0xf7db7080, 0x487cfcfb, 0x1000f9b0, 0x7080f04f, 0xfcf4f7db, 0x215bea4f, 
+    0x7080f04f, 0xfceef7db, 0xf9b0487b, 0xf04f1000, 0xf7db7080, 0x4973fce7, 0x7080f04f, 0xfce2f7db, 
+    0xe7ffe003, 0x49712000, 0x98228008, 0x2000bbe8, 0x90099008, 0xf7e5a805, 0xa803fae4, 0xfa15f7e5, 
+    0x1c406828, 0x2000b390, 0x90029001, 0x6829e049, 0x44089801, 0x1020f858, 0x9801682a, 0xf8594410, 
+    0x42810020, 0x6829db2d, 0x44089801, 0x1020f858, 0x9801682a, 0xf8594410, 0x1a080020, 0x99079007, 
+    0x1181ebc1, 0xf7e50848, 0x9007fb99, 0x9802a905, 0x0010f931, 0x001ff1c0, 0xf8314958, 0x99070010, 
+    0x90074348, 0x9802a903, 0xe039e001, 0xf931e01c, 0x98071010, 0xf0f1fbb0, 0x98079007, 0x900709c0, 
+    0x2000e001, 0x98079007, 0xaa08b281, 0xf8229802, 0x98011010, 0xb2003081, 0x98029001, 0xb2001c40, 
+    0x98029002, 0xdbb22804, 0x0020f8bd, 0x4844b201, 0xfbdaf7db, 0x0022f8bd, 0x4841b201, 0xf7db1c80, 
+    0xf8bdfbd3, 0xb2010024, 0x1d00483d, 0xfbccf7db, 0x0026f8bd, 0x483ab201, 0xf7db1d80, 0xbf00fbc5, 
+    0x11f4f240, 0x7080f04f, 0xfcacf7db, 0x2122f240, 0x7080f04f, 0xfc56f7db, 0x6801982c, 0x7080f04f, 
+    0xfc50f7db, 0x7080f04f, 0xf7db6829, 0x9814fc4b, 0xf04f0a01, 0xf7db7080, 0x4820fc45, 0x1000f9b0, 
+    0x7080f04f, 0xfc3ef7db, 0xf9b04822, 0xf04f1000, 0xf7db7080, 0x9813fc37, 0xf04f0a01, 0xf7db7080, 
+    0x4817fc31, 0x1000f9b0, 0x7080f04f, 0xfc2af7db, 0xf9b04819, 0xf04f1000, 0xf7db7080, 0xea4ffc23, 
+    0xf04f211b, 0xf7db7080, 0x490efc1d, 0x7080f04f, 0xfc18f7db, 0x00c0f242, 0xfc88f7db, 0x981f2145, 
+    0xb0238001, 0x8ff0e8bd, 0x00038d98, 0x00038da4, 0x00038d9a, 0x00038b23, 0x000361ee, 0x00038d9c, 
+    0x00038da0, 0xdcba01f5, 0x00038b38, 0x00038b8a, 0x00036226, 0x00038d9e, 0x00038da2, 0x00038a5c, 
+    0xd0035154, 0x4ff0e92d, 0x4682b08d, 0x469b460f, 0x90082000, 0x83e4f8df, 0x90092019, 0xf99048f8, 
+    0xf9ba9000, 0xf04f1000, 0xf04f52a0, 0xf7db7080, 0xf1bbfbf0, 0xd1190f00, 0x780048f2, 0xd0152805, 
+    0x780048f0, 0xd0112803, 0x680048ef, 0xd2042816, 0xf44f2100, 0xf7e33000, 0x2000fba7, 0xfa23f7f9, 
+    0x461a2300, 0x48e92101, 0xf919f7e2, 0xf9b048e8, 0x48e81000, 0xf880f009, 0x900b2000, 0x780048e1, 
+    0xd1012803, 0xe0002001, 0x900a2004, 0x0f00f1bb, 0x48dcd109, 0x28057800, 0xf8cdd105, 0xf109902c, 
+    0xb2400001, 0x9d0b900a, 0x48dbe201, 0x28067800, 0x2400db14, 0x48d9e009, 0x2085eb00, 0x0024f850, 
+    0xf84149d7, 0x1c600024, 0x48d6b204, 0x0000f9b0, 0xdbf04284, 0xf85048d4, 0xe0106025, 0xe0072400, 
+    0xf85048d2, 0x49ce0024, 0x0024f841, 0xb2041c60, 0xf9b048cc, 0x42840000, 0x48ccdbf2, 0x1eb86806, 
+    0xf85149c7, 0xebb00020, 0xdd010fe6, 0xe00310f0, 0x49c31eb8, 0x0020f851, 0x4ac11eb9, 0x0021f842, 
+    0x46111e78, 0x0020f851, 0x0fa6ebb0, 0x10b0dd01, 0x1e78e003, 0xf85149ba, 0x1e790020, 0xf8424ab8, 
+    0x46100021, 0x6027f840, 0x1c784601, 0x0020f851, 0x0fa6ebb0, 0x10b0dd01, 0x49b1e003, 0xf8511c78, 
+    0x4aaf0020, 0xf8421c79, 0x46110021, 0xf8511cb8, 0xebb00020, 0xdd010fe6, 0xe00310f0, 0x1cb849a8, 
+    0x0020f851, 0x1cb94aa6, 0x0021f842, 0x6800489e, 0xd37e2812, 0x880048a6, 0xd13a2801, 0xf9b048a5, 
+    0x1e400000, 0xf8514611, 0xebb00020, 0xdd010fa6, 0xe00610b0, 0xf9b0489f, 0x1e400000, 0xf8514998, 
+    0x499c0020, 0x1000f9b1, 0x4a951e49, 0x0021f842, 0x461010b1, 0xf9b24a97, 0xf8402000, 0x46011022, 
+    0xf9b04894, 0x1c400000, 0x0020f851, 0x0fa6ebb0, 0x10b0dd01, 0x498ae006, 0xf9b0488e, 0x1c400000, 
+    0x0020f851, 0x498b4a86, 0x1000f9b1, 0xf8421c49, 0x48890021, 0x28018800, 0x4888d13b, 0x0000f9b0, 
+    0x497f1e40, 0x0020f851, 0x0fa6ebb0, 0x10b0dd01, 0x4882e006, 0x0000f9b0, 0x49791e40, 0x0020f851, 
+    0xf9b1497e, 0x1e491000, 0xf8424a75, 0x10b10021, 0x4a7a4610, 0x2000f9b2, 0x1022f840, 0x48774601, 
+    0x0000f9b0, 0xf8511c40, 0xebb00020, 0xdd020fa6, 0xe00710b0, 0x496ae00d, 0xf9b04870, 0x1c400000, 
+    0x0020f851, 0x496d4a66, 0x1000f9b1, 0xf8421c49, 0x2f1a0021, 0x2f24db01, 0x4866dd1b, 0x0000f9b0, 
+    0xdb08281a, 0xf9b04863, 0x28240000, 0x4860dc03, 0x28018800, 0x4861d00d, 0x0000f9b0, 0xdb0c281c, 
+    0xf9b0485e, 0x28240000, 0x485bdc07, 0x28018800, 0x2001d103, 0x7008495a, 0x2000e002, 0x70084958, 
+    0xb9101c78, 0x49562002, 0x484e7008, 0x4000f9b0, 0x4847e00a, 0x0000f9b0, 0x49491b00, 0x0020f851, 
+    0x0024f841, 0xb2041c60, 0xf9b04841, 0x42840000, 0x2008dbef, 0xe9cd494b, 0x4a4b1000, 0x4840493d, 
+    0xf0089b08, 0xe00cfbb5, 0xe0082400, 0xf8504846, 0x00400024, 0xf8414944, 0x1c600024, 0x2c11b204, 
+    0x4841dbf4, 0xf1b06800, 0xdded5f00, 0x2400e00c, 0x483de008, 0x0024f850, 0x493b1040, 0x0024f841, 
+    0xb2041c60, 0xdbf42c11, 0x68004837, 0x4f80f1b0, 0x2400dced, 0x4834e009, 0x0024f850, 0x5000f100, 
+    0xf8414931, 0x1c600024, 0x2c11b204, 0xeb05dbf3, 0x4a2e1005, 0x0180eb02, 0x482b2210, 0xf858f7f2, 
+    0xe0242400, 0x1005eb05, 0xeb014928, 0xf8500080, 0xf5000024, 0x12407080, 0xf828b200, 0xf9380014, 
+    0x28800014, 0x2080dd01, 0xf938e001, 0xf8280014, 0xf9380014, 0xf1100014, 0xda020f7f, 0x007ef06f, 
+    0xf938e001, 0xf8280014, 0x1c600014, 0x2c10b204, 0x2400ddd8, 0x900c2000, 0x0000e032, 0x00043078, 
+    0x000362b1, 0x00038b1c, 0x000361dc, 0xd00305ae, 0x00038d98, 0x00048308, 0x00036226, 0x00049638, 
+    0x00047b08, 0x00038d9a, 0x0004a638, 0x00038b94, 0x00038d9c, 0x00038d9e, 0x00038da0, 0x00038da2, 
+    0x00038b22, 0x0002fcd0, 0x00045308, 0x00048b08, 0x1014f838, 0x4408980c, 0x900cb200, 0xb2041c60, 
+    0xdbf52c11, 0x42879809, 0xf8b8db06, 0x980c1020, 0xb2001a08, 0x0020f8a8, 0xe0092400, 0xf8181c60, 
+    0xb2400010, 0xeb0149fd, 0x55081105, 0xb2041c60, 0xdbf32c10, 0x49fa2001, 0xf0017809, 0xeb010107, 
+    0x4af81101, 0x0181eb02, 0x1c686248, 0x980ab245, 0xf6ff4285, 0x48f4adfa, 0xb9988800, 0xe00f2500, 
+    0xe0092400, 0xeb0048ed, 0x5d001005, 0xeb0149ef, 0x55081105, 0xb2041c60, 0xdbf32c10, 0xb2451c68, 
+    0xdbed2d04, 0x0f00f1bb, 0x48e9d17e, 0x28057800, 0xf04fd1fa, 0xf8cd0c00, 0xf8cdc01c, 0x1f81c018, 
+    0xe0282400, 0xc374f8df, 0x1c09eb0c, 0xe004f91c, 0xc01cf8dd, 0xfa0f44f4, 0xf8cdfc8c, 0xf1c1c01c, 
+    0xfa0f0c00, 0xf8dff18c, 0xeb0cc354, 0xf91c1c09, 0xf8dde004, 0xfb1ec018, 0xfa0fcc01, 0xf8cdfc8c, 
+    0xf04fc018, 0xf10d0c00, 0xf80e0e08, 0xf104c004, 0xfa0f0c01, 0x2c10f48c, 0x2208dbd4, 0xc018f8dd, 
+    0x0c40f1cc, 0xf38cfa0f, 0x42932000, 0xeba3dd07, 0xfa0f0c02, 0xf04ff08c, 0xf8cd0c01, 0xf1c2c004, 
+    0x45630c00, 0xf1c2da09, 0xebac0c00, 0xfa0f0c03, 0xf04ff08c, 0xf8cd3cff, 0xe01ec004, 0xc004f8dd, 
+    0x0100f1cc, 0xe0122400, 0x0c00f1c1, 0xf18cfa0f, 0x0c08f10d, 0xc004f81c, 0xfa4f448c, 0xf10dfc8c, 
+    0xf80e0e08, 0xf104c004, 0xfa0f0c01, 0x2c10f48c, 0xf1a0dbea, 0xfa0f0c10, 0x2800f08c, 0x2810dd01, 
+    0x2800dcdc, 0xe000dd1e, 0x2810e056, 0xf8dddc1a, 0xf1ccc004, 0x24000100, 0xf1c1e012, 0xfa0f0c00, 
+    0xf10df18c, 0xf81c0c08, 0x448cc004, 0xfc8cfa4f, 0x0e08f10d, 0xc004f80e, 0x0c01f104, 0xf48cfa0f, 
+    0xdbea4284, 0xe0162400, 0xc250f8df, 0x1c09eb0c, 0xc004f81c, 0x0e08f10d, 0xe004f81e, 0xfa4f44f4, 
+    0xf8dffc8c, 0xeb0ee238, 0xf80e1e09, 0xf104c004, 0xfa0f0c01, 0x2c10f48c, 0x2500dbe6, 0x454de019, 
+    0x2400d013, 0xf8dfe00f, 0xeb0cc214, 0xf81c1c09, 0xf8dfc004, 0xeb0ee208, 0xf80e1e05, 0xf104c004, 
+    0xfa0f0c01, 0x2c10f48c, 0xf105dbed, 0xfa4f0c01, 0x2d04f58c, 0xbf00dbe3, 0x7800487d, 0xd1132803, 
+    0xe00f2501, 0xe0092400, 0xf8181c60, 0xb2400010, 0xeb014972, 0x55081105, 0xb2041c60, 0xdbf32c10, 
+    0xb2451c68, 0xdbed2d04, 0x00c0f242, 0xf8fef7db, 0x7800486f, 0xd1032802, 0xf8aa2046, 0xe0120000, 
+    0x7800486b, 0xd1032803, 0xf8aa2049, 0xe00a0000, 0x78004867, 0xd1032805, 0xf8aa204c, 0xe0020000, 
+    0xf8aa200f, 0xb00d0000, 0x8ff0e8bd, 0x4ff0e92d, 0x4682b087, 0x46994690, 0xf9ba2700, 0xf04f1000, 
+    0xf04f52a0, 0xf7db7080, 0xf242f874, 0xf7db00c0, 0xf8d8f8cd, 0xf8c90000, 0xf8d80000, 0x1c400000, 
+    0xf240b150, 0xf8d83220, 0x43500000, 0xb2011240, 0xf7da4850, 0xe004ffa9, 0x31fff04f, 0xf7da484d, 
+    0xf240ffa3, 0xf04f11f4, 0xf7db7080, 0xf243f88b, 0xf04f3133, 0xf7db7080, 0xf04ff835, 0xf8d97080, 
+    0xf7db1000, 0xf04ff82f, 0xf8d87080, 0xf7db1000, 0x4841f829, 0x1000f9b0, 0x7080f04f, 0xf822f7db, 
+    0x213f2200, 0xf7e1483d, 0x4606fd91, 0xf04f4631, 0xf7db7080, 0x483af817, 0xf04f7801, 0xf7db7080, 
+    0x4938f811, 0x7080f04f, 0xf80cf7db, 0x48374936, 0xf7e26800, 0x2400fff4, 0x2500e022, 0xf8d9e016, 
+    0x1c400000, 0x4832b940, 0x1004eb00, 0x49315d40, 0x1104eb01, 0xe0075548, 0xeb004820, 0x5d401004, 
+    0xeb01492c, 0x55481104, 0xb2451c68, 0xdbe62d10, 0xeb004828, 0x46201104, 0xfa7ff7e1, 0xb2441c60, 
+    0xdbda2c04, 0xf7f82001, 0xf242fd83, 0xf7db00c0, 0x4821f84d, 0x4000f990, 0x90002001, 0xeb00481c, 
+    0x481c1204, 0x1104eb00, 0x46202300, 0xfb3df7e1, 0xe0092500, 0xeb004809, 0x5d401004, 0xeb014917, 
+    0x55481104, 0xb2451c68, 0xdbf32d10, 0x78004814, 0xf7e8b908, 0x2400fbf9, 0x0000e045, 0x000442c8, 
+    0x00038b38, 0x00048c18, 0x00038b8a, 0x0004cc88, 0x00038b1c, 0xd003513c, 0x00038b88, 0xd0034200, 
+    0x00036226, 0xdcba01f5, 0x00167fc4, 0x00036310, 0x00044288, 0x00038e90, 0x000362b1, 0x0004cc48, 
+    0x000361ee, 0xf990488c, 0x42840000, 0x2001d019, 0x488a9000, 0x1204eb00, 0xeb004889, 0x23001104, 
+    0xf7e14620, 0x2500faf2, 0x4886e009, 0x1004eb00, 0x49855d40, 0x1104eb01, 0x1c685548, 0x2d10b245, 
+    0x1c60dbf3, 0x2c04b244, 0x4980dbdc, 0x0000f991, 0xf7e1497b, 0x4a7efa44, 0x48792104, 0xfbd0f007, 
+    0x7800487c, 0x2001b920, 0x7008497b, 0xff63f7f7, 0x497a2001, 0xf7f87008, 0x2203f986, 0x48782108, 
+    0xfcc4f7e1, 0x2203b140, 0x48752108, 0xf7e11c80, 0xb108fcbd, 0xfe6af7e2, 0x00c0f242, 0xffb6f7da, 
+    0x78004870, 0xd0032803, 0x7800486e, 0xd10e2805, 0xe9cd2001, 0x97040702, 0x9000200e, 0x46022301, 
+    0x97054601, 0x02189001, 0xfd6bf7e3, 0x2001e00d, 0x0702e9cd, 0x200e9704, 0x23019000, 0x46014602, 
+    0x90019705, 0xf7e32080, 0xf242fd5c, 0xf7da00c0, 0x485cff8d, 0x28037800, 0x2001d10d, 0x0702e9cd, 
+    0x200f9704, 0x23019000, 0x46014602, 0x90019705, 0xf7e30258, 0xf242fd46, 0xf7da00c0, 0x4852ff77, 
+    0xfbeef7e4, 0xf9904849, 0x494f0000, 0x0020f851, 0x3fc0f5b0, 0xf242d931, 0xf7da00c0, 0x2600ff67, 
+    0x484ae01c, 0x0016f830, 0xf8214949, 0x48490016, 0x1016f830, 0xf5064a46, 0xf8227080, 0x48461010, 
+    0x0016f830, 0xf8214945, 0x48450016, 0x1016f830, 0xf5064a42, 0xf8227080, 0x1c761010, 0xdbe02e81, 
+    0x00c0f242, 0xff42f7da, 0x6800483e, 0xf240b120, 0x1e4831a6, 0xfed0f7e2, 0x2301bf00, 0x4619220f, 
+    0xf7e34610, 0x4838fdb5, 0x0000f9b0, 0xdb222801, 0x78004835, 0x9006b240, 0xf9b04833, 0x28050000, 
+    0x2005db01, 0xf04f9006, 0xe0110b00, 0x04482101, 0xfe8af7e2, 0xf44f2100, 0xf7e23000, 0x2100fe85, 
+    0x3000f44f, 0xfe80f7e2, 0x0001f10b, 0xfb80fa4f, 0x45839806, 0xf242dbea, 0xf7da00c0, 0xf242ff07, 
+    0xf7da00c0, 0x2048ff03, 0x0000f8aa, 0xe8bdb007, 0xb5708ff0, 0x460d4604, 0x491c2001, 0xf7ed7008, 
+    0x2004fddf, 0x8008491a, 0x8020200a, 0x00c0f242, 0xfeecf7da, 0x0000bd70, 0x000362b1, 0x00044288, 
+    0x00038e90, 0x000442c8, 0x0004cc48, 0x00036240, 0x00038ed0, 0x000361ee, 0x000362af, 0x000362b0, 
+    0xd28e0078, 0x0003626a, 0x00038fe0, 0x0004b648, 0x00044308, 0x0004b848, 0x0004be48, 0x00044b08, 
+    0x0004c048, 0x00052f80, 0x00038b8a, 0x000361f7, 0x00038610, 0x41f0e92d, 0x460f4605, 0x461e4614, 
+    0x1000f9b5, 0x52a0f04f, 0x7080f04f, 0xfe51f7da, 0x00c0f242, 0xfeaaf7da, 0x60306820, 0x1c406820, 
+    0xf240b148, 0x68203220, 0x12404350, 0x4896b201, 0xfd8af7da, 0xf04fe004, 0x489331ff, 0xfd84f7da, 
+    0x11f4f240, 0x7080f04f, 0xfe6cf7da, 0x3133f243, 0x7080f04f, 0xfe16f7da, 0x7080f04f, 0xf7da6831, 
+    0xf04ffe11, 0x68217080, 0xfe0cf7da, 0xf04f4987, 0xf7da7080, 0x4986fe07, 0x68004886, 0xfdeff7e2, 
+    0x00c0f242, 0xfe72f7da, 0x80282048, 0x81f0e8bd, 0x47f0e92d, 0x4681b086, 0xf04f468a, 0xf24b0800, 
+    0xf2407798, 0xf04f11f4, 0xf7da7080, 0xf649fe3b, 0xf04f0177, 0xf7da7080, 0x4877fde5, 0x1000f9b0, 
+    0x7080f04f, 0xfddef7da, 0xf04f4970, 0xf7da7080, 0x4872fdd9, 0xb9287800, 0xfa64f7e8, 0x46082100, 
+    0xfd89f7e4, 0xf990486e, 0x20014000, 0x486d9000, 0x1204eb00, 0xeb00486c, 0x23001104, 0xf7e14620, 
+    0x2500f934, 0x4869e009, 0x1004eb00, 0x49685d40, 0x1104eb01, 0x1c685548, 0x2d10b205, 0x485fdbf3, 
+    0xb9087800, 0xf9f0f7e8, 0xe0202400, 0xf990485c, 0x42840000, 0x2001d019, 0x485a9000, 0x1204eb00, 
+    0xeb004859, 0x23001104, 0xf7e14620, 0x2500f90e, 0x4856e009, 0x1004eb00, 0x49555d40, 0x1104eb01, 
+    0x1c685548, 0x2d10b205, 0x1c60dbf3, 0x2c04b244, 0xf242dbdc, 0xf7da00c0, 0x2001fdf9, 0x0802e9cd, 
+    0x8010f8cd, 0x9000200e, 0x46022301, 0xf8cd4601, 0x90018014, 0xf7e30218, 0xf242fbb4, 0xf7da00c0, 
+    0x483efde5, 0xb9807800, 0x20012100, 0xfd73f7e4, 0x200c2100, 0xfccdf7e4, 0x46082101, 0xfd1bf7e4, 
+    0x493c2001, 0xf7f77008, 0x2203fd66, 0x483a2108, 0xfaccf7e1, 0x2203b140, 0x48372108, 0xf7e11c80, 
+    0xb108fac5, 0xfc72f7e2, 0x220f2301, 0x46104619, 0xfc3ef7e3, 0x04482101, 0xfd26f7e2, 0x00c0f242, 
+    0xfdb4f7da, 0x88004824, 0xd13a2801, 0x4821492b, 0xf7e26800, 0x2600fd24, 0x4829e01a, 0xfa20f7e4, 
+    0x68004827, 0xd80b42b8, 0x68404825, 0xd80742b8, 0x68804823, 0xd80342b8, 0x68c04821, 0xd90442b8, 
+    0x04082101, 0xfd00f7e2, 0xe003e000, 0xb2461c70, 0xdbe22e0a, 0xf240bf00, 0xf04f11f4, 0xf7da7080, 
+    0xf241fd11, 0xf04f1100, 0xf7da7080, 0x4631fd0b, 0x7080f04f, 0xfd06f7da, 0xf04f4904, 0xf7da7080, 
+    0xb006fd01, 0x87f0e8bd, 0xd003513c, 0xdcba01f5, 0x001312d0, 0x00036310, 0x00038b88, 0x000361ee, 
+    0x000362b1, 0x00044288, 0x00038e90, 0x000442c8, 0x0004cc48, 0x000362af, 0xd28e0078, 0x005a000a, 
+    0x00038fe0, 0x43fee92d, 0x46894607, 0x46984615, 0x1000f9b7, 0x52a0f04f, 0x7080f04f, 0xfce9f7da, 
+    0x00c0f242, 0xfd42f7da, 0xe0112600, 0xeb0149f7, 0x4af72046, 0x2146eb02, 0x23002202, 0x2100e9cd, 
+    0x461a9002, 0x20014631, 0xfddef7e0, 0xb2461c70, 0xdbeb2e04, 0x48f049ef, 0xf7e26800, 0x2000fca0, 
+    0x46024603, 0x0100f640, 0xf7e59000, 0x2000feaf, 0xfb09f7f8, 0x461a2300, 0x48e82101, 0xf9fff7e1, 
+    0x780048e7, 0xd1022801, 0xf7f82003, 0x2100fbf4, 0xf7e34608, 0x2000fe0e, 0xfba3f7f8, 0xf8c86828, 
+    0x68280000, 0xb1481c40, 0x3220f240, 0x43506828, 0xb2011240, 0xf7da48db, 0xe004fbe7, 0x31fff04f, 
+    0xf7da48d8, 0xf240fbe1, 0xf04f11f4, 0xf7da7080, 0xf243fcc9, 0xf04f3133, 0xf7da7080, 0xf04ffc73, 
+    0xf8d87080, 0xf7da1000, 0xf04ffc6d, 0x68297080, 0xfc68f7da, 0xf04f49cc, 0xf7da7080, 0x2100fc63, 
+    0x3000f44f, 0xfc40f7e2, 0xf44f2100, 0xf7e23000, 0x2003fc3b, 0xf9fcf7f8, 0x00c0f242, 0xfcc6f7da, 
+    0x780048c2, 0xf7e8b968, 0x2400f88f, 0x2100e006, 0x3080f44f, 0xfc28f7e2, 0xb2441c60, 0xdbf62c0f, 
+    0x2400e00a, 0x2100e006, 0x3080f44f, 0xfc1cf7e2, 0xb2441c60, 0xdbf62c0f, 0x80382047, 0x83fee8bd, 
+    0x47fce92d, 0x46894605, 0x27004692, 0x1000f9b5, 0x52a0f04f, 0x7080f04f, 0xfc3bf7da, 0x00c0f242, 
+    0xfc94f7da, 0x780048a9, 0x48a9b920, 0xb9087800, 0xf8a8f7e8, 0xf7f82003, 0xf04ff9bb, 0xe17d0800, 
+    0xe00c2400, 0x780949a1, 0x2101b909, 0x2100e000, 0xf7f54608, 0x4607f9ad, 0xe002b107, 0x2c641c64, 
+    0xbf00dbf0, 0x489bb99f, 0xb1286800, 0x21c2f240, 0xf7e21e48, 0xe00afc01, 0x78004895, 0xd1022805, 
+    0xf7e44895, 0x200ff8dd, 0xe8bd8028, 0x489387fc, 0x0000f990, 0x220db283, 0x0100f246, 0x38aa4889, 
+    0xf93df7e1, 0x22052300, 0x48862120, 0xf7e138aa, 0x2301f936, 0x21202205, 0x38aa4882, 0xf92ff7e1, 
+    0x24002700, 0x220fe009, 0x487e4985, 0xf7e13878, 0xb108f93d, 0xe0032701, 0xf5b41c64, 0xdbf24f00, 
+    0xb9afbf00, 0x1000f9b5, 0x52a0f04f, 0x7080f04f, 0xfbcff7da, 0x78004876, 0xd0082805, 0x68004875, 
+    0xd0fa2800, 0x21c4f240, 0xf7e21e48, 0xe113fbb5, 0xf6432200, 0x486b71ff, 0xf7e13878, 0xf000f917, 
+    0x28000001, 0xf242d071, 0xf7da00c0, 0xf240fc0f, 0xf04f11f4, 0xf7da7080, 0xf241fbe5, 0xf04f1111, 
+    0xf7da7080, 0x4867fb8f, 0x1000f990, 0x7080f04f, 0xfb88f7da, 0xf04f495c, 0xf7da7080, 0x2600fb83, 
+    0x485ae03e, 0x28017800, 0x485fd004, 0x0000f990, 0xd0334286, 0x4b5d2000, 0x46314602, 0x20019000, 
+    0xfd83f7e0, 0x78004857, 0xd10f2801, 0x49572000, 0x00fef8a1, 0xe0062400, 0x1c604954, 0x0010f831, 
+    0x0014f821, 0x2c7f1c64, 0xe00ddbf6, 0x494f2000, 0x247f8008, 0x1e60e006, 0xf831494c, 0xf8210010, 
+    0x1e640014, 0xdcf62c00, 0x49482000, 0x46024603, 0x1000e9cd, 0x20014631, 0xfc8cf7e0, 0xb2461c70, 
+    0xdbbe2e04, 0xe0342600, 0x4b402000, 0x46314602, 0xf7e09000, 0x483bfd4a, 0x28017800, 0x2000d110, 
+    0xf8a1493a, 0x240000fe, 0xe094e007, 0x1c604937, 0x0010f831, 0x0014f821, 0x2c7f1c64, 0xe00ddbf6, 
+    0x49322000, 0x247f8008, 0x1e60e006, 0xf831492f, 0xf8210010, 0x1e640014, 0xdcf62c00, 0x492b2000, 
+    0x46024603, 0x1000e9cd, 0xf7e04631, 0x1c70fc53, 0x2e04b246, 0x481ddbc8, 0xbb287800, 0xff92f7e7, 
+    0xf9904821, 0x20006000, 0x46024b20, 0x90004631, 0xf7e02001, 0x481bfd0a, 0x28017800, 0x2000d10f, 
+    0xf8a1491a, 0x240000fe, 0x4918e006, 0xf8311c60, 0xf8210010, 0x1c640014, 0xdbf62c7f, 0x2000e031, 
+    0x80084912, 0xe02a247f, 0x0000e035, 0x00044b08, 0x00044308, 0x00393870, 0x00036310, 0xd00305ae, 
+    0x00038456, 0xd003513c, 0xdcba01f5, 0x000361ee, 0x00038b1c, 0x00052f80, 0x00038fe0, 0x00036240, 
+    0xffff8000, 0x00038b24, 0x000362b1, 0x00043078, 0x49b11e60, 0x0010f831, 0x0014f821, 0x2c001e64, 
+    0x2000dcf6, 0x460349ac, 0xe9cd4602, 0x46311000, 0xf7e02001, 0x48a9fbef, 0x42407800, 0x49a7b240, 
+    0x48a77008, 0xb9087800, 0xfedef7e7, 0x00c0f242, 0xfb0cf7da, 0xe005e000, 0x0801f108, 0x0f04f1b8, 
+    0xae7ef6ff, 0xf7f5bf00, 0x2047f8b4, 0xfda2f7e3, 0xf7e4204e, 0x2301f9a5, 0x499a220f, 0xf7e0489a, 
+    0x489affde, 0x28057800, 0x2101d108, 0xf7e204c8, 0x2101fa5b, 0xf7e204c8, 0xe015fa57, 0x78004890, 
+    0xd1032801, 0x03402101, 0xfa4ef7e2, 0xf7f82004, 0x2101f80f, 0xf7e203c8, 0x4889fa47, 0xb9187800, 
+    0xfc1ff7e3, 0xfea0f7e7, 0x78004888, 0xd1022805, 0x80282048, 0x2049e001, 0xbf008028, 0xe92de665, 
+    0xb08943f0, 0x46894680, 0xf9b82700, 0xf04f1000, 0xf04f52a0, 0xf7da7080, 0xf242fa5c, 0xf7da00c0, 
+    0xf649fab5, 0x48764540, 0xb9087800, 0xfecaf7e7, 0xf7f72003, 0x4876ffdd, 0x4000f990, 0x90002004, 
+    0xeb004874, 0x48741204, 0x1104eb00, 0x46202300, 0xfd9bf7e0, 0x00c0f242, 0xfa98f7da, 0x78004868, 
+    0x496eb930, 0x6800486e, 0xfa09f7e2, 0xfe5cf7e7, 0xe0122400, 0xf9904866, 0x42840000, 0x2004d00b, 
+    0x48649000, 0x1204eb00, 0xeb004863, 0x23001104, 0xf7e04620, 0x1c60fd7a, 0x2c04b244, 0xf242dbea, 
+    0xf7da00c0, 0x4856fa73, 0x28017800, 0x2101d10f, 0xf7e204c0, 0x2101f9d9, 0xf7e20448, 0xf7e7f9d5, 
+    0x2101fdc8, 0xf7e20488, 0xf7e7f9cf, 0x2003fe7b, 0xff8ef7f7, 0xe0292600, 0xe9cd2001, 0x97040702, 
+    0x9000200e, 0x46022301, 0x97054601, 0x02189001, 0xf817f7e3, 0x00c0f242, 0xfa48f7da, 0xdd132e01, 
+    0xf7e34848, 0x4847febd, 0x42a86800, 0x4845d20c, 0x42a86840, 0x4843d208, 0x42a86880, 0x4841d204, 
+    0x42a868c0, 0xe003d200, 0xb2461c70, 0xdbd32e10, 0x4833bf00, 0xb9207800, 0x493b2001, 0xf7f77008, 
+    0x2203f9ba, 0x48392108, 0xff20f7e0, 0x2203b140, 0x48362108, 0xf7e01c80, 0xb108ff19, 0xf8c6f7e2, 
+    0xf8ad2047, 0x4832001c, 0x48286802, 0x1000f990, 0xf7ffa807, 0x2600fd65, 0x2001e025, 0x0702e9cd, 
+    0x200e9704, 0x23019000, 0x46014602, 0x90019705, 0xf7e20218, 0x2e00ffc6, 0x4822dd13, 0xfe70f7e3, 
+    0x68004820, 0xd20c42a8, 0x6840481e, 0xd20842a8, 0x6880481c, 0xd20442a8, 0x68c0481a, 0xd20042a8, 
+    0x1c70e003, 0x2e10b246, 0xbf00dbd7, 0xf7e34815, 0x2003fe57, 0xff0cf7f7, 0x220f2301, 0x46104619, 
+    0xf856f7e3, 0x68004813, 0xd8022811, 0xf7e32000, 0xb009f8a0, 0x83f0e8bd, 0x00043078, 0x00038b24, 
+    0x000361ee, 0xffff8000, 0xd0035092, 0x00038b1c, 0x000362b1, 0x0004cc48, 0x00038e90, 0x001312d0, 
+    0x00036310, 0x00038fe0, 0x000362af, 0xd28e0078, 0x00038b40, 0x000361dc, 0x2108b510, 0xf7da489e, 
+    0x2102f893, 0x1c80489c, 0xf88ef7da, 0x7189f246, 0x300e4899, 0xf888f7da, 0x5155f245, 0x30104896, 
+    0xf882f7da, 0x7189f246, 0x30124893, 0xf87cf7da, 0x5155f245, 0x30144890, 0xf876f7da, 0x7189f246, 
+    0x3016488d, 0xf870f7da, 0x5155f245, 0x3018488a, 0xf86af7da, 0x7189f246, 0x301a4887, 0xf864f7da, 
+    0x5155f245, 0x301c4884, 0xf85ef7da, 0x4882213c, 0xf7da3876, 0xf241f859, 0x487f0100, 0xf7da3874, 
+    0xf240f853, 0x487c2100, 0xf7da3878, 0xf240f84d, 0x48791100, 0xf7da387a, 0x2100f847, 0x38464876, 
+    0xf842f7da, 0x48742100, 0xf7da3844, 0x2110f83d, 0x38364871, 0xf838f7da, 0x2102f240, 0x385e486e, 
+    0xf832f7da, 0x486c2100, 0xf7da3814, 0xf240f82d, 0x48693120, 0xf7da3842, 0x21d2f827, 0x383c4866, 
+    0xf822f7da, 0x48642169, 0xf7da383a, 0x4963f81d, 0x38724861, 0xf818f7da, 0x485f4961, 0xf7da3868, 
+    0xf244f813, 0x485c1194, 0xf7da3866, 0xf247f80d, 0x48592100, 0xf7da386c, 0xf244f807, 0x48561194, 
+    0xf7da386a, 0xf240f801, 0x48536166, 0xf7d9382c, 0xf240fffb, 0x485031d7, 0xf7d9382a, 0xf240fff5, 
+    0x484d1130, 0xf7d93838, 0x2109ffef, 0x3834484a, 0xffeaf7d9, 0x48482108, 0xf7d93832, 0x2101ffe5, 
+    0x38304845, 0xffe0f7d9, 0x48432120, 0xf7d9381e, 0x2150ffdb, 0x38184840, 0xffd6f7d9, 0x483e2120, 
+    0xf7d93816, 0xf640ffd1, 0x483b617f, 0xf7d9380c, 0xf647ffcb, 0x48385100, 0xf7d9380a, 0xf647ffc5, 
+    0x48355100, 0xf7d93808, 0xf647ffbf, 0x48322100, 0xf7d91f80, 0x2108ffb9, 0x1f00482f, 0xffb4f7d9, 
+    0x482d21fa, 0xf7d91e80, 0x2108ffaf, 0x301e482a, 0xffaaf7d9, 0x48282108, 0xf7d93020, 0xf240ffa5, 
+    0x482511f4, 0xf7d93022, 0x210aff9f, 0x30244822, 0xff9af7d9, 0x48202100, 0xf7d91d80, 0x2180ff95, 
+    0x3008481d, 0xff90f7d9, 0x481b2101, 0xf7d9300a, 0xf641ff8b, 0x481871f8, 0xf7d93864, 0xf641ff85, 
+    0x4815715b, 0xf7d93862, 0xf647ff7f, 0x4812119c, 0xf7d93860, 0x4913ff79, 0x1d00480f, 0xff74f7d9, 
+    0xb510bd10, 0x49102000, 0x200a8008, 0xf8faf7e2, 0x48092100, 0xf7d9389a, 0x2000ff67, 0x7008490b, 
+    0x7008490b, 0x7008490b, 0x7008490b, 0x7008490b, 0x7008490b, 0x0000bd10, 0xd003149a, 0xffff803c, 
+    0xffff82dc, 0xffffcccc, 0x00038dc2, 0x00038db1, 0x00038db2, 0x00038db3, 0x00038db4, 0x00038db5, 
+    0x00038db6, 0x4ff8e92d, 0x460d4604, 0x461f4616, 0x890ae9dd, 0xf2402205, 0x481231e0, 0xfd46f7e0, 
+    0xfb80fa4f, 0x011ff00b, 0xf3614628, 0xea40105f, 0xea402086, 0xf44020c7, 0x480b4aa0, 0x00c4eb00, 
+    0x46519000, 0xf7d99800, 0x4807ff14, 0xeb001d00, 0x900000c4, 0x4108ea49, 0xf7d99800, 0xe8bdff0a, 
+    0x00008ff8, 0xd03c821e, 0xd1800200, 0x41f0e92d, 0x460f4605, 0x28d18ea8, 0xdc0dd07d, 0xd07b28b2, 
+    0xb1e0dc05, 0xd0292858, 0xd1762859, 0x28b3e032, 0x28d0d074, 0xe128d1f9, 0x1203f240, 0x42901a81, 
+    0xdc07d06d, 0xd06b28e6, 0xd06a28e7, 0x7f81f5b0, 0xe194d1eb, 0xd0762915, 0xd1e62916, 0xe252e1cb, 
+    0x32fff04f, 0x48fe49fd, 0xf0016800, 0x4604f9c7, 0xb9501d20, 0x86a82058, 0x81f0e8bd, 0x49f72200, 
+    0x680048f7, 0xf9baf001, 0x1d604604, 0x2059b918, 0xe7f186a8, 0x2c012401, 0xe234d000, 0x880048ef, 
+    0xd173286d, 0xf9b048ed, 0xf04f1000, 0x17d04220, 0xff6ff7d9, 0x884048e9, 0x49eab200, 0x48e78008, 
+    0xb2008880, 0x800849e8, 0x88c048e4, 0x49e7b200, 0x46088008, 0xb3608800, 0x88004608, 0x6080f400, 
+    0x48e3b950, 0xbb207800, 0x780048e2, 0x4608bb08, 0xf4008800, 0xb1e07080, 0x49da2000, 0x48da8008, 
+    0xf0007800, 0xb1680020, 0xf9b04608, 0xf0400000, 0x80080020, 0xe0c6e00d, 0xe1f5e064, 0xe13de06f, 
+    0xe0ede0e0, 0xf9b048cf, 0xf0400000, 0x49cd0010, 0x48d18008, 0x28017800, 0x2000d106, 0x700849cf, 
+    0x700849cf, 0xe148e027, 0x21402206, 0xf7e048cd, 0xb110fc7d, 0x0802f04f, 0xf04fe001, 0x220d0800, 
+    0x0100f242, 0xf7e048c7, 0xb108fc71, 0xe0002001, 0xea482000, 0x2e010600, 0x2001d101, 0x2000e000, 
+    0x700849be, 0xd1022e02, 0xe0012001, 0x2000e1b9, 0x700849bb, 0xbf00bf00, 0x880048b2, 0x5080f400, 
+    0x48b0b378, 0x0000f9b0, 0x5080f420, 0x800849ad, 0x780048b5, 0x48b5bb30, 0xb3187800, 0xf2414ab4, 
+    0x20050100, 0xfee5f7d9, 0x49a4203b, 0x22008008, 0x680048b0, 0xf8e0f001, 0x1d204604, 0x20b2b948, 
+    0xe74986a8, 0x499d2200, 0x680048aa, 0xf8d4f001, 0x1d604604, 0xd1032800, 0x86a820b3, 0x2401e73c, 
+    0xe006e179, 0xf2414aa2, 0x20050101, 0xfec1f7d9, 0x4894e171, 0xf0007800, 0x28000020, 0x4891d072, 
+    0x0000f9b0, 0x0020f020, 0x8008498e, 0x7800488e, 0x0020f000, 0x4a96b3b0, 0x0120f242, 0xf7d92005, 
+    0x2000fea8, 0x70084994, 0x78004894, 0xd0072801, 0x78004893, 0xd0032801, 0x78004886, 0xd1062801, 
+    0x78004883, 0x4884b918, 0x28007800, 0x2071d0c8, 0x8008497a, 0x488b2200, 0xf0016800, 0x4604f88d, 
+    0xb9481d20, 0x86a820d0, 0x2200e6f6, 0x48854973, 0xf0016800, 0x4604f881, 0x28001d60, 0x20d1d1b0, 
+    0xe6e986a8, 0x2401e001, 0x4a79e125, 0x20052120, 0xfe6ff7d9, 0x7800486e, 0xd0a12801, 0x7800486e, 
+    0xd09d2800, 0xfb7ef7e8, 0x49642007, 0x22008008, 0x68004874, 0xf860f001, 0x1d204604, 0x20e6b948, 
+    0xe6c986a8, 0x495d2200, 0x6800486e, 0xf854f001, 0x1d604604, 0xd18b2800, 0x86a820e7, 0xe001e6bc, 
+    0xe0f82401, 0x78004857, 0x0010f000, 0xd0742800, 0xf9b04854, 0xf0200000, 0x49520010, 0x48528008, 
+    0xf0007800, 0xb3c00010, 0xf2424a59, 0x20050110, 0xfe2ff7d9, 0x49582000, 0x48587008, 0x28017800, 
+    0x4857d007, 0x28017800, 0x484ad003, 0x28017800, 0x4847d106, 0xb9187800, 0x78004847, 0xd01e2800, 
+    0x493e2070, 0x22008008, 0x6800484e, 0xf814f001, 0x1d204604, 0xf240b950, 0x86a81002, 0x2200e67c, 
+    0x48484936, 0xf0016800, 0x4604f807, 0x28001d60, 0xf240d105, 0x86a81003, 0xe001e66e, 0xe0aa2401, 
+    0x21104a3b, 0xf7d92005, 0x4831fdf4, 0x28017800, 0x4831d022, 0xb1f87800, 0xfb04f7e8, 0x49272007, 
+    0x22008008, 0x68004837, 0xffe6f000, 0x1d204604, 0xf240b950, 0x86a81018, 0x2200e64e, 0x4831491f, 
+    0xf0006800, 0x4604ffd9, 0xb9281d60, 0x1019f240, 0xe64186a8, 0x2401e001, 0x481ae07d, 0xf4008800, 
+    0xb3484080, 0xf9b04817, 0xf4200000, 0x49154080, 0x48158008, 0xf4008800, 0xb1f04080, 0x21024a1c, 
+    0xf7d92005, 0x2000fdb6, 0x7008491b, 0x7800481c, 0x481abbf0, 0xbbd87800, 0x7800480e, 0x2202bbc0, 
+    0x48192104, 0xfb02f7e0, 0x4818b2c6, 0x46317802, 0xf7da2001, 0xe02cfd85, 0xe02de041, 0x0004ccc8, 
+    0x00038dc4, 0x00038dc8, 0x00038dca, 0x00038dcc, 0x00036266, 0x0003625e, 0x00036265, 0x000361e8, 
+    0x000361e9, 0xd28fffc0, 0x00036277, 0x000361ed, 0xcccc0000, 0x00038ae4, 0x000384d6, 0x0003626b, 
+    0x0003626d, 0x00038654, 0xd03c8c04, 0x0003626a, 0xf7f3e021, 0xe01efcb6, 0x21034a1c, 0xf7d92005, 
+    0x2202fd68, 0x481a2104, 0xfac0f7e0, 0x2200b2c6, 0x46104631, 0xfd44f7da, 0xfca9f7f3, 0x4815e00b, 
+    0xf0007800, 0xb1300004, 0xf9b04812, 0xf0200000, 0x49100004, 0x480f8008, 0x28008800, 0xae4cf47f, 
+    0xe000e000, 0xe5abbf00, 0xbf00bf00, 0xb510e5b4, 0x21012200, 0x500bf2af, 0xfcd1f000, 0x20042108, 
+    0xfe6ef000, 0x60084904, 0x0000bd10, 0xcccc0000, 0xd03c8c04, 0x00038dc8, 0x00038dc4, 0x4ff0e92d, 
+    0x4606b0a5, 0xf2408eb0, 0x1a812242, 0xd07d4290, 0xb158dc05, 0xd0192880, 0xd1782881, 0x2901e022, 
+    0x29bad076, 0x29bbd075, 0xe3f6d1f7, 0xf04fe3f9, 0x49f832ff, 0x680048f8, 0xff40f000, 0x1d284605, 
+    0x2080b958, 0xb02586b0, 0x8ff0e8bd, 0x49f12200, 0x680048f1, 0xff32f000, 0x1d684605, 0x2081b918, 
+    0xe7f086b0, 0x2d012501, 0xe3dad000, 0x880048e9, 0xd17d2865, 0x22022301, 0x48e82104, 0xfa2ff7e0, 
+    0x780048e7, 0xd1742802, 0x780048e6, 0xd1fa2801, 0x780048e5, 0x2801b130, 0x2802d00f, 0x2803d018, 
+    0xe08ad168, 0xf830f7e8, 0x49df2001, 0x20007008, 0x700849de, 0x700849de, 0xf7e8e15a, 0xb118f86c, 
+    0x49d92002, 0xe0027008, 0x49d72001, 0xe14f7008, 0xf86df7e8, 0xd06c2800, 0xf804f7e8, 0xf44f2100, 
+    0xf7e13080, 0x2400fc81, 0x2100e00b, 0xeb024ad1, 0x601102c4, 0x4ad06051, 0x02c4eb02, 0x60516011, 
+    0x2c041c64, 0xf04fdbf1, 0xe04b0b00, 0xe389e291, 0xe373e29c, 0xf7e8a822, 0xa81af809, 0xf815f7e8, 
+    0xe0362400, 0xf831a922, 0xf0070014, 0x4607ff47, 0x4bc22200, 0xfd3af007, 0x0106e9cd, 0xeb0048be, 
+    0xe9d000c4, 0x463a7300, 0xf0079806, 0x4abafc73, 0x02c4eb02, 0xa81ac203, 0x00c4eb00, 0x4bb72200, 
+    0x7100e9d0, 0xf0074638, 0xe9cdfd21, 0xe0020106, 0xe0fee355, 0x48afe0f8, 0x00c4eb00, 0x7300e9d0, 
+    0x9806463a, 0xfc56f007, 0xeb024aaa, 0xc20302c4, 0x2c041c64, 0x2100dbc6, 0x2000f240, 0xfc24f7e1, 
+    0x0b01f10b, 0x0f64f1bb, 0x2003dbb4, 0x7008499e, 0x2002e002, 0x7008499c, 0x2400e0da, 0x2100e00b, 
+    0xeb02aa0a, 0x601102c4, 0xaa126051, 0x02c4eb02, 0x60516011, 0x2c041c64, 0xf04fdbf1, 0xe0450b00, 
+    0xf7e7a822, 0xa81affa3, 0xffaff7e7, 0xe0342400, 0xf831a922, 0xf0070014, 0x4607fee1, 0x4b8f2200, 
+    0xfcd4f007, 0x0106e9cd, 0xeb00a812, 0xe9d101c4, 0x463a7300, 0x0106e9dd, 0xfc0cf007, 0xeb02aa12, 
+    0xc20302c4, 0xeb00a81a, 0x220000c4, 0xe9d04b83, 0x46387100, 0xfcbaf007, 0x0106e9cd, 0xeb00a80a, 
+    0xe9d101c4, 0x463a7300, 0x0106e9dd, 0xfbf2f007, 0xeb02aa0a, 0xc20302c4, 0x2c041c64, 0x2100dbc8, 
+    0x2000f240, 0xfbc0f7e1, 0x0b01f10b, 0x0f64f1bb, 0x2000dbb6, 0x24009009, 0xa812e061, 0x00c4eb00, 
+    0xe9cdc803, 0x486c0102, 0x00c4eb00, 0xe9cdc803, 0xe9dd0100, 0xf0082302, 0xe9cdf821, 0xf0070104, 
+    0x9008fe19, 0xdb012800, 0xe0019908, 0x42499908, 0xf0074608, 0xe9cdfe6c, 0x485f0106, 0x01c4eb00, 
+    0x4602c903, 0xe9cd460b, 0xe9dd0104, 0xf0070106, 0x4607fc6d, 0xc80c485a, 0xf0074638, 0xd20affbd, 
+    0x78004852, 0xd00428ff, 0x78004850, 0x494f1c40, 0x20017008, 0x484f9009, 0x00c4eb00, 0xe9cdc803, 
+    0xa80a0104, 0x01c4eb00, 0x7100e9d1, 0xe9dd4638, 0xf0072304, 0xe9cdffe3, 0x484a0106, 0x9806c80c, 
+    0xff9af007, 0x4842d20a, 0x28ff7800, 0x4840d004, 0x1c407800, 0x7008493e, 0x90092001, 0x2c041c64, 
+    0x9809db9b, 0xf7e7b160, 0x2100fedf, 0x3000f44f, 0xfb4af7e1, 0xfec6f7e7, 0x49332002, 0xe0027008, 
+    0x49312003, 0xe0037008, 0x492f2000, 0xbf007008, 0x4835bf00, 0x28017800, 0x4834d003, 0x28016800, 
+    0x4833d174, 0x1c408800, 0x80084931, 0x78004608, 0x000ff000, 0x2000bb88, 0xfe25f004, 0x482a4682, 
+    0x28017800, 0x482bd103, 0x45826800, 0x4827da07, 0x28016800, 0x4828d10a, 0x45826800, 0x2301dc06, 
+    0x2102461a, 0xf7e04825, 0xe058f88a, 0x6800481f, 0xd1052801, 0x68004820, 0x68094921, 0xe0004408, 
+    0x45504820, 0x4818da4b, 0x28017800, 0x4819d106, 0x491d6800, 0x1a406809, 0xe009e002, 0x70fff647, 
+    0xdd3c4550, 0x22012300, 0x48142102, 0xf867f7e0, 0xe02be035, 0x00038dd4, 0x00038dd0, 0xd03c8318, 
+    0x0003626a, 0x000384f8, 0x000384e5, 0x000384e6, 0x000384e7, 0x0004c800, 0x0004c7e0, 0x40590000, 
+    0x000384e8, 0x000384f0, 0x00038471, 0x0003847c, 0x00038de6, 0x00038474, 0x00038480, 0xd00351da, 
+    0x00038484, 0xffff8001, 0x00038478, 0x49f62000, 0x23008008, 0x21022201, 0xf7e048f4, 0x48f4f830, 
+    0xb1187800, 0x780048f2, 0xd1452802, 0x880048f1, 0x49f01c40, 0x46088008, 0xf0007800, 0xb9f8000f, 
+    0xff2ef004, 0x780048ec, 0xd1352801, 0xf7e12002, 0xb908fb20, 0xff1ef004, 0x780048e5, 0xf003b9a8, 
+    0x48e6feb9, 0xfa0af7d9, 0xd125280b, 0xfb7af004, 0x800849e3, 0x88004608, 0x2001b118, 0x700849de, 
+    0x2002e01a, 0x700849dc, 0x48d9e016, 0x28027800, 0x48dad112, 0xf9f2f7d9, 0xd10d280b, 0xf9eaf004, 
+    0x800849d7, 0x88004608, 0x2001b118, 0x700849d2, 0x2002e002, 0x700849d0, 0x780048d2, 0xd0072803, 
+    0x780048d0, 0xd0032805, 0x780048ce, 0xd17d2804, 0x880048cd, 0x49cc1c40, 0x48cc8008, 0xf9cef7d9, 
+    0xf980fa1f, 0x0080f009, 0xd11b2880, 0x780048c8, 0xd1072801, 0x780048c4, 0x001ff000, 0xf7f6b990, 
+    0xe00ffc92, 0xb9682000, 0xfc8df7f6, 0x780949c1, 0x49c1b921, 0xb1097809, 0xe0002101, 0x46082100, 
+    0xf9fff7e7, 0x0008f009, 0xd1122808, 0x780048bb, 0xd10a2801, 0x780048ba, 0x48b3b938, 0xf0007800, 
+    0xb930001f, 0xfa47f7f6, 0x2000e003, 0xf7f6b908, 0xf409fa42, 0xf5b04000, 0xd1164f00, 0x880048aa, 
+    0x0008f3c0, 0xf7e1b908, 0x48a7f890, 0xf3c08800, 0xb9500009, 0x780048ab, 0xf7e1b138, 0x2000f947, 
+    0x700849a8, 0x49a82001, 0xf4097008, 0xf5b06080, 0xd12c6f80, 0x7800489c, 0x000ff000, 0x489bbb38, 
+    0xf7d91f80, 0xf000f96b, 0xb3000001, 0xf8d3f7fb, 0x499e2043, 0x22008008, 0x6800489d, 0xfc1cf000, 
+    0x1d284605, 0xf240b960, 0xe0002042, 0x86b0e02a, 0x2200e509, 0x48964995, 0xf0006800, 0x4605fc0d, 
+    0xb9201d68, 0x2043f240, 0xe4fc86b0, 0xf4092501, 0xf5b05080, 0xd1185f80, 0x78004883, 0x007ff000, 
+    0x488cb998, 0x28037800, 0x488bd003, 0x28018800, 0xf7f2d101, 0x4889fa63, 0xb1307800, 0xf7f22000, 
+    0xe002fca3, 0x49782000, 0x48858008, 0x28017800, 0x4884d002, 0xb3a87800, 0x78004882, 0x4882bb20, 
+    0x1c407800, 0x70084980, 0x78004608, 0xdb782828, 0x384e4866, 0xf912f7d9, 0x0001f000, 0x200ab948, 
+    0xf862f7e0, 0x0020f000, 0x2001b918, 0x70084975, 0x2025e006, 0x80084975, 0x21007808, 0xfc83f7e7, 
+    0x49712000, 0xe05c7008, 0x7800486e, 0xd10a2801, 0xf7e62003, 0x2001fab5, 0xfb31f7e6, 0x49692002, 
+    0xe04e7008, 0xf7e6e048, 0x4969fb8e, 0x22067008, 0x71c0f640, 0xf7df4867, 0xb200fef9, 0x80084963, 
+    0x78004863, 0x4608b1d0, 0x28258800, 0x2023d102, 0xe0068008, 0x8800485d, 0xd1022823, 0x495b2022, 
+    0x485d8008, 0x1c408800, 0x8008495b, 0x88004608, 0x483eb201, 0xf7d9384c, 0xe00ef8c7, 0x88004853, 
+    0xd1032822, 0x49512023, 0xe0068008, 0x8800484f, 0xd1022823, 0x494d2025, 0x494c8008, 0x21007808, 
+    0xfc31f7e7, 0xf7e62002, 0x2000fa6b, 0xfae7f7e6, 0x49442000, 0xe0047008, 0x49422000, 0x49427008, 
+    0x48467008, 0x1c408800, 0x80084944, 0x88004608, 0xdd142810, 0x21042202, 0xf7df4841, 0xb958fea7, 
+    0x21012200, 0xf7df483f, 0xb928fea1, 0x22002301, 0x483d4619, 0xfe83f7df, 0x49382000, 0x20298008, 
+    0x8008492a, 0x48392200, 0xf0006800, 0x4605fb35, 0xb9501d28, 0x20fcf240, 0xe42486b0, 0x49232200, 
+    0x68004832, 0xfb28f000, 0x1d684605, 0xf240b940, 0x86b020fd, 0xe000e417, 0x2501e003, 0xe000e000, 
+    0xe404bf00, 0xbf00bf00, 0xb510e40d, 0x21012200, 0x0037f6af, 0xf8a3f000, 0x200a2108, 0xfa40f000, 
+    0x60084923, 0x0000bd10, 0x00038de6, 0xd00351da, 0x000361d8, 0x00038dde, 0x0003846c, 0xd03d44e0, 
+    0x0003846e, 0x000361ec, 0x00038ddc, 0xd03c80b6, 0x000362b0, 0x000361ee, 0x00036328, 0x000362af, 
+    0x00038b22, 0x000362cc, 0x000362cd, 0x00038dd4, 0x00038b18, 0x0003626a, 0x000361cc, 0x000384d7, 
+    0x000384d6, 0x00038de0, 0x00038de1, 0x00038de4, 0x00038de2, 0xd003900e, 0x00038de8, 0x00038dea, 
+    0xd03c8c04, 0xd203a1c2, 0xd203a032, 0x00038acc, 0x00038dd0, 0x2008b508, 0xf958f7e1, 0x46032000, 
+    0x46012201, 0x20089000, 0xf9c3f7e1, 0x20084908, 0xf963f7e1, 0xf7e14807, 0x2008f9ea, 0xf967f7e1, 
+    0xf2462201, 0x200311a8, 0xf90ef7e1, 0x0000bd08, 0x000284c0, 0xc1000184, 0xf000e001, 0xe7fcf91b, 
+    0x4604b570, 0x8ea0460d, 0xf7d9b910, 0xbf00f847, 0xbd70bf00, 0x2200b510, 0xf2af4611, 0xf000001b, 
+    0xbd10f81e, 0x2400b510, 0xeb04e007, 0x4aac0184, 0x0081eb02, 0xf96af000, 0x2c021c64, 0x48a9d3f5, 
+    0xf964f000, 0xf00048a8, 0x48a8f961, 0xf95ef000, 0x49a748a4, 0x48a46008, 0x600849a6, 0xe92dbd10, 
+    0x460741f0, 0x4690460d, 0xf0002038, 0x4604fe1d, 0xd02e2c00, 0x680048a0, 0x489fb918, 0xf7ff6004, 
+    0x2d02ffd1, 0x2501d300, 0x86a02000, 0xf8c462e5, 0x60278030, 0xf0001d20, 0xf104f946, 0xf0000018, 
+    0x6124f942, 0xf1c56264, 0x61a0000a, 0x6ae04993, 0x42886809, 0x4991d902, 0x60086ae0, 0xeb016ae1, 
+    0x4a870181, 0x0081eb02, 0xf0001d21, 0x2601f92f, 0xf04fe001, 0x463036ff, 0x81f0e8bd, 0x4605b570, 
+    0x4887460c, 0x19466800, 0x68004883, 0xf0001d00, 0x4881f945, 0x60466800, 0x68004881, 0xd2074286, 
+    0x6801487d, 0x487b1d09, 0xf0006800, 0xe006f91d, 0x68014879, 0x48761d09, 0xf0006800, 0xb12cf915, 
+    0x68014875, 0x46203118, 0xf90ef000, 0xb510bd70, 0xb672e023, 0x6800486d, 0x486cb118, 0x68c068c0, 
+    0x2000e000, 0xf1044604, 0xf0000018, 0xb662f917, 0xf0001d20, 0x4969f913, 0x68096ae0, 0xd9024288, 
+    0x6ae04966, 0x6ae16008, 0x0181eb01, 0xeb024a5c, 0x1d210081, 0xf8daf000, 0x485cbf00, 0x28006800, 
+    0xbd10d1d7, 0xf000b510, 0x495efc7f, 0x1a406809, 0x6008495d, 0x485ae045, 0x1c406800, 0x60084958, 
+    0x68004859, 0x49581e40, 0x48556008, 0xb9406800, 0x6808494f, 0x6809494f, 0x60114a4d, 0x6008494d, 
+    0xe021bf00, 0x6860494e, 0x42886809, 0xe027d900, 0x1d20b672, 0xf8d2f000, 0xb1186aa0, 0x0018f104, 
+    0xf8ccf000, 0x4945b662, 0x68096ae0, 0xd9024288, 0x6ae04942, 0x6ae16008, 0x0181eb01, 0xeb024a38, 
+    0x1d210081, 0xf892f000, 0x68004839, 0xb1206800, 0x68004837, 0x68c068c0, 0x2000e000, 0xd1d10004, 
+    0x4839bf00, 0x28006800, 0x4835d1b5, 0x49356800, 0xbd106008, 0xf7ffb510, 0xf7ffff7a, 0xe008ffa3, 
+    0x6800482e, 0xbd10b900, 0x6800482c, 0x492b1e40, 0x482a6008, 0xeb006800, 0x49210080, 0x0020f851, 
+    0xd0ed2800, 0x68094925, 0x0181eb01, 0xeb024a1c, 0x68410081, 0x60416849, 0x0108f100, 0x428a6842, 
+    0x6841d102, 0x60416849, 0x68c96841, 0x60114a1a, 0x68004610, 0x46106b01, 0x68026800, 0x68004816, 
+    0xbf004790, 0xb570e7cf, 0x68204604, 0x68e0b110, 0xe00068c0, 0x46052000, 0x0018f105, 0xf85ef000, 
+    0x0118f105, 0xf0004809, 0x490bf831, 0x68096ae8, 0x42886ac9, 0x2601d301, 0x2600e000, 0xbd704630, 
+    0x0004ccd8, 0x0004cd00, 0x0004cd14, 0x0004cd28, 0x00038dec, 0x00038df0, 0x00038df4, 0x00038df8, 
+    0x00038dfc, 0x00038e00, 0x00038e04, 0x0108f100, 0xf04f6041, 0x608131ff, 0x0108f100, 0x610160c1, 
+    0x60012100, 0x21004770, 0x47706101, 0x68536842, 0x6843604b, 0x6853608b, 0x60516099, 0x61086041, 
+    0x1c5b6803, 0x47706003, 0x4602b510, 0x1c5c680b, 0x6910b90c, 0xf102e007, 0xe0000008, 0x68446840, 
+    0x429c6824, 0x6844d9fa, 0x684c604c, 0x608860a1, 0x610a6041, 0x1c646814, 0xbd106014, 0x3201e9d0, 
+    0xe9d0609a, 0x605a2301, 0x684a6901, 0xd1014282, 0x604a6882, 0x61022200, 0x1e52680a, 0x4770600a, 
+    0x41f0e92d, 0x460e4605, 0x204cb375, 0xfc7cf000, 0xb34c4604, 0xf006fb05, 0x46381c47, 0xfc74f000, 
+    0x68206020, 0x6820b1e8, 0x0006fb05, 0x20006060, 0x682063a0, 0x1e6860a0, 0xfb006821, 0x60e01006, 
+    0x642663e5, 0x30fff04f, 0x64a06460, 0x0010f104, 0xff8cf7ff, 0x0024f104, 0xff88f7ff, 0xe8bd4620, 
+    0x462081f0, 0xfc5cf000, 0xe7f82000, 0x4604b510, 0xfcb0f000, 0x6a60e00d, 0xf104b150, 0xf0000024, 
+    0xb108fbfd, 0xfc3af000, 0x1e406ca0, 0xe00064a0, 0x6ca0e002, 0xdcee2800, 0xf04fbf00, 0x64a030ff, 
+    0xfc9ff000, 0xfc96f000, 0x6920e00d, 0xf104b150, 0xf0000010, 0xb108fbe3, 0xfc20f000, 0x1e406c60, 
+    0xe0006460, 0x6c60e002, 0xdcee2800, 0xf04fbf00, 0x646030ff, 0xfc85f000, 0xb570bd10, 0xf0004604, 
+    0x6ba0fc79, 0x42886be1, 0x2001d101, 0x2000e000, 0xf0004605, 0x4628fc76, 0xb570bd70, 0x460e4604, 
+    0x6c204615, 0xb97db308, 0x6c224631, 0xf00468a0, 0x6c21ed32, 0x440868a0, 0xe9d460a0, 0x42881001, 
+    0x6820d313, 0xe01060a0, 0x6c224631, 0xf00468e0, 0x6c21ed22, 0x1a4068e0, 0x682160e0, 0x428868e0, 
+    0x6c21d203, 0x1a406860, 0x6ba060e0, 0x63a01c40, 0xb570bd70, 0xf0004604, 0x6ba0fc3d, 0x2001b908, 
+    0x2000e000, 0xf0004605, 0x4628fc3c, 0xb570bd70, 0x460d4604, 0xb1706820, 0x68e06c21, 0x60e04408, 
+    0x68e06861, 0xd3014288, 0x60e06820, 0x6c224628, 0xf00468e1, 0xbd70ecf0, 0x41f0e92d, 0x460f4604, 
+    0xb6724615, 0xf7ff4620, 0xb168ff98, 0xf104b14d, 0x46280110, 0xfdc2f7ff, 0xf06fb662, 0xe8bd0003, 
+    0xb66281f0, 0xe7fa2000, 0xbf00b662, 0x6ba0b672, 0x42886be1, 0x2200d20e, 0x46204639, 0xff8df7ff, 
+    0x6a602601, 0xf104b138, 0xf7ff0024, 0xb110fe8c, 0xe0001fb6, 0xb6622600, 0xe7e04630, 0x41f0e92d, 
+    0x460f4604, 0xb6724615, 0xb9686ba0, 0xf104b14d, 0x46280124, 0xfd92f7ff, 0xf06fb662, 0xe8bd0003, 
+    0xb66281f0, 0xe7fa2000, 0xbf00b662, 0x6ba0b672, 0x6c21b1d8, 0x440868e0, 0x686160e0, 0x428868e0, 
+    0x6820d301, 0x6ba060e0, 0x63a01e40, 0x6c224638, 0xf00468e1, 0x2601ec90, 0xb1386920, 0x0010f104, 
+    0xfe51f7ff, 0x1fb6b110, 0x2600e000, 0x4630b662, 0xb570e7d5, 0x460e4604, 0x6ba04615, 0x42886be1, 
+    0x2200d20e, 0x46204631, 0xff37f7ff, 0x6a60b945, 0xf104b130, 0xf7ff0024, 0xb108fe36, 0xbd702001, 
+    0xe7fc4628, 0x680048f9, 0x48f8b118, 0x6b006800, 0x20004770, 0xb510e7fc, 0xe0072400, 0x0184eb04, 
+    0xeb024af3, 0xf7ff0081, 0x1c64fe51, 0xd3f52c0a, 0xf7ff48f0, 0x48f0fe4b, 0xfe48f7ff, 0xf7ff48ef, 
+    0x48effe45, 0xfe42f7ff, 0xf7ff48ee, 0x48e9fe3f, 0x600849ed, 0x49ed48e8, 0xbd106008, 0x41f0e92d, 
+    0x460e4604, 0x46984615, 0x22209f06, 0xf1044631, 0xf0040034, 0x2100ecae, 0x55012053, 0xd3002d0a, 
+    0x62e52509, 0xf7ff1d20, 0xf104fe2e, 0xf7ff0018, 0x6124fe2a, 0x000af1c5, 0x626461a0, 0x81f0e8bd, 
+    0x4605b570, 0x2058460e, 0xfadef000, 0xb17c4604, 0xf00000a8, 0x6320fad9, 0xb9206b20, 0xf0004620, 
+    0x2400fadf, 0x00a9e004, 0x6b2022a5, 0xfc78f004, 0xbd704620, 0x4fffe92d, 0x4680b083, 0x46994616, 
+    0x5a10e9dd, 0x99124630, 0xffdaf7ff, 0x2c004604, 0x2000d05c, 0xf04fb110, 0xe0010b01, 0x0b00f04f, 
+    0x1e70bf00, 0xeb016b21, 0x90020080, 0xf0209802, 0x90020007, 0x462a9600, 0x9b134620, 0xf7ff9904, 
+    0x464aff9d, 0x98024641, 0xfab6f000, 0xf0006020, 0x48b7fb01, 0x1c406800, 0x600849b5, 0x68004608, 
+    0xd1042801, 0x600448a9, 0xff65f7ff, 0x48b1e009, 0xb9306800, 0x680048a5, 0x42a86ac0, 0x48a3d801, 
+    0x49ad6004, 0x68096ae0, 0xd9024288, 0x6ae049aa, 0x48aa6008, 0x65606800, 0x680048a8, 0x49a71c40, 
+    0x49a76008, 0x68096ae0, 0xd9024288, 0x6ae049a4, 0x6ae16008, 0x0181eb01, 0xeb024a95, 0x1d210081, 
+    0xfda4f7ff, 0xf0002701, 0xe001facc, 0x37fff04f, 0xd10d2f01, 0x0f00f1ba, 0xf8cad001, 0x48954000, 
+    0xb1286800, 0x68004889, 0x42a86ac0, 0xdf00d200, 0xb0074638, 0x8ff0e8bd, 0x4892b510, 0x28006800, 
+    0x4891d144, 0x1c406800, 0x6008498f, 0x68004608, 0x4985b968, 0x49856808, 0x4a836809, 0x49836011, 
+    0x498a6008, 0x1c496809, 0x60114a88, 0xe01fbf00, 0x68604985, 0x42886809, 0xe025d900, 0xf7ff1d20, 
+    0x6aa0fd8d, 0xf104b118, 0xf7ff0018, 0x497cfd87, 0x68096ae0, 0xd9024288, 0x6ae04979, 0x6ae16008, 
+    0x0181eb01, 0xeb024a6a, 0x1d210081, 0xfd4ef7ff, 0x6800486d, 0xb1206800, 0x6800486b, 0x68c068c0, 
+    0x2000e000, 0xd1d30004, 0xe004bf00, 0x68004870, 0x496f1c40, 0xbd106008, 0x2500b570, 0xfa5af000, 
+    0x68004868, 0x49671e40, 0x46086008, 0x28006800, 0x485fd149, 0x28006800, 0x2600d045, 0xf104e01e, 
+    0xf7ff0018, 0x1d20fd4b, 0xfd48f7ff, 0x6ae0495c, 0x42886809, 0x495ad902, 0x60086ae0, 0xeb016ae1, 
+    0x4a4b0181, 0x0081eb02, 0xf7ff1d21, 0x4947fd0f, 0x68096ae0, 0x42886ac9, 0x2601d300, 0x68004847, 
+    0x4846b118, 0x68c068c0, 0x2000e000, 0xd1d60004, 0x6800484f, 0xe006b158, 0xff6ef7ff, 0x6800484c, 
+    0x494b1e40, 0x484a6008, 0x28006800, 0x2e01d1f4, 0x4848d003, 0x28016800, 0x2501d104, 0x49452000, 
+    0xdf006008, 0xf000bf00, 0x4628fa0c, 0x483dbd70, 0x1c406800, 0x6008493b, 0xb5104770, 0x6b204604, 
+    0xf99ef000, 0xf0004620, 0xbd10f99b, 0x483ab570, 0xb3486800, 0xffebf7ff, 0x68004829, 0x2001b908, 
+    0x2000e000, 0xf7ff4605, 0xb9edff87, 0xf9e2f000, 0x68004823, 0x4822b118, 0x68c068c0, 0x2000e000, 
+    0x1d204604, 0xfcdaf7ff, 0x68004821, 0x49201e40, 0x48296008, 0x1e406800, 0x60084927, 0xf9d1f000, 
+    0xf7ff4620, 0xbf00ffca, 0xbf00bd70, 0xffcef7ff, 0xf7ffdf00, 0xe7f9fb01, 0x2000b51f, 0x90019000, 
+    0x46039002, 0x2200f240, 0x9003a11c, 0xf7ff481d, 0x4604fe81, 0xd1082c01, 0x2001b672, 0x6008490d, 
+    0x49112000, 0xf0006008, 0xbd1ff99e, 0x00038e08, 0x0004cd3c, 0x0004ce04, 0x0004ce18, 0x0004ce2c, 
+    0x0004ce40, 0x0004ce54, 0x00038e0c, 0x00038e10, 0x00038e18, 0x00038e28, 0x00038e20, 0x00038e3c, 
+    0x00038e24, 0x00038e2c, 0x00038e1c, 0x00038e38, 0x00038e30, 0x00038e34, 0x00038e14, 0x454c4449, 
+    0x00000000, 0x0002810b, 0xf000b510, 0x4853f973, 0xf0006804, 0x4620f976, 0x4601bd10, 0xe0022000, 
+    0x1c421c49, 0x780ab290, 0xd0f92aa5, 0x47700880, 0x43fee92d, 0x460c4681, 0x46204616, 0x68496841, 
+    0xf1006041, 0x68420108, 0xd102428a, 0x68496841, 0x68416041, 0xbf0068cf, 0x68414620, 0x60416849, 
+    0x0108f100, 0x428a6842, 0x6841d102, 0x60416849, 0x68cd6841, 0xf7ff6b28, 0x4680ffd0, 0x6ae96d68, 
+    0xf1054633, 0xe9cd0234, 0x90021800, 0x4839a134, 0xf926f004, 0x46484937, 0xe9eaf004, 0xd1db42bd, 
+    0x83fee8bd, 0x68004834, 0x2001b118, 0x60084933, 0xe0044770, 0x68004832, 0x49311e40, 0x48306008, 
+    0xeb006800, 0x492f0080, 0x0020f851, 0xd0f12800, 0x6809492b, 0x0181eb01, 0xeb024a2a, 0x68410081, 
+    0x60416849, 0x0108f100, 0x428a6842, 0x6841d102, 0x60416849, 0x68c96841, 0x60114a23, 0x68004823, 
+    0x4610b328, 0x6d406800, 0x68094921, 0xd0224288, 0x68004820, 0x49203008, 0x42886809, 0x4610d218, 
+    0x6d406800, 0x6008491a, 0x6800480c, 0x68094919, 0x48186008, 0x1d006800, 0x60084916, 0x68004814, 
+    0x60086809, 0x68004813, 0x49121d00, 0xe0026008, 0x490e2000, 0xbf006008, 0x0000e7aa, 0x00038e1c, 
+    0x09097325, 0x25096325, 0x75250975, 0x0d752509, 0x0000000a, 0x0004ce68, 0x00038e2c, 0x00038e34, 
+    0x00038e24, 0x0004cd3c, 0x00038e08, 0x00038e4c, 0x00038e50, 0x00038e40, 0x00038e48, 0x4605b570, 
+    0xb1106828, 0x68c068e8, 0x2000e000, 0xf1044604, 0xf7ff0018, 0x4814fba3, 0xb9a06800, 0xf7ff1d20, 
+    0x4912fb9d, 0x68096ae0, 0xd9024288, 0x6ae0490f, 0x6ae16008, 0x0181eb01, 0xeb024a0d, 0x1d210081, 
+    0xfb64f7ff, 0xf104e004, 0x480a0118, 0xfb5ef7ff, 0x6ae04909, 0x6ac96809, 0xd3014288, 0xe0002601, 
+    0x46302600, 0x0000bd70, 0x00038e2c, 0x00038e24, 0x0004cd3c, 0x0004ce2c, 0x00038e08, 0x49012001, 
+    0x47706008, 0x00038e34, 0x4604b570, 0xfe5ff7ff, 0xf0034620, 0x4605ffbb, 0xfdfef7ff, 0xbd704628, 
+    0x4604b510, 0xf7ffb134, 0x4620fe52, 0xffddf003, 0xfdf2f7ff, 0x0000bd10, 0x460bb510, 0x1d1c4601, 
+    0x1f006004, 0x34aaf04f, 0x1f006004, 0x1f006001, 0x3412f04f, 0x1f006004, 0x3411f04f, 0x1f006004, 
+    0x3410f04f, 0x1f006004, 0x3409f04f, 0x1f006004, 0x3408f04f, 0x1f006004, 0x3407f04f, 0x1f006004, 
+    0x3406f04f, 0x1f006004, 0x3405f04f, 0x1f006004, 0x3404f04f, 0x1f006004, 0x3403f04f, 0x1f006004, 
+    0x3402f04f, 0x1f006004, 0x60041064, 0x60021f00, 0x243f1f00, 0x1f006004, 0x60042400, 0xb510bd10, 
+    0xf928f7ff, 0xb510bd10, 0xfff9f7ff, 0xef58f004, 0xbd102000, 0x4809b672, 0x1c406800, 0x60084907, 
+    0x48064770, 0xb1406800, 0x68004804, 0x49031e40, 0x46086008, 0xb9006800, 0x4770b662, 0x00038e54, 
+    0xe92d500f, 0xe59f0078, 0xfaff6083, 0xfafffe99, 0xe59f0070, 0xe1d000b0, 0xe2800001, 0xe59f1064, 
+    0xe1c100b0, 0xe2810000, 0xe1d000b0, 0xe3500b01, 0xba00000e, 0xe3a00065, 0xe59f104c, 0xe1c100b0, 
+    0xe3a02000, 0xe59f0044, 0xe5900000, 0xfbfffe07, 0xe59f103c, 0xe5911000, 0xe0800001, 0xe59f1030, 
+    0xe5810000, 0xe3a00000, 0xe59f1018, 0xe1c100b0, 0xe59f0020, 0xfbff8164, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xd03c824a, 0x00038e60, 0x00038e58, 0x00038dd0, 0x000361e4, 0xc1000184, 0x2300b510, 
+    0x2101461a, 0xf7de48f9, 0x2300feba, 0xf244220e, 0x48f60100, 0xf7de3010, 0xbd10feb2, 0x49f4b510, 
+    0x301e48f2, 0xf8b0f7d8, 0x3100f240, 0x302048ef, 0xf8aaf7d8, 0x48ed21ef, 0xf7d83022, 0xf241f8a5, 
+    0x48ea3104, 0xf7d83026, 0xf240f89f, 0x48e71180, 0xf7d83028, 0xf244f899, 0x48e40100, 0xf7d8302c, 
+    0xf243f893, 0x48e10100, 0xf7d8302e, 0xf240f88d, 0x48de1119, 0xf7d83030, 0xf240f887, 0x48db2102, 
+    0xf7d83032, 0x210ff881, 0x303448d8, 0xf87cf7d8, 0x0100f245, 0x303648d5, 0xf876f7d8, 0x318ef247, 
+    0x303848d2, 0xf870f7d8, 0x0100f241, 0x303a48cf, 0xf86af7d8, 0x0100f241, 0x303c48cc, 0xf864f7d8, 
+    0x48ca49cc, 0xf7d8303e, 0xf244f85f, 0x48c701ff, 0xf7d8304e, 0xf241f859, 0x48c40100, 0xf7d8302a, 
+    0x2100f853, 0x302a48c1, 0xf84ef7d8, 0x48bf2100, 0xf7d83030, 0x2100f849, 0x303248bc, 0xf844f7d8, 
+    0x48ba2100, 0xf7d83034, 0x2100f83f, 0x303648b7, 0xf83af7d8, 0x48b52100, 0xf7d83038, 0x2100f835, 
+    0x303a48b2, 0xf830f7d8, 0x48b02100, 0xf7d8303c, 0x2100f82b, 0x303e48ad, 0xf826f7d8, 0x48ab2100, 
+    0xf7d8304e, 0xf640f821, 0x48a83100, 0xf7d83030, 0xf243f81b, 0x48a5113d, 0xf7d83032, 0x217cf815, 
+    0x303448a2, 0xf810f7d8, 0x48a049a3, 0xf7d8304e, 0xf241f80b, 0x489d0100, 0xf7d8302a, 0x2100f805, 
+    0x302a489a, 0xf800f7d8, 0x48982100, 0xf7d73030, 0x2100fffb, 0x30324895, 0xfff6f7d7, 0x48932100, 
+    0xf7d73034, 0x2100fff1, 0x304e4890, 0xffecf7d7, 0x488e2101, 0xf7d73030, 0xf240ffe7, 0x488b5140, 
+    0xf7d73032, 0xf640ffe1, 0x48886140, 0xf7d73034, 0xf640ffdb, 0x48850141, 0xf7d73036, 0xf241ffd5, 
+    0x48823144, 0xf7d73038, 0x4984ffcf, 0x3040487f, 0xffcaf7d7, 0x3133f644, 0x3042487c, 0xffc4f7d7, 
+    0x4100f240, 0x30444879, 0xffbef7d7, 0x487721d0, 0xf7d7302a, 0xbd10ffb9, 0x41f0e92d, 0x460c4605, 
+    0x2c004616, 0xf1c4da02, 0xb2040040, 0x2e01462f, 0x463dd101, 0x2500e000, 0x2200b2ab, 0x4870213f, 
+    0xfd9df7de, 0x2200b2ab, 0x486d213f, 0xf7de3010, 0xb2abfd96, 0x213f2200, 0x30084869, 0xfd8ff7de, 
+    0xd1012e02, 0xe000463d, 0xb2ab2500, 0x213f2200, 0x1c804863, 0xfd83f7de, 0x2200b2ab, 0x4860213f, 
+    0xf7de3012, 0xb2abfd7c, 0x213f2200, 0x300a485c, 0xfd75f7de, 0xd1012e03, 0xe000463d, 0xb2ab2500, 
+    0x213f2200, 0x1d004856, 0xfd69f7de, 0x2200b2ab, 0x4853213f, 0xf7de3014, 0xb2abfd62, 0x213f2200, 
+    0x300c484f, 0xfd5bf7de, 0xd1012e04, 0xe000463d, 0xb2ab2500, 0x213f2200, 0x1d804849, 0xfd4ff7de, 
+    0x2200b2ab, 0x4846213f, 0xf7de3016, 0xb2abfd48, 0x213f2200, 0x300e4842, 0xfd41f7de, 0x2208b2a3, 
+    0x7100f643, 0xf7de483e, 0xb2a3fd3a, 0xf6432208, 0x483b7100, 0xf7de1c80, 0xb2a3fd32, 0xf6432208, 
+    0x48377100, 0xf7de1d00, 0xb2a3fd2a, 0xf6432208, 0x48337100, 0xf7de1d80, 0xb2a3fd22, 0xf6432208, 
+    0x482f7100, 0xf7de3010, 0xb2a3fd1a, 0xf6432208, 0x482b7100, 0xf7de3012, 0xb2a3fd12, 0xf6432208, 
+    0x48277100, 0xf7de3014, 0xb2a3fd0a, 0xf6432208, 0x48237100, 0xf7de3016, 0xb2a3fd02, 0xf6432208, 
+    0x481f7100, 0xf7de3008, 0xb2a3fcfa, 0xf6432208, 0x481b7100, 0xf7de300a, 0xb2a3fcf2, 0xf6432208, 
+    0x48177100, 0xf7de300c, 0xb2a3fcea, 0xf6432208, 0x48137100, 0xf7de300e, 0x2101fce2, 0xf7df2004, 
+    0xe8bdff63, 0xb57081f0, 0x460d4604, 0x2c264616, 0x2300dd18, 0x21022201, 0xf7de4804, 0x1fe1fcd0, 
+    0xb232b208, 0xf7ffb229, 0xe016ff17, 0xd0039800, 0xffffa01a, 0xffffaa00, 0xffff8007, 0xffff8760, 
+    0xd0034200, 0x461a2301, 0x48fa2102, 0xfcb7f7de, 0xb229b232, 0xf7ffb220, 0xbd70feff, 0x47f0e92d, 
+    0x27014606, 0xe01e2500, 0xb2851c68, 0x48f149f2, 0xf7d73010, 0xf04ffea9, 0xe0110800, 0x301048ed, 
+    0xfe9cf7d7, 0x27c0f3c0, 0x0001f108, 0xf880fa1f, 0x0ffaf1b8, 0xe005dd00, 0x04c82101, 0xff14f7df, 
+    0xd1eb2f00, 0xb10fbf00, 0xdbdd2d06, 0xda152d06, 0x301248e0, 0xfe82f7d7, 0xf980fa1f, 0xe00b2400, 
+    0xf1c01c60, 0x00800004, 0xf000fa49, 0x000ff000, 0x0014f826, 0xb2841c60, 0xddf12c03, 0x87f0e8bd, 
+    0xb086b570, 0x48d54604, 0x90036800, 0x1d0048d3, 0x90026800, 0x300848d1, 0x90016800, 0xa8032600, 
+    0xf99149cf, 0xf8301000, 0xe0145011, 0xb2821c60, 0x46282107, 0xff77f7ff, 0xf7ffa804, 0xa804ff9f, 
+    0x0014f830, 0xd1012802, 0xe0002001, 0x44302000, 0x1c68b286, 0xa802b285, 0xf99149c1, 0xf8301000, 
+    0x42a80011, 0xa801dae2, 0xf99149bd, 0xf8301000, 0x42b00011, 0x2001dc02, 0xbd70b006, 0xe7fb2000, 
+    0x4604b57c, 0x25212600, 0x1c60e013, 0x2107b282, 0xf7ff4628, 0x4668ff48, 0xff70f7ff, 0x0014f83d, 
+    0xd1012803, 0xe0002001, 0x44302000, 0x1c68b286, 0x2d24b285, 0x2e03dde9, 0x2001db01, 0x2000bd7c, 
+    0xe92de7fc, 0xb0864ff7, 0x46894680, 0x25002600, 0x90012001, 0xf247e063, 0x90035031, 0x0b00f04f, 
+    0x90022000, 0x90052001, 0x2001e048, 0x27009004, 0x1c78e020, 0x4998b207, 0x30104896, 0xfdf4f7d7, 
+    0x0a00f04f, 0x4893e012, 0xf7d73010, 0xf3c0fde7, 0x900420c0, 0x0001f10a, 0xfa80fa0f, 0x0ffaf1ba, 
+    0xe006dd00, 0x04c82101, 0xfe5ef7df, 0x28009804, 0xbf00d1e9, 0xb1089804, 0xdbda2f06, 0xda192f06, 
+    0x31124984, 0xfb022202, 0xf7d71008, 0xb284fdc7, 0x5030f247, 0xda0d4284, 0xb2051c68, 0xdd00455c, 
+    0x980346a3, 0xda004284, 0x44269403, 0x1c409802, 0x9002b280, 0x1c409805, 0x9005b200, 0x98059908, 
+    0xddb24288, 0x28019802, 0xeba6dd05, 0x9803010b, 0x1ea81a0e, 0x9801b205, 0xb2801c40, 0x98019001, 
+    0xdd984548, 0xdd052d00, 0xf0f5fb96, 0xb009b280, 0x8ff0e8bd, 0x70fff64f, 0xe92de7f9, 0xb0854ff0, 
+    0x48664606, 0x6800300c, 0x24009000, 0x200fe004, 0x0014f826, 0xb2841c60, 0xddf82c03, 0xe10d2400, 
+    0x0801f04f, 0x0900f04f, 0x0014f836, 0xd0722804, 0xb28a1c61, 0xf9934b5a, 0xf83d3000, 0x21070013, 
+    0xfe91f7ff, 0xf7ffa803, 0x2700feb9, 0xe0112500, 0xd00142ac, 0xe0002001, 0xa9032000, 0x1015f831, 
+    0xd1012904, 0xe0002101, 0xfb002100, 0xb2877001, 0xb2851c68, 0xddeb2d03, 0xdd092f00, 0xf7ff4620, 
+    0x4682fedf, 0x0f00f1ba, 0x2002d002, 0x0014f826, 0x0014f836, 0xd07c2802, 0x0901f04f, 0x4840e04f, 
+    0xb1307800, 0xb2821c60, 0x20252107, 0xfe5bf7ff, 0x1c60e005, 0x2107b282, 0xf7ff2022, 0xa801fe54, 
+    0xfe7cf7ff, 0x0b01f04f, 0xe01c2500, 0xd01842ac, 0xf830a801, 0x28040015, 0xa803d004, 0x0015f830, 
+    0xd10e2804, 0x0f00f1bb, 0xa801d009, 0x0015f830, 0xf831a903, 0x42881015, 0x2001d101, 0x2000e000, 
+    0x1c684683, 0x2d03b285, 0xf1bbdde0, 0xd0030f00, 0x0800f04f, 0xe085e016, 0x0b00f04f, 0xb28a1c61, 
+    0xf9934b1f, 0xf83d3000, 0x21070013, 0xfe1bf7ff, 0xf7ffa803, 0xf109fe43, 0xfa1f0001, 0xf1b9f980, 
+    0xddac0f1c, 0xf1b8bf00, 0xd13d0f00, 0x25002700, 0x42ace011, 0x2001d001, 0x2000e000, 0xf831a903, 
+    0x29041015, 0x2101d101, 0x2100e000, 0x7001fb00, 0x1c68b287, 0x2d03b285, 0x2f00ddeb, 0x4620dd24, 
+    0xfe5ef7ff, 0xf1ba4682, 0xd00b0f00, 0xf8262002, 0xe0190014, 0xd0039800, 0xffff9000, 0x0002fba0, 
+    0x000362d1, 0xf8262004, 0x25000014, 0xa803e00a, 0x0015f830, 0xd1032804, 0xd00142ac, 0x0015f826, 
+    0xb2851c68, 0xddf22d03, 0x0014f836, 0xd129280f, 0x0f00f1b8, 0x48f8d126, 0xb9307800, 0xf7ff4620, 
+    0xb110fe6f, 0xf8262003, 0xf8360014, 0x28030014, 0x1c60d00d, 0x2107b282, 0xf7ff2021, 0xa803fdb4, 
+    0xfddcf7ff, 0xf830a803, 0xf8260014, 0xf8360014, 0x28020014, 0x4620d106, 0xfe12f7ff, 0x2001b910, 
+    0x0014f826, 0x0014f836, 0xd105280f, 0x0f01f1b8, 0x2000d102, 0x0014f826, 0xb2841c60, 0xf77f2c03, 
+    0xb005aeef, 0x8ff0e8bd, 0x4ff0e92d, 0x2220b09b, 0xa81049da, 0xec52f003, 0x49d82220, 0xa8083120, 
+    0xec4cf003, 0x32404ad5, 0x3101e9d2, 0x68d26810, 0x3105e9cd, 0x90049207, 0x48d12100, 0xfc54f7d7, 
+    0xf7d748d0, 0x2101fc4b, 0xf7d748cf, 0xf7fffc4d, 0x2300fb95, 0xf240220a, 0x48cb4100, 0xf7de3010, 
+    0x2301fa3e, 0x0319220c, 0x302e48c7, 0xfa37f7de, 0x220d2301, 0x48c40359, 0xf7de302e, 0xf647fa30, 
+    0x48c271ff, 0xfc30f7d7, 0x22072301, 0x48bd2180, 0xfa25f7de, 0x22092301, 0x48ba0259, 0xfa1ff7de, 
+    0x22082301, 0x48b70151, 0xfa19f7de, 0x22042300, 0x48b42110, 0xfa13f7de, 0x22002301, 0x48b24619, 
+    0xfa0df7de, 0x22012300, 0x48af2102, 0xfa07f7de, 0xf7d748af, 0x49affc03, 0xf2408008, 0x48ac1140, 
+    0xfc02f7d7, 0xf7e32000, 0x2101fc16, 0xf7df2004, 0xa818fc7b, 0xfe61f7ff, 0xf99048a7, 0xa9180001, 
+    0x1010f811, 0xf99048a4, 0xaa180000, 0x0010f812, 0x1000eb01, 0xf99149a0, 0xf8321002, 0xeb011011, 
+    0x499d1000, 0x1003f991, 0x1011f832, 0x1000eb01, 0x901ab280, 0xb201981a, 0xf7d74898, 0x2401fbd5, 
+    0x1e60e064, 0xf831a918, 0x28040010, 0x1e60d003, 0x0010f831, 0xf64fb910, 0xe04b76ff, 0xa9181e60, 
+    0x0010f831, 0xd1002801, 0x2000e000, 0xf991498c, 0x1c491000, 0x49804348, 0x1000f991, 0x0081eb00, 
+    0xa810b285, 0x9025f850, 0xf850a808, 0xa804a025, 0xb015f830, 0x21074622, 0xf7ff4658, 0x2205fcc4, 
+    0x46202104, 0xfd8df7ff, 0x46304606, 0xfb24f006, 0x90034649, 0xfb34f006, 0x46514680, 0xf9a4f006, 
+    0xf0064607, 0xb286fae1, 0x78004876, 0x4630b190, 0xfef4f005, 0x22004607, 0xf0054b73, 0x2200fce7, 
+    0xe9cd4b72, 0xf0050100, 0xe9cdfc25, 0xf0050102, 0xb286fea1, 0x4a681e61, 0x4a685651, 0xeb021c92, 
+    0xb2310041, 0xfb70f7d7, 0xb2c41c60, 0xdd982c04, 0xe8bdb01b, 0xe92d8ff0, 0x460541f0, 0x8ea8460f, 
+    0x42acf240, 0x42901a81, 0xdc11d071, 0x4285f240, 0x0102eba0, 0xd0354290, 0xb1b0dc05, 0x4084f2a0, 
+    0xd17d2800, 0x291be021, 0x291cd053, 0xe05fd1f9, 0xd076290d, 0x2901dc04, 0x290cd074, 0xe0c9d1f1, 
+    0xd070292a, 0xd1ec292b, 0xe12be119, 0x32fff04f, 0x4850494f, 0xf7fe6800, 0x4604fe21, 0xb9581d20, 
+    0x4084f240, 0xe8bd86a8, 0x220081f0, 0x48494948, 0xf7fe6800, 0x4604fe13, 0xb9201d60, 0x4085f240, 
+    0xe7f086a8, 0x2c012401, 0xe10bd000, 0x88004840, 0xd12f2866, 0xf9b0483e, 0xf04f1000, 0xf04f52c0, 
+    0xf7d75000, 0x2004fbc6, 0xfc9cf7df, 0x04c82101, 0xfb8af7df, 0x49362068, 0x22008008, 0x68004835, 
+    0xfdbaf7fe, 0x1d204604, 0xf240b950, 0x86a840a0, 0x2200e7c9, 0x482f492e, 0xf7fe6800, 0x4604fdad, 
+    0x28001d60, 0xf240d105, 0x86a840a1, 0xe024e7bb, 0xe0d62401, 0x88004826, 0xd14f2868, 0xf9b04824, 
+    0xf04f1000, 0xf04f52c0, 0xf7d75000, 0xf7fffb92, 0x2069fe6b, 0x8008491e, 0x481e2200, 0xe0036800, 
+    0xe065e0c1, 0xe09de038, 0xfd86f7fe, 0x1d204604, 0xf240b950, 0x86a840ac, 0x2200e795, 0x48154914, 
+    0xf7fe6800, 0x4604fd79, 0x28001d60, 0xf240d125, 0x86a840ad, 0x0000e787, 0x000362d1, 0x0002fbb0, 
+    0xd003900c, 0xd03c804a, 0xd0039800, 0xd03c8310, 0xd28fffc0, 0x00038e68, 0x00036254, 0xd003512c, 
+    0x000362d2, 0x000362d0, 0x40590000, 0x3fe00000, 0x00038e6c, 0x00038e64, 0xe0822401, 0x8800484a, 
+    0xd1272869, 0xf9b04848, 0xf04f1000, 0xf04f52c0, 0xf7d75000, 0x2067fb3e, 0x80084943, 0x48432200, 
+    0xf7fe6800, 0x4604fd39, 0xb9501d20, 0x40b8f240, 0xe74886a8, 0x493c2200, 0x6800483c, 0xfd2cf7fe, 
+    0x1d604604, 0xd15c2800, 0x40b9f240, 0xe73a86a8, 0xe0562401, 0x88004834, 0xd1512867, 0xf9b04832, 
+    0xf04f1000, 0xf04f52c0, 0xf7d75000, 0x2300fb12, 0x2101461a, 0xf7de482e, 0x2000f852, 0x7008492d, 
+    0x8800482d, 0x0010f020, 0x8008492b, 0x20702100, 0xf9dbf7de, 0xf040b280, 0x46310601, 0xf7de2070, 
+    0xf7e5f9be, 0x2007fd24, 0x8008491f, 0x48232200, 0xf7fe6800, 0x4604fcf1, 0xb9501d20, 0x40d6f240, 
+    0xe70086a8, 0x49182200, 0x6800481c, 0xfce4f7fe, 0x1d604604, 0xf240b920, 0x86a840d7, 0x2401e6f3, 
+    0xfaf0f7e5, 0x88004816, 0x4816b201, 0xfa1cf7d7, 0x220b2300, 0x0100f640, 0xf7de4813, 0xe000f810, 
+    0xbf00e000, 0xbf00e6d2, 0xe6dcbf00, 0x2200b510, 0xf2af2101, 0xf7fe20bd, 0x2108fa52, 0xf7fe2002, 
+    0x4902fbef, 0xbd106008, 0x00038e6c, 0x00038e64, 0xd0039800, 0x000362ce, 0x00036268, 0x00038654, 
+    0x00038e68, 0xd28fffc0, 0xd03c800c, 0xf240b570, 0x486a1600, 0xf9e2f7d7, 0x2c03b284, 0xb2e4da0b, 
+    0xf8504867, 0x47a85024, 0xb2314606, 0x38164863, 0xf9daf7d7, 0xf241e005, 0x48601122, 0xf7d73814, 
+    0xbd70f9d3, 0x4605b570, 0x8ea8460e, 0x2868b120, 0x2869d010, 0xe019d140, 0xf04fe03d, 0x495932ff, 
+    0x68004859, 0xfcaaf7fe, 0x1d204604, 0x2068b948, 0xbd7086a8, 0x49532200, 0x68004853, 0xfc9ef7fe, 
+    0x1d604604, 0x2069b918, 0xe7f286a8, 0x2c012401, 0xe020d000, 0xf9b0484b, 0xf04f1000, 0xf44f4220, 
+    0xf7d71000, 0x4847fa56, 0x286f8800, 0x4845d10b, 0x28016840, 0x2102d10e, 0x38164840, 0xf994f7d7, 
+    0xffa4f7ff, 0xf04fe006, 0x210052d0, 0x1000f44f, 0xfa3ff7d7, 0xe7c0bf00, 0xbf00bf00, 0xb510e7c9, 
+    0x21012200, 0x00a3f2af, 0xf9c9f7fe, 0x2004210c, 0xfb66f7fe, 0x60084934, 0xb510bd10, 0x46214604, 
+    0x381c482e, 0xf970f7d7, 0x482c2100, 0xf7d7381c, 0xf04ff96b, 0x482931ff, 0xf7d7381a, 0x2100f965, 
+    0x381a4826, 0xf960f7d7, 0xb510bd10, 0x48232101, 0xf7d73820, 0xbd10f959, 0x2100b510, 0x3818481f, 
+    0xf952f7d7, 0x481d2104, 0xf7d73816, 0xbd10f94d, 0x4604b570, 0xb229460d, 0x38124818, 0xf944f7d7, 
+    0x48164621, 0xf7d73818, 0x2301f93f, 0x46192200, 0x38244812, 0xff33f7dd, 0xb510bd70, 0x52d0f04f, 
+    0xf44f2100, 0xf7d71000, 0x2004f9e4, 0xb570bd10, 0x52d0f04f, 0x05082102, 0xf9dbf7d7, 0x1d804807, 
+    0xf91cf7d7, 0x4628b285, 0xf829f002, 0x4621b204, 0x38144802, 0xf918f7d7, 0xbd702004, 0xd03d1030, 
+    0x00038e78, 0x0004ce9c, 0x00038e74, 0x4606b570, 0x4615460c, 0xd1032d02, 0x0c000620, 0x2424ea40, 
+    0x22072302, 0x1180f240, 0xf7dd48f7, 0x2d02fef8, 0x2300d106, 0x02292209, 0xf7dd48f3, 0xe005fef0, 
+    0x22092301, 0x48f00259, 0xfee9f7dd, 0x48eeb231, 0xf7d71e80, 0x2101f8e9, 0xf7df2004, 0xb221f965, 
+    0x1c8048e9, 0xf8e0f7d7, 0xe92dbd70, 0xf44f41f0, 0x275026b0, 0x2300683d, 0x21102204, 0xf7dd48e2, 
+    0x2301fece, 0x46192200, 0x301648df, 0xfec7f7dd, 0x461a2301, 0x48dc2102, 0xf7dd3016, 0x2300fec0, 
+    0x21022201, 0x301648d8, 0xfeb9f7dd, 0x461a2301, 0x48d52102, 0xf7dd3016, 0x2300feb2, 0xf2402207, 
+    0x48d11180, 0xfeabf7dd, 0x22092300, 0x2100f240, 0xf7dd48cd, 0x2100fea4, 0x1e8048cb, 0xf8a4f7d7, 
+    0x220f2300, 0x48c849c9, 0xfe99f7dd, 0x220f2301, 0x48c549c6, 0xfe93f7dd, 0x220f2300, 0x48c249c3, 
+    0xfe8df7dd, 0x03c82101, 0xf90ef7df, 0x220fbf00, 0x48bd49be, 0xf7dd1d80, 0x2800fe99, 0xb229d0f7, 
+    0x1f0048b9, 0xf880f7d7, 0x48b72100, 0xf7d71e80, 0x2300f87b, 0x21022201, 0xf7dd48b3, 0x2301fe70, 
+    0x21082203, 0xf7dd48b0, 0x2301fe6a, 0x46192200, 0xf7dd48ad, 0x2400fe64, 0xf836e008, 0xb2010014, 
+    0x1c8048a9, 0xf860f7d7, 0xb2841c60, 0x71d5eb05, 0x0f61ebb4, 0x2300dbf1, 0x21082203, 0xf7dd48a2, 
+    0x2300fe4e, 0x2101461a, 0xf7dd489f, 0x2301fe48, 0x2102461a, 0xf7dd489c, 0xbf00fe42, 0x499b220f, 
+    0x1d804899, 0xfe52f7dd, 0xd0f72800, 0x22012300, 0x48952102, 0xfe33f7dd, 0x81f0e8bd, 0x41f0e92d, 
+    0x27b0f44f, 0x0850f04f, 0x4000f8d8, 0x4f00f5b4, 0x2000dd02, 0x81f0e8bd, 0x488bb221, 0xf7d71f00, 
+    0x2100f823, 0x1e804888, 0xf81ef7d7, 0x22022301, 0x48852104, 0xfe13f7dd, 0x22002301, 0x48824619, 
+    0xfe0df7dd, 0xe00c2500, 0x1d00487f, 0xf806f7d7, 0xf837b286, 0x42b00015, 0x2000d001, 0x1c68e7da, 
+    0xeb04b285, 0xebb571d4, 0xdbed0f61, 0x22022300, 0x48752104, 0xfdf3f7dd, 0x461a2300, 0x48722101, 
+    0xfdedf7dd, 0x461a2301, 0x486f2102, 0xfde7f7dd, 0x22012300, 0x486c2102, 0xfde1f7dd, 0xe7b92001, 
+    0x2300b510, 0x2101461a, 0xf7dd4869, 0x2301fdd8, 0x46192200, 0xf7dd4866, 0xbd10fdd2, 0x4865b510, 
+    0xffccf7d6, 0xf404b284, 0xb3585000, 0x220d2300, 0x0100f242, 0x306e485e, 0xfdc1f7dd, 0x220b2314, 
+    0x485b495d, 0xf7dd3064, 0x2307fdba, 0x210f2200, 0x30604857, 0xfdb3f7dd, 0x22092304, 0x6100f641, 
+    0x305e4853, 0xfdabf7dd, 0x2200233f, 0x48504619, 0xf7dd3072, 0x2303fda4, 0x4950220d, 0xf7dd4850, 
+    0xe090fd9e, 0x461a2300, 0x48492101, 0xf7dd3070, 0x2304fd96, 0x4948220b, 0x30644845, 0xfd8ff7dd, 
+    0x220d2301, 0x48420359, 0xf7dd306e, 0x2300fd88, 0xf241220c, 0x483e0100, 0xf7dd306e, 0x2301fd80, 
+    0x02d9220b, 0x306e483a, 0xfd79f7dd, 0x220a2301, 0x48370299, 0xf7dd306e, 0x2301fd72, 0x2106461a, 
+    0x30704833, 0xfd6bf7dd, 0x220023ce, 0x31fff240, 0x306e482f, 0xfd63f7dd, 0x0300f241, 0xf6432200, 
+    0x482b71ff, 0xf7dd306c, 0x2300fd5a, 0x492d220c, 0x306a4827, 0xfd53f7dd, 0x22002303, 0x4824210f, 
+    0xf7dd3060, 0x2307fd4c, 0xf6412209, 0x48206100, 0xf7dd305e, 0x2302fd44, 0xf640220a, 0x481c4100, 
+    0xf7dd306a, 0x230ffd3c, 0x21782203, 0x30704818, 0xfd35f7dd, 0x220f2300, 0x48154914, 0xf7dd306e, 
+    0x2303fd2e, 0x4918220e, 0x305e4811, 0xfd27f7dd, 0x2200233f, 0x480e4619, 0xf7dd3072, 0x2301fd20, 
+    0x46192200, 0x3070480a, 0xfd19f7dd, 0x220e2301, 0x48070399, 0xf7dd306e, 0x2306fd12, 0x4907220d, 
+    0xf7dd4807, 0xbd10fd0c, 0xd203a404, 0xffff8000, 0xd203a102, 0xd03c8038, 0xfffff800, 0xffffe000, 
+    0xd2052200, 0xfffff000, 0xffffc000, 0x41f0e92d, 0x48fe2700, 0xf0007800, 0x49fd0401, 0xf7d648fd, 
+    0xf04ffef3, 0xe0487680, 0xf7de4630, 0x4606ff6b, 0xdc062e00, 0x22022300, 0x48f7210c, 0xfcdff7dd, 
+    0x2301e03c, 0x210c2202, 0xf7dd48f3, 0x2202fcd8, 0x48f1210c, 0xf7dd3018, 0x2803fce9, 0x2001d109, 
+    0x0704ea20, 0x461a2302, 0x48eb210c, 0xfcc7f7dd, 0x2202e024, 0x48e8210c, 0xf7dd3018, 0x2801fcd7, 
+    0x2c01d113, 0xf7d6d10a, 0xf000ff3f, 0x2001010f, 0xf801fa00, 0x46404601, 0xff36f7de, 0x22022300, 
+    0x48dd210c, 0xfcabf7dd, 0x4627e007, 0x22022303, 0x48d9210c, 0xfca3f7dd, 0xe7b5e000, 0x2200bf00, 
+    0x48d62101, 0xfcb2f7dd, 0xd17d2800, 0x21012200, 0x300848d2, 0xfcaaf7dd, 0xd1f62800, 0xd17442bc, 
+    0x461a2300, 0x48ce2101, 0xfc89f7dd, 0x20042101, 0xff0af7de, 0x22002301, 0x48c94619, 0xfc7ff7dd, 
+    0x13f4f240, 0xf2402200, 0x48c531ff, 0xf7dd1d80, 0x49bffc76, 0x48bf1d89, 0xfe76f7d6, 0xf7ffbf00, 
+    0xf7fffd94, 0x4605fe3b, 0xd0f82d00, 0x22042301, 0x48bc2110, 0xfc63f7dd, 0x22062301, 0x48b82140, 
+    0xf7dd1c80, 0xbf00fc5c, 0x21802207, 0xf7dd48b6, 0x2800fc6d, 0x49aed0f8, 0x48ae1dc9, 0xfe54f7d6, 
+    0xfe7cf7ff, 0x49b12000, 0x46088008, 0xf0208800, 0x3026003e, 0x46088008, 0xf0208800, 0x80080001, 
+    0x88014608, 0x20502202, 0xfd30f7ff, 0x46112201, 0xf7ff205f, 0x2301fd2b, 0x46192200, 0xf7dd489e, 
+    0x2300fc2e, 0x21022201, 0x38e0489d, 0xfc27f7dd, 0x78004896, 0x4895b118, 0x28027800, 0xf002d101, 
+    0x2301fb2f, 0xe0012200, 0xe011e045, 0x48944619, 0xf7dd1c80, 0x2303fc14, 0x21302204, 0xf7dd488e, 
+    0x2301fc0e, 0x46192200, 0xf7dd488c, 0xe047fc08, 0x2200bf00, 0x48882101, 0xf7dd3018, 0x2801fc17, 
+    0x2300d1f7, 0x21022201, 0x38e04885, 0xfbf7f7dd, 0x7800487e, 0x487db118, 0x28027800, 0xf002d101, 
+    0x2301faff, 0x46192200, 0x1c80487d, 0xfbe7f7dd, 0x22002301, 0x48784619, 0xfbe1f7dd, 0x22042302, 
+    0x48752130, 0xfbdbf7dd, 0x22002301, 0x48734619, 0xfbd5f7dd, 0x2300e014, 0x21022201, 0x38e04870, 
+    0xfbcdf7dd, 0xfdecf7ff, 0x22002301, 0x486a4619, 0xfbc5f7dd, 0x22002301, 0x48684619, 0xfbbff7dd, 
+    0x22022300, 0x4864210c, 0xfbb9f7dd, 0x1c494960, 0xf7d64860, 0xe8bdfdb9, 0xb57081f0, 0x460d4604, 
+    0x22004623, 0x485e2101, 0xf7dd381c, 0x462bfba8, 0x21012200, 0x383c485a, 0xfba1f7dd, 0xe92dbd70, 
+    0x460441f0, 0x2300460d, 0x21022201, 0x38e04854, 0xfb95f7dd, 0x461a2300, 0x48512101, 0xf7dd38e0, 
+    0x2300fb8e, 0x2101461a, 0xf7dd4851, 0x2300fb88, 0x21022201, 0x3848484e, 0xfb81f7dd, 0x461a2300, 
+    0x484b2101, 0xf7dd3848, 0x2301fb7a, 0x46192200, 0x38e04843, 0xfb73f7dd, 0x78004846, 0xd1732801, 
+    0xd0052c03, 0xd0032c02, 0xd0012c05, 0xd16b2c04, 0x220c2302, 0x48400291, 0xfb61f7dd, 0x213af241, 
+    0xf7d6483e, 0x493efd61, 0x3008483c, 0xfd5cf7d6, 0x483a493b, 0xf7d6300a, 0x210ffd57, 0x30124837, 
+    0xfd52f7d6, 0x231cb945, 0xf2402205, 0x483031e0, 0xf7dd305c, 0xe007fb44, 0x22052315, 0x31e0f240, 
+    0x305c482b, 0xfb3bf7dd, 0xd0032c03, 0xd0012c05, 0xd1172c04, 0x492b2000, 0xf04f7008, 0x210c4260, 
+    0xf7d61e40, 0x2301fde6, 0x21082203, 0x305e4820, 0xfb25f7dd, 0x22052300, 0x481d2120, 0xf7dd305e, 
+    0xe011fb1e, 0x78004820, 0xd10d2802, 0x22032300, 0x48172108, 0xf7dd305e, 0x2301fb12, 0x21202205, 
+    0x305e4813, 0xfb0bf7dd, 0x22002301, 0x4810211f, 0xf7dd305c, 0x2301fb04, 0x01512208, 0x3052480c, 
+    0xfafdf7dd, 0xe0212300, 0x0000e02d, 0x000361d8, 0xffffbbb6, 0xd03c80b8, 0xd03d1026, 0xd0034010, 
+    0xd203a1e2, 0xd203a404, 0xd203a01a, 0x00038e84, 0xd20588ae, 0x00038489, 0xd2058616, 0xd20524a6, 
+    0xffff8382, 0x00038491, 0x0003626a, 0xf640220b, 0x48fe0100, 0xfad3f7dd, 0x22062300, 0x48fb2140, 
+    0xfacdf7dd, 0x2300e074, 0x01512208, 0xf7dd48f8, 0x2300fac6, 0xf640220b, 0x48f40100, 0xfabff7dd, 
+    0x22062301, 0x48f12140, 0xfab9f7dd, 0xd0012c03, 0xd10d2c05, 0x2200230f, 0x48ec213f, 0xfaaff7dd, 
+    0x220a2300, 0x4100f240, 0xf7dd48e8, 0xe04ffaa8, 0xd1302c04, 0x780048e7, 0xd10c2801, 0x4260f04f, 
+    0x1e802112, 0xfd55f7d6, 0x22002302, 0x48df213f, 0xfa95f7dd, 0xf04fe017, 0x48df4260, 0x31107801, 
+    0xf7d61750, 0x48dcfd46, 0xb9307800, 0x2200230f, 0x48d6213f, 0xfa83f7dd, 0x2303e005, 0x213f2200, 
+    0xf7dd48d2, 0x2300fa7c, 0xf240220a, 0x48cf4100, 0xfa75f7dd, 0x2c02e01c, 0x2302d10c, 0x213f2200, 
+    0xf7dd48ca, 0x2300fa6c, 0x0261220a, 0xf7dd48c7, 0xe00dfa66, 0xd10b2c01, 0x22002301, 0x48c3213f, 
+    0xfa5df7dd, 0x220a2301, 0x48c00299, 0xfa57f7dd, 0x22072301, 0x48bd2180, 0xfa51f7dd, 0x461a2301, 
+    0x48be2102, 0xfa4bf7dd, 0x780148bd, 0x780048bd, 0xfe93f7ff, 0x22012300, 0x48bb2102, 0xfa3ff7dd, 
+    0x49ba2000, 0x48ba8008, 0x28017800, 0x2c03d115, 0x2c02d005, 0x2c04d003, 0x2c05d001, 0x48b3d10d, 
+    0xf0208800, 0x1c400001, 0x800849b0, 0x88004608, 0x0002f020, 0x80081c80, 0x48ace010, 0xf0208800, 
+    0x49aa0001, 0x46088008, 0xf0208800, 0x80080002, 0x88004608, 0x0004f020, 0x80081d00, 0x0600f44f, 
+    0x4630e03e, 0xfc8ef7de, 0x2e004606, 0x2300dc06, 0x21022201, 0xf7dd489f, 0xe032fa02, 0x461a2301, 
+    0x489c2102, 0xf9fbf7dd, 0x21022201, 0x30184899, 0xfa0cf7dd, 0x2300b198, 0x21022201, 0xf7dd4895, 
+    0x2d01f9ee, 0xf7d6d10a, 0xf000fc6f, 0x2001010f, 0xf701fa00, 0x46384601, 0xfc66f7de, 0x4a8be010, 
+    0xf2408811, 0xeb024200, 0xb2902205, 0xf7ff2202, 0x2300facd, 0x21022201, 0xf7dd4886, 0xe000f9d0, 
+    0xbf00e7bf, 0x78004882, 0x4883b968, 0x48837803, 0x48837802, 0x48837801, 0xf0027800, 0x4882f939, 
+    0xf0027800, 0x2301f9b8, 0x2102461a, 0x389a4870, 0xf9b5f7dd, 0x22002301, 0x486d4619, 0xf7dd389a, 
+    0x2301f9ae, 0x2102461a, 0x38c4486c, 0xf9a7f7dd, 0x22002301, 0x48664619, 0xf7dd3852, 0x2301f9a0, 
+    0x21042202, 0x38604862, 0xf999f7dd, 0x81f0e8bd, 0x4604b510, 0x22052301, 0x486c2120, 0xf98ff7dd, 
+    0xd0012c03, 0xd1082c05, 0x0310f640, 0xf6402200, 0x4866711f, 0xf983f7dd, 0x2c04e038, 0x4855d121, 
+    0x28017800, 0xf240d108, 0x22002304, 0x711ff640, 0xf7dd485e, 0xe029f974, 0x7800484f, 0xf640b940, 
+    0x22000310, 0x711ff640, 0xf7dd4858, 0xe01df968, 0x4308f240, 0xf6402200, 0x4854711f, 0xf95ff7dd, 
+    0x2c02e014, 0xf240d108, 0x22002304, 0x711ff640, 0xf7dd484e, 0xe009f954, 0xd1072c01, 0x1302f240, 
+    0xf6402200, 0x4849711f, 0xf949f7dd, 0x22042301, 0x48462110, 0xf7dd1c80, 0x2303f942, 0x210c2202, 
+    0x1c804842, 0xf93bf7dd, 0x22002301, 0x483f2103, 0xf7dd1c80, 0x2c03f934, 0x2c02d005, 0x2c05d003, 
+    0x2c04d001, 0x2301d138, 0x46192200, 0x300a4837, 0xf925f7dd, 0x22002301, 0x48344619, 0xf7dd300e, 
+    0x2301f91e, 0x46192200, 0x30084830, 0xf917f7dd, 0x22002301, 0x482d4619, 0xf7dd300c, 0x2304f910, 
+    0x210e2201, 0x30084829, 0xf909f7dd, 0x22012307, 0x4826210e, 0xf7dd300c, 0x2300f902, 0x2101461a, 
+    0x30084822, 0xf8fbf7dd, 0x461a2300, 0x481f2101, 0xf7dd300c, 0xe05df8f4, 0x7800481d, 0xd1592801, 
+    0x22002301, 0x48194619, 0xf7dd3008, 0x2301f8e8, 0x46192200, 0x300c4815, 0xf8e1f7dd, 0x22002301, 
+    0x48124619, 0xf7dd300a, 0xe023f8da, 0xd2058616, 0xd2058900, 0x00038492, 0x00038491, 0xd203a1c6, 
+    0x0003848a, 0x0003848b, 0xd202012c, 0x00038e86, 0x00038489, 0xd03d1026, 0x0003848f, 0x0003848e, 
+    0x0003848d, 0x0003848c, 0x00038490, 0xd03c8c00, 0x0003626a, 0x22002301, 0x48594619, 0xf8aff7dd, 
+    0x22012308, 0x4856211e, 0xf7dd1f00, 0x2308f8a8, 0x211e2201, 0xf7dd4852, 0x2300f8a2, 0x2101461a, 
+    0x1f00484f, 0xf89bf7dd, 0x461a2300, 0x484c2101, 0xf895f7dd, 0xb510bd10, 0x22052301, 0x48482120, 
+    0xf7dd380e, 0xf240f959, 0x22002304, 0x711ff640, 0x380e4843, 0xf950f7dd, 0x22042301, 0x48402110, 
+    0xf7dd380c, 0x2303f949, 0x210c2202, 0x380c483c, 0xf942f7dd, 0x22002301, 0x48392103, 0xf7dd380c, 
+    0x2301f93b, 0x46192200, 0x1f004835, 0xf934f7dd, 0x22002301, 0x48324619, 0xf92ef7dd, 0x22002301, 
+    0x482f4619, 0xf7dd1f80, 0x2301f927, 0x46192200, 0x1e80482b, 0xf920f7dd, 0x22012304, 0x4828210e, 
+    0xf7dd1f80, 0x2307f919, 0x210e2201, 0x1e804824, 0xf912f7dd, 0x461a2300, 0x48212101, 0xf7dd1f80, 
+    0x2300f90b, 0x2101461a, 0x1e80481d, 0xf904f7dd, 0xb510bd10, 0x461a2300, 0x481a2101, 0xf82ff7dd, 
+    0xb570bd10, 0x460c4605, 0x2203b2ab, 0x48162108, 0xf825f7dd, 0x2203b2ab, 0x48142108, 0xf81ff7dd, 
+    0x22002301, 0x48124619, 0xf819f7dd, 0x22002301, 0x48104619, 0xf813f7dd, 0xd0032c03, 0xd0012c05, 
+    0xd1062c04, 0x22002303, 0x480b210f, 0xf807f7dd, 0xb2a3e005, 0x210f2200, 0xf7dd4807, 0xbd70f800, 
+    0xd03c8c0e, 0xd203a102, 0xd03d0004, 0xd03d1040, 0xd003b540, 0xd003b440, 0xd003b302, 0x41f0e92d, 
+    0x27544d47, 0x2400683e, 0xeb04e035, 0xf8350084, 0xb2010010, 0xf7d64843, 0xeb04f9e7, 0x1c400084, 
+    0x0010f835, 0x483fb201, 0xf7d61c80, 0xeb04f9dd, 0x1c800084, 0x0010f835, 0x483ab201, 0xf7d61d00, 
+    0xeb04f9d3, 0x1cc00084, 0x0010f835, 0x4835b201, 0xf7d61d80, 0xeb04f9c9, 0x1d000084, 0x0010f835, 
+    0x4830b201, 0xf7d63008, 0xb221f9bf, 0x1e80482d, 0xf9baf7d6, 0x17f11c64, 0x7151eb06, 0x0fe1ebb4, 
+    0xe8bddbc3, 0xb51081f0, 0x22072301, 0x48252180, 0xf7dc30ba, 0x2301ffa4, 0x21102204, 0x30ba4821, 
+    0xff9df7dc, 0x461a2301, 0x481e2102, 0xf7dc30ba, 0x2301ff96, 0x21102204, 0x30bc481a, 0xff8ff7dc, 
+    0x461a2301, 0x48172102, 0xf7dc30bc, 0x2301ff88, 0x0359220d, 0x30ba4813, 0xff81f7dc, 0x220a2301, 
+    0x48100299, 0xf7dc30ba, 0x2100ff7a, 0x30b8480d, 0xf97af7d6, 0x22002301, 0x480a4619, 0xf7dc30b6, 
+    0xbd10ff6e, 0x4604b510, 0x48064621, 0xf7d630c0, 0x2100f96b, 0x30c04803, 0xf966f7d6, 0x0000bd10, 
+    0x0005f600, 0xd003140c, 0x4604b510, 0x780048f7, 0xd1672800, 0x2301b9c4, 0x21102204, 0xf7dc48f4, 
+    0x2300ff4e, 0x21202205, 0xf7dc48f1, 0x2300ff48, 0x21402206, 0xf7dc48ee, 0x2300ff42, 0x21802207, 
+    0xf7dc48eb, 0xe04dff3c, 0xd1182c01, 0x22042300, 0x48e72110, 0xff33f7dc, 0x22052301, 0x48e42120, 
+    0xff2df7dc, 0x22062300, 0x48e12140, 0xff27f7dc, 0x22072300, 0x48de2180, 0xff21f7dc, 0x2c02e032, 
+    0x2300d118, 0x21102204, 0xf7dc48d9, 0x2300ff18, 0x21202205, 0xf7dc48d6, 0x2301ff12, 0x21402206, 
+    0xf7dc48d3, 0x2300ff0c, 0x21802207, 0xf7dc48d0, 0xe017ff06, 0x22042300, 0x48cd2110, 0xfefff7dc, 
+    0x22052300, 0x48ca2120, 0xfef9f7dc, 0x22062300, 0x48c72140, 0xfef3f7dc, 0x22072301, 0x48c42180, 
+    0xfeedf7dc, 0xb510bd10, 0x461a2301, 0x48c02102, 0xf7dc302c, 0x2301fee4, 0x21042202, 0x302c48bc, 
+    0xfeddf7dc, 0x5307f643, 0xf6432200, 0x48b871ff, 0xf7dc302e, 0xf244fed4, 0x22000300, 0x48b41e59, 
+    0xf7dc3030, 0xf640fecc, 0x22002388, 0x71fff643, 0x303248af, 0xfec3f7dc, 0x03e2f241, 0xf6432200, 
+    0x48ab71ff, 0xf7dc3034, 0xf640feba, 0x22002388, 0x71fff643, 0x303648a6, 0xfeb1f7dc, 0x461a2300, 
+    0x71fff643, 0x303848a2, 0xfea9f7dc, 0x5307f643, 0xf6432200, 0x489e71ff, 0xf7dc303a, 0xf244fea0, 
+    0x22000300, 0x489a1e59, 0xf7dc303c, 0xf643fe98, 0x22005307, 0x71fff643, 0x303e4895, 0xfe8ff7dc, 
+    0x0300f244, 0x1e592200, 0x30404891, 0xfe87f7dc, 0x2388f640, 0xf6432200, 0x488d71ff, 0xf7dc3042, 
+    0xf241fe7e, 0x220003e2, 0x71fff643, 0x30444888, 0xfe75f7dc, 0x2388f640, 0xf6432200, 0x488471ff, 
+    0xf7dc3046, 0x2300fe6c, 0xf643461a, 0x488071ff, 0xf7dc3048, 0xf643fe64, 0x22005307, 0x71fff643, 
+    0x304a487b, 0xfe5bf7dc, 0x0300f244, 0x1e592200, 0x304c4877, 0xfe53f7dc, 0x5307f643, 0xf6432200, 
+    0x487371ff, 0xf7dc304e, 0xf244fe4a, 0x22000300, 0x486f1e59, 0xf7dc3050, 0xf640fe42, 0x22002388, 
+    0x71fff643, 0x3052486a, 0xfe39f7dc, 0x03e2f241, 0xf6432200, 0x486671ff, 0xf7dc3054, 0xf640fe30, 
+    0x22002388, 0x71fff643, 0x30564861, 0xfe27f7dc, 0x461a2300, 0x71fff643, 0x3058485d, 0xfe1ff7dc, 
+    0x5307f643, 0xf6432200, 0x485971ff, 0xf7dc305a, 0xf244fe16, 0x22000300, 0x48551e59, 0xf7dc305c, 
+    0xf643fe0e, 0x22005307, 0x71fff643, 0x305e4850, 0xfe05f7dc, 0x0300f244, 0x1e592200, 0x3060484c, 
+    0xfdfdf7dc, 0x2388f640, 0xf6432200, 0x484871ff, 0xf7dc3062, 0xf241fdf4, 0x220003e2, 0x71fff643, 
+    0x30644843, 0xfdebf7dc, 0x2388f640, 0xf6432200, 0x483f71ff, 0xf7dc3066, 0x2300fde2, 0xf643461a, 
+    0x483b71ff, 0xf7dc3068, 0xf643fdda, 0x22005307, 0x71fff643, 0x306a4836, 0xfdd1f7dc, 0x0300f244, 
+    0x1e592200, 0x306c4832, 0xfdc9f7dc, 0x22032301, 0x482f2108, 0xf7dc302c, 0xbd10fdc2, 0x2301b510, 
+    0x46192200, 0x1e80482a, 0xfdb9f7dc, 0x461a2301, 0x48272102, 0xf7dc1e80, 0x2301fdb2, 0x21042202, 
+    0x1e804823, 0xfdabf7dc, 0x22032301, 0x48202108, 0xf7dc1e80, 0x2100fda4, 0xf7d5481d, 0xbd10ffa5, 
+    0x2300b570, 0xf240220a, 0x48194100, 0xf7dc300a, 0x2400fd96, 0x2500e025, 0xeb05e01f, 0xb28300c4, 
+    0xf2402200, 0x481271ff, 0xf7dc300e, 0xeb05fd88, 0x491000c4, 0x0020f831, 0x2200b283, 0x71fff643, 
+    0x3010480b, 0xfd7bf7dc, 0x220b2301, 0x480802d9, 0xf7dc300e, 0x1c68fd74, 0x2d08b285, 0x1c60dbdd, 
+    0x2c80b284, 0x2480dbd7, 0x0000e02c, 0x000361ee, 0xd0030a04, 0x00036354, 0xe01f2500, 0x00c4eb05, 
+    0x2200b283, 0x71fff240, 0xf7dc48f9, 0xf1a4fd58, 0xeb050080, 0x49f700c0, 0x0020f831, 0x2200b283, 
+    0x71fff643, 0x1c8048f2, 0xfd49f7dc, 0x220b2301, 0x48ef02d9, 0xfd43f7dc, 0xb2851c68, 0xdbdd2d08, 
+    0xb2841c60, 0xddd72cff, 0x220a2301, 0x48e80299, 0xf7dc1f00, 0xbd70fd34, 0x2301b510, 0x2102461a, 
+    0x381248e3, 0xfd2bf7dc, 0x22022301, 0x48e02104, 0xf7dc3812, 0x2301fd24, 0x21102204, 0x381248dc, 
+    0xfd1df7dc, 0x22002301, 0x48d94619, 0xf7dc3812, 0x2201fd16, 0x48d82102, 0xfd28f7dc, 0xf7ffb938, 
+    0x2301ff6f, 0x2102461a, 0xf7dc48d3, 0x2300fd08, 0x2101461a, 0x301e48ce, 0xfd01f7dc, 0x780048cf, 
+    0xd1702803, 0x220a2301, 0x48c90299, 0xf7dc1f00, 0xf7fffcf6, 0x2301ff33, 0x46192200, 0x380e48c4, 
+    0xfcedf7dc, 0x461a2301, 0x48c12102, 0xf7dc380e, 0x2301fce6, 0x21042202, 0x380e48bd, 0xfcdff7dc, 
+    0x22032301, 0x48ba2108, 0xf7dc380e, 0x48bcfcd8, 0x0000f990, 0xfd78f7ff, 0xe0732400, 0x2301b944, 
+    0xf2402200, 0x48b211ff, 0xf7dc300e, 0xe01dfcc8, 0xd1082c01, 0x22002301, 0x11fff240, 0x301048ac, 
+    0xfcbdf7dc, 0x2c02e012, 0x2301d108, 0xf2402200, 0x48a711ff, 0xf7dc3012, 0xe007fcb2, 0x22002301, 
+    0x11fff240, 0x301648a2, 0xfca9f7dc, 0x2301b93c, 0x01512208, 0x380e489e, 0xfca1f7dc, 0x2c01e01b, 
+    0x2301d107, 0x02592209, 0x380e4899, 0xfc97f7dc, 0x2c02e011, 0x2301d108, 0x0299220a, 0x380e4894, 
+    0xfc8df7dc, 0xe030e007, 0x220b2301, 0x489002d9, 0xf7dc380e, 0xb93cfc84, 0x22082300, 0x488c0151, 
+    0xf7dc380e, 0xe01bfc7c, 0xd1072c01, 0x22092300, 0x48870261, 0xf7dc380e, 0xe011fc72, 0xd1072c02, 
+    0x220a2300, 0x48820261, 0xf7dc380e, 0xe007fc68, 0x220b2300, 0x0100f640, 0x380e487d, 0xfc5ff7dc, 
+    0xb2841c60, 0xdb892c04, 0x487ce133, 0x28057800, 0x487ad003, 0x28047800, 0x487ad1f6, 0xbbe88800, 
+    0x48732100, 0xf7d53810, 0x21f0fe4f, 0x380e4870, 0xfe4af7d5, 0x486e2120, 0xf7d5380c, 0x2120fe45, 
+    0x380a486b, 0xfe40f7d5, 0x48692120, 0xf7d53808, 0x2120fe3b, 0x1f804866, 0xfe36f7d5, 0x220a2301, 
+    0x48630299, 0xf7dc1f00, 0x2300fc2a, 0x4966220c, 0x380e485f, 0xfc23f7dc, 0x220023ff, 0x11fff240, 
+    0x1d80485b, 0xfc1bf7dc, 0x220023ff, 0x11fff240, 0x30084857, 0xfc13f7dc, 0xe00023ff, 0x2200e01d, 
+    0x11fff240, 0x300a4852, 0xfc09f7dc, 0x220023ff, 0x11fff240, 0x300c484e, 0xfc01f7dc, 0x220c230f, 
+    0x484b4951, 0xf7dc380e, 0x2300fbfa, 0x494e220c, 0x380e4847, 0xfbf3f7dc, 0x2301e0ad, 0x0299220a, 
+    0x1f004843, 0xfbebf7dc, 0xfe28f7ff, 0x22002301, 0x483f4619, 0xf7dc380e, 0x2301fbe2, 0x2102461a, 
+    0x380e483b, 0xfbdbf7dc, 0x22022301, 0x48382104, 0xf7dc380e, 0x2301fbd4, 0x21082203, 0x380e4834, 
+    0xfbcdf7dc, 0xf9904836, 0xf7ff0000, 0x2400fc6d, 0xb944e07e, 0x22002301, 0x11fff240, 0x300e482c, 
+    0xfbbdf7dc, 0x2c01e01d, 0x2301d108, 0xf2402200, 0x482711ff, 0xf7dc3010, 0xe012fbb2, 0xd1082c02, 
+    0x22002301, 0x11fff240, 0x30124821, 0xfba7f7dc, 0x2301e007, 0xf2402200, 0x481d11ff, 0xf7dc3016, 
+    0xb93cfb9e, 0x22082301, 0x48190151, 0xf7dc380e, 0xe01afb96, 0xd1072c01, 0x22092301, 0x48140259, 
+    0xf7dc380e, 0xe010fb8c, 0xd1072c02, 0x220a2301, 0x480f0299, 0xf7dc380e, 0xe006fb82, 0x220b2301, 
+    0x480b02d9, 0xf7dc380e, 0xb93cfb7a, 0x22082300, 0x48070151, 0xf7dc380e, 0xe027fb72, 0xd1152c01, 
+    0x22092300, 0x48020261, 0xf7dc380e, 0xe01dfb68, 0xd0030a12, 0x00037354, 0xd03d0008, 0x0003626a, 
+    0x000362b1, 0x000361cc, 0xfffff000, 0xd1062c02, 0x220a2300, 0x48b70261, 0xfb51f7dc, 0x2300e006, 
+    0xf640220b, 0x48b30100, 0xfb49f7dc, 0xb2841c60, 0xf6ff2c04, 0x48b0af7e, 0x28047800, 0xf7ffd108, 
+    0x2301fc52, 0x46192200, 0x302c48aa, 0xfb37f7dc, 0x880048aa, 0x2300b968, 0x21042202, 0x1f0048a5, 
+    0xfb2df7dc, 0x22022301, 0x48a22104, 0xf7dc1f00, 0xbd10fb26, 0x4604b570, 0x4616460d, 0xb2abb93c, 
+    0x211f2200, 0x1c80489b, 0xfb19f7dc, 0x2c01e01a, 0xb2abd107, 0x211f2200, 0x1d004896, 0xfb0ff7dc, 
+    0x2c02e010, 0xb2abd107, 0x211f2200, 0x1d804891, 0xfb05f7dc, 0xb2abe006, 0x211f2200, 0x3008488d, 
+    0xfafdf7dc, 0x2301b93c, 0x21202205, 0x1c804889, 0xfaf5f7dc, 0x2c01e01a, 0x2301d107, 0x21202205, 
+    0x1d004884, 0xfaebf7dc, 0x2c02e010, 0x2301d107, 0x21202205, 0x1d80487f, 0xfae1f7dc, 0x2301e006, 
+    0x21202205, 0x3008487b, 0xfad9f7dc, 0x2300b93c, 0x21202205, 0x1c804877, 0xfad1f7dc, 0x2c01e01a, 
+    0x2300d107, 0x21202205, 0x1d004872, 0xfac7f7dc, 0x2c02e010, 0x2300d107, 0x21202205, 0x1d80486d, 
+    0xfabdf7dc, 0x2300e006, 0x21202205, 0x30084869, 0xfab5f7dc, 0xb2b3b944, 0xf2402200, 0x486511ff, 
+    0xf7dc301c, 0xe01dfaac, 0xd1082c01, 0x2200b2b3, 0x11fff240, 0x301e485f, 0xfaa1f7dc, 0x2c02e012, 
+    0xb2b3d108, 0xf2402200, 0x485a11ff, 0xf7dc3020, 0xe007fa96, 0x2200b2b3, 0x11fff240, 0x30244855, 
+    0xfa8df7dc, 0x2301b934, 0x01512208, 0xf7dc4851, 0xe017fa86, 0xd1062c01, 0x22092301, 0x484d0259, 
+    0xfa7df7dc, 0x2c02e00e, 0x2301d106, 0x0299220a, 0xf7dc4848, 0xe005fa74, 0x220b2301, 0x484502d9, 
+    0xfa6df7dc, 0x2300b934, 0x01512208, 0xf7dc4841, 0xe018fa66, 0xd1062c01, 0x22092300, 0x483d0261, 
+    0xfa5df7dc, 0x2c02e00f, 0x2300d106, 0x0261220a, 0xf7dc4838, 0xe006fa54, 0x220b2300, 0x0100f640, 
+    0xf7dc4834, 0xbd70fa4c, 0x41f0e92d, 0x460f4604, 0x88004832, 0xd15a2800, 0x2500463e, 0xda082e00, 
+    0xf506e004, 0xb20670ff, 0xb2051c68, 0xdbf82e00, 0xe004e008, 0x70fff5a6, 0x1e68b206, 0xf5b6b205, 
+    0xdaf77fff, 0x78004826, 0x4826b920, 0x0000f990, 0xd03b4284, 0x49242000, 0xb2b37008, 0x3114491d, 
+    0x0044eb01, 0xf2402200, 0xf7dc11ff, 0x2001fa18, 0xb28340a0, 0x491d220c, 0xf7dc4816, 0xb93cfa10, 
+    0x2200b2ab, 0x4813211f, 0xf7dc1c80, 0xe01afa08, 0xd1072c01, 0x2200b2ab, 0x480e211f, 0xf7dc1d00, 
+    0xe010f9fe, 0xd1072c02, 0x2200b2ab, 0x4809211f, 0xf7dc1d80, 0xe006f9f4, 0x2200b2ab, 0x4805211f, 
+    0xf7dc3008, 0x2001f9ec, 0x70084907, 0xe8bdbf00, 0x000081f0, 0xd0030a04, 0x0003626a, 0x000361cc, 
+    0x000361ee, 0x000362b1, 0x00038b1d, 0xfffff000, 0x4604b570, 0xb2a8460d, 0xea0149f8, 0x43084104, 
+    0x5680f040, 0x48f64631, 0xfbc3f7d5, 0x2210bf00, 0x48f30311, 0xf7dc1d00, 0x2801f9b2, 0x2100d0f7, 
+    0xf7d548ef, 0x2100fbb6, 0x3080f44f, 0xfc3cf7dd, 0xb570bd70, 0x46234604, 0x49e82210, 0xf7dc48e8, 
+    0xbf00f987, 0x03112210, 0x1d0048e5, 0xf997f7dc, 0xd0f72801, 0xf64f2200, 0x48e171ff, 0xf7dc1d00, 
+    0xb285f98e, 0x48de2100, 0xfb93f7d5, 0xf44f2100, 0xf7dd3080, 0x4628fc19, 0xe92dbd70, 0x460441f0, 
+    0x4616460d, 0xb2a0461f, 0xffd3f7ff, 0xea284680, 0xfa070005, 0x4029f106, 0xfa1f4308, 0xb2a0f880, 
+    0xf7ff4641, 0xe8bdffa5, 0xb51081f0, 0x46234604, 0xf06f2208, 0x200601ff, 0xffdff7ff, 0xf44f2100, 
+    0xf7dd3000, 0x2301fbf1, 0x2102461a, 0xf7ff2000, 0x2100ffd4, 0x3000f44f, 0xfbe6f7dd, 0x22012300, 
+    0x46182102, 0xffc9f7ff, 0xf44f2100, 0xf7dd1000, 0xbd10fbdb, 0xf240b510, 0x48ba310f, 0xfb54f7d5, 
+    0x220023e0, 0x48b721ff, 0xf7dc1c80, 0x23c0f948, 0x21ff2200, 0x1d0048b3, 0xf941f7dc, 0x22002301, 
+    0x48b04619, 0xf7dc1d80, 0x2100f93a, 0x3080f44f, 0xfbbaf7dd, 0xb570bd10, 0x460d4606, 0x48aa4614, 
+    0x282a8800, 0xb10dd02f, 0xffd4f7ff, 0x4620e014, 0xfba8f7dd, 0x2c004604, 0x48a2dd05, 0xf7d530a2, 
+    0x280ffb1d, 0x210fd105, 0x3082489e, 0xfb1cf7d5, 0xb10de008, 0xffbef7ff, 0x30a2489a, 0xfb0ef7d5, 
+    0xd1e442b0, 0x2c00bf00, 0x4896dd05, 0xf7d530a2, 0x280ffb05, 0x4895d107, 0xb9107800, 0xf7ff20b0, 
+    0x2000ff84, 0x2001bd70, 0xb570e7fc, 0xe0242400, 0xeb01498f, 0x22101084, 0xf7dc498e, 0xb285f8e0, 
+    0x3908498b, 0x1084eb01, 0x2210462b, 0xf7dc4989, 0x4987f8bf, 0x1084eb01, 0xf64f2200, 0xf7dc71ff, 
+    0xb286f8ce, 0x1f094982, 0x1084eb01, 0x22104633, 0xf7dc4980, 0x1c60f8ad, 0x2c23b2c4, 0xbd70dbd8, 
+    0x2400b570, 0x497ce013, 0x0084eb01, 0xf6472200, 0xf7dc71ff, 0xb285f8b4, 0xeb014978, 0x462b0084, 
+    0xf6472200, 0xf7dc71ff, 0x1c60f893, 0x2c20b2c4, 0xbd70dbe9, 0x2400b570, 0x496de026, 0x1084eb01, 
+    0x496c2210, 0xf89bf7dc, 0x4969b285, 0xeb013908, 0x462b1084, 0xf64f2200, 0xf7dc71ff, 0x4964f879, 
+    0x1084eb01, 0xf64f2200, 0xf7dc71ff, 0xb286f888, 0x1f09495f, 0x1084eb01, 0x22004633, 0x71fff64f, 
+    0xf866f7dc, 0xb2c41c60, 0xdbd62c23, 0xb570bd70, 0xe0132400, 0xeb014958, 0x22000084, 0x71fff647, 
+    0xf86df7dc, 0x4956b285, 0x0084eb01, 0x2200462b, 0x71fff647, 0xf84cf7dc, 0xb2c41c60, 0xdbe92c20, 
+    0xb570bd70, 0xbf004604, 0x4949bf00, 0x1084eb01, 0xfa5af7d5, 0x2036b285, 0x00404368, 0x31e8f240, 
+    0xf64f4348, 0xfb9071fe, 0xeb00f0f1, 0x00460080, 0xbd704630, 0x4604b5f0, 0x1ad79d05, 0x7c10f242, 
+    0xf70cfb07, 0x0c01eba4, 0xf6fcfb97, 0xf2421aef, 0xfb077c10, 0xfb97f70c, 0x1878f7f6, 0xb570bdf0, 
+    0xbf004604, 0x4932bf00, 0x1084eb01, 0xfa2cf7d5, 0x20360c05, 0x00404368, 0x31e8f240, 0xf64f4348, 
+    0xfb9071fe, 0xeb00f0f1, 0x00460080, 0xbd704630, 0xb9114601, 0x3061f646, 0x29014770, 0xf246d102, 
+    0xe7f95060, 0xd1022902, 0x3003f245, 0x2903e7f4, 0xf243d102, 0xe7ef50bc, 0xd1022904, 0x1086f249, 
+    0x2905e7ea, 0xf248d102, 0xe7e560f7, 0xd1022906, 0x60abf646, 0x2907e7e0, 0xf644d102, 0xe7db004c, 
+    0xd1012908, 0xe7d74817, 0xd1012909, 0xe7d34816, 0xd101290a, 0xe7cf4815, 0xd102290b, 0x4015f64c, 
+    0x290ce7ca, 0x4812d101, 0x290de7c6, 0x4811d101, 0x290ee7c2, 0xf64dd120, 0xe7bd7066, 0x03ff0000, 
+    0xd1811400, 0xd03d443e, 0x000361ce, 0x000361d8, 0xd181401c, 0xffff0000, 0xd1812220, 0xd1812e00, 
+    0xd1812d00, 0x0001a2d4, 0x00018038, 0x00013ed9, 0x00012f91, 0x00010c7a, 0xd102290f, 0x408ff648, 
+    0x2910e79a, 0x48fed101, 0x2911e796, 0xf24fd102, 0xe7917044, 0xd1022912, 0x7071f64c, 0x2913e78c, 
+    0xf248d102, 0xe78770a3, 0xd1022914, 0x5052f24a, 0x2915e782, 0xf648d102, 0xe77d70c9, 0xd1022916, 
+    0x2028f647, 0x2917e778, 0xf644d102, 0xe77350c7, 0xd1022918, 0x60b7f242, 0x2919e76e, 0xf242d102, 
+    0xe76930b8, 0xd102291a, 0x2051f242, 0x291be764, 0xf242d102, 0xe75f20c6, 0xd102291c, 0x0003f242, 
+    0x291de75a, 0xf242d102, 0xe7553034, 0xd102291e, 0x0065f641, 0x291fe750, 0xf641d102, 0xe74b0093, 
+    0xd1022920, 0x0090f640, 0x2921e746, 0xf240d102, 0xe7416063, 0xd1022922, 0x70cdf240, 0x2923e73c, 
+    0xf240d102, 0xe7376097, 0xe7352000, 0x4604b570, 0xbf00bf00, 0xeb0149cb, 0xf7d50084, 0xf3c0f945, 
+    0x2036050e, 0xf000fb15, 0x31e8f240, 0xf64f4348, 0xfb9071fe, 0xeb00f0f1, 0x00460080, 0xbd704630, 
+    0x4ff8e92d, 0x46884607, 0xe0172400, 0xf7ffb2e0, 0x4681ff0f, 0xf7ffb2e0, 0x4682ffd9, 0xf8cd48ba, 
+    0xf8509000, 0x46532024, 0x46384641, 0xfed2f7ff, 0x42b54605, 0x462edd00, 0xb2441c60, 0xdbe52c20, 
+    0xe0272400, 0xf7ffb2e0, 0x4681feda, 0x50bcf243, 0x48ae9000, 0x2024f850, 0x4641464b, 0xf7ff4638, 
+    0x4605feb9, 0xdd0042b5, 0xb2e0462e, 0xfe99f7ff, 0xf2464681, 0x90005060, 0xf85048a5, 0x464b2024, 
+    0x46384641, 0xfea6f7ff, 0x42b54605, 0x462edd00, 0xb2441c60, 0xdbd52c23, 0xe8bd4630, 0xe92d8ff8, 
+    0x46045fff, 0x0b00f04f, 0x2200b9fc, 0x31fff240, 0x38204894, 0xfed3f7db, 0xfb80fa1f, 0xf0034658, 
+    0x4a94fc4d, 0xe9cd4b94, 0xf0030102, 0x4607fc97, 0x4b934a92, 0xfdc6f003, 0xf0034605, 0x4681f949, 
+    0xf0044648, 0x4682f805, 0x2c03e0c0, 0x2200d12e, 0x31fff240, 0x38144883, 0xfeb1f7db, 0xfb80fa1f, 
+    0xf0034658, 0x4607fc2b, 0x4b862200, 0xfa1ef003, 0x4b852200, 0x0100e9cd, 0xfc70f003, 0x3266f04f, 
+    0xe9cd4b82, 0xf0030102, 0x4605fa11, 0xf920f003, 0x497f4681, 0xf0034648, 0x4606ff19, 0xf004497d, 
+    0x4605f83f, 0xffd4f003, 0xe08f4682, 0xd12e2c04, 0xf2402200, 0x486b31ff, 0xf7db3810, 0xfa1ffe80, 
+    0x4658fb80, 0xfbfaf003, 0x22004605, 0xf0034b6d, 0x4607f9ed, 0x4b6c2200, 0xfc40f003, 0x3266f04f, 
+    0xe9cd4b6a, 0xf0030100, 0xe9cdf9e1, 0xf0030102, 0x4681f8ef, 0x46484966, 0xfee8f003, 0x49654606, 
+    0xf80ef004, 0xf0034605, 0x4682ffa3, 0x2c05e05e, 0x2200d12d, 0x31fff240, 0x380c4852, 0xfe4ff7db, 
+    0xfb80fa1f, 0xf0034658, 0x2200fbc9, 0xe9cd4b55, 0xf0030100, 0x4607f9bb, 0x4b532200, 0xfc0ef003, 
+    0x4a554605, 0xf0034b55, 0xe9cdf9b1, 0xf0030102, 0x4681f8bf, 0x4648494e, 0xfeb8f003, 0x494d4606, 
+    0xffdef003, 0xf0034605, 0x4682ff73, 0x2c06e02e, 0x2200d12c, 0x31fff240, 0x3808483a, 0xfe1ff7db, 
+    0xfb80fa1f, 0xf0034658, 0x4605fb99, 0x4b3d2200, 0xf98cf003, 0x22004607, 0xf0034b3b, 0x4a3efbdf, 
+    0xe9cd4b3f, 0xf0030100, 0xe9cdf981, 0xf0030102, 0x4681f88f, 0x46484936, 0xfe88f003, 0x49354606, 
+    0xffaef003, 0xf0034605, 0x4682ff43, 0xb0044650, 0x9ff0e8bd, 0x47f0e92d, 0x210b2600, 0xf7d54831, 
+    0xf44ff803, 0x21000280, 0xf7ff200b, 0xb2c5fcc4, 0x2000b915, 0x87f0e8bd, 0x1200f44f, 0x20012100, 
+    0xfcb9f7ff, 0xb90db2c5, 0xe7f32000, 0xf7ff2003, 0x4607fef6, 0xe0072400, 0xf7ff4620, 0x4912fe87, 
+    0x0024f841, 0xb2c41c60, 0xdbf52c20, 0xe00d2400, 0xf7ff4620, 0x490dfd94, 0x0024f841, 0xf7ff4620, 
+    0x490bfd60, 0x0024f841, 0xb2c41c60, 0xdbef2c23, 0x48142101, 0xffc8f7d4, 0x1200f44f, 0xe0232100, 
+    0x00011b8e, 0xd1812220, 0x0004c648, 0x0004c6c8, 0x0004c754, 0xb3d07c85, 0x3fdff559, 0x84b5dcc6, 
+    0x407a937c, 0x40900000, 0x408b8000, 0x3fe66666, 0x447a0000, 0x461c4000, 0x9999999a, 0x3fd99999, 
+    0x3fc99999, 0xd03d44c0, 0xf7ff2002, 0xb2c5fc64, 0x2000b90d, 0x2003e79e, 0xfea1f7ff, 0x46414680, 
+    0xf7ff4638, 0x4606fe4d, 0x48feb231, 0xff8cf7d4, 0x48fc1431, 0xf7d41c80, 0x2102ff87, 0x1e8048f9, 
+    0xff82f7d4, 0x1200f44f, 0x20032100, 0xfc43f7ff, 0xb90db2c5, 0xe77d2000, 0xf7ff2003, 0x4681fe80, 
+    0x46384649, 0xfe2cf7ff, 0xb2314606, 0xf7d448ed, 0x1431ff6b, 0x1c8048eb, 0xff66f7d4, 0x48e92103, 
+    0xf7d41e80, 0xf44fff61, 0x21001200, 0xf7ff2004, 0xb2c5fc22, 0x2000b90d, 0xf7ffe75c, 0xf7fffcc8, 
+    0x2104fc99, 0x1e8048df, 0xff4ef7d4, 0x1200f44f, 0x20052100, 0xfc0ff7ff, 0xb90db2c5, 0xe7492000, 
+    0xfc6ef7ff, 0xfc41f7ff, 0x48d62105, 0xf7d41e80, 0xf44fff3b, 0x21001200, 0xf7ff2006, 0xb2c5fbfc, 
+    0x2000b90d, 0x2101e736, 0xf7d448cf, 0x2001ff2d, 0xb510e730, 0xe0072400, 0xeb0149cc, 0x49cc1084, 
+    0xff17f7d4, 0xb2c41c60, 0xdbf52c23, 0xb510bd10, 0xf7d448c8, 0x4604ff09, 0x047ff044, 0x48c54621, 
+    0xff07f7d4, 0x48c32100, 0xf7d41d00, 0xf04fff02, 0x48c031ff, 0xf7d43808, 0x210ffefc, 0x1f0048bd, 
+    0xfef7f7d4, 0x48bb2100, 0xf7d43808, 0x2100fef2, 0x1f0048b8, 0xfeedf7d4, 0xffcbf7ff, 0xb510bd10, 
+    0x210ff240, 0x388448af, 0xfeeef7d4, 0x220023c0, 0x48ac21ff, 0xf7db3882, 0x23e0fce2, 0x21ff2200, 
+    0x388048a8, 0xfcdbf7db, 0x22002301, 0x48a54619, 0xf7db387e, 0x2100fcd4, 0x3080f44f, 0xff54f7dc, 
+    0xb510bd10, 0x48a44604, 0x282a8800, 0xb221d006, 0x1e80489c, 0xfec8f7d4, 0xffd1f7ff, 0xe92dbd10, 
+    0x460547f0, 0x463e460f, 0x0800f04f, 0x2ec6e023, 0x2e60dc01, 0x4638da03, 0xfb37f7ff, 0x4630e01e, 
+    0xfb33f7ff, 0xf7ff2003, 0x4604fdba, 0x0032f1a5, 0xdc0342a0, 0x42843064, 0xe00fdc00, 0x211f1b60, 
+    0xf0f1fb90, 0xf980fa0f, 0x0009eba6, 0xf108b286, 0xfa4f0001, 0xf1b8f880, 0xdbd80f32, 0x4630bf00, 
+    0x87f0e8bd, 0x4ff0e92d, 0xf04fb08f, 0x20000800, 0x210b9006, 0x1e80487b, 0xfe86f7d4, 0xff8ff7ff, 
+    0x0280f44f, 0x200b2101, 0xfb45f7ff, 0xb91fb2c7, 0xb00f2000, 0x8ff0e8bd, 0xf7ff2006, 0x0a00faba, 
+    0xf242900e, 0x990e7010, 0xffa9f7ff, 0x2003900d, 0xfd75f7ff, 0x20019009, 0xff93f7ff, 0xe0072400, 
+    0xf7ff4620, 0x496dfd03, 0x0024f841, 0xb2c41c60, 0xdbf52c20, 0xe00d2400, 0xf7ff4620, 0x4968fc10, 
+    0x0024f841, 0xf7ff4620, 0x4966fbdc, 0x0024f841, 0xb2c41c60, 0xdbef2c23, 0x1200f44f, 0x46082101, 
+    0xfb09f7ff, 0xb90fb2c7, 0xe7c22000, 0x380a980d, 0x990a900a, 0xf7ffb288, 0x2003fab8, 0xfd3ff7ff, 
+    0xe9dd9008, 0x1a080108, 0xda072864, 0xf7ff200f, 0x20b0ff58, 0xfaa9f7ff, 0xe7aa2000, 0xf7ff2002, 
+    0xe9ddff50, 0xf7ff1008, 0x4680fcdb, 0x1200f44f, 0x20022101, 0xfadff7ff, 0xb90fb2c7, 0xe7982000, 
+    0x30204840, 0xfe0af7d4, 0x483e4683, 0xf7d43022, 0xea4bfe05, 0x90064000, 0x45409806, 0x9d06dd01, 
+    0x4645e000, 0x5088f5a5, 0x211f3894, 0xf0f1fb90, 0x900cb280, 0x7096f505, 0x980c9007, 0xb280300a, 
+    0x980b900b, 0xfa71f7ff, 0xf7ff2003, 0x9007fcf8, 0xf7ff2003, 0x9907ff16, 0xf7ff9809, 0x4680fca1, 
+    0x1200f44f, 0x20032101, 0xfaa5f7ff, 0xb90fb2c7, 0xe75e2000, 0x30204823, 0xfdd0f7d4, 0x48214683, 
+    0xf7d43022, 0xea4bfdcb, 0x90064000, 0x45409806, 0x9d06dd01, 0x4645e000, 0x1934f242, 0x70d8f242, 
+    0xf04f9002, 0xf2400afa, 0x900110f4, 0xeba09802, 0x98010109, 0x0000ebaa, 0x98014401, 0x000aeba0, 
+    0x7210f242, 0xf002fb10, 0xf0f1fb90, 0xeba99004, 0x9804010a, 0x46104341, 0xf0f0fb91, 0x0000ebaa, 
+    0x98049003, 0x46114368, 0xf1f1fb90, 0x44089803, 0x98059005, 0xfa0f182e, 0x4802f188, 0xf7d4387c, 
+    0xe011fd93, 0xd03d44c2, 0xd03d1024, 0xd1814010, 0x7fff00cf, 0xd1812074, 0x000361ce, 0x0004c648, 
+    0x0004c6c8, 0x0004c754, 0x4128ea4f, 0xf7d448fc, 0xb229fd7b, 0x1c8048fa, 0xfd76f7d4, 0x48f81429, 
+    0xf7d41d00, 0xb231fd71, 0x1d8048f5, 0xfd6cf7d4, 0x48f31431, 0xf7d43008, 0x9802fd67, 0xdd014286, 
+    0xe0029e02, 0xda00454e, 0xf5a6464e, 0x38945088, 0xfb90211f, 0xb280f0f1, 0x4630900c, 0xf7ff990c, 
+    0x900dfe8e, 0xb201980d, 0x300c48e5, 0xfd4cf7d4, 0xf7ff2004, 0xf7fffe76, 0xf7fffaba, 0xf44ffa8b, 
+    0x21011200, 0xf7ff2004, 0xb2c7fa06, 0x2000b90f, 0x48dbe6bf, 0xf7d4300c, 0x1d00fd31, 0xfb80fa1f, 
+    0xf7ff4658, 0x2005f9b2, 0xfe5bf7ff, 0xfa58f7ff, 0xfa2bf7ff, 0x1200f44f, 0x20052101, 0xf9ebf7ff, 
+    0xb90fb2c7, 0xe6a42000, 0x300c48cd, 0xfd16f7d4, 0xfb80fa1f, 0xf7ff4658, 0x2006f998, 0xfe41f7ff, 
+    0xe696980d, 0x49c7b510, 0xf7d448c7, 0x48c7fd0d, 0xb9387800, 0x0120f640, 0xf7ff2000, 0x20b0f929, 
+    0xf983f7ff, 0x780048c2, 0xd1032801, 0x49c12002, 0xe04f7008, 0x780048bd, 0x2200bb00, 0x48b82101, 
+    0xf7db381e, 0x2801fb03, 0xf7ffd110, 0xf7fffdd0, 0x49b9fe59, 0x21018008, 0xf7d448b8, 0x2300fce5, 
+    0x21042202, 0xf7db48b6, 0xe029fada, 0xf7ff200f, 0x2101fe08, 0xf7d448b1, 0xe021fcd7, 0x780048ab, 
+    0xd1102802, 0xfdb3f7ff, 0xfcc4f7ff, 0x800849aa, 0x48aa2101, 0xfcc8f7d4, 0x22022300, 0x48a82104, 
+    0xfabdf7db, 0xbf00e00c, 0x301848a4, 0xfcb6f7d4, 0xd0f92800, 0x22022300, 0x48a12104, 0xfaaff7db, 
+    0x8800489d, 0x2001b118, 0x7008499a, 0x2002e002, 0x70084998, 0x1c494993, 0xf7d44893, 0xbd10fca5, 
+    0x4605b570, 0x46292400, 0xf7fd2002, 0xe004fb51, 0x300e4892, 0xfc92f7d4, 0x2c044604, 0x2c08d005, 
+    0xf241d003, 0x42841022, 0x2100d1f2, 0x4000f240, 0xfd0af7dc, 0xd1042c04, 0x30104888, 0xfc7ef7d4, 
+    0x2000bd70, 0xb570e7fc, 0x48804605, 0xb1187800, 0x7800487e, 0xd1042802, 0xf7ff4628, 0xb204fb80, 
+    0x4628e003, 0xffccf7ff, 0x46204604, 0xb510bd70, 0x22002301, 0x487b4619, 0xfa3af7db, 0x461a2300, 
+    0x48782101, 0xfa34f7db, 0x220023ff, 0x48754619, 0xf7db3830, 0x2300fa2d, 0x21ff461a, 0x38304871, 
+    0xfa26f7db, 0x31fff04f, 0x382c486e, 0xfc41f7d4, 0x486c2100, 0xf7d4382c, 0x230ffc3c, 0x46192200, 
+    0x38284868, 0xfa14f7db, 0x461a2300, 0x4865210f, 0xf7db3828, 0xf04ffa0d, 0x486231ff, 0xf7d43824, 
+    0x2100fc28, 0x3824485f, 0xfc23f7d4, 0x31fff04f, 0x3820485c, 0xfc1df7d4, 0x485a2100, 0xf7d43820, 
+    0x233ffc18, 0x46192200, 0x381c4856, 0xf9f0f7db, 0x461a2300, 0x4853213f, 0xf7db381c, 0x2300f9e9, 
+    0x2101461a, 0x3838484f, 0xf9e2f7db, 0xf44f2100, 0xf7dc1000, 0xbd10fc89, 0x4ff8e92d, 0x90002000, 
+    0xf04f4683, 0xf04f09b6, 0x48400a80, 0x28027800, 0x2100d10a, 0x307e483a, 0xfbf6f7d4, 0x48382100, 
+    0xf7d43080, 0xe00cfbf1, 0x78004838, 0x2118b948, 0x30764833, 0xfbe8f7d4, 0x48312100, 0xf7d43076, 
+    0x2400fbe3, 0x4938e01f, 0x0084eb01, 0xfbccf7d4, 0x060ef3c0, 0xeb014935, 0xf7d40084, 0xf3c0fbc5, 
+    0x4933070e, 0x0084eb01, 0xfbbef7d4, 0x080ef3c0, 0xda0242be, 0x90002001, 0x4546e003, 0xf04fdc01, 
+    0x1c600b01, 0x2c20b2c4, 0x2400dbdd, 0x4929e05a, 0x1084eb01, 0xfba8f7d4, 0x49260c06, 0xeb013908, 
+    0xf7d41084, 0xb287fba1, 0x39084922, 0x1084eb01, 0xfb9af7d4, 0x4810ea4f, 0xda0242be, 0x90002001, 
+    0x4546e003, 0xf04fdc01, 0x491a0b01, 0x1084eb01, 0xfb8af7d4, 0x4917b286, 0xeb011f09, 0xf7d41084, 
+    0xb287fb83, 0x1f094913, 0x1084eb01, 0xfb7cf7d4, 0x4810ea4f, 0xda1f42be, 0x90002001, 0x0000e020, 
+    0xd03d4448, 0xffffbbb9, 0xd03c80b8, 0x000361d8, 0x00038470, 0x0003846c, 0x0003846e, 0xd03d1024, 
+    0xd03d0008, 0xd1812038, 0xd1812220, 0xd1812d00, 0xd1812e00, 0xd181401c, 0xdc014546, 0x0b01f04f, 
+    0xb2c41c60, 0xdba22c23, 0x48494659, 0xfb5cf7d4, 0x78004848, 0xd1102802, 0x28019800, 0x2101d105, 
+    0x30744843, 0xfb50f7d4, 0xf1bbe007, 0xd0040f01, 0x483f2101, 0xf7d43076, 0x483efb47, 0xbb207800, 
+    0xffe8f7fe, 0xf44f2100, 0xf7dc3080, 0x9800fbbd, 0xd0052801, 0x30944836, 0xfb30f7d4, 0xd1152801, 
+    0x1c804833, 0xfb2af7d4, 0xb2851c40, 0xdd01454d, 0xe002464d, 0xda004555, 0x46284655, 0xffa5f7fe, 
+    0x482bb229, 0xf7d41c80, 0xe021fb1f, 0x0f01f1bb, 0x4827d01e, 0xf7d43096, 0x2801fb11, 0x1e81d118, 
+    0xf7d44823, 0x4822fb11, 0xf7d41c80, 0x1e40fb07, 0x454db285, 0x464ddd01, 0x4555e002, 0x4655da00, 
+    0xf7fe4628, 0xb229ff82, 0x1c804819, 0xfafcf7d4, 0x8ff8e8bd, 0xf7ffb510, 0xf7fffe8a, 0xbd10feed, 
+    0x220ab510, 0x4100f240, 0xf7db4813, 0x2801f8d8, 0x2200d11d, 0x31fff240, 0xf7db480f, 0xb284f8d0, 
+    0x22004623, 0x31fff240, 0x384e4809, 0xf8d7f7db, 0x220a2301, 0x48060299, 0xf7db384e, 0x2300f8d0, 
+    0xf240220a, 0x48024100, 0xf7db384e, 0xbd10f8c8, 0xd03d4452, 0x000361d8, 0xd1812200, 0x4604b570, 
+    0xb90b2000, 0xe0002601, 0x46352600, 0xdd022c0a, 0x1601f240, 0x293c4330, 0xf440dd01, 0xb91d7081, 
+    0xdd012a12, 0x7082f440, 0x2a17b11d, 0xf440dd01, 0x2b057082, 0xf440dd01, 0x18a67084, 0x1c76441e, 
+    0xdd01428e, 0x7090f440, 0x44161866, 0x2e3c441e, 0xf440dd01, 0xb92570a0, 0x2e1618a6, 0xf440dd01, 
+    0xb12570c0, 0x2e1b18a6, 0xf440dd01, 0xbd7070c0, 0x41f0e92d, 0x460f4604, 0x461e4615, 0x462a4633, 
+    0x46204639, 0xffbaf7ff, 0x23084680, 0xf2402206, 0x485431c0, 0xf873f7db, 0x220a2302, 0x4100f643, 
+    0xf7db4850, 0xf1b8f86c, 0xd1610f00, 0x2001b90e, 0x2000e000, 0x220f4603, 0x484a494b, 0xf7db1d00, 
+    0x2c00f85e, 0x2001dd01, 0x2000e000, 0x220e4603, 0x0100f244, 0x1d004843, 0xf851f7db, 0xdd012d00, 
+    0xe0002001, 0x46032000, 0xf242220d, 0x483d0100, 0xf7db1d00, 0x2e00f844, 0x2001dd01, 0x2000e000, 
+    0x220c4603, 0x0100f241, 0x1d004836, 0xf837f7db, 0x22004623, 0x4833210f, 0xf7db30da, 0x463bf830, 
+    0x213f2200, 0x30dc482f, 0xf829f7db, 0x2205462b, 0x31e0f240, 0x30da482b, 0xf821f7db, 0x22074633, 
+    0x7180f240, 0x30dc4827, 0xf819f7db, 0x442819e0, 0x282d4430, 0x2305dd06, 0x213c2202, 0xf7db4821, 
+    0xe005f80e, 0x22022304, 0x481e213c, 0xf807f7db, 0xe8bd4640, 0xb51081f0, 0x2c054604, 0xe8dfd22c, 
+    0x0b03f004, 0x00231b13, 0x461a2300, 0x4815210f, 0xf7da1e80, 0xe021fff4, 0x22002301, 0x4811210f, 
+    0xf7da1e80, 0xe019ffec, 0x22002303, 0x480d210f, 0xf7da1e80, 0xe011ffe4, 0x22002307, 0x4809210f, 
+    0xf7da1e80, 0xe009ffdc, 0x2200230f, 0x48054619, 0xf7da1e80, 0xe001ffd4, 0xbd102011, 0x2000bf00, 
+    0x0000e7fb, 0xd203a146, 0xffff8000, 0x4606b570, 0xfa24f000, 0xf1066805, 0xf020000b, 0x42b40407, 
+    0x2000bf98, 0x462bd915, 0xb1ba686a, 0x42a06810, 0xf104d310, 0x42880108, 0x6850bf3c, 0xd3076058, 
+    0x19106851, 0x68116041, 0x60011b09, 0x60146058, 0xbd701d10, 0x68524613, 0xd1e72a00, 0x46284621, 
+    0xfa04f000, 0xd1de2800, 0xb570bd70, 0x1f054604, 0xf9f4f000, 0x2c006800, 0x6844bf18, 0x2c00d01b, 
+    0x42acbf18, 0x4620bf3c, 0xd3f86864, 0x180a6801, 0xbf1842aa, 0xd1036045, 0x4605682a, 0x60014411, 
+    0x19416828, 0xbf1842a1, 0xd104606c, 0x60696861, 0x44086821, 0xbd706028, 0x0320f1b2, 0xf1c2d50a, 
+    0xfa200320, 0xfa01f002, 0xfa21f303, 0xea40f102, 0x47700003, 0xf003fa21, 0x0100f04f, 0x00004770, 
+    0xe92d4010, 0xe1b040c1, 0xe02440a3, 0x5a000002, 0xe2700000, 0xe2611000, 0x32411001, 0xe1130003, 
+    0x5a000002, 0xe2722000, 0xe2633000, 0x32433001, 0xeb0000fa, 0xe3140101, 0x0a000002, 0xe2700000, 
+    0xe2611000, 0x32411001, 0xe3140102, 0x0a000002, 0xe2722000, 0xe2633000, 0x32433001, 0xe8bd8010, 
+    0xb51cb40f, 0xaa064b07, 0x4669447b, 0x98059000, 0xfbd7f000, 0x46692000, 0xfbe6f000, 0xf85dbc1c, 
+    0x0000fb14, 0x000007dd, 0x41f0e92d, 0x4604460e, 0x62202000, 0x68e14620, 0xb3304788, 0xd0052825, 
+    0x2101e9d4, 0x6a204790, 0xe7f21c40, 0x462068e1, 0x47882700, 0xd0180005, 0x0041f1a5, 0xd8022819, 
+    0xf44f3520, 0x46326700, 0x46204629, 0xf7d46027, 0xb140f86f, 0xd0042801, 0xf0261df6, 0x36080607, 
+    0x1d36e7d8, 0x4628e7d6, 0x6a20e7da, 0x81f0e8bd, 0x460cb570, 0x2a014605, 0x7828d005, 0xd5000680, 
+    0x230069ea, 0x2301e002, 0x1c5be005, 0xd2024293, 0x28005ce0, 0x69a8d1f9, 0x1ac018e6, 0x6a2861a8, 
+    0x62284418, 0xf3af4628, 0xe0048000, 0x2101e9d5, 0x0b01f814, 0x42b44790, 0x4628d3f8, 0x8000f3af, 
+    0x0000bd70, 0x41f0e92d, 0x25004680, 0x29756810, 0xa6144641, 0xf3afd011, 0x28008000, 0x4240da02, 
+    0xe008a611, 0x1000f8d8, 0xd501078a, 0xe002a60f, 0xd5040749, 0x2501a60e, 0xf3afe001, 0x24008000, 
+    0x0724f108, 0xf000e004, 0x3130eb9e, 0x1c645539, 0xd1f82800, 0x4632462b, 0x46404621, 0x41f0e8bd, 
+    0xbae1f000, 0x00000000, 0x0000002d, 0x0000002b, 0x00000020, 0xb510490b, 0x027cf1a1, 0xe9c24c0a, 
+    0x21371237, 0xeb00e006, 0xf8424310, 0x4b073021, 0x4003fb00, 0xf1a11e0b, 0xdcf40101, 0x2001bd10, 
+    0x0000e7e8, 0x0004cf24, 0x66d619e1, 0x00010dcd, 0xe2402001, 0xe5f23001, 0xe3530000, 0x1afffffc, 
+    0xe4d13001, 0xe3530000, 0xe4c23001, 0x1afffffb, 0xe12fff1e, 0xe3520003, 0x9a000017, 0xe210c003, 
+    0x0a000008, 0xe4d13001, 0xe35c0002, 0xe082200c, 0x94d1c001, 0xe4c03001, 0x34d13001, 0x94c0c001, 
+    0xe2422004, 0x34c03001, 0xe2113003, 0x0a000012, 0xe2522008, 0x3a000004, 0xe4913004, 0xe2522008, 
+    0xe491c004, 0xe8a01008, 0xeafffff9, 0xe2922004, 0x54913004, 0x54803004, 0xe1a00000, 0xe1b02f82, 
+    0x24d13001, 0x24d1c001, 0x44d12001, 0x24c03001, 0x24c0c001, 0x44c02001, 0xe12fff1e, 0xe92d4010, 
+    0xe2522020, 0x3a000005, 0xe8b15018, 0xe2522020, 0xe8a05018, 0xe8b15018, 0xe8a05018, 0x2afffff9, 
+    0xe1b0ce02, 0x28b15018, 0x28a05018, 0x48b10018, 0x48a00018, 0xe8bd4010, 0xe1b0cf02, 0x24913004, 
+    0x24803004, 0x012fff1e, 0xe1b02f82, 0x20d130b2, 0x44d12001, 0x20c030b2, 0x44c02001, 0xe12fff1e, 
+    0x03fff002, 0x2203ea43, 0x4202ea42, 0xbab9f000, 0xe3100003, 0xe92d4010, 0xe1a04000, 0x03110003, 
+    0x1a00000a, 0xe59fe04c, 0xe2522004, 0xba000006, 0xe4913004, 0xe043c00e, 0xe1ccc003, 0xe01cc38e, 
+    0x04803004, 0x0afffff7, 0xe2411004, 0xe2822004, 0xe2522001, 0xba000005, 0xe4d13001, 0xe3530000, 
+    0xe4c03001, 0x1afffff9, 0xe1a01002, 0xfb000142, 0xe1a00004, 0xe8bd8010, 0x01010101, 0x47704800, 
+    0x0004cf94, 0x47704770, 0x47704770, 0x4604b538, 0x2000460a, 0xf0004669, 0x2800fb04, 0x4602d005, 
+    0x99004620, 0xfaacf000, 0xbd382001, 0xf0002001, 0xb5f8babf, 0xfaeaf000, 0x20004605, 0x2010460c, 
+    0x4606bf00, 0x42a019a8, 0x4632d90d, 0x20004669, 0xfae7f000, 0xbf080007, 0xfaaaf000, 0x42a09800, 
+    0x4605bf18, 0xf7ff19c4, 0x6005ffc9, 0x1df04607, 0x0007f020, 0x46281946, 0xf80af000, 0xd00642b4, 
+    0x68384631, 0xe8bd1ba2, 0xf00040f8, 0xbdf8ba79, 0x60012100, 0x1001e9c0, 0x20104770, 0x00004770, 
+    0xe92d4070, 0xe1a04003, 0xe1a05002, 0xe1a03001, 0xe1a02000, 0xe3540000, 0x11a0c004, 0x01a0c005, 
+    0xe16fef1c, 0xe28e0001, 0xe1a0c01c, 0x127ee03f, 0x027ee01f, 0x4a000094, 0xe3530000, 0x116f1f13, 
+    0x016f1f12, 0x1271103f, 0x0271101f, 0xe051600e, 0x4a000092, 0x52760004, 0x5a000093, 0xe24e0020, 
+    0xe3500004, 0xd1a01035, 0xd18cc001, 0xe28f1f9f, 0xe1a0ce2c, 0xe35e001f, 0xe791c10c, 0x824ee020, 
+    0xe26e6020, 0x8a000048, 0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 
+    0xe2611000, 0x32411001, 0xe081019c, 0xe08cc001, 0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 
+    0xe1811004, 0xe2700000, 0xe2611000, 0x32411001, 0xe3530000, 0xe081019c, 0xe08cc001, 0x0a000009, 
+    0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 0xe2611000, 0x32411001, 
+    0xe081019c, 0xe08cc001, 0xe080129c, 0xe3a01000, 0xe0a1039c, 0xe1a00e30, 0xe1a04611, 0xe1800004, 
+    0xe1a01e31, 0xe0846590, 0xe0522006, 0xe0244591, 0xe0c33004, 0xe3530001, 0x31520005, 0x38bd8070, 
+    0xe086429c, 0xe3a04000, 0xe0a4639c, 0xe26ec020, 0xe1a06e36, 0xe1a03c14, 0xe1866003, 0xe3a03000, 
+    0xe1a04e34, 0xe08ce596, 0xe0900006, 0xe0a11004, 0xe042200e, 0xe1520005, 0x38bd8070, 0xe2900001, 
+    0xe2a11000, 0xe0422005, 0xe052c005, 0x21a0200c, 0xe2b00000, 0xe2a11000, 0xe052c005, 0x21a0200c, 
+    0xe2b00000, 0xe2a11000, 0xe8bd8070, 0xe080159c, 0xe3a01000, 0xe0a1049c, 0xe1a01611, 0xe1a06e30, 
+    0xe1811006, 0xe26e6020, 0xe2611000, 0xe1a00610, 0xe2700000, 0x32411001, 0xe081019c, 0xe08cc001, 
+    0xe080159c, 0xe3a01000, 0xe0a1049c, 0xe1a01611, 0xe1a06e30, 0xe1811006, 0xe26e6020, 0xe2611000, 
+    0xe1a00610, 0xe2700000, 0x32411001, 0xe081019c, 0xe08cc001, 0xe24cc001, 0xe080129c, 0xe3a01000, 
+    0xe0a1039c, 0xe1a00e31, 0xe0816590, 0xe0522006, 0xe0211490, 0xe0c33001, 0xe1530004, 0x01520005, 
+    0x33a01000, 0x38bd8070, 0xe081629c, 0xe3a06000, 0xe0a6139c, 0xe3a01000, 0xe1a06e36, 0xe08ce596, 
+    0xe0800006, 0xe052200e, 0xe02ec496, 0xe0c3300e, 0xe1530004, 0x01520005, 0x38bd8070, 0xe2800001, 
+    0xe0522005, 0xe0c33004, 0xe8bd8070, 0xe92d000c, 0xe3a01000, 0xe3a00000, 0xe1a00000, 0xe8bd807c, 
+    0xe3a01000, 0xe3a00000, 0xe8bd8070, 0xe266e020, 0xe3a00000, 0xe3a01000, 0xe1a04614, 0xe1a0ce35, 
+    0xe1a05615, 0xe184400c, 0xe052e005, 0xe0d3c004, 0xe0a00000, 0x21a0300c, 0x21a0200e, 0xe2566001, 
+    0x38bd8070, 0xe1b040a4, 0xe1a05065, 0xeafffff5, 0xf0f0f0f0, 0xe38e38e3, 0xd79435e5, 0xcccccccc, 
+    0xc30c30c3, 0xba2e8ba2, 0xb21642c8, 0xaaaaaaaa, 0xa3d70a3d, 0x9d89d89d, 0x97b425ed, 0x92492492, 
+    0x8d3dcb08, 0x88888888, 0x84210842, 0x80000000, 0xf000b510, 0x6800f8d1, 0xb510bd10, 0xf0004604, 
+    0x6004f8cb, 0xe92dbd10, 0x460d47f0, 0x46924699, 0xf1004604, 0x68010824, 0xd5040688, 0xf02169e0, 
+    0x60210110, 0x2001e000, 0xdd0142a8, 0xe0001b47, 0x69a12700, 0xeb02197a, 0x1a080009, 0x782061a0, 
+    0xd40206c0, 0xf3af4620, 0x26008000, 0xe9d4e008, 0xf81a2101, 0x47900006, 0x1c406a20, 0x62201c76, 
+    0xdbf4454e, 0x06c07820, 0x4620d50a, 0x8000f3af, 0xe9d4e006, 0x20302101, 0x6a204790, 0x62201c40, 
+    0xf1a71e38, 0xdcf40701, 0xe9d4e007, 0xf8182101, 0x47900005, 0x1c406a20, 0x1e286220, 0x0501f1a5, 
+    0x4620dcf3, 0x8000f3af, 0x06007820, 0x2002d502, 0x87f0e8bd, 0xe7fb2001, 0x1c4a6901, 0x78086102, 
+    0xb5004770, 0xe9cdb08f, 0x21003101, 0x49059105, 0xe9cd4479, 0x46111003, 0xf7ff4668, 0xb00ffc25, 
+    0x0000bd00, 0xffffffe5, 0xf802680a, 0x600a0b01, 0xb5104770, 0xb1136943, 0x8000f3af, 0xf7ffe001, 
+    0x2001fc47, 0x7812bd10, 0x0124f100, 0x2200700a, 0x2201704a, 0x6811e7ed, 0x32fff04f, 0xf04fe7e9, 
+    0x29040200, 0x8012f0c0, 0x0c03f010, 0x8059f000, 0x0c04f1cc, 0x0f02f1bc, 0xf800bf18, 0xbfa82b01, 
+    0x2b02f820, 0x010ceba1, 0xb84bf000, 0x7cc1ea5f, 0xf800bf24, 0xf8002b01, 0xbf482b01, 0x2b01f800, 
+    0x00004770, 0xe240100a, 0xe0400120, 0xe0800220, 0xe0800420, 0xe0800820, 0xe1a001a0, 0xe0802100, 
+    0xe0511082, 0x52800001, 0x4281100a, 0xe12fff1e, 0x47704800, 0x0004cf8c, 0x47704800, 0x0004cf8c, 
+    0x6843468c, 0xbf182b00, 0xbf38428b, 0xd3f84618, 0x44186803, 0xd0074288, 0x0003f10c, 0x0007f020, 
+    0x1a411d00, 0x46011a52, 0x600a1d08, 0xbb2df7ff, 0xf000b510, 0xe8bdf885, 0xf0004010, 0xf04fb87b, 
+    0xb5000200, 0x46944613, 0x39204696, 0xe8a0bf22, 0xe8a0500c, 0xf1b1500c, 0xf4bf0120, 0x0709aff7, 
+    0xe8a0bf28, 0xbf48500c, 0xf85dc00c, 0x0089eb04, 0xf840bf28, 0xbf082b04, 0xbf484770, 0x2b02f820, 
+    0x4f80f011, 0xf800bf18, 0x47702b01, 0x46694b12, 0x5280f500, 0x601a428a, 0x4611d801, 0x60194770, 
+    0xb5304770, 0x466b4d0c, 0x5380f5a3, 0x4422682c, 0xd80f429a, 0xf5021a9b, 0xeb035080, 0xeb0273d3, 
+    0x42980363, 0x4618d900, 0xf0201dc0, 0x600c0207, 0x602a1b10, 0x0000bd30, 0x00038e88, 0x46754770, 
+    0xff86f7ff, 0x000546ae, 0x46534669, 0x0007f020, 0xb0184685, 0xf001b520, 0xe8bde9ba, 0xf04f4020, 
+    0xf04f0600, 0xf04f0700, 0xf04f0800, 0xf0210b00, 0x46ac0107, 0x09c0e8ac, 0x09c0e8ac, 0x09c0e8ac, 
+    0x09c0e8ac, 0x4770468d, 0xf3af4604, 0x46208000, 0xfbdcf7d3, 0xd0012800, 0xb82af000, 0x00004770, 
+    0x2801b510, 0x2100d005, 0xf000a003, 0x2001f827, 0xa109bd10, 0x0000e7f8, 0x52474953, 0x4d454d54, 
+    0x754f203a, 0x666f2074, 0x61656820, 0x656d2070, 0x79726f6d, 0x00000000, 0x6548203a, 0x6d207061, 
+    0x726f6d65, 0x6f632079, 0x70757272, 0x00646574, 0x20184901, 0xe7fedfab, 0x00020026, 0x4605b570, 
+    0x200a460c, 0x1c6de000, 0xf811f000, 0x7828b135, 0xd1f82800, 0x1c64e002, 0xf809f000, 0x7820b114, 
+    0xd1f82800, 0x4070e8bd, 0xf3af200a, 0xb5088000, 0xf88d4669, 0x20030000, 0xbd08dfab, 0xe92d0003, 
+    0xe59f0050, 0xe580e000, 0xe59f004c, 0xe5901000, 0xe3510000, 0x1a000001, 0xe59f1040, 0xe5801000, 
+    0xe2811001, 0xe5801000, 0xe59f0034, 0xee151f10, 0xe5801000, 0xe59f002c, 0xee161f10, 0xe5801000, 
+    0xe59f0024, 0xee151f11, 0xe5801000, 0xe8bd0003, 0xe25ef008, 0xe320f000, 0xc300000c, 0xc3000010, 
+    0xdead0000, 0xc3000020, 0xc3000024, 0xc3000028, 0x5ffce92d, 0x0000f04f, 0xf8114918, 0xf04f2b01, 
+    0x429a03bb, 0xf811d128, 0xf04f2b01, 0x429a03a7, 0xf811d122, 0x42822b01, 0xf811d11e, 0x42822b01, 
+    0x480fd11a, 0x0a00f04f, 0x0200f04f, 0xea845c8c, 0xf005050a, 0xf83006ff, 0xea4f5016, 0xea85261a, 
+    0xf1020a06, 0x2a0a0201, 0x5a8cdbf0, 0x0001f04f, 0xd0014554, 0x0000f04f, 0x9ffce8bd, 0x00038fd0, 
+    0x00000300, 0xe92d500f, 0xe14fc000, 0xe92d1000, 0xe59f0024, 0xe5d01000, 0xe1a01201, 0xe59f201c, 
+    0xe0822001, 0xe5920000, 0xe8bd1000, 0xe16ff00c, 0xe8bd500f, 0xe25ef004, 0xe320f000, 0xc1000014, 
+    0xc1000104, 0x5ff0e92d, 0x90d0f8df, 0x0a52ea4f, 0x0b92ea4f, 0xf823880c, 0x88044b02, 0x4b02f823, 
+    0x401bf831, 0x4b02f823, 0x401bf830, 0x4b02f823, 0x0701f04f, 0x5007f819, 0x4015f831, 0x4b02f823, 
+    0x4015f830, 0x4b02f823, 0x0505ebaa, 0x4015f831, 0x0400f1c4, 0x4b02f823, 0x4015f830, 0x4b02f823, 
+    0x0701f107, 0xf6ff455f, 0xe8bdafe5, 0xe92d9ff0, 0xf8df5ff0, 0xea4f9068, 0xea4f0a51, 0xf04f0b91, 
+    0xf9300700, 0x801c4b02, 0x4b02f930, 0xf1078014, 0xf9300701, 0xf8234b02, 0xf930401b, 0xf8226b02, 
+    0xf819601b, 0xf9305007, 0xf8234b02, 0xf9304015, 0xf8226b02, 0xebaa6015, 0xf9300505, 0xf1c44b02, 
+    0xf8230400, 0xf9304015, 0xf8226b02, 0xf1076015, 0x455f0701, 0xafe5f6ff, 0x9ff0e8bd, 0x000308d0, 
+    0x5ff0e92d, 0x0a00f04f, 0x4694468b, 0x1000f990, 0x2001f990, 0x0302eb01, 0x5002f990, 0x6003f990, 
+    0x0706eb05, 0x0806eba5, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 
+    0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0402eba1, 0x0706eb05, 0x0806eba5, 0x0907eb04, 
+    0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 
+    0x9b04f84c, 0x0301eba2, 0x0706eb05, 0x0806eba5, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 
+    0x0800f1c7, 0x0705eba6, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0302eb01, 0x0400f1c3, 
+    0x0706eb05, 0x0806eba5, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 
+    0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0004f100, 0x0a01f10a, 0xf6ff45da, 0xe8bdaf87, 
+    0x00009ff0, 0xe92d500f, 0xe14fc000, 0xe92d1000, 0xe59f0024, 0xe5d01000, 0xe1a01201, 0xe59f201c, 
+    0xe0822001, 0xe5920000, 0xe8bd1000, 0xe16ff00c, 0xe8bd500f, 0xe25ef004, 0xe320f000, 0xc100000c, 
+    0xc1000104, 0x5ffce92d, 0x0300f04f, 0x4023f850, 0x4023f841, 0x0301f103, 0xf6ff4293, 0xe8bdaff7, 
+    0xe92d9ffc, 0xf04f5ffc, 0x2b000500, 0xf1c3da02, 0xe00b0300, 0x4025f850, 0xf403fa04, 0x4025f841, 
+    0x0501f105, 0xf6ff4295, 0xe00aaff5, 0x4025f850, 0xf403fa44, 0x4025f841, 0x0501f105, 0xf6ff4295, 
+    0xe8bdaff5, 0xe92d9ffc, 0xf04f5ffc, 0xf8300300, 0xf8214013, 0xf1034013, 0x42930301, 0xaff7f6ff, 
+    0x9ffce8bd, 0x5ffce92d, 0x0300f04f, 0x4013f930, 0x4023f841, 0x0301f103, 0xf6ff4293, 0xe8bdaff7, 
+    0xe92d9ffc, 0xf04f5ff0, 0xf9300500, 0xfa044b02, 0xf841f403, 0xf1054b04, 0x42950501, 0xaff5f6ff, 
+    0x9ff0e8bd, 0x5ffce92d, 0x0701f1a3, 0x0601f04f, 0xf607fa06, 0x0500f04f, 0x4025f850, 0xfa444434, 
+    0xf821f403, 0xf1054015, 0x42950501, 0xaff4f6ff, 0x9ffce8bd, 0xe92d5ffc, 0xeafffffe, 0xe8bd9ffc, 
+    0xe59f1150, 0xe5910000, 0xe590e000, 0xe59f0148, 0xe8be0002, 0xe5801000, 0xe8be0001, 0xe16ff000, 
+    0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 0xef000000, 0xe12fff1e, 0xe28ee004, 0xe92d0001, 
+    0xe94d2000, 0xe320f000, 0xe24dd004, 0xe8bd0001, 0xe9204000, 0xe1a0e000, 0xe8bd0001, 0xe94e7fff, 
+    0xe320f000, 0xe24ee03c, 0xe14f0000, 0xe92e0001, 0xe59f00e4, 0xe5900000, 0xe92e0001, 0xe59f10d4, 
+    0xe5910000, 0xe580e000, 0xe59f00d0, 0xe1a0e00f, 0xe12fff10, 0xe59f10bc, 0xe5910000, 0xe590e000, 
+    0xe59f00b4, 0xe8be0002, 0xe5801000, 0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 
+    0xe25ef004, 0xe92d0001, 0xe94d2000, 0xe320f000, 0xe24dd004, 0xe8bd0001, 0xe9204000, 0xe1a0e000, 
+    0xe8bd0001, 0xe94e7fff, 0xe320f000, 0xe24ee03c, 0xe14f0000, 0xe92e0001, 0xe59f005c, 0xe5900000, 
+    0xe92e0001, 0xe59f104c, 0xe5910000, 0xe580e000, 0xe59f004c, 0xe1a0e00f, 0xe12fff10, 0xe59f003c, 
+    0xe1a0e00f, 0xe12fff10, 0xe59f1028, 0xe5910000, 0xe590e000, 0xe59f0020, 0xe8be0002, 0xe5801000, 
+    0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 0x00038e08, 0x00038e54, 
+    0x00028245, 0x00027f39, 0xe92d0003, 0xe59f0034, 0xe59f1034, 0xe5801000, 0xe59f0030, 0xee151f31, 
+    0xe5801000, 0xe59f0028, 0xee151f30, 0xe5801000, 0xe59f0020, 0xee161f50, 0xe5801000, 0xe8bd0003, 
+    0xe25ef004, 0xe320f000, 0xc3000010, 0xfec0dead, 0xc300002c, 0xc3000030, 0xc3000034, 0x5ffce92d, 
+    0xf1a59d0d, 0xf04f0c05, 0xfa0b0b01, 0xea4ffa05, 0xb40c0a9a, 0x9a10b403, 0xf1009800, 0xf04f0104, 
+    0xf84d0e00, 0xf04fcd04, 0xb4040900, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 
+    0x0505eba3, 0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 
+    0xfb360600, 0xf8414413, 0xf840c03a, 0xeb02403a, 0xf84002cb, 0xf8417b08, 0xf1098b08, 0x45d10901, 
+    0xafd4f6ff, 0x00caeb00, 0x01caeb01, 0xf10ebc04, 0x45de0e01, 0xafc7f6ff, 0x0b4bea4f, 0x0a5aea4f, 
+    0xcb04f85d, 0x0c01f1ac, 0x0f00f1bc, 0x9800dcb4, 0x0104f100, 0x0e00f04f, 0x2982f645, 0x6803b404, 
+    0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 0xf8400606, 0xf841503a, 
+    0xf840603a, 0xf8417b08, 0xeb028b08, 0x680302cb, 0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 
+    0xeba30806, 0xeba40505, 0x68130606, 0x0545ea4f, 0x0646ea4f, 0xfc13fb35, 0xf403fb35, 0xcc03fb36, 
+    0x0600f1c6, 0x4413fb36, 0xc03af841, 0x403af840, 0x120beb02, 0x7b08f840, 0x8b08f841, 0xf8506803, 
+    0x680c503a, 0x603af851, 0x0705eba3, 0x0806eba4, 0x4426441d, 0x0307eb08, 0x0807eba8, 0x0343ea4f, 
+    0x0848ea4f, 0xf309fb33, 0xf809fb38, 0x303af840, 0x803af841, 0x5b08f840, 0x6b08f841, 0xf8506803, 
+    0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 0x0606eba4, 0xea4f6813, 0xea4f0545, 
+    0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 0xf8414413, 0xf840c03a, 0xeb02403a, 
+    0xf840120b, 0xf8417b08, 0x68038b08, 0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba50806, 
+    0xeba40503, 0xf8410606, 0xf840503a, 0xf840603a, 0xf8417b08, 0x68038b08, 0x503af850, 0xf851680c, 
+    0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 0x68130606, 0x0545ea4f, 0x0646ea4f, 0xfc13fb35, 
+    0xf403fb35, 0xcc03fb36, 0x0600f1c6, 0x4413fb36, 0xc03af841, 0x403af840, 0x120beb02, 0x7b08f840, 
+    0x8b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0806eba4, 0x4426441d, 0x0307eb08, 
+    0x0807eba8, 0x0343ea4f, 0x0848ea4f, 0xf309fb33, 0xf809fb38, 0x0300f1c3, 0x803af840, 0x303af841, 
+    0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 
+    0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 
+    0xf8414413, 0xf840c03a, 0xeb02403a, 0xf84002cb, 0xf8417b08, 0xeb008b08, 0xeb0100ca, 0xbc0401ca, 
+    0x0e01f10e, 0xf6ff45de, 0xea4faee9, 0xea4f0b4b, 0x98000a5a, 0x0104f100, 0x0800f04f, 0x2982f645, 
+    0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0206eb04, 0x0505eba3, 0x0606eba4, 0x503af840, 
+    0x603af841, 0x7b08f840, 0x2b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0206eba4, 
+    0x4426441d, 0x0307eb02, 0x0207eba2, 0x0343ea4f, 0x0242ea4f, 0xf309fb33, 0xf209fb32, 0x303af840, 
+    0x203af841, 0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0206eb04, 
+    0x0503eba5, 0x0606eba4, 0x503af841, 0x603af840, 0x7b08f840, 0x2b08f841, 0xf8506803, 0x680c503a, 
+    0x603af851, 0x0705eba3, 0x0206eba4, 0x4426441d, 0x0307eb02, 0x0207eba2, 0x0343ea4f, 0x0242ea4f, 
+    0xf309fb33, 0xf209fb32, 0x0300f1c3, 0x203af840, 0x303af841, 0x5b08f840, 0x6b08f841, 0x00caeb00, 
+    0x01caeb01, 0x0801f108, 0xf6ff45d8, 0xea4faf89, 0x98000b4b, 0x0104f100, 0x0800f04f, 0x2b08f850, 
+    0x3b08f850, 0x4b08f850, 0xf8516805, 0xf8516b08, 0xf8517b08, 0xf8d19b08, 0xeb02a000, 0xeba20c04, 
+    0xeb060204, 0xeba60409, 0xeb030609, 0xeba30905, 0xeb070305, 0xeba7050a, 0xeb0c070a, 0xebac0a09, 
+    0xeb040c09, 0xeba40905, 0xeb020405, 0xeba20507, 0xeb060207, 0xeba60703, 0xf8400603, 0xf8402908, 
+    0xf8405908, 0xf840c908, 0xf841ab20, 0xf8417908, 0xf8416908, 0xf8414908, 0xf1089b20, 0x45d80801, 
+    0xafbcf6ff, 0x058bea4f, 0xf985fab5, 0x091ef1c9, 0x0c1ff1c9, 0x0b59ea4f, 0x0b01f10b, 0x0901f009, 
+    0xbc0344cb, 0xf850bc0c, 0xf8509b04, 0xf850ab04, 0xf8504b04, 0xeb09790c, 0xeba9060a, 0xf04f090a, 
+    0xfa460800, 0xfa49f60b, 0xfa44f90b, 0xfa47f40b, 0x6016f70b, 0x8000f8c3, 0x9025f842, 0x8025f843, 
+    0x0655ea4f, 0xf842442e, 0xf8434026, 0xf1c77026, 0xf8420700, 0xf8434015, 0xf8dd7015, 0xf04fe030, 
+    0xb4200402, 0x6034f850, 0x0004f100, 0x7034f850, 0x0004f100, 0xf90cfa04, 0xf9a9fa99, 0x0109eba5, 
+    0xf1a1fa91, 0xf10cfa21, 0x01fef001, 0x8031f850, 0x0004f100, 0x1031f850, 0x000cf1a0, 0x0a08eb06, 
+    0x0608eba6, 0x0801eb07, 0x0701eba7, 0x1029f85e, 0x0767ea4f, 0xf511fb36, 0x0600f1c6, 0x5501fb38, 
+    0xf601fb36, 0x0a6aea4f, 0x6611fb38, 0x0105eb0a, 0x0a05ebaa, 0x0806eb07, 0x0706eba7, 0xf10bfa41, 
+    0xf80bfa48, 0xfa0bfa4a, 0xf70bfa47, 0x1029f842, 0x8029f843, 0xeb09bc20, 0xf8420605, 0xf843a026, 
+    0xeba57026, 0xf1c70609, 0xf8420700, 0xf843a026, 0x442e7026, 0x0800f1c8, 0x1026f842, 0x8026f843, 
+    0x0402f104, 0xdb9c42ac, 0x5ffce8bd, 0x00004770, 0x5ffce92d, 0xf04f9e0d, 0xfa0b0b01, 0xea4ff506, 
+    0xf1a60555, 0xf1c90902, 0x68060c1f, 0x9025f850, 0x4015f850, 0x7015f851, 0x0700f1c7, 0x0a09eba6, 
+    0xea4f44b1, 0xea4f0a6a, 0xf8420969, 0xf8429b04, 0xf842ab04, 0xf8424b04, 0xf8dd790c, 0xf04fe030, 
+    0xfa040402, 0xfa99f90c, 0xf850f9a9, 0xf8513029, 0xeba58029, 0xf8500609, 0xf851a026, 0xeb037026, 
+    0xeba3060a, 0xeba8030a, 0x44b80a07, 0x7029f85e, 0x0a6aea4f, 0xfb07fb33, 0xf317fb33, 0xbb17fb38, 
+    0x0800f1c8, 0x0666ea4f, 0x3307fb38, 0x0806eb03, 0x0303eba6, 0x060aeb0b, 0x0b0aebab, 0x8034f842, 
+    0x0204f102, 0x6034f842, 0x0204f102, 0x0809eba5, 0xf8a8fa98, 0xf80cfa28, 0x08fef008, 0x3038f842, 
+    0x0204f102, 0xb038f842, 0x020cf1a2, 0x0402f104, 0xdbb642ac, 0xf1a59d0d, 0xf04f0c01, 0xfa0a0a01, 
+    0xea4ffb05, 0xb4040b9b, 0x98009a0d, 0x0e00f04f, 0x0b5bea4f, 0xcd04f84d, 0x1b08f850, 0x3b08f850, 
+    0x4b08f850, 0x5914f850, 0x6b08f850, 0x7b08f850, 0x8b08f850, 0x9904f850, 0x0c03eb01, 0x0103eba1, 
+    0x0307eb06, 0x0607eba6, 0x0705eb04, 0x0405eba4, 0x0509eb08, 0x0809eba8, 0x0907eb0c, 0x0c07ebac, 
+    0x0705eb03, 0x0305eba3, 0x0508eb01, 0x0108eba1, 0x0804eb06, 0x0604eba6, 0x5908f840, 0xc908f840, 
+    0x1908f840, 0x9b1cf840, 0x6908f840, 0x3908f840, 0x8908f840, 0x7b1cf840, 0x0e01f10e, 0xf6ff45de, 
+    0xf85dafbb, 0xea4fcb04, 0xea4f0b5b, 0xf1ac0a8a, 0x98000c02, 0x0104f100, 0x0e00f04f, 0x2982f645, 
+    0xf8506803, 0x680c503a, 0x603af851, 0x0805eb03, 0x0305eba3, 0x0506eb04, 0x0406eba4, 0x303af840, 
+    0x403af841, 0x8b08f840, 0x5b08f841, 0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0x680c6803, 
+    0x0806eba5, 0xfb384435, 0xfb35f809, 0xeb03f509, 0xeba30608, 0xeb040308, 0xeba40805, 0xf8400405, 
+    0xf841303a, 0xf840403a, 0xf8416b08, 0x680c8b08, 0x603af851, 0xf8506803, 0xeba3503a, 0x44330806, 
+    0x0605eb04, 0x0405eba4, 0x303af840, 0x403af841, 0x8b08f840, 0x6b08f841, 0x503af850, 0x603af851, 
+    0x0545ea4f, 0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 0x0506eba5, 0xf809fb38, 0xf509fb35, 
+    0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 
+    0x00caeb00, 0x01caeb01, 0x0e01f10e, 0xf6ff45de, 0xea4faf87, 0xea4f0b5b, 0xf1ac0a4a, 0x98000c01, 
+    0x0104f100, 0x0e00f04f, 0x6803b404, 0x503af850, 0xf851680c, 0xeb03603a, 0xeba30805, 0xeb040305, 
+    0xeba40506, 0xea4f0406, 0xea4f03e3, 0xea4f04e4, 0xea4f08e8, 0xf84005e5, 0xf841303a, 0xf840403a, 
+    0xf8418b08, 0xeb025b08, 0x680302cb, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 
+    0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 
+    0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 
+    0x8b08f841, 0x02cbeb02, 0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0x680c6803, 0x0806eba5, 
+    0xfb384435, 0xfb35f809, 0xeb03f509, 0xeba30608, 0xeb040308, 0xeba40805, 0xea4f0405, 0xea4f03e3, 
+    0xea4f04e4, 0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8416b08, 0xeb028b08, 0x680302cb, 
+    0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 
+    0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 
+    0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0xf851680c, 
+    0x6803603a, 0x503af850, 0x0806eba3, 0xeb044433, 0xeba40605, 0xea4f0405, 0xea4f03e3, 0xea4f04e4, 
+    0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8418b08, 0xeb026b08, 0x680302cb, 0x503af850, 
+    0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 
+    0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 
+    0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0x503af850, 0x603af851, 
+    0x0545ea4f, 0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 0x0506eba5, 0xf809fb38, 0xf509fb35, 
+    0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 
+    0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0xf8506803, 0x680c503a, 0x603af851, 
+    0x0545ea4f, 0xea4f6817, 0xfb350646, 0xf1c5f807, 0xfb350500, 0xfb36f517, 0xfb368817, 0xeb035507, 
+    0xeba30608, 0xeb040308, 0xeba40805, 0xea4f0405, 0xea4f03e3, 0xea4f04e4, 0xea4f06e6, 0xf84008e8, 
+    0xf841303a, 0xf840403a, 0xf8416b08, 0xeb028b08, 0xeb0002cb, 0xeb0100ca, 0xbc0401ca, 0x0e01f10e, 
+    0xf6ff45de, 0xea4faea1, 0xea4f0b5b, 0xf1ac0a4a, 0x98000c01, 0x0104f100, 0x0e00f04f, 0x0900f04f, 
+    0x6803b404, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 
+    0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x303af840, 
+    0x403af841, 0x02cbeb02, 0x6b08f840, 0x8b08f841, 0x0901f109, 0xf6ff45d1, 0xeb00afd4, 0xeb0100ca, 
+    0xbc0401ca, 0x0e01f10e, 0xf6ff45de, 0xea4fafc7, 0xea4f0b5b, 0xf1ac0a4a, 0xf1bc0c01, 0xdcb80f00, 
+    0xe8bdbc04, 0x47705ffc, 0x5ffce92d, 0xf0f1fb90, 0x9ffce8bd, 0xe92d4001, 0xe14f0000, 0xe3100020, 
+    0x115e00b2, 0x13c00cff, 0x051e0004, 0x03c004ff, 0xe35000fe, 0x0a000007, 0xe35000ff, 0x0a000009, 
+    0xe3500000, 0x0a000001, 0xe8bd4001, 0xe1b0f00e, 0xe8bd4001, 0xeafffc8f, 0xe14f0000, 0xe38000c0, 
+    0xe16ff000, 0xea000003, 0xe14f0000, 0xe3c000c0, 0xe16ff000, 0xeaffffff, 0xe8bd4001, 0xe1b0f00e, 
+    0x5ffce92d, 0x0400f04f, 0x5024f851, 0xf6f5fbb0, 0x6024f842, 0x0401f104, 0xf6ff429c, 0xe8bdaff5, 
+    0x00009ffc, 0x0004cfec, 0x0004e5ec, 0xe51f0010, 0xe12fff1e, 0xe92d0003, 0xe59f0010, 0xe59f1010, 
+    0xe5801000, 0xe8bd0003, 0xe25ef004, 0xe320f000, 0xc3000010, 0xdef0dead, 0x5ff0e92d, 0x0200f04f, 
+    0x0300f04f, 0x3022f840, 0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0x00009ff0, 0x5ff0e92d, 0x0200f04f, 
+    0x0300f04f, 0x3012f820, 0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0xe92d9ff0, 0x460441f0, 0x461e4615, 
+    0xf0371e4f, 0xeb000206, 0xe9d101c7, 0xd00d0100, 0x4633462a, 0xfe22f000, 0xeb041e7f, 0xe9d303c7, 
+    0xf0002300, 0xf037fb07, 0xd1f10206, 0xd0232f02, 0xd0112f04, 0xd1312f06, 0x4633462a, 0xfe0ef000, 
+    0x230ae9d4, 0xfaf6f000, 0x4633462a, 0xfe06f000, 0x2308e9d4, 0xfaeef000, 0x4633462a, 0xfdfef000, 
+    0x2306e9d4, 0xfae6f000, 0x4633462a, 0xfdf6f000, 0x2304e9d4, 0xfadef000, 0x4633462a, 0xfdeef000, 
+    0x2302e9d4, 0xfad6f000, 0x4633462a, 0xfde6f000, 0x2300e9d4, 0x41f0e8bd, 0xbaccf000, 0x81f0e8bd, 
+    0x22004902, 0x46104613, 0xbb80f000, 0x3ff00000, 0xf0012201, 0x2200bb28, 0x46104613, 0xf0004611, 
+    0x0000bb75, 0x41f0e92d, 0x4604460d, 0x5c0af3c1, 0x4b2d4a2c, 0x36fff2ac, 0xda2d2e14, 0xda122e00, 
+    0xfaa8f000, 0x46132200, 0xfeb6f000, 0x2d00d245, 0xf04fbfbc, 0x24004500, 0xea55db3f, 0xbf180004, 
+    0xd1174d22, 0xf8dfe039, 0xfa2cc088, 0xea05f706, 0xea5c0c07, 0xd0320c04, 0xfa8cf000, 0x46132200, 
+    0xfe9af000, 0x2d00d229, 0xf44fdd03, 0x40f01080, 0x43bd4405, 0xe0202400, 0xdc202e33, 0x3cfff04f, 
+    0x0714f1a6, 0xf707fa2c, 0xd018423c, 0xfebaf000, 0x46132200, 0xfe80f000, 0x2d00d20f, 0x2e14dd0c, 
+    0x1c6dbf08, 0xf1c6d008, 0x20010134, 0x44204088, 0xbf3842a0, 0x46041c6d, 0x462943bc, 0xe8bd4620, 
+    0x000081f0, 0x8800759c, 0x7e37e43c, 0x3ff00000, 0x000fffff, 0x4df0e92d, 0xb0902400, 0x42914ac7, 
+    0xf021da05, 0x42934300, 0xd105d801, 0xb010b120, 0x4df0e8bd, 0xbf7cf7ff, 0x1f80f5b1, 0xea53da1b, 
+    0xd0090200, 0xda112900, 0xf7fe2001, 0xb010fbd6, 0x4df0e8bd, 0xbf6ff7ff, 0xf7fe2002, 0xf7fffbce, 
+    0xf081ff5f, 0xb0104100, 0x8df0e8bd, 0xf06f2236, 0xf0010435, 0xf3c1fa88, 0xeb040a13, 0x49b05221, 
+    0x32fff2a2, 0xf4014451, 0xf0811180, 0xeb02637f, 0xf0835821, 0xea435340, 0x4baa010a, 0xf0002200, 
+    0xf10afe5d, 0x4ea80202, 0x0213f3c2, 0x447e2a03, 0x460d4604, 0xe9d6d265, 0xf0002300, 0xd11dfc0f, 
+    0x0f00f1b8, 0xe9d6bf08, 0xd0cc0100, 0xf0004640, 0x4a9efc9e, 0x460d4604, 0xf0004b9d, 0x4a9dfcff, 
+    0x460f4606, 0x46294620, 0xf0004b9b, 0xb010fcf7, 0x463b4632, 0x4df0e8bd, 0xb9dcf000, 0xf04f4b97, 
+    0x46203255, 0xf0004629, 0x4b95fce9, 0xf0002200, 0x4622fe19, 0x4607462b, 0x4610460e, 0xf0004619, 
+    0x463afcdd, 0xf0004633, 0xf1b8fcd9, 0x46060f00, 0xd01f460f, 0xf0004640, 0x4a84fc6a, 0x468a4680, 
+    0xf0004b83, 0x4632fccb, 0xf000463b, 0x4622fdfb, 0xf000462b, 0x4a7ffe03, 0x460d4604, 0x46514640, 
+    0xf0004b7d, 0xb010fcbb, 0x462b4622, 0x4df0e8bd, 0xbdf4f000, 0x4622b010, 0xe8bd462b, 0xf0004df0, 
+    0x2200bde1, 0x4380f04f, 0xf994f000, 0x460b4602, 0x46294620, 0xfa4af000, 0x460f4606, 0xf0004640, 
+    0xe9cdfc36, 0x46321005, 0x4610463b, 0xf0004619, 0xe9cdfc95, 0x4602100b, 0x486a460b, 0x0c00eb0a, 
+    0xf8cd4610, 0xf000c004, 0xf1cafc89, 0x46830a51, 0x460b4602, 0xf50a4864, 0xf8cd2ad7, 0x9109a038, 
+    0x44782103, 0xfe47f7ff, 0x465a9b09, 0xfc76f000, 0x485d4682, 0x910d465a, 0x44782104, 0xf7ff9b09, 
+    0xe9ddfe3a, 0xf000320b, 0x4652fc69, 0x3a0de9dd, 0xc004f8dd, 0x0a0aea4c, 0xf94cf000, 0x0f00f1ba, 
+    0x91044683, 0xf04fdd4e, 0x462032ff, 0xf0014629, 0x4622f9aa, 0xf000462b, 0xf1b8fc51, 0x46800f00, 
+    0xd02c468a, 0x1005e9dd, 0x4b414a40, 0xfc46f000, 0x465a9109, 0x9b044651, 0x4640900c, 0xf92af000, 
+    0x463b4632, 0xfc3af000, 0x9a0c9b09, 0xf922f000, 0x46534642, 0xfd66f000, 0x462b4622, 0xfd6ef000, 
+    0x460d4604, 0x1005e9dd, 0x4b334a32, 0xfc26f000, 0x4622b010, 0xe8bd462b, 0xf0004df0, 0x9b04bd5f, 
+    0xf000465a, 0x4632f907, 0xf000463b, 0x4642fc17, 0xf0004653, 0xb010fd47, 0x462b4622, 0x4df0e8bd, 
+    0xbd40f000, 0x0f00f1b8, 0xe9ddd028, 0x4a1f1005, 0xf0004b1f, 0x9b04fc03, 0x468a4680, 0x4620465a, 
+    0xf0004629, 0x4632fd3b, 0xf000463b, 0x4642fbf7, 0xf0004653, 0x4622fd33, 0xf000462b, 0x4604fd2f, 
+    0xe9dd460d, 0x4a131005, 0xf0004b13, 0xb010fbe7, 0x462b4622, 0x4df0e8bd, 0xbd20f000, 0x462b4622, 
+    0xfd10f000, 0x463b4632, 0xfbd8f000, 0x4622b010, 0xe8bd462b, 0xf0004df0, 0x0000bd05, 0x7ff00000, 
+    0x00095f64, 0x3ff00000, 0x00001806, 0x35793c76, 0x3dea39ef, 0xfee00000, 0x3fe62e42, 0x3fd55555, 
+    0x3fe00000, 0xfff9eb86, 0x0000169a, 0x41f0e92d, 0x25004604, 0x4281482f, 0xf021da05, 0x42824200, 
+    0xd105d801, 0x4620b124, 0x41f0e8bd, 0xbdd0f7ff, 0x1f80f5b1, 0xea52da1b, 0xd0080004, 0xda0f2900, 
+    0xf7fe2001, 0xe8bdfa2a, 0xf7ff41f0, 0x2002bdc4, 0xfa23f7fe, 0xfdb4f7ff, 0x4100f081, 0x81f0e8bd, 
+    0x46202236, 0x0535f06f, 0xf8ddf001, 0xeb054604, 0xf2405021, 0x460d33ff, 0x32fff2a0, 0x1a1b0fd0, 
+    0xf3634410, 0xf000551f, 0x4606fb12, 0x4620460f, 0xf7ff4629, 0x4a10fe0f, 0xf0004b10, 0x4a10fb6f, 
+    0x460d4604, 0x46394630, 0xf0004b0e, 0x4622fb67, 0xf000462b, 0x4a0cf84f, 0x460d4604, 0x46394630, 
+    0xf0004b0a, 0x4622fb5b, 0xe8bd462b, 0xf00041f0, 0x0000b841, 0x7ff00000, 0x1526e50e, 0x3fdbcb7b, 
+    0x11f12b36, 0x3d59fef3, 0x509f6000, 0x3fd34413, 0x4200f021, 0x5260f1a2, 0x1f80f5b2, 0x4300f001, 
+    0xf1d2bf28, 0xd90b6c7f, 0x1c00ea5f, 0x02c2ea43, 0x7050eb42, 0x4770bf18, 0xf020bf28, 0x47700001, 
+    0x1f80f5b2, 0x4618bfbc, 0xea4f4770, 0xf51c0c41, 0xd2021f00, 0xf0004608, 0xb570bfca, 0xfbc8f000, 
+    0x89000000, 0xbff6f7ff, 0x4000f04f, 0x0080f5a0, 0x00004770, 0xea91b510, 0xbf480f03, 0x4300f083, 
+    0x8454f100, 0xeb711a84, 0xd2050c03, 0xeb431912, 0x1b00030c, 0x010ceb61, 0xe124f8df, 0x5411ea4f, 
+    0x5c13eba4, 0x0f43ea1e, 0xea9ebf18, 0xd0735f44, 0x030eea23, 0x0e20f1dc, 0x5104ea21, 0x1380f443, 
+    0xfa22d332, 0xeb10fe0c, 0xfa23000e, 0xeb41fe0c, 0xf1cc010e, 0xfa030e20, 0xeb10fe0e, 0xf151000e, 
+    0xf5b10100, 0xf1cc1f80, 0xd2320e20, 0x5104eb01, 0xf20efa12, 0x4010e8bd, 0x4770bf58, 0xbf381c40, 
+    0x0242ea5f, 0x4770bf18, 0xbf142800, 0x0001f020, 0x0100f141, 0x0341ea4f, 0x1f00f513, 0x4770bf38, 
+    0x41c0f1a1, 0xbbb2f000, 0xeb432a01, 0xf1ac0203, 0xf1dc0c20, 0xbf320e1f, 0x0e00f04f, 0xf30cfa23, 
+    0x0003eb10, 0x5104eb41, 0x5f11ebb4, 0xeba1d0d0, 0xf5015104, 0x08491180, 0x0030ea5f, 0x5104eb01, 
+    0xf150d30e, 0xbf380000, 0xfe0efa12, 0xe8bdd108, 0xe7c94010, 0xbf381c40, 0x0242ea5f, 0xe7c3d1ca, 
+    0x4010e8bd, 0x0341ea4f, 0x1f00f513, 0x4770bf38, 0x41c0f1a1, 0xbb7af000, 0x5f44ea9e, 0xea11d008, 
+    0xe8bd0f5e, 0xbf044010, 0x4100f001, 0x47702000, 0x4010e8bd, 0xf000b570, 0xbf00fb1b, 0x3ebefb64, 
+    0xffe00000, 0xf04f4902, 0xf0000000, 0xbf00bf8a, 0x7ff80000, 0xbf581049, 0x4140f1c1, 0xbf58105b, 
+    0x4340f1c3, 0xf3ef428b, 0x47708000, 0x41c0e92d, 0xf8dfb430, 0xea3cc2a0, 0xbf181411, 0x1413ea3c, 
+    0x80ecf000, 0x0503ea81, 0x1411ea1c, 0x74d5ea44, 0xea1cbf18, 0xf0001513, 0xeba480c7, 0xf04f0405, 
+    0xea454500, 0xea4521c1, 0xea4123c3, 0xea435150, 0xf1045352, 0x4299747f, 0x3400f504, 0x20c0ea4f, 
+    0x22c2ea4f, 0x4290bf08, 0x809cf000, 0x6513ea4f, 0x1640f20f, 0xea4f5d76, 0xfb064513, 0xf1c7f705, 
+    0xfb067780, 0xea4ff707, 0xfba737d7, 0x42766803, 0x3880f5c8, 0xce06fba7, 0xf1a8bf38, 0xfb070801, 
+    0xf04fe608, 0xfba60e00, 0xfbe68c02, 0xf1dcce03, 0xf1ce0c00, 0xbf384e00, 0x0e01f1ae, 0x580cfba6, 
+    0x0700f04f, 0x0500f04f, 0x870efbe6, 0xc608fba1, 0xce07fba0, 0x060eeb16, 0x0500f145, 0x6507fbe1, 
+    0x4ee0f115, 0xf5a4bf7e, 0xea5f3480, 0x416d0646, 0x0780f116, 0x0500f145, 0x2717ea4f, 0x6606ea4f, 
+    0x6705ea47, 0x46def1a6, 0x5f80f1b6, 0x2515ea4f, 0x4638d91f, 0x0c01f024, 0x71c4eb05, 0x6ffef1bc, 
+    0x110ceb01, 0xbcf0d802, 0x8100e8bd, 0xbf5c4224, 0x1e80f501, 0x7fc4ea9e, 0xbcf0d402, 0x8100e8bd, 
+    0xd4384224, 0xf1a1bcf0, 0xe8bd41c0, 0xf0004100, 0xea4fbaad, 0xea4222d2, 0xea4f5243, 0xfba723d3, 
+    0xea4f8602, 0xea4020d0, 0xfb075041, 0xea1e6603, 0xea4f0f0e, 0xfb0521d1, 0xbf586602, 0x5600eba6, 
+    0x5600ebb6, 0x0e52ea4f, 0x7ec3ea4e, 0x0e0eeb18, 0x0e53eb56, 0xeb18d5bd, 0x415e0802, 0xf1551c7f, 
+    0xe7b60500, 0x1580f44f, 0x0700f04f, 0x0600f04f, 0x0800f04f, 0xbcf0e7ad, 0x0000f04f, 0x41c0f101, 
+    0x4100f001, 0x8100e8bd, 0x1f0cea11, 0x1513ea0c, 0xe00cd000, 0x1f0cea13, 0x8025f000, 0x0000f04f, 
+    0xea81bcf0, 0xf0010103, 0xe8bd4100, 0xbcf08100, 0x4100e8bd, 0x0103ea81, 0xba58f000, 0xe8bdbcf0, 
+    0xb5704100, 0xfa04f000, 0x3efc7e09, 0xb807f000, 0x0103ea81, 0x0000f04f, 0x4100f001, 0xea814770, 
+    0xf0000103, 0xbcf0ba43, 0x4100e8bd, 0x0000f04f, 0x47704921, 0xf9fbfdff, 0xf2f4f5f7, 0xebedeef0, 
+    0xe4e6e8e9, 0xdee0e1e3, 0xd8dadbdd, 0xd3d4d5d7, 0xcdcfd0d1, 0xc8cacbcc, 0xc4c5c6c7, 0xbfc0c1c2, 
+    0xbbbcbdbe, 0xb7b8b9ba, 0xb3b4b5b6, 0xafb0b1b2, 0xabacadae, 0xa8a8a9aa, 0xa4a5a6a7, 0xa1a2a3a3, 
+    0x9e9f9fa0, 0x9b9c9c9d, 0x9899999a, 0x95969797, 0x93939495, 0x90919192, 0x8e8e8f8f, 0x8b8c8c8d, 
+    0x89898a8b, 0x87878888, 0x84858586, 0x82838384, 0x80818182, 0x07ff0000, 0x7ff80000, 0x0c03ea51, 
+    0xf51cd417, 0xbf581f80, 0x1f80f5bc, 0x8006f100, 0xbf184299, 0xbf084770, 0x47704290, 0xf511d707, 
+    0xbf581f80, 0x1f80f513, 0x4299d419, 0x42894770, 0xf51c4770, 0xd5081f80, 0x1f80f5bc, 0x428bd5f7, 
+    0x4770bf18, 0x4282bf08, 0xf44f4770, 0xeb1c1c00, 0xbf380f41, 0x0f43eb1c, 0x428bd201, 0xb5704770, 
+    0xf976f000, 0x00492492, 0x5100f04f, 0x5380f04f, 0xbe60f7ff, 0x0341ea4f, 0x5353ea4f, 0x6380f5a3, 
+    0x031ef1d3, 0xf1d3bfc8, 0xdd0c0c21, 0x4200f04f, 0x22c1ea42, 0x5250ea42, 0xfc03fa32, 0x7ce1ea8c, 
+    0x70e1ebac, 0x2b104770, 0x2000bfc4, 0xf5034770, 0xf1bc7c78, 0xd0043fff, 0x4200f06f, 0x0021ea82, 
+    0xb5704770, 0xf944f000, 0x80249249, 0x47702000, 0x0000e7f2, 0x5311ea4f, 0x6380f5a3, 0x031ef1d3, 
+    0xf1d3bfa8, 0xdb080c20, 0x4200f04f, 0x22c1ea42, 0x5250ea52, 0xf003fa32, 0x42094770, 0x2b10d40b, 
+    0x2000bfc4, 0xf5034770, 0xf1bc7c78, 0xd0053fff, 0x30fff04f, 0xf04f4770, 0x47700000, 0xf000b570, 
+    0xbf00f917, 0x80249249, 0x47702000, 0xf010e7f0, 0xbf484200, 0xfab04240, 0xfa10f380, 0xd00af103, 
+    0x031df1c3, 0x6380f503, 0x5041ea4f, 0x5203eb02, 0x21d1eb02, 0xf04f4770, 0x47700000, 0xf380fab0, 
+    0xf103fa10, 0xf1c3d00a, 0xf503031d, 0xea4f6380, 0xea4f5041, 0xeb025203, 0x477021d1, 0x0000f04f, 
+    0x00004770, 0x0c03ea51, 0xf51cd417, 0xbf581f80, 0x1f80f5bc, 0x8006f100, 0xbf184299, 0xbf084770, 
+    0x47704290, 0xf511d707, 0xbf581f80, 0x1f80f513, 0x4299d419, 0x42894770, 0xf51c4770, 0xd5081f80, 
+    0x1f80f5bc, 0x428bd5f7, 0x4770bf18, 0x4282bf08, 0xf44f4770, 0xeb1c1c00, 0xbf380f41, 0x0f43eb1c, 
+    0x428bd201, 0xb5704770, 0xf8b2f000, 0x00492492, 0x5100f04f, 0x5380f04f, 0xbd9cf7ff, 0xc148f8df, 
+    0xea1cb570, 0xbf1e1e11, 0x1513ea1c, 0x0f0cea9e, 0x0f0cea95, 0x806ff000, 0x0403ea81, 0x134cea23, 
+    0x7ed4ea4e, 0x114cea21, 0x1180f441, 0x1380f443, 0xfba144ae, 0xfba04c02, 0xf1ae6503, 0x19367e7f, 
+    0x050ceb55, 0x4c03fba1, 0x0300f14c, 0x1c02fba0, 0x060ceb16, 0xf1534165, 0x42090300, 0xf046bf18, 
+    0xf4130601, 0xd10b7f00, 0x3103ea4f, 0x3005ea4f, 0xea410334, 0xea405115, 0xf06f5016, 0xe00a0203, 
+    0x21c3ea4f, 0x20c5ea4f, 0xea4102f4, 0xea405155, 0xf06f5056, 0xeb020202, 0xeb01422e, 0xea855502, 
+    0xd00a71ce, 0x0c44ea5f, 0xf024bf18, 0xf1504400, 0xf1410000, 0xea200100, 0xf24070d4, 0x45627cfe, 
+    0xbd70d200, 0xbf1442a8, 0x4480f04f, 0x4440f04f, 0xbf082e00, 0xf1be2400, 0xbfa86f80, 0x41c0f1a1, 
+    0x4070e8bd, 0x8082f280, 0x0000f04f, 0x41c0f101, 0x4100f001, 0xea9e4770, 0xea0c0f0c, 0xbf181513, 
+    0x0f0cea95, 0xf04fd006, 0xea810000, 0xf00e0e03, 0xbd704100, 0xf81cf000, 0x3e010089, 0xb807f000, 
+    0xb809f000, 0x0c43ea4f, 0x5c5cea5f, 0xea81d008, 0xf0000103, 0xea4fb85b, 0xea5f0c41, 0xd1f65c5c, 
+    0x0000f04f, 0x47704901, 0x07ff0000, 0x7ff80000, 0x0e02f10e, 0x0e03f02e, 0x6b04f85e, 0xd4054236, 
+    0xeb432a01, 0xf5150503, 0xd8121f00, 0xeb412801, 0xf51c0c01, 0xd80c1f00, 0xea4fd10e, 0xf5157cd1, 
+    0xeb0c1f00, 0xf10c0c4c, 0xbf080c02, 0x7cd3eb4c, 0xf04fe004, 0xe0010c08, 0x7cd3ea4f, 0x054ceb0c, 
+    0xf605fa26, 0x0607f006, 0x0c04f1b6, 0xeb0ed206, 0xe8bd0c86, 0xf04c4070, 0x47600c01, 0xf00ce8df, 
+    0x02020b09, 0x4100f04f, 0x0000f04f, 0x2100f5a1, 0x4619bd70, 0x28014610, 0x0401eb51, 0xf5d4bf18, 
+    0xbf841400, 0xf0012000, 0xbd704100, 0xf5a00808, 0xea4f1100, 0x47700131, 0x0c01ea53, 0xf51cd417, 
+    0xbf581f80, 0x1f80f5bc, 0x8006f100, 0xbf18428b, 0xbf084770, 0x47704282, 0xf513d707, 0xbf581f80, 
+    0x1f80f511, 0x428bd419, 0x429b4770, 0xf51c4770, 0xd5081f80, 0x1f80f5bc, 0x4299d5f7, 0x4770bf18, 
+    0x4290bf08, 0xf44f4770, 0xeb1c1c00, 0xbf380f43, 0x0f41eb1c, 0x4299d201, 0xb40f4770, 0xbc03bc0c, 
+    0xbec1f7ff, 0x0f03ea91, 0xf081b510, 0xf53f4100, 0xf083abb9, 0xf0004300, 0x0000b809, 0xea91b510, 
+    0xbf480f03, 0x4300f083, 0xabacf53f, 0xeb711a84, 0xd2070c03, 0xf08c1912, 0xeb434c00, 0x1b00030c, 
+    0x010ceb61, 0xe1a4f8df, 0x5411ea4f, 0x5c13eba4, 0x0f43ea1e, 0xea9ebf18, 0xf0005f44, 0xea2380b0, 
+    0x4252036e, 0x5104ea21, 0x036eebc3, 0x1e5bbf38, 0x0e20f1dc, 0xfa22d325, 0xeb10fe0c, 0xfa43000e, 
+    0xeb41fe0c, 0xf1cc010e, 0xfa030e20, 0xeb10fe0e, 0xf151000e, 0xf1cc0100, 0xd4290e20, 0xf20efa12, 
+    0x5104eb01, 0x4010e8bd, 0x4770bf58, 0xbf1c1c40, 0x4f00f1b2, 0x28004770, 0x1c49bf0c, 0x0001f020, 
+    0xeb124770, 0xeb430e02, 0xbf180203, 0x0e01f04f, 0x0242ea4e, 0x0c20f1ac, 0x0e1ef1dc, 0xfa43d954, 
+    0xeb10fe0c, 0xf151000e, 0xf1cc31ff, 0xd5d50e1e, 0x0e01f10e, 0xfe0efa12, 0xeb414140, 0xeb010101, 
+    0xea5f5c44, 0xd9105c5c, 0x70deeb10, 0x5104eb01, 0xf1bebf38, 0xe8bd4f00, 0xbf184010, 0x28004770, 
+    0x1c49bf0c, 0x0001f020, 0xd2304770, 0x2cd4ea4f, 0x1100f511, 0x6400f424, 0xfab1d01b, 0x3a0bf281, 
+    0x1ea41aa4, 0x0320f1d2, 0xfa304091, 0x4319f303, 0xeb014090, 0x2c0071cc, 0x5104eb01, 0x4010e8bd, 
+    0x4770bfa8, 0x41c0f101, 0x0000f04f, 0x4100f001, 0xfab04770, 0xfa10f380, 0xd100f103, 0x1ae4bd10, 
+    0x05483c17, 0xe7e40ac9, 0x5104eb01, 0x1049bd10, 0x5104eb01, 0x4010e8bd, 0x0030ea4f, 0xf04fe002, 
+    0x47700100, 0xbf08004a, 0xd0f84200, 0x1f00f5b2, 0x4770bf28, 0x4100f001, 0x0000f04f, 0xea9e4770, 
+    0xd0075f44, 0x0f5eea11, 0x4010e8bd, 0x2100bf04, 0x47702000, 0x4010e8bd, 0xf7ffb570, 0xbf00fe89, 
+    0x3ef6df40, 0x4100f083, 0x47704610, 0xffe00000, 0xea4f0043, 0xea4f0cd3, 0x40430c3c, 0x0740bf1f, 
+    0x5160f10c, 0x4ffef013, 0xf01c4770, 0xd1036f00, 0xf00c2000, 0x47704100, 0x4300f00c, 0x7050ea43, 
+    0xea40b510, 0xf00000cc, 0xbf00fa1c, 0x92000000, 0x0100ea4f, 0xbeaaf7ff, 0x4100f04f, 0x0000f04f, 
+    0x2100f5a1, 0x00004770, 0x0f01ea90, 0xf081bf48, 0xf1004100, 0x1a428258, 0x1a80bf3c, 0xea4f1889, 
+    0xf04f52d0, 0xea1c4c7f, 0xeba20f41, 0xbf1853d1, 0x6f02ea9c, 0x803bf000, 0x4c00f04f, 0x2000ea4c, 
+    0x2101ea4c, 0xfc03fa21, 0x0c0ceb10, 0xf102d21e, 0xea5f32ff, 0xeb40201c, 0xbf3850c2, 0xf01c4770, 
+    0xea4f0f7f, 0xbf180c40, 0x4f7ff1bc, 0x4770bf38, 0x0320f1c3, 0xbf084099, 0x0001f020, 0x4f7ff1bc, 
+    0x4770bf38, 0x40c0f1a0, 0xba11f000, 0x003cea4f, 0xeb400a00, 0xbf2850c2, 0x0ffff01c, 0x0c40ea4f, 
+    0xbf18d0e6, 0x4f7ff1bc, 0x4770bf38, 0xea9ce7ea, 0xd0056f02, 0x0f5cea10, 0xf000bf08, 0x47704000, 
+    0xf000b510, 0xbf00f9ae, 0x3ebefb64, 0x0c7ff44f, 0x12d0ea1c, 0xea1cbf1e, 0xea9213d1, 0xea930f0c, 
+    0xf0000f0c, 0xea908085, 0xbf480f01, 0x7280f442, 0x0c00f440, 0x0000f441, 0x417ff02c, 0x407ff020, 
+    0x4281b500, 0x0203eba2, 0x1c08f20f, 0x4e50ebac, 0x0000f1c0, 0xe000f89e, 0x0e4eea4f, 0xfc0efb00, 
+    0x0049bf38, 0x1c2cea4f, 0x02faf502, 0xf30efb0c, 0x1eceea4f, 0x2c11ea4f, 0x21c1ea4f, 0x5e63eb0e, 
+    0x4222eb42, 0xfc0cfb0e, 0x531cea4f, 0x1103fb00, 0x2c11ea4f, 0x3101ea4f, 0xfc0cfb0e, 0x4cdcea4f, 
+    0x110cfb00, 0xbf2842c1, 0xeb4c1809, 0xf85d3303, 0xeb10eb04, 0xeb430141, 0xf5b250c2, 0xbf380f7c, 
+    0xd5294770, 0x0ff0f012, 0xf100bf1c, 0xf00040c0, 0x47704000, 0x83828100, 0x87868584, 0x8c8b8988, 
+    0x918f8e8d, 0x96959392, 0x9c9a9997, 0xa2a09f9d, 0xa8a7a5a3, 0xb0aeacaa, 0xb7b5b3b2, 0xc0bebcb9, 
+    0xc9c7c5c2, 0xd4d1cecc, 0xdfdcd9d7, 0xece9e6e2, 0xfaf7f3f0, 0x000000fe, 0x0c40ea4f, 0x7c80f10c, 
+    0x4f7ef1bc, 0x4770bf28, 0x40c0f1b0, 0xb95ff000, 0x0f01ea90, 0x13d1ea0c, 0xf442bf48, 0x45627280, 
+    0x4563bf38, 0xf413d207, 0xd0160f7f, 0x0001ea80, 0x4000f000, 0xb5104770, 0xf903f000, 0x3efc7e09, 
+    0xb805f000, 0x0001ea80, 0x4000f000, 0xea804770, 0xf0000001, 0xf0004000, 0xf412b93a, 0xbf040f7f, 
+    0x47704802, 0x0001ea80, 0xb931f000, 0x7fc00000, 0x0e0b0041, 0x029ef1d3, 0xf450d908, 0xea4f0300, 
+    0xfa232303, 0xbf48f002, 0x47704240, 0xf000b510, 0xbf00f8d8, 0x80249249, 0x47702000, 0x4200f06f, 
+    0x0020ea82, 0x00004770, 0xf1d10dc1, 0xdb06029e, 0x2300ea4f, 0x4300f043, 0xf002fa23, 0x42004770, 
+    0xea4fd507, 0xf1b10140, 0xd2024ffe, 0x0000f04f, 0xb5104770, 0xf8b5f000, 0x80249249, 0x47702000, 
+    0x0020ea6f, 0x00004770, 0x4100f010, 0x4240bf48, 0xf380fab0, 0xf203fa10, 0x039df1c3, 0xea51d00b, 
+    0xeb0151c3, 0x06532012, 0x4770bf38, 0x0001f100, 0xf020bf08, 0x47700001, 0xf380fab0, 0xf203fa10, 
+    0x039df1c3, 0x05d9d00a, 0x2012eb01, 0xbf380653, 0xf1004770, 0xbf080001, 0x0001f020, 0x00004770, 
+    0x0c7ff44f, 0x12d0ea1c, 0xea1cbf1e, 0xea9213d1, 0xea930f0c, 0xf0000f0c, 0xea908047, 0xbf480f01, 
+    0x7280f442, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 0x0203eb02, 0x1301fba0, 0x0200f5a2, 0xbf182900, 
+    0x0301f043, 0xbf28005b, 0x0333ea4f, 0x4222eb42, 0x2c13ea5f, 0x50c2eb4c, 0xebbcbf2e, 0xf5b26f43, 
+    0x47700f7c, 0x6c03ea4f, 0x4f00f1bc, 0xf020bf08, 0xf5b20001, 0xbf380f7c, 0xd50b4770, 0x02fff082, 
+    0x3f80f512, 0x4770bfc8, 0x40c0f100, 0xf000bfd8, 0x47704000, 0x0c00f500, 0x0c4cea5f, 0x4770bf48, 
+    0x40c0f1b0, 0xb873f000, 0x0f01ea90, 0x13d1ea0c, 0xf442bf48, 0x45627280, 0x4563bf38, 0xea80d204, 
+    0xf0000001, 0x47704000, 0xf000b510, 0xbf00f81a, 0x3e010089, 0xb807f000, 0xb809f000, 0x0c41ea5f, 
+    0x6c1cea5f, 0xea80d008, 0xf0000001, 0xea5fb850, 0xea5f0c40, 0xd1f66c1c, 0x4000f04f, 0x0080f5a0, 
+    0xf10e4770, 0xf02e0e02, 0xf85e0e03, 0x42244b04, 0xea4fd404, 0xf1b20241, 0xd8114f7f, 0x0340ea4f, 
+    0x4f7ff1b3, 0xd10ed80c, 0x7cd0ea4f, 0x4f7ff1b2, 0x0c4ceb0c, 0x0c02f10c, 0xeb4cbf08, 0xe0047cd1, 
+    0x0c08f04f, 0xea4fe001, 0xeb0c7cd1, 0xfa24034c, 0xf004f403, 0xf1b40407, 0xd2060c04, 0x0c84eb0e, 
+    0x4010e8bd, 0x0c01f04c, 0xe8df4760, 0x0807f00c, 0xf04f0202, 0xf5a04000, 0xbd100080, 0x00424608, 
+    0xf1d2bf18, 0xbf887280, 0x4000f000, 0x21ffbd10, 0x50d0ea41, 0x477005c0, 0x0f01ea90, 0xf081bf48, 
+    0xf53f4100, 0x1a42ada8, 0xf082d804, 0xeba04200, 0x44110002, 0x52d0ea4f, 0x4c7ff04f, 0x0f41ea1c, 
+    0x53d1eba2, 0xea9cbf18, 0xd04a6f02, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 0xfc03fa21, 0x0c0cebb0, 
+    0xf012d40f, 0xd0360ffe, 0x004cea5f, 0x1200d51d, 0x50c2eb40, 0x4770bf38, 0x0f3ff01c, 0x4770bf18, 
+    0xf1a2e00b, 0xea5f0201, 0xeb40201c, 0xbf3850c2, 0xf01c4770, 0xbf180f7f, 0xf1c34770, 0x40990320, 
+    0x1e40bf14, 0x0001f020, 0x08804770, 0x2312ea4f, 0x4770bf08, 0xfc80fab0, 0x020ceba2, 0x0c28f1cc, 
+    0xf00cfa60, 0x2f12ea93, 0xeb00bf04, 0x477050c2, 0x70c3ea4f, 0x0a134770, 0x10dcea5f, 0x4770bf08, 
+    0xea9ce7f6, 0xd0046f02, 0x0f5cea10, 0x2000bf08, 0xb5104770, 0xff45f7ff, 0x3ef6df40, 0x4000f081, 
+    0xf00c4770, 0x2b09030f, 0x2008bf08, 0x8059f000, 0xd00b2b0a, 0xbf182b08, 0xbf084770, 0x0f40f01c, 
+    0xf04fd00a, 0xf04f0000, 0x47700100, 0x0f40f01c, 0xf04fbf18, 0x47704000, 0x0f10f01c, 0xf020d008, 
+    0xf0004370, 0xea42427f, 0xea4f01d3, 0x47707043, 0x4060f000, 0x427ff021, 0x0200ea42, 0x407ff001, 
+    0x7072ea40, 0xf04f4770, 0xf44c0cff, 0xea1c6ce0, 0xbf1c5311, 0x0c03ea9c, 0xbfc24594, 0xeb0142da, 
+    0x47705102, 0xd00d2b00, 0x0f00f1bc, 0x2a00d00f, 0x4100f001, 0xf041bfa4, 0xf04141e0, 0xf04f617f, 
+    0x47700000, 0x4100f001, 0x0000f04f, 0xea504770, 0xf04f3301, 0xbf180c9b, 0x6c80f04c, 0xa812f47f, 
+    0xf41c4770, 0xd0111f80, 0x2fe0f41c, 0xea6fd003, 0x004931cc, 0xf04f4770, 0xf3ef5040, 0xf0228200, 
+    0xea424270, 0xf3820200, 0x47708800, 0x0000f04f, 0xfb904770, 0xfb02f2f1, 0x46100111, 0xfbb04770, 
+    0xfb02f2f1, 0x46100111, 0x02004770, 0x03010604, 0x00160011, 0x001e001b, 0x002a0025, 0x0034002f, 
+    0x003c0039, 0x00008000, 0x000014da, 0xffffd475, 0xffffe80d, 0xfffff580, 0xfffffb0b, 0xfffffe74, 
+    0xffffffa2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00008000, 
+    0x00001485, 0xffffc75c, 0xffffe6ca, 0xfffff8ce, 0xfffffdb2, 0x0000014a, 0x0000021c, 0x000002e6, 
+    0x0000024f, 0xfffffe3b, 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0xfffff021, 0xffffd31c, 
+    0xfffffd00, 0xffffffb0, 0x000006c6, 0x000003ac, 0x00000014, 0xfffffed1, 0x0000004c, 0x00000033, 
+    0x0000005f, 0x000002c5, 0x00000093, 0x00008000, 0x0000058e, 0xffffcb80, 0xfffff332, 0x000001a3, 
+    0x0000011a, 0xfffffc74, 0x00000139, 0x00000321, 0xfffffef5, 0x0000028f, 0x00000281, 0x000000c0, 
+    0xfffffeb8, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020100, 0x08060504, 0x0d0c0b0a, 
+    0x00100f0e, 0x04030201, 0x0a080605, 0x0e0d0c0b, 0x0100100f, 0x05040302, 0x09080706, 0x0d0c0b0a, 
+    0x0201000e, 0x06050403, 0x0a090807, 0x0e0d0c0b, 0x00000000, 0x00000000, 0x00000001, 0x0000000f, 
+    0x0000000f, 0x0000000e, 0x00000003, 0x00000002, 0x00000002, 0x0000000b, 0x0000000c, 0x0000000d, 
+    0x03020100, 0x08060504, 0x0d0c0b0a, 0x00100f0e, 0x04030201, 0x0a080605, 0x0e0d0c0b, 0x0100100f, 
+    0x05040302, 0x09080706, 0x0d0c0b0a, 0x0000000e, 0xd0033070, 0xd0033270, 0xd0033470, 0xd0033670, 
+    0x024d3fff, 0x016801d5, 0x01060131, 0x00cf00ea, 0x02b43fff, 0x020b0252, 0x017701c4, 0x011d0153, 
+    0x02e83fff, 0x024f0292, 0x01c901f8, 0x0160019d, 0x00230000, 0x0037002d, 0x004b0041, 0x005f0055, 
+    0x0020001b, 0x00250020, 0x00050005, 0x00260022, 0x3f7d3d64, 0x3f7b82e8, 0x3f7b82e8, 0x3f7b82e8, 
+    0x3f821965, 0x3f832f88, 0x3f832f88, 0x3f832f88, 0xc4ba4052, 0xc4eab6f0, 0xc4eab6f0, 0xc4eab6f0, 
+    0xc4bdd99a, 0xc4bb0000, 0xc4bb0000, 0xc4bb0000, 0x0020001f, 0x00200020, 0x001f0025, 0x001f001f, 
+    0x9997fa04, 0x3fd99999, 0x1d8e78af, 0x3fcc71c5, 0xd078c69f, 0x3fc39a09, 0x55555593, 0x3fe55555, 
+    0x94229359, 0x3fd24924, 0x96cb03de, 0x3fc74664, 0xdf3e5244, 0x3fc2f112, 0x00000000, 0x00000000, 
+    0x00030910, 0x00036000, 0x00002e8c, 0x0000053c, 0x00032560, 0x00052800, 0x00000010, 0x00000598, 
+    0x00032570, 0x00052f80, 0x00000018, 0x00000598, 0x00032560, 0x00038e8c, 0x00014100, 0x000005b4, 
+    0x00032560, 0x0004cf8c, 0x00000060, 0x000005b4, 0x00032560, 0x00050800, 0x00002000, 0x000005b4, 
+    0x00032570, 0x00052810, 0x00000490, 0x000005b4, 0x00032588, 0x00053000, 0x00001000, 0x000005b4, 
+    0x00032588, 0x00054000, 0x00004000, 0x000005b4, 0x00007fff, 0xfcdc7ff6, 0xf9b87fd9, 0xf6957fa7, 
+    0xf3747f62, 0xf0557f0a, 0xed387e9d, 0xea1e7e1e, 0xe7077d8a, 0xe3f47ce4, 0xe0e67c2a, 0xdddc7b5d, 
+    0xdad87a7d, 0xd7d9798a, 0xd4e17885, 0xd1ef776c, 0xcf047642, 0xcc217505, 0xc94673b6, 0xc6737255, 
+    0xc3a970e3, 0xc0e96f5f, 0xbe326dca, 0xbb856c24, 0xb8e36a6e, 0xb64c68a7, 0xb3c066d0, 0xb14064e9, 
+    0xaecc62f2, 0xac6560ec, 0xaa0a5ed7, 0xa7bd5cb4, 0xa57e5a82, 0xa34c5843, 0xa12955f6, 0x9f14539b, 
+    0x9d0e5134, 0x9b174ec0, 0x99304c40, 0x975949b4, 0x9592471d, 0x93dc447b, 0x923641ce, 0x90a13f17, 
+    0x8f1d3c57, 0x8dab398d, 0x8c4a36ba, 0x8afb33df, 0x89be30fc, 0x88942e11, 0x877b2b1f, 0x86762827, 
+    0x85832528, 0x84a32224, 0x83d61f1a, 0x831c1c0c, 0x827618f9, 0x81e215e2, 0x816312c8, 0x80f60fab, 
+    0x809e0c8c, 0x8059096b, 0x80270648, 0x800a0324, 0x80000000, 0x800afcdc, 0x8027f9b8, 0x8059f695, 
+    0x809ef374, 0x80f6f055, 0x8163ed38, 0x81e2ea1e, 0x8276e707, 0x831ce3f4, 0x83d6e0e6, 0x84a3dddc, 
+    0x8583dad8, 0x8676d7d9, 0x877bd4e1, 0x8894d1ef, 0x89becf04, 0x8afbcc21, 0x8c4ac946, 0x8dabc673, 
+    0x8f1dc3a9, 0x90a1c0e9, 0x9236be32, 0x93dcbb85, 0x9592b8e3, 0x9759b64c, 0x9930b3c0, 0x9b17b140, 
+    0x9d0eaecc, 0x9f14ac65, 0xa129aa0a, 0xa34ca7bd, 0xa57ea57e, 0xa7bda34c, 0xaa0aa129, 0xac659f14, 
+    0xaecc9d0e, 0xb1409b17, 0xb3c09930, 0xb64c9759, 0xb8e39592, 0xbb8593dc, 0xbe329236, 0xc0e990a1, 
+    0xc3a98f1d, 0xc6738dab, 0xc9468c4a, 0xcc218afb, 0xcf0489be, 0xd1ef8894, 0xd4e1877b, 0xd7d98676, 
+    0xdad88583, 0xdddc84a3, 0xe0e683d6, 0xe3f4831c, 0xe7078276, 0xea1e81e2, 0xed388163, 0xf05580f6, 
+    0xf374809e, 0xf6958059, 0xf9b88027, 0xfcdc800a, 0x00008000, 0x0324800a, 0x06488027, 0x096b8059, 
+    0x0c8c809e, 0x0fab80f6, 0x12c88163, 0x15e281e2, 0x18f98276, 0x1c0c831c, 0x1f1a83d6, 0x222484a3, 
+    0x25288583, 0x28278676, 0x2b1f877b, 0x2e118894, 0x30fc89be, 0x33df8afb, 0x36ba8c4a, 0x398d8dab, 
+    0x3c578f1d, 0x3f1790a1, 0x41ce9236, 0x447b93dc, 0x471d9592, 0x49b49759, 0x4c409930, 0x4ec09b17, 
+    0x51349d0e, 0x539b9f14, 0x55f6a129, 0x5843a34c, 0x5a82a57e, 0x5cb4a7bd, 0x5ed7aa0a, 0x60ecac65, 
+    0x62f2aecc, 0x64e9b140, 0x66d0b3c0, 0x68a7b64c, 0x6a6eb8e3, 0x6c24bb85, 0x6dcabe32, 0x6f5fc0e9, 
+    0x70e3c3a9, 0x7255c673, 0x73b6c946, 0x7505cc21, 0x7642cf04, 0x776cd1ef, 0x7885d4e1, 0x798ad7d9, 
+    0x7a7ddad8, 0x7b5ddddc, 0x7c2ae0e6, 0x7ce4e3f4, 0x7d8ae707, 0x7e1eea1e, 0x7e9ded38, 0x7f0af055, 
+    0x7f62f374, 0x7fa7f695, 0x7fd9f9b8, 0x7ff6fcdc, 0x7fff0000, 0x7ff60324, 0x7fd90648, 0x7fa7096b, 
+    0x7f620c8c, 0x7f0a0fab, 0x7e9d12c8, 0x7e1e15e2, 0x7d8a18f9, 0x7ce41c0c, 0x7c2a1f1a, 0x7b5d2224, 
+    0x7a7d2528, 0x798a2827, 0x78852b1f, 0x776c2e11, 0x764230fc, 0x750533df, 0x73b636ba, 0x7255398d, 
+    0x70e33c57, 0x6f5f3f17, 0x6dca41ce, 0x6c24447b, 0x6a6e471d, 0x68a749b4, 0x66d04c40, 0x64e94ec0, 
+    0x62f25134, 0x60ec539b, 0x5ed755f6, 0x5cb45843, 0x5a825a82, 0x58435cb4, 0x55f65ed7, 0x539b60ec, 
+    0x513462f2, 0x4ec064e9, 0x4c4066d0, 0x49b468a7, 0x471d6a6e, 0x447b6c24, 0x41ce6dca, 0x3f176f5f, 
+    0x3c5770e3, 0x398d7255, 0x36ba73b6, 0x33df7505, 0x30fc7642, 0x2e11776c, 0x2b1f7885, 0x2827798a, 
+    0x25287a7d, 0x22247b5d, 0x1f1a7c2a, 0x1c0c7ce4, 0x18f97d8a, 0x15e27e1e, 0x12c87e9d, 0x0fab7f0a, 
+    0x0c8c7f62, 0x096b7fa7, 0x06487fd9, 0x03247ff6, 0x00007fff, 0xfe6e7ffe, 0xfcdc7ff6, 0xfb4a7fea, 
+    0xf9b87fd9, 0xf8277fc2, 0xf6957fa7, 0xf5057f87, 0xf3747f62, 0xf1e47f38, 0xf0557f0a, 0xeec67ed6, 
+    0xed387e9d, 0xebab7e60, 0xea1e7e1e, 0xe8927dd6, 0xe7077d8a, 0xe57d7d3a, 0xe3f47ce4, 0xe26d7c89, 
+    0xe0e67c2a, 0xdf617bc6, 0xdddc7b5d, 0xdc597aef, 0xdad87a7d, 0xd9587a06, 0xd7d9798a, 0xd65c790a, 
+    0xd4e17885, 0xd36777fb, 0xd1ef776c, 0xd07976d9, 0xcf047642, 0xcd9275a6, 0xcc217505, 0xcab27460, 
+    0xc94673b6, 0xc7db7308, 0xc6737255, 0xc50d719e, 0xc3a970e3, 0xc2487023, 0xc0e96f5f, 0xbf8c6e97, 
+    0xbe326dca, 0xbcda6cf9, 0xbb856c24, 0xba336b4b, 0xb8e36a6e, 0xb796698c, 0xb64c68a7, 0xb50567bd, 
+    0xb3c066d0, 0xb27f65de, 0xb14064e9, 0xb00563ef, 0xaecc62f2, 0xad9761f1, 0xac6560ec, 0xab365fe4, 
+    0xaa0a5ed7, 0xa8e25dc8, 0xa7bd5cb4, 0xa69c5b9d, 0xa57e5a82, 0xa4635964, 0xa34c5843, 0xa238571e, 
+    0xa12955f6, 0xa01c54ca, 0x9f14539b, 0x9e0f5269, 0x9d0e5134, 0x9c114ffb, 0x9b174ec0, 0x9a224d81, 
+    0x99304c40, 0x98434afb, 0x975949b4, 0x9674486a, 0x9592471d, 0x94b545cd, 0x93dc447b, 0x93074326, 
+    0x923641ce, 0x91694074, 0x90a13f17, 0x8fdd3db8, 0x8f1d3c57, 0x8e623af3, 0x8dab398d, 0x8cf83825, 
+    0x8c4a36ba, 0x8ba0354e, 0x8afb33df, 0x8a5a326e, 0x89be30fc, 0x89272f87, 0x88942e11, 0x88052c99, 
+    0x877b2b1f, 0x86f629a4, 0x86762827, 0x85fa26a8, 0x85832528, 0x851123a7, 0x84a32224, 0x843a209f, 
+    0x83d61f1a, 0x83771d93, 0x831c1c0c, 0x82c61a83, 0x827618f9, 0x822a176e, 0x81e215e2, 0x81a01455, 
+    0x816312c8, 0x812a113a, 0x80f60fab, 0x80c80e1c, 0x809e0c8c, 0x80790afb, 0x8059096b, 0x803e07d9, 
+    0x80270648, 0x801604b6, 0x800a0324, 0x80020192, 0x80000000, 0x8002fe6e, 0x800afcdc, 0x8016fb4a, 
+    0x8027f9b8, 0x803ef827, 0x8059f695, 0x8079f505, 0x809ef374, 0x80c8f1e4, 0x80f6f055, 0x812aeec6, 
+    0x8163ed38, 0x81a0ebab, 0x81e2ea1e, 0x822ae892, 0x8276e707, 0x82c6e57d, 0x831ce3f4, 0x8377e26d, 
+    0x83d6e0e6, 0x843adf61, 0x84a3dddc, 0x8511dc59, 0x8583dad8, 0x85fad958, 0x8676d7d9, 0x86f6d65c, 
+    0x877bd4e1, 0x8805d367, 0x8894d1ef, 0x8927d079, 0x89becf04, 0x8a5acd92, 0x8afbcc21, 0x8ba0cab2, 
+    0x8c4ac946, 0x8cf8c7db, 0x8dabc673, 0x8e62c50d, 0x8f1dc3a9, 0x8fddc248, 0x90a1c0e9, 0x9169bf8c, 
+    0x9236be32, 0x9307bcda, 0x93dcbb85, 0x94b5ba33, 0x9592b8e3, 0x9674b796, 0x9759b64c, 0x9843b505, 
+    0x9930b3c0, 0x9a22b27f, 0x9b17b140, 0x9c11b005, 0x9d0eaecc, 0x9e0fad97, 0x9f14ac65, 0xa01cab36, 
+    0xa129aa0a, 0xa238a8e2, 0xa34ca7bd, 0xa463a69c, 0xa57ea57e, 0xa69ca463, 0xa7bda34c, 0xa8e2a238, 
+    0xaa0aa129, 0xab36a01c, 0xac659f14, 0xad979e0f, 0xaecc9d0e, 0xb0059c11, 0xb1409b17, 0xb27f9a22, 
+    0xb3c09930, 0xb5059843, 0xb64c9759, 0xb7969674, 0xb8e39592, 0xba3394b5, 0xbb8593dc, 0xbcda9307, 
+    0xbe329236, 0xbf8c9169, 0xc0e990a1, 0xc2488fdd, 0xc3a98f1d, 0xc50d8e62, 0xc6738dab, 0xc7db8cf8, 
+    0xc9468c4a, 0xcab28ba0, 0xcc218afb, 0xcd928a5a, 0xcf0489be, 0xd0798927, 0xd1ef8894, 0xd3678805, 
+    0xd4e1877b, 0xd65c86f6, 0xd7d98676, 0xd95885fa, 0xdad88583, 0xdc598511, 0xdddc84a3, 0xdf61843a, 
+    0xe0e683d6, 0xe26d8377, 0xe3f4831c, 0xe57d82c6, 0xe7078276, 0xe892822a, 0xea1e81e2, 0xebab81a0, 
+    0xed388163, 0xeec6812a, 0xf05580f6, 0xf1e480c8, 0xf374809e, 0xf5058079, 0xf6958059, 0xf827803e, 
+    0xf9b88027, 0xfb4a8016, 0xfcdc800a, 0xfe6e8002, 0x00008000, 0x01928002, 0x0324800a, 0x04b68016, 
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+    0x011a0b02, 0x20181114, 0x425294a1, 0x21294a50, 0x1094a528, 0x084a5294, 0x8425294a, 0x421294a5, 
+    0x21094a52, 0x1484a529, 0x1a14421a, 0x101a1421, 0x21081b14, 0x1f101a1f, 0x1a1f081a, 0x421a1f84, 
+    0x1f211a1f, 0x1a1f101a, 0x842a1f08, 0xb649c1a4, 0x801a05c9, 0x2c401a2c, 0x9c20100a, 0x901ab0a9, 
+    0x0b481a0b, 0x1a14a41a, 0x291a1452, 0x14941a14, 0x1a144a1a, 0x14191fa5, 0x1414481a, 0x140494a4, 
+    0x14024210, 0x23012108, 0x42231084, 0x19881908, 0x65191165, 0x19651911, 0x1f081a1f, 0x1a1f841a, 
+    0x211a1f42, 0x8e106a1f, 0xb905019a, 0x0b1831a5, 0x0f0e1002, 0x10100f10, 0x39041001, 0x01013926, 
+    0xffff142b, 0xfffe1c01, 0x3f290802, 0x04fffd14, 0x1604fb1a, 0xfffffffe, 0xfff61406, 0xfff31c0d, 
+    0xf9140e09, 0xe71411ff, 0xe6141dff, 0x02120fff, 0x2affea14, 0x3affc814, 0x14ffd214, 0xc5141112, 
+    0x8f145eff, 0xb51a6dff, 0x143f121c, 0x14d3ff6f, 0x16d8ff10, 0xffe5ff81, 0x1f1810ec, 0x4202dcfe, 
+    0x3c0469fc, 0x9704c4fb, 0x2403befb, 0x1401e1fd, 0x7f121bff, 0xf0ff2814, 0x91ff2d14, 0xf1ffc116, 
+    0x93144bff, 0xa21471ff, 0xef163bff, 0x2effecff, 0x38ffc614, 0x16ffd61c, 0xfff11478, 0xffe31c1a, 
+    0x071a1819, 0x90f73a78, 0xfa1a0a12, 0x1c0212b4, 0x0405fffc, 0x49ba035a, 0xfa2a09c4, 0x1b101001, 
+    0x20131e48, 0x23fd21fa, 0x2862261f, 0x2d4f2ac6, 0x32d62ffe, 0x390a35d9, 0x20283c6b, 0xcf43cb40, 
+    0x924c1047, 0x67555850, 0x6f5fc25a, 0xcf6b7265, 0xb2788e71, 0x4787437f, 0x0297c58f, 0x02dd16e1, 
+    0x181e0180, 0x5eff7d1a, 0x78ff71ff, 0x6aff6bff, 0x93ff80ff, 0x66ff81ff, 0xa3ff73ff, 0x01b2dfff, 
+    0x59fd5953, 0x1a150107, 0x08a901ff, 0x961d0281, 0x19af1c09, 0x6503154b, 0x74230102, 0x23302348, 
+    0x23157c23, 0x1e230ed8, 0x08c9230b, 0x23073c23, 0x4e23061a, 0x04b32305, 0x23043e1a, 0x8d1a03db, 
+    0x044f1a04, 0x2304231a, 0xd51a02f4, 0x04b91a04, 0x1a049c1a, 0x781a0489, 0x04691a04, 0x1a04611a, 
+    0x4d1a045b, 0x044e1a04, 0x1a044b1a, 0x461a0441, 0x04441a04, 0x5a08405a, 0x581a044c, 0x04631a04, 
+    0x1a04711a, 0x8c1a0483, 0x04931a04, 0x29609a5a, 0x04b81a04, 0x1a04c71a, 0xef1a04d3, 0x04f91a04, 
+    0x1a880a1a, 0x481a0425, 0x04541a04, 0x1a04831a, 0xb71a04a6, 0x04df1a04, 0x1a04fd1a, 0x541abc1b, 
+    0x04711a04, 0x1a04a31a, 0xf41a04d0, 0xdc1f1a04, 0x1a045d1a, 0xdc1a0493, 0xf02a1a04, 0x1a047f1a, 
+    0x472304e9, 0x04a01a07, 0x2304f91a, 0xc41a085a, 0x09252304, 0x23049e1a, 0xc21a0a1b, 0x0b592304, 
+    0x2304ce1a, 0x4f230c7e, 0x0e3d230d, 0x230f3223, 0x6c231026, 0x128f2311, 0x2313e023, 0x9c231542, 
+    0x17af1b16, 0x2c191a40, 0xa7231b22, 0x1ea9231c, 0x23212723, 0x2c232365, 0x29372326, 0x232c1823, 
+    0x38232ea5, 0x36042332, 0x23393923, 0x3c1b3e4c, 0x4722c042, 0x234acc23, 0x68235075, 0x5b032355, 
+    0x1b610223, 0x22cc6497, 0x70fb236b, 0x23778e23, 0xb01b7dd8, 0x871a7c83, 0x238e22a8, 0xe52391ab, 
+    0x98d92397, 0x239e1423, 0x1a039f72, 0x9f029ddd, 0x03ff3201, 0x3c270f22, 0x0402947b, 0x81048f1a, 
+    0x00000000, 0x00000000, 0x00053000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x00000000, 0x02338175, 0x33e58b56, 0x4e122870, 0xee5d1255, 0xe0600090, 0x1208e030, 
+    0x03706e2f, 0x90fa2f12, 0xb4e06600, 0xe0a30cff, 0xe407ffb4, 0x12167ffd, 0xf5e47036, 0x9011f510, 
+    0xa3e08304, 0x121e7ff0, 0x0e8e2f60, 0x0ee50f8f, 0x54131313, 0x8304901f, 0x1054eff0, 0x0fe51170, 
+    0xc3ce0578, 0xd813ce13, 0xff3f54f9, 0x909c0712, 0x60e01104, 0x7001642f, 0x1f070203, 0xe0110490, 
+    0x020302b4, 0x04907a37, 0x03b4e011, 0x19330203, 0xe0110490, 0x020304b4, 0x0490c418, 0x05b4e011, 
+    0x10430203, 0x480490e4, 0x840490f0, 0x900d70e0, 0x60e08304, 0x7f027d07, 0x70361203, 0xe0830490, 
+    0x02037014, 0x60045a02, 0xdf020203, 0xe0840490, 0x027d0760, 0x3612017f, 0x12897f70, 0x54efb160, 
+    0xff13c307, 0x04136014, 0x01020360, 0x3f0490ef, 0x120360e0, 0x3012e35c, 0x07122201, 0x75177062, 
+    0x2f1204a4, 0x189c7515, 0x007e0d7f, 0x007c007d, 0x02a95b12, 0x0712b25f, 0x70016462, 0xbb60120f, 
+    0x020370ef, 0x2f121f07, 0x189c7512, 0x0712867f, 0x6009f595, 0xd360123b, 0xe03c0490, 0x2201e030, 
+    0x750e3012, 0x9a75ffa7, 0x91581286, 0x7570a475, 0x2f120fa6, 0x129c7518, 0x7590a475, 0x2f120fa6, 
+    0x129c7518, 0x7580a475, 0x2f120fa6, 0x129c7518, 0x75cb2f12, 0x5c12859a, 0x010490e3, 0x03e030e0, 
+    0x7f165912, 0xb160128b, 0x750f54ef, 0x0ff5000e, 0x756f0712, 0xaea410f0, 0xee0f42f0, 0x0faf0e42, 
+    0x3c12017d, 0x20071280, 0x027f027d, 0x12703612, 0x3012f028, 0x13e0a363, 0x901ae020, 0x60e08904, 
+    0x4c2f1214, 0x75ffa775, 0xa475639a, 0x152f12d0, 0x80189c75, 0x122f120f, 0x12189c75, 0xa7750e30, 
+    0x639a75ff, 0x754c2f12, 0x9a75ffa7, 0x01301285, 0xe00b0490, 0x9022f004, 0x01744804, 0x12f87ff0, 
+    0x54efb160, 0x6413c307, 0x12417001, 0x9a75cb2f, 0x12f67ff5, 0x09f59507, 0x30120c60, 0xffa7750e, 
+    0x12f69a75, 0x6012785b, 0x510090d4, 0x03e030e0, 0x12d26012, 0x017d3607, 0x3612057f, 0x0090e470, 
+    0x2f12f064, 0xffa7754c, 0x22f59a75, 0xe0640090, 0x07020360, 0x7f017d1f, 0x70361204, 0x02640090, 
+    0x0490e203, 0x4460e03f, 0xe0020490, 0x04900670, 0x3870e03e, 0x12e35c12, 0xe0a36330, 0x23e02013, 
+    0x606f0712, 0x4c2f121e, 0x75182f12, 0x2f12179c, 0xffa7754c, 0x759ef5e4, 0x3012969c, 0x182f120e, 
+    0x90179c75, 0x44e03d04, 0x0580f001, 0x400490e4, 0x20a575f0, 0x75ffa675, 0x9a75dfa7, 0x89071210, 
+    0x0d600164, 0xe00a0490, 0x0712f004, 0x80077f4c, 0x8404900d, 0x600164e0, 0x4c071208, 0x3612067f, 
+    0x48049070, 0x90e20302, 0x64e08304, 0x90107002, 0x60e04004, 0x6a30120a, 0x0712027f, 0x907a807c, 
+    0xb4e04004, 0x6a500021, 0xf8070390, 0x02732828, 0x03027b03, 0xbe0602d7, 0x02fb0302, 0x0302fb03, 
+    0x060402fb, 0x02060402, 0x06028e04, 0xf10402d0, 0x020b0502, 0x05021605, 0x09060256, 0x02360602, 
+    0x04024106, 0xf90602a0, 0x02e20502, 0x05022105, 0x6a030221, 0x02210502, 0x05022105, 0x21050221, 
+    0x02210502, 0x05022105, 0x2b060221, 0x02ba0502, 0x3012ba05, 0x0712ff6a, 0x4c2f127c, 0x75ffa775, 
+    0x1222199a, 0x04906a30, 0xfe54e03d, 0x7eff7ff0, 0x7cff7dff, 0xa95b12ff, 0x90b25f12, 0x60e03f04, 
+    0x02049011, 0x900670e0, 0x70e03e04, 0x3c341205, 0x2f120680, 0x355c1278, 0x7d200712, 0x121a7f01, 
+    0x07127036, 0x7f017d36, 0x70361219, 0x7540a575, 0xa775ffa6, 0x109a75bf, 0x90890712, 0x90f08304, 
+    0x64e08304, 0x90076007, 0x01744004, 0x049022f0, 0x0f70e002, 0xe03e0490, 0x04900960, 0xf0107440, 
+    0x12410602, 0x64efdf45, 0x02037002, 0x58121f07, 0x0264ef4c, 0x07020370, 0x4904901f, 0x020360e0, 
+    0x2f12a004, 0xce077866, 0x13ce13c3, 0xe020f9d8, 0x57049077, 0xfff01e74, 0x12b95c12, 0x0090565e, 
+    0x1c70e05f, 0x78662f12, 0x13c3ce02, 0xf9d813ce, 0x30200490, 0x228002e0, 0x74a3f0e4, 0x2080f01e, 
+    0x78662f12, 0x13c3ce02, 0xf9d813ce, 0x30200490, 0xf0e408e0, 0xf00574a3, 0xf0e40680, 0xf01474a3, 
+    0x5d12097f, 0x755a127f, 0xef560490, 0xc85f12f0, 0x74400490, 0x6012f008, 0x0370ef90, 0x121f0702, 
+    0x0490135b, 0xe560e04d, 0x480490e4, 0x4a0490f0, 0x4a0490f0, 0x0494c3e0, 0x05020340, 0x41049088, 
+    0x602464e0, 0x25b4e004, 0x4a04900b, 0x700164e0, 0x88050203, 0xe0490490, 0x2f121570, 0xce077866, 
+    0x13ce13c3, 0xe020f9d8, 0x0490e406, 0x9005805c, 0x01745c04, 0x5e0490f0, 0x903a12f0, 0x700264ef, 
+    0x1f070203, 0xe05c0490, 0x900801b4, 0x64e05e04, 0x126f6001, 0x64efd956, 0x02037002, 0x52121f07, 
+    0x0264efec, 0x07020370, 0x6330121f, 0x120ce030, 0x07601530, 0xbf895512, 0x12220c02, 0x64ef8c46, 
+    0x02037002, 0x04901f07, 0x7670e07b, 0xe05c0490, 0x740502b4, 0x1180f001, 0xe05c0490, 0x35120b70, 
+    0x0264ef5c, 0x07020370, 0x5c04901f, 0x700164e0, 0x5e049093, 0x0502b4e0, 0x80f00174, 0xfc1f1287, 
+    0x30128280, 0x90096015, 0x04e04a04, 0xa90402f0, 0xe0490490, 0x2f124070, 0xce027866, 0x13ce13c3, 
+    0xe030f9d8, 0x00049031, 0x54f8c4e0, 0xe0a3c8f0, 0x64452f12, 0x901f6002, 0xffe08704, 0x200f54c4, 
+    0x231214e0, 0x0264eff3, 0x07020370, 0x7b04901f, 0x020360e0, 0x04902105, 0x1c60e089, 0xe0410490, 
+    0x14602764, 0x74400490, 0x2d12f013, 0x4104909f, 0x602764e0, 0x1f070203, 0x60153012, 0x662f1225, 
+    0xc3ce0778, 0xd813ce13, 0x16e020f9, 0x5d0490e4, 0x634a12f0, 0x700264ef, 0x1f070203, 0xe05d0490, 
+    0x6012ef60, 0x1660ef9c, 0x60153012, 0x40049011, 0x12f01e74, 0x64ef8848, 0x02037002, 0x3b121f07, 
+    0x0264ef90, 0x07020370, 0x121a7f1f, 0x54efb160, 0x12737001, 0xa475782f, 0x7b2f1220, 0xc3625c12, 
+    0xff9fff74, 0xfe9eff74, 0xfd9dff74, 0xfc9cff74, 0x2c120378, 0x8e0d8fbb, 0x8c0b8d0c, 0xfeffe40a, 
+    0xabfc017d, 0xa90caa0d, 0xc30aa80b, 0x40aa2c12, 0x7fff7e06, 0xae0480ff, 0x900daf0c, 0xf0ee1204, 
+    0x90f0efa3, 0x04e00c04, 0x3e0490f0, 0x7df00174, 0x120e7f02, 0x90e47036, 0x90f08504, 0xf0044804, 
+    0x04400490, 0x049022f0, 0x13ffe07f, 0x303f5413, 0x049015e0, 0x0870e049, 0xefda4e12, 0x47600264, 
+    0xe07f0490, 0x7ff0fb54, 0x0a60121f, 0x74400490, 0xa475f012, 0x7fa67580, 0x907e2f12, 0xff748304, 
+    0x480490f0, 0x12f00174, 0x60ef9060, 0x0804901a, 0x13c4ffe0, 0x01541313, 0x90d7e020, 0x01744c04, 
+    0x5a5d12f0, 0x22a00402, 0xe0000490, 0x12017dff, 0x0490803c, 0xffe0a300, 0x3c12017d, 0x00902280, 
+    0x7dffe050, 0x803c1201, 0xa3500090, 0x017dffe0, 0x22803c12, 0x60121d7f, 0x0754efb1, 0xf5000e75, 
+    0x027dff0f, 0x7d803c12, 0x187d2202, 0x6012d17f, 0x1313ef78, 0x7d223f54, 0x12ffe496, 0x54ef7860, 
+    0x2213c303, 0x3c12027d, 0x7f027d80, 0x70361215, 0x121e7f22, 0x13efa760, 0x1f541313, 0xb1601222, 
+    0x220154ef, 0x0015b4ef, 0x0d020340, 0xac07905f, 0x732828f8, 0x02eb0702, 0x0d02f507, 0x5f0d025f, 
+    0x023b0802, 0x09029c08, 0x140a02e2, 0x023c0a02, 0x0a024e0a, 0x9e0a0259, 0x02de0a02, 0x0d020a0b, 
+    0x3f0b025f, 0x02fe0b02, 0x0c02b90c, 0x670c02e7, 0x124d0d02, 0x13127f15, 0x6f131275, 0x7f0d1222, 
+    0x14ef3c70, 0x60141260, 0x70022417, 0x48049031, 0x020370e0, 0x00805f0d, 0x74110490, 0x70090201, 
+    0xe4e51512, 0xf0110490, 0x7f5a5d12, 0xb160121a, 0x700154ef, 0x110a0203, 0x02d01312, 0x017f110a, 
+    0x12310c02, 0x59707f0d, 0x2c6014ef, 0x14376014, 0x03244060, 0x90d34b70, 0x94e05300, 0x52009000, 
+    0x400094e0, 0x73141205, 0x60123480, 0xa4f5ef4f, 0xee4f6012, 0x2680a5f5, 0xefee5d12, 0x5d12a4f5, 
+    0xa5f5eeee, 0x33af1880, 0xf5ed07ad, 0xa5f5e4a4, 0x5c120c80, 0xa4f5ef62, 0xee625c12, 0x9a75a5f5, 
+    0x110a020e, 0x60120d7f, 0xe4007ea7, 0x0d020360, 0xfe24ef5f, 0x70147a60, 0x4a090203, 0x02037014, 
+    0x70147409, 0xa7090203, 0x02036014, 0x14125f0d, 0xef074067, 0x02ffc044, 0x1412310c, 0x7f0540e4, 
+    0x310c02d2, 0xe0480490, 0x13120870, 0x02035082, 0x13125f0d, 0x40007f82, 0x90017f02, 0xf0ef4e04, 
+    0x60120e7f, 0x2404902f, 0xefa3f0ee, 0xec3f12f0, 0x15e5158f, 0x400094d3, 0x4415e508, 0x0c02ff60, 
+    0x11049031, 0x12f00574, 0x9a757014, 0x110a020e, 0xe0480490, 0x13120870, 0x02035082, 0x04905f0d, 
+    0x0490e011, 0x0490f04e, 0xf0017411, 0x02de5f12, 0x1512110a, 0x110490e5, 0x0194d3e0, 0x13120840, 
+    0x0090e42e, 0x6012f065, 0xec14123f, 0x0240007f, 0x0490017f, 0x00151211, 0x110a02f0, 0x40671412, 
+    0x26151206, 0x12310c02, 0x0540e414, 0x0c02d27f, 0x48049031, 0x120870e0, 0x03508213, 0x125f0d02, 
+    0x007f7c13, 0x017f0240, 0x74341512, 0x12318002, 0x06406714, 0x02261512, 0x1412310c, 0x7f0540e4, 
+    0x310c02d2, 0xe0480490, 0x13120870, 0x02035082, 0x13125f0d, 0x40007f7c, 0x12017f02, 0x03743415, 
+    0x725712f0, 0x02c85f12, 0x0d12640c, 0xc314f560, 0x007e8094, 0x0950017b, 0xf92f0074, 0x800434ee, 
+    0x25807408, 0x34eef914, 0x2c12fa04, 0xf5128e35, 0x1213e513, 0x9a75f813, 0x640c020e, 0xf5600d12, 
+    0x980d1214, 0x94c314e5, 0x7c14e580, 0x50017b00, 0xec151207, 0x0680effa, 0xfaf31512, 0x2c1213e5, 
+    0x640c0270, 0xfa670d12, 0x8e352c12, 0xf6131212, 0x020e9a75, 0x0d12640c, 0x1207c098, 0x0b02670d, 
+    0x780d1236, 0x94c314f5, 0xef155080, 0x7b007cfd, 0xec151201, 0x74f61412, 0xecf92d01, 0x14800434, 
+    0x7cfd14e5, 0x12017b00, 0x1412f315, 0x2d8174f6, 0x0434ecf9, 0x352c12fa, 0xe5e41342, 0xf8131213, 
+    0x020e9a75, 0x0d12640c, 0x780d12a3, 0x94c314f5, 0xff12e580, 0x7cfd14e5, 0x50017b00, 0xec151211, 
+    0x2c12effa, 0x2d017470, 0x0434ecf9, 0x15120f80, 0x12effaf3, 0x8174702c, 0x34ecf92d, 0x13e5fa04, 
+    0x02702c12, 0x0d12640c, 0xfd14f588, 0x017b007c, 0xecf95024, 0x14120034, 0x2d5174f6, 0x0034ecf9, 
+    0x352c12fa, 0xe5e41342, 0xf8131213, 0x020e9a75, 0x0d12640c, 0xff12e5a3, 0x0d1207c0, 0x7b007e88, 
+    0xf9502401, 0xfa0034ee, 0x2c12e0d0, 0xc013af70, 0xad0d1207, 0x017b007e, 0xeef95124, 0xd0fa0034, 
+    0x702c12e0, 0x904b0d02, 0xd3e01104, 0x03400194, 0x7ffa0b02, 0xa760120d, 0x60e4007e, 0x5f0d0203, 
+    0x3e6014ef, 0x02037014, 0x0224ed0b, 0x0d020360, 0x7ffde45f, 0x70361211, 0x74650090, 0x0090f001, 
+    0xa3fee05a, 0x704effe0, 0x7d027c0a, 0x7f027ef7, 0x120380f7, 0x00901d15, 0xa3f0ee58, 0xffe4f0ef, 
+    0x00905d80, 0xa3fee058, 0x24017be0, 0x0174f900, 0x2c12fa3e, 0xf3131235, 0x900e9a75, 0xfee05a00, 
+    0x90ffe0a3, 0xb5e05800, 0xe0a30906, 0x7f0407b5, 0xe4028001, 0x695f12ff, 0xe0580090, 0xffe0a3fe, 
+    0x7e06704e, 0x80f77f02, 0x1d151203, 0xee580090, 0xf0efa3f0, 0x0090e422, 0x1312f065, 0x02017f2f, 
+    0x557f695f, 0x14123380, 0x900f4067, 0xc4e06500, 0x4044f054, 0xff4eeffe, 0x0d121f80, 0x12e230ad, 
+    0x648f0d12, 0x120b6001, 0x54c48f0d, 0xff8044f0, 0x14120780, 0x7f0540e4, 0x305f02d2, 0xe0480490, 
+    0x13120870, 0x02035082, 0x13125f0d, 0x40007f7c, 0x12017f02, 0x04743415, 0x120d7ff0, 0x90efa760, 
+    0x12f01704, 0x14128238, 0x0e9a7570, 0x124b0d02, 0x1312e515, 0x0090e42e, 0x1512f065, 0xef2a40bb, 
+    0x901ee120, 0xffe07804, 0x12c36012, 0x14125213, 0x79049052, 0x6012ffe0, 0x521312c3, 0x80591412, 
+    0x45049008, 0x5512ffe0, 0x3f6012e1, 0xf0021512, 0x128a1312, 0x007fec14, 0x017f0240, 0x80110490, 
+    0x9e12122a, 0x930174fe, 0x12160490, 0x12e0e012, 0x9a75f313, 0x1604900e, 0x94c3ffe0, 0x7e0640ff, 
+    0x80007f00, 0xff04ef03, 0xef160490, 0x127580f0, 0x74fe9e12, 0x90ff9301, 0xf9e01604, 0xe0e21212, 
+    0x94c3e9fd, 0x790440ff, 0x90068000, 0x04e01604, 0x160490f9, 0x9d1212e9, 0x930174fe, 0x7afbe9ff, 
+    0xff2bef00, 0xe91212ea, 0x001275e0, 0xc3e913f5, 0x0440ff94, 0x0680007f, 0xe0160490, 0x0490ff04, 
+    0xaff0ef16, 0xf513e505, 0x1245eda4, 0xa5f5eefe, 0x800e9a75, 0xb353120f, 0x12a4f5ef, 0xf5eeb353, 
+    0x0e9a75a5, 0x22f45f12, 0x60120d7f, 0x7f22efa7, 0xa760120d, 0x7b007eef, 0xf9502401, 0x220034ee, 
+    0x60120d7f, 0x7f22efa7, 0xa760120d, 0x22e4007e, 0x60120d7f, 0x7f22efa7, 0xb16012d9, 0x220154ef, 
+    0x60120e7f, 0x0012752f, 0x7f22138f, 0x2f60120e, 0x138f128e, 0x120d7f22, 0x22efa760, 0x7580a575, 
+    0xa775ffa6, 0xf5e4227f, 0xf3a675a4, 0x75ffa775, 0x9022309a, 0xfce01c04, 0x90fde0a3, 0x90e04e04, 
+    0xe0fb1e04, 0xe0a320f5, 0x752221f5, 0xa67530a5, 0x8fa775ff, 0x22309a75, 0x75ffa675, 0x9a75c1a7, 
+    0x0490222b, 0xa3fee000, 0x220278e0, 0x9414e5d3, 0x6413e500, 0x229f9480, 0xff3f54ef, 0x207d007e, 
+    0xec22007c, 0xe09533ff, 0xa4f5effe, 0x22a5f5ee, 0xe0600490, 0x7e007afb, 0xd65e1200, 0xe0610490, 
+    0x049022fb, 0xa3fee01c, 0x33eeffe0, 0xfcfde095, 0x2c120a78, 0xa904a8ce, 0xab06aa05, 0xfee0a307, 
+    0xeeffe0a3, 0xfde09533, 0xf0ef22fc, 0x6412e5d3, 0x22809480, 0x7504a575, 0xe422ffa6, 0xa675a5f5, 
+    0xa57522ff, 0xffa67510, 0x75efa775, 0x8522049a, 0x1b85231c, 0x211a8522, 0x90201985, 0xf5e05104, 
+    0x28188524, 0x85271785, 0x15852616, 0x29138525, 0x902a1485, 0xf5e04f04, 0xfee0222b, 0xd3ffe0a3, 
+    0x64ee0094, 0x22809480, 0x13effe13, 0xa3f0eeff, 0xf022f0ef, 0xf0a3f0a3, 0xf0a3f0a3, 0xffa77522, 
+    0x22159a75, 0xe04c0490, 0x220164ff, 0x0490e0a3, 0x0490f04e, 0x0490e062, 0x0490f04d, 0xa3ffe01c, 
+    0xf0cfa3e0, 0x22f0efa3, 0x75a4f5ef, 0x7522e0a6, 0xa67520a5, 0x18af22ff, 0xe09533ef, 0x75a4f5ef, 
+    0xef22c0a6, 0x13133f54, 0x221f5413, 0x0490ffe0, 0xa3fce024, 0x9022fde0, 0x13e00f04, 0x1f541313, 
+    0xe7a2ce22, 0x2213ce13, 0x75fea775, 0x90222b9a, 0xffe05004, 0x948064d3, 0xf5e42280, 0x02a575a4, 
+    0x757fa675, 0x9a75fca7, 0x04902204, 0x90ffe053, 0xd3e05604, 0x0490229f, 0x0490f053, 0xf0a3f020, 
+    0xf0200490, 0xd322f0a3, 0x948064ed, 0x25ef2280, 0xf5e025e0, 0xffa675a5, 0xffa77522, 0x22319a75, 
+    0x0490eeff, 0xefa3f024, 0xf5ee22f0, 0xc0a675a4, 0x01541322, 0xa4f5e025, 0x75fda675, 0xe522ffa7, 
+    0xffe02514, 0xfe3313e5, 0x02a57522, 0x75ffa675, 0x9a75f8a7, 0xfee02201, 0xc3ffe0a3, 0xe4ff9fe4, 
+    0xef22fe9e, 0x220490f0, 0x9022e0a3, 0xc3e05604, 0x90222a94, 0x1f745704, 0x5c12fff0, 0x1e0490b9, 
+    0xa3f08074, 0x7522f0e4, 0x9a75ffa7, 0xa5752204, 0xffa67508, 0x75f7a775, 0xee22049a, 0xf88064c3, 
+    0x988064ef, 0xe0fcf422, 0xe0a3fc5c, 0x4eecfd5d, 0xff4fedfe, 0x1f54ef22, 0x22007eff, 0x7580a475, 
+    0xa7757fa6, 0x109a75ff, 0xf01ae522, 0xf0a31be5, 0xe0620490, 0x0490e022, 0xf5e0fb1e, 0xf5e0a320, 
+    0x4feb2221, 0xfe4eeaff, 0xe8fd4de9, 0x24effc4c, 0x049022f1, 0x04f4e050, 0x33ef22ff, 0xf8543333, 
+    0x25ef22f0, 0xf5d524e0, 0x6234e482, 0x017483f5, 0xeeff2293, 0xeffe8355, 0xe5ff8255, 0xe5fdf482, 
+    0xf5ef2283, 0x64edc3a4, 0x22809480, 0xf0400490, 0x7522007f, 0xa67520a4, 0xf0ff22c0, 0xe4220490, 
+    0xf0efa3f0, 0xc85f1222, 0x22400490, 0x270490d3, 0x90f894e0, 0x64e02604, 0x22809480, 0xe0450490, 
+    0xe09533ff, 0xffee22fe, 0xefe09533, 0xefe09533, 0xa4fff075, 0xa3f0fe22, 0xeec3f0ef, 0x80948064, 
+    0x1c049022, 0xefa3f0ee, 0xefc322f0, 0xeef88064, 0x22988064, 0x85221485, 0x13852315, 0xac1bad24, 
+    0x54ef221a, 0x1313c47f, 0xf0220354, 0xe04b0490, 0xef22f004, 0x13130f54, 0x94c33f54, 0x0094e402, 
+    0x20049022, 0xefa3f0ee, 0x049022f0, 0x0490f040, 0xf0ff7483, 0x04903e22, 0xefa3f022, 0x049022f0, 
+    0xf0017462, 0x4d049022, 0x22f00174, 0xe09533ff, 0x7522effe, 0x9a75fba7, 0xa4752204, 0x80a67501, 
+    0xfba77522, 0x22309a75, 0x838e828f, 0xaeeb05af, 0x0807a802, 0x8064d322, 0x8064edf8, 0xa4752298, 
+    0xfea67501, 0x4c049022, 0x220164e0, 0xe0290490, 0x0490f02f, 0xf03ee028, 0x6d049022, 0x0490ffe0, 
+    0xff2fe050, 0x0090fe22, 0x909fe057, 0x9ee05600, 0xf8806422, 0x988064eb, 0x82e5d322, 0x83e50094, 
+    0x80948064, 0x21e5d322, 0x20e50094, 0x80948064, 0x60049022, 0x007afbe0, 0xc3e0ff22, 0xd312f59f, 
+    0x78948064, 0x0354ee22, 0xf01e0490, 0x22f0efa3, 0x641de5c3, 0x22809480, 0xe0070490, 0x131313fe, 
+    0x90221f54, 0xffe00904, 0x54131313, 0xf5ef221f, 0x80a675a4, 0xffa77522, 0x22339a75, 0x75ffa775, 
+    0x7522469a, 0x9a75ffa7, 0xa4752245, 0xdfa67520, 0x95e4c322, 0x95e4ff82, 0xc322fe83, 0xff2195e4, 
+    0xfe2095e4, 0x0124cf22, 0xa20034cf, 0xef2213e7, 0x13c43f54, 0x01640754, 0x2519e522, 0x18e5ffe0, 
+    0x9022fe33, 0xfee02004, 0x049022a3, 0xf0a3f028, 0x40049022, 0x22007ff0, 0xe0520490, 0x948064c3, 
+    0x04902280, 0xf075f077, 0xa433e502, 0x82f52924, 0x6434f0e5, 0x93e483f5, 0xa5f5e422, 0x22ffa675, 
+    0xe0380490, 0xffe0a3fe, 0x78fdfce4, 0xce2c1210, 0x05a904a8, 0x07ab06aa, 0xa3fee0a3, 0x4febffe0, 
+    0x0174fe22, 0x77049093, 0x7cfde0ff, 0xff2def00, 0x74fe3eec, 0x82f52f00, 0xf53e0174, 0x33ee2283, 
+    0xfcfde095, 0x2c020a78, 0xa4f5e4ce, 0x75dfa675, 0x9a75ffa7, 0x74fc2211, 0x90fd9301, 0xfee07704, 
+    0xed007afb, 0x3ceafd2b, 0x2d0074fc, 0x017482f5, 0xef83f53c, 0x90e422f0, 0xa3f05a00, 0x580090f0, 
+    0x7ef0a3f0, 0xfdf87f02, 0x017a017b, 0x2d020079, 0x12f17f1b, 0x33efc360, 0xf5efe095, 0xc0a675a4, 
+    0x38049022, 0xa3f0a3f0, 0x22f0a3f0, 0xff3f54ef, 0x207d007e, 0x7522007c, 0xa67580a4, 0xffa7757f, 
+    0x220d9a75, 0x74650090, 0x0490f001, 0x94d3e011, 0xa4752200, 0xf7a67508, 0x75ffa775, 0x7522409a, 
+    0xa67510a5, 0xefa775ff, 0x22049a75, 0x75a4f5e4, 0x9022c0a6, 0x54e01704, 0x0094d301, 0x00049022, 
+    0xe0a3fee0, 0x90220278, 0xfee02404, 0xc3ffe0a3, 0x64eef094, 0x227f9480, 0x7520a475, 0xa775dfa6, 
+    0x109a75ff, 0x25effe22, 0x33eeffe0, 0x0224effe, 0x903ee4ff, 0xa3f02404, 0x7522f0ef, 0x13f50012, 
+    0x12e5a4f5, 0x9022a5f5, 0xffe06100, 0xfefdfce4, 0xabce2c12, 0xa926aa27, 0xd324a825, 0xffaa2c02, 
+    0xe9fe4eea, 0xeffce8fd, 0xeeff1525, 0xedfe1435, 0xecfd1335, 0x22fc1235, 0xaa28abfc, 0xa826a927, 
+    0xaa2c0225, 0xe0780490, 0xeff88064, 0x22988064, 0x75a4f5e4, 0xa775fda6, 0xa77522ff, 0x449a75ff, 
+    0xffa77522, 0x22439a75, 0x75a4f5e4, 0x9022fea6, 0xffe01104, 0x220194d3, 0xe0240490, 0xf5e0a3fe, 
+    0xa5f5eea4, 0x24049022, 0xa3f0ff74, 0x22f0e174, 0x270490c3, 0x900494e0, 0x64e02604, 0x7d809480, 
+    0x04902200, 0xa3fee026, 0x94c3ffe0, 0x8064ee04, 0xfe228094, 0x16abfcfd, 0x14a915aa, 0x02c313a8, 
+    0xefd3aa2c, 0x64ee0f94, 0x22809480, 0x250490c3, 0x901f94e0, 0x64e02404, 0x22809480, 0xe0260490, 
+    0xa313e7a2, 0x015413e0, 0x22017dff, 0xe0490490, 0x220194d3, 0xe04e0490, 0x948064d3, 0x12fa2280, 
+    0x1375352c, 0x2212f500, 0x90e4f0ef, 0xa3f01404, 0x04904f22, 0xf0eeff14, 0x22f0efa3, 0x33ef18af, 
+    0xeffee095, 0xff24ef22, 0xff34eeff, 0x009022fe, 0x54c4e065, 0xfec044f0, 0x22ff4eef, 0xef4e0490, 
+    0x110490f0, 0xfc805422, 0xf9fafbe4, 0x2c02c3f8, 0x04a575aa, 0x22ffa675, 0x7508a575, 0x9022ffa6, 
+    0xf0e42404, 0xa57522a3, 0xffa67502, 0xaa29ab22, 0x222ba92a, 0x14aa15ab, 0x12a813a9, 0xaa2c02d3, 
+    0x75ffa775, 0xe422309a, 0xa675a4f5, 0x049022bf, 0x54c4e017, 0x00902203, 0x13c3e050, 0x5413e0a3, 
+    0x0490221f, 0x94c3e015, 0x0094e4fb, 0x17049022, 0x0254ffe0, 0x220094d3, 0xa3260490, 0xff0154e0, 
+    0x9022fde4, 0xffe01704, 0x94d30454, 0x74fc2200, 0x90fd9301, 0x22e07704, 0x75a4f5e4, 0xe422efa6, 
+    0xe5fdfeff, 0x60122225, 0x790490cb, 0x3f049022, 0x22f00174, 0xecf90024, 0x24220434, 0x34ecf980, 
+    0x14122204, 0xffa77560, 0x12919a75, 0xa775b112, 0x019a75f8, 0x12d01512, 0x14127815, 0xffa77560, 
+    0x12039a75, 0xa7756014, 0x619a75ff, 0x75481412, 0xf5e4519a, 0x75a5f5a4, 0xf5e4609a, 0x80a675a4, 
+    0x75ffa775, 0x1412499a, 0x219a7548, 0x75b11212, 0x9a757fa7, 0xb1121221, 0x75f3a775, 0x1212219a, 
+    0x9fa775b1, 0x12219a75, 0xa775a413, 0x229a75ff, 0x75b11212, 0x9a75c0a7, 0x48141222, 0x12239a75, 
+    0xa775b112, 0x239a757f, 0x75b11212, 0x9a75f3a7, 0xb1121223, 0x759fa775, 0x1312239a, 0xffa775a4, 
+    0x12249a75, 0xa775b112, 0x249a75c0, 0x75b11212, 0x9a757fa7, 0xb1121225, 0x75f3a775, 0x1212259a, 
+    0x9fa775b1, 0x12259a75, 0xa775a413, 0x269a75ff, 0x75b11212, 0x9a75c0a7, 0xb1121226, 0x757fa775, 
+    0x1212279a, 0xf3a775b1, 0x12279a75, 0xa775b112, 0x279a759f, 0x75a41312, 0x9a75ffa7, 0xb1121228, 
+    0x75c0a775, 0x1212289a, 0x7fa775b1, 0x12299a75, 0xa775b112, 0x299a75f3, 0x75b11212, 0x9a759fa7, 
+    0xa4131229, 0x75ffa775, 0x12122a9a, 0xc0a775b1, 0x122a9a75, 0xa775b112, 0x209a757f, 0x75b11212, 
+    0x9a75bfa7, 0xa4131220, 0x12521412, 0x1412a413, 0xa4131259, 0x75ffa775, 0x1312489a, 0xffa775a4, 
+    0x12479a75, 0xa775a413, 0x469a75ff, 0x75a41312, 0x9a75ffa7, 0xb1121245, 0x757fa775, 0x12122b9a, 
+    0xc1a775b1, 0xe42b9a75, 0xa5f5a4f5, 0x75fea775, 0x15122b9a, 0xd613127f, 0x7534a575, 0xa775ffa6, 
+    0x149a7583, 0x750da475, 0xa775e0a6, 0x159a75ff, 0x12a4f5e4, 0x14128d13, 0x90131260, 0x75a4f5e4, 
+    0xa775f8a6, 0x429a75ff, 0x75a4f5e4, 0xa775f0a6, 0x419a75ff, 0x75b11212, 0x9a75f7a7, 0xb1121204, 
+    0xe49d1312, 0xa675a4f5, 0xffa77580, 0x12049a75, 0xa775b112, 0x049a75fb, 0xf5a4f5e4, 0x7fa675a5, 
+    0x75fca775, 0xf5e4049a, 0x83a675a4, 0x75ffa775, 0x1212339a, 0x87a775b1, 0xe4339a75, 0xa5f5a4f5, 
+    0x757fa675, 0x9a75f8a7, 0xb1121233, 0x757fa775, 0x1212339a, 0x7fa775b1, 0x12309a75, 0xa775b112, 
+    0x309a758f, 0x75b11212, 0x9a75fba7, 0xa4f5e4d1, 0x12dfa675, 0x15127815, 0x071312d0, 0xe4011312, 
+    0xa675a4f5, 0x7815123f, 0x75b11212, 0x9a75fba7, 0xb1121230, 0xe4319a75, 0xa775a4f5, 0x319a75ff, 
+    0x75b11212, 0x9a75fda7, 0xb1121230, 0x75f7a775, 0x1212309a, 0x329a75b1, 0x75a4f5e4, 0x1512f3a6, 
+    0xa4f5e478, 0x75ffa775, 0x1412329a, 0xffa77560, 0x12339a75, 0x9a754814, 0xb1121233, 0x75bfa775, 
+    0xf5e4109a, 0x7fa675a4, 0x22d61312, 0x901af5e4, 0x30e01404, 0x1b0203e7, 0x20a4754c, 0x90041312, 
+    0x70e04904, 0x1b12fb06, 0x124f804d, 0x0540bf13, 0x40ba1412, 0x17049007, 0x14e120e0, 0x6012347f, 
+    0xf612122f, 0x05c004c0, 0x07c006c0, 0x1280357f, 0x6012367f, 0xf612122f, 0x05c004c0, 0x07c006c0, 
+    0x6012377f, 0xd003d0b1, 0xd001d002, 0xf54feb00, 0x14f5ea15, 0xe813f5e9, 0x007b12f5, 0x1679007a, 
+    0x75a25112, 0x1c8f001b, 0x12b81212, 0x15121714, 0x7408406c, 0xfdfeffff, 0x120680fc, 0x1412b812, 
+    0x8e158f17, 0x8c138d14, 0x641ce512, 0x601b4501, 0x2404900a, 0xa30270e0, 0x122e70e0, 0x1ae55d1b, 
+    0x017f0470, 0x007f0280, 0x3333c4ef, 0x8044c054, 0xc41ce5fc, 0x4ce05433, 0x770490fe, 0xffedfde0, 
+    0xee140490, 0xf0efa3f0, 0x62009022, 0xfce4ffe0, 0x0478fefd, 0x12ce2c12, 0x03506c15, 0xe4101b02, 
+    0xfd277eff, 0xaa19abfc, 0xa817a918, 0x2c12d316, 0xe41f50aa, 0x077ecc7f, 0x16a8fcfd, 0x50aa2c12, 
+    0x101b0203, 0xe0170490, 0x94d34054, 0x02035000, 0x1b12101b, 0xab13125d, 0x04901e40, 0xa3fee024, 
+    0x64eeffe0, 0x50809480, 0x0124ef09, 0xfe3ee4ff, 0x007e2180, 0x1b80007f, 0xe0240490, 0xffe0a3fe, 
+    0xee0094d3, 0x80948064, 0x15120540, 0x7e04801d, 0x90007f00, 0xf0ee2404, 0x12f0efa3, 0x5c40a515, 
+    0xe0490490, 0x54ef5160, 0x0094d304, 0x47800240, 0x40ab1312, 0x24049021, 0x0470f4e0, 0xf064e0a3, 
+    0xc17f0f70, 0x7fd65812, 0xd6581201, 0x80491512, 0x9713121e, 0x04902180, 0x0470e024, 0x0f64e0a3, 
+    0x3f7f1270, 0x7fd65812, 0xd65812ff, 0x75491512, 0x7080329a, 0x12971312, 0x68809713, 0x40bb1512, 
+    0x54c4ef5a, 0x2b601403, 0x14356014, 0x03243f60, 0x14125270, 0xee0a409a, 0xef13e7a2, 0x80007e13, 
+    0x90007e06, 0x54e02704, 0x1412ff01, 0x7d024088, 0x12238001, 0x007fab13, 0x017f0240, 0x1680fde4, 
+    0x7fab1312, 0x7f024000, 0x80017d01, 0xd4141209, 0x12884112, 0x4112b015, 0x90098088, 0xe0a32404, 
+    0xb95c12ff, 0xe4775e12, 0x12591312, 0x007bc85f, 0x124d1b12, 0x23800113, 0x14ae15af, 0x12ac13ad, 
+    0x2c121078, 0x380490bb, 0xefa3f0ee, 0x14e5a3f0, 0x15e5a3f0, 0xc85f12f0, 0x90011312, 0xe0a32404, 
+    0x1bf57f54, 0x90001c75, 0xffe07704, 0xe5fe1be5, 0x0915121c, 0x79007a22, 0x1452121a, 0x148e158f, 
+    0x128c138d, 0x00207522, 0x75002175, 0x007b1622, 0x1279007a, 0x222b4912, 0x1a75128f, 0x49049003, 
+    0x120660e0, 0x027f5d11, 0x15f5e422, 0x14f513f5, 0x18f517f5, 0x16f519f5, 0x6012387f, 0xf910122f, 
+    0x6012397f, 0xfd11122f, 0x909b5f12, 0xf0ef5104, 0x02b412e5, 0x6f049005, 0x12e51b80, 0x900503b4, 
+    0x11807004, 0x01b412e5, 0x71049005, 0x12e50780, 0x04900670, 0x16f5e072, 0x0490fde4, 0x0270e01c, 
+    0x1470e0a3, 0x121e0490, 0x2240b20e, 0x90e7a2ee, 0x0e121e04, 0xec800dc0, 0x04900a7d, 0xb20e121c, 
+    0xa2ee0c40, 0x1c0490e7, 0x0dc00e12, 0x24edec80, 0x1215f5fc, 0x07786411, 0x33ce33c3, 0x78f9d8ce, 
+    0x390f1203, 0xacfdfbd8, 0x22049006, 0xe0a3fee0, 0xc3ce0378, 0xd813ce13, 0xf59dc3f9, 0xf59cee14, 
+    0xb412e513, 0x0e120702, 0x80024004, 0xb412e521, 0x0e120703, 0x80024004, 0xb412e515, 0x0e120701, 
+    0x80024004, 0x7012e509, 0x040e120b, 0x13750640, 0x0014751f, 0x13ae14e5, 0x33c30378, 0xd8ce33ce, 
+    0x230490f9, 0x0490eef0, 0x16e5f022, 0xa408f075, 0x1425f0ae, 0x35ee14f5, 0xe513f513, 0x0702b412, 
+    0x40040e12, 0xe5218002, 0x0703b412, 0x40040e12, 0xe5158002, 0x0701b412, 0x40040e12, 0xe5098002, 
+    0x120b7012, 0x0640040e, 0x751f1375, 0x13ae0014, 0x037814e5, 0x33ce33c3, 0xf5f9d8ce, 0xe5178e18, 
+    0xfe075417, 0x037818e5, 0xce13c3ce, 0xf5f9d813, 0x6012e516, 0x0b03b403, 0x131317e5, 0xf51f5413, 
+    0xe50d8019, 0x13131317, 0xf0751f54, 0x19f5a4ff, 0x036012e5, 0xd32601b4, 0x806419e5, 0x05409f94, 
+    0x80510490, 0x19e5c32f, 0x61948064, 0x04900550, 0xe5328051, 0x903b6019, 0x80f05104, 0x6412e535, 
+    0xe5056002, 0x2a03b412, 0x6419e5d3, 0x409f9480, 0x50049008, 0x80f01f74, 0x19e5c319, 0x61948064, 
+    0x04900850, 0xf0e17450, 0x19e50880, 0x04900460, 0x1112f050, 0x7012e55d, 0x22049013, 0x0f0490e0, 
+    0x90dc0f12, 0x90f07504, 0x3e807204, 0x01b412e5, 0x22049013, 0x100490e0, 0x90dc0f12, 0x90f07604, 
+    0x26807104, 0x049012e5, 0x1002b422, 0x0d0490e0, 0x90dc0f12, 0x90f07304, 0x0e806f04, 0x0e0490e0, 
+    0x90dc0f12, 0x90f07404, 0x16e57004, 0x22007ff0, 0xf5e4128f, 0x0f157514, 0x12011375, 0x1140640e, 
+    0x6012467f, 0x100e12b1, 0x8ff41f12, 0x80457f16, 0x0e12c32a, 0x7f115065, 0xb1601248, 0x12100e12, 
+    0x168ff41f, 0x1380477f, 0x6012447f, 0x100e12b1, 0xef845f12, 0x8fe09533, 0x12437f16, 0x0e12b160, 
+    0x845f1210, 0xe09533ef, 0x0490178f, 0x0360e053, 0x7f011f02, 0x2f601234, 0x1b8f1a8e, 0xe04e0490, 
+    0x121c0490, 0x1112da0d, 0x1216af0c, 0x188fc140, 0xe0620490, 0x04903f60, 0x0490e04e, 0x5110121c, 
+    0x85221485, 0x18852315, 0xac1bad24, 0x1216af1a, 0x04908a39, 0x620e1251, 0x90e00740, 0x80f06704, 
+    0x0e12c314, 0x51049065, 0x900650e0, 0x80f06504, 0x63049004, 0x4e0490f0, 0x90f016e5, 0x10121c04, 
+    0x53049041, 0x40630e12, 0x0e0f1208, 0x80341212, 0x0e12c31a, 0x120b5065, 0xa7750e0f, 0x489a75ff, 
+    0x0f120980, 0xffa7750e, 0x90449a75, 0x60e06204, 0x640e1238, 0x057d0d40, 0x0e12207f, 0x7f057d28, 
+    0xc3218020, 0x12650e12, 0x0d50e911, 0x027f017d, 0x7d2f0e12, 0x80027f01, 0x7f037d0b, 0x2f0e1208, 
+    0x087f037d, 0x5e12007e, 0x540490f4, 0x020360e0, 0x367fe01f, 0x8e2f6012, 0x901b8f1a, 0x0d124f04, 
+    0x0c1112d6, 0x401217af, 0x90198fc1, 0x60e06204, 0x4f04903b, 0x854d1012, 0x15852214, 0x24198523, 
+    0x1aac1bad, 0x391217af, 0x5004908a, 0x40620e12, 0x0490e007, 0x1480f068, 0x650e12c3, 0xe0500490, 
+    0x04900650, 0x0480f066, 0xf0640490, 0xe54f0490, 0x0490f017, 0x4110121e, 0x12540490, 0x0a40630e, 
+    0x0f1219af, 0x3b121214, 0x12c31e80, 0x0d50650e, 0x0f1219af, 0xffa77514, 0x80479a75, 0x1219af0b, 
+    0xa775140f, 0x439a75ff, 0xe0620490, 0x0e123a60, 0x7d0d4064, 0x12107f04, 0x047d280e, 0x2380107f, 
+    0x650e12c3, 0x50e91112, 0x7ffde40f, 0x0e12fe01, 0x7ffde431, 0x0d80fe01, 0x047f027d, 0x7d2f0e12, 
+    0x7e047f02, 0xf45e1200, 0xe0530490, 0xe0a30860, 0x11120460, 0x90e4225d, 0x22f04d04, 0xef845f12, 
+    0x22e09533, 0x9012f5e4, 0x60e04904, 0x22007f03, 0xe04c0490, 0x900f01b4, 0xffe00804, 0x3f541313, 
+    0x0203e030, 0x0090c821, 0x1770e05f, 0xcefa0d12, 0x13ce13c3, 0x0490f9d8, 0x02e03053, 0x1e741a80, 
+    0x121880f0, 0xc3cefa0d, 0xd813ce13, 0x530490f9, 0x7405e030, 0x0380f005, 0x12f01474, 0x11123e5a, 
+    0xb44c1239, 0x12990f12, 0x0490755a, 0xf5f0ef56, 0x5f009012, 0x020360e0, 0x0d122f21, 0x13c3cefa, 
+    0xf9d813ce, 0x126ae030, 0x0f127b12, 0xecfb2f24, 0xebc3fa3e, 0x94eaa594, 0xc31f5000, 0xecd294ed, 
+    0x80948064, 0xefc31450, 0x94ee7d94, 0x120b5000, 0x0340e30f, 0x02af2102, 0x12129f21, 0xff2de07b, 
+    0xd3fe3eec, 0xeebe94ef, 0x03500094, 0x90af2102, 0x70e07c04, 0x620f120b, 0x21020350, 0xac2102af, 
+    0x50e30f12, 0xf004e003, 0x745e0490, 0x2102f001, 0x240490af, 0xe0a3fee0, 0xa594c3ff, 0x948064ee, 
+    0xc3165080, 0xeed294ef, 0x80948064, 0x0f120b50, 0x020340e3, 0x2102af21, 0x0490d39f, 0xbe94e025, 
+    0xe0240490, 0x80948064, 0x21020350, 0x620f12af, 0x21020350, 0x127d80af, 0xc3cefa0d, 0xd813ce13, 
+    0x57e030f9, 0xe07c0490, 0x04900b60, 0x94c3e056, 0x80025011, 0x7b121252, 0x0490ffe0, 0xfd2fe025, 
+    0xe0240490, 0xedc3fc3e, 0x94ecee94, 0x90165002, 0x70e08204, 0x94efc310, 0x0194ee77, 0x0f120750, 
+    0x800250e3, 0x94edd322, 0x0394ec39, 0x04900650, 0x2360e082, 0x40620f12, 0x9019801e, 0xffe08204, 
+    0x0f120a70, 0xe01050e3, 0x0b80f004, 0x120860ef, 0x0340620f, 0x90f014e0, 0xffe05604, 0x90df5a12, 
+    0xfee05604, 0x08601265, 0xe05e0490, 0x0901b4fd, 0x745e0490, 0x007ff001, 0x95d3ee22, 0xed234012, 
+    0x07600464, 0xe04c0490, 0x900801b4, 0x02745e04, 0x900680f0, 0x03745e04, 0x560490f0, 0x1295c3e0, 
+    0x049022ff, 0x0364e05e, 0x04900760, 0x01b4e04c, 0x5e049008, 0x80f00274, 0x5e049006, 0x90f00474, 
+    0xffe05604, 0x9f12e5c3, 0x22ff04f4, 0x60123b7f, 0x0754efa7, 0xc0007eff, 0x7f07c006, 0xa760123b, 
+    0xfd1b0f12, 0xff2de0d0, 0x0034e0d0, 0xeffe13c3, 0x06c0ff13, 0x3b7f07c0, 0xefb16012, 0xd0fd3f54, 
+    0x13f52de0, 0x0034e0d0, 0x3c7f12f5, 0x12b16012, 0x06c02d10, 0x3c7f07c0, 0x12a76012, 0xd0fd1b0f, 
+    0x1bf52de0, 0x0034e0d0, 0x3c7f1af5, 0x12b16012, 0x01641a11, 0x95c30a70, 0x95e4ff1b, 0x0480fe1a, 
+    0x1baf1aae, 0x178f168e, 0x60123c7f, 0x2d1012b1, 0x07c006c0, 0x60123c7f, 0x0754efa7, 0x2de0d0fd, 
+    0xe0d01df5, 0x1cf50034, 0x60123c7f, 0x671212b1, 0x95c30a70, 0x95e4ff1d, 0x0480fe1c, 0x1daf1cae, 
+    0xff2f17e5, 0xa23e16e5, 0x14f513e7, 0x15f513ef, 0x60123d7f, 0x100e12b1, 0xef845f12, 0xf5e09533, 
+    0xe5198f18, 0xf5192515, 0x3514e51f, 0x121ef518, 0x0f12df23, 0x12fbd839, 0xe0256411, 0xfc33eefd, 
+    0xe5711212, 0xe5cf2f1f, 0x2dcf3e1e, 0xc0fe3ccf, 0x7f07c006, 0x2f60123d, 0x120b78ef, 0xfbd8390f, 
+    0xe09533fd, 0x2de0d0fc, 0x3ce0d0ff, 0x90fc07ad, 0xfae00004, 0xeafbe0a3, 0xf054f8c4, 0x54c4ebc8, 
+    0x0354480f, 0x63700264, 0x7802aeeb, 0x13c3ce02, 0xf9d813ce, 0x1254e030, 0x0f12df23, 0x12fbd839, 
+    0xe0256411, 0xfc33eefd, 0xe02515e5, 0x3314e5ff, 0x2f13e5fe, 0x3e12e5cf, 0xfb1925cf, 0xfa1835ef, 
+    0xeb711212, 0x3eeaff2f, 0x3ccf2dcf, 0xc006c0fe, 0x123d7f07, 0x78ef2f60, 0x390f120b, 0x33fdfbd8, 
+    0xd0fce095, 0xd0fd2de0, 0x90fc3ce0, 0x70e05f00, 0x2513e511, 0x12e5cf1f, 0x24cf1e35, 0x0034cf02, 
+    0x04ae22fe, 0x7f2205af, 0x2f60123d, 0xfe0754ee, 0x047c007d, 0xef845f12, 0x90220678, 0x24e04004, 
+    0x146c60e1, 0x24020370, 0x90008081, 0x70e04904, 0xfa0d120d, 0xce13c3ce, 0x20f9d813, 0x007f03e0, 
+    0x0f12e422, 0x7b049078, 0x600164e0, 0x0490e405, 0x0490f04b, 0x2f60e07c, 0xe0450490, 0x0b24b4ff, 
+    0xe4200490, 0xf004a3f0, 0xef7f2502, 0x64d3dc24, 0x90809480, 0x40e04504, 0x80ff1404, 0x90ff0402, 
+    0xf0ef4504, 0x747f2502, 0xb02512f8, 0x12f01f74, 0x02bfcd4d, 0x22027f03, 0xe0530490, 0x0f12e4ff, 
+    0x1208749a, 0x2074b025, 0xcd4d12f0, 0x7f0302bf, 0x04902202, 0x240f1253, 0xfe9defc3, 0x04909ce4, 
+    0xcea3f024, 0x240490f0, 0xe0a3fee0, 0x9034604e, 0xd3e04b04, 0x03500094, 0xee3d2502, 0x80948064, 
+    0x007e0640, 0x0480017f, 0xff7fff7e, 0x40901212, 0x7d007c06, 0x7c048001, 0xefff7dff, 0xee02706d, 
+    0x9062606c, 0xf0e42004, 0x90f004a3, 0x0e122404, 0x800240b2, 0x24049006, 0x90ce0f12, 0xfde05204, 
+    0x948064d3, 0x80024080, 0x52049007, 0xfd04f4e0, 0xe09533ed, 0x9defd3fc, 0x041112ec, 0x04905e40, 
+    0x0164e07a, 0x10121a60, 0x901212d4, 0x007c0640, 0x0480017d, 0xff7dff7c, 0xecff2fed, 0x3780fe3e, 
+    0x80d41012, 0x7a049032, 0x600164e0, 0x0490c327, 0x8064e024, 0x06408094, 0x017f007e, 0xff7e0480, 
+    0x0490ff7f, 0x33fde045, 0xc3fce095, 0xecff9fed, 0x0380fe9e, 0x90d41012, 0xf0ef4504, 0xa3240490, 
+    0x520490e0, 0x90231112, 0xffe04504, 0x90e15512, 0x70e02004, 0x64e0a304, 0x90116001, 0xc3e04b04, 
+    0x08501094, 0x747b0490, 0x0580f001, 0x7b0490e4, 0x0490e4f0, 0x22fff040, 0xf0460490, 0x735412ff, 
+    0x22400490, 0x60123b7f, 0x0754efa7, 0xc0007eff, 0x7f07c006, 0xa760123b, 0xfd1b0f12, 0xff2de0d0, 
+    0x0034e0d0, 0xeffe13c3, 0x06c0ff13, 0x3b7f07c0, 0xefb16012, 0xd0fd3f54, 0x16f52de0, 0x0034e0d0, 
+    0x3c7f15f5, 0x12b16012, 0x06c02d10, 0x3c7f07c0, 0x12a76012, 0xd0fd1b0f, 0x20f52de0, 0x0034e0d0, 
+    0x3c7f1ff5, 0x12b16012, 0x01641a11, 0x95c30a70, 0x95e4ff20, 0x0480fe1f, 0x20af1fae, 0x1a8f198e, 
+    0x60123c7f, 0x2d1012b1, 0x07c006c0, 0x60123c7f, 0x0754efa7, 0x2de0d0fd, 0xe0d022f5, 0x21f50034, 
+    0x60123c7f, 0x671212b1, 0x95c30a70, 0x95e4ff22, 0x0480fe21, 0x22af21ae, 0xff2f1ae5, 0xa23e19e5, 
+    0x17f513e7, 0x18f513ef, 0x60123d7f, 0x100e12b1, 0xef845f12, 0xf5e09533, 0x7f1c8f1b, 0x2f60123d, 
+    0xfe0754ee, 0x047c007d, 0xef845f12, 0x0f120678, 0xfffbd839, 0xf5e09533, 0x7f1e8f1d, 0x2f60123d, 
+    0x120b78ef, 0xfbd8390f, 0xe09533ff, 0x18e5d3fe, 0x17e50094, 0x80948064, 0x17ac0640, 0x098018ad, 
+    0x1895e4c3, 0x1795e4fd, 0x16e5d3fc, 0x15e50094, 0x80948064, 0x15aa0640, 0x098016ab, 0x1695e4c3, 
+    0x1595e4fb, 0xfd2debfa, 0xd3fc3cea, 0x00941ce5, 0x80641be5, 0x06408094, 0x1cab1baa, 0xe4c30980, 
+    0xe4fb1c95, 0xedfa1b95, 0x3aecfd2b, 0x1ee5d3fc, 0x1de50094, 0x80948064, 0x1daa0640, 0x09801eab, 
+    0x1e95e4c3, 0x1d95e4fb, 0xfd2bedfa, 0xd3fc3aec, 0xb80e12ef, 0x03800240, 0xedd30f12, 0x3eecff2f, 
+    0x128f22fe, 0x387f138d, 0x8e2f6012, 0x12158f14, 0x60ef9c60, 0xb412e510, 0x12750304, 0xb412e505, 
+    0x12750305, 0x2412e504, 0x143860fe, 0x70147b60, 0x16280203, 0x02037014, 0x04243028, 0x28020360, 
+    0x123b7f48, 0x54efb160, 0x07c0ff3f, 0x60123b7f, 0x1b0f12a7, 0x2ee0d0fe, 0xf5e416f5, 0x3f177518, 
+    0x7f4b2802, 0xb160123c, 0x7f1a1112, 0x121f603c, 0x1012b160, 0xc006c02d, 0x123c7f07, 0x0f12a760, 
+    0xe0d0fd1b, 0xe0d0ff2d, 0xff9fe4c3, 0x60122680, 0x2d1012b1, 0x07c006c0, 0x60123c7f, 0x1b0f12a7, 
+    0x2de0d0fd, 0x80e0d0ff, 0x123d7f0b, 0x0e12b160, 0x845f1210, 0x1875168f, 0x1f1775e1, 0x3d7f3580, 
+    0xee2f6012, 0x7dfe0754, 0x12047c00, 0x78ef845f, 0x390f1206, 0x0d80fbd8, 0x60123d7f, 0x0b78ef2f, 
+    0xd8390f12, 0x168ffffb, 0x75f11875, 0x03800f17, 0x9016f5e4, 0x16e54f04, 0xfe0470f0, 0xc31380ff, 
+    0x806416e5, 0x06408094, 0x017f007e, 0xff7e0480, 0xe5c3ff7f, 0xe5ff9f15, 0xadfe9e14, 0x12007c13, 
+    0x148e822c, 0x0490158f, 0x94d3e04b, 0x12224000, 0x1885d30d, 0x23178522, 0x04f413e5, 0x15ad24f5, 
+    0x16af14ac, 0x8fc14012, 0x62049016, 0x4d0490e0, 0xb412e5f0, 0x16e52601, 0xc30f18b5, 0x806414e5, 
+    0x06508094, 0x747c0490, 0xe5d3f001, 0xf8806418, 0x806416e5, 0xe4054098, 0xf07c0490, 0x12af16ad, 
+    0x90822a12, 0x14e51e04, 0x15e5a3f0, 0x4f0490f0, 0x4e0490e0, 0x22231112, 0x60128b7f, 0x0f54efb1, 
+    0xf0490490, 0xceb51312, 0x13ce13c3, 0xe030f9d8, 0x08a47505, 0xf5e40380, 0xf3a675a4, 0x75ffa775, 
+    0x13122c9a, 0x13c3ceb5, 0xf9d813ce, 0x30060490, 0x44e00de0, 0x0490f010, 0x1044e008, 0xe00b80f0, 
+    0x90f0ef54, 0x54e00804, 0x5d12f0ef, 0xb513125a, 0xce13c3ce, 0x30f9d813, 0x118002e0, 0xe0490490, 
+    0x15121070, 0x0694c38e, 0x400094e4, 0xa4f5e405, 0xa4750380, 0xfba67504, 0x12901312, 0xc3ceb513, 
+    0xd813ce13, 0x16e020f9, 0xe0490490, 0x15121070, 0x0e94d38e, 0x400094e4, 0x80a47505, 0xf5e40380, 
+    0x7fa675a4, 0x90901312, 0xfce00004, 0xecfde0a3, 0xf054f8c4, 0x54c4edc8, 0x0354480f, 0x21700264, 
+    0x7804aeed, 0x13c3ce02, 0xf9d813ce, 0x7512e030, 0xa67504a4, 0x901312fb, 0x7580a475, 0x13127fa6, 
+    0xb5131290, 0xce13c3ce, 0x30f9d813, 0xa57505e0, 0xe4038002, 0xa675a5f5, 0xfda775ff, 0x7d959a75, 
+    0x12ffe496, 0x54ef7860, 0x13c3ff03, 0xf0890490, 0xa5752460, 0xffa67580, 0x757fa775, 0xa575a59a, 
+    0xffa67540, 0x75bfa775, 0xa575a59a, 0xffa67520, 0x75dfa775, 0xa475a59a, 0xfea67501, 0x75ffa775, 
+    0x0490019a, 0xfe24e049, 0x500008b4, 0x532a9030, 0xa403f075, 0xf02583c5, 0x027383c5, 0x2a026b2a, 
+    0x6b2a026b, 0x02702a02, 0x2a02702a, 0x6b2a026b, 0x75702a02, 0x088001a5, 0x8002a575, 0xa5f5e403, 
+    0x75ffa675, 0x9a75fca7, 0x24ef2203, 0x147a60fe, 0x2b020370, 0x037014e0, 0x14ef2b02, 0x2b020370, 
+    0x600424fe, 0x122c0203, 0x8064edd3, 0x0240c694, 0xedd3467d, 0xbf948064, 0x24ed0640, 0x0280ffc1, 
+    0x07ac007f, 0x1204a575, 0x0e12f00d, 0x400f121b, 0x75b40d12, 0xa5752b9a, 0xf00d1206, 0x121b0e12, 
+    0x0d12400f, 0x2b9a75b4, 0x1202a575, 0xffecf00d, 0xfee09533, 0x9533fbed, 0xebc3fae0, 0x9eeaff9f, 
+    0x12200e12, 0x2c02400f, 0x7f0f120b, 0x05af0440, 0xf4ed0480, 0xefd3ff04, 0x9f948064, 0x0f121340, 
+    0xaf04407f, 0xed048005, 0xefff04f4, 0x80ffe124, 0xac007f02, 0x0aa57507, 0x12f00d12, 0x0f121b0e, 
+    0xb40d1240, 0x752b9a75, 0x0d120ca5, 0x1b0e12f0, 0x12400f12, 0x9a75b40d, 0x08a5752b, 0x12f00d12, 
+    0x04407f0f, 0x048005af, 0xff04f4ed, 0xe09533ef, 0x9533fbec, 0xefc3fae0, 0xf5efff9b, 0x7f0f12a4, 
+    0x05af0440, 0xf4ed0480, 0x33efff04, 0xc3fee095, 0x9aee9bef, 0xa775a5f5, 0x2b9a75fe, 0x75b40d12, 
+    0xa5752b9a, 0xf00d1214, 0x509d1012, 0x80017f04, 0x12007f02, 0x007e9a10, 0x75a5f5ee, 0x9a75fea7, 
+    0xb40d122b, 0x752b9a75, 0x0d1216a5, 0x9d1012f0, 0x017f0450, 0x007f0280, 0x7e9a1012, 0xa5f5ee00, 
+    0x75fea775, 0x2b802b9a, 0x120ea575, 0x12edf00d, 0x0f121c0e, 0x751c8040, 0x0d1210a5, 0x0e12edf0, 
+    0x400f121c, 0xa5750d80, 0xf00d1212, 0x1c0e12ed, 0x12400f12, 0x9a75b40d, 0xc222222b, 0x07f730d5, 
+    0xf063d5b2, 0x30f005ff, 0xd5b20ce7, 0x638404f4, 0xf005fff0, 0x30840180, 0x04f402d5, 0x0601bb22, 
+    0x838a8289, 0x025022e0, 0xfebb22e7, 0x8922e302, 0xe4838a82, 0x01bb2293, 0x8a828909, 0x28e0f883, 
+    0x035022f0, 0xbb22f727, 0xe3f805fe, 0x8a22f328, 0xf8828983, 0x222893e4, 0x890601bb, 0xf0838a82, 
+    0xf7025022, 0x01febb22, 0x8def22f3, 0xf0a8a4f0, 0xa4f08ccf, 0xf08dce28, 0x22fe2ea4, 0xf0f59feb, 
+    0xf0429eea, 0xf0429de9, 0xc88064ec, 0x45988064, 0x9feb22f0, 0x9eeaf0f5, 0x9de9f042, 0x9ce8f042, 
+    0xe822f045, 0xc3ec0f60, 0x13edfc13, 0xfe13eefd, 0xd8ff13ef, 0x60e822f1, 0x33c3ef0f, 0xfe33eeff, 
+    0xecfd33ed, 0xf1d8fc33, 0x0701bb22, 0x838a8289, 0x50532d02, 0x02f8e905, 0xfebb472d, 0x02f8e905, 
+    0x82895f2d, 0x2d02838a, 0x0701bb6b, 0x838a8289, 0x50872d02, 0x02f8e905, 0xfebb7b2d, 0x02f8e905, 
+    0xef22932d, 0xef12604e, 0xed0e0160, 0x890b01bb, 0xf0838a82, 0xdefcdfa3, 0xf08922fa, 0x09f70750, 
+    0xf0a9fcdf, 0xfcfebb22, 0xfcdf09f3, 0xe622f0a9, 0xfde608fc, 0x08fee608, 0xe022ffe6, 0xfde0a3fc, 
+    0xa3fee0a3, 0xe222ffe0, 0xfde208fc, 0x08fee208, 0xe422ffe2, 0x0174fc93, 0x0274fd93, 0x0374fe93, 
+    0xec22ff93, 0xf6ed08f6, 0x08f6ee08, 0xec22f6ef, 0xf0eda3f0, 0xa3f0eea3, 0xec22f0ef, 0xf2ed08f2, 
+    0x08f2ee08, 0x9022f2ef, 0x70e06e04, 0x8604901e, 0x7d1860e0, 0x12ffe499, 0x30ee1d60, 0x04900de7, 
+    0xf001746e, 0x107f027d, 0x90703612, 0x24e04104, 0x143860df, 0x2e020370, 0x03701481, 0x14ac2e02, 
+    0x2e020370, 0x03701491, 0x14c32e02, 0x2e020370, 0x120080e3, 0x9a75cb2f, 0x7f027d51, 0x70361208, 
+    0x90625c12, 0xf0ee2004, 0x12f0efa3, 0x3170072f, 0xc3625c12, 0xe0210490, 0x0490ff9f, 0xfe9ee020, 
+    0xe894efc3, 0x400394ee, 0x7f027d11, 0x7036120f, 0x754c2f12, 0x9a75ffa7, 0x04902219, 0xf0217441, 
+    0x86049022, 0x7df00174, 0x12ffe499, 0x138e1d60, 0x7def148f, 0x803c1202, 0x097f027d, 0xe4703612, 
+    0xa5f5a4f5, 0xe4609a75, 0xa575a4f5, 0x609a7580, 0xf5a4f5e4, 0x609a75a5, 0x30122274, 0xae14af71, 
+    0x254c1213, 0x600164ef, 0x072f121a, 0x04906960, 0xf0117440, 0xf02474a3, 0xf02e1222, 0xe0690490, 
+    0x74da01b4, 0x71301223, 0x13ae14af, 0xef564f12, 0x21600164, 0x6012657f, 0x0154efb1, 0x376012f5, 
+    0x74400490, 0x74a3f011, 0x1222f025, 0x0490f02e, 0x01b4e06a, 0x4c2f12d3, 0x75ffa775, 0x027d619a, 
+    0x36120c7f, 0x41049070, 0x90f02674, 0x60e06e04, 0x41049006, 0x22f02774, 0x6012507f, 0x8f138e2f, 
+    0x027def14, 0x7d803c12, 0x12097f02, 0x7f227036, 0xb1601265, 0xf50154ef, 0xa4752212, 0x03a67550, 
+    0x75ffa775, 0x7422d19e, 0xf51c25f8, 0x0334e482, 0xffe083f5, 0x1c250074, 0x34e482f5, 0xef83f501, 
+    0x17ae22f0, 0xc4ee18af, 0xc8f054f8, 0x0f54c4ef, 0x22035448, 0x7501a475, 0x2522fea6, 0xe41cf51c, 
+    0x1bf51b35, 0x941ce5c3, 0x941be5f8, 0x04902202, 0xa3fee000, 0xfe5422e0, 0x670090f0, 0x22f004e0, 
+    0x75a4f5e4, 0xa775dfa6, 0x109a75ff, 0x7483f522, 0x0090f0ff, 0xa3fce066, 0xffecfde0, 0x74220174, 
+    0xf51e25f8, 0x0334e482, 0xffe083f5, 0x1e250074, 0x241be522, 0x1ae5ff08, 0xc3fefd34, 0xe49f1ce5, 
+    0x1ce5229e, 0xe5ff0824, 0xfefd341b, 0x9f1ee5c3, 0x75229ee4, 0xa67502a4, 0xffa775fd, 0x5c009022, 
+    0x146490e0, 0x90d32293, 0x94e06700, 0x66009000, 0x220094e0, 0x250074f0, 0x7482f51c, 0xf51b3501, 
+    0x00902283, 0xf004e066, 0x10a57522, 0x75ffa675, 0x9a75efa7, 0xf5e42210, 0xfea675a4, 0x4c049022, 
+    0x220164e0, 0x941be5c3, 0x941ae5f8, 0x00742202, 0x82f51b25, 0x1a350174, 0x742283f5, 0xf51b2508, 
+    0x35fd741b, 0x221af51a, 0x1c250874, 0xfd741cf5, 0x1bf51b35, 0x25027422, 0x7482f51c, 0x221b3501, 
+    0x82f51c25, 0x1b350174, 0x902283f5, 0xc3e00004, 0x04902213, 0xf001743f, 0x41049022, 0x13f5e4f0, 
+    0xae2214f5, 0xef16af15, 0x158ecf54, 0x75128f22, 0x12e5031e, 0x14750770, 0x8013f51f, 0xb412e51a, 
+    0x0d800201, 0x03b412e5, 0x1f147508, 0x8013f5e4, 0x14f5e406, 0x12e11375, 0x10123a0e, 0xee18f55a, 
+    0x17f5ff34, 0xf5ff34ed, 0xff34ec16, 0x387f15f5, 0x122f6012, 0x397ff910, 0x122f6012, 0x0e12fd11, 
+    0x5a10123a, 0x34ee1cf5, 0xed1bf5ff, 0x1af5ff34, 0xf5ff34ec, 0x4f049019, 0x404a0f12, 0x90078002, 
+    0xf4e04f04, 0xefd3ff04, 0x81948064, 0x04900840, 0xe7a2e04f, 0x0490f013, 0xf004e053, 0xe0530490, 
+    0x500594d3, 0x870e1211, 0xa32cf5e4, 0x4312ffe0, 0xe41d8fcf, 0x04901b80, 0x94d3e053, 0x12185007, 
+    0x2c75870e, 0xffe0a301, 0x8fcf4312, 0x6204901d, 0x4d0490e0, 0x900980f0, 0xf5e05004, 0x5d11121d, 
+    0xe0500490, 0x0490f0a3, 0xf01de550, 0x036012e5, 0x900a01b4, 0xffe05004, 0x80b95c12, 0xb1111206, 
+    0x90735412, 0x64e04d04, 0xe55c7001, 0x12127012, 0x0240470f, 0x10120380, 0x0f04906a, 0x80721012, 
+    0xb412e546, 0x0f121201, 0x80024047, 0x6a101203, 0x12100490, 0x2f807210, 0x02b412e5, 0x470f1216, 
+    0x03800240, 0xef6a1012, 0x54333333, 0x0d0490f8, 0x121480f0, 0x0240470f, 0x10120380, 0x3333ef6a, 
+    0x90f85433, 0x7ff00e04, 0x04902200, 0x0490e045, 0x0490f04f, 0xa3ffe00d, 0xff9fc3e0, 0xa20094e4, 
+    0xeffe13e7, 0x980f1213, 0x709d1112, 0x7d049031, 0x0794c3e0, 0xf0e44940, 0xd3260f12, 0x64ec0c94, 
+    0x40809480, 0x45049007, 0x2f8014e0, 0xf494edc3, 0x948064ec, 0x9028507f, 0x04e04504, 0x04901d80, 
+    0x0424e025, 0x240490ff, 0xfe0034e0, 0x120378ef, 0xfbd8390f, 0x450490ff, 0x909fc3e0, 0x90f04f04, 
+    0xffe04f04, 0x948064c3, 0x74055098, 0x0e80f018, 0x8064efd3, 0x0640ac94, 0x744f0490, 0x0490f02c, 
+    0x90ffe04f, 0xfee04504, 0x0203706f, 0xfdee1633, 0xfce09533, 0xe09533ef, 0x9defc3fe, 0xfe9ceeff, 
+    0xc30378ef, 0xce33ce33, 0x0f12f9d8, 0x4f049098, 0x0490ffe0, 0x5512f045, 0x0e0490e1, 0x0490ffe0, 
+    0xff2fe025, 0xe0240490, 0x04900034, 0xed101226, 0x90e40950, 0xa3f02604, 0x120b80f0, 0x0640c410, 
+    0x74a3f0e4, 0x0490f0f8, 0x90e0a326, 0x90f00e04, 0x0f120d04, 0x9defc324, 0xa39ce4ff, 0x50ed1012, 
+    0x0490e409, 0xf0a3f026, 0x10120b80, 0xe40640c4, 0xf874a3f0, 0x260490f0, 0x0490e0a3, 0x007ff00d, 
+    0x50531222, 0x6012128f, 0x0370ef90, 0x123b3402, 0x03409a15, 0x903b3402, 0x70e02404, 0x64e0a304, 
+    0x02037063, 0x04903b34, 0x2870e049, 0x6012387f, 0xf612122f, 0x05c004c0, 0x07c006c0, 0x6012397f, 
+    0x0354ee2f, 0xd003d0fe, 0xd001d002, 0xff4feb00, 0x4e804eea, 0x40bf1312, 0xba141228, 0x347f2350, 
+    0x122f6012, 0x04c0f612, 0x06c005c0, 0x357f07c0, 0xd0b16012, 0xd002d003, 0xeb00d001, 0x80eaff4f, 
+    0x12367f21, 0x12122f60, 0xc004c0f6, 0xc006c005, 0x12377f07, 0x03d0b160, 0x01d002d0, 0x4feb00d0, 
+    0xe9feeaff, 0x12fce8fd, 0x12123051, 0xc615129e, 0x12181312, 0x0d50c414, 0x12375612, 0x0490c85f, 
+    0xf012e577, 0x9b5f1222, 0x8064efd3, 0x4d406194, 0xe0490490, 0xc17f0c70, 0x7fd65812, 0xd6581201, 
+    0x047f0b80, 0x12d65812, 0x9a755e15, 0x7d141232, 0xef9b5f12, 0x5c12ff14, 0xc85f12b9, 0x121212e5, 
+    0xd912129a, 0x12e5f0e4, 0x40ff94c3, 0x80007f04, 0x77049006, 0x90ff04e0, 0xf0ef7704, 0x57151222, 
+    0x22f06374, 0x5a122a7f, 0x755a12df, 0xef560490, 0x601412f0, 0x12901312, 0xffe48a13, 0x90b95c12, 
+    0xfce00004, 0xaefde0a3, 0xce077804, 0x13ce13c3, 0xe020f9d8, 0x06049059, 0x52e020e0, 0x7804aeed, 
+    0x13c3ce02, 0xf9d813ce, 0x9010e030, 0x60e08904, 0x01a47505, 0xa4750880, 0x75038004, 0xa67507a4, 
+    0xffa775f0, 0x90419a75, 0x70e04904, 0x00049021, 0x54f8c4e0, 0xe0a3c8f0, 0x480f54c4, 0x02640354, 
+    0xa4750c60, 0xf8a67501, 0x75ffa775, 0x0490429a, 0x2460e049, 0x24186014, 0x240860fb, 0x240460fe, 
+    0x90397005, 0x2a744504, 0x1574a3f0, 0xe43680f0, 0xf0450490, 0x2d80f0a3, 0xe0040490, 0x5408e730, 
+    0x4504907f, 0x900e80f0, 0x70e05f00, 0x90008002, 0x24744504, 0x0490e4f0, 0x0980f046, 0x74450490, 
+    0xa3e4f020, 0x5f0090f0, 0x6d0490e0, 0x90f00274, 0xffe06d04, 0xe0460490, 0x0490f02f, 0x12ffe045, 
+    0x0490e155, 0x12ffe046, 0x13127354, 0x13c3ceb5, 0xf9d813ce, 0x1203e030, 0x13125f3d, 0x440490d0, 
+    0x22f00174, 0xe0490490, 0x007f0360, 0x40049022, 0x70f324e0, 0x09360203, 0x04900080, 0x01b4e04c, 
+    0x0804900a, 0x03e030e0, 0x12643602, 0x0d12565e, 0x13c3cefa, 0xf9d813ce, 0x7f05e020, 0x075c120c, 
+    0xcefa0d12, 0x13ce13c3, 0xe030f9d8, 0x9d111251, 0x04901a60, 0x0760e07c, 0x1212ff74, 0x126d8082, 
+    0x04902422, 0xa3f0ee28, 0x6080f0ef, 0xe0550490, 0x12120370, 0x7c049082, 0x901060e0, 0x24e02904, 
+    0x0490f0ff, 0xff34e028, 0x120680f0, 0x11122422, 0x550490a4, 0xe0f004e0, 0x58700864, 0x0d124e80, 
+    0x13c3cefa, 0xf9d813ce, 0x1249e020, 0x0d74bd10, 0x906012f0, 0x7f0370ef, 0x11122202, 0x7f12609d, 
+    0x2f601238, 0xee280490, 0xf0efa3f0, 0x80804412, 0x55049023, 0x120370e0, 0x387f8212, 0x122f6012, 
+    0x0490a411, 0xf004e055, 0x0808b4e0, 0xe4804412, 0xf0550490, 0xcefa0d12, 0x13ce13c3, 0xe020f9d8, 
+    0x5c049011, 0x020370e0, 0x06809835, 0x745c0490, 0x2e74f001, 0x22891212, 0x00901a8f, 0x1bf5e05a, 
+    0x1cf5e0a3, 0x12041d75, 0x03405c2f, 0xe5793702, 0x5000941a, 0x79370203, 0x1d941ae5, 0x37020340, 
+    0x65009079, 0x700164e0, 0x79370203, 0xe0050490, 0x03509dc3, 0x90793702, 0xb4e05d00, 0x1ce515ff, 
+    0xe4ff0824, 0xd3fe1b35, 0xeef894ef, 0x03400294, 0xe5793702, 0x124d702e, 0x2f8eee5d, 0x0090308f, 
+    0xe030e060, 0x6e2f1208, 0x2f120370, 0xde2f12fa, 0x30123240, 0x852f124d, 0xef583012, 0xedec2f12, 
+    0x120374f0, 0x1540532f, 0x121ef5e4, 0x0a50ba2f, 0x12972f12, 0x1e05302f, 0x3012f180, 0x0090e440, 
+    0xf0a3f066, 0x2e251de5, 0xe05433c4, 0x74ff3345, 0xf51c2503, 0x35017482, 0xef83f51b, 0xff2fe5f0, 
+    0xf54d3012, 0x74f0ef83, 0x58301201, 0x2f1230e5, 0xf01ae5ec, 0x2f120474, 0xe4154053, 0x2f121ef5, 
+    0x120a50ba, 0x2f12972f, 0x801e0530, 0x403012f1, 0xf52ff5e4, 0x902ef530, 0x1be55a00, 0x1ce5a3f0, 
+    0x531222f0, 0x12128f50, 0x70ef9060, 0x81380203, 0x409a1512, 0x81380203, 0xe0240490, 0xe0a30470, 
+    0x03706364, 0x90813802, 0x70e04904, 0x12387f28, 0x12122f60, 0xc004c0f6, 0xc006c005, 0x12397f07, 
+    0x54ee2f60, 0x03d0fe03, 0x01d002d0, 0x4feb00d0, 0x804eeaff, 0xbf13124e, 0x14122840, 0x7f2350ba, 
+    0x2f601234, 0xc0f61212, 0xc005c004, 0x7f07c006, 0xb1601235, 0x02d003d0, 0x00d001d0, 0xeaff4feb, 
+    0x367f2180, 0x122f6012, 0x04c0f612, 0x06c005c0, 0x377f07c0, 0xd0b16012, 0xd002d003, 0xeb00d001, 
+    0xfeeaff4f, 0xfce8fde9, 0x12305112, 0x15129e12, 0x181312c6, 0xd39b5f12, 0x948064ef, 0x12385061, 
+    0x2c50c414, 0x7f375612, 0xb95c121f, 0xe5c85f12, 0x9a121212, 0xe4d91212, 0xc312e5f0, 0x0440ff94, 
+    0x0680007f, 0xe0770490, 0x0490ff04, 0x22f0ef77, 0x74571512, 0x1222f063, 0x14ef9b5f, 0xb95c12ff, 
+    0x90c85f12, 0x12e57704, 0x5f1222f0, 0x4f04909b, 0xf0001512, 0xe0170490, 0x94d30854, 0xe4054000, 
+    0x0380a4f5, 0x1208a475, 0x04908d13, 0x0754e017, 0x400008b4, 0x2d390203, 0xf8b73890, 0x02732828, 
+    0x3802cf38, 0xdd3802d6, 0x02f23802, 0x39020739, 0x0e390209, 0x7f203902, 0x7439121f, 0xe17f4280, 
+    0x80743912, 0x8039124d, 0x207f0970, 0x7fd65812, 0x7f0280ff, 0xd65812fe, 0x39122680, 0x7f097080, 
+    0xd65812e0, 0x0280017f, 0x5812027f, 0x802380d6, 0x3d3e1200, 0x207f1f80, 0x7f045a12, 0x045a12ff, 
+    0x74571512, 0x0d80f01f, 0x5a12e07f, 0x12017f04, 0x1412045a, 0x1704907d, 0x27e220e0, 0x904e5f12, 
+    0xd3e04904, 0x18400094, 0x40a51512, 0x0154ef13, 0x400194d3, 0x5e151205, 0x15120380, 0x329a7550, 
+    0x12c85f12, 0x017baa5a, 0x5479047a, 0xe4145212, 0xf0160490, 0xf0770490, 0x22591312, 0x90b95c12, 
+    0xffe04604, 0x22735412, 0x5c12ffe4, 0x490490b9, 0x828d22e0, 0x07ad838c, 0xfce40479, 0x23e5017a, 
+    0x508d1112, 0x1223e516, 0x0f50c911, 0x1222e5c3, 0x07408e11, 0x111222e5, 0x7f0350c9, 0x24e52200, 
+    0xe532706d, 0x70834582, 0xeb22ff02, 0x408d1112, 0x12ff7a02, 0x0640d111, 0x82af83ae, 0x12120380, 
+    0x8f258e49, 0xdd111226, 0x20ae0640, 0x3b8021af, 0x80531212, 0x6b24e536, 0x21e53770, 0x02702045, 
+    0xedd322ff, 0x40c91112, 0x12ff7a02, 0x0640dd11, 0x21af20ae, 0x12120380, 0x8f258e53, 0xd1111226, 
+    0x83ae0640, 0x038082af, 0x8e491212, 0x80288f27, 0x22007f03, 0xd3edfde4, 0xc3445099, 0x289526e5, 
+    0x806427e5, 0x6425e5f8, 0x50ec9880, 0xfce02518, 0x9528e5c3, 0x27e5cf26, 0x12122595, 0xef27f55d, 
+    0x8028f513, 0x04e02517, 0x26e5c3fc, 0xe5cf2895, 0x12279525, 0x25f55d12, 0x26f513ef, 0xecb7800d, 
+    0x24641112, 0x3ee4ff01, 0xef13e7a2, 0xffbafc13, 0xff04f404, 0x2204af22, 0xe07f0490, 0x3013c3ff, 
+    0x007f03e0, 0x53591222, 0x188e198f, 0x168c178d, 0xe0200490, 0xfde0a3fc, 0x107804ae, 0x33ce33c3, 
+    0xfff9d8ce, 0xe4261012, 0x148e158f, 0x12f513f5, 0xe0400490, 0x1860f624, 0x90e40080, 0xf5f05304, 
+    0xf514f515, 0x1212f513, 0x0490c10f, 0xf00a7440, 0xef906012, 0x027f0370, 0x12067f22, 0x54efa760, 
+    0x12097001, 0x0f126e0f, 0x22007fc1, 0xfdfeffe4, 0xaa15abfc, 0xa813a914, 0x2c12c312, 0x800270aa, 
+    0x19e5c341, 0xe5fb1595, 0xfa149518, 0x139517e5, 0x9516e5f9, 0x0490f812, 0xe4ffe053, 0xebfefdfc, 
+    0x3aeeff2f, 0xfd39edfe, 0xe4fc38ec, 0xf9fa0a7b, 0x2c12c3f8, 0xe52740aa, 0xff159519, 0xe0530490, 
+    0x19aff02f, 0x17ad18ae, 0x107816ac, 0x12bb2c12, 0x19e53911, 0xfe18e5ff, 0x7f391112, 0x12e42202, 
+    0x0f126e0f, 0x961112c1, 0x75ffa775, 0x017d199a, 0x3612177f, 0x22017f70, 0xe0400490, 0x5260f124, 
+    0x04900080, 0x0360e049, 0x90503c02, 0xffe08704, 0x541313c4, 0x03e03003, 0x12503c02, 0x5f12565e, 
+    0x4e04909b, 0x0f7ff0ef, 0xe4a45d12, 0xf04b0490, 0xe04b0490, 0x0494c3ff, 0xe0a34650, 0x120501b4, 
+    0x0880954b, 0xe04b0490, 0x485012ff, 0x74bd1012, 0x6012f00f, 0x0370ef90, 0x9022027f, 0xb4e04c04, 
+    0x04900b01, 0x12ffe04b, 0x80ef701b, 0x4b049008, 0x3012ffe0, 0x4d049085, 0x12d160e0, 0xb0802411, 
+    0xe0460490, 0x735412ff, 0xe04e0490, 0xb95c12ff, 0xef8e5c12, 0x20700164, 0xe0060490, 0x1313c4ff, 
+    0xe0200354, 0x96111213, 0x75ffa775, 0x017d199a, 0x36121b7f, 0x22017f70, 0x74400490, 0x0490f02b, 
+    0xf004e07d, 0xe0490490, 0x0d121b70, 0x13c3cefa, 0xf9d813ce, 0x900ee020, 0xffe08704, 0x200f54c4, 
+    0x310203e0, 0x22007fe2, 0x0090198f, 0x1af5e05a, 0x1bf5e0a3, 0x401c3012, 0x5e3d0203, 0xe0650090, 
+    0x03700164, 0x905e3d02, 0xc3e00504, 0x0203509d, 0x00905e3d, 0xffb4e05d, 0x241be515, 0x35e4ff0c, 
+    0xefd3fe1a, 0x94eef894, 0x02034002, 0x2ee55e3d, 0x5d126270, 0x8f2f8eee, 0x60009030, 0x08e030e0, 
+    0x706e2f12, 0xfa2f1203, 0x40de2f12, 0x25027447, 0x7482f51b, 0x121a3501, 0x1b25852f, 0x017482f5, 
+    0x83f51a35, 0x3012f0ef, 0x74f0ed26, 0xf51b2503, 0x1a35e41b, 0x30121af5, 0xe412401c, 0x2f121cf5, 
+    0x120750a9, 0x1c051f2f, 0x3012f480, 0x0090e433, 0xf0a3f066, 0xe5263012, 0x1b05f019, 0x02701be5, 
+    0x12c31a05, 0x12401f30, 0x121cf5e4, 0x0750a92f, 0x051f2f12, 0x12f4801c, 0x2e053330, 0xe55a0090, 
+    0xe5a3f01a, 0x1222f01b, 0x9a75b40d, 0x40a57520, 0x75ffa675, 0x9a75bfa7, 0x07049020, 0x0f12c4e0, 
+    0x219a75a9, 0xe0070490, 0x0f1213c4, 0x239a75a9, 0x75730e12, 0x9a759fa7, 0xab101221, 0x75ffa775, 
+    0x0f12229a, 0xc0a77507, 0x12229a75, 0xa7756c0e, 0x219a75f3, 0x75730e12, 0x9a759fa7, 0xab101223, 
+    0x75ffa775, 0x0f12249a, 0xc0a77507, 0x12249a75, 0xa7756c0e, 0x239a75f3, 0x75730e12, 0x9a759fa7, 
+    0xab101225, 0x75ffa775, 0x0f12269a, 0xc0a77507, 0x12269a75, 0xa7756c0e, 0x259a75f3, 0x75730e12, 
+    0x9a759fa7, 0xab101227, 0x75ffa775, 0x0f12289a, 0xc0a77507, 0x12289a75, 0xa7756c0e, 0x279a75f3, 
+    0x75730e12, 0x9a759fa7, 0xab101229, 0x75ffa775, 0x0f122a9a, 0xc0a77507, 0x122a9a75, 0xa7756c0e, 
+    0x299a75f3, 0x0490e422, 0xf0a3f026, 0x6012447f, 0x641312b1, 0x12845f12, 0x0490cb60, 0x7ff0ef78, 
+    0xb1601243, 0x12641312, 0x1512845f, 0xd3f0efde, 0x80948064, 0xffe00440, 0x04900780, 0x04f4e079, 
+    0x780490ff, 0x64d3fee0, 0x40809480, 0x90078002, 0xf4e07804, 0xefd3fe04, 0xeef88064, 0x40988064, 
+    0x27049007, 0xf00444e0, 0x12780490, 0x0740ef14, 0xe0270490, 0x90f00244, 0x14127904, 0x900740ef, 
+    0x44e02704, 0x1512f001, 0x2b601486, 0x14356014, 0x03243f60, 0x14124770, 0xee0a409a, 0xef13e7a2, 
+    0x80007e13, 0x90007e06, 0x54e02704, 0x1412ff01, 0x7d024088, 0x12238001, 0x007fab13, 0x017f0240, 
+    0x1680fde4, 0x7fab1312, 0x7f024000, 0x80017d01, 0xd4141209, 0x12d04f12, 0x4f12b015, 0x157522d0, 
+    0x1f1675e1, 0x7fff1475, 0x2f601238, 0x138f128e, 0x9413e5d3, 0x6412e51f, 0x40809480, 0x7f127508, 
+    0x80ff1375, 0x13e5c32c, 0x12e5e094, 0x7f948064, 0xff740850, 0x13f512f5, 0x397f1780, 0xee2f6012, 
+    0xadfc0354, 0x2513e507, 0x4ce025e0, 0xf5ed12f5, 0x120a7f13, 0x10122f60, 0x1217f5de, 0x1585d30d, 
+    0x23168522, 0xad241485, 0xaf12ac13, 0xc1401217, 0x0490188f, 0x4260e062, 0xe09533ef, 0xf8c4effe, 
+    0x68c80f54, 0x54c4eeff, 0x049048f0, 0xefa3f032, 0x4e0490f0, 0x854d1012, 0x16852215, 0x24188523, 
+    0x12ac13ad, 0x391217af, 0x9533ef8a, 0x0490fee0, 0xf02fe033, 0xe0320490, 0x0490f03e, 0xf017e54e, 
+    0xe51e0490, 0x13e5f012, 0x90461012, 0xaff04d04, 0x73540218, 0xe0240490, 0xfde0a3fc, 0x188fffec, 
+    0x178fffed, 0x6417e5d3, 0x509f9480, 0x17e5c31b, 0x61948064, 0xe5d31240, 0x94806418, 0xc309509f, 
+    0x806418e5, 0x15506194, 0x04908074, 0xe5a3f014, 0x0490f018, 0xe5a3f078, 0x017ff017, 0x9b5f1222, 
+    0xef4f0490, 0x1217aff0, 0x5f12b95c, 0x4904904e, 0xaf0870e0, 0x9533ef18, 0xc33e80e0, 0x806418e5, 
+    0x10507094, 0x24141512, 0x3ee4ff1f, 0x12dd1312, 0x18805e15, 0x6418e5d3, 0x408f9480, 0x14151214, 
+    0xeeffe124, 0x1312ff34, 0x501512dd, 0x80329a75, 0x1415120b, 0xeeffe025, 0xeb131233, 0xa3240490, 
+    0x5812ffe0, 0x7a007bd6, 0x12167900, 0x5a121452, 0xc85f12aa, 0xe4140490, 0xf004a3f0, 0xe5780490, 
+    0xe5a3f018, 0x007ff017, 0x8c1c8f22, 0x8b1e8d1d, 0x26f5e41f, 0x1ee527f5, 0x0a701d45, 0x90251c85, 
+    0xf0046204, 0x12126780, 0xe50c5008, 0xe5009421, 0x94806420, 0xd3125080, 0x00941ee5, 0x40091212, 
+    0x6420e532, 0x50809480, 0xae21af2a, 0x5d601220, 0x07c006c0, 0x1dae1eaf, 0xd05d6012, 0xc304d005, 
+    0x9cee9def, 0x1c850550, 0x85038025, 0x1112251f, 0x121a8056, 0xff7f0812, 0x017f0240, 0xf02485ef, 
+    0xe5c3ffa4, 0x25f59f1c, 0x620490e4, 0x23e5d3f0, 0xe5f88064, 0x98806425, 0x23850540, 0xc3108025, 
+    0x806422e5, 0x6425e5f8, 0x09509880, 0x75252285, 0x11120126, 0x6525e556, 0xe5056023, 0x0322b525, 
+    0x90012775, 0x26e56004, 0x27e5a3f0, 0x2225aff0, 0x15121d8f, 0xf00e7457, 0xe54660ed, 0x1214601d, 
+    0x60122942, 0x1412c3cb, 0x1208503c, 0x24ef2942, 0xe5268001, 0x7f72701d, 0xb1601244, 0x12641312, 
+    0x6012845f, 0x1412d3cb, 0x7f5e403c, 0xb1601244, 0x12641312, 0x24ef845f, 0x1312ffff, 0x52141252, 
+    0x601de522, 0x3c421215, 0xe0de1512, 0x401412c3, 0x42120850, 0x0124ef3c, 0x1de52780, 0x437f2b70, 
+    0x12b16012, 0x5f126413, 0xde151284, 0x1412d3e0, 0x7f164040, 0xb1601243, 0x12641312, 0x24ef845f, 
+    0x1312ffff, 0x59141252, 0x0490e422, 0xf0a3f024, 0x12447f22, 0x54efb160, 0x007eff3f, 0x007c207d, 
+    0x22845f12, 0x6012437f, 0x3f54efb1, 0x7d007eff, 0x12007c20, 0xef22845f, 0x3860fe24, 0x145a6014, 
+    0x42020370, 0x037014da, 0x24f44202, 0x02036004, 0x0e120d43, 0x900760dc, 0x30e00704, 0xb4ef0be0, 
+    0x04900b01, 0xe020e009, 0x80017f04, 0xae007f02, 0x0d430207, 0x60dc0e12, 0x07049009, 0x3013c3e0, 
+    0xb4ef0de0, 0x04900d01, 0x13c3e009, 0x7f04e020, 0x7f028001, 0x8007ae00, 0xdc0e125c, 0x04900b60, 
+    0x1313e007, 0xe0303f54, 0x01b4ef0f, 0x0904900f, 0x541313e0, 0x04e0203f, 0x0280017f, 0x07ae007f, 
+    0x04903380, 0x01b4e04c, 0x0904900d, 0x20320f12, 0x017f04e0, 0x007f0280, 0x198007ae, 0xe04c0490, 
+    0x900e01b4, 0xc4e00904, 0xe0200f54, 0x80017f04, 0xae007f02, 0x2206af07, 0xe0140490, 0x03e730a3, 
+    0x75ce4302, 0x131220a4, 0x7a007b04, 0x12127900, 0x1a75a251, 0xe51b8f00, 0x4501641b, 0x0203601a, 
+    0x5712ca43, 0x490490be, 0x900870e0, 0x13121804, 0x9072805c, 0xffe07804, 0x948064c3, 0xd31c4070, 
+    0x948064ef, 0x7f14508f, 0x2f601234, 0xc0f61212, 0xc005c004, 0x7f07c006, 0x7f128035, 0x2f601236, 
+    0xc0f61212, 0xc005c004, 0x7f07c006, 0xb1601237, 0x02d003d0, 0x00d001d0, 0x19f54feb, 0xe918f5ea, 
+    0xf5e817f5, 0xae19af16, 0xfc17ad18, 0x2c121078, 0x180490bb, 0xefa3f0ee, 0xff19e5f0, 0xa3fe18e5, 
+    0xefa3f0ee, 0x441ae5f0, 0x140490ec, 0xa31be5f0, 0x131222f0, 0x8f222201, 0x642ce51f, 0xaf667001, 
+    0xad22ae23, 0xec20ac21, 0x704f4e4d, 0x2d1f850a, 0x04620490, 0xec6980f0, 0xe4125033, 0xfcfdfeff, 
+    0x27aa28ab, 0x25a826a9, 0x50942c12, 0xfeffe419, 0x23abfcfd, 0x21a922aa, 0x12d320a8, 0x1940942c, 
+    0x33ec25ac, 0x20ac1350, 0x055033ec, 0x802d1f85, 0x2d248503, 0x80561112, 0xec20ac27, 0x40ff7f33, 
+    0x80017f02, 0xec20ac0a, 0x40ff7f33, 0xef017f02, 0xa4f02b85, 0x1fe5c3ff, 0xe42df59f, 0xf0620490, 
+    0x642ae5d3, 0x2de5f880, 0x40988064, 0x2d2a8505, 0xe5c31080, 0xf8806429, 0x80642de5, 0x85065098, 
+    0x11122d29, 0x222daf56, 0x6012417f, 0x0f54efb1, 0x12580490, 0x0490b210, 0xb20e1228, 0x06800240, 
+    0x12280490, 0xefd3ce0f, 0x64ee0494, 0x50809480, 0x9d111205, 0x04904c60, 0x90ffe058, 0xfce02804, 
+    0x90fde0a3, 0xfee05a04, 0x2a0490fb, 0xe4db0d12, 0x237522f5, 0xff24750f, 0x90c14012, 0x0f125804, 
+    0x5a0490db, 0x620490f0, 0x01b4ffe0, 0x5a04900e, 0x0490fee0, 0x06b5e058, 0x90108002, 0xf0ef5c04, 
+    0x04900f80, 0x90e0a322, 0x90f05a04, 0x01745c04, 0x280490f0, 0x90f50e12, 0xb4e04c04, 0x04900b01, 
+    0x0164e05c, 0x02740360, 0x580490f0, 0x75a4f5e0, 0xa775f0a6, 0x419a75ff, 0x15f5e422, 0x900f1675, 
+    0x90e06304, 0x11126704, 0x750550f1, 0x11800113, 0x6412e5c3, 0x40889480, 0xff137505, 0xf5e40380, 
+    0x12467f13, 0x0e12b160, 0x845f1210, 0xf52f13e5, 0x15e5c314, 0xe5f88064, 0x98806414, 0x15850350, 
+    0x16e5d314, 0xe5f88064, 0x98806414, 0x16850340, 0x64049014, 0x680490e0, 0x50f11112, 0x01137505, 
+    0xe5c31180, 0x94806412, 0x75054088, 0x0380ff13, 0x7f13f5e4, 0xb1601245, 0x12100e12, 0x13e5845f, 
+    0x15e5ff2f, 0x50141012, 0xd315af02, 0x101216e5, 0xaf024015, 0xfd14e516, 0x0f1205ae, 0x341212a2, 
+    0x12140f12, 0x90223b12, 0x24e04004, 0x147060fd, 0x60142460, 0x7f00803f, 0x6b601201, 0x7510a475, 
+    0xa775efa6, 0x409a75ff, 0x4612ff7f, 0x125e1274, 0x74854612, 0x6012f004, 0x0370ef90, 0x7f22027f, 
+    0x7d4612ff, 0xffe4ea60, 0x12744612, 0x4612b75e, 0xf0057485, 0xef906012, 0x027f0370, 0x12ffe422, 
+    0xea607d46, 0x5c12ffe4, 0x12017fb9, 0x5e120758, 0x12097f56, 0x5f12985e, 0x400490c8, 0x12f00374, 
+    0x70ef9060, 0x22027f03, 0x1d12017f, 0x4d0490c8, 0x12e360e0, 0xffe43145, 0x226b6012, 0x12075812, 
+    0x097f565e, 0xc81d1222, 0xe04d0490, 0xc85f1222, 0x22400490, 0xe0400490, 0x5160e324, 0x90e40080, 
+    0x90f05104, 0x60e04904, 0x31470203, 0xcefa0d12, 0x13ce13c3, 0xe020f9d8, 0x31470203, 0x74500490, 
+    0x0490f001, 0xc3ffe050, 0x86948064, 0x42124c50, 0x3e60ef4f, 0xe0500490, 0x12067dff, 0x90e41454, 
+    0x90f04d04, 0x12f04b04, 0x1d74bd10, 0x906012f0, 0x7f0370ef, 0x04902202, 0x0490e07e, 0xe0067050, 
+    0x80027dff, 0x7dffe004, 0x5a271201, 0xe04d0490, 0x0490d560, 0xf004e050, 0x0490a880, 0xf004e051, 
+    0x8064d3e0, 0x06408094, 0x747e0490, 0x0490f001, 0x64c3e051, 0x40819480, 0x0490e483, 0x22fff040, 
+    0x278e288f, 0x258c268d, 0x2a8a298b, 0xffe42b89, 0x12c3fdfe, 0x08703014, 0x12651512, 0x22ff702c, 
+    0x7f2cf5e4, 0x7dff7eff, 0x1412d37f, 0x750c4030, 0x2775ff28, 0x7f2675ff, 0xaf002575, 0xad27ae28, 
+    0x7825ac26, 0xce2c1201, 0x278e288f, 0x258c268d, 0x15122c05, 0x3d1512d7, 0x2ce5e160, 0x1220f075, 
+    0xf0af132c, 0x9f1f74c3, 0x12651512, 0x1512702c, 0x352c1265, 0x0894c3fb, 0x15121a50, 0xf4ebfcd7, 
+    0xf91f2404, 0xbb2c12f8, 0x29ab2d8f, 0x12e42ba9, 0x1380702c, 0xfcd71512, 0x2c121878, 0x122d8fbb, 
+    0xf9746515, 0xaf4e2c12, 0x0f12222d, 0x83a77586, 0xe4149a75, 0x0d12a5f5, 0x219a75b7, 0x12a5f5e4, 
+    0x9a75b70d, 0xa5f5e423, 0x75b70d12, 0xf5e4259a, 0xb70d12a5, 0xe4279a75, 0x0d12a5f5, 0x299a75b7, 
+    0x60dc0e12, 0x07049007, 0x0ce030e0, 0x700164ef, 0x0904900d, 0x06e020e0, 0x75b40d12, 0x0e12219a, 
+    0x900960dc, 0xc3e00704, 0x0ee03013, 0x700164ef, 0x0904900f, 0x2013c3e0, 0x0d1206e0, 0x239a75b4, 
+    0x60dc0e12, 0x0704900b, 0x541313e0, 0x10e0303f, 0x700164ef, 0x09049011, 0x541313e0, 0x06e0203f, 
+    0x75b40d12, 0xa475259a, 0xbfa67540, 0x223a1012, 0xe0420490, 0x4160e624, 0x80776014, 0x49049000, 
+    0x127f70e0, 0xc3cefa0d, 0xd813ce13, 0x72e030f9, 0x60dc0e12, 0x10121206, 0xef0be030, 0x29700164, 
+    0x201b1212, 0x5e1223e0, 0x7f107d56, 0x14541204, 0x90c85f12, 0x1a744204, 0x906012f0, 0x7f0370ef, 
+    0x057f2202, 0x60214912, 0xdc0e12e7, 0x12120660, 0x0be03010, 0x700164ef, 0x1b121229, 0x1223e020, 
+    0x107d565e, 0x5412057f, 0xc85f1214, 0x74420490, 0x6012f01b, 0x0370ef90, 0x7f22027f, 0x21491204, 
+    0x90e4e760, 0xfff04204, 0x12017d22, 0x04905a27, 0x8b22e04d, 0x891e8a1d, 0xaa20ab1f, 0x1222a921, 
+    0x0378e12c, 0x7bbb2c12, 0x79007a00, 0x38471223, 0x129e1212, 0xc3ee0e13, 0x0640ff94, 0xff7f007e, 
+    0x24eb0780, 0x3ae4ff01, 0x770490fe, 0x1dabf0ef, 0x1fa91eaa, 0x7be12c12, 0x79007a00, 0x38471224, 
+    0x23e507a9, 0x45f054c4, 0x1212ff24, 0x0e13129e, 0xff94c3ee, 0xff7f0440, 0x24eb0680, 0x3ae4ff01, 
+    0xef770490, 0xfe9d1212, 0xff930174, 0xe0770490, 0x007afbfd, 0xeaff2bef, 0xe9e91212, 0x94c3edf0, 
+    0x7f0440ff, 0xeb0480ff, 0x90ff0124, 0xf0ef7704, 0xa5f5e422, 0x75b70d12, 0xf5e4309a, 0xe60d12a5, 
+    0x75730e12, 0x9a75f7a7, 0x730e1230, 0x12791112, 0xa775730e, 0x309a75fd, 0x75a4f5e4, 0x0d123fa6, 
+    0xa4f5e4c4, 0x12dfa675, 0xf5e4c40d, 0xefa675a4, 0x12c40d12, 0x0e12be0d, 0x319a7573, 0x12a4f5e4, 
+    0x0e12910f, 0x329a7573, 0x75a4f5e4, 0x9a75ffa7, 0xa5f5e432, 0x75b70d12, 0x0e12339a, 0x87a77573, 
+    0xe4339a75, 0xa5f5a4f5, 0x757fa675, 0x9a75f8a7, 0xa4f5e433, 0x1283a675, 0x12e42d12, 0x9a75ae0f, 
+    0xa4f5e433, 0x12fea675, 0x90222d12, 0x24e04004, 0x804560f2, 0x49049000, 0x907b70e0, 0xc4e00004, 
+    0xc8f054f8, 0x54c4e0a3, 0x0354480f, 0x66600264, 0x7f565e12, 0x345e120c, 0x240490e4, 0x90f0a3f0, 
+    0x06744b04, 0x4b0490f0, 0x94c3ffe0, 0x12425016, 0x10122657, 0xf00e74bd, 0xef906012, 0x027f0370, 
+    0x12387f22, 0x4eef2f60, 0x387f2260, 0xd32f6012, 0xb80e12ef, 0x007e0640, 0x0480017f, 0xff7fff7e, 
+    0xe0250490, 0x0490f02f, 0xf03ee024, 0x80241112, 0xd15412b4, 0x04900680, 0xf001745d, 0x74400490, 
+    0x007ff02c, 0x565e1222, 0x2e0490e4, 0x905c1312, 0xa3f08304, 0x860490f0, 0x3e0490f0, 0xa35c1312, 
+    0x440490f0, 0x2074a3f0, 0xf0a3e4f0, 0xf06d0490, 0xf07b0490, 0x0490f0a3, 0x0490f07e, 0x0490f04a, 
+    0x0490f04c, 0xf0a3f05a, 0xf0820490, 0xf0550490, 0xf0280490, 0x0490f0a3, 0xf0a3f05c, 0x0490f0a3, 
+    0x5c13122a, 0xf05f0490, 0xf06a0490, 0xf0690490, 0xf06b0490, 0x0490f0a3, 0x5c13126f, 0xf0120490, 
+    0x0490f0a3, 0x5c13120d, 0x12730490, 0x04905c13, 0x0490f06e, 0x0490f07d, 0xf0a3f032, 0xe407ad22, 
+    0xf04d0490, 0x121170ed, 0x04902f0f, 0x0490f051, 0x90fee00f, 0x17807504, 0x902001bd, 0x0f121004, 
+    0x9004f432, 0x90f05104, 0xfee01004, 0xe0760490, 0x0024007a, 0x1112eaff, 0xe405804d, 0xf0510490, 
+    0x901602bd, 0x0f120d04, 0x9004f432, 0x90f05004, 0xfee00d04, 0x80730490, 0x1e03bd15, 0x120e0490, 
+    0x0490320f, 0x0490f050, 0x90fee00e, 0x7ce07404, 0xff002400, 0x4d1112ec, 0x90e40580, 0x90f05004, 
+    0xffe05104, 0x12b95c12, 0x5402b111, 0x15f5e473, 0x178e16f5, 0x5912188f, 0x1207adca, 0xedffd52f, 
+    0x18509fd3, 0xe06b0490, 0x10509fc3, 0x643a2f12, 0x12096003, 0x10447b30, 0x458016f5, 0xffd52f12, 
+    0x409fd3ed, 0x6b049036, 0x509ffee0, 0xedffee2e, 0x33e4fb2f, 0xd52f12fa, 0xe4ffe025, 0xebd3fe33, 
+    0x8064ee9f, 0x8064eaf8, 0x12104098, 0x02643a2f, 0x30120960, 0xf520447b, 0x90008016, 0x01746904, 
+    0x6b0490f0, 0x15aef0ed, 0x2f1216af, 0xaf07603e, 0x1215ae16, 0x0490345d, 0x22ffe069, 0x1215f5e4, 
+    0x33ef9b5f, 0x13f5e095, 0x64c3148f, 0x50809480, 0x95e4c30e, 0xe414f514, 0x13f51395, 0x90011575, 
+    0x70e05f00, 0x344d121d, 0x0f120c60, 0x2f3f74b7, 0x637482f5, 0x0f122780, 0x2fff74b7, 0x627482f5, 
+    0x4d121b80, 0x120c6034, 0xbf74b70f, 0x7482f52f, 0x120a8063, 0x7f74b70f, 0x7482f52f, 0x83f53e63, 
+    0x16f593e4, 0xf5930174, 0x6015e517, 0x95e4c30a, 0x95e4ff17, 0xae22fe16, 0x2217af16, 0x6012407f, 
+    0x0f54efb1, 0x54131313, 0x1575221f, 0x3f1675c1, 0x90ff1475, 0x70e04904, 0x80387f04, 0x4904900d, 
+    0x0401b4e0, 0x0280367f, 0x6012387f, 0x8f128e2f, 0x12497f13, 0x54efb160, 0x007eff7f, 0x007c407d, 
+    0x8f845f12, 0xd30d1217, 0x85221585, 0x14852316, 0xac13ad24, 0xc1401212, 0x049007a9, 0xf017e54e, 
+    0xe51e0490, 0xe5a3f012, 0x0490f013, 0x0490e062, 0x0164f04d, 0x11121370, 0x7f067de9, 0x2f0e1240, 
+    0x407f067d, 0x5e12007e, 0x12ffe9f4, 0xa7752612, 0x499a75ff, 0x43049022, 0x60d824e0, 0x1360143d, 
+    0x147f0080, 0x120c5d12, 0x5f12eb0f, 0x430490c8, 0x12f02974, 0x70ef9060, 0x22027f03, 0x604b4e12, 
+    0x570490e9, 0x530490e0, 0x12147ff0, 0x0f12c95d, 0xc85f12eb, 0x74430490, 0x6012f028, 0x0370ef90, 
+    0x1222027f, 0xe9604b4e, 0x430490e4, 0x570490f0, 0x33fdffe0, 0x90fce095, 0xfee05304, 0x64ec9dd3, 
+    0x8074f880, 0xaf045098, 0x90008006, 0xf0ef5304, 0xe422007f, 0x2e5512ff, 0xe04d0490, 0x52009022, 
+    0xe0a3fee0, 0x02604eff, 0x60120380, 0xad06ac4f, 0x56009007, 0xe0a3fee0, 0xc3ce0378, 0xd813ce13, 
+    0xedc3fff9, 0x9eecff9f, 0x570090fe, 0x90f02fe0, 0x3ee05600, 0x0090e4f0, 0x0090f063, 0xd3ffe05c, 
+    0x17400094, 0x247a1012, 0x93e4ff50, 0x12d30034, 0x0740bd11, 0xe05c0090, 0x901f8014, 0xffe05c00, 
+    0x501494c3, 0x7a10121c, 0xe4ffb024, 0xc3ff3493, 0x50bd1112, 0x5c00900c, 0x90f004e0, 0x01746300, 
+    0x049022f0, 0xf724e040, 0x00803a60, 0x7f565e12, 0x2f60120a, 0x90de1012, 0x12f04f04, 0x04909b5f, 
+    0xe4f0ef50, 0x735412ff, 0x5c12ffe4, 0x961112b9, 0x75ffa775, 0x097f039a, 0x12475b12, 0x0490c85f, 
+    0xf0097440, 0xef906012, 0x027f0370, 0x163f1222, 0xe04d0490, 0x04900970, 0x94c3e04b, 0xe4dc4020, 
+    0xa675a4f5, 0xffa775fe, 0x90039a75, 0xffe04f04, 0x90735412, 0xffe05004, 0x7fb95c12, 0xf5e42200, 
+    0x8e16f515, 0x90188f17, 0x90e05c00, 0xff93ff63, 0xe0560490, 0x45509fc3, 0xe06c0490, 0x948064ff, 
+    0x80024080, 0x6c049007, 0xff04f4e0, 0x8064efc3, 0x29508194, 0x18af17ae, 0xce0278ef, 0x13ce13c3, 
+    0x0354f9d8, 0x15600264, 0x16af15ae, 0x8ef354ef, 0xf5084415, 0x6c049016, 0x80f014e0, 0x6a049006, 
+    0x90f00174, 0x64e06a04, 0xaf076001, 0x1215ae16, 0x0490345d, 0x22ffe06a, 0x60ed168f, 0x6016e528, 
+    0x49131211, 0x12521412, 0x03648615, 0x447f5760, 0x0f7f1f80, 0x124b1312, 0x15125214, 0x60036486, 
+    0x80447f44, 0x6016e52a, 0x4913121c, 0x7f591412, 0xb1601243, 0x12641312, 0xf1743e50, 0x2504909f, 
+    0x80ff74f0, 0x120f7f1b, 0x14124b13, 0x12437f59, 0x1312b160, 0x3e501264, 0x909f0f74, 0xe4f02504, 
+    0x2404909e, 0x5f1222f0, 0x9533ef84, 0x22c3fee0, 0x4d0490e4, 0x530490f0, 0x620490f0, 0x1c0490f0, 
+    0xefcd0e12, 0x12750970, 0x7504900f, 0xbf1080f0, 0x12750a01, 0x0490e4f0, 0x0380f076, 0xbf12f5e4, 
+    0x13750502, 0xbf0e80f0, 0x13750503, 0x9006800f, 0xf5e04604, 0x0264ef13, 0x03bf0360, 0x4f049008, 
+    0x80f013e5, 0x4f049006, 0xe4f012e5, 0xf0510490, 0xe04f0490, 0x12aff0a3, 0x90b95c12, 0x25e06d04, 
+    0x5402ff13, 0x0090e473, 0xf0a3f050, 0xe4500090, 0x2674a3f0, 0xf0a3e4f0, 0x74a3f0a3, 0x74a3f0d1, 
+    0x0090f00e, 0xf003745e, 0x745c0090, 0x90e4f00b, 0x13126300, 0x12f0a35c, 0x78ef4f60, 0xce33c303, 
+    0xf9d8ce33, 0x12560090, 0xf5e40d15, 0x554e1209, 0x09e50905, 0x400894c3, 0x0090e4f4, 0xf0a3f05f, 
+    0x045d0090, 0x0090e4f0, 0xf0a3f058, 0x381312a3, 0xf52ef5e4, 0x2230f52f, 0x158e168f, 0x138c148d, 
+    0x1412ffe4, 0xff0270ab, 0x017fe422, 0x70ab1412, 0x22e07f03, 0xe517f5e4, 0xe516f516, 0xe515f515, 
+    0xe514f514, 0xf57f5413, 0xae16af13, 0xac14ad15, 0x12017813, 0x168fce2c, 0x148d158e, 0x1705138c, 
+    0xfdfeffe4, 0x151213e5, 0xe4de603d, 0xe5fdfeff, 0xfc705413, 0x2c121778, 0x7517e5bb, 0x2c1220f0, 
+    0xc3f0ae13, 0x2f9e1f74, 0x1d8b22ff, 0x1f891e8a, 0x8f535912, 0x8d228e23, 0x90208c21, 0x12122004, 
+    0x4eeafbbb, 0x23e5c3fa, 0x22e5ff9b, 0x21e5fe9a, 0x20e5fd99, 0x1dabfc98, 0x1fa91eaa, 0x90012d12, 
+    0x12123404, 0x4eeafbbb, 0x23e5c3fa, 0xe527f59b, 0x26f59a22, 0xf59921e5, 0x9820e525, 0x049024f5, 
+    0x05b4e011, 0x1207780a, 0x0d40ff13, 0x7822017f, 0xff131211, 0x017f0340, 0x22007f22, 0x1e8a1d8b, 
+    0xda7f1f89, 0xee2f6012, 0xe4fe7f54, 0x228e238f, 0x20f521f5, 0x20ac21ad, 0x2c120f78, 0xaa1dabbb, 
+    0xef1fa91e, 0x7f702c12, 0x2f6012db, 0xc0fdfce4, 0xc005c004, 0xaf07c006, 0xad22ae23, 0x7820ac21, 
+    0xce2c1210, 0x02d003d0, 0x00d001d0, 0x23f54bef, 0x22f54aee, 0x21f549ed, 0x20f548ec, 0xe5ff23e5, 
+    0x21e5fe22, 0x5420e5fd, 0xe422fc7f, 0xf0000490, 0x0490f0a3, 0xf002743c, 0x90f0a3e4, 0x90f00b04, 
+    0x90f00a04, 0xa3f00c04, 0x90f0a3f0, 0x90f01004, 0x90f00f04, 0xa3f01204, 0x110490f0, 0x480490f0, 
+    0x040490f0, 0x060490f0, 0x905c1312, 0x02740504, 0x020490f0, 0x0090f014, 0x1070e05f, 0xe0070490, 
+    0x44f00844, 0x2044f010, 0xf04044f0, 0x7f0490e4, 0xfd4a02f0, 0xe0490490, 0x007f0360, 0x40049022, 
+    0x60f424e0, 0x90008039, 0xb4e04c04, 0x04900c01, 0xc4ffe008, 0x20075413, 0x5e1238e0, 0x57049056, 
+    0x5c12ffe0, 0x12097fb9, 0x12127f5d, 0xc40d1242, 0x909b5f12, 0xf0ef5704, 0x74bd1012, 0x6012f00c, 
+    0x0370ef90, 0x7f22027f, 0x2e55123c, 0xe04d0490, 0x2d74e660, 0x22891212, 0x90feffe4, 0xfde01604, 
+    0xe0770490, 0x409dc3fc, 0xfd9dec05, 0x04900b80, 0xc3fde016, 0x2c9dff74, 0x240490fd, 0xa30470e0, 
+    0x706364e0, 0x80064303, 0xe0770490, 0xff94c3fc, 0x007c0440, 0x04ec0380, 0x160490fc, 0x0304b5e0, 
+    0x90400643, 0xfbe01604, 0xe0770490, 0x430303b5, 0xfbed2006, 0x091512eb, 0x742204af, 0xf518f5ff, 
+    0x120e7f19, 0x1a8e2f60, 0xf5e41b8f, 0xf51df51c, 0xc317f516, 0x1b9517e5, 0x1a9516e5, 0x18e53950, 
+    0x251de5ff, 0xe582f517, 0xf516351c, 0x6f93e483, 0xfe19e5fd, 0xed02f075, 0xf5d524a4, 0x34f0e582, 
+    0xe483f560, 0x18f56e93, 0xf5930174, 0xe5170519, 0x05c07017, 0xaebc8016, 0x2219af18, 0x60fe24ef, 
+    0x12601411, 0x14136014, 0x04241460, 0x087c1470, 0x107c1280, 0x207c0e80, 0x407c0a80, 0x807c0680, 
+    0xfce40280, 0x12c94912, 0x9a75070f, 0x20a47531, 0x12910f12, 0x1112730e, 0xa5f5e479, 0x12e60d12, 
+    0x0d124212, 0xbe0d12c4, 0x75a5f5ec, 0x9a75ffa6, 0xa4f5ed32, 0x12e0a675, 0x8f22d50e, 0x120a7f1f, 
+    0xffee2f60, 0x252f1fe5, 0x13e7a2e0, 0xa4f5e4ff, 0x1201a575, 0x30ef580f, 0x0e120ce7, 0x6b111273, 
+    0xff04f4ef, 0x0e120680, 0x6b11126c, 0xe0440490, 0x11121360, 0xff0f1272, 0x1112fee4, 0x12195002, 
+    0x800e7a0e, 0x061012f5, 0x12261212, 0x0e12ff0f, 0x730e127a, 0x220c1012, 0x12427f22, 0x54efb160, 
+    0x59049007, 0x90b21012, 0x0f125904, 0x5b049024, 0x90fbfee0, 0x0d122c04, 0x012275db, 0x75072375, 
+    0x4012ff24, 0x590490c1, 0x90db0f12, 0x90f05b04, 0x90e06204, 0x90f05d04, 0xffe02404, 0x0490e0a3, 
+    0xa3f0cf2c, 0x0490f0ef, 0xa4f5e059, 0x75f8a675, 0x9a75ffa7, 0x128f2242, 0x6012387f, 0xef007c2f, 
+    0xecff1225, 0x1c04903e, 0xf0efa3f0, 0xe0570490, 0xe09533fe, 0xf0260490, 0xfff0cea3, 0xe4cb0d12, 
+    0x237522f5, 0xff24751f, 0x90c14012, 0xf0ef5704, 0x12260490, 0x0490e40e, 0x12ffe057, 0x0490b95c, 
+    0x0760e060, 0x74820490, 0xe422f001, 0xf0820490, 0x40049022, 0x60ec24e0, 0x3e60142e, 0x04900080, 
+    0x3f70e049, 0xcefa0d12, 0x13ce13c3, 0xe030f9d8, 0x5f049032, 0x7f1970e0, 0x8f591209, 0x745f0490, 
+    0x1474f001, 0x12421112, 0x70ef9060, 0x22027f03, 0x4712097f, 0x121574e2, 0x60124211, 0x0370ef90, 
+    0x7422027f, 0xa4101216, 0x7f1c8f22, 0xb160120a, 0x252f1ce5, 0x13e7a2e0, 0x520f12ff, 0x0ce730ef, 
+    0x12730e12, 0xf4ef6b11, 0x0680ff04, 0x126c0e12, 0x04906b11, 0x1360e044, 0x12721112, 0xfee4ff0f, 
+    0x50021112, 0x7a0e1219, 0x12f5800e, 0x12120610, 0xff0f1226, 0x127a0e12, 0x1012730e, 0x9022220c, 
+    0x70e04904, 0x902f8002, 0xf4e02404, 0xe0a30470, 0x0870ef64, 0x12805612, 0x12804915, 0xe0240490, 
+    0xe0a30470, 0x0b700f64, 0x12805612, 0x9a755015, 0x12068032, 0x13129713, 0x25049097, 0x70f004e0, 
+    0x24049006, 0x22f004e0, 0x5812c17f, 0x12017fd6, 0xe422d658, 0x32f531f5, 0x7f846012, 0xb16012f2, 
+    0xc47f54ef, 0x03541313, 0xfa7ff160, 0xefa76012, 0xf50f54c4, 0xbd501208, 0xe533f5e4, 0x0895c333, 
+    0x33850a50, 0x835212b1, 0xef803305, 0x8533f5e4, 0x0012b133, 0xe5330506, 0xf308b533, 0x8033f5e4, 
+    0x400490ee, 0x60f524e0, 0x9000802d, 0xb4e04c04, 0x04900a01, 0xc3ffe008, 0x2ce02013, 0xe0490490, 
+    0x500194d3, 0x565e1223, 0x5e12107f, 0xc85f1212, 0x74400490, 0x6012f00b, 0x0370ef90, 0x1222027f, 
+    0x0490424d, 0xe560e04d, 0x10122a74, 0x07ad22a4, 0x0d94d3ed, 0x24ed2150, 0x0174fffa, 0x07a8007e, 
+    0xc3058008, 0xce33ce33, 0xa5f5f9d8, 0x75ffa675, 0xa475329a, 0xed1f8004, 0x74fff224, 0xa8007e01, 
+    0x05800807, 0x33ce33c3, 0xf5f9d8ce, 0xffa675a5, 0x75329a75, 0x0d1208a4, 0x5f1222c1, 0x4f04909b, 
+    0x1f7ff0ef, 0x12b95c12, 0x04907d14, 0x0970e049, 0x5812e07f, 0x80017fd6, 0x12027f02, 0x90e4d658, 
+    0xa3f02604, 0x770490f0, 0x160490f0, 0x121f7ff0, 0x0490a45d, 0x94d3e049, 0x12064000, 0x9a755e15, 
+    0x02151232, 0x049022f0, 0xe230e017, 0x1ee1202b, 0xe0780490, 0xc36012ff, 0x124e1312, 0x04905214, 
+    0x12ffe079, 0x1312c360, 0x59141252, 0x04901a80, 0x12ffe045, 0x1080e155, 0xe04f0490, 0xb95c12ff, 
+    0xe0460490, 0x735412ff, 0x74110490, 0x7e22f001, 0x64efd308, 0x40809480, 0xa20f120d, 0x12341212, 
+    0x1212a20f, 0xefc3223b, 0x80948064, 0x0f121350, 0xffa775a2, 0x12489a75, 0xa775a20f, 0x479a75ff, 
+    0xa20f1222, 0x75ffa775, 0x0f12449a, 0xffa775a2, 0x22439a75, 0xe0400490, 0x2860f924, 0xf5e40080, 
+    0x80a675a4, 0x75ffa775, 0x0490499a, 0x94d3e049, 0x12235001, 0x107f565e, 0x12125e12, 0x0490c85f, 
+    0xf0077440, 0xef906012, 0x027f0370, 0x424d1222, 0xe04d0490, 0x007fe560, 0x80a47522, 0x757fa675, 
+    0x9a75ffa7, 0xa4f5e4d1, 0x7502a575, 0xa7753fa6, 0xa39a75fc, 0x75501512, 0x9a75c3a7, 0x5f0090a3, 
+    0x750560e0, 0x03801ca5, 0x7504a575, 0xa775ffa6, 0x959a75e3, 0x7510a475, 0x1312efa6, 0x07ad2290, 
+    0x75a4f5e4, 0x0f1201a5, 0x7f0f1258, 0x017f0440, 0x007f0280, 0x75860f12, 0x9a75fba7, 0x72111204, 
+    0xe4ff0f12, 0x7f0f12ff, 0x05ae0440, 0xf4ed0480, 0x1012fe04, 0x12065013, 0x800f7a0e, 0x887f22e8, 
+    0xefb16012, 0x1a700f64, 0x7502a475, 0xa775fda6, 0x9ef5e4ff, 0x90969c75, 0xf0e00004, 0x0444e0a3, 
+    0xf5e422f0, 0xfda675a4, 0xf5ffa775, 0x969c759e, 0xe0000490, 0x54e0a3f0, 0x1222f0fb, 0x8fe4ee5d, 
+    0xf52a8e2b, 0x9028f529, 0x30e06000, 0x2f1208e0, 0x1203706e, 0x0090fa2f, 0xa3fee066, 0xfce4ffe0, 
+    0x121078fd, 0x45efce2c, 0x45eeff2b, 0x45edfe2a, 0x45ecfd29, 0x1222fc28, 0xa775860f, 0x149a7583, 
+    0x12a5f5e4, 0x9a75b70d, 0xdc0e1221, 0x04900760, 0xe030e007, 0x0164ef0c, 0x04901770, 0xe020e009, 
+    0xb40d1210, 0x75219a75, 0xa67540a4, 0x3a1012bf, 0x3b7f2222, 0xefa76012, 0x7eff0754, 0xc006c000, 
+    0x123b7f07, 0x54efa760, 0x1313133f, 0xd0fd1f54, 0xd0ff2de0, 0xc30034e0, 0xff13ef13, 0x3b7f07c0, 
+    0xefb16012, 0xd0fe3f54, 0x22ff2ee0, 0x0f1207ad, 0x7f0f1252, 0x017f0440, 0x007f0280, 0x75860f12, 
+    0x9a75fba7, 0x72111204, 0xe4ff0f12, 0x7f0f12ff, 0x05ae0440, 0xf4ed0480, 0x1012fe04, 0x12065013, 
+    0x800f7a0e, 0x251222e8, 0xac07adbc, 0x5f009006, 0xed0b70e0, 0x14f5e025, 0x13f533ec, 0x25ed1a80, 
+    0x33ecfbe0, 0x04aeedfa, 0x33c30278, 0xd8ce33ce, 0x14f52bf9, 0x13f53aee, 0x14af13ae, 0x123a7f22, 
+    0x54efb160, 0x7f13f53f, 0xb160122c, 0x502b1112, 0x9413e51e, 0xaf03500e, 0x13e52213, 0x501d94d3, 
+    0x13e5c307, 0x22ff0194, 0x9413e5c3, 0xaf22ff02, 0x59122213, 0x8e1c8f53, 0x8c1a8d1b, 0xab1baa19, 
+    0x3604901c, 0xeba3f0ea, 0x121078f0, 0x0490bb2c, 0xa3f0ee34, 0x0490f0ef, 0xa3f0ea22, 0x0490f0eb, 
+    0xa3f0ee20, 0x8f22f0ef, 0x122c7f13, 0x1112b160, 0xe522502b, 0x500e9413, 0xe51a8002, 0x1c94d313, 
+    0x13e50550, 0xe50b8004, 0x2a94d313, 0x13e50c50, 0x80ff0224, 0x1213af02, 0x7f22125f, 0x2f601238, 
+    0x90f91012, 0xffe05604, 0x12b41012, 0xa3a3cb0d, 0x7522f5e0, 0x24752a23, 0xc1401201, 0xef560490, 
+    0x220490f0, 0x90e40e12, 0xffe05604, 0x12df5a02, 0x1212c949, 0xc40d1242, 0x75070f12, 0xa475319a, 
+    0x910f1220, 0x756c0e12, 0x0d12329a, 0x20a575be, 0x12e60d12, 0x9a75b40d, 0x000f1230, 0x22d50e12, 
+    0x75e0a475, 0xa67502a5, 0xfca7751f, 0x75d19e75, 0x0090309c, 0x0c70e05f, 0x7507a475, 0xa775f0a6, 
+    0xb19a75ff, 0x753fa475, 0xa775c0a6, 0xba9a75ff, 0x8e158f22, 0x8c138d14, 0x00e09012, 0x90f00474, 
+    0xf0ef02e0, 0x5c120878, 0x12107800, 0x1878f85b, 0x90f85b12, 0x057400e0, 0x00e090f0, 0xf9e020e0, 
+    0xffe0a322, 0xfefdfce4, 0xe5ce2c12, 0x19f54f19, 0xf54e18e5, 0x4d17e518, 0x16e517f5, 0x2216f54c, 
+    0x14ae15af, 0x12ac13ad, 0xa3bb2c12, 0x1222f0ef, 0xa575c949, 0xffa67538, 0x12329a75, 0xa575be0d, 
+    0xe60d1220, 0x12000f12, 0x0e12d50e, 0x7911126c, 0x75070f12, 0xa475319a, 0x910f1260, 0x56049022, 
+    0x5a12ffe0, 0x570490df, 0x5c12ffe0, 0x0490e4b9, 0xe0a3f044, 0xe15512ff, 0xe0460490, 0x735412ff, 
+    0x90d01312, 0x01744404, 0xe09022f0, 0xe4ffe006, 0x18f5198f, 0x16f517f5, 0x5b120878, 0x121078d9, 
+    0xe0a3d95b, 0xfdfce4ff, 0x121878fe, 0x19afe05b, 0x17ad18ae, 0x0f1222fc, 0x0194d32f, 0x12a32040, 
+    0x94d3320f, 0x90174001, 0x0f120d04, 0x0194d332, 0x12a30c40, 0x94d3320f, 0x7f034001, 0x017f2200, 
+    0x7507ad22, 0x0d121aa5, 0x33ffedf0, 0x12fee095, 0x78efd30f, 0xce33c303, 0xf9d8ce33, 0xf5eea4f5, 
+    0x400f12a5, 0x75b40d12, 0x12222b9a, 0x4a12fa15, 0x12017ffd, 0x027f045d, 0x7f822a12, 0x045d1203, 
+    0x2a12047f, 0x7ffde482, 0x822a0205, 0x2a12fde4, 0x22fde482, 0x75c94912, 0x0d120ca4, 0xe30d12c1, 
+    0x756c0e12, 0x0f12329a, 0xd50e1200, 0x7560a575, 0x9a75ffa6, 0x60a47531, 0x22910f12, 0x06ac07ad, 
+    0xf5a4f5e4, 0x609a75a5, 0xeca4f5ed, 0xa5f58044, 0xaf609a75, 0x027ded05, 0x7d803c12, 0x020a7f02, 
+    0x04907036, 0x01b4e04c, 0x0804900d, 0x870490e0, 0x090490f0, 0x04900b80, 0x0490e006, 0x0490f087, 
+    0x0490e007, 0x1222f088, 0xa475c949, 0xc10d120c, 0x12e30d12, 0x9a756c0e, 0x000f1232, 0x12d50e12, 
+    0x9a75070f, 0x20a47531, 0x22910f12, 0x12c94912, 0x9a756c0e, 0xbe0d1232, 0x75e30d12, 0x0f1202a4, 
+    0x339a75b0, 0x12961112, 0x0f122d12, 0xd50e1200, 0xc9491222, 0x120ca475, 0x0d12c10d, 0x6c0e12e3, 
+    0x12329a75, 0x0e12000f, 0x070f12d5, 0x75319a75, 0x0f1260a4, 0xbf852291, 0xefcbaf2c, 0xedcaadfe, 
+    0x95c306ac, 0x3195ec32, 0x00900750, 0x0144e060, 0x8d318cf0, 0xaf04ae32, 0x49122205, 0x6c0e12c9, 
+    0x75329a75, 0x0d120ca4, 0x20a575c1, 0x12e60d12, 0x9a75b40d, 0x000f1230, 0x22d50e12, 0x75c94912, 
+    0x0d1220a5, 0x000f12e6, 0x12d50e12, 0x11126c0e, 0x070f1279, 0x75319a75, 0x0f1260a4, 0x90e42291, 
+    0x0e121c04, 0x4b0490cd, 0x4d0490f0, 0x90cb0e12, 0xa3f05304, 0x200490f0, 0x12cb0e12, 0x1222ce0e, 
+    0x208f5359, 0x1e8d1f8e, 0x04901d8c, 0xa3f0ee22, 0x1078f0ef, 0x90bb2c12, 0xf0ee2004, 0x22f0efa3, 
+    0x12c94912, 0x9a756c0e, 0x0ca47532, 0x12c10d12, 0x0d12e30d, 0x309a75b4, 0x12000f12, 0x1222d50e, 
+    0x0e12c949, 0x329a756c, 0x75be0d12, 0x0d1210a5, 0xb40d12e6, 0x12309a75, 0x0e12000f, 0x111222d5, 
+    0xc3058080, 0xce33ce33, 0x1012f9d8, 0x2e04908a, 0x901d1012, 0xf0ee2e04, 0x22f0efa3, 0x80801112, 
+    0xce33c305, 0xf9d8ce33, 0x908a1012, 0x10123004, 0x3004901d, 0xefa3f0ee, 0x07ad22f0, 0x12a5f5e4, 
+    0x75edf00d, 0xaea408f0, 0xeea4f5f0, 0x0f12a5f5, 0xb40d1240, 0x222b9a75, 0xf5ed07ad, 0xffa675a5, 
+    0x120d9a75, 0x1312a413, 0x40a47575, 0x12bfa675, 0x13127513, 0x1f7f226f, 0x12a45d12, 0xa4750113, 
+    0xefa67510, 0x12071312, 0xa7754915, 0xd19a75fb, 0xed07ad22, 0xa675a5f5, 0x0d9a75ff, 0x12a41312, 
+    0x15127513, 0x7513127f, 0x226f1312, 0x06aa07ab, 0xebfe5cea, 0xffe0255d, 0xc3fe33ee, 0xeaff9feb, 
+    0x7f22fe9e, 0x2f60123a, 0xfe3f54ee, 0x207c007d, 0xee845f12, 0x04f4efff, 0xe09022ff, 0xf0047400, 
+    0xe090f004, 0xe020e000, 0x00e090f9, 0x22f00674, 0x12a5f5e4, 0x9a75b70d, 0xb40d1230, 0x12309a75, 
+    0x11123410, 0x5f122246, 0x4f04909b, 0x90e4f0ef, 0x90f07704, 0x7ff01604, 0x985e021c, 0x75b11212, 
+    0x13120d9a, 0x751312a4, 0x127f1512, 0x13127513, 0x4912226f, 0x000f12c9, 0x12d50e12, 0x9a75b40d, 
+    0x34101230, 0x8d9e8f22, 0xb4a1e59d, 0xa9adfb02, 0xfeefaaaf, 0x8f22ffed, 0xb4a1e59b, 0xa9adfb02, 
+    0xfeefaaaf, 0x1222ffed, 0x4912be57, 0xd01512c9, 0x12071312, 0xaf220113, 0xe507adbc, 0xfc0354bd, 
+    0x05af04ae, 0xf2101222, 0xf4ef0850, 0xfef4eeff, 0xef220080, 0xa675a4f5, 0xffa775fe, 0x22919a75, 
+    0x9d8d9e8f, 0x02b4a1e5, 0x22a9affb, 0xc9d2c8d2, 0xf5e4cbd2, 0x22cad2bf, 0xe0830490, 0x07b4007f, 
+    0x22017f02, 0xe05f0090, 0x0270007f, 0x8f22017f, 0xb4a1e59b, 0xaaaffb02, 0xe59b8f22, 0xfb02b4a1, 
+    0x9022a9af, 0x54e001e0, 0xef22ff01, 0xe7a20f24, 0xef22ff13, 0xf124e025, 0x222222ff, 0x10000022, 
+    0x30422021, 0x50844063, 0x70c660a5, 0x910881e7, 0xb14aa129, 0xd18cc16b, 0xf1cee1ad, 0x023112ef, 
+    0x22733210, 0x42b55252, 0x62f77294, 0x833993d6, 0xa37bb318, 0xc3bdd35a, 0xe3fff39c, 0x346224de, 
+    0x14200443, 0x74e66401, 0x54a444c7, 0xb56aa585, 0x9528854b, 0xf5eee509, 0xd5acc5cf, 0x2653368d, 
+    0x06111672, 0x66d77630, 0x469556f6, 0xa75bb7b4, 0x8719977a, 0xe7dff738, 0xc79dd7fe, 0x58c448bc, 
+    0x788668e5, 0x184008a7, 0x38022861, 0xd9ccc923, 0xf98ee9ed, 0x994889af, 0xb90aa969, 0x4af55a2b, 
+    0x6ab77ad4, 0x0a711a96, 0x2a333a50, 0xcbfddb12, 0xebbffbdc, 0x8b799b9e, 0xab3bbb58, 0x7ca66c1a, 
+    0x5ce44c87, 0x3c222cc5, 0x1c600c03, 0xfdaeed41, 0xddeccd8f, 0xbd2aadcd, 0x9d688d0b, 0x6e977e49, 
+    0x4ed55eb6, 0x2e133ef4, 0x0e511e32, 0xef9fff70, 0xcfdddfbe, 0xaf1bbffc, 0x8f599f3a, 0x81889178, 
+    0xa1cab1a9, 0xc10cd1eb, 0xe14ef12d, 0x0080106f, 0x20c230a1, 0x400450e3, 0x60467025, 0x93b98367, 
+    0xb3fba398, 0xd33dc3da, 0xf37fe31c, 0x12b1025e, 0x32f32290, 0x523542d2, 0x72776214, 0xa5eab556, 
+    0x85a895cb, 0xe56ef589, 0xc52cd54f, 0x24e2340d, 0x04a014c3, 0x64667481, 0x44245447, 0xb7dba705, 
+    0x979987fa, 0xf75fe7b8, 0xd71dc77e, 0x36d3263c, 0x169106f2, 0x765766b0, 0x56154676, 0xc94cd934, 
+    0xe90ef96d, 0x89c8992f, 0xa98ab9e9, 0x484458ab, 0x68067865, 0x08c01827, 0x288238e1, 0xdb7dcba3, 
+    0xfb3feb5c, 0x9bf98b1e, 0xbbbbabd8, 0x5a754a9a, 0x7a376a54, 0x1af10a16, 0x3ab32ad0, 0xed2efd92, 
+    0xcd6cdd0f, 0xadaabd4d, 0x8de89d8b, 0x6c267cc9, 0x4c645c07, 0x2ca23c45, 0x0ce01c83, 0xff1fefc1, 
+    0xdf5dcf3e, 0xbf9baf7c, 0x9fd98fba, 0x7e176ef8, 0x5e554e36, 0x3e932e74, 0x1ed10eb2, 0x1ca01cf0, 
+    0x1b981b18, 0x1a901a18, 0x19881910, 0x18801808, 0x16801700, 0x157816f8, 0x147015f0, 0x136814e8, 
+    0x126013e8, 0x005812e0, 0x00030000, 0x00090006, 0x000f000c, 0x00150012, 0x001b0018, 0x0021001e, 
+    0x00270024, 0x002d002a, 0x00330030, 0x00390036, 0x003f003c, 0x00450042, 0x004b0048, 0x005d0054, 
+    0x006f0066, 0x007e0078, 0x00050000, 0x000f000a, 0x00190014, 0x0023001e, 0x002d0028, 0x00370032, 
+    0x0041003c, 0x004b0046, 0x00550050, 0x005f005a, 0x00690064, 0x0073006e, 0x007d0078, 0x009b008c, 
+    0x00b900aa, 0x00d200c8, 0x00090000, 0x001b0012, 0x002d0024, 0x003f0036, 0x00510048, 0x0063005a, 
+    0x0075006c, 0x0087007e, 0x00990090, 0x00ab00a2, 0x00bd00b4, 0x00cf00c6, 0x01f000d8, 0x01200108, 
+    0x01500138, 0x00800168, 0x000f0000, 0x002d001e, 0x004b003c, 0x0069005a, 0x00870078, 0x00a50096, 
+    0x00c300b4, 0x00e100d2, 0x01ff00f0, 0x011d010e, 0x013b012c, 0x0159014a, 0x01900168, 0x02e001b8, 
+    0x02300208, 0x1a800258, 0x1c1b1b1a, 0x201f1e1d, 0x24232221, 0x28272625, 0x2a2a2929, 0x25242322, 
+    0x27272626, 0x29292828, 0x2b2b2a2a, 0x2e2d2c2c, 0x0100002f, 0x00000080, 0x90000000, 0x024c77a2, 
+    0x3a061005, 0x77a29000, 0x1005024c, 0x9000440e, 0x024c77a2, 0x4e161005, 0x77a29000, 0x1005024c, 
+    0x9000581e, 0x024c77a2, 0xe6261005, 0x77a29000, 0x1005024c, 0x9000a22e, 0x024c77a2, 0xe6361005, 
+    0x77a29000, 0x1005024c, 0x9000763e, 0x024c77a2, 0x14081005, 0x77a09002, 0x0005024c, 0x90060010, 
+    0x024c74c6, 0x00100185, 0x74c66006, 0x0185024c, 0x60060038, 0x024c7406, 0x00380185, 0x75266056, 
+    0x0185026d, 0x60560038, 0x027d7526, 0x00380185, 0x75266056, 0x01850271, 0x605600d0, 0x02717546, 
+    0x00380185, 0x74066006, 0x0185024c, 0x60060038, 0x024c7403, 0x2a180185, 0x74016006, 0x0185024c, 
+    0x600628e0, 0x024c7401, 0x00000185, 0x77a01006, 0x10050240, 0x60160038, 0x026c7423, 0x00382185, 
+    0x74236016, 0x0185027e, 0x60160038, 0x027a7463, 0x62b80185, 0x74436016, 0x01850272, 0x60160020, 
+    0x02727441, 0x62280185, 0x74416016, 0x01850272, 0x60160030, 0x02727441, 0x00386185, 0x75a1611e, 
+    0x0185027a, 0x611e0038, 0x027a75a1, 0x00380185, 0x75a1611e, 0x0185027a, 0x611e6228, 0x027275c1, 
+    0x00300185, 0x75c16106, 0x61850260, 0x621e0038, 0x027a75a1, 0x00380185, 0x75a1621e, 0x0185027a, 
+    0x621e0038, 0x027a75a1, 0x62280185, 0x75c1621e, 0x01850272, 0x62060030, 0x026075c1, 0x00386185, 
+    0x75a1641e, 0x0185027a, 0x641e0038, 0x027a75a1, 0x00380185, 0x75a1641e, 0x0185027a, 0x641e6228, 
+    0x027275c1, 0x00300185, 0x75c16406, 0x61850260, 0x681e0038, 0x027a75a1, 0x00380185, 0x75a1681e, 
+    0x0185027a, 0x681e0038, 0x027a75a1, 0x62280185, 0x75c1681e, 0x01850272, 0x68060030, 0x026075c1, 
+    0x00386185, 0x7621601e, 0x458502f2, 0x60c60038, 0x02e0f621, 0x00380585, 0x762160c6, 0x058502e0, 
+    0x60866c48, 0x02a07641, 0x6e0b0585, 0x74016086, 0x058503a0, 0x60060030, 0x02207401, 0x00388185, 
+    0x76bf60a6, 0x058506a0, 0x60a60060, 0x04a076dd, 0x00380585, 0x76dd60a6, 0x05850ca0, 0x60a60078, 
+    0x0ca0741d, 0x0038e585, 0x741f6fa6, 0x058d8ca0, 0x6fa60100, 0x8ca0381d, 0x7c04058c, 0x441d6fa6, 
+    0x058c8ca0, 0x6fa60108, 0x8ca0481d, 0x8290058c, 0x141d6fa6, 0x058c8ca0, 0x60a68632, 0x8ca0181d, 
+    0x8404018c, 0x441d6fa6, 0x058c8ca0, 0x6fa6a090, 0x8ca0141d, 0x0038058c, 0x141b6fa6, 0x01cc8ca0, 
+    0x6fa688b0, 0x8ca0141d, 0x8ee801cc, 0x181d60a6, 0x018c8ca0, 0x60a68a33, 0x8ca0181d, 0x931b018c, 
+    0x141d60a6, 0x019c8ca0, 0x60a68a33, 0x8ca0181d, 0x971b018c, 0x141d60a6, 0x019c8ca0, 0x60a68a33, 
+    0x8ca0181d, 0x9b1b018c, 0x141d60a6, 0x019c8ca0, 0x60a68a33, 0x8ca0181d, 0x9f1b018c, 0x141d60a6, 
+    0x019c8ca0, 0x60a68a33, 0x8ca0181d, 0x7433018c, 0x141d60a7, 0x018c8ca0, 0x6f060033, 0x0ca0141d, 
+    0x0038a18d, 0x741f6fa6, 0x058d8ca0, 0x6fa60100, 0x8ca0381d, 0xa804058c, 0x441d6fa6, 0x058c8ca0, 
+    0x6fa60108, 0x8ca0481d, 0xac04058c, 0x441d6fa6, 0x058c8ca0, 0x6fa6b498, 0x8ca0281d, 0xb004058c, 
+    0x441d6fa6, 0x058c8ca0, 0x6fa6b498, 0x8ca0281d, 0x7633058c, 0x281d6f07, 0xa18d0ca0, 0x60a60038, 
+    0x8ca0281d, 0x0038059c, 0x281d60a6, 0x059c8ca0, 0x60a6bb10, 0x8ca0281d, 0xbc33059c, 0x241d50a6, 
+    0x059c8ca0, 0x60a6bf10, 0x8ca0281d, 0xc110059c, 0x281d60a6, 0x059c8ca0, 0x50a6c233, 0x8ca0241d, 
+    0xc510059c, 0x281d60a6, 0x059c8ca0, 0x60a6c710, 0x8ca0281d, 0xc833059c, 0x241d50a6, 0x059c8ca0, 
+    0x60a6e510, 0x8ca0281d, 0x0038059c, 0x141b60a6, 0x05dc8ca0, 0x60a6ccb0, 0x8ca0141d, 0xd2e801dc, 
+    0x181d60a6, 0x019c8ca0, 0x60a6ce33, 0x8ca0181d, 0xd71b019c, 0x141d60a6, 0x019c8ca0, 0x60a6ce33, 
+    0x8ca0181d, 0xdb1b019c, 0x141d60a6, 0x019c8ca0, 0x60a6ce33, 0x8ca0181d, 0xdf1b019c, 0x141d60a6, 
+    0x019c8ca0, 0x60a6ce33, 0x8ca0181d, 0xe31b019c, 0x141d60a6, 0x019c8ca0, 0x60a6ce33, 0x8ca0181d, 
+    0x7433019c, 0x141d60a7, 0x019c8ca0, 0x60077833, 0x0ca0141d, 0x0038a19d, 0x773f6fa6, 0x058d8ca0, 
+    0x6fa60100, 0x8ca03b3d, 0xec04058c, 0x441d6fa6, 0x058c8ca0, 0x6fa60108, 0x8ca04b3d, 0xf0c0058c, 
+    0x4b5d6fa6, 0x058c8ca0, 0x50a6f233, 0x8ca0273d, 0xf4c0058c, 0x4b5d6fa6, 0x058c8ca0, 0x50a6f633, 
+    0x8ca0273d, 0xfec0058c, 0x4b5d6fa6, 0x058c8ca0, 0x50a6fa33, 0x8ca0273d, 0xfec0058c, 0x4b5d6fa6, 
+    0x058c8ca0, 0x6fa72033, 0x8ca01737, 0x0038058c, 0x273d60a6, 0x059c8ca0, 0x60a60038, 0x8ca02f3d, 
+    0x06c8059c, 0x2b5d60a7, 0x059c8ca0, 0x60a72033, 0x8ca02737, 0x0038018c, 0x141b60a6, 0x05dc8ca0, 
+    0x60a708b0, 0x8ca0141d, 0x0ee801dc, 0x181d60a7, 0x019c8ca0, 0x60a70a33, 0x8ca0141d, 0x131b019c, 
+    0x141d60a7, 0x019c8ca0, 0x60a70a33, 0x8ca0181d, 0x171b019c, 0x141d60a7, 0x019c8ca0, 0x60a70a33, 
+    0x8ca0181d, 0x1b1b019c, 0x141d60a7, 0x019c8ca0, 0x60a70a33, 0x8ca0181d, 0x1f1b019c, 0x141d60a7, 
+    0x019c8ca0, 0x60a70a33, 0x8ca0181d, 0x7433019c, 0x141d60a7, 0x019c8ca0, 0x60a60038, 0xdca0273d, 
+    0x0038059a, 0x275d60a6, 0x059adca0, 0x60a730c8, 0xdca02b5d, 0x2833059a, 0x241d50a7, 0x059adca0, 
+    0x60a730c8, 0xdca02b5d, 0x2c33059a, 0x241d50a7, 0x059adca0, 0x60a730c8, 0xdca02b5d, 0x4a33059a, 
+    0x273760a7, 0x059edca0, 0x60a60038, 0xdca0273b, 0x32b0059a, 0x273d60a7, 0x019adca0, 0x60a738e8, 
+    0xdca0181d, 0x3433019a, 0x181d60a7, 0x019adca0, 0x60a73d1b, 0xdca0141d, 0x3433019a, 0x181d60a7, 
+    0x019adca0, 0x60a7411b, 0xdca0141d, 0x3433019a, 0x181d60a7, 0x019adca0, 0x60a7451b, 0xdca0141d, 
+    0x3433019a, 0x181d60a7, 0x019adca0, 0x60a7491b, 0xdca0141d, 0x3433019a, 0x181d60a7, 0x019adca0, 
+    0x60a77433, 0x8ca0141d, 0x0038019c, 0x273d60a6, 0x059aeca0, 0x60a60038, 0xeca0275d, 0x5ac8059a, 
+    0x2f5d60a7, 0x059aeca0, 0x50a75233, 0xeca0241d, 0x5ac8059a, 0x2f5d60a7, 0x059aeca0, 0x50a75633, 
+    0xeca0241d, 0x5ac8059a, 0x2f5d60a7, 0x059aeca0, 0x60077c33, 0x6c20273d, 0x0038a19b, 0x271b60a6, 
+    0x059aeca0, 0x60a75cb0, 0xeca0271d, 0x62e8019a, 0x181d60a7, 0x019aeca0, 0x60a75e33, 0xeca0181d, 
+    0x671b019a, 0x141d60a7, 0x019aeca0, 0x60a75e33, 0xeca0181d, 0x6b1b019a, 0x141d60a7, 0x019aeca0, 
+    0x60a75e33, 0xeca0181d, 0x6f1b019a, 0x141d60a7, 0x019aeca0, 0x60a75e33, 0xeca0181d, 0x731b019a, 
+    0x141d60a7, 0x019aeca0, 0x60a75e33, 0xeca0181d, 0x7433019a, 0x141d60a7, 0x019c8ca0, 0x60062433, 
+    0x026c0002, 0x7630c005, 0x141d6f07, 0xa18d0ca0, 0x60077830, 0x0ca0141d, 0x7a30a19d, 0x141d6007, 
+    0xa19b5ca0, 0x60077c30, 0x6ca0141d, 0x7e33a19b, 0x00000001, 0xa0000000, 0x00018033, 0x00000000, 
+    0x8233a000, 0x00000001, 0xa0000000, 0x00018433, 0x00000000, 0x8633a000, 0x00000001, 0xa0000000, 
+    0x00018833, 0x00000000, 0x8a33a000, 0x00000001, 0xa0000000, 0x00018c33, 0x00000000, 0x8e33a000, 
+    0x00000001, 0xa0000000, 0x00019033, 0x00000000, 0x9233a000, 0x00000001, 0xa0000000, 0x00019433, 
+    0x00000000, 0x9633a000, 0x00000001, 0xa0000000, 0x0d81259d
+};
diff --git a/drivers/net/bcmbca/phy/mdio_drv_common.c b/drivers/net/bcmbca/phy/mdio_drv_common.c
new file mode 100644
index 0000000000..2753f50640
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mdio_drv_common.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Aug 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * MDIO common functions
+ */
+
+#include "mdio_drv_common.h"
+#if defined(DSL_DEVICES)
+/* TODO_DSL: SF2 based is little endian, no need to byte swap, but need to figure out how to use access_macros.h instead */
+#define WRITE_32(a, r)			( *(volatile uint32_t*)(a) = *(uint32_t*)&(r) )
+#define READ_32(a, r)			( *(volatile uint32_t*)&(r) = *(volatile uint32_t*) (a) )
+#else
+#include "access_macros.h"
+#endif
+
+#define MDIO_BUSY_RETRY         2000
+#define CHECK_MDIO_READY(x)     if (!is_mdio_ready(x)) {ret = MDIO_ERROR; goto Exit;}
+
+typedef enum
+{
+    MDIO_CLAUSE_45 = 0,
+    MDIO_CLAUSE_22 = 1,
+} mdio_clause_t;
+
+typedef enum
+{
+    MDIO22_WRITE = 1,
+    MDIO22_READ = 2,
+} mdio22_op_t;
+
+typedef enum
+{
+    MDIO45_ADDRESS = 0,
+    MDIO45_WRITE = 1,
+    MDIO45_READINC = 2,
+    MDIO45_READ = 3,
+} mdio45_op_t;
+
+#if defined(CONFIG_BCM963178) || defined(CONFIG_BCM947622)
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+#define _BYTE_ORDER_LITTLE_ENDIAN_
+#endif
+#endif
+
+#ifdef _BYTE_ORDER_LITTLE_ENDIAN_
+#pragma pack(push, 1)
+typedef struct
+{
+    uint32_t data_addr:16;
+    uint32_t reg_dev_addr:5;
+    uint32_t phy_prt_addr:5;
+    uint32_t op_code:2;
+    uint32_t fail:1;
+    uint32_t busy:1;
+    uint32_t reserved:2;
+} mdio_cmd_reg_t;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct
+{
+    uint32_t mdio_clause:1;
+    uint32_t unused1:3;
+    uint32_t mdio_clk_divider:8;
+    uint32_t unused2:1;
+    uint32_t free_run_clk_enable:1;
+    uint32_t unused3:18;
+} mdio_cfg_reg_t;
+#pragma pack(pop)
+#else
+#pragma pack(push, 1)
+typedef struct
+{
+    uint32_t reserved:2;
+    uint32_t busy:1;
+    uint32_t fail:1;
+    uint32_t op_code:2;
+    uint32_t phy_prt_addr:5;
+    uint32_t reg_dev_addr:5;
+    uint32_t data_addr:16;
+} mdio_cmd_reg_t;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct
+{
+    uint32_t unused3:18;
+    uint32_t free_run_clk_enable:1;
+    uint32_t unused2:1;
+    uint32_t mdio_clk_divider:8;
+    uint32_t unused1:3;
+    uint32_t mdio_clause:1;
+} mdio_cfg_reg_t;
+#pragma pack(pop)
+#endif
+
+static int32_t is_mdio_ready(uint32_t *p)
+{
+    uint32_t retry = MDIO_BUSY_RETRY;
+    mdio_cmd_reg_t cmd;
+
+    do {
+        READ_32(p, cmd);
+        if (!cmd.busy)
+            break;
+        udelay(10);
+    } while (retry--);
+
+    if (!retry)
+    {
+        printk("MDIO Error: mdio_is_ready() reached maximum retries of %d\n", MDIO_BUSY_RETRY);
+        return 0;
+    }
+
+    if (cmd.fail)
+    {
+        printk("MDIO Error: MDIO got failure status on phy %d\n", cmd.phy_prt_addr);
+        memset(&cmd, 0, sizeof(cmd));
+        WRITE_32(p, cmd);
+        return 0;
+    }
+
+    return 1;
+}
+
+static void mdio_cfg_clause_mode(uint32_t *p, mdio_clause_t mdio_clause)
+{
+    mdio_cfg_reg_t cfg;
+
+    READ_32(p, cfg);
+    cfg.free_run_clk_enable = 1;
+#if defined(CONFIG_BCM96846) || defined(CONFIG_BCM96856) || defined(CONFIG_BCM96878)
+    cfg.mdio_clk_divider = 12;
+#endif
+    cfg.mdio_clause = mdio_clause;
+    WRITE_32(p, cfg);
+}
+
+int32_t mdio_cmd_read_22(uint32_t *p, uint32_t addr, uint32_t reg, uint16_t *val)
+{
+    int ret = MDIO_OK;
+    mdio_cmd_reg_t cmd = {};
+
+    mdio_cfg_clause_mode(p + 1, MDIO_CLAUSE_22);
+
+    cmd.op_code = MDIO22_READ;
+    cmd.phy_prt_addr = addr;
+    cmd.reg_dev_addr = reg;
+    cmd.busy = 1;
+    WRITE_32(p, cmd);
+
+    CHECK_MDIO_READY(p);
+
+    READ_32(p, cmd);
+    *val = cmd.data_addr;
+
+Exit:
+    return ret;
+}
+
+int32_t mdio_cmd_write_22(uint32_t *p, uint32_t addr, uint32_t reg, uint16_t val)
+{
+    int ret = MDIO_OK;
+    mdio_cmd_reg_t cmd = {};
+
+    mdio_cfg_clause_mode(p + 1, MDIO_CLAUSE_22);
+
+    cmd.op_code = MDIO22_WRITE;
+    cmd.phy_prt_addr = addr;
+    cmd.reg_dev_addr = reg;
+    cmd.data_addr = val;
+    cmd.busy = 1;
+    WRITE_32(p, cmd);
+
+    CHECK_MDIO_READY(p);
+
+Exit:
+    return ret;
+}
+
+int32_t mdio_cmd_read_45(uint32_t *p, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t *val)
+{
+    int ret = MDIO_OK;
+    mdio_cmd_reg_t cmd = {};
+
+    mdio_cfg_clause_mode(p + 1, MDIO_CLAUSE_45);
+
+    cmd.op_code = MDIO45_ADDRESS;
+    cmd.phy_prt_addr = addr;
+    cmd.reg_dev_addr = dev;
+    cmd.data_addr = reg;
+    cmd.busy = 1;
+    WRITE_32(p, cmd);
+
+    CHECK_MDIO_READY(p);
+
+    cmd.op_code = MDIO45_READ;
+    cmd.busy = 1;
+    WRITE_32(p, cmd);
+
+    CHECK_MDIO_READY(p);
+
+    READ_32(p, cmd);
+    *val = cmd.data_addr;
+
+Exit:
+    return ret;
+}
+
+int32_t mdio_cmd_write_45(uint32_t *p, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t val)
+{
+    int ret = MDIO_OK;
+    mdio_cmd_reg_t cmd = {};
+
+    mdio_cfg_clause_mode(p + 1, MDIO_CLAUSE_45);
+
+    cmd.op_code = MDIO45_ADDRESS;
+    cmd.phy_prt_addr = addr;
+    cmd.reg_dev_addr = dev;
+    cmd.data_addr = reg;
+    cmd.busy = 1;
+    WRITE_32(p, cmd);
+
+    CHECK_MDIO_READY(p);
+
+    cmd.op_code = MDIO45_WRITE;
+    cmd.data_addr = val;
+    cmd.busy = 1;
+    WRITE_32(p, cmd);
+
+    CHECK_MDIO_READY(p);
+
+Exit:
+    return ret;
+}
diff --git a/drivers/net/bcmbca/phy/mdio_drv_common.h b/drivers/net/bcmbca/phy/mdio_drv_common.h
new file mode 100644
index 0000000000..674627dd7a
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mdio_drv_common.h
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Aug 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * MDIO common functions
+ */
+
+#ifndef __MDIO_DRV_COMMON_H__
+#define __MDIO_DRV_COMMON_H__
+
+#include "os_dep.h"
+
+#define MDIO_ERROR  -1
+#define MDIO_OK      0
+
+int32_t mdio_cmd_read_22(uint32_t *p, uint32_t addr, uint32_t reg, uint16_t *val);
+int32_t mdio_cmd_write_22(uint32_t *p, uint32_t addr, uint32_t reg, uint16_t val);
+int32_t mdio_cmd_read_45(uint32_t *p, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t *val);
+int32_t mdio_cmd_write_45(uint32_t *p, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t val);
+
+#endif
diff --git a/drivers/net/bcmbca/phy/mdio_drv_impl3.h b/drivers/net/bcmbca/phy/mdio_drv_impl3.h
new file mode 100644
index 0000000000..fada1fd570
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mdio_drv_impl3.h
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+#ifndef __MDIO_DRV_IMPL3_H
+#define __MDIO_DRV_IMPL3_H
+
+#include "os_dep.h"
+
+#define MDIO_ERROR     -1
+#define MDIO_OK        0
+
+extern int32_t mdio_read_c22_register(uint8_t core_num, uint32_t phy_addr, uint32_t reg_addr, uint16_t *data_read);
+extern int32_t mdio_write_c22_register(uint8_t core_num, uint32_t phy_addr, uint32_t reg_addr, uint16_t data_write);
+
+extern int32_t mdio_read_c45_register(uint8_t core_num, uint32_t port_addr, uint32_t dev_addr, uint16_t dev_offset, uint16_t *data_read);
+extern int32_t mdio_write_c45_register(uint8_t core_num, uint32_t port_addr, uint32_t dev_addr,uint16_t dev_offset, uint16_t data_write);
+
+
+#endif
diff --git a/drivers/net/bcmbca/phy/mdio_drv_impl5.c b/drivers/net/bcmbca/phy/mdio_drv_impl5.c
new file mode 100644
index 0000000000..5d14a5b9b1
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mdio_drv_impl5.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: June 2017
+ *      Author: dima.mamut@broadcom.com
+ */
+
+/*
+ * MDIO driver for BCM96846 6856 and 6878
+ */
+
+#include "os_dep.h"
+#include "mdio_drv_impl5.h"
+#include "dt_access.h"
+
+static uintptr_t mdio_base;
+static uintptr_t pMdioMasterSelect;
+
+static int mdio_probe(dt_device_t *pdev)
+{
+    int ret;
+
+    mdio_base = dt_dev_remap_resource(pdev, 0);
+    if (IS_ERR(mdio_base))
+    {
+        ret = PTR_ERR(mdio_base);
+        mdio_base = NULL;
+        dev_err(&pdev->dev, "Missing mdio_base entry\n");
+        goto Exit;
+    }
+
+    pMdioMasterSelect = dt_dev_remap_resource(pdev, 1);
+    if (IS_ERR(pMdioMasterSelect))
+    {
+        ret = PTR_ERR(pMdioMasterSelect);
+        pMdioMasterSelect = NULL;
+        dev_err(&pdev->dev, "Missing MdioMasterSelect entry\n");
+        goto Exit;
+    }
+
+    dev_dbg(&pdev->dev, "mdio_base=0x%lx\n", mdio_base);
+    dev_dbg(&pdev->dev, "pMdioMasterSelect=0x%lx\n", pMdioMasterSelect);
+
+    dev_info(&pdev->dev, "registered\n");
+
+    return 0;
+
+Exit:
+    return ret;
+}
+
+#ifdef __UBOOT__
+static const struct udevice_id mdio_ids[] = {
+#if defined(CONFIG_BCM63146) || defined(CONFIG_BCM4912) 
+    { .compatible = "brcm,mdio-sf2" },      //FIXME! redirect mdio-sf2 to mdio5 for now
+#else
+    { .compatible = "brcm,mdio5" },
+#endif
+    { /* end of list */ },
+};
+
+U_BOOT_DRIVER(brcm_mdio) = {
+    .name	= "brcm-mdio",
+    .id	= UCLASS_MISC,
+    .of_match = mdio_ids,
+    .probe = mdio_probe,
+};
+#else
+static const struct of_device_id of_platform_table[] = {
+    { .compatible = "brcm,mdio5" },
+    { /* end of list */ },
+};
+
+static struct platform_driver of_platform_driver = {
+    .driver = {
+        .name = "brcm-mdio",
+        .of_match_table = of_platform_table,
+    },
+    .probe = mdio_probe,
+};
+module_platform_driver(of_platform_driver);
+#endif
+
+#define MDIO_CMD        (void *)mdio_base
+
+static DEFINE_SPINLOCK(mdio_access);
+
+static void mdio_cfg_type(mdio_type_t type)
+{
+#if defined(CONFIG_BCM63146) || defined(CONFIG_BCM4912)
+    if (type != MDIO_INT)
+#else
+    if (type == MDIO_INT)
+#endif
+        *(uint32_t *)pMdioMasterSelect = 0;
+    else
+        *(uint32_t *)pMdioMasterSelect = 1;
+}
+
+int32_t mdio_read_c22_register(mdio_type_t type, uint32_t addr, uint32_t reg, uint16_t *val)
+{
+    int ret = MDIO_OK;
+
+    spin_lock_bh(&mdio_access);
+    mdio_cfg_type(type);
+    ret =  mdio_cmd_read_22(MDIO_CMD, addr, reg, val);
+    spin_unlock_bh(&mdio_access);
+
+    return ret;
+}
+EXPORT_SYMBOL(mdio_read_c22_register);
+
+int32_t mdio_write_c22_register(mdio_type_t type, uint32_t addr, uint32_t reg, uint16_t val)
+{
+    int ret = MDIO_OK;
+
+    spin_lock_bh(&mdio_access);
+    mdio_cfg_type(type);
+    ret = mdio_cmd_write_22(MDIO_CMD, addr, reg, val);
+    spin_unlock_bh(&mdio_access);
+
+    return ret;
+}
+EXPORT_SYMBOL(mdio_write_c22_register);
+
+int32_t mdio_read_c45_register(mdio_type_t type, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t *val)
+{
+    int ret = MDIO_OK;
+
+    spin_lock_bh(&mdio_access);
+    mdio_cfg_type(type);
+    ret = mdio_cmd_read_45(MDIO_CMD, addr, dev, reg, val);
+    spin_unlock_bh(&mdio_access);
+
+    return ret;
+}
+EXPORT_SYMBOL(mdio_read_c45_register);
+
+int32_t mdio_write_c45_register(mdio_type_t type, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t val)
+{
+    int ret = MDIO_OK;
+
+    spin_lock_bh(&mdio_access);
+    mdio_cfg_type(type);
+    ret = mdio_cmd_write_45(MDIO_CMD, addr, dev, reg, val);
+    spin_unlock_bh(&mdio_access);
+
+    return ret;
+}
+EXPORT_SYMBOL(mdio_write_c45_register);
+
+
diff --git a/drivers/net/bcmbca/phy/mdio_drv_impl5.h b/drivers/net/bcmbca/phy/mdio_drv_impl5.h
new file mode 100644
index 0000000000..aaa9d7f738
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mdio_drv_impl5.h
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: June 2017
+ *      Author: dima.mamut@broadcom.com
+ */
+
+/*
+ * MDIO driver for BCM96846 ,BCM96878 and BCM96856 
+ */
+
+#ifndef __MDIO_DRV_IMPL5_H__
+#define __MDIO_DRV_IMPL5_H__
+
+#include "mdio_drv_common.h"
+
+typedef enum
+{
+    MDIO_EXT = 0,
+    MDIO_INT = 1,
+} mdio_type_t;
+
+int32_t mdio_read_c22_register(mdio_type_t type, uint32_t addr, uint32_t reg, uint16_t *val);
+int32_t mdio_write_c22_register(mdio_type_t type, uint32_t addr, uint32_t reg, uint16_t val);
+int32_t mdio_read_c45_register(mdio_type_t type, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t *val);
+int32_t mdio_write_c45_register(mdio_type_t type, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t val);
+
+#endif	//__MDIO_DRV_IMPL5_H__
diff --git a/drivers/net/bcmbca/phy/mdio_drv_sf2.c b/drivers/net/bcmbca/phy/mdio_drv_sf2.c
new file mode 100644
index 0000000000..c83eb82ec8
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mdio_drv_sf2.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2013 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Nov 2016
+ *      Author: steven.hsieh@broadcom.com
+ */
+
+/*
+ * MDIO driver for StarFighter2 - 4908/63138/63148/63158
+ */
+
+#include "mdio_drv_sf2.h"
+#include "dt_access.h"
+
+#ifdef __UBOOT__
+#define spin_lock_bh(x)
+#define spin_unlock_bh(x)
+#else
+#include <linux/spinlock.h>
+DEFINE_SPINLOCK(mdio_access);
+#endif
+
+static uintptr_t switch_mdio_base;
+static uintptr_t switch_reg_base;
+
+static int mdio_probe(dt_device_t *pdev)
+{
+    int ret;
+
+    switch_mdio_base = dt_dev_remap_resource(pdev, 0);
+    if (IS_ERR(switch_mdio_base))
+    {
+        ret = PTR_ERR(switch_mdio_base);
+        switch_mdio_base = NULL;
+        dev_err(&pdev->dev, "Missing switch_mdio_base entry\n");
+        goto Exit;
+    }
+    dev_dbg(&pdev->dev, "switch_mdio_base=0x%lx\n", switch_mdio_base);
+
+#if defined(CONFIG_BCM963138) || defined(CONFIG_BCM963148) || defined(CONFIG_BCM94908)
+    switch_reg_base = dt_dev_remap_resource(pdev, 1);
+    if (IS_ERR(switch_reg_base))
+    {
+        ret = PTR_ERR(switch_reg_base);
+        switch_reg_base = NULL;
+        dev_err(&pdev->dev, "Missing switch_reg_base entry\n");
+        goto Exit;
+    }
+    dev_dbg(&pdev->dev, "switch_reg_base=0x%lx\n", switch_reg_base);
+#endif
+
+    dev_info(&pdev->dev, "registered\n");
+
+    return 0;
+
+Exit:
+    return ret;
+}
+
+#ifdef __UBOOT__
+static const struct udevice_id mdio_ids[] = {
+    { .compatible = "brcm,mdio-sf2" },
+    { /* end of list */ },
+};
+
+U_BOOT_DRIVER(brcm_mdio) = {
+    .name	= "brcm-mdio",
+    .id	= UCLASS_MISC,
+    .of_match = mdio_ids,
+    .probe = mdio_probe,
+};
+#else
+static const struct of_device_id of_platform_table[] = {
+    { .compatible = "brcm,mdio-sf2" },
+    { /* end of list */ },
+};
+
+static struct platform_driver of_platform_driver = {
+    .driver = {
+        .name = "brcm-mdio",
+        .of_match_table = of_platform_table,
+    },
+    .probe = mdio_probe,
+};
+module_platform_driver(of_platform_driver);
+#endif
+
+#define SWITCH_MDIO_BASE        (void *)switch_mdio_base
+#define SWITCH_REG_BASE         (void *)switch_reg_base
+
+#if defined(CONFIG_BCM963138) || defined(CONFIG_BCM963148) || defined(CONFIG_BCM94908)
+#define SF2_MDIO_MASTER                     0x01
+
+static void sf2_mdio_master_enable(void)
+{
+    volatile uint32_t *sw_ctrl_reg = (void *)(SWITCH_REG_BASE);
+    uint32_t val32 = *sw_ctrl_reg;
+    
+    val32 |= SF2_MDIO_MASTER;
+    *sw_ctrl_reg = val32;
+}
+
+static void sf2_mdio_master_disable(void)
+{
+    volatile uint32_t *sw_ctrl_reg = (void *)(SWITCH_REG_BASE);
+    uint32_t val32 = *sw_ctrl_reg;
+    val32 &= ~SF2_MDIO_MASTER;
+    *sw_ctrl_reg = val32;
+}
+#else
+#define sf2_mdio_master_enable()
+#define sf2_mdio_master_disable()
+#endif
+
+int32_t mdio_read_c22_register(mdio_type_t type, uint32_t addr, uint32_t reg, uint16_t *val)
+{
+    int ret = MDIO_OK;
+
+    spin_lock_bh(&mdio_access);
+    sf2_mdio_master_disable();
+
+    /* Read twice for DSL based chip requested by hardware */
+    ret = mdio_cmd_read_22((void *)SWITCH_MDIO_BASE, addr, reg, val);
+    ret += mdio_cmd_read_22((void *)SWITCH_MDIO_BASE, addr, reg, val);
+
+    sf2_mdio_master_enable();
+    spin_unlock_bh(&mdio_access);
+
+    return ret;
+}
+EXPORT_SYMBOL(mdio_read_c22_register);
+
+int32_t mdio_write_c22_register(mdio_type_t type, uint32_t addr, uint32_t reg, uint16_t val)
+{
+    int ret = MDIO_OK;
+
+    spin_lock_bh(&mdio_access);
+    sf2_mdio_master_disable();
+
+    ret = mdio_cmd_write_22((void *)SWITCH_MDIO_BASE, addr, reg, val);
+
+    sf2_mdio_master_enable();
+    spin_unlock_bh(&mdio_access);
+
+    return ret;
+}
+EXPORT_SYMBOL(mdio_write_c22_register);
+
+int32_t mdio_read_c45_register(mdio_type_t type, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t *val)
+{
+    int ret = MDIO_OK;
+
+    spin_lock_bh(&mdio_access);
+    sf2_mdio_master_disable();
+
+    ret = mdio_cmd_read_45((void *)SWITCH_MDIO_BASE, addr, dev, reg, val);
+
+    sf2_mdio_master_enable();
+    spin_unlock_bh(&mdio_access);
+
+    return ret;
+}
+EXPORT_SYMBOL(mdio_read_c45_register);
+
+int32_t mdio_write_c45_register(mdio_type_t type, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t val)
+{
+    int ret = MDIO_OK;
+
+    spin_lock_bh(&mdio_access);
+    sf2_mdio_master_disable();
+
+    ret = mdio_cmd_write_45((void *)SWITCH_MDIO_BASE, addr, dev, reg, val);
+
+    sf2_mdio_master_enable();
+    spin_unlock_bh(&mdio_access);
+
+    return ret;
+}
+EXPORT_SYMBOL(mdio_write_c45_register);
diff --git a/drivers/net/bcmbca/phy/mdio_drv_sf2.h b/drivers/net/bcmbca/phy/mdio_drv_sf2.h
new file mode 100644
index 0000000000..bf267472ff
--- /dev/null
+++ b/drivers/net/bcmbca/phy/mdio_drv_sf2.h
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Nov 2016
+ *      Author: steven.hsieh@broadcom.com
+ */
+
+/*
+ * MDIO driver for StarFighter2 - 4908/63138/63148/63158
+ */
+
+#ifndef __MDIO_DRV_SF2_H__
+#define __MDIO_DRV_SF2_H__
+
+#include "mdio_drv_common.h"
+
+typedef enum
+{
+    MDIO_SF2,   // for SF2 based, this type is not used.
+} mdio_type_t;
+
+int32_t mdio_read_c22_register(mdio_type_t type, uint32_t addr, uint32_t reg, uint16_t *val);
+int32_t mdio_write_c22_register(mdio_type_t type, uint32_t addr, uint32_t reg, uint16_t val);
+int32_t mdio_read_c45_register(mdio_type_t type, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t *val);
+int32_t mdio_write_c45_register(mdio_type_t type, uint32_t addr, uint32_t dev, uint16_t reg, uint16_t val);
+
+#endif
diff --git a/drivers/net/bcmbca/phy/orca_a0_firmware.h b/drivers/net/bcmbca/phy/orca_a0_firmware.h
new file mode 100644
index 0000000000..9ea6c6984d
--- /dev/null
+++ b/drivers/net/bcmbca/phy/orca_a0_firmware.h
@@ -0,0 +1,6739 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Aug 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Firmware for external 2.5G/5G/10G phys: Orca BCM84880, BCM84881, BCM84884, BCM84888
+ */
+
+char orca_a0_version[] = "Orca A0 v01-01-02-2017-10-20";
+
+uint32_t orca_a0_firmware[] = {
+    0xea000016, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe320f000, 0xe59ff018, 0xe59ff018, 
+    0x000001d4, 0x00029704, 0x00029664, 0x000289b0, 0x000282d8, 0x00000000, 0x0002865c, 0x0002843c, 
+    0x0002cfe8, 0xc0de512e, 0x00000000, 0x00000000, 0x000077c8, 0x000347b0, 0x00002081, 0x00000000, 
+    0xe59f0148, 0xe5901000, 0xe3510000, 0x0a000004, 0xe3a01000, 0xe5801000, 0xe59f0134, 0xe5801000, 
+    0xea000006, 0xe59f012c, 0xe580e000, 0xe59f0120, 0xe5901000, 0xe2811001, 0xe5801000, 0xe25ef004, 
+    0xe59f1114, 0xe3a0011a, 0xe5810000, 0xe59f110c, 0xee091f11, 0xe59fa108, 0xe59fb108, 0xe59fc108, 
+    0xe51f0088, 0xe51f1088, 0xe1a02000, 0xe1500001, 0x1a000003, 0xee110f30, 0xe3c0040e, 0xee010f30, 
+    0xea00002c, 0xe3a01805, 0xe51f209c, 0xe2820004, 0xe8a00002, 0xe1500001, 0x3afffffc, 0xe51f00bc, 
+    0xe3500000, 0x1a000023, 0xe51f20bc, 0xe3a01000, 0xe1cc10b0, 0xe3e00000, 0xe59f70b0, 0xe3a09008, 
+    0xe4d13001, 0xe3a08000, 0xe7e043d3, 0xe7e05fd0, 0xe0346005, 0xe1a00080, 0x0a000000, 0xe0200007, 
+    0xe1a03083, 0xe2888001, 0xe1580009, 0xbafffff5, 0xe1510002, 0xbafffff1, 0xe5912000, 0xe58a0000, 
+    0xe58b2000, 0xe3e03000, 0xe1520003, 0x0a000001, 0xe1500002, 0x1a00000a, 0xe3a02912, 0xe51f3134, 
+    0xe0821003, 0xe51f314c, 0xe8b30030, 0xe8a20030, 0xe1520001, 0x1afffffb, 0xe3a03901, 0xe1cc30b0, 
+    0xe51ff188, 0xe3a03902, 0xe1cc30b0, 0xeafffffe, 0xc300003c, 0xc3000038, 0xc300000c, 0xc2000010, 
+    0x00040021, 0x00000048, 0x0000004c, 0xd03c801a, 0x04c11db7, 0xebffffff, 0xebffffff, 0xebffffff, 
+    0xebffffff, 0xe3a01401, 0xee110f10, 0xe1800001, 0xe3c00a02, 0xee010f10, 0xee110f30, 0xe3800040, 
+    0xe3800501, 0xee010f30, 0xe59f0084, 0xe3a010d1, 0xe121f001, 0xe1a0d000, 0xe3a010d2, 0xe121f001, 
+    0xe2400080, 0xe1a0d000, 0xe3a010d7, 0xe121f001, 0xe2400c02, 0xe1a0d000, 0xe3a010db, 0xe121f001, 
+    0xe2400080, 0xe1a0d000, 0xe3a010d3, 0xe121f001, 0xe2400080, 0xe1a0d000, 0xe3a010df, 0xe121f001, 
+    0xe2400c02, 0xe1a0d000, 0xe3a010d3, 0xe121f001, 0xe59f0024, 0xe59f1018, 0xe59f2024, 0xe4802004, 
+    0xe1500001, 0xbafffffc, 0xeb000007, 0xe59fc014, 0xe12fff1c, 0x00047800, 0x00047000, 0x0003d59c, 
+    0x0003eb9c, 0xa5a5a5a5, 0x000002d4, 0xe3a00701, 0xe3a02008, 0xee191f11, 0xe2011d3e, 0xe1811000, 
+    0xe1811102, 0xe3811001, 0xee091f11, 0xf57ff04f, 0xe12fff1e, 0xfa000000, 0xfa000036, 0xe890a00a, 
+    0x44820c00, 0xf1aa4483, 0x45da0701, 0xf000d101, 0xf2aff863, 0xe8ba0e09, 0xf013000f, 0xbf180f01, 
+    0xf0431afb, 0x47180301, 0x0002b7a8, 0x0002b808, 0xf04f440a, 0xf8100c00, 0xf0133b01, 0xbf080407, 
+    0x4b01f810, 0xbf08111d, 0x5b01f810, 0xd0051e64, 0x6b01f810, 0xf8011e64, 0xd1f96b01, 0x0f08f013, 
+    0xf810bf1e, 0x1cad4b01, 0xd1091b0c, 0xbf581e6d, 0xcb01f801, 0xe005d5fa, 0x6b01f814, 0x6b01f801, 
+    0xd5f91e6d, 0xd3d64291, 0x00004770, 0xbf243a10, 0xc178c878, 0x0752d8fa, 0xc830bf24, 0xbf44c130, 
+    0x600c6804, 0x00004770, 0x24002300, 0x26002500, 0xbf283a10, 0xd8fbc178, 0xbf280752, 0xbf48c130, 
+    0x4770600b, 0xe89db51f, 0xf0270003, 0xf027fca2, 0xbd1ffbc8, 0xbd10b510, 0xff0ff027, 0xf7ff4611, 
+    0xf000fff1, 0xf027f8d7, 0xb403ff2d, 0xfff2f7ff, 0xf027bc03, 0x0000ff5b, 0xf8d1490b, 0x684ac000, 
+    0x3b04f85c, 0x44186810, 0x0b04f842, 0xbf28458c, 0x0cdcf1a1, 0xbf28428a, 0x02dcf1a1, 0xc000f8c1, 
+    0xf020604a, 0x47704000, 0x0003d534, 0x4ff8e92d, 0x0800f04f, 0x0005468a, 0x46464604, 0xd0184647, 
+    0xf02a4608, 0x4602fa6d, 0x2000460b, 0x4180f04f, 0xfab2f029, 0x9124f8df, 0x20004602, 0x4649460b, 
+    0xf892f02a, 0x464b2200, 0xffd2f029, 0x91004683, 0x2000e00c, 0xe8bd4601, 0x4b408ff8, 0x22000864, 
+    0x46394630, 0xffc4f029, 0x460f4606, 0xd8f42c01, 0x46394630, 0xfa00f02a, 0x20014601, 0xf02a4088, 
+    0x4604fa28, 0x46284689, 0xfa3af02a, 0x4622464b, 0xf86af02a, 0x9b00e035, 0x4620465a, 0xf02a4629, 
+    0xd332fa43, 0xe0232000, 0x462b4622, 0x46194610, 0xfa76f02a, 0x46042200, 0x0801f108, 0xf04f460d, 
+    0xf02a4380, 0xd811fb6b, 0xfa002001, 0xf02af008, 0x4602fa00, 0x4921460b, 0xf02a2000, 0x4632f845, 
+    0xf029463b, 0x4606ff85, 0xe004460f, 0x0001f109, 0x46814550, 0xf04fd3d8, 0x462032ff, 0xf02b4629, 
+    0x45d0f876, 0x460d4604, 0x4630d3c5, 0xe7a24639, 0x4606b570, 0x461d4614, 0x0104e9dd, 0xf9acf02a, 
+    0x4630b2c1, 0xff72f7ff, 0x462b4622, 0xfc44f02a, 0x4b0c4a0b, 0xf818f02a, 0x22004b0b, 0xfa30f02a, 
+    0xf04f4b0a, 0xf02a3233, 0x4b09fb5f, 0xf02a2200, 0xf02afa27, 0xb280f991, 0x0000bd70, 0x3ff00000, 
+    0x4ea4a8c1, 0x400a9340, 0x40340000, 0x40333333, 0x40240000, 0xbf90f002, 0xe28fc0bf, 0xe12fff1c, 
+    0x68124afb, 0xd00b4210, 0x68104afa, 0x6f00f5b0, 0x4bf9da06, 0xf843681b, 0x68101020, 0x60101c40, 
+    0xb5104770, 0xf7ff4604, 0x2000ffeb, 0xf948f007, 0x46204601, 0x4010e8bd, 0xb570e7e2, 0x4605460c, 
+    0xf00948ee, 0x4621f8dc, 0xf7ff4628, 0x4cebffea, 0x68214628, 0xffd4f7ff, 0x46286861, 0xffd0f7ff, 
+    0x462868a1, 0xffccf7ff, 0x462868e1, 0x4070e8bd, 0xb570e7c6, 0x4605460c, 0xf00948e1, 0x4621f962, 
+    0xf7ff4628, 0x48dfffce, 0xf2402200, 0xf02871ff, 0x4601f8f4, 0xf7ff4628, 0x4cd9ffb3, 0xf9b48861, 
+    0xeb000000, 0x46284101, 0xffaaf7ff, 0xf9b488e1, 0xeb000004, 0x46284101, 0x4070e8bd, 0xb570e7a0, 
+    0x48cb4605, 0x42056800, 0x188cd016, 0x4621b152, 0xf7ff4628, 0x2000ff95, 0xf8f2f007, 0x46284601, 
+    0xff8ef7ff, 0x880849c8, 0xf3c01c40, 0x60080009, 0x680949c6, 0x4020f841, 0x48c5bd70, 0xb5102100, 
+    0xf893f028, 0x212048c2, 0xf0283064, 0x48c1f88e, 0x22462100, 0x0400f640, 0x80428001, 0x80c18081, 
+    0x48bd4621, 0xf0296800, 0x48b3f877, 0x68004621, 0xf862f029, 0x00a148b9, 0xe8bd6800, 0xf0294010, 
+    0xb570b86b, 0xf240b281, 0xf3c01500, 0x2008040e, 0x52b8f04f, 0xffb3f7ff, 0xd8032cff, 0xb2e049ad, 
+    0xe0043108, 0x4f50f5b4, 0x49add205, 0xf851b2e0, 0x47800020, 0x48a64605, 0x30644629, 0xf855f028, 
+    0x462148a3, 0xf851f028, 0xf64f48a1, 0x307471ff, 0xf84bf028, 0xf248489e, 0xe8bd0100, 0x30704070, 
+    0xb843f028, 0xf241489a, 0xb5101122, 0xf0283066, 0x4897f83c, 0x30642108, 0xf837f028, 0xbd102008, 
+    0xf00eb510, 0xb2c1f9cd, 0x30684891, 0xf82df028, 0x88014894, 0x3066488e, 0xf827f028, 0xbd102004, 
+    0xb510488b, 0xf0283068, 0x498ef81d, 0x20018008, 0xfb41f00e, 0xbd102004, 0xb510488b, 0x0000f990, 
+    0x4883b281, 0xf0283066, 0x2004f810, 0x4880bd10, 0x3066b510, 0xf806f028, 0x70084983, 0xbd102004, 
+    0xb5104882, 0x487a7801, 0xf0273066, 0x4880fffe, 0x48777801, 0xf0273068, 0x487efff8, 0x48747801, 
+    0xf027306a, 0x2004fff2, 0x4871bd10, 0x3066b510, 0xffe8f027, 0xb2c04975, 0x28014c75, 0xd0037008, 
+    0x70202000, 0xbd102004, 0x30684869, 0xffdaf027, 0x4871e7f7, 0xb5104971, 0x78097800, 0xeb000180, 
+    0x496f1001, 0xeb007809, 0x496e0081, 0x44087809, 0x485fb281, 0xf0273066, 0x486bffc8, 0xffc2f027, 
+    0x485b4601, 0xf0273068, 0x4867ffc0, 0xf0271c80, 0x4601ffb9, 0x306a4856, 0xffb7f027, 0x1d004862, 
+    0xffb0f027, 0x48524601, 0xf027306c, 0x485fffae, 0x01017800, 0x306e484e, 0xffa7f027, 0xbd102004, 
+    0xb570484b, 0xf0273066, 0x4604ff9d, 0x306e4848, 0xff98f027, 0xb2054953, 0x0003f004, 0xf3c47008, 
+    0x494f0081, 0xf3c47008, 0x494c1001, 0xf3c47008, 0x49491081, 0x483e7008, 0xf0273068, 0x494cff83, 
+    0x483b8008, 0xf027306a, 0x494aff7d, 0x48388008, 0xf027306c, 0x4948ff77, 0x04208008, 0xf3c5d502, 
+    0xe0001006, 0x49412000, 0x20047008, 0xb510bd70, 0x22014c42, 0x46202102, 0xff8ff027, 0x482c4601, 
+    0xf0273066, 0x2206ff62, 0x21404620, 0xff85f027, 0x48274601, 0xf0273068, 0x2205ff58, 0x21204620, 
+    0xff7bf027, 0x48224601, 0xf027306a, 0x2004ff4e, 0x481fbd10, 0x3066b510, 0xff44f027, 0x22014c2f, 
+    0x46032102, 0xf0274620, 0x4819ff5a, 0xf0273068, 0x2206ff39, 0x21404603, 0xf0274620, 0x4814ff50, 
+    0xf027306a, 0x2205ff2f, 0x21204603, 0xf0274620, 0x2004ff46, 0x480ebd10, 0x3012b510, 0xff22f027, 
+    0x0101f000, 0x3066480a, 0xff1ff027, 0xbd102004, 0x00047ffc, 0x00047ff0, 0x000301c0, 0x0003113c, 
+    0x00030350, 0xd0030430, 0x00047ff4, 0x00047ff8, 0xd03c800a, 0x00030004, 0x000301bc, 0x000301b8, 
+    0x00030134, 0x00030250, 0x00030374, 0x0003028c, 0x0003028d, 0x000302d5, 0x000302aa, 0x000302a9, 
+    0x00030258, 0x00030257, 0xd0035118, 0x00030259, 0x0003025c, 0x0003025e, 0x00030260, 0xd28e0040, 
+    0xb51048fc, 0x48fc7801, 0xfedff027, 0xe7be2004, 0xb51048f9, 0xfed6f027, 0x700849f6, 0xe7b62004, 
+    0x4cf6b510, 0x22042300, 0x46202110, 0xfee7f027, 0x46202300, 0x21202205, 0xfee1f027, 0x230048ee, 
+    0x461a2101, 0xf0273854, 0x2004feda, 0xb570e79f, 0x230f4cea, 0x46192200, 0xf0274620, 0xf240fed0, 
+    0x1ca07507, 0xf0274629, 0x1d20feb0, 0xf0274629, 0x2301feac, 0x22044620, 0xf0272110, 0x2301fec0, 
+    0x22054620, 0xf0272120, 0x48dbfeba, 0x22002301, 0x38544619, 0xfeb3f027, 0xbd702004, 0x41f0e92d, 
+    0xf02748d5, 0x4607fe8f, 0x1c8048d3, 0xfe8af027, 0x48d14604, 0xf0271d00, 0x4606fe85, 0x1d8048ce, 
+    0xfe80f027, 0x46052f18, 0x2f1cd00f, 0x2f0fd012, 0x2f17d015, 0x2100d019, 0x403148c7, 0x300840e9, 
+    0xfe73f027, 0xe8bd2004, 0xb67281f0, 0xf005b2e0, 0xe012fed3, 0xb2e0b672, 0xfef7f005, 0xb672e00d, 
+    0x2101b2e0, 0xff1ef005, 0xb672e007, 0xf3c4b2e2, 0xf3c42103, 0xf0053041, 0xb281ff4e, 0xe7dbb662, 
+    0x41fce92d, 0xf02748b4, 0x4607fe4d, 0x1c8048b2, 0xfe48f027, 0x48b04604, 0xf0271d00, 0x4605fe43, 
+    0x1d8048ad, 0xfe3ef027, 0x48ab4606, 0xf0273008, 0x2f18fe39, 0xd0064680, 0xd0182f1c, 0xd01e2f0f, 
+    0xd0242f17, 0xb672e030, 0x4643b2e0, 0xb272b229, 0xfea1f005, 0x2c02b662, 0x06a8d126, 0x489ed524, 
+    0x03a1220f, 0x383c4643, 0xfe39f027, 0xb672e01c, 0x4643b2e0, 0xb272b229, 0xfeb4f005, 0xb672e013, 
+    0x4643b2e0, 0xb272b229, 0xfedff005, 0xb672e00b, 0xe9cdb271, 0xb22b1800, 0xf3c4b2e2, 0xf3c42103, 
+    0xf0053041, 0xb662ff0a, 0xe8bd2004, 0x488c81fc, 0x7801b510, 0xf0274888, 0x488afdf8, 0x48867801, 
+    0xf0271c80, 0x2004fdf2, 0x4883e6d1, 0xf027b510, 0x4983fde9, 0x48807008, 0xf0271c80, 0x4981fde3, 
+    0x20047008, 0x4880e6c3, 0x7800b510, 0xd0112803, 0x48792100, 0xfdd9f027, 0x7801487c, 0x1c804876, 
+    0xfdd3f027, 0x7801487a, 0x1d004873, 0xfdcdf027, 0xe6ac2004, 0xe7ec2101, 0xb510486f, 0xfdc2f027, 
+    0x70084972, 0xe6a22004, 0xb5104872, 0x0000f990, 0xd0092804, 0xd0072805, 0xd0052803, 0xd0242802, 
+    0xd0222801, 0xe6922008, 0x23014c64, 0x46192200, 0x46203c82, 0xfdc3f027, 0x46202301, 0x21082203, 
+    0xfdbdf027, 0x46202301, 0x21042202, 0xfdb7f027, 0xf0271ca0, 0x1d20fd97, 0xfd94f027, 0x46202300, 
+    0x461a2101, 0xfdabf027, 0x4c5be03b, 0x220f2301, 0x462003d9, 0xfda3f027, 0x46202301, 0x0399220e, 
+    0xfd9df027, 0x46202301, 0x461a2102, 0xfd97f027, 0x46202300, 0x21022201, 0xfd91f027, 0x46202301, 
+    0x46192200, 0xfd8bf027, 0x3c0a4c4b, 0xf0274620, 0x4620fd69, 0xfd66f027, 0x46201ca4, 0xfd62f027, 
+    0xf0274620, 0x1ca4fd5f, 0xf0274620, 0x4620fd5b, 0xfd58f027, 0x46201ca4, 0xfd54f027, 0xf0274620, 
+    0x2004fd51, 0xe92de633, 0x483347f0, 0xfd4af027, 0xb2c44d31, 0x1cad4837, 0xf1051cae, 0xf9900804, 
+    0xf1050000, 0x28040906, 0x2805d008, 0x2803d006, 0x2802d004, 0x2801d062, 0xe093d060, 0x23014f27, 
+    0x3f822203, 0x46382108, 0xfd49f027, 0x46382301, 0x21042202, 0xfd43f027, 0x2c01b114, 0xe081d01b, 
+    0x387e481e, 0xfd1ef027, 0x46284601, 0xfd1df027, 0x3880481a, 0xfd16f027, 0x46304601, 0xfd15f027, 
+    0x38764816, 0xfd0ef027, 0x46404601, 0xfd0df027, 0x38784812, 0x4811e019, 0xf027387a, 0x4601fd03, 
+    0xf0274628, 0x480dfd02, 0xf027387c, 0x4601fcfb, 0xf0274630, 0x4809fcfa, 0xf0273872, 0x4601fcf3, 
+    0xf0274640, 0x4805fcf2, 0xf0273874, 0x4601fceb, 0xe0454648, 0x000302a5, 0xd03c8070, 0xd003526c, 
+    0x000302a6, 0x000302a7, 0x00030394, 0x000302ac, 0x000303a6, 0x000301dc, 0xd28f215e, 0x2c01b114, 
+    0xe02fd011, 0x46204cfb, 0xfcccf027, 0x46304601, 0xfccbf027, 0xf0274620, 0x4601fcc5, 0xf0274628, 
+    0x1ca4fcc4, 0x4cf3e010, 0x46201ea4, 0xfcbaf027, 0x46304601, 0xfcb9f027, 0xf0274620, 0x4601fcb3, 
+    0xf0274628, 0x1ea4fcb2, 0xf0274620, 0x4601fcab, 0xf0274648, 0x4620fcaa, 0xfca4f027, 0x46404601, 
+    0xfca3f027, 0xe8bd2004, 0x48e387f0, 0xf027b510, 0x4ce2fc99, 0x48e07020, 0xf0271e80, 0x7821fc93, 
+    0xf00db2c0, 0x2004fdd8, 0xb570e571, 0x0500f244, 0x220e48db, 0xf0274629, 0x4cd7fcb0, 0xb1781ea4, 
+    0x220e48d7, 0x38444629, 0xfca7f027, 0x48d4b140, 0x21012200, 0xf0273850, 0xb108fca0, 0xe0002101, 
+    0x46202100, 0xfc71f027, 0x780148cc, 0xf02748ca, 0x2004fc6c, 0x49cbbd70, 0xb5102000, 0x46022301, 
+    0x46197008, 0xf02748c8, 0x48c7fc7a, 0xf0273044, 0x4601fc59, 0x1e8048c0, 0xfc57f027, 0x304648c2, 
+    0xfc50f027, 0x48bc4601, 0xfc4ff027, 0x304848be, 0xfc48f027, 0x48b84601, 0xf0271c80, 0x48bafc46, 
+    0xf027304a, 0x4601fc3f, 0x1d0048b3, 0xfc3df027, 0xe51c2004, 0xb51048b5, 0x48af7801, 0xf0271e80, 
+    0x2004fc34, 0x48ace513, 0x1e80b510, 0xfc2af027, 0x700849ae, 0xe50a2004, 0xb51048ad, 0x48a67801, 
+    0xf0271e80, 0x48abfc22, 0x48a37801, 0xfc1df027, 0xe4fc2004, 0xb51048a0, 0xf0271e80, 0x49a4fc13, 
+    0x489d7008, 0xfc0ef027, 0x700849a2, 0xe4ee2004, 0x4ca1b510, 0x0000f994, 0x4897b281, 0xf0271e80, 
+    0x7820fc04, 0xd1072802, 0x305e4893, 0xfbfaf027, 0x48914601, 0xfbf9f027, 0xe4d82004, 0xe92d488e, 
+    0x1e8041f0, 0xfbeef027, 0xb2404993, 0x4f934d8a, 0x8224f8df, 0x4e913566, 0x28023710, 0xf1087008, 
+    0xd040085e, 0x2300488e, 0x88002203, 0x20c0f3c0, 0x21087008, 0xf0274638, 0x2300fbdb, 0x22014628, 
+    0xf0272102, 0x2301fbec, 0x220a4628, 0xf0270299, 0x2301fbe6, 0x220b4628, 0xf02702d9, 0x2301fbe0, 
+    0x21024638, 0xf027461a, 0x2301fbc3, 0x21024630, 0xf027461a, 0x2300fbbd, 0x22014638, 0xf0272102, 
+    0x2300fbb7, 0x22014630, 0xf0272102, 0x2300fbb1, 0x21014628, 0xf027461a, 0x2100fbc2, 0xf0274640, 
+    0x2004fba4, 0x4864e52f, 0xfb9cf027, 0x2c1ab2c4, 0x2c2ad00b, 0x2c3ad009, 0x2c0bd007, 0x2c0cd005, 
+    0x2c0dd003, 0x2c0ed001, 0x4621d1eb, 0xf0274640, 0x2208fb8c, 0x23014628, 0xf0270151, 0x2301fba0, 
+    0x22094628, 0xf0270259, 0x2301fb9a, 0x22004628, 0xf0274619, 0x4859fb94, 0x3030495a, 0xfb6ff027, 
+    0x46302301, 0x21042202, 0xfb72f027, 0x46382301, 0x21042202, 0xfb6cf027, 0x22004853, 0xf990b261, 
+    0xf0180000, 0x4951fad7, 0x70082001, 0x4850e7b9, 0x7801b510, 0x1e804840, 0xfb57f027, 0x7801484d, 
+    0xf027483d, 0x2004fb52, 0x483be431, 0x1e80b510, 0xfb48f027, 0x70084946, 0xf0274837, 0x4945fb43, 
+    0x20047008, 0x4834e423, 0x4c43b570, 0xf0271e80, 0x07c0fb39, 0x4c41d000, 0xf9947861, 0x78e20000, 
+    0x2001ea40, 0xf994b281, 0xea400002, 0x79622002, 0xf994b286, 0xea400004, 0xb2852002, 0x0006f994, 
+    0x4825b284, 0xfb21f027, 0x46314823, 0xf0271c80, 0x4821fb1c, 0x1d004629, 0xfb17f027, 0x4621481e, 
+    0xf0271d80, 0x2004fb12, 0x481bbd70, 0x4c2ab570, 0x1e802500, 0xfb06f027, 0xd00107c0, 0x25014c27, 
+    0x46304e15, 0xfafef027, 0x46307020, 0xfafaf027, 0x70601200, 0x46301cb6, 0xfaf4f027, 0x463070a0, 
+    0xfaf0f027, 0x70e01200, 0x46301cb6, 0xfaeaf027, 0x46307120, 0xfae6f027, 0x71601200, 0xf0271cb0, 
+    0x4629fae1, 0x462071a0, 0xfb98f026, 0x2008b108, 0xe025bd70, 0xd28f2158, 0xd03c8072, 0x000302e4, 
+    0xd28f2050, 0x00030279, 0xd0030406, 0x000302d8, 0x000302db, 0x000302dc, 0x00030342, 0xc8000160, 
+    0x00030344, 0x00501bd0, 0x00030222, 0x000302dd, 0x000302a8, 0x00030394, 0x0003cd5c, 0x0003cd66, 
+    0xe7d52004, 0x4cfeb510, 0xf02748fe, 0x07c0faab, 0x4cfdd000, 0x1c8048fb, 0xf0277a61, 0x48f9faa6, 
+    0x1d007a21, 0xfaa1f027, 0xe4ad2004, 0x4cf4b570, 0x48f42500, 0xfa96f027, 0xd00107c0, 0x25014cf2, 
+    0x1c8048f0, 0xfa8ef027, 0x48ee7260, 0xf0271d00, 0xb2c1fa89, 0x7a607221, 0xf025462a, 0x2004f81c, 
+    0x2003e7a6, 0xf026b510, 0xb281f920, 0xf02748e5, 0x2004fa7c, 0xf919f026, 0x48e2b281, 0xf0271c80, 
+    0x2005fa74, 0xf911f026, 0x48deb281, 0xf0271d00, 0x2006fa6c, 0xf909f026, 0x48dab281, 0xf0271d80, 
+    0x2004fa64, 0xe92de470, 0x48d641ff, 0xfa5af027, 0x700849d6, 0xf00848d6, 0x4ed5fa42, 0x4fd52400, 
+    0xf8dfad02, 0x20008354, 0x463a49d4, 0xe9cd4643, 0xf8560100, 0xf7ff0024, 0xf825f8fb, 0x1c640014, 
+    0x2c04b264, 0x48c7dbef, 0x1008f8bd, 0xf0271c80, 0x48c4fa3c, 0x100af8bd, 0xf0271d00, 0x48c1fa36, 
+    0x100cf8bd, 0xf0271d80, 0x48befa30, 0x100ef8bd, 0xf0273008, 0x2004fa2a, 0xe683b004, 0xb5102000, 
+    0xf8c3f026, 0x48b7b281, 0xfa1ff027, 0xe42b2004, 0xb51048b4, 0xfa16f027, 0x600849b9, 0x1c8048b1, 
+    0xfa10f027, 0x600849b7, 0x1d0048ae, 0xfa0af027, 0x700849b5, 0xe4172004, 0xb51048b1, 0xb2818800, 
+    0xf02748a8, 0x48affa02, 0xb2818800, 0x1c8048a5, 0xf9fbf027, 0x780148ac, 0x1d0048a2, 0xf9f5f027, 
+    0xe40f2004, 0xb510489f, 0xf9ecf027, 0x600849a7, 0x1c80489c, 0xf9e6f027, 0x600849a5, 0x1d004899, 
+    0xf9e0f027, 0x600849a3, 0xe4122004, 0xb510489f, 0xb2818800, 0xf0274893, 0x489df9d8, 0xb2818800, 
+    0x1c804890, 0xf9d1f027, 0x8800489a, 0x488db281, 0xf0271d00, 0x2004f9ca, 0x4897e405, 0x7801b510, 
+    0xf0274888, 0x2004f9c2, 0x4886e40d, 0xf027b510, 0x4991f9b9, 0x20047008, 0xe92de405, 0x200841f0, 
+    0x0144f248, 0x52b8f04f, 0xf8f9f7ff, 0x26004c8b, 0x78204f7c, 0xd1092801, 0x46382200, 0xf0272103, 
+    0xb918f9cc, 0x70064886, 0xfa94f00d, 0x46382200, 0xf0272103, 0x2202f9c2, 0x211c7020, 0xf0274638, 
+    0x4980f9bc, 0x70082205, 0x46382120, 0xf9b5f027, 0x81b0f8df, 0x4c7c2801, 0x0802f108, 0x2208d10d, 
+    0x7100f64f, 0xf0274640, 0xf029f9a8, 0xf06ffa29, 0xf02a0207, 0xe9c4f89c, 0x22060100, 0x21404638, 
+    0xf99bf027, 0x28014d71, 0x2200d10c, 0x21ff4640, 0xf993f027, 0xfa14f029, 0x0204f06f, 0xf887f02a, 
+    0x0100e9c5, 0x46382207, 0xf0272180, 0x2801f986, 0x4968d103, 0xe9c44866, 0x22080100, 0x01514638, 
+    0xf97bf027, 0xd1032801, 0x48634964, 0x0100e9c5, 0xf2402209, 0x46382100, 0xf96ff027, 0xd1012801, 
+    0x7006485f, 0xf240220a, 0x46384100, 0xf965f027, 0xd1012801, 0x7006485b, 0xe5932004, 0x41f0e92d, 
+    0xf2482008, 0xf04f0145, 0xf7ff52b8, 0x4854f878, 0x7400f64f, 0x22084d3b, 0x78034621, 0xf0274628, 
+    0x4950f93e, 0x46282200, 0x21ff780b, 0xf937f027, 0x22084945, 0x0100e9d1, 0xf839f02a, 0xf97cf029, 
+    0x4621b283, 0x22081cad, 0xf0274628, 0x483ff928, 0xe9d02205, 0xf02a0100, 0xf029f82a, 0xb283f96d, 
+    0x22004628, 0xf02721ff, 0x4834f91a, 0x22001cae, 0x78032103, 0xf0274630, 0x4831f912, 0x210c2202, 
+    0x46307803, 0xf90bf027, 0x22044d2e, 0x46302170, 0xf027782b, 0x2300f904, 0x7180f64f, 0x46302207, 
+    0xf8fdf027, 0x1cb5782a, 0xb1521cae, 0x2a014c2e, 0x2a02d07e, 0x2100d07d, 0xf0274628, 0x2100f8d6, 
+    0x4f2ae095, 0xe9d72203, 0xf0290100, 0xf029fff0, 0x28fff903, 0x20ffdb00, 0x4628b283, 0x21ff2200, 
+    0xf8ddf027, 0xe9d72203, 0xf0290102, 0xf029ffe0, 0x28fff8f3, 0x20ffdb00, 0xb2834621, 0xe0372208, 
+    0x0003cd5c, 0xd03c8070, 0x0003cd66, 0x00030279, 0x0003113c, 0xb573eab3, 0x4030ab15, 0x40300000, 
+    0x00030290, 0x00030294, 0x0003028f, 0x0003029c, 0x000302a0, 0x00030298, 0x0003028e, 0x00030300, 
+    0x000302ec, 0x00030301, 0x000302f0, 0x000302f8, 0xb71758e2, 0x3fae00d1, 0x538ef34d, 0x3ff42474, 
+    0x000302ed, 0x000302ee, 0x0003cd70, 0x0003cd90, 0xf0274628, 0x2203f894, 0x0104e9d7, 0xff97f029, 
+    0xf8aaf029, 0xdb0028ff, 0xb28320ff, 0x22004630, 0xf02721ff, 0x2203f884, 0x0106e9d7, 0xff87f029, 
+    0xf89af029, 0xdb0028ff, 0xb28320ff, 0xe0012208, 0xe00fe005, 0x46304621, 0xf871f027, 0xe9d4e01a, 
+    0xf0290100, 0xb281f8b9, 0xf0274628, 0xe9d4f84e, 0xe0090102, 0x0104e9d4, 0xf8aef029, 0x4628b281, 
+    0xf843f027, 0x0106e9d4, 0xf8a6f029, 0x4630b281, 0xf83bf027, 0xe4952004, 0x5ff0e92d, 0x841cf8df, 
+    0x46402100, 0xf831f027, 0x0902f108, 0x46482100, 0xf82bf027, 0x0a04f108, 0x46502100, 0xf825f027, 
+    0x0b06f108, 0x46582100, 0xf81ff027, 0x4ffd4cfc, 0x88204dfd, 0x417ff5a0, 0xd01339ff, 0x28017838, 
+    0x2204d110, 0x21104628, 0xf837f027, 0x46062203, 0x46282108, 0xf831f027, 0xd1014286, 0xe0002000, 
+    0x80202001, 0x0000f997, 0x4640b281, 0xfffdf026, 0x46488821, 0xfff9f026, 0x46282204, 0xf0272110, 
+    0x4601f81c, 0xf0264650, 0x2203fff0, 0x21084628, 0xf813f027, 0x46584601, 0xffe7f026, 0xe8bd2004, 
+    0xe92d9ff0, 0x48dd5ff0, 0xffdcf026, 0x46044ddc, 0x70fff64f, 0x42818829, 0x2008d108, 0x0137f248, 
+    0x52b8f04f, 0xff1bf7fe, 0xe7e82008, 0xf04f4ed5, 0x49d20a02, 0x1c898028, 0xf9964fd4, 0xf1010000, 
+    0xf8df0b02, 0xf8df834c, 0x4284934c, 0x2c01d026, 0xf8a5d014, 0x200aa000, 0xf0067034, 0x2301f8f8, 
+    0x220a48cd, 0x4621029c, 0xffb2f026, 0x230148ca, 0x4621220a, 0xf0261d00, 0xe024ffab, 0xf0264608, 
+    0x7038ffa1, 0xf0264658, 0xf888ff9d, 0x48bb0000, 0xf0261d80, 0xf889ff97, 0xe7dc0000, 0xd1102c01, 
+    0xf0264608, 0x7038ff8f, 0xf0264658, 0xf888ff8b, 0x48b20000, 0xf0261d80, 0xf889ff85, 0xf00d0000, 
+    0xf8a5ff96, 0x2004a000, 0xb570e799, 0xf02648ab, 0x4604ff79, 0x1c8048a9, 0xff74f026, 0x4404ea40, 
+    0x1d8048a6, 0xff6ef026, 0x48a44605, 0xf0261d00, 0xb148ff69, 0xf0264620, 0x4601ff65, 0x3008489f, 
+    0xff63f026, 0xe4832004, 0x46204629, 0x48a4e7f8, 0x4ca2b510, 0x60206800, 0x606048a2, 0x60a048a2, 
+    0x60e048a2, 0x612048a2, 0x616048a2, 0x61a048a2, 0x61e048a2, 0x622048a2, 0x680048a2, 0x48a26260, 
+    0x200062a0, 0x632062e0, 0x63a06360, 0xf834f023, 0x462063e0, 0x4889b281, 0xf0261d80, 0x4620ff36, 
+    0x48860c01, 0xf0261d00, 0x4884ff30, 0xf0262110, 0x2004ff2c, 0x4889e489, 0xb281b510, 0x1d80487f, 
+    0xff23f026, 0x0c014885, 0x1d00487c, 0xff1df026, 0xe47a2004, 0xb5104879, 0xf0261d80, 0x4604ff13, 
+    0x1d004876, 0xff0ef026, 0x4400eb04, 0xb2818820, 0x1c804872, 0xff09f026, 0x0c016820, 0xf026486f, 
+    0x2004ff04, 0x486de461, 0x1d80b570, 0xfefaf026, 0x486a4604, 0xf0261d00, 0xeb04fef5, 0x48674400, 
+    0xf0261c80, 0x4605feef, 0xf0264864, 0xeb05feeb, 0x60204000, 0xe40b2004, 0x41f0e92d, 0x25004e6f, 
+    0x24004f72, 0x0044eb07, 0xfedcf026, 0x01c5eb04, 0xb2241c64, 0xf8262c08, 0xdbf30011, 0xb22d1c6d, 
+    0xdbee2d40, 0xe5982004, 0xb5104854, 0xf0261d80, 0x4c5ffec9, 0x48516020, 0xf0261d00, 0x6821fec3, 
+    0x4000ea41, 0x20046020, 0xb510e41f, 0x88204c58, 0x484ab281, 0xf0261d80, 0x6820feb8, 0x48470c01, 
+    0xf0261d00, 0x2004feb2, 0xb538e40f, 0xf0264843, 0xb245fea9, 0x1c804841, 0xfea4f026, 0x483fb244, 
+    0xf0261d00, 0xb242fe9f, 0x0000f04f, 0xd0062d01, 0x46214b4a, 0x20019000, 0xfb8bf004, 0x494ce00a, 
+    0xeb014a46, 0x560b1104, 0x3020f842, 0xb2401c40, 0xdbf82810, 0xbd382004, 0x2000493b, 0x6008b510, 
+    0x0100f640, 0x68004836, 0xfe66f027, 0x2100482b, 0xfe7bf026, 0xe4152004, 0x2208482b, 0x41f0e92d, 
+    0x38540151, 0xfe99f026, 0x22054d24, 0x46032120, 0x46283d56, 0xfe83f026, 0x22024c36, 0x46202104, 
+    0xfe8bf026, 0x4603220d, 0x0100f242, 0xf0264628, 0x2202fe76, 0x21044620, 0xfe7ff026, 0x22004e17, 
+    0x46032101, 0x46303e4e, 0xfe69f026, 0x22024c2b, 0xf9944829, 0x5c431000, 0x4628211c, 0xfe5ff026, 
+    0x22094827, 0x6100f240, 0x46287803, 0xfe57f026, 0x22074824, 0xf0262180, 0x2201fe60, 0x21024603, 
+    0xf0264628, 0x7820fe4c, 0xf842f00d, 0x0000f994, 0xd0392805, 0xd0392804, 0x0000e03c, 0xd03c8070, 
+    0x000302e8, 0x0003021b, 0xd28f2056, 0x000302e5, 0x000302e6, 0x000302e7, 0xc1000030, 0x00037d0c, 
+    0x000301c0, 0x00047ff8, 0x00047ff0, 0x00047ff4, 0x00047ffc, 0x00047c00, 0x00047c40, 0x00047800, 
+    0x00047c80, 0x000301bc, 0x00037aec, 0xd003612e, 0x00030fec, 0xd2054084, 0x0002b6de, 0x00030222, 
+    0x00030394, 0xd28f2404, 0xe00048fd, 0x780048fd, 0xd0512800, 0x220048fc, 0xf0262101, 0xf994fe0e, 
+    0xea411000, 0xb28300c0, 0x22014630, 0xf026211e, 0x48f6fdf6, 0x28017800, 0x4cf5d140, 0x21012200, 
+    0xf0264620, 0x2200fdfa, 0x21014603, 0xf0264628, 0x48f0fde6, 0x21402206, 0x46287803, 0xfddff026, 
+    0x0700f640, 0x220b48ec, 0xf0264639, 0x220bfde6, 0x46394603, 0xf0264628, 0x2202fdd2, 0x21044620, 
+    0xfddbf026, 0x4603220c, 0x46280079, 0xfdc7f026, 0x46202202, 0xf0262104, 0x2205fdd0, 0x21204603, 
+    0xf0264630, 0x49ddfdbc, 0x22064630, 0x21c0780b, 0x41f0e8bd, 0xbdb3f026, 0xe7b52303, 0xb510e45d, 
+    0xfb64f026, 0x4604b281, 0xf02648d5, 0x48d4fd8e, 0x1c800c21, 0xfd89f026, 0xe65b2004, 0xf24148d0, 
+    0xb5102134, 0xf0261d00, 0x4ccefd80, 0xb2814620, 0x1c8048cb, 0xfd79f026, 0x0c014620, 0xf02648c8, 
+    0xf026fd74, 0x6020fb53, 0xfb70f026, 0xf0266060, 0x60a0fb5d, 0xfb62f026, 0xf02660e0, 0x6120fb4f, 
+    0xfb6cf026, 0x21066160, 0x1f0048bd, 0xfd5df026, 0xe62f2004, 0x5ff0e92d, 0x240048b9, 0x1f004626, 
+    0xfd50f026, 0x48b64605, 0xf0261e80, 0xf8dffd4b, 0xf00092d8, 0xf3c50807, 0xf3c53300, 0xf3c02a03, 
+    0xf9991702, 0xf0050000, 0xb3e8051f, 0xd0502801, 0xf04f2802, 0xf04f0205, 0xd04f0120, 0xf02648ab, 
+    0xf999fd4e, 0xb3800000, 0xd0502801, 0x46532802, 0x0200f04f, 0x010ff04f, 0x48a4d04f, 0xfd3ff026, 
+    0x48a32300, 0xf643461a, 0xf02671ff, 0xf8dffd21, 0x2d1ab280, 0xa27cf8df, 0x0b78f10b, 0xf1c8d240, 
+    0xf64f0008, 0xeb0071ff, 0xea010040, 0xf04f2000, 0xeb0131ff, 0x48980150, 0xfd01f026, 0x21184894, 
+    0xf0261f00, 0xe001fcfc, 0xe01ae00e, 0xea454893, 0x43015147, 0xf0264658, 0xf89afcf2, 0xf44f1000, 
+    0xf0051080, 0xe026fd85, 0x22054888, 0x38602120, 0x4886e7b5, 0x21202205, 0xe7b03840, 0x38204883, 
+    0x4882e7ad, 0x210f2200, 0x38604653, 0x487fe7b6, 0x210f2200, 0x38404653, 0x487ce7b0, 0xe7ad3820, 
+    0xf04fd102, 0xe03f040b, 0xd0382d1b, 0xd0382d1c, 0xd0382d1d, 0xf999240b, 0x05781000, 0xea40464f, 
+    0xea403081, 0xea404086, 0x46581144, 0x465c4321, 0xfcb5f026, 0x2119486e, 0xf0261f00, 0xf997fcb0, 
+    0xb3191000, 0xd0272901, 0xf04f2902, 0xf04f0301, 0xf04f0204, 0xd0250110, 0xf0264864, 0x2d1afcc0, 
+    0x2301d205, 0x221c4620, 0xf0260719, 0xf89afca1, 0xf44f1000, 0xf0051080, 0x2004fd2b, 0x240fe4af, 
+    0x2410e7c9, 0x2411e7c7, 0xe7c42601, 0x23014857, 0x21102204, 0xe7e03860, 0x23014854, 0x21102204, 
+    0xe7da3840, 0x38204851, 0x4855e7d7, 0x7801b510, 0x1f00484b, 0xfc79f026, 0xe54b2004, 0xb5104848, 
+    0xf0261f00, 0x494efc6f, 0x20047008, 0xe92de542, 0x484c47fc, 0x1ca54c4c, 0x1000f990, 0x0904f104, 
+    0x0a06f104, 0xd0182903, 0xd0162905, 0xd0142904, 0x0600f248, 0x46314620, 0xfc57f026, 0x46284631, 
+    0xfc53f026, 0x46484631, 0xfc4ff026, 0x46504631, 0xfc4bf026, 0xe8bd2000, 0x483c87fc, 0xfc2ff007, 
+    0x2000493b, 0x4f3b4e39, 0x80ecf8df, 0x0100e9cd, 0x463a6830, 0xf7fe4643, 0xf500faeb, 0xb2814000, 
+    0xf0264620, 0x4932fc32, 0x463a2000, 0xe9cd4643, 0x68700100, 0xfadcf7fe, 0x4000f500, 0x4628b281, 
+    0xfc23f026, 0x2000492a, 0x4643463a, 0x0100e9cd, 0xf7fe68b0, 0xf500facd, 0xb2814000, 0xf0264648, 
+    0x4923fc14, 0x463a2000, 0xe9cd4643, 0x68f00100, 0xfabef7fe, 0x4000f500, 0xe7b8b281, 0xb510481f, 
+    0x0000f990, 0x480eb281, 0xf0261f00, 0x481cfbfe, 0x480b7801, 0xf0261e80, 0x2004fbf8, 0x0000e4ca, 
+    0x000302a7, 0x000302a6, 0xd2054180, 0x00030302, 0xd2154084, 0x00030303, 0xd2054080, 0x00030304, 
+    0xd03c8074, 0x00037d0c, 0x00030227, 0xd00308e2, 0xd1800408, 0x00030223, 0xd1800488, 0x00080400, 
+    0x00030278, 0x000301dc, 0xd00351ac, 0x0003113c, 0x40300000, 0xb573eab3, 0x4030ab15, 0x000301da, 
+    0x000301db, 0xb51048fe, 0xfbbcf026, 0x700849fd, 0x1c8048fb, 0xfbb6f026, 0x700849fb, 0xf0052007, 
+    0x2004fd5a, 0x48f9e486, 0x7801b510, 0xf02648f4, 0x48f7fbac, 0x48f27801, 0xf0261c80, 0x2004fba6, 
+    0x48efe478, 0xf026b510, 0x49f0fb9d, 0x48ec7008, 0xf0261c80, 0x49eefb97, 0x20077008, 0xfd3bf005, 
+    0xe4672004, 0x47f0e92d, 0x93a8f8df, 0x0800f241, 0x4604220c, 0x46484641, 0xfbaff026, 0x28014de6, 
+    0x4ee74fe6, 0x02c1d10c, 0xf0276838, 0x2300fb75, 0x220c4641, 0xf0264648, 0x2000fb92, 0x60307028, 
+    0xf99546a8, 0x28040000, 0x6838da7e, 0xf8206831, 0x68304011, 0x60301c40, 0x382648d1, 0xfb62f026, 
+    0x68326839, 0x4cd74dd7, 0x0012f821, 0x1c406830, 0x350e6030, 0xf0264620, 0x6839fb55, 0x68321ca4, 
+    0x0012f821, 0x1c406830, 0x42ac6030, 0x4ccdd9f2, 0x1ca53420, 0xf0264620, 0x6839fb45, 0x68321ca4, 
+    0x0012f821, 0x1c406830, 0x42ac6030, 0x4dc6d9f2, 0x350e4cc5, 0xf0264620, 0x6839fb35, 0x68321ca4, 
+    0x0012f821, 0x1c406830, 0x42ac6030, 0x4dbfd9f2, 0x35144cbe, 0xf0264620, 0x6839fb25, 0x68321ca4, 
+    0x0012f821, 0x1c406830, 0x42ac6030, 0x4cb7d9f2, 0x1ca5341c, 0xf0264620, 0x6839fb15, 0x68321ca4, 
+    0x0012f821, 0x1c406830, 0x42ac6030, 0x4db0d9f2, 0x35084caf, 0xf0264620, 0x6839fb05, 0x68321ca4, 
+    0x0012f821, 0x1c406830, 0x42ac6030, 0x4ca8d9f2, 0x34144da7, 0x4620351e, 0xfaf4f026, 0x68326839, 
+    0x0012f821, 0xe0006830, 0x1c40e0f3, 0x1ca46030, 0xd9f042ac, 0x24002500, 0xb2ea2100, 0xf004b2e0, 
+    0x6839fbda, 0x68321c64, 0x0012f821, 0x1c406830, 0x2c046030, 0x1c6dd3f0, 0xd9ec2d24, 0x21002400, 
+    0xf004b2e0, 0x6839fb8f, 0x68321c64, 0x0012f821, 0x1c406830, 0x2cff6030, 0x2400d9f1, 0xf004b2e0, 
+    0x6839fb2b, 0x68321c64, 0x0012f821, 0x1c406830, 0x2c076030, 0x2400d9f2, 0xf004b2e0, 0x6839fb46, 
+    0x68321c64, 0x0012f821, 0x1c406830, 0x2c1f6030, 0x4880d9f2, 0xfaa6f026, 0x68326839, 0x0012f821, 
+    0x1c406830, 0x487b6030, 0xf0261c80, 0x6839fa9b, 0xf8216832, 0x68300012, 0x60301c40, 0x30204875, 
+    0xfa90f026, 0x68326839, 0x0012f821, 0x1c406830, 0x48706030, 0xf0263026, 0x6839fa85, 0xf8216832, 
+    0x68300012, 0x60301c40, 0x3040486a, 0xfa7af026, 0x68326839, 0x0012f821, 0x1c406830, 0x48656030, 
+    0xf0263042, 0x6839fa6f, 0x4c626832, 0xf8213478, 0x68300012, 0x60301c40, 0x46201da5, 0xfa62f026, 
+    0x1ca46839, 0xf8216832, 0x68300012, 0x60301c40, 0xd9f242ac, 0x1d254c58, 0xf0264620, 0x6839fa53, 
+    0x68321ca4, 0x0012f821, 0x1c406830, 0x42ac6030, 0x4c51d9f2, 0x1d253432, 0xf0264620, 0x6839fa43, 
+    0x68321ca4, 0x0012f821, 0x1c406830, 0x42ac6030, 0x4c49d9f2, 0x1d253460, 0xf0264620, 0x6839fa33, 
+    0x68321ca4, 0x0012f821, 0x1c406830, 0x42ac6030, 0x4c41d9f2, 0x1d25347a, 0xf0264620, 0x6839fa23, 
+    0x68321ca4, 0x0012f821, 0x1c406830, 0x42ac6030, 0x4c39d9f2, 0x1d2534ac, 0xf0264620, 0x6839fa13, 
+    0x68321ca4, 0x0012f821, 0x1c406830, 0x42ac6030, 0x482dd9f2, 0xf0261f00, 0x6839fa05, 0xf8216832, 
+    0x68300012, 0x60301c40, 0x1000f898, 0xf8881c49, 0xe8bd1000, 0x4a2987f0, 0x71fff640, 0x1c406810, 
+    0xf3f1fb90, 0x0013fb01, 0x28006010, 0x4924d105, 0x1c407808, 0x000ff000, 0x47708008, 0x5ff0e92d, 
+    0xf0264820, 0x4a20f9df, 0x42818851, 0xd205d07e, 0x73fff64f, 0x0101eba3, 0xe0014401, 0x0101eba0, 
+    0x481a8050, 0x0101f101, 0x8068f8df, 0x4d18b28c, 0x0c02f108, 0xf1087800, 0xb1000b04, 0xe03de02c, 
+    0xd03c8070, 0x000301da, 0x000301db, 0x00030284, 0x00030285, 0xd00351a4, 0x000302cc, 0x000303b0, 
+    0x000302c0, 0xd0034200, 0xd0039004, 0xd28fffc0, 0xd28f2000, 0xd28e0000, 0xd28f0000, 0x000302b0, 
+    0x000302c4, 0xd03c826c, 0x00030000, 0x000302cd, 0xeeee0000, 0xd03c8264, 0xea4449fe, 0x4dfe0005, 
+    0x0600f04f, 0x46e146c2, 0x680a4688, 0xf842682b, 0x68280023, 0x0001f100, 0xe05e6028, 0xff8bf7ff, 
+    0xea4448f6, 0x49f60205, 0x468a4681, 0x680d6803, 0x2025f843, 0xe0282500, 0xff7df7ff, 0xf02648f1, 
+    0x4606f971, 0x1c8048ef, 0xf96cf026, 0x2000f8d9, 0x4100ea46, 0x0000f8da, 0x46d0464f, 0x1020f842, 
+    0xff69f7ff, 0xf0264658, 0xe000f95d, 0x4606e00f, 0x300848e4, 0xf956f026, 0xea46683a, 0xf8d84100, 
+    0x1c6d0000, 0xf842b2ad, 0x42a51020, 0xe4b5d3d4, 0xf0264650, 0x4607f947, 0xf0264648, 0x682af943, 
+    0x4100ea47, 0x0000f8d8, 0x1022f840, 0x1c406828, 0x46586028, 0xf936f026, 0x48d24607, 0xf0263008, 
+    0x682af931, 0x4100ea47, 0x0000f8d8, 0x1022f840, 0x1c406828, 0x1c766028, 0x42a6b2b6, 0xe48dd3d8, 
+    0xb5102005, 0xf96cf005, 0x680a49c7, 0xd2034282, 0x681a4bc6, 0x601a1c52, 0xe49e6008, 0x4604b570, 
+    0x250048bf, 0x46292215, 0x46286005, 0xfa03f004, 0x061ff000, 0xffe4f7ff, 0x42a648bd, 0x4abdd104, 
+    0x60012101, 0xe0027011, 0x29016801, 0x4cb2d17e, 0x31106821, 0x5f80f5b1, 0x2005da79, 0xf940f005, 
+    0x68224dac, 0xf8416829, 0x68200022, 0x1c404aaf, 0x68126020, 0x2020f841, 0x1c406820, 0x48ae6020, 
+    0xf8e0f026, 0x48ac4606, 0xf0263814, 0x6829f8db, 0x4000ea46, 0xf8416822, 0x68200022, 0x46112200, 
+    0x60201c40, 0xf0044610, 0x49a4f9c6, 0x6822b280, 0x68294408, 0x0022f841, 0x22006820, 0x1c404611, 
+    0x20016020, 0xf9b7f004, 0xb280499d, 0x44086822, 0xf8416829, 0x68200022, 0x46112200, 0x60201c40, 
+    0xf0042002, 0x6829f9a8, 0x6822b280, 0x5007f100, 0x0022f841, 0x22006820, 0x1c404611, 0x20036020, 
+    0xf999f004, 0xb280498f, 0x44086822, 0xf8416829, 0x68200022, 0x22022100, 0x60201c40, 0xf0044608, 
+    0x4989f98a, 0x6822b280, 0x68294408, 0x0022f841, 0x22026820, 0x1c402100, 0x20016020, 0xf97bf004, 
+    0xb2804982, 0x44086822, 0xe0016829, 0xe096e0a0, 0x0022f841, 0x22026820, 0x1c402100, 0x46106020, 
+    0xf969f004, 0xb2806829, 0xf1006822, 0xf841500b, 0x68200022, 0x21002202, 0x60201c40, 0xf0042003, 
+    0x4973f95a, 0x6822b280, 0x68294408, 0x0022f841, 0x21006820, 0x1c402205, 0x46086020, 0xf94bf004, 
+    0xb280496c, 0x44086822, 0xf8416829, 0x68200022, 0x21002205, 0x60201c40, 0xf0042001, 0x4966f93c, 
+    0x6822b280, 0x68294408, 0x0022f841, 0x22056820, 0x1c402100, 0x20026020, 0xf92df004, 0xb2806829, 
+    0xf1006822, 0xf841500f, 0x68200022, 0x21002205, 0x60201c40, 0xf0042003, 0x4958f91e, 0x6822b280, 
+    0x68294408, 0x0022f841, 0x21006820, 0x1c402215, 0x46086020, 0xf90ff004, 0xb2806829, 0xf1006822, 
+    0xf8415010, 0x68200022, 0x22162100, 0x60201c40, 0xf0044608, 0x6829f900, 0x6822b280, 0x5014f100, 
+    0x0022f841, 0x21006820, 0x1c402217, 0x46086020, 0xf8f1f004, 0xb2806829, 0xf1006822, 0xf8415018, 
+    0x68200022, 0x21012200, 0x60201c40, 0x1f00482d, 0xf813f026, 0xd10b2801, 0x4070e8bd, 0x6005e5fe, 
+    0xe8bd2301, 0x220a4070, 0x02994835, 0xbff7f025, 0x4921bd70, 0xb5702215, 0x20004606, 0x46016008, 
+    0xf8c9f004, 0x041ff000, 0xfeaaf7ff, 0x8801482d, 0xd105428c, 0x3fccf1b6, 0xf1b6d07e, 0xd07b3fbb, 
+    0x48278004, 0xf0253808, 0x4c15ffbd, 0x8820b138, 0x4070e8bd, 0x4822b281, 0xf025380a, 0xf7ffbfb6, 
+    0x4d0efdba, 0xd9042e0a, 0x68286821, 0x6021f840, 0x2e01e00f, 0x481cd13c, 0xffa4f025, 0x481a4606, 
+    0xf0251e80, 0x6829ff9f, 0x4000ea46, 0xf8416822, 0xe02b0022, 0x000303ac, 0x000302b4, 0x000303a8, 
+    0x000302b0, 0xd03c8264, 0x000302d0, 0x000302c8, 0x000302b8, 0x000302bc, 0xd28fffd4, 0x21a00000, 
+    0x21b00000, 0x21d00000, 0x22a00000, 0x22b00000, 0x22d00000, 0x23a00000, 0x23b00000, 0x23d00000, 
+    0xd00351a4, 0x00030000, 0xd0039028, 0xfd73f7ff, 0xf0042005, 0x6829ffb5, 0xf8416822, 0xf7ff0022, 
+    0x48f8fd6a, 0x68226829, 0xf8416800, 0xf7ff0022, 0x48f5fd62, 0xff56f025, 0x48f34606, 0xf0253814, 
+    0x6829ff51, 0x4000ea46, 0xf8416822, 0xf7ff0022, 0x2200fd52, 0xe0004611, 0x4610e105, 0xf83bf004, 
+    0xb2804eea, 0x508df100, 0x88316822, 0x4001ea40, 0xf8416829, 0xf7ff0022, 0x2200fd3e, 0x46112001, 
+    0xf829f004, 0xb28049e2, 0x44086822, 0xea408831, 0x68294001, 0x0022f841, 0xfd2df7ff, 0x20022200, 
+    0xf0044611, 0x8831f818, 0xf100b280, 0x6822508e, 0x4001ea40, 0xf8416829, 0xf7ff0022, 0x2200fd1c, 
+    0x46112003, 0xf807f004, 0xb28049d2, 0x44086822, 0xea408831, 0x68294001, 0x0022f841, 0xfd0bf7ff, 
+    0x22022100, 0xf0034608, 0x8831fff6, 0xf100b280, 0x68225095, 0x4001ea40, 0xf8416829, 0xf7ff0022, 
+    0x2202fcfa, 0x20012100, 0xffe5f003, 0xb28049c2, 0x44086822, 0xea408831, 0x68294001, 0x0022f841, 
+    0xfce9f7ff, 0x21002202, 0xf0034610, 0x8831ffd4, 0xf100b280, 0x68225096, 0x4001ea40, 0xf8416829, 
+    0xf7ff0022, 0x2202fcd8, 0x20032100, 0xffc3f003, 0xb28049b2, 0x44086822, 0xea408831, 0x68294001, 
+    0x0022f841, 0xfcc7f7ff, 0x22052100, 0xf0034608, 0x8831ffb2, 0xf100b280, 0x6822509d, 0x4001ea40, 
+    0xf8416829, 0xf7ff0022, 0x2205fcb6, 0x20012100, 0xffa1f003, 0xb28049a2, 0x44086822, 0xea408831, 
+    0x68294001, 0x0022f841, 0xfca5f7ff, 0x21002205, 0xf0032002, 0x8831ff90, 0xf100b280, 0x6822509e, 
+    0x4001ea40, 0xf8416829, 0xf7ff0022, 0x2205fc94, 0x20032100, 0xff7ff003, 0xb2804992, 0x44086822, 
+    0xea408831, 0x68294001, 0x0022f841, 0xfc83f7ff, 0x22152100, 0xf0034608, 0x8831ff6e, 0xf100b280, 
+    0x682250a0, 0x4001ea40, 0xf8416829, 0xf7ff0022, 0x2100fc72, 0x46082216, 0xff5df003, 0xb2808831, 
+    0x50a8f100, 0xea406822, 0x68294001, 0x0022f841, 0xfc61f7ff, 0x22172100, 0xf0034608, 0x8831ff4c, 
+    0xf100b280, 0x682250b0, 0x4001ea40, 0xf8416829, 0x48750022, 0x21012200, 0xfe6ff025, 0xd1022801, 
+    0x4070e8bd, 0xbd70e45a, 0x20004970, 0x6008b510, 0x6008496f, 0x80084965, 0x60084962, 0xf0042005, 
+    0x496cfe7f, 0xe5186008, 0x4ff8e92d, 0x81a8f8df, 0x2400f240, 0x46052600, 0x46212209, 0x96004640, 
+    0xfe4bf025, 0xd1112801, 0x20004964, 0x72fff640, 0xf8416809, 0x1c406020, 0xd3fa4290, 0x46212300, 
+    0x46402209, 0xfe2bf025, 0xffcef7ff, 0x2d014c5c, 0x0900f248, 0x0b00f244, 0x4f5ad010, 0xf44f2d02, 
+    0xf2420a00, 0xd02a0100, 0xd1262d03, 0x4645220d, 0xf0254640, 0x2801fe22, 0xe0b0d079, 0x220e484c, 
+    0x46454659, 0x46406006, 0xfe17f025, 0x4649220f, 0x46287020, 0xfe11f025, 0xd10e2801, 0x28007820, 
+    0x220ad10b, 0x4100f240, 0xf0254628, 0x2800fe06, 0xf04fd103, 0xf7ff30aa, 0xe8bdfdfc, 0x220d8ff8, 
+    0x46404645, 0xfdf9f025, 0xd1032801, 0x20aaf64a, 0xfa38f7ff, 0xf8cd4e3c, 0xe016a000, 0x21004a36, 
+    0x3a2a4668, 0xfecef004, 0xd0e62801, 0xb3e87820, 0x46282200, 0xf025211f, 0xb130fde0, 0x46282200, 
+    0xf025211f, 0xf7fffdda, 0x220ffc99, 0x46284649, 0xfdd3f025, 0xd1d02801, 0x4659220e, 0xf0254638, 
+    0x2800fdcc, 0x2204d1c9, 0x21104638, 0xfdc5f025, 0xd1c22800, 0x46382205, 0xf0252120, 0x2800fdbe, 
+    0x2203d1bb, 0x21084630, 0xfdb7f025, 0xd1b42800, 0x46302204, 0xf0252110, 0x2800fdb0, 0x2205d1ad, 
+    0x21204630, 0xfda9f025, 0xe0012800, 0xe032e02e, 0x220ad1a3, 0x4100f240, 0xf0254628, 0x2800fd9e, 
+    0xe79ad0ac, 0x000302c8, 0xd28fffd4, 0x000302c4, 0x11b00000, 0x11d00000, 0x12b00000, 0x12d00000, 
+    0x13b00000, 0x13d00000, 0xd03c8260, 0x000302b0, 0x000302b4, 0x000302d0, 0xd00351a4, 0x000303ac, 
+    0x000302cd, 0xd0039026, 0xd0035040, 0x30bbf04f, 0xfd6ff7ff, 0xf64be799, 0xf7ff30bb, 0xf8cdf9b3, 
+    0xe015a000, 0x21014afe, 0xf0044668, 0x2801fe4b, 0x7820d037, 0x2200b1a0, 0x211f4628, 0xfd5df025, 
+    0x2200b130, 0x211f4628, 0xfd57f025, 0xfc16f7ff, 0x4649220f, 0xf0254628, 0x2801fd50, 0xe020d005, 
+    0x30ccf04f, 0xfd45f7ff, 0x220ee7f2, 0x46384659, 0xfd43f025, 0x2204b9a8, 0x21104638, 0xfd3df025, 
+    0xd10e2801, 0x220448e7, 0xf02521f0, 0x2801fd36, 0x220ad007, 0x4100f240, 0xf0254628, 0x2800fd2e, 
+    0x220fd0c0, 0x46284649, 0xfd27f025, 0xd1882801, 0x28017820, 0x48dcd185, 0x28017800, 0x48dbd1f7, 
+    0x220a2301, 0x60060299, 0xf0254628, 0xe714fd08, 0xb51048d7, 0xfce6f025, 0x46012200, 0xf7fd2001, 
+    0x48d3fc2e, 0xf0251c80, 0x2200fcdd, 0x20014601, 0xfc25f7fd, 0x1d0048ce, 0xfcd4f025, 0x46012200, 
+    0x4010e8bd, 0xf7fd2001, 0xb570bc1a, 0x4615460c, 0x46012200, 0xf7fd2001, 0x2200fc12, 0x20014621, 
+    0xfc0df7fd, 0xe8bd4629, 0x22004070, 0xf7fd2001, 0xe92dbc06, 0x200841f0, 0x0125f248, 0x52b8f04f, 
+    0xfbfdf7fd, 0x220d4dbb, 0x0100f242, 0xf0254628, 0x220cfcd4, 0xf2414604, 0x46280100, 0xfccdf025, 
+    0x42044db5, 0x0602f105, 0x0704f105, 0x0406f105, 0x2100d021, 0x46082202, 0xfd8df003, 0x4628b281, 
+    0xfc93f025, 0x21002202, 0xf0032001, 0xb281fd84, 0xf0254630, 0x2202fc8a, 0x46102100, 0xfd7bf003, 
+    0x4638b281, 0xfc81f025, 0x21002202, 0xf0032003, 0xb281fd72, 0x2100e00c, 0xf0254628, 0x2100fc76, 
+    0xf0254630, 0x2100fc72, 0xf0254638, 0x2100fc6e, 0xf0254620, 0x2101fc6a, 0xf0032014, 0xb281fcbb, 
+    0x30084895, 0xfc61f025, 0xe8bd2004, 0x489281f0, 0xf025b510, 0x4991fc57, 0x488f8008, 0xf0251c80, 
+    0x498ffc51, 0x20048008, 0x488ce61d, 0x8801b510, 0xf0254889, 0x488afc4a, 0x48878801, 0xf0251c80, 
+    0x2004fc44, 0x4884e60f, 0xf025b510, 0x4985fc3b, 0x200c7008, 0xfd7bf004, 0x48832301, 0x031c220c, 
+    0xf0254621, 0x4880fc35, 0x220c2301, 0x1d004621, 0xfc2ef025, 0xe5f62004, 0xb510487a, 0x48767801, 
+    0xfc23f025, 0xe5ee2004, 0x41f0e92d, 0x81dcf8df, 0x21022201, 0xf0254640, 0xf108fc40, 0x46050402, 
+    0x46202201, 0xf0252102, 0xea45fc38, 0x486a0100, 0xfc0bf025, 0x22024d6e, 0x46282104, 0xfc2df025, 
+    0x22024e6b, 0x46072104, 0x4630360a, 0xfc25f025, 0x0100ea47, 0x1c804860, 0xfbf7f025, 0x46202201, 
+    0xf0252102, 0x2202fc1a, 0x21044604, 0xf0254630, 0xea44fc14, 0x46400600, 0x21022201, 0xfc0df025, 
+    0x46042202, 0x46282104, 0xfc07f025, 0xea464304, 0xb2810044, 0x1d004850, 0xfbd7f025, 0xe7742004, 
+    0x4ff8e92d, 0xf025484c, 0xb2c4fbcd, 0x1c80484a, 0xfbc8f025, 0x9000b2c0, 0x1d004847, 0xfbc2f025, 
+    0xf8dfb2c5, 0x4e4c8130, 0x07a84f4c, 0xf640d570, 0x46380900, 0x46492301, 0xf025220b, 0xf8dffbd0, 
+    0x2206a10c, 0x46232140, 0xf0254650, 0xb184fbc8, 0xf6412314, 0x22087100, 0x0004f1aa, 0xfbbff025, 
+    0x2327483a, 0xf2402204, 0x389a31f0, 0xfbb7f025, 0xf898e003, 0xf0060000, 0xf8dff98c, 0x2308b0d0, 
+    0xf10b2200, 0x211f0b14, 0xf0254658, 0x2324fba8, 0x7100f643, 0x46582208, 0xfba1f025, 0x46cb2300, 
+    0x4649220b, 0xf0254638, 0x2301fb9a, 0x220b4659, 0xf0254630, 0x2201fb94, 0x21024623, 0x465046d1, 
+    0xfb8df025, 0x46232207, 0x46482180, 0xfb87f025, 0x46592300, 0x4630220b, 0xfb81f025, 0x9070f8df, 
+    0x21022301, 0x4648461a, 0xfb79f025, 0x22009b00, 0x46482101, 0xfb73f025, 0x46482300, 0x21022201, 
+    0xfb6df025, 0x22029b00, 0x46482104, 0xfb67f025, 0xd07d07e8, 0xf2412301, 0x220c0900, 0xe01f4649, 
+    0xd003517a, 0xd28f0004, 0x000302bc, 0x000302b8, 0xd28e002c, 0xd28fffd4, 0xd03c8070, 0x000302e0, 
+    0x000302e2, 0x00030304, 0xc1000030, 0xd0035336, 0xd205409a, 0x00030222, 0xd03c8306, 0xd0035026, 
+    0x463846ba, 0xfb3bf025, 0x22034db7, 0x46232108, 0xf0254628, 0xb17cfb34, 0xf6412310, 0x22087100, 
+    0xf0251f28, 0x48b0fb2c, 0x22042324, 0x31f0f240, 0xf025389a, 0xe003fb24, 0x0000f898, 0xf8f9f006, 
+    0x23084fa9, 0x37142200, 0x4638211f, 0xfb17f025, 0xf6432320, 0x22087100, 0xf0254638, 0x2300fb10, 
+    0x220c464f, 0x46504649, 0xfb09f025, 0x46392301, 0x4630220c, 0xfb03f025, 0x46232201, 0x46282102, 
+    0xfafdf025, 0x46232204, 0x46282110, 0xfaf7f025, 0x46392300, 0x4630220c, 0xfaf1f025, 0x23014c93, 
+    0x461a2102, 0xf0254620, 0x2200faea, 0xe0002101, 0x9b00e00f, 0xf0254620, 0x2300fae2, 0x22014620, 
+    0xf0252102, 0x9b00fadc, 0x21042202, 0xf0254620, 0x2004fad6, 0x4886e4e1, 0x7801b510, 0xf0254885, 
+    0x4885fab4, 0xb2818800, 0x1c804882, 0xfaadf025, 0xe4782004, 0xb510487f, 0xfaa4f025, 0x7008497c, 
+    0x1c80487c, 0xfa9ef025, 0x6008497b, 0xe46a2004, 0xb510487a, 0x0000f990, 0x4876b281, 0xfa95f025, 
+    0xe4602004, 0xb5104873, 0xfa8cf025, 0x70084973, 0xe4582004, 0x22004973, 0x4c71b510, 0x0100e9d1, 
+    0xf0274623, 0xf027fb7d, 0xb281fab7, 0xf0254869, 0x496dfa7c, 0x46232200, 0x0100e9d1, 0xfb70f027, 
+    0xfaaaf027, 0x4863b281, 0xf0251c80, 0x4867fa6e, 0x48607801, 0xf0251d00, 0x4966fa68, 0x78094864, 
+    0xea407800, 0x485b2101, 0xf0251d80, 0x4862fa5e, 0x48587801, 0xf0253008, 0x2004fa58, 0x4855e423, 
+    0xf025b510, 0xb200fa4f, 0x1c414c55, 0xf027d008, 0x2200fae0, 0xf0274623, 0x4a52f927, 0x0100e9c2, 
+    0x1c80484c, 0xfa3ef025, 0x1c41b200, 0xf027d008, 0x2200fad0, 0xf0274623, 0x4a4bf917, 0x0100e9c2, 
+    0x1d004844, 0xfa2ef025, 0x4c424948, 0x70081da4, 0xf0254620, 0x4a47fa27, 0x29200a01, 0xd9017011, 
+    0x70102020, 0xf0254620, 0x4941fa1d, 0x48397008, 0xf0253008, 0x4940fa17, 0x20047008, 0x483fe5c4, 
+    0x7801b510, 0xf0254833, 0x483dfa10, 0x48317801, 0xf0251c80, 0x483bfa0a, 0x482e7801, 0xf0251d00, 
+    0x4839fa04, 0x482b7801, 0xf0251d80, 0x2004f9fe, 0x4828e5aa, 0xf025b510, 0x4930f9f5, 0x48257008, 
+    0xf0251c80, 0x492ef9ef, 0x0003f000, 0x48217008, 0xf0251d00, 0x492bf9e7, 0x0003f000, 0x481d7008, 
+    0xf0251d80, 0x4928f9df, 0x20047008, 0x4827e58c, 0x7801b510, 0xf0254817, 0x4825f9d8, 0x48157801, 
+    0xf0251c80, 0x2004f9d2, 0x4812e57e, 0xf025b510, 0x491ef9c9, 0x480f7008, 0xf0251c80, 0x491cf9c3, 
+    0x20047008, 0x481be570, 0x7801b510, 0xf0254809, 0x2004f9bc, 0x4807e568, 0xf025b510, 0x4915f9b3, 
+    0x20047008, 0x0000e560, 0xd0035338, 0xd20540a4, 0x00030309, 0xd03c8070, 0x0003030c, 0x00030305, 
+    0x40c38800, 0x00030268, 0x00030270, 0x00030380, 0x0003037e, 0x0003037d, 0x0003037f, 0x00030307, 
+    0x000303b8, 0x000303b9, 0x00030308, 0x00030310, 0x00030311, 0x00030312, 0xf01cb510, 0x2200fc4b, 
+    0x46112304, 0xf0082001, 0xf019fe53, 0xf019fe4c, 0xf015ffdf, 0xf000feee, 0xf000f884, 0xf021fdf9, 
+    0x2001fbb2, 0x0000bd10, 0x48ffb570, 0x31b4f64b, 0xf96bf025, 0x210048fd, 0xf967f025, 0x240048fc, 
+    0x48fc6004, 0x48fc6004, 0x48fc7004, 0x48fc8004, 0x48fc8004, 0x48fc7004, 0x48fc7004, 0x46207004, 
+    0xf9d6f004, 0x700849fa, 0x700448fa, 0x780048fa, 0x2020b100, 0x220149f9, 0x48f98008, 0x700449fd, 
+    0x700448f8, 0x700248f8, 0x700448f8, 0x880048f8, 0x7fa8f5b0, 0xf5b0d018, 0xd0157fac, 0x7fb0f5b0, 
+    0xf5b0d012, 0xd00f7fb4, 0x7fb8f5b0, 0xf5b0d00c, 0xd0097fbc, 0x724a720a, 0x48ef2524, 0x7806230c, 
+    0x2e0148ee, 0xe004d003, 0x724c720c, 0x7202e7f4, 0x700c7242, 0x708c704d, 0x710c70cc, 0x718c714b, 
+    0x7004d106, 0x70847045, 0x710470c4, 0x71847143, 0x48e349e4, 0x49e56008, 0x600848e3, 0x49e648e4, 
+    0x48e47002, 0xf2417002, 0x80084000, 0x49e448e3, 0x60086800, 0x600849e3, 0x209ef44f, 0x600849e2, 
+    0xb510bd70, 0xfc8ff007, 0x1e942201, 0x46212005, 0xf94cf004, 0x46212201, 0xf0042000, 0xf022f947, 
+    0xf7fffbf7, 0xf7fdff71, 0xf00af848, 0xf022fb87, 0xf015faeb, 0xf00bffed, 0xf021fc63, 0xf023fc6f, 
+    0xf004fe73, 0x48b0fbb9, 0x384a2104, 0xf8cdf025, 0x4010e8bd, 0xba56f005, 0x47f0e92d, 0x932cf8df, 
+    0x461e2804, 0xf8dd4617, 0x460da020, 0xf6404604, 0xd0174800, 0xd0272c05, 0xf0052000, 0x462bfc54, 
+    0x46394632, 0xf0054620, 0x2100fcb3, 0xf0054620, 0x2300fd20, 0x220a4641, 0xf0254648, 0x2100f8c0, 
+    0xe0274608, 0xf0054608, 0x462bfc3e, 0x46394632, 0xf0054620, 0xb12ffc9d, 0x46202100, 0xfd09f005, 
+    0xe0102302, 0xe7f84651, 0xf0054608, 0x462bfc2c, 0x46394632, 0xf0054620, 0xb1b6fc8b, 0x46202100, 
+    0xfcf7f005, 0x46412301, 0x4648220a, 0xf897f025, 0x46082101, 0xf89ef019, 0x7100f505, 0x47f0e8bd, 
+    0x5280f04f, 0xf7fc1250, 0x4651bfba, 0xe92de7e7, 0x000641f0, 0xf04f489e, 0x460d0700, 0x489d7007, 
+    0x489d7007, 0x489d7007, 0x489d7007, 0x489d7007, 0xd1247007, 0x49a0489c, 0x489c7007, 0x489c7007, 
+    0x489c7007, 0x20047007, 0x499c7008, 0x499c7008, 0x499c7008, 0x489c7008, 0x489c7007, 0x489c7007, 
+    0x489c7007, 0x489c7007, 0x489c7007, 0x489c7007, 0x489c7007, 0x489c7007, 0x489c7007, 0x24017007, 
+    0x7004489b, 0x7004489b, 0x7004489b, 0x7004489b, 0x7004489b, 0x7004489b, 0x7004489b, 0x7004489b, 
+    0x7007489b, 0x7007489b, 0x7007489b, 0x7007489b, 0x7007489b, 0x7007489b, 0x7007489b, 0x7007489b, 
+    0x7007489b, 0x8007489b, 0x8007489b, 0x7007489b, 0x7007489b, 0x7007489b, 0x7007489b, 0x7007489b, 
+    0x8007489b, 0xf0092001, 0x2005fb58, 0xfb75f009, 0x20004998, 0x7010f821, 0xb2401c40, 0xdbf92804, 
+    0xf0092001, 0x2000fb8c, 0xfb89f009, 0x4892b936, 0x48927801, 0xd0192903, 0x70012103, 0x2d044890, 
+    0x4b51494f, 0x70044a54, 0x48504c4e, 0x6021d010, 0x60032d05, 0xf241d011, 0x80114100, 0x68094989, 
+    0xd1012912, 0x60014988, 0x81f0e8bd, 0xe7e57004, 0x60036021, 0x70b8f644, 0xf242e001, 0x801070dc, 
+    0xe92de7f2, 0x46074ffe, 0x21004827, 0xf0241e80, 0x4825ffbc, 0x38082100, 0xffb7f024, 0x2400487b, 
+    0x46207004, 0xf988f005, 0xf902f00a, 0xf0074638, 0x2300fab9, 0x461a200f, 0x90004619, 0xf0074618, 
+    0xf014fadb, 0x2000f94b, 0xf7ff4639, 0xf8dfff30, 0x2f03a1c0, 0x4e6f4d68, 0xf89ad024, 0x78290000, 
+    0xd1204308, 0x7801486c, 0x7800481f, 0xff9bf00b, 0x4a6b496a, 0x78127809, 0xe9cd4011, 0x48690100, 
+    0x48697803, 0x40037800, 0x78024868, 0x78004868, 0x48684002, 0x48687801, 0x40017800, 0xf00b4638, 
+    0xe0cbff6c, 0xe0cae0d3, 0xd03c80b8, 0xd03c8322, 0x00047f7c, 0x00047f80, 0x00030215, 0x00030216, 
+    0x00030218, 0x0003021a, 0x0003021b, 0x00030222, 0x00030223, 0x000301dc, 0x00030343, 0x00030220, 
+    0x00030257, 0x00030258, 0x000302a8, 0x00030312, 0x00030318, 0x0003cd5c, 0x00030302, 0x0003cd66, 
+    0x0003d090, 0x0003039c, 0x1e8c2120, 0x000303a0, 0x000302a6, 0x000302a7, 0x000303a4, 0x000301b8, 
+    0x000303a8, 0x000303ac, 0x000303b0, 0xd0030802, 0x000301df, 0x000301e0, 0x000301e1, 0x000301e2, 
+    0x000301e3, 0x000301e4, 0x000301e5, 0x000301e6, 0x000301e7, 0x000301e8, 0x000301e9, 0x000301ea, 
+    0x000301eb, 0x000301ec, 0x000301ed, 0x000301ee, 0x000301ef, 0x000301f0, 0x000301f1, 0x000301f2, 
+    0x000301f3, 0x00030265, 0x00030c5b, 0x00030c5c, 0x000301f4, 0x000301f5, 0x000301f6, 0x000301f7, 
+    0x000301f8, 0x000301f9, 0x000301fa, 0x000301fb, 0x000301fc, 0x000301fd, 0x000301fe, 0x000301ff, 
+    0x00030200, 0x00030201, 0x00030202, 0x00030203, 0x00030204, 0x00030206, 0x00030208, 0x0003020a, 
+    0x0003020b, 0x0003020c, 0x0003020d, 0x000301de, 0x00030364, 0x00030366, 0x00030214, 0x00030227, 
+    0x00030224, 0x000301cc, 0x2245cdc0, 0x00030ae4, 0x00030284, 0x00030394, 0x000302ab, 0x000302ac, 
+    0x000303a6, 0x00030390, 0x00030391, 0x00030392, 0x00030393, 0x0003038e, 0x0003038f, 0x78307030, 
+    0xd0092801, 0xd0072802, 0xd0052803, 0x49ffe006, 0x70342022, 0xe0018008, 0x700448fd, 0x48fd46b0, 
+    0x90007800, 0x783148fc, 0x48fc7803, 0x46387802, 0xfdc2f7ff, 0x26017833, 0x93e4f8df, 0xd1012b03, 
+    0x6000f889, 0x680048f7, 0xd0172812, 0xd0152816, 0x210048f5, 0x463a9400, 0x00407800, 0xf017b240, 
+    0xf016fb43, 0x48f1f833, 0x78004df1, 0xd0262803, 0xd0082801, 0x0000f89a, 0xe010b9e8, 0x463a2100, 
+    0x94002004, 0xf015e7eb, 0x702efdbb, 0x94002100, 0xf898463a, 0x46083000, 0xfb26f017, 0x48e5e012, 
+    0x28027800, 0x2801d00b, 0x48e3d005, 0x21012200, 0xfe73f024, 0xf015b118, 0x702efda3, 0xf015e002, 
+    0x702cfdad, 0x3afff04f, 0x465148dc, 0xfe37f024, 0x200049db, 0xa000f8c1, 0xfdaff008, 0xe9cd2601, 
+    0x78286400, 0x46322300, 0xb2404619, 0xf80cf005, 0xf64748d1, 0x23007a00, 0x22084651, 0xf0243824, 
+    0xf8dffe3e, 0x2300b334, 0x461a217f, 0x0b22f1ab, 0xf0244658, 0x2300fe34, 0x22084651, 0xf0244658, 
+    0x21d2fe2e, 0x0004f1ab, 0xfe0ff024, 0xf1ab2100, 0xf0240006, 0x2002fe0a, 0xf92df00b, 0x4ac248c1, 
+    0x80c649c2, 0x80468086, 0x46468006, 0x3000f898, 0xfea6f005, 0xf44f2172, 0xf7fc0080, 0xf8dffd1a, 
+    0x230082f0, 0xf241220c, 0x46400100, 0xfe07f024, 0xf2422300, 0x220d0100, 0xf0244640, 0x2300fe00, 
+    0x0100f244, 0x4640220e, 0xfdf9f024, 0x0a00f248, 0x23004640, 0x220f4651, 0xfdf1f024, 0x28037830, 
+    0x48acd00d, 0x220f2301, 0xf0244651, 0x2023fde8, 0xff04f006, 0xd0182f04, 0xd0182f05, 0x49a2e01a, 
+    0xf9912080, 0xf82d3001, 0xf9910013, 0xf82d3000, 0xf9910013, 0xf82d0003, 0xf9914010, 0xf82d0002, 
+    0x46684010, 0xfdc0f005, 0x2008e7e1, 0x200de000, 0xfee4f006, 0x8260f8df, 0xf8df2000, 0xf8dfb260, 
+    0xf8b8a260, 0xf89b3000, 0xf99a2000, 0xf0051000, 0xf8b8ffe4, 0x20003000, 0x2000f89b, 0x1000f99a, 
+    0xfcd4f006, 0xfb82f002, 0x78004880, 0xd1042803, 0xb9487828, 0xf0064884, 0x7828f937, 0x7831b920, 
+    0x1000f240, 0xfb7cf002, 0xf0062001, 0xf8b8febd, 0x46c23000, 0x2000f89b, 0xf8df46d8, 0x7830b204, 
+    0x1000f99b, 0xffb9f005, 0x3000f8ba, 0x2000f898, 0x1000f99b, 0xf0067830, 0x486cfca9, 0x28037800, 
+    0x7828d104, 0x4870b910, 0xf90ef006, 0x2200486a, 0x71fff240, 0xf0241f80, 0x4972fd80, 0x80082200, 
+    0x71fff240, 0x1f004864, 0xfd77f024, 0x486eb201, 0x461a2300, 0x486b8001, 0x0000f9b0, 0xffbef004, 
+    0x23022101, 0x22084608, 0xfaa4f004, 0x46082140, 0xfa7bf004, 0x22152104, 0xf0044608, 0x4857fa5b, 
+    0x220c2300, 0x0100f24f, 0xf0241d00, 0x4853fd31, 0x22082300, 0x7100f640, 0xf0241d00, 0x484ffd29, 
+    0x22042300, 0x1d0021f0, 0xfd22f024, 0x2300484b, 0x461a210f, 0xf0241d00, 0x4847fd1b, 0x2200230f, 
+    0x30524619, 0xfd2bf024, 0x23004843, 0x21802207, 0xf0243052, 0x4840fd24, 0x22052300, 0x30522120, 
+    0xfd1df024, 0xf0182001, 0xf8bafe4b, 0x90000000, 0xf8982000, 0xf99b3000, 0x78312000, 0xfd59f018, 
+    0xfcd4f018, 0xf0042000, 0xf004f9a5, 0xf004f9a9, 0xf002f9c3, 0x7831ff96, 0xf0054638, 0xf006f9ef, 
+    0x482df9d3, 0x22002301, 0x382a4619, 0xfcf7f024, 0x78014836, 0xf0042000, 0x4827ff02, 0x21022301, 
+    0x381c461a, 0xfcebf024, 0xf0182000, 0x4f30fc71, 0x22012300, 0x46382102, 0xfce1f024, 0x80b4f8df, 
+    0x22012300, 0x46402102, 0xfcd9f024, 0xa06cf8df, 0x22112300, 0x0a48f1aa, 0x3100f44f, 0xf0244650, 
+    0x2301fcb7, 0x22004650, 0xf0244619, 0x2100fcb1, 0x0000f244, 0xfd3cf003, 0x46502300, 0x461a2101, 
+    0xfca6f024, 0x21022301, 0xe035461a, 0x000302de, 0x000302d7, 0x000302db, 0x000302a7, 0x000302a6, 
+    0x00030227, 0x000301cc, 0x000301e9, 0x00030214, 0x0003031c, 0x000301db, 0xd0035040, 0xd1800048, 
+    0x00030288, 0x00030350, 0x00030338, 0x00030366, 0xd00305c0, 0xd0030412, 0x00030250, 0x000302a4, 
+    0x000301c8, 0x00030324, 0x00030326, 0x00030223, 0xd0031008, 0xd003000a, 0xf0244638, 0x2301fc80, 
+    0x21024640, 0xf024461a, 0x2100fc7a, 0xf00a2004, 0xf00afabc, 0x7828f9b1, 0xd07d2800, 0xf00a2002, 
+    0x4881fb9c, 0x88002186, 0x21004348, 0xf00ab200, 0x2000f992, 0xf939f00a, 0xf00a2001, 0x2002f936, 
+    0xf933f00a, 0xf00a2003, 0x4d78f930, 0x0000f995, 0xf8e2f00a, 0x0000f995, 0xf976f00a, 0x21c04874, 
+    0xfc33f024, 0xf9954d73, 0xb2800000, 0xf96af023, 0xf0052001, 0xf999fe18, 0x21002000, 0xf005200c, 
+    0x2000fd83, 0xf90af00a, 0x90002001, 0x46024603, 0xf00a4601, 0x2003f983, 0xfd6af003, 0x22007829, 
+    0xf00b7830, 0x4964faaf, 0x78094864, 0xe9cd7800, 0x48630100, 0x48637803, 0x48637802, 0x48637801, 
+    0xf00b7800, 0xf002fb91, 0x4861ffba, 0x71fff64f, 0xfbfbf024, 0x8800485f, 0x485db281, 0xf0241c80, 
+    0x485dfbf4, 0xb2818800, 0x30164859, 0xfbedf024, 0x8800485a, 0x4856b281, 0xf0241d00, 0x4854fbe6, 
+    0x30182100, 0xfbe1f024, 0x21004851, 0xf024301a, 0x484ffbdc, 0xe0002100, 0x301ce012, 0xfbd5f024, 
+    0x2100484b, 0xf024301e, 0x484dfbd0, 0x22042300, 0xf0242110, 0x484bfbe4, 0x28017800, 0xe035d011, 
+    0xf00a2000, 0x2100fb0a, 0xf00a4608, 0xf999f904, 0x464d0000, 0xf8a9f00a, 0x0000f995, 0xf85cf00a, 
+    0x2208e780, 0x23004840, 0xf0240151, 0x483ffbc8, 0x4d40493f, 0x78097800, 0xd2014288, 0xe0007028, 
+    0x231e7029, 0x21004e3c, 0x20019400, 0x4601e9cd, 0xf018782a, 0x205efd89, 0x21029602, 0xe9cd231e, 
+    0x782a1000, 0x20012100, 0xffb2f009, 0xf2404933, 0x8008106c, 0x70044832, 0xf0142002, 0xb003fa86, 
+    0x23004830, 0x461a210f, 0x4ff0e8bd, 0xbb97f024, 0xf012b510, 0xf021f893, 0xf00cfd5c, 0xf00cf97e, 
+    0xf00dff46, 0xf00df8fc, 0xf00ffd8d, 0xf010f971, 0xf010f837, 0xf010fb97, 0xf01aff31, 0xf01dfe5f, 
+    0xf01af80f, 0xf01bff76, 0xf020fef7, 0xf01bfa0e, 0xf020fd65, 0xf021f9cb, 0xf01ffcbb, 0xe8bdfd1b, 
+    0xf0194010, 0x0000bcf9, 0x0003023c, 0x00030228, 0xd0030864, 0x00030222, 0x0003038a, 0x0003038b, 
+    0x00030396, 0x00030395, 0x00030398, 0x00030397, 0xd003513c, 0x00030c74, 0x00030ca0, 0x00047f80, 
+    0xd0035250, 0x000302d7, 0xd0030480, 0x000302d8, 0x000302d9, 0x000302da, 0x00030338, 0x00030320, 
+    0x000302d5, 0xd03c8316, 0xe92d500f, 0xe59f09bc, 0xfb000e57, 0xe3a02103, 0xe3a01030, 0xe3a00010, 
+    0xfbfff12d, 0xe3a02103, 0xe3a01031, 0xe3a00010, 0xfbfff129, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d4070, 0xe3a00003, 0xfa000e28, 0xe3a00002, 0xfa000e26, 0xe3a00001, 0xfa000e24, 0xe3a00011, 
+    0xfa000e22, 0xe3a00012, 0xfa000e20, 0xe3a00001, 0xfb000d92, 0xe3a00002, 0xfb000d90, 0xe3a00004, 
+    0xfb000d8e, 0xe59f0948, 0xfb000e39, 0xe59f0944, 0xe3a03001, 0xe3a0200c, 0xe3011000, 0xfb009176, 
+    0xe59f0934, 0xe1d000d0, 0xe3700001, 0x0a00000f, 0xe3a02000, 0xe3a01007, 0xe1a00002, 0xfb00157a, 
+    0xe59f1918, 0xe3a00001, 0xe59f2918, 0xe1c100b6, 0xe1c100b4, 0xe1c100b2, 0xe1c100b0, 0xe59f0900, 
+    0xe59f1904, 0xe5d03000, 0xe59f08f0, 0xfa0015ab, 0xe59f18f8, 0xe3a00000, 0xe59f58f4, 0xe3a02000, 
+    0xe5c10000, 0xe3a0000f, 0xe1c500b0, 0xe2851000, 0xe59f08e0, 0xe5900000, 0xfa0081b3, 0xe59f48d8, 
+    0xe3a02000, 0xe5941000, 0xe0800001, 0xe5840000, 0xe59f08c8, 0xe2851000, 0xe5900000, 0xfa0081aa, 
+    0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f08ac, 0xe2851000, 0xe5900000, 0xfa0081a2, 
+    0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f0890, 0xe2851000, 0xe5900000, 0xfa00819a, 
+    0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f0874, 0xe2851000, 0xe5900000, 0xfa008192, 
+    0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f0858, 0xe2851000, 0xe5900000, 0xfa00818a, 
+    0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f083c, 0xe2851000, 0xe5900000, 0xfa008182, 
+    0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f0820, 0xe2851000, 0xe5900000, 0xfa00817a, 
+    0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 0xe59f0804, 0xe2851000, 0xe5900000, 0xfa008172, 
+    0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 0xe3a00007, 0xe1c500b0, 0xe59f07e0, 0xe2851000, 
+    0xe5900000, 0xfa008168, 0xe5941000, 0xe0800001, 0xe5840000, 0xe8bd8070, 0xe1a01000, 0xe59f07c0, 
+    0xe92d4010, 0xe1d000b0, 0xe3500000, 0x13a02103, 0x13011101, 0x1a00001e, 0xe59f27a8, 0xe59f07a8, 
+    0xe59f47a8, 0xe1510002, 0x1a000005, 0xe3a02004, 0xe3a01010, 0xfb0090ff, 0xe20000ff, 0xe3a01011, 
+    0xea00000d, 0xe59f2788, 0xe1510002, 0x1a000005, 0xe3a02005, 0xe3a01020, 0xfb0090f6, 0xe20000ff, 
+    0xe3a01012, 0xea000004, 0xe3a02003, 0xe3a01008, 0xfb0090f0, 0xe20000ff, 0xe3a01001, 0xe3500001, 
+    0xe1c410b2, 0x0a000005, 0xebffff54, 0xe3a02103, 0xe3a01001, 0xe8bd4010, 0xe3a00010, 0xeafff045, 
+    0xe3a02103, 0xe3001101, 0xe3a00010, 0xfbfff072, 0xe1d400f2, 0xe3a02103, 0xe2801090, 0xe3a00010, 
+    0xfbfff06d, 0xe59f1710, 0xe3a02103, 0xe59f0704, 0xe5d11000, 0xe5d00000, 0xe0800081, 0xe2801c02, 
+    0xe3a00010, 0xfbfff064, 0xe3a00005, 0xe1c400b0, 0xe59f06c8, 0xe3a02000, 0xe59f16d0, 0xe5900000, 
+    0xfa008121, 0xe59f1690, 0xe5912000, 0xe0800002, 0xe5810000, 0xe3a00004, 0xfb000cd0, 0xe8bd4010, 
+    0xe3a0000b, 0xea000d44, 0xe92d503f, 0xe59f4640, 0xe1a00004, 0xfb000d76, 0xe3a02103, 0xe3a01032, 
+    0xe3a00010, 0xfbfff04c, 0xe1a00004, 0xebffffa9, 0xe3a02103, 0xe3a01033, 0xe3a00010, 0xfbfff046, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d50ff, 0xe59f0668, 0xfa00909a, 0xe59f0664, 0xfb000d64, 
+    0xe3a02103, 0xe3a01034, 0xe3a00010, 0xfbfff03a, 0xe3a00002, 0xfa000d3d, 0xe59f0648, 0xe3a03000, 
+    0xe3a02008, 0xe3001100, 0xfb00909b, 0xe59f0610, 0xe1d000b0, 0xe3500000, 0x13a02103, 0x13011102, 
+    0x1a00003d, 0xe59f0620, 0xe3a07000, 0xe59f561c, 0xe59f45c4, 0xe5d00000, 0xe3500000, 0x0a000023, 
+    0xe59f060c, 0xe59f160c, 0xe59f660c, 0xe1d000d0, 0xe1d110d0, 0xe1800001, 0xe1d610d0, 0xe1900001, 
+    0x1a00002f, 0xe3a00005, 0xfa000c9c, 0xe59f15ec, 0xe240093d, 0xe2400d09, 0xe3a02000, 0xe5810000, 
+    0xe3a00001, 0xe5c60000, 0xe3a0003e, 0xe1c500b0, 0xe2851000, 0xe59f055c, 0xe5900000, 0xfa0080d2, 
+    0xe5941000, 0xe0800001, 0xe5840000, 0xe59f05b0, 0xe59f15b0, 0xe5d00000, 0xe2800001, 0xe2000007, 
+    0xe0800200, 0xe0810100, 0xe5807008, 0xea000014, 0xe59f0594, 0xe5900000, 0xe3500000, 0x0a000000, 
+    0xeafffffe, 0xe59f0504, 0xe3a02000, 0xe59f155c, 0xe5c07000, 0xe3a00009, 0xe1c500b0, 0xe59f051c, 
+    0xe5900000, 0xfa0080b8, 0xe5941000, 0xe3a02103, 0xe0800001, 0xe3a01002, 0xe5840000, 0xe3a00010, 
+    0xfbffefed, 0xe3a02103, 0xe3a01035, 0xe3a00010, 0xfbffefe9, 0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 
+    0xe92d503f, 0xe59f0524, 0xfb000d09, 0xe3a02103, 0xe3a01036, 0xe3a00010, 0xfbffefdf, 0xe59f04c0, 
+    0xe1d000b0, 0xe3500000, 0x0a00000a, 0xe3a02103, 0xe3011103, 0xe3a00010, 0xfbffefd7, 0xe3a02103, 
+    0xe3a01037, 0xe3a00010, 0xfbffefd3, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe59f04ac, 0xe5d00000, 
+    0xe3500000, 0x0afffff4, 0xe59f04a4, 0xe59f24a4, 0xe1d010d0, 0xe1d220d0, 0xe1911002, 0x1affffee, 
+    0xe3a04001, 0xe5c04000, 0xe59f04a4, 0xe3a03000, 0xe1a02004, 0xe3a01002, 0xfb009027, 0xe3a00000, 
+    0xfa000e94, 0xe59f048c, 0xe5d00000, 0xe3500000, 0x1a000003, 0xe3a00802, 0xe3001803, 0xfbffef8f, 
+    0xfb002676, 0xe3a00001, 0xfa006e04, 0xe59f0450, 0xe59f1450, 0xe5d00000, 0xe2800001, 0xe2000007, 
+    0xe0800200, 0xe0810100, 0xe5804008, 0xe3a00005, 0xfa000c2a, 0xe59f1424, 0xe240093d, 0xe2400d09, 
+    0xe5810000, 0xe3a00000, 0xe59f13a0, 0xe5c10000, 0xe3a00002, 0xfa000ca5, 0xe3a00003, 0xfa000ca3, 
+    0xe59f03e0, 0xe3a03000, 0xe3a02008, 0xe3001100, 0xfb009001, 0xe3a02007, 0xe3a01000, 0xe3a00001, 
+    0xfb00157d, 0xe59f13f0, 0xe3a00043, 0xe3a02000, 0xe1c100b0, 0xe59f035c, 0xe5900000, 0xfa008052, 
+    0xe59f1354, 0xe5912000, 0xe0800002, 0xe5810000, 0xeaffffb1, 0xe92d5fff, 0xe3a02103, 0xe3a01038, 
+    0xe3a00010, 0xfbffef84, 0xe59f03b0, 0xe3a0200e, 0xe3041000, 0xfb008fef, 0xe59f43a4, 0xe3500000, 
+    0xe59fb3a0, 0x13a00000, 0x1a000003, 0xe3a0200e, 0xe3041000, 0xe1a00004, 0xfb008fe6, 0xe5cb0000, 
+    0xe59f0384, 0xfa008fce, 0xe1a08000, 0xe3a0200c, 0xe3011000, 0xe1a00004, 0xfb008fde, 0xe59f936c, 
+    0xe5c90000, 0xe59f0368, 0xfa008fc5, 0xe59f1364, 0xe6bf4070, 0xe7e003d4, 0xe5c10000, 0xe59f0358, 
+    0xfa008fbf, 0xe6bf5070, 0xe59f0350, 0xfa008fbc, 0xe6bf6070, 0xe59f0348, 0xfa008fb9, 0xe6bf7070, 
+    0xe3a02000, 0xe1a01005, 0xe3a00001, 0xfbffef5a, 0xe3a02000, 0xe1a01006, 0xe3a00001, 0xfbffef56, 
+    0xe3a02000, 0xe1a01004, 0xe3a00001, 0xfbffef52, 0xe59f0310, 0xe5d00000, 0xe3500001, 0x1a00000d, 
+    0xe3150004, 0x0a00000b, 0xe59fa2fc, 0xe3a02006, 0xe30011c0, 0xe1a0000a, 0xfb008fb6, 0xe3500003, 
+    0x1a000004, 0xe3a03006, 0xe30011c0, 0xe1a02003, 0xe1a0000a, 0xfb008fa8, 0xe59fa244, 0xe5da0000, 
+    0xe3100018, 0x0a000006, 0xe3e00000, 0xfa0027f1, 0xe59f22b8, 0xe3041004, 0xe3a00004, 0xfbffef36, 
+    0xea000042, 0xe5db1000, 0xe3a02000, 0xe3a00001, 0xfbffef31, 0xe5db1000, 0xe2063c01, 0xe1da00b0, 
+    0xe3510000, 0x13800080, 0x03c00080, 0xe1ca00b0, 0xe3160b01, 0x13510000, 0xe2050010, 0x03a02000, 
+    0x13a02001, 0xe1900003, 0x13140010, 0x0a000003, 0xe5d90000, 0xe3500000, 0x03a00001, 0x0a000000, 
+    0xe3a00000, 0xe205c020, 0xe193300c, 0x13140020, 0x0a000003, 0xe5d93000, 0xe3530000, 0x03a03001, 
+    0x0a000000, 0xe3a03000, 0xe3520000, 0x1a000005, 0xe59f221c, 0xe1d220d0, 0xe1911002, 0x1a000007, 
+    0xe1900003, 0x0a000005, 0xe59f0208, 0xe1d010d0, 0xe3510003, 0x13510004, 0x13510005, 0x0bfffddf, 
+    0xe3180003, 0x0a000011, 0xe3e00000, 0xfa0027b9, 0xe59f01e4, 0xe3a0106d, 0xe3a02000, 0xe1c050b2, 
+    0xe1c040b4, 0xe1c060b6, 0xe1c070b8, 0xe1c010b0, 0xe2801000, 0xe59f01c4, 0xe5900000, 0xfa007fba, 
+    0xe59f10f4, 0xe5912000, 0xe0800002, 0xe5810000, 0xe3a02103, 0xe3a01039, 0xe3a00010, 0xfbffeeee, 
+    0xe59f019c, 0xfb000c12, 0xf57ff05f, 0xe8bd5fff, 0xe25ef004, 0xe92d500f, 0xe59f0188, 0xfb000c0c, 
+    0xe3a02103, 0xe3a0103a, 0xe3a00010, 0xfbffeee2, 0xe3a02103, 0xe3a0103b, 0xe3a00010, 0xfbffeede, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0154, 0xfb000bfe, 0xe3a02103, 0xe3a0103c, 
+    0xe3a00010, 0xfbffeed4, 0xe59f1140, 0xe3a00008, 0xe3a02000, 0xe1c100b0, 0xe59f0080, 0xe5900000, 
+    0xfa007f91, 0xe59f1050, 0xe5912000, 0xe0800002, 0xe5810000, 0xe3a02103, 0xe3a0103d, 0xe3a00010, 
+    0xfbffeec5, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xc1000104, 0xc1000114, 0xd003902c, 0x00030242, 
+    0x00030350, 0x00030394, 0x00030338, 0x00030366, 0x00030266, 0x00030414, 0x00030c90, 0x000301d4, 
+    0x00030460, 0x00030470, 0x00030480, 0x00030490, 0x000304a8, 0x000304bc, 0x000304cc, 0x000304dc, 
+    0x000304ec, 0x00030220, 0xc1000214, 0xd0035040, 0x0003041c, 0xc1000224, 0x000302ac, 0x000303a6, 
+    0xd03c80b6, 0xc1000124, 0xd0035126, 0x00030c58, 0x000303cc, 0x00030265, 0x00030c5b, 0x00030c5c, 
+    0x0003024c, 0x00030c74, 0x00037aec, 0x00047f70, 0xc1000134, 0xd0035114, 0x0003031c, 0x000303d4, 
+    0xd0060000, 0xd28fffc0, 0x0003021d, 0xd0039048, 0x0003021c, 0xd0039026, 0x0003021e, 0xd0039028, 
+    0xd0039018, 0xd0039016, 0x00030302, 0xd0039034, 0xcccc0000, 0x00030215, 0x00030222, 0x0003cdb0, 
+    0x00030ed4, 0xc1000144, 0xc1000154, 0xc1000164, 0x000303dc, 0xe92d500f, 0xe59f0c74, 0xfb000ba4, 
+    0xe3a02103, 0xe3a0103e, 0xe3a00010, 0xfbffee7a, 0xebfffd52, 0xe3a02103, 0xe3a01007, 0xe3a00402, 
+    0xfbffee75, 0xe3a02103, 0xe3a0103f, 0xe3a00010, 0xfbffee71, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f0c2c, 0xfb000b91, 0xe3a02103, 0xe3a01040, 0xe3a00010, 0xfbffee67, 0xe3a02103, 
+    0xe3a01041, 0xe3a00010, 0xfbffee63, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d50ff, 0xe59f0bf8, 
+    0xfb000b83, 0xe59f0bf4, 0xfa008eb5, 0xe3500000, 0x0a00001c, 0xe59f4be8, 0xe3a01001, 0xe1a00004, 
+    0xfb008eb0, 0xe284000c, 0xe3a01000, 0xfb008ead, 0xe30b1bbb, 0xe1a00004, 0xfb008eaa, 0xe59f4bc4, 
+    0xe3a00062, 0xe1c400b0, 0xe59f0bbc, 0xfa008ea4, 0xe1c400b2, 0xe2841000, 0xe59f0bb0, 0xe3a02000, 
+    0xe5900000, 0xfa007f08, 0xe51f11d4, 0xe5912000, 0xe0800002, 0xe5810000, 0xe59f0b94, 0xe30f1fff, 
+    0xfb008e98, 0xea00003e, 0xe59f0b88, 0xfa008e94, 0xe3500000, 0x0a00003a, 0xe59f6b7c, 0xe1a00006, 
+    0xfa008e8f, 0xe51f1230, 0xe1b007a0, 0xe51f41f0, 0xe2865074, 0xe5c10000, 0x0a00002b, 0xe3a03000, 
+    0xe3a0200f, 0xe3081000, 0xe1a00006, 0xfb008e92, 0xe3a03001, 0xe3a0200b, 0xe3001800, 0xe1a00006, 
+    0xfb008e8d, 0xe59f0b34, 0xe5d00000, 0xe3500000, 0x1a000013, 0xe1a00006, 0xfa008e79, 0xe59f1b20, 
+    0xe7e006d0, 0xe5c10000, 0xe1a00006, 0xfa008e74, 0xe59f1b10, 0xe7e00550, 0xe5c10000, 0xe1a00006, 
+    0xfa008e6f, 0xe59f1b00, 0xe7e203d0, 0xe5c10000, 0xe1a00006, 0xfa008e6a, 0xe59f1af0, 0xe7e102d0, 
+    0xe5c10000, 0xe3081000, 0xe1a00005, 0xfb008e65, 0xe1d400b0, 0xe3800010, 0xe1c400b0, 0xe3a00004, 
+    0xfa000b0a, 0xebfffcdd, 0xea000005, 0xe30f1fff, 0xe1a00005, 0xfb008e5b, 0xe1d400b0, 0xe3c00010, 
+    0xe1c400b0, 0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xe92d500f, 0xe59f0a98, 0xfb000b1d, 0xe3a02103, 
+    0xe3a01085, 0xe3a00010, 0xfbffedf3, 0xe3a0000a, 0xfa000af6, 0xe59f0a7c, 0xe3a03000, 0xe3a0200a, 
+    0xe3001400, 0xfa008e49, 0xe59f0a6c, 0xe3a03000, 0xe3a0200a, 0xe3001400, 0xfa008e44, 0xebfffcbf, 
+    0xe3a02103, 0xe3a01086, 0xe3a00010, 0xfbffede2, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 
+    0xe59f0a38, 0xfb000b02, 0xe59f4a34, 0xe5d40000, 0xe3500001, 0x0a000002, 0xe3500002, 0x0a00001e, 
+    0xea00002a, 0xe3a02103, 0xe3a01042, 0xe3a00010, 0xfbffedd1, 0xe51f0378, 0xe1d000b0, 0xe3500000, 
+    0x0a000008, 0xe3a02103, 0xe3001176, 0xe3a00010, 0xfbffedc9, 0xe3a02103, 0xe3a01043, 0xe3a00010, 
+    0xfbffedc5, 0xea000019, 0xe59f09d8, 0xfa008e1c, 0xe1a01000, 0xe3a02000, 0xe3a00010, 0xfbffedbe, 
+    0xe3a03001, 0xe59f09c0, 0xe3a02000, 0xe1a01003, 0xfb008e21, 0xebfffc91, 0xeaffffed, 0xe3a00001, 
+    0xfa0016cf, 0xe51f5398, 0xe3a03001, 0xe3a02000, 0xe1a01003, 0xe1a00005, 0xfb008e17, 0xe3a03001, 
+    0xe3a01002, 0xe1a02003, 0xe1a00005, 0xfb008e12, 0xe59f0978, 0xe1d000d0, 0xe3500003, 0x13500005, 
+    0x13500004, 0x059f0968, 0x05d00000, 0x03500001, 0x0a000006, 0xe3a00000, 0xe5c40000, 0xe3a0000b, 
+    0xfa000aa2, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe5d40000, 0xe3500003, 0x13500002, 0x051f1494, 
+    0x03a00001, 0x05c10000, 0xeafffff1, 0xe92d500f, 0xe59f0920, 0xfb000ab6, 0xe3a02103, 0xe3a01087, 
+    0xe3a00010, 0xfbffed8c, 0xe3a0000c, 0xfa000a8f, 0xe59f08e0, 0xe3a03000, 0xe3a0200c, 0xe3011000, 
+    0xfa008de2, 0xe59f08d0, 0xe3a03000, 0xe3a0200c, 0xe3011000, 0xfa008ddd, 0xebfffc58, 0xe3a02103, 
+    0xe3a01088, 0xe3a00010, 0xfbffed7b, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f08b8, 
+    0xfb000a9b, 0xe3a02103, 0xe3a01044, 0xe3a00010, 0xfbffed71, 0xe3a02103, 0xe3a01045, 0xe3a00010, 
+    0xfbffed6d, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe59f0884, 0xe3a01001, 0xfb008dc1, 
+    0xe3a02103, 0xe3a0107f, 0xe3a00010, 0xfbffed62, 0xe59f486c, 0xe3a0006f, 0xe1c400b0, 0xe59f0864, 
+    0xfa008db7, 0xe1a05000, 0xe59f085c, 0xfa008db4, 0xe0850800, 0xe5840004, 0xe3a00001, 0xfa0082ab, 
+    0xe59f0848, 0xe2841000, 0xe3a02000, 0xe5900000, 0xfa007e15, 0xe51f15a0, 0xe5912000, 0xe0800002, 
+    0xe5810000, 0xe59f0828, 0xfb000a71, 0xe3a02103, 0xe3a01080, 0xe3a00010, 0xfbffed47, 0xf57ff05f, 
+    0xe8bd503f, 0xe25ef004, 0xe92d500f, 0xe59f0804, 0xfb000a67, 0xe3a02103, 0xe3a0104a, 0xe3a00010, 
+    0xfbffed3d, 0xe3a02103, 0xe3a0104b, 0xe3a00010, 0xfbffed39, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f07d0, 0xfb000a59, 0xe3a02103, 0xe3a01083, 0xe3a00010, 0xfbffed2f, 0xe3a02103, 
+    0xe3a01084, 0xe3a00010, 0xfbffed2b, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe51f461c, 
+    0xe1a00004, 0xfb000a4a, 0xe3a02103, 0xe3a01023, 0xe3a00010, 0xfbffed20, 0xe1a00004, 0xebfffc7d, 
+    0xe3a02103, 0xe3a01024, 0xe3a00010, 0xfbffed1a, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d503f, 
+    0xe51f4654, 0xe1a00004, 0xfb000a39, 0xe3a02103, 0xe3a01025, 0xe3a00010, 0xfbffed0f, 0xe1a00004, 
+    0xebfffc6c, 0xe3a02103, 0xe3a01026, 0xe3a00010, 0xfbffed09, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 
+    0xe92d500f, 0xe59f0714, 0xfb000a29, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0700, 
+    0xfb000a23, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f06ec, 0xfb000a1d, 0xe3a02103, 
+    0xe3a01085, 0xe3a00010, 0xfbffecf3, 0xe3a02103, 0xe3a01086, 0xe3a00010, 0xfbffecef, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f06b8, 0xfb000a0f, 0xe3a02103, 0xe3a01058, 0xe3a00010, 
+    0xfbffece5, 0xe3a02103, 0xe3a01059, 0xe3a00010, 0xfbffece1, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d503f, 0xe59f0684, 0xfb000a01, 0xe3a02103, 0xe3a0105e, 0xe3a00010, 0xfbffecd7, 0xe59f0670, 
+    0xfa008d2c, 0xe59f466c, 0xe584000c, 0xe59f0668, 0xfa008d28, 0xe6bf2070, 0xe1c420b6, 0xe594000c, 
+    0xe1b01fa0, 0xe5c41002, 0x1a000042, 0xe7e11d50, 0xe5c41000, 0xe7e41850, 0xe5c41001, 0xe1a01800, 
+    0xe1c400b8, 0xe3a00010, 0xfbffecc3, 0xe5d40000, 0xe3500001, 0x1a000037, 0xe1d410d1, 0xe3510007, 
+    0x1a000024, 0xe1d420f8, 0xe30f3ff8, 0xe6ff0072, 0xe1500003, 0x1309302a, 0x11500003, 0x1a00000e, 
+    0xe1d400f6, 0xe3a01007, 0xe1d11000, 0x0a000029, 0xe2001027, 0xe59f05e4, 0xe3510022, 0x03a03001, 
+    0x0a000002, 0xe3510002, 0x03a03000, 0x1a000021, 0xe3a0200f, 0xe3081000, 0xea000009, 0xe30f3fe0, 
+    0xe1500003, 0x1a000008, 0xe1d400b6, 0xe3100902, 0x0a000018, 0xe59f05a8, 0xe3a03001, 0xe3a02002, 
+    0xe3a01004, 0xfb008d04, 0xea000012, 0xe1a00802, 0xe1b00820, 0x0a000002, 0xe351001e, 0x1a00000d, 
+    0xea000003, 0xe1d400b6, 0xe3100902, 0x1b0090cd, 0xea000008, 0xe1d400b8, 0xe3041191, 0xe6ff0070, 
+    0xe1500001, 0x1a000003, 0xe5d40006, 0xe3100001, 0x0a000000, 0xeafffffe, 0xe3a02103, 0xe3a0105f, 
+    0xe3a00010, 0xfbffec84, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d500f, 0xe3a02103, 0xe3a01060, 
+    0xe3a00010, 0xfbffec7c, 0xe59f0518, 0xe3a0107f, 0xfb008cd4, 0xe59f0510, 0xe3a01003, 0xfb008cd1, 
+    0xe59f0508, 0xfb00099a, 0xe51f0880, 0xe5d00000, 0xe3500001, 0x051f08f8, 0x01d000b0, 0x03d00040, 
+    0x1a00000a, 0xe59f14e8, 0xe3a00074, 0xe3a02000, 0xe1c100b0, 0xe51f091c, 0xe5900000, 0xfa007d2a, 
+    0xe51f194c, 0xe5912000, 0xe0800002, 0xe5810000, 0xe3a02103, 0xe3a01061, 0xe3a00010, 0xfbffec5e, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe3a02103, 0xe3a0107c, 0xe3a00010, 0xfbffec56, 
+    0xfa001278, 0xe59f048c, 0xfb000979, 0xe3a01001, 0xe3a00008, 0xfa001257, 0xe3a00000, 0xfb00127d, 
+    0xe3a0001e, 0xfa000951, 0xe3a0001f, 0xfa00094f, 0xebfffb22, 0xe3a02103, 0xe3a0107d, 0xe3a00010, 
+    0xfbffec45, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0440, 0xfb000965, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f042c, 0xfb00095f, 0xe3a0001f, 0xfb000944, 0xe59f1420, 
+    0xe21000ff, 0xe5c10000, 0x1a000004, 0xe59f0414, 0xe3a03000, 0xe3a0200a, 0xe3001400, 0xfb008c96, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f03f4, 0xfb00094e, 0xe3a02103, 0xe3a0106a, 
+    0xe3a00010, 0xfbffec24, 0xe3a02103, 0xe3a0106b, 0xe3a00010, 0xfbffec20, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d503f, 0xe59f03c0, 0xfb000940, 0xe3a02103, 0xe3a0104c, 0xe3a00010, 0xfbffec16, 
+    0xe3a00021, 0xfb000921, 0xe59f13a4, 0xe6af0070, 0xe51f4a74, 0xe3500000, 0xe5c10000, 0xe1d400b0, 
+    0x0a00001a, 0xe3500000, 0x0a00001e, 0xe59f1384, 0xe3a00023, 0xe3a02000, 0xe1c100b0, 0xe51f0aa4, 
+    0xe5900000, 0xfa007cc8, 0xe51f1ad4, 0xe5912000, 0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 
+    0xe3001110, 0xe3800002, 0xe1c400b0, 0xe3a00010, 0xfbffebf9, 0xe3a02103, 0xe3a0104d, 0xe3a00010, 
+    0xfbffebf5, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3d00002, 0xe1c400b0, 0x0bfffac8, 0xe3a02103, 
+    0xe3a01010, 0xeafffff0, 0xebfffac4, 0xeaffffe9, 0xe92d503f, 0xe59f0300, 0xfb00090d, 0xe3a02103, 
+    0xe3a01068, 0xe3a00010, 0xfbffebe3, 0xe51f0ad4, 0xe3a0200e, 0xe3041000, 0xfb008c4e, 0xe51f4ab0, 
+    0xe3500000, 0x13a00022, 0x1b009018, 0xe5c40000, 0xe31000ff, 0xe51f4b58, 0xe1d400b0, 0x0a00001a, 
+    0xe3500000, 0x0a000022, 0xe59f12b0, 0xe3a00022, 0xe3a02000, 0xe1c100b0, 0xe51f0b80, 0xe5900000, 
+    0xfa007c91, 0xe51f1bb0, 0xe5912000, 0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3001111, 
+    0xe3800001, 0xe1c400b0, 0xe3a00201, 0xfbffebc2, 0xe3a02103, 0xe3a01069, 0xe3a00010, 0xfbffebbe, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3c00001, 0xe3a01011, 0xe3a02103, 0xe1c400b0, 0xe3a00201, 
+    0xfbffebb5, 0xe1d400b0, 0xe3500000, 0x0bfffa8b, 0xeaffffee, 0xebfffa89, 0xeaffffe5, 0xe92d500f, 
+    0xe59f021c, 0xfb0008d2, 0xe3a02103, 0xe3a01052, 0xe3a00010, 0xfbffeba8, 0xe3a02103, 0xe3a01053, 
+    0xe3a00010, 0xfbffeba4, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d50ff, 0xe3a02103, 0xe3a0105a, 
+    0xe3a00010, 0xfbffeb9c, 0xe59f01d8, 0xfb0008c0, 0xe59f61d4, 0xe3a03001, 0xe1a02003, 0xe3a01002, 
+    0xe1a00006, 0xfb008bfc, 0xe59f51c0, 0xe3a00001, 0xe5c50000, 0xfb004e95, 0xe59f01b4, 0xe3a02000, 
+    0xe1d010b0, 0xe3a00010, 0xfbffeb8b, 0xe59f01a4, 0xe3a02005, 0xe51f4c98, 0xe3a01020, 0xe5d00000, 
+    0xe3500000, 0xe1d400b0, 0x03a03000, 0x13a03001, 0x03c00020, 0x13800020, 0xe1c400b0, 0xe59f0178, 
+    0xfb008be5, 0xe59f0174, 0xe5d00000, 0xe3500000, 0xe1d400b0, 0x03c00040, 0x13800040, 0xe1c400b0, 
+    0xe6ff0070, 0xe3d00060, 0x0a000055, 0xe3a02103, 0xe3a01022, 0xe3a00010, 0xfbffeb6f, 0xe3a03000, 
+    0xe3a02001, 0xe3a01002, 0xe1a00006, 0xfb008bd2, 0xe3a00000, 0xe5c50000, 0xe3a02103, 0xe3a0105b, 
+    0xe3a00010, 0xfbffeb64, 0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xc1000174, 0xc1000184, 0xc1000194, 
+    0xd03c8082, 0xd03c806e, 0x000303e4, 0xd03c800a, 0x00030c4c, 0xd03c807e, 0xd03c8084, 0xd03c800c, 
+    0x00030243, 0x00030360, 0x00030361, 0x00030362, 0x00030363, 0xc10001a4, 0xc1000030, 0xc1000034, 
+    0xc10001b4, 0x0003038d, 0xd28f0004, 0xd28f20e0, 0x000301dc, 0x00030380, 0xc10001c4, 0xc10001d4, 
+    0xd03d101a, 0x0003cdc0, 0xd03d1028, 0xd03d102a, 0x00030f8c, 0xc10001e4, 0xc10001f4, 0xc1000204, 
+    0xc1000234, 0xc1000244, 0xc1000254, 0xc1000274, 0xc10002a4, 0xd1800288, 0x000303bc, 0xd180028c, 
+    0xd03c8034, 0xd03c830c, 0xd2154124, 0xd03d104e, 0xc10002b4, 0x000303ec, 0xc10002c4, 0xc10002e4, 
+    0xc10002f4, 0x00030262, 0xd00350f6, 0xc1000304, 0xc1000314, 0x0003021a, 0x000303f4, 0xc1000324, 
+    0x000303fc, 0xc1000334, 0xc1000344, 0xd03c801c, 0x00030346, 0x00030344, 0x00030343, 0xd28f2054, 
+    0x00030341, 0xebfff9f5, 0xeaffffb2, 0xe92d503f, 0xe59f04a4, 0xfb00083e, 0xe3a02103, 0xe3a0104e, 
+    0xe3a00010, 0xfbffeb14, 0xe59f0490, 0xfa008b6c, 0xe59f148c, 0xe200001f, 0xe1c100b0, 0xe59f1484, 
+    0xe1d120f0, 0xe1500002, 0x0a000018, 0xe51f4e90, 0xe3500000, 0xe1c100b0, 0xe1d400b0, 0x0a00001a, 
+    0xe3500000, 0x0a000022, 0xe59f145c, 0xe3a00021, 0xe3a02000, 0xe1c100b0, 0xe51f0ec0, 0xe5900000, 
+    0xfa007bc1, 0xe51f1ef0, 0xe5912000, 0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3a01012, 
+    0xe3800004, 0xe1c400b0, 0xe3a00201, 0xfbffeaf2, 0xe3a02103, 0xe3a0104f, 0xe3a00010, 0xfbffeaee, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3c00004, 0xe3001112, 0xe3a02103, 0xe1c400b0, 0xe3a00201, 
+    0xfbffeae5, 0xe1d400b0, 0xe3500000, 0x0bfff9bb, 0xeaffffee, 0xebfff9b9, 0xeaffffe5, 0xe92d5fff, 
+    0xe59f03c8, 0xfb000802, 0xe3a02103, 0xe3a01050, 0xe3a00010, 0xfbffead8, 0xe59f43b4, 0xe1a00004, 
+    0xfa008b2f, 0xe59f63ac, 0xe1a006a0, 0xe5c60000, 0xe1a00004, 0xfa008b2a, 0xe59f739c, 0xe7e22550, 
+    0xe51f51b0, 0xe51f4f88, 0xe5c72000, 0xe5d51003, 0xe5d60000, 0xe1510000, 0x1a000004, 0xe3500004, 
+    0x1a000023, 0xe5d53004, 0xe1530002, 0x0a000025, 0xe59f9368, 0xe3510000, 0xe51f8fe4, 0x03500007, 
+    0x0a00002a, 0xe59fa358, 0xe3a03000, 0xe3a0200c, 0xe3011000, 0xe1a0000a, 0xfb008b1f, 0xe3a03000, 
+    0xe3a0200b, 0xe3001800, 0xe1a0000a, 0xfb008b1a, 0xe1d400b0, 0xe3d00008, 0x0a000022, 0xe3a00006, 
+    0xe1c900b0, 0xe59f1314, 0xe3a02000, 0xe59f0314, 0xe5900000, 0xfa007b6c, 0xe5981000, 0xe0800001, 
+    0xe5880000, 0xe5d60000, 0xe5c50003, 0xe5d70000, 0xe5c50004, 0xe5d60000, 0xe3500000, 0x01d400b0, 
+    0x03c00008, 0x0a000001, 0xe1d400b0, 0xe3800008, 0xe3a01051, 0xe3a02103, 0xe1c400b0, 0xe3a00010, 
+    0xfbffea95, 0xf57ff05f, 0xe8bd5fff, 0xe25ef004, 0xe3a0006e, 0xe1c900b0, 0xe59f12a0, 0xe3a02000, 
+    0xe59f02a4, 0xeaffffe1, 0xebfff964, 0xeaffffe4, 0xe92d500f, 0xe59f0294, 0xfb0007ad, 0xe3a02103, 
+    0xe3a01074, 0xe3a00010, 0xfbffea83, 0xe3a02103, 0xe3a01075, 0xe3a00010, 0xfbffea7f, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0260, 0xfb00079f, 0xe3a02103, 0xe3a0106c, 0xe3a00010, 
+    0xfbffea75, 0xe3a02103, 0xe3a0106d, 0xe3a00010, 0xfbffea71, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f022c, 0xfb000791, 0xe3a02103, 0xe3a01046, 0xe3a00010, 0xfbffea67, 0xe3a02103, 
+    0xe3a01047, 0xe3a00010, 0xfbffea63, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe3a02103, 
+    0xe3a01081, 0xe3a00010, 0xfbffea5b, 0xe59f01e8, 0xe3a04000, 0xe59f21ec, 0xe1d010b0, 0xe3510001, 
+    0x03a01002, 0x01c010b0, 0xe59f01d0, 0xe59f11d8, 0xe1c040b6, 0xe1c040b4, 0xe1c040b2, 0xe1c040b0, 
+    0xe59f01bc, 0xe5d03000, 0xe59f01b0, 0xfa000efb, 0xe3a00001, 0xfb001a51, 0xe3a01000, 0xe3a00040, 
+    0xfa0006ea, 0xe3a00000, 0xfb001a4c, 0xe59f019c, 0xe3a0100f, 0xfb008a9b, 0xe59f0194, 0xfb000764, 
+    0xe59f0190, 0xe1d000d0, 0xe3500003, 0x13500005, 0x13500004, 0x1a000019, 0xe59f017c, 0xe59f5180, 
+    0xe5901000, 0xe2811001, 0xe5801000, 0xe59f016c, 0xe5d00000, 0xe3500000, 0x0a000017, 0xe3a00501, 
+    0xe3a01071, 0xfbffea19, 0xe1d500b0, 0xe3500014, 0x9a00000a, 0xe3a02103, 0xe3a01081, 0xe3a00010, 
+    0xfbffea25, 0xe3a03000, 0xe59f0138, 0xe1a02003, 0xe3a01001, 0xfb008a88, 0xe1c540b0, 0xebfff8f7, 
+    0xe3a02103, 0xe3a01082, 0xe3a00010, 0xfbffea1a, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3a00005, 
+    0xfa000696, 0xe59f1100, 0xe5911000, 0xe0400001, 0xe3500000, 0xc1d500b0, 0xc2800001, 0xc1c500b0, 
+    0xd1c540b0, 0xdaffffed, 0xeaffffde, 0xe92d500f, 0xe59f00d8, 0xfb00072e, 0xe3a02103, 0xe3a0105c, 
+    0xe3a00010, 0xfbffea04, 0xe3a02103, 0xe3a0105d, 0xe3a00010, 0xfbffea00, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f00a4, 0xfb000720, 0xe3a02103, 0xe3a01062, 0xe3a00010, 0xfbffe9f6, 
+    0xe3a02103, 0xe3a01063, 0xe3a00010, 0xfbffe9f2, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xc1000354, 
+    0xd0020012, 0x00030216, 0x00030218, 0x00030404, 0xc1000364, 0xd0020108, 0x00030214, 0x00030340, 
+    0x0003040c, 0xd28fffd2, 0x000304ec, 0x00030be4, 0xc1000374, 0xc1000394, 0xc10003a4, 0x00030248, 
+    0x00030350, 0x00030394, 0x00030338, 0x00030366, 0xd00305c4, 0xc10003b4, 0x00030222, 0x00030244, 
+    0x00030ae4, 0x00030364, 0xd00305cc, 0x0003024c, 0xc10003c4, 0xc10003d4, 0x47f0e92d, 0x469ab086, 
+    0x46894617, 0xe9dd2200, 0xe02a850e, 0x0180eb00, 0xeb022f00, 0xdd010441, 0xe0002101, 0x28002100, 
+    0x2302dd01, 0x2308e000, 0x4103fb11, 0xf9334bfb, 0x23006011, 0xeb034271, 0xf9352c02, 0x428c401c, 
+    0x46a6dd01, 0x468ee000, 0xda0345b6, 0xdc02428c, 0xe000460c, 0x1c5b4634, 0xf8252bff, 0xd9ea401c, 
+    0x45421c52, 0xea4fd3d2, 0x4eed2148, 0xea4fb20c, 0xea41114a, 0xea4202c7, 0x43010149, 0xf0414630, 
+    0x46390780, 0xfc0bf022, 0x7100f447, 0xf0224630, 0x2000fc06, 0x21019005, 0x1d33462a, 0xe9cd9004, 
+    0x46211002, 0x90019000, 0xfd1ef000, 0x7180f447, 0xf0224630, 0x0275fbf4, 0x126f2400, 0x1c64e002, 
+    0xd20642ac, 0x46392208, 0xf0224630, 0x2800fbff, 0xb006d1f5, 0x87f0e8bd, 0x4fffe92d, 0x4ed1b083, 
+    0x469a2400, 0xf2404693, 0x9f121900, 0x5810e9dd, 0xeb00e00a, 0x464a2344, 0x2104eb07, 0x2004eb08, 
+    0xfa3cf022, 0xb2241c64, 0x42ac6830, 0xe9cddbf1, 0xe9dd5000, 0x46530103, 0xf7ff465a, 0xb007ff6d, 
+    0x8ff0e8bd, 0x4fffe92d, 0x2000b083, 0xba10e9dd, 0x98039002, 0xd0072801, 0xb1389805, 0xf8df2702, 
+    0x260082e4, 0xe0404634, 0xe7f82701, 0xe7f62708, 0xf1ba48b5, 0xf8df0f00, 0xeb0092d4, 0xd10b2584, 
+    0xf2404628, 0xf0231100, 0x230cfb87, 0x22804629, 0x0046eb0b, 0xfb61f022, 0x48ad2108, 0x4aae4bad, 
+    0x0100e9cd, 0x46289902, 0xfcbcf022, 0x230848aa, 0x228049a8, 0x0200f8d0, 0x46296008, 0xf02248a6, 
+    0x48a4fb5d, 0x22802308, 0xf0224649, 0xf8d8fb57, 0xf2400000, 0x46491200, 0x2344eb00, 0xf0224628, 
+    0x3680f9dd, 0xb2361c64, 0x42bcb224, 0xf8d8dbc0, 0xac030000, 0x7000e9cd, 0x000fe894, 0xff0cf7ff, 
+    0xe92de79d, 0x00d247f0, 0xb0864f8d, 0x0541ea42, 0x4305025b, 0xa038f8dd, 0xf883fa0f, 0xf4454638, 
+    0xf0227180, 0x2400fb4c, 0x1900f240, 0xe002027e, 0x42b41c64, 0x2208d206, 0x46384649, 0xfb56f022, 
+    0xd1f52800, 0x7100f445, 0xf0224638, 0x2000fb38, 0x21014a7b, 0x1d129005, 0x90044653, 0x0102e9cd, 
+    0x90004641, 0x20019001, 0xfc4ef000, 0xe92de741, 0xf8df43f8, 0x461d81d0, 0x7608e9dd, 0x3000f8d8, 
+    0x462b9300, 0xffbdf7ff, 0xf2402400, 0xe00c1900, 0x0000f8d8, 0x2304eb06, 0x2204eb07, 0xeb004649, 
+    0xf0222044, 0x1c64f9b0, 0x42acb224, 0xe8bddbf0, 0xe92d83f8, 0x469b4ffe, 0x28012300, 0xd00f9302, 
+    0x2302b182, 0xa17cf8df, 0xf8da4699, 0x93003000, 0xf7ff464b, 0x2600ff96, 0x816cf8df, 0xe04c4634, 
+    0xe7ef2301, 0xe7ed2308, 0xeb084f58, 0xf8da2584, 0x462a0000, 0xf240463b, 0xeb001100, 0xf0222044, 
+    0x4955f982, 0x22802308, 0xf0224628, 0x4951faa6, 0x22802308, 0xf0224638, 0x4a4efaa0, 0x68104b4e, 
+    0x0200f8c3, 0x60102000, 0x0200f8c2, 0xf5c02001, 0xf8537180, 0xf8437020, 0xf8527021, 0x1c407020, 
+    0x427fb200, 0xf8422880, 0xdbf07021, 0x48402108, 0x46479b02, 0xe9cd462a, 0x493e0100, 0xf022483e, 
+    0x980cfecb, 0x2280b168, 0xeb074628, 0xf0222144, 0x3680fa25, 0xb2361c64, 0x454cb224, 0xe8bddbb4, 
+    0x230c8ffe, 0x22804628, 0x0146eb0b, 0xfa76f022, 0xe92de7ef, 0x4a3141f0, 0x460c2500, 0x1700eb02, 
+    0x0000f994, 0xd0152880, 0xf3604240, 0xf9940607, 0x28800001, 0x4240d010, 0x260ff360, 0xeb07b2b1, 
+    0xf0220045, 0x1c6dfa82, 0x1ca4b22d, 0xdbe72d08, 0x81f0e8bd, 0xe7e8207f, 0xe7ed207f, 0x460eb570, 
+    0x2400491e, 0x1500eb01, 0x0044eb05, 0xfa6af022, 0xb241b200, 0xd00d2980, 0xeb064249, 0x12000244, 
+    0x70112880, 0x4240d008, 0x1c647050, 0x2c08b224, 0xbd70dbea, 0xe7f0217f, 0xe7f5207f, 0x4d09b570, 
+    0x68282120, 0xfa48f023, 0x68292400, 0xf7ffb260, 0x1c64ffb0, 0x2c04b224, 0xbd70dbf7, 0x00030424, 
+    0xd1800100, 0x000301b8, 0x000341dc, 0x000361dc, 0x0002bb10, 0x000371dc, 0x000369dc, 0xd00304a2, 
+    0x41fce92d, 0x46074e32, 0x0100f640, 0xf0236830, 0x2500fa23, 0x2f012400, 0xb1acd014, 0x68312002, 
+    0x46222300, 0x0100e9cd, 0x46384629, 0xfdc4f7ff, 0xb2641c64, 0xdbee2c04, 0xb26d1c6d, 0xdbe92d04, 
+    0x81fce8bd, 0xe7ea2001, 0xe7e82008, 0xb5102000, 0xffd6f7ff, 0xf7ff2001, 0xe8bdffd3, 0xe7ad4010, 
+    0x4e1bb57c, 0x46142200, 0xf8236833, 0x1c524012, 0xf823b212, 0x1c520012, 0x2affb212, 0x2501ddf5, 
+    0x29038018, 0x2400d00e, 0x23006830, 0xb261461a, 0x5000e9cd, 0xf7ff2001, 0x1c64fd8f, 0x2c04b224, 
+    0xbd7cdbf2, 0x20014c0b, 0x5300e9cd, 0x461a2300, 0x1000f994, 0xfd80f7ff, 0x23006830, 0xe9cd461a, 
+    0xf9945000, 0x20011001, 0xfd76f7ff, 0x0000bd7c, 0x000301b8, 0x00030338, 0x4fffe92d, 0x48a6b085, 
+    0xb298f8df, 0xf500460d, 0x4ea56a80, 0xf50b9002, 0x48a46980, 0x6880f506, 0x20009004, 0xf2409003, 
+    0x98044100, 0xf9a8f023, 0xf240489f, 0xf0231100, 0x4c9df993, 0xf44f2000, 0x60273780, 0x0280eb04, 
+    0x1c405629, 0x60510289, 0xdbf72810, 0x49972508, 0x46534895, 0x1500e9cd, 0x2102e9dd, 0xfac2f022, 
+    0x01694891, 0xf978f023, 0x60272000, 0xeb049907, 0x56090280, 0x02891c40, 0x28106051, 0x2108dbf6, 
+    0x464b488a, 0xe9cd465a, 0x48870100, 0xf0229903, 0x2400faa9, 0xf85b9902, 0xf8510024, 0xf8595024, 
+    0xf85a1024, 0xfb003024, 0xfb01f205, 0x43432203, 0xfb014340, 0xfb010001, 0x12073515, 0x4639d00a, 
+    0xf0234610, 0xf846f8b9, 0x46390024, 0xf0234628, 0xe004f8b3, 0x1000f240, 0x0024f846, 0xf8482000, 
+    0x1c640024, 0xdbd52c81, 0xe0c39808, 0x1e409812, 0x486fe0b8, 0x28057800, 0xf1bad00d, 0xd0200f01, 
+    0x496c9805, 0x2540eb01, 0xf04f496b, 0xeb010b01, 0x23002440, 0x4d69e067, 0x0f01f1ba, 0x46504c68, 
+    0xf1b9d003, 0xd00a0f00, 0x464a2002, 0x5400e9cd, 0x46839905, 0x46504603, 0xfdf9f7ff, 0x2008e7e9, 
+    0x9805e7f3, 0xeb01495f, 0x495f2540, 0x01d9e7dd, 0x4f5e6830, 0x2011f935, 0xf8474350, 0xf9340021, 
+    0xf8d62011, 0x43500200, 0xf8424a59, 0x20010021, 0xf8561842, 0xf9357020, 0xf934c012, 0xfb07e012, 
+    0xf858f70c, 0xfb0cc020, 0x4f507c1e, 0xc022f847, 0x7020f856, 0xc012f934, 0xe012f935, 0xf70cfb07, 
+    0xc020f858, 0x28801c40, 0x7c0efb0c, 0xf8474f48, 0xdbddc022, 0x7800483e, 0xd1122805, 0xe10cf8df, 
+    0x18422000, 0x28801c40, 0xc022f85e, 0x2c2cea4f, 0xc012f825, 0xc022f857, 0x2c2cea4f, 0xc012f824, 
+    0x1c5bdbef, 0x455bb25b, 0x4831dbb1, 0x28057800, 0x4b37d047, 0x4a352400, 0xf8c26818, 0x20810200, 
+    0xf8c3601c, 0xf5c04200, 0xf8527180, 0xf8425021, 0xf8535020, 0x42491021, 0x1020f843, 0x28ff1c40, 
+    0x2108ddf1, 0x4a204821, 0xe9cd9b03, 0x49280100, 0xf0224826, 0x481cfcc1, 0x9904230c, 0xf0222280, 
+    0x9804f87d, 0xf5002180, 0xf0237080, 0x9804f895, 0xe9cd2300, 0x99050400, 0x4650461a, 0xfcd2f7ff, 
+    0x0001f1a9, 0xea5fb240, 0xf57f0900, 0xf10aaf42, 0xb2400001, 0x46822801, 0xaf38f77f, 0xe8bdb009, 
+    0xf8cd8ff0, 0x2300b000, 0x5401e9cd, 0x464a9905, 0xf7ff4650, 0xe7e3fc91, 0x0003214c, 0x0003114c, 
+    0x0003194c, 0x0003294c, 0x000341dc, 0x0002bb10, 0x00030c58, 0x00039d5c, 0x0003a55c, 0x000331dc, 
+    0x000339dc, 0x00038d5c, 0x0003955c, 0x000369dc, 0x000371dc, 0x43f8e92d, 0x2100460d, 0x91002600, 
+    0x4634b281, 0x48500c07, 0xf84ff022, 0x4639484e, 0xf0221c80, 0x484cf84a, 0x1d004629, 0xf845f022, 
+    0x21004849, 0xf0221d80, 0x4f47f840, 0x0000f44f, 0x8118f8df, 0x90001f3f, 0x4642210e, 0xf0014668, 
+    0x2801f941, 0xb2a3d027, 0x22044841, 0xf02221f0, 0x1c64f846, 0x2c0fb264, 0x2400dd00, 0x23014638, 
+    0x210c2202, 0xf83bf022, 0x46382301, 0x46192200, 0xf835f022, 0x46382500, 0x21012200, 0xf83df022, 
+    0x1c6db158, 0x2d04b22d, 0x2100dbf5, 0xf0224638, 0x2e00f80c, 0xe8bdd0d0, 0x260183f8, 0xe92de7f5, 
+    0x210043f8, 0x91002600, 0x0c05b281, 0x46344826, 0xfffbf021, 0x46294824, 0xf0211c80, 0x4f22fff6, 
+    0x0000f44f, 0x8084f8df, 0x90001f3f, 0x4642210d, 0xf0014668, 0x2801f8f7, 0xb2a3d027, 0x2200481c, 
+    0xf021210f, 0x1c64fffc, 0x2c0fb264, 0x2400dd00, 0x23014638, 0x210c2202, 0xfff1f021, 0x46382301, 
+    0x461a2102, 0xffebf021, 0x46382500, 0x21022201, 0xfff3f021, 0x1c6db170, 0x2d04b22d, 0x2100dbf5, 
+    0xf0214638, 0x2e00ffc2, 0x4807d0d0, 0xf0211d00, 0xe7b0ffb9, 0xe7f22601, 0x4614b570, 0xf7ff460d, 
+    0x4028ffae, 0xbd7040e0, 0xd03d1004, 0xd003517c, 0xd03c80c0, 0xea410589, 0x49620040, 0x4308b510, 
+    0xffa0f021, 0xbd10b200, 0x0107f021, 0x485d4301, 0x3030b289, 0xbf99f021, 0x4c5ab510, 0xeb012107, 
+    0xb2813000, 0x46203430, 0xff8ff021, 0xf0214620, 0xb200ff89, 0xe92dbd10, 0x461d41f0, 0x460c4617, 
+    0xf7ff4606, 0x40bdffe9, 0x402543a0, 0xb2814328, 0xe8bd4630, 0xe7d741f0, 0x219ff360, 0xf440b288, 
+    0x48484100, 0xf0213038, 0xb510bf70, 0x06804c45, 0x34380c01, 0xf0214620, 0x4620ff68, 0xff62f021, 
+    0xbd10b200, 0x41f0e92d, 0x4617461d, 0x4606460c, 0xffebf7ff, 0x43a040bd, 0x43284025, 0x4630b281, 
+    0x41f0e8bd, 0xb510e7d8, 0xf440460c, 0x48356170, 0xf021302e, 0x4833ff4a, 0xe8bd4621, 0x302a4010, 
+    0xbf43f021, 0x460cb510, 0x482e4601, 0x6170f441, 0xea40302e, 0xf0215084, 0x482aff38, 0xea40302a, 
+    0xf0215084, 0xb200ff2f, 0xe92dbd10, 0x461d41f0, 0x460c4617, 0x21004606, 0xffe4f7ff, 0x43a040bd, 
+    0x43284025, 0x4630b281, 0x41f0e8bd, 0x0780e7cb, 0x010ff001, 0xea400c40, 0x481a2101, 0x4311b510, 
+    0x302e461c, 0xff11f021, 0x46214816, 0x4010e8bd, 0xf021302a, 0x0780bf0a, 0x010ff001, 0xea400c40, 
+    0x48102101, 0x302e4311, 0xf021b510, 0x480dfefe, 0xf021302a, 0xb200fef7, 0xe92dbd10, 0x461c47f0, 
+    0x46884617, 0xe9dd4681, 0xf7ff6508, 0x40b5ffe4, 0x463a43a0, 0x46414025, 0xb2834328, 0xe8bd4648, 
+    0xe7c447f0, 0xd28fffc0, 0x5ff0e92d, 0x461f4d53, 0x46902301, 0xb030f8dd, 0xf8dd460c, 0x2102a038, 
+    0x9028f8dd, 0x4628461a, 0xfee9f021, 0x20042100, 0xff5ef000, 0x2c404e4a, 0x7100f643, 0x0660dd08, 
+    0x2310d406, 0x22084630, 0xfec2f021, 0xe01f2310, 0xdd012c1f, 0xd5f406a0, 0xdd082c0f, 0xd40606e0, 
+    0x46302304, 0xf0212208, 0x2304feb3, 0x2c07e010, 0x0720dd08, 0x2302d406, 0x22084630, 0xfea8f021, 
+    0xe0052302, 0x46302301, 0xf0212208, 0x2301fea1, 0x22004630, 0xf021213f, 0x4e31fe9b, 0x21042202, 
+    0x1d36464b, 0xf0214630, 0x2201fe93, 0x2102465b, 0xf0214630, 0x2200fe8d, 0x21014653, 0xf0214630, 
+    0x4e27fe87, 0x9b0b2202, 0x36142104, 0xf0214630, 0x9b0dfe7f, 0x21022201, 0xf0214630, 0x9b0ffe79, 
+    0x21012200, 0xf0214630, 0x481dfe73, 0x46232200, 0x71fff64f, 0xf0211f00, 0x4819fe6b, 0x30084641, 
+    0xfe5df021, 0x46391d30, 0xfe59f021, 0x22002301, 0xf04f4619, 0xf0214040, 0x04b4fe5b, 0x3e084e10, 
+    0x4620e00e, 0xfee2f000, 0xdc091e04, 0x46204c0d, 0xfe48f021, 0x5180f440, 0xf0214620, 0xe004fe46, 
+    0xf0214630, 0x2801fe39, 0x4628d1eb, 0x5ff0e8bd, 0x22012300, 0xf0212102, 0x0000be52, 0xd003529a, 
+    0xc000000c, 0xd003517c, 0x22004884, 0x31fff240, 0xf021b510, 0xb200fe3b, 0xb5f8bd10, 0x20004605, 
+    0xf7ff9000, 0x4c7efff1, 0x80204e7e, 0x0000f44f, 0xe0099000, 0x46322108, 0xf0004668, 0x2801ff23, 
+    0xf7ffd005, 0x8020ffe1, 0x42a88820, 0xbdf8dcf2, 0x5fffe92d, 0x46044d74, 0x468a4e74, 0x46914f74, 
+    0xf8df2202, 0x782881d0, 0xb038f8dd, 0x0101f000, 0xea027830, 0x43010040, 0x22047838, 0x0080ea02, 
+    0xf8984301, 0x22080000, 0x00c0ea02, 0x486a4301, 0x78002210, 0x1000ea02, 0x48684301, 0x78002220, 
+    0x1040ea02, 0x48664301, 0x07807800, 0x6110ea41, 0x3808485a, 0xfdd3f021, 0x01e04962, 0xea407809, 
+    0xf04f1101, 0xf0214048, 0x495ffdca, 0x10caea4f, 0xea407809, 0x48511101, 0xf0213810, 0x495bfdc0, 
+    0x10c9ea4f, 0xea407809, 0x484c1101, 0xf021380c, 0x484afdb6, 0xb19c1f00, 0xf021210f, 0x4847fdb0, 
+    0x1d077839, 0x29011d3c, 0x7829d00c, 0xd0352901, 0x29017831, 0xf898d032, 0x29011000, 0xe011d02e, 
+    0xe7ea2100, 0x4a4b494a, 0x78127809, 0xea410189, 0x4a491102, 0xea417812, 0x4a480182, 0x43117812, 
+    0xfd8df021, 0x46389903, 0xfd89f021, 0x46202300, 0x21062201, 0xfd8cf021, 0x46202301, 0x46192200, 
+    0xfd86f021, 0x0f00f1bb, 0x482cd106, 0x21042202, 0xf0213010, 0xb1e0fd8b, 0x9fffe8bd, 0x88094928, 
+    0xfd6df021, 0x46389903, 0xfd69f021, 0xe7de2301, 0xf0002002, 0x2801fdbb, 0x4c22d00b, 0xf0214620, 
+    0xb004fd61, 0x7100f440, 0xe8bd4620, 0xf0215ff0, 0x2200bd5c, 0x21014620, 0xfd68f021, 0xd1e72800, 
+    0xb5f8e7da, 0x23012500, 0x4629462a, 0x95004628, 0xf882f004, 0x24004e11, 0x46233610, 0x46302203, 
+    0xf0212108, 0x2301fd45, 0x22024630, 0xf0212104, 0x2300fd3f, 0x461a9500, 0x46184619, 0xff28f7ff, 
+    0xb2641c64, 0xdbe82c02, 0x4630b001, 0x22022300, 0x40f0e8bd, 0xf0212104, 0x0000bd2b, 0xc8000014, 
+    0x00030206, 0xd003517a, 0x00030203, 0x00030201, 0x000301fc, 0x000301ff, 0x000301e3, 0x000301e1, 
+    0x000301de, 0x000301e9, 0x000301e7, 0x000301e5, 0x000301f4, 0x000301f5, 0x000301f6, 0x000301f7, 
+    0x41f0e92d, 0x4d1c2301, 0x4607220a, 0x4628029c, 0xf0214621, 0x00a6fd14, 0x46304639, 0xfd88f000, 
+    0x46212300, 0x4628220a, 0xfd09f021, 0x46304639, 0xfd7ef000, 0x22012300, 0x1f282102, 0x41f0e8bd, 
+    0xbcfdf021, 0xb1884b0d, 0x1002ea41, 0x0041ea40, 0x00c1ea40, 0x2001ea40, 0x2041ea40, 0x2081ea40, 
+    0x20c1ea40, 0x4618b281, 0xbccff021, 0xea400110, 0xea400041, 0xe7eb0081, 0xd00350f6, 0xd00352ac, 
+    0x41f0e92d, 0x28014afe, 0xd0094607, 0x2f0249fd, 0x880e48fd, 0xf6478805, 0xd0092012, 0xd0212f03, 
+    0x46102100, 0xfcb1f021, 0x46352600, 0xe0234634, 0x880c49f6, 0x4285b916, 0x4605d200, 0x4006eb05, 
+    0xdc0142a0, 0xb2841e40, 0x4080f240, 0xd2014284, 0xe0044604, 0x6f00f5b4, 0xf240d301, 0xf24074ff, 
+    0xe0061104, 0xb9162400, 0xd2004285, 0xf2404605, 0x46101100, 0xfc89f021, 0x463148e1, 0xf0211d00, 
+    0x48dffc84, 0x1d804629, 0xfc7ff021, 0x462148dc, 0xf0213008, 0x48dafc7a, 0xb10f3822, 0xe0002301, 
+    0x22012300, 0xf0212102, 0x48d9fc8a, 0xe8bd7007, 0x48d881f0, 0xf990b510, 0x48d71000, 0xd0052903, 
+    0xd0122904, 0xd0082905, 0xe0152000, 0x21202205, 0xfc83f021, 0x48d1b180, 0x2204e005, 0xf0212110, 
+    0xb148fc7c, 0x780048ce, 0x2203e006, 0xf0212108, 0xb108fc74, 0xe7f648cb, 0x4010e8bd, 0x48c0e780, 
+    0x2112f240, 0x381cb570, 0xfc3ff021, 0xf64748bc, 0x381a011c, 0xfc39f021, 0xf24048c3, 0xf0212173, 
+    0x48b7fc34, 0x38182102, 0xfc2ff021, 0xf24348b4, 0x46210400, 0xf0213814, 0x48b1fc28, 0x38102120, 
+    0xfc23f021, 0x210048b9, 0xfc1ff021, 0xf24048b7, 0x1c8011fe, 0xfc19f021, 0x230048b4, 0x4621220c, 
+    0xf0213816, 0x48abfc2c, 0x4db24cb1, 0x28037800, 0x2001d07e, 0x203c70a8, 0x78207020, 0x1e400201, 
+    0x7180f5a1, 0x489e4301, 0x380eb289, 0xfbfdf021, 0xf240489b, 0x380c3103, 0xfbf7f021, 0x1e407820, 
+    0x4897b281, 0xf0211f80, 0x7820fbf0, 0xb2811e40, 0x38084893, 0xfbe9f021, 0xf64f489b, 0x38087180, 
+    0xfbe3f021, 0xf64f4898, 0x1f806170, 0xfbddf021, 0x2110488b, 0xf0213822, 0x4889fbd8, 0x210af64a, 
+    0xf0213820, 0x4c94fbd2, 0x4e942209, 0x2100f240, 0xf3407820, 0x46301300, 0xf0211c5b, 0x7820fbe0, 
+    0x01512208, 0x1300f340, 0x1c5b4630, 0xfbd7f021, 0x46302300, 0x21102204, 0xfbd1f021, 0x46302300, 
+    0x461a2101, 0xfbcbf021, 0x46302300, 0x21022201, 0xfbc5f021, 0x46302300, 0x21042202, 0xfbbff021, 
+    0x46302300, 0x21082203, 0xfbb9f021, 0xf3c07820, 0xf00200c0, 0x78a8fd8e, 0x22142128, 0x40c240c1, 
+    0xea411db0, 0xf0212102, 0x78a8fb90, 0xe0002168, 0x2254e0ee, 0x40c240c1, 0xea414870, 0x30082102, 
+    0xfb83f021, 0xf244485e, 0x381e0120, 0xfb7df021, 0xf648486a, 0x30100188, 0xfb77f021, 0x21004867, 
+    0xf0213012, 0x7820fb72, 0x0040f3c0, 0xfda2f002, 0x210c485d, 0xf02130a4, 0x4d5bfb68, 0x7400f641, 
+    0x46212303, 0x22081cad, 0xf0214628, 0x2304fb78, 0x22004628, 0xf021211f, 0x4d53fb72, 0x22082305, 
+    0x35a04621, 0xf0214628, 0x230afb6a, 0x22004628, 0xf021211f, 0x1cadfb64, 0x46282301, 0x21702204, 
+    0xfb5df021, 0x46282300, 0x461a2107, 0xfb57f021, 0x2100484a, 0xf02138a4, 0x4848fb38, 0x38a22100, 
+    0xfb33f021, 0x21024845, 0xf02138b6, 0x4843fb2e, 0x38782100, 0xfb29f021, 0xfebbf7ff, 0x211b4830, 
+    0xf0213844, 0x4e3ffb22, 0x4580f240, 0x2210493c, 0x4630462b, 0xfb1cf021, 0x462b2200, 0x71fff64f, 
+    0xf0214630, 0x4938fb15, 0xf0211d30, 0x4d33fb08, 0x220e2300, 0x0100f24c, 0x46283516, 0xfb1ff021, 
+    0xf6432303, 0x22087100, 0xf0214628, 0x2300fb18, 0x22064628, 0xf02121c0, 0x2303fb12, 0x22004628, 
+    0xf021213f, 0x4827fb0c, 0x22182302, 0xf04f383c, 0xf02161e0, 0x4621faed, 0x23084c1b, 0x461a34a6, 
+    0xf0214620, 0x2302fafc, 0x22044620, 0xf0212130, 0x2307faf6, 0x22004620, 0xf021210f, 0x2109faf0, 
+    0xf0211ea8, 0x4811fad2, 0x310ff244, 0xf0211e80, 0x4812facc, 0x1111f241, 0x4070e8bd, 0xe025300a, 
+    0xd0035114, 0x0003025c, 0x0003025e, 0x00030260, 0x0003025b, 0x00030222, 0xd28f007c, 0x00030257, 
+    0x000302aa, 0x000302a9, 0xd003050a, 0xd0030818, 0x0003025a, 0x00030440, 0x00030259, 0xd00352a0, 
+    0xffff0000, 0xd1800040, 0x00080005, 0xba9df021, 0x7020207c, 0x70a82000, 0xe92de68f, 0x4cfe5ffc, 
+    0xf8df2600, 0x463783f8, 0x4bff48fd, 0x78024dff, 0xf3c248fc, 0x78000180, 0x789bb3e8, 0xf8df706b, 
+    0x4bfcc3f0, 0x1200f342, 0x46e21c52, 0xf7ff469b, 0x4df6fd99, 0x0900f04f, 0x9000f8cd, 0x464a4643, 
+    0xb2417868, 0xf7fe2001, 0x48f3ff64, 0xfaf9f002, 0x786948f1, 0x0011f830, 0x25018128, 0x0015f938, 
+    0xda001e01, 0x42b04248, 0x0008dd04, 0x4248d500, 0xb206462f, 0xb22d1c6d, 0xdbef2d80, 0xb2381fbf, 
+    0xf1c09000, 0xf240007f, 0x90011700, 0x7080f5a7, 0x2000b206, 0xe003e000, 0xf8444605, 0xe01c0026, 
+    0x706b781b, 0xc374f8df, 0xe7bb4bdd, 0x46599800, 0xfa0f4428, 0x1b78f980, 0x0245f3c0, 0xf0204650, 
+    0x43c0fba7, 0x2026f854, 0xf93807c0, 0xd0210019, 0x1c6d4410, 0xf844b22d, 0x98010026, 0xdae542a8, 
+    0xb23f1c7f, 0x7fc0f5b7, 0x2600dbd0, 0x0804f06f, 0xf06f4635, 0xf854077f, 0xf0230025, 0xf023ff99, 
+    0x4642fe05, 0xf933f024, 0xfa46f023, 0xdb03287f, 0xe002217f, 0xe7dc1a10, 0x42b94601, 0x4639dc00, 
+    0xf844b249, 0x1c6d1025, 0x6600fb01, 0x2d80b22d, 0x48b6dbe1, 0x61062500, 0xeb044eba, 0x684100c5, 
+    0x0035f834, 0x201ff361, 0xeb06b281, 0xf0210045, 0x1c6df9ec, 0x2d40b22d, 0xe8bddbef, 0xe92d9ffc, 
+    0x48b147f0, 0x1890f240, 0x92c0f8df, 0x78004ea7, 0xd16a2800, 0x693448a8, 0xfa63f002, 0x787148a6, 
+    0x0011f830, 0x46208170, 0xff6af023, 0x460749a8, 0xff7af023, 0xfdbaf023, 0x22004ca6, 0xf0234623, 
+    0xf06ffabf, 0x462a050b, 0xf8e1f024, 0xf9f4f023, 0x80b01040, 0x46382101, 0xf907f024, 0xfda6f023, 
+    0x46232200, 0xfaacf023, 0xf024462a, 0xf023f8d0, 0x1040f9e3, 0xf00280f0, 0x4540fce1, 0xf8d9d206, 
+    0x28110000, 0x4640d802, 0xfcd3f002, 0x25004f92, 0x703d462c, 0xf0034620, 0x7871f8a6, 0xd100428c, 
+    0x78394605, 0xdd004288, 0x7039b2c1, 0xb2e41c64, 0xd3ef2c04, 0xf6411c6d, 0x2200715e, 0x0065eba1, 
+    0x1ec0b200, 0xeb0017c1, 0xf0216191, 0x1a40013f, 0x487cb283, 0x380a213f, 0xf991f021, 0x2303487f, 
+    0xf247220c, 0xf0210100, 0x88f0f98a, 0xb2814240, 0x380e4874, 0xf969f021, 0x424088b0, 0x4871b281, 
+    0xf021380c, 0x88b0f962, 0xb2814240, 0x3090486d, 0xf95bf021, 0x78004872, 0xf9b6b360, 0xeb000004, 
+    0xf3c00040, 0xf002004f, 0x4866fc84, 0xf021381c, 0x4540f949, 0xf8d9d206, 0x28110000, 0x4640d802, 
+    0xfc77f002, 0x23004865, 0xf240220a, 0x380a4100, 0xf955f021, 0x20082101, 0xfc8ef002, 0xf0022000, 
+    0xf002fcdc, 0x485ffcc1, 0x28027800, 0x2803d005, 0xe009d003, 0x70fff647, 0x4858e7d5, 0x22012300, 
+    0x30142102, 0xf93bf021, 0xe8bd7870, 0xf24f87f0, 0xea401060, 0xb2810041, 0xb510484a, 0xf0213810, 
+    0x4848f914, 0x4100f240, 0xf0211e80, 0x2207f90e, 0xe8bd2101, 0x20004010, 0xbc21f002, 0x47fce92d, 
+    0x80dcf8df, 0x4e482301, 0x4d382200, 0xf8984f47, 0xe9cd0000, 0xf3c07600, 0x78280980, 0x4618b241, 
+    0xfdc5f7fe, 0x20762400, 0x1010f837, 0xf201fb11, 0x1010f836, 0xb2801c40, 0xfb11287f, 0x440c2101, 
+    0x483bd9f2, 0xf8407829, 0x483a4021, 0xf8c7f002, 0x78284939, 0x3020f851, 0xd4011b19, 0xe000460e, 
+    0x4a22424e, 0x24004f33, 0xebb6320c, 0xdb0d0fa3, 0xda002900, 0xebb14249, 0xda050f63, 0x1020f857, 
+    0x13f6f64b, 0xd90f4299, 0xe00d5414, 0xda002900, 0xebb14249, 0xdb050fe3, 0x1020f857, 0x53bdf24a, 
+    0xd2014299, 0x54112101, 0x78004824, 0xf898b190, 0x78131000, 0x4e0b4822, 0x1700f341, 0xb1531c7f, 
+    0xb1437853, 0xb1337893, 0xb12278d2, 0xd03907c9, 0xe03c2300, 0xe04fe047, 0x00038d5c, 0x0003955c, 
+    0x00030259, 0x0003031c, 0x00030330, 0x00030440, 0x8365f253, 0x7425eef5, 0x00030358, 0xaf77a42e, 
+    0xca4fa6c1, 0xd0030510, 0x00030c58, 0x000301cc, 0x40e00000, 0x40220000, 0x00030263, 0xd0035100, 
+    0x00030c5a, 0x00030257, 0x000339dc, 0x000331dc, 0x00030fdc, 0x0003113c, 0x00030fcc, 0x00030241, 
+    0xd00352a0, 0x7809493f, 0xd0072904, 0x2200230f, 0xf021211f, 0x463af874, 0xe0014649, 0xe7f6231f, 
+    0xf7ff7830, 0x7828fb6f, 0xb2c01c40, 0x28047028, 0x702cd300, 0x87fce8bd, 0x211f2300, 0xf021461a, 
+    0x2100f85e, 0xe7eb463a, 0x4d2fb57c, 0x4e2f2400, 0x22002301, 0xb2614618, 0x6500e9cd, 0xfd07f7fe, 
+    0x20762100, 0x2010f836, 0xf302fb12, 0x2010f835, 0xb2801c40, 0xfb12287f, 0x44113202, 0x4824d9f2, 
+    0x1024f840, 0xf8404823, 0x1c641024, 0x2c04b2e4, 0xbd7cd3de, 0xb570481b, 0xf9902423, 0x28040000, 
+    0x2805d002, 0xe002d002, 0xe0002408, 0x481a240d, 0x7161f641, 0x76fff641, 0x78002200, 0xeba11c40, 
+    0x48160550, 0xf0214631, 0x4420f828, 0x1b403008, 0x5000f500, 0x17c1b200, 0x6191eb00, 0x013ff021, 
+    0xd0011a40, 0x0040f1c0, 0x010af242, 0x1a081a28, 0xb2834631, 0xe8bd4809, 0x22004070, 0xf0203096, 
+    0x0000bffe, 0x00030222, 0x000339dc, 0x000331dc, 0x00030fcc, 0x00030fdc, 0x00030263, 0xd003504a, 
+    0x460db570, 0xeb014929, 0x21001000, 0xf0204604, 0x2001ffc6, 0x0185eb00, 0xe8bd4620, 0xf0204070, 
+    0x4922bfbe, 0x1000eb01, 0xf0202102, 0x491fbfb8, 0xeb01b510, 0xf0201000, 0xf3c0ffaf, 0xbd100040, 
+    0x310c491a, 0x1000eb01, 0xbfa6f020, 0x4604b510, 0xd0091c40, 0xf7ff4620, 0xb118fff3, 0xf7ff4620, 
+    0xb108ffe6, 0xbd102000, 0xbd102001, 0x41f0e92d, 0x480e4605, 0x460f4616, 0x1405eb00, 0x46202102, 
+    0xff8df020, 0x46394809, 0xeb003008, 0xf0201005, 0x2100ff86, 0xf0204620, 0x2001ff82, 0x0186eb00, 
+    0xe8bd4620, 0xf02041f0, 0x0000bf7a, 0xc8000100, 0xd0052801, 0xd0032802, 0xd0032804, 0xd0032805, 
+    0x47702000, 0x47702002, 0x47702001, 0x47701e40, 0xe0004088, 0x28001e40, 0x4770d1fc, 0x41f0e92d, 
+    0x460c4e44, 0x810cf8df, 0x1d374605, 0x080cf108, 0x2201e00d, 0x21024630, 0xff68f020, 0xd00e2801, 
+    0x46382200, 0xf0202101, 0x2801ff61, 0x4640d007, 0xff42f020, 0x42a01a28, 0xe8bdd3eb, 0x4c3681f0, 
+    0xf0204620, 0xf440ff3f, 0x46206180, 0x41f0e8bd, 0xbf3bf020, 0x41f0e92d, 0x460e4615, 0x46984607, 
+    0xf0204618, 0xf242ff2f, 0xb1387410, 0xd0142d01, 0x44382000, 0x4640b281, 0xff27f020, 0xf0204640, 
+    0x2800ff21, 0x2d01d1fa, 0x2400d000, 0xb28119a0, 0xe8bd4640, 0xf02041f0, 0x4620bf18, 0xe92de7e9, 
+    0x461c41f0, 0x460e4615, 0x20004607, 0xff58f7ff, 0xe0101b04, 0xf7ff2000, 0x1b00ff53, 0xdc0a2800, 
+    0x46204c15, 0xfefef020, 0x7100f440, 0xe8bd4620, 0xf02041f0, 0x4638befa, 0xfef4f020, 0x42a84030, 
+    0xe7aad1e8, 0x4603b570, 0x460c6800, 0x1e404615, 0x60182800, 0x4610dc0b, 0xfee4f020, 0x40a12101, 
+    0xb2814308, 0xf0204628, 0x2001fee0, 0x2000bd70, 0x0000bd70, 0xc8000120, 0xd003517e, 0xe28fc04d, 
+    0xe12fff1c, 0x2101e7fe, 0xd2042820, 0x23014081, 0x4853b242, 0x3820e004, 0x4081b242, 0x23014851, 
+    0xbec6f020, 0xeb024a50, 0xf0201000, 0x2101beb8, 0xd2052820, 0xb2424081, 0xf04f2300, 0xe0054041, 
+    0xb2423820, 0x48474081, 0x38082300, 0xbeb0f020, 0x28202101, 0x4081d205, 0x2301b242, 0x4041f04f, 
+    0x3820e005, 0x4081b242, 0x2301483e, 0xf0203808, 0x2101be9f, 0xd2042820, 0xb2424081, 0x301c4838, 
+    0x3820e004, 0x4081b242, 0x300c4836, 0xbe9ef020, 0x41f0e92d, 0x4934460d, 0x4613461f, 0x9e063908, 
+    0x1400eb01, 0x46202204, 0xf0202130, 0x2203fe81, 0x21084620, 0xf020462b, 0x2202fe7b, 0x21044620, 
+    0xf020463b, 0x4620fe75, 0xe8bd4633, 0x220041f0, 0xf0202103, 0xb570be6d, 0xe8bdb118, 0xf0204070, 
+    0x4c21be5b, 0x1f244d21, 0xf0204620, 0x3410fe55, 0xd9f942ac, 0xe92dbd70, 0x240141f0, 0xd20e2820, 
+    0xb2424e17, 0x36284084, 0x23014615, 0x46304621, 0xfe4ef020, 0x46212301, 0x462a1d37, 0x3820e00e, 
+    0xb2424e10, 0x36184084, 0x23014615, 0x46304621, 0xfe3ef020, 0x46212301, 0x462a1d37, 0xf0204638, 
+    0x2300fe37, 0x462a4621, 0xf0204630, 0x4621fe31, 0x4638462a, 0x41f0e8bd, 0xf0202300, 0x0000be29, 
+    0xc1000008, 0xc1000508, 0xc1000108, 0xc10003f4, 0xf04fb510, 0xf04f34ff, 0x46214041, 0xfe0ff020, 
+    0x462148fe, 0xfe0bf020, 0x462148fd, 0xfe07f020, 0x462148fa, 0xf0203008, 0x49fafe02, 0xf02048fa, 
+    0x48f9fdfe, 0x301049f9, 0xfdf9f020, 0x49f848f6, 0xf0203020, 0x48f4fdf4, 0x303049f6, 0xfdeff020, 
+    0x49f548f1, 0xf0203040, 0x48effdea, 0x305049f3, 0xfde5f020, 0x49f248ec, 0xf0203060, 0x48eafde0, 
+    0x307049f0, 0xfddbf020, 0x49ef48e7, 0xf0203080, 0x48e5fdd6, 0x309049ed, 0xfdd1f020, 0x49ec48e2, 
+    0xf02030a0, 0x48e0fdcc, 0x30b049ea, 0xfdc7f020, 0x49e948dd, 0xf02030c0, 0x48dbfdc2, 0x30d049e7, 
+    0xfdbdf020, 0x49e648d8, 0xf02030e0, 0x48d6fdb8, 0x30f049e4, 0xfdb3f020, 0x48e449e3, 0xfdaff020, 
+    0x49e348e2, 0xf0203010, 0x48e0fdaa, 0x302049e1, 0xfda5f020, 0x49e048dd, 0xf0203030, 0x48dbfda0, 
+    0x304049de, 0xfd9bf020, 0x49dd48d8, 0xf0203050, 0x48d6fd96, 0x306049db, 0xfd91f020, 0x49da48d3, 
+    0xf0203070, 0x48d1fd8c, 0x308049d6, 0xfd87f020, 0x49d448ce, 0xf0203090, 0x48ccfd82, 0x30a049d3, 
+    0xfd7df020, 0x49d248c9, 0xf02030b0, 0x48c7fd78, 0x30c049d0, 0xfd73f020, 0x49ca48c4, 0xf02030d0, 
+    0x48c2fd6e, 0x30e049cc, 0xfd69f020, 0x49cb48bf, 0xf02030f0, 0x49cafd64, 0xf02048ca, 0x48c9fd60, 
+    0x301049c9, 0xfd5bf020, 0x49c848c6, 0xf0203020, 0x48c4fd56, 0x303049c6, 0xfd51f020, 0x49c548c1, 
+    0xf0203040, 0x48bffd4c, 0x305049c3, 0xfd47f020, 0x49c248bc, 0xf0203060, 0x48bafd42, 0x307049c0, 
+    0xfd3df020, 0x49af48b7, 0xf0203080, 0x48b5fd38, 0x309049bc, 0xfd33f020, 0x49bb48b2, 0xf02030a0, 
+    0x48b0fd2e, 0x30b049b9, 0xfd29f020, 0x49b848ad, 0xf02030c0, 0x48abfd24, 0x30d049b6, 0xfd1ff020, 
+    0x49a048a8, 0xf02030e0, 0x48a6fd1a, 0x4010e8bd, 0x30f0499c, 0xbd13f020, 0x41fce92d, 0xfef8f7ff, 
+    0xf7ff2000, 0xb662fea8, 0x94002400, 0x46232201, 0x46212006, 0xfe7cf7ff, 0xf7ff2006, 0x2300fe48, 
+    0x22019400, 0x20074619, 0xfe72f7ff, 0xf7ff2007, 0x2300fe3e, 0x22039400, 0x20014619, 0xfe68f7ff, 
+    0x94002300, 0x46192203, 0xf7ff2011, 0x2300fe61, 0x22039400, 0x20124619, 0xfe5af7ff, 0xf7ff2001, 
+    0x2011fe26, 0xfe23f7ff, 0xf7ff2012, 0x2300fe20, 0x22029400, 0x46104619, 0xfe4af7ff, 0xf7ff2002, 
+    0x2300fe27, 0x22039400, 0x201e4619, 0xfe40f7ff, 0xf7ff201e, 0x2300fe0c, 0x22039400, 0x201f4619, 
+    0xfe36f7ff, 0xf7ff201f, 0x2201fe02, 0x23009400, 0x201c4611, 0xfe2cf7ff, 0x23014e7f, 0x461a2102, 
+    0xf0204630, 0x487cfccc, 0x75fff64f, 0x382a4629, 0xfcabf020, 0x46294878, 0xf020382c, 0x2300fca6, 
+    0x22024630, 0xf0202104, 0x4873fcba, 0x380a4629, 0xfc9bf020, 0x46294870, 0xf020380c, 0xf006fc96, 
+    0x1e67fed3, 0xf0064638, 0x2301fd47, 0x22004630, 0xf0204619, 0x2201fca4, 0x23009400, 0x20044611, 
+    0xfdf6f7ff, 0xf7ff2004, 0x2300fdc2, 0x22039400, 0x20224619, 0xfdecf7ff, 0xf7ff2022, 0x2300fdb8, 
+    0x22039400, 0x20214619, 0xfde2f7ff, 0xf7ff2021, 0x2300fdae, 0x22019400, 0x20254619, 0xfdd8f7ff, 
+    0xf7ff2025, 0x2300fda4, 0x22019400, 0x20264619, 0xfdcef7ff, 0xf7ff2026, 0x4e50fd9a, 0x78304a50, 
+    0xd0392801, 0x717ff647, 0xf0204610, 0x2300fc4e, 0x22019400, 0x20244619, 0xfdbaf7ff, 0xf7ff2024, 
+    0x2300fd86, 0x22019400, 0x20094619, 0xfdb0f7ff, 0x46294843, 0xf0203814, 0x4841fc38, 0x38124629, 
+    0xfc33f020, 0xf248483e, 0x46290500, 0xf0203818, 0x483bfc2c, 0x38164629, 0xfc27f020, 0xf7ff2009, 
+    0x2300fd66, 0x70e0f64f, 0x90002201, 0x90012107, 0xf01b4618, 0xe065faf3, 0x0000e0b3, 0xc1000500, 
+    0xc1000008, 0x00004168, 0xc1000108, 0x000044e8, 0x0000452c, 0x000046a0, 0x00004814, 0x00004a94, 
+    0x00004acc, 0x00004c34, 0x00004c80, 0x00004cb8, 0x00004e50, 0x00004ebc, 0x00004fec, 0x00005058, 
+    0x00005090, 0x00005128, 0x00005160, 0xc1000208, 0x00005198, 0x000051dc, 0x00005220, 0x00005238, 
+    0x00005250, 0x00007a05, 0x00005288, 0x000052c0, 0x00005434, 0x000054cc, 0x00005530, 0x00005548, 
+    0x0000558c, 0xc1000308, 0x000055c4, 0x00005690, 0x0000577c, 0x000057b4, 0x000059cc, 0x00005abc, 
+    0x00005c10, 0x00005c48, 0x00005c80, 0x00005cb8, 0x00005e0c, 0x00005e44, 0xd0039046, 0x00030302, 
+    0xd03c8092, 0x94002201, 0x46102300, 0x94012107, 0xfa84f01b, 0x70f8f64f, 0x23009000, 0x22019001, 
+    0x20022107, 0xfa7af01b, 0x002af249, 0x23009000, 0x22019001, 0x20032107, 0xfa70f01b, 0x1091f244, 
+    0x23009000, 0x22019001, 0x2004211e, 0xfa66f01b, 0x94002201, 0x46112300, 0xf7ff201a, 0x201afcf9, 
+    0xfcc5f7ff, 0xfd23f005, 0x94002201, 0x46112300, 0xf7ff202b, 0x202bfced, 0xfcb9f7ff, 0xfd7ff01d, 
+    0xf01d4638, 0x2300fd65, 0x22019400, 0x200e4619, 0xfcdef7ff, 0xf7ff200e, 0x7830fcaa, 0xd0032801, 
+    0xf647e00e, 0xe70f617f, 0xfe57f01e, 0x94002201, 0x46112300, 0xf7ff201b, 0x201bfccb, 0xfc97f7ff, 
+    0x41fce8bd, 0xf64b4802, 0xf02031bb, 0x0000bb4e, 0xd03c80b8, 0x46032200, 0x2103481d, 0xbb48f020, 
+    0x4c1cb510, 0x22042300, 0x46202110, 0xfb40f020, 0x46202301, 0x21402206, 0xfb3af020, 0x46202300, 
+    0x21402206, 0xfb34f020, 0x46202301, 0xe8bd2204, 0x21104010, 0xbb2cf020, 0x4c0eb510, 0x22052300, 
+    0x46202120, 0xfb24f020, 0x46202301, 0x21802207, 0xfb1ef020, 0x46202300, 0x21802207, 0xfb18f020, 
+    0x46202301, 0xe8bd2205, 0x21204010, 0xbb10f020, 0xd1800900, 0xd1800800, 0x4e50b570, 0x21012200, 
+    0xf6404605, 0x46030400, 0xf0204630, 0x2d01fb01, 0x4635d017, 0x46280526, 0x4631221f, 0xfb06f020, 
+    0xd00e2801, 0xb2241e64, 0xdcf42c00, 0x46204c44, 0xfae8f020, 0x4100f440, 0xe8bd4620, 0xf0204070, 
+    0xbd70bae4, 0x2200483d, 0xb5102101, 0xfaeef020, 0xbd10b240, 0x4c39b570, 0x22104615, 0x1d24460e, 
+    0xf44f4603, 0x4620017f, 0xfad2f020, 0x46332200, 0x462021ff, 0xfaccf020, 0x4620462b, 0x4070e8bd, 
+    0xf64f2208, 0xf0207100, 0xb570bac3, 0x22104c2b, 0x492c460d, 0x46033420, 0xf0204620, 0x462bfab9, 
+    0xe8bd4620, 0x22004070, 0x71fff64f, 0xbab0f020, 0x4c22b570, 0x460d2204, 0x341c4603, 0x462021f0, 
+    0xfaa6f020, 0x4620462b, 0x4070e8bd, 0x210f2200, 0xba9ef020, 0x41f0e92d, 0x461f4c18, 0x460e4615, 
+    0x46033408, 0xf241220c, 0x46200100, 0xfa90f020, 0x46332208, 0x01514620, 0xfa8af020, 0x462b2204, 
+    0x462021f0, 0xfa84f020, 0x4620463b, 0x41f0e8bd, 0x21032200, 0xba7cf020, 0x4c08b570, 0x21f0461d, 
+    0x34144613, 0x46202204, 0xfa72f020, 0x4620462b, 0x4070e8bd, 0x210f2200, 0xba6af020, 0xd1800000, 
+    0xd003517c, 0xffff0000, 0x41f0e92d, 0x460e1e52, 0xb2541e5b, 0x4603b25d, 0xf04f2218, 0x4ffe51f8, 
+    0xf0204638, 0x2210fa55, 0xf44f4633, 0x463811f8, 0xfa4ef020, 0x46232208, 0x7100f641, 0xf0204638, 
+    0x462bfa47, 0xe8bd4638, 0x220041f0, 0xf020211f, 0xe92dba3f, 0xf44f4ff8, 0x46802780, 0x461d2000, 
+    0xa028f8dd, 0x460e4614, 0x0110f243, 0x46389000, 0xf927f7f8, 0xf1041c70, 0xd0010001, 0xe011b188, 
+    0x261ab108, 0x2100e00e, 0xf7f84638, 0x2100f909, 0xf7f84638, 0x2100f905, 0xf7f84638, 0xe8bdf901, 
+    0x241a8ff8, 0x9370f8df, 0xf1a92300, 0x2204090c, 0x21104648, 0xfa0cf020, 0x461a2300, 0xb270b261, 
+    0xffa2f7ff, 0x461a2300, 0x46184619, 0xff84f7ff, 0x20012100, 0xff4cf7ff, 0x464148cf, 0xf0203018, 
+    0x48cdf9ee, 0x22002301, 0x30244619, 0xf9f0f020, 0x1f0048c9, 0xf9e0f020, 0x46384601, 0xf8d0f7f8, 
+    0xf02048c5, 0x4601f9d9, 0xf7f84638, 0x4641f8c9, 0xf7f84638, 0x4ec1f8c5, 0x2000f240, 0xf7ff7831, 
+    0xf8dffa67, 0x4cbf82fc, 0x0000f898, 0xf994b948, 0xb1152000, 0x4629980b, 0x2100e001, 0xf0014608, 
+    0x2301fb69, 0x2211464f, 0x04594648, 0xf9c0f020, 0x46382301, 0x46192200, 0xf9baf020, 0xb2c8f8df, 
+    0x0000f44f, 0x4900f04f, 0xe0069000, 0x465a2101, 0xf7ff4668, 0x2801fab7, 0x221fd006, 0x46384649, 
+    0xf9b4f020, 0xd0f12800, 0x0000f898, 0xf1bab970, 0xd0040f00, 0x2000f994, 0x980b4629, 0xb12de004, 
+    0xf9942100, 0x46082000, 0xfb34f001, 0x46382301, 0x03d9220f, 0xf98cf020, 0xf2407831, 0xf7ff2000, 
+    0xe76cfa17, 0x43f8e92d, 0x2680f44f, 0x20004680, 0x460d4614, 0x0120f243, 0x46309000, 0xf871f7f8, 
+    0xf1041c68, 0xd0010001, 0xe011b188, 0x251ab108, 0x2100e00e, 0xf7f84630, 0x2100f853, 0xf7f84630, 
+    0x2100f84f, 0xf7f84630, 0xe8bdf84b, 0x241a83f8, 0x23004f81, 0x22043f0c, 0x21104638, 0xf958f020, 
+    0x46082100, 0xb26ab263, 0xfeeef7ff, 0x461a2300, 0x46184619, 0xfed0f7ff, 0x20002101, 0xfe98f7ff, 
+    0x46414875, 0xf0203018, 0x4873f93a, 0x22002301, 0x30244619, 0xf93cf020, 0x1f00486f, 0xf92cf020, 
+    0x46304601, 0xf81cf7f8, 0xf020486b, 0x4601f925, 0xf7f84630, 0x4641f815, 0xf7f84630, 0x4c67f811, 
+    0x2800f240, 0x78214640, 0xf9b2f7ff, 0x46382301, 0x04592211, 0xf91cf020, 0x46382301, 0x46192200, 
+    0xf916f020, 0xf44f4d60, 0x90000000, 0x02061ead, 0x210fe006, 0x4668462a, 0xfa14f7ff, 0xd0062801, 
+    0x4631221f, 0xf0204638, 0x2800f911, 0x2301d0f1, 0x220f4638, 0xf02003d9, 0x7821f8fb, 0xf7ff4640, 
+    0xe792f987, 0x4fffe92d, 0x469bb081, 0x46162000, 0x2980f44f, 0xe9dd460f, 0xf8dd540e, 0xf2438044, 
+    0x90000130, 0xf7f74648, 0x1c78ffdc, 0x1c70d101, 0x1c68d002, 0xe004d004, 0xd1021c68, 0xd0031c60, 
+    0x1c60251a, 0xe010d010, 0x464c2100, 0xf7f74648, 0x2100ffb7, 0xf7f74620, 0x2100ffb3, 0xf7f74620, 
+    0xb005ffaf, 0x8ff0e8bd, 0xf8df241a, 0x2301a0cc, 0x0a0cf1aa, 0x46502204, 0xf0202110, 0xb263f8b9, 
+    0xb271b26a, 0xf7ffb278, 0x2300fe4f, 0x4619461a, 0xf7ff4618, 0x9810fe31, 0xfa4fb241, 0xf7fff08b, 
+    0x4825fdf7, 0x30189901, 0xf899f020, 0x23014822, 0x46192200, 0xf0203024, 0x481ff89b, 0xf0201f00, 
+    0x4601f88b, 0x4648464c, 0xff7af7f7, 0xf020481a, 0x4601f883, 0xf7f74620, 0x9901ff73, 0xf7f74620, 
+    0x4d16ff6f, 0x2b00f240, 0x78294658, 0xf910f7ff, 0x4c144e13, 0xb9587830, 0x2000f994, 0x0008ea5f, 
+    0x4601d002, 0xe0019813, 0x46082100, 0xfa12f001, 0x46572301, 0x46502211, 0xf0200459, 0x2301f869, 
+    0x22004638, 0xf0204619, 0xf8dff863, 0xf44fa01c, 0xf04f0000, 0xe0094900, 0xd180000c, 0x00030223, 
+    0x0003031c, 0x00030227, 0xd003517c, 0xe0069000, 0x46522100, 0xf7ff4668, 0x2801f955, 0x221fd006, 
+    0x46384649, 0xf852f020, 0xd0f12800, 0xb9787830, 0xb1209812, 0x2000f994, 0x98134641, 0xf1b8e006, 
+    0xd0050f00, 0xf9942100, 0x46082000, 0xf9d2f001, 0x46382301, 0x03d9220f, 0xf82af020, 0x46587829, 
+    0xf8b6f7ff, 0xe92de75d, 0xf44f47f0, 0x461e2480, 0x46894617, 0xf2434680, 0x46200160, 0xff11f7f7, 
+    0x23014dcd, 0x21102204, 0xf0204628, 0xb27bf811, 0xf188fa4f, 0x4608461a, 0xfda6f7ff, 0x461a2300, 
+    0x46184619, 0xfd88f7ff, 0xfa4fb271, 0xf7fff089, 0x48c1fd4f, 0x21012300, 0x3030461a, 0xfff8f01f, 
+    0x300848bd, 0xffe8f01f, 0x46204601, 0xfed8f7f7, 0x300c48b9, 0xffe0f01f, 0x46204601, 0xfed0f7f7, 
+    0x46202100, 0xfeccf7f7, 0x46282300, 0x10612211, 0xffdef01f, 0xe8bd4628, 0x230147f0, 0x46192200, 
+    0xbfd6f01f, 0xb51048ad, 0x7800b086, 0x2000b188, 0x21019004, 0x22099005, 0xe9cd460b, 0x200b1002, 
+    0x90004611, 0xf2409001, 0xf7ff2000, 0xb006fecb, 0x4ca3bd10, 0x21012200, 0xf01f4620, 0xb990ffde, 
+    0x46202201, 0xf01f2102, 0xb960ffd8, 0x46202202, 0xf01f2104, 0xb930ffd2, 0x46202203, 0xf01f2108, 
+    0x2800ffcc, 0x2001d0d4, 0x4894e7d2, 0xb087b530, 0xb9d07800, 0x22004c92, 0x46202101, 0xffbdf01f, 
+    0x2201b988, 0x21024620, 0xffb7f01f, 0x2202b958, 0x21044620, 0xffb1f01f, 0x2203b928, 0x21084620, 
+    0xffabf01f, 0x2401b108, 0x2400e000, 0x25019404, 0x9000200b, 0x462b2209, 0x5402e9cd, 0x94054611, 
+    0x02689001, 0xfe7ef7ff, 0x9000200c, 0x94042301, 0x9405220a, 0x5402e9cd, 0x90014611, 0xf7ff02d8, 
+    0xb007fe71, 0x220bbd30, 0x2000f240, 0xb5104611, 0xfdd8f7ff, 0xf640220c, 0xe8bd0000, 0x46114010, 
+    0x486ee5d0, 0x7800b51c, 0x4c6db9d0, 0x21012200, 0xf01f4620, 0xb988ff72, 0x46202201, 0xf01f2102, 
+    0xb958ff6c, 0x46202202, 0xf01f2104, 0xb928ff66, 0x46202203, 0xf01f2108, 0xb108ff60, 0xe0002401, 
+    0xf2402400, 0x22092000, 0x46114623, 0x94019400, 0xfceff7ff, 0x4623220a, 0xf6404611, 0x94000000, 
+    0xf7ff9401, 0xbd1cfce6, 0x41ffe92d, 0x466c2300, 0x429a2200, 0x2108d101, 0x2102e000, 0x1542eb00, 
+    0xeb051e49, 0xe00305c3, 0xb91e5c6e, 0xb2491e49, 0xdaf92900, 0x0582eb04, 0x1c521c49, 0x2a04b252, 
+    0xdbe654e9, 0xb25b1c5b, 0xdbe12b04, 0x46182300, 0x0180eb04, 0x42995609, 0x460bdd00, 0xb2401c40, 
+    0xdbf52804, 0x22044d3c, 0x350821f0, 0xf01f4628, 0x2300feef, 0x20004619, 0xd0054288, 0x0280eb04, 
+    0x429a5652, 0x4613dd00, 0xb2401c40, 0xdbf32804, 0xb2491c49, 0xdbee2904, 0x46282200, 0xf01f2103, 
+    0x4d2dfed7, 0x46283548, 0xfec6f01f, 0x4601230f, 0x27012200, 0xeb042000, 0x5cb60680, 0xfa07b916, 
+    0x43b1f603, 0x1e5b1c40, 0x2804b240, 0x1c52dbf3, 0x2a04b252, 0x4628dbee, 0xfeb1f01f, 0x81ffe8bd, 
+    0x41f0e92d, 0x46042300, 0x20004619, 0xd0054288, 0x0280eb04, 0x429a5652, 0x4613dd00, 0xb2401c40, 
+    0xdbf32804, 0xb2491c49, 0xdbee2904, 0x22084812, 0x30080151, 0xfe9cf01f, 0x35484d0f, 0xf01f4628, 
+    0x231ffe8b, 0x22004601, 0x20002601, 0x0780eb04, 0xb9175cbf, 0xf703fa06, 0x1c4043b9, 0xb2401e5b, 
+    0xdbf32804, 0xb2521c52, 0xdbee2a04, 0xe8bd4628, 0xf01f41f0, 0x0000be74, 0xd1800000, 0x0003031c, 
+    0xd0030024, 0x22002301, 0xb5104619, 0xf01f48fe, 0x2300fe86, 0x210148fd, 0xf01f461a, 0xe8bdfe80, 
+    0x48fb4010, 0x0140f242, 0xbe5ff01f, 0x4df7b570, 0x2203b28b, 0x1ead4604, 0x46282108, 0xfe6ff01f, 
+    0x4628b2a3, 0x4070e8bd, 0x21042202, 0xbe67f01f, 0x4deeb570, 0x2201b28b, 0x1ead4604, 0x46282102, 
+    0xfe5df01f, 0x4628b2a3, 0x4070e8bd, 0x21012200, 0xbe55f01f, 0x4de5b570, 0x2206b283, 0x1ead460c, 
+    0x46282140, 0xfe4bf01f, 0x4628b2a3, 0x4070e8bd, 0x21202205, 0xbe43f01f, 0x48dcb283, 0xf2402208, 
+    0x1e803100, 0xbe3bf01f, 0x41f0e92d, 0x4690461f, 0x46084604, 0x5606e9dd, 0xffeef7ff, 0x462043e1, 
+    0xffd8f7ff, 0x46404639, 0xffc2f7ff, 0x46284631, 0x41f0e8bd, 0xb570e7aa, 0x23014dcc, 0x03de220f, 
+    0x46311ead, 0xf01f4628, 0x2301fe1a, 0x22074628, 0xf01f2180, 0x2001fe14, 0xffcef7ff, 0xe00f0234, 
+    0xf7fe4620, 0x1e04fe83, 0x4cc2dc0a, 0xf01f4620, 0xf040fde9, 0x46200101, 0x4070e8bd, 0xbde5f01f, 
+    0x4631220f, 0xf01f4628, 0x2800fe08, 0xbd70d1e8, 0x230148b6, 0x21102204, 0xf01f1e80, 0xe92dbdf0, 
+    0x4db241f0, 0x4000f500, 0xb281460f, 0x46283d14, 0xfdcbf01f, 0x0400f44f, 0xe00e1226, 0xf7fe4620, 
+    0x1e04fe55, 0x4cabdc09, 0xf01f4620, 0xf040fdbb, 0x46200102, 0xfdb9f01f, 0x220fe006, 0x46284631, 
+    0xfddbf01f, 0xd1e92800, 0xf2424639, 0xe8bd0000, 0xf7fe41f0, 0xb570be3d, 0x46164d9e, 0x4604220f, 
+    0x460b3d9a, 0x0100f248, 0xf01f4628, 0x220dfdb8, 0xf2464633, 0x46280100, 0xfdb1f01f, 0x4628b2a3, 
+    0x4070e8bd, 0xf6412200, 0xf01f71ff, 0xb283bda8, 0x2200488e, 0x30602101, 0xbda1f01f, 0x41f0e92d, 
+    0x461e4d8a, 0xf248b293, 0x35200400, 0x220f4688, 0x46214607, 0xf01f4628, 0xb2bbfd92, 0x77fff240, 
+    0x46392200, 0xf01f4628, 0x4621fd8a, 0xb2b31eac, 0x220f4620, 0xfd83f01f, 0xf388fa1f, 0x46204639, 
+    0x41f0e8bd, 0xf01f2200, 0xb570bd7a, 0x48794605, 0x46162301, 0x460c3892, 0x461a2102, 0xfd6ff01f, 
+    0x0045ea44, 0xb2834c73, 0x71fff640, 0x22003c8e, 0xf01f4620, 0x2301fd64, 0x220c4620, 0xf01f0319, 
+    0x4631fd5e, 0x4070e8bd, 0xf7fe2004, 0xb570bdd1, 0x48684605, 0x46162301, 0x460c3898, 0x461a2102, 
+    0xfd4df01f, 0x0045ea44, 0xb2834c62, 0x71fff640, 0x22003c96, 0xf01f4620, 0x2301fd42, 0x220c4620, 
+    0xf01f0319, 0x4631fd3c, 0x4070e8bd, 0xf7fe2004, 0xe92dbdaf, 0x4d5847f0, 0x461f0004, 0x46894690, 
+    0x0300f04f, 0xf240d418, 0x46282600, 0x46312209, 0xfd25f01f, 0x2301e00d, 0x22094631, 0xf01f4628, 
+    0x2300fd1e, 0x22094631, 0xf01f4628, 0x1e64fd18, 0x2c00b224, 0xe016dcef, 0x46282208, 0x46310156, 
+    0xfd0df01f, 0x2301e00d, 0x22084631, 0xf01f4628, 0x2300fd06, 0x22084631, 0xf01f4628, 0x1c64fd00, 
+    0x2c00b224, 0x2004dbef, 0xf7fe4639, 0x463afd71, 0x46484641, 0x47f0e8bd, 0xb570e777, 0xb2834d33, 
+    0x4604220b, 0xf6401cad, 0x46280100, 0xfce7f01f, 0x4628b2a3, 0x4070e8bd, 0xf241220c, 0xf01f0100, 
+    0xe92dbcde, 0x4c2d41f0, 0x46062904, 0x2800f240, 0x4500f240, 0x2905d002, 0xe009d004, 0x46032209, 
+    0xe0024641, 0x4603220a, 0x46204629, 0xfcc7f01f, 0x220c4f1e, 0xf2414633, 0x1ebf0100, 0xf01f4638, 
+    0x220dfcbe, 0xf2424633, 0x46380100, 0xfcb7f01f, 0x4633220b, 0x0100f640, 0xf01f4638, 0x2202fcb0, 
+    0x21044633, 0xf01f1cb8, 0x4811fcaa, 0xf01f3010, 0x220ffc89, 0x1d384633, 0x0100f248, 0xfc9ff01f, 
+    0x2300b98e, 0x220a4629, 0xf01f4638, 0x2209fc98, 0x46414633, 0xf01f4620, 0x220afc92, 0x46294633, 
+    0xf01f4620, 0xe00bfc8c, 0xd0020126, 0xd0035024, 0xd0020000, 0xd003517e, 0xd0035092, 0xd0039000, 
+    0xe8bd2001, 0xb57081f0, 0x23004db1, 0x46042203, 0x46282108, 0xfc73f01f, 0x46282300, 0x21042202, 
+    0xfc6df01f, 0x46282300, 0x461a2101, 0xfc67f01f, 0x1cae2300, 0x2101461a, 0xf01f4630, 0xb374fc60, 
+    0xd0362c01, 0xd0342c02, 0xd1402c03, 0x46282300, 0x21102204, 0xfc53f01f, 0x46302300, 0x21042202, 
+    0xfc4df01f, 0x46282301, 0x21082203, 0xfc47f01f, 0x46282301, 0x21042202, 0xfc41f01f, 0x46282301, 
+    0x46192200, 0xfc3bf01f, 0x22002301, 0x46304619, 0xfc35f01f, 0xe8bd2000, 0xf0134070, 0x2300bc1d, 
+    0x22044628, 0xf01f2110, 0x2300fc2a, 0x21042202, 0x2301e7ed, 0x22044628, 0xf01f2110, 0x2301fc20, 
+    0x22024630, 0xf01f2104, 0x2001fc1a, 0xbd70e7e3, 0x5ff0e92d, 0x487e4604, 0x4693469a, 0x46892200, 
+    0xf240387c, 0xf24033c2, 0xf01f31ff, 0xf8dffc08, 0x2c0481e0, 0x0500f247, 0x1600f240, 0x087ef1a8, 
+    0x6700f240, 0x2c05d002, 0xe01cd01a, 0x0f00f1b9, 0xf1bad119, 0xd0160f03, 0x46402301, 0x46192200, 
+    0xfbedf01f, 0x46402302, 0x21062201, 0xfbe7f01f, 0x46312301, 0x46402208, 0xfbe1f01f, 0xe02f2302, 
+    0x0f00f1bb, 0x2300d019, 0x22014640, 0xf01f2106, 0x2300fbd6, 0x22094639, 0xf01f4640, 0x2300fbd0, 
+    0x22084631, 0xf01f4640, 0x2300fbca, 0x461a2101, 0xe8bd4640, 0xf01f5ff0, 0x2301bbc2, 0x22004640, 
+    0xf01f4619, 0x2303fbbc, 0x22014640, 0xf01f2106, 0x2301fbb6, 0x22084631, 0xf01f4640, 0x2303fbb0, 
+    0x22094639, 0xf01f4640, 0x2301fbaa, 0x220c4629, 0xe92de7de, 0x4c475ff0, 0x4f47000d, 0xf8dfd048, 
+    0x28048118, 0x0a02f104, 0x76fff240, 0x081cf108, 0x0902f108, 0x0b04f104, 0x2805d04b, 0x2200d175, 
+    0x2101460b, 0xf01f4620, 0x2300fb8a, 0x22014620, 0xf01f2102, 0x2200fb84, 0x2101462b, 0xf01f4638, 
+    0xf240fb7e, 0x464011e1, 0xfb5ff01f, 0x46482100, 0xfb5bf01f, 0xf2402200, 0x46312382, 0xf01f4650, 
+    0x2300fb6e, 0x461a4631, 0xf01f4658, 0xf240fb68, 0x4829237c, 0x46312200, 0xf01f1f00, 0x4826fb60, 
+    0x461a2300, 0x1e804631, 0x5ff0e8bd, 0xbb57f01f, 0x46202300, 0x21022201, 0xfb51f01f, 0x46202300, 
+    0x461a2101, 0xfb4bf01f, 0x46382300, 0x461a2101, 0x2200e7ea, 0x2101460b, 0xf01f4620, 0x2300fb40, 
+    0x22014620, 0xf01f2102, 0x2200fb3a, 0x2101462b, 0xf01f4638, 0xf240fb34, 0x464051a2, 0xfb15f01f, 
+    0x46482100, 0xfb11f01f, 0xf2402200, 0x463133d2, 0xf01f4650, 0x2300fb24, 0x461a4631, 0xf01f4658, 
+    0xf240fb1e, 0xe7b43384, 0xe8bde7ff, 0x00009ff0, 0xd0035336, 0xd00352dc, 0xd00352e6, 0x5ff0e92d, 
+    0x460c2301, 0x46052102, 0x4efe461a, 0xf01f4630, 0x48fdfb06, 0xb9287800, 0x46302301, 0x46192200, 
+    0xfafdf01f, 0xa3dcf8df, 0x220f2301, 0xf10a03df, 0x46390a02, 0x465046d1, 0xfaf1f01f, 0x0800f246, 
+    0x23014648, 0x220d4641, 0xfae9f01f, 0x76fff641, 0x23294648, 0x22004631, 0xfae1f01f, 0x0902f10a, 
+    0x23004639, 0x220f4648, 0xfad9f01f, 0x46412303, 0x4648220d, 0xfad3f01f, 0x46312305, 0x46482200, 
+    0xfacdf01f, 0x0902f109, 0x23014639, 0x220f4648, 0xfac5f01f, 0x46412301, 0x4648220d, 0xfabff01f, 
+    0x46312324, 0x46482200, 0xfab9f01f, 0x0b02f109, 0x23014639, 0x220f4658, 0xfab1f01f, 0x2c01b134, 
+    0x2c02d006, 0x2c03d004, 0xe009d004, 0xe0022301, 0xe0002303, 0x46412302, 0x4658220d, 0xfa9ff01f, 
+    0x46312300, 0x4658461a, 0xfa99f01f, 0xb314f8df, 0x220f2300, 0xf10b4639, 0x46580b0a, 0xfa8ff01f, 
+    0x46442301, 0x4641220d, 0xf01f4658, 0x2304fa88, 0x22004631, 0xf01f4658, 0x4639fa82, 0x0702f10b, 
+    0x46382300, 0xf01f220f, 0x2301fa7a, 0x220d4621, 0xf01f4638, 0x4cb3fa74, 0xf6412200, 0x46317373, 
+    0x462034f0, 0xfa6bf01f, 0xd0022d04, 0xd00f2d05, 0x230ee021, 0x22004631, 0xf01f4650, 0x2200fa60, 
+    0x738ef641, 0x46204631, 0xfa59f01f, 0xe00d2309, 0x46312313, 0x46502200, 0xfa51f01f, 0xf6412200, 
+    0x46317389, 0xf01f4620, 0x230efa4a, 0x22004631, 0xf01f4648, 0x489dfa44, 0x28017800, 0x2300d114, 
+    0x217f489b, 0xf01f461a, 0x4c99fa3a, 0x220823c8, 0x7100f64f, 0x46201ca4, 0xfa31f01f, 0x46202310, 
+    0x21ff2200, 0xfa2bf01f, 0x5ff0e8bd, 0xf0002001, 0xe92dbc22, 0x4c8f47f0, 0x7100f641, 0xc234f8df, 
+    0x35f0f240, 0xf24f3c96, 0x1ca70600, 0x0306f04f, 0xf04f2804, 0xf10c0208, 0x46880902, 0xd02d4660, 
+    0xfa0df01f, 0x46202303, 0x210f2200, 0xfa07f01f, 0x4629230c, 0x46202204, 0xfa01f01f, 0x46312304, 
+    0x4620220c, 0xf9fbf01f, 0x46382303, 0x210f2200, 0xf9f5f01f, 0x4629230d, 0x46382204, 0xf9eff01f, 
+    0x46412302, 0x46482208, 0xf9e9f01f, 0x46384631, 0x47f0e8bd, 0x220c2304, 0xb9e1f01f, 0xf9dff01f, 
+    0x46202303, 0x210f2200, 0xf9d9f01f, 0x4629230b, 0x46202204, 0xf9d3f01f, 0x46312304, 0x4620220c, 
+    0xf9cdf01f, 0x46382303, 0x210f2200, 0xf9c7f01f, 0xe7d0230c, 0x41fce92d, 0x20032400, 0xf7fe9401, 
+    0x2002faf7, 0xfaf4f7fe, 0xf7fe2001, 0x2011faf1, 0xfaeef7fe, 0xf7fe2012, 0x2001faeb, 0xf9d1f7fe, 
+    0xf7fe2002, 0x2004f9ce, 0xf9cbf7fe, 0x48522301, 0x0319220c, 0xf9a3f01f, 0x70044850, 0x68004850, 
+    0xd1072801, 0xf640484f, 0x60040100, 0x6800484e, 0xf962f020, 0x8800484d, 0x2301b128, 0x2200484c, 
+    0xf01f4619, 0xf005f98c, 0x2001fedb, 0xfc95f7ff, 0xf6412200, 0x20040300, 0x94004611, 0xfc9cf001, 
+    0x78014844, 0xf7ff2000, 0x4836fc9c, 0x22012300, 0x38b02102, 0xf973f01f, 0x22084c32, 0x34522300, 
+    0x46200151, 0xf96bf01f, 0xf44f4d2e, 0x4f2d0100, 0x910135a8, 0x3fa8138e, 0x2103e00c, 0xa801462a, 
+    0xfa50f7fe, 0xd00c2801, 0x46312301, 0x46202209, 0xf955f01f, 0x46382206, 0xf01f2140, 0x2800f95e, 
+    0x2200d1eb, 0x0400f242, 0x46104621, 0xfbb0f013, 0x46212200, 0xf0044610, 0x4d27fdaa, 0x22032301, 
+    0x46282108, 0xf93bf01f, 0x46282300, 0x21082203, 0xf935f01f, 0x78004821, 0xfc12f7fd, 0x23014d20, 
+    0x4621220d, 0xf01f4628, 0x2301f92a, 0x03de1daf, 0x220f4638, 0xf01f4631, 0x2300f922, 0x220f4631, 
+    0xf01f4638, 0x2300f91c, 0x220d4621, 0xf01f4628, 0x2000f916, 0xfad0f7ff, 0xf00f2001, 0xf010fe8f, 
+    0xe01ffb23, 0xd00350d4, 0x0003031c, 0x000302d7, 0xd0030480, 0xd0035332, 0xd003902c, 0x000301dc, 
+    0x00047f74, 0x00047ff0, 0x000301c0, 0x00030220, 0xd28f20e0, 0x00030222, 0xd0036100, 0x00030223, 
+    0xd03c8306, 0xfa58f7f8, 0x23004c2d, 0x461a2101, 0xf01f4620, 0x2300f8e4, 0x22014620, 0xf01f2102, 
+    0x2300f8de, 0x22024620, 0xf01f2104, 0x2300f8d8, 0x22034620, 0xf01f2108, 0x4822f8d2, 0x220f2300, 
+    0xf01f4631, 0xe8bdf8cc, 0x210281fc, 0x422bf04f, 0xb5100488, 0xfff3f7f6, 0xf0042003, 0x2006f8d3, 
+    0xf8d0f004, 0xfb81f001, 0x78004817, 0xd1072801, 0x48162301, 0xe8bd2202, 0x21044010, 0xb8aff01f, 
+    0x2101bd10, 0x422bf04f, 0xb51004c8, 0xffd7f7f6, 0xf0042000, 0x480cf8b7, 0x28017800, 0x480bd10f, 
+    0x22062303, 0x11c0f240, 0xf01f3008, 0x2300f898, 0x22024806, 0x4010e8bd, 0xf01f2104, 0xbd10b890, 
+    0xd0035018, 0xd28f201c, 0x00030302, 0xd003902c, 0x41f0e92d, 0x8464f8df, 0xb283461c, 0x22064615, 
+    0x21c0460e, 0x46404607, 0xf879f01f, 0x4640b2b3, 0x21302204, 0xf873f01f, 0x4640b2ab, 0x210c2202, 
+    0xf86df01f, 0x4640b2a3, 0x21032200, 0xf867f01f, 0x8428f8df, 0x2206b2bb, 0x081cf108, 0x464021c0, 
+    0xf85df01f, 0x4640b2b3, 0x21302204, 0xf857f01f, 0x4640b2ab, 0x210c2202, 0xf851f01f, 0x4640b2a3, 
+    0x21032200, 0xf84bf01f, 0x4ffdb2bb, 0x21032200, 0xf01f4638, 0xb2b3f844, 0x22024638, 0xf01f210c, 
+    0xb2abf83e, 0x22044638, 0xf01f2130, 0xb2a3f838, 0xe8bd4638, 0x220641f0, 0xf01f21c0, 0xb570b830, 
+    0x23014cee, 0x46052200, 0x46193c40, 0xf01f4620, 0x4aeaf826, 0x4620462b, 0x4070e8bd, 0x21013a2e, 
+    0xbf3df01f, 0x460db570, 0xf7ff4604, 0x2200ffe8, 0x0022f854, 0xd90142a8, 0xbd702001, 0xb2521c52, 
+    0xdbf52a04, 0xbd702000, 0x4605b570, 0x230048db, 0x0100f248, 0x3834220f, 0xf801f01f, 0x24004ed7, 
+    0xf8353e12, 0xf3c00014, 0xf4400009, 0xeb066180, 0xf01e0044, 0x1c64ffda, 0x2c04b264, 0xbd70dbf1, 
+    0x48ceb283, 0x21012200, 0xf01e383e, 0xe92dbfe8, 0x4fca47f0, 0xf640b293, 0x46140800, 0x460d3f1e, 
+    0x4606220b, 0x46384641, 0xffd9f01e, 0x0900f247, 0xb2ab4638, 0x220c4649, 0xffd1f01e, 0x0a00f248, 
+    0xb2b34638, 0x220f4651, 0xffc9f01e, 0x46411cbf, 0x4638b2a3, 0xf01e220b, 0xb2abffc2, 0x220c4649, 
+    0xf01e4638, 0xb2b3ffbc, 0x220f4651, 0xf01e4638, 0x1cbfffb6, 0xb2a34641, 0x220b4638, 0xffaff01e, 
+    0x4649b2ab, 0x4638220c, 0xffa9f01e, 0x4651b2b3, 0x4638220f, 0xffa3f01e, 0x4641b2a3, 0x220b1cbc, 
+    0xf01e4620, 0xb2abff9c, 0x220c4649, 0xf01e4620, 0xb2b3ff96, 0x46204651, 0x47f0e8bd, 0xf01e220f, 
+    0xb510bf8e, 0x489d4604, 0xf01e380a, 0xf000ff6b, 0x8020001f, 0x38084899, 0xff64f01e, 0x001ff000, 
+    0x48968060, 0xf01e1f80, 0xf000ff5d, 0x80a0001f, 0x1f004892, 0xff56f01e, 0x001ff000, 0xbd1080e0, 
+    0x41f0e92d, 0x460c2b03, 0xd1084605, 0x1002f992, 0xf8252001, 0xf9920011, 0xf8251003, 0x48890011, 
+    0x210f2200, 0xff69f01e, 0x22008821, 0x80204408, 0x210f4885, 0xff61f01e, 0x22008861, 0x80604408, 
+    0x210f4882, 0xff59f01e, 0x220088a1, 0x80a04408, 0x210f487f, 0xff51f01e, 0x230188e1, 0x44082205, 
+    0x4c7880e0, 0x3c2e2120, 0xf01e4620, 0x4e76ff38, 0x22052301, 0x21203e2e, 0xf01e4630, 0x4f73ff30, 
+    0x22052301, 0x21203f2e, 0xf01e4638, 0xf8dfff28, 0x230181c0, 0xf1a82205, 0x2120082e, 0xf01e4640, 
+    0x2300ff1e, 0x22054620, 0xf01e2120, 0x2300ff18, 0x22054630, 0xf01e2120, 0x2300ff12, 0x22054638, 
+    0xf01e2120, 0x2300ff0c, 0x22054640, 0xf01e2120, 0x4e5aff06, 0x3e0a2400, 0x0014f815, 0x001ff000, 
+    0x0120f040, 0x0044eb06, 0xfedff01e, 0xb2641c64, 0xdbf12c04, 0x81f0e8bd, 0x4605b5f0, 0xf5b52000, 
+    0x46043f80, 0x210fd301, 0x2107e000, 0x2701004a, 0xf302fa07, 0xfa001c4a, 0x4422f202, 0x42aa441a, 
+    0xfa07d804, 0xea46f601, 0x46140000, 0xea4fd003, 0xf1a10393, 0x29000101, 0x42aadb01, 0xbdf0d1ea, 
+    0x460cb510, 0x483d4601, 0xf01e1e80, 0x4621feae, 0xe8bd4840, 0xf01e4010, 0x4838bea8, 0x21022301, 
+    0x3840461a, 0xbebbf01e, 0x4d3bb570, 0x4614b283, 0x220c460e, 0x0100f24f, 0xf01e4628, 0x2208feb0, 
+    0xb2b34628, 0xf01e0151, 0x2c03feaa, 0x2c02d013, 0x2c01d01b, 0x2c00d023, 0x2300d12b, 0x22044628, 
+    0xf01e2110, 0x2300fe9c, 0x461a2101, 0xe8bd4628, 0xf01e4070, 0x2300be94, 0x22074628, 0xf01e2180, 
+    0x2300fe8e, 0x21082203, 0x2300e7f0, 0x22064628, 0xf01e2140, 0x2300fe84, 0x21042202, 0x2300e7e6, 
+    0x22054628, 0xf01e2120, 0x2300fe7a, 0x21022201, 0xbd70e7dc, 0x4d18b570, 0x460c2a03, 0x2a02d013, 
+    0x2a01d02c, 0x2a00d034, 0xb283d13c, 0x22044628, 0xf01e2110, 0x2200fe64, 0x2101b2a3, 0xe8bd4628, 
+    0xf01e4070, 0xb283be5c, 0x22074628, 0xf01e2180, 0x2203fe56, 0x2108b2a3, 0x0000e7f0, 0xd0030446, 
+    0xd0035124, 0xd003c2c2, 0xd003cac2, 0xd003d2c2, 0xd003dac2, 0xd0031012, 0xd0030024, 0x4628b283, 
+    0x21402206, 0xfe3bf01e, 0xb2a32202, 0xe7d52104, 0x4628b283, 0x21202205, 0xfe31f01e, 0xb2a32201, 
+    0xe7cb2102, 0x2200bd70, 0x48e5b283, 0xf01e2101, 0xb570be26, 0x220c4ce3, 0x46034605, 0x0100f241, 
+    0xf01e4620, 0x462bfe1c, 0xe8bd4620, 0x220a4070, 0x4100f240, 0xbe13f01e, 0x48da4603, 0x210f2200, 
+    0xf01e3048, 0x48d7be0c, 0x3048b510, 0xfdeaf01e, 0x000ff000, 0x4603bd10, 0x220048d2, 0x31fff240, 
+    0xf01e1d00, 0xb510bdfc, 0x46042207, 0x46032180, 0xf01e48cc, 0x48cbfdf4, 0x21012200, 0x30444623, 
+    0xfdedf01e, 0x46232200, 0x4010e8bd, 0x210148c6, 0xbde5f01e, 0x4cc3b570, 0x4605220d, 0xf2424603, 
+    0x46200100, 0xfddbf01e, 0x4620462b, 0x4070e8bd, 0xf640220b, 0xf01e0100, 0xe92dbdd2, 0x4db85fff, 
+    0x46922301, 0x3d20460c, 0x22064683, 0x21404628, 0xfdc5f01e, 0x46282301, 0x21042202, 0xfdbff01e, 
+    0x46282301, 0x461a2102, 0xfdb9f01e, 0x46282301, 0x46192200, 0xfdb3f01e, 0x23011cae, 0x22064630, 
+    0xf01e2140, 0x2301fdac, 0x22024630, 0xf01e2104, 0x2301fda6, 0x21024630, 0xf01e461a, 0x2301fda0, 
+    0x22004630, 0xf01e4619, 0xf105fd9a, 0x23010804, 0x22064647, 0x21404640, 0xfd91f01e, 0x46382301, 
+    0x21042202, 0xfd8bf01e, 0x46382301, 0x461a2102, 0xfd85f01e, 0x46382301, 0x46192200, 0xfd7ff01e, 
+    0x23011daf, 0x22064638, 0xf01e2140, 0x2301fd78, 0x22024638, 0xf01e2104, 0x2301fd72, 0x21024638, 
+    0xf01e461a, 0x2301fd6c, 0x22004638, 0xf01e4619, 0xf107fd66, 0x23010904, 0x22024648, 0xf01e2104, 
+    0x2301fd5e, 0x21024648, 0xf01e461a, 0x2301fd58, 0x22004648, 0xf01e4619, 0xf1bbfd52, 0xd14c0f03, 
+    0x2c02b10c, 0xf1bad102, 0xd0260f01, 0xb2c09803, 0xd022281b, 0x46402100, 0xfd27f01e, 0x46382100, 
+    0xfd23f01e, 0x46282300, 0x21022201, 0xfd37f01e, 0x46282300, 0x461a2101, 0xfd31f01e, 0x46302300, 
+    0x21022201, 0xfd2bf01e, 0x46302300, 0x461a2101, 0xe8bdb004, 0xf01e5ff0, 0x2100bd22, 0xf01e4628, 
+    0x2100fd04, 0xf01e4630, 0x2300fd00, 0x22024644, 0x21044640, 0xfd13f01e, 0x46202300, 0x21022201, 
+    0xfd0df01e, 0x46382300, 0x21042202, 0xfd07f01e, 0x46382300, 0x21022201, 0xe8bde7da, 0xb5709fff, 
+    0x46144d50, 0x460e2201, 0x460335f2, 0x46282102, 0xfcf5f01e, 0x46281e64, 0x2204b2a3, 0xf01e2170, 
+    0x4633fcee, 0xe8bd4628, 0x22004070, 0xf01e2101, 0x4601bce6, 0x30f44843, 0xbcc7f01e, 0x30f44841, 
+    0xbcc0f01e, 0x483fb283, 0xf2402200, 0x303071ff, 0xbcd5f01e, 0x4c3bb510, 0x2200b283, 0x71fff643, 
+    0x46203416, 0xfccbf01e, 0x46202301, 0xe8bd220e, 0x03994010, 0xbcc3f01e, 0x460b2200, 0x46112801, 
+    0x2802d00e, 0x2804d009, 0x2808d004, 0x2203d109, 0xe0062108, 0x21042202, 0x2201e003, 0xe0002102, 
+    0x482a2101, 0xbcabf01e, 0x460b2200, 0x46112801, 0x2802d010, 0x2804d00b, 0x2808d005, 0x220cd10b, 
+    0x0100f247, 0x2208e007, 0x7100f240, 0x2170e003, 0xe0002204, 0x481d2107, 0xf01e1c80, 0x4601bc90, 
+    0x1d00481a, 0xbc71f01e, 0x210f4818, 0xf01e1f00, 0x4603bc6c, 0x22004815, 0x3828211f, 0xbc7ff01e, 
+    0x48124601, 0xf01e382a, 0x4603bc60, 0x2208480f, 0x7100f640, 0xf01e382c, 0x4603bc72, 0x2200480b, 
+    0x382c2101, 0xbc6bf01e, 0xf04f7800, 0xb1100100, 0x38204803, 0x4802e001, 0xf01e381a, 0x0000bc46, 
+    0xd0030020, 0xd0030400, 0xd0031012, 0xd00305de, 0x41f0e92d, 0x48fe4604, 0xfc21f7ff, 0x21004bfd, 
+    0xf24a4dfd, 0x4afa0700, 0x2662f249, 0xb9b05c60, 0x28126818, 0x2816d00d, 0xf995d00b, 0x28040000, 
+    0x2805d007, 0xf852d005, 0x42b00021, 0x2001d905, 0xf852e004, 0x42b80021, 0x2000d8f9, 0x1c495460, 
+    0x2904b249, 0xe8bddbe2, 0x200181f0, 0xf012b510, 0x2000fbaf, 0xfe27f7ff, 0xf2402100, 0xf7ff1000, 
+    0x2201fd4f, 0x20472100, 0xfe55f7fe, 0xf7ff204e, 0x48e2ff41, 0xf6407801, 0xe8bd0000, 0xf7fd4010, 
+    0xe92dbc87, 0xb0874ff3, 0x0b04f04f, 0x90022000, 0x90049003, 0x48da9005, 0x28037800, 0xf04fd101, 
+    0x27000b02, 0x48d7e081, 0x980857c4, 0xa802b1f8, 0x6014f930, 0xf930a804, 0xf2065014, 0xfb1612ff, 
+    0xf240f006, 0xfb1531fe, 0x428a0005, 0xf205d803, 0x428a12ff, 0x0100d921, 0xfceef7ff, 0x04f1b200, 
+    0xf2f0fb91, 0xfb9104e9, 0x1080f1f0, 0xf8dfe020, 0x23018318, 0x22004dc5, 0x46184621, 0x5800e9cd, 
+    0xf885f7fc, 0xf9b5a802, 0xf9b86040, 0xf8205040, 0xa8046014, 0x5014f820, 0x0280e7cf, 0xfcccf7ff, 
+    0x05b1b200, 0xf2f0fb91, 0xfb9105a9, 0x1140f1f0, 0xf44f4680, 0xea4f3000, 0xea4f1a62, 0xf6401961, 
+    0xf7f60101, 0xf44ffa8e, 0x46313000, 0xfa78f7f6, 0x3000f44f, 0xf7f64629, 0xf44ffa73, 0x46493000, 
+    0xfa6ef7f6, 0x3000f44f, 0xf7f64651, 0xf44ffa69, 0x46413000, 0xfa64f7f6, 0xfa1f48a5, 0xeb00f18a, 
+    0xf01e0084, 0x48a2fb72, 0xf189fa1f, 0xeb001c80, 0xf01e0084, 0x489efb6a, 0xf188fa1f, 0xeb003810, 
+    0xf01e0044, 0x1c7ffb62, 0x455fb2ff, 0xaf7bf4ff, 0x23024c97, 0xf64f2208, 0x3c1e7100, 0xf01e4620, 
+    0x2201fb6e, 0x210e4620, 0x234ff3c8, 0xfb67f01e, 0x22009807, 0xb2832101, 0xf01e4620, 0xb009fb60, 
+    0x8ff0e8bd, 0xb5102000, 0xfec9f7ff, 0x20082101, 0xfe92f7ff, 0x20042101, 0xfe8ef7ff, 0x20022101, 
+    0xfe8af7ff, 0x46082101, 0xfe86f7ff, 0x20082103, 0xfe9af7ff, 0x20042103, 0xfe96f7ff, 0x20022103, 
+    0xfe92f7ff, 0x20012103, 0xfe8ef7ff, 0x3000f240, 0xfeb6f7ff, 0xf7ff2010, 0x2005feac, 0xfeb5f7ff, 
+    0x4010e8bd, 0xbea0f7ff, 0x21004872, 0xf01eb510, 0xf7fffb0c, 0xe8bdffc7, 0x201c4010, 0xbc47f7fd, 
+    0x4ff0e92d, 0xf8dfb087, 0x240091b0, 0x3bfff04f, 0x0814f10d, 0xae014625, 0x0a0cf10d, 0xf8d99500, 
+    0x22003000, 0x464f2001, 0xf7fbb261, 0xf828ffe2, 0xf8265014, 0x683ab014, 0x46c42000, 0x1010f932, 
+    0xda001e0b, 0xf93c4259, 0x42b97014, 0x2b00dd06, 0x425bda00, 0x3014f82c, 0x0014f826, 0xb2001c40, 
+    0xdbeb2880, 0x0014f936, 0x46072300, 0xf932e008, 0x29001010, 0x4249da00, 0x44191c40, 0xb200b20b, 
+    0xdbf42880, 0x46d62000, 0x1ce3ea4f, 0xf82a4603, 0xe00d5014, 0x1010f932, 0xda002900, 0x44194249, 
+    0x4563b20b, 0xf82edd02, 0xe0030014, 0xb2001c40, 0xdcef4287, 0xb2241c64, 0xdbaf2c04, 0x22002001, 
+    0xf9364611, 0xf9363010, 0x42a34012, 0x4602dd00, 0x4010f93e, 0x5011f93e, 0xf9361b1b, 0x1b644011, 
+    0xdd0042a3, 0x1c404601, 0x2804b200, 0xf836dbe9, 0xf8360012, 0xf83a2011, 0xebc01011, 0x1a400042, 
+    0xb2043808, 0xdd6f2c00, 0xd00107e0, 0xb2241c64, 0x4e224d2a, 0xeb008828, 0x80280064, 0x10607831, 
+    0xfc9df7fe, 0x22017833, 0x1000f9b5, 0xf7fe4620, 0x7831fd50, 0x1000f240, 0xfafaf7fd, 0x0500f44f, 
+    0x11f4f240, 0xf7f64628, 0xf04ff95c, 0x46283134, 0xf946f7f6, 0x1004f9bd, 0xf7f64628, 0xf9bdf941, 
+    0x46281006, 0xf93cf7f6, 0x1008f9bd, 0xf7f64628, 0xf9bdf937, 0x4628100a, 0xf932f7f6, 0x100cf9bd, 
+    0xf7f64628, 0xf9bdf92d, 0x4628100e, 0x0000e018, 0x0003113c, 0x000301cc, 0x00030222, 0x00030223, 
+    0x00030394, 0x00030338, 0x000339dc, 0x000331dc, 0xd0030040, 0xd0030400, 0x000301c4, 0x00030320, 
+    0xf90ef7f6, 0x1010f9bd, 0xf7f64628, 0xf9bdf909, 0x46281012, 0xf904f7f6, 0x46284621, 0xf900f7f6, 
+    0x462849a6, 0xf8fcf7f6, 0xe6c9b007, 0x47fce92d, 0x928cf8df, 0x46062500, 0x240046a8, 0xd10242ac, 
+    0x0000f04f, 0xda02e004, 0x0001f104, 0x4620e000, 0x7000f8d9, 0xfa80fa4f, 0x463b4629, 0xf04f4652, 
+    0xf8cd0001, 0xf7fb8000, 0xeb06fee4, 0x5d400084, 0x2180b958, 0xf01f4638, 0x2300f9df, 0x20014652, 
+    0xe9cd4629, 0xf7fb7800, 0x1c64fe1d, 0x2c04b264, 0x1c6ddbd4, 0x2d04b26d, 0x2400dbcf, 0x20004621, 
+    0xd0044288, 0x0280eb06, 0xb1025c52, 0x1c402401, 0x2804b240, 0x1c49dbf4, 0x2904b249, 0x4e81dbef, 
+    0xf01e4630, 0xb200f9bf, 0xf040b16c, 0x24000507, 0xeb06b2a9, 0xf01e0044, 0x1c64f9b8, 0x2c04b264, 
+    0xe8bddbf6, 0xf02087fc, 0xe7f00507, 0x4ff0e92d, 0x275a4875, 0x21012200, 0xf01eb087, 0xb240f9b7, 
+    0x20009005, 0xfe98f7fd, 0x91b4f8df, 0xf10d2600, 0x46b00b04, 0x42b42400, 0xf04fd102, 0xe0040000, 
+    0xf104da02, 0xe0000001, 0xf8d94620, 0xb242a000, 0x46534631, 0x0001f04f, 0x8000f8cd, 0xfe79f7fb, 
+    0x46502500, 0x01e92280, 0xfcd4f013, 0xdc0342b8, 0xb26d1e6d, 0xdaf42d00, 0x0084eb0b, 0x42b41c6d, 
+    0xd1015585, 0x55812101, 0xb2641c64, 0xdbd22c04, 0xb2761c76, 0xdbcd2e04, 0xf7ffa801, 0xa801ff57, 
+    0xfaaef7fe, 0xf7fd9805, 0xf44ffe57, 0xf2400400, 0x462011f4, 0xf855f7f6, 0xf01e484a, 0x4601f953, 
+    0xf7f64620, 0x4847f83d, 0xf01e1c80, 0x4601f94b, 0xf7f64620, 0x4843f835, 0xf01e1d00, 0x4601f943, 
+    0xf7f64620, 0x483ff82d, 0xf01e1d80, 0x4601f93b, 0xf7f64620, 0x483cf825, 0xf01e3008, 0x4601f92d, 
+    0xf7f64620, 0x4838f81d, 0xf01e3048, 0x4601f925, 0xf7f64620, 0x4931f815, 0xf7f64620, 0xe713f811, 
+    0x43f8e92d, 0x80b8f8df, 0x460d2400, 0x46274606, 0x39fff04f, 0x22009700, 0x3000f8d8, 0xb2612001, 
+    0xfe07f7fb, 0x7014f825, 0x46422000, 0x9014f826, 0xf9316811, 0x1e0b1010, 0x4259da00, 0xc014f935, 
+    0xdd064561, 0xd5000019, 0xf8254259, 0xf8261014, 0x1c400014, 0x2880b200, 0x1c64dbea, 0x2c04b224, 
+    0xe8bddbd8, 0xe92d83f8, 0x4d1543f8, 0x460a2100, 0xb2419100, 0x682b2001, 0xfddbf7fb, 0xf8d52200, 
+    0x46138000, 0x46114610, 0xf8384614, 0xfb155014, 0x17eef505, 0x41731952, 0xce04fba5, 0xfb0617e7, 
+    0xfb05e604, 0xeb1c6507, 0x41690000, 0xb2241c64, 0xdbea2c80, 0xea50f01d, 0xe7d2b200, 0xdcba01f5, 
+    0x000301c4, 0xd0030000, 0xd1800000, 0x5fffe92d, 0x4df92301, 0x460c220e, 0x4628039f, 0xf01e4639, 
+    0xf241f8ce, 0x46280900, 0x46492301, 0xf01e220c, 0xf640f8c6, 0x46280a00, 0x46512301, 0xf01e220b, 
+    0xf240f8be, 0x46284b00, 0x46592301, 0xf01e220a, 0x2301f8b6, 0x22094628, 0xf01e0259, 0x2208f8b0, 
+    0x23014628, 0xf01e0151, 0x2301f8aa, 0x22074628, 0xf01e2180, 0x2301f8a4, 0x22064628, 0xf01e2140, 
+    0x1caef89e, 0x23014639, 0x220e4630, 0xf897f01e, 0x46492301, 0x4630220c, 0xf891f01e, 0x46512301, 
+    0x4630220b, 0xf88bf01e, 0x46592301, 0x4630220a, 0xf885f01e, 0x46302301, 0x02592209, 0xf87ff01e, 
+    0x46302208, 0x01512301, 0xf879f01e, 0x46302301, 0x21802207, 0xf873f01e, 0x46302301, 0x21402206, 
+    0xf86df01e, 0x0804f105, 0x23014639, 0x220e4640, 0xf865f01e, 0x46492301, 0x4640220c, 0xf85ff01e, 
+    0x46512301, 0x4640220b, 0xf859f01e, 0x46592301, 0x4640220a, 0xf853f01e, 0x46402301, 0x02592209, 
+    0xf84df01e, 0x46402208, 0x01512301, 0xf847f01e, 0x46402301, 0x21802207, 0xf841f01e, 0x46402301, 
+    0x21402206, 0xf83bf01e, 0x1daf4639, 0x46382301, 0xf01e220e, 0x2301f834, 0x220c4649, 0xf01e4638, 
+    0x2301f82e, 0x220b4651, 0xf01e4638, 0x2301f828, 0x220a4659, 0xf01e4638, 0x2301f822, 0x22094638, 
+    0xf01e0259, 0x2208f81c, 0x23014638, 0xf01e0151, 0x2301f816, 0x22074638, 0xf01e2180, 0x2301f810, 
+    0x22064638, 0xf01e2140, 0x2301f80a, 0x22054628, 0xf01e2120, 0x2301f804, 0x22034628, 0xf01d2108, 
+    0x2301fffe, 0x21024628, 0xf01d461a, 0x2301fff8, 0x22054630, 0xf01d2120, 0x2301fff2, 0x22034630, 
+    0xf01d2108, 0x2301ffec, 0x21024630, 0xf01d461a, 0x2301ffe6, 0x22054640, 0xf01d2120, 0x2301ffe0, 
+    0x22034640, 0xf01d2108, 0x2301ffda, 0x21024640, 0xf01d461a, 0x2301ffd4, 0x22054638, 0xf01d2120, 
+    0x2301ffce, 0x22034638, 0xf01d2108, 0x2301ffc8, 0x21024638, 0xf01d461a, 0x2301ffc2, 0x22044628, 
+    0xf01d2110, 0x2301ffbc, 0x22024628, 0xf01d2104, 0x2301ffb6, 0x22004628, 0xf01d4619, 0x2301ffb0, 
+    0x22044630, 0xf01d2110, 0x2301ffaa, 0x22024630, 0xf01d2104, 0x2301ffa4, 0x22004630, 0xf01d4619, 
+    0x2301ff9e, 0x22044640, 0xf01d2110, 0x2301ff98, 0x22024640, 0xf01d2104, 0x2301ff92, 0x22004640, 
+    0xf01d4619, 0x2301ff8c, 0x22044638, 0xf01d2110, 0x2301ff86, 0x22024638, 0xf01d2104, 0x2301ff80, 
+    0x22004638, 0xf01d4619, 0x9800ff7a, 0xd1412803, 0x2c02b10c, 0x9802d102, 0xd0522801, 0xb2c09803, 
+    0xd04e281b, 0x46282300, 0x21082203, 0xff67f01d, 0x46282300, 0x21042202, 0xff61f01d, 0x46282300, 
+    0x21022201, 0xff5bf01d, 0x46282300, 0x461a2101, 0xff55f01d, 0x46302300, 0x21082203, 0xff4ff01d, 
+    0x46302300, 0x21042202, 0xff49f01d, 0x46302300, 0x21022201, 0xff43f01d, 0x46302300, 0x461a2101, 
+    0xff3df01d, 0x46402100, 0xff1ff01d, 0x46382100, 0xff1bf01d, 0x23014c28, 0x34082202, 0x46202104, 
+    0xff2df01d, 0x46202301, 0x461a2102, 0xff27f01d, 0x4620b004, 0x22002301, 0xe8bd4619, 0xf01d5ff0, 
+    0x2100bf1e, 0xf01d4628, 0x2100ff00, 0xf01d4630, 0x2300fefc, 0x22054644, 0x21204640, 0xff0ff01d, 
+    0x46202300, 0x21102204, 0xff09f01d, 0x46202300, 0x21082203, 0xff03f01d, 0x46202300, 0x21042202, 
+    0xfefdf01d, 0x46382300, 0x21202205, 0xfef7f01d, 0x46382300, 0x21102204, 0xfef1f01d, 0x46382300, 
+    0x21082203, 0xfeebf01d, 0x46382300, 0x21042202, 0xfee5f01d, 0x0000e7ae, 0xd0031000, 0x46032200, 
+    0x217f482d, 0xbedbf01d, 0x4604b510, 0xf64f482a, 0x302471ff, 0xfeb9f01d, 0x21004827, 0xf01d3026, 
+    0x4825feb4, 0x2200b2a3, 0xe8bd2101, 0x30224010, 0xbec5f01d, 0x41f0e92d, 0x461d4c1f, 0x4616b283, 
+    0x460f1ca4, 0x46202206, 0xf01d21c0, 0xb2bbfeb8, 0x22044620, 0xf01d2130, 0xb2b3feb2, 0x22024620, 
+    0xf01d210c, 0xb2abfeac, 0xe8bd4620, 0x220041f0, 0xf01d2103, 0xb283bea4, 0x2200480f, 0x1d002101, 
+    0xbe9df01d, 0x0004b570, 0x2300d013, 0x22014d0a, 0x21023522, 0xf01d4628, 0xb2a3fe92, 0x22004628, 
+    0xf01d2101, 0x2104fe8c, 0xe8bd1da8, 0xf01d4070, 0x2301be6c, 0x0000e7ea, 0xd003100e, 0x5fffe92d, 
+    0xa248f8df, 0x46812500, 0x489146ab, 0x0045eb00, 0xf01d9003, 0xb207fe57, 0x42ac2400, 0xf04fd102, 
+    0xe0040000, 0xf104da02, 0xe0000001, 0x42ac4620, 0x9002b240, 0xf04fd102, 0xe0010608, 0x0602f04f, 
+    0xf04fd102, 0xe00b0106, 0xf04fdd02, 0xe0010001, 0x0000f04f, 0x0000eba4, 0x0040ea4f, 0x0104f1c0, 
+    0x0301f04f, 0x1244eb09, 0x0001f1a6, 0x02c5eb02, 0x0c06eb01, 0x5c11e01e, 0xd01d2901, 0xdb102803, 
+    0xd10e2c03, 0xd10c2d03, 0x1000f819, 0xeb09b9a1, 0xf8910100, 0xf1bee028, 0xd10d0f00, 0x1050f891, 
+    0xebacb951, 0x1e490100, 0xf101fa03, 0x1e40438f, 0xb240b23f, 0xdade2800, 0xf8cd1c40, 0xfa4fb000, 
+    0xf8daf880, 0x9a023000, 0x46292000, 0xfaf1f7fb, 0xda1245b0, 0x0008eba6, 0x2000f8da, 0x01c14656, 
+    0x2008eb02, 0xfde8f01e, 0x23006831, 0x1b00e9cd, 0x46299a02, 0xf7fb4618, 0x1c64fa25, 0x2c04b264, 
+    0xb2b9db8b, 0xf01d9803, 0x1c6dfde0, 0x2d04b26d, 0xaf7bf6ff, 0x9fffe8bd, 0x4ff0e92d, 0xb0a1484d, 
+    0x28507800, 0x2020d201, 0x2010e000, 0x46802200, 0x21014849, 0xfddaf01d, 0xfb80fa4f, 0xf7fd2000, 
+    0xf8dffabb, 0x26009108, 0x240046b2, 0xd10242b4, 0x0000f04f, 0xda02e004, 0x0001f104, 0x4620e000, 
+    0xb24242b4, 0x2508d101, 0x2502e000, 0xa000f8cd, 0x3000f8d9, 0x464f2000, 0xf7fb4631, 0xa801fa9a, 
+    0xeb0046b9, 0x1e6d1044, 0x07c6eb00, 0xf8d9e00d, 0x01e90000, 0xf0132280, 0x4540f8ed, 0x2001dd01, 
+    0x2000e000, 0x1e6d5578, 0x2d00b26d, 0x1c64daef, 0x2c04b264, 0x1c76dbca, 0x2e04b276, 0xa801dbc5, 
+    0xff1cf7ff, 0xf7fda801, 0x4658fe5f, 0xfa74f7fd, 0x0400f44f, 0x11f4f240, 0xf7f54620, 0x481cfc72, 
+    0xfd70f01d, 0x46204601, 0xfc5af7f5, 0x1c804818, 0xfd68f01d, 0x46204601, 0xfc52f7f5, 0x1d004814, 
+    0xfd60f01d, 0x46204601, 0xfc4af7f5, 0x1d804810, 0xfd58f01d, 0x46204601, 0xfc42f7f5, 0x3008480e, 
+    0xfd4af01d, 0x46204601, 0xfc3af7f5, 0x3048480a, 0xfd42f01d, 0x46204601, 0xfc32f7f5, 0x46204907, 
+    0xfc2ef7f5, 0xe8bdb021, 0x00008ff0, 0x000301c4, 0xd0031000, 0x0003031e, 0xd1800000, 0xdcba01f5, 
+    0x23004831, 0xf248220f, 0xb5100100, 0xfd47f01d, 0x7801482e, 0xf7fc2040, 0x2300fdbb, 0x2201482c, 
+    0x4010e8bd, 0xf01d2102, 0x210fbd3a, 0x422bf04f, 0x2000f44f, 0xf7f5b508, 0xf7fffc62, 0x2100ffe1, 
+    0xf0004608, 0x2300f895, 0x21014822, 0xf01d461a, 0x2000fd26, 0x0200f242, 0x46014603, 0xf0009000, 
+    0xbd08f83b, 0x481a4601, 0x29043022, 0x2905d006, 0x2300d006, 0x21032200, 0xbd11f01d, 0xe7f92303, 
+    0xe7f72302, 0xf7ffb508, 0x2101ffed, 0xf0004608, 0x2301f86f, 0x2102480e, 0xf01d461a, 0x2301fd00, 
+    0x2200480c, 0xf01d4619, 0x2000fcfa, 0x7203f247, 0xf6402317, 0x90004102, 0x1084f240, 0xf80cf000, 
+    0x4008e8bd, 0xbe73f002, 0xd0035026, 0x00030223, 0xd03c8310, 0xd003529a, 0x47f0e92d, 0x460d4c8f, 
+    0x461eb281, 0x8020f8dd, 0x46204617, 0xfcbdf01d, 0x1ca5b2a9, 0xf01d4628, 0xf104fcb8, 0xb2b90a04, 
+    0xf01d4650, 0xb2b1fcb2, 0x46301da6, 0xfcadf01d, 0xfa1f1daf, 0x4638f188, 0xfca7f01d, 0x2301b672, 
+    0x91f8f8df, 0x0800f248, 0x090cf109, 0x220f4641, 0xf01d4648, 0x2300fcb4, 0x220f4641, 0xf01d4648, 
+    0xb662fcae, 0x46202100, 0xfc8ff01d, 0x46282100, 0xfc8bf01d, 0x46502100, 0xfc87f01d, 0x46302100, 
+    0xfc83f01d, 0xe8bd4638, 0x210047f0, 0xbc7df01d, 0x4c6ab570, 0x460d220a, 0x34104606, 0xf2404603, 
+    0x46204100, 0xfc8bf01d, 0x46332209, 0x2100f240, 0xf01d4620, 0x462bfc84, 0xe8bd4620, 0x22024070, 
+    0xf01d2104, 0x485ebc7c, 0x22042300, 0xb5102110, 0xfc75f01d, 0x23014c59, 0x3410220e, 0x46200399, 
+    0xfc6df01d, 0x46202301, 0x21402206, 0xfc67f01d, 0x48542301, 0x46192200, 0xfc61f01d, 0x23014c52, 
+    0x21102204, 0xf01d4620, 0x2301fc5a, 0x22024620, 0xf01d2104, 0x2301fc54, 0x22034620, 0xf01d2108, 
+    0x2300fc4e, 0x22044620, 0xf01d2110, 0x4c44fc48, 0x22002301, 0x210f348a, 0xf01d4620, 0x2300fc40, 
+    0x22044620, 0xf01d21f0, 0x2305fc3a, 0x7100f640, 0x46202208, 0xfc33f01d, 0x46202305, 0x4010e8bd, 
+    0xf24f220c, 0xf01d0100, 0xe92dbc2a, 0xf8df5ff0, 0xea5f90dc, 0x4f360a00, 0x4615461e, 0xf240460c, 
+    0xd0031b00, 0x28017838, 0xe025d00e, 0x46482300, 0x21102204, 0xfc13f01d, 0x28017838, 0x2300d14c, 
+    0x2208482c, 0xe0434659, 0x2200482a, 0x309e2101, 0xfc13f01d, 0x80a0f8df, 0xf2482801, 0xd0170700, 
+    0x23004824, 0x46592208, 0xfbf9f01d, 0x46392300, 0x4640220f, 0xfbf3f01d, 0xd0152c03, 0xd0132c05, 
+    0xd0112c04, 0xd00b2c02, 0xd0092c01, 0xe01c2300, 0x23014818, 0x46592208, 0xfbe1f01d, 0xe7e62301, 
+    0x0504f045, 0x0604f046, 0x78004814, 0x4c14b960, 0x21702204, 0x4620462b, 0xfbd1f01d, 0x46332207, 
+    0x01d14620, 0xfbcbf01d, 0x46484653, 0x21102204, 0x5ff0e8bd, 0xbbc3f01d, 0x9ff0e8bd, 0xd03c8300, 
+    0xd03c8004, 0xd03d0004, 0xd003529a, 0xd03c809e, 0x00030302, 0xd2154082, 0xd213a124, 0x000301c8, 
+    0xd03d4098, 0x41f0e92d, 0x28014cfe, 0x2800f240, 0x0500f248, 0x2100d051, 0xf01d4620, 0x2301fb86, 
+    0x0100f641, 0x4620220b, 0xfb99f01d, 0x46202301, 0x029e220a, 0xf01d4631, 0x2301fb92, 0x220e4620, 
+    0x4639039f, 0xfb8bf01d, 0x46292301, 0x4620220f, 0xfb85f01d, 0x46292300, 0x4620220f, 0xfb7ff01d, 
+    0x210011ed, 0xf7fc4628, 0x2300fbf3, 0x220a4631, 0xf01d4620, 0x2100fb74, 0xf7fc4628, 0x2300fbe9, 
+    0x220e4639, 0xf01d4620, 0x2300fb6a, 0x22044620, 0xf01d2110, 0x2300fb64, 0x22034620, 0xf01d2108, 
+    0x2100fb5e, 0xf7fc4628, 0x2300fbd3, 0x22094641, 0xe8bd4620, 0xf01d41f0, 0x2301bb52, 0x22034620, 
+    0xf01d2108, 0x2300fb4c, 0x22044620, 0xf01d2110, 0x2301fb46, 0x22094641, 0xf01d4620, 0x2301fb40, 
+    0x220f4629, 0x220be7e4, 0x48c74603, 0x0100f641, 0xbb35f01d, 0x220fb510, 0xf0004604, 0x48c20301, 
+    0x0100f248, 0xfb2bf01d, 0x220048bf, 0xf3c42101, 0xe8bd0340, 0x1c804010, 0xbb21f01d, 0x41f0e92d, 
+    0xf2404cb9, 0xf2482800, 0x3c100500, 0xd0512801, 0x46202100, 0xfaf9f01d, 0xf6412301, 0x220b0100, 
+    0xf01d4620, 0x2301fb0c, 0x220a4620, 0x4631029e, 0xfb05f01d, 0x46202301, 0x039f220e, 0xf01d4639, 
+    0x2301fafe, 0x220f4629, 0xf01d4620, 0x2300faf8, 0x220f4629, 0xf01d4620, 0x11edfaf2, 0x46282100, 
+    0xfb66f7fc, 0x46312300, 0x4620220a, 0xfae7f01d, 0x46282100, 0xfb5cf7fc, 0x46392300, 0x4620220e, 
+    0xfaddf01d, 0x46202300, 0x21102204, 0xfad7f01d, 0x46202300, 0x21082203, 0xfad1f01d, 0x46282100, 
+    0xfb46f7fc, 0x46412300, 0x46202209, 0x41f0e8bd, 0xbac5f01d, 0x46202301, 0x21082203, 0xfabff01d, 
+    0x46202300, 0x21102204, 0xfab9f01d, 0x46412301, 0x46202209, 0xfab3f01d, 0x46292301, 0xe7e4220f, 
+    0x46032209, 0xf2404880, 0xf01d6100, 0x220dbaa8, 0x487d4603, 0x0100f246, 0xbaa1f01d, 0x41f0e92d, 
+    0x28014c7a, 0x2800f240, 0x0500f248, 0x2100d051, 0xf01d4620, 0x2301fa7a, 0x0100f641, 0x4620220b, 
+    0xfa8df01d, 0x46202301, 0x029e220a, 0xf01d4631, 0x2301fa86, 0x220e4620, 0x4639039f, 0xfa7ff01d, 
+    0x46292301, 0x4620220f, 0xfa79f01d, 0x46292300, 0x4620220f, 0xfa73f01d, 0x210011ed, 0xf7fc4628, 
+    0x2300fae7, 0x220a4631, 0xf01d4620, 0x2100fa68, 0xf7fc4628, 0x2300fadd, 0x220e4639, 0xf01d4620, 
+    0x2300fa5e, 0x22044620, 0xf01d2110, 0x2300fa58, 0x22034620, 0xf01d2108, 0x2100fa52, 0xf7fc4628, 
+    0x2300fac7, 0x22094641, 0xe8bd4620, 0xf01d41f0, 0x2301ba46, 0x22034620, 0xf01d2108, 0x2300fa40, 
+    0x22044620, 0xf01d2110, 0x2301fa3a, 0x22094641, 0xf01d4620, 0x2301fa34, 0x220f4629, 0x220be7e4, 
+    0x48434603, 0x0100f641, 0xba29f01d, 0x220fb510, 0xf0004604, 0x483e0301, 0x0100f248, 0xfa1ff01d, 
+    0x2200483b, 0xf3c42101, 0xe8bd0340, 0x1c804010, 0xba15f01d, 0x41f0e92d, 0xf2404c35, 0xf2482800, 
+    0x3c100500, 0xd0512801, 0x46202100, 0xf9edf01d, 0xf6412301, 0x220b0100, 0xf01d4620, 0x2301fa00, 
+    0x220a4620, 0x4631029e, 0xf9f9f01d, 0x46202301, 0x039f220e, 0xf01d4639, 0x2301f9f2, 0x220f4629, 
+    0xf01d4620, 0x2300f9ec, 0x220f4629, 0xf01d4620, 0x11edf9e6, 0x46282100, 0xfa5af7fc, 0x46312300, 
+    0x4620220a, 0xf9dbf01d, 0x46282100, 0xfa50f7fc, 0x46392300, 0x4620220e, 0xf9d1f01d, 0x46202300, 
+    0x21102204, 0xf9cbf01d, 0x46202300, 0x21082203, 0xf9c5f01d, 0x46282100, 0xfa3af7fc, 0x46412300, 
+    0x46202209, 0x41f0e8bd, 0xb9b9f01d, 0x46202301, 0x21082203, 0xf9b3f01d, 0x46202300, 0x21102204, 
+    0x0000e008, 0xd003d800, 0xd003d010, 0xd003c800, 0xd003c010, 0xf9a3f01d, 0x46412301, 0x46202209, 
+    0xf99df01d, 0x46292301, 0xe7da220f, 0x46032209, 0xf24048ff, 0xf01d6100, 0x220db992, 0x48fc4603, 
+    0x0100f246, 0xb98bf01d, 0x43f8e92d, 0x00044df9, 0x2600f240, 0x2c04d001, 0x2300d114, 0x22094631, 
+    0xf01d4628, 0x2300f97c, 0x22074628, 0xf01d2180, 0x2000f976, 0xffe1f7ff, 0xf7ff2003, 0x2001ffd7, 
+    0xff58f7ff, 0xf2402c01, 0xf2404700, 0xd0011800, 0xd1142c04, 0x46392300, 0x4628220a, 0xf95ff01d, 
+    0x46412300, 0x46282208, 0xf959f01d, 0xf7ff2000, 0x2003ff2d, 0xff23f7ff, 0xf7ff2001, 0x4ddefeaf, 
+    0xd0012c02, 0xd1142c04, 0x46312300, 0x46282209, 0xf945f01d, 0x46282300, 0x21802207, 0xf93ff01d, 
+    0xf7ff2000, 0x2003fe94, 0xfe8af7ff, 0xf7ff2001, 0x2c03fe15, 0x2c04d001, 0x2300d11e, 0x220a4639, 
+    0xf01d4628, 0x2300f92c, 0x22084641, 0xf01d4628, 0x2000f926, 0xfdeef7ff, 0xf7ff2003, 0x2001fde4, 
+    0xfd70f7ff, 0xd1072c04, 0x90002000, 0x46032202, 0x20122101, 0xfdc8f00f, 0x83f8e8bd, 0x4cbcb570, 
+    0x22052300, 0x21603c10, 0xf01d4620, 0x2300f908, 0x22044620, 0xf01d2110, 0x2300f902, 0x22034620, 
+    0xf01d2108, 0x4cb3f8fc, 0x22052300, 0x21603408, 0xf01d4620, 0x2300f8f4, 0x22044620, 0xf01d2110, 
+    0x2300f8ee, 0x21014620, 0xf01d461a, 0x4cabf8e8, 0x22052300, 0x46202160, 0xf8e1f01d, 0x46202300, 
+    0x21102204, 0xf8dbf01d, 0x46202300, 0x21082203, 0xf8d5f01d, 0x23004ca1, 0x341a2205, 0x46202160, 
+    0xf8cdf01d, 0x46202300, 0x21102204, 0xf8c7f01d, 0x46202300, 0x461a2101, 0xf8c1f01d, 0x23004c96, 
+    0x3c122205, 0x46202160, 0xf8b9f01d, 0x46202300, 0x21102204, 0xf8b3f01d, 0x46202300, 0x21082203, 
+    0xf8adf01d, 0x23004c8c, 0x34082205, 0x46202160, 0xf8a5f01d, 0x46202300, 0x21102204, 0xf89ff01d, 
+    0x46202300, 0x461a2101, 0xf899f01d, 0x23004c84, 0x21602205, 0xf01d4620, 0x2300f892, 0x22044620, 
+    0xf01d2110, 0x2300f88c, 0x22034620, 0xf01d2108, 0x4c7bf886, 0x22052300, 0x2160341a, 0xf01d4620, 
+    0x2300f87e, 0x22044620, 0xf01d2110, 0x2300f878, 0x21014620, 0xf01d461a, 0x4870f872, 0x22052300, 
+    0x30122120, 0xf86bf01d, 0x2300486d, 0x21202205, 0xf01d3012, 0x4e69f864, 0x0400f241, 0x46212300, 
+    0x220c3610, 0xf01d4630, 0x1065f85a, 0x23004630, 0x220b4629, 0xf853f01d, 0x4c614621, 0x34102300, 
+    0x4620220c, 0xf84bf01d, 0x46204629, 0x4070e8bd, 0x220b2300, 0xb843f01d, 0x41f0e92d, 0x46164c57, 
+    0x460f2205, 0x46053410, 0x46032120, 0xf01d4620, 0x462bf836, 0x22054d52, 0x21203510, 0xf01d4628, 
+    0x2203f82e, 0x2108463b, 0xf01d4620, 0x2203f828, 0x2108463b, 0xf01d4628, 0x2202f822, 0x21044633, 
+    0xf01d4620, 0x4633f81c, 0xe8bd4628, 0x220241f0, 0xf01d2104, 0xe92db814, 0x4d3d47f0, 0x22084691, 
+    0x1fad468a, 0x01544680, 0x46214603, 0xf01d4628, 0x4e3af806, 0x46432208, 0x360a4621, 0xf01c4630, 
+    0x4f35fffe, 0x46432208, 0x3f084621, 0xf01c4638, 0x4621fff6, 0x22084c32, 0x340a4643, 0xf01c4620, 
+    0x2207ffee, 0x21804653, 0xf01c4628, 0x2207ffe8, 0x21804653, 0xf01c4630, 0x2207ffe2, 0x21804653, 
+    0xf01c4638, 0x2207ffdc, 0x21804653, 0xf01c4620, 0x2206ffd6, 0x2140464b, 0xf01c4628, 0x2206ffd0, 
+    0x2140464b, 0xf01c4630, 0x2206ffca, 0x2140464b, 0xf01c4638, 0x464bffc4, 0xe8bd4620, 0x220647f0, 
+    0xf01c2140, 0xe92dbfbc, 0x4d1141f0, 0x0440eb01, 0x46902160, 0x46233d08, 0x46282205, 0xffaff01c, 
+    0x22054e0e, 0x46232160, 0x46303608, 0xffa7f01c, 0x22054f09, 0x46232160, 0x46383f0a, 0xff9ff01c, 
+    0x4c074623, 0x21602205, 0x46203408, 0x0000e00a, 0xd003c010, 0xd003c012, 0xd003d012, 0xd003c800, 
+    0xd003d800, 0xff8bf01c, 0x46432203, 0x46282108, 0xff85f01c, 0x46432203, 0x46302108, 0xff7ff01c, 
+    0x46432203, 0x46382108, 0xff79f01c, 0x46204643, 0x41f0e8bd, 0x21082203, 0xbf71f01c, 0x47f0e92d, 
+    0x0600f244, 0x220e4692, 0x46074689, 0x46314603, 0x46204cfe, 0xff63f01c, 0x220e4dfd, 0x4631463b, 
+    0xf01c4628, 0xf8dfff5c, 0x220e83ec, 0x4631463b, 0xf01c4640, 0x4631ff54, 0x220e4ef7, 0x4630463b, 
+    0xff4df01c, 0x0700f242, 0x220d464b, 0x46204639, 0xff45f01c, 0x464b220d, 0x46284639, 0xff3ff01c, 
+    0x464b220d, 0x46404639, 0xff39f01c, 0x464b220d, 0x46304639, 0xff33f01c, 0x4653107f, 0x4639220c, 
+    0xf01c4620, 0x220cff2c, 0x46394653, 0xf01c4628, 0x220cff26, 0x46394653, 0xf01c4640, 0x4653ff20, 
+    0x46304639, 0x47f0e8bd, 0xf01c220c, 0xb570bf18, 0x23004cd6, 0x1fa42205, 0x46202160, 0xff0ff01c, 
+    0x46202300, 0x21102204, 0xff09f01c, 0x46202300, 0x21082203, 0xff03f01c, 0x23024ccc, 0x34142205, 
+    0x46202160, 0xfefbf01c, 0x46202301, 0x21102204, 0xfef5f01c, 0x46202301, 0x46192200, 0xfeeff01c, 
+    0x23004cc3, 0x1fa42205, 0x46202160, 0xfee7f01c, 0x46202300, 0x21102204, 0xfee1f01c, 0x46202300, 
+    0x21082203, 0xfedbf01c, 0x23024cb9, 0x34142205, 0x46202160, 0xfed3f01c, 0x46202301, 0x21102204, 
+    0xfecdf01c, 0x46202301, 0x46192200, 0xfec7f01c, 0x23004cb0, 0x1fa42205, 0x46202160, 0xfebff01c, 
+    0x46202300, 0x21102204, 0xfeb9f01c, 0x46202300, 0x21082203, 0xfeb3f01c, 0x23034ca6, 0x34142205, 
+    0x46202160, 0xfeabf01c, 0x46202300, 0x21102204, 0xfea5f01c, 0x46202301, 0x46192200, 0xfe9ff01c, 
+    0x23014c9d, 0x1fa42205, 0x46202160, 0xfe97f01c, 0x46202301, 0x21102204, 0xfe91f01c, 0x46202301, 
+    0x21082203, 0xfe8bf01c, 0x23024c93, 0x34142205, 0x46202160, 0xfe83f01c, 0x46202300, 0x21102204, 
+    0xfe7df01c, 0x46202301, 0x46192200, 0xfe77f01c, 0x23004887, 0x21202205, 0xf01c300c, 0x4886fe70, 
+    0x22052300, 0x300c2120, 0xfe69f01c, 0xf2414e80, 0x23000400, 0x360a4621, 0x4630220c, 0xfe5ff01c, 
+    0x46301065, 0x46292300, 0xf01c220b, 0x4621fe58, 0x23004c79, 0x220c340a, 0xf01c4620, 0x4629fe50, 
+    0xe8bd4620, 0x23004070, 0xf01c220b, 0xb510be48, 0x23004c6e, 0x1fa42205, 0x46202160, 0xfe3ff01c, 
+    0x46202300, 0x21102204, 0xfe39f01c, 0x46202300, 0x21082203, 0xfe33f01c, 0x23024c64, 0x34142205, 
+    0x46202160, 0xfe2bf01c, 0x46202301, 0x21102204, 0xfe25f01c, 0x46202301, 0x46192200, 0xfe1ff01c, 
+    0x23004c5b, 0x1fa42205, 0x46202160, 0xfe17f01c, 0x46202300, 0x21102204, 0xfe11f01c, 0x46202300, 
+    0x21082203, 0xfe0bf01c, 0x23034c51, 0x34142205, 0x46202160, 0xfe03f01c, 0x46202300, 0x21102204, 
+    0xfdfdf01c, 0x46202301, 0x46192200, 0xfdf7f01c, 0x23004c48, 0x1fa42205, 0x46202160, 0xfdeff01c, 
+    0x46202300, 0x21102204, 0xfde9f01c, 0x46202300, 0x21082203, 0xfde3f01c, 0x23024c3e, 0x34142205, 
+    0x46202160, 0xfddbf01c, 0x46202301, 0x21102204, 0xfdd5f01c, 0x46202301, 0x46192200, 0xfdcff01c, 
+    0x23004c35, 0x1fa42205, 0x46202160, 0xfdc7f01c, 0x46202300, 0x21102204, 0xfdc1f01c, 0x46202300, 
+    0x21082203, 0xfdbbf01c, 0x23034c2b, 0x34142205, 0x46202160, 0xfdb3f01c, 0x46202300, 0x21102204, 
+    0xfdadf01c, 0x46202301, 0x4010e8bd, 0x46192200, 0xbda5f01c, 0x4c1db570, 0x22052300, 0x21601fa4, 
+    0xf01c4620, 0x2300fd9c, 0x22044620, 0xf01c2110, 0x2300fd96, 0x22034620, 0xf01c2108, 0x4c13fd90, 
+    0x22052302, 0x21603414, 0xf01c4620, 0x2301fd88, 0x22044620, 0xf01c2110, 0x2301fd82, 0x22004620, 
+    0xf01c4619, 0x4c0afd7c, 0x22052301, 0x21601fa4, 0xf01c4620, 0x2301fd74, 0x22044620, 0xf01c2110, 
+    0x2301fd6e, 0x22034620, 0xe0072108, 0xd003c006, 0xd003c806, 0xd003d006, 0xd003d806, 0xfd5ff01c, 
+    0x23024cfc, 0x21602205, 0xf01c4620, 0x2300fd58, 0x22044620, 0xf01c2110, 0x2301fd52, 0x22004620, 
+    0xf01c4619, 0x4cf4fd4c, 0x22052300, 0x46202160, 0xfd45f01c, 0x46202300, 0x21102204, 0xfd3ff01c, 
+    0x46202300, 0x21082203, 0xfd39f01c, 0x23024cea, 0x341a2205, 0x46202160, 0xfd31f01c, 0x46202301, 
+    0x21102204, 0xfd2bf01c, 0x46202301, 0x46192200, 0xfd25f01c, 0x23014ce1, 0x21602205, 0xf01c4620, 
+    0x2301fd1e, 0x22044620, 0xf01c2110, 0x2301fd18, 0x22034620, 0xf01c2108, 0x4cd8fd12, 0x22052302, 
+    0x2160341a, 0xf01c4620, 0x2300fd0a, 0x22044620, 0xf01c2110, 0x2301fd04, 0x22004620, 0xf01c4619, 
+    0x48ccfcfe, 0x22052300, 0x38082120, 0xfcf7f01c, 0x230048ca, 0x21202205, 0xf01c3012, 0x4ec5fcf0, 
+    0x0400f241, 0x46212300, 0x220c3e0a, 0xf01c4630, 0x1065fce6, 0x23004630, 0x220b4629, 0xfcdff01c, 
+    0x4cbe4621, 0x34102300, 0x4620220c, 0xfcd7f01c, 0x46204629, 0x4070e8bd, 0x220b2300, 0xbccff01c, 
+    0x230048b4, 0x2205b570, 0x38082120, 0xfcc7f01c, 0x230148b2, 0x21202205, 0xf01c3012, 0x4eadfcc0, 
+    0x0400f241, 0x46212300, 0x220c3e0a, 0xf01c4630, 0x1065fcb6, 0x23004630, 0x220b4629, 0xfcaff01c, 
+    0x4ca64621, 0x34102301, 0x4620220c, 0xfca7f01c, 0x46204629, 0x4070e8bd, 0x220b2301, 0xbc9ff01c, 
+    0x2805b510, 0xd0014604, 0xd1002c04, 0x489c2104, 0x70042c03, 0x7001489b, 0x2c05d020, 0x2c04d01e, 
+    0x2c02d01c, 0xb10cd002, 0xd1752c01, 0x22012100, 0xf7ff4608, 0x2200fd13, 0x46102101, 0xfcc3f7ff, 
+    0x46112200, 0xf7ff4610, 0x2200fc66, 0x46104611, 0xfc32f7ff, 0x4010e8bd, 0xbb60f7ff, 0x2901b351, 
+    0x2902d03b, 0x2903d04b, 0x2904d057, 0x2905d063, 0x2906d07d, 0x2907d07e, 0x2908d078, 0x2200d14c, 
+    0x46104611, 0xfceaf7ff, 0x46112200, 0xf7ff4610, 0x2200fc9a, 0x46104611, 0xfc3df7ff, 0x21012200, 
+    0xf7ff4610, 0x2c04fc09, 0x2c05d07e, 0xe8bdd07c, 0xe52c4010, 0x46112200, 0xf7ff4610, 0x2200fccf, 
+    0x46112001, 0xfc7ff7ff, 0x46112201, 0xf7ff4610, 0x2201fc22, 0x46102100, 0x2100e05e, 0x46082201, 
+    0xfcbcf7ff, 0x21012200, 0xf7ff4610, 0x2200fc6c, 0x46102101, 0xfc0ff7ff, 0x21002201, 0x2200e04b, 
+    0x46102101, 0xfcaaf7ff, 0x46112200, 0xf7ff4610, 0x2200fc5a, 0xe0392101, 0x2100e05e, 0x46082201, 
+    0xfc9cf7ff, 0x21012200, 0xf7ff4610, 0x2200fc4c, 0x46082101, 0x2100e00c, 0x46082201, 0xfc8ef7ff, 
+    0x21012200, 0xf7ff4610, 0x2200fc3e, 0x46104611, 0xfbe1f7ff, 0x22012100, 0xf7ff4608, 0xf7fffbad, 
+    0xe8bdfadd, 0xe71b4010, 0xe003e001, 0x2200e018, 0xe0012101, 0x46112200, 0xf7ff2000, 0x2200fc6f, 
+    0x46104611, 0xfc1ff7ff, 0x46112200, 0xf7ff2000, 0x2200fbc2, 0x20002101, 0x4010e8bd, 0xbb8cf7ff, 
+    0x46112200, 0xe0004610, 0xf7ffe013, 0x2200fc57, 0x46104611, 0xfc07f7ff, 0x46112200, 0xf7ff4610, 
+    0x2200fbaa, 0x46102101, 0xfb76f7ff, 0x4010e8bd, 0xe8bde610, 0xe56a4010, 0x4827bd10, 0xf641220b, 
+    0x30100100, 0xf01cb510, 0xb2c0fbb8, 0x4822bd10, 0xf248220f, 0x30100100, 0xf01cb510, 0x4604fbae, 
+    0x2200481d, 0x30122101, 0xfba7f01c, 0x0040eb04, 0xbd10b2c0, 0x22094818, 0x6100f240, 0xb5103010, 
+    0xfb9bf01c, 0xbd10b2c0, 0x220d4813, 0x0100f246, 0xb5103010, 0xfb91f01c, 0xbd10b2c0, 0x220b4812, 
+    0x0100f641, 0xf01cb510, 0xb2c0fb88, 0x480ebd10, 0xf248220f, 0xb5100100, 0xfb7ff01c, 0x480a4604, 
+    0x21012200, 0xf01c1c80, 0xeb04fb78, 0xb2c00040, 0x0000bd10, 0xd003c81a, 0xd003d000, 0xd003d800, 
+    0x000302ea, 0x000302eb, 0xd003c010, 0xf2402209, 0xb5106100, 0xf01c48fe, 0xb2c0fb60, 0x48fce7e8, 
+    0xf246220d, 0xb5100100, 0xfb57f01c, 0xe7dfb2c0, 0x47f0e92d, 0x461e2801, 0x460d4614, 0xf8dfd17e, 
+    0x0247a3d0, 0x46392300, 0x0a02f10a, 0x46502209, 0xfb35f01c, 0x4800f240, 0x23004650, 0x220a4641, 
+    0xfb2df01c, 0x93acf8df, 0x22092300, 0x46484639, 0xfb25f01c, 0x46412300, 0x4648220a, 0xfb1ff01c, 
+    0x46502300, 0x21802207, 0xfb19f01c, 0x46502208, 0x01572300, 0xf01c4639, 0x2300fb12, 0x22074648, 
+    0xf01c2180, 0x2300fb0c, 0x22084639, 0xf01c4648, 0xea45fb06, 0xf44f0704, 0xb10e3800, 0xd1652e04, 
+    0xd1022d01, 0xd0202c01, 0xf7ffb3cc, 0xb148ffa8, 0xf7ff2001, 0x2100f962, 0xf7fb2004, 0x2000fb69, 
+    0xf95bf7ff, 0xff92f7ff, 0xd0092803, 0xf7ff2001, 0x2100f94d, 0xf7fb2004, 0x2003fb5b, 0xf946f7ff, 
+    0xd0382d01, 0xd0362c01, 0xf7ffe038, 0xb148ff7f, 0xf7ff2001, 0x2100f93b, 0xf7fb2004, 0x2000fb49, 
+    0xf934f7ff, 0xff7bf7ff, 0x2001b328, 0xf935f7ff, 0x20042100, 0xfb3cf7fb, 0xe01a2000, 0xe7ffe173, 
+    0xff64f7ff, 0x2001b148, 0xf920f7ff, 0x20042100, 0xfb2ef7fb, 0xf7ff2000, 0xf7fff919, 0x2803ff60, 
+    0x2001d009, 0xf919f7ff, 0x20042100, 0xfb20f7fb, 0xf7ff2003, 0x2000f912, 0xf88cf7ff, 0x2000b917, 
+    0xf912f7ff, 0x46402100, 0xfb12f7fb, 0xd0012e01, 0xd1642e04, 0xd1022d01, 0xd0202c01, 0xf7ffb3c4, 
+    0xb148ff16, 0xf7ff2001, 0x2100f861, 0xf7fb2004, 0x2000faff, 0xf85af7ff, 0xff00f7ff, 0xd0092803, 
+    0xf7ff2001, 0x2100f84c, 0xf7fb2004, 0x2003faf1, 0xf845f7ff, 0xd0372d01, 0xd0352c01, 0xf7ffe037, 
+    0xb148feed, 0xf7ff2001, 0x2100f83a, 0xf7fb2004, 0x2000fadf, 0xf833f7ff, 0xfee9f7ff, 0x2001b320, 
+    0xf834f7ff, 0x20042100, 0xfad2f7fb, 0xe0192000, 0xf7ffe7ff, 0xb148fed3, 0xf7ff2001, 0x2100f820, 
+    0xf7fb2004, 0x2000fac5, 0xf819f7ff, 0xfecff7ff, 0xd0092803, 0xf7ff2001, 0x2100f819, 0xf7fb2004, 
+    0x2003fab7, 0xf812f7ff, 0xf7fe2000, 0xb917ff97, 0xf7ff2001, 0x2100f8a9, 0xf7fb4640, 0x2e02faa9, 
+    0x2e04d001, 0x2d01d164, 0x2c01d102, 0xb3c4d020, 0xfe9af7ff, 0x2001b148, 0xff79f7fe, 0x20042100, 
+    0xfa96f7fb, 0xf7fe2000, 0xf7ffff72, 0x2803fe83, 0x2001d009, 0xff64f7fe, 0x20042100, 0xfa88f7fb, 
+    0xf7fe2003, 0x2d01ff5d, 0x2c01d037, 0xe037d035, 0xfe70f7ff, 0x2001b148, 0xff52f7fe, 0x20042100, 
+    0xfa76f7fb, 0xf7fe2000, 0xf7ffff4b, 0xb320fe6d, 0xf7fe2001, 0x2100ff4c, 0xf7fb2004, 0x2000fa69, 
+    0xe7ffe019, 0xfe56f7ff, 0x2001b148, 0xff38f7fe, 0x20042100, 0xfa5cf7fb, 0xf7fe2000, 0xf7ffff31, 
+    0x2803fe53, 0x2001d009, 0xff31f7fe, 0x20042100, 0xfa4ef7fb, 0xf7fe2003, 0x2000ff2a, 0xfeaef7fe, 
+    0x2002b917, 0xf840f7ff, 0x46402100, 0xfa40f7fb, 0xd0012e03, 0xd1642e04, 0xd1022d01, 0xd0202c01, 
+    0xf7ffb3c4, 0xb148fe14, 0xf7fe2001, 0x2100fe83, 0xf7fb2004, 0x2000fa2d, 0xfe7cf7fe, 0xfdfdf7ff, 
+    0xd0092803, 0xf7fe2001, 0x2100fe6e, 0xf7fb2004, 0x2003fa1f, 0xfe67f7fe, 0xd0372d01, 0xd0352c01, 
+    0xf7ffe037, 0xb148fdea, 0xf7fe2001, 0x2100fe5c, 0xf7fb2004, 0x2000fa0d, 0xfe55f7fe, 0xfde7f7ff, 
+    0x2001b320, 0xfe56f7fe, 0x20042100, 0xfa00f7fb, 0xe0192000, 0xf7ffe7ff, 0xb148fdd0, 0xf7fe2001, 
+    0x2100fe42, 0xf7fb2004, 0x2000f9f3, 0xfe3bf7fe, 0xfdcdf7ff, 0xd0092803, 0xf7fe2001, 0x2100fe3b, 
+    0xf7fb2004, 0x2003f9e5, 0xfe34f7fe, 0xf7fe2000, 0xb917fdb9, 0xf7fe2003, 0x2100ffd7, 0xf7fb4640, 
+    0x2d01f9d7, 0x2c01d001, 0x4803d10d, 0xe0057801, 0xd003c010, 0xd003d012, 0x000302eb, 0x780048fe, 
+    0x47f0e8bd, 0xe8bde4ac, 0xb57087f0, 0xb3984cfb, 0xd0352801, 0xd0372802, 0xd01f2803, 0x46202301, 
+    0x46192200, 0xf93bf01c, 0x3580f44f, 0x46282100, 0xf9aef7fb, 0x46202301, 0x461a2102, 0xf92ff01c, 
+    0x46282100, 0xf9a4f7fb, 0x46202301, 0x21042202, 0xf925f01c, 0x46282100, 0xf99af7fb, 0x22032301, 
+    0x46202108, 0xf91bf01c, 0x48e52300, 0x4070e8bd, 0x461a2101, 0xb913f01c, 0x22002301, 0xe7f04619, 
+    0x21022301, 0xe7ec461a, 0x22022301, 0xe7e82104, 0x4cdab570, 0x2801b390, 0x2802d034, 0x2803d036, 
+    0x0300f04f, 0x2200d036, 0x21014620, 0xf8f7f01c, 0x3580f44f, 0x46282100, 0xf96af7fb, 0x46202300, 
+    0x21022201, 0xf8ebf01c, 0x46282100, 0xf960f7fb, 0x46202300, 0x21042202, 0xf8e1f01c, 0x46282100, 
+    0xf956f7fb, 0x46202300, 0x21082203, 0xf8d7f01c, 0xe8bd4628, 0x21004070, 0xb94af7fb, 0x21012300, 
+    0xe009461a, 0x22012300, 0xe0052102, 0x22022300, 0xe0012104, 0x21082203, 0xe8bd4620, 0xf01c4070, 
+    0xb510b8be, 0x46042204, 0x46032110, 0xf01c48b5, 0x48b5f8b6, 0x21102204, 0xf01c4623, 0x48b3f8b0, 
+    0x21102204, 0xf01c4623, 0x2204f8aa, 0xe8bd4623, 0x48af4010, 0xf01c2110, 0xb510b8a2, 0x48a94604, 
+    0xf01c1d00, 0xf364f87f, 0xe8bd300f, 0x46014010, 0xf01c48a8, 0xe92db87a, 0x4ea741f0, 0x0401f000, 
+    0x0541f3c0, 0x22034623, 0x21084630, 0xf887f01c, 0x22034fa2, 0x46232108, 0xf01c4638, 0xf8dff880, 
+    0x22038280, 0x46232108, 0xf01c4640, 0x4623f878, 0x22034c9c, 0x46202108, 0xf871f01c, 0x462b2204, 
+    0x46302130, 0xf86bf01c, 0x462b2204, 0x46382130, 0xf865f01c, 0x462b2204, 0x46402130, 0xf85ff01c, 
+    0x4620462b, 0x41f0e8bd, 0x21302204, 0xb857f01c, 0x41f0e92d, 0xf2404d83, 0x22087400, 0x3508460e, 
+    0x46034607, 0x46284621, 0xf849f01c, 0x46332204, 0x46282170, 0xf843f01c, 0x46282300, 0x461a2101, 
+    0xf83df01c, 0x46282301, 0x46192200, 0xf837f01c, 0x46282300, 0x461a2101, 0xf831f01c, 0x22084d72, 
+    0x4621463b, 0x46283508, 0xf829f01c, 0x46332204, 0x46282170, 0xf823f01c, 0x46282300, 0x461a2101, 
+    0xf81df01c, 0x46282301, 0x46192200, 0xf817f01c, 0x46282300, 0x461a2101, 0xf811f01c, 0x22084d63, 
+    0x4621463b, 0x46283508, 0xf809f01c, 0x46332204, 0x46282170, 0xf803f01c, 0x46282300, 0x461a2101, 
+    0xfffdf01b, 0x46282301, 0x46192200, 0xfff7f01b, 0x46282300, 0x461a2101, 0xfff1f01b, 0x4c544621, 
+    0x463b2208, 0x46203408, 0xffe9f01b, 0x46332204, 0x46202170, 0xffe3f01b, 0x46202300, 0x461a2101, 
+    0xffddf01b, 0x46202301, 0x46192200, 0xffd7f01b, 0x46202300, 0x461a2101, 0xffd1f01b, 0xf2404841, 
+    0x230d14e0, 0x22054621, 0xf01b1e80, 0x483effc8, 0x2205230d, 0x1e804621, 0xffc1f01b, 0x230d483b, 
+    0x46212205, 0xf01b1e80, 0x4621ffba, 0xe8bd4838, 0x230d41f0, 0x1e802205, 0xbfb1f01b, 0x41f0e92d, 
+    0x48354604, 0xb3793808, 0x3d084d34, 0xd0312901, 0x3e084e33, 0xd0282902, 0x3f084f32, 0xd01e2903, 
+    0x46232201, 0xf01b2102, 0xf241ff9a, 0x21000800, 0xf7fb4640, 0x2201f80d, 0x21024623, 0xf01b4628, 
+    0x2100ff8e, 0xf7fb4640, 0x2201f803, 0x21024623, 0xf01b4630, 0x2100ff84, 0xf7fa4640, 0x2201fff9, 
+    0x21024623, 0xe00d4638, 0x2201e009, 0x21024623, 0xe0074630, 0x46232201, 0x46282102, 0x2201e002, 
+    0x21024623, 0x41f0e8bd, 0xbf69f01b, 0xb5704770, 0x00454e11, 0x46042205, 0x462b3610, 0x46302160, 
+    0xff5df01b, 0x46232204, 0x46302110, 0xff57f01b, 0x46232200, 0xe0172101, 0x000302ea, 0xd0034222, 
+    0xd00305cc, 0xd003c286, 0xd003ca86, 0xd003d286, 0xd003da86, 0xd003e28a, 0xd003c00a, 0xd003c80a, 
+    0xd003d00a, 0xd003d80a, 0xf01b4630, 0x2300ff38, 0x21602205, 0x46304efe, 0xff31f01b, 0x46302300, 
+    0x21102204, 0xff2bf01b, 0x46302300, 0x461a2101, 0xff25f01b, 0x4df7462b, 0x21602205, 0xf01b4628, 
+    0x2204ff1e, 0x21104623, 0xf01b4628, 0x2200ff18, 0x21014623, 0xf01b4628, 0x4cefff12, 0x22052300, 
+    0x46202160, 0xff0bf01b, 0x46202300, 0x21102204, 0xff05f01b, 0x46202300, 0x4070e8bd, 0x461a2101, 
+    0xbefdf01b, 0x2200b510, 0x21034604, 0x48e34603, 0xfef5f01b, 0x220048e2, 0x46232103, 0xfeeff01b, 
+    0x220048e0, 0x46232103, 0xfee9f01b, 0x46232200, 0x4010e8bd, 0x210348dc, 0xbee1f01b, 0x47f0e92d, 
+    0x4ed64dda, 0xf8df4fd6, 0x362a835c, 0x9358f8df, 0x7828372a, 0x082af108, 0x092af109, 0x7868b148, 
+    0x78a8b158, 0x0205f04f, 0x0160f04f, 0x4648b168, 0x2205e006, 0x21604630, 0x2205e002, 0x21604638, 
+    0xfecbf01b, 0x2401b118, 0x4640e002, 0x2400e7f8, 0x28017828, 0x7868d013, 0xd0142801, 0xf04f78a8, 
+    0xf04f0205, 0x28010160, 0x4648d011, 0xfeb5f01b, 0x2001b100, 0x28024420, 0x2001db0b, 0x2205e553, 
+    0x21604630, 0x2205e7f2, 0x21604638, 0x4640e7ee, 0x2000e7ec, 0xb570e547, 0x46034605, 0xf24c48af, 
+    0x220e0400, 0x30084621, 0xfe89f01b, 0x220e48ac, 0x4621462b, 0xf01b3008, 0x48aafe82, 0x462b220e, 
+    0x30084621, 0xfe7bf01b, 0x220e48a7, 0x4621462b, 0xf01b3008, 0x4ca1fe74, 0x21032300, 0x341c461a, 
+    0xf01b4620, 0x2301fe6c, 0x22004620, 0xf01b2103, 0x4c9bfe66, 0x21032300, 0x341c461a, 0xf01b4620, 
+    0x2301fe5e, 0x22004620, 0xf01b2103, 0x4c95fe58, 0x21032300, 0x341c461a, 0xf01b4620, 0x2301fe50, 
+    0x22004620, 0xf01b2103, 0x4c8ffe4a, 0x21032300, 0x341c461a, 0xf01b4620, 0x4620fe42, 0x4070e8bd, 
+    0x22002301, 0xf01b2103, 0xb510be3a, 0x46034604, 0x22004882, 0x1f802101, 0xfe31f01b, 0x22004880, 
+    0x46232101, 0xf01b1f80, 0x487efe2a, 0x21012200, 0x1f804623, 0xfe23f01b, 0x2200487b, 0x46232101, 
+    0x4010e8bd, 0xf01b1f80, 0xb510be1a, 0x46034604, 0x22014872, 0x1f802102, 0xfe11f01b, 0x22014870, 
+    0x46232102, 0xf01b1f80, 0x486efe0a, 0x21022201, 0x1f804623, 0xfe03f01b, 0x2201486b, 0x46232102, 
+    0x4010e8bd, 0xf01b1f80, 0xb510bdfa, 0x46034604, 0x22024862, 0x1f802104, 0xfdf1f01b, 0x22024860, 
+    0x46232104, 0xf01b1f80, 0x485efdea, 0x21042202, 0x1f804623, 0xfde3f01b, 0x2202485b, 0x46232104, 
+    0x4010e8bd, 0xf01b1f80, 0xb570bdda, 0x46034605, 0xf2474852, 0x220c0400, 0x388a4621, 0xfdcff01b, 
+    0x220c484f, 0x4621462b, 0xf01b388a, 0x484dfdc8, 0x462b220c, 0x388a4621, 0xfdc1f01b, 0x462b484a, 
+    0xe8bd4621, 0x220c4070, 0xf01b388a, 0xb570bdb8, 0x46052207, 0x48414603, 0x381601d4, 0xf01b4621, 
+    0x483ffdae, 0x462b2207, 0x38164621, 0xfda7f01b, 0x2207483c, 0x4621462b, 0xf01b3816, 0x483afda0, 
+    0x4621462b, 0x4070e8bd, 0x38162207, 0xbd97f01b, 0x4605b570, 0x48314603, 0x4400f641, 0x4621220a, 
+    0xf01b3816, 0x482efd8c, 0x462b220a, 0x38164621, 0xfd85f01b, 0x220a482b, 0x4621462b, 0xf01b3816, 
+    0x4829fd7e, 0x4621462b, 0x4070e8bd, 0x3816220a, 0xbd75f01b, 0x4604b510, 0x48204603, 0x21072200, 
+    0xf01b3814, 0x481efd6c, 0x21072200, 0x38144623, 0xfd65f01b, 0x2200481b, 0x46232107, 0xf01b3814, 
+    0x4819fd5e, 0x21072200, 0xe8bd4623, 0x38144010, 0xbd55f01b, 0x4604b510, 0x48104603, 0x21702204, 
+    0xf01b3814, 0x480efd4c, 0x21702204, 0x38144623, 0xfd45f01b, 0x2204480b, 0x46232170, 0xf01b3814, 
+    0x4809fd3e, 0x21702204, 0x38144623, 0x0000e010, 0xd003c81a, 0xd003d01a, 0xd003d81a, 0xd003c296, 
+    0xd003ca96, 0xd003d296, 0xd003da96, 0x00030338, 0x4010e8bd, 0xbd23f01b, 0x46032208, 0x0154b570, 
+    0x48f84605, 0xf01b4621, 0x48f7fd1a, 0x462b2208, 0xf01b4621, 0x48f5fd14, 0x462b2208, 0xf01b4621, 
+    0x462bfd0e, 0xe8bd4621, 0x48f14070, 0xf01b2208, 0xb570bd06, 0x46034605, 0xf24848ea, 0x220f0400, 
+    0x30a84621, 0xfcfbf01b, 0x220f48e7, 0x4621462b, 0xf01b30a8, 0x48e5fcf4, 0x462b220f, 0x30a84621, 
+    0xfcedf01b, 0x462b48e2, 0xe8bd4621, 0x220f4070, 0xf01b30a8, 0xb570bce4, 0x46034605, 0xf24448d9, 
+    0x220e0400, 0x30a84621, 0xfcd9f01b, 0x220e48d6, 0x4621462b, 0xf01b30a8, 0x48d4fcd2, 0x462b220e, 
+    0x30a84621, 0xfccbf01b, 0x462b48d1, 0xe8bd4621, 0x220e4070, 0xf01b30a8, 0xb510bcc2, 0x46034604, 
+    0x220448c8, 0x308c2110, 0xfcb9f01b, 0x220448c6, 0x46232110, 0xf01b308c, 0x48c4fcb2, 0x21102204, 
+    0x308c4623, 0xfcabf01b, 0x220448c1, 0x46232110, 0x4010e8bd, 0xf01b308c, 0xb570bca2, 0x46034605, 
+    0xf64048b8, 0x22096400, 0x308c4621, 0xfc97f01b, 0x220948b5, 0x4621462b, 0xf01b308c, 0x48b3fc90, 
+    0x462b2209, 0x308c4621, 0xfc89f01b, 0x462b48b0, 0xe8bd4621, 0x22094070, 0xf01b308c, 0xb510bc80, 
+    0x46034604, 0x220548a7, 0x308c2120, 0xfc77f01b, 0x220548a5, 0x46232120, 0xf01b308c, 0x48a3fc70, 
+    0x21202205, 0x308c4623, 0xfc69f01b, 0x220548a0, 0x46232120, 0x4010e8bd, 0xf01b308c, 0xb570bc60, 
+    0x22004c9c, 0x46052101, 0x46204603, 0xfc57f01b, 0x462b2201, 0x46202102, 0xfc51f01b, 0x462b2202, 
+    0x46202104, 0xfc4bf01b, 0x4620462b, 0x4070e8bd, 0x21082203, 0xbc43f01b, 0x4605b570, 0x48894603, 
+    0x14e0f240, 0x46212205, 0xf01b3008, 0x4886fc38, 0x462b2205, 0x30084621, 0xfc31f01b, 0x22054883, 
+    0x4621462b, 0xf01b3008, 0x4881fc2a, 0x4621462b, 0x4070e8bd, 0x30082205, 0xbc21f01b, 0xeb01497e, 
+    0xf01b20c0, 0x4a7cbbff, 0xeb02b289, 0xf01b20c0, 0xb570bbfc, 0xf7ff2000, 0x2400ffcf, 0x1500f240, 
+    0x46204629, 0xffeff7ff, 0xb2e41c64, 0xd3f72c04, 0xe92dbd70, 0x250147f0, 0x43a54604, 0x2200486f, 
+    0x2101462b, 0xfbfbf01b, 0xf2484e6c, 0x220f0a00, 0x1eb6462b, 0x46304651, 0xfbf1f01b, 0x0700f244, 
+    0x220e462b, 0x46304639, 0xfbe9f01b, 0x0800f242, 0x220d462b, 0x46304641, 0xfbe1f01b, 0x0900f241, 
+    0x220c462b, 0x46304649, 0xfbd9f01b, 0x2200485c, 0x462b2101, 0xfbd3f01b, 0x220f4e59, 0x4651462b, 
+    0x46301eb6, 0xfbcbf01b, 0x462b220e, 0x46304639, 0xfbc5f01b, 0x462b220d, 0x46304641, 0xfbbff01b, 
+    0x462b220c, 0x46304649, 0xfbb9f01b, 0x2200484d, 0x462b2101, 0xfbb3f01b, 0x220f4e4a, 0x4651462b, 
+    0x46301eb6, 0xfbabf01b, 0x462b220e, 0x46304639, 0xfba5f01b, 0x462b220d, 0x46304641, 0xfb9ff01b, 
+    0x462b220c, 0x46304649, 0xfb99f01b, 0x2200483e, 0x462b2101, 0xfb93f01b, 0x220f4e3b, 0x4651462b, 
+    0x46301eb6, 0xfb8bf01b, 0x462b220e, 0x46304639, 0xfb85f01b, 0x462b220d, 0x46304641, 0xfb7ff01b, 
+    0x462b220c, 0x46304649, 0xfb79f01b, 0xb2a3482b, 0x4651220f, 0xf01b1d00, 0x4829fb72, 0x220fb2a3, 
+    0x1d004651, 0xfb6bf01b, 0xb2a34826, 0x4651220f, 0xf01b1d00, 0x220ffb64, 0xb2a34651, 0xe8bd1db0, 
+    0xf01b47f0, 0xe92dbb5c, 0x4c1c41f0, 0x22044615, 0x1da4460e, 0x21104607, 0x46204603, 0xfb4ff01b, 
+    0x46332203, 0x46202108, 0xfb49f01b, 0x462b2202, 0x46202104, 0xfb43f01b, 0x22044c12, 0x463b2110, 
+    0x46201da4, 0xfb3bf01b, 0x46332203, 0x46202108, 0xfb35f01b, 0x4620462b, 0x41f0e8bd, 0x21042202, 
+    0xbb2df01b, 0xd003c208, 0xd003ca08, 0xd003d208, 0xd003da08, 0xd0034224, 0xd003c3e8, 0xd003c00a, 
+    0xd003c80a, 0xd003d00a, 0xd003d80a, 0x4c4fb570, 0x460e2201, 0x21024605, 0x46204603, 0xfb0ff01b, 
+    0x4d4b462b, 0x21022201, 0xf01b4628, 0x2200fb08, 0x21014633, 0xf01b4620, 0x4633fb02, 0xe8bd4628, 
+    0x22004070, 0xf01b2101, 0xb570bafa, 0x0400f242, 0x220d4605, 0x483f4603, 0xf01b4621, 0x483efaf0, 
+    0x462b220d, 0xf01b4621, 0x483cfaea, 0x462b220d, 0xf01b4621, 0x462bfae4, 0xe8bd4621, 0x48384070, 
+    0xf01b220d, 0xe92dbadc, 0x4c3141f0, 0x4d354e2f, 0x4f35340a, 0x2801360a, 0x220dd113, 0x48330341, 
+    0xfadbf01b, 0x48320001, 0x7840d001, 0x7800e000, 0x0100f244, 0x2801b378, 0x2802d02e, 0x2803d020, 
+    0x2300d013, 0x22034638, 0xf01b2108, 0x2300fab8, 0x22034630, 0xf01b2108, 0x2300fab2, 0x22034628, 
+    0xf01b2108, 0x2300faac, 0x4819e006, 0x220e2301, 0xf01b3810, 0x2301faa4, 0x22034620, 0xe0202108, 
+    0x23014818, 0x381a220e, 0xfa99f01b, 0x46282301, 0x21082203, 0xe00ae015, 0x2301480c, 0x3810220e, 
+    0xfa8df01b, 0x46302301, 0x21082203, 0x480ee009, 0x220e2301, 0xf01b381a, 0x2301fa82, 0x22034638, 
+    0xe8bd2108, 0xf01b41f0, 0x0000ba7a, 0xd003c810, 0xd003d810, 0xd003c292, 0xd003ca92, 0xd003d292, 
+    0xd003da92, 0xd003d01a, 0xd003c01a, 0xd28f2002, 0x00030338, 0x22032301, 0xb5102108, 0xf01b48fe, 
+    0x2000fa47, 0xfc21f7ff, 0xf7ff2000, 0x2001fc3e, 0xfc5bf7ff, 0x4010e8bd, 0xf7ff2005, 0x48f6bc76, 
+    0x22032301, 0xb5102108, 0xfa32f01b, 0xf7ff2000, 0x2000fc0c, 0xfc49f7ff, 0xf7ff2001, 0x2003fc26, 
+    0xfcc8f7ff, 0xf7ff2003, 0x2005fce5, 0xfc5df7ff, 0xf7ff2003, 0x2003fc7c, 0xfc9af7ff, 0x4010e8bd, 
+    0xf7ff2000, 0xe92dbd09, 0x460547f0, 0xf7ff2000, 0x2301fdc6, 0x220c48e1, 0x4621031c, 0xfa1ff01b, 
+    0x230148df, 0x4621220c, 0xfa19f01b, 0x230148dd, 0x4621220c, 0xfa13f01b, 0x230148db, 0x4621220c, 
+    0xfa0df01b, 0xf7ff2000, 0x2000fc95, 0xfcb2f7ff, 0x230048d1, 0x21082203, 0xf9eaf01b, 0xf7ff2000, 
+    0x2001fcf8, 0xfd17f7ff, 0xf7ff2001, 0x2000fbbe, 0xfbdbf7ff, 0xf7ff2000, 0x2104fbf8, 0xf7ff2001, 
+    0x2001fa3d, 0xfa82f7ff, 0x462849c8, 0xf7fe7809, 0x2000fd47, 0xfcc0f7ff, 0x23014cc5, 0x21402206, 
+    0xf01b4620, 0xf240f9dc, 0x46201900, 0x46492300, 0xf01b2208, 0x4cbff9d4, 0x22092300, 0x2100f240, 
+    0xf01b4620, 0x2300f9cc, 0x22084649, 0xf01b4620, 0x2300f9c6, 0x22074620, 0xf01b2180, 0x2300f9c0, 
+    0x22064620, 0xf01b2140, 0x4db3f9ba, 0x22072300, 0x46282180, 0xf9b3f01b, 0x46282301, 0x21402206, 
+    0xf9adf01b, 0x46282300, 0x21202205, 0xf9a7f01b, 0x46282300, 0x21102204, 0xf9a1f01b, 0x46282301, 
+    0x21082203, 0xf99bf01b, 0x46282300, 0x21022201, 0xf995f01b, 0x46282301, 0x46192200, 0xf98ff01b, 
+    0x23014d9b, 0x46192200, 0x46283d0e, 0xf987f01b, 0x23014f97, 0x03de220f, 0x46311ebf, 0xf01b4638, 
+    0xf8dff97e, 0x23018258, 0x46492208, 0xf01b4640, 0x2300f976, 0x22034640, 0xf01b2108, 0x2301f970, 
+    0x22054620, 0xf01b2120, 0x2301f96a, 0x22044620, 0xf01b2110, 0x2301f964, 0x22034620, 0xf01b2108, 
+    0x2301f95e, 0x22024620, 0xf01b2104, 0x2300f958, 0x220f4631, 0xf01b4638, 0x2300f952, 0x21014628, 
+    0xf01b461a, 0x2301f94c, 0x22074620, 0xf01b2180, 0x2301f946, 0x22064620, 0xf01b2140, 0x2300f940, 
+    0x22084649, 0xf01b4640, 0x2301f93a, 0x22034640, 0xf01b2108, 0xf7fff934, 0x4870fd1c, 0x5468f64a, 
+    0x30084621, 0xf911f01b, 0x4621486c, 0xf01b300a, 0xe8bdf90c, 0x486947f0, 0x300c2100, 0xb905f01b, 
+    0x47f0e92d, 0x20004604, 0xfcb9f7ff, 0xf7ff2000, 0x2000fc10, 0xfc2ff7ff, 0xf2404e58, 0x4f5815e0, 
+    0x8160f8df, 0xf8df1cb6, 0x1cbf9160, 0xf1082c04, 0xf1090802, 0xd07d0902, 0xd0fc2c05, 0x20002102, 
+    0xf8a6f7ff, 0x46292300, 0x46302205, 0xf8f7f01b, 0x46292300, 0x46382205, 0xf8f1f01b, 0x46292300, 
+    0x46402205, 0xf8ebf01b, 0x46292300, 0x46482205, 0xf8e5f01b, 0x484a2301, 0x039d220e, 0xf01b4629, 
+    0x4848f8de, 0x220e2301, 0xf01b4629, 0x4846f8d8, 0x220e2301, 0xf01b4629, 0x4844f8d2, 0x220e2301, 
+    0xf01b4629, 0x4834f8cc, 0x22032300, 0xf01b2108, 0x2000f8af, 0xfa89f7ff, 0xf7ff2000, 0x2000faa6, 
+    0xfac3f7ff, 0xf7ff2000, 0x2000fae0, 0xfafff7ff, 0xf7ff2000, 0x2000fb1d, 0xfb3cf7ff, 0xf7ff2000, 
+    0x2001fb59, 0xfb88f7ff, 0x20002104, 0xf8f6f7ff, 0xf7ff2000, 0x4825f93b, 0x46207801, 0xfc00f7fe, 
+    0x23004c25, 0x21802207, 0xf01b4620, 0x2300f898, 0x22064620, 0xf01b2140, 0x2301f892, 0x22054620, 
+    0xf01b2120, 0x2300f88c, 0x22044620, 0xf01b2110, 0xe000f886, 0x2300e07e, 0x22034620, 0xf01b2108, 
+    0x2300f87e, 0x22014620, 0xf01b2102, 0x2300f878, 0x21014620, 0xf01b461a, 0x4d0df872, 0x22062300, 
+    0x46282140, 0xf86bf01b, 0x46282208, 0x01542301, 0xf01b4621, 0xe01bf864, 0xd1800800, 0xd003c282, 
+    0xd003ca82, 0xd003d282, 0xd003da82, 0x000302d4, 0xd03c830e, 0xd03c804a, 0xd0034228, 0xd0039000, 
+    0xd003c01e, 0xd003c81e, 0xd003d01e, 0xd003d81e, 0x22092300, 0x46290065, 0x46304efe, 0xf83ff01b, 
+    0x46212300, 0x46302208, 0xf839f01b, 0x46302300, 0x21802207, 0xf833f01b, 0x46302300, 0x21402206, 
+    0xf82df01b, 0x46302300, 0x21202205, 0xf827f01b, 0x46302300, 0x21102204, 0xf821f01b, 0x46302300, 
+    0x21082203, 0xf81bf01b, 0x46302300, 0x21042202, 0xf815f01b, 0x46292301, 0x46302209, 0xf80ff01b, 
+    0x46212301, 0x46302208, 0xf809f01b, 0x47f0e8bd, 0xbbeff7ff, 0x20032102, 0xffaaf7fe, 0x4629230d, 
+    0x46302205, 0xfffbf01a, 0x4629230d, 0x46382205, 0xfff5f01a, 0x4629230d, 0x46402205, 0xffeff01a, 
+    0xe702230d, 0x2200b5f8, 0x46114604, 0xf7ff4610, 0x2c03fc8a, 0x2c04d03b, 0x2c05d039, 0x2500d037, 
+    0xd0462c02, 0xd0442c01, 0xd0712c06, 0xd0702c07, 0xd06f2c08, 0xf7ff2000, 0x2000fcf6, 0xff2df7fe, 
+    0x46112201, 0xf7ff4610, 0xb2e0fc6e, 0xfd9bf7ff, 0xf7fe2000, 0x2000ff30, 0xfcc7f7ff, 0x23042101, 
+    0x22004608, 0xfc74f7fe, 0x200e2105, 0xfd8cf00d, 0x95002300, 0x46192201, 0xf00d4618, 0x2001fc65, 
+    0xf9acf001, 0x40f8e8bd, 0xf7ff2000, 0x2001bba2, 0xfb9ff7ff, 0xf7ffb2e0, 0x2100fe83, 0xf00d200e, 
+    0x2c03fd73, 0x2006d003, 0xff05f7fe, 0x2000e0bf, 0x2001e7fa, 0xfb8df7ff, 0x22014ea7, 0x46302102, 
+    0xff9bf01a, 0x2c02b108, 0xb2e0d102, 0xfd5bf7ff, 0xf7fe2006, 0x2c02fef0, 0x0100f04f, 0x2001d01b, 
+    0xfd52f00d, 0x95002300, 0x46192201, 0xf00d4610, 0x2102fc2b, 0xf7fe2001, 0x4898fad3, 0xf242220d, 
+    0xf01a0100, 0x0001ff7a, 0xd0154895, 0xe0147841, 0xe050e044, 0x200ee073, 0xfd36f00d, 0x95002300, 
+    0x46182202, 0xf00d2101, 0x488efc0f, 0x20027801, 0xfab6f7fe, 0xe0042000, 0x20017801, 0xff9ef7fe, 
+    0xf0012001, 0x2001f94b, 0xfc4ff7ff, 0x48862300, 0x461a2101, 0xff43f01a, 0xf7fe2001, 0x2c02fe82, 
+    0x2201d006, 0x21024630, 0xff47f01a, 0xe008b118, 0x22012304, 0x2304e001, 0x21012200, 0xf7fe4608, 
+    0x2201fbe7, 0x21024630, 0xff37f01a, 0xd15e2801, 0xd15c2c01, 0x40f8e8bd, 0xbc45f7ff, 0x23042200, 
+    0x20014611, 0xfbd4f7fe, 0xf7fe2004, 0x2001fdce, 0xfab5f7ff, 0x4c67e01e, 0x22072301, 0x46202180, 
+    0xff0df01a, 0x46202301, 0x02592209, 0xff07f01a, 0x46202208, 0x01512301, 0xff01f01a, 0x46202300, 
+    0x21102204, 0xfefbf01a, 0x22002304, 0x20012101, 0xfbaef7fe, 0x40f8e8bd, 0xf0012000, 0x4c5bb8ef, 
+    0xf7ff7820, 0x2006fdcd, 0xfe55f7fe, 0x200e2100, 0xfcbaf00d, 0x78034856, 0x9500b163, 0x78222100, 
+    0xf00d2000, 0x4853fb91, 0x28037800, 0x2304d00b, 0xe7db2201, 0x462b4850, 0x95007800, 0xd1ed2801, 
+    0x21017822, 0x2304e7ec, 0x46112200, 0xbdf8e7cf, 0xf04f2109, 0xf44f422b, 0xb5102000, 0xfdeff7f2, 
+    0xf2402001, 0xf7f211f4, 0x4844fd9c, 0x20017801, 0xfd86f7f2, 0x20014942, 0xfd82f7f2, 0x23004841, 
+    0xf2402208, 0xf01a3100, 0x493ffeaa, 0x4a342000, 0x808880c8, 0x80088048, 0x493c4835, 0x483a7803, 
+    0xff2ef7fb, 0xf44f2172, 0xf7f20080, 0x4838fda2, 0xfe78f01a, 0x0120f020, 0xf01a4836, 0x4834fe76, 
+    0xf01a1c80, 0x4601fe6f, 0x1c804832, 0xfe6df01a, 0xf7fe2004, 0x2001fd7d, 0xfdc3f7fe, 0x20402100, 
+    0xfef6f7f9, 0x4010e8bd, 0xf7fe2000, 0xb570bdba, 0x23004c1d, 0x461a2101, 0xf01a4620, 0x1fa0fe70, 
+    0xfe50f01a, 0x23021ea5, 0x22004628, 0xf01a2107, 0x2302fe66, 0x22044628, 0xf01a2170, 0x2302fe60, 
+    0x7100f240, 0x46282208, 0xfe59f01a, 0xf2472302, 0x220c0100, 0xf01a4628, 0x2100fe52, 0xf01a1f20, 
+    0x2301fe34, 0x22004620, 0xf01a4619, 0x2001fe48, 0x0000e022, 0xd03c804a, 0xd28f007c, 0xd28f2002, 
+    0x00030338, 0x000302d4, 0xd00305cc, 0x00030222, 0x00030394, 0x00030214, 0x00030312, 0x0003031c, 
+    0xdcba01f5, 0xd0035022, 0x00030350, 0x00030366, 0xd003c286, 0xd003e286, 0xfd63f7fe, 0x20402100, 
+    0xfe96f7f9, 0x4070e8bd, 0xf7fe2000, 0xe92dbd5a, 0x230141f0, 0x220c48ba, 0x4621031c, 0xfe0ff01a, 
+    0x230148b8, 0x4621220c, 0xfe09f01a, 0x230148b6, 0x4621220c, 0xfe03f01a, 0x230148b4, 0x4621220c, 
+    0xfdfdf01a, 0x10a448ae, 0x46212300, 0x3024220a, 0xfdf5f01a, 0x230048ab, 0x4621220a, 0xf01a3024, 
+    0x48a9fdee, 0x220a2300, 0x30244621, 0xfde7f01a, 0x230048a6, 0x4621220a, 0xf01a3024, 0x48a0fde0, 
+    0x230000e4, 0x220d4621, 0xf01a3058, 0x489dfdd8, 0x220d2300, 0x30584621, 0xfdd1f01a, 0x2300489a, 
+    0x4621220d, 0xf01a3058, 0x4898fdca, 0x220d2300, 0x30584621, 0xfdc3f01a, 0x23014c91, 0x46192200, 
+    0x4620345c, 0xfdbbf01a, 0x23014d8e, 0x46192200, 0x4628355c, 0xfdb3f01a, 0x23014e8b, 0x46192200, 
+    0x4630365c, 0xfdabf01a, 0x23014f88, 0x46192200, 0x4638375c, 0xfda3f01a, 0x46202300, 0x21202205, 
+    0xfd9df01a, 0x46282300, 0x21202205, 0xfd97f01a, 0x46302300, 0x21202205, 0xfd91f01a, 0x46382300, 
+    0x21202205, 0xfd8bf01a, 0x21072300, 0x1ca0461a, 0xfd85f01a, 0x21072300, 0x1ca8461a, 0xfd7ff01a, 
+    0x21072300, 0x1cb0461a, 0xfd79f01a, 0x21072300, 0x1cb8461a, 0x41f0e8bd, 0xbd71f01a, 0x486cb538, 
+    0x31b5f64b, 0xfd51f01a, 0x486a2301, 0x0399220e, 0xfd65f01a, 0x23014866, 0x46192200, 0xf01a386e, 
+    0x231ffd5e, 0x22054864, 0x4621015c, 0xfd57f01a, 0x231f4862, 0x46212205, 0xfd51f01a, 0x231f4860, 
+    0x46212205, 0xfd4bf01a, 0x231f485e, 0x46212205, 0xfd45f01a, 0x23042200, 0x20014611, 0xf9f8f7fe, 
+    0xfe76f7ff, 0xf647200f, 0xf2470395, 0xf6400202, 0x90000102, 0x1045f243, 0xf84ef7fd, 0x21004852, 
+    0xfd13f01a, 0x23004846, 0x21042202, 0xf01a3032, 0x4844fd26, 0x22022300, 0x30322104, 0xfd1ff01a, 
+    0x23004841, 0x21042202, 0xf01a3032, 0x483ffd18, 0x22022300, 0x30322104, 0xfd11f01a, 0x49444843, 
+    0x78097800, 0xf86cf7fe, 0xf7fe2000, 0x2101fda0, 0xf7ff4608, 0x4832f9eb, 0x7400f240, 0x46212302, 
+    0x30622208, 0xfcfbf01a, 0x2302482e, 0x46212208, 0xf01a3062, 0x482cfcf4, 0x22082302, 0x30624621, 
+    0xfcedf01a, 0x23024829, 0x46212208, 0xf01a3062, 0x4829fce6, 0x230510a4, 0x22064621, 0xf01a1e80, 
+    0x4826fcde, 0x22062305, 0x1e804621, 0xfcd7f01a, 0x23054823, 0x46212206, 0xf01a1e80, 0x4821fcd0, 
+    0x22062305, 0x1e804621, 0xfcc9f01a, 0xf641481a, 0x23010400, 0x220b4621, 0xf01a381e, 0x4817fcc0, 
+    0x220b2301, 0x381e4621, 0xfcb9f01a, 0x23014814, 0x4621220b, 0xf01a381e, 0x4812fcb2, 0x220b2301, 
+    0x381e4621, 0xfcabf01a, 0xf7ff2003, 0x2001fcbb, 0xf8c8f00b, 0xf7ff2000, 0xe8bdfcb5, 0xe6864038, 
+    0xd003c22a, 0xd003ca2a, 0xd003d22a, 0xd003da2a, 0xd03c80b8, 0xd03c830c, 0xd003c01e, 0xd003c81e, 
+    0xd003d01e, 0xd003d81e, 0xd0034224, 0x00030222, 0x000302d4, 0x41f0e92d, 0x461d4c84, 0x4616b283, 
+    0x460f2206, 0x462021c0, 0xfc79f01a, 0x4620b2bb, 0x21302204, 0xfc73f01a, 0x4620b2b3, 0x210c2202, 
+    0xfc6df01a, 0x4620b2ab, 0x41f0e8bd, 0x21032200, 0xbc65f01a, 0x41f0e92d, 0x46142301, 0x4607460e, 
+    0x21024873, 0xf01a461a, 0x2100fc5a, 0x0000f241, 0xfccef7f9, 0x23014d6f, 0x0299220a, 0xf01a4628, 
+    0x2204fc4e, 0xf240463b, 0x462811f0, 0xfc47f01a, 0x46332201, 0x46282102, 0xfc41f01a, 0xf6401d2f, 
+    0xf24c0100, 0xb1340600, 0xd0062c01, 0xd0042c02, 0xd0092c03, 0x2300e013, 0x2301e000, 0x220b4628, 
+    0xfc2df01a, 0xe0052300, 0x46282300, 0xf01a220b, 0x2301fc26, 0x220e4631, 0xf01a4638, 0x4628fc20, 
+    0x41f0e8bd, 0x22022301, 0xf01a2104, 0x4851bc18, 0xb5102100, 0xf01a3016, 0x484efbf8, 0x30182100, 
+    0xfbf3f01a, 0x2100484b, 0xf01a3012, 0x4849fbee, 0x30142100, 0xfbe9f01a, 0x21004846, 0xf01a301a, 
+    0x4844fbe4, 0xe8bd2100, 0x301c4010, 0xbbddf01a, 0x47f0e92d, 0x46984d3f, 0x460e4614, 0x46073544, 
+    0x46032200, 0x46282101, 0x9a08e9dd, 0xfbe7f01a, 0x463b2201, 0x46282102, 0xfbe1f01a, 0x46332202, 
+    0x46282104, 0xfbdbf01a, 0x46281e64, 0x2204b2a3, 0xf01a2170, 0x1cacfbd4, 0x22084643, 0x7100f643, 
+    0xf01a4620, 0x2303fbcc, 0x46191ca6, 0x46302200, 0xfbc5f01a, 0x46302302, 0x461a210c, 0xfbbff01a, 
+    0x46302301, 0x21302204, 0xfbb9f01a, 0x46302300, 0x21c02206, 0xfbb3f01a, 0x464b2208, 0x7100f640, 
+    0xf01a4628, 0x2200fbac, 0x217f4653, 0xf01a4620, 0x2301fba6, 0x22034628, 0xf01a2108, 0x4628fba0, 
+    0x47f0e8bd, 0x22032300, 0xf01a2108, 0xb570bb98, 0x460d4c10, 0x46014616, 0x46203444, 0xfb75f01a, 
+    0x46291ca0, 0xfb71f01a, 0x46311d20, 0xfb6df01a, 0x46202301, 0x21082203, 0xfb81f01a, 0xe8bd4620, 
+    0x23004070, 0x21082203, 0xbb79f01a, 0xd0030484, 0xd03c8310, 0xd0036100, 0x2801b158, 0x2802d00f, 
+    0x2803d013, 0x2301d117, 0x21024872, 0xf01a461a, 0x4870bb66, 0x21022301, 0x3860461a, 0x486de7f7, 
+    0x21022301, 0x3840461a, 0x486ae7f1, 0x21022301, 0x3820461a, 0x4770e7eb, 0x4866b281, 0xf01a38e0, 
+    0xb510bb34, 0x23014c63, 0x46192200, 0x46203ce0, 0xfb45f01a, 0x46202301, 0x461a2102, 0xfb3ff01a, 
+    0x46202301, 0x21042202, 0xfb39f01a, 0x46202301, 0xe8bd2203, 0x21084010, 0xbb31f01a, 0x4855b283, 
+    0x21c02206, 0xf01a38de, 0xb158bb2a, 0xd00f2801, 0xd0132802, 0xd1172803, 0x484e2301, 0x46192200, 
+    0xbb1df01a, 0x2301484b, 0x46192200, 0xe7f73860, 0x23014848, 0x46192200, 0xe7f13840, 0x23014845, 
+    0x46192200, 0xe7eb3820, 0xb5704770, 0x36fff240, 0x1c754614, 0x2801b1a8, 0x2802d019, 0x2803d01d, 
+    0xb28bd121, 0x4e3b4631, 0x360e2200, 0xf01a4630, 0xb2a3faf6, 0x46304629, 0x4070e8bd, 0xf01a220a, 
+    0xb28bbaee, 0x4e334631, 0x3e522200, 0xb28be7ee, 0x4e304631, 0x3e322200, 0xb28be7e8, 0x4e2d4631, 
+    0x3e122200, 0xbd70e7e2, 0x482ab283, 0x21032200, 0xf01a3880, 0xb283bad4, 0xb5104826, 0x460c2200, 
+    0xf64738d8, 0xf01a71ff, 0x4822faca, 0xe8bdb2a1, 0x38d64010, 0xbaa9f01a, 0x4d1eb570, 0x220f2301, 
+    0x3de003dc, 0x46284621, 0xfab9f01a, 0x46284621, 0x4070e8bd, 0x220f2300, 0xbab1f01a, 0x41f0e92d, 
+    0x4603461f, 0x46144813, 0x22099e06, 0x460d387c, 0x2100f240, 0xfaa3f01a, 0x2207480e, 0x462b2180, 
+    0xf01a385e, 0x480bfa9c, 0x21802207, 0x383e4623, 0xfa95f01a, 0x22074807, 0x463b2180, 0xf01a381e, 
+    0x4633fa8e, 0xe8bd4803, 0x220741f0, 0x1c802180, 0xba85f01a, 0xd00308e0, 0x2100b51c, 0x91019100, 
+    0x1010f82d, 0x1000f8bd, 0xf01a48f8, 0x48f7fa5e, 0x1002f8bd, 0xf01a3020, 0x48f4fa58, 0x1004f8bd, 
+    0xf01a3040, 0x48f1fa52, 0x1006f8bd, 0xf01a3060, 0xbd1cfa4c, 0x220448ee, 0x4cecb510, 0xf9902130, 
+    0x3c740000, 0x4620b283, 0xfa59f01a, 0x46202304, 0x210f2200, 0xfa53f01a, 0x46202301, 0x21402206, 
+    0xfa4df01a, 0xf01a1ca0, 0x4604fa2d, 0x387048df, 0xfa28f01a, 0x4000eb04, 0xbd101040, 0xb50848dd, 
+    0xf2447801, 0xf7f90000, 0x48d8fab3, 0x01c9f640, 0xf01a387e, 0x48d5fa1a, 0x1101f241, 0xf01a387c, 
+    0x2000fa14, 0xff01f7ff, 0xf7ff2001, 0x2002fefe, 0xfefbf7ff, 0xf7ff2003, 0x48ccfef8, 0x22062301, 
+    0xf01a2140, 0x48c9fa1c, 0x22062301, 0x30202140, 0xfa15f01a, 0x230148c5, 0x21402206, 0xf01a3040, 
+    0x48c2fa0e, 0x22062301, 0x30602140, 0xfa07f01a, 0x90002001, 0x46024603, 0xf7ff4601, 0xbd08ff4f, 
+    0xf44fb570, 0xf6403400, 0x46200102, 0xf8d9f7f2, 0x1d0048b6, 0xf9d6f01a, 0x48b44605, 0xf01a1c80, 
+    0xeb05f9d1, 0x46204100, 0xf8baf7f2, 0x302448af, 0xf9c8f01a, 0x48ad4605, 0xf01a3022, 0xeb05f9c3, 
+    0x46204100, 0xf8acf7f2, 0x304448a8, 0xf9baf01a, 0x48a64605, 0xf01a3042, 0xeb05f9b5, 0x46204100, 
+    0xf89ef7f2, 0x306448a1, 0xf9acf01a, 0x489f4605, 0xf01a3062, 0xeb05f9a7, 0x46204100, 0xf890f7f2, 
+    0x4070e8bd, 0xf7ff20f0, 0x2804be67, 0x2201d010, 0xf0824082, 0xb200000f, 0xd00b2901, 0x1000ea40, 
+    0xb283b200, 0x22004891, 0x388221ff, 0xb9a7f01a, 0xe7f620ff, 0xeb012102, 0xf0401000, 0xe7ef000f, 
+    0xf44fb570, 0xf6403400, 0x46200102, 0xf879f7f2, 0x1d004886, 0xf976f01a, 0x48844605, 0xf01a1c80, 
+    0xeb05f971, 0x46204100, 0xf85af7f2, 0x3024487f, 0xf968f01a, 0x487d4605, 0xf01a3022, 0xeb05f963, 
+    0x46204100, 0xf84cf7f2, 0x30444878, 0xf95af01a, 0x48764605, 0xf01a3042, 0xeb05f955, 0x46204100, 
+    0xf83ef7f2, 0x30644871, 0xf94cf01a, 0x486f4605, 0xf01a3062, 0xeb05f947, 0x46204100, 0xf830f7f2, 
+    0x2100486b, 0x0000f990, 0x4070e8bd, 0xe92de79d, 0x460c47f0, 0x220f4965, 0x1940eb01, 0xeb014966, 
+    0x200128c0, 0x75e4eb00, 0x03c14603, 0x3880485f, 0xf945f01a, 0x46482206, 0xf01a2140, 0xb246f94e, 
+    0xf01a4640, 0x2c00f91f, 0xda004607, 0x485b4264, 0xf990b224, 0x28040000, 0x2805d002, 0xe003d002, 
+    0xe00000a0, 0xb2040060, 0x2204462b, 0x21104640, 0xf925f01a, 0xe0052500, 0x46482111, 0xf905f01a, 
+    0xb22d1c6d, 0xdbf742a5, 0x4648b2b3, 0x21402206, 0xf915f01a, 0x46404639, 0x47f0e8bd, 0xb8f5f01a, 
+    0x4d42b570, 0x1cac3d7e, 0x2801b120, 0x2802d00a, 0xe02ad10f, 0x46282306, 0x21f02204, 0xf8fff01a, 
+    0xe0012303, 0xe0212307, 0x46202204, 0xf01a2170, 0x2305f8f6, 0x22044628, 0xf01a21f0, 0x2302f8f0, 
+    0x22044620, 0xf01a2170, 0x2305f8ea, 0x0100f24f, 0x4628220c, 0xf8e3f01a, 0xf2474620, 0xe8bd0100, 
+    0x23024070, 0xf01a220c, 0x2308b8da, 0x22044628, 0xf01a21f0, 0x2302f8d4, 0x4601e7d6, 0xb5704823, 
+    0xf242387e, 0x1c854424, 0x3613f241, 0xf2472908, 0xd22b4287, 0xf001e8df, 0x160a0704, 0x1f181610, 
+    0x2163f245, 0xf247e00a, 0xe0014185, 0x7187f247, 0xf89bf01a, 0xe0144631, 0x418cf240, 0xf895f01a, 
+    0xe00e4621, 0xe7f34611, 0x61a7f249, 0xf88df01a, 0x2102f240, 0xf64be005, 0xf01a01c9, 0xf240f886, 
+    0x46281101, 0x4070e8bd, 0xb87ff01a, 0xb570bd70, 0x22004c06, 0x4605210f, 0x46203c7e, 0xf89df01a, 
+    0xb2401b40, 0xdd0b280f, 0xe00c200f, 0xd0030882, 0x00030227, 0x00030223, 0xd003c28c, 0x00030222, 
+    0xda002800, 0xb2832000, 0xe8bd4620, 0x22004070, 0xf01a210f, 0xb430b874, 0xb1419902, 0x2408f245, 
+    0x1aa42100, 0xda094199, 0x0409f06f, 0x2b00e02d, 0x2401da01, 0xf04fe029, 0xe02634ff, 0x0100f244, 
+    0xf1731a51, 0xdb020100, 0x0403f06f, 0xf242e01d, 0x1a510100, 0x0100f173, 0x0401f06f, 0x2b00da15, 
+    0x0324da13, 0x1aa41361, 0xdb044199, 0x13a14c6b, 0x41991aa4, 0x2402da01, 0x4c69e007, 0x1aa213e1, 
+    0xda014199, 0xe0002404, 0xf64f240a, 0xb1500100, 0xd00d2801, 0xf04fb2a3, 0x2802020b, 0x4861d00d, 
+    0xf01abc30, 0x485fb82c, 0xb2a3220b, 0xe7f73860, 0x220b485c, 0x3840b2a3, 0x485ae7f2, 0xe7ef3820, 
+    0xf2444858, 0xb510310f, 0xf01938d8, 0x4855fffe, 0x22082307, 0x7100f640, 0xf01a38ea, 0x4851f810, 
+    0x22002301, 0x386e4619, 0xf809f01a, 0x2301484d, 0x46192200, 0xf01a384e, 0x484af802, 0x22002301, 
+    0x382e4619, 0xfffbf019, 0x23014846, 0x46192200, 0x4010e8bd, 0xf019380e, 0xb570bff2, 0xf6404605, 
+    0xf44f0103, 0xf7f13000, 0xf7fffecc, 0x4c3efc9a, 0x46082100, 0x2000f994, 0xf96cf7fb, 0xfd7af7ff, 
+    0x7025b201, 0x46101402, 0xfd05f7ff, 0x0000f994, 0xfc62f7ff, 0x0000f994, 0xfca7f7ff, 0x0000f994, 
+    0xfcf2f7ff, 0x20012100, 0xfbbbf7fb, 0x2000f994, 0x200c2100, 0xf908f7fb, 0xf9942101, 0x46082000, 
+    0xf948f7fb, 0x4070e8bd, 0xe92de61a, 0x46824ff8, 0x909cf8df, 0x46e8a025, 0x462a2500, 0x90006800, 
+    0x1000f999, 0x0001eb0d, 0xf81021ff, 0x481d3c03, 0xf0193888, 0x2704ffa4, 0xf1ba2610, 0xd0230f00, 
+    0xf7ff2400, 0x4138fd37, 0xb2e41c64, 0x440542b4, 0xf44fd3f7, 0x46293080, 0xfe62f7f1, 0x2000f999, 
+    0xeb081228, 0x22000102, 0x1c03f811, 0x49114348, 0xf1c17809, 0x41080117, 0x31fff240, 0x0309f3c0, 
+    0x38864808, 0xff7bf019, 0x22024806, 0x46532104, 0xf019388e, 0xe8bdff74, 0x00008ff8, 0xffffc000, 
+    0xffffadf8, 0xd00308ee, 0x00030227, 0x00b6b1b6, 0x00030222, 0x00030223, 0x4cbab510, 0x4620b281, 
+    0xff43f019, 0x46202100, 0xff3ff019, 0xf64f4cb5, 0x3c1071ff, 0xf0194620, 0x4620ff38, 0x4010e8bd, 
+    0xf0192100, 0xf04fbf32, 0xb51030ff, 0xffe4f7ff, 0xf01948ad, 0xe8bdff21, 0x20044010, 0xb867f7f9, 
+    0x9c02b510, 0x70427001, 0x70c47083, 0xe92dbd10, 0x250f41fc, 0x260b2400, 0x220002ef, 0xe9cd463b, 
+    0x46116500, 0xf7f8b2e0, 0x1c64f818, 0xdbf42c04, 0x81fce8bd, 0x41fce92d, 0xf6472400, 0x260b0700, 
+    0x22004625, 0x4611463b, 0x6500e9cd, 0xf7f8b2e0, 0x1c64f804, 0xdbf42c04, 0xb570e7ea, 0x46052400, 
+    0x21012200, 0xf7f7b2e0, 0xf825ffe6, 0x1c640014, 0xdbf52c04, 0xb570bd70, 0x46052400, 0x060ef06f, 
+    0x21002202, 0xf7f7b2e0, 0xf01bffd6, 0x4632ff72, 0xfdfdf01c, 0x03c4eb05, 0x2c041c64, 0x0100e9c3, 
+    0xbd70dbee, 0x46082101, 0xf7f7b510, 0x2101ff23, 0xf7f74608, 0xf010ff1f, 0xd0000020, 0xbd102001, 
+    0x220d487a, 0x0100f242, 0xf019b510, 0x2800fee6, 0x2001d000, 0xe92dbd10, 0xf24441f0, 0x460c0600, 
+    0x4607220e, 0x48724603, 0xf0194631, 0x4871fec8, 0xf0192100, 0x486efeaa, 0x38504d6d, 0x2c023d44, 
+    0x2c01d00e, 0x2300d013, 0x21012200, 0xfeb7f019, 0x4631463b, 0xe8bd4628, 0x220e41f0, 0xbeaff019, 
+    0x463b2200, 0xf0192101, 0x2300feaa, 0x463be7f1, 0xe92de7ea, 0x4c5e41f0, 0x4615461f, 0x3422460e, 
+    0x22004603, 0x21034620, 0xfe99f019, 0x46332202, 0x4620210c, 0xfe93f019, 0x462b2204, 0x46202130, 
+    0xfe8df019, 0x463b2206, 0x462021c0, 0xfe87f019, 0xe8bd4620, 0x220841f0, 0x01512301, 0xbe7ff019, 
+    0x4d4bb570, 0x21032200, 0x46283522, 0xfe85f019, 0x46042202, 0x4628210c, 0xfe7ff019, 0x0480ea44, 
+    0x22044628, 0xf0192130, 0xea44fe78, 0x46281400, 0x21c02206, 0xfe71f019, 0x1080ea44, 0xbd70b280, 
+    0x460db570, 0x483c4604, 0xf0194611, 0x483afe3e, 0x1e804629, 0xfe39f019, 0x46214837, 0x4070e8bd, 
+    0xf0191f00, 0xb5f0be32, 0x5408e9dd, 0x7606e9dd, 0xc014f8dd, 0xf040b109, 0xb10a0002, 0x0001f040, 
+    0xf040b10b, 0xf1bc0008, 0xd0010f00, 0x0004f040, 0xf040b10f, 0xb10d0010, 0x0020f040, 0xf040b10e, 
+    0x2c000040, 0xf040d001, 0xbdf00080, 0x20004601, 0xb5102901, 0x2903d00c, 0x4820d115, 0x213c2202, 
+    0xfe2bf019, 0x2807b2c0, 0x2808d00e, 0xe00dd10a, 0x2202481b, 0xf019213c, 0xb2c0fe20, 0xd0032806, 
+    0xd0032807, 0xbd102003, 0xbd102004, 0xbd102005, 0x46032200, 0x21074813, 0xbe01f019, 0x4c0db570, 
+    0x220a230c, 0x34744605, 0x4100f643, 0xf0194620, 0x462bfdf6, 0xe8bd4620, 0x220e4070, 0x0100f244, 
+    0xbdedf019, 0xd003902a, 0xc1000144, 0xd28fffd4, 0xd28f2050, 0xd28f2182, 0xd28e0030, 0xd0060000, 
+    0xd0020000, 0xd0070000, 0x220c2301, 0x0319b570, 0x46204cfe, 0xfdd3f019, 0x46202301, 0x21402206, 
+    0xfdcdf019, 0x46202300, 0x21202205, 0xfdc7f019, 0x46202300, 0x21102204, 0xfdc1f019, 0x46202301, 
+    0x21802207, 0xfdbbf019, 0x780949f1, 0xd1052901, 0x46202300, 0x21042202, 0xfdb1f019, 0xf2442300, 
+    0x220e0100, 0xf0194620, 0x4ce8fdaa, 0x220a2300, 0x4100f240, 0x46203c10, 0xfda1f019, 0x46202208, 
+    0x01512300, 0xfd9bf019, 0xf2404de0, 0x230014c0, 0x1dad4621, 0x46282206, 0xfd91f019, 0x46282306, 
+    0x21382203, 0xfd8bf019, 0x46282306, 0x21072200, 0xfd85f019, 0x46212306, 0x461a1cad, 0xf0194628, 
+    0x1faefd7e, 0x46302302, 0x21072200, 0xfd77f019, 0x46282300, 0x461a2107, 0xfd71f019, 0x46212306, 
+    0x4630461a, 0xfd6bf019, 0x4cc84621, 0x3c0c2306, 0x4620461a, 0xfd63f019, 0xe8bd4620, 0x23064070, 
+    0x21072200, 0xbd5bf019, 0x43f8e92d, 0x9304f8df, 0x49c12500, 0x27012602, 0x0803f04f, 0x0000f899, 
+    0x7080f440, 0x0000f8a9, 0x1000f991, 0x2902b109, 0x49bad103, 0x29017809, 0xf3c0d038, 0x91001181, 
+    0x0103f000, 0x1301f3c0, 0x0281f3c0, 0xf7ff48b4, 0xf365fdf7, 0xf3670407, 0xf366240f, 0xf3684417, 
+    0xf899641f, 0xb0010000, 0xf3c00782, 0x0f520381, 0xf102fa04, 0x005b1222, 0xf3c0409a, 0x43111301, 
+    0x005b1422, 0x1081f3c0, 0x4311409a, 0x00401622, 0x43f0e8bd, 0x43114082, 0x0003f001, 0x1381f3c1, 
+    0x1201f3c1, 0x0181f3c1, 0xbe63f7ff, 0x0103f000, 0xf3c09100, 0xf3c00381, 0xf3c01201, 0x48981181, 
+    0xfdbef7ff, 0x0407f368, 0x240ff366, 0x4417f367, 0x641ff365, 0xb538e7c5, 0xd0042801, 0xb1282403, 
+    0x8800488c, 0xf7ffb138, 0xe023ff8f, 0x94002302, 0x21002201, 0x4889e01b, 0x28017800, 0x4886d105, 
+    0x0000f990, 0x2802b140, 0x2303d006, 0x21012202, 0xf7ff2000, 0xe7e9fe2e, 0x22012300, 0x20032102, 
+    0xfe27f7ff, 0x90002000, 0x22022301, 0x487c2103, 0xfd86f7ff, 0x4c7a487b, 0x1000f990, 0x70015c61, 
+    0x3003f994, 0x2002f994, 0x1001f994, 0x0000f994, 0xf830f7ff, 0x3003f994, 0x2002f994, 0x1001f994, 
+    0x0000f994, 0xfc24f7fa, 0x3003f994, 0x2002f994, 0x1001f994, 0x0000f994, 0xfddcf7fb, 0x3003f994, 
+    0x2002f994, 0x1001f994, 0x0000f994, 0xfe37f00d, 0xfe16f7ff, 0x4038e8bd, 0x48634601, 0xbc75f019, 
+    0x5ff0e92d, 0xf64b4860, 0x30a631b8, 0xfc6df019, 0x23014c5e, 0x0399220e, 0xf0194620, 0x4d5cfc80, 
+    0x22022300, 0x46282104, 0xfc79f019, 0xf2414859, 0x88020600, 0x7facf5b2, 0xf5b2d008, 0xd0057fa4, 
+    0x7fb4f5b2, 0xf5b2d002, 0xd1057fbc, 0x46312300, 0x4628220c, 0xfc63f019, 0xb130f8df, 0x22022301, 
+    0x0b60f10b, 0x46582104, 0xfc59f019, 0x23014f48, 0x3f20220f, 0x463803d9, 0xfc51f019, 0x46312301, 
+    0x4638220c, 0xfc4bf019, 0x46382300, 0x21402206, 0xfc45f019, 0x46382300, 0x21202205, 0xfc3ff019, 
+    0x2300483d, 0x21402206, 0xfc39f019, 0x1a00f240, 0x23014628, 0x22084651, 0xfc31f019, 0x46282301, 
+    0x21802207, 0xfc2bf019, 0x46282301, 0x21402206, 0xfc25f019, 0x46282301, 0x21202205, 0xfc1ff019, 
+    0x4500f240, 0x2300482d, 0x220a4629, 0xfc17f019, 0x90acf8df, 0x0800f640, 0x46412301, 0x4648220b, 
+    0xfc0df019, 0xf7ff2002, 0x4818ff16, 0x22072300, 0x382c2180, 0xfc03f019, 0x78014822, 0xf7ff2001, 
+    0x4f1ffd2a, 0x22082301, 0x3f1c4651, 0xf0194638, 0x2301fbf6, 0x22054638, 0xf0192120, 0x2301fbf0, 
+    0x22044638, 0xf0192110, 0x4811fbea, 0x30382100, 0xfbcbf019, 0x46202301, 0x46192200, 0xfbdff019, 
+    0x46312301, 0x4620220c, 0x0000e01e, 0xd003902c, 0x00030302, 0x00030250, 0x000301c8, 0x000302a4, 
+    0x00030338, 0x00030227, 0xd03c8012, 0xd28f0000, 0xd28e0040, 0x00030318, 0xd003507c, 0xd28fffc0, 
+    0xd28f2050, 0x000302e4, 0xfbb9f019, 0x46202301, 0x0359220d, 0xfbb3f019, 0x46512300, 0x46582208, 
+    0xfbadf019, 0xf24048f8, 0xf01911d4, 0x48f6fb8e, 0x1129f240, 0xf0191c80, 0x2301fb88, 0x220b4641, 
+    0xf0194658, 0x2300fb9c, 0x220a4629, 0xf0194658, 0xf10bfb96, 0x46410404, 0x46202301, 0xf019220b, 
+    0x2301fb8e, 0x220a4629, 0xf0194620, 0x2301fb88, 0x21024620, 0xf019461a, 0x2301fb82, 0x22004620, 
+    0xf0194619, 0x2300fb7c, 0x22044648, 0xf0192130, 0xe8bdfb76, 0x23015ff0, 0x220048dc, 0xf0194619, 
+    0x4adbbb6e, 0x2005210a, 0xf7f1b510, 0x2004fa98, 0xfb87f7f8, 0xf7f82002, 0x2002fb84, 0xfdaef00a, 
+    0x200249d4, 0x22002301, 0x210f7008, 0xf01948d2, 0x2101fb56, 0x46082200, 0xf986f009, 0x230f48cb, 
+    0x46192200, 0xf019385a, 0x48c7fb4a, 0x21042202, 0xf0193828, 0x2801fb52, 0x2000d118, 0xfc42f7fd, 
+    0x23004cc2, 0xf240220a, 0x3c324100, 0xf0194620, 0x2300fb36, 0x2100f240, 0x46202209, 0xfb2ff019, 
+    0x46202208, 0x01512301, 0xfb29f019, 0x780048bb, 0x2003b910, 0xfcd8f7f3, 0x48b92301, 0x03d9220f, 
+    0xfb1df019, 0x210048b1, 0x4010e8bd, 0xf0193848, 0xe92dbafc, 0x4aae41f0, 0x2005210b, 0xfa3ff7f1, 
+    0xf7f82004, 0x2002fb2e, 0xfb2bf7f8, 0xf00a2001, 0x49a8fd55, 0x22002001, 0x70084603, 0x48a6210f, 
+    0xfafdf019, 0xf2414da1, 0x23000400, 0x3d504621, 0x4628220c, 0xfaf3f019, 0x1eae2303, 0x22004619, 
+    0xf0194630, 0x2301faec, 0x22024630, 0xf0192104, 0x2301fae6, 0x220f4630, 0x463903df, 0xfadff019, 
+    0x46212301, 0x4628220c, 0xfad9f019, 0x46212300, 0x4628220c, 0xfad3f019, 0x46392300, 0x4630220f, 
+    0xfacdf019, 0x46302300, 0x461a2103, 0xfac7f019, 0x46302300, 0x21042202, 0xfac1f019, 0x22002101, 
+    0xf0094608, 0x4887f8f1, 0x00a1220e, 0xfac5f019, 0xd0032800, 0x41f0e8bd, 0xbd83f00a, 0x81f0e8bd, 
+    0x20004981, 0x7008b510, 0xfb84f7ff, 0x2301487d, 0x0319220c, 0xf0191d80, 0x2002faa2, 0xfba2f7fd, 
+    0xfb51f7ff, 0x21004876, 0xf019303a, 0x4874fa7e, 0x30542101, 0xfa79f019, 0xf6424871, 0x30520100, 
+    0xfa73f019, 0x23014c69, 0x3c32220a, 0x46200299, 0xfa85f019, 0x46202301, 0x02592209, 0xfa7ff019, 
+    0x46202208, 0x01512301, 0xfa79f019, 0xfd14f00a, 0xfbe2f7f2, 0x46112200, 0xf0094610, 0x2109f8a5, 
+    0xe8bd4a5b, 0x20054010, 0xb999f7f1, 0xb570485f, 0x78004d5f, 0x2301b108, 0x2300e000, 0x22034628, 
+    0xf0192108, 0x4c5bfa5c, 0xb1f17821, 0x46282301, 0x21042202, 0xfa53f019, 0x46282301, 0x461a2102, 
+    0xfa4df019, 0x7821484f, 0x2901302c, 0x2301d901, 0x2300e000, 0x21012200, 0xfa41f019, 0x4c4c484e, 
+    0x78011d24, 0x2301b161, 0x2300e00b, 0x22024628, 0xf0192104, 0x2300fa34, 0x22014628, 0xe7eb2102, 
+    0x46202300, 0x21012200, 0xfa29f019, 0x78094943, 0x2301b109, 0x2300e000, 0x22014620, 0xf0192102, 
+    0x493ffa1e, 0x70082001, 0x680a493e, 0x2a01493e, 0x7008d02d, 0x493d2201, 0x3d384d35, 0x21027008, 
+    0xf0194628, 0x2206fa1a, 0x21404604, 0xf0194628, 0x4304fa14, 0x22054628, 0xf0192120, 0x4304fa0e, 
+    0xb2e34833, 0x22044c34, 0x70032110, 0x70034831, 0xf0194620, 0x2300f9f4, 0x22034620, 0xf0192108, 
+    0xe8bdf9ee, 0x482d4070, 0xf0192100, 0x2200b9ce, 0xe7cf700a, 0xf3c04a2a, 0x70111100, 0x11c0f3c0, 
+    0x70114a28, 0x78094928, 0xd11b2901, 0xf3c04a27, 0x70110180, 0x01c0f3c0, 0x70114a25, 0x1140f3c0, 
+    0x70114a24, 0x1180f3c0, 0x70114a23, 0x0201f000, 0xf3c04922, 0x780b0040, 0x700a431a, 0x780a4920, 
+    0x700a4302, 0x00004770, 0xd28f00a4, 0xd28f22d2, 0xcccc0000, 0x000301dc, 0xd03c8316, 0x0003021d, 
+    0xd28f201c, 0xd0039026, 0x000302ec, 0x00030257, 0xd28e0078, 0x00030258, 0x000302a9, 0x000302aa, 
+    0x00030390, 0x00030314, 0x0003038e, 0x00030392, 0x00030387, 0x00030381, 0xd0035256, 0xd03c8026, 
+    0x000303a6, 0x000302ab, 0x0003038f, 0x00030396, 0x00030395, 0x0003038a, 0x0003038b, 0x00030398, 
+    0x00030397, 0x5ff0e92d, 0x9384f8df, 0x4be12400, 0x4ee24de1, 0x4000f889, 0x781b4fe1, 0xf8dfb310, 
+    0x2801c384, 0x8380f8df, 0xa380f8df, 0xe00bf89c, 0x1cdeea4f, 0x2802d01c, 0x2000d02a, 0x0000f88a, 
+    0x0000f888, 0x70307028, 0x29037038, 0x8360f8df, 0xa360f8df, 0xb360f8df, 0x2905d023, 0x2904d036, 
+    0xe05cd049, 0x680048d5, 0xd3172818, 0xe7ec703b, 0xd1ea2a01, 0xc000f888, 0x1040f3ce, 0xc000f88a, 
+    0x1280f3ce, 0x70307028, 0xf889703b, 0xe7dc2000, 0xd1032a01, 0xc000f888, 0xc000f88a, 0x7033702b, 
+    0x2201e7e4, 0x21024640, 0xf937f019, 0xf88a2201, 0x21020000, 0xf0194640, 0x49c1f930, 0x70082405, 
+    0x783849c0, 0x0000f88b, 0xe0287008, 0x46402206, 0xf0192140, 0x2206f922, 0x0000f88a, 0x46402140, 
+    0xf91bf019, 0x240449b6, 0x49b67008, 0xf88b7830, 0x70080000, 0x2205e013, 0x21204640, 0xf90df019, 
+    0xf88a2205, 0x21200000, 0xf0194640, 0x49acf906, 0x70082403, 0x782849ab, 0x0000f88b, 0x25017008, 
+    0x1000f89a, 0x4fa948a8, 0x4ea92901, 0x82a4f8df, 0xf89bd103, 0x29011000, 0x49a1d004, 0x29017809, 
+    0xe027d024, 0x6809499d, 0xd3092912, 0x70012102, 0x1000f899, 0xf004fa05, 0xf4404308, 0xe008403c, 
+    0x70012103, 0x1000f899, 0xf004fa05, 0xf4404308, 0xb281406e, 0xf0194638, 0x4640f8a8, 0xe8bd7035, 
+    0x23005ff0, 0x21082203, 0xb8b9f019, 0x7809498d, 0xd00e2901, 0x70042400, 0x46232203, 0x46402108, 
+    0xf8adf019, 0x46382100, 0xf88ff019, 0xe8bd7034, 0x21059ff0, 0x23017001, 0x22034640, 0xf0192108, 
+    0x2301f89e, 0x22004884, 0xf0194619, 0xf899f898, 0xfa051000, 0x4308f004, 0xf440b280, 0x4638414f, 
+    0xf873f019, 0xe7e27035, 0x47f0e92d, 0x48774604, 0x46154699, 0x460e2301, 0x21042202, 0xe9dd3816, 
+    0xf0197808, 0x4623f87c, 0x22084c70, 0x01513c40, 0xf0194620, 0x2207f874, 0x21804633, 0xf0194620, 
+    0x220af86e, 0xf240462b, 0x46204100, 0xf867f019, 0x464b2209, 0x2100f240, 0xf0194620, 0x2206f860, 
+    0x2140463b, 0xf0194620, 0x2205f85a, 0x21204643, 0xf0194620, 0x2301f854, 0x220f4620, 0x462903dd, 
+    0xf84df019, 0x46204629, 0x47f0e8bd, 0x220f2300, 0xb845f019, 0x2801b51c, 0x494ad11e, 0x098a79c9, 
+    0x2a014956, 0xd117700a, 0x78094955, 0xfebaf7ff, 0x48414942, 0x78007809, 0x0100e9cd, 0x78034843, 
+    0x78024841, 0x7801484f, 0x7800484f, 0xff9cf7ff, 0x401ce8bd, 0xbb9df7f7, 0xb530bd1c, 0x5403e9dd, 
+    0x2804b10c, 0xb11dd002, 0xe004b95a, 0xbd302003, 0xb932b911, 0xb109e002, 0xbd302000, 0x2002b10b, 
+    0x2001bd30, 0x4308bd30, 0x2001d000, 0xb570e64a, 0x21034c3e, 0xf0184620, 0x483cffe8, 0x4101f240, 
+    0xf018301a, 0x4839ffe2, 0x0100f642, 0xf0183018, 0x2181ffdc, 0xf0181f20, 0x4935ffd8, 0x4620220f, 
+    0xf248780b, 0xf0180100, 0x4d32ffea, 0xb3587828, 0x46202301, 0x21402206, 0xffe1f018, 0xf6477828, 
+    0x1e404100, 0x220ab283, 0xf0184620, 0x482affd8, 0x21802207, 0x46207803, 0xffd1f018, 0x46202301, 
+    0x21202205, 0xffcbf018, 0xff3bf00f, 0xf7f72004, 0x200bffe8, 0xf8fcf7f8, 0x46202208, 0x4070e8bd, 
+    0x01512301, 0xbfbbf018, 0x22062300, 0xe7db2140, 0x00030383, 0x0003038c, 0x0003038b, 0x0003038a, 
+    0x00030389, 0x0003112c, 0x00030395, 0x00030396, 0xd28e0040, 0x00030387, 0x00030388, 0x000301cc, 
+    0x00030381, 0x00030382, 0x00030c5a, 0xd28f0076, 0x00030c59, 0xd0035256, 0xd03c8024, 0x0003031d, 
+    0x00030222, 0x00030398, 0x00030397, 0xd28f2056, 0x000302e5, 0x000302e6, 0x000302e7, 0x4ff0e92d, 
+    0x92c4f8df, 0xb0872000, 0x8000f8d9, 0xf97bf7fa, 0x4100f240, 0x0b01f04f, 0xf8cd2205, 0x104cb00c, 
+    0xe9cd9400, 0xf8d92101, 0x1f920000, 0xf2402103, 0xf2406500, 0xf24016df, 0x465b17a7, 0xff64f00b, 
+    0xf04f48a2, 0xf8df0100, 0x7800a288, 0x46082803, 0xf8d9d013, 0xf9333000, 0x2a002011, 0x4252da00, 
+    0x42a11c49, 0xdbf64410, 0x20001244, 0xdd1242b4, 0x1464eba4, 0x1165eba5, 0xf99ae013, 0xeb082001, 
+    0xf9332382, 0x2a002011, 0x4252da00, 0x42a11c49, 0xdbf64410, 0x42bce7e8, 0xeb04da08, 0xeb051464, 
+    0x1c401165, 0xb20db240, 0xdbdf2810, 0x0800f44f, 0x11f4f240, 0xf7f04640, 0x4986fe04, 0xf7f04640, 
+    0x4639fdef, 0xf7f04640, 0x4621fdeb, 0xf7f04640, 0x4631fde7, 0xf7f04640, 0x4629fde3, 0xf7f04640, 
+    0x497dfddf, 0xf7f04640, 0x2000fddb, 0xfbe4f7f8, 0xf2404e7a, 0x46404800, 0xf7f77831, 0x2001ff79, 
+    0xfcaef7f6, 0xf2404f76, 0x68381100, 0xfed4f019, 0x10696838, 0x01a5eb01, 0xf8204249, 0x25005f60, 
+    0x8041462c, 0x7800486f, 0xd0372803, 0x23006838, 0x0500e9cd, 0x461a2001, 0xf7f6b261, 0x1c64fb03, 
+    0x2c04b2a4, 0x2000d3f2, 0xfc8af7f6, 0x78204c66, 0xd0322801, 0xf00c2002, 0x7831fe5b, 0xf7f72040, 
+    0xf7feff47, 0x7831fd2d, 0x0000f244, 0xff40f7f7, 0x4640220b, 0x46112300, 0x95019500, 0xfc69f7f8, 
+    0xf241220d, 0x23000000, 0x95004611, 0xf7f89501, 0x4f56fc60, 0xb3e87838, 0xe04e2001, 0x23006838, 
+    0x0500e9cd, 0x1004f91a, 0x461a2001, 0xfacaf7f6, 0xb2a41c64, 0xd3f12c03, 0x2000e7c5, 0xfe28f00c, 
+    0xf640220e, 0x46110900, 0xf7f84648, 0x2002fcfb, 0xfe1ef00c, 0x20407831, 0xff0af7f7, 0x9000200c, 
+    0x465f220d, 0x46112301, 0xb502e9cd, 0x95059504, 0x46409001, 0xfd76f7f8, 0x9000200d, 0x46022301, 
+    0x7502e9cd, 0x95044601, 0x90019505, 0xf7f84648, 0xe000fd69, 0x200ee00d, 0x23019000, 0xe9cd4602, 
+    0x46017502, 0x95059504, 0x46489001, 0xfd5af7f8, 0x7820e7af, 0xd1af2801, 0xf00b2000, 0x4605f889, 
+    0xf7f82000, 0x7831fb39, 0x464046c1, 0xfed0f7f7, 0xd0362d00, 0xd13407e8, 0xf2464d25, 0xf8df0a00, 
+    0x220d8094, 0xf9954651, 0xb2830000, 0xf0184640, 0x2301fe46, 0x220f4640, 0xf01803d9, 0x2001fe40, 
+    0xfdc6f00c, 0x46487831, 0xfeb2f7f7, 0x481a7839, 0xf9952900, 0x5c411000, 0x7820d102, 0xd0012801, 
+    0xe0002001, 0xf00a2000, 0x2300fef8, 0x220d4651, 0xf0184640, 0xb007fe24, 0xe8bd2000, 0xf00c4ff0, 
+    0xb007bda7, 0x8ff0e8bd, 0x000301b8, 0x00030394, 0x00030338, 0x99339933, 0xdcba01f5, 0x00030223, 
+    0x000301c4, 0x00030214, 0x0003031c, 0x00030284, 0x0003020e, 0xd0035092, 0x0003033c, 0x41ffe92d, 
+    0xf04f4efe, 0x15505200, 0x1000f996, 0xfd27f7f0, 0xfe74f7ff, 0xf7f82000, 0xf44ffacf, 0xf2400500, 
+    0x462811f4, 0xfccdf7f0, 0x462849f5, 0xfcb8f7f0, 0xf9944cf4, 0xb2810000, 0xf7f04628, 0x49f2fcc2, 
+    0xf7f04628, 0x4668fcad, 0xfda9f7f9, 0x0000f994, 0xd0011c40, 0xe0232007, 0xf2404dec, 0xf8df2700, 
+    0xf99583b0, 0x1c400000, 0xeb0017c1, 0xf0217191, 0x1a400103, 0x24007028, 0xb1087828, 0xe0004639, 
+    0x46204641, 0xfc63f7fe, 0xb2641c64, 0xdbf32c04, 0x28007828, 0x48dfd105, 0xf7f37800, 0x2003fdd2, 
+    0xe8bd7030, 0xe92d81ff, 0x24005ffc, 0x46a24615, 0xfad2f01b, 0xfa0f4ed8, 0xf8dff980, 0x27018360, 
+    0x0b80f44f, 0x49d74ad6, 0x80374668, 0xa006f8ad, 0xa002f8ad, 0xa004f8ad, 0xa000f8ad, 0x3000f898, 
+    0xfe1ef7f9, 0x46582172, 0xfc93f7f0, 0x46482202, 0xf00c2107, 0x4668fd13, 0xfdf3f7f9, 0x46692000, 
+    0x2010f931, 0xdb0142aa, 0x5010f821, 0xb2401c40, 0xdbf52804, 0x780048c4, 0xd1042803, 0xf99048c3, 
+    0xf8210003, 0xf8987010, 0x46683000, 0x49bd4abc, 0xfdf6f7f9, 0x46582172, 0xfc6bf7f0, 0x28028830, 
+    0x1c64d103, 0x2c0ab264, 0xf8a6dbbc, 0xe8bda000, 0xe92d9ffc, 0x4fa947f0, 0x5200f04f, 0x60782050, 
+    0xf9971550, 0xf7f01000, 0x4eb1fc7a, 0xf8df2000, 0x4aab82ac, 0x80f049ab, 0x807080b0, 0x46308030, 
+    0x3000f898, 0xfdccf7f9, 0x0980f44f, 0x46482172, 0xfc3ff7f0, 0xf2402202, 0x21071048, 0xfcbef00c, 
+    0x4630251e, 0xf7f92401, 0x2000fd9c, 0x1010f936, 0xdb0142a9, 0x5010f826, 0x1010f936, 0xdc0142a1, 
+    0x4010f826, 0xb2401c40, 0xdbef2804, 0x3000f898, 0x49944a93, 0xf7f94896, 0x2172fda3, 0xf7f04648, 
+    0x2060fc18, 0xe8bd6078, 0xb53887f0, 0x20004c83, 0x20309000, 0x46686060, 0xf8aaf7fa, 0x7801488a, 
+    0x29034668, 0x4a89d104, 0xf9922101, 0x54812003, 0x78094982, 0xd10c2903, 0xf9914981, 0xf9912000, 
+    0x5c823002, 0xf99154c2, 0xf9912001, 0x5c821003, 0xf89d5442, 0x4d7f0000, 0xf89db1b8, 0xb1e80001, 
+    0x0002f89d, 0xf89db188, 0xb1700003, 0xf2422040, 0x60600110, 0xf7f00640, 0x2003fbc0, 0x23017020, 
+    0x22004628, 0xf0184619, 0xf89dfcca, 0xb1280001, 0x46282301, 0x461a2102, 0xfcc1f018, 0x0002f89d, 
+    0x2301b128, 0x22024628, 0xf0182104, 0xf89dfcb8, 0x28000003, 0x2301d005, 0x22034628, 0xf0182108, 
+    0xbd38fcae, 0x5ff0e92d, 0x8e804604, 0x26014d53, 0x7f96f5b0, 0x1a05f240, 0x1b61f240, 0xdc35d07b, 
+    0xf2a04550, 0xd0691105, 0x28f0dc18, 0xdc06d074, 0x28ceb330, 0x28cfd075, 0x60aed170, 0x28f1e07c, 
+    0xf5b0d05c, 0xd1697f82, 0x22004944, 0x311068e8, 0xfcd7f014, 0x1d4060a8, 0xe050d07c, 0xd04d2910, 
+    0x2907dc0f, 0x2908d077, 0x290fd048, 0x493bd156, 0x68e82200, 0xf0143110, 0x60a8fcc4, 0xd06b1d40, 
+    0x291fe03d, 0x2920d069, 0xe037d148, 0xf2a04558, 0xd0331161, 0xf5b0dc1b, 0xd07d7fa6, 0xf111dc07, 
+    0xd02b0034, 0xd0782813, 0xd1372814, 0xf5a0e026, 0x384d7080, 0x2813d022, 0x4928d130, 0x68e82200, 
+    0xf0143110, 0x60a8fc9e, 0xd0671d40, 0x291ae017, 0xdc0fd014, 0xd07d2911, 0xd00f2912, 0xd11d2919, 
+    0x2200491e, 0x311068e8, 0xfc8bf014, 0x1d4060a8, 0xe004d071, 0xd06f2921, 0xd10f2922, 0xf04f60ae, 
+    0x491632ff, 0x311068e8, 0xfcaaf014, 0x1d0060a8, 0x68a8d005, 0xe159e00c, 0xe002e0a5, 0x20cee0d4, 
+    0x490ee209, 0x68e82200, 0xf0143110, 0x60a8fc99, 0xd0671d41, 0xd1e22801, 0xf2404f08, 0x37101000, 
+    0x3000f9b7, 0xd05f2b0f, 0xf04f0542, 0xf04f080a, 0xe0244c20, 0xe0cbe0b6, 0xe11be0ef, 0x00030454, 
+    0x99349934, 0x0003020e, 0xdcba01f5, 0x00030322, 0xfffffa00, 0x00030222, 0x00030248, 0x00030394, 
+    0x00030338, 0x00030366, 0x00030214, 0x00030330, 0x00030350, 0xd0035018, 0xe139e158, 0x2b10e17f, 
+    0x2b0ad03a, 0xf995d1ab, 0xf8df1000, 0xb3919420, 0xd06f2903, 0xd06e2906, 0xd06d2902, 0xd06c2904, 
+    0xd06b290c, 0xd06a2907, 0xd0692905, 0xd0682909, 0xe002290a, 0xe19de17c, 0xd06fe1a2, 0xd18e290b, 
+    0x46624619, 0xfaebf7f0, 0x8038200b, 0xf04f48f8, 0x463932ff, 0xf0146800, 0x60a8fc04, 0xd0731d00, 
+    0xe19468a8, 0xe19620cf, 0x4222f04f, 0xf7f04619, 0x702efad6, 0xe030e773, 0xf99149ee, 0x29031000, 
+    0x2905d003, 0x2904d001, 0x49ebd102, 0xb1217809, 0x702e210f, 0xfac3f7f0, 0x4619e761, 0xf7f04662, 
+    0xf000fabe, 0x2000fa72, 0xf8a77028, 0x46028000, 0x68e849e2, 0xfbd5f014, 0x1d0060a8, 0x68a8d001, 
+    0x20f0e007, 0x49dde167, 0x68e82200, 0xfbc9f014, 0x1d4060a8, 0x20f1d1ce, 0xf7ffe15d, 0x2002fe66, 
+    0xfba4f7f7, 0xf899b920, 0x1e400000, 0xd2092806, 0xe008200a, 0xe036e01a, 0xe086e052, 0xe0c2e0a1, 
+    0xe0ffe0df, 0x8038200f, 0x220049cc, 0xf01468e8, 0x60a8fba8, 0xd0021d00, 0xe6cc68a8, 0xf240e113, 
+    0xe1381004, 0xa034f8a4, 0x9ff0e8bd, 0xfdf1f7ff, 0x70282006, 0x220049c1, 0xf01468e8, 0x60a8fb92, 
+    0xd0021d00, 0xe00968a8, 0xf240e117, 0xe122100c, 0x220049ba, 0xf01468e8, 0x60a8fb84, 0xd1891d40, 
+    0x100df240, 0x2370e117, 0xf7f0606b, 0x49b4fa58, 0x48b4221e, 0xfd77f7ff, 0x60682080, 0x70282002, 
+    0x220049ae, 0xf01468e8, 0x60a8fb6c, 0xd0011d00, 0xe6a368a8, 0x1014f240, 0xf240e0fd, 0xe0fa1015, 
+    0x606b2390, 0xfa3bf7f0, 0x22002101, 0xf0084608, 0x2100f93b, 0x1080f44f, 0xfb7af7f7, 0x20012200, 
+    0xf0084611, 0xf00cf931, 0xf7f7fac1, 0xf7f7ff99, 0x20a0ffb3, 0x20046068, 0x49987028, 0x68e82200, 
+    0xfb3ff014, 0x1d0060a8, 0x68a8d001, 0xf240e008, 0xe0d01024, 0x22004991, 0xf01468e8, 0x60a8fb32, 
+    0xd1ac1d40, 0x1025f240, 0xf000e0c5, 0x200cf991, 0x498a7028, 0x68e82200, 0xfb23f014, 0x1d0060a8, 
+    0x68a8d001, 0xf240e008, 0xe0b4102c, 0x22004983, 0xf01468e8, 0x60a8fb16, 0xd1901d40, 0x102df240, 
+    0xf7ffe0a9, 0x2002fcbb, 0xfaf0f7f7, 0x200ab108, 0x200fe000, 0x49798038, 0x68e82200, 0xfb01f014, 
+    0x1d0060a8, 0x68a8d001, 0xf240e008, 0xe0921040, 0x22004972, 0xf01468e8, 0x60a8faf4, 0xd1c01d40, 
+    0x1041f240, 0xf7f0e087, 0xf006f9ca, 0x2005ff9d, 0x496a7028, 0x68e82200, 0xfae3f014, 0x1d0060a8, 
+    0x68a8d001, 0xf240e008, 0xe074104c, 0x22004963, 0xf01468e8, 0x60a8fad6, 0xd1a21d40, 0x104df240, 
+    0xf000e069, 0xf899f8ff, 0x28030000, 0x2002d005, 0xfaacf7f7, 0x200ab120, 0xf8a7e003, 0xe0018000, 
+    0x8038200f, 0x22004955, 0xf01468e8, 0x60a8faba, 0xd0011d00, 0xe61768a8, 0x1060f240, 0xf8a4e04b, 
+    0xe711b034, 0xf8adf000, 0x0000f899, 0xf43f2803, 0xf885add4, 0x22008000, 0x68e84948, 0xfaa1f014, 
+    0x1d0060a8, 0x68a8d001, 0xf240e008, 0xe0321072, 0x22004942, 0xf01468e8, 0x60a8fa94, 0xd19e1d40, 
+    0x1073f240, 0xf000e027, 0x2002f837, 0xfa6ef7f7, 0x200ab108, 0x200fe000, 0x49388038, 0x68e82200, 
+    0xfa7ff014, 0x1d0060a8, 0x68a8d001, 0xf240e5ef, 0xe010107a, 0x107bf240, 0xf240e00d, 0xe00a1082, 
+    0x2200482b, 0x6800492d, 0xfa6bf014, 0x1d4060a8, 0xf240d193, 0x86a01083, 0x2200e6c6, 0xb5102101, 
+    0x503ff2af, 0xf8a8f014, 0x20032108, 0xfa06f014, 0x39104922, 0xbd1060c8, 0xf00ab510, 0x4922f95f, 
+    0xf0174822, 0x2801fff3, 0x1300f240, 0x21e2d019, 0x4618461c, 0xf8d5f7f0, 0x46202100, 0xf8c0f7f0, 
+    0x01d0f242, 0xf7f04620, 0x4819f8d8, 0x28017800, 0x2100d034, 0xe8bd4817, 0xf2014010, 0xf018312b, 
+    0x4812b9c4, 0x79c04914, 0x1000f3c0, 0x28007008, 0x4c0ad00a, 0x5200f04f, 0x3c104618, 0x1000f994, 
+    0xf8fdf7f0, 0x7020200b, 0x0000bd10, 0x00030214, 0x000304ec, 0x00030222, 0x00030284, 0x00030464, 
+    0x44b861ec, 0x43a4170a, 0x0002b8b0, 0x0003112c, 0x0003031c, 0xd03c80b8, 0x000301e4, 0x7110f242, 
+    0x4965e7c8, 0xb5082001, 0x48647008, 0xb1487800, 0x78014863, 0x78034863, 0x78024863, 0x78004863, 
+    0xfd73f7fa, 0x49634862, 0x0000f990, 0xff06f7f5, 0x21044a61, 0xf018485f, 0x4860f84f, 0x5200f04f, 
+    0x1000f990, 0xf7f01550, 0x2004f8ba, 0xffdaf00c, 0x7008495b, 0x46032000, 0x46014602, 0xf7f69000, 
+    0xbd08fb57, 0x4c55b510, 0x5200f04f, 0xf9941550, 0xf7f01000, 0xf00af8a4, 0xb158fc20, 0x78004851, 
+    0xd0022803, 0x70202009, 0x2004e79e, 0xf989f7f7, 0xe7f8200b, 0xf7f92000, 0x4841fb66, 0xf7f37800, 
+    0x4849f980, 0x70222203, 0x49412300, 0x4000f990, 0xf990550b, 0x23014001, 0xf990550b, 0x23024002, 
+    0xf990550b, 0x540a0003, 0x4010e8bd, 0xbb78f00a, 0x4c3ab510, 0x5200f04f, 0x606020b0, 0xf9941550, 
+    0xf7f01000, 0x20b1f86c, 0xf00c6060, 0xf7f7f8ff, 0xf7f7fdd7, 0x20bbfdf1, 0x48326060, 0xb1707800, 
+    0xd00c2807, 0x606020e0, 0x22004830, 0x20026801, 0xf96cf7f7, 0xfaa2f00b, 0x606020f0, 0x20c0e754, 
+    0xf00b6060, 0x20d0fa9b, 0xb570e7f7, 0x20104c23, 0x01052101, 0x46286060, 0xfff3f7ef, 0x11f4f240, 
+    0xf7ef4628, 0x4822ffee, 0xf0406800, 0x462841d0, 0xffd6f7ef, 0x4628491f, 0xffd2f7ef, 0xf7f92000, 
+    0xf7f9f90f, 0x2020fa3a, 0x48176060, 0x49102400, 0x2000f990, 0xf990548c, 0x22013001, 0xf99054ca, 
+    0x22023002, 0xf99054ca, 0x22030003, 0xf00a540a, 0x4811fb17, 0xbd707004, 0x000301e3, 0x00030308, 
+    0x00030222, 0x000303b9, 0x000303b8, 0x00030307, 0x00030330, 0x00030fec, 0x0003102c, 0x00030454, 
+    0x000301e5, 0x00030214, 0x00030338, 0x000303a0, 0x00047f78, 0xdcba01f5, 0x00030322, 0x4cffb510, 
+    0x4280f04f, 0xf9b41510, 0xf7ef1000, 0xf00affe8, 0xb160fb64, 0x230048fa, 0xf44f2211, 0xf0183100, 
+    0x2001f897, 0xfd88f7f7, 0x8020200e, 0x2007bd10, 0x48f48020, 0x49f42200, 0x3000f990, 0xf99054ca, 
+    0x22013001, 0xf99054ca, 0x22023002, 0xf99054ca, 0x22030003, 0xe8bd540a, 0xf00a4010, 0x48e7bac1, 
+    0x4280f04f, 0xf9b0b510, 0x15101000, 0xffb7f7ef, 0xf7f948e6, 0x49e5f8f6, 0x221e2000, 0xf9312301, 
+    0x2c1e4010, 0xf821db01, 0xf9312010, 0x2c014010, 0xf821dc01, 0x1c403010, 0x2804b240, 0x48dcdbef, 
+    0x49dc4ad8, 0x48d97803, 0xf8faf7f9, 0xf44f2172, 0xf7ef0080, 0xe8bdff6e, 0xf0064010, 0xe92dbd65, 
+    0x4ece41f0, 0x4280f04f, 0xf9b61510, 0xf7ef1000, 0xf7ffff86, 0x2000f8d3, 0xfd2ef7f7, 0xf99048ce, 
+    0x1c400000, 0x2012d001, 0x4dcce01f, 0x2700f240, 0x832cf8df, 0x0000f995, 0x17c11c40, 0x7191eb00, 
+    0x0103f021, 0x70281a40, 0x78282400, 0x4639b108, 0x4641e000, 0xf7fd4620, 0x1c64feda, 0x2c04b264, 
+    0x7828dbf3, 0xd1012800, 0x80302007, 0x81f0e8bd, 0x4ff0e92d, 0x4fbda0bb, 0xe9d0b08d, 0xe9cd1000, 
+    0x48bb100b, 0x6800683d, 0xd3142812, 0x409cf648, 0xf6469004, 0x900530ad, 0x707af242, 0xf2419006, 
+    0x90071029, 0x3063f640, 0xf2409008, 0x900940e7, 0x20a9f240, 0xf244e013, 0x900430a4, 0x401cf243, 
+    0xf2419005, 0x90064016, 0x003df640, 0xf2409007, 0x9008505b, 0x207ff240, 0xf2409009, 0xf8df104d, 
+    0xf240b25c, 0x900a4a00, 0x4280f04f, 0x46504656, 0x1000f9bb, 0xff13f7ef, 0xf44f2100, 0xf7f72000, 
+    0x2101f857, 0x02082405, 0xe9cd1e8a, 0xe9cd6102, 0x68380400, 0x21082300, 0xffd6f00a, 0x46132200, 
+    0x20004611, 0x2741eb05, 0x6010f937, 0xb2801c40, 0xfbc628ff, 0xd9f72386, 0xb2c91c49, 0xd3f02904, 
+    0x0c959804, 0xea454e8b, 0x42a83583, 0x7034d801, 0x2000e033, 0x46047030, 0xeb00a804, 0x68490184, 
+    0xd82242a9, 0x7024f850, 0x0084eb00, 0x1a386840, 0xf836f01a, 0x46894680, 0xf01a1b78, 0x4605f831, 
+    0xa80b460f, 0x5d041901, 0x1b087849, 0xf811f01a, 0x463b462a, 0xf874f01a, 0x464b4642, 0xfe54f019, 
+    0xffdaf019, 0x70304420, 0x1c64e003, 0x2c06b2a4, 0x7830d3d3, 0x2064b908, 0x78307030, 0x0100f640, 
+    0x30234654, 0x46507030, 0xfe5bf7ef, 0x46207831, 0xfe46f7ef, 0x22002101, 0xf0074608, 0x4c66fda5, 
+    0x4e5b2500, 0x46204a57, 0x80e5495a, 0x806580a5, 0x78338025, 0xfff4f7f8, 0x0880f44f, 0x46402172, 
+    0xfe67f7ef, 0x22004f5d, 0x46382101, 0xff65f017, 0x2201b988, 0x21024638, 0xff5ff017, 0x2202b958, 
+    0x21044638, 0xff59f017, 0x2203b928, 0x21084638, 0xff53f017, 0x2001b110, 0xfe83f7fb, 0xf2402202, 
+    0x210710c3, 0xfecaf00b, 0xf7f8484b, 0xf9bbffaa, 0x20001002, 0x2010f934, 0xdb01428a, 0x1010f824, 
+    0xb2401c40, 0xdbf52804, 0x4a367833, 0x48424939, 0xffb6f7f8, 0x46402172, 0xfe2bf7ef, 0xf00b2002, 
+    0x2000fea7, 0xf91ff7f9, 0xf7fa2000, 0x2101f874, 0x46082200, 0xfd48f007, 0xf44f2100, 0xf7f62000, 
+    0x2004ff87, 0xfd5ef00c, 0x23004935, 0x7008461a, 0x46184619, 0xf7f69500, 0x2200f8db, 0x46112001, 
+    0xfd32f007, 0xe8bdb00d, 0x481c8ff0, 0x4280f04f, 0x1000f9b0, 0xf7ef1510, 0x2101be22, 0x028cb510, 
+    0xf7ef4620, 0xf240fdce, 0x462011f4, 0xfdc9f7ef, 0x68084924, 0x41f0f040, 0xf7ef4620, 0x4922fdb1, 
+    0xf7ef4620, 0x490dfdad, 0x8048201e, 0xf7f82001, 0x480cf893, 0x490c2400, 0x2000f990, 0xf990548c, 
+    0x22013001, 0xf99054ca, 0x22023002, 0xf99054ca, 0x22030003, 0xf00a540a, 0xe027f8f3, 0x0003046c, 
+    0xd1800000, 0x00030338, 0x00030330, 0x00030358, 0x00030394, 0x00030366, 0x0003020e, 0x00030322, 
+    0xfffffa00, 0x321e0a05, 0x0064503c, 0x000301b8, 0x000301cc, 0x0003031e, 0x00030350, 0xd00305c2, 
+    0x000301e5, 0x00047f78, 0xdcba01f5, 0x700448fa, 0xe92dbd10, 0x46045ff0, 0x4df88e80, 0x1b50f240, 
+    0xa3dcf8df, 0xf2404558, 0xf2401801, 0xd0741969, 0x4540dc32, 0x1101f2a0, 0xdc16d064, 0xd06d28e6, 
+    0xb318dc05, 0xd06c28c4, 0xd16928c5, 0x28e7e073, 0xf5b0d058, 0xd1637f80, 0x220049e8, 0x31086868, 
+    0xfebff013, 0xd07d1d40, 0x291ce04c, 0xdc0ed04a, 0xd0782909, 0xd045290a, 0xd151291b, 0x220049df, 
+    0x31086868, 0xfeadf013, 0xd06d1d40, 0x2945e03a, 0x2946d06b, 0xe035d144, 0xf2a04548, 0xd0311169, 
+    0xf5b0dc1a, 0xd07d7fb0, 0xf111dc07, 0xd0290018, 0xd0782807, 0xd1332808, 0xf5a0e024, 0x38617080, 
+    0x2807d020, 0x49cdd12c, 0x68682200, 0xf0133108, 0x1d40fe88, 0xe015d068, 0xd0132910, 0x2907dc0e, 
+    0x2908d070, 0x290fd00e, 0x49c4d11a, 0x68682200, 0xf0133108, 0x1d40fe76, 0xe003d07c, 0xd07a291b, 
+    0xd10d291c, 0xf04f49bd, 0x686832ff, 0xf0133108, 0x1d01fe97, 0x20c4d10b, 0xe11fe1c7, 0xe000e080, 
+    0x49b6e0aa, 0x68682200, 0xf0133108, 0x1d41fe89, 0x2801d046, 0x4eb1d1e6, 0xf2402700, 0x36084000, 
+    0x1000f9b6, 0xd03e290f, 0x29110502, 0x290ad041, 0xf9b5d1d8, 0x4fab1000, 0xd06b2902, 0xd07d2901, 
+    0xe0032903, 0xe09ee086, 0xe0dde0bf, 0x2904d077, 0x2905d076, 0x2906d075, 0x2907d074, 0x2910d073, 
+    0x2912d072, 0x2908d071, 0x290ed070, 0xf7efd1ba, 0xf242fd06, 0x06c80170, 0xfcbff7ef, 0x8030200b, 
+    0xe002200f, 0xe0f9e114, 0x8028e13f, 0x32fff04f, 0x0000f8da, 0xf0134631, 0x1d01fe14, 0xe170d072, 
+    0xe17220c5, 0xf04fe142, 0xf7ef4224, 0x802ffce8, 0x4b8de798, 0x3000f993, 0xd0032b03, 0xd0012b05, 
+    0xd1022b04, 0x781b4b89, 0x2113b133, 0xf7ef802f, 0xe787fcd6, 0xe14ee149, 0x4220f04f, 0xfccff7ef, 
+    0xfeabf7ff, 0x2002497d, 0x200a8028, 0x22008030, 0x31086868, 0xfde5f013, 0xd1071d01, 0xe14420e6, 
+    0x22004976, 0x31086868, 0xfddbf013, 0xd1cf1d40, 0xe13a20e7, 0x28017838, 0x2002d102, 0xfda1f7f6, 
+    0xfe83f7ff, 0x2001496d, 0x22008028, 0x31086868, 0xfdc7f013, 0xf47f1d01, 0xe008af05, 0xe02de00e, 
+    0xe06ce046, 0xe0a4e085, 0xe0e1e0bd, 0xf240e0f8, 0xe11a1000, 0x8034f8a4, 0x9ff0e8bd, 0xfc8ff7ef, 
+    0x22002101, 0xf0074608, 0x495cfb8f, 0x80282003, 0x68682200, 0xf0133108, 0x1d01fda4, 0xf240d109, 
+    0xe102100a, 0x4955e0f4, 0x68682200, 0xf0133108, 0x1d40fd98, 0xf240d18c, 0xe0f6100b, 0xfc6ff7ef, 
+    0xf44f2100, 0xf7f61080, 0xf005fdb3, 0x494bfe54, 0x80282004, 0x68682200, 0xf0133108, 0x1d01fd82, 
+    0xaed2f47f, 0x101cf240, 0xf240e0df, 0xe0dc101d, 0xfc55f7ef, 0x20012200, 0xf0074611, 0x7838fb55, 
+    0xd00a2801, 0x2005493d, 0x22008028, 0x31086868, 0xfd67f013, 0xd0041d01, 0x2002e00c, 0xfd31f7f6, 
+    0xf240e6f0, 0xe0c01046, 0x22004934, 0x31086868, 0xfd57f013, 0xd1f31d40, 0x1047f240, 0xf000e0b5, 
+    0x492ef920, 0x80282006, 0x68682200, 0xf0133108, 0x1d01fd48, 0xf8a4d108, 0xe78db034, 0x22004927, 
+    0x31086868, 0xfd3df013, 0xd1d91d40, 0x1051f240, 0xf000e09b, 0x2002f8ab, 0xfd18f7f6, 0x200ab108, 
+    0x200fe000, 0x8030491d, 0x68682200, 0xf0133108, 0x1d01fd28, 0xf240d108, 0xe0861058, 0x22004917, 
+    0x31086868, 0xfd1df013, 0xd1b91d40, 0x1059f240, 0xf7ffe07b, 0x4911fc9d, 0x80282010, 0x68682200, 
+    0xf0133108, 0x1d01fd0e, 0xf240d108, 0xe06c1060, 0x2200490a, 0x31086868, 0xfd03f013, 0xd19f1d40, 
+    0x1061f240, 0xf7ffe061, 0x2002fc4a, 0xfcdef7f6, 0x200ab170, 0x0000e00d, 0x00030322, 0x0003046c, 
+    0x000304ec, 0x00030214, 0x00030222, 0x00030284, 0x8030200f, 0x22004974, 0xf0136868, 0x1d01fce2, 
+    0xae57f47f, 0x1068f240, 0xf8a4e03f, 0xe7239034, 0xfbf5f7ff, 0x80282008, 0x2200496b, 0xf0136868, 
+    0x1d01fcd0, 0xf240d107, 0xe02e1070, 0x22004966, 0xf0136868, 0x1d40fcc6, 0xf240d187, 0xe0241071, 
+    0xfbacf7ff, 0xf7f62002, 0xb108fca1, 0xe000200a, 0x8030200f, 0x2200495c, 0xf0136868, 0x1d01fcb2, 
+    0xae39f47f, 0x1078f240, 0xf240e00f, 0xe00c1079, 0x1084f240, 0x4954e009, 0xf8da2200, 0xf0130000, 
+    0x1d40fca0, 0xf240d19b, 0x86a01085, 0x2200e6e4, 0xb5102101, 0x40a5f2af, 0xfadef013, 0x20032108, 
+    0xfc3cf013, 0x39084948, 0xbd106048, 0x2000b5f8, 0x46689000, 0xffdcf7f8, 0x78004844, 0xd1102803, 
+    0xf9904843, 0xf9902000, 0xf81d3002, 0xf80d2002, 0xf9902003, 0xf9902001, 0xf81d0003, 0xf80d2002, 
+    0xf89d2000, 0x28000000, 0xf89dd03a, 0x28000001, 0xf89dd036, 0x28000002, 0xf89dd032, 0x28000003, 
+    0xf242d02e, 0x46210410, 0x462806e5, 0xfaf5f7ef, 0xf7f72000, 0x4b2cf8e1, 0x4e2e2207, 0x46303b08, 
+    0x2301801a, 0x46192200, 0xfbf9f017, 0x46302301, 0x461a2102, 0xfbf3f017, 0x46302301, 0x21042202, 
+    0xfbedf017, 0x46302301, 0x21082203, 0xfbe7f017, 0x68004821, 0xd8032810, 0x46284621, 0xfacdf7ef, 
+    0x4819bdf8, 0x4280f04f, 0x3808b508, 0x1000f9b0, 0xf7ef1510, 0x4919fb04, 0x4a1c2000, 0x70082300, 
+    0x70084917, 0x70084917, 0x70084917, 0x70112101, 0x4917461a, 0x49177008, 0x46197008, 0x20019000, 
+    0xfd96f7f5, 0x0140f242, 0xf7ef0648, 0xf7f8faa6, 0x2001fcf4, 0xf890f7f7, 0x4008e8bd, 0xf44f2100, 
+    0xf7f62000, 0x0000bc25, 0x00030474, 0x00030394, 0x00030338, 0xd0035018, 0x000301cc, 0x00030203, 
+    0x00030201, 0x000301fc, 0x000301ff, 0x000301e3, 0x000301e1, 0x000301de, 0x5ff0e92d, 0x46044da9, 
+    0x4ea98e80, 0x686b28c8, 0xdc15d070, 0xd0342893, 0xb300dc0d, 0xd16a2892, 0x46182200, 0x0108f105, 
+    0xfbfef013, 0xd0261d41, 0xd1192801, 0x28b4e025, 0x28b5d06f, 0xe013d15b, 0xd01128d1, 0x28c9dc0c, 
+    0x28d0d00e, 0x4997d153, 0x46182200, 0xf0133108, 0x1d40fbb8, 0xe003d07e, 0xd07c28da, 0xd14628db, 
+    0xf04f4990, 0x686832ff, 0xf0133108, 0x1d01fbd9, 0x2092d1d8, 0x2093e0c0, 0xf8dfe0be, 0x27008228, 
+    0x2000f240, 0x0808f108, 0x1000f9b8, 0xd027290f, 0xf04f2912, 0xf04f090a, 0xf04f5240, 0xd0274b00, 
+    0xd1dd290a, 0x1000f9b5, 0xfa69f7ef, 0x0000f9b5, 0xd06d2802, 0xd077280a, 0xd1d12806, 0x0170f242, 
+    0xf7ef4658, 0x200bfa1a, 0x0000f8a8, 0x80282007, 0x1e7a6830, 0xf0134641, 0x1d01fb74, 0xe088d06f, 
+    0x4223f04f, 0xfa4bf7ef, 0xe7b9802f, 0xe084e05d, 0xf9934b6e, 0x2b033000, 0x2b05d003, 0x2b04d001, 
+    0x4b6bd102, 0xb12b781b, 0x802f2109, 0xfa37f7ef, 0xe033e7a6, 0x4a20f04f, 0x46524607, 0xfa2ff7ef, 
+    0x465221f1, 0xf7ef4638, 0xf242fa2a, 0x46580150, 0xf9e3f7ef, 0xf7f62000, 0x485effcf, 0xf44f7801, 
+    0xf7f62080, 0xf44ffb65, 0xf6403000, 0xf7ef0103, 0xe001f9c8, 0xe046e043, 0xff93f7fc, 0xfcbbf7f7, 
+    0x20024950, 0x22008028, 0x9000f8a8, 0x68683108, 0xfb27f013, 0xd1071d01, 0xe03d20b4, 0x22004949, 
+    0x31084618, 0xfb1df013, 0xd1ae1d40, 0xe03320b5, 0x22004944, 0x9000f8a5, 0x31086868, 0xfb11f013, 
+    0xd1081d01, 0xe02720c8, 0x493ee00a, 0x46182200, 0xf0133108, 0x1d40fb06, 0x20c9d197, 0xe010e01c, 
+    0xf82bf000, 0x20064937, 0x22008028, 0x31086868, 0xfaf7f013, 0xf47f1d01, 0x20d0af3c, 0x20d1e00c, 
+    0x20dae00a, 0x492fe008, 0x68302200, 0xf0133108, 0x1d40fae8, 0x20dbd18c, 0xe8bd86a0, 0x22009ff0, 
+    0xb5102101, 0x200ff2af, 0xf926f013, 0x20032108, 0xfa84f013, 0x60484923, 0x2101bd10, 0x2200b570, 
+    0xf0074608, 0x2100f8b1, 0x2000f44f, 0xfaf0f7f6, 0x20012200, 0xf0074611, 0x4c1ff8a7, 0x46082100, 
+    0x2000f994, 0xfbf6f7f8, 0x0550f242, 0x06ee4629, 0xf7ef4630, 0xf005f952, 0x4629fb7e, 0xf7ef4630, 
+    0x2100f94c, 0xf7f82001, 0xf994fe4c, 0x21002000, 0xf7f8200c, 0x2101fb99, 0x2000f994, 0xf7f84608, 
+    0xf7fdfbd9, 0x4629f8ad, 0xf7ef4630, 0x480bf936, 0x22112300, 0xf0170bb1, 0xe8bdfa2b, 0x20014070, 
+    0xbf1af7f6, 0x0003047c, 0x000304ec, 0x00030222, 0x00030284, 0x00030223, 0x00030227, 0xd1800000, 
+    0x4ff8e92d, 0x0170f242, 0x06c82400, 0xf915f7ef, 0xf7f62000, 0x48ffff01, 0xf8df2501, 0xf04fa3fc, 
+    0xf8df0800, 0x0269b3f8, 0x7005462a, 0xf8aa4628, 0x46291000, 0x8000f8cd, 0x3008f8db, 0xfbe8f7f5, 
+    0x49f84ff7, 0x4afb4efa, 0x70087838, 0x49f748f6, 0x70387800, 0x29106809, 0x7811d91f, 0xf8df4bf6, 
+    0x2905c3dc, 0x7831d111, 0xd0062901, 0xe3d0f8df, 0xe000f89e, 0x010eea51, 0x7819d107, 0xd904294b, 
+    0x1000f89c, 0xd1002901, 0x78191e8c, 0xd204290f, 0x1000f89c, 0xd1002901, 0xf9921e64, 0x46911000, 
+    0x29039500, 0xeb04d00e, 0x78330040, 0x2100b2ca, 0xf009b240, 0xf242fe89, 0x06c80170, 0xf8bdf7ef, 
+    0xe0174655, 0x78330040, 0x21012203, 0xe7f0b240, 0xf7f62002, 0x2801f9fb, 0x4ddad009, 0xf0174628, 
+    0xf440f9a1, 0x46287180, 0xf99ff017, 0xf7f5e005, 0x8028fb6b, 0x28008828, 0xf999d1ea, 0xf8cd0000, 
+    0x28038000, 0xb2c2d012, 0x78337838, 0xeb042100, 0xb2400040, 0xfe58f009, 0x1000f9bb, 0x42a0f04f, 
+    0x4ff8e8bd, 0x0000f640, 0xb8c9f7ef, 0x22037838, 0x00407833, 0xb2402101, 0xe92de7ec, 0x24004ff8, 
+    0xf8ecf009, 0x48c149c0, 0xff80f016, 0xd01a2801, 0x0400f640, 0x462021e2, 0xf863f7ef, 0x46202100, 
+    0xf84ef7ef, 0x01d0f242, 0xf7ef4620, 0x48b8f866, 0x28017800, 0x2100d07e, 0xe8bd48b6, 0xf2014ff8, 
+    0xf017312e, 0x4eaab952, 0xf7fe7830, 0x4daff923, 0x79e849b1, 0x00c0f3c0, 0x28007008, 0xf242d06b, 
+    0x06c80170, 0xf849f7ef, 0xf7f62000, 0xf44ffe35, 0xf6403000, 0xf7ef0103, 0xf7fcf834, 0x7a29fe02, 
+    0x7a684fa6, 0x0103f001, 0x2001ea40, 0x80382840, 0x2002d951, 0xf974f7f6, 0x48a14601, 0x8288f8df, 
+    0x1a436800, 0xf9b1499f, 0xfbb32000, 0x1cc9f1f2, 0x1000f8c8, 0x43511e89, 0xf9b0f7f6, 0x25014885, 
+    0xb214f8df, 0xf8df462a, 0x7005a214, 0xf8b88839, 0xf04f0000, 0x1a080800, 0x0000f8ab, 0x8000f8cd, 
+    0xf8da4629, 0x46283008, 0xfaf2f7f5, 0x497d4f7c, 0x78384a80, 0x487c7008, 0x7800497c, 0x68097038, 
+    0xd9222910, 0x4b7c7811, 0xc1f0f8df, 0xd1142905, 0x29017831, 0xf8dfd006, 0xf89ee1e8, 0xea51e000, 
+    0xd10a010e, 0x294b7819, 0xf89cd907, 0x29011000, 0xe001d103, 0xe04de057, 0x78191e8c, 0xd204290f, 
+    0x1000f89c, 0xd1002901, 0xf9921e64, 0x46911000, 0x29039500, 0xeb04d009, 0x78330040, 0x2100b2ca, 
+    0xf009b240, 0x465dfd91, 0x0040e017, 0x22037833, 0xb2402101, 0x2002e7f5, 0xf908f7f6, 0xd0092801, 
+    0x46284d60, 0xf8aef017, 0x0180f040, 0xf0174628, 0xe005f8ac, 0xfa78f7f5, 0x88288028, 0xd1ea2800, 
+    0x0000f999, 0x8000f8cd, 0xd0152803, 0x7838b2c2, 0x21007833, 0x0040eb04, 0xf009b240, 0xf9bafd65, 
+    0xf04f1000, 0x465442a0, 0x0000f640, 0xffd7f7ee, 0x80202007, 0x8ff8e8bd, 0x22037838, 0x00407833, 
+    0xb2402101, 0xf242e7e9, 0xe7257110, 0x41f0e92d, 0xfff4f008, 0x48454944, 0xfe88f016, 0x28014e44, 
+    0x0500f640, 0x21e2d017, 0xf7ee4628, 0x2100ff6a, 0xf7ee4628, 0xf242ff55, 0x462801d0, 0xff6df7ee, 
+    0x28017830, 0x2100d03f, 0xe8bd483a, 0xf50141f0, 0xf017714b, 0x482eb85a, 0xf7fe7800, 0x4c27f82b, 
+    0x42a0f04f, 0xf9b44628, 0xf7ee1000, 0x482fff98, 0x0702f04f, 0x4d364a35, 0x09c87901, 0xd0017010, 
+    0xb1387830, 0x28017830, 0x2004d11b, 0xfeaaf00b, 0xe0157028, 0x1002f3c1, 0x7008492e, 0xf00b2004, 
+    0xb2c0fea1, 0x78317028, 0x492bb951, 0x1c8a7809, 0xd9014290, 0xe003702a, 0x42881e89, 0x7029da00, 
+    0xe8bd8027, 0xf24281f0, 0xe7bd7110, 0xe92d480f, 0x680043f8, 0xd3042812, 0xf44f2100, 0xf7f61080, 
+    0x491ef8a7, 0x4e0a2001, 0x4c042700, 0x78307008, 0xe0352801, 0x000301ff, 0x00030206, 0x0003048c, 
+    0x000301e9, 0x000301ea, 0x000301e7, 0x000301cc, 0x00030394, 0x00030222, 0x0003031e, 0x00030305, 
+    0x00030312, 0xd003517c, 0x0002b8b0, 0x0003112c, 0x0003031c, 0xd03c80b8, 0x00030200, 0x00030208, 
+    0x00030210, 0x000303a4, 0x0003032c, 0x000301f2, 0x000301e5, 0x000301eb, 0x000301e6, 0x000301de, 
+    0x2802d00f, 0x60a7d00d, 0x97002200, 0x68a32001, 0xf7f54611, 0x48faf9bd, 0x780049fa, 0xe8bd7008, 
+    0x4df983f8, 0x83e4f8df, 0x28057828, 0x2201d105, 0x21024640, 0xffe1f016, 0x7828b940, 0xd1072804, 
+    0x46402200, 0xf0162101, 0xb108ffd8, 0xe0002001, 0x01c02000, 0x783060a0, 0xd0012801, 0xe01a68a0, 
+    0x78284eea, 0x28053e3c, 0x2206d105, 0x21404630, 0xffc3f016, 0x7828b940, 0xd1072804, 0x46302205, 
+    0xf0162120, 0xb108ffba, 0xe0002001, 0x68a12000, 0x1040ea41, 0x020060a0, 0xe7b560a0, 0x4ff8e92d, 
+    0x8e804604, 0xf2404dda, 0xf5b01b1d, 0xd07d7f80, 0x28d3dc1b, 0xdc0fd038, 0x28a4b368, 0x28a5d03f, 
+    0x28d2d047, 0x6868d173, 0xf1052200, 0xf012010c, 0x1d40ffd8, 0xe027d06c, 0xd06a28e4, 0xd02328e5, 
+    0xd06728ec, 0xd16228ed, 0x4558e01e, 0x111df2a0, 0xdc11d01a, 0x001cf111, 0x2813d016, 0x2814d07c, 
+    0x281bd012, 0x49c2d153, 0x68682200, 0xf012310c, 0x1d40ffb8, 0xe007d071, 0xd06f2907, 0xd0032908, 
+    0xd06c2911, 0xd1422912, 0xf04f49b9, 0x686832ff, 0xf012310c, 0x1d01ffd5, 0x20a4d107, 0x49b4e150, 
+    0x68682200, 0xf012310c, 0x1d41ffcb, 0x2801d03b, 0x4eafd1ea, 0xf6402700, 0x360c0000, 0x1000f9b6, 
+    0xd032290f, 0x82acf8df, 0xf04f2913, 0xf04f42a0, 0xf04f0901, 0xd02e0a03, 0xd1d5290a, 0x1000f9b5, 
+    0xd05a2901, 0xd07b2903, 0xd0752902, 0xd0742904, 0xd0732905, 0xd0722906, 0xd1c52907, 0xf944f000, 
+    0x8030200b, 0x80282009, 0xe0041e7a, 0xe0eee0ab, 0xe056e041, 0x4898e079, 0x68004631, 0xff61f012, 
+    0xd0711d01, 0x20a5e108, 0xf04fe10a, 0xf7ee4225, 0x802ffe36, 0x4b8ce7a8, 0x3000f993, 0xd0032b03, 
+    0xd0012b05, 0xd1022b04, 0x781b4b8c, 0x210ab143, 0xf7ee802f, 0xe797fe24, 0xe0c6e0a6, 0xe0e4e0d7, 
+    0x4220f04f, 0xfe1bf7ee, 0xfeb0f7ff, 0x0000f898, 0xf8a5b170, 0x200a9000, 0x2200497d, 0x68688030, 
+    0xf012310c, 0x1d01ff2e, 0xaf53f47f, 0xe0d720d2, 0xa000f8a5, 0x20d3e7ef, 0xf7ffe0d2, 0x2002fe37, 
+    0xff04f7f5, 0x200ab108, 0x200fe000, 0x80304970, 0x68682200, 0xf012310c, 0x1d01ff14, 0x20e4d107, 
+    0x496be0be, 0x68682200, 0xf012310c, 0x1d40ff0a, 0x20e5d1b0, 0xe003e0b4, 0xe04fe021, 0xe087e06f, 
+    0xf936f000, 0xf7f52002, 0xb108fee1, 0xe000200a, 0x495f200f, 0x22008030, 0x310c6868, 0xfef1f012, 
+    0xd1081d01, 0xe09b20ec, 0x4959e08c, 0x68682200, 0xf012310c, 0x1d40fee6, 0x20edd18c, 0xf7eee090, 
+    0x4957fdbe, 0x46102201, 0x9000f881, 0xf8814955, 0x21009000, 0x68ab9700, 0xf85af7f5, 0x0000f898, 
+    0xd00a2801, 0x80282004, 0x22004949, 0x310c6868, 0xfec7f012, 0xd0031d01, 0xf8a5e00b, 0xe7f3a000, 
+    0x1000f240, 0x4942e06c, 0x68682200, 0xf012310c, 0x1d40feb8, 0xf240d1ac, 0xe0611001, 0xf8aff000, 
+    0x0000f898, 0xd00a2801, 0x49392005, 0x22008028, 0x310c6868, 0xfea5f012, 0xd0021d01, 0x2006e00a, 
+    0xf240e7f3, 0xe04b1014, 0x22004931, 0x310c6868, 0xfe97f012, 0xd18b1d40, 0x1015f240, 0xf7ffe040, 
+    0x2002fcac, 0xfe72f7f5, 0x200ab108, 0x200fe000, 0x80304927, 0x68682200, 0xf012310c, 0x1d01fe82, 
+    0xaec7f47f, 0x101cf240, 0xf8a4e02a, 0xe581b034, 0xfbf6f7ff, 0x2007491e, 0x22008028, 0x310c6868, 
+    0xfe6ff012, 0xd1081d01, 0x1024f240, 0x4918e018, 0x68682200, 0xf012310c, 0x1d40fe64, 0xf240d1aa, 
+    0xe00d1025, 0x102ef240, 0x4813e00a, 0x49102200, 0x6800310c, 0xfe55f012, 0xd19b1d40, 0x102ff240, 
+    0xe55786a0, 0x21012200, 0xf2afb510, 0xf012304f, 0x2108fc93, 0xf0122003, 0x4905fdf1, 0xbd106048, 
+    0x000301eb, 0x000301ec, 0x00030222, 0xd28e007c, 0x0003048c, 0x0003031c, 0x000304ec, 0x00030284, 
+    0x000301f1, 0x000301ed, 0xf04f4855, 0xb51042a0, 0x0400f640, 0x1000f9b0, 0xf7ee4620, 0xf240fd00, 
+    0x46202101, 0xfcadf7ee, 0x2400484e, 0x49504a4f, 0x808480c4, 0x80048044, 0x7803484b, 0xf7f74849, 
+    0x2172fe4f, 0x0080f44f, 0xfcc3f7ee, 0x21004849, 0xf44f7004, 0xe8bd3080, 0xf7f54010, 0xb5f8be29, 
+    0xf6404d3f, 0xf04f0600, 0x463042a0, 0x1000f9b5, 0xfcd5f7ee, 0x463010b1, 0xfc83f7ee, 0x2001493e, 
+    0x22014c3f, 0x46117008, 0x7800483c, 0x20007020, 0x46109000, 0xf7f468ab, 0x4d3aff6b, 0x4f3a2203, 
+    0x46382138, 0xf016782b, 0x7823fd8a, 0x21072200, 0xf0164638, 0x7821fd84, 0xf7ee4630, 0x7829fc51, 
+    0xf7ee4630, 0xe8bdfc4d, 0x483040f8, 0xbde9f7f7, 0x41f0e92d, 0xfcd2f008, 0x482e492d, 0xfb66f016, 
+    0x28014c2d, 0x0600f640, 0x21e2d017, 0xf7ee4630, 0x2100fc48, 0xf7ee4630, 0xf242fc33, 0x463001d0, 
+    0xfc4bf7ee, 0x28017820, 0x2100d026, 0xe8bd4823, 0xf20141f0, 0xf016312d, 0x4813bd38, 0xf7fd7800, 
+    0x4d1cfd09, 0x09c179a8, 0x7001481d, 0x4f0cd011, 0x42a0f04f, 0xf9b74630, 0xf7ee1000, 0x490ffc70, 
+    0xf3c079a8, 0x70081002, 0x28017820, 0x2001d002, 0xe4f68038, 0xe7fb2004, 0x7110f242, 0x0000e7d6, 
+    0x0003048c, 0x00030350, 0x00030394, 0x00030338, 0x00030366, 0x0003036e, 0x000301ef, 0x000301e6, 
+    0x000301e7, 0x000301e5, 0xd003501a, 0x00030348, 0x0002b8b0, 0x0003112c, 0x0003031c, 0xd03c80b8, 
+    0x000301ee, 0x41fce92d, 0xf04f48ff, 0xf9b042c0, 0xf2411002, 0xf7ee0000, 0x49fcfc32, 0x22012000, 
+    0x70084603, 0x90004611, 0xf7f44610, 0x4cf8fed1, 0x0800f640, 0x78214640, 0xfd6af7f5, 0x0680f242, 
+    0x06374631, 0xf7ee4638, 0x4df2fbd8, 0x1000f995, 0xd02b2905, 0xd0292903, 0x2007b111, 0xf8caf003, 
+    0x46407821, 0xfd54f7f5, 0x46384631, 0xfbc5f7ee, 0x4cea48e9, 0x28116800, 0x7820d80c, 0xd1092801, 
+    0xf8ad2047, 0x48e60000, 0x1000f995, 0x46686802, 0xf87ef011, 0x28007820, 0xf7fcd121, 0x48e1fc28, 
+    0x0000f990, 0x41fce8bd, 0xb98ff7fc, 0xd0022905, 0xd0072903, 0x204de00c, 0x0000f8ad, 0xf0114668, 
+    0xe005fa48, 0xf8ad204a, 0x46680000, 0xfe95f010, 0xf0032007, 0x7821f88f, 0xf7f54640, 0xe8bdfd19, 
+    0xe92d81fc, 0x48d04ff8, 0x49c82400, 0x70044dc9, 0x70082001, 0x0000f995, 0x2140b138, 0x80314ecb, 
+    0x780949cb, 0xd0032904, 0xf240e014, 0xe7f52100, 0x2020b180, 0x11f4f240, 0x04c78030, 0xf7ee4638, 
+    0xf64bfb60, 0x463831ba, 0xfb4af7ee, 0x463849c1, 0xfb46f7ee, 0x780048c0, 0xd1012802, 0x803001c0, 
+    0x68304eb5, 0xd8022810, 0xf7f62000, 0x2201f945, 0x23009400, 0x46104611, 0xfe3af7f4, 0x20002101, 
+    0xfdf6f7f6, 0xf7f4200f, 0xf04ffe18, 0xf2424900, 0x46390780, 0xf7ee4648, 0x2002fb40, 0xfc80f7f5, 
+    0xf9954604, 0x28050000, 0x2803d01c, 0x2000d01a, 0xf811f008, 0xf7f52002, 0x4aa8fc73, 0xf8df1a21, 
+    0x4ca78268, 0x7a127a50, 0x0203f002, 0x2002ea40, 0x2004f8d8, 0xeba01a89, 0x80203011, 0xf7f62000, 
+    0xe009f90b, 0xf0082001, 0xe7e3f86e, 0xf0082000, 0x8820f86a, 0x80201e40, 0x28018820, 0x4639d8f6, 
+    0x4648464c, 0xfb09f7ee, 0x28116830, 0x2003d803, 0xfb9ef00a, 0x2004e002, 0xfb9cf00a, 0x463946ba, 
+    0x462046a1, 0xfaf9f7ee, 0xf7f42001, 0xf995fdc6, 0x28050000, 0x2803d001, 0x4f8ad114, 0x24002500, 
+    0x1605eb07, 0x46284621, 0xf00a5732, 0x1c64fd5a, 0x2c10b2e4, 0x1c6dd3f6, 0x2d04b2ed, 0x2003d3ef, 
+    0xfd60f00a, 0x46484651, 0xfad7f7ee, 0x1002f9b8, 0x42c0f04f, 0x4ff8e8bd, 0x0000f241, 0xbb0ff7ee, 
+    0x4ff8e92d, 0xf9964e6b, 0xb1280000, 0x49702420, 0x29047809, 0xe012d002, 0xe7f82440, 0x2410b178, 
+    0x11f4f240, 0x46280525, 0xfaabf7ee, 0x31baf64b, 0xf7ee4628, 0x4967fa95, 0xf7ee4628, 0xf8dffa91, 
+    0xf8999198, 0x28020000, 0x2440d100, 0x0000f996, 0xd0352805, 0xd0332803, 0xf0072000, 0x4962ff7c, 
+    0xf016485e, 0x2801f9a3, 0x4c60d02e, 0x0500f241, 0x682021e2, 0x60201c40, 0xf7ee4628, 0x6821fa82, 
+    0xf7ee4628, 0xf242fa6d, 0x462801d0, 0xfa85f7ee, 0x7800484a, 0xd07d2801, 0x48552100, 0x714cf501, 
+    0xfb73f016, 0x49544853, 0xf0007800, 0xeb000007, 0xf8511000, 0x1c522020, 0x2020f841, 0x8ff8e8bd, 
+    0xf0072001, 0xe7caffc0, 0x494c4f44, 0xf3c079f8, 0x70080040, 0xd0f12800, 0x4d417a39, 0xf0017a78, 
+    0xea400103, 0x42a02001, 0xdde78028, 0xf7f52002, 0x4601fb97, 0x4c444842, 0x1a436800, 0xf9b14941, 
+    0xfbb32000, 0x1cc9f1f2, 0x1e896021, 0xf7f54351, 0x4926fbd5, 0x22012001, 0x88287008, 0x1a408821, 
+    0x8008492a, 0x46032000, 0x90004611, 0xf7f44610, 0x2101fd1f, 0xf7f62000, 0xf7f7fcdb, 0x200ffc7e, 
+    0xfcfbf7f4, 0x4a00f04f, 0x0b80f242, 0x46504659, 0xfa23f7ee, 0xb9607830, 0x21004c1a, 0xf994200c, 
+    0xf7f72000, 0x2101fc71, 0x2000f994, 0xf7f74608, 0x2002fcb1, 0xfb54f7f5, 0xf9964604, 0x28050000, 
+    0x2803d052, 0x2000d050, 0xfee5f007, 0xf7f52002, 0xe000fb47, 0x7a3ae0a0, 0x7a791a20, 0x0203f002, 
+    0xea414f01, 0xe0312102, 0x000304a0, 0x00030201, 0x00030223, 0x00030c58, 0x000301cc, 0x0003031c, 
+    0x00030c78, 0x00030227, 0x000301ff, 0x00030206, 0x00030222, 0xdcba01f5, 0x0003036e, 0x0003112c, 
+    0x00030208, 0x0003cdcc, 0x0002b8b0, 0x0003027c, 0xd03c80b8, 0x00030c74, 0x00037aec, 0x00030202, 
+    0x00030210, 0x000303a4, 0x0003032c, 0x1a80687a, 0x3010eba1, 0x0103f640, 0xf44f8028, 0xf7ee3000, 
+    0xf7fbf9b0, 0xe009ff7e, 0xf0072001, 0xe7adff0c, 0xf0072000, 0x8828ff08, 0x80281e40, 0x28018828, 
+    0x465cd8f6, 0x46554659, 0xf7ee4650, 0x2004f9a6, 0xfa40f00a, 0x46284621, 0xf99ff7ee, 0xf7f42001, 
+    0xf996fc6c, 0x28050000, 0x2803d001, 0xf8dfd115, 0x25008438, 0xeb082400, 0x46211605, 0x57324628, 
+    0xfbfff00a, 0xb2e41c64, 0xd3f62c10, 0xb2ed1c6d, 0xd3ef2d04, 0xf00a2003, 0xf899fc05, 0x28020000, 
+    0x0400d10b, 0x0103f640, 0xf96bf7ee, 0xff39f7fb, 0xf01648fe, 0x49fefa61, 0x46596008, 0xf7ee4650, 
+    0xf9b7f96c, 0xf04f1002, 0xf24142c0, 0xf7ee0000, 0x200bf9a6, 0xe6f18078, 0x7110f242, 0xe92de6dd, 
+    0x4ff45ff0, 0xf9972500, 0x28050000, 0x2803d00c, 0x2001d00a, 0xfe2ff007, 0x24014eef, 0x93bcf8df, 
+    0x28017830, 0xe02ad004, 0xf0072001, 0xe7f3fe9c, 0xbb207838, 0xf7f748ea, 0x48eafa22, 0x780049e8, 
+    0xd1102803, 0xf99048e8, 0xf9902000, 0xf8513002, 0xf8412022, 0xf9902023, 0xf9902001, 0xf8510003, 
+    0xf8412022, 0x4ae12020, 0xf8512000, 0x42933020, 0x2400d900, 0xb2c01c40, 0xd3f62804, 0x49dcb12c, 
+    0xf01648dc, 0x2801f823, 0x4cdbd008, 0x1c406820, 0xf3c06020, 0x28010008, 0xe0d6d07e, 0x8354f8df, 
+    0xf89849d6, 0xf3c00007, 0x70080080, 0xd0742800, 0xf89849d3, 0x4bd50009, 0xb354f8df, 0x700a0982, 
+    0xf3c049d0, 0xf8df1201, 0x700aa34c, 0x0181f3c0, 0xf0004acd, 0x70110003, 0xf89b7018, 0x42a14000, 
+    0xf89ad103, 0x42a04000, 0x1e40d06d, 0x07801e49, 0x0603f001, 0x100af898, 0x20810f04, 0xd1012980, 
+    0x000af888, 0x100bf898, 0xd1012980, 0x000bf888, 0x100cf898, 0xd1012980, 0x000cf888, 0x100df898, 
+    0xd1012980, 0x000df888, 0x0000f997, 0xd0222805, 0xd0202803, 0x000af898, 0x42404621, 0x4630b242, 
+    0xfb2ff00a, 0x000bf898, 0x42401c61, 0x4630b242, 0xfb27f00a, 0x000cf898, 0x42401ca1, 0x4630b242, 
+    0xfb1ff00a, 0x000df898, 0x42401ce1, 0x4630b242, 0xfb17f00a, 0xf898e016, 0x4241000a, 0xeb004892, 
+    0x55011006, 0xf8984420, 0x4249100b, 0xf8987041, 0x4249100c, 0xe0017081, 0xe03ee048, 0x100df898, 
+    0x70c14249, 0x78184b9c, 0xd00c2801, 0x25014896, 0x48967801, 0x1000f88b, 0xf88a7800, 0x43010000, 
+    0x2001d101, 0x4f957018, 0x28017838, 0x488cd021, 0x78004c93, 0x42887821, 0x4a8ad11b, 0x78134e91, 
+    0x42937832, 0x4318d115, 0x1c52d007, 0x7030b2d0, 0x28042200, 0x7032d304, 0x2001e00d, 0xe00a7038, 
+    0xd1082801, 0xb2c81c49, 0x28047020, 0x7022d303, 0x2d00e001, 0x2107d008, 0x487fe004, 0x28007800, 
+    0x2108d002, 0x1002f8a9, 0x9ff0e8bd, 0x0500f241, 0x462821e2, 0xf835f7ee, 0x46286821, 0xf820f7ee, 
+    0x01d0f242, 0xf7ee4628, 0x7830f838, 0xd01c2801, 0x48752100, 0x312ff201, 0xf927f016, 0x49744873, 
+    0xf0007800, 0xeb000007, 0xf8511000, 0x1c522020, 0x2020f841, 0x28007838, 0x6820d1d6, 0xdbd3280a, 
+    0x28017830, 0x2110d1d0, 0xf242e7cc, 0xe7e07110, 0xf04f4852, 0xb5f842c0, 0x1002f9b0, 0x0000f241, 
+    0xf84df7ee, 0x25004e4b, 0xb1687830, 0x0180f242, 0xf7ee0608, 0x485df802, 0x7800495d, 0x0007f000, 
+    0x1000eb00, 0x5020f841, 0x2001495a, 0x70084c5b, 0x70084959, 0x700d494e, 0x700d494e, 0x70084950, 
+    0x70084950, 0x0000f996, 0xd0342805, 0xd0322803, 0xf0082000, 0x4621f8c9, 0xf7f3b240, 0x2001fe5f, 
+    0xf8c2f008, 0x0110f104, 0xf7f3b240, 0x2002fe57, 0xf8baf008, 0x0120f104, 0xf7f3b240, 0x2003fe4f, 
+    0xf8b2f008, 0x0130f104, 0xf7f3b240, 0x78e0fe47, 0x78a12201, 0xea400600, 0x78614001, 0x2301ea40, 
+    0x46117820, 0x43039500, 0xf7f44610, 0x7830faa1, 0xb1984c3b, 0xf8dfe01c, 0x2100c0ec, 0xeb0c2000, 
+    0xeb041701, 0x5c3b1201, 0x1c405413, 0x2810b200, 0x1c49dbf9, 0x2904b2c9, 0xe7d8d3f0, 0x0000f994, 
+    0xf7f3492e, 0x4a30fe1b, 0x482c2104, 0xff64f015, 0x0000f994, 0x40f8e8bd, 0xbc16f007, 0x43f0e92d, 
+    0xf241480e, 0xb0870900, 0x42c0f04f, 0x1002f9b0, 0xf7ed4648, 0xf7f7ffc4, 0xf242fc68, 0x06cf0150, 
+    0xf7ed4638, 0xe041ff7a, 0x0003cdcc, 0xc800012c, 0x00030370, 0x00030c58, 0x0003031c, 0x000304a0, 
+    0x0003113c, 0x00030394, 0x00030338, 0x0001a02b, 0x0002b8b0, 0x0003112c, 0x0003027c, 0x000301fd, 
+    0x000301f8, 0x000301f9, 0x000301fa, 0x000301fb, 0x000301f4, 0x000301f5, 0x0003020d, 0x0003020c, 
+    0x000301f6, 0x000301f7, 0xd03c80b8, 0x00030c74, 0x00037aec, 0x000301df, 0x000301fc, 0x00030fec, 
+    0x00030330, 0x0003319c, 0x0003102c, 0x260048fe, 0x0570f242, 0x0d387801, 0xd0132903, 0xf04f4cfb, 
+    0x7821020c, 0x46112903, 0x10c0d000, 0xfe9af7f5, 0x462946a8, 0x4638463d, 0xff1ff7ed, 0x78384ff4, 
+    0xe00db160, 0x96002300, 0x96011e5a, 0xf7f5210e, 0xf7fbfdd0, 0x4629fe85, 0xe0384638, 0xfe80f7fb, 
+    0x96042001, 0x0602e9cd, 0x9000200c, 0x96052301, 0x9001220e, 0x46110358, 0xff04f7f5, 0x46414646, 
+    0xf7ed4628, 0x7838fefa, 0xf994b9c8, 0x2a042000, 0x2a05d001, 0x48dfd113, 0xb9807800, 0x20012100, 
+    0xfbeff7f7, 0x21004cdc, 0xf994200c, 0xf7f72000, 0x2101f93b, 0x2000f994, 0xf7f74608, 0x2301f97b, 
+    0x4619220c, 0xf7f5200e, 0x4631ffae, 0xf7ed4628, 0x48d2fed4, 0x31b8f44f, 0xffc4f7f6, 0xd0102800, 
+    0x11f4f240, 0x4648464c, 0xfebbf7ed, 0x462049cc, 0xfea6f7ed, 0x4620b007, 0xe8bd49ca, 0xf7ed43f0, 
+    0xb007be9f, 0x83f0e8bd, 0xf04f48c7, 0xb51042c0, 0x1002f9b0, 0x0000f241, 0xfef1f7ed, 0x78204cbc, 
+    0xf004b908, 0xf005fa07, 0x7820fea3, 0xd1012801, 0xfa00f004, 0xfc94f7f7, 0x4010e8bd, 0xba57f004, 
+    0x4ff0e92d, 0xb0874cb8, 0x42c0f04f, 0x0000f241, 0x1002f9b4, 0xfed3f7ed, 0x78284dad, 0xd1102801, 
+    0x780148b2, 0x2080f44f, 0xf812f7f5, 0xf7f52000, 0xf44ffc73, 0xf6403000, 0xf7ed0103, 0xf7fbfe72, 
+    0xf04ffc40, 0xf2424a00, 0x46490980, 0xf7ed4650, 0x48a7fe74, 0x260c2701, 0x0800f04f, 0x28116800, 
+    0x7828d202, 0xd1112801, 0x96002301, 0xf8cd220d, 0x02588010, 0xe9cd4611, 0xf8cd7802, 0x96018014, 
+    0xfe60f7f5, 0x46504649, 0xfe57f7ed, 0x22002101, 0xf0054608, 0x7828fd99, 0xb1f046ab, 0x0000f994, 
+    0x220d2301, 0x46119600, 0x96019004, 0x7002e9cd, 0x02989005, 0xfe46f7f5, 0x46504649, 0xfe3df7ed, 
+    0x0000f994, 0x220e2301, 0x46119600, 0x96019004, 0x7002e9cd, 0x03589005, 0xf7fbe050, 0x4883fda1, 
+    0xf44f7801, 0xf7f43080, 0x2301ffb3, 0x220d9600, 0x02984645, 0xe9cd4611, 0xf8cd7802, 0xf8cd8010, 
+    0x96018014, 0xfe1ef7f5, 0x46504649, 0xfe15f7ed, 0xf241220e, 0x96000800, 0xe9cd2301, 0x46117502, 
+    0x95044640, 0x95059601, 0xfe0cf7f5, 0x46504649, 0xfe03f7ed, 0xfd74f7fb, 0x78004866, 0x7820b990, 
+    0x2100b180, 0xf7f72001, 0x4d63fafc, 0x200c2100, 0x2000f995, 0xf848f7f7, 0xf9952101, 0x46082000, 
+    0xf888f7f7, 0x0000f994, 0x9600220e, 0x46112301, 0x96019004, 0x7002e9cd, 0x46409005, 0xfde2f7f5, 
+    0x464946c8, 0x46504655, 0xfdd7f7ed, 0x20012200, 0xf0054611, 0x4641fd19, 0xf7ed4628, 0xf89bfdce, 
+    0xf04f0000, 0x46d9020e, 0x0301f04f, 0xf9942800, 0x96000000, 0x90044611, 0xe9cd9601, 0x90057002, 
+    0x0358d031, 0xfdbef7f5, 0x46414644, 0xf7ed4628, 0x4842fdb4, 0x3190f44f, 0xfea4f7f6, 0xf241b178, 
+    0xf2400600, 0x463011f4, 0xfd9bf7ed, 0x4630493c, 0xf7ed1c49, 0x493bfd85, 0xf7ed4630, 0x2301fd81, 
+    0x0000f899, 0x4619220c, 0xf7f5200e, 0x2100fe6c, 0x1000f44f, 0xff1cf7f4, 0x4621b007, 0xe8bd4628, 
+    0xf7ed4ff0, 0xf244bd8a, 0xe7cb0000, 0x5ff0e92d, 0xf04f4e2d, 0xf24142c0, 0xf9b60000, 0xf7ed1002, 
+    0xf04ffdbe, 0xf2424900, 0x46210470, 0xf7ed4648, 0x4f1ffd74, 0x080ef04f, 0x28017838, 0xf7f5d17e, 
+    0x4824fe91, 0x22112300, 0x3100f44f, 0xfe60f015, 0xf7f52001, 0x4820fb51, 0xfe4ef015, 0x6809491c, 
+    0xd8012910, 0xe000491d, 0xf8df2100, 0x46a2b06c, 0x1a454c16, 0x0b0cf1ab, 0x46484651, 0xfd4df7ed, 
+    0xf7f52000, 0xf008fb39, 0xb160f8b4, 0x4080f500, 0x10407821, 0xf863f7f6, 0x22014811, 0xf9b07823, 
+    0x20001000, 0xe026e01e, 0x00030214, 0x00030222, 0x0003031c, 0x00030c58, 0x00030227, 0x0003113c, 
+    0x77777771, 0xdcba01f5, 0x000304a0, 0x00030223, 0x000301cc, 0xd1800000, 0xc800012c, 0x01e84800, 
+    0x00030320, 0xf8f5f7f6, 0xf7f52001, 0x7821fb05, 0x2080f44f, 0x2001e005, 0xfafef7f5, 0xf44f7821, 
+    0xf7f43080, 0x2201fe95, 0x21024658, 0xfe0ef015, 0xd01a2801, 0x220048fb, 0xf0152101, 0x2801fe07, 
+    0x48f8d013, 0xf0153008, 0x42a8fde7, 0x2001d8a4, 0xfae2f7f5, 0xf44f7821, 0xe0002080, 0xf7f4e01a, 
+    0x7838fe77, 0xd00a2801, 0x4defe014, 0xf0154628, 0xf040fdd9, 0x46280110, 0xfdd7f015, 0xf007e7e7, 
+    0x49eafd4d, 0xf01548ea, 0x2801fbe1, 0x2010d002, 0xe4898070, 0x8002f8a6, 0xe92de486, 0x48e541f0, 
+    0x4de54ce6, 0x78207801, 0x2832b109, 0x7829d301, 0x2101b101, 0x4ee34fe2, 0x7039282d, 0x2000f996, 
+    0x2a04d201, 0x286ed006, 0x2a05d201, 0x2000d002, 0xe001b921, 0xe7fb2001, 0xd0522800, 0xf04f48da, 
+    0xf9b042c0, 0xf2411002, 0xf7ed0000, 0x2000fce8, 0xfa92f7f5, 0x780048d5, 0xf44fb938, 0xf6403000, 
+    0xf7ed0103, 0xf7fbfc8e, 0x7838fa5c, 0xd0062801, 0x0000f996, 0xd0112804, 0xd01b2805, 0x7828e021, 
+    0x2801b130, 0x2802d004, 0x2803d002, 0xe018d003, 0xfb45f7fa, 0xf7fae015, 0xe012fb2d, 0x280f7820, 
+    0x2102d202, 0xe00a2006, 0x281e380f, 0x2102d209, 0xe0042000, 0x280f7820, 0x2102d20f, 0xf7f92001, 
+    0x2101fd27, 0x46082200, 0xfbaef005, 0x41f0e8bd, 0xf44f2100, 0xf7f42080, 0x380fbdeb, 0xd3e6285f, 
+    0xe8bde7ef, 0xb53881f0, 0xf04f4caf, 0xf24142c0, 0xf9b40000, 0xf7ed1002, 0x49adfc92, 0x4aad2000, 
+    0x70084603, 0x70112102, 0x46112201, 0x46109000, 0xff2ef7f3, 0x49a848a5, 0xf9917800, 0x43081000, 
+    0x2000d00f, 0xf6407020, 0x60603040, 0xf990489d, 0x28040000, 0x2805d007, 0xf241d102, 0x60606080, 
+    0x2001bd38, 0xf642e7ee, 0xe7f85000, 0x5ff0e92d, 0xf2404d95, 0x8e811b53, 0xf8df4604, 0x4559a260, 
+    0xf2a168ab, 0xd03d1053, 0xf5b1dc4c, 0xd0757f93, 0xf240dc20, 0x42911207, 0x1007f2a1, 0xdc10d078, 
+    0x29d8b381, 0x29d9d06b, 0xf5b1d06a, 0xd1687f83, 0x46182200, 0x010cf105, 0xfd63f011, 0xd0721d40, 
+    0x2811e066, 0x2812d070, 0x2819d062, 0x281ad06d, 0xe05dd157, 0x1233f240, 0xf2a14291, 0xd0571033, 
+    0xf110dc11, 0xd053010c, 0xd07d2905, 0xd04f2906, 0xd146290b, 0x22004974, 0x310c4618, 0xfd41f011, 
+    0xd0721d40, 0x2805e044, 0x2806d070, 0x281fd040, 0x496dd137, 0x46182200, 0xf011310c, 0x1d40fd32, 
+    0xe035d07e, 0xd0332846, 0x2829dc1c, 0xdc08d079, 0xd0772807, 0xd02b2808, 0xd074281f, 0xd1202820, 
+    0x282ae026, 0x2831d024, 0x2832d06e, 0x2845d020, 0x495dd117, 0x46182200, 0xf011310c, 0x1d40fd12, 
+    0xe015d07d, 0xd07b2869, 0x2859dc0c, 0x285ad079, 0x2861d00e, 0x2862d076, 0xe009d103, 0xe015e13f, 
+    0xe071e01e, 0xd003286a, 0xd06c2873, 0xd16b2874, 0xf04f494d, 0x68a832ff, 0xf011310c, 0x1d01fd21, 
+    0x20d8d10a, 0xe0cbe282, 0xe112e0dc, 0x22004946, 0x310c4618, 0xfd14f011, 0xd05b1d41, 0xd1e72801, 
+    0x27004e41, 0x0000f241, 0xf9b6360c, 0x290f1000, 0x4b3cd052, 0xf8df2914, 0xf04f8108, 0xf04f42c0, 
+    0xd04f090a, 0xe002290a, 0xe139e11f, 0xd1cfe147, 0x1002f9b5, 0xd0772913, 0x29014f34, 0x2902d075, 
+    0x2910d074, 0x2911d073, 0x2912d072, 0x2903d071, 0x290ed070, 0x290fd06f, 0xf04fd06f, 0xe0040806, 
+    0xe19de149, 0xe183e158, 0x2904e1b8, 0x2906d07d, 0x2907d07c, 0x2908d07b, 0x2909d07a, 0x270bd079, 
+    0xd077290a, 0xd1a3290b, 0xff3cf7fe, 0x200c8037, 0xf04f8068, 0xf8da32ff, 0x46310000, 0xe1c1e005, 
+    0xe1d7e20d, 0xe217e1f4, 0xf011e127, 0x1d01fc8a, 0xe217d077, 0xe21920d9, 0x4226f04f, 0xfb5ff7ed, 
+    0xe785806f, 0x3000f993, 0xd0032b03, 0xd0012b05, 0xd1022b04, 0x781b4b13, 0x210db373, 0xf7ed806f, 
+    0xe775fb4e, 0xc8000124, 0xd003517c, 0x0002b8b0, 0x0003112c, 0x0003028c, 0x0003028d, 0x0003031e, 
+    0x000302d5, 0x00030222, 0x000304a0, 0x0003031c, 0x000301ff, 0x000301de, 0x00030c58, 0x000304ec, 
+    0x00030214, 0x00030284, 0xe045e02d, 0xe090e07b, 0xe0b8e0a5, 0xe0e1e0cd, 0xe0f7e000, 0x4220f04f, 
+    0xfb1df7ed, 0xfe7ff7ff, 0x0000f898, 0xd0152803, 0x80682013, 0x9000f8a6, 0x49fe2200, 0xf01168a8, 
+    0x1d01fc30, 0xaecaf47f, 0xe10be005, 0xe13fe122, 0xe179e15b, 0xf240e196, 0xe1b71006, 0xe7e8200e, 
+    0x1007f240, 0xf7ffe1b2, 0x2001fde8, 0x49f18068, 0x68a82200, 0xfc15f011, 0xd1081d01, 0x1018f240, 
+    0xe196e1a4, 0x220049eb, 0xf0114618, 0x1d40fc0a, 0xf240d187, 0xe1991019, 0xfae1f7ed, 0x0170f242, 
+    0x463006ce, 0xfa99f7ed, 0x0bf02100, 0xfc20f7f4, 0x28017838, 0x2100d103, 0xf7f40500, 0xf242fc19, 
+    0x46300180, 0xfa89f7ed, 0x221e49db, 0xf7fc48db, 0x7838fdea, 0xf7fbb908, 0x2002f9f3, 0x49d58068, 
+    0x68a82200, 0xfbddf011, 0xd1071d01, 0x1020f240, 0x49d0e16c, 0x46182200, 0xfbd3f011, 0xd1c71d40, 
+    0x1021f240, 0xf7ffe162, 0x49cafce1, 0x68a82200, 0xfbc7f011, 0xd1071d01, 0x1026f240, 0x49c5e156, 
+    0x46182200, 0xfbbdf011, 0xd1b11d40, 0x1027f240, 0xf000e14c, 0x49bffa14, 0x68a82200, 0xfbb1f011, 
+    0xd1071d01, 0x102cf240, 0x49bae140, 0x46182200, 0xfba7f011, 0xd19b1d40, 0x102df240, 0xf7ede136, 
+    0xf004fa7e, 0x2012f851, 0x49b28068, 0x68a82200, 0xfb97f011, 0xf47f1d01, 0xf240ae53, 0xe1251032, 
+    0x1033f240, 0xf000e122, 0x49aaf9ca, 0x68a82200, 0xfb87f011, 0xd1071d01, 0x1038f240, 0x49a5e116, 
+    0x46182200, 0xfb7df011, 0xd1a81d40, 0x1039f240, 0x7818e10c, 0xd1012803, 0xfb72f7ff, 0x80682004, 
+    0x2200499c, 0xf01168a8, 0x1d01fb6c, 0xae37f47f, 0x1052f240, 0xf8a4e0fa, 0xe52ab034, 0xfb44f7ff, 
+    0x8068200f, 0x22004993, 0xf01168a8, 0x1d01fb5a, 0xf240d107, 0xe0e9105a, 0x2200498e, 0xf0114618, 
+    0x1d40fb50, 0xf240d191, 0xe0df105b, 0xfa56f7ff, 0x0000f898, 0xd0092803, 0x80682003, 0x22004985, 
+    0xf01168a8, 0x1d01fb3e, 0xe016d00f, 0xf7f42002, 0x4883fb08, 0xf44f7801, 0xf7f41080, 0x2000fb59, 
+    0xffbaf7f4, 0xfc76f00a, 0xf240e632, 0xe0bd1072, 0x22004978, 0xf0114618, 0x1d40fb24, 0xf240d1f4, 
+    0xe0b31073, 0xf9a4f7ff, 0x8002f8a5, 0x49712200, 0xf01168a8, 0x1d01fb16, 0xf240d107, 0xe0a5107c, 
+    0x2200496c, 0xf0114618, 0x1d40fb0c, 0xf240d1dc, 0xe09b107d, 0xf843f7ff, 0xf7f42002, 0xb108fae7, 
+    0xe000200a, 0x8030200f, 0x22004962, 0xf01168a8, 0x1d01faf8, 0xf240d107, 0xe0871084, 0x2200495d, 
+    0xf0114618, 0x1d40faee, 0xf240d1be, 0xe07d1085, 0xf8ecf000, 0x7800485b, 0xd1032801, 0x7800485a, 
+    0xd00c2801, 0x8002f8a5, 0x49522200, 0xf01168a8, 0x1d01fad8, 0xadc3f47f, 0x1098f240, 0x2008e066, 
+    0xe7f18068, 0x1099f240, 0xf000e060, 0x7838f870, 0xd0092801, 0x80682009, 0x22004946, 0xf01168a8, 
+    0x1d01fac0, 0xe00ad003, 0x9002f8a5, 0xf240e7f4, 0xe04b10ac, 0x2200493f, 0xf0114618, 0x1d40fab2, 
+    0xf240d18c, 0xe04110ad, 0xfe7af7fe, 0xf7f42002, 0xb108fa8d, 0xe000200a, 0x8030200f, 0x22004935, 
+    0xf01168a8, 0x1d01fa9e, 0xf240d107, 0xe02d10b4, 0x22004930, 0xf0114618, 0x1d40fa94, 0xf240d186, 
+    0xe02310b5, 0xfd9df7fe, 0x2200806f, 0x68a84929, 0xfa87f011, 0xd1071d01, 0x10bcf240, 0x4925e016, 
+    0x46182200, 0xfa7df011, 0xd18d1d40, 0x10bdf240, 0xf240e00c, 0xe00910c6, 0x2200491e, 0x0000f8da, 
+    0xfa6ff011, 0xd1bb1d40, 0x10c7f240, 0xe43086a0, 0x21012200, 0xf2afb510, 0xf011604b, 0x2108f8ad, 
+    0xf0112003, 0x4913fa0b, 0x6088390c, 0x4811bd10, 0x42c0f04f, 0x380cb538, 0x0400f241, 0x1002f9b0, 
+    0xf7ed4620, 0x2104f92c, 0xf7ed4620, 0x490cf8da, 0x78094620, 0xfa6cf7f4, 0xf0092000, 0x480bfb21, 
+    0x0000f990, 0xd0042805, 0xd0022803, 0xf0092003, 0xe00dfb59, 0x000304ac, 0x450f6429, 0x43e187ae, 
+    0x00030223, 0x0003020c, 0x0003020d, 0x00030c58, 0x0180f242, 0xf7ed0608, 0x485bf8c0, 0x495b2400, 
+    0x70044d5b, 0x70082001, 0x2002e00e, 0xf9fef7f4, 0xd0092801, 0x46284d57, 0xf9a4f015, 0x0140f040, 
+    0xf0154628, 0xe006f9a2, 0x46282200, 0xf0152101, 0x2800f9ad, 0x2201d1e9, 0x23009400, 0x46104611, 
+    0xfb86f7f3, 0x4038e8bd, 0xbd40f006, 0xb538484a, 0x78004a4b, 0x1e404d46, 0x0103f000, 0xeb024847, 
+    0x78001201, 0x07801e40, 0x18110f00, 0x78cb5c10, 0x7849788c, 0xea43061b, 0xea434304, 0x43042401, 
+    0x2002e00e, 0xf9c2f7f4, 0xd0092801, 0x46284d39, 0xf968f015, 0x0120f040, 0xf0154628, 0xe006f966, 
+    0x46282200, 0xf0152101, 0x2800f971, 0x2001d1e9, 0x46024623, 0x90004601, 0xfb4af7f3, 0xb510bd38, 
+    0xf04f4c30, 0xf24142c0, 0xf9b40000, 0xf7ed1002, 0xf007f896, 0xb110fc12, 0x8060200e, 0x2010bd10, 
+    0x48298060, 0x78024929, 0x7842700a, 0x7882704a, 0x78c0708a, 0xe8bd70c8, 0xf0074010, 0xe92dbb81, 
+    0x4c2041f0, 0x42c0f04f, 0x0000f241, 0x1002f9b4, 0xf875f7ed, 0xf9c2f7fc, 0xf7f42000, 0x481cfe1d, 
+    0x0000f990, 0xd0031c40, 0x80602011, 0x81f0e8bd, 0xf2404d18, 0x4f182600, 0x0000f995, 0x17c11c40, 
+    0x7191eb00, 0x0103f021, 0x70281a40, 0x78282400, 0x4631b108, 0x4639e000, 0xf7fa4620, 0x1c64ffc8, 
+    0x2c04b264, 0xe7e1dbf3, 0x000301fc, 0x000301fe, 0xc800001c, 0xd003517c, 0x000301f6, 0x000301f7, 
+    0x00030fec, 0x000304a0, 0x00030338, 0x00030330, 0x0003020e, 0x00030322, 0xfffffa00, 0xf04f48ff, 
+    0xb5f842e0, 0x0400f242, 0x1006f9b0, 0xf7ed4620, 0x2107f826, 0xf7ec4620, 0x04a6ffd4, 0x05a0f242, 
+    0x46304629, 0xffd9f7ec, 0x220048f5, 0x70024613, 0x22019200, 0x46104611, 0xfabaf7f3, 0x46304629, 
+    0xffcbf7ec, 0xf9944cef, 0xb1222000, 0xd0082a02, 0xd0062a03, 0x2000e010, 0xfdaef7f4, 0x220c2301, 
+    0x2000e006, 0xfda8f7f4, 0x230148e7, 0x7800220d, 0x200e2101, 0xf887f7f5, 0x46304629, 0xffadf7ec, 
+    0xb9307820, 0x230048e1, 0xf244220e, 0xf0150100, 0x49dff8b6, 0x70082001, 0xe92dbdf8, 0x4ed94ff8, 
+    0x0a00f242, 0x28037830, 0xf240d113, 0x465411f4, 0xf7ec4650, 0xf243ff86, 0x46203199, 0xff70f7ec, 
+    0x462049d4, 0xff6cf7ec, 0x49d348d4, 0xf7f46800, 0x49cbf915, 0x27002001, 0x48d17008, 0xf9967007, 
+    0xb1380000, 0x4acf2140, 0x49cf8011, 0x29047809, 0xe005d003, 0x2100f240, 0xb108e7f5, 0x80102020, 
+    0x780048ca, 0xd1012802, 0x801001c0, 0x97002201, 0x46112300, 0xf7f34610, 0x2002fa4b, 0xfa2cf7f5, 
+    0x4800f04f, 0x0490f242, 0x46404621, 0xff55f7ec, 0xfe65f7f3, 0x80a84db1, 0xf82cf7f4, 0x28037830, 
+    0x201ed10c, 0xfa19f7f3, 0xf0082003, 0x48afffe1, 0x220e2300, 0x0100f244, 0xf851f015, 0xf7f32005, 
+    0x46a1fa0c, 0x46404621, 0xff37f7ec, 0xf0062001, 0x49affc8a, 0x4caf2301, 0xf8df461a, 0x7a48b2bc, 
+    0xf0017a09, 0xea400103, 0x80202001, 0x46582102, 0xf835f015, 0x46582300, 0x21022201, 0xf82ff015, 
+    0x46582301, 0x46192200, 0xf829f015, 0x2001e005, 0xfc69f006, 0x1e408820, 0x88208020, 0xd8f62801, 
+    0x7800489e, 0xd00b2801, 0x7800489d, 0xd0072801, 0xd0052802, 0xf0082005, 0x7830ff9d, 0xe00bb120, 
+    0xf0082006, 0xe7f8ff95, 0xb1287828, 0x1e912201, 0xf7f42005, 0x702ff84b, 0x4649464c, 0x46404646, 
+    0xfeebf7ec, 0x2301488c, 0x21102204, 0xf01430aa, 0x4889fff6, 0x220f2301, 0x30d403d9, 0xffeff014, 
+    0x1004f9b5, 0xf7f32000, 0xf9b5feb2, 0xf04f1006, 0x465042e0, 0xff13f7ec, 0x46304621, 0x4ff8e8bd, 
+    0xbecbf7ec, 0x4ff8e92d, 0xf2424e6e, 0x78300800, 0xd1132803, 0x11f4f240, 0x46404644, 0xfeb1f7ec, 
+    0x1199f241, 0xf7ec4620, 0x496afe9b, 0xf7ec4620, 0x486afe97, 0x68004968, 0xf840f7f4, 0xf0062001, 
+    0x4970fc02, 0xf014486a, 0x2801fdb1, 0x4c6ed029, 0x464521e2, 0x1c406820, 0x46406020, 0xfe91f7ec, 
+    0x46286821, 0xfe7cf7ec, 0x01d0f242, 0xf7ec4628, 0x4855fe94, 0x28017800, 0x2100d07e, 0xf2014863, 
+    0xf0143132, 0x4862ff82, 0xf0007800, 0xeb000007, 0x48601100, 0x0081eb00, 0x1c496841, 0xe8bd6041, 
+    0x4d538ff8, 0x79e8495c, 0x0001f010, 0xd0f67008, 0x1000f996, 0x2020b129, 0x78124a4b, 0xd0022a04, 
+    0x2040e003, 0xb101e7f8, 0x49482010, 0x29027809, 0x2040d100, 0x4c477a2a, 0xf0027a69, 0xea410203, 
+    0x42812102, 0xddda8021, 0xf7f32002, 0x4601ff99, 0xf8df484a, 0x68009130, 0x49491a43, 0x2000f9b1, 
+    0xf1f2fbb3, 0xf8c91cc9, 0x1e891000, 0xf7f34351, 0x492bffd5, 0x4a332001, 0x0a00f04f, 0x70084657, 
+    0xf880482f, 0x8821a000, 0x0000f8b9, 0x80111a09, 0x483db281, 0xff29f014, 0x97002201, 0x46112300, 
+    0xf7f34610, 0x2002f915, 0xf8f6f7f5, 0x4900f04f, 0x0b90f242, 0x46484659, 0xfe1ff7ec, 0xfd2ff7f3, 
+    0x80784f16, 0xfef6f7f3, 0x28037830, 0x201ed10e, 0xf8e3f7f3, 0xe0002003, 0xf008e0b3, 0x4813fea9, 
+    0x220e2300, 0x0100f244, 0xff19f014, 0xf7f32005, 0x4659f8d4, 0xf7ec4648, 0x2001fe00, 0xfb53f006, 
+    0x23017a29, 0x461a7a68, 0x0103f001, 0xea404d12, 0x80202001, 0x46282102, 0x0000e038, 0x000304b4, 
+    0x00030203, 0x00030c58, 0x0003031c, 0xd0030416, 0x000301e1, 0xdcba01f5, 0x0066ff30, 0x00030370, 
+    0x00030201, 0x00030206, 0x00030222, 0x0003036e, 0x0003112c, 0x00030208, 0xd003504c, 0x000302d7, 
+    0x00030394, 0x0002b8b0, 0x00030280, 0xd03c80b8, 0x00030c74, 0x00037aec, 0x00030204, 0x00030210, 
+    0x000303a4, 0x0003032c, 0xd003519a, 0xfec7f014, 0x46282300, 0x21022201, 0xfec1f014, 0x46282301, 
+    0x46192200, 0xfebbf014, 0x2001e005, 0xfafbf006, 0x1e408820, 0x88208020, 0xd8f62801, 0x780048fe, 
+    0xd00b2801, 0x780048fd, 0xd0072801, 0xd0052802, 0xf0082005, 0x7830fe2f, 0xe00cb120, 0xf0082006, 
+    0xe7f8fe27, 0xb1307838, 0x1e912201, 0xf7f32005, 0xf887fedd, 0x465ca000, 0x464d4659, 0xf7ec4648, 
+    0x48effd7c, 0x22042301, 0xf0142110, 0x48ecfe88, 0x220f2301, 0x302a03d9, 0xfe81f014, 0x1002f9b7, 
+    0xf7f32001, 0xf9b7fd44, 0xf04f1006, 0x464042e0, 0xfda5f7ec, 0x46284621, 0xfd5ff7ec, 0x80f82006, 
+    0xf242e6dd, 0xe6c97110, 0x2001b570, 0xfaabf006, 0x48dd49dc, 0xfc5af014, 0x28014edc, 0x0500f242, 
+    0x4cdbd026, 0x682021e2, 0x60201c40, 0xf7ec4628, 0x6821fd38, 0xf7ec4628, 0xf242fd23, 0x462801d0, 
+    0xfd3bf7ec, 0x28017830, 0x2100d032, 0xf20148d1, 0xf0143131, 0x48d0fe2a, 0xf0007800, 0xeb000007, 
+    0x48ce1100, 0x0081eb00, 0x1c496841, 0xbd706041, 0x79c048c5, 0x1140f3c0, 0x700148c9, 0x780048c9, 
+    0xd1f42801, 0xd0f22900, 0xf04f4cc7, 0x462842e0, 0x1006f9b4, 0xfd53f7ec, 0x46282106, 0xfd01f7ec, 
+    0x28017830, 0x2004d002, 0xbd7080e0, 0xe7fb2005, 0x7110f242, 0xe92de7ca, 0x4fbb4ff0, 0xf04fb087, 
+    0xf24242e0, 0xf9b70000, 0xf7ec1006, 0x4cb7fd38, 0x0b01f04f, 0x4eb64dad, 0xb1c87820, 0x210048ae, 
+    0x78004aae, 0x0007f000, 0x1000eb00, 0x0080eb02, 0x78286041, 0xf7fab908, 0x7820fc53, 0xd02b2802, 
+    0xb9987828, 0xf44f7831, 0xf7f33080, 0xe00dfe61, 0xb9687828, 0xfc44f7fa, 0xf44f7831, 0xf7f32000, 
+    0xf242fe57, 0x06080180, 0xfcc7f7ec, 0xb9987820, 0x0001f997, 0x90042301, 0x9005220e, 0xe9cd4611, 
+    0x200cb002, 0x90019000, 0xf7f40398, 0xf242fcbb, 0x06c80190, 0xfcb1f7ec, 0x46a07828, 0x1000f994, 
+    0xd17c4308, 0x25004893, 0xfd89f7f5, 0xa20cf8df, 0xf89a4a90, 0x28030000, 0x4990d109, 0xf991488e, 
+    0xf8423002, 0xf9910023, 0xf8421003, 0x68110021, 0xf8522401, 0x42880024, 0x4601d201, 0x1c644625, 
+    0x2c04b264, 0xf44fdbf5, 0xf6403000, 0xf7ec0103, 0xf7fafc78, 0x4c82fa46, 0x46082100, 0x2000f994, 
+    0xff18f7f5, 0xfb26f7fa, 0x46072203, 0x2138487d, 0xf0147025, 0xf8dffd92, 0xb15891f0, 0x0000f899, 
+    0xd5070740, 0x0000f89a, 0xd0032803, 0x78004877, 0xe0007020, 0xb2397025, 0xf7fa1438, 0x4974fa9c, 
+    0xf8812002, 0xf7fab000, 0xf994fc98, 0xf7fa0000, 0xf994f9f3, 0xf7fa0000, 0xf994fa38, 0xf7fa0000, 
+    0x4868fa83, 0x21382203, 0xfd67f014, 0xf899b128, 0x07400000, 0xf7fad501, 0xf7fafd33, 0x7831fbb1, 
+    0x0000f242, 0xfdc4f7f3, 0x20012100, 0xf939f7f6, 0x2000f994, 0x200c2100, 0xfe86f7f5, 0xe005e000, 
+    0xf9942101, 0x46082000, 0xfec4f7f5, 0x0000f898, 0x28034644, 0x2301d00c, 0x4619220c, 0xf7f4200e, 
+    0x7820fcf2, 0x2100b920, 0x0000f44f, 0xfda0f7f3, 0xf242b007, 0x06c80190, 0x4ff0e8bd, 0xbc0df7ec, 
+    0x4ff8e92d, 0x46044d40, 0xf2408e80, 0x28fe1b0f, 0xd05f68ab, 0x28dddc1b, 0xdc0fd039, 0x28b0b370, 
+    0x28b1d040, 0x28dcd048, 0x2200d155, 0xf1054618, 0xf010010c, 0x1d40fd56, 0xe028d07c, 0xd07a28ee, 
+    0xd02428ef, 0xd07728f6, 0xd14428f7, 0x4558e01f, 0x110ff2a0, 0xdc12d01b, 0xd01828ff, 0x7f83f5b0, 
+    0xf111d06b, 0xd0120008, 0xd1342807, 0x22004926, 0x310c4618, 0xfd35f010, 0xd07d1d40, 0x2907e007, 
+    0x2908d07b, 0x2911d003, 0x2912d078, 0x491ed123, 0x32fff04f, 0x310c68a8, 0xfd52f010, 0xd1071d01, 
+    0xe17b20b0, 0x22004918, 0x310c4618, 0xfd48f010, 0xd06f1d41, 0xd1ea2801, 0x26004f13, 0x0000f242, 
+    0xf9b7370c, 0x290f1000, 0xf04fd066, 0xf04f0802, 0xe0330901, 0xe13be0fe, 0x000302d7, 0x00030394, 
+    0xd00350f6, 0x0002b8b0, 0x0003112c, 0x0003031c, 0x00030280, 0xd03c80b8, 0x00030c74, 0x00037aec, 
+    0x000301e2, 0x000301e1, 0x000304b4, 0x00030c58, 0x00030223, 0x0003113c, 0x00029395, 0x00030338, 
+    0x00030227, 0xd28f007c, 0x00030259, 0x00030441, 0x00030225, 0xe096e088, 0xe0e8e0ac, 0xf04f2915, 
+    0xf04f0a03, 0xd02d42e0, 0xd1a0290a, 0x1006f9b5, 0xd07b2901, 0xd0722909, 0xd0712902, 0xd0702903, 
+    0xd06f2904, 0xd06e2905, 0xd1902906, 0xfb66f7ff, 0x8038200b, 0xe0022007, 0xe0f8e0e8, 0x80e8e104, 
+    0x48a81e72, 0x68004639, 0xfcabf010, 0xd0731d01, 0xe7ffe100, 0xe10120b1, 0x4227f04f, 0xfb7ff7ec, 
+    0xe77480ee, 0xf9934ba0, 0x2b033000, 0x2b05d003, 0x2b04d001, 0x4b9dd102, 0xb123781b, 0x80ee2108, 
+    0xfb6df7ec, 0xf04fe763, 0x46074220, 0xfb67f7ec, 0x46382105, 0xfb15f7ec, 0x20002101, 0xfdb6f7f4, 
+    0xf0082004, 0x4892fbb5, 0x78004992, 0x1000f991, 0xd0124308, 0x49902000, 0x22017068, 0x46102300, 
+    0xa000f881, 0x96004611, 0xfdf2f7f2, 0xf8a5488b, 0x78009006, 0xd0022802, 0x2001e003, 0xf8a5e7eb, 
+    0x210a8006, 0x22004886, 0x46018001, 0xf01068a8, 0x1d01fc58, 0xaefff47f, 0xe0af20dc, 0xe01ce006, 
+    0xe050e031, 0xe084e06d, 0xe0a720dd, 0xfde3f7ff, 0x80e82009, 0x2200497a, 0xf01068a8, 0x1d01fc42, 
+    0x20eed106, 0x4976e09a, 0x46182200, 0xfc39f010, 0xd1961d40, 0xe09120ef, 0xf000e083, 0xf8a5f8a0, 
+    0x22008006, 0x68a8496e, 0xfc2bf010, 0xd1061d01, 0xe08320f6, 0x2200496a, 0xf0104618, 0x1d40fc22, 
+    0x20f7d190, 0xf7ece07a, 0x4966fafa, 0x23002201, 0xf8814610, 0x46119000, 0xf7f29600, 0xf8a5fd99, 
+    0x2200a006, 0x68a8495e, 0xfc0bf010, 0xd1061d01, 0xe06320fe, 0x2200495a, 0xf0104618, 0x1d40fc02, 
+    0x20ffd1c7, 0xf7ffe05a, 0x2002fd3f, 0xfbdef7f3, 0x200ab108, 0x200fe000, 0x49518038, 0x68a82200, 
+    0xfbeff010, 0xd1071d01, 0x1006f240, 0x494ce046, 0x46182200, 0xfbe5f010, 0xd1aa1d40, 0x1007f240, 
+    0xf7ffe03c, 0x2002fbaf, 0xfbc0f7f3, 0x200ab108, 0x200fe000, 0x49428038, 0x68a82200, 0xfbd1f010, 
+    0xf47f1d01, 0xf240ae99, 0xe027100e, 0xb034f8a4, 0xf7ffe506, 0x2006fac2, 0x493980e8, 0x68a82200, 
+    0xfbbff010, 0xd1071d01, 0x1016f240, 0x4934e016, 0x46182200, 0xfbb5f010, 0xd1911d40, 0x1017f240, 
+    0xf240e00c, 0xe0091020, 0x22004826, 0x6800492c, 0xfba7f010, 0xd1a31d40, 0x1021f240, 0xe4df86a0, 
+    0x21012200, 0xf2afb510, 0xf01030a7, 0x2108f9e5, 0xf0102002, 0x4922fb43, 0x6088390c, 0x4822bd10, 
+    0x7800b510, 0x481bb330, 0xbb187800, 0x7800481f, 0xd01f2803, 0x78004814, 0xd1022803, 0x7800481c, 
+    0x4817b1c0, 0x42e0f04f, 0xf9b0380c, 0xf2421006, 0xf7ec0000, 0x2000fa54, 0xfffef7f3, 0xfd2cf7f6, 
+    0xf954f7f6, 0xf7f32001, 0x2100fff7, 0x1000f44f, 0xfb8ef7f3, 0x0190f242, 0x4010e8bd, 0xf7ec06c8, 
+    0x0000b9fc, 0x000304ec, 0x00030222, 0x00030284, 0x0003031c, 0x00030c58, 0x000301de, 0x0003036e, 
+    0x000304c0, 0x000301e1, 0x0003028e, 0x00030394, 0x000302d5, 0x41f0e92d, 0x0500f244, 0x4628210a, 
+    0xf9cff7ec, 0xf24f2307, 0x220c0100, 0x46204cfe, 0xfacef014, 0xf6402307, 0x22087100, 0xf0144620, 
+    0x48fafac7, 0xf0142104, 0x48f9fac0, 0x78002400, 0x48f8b388, 0xb9807800, 0x20012100, 0xfec1f7f5, 
+    0x21004ef5, 0xf996200c, 0xf7f52000, 0x2101fc0d, 0x2000f996, 0xf7f54608, 0x4ef0fc4d, 0x28017830, 
+    0x2401d100, 0x11f4f240, 0x7780f04f, 0xf7ec4638, 0xf249f998, 0x46382122, 0xf982f7ec, 0x1000f996, 
+    0xf7ec4638, 0x4621f97d, 0xf7ec4638, 0x49e4f979, 0xf7ec4638, 0x49e3f975, 0x7809200d, 0xd1032905, 
+    0x780949e1, 0x200fb901, 0x780949e0, 0xd1002901, 0x19021c64, 0xf1042301, 0x4619000e, 0xfa53f7f4, 
+    0x01b0f242, 0xf7ec06c8, 0x4628f978, 0x41f0e8bd, 0xf7ec210b, 0xe92db966, 0x4ed55ff0, 0x8e804604, 
+    0x7fc1f5b0, 0xd06e6873, 0x28e6dc12, 0xdc05d06c, 0x288cb318, 0x288dd02c, 0xe033d167, 0xd01c28e7, 
+    0x7fa3f5b0, 0xf5a0d074, 0x38477080, 0xe014d15d, 0x7fc8f5b0, 0xdc08d06d, 0x7080f5a0, 0xd00c3883, 
+    0xd0672805, 0xd1502806, 0xf5a0e007, 0x38917080, 0x280dd003, 0x280ed07e, 0x49bdd147, 0x32fff04f, 
+    0x31086870, 0xfaccf010, 0xd1071d01, 0xe256208c, 0x220049b7, 0x31084618, 0xfac2f010, 0xd0281d41, 
+    0xd1ea2801, 0xf2444fb2, 0xf04f0a00, 0x37080800, 0x1000f9b7, 0xd01e290f, 0x29164dae, 0x4900f04f, 
+    0xf9b6d024, 0x29011000, 0x2902d07e, 0x0388d1d5, 0xf7ec464a, 0xf7fff954, 0x200bff2d, 0x48a68038, 
+    0x32fff04f, 0x68004639, 0xfa6bf010, 0xd06c1d01, 0x208de221, 0xf04fe223, 0x46504228, 0xf93ff7ec, 
+    0x8000f8a6, 0xe1c9e7b9, 0xe219e06b, 0xb254f8df, 0x0000f99b, 0xd00e2803, 0xd00c2805, 0xd00a2804, 
+    0x464a2103, 0xf8a64650, 0xf7ec8000, 0xe7a4f928, 0xe1ede14c, 0xf04fe1d0, 0x46574220, 0xf7ec4650, 
+    0x2109f91e, 0xf7ec4638, 0xf242f8cc, 0x464801b0, 0xf8d3f7ec, 0x78004885, 0xd01a2801, 0x28017828, 
+    0x2802d017, 0x2005d015, 0xf962f008, 0x78004883, 0xe0002801, 0xd00ee1d9, 0x8000f8a6, 0x497c200a, 
+    0x31082200, 0x68708008, 0xfa1bf010, 0xd0261d01, 0x2006e02d, 0x2301e7e8, 0x220a4879, 0xf0140299, 
+    0x2000f9be, 0xfe98f7f3, 0x68004876, 0xd8032811, 0x46382100, 0xfa2cf7f3, 0x1000f89b, 0x29042008, 
+    0x7829d106, 0xe0012901, 0xe1abe015, 0x2010d100, 0x2101782a, 0xfd3ef7f9, 0x80302001, 0x20e6e7ce, 
+    0x4963e1ad, 0x46182200, 0xf0103108, 0x1d40f9ea, 0x20e7d188, 0xf242e1a3, 0x06c801b0, 0xf87df7ec, 
+    0xf8df46c1, 0x48618184, 0x9000f888, 0xf2427801, 0xf7f30000, 0x485af9fd, 0x21202205, 0xf014300a, 
+    0xb2c0f98c, 0x0000f888, 0xd0712801, 0x22054854, 0x300a2120, 0xf981f014, 0xf888b2c0, 0x78290000, 
+    0x290346ab, 0x2801d117, 0xd0144645, 0xf641484c, 0x220071ff, 0x30ba460b, 0xf961f014, 0x7801484b, 
+    0x0000f248, 0xf9d4f7f3, 0x22054845, 0x300a2120, 0xf963f014, 0x483d7028, 0x28017800, 0xf898d004, 
+    0x28010000, 0xe020d044, 0x48412500, 0x22002310, 0xf01421ff, 0x483ef944, 0x23012208, 0x1e800151, 
+    0xf93df014, 0xf2422100, 0xf7f30000, 0x4834f9b1, 0x21202205, 0xf014300a, 0xb2c0f940, 0x0000f888, 
+    0xd0252801, 0x2d101c6d, 0x2198dbdf, 0xf7ec4650, 0x4830f808, 0xb1886800, 0xf7f32000, 0xf242fdfd, 
+    0x06c801b0, 0xf809f7ec, 0xf240481a, 0xf8a63190, 0x4b299000, 0x1e487802, 0xf9bcf7f3, 0xf7f54827, 
+    0xf89bf8de, 0x48251000, 0xd06a2903, 0xe7ffe07a, 0x4200f04f, 0x1000f9b6, 0xf7ec0c10, 0x4820f830, 
+    0xf8daf014, 0x20024605, 0xf92af7f3, 0x481d1a29, 0xf0007800, 0xeb000007, 0x481b1200, 0x0082eb00, 
+    0x20026281, 0xe0318030, 0xd180004c, 0xd0031034, 0x00030c58, 0x0003031c, 0x00030227, 0x00030c9c, 
+    0xdcba01f5, 0x00030222, 0x0003025b, 0x000302d7, 0x000304c8, 0x00030394, 0x000304ec, 0x000301e1, 
+    0xd0035022, 0x000301cc, 0x0003020b, 0x00030223, 0xd0030482, 0x00047f70, 0xd03c80b8, 0x0003113c, 
+    0xc8000128, 0x00030c74, 0x00037aec, 0x2200486d, 0x1c496801, 0x200a6001, 0x496b8038, 0xf0106870, 
+    0x1d01f900, 0xf240d107, 0xe0b81046, 0x22004966, 0xf0104618, 0x1d40f8f6, 0xae39f47f, 0x1047f240, 
+    0x4962e0ad, 0x2000f991, 0x3002f991, 0x2022f850, 0x2023f840, 0x2001f991, 0x1003f991, 0x2022f850, 
+    0x2021f840, 0x3200e9d0, 0x1002e9d0, 0xeb01189d, 0x44650c00, 0x5ce8f64f, 0x0f95ebbc, 0x4293d917, 
+    0x461dd901, 0x4615e000, 0xd9014281, 0xe000468c, 0x45654684, 0x4293d905, 0x4618d901, 0x4610e004, 
+    0x4281e002, 0x4608d900, 0x42884949, 0x4849d94e, 0xb3707800, 0xf9b14948, 0x28140000, 0x1c40da2a, 
+    0x48468008, 0x78002200, 0xf0001c40, 0xeb000007, 0x48431100, 0x0081eb00, 0xf5016881, 0x60816180, 
+    0x9000f8a6, 0x8038203f, 0x4937483e, 0xf0106800, 0x1d01f898, 0xf240d108, 0xe0501082, 0x22004839, 
+    0x68004931, 0xf88df010, 0xd1951d40, 0x1083f240, 0xe7ffe045, 0xf7f32002, 0xb108f869, 0xe000200a, 
+    0x8038200f, 0x22004928, 0xf0106870, 0x1d01f87a, 0xf240d107, 0xe0321088, 0x22004923, 0xf0104618, 
+    0x1d40f870, 0xf240d1e1, 0xe0281089, 0xf7f32002, 0xb108f84d, 0xe000200a, 0x8038200f, 0x2200491a, 
+    0xf0106870, 0x1d01f85e, 0xf240d107, 0xe0161090, 0x22004915, 0xf0104618, 0x1d40f854, 0xf240d1c5, 
+    0xe00c1091, 0x109ef240, 0x4817e009, 0x490e2200, 0xf0106800, 0x1d40f846, 0xf240d1b7, 0x86a0109f, 
+    0x9ff0e8bd, 0x21012200, 0xf2afb510, 0xf00f5035, 0x2108fe83, 0xf00f2003, 0x4903ffe1, 0x60483908, 
+    0x0000bd10, 0x00047f84, 0x000304d0, 0x00030338, 0x00013880, 0x00030c58, 0x00030c5e, 0x00030c74, 
+    0x00037aec, 0x00030c90, 0x000304ec, 0x5ffce92d, 0xf2482700, 0x210c0000, 0xfea3f7eb, 0x220148f8, 
+    0xf0132102, 0xb110ffca, 0xf7f42000, 0xf8dffac6, 0x465cb3d4, 0x0000f89b, 0xfd8bf7f4, 0xf0057820, 
+    0xf005f973, 0xf8dffaac, 0xf89883c0, 0xbbe80000, 0xa3b8f8df, 0x0900f04f, 0x464c4aed, 0x0000f89a, 
+    0x0007f000, 0x1000eb00, 0x0080eb02, 0x902cf8c0, 0x48e82301, 0x46212200, 0x2644eb00, 0xeb0048e6, 
+    0x46182544, 0x5600e9cd, 0xfc41f7f1, 0x20762100, 0x2010f835, 0xf302fb12, 0x2010f836, 0xb2801c40, 
+    0xfb12287f, 0x44113202, 0x48dcd9f2, 0x22002301, 0x1024f840, 0xf84048da, 0x48da1024, 0xeb0049da, 
+    0xeb012044, 0xe9cd2144, 0xe0001000, 0x4621e00a, 0xf7f14610, 0x1c64fc1c, 0x2c04b264, 0xf898dbc8, 
+    0xb3780000, 0x46304ed1, 0xff3cf013, 0x0104f640, 0x0401ea00, 0xf0134630, 0xf000ff35, 0x46300580, 
+    0xff30f013, 0x5680f400, 0xf0032004, 0x2201fe2e, 0x46104611, 0xfd78f003, 0x9314f8df, 0xf89949c5, 
+    0xb1500000, 0xf0254ac4, 0x78120580, 0xd4010692, 0x6400f424, 0x28014fc1, 0x4ac1d824, 0x2a017812, 
+    0xe02bd01e, 0xf89be7ff, 0xf6400000, 0x28030404, 0x2500d014, 0x9000f8ca, 0xf8df4649, 0x48ba92e8, 
+    0x0600f241, 0x1000f8c9, 0xfefff013, 0x0000f8b9, 0x48b5b281, 0xf0133014, 0xe7c5fef8, 0xe7e92580, 
+    0xd9012801, 0xe0002002, 0x70082003, 0x220049af, 0xf7f22004, 0x200bff4b, 0xf829f7f3, 0xa2b0f8df, 
+    0x0000f89a, 0xf899b920, 0xb1080000, 0xe0002001, 0xf7f92000, 0xf89aff3a, 0x46d10000, 0x48a5b920, 
+    0xb1087800, 0xe0002008, 0x432c2000, 0x433c4304, 0xb2a04334, 0x61e0f440, 0xf0134894, 0x489efec6, 
+    0xf0132100, 0xf898fec2, 0xb9480000, 0x2001499b, 0x499b7008, 0x499b7008, 0x20007008, 0x7008499a, 
+    0xf7f92001, 0x4899fdbd, 0x0000f990, 0xfb9df7f9, 0x0000f899, 0xd0112801, 0x48952100, 0xeb008800, 
+    0xebc20240, 0xe8bd10c0, 0xeb015ffc, 0xf2a000c0, 0xb28110e5, 0x1c80487d, 0xbe97f013, 0x7110f242, 
+    0xe92de7eb, 0x4e8b5ffc, 0x498b4604, 0x0a00f04f, 0x68738e80, 0x7f8ff5b0, 0xd075680d, 0x28e2dc12, 
+    0xdc05d073, 0x28b6b318, 0x28b7d02c, 0xe033d16e, 0xd01c28e3, 0x7f89f5b0, 0xf5a0d069, 0x38137080, 
+    0xe014d164, 0x7fd6f5b0, 0xdc08d072, 0x7080f5a0, 0xd00c381f, 0xd06c2867, 0xd1572868, 0xf5a0e1d2, 
+    0x38ad7080, 0x2821d003, 0x2822d078, 0x4971d14e, 0x32fff04f, 0x31086870, 0xfef2f00f, 0xd1071d01, 
+    0xe21820b6, 0x2200496b, 0x31084618, 0xfee8f00f, 0xd01f1d41, 0xd1ea2801, 0x27004d66, 0xf9b53508, 
+    0x290f1000, 0x2917d018, 0x4210f04f, 0xf9b6d030, 0xf2481000, 0xf7eb0000, 0xf9b6fd82, 0xf8df0000, 
+    0x2801b108, 0x2802d055, 0x4851d1d1, 0x28017800, 0xe1d8d075, 0xe1ee20b7, 0x4229f04f, 0x0000f248, 
+    0xfd6df7eb, 0x4a524955, 0x68088037, 0x42906812, 0x1c40da01, 0x88086008, 0x4843b281, 0xf0131c80, 
+    0x484ffe14, 0xe7b27007, 0xe028e106, 0xe0d0e1d4, 0xf990482c, 0x28030000, 0x2805d00c, 0x2804d00a, 
+    0x2103d008, 0x0000f248, 0xf7eb8037, 0xe79efd48, 0xe15fe192, 0x4220f04f, 0x0000f248, 0xfd3ff7eb, 
+    0x2001493c, 0x200a8030, 0x22008028, 0x31086870, 0xfe57f00f, 0xd1081d01, 0xe1ac20e2, 0x4935e1a2, 
+    0x46182200, 0xf00f3108, 0x1d40fe4c, 0x20e3d1cb, 0xf8dfe1a1, 0x230180d0, 0x461a2102, 0xf0134640, 
+    0x2300fdee, 0x22014640, 0xf0132102, 0x2002fde8, 0xff2ff7f2, 0x90b0f8df, 0x482cb120, 0x28017800, 
+    0xe0f9d07e, 0x0000f99b, 0x8020f8df, 0xb020f8df, 0xd04d2805, 0xd0502802, 0xd04e2803, 0xe155e084, 
+    0xd03d104a, 0x00030222, 0x00030c58, 0x00030c74, 0x00037aec, 0x0003955c, 0x00038d5c, 0x00030fcc, 
+    0x00030fdc, 0x0003a55c, 0x00039d5c, 0xd03c80b6, 0x0003025b, 0x0003038d, 0x00030259, 0xffff8000, 
+    0x00030380, 0x00030ca0, 0xd003513e, 0x0ee6b280, 0x0003031c, 0x00030c9c, 0xd003086e, 0x00030225, 
+    0x00030226, 0x00030240, 0x00030241, 0x00030227, 0x00047f78, 0x000304d8, 0x00030c90, 0x00047f80, 
+    0x00030ae4, 0xd03c8314, 0x00030c5e, 0x00030309, 0x0000f9b9, 0xdb042814, 0xf9b9e036, 0x28040000, 
+    0x489eda32, 0xf2427801, 0xf7f20000, 0xf8b9fdf1, 0x1c491000, 0x1000f8a9, 0x0000f898, 0xf0001c40, 
+    0xeb000007, 0xeb0b1100, 0x68810081, 0x6180f501, 0x80376081, 0x8028203f, 0x49912200, 0xe0004891, 
+    0x6800e045, 0xfdadf00f, 0xd1071d01, 0x1012f240, 0x498be101, 0x46282200, 0xfda3f00f, 0xf47f1d40, 
+    0xf240aec0, 0xe0f61013, 0x68004887, 0x4888b148, 0x319bf240, 0x4b858037, 0x1e487802, 0xfdeaf7f2, 
+    0xf898e6c5, 0x22000000, 0xf0001c40, 0xeb000007, 0xeb0b1100, 0x68810081, 0x7100f501, 0x80376081, 
+    0x80282009, 0x4976487b, 0xf00f6800, 0x1d01fd7a, 0xf240d108, 0xe0ce101e, 0x22004876, 0x68004970, 
+    0xfd6ff00f, 0xd1db1d40, 0x101ff240, 0xf89be0c3, 0xbb880000, 0xf7f44870, 0xf8dffce2, 0x220081c0, 
+    0x0000f248, 0x1000f8d8, 0xfc39f7eb, 0xf8df2500, 0x220081a8, 0x0000f248, 0x1025f858, 0xfc2ff7eb, 
+    0x20004967, 0x4b684a67, 0x0100e9cd, 0x0025f858, 0xfb8ef7eb, 0x48614602, 0x42826800, 0x4963d208, 
+    0x0000f248, 0xf7eb8037, 0xf04ffc1a, 0xe66e0a01, 0xb2ed1c6d, 0xd3da2d04, 0x0f00f1ba, 0xf8a9d1a0, 
+    0xf89b7000, 0xb1380000, 0x68084959, 0x60081c40, 0x4858b281, 0xfcb9f013, 0xf8b9f7f9, 0x20014d56, 
+    0xf7f37829, 0x4955ffee, 0x0000f995, 0x49547008, 0xb1b98809, 0x22734953, 0x2201800a, 0x2200708a, 
+    0x485170c8, 0xf00f6800, 0x1d01fd0c, 0xf240d108, 0xe0601086, 0x2200484c, 0x6800494a, 0xfd01f00f, 
+    0xd0231d40, 0xf0134849, 0x2301fc8d, 0x220f4848, 0xf01303d9, 0xf7ecfca4, 0x2002fe0f, 0xfdc7f7f2, 
+    0x20082100, 0xffd8f7f4, 0xf7f52001, 0x2001f826, 0xf805f7f5, 0x2002492a, 0x200a8030, 0x80082200, 
+    0xf00f6870, 0x1d01fcde, 0xe00ad003, 0x1087f240, 0xf240e031, 0xe02e10ac, 0x22004921, 0xf00f4618, 
+    0x1d40fcd0, 0xf240d193, 0xe02410ad, 0x0000f89b, 0xf7f9b948, 0xf44ffa33, 0xf6403000, 0xf7eb0103, 
+    0xf7f9fb50, 0xf7fff91e, 0x203ffca1, 0x48158028, 0x49132200, 0xf00f6800, 0x1d01fcb4, 0xf240d107, 
+    0xe00810ce, 0x2200490e, 0xf00f4628, 0x1d40fcaa, 0xf240d1d8, 0x86a010cf, 0x9ffce8bd, 0x21012200, 
+    0xf2afb510, 0xf00f40c1, 0x2108fae7, 0xf00f2003, 0x4903fc45, 0x60483908, 0x0000bd10, 0x00030223, 
+    0x000304e0, 0x00030c90, 0x00047f70, 0xd03c80b8, 0x0003031c, 0x000304ec, 0x0003113c, 0x0003030c, 
+    0x40300000, 0xb573eab3, 0x4030ab15, 0xdead0000, 0x00030ca0, 0xd0035152, 0x00030222, 0x000301dc, 
+    0x000302e0, 0x0003ce0c, 0x00030c24, 0xd0060010, 0xd003501a, 0x800849fe, 0xe92d4770, 0xf8df4ff8, 
+    0x4604b3f4, 0xf04f8e80, 0xf8df0a00, 0x4df893e4, 0x7f33f5b0, 0xf1094ef8, 0xf8db0908, 0xd0763000, 
+    0xf240dc7e, 0x4290129d, 0x119df2a0, 0xdc4ed04e, 0x1259f240, 0xf2a04290, 0xd0251159, 0x28b5dc25, 
+    0xdc11d011, 0xd07d2800, 0xd07c28ac, 0xd06628ad, 0xd17928b4, 0x22006868, 0xf00f4649, 0x1d41fc61, 
+    0x2801d073, 0xe12ad15b, 0x7f9af5b0, 0xf5a0d06e, 0x38357080, 0x2823d053, 0x49e0d1eb, 0x46182200, 
+    0xfc1ff00f, 0xd07d1d40, 0x2920e238, 0xdc0fd00f, 0xd0782919, 0xd0f9291a, 0xd1da291f, 0x220048d8, 
+    0x310849d3, 0xf00f6800, 0x1d40fc0c, 0xe38dd06c, 0xd06a2939, 0xd069293a, 0xd1ca2943, 0x220049cc, 
+    0x31086868, 0xfbfdf00f, 0xd0721d40, 0x2981e2b0, 0xdc12d070, 0xd06e292f, 0x2909dc08, 0x290ad06c, 
+    0x2929d06b, 0x292ad06a, 0xe36fd1b3, 0xd0de2930, 0xd0782963, 0xd1ac2964, 0x29f3e368, 0xdc08d074, 
+    0xd0722982, 0xd07129bd, 0xd1a229be, 0xe3fbe38d, 0x29f4e006, 0x29fbd06b, 0x29fcd06a, 0xe0bed199, 
+    0xf2404fb8, 0x4290327f, 0x317ff2a0, 0xd02f683f, 0xf8dfdc6e, 0xf2a0c2d4, 0xf2403143, 0xf8dc3243, 
+    0xe004c000, 0xe0a0e090, 0xe0b6e3f9, 0x4290e1ae, 0xdc34d02e, 0x322df240, 0xf2a04290, 0xd017312d, 
+    0xf111dc17, 0xd0130060, 0xd075281f, 0xd00f2820, 0xd192285f, 0x2200499e, 0x31084660, 0xfba1f00f, 
+    0xe0041d40, 0xe1e6e1b7, 0xe232e1f0, 0xd078e238, 0x290de085, 0x290ed076, 0x2915d075, 0x489bd18d, 
+    0x49932200, 0x68003108, 0xfb8bf00f, 0xd06b1d40, 0xe23ae3ef, 0xe29ce2ff, 0xe252e24c, 0x2910e27f, 
+    0xdc16d00f, 0xd0762907, 0xd0f12908, 0xd18b290f, 0x2200488f, 0x31084986, 0xf00f6800, 0x1d40fb72, 
+    0x2009d06a, 0xe2c7e3d0, 0xe2ece3b8, 0xe3bce3a8, 0x2919e3dd, 0x291ad07e, 0x293bd051, 0x497cd185, 
+    0x46382200, 0xf00f3108, 0x1d40fb5c, 0xe046d073, 0x1221f240, 0xf2a14291, 0xd06d1021, 0x291ddc12, 
+    0xdc08d06b, 0xd069290d, 0xd068290e, 0xd0672915, 0xd19e2916, 0x291ee3f5, 0x29c9d07e, 0x29cad07d, 
+    0xe02cd197, 0xd0792836, 0x2801dc07, 0x282ad027, 0x282bd075, 0xe022d18d, 0x2837e3fe, 0x2850d01f, 
+    0x2851d06e, 0xe01ad185, 0xf8a92107, 0x49601000, 0x68682200, 0xf00f3108, 0x1d01fb24, 0x20acd10b, 
+    0xe3eae21c, 0xe3eae3ea, 0x4959e3ea, 0x68682200, 0xf00f3108, 0x1d40fb16, 0x20add101, 0x4954e7f0, 
+    0x32fff04f, 0x31086868, 0xfb3af00f, 0xf47f1d01, 0x20b4aed6, 0xe3fce7e4, 0x20b5e3fc, 0xf44fe7e0, 
+    0xf9b92800, 0xf04f1000, 0x464f4220, 0xf7eb4640, 0xf9b7f9d6, 0x28070000, 0x2806d047, 0x2805d07c, 
+    0x2870d07b, 0x2871d07a, 0x2808d079, 0x280bd078, 0xe006d077, 0xe3f0e3f0, 0xe3f0e3f0, 0xe3f0e3f0, 
+    0x2809e3f0, 0x2821d06e, 0x2822d06d, 0x2823d06c, 0x2820d06b, 0x2874d06a, 0xd1c046b9, 0x2202483d, 
+    0xf0132104, 0x4607fa8a, 0x2202483a, 0x1d802104, 0xfa83f013, 0xe0042800, 0xe3f9e3f9, 0xe3f9e3f9, 
+    0xd054e3f9, 0x40072000, 0x22004833, 0xf0132101, 0xb2c0fa74, 0x0100ea57, 0x4930d072, 0x780ab117, 
+    0xd06e2a00, 0xd06d2801, 0x200be3f9, 0x46508028, 0xa000f886, 0xfabcf7f2, 0x70084929, 0x78004829, 
+    0x4829b140, 0x78037831, 0x78024828, 0x78004828, 0xfe1bf7f5, 0xf87ef7f4, 0x88004826, 0x2000b910, 
+    0xfb76f011, 0x8090f8df, 0x0000f898, 0xd1012801, 0xfb6ef011, 0xf969f7f4, 0x23004820, 0x21802207, 
+    0xfa2df013, 0x2301481d, 0x21402206, 0xfa27f013, 0x22052301, 0xe0362120, 0xe208e073, 0xe321e2f3, 
+    0xe3efe354, 0xe3efe3ef, 0xe3efe3ef, 0xe3efe3ef, 0x000304e8, 0x00030c24, 0x00030222, 0x0003ce18, 
+    0x00030be4, 0x000304a8, 0x000304dc, 0x00030480, 0x000304cc, 0xd0039026, 0xd2154120, 0x00030303, 
+    0x00030223, 0x00030308, 0x000303b9, 0x000303b8, 0x00030307, 0x000302e0, 0x00030302, 0xd0034228, 
+    0xe3f5e3f5, 0x48fee3f5, 0xf9e9f013, 0x230148fc, 0x21102204, 0xf9e3f013, 0x230048f9, 0x21082203, 
+    0xf9ddf013, 0x230048f6, 0x21022201, 0xf9d7f013, 0x48f32301, 0x46192200, 0xf9d1f013, 0x0000f898, 
+    0xd1042801, 0x880048ef, 0x0040f030, 0x2006d009, 0x49ed8038, 0x68682200, 0xfa13f00f, 0xd0021d01, 
+    0x2074e009, 0xf240e7f4, 0xe1071034, 0x220049e6, 0xf00f6868, 0x1d40fa06, 0xae31f47f, 0x1035f240, 
+    0x48e2e0fc, 0xb1c88800, 0x780048e1, 0xd0152801, 0x217348e0, 0x80012200, 0xa002f880, 0x70c17831, 
+    0xf8db4601, 0xf00f0000, 0x1d01f9ec, 0xadcaf47f, 0x1058f240, 0xf240e0e2, 0xe0df1059, 0x8028200c, 
+    0xf7f92000, 0x48d4fb85, 0xf88046d4, 0x48d3a000, 0x28017800, 0x48d2d011, 0xb3507800, 0x216e48d1, 
+    0x1000f8a9, 0x49c82200, 0xf00f6800, 0x1d01f9ca, 0xadbbf47f, 0x1078f240, 0x48cbe0c0, 0xf8a92166, 
+    0x22001000, 0x680049c0, 0xf9bbf00f, 0xd1081d01, 0x1072f240, 0x48c4e0b2, 0x49bb2200, 0xf00f6800, 
+    0x1d40f9b0, 0xf240d175, 0xe0a71073, 0x1079f240, 0x48bee0a4, 0x28017800, 0x48b5d01b, 0x28017800, 
+    0x48bbd02a, 0x28018800, 0x48bad03d, 0x28017800, 0x48b9d036, 0x28017800, 0x48b8d032, 0x28017800, 
+    0x48b7d02e, 0x28017800, 0x4fb6d071, 0xb3c07838, 0x2000e0a9, 0xf946f7f8, 0xf44f2100, 0xf7f23080, 
+    0x2000f9a7, 0xfa2ef7f7, 0xf921f7fa, 0x200249ae, 0x800806c2, 0xe05d211a, 0xf8a92122, 0x499a1000, 
+    0x68682200, 0xf96df00f, 0xd1071d01, 0x1092f240, 0x4995e064, 0x68682200, 0xf963f00f, 0xd0111d40, 
+    0x8800489b, 0x2121b1a0, 0x1000f8a9, 0x2200498e, 0xf00f6868, 0x1d01f956, 0xad56f47f, 0x109cf240, 
+    0xe03ce04c, 0x1093f240, 0xf240e048, 0xe045109d, 0x78004890, 0xd1142801, 0xf8a92123, 0x49821000, 
+    0x68682200, 0xf93df00f, 0xd1081d01, 0x10a6f240, 0xe023e034, 0x2200497c, 0xf00f6868, 0x1d40f932, 
+    0x4885d004, 0x28017800, 0xe008d003, 0x10a7f240, 0xf04fe024, 0x21125280, 0xf7eb1250, 0x487ff800, 
+    0x28017800, 0x0702d10a, 0xe0032113, 0x2115e7ff, 0x5280f04f, 0x2000f44f, 0xfff1f7ea, 0x487be096, 
+    0xb1b07800, 0xf8a92170, 0x49671000, 0x68682200, 0xf907f00f, 0xd1071d01, 0x10c6f240, 0x4962e24e, 
+    0x68682200, 0xf8fdf00f, 0xd17f1d40, 0x10c7f240, 0x486fe244, 0xb1b07800, 0xf8a92171, 0x495a1000, 
+    0x68682200, 0xf8edf00f, 0xd1071d01, 0x10ccf240, 0x4955e234, 0x68682200, 0xf8e3f00f, 0xd1651d40, 
+    0x10cdf240, 0x4863e22a, 0x1000f990, 0x78004862, 0xd03b4301, 0x22014b61, 0x2002f8a9, 0xf8834649, 
+    0xb1e0c000, 0x7800485e, 0xd0180907, 0x1f10ebb2, 0x2011d101, 0x2702e004, 0x1f10ebb7, 0x2012d102, 
+    0xe00c8048, 0xebb72703, 0xd1011f10, 0xe0042011, 0xebb72704, 0xd1021f10, 0x80482012, 0x2005701a, 
+    0x0000f8a9, 0x49382200, 0xf00f6868, 0x1d01f8aa, 0xf240d107, 0xe1f12000, 0x22004933, 0xf00f6868, 
+    0x1d40f8a0, 0xf240d122, 0xe1e72001, 0xf7f82000, 0x7838f859, 0xd1192801, 0x213a4842, 0x1000f8a9, 
+    0x49292200, 0xf00f6800, 0x1d01f88c, 0xf240d109, 0xe1d3201e, 0x483be00a, 0x49232200, 0xf00f6800, 
+    0x1d40f880, 0x4924d010, 0x70082001, 0x78014836, 0xf47f2901, 0xf880aca4, 0x2300a000, 0x22014833, 
+    0xf0132102, 0xe55af81c, 0x201ff240, 0x491ae1b6, 0x8028200d, 0xf881481a, 0x7800a000, 0xf9b7b9a8, 
+    0x28120002, 0x2811d07e, 0x4829d07d, 0xf5b08800, 0xd07a7fac, 0x7fa4f5b0, 0xf5b0d07e, 0xd07b7fb4, 
+    0x7fbcf5b0, 0x2003d078, 0x78307030, 0xf860f7f2, 0x70084920, 0x0000f996, 0xf804f7f8, 0x0000e03c, 
+    0xd0034228, 0x00030220, 0x000304f0, 0x000302e0, 0x00030215, 0x0003ce18, 0x00030306, 0x00030242, 
+    0x00030214, 0x00030be4, 0x00030f80, 0x0003021b, 0x00030216, 0x0003021a, 0x00030341, 0x00030343, 
+    0x0003021d, 0x0003021c, 0x000302e8, 0x000301d9, 0x000301d8, 0x000301da, 0x00030284, 0x00030394, 
+    0x00030285, 0x00030c30, 0x00030346, 0xd03c801c, 0x00030318, 0x00030223, 0xf956f7ed, 0xf7f97830, 
+    0x48fef9a7, 0x1c496801, 0x20026001, 0xffd8f7f1, 0x600849fb, 0xf7ed7830, 0x48faffc4, 0x68012200, 
+    0xf7f12002, 0x48f8ffe3, 0x78312200, 0x212670c1, 0xa004f880, 0x46018001, 0x0000f8db, 0xffe1f00e, 
+    0xe0031d01, 0xe005e004, 0xe005e081, 0xe02ad023, 0xe7892004, 0xe7872005, 0x230048ec, 0xf241220c, 
+    0xf0120100, 0x2007ff7c, 0x49e98038, 0x68682200, 0xffc7f00e, 0xd1081d01, 0x205af240, 0xe3e3e10e, 
+    0x220049e3, 0xf00e6868, 0x1d40ffbc, 0xaf6df47f, 0x205bf240, 0xf240e102, 0xe0ff2090, 0x220049da, 
+    0xf00e4618, 0x1d40ffae, 0x48dad010, 0x28017800, 0x48d9d010, 0x68012200, 0xf7f12001, 0x48d7ff97, 
+    0x28017800, 0x2003d01d, 0xe4888028, 0x2091f240, 0xe132e0e4, 0xf8a92120, 0x49cd1000, 0x68682200, 
+    0xff8ff00e, 0xd1071d01, 0x2098f240, 0x49c8e0d6, 0x68682200, 0xff85f00e, 0xd1e61d40, 0x2099f240, 
+    0x2002e0cc, 0x48c6e7e0, 0xf8804657, 0x2002a000, 0xf7f77030, 0x48c3ff37, 0xb9087800, 0xfbb1f7f9, 
+    0x210048c1, 0xff01f012, 0x222649b7, 0x70c87830, 0x800a710f, 0xf90cf7f9, 0x220049b3, 0x0000f8db, 
+    0xff5ff00e, 0xd1071d01, 0x20ccf240, 0x49aee0a6, 0x46182200, 0xff55f00e, 0xd1b61d40, 0x20cdf240, 
+    0xe1c0e3f9, 0x465748ae, 0xa000f880, 0x70302001, 0xff08f7f7, 0x780048ab, 0xf7f9b908, 0x48aafbda, 
+    0xf0122100, 0x49a0fed2, 0x78302226, 0x710f70c8, 0xf7f9800a, 0xe004f8dd, 0xe081e00e, 0xe0afe0a8, 
+    0x4999e0c8, 0xf8db2200, 0xf00e0000, 0x1d01ff2a, 0xf240d107, 0xe3ce20ec, 0x22004993, 0xf00e4618, 
+    0x1d40ff20, 0xf240d199, 0xe3c420ed, 0x5280f04f, 0x1000f9b5, 0xf7ea1250, 0xf9b5fdf2, 0xf04f0000, 
+    0x280a0817, 0x4991d007, 0xf0318809, 0xd10e0108, 0xe0b1e059, 0x488ee0cc, 0xb9a07800, 0xf7f12002, 
+    0xb180fff8, 0x88004889, 0x0008f030, 0xf04fd034, 0x21195280, 0xe0d91250, 0xe133e0c0, 0xe174e2b9, 
+    0xe147e140, 0xf004e158, 0x2000f8af, 0xf854f7f3, 0x20014980, 0x60084a71, 0x6812497f, 0x42906808, 
+    0x1c40da01, 0x88086008, 0x4877b281, 0xf0123024, 0x7831fe6c, 0xf7f32000, 0x4978f9a4, 0xf881201c, 
+    0xf7f1a000, 0x2000ffb5, 0xf9b7f7f7, 0xe154e165, 0xe35ae230, 0xe365e33b, 0xf7f12002, 0x2009ff98, 
+    0x486f8028, 0xf8a72200, 0x49618000, 0xf00e6800, 0x1d01feb8, 0xab14f47f, 0x302cf240, 0xe285e35b, 
+    0x302df240, 0x2803e357, 0x2804d015, 0x2802d034, 0x2808d045, 0x2809d05e, 0x2002d1a9, 0xfe71f7f1, 
+    0x2200485f, 0x8000f8a7, 0x68004951, 0xfe99f00e, 0xd0601d01, 0x2010e067, 0x485a8038, 0x494c2200, 
+    0xf00e6800, 0x1d01fe8e, 0xf240d108, 0xe332303a, 0x22004854, 0x68004946, 0xfe83f00e, 0xd0081d40, 
+    0xe6e12004, 0xe10de055, 0xe134e119, 0xe1eee1ed, 0xf240e1fa, 0xe31e303b, 0x80382012, 0x2200484a, 
+    0x6800493b, 0xfe6df00e, 0xf47f1d01, 0xf240aadf, 0xe3103042, 0x3043f240, 0x2005e30d, 0x2011e6c4, 
+    0x48428038, 0x49322200, 0xf00e6800, 0x1d01fe5a, 0xf240d108, 0xe2fe304a, 0x2200483c, 0x6800492c, 
+    0xfe4ff00e, 0xd1e81d40, 0x304bf240, 0xe1cee2f3, 0xe218e1f9, 0x80382016, 0x22004835, 0x68004924, 
+    0xfe3ff00e, 0xf47f1d01, 0xf240aaca, 0xe2e23052, 0x3053f240, 0xf240e2df, 0xe2dc305c, 0x2200491c, 
+    0xf00e4660, 0x1d40fe2e, 0xadbdf47f, 0x305df240, 0xf9b5e2d1, 0xf04f1000, 0x46405280, 0xfcfff7ea, 
+    0x8800481a, 0x0008f030, 0xe002d112, 0xfcf7f7ea, 0xf9b5e5a9, 0x21140000, 0xd03b2804, 0xd0542805, 
+    0xd06c2806, 0xd0762807, 0xd0372808, 0xd0352809, 0x46402118, 0x5280f04f, 0x0000e7e8, 0x00047f78, 
+    0x00030370, 0x000303a0, 0x0003ce18, 0xd28e0040, 0x000304f0, 0x00030284, 0x0003039c, 0x0003031c, 
+    0x00030306, 0x0003021d, 0xd003511c, 0x00030220, 0x00030c5a, 0x00047f7c, 0x00047f80, 0x000301dc, 
+    0x000304dc, 0x00030460, 0x00030480, 0x00030470, 0x000304cc, 0x780048fe, 0xd0062803, 0x220048fd, 
+    0x20016801, 0xfdc2f7f1, 0x48fce55d, 0x80392200, 0x680049f9, 0xfdc5f00e, 0xf47f1d01, 0xf240aa66, 
+    0xe268307e, 0x307ff240, 0x2013e265, 0x48f48038, 0x49f12200, 0xf00e6800, 0x1d01fdb4, 0xf240d108, 
+    0xe258308c, 0x220048ee, 0x680049eb, 0xfda9f00e, 0xd0011d40, 0xe6072006, 0x308df240, 0x48e7e24b, 
+    0x80392200, 0x680049e4, 0xfd9bf00e, 0xd1081d01, 0x3094f240, 0xe00be23f, 0x220049df, 0xf00e4638, 
+    0x1d40fd90, 0x2007d001, 0xf240e5ee, 0xe2323095, 0x80382015, 0x220048db, 0x680049d7, 0xfd81f00e, 
+    0xd1081d01, 0x309cf240, 0x48d6e225, 0x49d22200, 0xf00e6800, 0x1d40fd76, 0x2008d001, 0xf240e5d4, 
+    0xe218309d, 0xf04f48d0, 0x78000200, 0x49cfb108, 0x49cfe000, 0xf7f12001, 0x200afd59, 0xf8dfe5c4, 
+    0x200e8334, 0xf8988028, 0x07c00000, 0x2101d18c, 0xf86ef7f5, 0xf9b82000, 0x1c471000, 0x07c94139, 
+    0x2201d105, 0x4611b2c3, 0xf7f64610, 0xb238f9b1, 0xdbf02804, 0x2003e4d7, 0xfec8f7f8, 0x7030b240, 
+    0xd1152803, 0x880048bc, 0x7facf5b0, 0xf5b0d008, 0xd0057fa4, 0x7fb4f5b0, 0xf5b0d002, 0xd1077fbc, 
+    0x70302005, 0x230848b5, 0x213c2202, 0xfcd7f012, 0xf7f17830, 0x49b2fd3d, 0x4fb22300, 0x70082206, 
+    0x2140200f, 0x46388028, 0xfcc9f012, 0x46382300, 0x21102204, 0xfcc3f012, 0x46382300, 0x21022201, 
+    0xfcbdf012, 0x46382300, 0x461a2101, 0xfcb7f012, 0x23014fa5, 0x21402206, 0xf0124638, 0x2300fcb0, 
+    0x22024638, 0xf0122104, 0x49a0fcaa, 0xa000f8cd, 0x780b7830, 0x780a499e, 0x7809499e, 0xfbbcf7ed, 
+    0xf7f82000, 0x4896ffa8, 0x46407801, 0xfd10f7f1, 0x21002700, 0xf7f24608, 0x2200fe19, 0x0300f647, 
+    0x46104611, 0xa000f8cd, 0xffa6f7f4, 0x7801488c, 0xf7f14640, 0xf240fcfd, 0x464011f4, 0xfb61f7ea, 
+    0x22004886, 0x304221ff, 0xfc87f012, 0x46404601, 0xfb46f7ea, 0x46404988, 0xfb42f7ea, 0xb23f1c7f, 
+    0xd01a2f40, 0x2200487d, 0x304221ff, 0xfc75f012, 0xd0ce28ff, 0xf7f37830, 0x4880fa3c, 0x78312200, 
+    0x212670c1, 0xa004f880, 0x46018001, 0x0000f8db, 0xfca7f00e, 0xd00a1d01, 0x4f79e011, 0xf0124638, 
+    0xf040fc31, 0x46380104, 0xfc2ff012, 0xf240e7e2, 0xe1404048, 0x22004971, 0xf00e4618, 0x1d40fc92, 
+    0xac21f47f, 0x4049f240, 0x2010e135, 0x2002e4ec, 0xfc57f7f1, 0xf7f17830, 0x4961fc9b, 0xf9967008, 
+    0xf0080000, 0xe40efdf5, 0xf7ff2001, 0x211bb9bc, 0xf04f4647, 0x46405280, 0xfb51f7ea, 0x78004861, 
+    0x2112b1c0, 0xf04f4638, 0xf7ea5280, 0x485efb48, 0x21012200, 0xfc21f012, 0xd1e42800, 0x21014f5b, 
+    0xf0107838, 0x2301f9a1, 0x22007838, 0xf0104619, 0xe4bafb8c, 0xfb55f7f3, 0x23004855, 0x21042202, 
+    0xfbfdf012, 0x211ce7e3, 0xf04f4640, 0xf7ea5280, 0x2001fb26, 0xfd2cf010, 0xf8a92006, 0x49360000, 
+    0x68682200, 0xfc3df00e, 0xd1071d01, 0x40a0f240, 0x4931e0e1, 0x68682200, 0xfc33f00e, 0xd1b21d40, 
+    0x40a1f240, 0x780ae0d7, 0xd02b2a01, 0x780ab117, 0xd04a2a01, 0xd1a62801, 0x28007808, 0x211fd1a3, 
+    0xf04f4640, 0xf7ea5280, 0x483afafa, 0xb1407800, 0x78314839, 0x48397803, 0x48397802, 0xf7f47800, 
+    0x4832ff94, 0x78012200, 0x70c1482c, 0x71012101, 0x80012126, 0xf8db4601, 0xf00e0000, 0x1d01fc02, 
+    0xe0a4d025, 0x4640211d, 0x5280f04f, 0xfad7f7ea, 0x23014827, 0x21042202, 0xfba1f012, 0x23014824, 
+    0x21042202, 0xf0121e80, 0xf7f3fb9a, 0xf7f3f9d3, 0x4820facc, 0xb1487800, 0x7831481f, 0x481f7803, 
+    0x481f7802, 0xe03d7800, 0xe05be086, 0xe076e03c, 0x00030214, 0x0003039c, 0x000304f0, 0x000304a8, 
+    0x00030490, 0x000304bc, 0x00030c59, 0x0094c5f0, 0x00b71b00, 0x00030216, 0x00030318, 0xd0060000, 
+    0x00030223, 0xd0034228, 0xd03c8310, 0x000302a7, 0x000302a6, 0x00030394, 0xdcba01f5, 0x0003ce18, 
+    0xd003517c, 0x00030341, 0xd2154120, 0x00030304, 0xd003902c, 0x00030308, 0x000303b9, 0x000303b8, 
+    0x00030307, 0xff21f7f4, 0x2200482b, 0x482b7801, 0x210170c1, 0x21267101, 0x46018001, 0x0000f8db, 
+    0xfb8ff00e, 0xd1071d01, 0x40caf240, 0x4923e033, 0x46182200, 0xfb85f00e, 0xf47f1d40, 0xf240ad69, 
+    0xe02840cb, 0x4640211e, 0x5280f04f, 0xfa57f7ea, 0xf8a92006, 0x491a0000, 0x68682200, 0xfb71f00e, 
+    0xd1071d01, 0x40d6f240, 0x4915e015, 0x68682200, 0xfb67f00e, 0xd1e01d40, 0x40d7f240, 0xf240e00b, 
+    0xe00840f0, 0x2200490d, 0xf00e4618, 0x1d40fb5a, 0xf240d1d3, 0x86a040f1, 0x8ff8e8bd, 0x22004809, 
+    0xb5102101, 0xf998f00e, 0x20052108, 0xfaf6f00e, 0x39084903, 0xbd106048, 0x00030304, 0x0003ce18, 
+    0x000304f0, 0x00014fbb, 0x4ff0e92d, 0x94e0f8df, 0xf8df2404, 0xb09384e0, 0x46832700, 0x0a08f10d, 
+    0x464d2600, 0x46312301, 0x46182200, 0x8900e9cd, 0xff8df7ef, 0x00fcf8b8, 0xf100fb10, 0x00fcf8b5, 
+    0x1100fb10, 0x00f6f8b8, 0xf200fb10, 0x00f6f8b5, 0x2200fb10, 0x00f0f8b8, 0xfb104411, 0xf8b5f300, 
+    0xfb1000f0, 0xf8b83300, 0xfb1000ea, 0xf8b5fc00, 0x465500ea, 0xc000fb10, 0x44084418, 0x1106eb0a, 
+    0x0027f841, 0xf2412100, 0xf7f10000, 0x1c76fb21, 0x2e04b276, 0x1c7fdbc5, 0x42a7b23f, 0x2700dbc0, 
+    0xe0142100, 0xb2001c48, 0x1207eb05, 0xe00b4684, 0x3021f852, 0x6020f852, 0xdd0342b3, 0x6021f842, 
+    0x3020f842, 0xb2001c40, 0xdbf142a0, 0x42a14661, 0x1c7fdbe8, 0x2f04b27f, 0xeb04dbe2, 0x200071d4, 
+    0xeb05104a, 0xf8511100, 0xf84b3022, 0x1c403020, 0x2804b240, 0xb013dbf5, 0x8ff0e8bd, 0x4ffee92d, 
+    0xb3f4f8df, 0x20004682, 0x46044689, 0x49fa9002, 0xeb0a2308, 0x22812644, 0xf0124630, 0xeb09fa0e, 
+    0x49f62544, 0x46282308, 0xf0122281, 0x4bf3fa06, 0x465a2081, 0x7180f5c0, 0x7021f852, 0x7020f842, 
+    0x1021f853, 0xf8434249, 0x1c401020, 0x28ffb200, 0x2708ddf0, 0x83a8f8df, 0x49e84aea, 0x9b0248e6, 
+    0x8700e9cd, 0xfe38f012, 0x218048e7, 0xfa04f013, 0x4ae14be2, 0x990248e3, 0x8700e9cd, 0xfb42f012, 
+    0x230848dd, 0x46312281, 0xf9e8f012, 0x230848db, 0x46292281, 0xf9e2f012, 0xb2641c64, 0xdbb62c04, 
+    0x8ffee8bd, 0x4bd9b57c, 0x2540eb01, 0x781b4cd8, 0xeb027826, 0xf0032440, 0x2e030301, 0x2301d003, 
+    0x22004601, 0xb2c1e017, 0x4ad2b91b, 0x2a017812, 0x4ad1d008, 0x2a1b7812, 0x2802d004, 0x2803d007, 
+    0xe005d005, 0x2801b108, 0x2103d102, 0x2100e000, 0x22002301, 0x2001b249, 0x5400e9cd, 0xfea7f7ef, 
+    0xf8a58820, 0x20000100, 0xf8a48020, 0xbd7c0100, 0xe92d48c3, 0xf99041f0, 0x48c21000, 0x29044fbf, 
+    0xd0057800, 0xd00e2905, 0xd2122841, 0xe0112001, 0xd90128be, 0xe00d2000, 0x200249b5, 0x29037809, 
+    0x2005d108, 0x284be006, 0x2006d201, 0x2008e002, 0x2004e000, 0xf8df4ab4, 0x2100c2ac, 0x00c0ebc0, 
+    0x080cf06f, 0x0ec0eb02, 0xeb072000, 0xe9c404c1, 0x46400000, 0xd5001a0b, 0x28001a43, 0x4242da01, 
+    0x4602e000, 0x5023f85c, 0x280e1c40, 0x6022f85e, 0x2300e9d4, 0x2306fbc5, 0x2300e9c4, 0x1c49dbea, 
+    0xdbe12911, 0xeb072000, 0x680a01c0, 0x040b8889, 0x4112ea43, 0x1020f84c, 0x28111c40, 0xf04fdbf3, 
+    0xf8dc5100, 0x42880000, 0x2000dc12, 0x2020f85c, 0xf84c0052, 0x1c402020, 0xdbf72811, 0xf85ce7f1, 
+    0x10522020, 0x2020f84c, 0x28111c40, 0xe001dbf7, 0x4180f04f, 0x0000f8dc, 0xf04f4288, 0xdcee0000, 
+    0x1020f85c, 0x5100f101, 0x1020f84c, 0x28111c40, 0xe8bddbf6, 0xe92d81f0, 0x460547fc, 0xf04f4c76, 
+    0xf04f36ff, 0xf8dd0900, 0xeb01a028, 0xeb022745, 0x46982245, 0x464b4630, 0x1013f837, 0xfc01fb11, 
+    0x1013f832, 0xc101fb11, 0x1023f844, 0xdd014281, 0x4608b103, 0xb21b1c5b, 0xdbed2b81, 0xd07d2800, 
+    0xf44f2200, 0xe0020100, 0xb2121c52, 0x42881040, 0x2a00dafa, 0x2100dd09, 0x3021f854, 0xf8444113, 
+    0x1c493021, 0x2981b209, 0x2100dbf6, 0x0280f44f, 0x1c49e002, 0x0040b209, 0xdbfa4290, 0xdd092900, 
+    0xf8542000, 0x408a2020, 0x2020f844, 0xb2001c40, 0xdbf62881, 0x20402100, 0x2021f854, 0xda012a40, 
+    0x0021f844, 0xb2091c49, 0xdbf52981, 0x23814a4a, 0x46114630, 0xf87cf013, 0xf5c02081, 0xf8547180, 
+    0xf8441021, 0x1c401020, 0x28ffb200, 0x4842ddf5, 0xeb082281, 0xf0122185, 0xf04ff851, 0x483f6180, 
+    0x1025f84a, 0xf0131489, 0x2108f8b7, 0x4a3d483c, 0xe9cd464b, 0x49390100, 0xf0124837, 0x4939fcdd, 
+    0x5200f04f, 0x2000e009, 0x3020f851, 0xf841005b, 0x1c403020, 0x281fb200, 0x6808dbf6, 0xddf24290, 
+    0x4280f04f, 0x42906808, 0x0000f04f, 0xf851dd0b, 0x105b3020, 0x3020f841, 0xe0001c40, 0xb200e00d, 
+    0xdbf4281f, 0xf851e7ee, 0xf1022020, 0xf8415200, 0x1c402020, 0x281fb200, 0xe8bddbf5, 0xe92d87fc, 
+    0xf5004ff7, 0x460776c8, 0x08c8f100, 0x507ef04f, 0x68386030, 0xfe0cf014, 0x68784604, 0xf0144240, 
+    0x4621fe07, 0xfd06f014, 0x46046070, 0xf0146838, 0xf014fdff, 0x4689fc6b, 0x46054621, 0xf0144608, 
+    0xf014fe23, 0x4b19fc63, 0xf0142200, 0x464bfa9d, 0xf014462a, 0xf013f965, 0x4682fe59, 0x24029802, 
+    0x0b01f100, 0x2501e078, 0x0900f04f, 0x0000e02f, 0x000339dc, 0x000331dc, 0x000369dc, 0x000371dc, 
+    0x0002bb10, 0x000341dc, 0x000343dc, 0x000301c8, 0x00030394, 0x000302a4, 0x00030250, 0x000349dc, 
+    0x00030222, 0x0003031e, 0x00030500, 0x3ff00000, 0x0025f857, 0xfdbcf014, 0xf8561b61, 0xf0141021, 
+    0x4649fde3, 0xfc4ef014, 0x46811c6d, 0x42a5b22d, 0xf857dbee, 0xf0140024, 0x4649fdab, 0xfc42f014, 
+    0x4000f080, 0xf0144651, 0x2501fca5, 0xe00d4681, 0xf8561b60, 0x46481020, 0xfdc6f014, 0x1025f856, 
+    0xfc30f014, 0x0025f848, 0xb22d1c6d, 0xdbef42a5, 0x46084649, 0x9024f848, 0xfdb6f014, 0xfbf6f014, 
+    0x22004bfe, 0xfa30f014, 0x46894605, 0xf0144650, 0x462afbed, 0xf014464b, 0xf013f8f3, 0x4682fde7, 
+    0x1c642001, 0xf858e005, 0xf8461020, 0x1c401020, 0x42a0b200, 0xb224dbf7, 0xdb84455c, 0x24009d02, 
+    0xe00b1cad, 0x0024f856, 0xf014210f, 0xf014ff2e, 0x9901fd23, 0x0024f841, 0xb2241c64, 0xdbf142ac, 
+    0xe92de5ce, 0x46815ffc, 0x460f48e5, 0xf46f4616, 0xf04f719a, 0x88000b00, 0xeb000440, 0x14054041, 
+    0x2500d501, 0x2defe002, 0x25efdd00, 0xa374f8df, 0x48dc2400, 0x1100f240, 0xff9ef012, 0x1104eb04, 
+    0x20004652, 0x0181eb09, 0x0c05eb00, 0x3020f851, 0xb2001c40, 0x2811029b, 0x302cf842, 0x2108dbf4, 
+    0x4bd248d1, 0xe9cd4ad2, 0x48ce0100, 0xf0124659, 0xf06ff8c9, 0x48ce0809, 0x46432281, 0x2184eb07, 
+    0xff1bf011, 0x228148c9, 0x2184eb06, 0xf0114643, 0x1c64ff14, 0x2c04b264, 0xe8bddbcb, 0xe92d9ffc, 
+    0xb0854fff, 0xe9dd2500, 0xe9cd0112, 0x98050100, 0xeb002400, 0x90032045, 0xeb009806, 0x90022045, 
+    0xeb009800, 0x98082b85, 0x2a45eb00, 0xeb009801, 0x98072985, 0x2845eb00, 0x6024f85b, 0x1014f93a, 
+    0x3024f859, 0x0014f938, 0xf206fb00, 0x2203fb01, 0xfb104343, 0xfb01f000, 0xfb113316, 0x01520001, 
+    0x10c7015e, 0x46394610, 0xfea6f012, 0xf8219903, 0x46390014, 0xf0124630, 0x9902fe9f, 0x0014f821, 
+    0xb2241c64, 0xdbd72c81, 0xb26d1c6d, 0xdbbe2d04, 0x46012000, 0xeb029a05, 0x1c402240, 0x2804b240, 
+    0xdbf78011, 0x0105e9dd, 0xe8bdb009, 0xe4d54ff0, 0x4ffee92d, 0x460e4605, 0xe9dd2000, 0x9002980c, 
+    0xf7ef2001, 0x2000fced, 0xfceaf7ef, 0xa240f8df, 0xf8df2400, 0x4f8bb238, 0x498d2308, 0xeb092281, 
+    0xf0112044, 0x4989feda, 0x22812308, 0x2044eb08, 0xfed3f011, 0x46522081, 0xf5c0465b, 0xf8527180, 
+    0xf842c021, 0xf853c020, 0x42491021, 0x1020f843, 0xb2001c40, 0xddf028ff, 0x487b2108, 0x9b024a79, 
+    0x0100e9cd, 0x487a4979, 0xfb06f012, 0x1ba92000, 0xf8571c49, 0x410a2020, 0x2020f847, 0xb2001c40, 
+    0xdbf62881, 0x217f4873, 0xfec6f012, 0x46212001, 0x461a2300, 0x7000e9cd, 0xfb14f7ef, 0xb2641c64, 
+    0xdbb92c04, 0xd0042d01, 0xe8bd2007, 0xf7f34ffe, 0x2006b8d3, 0xb570e7f9, 0xf0052000, 0x4d66fe69, 
+    0x22032300, 0x46282108, 0xfed9f011, 0x78204c63, 0xd02d2801, 0x46282300, 0x21042202, 0xfecff011, 
+    0x46282301, 0x46192200, 0xfec9f011, 0xf7f32001, 0x2301f8ca, 0x2200485a, 0xf0114619, 0x4859fec0, 
+    0xf9904959, 0x28050000, 0x780ad014, 0xf04f2804, 0xd0130101, 0xf7f22078, 0x2100f95a, 0x1000f240, 
+    0xff26f7f0, 0xb1587820, 0x4070e8bd, 0xbf2bf7f1, 0xe7d02301, 0x2101780a, 0xe7ec2089, 0xe7ea208e, 
+    0x4070e8bd, 0xbee1f7f1, 0x4ff0e92d, 0xb0894847, 0xc80f466d, 0x000fe88d, 0x90042000, 0xf8451e41, 
+    0x1c401020, 0x2804b240, 0x2000dbf9, 0xfb64f7f1, 0x24004f3a, 0x80f8f8df, 0x0b30f242, 0x90f4f8df, 
+    0xf2402600, 0x78382a00, 0xd0032801, 0x0000f998, 0xd0054286, 0xd0502c00, 0x46304651, 0xfd17f7f7, 
+    0xb2761c76, 0xdbee2e04, 0xfe7cf7f1, 0x4a00f04f, 0x465946d9, 0xf7e94650, 0x482ffd50, 0x22112300, 
+    0x3100f44f, 0xfe44f011, 0xf7f12001, 0xa805fb35, 0xfb6af7ff, 0xf7f12000, 0x2000fb2f, 0xae04aa05, 
+    0x3020f855, 0x1020f852, 0xdd024299, 0xf8455434, 0x1c401020, 0x2804b240, 0x4649dbf2, 0xf7e94650, 
+    0x1c64fd2c, 0x2c04b264, 0x2000dbb8, 0x4480f04f, 0x1020f855, 0xda0042a1, 0x1c40460c, 0x2804b240, 
+    0x46b9dbf6, 0xa054f8df, 0xf8df4647, 0x25008054, 0x0000f899, 0xd0292801, 0xe02ee024, 0x3ff00000, 
+    0x00030320, 0x000341dc, 0x0002bb10, 0x000371dc, 0x000369dc, 0x000343e0, 0xd00350e6, 0x0003031c, 
+    0xd0031012, 0x00030222, 0x00030223, 0x0002b6f8, 0x00030227, 0xfffffd00, 0xd1800000, 0xfffffa00, 
+    0xfffffe00, 0x0000f997, 0xd0104285, 0xb1305770, 0xd0062801, 0xd0062802, 0x4649e009, 0x4651e77d, 
+    0x49fae002, 0x4641e000, 0xf7f74628, 0x1c6dfc90, 0x2d04b26d, 0xf04fdbbc, 0x46594000, 0xfccdf7e9, 
+    0xf2432080, 0xf7e901a0, 0xf89dfcbc, 0xf99d1010, 0xf99d0013, 0xea402012, 0xf99d6101, 0x04000011, 
+    0x2002ea40, 0x20804301, 0xfc9af7e9, 0x20809900, 0xfc96f7e9, 0x20809901, 0xfc92f7e9, 0x20809902, 
+    0xfc8ef7e9, 0x20809903, 0xfc8af7e9, 0x4620b009, 0x8ff0e8bd, 0x4edeb570, 0xb9087830, 0xfdf5f7f1, 
+    0x22002101, 0xf0014608, 0x2100fbdf, 0x2080f44f, 0xfe1ef7f0, 0x22002101, 0xf0014608, 0x48d5fbd5, 
+    0xb1387800, 0xf0012001, 0x2101fdc7, 0x46082200, 0xfbcaf001, 0x682c4dd0, 0x20c0f424, 0x78306028, 
+    0x49cfb9c0, 0x780948cd, 0x6000f990, 0xd0232903, 0x17c81cf1, 0x7090eb01, 0x0003f020, 0xb2401a08, 
+    0xfd8bf7f7, 0xf7ff2001, 0xf7f1fedf, 0x4630fdbe, 0xfd83f7f7, 0xf7ff2001, 0xf7f1fed7, 0xf242fdb6, 
+    0x06480140, 0xfc59f7e9, 0x602c2200, 0x4070e8bd, 0x46082101, 0xbb98f001, 0x578849ba, 0xeb001c40, 
+    0xf02272d0, 0x1a800201, 0x5608b240, 0xe92de7d8, 0x20004ff0, 0xb2d4f8df, 0xf8df1e41, 0xb087a2d4, 
+    0x0105e9cd, 0x0102e9cd, 0x680448af, 0x46072000, 0x46064605, 0x4aaf9004, 0x49af4628, 0xfb22f7ff, 
+    0x4baf48ae, 0x49ac4aab, 0x46289000, 0xfbd3f7ff, 0x46592000, 0xf8514652, 0x1c403020, 0x3026f842, 
+    0xb2001c76, 0x281fb236, 0xf8dfdbf5, 0xeb058298, 0x489e1105, 0xeb082210, 0x46890181, 0xfc6ff7ff, 
+    0xf06f2000, 0xf859027e, 0xf5011020, 0xf3417180, 0x297f214f, 0x1010f824, 0x217fdd00, 0x45414690, 
+    0x1010f824, 0x4611da00, 0x1010f824, 0xb2001c40, 0xdde82810, 0x46012000, 0x2010f834, 0xb2001c40, 
+    0xb2094411, 0xdbf72811, 0xf04f8c20, 0xf8df0e10, 0x1a40923c, 0xeb09498c, 0x84201305, 0x1c05eb01, 
+    0x2000498b, 0x1105eb01, 0x0240eb04, 0x0f40ebbe, 0xb2527892, 0x541a540a, 0x2000f80c, 0x42badd02, 
+    0x4617dd00, 0xb2001c40, 0xdbed2810, 0xf7ef4628, 0x1c6dfa20, 0x2d04b26d, 0xf7f0db8d, 0x487dfa1e, 
+    0x0000f990, 0xd0042803, 0xd0062804, 0xd0092805, 0x4868e06d, 0xb1487800, 0x4877e069, 0x28967800, 
+    0xe064d304, 0x78004874, 0xd2602882, 0x78004873, 0x2500bbf0, 0x4659462e, 0x46532000, 0x2026f853, 
+    0xb2361c76, 0x5200f1a2, 0x2020f841, 0xb2001c40, 0xdbf3281f, 0xfabcf7ff, 0xeb054862, 0x22101105, 
+    0x0781eb00, 0x46394859, 0xfbe9f7ff, 0x46422000, 0x1020f857, 0x7180f501, 0x214ff341, 0xf824297f, 
+    0xdd001010, 0x4291217f, 0x1010f824, 0x4611da00, 0x1010f824, 0xb2001c40, 0xdde92810, 0x46012000, 
+    0x2010f834, 0xb2001c40, 0xb2094411, 0xe0002811, 0xdbf5e01d, 0xeb098c20, 0x1a401305, 0x8420494a, 
+    0xeb012000, 0x494a1705, 0x1105eb01, 0x0240eb04, 0x540a7892, 0x543a541a, 0xb2001c40, 0xdbf52810, 
+    0xf7ef4628, 0x1c6df9a6, 0x2d04b26d, 0x2200dba3, 0x46112001, 0xfa88f001, 0x78004831, 0xd0062803, 
+    0x7800483d, 0xd80228fa, 0x7800483c, 0x2000b390, 0x22009002, 0x46112001, 0xfa76f001, 0x4c389a02, 
+    0xdd762a00, 0x23014837, 0xf00b9906, 0x9806f99d, 0x31c8f44f, 0x0c014348, 0xf0114620, 0xf8dffc16, 
+    0x240080c8, 0x464d4e2a, 0xeb082200, 0xeb051704, 0xeb061304, 0x5c881104, 0x549854b8, 0xb2121c52, 
+    0xdbf82a10, 0xf7ef4620, 0x1c64f964, 0x2c04b264, 0xe053dbea, 0x4923e7ff, 0x23012044, 0x80082210, 
+    0x46104619, 0xfbcff7f1, 0x78014820, 0x2000f44f, 0xfc7ef7f0, 0x9000a803, 0x2301481a, 0xa906aa02, 
+    0xfa89f00a, 0xf7f12000, 0xe7b2f8d7, 0xfffffc00, 0x0003031c, 0x000302d5, 0x00047ffc, 0x00030227, 
+    0x00030394, 0x00030338, 0x000301c4, 0x000341dc, 0x0003ad5c, 0x0003194c, 0x0003114c, 0x00038d4c, 
+    0x00037d4c, 0x000379dc, 0x0003d1ec, 0x0003315c, 0x0003319c, 0x00030222, 0x0003031e, 0x00030284, 
+    0xd003513c, 0x000304f8, 0x00030fec, 0x00030223, 0xf64fe7ff, 0x462071ff, 0xfba7f011, 0x49f84af7, 
+    0xf7ff48f8, 0x49f5fbce, 0x4af84bf7, 0xe9cd48f9, 0x49f7a100, 0xfc13f7ff, 0x780048f7, 0xf44fb938, 
+    0xf6403000, 0xf7e90103, 0xf7f7fa8c, 0x49f0f85a, 0x4bed48f0, 0xe9cd4aed, 0xe9dd0100, 0xf7ff1004, 
+    0x2200fc57, 0x46112001, 0xf9cef001, 0xe5dfb007, 0x4ff0e92d, 0xb09948ea, 0x0904f10d, 0x4ee94de7, 
+    0xaf0e2400, 0x0801f04f, 0xe889c80f, 0x4be5000f, 0x20012200, 0x8000f8cd, 0xf7efb261, 0x2000f85a, 
+    0x0cc4eb07, 0xe9cc4602, 0xf8560000, 0x1c401020, 0x3004f8dc, 0x2880b200, 0x2301fbc1, 0x2300e9cc, 
+    0x1c64dbf3, 0x2c04b2e4, 0xa816d3e1, 0xfbd9f7f2, 0x46bb2400, 0x0a58f10d, 0xaf064626, 0x465046a1, 
+    0x1014f93a, 0xdd02291e, 0xf820211e, 0xf9301014, 0x29001014, 0xf820da01, 0xf93a9014, 0x48ca1014, 
+    0x0011f830, 0x0c810382, 0xce00fba2, 0xe000fb01, 0x0209fb02, 0x2100205d, 0x3e00fbac, 0xe000fb02, 
+    0x0001fb0c, 0xeb0b0d5a, 0x154301c4, 0x22c0ea42, 0x0100e9d1, 0xeca0f010, 0x02c4eb07, 0x19864690, 
+    0x48bac203, 0x28017800, 0xf857d10c, 0xf7f20034, 0xb280fc33, 0x0100f248, 0xe9c80fc2, 0x18400200, 
+    0x0b02f825, 0xf837a901, 0xf8510034, 0xf1041024, 0xb2e40401, 0x80082c04, 0x48add3b1, 0x28037800, 
+    0x19b6d100, 0xf7f24630, 0x49aafc17, 0x305db280, 0x29126809, 0x2916d001, 0x21a2d102, 0x0a004348, 
+    0x600849a5, 0xe543b019, 0x41f0e92d, 0xf7f22007, 0x2000fce3, 0xfa7cf005, 0x23004c98, 0x3cd02203, 
+    0x46202108, 0xfaebf011, 0x78304e93, 0x489bb110, 0xb1087800, 0xe0002301, 0x46202300, 0x21042202, 
+    0xfaddf011, 0x46202301, 0x46192200, 0xfad7f011, 0xf7f22001, 0x4c92fcd8, 0x22082301, 0x3100f240, 
+    0xf0114620, 0x2301facc, 0x22004620, 0xf0114619, 0x2301fac6, 0x2200488b, 0xf0114619, 0x488afac0, 
+    0x78022101, 0xf9b04889, 0xf7f10000, 0xf240fd3e, 0x21001700, 0xf7f04638, 0x2101fb2b, 0x46082200, 
+    0xf8e2f001, 0x682c4d82, 0x20c0f424, 0x20016028, 0xf856f7ef, 0x46382100, 0xfb1af7f0, 0x28017830, 
+    0xf7f1d018, 0x487bfb2e, 0x22112300, 0x3100f44f, 0xfa7ef011, 0xf7f02001, 0xf242ff6f, 0x06c80130, 
+    0xf97bf7e9, 0x20012200, 0xf0014611, 0x602cf8bd, 0x81f0e8bd, 0xf7ef2000, 0xf7f1f833, 0xe7e2fac6, 
+    0x5ff0e92d, 0xfee4f7ff, 0xf04f496b, 0x48620891, 0x53aaf240, 0xf2404a70, 0x4e6855dc, 0x68007809, 
+    0x29014f67, 0xc19cf8df, 0xe19cf8df, 0x919cf8df, 0xa19cf8df, 0xb19cf8df, 0xf9924c68, 0xd0061000, 
+    0xd0432903, 0xd0272905, 0xd0752904, 0x2903e05f, 0x2905d004, 0x2904d020, 0xe058d02b, 0x7faff5b0, 
+    0xf240dd0b, 0x428841e2, 0x4608dd00, 0xeb004b5c, 0xf5a10140, 0x39ba5104, 0x287de00a, 0x207dda00, 
+    0xeb004b58, 0xebc101c0, 0xf5a11180, 0x39aa4139, 0x3000fb01, 0xe0390c00, 0x7fc3f5b0, 0x4298dd4f, 
+    0xebc0dc4b, 0xeb061140, 0xfb010181, 0x0d407000, 0xf5b0e02c, 0xdd507f9b, 0xdd0042a8, 0xf2404628, 
+    0xfb001151, 0xe0a29301, 0xe01f20fa, 0x7fa1f5b0, 0xf240db0d, 0x4288512c, 0x4608dd00, 0x21a94b42, 
+    0x44194341, 0xfb014b41, 0x0d803000, 0xeba0e00e, 0x493f1000, 0x0040eb00, 0x1000ebc0, 0x1040eb01, 
+    0x4007f3c0, 0x287b7020, 0x207bd901, 0x48207020, 0x28017800, 0x2802d070, 0x4936d06e, 0x43017809, 
+    0x2803d06a, 0xf992d068, 0x28040000, 0x2805d072, 0x2803d001, 0xe09ad06f, 0x4618e05f, 0xf240e7b1, 
+    0xfb016151, 0xfb01c100, 0xf3c0e000, 0x70205047, 0xd9dc2891, 0x8000f884, 0xe05de7d9, 0x0003bd5c, 
+    0x0003ad5c, 0x000379dc, 0x0003194c, 0x0003114c, 0x0003294c, 0x0003214c, 0x0003031c, 0xd00351bc, 
+    0x0002b708, 0x000341dc, 0x00030ae6, 0x00030278, 0x00030394, 0x000301cc, 0x000303b4, 0x00030284, 
+    0xd0030444, 0xd0031012, 0x00030223, 0x00030320, 0x00047ffc, 0xd1800000, 0x00030264, 0xfffa6eca, 
+    0x10133079, 0xffe89b85, 0x1dcb8bb0, 0xfff063b3, 0x2ec83679, 0xffa22500, 0x00030222, 0x0003031e, 
+    0x005d41c4, 0x00c96ba6, 0xfff7c4ea, 0x18e997a9, 0x00a84018, 0x00030312, 0xf5b0e01c, 0xdd0b7f9b, 
+    0xdd0042a8, 0xf2404628, 0xfb001151, 0xfb039301, 0xe76aa000, 0xe025e037, 0x7185f641, 0xb301fb00, 
+    0xfb03491a, 0xf3c01000, 0x70205087, 0xf63f28fa, 0xe76caf4b, 0x0000f992, 0xd0082804, 0xf47f2805, 
+    0x7820af78, 0xd20b283c, 0xd303280c, 0x7820e006, 0xd2012819, 0xe00908c0, 0xe0073819, 0xe005380c, 
+    0xe0031f40, 0x28197820, 0x3010d300, 0xf6407020, 0x030d0100, 0xf7e94628, 0x7821f824, 0xe8bd4628, 
+    0xf7e95ff0, 0x7820b80d, 0x0000e7de, 0x61737224, 0x47f0e92d, 0x46894692, 0x46062200, 0x46032101, 
+    0x46204cfe, 0xf914f011, 0x46331d25, 0x46282200, 0xf0112101, 0xf105f90d, 0x46330804, 0x46402200, 
+    0xf0112101, 0x4633f905, 0x0604f108, 0x46302200, 0xf0112101, 0x2208f8fd, 0x4620464b, 0x46390157, 
+    0xf8f6f011, 0x464b2208, 0x46284639, 0xf8f0f011, 0x464b2208, 0x46404639, 0xf8eaf011, 0x464b2208, 
+    0x46304639, 0xf8e4f011, 0x4653013f, 0x4639220c, 0xf0114620, 0x220cf8dd, 0x46394653, 0xf0114628, 
+    0x220cf8d7, 0x46394653, 0xf0114640, 0x4653f8d1, 0x46304639, 0x47f0e8bd, 0xf011220c, 0xe92db8c9, 
+    0x4ed75ff0, 0xf8df2400, 0xf8df835c, 0x3680a35c, 0xf1084dd3, 0x4fd30880, 0x0a80f10a, 0x9348f8df, 
+    0xb348f8df, 0x19602140, 0xf8aff011, 0x19a02140, 0xf8abf011, 0x19e02140, 0xf8a7f011, 0xeb042140, 
+    0xf0110008, 0x2140f8a2, 0x0009eb04, 0xf89df011, 0xeb042140, 0xf011000a, 0x2140f898, 0x000beb04, 
+    0xf893f011, 0x214048c1, 0x44203080, 0xf88df011, 0x214048bf, 0xf0114420, 0x48bdf888, 0x30802140, 
+    0xf0114420, 0x48bbf882, 0x44202140, 0xf87df011, 0x214048b8, 0x44203080, 0xf877f011, 0x214048b6, 
+    0xf0114420, 0x48b4f872, 0x30802140, 0xf0114420, 0x48b2f86c, 0x44202140, 0xf867f011, 0x214048af, 
+    0x44203080, 0xf861f011, 0x2c201ca4, 0x4ea4d3aa, 0x4fa52400, 0x1500f240, 0x8294f8df, 0xf8df3e1c, 
+    0x3f1c9298, 0x081cf1a8, 0x091cf1a9, 0x19a04629, 0xf84bf011, 0x462919e0, 0xf847f011, 0x0008eb04, 
+    0xf0114629, 0xeb04f842, 0x46290009, 0xf83df011, 0x2c081ca4, 0xf8dfd3ea, 0x27009244, 0xf1a94e98, 
+    0xf1090984, 0x25000804, 0x03202400, 0x2005ea40, 0x1107ea40, 0xf0114648, 0x7831f822, 0xf7f02040, 
+    0x2100f8b7, 0xf0114640, 0x7831f81a, 0xf7f02040, 0x1c64f8af, 0xd3e82c04, 0x2d021c6d, 0x1c7fd3e4, 
+    0xd3e02f02, 0x24004d7d, 0x81f0f8df, 0x91ecf8df, 0xf1a83d74, 0xf1a9086c, 0xf1050964, 0xf1080a04, 
+    0xe0370b04, 0x2c01b3ac, 0x2c02d041, 0x0300f04f, 0x0204f04f, 0x0110f04f, 0x4648d044, 0xfff8f010, 
+    0x2300486e, 0x21102204, 0xf0103860, 0x1c64fff1, 0x2c04b2e4, 0x2700d3e6, 0x03202400, 0x2107ea40, 
+    0x38544866, 0xffdbf010, 0x20407831, 0xf870f7f0, 0x21004862, 0xf0103850, 0x7831ffd2, 0xf7f02040, 
+    0x1c64f867, 0xd3e82c04, 0x2f021c7f, 0x2400d3e4, 0xe7ffe03b, 0x23004859, 0x21102204, 0xf010387c, 
+    0x4856ffc7, 0x22042300, 0x38782110, 0x2300e7cd, 0x22044628, 0xf0102110, 0x2300ffbb, 0x22044650, 
+    0xe7c22110, 0xf0104640, 0x2300ffb3, 0x22044658, 0xe7ba2110, 0x2c01b1cc, 0x2c02d028, 0x0301f04f, 
+    0x0204f04f, 0x0110f04f, 0x4638d02b, 0xffa0f010, 0x23014842, 0x21102204, 0xf0103860, 0x1c64ff99, 
+    0x2c04b2e4, 0xe8bdd3e6, 0x483c9ff0, 0x22042301, 0x387c2110, 0xff8cf010, 0x23014838, 0x21102204, 
+    0xf0103878, 0x4646ff85, 0xe7e8464f, 0x46282301, 0x21102204, 0xff7cf010, 0x46502301, 0x21102204, 
+    0x4630e7db, 0xff74f010, 0x46582301, 0x21102204, 0xb430e7d3, 0x02c84604, 0xeb004929, 0xeb0010c2, 
+    0x44080043, 0xbc30b2a1, 0xbf5ff010, 0x4605b570, 0x492302c8, 0x10c2eb00, 0x0043eb00, 0x46201844, 
+    0xff50f010, 0xf0104620, 0x8028ff4d, 0xe92dbd70, 0xb09f4ff0, 0x201e4923, 0x085ef04f, 0x223c2722, 
+    0xa808901c, 0xe95af010, 0x6800a01f, 0x2000901d, 0x25009018, 0xe001b246, 0xd2482d02, 0x4631b26a, 
+    0x46142307, 0xf7ffa817, 0xf9bdffd1, 0x4641005c, 0xda034540, 0xdc0242b8, 0xe0004638, 0x46224608, 
+    0x46312307, 0x005cf8ad, 0xffb3f7ff, 0x46222309, 0x4631a817, 0xffbaf7ff, 0x0000e018, 0xd18008f0, 
+    0xd003c400, 0xd003c500, 0xd003cc00, 0xd003cd00, 0xd003d400, 0xd003d500, 0xd003dc00, 0xd003dd00, 
+    0x00030223, 0x0002b718, 0x0d0f0f0f, 0x005cf9bd, 0x45404641, 0x42b8da03, 0x4638dc02, 0x4608e000, 
+    0x23094622, 0xf8ad4631, 0xf7ff005c, 0xa81dff82, 0x2400a908, 0xb005f910, 0x1005ebc5, 0x901b4408, 
+    0x901ab268, 0x981be016, 0x9a1a4631, 0xa8175703, 0xff7cf7ff, 0x005cf9bd, 0x45404641, 0x42b8da03, 
+    0x4638dc02, 0x4608e000, 0x005cf8ad, 0x0014f82d, 0xb2e41c64, 0xdbe6455c, 0xf1ab2400, 0x901e0001, 
+    0x4669e02e, 0x0044eb01, 0xf93d9019, 0xf9b09014, 0xebbaa002, 0xd5000009, 0x991c4240, 0x4288b200, 
+    0x1a40dd1b, 0x70d0eb00, 0xf0121040, 0xf011ff42, 0xf012ff3b, 0xb200fee1, 0x45d14669, 0xeb09da06, 
+    0xebaa0200, 0xf8210000, 0xe0042014, 0x0200eba9, 0xf8214450, 0x99192014, 0x1c648048, 0xb2e4981e, 
+    0xdbce4284, 0x46e92400, 0x981be009, 0x9a1a4631, 0xf9395703, 0xf7ff0014, 0x1c64ff1c, 0x455cb2e4, 
+    0x1c6ddbf3, 0x2d04b2ed, 0xaf46f4ff, 0x1c409818, 0x9018b2c0, 0xf4ff2804, 0xb01faf3c, 0x8ff0e8bd, 
+    0x22002301, 0xb5104619, 0xf01048fe, 0x48fdfe71, 0x22002301, 0x30084619, 0xfe6af010, 0x230148f9, 
+    0x46192200, 0xf0103010, 0x48f6fe63, 0x22002301, 0xe8bd4619, 0x30184010, 0xbe5af010, 0x4ff8e92d, 
+    0x20004df1, 0x46044ff1, 0xf6409000, 0xf8df4a00, 0xf24283c0, 0xf8df0b00, 0x802893bc, 0x2c00e055, 
+    0x2c01d053, 0x8828d07e, 0xf04f2c02, 0xf243020c, 0xb2830100, 0x48e7d077, 0xf010387a, 0x2303fe50, 
+    0x0100f247, 0x464e220c, 0xf0104648, 0x48e1fe48, 0x22092301, 0x1c800259, 0xfe41f010, 0x46302305, 
+    0x21702204, 0xfe3bf010, 0x230148da, 0x4651220a, 0xf0103872, 0x48d7fe34, 0x210c2302, 0x3848461a, 
+    0xfe2df010, 0x230148d3, 0x4659220d, 0xf010383a, 0x1c64fe26, 0x2c04b264, 0x2101dbc1, 0x46082200, 
+    0xfce6f7ff, 0xfd3bf7ff, 0x221048c6, 0x03112300, 0xf0103068, 0x4dc5fdfd, 0x4ec52400, 0x3d2c4fc5, 
+    0xf8df3e2c, 0x3f2c8314, 0x8828e09d, 0xb283220c, 0x029148c1, 0xf010384e, 0x4ebffe02, 0x220c2303, 
+    0x0100f247, 0x4630362c, 0xfdf9f010, 0x22092301, 0x1cb00259, 0xfdf3f010, 0x46302305, 0x21702204, 
+    0xfdedf010, 0x230148b4, 0x4651220a, 0xf0103846, 0x48b1fde6, 0x210c2302, 0x381c461a, 0xfddff010, 
+    0xe0012301, 0xe034e005, 0x220d48ab, 0x380e4659, 0x8828e7ad, 0xb283220c, 0x029148a4, 0xf010387a, 
+    0x2303fdce, 0x0100f247, 0x4638220c, 0xfdc7f010, 0x2301489e, 0x02592209, 0xf0101c80, 0x2305fdc0, 
+    0x22044638, 0xf0102170, 0x4898fdba, 0x220a2301, 0x38724651, 0xfdb3f010, 0x23024894, 0x461a210c, 
+    0xf0103848, 0x4891fdac, 0x220d2301, 0x383a4659, 0x488fe77d, 0xf010387a, 0x2303fda2, 0x0100f247, 
+    0x4646220c, 0xf0104640, 0x4889fd9a, 0x22092301, 0x1c800259, 0xfd93f010, 0x46302305, 0x21702204, 
+    0xfd8df010, 0x23014882, 0x4651220a, 0xf0103872, 0x487ffd86, 0x210c2302, 0x3848461a, 0xfd7ff010, 
+    0x2301487b, 0x4659220d, 0xe750383a, 0x2c01b15c, 0x2c02d00e, 0x0300f04f, 0x0202f04f, 0x0104f04f, 
+    0x4638d00b, 0x2300e00a, 0x22024640, 0xe0052104, 0x46282300, 0x21042202, 0x4630e000, 0xfd5ff010, 
+    0xb2641c64, 0xdbe12c04, 0x2140486c, 0xfd3df010, 0xfec6f7ff, 0xb18cf8df, 0x0000f44f, 0x91a0f8df, 
+    0xa180f8df, 0xf10b0204, 0x90000b08, 0x2102e006, 0x4668464a, 0xfe36f7ef, 0xd01d2801, 0x4621221f, 
+    0xf0104650, 0x2800fd33, 0x221fd0f1, 0x46584621, 0xfd2cf010, 0xd0ea2800, 0x221f4852, 0x30104621, 
+    0xfd24f010, 0xd0e22800, 0x221f484e, 0x30184621, 0xfd1cf010, 0xd0da2800, 0xfdb9f7ff, 0x22104849, 
+    0x03112301, 0xf0103068, 0x2400fd03, 0xb15ce00c, 0xd00e2c01, 0xf04f2c02, 0xf04f0301, 0xf04f0202, 
+    0xd00b0104, 0xe00a4638, 0x46402301, 0x21042202, 0x2301e005, 0x22024628, 0xe0002104, 0xf0104630, 
+    0x1c64fcfe, 0x2c04b264, 0x2200dbe1, 0x46104611, 0xfbbef7ff, 0x8ff8e8bd, 0x4604b510, 0x48314603, 
+    0x21012200, 0xf0103070, 0x482efcd3, 0x21012200, 0x30744623, 0xfcccf010, 0x2200482a, 0x46232101, 
+    0xf0103078, 0x4827fcc5, 0x21012200, 0x307c4623, 0xfcbef010, 0x22004823, 0x46232101, 0xf0103080, 
+    0x4820fcb7, 0x21012200, 0x30844623, 0xfcb0f010, 0x2200481c, 0x46232101, 0xf0103088, 0x4819fca9, 
+    0x21012200, 0xe8bd4623, 0x308c4010, 0xbca0f010, 0x4604b510, 0x48134603, 0x21102204, 0xf0103070, 
+    0x4810fc97, 0x21102204, 0x30744623, 0xfc90f010, 0x2204480c, 0x46232110, 0xf0103078, 0x4809fc89, 
+    0x21102204, 0x307c4623, 0xfc82f010, 0x22044805, 0x46232110, 0xf0103080, 0x2204fc7b, 0x21104801, 
+    0xe00f4623, 0xd1800804, 0x000306f8, 0xd003ca88, 0xd003d288, 0xd003da88, 0xd003c25c, 0xd003c424, 
+    0xd003517a, 0xf0103084, 0x48fbfc63, 0x21102204, 0xf0104623, 0x48f8fc5d, 0x21102204, 0xe8bd4623, 
+    0x1d004010, 0xbc54f010, 0x4605b570, 0x48f24603, 0x7400f240, 0x46212208, 0xf0103818, 0x48eefc49, 
+    0x462b2208, 0x38144621, 0xfc42f010, 0x220848ea, 0x4621462b, 0xf0103810, 0x48e7fc3b, 0x462b2208, 
+    0x380c4621, 0xfc34f010, 0x220848e3, 0x4621462b, 0xf0103808, 0x48e0fc2d, 0x462b2208, 0x1f004621, 
+    0xfc26f010, 0x220848dc, 0x4621462b, 0xfc20f010, 0x462b48d9, 0xe8bd4621, 0x22084070, 0xf0101d00, 
+    0xb510bc17, 0x46034604, 0x220048d3, 0x38642101, 0xfc0ef010, 0x220048d0, 0x46232101, 0xf010385c, 
+    0x48cdfc07, 0x21012200, 0x38544623, 0xfc00f010, 0x220048c9, 0x46232101, 0xf010384c, 0x48c6fbf9, 
+    0x21012200, 0x38444623, 0xfbf2f010, 0x220048c2, 0x46232101, 0xf010383c, 0x48bffbeb, 0x21012200, 
+    0x38344623, 0xfbe4f010, 0x220048bb, 0x46232101, 0x4010e8bd, 0xf010382c, 0xb510bbdb, 0x46034604, 
+    0x220148b5, 0x38642102, 0xfbd2f010, 0x220148b2, 0x46232102, 0xf010385c, 0x48affbcb, 0x21022201, 
+    0x38544623, 0xfbc4f010, 0x220148ab, 0x46232102, 0xf010384c, 0x48a8fbbd, 0x21022201, 0x38444623, 
+    0xfbb6f010, 0x220148a4, 0x46232102, 0xf010383c, 0x48a1fbaf, 0x21022201, 0x38344623, 0xfba8f010, 
+    0x2201489d, 0x46232102, 0x4010e8bd, 0xf010382c, 0xb570bb9f, 0x46034605, 0xf6434897, 0x220474f0, 
+    0x38644621, 0xfb94f010, 0x22044893, 0x4621462b, 0xf010385c, 0x4890fb8d, 0x462b2204, 0x38544621, 
+    0xfb86f010, 0x2204488c, 0x4621462b, 0xf010384c, 0x4889fb7f, 0x462b2204, 0x38444621, 0xfb78f010, 
+    0x22044885, 0x4621462b, 0xf010383c, 0x4882fb71, 0x462b2204, 0x38344621, 0xfb6af010, 0x462b487e, 
+    0xe8bd4621, 0x22044070, 0xf010382c, 0xb570bb61, 0x46034605, 0xf44f4878, 0x221204f8, 0x38644621, 
+    0xfb56f010, 0x22124874, 0x4621462b, 0xf010385c, 0x4871fb4f, 0x462b2212, 0x38544621, 0xfb48f010, 
+    0x2212486d, 0x4621462b, 0xf010384c, 0x486afb41, 0x462b2212, 0x38444621, 0xfb3af010, 0x22124866, 
+    0x4621462b, 0xf010383c, 0x4863fb33, 0x462b2212, 0x38344621, 0xfb2cf010, 0x462b485f, 0xe8bd4621, 
+    0x22124070, 0xf010382c, 0xb570bb23, 0x46034605, 0xf04f4859, 0x221854f8, 0x38644621, 0xfb18f010, 
+    0x22184855, 0x4621462b, 0xf010385c, 0x4852fb11, 0x462b2218, 0x38544621, 0xfb0af010, 0x2218484e, 
+    0x4621462b, 0xf010384c, 0x484bfb03, 0x462b2218, 0x38444621, 0xfafcf010, 0x22184847, 0x4621462b, 
+    0xf010383c, 0x4844faf5, 0x462b2218, 0x38344621, 0xfaeef010, 0x462b4840, 0xe8bd4621, 0x22184070, 
+    0xf010382c, 0xb510bae5, 0x46034604, 0x2200483a, 0x38682101, 0xfadcf010, 0x22004837, 0x46232101, 
+    0xf0103860, 0x4834fad5, 0x21012200, 0x38584623, 0xfacef010, 0x22004830, 0x46232101, 0xf0103850, 
+    0x482dfac7, 0x21012200, 0x38484623, 0xfac0f010, 0x22004829, 0x46232101, 0xf0103840, 0x4826fab9, 
+    0x21012200, 0x38384623, 0xfab2f010, 0x22004822, 0x46232101, 0x4010e8bd, 0xf0103830, 0xb510baa9, 
+    0x46034604, 0x2201481c, 0x38682102, 0xfaa0f010, 0x22014819, 0x46232102, 0xf0103860, 0x4816fa99, 
+    0x21022201, 0x38584623, 0xfa92f010, 0x22014812, 0x46232102, 0xf0103850, 0x480ffa8b, 0x21022201, 
+    0x38484623, 0xfa84f010, 0x2201480b, 0x46232102, 0xf0103840, 0x4808fa7d, 0x21022201, 0x38384623, 
+    0xfa76f010, 0x22014804, 0x46232102, 0x4010e8bd, 0xf0103830, 0x0000ba6d, 0xd180088c, 0x4cfeb570, 
+    0x46052204, 0x48fd4603, 0xf0104621, 0x48fbfa61, 0x462b2204, 0x30084621, 0xfa5af010, 0x220448f7, 
+    0x4621462b, 0xf0103010, 0x48f4fa53, 0x462b2204, 0x30184621, 0xfa4cf010, 0x220448f0, 0x4621462b, 
+    0xf0103020, 0x48edfa45, 0x462b2204, 0x30284621, 0xfa3ef010, 0x220448e9, 0x4621462b, 0xf0103030, 
+    0x48e6fa37, 0x4621462b, 0x4070e8bd, 0x30382204, 0xba2ef010, 0xf44fb570, 0x460504f8, 0x46032212, 
+    0x462148de, 0xfa24f010, 0x221248dc, 0x4621462b, 0xf0103008, 0x48d9fa1d, 0x462b2212, 0x30104621, 
+    0xfa16f010, 0x221248d5, 0x4621462b, 0xf0103018, 0x48d2fa0f, 0x462b2212, 0x30204621, 0xfa08f010, 
+    0x221248ce, 0x4621462b, 0xf0103028, 0x48cbfa01, 0x462b2212, 0x30304621, 0xf9faf010, 0x462b48c7, 
+    0xe8bd4621, 0x22124070, 0xf0103038, 0xb570b9f1, 0x54f8f04f, 0x22184605, 0x48c04603, 0xf0104621, 
+    0x48bef9e7, 0x462b2218, 0x30084621, 0xf9e0f010, 0x221848ba, 0x4621462b, 0xf0103010, 0x48b7f9d9, 
+    0x462b2218, 0x30184621, 0xf9d2f010, 0x221848b3, 0x4621462b, 0xf0103020, 0x48b0f9cb, 0x462b2218, 
+    0x30284621, 0xf9c4f010, 0x221848ac, 0x4621462b, 0xf0103030, 0x48a9f9bd, 0x4621462b, 0x4070e8bd, 
+    0x30382218, 0xb9b4f010, 0x4ff7e92d, 0x48a44604, 0x7800460d, 0xd1012804, 0x90022000, 0x46209a02, 
+    0xf886f7ff, 0xf7ff2014, 0x201fffb2, 0xff72f7ff, 0x0000f640, 0xff32f7ff, 0xf7ff2001, 0xb2e0fef0, 
+    0xfeb1f7ff, 0xf7ff2012, 0x201ffe70, 0xfe2ff7ff, 0x1000f240, 0xfdedf7ff, 0xf7ff2001, 0xb2e0fdae, 
+    0xfd6ff7ff, 0x7800488f, 0xf7ffb240, 0x2001fd2d, 0xfcdef7ff, 0xf7ffb2e8, 0xf8dffc9f, 0x2400b220, 
+    0x5af8f04f, 0x0b80f10b, 0x0504f10b, 0xf44f1d2e, 0xf1061970, 0xe02b0804, 0x2c01b354, 0x2c02d02e, 
+    0x0309f04f, 0x0218f04f, 0xd0444651, 0x46404647, 0xf95ef010, 0x4649230f, 0x46382212, 0xf958f010, 
+    0x46382305, 0x21302204, 0xf952f010, 0x46382301, 0x461a2102, 0xf94cf010, 0x22009b02, 0x46382101, 
+    0xf946f010, 0xb2e41c64, 0xd3d52c04, 0x8ffee8bd, 0x46512309, 0x465f2218, 0xe7d94658, 0x46512309, 
+    0x46282218, 0xf934f010, 0x4649230f, 0x46282212, 0xf92ef010, 0x46282305, 0x21302204, 0xf928f010, 
+    0x46282301, 0x461a2102, 0xf922f010, 0x9b022200, 0x46282101, 0x4630e7d4, 0xf91af010, 0x4649230f, 
+    0x46302212, 0xf914f010, 0x46302305, 0x21302204, 0xf90ef010, 0x46302301, 0x461a2102, 0xf908f010, 
+    0x9b022200, 0x46302101, 0x494ee7ba, 0x47707008, 0x4ff0e92d, 0x484cb0bb, 0xf8dfac2b, 0xf8dfb134, 
+    0x9038a134, 0x90364849, 0x9035484b, 0xc80e484b, 0x000ee884, 0xac28c80e, 0x000ee884, 0xac2ec80e, 
+    0x000ee884, 0xab31c807, 0x0007e883, 0x22304943, 0x3130a805, 0xeaf2f00f, 0x78014841, 0xd0062901, 
+    0x90372001, 0x20029034, 0x903a2500, 0x2108e0ea, 0x21049137, 0x21009134, 0xe7f47001, 0x2000a924, 
+    0xf8214680, 0x983a0015, 0xfa4f9039, 0xe9ddf188, 0x22000335, 0xe9cd460e, 0xe9cda003, 0x98383b01, 
+    0x4300f240, 0x98399000, 0xf95af003, 0xb1242400, 0xd0052c01, 0xd17c2c02, 0x9f36e005, 0xe004465b, 
+    0x4653465f, 0x9b35e001, 0x20004657, 0x1e422110, 0x0c44f10d, 0x0e68f10d, 0x1010f82c, 0x2010f82e, 
+    0x28101c40, 0xa82bddf4, 0xf8502100, 0xf9379024, 0xf9330011, 0x45812011, 0xf10dda17, 0xf85c0ca0, 
+    0x4584c024, 0xf10ddd11, 0xf93e0e44, 0x4594c010, 0x4694db00, 0xc010f82e, 0x0e68f10d, 0xc010f93e, 
+    0xdd004594, 0xf82e4662, 0x1c492010, 0x6f80f5b1, 0xf109dbdd, 0xe0720701, 0x0001fff0, 0xd1800824, 
+    0x00030222, 0x000302d6, 0x000341dc, 0x000331dc, 0x000339dc, 0x000369dc, 0x000371dc, 0x0002b754, 
+    0x00030224, 0xa92ea811, 0x0017f930, 0x1024f851, 0xdc274288, 0x1104ebc4, 0x4408a805, 0x44384631, 
+    0x4691b262, 0x0c01f910, 0x46039000, 0xf7ffa823, 0xf8bdf8dd, 0x9834108c, 0xb2004408, 0x008cf8ad, 
+    0xdb00287f, 0xf8ad207f, 0x9b00008c, 0x4631464a, 0xe039e000, 0xf8bdf7ff, 0xf830a824, 0x1c491015, 
+    0x1015f820, 0xa931a81a, 0x0017f930, 0x1024f851, 0xdb234288, 0x1104ebc4, 0x4408a805, 0xb2624631, 
+    0x57c04691, 0x46039000, 0xf7ffa823, 0xf8bdf8af, 0x9834108c, 0xb2001a08, 0x008cf8ad, 0xdc002800, 
+    0xf8ad2000, 0x9b00008c, 0x4631464a, 0xf891f7ff, 0xf830a824, 0x1c491015, 0x1015f820, 0xa8281c7f, 
+    0x0024f850, 0xdc9d42b8, 0xb2e41c64, 0xf4ff2c03, 0xf108af3e, 0xf0000001, 0xf1b808ff, 0xf4ff0f04, 
+    0x1c6daf24, 0x42859837, 0xaf18f6ff, 0xf88ff7ff, 0xe8bdb03b, 0xb5708ff0, 0x220c4c64, 0x4603460d, 
+    0x46200291, 0xffd4f00f, 0x462b2208, 0x01514620, 0xffcef00f, 0x20402100, 0xf85af7ef, 0xf6402200, 
+    0x1d2071ff, 0xffd2f00f, 0x000af3c0, 0x6f80f5b0, 0xf5a0db01, 0xbd706000, 0x5ff0e92d, 0xf2400006, 
+    0xd03c2b00, 0x0000f44f, 0x11f4f240, 0xfea9f7e7, 0xf7f42003, 0x2101fb81, 0x46082200, 0xfdf4f7ff, 
+    0xf2402500, 0xf8df6800, 0x2701a128, 0x21002400, 0xf7ff4620, 0x2101ffc0, 0x46204681, 0xffbbf7ff, 
+    0x7140f509, 0xd8034541, 0x7040f500, 0xd9084540, 0xb2e04629, 0xfb87f7f4, 0x46502140, 0xff85f00f, 
+    0x1c642700, 0x2c04b264, 0xb947dbe1, 0xf44f2100, 0xf7ef3080, 0x353ff80d, 0x455db22d, 0xf8dfdbd3, 
+    0x2500a0d4, 0x39fff240, 0x2400e049, 0x0801f04f, 0x46202100, 0xff8ff7ff, 0x46072101, 0xf7ff4620, 
+    0x4557ff8a, 0x464fd100, 0xd1004550, 0x44384648, 0x1040b200, 0xf100b14e, 0xf5b10180, 0xd9207f80, 
+    0xf04f10c7, 0xd1090800, 0x2880e01b, 0x2701dd01, 0xf110e004, 0xda140f80, 0x37fff04f, 0xf7f4b2e0, 
+    0x4438fb3d, 0x2900b201, 0x2100da00, 0xdb014559, 0x11fff240, 0xf7f4b2e0, 0x4815fb36, 0xf00f2140, 
+    0x1c64ff34, 0x2c04b264, 0xf1b8dbc2, 0xd10c0f00, 0xf44f2100, 0xf7ee3080, 0x1c6dffbb, 0xb10eb22d, 
+    0xe0002008, 0x42a82001, 0x2e00dcaf, 0x2200d00b, 0x46112001, 0xfd68f7ff, 0x5ff0e8bd, 0xf44f4906, 
+    0xf7e70000, 0xe8bdbdfd, 0x00009ff0, 0xd180089c, 0xd003c424, 0xfffffc00, 0xdcba01f5, 0x41f0e92d, 
+    0xea5f4dfd, 0x4efd0800, 0x0700f241, 0x0400f640, 0x2300d025, 0x220c4639, 0xf00f4628, 0x2300ff10, 
+    0x220b4621, 0xf00f4628, 0x2300ff0a, 0x220c4639, 0xf00f4630, 0x2300ff04, 0x220b4621, 0xf00f4630, 
+    0x2203fefe, 0x21084643, 0xf00f4628, 0x4643fef8, 0xe8bd4630, 0x220341f0, 0xf00f2108, 0x2301bef0, 
+    0x220c4639, 0xf00f4628, 0x2301feea, 0x220b4621, 0xf00f4628, 0x2301fee4, 0x220c4639, 0xf00f4630, 
+    0x2301fede, 0xe92de7d8, 0x48dd5ff0, 0x0900f04f, 0xb1108800, 0xd0032801, 0xf643e004, 0xe0016608, 
+    0x6608f647, 0xa35cf8df, 0xf2402500, 0x24003bf0, 0x28c5ea4f, 0x0144eb08, 0x000aeb01, 0x22044659, 
+    0xf00f4607, 0xb200feca, 0xdd05283c, 0x4638b2b1, 0xfe9bf00f, 0x0901f04f, 0xb2241c64, 0xdbe92c80, 
+    0xb22d1c6d, 0xdbe22d04, 0xe8bd4648, 0xb5709ff0, 0x0400f244, 0x220e4605, 0x48c34603, 0xf00f4621, 
+    0x48bdfe9e, 0x462b220e, 0x30084621, 0xfe97f00f, 0x220e48be, 0x4621462b, 0xfe91f00f, 0x462b48b7, 
+    0xe8bd4621, 0x220e4070, 0xf00f3008, 0xb570be88, 0x6400f240, 0x22094605, 0x48b34603, 0xf00f4621, 
+    0x48adfe7e, 0x462b2209, 0x30084621, 0xfe77f00f, 0x220948ae, 0x4621462b, 0xfe71f00f, 0x462b48a7, 
+    0xe8bd4621, 0x22094070, 0xf00f3008, 0xe92dbe68, 0x21004ff8, 0xf7ff9100, 0x2001ffda, 0xffb7f7ff, 
+    0xf7ff2000, 0x2301ffb4, 0x220e4d9f, 0x4628039c, 0xf00f4621, 0x4e98fe54, 0x220e2301, 0x36084621, 
+    0xf00f4630, 0x4f99fe4c, 0x220e2301, 0x46384621, 0xfe45f00f, 0x8244f8df, 0x220e2301, 0xf1084621, 
+    0x46400808, 0xfe3bf00f, 0x46212300, 0x4628220e, 0xfe35f00f, 0x46212300, 0x4630220e, 0xfe2ff00f, 
+    0x46212300, 0x4638220e, 0xfe29f00f, 0x46212300, 0x4640220e, 0xfe23f00f, 0x01602100, 0xfe98f7ee, 
+    0x4e830265, 0x11a44f83, 0x820cf8df, 0xa20cf8df, 0x920cf8df, 0xe0069500, 0x46322103, 0xf7ee4668, 
+    0x2801ff01, 0x2208d01b, 0x46384621, 0xfe15f00f, 0xd1f12800, 0x46212208, 0xf00f4640, 0x2800fe0e, 
+    0x2208d1ea, 0x46504621, 0xfe07f00f, 0xd1e32800, 0x46212208, 0xf00f4648, 0x2800fe00, 0xf240d1dc, 
+    0x462811f4, 0xfccdf7e7, 0x4628496e, 0xfcb8f7e7, 0xf00f4861, 0x4601fdc7, 0xf7e74628, 0x485ffcb1, 
+    0xfdc0f00f, 0x46284601, 0xfcaaf7e7, 0x46284966, 0xfca6f7e7, 0x8ff8e8bd, 0x47f0e92d, 0xb0864863, 
+    0xe88dc80e, 0xc807000e, 0xe883ab03, 0x48540007, 0x28018800, 0xf8dfd13c, 0x27009178, 0x2402469a, 
+    0x28c7ea4f, 0x0144eb08, 0x0509eb01, 0x46282200, 0xf00f210f, 0xb206fdc2, 0x0014f93a, 0xda0842b0, 
+    0x46282301, 0x03d9220f, 0xfda9f00f, 0x46283e0b, 0xf93de00c, 0x42b00014, 0xdd0b4628, 0xf2442300, 
+    0x220e0100, 0xfd9bf00f, 0x4628360b, 0xb2b32200, 0xe003210f, 0xf24c2301, 0x220e0100, 0xfd8ff00f, 
+    0xb2241c64, 0xdbcd2c05, 0xb23f1c7f, 0xdbc62f04, 0xe8bdb006, 0xe92d87f0, 0xf8df5ff0, 0x260090c8, 
+    0xf2484682, 0x482e0b00, 0xb1108800, 0xd01d2801, 0x2400e04d, 0x02f746c8, 0x0144eb07, 0x0508eb01, 
+    0x46282200, 0xf00f210f, 0xf93afd78, 0x42881016, 0xdd014628, 0xe0002301, 0x46592300, 0xf00f220f, 
+    0x1c64fd5e, 0x2c80b224, 0xe030dbe6, 0xea4f2700, 0xeb0828c6, 0xeb010147, 0x22000409, 0x210f4620, 
+    0xfd5bf00f, 0x2d0db205, 0x2301dd08, 0x220f4620, 0xf00f4659, 0x3d0bfd44, 0xe00a4620, 0x46202d02, 
+    0x2300da0b, 0x0100f244, 0xf00f220e, 0x350bfd38, 0x22004620, 0x210fb2ab, 0x2301e003, 0x0100f24c, 
+    0xf00f220e, 0x1c7ffd2c, 0x2f82b23f, 0x1c76dbd1, 0x2e04b236, 0xe678dba7, 0xd003c810, 0xd003d810, 
+    0x000301d0, 0xd003c600, 0xd003c018, 0xd003d018, 0xd003517a, 0xd003c2c0, 0xd003cac0, 0xd003d2c0, 
+    0xd003dac0, 0x00029ec5, 0xdcba01f5, 0x0002b7b8, 0xd003c704, 0x8803b570, 0x35c0f240, 0x46042206, 
+    0x462948f5, 0xfcfbf00f, 0x22068863, 0x462948f3, 0xfcf5f00f, 0x220688a3, 0x462948f1, 0xfceff00f, 
+    0x462988e3, 0x4070e8bd, 0x220648ee, 0xbce7f00f, 0xf240b570, 0x460435c0, 0x220648e7, 0xf00f4629, 
+    0x8020fcec, 0x48e52206, 0xf00f4629, 0x80a0fce6, 0x48e32206, 0xf00f4629, 0x8120fce0, 0x48e12206, 
+    0xf00f4629, 0x81a0fcda, 0x48db2206, 0x1c804629, 0xfcd3f00f, 0x22068060, 0x462948d8, 0xf00f1c80, 
+    0x80e0fccc, 0x48d62206, 0x1c804629, 0xfcc5f00f, 0x22068160, 0x462948d3, 0xf00f1c80, 0x81e0fcbe, 
+    0xe92dbd70, 0xf8df47f0, 0x24009340, 0x833cf8df, 0xf8b94605, 0xb1100000, 0xd01c2801, 0x203fe032, 
+    0x02e72600, 0x0014f825, 0x0146eb07, 0x0008eb01, 0x210f2200, 0xfca1f00f, 0x1014f835, 0xb2361c76, 
+    0x2e804408, 0x0014f825, 0xf935dbee, 0x11c00014, 0x0014f825, 0x2600e016, 0x0060f06f, 0xf82502e7, 
+    0xeb070014, 0xeb010146, 0x22000008, 0xf00f210f, 0xf835fc84, 0x1c761014, 0x4408b236, 0xf8252e82, 
+    0xdbee0014, 0xb2241c64, 0xdbc22c04, 0xb570e6e1, 0x6400f640, 0x22094605, 0x48ad4603, 0xf00f4621, 
+    0x48a5fc5e, 0x462b2209, 0x30fa4621, 0xfc57f00f, 0x220948a2, 0x4621462b, 0xf00f30fa, 0x48a0fc50, 
+    0x4621462b, 0x4070e8bd, 0x30fa2209, 0xbc47f00f, 0x8801b510, 0x48984604, 0xfc27f00f, 0x48978821, 
+    0xfc23f00f, 0x48968821, 0xfc1ff00f, 0x48958821, 0xfc1bf00f, 0x88614890, 0xf00f1c80, 0x488ffc16, 
+    0x1c808861, 0xfc11f00f, 0x8861488d, 0xf00f1c80, 0x488cfc0c, 0xe8bd8861, 0x1c804010, 0xbc05f00f, 
+    0x5ff0e92d, 0xb220f8df, 0xf8df2500, 0xf6478220, 0xf8bb6a08, 0xb1100000, 0xd0122801, 0x2400e02d, 
+    0x0900f248, 0x464702ee, 0x0044eb06, 0x23004649, 0x4438220f, 0xfc03f00f, 0xb2241c64, 0xdbf32c80, 
+    0x2400e01b, 0x02ee4657, 0x0144eb06, 0x0008eb01, 0xf00f4639, 0x1c64fbda, 0x2c82b224, 0x46b9dbf4, 
+    0x24004f6d, 0x46493f0a, 0x0044eb06, 0xf00f4438, 0x1c64fbcc, 0x2c05b224, 0x1c6ddbf5, 0x2d04b22d, 
+    0xe532dbc7, 0x41f0e92d, 0x486a4605, 0xb0884c66, 0x0200f04f, 0x010ff04f, 0xf0107800, 0x48660f01, 
+    0xf7edd006, 0x8020fbf9, 0x2801b280, 0xe008d003, 0xfbd3f00f, 0x2301e7f7, 0x220e4860, 0xf00f0399, 
+    0x2700fbbe, 0x22039700, 0x4639463b, 0xf0024638, 0x2000f86b, 0xfc92f7ff, 0xff92f7ff, 0xb9408820, 
+    0x6008f643, 0x001cf8ad, 0x001ef8ad, 0xf7ffa807, 0xb12dff5f, 0xae018820, 0x2801b130, 0xe07ed033, 
+    0xf7ff2000, 0xe02aff34, 0xf7ff2001, 0x2002ff30, 0xfd2df7ff, 0xf7ffa801, 0x2000fee4, 0x1010f936, 
+    0x0112f1c1, 0x2900b209, 0x1010f826, 0x2100da00, 0xf826290f, 0xdd001010, 0xf826210f, 0x1c401010, 
+    0x2804b200, 0xa801dbea, 0xfe74f7ff, 0xf7ff2002, 0xa801fd0e, 0xfec5f7ff, 0xf7ffa801, 0x2003fdec, 
+    0xfd05f7ff, 0x2001e04b, 0xff01f7ff, 0x25c32400, 0x080cf10d, 0xf7ff2002, 0xf7fffcfa, 0xa801fc84, 
+    0xfeaff7ff, 0xf7ffa803, 0x2000fe73, 0xf9364641, 0xf8312010, 0xf2a23020, 0x425232cf, 0xf2f5fb92, 
+    0xb212441a, 0xf8262a00, 0xda002010, 0x2a0f2200, 0x2010f826, 0x220fdd00, 0x2010f826, 0xb2001c40, 
+    0xdbe42804, 0xf7ffa801, 0x1c64fe35, 0x2c03b224, 0x2002dbd0, 0xfccbf7ff, 0xfc55f7ff, 0xf7ffa801, 
+    0xf7fffdaa, 0x2003fd59, 0xfcc1f7ff, 0xfc4bf7ff, 0xd1042801, 0xf7ff2002, 0xf7fffcba, 0x2300fc44, 
+    0x22039700, 0x20084619, 0xffcef001, 0xf7ff2001, 0xb008fbf5, 0x81f0e8bd, 0xd003c70e, 0xd003cf0e, 
+    0xd003d70e, 0xd003df0e, 0x000301d0, 0xd003c600, 0xd003c008, 0x000301c8, 0xd03d409a, 0xd003c80e, 
+    0x4c33b570, 0x211f2300, 0x4620461a, 0xfaf7f00f, 0xf240482f, 0x220535e0, 0x301a4629, 0xfafdf00f, 
+    0x46032205, 0x46204629, 0xfae9f00f, 0x46202301, 0x0299220a, 0xfae3f00f, 0x23024c25, 0xf24f220c, 
+    0x34200100, 0xf00f4620, 0x2304fada, 0x22004620, 0xf00f210f, 0x2301fad4, 0x210f2200, 0xf00f1f20, 
+    0x2301face, 0x210f2200, 0xe8bd1ea0, 0xf00f4070, 0x4818bac6, 0xf00fb510, 0x4917faa5, 0x80084a17, 
+    0x1140f3c0, 0xf3c07011, 0x4a151180, 0x4a157011, 0xf3c07011, 0x4a1411c0, 0xf3c07011, 0x4a132100, 
+    0xf3c07011, 0x4a1221c0, 0x70110bc0, 0x70084911, 0x4808bd10, 0x31b3f64b, 0x3084b510, 0xfa85f00f, 
+    0xffd7f7ff, 0x2000490c, 0xe8bd7008, 0xe7974010, 0xd03c8204, 0xd03c8034, 0x00030344, 0x000302a4, 
+    0x0003028d, 0x0003028c, 0x00030341, 0x00030303, 0x00030342, 0x00030343, 0x00030374, 0x4db8b570, 
+    0x2200b283, 0x21014604, 0xf00f4628, 0xb2a3fa78, 0x22014628, 0xf00f2102, 0xb2a3fa72, 0x22024628, 
+    0xf00f2104, 0x2301fa6c, 0x22034628, 0xf00f2108, 0xb2a3fa66, 0xe8bd4628, 0x22044070, 0xf00f2110, 
+    0xe92dba5e, 0x48a741f0, 0xf00f2100, 0x48a5fa3e, 0x1c802100, 0xfa39f00f, 0x210048a2, 0xf00f1d00, 
+    0x48a0fa34, 0x1d802100, 0xfa2ff00f, 0x2100489d, 0xf00f3008, 0x489bfa2a, 0x300a2100, 0xfa25f00f, 
+    0x21004898, 0xf00f300c, 0x4896fa20, 0x300e2100, 0xfa1bf00f, 0x21004893, 0xf00f3010, 0x4891fa16, 
+    0x30122140, 0xfa11f00f, 0x2100488e, 0xf00f3014, 0x488cfa0c, 0x30162104, 0xfa07f00f, 0x21004889, 
+    0xf00f3018, 0x4887fa02, 0x301a2100, 0xf9fdf00f, 0x21004884, 0xf00f301c, 0x2307f9f8, 0x22004882, 
+    0xf00f4619, 0x4881fa0c, 0x1cad4d7d, 0x487d7801, 0x1c843020, 0x29001e86, 0x0100f04f, 0x4607d019, 
+    0xf9e3f00f, 0x46382301, 0x21202205, 0xf9f7f00f, 0x46202100, 0xf9d9f00f, 0x46282100, 0xf9d5f00f, 
+    0x4100f240, 0xf00f4630, 0xe8bdf9d0, 0x200141f0, 0xf00fe764, 0x2100f9ca, 0xf00f4620, 0x2100f9c6, 
+    0xf00f4628, 0xf242f9c2, 0xe7eb4192, 0x460cb510, 0x78094966, 0xd1152900, 0x4862b283, 0x21032200, 
+    0xf00f301e, 0x485ff9cc, 0x2200b2a3, 0x1d00210f, 0xf9c5f00f, 0x485a2301, 0xe8bd2205, 0x21204010, 
+    0xb9bdf00f, 0x4859bd10, 0x28007800, 0x4855d106, 0x21032300, 0x301e461a, 0xb9b1f00f, 0xb5104770, 
+    0x4952460c, 0x29007809, 0xb283d115, 0x2203484d, 0x301e2118, 0xf9a3f00f, 0xb2a3484a, 0x210f2200, 
+    0xf00f300a, 0x2301f99c, 0x22064845, 0x4010e8bd, 0xf00f2140, 0xbd10b994, 0x78004844, 0xd1062800, 
+    0x23004840, 0x21182203, 0xf00f301e, 0x4770b988, 0x460cb510, 0x7809493d, 0xd1152900, 0x4839b283, 
+    0x21c02206, 0xf00f301e, 0x4836f97a, 0x2200b2a3, 0x3010210f, 0xf973f00f, 0x48312301, 0xe8bd2207, 
+    0x21804010, 0xb96bf00f, 0x4830bd10, 0x28007800, 0x482cd106, 0x22062300, 0x301e21c0, 0xb95ff00f, 
+    0x48284770, 0x22062301, 0x30202140, 0xb957f00f, 0x23004824, 0x21402206, 0xf00f3020, 0xb510b950, 
+    0x4922460c, 0x29007809, 0xb283d115, 0x220c481d, 0x0291301e, 0xf943f00f, 0xb2a3481a, 0x210f2200, 
+    0xf00f301c, 0x2301f93c, 0x22094815, 0x4010e8bd, 0xf00f0259, 0xbd10b934, 0x78004814, 0xd1062800, 
+    0x4810220c, 0x02912300, 0xf00f301e, 0x4770b928, 0xf000b510, 0x2100f81d, 0xf7ff2001, 0x2100ff47, 
+    0xf7ff2001, 0x2100ff6c, 0xf7ff2001, 0x2100ff91, 0xf7ff2001, 0x2100ffb6, 0x4010e8bd, 0xe7be2001, 
+    0xd00351d8, 0xd0035058, 0xd03d1042, 0x00030342, 0xf7ffb510, 0x2301fea6, 0x220048fb, 0xf00f4619, 
+    0x48faf8fe, 0x22042301, 0xf00f2110, 0x4cf6f8f8, 0x22022301, 0x21041ca4, 0xf00f4620, 0x2301f8f0, 
+    0x22034620, 0xf00f2108, 0x4cf0f8ea, 0x22022301, 0x21041da4, 0xf00f4620, 0x2301f8e2, 0x21024620, 
+    0xf00f461a, 0x2301f8dc, 0x21402206, 0xf00f1da0, 0x48e6f8d6, 0x22072301, 0x30122180, 0xf8cff00f, 
+    0x23014ce1, 0x34082202, 0x46202104, 0xf8c7f00f, 0x46202301, 0xe8bd2203, 0x21084010, 0xb8bff00f, 
+    0x230148d9, 0x46192200, 0xb5101f00, 0xf8b7f00f, 0xe8bd2100, 0x20024010, 0xbed8f7ff, 0x230048d2, 
+    0x461a2101, 0xb5101f00, 0xf8a9f00f, 0x4010e8bd, 0xbee9f7ff, 0x5ff0e92d, 0xf0014dcd, 0x2300080f, 
+    0x22024614, 0x0901f04f, 0x46282104, 0xf897f00f, 0x46282301, 0x21402206, 0xf891f00f, 0x46282301, 
+    0x21802207, 0xf88bf00f, 0x46282300, 0x21102204, 0xf885f00f, 0x46282300, 0x21202205, 0xf87ff00f, 
+    0x46282300, 0x21022201, 0xf879f00f, 0x46282300, 0x21082203, 0xf873f00f, 0xf1a84fb6, 0x4eb5080a, 
+    0xb2d0f8df, 0xf8df3f18, 0x3e08a2d0, 0x0f05f1b8, 0xe8dfd276, 0xf903f008, 0x00f5f6f7, 0x82bcf8df, 
+    0xd0111c60, 0x46282300, 0x21402206, 0xf857f00f, 0x1e60b3ec, 0xd8542809, 0xea4f48a6, 0x38100148, 
+    0xf82df00f, 0xe0562130, 0x464448a2, 0x38104641, 0xf825f00f, 0x46584621, 0xf821f00f, 0x46282300, 
+    0x21402206, 0xf83bf00f, 0x46282300, 0x21802207, 0xf835f00f, 0x46282301, 0x461a2102, 0xf82ff00f, 
+    0x21184893, 0xf00f1c80, 0x4891f810, 0x30082118, 0xf80bf00f, 0x22012300, 0x46282102, 0xf81ff00f, 
+    0x21022301, 0x4628461a, 0xf819f00f, 0xe7ffe1ae, 0x46382301, 0x461a2102, 0xfffaf00e, 0x46302301, 
+    0x461a2102, 0xfff4f00e, 0x46382300, 0x21022201, 0xffeef00e, 0x46302300, 0x21022201, 0xffe8f00e, 
+    0xf1a4e183, 0x2859000b, 0x487ad80b, 0x3810497c, 0xffd5f00e, 0x4876212c, 0xf00e1c80, 0xe185ffd6, 
+    0xf1a4e181, 0xf5b00065, 0xd2067fc8, 0x49754871, 0xf00e3810, 0x2128ffc4, 0xf2a4e7ed, 0xf5b010f5, 
+    0xd2067ffa, 0x4970486b, 0xf00e3810, 0x2124ffb8, 0xf2a4e7e1, 0xf5b030e9, 0xd2066f7a, 0x496b4865, 
+    0xf00e3810, 0x2120ffac, 0xf5a4e7d5, 0xf2415098, 0x38893187, 0xd8064288, 0x4965485e, 0xf00e3810, 
+    0x211cff9e, 0xf5a4e7c7, 0xf649501c, 0x3811413f, 0xd8064288, 0x46414857, 0xf00e3810, 0x2118ff90, 
+    0xf5a4e7b9, 0xf24c4043, 0x3851314f, 0xd8064288, 0x49584850, 0xf00e3810, 0x2114ff82, 0x4956e7ab, 
+    0x30c3f5a4, 0x428838a1, 0x484ad806, 0x38104953, 0xff75f00e, 0xe79e2110, 0x49524851, 0x42884420, 
+    0x4844d806, 0x38104950, 0xff69f00e, 0xe792210c, 0x494f484e, 0x42884420, 0x483ed806, 0x38104651, 
+    0xff5df00e, 0xe7862108, 0x494b484a, 0x42884420, 0x4838d885, 0x38104949, 0xff51f00e, 0xe77a2104, 
+    0xe041e050, 0xe7ffe01e, 0x46544832, 0x38104651, 0xff45f00e, 0x46584621, 0xff41f00e, 0x2108482c, 
+    0xf00e1c80, 0x482aff42, 0x30082108, 0xff3df00e, 0x46282300, 0x21402206, 0xff51f00e, 0x22072300, 
+    0xe72a2180, 0x46382301, 0x461a2102, 0xff30f00e, 0x46302301, 0x461a2102, 0xff2af00e, 0x46382300, 
+    0x21022201, 0xff24f00e, 0x46302300, 0x21022201, 0xff1ef00e, 0x46282300, 0x21802207, 0xff2ff00e, 
+    0x22052301, 0xe0b32120, 0x46282300, 0x21802207, 0xff25f00e, 0x46584922, 0xff01f00e, 0x2102480c, 
+    0xe72a3008, 0xf990481f, 0x28030000, 0x2805d03c, 0x2804d03a, 0x2802d038, 0x2801d06d, 0x0301f04f, 
+    0x2206d076, 0xe6ee2140, 0xd00351de, 0xd003505e, 0xd03c80d8, 0xc8000178, 0x0501bd00, 0x0f053700, 
+    0x1b898f80, 0x1908b100, 0x1687d280, 0x1406f400, 0x11861580, 0x0c845880, 0x00061a7f, 0x0a037a00, 
+    0xfff85edf, 0x0007a11f, 0x07829b80, 0xfff0bdbf, 0x003d08ff, 0xffb3b4bf, 0x004c4b3f, 0x0280de80, 
+    0x01406f40, 0x000301dc, 0x46382301, 0x461a2102, 0xfebef00e, 0x46302301, 0x461a2102, 0xfeb8f00e, 
+    0x48f749f6, 0xfeabf00e, 0x46282300, 0x21402206, 0xfec5f00e, 0x210548f3, 0xfea7f00e, 0x210a48f1, 
+    0xf00e1c80, 0x48effea2, 0x1d002105, 0xfe9df00e, 0x46282301, 0x21042202, 0xfeb1f00e, 0x46382300, 
+    0x21022201, 0xfe94f00e, 0x46302300, 0x21022201, 0xfe8ef00e, 0x49e1e03a, 0xf00e48e1, 0x2300fe80, 
+    0x22064628, 0xf00e2140, 0x2105fe9a, 0xe7ffe6a3, 0x46382201, 0xf00e2102, 0x2301fe7b, 0x21024630, 
+    0xf00e461a, 0x2300fe75, 0x22014638, 0xf00e2102, 0x2300fe6f, 0x22014630, 0xf00e2102, 0x2300fe69, 
+    0x22064628, 0xf00e2140, 0x2301fe7a, 0x21102204, 0xf00e4628, 0x4628fe74, 0x5ff0e8bd, 0x22032301, 
+    0xf00e2108, 0xf1b9be6c, 0xd00d0f00, 0x46302300, 0x21082203, 0xfe4cf00e, 0xe8bd4630, 0x23015ff0, 
+    0x21082203, 0xbe44f00e, 0x9ff0e8bd, 0x230148be, 0x21102204, 0xf00eb510, 0x2100fe52, 0xf7ff2001, 
+    0x48bafc9e, 0x28027800, 0x48b6d10d, 0xf00e380a, 0x280efe29, 0x48b6d107, 0x210e2200, 0x0000f990, 
+    0x4010e8bd, 0xbd10e596, 0x4db2b570, 0x4cae2803, 0x2805d004, 0x2804d017, 0xe030d017, 0x46282300, 
+    0x210c2202, 0xfe2bf00e, 0x46202301, 0x21802207, 0xfe25f00e, 0x46202300, 0x21102204, 0xfe1ff00e, 
+    0xfc8af7ff, 0x2302e017, 0x2301e000, 0x22024628, 0xf00e210c, 0x2300fe14, 0x22074620, 0xf00e2180, 
+    0x2300fe0e, 0x22044620, 0xf00e2110, 0x2100fe08, 0xf7ff2002, 0x2100fc54, 0xf7ff2002, 0x2100fcb0, 
+    0xf7ff2002, 0x4891fc9e, 0x28027800, 0x488dd10b, 0xf00e380a, 0xb241fdd7, 0x2200488d, 0x0000f990, 
+    0x4070e8bd, 0xbd70e546, 0xf7ffb510, 0xf7fffc2c, 0xf7fffc53, 0xf7fffc7a, 0xf7fffc8b, 0x4c85fcad, 
+    0x21012300, 0x4620461a, 0xfdd9f00e, 0x46202300, 0x210c2202, 0xfdd3f00e, 0x23004c7b, 0x21802207, 
+    0xf00e4620, 0x2300fdcc, 0x22044620, 0xf00e2110, 0x4876fdc6, 0x28027800, 0x4c72d10f, 0x22062301, 
+    0x21401ea4, 0xf00e4620, 0x2301fdba, 0x22074620, 0x4010e8bd, 0xf00e2180, 0xbd10bdb2, 0xb510496b, 
+    0x1000f991, 0x2901b189, 0x2902d014, 0x4865d143, 0xf00e380a, 0x280efd87, 0x4865d13d, 0x210e2200, 
+    0x0000f990, 0x4010e8bd, 0xe8bde4f4, 0x20004010, 0xbb14f7ff, 0xb3004c5c, 0xd0202801, 0xd12a2802, 
+    0x46202301, 0x21102204, 0xfd89f00e, 0x46202301, 0x21082203, 0xfd83f00e, 0x220e4857, 0x0100f244, 
+    0xfd8bf00e, 0x28014c53, 0x2300d013, 0x21012200, 0xe8bd4620, 0xf00e4010, 0x2300bd72, 0x2301e000, 
+    0x22044620, 0xf00e2110, 0x2300fd6a, 0x21082203, 0x2301e7ee, 0xbd10e7ea, 0x4c44b570, 0x0000f994, 
+    0x2801b110, 0xe010d004, 0xf7ff2001, 0xe00cfad7, 0x23004d3d, 0x21102204, 0xf00e4628, 0x2300fd50, 
+    0x22034628, 0xf00e2108, 0xf7fffd4a, 0x2300fbf1, 0x21014838, 0xf00e461a, 0x7820fd42, 0xd10f2802, 
+    0x23014c30, 0x1ea42206, 0x46202140, 0xfd37f00e, 0xe8bd4620, 0x23014070, 0x21802207, 0xbd2ff00e, 
+    0x2100bd70, 0xb5102002, 0xfbcbf7ff, 0x78004827, 0xd10b2802, 0x380a4823, 0xfd04f00e, 0x4824b241, 
+    0xf9902200, 0xe8bd0000, 0xe4734010, 0xb510bd10, 0xfbbef7ff, 0x7800481d, 0xd10f2802, 0x23014c19, 
+    0x1ea42206, 0x46202140, 0xfd09f00e, 0x46202301, 0xe8bd2207, 0x21804010, 0xbd01f00e, 0x2100bd10, 
+    0xf7ff2001, 0x2200bb75, 0x4614b510, 0x1e43b128, 0xd20a2b09, 0x700c2000, 0x20ffbd10, 0xbd10700c, 
+    0xf0f3fbb0, 0xb2d21c52, 0x230ae000, 0xd8f7280a, 0xd3132805, 0x70082001, 0x0000e011, 0x1e0a6e00, 
+    0xc8000168, 0xd03c80da, 0xd0035078, 0x00030342, 0x00030222, 0xd00351da, 0xd28fffd4, 0x4610700c, 
+    0x0fc2bd10, 0x7fd1ebb2, 0xf1c1d203, 0x440831ff, 0x1a404770, 0x48194770, 0xf990b510, 0x28030000, 
+    0x2805d012, 0x2804d010, 0x2101d00e, 0xf7ec4608, 0x0780fcf1, 0x2101d406, 0xf7ec2011, 0xb2c0fceb, 
+    0xd0002800, 0xbd102001, 0x22054c0d, 0x46202120, 0xfcb3f00e, 0xd0f52800, 0x46202204, 0xf00e2110, 
+    0x2801fcac, 0x4807d0ee, 0xfc7cf00e, 0xd1e92800, 0x1c804804, 0xfc76f00e, 0x0000e7e2, 0x000301dc, 
+    0xd003502c, 0xd03c80e6, 0x4604b570, 0xea4048f9, 0x48f90144, 0xfc63f00e, 0x210048f7, 0xf00e3084, 
+    0x48f6fc5e, 0xea404df4, 0x357c3184, 0xf00e4628, 0x48f3fc56, 0x20107801, 0xfceaf7ed, 0xea4048f1, 
+    0x46283184, 0xfc4bf00e, 0xbd702001, 0x210048ea, 0xf00eb510, 0xe8bdfc44, 0xf0014010, 0xb510bc5e, 
+    0x4604b086, 0xfaa6f001, 0xd0222800, 0x308048e2, 0xfc32f00e, 0x010bf3c0, 0xda022953, 0x31adf601, 
+    0x3953e000, 0x0c810508, 0x1d0048db, 0xfc27f00e, 0x4ad92101, 0x90002000, 0x4623323c, 0x0102e9cd, 
+    0x91059104, 0x5130f240, 0x20019001, 0xfd3cf7ec, 0xb0062001, 0xe92dbd10, 0x000741f0, 0xf8df48d2, 
+    0x6805834c, 0xf998d103, 0xf7ff0000, 0xf505ff9d, 0xf5057626, 0x463074a6, 0xffc1f7ff, 0xffb6f7ff, 
+    0x46202200, 0x68334629, 0xc0081c52, 0xb2126873, 0x2a533610, 0xdbf6c108, 0xd1032f01, 0x0000f998, 
+    0xff82f7ff, 0x22012100, 0xf8344608, 0xb10b3b02, 0xb2894311, 0x00521c40, 0xb212b200, 0xdbf42810, 
+    0xf8df2200, 0xf8dfe2ec, 0x3520c2ec, 0x20004690, 0x8002f80c, 0x030ff001, 0x1603f3c1, 0x0383eb0e, 
+    0x0686eb0e, 0x30c0f8d3, 0x6080f8d6, 0xf3c14433, 0xeb0e2603, 0x6c360686, 0x0b0e4433, 0x6026f85e, 
+    0xf9354433, 0xeb036b02, 0x429e03c3, 0x2301da01, 0x2300e000, 0x6002f81c, 0x7b02f814, 0x4087405f, 
+    0x433e0849, 0xb2001c40, 0x31c3ea41, 0x2808b289, 0x6002f80c, 0x4ba0dbce, 0x1c52549e, 0x2a10b212, 
+    0xe8bddbc5, 0xb5f081f0, 0xb0854e98, 0x46072500, 0x462c2101, 0xf6439500, 0xf996737a, 0x462a0000, 
+    0xfb26f001, 0x21802001, 0xe9cd2305, 0x90004001, 0xe9cd4618, 0xf9961403, 0x21072000, 0xfad9f001, 
+    0xf9e8f001, 0xf001b118, 0x0005fa03, 0xb17fd110, 0x6480f04f, 0x11f4f240, 0xf7e64620, 0xf246fa72, 
+    0x46206166, 0xfa5cf7e6, 0x46204984, 0xfa58f7e6, 0xfb83f001, 0x24004e7f, 0xf0014620, 0xf846f9f0, 
+    0x1c640024, 0x2c04b264, 0xb005dbf6, 0xbdf04628, 0x4ff3e92d, 0xb08b4874, 0xf6404689, 0x24100200, 
+    0x90076800, 0x5180f500, 0x49759109, 0x04498809, 0x719af1a1, 0x91061409, 0x91082100, 0x460e1e4d, 
+    0x9f0b4688, 0x1504e9cd, 0xf5074968, 0xf9916700, 0x99063000, 0x39161a79, 0xea4f2702, 0xeb017ce1, 
+    0xf36f4c9c, 0xeba10c0d, 0xf04f010c, 0xb2090c05, 0x1702e9cd, 0x2c00e9cd, 0x46612207, 0xfb44f001, 
+    0x22004860, 0x46934613, 0x0000f990, 0x900a9202, 0x4f584610, 0x54392100, 0xb2001c40, 0xdbf82810, 
+    0xeb094261, 0x30200004, 0xe12b9003, 0x44089806, 0x98091907, 0x7017f830, 0x30fff04f, 0x0047eb00, 
+    0xfa0f9f07, 0x980afa80, 0x44204408, 0xc010f837, 0x0040eb07, 0x0c02f830, 0x0000ebac, 0xfa0f00c0, 
+    0x2001f980, 0xea4f4f42, 0xeb070c80, 0xfa231780, 0xfa22fe0c, 0xf00efc0c, 0xf00c0e0f, 0x1c400c0f, 
+    0xe02ef837, 0xf837b200, 0x2803702c, 0x0c07ebae, 0x0709eb0c, 0xf987fa0f, 0xf8dfdbe4, 0xf003e0d4, 
+    0xf002070f, 0xf8cd0c0f, 0xf83e9000, 0xf83e7027, 0xf00b002c, 0x1a3f0c0f, 0x0009eb07, 0xf980fa0f, 
+    0xf0009802, 0xf83e070f, 0xf83e002c, 0x1a3f7027, 0x45469800, 0xb2004438, 0xd9049000, 0x0008eba6, 
+    0x0e00f04f, 0x2000e002, 0x0e06eba8, 0x88374e26, 0xf60afb17, 0x9701b237, 0x0707eba9, 0x0609fb19, 
+    0x0807fb07, 0x0700e9dd, 0x1bc04691, 0xfb009f00, 0xfb17e000, 0x9f02ec07, 0x4566469e, 0xea4fd204, 
+    0xea4f034e, 0xe0030249, 0x4666007b, 0x024bea4f, 0xd22d4540, 0x0f01f1ba, 0x46504680, 0x2000d000, 
+    0x3ffff1ba, 0x0047ea40, 0xd01f9002, 0xea402000, 0xe02b004b, 0x20080038, 0xd1800404, 0x000c04e5, 
+    0x00030223, 0x000c14e5, 0x000301b8, 0x00030330, 0x0003102c, 0x0003112c, 0x0003314c, 0xdcba01f5, 
+    0x00030320, 0x00030328, 0x0003032a, 0xe7de2001, 0x0f01f1ba, 0xd0004650, 0xf1ba2000, 0xea403fff, 
+    0x9002004e, 0x2000d00a, 0x0049ea40, 0x46834546, 0xfa23d20e, 0x07c0f004, 0xe001d105, 0xe7f32001, 
+    0xf004fa22, 0x2001e00a, 0xf04fe00a, 0xe00730ff, 0x40e09802, 0xd1f607c0, 0xf004fa2b, 0xd1f407c0, 
+    0xda002800, 0x9f0b4240, 0x1b3f440f, 0x7ce7ea4f, 0x6c1ceb07, 0x0cfff02c, 0x0e0ceba7, 0xc020f8dd, 
+    0xd10145e6, 0x2000b178, 0xdb3842a1, 0xc010f8dd, 0x0c5cea4f, 0x2001b100, 0x70c0ea4c, 0x98059004, 
+    0xd0021c40, 0x2001e01b, 0x9804e7ee, 0x4c27f5a0, 0x0cbbf1bc, 0xf643d113, 0x443870e1, 0x17c527bb, 
+    0x4595eb00, 0x050df36f, 0xb2001b40, 0x48e99005, 0x7007251f, 0x704727a7, 0x70872700, 0x1c6870c7, 
+    0x2d80d00d, 0x48e4da09, 0x28074028, 0x9804d105, 0x48e00e07, 0x00e5eb00, 0x1c6d7007, 0x9803b22d, 
+    0xb2091c49, 0xdd024288, 0xf6ff2d80, 0x9805aecf, 0xe8bdb00d, 0xe92d8ff0, 0x200043f8, 0x4dd84fd7, 
+    0x90002200, 0x6680f507, 0xf04f48d6, 0x463b34ff, 0x1000f990, 0xf7eb2001, 0x8838febc, 0x20018030, 
+    0x0240eb07, 0x1010f837, 0x2c02f832, 0xb2091a89, 0xf8261c62, 0xd0051010, 0x460a2900, 0x4252da00, 
+    0xdd054542, 0x46042900, 0x4249da00, 0xf881fa0f, 0xb2001c40, 0xdbe32880, 0xda002c03, 0xea4f2403, 
+    0xeb0601e8, 0xf9320244, 0x28000c06, 0x4240da00, 0xdd014288, 0xe0101ee4, 0x0c04f932, 0xda002800, 
+    0x42884240, 0x1ea4dd01, 0xf932e007, 0x28000c02, 0x4240da00, 0xdd004288, 0x20001e64, 0x18c1b263, 
+    0x1011f836, 0x1010f825, 0xb2001c40, 0xdbf62811, 0x22004ead, 0x00c2eb05, 0x1008f9b0, 0x4006f9b0, 
+    0x7002f9b0, 0xf9b04421, 0x443c4004, 0xeb014421, 0xeb0604c1, 0x600c1182, 0x4008f9b0, 0x7006f9b0, 
+    0xf9b0443c, 0x443c7004, 0x7002f9b0, 0xeb041be4, 0x604c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 
+    0x1be47004, 0x7002f9b0, 0xeb04443c, 0x608c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1be47004, 
+    0x7002f9b0, 0xeb041be4, 0x60cc04c4, 0x4008f9b0, 0x7006f9b0, 0xc002f9b0, 0xf9b01be4, 0x44677004, 
+    0xeb04443c, 0x610c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x443c7004, 0x7002f9b0, 0xeb041be4, 
+    0x614c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb04443c, 0x618c04c4, 
+    0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb041be4, 0x61cc04c4, 0x4006f9b0, 
+    0xf9b01c52, 0xb2127008, 0xc002f9b0, 0xf9b01be4, 0x44677004, 0xeb04443c, 0x620c04c4, 0x4006f9b0, 
+    0x7008f9b0, 0xf9b01be4, 0x443c7004, 0x7002f9b0, 0xeb041be4, 0x624c04c4, 0x4006f9b0, 0x7008f9b0, 
+    0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb04443c, 0x628c04c4, 0x4006f9b0, 0x7008f9b0, 0xf9b01be4, 
+    0x1be47004, 0x7002f9b0, 0xeb041be4, 0x62cc04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1b3c7004, 
+    0x7002f9b0, 0xeb04443c, 0x630c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1b3c7004, 0x7002f9b0, 
+    0xeb041be4, 0x634c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x443c7004, 0x7002f9b0, 0xeb041b3c, 
+    0x638c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0xf9b07004, 0x44380002, 0x42404420, 0xeb002a04, 
+    0x63c800c0, 0xaf16f6ff, 0x49388828, 0x00c0eb00, 0x80080040, 0x70034836, 0x83f8e8bd, 0xf7ffb510, 
+    0x2002feaa, 0xf8ccf7ed, 0xf2404604, 0xf6431100, 0xf7ff7060, 0x2002fd1d, 0xf8c2f7ed, 0x1a20492d, 
+    0x1000f9b1, 0xf0f1fbb0, 0x6008492b, 0xe92dbd10, 0xf24041f0, 0xf7ff2500, 0x2400fe8e, 0x36fff04f, 
+    0x6700f643, 0x0800f248, 0x4629e02e, 0xf7ff4638, 0x1c41fcff, 0xf5a0d01e, 0xb200507e, 0x6480f04f, 
+    0xeb000fc1, 0xf2403081, 0xb20611f4, 0xf7e54620, 0x491aff48, 0xf7e54620, 0x4919ff33, 0xf7e54620, 
+    0x4631ff2f, 0xf7e54620, 0x4916ff2b, 0xf7e54620, 0xe00dff27, 0x1c641979, 0xb22417c8, 0x4090eb01, 
+    0x000df36f, 0xb2071a08, 0xf0f5fb98, 0xdccc42a0, 0xe4864630, 0x0003112c, 0x80000007, 0x00038d5c, 
+    0x0003975c, 0x00030330, 0x0003102c, 0x0003032a, 0x00030328, 0x000303a4, 0x0003032c, 0xa5a55a5a, 
+    0xdde50000, 0xdcba01f5, 0x5c0849f8, 0x49f84770, 0x47f0e92d, 0x26007809, 0x250eb3f1, 0xb2834cf5, 
+    0x0700f248, 0x4639220f, 0xf00e4620, 0x2380f818, 0x31fff240, 0x46202200, 0xf811f00e, 0x22002306, 
+    0x1ca021ff, 0xf80bf00e, 0xf6412200, 0x217f73f8, 0xf00e1d20, 0xf1a4f804, 0x46390802, 0x46404644, 
+    0xffe3f00d, 0x0180f248, 0xf00d4620, 0xf8dfffde, 0x2400a384, 0x9380f8df, 0x0a0ef10a, 0x0204f04f, 
+    0x01f0f04f, 0x0000f899, 0x46502803, 0xf00dd009, 0x43c0fff4, 0xe0000700, 0xd01de001, 0x2507e006, 
+    0xf00de7bc, 0xea35ffea, 0xd0130000, 0x42bc1c64, 0x2301dbe4, 0x220a4644, 0x029d4640, 0xf00d4629, 
+    0x2300ffce, 0x220a4629, 0xf00d4620, 0x4630ffc8, 0x87f0e8bd, 0xe7ec2601, 0x46502200, 0xf00d210f, 
+    0x49c6ffcc, 0x0201f000, 0xf3c0700a, 0x704a0240, 0x0280f3c0, 0xf3c0708a, 0x70c800c0, 0x48bde7ea, 
+    0xe92d2200, 0x303041f0, 0x71fff643, 0xffb5f00d, 0x4ebbb205, 0xd00e07e8, 0x46302301, 0x025c2209, 
+    0xf00d4621, 0x2300ff9c, 0x22094621, 0xf00d4630, 0x1e6dff96, 0xf240b22d, 0x24001700, 0x23014639, 
+    0x22084630, 0xff8bf00d, 0x46392300, 0x46302208, 0xff85f00d, 0x2c181c64, 0x49aadbf0, 0x005af105, 
+    0x004cf3c0, 0xf7ee7809, 0x4628f98a, 0x81f0e8bd, 0x43f0e92d, 0xb1434689, 0x4ca3b11a, 0x0584f1a4, 
+    0x4ca2e00d, 0x0584f1a4, 0xb122e009, 0x3ca84c9e, 0x0584f1a4, 0x4c9ce003, 0xf1a434a8, 0xf8900584, 
+    0x6807e004, 0x2201b902, 0x0c00f04f, 0x2300e01f, 0x46184619, 0xf600fa27, 0xd00707f6, 0x0820f1c0, 
+    0x6008f814, 0xf8554073, 0x40716028, 0xb2001c40, 0xdbef2820, 0x70ceea5f, 0x7820d003, 0x68284043, 
+    0x469e4041, 0x0c01f10c, 0xfa0f460f, 0x4594fc8c, 0xe9c9dbdd, 0xe8bd7e00, 0xe92d83f0, 0x468247fc, 
+    0xf8df4883, 0x25019210, 0x81f4f8df, 0x464a460f, 0x02a97001, 0xf00d4640, 0x4606ffed, 0xf990487e, 
+    0x28030000, 0x2802d017, 0x2801d022, 0x4871d02d, 0xf00d3012, 0x9001fef7, 0x3014486e, 0xfef2f00d, 
+    0x486c9000, 0xf00d3016, 0x9900feed, 0xea402400, 0x90004001, 0x4867e02c, 0xf00d3024, 0x9001fee3, 
+    0x30264864, 0xfedef00d, 0x48629000, 0xe7ea3028, 0x301e4860, 0xfed6f00d, 0x485e9001, 0xf00d3020, 
+    0x9000fed1, 0x3022485b, 0x485ae7dd, 0xf00d3018, 0x9001fec9, 0x301a4857, 0xfec4f00d, 0x48559000, 
+    0xe7d0301c, 0x22004669, 0xf7ff4608, 0x1c64ff61, 0x42bc4653, 0x4669dbf6, 0x4608462a, 0xff58f7ff, 
+    0xb2819800, 0x300a484b, 0xfeaff00d, 0x0c019800, 0x30084848, 0xfea9f00d, 0xb2819801, 0x1d804845, 
+    0xfea3f00d, 0x0700f246, 0x23004644, 0x220d4639, 0xf00d4640, 0x4849feb4, 0x3120f240, 0x0000f990, 
+    0xd01e2804, 0xd01f2805, 0x107af44f, 0x2210464b, 0xfb954345, 0x4621f0f1, 0x30201a30, 0xff7af00d, 
+    0x46392300, 0x4620220d, 0xfe99f00d, 0x22014835, 0x483b7803, 0x1000f9b0, 0xf7ee2000, 0xe8bdf95a, 
+    0xf44f87fc, 0xe7e1007a, 0x00faf44f, 0x4a32e7de, 0xb570b283, 0x21ff4d27, 0x0400f248, 0x220f7011, 
+    0x46284621, 0xfe7bf00d, 0xf2402380, 0x220031ff, 0xf00d4628, 0x2306fe74, 0x21ff2200, 0xf00d1ca8, 
+    0x2200fe6e, 0x73f8f641, 0x1d28217f, 0xfe67f00d, 0x1eac4621, 0x46202301, 0xf00d220f, 0x2300fe60, 
+    0x22064620, 0xf00d2140, 0x2300fe5a, 0x22054620, 0xf00d2120, 0x2300fe54, 0x22044620, 0xf00d2110, 
+    0x2300fe4e, 0x210f4620, 0xf00d461a, 0x2300fe48, 0x22074620, 0xf00d2180, 0x4620fe42, 0x4070e8bd, 
+    0x22072301, 0xf00d2180, 0x0000be3a, 0x00030330, 0x00030338, 0xd0035094, 0x00030214, 0x00030334, 
+    0xd0035092, 0x00030223, 0x00030828, 0x00030978, 0x0003020f, 0xc800010c, 0x0003020e, 0x00030222, 
+    0x00030320, 0x47f0e92d, 0x46814efe, 0x28037830, 0x250fd00f, 0x83f0f8df, 0xf2482400, 0x22040700, 
+    0x21f04640, 0xfe19f00d, 0xb2407831, 0xd0072903, 0x48f6e007, 0xb1087800, 0xe7eb250e, 0xe7e92507, 
+    0xb9104028, 0x42bc1c64, 0x2204dbe9, 0x21f04640, 0xfe03f00d, 0x48eeb204, 0xd5010721, 0xe00c2103, 
+    0xd5010761, 0xe0082102, 0xd50107a1, 0xe0042101, 0xd00107e1, 0xe0002100, 0x700121ff, 0x1c41b248, 
+    0x49e4d004, 0x46485c09, 0xfea7f7ff, 0xe60fb260, 0x4604b510, 0xff4bf7ff, 0xe8bd4620, 0xe7b14010, 
+    0x4cddb510, 0x48db2100, 0x2000f994, 0xf9945481, 0x21012001, 0xf9945481, 0x21022002, 0xf9945481, 
+    0x21032003, 0xf9905481, 0xf9903003, 0xf9902002, 0xf9901001, 0xf7ee0000, 0xf994fd2b, 0xf9943003, 
+    0xf9942002, 0xf9941001, 0xe8bd0000, 0xf7f34010, 0xb57fb921, 0xa9022000, 0x90019000, 0x90039002, 
+    0xf7ef4668, 0x48c5fc5d, 0x7800466b, 0xd1102803, 0xf99048be, 0xf9901000, 0xf8332002, 0xf8231011, 
+    0xf9901012, 0xf9901001, 0xf8330003, 0xf8231011, 0x21001010, 0xf8334608, 0x1c402010, 0x4411b200, 
+    0x2804b209, 0x1c89dbf7, 0xf9bd1088, 0x38401000, 0x0401f020, 0xf9332001, 0x428a2010, 0x4611dd00, 
+    0xb2001c40, 0xdbf62804, 0x1c494aad, 0x0101f021, 0x42438810, 0x0143eb01, 0x711ff501, 0x1b61b20d, 
+    0x0061eba0, 0x48a7b201, 0x22018011, 0x46287803, 0xf81ff7ee, 0x4628b004, 0xe92dbd70, 0xb0894ff0, 
+    0x200049a1, 0x8284f8df, 0xf10d4d9a, 0x90010b08, 0x90004604, 0x9002466e, 0x90069003, 0x1000f991, 
+    0x9260f8df, 0x90079105, 0x4668a902, 0xfbf8f7ef, 0xf8904892, 0xf1bee000, 0xd1100f03, 0xf990488b, 
+    0xf9901000, 0xf8362002, 0xf8261011, 0xf9901012, 0xf9901001, 0xf8360003, 0xf8261011, 0xf8981010, 
+    0x2000c000, 0x4682af04, 0x0f01f1bc, 0xf807562a, 0xf93ba002, 0xd0083010, 0x428b2140, 0xf936dd0a, 
+    0x29801010, 0x2101da04, 0xf240e003, 0xe7f41100, 0x54b92102, 0xb2c01c40, 0xd3e52804, 0x78004871, 
+    0xd1022803, 0xf88d2001, 0xf1be0013, 0xd1070f03, 0x0010f89d, 0x0012f88d, 0x0011f89d, 0x0013f88d, 
+    0x0170f242, 0xf7e506c8, 0xf44ffbd8, 0xf2400a00, 0x465011f4, 0xfbc5f7e5, 0x4650496d, 0xfbb0f7e5, 
+    0xf9974f65, 0xf9971003, 0xf9970000, 0xeb002001, 0xf9973001, 0x02091002, 0x1102eb01, 0x46504401, 
+    0xfb9ef7e5, 0xf00d4863, 0x4601fcad, 0xf7e54650, 0x4861fb97, 0xfca0f00d, 0x46504601, 0xfb90f7e5, 
+    0x1013f89d, 0x0010f89d, 0x2011f89d, 0x3001eb00, 0x1012f89d, 0xeb010209, 0x44011102, 0xf7e54650, 
+    0xf89dfb7f, 0xf89d0010, 0xb1581011, 0xf89d2900, 0xd0011012, 0xe022b301, 0xf89d2900, 0xd0151013, 
+    0xe01cb139, 0xf89db151, 0xb9d11012, 0x0013f89d, 0x7838b168, 0x70397879, 0xe0227078, 0x0012f89d, 
+    0xf89d2800, 0xd01b0013, 0xe01ab908, 0x7838b939, 0x70397879, 0xe02a7078, 0x1013f89d, 0x2802b189, 
+    0xf89dd014, 0x29021011, 0xf89dd010, 0x2a022012, 0xf89dd00c, 0x2b023013, 0x2801d008, 0xe010d117, 
+    0x78b8b1a8, 0x70b978f9, 0xe01070f8, 0x2201482c, 0x3000f899, 0x1000f9b0, 0x000ff06f, 0xff29f7ed, 
+    0x2901e005, 0x2a01d103, 0x2b01d101, 0x492bd013, 0xf7e54650, 0xf7fffb25, 0xf898fe83, 0x28010000, 
+    0xf990481b, 0x5c290000, 0x4825d003, 0x28017800, 0x2001d007, 0x4921e006, 0x0000f44f, 0xfb10f7e5, 
+    0x2000e010, 0xfd09f7ff, 0x1000f899, 0x2080f44f, 0xfcaef7ec, 0xb2241c64, 0xf6ff2c03, 0x9807aef5, 
+    0xd07d2800, 0xfe85f7ff, 0xf7ed2000, 0x4f14f905, 0x28017838, 0xf7edd02e, 0xf242fcb4, 0x46290570, 
+    0x0000e020, 0x00030214, 0xd00350a2, 0x00030338, 0x0003020e, 0x0003033c, 0x00030330, 0x00030394, 
+    0x00030320, 0x00030223, 0x00030227, 0x00030284, 0x77777776, 0xd0030446, 0xd180000c, 0xdcba01f5, 
+    0x0003031c, 0x4800f04f, 0xf7e54640, 0x7838fae6, 0xe015b118, 0xfc39f7ed, 0x2100e7cf, 0xf7ee2001, 
+    0x4c4dffe0, 0x200c2100, 0x2000f994, 0xfd2cf7ee, 0xf9942101, 0x46082000, 0xfd6cf7ee, 0xfa40f7f3, 
+    0x462946aa, 0xf7e54640, 0xf7fffac8, 0xb204fb50, 0xd07c1c60, 0x90062001, 0xf7ed2000, 0x07e0f8ad, 
+    0x483ed00a, 0xf8992201, 0xf9b03000, 0x46101000, 0xfe8ff7ed, 0xb2241c64, 0x1000f899, 0x464c1060, 
+    0xfdcdf7ed, 0x22014d35, 0x20007823, 0x1000f9b5, 0xfe7ff7ed, 0x4668a902, 0xfa72f7ef, 0xe0004830, 
+    0x7800e055, 0xd1102803, 0xf990482e, 0xf9902000, 0xf8363002, 0xf8262012, 0xf9902013, 0xf9902001, 
+    0xf8360003, 0xf8262012, 0xf9bd2010, 0x20011000, 0x2010f936, 0xda00428a, 0x1c404611, 0x2804b2c0, 
+    0x3908d3f6, 0x8829b208, 0xeba12201, 0x38550060, 0x2100b200, 0xfdbff7ed, 0xf7ee2074, 0x7821feab, 
+    0x0000f640, 0xfbf4f7ec, 0x28017838, 0x4812d016, 0x0000f990, 0x1cc09005, 0xeb0017c1, 0xf0217191, 
+    0x1a400103, 0xf7f3b240, 0xf7edfb78, 0x4651fbfa, 0xf7e54640, 0x7838fa52, 0xe005b118, 0xfb72f7ed, 
+    0x9805e7f5, 0xfb69f7f3, 0xf7ed2001, 0x9806f835, 0xe8bdb009, 0x00008ff0, 0x00030227, 0x00030320, 
+    0x00030394, 0x00030338, 0x5ff0e92d, 0xa214f8df, 0xf8dd2a05, 0xf89a9028, 0xf0066000, 0xd0040601, 
+    0xd0022a04, 0xd00e2a03, 0x2b01e012, 0x2b02d009, 0x4a7dd007, 0x78124b7d, 0x4313781b, 0x2a03d001, 
+    0x1c80d106, 0x4a7ae003, 0xb90a7812, 0xb2401c40, 0xb1112701, 0x0040eb07, 0x0040e000, 0x280cb240, 
+    0x2400da03, 0x050cf1c0, 0xf1a0e014, 0x290c010c, 0x2401d203, 0x0518f1c0, 0xf1a0e00c, 0x290c0118, 
+    0x2402d203, 0x0524f1c0, 0x2824e004, 0x2403db02, 0x0530f1c0, 0xb19cf8df, 0x46d82101, 0xf00d4658, 
+    0x4864fae4, 0xf00d3016, 0x07c0fadd, 0x2100d010, 0xf00d4640, 0x2e00fada, 0xf7e5d0ee, 0xf000f8ed, 
+    0xfa07010f, 0x495cf001, 0xf7ec7809, 0xe7e3fb61, 0xf04f4858, 0xf8df0200, 0xf04f815c, 0x30140101, 
+    0xf1a82e00, 0xd0720804, 0xfae7f00d, 0x0100ea27, 0xf00d4640, 0x4e51faba, 0x22072300, 0x46302180, 
+    0xfacdf00d, 0x1800f240, 0x23004630, 0x22084641, 0xfac5f00d, 0xf04fb2a3, 0xf1b90200, 0xf04f0f01, 
+    0xd0580103, 0xf00d4846, 0x4845faba, 0x2200b2a3, 0x1c802103, 0xfab3f00d, 0xb2a34841, 0x21032200, 
+    0xf00d1d00, 0x483efaac, 0x2200b2a3, 0x1d802103, 0xfaa5f00d, 0xb2ab483a, 0x210f2200, 0xf00d302e, 
+    0x4f38fa9e, 0x2202b2a3, 0x4638210c, 0xfa97f00d, 0x4638b2a3, 0x21032200, 0xfa91f00d, 0xb2a31cbf, 
+    0x22024638, 0xf00d210c, 0xb2a3fa8a, 0x22004638, 0xf00d2103, 0xb2abfa84, 0x210f2200, 0xf00d1cb8, 
+    0xf99afa7e, 0xb3a80000, 0xd0342802, 0x46412301, 0x46302208, 0xfa73f00d, 0x46582100, 0xfa55f00d, 
+    0x0f01f1b9, 0xe8bdd12b, 0xf7ed5ff0, 0xf00dbc71, 0x4601fa74, 0x481ae78c, 0xf00d3008, 0x4818fa60, 
+    0x2200b2a3, 0x300a2103, 0xfa59f00d, 0xb2a34814, 0x21032200, 0xf00d300c, 0x4811fa52, 0x2200b2a3, 
+    0x300e2103, 0xfa4bf00d, 0x2200480d, 0xb2ab210f, 0xe7c43030, 0x2301e7ff, 0x21802207, 0xe8bde7c9, 
+    0x00009ff0, 0x000301c8, 0x00030394, 0x00030312, 0x00030214, 0xd003400e, 0x00030223, 0xd003e834, 
+    0xd0034200, 0xd003900e, 0x47f0e92d, 0x48334606, 0x468a4f33, 0x90c8f8df, 0x80c8f8df, 0x78003f16, 
+    0xf0002501, 0x46380401, 0xf00d2101, 0x4648f9fe, 0xf9f8f00d, 0xd01007c0, 0x46382100, 0xf9f5f00d, 
+    0xd0f02c00, 0xf808f7e5, 0x010ff000, 0xf001fa05, 0x1000f898, 0xfa7cf7ec, 0x4821e7e5, 0x0200f04f, 
+    0x807cf8df, 0x0101f04f, 0x907cf8df, 0xf1a81e80, 0xb33c081a, 0xfa01f00d, 0x0100ea25, 0xf00d4640, 
+    0x08b3f9d4, 0x21072200, 0x0002f109, 0xf9e7f00d, 0xf24c220e, 0xf0060100, 0x46480303, 0xf9dff00d, 
+    0x46382100, 0xf9c1f00d, 0x22044810, 0x46532170, 0xf9d5f00d, 0x480e4653, 0x47f0e8bd, 0x21702204, 
+    0xb9cdf00d, 0xf9d9f00d, 0x46404601, 0xf9adf00d, 0x46332209, 0x6100f643, 0x0000e7df, 0x000301c8, 
+    0xd0034024, 0x00030223, 0xd003e832, 0xd003c012, 0xd003d012, 0x4cfeb510, 0xf7ece002, 0xb160f9e7, 
+    0xf00d4620, 0x0300f989, 0x0002f04f, 0xf7ecd4f5, 0x49f8f9d7, 0x20016008, 0x4cf7bd10, 0xf00d4620, 
+    0xf040f981, 0x46200110, 0xf97ff00d, 0xbd102000, 0xb51048ef, 0xf00d1d00, 0x0fc0f96f, 0x49ecbd10, 
+    0x0003f1c0, 0xeb01310c, 0xf00d0080, 0xe92db965, 0xf8df41f0, 0x108d839c, 0x4604b086, 0x0840f1a8, 
+    0x2b01b133, 0x2b02d014, 0x2b03d06e, 0xe0a8d06f, 0x90052000, 0x90042201, 0x46239000, 0xe9cd9001, 
+    0x00880202, 0xb2014642, 0xf7eb2001, 0xe098fa6d, 0xf04f2a07, 0xd0540600, 0x0745eb05, 0x4640e019, 
+    0xf93af00d, 0x0026f844, 0xf00d4640, 0x1971f935, 0x0021f844, 0xf00d4640, 0xeb06f92f, 0xf8440145, 
+    0x46400021, 0xf928f00d, 0x1c7619b9, 0xf844b236, 0x42ae0021, 0xe074dbe3, 0x46404647, 0xf91cf00d, 
+    0x0202f000, 0x0101f000, 0x31c2ea41, 0x1026f844, 0x0108f000, 0x0280f3c0, 0x3141ea42, 0xf8441972, 
+    0xf0001022, 0xf3c00120, 0xea421200, 0xeb0621c1, 0xf8440245, 0xf0001022, 0xf3c00180, 0xea401080, 
+    0xeb052041, 0x44310145, 0x0021f844, 0xf00d4638, 0x4638f8f3, 0xf8f0f00d, 0xf00d4638, 0x1c76f8ed, 
+    0x42aeb236, 0xe03cdbc8, 0x46472600, 0xe015e013, 0xf00d4638, 0x1971f8e1, 0x0021f844, 0xf00d4638, 
+    0xf844f8db, 0x46380026, 0xf8d6f00d, 0xf00d4638, 0x1c76f8d3, 0x42aeb236, 0xe022dbea, 0x463e2700, 
+    0x4640e01d, 0xf8c8f00d, 0x0027f844, 0x46401c7f, 0xf00db23f, 0xf844f8c1, 0x1c7f0027, 0xb23f4640, 
+    0xf8baf00d, 0x0027f844, 0x46401c7f, 0xf00db23f, 0xf844f8b3, 0x1c7f0027, 0xb23f1c76, 0x42aeb236, 
+    0xb006dbdf, 0x2100488a, 0xe8bd387c, 0xf00d41f0, 0xe92db8a6, 0x27005ff0, 0x2b0b4698, 0xe9dd4692, 
+    0xf8dd6b0d, 0x460c902c, 0xd1044605, 0x46494880, 0xf00d301c, 0x1c60f894, 0x2c07d007, 0x2d05d106, 
+    0x2d06d001, 0x2701d102, 0x2400e000, 0xdd022e00, 0x1e401070, 0x4876b206, 0x30084631, 0xf87ff00d, 
+    0xea4f980c, 0xea41718b, 0xea417109, 0x980a5100, 0x40c0ea41, 0x4187ea40, 0x318aea41, 0x2088ea41, 
+    0x1144ea40, 0x4329486a, 0x5ff0e8bd, 0xb867f00d, 0x460db570, 0x9c041059, 0xea410409, 0xea411142, 
+    0xea4101c5, 0xf0400040, 0x48610110, 0xf00d387c, 0x2c00f856, 0x485ed006, 0xe8bd4621, 0x38784070, 
+    0xb84df00d, 0xb570bd70, 0x48594606, 0x460d4614, 0xf6402200, 0x1d0071ff, 0xf858f00d, 0xb925b12e, 
+    0x0064ebb0, 0xf500d501, 0xf6436040, 0xe8bd71ff, 0x00834070, 0x2200484e, 0xf00d3878, 0xb5f0b839, 
+    0x56614c4e, 0x29013c10, 0x2910d011, 0x2501da0f, 0x408d1e49, 0xf04f6065, 0x408d35ff, 0x6021b2a9, 
+    0x040989a1, 0x892160e1, 0x60a10409, 0x2100e001, 0x68676061, 0x2f00b132, 0x6826d01c, 0xe9d42100, 
+    0xe0264502, 0xd0152f00, 0x21006826, 0x4502e9d4, 0xf850e00d, 0x423a2021, 0x4332d002, 0x2021f840, 
+    0xd002422a, 0xf8404322, 0x1c492021, 0xebb1b209, 0xdbee0f43, 0xf850bdf0, 0x423a2021, 0x4332d002, 
+    0x2021f840, 0xd002422a, 0xf8404322, 0x1d092021, 0xebb1b209, 0xdbee0f43, 0x4825bdf0, 0x22032301, 
+    0x30482108, 0xbfe4f00c, 0x4fffe92d, 0xf04fb081, 0x46980900, 0x460d4614, 0x0a01f04f, 0x464f9e0e, 
+    0xb00fe9dd, 0x7f80f5b6, 0x9000f8cd, 0x4430dc01, 0xf1bbb200, 0xd0050f05, 0x1c612000, 0x2c07d00e, 
+    0xe00cd006, 0xf04f1040, 0xf04f0901, 0xe7f40a00, 0xd0012d05, 0xd1022d06, 0xe0072701, 0x490f2400, 
+    0x5d49310b, 0xd1012901, 0x0800f04f, 0xea410401, 0xea411149, 0xf0400048, 0x48050118, 0xf00c387c, 
+    0x4803ff9e, 0x30089900, 0xff99f00c, 0xe00704b9, 0xd1800480, 0x00030210, 0xd003517e, 0x000309ac, 
+    0x3088ea41, 0x1144ea40, 0x4329488e, 0x488e4301, 0xff85f00c, 0x7801488d, 0x4000f240, 0xf818f7ec, 
+    0x700aea4f, 0x4187ea40, 0x3188ea41, 0x208bea41, 0x1044ea40, 0xf4404328, 0x48832100, 0xff6ff00c, 
+    0xfdd8f7ff, 0xd0182800, 0xf00c4881, 0xb204ff6b, 0x46329900, 0xf7ff4648, 0x0070ff16, 0xb2019b11, 
+    0x462a9801, 0xfdf3f7ff, 0xff77f7ff, 0x46339801, 0x4629463a, 0xff23f7ff, 0xb0054620, 0x8ff0e8bd, 
+    0x4fffe92d, 0x4607b083, 0x20004c72, 0x461d221d, 0x8613e9dd, 0xa911e9dd, 0xb040f8dd, 0x4160f04f, 
+    0x20059002, 0x9001463b, 0xf00c4620, 0x486aff41, 0x0100f24c, 0x0000f990, 0xd0042803, 0xd0042805, 
+    0xd0042804, 0x2300e008, 0x2301e002, 0x2302e000, 0x220e4620, 0xff2cf00c, 0x9b04220c, 0x02914620, 
+    0xff26f00c, 0x22189b02, 0x51f8f04f, 0xf00c4620, 0x9b01ff1f, 0xf44f2210, 0x4620017f, 0xff18f00c, 
+    0xd0052f07, 0x9b052208, 0x01514620, 0xff10f00c, 0x23014c50, 0x21202205, 0xf00c4620, 0x2301ff09, 
+    0x22044620, 0xf00c2110, 0x4847ff03, 0x3048211f, 0xfef5f00c, 0x1d004844, 0xfeeef00c, 0x21004842, 
+    0xf00c3880, 0x4c40feec, 0x3c782100, 0xf00c4620, 0xf5c5fee6, 0x46205140, 0xfee1f00c, 0xf240483a, 
+    0xf00c11ad, 0x1f24fedc, 0x46202118, 0xfed7f00c, 0x46202119, 0xfed3f00c, 0x0000f44f, 0xe0079000, 
+    0x21064a33, 0x325e4668, 0xffdcf7eb, 0xd0042801, 0xf00c4620, 0x07c0fec1, 0x482bd1f2, 0xf00c3878, 
+    0xebc5febb, 0xe0010180, 0x5140f501, 0xdbfb2900, 0x0400f243, 0xdb0242a1, 0x5140f5a1, 0x4822e7fa, 
+    0xf00c3878, 0x4820feac, 0x3048211f, 0xfea7f00c, 0x1d00481d, 0xfea0f00c, 0x2300481e, 0xf04f221d, 
+    0xf00c4160, 0x481bfea5, 0x220c2300, 0xf00c4621, 0x2f07fe9f, 0x2208d005, 0x23004816, 0xf00c0151, 
+    0x4f11fe97, 0x3f402400, 0x4638e017, 0xfe84f00c, 0x5201f3c0, 0x2014f82b, 0x3203f3c0, 0x2014f82a, 
+    0x2203f3c0, 0x2014f829, 0x1203f3c0, 0x000ff000, 0x2014f828, 0x0014f826, 0x42ac1c64, 0xb007d3e5, 
+    0x0000e71c, 0x00080400, 0xd1800480, 0x00030223, 0xd0035120, 0xd1800800, 0x00030222, 0x4ff0e92d, 
+    0x2000b089, 0x48fe9007, 0x20099005, 0x48fd9004, 0x49fd6804, 0x49fd9106, 0xf8df9408, 0x7809b3f4, 
+    0xd10a2904, 0x1000f89b, 0xd1062903, 0x784949f9, 0xd0022901, 0x1c8949f4, 0xf8df9106, 0x22b183dc, 
+    0x21014ff7, 0xf5044ef5, 0xf5045a80, 0xf8c859c0, 0x46352000, 0x0000f997, 0xfc97f7f2, 0x0000f997, 
+    0xfb72f7f2, 0xf8c821b2, 0x20001000, 0xfb16f7f2, 0xf7f22002, 0xf997fd72, 0xf7f20000, 0x2100fb16, 
+    0x0000f244, 0xfb67f7f2, 0x0000f997, 0xfac4f7f2, 0xf44f2100, 0xf7eb2000, 0x21b3feab, 0x23c048e1, 
+    0x1000f8c8, 0xf2402200, 0xf00c11ff, 0xf997fe28, 0xf7f20000, 0x48d6fba1, 0x0800f04f, 0x78004fda, 
+    0xd03a2803, 0x21012300, 0xe9cd461a, 0x46087800, 0xfa38f7ea, 0x48cb2101, 0xf2402305, 0x028a2b00, 
+    0xb000f8cd, 0xe9cd9103, 0x1e8a3201, 0x460b6800, 0xf7ff2105, 0x48c6fe09, 0x0100f04f, 0x28037800, 
+    0xd0234608, 0x46dc4abf, 0xf9336813, 0x2a002011, 0x4252da00, 0xb2091c49, 0x44104561, 0x1240dbf5, 
+    0x28102100, 0x1c49dd04, 0xb2491040, 0xdbf82906, 0x780048be, 0xd01b2803, 0x48b6e01b, 0xe9cd2300, 
+    0x461a7800, 0x1001f990, 0xe7c12001, 0x46dc4ab1, 0xf9929b08, 0xeb032001, 0xf9332382, 0x2a002011, 
+    0x4252da00, 0xb2091c49, 0x44104561, 0xe7d6dbf5, 0x20002105, 0x2010f937, 0xf825410a, 0x1c402010, 
+    0x2880b200, 0x4fa4dbf6, 0x230020b4, 0x4619461a, 0x20016038, 0x5800e9cd, 0xf9d4f7ea, 0x603820b5, 
+    0x21012300, 0xe9cd461a, 0x46085800, 0xf9caf7ea, 0x603820b6, 0x21022300, 0x2001461a, 0x5800e9cd, 
+    0xf9c0f7ea, 0x603820b7, 0x21032300, 0x2001461a, 0x5800e9cd, 0xf9b6f7ea, 0x464120b8, 0x20006038, 
+    0x1020f846, 0xb2001c40, 0x7f00f5b0, 0x2500dbf8, 0xf7eb2002, 0x4f8cfdb5, 0x3f204623, 0x20b961f8, 
+    0x3105eb00, 0x60014884, 0x0000f640, 0x21019000, 0x9a06487d, 0xf00d3846, 0x2002fc7b, 0xfda0f7eb, 
+    0xf64069f9, 0xf8df0200, 0x1a08b208, 0x210061f8, 0x0814f10b, 0x1025f84b, 0xf8281e49, 0x21001015, 
+    0xf8544608, 0x1c403020, 0x4290b200, 0xdbf84419, 0x200012c9, 0x3020f854, 0xf8441a5b, 0x1c403020, 
+    0x4290b200, 0x4869dbf6, 0x0000f990, 0xd0082804, 0xd0082805, 0x22042700, 0x40ba2000, 0x6300f5c2, 
+    0x2702e012, 0x2701e7f7, 0xeb00e7f5, 0xf8540e01, 0x1c49c020, 0xf854b209, 0x44f4e02e, 0xc020f844, 
+    0xdcf2428a, 0xb2001c40, 0x0100f04f, 0xdcf74283, 0xf1c72000, 0xe0090e06, 0xc021f854, 0xb2094411, 
+    0xfc0efa0c, 0xc020f844, 0xb2001c40, 0xdcf3428b, 0xf2402100, 0x42902200, 0xf844da04, 0x1c401020, 
+    0xe7f8b200, 0x464b20ba, 0x3105eb00, 0x4652484a, 0xe9dd6001, 0xe9cd1004, 0x99070100, 0xf00c4620, 
+    0x20bbfe11, 0xeb00465b, 0x48433105, 0x070cf1c7, 0x200e6001, 0x2020f85a, 0x1020f859, 0x4352413a, 
+    0xfb014139, 0xf8442101, 0xf8561020, 0xeb022020, 0xf84601e1, 0xf8541020, 0xf8531020, 0x42912025, 
+    0xf843dd03, 0xf8281025, 0x1c400015, 0x28c3b200, 0xf938dbe0, 0x1e481015, 0x0c81eb04, 0x3021f854, 
+    0x2020f854, 0xf8dc4408, 0xf04fc004, 0xeba24120, 0x44670743, 0x12bb1ad2, 0xf2f3fb92, 0xeb022300, 
+    0x4a292040, 0xfba03a20, 0xea4f7e01, 0x61907ce0, 0xfb0c69d2, 0xfb00e101, 0x17d31103, 0xf00b4638, 
+    0xf8dfee1c, 0xf04f808c, 0x18804240, 0x0828f1a8, 0x31fff141, 0x07c5eb08, 0x3b00f44f, 0x0100e9c7, 
+    0xf858481c, 0xf8401035, 0xf2401025, 0x46581103, 0xfb77f7e4, 0x79396838, 0xea400c00, 0xb2814001, 
+    0xf7e44658, 0xf838fb5d, 0xb2810035, 0xf7e44658, 0x20bcfb57, 0x3105eb00, 0x1c6d4807, 0xe01bb26d, 
+    0x0002bf10, 0x000301b8, 0xd003044c, 0x00030222, 0x00030394, 0x00030338, 0x00030458, 0x00038d5c, 
+    0x00030227, 0xd0030864, 0x000309e4, 0x00030214, 0x0003d1c0, 0x00030fb4, 0x60012d05, 0xaed8f6ff, 
+    0x0228f108, 0x0314f102, 0x1e682500, 0x80186015, 0xf856200e, 0xf8441020, 0xf8561020, 0xf8521020, 
+    0x42b97025, 0xf842dd03, 0xf8231025, 0x1c400015, 0x28c3b200, 0xf933dbed, 0x1e410015, 0x0480eb04, 
+    0x3020f856, 0xf8564408, 0x68642021, 0x0643eba2, 0x1ad24434, 0xfb9212a3, 0x4bfdf2f3, 0xeb022400, 
+    0x61992140, 0x4220f04f, 0xfba117ce, 0xfb060702, 0xfb017202, 0x69da2104, 0xf00b17d3, 0x4ef5ed8e, 
+    0x4240f04f, 0x4ff51880, 0x31fff141, 0x04c5eb06, 0x3800f44f, 0x0100e9c4, 0xf85648ef, 0x61411035, 
+    0xf24020bd, 0x60381103, 0xf7e44640, 0x6820faea, 0x0c007921, 0x4001ea40, 0x4640b281, 0xfad0f7e4, 
+    0x0035f836, 0x4640b281, 0xfacaf7e4, 0x0035f836, 0xb2017922, 0x0c006820, 0x4002ea40, 0xf7f2b200, 
+    0x20bef91a, 0x48de6038, 0x0000f990, 0xf874f7f2, 0x603820bf, 0x2001b009, 0x4ff0e8bd, 0xb990f7ea, 
+    0x4ffee92d, 0x48d72500, 0x462c2101, 0x9502462a, 0xfbccf00c, 0x28014ed2, 0x2301d009, 0x31fef240, 
+    0x0000f996, 0xf7f22200, 0xe8bdf8c0, 0x22088ffe, 0x015148cd, 0xfbd1f00c, 0x23002208, 0xfa4f0151, 
+    0x48c9fb80, 0xfbbbf00c, 0xf04f48c8, 0x4fc8090a, 0x0301f04f, 0x831cf8df, 0x0200f04f, 0x28017800, 
+    0xe9cdd04b, 0xf9968700, 0x20011000, 0xf85ff7ea, 0xc308f8df, 0xf8df2000, 0x4643a300, 0x0850f10c, 
+    0xe030f85c, 0x1010f93a, 0x2011f937, 0x1011f933, 0x2e0efba2, 0xf8581955, 0xf1002030, 0xb2c00001, 
+    0x1202fba1, 0x4548190c, 0x48b5d3ea, 0xf9961b2c, 0xf04f1000, 0x4fa60500, 0x0203f04f, 0x4021f840, 
+    0xf04f6978, 0xf1000138, 0x61780001, 0xf00c48ad, 0x2800fb84, 0xf8dfd07e, 0x23038290, 0xf1082202, 
+    0x210c08c4, 0xf00c4640, 0xf8dffb6a, 0xf44f927c, 0x90020000, 0x0956f109, 0x4899e09b, 0x8700e9cd, 
+    0x1000f990, 0xf7ea2001, 0x2400f812, 0x826cf8df, 0xf10821c9, 0xfb190850, 0x4897fa01, 0x3a284a97, 
+    0x1014f930, 0xf8304893, 0xf8220011, 0x4a900014, 0x5011f832, 0xfb114a91, 0x3a14f10a, 0x5014f822, 
+    0xf200fb10, 0x2205fb15, 0x2302fb81, 0x200004c1, 0x461f4616, 0xeca0f00b, 0x48880c02, 0x4201ea42, 
+    0x1409463b, 0x00c4eb00, 0x2100e9c0, 0x463204e9, 0xf00b2000, 0x0c02ec92, 0x4201ea42, 0x00c4eb08, 
+    0x1c641409, 0x454cb2e4, 0x2100e9c0, 0x4c74d3c5, 0xf9942100, 0xf7f20000, 0x4974f958, 0x23012000, 
+    0x7008461a, 0xf9944601, 0xf7f10000, 0x4875fffe, 0x21382203, 0xfb11f00c, 0xd0322800, 0x23034c6a, 
+    0x34c42202, 0x4620210c, 0xfaf9f00c, 0xf44f4d66, 0xe0000100, 0x3556e069, 0xe0069102, 0x462a210a, 
+    0xf7eba802, 0x2801fbdf, 0x2202d006, 0x210c4620, 0xfaf3f00c, 0xd1f12800, 0x30cc485b, 0xfac2f00c, 
+    0x81604c53, 0x30ca4858, 0xfabcf00c, 0x485681a0, 0xf00c30d4, 0x81e0fab7, 0x30d24853, 0xfab2f00c, 
+    0xe0758220, 0x464a210b, 0xf7eba802, 0x2801fbbb, 0x2202d006, 0x210c4640, 0xfacff00c, 0xd1f12800, 
+    0x30cc4849, 0xfa9ef00c, 0x48478078, 0xf00c30ca, 0x80b8fa99, 0x30d44844, 0xfa94f00c, 0x484280f8, 
+    0xf00c30d2, 0xb200fa8f, 0xf9b78138, 0xf9b71002, 0x4291200a, 0xf9b7d10f, 0xf9b72004, 0x429a300c, 
+    0xf9b7d109, 0xf9b72006, 0x429a300e, 0xf9b7d103, 0x42902010, 0x697ad003, 0x1e522501, 0x8179617a, 
+    0x81b988b9, 0x81f988f9, 0x17e38238, 0x46229500, 0x0000f996, 0xfa0ff7f2, 0x0200f248, 0x10510055, 
+    0xdd152c00, 0xdd0f4294, 0x2200482f, 0xf00c213f, 0x281afa84, 0xf240d202, 0xe00111ff, 0x31fef240, 
+    0xdc0f42ac, 0xe00d0849, 0xdd08428c, 0xe0092103, 0x42904260, 0x42a8dd05, 0x2105dd01, 0x2102e002, 
+    0x2100e000, 0x0000f996, 0x461a2301, 0xff4df7f1, 0x48152208, 0xf38bfa1f, 0xf00c0151, 0xe684fa50, 
+    0x4ff0e92d, 0xf44fb089, 0x90023000, 0x48171084, 0xfa28f00c, 0x0003f010, 0x0100f241, 0x2801d005, 
+    0x2802d026, 0x2803d028, 0x9102d027, 0x0000e025, 0x000309c4, 0x0003d198, 0x00030fb4, 0x00030458, 
+    0x00030227, 0xd1800000, 0xd0035126, 0x00030225, 0x000339dc, 0x000331dc, 0x0002b6e4, 0x0003ce50, 
+    0x00030fa4, 0xd28f007c, 0xd0034200, 0xd003086e, 0x0000f244, 0xe0009002, 0x22009402, 0x21019802, 
+    0x70d0eb00, 0x90071040, 0xf00c489b, 0x2801f9ff, 0x489ad174, 0x0b0af04f, 0x28017800, 0x2400d005, 
+    0x78004897, 0xd1712800, 0xf8dfe06b, 0x2500a258, 0x21004895, 0x1045eb00, 0xf9d7f00c, 0x20004993, 
+    0x22002301, 0x0015f821, 0xf8304891, 0x1c491015, 0x1015f820, 0x4618498f, 0x1a00e9cd, 0xf7e9b269, 
+    0x2400fe96, 0x488ce03f, 0x4a8c23c9, 0x1014f930, 0xf8304888, 0xf8220011, 0x32140014, 0x6011f83a, 
+    0x6014f822, 0xf203fb1b, 0xf102fb11, 0xf200fb10, 0x2206fb16, 0x7302fb81, 0x200004c1, 0x463a4698, 
+    0xeb2af00b, 0x0c024b7d, 0x0985eb05, 0xea423328, 0xeb034201, 0x46431009, 0xeb001409, 0xe9c000c4, 
+    0x04f12100, 0x2000463a, 0xeb16f00b, 0x4b740c02, 0x4201ea42, 0x1009eb03, 0xeb001409, 0x1c6400c4, 
+    0xe9c0b2e4, 0x455c2100, 0x1c6dd3bd, 0x2d04b2ed, 0x4862d39e, 0x70012100, 0x7001486a, 0xe8bdb009, 
+    0x48698ff0, 0x0000f990, 0xd0784284, 0x78004867, 0xd0f32801, 0x78004866, 0xd0ef2801, 0x78004865, 
+    0xd0eb2801, 0x23014e57, 0xb2614d5a, 0x468a2200, 0xe9cd4618, 0xf7e95600, 0x4d58fe2a, 0xeb042000, 
+    0x46010384, 0x46813528, 0x1503eb05, 0x4d549508, 0x46804602, 0x1303eb05, 0xe02a9301, 0x4f499b08, 
+    0x03c0eb03, 0x5600e9d3, 0xf9334b4b, 0x93003010, 0x3013f937, 0xce03fba5, 0xfb0617df, 0xfb05e303, 
+    0xeb1c3307, 0x4f430909, 0x9b014159, 0x03c0eb03, 0x5600e9d3, 0xf9379b00, 0xfba53013, 0x17dfce03, 
+    0xe303fb06, 0x3307fb05, 0x0808eb1c, 0x1c40415a, 0x4558b2c0, 0xebb9d3d2, 0xeb610008, 0xf06f0102, 
+    0x22004300, 0x418a1a1b, 0xf06fda02, 0xe0054000, 0x1a824a39, 0x31fff171, 0x4837da00, 0x2800ad03, 
+    0xf8454601, 0xda000024, 0x9a024249, 0xdd0d4291, 0xda052800, 0xf04f482b, 0x700101ff, 0xe034e014, 
+    0x4828dd2e, 0x0101f04f, 0xe01b7001, 0xf9924a25, 0x00491000, 0x2800d022, 0xda004601, 0x9b074249, 
+    0xdd1b4299, 0xda0c2800, 0xf8304818, 0xf1a11014, 0xf8200102, 0xf06f1014, 0x46500101, 0xff97f7f1, 
+    0xdd0de00e, 0x0102f04f, 0xf7f14650, 0x480fff90, 0x1014f830, 0xf8201c89, 0xe0011014, 0x70102000, 
+    0xf8554916, 0xf8410024, 0x1c640024, 0x2c04b2e4, 0xaed6f4ff, 0x0000e742, 0xd1800000, 0x00030226, 
+    0x0003031c, 0x000339dc, 0xd0030882, 0x0003022a, 0x00030232, 0x000331dc, 0x0002b6e4, 0x0003cef0, 
+    0x0003d058, 0x000309c4, 0x00030227, 0x00030265, 0x00030c5b, 0x00030c5c, 0x80000001, 0x00030fa4, 
+    0x41f0e92d, 0x460e2400, 0x46252809, 0xe8dfd215, 0x0705f000, 0x140c0a15, 0x0012100e, 0xe00d2409, 
+    0x25012408, 0x2401e00a, 0x2404e008, 0x2402e006, 0x2405e004, 0x2406e002, 0x2403e000, 0xb12e4f0e, 
+    0xf00c4638, 0xf000f86f, 0xe000000f, 0x02314620, 0x1104ea41, 0x46384301, 0xf00cb289, 0x462bf866, 
+    0xe8bd4805, 0x220041f0, 0x30402101, 0xb877f00c, 0xe7c52100, 0xe7c32101, 0xd0030460, 0x41f0e92d, 
+    0x2a014e19, 0x0880f44f, 0x46074614, 0xd001b24d, 0xd1112c02, 0x46402170, 0xff43f7e3, 0xf7ed4638, 
+    0x2000fb81, 0xf86cf7ed, 0x46292001, 0x70302200, 0xf86df7ed, 0xd0032c02, 0x2c02b13c, 0xe00fd005, 
+    0xf44f2100, 0xf7eb2080, 0x2200f8c3, 0x46104629, 0xf85df7ed, 0x70302000, 0x46402171, 0xff49f7e3, 
+    0xe8bd2001, 0x000081f0, 0x00030ae4, 0x4cfcb510, 0xf00c4620, 0xf64ef817, 0x400861ee, 0x1111f241, 
+    0x46204401, 0x4010e8bd, 0xb80ff00c, 0x4cf4b510, 0xf00c4620, 0xf242f807, 0x43012122, 0xf00c4620, 
+    0x4620f804, 0xfffef00b, 0x51ddf64d, 0x46204001, 0x4010e8bd, 0xbff9f00b, 0xf241b570, 0x46050400, 
+    0x4603220c, 0x462148e7, 0xf809f00c, 0x220c48e6, 0x4621462b, 0xf803f00c, 0x220c48e4, 0x4621462b, 
+    0xfffdf00b, 0x4621462b, 0x4070e8bd, 0x220c48e0, 0xbff5f00b, 0x47f0e92d, 0xf6404cda, 0x220b0600, 
+    0x46074689, 0x46314603, 0xf00b4620, 0x4dd6ffe8, 0x463b220b, 0x46284631, 0xffe1f00b, 0x834cf8df, 
+    0x463b220b, 0x46404631, 0xffd9f00b, 0x4ed04631, 0x463b220b, 0xf00b4630, 0xf240ffd2, 0x464b4700, 
+    0x4639220a, 0xf00b4620, 0x220affca, 0x4639464b, 0xf00b4628, 0x220affc4, 0x4639464b, 0xf00b4640, 
+    0x464bffbe, 0x46304639, 0x47f0e8bd, 0xf00b220a, 0xe92dbfb6, 0xf8df5ff0, 0x461e92ec, 0x460d4614, 
+    0x8028f8dd, 0x21e02205, 0x46034607, 0xf00b4648, 0xf8dfffa6, 0x2205a2d4, 0x463b21e0, 0xf00b4650, 
+    0xf8dfff9e, 0x2205b2c8, 0x463b21e0, 0xf00b4658, 0x463bff96, 0x22054fae, 0x463821e0, 0xff8ff00b, 
+    0xd1212d03, 0x2c02b10c, 0x2e01d101, 0xf008d011, 0x281b00ff, 0x2304d00d, 0x22054658, 0xf00b21e0, 
+    0x2304ff7e, 0x22054638, 0xe8bd21e0, 0xf00b5ff0, 0x2304bf76, 0x22054648, 0xf00b21e0, 0x2304ff70, 
+    0x22054650, 0xe7f021e0, 0x9ff0e8bd, 0x46032200, 0x21074898, 0xbf63f00b, 0x4d96b570, 0x0400f248, 
+    0x46212300, 0x4628220f, 0xff59f00b, 0x46212301, 0x4628220f, 0xff53f00b, 0x46284621, 0x4070e8bd, 
+    0x220f2300, 0xbf4bf00b, 0x2801b570, 0x460d4604, 0xb92cd000, 0x22044888, 0x2130460b, 0xff3ff00b, 
+    0xd0012c02, 0xd1082c00, 0x462b4883, 0x4070e8bd, 0x21302204, 0xf00b3080, 0xbd70bf32, 0x41f0e92d, 
+    0x46150c17, 0x460c2801, 0xd0004606, 0x2c01b9ce, 0xb94cd000, 0x46394878, 0xf00b1d00, 0x4876ff06, 
+    0x1d80b2a9, 0xff01f00b, 0xd0002c02, 0x4872b94c, 0x30084639, 0xfef9f00b, 0xb2a9486f, 0xf00b300a, 
+    0x2e02fef4, 0x2e00d001, 0x2c01d11c, 0xb94cd000, 0x46394869, 0xf00b3084, 0x4867fee8, 0x3086b2a9, 
+    0xfee3f00b, 0xd0012c02, 0xd10b2c00, 0x46394862, 0xf00b3088, 0xb2a9feda, 0xe8bd485f, 0x308a41f0, 
+    0xbed3f00b, 0x81f0e8bd, 0x21004b5c, 0xb130b510, 0xd0072801, 0xd00d2802, 0xd1092803, 0x2200e00d, 
+    0xe0012103, 0x210c2202, 0xf00b4618, 0xb241fee6, 0xbd10b2c8, 0x21302204, 0x2206e7f6, 0xe7f321c0, 
+    0x4d48b570, 0x1cad4604, 0xf00b4628, 0x4e4cfeab, 0x0000f364, 0x46304601, 0xfea7f00b, 0xd1092c00, 
+    0xf00b4628, 0xf020fe9f, 0x46300102, 0x4070e8bd, 0xbe9bf00b, 0xb570bd70, 0x1ca44c3a, 0xf00b4620, 
+    0x4d3ffe91, 0x0102f040, 0xf00b4628, 0x4620fe8e, 0xfe88f00b, 0x0102f020, 0xe8bd4628, 0xf00b4070, 
+    0xb57fbe84, 0x46144b37, 0xcb4e460d, 0x004ee88d, 0xffaaf7ff, 0x0020f85d, 0xeb00b2a1, 0xf00b0045, 
+    0xbd7ffe74, 0x4604b510, 0x1c804826, 0xfe6af00b, 0x7100f240, 0x2104ea01, 0x60e2f420, 0xe8bd4308, 
+    0xf0404010, 0x48260110, 0xbe5ff00b, 0x2801b510, 0xd0004604, 0x2301b92c, 0x2200481f, 0xf00b4619, 
+    0x2c02fe6e, 0x2c00d001, 0x481bd108, 0x22002301, 0xe8bd4619, 0x30804010, 0xbe61f00b, 0xe92dbd10, 
+    0x4c1641f0, 0xb283461d, 0x22004616, 0x2103460f, 0xf00b4620, 0xb2bbfe54, 0x22024620, 0xf00b210c, 
+    0xb2b3fe4e, 0x22044620, 0xf00b2130, 0xb2abfe48, 0xe8bd4620, 0x220641f0, 0xf00b21c0, 0x0000be40, 
+    0xd03c8000, 0xd0033040, 0xd0033240, 0xd0033440, 0xd0033640, 0xd0033a00, 0xd0033b00, 0xd0035026, 
+    0xd0033842, 0x0002b7d0, 0x5ff0e92d, 0x469a4e5a, 0x46894617, 0xb028f8dd, 0x9c0c4605, 0xf00b4630, 
+    0xf8dffe01, 0xf0208158, 0x43290101, 0xf00b4640, 0x4630fdfc, 0xfdf6f00b, 0x0002f020, 0x0145ea40, 
+    0xf00b4640, 0x4630fdf2, 0xfdecf00b, 0x0104f020, 0xea414640, 0xf00b0189, 0x4630fde8, 0xfde2f00b, 
+    0x010ff06f, 0x0070f020, 0x1107eb01, 0xb2814308, 0xf00b4640, 0x4630fdda, 0xfdd4f00b, 0x6170f420, 
+    0xea414640, 0xf00b210b, 0x1cb7fdd0, 0xf00b4638, 0xf420fdc9, 0xf108517c, 0xea410502, 0x4628210a, 
+    0xfdc3f00b, 0xf00b4638, 0xf020fdbd, 0x980b017f, 0x46284301, 0xfdb9f00b, 0x0000f994, 0x21032200, 
+    0x1d30b283, 0xfdcbf00b, 0x0001f994, 0x21032200, 0x482bb283, 0xfdc3f00b, 0x0002f994, 0x21032200, 
+    0x4828b283, 0xfdbbf00b, 0x0003f994, 0x21032200, 0x4825b283, 0xfdb3f00b, 0xf00b4630, 0xf020fd93, 
+    0xf4400008, 0x46405180, 0xfd8ff00b, 0xf00b4630, 0xf040fd89, 0x46400108, 0xfd87f00b, 0xf00b4630, 
+    0xf020fd81, 0x46400108, 0x5ff0e8bd, 0xbd7df00b, 0x4c12b570, 0x4616460d, 0x46204601, 0xfd75f00b, 
+    0x46291ca0, 0xfd71f00b, 0x46311d20, 0xfd6df00b, 0x46284d09, 0xfd66f00b, 0x0108f040, 0xf00b4620, 
+    0x4628fd64, 0xfd5ef00b, 0x0108f020, 0xe8bd4620, 0xf00b4070, 0x0000bd5a, 0xd0033180, 0xd0033980, 
+    0xd0033384, 0xd0033584, 0xd0033784, 0x48fd2300, 0x461a2101, 0xf00bb510, 0x48fafd62, 0x1103f240, 
+    0x4010e8bd, 0xf00b1c80, 0xe92dbd40, 0x4df65ff0, 0x22062301, 0x46282140, 0xfd51f00b, 0x46282301, 
+    0x21202205, 0xfd4bf00b, 0x46282301, 0x21102204, 0xfd45f00b, 0x46282301, 0x21082203, 0xfd3ff00b, 
+    0x46282300, 0x21402206, 0xfd39f00b, 0x46282300, 0x21202205, 0xfd33f00b, 0x46282300, 0x21102204, 
+    0xfd2df00b, 0x46282300, 0x21082203, 0xfd27f00b, 0xf24048de, 0xf00b7100, 0x48dcfd08, 0x0800f248, 
+    0x1d004641, 0xfd01f00b, 0x220d48d9, 0x0100f242, 0xfd23f00b, 0xf64f4cd4, 0xf2407b80, 0x3c1a7aff, 
+    0x1da71ca6, 0xd0562800, 0x46412301, 0x4628220f, 0xfd05f00b, 0x0902f1a4, 0x46482300, 0x21782203, 
+    0xfcfdf00b, 0x46482300, 0x461a2107, 0xfcf7f00b, 0x465923cd, 0x46482207, 0xfcf1f00b, 0xf2402200, 
+    0x46516366, 0xf00b4620, 0x231cfcea, 0x0100f64f, 0x4620220b, 0xfce3f00b, 0x46302300, 0x461a211f, 
+    0xfcddf00b, 0xf2402302, 0x220511e0, 0xf00b4630, 0x2300fcd6, 0x0100f24f, 0x4630220c, 0xfccff00b, 
+    0xf6402300, 0x22096100, 0xf00b4630, 0x1d20fcc8, 0x213df640, 0xfca9f00b, 0x46382307, 0x210f2200, 
+    0xfcbdf00b, 0xf643237d, 0x220471f0, 0xf00b4638, 0x2302fcb6, 0x2300e056, 0x220f4641, 0xf00b4628, 
+    0xf8dffcae, 0x23009284, 0xf1a92203, 0x2178091c, 0xf00b4648, 0x2300fca4, 0x21074648, 0xf00b461a, 
+    0x2300fc9e, 0x22074659, 0xf00b4648, 0x2300fc98, 0x461a4651, 0xf00b4620, 0x2300fc92, 0x0100f64f, 
+    0x4620220b, 0xfc8bf00b, 0x46302300, 0x461a211f, 0xfc85f00b, 0xf2402300, 0x220511e0, 0xf00b4630, 
+    0x2300fc7e, 0x0100f24f, 0x4630220c, 0xfc77f00b, 0xf6402300, 0x22096100, 0xf00b4630, 0x2100fc70, 
+    0x0006f109, 0xfc51f00b, 0x46382300, 0x461a210f, 0xfc65f00b, 0xf6432300, 0x220471f0, 0xf00b4638, 
+    0x2300fc5e, 0x0100f24c, 0x4638220e, 0xfc57f00b, 0x23004875, 0x461a2103, 0xf00b3812, 0xf8dffc50, 
+    0xf240b1c4, 0xf10b1103, 0x46580b02, 0xfc2df00b, 0x21004870, 0xfc29f00b, 0x486a2300, 0x461a2101, 
+    0xfc3df00b, 0xf44f4c6c, 0x78213080, 0xfcb0f7ea, 0x2300486a, 0x21802207, 0xfc31f00b, 0x0600f242, 
+    0x46307821, 0xfca4f7ea, 0x230e4f5f, 0xf6432209, 0x1ebf6100, 0xf00b4638, 0x2302fc22, 0x0100f24c, 
+    0x4638220e, 0xfc1bf00b, 0x46282303, 0x21072200, 0xfc15f00b, 0x46282301, 0x0399220e, 0xfc0ff00b, 
+    0x46312301, 0x4628220d, 0xfc09f00b, 0x46282301, 0x21802207, 0xfc03f00b, 0x1a00f240, 0x23014628, 
+    0x22084651, 0xfbfbf00b, 0x10f07821, 0xfc70f7ea, 0x46282300, 0x21802207, 0xfbf1f00b, 0x46512300, 
+    0x46282208, 0xfbebf00b, 0x9100f8df, 0x46482100, 0xfbcbf00b, 0xf1092100, 0xf00b0004, 0x7821fbc6, 
+    0xf7ea4630, 0x2300fc55, 0x22084651, 0xf00b4658, 0x4838fbd6, 0x220f2301, 0x46414645, 0xfbcff00b, 
+    0x46512301, 0x46482208, 0xfbc9f00b, 0x46582300, 0x21022201, 0xfbc3f00b, 0x46582300, 0x461a2101, 
+    0xfbbdf00b, 0x46482301, 0x025f2209, 0xf00b4639, 0x7821fbb6, 0xf7ea2004, 0x2301fc2b, 0x22084651, 
+    0xf00b4658, 0x2301fbac, 0x21024658, 0xf00b461a, 0x7821fba6, 0xf7ea4630, 0x481efc1b, 0x220f2300, 
+    0xf00b4629, 0x2301fb9c, 0x22004658, 0xf00b4619, 0x7821fb96, 0xf7ea00f0, 0x2300fc0b, 0x22084651, 
+    0xf00b4648, 0x2300fb8c, 0x22094639, 0xf00b4648, 0x4f0dfb86, 0x05ec2501, 0x12e6370c, 0x0802f107, 
+    0x4620e020, 0xfbf2f7ea, 0xdc1b1e04, 0x25004c0c, 0xf00b4620, 0xf440fb57, 0x46206180, 0xfb55f00b, 
+    0x0000e01e, 0xd0034000, 0xd003e834, 0xd03c8308, 0xd03c8038, 0xd0039004, 0x00030223, 0xd0034228, 
+    0xd003517a, 0x4631220c, 0xf00b4638, 0x2800fb66, 0x220cd0d7, 0x46404631, 0xfb5ff00b, 0xd0d02800, 
+    0xe8bd4628, 0xe92d9ff0, 0x20005ffc, 0x20049001, 0xf9baf7ee, 0xf64b48b3, 0xf00b31b1, 0x4db2fb26, 
+    0x46282100, 0xfb21f00b, 0xf24148ae, 0x220c0a00, 0x38804651, 0xfb41f00b, 0xf1a507c0, 0xd0010406, 
+    0xe0002301, 0x46202300, 0x21022201, 0xfb27f00b, 0x9298f8df, 0xf8df46a8, 0x2601b290, 0x4da54fa4, 
+    0x0b16f10b, 0x0000f899, 0x0401f000, 0x21014640, 0xfafbf00b, 0xf00b4658, 0x07c0faf5, 0x2100d016, 
+    0xf00b4640, 0xb144faf2, 0xf906f7e3, 0x010ff000, 0xf001fa06, 0xf7ea7839, 0x4628fb7b, 0xfae2f00b, 
+    0x6100f440, 0xf00b4628, 0xe7dffae0, 0xf00b4628, 0x2100fad9, 0xf00b4628, 0xf8dffad8, 0x2200b22c, 
+    0xf1ab2101, 0x46580b04, 0xfaf7f00b, 0xd00f42a0, 0xfd7cf7ff, 0xf04f4884, 0xf04f0200, 0x30140101, 
+    0xf00bb1dc, 0xea26faea, 0x46580100, 0xfabdf00b, 0x220c4881, 0x46514656, 0xfadff00b, 0x3c084c7a, 
+    0x487db178, 0x4631220c, 0xf00b1c80, 0xb140fad6, 0xf00b4620, 0xb120faa7, 0xf00be025, 0x4601face, 
+    0x2003e7e3, 0x66adf64d, 0xe00a9001, 0x462a210c, 0xf7eaa801, 0x2801fba7, 0x4631d007, 0xf00b4620, 
+    0xf7fffa94, 0x2800fd52, 0x2200d0f0, 0x21014658, 0xfab3f00b, 0x1d124a64, 0xd07c2800, 0x11e1f24d, 
+    0xf00b4610, 0x2103fa82, 0xf00b4620, 0x485dfa7e, 0x31b2f64b, 0xfa79f00b, 0x23014860, 0x21402206, 
+    0xfa8df00b, 0x2300485e, 0x21202205, 0xfa87f00b, 0x464d4c59, 0x0000f999, 0x28003c0c, 0x2802d07d, 
+    0x2301d07b, 0x22044620, 0xf00b2110, 0x2301fa78, 0x21402206, 0xf00b4620, 0x200ffa72, 0x49519000, 
+    0x3395f647, 0xf2474850, 0xf7ed0282, 0x2100fd85, 0xf7ea2004, 0x2001fadd, 0xfe5bf7ef, 0x0000f995, 
+    0xd0702800, 0xd06e2802, 0x46202300, 0x21102204, 0xfa55f00b, 0x22062300, 0x46202140, 0xfa4ff00b, 
+    0xf44f2100, 0xf7ea3080, 0x2300fac3, 0x22074620, 0xf00b2180, 0x2208fa44, 0x23004620, 0x46310156, 
+    0xfa3df00b, 0x20042100, 0xfab2f7ea, 0x0000f995, 0x2802b3a0, 0x2301d051, 0x22084631, 0xf00b4620, 
+    0x2100fa2e, 0xf00b4640, 0x2301fa10, 0x220d482f, 0x4621035c, 0xe028e000, 0xfa21f00b, 0x2301482c, 
+    0x4621220d, 0xfa1bf00b, 0x01e07839, 0xfa90f7ea, 0x23004c28, 0x21102204, 0xf00b4620, 0x2301fa10, 
+    0x22044620, 0xf00b2110, 0x2301fa0a, 0x22074620, 0xf00b2180, 0x7839fa04, 0xe009e001, 0xf240e01d, 
+    0xf7ea2000, 0xe8bdfa75, 0xf24d9ffc, 0xe75711e0, 0x46202301, 0x21082203, 0xf9f1f00b, 0x22052301, 
+    0xe7772120, 0x2300e7ff, 0x22034620, 0xf00b2108, 0x2300f9e6, 0x21202205, 0x2301e78f, 0x21802207, 
+    0x0000e7ac, 0xd03c80b8, 0xd003400e, 0x000301c8, 0x00030223, 0xd003517a, 0xd003e840, 0xd03c830e, 
+    0xd0034228, 0xffffaa02, 0xffffa14d, 0xd003c81e, 0xd003d81e, 0xd0039000, 0x4d09b570, 0x21002400, 
+    0x0044eb05, 0xf9a1f00b, 0x2c301c64, 0xbd70dbf7, 0xf7ffb510, 0xe8bdfff1, 0x20004010, 0xb90df7ef, 
+    0xd003e200, 0x41f0e92d, 0xf7f92400, 0x4866ff29, 0x4d684f66, 0xc1a0f8df, 0x48657801, 0x683a4e67, 
+    0x3000f990, 0xd0042b03, 0xd0132b05, 0xd0242b04, 0x4863e02f, 0x28126800, 0xf64dd302, 0xe00160f7, 
+    0x60eaf64e, 0x78284342, 0xb1081412, 0xe020240a, 0xe01e2409, 0x28017830, 0x2802d009, 0xf89cd007, 
+    0x43044000, 0x2803d003, 0x2401d001, 0x7828e011, 0x2404b108, 0x2403e00d, 0x7830e00b, 0xd02b2801, 
+    0xd0292802, 0x4000f89c, 0xd0254304, 0xd0232803, 0xf6432402, 0x428270ff, 0x1e42db00, 0x20004d49, 
+    0x1404eb05, 0x0507f1c0, 0x5015f934, 0xdc034295, 0xb2001c40, 0xdbf52808, 0xf1c04a42, 0x32b00007, 
+    0xf8122b04, 0x4a405010, 0x2b05d00c, 0x2d0cd02b, 0x7810d25f, 0xe01cb318, 0xb1087828, 0xe7d82406, 
+    0xe7d62405, 0x28017830, 0x2802d00c, 0xf89cd00a, 0x43033000, 0x2803d006, 0xe006d004, 0xe0222401, 
+    0xe0202400, 0xd2fb2d2d, 0x2d0ce7f8, 0x7810d247, 0x290fb138, 0x2407d23a, 0x2406e019, 0x2405e017, 
+    0x2402e011, 0x7830e00f, 0xd0052801, 0xd0032802, 0x3000f89c, 0xd1e84318, 0xd2012d23, 0xe0022404, 
+    0xd21e2d2d, 0x48212403, 0x28017800, 0x2000d0e5, 0xda002c00, 0x481e4604, 0xf8e7f00b, 0xb2818838, 
+    0x3020481b, 0xf8e1f00b, 0x03207831, 0x2001eb00, 0xb2814428, 0x30264816, 0xf8d7f00b, 0xe8bd4620, 
+    0x2d4181f0, 0x2d55d3cd, 0xe7b7d2ba, 0xd2c62919, 0x2d23e7c3, 0x2d2dd3c3, 0x2d37d3d0, 0x2d41d3d2, 
+    0x2d4bd3bf, 0xe7a9d2ac, 0x0003031e, 0x000303b4, 0x00030222, 0x0003031c, 0x00030312, 0x00030394, 
+    0x000301cc, 0x00030b24, 0x0003028c, 0x0003028d, 0xd0035182, 0xb50848fe, 0x90008800, 0x780348fd, 
+    0xf99048fd, 0x48fd2000, 0x20007801, 0xf901f7ff, 0x4008e8bd, 0xf7ee2004, 0xb57cbfab, 0xf7f12001, 
+    0x4cf7fa85, 0x2803b240, 0xd1157020, 0x880048f5, 0x7facf5b0, 0xf5b0d008, 0xd0057fa4, 0x7fb4f5b0, 
+    0xf5b0d002, 0xd1077fbc, 0x70202005, 0x230748ee, 0x213c2202, 0xf893f00b, 0xf7ea7820, 0x49ebf8f9, 
+    0x20087008, 0xf89ef7f0, 0xf7ed7820, 0x49e3fb6b, 0x95002500, 0x78202301, 0x7809461a, 0xff9cf7e5, 
+    0x46082101, 0xfbe4f7ed, 0x4100f640, 0x7203f647, 0x95002317, 0xf7ed0088, 0x48ddfb8f, 0xf00b2102, 
+    0x48dcf854, 0x7131f640, 0xf84ff00b, 0x23002001, 0xe9cd4602, 0x46190500, 0xfa26f7eb, 0x201849d6, 
+    0xbd7c6008, 0x5ffce92d, 0x46064fd4, 0xf8df8e80, 0xf8dfb350, 0x28e28350, 0xd079683b, 0xb170dc05, 
+    0xd018289a, 0xd174289b, 0x28e3e020, 0xf5b0d006, 0xd06f7f90, 0x7080f5a0, 0xd16a3821, 0x49c8e1c2, 
+    0x32fff04f, 0x0000f8db, 0xf0071d09, 0x1d01f8b9, 0x209ad108, 0x49c2e0ae, 0xf8db2200, 0x1d090000, 
+    0xf8aef007, 0xd0311d41, 0xd1e82801, 0x1d0048bc, 0x1000f9b0, 0xd1e2296e, 0x5580f04f, 0xf04f4681, 
+    0x46284220, 0xff4bf7e2, 0x1000f898, 0x5290f04f, 0x46284644, 0xff43f7e2, 0x28007820, 0x2500d07b, 
+    0x0a05f04f, 0x28012401, 0x2802d012, 0x2803d04a, 0xf8dfd04d, 0x2804928c, 0xa280f8df, 0x2805d07d, 
+    0x2806d06b, 0x2807d06a, 0xe182d069, 0xe071209b, 0xff36f7fb, 0xff41f7ff, 0xff2cf7ff, 0x2300489d, 
+    0xf248220f, 0x301a0100, 0xffe9f00a, 0x23002201, 0xe9cd4611, 0x46104500, 0xf9a6f7eb, 0xf00a489a, 
+    0x499affc1, 0x07018008, 0xd0044899, 0xe0038004, 0xe050e00e, 0x8005e044, 0x49912200, 0xa000f8a9, 
+    0x1d096838, 0xf81df007, 0xd1071d01, 0xe04120e2, 0x2200498b, 0x1d094618, 0xf813f007, 0xd1781d40, 
+    0xe03720e3, 0xff09f7ff, 0xfef4f7ff, 0xf7ffe12e, 0x4d88ff04, 0x220b2300, 0x0100f640, 0xf00a4628, 
+    0x2301ffae, 0x220c4628, 0xf00a0319, 0x4879ffa8, 0x1137f640, 0xff89f00a, 0x2200487f, 0x1d094978, 
+    0xf8a97004, 0x6838a000, 0xffebf006, 0xd10d1d01, 0x1020f240, 0xe113e00e, 0xe06ee00f, 0xe10ee0fd, 
+    0x2200496f, 0x1d094618, 0xffdbf006, 0xd1c61d40, 0x1021f240, 0xe8bd86b0, 0xf7ff9ffc, 0xf7fffece, 
+    0xf999feb9, 0x28050000, 0x2804d034, 0x2000d034, 0x7809496a, 0xd0312901, 0xd0352902, 0xd0392904, 
+    0xd03d2905, 0xd0412906, 0x462c2500, 0xf804f7ff, 0x8800484f, 0x484f9000, 0x1000f89a, 0x484e7803, 
+    0x2000f990, 0xf7fe2003, 0x2004ffa4, 0xffeef7fe, 0x46082100, 0xf808f7ff, 0x462a2101, 0xf7ff2000, 
+    0x2102f81d, 0x20004622, 0xf818f7ff, 0xf7ff2000, 0xe0c7f8cd, 0xe7cb2001, 0xe7c92002, 0x7580f241, 
+    0x2480f641, 0xe01640c5, 0x2580f243, 0x3480f243, 0xe01040c5, 0x1580f645, 0x2480f645, 0xe00a40c5, 
+    0x2580f648, 0x4480f648, 0xe00440c5, 0x6580f24c, 0x0480f64c, 0x40c440c5, 0xf7ffe7b8, 0xf7fffe6e, 
+    0xf7fffe59, 0x2100f868, 0x46082240, 0xf879f7ff, 0x2101220d, 0xf7ff2000, 0x2205f874, 0x20002102, 
+    0xf86ff7ff, 0x21002240, 0xf7ff2001, 0x2101f86a, 0x4608220d, 0xf865f7ff, 0x21022205, 0xf7ff2001, 
+    0x2240f860, 0x20022100, 0xf85bf7ff, 0x2101220d, 0xf7ff2002, 0x2102f856, 0x46082205, 0xf851f7ff, 
+    0x21002240, 0xf7ff2003, 0x220df84c, 0x20032101, 0xf847f7ff, 0x21022205, 0xf7ff2003, 0x2000f842, 
+    0xf80ef7ff, 0xf7ff2003, 0x2301f84d, 0x46192200, 0x5400e9cd, 0xf7eb4618, 0x2301f897, 0x46182200, 
+    0xe9cd2102, 0xf7eb5400, 0xf999f88f, 0xe0270000, 0x00030250, 0x000302a4, 0x000301c8, 0x00030394, 
+    0x00030222, 0x00030318, 0xd0020000, 0x00030223, 0xd03c8304, 0xd003502a, 0x000301cc, 0x000304ec, 
+    0x00030be4, 0x00030214, 0xd0035136, 0x00030252, 0x00030254, 0xd28fffd2, 0x00030227, 0x00030340, 
+    0xd0012805, 0xd11d2804, 0x9500b2c2, 0x3000f89a, 0x20002101, 0xfb48f7fd, 0xf7ffe014, 0xf7fffdde, 
+    0x4838fdc9, 0x7131f640, 0xfe6ff00a, 0x22012300, 0xe9cd4618, 0x46114500, 0xf846f7eb, 0x2001e002, 
+    0xf8d5f7eb, 0x0000f898, 0xf43f2807, 0x2800ae38, 0xf7fed0fb, 0xe632fe4b, 0x21012200, 0xf2afb510, 
+    0xf00630db, 0x2108fd09, 0xf0062002, 0x4926fe67, 0xbd106008, 0x2000b57c, 0xfb3ef7ea, 0x200e2100, 
+    0xfc32f7fd, 0x25004821, 0x46294c21, 0x78029500, 0x78234628, 0xfb08f7fd, 0xf7f02004, 0x481dfd7e, 
+    0x90008800, 0x7821481c, 0x481c7803, 0x2000f990, 0xf7fe2000, 0x2000fe8e, 0xfffef7ea, 0x23002001, 
+    0xe9cd4602, 0x46010500, 0xf7ea4618, 0x4814fffd, 0xf00a2100, 0x4c13fe1a, 0x0000f241, 0xf7e97821, 
+    0xf242fea7, 0x46290550, 0x463006ee, 0xfd15f7e2, 0x0bf07821, 0xfe9cf7e9, 0x46304629, 0x407ce8bd, 
+    0xbd0bf7e2, 0xd003502a, 0x00030be4, 0x00030222, 0x00030394, 0x00030250, 0x000302a4, 0x000301c8, 
+    0xd0034220, 0x00030223, 0x43f8e92d, 0x48ff4606, 0x600149fd, 0xf00a48fe, 0x2000fde2, 0xfadcf7ea, 
+    0xfbd4f7e8, 0x83ecf8df, 0x2400f240, 0xf8984620, 0xf7e81000, 0x48f8fbd5, 0x71fff64f, 0xfdcff00a, 
+    0x20022100, 0xfdfcf7e9, 0x230048f4, 0x21022201, 0xfde5f00a, 0x93c8f8df, 0x22092300, 0x46484621, 
+    0xfdddf00a, 0x230148ee, 0x03d9220f, 0xf00a3012, 0x4fe6fdd6, 0x1d3f2500, 0xb2e12400, 0x0014f817, 
+    0xb2424240, 0xf7feb2e8, 0x1c64ff2c, 0xdbf42c10, 0x2d041c6d, 0x2000dbf0, 0xfef2f7fe, 0xf7fe2003, 
+    0x48dfff31, 0x21012300, 0x30a0461a, 0xfdb7f00a, 0x46082100, 0xff4cf7ea, 0xf7ec201b, 0x2300fecf, 
+    0x22074648, 0xf00a2180, 0x2300fdaa, 0x210148d5, 0xf00a461a, 0x2000fda4, 0xf8989000, 0x22033000, 
+    0x20084601, 0xfa50f7fd, 0x23004dcf, 0x21e02205, 0xf00a4628, 0x4ccdfd94, 0x22052300, 0x462021e0, 
+    0xfd8df00a, 0x8328f8df, 0x22052300, 0x464021e0, 0xfd85f00a, 0x931cf8df, 0x22052300, 0x464821e0, 
+    0xfd7df00a, 0xf7ea2001, 0x2100ff37, 0x2080f44f, 0xfdeef7e9, 0x46112201, 0xf7fa4610, 0x2202fba5, 
+    0x10c3f240, 0xf7fe2107, 0x48bbfcf9, 0xfdd9f7eb, 0xf7fe2000, 0x2100fced, 0x46082302, 0xf7ea2208, 
+    0x230cfaa9, 0x461a2100, 0xf7ea4608, 0x2300fadd, 0x4619461a, 0xf7ea4618, 0x2101fabf, 0xf7ea2000, 
+    0x48a5fa87, 0x22112300, 0xf44f3848, 0xf00a3100, 0x2001fd2f, 0xfa20f7ea, 0x1700f44f, 0x46382100, 
+    0xfdb6f7e9, 0x2100230c, 0x4608461a, 0xfabcf7ea, 0x46382100, 0xfdacf7e9, 0x2100230d, 0x4608461a, 
+    0xfab2f7ea, 0x46382100, 0xfda2f7e9, 0x220504f0, 0x21e010c0, 0x46280f43, 0xfd21f00a, 0x220504b0, 
+    0x21e010c0, 0x46200f43, 0xfd19f00a, 0x22050470, 0x21e010c0, 0x46400f43, 0xfd11f00a, 0x22050430, 
+    0x21e010c0, 0x46480f43, 0xfd09f00a, 0x43f8e8bd, 0xf7e92002, 0xe92dbd26, 0xb08847f0, 0x20004605, 
+    0x4601ae04, 0x1020f846, 0x28041c40, 0xf8dfdbfa, 0x240091f0, 0xa1e8f8df, 0x0800f248, 0x0918f109, 
+    0xf10a466f, 0x46400a06, 0xf7e92100, 0x2101fd61, 0x464a466b, 0xf00b4650, 0x2000fc02, 0x1020f856, 
+    0x2020f857, 0xf8464411, 0x1c401020, 0xdbf52804, 0x2c401c64, 0x2000dbe7, 0x1020f856, 0x11893120, 
+    0x1020f845, 0x28041c40, 0xb008dbf6, 0x0010f105, 0x87f0e8bd, 0x20004603, 0x188cb510, 0xf833e005, 
+    0x1c492011, 0xf202fb12, 0x428c4410, 0xbd10dcf7, 0x4ff8e92d, 0x46044d58, 0x46283d48, 0xfc8cf00a, 
+    0x46832300, 0x461a2101, 0xf00a4628, 0x46aafc91, 0xf00a4650, 0x07c0fc81, 0x4858d1fa, 0x46a92500, 
+    0x8000f8d0, 0xb2692200, 0x46434610, 0xf8cd460e, 0xf7e89000, 0x2700f96e, 0x46bc46be, 0xf938463a, 
+    0x28000012, 0x4603db01, 0x4243e000, 0x42b9b219, 0x460fdd02, 0x46944686, 0xb2121c52, 0xdbee2a80, 
+    0x46402280, 0xe9c42100, 0xf7ffec00, 0x2280ffb3, 0x461160a0, 0xf7ff4640, 0x2280ffad, 0x464060e0, 
+    0xf7ff0051, 0x2280ffa7, 0x1180f240, 0x46406120, 0xffa0f7ff, 0x61602280, 0x00914640, 0xff9af7ff, 
+    0xf2402280, 0x61a02180, 0xf7ff4640, 0x2280ff93, 0x3100f240, 0x464061e0, 0xff8cf7ff, 0xf2402280, 
+    0x62203180, 0xf7ff4640, 0x2701ff85, 0x34286260, 0x20004643, 0xb27a4631, 0x9000f8cd, 0xf919f7e8, 
+    0x46402280, 0xf7ff2100, 0x2280ff75, 0x46116020, 0xf7ff4640, 0x1c7fff6f, 0xb23f6060, 0x2f043408, 
+    0x1c6ddbe6, 0x2d04b22d, 0x4659db8c, 0xf00a4650, 0x4620fc06, 0x8ff8e8bd, 0x4ff0e92d, 0x7d0bf5ad, 
+    0xfe12f7ff, 0xad402000, 0xf8454601, 0x1c401020, 0xdbfa2840, 0xf06f2000, 0xaa86417f, 0xf8424690, 
+    0x1c401020, 0xe01b2804, 0x0003ad5c, 0x00030bf0, 0xc3000088, 0x00030394, 0xd1800048, 0xd03c8310, 
+    0xd0030400, 0xd0031012, 0xd0033040, 0xd0033240, 0xd0033440, 0xd0033640, 0x00030350, 0x000301c4, 
+    0x2400dbdc, 0xf50d46eb, 0xf2407a00, 0x26004700, 0x0900f1c7, 0xd0642c00, 0xb2704649, 0xfa87f7f0, 
+    0x2e041c76, 0x2100dbf6, 0x0000f44f, 0xfc50f7e9, 0xf7ff4668, 0xa880ff1d, 0xfecdf7ff, 0x46dc2000, 
+    0xeb0c0101, 0xeb050681, 0x68b30281, 0x42bb6897, 0xf85cdd06, 0xf8457021, 0x68767021, 0x6301e9c2, 
+    0x188e2203, 0x3026f85c, 0x7026f855, 0xdd0142bb, 0x3026f845, 0x2a0f1c52, 0xf858ddf3, 0x46423020, 
+    0x1020f85a, 0xdd01428b, 0x1020f842, 0x28041c40, 0x1c64dbd6, 0xdbb82c02, 0x680448fe, 0xf8522000, 
+    0x1c401020, 0xc4022804, 0xa884dbf9, 0xfc09f7eb, 0xa9842000, 0x2010f931, 0x28041c40, 0xdbf9c404, 
+    0xf8552000, 0xf8441020, 0x1c401020, 0xdbf82840, 0xf44f2100, 0xf7e91080, 0xf50dfbfb, 0xe8bd7d0b, 
+    0x46398ff0, 0xb510e799, 0x20004604, 0xe0074602, 0x3012f934, 0xda012b00, 0xe0001ac0, 0x1c524418, 
+    0xdbf5428a, 0xb5ffbd10, 0x466d2300, 0xf845461c, 0x1c5b4023, 0xdbfa2b04, 0xe0162300, 0x6013f930, 
+    0x44349c00, 0xeb009400, 0x9e010443, 0xf9b41d1b, 0x443e7002, 0xf9b49601, 0x9e027004, 0x9602443e, 
+    0x4006f9b4, 0x44349e03, 0x428b9403, 0x108bdbe6, 0xb2141e92, 0xf8552100, 0xeb022021, 0x41220263, 
+    0x2021f845, 0x29041c49, 0x2100dbf5, 0xf830e014, 0x9c002011, 0xf8201b12, 0xeb002011, 0x9d010241, 
+    0x1b648854, 0x88948054, 0x1b649d02, 0x88d48094, 0x1b649d03, 0x1d0980d4, 0xdbe84299, 0xe92dbdff, 
+    0xb0934ff0, 0xfd10f7ff, 0x9004200a, 0x4dba2300, 0x210148ba, 0x4400f240, 0xf00a461a, 0x48b7faf9, 
+    0x21012300, 0x3830461a, 0xfaf2f00a, 0xf7fe2000, 0x2140fa8f, 0xf7ea2000, 0x48aef828, 0x090df04f, 
+    0x20006807, 0x90094680, 0x49ad9012, 0x80c84aae, 0x80488088, 0x48ab8008, 0x780349ac, 0xf7eb48a8, 
+    0xf44ffb7f, 0x21001680, 0xf7e94630, 0x2200fb61, 0x46112304, 0xf7ed2001, 0x2100ff9b, 0xf7e94630, 
+    0x12b1fb57, 0x0b01f04f, 0x23009400, 0x46281e5a, 0xb101e9cd, 0xf8cd2103, 0xf7fdb00c, 0x2600fad5, 
+    0x0a38f10d, 0xfb069a04, 0x4621f004, 0x0040eb05, 0xf7ff4684, 0x4660ff58, 0xf7ff4621, 0xf84aff44, 
+    0x1c760026, 0xdbed2e04, 0x4100f240, 0x23009400, 0x1e5a4628, 0xb101e9cd, 0xf8cd2103, 0xf7fdb00c, 
+    0x2600fab3, 0x46219a04, 0xf004fb06, 0x0040eb05, 0xf7ff4684, 0x4660ff38, 0xf7ff4621, 0xf85aff24, 
+    0x18812026, 0x1026f84a, 0x2e041c76, 0xf240dbea, 0x94004100, 0x46282300, 0xe9cd1e5a, 0x2103b101, 
+    0xb00cf8cd, 0xfa90f7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 0x46840040, 0xff15f7ff, 0x46214660, 
+    0xff01f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 0xdbea2e04, 0x94002001, 0x02811e82, 0xe9cd2300, 
+    0x21030101, 0x46289003, 0xfa6ef7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 0x46840040, 0xfef3f7ff, 
+    0x46214660, 0xfedff7ff, 0x2026f85a, 0x188146d3, 0x1026f84a, 0x2e041c76, 0x2201dbe9, 0x46112304, 
+    0xf7ed4610, 0x2100ff05, 0x1080f44f, 0xfac0f7e9, 0x48544953, 0xf8a14a54, 0xf8a19006, 0xf8a19004, 
+    0xf8a19002, 0x78039000, 0x484d4950, 0xfac8f7eb, 0x23022101, 0x22084608, 0xff7cf7e9, 0xf242220b, 
+    0x46110600, 0xf7ea4630, 0x220cf88d, 0x46114630, 0xf888f7ea, 0x4630220d, 0xf7ea4611, 0x2001f883, 
+    0x1e829400, 0x23000281, 0x0101e9cd, 0x90032103, 0xf7fd4628, 0x2600fa19, 0x0a28f10d, 0xfb069a04, 
+    0x4621f004, 0x0040eb05, 0xf7ff4684, 0x4660fe9c, 0xf7ff4621, 0xf84afe88, 0x1c760026, 0xdbed2e04, 
+    0x94002001, 0x02811e82, 0xe9cd2300, 0x21030101, 0x46289003, 0xf9f8f7fd, 0x9a042600, 0xfb064621, 
+    0xeb05f004, 0x46840040, 0xfe7df7ff, 0x46214660, 0xfe69f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 
+    0xdbea2e04, 0x94002001, 0x02811e82, 0xe9cd2300, 0x21030101, 0x46289003, 0xf9d6f7fd, 0x9a042600, 
+    0xfb064621, 0xeb05f004, 0x46840040, 0xfe5bf7ff, 0x46214660, 0xfe47f7ff, 0x2026f85a, 0xf84a1881, 
+    0x1c761026, 0xdbea2e04, 0x94002001, 0x02811e82, 0xe9cd2300, 0x21030101, 0x46289003, 0xf9b4f7fd, 
+    0x9a042600, 0xfb064621, 0xeb05f004, 0x46840040, 0x0000e00e, 0x00030bf0, 0x0003114c, 0xd1800030, 
+    0x00030350, 0x00030394, 0x00030338, 0x00030366, 0xfe29f7ff, 0x46214660, 0xfe15f7ff, 0x2026f85a, 
+    0xf84a1881, 0x1c761026, 0xdbda2e04, 0xf7ffa805, 0x2000fc82, 0xab054651, 0xf852465a, 0x603e6020, 
+    0x6020f851, 0xf853607e, 0x1c406020, 0x370c60be, 0xdbf22804, 0x21402600, 0xf7f0b270, 0x1c76f818, 
+    0xdbf82e04, 0x0801f108, 0x0f40f1b8, 0x9812da01, 0x2100e66b, 0x1080f44f, 0xf9daf7e9, 0xea409809, 
+    0xea412100, 0xea414100, 0x60386000, 0x2109ea49, 0x4109ea41, 0x6009ea41, 0xb0136078, 0xe92de5cf, 
+    0x250041f0, 0x4700f240, 0x21004efe, 0xf7e94638, 0x4630f9bf, 0xf926f00a, 0x0720b204, 0x48f9d0f5, 
+    0x1c80b2a1, 0xf921f00a, 0x000ff004, 0xd00f2801, 0xd0112802, 0xd0132803, 0xf64f2501, 0xea0470f0, 
+    0x46300100, 0xf911f00a, 0xd0de2d00, 0x81f0e8bd, 0xf7ff4620, 0xe7f0fe04, 0xf7ff4620, 0xe7ecfcfd, 
+    0xf7ff4620, 0xe7e8fb11, 0x4ff8e92d, 0xa398f8df, 0x71fff64f, 0xf00a4650, 0x2100f8f2, 0xf7e92002, 
+    0xf7f2f91f, 0x4ee1fa1a, 0x94002400, 0x21012203, 0x7833200a, 0xfdb8f7fc, 0xfa07f7f2, 0x22002101, 
+    0xf7f94608, 0xf7f8ff31, 0x2101fa16, 0x46082200, 0xff2af7f9, 0x210048d6, 0x68052201, 0x94004608, 
+    0xf7e7462b, 0x2280fdc6, 0x21004628, 0xfc22f7ff, 0x46072201, 0x462b2000, 0x94004611, 0xfdb9f7e7, 
+    0x46282280, 0xf7ff2100, 0x2203fc15, 0x21024681, 0x2000462b, 0xf7e79400, 0x2280fdac, 0x21004628, 
+    0xfc08f7ff, 0x46802203, 0x462b2000, 0x94004611, 0xfd9ff7e7, 0x46282280, 0xf7ff2100, 0x4cbdfbfb, 
+    0x0200f242, 0xda054297, 0xda034591, 0xda014590, 0xdb014290, 0xe0004db8, 0x46504db8, 0xf00a4629, 
+    0x2000f88e, 0xf7e96025, 0xf7e7fd87, 0xf7f2fe7f, 0x4dacf87f, 0x35742400, 0xb2241c64, 0xf91ef7f1, 
+    0xfda2f7f8, 0xfb49f7fc, 0xf249b110, 0xe003010d, 0xddf12c05, 0x31adf640, 0xf00a4628, 0x2101f876, 
+    0x46082200, 0xfec0f7f9, 0xf9f0f7f4, 0xf8bcf7f4, 0xffe4f7f3, 0xf8d4f7f4, 0xff5af7f3, 0xf7e92000, 
+    0x2000fd5b, 0xf850f7fc, 0xb240499d, 0xfde6f7e7, 0xf7fc2001, 0x499af849, 0x3110b240, 0xfddef7e7, 
+    0xf7fc2002, 0x4996f841, 0x3120b240, 0xfdd6f7e7, 0xf7fc2003, 0x4992f839, 0x3130b240, 0xfdcef7e7, 
+    0x823cf8df, 0x24002500, 0x1705eb08, 0x5d384621, 0xb2424240, 0xf7fe4628, 0x1c64f9b4, 0x2c10b2e4, 
+    0x1c6dd3f4, 0x2d04b2ed, 0x2000d3ed, 0xf978f7fe, 0xf7fe2003, 0x2300f9b7, 0x21014882, 0xf00a461a, 
+    0x2100f83e, 0xf7ea4608, 0x4c7ff9d3, 0x0500f241, 0x78214628, 0xf8acf7e9, 0x22002101, 0xf7f94608, 
+    0x2004fe63, 0xffb4f7fd, 0x46287821, 0xf8a0f7e9, 0xf7e92001, 0x7821fd01, 0xf7e901e8, 0x2000f899, 
+    0xfcfaf7e9, 0xf7ea2002, 0x4d70f9d7, 0x22022300, 0x4628210c, 0xf813f00a, 0xb1207830, 0xd0042801, 
+    0xd0022802, 0x2005e004, 0x2006e000, 0xff92f7fd, 0x46282301, 0x029f220a, 0xf00a4639, 0x7821f800, 
+    0xf7e94638, 0x2001f875, 0xfcd6f7e9, 0x01794855, 0xf0093816, 0x7832ffda, 0x20082101, 0xfb8af7ef, 
+    0x485b2300, 0x461a2101, 0xffe9f009, 0xfbcff7ef, 0x20014c58, 0xf7ea7821, 0x4957fb04, 0x78202201, 
+    0x21027008, 0xf0094855, 0xb110ffe8, 0xf7ea2000, 0x7820fae4, 0xfdadf7ea, 0xf7f92004, 0xe8bdfeb6, 
+    0x22014ff8, 0x46104611, 0xbdfef7f9, 0x5ff0e92d, 0x20022100, 0xffd4f7e8, 0x23014842, 0x02592209, 
+    0xf00938a0, 0x2000ffbc, 0xfc96f7e9, 0xfd8ef7e7, 0x483c2301, 0x03dc220f, 0x4621388e, 0xffaff009, 
+    0xf7ea2001, 0x4837f969, 0x38402100, 0xff8df009, 0x23014834, 0x21802207, 0xf00938a0, 0x4e32ffa0, 
+    0x46281165, 0xf7e97831, 0x4f30f813, 0x220f2301, 0x37724621, 0xf0094638, 0x2380ff92, 0x22004638, 
+    0xf0091e69, 0x2306ff8c, 0x21ff2200, 0xf0091cb8, 0x2200ff86, 0x73f8f641, 0x1d38217f, 0xff7ff009, 
+    0x0902f1a7, 0x46484621, 0xff5ff009, 0x0180f248, 0xf0094648, 0x7831ff5a, 0xf7e84628, 0xf44fffe9, 
+    0xf2400800, 0x464711f4, 0xf7e14640, 0x491cfe4a, 0xf7e14638, 0x4815fe35, 0xff44f009, 0x46384601, 
+    0xfe2ef7e1, 0xa044f8df, 0x0a80f10a, 0xf0094650, 0x4601ff39, 0xf7e14638, 0x4912fe23, 0xf7e14638, 
+    0xe021fe1f, 0xd0035136, 0xd1800048, 0x00030394, 0x000301c4, 0x00030288, 0x8421b7ed, 0x84217bde, 
+    0x00030fec, 0xd00304a0, 0x00030223, 0xd0035022, 0xd0036104, 0x00030222, 0x000301dc, 0xd03d104a, 
+    0x90010000, 0xdcba01f5, 0xf0094650, 0x4601ff0b, 0xf00948ab, 0x2300ff0a, 0x220a4629, 0xf0094648, 
+    0x2301ff1e, 0x220a4629, 0xf0094648, 0x2300ff18, 0x220a4629, 0xf0094648, 0x48a2ff12, 0xf246220d, 
+    0xf9900100, 0xb2830000, 0xf0094648, 0x2300ff08, 0x22054648, 0xf0092120, 0x2301ff02, 0x22054648, 
+    0xf0092120, 0xf8dffefc, 0x2700b258, 0x0be6f1ab, 0x220f4621, 0xf0094658, 0xb918ff00, 0xb23f1c7f, 
+    0xdbf542a7, 0xff3bf7fb, 0xf2404682, 0x464711f4, 0xf7e14640, 0x498cfdc6, 0xf7e14638, 0x4658fdb1, 
+    0xfec0f009, 0x46384601, 0xfdaaf7e1, 0x46384651, 0xfda6f7e1, 0x46384985, 0xfda2f7e1, 0xf2402201, 
+    0x2100102b, 0xf907f7ea, 0xf7eb2074, 0x2301f9f3, 0x220f4621, 0xf0094648, 0x4f7dfec2, 0x220b2300, 
+    0x0100f640, 0xf0094638, 0x2300feba, 0x220a4629, 0xf0094638, 0x2300feb4, 0x2100f240, 0x46382209, 
+    0xfeadf009, 0x46382208, 0x01512300, 0xfea7f009, 0x46382303, 0x21c02206, 0xfea1f009, 0xf647486c, 
+    0x23007700, 0x22084639, 0xf0091c80, 0xf8dffe98, 0x230081a0, 0x461a217f, 0x0804f108, 0xf0094640, 
+    0x2300fe8e, 0x22084639, 0xf0094640, 0x2002fe88, 0xf842f7ea, 0x46082100, 0xf808f7ea, 0x78384f5d, 
+    0x2801b120, 0x2802d004, 0xe004d002, 0xe0002005, 0xf7fd2006, 0x4856fdff, 0x220a2301, 0x30084629, 
+    0xfe6df009, 0x46287831, 0xfee2f7e8, 0x4621484c, 0xf009388a, 0x783afe4a, 0x20082101, 0xf9faf7ef, 
+    0x484d2300, 0x461a2101, 0xfe59f009, 0x46287831, 0xfecef7e8, 0xfa3bf7ef, 0x20014d48, 0xf7ea7829, 
+    0x4947f970, 0x78282201, 0x21027008, 0xf0094845, 0xb110fe54, 0xf7ea2000, 0x7828f950, 0xfc19f7ea, 
+    0xe8bd4620, 0x21025ff0, 0x4210f04f, 0xbd67f7e1, 0x4604b570, 0xff90f7e2, 0xf7e92000, 0x4d34ffed, 
+    0x220a2300, 0x4100f240, 0x46283508, 0xfe27f009, 0x20012100, 0xffaaf7e9, 0x20012100, 0xffb8f7e9, 
+    0x46282301, 0x21402206, 0xfe19f009, 0x46282301, 0x21202205, 0xfe13f009, 0x2018492b, 0x60084a21, 
+    0x492a2000, 0x3000f991, 0xf99154d0, 0x20013001, 0xf99154d0, 0x20023002, 0xf99154d0, 0x20031003, 
+    0xf7fc5450, 0x2000f82d, 0xff32f007, 0xb2e02100, 0xfb8af007, 0x461a2300, 0xb2e04619, 0xfd75f007, 
+    0x06ea481b, 0xf0007800, 0x1250010f, 0xd0042901, 0xd0082902, 0xd00c2903, 0x2116e00d, 0xfd0ff7e1, 
+    0xfe14f7ff, 0x2117e007, 0xfd09f7e1, 0xfcbcf7ff, 0xf7ffe001, 0xe8bdfc84, 0x20024070, 0xbdf1f7e8, 
+    0xd00351aa, 0x00030330, 0x90010001, 0xdcba01f5, 0xd003501a, 0x00030394, 0xd0036104, 0x00030222, 
+    0x000301dc, 0xd03d104a, 0x000301cc, 0x00030338, 0x00030285, 0x43f8e92d, 0x46044d4f, 0xb1208e80, 
+    0xd00d287e, 0xd134287f, 0x494be014, 0x32fff04f, 0x1d096828, 0xfe24f005, 0xd1071d01, 0xe027207e, 
+    0x22004945, 0x1d096828, 0xfe1af005, 0xd01e1d41, 0xd1ea2801, 0x1d004840, 0x28298800, 0x483fd1e5, 
+    0x21042202, 0xfd99f009, 0xb2c04b3d, 0x28014f3d, 0xf04f4e3d, 0xf44f58a8, 0xf6400900, 0xf04f0100, 
+    0x4618020b, 0xf009d007, 0xb1e8fd88, 0x207fe038, 0xe8bd86a0, 0xf00983f8, 0x2801fd80, 0xf996d130, 
+    0x28030000, 0x2805d006, 0x2804d004, 0x7838d002, 0xd1252801, 0xf2404642, 0x46481160, 0xfc8ff7e1, 
+    0xf7ea2000, 0xe01bf86a, 0x0000f996, 0xd0062803, 0xd0042805, 0xd0022804, 0x28017838, 0x4642d110, 
+    0x1161f240, 0xf7e14648, 0x2001fc7a, 0xf855f7ea, 0xf6412000, 0x46020300, 0x90004601, 0xf85cf7ec, 
+    0xfeaaf7e2, 0x22024819, 0xf0092104, 0x2201fd46, 0x48174603, 0xf0092102, 0xf996fd32, 0x28030000, 
+    0x2805d003, 0x2804d001, 0xf001d101, 0x4811f90d, 0x28017800, 0xf7e3d18d, 0xe776f89a, 0x21012200, 
+    0xf2afb510, 0xf005102f, 0x2108fbb7, 0xf0052003, 0x4901fd15, 0xbd106008, 0x00030c14, 0xd2054084, 
+    0xd0035026, 0x00030215, 0x000301dc, 0xd0039026, 0xd03c801a, 0x00030279, 0x4ff8e92d, 0x46044d84, 
+    0xf04f8e80, 0x28813aff, 0xd01c686b, 0xb178dc0c, 0xd17d2880, 0x2200497f, 0xf0054618, 0x1d41fd71, 
+    0x2801d00f, 0xe00ed104, 0xd07228e4, 0xd16f28e5, 0x46524978, 0xf0056868, 0x1d01fd63, 0x2080d1ef, 
+    0x2081e0a9, 0x4e73e0a7, 0xf04f46d0, 0x46574220, 0xf9b64640, 0xf7e11000, 0xf996fc02, 0x46381004, 
+    0xf7e14a6d, 0xf9b6fbfc, 0x4f6c0000, 0xd0152826, 0xd1dd2873, 0x0002f996, 0x1000f995, 0xd1054288, 
+    0x1000f997, 0x2001f995, 0xd0d14291, 0x22007028, 0x1003f996, 0xf0077069, 0xe7c9fed0, 0xf0072000, 
+    0x485ffe37, 0x917cf8df, 0x28018800, 0x2000d012, 0xfddef007, 0x1003f996, 0xddb92900, 0x4260f04f, 
+    0xf7e14640, 0xf996fbcc, 0x28040003, 0x2805d066, 0xe074d072, 0xb150f8df, 0x21042202, 0xf0094658, 
+    0x2801fc9c, 0x0801f04f, 0x2204d107, 0xf1ab2110, 0xf0090004, 0x2801fc92, 0x2000d01b, 0xfdb8f007, 
+    0x20032100, 0xfa10f007, 0xf8997933, 0xe0012000, 0xe038e042, 0x20032100, 0xfbf7f007, 0xfddcf7e2, 
+    0x46582201, 0xf8cd2104, 0xf44f8000, 0xf7e83380, 0xf997fd36, 0x21000000, 0xfe27f007, 0x7800483b, 
+    0xd0172801, 0x7800483a, 0xd0132801, 0x46082100, 0xff57f007, 0x48372208, 0xf0090151, 0x70b0fc5e, 
+    0x80302073, 0x492b2200, 0xf0056868, 0x1d01fc9a, 0xe00dd007, 0x20012100, 0xff43f007, 0x8002f886, 
+    0x20e4e7ee, 0x4923e007, 0x46182200, 0xfc89f005, 0xd1821d40, 0x86a020e5, 0x8ff8e8bd, 0x0000f899, 
+    0xd10c2803, 0x20022100, 0xf9bef007, 0x22032300, 0x20044619, 0xe7ffe011, 0x7800481f, 0x7838b180, 
+    0xd1022804, 0x7800481d, 0x78f0b150, 0xf0072100, 0x2200f9ab, 0x78f07933, 0xf0074611, 0xe727fb96, 
+    0x20032100, 0xf9a0f007, 0x20032300, 0x4619461a, 0x2200e7f3, 0xb5102101, 0x2003f2af, 0xfa9cf005, 
+    0x20022108, 0xfbfaf005, 0x60484901, 0x0000bd10, 0x00030c20, 0x0003d1e0, 0xe0000100, 0x00030222, 
+    0x000302e0, 0x00030394, 0xd2054084, 0x00030215, 0x0003021d, 0xd28f2002, 0x000302a7, 0x000302a6, 
+    0x4ff0e92d, 0x9408f8df, 0xb0852001, 0x5298f04f, 0x1000f999, 0xfb03f7e1, 0xf8df48fe, 0x7800a3fc, 
+    0xf8dfb3a0, 0x2206b3f8, 0x46582140, 0xfbd5f009, 0x08fff000, 0x22054658, 0xf0092120, 0x4cf7fbce, 
+    0x2201b2c7, 0x2102343c, 0xf0094620, 0xb2c6fbc6, 0x22004620, 0xf0092101, 0x2208fbc0, 0x4658b2c5, 
+    0xf0090151, 0xb2c4fbba, 0x22074658, 0xf0092180, 0xb2c1fbb4, 0xf89a48ea, 0x78032000, 0xe9cd9702, 
+    0xe9cd8303, 0x462b6200, 0xe00c4622, 0x2201e7ff, 0x1000f89a, 0x46032000, 0x1001e9cd, 0x0203e9cd, 
+    0x46014602, 0xf2489000, 0xf7ef0000, 0x2200fd3c, 0xf7ef4611, 0x210ffd25, 0x1000f889, 0xe8bdb005, 
+    0xf7e34ff0, 0x48d2be75, 0xb570212c, 0x5498f04f, 0x70414622, 0xf7e12001, 0x48d2faa2, 0x28126800, 
+    0x2813d012, 0x2815d013, 0x2816d014, 0x2817d015, 0x2818d016, 0x2811d017, 0x28ffd018, 0x2801d019, 
+    0x2810d01a, 0xe01fd01b, 0x46222120, 0x2121e019, 0xe0164622, 0x46222123, 0x2124e013, 0xe0104622, 
+    0x46222133, 0x2136e00d, 0xe00a4622, 0x4622211f, 0x212fe007, 0xe0044622, 0x46222130, 0x211ee001, 
+    0x20014622, 0xfa6bf7e1, 0xf00948b7, 0x2200fb1b, 0x20014601, 0xfa63f7e1, 0x380a48b0, 0xfb12f009, 
+    0x48ae4604, 0xf009380c, 0x4605fb0d, 0x380e48ab, 0xfb08f009, 0x46294622, 0x4070e8bd, 0xbe35f7e3, 
+    0x5ffce92d, 0x20014ea2, 0x5298f04f, 0x1001f996, 0xfa45f7e1, 0x380a48a1, 0xfaf4f009, 0x489f4607, 
+    0xf009380c, 0xf8dffaef, 0x46058274, 0x080ef1a8, 0xf0094640, 0x4604fae7, 0x4629463a, 0xfe15f7e3, 
+    0xf248220f, 0x46400100, 0xfb07f009, 0x1002f996, 0x08fff000, 0xb254f8df, 0x0a00f04f, 0x9250f8df, 
+    0xd00e2904, 0xd05d2932, 0xf04f2905, 0xd0785298, 0x2001211c, 0xfa13f7e1, 0x0f01f1b8, 0x202bd070, 
+    0x2001e0e6, 0x5298f04f, 0xfa09f7e1, 0xf3c46970, 0x43082141, 0xf5b06170, 0xd01f6f85, 0x42884985, 
+    0x07a8d1ea, 0x2001d000, 0xf3c54983, 0x70080240, 0x0001f005, 0x1000f89b, 0x4a804311, 0x1000f88b, 
+    0x43187813, 0x4a7e7010, 0x4a7e7813, 0xe9cd7812, 0x4a7d2300, 0x3000f899, 0xe03d7812, 0xf3c4497b, 
+    0x4a7b1082, 0x4d7b2804, 0x4b7c4f7b, 0xf881d00c, 0x2100a000, 0xa000f882, 0xa000f885, 0xa000f887, 
+    0xf0094618, 0xe7b7fa82, 0x70082001, 0x0080f3c4, 0xf3c47010, 0x70280040, 0x0001f004, 0x05e07038, 
+    0xe7ed0c01, 0xf04f2001, 0xf7e15298, 0x4620f9b8, 0xf8a0f7f0, 0x7800486a, 0xd19d2801, 0x78014860, 
+    0x78004860, 0x0100e9cd, 0xf899485f, 0xf89b3000, 0x78021000, 0x78004859, 0xf9e6f7f0, 0xe000e78c, 
+    0x2001e075, 0xf99bf7e1, 0x484e69b1, 0xf5a14a5d, 0x3b974358, 0x2310d005, 0x4568f5a1, 0xd0363d6d, 
+    0xf005e03c, 0x23ff0103, 0x141ff361, 0xf3c580b4, 0xf5b1018b, 0xd0046f80, 0x7f60f415, 0x2111d010, 
+    0x2c10e018, 0x2c20d00e, 0xb15cd00c, 0xd00e2c01, 0xd00e2c02, 0xd00f2c03, 0xd00f2c04, 0xd00f2c05, 
+    0xe00f6003, 0x60012112, 0x7030200f, 0x2113e017, 0x2115e000, 0xe0126001, 0xe7fb2116, 0xe0002117, 
+    0x60012118, 0xd00a0b78, 0x70100b78, 0xf3c4e009, 0x29021145, 0x0861d102, 0xd0090709, 0xf8826003, 
+    0x4839a000, 0xb1287800, 0xb1187810, 0xe0022001, 0xe7df2101, 0x49352000, 0xf3c77008, 0x4834010b, 
+    0xf9f3f009, 0x21004832, 0xf0091c80, 0x8b30f9ee, 0x482fb281, 0xf0091d00, 0x69b0f9e8, 0x21ff2200, 
+    0x4307f3c0, 0x1d80482a, 0xf9f9f009, 0x2002e714, 0xe8bd7070, 0xe92d9ffc, 0x4d0d47fc, 0x5a98f04f, 
+    0x46522001, 0x1001f995, 0xf919f7e1, 0x380a480b, 0xf9c8f009, 0x48094604, 0xf009380c, 0xf8dff9c3, 
+    0x4606901c, 0x090ef1a9, 0xf0094648, 0xe031f9bb, 0x00030c28, 0x0003038e, 0x000302ac, 0xd28e0040, 
+    0x000302a8, 0x000301cc, 0xd28fffd0, 0x00030398, 0x00030396, 0x00fa073e, 0x00030391, 0x00030397, 
+    0x0003038a, 0x0003038b, 0x00030395, 0x00030382, 0x00030384, 0x00030385, 0x00030386, 0xd03c8026, 
+    0x0003038f, 0x000302d9, 0x000302d8, 0x000302d7, 0xd003515c, 0x46314622, 0xfcb7f7e3, 0xf248220f, 
+    0x46480100, 0xf9a9f009, 0x08fff000, 0x0100f242, 0x4648220d, 0xf9a1f009, 0xf240b2c7, 0x220071ff, 
+    0xf0094648, 0x2f01f99a, 0xd108b2c0, 0xd0122809, 0x280b2703, 0x2805d03d, 0x2806d050, 0x2129d05a, 
+    0x20014652, 0xf8abf7e1, 0x0f01f1b8, 0x202bd001, 0xe8bd7068, 0x212787fc, 0x20014652, 0xf89ff7e1, 
+    0x50c0f414, 0x2001d000, 0x4eff49fe, 0x70084fff, 0x20c0f3c4, 0x703049fe, 0x3000f3c4, 0xf3c47038, 
+    0x700800c0, 0xea00200e, 0x48fa1154, 0x48fa7001, 0xf93bf009, 0x48fa49f9, 0x78007809, 0x0100e9cd, 
+    0x783148f8, 0x48f87803, 0x78387802, 0xf8bcf7f0, 0x2128e7ca, 0x20014652, 0xf871f7e1, 0x4af3b2e0, 
+    0xea4649f3, 0x61284000, 0xd1024290, 0x2000f3c4, 0x2000e000, 0x20327008, 0xe015706f, 0x46522125, 
+    0xf7e12001, 0x0370f85c, 0x0084ea40, 0x20046168, 0xe009706f, 0x46522126, 0xf7e12001, 0xea44f850, 
+    0x61a820c6, 0x706f2005, 0xe79d70a8, 0x43f8e92d, 0xf04f4ce0, 0x20015898, 0xf9944642, 0xf7e11001, 
+    0x4fddf83e, 0xf0094638, 0x2200f8ed, 0x46014606, 0xf7e12001, 0x220cf834, 0x0100f241, 0xf0094638, 
+    0x2500f90c, 0xf7efb130, 0x200dfe91, 0x20027020, 0xe0167060, 0xf248220f, 0x46380100, 0xf8fdf009, 
+    0x2011b128, 0x20067020, 0x70e57060, 0x202de009, 0x202b7020, 0xb9267060, 0x4642212e, 0xf7e12001, 
+    0x48c6f80e, 0x70052105, 0xf7fb200e, 0x2300fead, 0x22019500, 0x46184619, 0xfd86f7fb, 0x200149c0, 
+    0x70082200, 0x49bf2004, 0xf910f7e8, 0x43f8e8bd, 0xf7e8200b, 0x49b7b9ec, 0x30fff04f, 0x70084aba, 
+    0x70887048, 0x61882000, 0x61086148, 0x60112110, 0x700849b6, 0x700849b6, 0x700849b6, 0x700849b6, 
+    0x700849b6, 0x700849a2, 0x700849b5, 0x700849a3, 0x700849a3, 0x700849a6, 0x700849b2, 0x70084999, 
+    0x700849a0, 0x700849a0, 0x70084998, 0x70084996, 0x700849ad, 0x700849ad, 0x700849ad, 0x700849ad, 
+    0xb57c4770, 0xffc7f7ff, 0x210848ab, 0xf86df009, 0xf7e32001, 0x48a9fa39, 0x0500f241, 0x341a4c96, 
+    0xf5b28802, 0xd0087fac, 0x7fa4f5b2, 0xf5b2d005, 0xd0027fb4, 0x7fbcf5b2, 0x2300d105, 0x220c4629, 
+    0xf0094620, 0x2300f86c, 0x22024620, 0xf0092104, 0x4889f866, 0x21012300, 0x3052461a, 0xf85ff009, 
+    0xfdf4f7ef, 0x90002000, 0x46024603, 0x90014601, 0xffcaf7ef, 0x21004892, 0xf837f009, 0x21004876, 
+    0xf009304a, 0x4874f832, 0x304c2100, 0xf82df009, 0x21004871, 0xf009304e, 0x486ff828, 0x21ff2300, 
+    0x3050461a, 0xf83bf009, 0xf7e82001, 0x2011f960, 0xf95df7e8, 0xf7e82012, 0x2002f95a, 0xfb3bf7ef, 
+    0x22024880, 0xf0092104, 0x2401f838, 0xd1092801, 0x2201486b, 0x7004496b, 0xf7e82004, 0x200bf867, 
+    0xf945f7e8, 0x201b4978, 0x220c2300, 0x46297008, 0x70444860, 0x1d804873, 0xf811f009, 0x2102b002, 
+    0xe8bd2001, 0xf04f4070, 0xf7e04270, 0xe92dbf38, 0x4c585ff0, 0x8e804605, 0x0901f04f, 0x28f0b130, 
+    0x28f1d014, 0xf8c4d134, 0xe01a900c, 0xff33f7ff, 0xf04f4950, 0x68a032ff, 0xf005311c, 0x60e0f871, 
+    0xd0011d00, 0xe00868e0, 0xe02020f0, 0x22004949, 0x311c68a0, 0xf864f005, 0x1d4160e0, 0x2801d016, 
+    0x4f44d1e6, 0x4620f04f, 0x46322001, 0xf9b7371c, 0xf7e01000, 0xf9b7ff04, 0x293a1000, 0x293bd00a, 
+    0x2001d00b, 0xf7e04632, 0xe7d1fefa, 0x86a820f1, 0x9ff0e8bd, 0xff35f7ff, 0x484ce7ca, 0x28017800, 
+    0xf884d101, 0xf9949001, 0x28010001, 0x2802d008, 0x2803d009, 0x2806d00a, 0x2807d00b, 0xe00dd00c, 
+    0xfe94f7ff, 0xf7ffe00a, 0xe007fdb6, 0xfc88f7ff, 0xf000e004, 0xe001fa02, 0xf9c8f000, 0x282b7860, 
+    0xf7ffd101, 0xf994fc20, 0xf04f1000, 0x290d5b98, 0x290ed070, 0x2931d06f, 0x2934d06e, 0x0605f24a, 
+    0x2935d06b, 0xf8dfd06a, 0x290fa070, 0x0a06f10a, 0x262dd07e, 0xd07c2910, 0x80b4f8df, 0xf2422919, 
+    0xd0770701, 0xd076291a, 0xd0752911, 0xd0742912, 0xd0732913, 0xd1a8292d, 0x465a2001, 0xfe9ff7e0, 
+    0xe04c2100, 0x00030393, 0x00030398, 0x00030397, 0x0003038c, 0x00030256, 0xd0035112, 0x0003038a, 
+    0x0003038b, 0x00030396, 0x00030395, 0x002901d4, 0x0003038f, 0x00030c28, 0xd28e0026, 0x00030306, 
+    0x0003038d, 0x684ee180, 0x000301cc, 0x00030384, 0x00030385, 0x00030386, 0x00030382, 0x00030388, 
+    0x00030389, 0x00030391, 0x000303a6, 0x000302d7, 0x000302d9, 0x000302da, 0xd28f228a, 0x00030318, 
+    0xd28f0076, 0xd0039026, 0x000301dd, 0x0003021e, 0xd28fffce, 0xe03de032, 0xe050e04e, 0x04f8e05c, 
+    0xff96f7e7, 0xf10a2100, 0xf0080002, 0x2100fefe, 0x0004f10a, 0xfef9f008, 0x46504639, 0xfef5f008, 
+    0x46404639, 0xfef1f008, 0x282d7820, 0xe006d193, 0xe06ce05d, 0xe0a6e089, 0xe0c9e0c7, 0x7860e0d6, 
+    0xd188282c, 0x200049c8, 0x7008465a, 0x2001211d, 0xfe25f7e0, 0xf7e32002, 0xe6f9f8a7, 0x465a2001, 
+    0xfe1df7e0, 0xf24a2200, 0x46110009, 0xf888f7ef, 0xe00f2034, 0x465a2001, 0xfe11f7e0, 0x212948bb, 
+    0xea417800, 0xf2402200, 0xf24a11d4, 0xf7ef000b, 0x2031f877, 0xe04e7020, 0xfaf2f7ff, 0x2001e7c4, 
+    0xf7e0465a, 0xf240fdfc, 0xf24012cf, 0x463071d0, 0xf866f7ef, 0xe7ed2035, 0x465a2001, 0xfdeff7e0, 
+    0x20194fab, 0x70202207, 0x46382180, 0xfec5f008, 0x46062208, 0x01514638, 0xfebff008, 0x0040ea46, 
+    0xf248b281, 0x22004000, 0xf84af7ef, 0x2001e023, 0xf7e0465a, 0x4631fdd4, 0xf0084650, 0x2100fe86, 
+    0x120af240, 0xf7ef4630, 0x2010f83b, 0x2001e7c2, 0xf7e0465a, 0x4897fdc4, 0x0200f04f, 0x46114f96, 
+    0x28017800, 0x2000d00a, 0xf82af7ef, 0x46382100, 0xfe6bf008, 0xf7e37026, 0xe775f97b, 0x1006f240, 
+    0xf81ef7ef, 0x3100f248, 0x2001e7f1, 0xf7e0465a, 0x7860fda6, 0xd103282c, 0x68004888, 0xd0072801, 
+    0xf24a2297, 0x211b0006, 0xf80af7ef, 0xe791201a, 0x46382200, 0xf7ef4611, 0x4639f803, 0xf0084640, 
+    0x7026fe44, 0x2001e753, 0xf7e0465a, 0x487cfd88, 0xf2412105, 0x88000700, 0x707ef400, 0x0040eb01, 
+    0x4600f440, 0x1f804874, 0xfe2cf008, 0x020bf3c0, 0xf64f4874, 0x780071ff, 0x3040ea01, 0x43024639, 
+    0xf7ee4630, 0x200effdd, 0xf000e764, 0xe72bf835, 0x465a2001, 0xfd63f7e0, 0x010af24a, 0x46404646, 
+    0xfe13f008, 0x70202013, 0xe00f4630, 0x465a2001, 0xfd55f7e0, 0x3038485e, 0xfe04f008, 0x010ef000, 
+    0x46404647, 0xfe01f008, 0x70264638, 0xfdfaf008, 0x46012200, 0xf7e02001, 0xe705fd42, 0x21012200, 
+    0xf2afb510, 0xf00430f5, 0x2108fca7, 0xf0042004, 0x4955fe05, 0xbd106088, 0x4c53b570, 0xf04f2001, 
+    0xf9945298, 0xf7e01000, 0x78e2fd2a, 0xb1324d4f, 0xf2482a01, 0xd0040100, 0xd0062a02, 0xf24ae00a, 
+    0x46280108, 0xfdd1f008, 0x4628e004, 0xfdcdf008, 0x70202012, 0xf0084628, 0x2200fdc5, 0x20014601, 
+    0xfd0df7e0, 0x1c4078e0, 0xbd7070e0, 0x41f0e92d, 0xf04f4c3d, 0x20015698, 0xf9944632, 0xf7e01001, 
+    0x4f3afcfe, 0xf248220f, 0x1cbf0100, 0xf0084638, 0x2200fdd4, 0xf2404605, 0x463871ff, 0xfdcdf008, 
+    0x46384680, 0xfd9ef008, 0x46012200, 0xf7e02001, 0xf994fce6, 0x29081002, 0x2001d109, 0xf7e04632, 
+    0x482bfcde, 0xf0084641, 0x2006fd90, 0x2d007060, 0x202bd101, 0xe8bd7060, 0xe92d81f0, 0x4c2241f0, 
+    0xf04f2001, 0xf9945298, 0xf7e01001, 0x4f1ffcc8, 0xf248220f, 0x1cbf0100, 0xf0084638, 0x220dfd9e, 
+    0xf2424680, 0x46380100, 0xfd97f008, 0x46062200, 0x71fff240, 0xf0084638, 0x4605fd90, 0xf0084638, 
+    0x2200fd61, 0x20014601, 0xfca9f7e0, 0xd1052e01, 0xd1032d0a, 0x70a02008, 0x70602007, 0x0f00f1b8, 
+    0x202bd1c9, 0xe7c67060, 0x000301dd, 0x0003038e, 0xd28e0040, 0x00030381, 0xd03c8024, 0x000301cc, 
+    0x00030318, 0x000302d8, 0x00030c28, 0xd28fffce, 0xd0035112, 0x41f0e92d, 0x255c4847, 0xfd32f008, 
+    0x48454604, 0xf0081e80, 0x4e44fd2d, 0x717ff404, 0xf2454a43, 0x80311744, 0x0103f004, 0xf5a08011, 
+    0x3902412e, 0x0403f024, 0xf5a4d115, 0x384040a2, 0x3808d024, 0x42bcd022, 0x3808d020, 0x3808d01e, 
+    0x3818d01c, 0x1f00d01a, 0x3014d018, 0x3808d016, 0x3810d014, 0x2000d012, 0x4832b190, 0xf2402208, 
+    0xf0083100, 0x4930fd2a, 0x7008b240, 0xf5b18831, 0xd00e7fa8, 0x7facf5b1, 0xe013d00b, 0xe7eb2001, 
+    0xfbe6f7f9, 0xf64b4827, 0x308031b0, 0xfcedf008, 0x07c0e7fe, 0xbf30d001, 0x4824e004, 0x0100f640, 
+    0xfc88f7e6, 0x22004e21, 0x36082101, 0xf0084630, 0x2801fd04, 0x2301d105, 0x22044630, 0xf0082110, 
+    0x481afcee, 0x71fff64f, 0xf0083010, 0x2301fcce, 0x22024630, 0xf0082104, 0x2301fce2, 0x21024630, 
+    0xf008461a, 0x4912fcdc, 0x60086828, 0x5141f243, 0x3818480c, 0xfcb9f008, 0xf242480a, 0x381a0181, 
+    0xfcb3f008, 0xfa6df7f9, 0xd10242bc, 0x20014909, 0xe8bd7008, 0x000081f0, 0xd0020006, 0x00030318, 
+    0x0003031a, 0xd03c8038, 0x000301c8, 0xd03c8310, 0x00030314, 0x00030302, 0x4d1eb570, 0x8e804604, 
+    0x285eb120, 0x285fd00d, 0xe014d125, 0xf04f4919, 0x682832ff, 0xf0041d09, 0x1d01fd23, 0x205ed107, 
+    0x4914e018, 0x68282200, 0xf0041d09, 0x1d41fd19, 0x2801d00f, 0x4e0fd1ea, 0x88301d36, 0xd1e52862, 
+    0x2102480d, 0xfc71f008, 0x0002f9b6, 0xfbf9f7e0, 0x205fe7dc, 0xbd7086a0, 0x21012200, 0xf2afb510, 
+    0xf0040067, 0x2108fb19, 0xf0042003, 0x4901fc77, 0xbd106008, 0x00030c4c, 0xd03c806e, 0x41f0e92d, 
+    0x22014dff, 0x46282106, 0xfc77f008, 0x1cb74efd, 0xb3201eb4, 0x46282201, 0xf0082106, 0x2801fc6e, 
+    0x2201d020, 0x21064628, 0xfc67f008, 0xd1252802, 0x0100f243, 0xf0084630, 0x219cfc38, 0xf0084638, 
+    0x2301fc34, 0x22004620, 0xf008210f, 0x4620fc48, 0x41f0e8bd, 0x22042301, 0xf0082110, 0xf240bc40, 
+    0xe7e71100, 0x7507f240, 0x46294630, 0xfc1df008, 0x46384629, 0xfc19f008, 0xe7e3230f, 0x81f0e8bd, 
+    0x4604b510, 0xffbaf7ff, 0x20012100, 0xfdaef7e8, 0xb2a348dc, 0x21012200, 0xf0083824, 0xe8bdfc20, 
+    0x20034010, 0xbdd8f7e8, 0x2000b51f, 0x90019000, 0x90039002, 0xf7e94668, 0x9800fbe2, 0x48d2b281, 
+    0xfbf3f008, 0x0c019800, 0x1c8048cf, 0xfbedf008, 0xb2819801, 0x1d0048cc, 0xfbe7f008, 0x0c019801, 
+    0x1d8048c9, 0xfbe1f008, 0xb2819802, 0x300848c6, 0xfbdbf008, 0x0c019802, 0x300a48c3, 0xfbd5f008, 
+    0xb2819803, 0x300c48c0, 0xfbcff008, 0x0c019803, 0x300e48bd, 0xfbc9f008, 0xb570bd1f, 0x20014cbb, 
+    0x52a0f04f, 0x1103f240, 0x70e00605, 0xf7e04628, 0xf240fb06, 0x462811f4, 0xfab3f7e0, 0x61eef64e, 
+    0xf7e04628, 0x49b2fa9d, 0xf7e04628, 0x2300fa99, 0x210148b0, 0xf008461a, 0x49affbc2, 0x4aaf2000, 
+    0x13697008, 0x1c407f20, 0x0007f000, 0x1000eb00, 0x0080eb02, 0x20026081, 0xfceaf7e7, 0x4070e8bd, 
+    0xf7e72003, 0xe92dbce5, 0x469b4ff0, 0x0a00f04f, 0xa000f8c2, 0x2300f240, 0x46894690, 0x3000f8ab, 
+    0x0c81f04f, 0x46569a09, 0xa000f8a2, 0xe02c2500, 0x0e05eb06, 0x0f02f1be, 0xeb00d404, 0xf851018e, 
+    0xe0007c08, 0x46522700, 0xf04f4654, 0x18e933ff, 0x4561d406, 0xeb0eda04, 0xf8500103, 0xe0001021, 
+    0x428f2100, 0x4614da03, 0x460f463a, 0x428ae007, 0x4614da02, 0xe002460a, 0xda00428c, 0x1c5b460c, 
+    0xdbe42b03, 0xf8491c6d, 0x4565402e, 0x2300dbd0, 0x18f1e01f, 0x5000f8d8, 0x4021f850, 0x1021f859, 
+    0x17ca1a61, 0xeb7a1a6d, 0xda110402, 0xda012a00, 0xe0072100, 0x4580f04f, 0x1a6d2400, 0xda014194, 
+    0x5100f04f, 0x1000f8c8, 0x3000f8ab, 0x800e9909, 0x45631c5b, 0x4466dbdd, 0x0f8cebb6, 0xe8bddba6, 
+    0xe92d8ff0, 0x240043f8, 0x461d460f, 0x94004616, 0x52a0f04f, 0x8020f8dd, 0x1000f9b0, 0x7080f04f, 
+    0xfa5df7e0, 0x70044866, 0x70c44860, 0x48657104, 0xb1786800, 0x78004864, 0xd0082801, 0x485d2100, 
+    0x3102f201, 0xf0083008, 0xe8bdfb00, 0xf24283f8, 0xe7f47110, 0xf04f703c, 0x603030ff, 0x0000f8c8, 
+    0x48510c01, 0x1f80602c, 0xfaeff008, 0x22084c4e, 0x3c1c2300, 0x46200151, 0xfb01f008, 0xf44f4d4a, 
+    0x4f520100, 0x91003538, 0xe00c138e, 0x462a2104, 0xf7e74668, 0x2801fbe7, 0x2301d00c, 0x22094631, 
+    0xf0084620, 0x2206faec, 0x21404638, 0xfaf5f008, 0xd1eb2800, 0x2300483b, 0x21102204, 0xf0081e80, 
+    0xe7c2fade, 0x4ff8e92d, 0x460e2500, 0x46904699, 0xab0ae9dd, 0xf04f9500, 0xf9b052a0, 0xf04f1000, 
+    0xf7e07080, 0x483af9fc, 0x60054c30, 0x70054839, 0x0005f994, 0xd1121c40, 0xc0dcf8df, 0xf8df2100, 
+    0x2000e0dc, 0x1701eb0c, 0x1201eb0e, 0x54135c3b, 0x28101c40, 0x1c49dbfa, 0xdbf22904, 0x48287165, 
+    0x70e57005, 0xf8c87125, 0xf8c95000, 0xf8ca5000, 0xf8cb5000, 0x79605000, 0xd17d2800, 0x28007860, 
+    0xf994d07b, 0x70300002, 0xd0752800, 0xf44f4d16, 0x4e150000, 0x2800f240, 0x4f1c3d1c, 0x90003638, 
+    0x2105e00c, 0x46684632, 0xfb7cf7e7, 0xd00c2801, 0x46412301, 0x46282209, 0xfa81f008, 0x46382206, 
+    0xf0082140, 0x2800fa8a, 0x4806d1eb, 0x36fff240, 0x46312301, 0x30302200, 0xfa71f008, 0xe01f230f, 
+    0xd0020126, 0xd0035252, 0xd0035142, 0x00030c58, 0xdcba01f5, 0xd03c80b0, 0x00030266, 0x00037aec, 
+    0x00030265, 0x00047f70, 0x0003031c, 0xd003502c, 0x00030378, 0x0003037c, 0x0003315c, 0x0003d1ec, 
+    0x220048ff, 0xf0084631, 0x88e0fa4a, 0x2002bb08, 0xfb6df7e7, 0x46282208, 0x01512301, 0xfa3ff008, 
+    0x20402100, 0xfab4f7e7, 0xf7e72003, 0x2100fb60, 0xf7e72040, 0x2100faad, 0xf7e92008, 0x2001fd6d, 
+    0xfdbbf7e9, 0x230048ee, 0x21102204, 0xf0083830, 0x2207fa26, 0xe0012101, 0xe036e032, 0xf7e94608, 
+    0x48e8fd1e, 0xf008218c, 0x48e5fa00, 0x220023ff, 0x38164631, 0xfa13f008, 0x233f48e1, 0xf2402200, 
+    0x1e8011ff, 0xfa0bf008, 0x780048df, 0xd0192801, 0x6120f644, 0x880048dd, 0x0240eb00, 0x10c0ebc2, 
+    0x00c0eb01, 0x44088ba1, 0x707af5a0, 0x48d5b281, 0xf0083014, 0x8ba0f9da, 0x48d5b281, 0xf9d5f008, 
+    0x8ff8e8bd, 0x5130f247, 0x2141e7e4, 0xf04f7035, 0xf04f52a0, 0xf7e07080, 0xe7f1f912, 0x4fffe92d, 
+    0x4607b083, 0xf04f2005, 0xf7e70b00, 0x4cc9fa09, 0x48c960e0, 0x28017800, 0x2802d037, 0x48c7d035, 
+    0xf9b0f008, 0x48c54605, 0xf0081c80, 0xea45f9ab, 0x61604000, 0x70e02000, 0x46806360, 0x21009000, 
+    0x4000f240, 0xfa34f7e7, 0x780048bd, 0x4cb9b328, 0xf04f2000, 0xf2407580, 0x70e011f4, 0xf7e04628, 
+    0x49b8f890, 0xf7e04628, 0x49b7f87b, 0xf7e04628, 0x7f20f877, 0xf0001c40, 0xeb000007, 0x48b31100, 
+    0x0081eb00, 0x31106881, 0x48ace184, 0xf0081f00, 0x4605f979, 0x1e8048a9, 0x2005e7c7, 0xf9c0f7e7, 
+    0x61204ca4, 0x780048a4, 0xd0132801, 0xd0112802, 0xf00848a2, 0x4605f967, 0x1c8048a0, 0xf962f008, 
+    0x4000ea45, 0xe9d461a0, 0x42810103, 0x1a41d90a, 0xe0081c09, 0x1f004899, 0xf954f008, 0x48974605, 
+    0xe7eb1e80, 0x4a9a1a41, 0x0004f04f, 0x0a14f04f, 0x091ef04f, 0x2000f992, 0xd0022a05, 0xd0052a04, 
+    0x2005e009, 0x0a0ff04f, 0xe0032214, 0xf04f2006, 0x220f0a0a, 0x40c14691, 0x91014886, 0x0105e9d0, 
+    0xd2024281, 0x1c241a0c, 0x1a0ce000, 0x3f80f5b4, 0xf5a4d301, 0x98013480, 0xf00a44a0, 0x4605f9d1, 
+    0x4620460e, 0xf9ccf00a, 0x22004b82, 0xfa18f00a, 0x4633462a, 0xfff8f009, 0x487f4605, 0xe9d0460e, 
+    0x46282300, 0xfb0af00a, 0x6b414872, 0x1c49d20d, 0x487a6341, 0xe9d04631, 0x46282300, 0xfafef00a, 
+    0x486cd207, 0x1c496b41, 0x2900e002, 0x2100da01, 0x48686341, 0x6b404659, 0xdd004583, 0x46834608, 
+    0x45d0b127, 0x4963d302, 0x6348200b, 0xd0041c78, 0xd30245c8, 0x200b495f, 0x46316348, 0xe9d04867, 
+    0x46282300, 0xfadaf00a, 0x485ad303, 0x290a6b41, 0xf8dfdd7e, 0x21019160, 0x0000f999, 0xd0082802, 
+    0xd0062803, 0x4850b3a7, 0x1003f889, 0xb3807800, 0xb36fe03b, 0xf04f9805, 0x70017a80, 0x11f4f240, 
+    0xf7df4650, 0xf64affbe, 0x465041ca, 0xffa8f7df, 0x46504641, 0xffa4f7df, 0x22004b51, 0x46314628, 
+    0xf9aef00a, 0xf918f00a, 0x46504601, 0xff98f7df, 0x1034f8d9, 0xf7df4650, 0x9805ff93, 0x1000f990, 
+    0xf7df4650, 0x4940ff8d, 0xf7df4650, 0xe00cff89, 0xe7ffe009, 0x3000f44f, 0x0103f640, 0xff91f7df, 
+    0xfd5ff7ed, 0x9806e001, 0xf04f7001, 0xf2407a80, 0x46501bf4, 0xf7df4659, 0xf64aff84, 0x183920aa, 
+    0xf7df4650, 0x9805ff6d, 0x1000f990, 0xf7df4650, 0x9806ff67, 0x1000f990, 0xf7df4650, 0x4831ff61, 
+    0xf870f008, 0x46504601, 0xff5af7df, 0x4631482b, 0x2300e9d0, 0xf00a4628, 0xd208fa61, 0x46544621, 
+    0xf7df4650, 0x9901ff4d, 0xf7df4620, 0xe000ff49, 0xf8d9e087, 0x464c1010, 0x46504655, 0xff40f7df, 
+    0x462868e1, 0xff3cf7df, 0x46284e17, 0xf7df4631, 0xf242ff37, 0x064801c0, 0xff4ff7df, 0x78004810, 
+    0x2100b168, 0xb13f70e1, 0x0000f994, 0xd0012802, 0xd1012803, 0x70019805, 0x46284659, 0xe041e024, 
+    0xd0035280, 0xd03c80a4, 0x0003031c, 0x00047f78, 0xd003513e, 0x00030c58, 0x00030394, 0xd0036116, 
+    0x00030265, 0x0bbbdead, 0xdcba01f5, 0x00037aec, 0x00030222, 0x40140000, 0x00030268, 0x00030270, 
+    0x40c38800, 0xd003502c, 0xff0bf7df, 0x21bbf64a, 0xf7df4628, 0x4631fef5, 0xf7df4628, 0x7f20fef1, 
+    0xf0001c40, 0xeb000007, 0x48fd1100, 0x0081eb00, 0x31206881, 0x49fb6081, 0x60089804, 0x0003f994, 
+    0xe4ccb007, 0x0000f994, 0xd0042802, 0xd0022803, 0xf7e72003, 0x4659f93d, 0xf7df4628, 0xf64bfee2, 
+    0x462831bb, 0xfeccf7df, 0x46284641, 0xfec8f7df, 0x46286b61, 0xfec4f7df, 0x46284631, 0xfec0f7df, 
+    0x6981e009, 0x69016141, 0x980060c1, 0x90001c40, 0xf4ff2832, 0xb1c7ae24, 0x7480f04f, 0x11f4f240, 
+    0xf7df4620, 0xf64bfebe, 0x462031bd, 0xfea8f7df, 0x46204641, 0xfea4f7df, 0x462049db, 0xf7df6b49, 
+    0x49dafe9f, 0xf7df4620, 0x48d7fe9b, 0x0003f990, 0xe92de7b6, 0x4cd34ffe, 0x0a00f04f, 0x52a0f04f, 
+    0xf88d4680, 0xf88da000, 0xf9b0a004, 0xf04f1000, 0x68267080, 0xfee3f7df, 0x78e84dcb, 0x2000b120, 
+    0xa030f8c5, 0x8ffee8bd, 0x20016821, 0xf42146a3, 0x602121c0, 0xf7e76328, 0x9002fca5, 0xf7e72000, 
+    0x2000fc7b, 0xab01466a, 0xf7ff4631, 0x2002fdb7, 0x48bf6328, 0xb1907800, 0x7480f04f, 0x11f4f240, 
+    0xf8c54620, 0xf7dfa030, 0xf64ffe6c, 0x462071ff, 0xfe56f7df, 0x462049b5, 0xfe52f7df, 0x2003e19d, 
+    0x20966328, 0xf89d62e8, 0x28000004, 0x2005d07e, 0x78286328, 0xd07a2800, 0xf04f2006, 0xab01090a, 
+    0x4631466a, 0x20016328, 0xfd88f7ff, 0x780048a8, 0xf8c5b110, 0xe180a030, 0x63282007, 0xf99048a5, 
+    0x28050000, 0x2804d002, 0x2003d101, 0xf89d4681, 0x28000000, 0xf04fd07e, 0xf2407480, 0x462011f4, 
+    0xfe2ff7df, 0x0176f649, 0xf7df4620, 0x4997fe19, 0xf7df4620, 0x2400fe15, 0x4897e07e, 0x28017800, 
+    0x2802d014, 0x4895d012, 0xff1cf007, 0x48934607, 0xf0071c80, 0xea47ff17, 0x61a84000, 0x1a416969, 
+    0xd3134549, 0x7800488e, 0xe00fb140, 0x1f00488b, 0xff08f007, 0x48894607, 0xe7ea1e80, 0x3000f44f, 
+    0x0103f640, 0xfdfdf7df, 0xfbcbf7ed, 0x1f406ae8, 0xd3174284, 0x7780f04f, 0x11f4f240, 0xf7df4638, 
+    0xf246fdf0, 0x46387189, 0xfddaf7df, 0x46384621, 0xfdd6f7df, 0x463869a9, 0xfdd2f7df, 0x46384973, 
+    0xfdcef7df, 0x1e406ae8, 0xe0014284, 0xe059e057, 0x2001d101, 0x210070e8, 0x4000f240, 0xff68f7e6, 
+    0x7800486b, 0xf04fb328, 0xf8857780, 0x4654a003, 0x11f4f240, 0xf88d4638, 0xf7dfa000, 0x4969fdc2, 
+    0xf7df4638, 0x4961fdad, 0xf7df4638, 0x7f28fda9, 0xe0001c40, 0xf000e017, 0xeb000007, 0x48581100, 
+    0x0081eb00, 0x31306881, 0xf8cb6081, 0x632c6000, 0x69a8e0e3, 0x61681c64, 0x42846ae8, 0xaf7df4ff, 
+    0xf7e62003, 0x78e8fff5, 0xf04fb1e0, 0xf2407480, 0x462011f4, 0xfd95f7df, 0x41ccf64c, 0xf7df4620, 
+    0x494afd7f, 0xf7df4620, 0x7828fd7b, 0x2143b118, 0x1000f8a8, 0x2009e006, 0x0000f8a8, 0x9802e002, 
+    0xfb7af7e7, 0x63282008, 0x280078e8, 0x7828d177, 0xd0742800, 0xf7e79802, 0x4841fb6f, 0xb9087800, 
+    0xfceef7ed, 0x46572002, 0xa004f885, 0xffaff7e6, 0x90f4f8df, 0x200a2208, 0x23016328, 0x01514648, 
+    0xfe7df007, 0x63282009, 0x0400f44f, 0x1e64e012, 0xdc092c00, 0x46204c35, 0xfe4ef007, 0x0140f040, 
+    0xf0074620, 0xe00dfe4c, 0x46482301, 0x02592209, 0xfe65f007, 0x2206482c, 0x38fa2140, 0xfe6df007, 
+    0xd1e42800, 0xf007482a, 0xb204fe3d, 0x0101f004, 0xf0041e49, 0x43080002, 0x2001d072, 0x200270e8, 
+    0xff86f7e6, 0x7980f04f, 0x11f4f240, 0xf7df4648, 0x4920fd28, 0xf7df4648, 0x481bfd13, 0xf00738fa, 
+    0xea40fe21, 0x46484104, 0xfd0af7df, 0x4648490f, 0xfd06f7df, 0x7800480e, 0xf240b380, 0x464c11f4, 
+    0x70ef4648, 0xfd0df7df, 0x46204913, 0xfcf8f7df, 0x46204906, 0xfcf4f7df, 0x1c407f28, 0xe03fe01f, 
+    0x00037aec, 0x00047ffc, 0x00030c58, 0xdcba01f5, 0x00030265, 0x00030222, 0x00030394, 0xd0036116, 
+    0x0003031c, 0x0ddddead, 0xd0035126, 0xc300006c, 0xd0060040, 0x00011104, 0x0eeedead, 0xf000e00a, 
+    0xeb000007, 0x48fe1100, 0x0081eb00, 0x31306881, 0xe00f6081, 0xb19878e8, 0xb1187828, 0xf8a82043, 
+    0xe0020000, 0xf8a82109, 0x200b1000, 0xff20f7e6, 0x700748f4, 0x6000f8cb, 0xf995632f, 0xe6310003, 
+    0x6000f8cb, 0xe92de675, 0x4def5ffc, 0x49dff240, 0x46044eee, 0xf2408e81, 0xf8df4bcc, 0xf240a3b4, 
+    0x6bab48be, 0x68374549, 0x40dff2a1, 0xdc2ed06a, 0xf2a14559, 0xd07140cc, 0x4541dc12, 0x40bef2a1, 
+    0xdc06d06d, 0xf110b311, 0xd06b0132, 0xd1682901, 0x2801e072, 0x2808d056, 0x2809d07e, 0xe051d161, 
+    0xd07a280c, 0x2801dc06, 0x2806d04c, 0x2807d076, 0xe047d157, 0xd045280d, 0xd1522812, 0x220049d2, 
+    0x313c4638, 0xfdedf003, 0xd0681d40, 0x2818e03a, 0xdc20d038, 0xd035280c, 0x2805dc0e, 0x2806d07e, 
+    0x280bd030, 0x49c8d13d, 0x46382200, 0xf003313c, 0x1d40fdd8, 0xe025d073, 0xd0712811, 0xd0212812, 
+    0xd12e2817, 0x220049c0, 0x313c4638, 0xfdc9f003, 0xd0661d40, 0x2826e016, 0xdc0fd014, 0xd075281d, 
+    0xd00f281e, 0xd11c2825, 0x220049b7, 0x0000f8da, 0xf003313c, 0x1d40fdb6, 0xe003d069, 0xd0672829, 
+    0xd10e282a, 0xf04f49b0, 0x6ba832ff, 0xf003313c, 0x1d01fdd7, 0xf240d10c, 0xe1df408c, 0xe09de0de, 
+    0xe08fe000, 0x220049a8, 0x313c4618, 0xfdc8f003, 0xd03e1d41, 0xd1e52801, 0x373c4fa3, 0x0114f1a7, 
+    0x0000f9b7, 0xd037280f, 0xd042283f, 0xd07b2843, 0xd07a2844, 0xe0032845, 0xe0fce0a1, 0xe117e0db, 
+    0x2846d074, 0x2848d073, 0x2849d072, 0x284ad071, 0x284cd070, 0x284dd06f, 0x2847d06e, 0x283ed06d, 
+    0xf995d1c0, 0x46381000, 0xfd53f7ff, 0xd0b92800, 0xf04f8838, 0x46390200, 0xe0032809, 0xe137e11e, 
+    0xe165e14c, 0x6ba8d079, 0xfd5bf003, 0xd0751d01, 0xf240e190, 0xe191408d, 0x91004b83, 0x33244982, 
+    0xf1011f1a, 0xf7ff003c, 0xe79bf9bc, 0xe176e163, 0x497de17b, 0x1f083118, 0xe9cd1f03, 0x1f1a0100, 
+    0x30283918, 0xfa0ef7ff, 0xb92088e8, 0xf7e62002, 0x2800fe30, 0x4977d186, 0x28007808, 0x8928d182, 
+    0x81281c40, 0x70082001, 0x80382043, 0x0000f995, 0xd0012802, 0xd10b2803, 0x1c408968, 0x486e8168, 
+    0xf2487801, 0xf7e60000, 0x2000fd43, 0xf898f7ff, 0x22004965, 0x313c6ba8, 0xfd13f003, 0xd1131d01, 
+    0x8034f8a4, 0x9ffce8bd, 0xe033e013, 0xe06de051, 0xe0a0e08c, 0xe0dee0cc, 0xe10ce0fa, 0x2200495a, 
+    0x313c4618, 0xfcfdf003, 0xd1ae1d40, 0x40bff240, 0x4b55e134, 0x49549100, 0x1f1a3324, 0x003cf101, 
+    0xf940f000, 0x22004950, 0x313c6ba8, 0xfce9f003, 0xd10a1d01, 0x40c6f240, 0xe106e120, 0x494ae112, 
+    0x46182200, 0xf003313c, 0x1d40fcdc, 0xf240d18d, 0xe11340c7, 0x23004a44, 0x32249100, 0xf1011f11, 
+    0xf000001c, 0x4940fb08, 0x6ba82200, 0xf003313c, 0x1d01fcc8, 0xf8a4d108, 0xe7b3b034, 0x2200493a, 
+    0x313c4618, 0xfcbdf003, 0xd1871d40, 0x40cdf240, 0x4835e0f4, 0xe9d52300, 0x303c1208, 0xf9c4f001, 
+    0x22004931, 0x313c6ba8, 0xfcabf003, 0xd1081d01, 0x40d2f240, 0x492ce0e2, 0x46182200, 0xf003313c, 
+    0x1d40fca0, 0xf240d1a1, 0xe0d740d3, 0xf9954b26, 0x33281000, 0x0208f1a3, 0x001cf102, 0xfc0ef001, 
+    0x22004921, 0x313c6ba8, 0xfc8bf003, 0xd1081d01, 0x40d8f240, 0x491ce0c2, 0x46182200, 0xf003313c, 
+    0x1d40fc80, 0xf240d1a2, 0xe0b740d9, 0xf9954816, 0x303c1000, 0xfd78f001, 0x22004913, 0x313c6830, 
+    0xfc6ff003, 0xf47f1d01, 0xf240ae7f, 0xe0a540de, 0x9034f8a4, 0x4b0ce756, 0x1000f995, 0xf1a33328, 
+    0xf1020208, 0xf001001c, 0x4907fdaf, 0x6ba82200, 0xf003313c, 0x1d01fc56, 0xf240d115, 0xe08d40e4, 
+    0x00037aec, 0x00030266, 0x00030c58, 0x000304a8, 0x000304ec, 0x00030265, 0x00030223, 0x22004948, 
+    0xf0034618, 0x1d40fc3e, 0xf240d19c, 0xe07540e5, 0x1000f995, 0xf0014842, 0x4941fdd0, 0x68302200, 
+    0xfc2ff003, 0xf47f1d01, 0xf240ae54, 0xe06540ea, 0x40ebf240, 0x4b3ae062, 0x1000f995, 0x48383b14, 
+    0x0208f1a3, 0xfed4f001, 0x22004935, 0xf0036ba8, 0x1d01fc18, 0xf240d107, 0xe04f40f0, 0x22004930, 
+    0xf0034618, 0x1d40fc0e, 0xf240d18c, 0xe04540f1, 0x1000f995, 0xf002482a, 0x4929f94c, 0x68302200, 
+    0xfbfff003, 0xf47f1d01, 0xf240ae33, 0xe03540f6, 0x40f7f240, 0xf995e032, 0x48211000, 0xf0016a2a, 
+    0x491fff57, 0x6ba82200, 0xfbebf003, 0xd1071d01, 0x40fcf240, 0x491ae022, 0x46182200, 0xfbe1f003, 
+    0xd1a11d40, 0x40fdf240, 0xf8dae018, 0xf0030000, 0x1d01fbd8, 0xae1ff47f, 0x5004f240, 0xf240e00e, 
+    0xe00b5005, 0x5008f240, 0x490de008, 0x46182200, 0xfbc7f003, 0xd1871d40, 0x5009f240, 0xe6b186a0, 
+    0x21012200, 0xf2afb510, 0xf00340e1, 0x2108fa05, 0xf0032004, 0x4902fb63, 0x6388393c, 0x0000bd10, 
+    0x00030c94, 0x4fffe92d, 0x0a00f04f, 0xb083460d, 0x46544681, 0xf04f48fe, 0xf8cd52a0, 0xf9b9a008, 
+    0x68071000, 0x7080f04f, 0xf50746b8, 0xf7df5780, 0x2000fa76, 0xf820f7e7, 0x23004ef6, 0xf24f220c, 
+    0x46300100, 0xfb24f007, 0xf6402300, 0x22087100, 0xf0074630, 0x2300fb1d, 0x22044630, 0xf00721f0, 
+    0x2300fb17, 0x210f4630, 0xf007461a, 0x48eafb11, 0xf0072100, 0x2200fb0a, 0x23109400, 0x46104611, 
+    0xfe3af7e9, 0x700448e5, 0x780048e5, 0x7828b988, 0xd00e2803, 0x3000f44f, 0x0103f640, 0xf9f1f7df, 
+    0xffbff7ec, 0x210048df, 0x2000f990, 0xf7e84608, 0x4cddfc91, 0x23002208, 0x46200151, 0xfafff007, 
+    0xb364f8df, 0x0100f44f, 0x138e9102, 0x0bfaf1ab, 0x4ad5e00d, 0xa8022107, 0xf7e63254, 0x2801fbe3, 
+    0x2301d00c, 0x22094631, 0xf0074620, 0x2206fae8, 0x21404658, 0xfaf1f007, 0xd1ea2800, 0xb32cf8df, 
+    0xf99b2401, 0x28050000, 0x2804d002, 0xe002d002, 0xe0002402, 0xf9952404, 0x48c51000, 0x29034ec5, 
+    0x2902d004, 0x2905d00f, 0xe020d01a, 0x1000f9b6, 0xda042901, 0x21382203, 0xfacff007, 0x48beb108, 
+    0x48bee00f, 0xf9b6e00d, 0x29011000, 0x2203da04, 0xf0072138, 0xb108fac2, 0xe00248b9, 0xe00048b9, 
+    0x220048b9, 0xf100fb04, 0xf7e62002, 0x2100faef, 0xf7e62002, 0x9805fab5, 0x31fff04f, 0x4ab44cb3, 
+    0x99066001, 0xa000f8c1, 0x1c406820, 0x88116020, 0x80111c49, 0x48a4b281, 0xf0073018, 0xf240fa76, 
+    0x81b01000, 0x81f02081, 0x46517820, 0xa2a4f8df, 0x0007f000, 0x1200eb00, 0x0082eb0a, 0x20056301, 
+    0xfaaef7e6, 0xf0026822, 0xeb010107, 0xeb0a1301, 0xe9c10183, 0x48a0020d, 0x63c88800, 0x6800489f, 
+    0xf7e56408, 0x489efcfe, 0x213f2200, 0xfa75f007, 0xd3012811, 0xe0002001, 0xf8df2000, 0x2301a22c, 
+    0xf1aa8170, 0x029c0a30, 0x220a4650, 0xf0074621, 0x2300fa56, 0x220a4621, 0xf0074650, 0x4891fa50, 
+    0xb9107800, 0xf7fe2000, 0xf89bfe1b, 0xf9951000, 0xf7e20000, 0x2301f9bc, 0x220e488b, 0xf0070399, 
+    0xf995fa3e, 0x4c890000, 0xa224f8df, 0xf8df2802, 0x4d89b224, 0x2803d004, 0x2805d01d, 0xe078d041, 
+    0xf7fb2001, 0x2100fb5d, 0xf7e72001, 0x8820fbc1, 0x20079000, 0x3000f89a, 0x2000f99b, 0xf7fb7829, 
+    0x2301fa68, 0x2200487d, 0xf0074619, 0x2000fa18, 0xf99ef7fb, 0x8970e058, 0xd1142801, 0x22004878, 
+    0xf9902308, 0x46104000, 0x8700e9cd, 0xf7e44621, 0x4974febe, 0x48742301, 0xe9cd2200, 0x46210100, 
+    0xf7e44618, 0x4871feb4, 0x28017800, 0xf7fbd105, 0x2100fb27, 0xf7e72001, 0x2004fb8b, 0xf978f7fb, 
+    0x8820e037, 0x20079000, 0x3000f89a, 0x2000f99b, 0xf7fb7829, 0x2301fa2e, 0x22004860, 0xf0074619, 
+    0x2002f9de, 0xfa0cf7e6, 0x60084961, 0x49612002, 0x20007008, 0xf95cf7fb, 0x2220495f, 0xf007485f, 
+    0x4e58f95e, 0x4f582400, 0xeb062301, 0xeb072144, 0x22002044, 0x0100e9cd, 0x46184621, 0xfe77f7e4, 
+    0xb2641c64, 0xdbef2c04, 0xf2407829, 0xf7e41000, 0xf04fff97, 0xf2407480, 0x462011f4, 0xf891f7df, 
+    0x3100f243, 0xf7df4620, 0x494df87b, 0xf9914620, 0xf7df1000, 0x494bf875, 0x68094620, 0xf870f7df, 
+    0x46204949, 0xf86cf7df, 0xf8a92144, 0xb0071000, 0x8ff0e8bd, 0x41f0e92d, 0xe098f8df, 0xf04f4690, 
+    0xeb0834ff, 0xfa0f0c04, 0x2200f78c, 0x500ef9be, 0xfb026806, 0xf853c505, 0x42b55025, 0x6005d301, 
+    0x1c52800f, 0x2a04b212, 0x1c64dbf0, 0x2c01b224, 0xe8bddde7, 0xe92d81f0, 0xb0934fff, 0x2000460e, 
+    0xf04f4d32, 0x901152a0, 0x90064831, 0x90092019, 0x68004807, 0xf500900b, 0x900a5080, 0x6800482d, 
+    0x98139008, 0x1000f9b0, 0x7080f04f, 0x0000e054, 0x000301c4, 0xd180004c, 0xd0031034, 0x00030ae4, 
+    0x0003031c, 0x00030227, 0xd0035126, 0x00030222, 0xd28f007c, 0x00030ca8, 0x02faf080, 0x015752a0, 
+    0x017d7840, 0x0094c5f0, 0x03b9aca0, 0x00030c74, 0x00030ca4, 0x00037aec, 0x00030364, 0x00030244, 
+    0xd0034200, 0x00030265, 0xd0030416, 0x00030250, 0x000302a4, 0x000301c8, 0x00030394, 0xd00305ae, 
+    0x00030330, 0x000339dc, 0x000331dc, 0x00030383, 0x00030370, 0x0003036e, 0x0003d1ec, 0x00030fec, 
+    0x00030c58, 0x000301cc, 0xdcba01f5, 0x0003ad5c, 0x0003bd5c, 0x000301b8, 0xf831f7df, 0xf24048fe, 
+    0x81811100, 0x81c12181, 0xf44f2100, 0xf7e63080, 0xf8dff96f, 0xf99bb3e8, 0x28050000, 0x2804d001, 
+    0x2100d104, 0x3000f44f, 0xf962f7e6, 0x21002000, 0x1020f845, 0xb2001c40, 0x6f80f5b0, 0x9816dbf7, 
+    0xd16c2800, 0x78204cee, 0xd1172803, 0xf24848ed, 0x78010700, 0xf7e64638, 0x48ebf94b, 0xb9087800, 
+    0xff2ef7ec, 0xf04f48e4, 0x89400100, 0xd00c2801, 0xf7e64638, 0x7820f93d, 0xd0092803, 0x0000f994, 
+    0xd0052802, 0xd0032805, 0xf244e057, 0xe7f00000, 0xf00748de, 0xb207f897, 0xf44f2100, 0xf7e63000, 
+    0x0778f927, 0xf64fd511, 0xea0770fb, 0x48d70100, 0xf88bf007, 0x0000f89b, 0xd1062803, 0x28027820, 
+    0x2100d103, 0xf7e60400, 0x4fd0f913, 0xf0074638, 0xb201f879, 0xd5050608, 0x707ff64f, 0x46384001, 
+    0xf873f007, 0xf0074638, 0xb201f86d, 0xd50504c8, 0x70fff64e, 0x46384001, 0xf867f007, 0x28057820, 
+    0xf44fd10d, 0x21003400, 0xf7e64620, 0x2100f8f1, 0xf7e64620, 0x2100f8ed, 0xf7e64620, 0x48b8f8e9, 
+    0x0000f990, 0xd0012802, 0xd1062805, 0xfa5bf7e8, 0x9010b200, 0xf7e82008, 0xf242fa4f, 0x064801c0, 
+    0xff4bf7de, 0x0b00f04f, 0xf2422700, 0x064801c0, 0xff43f7de, 0x230148a8, 0x029a2105, 0x000cf9b0, 
+    0x000fe88d, 0x1f8a48aa, 0x21082300, 0xf7fa6800, 0x2400f84b, 0x980849a0, 0xeb00230c, 0xf9b12044, 
+    0x49a4200c, 0xffe9f006, 0x48a32108, 0x4aa44ba3, 0x0100e9cd, 0x9911489f, 0xf944f007, 0xe258f8df, 
+    0xe0172000, 0xf851499e, 0x499c3020, 0x1020f851, 0x1201fb81, 0x1203fbc3, 0x030cfb04, 0x1206e9ce, 
+    0xf8550d89, 0xea41c023, 0x1c402182, 0xb2004461, 0x1023f845, 0xc00ef9be, 0xdbe34560, 0x100ef9be, 
+    0x43612000, 0x0021f845, 0xf9914985, 0x29021000, 0x2905d001, 0xf9bed108, 0xf9be100e, 0x4361200c, 
+    0x0162eb01, 0x0021f845, 0x680a9920, 0x100cf9be, 0x0fa1ebb2, 0xf9bed106, 0x4362200e, 0x01a1eb02, 
+    0x0021f845, 0xb2641c64, 0xdba32c04, 0xb23f1c7f, 0xdb8a2f02, 0x0f00f1bb, 0xa80dd10f, 0xab059906, 
+    0xaa079000, 0xf7fe4628, 0x486bfc2e, 0x1034f9bd, 0x200ef9b0, 0xf1f2fb91, 0xf10b8101, 0xfa0f0001, 
+    0xf1bbfb80, 0xf6ff0f01, 0xf242af6f, 0x064801c0, 0xfeb3f7de, 0xf9904862, 0x28020000, 0x2805d001, 
+    0x9810d103, 0xf7e8b2c0, 0x495bf9a7, 0x90042000, 0x82081e40, 0x68004863, 0xd37c2812, 0xbbe89816, 
+    0x78004859, 0x4856bbd0, 0x28027800, 0xf04fd178, 0xf2407b80, 0x465811f4, 0xfe83f7de, 0x1199f641, 
+    0xf7de4658, 0x4c58fe6d, 0xf9944658, 0xf7de1000, 0xf9bdfe67, 0x46581034, 0xfe62f7de, 0x46584f46, 
+    0x1008f9b7, 0xfe5cf7de, 0x0000f994, 0x1008f9b7, 0xd14e4288, 0xb01cf8dd, 0x46042000, 0xf9b79000, 
+    0xf9bd100e, 0xfb040014, 0xf8550001, 0xf04f1020, 0xf7de7080, 0xf9bdfe45, 0xe0000014, 0xf9b7e040, 
+    0xfb04100e, 0xf8550001, 0x45580020, 0x4683da01, 0x1c649400, 0x2c04b264, 0xf04fdbe1, 0x99007780, 
+    0xf7de4638, 0xf9bdfe2d, 0x46381014, 0xfe28f7de, 0xfcf0f7ec, 0x14024c34, 0x70219900, 0x4610b201, 
+    0xfc79f7ec, 0x20014931, 0x20027008, 0xfe75f7ec, 0x0000f994, 0xfbd0f7ec, 0x0000f994, 0xfc15f7ec, 
+    0x0000f994, 0xfc60f7ec, 0x1000f994, 0xf7de4638, 0x4927fe07, 0xe0a3e000, 0x7080f04f, 0xfe00f7de, 
+    0xb054f8df, 0x0000f8bb, 0xf9bdbb28, 0x27030014, 0x0110f10b, 0xfb90462b, 0xb202f0f7, 0xf7ffa804, 
+    0xf9bbfd89, 0x465c100c, 0x0014f9bd, 0xfb911a09, 0xb20af1f7, 0x1d001a10, 0xd9052808, 0x0110f10b, 
+    0xa804462b, 0xfd76f7ff, 0xf8dd8a20, 0x80e0a010, 0x0014f9bd, 0xe037e01e, 0x00030ca8, 0x00030222, 
+    0x00030c58, 0x00030223, 0x0003031c, 0xd03c80b6, 0x000301b8, 0x000341dc, 0x0002bb10, 0x000371dc, 
+    0x000369dc, 0x000301cc, 0x00030227, 0x00030225, 0xdcba01f5, 0x70d0eb00, 0x462b49ff, 0xa8041042, 
+    0xfd48f7ff, 0x100cf9b4, 0x0014f9bd, 0xeb011a09, 0x104971d1, 0x1a10b20a, 0x28081d00, 0x49f6d904, 
+    0x462ba804, 0xfd36f7ff, 0x1010f9bb, 0x9809465c, 0xda034281, 0x90042000, 0x82201e40, 0x0014f9bd, 
+    0x00412201, 0xf9b4b20f, 0xeb02100c, 0x428202a1, 0x4242dc03, 0x0142eb01, 0x287db20f, 0x49e6dc05, 
+    0x462ba804, 0xf7ff463a, 0x970efd15, 0x900c9804, 0x0014f9bd, 0xeb00282b, 0xb20a0140, 0x89a2db04, 
+    0x0180eba0, 0xb20a4411, 0xdc092845, 0x100cf9b4, 0x0fa1ebb0, 0x49d8d004, 0x462ba804, 0xfcfaf7ff, 
+    0xf188fa1f, 0xf00648d5, 0x48d4fe70, 0xf189fa1f, 0xf0061c80, 0x980ffe6a, 0xb2811c40, 0x1d0048cf, 
+    0xfe63f006, 0xf3c09807, 0x48cc214f, 0xf0061d80, 0xf8bdfe5c, 0xb2810014, 0x300a48c8, 0xfe55f006, 
+    0x7780f04f, 0x11f4f240, 0xf7de4638, 0xf240fd4a, 0x46387177, 0xfd34f7de, 0x46384cc1, 0xf7de6821, 
+    0xf9bdfd2f, 0x46381014, 0xfd2af7de, 0x0a019807, 0xf7de4638, 0x49bbfd25, 0xf7de4638, 0x7820fd21, 
+    0xf0004cba, 0xeb000007, 0x48b71100, 0x0081eb00, 0x8903e9c0, 0xf04f990f, 0x61410800, 0x7014f9bd, 
+    0xf9bd61c7, 0xf8df1034, 0x620192b0, 0xf1a99b07, 0xf8c00910, 0x0a5a8024, 0xf9b96182, 0xea4f000c, 
+    0xf8c60ea0, 0xf8dde000, 0xf8cee054, 0xf8a98000, 0xf8a98002, 0xf9948004, 0xf1bcc000, 0xd0070f03, 
+    0x0e04f04f, 0xe020f8cd, 0xf240d105, 0xe00414f4, 0x0e32f04f, 0xf04fe7f6, 0xebbe040a, 0xd2202f53, 
+    0x98156037, 0x43c86002, 0x4894b281, 0xf0061d00, 0x4896fdec, 0x28037800, 0xd0069804, 0x2f10ebb4, 
+    0x2001d864, 0x0002f8a9, 0xebb4e060, 0xd85d2f10, 0x2010f9b9, 0x428a9909, 0x2101db58, 0x1002f8a9, 
+    0xf1bce054, 0xd0250f03, 0x7b80f04f, 0x11f4f240, 0xf7de4658, 0xf648fcc6, 0x46580180, 0xfcb0f7de, 
+    0x46584c7f, 0xf7de6821, 0x4f81fcab, 0x78394658, 0xfca6f7de, 0x46586831, 0xfca2f7de, 0x46584979, 
+    0xfc9ef7de, 0x28016820, 0x7838db13, 0xd8102823, 0xe0102080, 0x68099920, 0xd0071c4a, 0x10406031, 
+    0x0010f8a9, 0xf8a92001, 0xe0170002, 0x60301040, 0xf04fe014, 0xf24030ff, 0x465c11f4, 0x46586030, 
+    0xfc8ff7de, 0x46206831, 0xfc7af7de, 0x46204965, 0xfc76f7de, 0x8002f8a9, 0x8004f8a9, 0xf600980f, 
+    0xb28130b8, 0x1d00485d, 0xfd7ff006, 0x68004861, 0xd3772812, 0x000cf9b9, 0x1014f9bd, 0x0fa0ebb1, 
+    0xf8b9d108, 0x464a3002, 0x1043b923, 0x23018213, 0x3002f8a9, 0xf9944c55, 0x2a032000, 0xebb1d10f, 
+    0x464b0f60, 0x1f17d004, 0x0760eb07, 0xd106428f, 0xb927885f, 0x82181080, 0xf8a92001, 0x98090002, 
+    0xdc034281, 0x8002f8a9, 0x8004f8a9, 0x46a32a03, 0xf8b9d13f, 0x46481002, 0x9920b921, 0x82018809, 
+    0x80412101, 0x000af8b9, 0xd1322801, 0xf9904842, 0x88307000, 0xf04fb204, 0x2c800000, 0x4642d033, 
+    0xeb049b0b, 0x1c4011c0, 0xf823b200, 0x9b0a2011, 0xf8232808, 0xdbf32011, 0x210ae9dd, 0x23002008, 
+    0x0007e88d, 0x4639461a, 0xf7e44618, 0x4833f935, 0x4a332c80, 0xf822d021, 0xf8208014, 0x21018014, 
+    0x23009100, 0xe9cd4639, 0x20012001, 0xf7e4461a, 0xf9b9f923, 0x464c0006, 0x1010f9b9, 0xd0554288, 
+    0xb1698861, 0x4641e052, 0xeb029a0a, 0x1c402200, 0x2808b200, 0xdbf78011, 0xf8a0e7ce, 0xe7de8000, 
+    0x1000f89b, 0xd07d2903, 0x215aea5f, 0x9909d03e, 0xdb3b4288, 0xf2402001, 0x80a011f4, 0x46380607, 
+    0xfbdff7de, 0x5122f245, 0xf7de4638, 0xf9b4fbc9, 0x46381004, 0xfbc4f7de, 0x215aea4f, 0xf7de4638, 
+    0xf9b4fbbf, 0x46381010, 0xfbbaf7de, 0x1006f9b4, 0xf7de4638, 0xe015fbb5, 0x00030cb8, 0xd03c80a8, 
+    0x00030c74, 0xdcba01f5, 0x00037aec, 0x00030c58, 0x0003031e, 0x000301cc, 0x00030330, 0x000339dc, 
+    0x000331dc, 0x463849fe, 0xfb9af7de, 0xb3d09816, 0x77d0f240, 0xf04f9700, 0x24007b80, 0x10b94658, 
+    0xfb9ff7de, 0x3111f243, 0xf7de4658, 0x4639fb89, 0xf7de4658, 0x48f3fb85, 0x46587801, 0xfb80f7de, 
+    0x46584639, 0xfb7cf7de, 0x465849ed, 0xfb78f7de, 0x0014f9bd, 0xda012819, 0x91000079, 0x9a009907, 
+    0xebb29101, 0xd2302f51, 0xe00ef9b9, 0xf8cd2103, 0x46cce008, 0xb00cf9b9, 0x0e08f1ae, 0xdc0e4570, 
+    0xe0011843, 0xe0a1e04e, 0x7008f8bc, 0xfb179a02, 0x9a063302, 0x2023f852, 0xdb0042a2, 0xebb04614, 
+    0xd0020f6b, 0x0fabebb0, 0xf8bcd10b, 0x9a023008, 0x1302fb13, 0xeb029a06, 0x6c920283, 0xdb0042a2, 
+    0x1c894614, 0x2907b209, 0xf9b9ddd8, 0x2100200c, 0xebb0464f, 0xd0020f62, 0x0fa2ebb0, 0x2102d100, 
+    0x89fb893a, 0xfb121d49, 0xf8550203, 0x410a2022, 0xdb0442a2, 0x1200e9dd, 0x2f52ebb1, 0x9a15d302, 
+    0x8000f8c2, 0xf8df4641, 0xf88bb300, 0x9a158000, 0x2a006812, 0x381cdd16, 0xd8132808, 0x780048bb, 
+    0xe00fb168, 0xebb12105, 0xf63f2f5a, 0x9909af1b, 0xf6ff4288, 0x2001af17, 0x0004f8a9, 0x2201e766, 
+    0x2000f88b, 0xf2409a04, 0xebb070d0, 0xd3002f52, 0xebb08079, 0xd3002f5a, 0xf04f80b9, 0xf2407080, 
+    0xf7de11f4, 0xf04ffafe, 0xf2417080, 0xf7de1122, 0xf99bfae7, 0xf04f1000, 0xf7de7080, 0x9900fae1, 
+    0x7080f04f, 0xfadcf7de, 0x0a419807, 0x7080f04f, 0xfad6f7de, 0x1014f9bd, 0x7080f04f, 0xfad0f7de, 
+    0x7080f04f, 0xf7de4621, 0xf9b7facb, 0xf04f1002, 0xf7de7080, 0xf9b7fac5, 0xf04f1004, 0xf7de7080, 
+    0x498ffabf, 0x7080f04f, 0xfabaf7de, 0x0107e9dd, 0x2f50ebb1, 0xf04fd33a, 0xf2407b80, 0x465811f4, 
+    0xfabff7de, 0x0181f648, 0xf7de4658, 0x4c88faa9, 0x68214658, 0xfaa4f7de, 0x46584f82, 0xf7de7839, 
+    0x6831fa9f, 0xf7de4658, 0x497dfa9b, 0xf7de4658, 0x6820fa97, 0xdb042801, 0x28237838, 0x2080d801, 
+    0xf04fe001, 0xf24030ff, 0x465c11f4, 0x46586030, 0xfa97f7de, 0x46206831, 0xfa82f7de, 0x46204970, 
+    0xfa7ef7de, 0x8002f8a9, 0x8004f8a9, 0x68019820, 0x42816830, 0x1c40d164, 0xf8b9d062, 0x464c0000, 
+    0x1c404968, 0xf8a9b200, 0x78090000, 0xd3112946, 0xdb0d2802, 0x2b018863, 0x88a2d10a, 0xd1072a01, 
+    0x45539b04, 0xf8a4d302, 0xe0018004, 0x8002f8a4, 0xd8472946, 0xdb452801, 0x2232980c, 0x2f50ebb2, 
+    0x8861d20d, 0xf9b4b959, 0x46203010, 0x428b9909, 0x2101db05, 0x990e8041, 0x980c8221, 0x980c9004, 
+    0x2f50ebb2, 0x88a0d22e, 0xf9b4bb48, 0x98091010, 0xdb274281, 0x80a02001, 0xf04f980e, 0x80e07780, 
+    0x11f4f240, 0xa030f8dd, 0xf7de4638, 0xf245fa3a, 0x46385111, 0xfa24f7de, 0x1004f9b4, 0xf7de4638, 
+    0xea4ffa1f, 0x4638215a, 0xfa1af7de, 0x1006f9b4, 0xf7de4638, 0x493afa15, 0xf7de4638, 0xe001fa11, 
+    0x8000f8a9, 0xbbe89816, 0xf8cda802, 0xf8cd8000, 0xf7e78004, 0x6830fba6, 0xd0251c40, 0x46e82700, 
+    0x6830463c, 0x19c19a06, 0x0021f855, 0x1021f852, 0xdb104288, 0xebc01a40, 0x08401080, 0xfc2cf7e7, 
+    0x4a2ca902, 0x1014f931, 0x011ff1c1, 0x1011f832, 0x0b884341, 0x2000e000, 0x0014f828, 0x1c643781, 
+    0xb23fb224, 0xdbdc2c04, 0x1000f8bd, 0xf0064822, 0x4821faec, 0x1002f8bd, 0xf0061c80, 0xf8bdfae6, 
+    0xe0001004, 0x481ce009, 0xf0061d00, 0x481afade, 0x1006f8bd, 0xf0061d80, 0xf04ffad8, 0xf2407580, 
+    0x462811f4, 0xf9cdf7de, 0x2122f240, 0xf7de4628, 0x9820f9b7, 0x46286801, 0xf9b2f7de, 0x46286831, 
+    0xf9aef7de, 0x0a019807, 0xf7de4628, 0xf9b9f9a9, 0x464c1002, 0xf7de4628, 0xf9b4f9a3, 0xe00d1010, 
+    0xdcba01f5, 0x0003031e, 0x00030c9d, 0x0003031c, 0x00030c74, 0x00030ae6, 0xd0035154, 0xf7de4628, 
+    0x9804f98f, 0x46280a01, 0xf98af7de, 0x1004f9b4, 0xf7de4628, 0xf9b4f985, 0x46281006, 0xf980f7de, 
+    0x211aea4f, 0xf7de4628, 0x49faf97b, 0xf7de4628, 0xf242f977, 0x064801c0, 0xf98ff7de, 0x21459813, 
+    0xb0178001, 0x8ff0e8bd, 0x4fffe92d, 0x4682b085, 0x460f2000, 0x52a0f04f, 0x48ef9003, 0x20196804, 
+    0x48ee9004, 0x1000f9ba, 0x8000f990, 0x7080f04f, 0xf9b5f7de, 0x98084dea, 0xf995bb08, 0x28050000, 
+    0x2803d01d, 0x48e7d01b, 0x28166800, 0x2100d204, 0x3000f44f, 0xfaecf7e5, 0x880048e3, 0x48e39000, 
+    0x48e37803, 0x2000f990, 0x780148e2, 0xf7fa2000, 0x2300fab0, 0x210148e0, 0xf006461a, 0xf8dffa60, 
+    0x48df937c, 0x100cf9b9, 0xfa26f007, 0x260048d4, 0x0000f990, 0xd0042803, 0x91022104, 0xb1119908, 
+    0x2101e007, 0x2805e7f9, 0x4646d103, 0xb2401c70, 0x48d49002, 0x0587eb00, 0x48d3e12f, 0x28067800, 
+    0x0000f04f, 0x49d1d312, 0xeb014bce, 0xf9b92286, 0xe005100e, 0xc020f852, 0xc020f843, 0xb2001c40, 
+    0xdbf74288, 0xf85048ca, 0xe00e0026, 0xf9b94bc3, 0x49c4200e, 0xe0053320, 0xc020f853, 0xc020f841, 
+    0xb2001c40, 0xdbf74290, 0xf8556818, 0xf8df1c08, 0xebb1c2f4, 0xdd000fe0, 0xf84510c1, 0xf8551c08, 
+    0xebb11c04, 0xdd000fa0, 0xf8451081, 0xf84c1c04, 0x68690027, 0x0fa0ebb1, 0x1081dd00, 0x68a96069, 
+    0x0fe0ebb1, 0x10c1dd00, 0x49a660a9, 0x29126809, 0xf8b9d332, 0x46ce1002, 0xd1142901, 0x3010f9be, 
+    0x0183eb0c, 0x2c04f851, 0x0fa0ebb2, 0x1082dd00, 0x2c04f841, 0xf84c1082, 0x684b2023, 0x0fa0ebb3, 
+    0x461adc00, 0xf8be604a, 0x29011004, 0xf9b9d114, 0xeb0c3006, 0xf8510183, 0xebb22c04, 0xdd000fa0, 
+    0xf8411082, 0x10822c04, 0x2023f84c, 0xebb3684b, 0xdc000fa0, 0x604a461a, 0x001af1a7, 0xd917280a, 
+    0x1010f9b9, 0x391a4648, 0xd802290a, 0x29018841, 0xf9b0d00e, 0x391c1006, 0xd8032908, 0x0004f8b9, 
+    0xd0052801, 0x498b2000, 0x1c787008, 0xe004d002, 0xe7f82001, 0x21024887, 0xf9b97001, 0xf9b9000e, 
+    0xe006100c, 0xf85c1a0a, 0xf84c2022, 0x1c402020, 0x4288b200, 0x2108dbf6, 0x4a80487f, 0xe9cd9b03, 
+    0x49770100, 0xf0064877, 0x497cfd87, 0x5200f04f, 0x2000e009, 0x3020f851, 0xf841005b, 0x1c403020, 
+    0x2811b200, 0x6808dbf6, 0xddf24290, 0x4280f04f, 0x42906808, 0x0000f04f, 0xf851dd09, 0x105b3020, 
+    0x3020f841, 0xb2001c40, 0xdbf62811, 0xf851e7f0, 0xf1022020, 0xf8415200, 0x1c402020, 0x2811b200, 
+    0x4867dbf5, 0x1106eb06, 0xeb002210, 0x48630181, 0xf7f4468b, 0x2000f8a4, 0x027ef06f, 0x1020f85b, 
+    0x7180f501, 0x214ff341, 0xf8242980, 0xdd001010, 0x42912180, 0x1010f824, 0x4611da00, 0x1010f824, 
+    0xb2001c40, 0xdde92810, 0x46012000, 0x2010f834, 0xb2001c40, 0xb2094411, 0xdbf72811, 0x42879804, 
+    0x8c20db02, 0x84201a40, 0x2000494e, 0x1106eb01, 0x0240eb04, 0x540a7892, 0xb2001c40, 0xdbf72810, 
+    0x21014849, 0x1c764a49, 0x7800b276, 0x0007f000, 0x1000eb00, 0x0080eb02, 0x98026241, 0xf6ff4286, 
+    0xf8b9aecc, 0xb9880000, 0x21004e41, 0x20004d3d, 0x1301eb06, 0x1201eb05, 0x541f5c17, 0xb2001c40, 
+    0xdbf92810, 0xb2491c49, 0xdbf02904, 0xbbe89808, 0x78004823, 0xd1392805, 0xc0c8f8df, 0xf04f2200, 
+    0x461039ff, 0x1308eb0c, 0x46154649, 0x4249466e, 0xe000f913, 0x5435b209, 0xfb1e1c40, 0xb2002201, 
+    0x2810b212, 0xf1c2dbf3, 0xb2000040, 0x28082100, 0xf1a0dd03, 0xb2090108, 0xf1102701, 0xda030f08, 
+    0x464f3008, 0xb2014240, 0x2900427f, 0x2910dd42, 0x2000dd40, 0x4252463a, 0x5c35b212, 0x54354415, 
+    0xb2001c40, 0xdbf62810, 0xe0003910, 0xb209e059, 0x0000e7eb, 0xdcba01f5, 0x000301c4, 0x00030227, 
+    0x00030c58, 0x000301cc, 0x00030250, 0x000302a4, 0x000301c8, 0x00030394, 0xd00305ae, 0x00030ca8, 
+    0x000371dc, 0x000369dc, 0x0003031e, 0x00037d4c, 0x00038d4c, 0x00030c9c, 0x0002bb10, 0x000341dc, 
+    0x000379dc, 0x0003319c, 0x00030c74, 0x00037aec, 0x0003d22c, 0x280f1e48, 0x2000d80a, 0x427ae006, 
+    0x5c32b217, 0x5432443a, 0xb2001c40, 0xdbf64288, 0x5c192000, 0x44115c32, 0x1c405419, 0x2810b200, 
+    0x2100dbf7, 0xd0084541, 0xeb0c2000, 0x5c1d1201, 0x1c405415, 0x2810b200, 0x1c49dbf9, 0x2904b249, 
+    0x4de3dbf0, 0x28037828, 0x4ee2d110, 0x20002101, 0x1301eb06, 0x0240eb04, 0x541a7892, 0xb2001c40, 
+    0xdbf72810, 0xb2491c49, 0xdbf02904, 0x01c0f242, 0xf7dd0648, 0xf995ff32, 0x28020000, 0x2803d005, 
+    0x2805d005, 0x210fd008, 0x2146e002, 0x2149e000, 0x1000f8aa, 0xe595b009, 0xe7f9214c, 0x4ff0e92d, 
+    0x7780f04f, 0x1000f9b0, 0x461e2500, 0x4614b087, 0x52a0f04f, 0x46384682, 0xff51f7dd, 0x01c0f242, 
+    0xf7dd0648, 0x6820ff0a, 0x68206030, 0x1c414ac2, 0xf44fd004, 0x434831c8, 0xe0010c01, 0x71fff64f, 
+    0xf0054610, 0xf240fff2, 0x463811f4, 0xfee9f7dd, 0x3133f243, 0xf7dd4638, 0x6831fed3, 0xf7dd4638, 
+    0x6821fecf, 0xf7dd4638, 0x48b4fecb, 0x100af9b0, 0xf7dd4638, 0x48b2fec5, 0x213f2200, 0xfffdf005, 
+    0x46384601, 0xfebcf7dd, 0x780148ae, 0xf7dd4638, 0x49adfeb7, 0xf7dd4638, 0x48adfeb3, 0x680049ab, 
+    0xf85cf7e5, 0x82acf8df, 0xf8df2400, 0x4fa192ac, 0xeb082000, 0xeb091c04, 0xeb071104, 0x68321304, 
+    0xd0321c52, 0x540a5c1a, 0xb2401c40, 0xdbf62810, 0xf7e34620, 0x1c64fd0e, 0x2c04b264, 0x2001dbe8, 
+    0xff46f7f9, 0x01c0f242, 0xf7dd0648, 0xf8dffea6, 0x2001b26c, 0xf99b2300, 0x90004000, 0xeb084620, 
+    0xeb091204, 0xf7e31104, 0x4e95fdc7, 0xeb072000, 0xeb061204, 0x5c131104, 0x1c40540b, 0x2810b240, 
+    0x4890dbf9, 0xb1187800, 0xf81ce004, 0xe7ca2000, 0xfdf6f7eb, 0x46c32400, 0x270146b8, 0xf9904887, 
+    0x42840000, 0x2300d013, 0xeb0b4620, 0x97001204, 0x1104eb09, 0xfda0f7e3, 0xeb082000, 0xeb061104, 
+    0x5c0b1204, 0x1c405413, 0x2810b240, 0x1c64dbf9, 0x2c04b264, 0xf8dfdbe2, 0x497781f0, 0x0000f998, 
+    0xfcdcf7e3, 0x21044a79, 0xf0054873, 0x4c75fe25, 0xb9187820, 0x70074876, 0xfb82f7f9, 0x70074875, 
+    0xfd0ef7f9, 0x22034874, 0xf0052138, 0xb108ff66, 0xfefaf7e4, 0x4b00f04f, 0x09c0f242, 0x46584649, 
+    0xfe3bf7dd, 0x210e4e6d, 0x0000f996, 0xd0152803, 0xd0132805, 0x9100220e, 0x95042301, 0x95052080, 
+    0x7502e9cd, 0x46119101, 0xfe2cf7e5, 0x46584649, 0xfe23f7dd, 0x28037830, 0xe017d00b, 0x91002301, 
+    0x9504220e, 0x95050218, 0x7502e9cd, 0x46119101, 0x200fe7ea, 0x23019000, 0xe9cd4602, 0x46017502, 
+    0x95059504, 0x02589001, 0xfe0cf7e5, 0x46584649, 0xfe03f7dd, 0xf7e64852, 0xf998fee2, 0x49500000, 
+    0x0020f851, 0x3fc0f5b0, 0x4649d931, 0xf7dd4658, 0x4d4cfdf4, 0x4a4c2000, 0x494d4b4c, 0x0740eb02, 
+    0x6010f835, 0x6010f822, 0x0640eb05, 0x6200f8b6, 0x6200f8a7, 0x0740eb01, 0x6010f833, 0x6010f821, 
+    0x0640eb03, 0x28811c40, 0x6200f8b6, 0x6200f8a7, 0x4649dbe4, 0xf7dd4658, 0x483efdd0, 0xb1306800, 
+    0x31a6f240, 0x78224b3c, 0xf7e41e48, 0x2301ff83, 0x4619220f, 0xf7e54610, 0x4820fe96, 0x0000f9b0, 
+    0xdb182801, 0xb2452805, 0x2505db00, 0x24004f33, 0x3600f44f, 0x7839e00d, 0xf7e44630, 0x2100ff39, 
+    0xf7e44630, 0x2100ff35, 0xf7e44630, 0x1c64ff31, 0x42acb264, 0x4649dbef, 0xf7dd4658, 0x2148fd9e, 
+    0x1000f8aa, 0xe40db007, 0x21014a25, 0x4604b510, 0xf7f07011, 0x4823f938, 0x80012104, 0x8020200a, 
+    0x01c0f242, 0x4010e8bd, 0xf7dd0780, 0x0000bd86, 0x00030c58, 0x0003319c, 0xd003513c, 0x00030ca8, 
+    0xd0034200, 0x0003031e, 0xdcba01f5, 0x00167fc4, 0x00030370, 0x0003315c, 0x00030fec, 0x00030227, 
+    0x0003d1ec, 0x0003031c, 0x00030330, 0x0003102c, 0x00030225, 0x00030226, 0xd28f007c, 0x00030222, 
+    0x0003113c, 0x00039d5c, 0x000331dc, 0x0003a55c, 0x000339dc, 0x00047f70, 0xd03c80b8, 0x00030223, 
+    0x000301e3, 0x000304a2, 0x47f0e92d, 0x7780f04f, 0x1000f9b0, 0x4614461d, 0x52a0f04f, 0x46384606, 
+    0xfd7df7dd, 0x4900f04f, 0x08c0f242, 0x46484641, 0xfd33f7dd, 0x60286820, 0x4a956820, 0xd0041c41, 
+    0x31c8f44f, 0x0c014348, 0xf64fe001, 0x461071ff, 0xfe1bf005, 0x11f4f240, 0xf7dd4638, 0xf243fd12, 
+    0x46383133, 0xfcfcf7dd, 0x46386829, 0xfcf8f7dd, 0x46386821, 0xfcf4f7dd, 0x46384986, 0xfcf0f7dd, 
+    0x49854886, 0xf7e46800, 0x4641fe99, 0xf7dd4648, 0x2048fd04, 0xe8bd8030, 0xe92d87f0, 0xf04f4ff0, 
+    0xf24b7480, 0x26007598, 0x11f4f240, 0x4620b087, 0xfce7f7dd, 0x0177f649, 0xf7dd4620, 0x4978fcd1, 
+    0xf9b14620, 0xf7dd1000, 0x4972fccb, 0xf7dd4620, 0xf8dffcc7, 0x4c74b1d0, 0x0000f89b, 0xf44fb968, 
+    0xf6403000, 0xf7dd0103, 0xf7ebfccc, 0x2100fa9a, 0x2000f994, 0xf7e64608, 0x46a1ff6d, 0x4000f994, 
+    0x90002001, 0x2300486a, 0xa1a0f8df, 0x1104eb00, 0xeb0a4620, 0xf7e31204, 0x4f66fbef, 0x4b662000, 
+    0x1104eb07, 0x1204eb03, 0x5c0c4698, 0x1c405414, 0x2810b200, 0xf89bdbf8, 0xb9080000, 0xfc20f7eb, 
+    0x27012400, 0x0000f999, 0xd0154284, 0x23004858, 0x1204eb0a, 0xeb009700, 0x46201104, 0xfbccf7e3, 
+    0x20004954, 0x1204eb08, 0x1104eb01, 0x54135c0b, 0xb2001c40, 0xdbf92810, 0xb2641c64, 0xdbe12c04, 
+    0x4800f04f, 0x0ac0f242, 0x46514654, 0xf7dd4640, 0x200efc84, 0x23019000, 0xe9cd4602, 0x46017602, 
+    0x96059604, 0x02189001, 0xfc7cf7e5, 0x46404621, 0xfc73f7dd, 0x0000f89b, 0x2100b9a0, 0xf7e72001, 
+    0xf999f970, 0x21002000, 0x464c200c, 0xfebcf7e6, 0xf9942101, 0x46082000, 0xfefcf7e6, 0x70074837, 
+    0xf98ef7f9, 0x22034836, 0xf0052138, 0xb108fd76, 0xfd0af7e4, 0x220f2301, 0x46104619, 0xfd23f7e5, 
+    0xf44f4f30, 0x78393000, 0xfdd2f7e4, 0x46404651, 0xfc43f7dd, 0x88004822, 0xd1362801, 0x492a481f, 
+    0xf7e46800, 0x4e29fdcb, 0xf44f2400, 0x48273880, 0xfd15f7e6, 0x42a86830, 0x6870d808, 0xd80542a8, 
+    0x42a868b0, 0x68f0d802, 0xd90742a8, 0x46407839, 0xfdaef7e4, 0xb2641c64, 0xdbe82c0a, 0x7580f04f, 
+    0x11f4f240, 0xf7dd4628, 0xf241fbfb, 0x46281100, 0xfbf6f7dd, 0x46284621, 0xfbf2f7dd, 0x4628b007, 
+    0xe8bd4904, 0xf7dd4ff0, 0xb007bbeb, 0x8ff0e8bd, 0xd003513c, 0xdcba01f5, 0x001312d0, 0x00030370, 
+    0x00030cb2, 0x0003031c, 0x00030227, 0x0003315c, 0x00030fec, 0x0003319c, 0x0003d1ec, 0x00030225, 
+    0xd28f007c, 0x00030223, 0x005a000a, 0x0003113c, 0x4ffee92d, 0x7b80f04f, 0x1000f9b0, 0x4616461f, 
+    0x52a0f04f, 0x46584605, 0xfc19f7dd, 0x01c0f242, 0xf7dd0648, 0xf8dffbd2, 0x24009408, 0x8404f8df, 
+    0x0a01f04f, 0x2044eb09, 0xa000f8cd, 0x2144eb08, 0xe9cd2300, 0x20011001, 0x4621461a, 0xf8ccf7e3, 
+    0xb2641c64, 0xdbed2c04, 0x49f748f8, 0xf7e46800, 0x2000fd45, 0x0100f640, 0x46024603, 0xf7e79000, 
+    0x48f3ffdb, 0x90008800, 0x780348f2, 0xf99048f2, 0x48f22000, 0x20007801, 0xfcfbf7f9, 0x48f02300, 
+    0x461a2101, 0xfcabf005, 0x780048ee, 0xd1022801, 0xf7f92003, 0x2100fe17, 0xf7e54608, 0x2000fe39, 
+    0xfdcef7f9, 0x60386830, 0x4ae76830, 0xd0041c41, 0x31c8f44f, 0x0c014348, 0xf64fe001, 0x461071ff, 
+    0xfc73f005, 0x11f4f240, 0x4658465c, 0xfb69f7dd, 0x3133f243, 0xf7dd4620, 0x6839fb53, 0xf7dd4620, 
+    0x6831fb4f, 0xf7dd4620, 0x49d8fb4b, 0xf7dd4620, 0xf44ffb47, 0x21003400, 0xf7e44620, 0x2100fce9, 
+    0xf7e44620, 0x2003fce5, 0xfbf2f7f9, 0x01c0f242, 0xf7dd0648, 0x48cefb52, 0x78001066, 0x2400b160, 
+    0x21004630, 0xfcd4f7e4, 0xb2641c64, 0xdbf72c0f, 0x80282047, 0x8ffee8bd, 0xfab2f7eb, 0x46302400, 
+    0xf7e42100, 0x1c64fcc5, 0x2c0fb264, 0xe7efdbf7, 0x4ffee92d, 0x1000f9b0, 0x52a0f04f, 0xf04f4680, 
+    0xf7dd7080, 0xf242fb6c, 0x064801c0, 0xfb25f7dd, 0xf8df4cb7, 0x7820b2e0, 0xf89bb950, 0xb9380000, 
+    0x3000f44f, 0x0103f640, 0xfb0bf7dd, 0xf8d9f7eb, 0xf7f92003, 0x2700fbad, 0x240046a2, 0x78284655, 
+    0x2000b120, 0xfbf3f7f7, 0xe001b978, 0xe7f92001, 0x2c641c64, 0x48a8dbf3, 0xb3586800, 0x21c2f240, 
+    0x782a4ba6, 0xf7e41e48, 0x48a5fcb5, 0x4c9e220d, 0x0100f246, 0xf9903caa, 0xb2830000, 0xf0054620, 
+    0x2300fbfe, 0x22054620, 0xf0052120, 0x2301fbf8, 0x22054620, 0xf0052120, 0xf04ffbf2, 0xf2480900, 
+    0x464c0600, 0x220f4890, 0x38784631, 0xfbf5f005, 0xe008b978, 0x0000f89b, 0xd1022805, 0xf7e64891, 
+    0x210ffbae, 0x1c64e170, 0xdbeb42b4, 0x0f00f1b9, 0x4885d07e, 0xf6432200, 0x387871ff, 0xfbddf005, 
+    0xd07607c0, 0x01c0f242, 0xf7dd0648, 0xf04ffab6, 0xf2407480, 0x462011f4, 0xfaa3f7dd, 0x1111f241, 
+    0xf7dd4620, 0xf8dffa8d, 0x46209200, 0x1000f999, 0xfa86f7dd, 0x46204975, 0xfa82f7dd, 0x46aa2400, 
+    0x0000f89a, 0xd0042801, 0xf9904878, 0x42840000, 0x4d77d021, 0x96002600, 0x46322001, 0x682b4621, 
+    0xf877f7e3, 0x0000f899, 0x28016829, 0x207fd05d, 0xeb01800e, 0xf8320240, 0xf8212c02, 0x1e402010, 
+    0xdcf62800, 0x23006828, 0x0600e9cd, 0x461a2001, 0xf7e24621, 0x1c64ffa7, 0x2c04b264, 0x4d64dbd0, 
+    0x46262400, 0x22009600, 0x46104621, 0xf7e3682b, 0xf899f850, 0x68290000, 0xd0422801, 0x800e207f, 
+    0x0240eb01, 0x2c02f832, 0x2010f821, 0x28001e40, 0x6828dcf6, 0xe9cd2300, 0x461a0600, 0x46184621, 
+    0xff80f7e2, 0xb2641c64, 0xdbdb2c04, 0xe0014654, 0xe0abe004, 0x0000f89a, 0xe05db378, 0x1000f9b8, 
+    0x52a0f04f, 0x7080f04f, 0xfa79f7dd, 0x0000f89b, 0xd0402805, 0x68004840, 0xf240b3e8, 0x4b3f21c4, 
+    0x1e48782a, 0xfbe6f7e4, 0x2000e08c, 0x60fef8a1, 0x0240eb01, 0xf8218852, 0x1c402010, 0xdbf7287f, 
+    0x2000e7a0, 0x60fef8a1, 0x0240eb01, 0xf8218852, 0x1c402010, 0xdbf7287f, 0xe7ffe7bb, 0x3000f44f, 
+    0x0103f640, 0xf9fdf7dd, 0xffcbf7ea, 0x2200482f, 0x0000f990, 0x90029600, 0x682b4601, 0xf7e22001, 
+    0xf899ffe8, 0x68290000, 0xd01d2801, 0x800e207f, 0x0240eb01, 0xe055e000, 0x2c02f832, 0x2010f821, 
+    0x28001e40, 0x6828dcf4, 0xe9cd2300, 0x99020600, 0x461a2001, 0xff16f7e2, 0x1000f899, 0xf8894249, 
+    0x78201000, 0xe038b3b0, 0xf8a12000, 0xeb0160fe, 0x88520240, 0x2010f821, 0x287f1c40, 0xe7e2dbf7, 
+    0x000339dc, 0x000331dc, 0x00393870, 0x00030370, 0x00030250, 0x000302a4, 0x000301c8, 0x00030394, 
+    0xd00305ae, 0x00030384, 0xd003513c, 0xdcba01f5, 0x0003031c, 0x00030c58, 0x00047f70, 0xd03c80b8, 
+    0x00030330, 0x0003113c, 0x00030c9e, 0x00030227, 0x000301c4, 0xf7ebe7ff, 0xf242f913, 0x064801c0, 
+    0xf99bf7dd, 0x2f041c7f, 0xae87f6ff, 0xfaf7f7f7, 0x21002201, 0xf7e52047, 0x204efcde, 0xfdcaf7e6, 
+    0x48a02301, 0x03de220f, 0xf0054631, 0xf89bfa98, 0x465d0000, 0x28054c9c, 0xf89ad005, 0x46570000, 
+    0xd00b2801, 0xf44fe00f, 0x78212600, 0xf7e44630, 0x7821faff, 0xf7e44630, 0xe011fafb, 0xf2427821, 
+    0xf7e40000, 0x2004faf5, 0xfa02f7f9, 0x46307821, 0xfaeef7e4, 0xb9187838, 0xfc4df7e5, 0xf8d0f7eb, 
+    0x28057828, 0x2149d003, 0x1000f8a8, 0x2148e612, 0xe92de7fa, 0xf9b04ff0, 0x26001000, 0xf04fb089, 
+    0xf04f52a0, 0xf7dd7080, 0xf242f98a, 0x064801c0, 0xf943f7dd, 0xf6494f7d, 0x78384440, 0xf44fb938, 
+    0xf6403000, 0xf7dd0103, 0xf7eaf92c, 0x2003fefa, 0xf9cef7f9, 0x91d8f8df, 0xf8df2300, 0xf04f81d8, 
+    0x49750a04, 0x0000f999, 0xa000f8cd, 0x1200eb08, 0x1100eb01, 0xf850f7e3, 0x01c0f242, 0xf7dd0648, 
+    0x7838f91c, 0x486eb930, 0x6800496c, 0xfaa6f7e4, 0xf886f7eb, 0x46c146cb, 0x819cf8df, 0xf99b2500, 
+    0x42850000, 0x2300d009, 0xeb094628, 0xf8cd1205, 0xeb08a000, 0xf7e31105, 0x1c6df82f, 0x2d04b26d, 
+    0xf242dbed, 0x064801c0, 0xf8f7f7dd, 0x46bb7838, 0xd1182801, 0x04c04f54, 0xf7e47839, 0xf44ffa79, 
+    0x78393900, 0xf7e44648, 0xf7eafa73, 0x7839fff9, 0x2080f44f, 0xfa6cf7e4, 0x0103f640, 0xf7dd4648, 
+    0xf7eaf8d0, 0x2003fe9e, 0xf972f7f9, 0xa134f8df, 0x250e2700, 0x0801f04f, 0x1900f240, 0x220e9500, 
+    0x23014648, 0xe9cd4611, 0x96048602, 0x95019605, 0xf8c8f7e5, 0x01c0f242, 0xf7dd0648, 0x2f01f8be, 
+    0x4840dd11, 0xf99bf7e6, 0x1000f8da, 0x42a14650, 0x6841d209, 0xd20642a1, 0x42a16881, 0xf8dad203, 
+    0x42a0000c, 0x1c7fd303, 0x2f10b27f, 0xf89bdbd6, 0xb9200000, 0xf8814934, 0xf7f88000, 0x4833fdd1, 
+    0x21382203, 0xf9b9f005, 0xf7e4b108, 0x2047f94d, 0x0018f8ad, 0x6802482e, 0xf990482e, 0xa8061000, 
+    0xfd56f7ff, 0x46a846c3, 0x46552700, 0xf8cd220e, 0x23018000, 0xe9cd4611, 0x4648b602, 0xf8cd9604, 
+    0x96058004, 0xf87ef7e5, 0xdd0e2f00, 0xf7e6481d, 0x6828f956, 0xd20842a0, 0x42a06868, 0x68a8d205, 
+    0xd20242a0, 0x42a068e8, 0x1c7fd303, 0x2f10b27f, 0x4814dbdc, 0xf943f7e6, 0xf7f92003, 0x2301f8f9, 
+    0x4619220f, 0xf7e54610, 0x4813f92e, 0x28116800, 0xb009d805, 0xe8bd2000, 0xf7e44ff0, 0xb009be3d, 
+    0x8ff0e8bd, 0xd0035092, 0x00030223, 0x0003031c, 0x00030227, 0x0003d1ec, 0x00030fec, 0x001312d0, 
+    0x00030370, 0x0003113c, 0x00030225, 0xd28f007c, 0x00030c78, 0x00030c58, 0x000301cc, 0x47f0e92d, 
+    0x35e0f240, 0x4617461e, 0x22054688, 0x48134604, 0xe9dd4629, 0xf0059a08, 0xb2c0f940, 0x011ff008, 
+    0x1040ea05, 0xf2404301, 0xea004000, 0x43012087, 0x0000f640, 0x20c6ea00, 0x48094301, 0x41a0f441, 
+    0x00c4eb00, 0xf8fbf005, 0xea4a4805, 0x1d004109, 0x00c4eb00, 0x47f0e8bd, 0xb8f1f005, 0xd03c821e, 
+    0xd1800200, 0x5ff0e92d, 0x93fcf8df, 0x8e804604, 0xf8df2600, 0xf8dfb3f8, 0xf5b083f8, 0x4dfd7f9a, 
+    0xa3f4f8df, 0x3000f8d9, 0xdc1ed078, 0xd00f28df, 0xb3a8dc0f, 0xd0482880, 0xd0502881, 0xd16e28de, 
+    0x220048f6, 0x68004629, 0xf93bf001, 0xd0671d40, 0xf5b0e282, 0xd06f7f80, 0x7080f5a0, 0xd0f73801, 
+    0xd06a2813, 0xd15a2814, 0x4fede276, 0x127ff240, 0xf2a04290, 0x683f117f, 0xdc12d0ea, 0x004af111, 
+    0x2813d0e6, 0x2814d06f, 0x2849d0e2, 0x49e1d147, 0x46382200, 0xf0013110, 0x1d40f914, 0xe25bd07e, 
+    0x2919e008, 0x291ad07b, 0x292bd0d2, 0x292cd078, 0xe242d135, 0xf04f49d7, 0xf8da32ff, 0xf0010008, 
+    0x1d01f92f, 0x2080d107, 0x49d2e24e, 0xf8da2200, 0xf0010008, 0x1d41f925, 0x2801d023, 0xf9b5d1ea, 
+    0x296d1000, 0x074ad1e6, 0xf7dc17d0, 0x8868ffc8, 0xf8aa4652, 0xf9b50000, 0xf8aa1004, 0xf9b51002, 
+    0xf8aa0006, 0xb1e80004, 0xd40e0543, 0xf89b4fc5, 0xf9973000, 0x433b7000, 0xe013d005, 0xe224e10d, 
+    0x2081e065, 0x05c0e220, 0x0688d50c, 0x80164630, 0xf040d504, 0xe0030020, 0xe0bbe099, 0x0010f040, 
+    0x0000f8aa, 0x0000f898, 0xd0072801, 0x220648b6, 0xf0052140, 0xb138f872, 0xe0062702, 0x700648b3, 
+    0x700648b3, 0xe10ae014, 0x48af2700, 0xf242220d, 0xf0050100, 0xb100f862, 0x43072001, 0xd01d2f01, 
+    0x49aa2000, 0x70082f02, 0x2000d01a, 0x700849a8, 0xf9ba4651, 0x04c20000, 0xe002d530, 0xe193e174, 
+    0xf420e1c3, 0xf2415080, 0xf8aa0700, 0x220c0000, 0x463948a0, 0xf841f005, 0xe01ab120, 0xe7e02001, 
+    0xe7e32001, 0x7800489c, 0x4a9cb198, 0x46392005, 0xff55f7dc, 0x8028203b, 0x22004890, 0x6800498d, 
+    0xf86ff001, 0xf47f1d01, 0x20deaf31, 0x20dfe1bc, 0x4a92e1ba, 0xf2412005, 0xe1ab0101, 0x06824f90, 
+    0xf020d562, 0x80080020, 0x0002f89a, 0x06804a8b, 0x2005d537, 0x0120f242, 0xff31f7dc, 0x703e4889, 
+    0x28017800, 0x4888d00f, 0x28017800, 0x4887d00b, 0x28018800, 0x4886d007, 0x28017800, 0x4879d003, 
+    0x28017800, 0xf89bd106, 0xb9180000, 0x0000f898, 0xd0712800, 0x80282071, 0x2200496e, 0x0000f8d9, 
+    0xf82ff001, 0xd1071d01, 0x1000f240, 0x4969e17c, 0x46182200, 0xf825f001, 0xd15d1d40, 0x1001f240, 
+    0x2120e172, 0xf7dc2005, 0xf89bfefa, 0x28010000, 0xf898d0df, 0x28000000, 0x2007d0db, 0x495d8028, 
+    0xf8d92200, 0xf0010000, 0x1d01f80c, 0xf240d107, 0xe1591014, 0x22004957, 0xf0014618, 0x1d40f802, 
+    0xf240d1db, 0xe14f1015, 0xd56206c2, 0x0010f020, 0xf89a8008, 0x4a590002, 0xd53806c0, 0xf2422005, 
+    0xf7dc0110, 0x4857fecc, 0x7800703e, 0xd00f2801, 0x78004855, 0xd00b2801, 0x88004854, 0xd0072801, 
+    0x78004853, 0xd0032801, 0x78004846, 0xd1062801, 0x0000f89b, 0xf898b918, 0x28000000, 0x2070d00c, 
+    0x493c8028, 0xf8d92200, 0xf0000000, 0x1d01ffca, 0xf240d108, 0xe1171034, 0x4936e052, 0x46182200, 
+    0xffbff000, 0xd14b1d40, 0x1035f240, 0x2110e10c, 0xf7dc2005, 0xf89bfe94, 0x28010000, 0xf898d040, 
+    0xb3e80000, 0x80282007, 0x2200492a, 0x0000f8d9, 0xffa7f000, 0xd1071d01, 0x1048f240, 0x4925e0f4, 
+    0x46182200, 0xff9df000, 0xd1291d40, 0x1049f240, 0x0442e0ea, 0xf420d56b, 0x80084080, 0x0002f8ba, 
+    0x04404a26, 0x2102d573, 0xf7dc2005, 0x4829fe68, 0x7800703e, 0x4828b148, 0x48287801, 0x48287803, 
+    0x48287802, 0xf7e77800, 0x481ffb00, 0x7800491d, 0x1000f991, 0x49134308, 0x1000f991, 0xe0004308, 
+    0xd103e044, 0xf888f7de, 0xf9ebf7f6, 0x8800481e, 0x4808b3e0, 0x30102173, 0x21018001, 0x22007081, 
+    0x78094915, 0xe03370c1, 0x000304ec, 0x0003021d, 0x0003021c, 0x0003d26c, 0x00030ecc, 0x00030c30, 
+    0x00030c24, 0x00030215, 0xd28fffc0, 0x000301d8, 0x000301d9, 0xd003902c, 0x000301dd, 0xcccc0000, 
+    0x00030306, 0x00030341, 0x00030343, 0x00030216, 0x0003021a, 0x00030308, 0x00030222, 0x000303b9, 
+    0x000303b8, 0x00030307, 0x000302e0, 0xe035e058, 0x48474601, 0xf0006800, 0x1d01ff24, 0xae0df47f, 
+    0x107ef240, 0xe002e070, 0x107ff240, 0x2103e06c, 0xf7dc2005, 0xf7defdf4, 0xf7f6f82f, 0x483df9a8, 
+    0xb3e88800, 0x2173483c, 0x80012200, 0x7086493b, 0x70c17809, 0x48364601, 0xf0006800, 0x1d01ff02, 
+    0xf240d107, 0xe04f1098, 0x22004933, 0xf0004638, 0x1d40fef8, 0xf240d140, 0xe0451099, 0xd53b0742, 
+    0x0004f020, 0x0000f8aa, 0x0000f898, 0xd1042801, 0x8800482b, 0x0040f030, 0x4a2ad002, 0xe0282108, 
+    0x4a282104, 0xf7dc4608, 0x4923fdba, 0x80282074, 0xf8d92200, 0x39100000, 0xfed3f000, 0xe0001d01, 
+    0xd108e01a, 0x10aaf240, 0x491be01e, 0x46182200, 0xf0003910, 0x1d40fec6, 0x481bd014, 0x21042202, 
+    0xfe7bf004, 0xd0122801, 0xf7e32004, 0x4a15fe8a, 0x20042106, 0xfd93f7dc, 0x0000f8ba, 0xf47f2800, 
+    0xe5a7ae01, 0x10abf240, 0xe8bd86a0, 0x4a0d9ff0, 0xe7ee2105, 0x21012200, 0xf2afb510, 0xf0005077, 
+    0x2108fceb, 0xf0002004, 0x4908fe49, 0xbd106088, 0x00030c24, 0x000302e0, 0x0003d27c, 0x00030222, 
+    0x00030220, 0xcccc0000, 0xd0039026, 0x00030ecc, 0x4ff0e92d, 0x4605b09d, 0xf8df2400, 0xf88d9428, 
+    0x9418406c, 0x8e80941c, 0x7f5af5b0, 0xdc05d07e, 0x28d0b160, 0x28d1d016, 0xe01ed179, 0x7040f5a0, 
+    0xd0753869, 0xd07428ed, 0xd17028ee, 0xf04f49fd, 0xf8d932ff, 0x3124001c, 0xfe92f000, 0xd1081d01, 
+    0xe34e20d0, 0x220049f7, 0x001cf8d9, 0xf0003124, 0x1d41fe87, 0x2801d011, 0x48f2d1e8, 0x88003024, 
+    0xd1e32865, 0x230148f0, 0x21042202, 0xfdf7f004, 0x780048ee, 0xd0022802, 0x20d1e012, 0x48ece331, 
+    0x28017800, 0xf8dfd10c, 0xf89aa3ac, 0xb1e00000, 0xd0242801, 0xd0292802, 0xd07d2803, 0x4000f88a, 
+    0x48e52208, 0xf0040151, 0x2800fde8, 0xf8b9d075, 0x210a0008, 0xb2801c40, 0x0008f8a9, 0xf2f1fbb0, 
+    0x0012fb01, 0xd0692800, 0xf7eae1e1, 0x2001fea3, 0x0000f88a, 0x700448d9, 0x700448d9, 0xf7eae7e0, 
+    0xb108fed1, 0xe0fe2002, 0xe0fc2001, 0xfed8f7ea, 0xd0f72800, 0xfe7bf7ea, 0xf44f2100, 0xf7e33080, 
+    0x4ed0fe27, 0x4bd02000, 0xe0032200, 0xe3a8e2ea, 0xe3ebe1f7, 0x01c0eb03, 0x2200e9c1, 0x01c0eb06, 
+    0x28041c40, 0x2200e9c1, 0xf8dfdbee, 0x2700b320, 0xf7eaa819, 0x4668fe82, 0xfe8df7ea, 0xa8192600, 
+    0x0016f830, 0xfe1cf006, 0x465b2200, 0xfc4cf006, 0xeb024abc, 0x469803c6, 0xf006cb0c, 0xe9c8fb89, 
+    0x46680100, 0xeb00465b, 0x220000c6, 0x0100e9d0, 0xfc3af006, 0xeb024ab4, 0x469803c6, 0xf006cb0c, 
+    0x1c76fb77, 0xe9c82e04, 0xdbd80100, 0xf2402100, 0xf7e32000, 0xe002fddd, 0xe16fe008, 0x1c7fe0a6, 
+    0xdbc52f64, 0xf88a2103, 0xe7791000, 0xf10d2000, 0xae100c20, 0xeb062200, 0xe9c101c0, 0xeb0c2200, 
+    0x1c4001c0, 0xe9c12804, 0xdbf32200, 0xb27cf8df, 0xa8192700, 0xfe31f7ea, 0xf7ea4668, 0x2600fe3c, 
+    0xf830a819, 0xf0060016, 0x2200fdcb, 0xf006465b, 0xaa08fbfb, 0x03c6eb02, 0xcb0c4698, 0xfb38f006, 
+    0x0100e9c8, 0x465b4668, 0x00c6eb00, 0xe9d02200, 0xf0060100, 0xaa10fbe9, 0x03c6eb02, 0xcb0c4698, 
+    0xfb26f006, 0x2e041c76, 0x0100e9c8, 0x2100dbd8, 0x2000f240, 0xfd8cf7e3, 0x2f641c7f, 0x2700dbc9, 
+    0xa808463e, 0x00c6eb00, 0x2300e9d0, 0xeb00487d, 0xe9d101c6, 0x46800100, 0xf006468b, 0xf006ffed, 
+    0x2800fd1b, 0x4240da00, 0xfd73f006, 0x465b4642, 0xfbbaf006, 0x48764684, 0x2300e9d0, 0xf0064660, 
+    0xd206fecd, 0x7808496d, 0xd00128ff, 0x70081c40, 0x486d2701, 0x00c6eb00, 0x2300e9d0, 0xeb00a810, 
+    0xe9d101c6, 0xf0060100, 0x4684fb9f, 0xe9d04869, 0x46602300, 0xfeb2f006, 0x4961d206, 0x28ff7808, 
+    0x1c40d001, 0x27017008, 0x2e041c76, 0xb14fdbb9, 0xfda0f7ea, 0xf44f2100, 0xf7e33000, 0xf7eafd39, 
+    0xe6fffd86, 0xf88a2003, 0xe6d90000, 0x7800485a, 0xd17d2802, 0xf0044859, 0xb2c6fc95, 0x000ff006, 
+    0xd176280a, 0xffe7f7f5, 0x8154f8df, 0xd0372801, 0x4f524854, 0xf9903724, 0x28030000, 0x2805d042, 
+    0x2804d040, 0x2300d03e, 0x22044638, 0xf0042110, 0x484afc96, 0xf004301e, 0x4607fc75, 0x301c4847, 
+    0xfc70f004, 0x4a00ea47, 0x30224844, 0xfc6af004, 0x48424607, 0xf0043020, 0xea47fc65, 0x20034b00, 
+    0x1f16ebb0, 0xf8d9d120, 0x46501014, 0xffa9f7f5, 0x1018f8d9, 0x46584607, 0xffa3f7f5, 0xe0244438, 
+    0x406cf88d, 0xf89927fe, 0x29fe1000, 0xf899d107, 0x42860002, 0xf898d103, 0x28010000, 0xf04fd139, 
+    0xe06232ff, 0xe7bf2301, 0xebb02001, 0xd1031f16, 0x1014f8d9, 0xe0064650, 0xebb02002, 0xd1051f16, 
+    0x1018f8d9, 0xf7f54658, 0x9018ff7c, 0xe9c9a91b, 0x9818ab05, 0xff47f7f5, 0xf8994607, 0x42b00002, 
+    0xf898d142, 0x28010000, 0xf899d03e, 0xe0011000, 0xe014e04d, 0xd105428f, 0x106cf89d, 0x0001f899, 
+    0xd0064281, 0xb2714809, 0xf9909a18, 0xf7f50000, 0xf889fb81, 0xf89d7000, 0xf889106c, 0xf8891001, 
+    0xe0346002, 0x00030ed8, 0xd03c8318, 0x00030222, 0x00030300, 0x000302ec, 0xd28f2002, 0x000302ed, 
+    0x000302ee, 0x0003cd70, 0x0003cd90, 0x40590000, 0x000302f0, 0x000302f8, 0x00030342, 0xd03c80d0, 
+    0x000302dd, 0x000301dc, 0xb2719a18, 0xf99048fd, 0xf7f50000, 0xf888fb4f, 0xe7ca4000, 0x4008f8a9, 
+    0xf88921fd, 0xf8891002, 0xf8891000, 0x4ef61001, 0xf8df4ff6, 0x783083dc, 0xd0052801, 0x28016838, 
+    0xf8a9d002, 0xe01b4010, 0x0010f8b9, 0xf8a91c40, 0x07000010, 0xf003d11a, 0x7831fa58, 0x29014bed, 
+    0x681ad102, 0xda2a4290, 0x2a01683a, 0x4aead023, 0xda0b4282, 0xd0282901, 0x71fff647, 0xdd054281, 
+    0x46402300, 0x21022201, 0xfbb9f004, 0xf99048e3, 0x28030000, 0x2805d01e, 0x2804d01c, 0xf8a9d01a, 
+    0x2725400e, 0x780048de, 0xd07d2801, 0x1003f899, 0xd17a2900, 0x4adbe195, 0x42906812, 0x2301dc01, 
+    0x4ed9e7df, 0x44326836, 0x4ad8e7d2, 0x68126819, 0xe7d31a89, 0x100ef8b9, 0x1c4948d5, 0x100ef8a9, 
+    0xfb70f004, 0x06004606, 0x48d2d518, 0x28017800, 0xf7f8d005, 0x48d0f935, 0xb1387800, 0xf899e00b, 
+    0x06c0000e, 0xf7f8d10a, 0xe007f92b, 0x780048cb, 0x2001b108, 0x2000e000, 0xfbb7f7ea, 0xd50c0730, 
+    0x780048c7, 0xd1062801, 0x780048c6, 0xf899b918, 0x06c0000e, 0xf7f7d101, 0x0430ff83, 0xf8b9d515, 
+    0x464f000e, 0xd1010580, 0xfa38f7e3, 0xf0107bb8, 0xd10a0f05, 0x78384fbc, 0xf7e3b138, 0x49bbfaf5, 
+    0x703c2001, 0xf7e37008, 0x04f0fa29, 0xf899d50b, 0x0640000e, 0xf7f4d107, 0x48b5fa2b, 0xb1107800, 
+    0xf7f42000, 0x48b3fb69, 0x28017800, 0x48b2d158, 0x28017800, 0xf899d154, 0x4ab00006, 0xb2c01c40, 
+    0x0006f889, 0xe0017812, 0xe07ae077, 0xd9474290, 0x46c848ab, 0x4006f889, 0x28017800, 0x2802d027, 
+    0x48a8d025, 0xfafef004, 0x48a64607, 0xf0041c80, 0xf8d8faf9, 0xea471020, 0x4fa34000, 0x42884ba3, 
+    0x783ad005, 0x40912101, 0x4311681a, 0x78396019, 0x1c494a9f, 0x7039b2c9, 0x42917812, 0x703cd300, 
+    0xf8c82100, 0x27010020, 0x4608681b, 0x4895e010, 0xf0041f00, 0x4607fad7, 0x1e804892, 0xfa07e7d7, 
+    0xea1cfc00, 0xd0010f03, 0xb2c91c49, 0xb2c01c40, 0xd3f44290, 0x7800488f, 0xd9014281, 0x901c2001, 
+    0xd5090570, 0x000ef899, 0xd1050700, 0x1f804878, 0xfab8f004, 0xd10307c0, 0x2801981c, 0xaf21f47f, 
+    0x901c2000, 0xfee9f7fb, 0x21434883, 0x80012200, 0x48824601, 0xf0006800, 0x1d01fb14, 0xf240d108, 
+    0xe10f3068, 0x2200487d, 0x6800497b, 0xfb09f000, 0xd1e31d40, 0x3069f240, 0xf899e104, 0x464e0003, 
+    0xf899b318, 0x464e0003, 0xd0492801, 0xfbc6f7e8, 0xf04f2200, 0x71703133, 0xf7dc2001, 0x7971f9d0, 
+    0x20012200, 0xf9cbf7dc, 0x100af9b6, 0x20012200, 0xf9c5f7dc, 0x21237970, 0xf9b62800, 0xd05f000a, 
+    0xd03c2825, 0xd0452823, 0x7930e051, 0xb2c01c40, 0x28287130, 0x4862d377, 0x21202205, 0xfa8df004, 
+    0x4843b928, 0xf004384e, 0x07c0fa5d, 0x8970d010, 0xd00b2825, 0x81772105, 0xf7f7200e, 0x2300f845, 
+    0x22019400, 0x46184619, 0xff1ef7f6, 0xe05a7134, 0x20017932, 0xf7dc4953, 0x2001f992, 0xe7f570f0, 
+    0xf04f2200, 0x20013122, 0xf989f7dc, 0xf7e82003, 0x2001fb59, 0xfbbff7e8, 0x70f02002, 0x200ee043, 
+    0x21008171, 0xf820f7f7, 0x94002300, 0x46192201, 0xe00a4618, 0x81702022, 0x200e2100, 0xf814f7f7, 
+    0x94002300, 0x46192201, 0xf7f64610, 0x89b0feed, 0xb2811c40, 0x81b1481e, 0xf004384c, 0xe013fa16, 
+    0xd0022822, 0xd0032823, 0x8171e00e, 0xe0012100, 0x81772105, 0xf7f6200e, 0x2300fff7, 0x22019400, 
+    0x46184619, 0xfed0f7f6, 0xf7e82002, 0x2000fb1b, 0xfb81f7e8, 0x70f42200, 0x20011e51, 0xf93ff7dc, 
+    0xf889e001, 0x21294004, 0x22004823, 0x46018001, 0x68004825, 0xfa55f000, 0xd14e1d01, 0x4056f240, 
+    0xe050e050, 0x00030222, 0x0003028f, 0x00030298, 0xd00351da, 0x00030290, 0xffff8001, 0x000301dc, 
+    0x00030306, 0x0003029c, 0x000302a0, 0x00030294, 0xd03c80b6, 0x00030226, 0x0003031c, 0x0003025b, 
+    0x00030225, 0x00030c9c, 0x00030240, 0x00030241, 0x000302d5, 0x00030380, 0x00030266, 0x0003037f, 
+    0x00030394, 0xd0036116, 0x0003037c, 0x00030378, 0x0003037d, 0x0003037e, 0x00030efc, 0x00030c90, 
+    0xd28f2034, 0x11111110, 0x00030c14, 0x4810e7ff, 0x490e2200, 0xf0006800, 0x1d40fa04, 0xab96f47f, 
+    0x4057f240, 0xb01d86a8, 0x8ff0e8bd, 0x21012200, 0xf6afb510, 0xf0001023, 0x2108f83f, 0xf000200a, 
+    0x4902f99d, 0x61c83924, 0x0000bd10, 0x00030efc, 0x00030c14, 0xb5082008, 0xfaa5f7e3, 0x90002000, 
+    0x46032201, 0x20084601, 0xfae2f7e3, 0x20084908, 0xfaa8f7e3, 0xf7e34807, 0x2008fafe, 0xfaa7f7e3, 
+    0xf2462201, 0xe8bd11a8, 0x20034008, 0xb9bef7e3, 0x00024e54, 0xc1000184, 0xf8bcf000, 0x8e80e7fc, 
+    0xd1012800, 0xb918f005, 0x22004770, 0xf2af4611, 0xf0000011, 0x0000b801, 0x47f0e92d, 0x460e4691, 
+    0x20384682, 0xfc20f000, 0xd0440004, 0xf8df4f86, 0x6838821c, 0x2500b9d8, 0xeb05603c, 0xeb080185, 
+    0xf0000081, 0x1c6df905, 0xd3f62d02, 0x3028487f, 0xf8fef000, 0x303c487d, 0xf8faf000, 0x3050487b, 
+    0xf8f6f000, 0x30284879, 0x30146178, 0x2e0261b8, 0x2601d300, 0x86a02000, 0xa000f8c4, 0xe9c41d20, 
+    0xf000690b, 0xf104f8f0, 0xf0000018, 0x6124f8ec, 0x000af1c6, 0x61a06264, 0x68796ae0, 0xd9004288, 
+    0xeb006078, 0xeb080180, 0x1d210081, 0xf8def000, 0xe8bd2001, 0xf04f87f0, 0xe7fa30ff, 0x4d62b570, 
+    0x68a9460e, 0x6828180c, 0xf0001d00, 0x6829f8f5, 0x68a8604c, 0xd2014284, 0xe00069a8, 0x1d096968, 
+    0xf8d2f000, 0xd0062e00, 0x46306829, 0x4070e8bd, 0xf0003118, 0xbd70b8c9, 0xf000b570, 0x4d52fb2d, 
+    0x1a4068e9, 0xe02f6128, 0x0101f1a1, 0x1c406129, 0xd10360a8, 0x1005e9d5, 0x0105e9c5, 0x69684e4b, 
+    0xb1f16801, 0x68c468c0, 0x6860e01c, 0x428868a9, 0xb672d81a, 0xf0001d20, 0x6aa0f8bf, 0xf104b118, 
+    0xf0000018, 0xb662f8b9, 0x68696ae0, 0xd9004288, 0xeb006068, 0x1d210080, 0x0080eb06, 0xf886f000, 
+    0x2400e7dd, 0xd1e02c00, 0x68a86929, 0xd1cb2900, 0xbd7060e8, 0xf000b510, 0xf7fff840, 0x4932ffbd, 
+    0x68484a32, 0x2800e003, 0x1e40d01b, 0xeb006048, 0xf8520380, 0x2b003023, 0xeb00d0f5, 0xeb020080, 
+    0x68420080, 0xf1006852, 0x60420308, 0xd101429a, 0x60426852, 0x600868d0, 0x6b016802, 0x4010e8bd, 
+    0xbd104710, 0x6801b570, 0x68c0b111, 0xe00068c4, 0xf1042400, 0x46050018, 0xf86ef000, 0x4629481b, 
+    0xf0003050, 0x4918f843, 0x68096ae0, 0x42886ac9, 0x2001d301, 0x2000bd70, 0xe92dbd70, 0x4d1341f0, 
+    0x4f124e11, 0xe01a3550, 0x6828b672, 0x68e8b110, 0xe00068c4, 0xf1042400, 0xf0000018, 0xb662f84d, 
+    0xf0001d20, 0x6ae0f849, 0x42886871, 0x6070d900, 0x0080eb00, 0xeb071d21, 0xf0000080, 0x6828f817, 
+    0xd1e12800, 0x81f0e8bd, 0x00030f04, 0x0003d288, 0x32fff04f, 0x0108f100, 0x1201e9c0, 0x610160c1, 
+    0x60012100, 0x21004770, 0x47706101, 0x68536842, 0x6843604b, 0x6853608b, 0x60516099, 0x61086041, 
+    0x1c496801, 0x47706001, 0x680bb510, 0xd0021c5a, 0x0208f100, 0x6902e002, 0x6852e004, 0x68246854, 
+    0xd9fa429c, 0x604b6853, 0x608a6099, 0x61086051, 0x1c496801, 0xbd106001, 0x1201e9d0, 0xe9d0608a, 
+    0x60511201, 0x684a6901, 0xd1014282, 0x604a6882, 0x61022200, 0x1e406808, 0x47706008, 0x0005b570, 
+    0xd028460e, 0xf000204c, 0x0004fabf, 0xfb05d023, 0x1c40f006, 0xfab8f000, 0xb1c86020, 0x0106fb05, 
+    0x21006061, 0x1e6963a1, 0xfb0160a0, 0x63e50006, 0xf04f60e0, 0xe9c430ff, 0x64a06010, 0x0010f104, 
+    0xff96f7ff, 0x0024f104, 0xff92f7ff, 0xbd704620, 0xf0004620, 0x2000faa5, 0xb510bd70, 0x6c024613, 
+    0xb16a4604, 0x68e0b183, 0xe984f003, 0x6c2068e1, 0x60e11a09, 0x42916822, 0x6861d202, 0x60e01a08, 
+    0x1c406ba0, 0xbd1063a0, 0xf00368a0, 0x6c21e974, 0x440868a0, 0x686160a0, 0xd3f14288, 0x60a06820, 
+    0xb570e7ee, 0x460e4615, 0xb6724604, 0xf875f000, 0xb145b160, 0x0110f104, 0xf7ff4628, 0xb662fe8f, 
+    0x0003f06f, 0xb662bd70, 0xbd702000, 0xbf00b662, 0x6ba0b672, 0x42886be1, 0x2200d20e, 0x46204631, 
+    0xffbbf7ff, 0x25016a60, 0xf104b138, 0xf7ff0024, 0xb110fef9, 0xe0001fad, 0xb6622500, 0xbd704628, 
+    0x460bb570, 0xb6724604, 0xb1f06b80, 0xbf00b662, 0x6ba0b672, 0x6c22b330, 0x441068e0, 0x686160e0, 
+    0xd3014288, 0x60e06820, 0x1e406ba0, 0x68e163a0, 0xf0034618, 0x6920e920, 0xb1a02501, 0x0010f104, 
+    0xfed0f7ff, 0x1fadb178, 0xb142e00d, 0x0124f104, 0xf7ff4610, 0xb662fe43, 0x0003f06f, 0xb662bd70, 
+    0xbd702000, 0xb6622500, 0xbd704628, 0x4604b570, 0x46156b80, 0x42906be2, 0x2200d20d, 0xf7ff4620, 
+    0xb945ff6c, 0xb1306a60, 0x0024f104, 0xfeaaf7ff, 0x2001b108, 0x4628bd70, 0xb510bd70, 0xf0004604, 
+    0x6ba0fa54, 0x42886be1, 0x2401d101, 0x2400e000, 0xfa51f000, 0xbd104620, 0x680148ed, 0x6800b111, 
+    0x47706b00, 0x47702000, 0x5ff0e92d, 0x4615469a, 0x46834689, 0xe9dd2058, 0xf000680a, 0x0004f9d5, 
+    0x00afd009, 0xf0004638, 0x6320f9cf, 0x22a5b3d8, 0xf0034639, 0x2c00f935, 0x6b21d07e, 0x0003f06f, 
+    0x0085eb00, 0x44084635, 0xf0204649, 0x22200707, 0x0034f104, 0xe92cf003, 0xf8842000, 0x2d0a0053, 
+    0x2509d300, 0x1d2062e5, 0xfeadf7ff, 0x0018f104, 0xfea9f7ff, 0xf1c56124, 0x6264010a, 0x46384652, 
+    0x465961a1, 0xf9baf000, 0xf0006020, 0x4fc8f9fe, 0x1c4068b8, 0x68b860b8, 0x9318f8df, 0xd0082801, 
+    0xb35069b8, 0xe7ffe02e, 0xf0004620, 0x2400f999, 0x603ce7c1, 0xeb052500, 0xeb090185, 0xf7ff0081, 
+    0x1c6dfe77, 0xd3f62d0a, 0x30c848ba, 0xfe70f7ff, 0x30dc48b8, 0xfe6cf7ff, 0x30f048b6, 0xfe68f7ff, 
+    0xf7ff48b5, 0x48b4fe65, 0xf7ff3014, 0x48b2fe61, 0x63b8383c, 0x63f83014, 0x6838e004, 0x42b06ac0, 
+    0x603cd800, 0x69396ae0, 0xd9004288, 0x6af96138, 0x1c496561, 0x697962f9, 0xd9004288, 0xeb006178, 
+    0xeb090180, 0x1d210081, 0xfe50f7ff, 0xf0002501, 0xf1b8f9b2, 0xe0000f00, 0xd001e00c, 0x4000f8c8, 
+    0xb12069b8, 0x6ac06838, 0xd20042b0, 0x4628df00, 0x9ff0e8bd, 0x35fff04f, 0xb570e7f9, 0x69e84d94, 
+    0x6a28b118, 0x62281c40, 0x68e8bd70, 0x60e81c40, 0xb93068e8, 0x6be96ba8, 0x63e863a9, 0x1c406aa8, 
+    0x4e8c62a8, 0x6860e018, 0x428868e9, 0x1d20d8ec, 0xfe42f7ff, 0xb1186aa0, 0x0018f104, 0xfe3cf7ff, 
+    0x69696ae0, 0xd9004288, 0xeb006168, 0x1d210080, 0x0080eb06, 0xfe0af7ff, 0x68006ba8, 0x6ba8b118, 
+    0x68c468c0, 0x2400e000, 0xd1dc2c00, 0xe92dbd70, 0x270047f0, 0xf959f000, 0x69f04e75, 0x61f01e40, 
+    0xbb7869f0, 0xb36868b0, 0x81ccf8df, 0xf8df2500, 0xf1a891c4, 0xe0180814, 0x0018f104, 0xfe0cf7ff, 
+    0xf7ff1d20, 0x6ae0fe09, 0x42886971, 0x6170d900, 0x0180eb00, 0x0081eb09, 0xf7ff1d21, 0x6ae0fdd7, 
+    0x6ac96831, 0xd3004288, 0xf8d82501, 0x46401000, 0x68c0b111, 0xe00068c4, 0x2c002400, 0x6a30d1dc, 
+    0xe008b930, 0xf7ffe00f, 0x6a30ff88, 0x62301e40, 0x28006a30, 0xb915d1f7, 0x28016a70, 0x2701d103, 
+    0x62702000, 0xf000df00, 0x4638f916, 0x87f0e8bd, 0x69c1484f, 0x61c11c49, 0xf0004770, 0xdf00f870, 
+    0xfc6af7ff, 0xb51fe7f9, 0x484e2400, 0x4623a14b, 0x2200f240, 0x94019400, 0x94039402, 0xfeb4f7ff, 
+    0xd1082801, 0x2101b672, 0x61814841, 0xe8bd60c4, 0xf000401f, 0xbd1fb8e3, 0xf000b510, 0x483cf8e6, 
+    0xf00068c4, 0x4620f8e8, 0x4939bd10, 0x4a3969c8, 0x2001b120, 0x47706248, 0x61481e40, 0xeb006948, 
+    0xf8520080, 0x28000020, 0xd0f56948, 0x0080eb00, 0x0080eb02, 0x68526842, 0x0308f100, 0x429a6042, 
+    0x6852d101, 0x68d06042, 0x6b086008, 0xd0e22800, 0x6b4a6808, 0x42906d40, 0x6c08d0dd, 0x30086c8a, 
+    0xd20f4290, 0x6d406808, 0x68c86348, 0x60106c0a, 0x1d006c08, 0x6c0a6408, 0x60106b48, 0x1d006c08, 
+    0x47706408, 0x63082000, 0xb5104770, 0x6b004604, 0xf846f000, 0xe8bd4620, 0xf0004010, 0xb570b841, 
+    0x68684d13, 0xd0222800, 0xff82f7ff, 0x68304e12, 0x2400b158, 0xff2bf7ff, 0xd1182c00, 0xf885f000, 
+    0xb1206830, 0x68c468f0, 0x2401e002, 0x2400e7f2, 0xf7ff1d20, 0x68a8fd41, 0x60a81e40, 0x1e406868, 
+    0xf0006068, 0x4620f878, 0x4070e8bd, 0xbd70e7cd, 0x00030f20, 0x0003d2ec, 0x0003d3f0, 0x454c4449, 
+    0x00000000, 0x00024c1b, 0x4604b510, 0xff50f7ff, 0xf0024620, 0x4604fe37, 0xfef9f7ff, 0xbd104620, 
+    0x0004b510, 0xf7ffd008, 0x4620ff43, 0xfe59f002, 0x4010e8bd, 0xbeebf7ff, 0x0000bd10, 0x60011d09, 
+    0xf04f1f01, 0x600b33aa, 0xf04f1f09, 0x60083312, 0x600b1f09, 0xf04f1f09, 0x600b3311, 0xf04f1f09, 
+    0x600b3310, 0xf04f1f09, 0x600b3309, 0xf04f1f09, 0x600b3308, 0xf04f1f09, 0x600b3307, 0xf04f1f09, 
+    0x600b3306, 0xf04f1f09, 0x600b3305, 0xf04f1f09, 0x600b3304, 0xf04f1f09, 0x600b3303, 0xf04f1f09, 
+    0x600b3302, 0x105b1f09, 0x1f09600b, 0x1f09600a, 0x600a223f, 0xf8402100, 0x47701d44, 0xf7ffb510, 
+    0xf003fb49, 0x2000ecf4, 0xb672bd10, 0x68414808, 0x60411c49, 0x48064770, 0x29006841, 0x6841d006, 
+    0x60411e49, 0x28006840, 0xb662d100, 0x00004770, 0x00030f6c, 0xe92d503f, 0xe59f0068, 0xfa000e50, 
+    0xfbffff24, 0xe59f4060, 0xe1d400b0, 0xe2800001, 0xe6ff0070, 0xe1c400b0, 0xe3500b01, 0x3a00000c, 
+    0xe2841008, 0xe3a00065, 0xe3a02000, 0xe1c100b0, 0xe59f0038, 0xe5900000, 0xfafffeab, 0xe59f1030, 
+    0xe5912000, 0xe0800002, 0xe5810000, 0xe3a00000, 0xe1c400b0, 0xe59f001c, 0xfbff8b05, 0xf57ff05f, 
+    0xe8bd503f, 0xe25ef004, 0xd03c824a, 0x00030f6c, 0x00030ef4, 0x000301d4, 0xc1000184, 0x21012300, 
+    0xb510461a, 0xf00348fe, 0x48fdfc7a, 0x220e2300, 0x0100f244, 0x4010e8bd, 0xf0033010, 0xe92dbc70, 
+    0x48f75ff0, 0x011af24a, 0xf003301e, 0x48f4fc4e, 0x3100f240, 0xf0033020, 0x4cf2fc48, 0x01eff243, 
+    0x302248ef, 0xf0037822, 0x48edfc40, 0x3184f249, 0xf0033026, 0x48eafc3a, 0x30282100, 0xfc35f003, 
+    0xf24448e7, 0x302c0100, 0xfc2ff003, 0xf24348e4, 0x302e0100, 0xfc29f003, 0xf2417820, 0x4ce01115, 
+    0x2712f241, 0x1ca53430, 0x1d264620, 0xfc1df003, 0x46284639, 0xfc19f003, 0x46302113, 0xfc15f003, 
+    0x21001da7, 0xf0034638, 0xf105fc10, 0xf2470806, 0x46404121, 0xfc09f003, 0x0906f106, 0x46482100, 
+    0xfc03f003, 0x0b06f107, 0x0a00f241, 0x46584651, 0xfbfbf003, 0x0006f108, 0x2100f64a, 0xfbf5f003, 
+    0xf24448c7, 0x304e01ff, 0xfbeff003, 0x46511fa0, 0xfbebf003, 0x1fa02100, 0xfbe7f003, 0x46202100, 
+    0xfbe3f003, 0x46282100, 0xfbdff003, 0x46302100, 0xfbdbf003, 0x46382100, 0xfbd7f003, 0x46402100, 
+    0xfbd3f003, 0x46482100, 0xfbcff003, 0x46582100, 0xfbcbf003, 0xf1082100, 0xf0030006, 0x48b0fbc6, 
+    0x304e2100, 0xfbc1f003, 0x412df643, 0xf0034620, 0xf642fbbc, 0x46281128, 0xfbb7f003, 0x46302174, 
+    0xfbb3f003, 0xf24848a6, 0x304e0107, 0xfbadf003, 0x46511fa0, 0xfba9f003, 0x1fa02100, 0xfba5f003, 
+    0x46202100, 0xfba1f003, 0x46282100, 0xfb9df003, 0x46302100, 0xfb99f003, 0x21004899, 0xf003304e, 
+    0x2103fb94, 0xf0034620, 0xf240fb90, 0x46285140, 0xfb8bf003, 0x6140f640, 0xf0034630, 0xf640fb86, 
+    0x46380141, 0xfb81f003, 0x3144f241, 0xf0034640, 0xf108fb7c, 0xf2450006, 0xf003011c, 0x2140fb76, 
+    0x0006f109, 0xfb71f003, 0x0006f10b, 0x113bf645, 0xfb6bf003, 0xf2404882, 0x30444100, 0xfb65f003, 
+    0x1fa021d0, 0x5ff0e8bd, 0xbb5ff003, 0x5ff0e92d, 0xf24a487b, 0x301e011a, 0xfb57f003, 0xf2404878, 
+    0x30203100, 0xfb51f003, 0x21ef4875, 0xf0033022, 0x4873fb4c, 0x3104f241, 0xf0033026, 0x4870fb46, 
+    0x1180f240, 0xf0033028, 0x486dfb40, 0x0100f244, 0xf003302c, 0x486afb3a, 0x0100f243, 0xf003302e, 
+    0x4c67fb34, 0x1105f240, 0x46203430, 0xfb2df003, 0xf2401ca5, 0x46282102, 0xfb27f003, 0x0904f104, 
+    0x4648210f, 0xfb21f003, 0x0a06f104, 0x5100f240, 0xf0034650, 0xf105fb1a, 0xf2470b06, 0x4658318e, 
+    0xfb13f003, 0x0606f109, 0x0800f241, 0x46304641, 0xfb0bf003, 0x46411cb7, 0xf0034638, 0x1d30fb06, 
+    0x2100f64a, 0xfb01f003, 0xf244484d, 0x304e01ff, 0xfafbf003, 0x46411fa0, 0xfaf7f003, 0x1fa02100, 
+    0xfaf3f003, 0x46202100, 0xfaeff003, 0x46282100, 0xfaebf003, 0x46482100, 0xfae7f003, 0x46502100, 
+    0xfae3f003, 0x46582100, 0xfadff003, 0x46302100, 0xfadbf003, 0x46382100, 0xfad7f003, 0x1d302100, 
+    0xfad3f003, 0x21004836, 0xf003304e, 0xf243face, 0x46205114, 0xfac9f003, 0x1130f243, 0xf0034628, 
+    0x210bfac4, 0xf0034648, 0x2106fac0, 0xf0034630, 0x482bfabc, 0x0127f248, 0xf003304e, 0x1fa0fab6, 
+    0xf0034641, 0x2100fab2, 0xf0031fa0, 0x2100faae, 0xf0034620, 0x2100faaa, 0xf0034628, 0x2100faa6, 
+    0xf0034648, 0x2100faa2, 0xf0034658, 0x2100fa9e, 0xf0034630, 0x2100fa9a, 0xf0031d30, 0x1dbefa96, 
+    0x46302100, 0xfa91f003, 0x21004815, 0xf003304e, 0x2101fa8c, 0xf0034620, 0xf240fa88, 0x46285140, 
+    0xfa83f003, 0x6140f640, 0xf0034648, 0xf640fa7e, 0x46500141, 0xfa79f003, 0x3144f241, 0xf0034658, 
+    0x1f30fa74, 0x0114f248, 0xfa6ff003, 0xf2481eb0, 0xf0037160, 0xf644fa6a, 0x46303133, 0x0000e004, 
+    0xd0039800, 0x00030360, 0xfa5ff003, 0xf2401cb0, 0xf0034100, 0x21d0fa5a, 0xe8bd1fa0, 0xf0035ff0, 
+    0xe92dba54, 0x48fb4ff0, 0xaf03b09d, 0xe887c84e, 0xc84e004e, 0xe887af07, 0xc84e004e, 0xe887af0b, 
+    0xc80f004e, 0xe886ae0f, 0x2002000f, 0xfa6af7e8, 0xf7e72001, 0x48f0fc1a, 0xf0032100, 0x48effa36, 
+    0xfa30f003, 0x21014eee, 0xf0034630, 0x49edfa2e, 0xb1107808, 0xfecaf7ff, 0xf7ffe001, 0x48e8fdd0, 
+    0x220a2300, 0x4100f240, 0xf0033010, 0x4fe4fa38, 0x220c2301, 0x0319372e, 0xf0034638, 0x2301fa30, 
+    0x220d4638, 0xf0030359, 0x48dffa2a, 0x71fff647, 0xfa0bf003, 0x46302301, 0x46192200, 0xfa1ff003, 
+    0x46302301, 0x461a2102, 0xfa19f003, 0x46304ed7, 0xf9f8f003, 0x800849d6, 0x1140f240, 0xf0034630, 
+    0x2000f9f4, 0x22029000, 0x46014603, 0xfebcf7f5, 0x230148d0, 0x21042202, 0xfa01f003, 0x230148ce, 
+    0x21042202, 0xf9fbf003, 0x4fcc2301, 0x025e2209, 0x46314638, 0xf9f3f003, 0x22002301, 0x1db84619, 
+    0xf9edf003, 0x0800f248, 0x46412300, 0x1cb8220f, 0xf9e5f003, 0x46412301, 0x4638220f, 0xf9dff003, 
+    0x23014fbf, 0x46312209, 0xf0034638, 0x2301f9d8, 0x46192200, 0xf0031db8, 0x2300f9d2, 0x220f4641, 
+    0xf0031cb8, 0x2301f9cc, 0x220f4641, 0xf0034638, 0x4fb4f9c6, 0x22092301, 0x46384631, 0xf9bff003, 
+    0x22002301, 0x1db84619, 0xf9b9f003, 0x46412300, 0x1cb8220f, 0xf9b3f003, 0x46412301, 0x4638220f, 
+    0xf9adf003, 0x4ea84631, 0x22092301, 0xf0034630, 0x2301f9a6, 0x46192200, 0xf0031db0, 0x2300f9a0, 
+    0x220f4641, 0xf0031cb0, 0x2301f99a, 0x220f4641, 0xf0034630, 0x4e94f994, 0x22002301, 0x3e104619, 
+    0xf0034630, 0x2300f98c, 0x21014630, 0xf003461a, 0x4e89f986, 0x22032300, 0x21083e0c, 0xf0034630, 
+    0x4f92f97e, 0x0080f44f, 0xf7e27839, 0x2301f9f1, 0x22034630, 0xf0032108, 0x4880f972, 0xf0033838, 
+    0xb2c0f951, 0xd00e28e4, 0x90002003, 0x22012302, 0x48872100, 0xfa24f7e9, 0x0901f04f, 0x0a64f10d, 
+    0xae1b46c8, 0x2000e012, 0x23019000, 0x21032202, 0xd10be7ef, 0x2801b2a0, 0x0c20d108, 0xd1052801, 
+    0x2801b2a8, 0x0c28d102, 0xd07b2801, 0x78014879, 0x0000f249, 0x3041ea40, 0x4869b281, 0xf0033010, 
+    0x4f72f924, 0x0b80f44f, 0x78394658, 0xf9b0f7e2, 0x46587839, 0xf9acf7e2, 0x30124861, 0xf912f003, 
+    0xe1acf8df, 0x0b4cf10d, 0xf3c00b02, 0xf3c02103, 0xf99e1703, 0xf1b93003, 0xf82b0f01, 0xf99e2013, 
+    0xf82b2002, 0xf99e1012, 0xf82b1001, 0xf0007011, 0xf99e070f, 0xf82b0000, 0xd0087010, 0x0f02f1b9, 
+    0xfa1fd027, 0xf1bcfc84, 0xd05a0f00, 0xf10de06a, 0xf83b0c04, 0xf82ce013, 0xf83be013, 0xf82ce012, 
+    0xf83be012, 0xf82ce011, 0xf82ce011, 0x27007010, 0x7010f826, 0x7011f826, 0x040ff367, 0x050ff367, 
+    0x7012f826, 0x441ff367, 0x451ff367, 0x7013f826, 0xf10de0a8, 0xf83c0c04, 0x45bee010, 0xf826d104, 
+    0xf3687010, 0xe001040f, 0x7010f82a, 0x7011f83c, 0xf83b46de, 0x42870011, 0xf368d105, 0xf826441f, 
+    0xe0020011, 0xf82ae096, 0xf83c0011, 0x46717012, 0x0012f83e, 0xd1044287, 0x0012f826, 0x050ff368, 
+    0xf82ae001, 0xf83c0012, 0xf8312013, 0x42820013, 0xf368d104, 0xf826451f, 0xe0730013, 0x0013f82a, 
+    0xf83ae070, 0x4567c010, 0xf10dd005, 0xf83c0c04, 0x4567c010, 0xf826d104, 0xf3687010, 0xe001040f, 
+    0xc010f826, 0xd1110c20, 0x0011f83b, 0x7011f83a, 0xd00442b8, 0xf837af01, 0x42b87011, 0xf368d104, 
+    0xf826441f, 0xe0010011, 0x7011f826, 0x0c000428, 0xf83bd134, 0xf83a0012, 0x42881012, 0xa901d004, 
+    0x1012f831, 0xd1274288, 0x0012f826, 0x050ff368, 0x0000e024, 0x0002b7e0, 0xd003900c, 0xd03c804a, 
+    0xd0039800, 0x00030362, 0xd03c8310, 0xd28fffc0, 0x00030f7c, 0xd003c810, 0xd003d810, 0xd003c286, 
+    0xd003ca86, 0xd003d286, 0xd003da86, 0x00030223, 0x00030338, 0x00030360, 0x1012f826, 0xd1110c28, 
+    0x0013f83b, 0x1013f83a, 0xd0044288, 0xf831a901, 0x42881013, 0xf368d104, 0xf826451f, 0xe0010013, 
+    0x1013f826, 0x0001f109, 0x09fff000, 0x0f03f1b9, 0xaedff67f, 0x0000f04f, 0xf836465d, 0xf8251010, 
+    0xf1001010, 0xb2c00001, 0xd9f62803, 0x82fcf8df, 0x4fbf2400, 0xeb08ae15, 0xf0030044, 0xf1c4f803, 
+    0x1c640103, 0x5679b2e4, 0xf8262c03, 0xd9f20011, 0x46a92400, 0xaf1746b8, 0x5004f918, 0x0015f839, 
+    0xd0422802, 0xd0402803, 0xd03e2804, 0x0015f836, 0xfd86f005, 0xf851a90b, 0xf0051025, 0xa90ffd95, 
+    0x1025f851, 0xfbfef005, 0xfd42f005, 0xb2e41c64, 0xf8272c03, 0xd9df0015, 0x24004da6, 0xf04f4ea6, 
+    0xf8370864, 0x78281014, 0xfbb1b108, 0xeb06f1f8, 0xf0020044, 0x1c64ffca, 0x2c03b2e4, 0xf8bdd9f1, 
+    0xf8bd104c, 0xf8bd0052, 0xea402050, 0xf8bd3001, 0x0209104e, 0x1102ea41, 0xb2814308, 0x1e804896, 
+    0xffb3f002, 0xe8bdb01d, 0xf8368ff0, 0xf0050015, 0xa903fd47, 0x1025f851, 0xfd56f005, 0xe7bfa907, 
+    0x47f0e92d, 0x8e804604, 0x8230f8df, 0x5602f240, 0x42b04d8b, 0x5102f2a0, 0x47cff240, 0xdc17d073, 
+    0xf2a042b8, 0xd03741cf, 0xb300dc0d, 0xd1311c48, 0x22006868, 0x0108f105, 0xf822f7ff, 0xd0281d41, 
+    0xd11a2801, 0x2925e028, 0x2926d07e, 0xe014d122, 0xd012290d, 0x2901dc0c, 0x290cd00f, 0x4978d11a, 
+    0x68682200, 0xf7fe3108, 0x1d40ffdc, 0xe004d06d, 0xd06b292a, 0xd10d292b, 0x4971e0b8, 0x32fff04f, 
+    0x31086868, 0xfffcf7fe, 0xd1d71d01, 0x40cef240, 0x86a7e0bc, 0x87f0e8bd, 0xf04f4b69, 0xf04f52c0, 
+    0x33085000, 0x1000f9b3, 0xd02d2966, 0xd05e2968, 0xd07a2969, 0xd1e02967, 0xf7da4699, 0x485bfe90, 
+    0x21012300, 0x3814461a, 0xff59f002, 0x2000495d, 0x22002301, 0x485c7008, 0xf0218801, 0x80010110, 
+    0x4619485a, 0xff4bf002, 0xfabaf7e9, 0xf8a92107, 0x49531000, 0xf8d82200, 0x31080000, 0xff91f7fe, 
+    0xd0671d01, 0xe045e070, 0xf7da4699, 0xf8dffe68, 0x4650a140, 0xff16f002, 0xb2811c40, 0xf0024650, 
+    0x2004ff14, 0xf864f7e2, 0x7801484a, 0x2000f44f, 0xff9ef7e1, 0xf8a92168, 0x49411000, 0x68682200, 
+    0xf7fe3108, 0xe002ff6e, 0xe040e006, 0x1d01e045, 0xf240d108, 0xe05940f4, 0x22004939, 0x31086868, 
+    0xff5ff7fe, 0xd1881d40, 0x40f5f240, 0x4699e04e, 0xfe35f7da, 0xfc95f7ff, 0xf8a92169, 0x49301000, 
+    0x68682200, 0xf7fe3108, 0x1d01ff4c, 0x86a6d108, 0xe00ae780, 0x2200492a, 0x31086868, 0xff41f7fe, 
+    0xd1881d40, 0x5003f240, 0x4699e030, 0xfe17f7da, 0xf8a92167, 0x49221000, 0x68682200, 0xf7fe3108, 
+    0x1d01ff30, 0xaf51f47f, 0x500ef240, 0xf240e01e, 0xe01b500f, 0x502cf240, 0x4919e018, 0xf8d82200, 
+    0x31080000, 0xff1df7fe, 0xd00d1d40, 0xff7bf7e8, 0x48198829, 0xfea9f002, 0x23004818, 0xf640220b, 
+    0xf0020100, 0xe738febc, 0x502df240, 0xe74186a0, 0x21012200, 0xf2afb510, 0xf7fe2017, 0x2108fd4d, 
+    0xf7fe2002, 0x4906feab, 0xbd106048, 0xd0039814, 0x00030338, 0x00030361, 0xd003512e, 0x000304ec, 
+    0x00030f7c, 0x00030242, 0x00030220, 0xd28f20e0, 0xd0039ffe, 0x00030223, 0xd28fffc0, 0xd03c800c, 
+    0xb5104861, 0xfe6ef002, 0xd2082803, 0xb2c0495f, 0x0020f851, 0x46014780, 0x3816485b, 0x485ae003, 
+    0x1122f241, 0xe8bd3814, 0xf0024010, 0xe92dbe5e, 0x4d5641f0, 0x8e804604, 0xb1201f2d, 0xd00c288c, 
+    0xd129288d, 0x4952e012, 0x32fff04f, 0xf7fe6828, 0x1d01fee7, 0x208cd106, 0x494de01d, 0x68282200, 
+    0xfedef7fe, 0xd0151d41, 0xd1ec2801, 0xf44f4e48, 0xf04f1700, 0x46384220, 0x1000f9b6, 0xfd7ff7da, 
+    0x286f8830, 0x2100d00a, 0xf04f4638, 0xf7da52d0, 0xe7d8fd76, 0x86a0208d, 0x81f0e8bd, 0x28016870, 
+    0x4839d1d1, 0x38162102, 0xfe1ff002, 0xffa8f7ff, 0x2200e7c9, 0xb5102101, 0x008df2af, 0xfcccf7fe, 
+    0x2004210c, 0xfe2af7fe, 0x1f094930, 0xbd106008, 0x4c2db510, 0x3c1cb281, 0xf0024620, 0x2100fe06, 
+    0xf0024620, 0x1ca4fe02, 0x71fff64f, 0xf0024620, 0x4620fdfc, 0x4010e8bd, 0xf0022100, 0x4822bdf6, 
+    0x38202101, 0xbdf1f002, 0x2100481f, 0x3818b510, 0xfdebf002, 0x2104481c, 0x4010e8bd, 0xf0023816, 
+    0xb510bde4, 0x48184604, 0xf0023812, 0x4816fdde, 0x38184621, 0xfdd9f002, 0x23014813, 0x46192200, 
+    0x4010e8bd, 0xf0023824, 0x2100bdea, 0x52d0f04f, 0x1000f44f, 0xf7dab510, 0x2004fd12, 0x2102bd10, 
+    0x52d0f04f, 0xb5100508, 0xfd09f7da, 0x1d804806, 0xfdb8f002, 0xfbc1f001, 0x4803b281, 0xf0023814, 
+    0x2004fdb4, 0x0000bd10, 0xd03d1030, 0x00030f90, 0x0003d44c, 0xb108b510, 0x1080f44f, 0x23014cfb, 
+    0x22054420, 0x21204604, 0xfdb9f002, 0x46202301, 0x21402206, 0xfdb3f002, 0xe8bd2100, 0x20044010, 
+    0xbe26f7e1, 0xb108b510, 0x1080f44f, 0x23014cef, 0x4420347e, 0x46042204, 0xf0022110, 0x2303fda0, 
+    0x22024620, 0xf002210c, 0x2302fd9a, 0x22004620, 0x4010e8bd, 0xf0022103, 0xb510bd92, 0xf44fb108, 
+    0x4ce21080, 0x44202301, 0x46042202, 0xf0022104, 0x2301fd86, 0x21024620, 0xf002461a, 0x2301fd80, 
+    0x22004620, 0xf0024619, 0x2100fd7a, 0x4010e8bd, 0xf7e12004, 0xb5f8bded, 0xd0532800, 0x1480f44f, 
+    0x90002000, 0x48d14602, 0x44202301, 0xf0024619, 0x48cffd66, 0x21012300, 0x4420461a, 0xf0024605, 
+    0x48ccfd5e, 0x20047801, 0xfdd2f7e1, 0x46282301, 0x46192200, 0xfd53f002, 0x220048c5, 0x13f4f240, 
+    0x31fff240, 0x44201d80, 0xf0024606, 0x4fc2fd48, 0x31bcf64b, 0xf0024638, 0x4dc0fd28, 0x9000200a, 
+    0x462a2102, 0xf7e14668, 0x2801fe2d, 0x4620d007, 0xfc2af001, 0xf0014620, 0x2800fcf2, 0x48b8d0f0, 
+    0x22042301, 0x44202110, 0xfd29f002, 0x46302301, 0x03d9220f, 0xfd23f002, 0x0000f44f, 0x48b19000, 
+    0xe0084404, 0xe7ab2400, 0x462a2103, 0xf7e14668, 0x2801fe09, 0x2207d006, 0x21804620, 0xfd1df002, 
+    0xd0f12800, 0x31bdf64b, 0xf0024638, 0xbdf8fcee, 0x4da1b570, 0x31b6f64b, 0xf0024628, 0x4ea2fce6, 
+    0x21012200, 0xf0024630, 0x4ca0fd08, 0x2000b968, 0xff81f7ff, 0x28017820, 0xf7ffd101, 0x2301ff7c, 
+    0x22004630, 0xf0024619, 0xf64bfcea, 0x462831b7, 0xfccbf002, 0xf7ff2000, 0x2000ff50, 0xff32f7ff, 
+    0xf7ff2000, 0x7820ff17, 0xd1082801, 0xff45f7ff, 0xf7ff2001, 0xe8bdff27, 0x20014070, 0xbd70e70a, 
+    0x47f0e92d, 0x488a4604, 0x0700f24f, 0x46394420, 0x46052304, 0xf002220c, 0x2308fcc2, 0x113e4628, 
+    0x4631461a, 0xfcbbf002, 0x46282308, 0x21f02204, 0xfcb5f002, 0x2309487e, 0x4639220c, 0x44201c80, 
+    0xf0024605, 0x2309fcac, 0x22084631, 0xf0024628, 0x2304fca6, 0x21f04628, 0xf002461a, 0x2300fca0, 
+    0x210f4628, 0xf002461a, 0x4871fc9a, 0x79fff643, 0x46492319, 0x220030d2, 0xf0024420, 0x486cfc90, 
+    0x7afff641, 0x46512306, 0x220030d4, 0xf0024420, 0x4867fc86, 0x7600f64f, 0x46312301, 0x442030d6, 
+    0x46052208, 0xfc7bf002, 0x46282300, 0x461a21ff, 0xfc75f002, 0x2300485e, 0x461a213f, 0x442030d8, 
+    0xfc6df002, 0xf240485a, 0x230518ff, 0x30624641, 0x44202200, 0xfc63f002, 0x237d4855, 0x46492200, 
+    0x442030c8, 0xfc5bf002, 0x231f4851, 0x46512200, 0x442030ce, 0xf0024605, 0x484dfc52, 0x22082301, 
+    0x30ca4631, 0x46064420, 0xfc49f002, 0x46302300, 0x461a21ff, 0xfc43f002, 0xf24e4845, 0x23000600, 
+    0x30d04631, 0x220d4420, 0xf0024607, 0x2300fc38, 0x220d4631, 0xf0024628, 0x483dfc32, 0x22002332, 
+    0x30cc4649, 0xf0024420, 0x2331fc2a, 0x22004651, 0xf0024638, 0x4836fc24, 0x2200231f, 0x30604641, 
+    0xe8bd4420, 0xf00247f0, 0xe92dbc1a, 0x46044ff8, 0x460f4829, 0x0800f04f, 0xf0023880, 0x2c03fbf3, 
+    0x2c05d008, 0x2c04d009, 0x2c02d007, 0x2c01d008, 0xe016d006, 0xd4140480, 0x0480e04e, 0xe00ed408, 
+    0x48240481, 0xd5067800, 0xd1012801, 0xd0082c02, 0x0802f04f, 0x2801e005, 0x2c02d101, 0xf04fd03c, 
+    0x4a130803, 0xf2484812, 0x326c0100, 0x9200443a, 0x38724a0f, 0x3a7a183c, 0xf1b818bd, 0xd02e0f00, 
+    0xeb071e80, 0x1f920b00, 0xeb071e80, 0x1c900a00, 0xf1b818be, 0xeb070f01, 0xd03d0900, 0x0f02f1b8, 
+    0xf1b8d07e, 0xd17c0f03, 0x0000e0c4, 0xd2054004, 0xd203a1e2, 0x00030223, 0xd03c80b8, 0xd003517e, 
+    0xd203a404, 0xd203a01a, 0xd0034010, 0x00030302, 0xd2052402, 0x000302a5, 0x0801f04f, 0x2300e7c1, 
+    0x220f4620, 0xfbabf002, 0x230a9800, 0x210f2200, 0xfba5f002, 0xf2402300, 0x22083100, 0xf0024628, 
+    0x2301fb9e, 0x220e4628, 0xf0020399, 0x220cfb98, 0x23024628, 0xe0670291, 0x46202301, 0xf002220f, 
+    0x23cefb8e, 0x71f0f643, 0x46202204, 0xfb87f002, 0x46202301, 0x21032200, 0xfb81f002, 0x46582100, 
+    0xfb63f002, 0x0800f244, 0x23004620, 0x220e4641, 0xfb75f002, 0x46202300, 0x21082203, 0xfb6ff002, 
+    0x46202300, 0x21042202, 0xfb69f002, 0x46412301, 0x4628220e, 0xfb63f002, 0x4628220c, 0x02912302, 
+    0xfb5df002, 0xf2402300, 0x22083100, 0xf0024628, 0x2300fb56, 0x22064630, 0xf0022140, 0xe001fb50, 
+    0xe0abe025, 0x46302300, 0x21802207, 0xfb47f002, 0x46502300, 0x21202205, 0xfb41f002, 0x46302303, 
+    0x21302204, 0xfb3bf002, 0x46302301, 0x21082203, 0xfb35f002, 0x46482306, 0x211e2201, 0xfb2ff002, 
+    0x46482301, 0x46192200, 0xfb29f002, 0x2300e086, 0x220f4620, 0xfb23f002, 0x230d9800, 0x210f2200, 
+    0xfb1df002, 0x46282301, 0x0399220e, 0xfb17f002, 0xf2402300, 0x22083100, 0xf0024628, 0x220cfb10, 
+    0x23024628, 0xf0020291, 0x2300fb0a, 0x22064630, 0xe05e2140, 0x46202301, 0xf002220f, 0x23fafb00, 
+    0x71f0f643, 0x46202204, 0xfaf9f002, 0x46202300, 0x461a2103, 0xfaf3f002, 0x46582100, 0xfad5f002, 
+    0x0800f244, 0x23004620, 0x220e4641, 0xfae7f002, 0x46202300, 0x21082203, 0xfae1f002, 0x46202300, 
+    0x21042202, 0xfadbf002, 0x46412301, 0x4628220e, 0xfad5f002, 0x4628220c, 0x02912302, 0xfacff002, 
+    0xf2402300, 0x22083100, 0xf0024628, 0x2300fac8, 0x22064630, 0xf0022140, 0x2300fac2, 0x22074630, 
+    0xf0022180, 0x2300fabc, 0x22054650, 0xf0022120, 0x2300fab6, 0x22044630, 0xf0022130, 0x2300fab0, 
+    0x22034630, 0xf0022108, 0x2301faaa, 0x22004648, 0xf0024619, 0x4638faa4, 0xfdd2f7ff, 0x220d48ff, 
+    0x0100f242, 0xfaa9f002, 0x48fd0001, 0x0400f24e, 0xd0014438, 0xe0002303, 0x46212306, 0xf002220d, 
+    0x48f8fa8e, 0x2301b001, 0x461a4438, 0x4ff0e8bd, 0xf0022102, 0xb570ba84, 0xb19a460d, 0x1480f44f, 
+    0x48f04603, 0x21012200, 0x44203066, 0xfa77f002, 0x220048ec, 0x462b2101, 0x44203046, 0x4070e8bd, 
+    0xba6df002, 0xe7eb2400, 0x4ff3e92d, 0x4605b083, 0x28009804, 0xf44fd004, 0xd1041480, 0xe00348e2, 
+    0x0400f04f, 0x48e1e7f9, 0x46804621, 0xf7ff4628, 0x48dffe3c, 0xf04f2d05, 0xf8a00a00, 0xd056a000, 
+    0xd0542d04, 0x46232126, 0xf021b289, 0x80010101, 0x20502202, 0xf908f001, 0x46232201, 0x4611205f, 
+    0xf902f001, 0x230048cf, 0x385e2201, 0x46834420, 0x465e2102, 0xfa33f002, 0x230148ca, 0x3088220d, 
+    0x44200359, 0xfa2bf002, 0x46302300, 0x21022201, 0xfa25f002, 0x230048c3, 0x461a2101, 0x44203844, 
+    0xf0024606, 0x48c3fa1c, 0x21012300, 0x4420461a, 0xf0029001, 0x48bffa14, 0x22012300, 0x44203848, 
+    0x46072102, 0xfa0bf002, 0x46382300, 0x461a2101, 0xfa05f002, 0x46302301, 0x46192200, 0xf9fff002, 
+    0xf8df48b5, 0x780092d8, 0xd0022801, 0x2138e009, 0x2d03e7a9, 0x2d02d027, 0x2d05d025, 0x2d04d023, 
+    0x48acd021, 0x23002208, 0x01513052, 0xf0024420, 0xeb04f9e6, 0xf6400009, 0x23000100, 0x220b4606, 
+    0xf9ddf002, 0x46302301, 0x21402206, 0xf9d7f002, 0xd07d2d03, 0xd07c2d05, 0xd07b2d04, 0xd07a2d02, 
+    0xd0792d01, 0x220ce0b7, 0x0009eb04, 0x46062302, 0xf0020291, 0x489af9c4, 0x01eef241, 0xf0024420, 
+    0x4897f9a4, 0x0100f24a, 0x44201c80, 0xf99df002, 0xf6404893, 0x1d0031b8, 0xf0024420, 0x4890f996, 
+    0x3100f641, 0x44201d80, 0xf98ff002, 0xf248488c, 0x30082135, 0xf0024420, 0x4889f988, 0x2135f248, 
+    0x4420300a, 0xf981f002, 0xf2484885, 0x300e2135, 0xf0024420, 0x4882f97a, 0x3012210f, 0xf0024420, 
+    0x487cf974, 0x2205231c, 0x31e0f240, 0x4420305c, 0xf0029000, 0x2d03f984, 0x2d05d006, 0x2d04d004, 
+    0x2d02d002, 0xe022d014, 0xf04f4976, 0x17504260, 0xa000f881, 0xf7da210c, 0x486ef8a2, 0x22032301, 
+    0x2108305e, 0x90024420, 0xf969f002, 0xe0092300, 0x23004868, 0x305e2203, 0x44202108, 0xf0029002, 
+    0x2301f95e, 0x22059802, 0xf0022120, 0xe004f958, 0xe01de01c, 0xe02fe026, 0x9800e030, 0x22002301, 
+    0xf002211f, 0x485bf94c, 0x23012208, 0x01513052, 0xf0024420, 0x2300f944, 0x0100f640, 0x4630220b, 
+    0xf93df002, 0x22062300, 0xe0212140, 0xe016230f, 0xf04f4855, 0x78014260, 0x31201750, 0xf85ff7da, 
+    0xe00c2310, 0xf04f484f, 0x78014260, 0x31101750, 0xf855f7da, 0xe0022303, 0xe0002302, 0x46302301, 
+    0x213f2200, 0xf91bf002, 0xf2402300, 0x220a4100, 0xf0024630, 0x2301f914, 0x21802207, 0x0009eb04, 
+    0xf90df002, 0x23014837, 0x461a2102, 0x44203066, 0xf905f002, 0x1008f898, 0x0009f898, 0xf7ff9a04, 
+    0x483afe7a, 0x22012300, 0x44202102, 0xf8f7f002, 0x4e31482f, 0xf8a01c80, 0x7831a000, 0xd1072901, 
+    0xd0102d03, 0xd00e2d02, 0xd00c2d04, 0xd00a2d05, 0x80012104, 0x46232202, 0x0250b289, 0xffa4f000, 
+    0xb1107830, 0x2103e005, 0x9904e7f3, 0xf0014640, 0x2301f975, 0x21024638, 0xf002461a, 0x2301f8d0, 
+    0x22004638, 0xf0024619, 0x2301f8ca, 0x21024658, 0xf002461a, 0x2301f8c4, 0x22009801, 0xf0024619, 
+    0x4814f8be, 0x22022301, 0xb0052104, 0x4420380e, 0x4ff0e8bd, 0xb8b3f002, 0x4605b570, 0x48144603, 
+    0x220e460c, 0x0100f244, 0x46044420, 0xf8a7f002, 0x462b220d, 0x0100f242, 0xe01b4620, 0xd03c8038, 
+    0xd2052200, 0xd203a160, 0x0003cd5c, 0x0003cd66, 0x00030f9c, 0xd20588ae, 0x000302a5, 0xd2058616, 
+    0xd20524a6, 0x000302a6, 0x000302a7, 0xd202012c, 0xd2054080, 0xf883f002, 0x4620462b, 0x4070e8bd, 
+    0xf241220c, 0xf0020100, 0xe92db87a, 0x46905fff, 0xb1d14607, 0x1480f44f, 0x230148f9, 0x22054420, 
+    0x21204605, 0xf86bf002, 0xf2404ef5, 0xf64071df, 0x1cb60a00, 0xd00a2f03, 0xd00b2f05, 0xd0122f04, 
+    0xd0392f02, 0xd0392f01, 0x2400e041, 0xf240e7e4, 0xe0344310, 0xf2402200, 0x46282308, 0xf84ff002, 
+    0x46212001, 0x2200e031, 0x1304f240, 0x46284689, 0xf845f002, 0x46212001, 0xff8ef7ff, 0x0f03f1b8, 
+    0x2382d125, 0x22004649, 0xf0024628, 0x19a0f838, 0x2900f240, 0x46492301, 0x46802209, 0xf82ff002, 
+    0x780148d8, 0xf7e14650, 0x2300f8a3, 0x22094649, 0xf0024640, 0xe00af824, 0xe0002382, 0x46282341, 
+    0xf0022200, 0x2000f81c, 0xf7ff4621, 0x9803ff65, 0xd07d2801, 0x46512300, 0x4628220b, 0xf80ff002, 
+    0x230119a0, 0x22074605, 0xf0022180, 0x2300f808, 0x22064628, 0xf0022140, 0x2301f802, 0x21202205, 
+    0xf00119a0, 0x48befffc, 0x22002301, 0x30104619, 0x46834420, 0xfff3f001, 0x230148b9, 0x46192200, 
+    0x4420300a, 0xf0014682, 0x48b5ffea, 0x22002301, 0x300e4619, 0x46814420, 0xffe1f001, 0x230148b0, 
+    0x46192200, 0x44203008, 0xf0014606, 0x48acffd8, 0x22002301, 0x300c4619, 0x46054420, 0xffcff001, 
+    0x46582301, 0x21082203, 0xffc9f001, 0xf6412f03, 0xd0666800, 0xd0672f05, 0xd0652f04, 0xd07c2f02, 
+    0xd17b2f01, 0x0400f64f, 0x23044650, 0x220b4621, 0xffb5f001, 0x46212304, 0x4648220b, 0xffaff001, 
+    0x46502306, 0x461a1164, 0xf0014621, 0x2306ffa8, 0x461a4621, 0xf0014648, 0x2301ffa2, 0x22054650, 
+    0xf0012120, 0x2301ff9c, 0x22054648, 0xe0002120, 0xf001e028, 0x2302ff94, 0x22014650, 0xf001211e, 
+    0x2302ff8e, 0x22014648, 0xf001211e, 0x2306ff88, 0x461a4621, 0xf0014650, 0x2306ff82, 0x461a4621, 
+    0xf0014648, 0x2300ff7c, 0x21014650, 0xf001461a, 0x2300ff76, 0x21014648, 0xb004461a, 0x5ff0e8bd, 
+    0xbf6df001, 0x46512301, 0x4628220b, 0xff67f001, 0x230019a0, 0x22074605, 0xf0012180, 0x2301ff60, 
+    0x9803e756, 0xd0322801, 0x46412302, 0x46302209, 0xff55f001, 0x46412302, 0x46282209, 0xff4ff001, 
+    0x14e0f240, 0x23034630, 0x22054621, 0xff47f001, 0x46212303, 0x46282205, 0xe03ae001, 0xf001e076, 
+    0x2301ff3e, 0x22044630, 0xf0012110, 0x2301ff38, 0x22044628, 0xf0012110, 0x2303ff32, 0x22014630, 
+    0xf001210e, 0x2303ff2c, 0x210e2201, 0x2304e050, 0x0100f24e, 0x4658220d, 0xff21f001, 0x23034850, 
+    0x30122200, 0x211f4420, 0xf0014604, 0x230cff18, 0x7100f641, 0x46202208, 0xff11f001, 0x46582300, 
+    0x461a2101, 0xff0bf001, 0x46582301, 0x21082203, 0x2302e793, 0x22094641, 0xf0014630, 0x2302ff00, 
+    0x22094641, 0xf0014628, 0x2301fefa, 0x22044630, 0xf0012110, 0x2301fef4, 0x22044628, 0xf0012110, 
+    0x2303feee, 0x22014630, 0xf001210e, 0x2303fee8, 0x22014628, 0xf001210e, 0xf240fee2, 0x463014e0, 
+    0x46212303, 0xf0012205, 0x2303feda, 0x22054621, 0xf0014628, 0x2300fed4, 0x21014630, 0xf001461a, 
+    0x2300fece, 0x21014628, 0xe756461a, 0x9fffe8bd, 0xf44fb570, 0xb3e01580, 0x2001462c, 0xf0004621, 
+    0x4821fed2, 0x21012300, 0x4420461a, 0xf0014606, 0x2301feb6, 0x22004630, 0xf0014619, 0x481afeb0, 
+    0x220f2301, 0x03d91d80, 0xf0014420, 0x2000fea8, 0xf0004621, 0x2100feb8, 0xf7e04628, 0x2100ff19, 
+    0x2080f44f, 0xff14f7e0, 0x23014810, 0x46192200, 0xf0014420, 0x480afe94, 0x22042300, 0x4420387c, 
+    0x46042110, 0xfe8bf001, 0x46202301, 0x21102204, 0xe003e000, 0x4070e8bd, 0xbe81f001, 0xe7bc2400, 
+    0xd2054080, 0x00030223, 0xd203a1e2, 0xd2052200, 0xb108b430, 0x1080f44f, 0x23004cc1, 0x44202203, 
+    0x2108bc30, 0xbe6bf001, 0x48be0002, 0xf1a0b570, 0xf1a00404, 0xd00a0506, 0xd00f2a01, 0xd1232a02, 
+    0xd01c2901, 0xf0012104, 0x2102fe40, 0x2901e00c, 0x2108d015, 0xfe39f001, 0xe0052104, 0xd0052901, 
+    0xf001210c, 0x2106fe32, 0xe0044628, 0xf0012108, 0x2110fe2c, 0xe8bd4620, 0xf0014070, 0x2104be26, 
+    0xfe23f001, 0xe7f52100, 0xb570bd70, 0xb3214604, 0x1680f44f, 0xf24448a2, 0x307c0100, 0xd01e2c04, 
+    0xd01c2c05, 0x220e2300, 0xf0014430, 0x489dfe28, 0x220d2301, 0x44303808, 0x46050359, 0xfe1ff001, 
+    0xf2412c01, 0xd00c0100, 0xd00a2c02, 0xd00a2c03, 0xd0082c05, 0xd0062c04, 0x2600e00a, 0x2301e7da, 
+    0x2300e7e1, 0x2301e000, 0x220c4628, 0xfe07f001, 0x46282301, 0x21082203, 0xfe01f001, 0x46282301, 
+    0x21042202, 0xfdfbf001, 0x46282301, 0x46192200, 0xfdf5f001, 0xd0012c01, 0xd1052c02, 0x46324882, 
+    0x78004621, 0xff80f7ff, 0x2301487d, 0x44302203, 0x4070e8bd, 0xf0012108, 0xe92dbde2, 0x2a005ff0, 
+    0xd07c460e, 0x1580f44f, 0xf2484c76, 0xf2410100, 0x1ca40a00, 0x6b00f640, 0xf2402800, 0xf04f1900, 
+    0xf04f0300, 0xd07f020f, 0x46881928, 0xf0014604, 0x486bfdc6, 0x22052300, 0x4428307e, 0x46072120, 
+    0xfdbdf001, 0x46512301, 0x4620220c, 0xfdb7f001, 0x4659b2b3, 0x46202209, 0xfdb1f001, 0x46492301, 
+    0x46202208, 0xfdabf001, 0x46202301, 0x46192200, 0xfda5f001, 0x46412301, 0x4620220f, 0xfd9ff001, 
+    0x46382301, 0x21202205, 0xfd99f001, 0x23014855, 0x1d002209, 0x02594428, 0xf0014604, 0x2300fd90, 
+    0x2208464e, 0x46204649, 0xfd89f001, 0x46202300, 0x21082203, 0xfd83f001, 0x8800484c, 0xd04e2800, 
+    0x46202301, 0x21082203, 0xfd79f001, 0x23004845, 0x46592209, 0x44283808, 0xf0014605, 0x2301fd70, 
+    0x22084631, 0xf0014628, 0x2100fd6a, 0x4000f240, 0xfddef7e0, 0x46202300, 0x21042202, 0xe011e001, 
+    0xf001e012, 0x2301fd5c, 0x22024620, 0xf0012104, 0x2100fd56, 0xf7e02004, 0x2300fdcb, 0x22084631, 
+    0xe0264628, 0xe76f2500, 0x46041928, 0xfd47f001, 0x46512301, 0x4620220c, 0xfd41f001, 0x4659b2b3, 
+    0x46202209, 0xfd3bf001, 0x46492301, 0x46202208, 0xfd35f001, 0x46202301, 0x46192200, 0x2300e794, 
+    0x22024620, 0xf0012104, 0x2300fd2a, 0x22014620, 0xe8bd2102, 0xf0015ff0, 0x481dbd22, 0x22002303, 
+    0xb5102107, 0xfd1bf001, 0x23014819, 0x21042202, 0xf0011f80, 0x4817fd14, 0x22002306, 0xf0012107, 
+    0x4814fd0e, 0x21022301, 0x1c80461a, 0xfd07f001, 0x23004810, 0x461a2101, 0x4010e8bd, 0xf0013808, 
+    0xb430bcfe, 0xf44fb151, 0x46031480, 0x22044805, 0x38082110, 0xbc304420, 0xbcf1f001, 0xe7f42400, 
+    0xd2054004, 0xd2054188, 0x000302e4, 0x000302e2, 0xd03d1046, 0xd215412e, 0x47f0e92d, 0x23014cff, 
+    0x46192200, 0xf0014620, 0x2301fcda, 0x21024620, 0xf001461a, 0x48f9fcd4, 0x5507f643, 0x76fff643, 
+    0x2200462b, 0x30424631, 0xfcc9f001, 0x1c7748f3, 0x463b2200, 0x46313044, 0xfcc1f001, 0xf64048ef, 
+    0x22002888, 0x30464643, 0xf0014631, 0x48ebfcb8, 0x09e2f241, 0x464b2200, 0x46313048, 0xfcaff001, 
+    0x220048e6, 0x46314643, 0xf001304a, 0x48e3fca8, 0x461a2300, 0x304c4631, 0xfca1f001, 0x220048df, 
+    0x4631462b, 0xf001304e, 0x48dcfc9a, 0x463b2200, 0x30504631, 0xfc93f001, 0x220048d8, 0x4631462b, 
+    0xf0013052, 0x48d5fc8c, 0x463b2200, 0x30544631, 0xfc85f001, 0x220048d1, 0x46314643, 0xf0013056, 
+    0x48cefc7e, 0x464b2200, 0x30584631, 0xfc77f001, 0x220048ca, 0x46314643, 0xf001305a, 0x48c7fc70, 
+    0x461a2300, 0x305c4631, 0xfc69f001, 0x220048c3, 0x4631462b, 0xf001305e, 0x48c0fc62, 0x463b2200, 
+    0x30604631, 0xfc5bf001, 0x220048bc, 0x4631462b, 0xf0013062, 0x48b9fc54, 0x463b2200, 0x30644631, 
+    0xfc4df001, 0x220048b5, 0x46314643, 0xf0013066, 0x48b2fc46, 0x464b2200, 0x30684631, 0xfc3ff001, 
+    0x220048ae, 0x46314643, 0xf001306a, 0x48abfc38, 0x461a2300, 0x306c4631, 0xfc31f001, 0x220048a7, 
+    0x4631462b, 0xf001306e, 0x48a4fc2a, 0x463b2200, 0x30704631, 0xfc23f001, 0x220048a0, 0x4631462b, 
+    0xf0013072, 0x489dfc1c, 0x463b2200, 0x30744631, 0xfc15f001, 0x22004899, 0x46314643, 0xf0013076, 
+    0x4896fc0e, 0x464b2200, 0x30784631, 0xfc07f001, 0x22004892, 0x46314643, 0xf001307a, 0x488ffc00, 
+    0x461a2300, 0x307c4631, 0xfbf9f001, 0x2200488b, 0x4631462b, 0xf001307e, 0x4888fbf2, 0x463b2200, 
+    0x30804631, 0xfbebf001, 0xe8bd4620, 0x230147f0, 0x21042202, 0xbbe3f001, 0x41f0e92d, 0x23014c7f, 
+    0x1f242202, 0x46202104, 0xfbd9f001, 0x46202301, 0x21082203, 0xfbd3f001, 0xf6434878, 0xf6435407, 
+    0x462375ff, 0x46292200, 0xf0011c80, 0x4873fbc8, 0x22001c6e, 0x1d004633, 0xf0014629, 0x486ffbc0, 
+    0x2788f640, 0x463b2200, 0x46291d80, 0xfbb7f001, 0xf241486a, 0x220008e2, 0x30084643, 0xf0014629, 
+    0x4866fbae, 0x463b2200, 0x300a4629, 0xfba7f001, 0x23004862, 0x4629461a, 0xf001300c, 0x485ffba0, 
+    0x46232200, 0x300e4629, 0xfb99f001, 0x2200485b, 0x46294633, 0xf0013010, 0x4858fb92, 0x46232200, 
+    0x30124629, 0xfb8bf001, 0x22004854, 0x46294633, 0xf0013014, 0x4851fb84, 0x463b2200, 0x30164629, 
+    0xfb7df001, 0x2200484d, 0x46294643, 0xf0013018, 0x484afb76, 0x463b2200, 0x301a4629, 0xfb6ff001, 
+    0x23004846, 0x4629461a, 0xf001301c, 0x4843fb68, 0x46232200, 0x301e4629, 0xfb61f001, 0x2200483f, 
+    0x46294633, 0xf0013020, 0x483cfb5a, 0x46232200, 0x30224629, 0xfb53f001, 0x22004838, 0x46294633, 
+    0xf0013024, 0x4835fb4c, 0x463b2200, 0x30264629, 0xfb45f001, 0x22004831, 0x46294643, 0xf0013028, 
+    0x482efb3e, 0x463b2200, 0x302a4629, 0xfb37f001, 0x2300482a, 0x4629461a, 0xf001302c, 0x4827fb30, 
+    0x46232200, 0x302e4629, 0xfb29f001, 0x22004823, 0x46294633, 0xf0013030, 0x4820fb22, 0x46232200, 
+    0x30324629, 0xfb1bf001, 0x2200481c, 0x46294633, 0xf0013034, 0x4819fb14, 0x463b2200, 0x30364629, 
+    0xfb0df001, 0x22004815, 0x46294643, 0xf0013038, 0x4812fb06, 0x463b2200, 0x303a4629, 0xfafff001, 
+    0x2300480e, 0x4629461a, 0xf001303c, 0x480bfaf8, 0x46232200, 0x303e4629, 0xfaf1f001, 0x22004807, 
+    0x46294633, 0xf0013040, 0xe8bdfaea, 0x480341f0, 0x22002301, 0x1e804619, 0x0000e002, 0xd0030a04, 
+    0xbaddf001, 0x4c2fb570, 0xd0282803, 0x28051d25, 0x2804d035, 0x2301d154, 0x22024620, 0xf0012104, 
+    0x2301face, 0x22034620, 0xf0012108, 0x2301fac8, 0x21024628, 0xf001461a, 0x2301fac2, 0x22004628, 
+    0xf0014619, 0xf7fffabc, 0xf7fffed7, 0x2302fdd5, 0x21032200, 0xe8bd4620, 0xf0014070, 0x2300bab0, 
+    0x21034620, 0xf001461a, 0x2300faaa, 0x22024620, 0xf0012104, 0x2300faa4, 0x21082203, 0x2301e7ea, 
+    0x22024620, 0xf0012104, 0x2301fa9a, 0x22034620, 0xf0012108, 0x2300fa94, 0x22014628, 0xf0012102, 
+    0x2300fa8e, 0x21014628, 0xf001461a, 0x2301fa88, 0x22004620, 0xf0012103, 0xe8bdfa82, 0xe69b4070, 
+    0x0000bd70, 0xd0030a00, 0x488f2301, 0x46192200, 0xf001b510, 0x488dfa74, 0x0000f990, 0x2802b108, 
+    0x4c8bd10e, 0x21012300, 0x4620461a, 0xfa67f001, 0x46202301, 0x4010e8bd, 0x461a2102, 0xba5ff001, 
+    0xe92dbd10, 0x460543f8, 0x46292000, 0x90004604, 0xf7fe2002, 0xf8dffc56, 0xf44f91fc, 0x4f7d0000, 
+    0x1622f241, 0x81f0f8df, 0x0914f109, 0xe0109000, 0x46422109, 0xf7e04668, 0x2801fb35, 0x4648d00e, 
+    0xfa20f001, 0x2c04b204, 0x2c08d008, 0x42b4d006, 0x4638d004, 0xfa16f001, 0xd0e942a8, 0xf2402100, 
+    0xf7e04000, 0x2c04faa5, 0x4638d115, 0xfa0af001, 0xd11042a8, 0x34164c67, 0xf0014620, 0x2200fa03, 
+    0xf44f4601, 0xf7d91000, 0x4620f94a, 0xf9faf001, 0xe8bdb200, 0x200083f8, 0xe92de7fb, 0x4f5f5ff0, 
+    0xf04f0004, 0xd0050500, 0x46382301, 0x21102204, 0xfa05f001, 0x22024e56, 0x4623211c, 0xf0014630, 
+    0x2301f9fe, 0x22054630, 0xf0012120, 0xf240f9f8, 0x21004800, 0xf7e04640, 0x2301fa6b, 0x21802207, 
+    0xf0011cb0, 0x2100f9ec, 0xf7e04640, 0x2200fa61, 0x31fff240, 0xf0011db0, 0x4f49f9f0, 0xf8dfb184, 
+    0x2c039124, 0xb120f8df, 0x0809f06f, 0x3a66f04f, 0x2c04d016, 0x2c05d014, 0x2c06d01e, 0xe033d049, 
+    0xfa5ef003, 0x4b424a41, 0xfaaaf003, 0x463a4b41, 0xfbdaf003, 0xff9af002, 0xfeeef003, 0xe0354605, 
+    0xfa4ef003, 0xf0044642, 0x2200f8c2, 0xf003464b, 0x4652fa97, 0xe00a465b, 0xfa42f003, 0xf0044642, 
+    0x2200f8b6, 0xf003464b, 0x4b33fa8b, 0xf003463a, 0xf002f86b, 0x4931ff7b, 0xfe0cf003, 0xf0034930, 
+    0xf003ff33, 0x4605fec9, 0x23004630, 0x211c2202, 0xf995f001, 0x46302301, 0x21202205, 0xf98ff001, 
+    0x2300481e, 0x21102204, 0xf989f001, 0xe8bd4628, 0xf0039ff0, 0x4642fa15, 0xf889f004, 0x464b2200, 
+    0xfa5ef003, 0x463a4b1f, 0xb570e7d1, 0x480f4605, 0x0000f990, 0x2802b198, 0x4628d011, 0xff11f7ff, 
+    0x46294604, 0x1500f44f, 0x46282200, 0xf897f7d9, 0x46212200, 0xf7d94628, 0x4620f892, 0x4628bd70, 
+    0xff4bf7ff, 0xe7ecb204, 0xd03d0004, 0x000301c8, 0xd03d408a, 0xd03d101e, 0xd003517c, 0xd03d408c, 
+    0x9999999a, 0x408b8000, 0x3fe66666, 0xd3c36113, 0x3fdf652b, 0x4079d599, 0x3fd99999, 0x447a0000, 
+    0x461c4000, 0x3fc99999, 0x41f0e92d, 0x461d2a02, 0x46804617, 0xd100460e, 0x48cbba4e, 0xf2402302, 
+    0x44281180, 0x46042207, 0xf929f001, 0xf2402f02, 0xd0172100, 0x46202301, 0xf0012209, 0x48c2f920, 
+    0x1e804641, 0xf0014428, 0x48c0f900, 0x20047801, 0xf98ef7e0, 0x463148bc, 0x44281c80, 0x41f0e8bd, 
+    0xb8f3f001, 0xe7e62300, 0x4ff8e92d, 0x20504606, 0x22042300, 0x8000f8d0, 0x48b32110, 0x2990f44f, 
+    0x46044430, 0xf8fbf001, 0x230148af, 0x46192200, 0x44303016, 0xf0014605, 0x2301f8f2, 0x21024628, 
+    0xf001461a, 0x2300f8ec, 0x22014628, 0xf0012102, 0x2301f8e6, 0x21024628, 0xf001461a, 0x2300f8e0, 
+    0x1180f240, 0x46202207, 0xf8d9f001, 0xf2402300, 0x22092100, 0xf0014620, 0x489bf8d2, 0x1e802100, 
+    0x46054430, 0xf8b1f001, 0x0a00f248, 0x23004620, 0x220f4657, 0xf0014651, 0x2301f8c2, 0x220f4639, 
+    0xf0014620, 0x2300f8bc, 0x220f4639, 0xf0014620, 0x488ef8b6, 0x46387801, 0xf92af7e0, 0xf44f488a, 
+    0xf8cd0b00, 0x1d80b000, 0xe0061837, 0x21074a88, 0xf7e04668, 0x2801f997, 0x220fd006, 0x46384651, 
+    0xf8abf001, 0xd0f12800, 0xfa1f487f, 0x1f00f188, 0xf0014430, 0x2100f87a, 0xf0014628, 0x2300f876, 
+    0x22014620, 0xf0012102, 0x2301f88a, 0x22034620, 0xf0012108, 0x2301f884, 0x22004620, 0xf0014619, 
+    0x4871f87e, 0xeb082500, 0x1c8078d8, 0xe0064406, 0x1015f839, 0xf0014630, 0x1c6df858, 0xebb5b2ad, 
+    0xdbf50f68, 0x46202300, 0x21082203, 0xf867f001, 0x46202300, 0x461a2101, 0xf861f001, 0x46202301, 
+    0x461a2102, 0xf85bf001, 0x46564d61, 0xb000f8cd, 0x2108e006, 0x4668462a, 0xf944f7e0, 0xd0062801, 
+    0x4631220f, 0xf0014638, 0x2800f858, 0x2300d0f1, 0x22014620, 0xf0012102, 0xe8bdf842, 0xe92d8ff8, 
+    0x460741f0, 0xf44f2050, 0x68062890, 0x4f00f5b6, 0x484ddc27, 0x1f00b2b1, 0xf0014438, 0x484af816, 
+    0x1e802100, 0xf0014438, 0x4847f810, 0x22022301, 0x21044438, 0xf0014605, 0x2301f822, 0x22004628, 
+    0xf0014619, 0x4840f81c, 0xeb062400, 0x1d0076d6, 0xe00b4407, 0xf0004638, 0xf838fff5, 0x42811014, 
+    0x2000d002, 0x81f0e8bd, 0xb2a41c64, 0x0f66ebb4, 0x2300dbf0, 0x22024628, 0xf0012104, 0x2300f800, 
+    0x21014628, 0xf000461a, 0x2301fffa, 0x21024628, 0xf000461a, 0x2300fff4, 0x22014628, 0xf0002102, 
+    0x2001ffee, 0xb570e7de, 0x4927460c, 0x49261866, 0x18653116, 0x4824b3a0, 0x1f002100, 0xf0004420, 
+    0x4821ffc4, 0x1e802100, 0xf0004420, 0x2100ffbe, 0xf0004630, 0x481cffba, 0x1c802100, 0xf0004420, 
+    0x4819ffb4, 0x30122100, 0xf0004420, 0x4816ffae, 0x300e2100, 0xf0004420, 0x4813ffa8, 0x010ff640, 
+    0x44203010, 0xffa1f000, 0x2102480f, 0x44203014, 0xff9bf000, 0xe8bd4628, 0x21004070, 0xbf95f000, 
+    0x46282301, 0x46192200, 0xffa9f000, 0x46282301, 0x461a2102, 0xffa3f000, 0xe8bd4630, 0x23014070, 
+    0x21102204, 0xbf9bf000, 0xd203a404, 0x00030223, 0xd003517e, 0x4605b5f0, 0x9c052000, 0xd3012d20, 
+    0x1001f240, 0xd3012971, 0x7081f440, 0xd3012a40, 0x7082f440, 0x060ff103, 0xd3012e1f, 0x7084f440, 
+    0x2e0f1de6, 0xf440d301, 0x18ae7088, 0x4426441e, 0xf1011c76, 0x42be0730, 0xf440dd01, 0x44297090, 
+    0x44112b00, 0x425bdc00, 0x44192c00, 0x4264dc00, 0x29704421, 0xf440dd01, 0xbdf070a0, 0x5ffce92d, 
+    0xf44fb1d1, 0xf9901480, 0xf990c000, 0xf9908001, 0xf9909002, 0xf990a003, 0x464a1005, 0x7004f990, 
+    0x91014653, 0xf9904641, 0x46606006, 0xf7ff9700, 0x0005ffb1, 0xe02cd002, 0xe7e42400, 0xfa1f4820, 
+    0x2200f38c, 0x211f4420, 0xf0004683, 0x481cff38, 0xf388fa1f, 0x1c802200, 0x217f4420, 0xf0004680, 
+    0xfa1fff2e, 0xf240f389, 0x220571e0, 0xf0004658, 0xfa1fff26, 0xf640f38a, 0x22077180, 0xf0004640, 
+    0x480fff1e, 0x2200b2bb, 0x210f3012, 0xf0004420, 0x9801ff16, 0x210f2200, 0x4809b283, 0x442038dc, 
+    0xf0004604, 0x2e03ff0c, 0xb2b3dd07, 0x0100f246, 0x4620220d, 0xff03f000, 0x46282501, 0x9ffce8bd, 
+    0xd203a220, 0x4606b570, 0xf968f000, 0xf1066805, 0xf020000b, 0x42b40407, 0x2000bf98, 0x462bd915, 
+    0xb1ba686a, 0x42a06810, 0xf104d310, 0x42880108, 0x6850bf3c, 0xd3076058, 0x19106851, 0x68116041, 
+    0x60011b09, 0x60146058, 0xbd701d10, 0x68524613, 0xd1e72a00, 0x46284621, 0xf948f000, 0xd1de2800, 
+    0xb570bd70, 0x1f054604, 0xf938f000, 0x2c006800, 0x6844bf18, 0x2c00d01b, 0x42acbf18, 0x4620bf3c, 
+    0xd3f86864, 0x180a6801, 0xbf1842aa, 0xd1036045, 0x4605682a, 0x60014411, 0x19416828, 0xbf1842a1, 
+    0xd104606c, 0x60696861, 0x44086821, 0xbd706028, 0x0320f1b2, 0xf1c2d50a, 0xfa200320, 0xfa01f002, 
+    0xfa21f303, 0xea40f102, 0x47700003, 0xf003fa21, 0x0100f04f, 0x00004770, 0xe92d4010, 0xe1b040c1, 
+    0xe02440a3, 0x5a000002, 0xe2700000, 0xe2611000, 0x32411001, 0xe1130003, 0x5a000002, 0xe2722000, 
+    0xe2633000, 0x32433001, 0xeb00009c, 0xe3140101, 0x0a000002, 0xe2700000, 0xe2611000, 0x32411001, 
+    0xe3140102, 0x0a000002, 0xe2722000, 0xe2633000, 0x32433001, 0xe8bd8010, 0xb510490b, 0x027cf1a1, 
+    0xe9c24c0a, 0x21371237, 0xeb00e006, 0xf8424310, 0x4b073021, 0x4003fb00, 0xf1a11e0b, 0xdcf40101, 
+    0x2001bd10, 0x0000e7e8, 0x0003d4d4, 0x66d619e1, 0x00010dcd, 0xe3520003, 0x9a000017, 0xe210c003, 
+    0x0a000008, 0xe4d13001, 0xe35c0002, 0xe082200c, 0x94d1c001, 0xe4c03001, 0x34d13001, 0x94c0c001, 
+    0xe2422004, 0x34c03001, 0xe2113003, 0x0a000012, 0xe2522008, 0x3a000004, 0xe4913004, 0xe2522008, 
+    0xe491c004, 0xe8a01008, 0xeafffff9, 0xe2922004, 0x54913004, 0x54803004, 0xe1a00000, 0xe1b02f82, 
+    0x24d13001, 0x24d1c001, 0x44d12001, 0x24c03001, 0x24c0c001, 0x44c02001, 0xe12fff1e, 0xe92d4010, 
+    0xe2522020, 0x3a000005, 0xe8b15018, 0xe2522020, 0xe8a05018, 0xe8b15018, 0xe8a05018, 0x2afffff9, 
+    0xe1b0ce02, 0x28b15018, 0x28a05018, 0x48b10018, 0x48a00018, 0xe8bd4010, 0xe1b0cf02, 0x24913004, 
+    0x24803004, 0x012fff1e, 0xe1b02f82, 0x20d130b2, 0x44d12001, 0x20c030b2, 0x44c02001, 0xe12fff1e, 
+    0x03fff002, 0x2203ea43, 0x4202ea42, 0xba2df000, 0xe3100003, 0xe92d4010, 0xe1a04000, 0x03110003, 
+    0x1a00000a, 0xe59fe04c, 0xe2522004, 0xba000006, 0xe4913004, 0xe043c00e, 0xe1ccc003, 0xe01cc38e, 
+    0x04803004, 0x0afffff7, 0xe2411004, 0xe2822004, 0xe2522001, 0xba000005, 0xe4d13001, 0xe3530000, 
+    0xe4c03001, 0x1afffff9, 0xe1a01002, 0xfb0000fc, 0xe1a00004, 0xe8bd8010, 0x01010101, 0x47704800, 
+    0x0003d544, 0x47704770, 0x47704770, 0x4604b538, 0x2000460a, 0xf0004669, 0x2800fa62, 0x4602d005, 
+    0x99004620, 0xfa0af000, 0xbd382001, 0xf0002001, 0xb5f8ba1d, 0xfa48f000, 0x20004605, 0x2010460c, 
+    0x4606bf00, 0x42a019a8, 0x4632d90d, 0x20004669, 0xfa45f000, 0xbf080007, 0xfa08f000, 0x42a09800, 
+    0x4605bf18, 0xf7ff19c4, 0x6005ffc9, 0x1df04607, 0x0007f020, 0x46281946, 0xf80af000, 0xd00642b4, 
+    0x68384631, 0xe8bd1ba2, 0xf00040f8, 0xbdf8b9d7, 0x60012100, 0x1001e9c0, 0x20104770, 0x00004770, 
+    0xe92d4070, 0xe1a04003, 0xe1a05002, 0xe1a03001, 0xe1a02000, 0xe3540000, 0x11a0c004, 0x01a0c005, 
+    0xe16fef1c, 0xe28e0001, 0xe1a0c01c, 0x127ee03f, 0x027ee01f, 0x4a000094, 0xe3530000, 0x116f1f13, 
+    0x016f1f12, 0x1271103f, 0x0271101f, 0xe051600e, 0x4a000092, 0x52760004, 0x5a000093, 0xe24e0020, 
+    0xe3500004, 0xd1a01035, 0xd18cc001, 0xe28f1f9f, 0xe1a0ce2c, 0xe35e001f, 0xe791c10c, 0x824ee020, 
+    0xe26e6020, 0x8a000048, 0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 
+    0xe2611000, 0x32411001, 0xe081019c, 0xe08cc001, 0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 
+    0xe1811004, 0xe2700000, 0xe2611000, 0x32411001, 0xe3530000, 0xe081019c, 0xe08cc001, 0x0a000009, 
+    0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 0xe2611000, 0x32411001, 
+    0xe081019c, 0xe08cc001, 0xe080129c, 0xe3a01000, 0xe0a1039c, 0xe1a00e30, 0xe1a04611, 0xe1800004, 
+    0xe1a01e31, 0xe0846590, 0xe0522006, 0xe0244591, 0xe0c33004, 0xe3530001, 0x31520005, 0x38bd8070, 
+    0xe086429c, 0xe3a04000, 0xe0a4639c, 0xe26ec020, 0xe1a06e36, 0xe1a03c14, 0xe1866003, 0xe3a03000, 
+    0xe1a04e34, 0xe08ce596, 0xe0900006, 0xe0a11004, 0xe042200e, 0xe1520005, 0x38bd8070, 0xe2900001, 
+    0xe2a11000, 0xe0422005, 0xe052c005, 0x21a0200c, 0xe2b00000, 0xe2a11000, 0xe052c005, 0x21a0200c, 
+    0xe2b00000, 0xe2a11000, 0xe8bd8070, 0xe080159c, 0xe3a01000, 0xe0a1049c, 0xe1a01611, 0xe1a06e30, 
+    0xe1811006, 0xe26e6020, 0xe2611000, 0xe1a00610, 0xe2700000, 0x32411001, 0xe081019c, 0xe08cc001, 
+    0xe080159c, 0xe3a01000, 0xe0a1049c, 0xe1a01611, 0xe1a06e30, 0xe1811006, 0xe26e6020, 0xe2611000, 
+    0xe1a00610, 0xe2700000, 0x32411001, 0xe081019c, 0xe08cc001, 0xe24cc001, 0xe080129c, 0xe3a01000, 
+    0xe0a1039c, 0xe1a00e31, 0xe0816590, 0xe0522006, 0xe0211490, 0xe0c33001, 0xe1530004, 0x01520005, 
+    0x33a01000, 0x38bd8070, 0xe081629c, 0xe3a06000, 0xe0a6139c, 0xe3a01000, 0xe1a06e36, 0xe08ce596, 
+    0xe0800006, 0xe052200e, 0xe02ec496, 0xe0c3300e, 0xe1530004, 0x01520005, 0x38bd8070, 0xe2800001, 
+    0xe0522005, 0xe0c33004, 0xe8bd8070, 0xe92d000c, 0xe3a01000, 0xe3a00000, 0xe1a00000, 0xe8bd807c, 
+    0xe3a01000, 0xe3a00000, 0xe8bd8070, 0xe266e020, 0xe3a00000, 0xe3a01000, 0xe1a04614, 0xe1a0ce35, 
+    0xe1a05615, 0xe184400c, 0xe052e005, 0xe0d3c004, 0xe0a00000, 0x21a0300c, 0x21a0200e, 0xe2566001, 
+    0x38bd8070, 0xe1b040a4, 0xe1a05065, 0xeafffff5, 0xf0f0f0f0, 0xe38e38e3, 0xd79435e5, 0xcccccccc, 
+    0xc30c30c3, 0xba2e8ba2, 0xb21642c8, 0xaaaaaaaa, 0xa3d70a3d, 0x9d89d89d, 0x97b425ed, 0x92492492, 
+    0x8d3dcb08, 0x88888888, 0x84210842, 0x80000000, 0xf000b510, 0x6800f82f, 0xb510bd10, 0xf0004604, 
+    0x6004f829, 0xf04fbd10, 0x29040200, 0x8012f0c0, 0x0c03f010, 0x8043f000, 0x0c04f1cc, 0x0f02f1bc, 
+    0xf800bf18, 0xbfa82b01, 0x2b02f820, 0x010ceba1, 0xb835f000, 0x7cc1ea5f, 0xf800bf24, 0xf8002b01, 
+    0xbf482b01, 0x2b01f800, 0x00004770, 0x47704800, 0x0003d53c, 0x47704800, 0x0003d53c, 0x6843468c, 
+    0xbf182b00, 0xbf38428b, 0xd3f84618, 0x44186803, 0xd0074288, 0x0003f10c, 0x0007f020, 0x1a411d00, 
+    0x46011a52, 0x600a1d08, 0xbc8bf7ff, 0xf000b510, 0xe8bdf885, 0xf0004010, 0xf04fb87b, 0xb5000200, 
+    0x46944613, 0x39204696, 0xe8a0bf22, 0xe8a0500c, 0xf1b1500c, 0xf4bf0120, 0x0709aff7, 0xe8a0bf28, 
+    0xbf48500c, 0xf85dc00c, 0x0089eb04, 0xf840bf28, 0xbf082b04, 0xbf484770, 0x2b02f820, 0x4f80f011, 
+    0xf800bf18, 0x47702b01, 0x46694b12, 0x5280f500, 0x601a428a, 0x4611d801, 0x60194770, 0xb5304770, 
+    0x466b4d0c, 0x5380f5a3, 0x4422682c, 0xd80f429a, 0xf5021a9b, 0xeb035080, 0xeb0273d3, 0x42980363, 
+    0x4618d900, 0xf0201dc0, 0x600c0207, 0x602a1b10, 0x0000bd30, 0x00030fa0, 0x46754770, 0xff86f7ff, 
+    0x000546ae, 0x46534669, 0x0007f020, 0xb0184685, 0xf001b520, 0xe8bdea84, 0xf04f4020, 0xf04f0600, 
+    0xf04f0700, 0xf04f0800, 0xf0210b00, 0x46ac0107, 0x09c0e8ac, 0x09c0e8ac, 0x09c0e8ac, 0x09c0e8ac, 
+    0x4770468d, 0xf3af4604, 0x46208000, 0xf8cdf7d8, 0xd0012800, 0xb82af000, 0x00004770, 0x2801b510, 
+    0x2100d005, 0xf000a003, 0x2001f827, 0xa109bd10, 0x0000e7f8, 0x52474953, 0x4d454d54, 0x754f203a, 
+    0x666f2074, 0x61656820, 0x656d2070, 0x79726f6d, 0x00000000, 0x6548203a, 0x6d207061, 0x726f6d65, 
+    0x6f632079, 0x70757272, 0x00646574, 0x20184901, 0xe7fedfab, 0x00020026, 0x4605b570, 0x200a460c, 
+    0x1c6de000, 0xf811f000, 0x7828b135, 0xd1f82800, 0x1c64e002, 0xf809f000, 0x7820b114, 0xd1f82800, 
+    0x4070e8bd, 0xf3af200a, 0xb5088000, 0xf88d4669, 0x20030000, 0xbd08dfab, 0xe92d0003, 0xe59f0050, 
+    0xe580e000, 0xe59f004c, 0xe5901000, 0xe3510000, 0x1a000001, 0xe59f1040, 0xe5801000, 0xe2811001, 
+    0xe5801000, 0xe59f0034, 0xee151f10, 0xe5801000, 0xe59f002c, 0xee161f10, 0xe5801000, 0xe59f0024, 
+    0xee151f11, 0xe5801000, 0xe8bd0003, 0xe25ef008, 0xe320f000, 0xc300000c, 0xc3000010, 0xdead0000, 
+    0xc3000020, 0xc3000024, 0xc3000028, 0xf04fb500, 0xee116060, 0xea011f30, 0xee010100, 0xee111f30, 
+    0xf3bf0f30, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f10, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 
+    0xf3bf0f30, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f11, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 
+    0xf3bf0f31, 0xf85d8f6f, 0x4770eb04, 0xee16b500, 0xf3bf0f10, 0xf85d8f6f, 0x4770eb04, 0xee16b500, 
+    0xf3bf0f50, 0xf85d8f6f, 0x4770eb04, 0x5ffce92d, 0x4601468a, 0x0000f04f, 0x2b01f811, 0x03bbf04f, 
+    0xd128429a, 0x2b01f811, 0x03a7f04f, 0xd122429a, 0x2b01f811, 0xd11e4282, 0x2b01f811, 0xd11a4282, 
+    0xf04f4650, 0xf04f0a00, 0x5c8c0200, 0x050aea84, 0x06fff005, 0x5016f830, 0x261aea4f, 0x0a06ea85, 
+    0x0201f102, 0xdbf02a0a, 0xf04f5a8c, 0x45540001, 0xf04fd001, 0xe8bd0000, 0x00009ffc, 0xe92d500f, 
+    0xe14fc000, 0xe92d1000, 0xe59f0024, 0xe5d01000, 0xe1a01201, 0xe59f201c, 0xe0822001, 0xe5920000, 
+    0xe8bd1000, 0xe16ff00c, 0xe8bd500f, 0xe25ef004, 0xe320f000, 0xc1000014, 0xc1000104, 0x5ff0e92d, 
+    0x90d0f8df, 0x0a52ea4f, 0x0b92ea4f, 0xf823880c, 0x88044b02, 0x4b02f823, 0x401bf831, 0x4b02f823, 
+    0x401bf830, 0x4b02f823, 0x0701f04f, 0x5007f819, 0x4015f831, 0x4b02f823, 0x4015f830, 0x4b02f823, 
+    0x0505ebaa, 0x4015f831, 0x0400f1c4, 0x4b02f823, 0x4015f830, 0x4b02f823, 0x0701f107, 0xf6ff455f, 
+    0xe8bdafe5, 0xe92d9ff0, 0xf8df5ff0, 0xea4f9068, 0xea4f0a51, 0xf04f0b91, 0xf9300700, 0x801c4b02, 
+    0x4b02f930, 0xf1078014, 0xf9300701, 0xf8234b02, 0xf930401b, 0xf8226b02, 0xf819601b, 0xf9305007, 
+    0xf8234b02, 0xf9304015, 0xf8226b02, 0xebaa6015, 0xf9300505, 0xf1c44b02, 0xf8230400, 0xf9304015, 
+    0xf8226b02, 0xf1076015, 0x455f0701, 0xafe5f6ff, 0x9ff0e8bd, 0x0002c710, 0x5ff0e92d, 0x0a00f04f, 
+    0x4694468b, 0x1000f990, 0x2001f990, 0x0302eb01, 0x5002f990, 0x6003f990, 0x0706eb05, 0x0806eba5, 
+    0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb03, 0x9b04f84c, 
+    0x0908eb03, 0x9b04f84c, 0x0402eba1, 0x0706eb05, 0x0806eba5, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 
+    0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0301eba2, 
+    0x0706eb05, 0x0806eba5, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 
+    0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0302eb01, 0x0400f1c3, 0x0706eb05, 0x0806eba5, 
+    0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb04, 0x9b04f84c, 
+    0x0908eb04, 0x9b04f84c, 0x0004f100, 0x0a01f10a, 0xf6ff45da, 0xe8bdaf87, 0x00009ff0, 0xe92d500f, 
+    0xe14fc000, 0xe92d1000, 0xe59f0024, 0xe5d01000, 0xe1a01201, 0xe59f201c, 0xe0822001, 0xe5920000, 
+    0xe8bd1000, 0xe16ff00c, 0xe8bd500f, 0xe25ef004, 0xe320f000, 0xc100000c, 0xc1000104, 0x5ffce92d, 
+    0x0300f04f, 0x4023f850, 0x4023f841, 0x0301f103, 0xf6ff4293, 0xe8bdaff7, 0xe92d9ffc, 0xf04f5ffc, 
+    0x2b000500, 0xf1c3da02, 0xe00b0300, 0x4025f850, 0xf403fa04, 0x4025f841, 0x0501f105, 0xf6ff4295, 
+    0xe00aaff5, 0x4025f850, 0xf403fa44, 0x4025f841, 0x0501f105, 0xf6ff4295, 0xe8bdaff5, 0xe92d9ffc, 
+    0xf04f5ffc, 0xf8300300, 0xf8214013, 0xf1034013, 0x42930301, 0xaff7f6ff, 0x9ffce8bd, 0x5ffce92d, 
+    0x0300f04f, 0x4013f930, 0x4023f841, 0x0301f103, 0xf6ff4293, 0xe8bdaff7, 0xe92d9ffc, 0xf04f5ff0, 
+    0xf9300500, 0xfa044b02, 0xf841f403, 0xf1054b04, 0x42950501, 0xaff5f6ff, 0x9ff0e8bd, 0x5ffce92d, 
+    0x0701f1a3, 0x0601f04f, 0xf607fa06, 0x0500f04f, 0x4025f850, 0xfa444434, 0xf821f403, 0xf1054015, 
+    0x42950501, 0xaff4f6ff, 0x9ffce8bd, 0xe92d5ffc, 0xeafffffe, 0xe8bd9ffc, 0x6800b500, 0xb500bd00, 
+    0xbd006001, 0x8800b500, 0xb500bd00, 0xbd008001, 0x41f0e92d, 0xea246804, 0xfa030401, 0xea05f502, 
+    0xea440501, 0x60040405, 0x81f0e8bd, 0x41f0e92d, 0xea006800, 0xfa200001, 0xe8bdf002, 0xe92d81f0, 
+    0x880441f0, 0x0401ea24, 0xf502fa03, 0x0501ea05, 0x0405ea44, 0xe8bd8004, 0xe92d81f0, 0x880041f0, 
+    0x0001ea00, 0xf002fa20, 0x81f0e8bd, 0xe59f1150, 0xe5910000, 0xe590e000, 0xe59f0148, 0xe8be0002, 
+    0xe5801000, 0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 0xef000000, 
+    0xe12fff1e, 0xe28ee004, 0xe92d0001, 0xe94d2000, 0xe320f000, 0xe24dd004, 0xe8bd0001, 0xe9204000, 
+    0xe1a0e000, 0xe8bd0001, 0xe94e7fff, 0xe320f000, 0xe24ee03c, 0xe14f0000, 0xe92e0001, 0xe59f00e4, 
+    0xe5900000, 0xe92e0001, 0xe59f10d4, 0xe5910000, 0xe580e000, 0xe59f00d0, 0xe1a0e00f, 0xe12fff10, 
+    0xe59f10bc, 0xe5910000, 0xe590e000, 0xe59f00b4, 0xe8be0002, 0xe5801000, 0xe8be0001, 0xe16ff000, 
+    0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 0xe92d0001, 0xe94d2000, 0xe320f000, 0xe24dd004, 
+    0xe8bd0001, 0xe9204000, 0xe1a0e000, 0xe8bd0001, 0xe94e7fff, 0xe320f000, 0xe24ee03c, 0xe14f0000, 
+    0xe92e0001, 0xe59f005c, 0xe5900000, 0xe92e0001, 0xe59f104c, 0xe5910000, 0xe580e000, 0xe59f004c, 
+    0xe1a0e00f, 0xe12fff10, 0xe59f003c, 0xe1a0e00f, 0xe12fff10, 0xe59f1028, 0xe5910000, 0xe590e000, 
+    0xe59f0020, 0xe8be0002, 0xe5801000, 0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 
+    0xe25ef004, 0x00030f20, 0x00030f70, 0x00024c6b, 0x00024afb, 0x41f0e92d, 0x460c4603, 0xea218819, 
+    0x80190104, 0x0104ea41, 0x42806810, 0x8019dcfc, 0x81f0e8bd, 0x41f0e92d, 0xea45880d, 0x800d0502, 
+    0x0502ea25, 0x4284681c, 0x800ddcfc, 0x81f0e8bd, 0xe92d0003, 0xe59f0034, 0xe59f1034, 0xe5801000, 
+    0xe59f0030, 0xee151f31, 0xe5801000, 0xe59f0028, 0xee151f30, 0xe5801000, 0xe59f0020, 0xee161f50, 
+    0xe5801000, 0xe8bd0003, 0xe25ef004, 0xe320f000, 0xc3000010, 0xfec0dead, 0xc300002c, 0xc3000030, 
+    0xc3000034, 0x5ffce92d, 0xf1a59d0d, 0xf04f0c05, 0xfa0b0b01, 0xea4ffa05, 0xb40c0a9a, 0x9a10b403, 
+    0xf1009800, 0xf04f0104, 0xf84d0e00, 0xf04fcd04, 0xb4040900, 0xf8506803, 0x680c503a, 0x603af851, 
+    0x0705eb03, 0x0806eb04, 0x0505eba3, 0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 
+    0xfb36f403, 0xf1c6cc03, 0xfb360600, 0xf8414413, 0xf840c03a, 0xeb02403a, 0xf84002cb, 0xf8417b08, 
+    0xf1098b08, 0x45d10901, 0xafd4f6ff, 0x00caeb00, 0x01caeb01, 0xf10ebc04, 0x45de0e01, 0xafc7f6ff, 
+    0x0b4bea4f, 0x0a5aea4f, 0xcb04f85d, 0x0c01f1ac, 0x0f00f1bc, 0x9800dcb4, 0x0104f100, 0x0e00f04f, 
+    0x2982f645, 0x6803b404, 0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 
+    0xf8400606, 0xf841503a, 0xf840603a, 0xf8417b08, 0xeb028b08, 0x680302cb, 0x503af850, 0xf851680c, 
+    0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 0x68130606, 0x0545ea4f, 0x0646ea4f, 0xfc13fb35, 
+    0xf403fb35, 0xcc03fb36, 0x0600f1c6, 0x4413fb36, 0xc03af841, 0x403af840, 0x120beb02, 0x7b08f840, 
+    0x8b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0806eba4, 0x4426441d, 0x0307eb08, 
+    0x0807eba8, 0x0343ea4f, 0x0848ea4f, 0xf309fb33, 0xf809fb38, 0x303af840, 0x803af841, 0x5b08f840, 
+    0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 0x0606eba4, 
+    0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 0xf8414413, 
+    0xf840c03a, 0xeb02403a, 0xf840120b, 0xf8417b08, 0x68038b08, 0x503af850, 0xf851680c, 0xeb03603a, 
+    0xeb040705, 0xeba50806, 0xeba40503, 0xf8410606, 0xf840503a, 0xf840603a, 0xf8417b08, 0x68038b08, 
+    0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 0x68130606, 0x0545ea4f, 
+    0x0646ea4f, 0xfc13fb35, 0xf403fb35, 0xcc03fb36, 0x0600f1c6, 0x4413fb36, 0xc03af841, 0x403af840, 
+    0x120beb02, 0x7b08f840, 0x8b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0806eba4, 
+    0x4426441d, 0x0307eb08, 0x0807eba8, 0x0343ea4f, 0x0848ea4f, 0xf309fb33, 0xf809fb38, 0x0300f1c3, 
+    0x803af840, 0x303af841, 0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 
+    0x0806eb04, 0x0505eba3, 0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 0xfb36f403, 
+    0xf1c6cc03, 0xfb360600, 0xf8414413, 0xf840c03a, 0xeb02403a, 0xf84002cb, 0xf8417b08, 0xeb008b08, 
+    0xeb0100ca, 0xbc0401ca, 0x0e01f10e, 0xf6ff45de, 0xea4faee9, 0xea4f0b4b, 0x98000a5a, 0x0104f100, 
+    0x0800f04f, 0x2982f645, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0206eb04, 0x0505eba3, 
+    0x0606eba4, 0x503af840, 0x603af841, 0x7b08f840, 0x2b08f841, 0xf8506803, 0x680c503a, 0x603af851, 
+    0x0705eba3, 0x0206eba4, 0x4426441d, 0x0307eb02, 0x0207eba2, 0x0343ea4f, 0x0242ea4f, 0xf309fb33, 
+    0xf209fb32, 0x303af840, 0x203af841, 0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 
+    0x0705eb03, 0x0206eb04, 0x0503eba5, 0x0606eba4, 0x503af841, 0x603af840, 0x7b08f840, 0x2b08f841, 
+    0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0206eba4, 0x4426441d, 0x0307eb02, 0x0207eba2, 
+    0x0343ea4f, 0x0242ea4f, 0xf309fb33, 0xf209fb32, 0x0300f1c3, 0x203af840, 0x303af841, 0x5b08f840, 
+    0x6b08f841, 0x00caeb00, 0x01caeb01, 0x0801f108, 0xf6ff45d8, 0xea4faf89, 0x98000b4b, 0x0104f100, 
+    0x0800f04f, 0x2b08f850, 0x3b08f850, 0x4b08f850, 0xf8516805, 0xf8516b08, 0xf8517b08, 0xf8d19b08, 
+    0xeb02a000, 0xeba20c04, 0xeb060204, 0xeba60409, 0xeb030609, 0xeba30905, 0xeb070305, 0xeba7050a, 
+    0xeb0c070a, 0xebac0a09, 0xeb040c09, 0xeba40905, 0xeb020405, 0xeba20507, 0xeb060207, 0xeba60703, 
+    0xf8400603, 0xf8402908, 0xf8405908, 0xf840c908, 0xf841ab20, 0xf8417908, 0xf8416908, 0xf8414908, 
+    0xf1089b20, 0x45d80801, 0xafbcf6ff, 0x058bea4f, 0xf985fab5, 0x091ef1c9, 0x0c1ff1c9, 0x0b59ea4f, 
+    0x0b01f10b, 0x0901f009, 0xbc0344cb, 0xf850bc0c, 0xf8509b04, 0xf850ab04, 0xf8504b04, 0xeb09790c, 
+    0xeba9060a, 0xf04f090a, 0xfa460800, 0xfa49f60b, 0xfa44f90b, 0xfa47f40b, 0x6016f70b, 0x8000f8c3, 
+    0x9025f842, 0x8025f843, 0x0655ea4f, 0xf842442e, 0xf8434026, 0xf1c77026, 0xf8420700, 0xf8434015, 
+    0xf8dd7015, 0xf04fe030, 0xb4200402, 0x6034f850, 0x0004f100, 0x7034f850, 0x0004f100, 0xf90cfa04, 
+    0xf9a9fa99, 0x0109eba5, 0xf1a1fa91, 0xf10cfa21, 0x01fef001, 0x8031f850, 0x0004f100, 0x1031f850, 
+    0x000cf1a0, 0x0a08eb06, 0x0608eba6, 0x0801eb07, 0x0701eba7, 0x1029f85e, 0x0767ea4f, 0xf511fb36, 
+    0x0600f1c6, 0x5501fb38, 0xf601fb36, 0x0a6aea4f, 0x6611fb38, 0x0105eb0a, 0x0a05ebaa, 0x0806eb07, 
+    0x0706eba7, 0xf10bfa41, 0xf80bfa48, 0xfa0bfa4a, 0xf70bfa47, 0x1029f842, 0x8029f843, 0xeb09bc20, 
+    0xf8420605, 0xf843a026, 0xeba57026, 0xf1c70609, 0xf8420700, 0xf843a026, 0x442e7026, 0x0800f1c8, 
+    0x1026f842, 0x8026f843, 0x0402f104, 0xdb9c42ac, 0x5ffce8bd, 0x00004770, 0x5ffce92d, 0xf04f9e0d, 
+    0xfa0b0b01, 0xea4ff506, 0xf1a60555, 0xf1c90902, 0x68060c1f, 0x9025f850, 0x4015f850, 0x7015f851, 
+    0x0700f1c7, 0x0a09eba6, 0xea4f44b1, 0xea4f0a6a, 0xf8420969, 0xf8429b04, 0xf842ab04, 0xf8424b04, 
+    0xf8dd790c, 0xf04fe030, 0xfa040402, 0xfa99f90c, 0xf850f9a9, 0xf8513029, 0xeba58029, 0xf8500609, 
+    0xf851a026, 0xeb037026, 0xeba3060a, 0xeba8030a, 0x44b80a07, 0x7029f85e, 0x0a6aea4f, 0xfb07fb33, 
+    0xf317fb33, 0xbb17fb38, 0x0800f1c8, 0x0666ea4f, 0x3307fb38, 0x0806eb03, 0x0303eba6, 0x060aeb0b, 
+    0x0b0aebab, 0x8034f842, 0x0204f102, 0x6034f842, 0x0204f102, 0x0809eba5, 0xf8a8fa98, 0xf80cfa28, 
+    0x08fef008, 0x3038f842, 0x0204f102, 0xb038f842, 0x020cf1a2, 0x0402f104, 0xdbb642ac, 0xf1a59d0d, 
+    0xf04f0c01, 0xfa0a0a01, 0xea4ffb05, 0xb4040b9b, 0x98009a0d, 0x0e00f04f, 0x0b5bea4f, 0xcd04f84d, 
+    0x1b08f850, 0x3b08f850, 0x4b08f850, 0x5914f850, 0x6b08f850, 0x7b08f850, 0x8b08f850, 0x9904f850, 
+    0x0c03eb01, 0x0103eba1, 0x0307eb06, 0x0607eba6, 0x0705eb04, 0x0405eba4, 0x0509eb08, 0x0809eba8, 
+    0x0907eb0c, 0x0c07ebac, 0x0705eb03, 0x0305eba3, 0x0508eb01, 0x0108eba1, 0x0804eb06, 0x0604eba6, 
+    0x5908f840, 0xc908f840, 0x1908f840, 0x9b1cf840, 0x6908f840, 0x3908f840, 0x8908f840, 0x7b1cf840, 
+    0x0e01f10e, 0xf6ff45de, 0xf85dafbb, 0xea4fcb04, 0xea4f0b5b, 0xf1ac0a8a, 0x98000c02, 0x0104f100, 
+    0x0e00f04f, 0x2982f645, 0xf8506803, 0x680c503a, 0x603af851, 0x0805eb03, 0x0305eba3, 0x0506eb04, 
+    0x0406eba4, 0x303af840, 0x403af841, 0x8b08f840, 0x5b08f841, 0x503af850, 0x603af851, 0x0545ea4f, 
+    0x0646ea4f, 0x680c6803, 0x0806eba5, 0xfb384435, 0xfb35f809, 0xeb03f509, 0xeba30608, 0xeb040308, 
+    0xeba40805, 0xf8400405, 0xf841303a, 0xf840403a, 0xf8416b08, 0x680c8b08, 0x603af851, 0xf8506803, 
+    0xeba3503a, 0x44330806, 0x0605eb04, 0x0405eba4, 0x303af840, 0x403af841, 0x8b08f840, 0x6b08f841, 
+    0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 0x0506eba5, 
+    0xf809fb38, 0xf509fb35, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x303af840, 0x403af841, 
+    0x6b08f840, 0x8b08f841, 0x00caeb00, 0x01caeb01, 0x0e01f10e, 0xf6ff45de, 0xea4faf87, 0xea4f0b5b, 
+    0xf1ac0a4a, 0x98000c01, 0x0104f100, 0x0e00f04f, 0x6803b404, 0x503af850, 0xf851680c, 0xeb03603a, 
+    0xeba30805, 0xeb040305, 0xeba40506, 0xea4f0406, 0xea4f03e3, 0xea4f04e4, 0xea4f08e8, 0xf84005e5, 
+    0xf841303a, 0xf840403a, 0xf8418b08, 0xeb025b08, 0x680302cb, 0x503af850, 0xf851680c, 0xea4f603a, 
+    0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 
+    0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 0x303af840, 
+    0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 
+    0x680c6803, 0x0806eba5, 0xfb384435, 0xfb35f809, 0xeb03f509, 0xeba30608, 0xeb040308, 0xeba40805, 
+    0xea4f0405, 0xea4f03e3, 0xea4f04e4, 0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8416b08, 
+    0xeb028b08, 0x680302cb, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 
+    0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 
+    0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 
+    0x02cbeb02, 0xf851680c, 0x6803603a, 0x503af850, 0x0806eba3, 0xeb044433, 0xeba40605, 0xea4f0405, 
+    0xea4f03e3, 0xea4f04e4, 0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8418b08, 0xeb026b08, 
+    0x680302cb, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 
+    0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 
+    0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 
+    0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 0x0506eba5, 
+    0xf809fb38, 0xf509fb35, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 
+    0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0xf8506803, 
+    0x680c503a, 0x603af851, 0x0545ea4f, 0xea4f6817, 0xfb350646, 0xf1c5f807, 0xfb350500, 0xfb36f517, 
+    0xfb368817, 0xeb035507, 0xeba30608, 0xeb040308, 0xeba40805, 0xea4f0405, 0xea4f03e3, 0xea4f04e4, 
+    0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8416b08, 0xeb028b08, 0xeb0002cb, 0xeb0100ca, 
+    0xbc0401ca, 0x0e01f10e, 0xf6ff45de, 0xea4faea1, 0xea4f0b5b, 0xf1ac0a4a, 0x98000c01, 0x0104f100, 
+    0x0e00f04f, 0x0900f04f, 0x6803b404, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 
+    0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 
+    0x0405eba4, 0x303af840, 0x403af841, 0x02cbeb02, 0x6b08f840, 0x8b08f841, 0x0901f109, 0xf6ff45d1, 
+    0xeb00afd4, 0xeb0100ca, 0xbc0401ca, 0x0e01f10e, 0xf6ff45de, 0xea4fafc7, 0xea4f0b5b, 0xf1ac0a4a, 
+    0xf1bc0c01, 0xdcb80f00, 0xe8bdbc04, 0x47705ffc, 0x41f0e92d, 0x88079c06, 0x0701ea27, 0x0801ea47, 
+    0x0500f04f, 0xf8a08007, 0x88168000, 0x6025f843, 0x0501f105, 0xdbf542a5, 0xe8bdbf00, 0xe92d81f0, 
+    0x880541f0, 0x0701ea25, 0x0801ea45, 0xf8a08007, 0xf04f8000, 0xf04f0604, 0xf8320500, 0xf8327b02, 
+    0xea488b02, 0xf8434707, 0xf1057b04, 0x42b50501, 0xe8bddbf3, 0x000081f0, 0x5ffce92d, 0xf0f1fb90, 
+    0x9ffce8bd, 0xe92d4001, 0xe14f0000, 0xe3100020, 0x115e00b2, 0x13c00cff, 0x051e0004, 0x03c004ff, 
+    0xe35000fe, 0x0a000007, 0xe35000ff, 0x0a000009, 0xe3500000, 0x0a000001, 0xe8bd4001, 0xe1b0f00e, 
+    0xe8bd4001, 0xeafffc66, 0xe14f0000, 0xe38000c0, 0xe16ff000, 0xea000003, 0xe14f0000, 0xe3c000c0, 
+    0xe16ff000, 0xeaffffff, 0xe8bd4001, 0xe1b0f00e, 0x5ffce92d, 0x0400f04f, 0x5024f851, 0xf6f5fbb0, 
+    0x6024f842, 0x0401f104, 0xf6ff429c, 0xe8bdaff5, 0x00009ffc, 0x0003d59c, 0x0003eb9c, 0xe51f0010, 
+    0xe12fff1e, 0xe92d0003, 0xe59f0010, 0xe59f1010, 0xe5801000, 0xe8bd0003, 0xe25ef004, 0xe320f000, 
+    0xc3000010, 0xdef0dead, 0xe51ff004, 0x0000eec1, 0xe51ff004, 0x00007a73, 0x46c04778, 0xe92d41f0, 
+    0xf10c0080, 0xe59f1028, 0xe5910000, 0xe3500000, 0x0a000003, 0xe3a00000, 0xe5810000, 0xf1080080, 
+    0xe8bd81f0, 0xf1080080, 0xf57ff04f, 0xe320f003, 0xe8bd81f0, 0x000301d4, 0x5ff0e92d, 0x0200f04f, 
+    0x0300f04f, 0x3022f840, 0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0x00009ff0, 0x5ff0e92d, 0x0200f04f, 
+    0x0300f04f, 0x3012f820, 0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0x00499ff0, 0x20c1ea50, 0x2004bf18, 
+    0xbf180d4a, 0x0001f040, 0x72fff240, 0x5f51ebb2, 0xf040bf08, 0x28010002, 0x2005bf08, 0xe92d4770, 
+    0x460441f0, 0x461e4615, 0xf0371e4f, 0xeb000206, 0xe9d101c7, 0xd00d0100, 0x4633462a, 0xf8d0f001, 
+    0xeb041e7f, 0xe9d303c7, 0xf0002300, 0xf037fdf1, 0xd1f10206, 0xd0232f02, 0xd0112f04, 0xd1312f06, 
+    0x4633462a, 0xf8bcf001, 0x230ae9d4, 0xfde0f000, 0x4633462a, 0xf8b4f001, 0x2308e9d4, 0xfdd8f000, 
+    0x4633462a, 0xf8acf001, 0x2306e9d4, 0xfdd0f000, 0x4633462a, 0xf8a4f001, 0x2304e9d4, 0xfdc8f000, 
+    0x4633462a, 0xf89cf001, 0x2302e9d4, 0xfdc0f000, 0x4633462a, 0xf894f001, 0x2300e9d4, 0x41f0e8bd, 
+    0xbdb6f000, 0x81f0e8bd, 0x22004902, 0x46104613, 0xbe6af000, 0x3ff00000, 0xbdaaf000, 0x46132200, 
+    0x46114610, 0xbe60f000, 0xf2402000, 0xf04f3201, 0xf00141e0, 0x0000be9c, 0x20004a02, 0xf0010711, 
+    0x0000be96, 0xfffffd01, 0x41f0e92d, 0x4604460d, 0x5c0af3c1, 0x4b2d4a2c, 0x36fff2ac, 0xda2d2e14, 
+    0xda122e00, 0xfd84f000, 0x46132200, 0xf956f001, 0x2d00d245, 0xf04fbfbc, 0x24004500, 0xea55db3f, 
+    0xbf180004, 0xd1174d22, 0xf8dfe039, 0xfa2cc088, 0xea05f706, 0xea5c0c07, 0xd0320c04, 0xfd68f000, 
+    0x46132200, 0xf93af001, 0x2d00d229, 0xf44fdd03, 0x40f01080, 0x43bd4405, 0xe0202400, 0xdc202e33, 
+    0x3cfff04f, 0x0714f1a6, 0xf707fa2c, 0xd018423c, 0xf95af001, 0x46132200, 0xf920f001, 0x2d00d20f, 
+    0x2e14dd0c, 0x1c6dbf08, 0xf1c6d008, 0x20010134, 0x44204088, 0xbf3842a0, 0x46041c6d, 0x462943bc, 
+    0xe8bd4620, 0x000081f0, 0x8800759c, 0x7e37e43c, 0x3ff00000, 0x000fffff, 0x4df0e92d, 0x461c4616, 
+    0x2800460f, 0xf021b094, 0xf0234100, 0xbf144200, 0x25002501, 0xc410f8df, 0x0547eb05, 0xea4f4465, 
+    0x429d036c, 0x0035d32b, 0x2501bf18, 0x0544eb05, 0x44ac4bfe, 0xd322459c, 0x0306ea52, 0xd0024bfc, 
+    0xd105429f, 0xb014b948, 0x20004619, 0x8df0e8bd, 0xbf082800, 0x0c00f04f, 0xf04fd001, 0xeb0c0c01, 
+    0xf5130347, 0xd80a1f00, 0xbf142e00, 0x0c01f04f, 0x0c00f04f, 0x0344eb0c, 0x1f00f513, 0x4632d907, 
+    0x46394623, 0xe8bdb014, 0xf7ff4df0, 0xf8dfbf35, 0xf04f83a4, 0x2f000a00, 0x4542bfb8, 0x4be6da23, 
+    0xbfa8429a, 0x0a02f04f, 0x4be1da1d, 0xdc1a4293, 0xeb034be2, 0x2b145322, 0xf1c3dd08, 0xfa260c34, 
+    0xfa03f30c, 0x45b4fc0c, 0xe008d10d, 0xf1c3b95e, 0xfa220c14, 0xfa03f30c, 0x4594fc0c, 0xf003d103, 
+    0xf1c30301, 0xea510a02, 0xd11b0300, 0xda192c00, 0xbf182f00, 0x0f02f1ba, 0xf1bad002, 0xd0070f01, 
+    0xf7fe2002, 0xb014fafa, 0x4df0e8bd, 0xbeecf7ff, 0xf7fe2002, 0xf7fffaf2, 0xf081fee7, 0xb0144100, 
+    0x8df0e8bd, 0xd16b0033, 0xd1204542, 0x4280f107, 0x1280f512, 0x2800bf02, 0x49bd2000, 0x48bcd0ef, 
+    0xdc054288, 0xbfa42c00, 0x46214618, 0xe007dae7, 0xda051e20, 0xf080b014, 0x46184100, 0x8df0e8bd, 
+    0x447949b7, 0x0100e9d1, 0xe8bdb014, 0xf8df8df0, 0x4562c2c0, 0x2c00d12a, 0xb139da24, 0xd1174541, 
+    0xbf042800, 0x46022000, 0xe006d11c, 0x2002b140, 0xfab3f7fe, 0xfeb8f7ff, 0x4639460a, 0xbad2f000, 
+    0x46394aa4, 0x2000b014, 0x011ef362, 0x8df0e8bd, 0x463bda08, 0x46614602, 0x2000b014, 0x4df0e8bd, 
+    0xbd02f000, 0xb0144639, 0x8df0e8bd, 0xda174541, 0x4f80f1b4, 0xf1a4d00c, 0xf1b35300, 0xd10f53ff, 
+    0xdb0d1e3b, 0xb0144619, 0x4df0e8bd, 0xbbd8f000, 0x463bb014, 0x46194602, 0x4df0e8bd, 0xbf00f000, 
+    0xf0270005, 0xd1384300, 0x4541b1d1, 0x2f00d135, 0x2c00dd04, 0x2000bfa4, 0xdad44641, 0xdd012f00, 
+    0xdb1f2c00, 0xda162f00, 0xdb142c00, 0x0000f04f, 0x0f01f1ba, 0x497fbf14, 0xb0144982, 0x8df0e8bd, 
+    0x0f02f1ba, 0x2f00bf18, 0xf1bad00c, 0xd1090f01, 0xda072f00, 0x2f00e00b, 0x2c00bfb8, 0xf1bada0d, 
+    0xd0040f01, 0x2000b014, 0xe8bd4601, 0xb0148df0, 0xf04f2000, 0xe8bd4100, 0xf04f8df0, 0x46b80c01, 
+    0x7ce7eb0c, 0xc044f8cd, 0x0c0aea5c, 0xf8dfd00d, 0x4562c1b8, 0xf8dfdd7e, 0x4b6dc1b4, 0xdd124562, 
+    0xdb0a428b, 0xdb182c00, 0x2001e023, 0xfa25f7fe, 0xe8bdb014, 0xf7ff4df0, 0x4a5dbe21, 0xdc02428a, 
+    0xdc0a2c00, 0x4299e015, 0x2c00da02, 0xe004da11, 0x42994b57, 0x2c00dd19, 0x2002dd0b, 0xfa0df7fe, 
+    0xfe12f7ff, 0xb0144a53, 0x021ef361, 0xe8bd4611, 0x20028df0, 0xfa01f7fe, 0xfe0ef7ff, 0xb0144a4c, 
+    0x021ef361, 0xe8bd4611, 0x22008df0, 0xf0014641, 0xf06ff883, 0x46050201, 0xf001460f, 0x4b4dfc98, 
+    0x3255f04f, 0xffa0f000, 0x463b462a, 0xfe68f000, 0x22004b49, 0xff98f000, 0x463b462a, 0x468b4680, 
+    0x46194610, 0xfe5cf000, 0x465b4642, 0xfe58f000, 0x46804b42, 0xf04f4628, 0x910942c0, 0xf0004639, 
+    0x9107fe4f, 0x46404683, 0x4b3c4a3d, 0xf0009909, 0x4a3cfe47, 0x46284680, 0x91014b3b, 0xf0004639, 
+    0x9b01fe3f, 0xf0014642, 0x900cf847, 0x4602460d, 0xe000460b, 0x9907e00e, 0xf0004658, 0x9b07fb59, 
+    0x465a4688, 0x46382700, 0xf836f001, 0x462b9a0c, 0xb976f000, 0x1f80f5b1, 0x0000f04f, 0x4628da07, 
+    0x22354619, 0xfc43f001, 0xf06f4605, 0xeb000034, 0xf3c15221, 0x4b250013, 0x31fff2a2, 0x677ff040, 
+    0xf0474298, 0x91015740, 0xf04fbfd8, 0xdd0c0b00, 0x4281491f, 0xf04fbfc8, 0xdc060b01, 0x0b00f04f, 
+    0xf5a79801, 0x1c401780, 0x481a9001, 0x46394478, 0x00cbeb00, 0xe9d09704, 0x46282300, 0x93099212, 
+    0xfffaf000, 0x0000e028, 0x001fffff, 0x000fffff, 0x3ff00000, 0x7ff00000, 0x43400000, 0xfffffc01, 
+    0x00001da2, 0xfff00000, 0x41e00000, 0x43f00000, 0x3fefffff, 0x3fd55555, 0x3fe00000, 0x3ff71547, 
+    0x652b82fe, 0xf85ddf44, 0x3e54ae0b, 0x0003988e, 0x000bb67a, 0x00001a70, 0x1007e9cd, 0x9b094628, 
+    0x99049a12, 0xfae4f000, 0x20004602, 0x49fe460b, 0xfb9af000, 0x46029100, 0x900c460b, 0x1007e9dd, 
+    0xfdaef000, 0x46889006, 0x447848f8, 0x68009a12, 0xf04f900e, 0xea405000, 0xeb000067, 0xf500408b, 
+    0x9b092100, 0x2700980e, 0xf0009102, 0x9b04ffa5, 0xf000462a, 0x463afec9, 0xf0004643, 0x9104fd91, 
+    0x46384605, 0x9b024641, 0xf0009a0e, 0xe9ddfd89, 0xf0003207, 0x9b04feb9, 0xf000462a, 0x9b00ff8d, 
+    0xf0009a0c, 0x9a06fd7d, 0x91094643, 0x900c4619, 0xf0004610, 0x4605fd75, 0x48dd4602, 0x9107460b, 
+    0x44782106, 0xfc8bf7ff, 0x462a9b07, 0x90009102, 0x46194610, 0xfd64f000, 0x9a009b02, 0xfd60f000, 
+    0x46439a06, 0x46384605, 0x46199100, 0xfa80f000, 0x9a0c9b09, 0xfd54f000, 0x462a9b00, 0xfa78f000, 
+    0x4643463a, 0x90089100, 0x46194610, 0xfd48f000, 0x22004bc8, 0x90049107, 0xfa6af000, 0x9a089b00, 
+    0xfa66f000, 0x460d4bc3, 0x4638463a, 0xff44f000, 0x9a049b07, 0xff40f000, 0x9a089b00, 0xfe64f000, 
+    0x9104463a, 0x4641462b, 0x4610900a, 0xfd28f000, 0x1007e9cd, 0x9a064643, 0x980a9904, 0xfd20f000, 
+    0x4680462b, 0x460d980c, 0x9909463a, 0xfd18f000, 0x462b4642, 0xfa3cf000, 0x46809100, 0x460b4602, 
+    0x1007e9dd, 0xfa34f000, 0x3207e9dd, 0x2000460f, 0xf0004605, 0x9b00ff11, 0xf0004642, 0x4ba6fe35, 
+    0x46284680, 0x4260f04f, 0x46399109, 0xfcf8f000, 0x90049102, 0x4aa14640, 0x99094b9f, 0xfcf0f000, 
+    0x46804a9f, 0x4b9f4628, 0x46399103, 0xfce8f000, 0x46429b03, 0xfa0cf000, 0x447a4a9b, 0x03cbeb02, 
+    0x2300e9d3, 0xfa04f000, 0x98014605, 0xf0009105, 0x9000fc70, 0xe9dd462a, 0x91030304, 0xf0009902, 
+    0x4a92f9f7, 0xeb02447a, 0xe9d303cb, 0x46932300, 0xf0009301, 0x9b03f9ed, 0xf0009a00, 0x9b03f9e9, 
+    0x9a004688, 0x46382700, 0xfec6f000, 0x465a9b01, 0xfec2f000, 0x9a049b02, 0xfebef000, 0x462a9b05, 
+    0xfde2f000, 0x4d789b11, 0xf1aa2200, 0xea530c01, 0x9206030c, 0x4d7ed101, 0xf04f9206, 0x46320a00, 
+    0xf0004623, 0x4623fc9d, 0x46839103, 0x46304652, 0xf0004619, 0x463afea1, 0xf0004643, 0x9b03fc91, 
+    0xf000465a, 0x463af9b5, 0x46064643, 0x4650468b, 0xf0004621, 0x4604fc85, 0x4632460f, 0xf000465b, 
+    0x4a6cf9a7, 0x4291468a, 0xebaadb21, 0xea530302, 0xd1100200, 0x463b4622, 0xfe7ef000, 0x46804a66, 
+    0x4b664630, 0x46599101, 0xf992f000, 0x46429b01, 0xfd64f000, 0x2002d22b, 0xffdff7fd, 0xfbe4f7ff, 
+    0x4629460a, 0xf362b014, 0xe8bd011e, 0x4b5c8df0, 0x4200f02a, 0xd31a429a, 0xeb0a4a5a, 0xea530302, 
+    0xd1080200, 0x463b4622, 0xfe56f000, 0x465b4632, 0xfd44f000, 0x2002d80b, 0xffbff7fd, 0xfbccf7ff, 
+    0x5310ea4f, 0x4629460a, 0x5303ea4f, 0x494ee7da, 0x0800f04f, 0xf02a4a4d, 0x42824000, 0x5120eb01, 
+    0x484bda25, 0x1c80f44f, 0x1c494478, 0xfa2c6802, 0x4450f001, 0x0301f1ac, 0x510af3c0, 0x31fff2a1, 
+    0x0f00f1ba, 0xf301fa23, 0x0c13f3c0, 0x0114f1c1, 0x1c80f44c, 0xf801fa2c, 0x0303ea20, 0xf1c8bfb8, 
+    0x46200800, 0xf0004639, 0x4604fe17, 0x4630460f, 0x46224659, 0xf000463b, 0x4b36f92b, 0x0a00f04f, 
+    0x46529103, 0xf0004650, 0xe9cdfbfb, 0x46501007, 0x4b324a31, 0xf0009903, 0x9102fbf3, 0x463b4622, 
+    0x90049903, 0xf0004650, 0x4632fdf7, 0xf000465b, 0x4a2bfd1b, 0xf0004b2b, 0x9b02fbe3, 0xf0009a04, 
+    0x4607f907, 0x4602468a, 0xe9dd460b, 0xf0001007, 0xe9ddf8ff, 0x46043207, 0xf000460e, 0x463afddd, 
+    0xf0004653, 0x4622fd01, 0x900c4633, 0x4610460f, 0xf0004619, 0x4682fbc5, 0x481b4602, 0x460b468b, 
+    0x44782105, 0x0000e032, 0x3ff00000, 0x00001a5a, 0x0000198a, 0x40080000, 0x3feec709, 0xdc3a03fd, 
+    0x145b01f5, 0xbe3e2fe0, 0x00001862, 0x00001828, 0xbff00000, 0x40900000, 0x652b82fe, 0x3c971547, 
+    0x4090cc00, 0x3f6f3400, 0xfffffc01, 0x3fe00000, 0x0000175c, 0x3fe62e43, 0x0ca86c39, 0xbe205c61, 
+    0xfefa39ef, 0x3fe62e42, 0x0000165a, 0xfaa7f7ff, 0x465b4652, 0xfb84f000, 0x46334622, 0xfcb4f000, 
+    0x46829a0c, 0x463b468b, 0x46314620, 0xfb78f000, 0x463b9a0c, 0xf89cf000, 0x46072200, 0xf04f4650, 
+    0x91004380, 0xf0004659, 0x9103fd77, 0x465b4652, 0x900a4631, 0xf0004620, 0x9b03fb63, 0xf0009a0a, 
+    0x9b00f943, 0xf000463a, 0x4622fd67, 0xf0004633, 0x4b12fd63, 0xf0002200, 0x460efc87, 0x5108eb01, 
+    0x15084604, 0xdc102800, 0x46204642, 0xf0014631, 0xf7fff96e, 0x2804fa50, 0xf7ffbf08, 0x4642facd, 
+    0x46314620, 0xf963f001, 0x98064604, 0x4629460b, 0x4622b014, 0x4df0e8bd, 0xbb32f000, 0x3ff00000, 
+    0x41f0e92d, 0x460f4606, 0xfc6af000, 0x460d0004, 0x2001bf18, 0xf0204328, 0xf1c04000, 0xf100607f, 
+    0x0fc040e0, 0x1c30d00e, 0x2001bf18, 0xf0204338, 0xf1c04000, 0xf100607f, 0x0fc040e0, 0x2001bf04, 
+    0xfe8bf7fd, 0x46294620, 0x81f0e8bd, 0x4200f021, 0x5260f1a2, 0x1f80f5b2, 0x4300f001, 0xf1d2bf28, 
+    0xd90b6c7f, 0x1c00ea5f, 0x02c2ea43, 0x7050eb42, 0x4770bf18, 0xf020bf28, 0x47700001, 0x1f80f5b2, 
+    0x4618bfbc, 0xea4f4770, 0xf51c0c41, 0xd2021f00, 0xf0014608, 0xb570b860, 0xfb8cf000, 0x89000000, 
+    0xbff6f7ff, 0x4000f04f, 0x0080f5a0, 0x00004770, 0xea91b510, 0xbf480f03, 0x4300f083, 0x84e4f100, 
+    0xeb711a84, 0xd2050c03, 0xeb431912, 0x1b00030c, 0x010ceb61, 0xe124f8df, 0x5411ea4f, 0x5c13eba4, 
+    0x0f43ea1e, 0xea9ebf18, 0xd0735f44, 0x030eea23, 0x0e20f1dc, 0x5104ea21, 0x1380f443, 0xfa22d332, 
+    0xeb10fe0c, 0xfa23000e, 0xeb41fe0c, 0xf1cc010e, 0xfa030e20, 0xeb10fe0e, 0xf151000e, 0xf5b10100, 
+    0xf1cc1f80, 0xd2320e20, 0x5104eb01, 0xf20efa12, 0x4010e8bd, 0x4770bf58, 0xbf381c40, 0x0242ea5f, 
+    0x4770bf18, 0xbf142800, 0x0001f020, 0x0100f141, 0x0341ea4f, 0x1f00f513, 0x4770bf38, 0x41c0f1a1, 
+    0xbb76f000, 0xeb432a01, 0xf1ac0203, 0xf1dc0c20, 0xbf320e1f, 0x0e00f04f, 0xf30cfa23, 0x0003eb10, 
+    0x5104eb41, 0x5f11ebb4, 0xeba1d0d0, 0xf5015104, 0x08491180, 0x0030ea5f, 0x5104eb01, 0xf150d30e, 
+    0xbf380000, 0xfe0efa12, 0xe8bdd108, 0xe7c94010, 0xbf381c40, 0x0242ea5f, 0xe7c3d1ca, 0x4010e8bd, 
+    0x0341ea4f, 0x1f00f513, 0x4770bf38, 0x41c0f1a1, 0xbb3ef000, 0x5f44ea9e, 0xea11d008, 0xe8bd0f5e, 
+    0xbf044010, 0x4100f001, 0x47702000, 0x4010e8bd, 0xf000b570, 0xbf00fadf, 0x3ebefb64, 0xffe00000, 
+    0xf04f4902, 0xf0010000, 0xbf00b820, 0x7ff80000, 0xbf581049, 0x4140f1c1, 0xbf58105b, 0x4340f1c3, 
+    0xf3ef428b, 0x47708000, 0x41c0e92d, 0xf8dfb430, 0xea3cc2a0, 0xbf181411, 0x1413ea3c, 0x80ecf000, 
+    0x0503ea81, 0x1411ea1c, 0x74d5ea44, 0xea1cbf18, 0xf0001513, 0xeba480c7, 0xf04f0405, 0xea454500, 
+    0xea4521c1, 0xea4123c3, 0xea435150, 0xf1045352, 0x4299747f, 0x3400f504, 0x20c0ea4f, 0x22c2ea4f, 
+    0x4290bf08, 0x809cf000, 0x6513ea4f, 0x1640f20f, 0xea4f5d76, 0xfb064513, 0xf1c7f705, 0xfb067780, 
+    0xea4ff707, 0xfba737d7, 0x42766803, 0x3880f5c8, 0xce06fba7, 0xf1a8bf38, 0xfb070801, 0xf04fe608, 
+    0xfba60e00, 0xfbe68c02, 0xf1dcce03, 0xf1ce0c00, 0xbf384e00, 0x0e01f1ae, 0x580cfba6, 0x0700f04f, 
+    0x0500f04f, 0x870efbe6, 0xc608fba1, 0xce07fba0, 0x060eeb16, 0x0500f145, 0x6507fbe1, 0x4ee0f115, 
+    0xf5a4bf7e, 0xea5f3480, 0x416d0646, 0x0780f116, 0x0500f145, 0x2717ea4f, 0x6606ea4f, 0x6705ea47, 
+    0x46def1a6, 0x5f80f1b6, 0x2515ea4f, 0x4638d91f, 0x0c01f024, 0x71c4eb05, 0x6ffef1bc, 0x110ceb01, 
+    0xbcf0d802, 0x8100e8bd, 0xbf5c4224, 0x1e80f501, 0x7fc4ea9e, 0xbcf0d402, 0x8100e8bd, 0xd4384224, 
+    0xf1a1bcf0, 0xe8bd41c0, 0xf0004100, 0xea4fba71, 0xea4222d2, 0xea4f5243, 0xfba723d3, 0xea4f8602, 
+    0xea4020d0, 0xfb075041, 0xea1e6603, 0xea4f0f0e, 0xfb0521d1, 0xbf586602, 0x5600eba6, 0x5600ebb6, 
+    0x0e52ea4f, 0x7ec3ea4e, 0x0e0eeb18, 0x0e53eb56, 0xeb18d5bd, 0x415e0802, 0xf1551c7f, 0xe7b60500, 
+    0x1580f44f, 0x0700f04f, 0x0600f04f, 0x0800f04f, 0xbcf0e7ad, 0x0000f04f, 0x41c0f101, 0x4100f001, 
+    0x8100e8bd, 0x1f0cea11, 0x1513ea0c, 0xe00cd000, 0x1f0cea13, 0x8025f000, 0x0000f04f, 0xea81bcf0, 
+    0xf0010103, 0xe8bd4100, 0xbcf08100, 0x4100e8bd, 0x0103ea81, 0xba1cf000, 0xe8bdbcf0, 0xb5704100, 
+    0xf9c8f000, 0x3efc7e09, 0xb807f000, 0x0103ea81, 0x0000f04f, 0x4100f001, 0xea814770, 0xf0000103, 
+    0xbcf0ba07, 0x4100e8bd, 0x0000f04f, 0x47704921, 0xf9fbfdff, 0xf2f4f5f7, 0xebedeef0, 0xe4e6e8e9, 
+    0xdee0e1e3, 0xd8dadbdd, 0xd3d4d5d7, 0xcdcfd0d1, 0xc8cacbcc, 0xc4c5c6c7, 0xbfc0c1c2, 0xbbbcbdbe, 
+    0xb7b8b9ba, 0xb3b4b5b6, 0xafb0b1b2, 0xabacadae, 0xa8a8a9aa, 0xa4a5a6a7, 0xa1a2a3a3, 0x9e9f9fa0, 
+    0x9b9c9c9d, 0x9899999a, 0x95969797, 0x93939495, 0x90919192, 0x8e8e8f8f, 0x8b8c8c8d, 0x89898a8b, 
+    0x87878888, 0x84858586, 0x82838384, 0x80818182, 0x07ff0000, 0x7ff80000, 0x0341ea4f, 0x5353ea4f, 
+    0x6380f5a3, 0x031ef1d3, 0xf1d3bfc8, 0xdd0c0c21, 0x4200f04f, 0x22c1ea42, 0x5250ea42, 0xfc03fa32, 
+    0x7ce1ea8c, 0x70e1ebac, 0x2b104770, 0x2000bfc4, 0xf5034770, 0xf1bc7c78, 0xd0043fff, 0x4200f06f, 
+    0x0021ea82, 0xb5704770, 0xf944f000, 0x80249249, 0x47702000, 0x0000e7f2, 0x5311ea4f, 0x6380f5a3, 
+    0x031ef1d3, 0xf1d3bfa8, 0xdb080c20, 0x4200f04f, 0x22c1ea42, 0x5250ea52, 0xf003fa32, 0x42094770, 
+    0x2b10d40b, 0x2000bfc4, 0xf5034770, 0xf1bc7c78, 0xd0053fff, 0x30fff04f, 0xf04f4770, 0x47700000, 
+    0xf000b570, 0xbf00f917, 0x80249249, 0x47702000, 0xf010e7f0, 0xbf484200, 0xfab04240, 0xfa10f380, 
+    0xd00af103, 0x031df1c3, 0x6380f503, 0x5041ea4f, 0x5203eb02, 0x21d1eb02, 0xf04f4770, 0x47700000, 
+    0xf380fab0, 0xf103fa10, 0xf1c3d00a, 0xf503031d, 0xea4f6380, 0xea4f5041, 0xeb025203, 0x477021d1, 
+    0x0000f04f, 0x00004770, 0x0c03ea51, 0xf51cd417, 0xbf581f80, 0x1f80f5bc, 0x8006f100, 0xbf184299, 
+    0xbf084770, 0x47704290, 0xf511d707, 0xbf581f80, 0x1f80f513, 0x4299d419, 0x42894770, 0xf51c4770, 
+    0xd5081f80, 0x1f80f5bc, 0x428bd5f7, 0x4770bf18, 0x4282bf08, 0xf44f4770, 0xeb1c1c00, 0xbf380f41, 
+    0x0f43eb1c, 0x428bd201, 0xb5704770, 0xf8b2f000, 0x00492492, 0x5100f04f, 0x5380f04f, 0xbdd8f7ff, 
+    0xc148f8df, 0xea1cb570, 0xbf1e1e11, 0x1513ea1c, 0x0f0cea9e, 0x0f0cea95, 0x806ff000, 0x0403ea81, 
+    0x134cea23, 0x7ed4ea4e, 0x114cea21, 0x1180f441, 0x1380f443, 0xfba144ae, 0xfba04c02, 0xf1ae6503, 
+    0x19367e7f, 0x050ceb55, 0x4c03fba1, 0x0300f14c, 0x1c02fba0, 0x060ceb16, 0xf1534165, 0x42090300, 
+    0xf046bf18, 0xf4130601, 0xd10b7f00, 0x3103ea4f, 0x3005ea4f, 0xea410334, 0xea405115, 0xf06f5016, 
+    0xe00a0203, 0x21c3ea4f, 0x20c5ea4f, 0xea4102f4, 0xea405155, 0xf06f5056, 0xeb020202, 0xeb01422e, 
+    0xea855502, 0xd00a71ce, 0x0c44ea5f, 0xf024bf18, 0xf1504400, 0xf1410000, 0xea200100, 0xf24070d4, 
+    0x45627cfe, 0xbd70d200, 0xbf1442a8, 0x4480f04f, 0x4440f04f, 0xbf082e00, 0xf1be2400, 0xbfa86f80, 
+    0x41c0f1a1, 0x4070e8bd, 0x8082f280, 0x0000f04f, 0x41c0f101, 0x4100f001, 0xea9e4770, 0xea0c0f0c, 
+    0xbf181513, 0x0f0cea95, 0xf04fd006, 0xea810000, 0xf00e0e03, 0xbd704100, 0xf81cf000, 0x3e010089, 
+    0xb807f000, 0xb809f000, 0x0c43ea4f, 0x5c5cea5f, 0xea81d008, 0xf0000103, 0xea4fb85b, 0xea5f0c41, 
+    0xd1f65c5c, 0x0000f04f, 0x47704901, 0x07ff0000, 0x7ff80000, 0x0e02f10e, 0x0e03f02e, 0x6b04f85e, 
+    0xd4054236, 0xeb432a01, 0xf5150503, 0xd8121f00, 0xeb412801, 0xf51c0c01, 0xd80c1f00, 0xea4fd10e, 
+    0xf5157cd1, 0xeb0c1f00, 0xf10c0c4c, 0xbf080c02, 0x7cd3eb4c, 0xf04fe004, 0xe0010c08, 0x7cd3ea4f, 
+    0x054ceb0c, 0xf605fa26, 0x0607f006, 0x0c04f1b6, 0xeb0ed206, 0xe8bd0c86, 0xf04c4070, 0x47600c01, 
+    0xf00ce8df, 0x02020b09, 0x4100f04f, 0x0000f04f, 0x2100f5a1, 0x4619bd70, 0x28014610, 0x0401eb51, 
+    0xf5d4bf18, 0xbf841400, 0xf0012000, 0xbd704100, 0xf5a00808, 0xea4f1100, 0x47700131, 0x0c01ea53, 
+    0xf51cd417, 0xbf581f80, 0x1f80f5bc, 0x8006f100, 0xbf18428b, 0xbf084770, 0x47704282, 0xf513d707, 
+    0xbf581f80, 0x1f80f511, 0x428bd419, 0x429b4770, 0xf51c4770, 0xd5081f80, 0x1f80f5bc, 0x4299d5f7, 
+    0x4770bf18, 0x4290bf08, 0xf44f4770, 0xeb1c1c00, 0xbf380f43, 0x0f41eb1c, 0x4299d201, 0xb40f4770, 
+    0xbc03bc0c, 0xbec1f7ff, 0x0f03ea91, 0xf081b510, 0xf53f4100, 0xf083abf5, 0xf0004300, 0x0000b8d5, 
+    0x41f0e92d, 0x1c80f501, 0x1f00f5bc, 0x80a9f2c0, 0x5c11ea4f, 0x510cea21, 0x0cfdf10c, 0x1180f441, 
+    0x0c5cea5f, 0x7cc0f50c, 0x0040d301, 0xa4304149, 0xea410289, 0x02875190, 0x0c0a0e8e, 0xfb045da4, 
+    0xfb02f604, 0xf1c6f606, 0xfba44640, 0x0df66206, 0x2642ea46, 0xf406fb06, 0x2301fba4, 0xf1c34252, 
+    0xbf384340, 0xfba61e5b, 0x24004202, 0x2403fbe6, 0xea420bd2, 0xfba64644, 0xfba12306, 0xfba3e202, 
+    0xfbe3e407, 0x42644261, 0x4e40f1c2, 0xf1aebf38, 0xfba60e01, 0xf04f2304, 0xfbe60200, 0xfba2320e, 
+    0x00344603, 0x6462fbe2, 0xe606fba1, 0xe807fba4, 0x6861fbe4, 0xf1c84276, 0xbf385840, 0x0801f1a8, 
+    0xe406fba2, 0xe508fba3, 0x5468fbe2, 0xe605fba1, 0xe804fba7, 0x8664fbe1, 0x0520f118, 0x0600f156, 
+    0xf1a809a8, 0x09b1081b, 0x083ff008, 0x0f0af1b8, 0x6086ea40, 0xeb01d91c, 0xe8bd510c, 0xbf0081f0, 
+    0xe8eef5fc, 0xd3d8dde2, 0xc3c7cbcf, 0xb6b9bdc0, 0xacaeb1b4, 0xa3a5a7a9, 0x9b9d9fa1, 0x9596989a, 
+    0x8f909293, 0x898b8c8d, 0x85868788, 0x81828384, 0x6800fba0, 0xf201fb00, 0x0842eb08, 0x2887ebb8, 
+    0x1834d507, 0x0401eb58, 0x1c40d5d5, 0x0100f151, 0x1a34e7d1, 0x0401eb78, 0x1e40d4cd, 0x0100f171, 
+    0xea5fe7c9, 0xea5f0c4c, 0xd10d5c9c, 0xf04fd305, 0xf0010000, 0xe8bd4100, 0xe8bd81f0, 0xb57041f0, 
+    0xfea8f7ff, 0xbeffdb6d, 0x41f0e8bd, 0x0000f04f, 0x47704900, 0x7ff80000, 0xea91b510, 0xbf480f03, 
+    0x4300f083, 0xab1cf53f, 0xeb711a84, 0xd2070c03, 0xf08c1912, 0xeb434c00, 0x1b00030c, 0x010ceb61, 
+    0xe1a4f8df, 0x5411ea4f, 0x5c13eba4, 0x0f43ea1e, 0xea9ebf18, 0xf0005f44, 0xea2380b0, 0x4252036e, 
+    0x5104ea21, 0x036eebc3, 0x1e5bbf38, 0x0e20f1dc, 0xfa22d325, 0xeb10fe0c, 0xfa43000e, 0xeb41fe0c, 
+    0xf1cc010e, 0xfa030e20, 0xeb10fe0e, 0xf151000e, 0xf1cc0100, 0xd4290e20, 0xf20efa12, 0x5104eb01, 
+    0x4010e8bd, 0x4770bf58, 0xbf1c1c40, 0x4f00f1b2, 0x28004770, 0x1c49bf0c, 0x0001f020, 0xeb124770, 
+    0xeb430e02, 0xbf180203, 0x0e01f04f, 0x0242ea4e, 0x0c20f1ac, 0x0e1ef1dc, 0xfa43d954, 0xeb10fe0c, 
+    0xf151000e, 0xf1cc31ff, 0xd5d50e1e, 0x0e01f10e, 0xfe0efa12, 0xeb414140, 0xeb010101, 0xea5f5c44, 
+    0xd9105c5c, 0x70deeb10, 0x5104eb01, 0xf1bebf38, 0xe8bd4f00, 0xbf184010, 0x28004770, 0x1c49bf0c, 
+    0x0001f020, 0xd2304770, 0x2cd4ea4f, 0x1100f511, 0x6400f424, 0xfab1d01b, 0x3a0bf281, 0x1ea41aa4, 
+    0x0320f1d2, 0xfa304091, 0x4319f303, 0xeb014090, 0x2c0071cc, 0x5104eb01, 0x4010e8bd, 0x4770bfa8, 
+    0x41c0f101, 0x0000f04f, 0x4100f001, 0xfab04770, 0xfa10f380, 0xd100f103, 0x1ae4bd10, 0x05483c17, 
+    0xe7e40ac9, 0x5104eb01, 0x1049bd10, 0x5104eb01, 0x4010e8bd, 0x0030ea4f, 0xf04fe002, 0x47700100, 
+    0xbf08004a, 0xd0f84200, 0x1f00f5b2, 0x4770bf28, 0x4100f001, 0x0000f04f, 0xea9e4770, 0xd0075f44, 
+    0x0f5eea11, 0x4010e8bd, 0x2100bf04, 0x47702000, 0x4010e8bd, 0xf7ffb570, 0xbf00fdbd, 0x3ef6df40, 
+    0x4100f083, 0x47704610, 0xffe00000, 0xea4f0043, 0xea4f0cd3, 0x40430c3c, 0x0740bf1f, 0x5160f10c, 
+    0x4ffef013, 0xf01c4770, 0xd1036f00, 0xf00c2000, 0x47704100, 0x4300f00c, 0x7050ea43, 0xea40b510, 
+    0xf00000cc, 0xbf00fa22, 0x92000000, 0x0100ea4f, 0xbddef7ff, 0x4100f04f, 0x0000f04f, 0x2100f5a1, 
+    0x00004770, 0x0f01ea90, 0xf081bf48, 0xf1004100, 0x1a42825e, 0x1a80bf3c, 0xea4f1889, 0xf04f52d0, 
+    0xea1c4c7f, 0xeba20f41, 0xbf1853d1, 0x6f02ea9c, 0x803bf000, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 
+    0xfc03fa21, 0x0c0ceb10, 0xf102d21e, 0xea5f32ff, 0xeb40201c, 0xbf3850c2, 0xf01c4770, 0xea4f0f7f, 
+    0xbf180c40, 0x4f7ff1bc, 0x4770bf38, 0x0320f1c3, 0xbf084099, 0x0001f020, 0x4f7ff1bc, 0x4770bf38, 
+    0x40c0f1a0, 0xba17f000, 0x003cea4f, 0xeb400a00, 0xbf2850c2, 0x0ffff01c, 0x0c40ea4f, 0xbf18d0e6, 
+    0x4f7ff1bc, 0x4770bf38, 0xea9ce7ea, 0xd0056f02, 0x0f5cea10, 0xf000bf08, 0x47704000, 0xf000b510, 
+    0xbf00f9b4, 0x3ebefb64, 0xf0004801, 0xbf00ba6e, 0x7fc00000, 0x0c7ff44f, 0x12d0ea1c, 0xea1cbf1e, 
+    0xea9213d1, 0xea930f0c, 0xf0000f0c, 0xea908085, 0xbf480f01, 0x7280f442, 0x0c00f440, 0x0000f441, 
+    0x417ff02c, 0x407ff020, 0x4281b500, 0x0203eba2, 0x1c08f20f, 0x4e50ebac, 0x0000f1c0, 0xe000f89e, 
+    0x0e4eea4f, 0xfc0efb00, 0x0049bf38, 0x1c2cea4f, 0x02faf502, 0xf30efb0c, 0x1eceea4f, 0x2c11ea4f, 
+    0x21c1ea4f, 0x5e63eb0e, 0x4222eb42, 0xfc0cfb0e, 0x531cea4f, 0x1103fb00, 0x2c11ea4f, 0x3101ea4f, 
+    0xfc0cfb0e, 0x4cdcea4f, 0x110cfb00, 0xbf2842c1, 0xeb4c1809, 0xf85d3303, 0xeb10eb04, 0xeb430141, 
+    0xf5b250c2, 0xbf380f7c, 0xd5294770, 0x0ff0f012, 0xf100bf1c, 0xf00040c0, 0x47704000, 0x83828100, 
+    0x87868584, 0x8c8b8988, 0x918f8e8d, 0x96959392, 0x9c9a9997, 0xa2a09f9d, 0xa8a7a5a3, 0xb0aeacaa, 
+    0xb7b5b3b2, 0xc0bebcb9, 0xc9c7c5c2, 0xd4d1cecc, 0xdfdcd9d7, 0xece9e6e2, 0xfaf7f3f0, 0x000000fe, 
+    0x0c40ea4f, 0x7c80f10c, 0x4f7ef1bc, 0x4770bf28, 0x40c0f1b0, 0xb95ff000, 0x0f01ea90, 0x13d1ea0c, 
+    0xf442bf48, 0x45627280, 0x4563bf38, 0xf413d207, 0xd0160f7f, 0x0001ea80, 0x4000f000, 0xb5104770, 
+    0xf903f000, 0x3efc7e09, 0xb805f000, 0x0001ea80, 0x4000f000, 0xea804770, 0xf0000001, 0xf0004000, 
+    0xf412b93a, 0xbf040f7f, 0x47704802, 0x0001ea80, 0xb931f000, 0x7fc00000, 0x0e0b0041, 0x029ef1d3, 
+    0xf450d908, 0xea4f0300, 0xfa232303, 0xbf48f002, 0x47704240, 0xf000b510, 0xbf00f8d8, 0x80249249, 
+    0x47702000, 0x4200f06f, 0x0020ea82, 0x00004770, 0xf1d10dc1, 0xdb06029e, 0x2300ea4f, 0x4300f043, 
+    0xf002fa23, 0x42004770, 0xea4fd507, 0xf1b10140, 0xd2024ffe, 0x0000f04f, 0xb5104770, 0xf8b5f000, 
+    0x80249249, 0x47702000, 0x0020ea6f, 0x00004770, 0x4100f010, 0x4240bf48, 0xf380fab0, 0xf203fa10, 
+    0x039df1c3, 0xea51d00b, 0xeb0151c3, 0x06532012, 0x4770bf38, 0x0001f100, 0xf020bf08, 0x47700001, 
+    0xf380fab0, 0xf203fa10, 0x039df1c3, 0x05d9d00a, 0x2012eb01, 0xbf380653, 0xf1004770, 0xbf080001, 
+    0x0001f020, 0x00004770, 0x0c7ff44f, 0x12d0ea1c, 0xea1cbf1e, 0xea9213d1, 0xea930f0c, 0xf0000f0c, 
+    0xea908047, 0xbf480f01, 0x7280f442, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 0x0203eb02, 0x1301fba0, 
+    0x0200f5a2, 0xbf182900, 0x0301f043, 0xbf28005b, 0x0333ea4f, 0x4222eb42, 0x2c13ea5f, 0x50c2eb4c, 
+    0xebbcbf2e, 0xf5b26f43, 0x47700f7c, 0x6c03ea4f, 0x4f00f1bc, 0xf020bf08, 0xf5b20001, 0xbf380f7c, 
+    0xd50b4770, 0x02fff082, 0x3f80f512, 0x4770bfc8, 0x40c0f100, 0xf000bfd8, 0x47704000, 0x0c00f500, 
+    0x0c4cea5f, 0x4770bf48, 0x40c0f1b0, 0xb873f000, 0x0f01ea90, 0x13d1ea0c, 0xf442bf48, 0x45627280, 
+    0x4563bf38, 0xea80d204, 0xf0000001, 0x47704000, 0xf000b510, 0xbf00f81a, 0x3e010089, 0xb807f000, 
+    0xb809f000, 0x0c41ea5f, 0x6c1cea5f, 0xea80d008, 0xf0000001, 0xea5fb850, 0xea5f0c40, 0xd1f66c1c, 
+    0x4000f04f, 0x0080f5a0, 0xf10e4770, 0xf02e0e02, 0xf85e0e03, 0x42244b04, 0xea4fd404, 0xf1b20241, 
+    0xd8114f7f, 0x0340ea4f, 0x4f7ff1b3, 0xd10ed80c, 0x7cd0ea4f, 0x4f7ff1b2, 0x0c4ceb0c, 0x0c02f10c, 
+    0xeb4cbf08, 0xe0047cd1, 0x0c08f04f, 0xea4fe001, 0xeb0c7cd1, 0xfa24034c, 0xf004f403, 0xf1b40407, 
+    0xd2060c04, 0x0c84eb0e, 0x4010e8bd, 0x0c01f04c, 0xe8df4760, 0x0807f00c, 0xf04f0202, 0xf5a04000, 
+    0xbd100080, 0x00424608, 0xf1d2bf18, 0xbf887280, 0x4000f000, 0x21ffbd10, 0x50d0ea41, 0x477005c0, 
+    0x0f01ea90, 0xf081bf48, 0xf53f4100, 0x1a42ada2, 0xf082d804, 0xeba04200, 0x44110002, 0x52d0ea4f, 
+    0x4c7ff04f, 0x0f41ea1c, 0x53d1eba2, 0xea9cbf18, 0xd04a6f02, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 
+    0xfc03fa21, 0x0c0cebb0, 0xf012d40f, 0xd0360ffe, 0x004cea5f, 0x1200d51d, 0x50c2eb40, 0x4770bf38, 
+    0x0f3ff01c, 0x4770bf18, 0xf1a2e00b, 0xea5f0201, 0xeb40201c, 0xbf3850c2, 0xf01c4770, 0xbf180f7f, 
+    0xf1c34770, 0x40990320, 0x1e40bf14, 0x0001f020, 0x08804770, 0x2312ea4f, 0x4770bf08, 0xfc80fab0, 
+    0x020ceba2, 0x0c28f1cc, 0xf00cfa60, 0x2f12ea93, 0xeb00bf04, 0x477050c2, 0x70c3ea4f, 0x0a134770, 
+    0x10dcea5f, 0x4770bf08, 0xea9ce7f6, 0xd0046f02, 0x0f5cea10, 0x2000bf08, 0xb5104770, 0xff45f7ff, 
+    0x3ef6df40, 0x4000f081, 0xf00c4770, 0x2b09030f, 0x2008bf08, 0x807ff000, 0xd00b2b0a, 0xbf182b08, 
+    0xbf084770, 0x0f40f01c, 0xf04fd00a, 0xf04f0000, 0x47700100, 0x0f40f01c, 0xf04fbf18, 0x47704000, 
+    0x0f10f01c, 0xf020d008, 0xf0004370, 0xea42427f, 0xea4f01d3, 0x47707043, 0x4060f000, 0x427ff021, 
+    0x0200ea42, 0x407ff001, 0x7072ea40, 0xf04f4770, 0xf44c0cff, 0xea1c6ce0, 0xbf1c5311, 0x0c03ea9c, 
+    0xbfc24594, 0xeb0142da, 0x47705102, 0xd00d2b00, 0x0f00f1bc, 0x2a00d00f, 0x4100f001, 0xf041bfa4, 
+    0xf04141e0, 0xf04f617f, 0x47700000, 0x4100f001, 0x0000f04f, 0xea504770, 0xf04f3301, 0xbf180c9b, 
+    0x6c80f04c, 0xaf7cf47e, 0xf04f4770, 0xea1202ff, 0xbf1c52d0, 0x03fff092, 0xbfc2428b, 0xeb0042d1, 
+    0x477050c1, 0xd00a2a00, 0xd00b2b00, 0xf0002900, 0xbfa44000, 0x40fef040, 0x0000f440, 0xf0004770, 
+    0x47704000, 0xf04f0243, 0xbf180c0b, 0x6c80f04c, 0xad0af47f, 0xf41c4770, 0xd0111f80, 0x2fe0f41c, 
+    0xea6fd003, 0x004931cc, 0xf04f4770, 0xf3ef5040, 0xf0228200, 0xea424270, 0xf3820200, 0x47708800, 
+    0x0000f04f, 0xfb904770, 0xfb02f2f1, 0x46100111, 0xfbb04770, 0xfb02f2f1, 0x46100111, 0x02004770, 
+    0x03010604, 0x00160011, 0x0020001b, 0x002a0025, 0x0034002f, 0x003c0039, 0xffffffff, 0xffffffff, 
+    0xffffffff, 0xffffffff, 0xd0035190, 0xd0035192, 0xd0035194, 0xd0035196, 0x03020100, 0x08060504, 
+    0x0d0c0b0a, 0x00100f0e, 0x04030201, 0x0a080605, 0x0e0d0c0b, 0x0100100f, 0x05040302, 0x09080706, 
+    0x0d0c0b0a, 0x0201000e, 0x06050403, 0x0a090807, 0x0e0d0c0b, 0x00000000, 0x00000000, 0x00000001, 
+    0x0000000f, 0x0000000f, 0x0000000e, 0x00000003, 0x00000002, 0x00000002, 0x0000000b, 0x0000000c, 
+    0x0000000d, 0x03020100, 0x08060504, 0x0d0c0b0a, 0x00100f0e, 0x04030201, 0x0a080605, 0x0e0d0c0b, 
+    0x0100100f, 0x05040302, 0x09080706, 0x0d0c0b0a, 0x0000000e, 0x3e083e08, 0x00040004, 0x00040004, 
+    0x00000002, 0x000c000c, 0x000c000c, 0x0000000d, 0xd0033070, 0xd0033270, 0xd0033470, 0xd0033670, 
+    0x3f7ec56d, 0x3f700d1b, 0x3f7240b8, 0x3f833333, 0x41c55c29, 0x41726666, 0x411c28f6, 0xc03f5c29, 
+    0x3f7a8588, 0x3f6cb296, 0x3f6de69b, 0x3f822d0e, 0xc39030a4, 0xc39eb99a, 0xc390651f, 0xc39cd852, 
+    0x00000000, 0x3ff00000, 0x00000000, 0x3ff80000, 0x00000000, 0x00000000, 0x40000000, 0x3fe2b803, 
+    0x00000000, 0x00000000, 0x43cfd006, 0x3e4cfdeb, 0x33333303, 0x3fe33333, 0xdb6fabff, 0x3fdb6db6, 
+    0x518f264d, 0x3fd55555, 0xa91d4101, 0x3fd17460, 0x93c9db65, 0x3fcd864a, 0x4a454eef, 0x3fca7e28, 
+    0x5555553e, 0x3fc55555, 0x16bebd93, 0xbf66c16c, 0xaf25de2c, 0x3f11566a, 0xc5d26bf1, 0xbebbbd41, 
+    0x72bea4d0, 0x3e663769, 0x00000000, 0x00000000, 0xc0c10000, 0x0140c181, 0x03c0c301, 0xc2410280, 
+    0x06c0c601, 0xc7410780, 0xc5c10500, 0x0440c481, 0x0cc0cc01, 0xcd410d80, 0xcfc10f00, 0x0e40ce81, 
+    0xcac10a00, 0x0b40cb81, 0x09c0c901, 0xc8410880, 0x18c0d801, 0xd9411980, 0xdbc11b00, 0x1a40da81, 
+    0xdec11e00, 0x1f40df81, 0x1dc0dd01, 0xdc411c80, 0xd4c11400, 0x1540d581, 0x17c0d701, 0xd6411680, 
+    0x12c0d201, 0xd3411380, 0xd1c11100, 0x1040d081, 0x30c0f001, 0xf1413180, 0xf3c13300, 0x3240f281, 
+    0xf6c13600, 0x3740f781, 0x35c0f501, 0xf4413480, 0xfcc13c00, 0x3d40fd81, 0x3fc0ff01, 0xfe413e80, 
+    0x3ac0fa01, 0xfb413b80, 0xf9c13900, 0x3840f881, 0xe8c12800, 0x2940e981, 0x2bc0eb01, 0xea412a80, 
+    0x2ec0ee01, 0xef412f80, 0xedc12d00, 0x2c40ec81, 0x24c0e401, 0xe5412580, 0xe7c12700, 0x2640e681, 
+    0xe2c12200, 0x2340e381, 0x21c0e101, 0xe0412080, 0x60c0a001, 0xa1416180, 0xa3c16300, 0x6240a281, 
+    0xa6c16600, 0x6740a781, 0x65c0a501, 0xa4416480, 0xacc16c00, 0x6d40ad81, 0x6fc0af01, 0xae416e80, 
+    0x6ac0aa01, 0xab416b80, 0xa9c16900, 0x6840a881, 0xb8c17800, 0x7940b981, 0x7bc0bb01, 0xba417a80, 
+    0x7ec0be01, 0xbf417f80, 0xbdc17d00, 0x7c40bc81, 0x74c0b401, 0xb5417580, 0xb7c17700, 0x7640b681, 
+    0xb2c17200, 0x7340b381, 0x71c0b101, 0xb0417080, 0x90c15000, 0x51409181, 0x53c09301, 0x92415280, 
+    0x56c09601, 0x97415780, 0x95c15500, 0x54409481, 0x5cc09c01, 0x9d415d80, 0x9fc15f00, 0x5e409e81, 
+    0x9ac15a00, 0x5b409b81, 0x59c09901, 0x98415880, 0x48c08801, 0x89414980, 0x8bc14b00, 0x4a408a81, 
+    0x8ec14e00, 0x4f408f81, 0x4dc08d01, 0x8c414c80, 0x84c14400, 0x45408581, 0x47c08701, 0x86414680, 
+    0x42c08201, 0x83414380, 0x81c14100, 0x40408081, 0x0002c750, 0x00030000, 0x00000fa4, 0x00000310, 
+    0x0002cfc0, 0x00047f70, 0x00000018, 0x0000036c, 0x0002cfd8, 0x00047ff0, 0x00000010, 0x0000036c, 
+    0x0002cfc0, 0x00030fa4, 0x0000c598, 0x00000388, 0x0002cfc0, 0x0003d53c, 0x00000060, 0x00000388, 
+    0x0002cfc0, 0x00047800, 0x00000490, 0x00000388, 0x00007fff, 0xfcdc7ff6, 0xf9b87fd9, 0xf6957fa7, 
+    0xf3747f62, 0xf0557f0a, 0xed387e9d, 0xea1e7e1e, 0xe7077d8a, 0xe3f47ce4, 0xe0e67c2a, 0xdddc7b5d, 
+    0xdad87a7d, 0xd7d9798a, 0xd4e17885, 0xd1ef776c, 0xcf047642, 0xcc217505, 0xc94673b6, 0xc6737255, 
+    0xc3a970e3, 0xc0e96f5f, 0xbe326dca, 0xbb856c24, 0xb8e36a6e, 0xb64c68a7, 0xb3c066d0, 0xb14064e9, 
+    0xaecc62f2, 0xac6560ec, 0xaa0a5ed7, 0xa7bd5cb4, 0xa57e5a82, 0xa34c5843, 0xa12955f6, 0x9f14539b, 
+    0x9d0e5134, 0x9b174ec0, 0x99304c40, 0x975949b4, 0x9592471d, 0x93dc447b, 0x923641ce, 0x90a13f17, 
+    0x8f1d3c57, 0x8dab398d, 0x8c4a36ba, 0x8afb33df, 0x89be30fc, 0x88942e11, 0x877b2b1f, 0x86762827, 
+    0x85832528, 0x84a32224, 0x83d61f1a, 0x831c1c0c, 0x827618f9, 0x81e215e2, 0x816312c8, 0x80f60fab, 
+    0x809e0c8c, 0x8059096b, 0x80270648, 0x800a0324, 0x80000000, 0x800afcdc, 0x8027f9b8, 0x8059f695, 
+    0x809ef374, 0x80f6f055, 0x8163ed38, 0x81e2ea1e, 0x8276e707, 0x831ce3f4, 0x83d6e0e6, 0x84a3dddc, 
+    0x8583dad8, 0x8676d7d9, 0x877bd4e1, 0x8894d1ef, 0x89becf04, 0x8afbcc21, 0x8c4ac946, 0x8dabc673, 
+    0x8f1dc3a9, 0x90a1c0e9, 0x9236be32, 0x93dcbb85, 0x9592b8e3, 0x9759b64c, 0x9930b3c0, 0x9b17b140, 
+    0x9d0eaecc, 0x9f14ac65, 0xa129aa0a, 0xa34ca7bd, 0xa57ea57e, 0xa7bda34c, 0xaa0aa129, 0xac659f14, 
+    0xaecc9d0e, 0xb1409b17, 0xb3c09930, 0xb64c9759, 0xb8e39592, 0xbb8593dc, 0xbe329236, 0xc0e990a1, 
+    0xc3a98f1d, 0xc6738dab, 0xc9468c4a, 0xcc218afb, 0xcf0489be, 0xd1ef8894, 0xd4e1877b, 0xd7d98676, 
+    0xdad88583, 0xdddc84a3, 0xe0e683d6, 0xe3f4831c, 0xe7078276, 0xea1e81e2, 0xed388163, 0xf05580f6, 
+    0xf374809e, 0xf6958059, 0xf9b88027, 0xfcdc800a, 0x00008000, 0x0324800a, 0x06488027, 0x096b8059, 
+    0x0c8c809e, 0x0fab80f6, 0x12c88163, 0x15e281e2, 0x18f98276, 0x1c0c831c, 0x1f1a83d6, 0x222484a3, 
+    0x25288583, 0x28278676, 0x2b1f877b, 0x2e118894, 0x30fc89be, 0x33df8afb, 0x36ba8c4a, 0x398d8dab, 
+    0x3c578f1d, 0x3f1790a1, 0x41ce9236, 0x447b93dc, 0x471d9592, 0x49b49759, 0x4c409930, 0x4ec09b17, 
+    0x51349d0e, 0x539b9f14, 0x55f6a129, 0x5843a34c, 0x5a82a57e, 0x5cb4a7bd, 0x5ed7aa0a, 0x60ecac65, 
+    0x62f2aecc, 0x64e9b140, 0x66d0b3c0, 0x68a7b64c, 0x6a6eb8e3, 0x6c24bb85, 0x6dcabe32, 0x6f5fc0e9, 
+    0x70e3c3a9, 0x7255c673, 0x73b6c946, 0x7505cc21, 0x7642cf04, 0x776cd1ef, 0x7885d4e1, 0x798ad7d9, 
+    0x7a7ddad8, 0x7b5ddddc, 0x7c2ae0e6, 0x7ce4e3f4, 0x7d8ae707, 0x7e1eea1e, 0x7e9ded38, 0x7f0af055, 
+    0x7f62f374, 0x7fa7f695, 0x7fd9f9b8, 0x7ff6fcdc, 0x7fff0000, 0x7ff60324, 0x7fd90648, 0x7fa7096b, 
+    0x7f620c8c, 0x7f0a0fab, 0x7e9d12c8, 0x7e1e15e2, 0x7d8a18f9, 0x7ce41c0c, 0x7c2a1f1a, 0x7b5d2224, 
+    0x7a7d2528, 0x798a2827, 0x78852b1f, 0x776c2e11, 0x764230fc, 0x750533df, 0x73b636ba, 0x7255398d, 
+    0x70e33c57, 0x6f5f3f17, 0x6dca41ce, 0x6c24447b, 0x6a6e471d, 0x68a749b4, 0x66d04c40, 0x64e94ec0, 
+    0x62f25134, 0x60ec539b, 0x5ed755f6, 0x5cb45843, 0x5a825a82, 0x58435cb4, 0x55f65ed7, 0x539b60ec, 
+    0x513462f2, 0x4ec064e9, 0x4c4066d0, 0x49b468a7, 0x471d6a6e, 0x447b6c24, 0x41ce6dca, 0x3f176f5f, 
+    0x3c5770e3, 0x398d7255, 0x36ba73b6, 0x33df7505, 0x30fc7642, 0x2e11776c, 0x2b1f7885, 0x2827798a, 
+    0x25287a7d, 0x22247b5d, 0x1f1a7c2a, 0x1c0c7ce4, 0x18f97d8a, 0x15e27e1e, 0x12c87e9d, 0x0fab7f0a, 
+    0x0c8c7f62, 0x096b7fa7, 0x06487fd9, 0x03247ff6, 0x00007fff, 0xfe6e7ffe, 0xfcdc7ff6, 0xfb4a7fea, 
+    0xf9b87fd9, 0xf8277fc2, 0xf6957fa7, 0xf5057f87, 0xf3747f62, 0xf1e47f38, 0xf0557f0a, 0xeec67ed6, 
+    0xed387e9d, 0xebab7e60, 0xea1e7e1e, 0xe8927dd6, 0xe7077d8a, 0xe57d7d3a, 0xe3f47ce4, 0xe26d7c89, 
+    0xe0e67c2a, 0xdf617bc6, 0xdddc7b5d, 0xdc597aef, 0xdad87a7d, 0xd9587a06, 0xd7d9798a, 0xd65c790a, 
+    0xd4e17885, 0xd36777fb, 0xd1ef776c, 0xd07976d9, 0xcf047642, 0xcd9275a6, 0xcc217505, 0xcab27460, 
+    0xc94673b6, 0xc7db7308, 0xc6737255, 0xc50d719e, 0xc3a970e3, 0xc2487023, 0xc0e96f5f, 0xbf8c6e97, 
+    0xbe326dca, 0xbcda6cf9, 0xbb856c24, 0xba336b4b, 0xb8e36a6e, 0xb796698c, 0xb64c68a7, 0xb50567bd, 
+    0xb3c066d0, 0xb27f65de, 0xb14064e9, 0xb00563ef, 0xaecc62f2, 0xad9761f1, 0xac6560ec, 0xab365fe4, 
+    0xaa0a5ed7, 0xa8e25dc8, 0xa7bd5cb4, 0xa69c5b9d, 0xa57e5a82, 0xa4635964, 0xa34c5843, 0xa238571e, 
+    0xa12955f6, 0xa01c54ca, 0x9f14539b, 0x9e0f5269, 0x9d0e5134, 0x9c114ffb, 0x9b174ec0, 0x9a224d81, 
+    0x99304c40, 0x98434afb, 0x975949b4, 0x9674486a, 0x9592471d, 0x94b545cd, 0x93dc447b, 0x93074326, 
+    0x923641ce, 0x91694074, 0x90a13f17, 0x8fdd3db8, 0x8f1d3c57, 0x8e623af3, 0x8dab398d, 0x8cf83825, 
+    0x8c4a36ba, 0x8ba0354e, 0x8afb33df, 0x8a5a326e, 0x89be30fc, 0x89272f87, 0x88942e11, 0x88052c99, 
+    0x877b2b1f, 0x86f629a4, 0x86762827, 0x85fa26a8, 0x85832528, 0x851123a7, 0x84a32224, 0x843a209f, 
+    0x83d61f1a, 0x83771d93, 0x831c1c0c, 0x82c61a83, 0x827618f9, 0x822a176e, 0x81e215e2, 0x81a01455, 
+    0x816312c8, 0x812a113a, 0x80f60fab, 0x80c80e1c, 0x809e0c8c, 0x80790afb, 0x8059096b, 0x803e07d9, 
+    0x80270648, 0x801604b6, 0x800a0324, 0x80020192, 0x80000000, 0x8002fe6e, 0x800afcdc, 0x8016fb4a, 
+    0x8027f9b8, 0x803ef827, 0x8059f695, 0x8079f505, 0x809ef374, 0x80c8f1e4, 0x80f6f055, 0x812aeec6, 
+    0x8163ed38, 0x81a0ebab, 0x81e2ea1e, 0x822ae892, 0x8276e707, 0x82c6e57d, 0x831ce3f4, 0x8377e26d, 
+    0x83d6e0e6, 0x843adf61, 0x84a3dddc, 0x8511dc59, 0x8583dad8, 0x85fad958, 0x8676d7d9, 0x86f6d65c, 
+    0x877bd4e1, 0x8805d367, 0x8894d1ef, 0x8927d079, 0x89becf04, 0x8a5acd92, 0x8afbcc21, 0x8ba0cab2, 
+    0x8c4ac946, 0x8cf8c7db, 0x8dabc673, 0x8e62c50d, 0x8f1dc3a9, 0x8fddc248, 0x90a1c0e9, 0x9169bf8c, 
+    0x9236be32, 0x9307bcda, 0x93dcbb85, 0x94b5ba33, 0x9592b8e3, 0x9674b796, 0x9759b64c, 0x9843b505, 
+    0x9930b3c0, 0x9a22b27f, 0x9b17b140, 0x9c11b005, 0x9d0eaecc, 0x9e0fad97, 0x9f14ac65, 0xa01cab36, 
+    0xa129aa0a, 0xa238a8e2, 0xa34ca7bd, 0xa463a69c, 0xa57ea57e, 0xa69ca463, 0xa7bda34c, 0xa8e2a238, 
+    0xaa0aa129, 0xab36a01c, 0xac659f14, 0xad979e0f, 0xaecc9d0e, 0xb0059c11, 0xb1409b17, 0xb27f9a22, 
+    0xb3c09930, 0xb5059843, 0xb64c9759, 0xb7969674, 0xb8e39592, 0xba3394b5, 0xbb8593dc, 0xbcda9307, 
+    0xbe329236, 0xbf8c9169, 0xc0e990a1, 0xc2488fdd, 0xc3a98f1d, 0xc50d8e62, 0xc6738dab, 0xc7db8cf8, 
+    0xc9468c4a, 0xcab28ba0, 0xcc218afb, 0xcd928a5a, 0xcf0489be, 0xd0798927, 0xd1ef8894, 0xd3678805, 
+    0xd4e1877b, 0xd65c86f6, 0xd7d98676, 0xd95885fa, 0xdad88583, 0xdc598511, 0xdddc84a3, 0xdf61843a, 
+    0xe0e683d6, 0xe26d8377, 0xe3f4831c, 0xe57d82c6, 0xe7078276, 0xe892822a, 0xea1e81e2, 0xebab81a0, 
+    0xed388163, 0xeec6812a, 0xf05580f6, 0xf1e480c8, 0xf374809e, 0xf5058079, 0xf6958059, 0xf827803e, 
+    0xf9b88027, 0xfb4a8016, 0xfcdc800a, 0xfe6e8002, 0x00008000, 0x01928002, 0x0324800a, 0x04b68016, 
+    0x06488027, 0x07d9803e, 0x096b8059, 0x0afb8079, 0x0c8c809e, 0x0e1c80c8, 0x0fab80f6, 0x113a812a, 
+    0x12c88163, 0x145581a0, 0x15e281e2, 0x176e822a, 0x18f98276, 0x1a8382c6, 0x1c0c831c, 0x1d938377, 
+    0x1f1a83d6, 0x209f843a, 0x222484a3, 0x23a78511, 0x25288583, 0x26a885fa, 0x28278676, 0x29a486f6, 
+    0x2b1f877b, 0x2c998805, 0x2e118894, 0x2f878927, 0x30fc89be, 0x326e8a5a, 0x33df8afb, 0x354e8ba0, 
+    0x36ba8c4a, 0x38258cf8, 0x398d8dab, 0x3af38e62, 0x3c578f1d, 0x3db88fdd, 0x3f1790a1, 0x40749169, 
+    0x41ce9236, 0x43269307, 0x447b93dc, 0x45cd94b5, 0x471d9592, 0x486a9674, 0x49b49759, 0x4afb9843, 
+    0x4c409930, 0x4d819a22, 0x4ec09b17, 0x4ffb9c11, 0x51349d0e, 0x52699e0f, 0x539b9f14, 0x54caa01c, 
+    0x55f6a129, 0x571ea238, 0x5843a34c, 0x5964a463, 0x5a82a57e, 0x5b9da69c, 0x5cb4a7bd, 0x5dc8a8e2, 
+    0x5ed7aa0a, 0x5fe4ab36, 0x60ecac65, 0x61f1ad97, 0x62f2aecc, 0x63efb005, 0x64e9b140, 0x65deb27f, 
+    0x66d0b3c0, 0x67bdb505, 0x68a7b64c, 0x698cb796, 0x6a6eb8e3, 0x6b4bba33, 0x6c24bb85, 0x6cf9bcda, 
+    0x6dcabe32, 0x6e97bf8c, 0x6f5fc0e9, 0x7023c248, 0x70e3c3a9, 0x719ec50d, 0x7255c673, 0x7308c7db, 
+    0x73b6c946, 0x7460cab2, 0x7505cc21, 0x75a6cd92, 0x7642cf04, 0x76d9d079, 0x776cd1ef, 0x77fbd367, 
+    0x7885d4e1, 0x790ad65c, 0x798ad7d9, 0x7a06d958, 0x7a7ddad8, 0x7aefdc59, 0x7b5ddddc, 0x7bc6df61, 
+    0x7c2ae0e6, 0x7c89e26d, 0x7ce4e3f4, 0x7d3ae57d, 0x7d8ae707, 0x7dd6e892, 0x7e1eea1e, 0x7e60ebab, 
+    0x7e9ded38, 0x7ed6eec6, 0x7f0af055, 0x7f38f1e4, 0x7f62f374, 0x7f87f505, 0x7fa7f695, 0x7fc2f827, 
+    0x7fd9f9b8, 0x7feafb4a, 0x7ff6fcdc, 0x7ffefe6e, 0x7fff0000, 0x7ffe0192, 0x7ff60324, 0x7fea04b6, 
+    0x7fd90648, 0x7fc207d9, 0x7fa7096b, 0x7f870afb, 0x7f620c8c, 0x7f380e1c, 0x7f0a0fab, 0x7ed6113a, 
+    0x7e9d12c8, 0x7e601455, 0x7e1e15e2, 0x7dd6176e, 0x7d8a18f9, 0x7d3a1a83, 0x7ce41c0c, 0x7c891d93, 
+    0x7c2a1f1a, 0x7bc6209f, 0x7b5d2224, 0x7aef23a7, 0x7a7d2528, 0x7a0626a8, 0x798a2827, 0x790a29a4, 
+    0x78852b1f, 0x77fb2c99, 0x776c2e11, 0x76d92f87, 0x764230fc, 0x75a6326e, 0x750533df, 0x7460354e, 
+    0x73b636ba, 0x73083825, 0x7255398d, 0x719e3af3, 0x70e33c57, 0x70233db8, 0x6f5f3f17, 0x6e974074, 
+    0x6dca41ce, 0x6cf94326, 0x6c24447b, 0x6b4b45cd, 0x6a6e471d, 0x698c486a, 0x68a749b4, 0x67bd4afb, 
+    0x66d04c40, 0x65de4d81, 0x64e94ec0, 0x63ef4ffb, 0x62f25134, 0x61f15269, 0x60ec539b, 0x5fe454ca, 
+    0x5ed755f6, 0x5dc8571e, 0x5cb45843, 0x5b9d5964, 0x5a825a82, 0x59645b9d, 0x58435cb4, 0x571e5dc8, 
+    0x55f65ed7, 0x54ca5fe4, 0x539b60ec, 0x526961f1, 0x513462f2, 0x4ffb63ef, 0x4ec064e9, 0x4d8165de, 
+    0x4c4066d0, 0x4afb67bd, 0x49b468a7, 0x486a698c, 0x471d6a6e, 0x45cd6b4b, 0x447b6c24, 0x43266cf9, 
+    0x41ce6dca, 0x40746e97, 0x3f176f5f, 0x3db87023, 0x3c5770e3, 0x3af3719e, 0x398d7255, 0x38257308, 
+    0x36ba73b6, 0x354e7460, 0x33df7505, 0x326e75a6, 0x30fc7642, 0x2f8776d9, 0x2e11776c, 0x2c9977fb, 
+    0x2b1f7885, 0x29a4790a, 0x2827798a, 0x26a87a06, 0x25287a7d, 0x23a77aef, 0x22247b5d, 0x209f7bc6, 
+    0x1f1a7c2a, 0x1d937c89, 0x1c0c7ce4, 0x1a837d3a, 0x18f97d8a, 0x176e7dd6, 0x15e27e1e, 0x14557e60, 
+    0x12c87e9d, 0x113a7ed6, 0x0fab7f0a, 0x0e1c7f38, 0x0c8c7f62, 0x0afb7f87, 0x096b7fa7, 0x07d97fc2, 
+    0x06487fd9, 0x04b67fea, 0x03247ff6, 0x01927ffe, 0x50102000, 0x68284808, 0x64244404, 0x74345414, 
+    0x62224202, 0x72325212, 0x6a2a4a0a, 0x7a3a5a1a, 0x61214101, 0x71315111, 0x69294909, 0x79395919, 
+    0x65254505, 0x75355515, 0x6d2d4d0d, 0x7d3d5d1d, 0x41231fb2, 0x04611a07, 0x1a04255a, 0x8f1a0479, 
+    0x04a11a04, 0x2a04cb1a, 0x082220f3, 0x4b04cf1a, 0x1a240913, 0xe11a0857, 0x04f11a04, 0x1a0a0123, 
+    0x7f23042f, 0x04b31a33, 0x230c7d1a, 0xaf1a0b01, 0x04cb1a04, 0x2304e71a, 0x291a0c19, 0x0d072304, 
+    0x1a0e6b23, 0xd71a048b, 0x0f592304, 0x1a04751a, 0xbd1a0491, 0x10ef2304, 0x1b110b23, 0x190c2e33, 
+    0x2f0b4b04, 0x1c351a70, 0x1a04471a, 0x8b1a1c27, 0x12452304, 0x1a046d1a, 0xe71a04a3, 0x135d2304, 
+    0x1a04711a, 0xc51a0499, 0x04ed1a04, 0x1a173923, 0x271a04e3, 0x04591a44, 0x1a323723, 0x711a0455, 
+    0x04851a04, 0x1a04951a, 0x691a04ff, 0x3001231c, 0x1a141b23, 0x3b1a042b, 0x153d1b04, 0x1bcc1980, 
+    0x1940340b, 0x04371a04, 0xfc398829, 0x4b1b1922, 0x0819b81a, 0x6904a71a, 0x04220918, 0x1a30d91a, 
+    0x2b1a3c09, 0x20631b04, 0x1b0419d4, 0x19b818ef, 0x1c7f2310, 0x29049d1a, 0x08f51a28, 0x1a1eab23, 
+    0x9d1b04bd, 0x2819141f, 0x1128ab1a, 0x1a048023, 0xd01a04c0, 0x04f01a04, 0x82107231, 0x1affb201, 
+    0x20690104, 0x12010159, 0x8101ff3a, 0x01122169, 0x03013203, 0x48297c92, 0x01999a2b, 0x333fa93c, 
+    0x3fd3d301, 0x78492119, 0x69931109, 0x292701b2, 0x12087248, 0x5a225207, 0x38410402, 0x8ce70410, 
+    0xae0ded28, 0x8ef34d3f, 0xf4247453, 0x1bdd6988, 0x0266ffff, 0x130107ff, 0xff3fff1f, 0x0203ff07, 
+    0x1102013a, 0x0c0fff1b, 0xe20a0f1a, 0x01011a03, 0xae5a0381, 0x016579ae, 0x23802244, 0x190814da, 
+    0xffd4751a, 0xffe80dff, 0xfff580ff, 0xfffb0bff, 0xfffe74ff, 0xffffa2ff, 0x851a38ff, 0x5c121838, 
+    0xcaffffc7, 0xceffffe6, 0xb2fffff8, 0x4afffffd, 0x021c239d, 0x1a04e61a, 0x3b1a044f, 0x1a38e948, 
+    0x2b1e2cbb, 0x4effffcf, 0x04be1a68, 0x1a047923, 0x361a385e, 0x34641a40, 0x3278941a, 0x18ae1af8, 
+    0x1920551a, 0x38ff2a9b, 0x18082a23, 0xffc8680a, 0xfff10eff, 0x1a14b4ff, 0x4a1a2ce4, 0x3c581a24, 
+    0xfffacf1e, 0x2340edff, 0xb81a031d, 0x0cc01a18, 0x197cd12a, 0x16042338, 0xf6b70a18, 0xf499ffff, 
+    0x7c42ffff, 0xfffc7d36, 0x561ad0ff, 0x30971a28, 0x1a44c51a, 0xc31a0478, 0x4cd41a0c, 0x29183e1a, 
+    0x400a1a38, 0xffcc921e, 0x111871ff, 0x6a1a0922, 0xf925273c, 0x11a3ffff, 0x1e30771a, 0xfffff7a9, 
+    0x1c231cb7, 0x38ef1a0b, 0x29acc11a, 0x1a8f2338, 0xd0490e18, 0xe845ffff, 0xf578ffff, 0x7cf9ffff, 
+    0x1ab0e01a, 0x351ac034, 0x1a973228, 0x6dc238eb, 0x34233819, 0xab0a183e, 0xafffffe5, 0xbaffffd3, 
+    0x60181a3c, 0x1a549b1a, 0x2e1acccf, 0xb8bd1a8c, 0x1a0cf21a, 0xf81a4450, 0xe0165a04, 0x180e9423, 
+    0xffd2320a, 0xfff25eff, 0x1aa0feff, 0x281a1809, 0x328a3228, 0x7c361a3d, 0x1a3cc91a, 0xc6320479, 
+    0x413c691a, 0x54c72118, 0xaa63e771, 0x553173b8, 0x2a9839dc, 0x154c1cee, 0x8aa60e77, 0xc553073b, 
+    0xe2a9839d, 0x1a1fc1ce, 0xb01a1f60, 0x1f581a1f, 0x181fac1a, 0x6f4d5622, 0x37a64c76, 0x9bd3a63b, 
+    0xcde9531d, 0x66f4a98e, 0xb37a54c7, 0xd9bdaa63, 0xecde5531, 0x1a1f2a98, 0x8a1a1f15, 0x1fc51a1f, 
+    0x1a1fe21a, 0xb81a1f71, 0x1fdc1a1f, 0x1a1fee1a, 0x3b1a1f77, 0x1f9d1a1f, 0x0113ce52, 0x49023901, 
+    0x29102907, 0x390a190d, 0x20281105, 0xf6d9c40d, 0x7b6ce206, 0xbdb67103, 0xdedb3881, 0x6f6d9c40, 
+    0x37b6ce20, 0x1bdb6710, 0x1fedb388, 0x1a1f861a, 0x611a1fc3, 0x1fb01a1f, 0x1a1f581a, 0x961a1f2c, 
+    0x1fcb1a1f, 0x1a1fe51a, 0x392a1f72, 0x6016181f, 0xb03881ab, 0xd89c40d5, 0x6cce206a, 0xb6671035, 
+    0x5bb3881a, 0x65ad1a46, 0x1965561a, 0x1fdb1a1f, 0x1a1f6d1a, 0xdb1a1fb6, 0x9ded2a1f, 0x9c79aa69, 
+    0xac39b349, 0x0d181e29, 0x42108425, 0x21084212, 0x10842109, 0x0b081a0b, 0x1a0b841a, 0x211a0b42, 
+    0x1a14690b, 0x021a0b04, 0x14011a0b, 0xa1201811, 0x50425294, 0x2821294a, 0x941094a5, 0x4a084a52, 
+    0xa5842529, 0x52421294, 0x2921094a, 0x1a1484a5, 0x211a1442, 0x14101a14, 0x1f21081b, 0x1a1f101a, 
+    0x841a1f08, 0x1f421a1f, 0x1a1f211a, 0x081a1f10, 0xa4842a1f, 0xc9b649c1, 0x2c801a05, 0x0a2c401a, 
+    0xa99c2010, 0x0b901ab0, 0x1a0b481a, 0x521a14a4, 0x14291a14, 0x1a14941a, 0xa51a144a, 0x1a14191f, 
+    0xa4141448, 0x10140494, 0x08140242, 0x84230121, 0x08422310, 0x65198819, 0x11651911, 0x1f196519, 
+    0x1a1f081a, 0x421a1f84, 0x1f211a1f, 0x9a8e106a, 0xa5b90501, 0x0a181301, 0x100f0e10, 0x0110100f, 
+    0x35390410, 0x3a010139, 0x01ffff14, 0x02fffe1c, 0x144e2908, 0x1a04fffd, 0xfe1604fb, 0x06ffffff, 
+    0x0dfff614, 0x09fff31c, 0xfff9140e, 0xffe71411, 0xffe6141d, 0x1402120f, 0x142affea, 0x143affc8, 
+    0x1214ffd2, 0xffc51411, 0xff8f145e, 0x1cb51a6d, 0x6f143f12, 0x1014d3ff, 0x8116d8ff, 0xecffe5ff, 
+    0xfe1f1810, 0xfc4202dc, 0xfb3c0469, 0xfb9704c4, 0xfd2403be, 0xff1401e1, 0x147f121b, 0x14f0ff28, 
+    0x1691ff2d, 0xfff1ffc1, 0xff93144b, 0xffa21471, 0xffef163b, 0x142effec, 0x1c38ffc6, 0x7816ffd6, 
+    0x1afff114, 0x19ffe31c, 0x78071a18, 0x1290f73a, 0xb4fa1a0a, 0xfc1c0212, 0x5a0405ff, 0xc449ba03, 
+    0x10011b02, 0x131e481b, 0xfd21fa20, 0x62261f23, 0x4f2ac628, 0xd62ffe2d, 0x0a35d932, 0x283c6b39, 
+    0x43cb4020, 0x4c1047cf, 0x55585092, 0x5fc25a67, 0x6b72656f, 0x788e71cf, 0x87437fb2, 0x97c58f47, 
+    0xff101002, 0xd5024d3f, 0x5e019701, 0x09013601, 0x2018f001, 0x029a3fff, 0x02090252, 0x018b01b4, 
+    0x013a0158, 0x02fb3fff, 0x026602af, 0x01e60221, 0x106f0193, 0xe902371c, 0x6208181c, 0x2d015701, 
+    0x1e100601, 0x01da020e, 0x511c2c86, 0x18422e01, 0x8b3fff10, 0xef024202, 0x7f01a401, 0x27015001, 
+    0x3c651a10, 0x01d90a18, 0x017b019e, 0x102a014b, 0x02e80e18, 0x024f0292, 0x01c901f8, 0x1060019d, 
+    0x31016b15, 0xdd011301, 0xb612c212, 0x1880a01a, 0xcc022f0a, 0x3f01bd01, 0x1a4e0801, 0x081e10d2, 
+    0x9a01ab02, 0x02061a8a, 0x2312d132, 0x37122d12, 0x4b124112, 0x11025512, 0x02dd165f, 0xc01e0180, 
+    0x5eff7d1b, 0x78ff71ff, 0x6aff6bff, 0x93ff80ff, 0x66ff81ff, 0xa3ff73ff, 0xbaffdfff, 0x2f010eff, 
+    0x1a3c1909, 0x086901ff, 0x0a961902, 0x176b0128, 0x6503ffff, 0x74230102, 0x23302348, 0x23157c23, 
+    0x1e230ed8, 0x08c9230b, 0x23073c23, 0x4e23061a, 0x04b32305, 0x23043e1a, 0x8d1a03db, 0x044f1a04, 
+    0x2304231a, 0xd51a02f4, 0x04b91a04, 0x1a049c1a, 0x781a0489, 0x04691a04, 0x1a04611a, 0x4d1a045b, 
+    0x044e1a04, 0x1a044b1a, 0x461a0441, 0x04441a04, 0x5a08405a, 0x581a044c, 0x04631a04, 0x1a04711a, 
+    0x8c1a0483, 0x04931a04, 0x29609a5a, 0x04b81a04, 0x1a04c71a, 0xef1a04d3, 0x04f91a04, 0x1a880a1a, 
+    0x481a0425, 0x04541a04, 0x1a04831a, 0xb71a04a6, 0x04df1a04, 0x1a04fd1a, 0x541abc1b, 0x04711a04, 
+    0x1a04a31a, 0xf41a04d0, 0xdc1f1a04, 0x1a045d1a, 0xdc1a0493, 0xf02a1a04, 0x1a047f1a, 0x472304e9, 
+    0x04a01a07, 0x2304f91a, 0xc41a085a, 0x09252304, 0x23049e1a, 0xc21a0a1b, 0x0b592304, 0x2304ce1a, 
+    0x4f230c7e, 0x0e3d230d, 0x230f3223, 0x6c231026, 0x128f2311, 0x2313e023, 0x9c231542, 0x17af1b16, 
+    0x2c191a40, 0xa7231b22, 0x1ea9231c, 0x23212723, 0x2c232365, 0x29372326, 0x232c1823, 0x38232ea5, 
+    0x36042332, 0x23393923, 0x3c1b3e4c, 0x4722c042, 0x234acc23, 0x68235075, 0x5b032355, 0x1b610223, 
+    0x22cc6497, 0x70fb236b, 0x23778e23, 0xb01b7dd8, 0x871a7c83, 0x238e22a8, 0xe52391ab, 0x98d92397, 
+    0x239e1423, 0xdde39f72, 0xfdfd749d, 0x257102fd, 0x03ff1b02, 0x3c270f1e, 0x04025c0b, 0x81041f1a, 
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x0004c000, 0xffffffff, 0x02388175, 0x38e5566b, 0x58123170, 0xcb7212d0, 0xe0600090, 0x5411e030, 
+    0x0090f0fe, 0xf004e067, 0x00900670, 0xf004e066, 0xe0660090, 0xa30cffb4, 0x07ffb4e0, 0x167ffde4, 
+    0xe4b93112, 0x11f510f5, 0xe0830490, 0x1e7ff0a3, 0x8e807412, 0xe50f8f0e, 0x1313130e, 0x04901f54, 
+    0x54eff083, 0xe5117010, 0xce05780f, 0x13ce13c3, 0x3f54f9d8, 0x3b0a12ff, 0xe0110490, 0x01642f60, 
+    0x0a020370, 0x1104903a, 0x0302b4e0, 0x90843a02, 0xb4e01104, 0x35020303, 0x11049060, 0x0304b4e0, 
+    0x90ce1102, 0xb4e01104, 0x4f020305, 0x0490e40b, 0x0490f048, 0x13c3e000, 0x2013e0a3, 0x04905fe0, 
+    0x13c3e000, 0x9056e030, 0xd3e08304, 0x4d400394, 0xe0890490, 0x1a7f4760, 0xefb37412, 0x3d700154, 
+    0xa8dd6212, 0xaa05a904, 0xff74c306, 0x740df59f, 0x0cf59aff, 0xf599ff74, 0x98ff740b, 0x607f0af5, 
+    0xff7dea7e, 0x0dabff7c, 0x0ba90caa, 0x2612c3f8, 0x7d0a4018, 0x121e7f02, 0x0402b931, 0x840490c9, 
+    0x900d70e0, 0x60e08304, 0x7f027d07, 0xb9311203, 0xe0830490, 0x02037014, 0x60044403, 0x10040203, 
+    0xe0840490, 0x027d0760, 0x3112017f, 0x12897fb9, 0x54efb374, 0xff13c307, 0x041c6014, 0x02020360, 
+    0x3f0490a8, 0x120360e0, 0xa575e171, 0xffa67510, 0x75efa775, 0x7d22109a, 0x12d17f18, 0x13efa774, 
+    0x703f5413, 0x04a4751d, 0x7503a675, 0x9e75ffa7, 0x189c75d1, 0x007e0d7f, 0x007c007d, 0x02a36b12, 
+    0x187dcb73, 0x7412d17f, 0x1313efa7, 0x01643f54, 0x74121870, 0x0370ef9f, 0x753a0a02, 0xa67550a4, 
+    0xffa77503, 0x75d19e75, 0x867f189c, 0xefb37412, 0x09f50154, 0x74121a60, 0x3c0490bf, 0x01e030e0, 
+    0xa4f5e422, 0x75fea675, 0x9a75ffa7, 0x0a721286, 0x7502a475, 0xa775fda6, 0x859a75ff, 0x90e17112, 
+    0x30e00104, 0x6d1203e0, 0x128b7f90, 0x54efb374, 0x000e750f, 0x967d0ff5, 0x7412ffe4, 0x0354efa7, 
+    0xf07513c3, 0xf0aea410, 0x42ee0f42, 0x7d0faf0e, 0xba3d1202, 0x12000490, 0x3d12b63d, 0x7f027db2, 
+    0xb9311202, 0x90af2112, 0xc3e00004, 0x13e0a313, 0x9023e020, 0x60e08904, 0x01a4751d, 0x75fea675, 
+    0x9a75ffa7, 0xd0a47563, 0x7503a675, 0x9e75ffa7, 0x189c75d1, 0xa4751b80, 0x03a67550, 0x75ffa775, 
+    0x9c75d19e, 0xa4f5e418, 0x75fea675, 0x9a75ffa7, 0x01a47563, 0x75fea675, 0x9a75ffa7, 0x10a57585, 
+    0x75ffa675, 0x9a75efa7, 0x0b049010, 0x22f004e0, 0xe03f0490, 0x71120360, 0x480490e1, 0x7ff00174, 
+    0xb37412f6, 0xf50154ef, 0x12f87f09, 0x54efb374, 0x6413c307, 0x75527001, 0xa67502a4, 0xffa775fd, 
+    0xe4f59a75, 0xf0640090, 0xe0500090, 0x12017dff, 0x0090ba3d, 0xffe0a350, 0x3d12017d, 0x7ffde4ba, 
+    0xb9311205, 0x036009e5, 0x12c27412, 0x0090ef72, 0xe030e051, 0xbe741203, 0x753c6412, 0xa67501a4, 
+    0xffa775fe, 0x80f59a75, 0x6400900f, 0x040970e0, 0x7ffde4f0, 0xb9311204, 0x037009e5, 0xe43a0a02, 
+    0xa675a4f5, 0xffa775fe, 0x22f69a75, 0xe03f0490, 0x04905f60, 0x0670e002, 0xe03e0490, 0x71125370, 
+    0x000490e1, 0xa313c3e0, 0xe02013e0, 0xe4967d3b, 0xa77412ff, 0xc30354ef, 0x752d6013, 0xa67501a4, 
+    0xffa775fe, 0x75d19e75, 0xa475179c, 0xfea67501, 0xe4ffa775, 0x9c759ef5, 0xa4f5e496, 0x75fea675, 
+    0x9e75ffa7, 0x179c75d1, 0xe03d0490, 0x80f00144, 0x0490e405, 0xa575f040, 0xffa67520, 0x75dfa775, 
+    0x1e7f109a, 0xefae7412, 0x54131313, 0x6001641f, 0x0a04901f, 0x7ff004e0, 0xb374121d, 0x750754ef, 
+    0x0ff5000e, 0x12027dff, 0x027dba3d, 0x1f80077f, 0xe0840490, 0x1a600164, 0x74121d7f, 0x0754efb3, 
+    0xf5000e75, 0x027dff0f, 0x7dba3d12, 0x12067f02, 0x0490b931, 0x8b050248, 0xe0830490, 0x1f700264, 
+    0xe0400490, 0x04901960, 0xf001743f, 0x027f027d, 0x7dba3d12, 0x12157f02, 0x0080b931, 0x90c90402, 
+    0xb4e04004, 0x76500025, 0xf8470490, 0x02732828, 0x0502d604, 0xd1090280, 0x02a40502, 0x0502a405, 
+    0xce0502a4, 0x02ce0502, 0x0702ce05, 0xe4050214, 0x026f0602, 0x0702e309, 0x4c070231, 0x02600702, 
+    0x0802b307, 0x320902e1, 0x02420902, 0x0a028106, 0xb308020f, 0x026b0702, 0x04026b07, 0x6b0702b6, 
+    0x026b0702, 0x07026b07, 0x6b07026b, 0x026b0702, 0x07026b07, 0x2709026b, 0x028b0802, 0x04908b08, 
+    0xf001743f, 0x12ff027d, 0x027dba3d, 0x3112157f, 0x01a475b9, 0x75fea675, 0x9a75ffa7, 0x04902219, 
+    0xf001743f, 0xe03d0490, 0x7ff0fe54, 0x7dff7eff, 0x12ff7cff, 0x7312a36b, 0x3f0490cb, 0x901160e0, 
+    0x70e00204, 0x3e049006, 0x120570e0, 0x0f808643, 0x75a4f5e4, 0xa775dfa6, 0x109a75ff, 0x7fb56e12, 
+    0xb374128b, 0x750f54ef, 0x0ff5000e, 0xffe4967d, 0xefa77412, 0x13c30354, 0xa410f075, 0x0f42f0ae, 
+    0xaf0e42ee, 0x12027d0f, 0x0490ba3d, 0xb63d1200, 0x7db23d12, 0x121a7f02, 0x0090b931, 0xb63d1250, 
+    0x12500090, 0x027db53d, 0x3112197f, 0x40a575b9, 0x75ffa675, 0x9a75bfa7, 0x121e7f10, 0x13efae74, 
+    0x1f541313, 0xf0830490, 0xe0830490, 0x07600764, 0x74400490, 0x9022f001, 0x70e00204, 0x3e04900f, 
+    0x900960e0, 0x13744004, 0x420902f0, 0xef285a12, 0x03700264, 0x753a0a02, 0xa67580a4, 0xffa7757f, 
+    0xe4019a75, 0xa675a4f5, 0xffa7757f, 0x90019a75, 0x06744004, 0x571222f0, 0x0264ef61, 0x0a020370, 
+    0x6157123a, 0x700164ef, 0x3a0a0203, 0xef076b12, 0x03700264, 0x903a0a02, 0x60e04904, 0x6001641a, 
+    0x81060203, 0xe0000490, 0x78e0a3fe, 0x13c3ce02, 0xf9d813ce, 0x9072e030, 0xfee00004, 0x0778e0a3, 
+    0xce13c3ce, 0x20f9d813, 0x1e7f5fe0, 0x12546f12, 0x0090c86c, 0x0490e05f, 0xa3fee000, 0xce0278e0, 
+    0x13ce13c3, 0x0490f9d8, 0x08e03020, 0x74a3f0e4, 0x0680f005, 0x74a3f0e4, 0x097ff014, 0x7dba6f12, 
+    0x12267f04, 0x7412b931, 0x5604908b, 0x7112f0ef, 0x4004900e, 0x12f00b74, 0x70ef7474, 0x3a0a0203, 
+    0x90536312, 0x60e04d04, 0x0490e4e5, 0x0490f048, 0x0490f04a, 0x94c3e04a, 0x02034004, 0x0490f407, 
+    0x2864e041, 0xb4e00460, 0x04900b29, 0x0164e04a, 0x07020370, 0x490490f4, 0xb41660e0, 0x04902c01, 
+    0xa3fee000, 0xce0278e0, 0x13ce13c3, 0xe030f9d8, 0x00049019, 0xe0a3fee0, 0xc3ce0778, 0xd813ce13, 
+    0x06e020f9, 0x5c0490e4, 0x04900580, 0xf001745c, 0xf05e0490, 0xe0490490, 0x400294c3, 0x02a4753c, 
+    0x75f0a675, 0x9a75ffa7, 0x03a57518, 0x75ffa675, 0x9a75fca7, 0x40049018, 0x22f00974, 0x400490e4, 
+    0xa4f5e4f0, 0x75f0a675, 0x9a75ffa7, 0xa5f5e418, 0x75ffa675, 0x9a75fca7, 0x7d6c1218, 0x020360ef, 
+    0x04903a0a, 0x01b4e05c, 0x5e04900b, 0x700164e0, 0xe3070203, 0xefec6b12, 0x03700264, 0x903a0a02, 
+    0x60e08a04, 0xfb080203, 0xeff36012, 0x03700264, 0x7d3a0a02, 0x12277f04, 0x0490b931, 0x13ffe03c, 
+    0x303f5413, 0x04900fe0, 0x0164e04c, 0x65120760, 0x0c02bf96, 0xd2441222, 0x700264ef, 0x3a0a0203, 
+    0xe07b0490, 0x08020360, 0x5c04908b, 0x0502b4e0, 0x80f00174, 0x5c049018, 0x7d1270e0, 0x12287f04, 
+    0x3712b931, 0x0264ef24, 0x0a020370, 0x5c04903a, 0x600164e0, 0x3a070203, 0xe05e0490, 0x740602b4, 
+    0x0702f001, 0xe638123a, 0x903a0702, 0x64e04c04, 0x90096001, 0x04e04a04, 0x8a0602f0, 0xe0490490, 
+    0x08020360, 0x0004909f, 0xe0a3fee0, 0xc3ce0278, 0xd813ce13, 0x03e020f9, 0x909f0802, 0x30e00404, 
+    0x7f540ce7, 0x450490ff, 0x9f5e12f0, 0x04907980, 0xf8c4e000, 0xa3c8f054, 0x0f54c4e0, 0x64035448, 
+    0x90646002, 0xfee00004, 0x0778e0a3, 0xce13c3ce, 0x20f9d813, 0x049051e0, 0xc4ffe087, 0xe0200f54, 
+    0x7f049046, 0x13c4ffe0, 0xe0300754, 0x50009013, 0xa313c3e0, 0x1f5413e0, 0xe41094d3, 0x13500094, 
+    0xe0500090, 0xe0a313c3, 0xd31f5413, 0x94e41694, 0x12144000, 0x64ef6429, 0x02037002, 0x04903a0a, 
+    0x0360e07b, 0x90600702, 0x60e08904, 0x4104901c, 0x602c64e0, 0x40049014, 0x12f01674, 0x0490c32d, 
+    0x2c64e041, 0x0a020360, 0x4c04903a, 0x600164e0, 0x00049037, 0xe0a3fee0, 0xc3ce0778, 0xd813ce13, 
+    0x24e020f9, 0x5d0490e4, 0x795b12f0, 0x700264ef, 0x3a0a0203, 0xe05d0490, 0x0490ef60, 0xf001748a, 
+    0xe44c0702, 0xf08a0490, 0xefb87412, 0x04902c60, 0xa3fee000, 0xce0778e0, 0x13ce13c3, 0xe020f9d8, 
+    0x4c049019, 0x600164e0, 0x40049011, 0x12f02274, 0x64ef035e, 0x02037002, 0x047d3a0a, 0x3112297f, 
+    0xb74912b9, 0x020360ef, 0x1a7f3a0a, 0xefb37412, 0x03600154, 0xe4d10902, 0xa675a4f5, 0xffa775df, 
+    0x75109a75, 0xa67520a4, 0xffa775df, 0x12109a75, 0x74c3dd62, 0x74ff9fff, 0x74fe9eff, 0x74fd9dff, 
+    0x78fc9cff, 0x29261203, 0x0c8e0d8f, 0x0a8c0b8d, 0x7dfeffe4, 0x0dabfc01, 0x0ba90caa, 0x12c30aa8, 
+    0x06401826, 0xff7fff7e, 0x0cae0480, 0x04900daf, 0xa3f0ee12, 0x0490f0ef, 0xf004e00c, 0x743e0490, 
+    0x027df001, 0x31120e7f, 0x0490e4b9, 0x0490f085, 0x90f00448, 0xf0044004, 0x7f049022, 0x1313ffe0, 
+    0xe0303f54, 0x49049015, 0x120870e0, 0x64ef7061, 0x904f6002, 0x54e07f04, 0x1f7ff0fb, 0x90b77112, 
+    0x15744004, 0x80a475f0, 0x757fa675, 0x9a75ffa7, 0x83049010, 0x90f0ff74, 0x01744804, 0x747412f0, 
+    0x901f60ef, 0xffe00804, 0x131313c4, 0xe0200154, 0x8b0490d4, 0x90ce70e0, 0xf0044c04, 0x02a67212, 
+    0xef228106, 0x400015b4, 0xcd110203, 0xf84b0a90, 0x02732828, 0x0a028a0a, 0xcd110297, 0x02cd1102, 
+    0x0b02ee0a, 0x2c0d025a, 0x02640d02, 0x0d029c0d, 0xdf0d02c0, 0x023c0e02, 0x0e028b0e, 0xcd1102c3, 
+    0x02040f02, 0x1002ed0f, 0x1d1102c5, 0x02881002, 0xa475bb11, 0x3fa67580, 0x75ffa775, 0x7f220d9a, 
+    0xae74120d, 0x70e4007e, 0x6014ef48, 0x17601412, 0x3d700224, 0xe0480490, 0x11020370, 0x900080cd, 
+    0x01741104, 0x906e0c02, 0x01743f04, 0x0490e4f0, 0x7212f011, 0x121a7fa6, 0x54efb374, 0x02037001, 
+    0xa475610d, 0xdfa67520, 0x75ffa775, 0x0d02109a, 0x02017f61, 0x0d7f3610, 0x7eae7412, 0x5f70e400, 
+    0x326014ef, 0x143d6014, 0x03244660, 0x90d35170, 0x94e05300, 0x52009000, 0x400094e0, 0xa3fee00b, 
+    0xeea4f5e0, 0x3480a5f5, 0xef3f7412, 0x7412a4f5, 0xa5f5ee3f, 0x72122680, 0xa4f5efcb, 0xeecb7212, 
+    0x1880a5f5, 0x07ad38af, 0xe4a4f5ed, 0x0c80a5f5, 0xefdd6212, 0x6212a4f5, 0xa5f5eedd, 0x020e9a75, 
+    0x0d7f610d, 0x7eae7412, 0x0360e400, 0xefcd1102, 0x0370fe24, 0x14030c02, 0x0c020370, 0x03701429, 
+    0x14720c02, 0x0c020370, 0x036014cb, 0x90cd1102, 0xffe01104, 0x400194d3, 0xc044ef07, 0x361002ff, 
+    0xe0490490, 0x400194d3, 0x02d27f05, 0x04903610, 0x0c70e048, 0xe0110490, 0x500094d3, 0xcd110203, 
+    0xe0110490, 0x7f0094d3, 0x7f024000, 0x4e049001, 0x0e7ff0ef, 0x90807412, 0xf0ee2404, 0x12f0efa3, 
+    0x158fff4b, 0x94d315e5, 0xe5084000, 0xff604415, 0x90361002, 0x05741104, 0x240490f0, 0xe0a3fee0, 
+    0xf5eea4f5, 0x0e9a75a5, 0x90610d02, 0x70e04804, 0x1104900c, 0x0094d3e0, 0x11020350, 0x110490cd, 
+    0x4e0490e0, 0x110490f0, 0x12f00174, 0x0d02e173, 0x3f049061, 0x90f00174, 0xd3e01104, 0x20400194, 
+    0x5a0090e4, 0x90f0a3f0, 0xa3f05800, 0x7f027ef0, 0x017bfdf8, 0x0079017a, 0xe4892612, 0xf0650090, 
+    0x90867012, 0xd3e04e04, 0x80948064, 0x0240007f, 0x0490017f, 0x02f0ef11, 0x0490610d, 0xd3ffe011, 
+    0x10400194, 0xe0650090, 0x44f054c4, 0x4eeffec0, 0x361002ff, 0xe0490490, 0x400194d3, 0x02d27f05, 
+    0x04903610, 0x0c70e048, 0xe0110490, 0x500094d3, 0xcd110203, 0x74650090, 0x0490f001, 0x94d3e011, 
+    0x40007f00, 0x90017f02, 0xf0ef4e04, 0x74110490, 0x90578002, 0xffe01104, 0x400194d3, 0x65009010, 
+    0xf054c4e0, 0xeffec044, 0x1002ff4e, 0x49049036, 0x0194d3e0, 0xd27f0540, 0x90361002, 0x70e04804, 
+    0x1104900c, 0x0094d3e0, 0x11020350, 0x650090cd, 0x90f00174, 0xd3e01104, 0x007f0094, 0x017f0240, 
+    0xef4e0490, 0x110490f0, 0x12f00374, 0x7112b069, 0x8510020e, 0x74120d7f, 0x14f5efae, 0x7e8094c3, 
+    0x50017b00, 0x2f007409, 0x0434eef9, 0x80740880, 0xeef91425, 0x12fa0434, 0x128ea325, 0x13e513f5, 
+    0x12e5a4f5, 0x9a75a5f5, 0x8510020e, 0x74120d7f, 0x14f5efae, 0x74120e7f, 0x00127580, 0x14e5138f, 
+    0xe58094c3, 0x7b007c14, 0x240a5001, 0x34ecf900, 0x80effa04, 0xf9802409, 0xfa0434ec, 0x251213e5, 
+    0x851002de, 0x74120d7f, 0x007eefae, 0x5024017b, 0x0034eef9, 0xa32512fa, 0x13f5128e, 0x12e5a4f5, 
+    0x9a75a5f5, 0x8510020e, 0x74120e7f, 0x00127580, 0x07c0138f, 0x74120d7f, 0x007eefae, 0x5024017b, 
+    0x0034eef9, 0x7ffb0e02, 0xae74120d, 0xc314f5ef, 0x1e508094, 0x007cfdef, 0x0024017b, 0x0434ecf9, 
+    0xa32512fa, 0xf5001375, 0x2d017412, 0x0434ecf9, 0x14e51d80, 0x7b007cfd, 0xf9802401, 0xfa0434ec, 
+    0x75a32512, 0x12f50013, 0xf92d8174, 0xfa0434ec, 0x42a32512, 0x13e5e413, 0x12e5a4f5, 0x9a75a5f5, 
+    0x8510020e, 0x74120e7f, 0x8f128e80, 0x120d7f13, 0xf5efae74, 0x8094c314, 0xe5ff12e5, 0x007cfd14, 
+    0x1450017b, 0xecf90024, 0xeffa0434, 0x74de2512, 0xecf92d01, 0x12800434, 0xecf98024, 0xeffa0434, 
+    0x74de2512, 0xecf92d81, 0xe5fa0434, 0xde251213, 0x7f851002, 0xae74120d, 0xfd14f5ef, 0x017b007c, 
+    0xecf95024, 0x12fa0034, 0x1375a325, 0x7412f500, 0xecf92d51, 0x12fa0034, 0x1342a325, 0xf513e5e4, 
+    0xf512e5a4, 0x0e9a75a5, 0x7f851002, 0x8074120e, 0x138f128e, 0xc0ff12e5, 0x120d7f07, 0x7eefae74, 
+    0x24017b00, 0x34eef950, 0xe0d0fa00, 0xafde2512, 0x7f07c013, 0xae74120d, 0x7b007eef, 0xf9512401, 
+    0xfa0034ee, 0x2512e0d0, 0xb91102de, 0xe0110490, 0x400194d3, 0xe90f0203, 0x74120d7f, 0xe4007eae, 
+    0x11020360, 0x6014efcd, 0x03701444, 0x24c50f02, 0x02036002, 0xfde4cd11, 0x3112117f, 0x650090b9, 
+    0x90f00174, 0xfee05a00, 0x4effe0a3, 0x027c0a70, 0x027ef77d, 0x0880f77f, 0xffff24ef, 0xfeff34ee, 
+    0xee580090, 0xf0efa3f0, 0x0f02ffe4, 0x580090e6, 0xe0a3fee0, 0x0024017b, 0x3e0174f9, 0xa32512fa, 
+    0xf5001275, 0xe5a4f513, 0x75a5f512, 0x00900e9a, 0xa3fee05a, 0x0090ffe0, 0x06b5e058, 0xb5e0a309, 
+    0x017f0407, 0xffe40280, 0x904d7412, 0xfee05800, 0x4effe0a3, 0x027e0670, 0x0880f77f, 0xffff24ef, 
+    0xfeff34ee, 0xee580090, 0xf0efa3f0, 0x0090e422, 0x0090f065, 0xf0a3f05a, 0xf0580090, 0x027ef0a3, 
+    0x7bfdf87f, 0x79017a01, 0x89261200, 0x7402017f, 0x80557f4d, 0x11049049, 0x94d3ffe0, 0x900f4001, 
+    0xc4e06500, 0x4044f054, 0xff4eeffe, 0x0d7f3080, 0xefae7412, 0x7f1ce230, 0xb37412d9, 0x640154ef, 
+    0x7f106001, 0xb37412d9, 0xc40154ef, 0x8044f054, 0x900b80ff, 0xd3e04904, 0x05400194, 0x7402d27f, 
+    0x4804902e, 0x900c70e0, 0xd3e01104, 0x03500094, 0x90cd1102, 0x01746500, 0x110490f0, 0x0094d3e0, 
+    0x0240007f, 0x0490017f, 0x90f0ef4e, 0x04741104, 0x120d7ff0, 0x90efae74, 0x12f01704, 0x04901c46, 
+    0xa3fee024, 0xeea4f5e0, 0x9a75a5f5, 0xb911020e, 0x743f0490, 0x90e4f001, 0xa3f05a00, 0x580090f0, 
+    0x7ef0a3f0, 0xfdf87f02, 0x017a017b, 0x26120079, 0x0090e489, 0x7012f065, 0x4e049086, 0x8064d3e0, 
+    0x007f8094, 0x017f0240, 0x80110490, 0x02f07553, 0x24a438e5, 0xe582f5c1, 0xf57734f0, 0xfe93e483, 
+    0xff930174, 0xe0160490, 0xef007cfd, 0x3eecff2d, 0x2f0074fe, 0x017482f5, 0xe083f53e, 0xf5001275, 
+    0xe5a4f513, 0x75a5f512, 0x04900e9a, 0xc3ffe016, 0x0640ff94, 0x007f007e, 0x04ef0380, 0x160490ff, 
+    0x1102f0ef, 0x02f075ca, 0x24a438e5, 0xe582f5c1, 0xf57734f0, 0xfe93e483, 0xff930174, 0xe0160490, 
+    0x007cfdf9, 0xecff2def, 0x0074fe3e, 0x7482f52f, 0x83f53e01, 0xc3e9fde0, 0x0440ff94, 0x06800079, 
+    0xe0160490, 0x0490f904, 0x75f0e916, 0x38e502f0, 0xf5c124a4, 0x34f0e582, 0xe483f577, 0x0174fe93, 
+    0xfbe9ff93, 0x2bef007a, 0xfe3eeaff, 0xf52f0074, 0x3e017482, 0x75e083f5, 0x13f50012, 0xff94c3e9, 
+    0x007f0440, 0x04900680, 0xff04e016, 0xef160490, 0xe505aff0, 0xeda4f513, 0xeefe1245, 0x9a75a5f5, 
+    0x120f800e, 0xf5efef68, 0xef6812a4, 0x75a5f5ee, 0x74120e9a, 0xf5e42295, 0x1404901a, 0x03e730e0, 
+    0x75b21502, 0xa67520a4, 0xffa775df, 0x90119a75, 0x70e04904, 0x007afb12, 0x66121a79, 0x8e158f74, 
+    0x8c138d14, 0x90728012, 0xfee02404, 0xc3ffe0a3, 0x64eef094, 0x407f9480, 0x94efd30b, 0x8064ee0f, 
+    0x07408094, 0xe0170490, 0x7f1ce120, 0x80741234, 0xe09533ee, 0x0a78fcfd, 0xc03c2612, 0xc005c004, 
+    0x7f07c006, 0x7f1a8035, 0x80741236, 0xe09533ee, 0x0a78fcfd, 0xc03c2612, 0xc005c004, 0x7f07c006, 
+    0xb3741237, 0x02d003d0, 0x00d001d0, 0x15f54feb, 0xe914f5ea, 0xf5e813f5, 0x7a007b12, 0x12167900, 
+    0x1b756c53, 0x901c8f00, 0xfee03804, 0xe4ffe0a3, 0x1078fdfc, 0xa83c2612, 0xaa05a904, 0xa307ab06, 
+    0xe0a3fee0, 0xff4febff, 0xe9fe4eea, 0xeffce8fd, 0xeeff1525, 0xedfe1435, 0xecfd1335, 0xabfc1235, 
+    0xa914aa15, 0xd312a813, 0x40182612, 0xffff7408, 0x80fcfdfe, 0x38049038, 0xe0a3fee0, 0xfdfce4ff, 
+    0x26121078, 0xa904a83c, 0xab06aa05, 0xfee0a307, 0xebffe0a3, 0x4eeaff4f, 0xe8fde9fe, 0x1525effc, 
+    0x1435eeff, 0x1335edfe, 0x1235ecfd, 0x8e158ffc, 0x8c138d14, 0x641ce512, 0x601b4501, 0x2404900a, 
+    0xa30270e0, 0x122e70e0, 0x1ae5e34a, 0x017f0470, 0x007f0280, 0x3333c4ef, 0x8044c054, 0xc41ce5fc, 
+    0x4ce05433, 0x770490fe, 0xffedfde0, 0xee140490, 0xf0efa3f0, 0x62009022, 0xfce4ffe0, 0x0478fefd, 
+    0xab3c2612, 0xa914aa15, 0xd312a813, 0x50182612, 0x66150203, 0x277effe4, 0x19abfcfd, 0x17a918aa, 
+    0x12d316a8, 0x1f501826, 0x7ecc7fe4, 0xa8fcfd07, 0x18261216, 0x15020350, 0x17049066, 0xd34054e0, 
+    0x03500094, 0x12661502, 0x0490e34a, 0x0154e017, 0x400094d3, 0x2404901e, 0xe0a3fee0, 0x8064eeff, 
+    0x09508094, 0xff0124ef, 0x80fe3ee4, 0x7f007e26, 0x90208000, 0xfee02404, 0xd3ffe0a3, 0x64ee0094, 
+    0x40809480, 0xff24ef0a, 0xff34eeff, 0x7e0480fe, 0x90007f00, 0xf0ee2404, 0x90f0efa3, 0xffe01704, 
+    0x94d30254, 0x02035000, 0x04908714, 0x7060e049, 0xd30454ef, 0x02400094, 0x04906680, 0x0154e017, 
+    0x400094d3, 0x2404902d, 0x0470f4e0, 0xf064e0a3, 0xc17f1270, 0x7f5f6a12, 0x5f6a1201, 0x7504a575, 
+    0x2a80ffa6, 0x7502a575, 0xa775ffa6, 0x049a75fd, 0x04902e80, 0x0470e024, 0x0f64e0a3, 0x3f7f1670, 
+    0x7f5f6a12, 0x5f6a12ff, 0x7504a575, 0x9a75ffa6, 0x36150232, 0x7502a575, 0xa775ffa6, 0x049a75fd, 
+    0x7502a575, 0xa775ffa6, 0x049a75fd, 0x90361502, 0xffe01704, 0x94d30454, 0x02035000, 0xc4ef2d15, 
+    0x60140354, 0x59601449, 0x24696014, 0x02036003, 0x04903615, 0xa3fee026, 0x94c3ffe0, 0x8064ee04, 
+    0x0a408094, 0x13e7a2ee, 0x007e13ef, 0x007e0680, 0xe0270490, 0xc3ff0154, 0xe0270490, 0x04900494, 
+    0x8064e026, 0x007d8094, 0x017d0240, 0x04904280, 0x0154e017, 0x7f0094d3, 0x7f024000, 0x80fde401, 
+    0x1704902f, 0xd30154e0, 0x007f0094, 0x017f0240, 0x1c80017d, 0xe0260490, 0xa313e7a2, 0x015413e0, 
+    0x12017dff, 0x04908848, 0x54e0a326, 0xfde4ff01, 0x80884812, 0x24049009, 0x12ffe0a3, 0x7312546f, 
+    0x0490e457, 0xf0a3f038, 0xf0a3f0a3, 0x7b0e7112, 0x79007a00, 0x7466121a, 0x148e158f, 0x128c138d, 
+    0x75a4f5e4, 0xa775dfa6, 0x119a75ff, 0x15af2c80, 0x13ad14ae, 0x107812ac, 0x90292612, 0xf0ee3804, 
+    0xa3f0efa3, 0xa3f014e5, 0x12f015e5, 0xf5e40e71, 0xdfa675a4, 0x75ffa775, 0x0490119a, 0x54e0a324, 
+    0x751bf57f, 0x0490001c, 0xe5ffe077, 0x1ce5fe1b, 0x0490ff4f, 0xa3f0ee14, 0x8f22f0ef, 0xe1147512, 
+    0x751f1575, 0xe5d3ff13, 0x94806412, 0x7f1c4080, 0xb3741246, 0xff3f54ef, 0x207d007e, 0x7312007c, 
+    0x9533efb4, 0x7f168fe0, 0xc33f8045, 0x806412e5, 0x1c508094, 0x7412487f, 0x3f54efb3, 0x7d007eff, 
+    0x12007c20, 0x33efb473, 0x168fe095, 0x1a80477f, 0x7412447f, 0x3f54efb3, 0x7d007eff, 0x12007c20, 
+    0x33efb473, 0x168fe095, 0x7412437f, 0x3f54efb3, 0x7d007eff, 0x12007c20, 0x33efb473, 0x178fe095, 
+    0xe0530490, 0x17020360, 0x12347f80, 0x1a8e8074, 0x04901b8f, 0x90fbe04e, 0xf5e01c04, 0xf5e0a320, 
+    0x22148521, 0x85231585, 0x1bad2413, 0x16af1aac, 0x8fba5112, 0x62049018, 0x904d60e0, 0xfbe04e04, 
+    0xe01c0490, 0xe0a320f5, 0x148521f5, 0x23158522, 0xad241885, 0xaf1aac1b, 0xb8401216, 0xef510490, 
+    0x12e5d3f0, 0x80948064, 0x90e00740, 0x80f06704, 0x12e5c317, 0x80948064, 0xe0510490, 0x04900650, 
+    0x0480f065, 0xf0630490, 0xe54e0490, 0x0490f016, 0xf01ae51c, 0xf01be5a3, 0xe0620490, 0xf0530490, 
+    0x6412e5d3, 0x40809480, 0xef18af14, 0xefe09533, 0xa675a4f5, 0xffa775c0, 0x80469a75, 0x12e5c32f, 
+    0x80948064, 0x18af1450, 0xe09533ef, 0x75a4f5ef, 0xa775c0a6, 0x489a75ff, 0x18af1280, 0xe09533ef, 
+    0x75a4f5ef, 0xa775c0a6, 0x449a75ff, 0xe0620490, 0xe5d35660, 0x94806412, 0x7d124080, 0x12207f05, 
+    0x0490356c, 0x7dfbe061, 0x80207f05, 0x12e5c336, 0x80948064, 0xe0600490, 0x50007afb, 0x7f017d14, 
+    0x12007e02, 0x04903e6c, 0x7dfbe061, 0x80027f01, 0x7f037d12, 0x12007e08, 0x04903e6c, 0x7dfbe061, 
+    0x7e087f03, 0x516d1200, 0xe0540490, 0x18020360, 0x12367fbc, 0x1a8e8074, 0x04901b8f, 0x90fbe04f, 
+    0xf5e01e04, 0xf5e0a320, 0x22148521, 0x85231585, 0x1bad2413, 0x17af1aac, 0x8fba5112, 0x62049019, 
+    0x904d60e0, 0xfbe04f04, 0xe01e0490, 0xe0a320f5, 0x148521f5, 0x23158522, 0xad241985, 0xaf1aac1b, 
+    0xb8401217, 0xef500490, 0x12e5d3f0, 0x80948064, 0x90e00740, 0x80f06804, 0x12e5c317, 0x80948064, 
+    0xe0500490, 0x04900650, 0x0480f066, 0xf0640490, 0xe54f0490, 0x0490f017, 0xf01ae51e, 0xf01be5a3, 
+    0xe0620490, 0xf0540490, 0x6412e5d3, 0x40809480, 0xef19af10, 0xa675a4f5, 0xffa775c0, 0x80459a75, 
+    0x12e5c327, 0x80948064, 0x19af1050, 0x75a4f5ef, 0xa775c0a6, 0x479a75ff, 0x19af0e80, 0x75a4f5ef, 
+    0xa775c0a6, 0x439a75ff, 0xe0620490, 0xe5d35660, 0x94806412, 0x7d124080, 0x12107f04, 0x0490356c, 
+    0x7dfbe061, 0x80107f04, 0x12e5c336, 0x80948064, 0xe0600490, 0x50007afb, 0x7ffde414, 0x6c12fe01, 
+    0x6104903e, 0xfde4fbe0, 0x80fe017f, 0x7f027d14, 0x12007e04, 0x04903e6c, 0x7dfbe061, 0x7e047f02, 
+    0x516d1200, 0xe0530490, 0xe0a30b60, 0x04900760, 0xf001744d, 0x0490e422, 0x9022f04d, 0xffe05004, 
+    0x8ffde0a3, 0x90138d12, 0xb4e04904, 0x347f0401, 0x00905d80, 0x13c3e050, 0x7e13e0a3, 0xff1f5400, 
+    0xee1094d3, 0x45400094, 0xe07f0490, 0x0f54c4fd, 0xd309e020, 0xee1694ef, 0x31400094, 0x01b412e5, 
+    0x8804900b, 0x5413c4e0, 0x12e03007, 0x026412e5, 0x04901b70, 0x13c4e088, 0x20035413, 0x13e50fe0, 
+    0x347f0470, 0x367f0280, 0x80807412, 0x12387f05, 0x148e8074, 0x7412158f, 0x1060efb8, 0x04b412e5, 
+    0x05127503, 0x05b412e5, 0x04127503, 0xfe2412e5, 0x70146260, 0x831a0203, 0x02037014, 0x70149f1a, 
+    0xbc1a0203, 0x03600424, 0xe5d71a02, 0x703b7f13, 0xb374121c, 0xff3f54ef, 0x06c0007e, 0x3b7f07c0, 
+    0xefae7412, 0x13133f54, 0x801f5413, 0xb3741215, 0xff3f54ef, 0x06c0007e, 0x3b7f07c0, 0xefae7412, 
+    0xd0fd0754, 0xd0ff2de0, 0xe4168fe0, 0x177518f5, 0xda1a0246, 0x5b7013e5, 0x74123c7f, 0x7f54efb3, 
+    0x541313c4, 0x603c7f03, 0xb3741227, 0xff1f54ef, 0x06c0007e, 0x3c7f07c0, 0xefae7412, 0x13133f54, 
+    0xfd1f5413, 0xff2de0d0, 0xe4c3e0d0, 0x7180ff9f, 0xefb37412, 0x7eff1f54, 0xc006c000, 0x123c7f07, 
+    0x54efae74, 0x1313133f, 0xd0fd1f54, 0xd0ff2de0, 0x7f4e80e0, 0xb374123c, 0xc43f54ef, 0x7f075413, 
+    0x1222603c, 0x54efb374, 0x007eff1f, 0x07c006c0, 0x74123c7f, 0x0754efae, 0x2de0d0fd, 0xc3e0d0ff, 
+    0x80ff9fe4, 0xb374121c, 0xff1f54ef, 0x06c0007e, 0x3c7f07c0, 0xefae7412, 0xd0fd0754, 0xd0ff2de0, 
+    0x75168fe0, 0x1775da18, 0x7f578026, 0xb374123d, 0xff3f54ef, 0x207d007e, 0x7312007c, 0x75168fb4, 
+    0x1775e118, 0x7f3b801f, 0x8074123d, 0xfe0754ee, 0x047c007d, 0xefb47312, 0xa2ce0678, 0x13ce13e7, 
+    0x1080f8d8, 0x74123d7f, 0x0b78ef80, 0x13e7a2ce, 0xf8d813ce, 0x75168fff, 0x1775f118, 0xe403800f, 
+    0x049016f5, 0xf016e54f, 0xfffe0470, 0xe5c31380, 0x94806416, 0x7e064080, 0x80017f00, 0x7fff7e04, 
+    0x15e5c3ff, 0xe515f59f, 0x14f59e14, 0xe04b0490, 0x400094d3, 0x4e04902b, 0x0490fbe0, 0x20f5e01e, 
+    0x21f5e0a3, 0x85221885, 0x24752317, 0xac15adff, 0x1216af14, 0x168fba51, 0xe0620490, 0xf04d0490, 
+    0x01b412e5, 0xb516e51f, 0xe5c31518, 0xe5ff9415, 0x94806414, 0x9008507f, 0x01747c04, 0xe40580f0, 
+    0xf07c0490, 0xe04c0490, 0x08600164, 0xe04a0490, 0x31700364, 0x01b412e5, 0x6516e506, 0xe5136017, 
+    0x0194d312, 0x16e51f40, 0x06601765, 0x186516e5, 0xa4751370, 0xfea67501, 0x75ffa775, 0x017d199a, 
+    0x31121c7f, 0x490490b9, 0x0901b4e0, 0x12af16ad, 0x80a52b12, 0x4f04900f, 0xab1cf5e0, 0xaf13ad16, 
+    0xd51b1212, 0xe51e0490, 0xe5a3f014, 0x0490f015, 0x0490e04f, 0x0490f04e, 0xf004e04b, 0x8d198f22, 
+    0xc31b8b1a, 0x1c951be5, 0x19e51df5, 0x0370fe24, 0x04f81c02, 0x1e020360, 0x123b7fc9, 0x54efae74, 
+    0x1313133f, 0x20f51f54, 0x74123b7f, 0x0754efae, 0x3b7f21f5, 0xefb37412, 0x22f53f54, 0xe53f2375, 
+    0x6960141a, 0x02036004, 0x2778aa1c, 0x007d007c, 0x007a007b, 0x007e1e79, 0x2512067f, 0xaf017d5b, 
+    0x5069121d, 0x1e7803c0, 0xd01d007c, 0x7f007e03, 0x5b251206, 0xe0500090, 0xe0a313c3, 0x54007e13, 
+    0x94d3ff1f, 0x0094ee10, 0x04901e40, 0x54c4e07f, 0x09e0200f, 0x1694efd3, 0x400094ee, 0x8804900b, 
+    0x5413c4e0, 0x2ae03007, 0x80212085, 0x7c277825, 0x7b007d00, 0x79007a00, 0x7f007e1e, 0x5b251206, 
+    0x1daffde4, 0x78506912, 0x7e007c1e, 0x12067f00, 0x21af5b25, 0xf5ed07ad, 0xf50474a4, 0xc0a775a5, 
+    0x752b9a75, 0xa67580a5, 0x7fa775ff, 0xaf2b9a75, 0xed07ad20, 0x0674a4f5, 0xa775a5f5, 0x2b9a75c0, 
+    0x7580a575, 0xa775ffa6, 0x2b9a757f, 0x07ad22af, 0x74a4f5ed, 0x75a5f502, 0x9a75c0a7, 0xbc1e022b, 
+    0x74123c7f, 0x7f54efb3, 0x541313c4, 0x7f1ef503, 0xb374123c, 0xc43f54ef, 0xf5075413, 0x123c7f1f, 
+    0x54efae74, 0x1313133f, 0x20f51f54, 0x74123c7f, 0x0754efae, 0x3c7f21f5, 0xefb37412, 0x22f51f54, 
+    0xe51f2375, 0x0370141a, 0x04e11d02, 0x1e020360, 0x2520e537, 0x33e4ff22, 0xe508704f, 0x03ffb41d, 
+    0xaf011e75, 0x7c007e1e, 0x12fe7dff, 0x04eff025, 0xa4f01d85, 0x277824f5, 0x007d007c, 0x007a007b, 
+    0x007e1e79, 0x2512067f, 0xaf017d5b, 0x50691224, 0x1e7803c0, 0xd01d007c, 0x7f007e03, 0x5b251206, 
+    0x222520e5, 0x4f33e4ff, 0x1ef50270, 0xe0500090, 0xe0a313c3, 0x54007e13, 0x94d3ff1f, 0x0094ee10, 
+    0x04901f40, 0x54c4e07f, 0x09e0200f, 0x1694efd3, 0x400094ee, 0x8804900c, 0x1313c4e0, 0xe0300354, 
+    0x2120855e, 0x801f1e85, 0x2521e556, 0x33e4ff22, 0xe508704f, 0x03ffb41d, 0xaf011f75, 0x7c007e1f, 
+    0x12fe7dff, 0x04eff025, 0xa4f01d85, 0x277824f5, 0x007d007c, 0x007a007b, 0x007e1e79, 0x2512067f, 
+    0xaffde45b, 0x50691224, 0x007c1e78, 0x067f007e, 0xe55b2512, 0xff222521, 0x704f33e4, 0xaf1ff502, 
+    0xed07ad21, 0x0a74a4f5, 0xa775a5f5, 0x2b9a75c0, 0x7580a575, 0xa775ffa6, 0x2b9a757f, 0x07ad20af, 
+    0x74a4f5ed, 0x75a5f50c, 0x9a75c0a7, 0x80a5752b, 0x75ffa675, 0x9a757fa7, 0xad22af2b, 0xa4f5ed07, 
+    0xa5f50874, 0x75c0a775, 0xa5752b9a, 0xffa67580, 0x757fa775, 0x1eaf2b9a, 0xf5ed07ad, 0xf51474a4, 
+    0xc0a775a5, 0x752b9a75, 0xa67580a5, 0x7fa775ff, 0xaf2b9a75, 0xed07ad1f, 0x1674a4f5, 0xa775a5f5, 
+    0x2b9a75c0, 0x7580a575, 0xa775ffa6, 0x2b9a757f, 0xaf1bad22, 0xa52b1219, 0x75128f22, 0x0490031a, 
+    0x0960e049, 0x744d0490, 0x027ff001, 0x15f5e422, 0x14f513f5, 0x18f517f5, 0x16f519f5, 0x7412387f, 
+    0x1c049080, 0xefa3f0ee, 0x12397ff0, 0x54ee8074, 0x1e049003, 0xf0efa3f0, 0x900a7412, 0xf0ef5104, 
+    0x02b412e5, 0x6f049005, 0x12e51b80, 0x900503b4, 0x11807004, 0x01b412e5, 0x71049005, 0x12e50780, 
+    0x04900670, 0x16f5e072, 0x0490fde4, 0x0270e01c, 0x2570e0a3, 0xe01e0490, 0xffe0a3fe, 0xee0094d3, 
+    0x80948064, 0xa2ee3a40, 0xeffe13e7, 0x0490ff13, 0xa3f0ee1e, 0x800df0ef, 0x900a7ddb, 0xfee01c04, 
+    0xd3ffe0a3, 0x64ee0094, 0x40809480, 0xe7a2ee13, 0x13effe13, 0x1c0490ff, 0xefa3f0ee, 0xdb800df0, 
+    0xf5fc24ed, 0x9533ff15, 0x78effee0, 0xce33c307, 0xf9d8ce33, 0xa2ce0378, 0x13ce13e7, 0xacfdf8d8, 
+    0x22049006, 0xe0a3fee0, 0xc3ce0378, 0xd813ce13, 0xf59dc3f9, 0xf59cee14, 0xb412e513, 0xe5d30f02, 
+    0xe5009414, 0x94806413, 0x8002409f, 0xb412e539, 0xe5d30f03, 0xe5009414, 0x94806413, 0x8002409f, 
+    0xb412e525, 0xe5d30f01, 0xe5009414, 0x94806413, 0x8002409f, 0x7012e511, 0x14e5d313, 0x13e50094, 
+    0x9f948064, 0x13750640, 0x0014751f, 0x13ae14e5, 0x33c30378, 0xd8ce33ce, 0x230490f9, 0x0490eef0, 
+    0x16e5f022, 0xa408f075, 0x1425f0ae, 0x35ee14f5, 0xe513f513, 0x0f02b412, 0x9414e5d3, 0x6413e500, 
+    0x409f9480, 0xe5398002, 0x0f03b412, 0x9414e5d3, 0x6413e500, 0x409f9480, 0xe5258002, 0x0f01b412, 
+    0x9414e5d3, 0x6413e500, 0x409f9480, 0xe5118002, 0xd3137012, 0x009414e5, 0x806413e5, 0x06409f94, 
+    0x751f1375, 0x13ae0014, 0x037814e5, 0x33ce33c3, 0xf5f9d8ce, 0xe5178e18, 0xfe075417, 0x037818e5, 
+    0xce13c3ce, 0xf5f9d813, 0x6012e516, 0x0b03b403, 0x131317e5, 0xf51f5413, 0xe50d8019, 0x13131317, 
+    0xf0751f54, 0x19f5a4ff, 0x036012e5, 0xd32601b4, 0x806419e5, 0x05409f94, 0x80510490, 0x19e5c32f, 
+    0x61948064, 0x04900550, 0xe5328051, 0x903b6019, 0x80f05104, 0x6412e535, 0xe5056002, 0x2a03b412, 
+    0x6419e5d3, 0x409f9480, 0x50049008, 0x80f01f74, 0x19e5c319, 0x61948064, 0x04900850, 0xf0e17450, 
+    0x19e50880, 0x04900460, 0x0490f050, 0xf001744d, 0x167012e5, 0xe0220490, 0xf00f0490, 0xa3220490, 
+    0x750490e0, 0x720490f0, 0x12e54780, 0x901601b4, 0x90e02204, 0x90f01004, 0xe0a32204, 0xf0760490, 
+    0x80710490, 0x9012e52c, 0x02b42204, 0x0490e013, 0x0490f00d, 0x90e0a322, 0x90f07304, 0x11806f04, 
+    0x0e0490e0, 0x220490f0, 0x0490e0a3, 0x0490f074, 0xf016e570, 0x7f22007f, 0xb374128b, 0x900f54ef, 
+    0x12f04904, 0x0490a672, 0xa3fee000, 0xce0278e0, 0x13ce13c3, 0xe030f9d8, 0x90198002, 0x70e04904, 
+    0x50009018, 0xa313c3e0, 0x1f5413e0, 0xe40694c3, 0x05400094, 0x80a4f5e4, 0x04a47503, 0x75fba675, 
+    0x9a75ffa7, 0x00049040, 0xe0a3fee0, 0xc3ce0278, 0xd813ce13, 0x1ee020f9, 0xe0490490, 0x00901870, 
+    0x13c3e050, 0x5413e0a3, 0x0e94d31f, 0x400094e4, 0x80a47505, 0xf5e40380, 0x7fa675a4, 0x75ffa775, 
+    0x0490409a, 0xa3fce000, 0xc4ecfde0, 0xc8f054f8, 0x0f54c4ed, 0x64035448, 0xed0c7002, 0x027804ae, 
+    0xce13c3ce, 0x90f9d813, 0xfee00004, 0x0278e0a3, 0xce13c3ce, 0x20f9d813, 0x230203e0, 0x01a57514, 
+    0x75ffa675, 0x9a75fea7, 0x49049040, 0x020360e0, 0x00903823, 0x13c3e050, 0x7e13e0a3, 0xff1f5400, 
+    0xee0a94c3, 0x03500094, 0xef382302, 0x94ee0e94, 0x75115000, 0xa67501a4, 0xffa775fc, 0x75909a75, 
+    0x738002a5, 0x1294efc3, 0x500094ee, 0x02a47511, 0x75fca675, 0x9a75ffa7, 0x04a57590, 0xa4755980, 
+    0xfca67503, 0x75ffa775, 0xa575909a, 0xffa67506, 0x75f9a775, 0x0090929a, 0x13c3e050, 0x5413e0a3, 
+    0x1594d31f, 0x400094e4, 0x20a57505, 0xf5e40380, 0xffa675a5, 0x75dfa775, 0x2480909a, 0x75a5f5e4, 
+    0xa775ffa6, 0x409a75fe, 0x75a4f5e4, 0xa775fca6, 0x909a75ff, 0x75a5f5e4, 0xa775ffa6, 0x929a75f9, 
+    0xf512f5e4, 0x50009013, 0xa313c3e0, 0x1f5413e0, 0xe40594c3, 0x06500094, 0x75041375, 0x13e50612, 
+    0x13c30254, 0xe025e025, 0xe5ff0454, 0x13045413, 0x333f5413, 0x08543333, 0x13e5ff4f, 0xe0250154, 
+    0xf54f0254, 0xf1a675a4, 0x75ffa775, 0x12e5919a, 0x13c30254, 0xff1054c4, 0x045412e5, 0x3f541313, 
+    0x205433c4, 0x12e5ff4f, 0x33330154, 0x4f085433, 0xa675a4f5, 0xffa775c7, 0xe5929a75, 0xc3025413, 
+    0x1054c413, 0x5413e5ff, 0x54131304, 0x5433c43f, 0xe5ff4f20, 0xfe015413, 0x54333333, 0xa4f54f08, 
+    0x75c7a675, 0x9a75ffa7, 0x49049093, 0x700164e0, 0x01a47505, 0xf5e40380, 0xfea675a4, 0x75ffa775, 
+    0x0490a89a, 0x0464e049, 0xa4750570, 0xe4038001, 0xa675a4f5, 0xffa775fe, 0x7da09a75, 0x12ffe496, 
+    0x54efa774, 0x13c3ff03, 0xf0890490, 0xa5750560, 0x7503801b, 0xa67511a5, 0xe0a775ff, 0x75c09a75, 
+    0xa67501a4, 0xffa775fe, 0x90019a75, 0x24e04904, 0x0008b4fe, 0x24903050, 0x03f0755c, 0x2583c5a4, 
+    0x7383c5f0, 0x02742402, 0x24027424, 0x79240274, 0x02792402, 0x24027424, 0x79240274, 0x8001a575, 
+    0x02a57508, 0xf5e40380, 0xffa675a5, 0x75fca775, 0xe722039a, 0xdf08f609, 0xe74680fa, 0xdf08f209, 
+    0x883e80fa, 0xe7838c82, 0xdfa3f009, 0xe33280fa, 0xdf08f609, 0xe37880fa, 0xdf08f209, 0x887080fa, 
+    0xe3838c82, 0xdfa3f009, 0x896480fa, 0xe0838a82, 0xdf08f6a3, 0x895880fa, 0xe0838a82, 0xdf08f2a3, 
+    0x804c80fa, 0x80fa80d2, 0x80d480c6, 0x80f28069, 0x80108033, 0x80ea80a6, 0x80a8809a, 0x80e280da, 
+    0x893380ca, 0xec838a82, 0xa393e4fa, 0xc882c5c8, 0xcc83c5cc, 0xc5c8a3f0, 0xc5ccc882, 0xe9dfcc83, 
+    0x0d80e7de, 0x838a8289, 0xf6a393e4, 0xecf9df08, 0xedf0a9fa, 0x828922fb, 0xfaec838a, 0xc5c8a3e0, 
+    0xc5ccc882, 0xa3f0cc83, 0xc882c5c8, 0xcc83c5cc, 0xe8deeadf, 0x8289db80, 0x93e4838a, 0xdf08f2a3, 
+    0x88cc80f9, 0x0160eff0, 0xc3604e0e, 0x24edf088, 0x0004b402, 0x82f5b950, 0xb40224eb, 0xaf500004, 
+    0x82452323, 0xdb249023, 0x30d5c273, 0xd5b207f7, 0x05fff063, 0x0ce730f0, 0x04f4d5b2, 0xfff06384, 
+    0x0180f005, 0x02d53084, 0xbb2204f4, 0x82890601, 0x22e0838a, 0x22e70250, 0xe302febb, 0x8a828922, 
+    0x2293e483, 0x890901bb, 0xf8838a82, 0x22f028e0, 0xf7270350, 0x05febb22, 0xf328e3f8, 0x89838a22, 
+    0x93e4f882, 0x01bb2228, 0x8a828906, 0x5022f083, 0xbb22f702, 0x22f301fe, 0xa4f08def, 0x8ccff0a8, 
+    0xce28a4f0, 0x2ea4f08d, 0x9feb22fe, 0x9eeaf0f5, 0x9de9f042, 0x64ecf042, 0x8064c880, 0x22f04598, 
+    0xf0f59feb, 0xf0429eea, 0xf0429de9, 0xf0459ce8, 0x0f60e822, 0xfc13c3ec, 0xeefd13ed, 0x13effe13, 
+    0x22f1d8ff, 0xef0f60e8, 0xeeff33c3, 0x33edfe33, 0xfc33ecfd, 0xbb22f1d8, 0x82890701, 0x2602838a, 
+    0xe90550c1, 0xb52602f8, 0xe905febb, 0xcd2602f8, 0x838a8289, 0xbbd92602, 0x82890701, 0x2602838a, 
+    0xe90550f5, 0xe92602f8, 0xe905febb, 0x012702f8, 0x604eef22, 0x0160ef12, 0x01bbed0e, 0x8a82890b, 
+    0xdfa3f083, 0x22fadefc, 0x0750f089, 0xfcdf09f7, 0xbb22f0a9, 0x09f3fcfe, 0xf0a9fcdf, 0x08fce622, 
+    0xe608fde6, 0xffe608fe, 0xa3fce022, 0xe0a3fde0, 0xffe0a3fe, 0x08fce222, 0xe208fde2, 0xffe208fe, 
+    0xfc93e422, 0xfd930174, 0xfe930274, 0xff930374, 0x08f6ec22, 0xee08f6ed, 0xf6ef08f6, 0xa3f0ec22, 
+    0xeea3f0ed, 0xf0efa3f0, 0x08f2ec22, 0xee08f2ed, 0xf2ef08f2, 0x75128f22, 0x12e5031e, 0x14750770, 
+    0x8013f51f, 0xb412e51a, 0x0d800201, 0x03b412e5, 0x1f147508, 0x8013f5e4, 0x14f5e406, 0x90e11375, 
+    0xfee01c04, 0xeeffe0a3, 0xfde09533, 0x120a78fc, 0x04a83c26, 0x06aa05a9, 0xe0a307ab, 0xffe0a3fe, 
+    0xe09533ee, 0x4febfcfd, 0xfe4eeaff, 0xe8fd4de9, 0x24effc4c, 0xee18f5f1, 0x17f5ff34, 0xf5ff34ed, 
+    0xff34ec16, 0x387f15f5, 0x90807412, 0xf0ee1c04, 0x7ff0efa3, 0x80741239, 0x900354ee, 0xa3f01e04, 
+    0x0490f0ef, 0xa3fee01c, 0x33eeffe0, 0xfcfde095, 0x26120a78, 0xa904a83c, 0xab06aa05, 0xfee0a307, 
+    0xeeffe0a3, 0xfde09533, 0xff4febfc, 0xe9fe4eea, 0x4ce8fd4d, 0xf124effc, 0x34ee1cf5, 0xed1bf5ff, 
+    0x1af5ff34, 0xf5ff34ec, 0x4f049019, 0x64d3ffe0, 0x40809480, 0x90078002, 0xf4e04f04, 0xefd3ff04, 
+    0x81948064, 0x04900840, 0xe7a2e04f, 0x0490f013, 0xf004e053, 0xe0530490, 0x500594d3, 0x231c8538, 
+    0x85221b85, 0x1985211a, 0x51049020, 0x8524f5e0, 0x17852818, 0x26168527, 0x85251585, 0x14852913, 
+    0x4f04902a, 0xe42bf5e0, 0xe0a32cf5, 0x195812ff, 0x80e41d8f, 0x53049042, 0x0794d3e0, 0x1c853f50, 
+    0x221b8523, 0x85211a85, 0x04902019, 0x24f5e051, 0x85281885, 0x16852717, 0x25158526, 0x85291385, 
+    0x04902a14, 0x2bf5e04f, 0xa3012c75, 0x5812ffe0, 0x901d8f19, 0x90e06204, 0x80f04d04, 0x5004900c, 
+    0x901df5e0, 0x01744d04, 0x500490f0, 0x90f0a3e0, 0x1de55004, 0x6012e5f0, 0x0a01b403, 0xe0500490, 
+    0x546f12ff, 0x04900880, 0x12ffe050, 0x0490d25a, 0x0164e04d, 0x29020360, 0x7012e561, 0x50049021, 
+    0x64d3ffe0, 0x40809480, 0x90078002, 0xf4e05004, 0x33efff04, 0xf8543333, 0xf00f0490, 0x12e56b80, 
+    0x902101b4, 0xffe05004, 0x948064d3, 0x80024080, 0x50049007, 0xff04f4e0, 0x333333ef, 0x0490f854, 
+    0x4580f010, 0x02b412e5, 0x50049021, 0x64d3ffe0, 0x40809480, 0x90078002, 0xf4e05004, 0x33efff04, 
+    0xf8543333, 0xf00d0490, 0x04901f80, 0xd3ffe050, 0x80948064, 0x07800240, 0xe0500490, 0xefff04f4, 
+    0x54333333, 0x0e0490f8, 0x22007ff0, 0x75001275, 0x04902013, 0xdd24e040, 0x2a020370, 0x03701408, 
+    0x802e2a02, 0x49049000, 0x901370e0, 0xfee00004, 0x0278e0a3, 0xce13c3ce, 0x20f9d813, 0x007f03e0, 
+    0x0490e422, 0xf0a3f020, 0xe07b0490, 0x05600164, 0x4b0490e4, 0x7c0490f0, 0x904560e0, 0xffe04504, 
+    0xfee09533, 0x1395efc3, 0x1295eeff, 0x94efd3fe, 0x8064ee00, 0x03408094, 0x90f014e0, 0xffe04504, 
+    0xfee09533, 0x1395efc3, 0xc31295ee, 0x80948064, 0x04e00350, 0x200490f0, 0x04a3f0e4, 0x692b02f0, 
+    0xe0030490, 0x12fff824, 0x0490d25a, 0xf0237440, 0xbf205c12, 0x027f0302, 0x53049022, 0x0490ffe0, 
+    0xa3f0e424, 0x0490f0ef, 0x0824e003, 0xd25a12ff, 0x74400490, 0x5c12f024, 0x0302bf20, 0x9022027f, 
+    0xffe05304, 0xe0240490, 0xfde0a3fc, 0xfe9defc3, 0x04909ce4, 0xcea3f024, 0x240490f0, 0xe0a3fee0, 
+    0x903d604e, 0xd3e04b04, 0x03500094, 0xee232b02, 0x80948064, 0x007e0640, 0x0480017f, 0xff7fff7e, 
+    0xe0520490, 0x948064c3, 0x7c064080, 0x80017d00, 0x7dff7c04, 0x706defff, 0x706cee02, 0x232b0203, 
+    0xe4200490, 0xf004a3f0, 0xe0240490, 0xffe0a3fe, 0xee0094d3, 0x80948064, 0x0f800240, 0xe0240490, 
+    0xffe0a3fe, 0xff9fe4c3, 0x90fe9ee4, 0xfde05204, 0x948064d3, 0x80024080, 0x52049007, 0xfd04f4e0, 
+    0xe09533ed, 0x9defd3fc, 0xf88064ec, 0x988064ee, 0x04907640, 0x0164e07a, 0x04902660, 0x33ffe045, 
+    0x90fee095, 0xc3e05204, 0x80948064, 0x007c0640, 0x0480017d, 0xff7dff7c, 0xecff2fed, 0x4380fe3e, 
+    0xe0450490, 0xe09533ff, 0x903880fe, 0x64e07a04, 0xc3276001, 0xe0240490, 0x80948064, 0x007e0640, 
+    0x0480017f, 0xff7fff7e, 0xe0450490, 0xe09533fd, 0x9fedc3fc, 0xfe9eecff, 0x04900980, 0x33ffe045, 
+    0x90fee095, 0xf0ef4504, 0xa3240490, 0x520490e0, 0x450490f0, 0x5e12ffe0, 0x4b04909f, 0x90f004e0, 
+    0x70e02004, 0x64e0a304, 0x90116001, 0xc3e04b04, 0x08501094, 0x747b0490, 0x0580f001, 0x7b0490e4, 
+    0x0490e4f0, 0x12fff040, 0x007fd25a, 0xfe24ef22, 0x2c020370, 0x0370144c, 0x146f2d02, 0x2d020370, 
+    0x03701487, 0x249f2d02, 0x02036004, 0xedd3c22d, 0xc6948064, 0x467d0240, 0x8064edd3, 0x0640bf94, 
+    0xffc124ed, 0x007f0280, 0xffec07ac, 0xfee09533, 0xeea4f5ef, 0x04440154, 0xa775a5f5, 0x2b9a75c0, 
+    0x7580a575, 0xa775ffa6, 0x2b9a757f, 0x9533ffec, 0xf5effee0, 0x0154eea4, 0xa5f50644, 0x75c0a775, 
+    0xa5752b9a, 0xffa67580, 0x757fa775, 0xffec2b9a, 0xfee09533, 0x9533fbed, 0xebc3fae0, 0x9eeaff9f, 
+    0xa4f5effe, 0x440154ee, 0x75a5f502, 0x9a75c0a7, 0xb52d022b, 0x8064edd3, 0x04408094, 0x048005af, 
+    0xff04f4ed, 0x8064efd3, 0x16409f94, 0x8064edd3, 0x04408094, 0x048005af, 0xff04f4ed, 0xffe124ef, 
+    0x007f0280, 0xffec07ac, 0xfee09533, 0xeea4f5ef, 0x0a440154, 0xa775a5f5, 0x2b9a75c0, 0x7580a575, 
+    0xa775ffa6, 0x2b9a757f, 0x9533ffec, 0xf5effee0, 0x0154eea4, 0xa5f50c44, 0x75c0a775, 0xa5752b9a, 
+    0xffa67580, 0x757fa775, 0xedd32b9a, 0x80948064, 0x05af0440, 0xf4ed0480, 0x33efff04, 0xfbece095, 
+    0xfae09533, 0xff9befc3, 0xd3a4f5ef, 0x948064ed, 0xaf044080, 0xed048005, 0xefff04f4, 0xfee09533, 
+    0xee9befc3, 0x4401549a, 0x75a5f508, 0x9a75c0a7, 0x80a5752b, 0x75ffa675, 0x9a757fa7, 0x64edc32b, 
+    0x50809480, 0x80017f04, 0xef007f02, 0xedc3a4f5, 0x80948064, 0x54ee007e, 0xf5144401, 0xc0a775a5, 
+    0x752b9a75, 0xa67580a5, 0x7fa775ff, 0xc32b9a75, 0x948064ed, 0x7f045080, 0x7f028001, 0xa4f5ef00, 
+    0x8064edc3, 0x007e8094, 0x440154ee, 0x75a5f516, 0x9a75c0a7, 0xed46802b, 0xe09533ff, 0xa4f5effe, 
+    0x440154ee, 0x75a5f50e, 0x9a75c0a7, 0xed2e802b, 0xe09533ff, 0xa4f5effe, 0x440154ee, 0x75a5f510, 
+    0x9a75c0a7, 0xed16802b, 0xe09533ff, 0xa4f5effe, 0x440154ee, 0x75a5f512, 0x9a75c0a7, 0x80a5752b, 
+    0x75ffa675, 0x9a757fa7, 0x9022222b, 0x70e06e04, 0x8604901e, 0x7d1860e0, 0x12ffe499, 0x30ee5b74, 
+    0x04900de7, 0xf001746e, 0x107f027d, 0x90b93112, 0x24e04104, 0x0007b4db, 0x2e902350, 0x03f07500, 
+    0x2583c5a4, 0x7383c5f0, 0x02382e02, 0x2f02032f, 0x1d2f0253, 0x026a2f02, 0x2f02902f, 0x02a475b3, 
+    0x75fda675, 0x9a75ffa7, 0x7f027d51, 0xb9311208, 0x90dd6212, 0xf0ee2004, 0xe4f0efa3, 0xf04e0490, 
+    0x7412657f, 0x0154efb3, 0x6f7012f5, 0xc3dd6212, 0xe0210490, 0x0490ff9f, 0xfe9ee020, 0x6494efc3, 
+    0x400094ee, 0x4e04904f, 0x900770e0, 0x20e00004, 0x027d15e0, 0x31120f7f, 0x01a475b9, 0x75fea675, 
+    0x9a75ffa7, 0x7f2d8019, 0xb37412d3, 0x640154ef, 0x75a4f501, 0xa775fea6, 0xd39a75ff, 0x90dd6212, 
+    0xf0ee2004, 0x90f0efa3, 0x01744e04, 0x7f027df0, 0xb931121d, 0x74410490, 0x9022f025, 0x01748604, 
+    0xe4997df0, 0x5b7412ff, 0x148f138e, 0x12037def, 0x3112ba3d, 0xa4f5e4b5, 0x9a75a5f5, 0xa4f5e460, 
+    0x7580a575, 0xf5e4609a, 0x75a5f5a4, 0x0490609a, 0xf0267441, 0xf513f5e4, 0xae14af14, 0xd1551213, 
+    0x600164ef, 0x41049039, 0x7ff02674, 0xb3741265, 0xf50154ef, 0x02037012, 0x0490bf2f, 0xf0147440, 
+    0xf02874a3, 0x12507f22, 0x138e8074, 0x7def148f, 0xba3d1203, 0x90b53112, 0xb4e06904, 0x0490bb01, 
+    0xf0277441, 0xf513f5e4, 0xae14af14, 0xeb611213, 0x600164ef, 0x41049036, 0x7ff02774, 0xb3741265, 
+    0xf50154ef, 0x90606012, 0x14744004, 0x2974a3f0, 0x507f22f0, 0x8e807412, 0xef148f13, 0x3d12037d, 
+    0xb53112ba, 0xe06a0490, 0x90be01b4, 0x44e03d04, 0x0490f004, 0xf02a7441, 0xe03c0490, 0xe02013c3, 
+    0xa4752201, 0xfea67501, 0x75ffa775, 0x027d619a, 0x31120c7f, 0x410490b9, 0x90f02b74, 0x60e06e04, 
+    0x41049006, 0x22f02c74, 0xf5a4f5e4, 0x7fa675a5, 0x75f8a775, 0xa475019a, 0x06a57590, 0x7501a675, 
+    0xf5e4029a, 0xfea675a4, 0x75ffa775, 0xf5e4039a, 0x75a5f5a4, 0xa77580a6, 0x049a7581, 0xf5a4f5e4, 
+    0x3fa675a5, 0x75bfa775, 0xf5e4109a, 0xcfa675a4, 0x75ffa775, 0xa575119a, 0xffa67534, 0x7583a775, 
+    0xa475149a, 0xe0a6750d, 0x75ffa775, 0xa475159a, 0xa5f5e401, 0x75f0a675, 0x9a75fca7, 0xa5f5e418, 
+    0x75ffa675, 0x9a753fa7, 0xa4f5e420, 0xa675a5f5, 0x13a775fd, 0xe4219a75, 0xa5f5a4f5, 0x75c0a675, 
+    0x9a75c0a7, 0xa4f5e422, 0xa675a5f5, 0x13a775fd, 0xe4239a75, 0xa5f5a4f5, 0x75c0a675, 0x9a75c0a7, 
+    0xa5f5e424, 0x75ffa675, 0x9a7513a7, 0xa4f5e425, 0xa675a5f5, 0xc0a775c0, 0xe4269a75, 0xa675a5f5, 
+    0x13a775ff, 0xe4279a75, 0xa5f5a4f5, 0x75c0a675, 0x9a75c0a7, 0xa5f5e428, 0x75ffa675, 0x9a7513a7, 
+    0xa4f5e429, 0xa675a5f5, 0xc0a775c0, 0xe42a9a75, 0xa5f5a4f5, 0x7540a775, 0xf5e42b9a, 0x75a5f5a4, 
+    0xa77503a6, 0x309a7501, 0xf5a4f5e4, 0x319a75a5, 0xf5a4f5e4, 0x329a75a5, 0xf5a4f5e4, 0x339a75a5, 
+    0x75a4f5e4, 0xa775f6a6, 0x409a75ff, 0x75a4f5e4, 0xa775f0a6, 0x419a75ff, 0x75a4f5e4, 0xa775f8a6, 
+    0x429a75ff, 0x75a4f5e4, 0xa775c0a6, 0x439a75ff, 0x75a4f5e4, 0xa775c0a6, 0x449a75ff, 0x75a4f5e4, 
+    0xa775c0a6, 0x459a75ff, 0x75a4f5e4, 0xa775c0a6, 0x469a75ff, 0x75a4f5e4, 0xa775c0a6, 0x479a75ff, 
+    0x75a4f5e4, 0xa775c0a6, 0x489a75ff, 0x75a4f5e4, 0xa77580a6, 0x499a75ff, 0x75a4f5e4, 0xa775fda6, 
+    0x519a75ff, 0xf5a4f5e4, 0x609a75a5, 0x75a4f5e4, 0xa775fea6, 0x619a75ff, 0x75a4f5e4, 0xa7757fa6, 
+    0x909a75ff, 0x75a4f5e4, 0xa775fea6, 0x989a75ff, 0x75a5f5e4, 0xa775ffa6, 0xd19a75fb, 0x7f037d22, 
+    0x901a8f09, 0xf5e05a00, 0xf5e0a31b, 0x041d751c, 0x941ce5c3, 0x941be5f8, 0x02034002, 0x1ae59133, 
+    0x03500094, 0xe5913302, 0x4033941a, 0x91330203, 0xe0650090, 0x03700164, 0x90913302, 0xc3e00504, 
+    0x0203509d, 0x00909133, 0xffb4e05d, 0x241ce515, 0x35e4ff08, 0xefd3fe1b, 0x94eef894, 0x02034002, 
+    0x33e59133, 0x32020360, 0xcb7212e3, 0x358f348e, 0xe0600090, 0x5411e030, 0x0090f0fe, 0xf004e067, 
+    0x00900670, 0xf004e066, 0x670090d3, 0x900094e0, 0x94e06600, 0x02035000, 0x0274e332, 0x82f51c25, 
+    0x1b350174, 0xff7483f5, 0x660090f0, 0xe0a3fce0, 0x74ffecfd, 0xf51c2501, 0x35017482, 0xef83f51b, 
+    0x250074f0, 0x7482f51c, 0xf51b3501, 0x74f0ed83, 0xf51c2503, 0x1b35e41c, 0xe5c31bf5, 0xe5f8941c, 
+    0x4002941b, 0x1ef5e43f, 0x08241ce5, 0x341be5ff, 0xe5c3fefd, 0x9ee49f1e, 0xf8741e50, 0x82f51e25, 
+    0xf50334e4, 0x74ffe083, 0xf51e2500, 0x0134e482, 0xf0ef83f5, 0xd0801e05, 0x1c250874, 0xfd741cf5, 
+    0x1bf51b35, 0x660090e4, 0xe5f0a3f0, 0xc433251d, 0x45e05433, 0x0374ff38, 0x82f51c25, 0x1b350174, 
+    0xf0ef83f5, 0x74ff34e5, 0xf51c2502, 0x35017482, 0xef83f51b, 0x250174f0, 0x7482f51c, 0xf51b3501, 
+    0xf035e583, 0x1c250074, 0x017482f5, 0x83f51b35, 0x74f01ae5, 0xf51c2504, 0x1b35e41c, 0xe5c31bf5, 
+    0xe5f8941c, 0x4002941b, 0x1ef5e43f, 0x08241ce5, 0x341be5ff, 0xe5c3fefd, 0x9ee49f1e, 0xf8741e50, 
+    0x82f51e25, 0xf50334e4, 0x74ffe083, 0xf51e2500, 0x0134e482, 0xf0ef83f5, 0xd0801e05, 0x1c250874, 
+    0xfd741cf5, 0x1bf51b35, 0xf534f5e4, 0x9033f535, 0x1be55a00, 0x1ce5a3f0, 0x3b7f22f0, 0xefae7412, 
+    0x7eff0754, 0xc006c000, 0x123b7f07, 0x54efae74, 0x1313133f, 0xd0fd1f54, 0xd0ff2de0, 0xc30034e0, 
+    0x13effe13, 0xc006c0ff, 0x123b7f07, 0x54efb374, 0xe0d0fd3f, 0xd014f52d, 0xf50034e0, 0x123c7f13, 
+    0x54efb374, 0x007eff1f, 0x07c006c0, 0x74123c7f, 0x3f54efae, 0x54131313, 0xe0d0fd1f, 0xd01ef52d, 
+    0xf50034e0, 0x123c7f1d, 0x54efb374, 0x1313c47f, 0x01640354, 0x95c30a70, 0x95e4ff1e, 0x0480fe1d, 
+    0x1eaf1dae, 0x188f178e, 0x74123c7f, 0x1f54efb3, 0xc0007eff, 0x7f07c006, 0xae74123c, 0xfd0754ef, 
+    0xf52de0d0, 0x34e0d020, 0x7f1ff500, 0xb374123c, 0xc43f54ef, 0x64075413, 0xc30a7001, 0xe4ff2095, 
+    0x80fe1f95, 0xaf1fae04, 0x2f18e520, 0x3e17e5ff, 0xf513e7a2, 0xf513ef15, 0x123d7f16, 0x54efb374, 
+    0x007eff3f, 0x007c207d, 0xefb47312, 0xf5e09533, 0x7f1a8f19, 0x8074123d, 0xfe0754ee, 0x047c007d, 
+    0xefb47312, 0xa2ce0678, 0x13ce13e7, 0x33fff8d8, 0x1bf5e095, 0x3d7f1c8f, 0xef807412, 0xa2ce0b78, 
+    0x13ce13e7, 0x33fff8d8, 0xd3fee095, 0x009416e5, 0x806415e5, 0x06408094, 0x16ad15ac, 0xe4c30980, 
+    0xe4fd1695, 0xd3fc1595, 0x009414e5, 0x806413e5, 0x06408094, 0x14ab13aa, 0xe4c30980, 0xe4fb1495, 
+    0xebfa1395, 0x3ceafd2d, 0x1ae5d3fc, 0x19e50094, 0x80948064, 0x19aa0640, 0x09801aab, 0x1a95e4c3, 
+    0x1995e4fb, 0xfd2bedfa, 0xd3fc3aec, 0x00941ce5, 0x80641be5, 0x06408094, 0x1cab1baa, 0xe4c30980, 
+    0xe4fb1c95, 0xedfa1b95, 0x3aecfd2b, 0x94efd3fc, 0x8064ee00, 0x02408094, 0xe4c30780, 0x9ee4ff9f, 
+    0xff2fedfe, 0x22fe3eec, 0x8fba6712, 0x74741212, 0x020370ef, 0x04902337, 0x94c3e015, 0x0094e4fb, 
+    0x37020340, 0x24049023, 0xa30470e0, 0x706364e0, 0x23370203, 0xe0490490, 0x387f3070, 0xee807412, 
+    0xfde09533, 0x120a78fc, 0x04c03c26, 0x06c005c0, 0x397f07c0, 0xee807412, 0xd0fe0354, 0xd002d003, 
+    0xeb00d001, 0x4eeaff4f, 0x04907180, 0xa3fee024, 0x94c3ffe0, 0x8064eef0, 0x36407f94, 0x0f94efd3, 
+    0x948064ee, 0x7f2b5080, 0x80741234, 0xe09533ee, 0x0a78fcfd, 0xc03c2612, 0xc005c004, 0x7f07c006, 
+    0xb3741235, 0x02d003d0, 0x00d001d0, 0xeaff4feb, 0x367f2980, 0xee807412, 0xfde09533, 0x120a78fc, 
+    0x04c03c26, 0x06c005c0, 0x377f07c0, 0xd0b37412, 0xd002d003, 0xeb00d001, 0xfeeaff4f, 0xfce8fde9, 
+    0x75d15f12, 0x38e502f0, 0xf5c124a4, 0x34f0e582, 0xe483f577, 0x0174fc93, 0x0490fd93, 0x7afbe077, 
+    0xfd2bed00, 0x74fc3cea, 0x82f52d00, 0xf53c0174, 0xc3f0ef83, 0xe0250490, 0x04901f94, 0x8064e024, 
+    0x0d508094, 0x12056612, 0x04900e71, 0xf012e577, 0x0a741222, 0x8064efd3, 0x03506194, 0x901a3702, 
+    0x70e04904, 0x12c17f0c, 0x017f5f6a, 0x805f6a12, 0x12047f0e, 0xa5755f6a, 0xffa67502, 0x90329a75, 
+    0xff742404, 0xe174a3f0, 0x0a7412f0, 0x12ff14ef, 0x7112546f, 0x7704900e, 0x75f012e5, 0x38e502f0, 
+    0xf5c124a4, 0x34f0e582, 0xe483f577, 0x0174fe93, 0x0490ff93, 0x7cfde077, 0xff2def00, 0x74fe3eec, 
+    0x82f52f00, 0xf53e0174, 0xe5f0e483, 0xff94c312, 0x007f0440, 0x04900680, 0xff04e077, 0xef770490, 
+    0x049022f0, 0xa3f0e424, 0x22f06374, 0xe0400490, 0x0370f024, 0x80f23702, 0x49049000, 0x020360e0, 
+    0x04906538, 0xe030e087, 0x65380203, 0x90c86c12, 0xfee00004, 0x0278e0a3, 0xce13c3ce, 0x20f9d813, 
+    0x0c7f05e0, 0x90ed6f12, 0xfee00004, 0x0278e0a3, 0xce13c3ce, 0x30f9d813, 0x049064e0, 0x0164e04c, 
+    0x04901e60, 0x0b60e07c, 0x0490ff74, 0xf0a3f028, 0x12103802, 0x04901f42, 0xa3f0ee28, 0x7880f0ef, 
+    0xe0550490, 0x04900670, 0xf0a3f028, 0xe07c0490, 0x04901060, 0xff24e029, 0x280490f0, 0xf0ff34e0, 
+    0x42120f80, 0x2904901f, 0x90f02fe0, 0x3ee02804, 0x550490f0, 0xe0f004e0, 0x70700864, 0x04906680, 
+    0xa3fee000, 0xce0278e0, 0x13ce13c3, 0xe020f9d8, 0x0e71125b, 0x74400490, 0x7412f010, 0x0370ef74, 
+    0x9022027f, 0x64e04c04, 0x7f126001, 0x80741238, 0xee280490, 0xf0efa3f0, 0x80d65012, 0x5504902f, 
+    0x900670e0, 0xa3f02804, 0x12387ff0, 0x04908074, 0xf02fe029, 0xe0280490, 0x0490f03e, 0xf004e055, 
+    0x0808b4e0, 0xe4d65012, 0xf0550490, 0xe0000490, 0x78e0a3fe, 0x13c3ce02, 0xf9d813ce, 0x0203e030, 
+    0x0490dd38, 0x0370e05c, 0x805f3702, 0x49049078, 0x700164e0, 0x8704906a, 0x63e020e0, 0x90c86c12, 
+    0x64e04c04, 0x12106001, 0x0490c25c, 0xa3f0ee28, 0x5012f0ef, 0x902d80d6, 0x70e05504, 0x28049006, 
+    0x12f0a3f0, 0x0490c25c, 0xf02fe029, 0xe0280490, 0x0490f03e, 0xf004e055, 0x0808b4e0, 0xe4d65012, 
+    0xf0550490, 0xe0000490, 0x78e0a3fe, 0x13c3ce02, 0xf9d813ce, 0x900ee020, 0x60e05c04, 0x900680a2, 
+    0x01745c04, 0x400490f0, 0x7ff03374, 0xf5e42200, 0x49049012, 0x1960ffe0, 0x901301b4, 0xfee00004, 
+    0x0278e0a3, 0xce13c3ce, 0x20f9d813, 0x3a0203e0, 0x87049028, 0x1313ffe0, 0xe0303f54, 0x283a0203, 
+    0xe05f0090, 0xe0000490, 0x78e0a3fe, 0x13c3ce02, 0xf9d813ce, 0x30530490, 0x057405e0, 0x740380f0, 
+    0x0490f014, 0xa3fee000, 0xce0278e0, 0x13ce13c3, 0xe030f9d8, 0x7873120b, 0xee200490, 0xf0efa3f0, 
+    0x90b06412, 0xf0ee2404, 0x12f0efa3, 0x04908b74, 0xf5f0ef56, 0x5f009012, 0x000490e0, 0xe0a3fee0, 
+    0xc3ce0278, 0xd813ce13, 0x66e030f9, 0xe07c0490, 0x04900b60, 0x94c3e056, 0x8002500f, 0x20049065, 
+    0xe0a3fee0, 0x250490ff, 0x90fd2fe0, 0x3ee02404, 0x94edc3fc, 0x0294ecee, 0x04901a50, 0x1470e082, 
+    0x7794efc3, 0x500194ee, 0x5604900b, 0x2d94c3e0, 0x2e800250, 0x3994edd3, 0x500394ec, 0x82049006, 
+    0x903760e0, 0xffe05304, 0xe0560490, 0x2a409fd3, 0x04902580, 0x70ffe082, 0x5604900e, 0x2d94c3e0, 
+    0x04e01850, 0xef1380f0, 0x04901060, 0x90ffe053, 0xd3e05604, 0xe003409f, 0x0490f014, 0x12ffe056, 
+    0xfee0bb74, 0x08601265, 0xe05e0490, 0x0901b4fd, 0x745e0490, 0x007ff001, 0x95d3ee22, 0xed234012, 
+    0x07600464, 0xe04c0490, 0x900801b4, 0x02745e04, 0x900680f0, 0x03745e04, 0x560490f0, 0x1295c3e0, 
+    0x049022ff, 0x0364e05e, 0x04900760, 0x01b4e04c, 0x5e049008, 0x80f00274, 0x5e049006, 0x90f00474, 
+    0xffe05604, 0x9f12e5c3, 0x22ff04f4, 0x8fba6712, 0x74741212, 0x020370ef, 0x04901f3c, 0x94c3e015, 
+    0x0094e4fb, 0x3c020340, 0x2404901f, 0xa30470e0, 0x706364e0, 0x1f3c0203, 0xe0490490, 0x387f3070, 
+    0xee807412, 0xfde09533, 0x120a78fc, 0x04c03c26, 0x06c005c0, 0x397f07c0, 0xee807412, 0xd0fe0354, 
+    0xd002d003, 0xeb00d001, 0x4eeaff4f, 0x04907180, 0xa3fee024, 0x94c3ffe0, 0x8064eef0, 0x36407f94, 
+    0x0f94efd3, 0x948064ee, 0x7f2b5080, 0x80741234, 0xe09533ee, 0x0a78fcfd, 0xc03c2612, 0xc005c004, 
+    0x7f07c006, 0xb3741235, 0x02d003d0, 0x00d001d0, 0xeaff4feb, 0x367f2980, 0xee807412, 0xfde09533, 
+    0x120a78fc, 0x04c03c26, 0x06c005c0, 0x377f07c0, 0xd0b37412, 0xd002d003, 0xeb00d001, 0xfeeaff4f, 
+    0xfce8fde9, 0x75d15f12, 0x38e502f0, 0xf5c124a4, 0x34f0e582, 0xe483f577, 0x0174fc93, 0x0490fd93, 
+    0x7afbe077, 0xfd2bed00, 0x74fc3cea, 0x82f52d00, 0xf53c0174, 0x12f0ef83, 0xefd30a74, 0x61948064, 
+    0x90c37350, 0x94e02504, 0x2404901f, 0x948064e0, 0x12585080, 0x1f7f0566, 0x12546f12, 0x04900e71, 
+    0xf012e577, 0xe502f075, 0xc124a438, 0xf0e582f5, 0x83f57734, 0x74fe93e4, 0x90ff9301, 0xfde07704, 
+    0x2def007c, 0xfe3eecff, 0xf52f0074, 0x3e017482, 0xf0e483f5, 0x94c312e5, 0x7f0440ff, 0x90068000, 
+    0x04e07704, 0x770490ff, 0x9022f0ef, 0xf0e42404, 0xf06374a3, 0x0a741222, 0x12ff14ef, 0x7112546f, 
+    0x7704900e, 0x22f012e5, 0x7501a575, 0xa775ffa6, 0x409a75fe, 0x75c0a575, 0xa775ffa6, 0x209a753f, 
+    0xe0500090, 0xe0a313c3, 0x54007e13, 0x94d3ff1f, 0x0094ee10, 0x04901e40, 0x54c4e07f, 0x09e0200f, 
+    0x1694efd3, 0x400094ee, 0x8804900b, 0x5413c4e0, 0x04e03007, 0x0280017f, 0x25ef007f, 0xf50254e0, 
+    0x500090a4, 0xa313c3e0, 0x007e13e0, 0xd3ff1f54, 0x94ee1094, 0x90204000, 0xc4e07f04, 0xe0200f54, 
+    0x94efd309, 0x0094ee16, 0x04900d40, 0x13c4e088, 0xe0300754, 0x74008002, 0x75a5f504, 0xa775fda6, 
+    0x219a7593, 0x7520a475, 0xa67520a5, 0xc0a775c0, 0x90229a75, 0xc3e05000, 0x13e0a313, 0x1f54007e, 
+    0x1094d3ff, 0x400094ee, 0x7f04901f, 0x0f54c4e0, 0xd309e020, 0xee1694ef, 0x0c400094, 0xe0880490, 
+    0x541313c4, 0x04e03003, 0x0280017f, 0x25ef007f, 0xf50254e0, 0x500090a4, 0xa313c3e0, 0x007e13e0, 
+    0xd3ff1f54, 0x94ee1094, 0x90214000, 0xc4e07f04, 0xe0200f54, 0x94efd309, 0x0094ee16, 0x04900e40, 
+    0x13c4e088, 0x30035413, 0x008002e0, 0xa5f50474, 0x75fda675, 0x9a7593a7, 0x20a47523, 0x7520a575, 
+    0xa775c0a6, 0x249a75c0, 0x7504a575, 0xa775ffa6, 0x259a7593, 0x7520a475, 0xa67520a5, 0xc0a775c0, 
+    0x75269a75, 0xa67504a5, 0x93a775ff, 0x75279a75, 0xa57520a4, 0xc0a67520, 0x75c0a775, 0xa575289a, 
+    0xffa67504, 0x7593a775, 0xa475299a, 0x20a57520, 0x75c0a675, 0x9a75c0a7, 0x0490222a, 0xffe0a300, 
+    0x1a8f027d, 0xe05a0090, 0xe0a31bf5, 0xe5c31cf5, 0xe5f8941c, 0x4002941b, 0x3a3f0203, 0xe0650090, 
+    0x03700164, 0x903a3f02, 0xc3e00504, 0x0203509d, 0x00903a3f, 0xffb4e05d, 0x241ce515, 0x35e4ff0c, 
+    0xefd3fe1b, 0x94eef894, 0x02034002, 0x33e53a3f, 0x3e020360, 0xcb7212cf, 0x358f348e, 0xe0600090, 
+    0x5411e030, 0x0090f0fe, 0xf004e067, 0x00900670, 0xf004e066, 0x670090d3, 0x900094e0, 0x94e06600, 
+    0x02035000, 0x0274cf3e, 0x82f51c25, 0x1b350174, 0xff7483f5, 0x660090f0, 0xe0a3fce0, 0x74ffecfd, 
+    0xf51c2501, 0x35017482, 0xef83f51b, 0x250074f0, 0x7482f51c, 0xf51b3501, 0x74f0ed83, 0xf51c2503, 
+    0x1b35e41c, 0xe5c31bf5, 0xe5f8941c, 0x4002941b, 0x1df5e43f, 0x08241ce5, 0x341be5ff, 0xe5c3fefd, 
+    0x9ee49f1d, 0xf8741e50, 0x82f51d25, 0xf50334e4, 0x74ffe083, 0xf51d2500, 0x0134e482, 0xf0ef83f5, 
+    0xd0801d05, 0x1c250874, 0xfd741cf5, 0x1bf51b35, 0x660090e4, 0x74f0a3f0, 0xf51c2500, 0x35017482, 
+    0xe583f51b, 0x1c05f01a, 0x02701ce5, 0x94c31b05, 0x941be5f8, 0xe43f4002, 0x1ce51df5, 0xe5ff0824, 
+    0xfefd341b, 0x9f1de5c3, 0x1e509ee4, 0x1d25f874, 0x34e482f5, 0xe083f503, 0x250074ff, 0xe482f51d, 
+    0x83f50134, 0x1d05f0ef, 0x0874d080, 0x1cf51c25, 0x1b35fd74, 0x33051bf5, 0xe55a0090, 0xe5a3f01b, 
+    0x9022f01c, 0x90e04504, 0x90f04f04, 0xffe00d04, 0x9fc3e0a3, 0x0094e4ff, 0xfe13e7a2, 0x90ff13ef, 
+    0xf0ee2404, 0x90f0efa3, 0x64e04c04, 0x90367001, 0xc3e07d04, 0x51400794, 0x0490f0e4, 0xa3fce024, 
+    0x94d3fde0, 0x8064ec0c, 0x07408094, 0xe0450490, 0xc3328014, 0xecf494ed, 0x7f948064, 0x04902b50, 
+    0x8004e045, 0x25049020, 0xff0424e0, 0xe0240490, 0xeffe0034, 0xa2ce0378, 0x13ce13e7, 0x90fff8d8, 
+    0xc3e04504, 0x4f04909f, 0x4f0490f0, 0x64c3ffe0, 0x50989480, 0xf0187405, 0xefd30e80, 0xac948064, 
+    0x04900640, 0xf02c744f, 0xe04f0490, 0x450490ff, 0x706ffee0, 0xb5400203, 0x9533fdee, 0x33effce0, 
+    0xc3fee095, 0xeeff9def, 0x78effe9c, 0xce33c303, 0xf9d8ce33, 0x240490ff, 0xefa3f0ee, 0x4f0490f0, 
+    0x0490ffe0, 0x5e12f045, 0x0e04909f, 0x0490ffe0, 0xff2fe025, 0xe0240490, 0x90fe0034, 0xa3f02604, 
+    0xeec3f0ef, 0x80948064, 0x90e40950, 0xa3f02604, 0xd31780f0, 0xe0270490, 0x0490f894, 0x8064e026, 
+    0x06408094, 0x74a3f0e4, 0x0490f0f8, 0x90e0a326, 0x90f00e04, 0xffe00d04, 0xe0240490, 0xfde0a3fc, 
+    0xff9defc3, 0xa3fe9ce4, 0xf0efa3f0, 0x8064eec3, 0x09508094, 0x260490e4, 0x80f0a3f0, 0x0490d317, 
+    0xf894e027, 0xe0260490, 0x80948064, 0xf0e40640, 0xf0f874a3, 0xa3260490, 0x0d0490e0, 0x22007ff0, 
+    0x838c828d, 0x047907ad, 0x017afce4, 0x6423e5d3, 0x64edf880, 0x22509880, 0x806423e5, 0x8064ebf8, 
+    0xc3175098, 0x806422e5, 0x8064edf8, 0xe50b4098, 0xf8806422, 0x988064eb, 0x007f0350, 0x6d24e522, 
+    0x82e55370, 0x02708345, 0xebd322ff, 0xedf88064, 0x40988064, 0xd3ff7a02, 0x009482e5, 0x806483e5, 
+    0x06408094, 0x82af83ae, 0xe4c30980, 0xe4ff8295, 0x8efe8395, 0xd3268f25, 0x009421e5, 0x806420e5, 
+    0x06408094, 0x21af20ae, 0xe4c36180, 0xe4ff2195, 0x80fe2095, 0x6b24e556, 0x21e55770, 0x02702045, 
+    0xedd322ff, 0xebf88064, 0x40988064, 0xd3ff7a02, 0x009421e5, 0x806420e5, 0x06408094, 0x21af20ae, 
+    0xe4c30980, 0xe4ff2195, 0x8efe2095, 0xd3268f25, 0x009482e5, 0x806483e5, 0x06408094, 0x82af83ae, 
+    0xe4c30980, 0xe4ff8295, 0x8efe8395, 0x80288f27, 0x22007f03, 0xd3edfde4, 0xc3505099, 0x289526e5, 
+    0x806427e5, 0x6425e5f8, 0x50ec9880, 0xfce0251e, 0x9528e5c3, 0x27e5cf26, 0x24cf2595, 0x0034cf01, 
+    0xf513e7a2, 0xf513ef27, 0x251d8028, 0xc3fc04e0, 0x289526e5, 0x9525e5cf, 0x0124cf27, 0xa20034cf, 
+    0x25f513e7, 0x26f513ef, 0xecab800d, 0xe09533ff, 0x0124effe, 0xa23ee4ff, 0x13ef13e7, 0x04ffbafc, 
+    0x22ff04f4, 0x7f2204af, 0xae74123b, 0xff0754ef, 0x06c0007e, 0x3b7f07c0, 0xefae7412, 0x13133f54, 
+    0xfd1f5413, 0xff2de0d0, 0x0034e0d0, 0xeffe13c3, 0x06c0ff13, 0x3b7f07c0, 0xefb37412, 0xd0fd3f54, 
+    0x13f52de0, 0x0034e0d0, 0x3c7f12f5, 0xefb37412, 0x7eff1f54, 0xc006c000, 0x123c7f07, 0x54efae74, 
+    0x1313133f, 0xd0fd1f54, 0x1bf52de0, 0x0034e0d0, 0x3c7f1af5, 0xefb37412, 0x13c47f54, 0x64035413, 
+    0xc30a7001, 0xe4ff1b95, 0x80fe1a95, 0xaf1aae04, 0x8f168e1b, 0x123c7f17, 0x54efb374, 0x007eff1f, 
+    0x07c006c0, 0x74123c7f, 0x0754efae, 0x2de0d0fd, 0xe0d01df5, 0x1cf50034, 0x74123c7f, 0x3f54efb3, 
+    0x075413c4, 0x0a700164, 0xff1d95c3, 0xfe1c95e4, 0x1cae0480, 0x17e51daf, 0x16e5ff2f, 0x13e7a23e, 
+    0x13ef14f5, 0x3d7f15f5, 0xefb37412, 0x7eff3f54, 0x7c207d00, 0xb4731200, 0xe09533ef, 0x198f18f5, 
+    0x192515e5, 0x14e51ff5, 0x1ef51835, 0x74123d7f, 0x0754ee80, 0x7c007dfe, 0xb4731204, 0xce0678ef, 
+    0xce13e7a2, 0xfff8d813, 0xfee09533, 0xfde025ef, 0xe5fc33ee, 0xffe02519, 0xfe3318e5, 0xcf2f1fe5, 
+    0xcf3e1ee5, 0xfe3ccf2d, 0x07c006c0, 0x74123d7f, 0x0b78ef80, 0x13e7a2ce, 0xf8d813ce, 0xe09533fd, 
+    0x2de0d0fc, 0x3ce0d0ff, 0x5f0090fe, 0x2d7f22e0, 0x12bb7412, 0x04908b74, 0x75f0ef56, 0xa67508a4, 
+    0xffa775f6, 0xe4409a75, 0x546f12ff, 0xe0000490, 0xfde0a3fc, 0x077804ae, 0xce13c3ce, 0x20f9d813, 
+    0x049032e0, 0xe020e006, 0x04aeed2b, 0xc3ce0278, 0xd813ce13, 0x10e030f9, 0xe0890490, 0xa4750560, 
+    0x75088001, 0x038004a4, 0x7507a475, 0xa775f0a6, 0x419a75ff, 0xe0490490, 0x60142460, 0x60fb2418, 
+    0x60fe2408, 0x70052404, 0x4504904a, 0xa3f02a74, 0x80f01574, 0x0490e447, 0xf0a3f045, 0x04903e80, 
+    0x30ffe004, 0x7f5408e7, 0xf0450490, 0x04901e80, 0xa3fee000, 0xce0278e0, 0x13ce13c3, 0x0490f9d8, 
+    0x05e03045, 0x80f02474, 0xf0207403, 0x460490e4, 0x900980f0, 0x20744504, 0xf0a3e4f0, 0xe0500090, 
+    0xe0a313c3, 0xc31f5413, 0x94e40594, 0x6d049000, 0xff740550, 0x740380f0, 0x0490f0fe, 0x12ffe045, 
+    0x04909f5e, 0x12ffe046, 0x0490d25a, 0xa3fee000, 0xce0278e0, 0x13ce13c3, 0xe030f9d8, 0x203c1203, 
+    0xe0490490, 0x1f700164, 0xe0000490, 0x78e0a3fe, 0x13c3ce02, 0xf9d813ce, 0x750ce030, 0xa67501a4, 
+    0xffa775fe, 0x75989a75, 0xa67520a4, 0xffa775df, 0x90109a75, 0x01744404, 0x049022f0, 0xe024e040, 
+    0x70145360, 0xf4450203, 0x6c120080, 0x490490c8, 0x020360e0, 0x0490b045, 0xa3fee000, 0xce0278e0, 
+    0x13ce13c3, 0xe020f9d8, 0xb0450203, 0x74500490, 0xa3e4f001, 0x500490f0, 0x6612ffe0, 0x2760efe3, 
+    0xe48d6812, 0xf04d0490, 0xf04b0490, 0x900e7112, 0x20744004, 0x747412f0, 0x7f0370ef, 0x18122202, 
+    0x4d0490d3, 0x90e560e0, 0xc3e05000, 0x13e0a313, 0x1f54007e, 0x1094d3ff, 0x400094ee, 0x7f049040, 
+    0x0f54c4e0, 0xd309e020, 0xee1694ef, 0x2d400094, 0xe0500490, 0x0b01b4ff, 0xe0880490, 0x075413c4, 
+    0xef10e030, 0x901602b4, 0xc4e08804, 0x03541313, 0x900ae020, 0x70e05104, 0x80f00404, 0x0490e40b, 
+    0x0490f051, 0xf004e050, 0xe0500490, 0x948064c3, 0x02035086, 0x65800d45, 0xe0490490, 0x5d700164, 
+    0xe0000490, 0x78e0a3fe, 0x13c3ce02, 0xf9d813ce, 0x904ae030, 0x02745004, 0xf0a3e4f0, 0xe0500490, 
+    0xe36612ff, 0x122760ef, 0x90e48d68, 0x90f04d04, 0x12f04b04, 0x04900e71, 0xf0217440, 0xef747412, 
+    0x027f0370, 0xd3181222, 0xe04d0490, 0x0490e560, 0x0224e050, 0x64c3e0f0, 0x40859480, 0x0490e4bf, 
+    0x22fff040, 0x900a7412, 0xf0ef4f04, 0x140490e4, 0x90f0a3f0, 0x54e01704, 0x0094d308, 0xf5e40540, 
+    0x750380a4, 0xa67508a4, 0xffa775f7, 0x90409a75, 0x54e01704, 0x0008b407, 0x46020340, 0x5c4690f8, 
+    0x732828f8, 0x02744602, 0x46028346, 0xad460292, 0x02c84602, 0x4602ca46, 0xe44602cf, 0x6f121f7f, 
+    0x46049054, 0x5a12ffe0, 0x7f5680d2, 0x546f12e1, 0xe0460490, 0xd25a12ff, 0xffe45c80, 0x90546f12, 
+    0x70e04904, 0x12207f09, 0xff7f5f6a, 0xfe7f0280, 0x805f6a12, 0x12ffe42c, 0x0490546f, 0x0970e049, 
+    0x6a12e07f, 0x80017f5f, 0x12027f02, 0x26805f6a, 0x47120080, 0x7f298053, 0x096a1220, 0x6a12ff7f, 
+    0x24049009, 0x74a3f0e4, 0x1480f01f, 0x6a12e07f, 0x12017f09, 0x0490096a, 0xf0ff7424, 0xf0e174a3, 
+    0xe0170490, 0x1234e220, 0x04909673, 0x94d3e049, 0x90254000, 0xffe01704, 0x94d30254, 0xef194000, 
+    0x94d30154, 0x75084001, 0xa67502a5, 0x750680ff, 0xa67508a5, 0x329a75ff, 0x120e7112, 0x017beb6e, 
+    0x5479047a, 0xe4746612, 0xf0160490, 0xf0770490, 0xf0380490, 0xf0a3f0a3, 0xe422f0a3, 0xf0260490, 
+    0x447ff0a3, 0xefb37412, 0x7eff3f54, 0x7c207d00, 0xb4731200, 0xe09533ef, 0x90c07412, 0xf0ef7804, 
+    0x7412437f, 0x3f54efb3, 0x7d007eff, 0x12007c20, 0x7412b473, 0x790490c0, 0x64d3f0ef, 0x40809480, 
+    0x80ffe004, 0x79049007, 0xff04f4e0, 0xe0780490, 0x8064d3fe, 0x02408094, 0x04900780, 0x04f4e078, 
+    0x64efd3fe, 0x64eef880, 0x07409880, 0xe0270490, 0x90f00444, 0xd3e07804, 0x80948064, 0x04900740, 
+    0x0244e027, 0x790490f0, 0x8064d3e0, 0x07408094, 0xe0270490, 0x90f00144, 0xc4e01704, 0x60140354, 
+    0x59601449, 0x24696014, 0x02036003, 0x04908748, 0xa3fee026, 0x94c3ffe0, 0x8064ee04, 0x0a408094, 
+    0x13e7a2ee, 0x007e13ef, 0x007e0680, 0xe0270490, 0xc3ff0154, 0xe0270490, 0x04900494, 0x8064e026, 
+    0x007d8094, 0x017d0240, 0x04904280, 0x0154e017, 0x7f0094d3, 0x7f024000, 0x80fde401, 0x1704902f, 
+    0xd30154e0, 0x007f0094, 0x017f0240, 0x1c80017d, 0xe0260490, 0xa313e7a2, 0x015413e0, 0x12017dff, 
+    0x04903c54, 0x54e0a326, 0xfde4ff01, 0x223c5412, 0x04901d8f, 0xa3f0e424, 0xedf00e74, 0x49020370, 
+    0x601de527, 0x12447f3a, 0x54efb374, 0x007eff3f, 0x007c207d, 0x12b47312, 0x0490c074, 0x64c3e078, 
+    0x64eff880, 0x17509880, 0x7412447f, 0x3f54efb3, 0x7d007eff, 0x12007c20, 0x24efb473, 0xe5428001, 
+    0x0203601d, 0x447faf49, 0xefb37412, 0x7eff3f54, 0x7c207d00, 0xb4731200, 0x90c07412, 0xd3e07804, 
+    0xeff88064, 0x50988064, 0xaf490203, 0x7412447f, 0x3f54efb3, 0x7d007eff, 0x12007c20, 0x24efb473, 
+    0xf5efffff, 0xc0a675a4, 0x75ffa775, 0xe522449a, 0x7f3a601d, 0xb3741243, 0xff3f54ef, 0x207d007e, 
+    0x7312007c, 0xc07412b4, 0xe0790490, 0xf88064c3, 0x988064ef, 0x437f1750, 0xefb37412, 0x7eff3f54, 
+    0x7c207d00, 0xb4731200, 0x800124ef, 0x701de53c, 0x12437f46, 0x54efb374, 0x007eff3f, 0x007c207d, 
+    0x12b47312, 0x0490c074, 0x64d3e079, 0x64eff880, 0x23409880, 0x7412437f, 0x3f54efb3, 0x7d007eff, 
+    0x12007c20, 0x24efb473, 0xf5efffff, 0xc0a675a4, 0x75ffa775, 0xe422439a, 0xf0240490, 0x9022f0a3, 
+    0x24e04004, 0x805d60ee, 0x49049000, 0x020360e0, 0x04909b4a, 0xc4ffe087, 0x03541313, 0x0203e030, 
+    0x6c129b4a, 0x0a7412c8, 0xef4e0490, 0x460490f0, 0x520490e0, 0x120f7ff0, 0x90e47f6e, 0x90f04b04, 
+    0xffe04b04, 0x500494c3, 0xb4e0a34c, 0x59120501, 0x9008807d, 0xffe04b04, 0x12c86312, 0x04900e71, 
+    0xf0127440, 0xef747412, 0x027f0370, 0x4c049022, 0x0b01b4e0, 0xe04b0490, 0xd11e12ff, 0x900880ef, 
+    0xffe04b04, 0x900d2712, 0x60e04d04, 0x4b0490ce, 0x80f004e0, 0x520490aa, 0x5a12ffe0, 0x4e0490d2, 
+    0x6f12ffe0, 0x456e1254, 0x700164ef, 0x06049036, 0x13c4ffe0, 0x20035413, 0x017d29e0, 0x31121b7f, 
+    0x7f0490b9, 0x1313ffe0, 0x201f5413, 0xa4750fe0, 0xfea67501, 0x75ffa775, 0x017f199a, 0x8b049022, 
+    0x90f00174, 0x30744004, 0x7d0490f0, 0x90f004e0, 0x70e04904, 0x00049033, 0xe0a3fce0, 0x7804aefd, 
+    0x13c3ce02, 0xf9d813ce, 0xed1de020, 0x077804ae, 0xce13c3ce, 0x20f9d813, 0x04900ee0, 0xc4ffe087, 
+    0xe0200f54, 0x3b3f0203, 0x7522007f, 0x21750020, 0x16227500, 0x007a007b, 0x1d8b1279, 0x1f891e8a, 
+    0x21aa20ab, 0x261222a9, 0x1203784f, 0x007b2926, 0x2379007a, 0x75925212, 0x38e502f0, 0xf5c124a4, 
+    0x34f0e582, 0xe483f577, 0x0174fc93, 0x0490fd93, 0xfbfee077, 0x2bed007a, 0xfc3ceafd, 0xf52d0074, 
+    0x3c017482, 0xf0ef83f5, 0xff94c3ee, 0x007e0640, 0x0780ff7f, 0xff0124eb, 0x90fe3ae4, 0xf0ef7704, 
+    0x1eaa1dab, 0x26121fa9, 0x7a007b4f, 0x12247900, 0x07a99252, 0x54c423e5, 0xff2445f0, 0xe502f075, 
+    0xc124a438, 0xf0e582f5, 0x83f57734, 0x74fc93e4, 0x90fd9301, 0xfee07704, 0xed007afb, 0x3ceafd2b, 
+    0x2d0074fc, 0x017482f5, 0xef83f53c, 0x94c3eef0, 0x7f0440ff, 0xeb0680ff, 0xe4ff0124, 0x7704903a, 
+    0xf075f0ef, 0xa438e502, 0x82f5c124, 0x7734f0e5, 0x93e483f5, 0x930174fe, 0x770490ff, 0x7afbfde0, 
+    0xff2bef00, 0x74fe3eea, 0x82f52f00, 0xf53e0174, 0xedf0e983, 0x40ff94c3, 0x80ff7f04, 0x0124eb04, 
+    0x770490ff, 0x9022f0ef, 0xfce02404, 0xecfde0a3, 0xed188fff, 0xd3178fff, 0x806417e5, 0x1b509f94, 
+    0x6417e5c3, 0x40619480, 0x18e5d312, 0x9f948064, 0xe5c30950, 0x94806418, 0x74155061, 0x14049080, 
+    0x18e5a3f0, 0x780490f0, 0x17e5a3f0, 0x22017ff0, 0x900a7412, 0xf0ef4f04, 0x6f1217af, 0x96731254, 
+    0xe0490490, 0x18af0870, 0xe09533ef, 0xe5c37780, 0x94806418, 0xaf2a5070, 0x9533ef18, 0x24effee0, 
+    0x3ee4ff1f, 0xe025effe, 0xfe33eeff, 0xff0224ef, 0x04903ee4, 0xefa3f024, 0x02a575f0, 0x80ffa675, 
+    0x18e5d332, 0x8f948064, 0x18af2e40, 0xe09533ef, 0xe124effe, 0xff34eeff, 0xe025effe, 0xfe33eeff, 
+    0xff0224ef, 0x04903ee4, 0xefa3f024, 0x08a575f0, 0x75ffa675, 0x1480329a, 0x33ef18af, 0xeffee095, 
+    0xeeffe025, 0x24049033, 0xf0efa3f0, 0xa3240490, 0x6a12ffe0, 0x7a007b5f, 0x12167900, 0x6e127466, 
+    0x0e7112eb, 0xe4140490, 0xf004a3f0, 0xe5780490, 0xe5a3f018, 0x007ff017, 0xf5fde422, 0x9014f513, 
+    0xfee00004, 0x0278e0a3, 0xce13c3ce, 0x20f9d813, 0x4d0203e0, 0x4e0490d9, 0x64d3ffe0, 0x40809480, 
+    0x90078002, 0xf4e04e04, 0xefc3ff04, 0x88948064, 0xfde40850, 0xf0580490, 0x04907380, 0xd3ffe04e, 
+    0x80948064, 0x07800240, 0xe04e0490, 0xc3ff04f4, 0x948064ef, 0x7d0a5090, 0x58049010, 0x80f00474, 
+    0x4e04904c, 0x64d3ffe0, 0x40809480, 0x90078002, 0xf4e04e04, 0xefc3ff04, 0x98948064, 0x207d0a50, 
+    0x74580490, 0x2580f008, 0xe04e0490, 0x8064d3ff, 0x02408094, 0x04900780, 0x04f4e04e, 0x64efc3ff, 
+    0x50a09480, 0x90307d08, 0x0c745804, 0x12017ff0, 0x0490a52b, 0xa4f5e058, 0x75f0a675, 0x9a75ffa7, 
+    0x4e049041, 0x8064c3e0, 0x06508094, 0xff7f3f7e, 0xc07e0480, 0x138e007f, 0x25ef148f, 0xe5a4f5e0, 
+    0xe5e02514, 0xa5f53313, 0x7501a675, 0xa475029a, 0x7fa67580, 0x75ffa775, 0xf5e4019a, 0x7fa675a4, 
+    0x75ffa775, 0x007f019a, 0xe1157522, 0x751f1675, 0x387fff14, 0x8e807412, 0xd3138f12, 0x1f9413e5, 
+    0x806412e5, 0x08408094, 0x757f1275, 0x2c80ff13, 0x9413e5c3, 0x6412e5e0, 0x507f9480, 0xf5ff7408, 
+    0x8013f512, 0x12397f17, 0x54ee8074, 0x07adfc03, 0xe02513e5, 0xf54ce025, 0x13f5ed12, 0xe0460490, 
+    0x049017f5, 0x90fbe04e, 0xf5e01e04, 0xf5e0a320, 0x22158521, 0x85231685, 0x13ad2414, 0x17af12ac, 
+    0x8fba5112, 0x62049018, 0xef4b60e0, 0xfee09533, 0x54f8c4ef, 0xff68c80f, 0xf054c4ee, 0x32049048, 
+    0xf0efa3f0, 0xe04e0490, 0x1e0490fb, 0xa320f5e0, 0x8521f5e0, 0x16852215, 0x24188523, 0x12ac13ad, 
+    0x401217af, 0x9533efb8, 0x0490fee0, 0xf02fe033, 0xe0320490, 0x0490f03e, 0xf017e54e, 0xe51e0490, 
+    0xe5a3f012, 0x0490f013, 0x0490e062, 0x18aff04d, 0x90d25a02, 0xa3e01404, 0x0203e730, 0xa475f34f, 
+    0xdfa67520, 0x75ffa775, 0x007b119a, 0x1279007a, 0x756c5312, 0x1b8f001a, 0x01641be5, 0x03601a45, 
+    0x12e64f02, 0x04904f67, 0xf0017411, 0xe0490490, 0x04900d70, 0xf0a3f018, 0xf0a3f0a3, 0x90d94f02, 
+    0xffe07804, 0x948064c3, 0xd3244070, 0x948064ef, 0x7f1c508f, 0x80741234, 0xe09533ee, 0x0a78fcfd, 
+    0xc03c2612, 0xc005c004, 0x7f07c006, 0x7f1a8035, 0x80741236, 0xe09533ee, 0x0a78fcfd, 0xc03c2612, 
+    0xc005c004, 0x7f07c006, 0xb3741237, 0x02d003d0, 0x00d001d0, 0x19f54feb, 0xe918f5ea, 0xf5e817f5, 
+    0xae19af16, 0xfc17ad18, 0x26121078, 0x18049029, 0xefa3f0ee, 0xff19e5f0, 0xa3fe18e5, 0xefa3f0ee, 
+    0x441ae5f0, 0x140490ec, 0xa31be5f0, 0xf5e422f0, 0xdfa675a4, 0x75ffa775, 0x2222119a, 0x75e11575, 
+    0x04901f16, 0x90ffe063, 0xc3e06704, 0xd312f59f, 0x78948064, 0x13750550, 0xc3118001, 0x806412e5, 
+    0x05408894, 0x80ff1375, 0x13f5e403, 0x7412467f, 0x3f54efb3, 0x7d007eff, 0x12007c20, 0x13e5b473, 
+    0xc314f52f, 0x806415e5, 0x6414e5f8, 0x03509880, 0xd3141585, 0x806416e5, 0x6414e5f8, 0x03409880, 
+    0x90141685, 0xffe06404, 0xe0680490, 0x12f59fc3, 0x948064d3, 0x75055078, 0x11800113, 0x6412e5c3, 
+    0x40889480, 0xff137505, 0xf5e40380, 0x12457f13, 0x54efb374, 0x007eff3f, 0x007c207d, 0xe5b47312, 
+    0xc3ff2f13, 0x806415e5, 0x8064eff8, 0xaf025098, 0x16e5d315, 0xeff88064, 0x40988064, 0xef16af02, 
+    0xa4f53f54, 0x75c0a675, 0x9a75ffa7, 0xef14af45, 0xa4f53f54, 0x75c0a675, 0x9a75ffa7, 0x417f2246, 
+    0xefb37412, 0x90ff0f54, 0x90f05804, 0xf0e42204, 0x90f0efa3, 0xfee02804, 0xd3ffe0a3, 0x64ee0094, 
+    0x40809480, 0x900f8002, 0xfee02804, 0xc3ffe0a3, 0xe4ff9fe4, 0xefd3fe9e, 0x64ee0494, 0x50809480, 
+    0x4c049008, 0x600164e0, 0x58049058, 0x0490ffe0, 0xa3fce028, 0x0490fde0, 0xfbfee05a, 0xe02a0490, 
+    0xe0a320f5, 0xf5e421f5, 0x0f237522, 0x90b75112, 0xf0ef5804, 0xa3220490, 0x5a0490e0, 0x620490f0, 
+    0x1601b4e0, 0xe05a0490, 0x580490ff, 0x5c0490e0, 0x800207b5, 0xf0027418, 0x90e41680, 0x80f05c04, 
+    0x2204900f, 0x0490e0a3, 0x0490f05a, 0xf001745c, 0xe0280490, 0xa3e0a3ff, 0xefa3f0cf, 0x4c0490f0, 
+    0x0b01b4e0, 0xe05c0490, 0x03600164, 0x90f00274, 0xf5e05804, 0xf0a675a4, 0x75ffa775, 0x7522419a, 
+    0x1c8fff24, 0x1e8d1d8c, 0xf5e41f8b, 0xe527f526, 0x701d451e, 0x251c850a, 0x04620490, 0xc37580f0, 
+    0x80641de5, 0x0c508094, 0x009421e5, 0x806420e5, 0x15508094, 0x941ee5d3, 0x641de500, 0x40809480, 
+    0x6420e535, 0x50809480, 0xae21af2d, 0x1d741220, 0x07c006c0, 0x1dae1eaf, 0xd01d7412, 0xc304d005, 
+    0x9cee9def, 0x1c850550, 0x85038025, 0x0490251f, 0xf0017462, 0xe5c31e80, 0x9480641d, 0x40ff7f80, 
+    0xef017f02, 0xa4f02485, 0x1ce5c3ff, 0xe425f59f, 0xf0620490, 0x6423e5d3, 0x25e5f880, 0x40988064, 
+    0x25238505, 0xe5c31080, 0xf8806422, 0x806425e5, 0x850c5098, 0x26752522, 0x62049001, 0xe5f00174, 
+    0x60236525, 0xb525e505, 0x27750322, 0x60049001, 0xa3f026e5, 0xaff027e5, 0x288f2225, 0x268d278e, 
+    0x298b258c, 0x2b892a8a, 0xfdfeffe4, 0xaa28abfc, 0xa826a927, 0x2612c325, 0xab0b7018, 0xa92aaa29, 
+    0xde25122b, 0xf5e422ff, 0x7eff7f2c, 0xfc7f7dff, 0x27aa28ab, 0x25a826a9, 0x182612d3, 0x28750c40, 
+    0xff2775ff, 0x757f2675, 0x28af0025, 0x26ad27ae, 0x017825ac, 0x8f3c2612, 0x8d278e28, 0x05258c26, 
+    0xfeffe42c, 0x5425e5fd, 0xfbe4fc80, 0xc3f8f9fa, 0x60182612, 0x752ce5d5, 0x251220f0, 0xc3f0af81, 
+    0xab9f1f74, 0xa92aaa29, 0xde25122b, 0x2aaa29ab, 0x25122ba9, 0x94c3fba3, 0xe41d5008, 0xe5fdfeff, 
+    0xf4ebfc25, 0xf91f2404, 0x292612f8, 0x29ab2d8f, 0x12e42ba9, 0x1980de25, 0xfdfeffe4, 0x78fc25e5, 
+    0x29261218, 0x29ab2d8f, 0x2ba92aaa, 0x2512f974, 0x222dafbc, 0x1e8a1d8b, 0x6d121f89, 0x8e238f0c, 
+    0x8c218d22, 0x20049020, 0xe0a3fee0, 0xfdfce4ff, 0x26121078, 0xa904a83c, 0xab06aa05, 0xfee0a307, 
+    0xebffe0a3, 0x4eeafb4f, 0x23e5c3fa, 0x22e5ff9b, 0x21e5fe9a, 0x20e5fd99, 0x1dabfc98, 0x1fa91eaa, 
+    0x906f2612, 0xfee03404, 0xe4ffe0a3, 0x1078fdfc, 0xa83c2612, 0xaa05a904, 0xa307ab06, 0xe0a3fee0, 
+    0xfb4febff, 0xc3fa4eea, 0xf59b23e5, 0x9a22e527, 0x21e526f5, 0xe525f599, 0x24f59820, 0xe0110490, 
+    0x901f05b4, 0xffe06100, 0xfefdfce4, 0x26120778, 0xaa27ab3c, 0xa825a926, 0x2612d324, 0x7f224018, 
+    0x00902201, 0xe4ffe061, 0x78fefdfc, 0x3c261211, 0x26aa27ab, 0x24a825a9, 0x182612d3, 0x017f0340, 
+    0x22007f22, 0x60ed168f, 0x6016e54f, 0x12f17f27, 0x33efc174, 0xf5efe095, 0xc0a675a4, 0x75ffa775, 
+    0x0490449a, 0x54c4e017, 0x70036403, 0x06550203, 0x3f80447f, 0x74120f7f, 0x9533efc1, 0xa4f5efe0, 
+    0x75c0a675, 0x9a75ffa7, 0x17049044, 0x0354c4e0, 0x7a600364, 0x5380447f, 0x386016e5, 0x7412f17f, 
+    0x9533efc1, 0xa4f5efe0, 0x75c0a675, 0x9a75ffa7, 0x12437f43, 0x54efb374, 0x007eff3f, 0x007c207d, 
+    0xefb47312, 0xfee09533, 0x9ff174c3, 0xf0250490, 0x3580ff74, 0x74120f7f, 0x9533efc1, 0xa4f5efe0, 
+    0x75c0a675, 0x9a75ffa7, 0x12437f43, 0x54efb374, 0x007eff3f, 0x007c207d, 0xefb47312, 0xfee09533, 
+    0x9f0f74c3, 0xf0250490, 0x04909ee4, 0x1222f024, 0x90e4c86c, 0xa3f02e04, 0xa3f0a3f0, 0x830490f0, 
+    0x90f0a3f0, 0x90f08604, 0xa3f03e04, 0xa3f0a3f0, 0x90f0a3f0, 0x90f08a04, 0xa3f04404, 0xe4f02074, 
+    0x0490f0a3, 0x0490f06d, 0xf0a3f07b, 0xf07e0490, 0xf04a0490, 0xf04c0490, 0xf05a0490, 0x0490f0a3, 
+    0x0490f082, 0x0490f055, 0xf0a3f028, 0xf05c0490, 0xf0a3f0a3, 0xf02a0490, 0xf0a3f0a3, 0x0490f0a3, 
+    0x0490f05f, 0x0490f06a, 0x0490f069, 0xf0a3f06b, 0xf06f0490, 0xf0a3f0a3, 0x0490f0a3, 0xf0a3f012, 
+    0xf00d0490, 0xf0a3f0a3, 0x0490f0a3, 0xf0a3f073, 0xf0a3f0a3, 0xf06e0490, 0xf07d0490, 0xf0320490, 
+    0x0490f0a3, 0x0490f08b, 0xf0a3f014, 0xf0a3f0a3, 0xf0a3f0a3, 0xf0a3f0a3, 0xaa07ab22, 0x5c009006, 
+    0x7012ffe0, 0xe4198fe1, 0x16f515f5, 0x188b178a, 0xad0b6e12, 0x95d3ed07, 0x902d5019, 0xc3e06b04, 
+    0x24501995, 0x18af17ae, 0x54f8c4ee, 0xc4efc8f0, 0x54480f54, 0x60036403, 0xaf15ae0f, 0xcf54ef16, 
+    0x1044158e, 0x548016f5, 0x1995d3ed, 0x04904840, 0x95ffe06b, 0xed3f5019, 0x33e4fb2f, 0x2519e5fa, 
+    0x33e4ffe0, 0x9febd3fe, 0xf88064ee, 0x988064ea, 0x17ae2440, 0xc4ee18af, 0xc8f054f8, 0x0f54c4ef, 
+    0x64035448, 0xae0f6002, 0xef16af15, 0x158ecf54, 0x16f52044, 0x04900080, 0xf0017469, 0xed6b0490, 
+    0xaf15aef0, 0xf8c4ee16, 0xefc8f054, 0x480f54c4, 0x07600354, 0x15ae16af, 0x90807212, 0xffe06904, 
+    0xc1157522, 0x753f1675, 0x0490ff14, 0x0470e049, 0x0d80387f, 0xe0490490, 0x7f0401b4, 0x7f028036, 
+    0x80741238, 0x138f128e, 0x7412497f, 0x7f54efb3, 0x7d007eff, 0x12007c40, 0x178fb473, 0xe04e0490, 
+    0x1e0490fb, 0xa320f5e0, 0x8521f5e0, 0x16852215, 0x24148523, 0x12ac13ad, 0xa9ba5112, 0x4e049007, 
+    0x90f017e5, 0x12e51e04, 0x13e5a3f0, 0x620490f0, 0x4d0490e0, 0x700164f0, 0x6004901e, 0x007afbe0, 
+    0x407f067d, 0x6c12007e, 0x6104903e, 0x067dfbe0, 0x007e407f, 0xe9516d12, 0xa4f5efff, 0x7580a675, 
+    0x9a75ffa7, 0x64e9d349, 0x40809480, 0x8001af04, 0x04f4e904, 0x64efc3ff, 0x90bf9480, 0x40e03d04, 
+    0xf0024404, 0xf0fd5422, 0x12f5e422, 0xe07f0490, 0x0203e030, 0x04901058, 0xf924e040, 0x60140c60, 
+    0xe4008012, 0xf04e0490, 0x6f12f0a3, 0x40049020, 0x12f00874, 0x70ef7474, 0x22027f03, 0x8f367312, 
+    0x6012e512, 0x4e049073, 0xf01225e0, 0xf004e0a3, 0xe04e0490, 0x8064c3ff, 0x007ea094, 0x017e0250, 
+    0x8064eed3, 0x0d408094, 0x948064ef, 0x50007fa0, 0x80017f02, 0x4e049013, 0x8064c3e0, 0x007fa094, 
+    0x017f0250, 0xff04f4ef, 0x901760ef, 0xc3e04f04, 0xb0948064, 0x4d120c50, 0x40049011, 0x7ff00774, 
+    0xa4752202, 0xfea67501, 0x75ffa775, 0x017d199a, 0x3112177f, 0x22017fb9, 0x4e0490e4, 0xfff0a3f0, 
+    0xe51f8f22, 0x7001642c, 0xae23af69, 0xac21ad22, 0x4e4dec20, 0x850a704f, 0x04902d1f, 0x80f00462, 
+    0x5033ec6c, 0xfeffe412, 0x28abfcfd, 0x26a927aa, 0x261225a8, 0xe4195002, 0xfcfdfeff, 0x22aa23ab, 
+    0x20a821a9, 0x022612d3, 0x25ac1c40, 0x165033ec, 0x33ec20ac, 0x1f850550, 0x8503802d, 0x04902d24, 
+    0xf0017462, 0x20ac2780, 0xff7f33ec, 0x017f0240, 0x20ac0a80, 0xff7f33ec, 0x017f0240, 0xf02b85ef, 
+    0xe5c3ffa4, 0x2df59f1f, 0x620490e4, 0x2ae5d3f0, 0xe5f88064, 0x9880642d, 0x2a850540, 0xc310802d, 
+    0x806429e5, 0x642de5f8, 0x09509880, 0x902d2985, 0x01746204, 0x222daff0, 0xe0520090, 0xffe0a3fe, 
+    0x8002604e, 0x3f741203, 0x07ad06ac, 0xe0560090, 0x78e0a3fe, 0x13c3ce03, 0xf9d813ce, 0x9fedc3ff, 
+    0xfe9eecff, 0xe0570090, 0x0090f02f, 0xf03ee056, 0x630090e4, 0x5c0090f0, 0x94d3ffe0, 0xef2b4000, 
+    0xc324e025, 0x34e482f5, 0x7483f576, 0x50249301, 0x3493e4ff, 0x90d3fe00, 0x9fe05700, 0xe0560090, 
+    0x9007409e, 0x14e05c00, 0x00903380, 0xc3ffe05c, 0x30501494, 0x24e025ef, 0xe482f5c3, 0x83f57634, 
+    0x24930174, 0x93e4ffb0, 0xc3feff34, 0xe0570090, 0x5600909f, 0x0c509ee0, 0xe05c0090, 0x0090f004, 
+    0xf0017463, 0xe407ad22, 0xf04d0490, 0x901770ed, 0x13e00f04, 0x1f541313, 0xf0510490, 0xe00f0490, 
+    0x750490fe, 0x01bd1a80, 0x10049028, 0x131313e0, 0x04f41f54, 0xf0510490, 0xe0100490, 0x760490fe, 
+    0x24007ae0, 0x3eeaff00, 0xf0220490, 0x80f0efa3, 0x0490e405, 0x02bdf051, 0x0d049019, 0x131313e0, 
+    0x04f41f54, 0xf0500490, 0xe00d0490, 0x730490fe, 0x03bd1880, 0x0e049026, 0x131313e0, 0x04901f54, 
+    0x0490f050, 0x90fee00e, 0x7ce07404, 0xff002400, 0x04903eec, 0xefa3f022, 0xe40580f0, 0xf0500490, 
+    0xe0510490, 0x546f12ff, 0xe0500490, 0xd25a02ff, 0xe0400490, 0x0370fd24, 0x14b55a02, 0x60142960, 
+    0x7f00804d, 0xf7731201, 0x7510a475, 0xa775efa6, 0x409a75ff, 0x6c12ff7f, 0x12097fc5, 0x71126371, 
+    0x4004900e, 0x12f00474, 0x70ef7474, 0x22027f03, 0x1512ff7f, 0x4d0490b3, 0xe4e360e0, 0xc56c12ff, 
+    0x7112097f, 0x0e71128d, 0x74400490, 0x7412f005, 0x0370ef74, 0xe422027f, 0xb31512ff, 0xe04d0490, 
+    0xffe4e360, 0x7f546f12, 0x24681201, 0x7fc86c12, 0x39711209, 0x900e7112, 0x03744004, 0x747412f0, 
+    0x7f0370ef, 0x017f2202, 0x90b31512, 0x60e04d04, 0xf44f12e3, 0x7312ffe4, 0x1f8f22f7, 0x74120a7f, 
+    0xe5ffee80, 0x90ff2f1f, 0x2fe06d04, 0xe7a2e025, 0xa575ff13, 0xffa67520, 0x758fa775, 0x30ef049a, 
+    0xf5e412e7, 0xffa675a5, 0x75fba775, 0xf4ef049a, 0x0c80ff04, 0x7504a575, 0xa775ffa6, 0x049a75fb, 
+    0xe0440490, 0xa4752860, 0x80a67501, 0x75ffa775, 0xfee4049a, 0x8064efc3, 0x8064eef8, 0x753b5098, 
+    0xa67502a5, 0xfda775ff, 0x0e049a75, 0xfdefe680, 0xf57f54ed, 0xf50874a4, 0x80a675a5, 0x75f7a775, 
+    0xa575049a, 0xffa67502, 0x75fda775, 0xf5e4049a, 0xffa675a5, 0x75f7a775, 0x0490049a, 0xf01fe546, 
+    0x40049022, 0x60ef24e0, 0x9000804b, 0x60e04904, 0x115c0203, 0xe0000490, 0xf054f8c4, 0xc4e0a3c8, 
+    0x54480f54, 0x60026403, 0xc86c1270, 0x72120c7f, 0x0490e459, 0xf0a3f024, 0x744b0490, 0x0490f006, 
+    0xc3ffe04b, 0x4c501694, 0x12b56a12, 0x04900e71, 0xf0117440, 0xef747412, 0x027f0370, 0x12387f22, 
+    0x4eef8074, 0x387f2660, 0xd3807412, 0xee0094ef, 0x80948064, 0x007e0640, 0x0480017f, 0xff7fff7e, 
+    0xe0250490, 0x0490f02f, 0xf03ee024, 0xe04b0490, 0xaa80f004, 0x80236512, 0x5d049006, 0x90f00174, 
+    0x31744004, 0x22007ff0, 0xe0430490, 0x5360d324, 0x801f6014, 0x57049000, 0x8c0490e0, 0x12147ff0, 
+    0x90e42070, 0xa3f01e04, 0x0e7112f0, 0x74430490, 0x7412f02e, 0x0370ef74, 0xe422027f, 0x646012ff, 
+    0xe04d0490, 0x0490e360, 0x0490e057, 0x147ff053, 0xe4537012, 0xf01e0490, 0x7112f0a3, 0x4304900e, 
+    0x12f02d74, 0x70ef7474, 0x22027f03, 0x6012ffe4, 0x4d049064, 0xe4e360e0, 0xf0430490, 0xe0570490, 
+    0x9533fdff, 0x0490fce0, 0xd3fee053, 0x8064ec9d, 0x988074f8, 0x06af0450, 0x04900080, 0x90f0ef53, 
+    0xffe08c04, 0x7f546f12, 0x3c7f2200, 0xefb37412, 0x7eff1f54, 0xc006c000, 0x123c7f07, 0x54efae74, 
+    0x1313133f, 0xd0fd1f54, 0x15f52de0, 0x0034e0d0, 0x3c7f14f5, 0xefb37412, 0x13c47f54, 0x64035413, 
+    0xc30a7001, 0xe4ff1595, 0x80fe1495, 0xaf14ae04, 0x8f128e15, 0x123c7f13, 0x54efb374, 0x007eff1f, 
+    0x07c006c0, 0x74123c7f, 0x0754efae, 0x2de0d0fd, 0xe0d017f5, 0x16f50034, 0x74123c7f, 0x3f54efb3, 
+    0x075413c4, 0x0a700164, 0xff1795c3, 0xfe1695e4, 0x16ae0480, 0x13e517af, 0x12e5ff2f, 0x13e7a23e, 
+    0x2413effe, 0x34eeffef, 0x7e22feff, 0x7d407f00, 0x7a017b00, 0x12507900, 0x90e48926, 0xa3f05000, 
+    0x500090f0, 0x74a3f0e4, 0xa3e4f026, 0xa3f0a3f0, 0xa3f0d174, 0x90f00f74, 0x12745e00, 0x5c0090f0, 
+    0xe4f00b74, 0xf0630090, 0xf0a3f0a3, 0xf0a3f0a3, 0xf0a3f0a3, 0x04a3f0a3, 0x3f7412f0, 0xc30378ef, 
+    0xce33ce33, 0x90fff9d8, 0xf0ee5600, 0xe4f0efa3, 0x581209f5, 0xe50905d0, 0x0894c309, 0x90e4f440, 
+    0xa3f05f00, 0x5d0090f0, 0x90e4f004, 0xa3f05800, 0xa3f0a3f0, 0x7f027ef0, 0x017bfdf8, 0x0079017a, 
+    0xe4892612, 0x34f533f5, 0x902235f5, 0x24e04204, 0x144160e3, 0x00807460, 0xe0490490, 0x5e020360, 
+    0x00049098, 0xe0a3fee0, 0xc3ce0278, 0xd813ce13, 0x6ce030f9, 0xe0880490, 0x131313ff, 0xe0201f54, 
+    0xc86c1229, 0x047f107d, 0x12946812, 0x04900e71, 0xf01d7442, 0xef747412, 0x027f0370, 0x7f017d22, 
+    0xdb181205, 0xe04d0490, 0x0490e160, 0x13ffe088, 0x1f541313, 0x1229e020, 0x107dc86c, 0x6812057f, 
+    0x0e711294, 0x74420490, 0x7412f01e, 0x0370ef74, 0x7d22027f, 0x12047f01, 0x0490db18, 0xe160e04d, 
+    0x420490e4, 0x8f22fff0, 0x120a7f1c, 0x1ce5b374, 0xa2e0252f, 0x75ff13e7, 0xa67540a5, 0x8fa775ff, 
+    0xef049a75, 0xe412e730, 0xa675a5f5, 0xfba775ff, 0xef049a75, 0x80ff04f4, 0x04a5750c, 0x75ffa675, 
+    0x9a75fba7, 0x44049004, 0x752860e0, 0xa67501a4, 0xffa77580, 0xe4049a75, 0x64efc3fe, 0x64eef880, 
+    0x3c509880, 0x7502a575, 0xa775ffa6, 0x049a75fd, 0xefe6800e, 0x7f54edfd, 0x0874a4f5, 0xa675a5f5, 
+    0xf7a77580, 0x75049a75, 0xa67502a5, 0xfda775ff, 0xe4049a75, 0xa675a5f5, 0xf7a775ff, 0x22049a75, 
+    0xe025ef22, 0xa5f5e025, 0x75ffa675, 0x9a7583a7, 0xa5f5e414, 0x75ffa675, 0x9a757fa7, 0xa5f5e421, 
+    0x75ffa675, 0x9a757fa7, 0xa5f5e423, 0x75ffa675, 0x9a757fa7, 0xa5f5e425, 0x75ffa675, 0x9a757fa7, 
+    0xa5f5e427, 0x75ffa675, 0x9a757fa7, 0x88049029, 0x0ce020e0, 0x7580a575, 0xa775ffa6, 0x219a757f, 
+    0xe0880490, 0xe02013c3, 0x80a5750c, 0x75ffa675, 0x9a757fa7, 0x88049023, 0x541313e0, 0x0ce0203f, 
+    0x7580a575, 0xa775ffa6, 0x259a757f, 0x7540a475, 0xa775bfa6, 0x109a75ff, 0x8e168f22, 0x8c148d15, 
+    0xfeffe413, 0x16abfcfd, 0x14a915aa, 0x12c313a8, 0x02701826, 0x7fe422ff, 0xfcfdfe01, 0x15aa16ab, 
+    0x13a814a9, 0x182612c3, 0xe07f0370, 0x17f5e422, 0x16f516e5, 0x15f515e5, 0x14f514e5, 0x7f5413e5, 
+    0x16af13f5, 0x14ad15ae, 0x017813ac, 0x8f3c2612, 0x8d158e16, 0x05138c14, 0xfeffe417, 0x5413e5fd, 
+    0xfbe4fc80, 0xc3f8f9fa, 0x60182612, 0xfeffe4d5, 0x5413e5fd, 0x1778fc70, 0xe5292612, 0x20f07517, 
+    0xae812512, 0x1f74c3f0, 0x22ff2f9e, 0x0490148f, 0x01b4e049, 0x80347f04, 0x12387f02, 0x007c8074, 
+    0xff1425ef, 0x04903eec, 0xefa3f01c, 0x570490f0, 0x9533fee0, 0x260490e0, 0xf0cea3f0, 0x1c0490ff, 
+    0xe0a3fce0, 0x4e0490fd, 0x0490fbe0, 0x20f5e01e, 0x21f5e0a3, 0x7522f5e4, 0x51121f23, 0x570490b7, 
+    0x0490f0ef, 0x90e0a326, 0x90f04e04, 0x90e06204, 0x90f04d04, 0xffe01c04, 0xcfa3e0a3, 0xf0efa3f0, 
+    0xe0570490, 0x546f12ff, 0xe0600490, 0x04900760, 0xf0017482, 0x0490e422, 0x9022f082, 0xffe04904, 
+    0x01b41960, 0x00049013, 0xe0a3fee0, 0xc3ce0278, 0xd813ce13, 0x03e020f9, 0x9022007f, 0x24e04004, 
+    0x803860f1, 0x87049000, 0x13c4ffe0, 0xe0200754, 0xc86c123e, 0x5a12ffe4, 0x12097fd2, 0xa475ba6f, 
+    0xdfa67520, 0x75ffa775, 0x7412309a, 0x5704900a, 0x7112f0ef, 0x4004900e, 0x12f00f74, 0x70ef7474, 
+    0x22027f03, 0x60123c7f, 0x4d049064, 0x90e360e0, 0x32744004, 0x22007ff0, 0xe0400490, 0x3960f424, 
+    0x6c120080, 0x460490c8, 0x4f0490e0, 0x0a7412f0, 0xef500490, 0x12ffe4f0, 0xffe4d25a, 0x75546f12, 
+    0xa67501a4, 0xffa775fe, 0x7f039a75, 0x876f1209, 0x900e7112, 0x0c744004, 0x747412f0, 0x7f0370ef, 
+    0x4e122202, 0x4d049021, 0x900970e0, 0xc3e04b04, 0xdc402094, 0x75a4f5e4, 0xa775fea6, 0x039a75ff, 
+    0xe04f0490, 0xd25a12ff, 0xe0500490, 0x546f12ff, 0xe422007f, 0x16f515f5, 0x188f178e, 0xe05c0090, 
+    0xb47012ff, 0xe0560490, 0x45509fc3, 0xe06c0490, 0x948064ff, 0x80024080, 0x6c049007, 0xff04f4e0, 
+    0x8064efc3, 0x29508194, 0x18af17ae, 0xce0278ef, 0x13ce13c3, 0x0354f9d8, 0x15600264, 0x16af15ae, 
+    0x8ef354ef, 0xf5084415, 0x6c049016, 0x80f014e0, 0x6a049006, 0x90f00174, 0x64e06a04, 0xaf076001, 
+    0x1215ae16, 0x04908072, 0x22ffe06a, 0x807f007e, 0x017b007d, 0x0079047a, 0x7e892612, 0x7d207f00, 
+    0x7a017b00, 0x12807904, 0x90e48926, 0xa3f00004, 0x3c0490f0, 0xe4f00274, 0x0490f0a3, 0x0490f00b, 
+    0x0490f00a, 0xf0a3f00c, 0x0490f0a3, 0x0490f010, 0x0490f00f, 0xf0a3f012, 0xf0110490, 0xf0480490, 
+    0xf0040490, 0xf0030490, 0xf0060490, 0xf0a3f0a3, 0x0490f0a3, 0xf0027405, 0x14020490, 0x0490e4f0, 
+    0x5502f07f, 0x06e09007, 0x8fe4ffe0, 0xf518f519, 0xa316f517, 0xfce4ffe0, 0x0878fefd, 0xe53c2612, 
+    0x19f54f19, 0xf54e18e5, 0x4d17e518, 0x16e517f5, 0xa316f54c, 0xfce4ffe0, 0x1078fefd, 0xe53c2612, 
+    0x19f54f19, 0xf54e18e5, 0x4d17e518, 0x16e517f5, 0xa316f54c, 0xfce4ffe0, 0x1878fefd, 0xe53c2612, 
+    0x19f54f19, 0xf54e18e5, 0x4d17e518, 0x16e517f5, 0xaf16f54c, 0xad18ae19, 0x9022fc17, 0xb4e04904, 
+    0x347f0401, 0x387f0280, 0x90807412, 0xf0ee1c04, 0x90f0efa3, 0xffe05604, 0xe4220490, 0xf0efa3f0, 
+    0xe01c0490, 0xfde0a3fc, 0xe04e0490, 0x1e0490fb, 0xa320f5e0, 0xa321f5e0, 0x22f5e0a3, 0x752d2375, 
+    0x51120124, 0x560490ba, 0x0490f0ef, 0x90e0a322, 0x90f04e04, 0x90e06204, 0x90f04d04, 0xffe01c04, 
+    0xcfa3e0a3, 0xf0efa3f0, 0xe0560490, 0xbb7402ff, 0x4d0490e4, 0x530490f0, 0x620490f0, 0x1c0490f0, 
+    0xa3f0a3f0, 0xeff0a3f0, 0x12750970, 0x7504900f, 0xbf1080f0, 0x12750a01, 0x0490e4f0, 0x0380f076, 
+    0xbf12f5e4, 0x13750502, 0xbf0e80f0, 0x13750503, 0x9006800f, 0xf5e04604, 0x0264ef13, 0x03bf0360, 
+    0x4f049008, 0x80f013e5, 0x4f049006, 0xe4f012e5, 0xf0510490, 0xe04f0490, 0x12aff0a3, 0xaf546f12, 
+    0xd25a0213, 0xfbfcfde4, 0xe0500090, 0xe0a313c3, 0xc31f5413, 0x94e40594, 0x7d055000, 0x0b047c04, 
+    0xf50154eb, 0xfea675a4, 0x75ffa775, 0x54ecb09a, 0x2513c302, 0xff0254e0, 0x130454ec, 0x253f5413, 
+    0x54e025e0, 0xecff4f04, 0xff4f0154, 0x130454ed, 0xc43f5413, 0x4f205433, 0x0254edff, 0x54c413c3, 
+    0xedff4f10, 0x33330154, 0x4f085433, 0xa675a4f5, 0xffa775c0, 0x22b39a75, 0x1215f5e4, 0x33ef0a74, 
+    0x13f5e095, 0x64c3148f, 0x50809480, 0x95e4c30e, 0xe414f514, 0x13f51395, 0x7f011575, 0xb3741240, 
+    0x130f54ef, 0x1f541313, 0x14e51260, 0xe5ffe025, 0x74fe3313, 0x82f52f2d, 0x10807774, 0xe02514e5, 
+    0x3313e5ff, 0x2fed74fe, 0x767482f5, 0xe483f53e, 0x7416f593, 0x17f59301, 0x0a6015e5, 0x1795e4c3, 
+    0x1695e4ff, 0x16ae22fe, 0x7f2217af, 0xb3741242, 0xff0754ef, 0xf0590490, 0xe4220490, 0xf0efa3f0, 
+    0xe0590490, 0x240490ff, 0xe0a3fce0, 0x5b0490fd, 0x90fbfee0, 0xf5e02c04, 0xf5e0a320, 0x22f5e421, 
+    0x75072375, 0x5112ff24, 0x590490ba, 0x0490f0ef, 0x90e0a322, 0x90f05b04, 0x90e06204, 0x90f05d04, 
+    0xffe02404, 0x0490e0a3, 0xa3f0cf2c, 0x0490f0ef, 0xa4f5e059, 0x75f8a675, 0x9a75ffa7, 0x04902242, 
+    0xe924e040, 0x60143b60, 0x90008052, 0x70e04904, 0x00049053, 0xe0a3fee0, 0xc3ce0278, 0xd813ce13, 
+    0x40e030f9, 0xe05f0490, 0x097f2070, 0x90ce6d12, 0x01745f04, 0x400490f0, 0x90f01774, 0xff748304, 
+    0x747412f0, 0x7f0370ef, 0x097f2202, 0x90395f12, 0x18744004, 0x830490f0, 0x12f0ff74, 0x70ef7474, 
+    0x22027f03, 0x74400490, 0x007ff019, 0x49049022, 0x800270e0, 0x2404904c, 0x0470f4e0, 0xef64e0a3, 
+    0xc17f1270, 0x7f5f6a12, 0x5f6a1201, 0x7504a575, 0x1c80ffa6, 0xe0240490, 0xe0a30470, 0x15700f64, 
+    0x6a12c17f, 0x12017f5f, 0xa5755f6a, 0xffa67508, 0x80329a75, 0x02a57518, 0x75ffa675, 0x9a75fda7, 
+    0x02a57504, 0x75ffa675, 0x9a75fda7, 0x25049004, 0x70f004e0, 0x24049006, 0x22f004e0, 0x1e8a1d8b, 
+    0xda7f1f89, 0xee807412, 0xe4fe7f54, 0x228e238f, 0x20f521f5, 0x20ac21ad, 0x26120f78, 0xaa1dab29, 
+    0xef1fa91e, 0x7fde2512, 0x807412db, 0xc0fdfce4, 0xc005c004, 0xaf07c006, 0xad22ae23, 0x7820ac21, 
+    0x3c261210, 0x02d003d0, 0x00d001d0, 0x23f54bef, 0x22f54aee, 0x21f549ed, 0x20f548ec, 0xe5ff23e5, 
+    0x21e5fe22, 0x5420e5fd, 0xef22fc7f, 0x1c60fe24, 0x142a6014, 0x60143a60, 0x7004244b, 0x88049057, 
+    0x20007fe0, 0x017f02e0, 0x488007ae, 0xe0880490, 0x007f13c3, 0x7f02e020, 0x8007ae01, 0x88049037, 
+    0x541313e0, 0x20007f3f, 0x017f02e0, 0x248007ae, 0xe0880490, 0x54131313, 0x20007f1f, 0x017f02e0, 
+    0x108007ae, 0xe0880490, 0x7f0f54c4, 0x02e02000, 0x07ae017f, 0x902206af, 0x30e01704, 0xe1203fe2, 
+    0x79049032, 0x7412ffe0, 0x9533efc1, 0x3f54efe0, 0xa675a4f5, 0xffa775c0, 0x90439a75, 0xffe07804, 
+    0xefc17412, 0xa4f53f54, 0x75c0a675, 0x9a75ffa7, 0x901a8044, 0xffe04504, 0x809f5e12, 0x4f049010, 
+    0x6f12ffe0, 0x46049054, 0x5a12ffe0, 0x170490d2, 0x0de330e0, 0x7508a475, 0xa775f7a6, 0x409a75ff, 
+    0xffe42222, 0x160490fe, 0x0490fde0, 0xc3fce077, 0xec05409d, 0x0b80fd9d, 0xe0160490, 0xff74c3fd, 
+    0x90fd2c9d, 0x70e02404, 0x64e0a304, 0x43037063, 0x04908006, 0xc3fce077, 0x0440ff94, 0x0380007c, 
+    0x90fc04ec, 0xb5e01604, 0x06430304, 0x16049040, 0x0490fbe0, 0x03b5e077, 0x20064303, 0x4febfbed, 
+    0x140490ff, 0xefa3f0ee, 0x2204aff0, 0xfce407ad, 0x8064edd3, 0x1b408094, 0x75a4f5ec, 0xa775c0a6, 
+    0x459a75ff, 0xf53f54ec, 0xc0a675a4, 0x75ffa775, 0xc322469a, 0x948064ed, 0xec1d5080, 0xa4f53f54, 
+    0x75c0a675, 0x9a75ffa7, 0x3f54ec47, 0xa675a4f5, 0xffa775c0, 0x22489a75, 0xf53f54ec, 0xc0a675a4, 
+    0x75ffa775, 0x54ec439a, 0x75a4f53f, 0xa775c0a6, 0x449a75ff, 0x50049022, 0x067dffe0, 0x60fe24ef, 
+    0x12601411, 0x14136014, 0x04241460, 0x087c1470, 0x107c1280, 0x207c0e80, 0x407c0a80, 0x807c0680, 
+    0xfce40280, 0xed327212, 0xa4f51f54, 0x75e0a675, 0x9a75ffa7, 0x20a47515, 0x75a5f5e4, 0xa775d3a6, 
+    0x309a758b, 0x7520a475, 0x9a7520a5, 0xa5f5ec31, 0x75ffa675, 0x7422329a, 0xf518f5ff, 0x120e7f19, 
+    0x1a8e8074, 0xf5e41b8f, 0xf51df51c, 0xc317f516, 0x1b9517e5, 0x1a9516e5, 0x18e53950, 0x251de5ff, 
+    0xe582f517, 0xf516351c, 0x6f93e483, 0xfe19e5fd, 0xed02f075, 0xf5c324a4, 0x34f0e582, 0xe483f574, 
+    0x18f56e93, 0xf5930174, 0xe5170519, 0x05c07017, 0xaebc8016, 0x2219af18, 0x2aac29ae, 0x2caa2bab, 
+    0xae0470ed, 0xbf29ac2a, 0xc3ee1801, 0x03500794, 0xec29800e, 0x400094d3, 0xc3eb1c01, 0x0b1d509a, 
+    0xffbf1a80, 0x94d3ee17, 0x1e034000, 0xc3ec0e80, 0x01500794, 0x94d3eb0c, 0x1b014000, 0x70ed318b, 
+    0x8c308e06, 0x8e04802f, 0x85308c2f, 0x28852d27, 0x7a007b2e, 0x222d7900, 0x900a7412, 0xf0ef4f04, 
+    0x6f121f7f, 0x24049054, 0xa3f0ff74, 0x90f0e174, 0x70e04904, 0x12e07f09, 0x017f5f6a, 0x027f0280, 
+    0xe45f6a12, 0xf0260490, 0x0490f0a3, 0x0490f077, 0x1f7ff016, 0x907f6e12, 0xd3e04904, 0x09400094, 
+    0x7502a575, 0x9a75ffa6, 0x0490e432, 0xf0a3f014, 0x7507ad22, 0xedd301a4, 0x80948064, 0x017f0440, 
+    0x007f0280, 0x25e025ef, 0x440454e0, 0xf5eefe40, 0x80a675a5, 0x758ba775, 0xffe4049a, 0x8064edd3, 
+    0x04408094, 0x048005ae, 0xfe04f4ed, 0x8064eec3, 0x8064eff8, 0x750f5098, 0xa67502a5, 0xfda775ff, 
+    0x0f049a75, 0xad22d680, 0x01a47507, 0x8064edd3, 0x04408094, 0x0280017f, 0x25ef007f, 0x54e025e0, 
+    0xfe204404, 0x75a5f5ee, 0xa77580a6, 0x049a758b, 0xedd3ffe4, 0x80948064, 0x05ae0440, 0xf4ed0480, 
+    0xeec3fe04, 0xeff88064, 0x50988064, 0x02a5750f, 0x75ffa675, 0x9a75fda7, 0xd6800f04, 0xed07ad22, 
+    0x500d94d3, 0xfa24ed21, 0x7e0174ff, 0x0807a800, 0x33c30580, 0xd8ce33ce, 0x75a5f5f9, 0x9a75ffa6, 
+    0x04a47532, 0x24ed1f80, 0x0174fff2, 0x07a8007e, 0xc3058008, 0xce33ce33, 0xa5f5f9d8, 0x75ffa675, 
+    0xa475329a, 0xf3a67508, 0x75ffa775, 0x9022309a, 0x24e04004, 0x803260f6, 0x87049000, 0x13c3ffe0, 
+    0xe438e020, 0xa675a4f5, 0xffa77580, 0x90499a75, 0xd3e04904, 0x23500194, 0x7fc86c12, 0x63711210, 
+    0x900e7112, 0x0a744004, 0x747412f0, 0x7f0370ef, 0x56122202, 0x4d049099, 0x7fe560e0, 0xf5e42200, 
+    0x1237f536, 0xf47f6874, 0xefae7412, 0x131313c4, 0xf2600154, 0x7412fa7f, 0x54c4efae, 0x1208f50f, 
+    0xf5e4635d, 0xc338e538, 0x0a500895, 0x12b13885, 0x38056462, 0xf5e4ef80, 0xb1388538, 0x05060012, 
+    0xb538e538, 0xf5e4f308, 0x8fee8038, 0x8d148e15, 0x90128c13, 0x047400e0, 0x02e090f0, 0x0878f0ef, 
+    0xa3292612, 0x15aff0ef, 0x13ad14ae, 0x107812ac, 0xa3292612, 0x15aff0ef, 0x13ad14ae, 0x187812ac, 
+    0xa3292612, 0xe090f0ef, 0xf0057400, 0xe000e090, 0x22f9e020, 0xe0400490, 0x2660f224, 0x04900080, 
+    0xc3ffe087, 0x2ce02013, 0xe0490490, 0x500194d3, 0xc86c1223, 0x7112107f, 0x0e711263, 0x74400490, 
+    0x7412f00e, 0x0370ef74, 0x1222027f, 0x04909956, 0xe560e04d, 0x74400490, 0x007ff02f, 0x60049022, 
+    0x007afbe0, 0x828f007e, 0x05af838e, 0xa802aeeb, 0x05800807, 0x33ce33c3, 0xfff9d8ce, 0xfe8355ee, 
+    0xff8255ef, 0xfdf482e5, 0xfcf483e5, 0xe02e0490, 0xe0a3fc5c, 0x4eecfd5d, 0xff4fedfe, 0xee2e0490, 
+    0xf0efa3f0, 0x7f049022, 0x13c3ffe0, 0x7f03e030, 0x04902200, 0xf324e040, 0x00800b60, 0x90206f12, 
+    0x0d744004, 0x747412f0, 0x7f0370ef, 0x73122202, 0x1660ef36, 0x7501a475, 0xa775fea6, 0x199a75ff, 
+    0x177f017d, 0x7fb93112, 0x007f2201, 0x24681222, 0x1c0490e4, 0xa3f0a3f0, 0x90f0a3f0, 0x90f04b04, 
+    0xa3f04d04, 0xa3f0a3f0, 0x90f0a3f0, 0xa3f05304, 0x7b0490f0, 0x600164e0, 0x0490e40d, 0xf0a3f020, 
+    0xf0240490, 0x90e4f0a3, 0xa3f02204, 0x260490f0, 0x22f0a3f0, 0xe4cb7212, 0x2a8e2b8f, 0x28f529f5, 
+    0xe0600090, 0x5411e030, 0x0090f0fe, 0xf004e067, 0x00900670, 0xf004e066, 0xe0660090, 0xffe0a3fe, 
+    0x78fdfce4, 0x3c261210, 0xff2b45ef, 0xfe2a45ee, 0xfd2945ed, 0xfc2845ec, 0x8e828f22, 0xeb05af83, 
+    0x07a802ae, 0xc3058008, 0xce33ce33, 0xeefff9d8, 0xeffe8355, 0xe5ff8255, 0xe5fdf482, 0x90fcf483, 
+    0x5ce03004, 0x5de0a3fc, 0xfe4eecfd, 0x90ff4fed, 0xf0ee3004, 0x22f0efa3, 0x7412887f, 0x0f64ef80, 
+    0x751a704e, 0xa67502a4, 0xffa775fd, 0x759ef5e4, 0x0490969c, 0xa3f0e000, 0xf00444e0, 0xa4f5e422, 
+    0x75fda675, 0x9ef5ffa7, 0x90969c75, 0xf0e00004, 0xfb54e0a3, 0x25ef22f0, 0xf5e025e0, 0xffa675a5, 
+    0x7583a775, 0xf5e4149a, 0xffa675a5, 0x757fa775, 0x0490219a, 0xe020e088, 0x80a57519, 0x75ffa675, 
+    0x9a757fa7, 0x40a47521, 0x75bfa675, 0x9a75ffa7, 0x7f222210, 0xae74123b, 0xff0754ef, 0x06c0007e, 
+    0x3b7f07c0, 0xefae7412, 0x13133f54, 0xfd1f5413, 0xff2de0d0, 0x0034e0d0, 0x13ef13c3, 0x7f07c0ff, 
+    0xb374123b, 0xfe3f54ef, 0xff2ee0d0, 0x0f049022, 0x131313e0, 0x94d31f54, 0xa3294001, 0x131313e0, 
+    0x94d31f54, 0x901d4001, 0x13e00d04, 0x1f541313, 0x400194d3, 0x13e0a30f, 0x1f541313, 0x400194d3, 
+    0x22007f03, 0x1222017f, 0x54ef3272, 0x75a4f51f, 0xa775e0a6, 0x159a75ff, 0x75a4f5e4, 0xa67530a5, 
+    0x8fa775f3, 0x75309a75, 0xa67504a5, 0x329a75ff, 0x7503a475, 0xa775fca6, 0x339a75ff, 0x56049022, 
+    0x7412ffe0, 0x570490bb, 0x6f12ffe0, 0x0490e454, 0xe0a3f044, 0x9f5e12ff, 0xe0460490, 0xd25a12ff, 
+    0x7520a475, 0xa775dfa6, 0x109a75ff, 0x74440490, 0x1222f001, 0x1c8f0c6d, 0x1a8d1b8e, 0x1baa198c, 
+    0x04901cab, 0xa3f0ea36, 0x1078f0eb, 0x90292612, 0xf0ee3404, 0x90f0efa3, 0xf0ea2204, 0x90f0eba3, 
+    0xf0ee2004, 0x22f0efa3, 0x7502a575, 0xa775ffa6, 0x019a75f8, 0x7412067f, 0x0154efae, 0x721213f5, 
+    0x10a47532, 0x75e0a675, 0x9a75ffa7, 0x80a57515, 0x75ffa675, 0x9a757fa7, 0x0e710230, 0xffed07ad, 
+    0xfee09533, 0xc30378ef, 0xce33ce33, 0xa4f5f9d8, 0x440154ee, 0x75a5f51a, 0x9a75c0a7, 0x80a5752b, 
+    0x75ffa675, 0x9a757fa7, 0x5704902b, 0x1222f0ed, 0x54ef3272, 0x75a4f51f, 0xa775e0a6, 0x159a75ff, 
+    0x7520a475, 0xa675a0a5, 0x0fa775d3, 0x75309a75, 0xa57520a4, 0x319a7520, 0x7504a575, 0x9a75ffa6, 
+    0x72122232, 0x1f54ef32, 0xa675a4f5, 0xffa775e0, 0x75159a75, 0xa5750ca4, 0xf3a67530, 0x758fa775, 
+    0xa475309a, 0x20a57520, 0x75319a75, 0xa67504a5, 0x329a75ff, 0x32721222, 0xf51f54ef, 0xe0a675a4, 
+    0x75ffa775, 0xf5e4159a, 0x24a575a4, 0x75f3a675, 0x9a758ba7, 0x60a47530, 0x7520a575, 0xa575319a, 
+    0xffa67538, 0x22329a75, 0xef327212, 0xa4f51f54, 0x75e0a675, 0x9a75ffa7, 0x0ca47515, 0x7530a575, 
+    0xa775f3a6, 0x309a758f, 0x7560a475, 0x9a7560a5, 0x04a57531, 0x75ffa675, 0x1222329a, 0x54ef3272, 
+    0x75a4f51f, 0xa775e0a6, 0x159a75ff, 0x750ca475, 0xa67530a5, 0x8fa775f3, 0x75309a75, 0xa57560a4, 
+    0x319a7520, 0x7504a575, 0x9a75ffa6, 0x67122232, 0x3272124f, 0x75a4f5e4, 0xa775cfa6, 0x119a75ff, 
+    0x75a5f5e4, 0xa775ffa6, 0xd19a75fb, 0x170490e4, 0x160490f0, 0x140490f0, 0x22f0a3f0, 0x049007ad, 
+    0x54c4e07f, 0x13e0200f, 0xe0500090, 0xe0a313c3, 0xd31f5413, 0x94e41694, 0xed074000, 0x93827790, 
+    0x90ed22ff, 0xff936d77, 0x9007ad22, 0xc4e07f04, 0xe0200f54, 0x50009013, 0xa313c3e0, 0x1f5413e0, 
+    0xe41694d3, 0x07400094, 0xac7790ed, 0xed22ff93, 0x93977790, 0xf5e422ff, 0xffa675a5, 0x757fa775, 
+    0xa575309a, 0xffa67580, 0x757fa775, 0xa475309a, 0x7fa67580, 0x75ffa775, 0x0490109a, 0xf0ff7483, 
+    0x32721222, 0xf51f54ef, 0xe0a675a4, 0x75ffa775, 0xa475159a, 0xb0a5750c, 0x75f3a675, 0x9a750fa7, 
+    0x04a57530, 0x75ffa675, 0x1222329a, 0x54ef3272, 0x75a4f51f, 0xa775e0a6, 0x159a75ff, 0x750ca475, 
+    0xa675a0a5, 0x0fa775f3, 0x75309a75, 0xa67504a5, 0x329a75ff, 0x32721222, 0xf51f54ef, 0xe0a675a4, 
+    0x75ffa775, 0xf5e4159a, 0x90a575a4, 0x75f3a675, 0x9a750fa7, 0x04a57530, 0x75ffa675, 0x1222329a, 
+    0x54ef3272, 0x75a4f51f, 0xa775e0a6, 0x159a75ff, 0x7580a575, 0xa775ffa6, 0x309a757f, 0x7580a475, 
+    0xa7757fa6, 0x109a75ff, 0xc02f1222, 0xe4075512, 0x12017ffd, 0xfde4a52b, 0x2b12027f, 0x7ffde4a5, 
+    0xa52b1203, 0x047ffde4, 0xe4a52b12, 0x02057ffd, 0xa475a52b, 0xe0a67506, 0x75ffa775, 0xa475d09a, 
+    0xefa67510, 0x75ffa775, 0xa475409a, 0x03a67550, 0x75ffa775, 0x9c75d19e, 0xf5e42218, 0x75a5f5a4, 
+    0xa77503a6, 0x309a7501, 0xf5a4f5e4, 0x319a75a5, 0xf5a4f5e4, 0x329a75a5, 0xf5a4f5e4, 0x339a75a5, 
+    0x32721222, 0xf51f54ef, 0xe0a675a4, 0x75ffa775, 0xa575159a, 0xffa67524, 0x758ba775, 0xa475309a, 
+    0x20a57560, 0x22319a75, 0x06ac07ad, 0xf5a4f5e4, 0x609a75a5, 0xeca4f5ed, 0xa5f58044, 0xaf609a75, 
+    0x027ded05, 0x7dba3d12, 0x020a7f02, 0x0490b931, 0x01b4e04c, 0x0804900d, 0x870490e0, 0x090490f0, 
+    0x04900b80, 0x0490e006, 0x0490f087, 0x0490e007, 0x8522f088, 0xcbaf2cbf, 0xcaadfeef, 0xc306aced, 
+    0x95ec3795, 0x90075036, 0x44e06000, 0x368cf001, 0x04ae378d, 0x7f2205af, 0xae7412a9, 0xff0f54ef, 
+    0x400394c3, 0x94d3ef06, 0x9008400d, 0x44e06000, 0x9022f010, 0x54e06000, 0xad22f0ef, 0xf075ed07, 
+    0xf0aea408, 0x54eea4f5, 0x75a5f501, 0x9a75c0a7, 0x80a5752b, 0x75ffa675, 0x9a757fa7, 0x067f222b, 
+    0xefae7412, 0x13f50154, 0x7412057f, 0x6013e580, 0x64eec30b, 0x50809480, 0xff137503, 0x122213af, 
+    0x208f0c6d, 0x1e8d1f8e, 0x04901d8c, 0xa3f0ee22, 0x1078f0ef, 0x90292612, 0xf0ee2004, 0x22f0efa3, 
+    0xad923312, 0xed06ac07, 0xecfbe025, 0x78edfa33, 0xce33c302, 0xf9d8ce33, 0x3aeeff2b, 0x1f7f22fe, 
+    0x757f6e12, 0xa67510a4, 0xffa775cf, 0x75119a75, 0xa67504a5, 0xfba775ff, 0x22d19a75, 0x06aa07ab, 
+    0xebfe5cea, 0xffe0255d, 0xc3fe33ee, 0xeaff9feb, 0x9022fe9e, 0x047400e0, 0x90f004f0, 0x20e000e0, 
+    0xe090f9e0, 0xf0067400, 0x0a741222, 0xef4f0490, 0x0490e4f0, 0x0490f077, 0x1c7ff016, 0xef397102, 
+    0x333333c4, 0xa4f58054, 0x757fa675, 0x9a75ffa7, 0x3a7f2290, 0xee807412, 0x7dfe3f54, 0x12207c00, 
+    0xffeeb473, 0x64eec322, 0x50809480, 0xfff4ef08, 0x80fef4ee, 0x07ad2200, 0xedc0a475, 0xa5f5eefe, 
+    0x753fa675, 0xaf220d9a, 0xe507adbc, 0xfc0354bd, 0x05af04ae, 0x7507ad22, 0xfeed80a4, 0x75a5f5ee, 
+    0x8f220d9a, 0xad9d8d9e, 0xefaaafa9, 0x22ffedfe, 0xc9d2c8d2, 0xf5e4cbd2, 0x22cad2bf, 0xe0830490, 
+    0x07b4007f, 0x22017f02, 0xa9ad9b8f, 0xfeefaaaf, 0x7f22ffed, 0xb374123a, 0xff3f54ef, 0x80a47522, 
+    0x75a5f5e4, 0x90220d9a, 0x54e001e0, 0x8f22ff01, 0xaf9d8d9e, 0x9b8f22a9, 0x8f22aaaf, 0x22a9af9b, 
+    0x0222007f, 0x22221373, 0x00222222, 0x20211000, 0x40633042, 0x60a55084, 0x81e770c6, 0xa1299108, 
+    0xc16bb14a, 0xe1add18c, 0x12eff1ce, 0x32100231, 0x52522273, 0x729442b5, 0x93d662f7, 0xb3188339, 
+    0xd35aa37b, 0xf39cc3bd, 0x24dee3ff, 0x04433462, 0x64011420, 0x44c774e6, 0xa58554a4, 0x854bb56a, 
+    0xe5099528, 0xc5cff5ee, 0x368dd5ac, 0x16722653, 0x76300611, 0x56f666d7, 0xb7b44695, 0x977aa75b, 
+    0xf7388719, 0xd7fee7df, 0x48bcc79d, 0x68e558c4, 0x08a77886, 0x28611840, 0xc9233802, 0xe9edd9cc, 
+    0x89aff98e, 0xa9699948, 0x5a2bb90a, 0x7ad44af5, 0x1a966ab7, 0x3a500a71, 0xdb122a33, 0xfbdccbfd, 
+    0x9b9eebbf, 0xbb588b79, 0x6c1aab3b, 0x4c877ca6, 0x2cc55ce4, 0x0c033c22, 0xed411c60, 0xcd8ffdae, 
+    0xadcdddec, 0x8d0bbd2a, 0x7e499d68, 0x5eb66e97, 0x3ef44ed5, 0x1e322e13, 0xff700e51, 0xdfbeef9f, 
+    0xbffccfdd, 0x9f3aaf1b, 0x91788f59, 0xb1a98188, 0xd1eba1ca, 0xf12dc10c, 0x106fe14e, 0x30a10080, 
+    0x50e320c2, 0x70254004, 0x83676046, 0xa39893b9, 0xc3dab3fb, 0xe31cd33d, 0x025ef37f, 0x229012b1, 
+    0x42d232f3, 0x62145235, 0xb5567277, 0x95cba5ea, 0xf58985a8, 0xd54fe56e, 0x340dc52c, 0x14c324e2, 
+    0x748104a0, 0x54476466, 0xa7054424, 0x87fab7db, 0xe7b89799, 0xc77ef75f, 0x263cd71d, 0x06f236d3, 
+    0x66b01691, 0x46767657, 0xd9345615, 0xf96dc94c, 0x992fe90e, 0xb9e989c8, 0x58aba98a, 0x78654844, 
+    0x18276806, 0x38e108c0, 0xcba32882, 0xeb5cdb7d, 0x8b1efb3f, 0xabd89bf9, 0x4a9abbbb, 0x6a545a75, 
+    0x0a167a37, 0x2ad01af1, 0xfd923ab3, 0xdd0fed2e, 0xbd4dcd6c, 0x9d8badaa, 0x7cc98de8, 0x5c076c26, 
+    0x3c454c64, 0x1c832ca2, 0xefc10ce0, 0xcf3eff1f, 0xaf7cdf5d, 0x8fbabf9b, 0x6ef89fd9, 0x4e367e17, 
+    0x2e745e55, 0x0eb23e93, 0x1cf01ed1, 0x1b181ca0, 0x1a181b98, 0x19101a90, 0x18081988, 0x17001880, 
+    0x16f81680, 0x15f01578, 0x14e81470, 0x13e81368, 0x12e01260, 0x00000058, 0x00130009, 0x0026001c, 
+    0x0038002f, 0x004b0042, 0x005e0054, 0x00710067, 0x0083007a, 0x0096008d, 0x00a9009f, 0x00bc00b2, 
+    0x00ce00c5, 0x01f400e1, 0x01190107, 0x013f012c, 0x01640152, 0x00000077, 0x001f0010, 0x003f002f, 
+    0x005e004e, 0x007d006d, 0x009c008d, 0x00bc00ac, 0x00db00cb, 0x01fa00ea, 0x0119010a, 0x01390129, 
+    0x01580148, 0x01960177, 0x01d501b6, 0x021302f4, 0x02520233, 0x1b1a1a71, 0x1e1d1c1b, 0x2221201f, 
+    0x26252423, 0x29292827, 0x16152a2a, 0x18171716, 0x1a191918, 0x1c1c1b1a, 0x1e1e1d1d, 0x22201f1f, 
+    0x26252423, 0x28272726, 0x2a292928, 0x2c2b2b2a, 0x2f2e2d2c, 0x23232221, 0x26262524, 0x29282827, 
+    0x2c2b2a2a, 0x2f2e2d2d, 0x0000002f, 0x00000000, 0x99145ba6
+};
diff --git a/drivers/net/bcmbca/phy/orca_b0_firmware.h b/drivers/net/bcmbca/phy/orca_b0_firmware.h
new file mode 100644
index 0000000000..ed835d0b4e
--- /dev/null
+++ b/drivers/net/bcmbca/phy/orca_b0_firmware.h
@@ -0,0 +1,7076 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: April 2017
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Firmware for external 2.5G/5G/10G phys: Orca BCM84880, BCM84881, BCM84884, BCM84888
+ */
+
+char orca_b0_version[] = "Orca B0 v02-03-05-2019-12-03";
+
+uint32_t orca_b0_firmware[] = {
+    0xea000016, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe59ff018, 0xe320f000, 0xe59ff018, 0xe59ff018, 
+    0x000001d4, 0x0002c0bc, 0x0002c01c, 0x0002b368, 0x0002ac90, 0x00000000, 0x0002b014, 0x0002adf4, 
+    0x0002fa10, 0xc0de512e, 0x00000000, 0x00000000, 0x000077c8, 0x000371d8, 0x00005103, 0x00000000, 
+    0xe59f0148, 0xe5901000, 0xe3510000, 0x0a000004, 0xe3a01000, 0xe5801000, 0xe59f0134, 0xe5801000, 
+    0xea000006, 0xe59f012c, 0xe580e000, 0xe59f0120, 0xe5901000, 0xe2811001, 0xe5801000, 0xe25ef004, 
+    0xe59f1114, 0xe3a0011a, 0xe5810000, 0xe59f110c, 0xee091f11, 0xe59fa108, 0xe59fb108, 0xe59fc108, 
+    0xe51f0088, 0xe51f1088, 0xe1a02000, 0xe1500001, 0x1a000003, 0xee110f30, 0xe3c0040e, 0xee010f30, 
+    0xea00002c, 0xe3a01805, 0xe51f209c, 0xe2820004, 0xe8a00002, 0xe1500001, 0x3afffffc, 0xe51f00bc, 
+    0xe3500000, 0x1a000023, 0xe51f20bc, 0xe3a01000, 0xe1cc10b0, 0xe3e00000, 0xe59f70b0, 0xe3a09008, 
+    0xe4d13001, 0xe3a08000, 0xe7e043d3, 0xe7e05fd0, 0xe0346005, 0xe1a00080, 0x0a000000, 0xe0200007, 
+    0xe1a03083, 0xe2888001, 0xe1580009, 0xbafffff5, 0xe1510002, 0xbafffff1, 0xe5912000, 0xe58a0000, 
+    0xe58b2000, 0xe3e03000, 0xe1520003, 0x0a000001, 0xe1500002, 0x1a00000a, 0xe3a02912, 0xe51f3134, 
+    0xe0821003, 0xe51f314c, 0xe8b30030, 0xe8a20030, 0xe1520001, 0x1afffffb, 0xe3a03901, 0xe1cc30b0, 
+    0xe51ff188, 0xe3a03902, 0xe1cc30b0, 0xeafffffe, 0xc300003c, 0xc3000038, 0xc300000c, 0xc2000010, 
+    0x00040021, 0x00000048, 0x0000004c, 0xd03c801a, 0x04c11db7, 0xebffffff, 0xebffffff, 0xebffffff, 
+    0xebffffff, 0xe3a01401, 0xee110f10, 0xe1800001, 0xe3c00a02, 0xee010f10, 0xee110f30, 0xe3800040, 
+    0xe3800501, 0xee010f30, 0xe59f0084, 0xe3a010d1, 0xe121f001, 0xe1a0d000, 0xe3a010d2, 0xe121f001, 
+    0xe2400080, 0xe1a0d000, 0xe3a010d7, 0xe121f001, 0xe2400c02, 0xe1a0d000, 0xe3a010db, 0xe121f001, 
+    0xe2400080, 0xe1a0d000, 0xe3a010d3, 0xe121f001, 0xe2400080, 0xe1a0d000, 0xe3a010df, 0xe121f001, 
+    0xe2400c02, 0xe1a0d000, 0xe3a010d3, 0xe121f001, 0xe59f0024, 0xe59f1018, 0xe59f2024, 0xe4802004, 
+    0xe1500001, 0xbafffffc, 0xeb000007, 0xe59fc014, 0xe12fff1c, 0x00047800, 0x00047000, 0x00040674, 
+    0x00041c74, 0xa5a5a5a5, 0x000002d4, 0xe3a00701, 0xe3a02008, 0xee191f11, 0xe2011d3e, 0xe1811000, 
+    0xe1811102, 0xe3811001, 0xee091f11, 0xf57ff04f, 0xe12fff1e, 0xfa000000, 0xfa000036, 0xe890a00a, 
+    0x44820c00, 0xf1aa4483, 0x45da0701, 0xf000d101, 0xf2aff863, 0xe8ba0e09, 0xf013000f, 0xbf180f01, 
+    0xf0431afb, 0x47180301, 0x0002e1a8, 0x0002e208, 0xf04f440a, 0xf8100c00, 0xf0133b01, 0xbf080407, 
+    0x4b01f810, 0xbf08111d, 0x5b01f810, 0xd0051e64, 0x6b01f810, 0xf8011e64, 0xd1f96b01, 0x0f08f013, 
+    0xf810bf1e, 0x1cad4b01, 0xd1091b0c, 0xbf581e6d, 0xcb01f801, 0xe005d5fa, 0x6b01f814, 0x6b01f801, 
+    0xd5f91e6d, 0xd3d64291, 0x00004770, 0xbf243a10, 0xc178c878, 0x0752d8fa, 0xc830bf24, 0xbf44c130, 
+    0x600c6804, 0x00004770, 0x24002300, 0x26002500, 0xbf283a10, 0xd8fbc178, 0xbf280752, 0xbf48c130, 
+    0x4770600b, 0xe89db51f, 0xf02a0003, 0xf02af97e, 0xbd1ff8a4, 0xbd10b510, 0xfbebf02a, 0xf7ff4611, 
+    0xf000fff1, 0xf02af8d7, 0xb403fc09, 0xfff2f7ff, 0xf02abc03, 0x0000fc37, 0xf8d1490b, 0x684ac000, 
+    0x3b04f85c, 0x44186810, 0x0b04f842, 0xbf28458c, 0x0cdcf1a1, 0xbf28428a, 0x02dcf1a1, 0xc000f8c1, 
+    0xf020604a, 0x47704000, 0x0004060c, 0x4ff8e92d, 0x0800f04f, 0x0005468a, 0x46464604, 0xd0184647, 
+    0xf02c4608, 0x4602ff49, 0x2000460b, 0x4180f04f, 0xff8ef02b, 0x9124f8df, 0x20004602, 0x4649460b, 
+    0xfd6ef02c, 0x464b2200, 0xfcaef02c, 0x91004683, 0x2000e00c, 0xe8bd4601, 0x4b408ff8, 0x22000864, 
+    0x46394630, 0xfca0f02c, 0x460f4606, 0xd8f42c01, 0x46394630, 0xfedcf02c, 0x20014601, 0xf02c4088, 
+    0x4604ff04, 0x46284689, 0xff16f02c, 0x4622464b, 0xfd46f02c, 0x9b00e035, 0x4620465a, 0xf02c4629, 
+    0xd332ff1f, 0xe0232000, 0x462b4622, 0x46194610, 0xff52f02c, 0x46042200, 0x0801f108, 0xf04f460d, 
+    0xf02d4380, 0xd811f847, 0xfa002001, 0xf02cf008, 0x4602fedc, 0x4921460b, 0xf02c2000, 0x4632fd21, 
+    0xf02c463b, 0x4606fc61, 0xe004460f, 0x0001f109, 0x46814550, 0xf04fd3d8, 0x462032ff, 0xf02d4629, 
+    0x45d0fd52, 0x460d4604, 0x4630d3c5, 0xe7a24639, 0x4606b570, 0x461d4614, 0x0104e9dd, 0xfe88f02c, 
+    0x4630b2c1, 0xff72f7ff, 0x462b4622, 0xf920f02d, 0x4b0c4a0b, 0xfcf4f02c, 0x22004b0b, 0xff0cf02c, 
+    0xf04f4b0a, 0xf02d3233, 0x4b09f83b, 0xf02c2200, 0xf02cff03, 0xb280fe6d, 0x0000bd70, 0x3ff00000, 
+    0x4ea4a8c1, 0x400a9340, 0x40340000, 0x40333333, 0x40240000, 0xbfc0f002, 0xe28fc0bf, 0xe12fff1c, 
+    0x68124af9, 0xd00b4210, 0x68104af8, 0x6f00f5b0, 0x4bf7da06, 0xf843681b, 0x68101020, 0x60101c40, 
+    0xb5104770, 0xf7ff4604, 0x2000ffeb, 0xf9d4f007, 0x46204601, 0x4010e8bd, 0xb570e7e2, 0x4605460c, 
+    0xf00948ec, 0x4621fada, 0xf7ff4628, 0x4ce9ffea, 0x68214628, 0xffd4f7ff, 0x46286861, 0xffd0f7ff, 
+    0x462868a1, 0xffccf7ff, 0x462868e1, 0x4070e8bd, 0xb570e7c6, 0x4605460c, 0xf00948df, 0x4621fb60, 
+    0xf7ff4628, 0x48ddffce, 0xf2402200, 0xf02a71ff, 0x4601fdd0, 0xf7ff4628, 0x4cd7ffb3, 0xf9b48861, 
+    0xeb000000, 0x46284101, 0xffaaf7ff, 0xf9b488e1, 0xeb000004, 0x46284101, 0x4070e8bd, 0xb570e7a0, 
+    0x48c94605, 0x42056800, 0x188cd016, 0x4621b152, 0xf7ff4628, 0x2000ff95, 0xf97ef007, 0x46284601, 
+    0xff8ef7ff, 0x880849c6, 0xf3c01c40, 0x60080009, 0x680949c4, 0x4020f841, 0x48c3bd70, 0xb5102100, 
+    0xfd6ff02a, 0x212048c0, 0xf02a3064, 0x48bffd6a, 0x22462100, 0x0400f640, 0x80428001, 0x80c18081, 
+    0x48bb4621, 0xf02b6800, 0x48b1fd53, 0x68004621, 0xfd3ef02b, 0x00a148b7, 0xe8bd6800, 0xf02b4010, 
+    0xb570bd47, 0xf240b281, 0xf3c01500, 0x2008040e, 0x52b8f04f, 0xffb3f7ff, 0xd8032cff, 0xb2e049ab, 
+    0xe0043108, 0x4f50f5b4, 0x49abd205, 0xf851b2e0, 0x47800020, 0x48a44605, 0x30644629, 0xfd31f02a, 
+    0x462148a1, 0xfd2df02a, 0xf64f489f, 0x307471ff, 0xfd27f02a, 0xf248489c, 0xe8bd0100, 0x30704070, 
+    0xbd1ff02a, 0xf2414898, 0xb5101122, 0xf02a3066, 0x4895fd18, 0x30642108, 0xfd13f02a, 0xbd102008, 
+    0xf00fb510, 0xb2c1fba3, 0x3068488f, 0xfd09f02a, 0x88014892, 0x3066488c, 0xfd03f02a, 0xbd102004, 
+    0xb5104889, 0xf02a3068, 0x498cfcf9, 0x20018008, 0xfd25f00f, 0xbd102004, 0xb5104889, 0x0000f990, 
+    0x4881b281, 0xf02a3066, 0x2004fcec, 0x487ebd10, 0x3066b510, 0xfce2f02a, 0x70084981, 0xbd102004, 
+    0xb5104880, 0x48787801, 0xf02a3066, 0x487efcda, 0x48757801, 0xf02a3068, 0x487cfcd4, 0x48727801, 
+    0xf02a306a, 0x2004fcce, 0x486fbd10, 0x3066b510, 0xfcc4f02a, 0xf0104973, 0x4c7300ff, 0xd0037008, 
+    0x30684869, 0xfcbaf02a, 0x20047020, 0x4870bd10, 0xb5104a70, 0x78127800, 0x010cf000, 0x0003f000, 
+    0xeb010209, 0x4a6c1182, 0xeb017812, 0xeb011102, 0x496a0080, 0x44087809, 0x485bb281, 0xf02a3066, 
+    0x4867fca0, 0xfc9af02a, 0x48574601, 0xf02a3068, 0x4863fc98, 0xf02a1c80, 0x4601fc91, 0x306a4852, 
+    0xfc8ff02a, 0x1d00485e, 0xfc88f02a, 0x484e4601, 0xf02a306c, 0x485bfc86, 0x01017800, 0x306e484a, 
+    0xfc7ff02a, 0xbd102004, 0xb5704847, 0xf02a3066, 0x4604fc75, 0x306e4844, 0xfc70f02a, 0xb205494f, 
+    0x0003f004, 0x200c7008, 0x2014ea00, 0x0181f3c4, 0x49474408, 0xf3c47008, 0x49471001, 0xf3c47008, 
+    0x49441081, 0x48387008, 0xf02a3068, 0x4946fc57, 0x48358008, 0xf02a306a, 0x4944fc51, 0x48328008, 
+    0xf02a306c, 0x4942fc4b, 0x04208008, 0xf3c5d502, 0xe0001006, 0x493b2000, 0x20047008, 0xb510bd70, 
+    0x22014c3c, 0x46202102, 0xfc63f02a, 0x48264601, 0xf02a3066, 0x2206fc36, 0x21404620, 0xfc59f02a, 
+    0x48214601, 0xf02a3068, 0x2205fc2c, 0x21204620, 0xfc4ff02a, 0x481c4601, 0xf02a306a, 0x2004fc22, 
+    0x4819bd10, 0x3066b510, 0xfc18f02a, 0x22014c29, 0x46032102, 0xf02a4620, 0x4813fc2e, 0xf02a3068, 
+    0x2206fc0d, 0x21404603, 0xf02a4620, 0x480efc24, 0xf02a306a, 0x2205fc03, 0x21204603, 0xf02a4620, 
+    0x2004fc1a, 0x0000bd10, 0x00047ffc, 0x00047ff0, 0x00032220, 0x000331dc, 0x000323cc, 0xd0030430, 
+    0x00047ff4, 0x00047ff8, 0xd03c800a, 0x00032020, 0x0003221c, 0x00032218, 0x00032198, 0x000322ac, 
+    0x000323f0, 0x000322ec, 0x000322ed, 0x00032331, 0x000322b4, 0x0003230a, 0x00032309, 0x000322b3, 
+    0xd0035118, 0x000322b5, 0x000322b8, 0x000322ba, 0x000322bc, 0xd28e0040, 0xb51048fe, 0xfbbef02a, 
+    0x0101f000, 0x305448fb, 0xfbbbf02a, 0xe7b92004, 0xb51048f9, 0x48f77801, 0xf02a3054, 0x2004fbb2, 
+    0x48f4e7b0, 0x3054b510, 0xfba8f02a, 0x700849f2, 0xe7a72004, 0x4cf1b510, 0x22042300, 0x46202110, 
+    0xfbb9f02a, 0x46202300, 0x21202205, 0xfbb3f02a, 0x48e82300, 0x461a2101, 0xfbadf02a, 0xe7912004, 
+    0x4ce6b570, 0x2200230f, 0x46204619, 0xfba3f02a, 0x7507f240, 0x46291ca0, 0xfb83f02a, 0x46291d20, 
+    0xfb7ff02a, 0x46202301, 0x21102204, 0xfb93f02a, 0x46202301, 0x21202205, 0xfb8df02a, 0x48d52301, 
+    0x46192200, 0xfb87f02a, 0xbd702004, 0xe92d48d1, 0x305441f0, 0xfb62f02a, 0x48ce4607, 0xf02a3056, 
+    0x4604fb5d, 0x305848cb, 0xfb58f02a, 0x48c94606, 0xf02a305a, 0x2f18fb53, 0xd00f4605, 0xd0122f1c, 
+    0xd0152f0f, 0xd0192f17, 0x48c22100, 0x40e94031, 0xf02a305c, 0x2004fb46, 0x81f0e8bd, 0xb2e0b672, 
+    0xff28f005, 0xb672e012, 0xf005b2e0, 0xe00dff4c, 0xb2e0b672, 0xf0052101, 0xe007ff73, 0xb2e2b672, 
+    0x2103f3c4, 0x3041f3c4, 0xffa3f005, 0xb662b281, 0xe92de7db, 0x48af41fc, 0xf02a3054, 0x4607fb1f, 
+    0x305648ac, 0xfb1af02a, 0x48aa4604, 0xf02a3058, 0x4605fb15, 0x305a48a7, 0xfb10f02a, 0x48a54606, 
+    0xf02a305c, 0x2f18fb0b, 0xd0064680, 0xd0182f1c, 0xd01e2f0f, 0xd0242f17, 0xb672e030, 0x4643b2e0, 
+    0xb272b229, 0xfef5f005, 0x2c02b662, 0x06a8d126, 0x4898d524, 0x03a1220f, 0x30184643, 0xfb0bf02a, 
+    0xb672e01c, 0x4643b2e0, 0xb272b229, 0xff08f005, 0xb672e013, 0x4643b2e0, 0xb272b229, 0xff33f005, 
+    0xb672e00b, 0xe9cdb271, 0xb22b1800, 0xf3c4b2e2, 0xf3c42103, 0xf0053041, 0xb662ff5e, 0xe8bd2004, 
+    0x488781fc, 0x7801b510, 0x30544882, 0xfac9f02a, 0x78014884, 0x3056487f, 0xfac3f02a, 0xe6c12004, 
+    0xb510487c, 0xf02a3054, 0x497dfab9, 0x48797008, 0xf02a3056, 0x497bfab3, 0x20047008, 0x487ae6b2, 
+    0x7800b510, 0xd0122803, 0x48722100, 0xf02a3054, 0x4876faa8, 0x486f7801, 0xf02a3056, 0x4874faa2, 
+    0x486c7801, 0xf02a3058, 0x2004fa9c, 0x2101e69a, 0x4868e7eb, 0x3054b510, 0xfa90f02a, 0x7008496b, 
+    0xe68f2004, 0xb510486b, 0x0000f990, 0xd0092804, 0xd0072805, 0xd0052803, 0xd0242802, 0xd0222801, 
+    0xe67f2008, 0x23014c5d, 0x46192200, 0x46203c82, 0xfa91f02a, 0x46202301, 0x21082203, 0xfa8bf02a, 
+    0x46202301, 0x21042202, 0xfa85f02a, 0xf02a1ca0, 0x1d20fa65, 0xfa62f02a, 0x46202300, 0x461a2101, 
+    0xfa79f02a, 0x4c54e03b, 0x220f2301, 0x462003d9, 0xfa71f02a, 0x46202301, 0x0399220e, 0xfa6bf02a, 
+    0x46202301, 0x461a2102, 0xfa65f02a, 0x46202300, 0x21022201, 0xfa5ff02a, 0x46202301, 0x46192200, 
+    0xfa59f02a, 0x3c0a4c44, 0xf02a4620, 0x4620fa37, 0xfa34f02a, 0x46201ca4, 0xfa30f02a, 0xf02a4620, 
+    0x1ca4fa2d, 0xf02a4620, 0x4620fa29, 0xfa26f02a, 0x46201ca4, 0xfa22f02a, 0xf02a4620, 0x2004fa1f, 
+    0xe92de620, 0x482b47f0, 0xf02a3054, 0x4d29fa17, 0x4830b2c4, 0x1cae3556, 0x0804f105, 0x0000f990, 
+    0x0906f105, 0xd0082804, 0xd0062805, 0xd0042803, 0xd0632802, 0xd0612801, 0x4f20e094, 0x22032301, 
+    0x21083f82, 0xf02a4638, 0x2301fa16, 0x22024638, 0xf02a2104, 0xb114fa10, 0xd01b2c01, 0x4817e082, 
+    0xf02a387e, 0x4601f9eb, 0xf02a4628, 0x4813f9ea, 0xf02a3880, 0x4601f9e3, 0xf02a4630, 0x480ff9e2, 
+    0xf02a3876, 0x4601f9db, 0xf02a4640, 0x480bf9da, 0xe02e3878, 0x387a4809, 0xf9d0f02a, 0x46284601, 
+    0xf9cff02a, 0x387c4805, 0xf9c8f02a, 0x46304601, 0x0000e014, 0xd03c801c, 0x00032305, 0xd003526c, 
+    0x00032306, 0x00032307, 0x00032411, 0x0003230c, 0x00032422, 0x00032238, 0xd28f215e, 0xf9b1f02a, 
+    0xf02a48fe, 0x4601f9ab, 0xf02a4640, 0x48fbf9aa, 0xf02a1e80, 0x4601f9a3, 0xe0314648, 0x2c01b114, 
+    0xe02fd011, 0x46204cf6, 0xf998f02a, 0x46304601, 0xf997f02a, 0xf02a4620, 0x4601f991, 0xf02a4628, 
+    0x1ca4f990, 0x4ceee010, 0x46201ea4, 0xf986f02a, 0x46304601, 0xf985f02a, 0xf02a4620, 0x4601f97f, 
+    0xf02a4628, 0x1ea4f97e, 0xf02a4620, 0x4601f977, 0xf02a4648, 0x4620f976, 0xf970f02a, 0x46404601, 
+    0xf96ff02a, 0xe8bd2004, 0x48de87f0, 0xf02ab510, 0x4cddf965, 0x48db7020, 0xf02a1e80, 0x7821f95f, 
+    0xf00eb2c0, 0x2004ff9e, 0xb570e55c, 0x0500f244, 0x220e48d6, 0xf02a4629, 0x4cd2f97c, 0xb1781ea4, 
+    0x220e48d2, 0x38444629, 0xf973f02a, 0x48cfb140, 0x21012200, 0xf02a3850, 0xb108f96c, 0xe0002101, 
+    0x46202100, 0xf93df02a, 0x780148c7, 0xf02a48c5, 0x2004f938, 0x2301bd70, 0x220048c5, 0xb5104619, 
+    0xf949f02a, 0x304448c2, 0xf928f02a, 0x48bd4601, 0xf02a1e80, 0x48bef926, 0xf02a3046, 0x4601f91f, 
+    0xf02a48b8, 0x48baf91e, 0xf02a3048, 0x4601f917, 0x1c8048b4, 0xf915f02a, 0x304a48b5, 0xf90ef02a, 
+    0x48b04601, 0xf02a1d00, 0x2004f90c, 0x48b1e50a, 0x7801b510, 0x1e8048ab, 0xf903f02a, 0xe5012004, 
+    0xb51048a8, 0xf02a1e80, 0x49aaf8f9, 0x20047008, 0x48a9e4f8, 0x7801b510, 0x1e8048a2, 0xf8f1f02a, 
+    0x780148a6, 0xf02a489f, 0x2004f8ec, 0x489de4ea, 0x1e80b510, 0xf8e2f02a, 0x7008499f, 0xf02a4899, 
+    0x499ef8dd, 0x20047008, 0xb510e4dc, 0xf9944c9c, 0xb2810000, 0x1e804893, 0xf8d3f02a, 0x28027820, 
+    0x4890d107, 0xf02a305e, 0x4601f8c9, 0xf02a488d, 0x2004f8c8, 0x488be4c6, 0x41f0e92d, 0xf02a1e80, 
+    0x498ff8bd, 0x4d87b240, 0xf8df4f8e, 0x35668218, 0x37104e8c, 0x70082802, 0x085ef108, 0x488ad040, 
+    0x22032300, 0xf3c08800, 0x700820c0, 0x46382108, 0xf8aaf02a, 0x46282300, 0x21022201, 0xf8bbf02a, 
+    0x46282301, 0x0299220a, 0xf8b5f02a, 0x46282301, 0x02d9220b, 0xf8aff02a, 0x46382301, 0x461a2102, 
+    0xf892f02a, 0x46302301, 0x461a2102, 0xf88cf02a, 0x46382300, 0x21022201, 0xf886f02a, 0x46302300, 
+    0x21022201, 0xf880f02a, 0x46282300, 0x461a2101, 0xf891f02a, 0x46402100, 0xf873f02a, 0xe52b2004, 
+    0xf02a4860, 0xb2c4f86b, 0xd00b2c1a, 0xd0092c2a, 0xd0072c3a, 0xd0052c0b, 0xd0032c0c, 0xd0012c0d, 
+    0xd1eb2c0e, 0x46404621, 0xf85bf02a, 0x46282208, 0x01512301, 0xf86ff02a, 0x46282301, 0x02592209, 
+    0xf869f02a, 0x46282301, 0x46192200, 0xf863f02a, 0x49564854, 0xf02a3030, 0x2301f83e, 0x22024630, 
+    0xf02a2104, 0x2301f841, 0x22024638, 0xf02a2104, 0x484ff83b, 0xb2612200, 0x0000f990, 0xf801f01a, 
+    0x2001494c, 0xe7b97008, 0xb510484b, 0x483d7801, 0xf02a1e80, 0x4849f826, 0x483a7801, 0xf821f02a, 
+    0xe41f2004, 0xb5104837, 0xf02a1e80, 0x4942f817, 0x48347008, 0xf812f02a, 0x70084940, 0xe4112004, 
+    0x0110f1c1, 0xb2004088, 0x47704108, 0x47f0e92d, 0x2400482c, 0xf02a1e80, 0x07c0f801, 0xf44fd001, 
+    0x48371480, 0x44202200, 0x4606211f, 0xf821f02a, 0xf7ff2105, 0x4680ffe5, 0x22004831, 0x44201c80, 
+    0x4605217f, 0xf815f02a, 0xf7ff2109, 0x2205ffd9, 0xf2404681, 0x463071e0, 0xf80bf02a, 0xf7ff2106, 
+    0x2207ffcf, 0xf6404606, 0x46287180, 0xf801f02a, 0xf7ff2105, 0x220cffc5, 0xf24f4607, 0x46280100, 
+    0xfff7f029, 0xf7ff2104, 0x4605ffbb, 0xf3674640, 0xf369261f, 0xfa1f201f, 0x4819f880, 0x38e6b2b6, 
+    0x22004420, 0x210f4604, 0xffe3f029, 0x251ff360, 0x0100f246, 0x4620b2ad, 0xe023220d, 0xd00351fa, 
+    0xd28f2158, 0xd03c8072, 0x00032340, 0xd28f2050, 0xd0030406, 0x00032334, 0x00032337, 0x00032338, 
+    0x000323be, 0xc8000160, 0x000323c0, 0x00501bd0, 0x0003227e, 0x00032339, 0x00032308, 0x00032411, 
+    0xd203a22a, 0xffb5f029, 0x48ff4604, 0xf0294641, 0x48fdff88, 0x1c804631, 0xff83f029, 0x462948fa, 
+    0xf0291d00, 0x48f8ff7e, 0x1d804621, 0xff79f029, 0xe6082004, 0x47f0e92d, 0x27004df3, 0x1ead4cf3, 
+    0xf0294628, 0x0a06ff6b, 0xf0294628, 0x07c0ff67, 0x4cefd001, 0xf8df2701, 0x464893b0, 0xff5ef029, 
+    0x0586eb06, 0x46485560, 0xff58f029, 0x12004425, 0x0802f109, 0x46407068, 0xff50f029, 0x464070a8, 
+    0xff4cf029, 0x70e81200, 0x0a02f108, 0xf0294650, 0x7128ff45, 0x464db9fe, 0xf0294648, 0x73e0ff3f, 
+    0xf0294628, 0x1200ff3b, 0x74204645, 0xf0294640, 0x7460ff35, 0xf0294628, 0x1200ff31, 0x465074a0, 
+    0xff2cf029, 0x463a2103, 0x462074e0, 0xffdbf028, 0x2008b108, 0x2004e5b7, 0x48cbe5b5, 0x4ccbb510, 
+    0xf0291e80, 0x07c0ff1b, 0x4cc9d000, 0xf89448c6, 0x34211022, 0xff15f029, 0x782148c3, 0xf0291c80, 
+    0x2004ff10, 0x48c0e44b, 0x4cc0b570, 0x1e802500, 0xff04f029, 0xd00107c0, 0x25014cbd, 0xf02948ba, 
+    0xf884fefd, 0x34210022, 0x1c8048b7, 0xfef6f029, 0x7021b2c1, 0x462a7860, 0xfbaff027, 0xbd702004, 
+    0xb5102003, 0xfd7ff028, 0x48afb281, 0xf0291e80, 0x2004fee8, 0xfd77f028, 0x48abb281, 0xfee1f029, 
+    0xf0282005, 0xb281fd70, 0x1c8048a7, 0xfed9f029, 0xf0282006, 0xb281fd68, 0x1d0048a3, 0xfed1f029, 
+    0xe40c2004, 0x5ffce92d, 0x4da349a2, 0x0608f105, 0x1000f991, 0xd0032903, 0xd0012905, 0xd1002904, 
+    0x2000b180, 0xf8252180, 0xf8261010, 0x1c401010, 0x2804b2c0, 0xe8bdd3f7, 0x49975ffc, 0x31084896, 
+    0xb84af008, 0xf0084895, 0xf8dffbb8, 0x24009250, 0xb24cf8df, 0x0aeaf06f, 0xf06f4f92, 0x4992087e, 
+    0x4b922000, 0xe9cd465a, 0xf8590100, 0xf7ff0024, 0xfa0af86f, 0xb200f080, 0xf825287f, 0xdd030014, 
+    0xf825207f, 0xe0030014, 0xda014540, 0x8014f825, 0x1014f936, 0x0014f935, 0xdc024281, 0x29015d39, 
+    0xf826d103, 0x20000014, 0x1c645538, 0x2c04b2e4, 0xe7c0d3d5, 0x47ffe92d, 0x1e804873, 0xfe6ef029, 
+    0x70284d7b, 0xf0084875, 0x4f74fb78, 0xf8df2400, 0xae0281d0, 0x91d4f8df, 0x49732000, 0x464b4642, 
+    0x0100e9cd, 0x0024f857, 0xf832f7ff, 0x0014f826, 0xb2641c64, 0xdbef2c04, 0x1008f8bd, 0xf0294862, 
+    0x4861fe50, 0x100af8bd, 0xf0291c80, 0x485efe4a, 0x100cf8bd, 0xf0291d00, 0x485bfe44, 0x100ef8bd, 
+    0xf0291d80, 0x7828fe3e, 0x2000b110, 0xff6af7ff, 0xb0042004, 0x2000e4c7, 0xf028b510, 0xb281fcc4, 
+    0x1e804851, 0xfe2df029, 0xe4092004, 0xb510484e, 0xf0291e80, 0x4957fe23, 0x484b6008, 0xfe1ef029, 
+    0x60084955, 0x1c804848, 0xfe18f029, 0x70084953, 0xe4b92004, 0xb510484f, 0xb2818800, 0x1e804842, 
+    0xfe0ff029, 0x8800484c, 0x483fb281, 0xfe09f029, 0x7801484a, 0x1c80483c, 0xfe03f029, 0xe4a32004, 
+    0xb5104839, 0xf0291e80, 0x4945fdf9, 0x48366008, 0xfdf4f029, 0x60084943, 0x1c804833, 0xfdeef029, 
+    0x60084941, 0xe48f2004, 0xb510483d, 0xb2818800, 0x1e80482d, 0xfde5f029, 0x8800483a, 0x482ab281, 
+    0xfddff029, 0x88004838, 0x4827b281, 0xf0291c80, 0x2004fdd8, 0x4835e478, 0x7801b510, 0x1e804822, 
+    0xfdcff029, 0xe46f2004, 0xb510481f, 0xf0291e80, 0x492efdc5, 0x20047008, 0xe92de466, 0x200841f0, 
+    0x0144f248, 0x52b8f04f, 0xf829f7ff, 0x26004c28, 0x1ebf4f15, 0x28017820, 0x2200d109, 0x21034638, 
+    0xfdd7f029, 0x4823b918, 0xf00e7006, 0x2200fb99, 0x21034638, 0xfdcdf029, 0x70202202, 0x4638211c, 
+    0xfdc7f029, 0x2205491c, 0x21207008, 0xf0294638, 0xf8dffdc0, 0x28018014, 0xd13b4c18, 0xf64f2208, 
+    0x46407100, 0x0000e02c, 0xd03c8072, 0x0003fdfc, 0x0003fe1f, 0x00032238, 0x00032010, 0x000331dc, 
+    0xb573eab3, 0x0003238a, 0x40300000, 0x4030ab15, 0x000322d9, 0x000322f0, 0x000322f4, 0x000322ef, 
+    0x000322fc, 0x00032300, 0x000322f8, 0x000322ee, 0x00032360, 0x00032348, 0x00032361, 0x00032350, 
+    0xfd87f029, 0xfe08f02b, 0x0207f06f, 0xfc7bf02c, 0x0100e9c4, 0x46382206, 0xf0292140, 0x4df8fd7a, 
+    0xd10c2801, 0x46402200, 0xf02921ff, 0xf02bfd72, 0xf06ffdf3, 0xf02c0204, 0xe9c5fc66, 0x22070100, 
+    0x21804638, 0xfd65f029, 0xd1032801, 0x48ed49ee, 0x0100e9c4, 0x46382208, 0xf0290151, 0x2801fd5a, 
+    0x49ebd103, 0xe9c548e9, 0x22090100, 0x2100f240, 0xf0294638, 0x2801fd4e, 0x48e6d101, 0x220a7006, 
+    0x4100f240, 0xf0294638, 0x2801fd44, 0x48e2d101, 0x20047006, 0xe92de4a3, 0x200841f0, 0x0145f248, 
+    0x52b8f04f, 0xff7bf7fe, 0xf64f48da, 0x4ddb7400, 0x46212208, 0x46287803, 0xfd1df029, 0x220049d6, 
+    0x780b4628, 0xf02921ff, 0x49d5fd16, 0xe9d12208, 0xf02c0100, 0xf02bfc18, 0xb283fd5b, 0x1cad4621, 
+    0x46282208, 0xfd07f029, 0x220548c5, 0x0100e9d0, 0xfc09f02c, 0xfd4cf02b, 0x4628b283, 0x21ff2200, 
+    0xfcf9f029, 0x1cae48c7, 0x21032200, 0x46307803, 0xfcf1f029, 0x220248c4, 0x7803210c, 0xf0294630, 
+    0x4dc2fcea, 0x21702204, 0x782b4630, 0xfce3f029, 0xf64f2300, 0x22077180, 0xf0294630, 0x782afcdc, 
+    0x1cae1cb5, 0x4cbab152, 0xd0492a01, 0xd0522a02, 0x46282100, 0xfcb5f029, 0xe0592100, 0x22034fb5, 
+    0x0100e9d7, 0xfbcff02c, 0xfce2f02b, 0xdb0028ff, 0xb28320ff, 0x22004628, 0xf02921ff, 0x2203fcbc, 
+    0x0102e9d7, 0xfbbff02c, 0xfcd2f02b, 0xdb0028ff, 0x462120ff, 0x4628b283, 0xf0292208, 0x2203fcac, 
+    0x0104e9d7, 0xfbaff02c, 0xfcc2f02b, 0xdb0028ff, 0xb28320ff, 0x22004630, 0xf02921ff, 0x2203fc9c, 
+    0x0106e9d7, 0xfb9ff02c, 0xfcb2f02b, 0xdb0028ff, 0x462120ff, 0x4630b283, 0xf0292208, 0xe01afc8c, 
+    0x0100e9d4, 0xfcd4f02b, 0x4628b281, 0xfc69f029, 0x0102e9d4, 0xe9d4e009, 0xf02b0104, 0xb281fcc9, 
+    0xf0294628, 0xe9d4fc5e, 0xf02b0106, 0xb281fcc1, 0xf0294630, 0x2004fc56, 0xe92de73c, 0xf8df5ff0, 
+    0x210081fc, 0xf0294640, 0xf108fc4c, 0x21000902, 0xf0294648, 0xf108fc46, 0x21000a04, 0xf0294650, 
+    0xf108fc40, 0x21000b06, 0xf0294658, 0x4c7afc3a, 0x4d7b4f7a, 0xf5a08820, 0x39ff417f, 0x7838d013, 
+    0xd1102801, 0x46282204, 0xf0292110, 0x2203fc52, 0x21084606, 0xf0294628, 0x4286fc4c, 0x2000d101, 
+    0x2001e000, 0xf9978020, 0xb2810000, 0xf0294640, 0x8821fc18, 0xf0294648, 0x2204fc14, 0x21104628, 
+    0xfc37f029, 0x46504601, 0xfc0bf029, 0x46282203, 0xf0292108, 0x4601fc2e, 0xf0294658, 0x2004fc02, 
+    0x9ff0e8bd, 0x5ff0e92d, 0xf0294854, 0x4d5afbf7, 0xf64f4604, 0x882970ff, 0xd1084281, 0xf2482008, 
+    0xf04f0137, 0xf7fe52b8, 0x2008fe5a, 0x4e53e7e8, 0x0a02f04f, 0x80284949, 0x4f521c89, 0x0000f996, 
+    0x0b02f101, 0x8140f8df, 0x9140f8df, 0xd02c4284, 0xd01a2c01, 0x484e2301, 0x46192200, 0xa000f8a5, 
+    0xfbe9f029, 0x7034200a, 0xf8bdf006, 0x48492301, 0x029c220a, 0xf0294621, 0x4846fbc7, 0x220a2301, 
+    0x1d004621, 0xfbc0f029, 0x4608e024, 0xfbb6f029, 0x46587038, 0xfbb2f029, 0x0000f888, 0x1d80482f, 
+    0xfbacf029, 0x0000f889, 0x2c01e7dc, 0x4608d110, 0xfba4f029, 0x46587038, 0xfba0f029, 0x0000f888, 
+    0x1d804826, 0xfb9af029, 0x0000f889, 0xf8bdf00f, 0xa000f8a5, 0xe7932004, 0xb5104830, 0x68004c2e, 
+    0x482f6020, 0x482f6060, 0x482f60a0, 0x482f60e0, 0x482f6120, 0x482f6160, 0x482f61a0, 0x482f61e0, 
+    0x482f6220, 0x62606800, 0x62a0482e, 0x62e02000, 0x63606320, 0xf02563a0, 0x63e0f811, 0xb2814620, 
+    0x1d80480e, 0xfb6df029, 0x0c014620, 0x1d00480b, 0xfb67f029, 0x21104809, 0xfb63f029, 0xe4512004, 
+    0x00032358, 0xb71758e2, 0x3fae00d1, 0x538ef34d, 0x3ff42474, 0x00032349, 0x0003234a, 0xd03c8070, 
+    0x00032350, 0x00032360, 0x00032348, 0x00032361, 0x0003fe48, 0x0003fe68, 0x00032344, 0x00032277, 
+    0xd28f2056, 0x00032341, 0x00032342, 0x00032343, 0xd28f0000, 0xc1000030, 0x0003adac, 0x00032220, 
+    0x00047ff8, 0x00047ff0, 0x00047ff4, 0x00047ffc, 0x00047c00, 0x00047c40, 0x00047800, 0x00047c80, 
+    0x0003221c, 0x0003ab8c, 0xb51048fe, 0x48feb281, 0xfb17f029, 0x0c0148fb, 0x1e8048fb, 0xfb11f029, 
+    0xe43e2004, 0xb51048f8, 0xfb08f029, 0x48f64604, 0xf0291e80, 0xeb04fb03, 0x88204400, 0x48f2b281, 
+    0xf0291f00, 0x6820fafe, 0x48ef0c01, 0xf0291f80, 0x2004faf8, 0xb570e425, 0xf02948eb, 0x4604faef, 
+    0x1e8048e9, 0xfaeaf029, 0x4400eb04, 0x1f0048e6, 0xfae4f029, 0x48e44605, 0xf0291f80, 0xeb05fadf, 
+    0x60204000, 0xbd702004, 0x41f0e92d, 0x25004edf, 0x24004fdf, 0x0044eb07, 0xfad0f029, 0x01c5eb04, 
+    0xb2241c64, 0xf8262c08, 0xdbf30011, 0xb22d1c6d, 0xdbee2d40, 0xe5ad2004, 0xb51048d3, 0xfabef029, 
+    0x60204cd4, 0x1e8048d0, 0xfab8f029, 0xea416821, 0x60204000, 0xe4882004, 0x4cceb510, 0xb2818820, 
+    0xf02948c9, 0x6820faae, 0x48c70c01, 0xf0291e80, 0x2004faa8, 0x48c4e479, 0x1f80b538, 0xfa9ef029, 
+    0x48c1b245, 0xf0291f00, 0xb244fa99, 0x1e8048be, 0xfa94f029, 0xf04fb242, 0x2d010000, 0x4bbbd006, 
+    0x90004621, 0xf0042001, 0xe00afb56, 0x4ab749ba, 0x1104eb01, 0xf842560b, 0x1c403020, 0x2810b240, 
+    0x2004dbf8, 0x49b5bd38, 0xb5102000, 0xf6406008, 0x48b30100, 0xf02a6800, 0x48abfa5b, 0x1f802100, 
+    0xfa6ff029, 0xe4402004, 0x48ae2208, 0x41f0e92d, 0xf0290151, 0x4da4fa8e, 0x21202205, 0x3d5c4603, 
+    0xf0294628, 0x4ca8fa78, 0x21042202, 0xf0294620, 0x220dfa80, 0xf2424603, 0x46280100, 0xfa6bf029, 
+    0x46202202, 0xf0292104, 0x4e97fa74, 0x21012200, 0x3e544603, 0xf0294630, 0x4c9dfa5e, 0x489b2202, 
+    0x1000f994, 0x211c5c43, 0xf0294628, 0x4899fa54, 0xf2402209, 0x78036100, 0xf0294628, 0x4896fa4c, 
+    0x21802207, 0xfa55f029, 0x46032201, 0x46282102, 0xfa41f029, 0xf00e7820, 0xf994f931, 0x28050000, 
+    0x2804d002, 0xe005d002, 0xe000488c, 0x7800488c, 0xd0532800, 0x22004884, 0x30fc2101, 0xfa39f029, 
+    0x1000f994, 0x00c0ea41, 0x4630b283, 0x211e2201, 0xfa21f029, 0x78004883, 0xd1412801, 0x22004c82, 
+    0x46202101, 0xfa25f029, 0x46032200, 0x46282101, 0xfa11f029, 0x2206487d, 0x78032140, 0xf0294628, 
+    0x4871fa0a, 0x0700f640, 0x4639220b, 0xf0291f00, 0x220bfa10, 0x46394603, 0xf0294628, 0x2202f9fc, 
+    0x21044620, 0xfa05f029, 0x4603220c, 0x46280079, 0xf9f1f029, 0x46202202, 0xf0292104, 0x2205f9fa, 
+    0x21204603, 0xf0294630, 0x4969f9e6, 0x22064630, 0x21c0780b, 0x41f0e8bd, 0xb9ddf029, 0xe7b42303, 
+    0xb510e4a8, 0xff8ef028, 0x4604b281, 0x1e80484e, 0xf9b7f029, 0x0c21484c, 0xf9b3f029, 0xe64e2004, 
+    0xf2414849, 0xb5102134, 0xf0291c80, 0x4c45f9aa, 0xb2814620, 0xf0294844, 0x4620f9a4, 0x48420c01, 
+    0xf0291e80, 0xf028f99e, 0x6020ff7d, 0xff9af028, 0xf0286060, 0x60a0ff87, 0xff8cf028, 0xf02860e0, 
+    0x6120ff79, 0xff96f028, 0x21066160, 0x1f804836, 0xf987f029, 0xe6222004, 0x5ff0e92d, 0x24004832, 
+    0x1f804626, 0xf97af029, 0x482f4605, 0xf0291f00, 0xf8dff975, 0xf0009100, 0xf3c50807, 0xf3c53300, 
+    0xf3c02a03, 0xf9991702, 0xf0050000, 0xb3e8051f, 0xd07b2801, 0xf04f2802, 0xf04f0205, 0xd0760120, 
+    0xf0294835, 0xf999f978, 0xb3800000, 0xd06f2801, 0x46532802, 0x0200f04f, 0x010ff04f, 0x482ed069, 
+    0xf969f029, 0x482d2300, 0xf643461a, 0xf02971ff, 0xf8dff94b, 0x2d1ab0a8, 0xa0a4f8df, 0x0b78f10b, 
+    0xf1c8d278, 0xf64f0008, 0xeb0071ff, 0xea010040, 0xf04f2000, 0xeb0131ff, 0x48220150, 0xf92bf029, 
+    0x2118481e, 0xf0291f00, 0xe001f926, 0xe052e047, 0xea45481d, 0x43015147, 0xf0294658, 0xf89af91c, 
+    0xe0371000, 0x0003adac, 0xd03c8076, 0x00047800, 0xd003612e, 0x00047ffc, 0x0003308c, 0x00047ff0, 
+    0x00032220, 0xd28f2002, 0xd2054084, 0x0002e096, 0x0003227e, 0x00032411, 0xd28f2404, 0x00032307, 
+    0x00032306, 0x00032362, 0xd2154084, 0x00032363, 0x00032364, 0x00032283, 0xd00308e2, 0xd1800408, 
+    0x0003227f, 0xd1800488, 0x00080400, 0xe00fe00b, 0xe01ce016, 0x1080f44f, 0xfd26f005, 0x2205e025, 
+    0x212048fe, 0x48fde77d, 0x21202205, 0xe7783020, 0x304048fa, 0x2200e775, 0x210f48f8, 0xe77f4653, 
+    0x220048f6, 0x4653210f, 0xe7793020, 0x48f3e002, 0xe7753040, 0xf04fd102, 0xe03f040b, 0xd0382d1b, 
+    0xd0382d1c, 0xd0382d1d, 0xf999240b, 0x05781000, 0xea40464f, 0xea403081, 0xea404086, 0x46581144, 
+    0x465c4321, 0xf8a7f029, 0x211948e5, 0xf8a3f029, 0x1000f997, 0x2901b321, 0x2902d027, 0x0301f04f, 
+    0x0204f04f, 0x0110f04f, 0x48dcd025, 0xf0293060, 0x2d1af8b2, 0x2301d205, 0x221c4620, 0xf0290719, 
+    0xf89af893, 0xf44f1000, 0xf0051080, 0x2004fccd, 0x240fe486, 0x2410e7c9, 0x2411e7c7, 0xe7c42601, 
+    0x48ce2301, 0x21102204, 0x48cce7e1, 0x22042301, 0x30202110, 0x48c9e7db, 0xe7d83040, 0xb51048c9, 
+    0x48c97801, 0xf86df029, 0xe5082004, 0xb51048c6, 0xf864f029, 0x700849c3, 0xe5002004, 0xb51048c3, 
+    0x0000f990, 0x48c0b281, 0xf85bf029, 0x780148c0, 0x1c8048bd, 0xf855f029, 0xe4f02004, 0xb51048ba, 
+    0xf84cf029, 0x700849b9, 0x1c8048b7, 0xf846f029, 0x700849b7, 0xf0052007, 0x2004fd9a, 0x48b5e4df, 
+    0x7801b510, 0xf02948b0, 0x48b3f83c, 0x48ae7801, 0xf0291c80, 0x2004f836, 0x48abe4d1, 0xf029b510, 
+    0x49acf82d, 0x48a87008, 0xf0291c80, 0x49aaf827, 0x20077008, 0xfd7bf005, 0xe4c02004, 0x47f0e92d, 
+    0x9298f8df, 0x0800f241, 0x4604220c, 0x46484641, 0xf83ff029, 0x28014da2, 0x4ea34fa2, 0x02c1d10c, 
+    0xf02a6838, 0x2300f805, 0x220c4641, 0xf0294648, 0x2000f822, 0x60307028, 0xf99546a8, 0x28040000, 
+    0x6838da7e, 0xf8206831, 0x68304011, 0x60301c40, 0x3826488d, 0xfff2f028, 0x68326839, 0x4c934d93, 
+    0x0012f821, 0x1c406830, 0x350e6030, 0xf0284620, 0x6839ffe5, 0x68321ca4, 0x0012f821, 0x1c406830, 
+    0x42ac6030, 0x4c89d9f2, 0x1ca53420, 0xf0284620, 0x6839ffd5, 0x68321ca4, 0x0012f821, 0x1c406830, 
+    0x42ac6030, 0x4d82d9f2, 0x350e4c81, 0xf0284620, 0x6839ffc5, 0x68321ca4, 0x0012f821, 0x1c406830, 
+    0x42ac6030, 0x4d7bd9f2, 0x35144c7a, 0xf0284620, 0x6839ffb5, 0x68321ca4, 0x0012f821, 0x1c406830, 
+    0x42ac6030, 0x4c73d9f2, 0x1ca5341c, 0xf0284620, 0x6839ffa5, 0x68321ca4, 0x0012f821, 0x1c406830, 
+    0x42ac6030, 0x4d6cd9f2, 0x35084c6b, 0xf0284620, 0x6839ff95, 0x68321ca4, 0x0012f821, 0x1c406830, 
+    0x42ac6030, 0x4c64d9f2, 0x34144d63, 0x4620351e, 0xff84f028, 0x68326839, 0x0012f821, 0xe0006830, 
+    0x1c40e116, 0x1ca46030, 0xd9f042ac, 0x24002500, 0xb2ea2100, 0xf004b2e0, 0x6839fbec, 0x68321c64, 
+    0x0012f821, 0x1c406830, 0x2c046030, 0x1c6dd3f0, 0xd9ec2d24, 0x21002400, 0xf004b2e0, 0x6839fba1, 
+    0x68321c64, 0x0012f821, 0x1c406830, 0x2cff6030, 0x2400d9f1, 0xf004b2e0, 0x6839fb3d, 0x68321c64, 
+    0x0012f821, 0x1c406830, 0x2c076030, 0x2400d9f2, 0xf004b2e0, 0x6839fb58, 0x68321c64, 0x0012f821, 
+    0x1c406830, 0x2c1f6030, 0x483cd9f2, 0xff36f028, 0x68326839, 0x0012f821, 0x1c406830, 0x48376030, 
+    0xf0281c80, 0x6839ff2b, 0xf8216832, 0x68300012, 0x60301c40, 0x30204831, 0xff20f028, 0x68326839, 
+    0x0012f821, 0x1c406830, 0x482c6030, 0xf0283026, 0x6839ff15, 0xf8216832, 0x68300012, 0x60301c40, 
+    0x30404826, 0xff0af028, 0x68326839, 0x0012f821, 0x1c406830, 0x48216030, 0xf0283042, 0x6839feff, 
+    0x4c1e6832, 0xf8213478, 0x68300012, 0x60301c40, 0x46201da5, 0xfef2f028, 0x1ca46839, 0xf8216832, 
+    0x68300012, 0x60301c40, 0xd9f242ac, 0x1d254c14, 0xf0284620, 0x6839fee3, 0xe0236832, 0xd0030882, 
+    0xd1800404, 0x000322d8, 0xd03c8070, 0x00032236, 0x00032237, 0x000322e4, 0x000322e5, 0xd00351a4, 
+    0x00032328, 0x00032428, 0x0003231c, 0xd0034200, 0xd0039004, 0xd28fffc0, 0xd28f2000, 0xd28e0000, 
+    0xd28f0000, 0x0012f821, 0x1ca46830, 0x60301c40, 0xd9cd42ac, 0x1d254cfe, 0xf0284620, 0x6839feaf, 
+    0x68321ca4, 0x0012f821, 0x1c406830, 0x42ac6030, 0x4cf7d9f2, 0x1d25342e, 0xf0284620, 0x6839fe9f, 
+    0x68321ca4, 0x0012f821, 0x1c406830, 0x42ac6030, 0x4cefd9f2, 0x1d253448, 0xf0284620, 0x6839fe8f, 
+    0x68321ca4, 0x0012f821, 0x1c406830, 0x42ac6030, 0x4ce7d9f2, 0x1d25347a, 0xf0284620, 0x6839fe7f, 
+    0x68321ca4, 0x0012f821, 0x1c406830, 0x42ac6030, 0x48e0d9f2, 0xfe72f028, 0x68326839, 0x0012f821, 
+    0x1c406830, 0xf8986030, 0x1c491000, 0x1000f888, 0x87f0e8bd, 0xf6404ad8, 0x681071ff, 0xfb901c40, 
+    0xfb01f3f1, 0x60100013, 0xd1052800, 0x780849d3, 0xf0001c40, 0x8008000f, 0xe92d4770, 0x4ed05ff0, 
+    0xf0284630, 0x4acffe4b, 0x42818891, 0xd205d048, 0x73fff64f, 0x0101eba3, 0xe0014401, 0x0101eba0, 
+    0xf8df4fca, 0xf101c314, 0x80900101, 0x48c6b28d, 0xf8dc6839, 0xea452000, 0xf8410000, 0xf7ff0022, 
+    0xf8dfffc9, 0x2400a2fc, 0x46e046b1, 0x0a08f1aa, 0x0b02f10a, 0x4650e022, 0xfe20f028, 0x46584606, 
+    0xfe1cf028, 0xea46683a, 0xf8d84100, 0xf8420000, 0xf7ff1020, 0x48b2ffaf, 0xf0281f00, 0x4606fe0f, 
+    0xf0284648, 0x683afe0b, 0x4100ea46, 0x0000f8d8, 0x1020f842, 0xff9ef7ff, 0xb2a41c64, 0xd3da42ac, 
+    0xb570e576, 0xf0052005, 0x4ca8f9f7, 0x68214da2, 0xf841682a, 0xf7ff0022, 0x48a5ff8d, 0x682a6821, 
+    0xf8416800, 0xf7ff0022, 0x48a2ff85, 0xfde6f028, 0x48a04606, 0xf0283814, 0x6821fde1, 0x4000ea46, 
+    0xf841682a, 0xf7ff0022, 0x489bff75, 0xfdd6f028, 0xf1004e92, 0x682a508d, 0xea408831, 0x68214001, 
+    0x0022f841, 0xff66f7ff, 0x1c804893, 0xfdc6f028, 0x682a4992, 0x88314408, 0x4001ea40, 0xf8416821, 
+    0xf7ff0022, 0x488cff57, 0xf0281d00, 0x8831fdb7, 0x508ef100, 0xea40682a, 0x68214001, 0x0022f841, 
+    0xff48f7ff, 0x1d804884, 0xfda8f028, 0x682a4984, 0x88314408, 0x4001ea40, 0xf8416821, 0xf7ff0022, 
+    0x487dff39, 0xf0283010, 0x8831fd99, 0x5095f100, 0xea40682a, 0x68214001, 0x0022f841, 0xff2af7ff, 
+    0x30124875, 0xfd8af028, 0x682a4976, 0x88314408, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x486eff1b, 
+    0xf0283014, 0x8831fd7b, 0x5096f100, 0xea40682a, 0x68214001, 0x0022f841, 0xff0cf7ff, 0x30164866, 
+    0xfd6cf028, 0x682a4968, 0x88314408, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x485ffefd, 0xf0283028, 
+    0x8831fd5d, 0x509df100, 0xea40682a, 0x68214001, 0x0022f841, 0xfeeef7ff, 0x302a4857, 0xfd4ef028, 
+    0x682a495a, 0x88314408, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x4850fedf, 0xf028302c, 0x8831fd3f, 
+    0x509ef100, 0xea40682a, 0x68214001, 0x0022f841, 0xfed0f7ff, 0x302e4848, 0xfd30f028, 0x682a494c, 
+    0x88314408, 0x4001ea40, 0xf8416821, 0xf7ff0022, 0x4841fec1, 0xf028307a, 0x8831fd21, 0x50a0f100, 
+    0xea40682a, 0x68214001, 0x0022f841, 0xfeb2f7ff, 0x307c4839, 0xfd12f028, 0xf1008831, 0x682a50a8, 
+    0x4001ea40, 0xf8416821, 0xf7ff0022, 0x4832fea3, 0xf028307e, 0x8831fd03, 0x50b0f100, 0xea40682a, 
+    0x68214001, 0x0022f841, 0xfe94f7ff, 0xf0284831, 0x8831fcf5, 0x50b8f100, 0xea40682a, 0x68214001, 
+    0x0022f841, 0xfe86f7ff, 0x382e4819, 0xfce6f028, 0xf1008831, 0x682a50c0, 0x4001ea40, 0xf8416821, 
+    0xe8bd0022, 0xe6754070, 0xb5102005, 0xf8d4f005, 0x680a4921, 0xd2034282, 0x681a4b15, 0x601a1c52, 
+    0xe4626008, 0x5ff0e92d, 0x48134604, 0xf028307a, 0xf000fcc5, 0x4806051f, 0x21f02204, 0xf028382e, 
+    0xb2c7fce8, 0xffe0f7ff, 0xf8df4e14, 0xe0298054, 0xd28f0032, 0xd0039000, 0x00032310, 0x00032320, 
+    0xd03c826c, 0x00032000, 0xeeee0000, 0x00032424, 0x00032324, 0xd28fffd4, 0xd28f2200, 0x11b00000, 
+    0x11d00000, 0x12b00000, 0x12d00000, 0x13b00000, 0x13d00000, 0xd28f2012, 0x0003232c, 0x00032314, 
+    0x00032318, 0xb454f8df, 0x68312207, 0xf8c84658, 0xf2401000, 0xf0281180, 0xf8dffcac, 0xf04f9444, 
+    0xb3000a01, 0x46582205, 0xf0282120, 0x2801fca2, 0xf899d10c, 0x42850000, 0x2200d008, 0x211f4658, 
+    0xfc97f028, 0x1000f899, 0xd00c4288, 0x46582205, 0xf0282120, 0xb940fc8e, 0x46582200, 0xf028211f, 
+    0x42a8fc88, 0xf8c6d101, 0x2206a000, 0x214048fb, 0xfc7ff028, 0xf899b148, 0x428d1000, 0xf899d105, 
+    0x42870001, 0x2c00d101, 0xf889d067, 0x2c0a5000, 0xb3d0f8df, 0xf8894df4, 0xd9057001, 0x0000f8db, 
+    0xf8406829, 0xe0104021, 0xd1102c01, 0xf02848ef, 0x4607fc35, 0x1e8048ed, 0xfc30f028, 0xea47682a, 
+    0xf8db4100, 0xf8400000, 0xf7ff1022, 0x48e3fdc3, 0xf2402207, 0xf0281180, 0xb3e8fc4c, 0x220748df, 
+    0x1180f240, 0xfc45f028, 0x68302801, 0x77fff640, 0xb388d003, 0xd0172801, 0x2801e019, 0xf8dfd152, 
+    0x0381935c, 0x4648220e, 0xfc33f028, 0x6828b320, 0x42b83010, 0x2000db25, 0x23016030, 0x0000f8c8, 
+    0x4648220a, 0xe0380299, 0x0000f8d8, 0xf8d9b1e0, 0x42b8000c, 0xfbb0d30c, 0xfb07f1f7, 0x68290311, 
+    0x0c10f101, 0xd80c4563, 0x2008f8d9, 0xd8084291, 0xd21a42b8, 0xe0016829, 0xe056e003, 0x42813110, 
+    0xf7ffd213, 0xe01afdde, 0x0000f8db, 0x31fff04f, 0xf840682a, 0xf7ff1022, 0x6828fd6d, 0x0008f8c9, 
+    0x70fff200, 0x000cf8c9, 0x2000e7eb, 0x23016030, 0x0000f8c8, 0x220a48b1, 0xf0280299, 0x6830fbdc, 
+    0xd0072801, 0x220748ad, 0x1180f240, 0xfbe1f028, 0xd1202802, 0x220648a9, 0xf0282140, 0xb9d0fbda, 
+    0x4cabb9cc, 0x210f2200, 0xf0284620, 0xb190fbd2, 0x46202200, 0xf028210f, 0xfa0afbcc, 0xb28cf100, 
+    0x2500f240, 0x2100e005, 0xf0044628, 0x1e64ffdd, 0x2c00b2a4, 0x489fd1f7, 0x21012200, 0xfbb9f028, 
+    0xd1022801, 0x5ff0e8bd, 0xe589e537, 0x20004996, 0x6008b510, 0x80084998, 0x60084998, 0xf0042005, 
+    0x4997ff7b, 0xe6ac6008, 0x4ff8e92d, 0xb22cf8df, 0x2800f240, 0x46152700, 0x460e2209, 0x46414604, 
+    0x97004658, 0xfb95f028, 0xd1112801, 0x20004985, 0x72fff640, 0xf8416809, 0x1c407020, 0xd3fa4290, 
+    0x46412300, 0x46582209, 0xfb75f028, 0xffcef7ff, 0xf2482c01, 0xeb050900, 0xd0172606, 0xd02f2c02, 
+    0xf2424d7a, 0xf8df0100, 0xf04fa1d8, 0x1ead0801, 0xd02b2c03, 0xd07d2cfe, 0xd1252c04, 0x465c220d, 
+    0xf0284658, 0x2801fb66, 0xe084d075, 0x4649220f, 0x4658465c, 0xfb5df028, 0xd0152800, 0xf244220e, 
+    0x46200100, 0xfb55f028, 0xd10d2800, 0xf240220a, 0x46204100, 0xfb4df028, 0xd1052800, 0xe0004869, 
+    0x44304869, 0xfe4ef7ff, 0x8ff8e8bd, 0x4654220d, 0xf88a4658, 0xf0287002, 0x2801fb3c, 0xf64ad103, 
+    0xf7ff20aa, 0x4f61faeb, 0x0000f44f, 0x46d946ca, 0xe00d9000, 0x21004a51, 0x3a2a4668, 0xffbef004, 
+    0xd0e12801, 0x4430485a, 0xfe2cf7ff, 0x8002f884, 0x4651220f, 0xf0284648, 0x2801fb1c, 0x0381d1d4, 
+    0x220e4628, 0xfb15f028, 0xd1cd2800, 0x46282204, 0xf0282110, 0x2800fb0e, 0x2205d1c6, 0x21204628, 
+    0xfb07f028, 0xd1bf2800, 0x46382203, 0xf0282108, 0x2800fb00, 0x2204d1b8, 0x21104638, 0xfaf9f028, 
+    0xd1b12800, 0x46382205, 0xf0282120, 0x2800faf2, 0xe001d1aa, 0xe00ae009, 0xf240220a, 0x46484100, 
+    0xfae7f028, 0xd0b52800, 0x483ae79e, 0xf64be79a, 0xf7ff30bb, 0x220bfa93, 0x0100f640, 0xf0284620, 
+    0x0001fad8, 0x30ddf04f, 0xf88a4656, 0xd0077002, 0x46834647, 0x0802f04f, 0xf24046ca, 0xe0784900, 
+    0xa078f8df, 0x0100f44f, 0x46834647, 0x0a2af1aa, 0x4800f240, 0xe00b9100, 0x46522101, 0xf0044668, 
+    0x2801ff4d, 0x78b0d0d0, 0x2000b330, 0xfdbaf7ff, 0x4649220f, 0xf0284620, 0x2801faac, 0x0381d1c4, 
+    0x220e4628, 0xfaa5f028, 0xd1bd2800, 0x46282204, 0xf0282110, 0x2801fa9e, 0x4817d1b6, 0x21f02204, 
+    0xfa97f028, 0xd0af2801, 0x4641220a, 0xf0284620, 0x2800fa90, 0xe747d0d0, 0x0000e020, 0xd00351a4, 
+    0x00032000, 0x00032424, 0x00032310, 0xd0039028, 0xd03c802a, 0xd03c8260, 0x00032320, 0x00032324, 
+    0x0003232c, 0xaaaa0000, 0xbbbb0000, 0xd0035040, 0xcccc0000, 0xdddcdddd, 0xd28f0004, 0xf7ff4658, 
+    0x70b7fd71, 0x220ee7b4, 0x0100f244, 0xf0284628, 0x2800fa60, 0xd00878b0, 0xd0072802, 0x30eef04f, 
+    0xfd60f7ff, 0x8002f886, 0xb1c0e003, 0xf7ff2000, 0x220ffd59, 0x46204651, 0xfa4bf028, 0xd1ba2801, 
+    0x46282204, 0xf0282110, 0x2801fa44, 0x220ad1b3, 0x46204649, 0xfa3df028, 0xd0d42800, 0x4658e6f4, 
+    0xfd40f7ff, 0xe7e470b7, 0xb51048fe, 0xfa06f028, 0x46012200, 0xf7fd2001, 0x48fafc72, 0xf0281c80, 
+    0x2200f9fd, 0x20014601, 0xfc69f7fd, 0x1d0048f5, 0xf9f4f028, 0x46012200, 0x4010e8bd, 0xf7fd2001, 
+    0xb570bc5e, 0x4615460c, 0x46012200, 0xf7fd2001, 0x2200fc56, 0x20014621, 0xfc51f7fd, 0xe8bd4629, 
+    0x22004070, 0xf7fd2001, 0xe92dbc4a, 0x200841f0, 0x0125f248, 0x52b8f04f, 0xfc41f7fd, 0x220d4de2, 
+    0x0100f242, 0xf0284628, 0x220cf9f4, 0xf2414604, 0x46280100, 0xf9edf028, 0x42044ddc, 0x0602f105, 
+    0x0704f105, 0x0406f105, 0x2100d021, 0x46082202, 0xfe2ff003, 0x4628b281, 0xf9b3f028, 0x21002202, 
+    0xf0032001, 0xb281fe26, 0xf0284630, 0x2202f9aa, 0x46102100, 0xfe1df003, 0x4638b281, 0xf9a1f028, 
+    0x21002202, 0xf0032003, 0xb281fe14, 0x2100e00c, 0xf0284628, 0x2100f996, 0xf0284630, 0x2100f992, 
+    0xf0284638, 0x2100f98e, 0xf0284620, 0x2101f98a, 0xf0032014, 0xb281fd5d, 0x300848bc, 0xf981f028, 
+    0xe8bd2004, 0x48b981f0, 0xf028b510, 0x49b8f977, 0x48b68008, 0xf0281c80, 0x49b6f971, 0x20048008, 
+    0x48b3e49f, 0x8801b510, 0xf02848b0, 0x48b1f96a, 0x48ae8801, 0xf0281c80, 0x2004f964, 0x48abe491, 
+    0xf028b510, 0x49acf95b, 0x200c7008, 0xfe4bf004, 0x48aa2301, 0x031c220c, 0xf0284621, 0x48a7f955, 
+    0x220c2301, 0x1d004621, 0xf94ef028, 0xe4782004, 0xb51048a1, 0x489d7801, 0xf943f028, 0xe4702004, 
+    0x41f0e92d, 0x8278f8df, 0x21022201, 0xf0284640, 0xf108f960, 0x46050402, 0x46202201, 0xf0282102, 
+    0xea45f958, 0x48910100, 0xf92bf028, 0x22024d95, 0x46282104, 0xf94df028, 0x22024e92, 0x46072104, 
+    0x4630360a, 0xf945f028, 0x0100ea47, 0x1c804887, 0xf917f028, 0x46202201, 0xf0282102, 0x2202f93a, 
+    0x21044604, 0xf0284630, 0xea44f934, 0x46400600, 0x21022201, 0xf92df028, 0x46042202, 0x46282104, 
+    0xf927f028, 0xea464304, 0xb2810044, 0x1d004877, 0xf8f7f028, 0xe7742004, 0x4ff8e92d, 0xf0284873, 
+    0xb2c4f8ed, 0x1c804871, 0xf8e8f028, 0x9000b2c0, 0x1d00486e, 0xf8e2f028, 0xf8dfb2c5, 0x4e7381cc, 
+    0x07a84f73, 0xf640d570, 0x46380900, 0x46492301, 0xf028220b, 0xf8dff8f0, 0x2206a1a8, 0x46232140, 
+    0xf0284650, 0xb184f8e8, 0xf6412314, 0x22087100, 0x0004f1aa, 0xf8dff028, 0x23274861, 0xf2402204, 
+    0x389a31f0, 0xf8d7f028, 0xf898e003, 0xf0060000, 0xf8dffb96, 0x2308b16c, 0xf10b2200, 0x211f0b14, 
+    0xf0284658, 0x2324f8c8, 0x7100f643, 0x46582208, 0xf8c1f028, 0x46cb2300, 0x4649220b, 0xf0284638, 
+    0x2301f8ba, 0x220b4659, 0xf0284630, 0x2201f8b4, 0x21024623, 0x465046d1, 0xf8adf028, 0x46232207, 
+    0x46482180, 0xf8a7f028, 0x46592300, 0x4630220b, 0xf8a1f028, 0x910cf8df, 0x21022301, 0x4648461a, 
+    0xf899f028, 0x22009b00, 0x46482101, 0xf893f028, 0x46482300, 0x21022201, 0xf88df028, 0x22029b00, 
+    0x46482104, 0xf887f028, 0xd05a07e8, 0x0900f241, 0x230146ba, 0x220c4649, 0xf0284638, 0x4d30f87c, 
+    0x21082203, 0x1cad4623, 0xf0284628, 0xb17cf874, 0xf6412310, 0x22087100, 0xf0281f28, 0x4828f86c, 
+    0x22042324, 0x31f0f240, 0xf0283898, 0xe003f864, 0x0000f898, 0xfb23f006, 0x23084f21, 0x37162200, 
+    0x4638211f, 0xf857f028, 0xf6432320, 0x22087100, 0xf0284638, 0x2300f850, 0x220c464f, 0x46504649, 
+    0xf849f028, 0x46392301, 0x4630220c, 0xf843f028, 0x46232201, 0x46282102, 0xf83df028, 0x46232204, 
+    0x46282110, 0xf837f028, 0x46392300, 0x4630220c, 0xf831f028, 0x23014c0b, 0x461a2102, 0x4620340a, 
+    0xe02be018, 0xd28e002c, 0xd28fffd4, 0xd03c8070, 0x0003233c, 0x0003233e, 0x00032364, 0xc1000030, 
+    0xd0035336, 0xd205409a, 0x0003227e, 0xd03c8306, 0xd0035026, 0xf80ff028, 0x22009b00, 0x46202101, 
+    0xf809f028, 0x46202300, 0x21022201, 0xf803f028, 0x22029b00, 0x46202104, 0xfffdf027, 0xe4c32004, 
+    0xb51048bb, 0x48bb7801, 0xffdbf027, 0x880048ba, 0x48b8b281, 0xf0271c80, 0x2004ffd4, 0x48b5e453, 
+    0xf027b510, 0x49b2ffcb, 0x48b27008, 0xf0271c80, 0x49b1ffc5, 0x20046008, 0x48b0e445, 0xf990b510, 
+    0xb2810000, 0xf02748ab, 0x2004ffbc, 0x48a9e43b, 0xf027b510, 0x49a9ffb3, 0x20047008, 0x49a9e433, 
+    0xb5102200, 0xe9d14ca6, 0x46230100, 0xf8a4f02a, 0xffdef029, 0x489fb281, 0xffa3f027, 0x220049a2, 
+    0xe9d14623, 0xf02a0100, 0xf029f897, 0xb281ffd1, 0x1c804898, 0xff95f027, 0x7801489c, 0x1d004895, 
+    0xff8ff027, 0x489a499b, 0x78007809, 0x2101ea40, 0x1d804890, 0xff85f027, 0x78014897, 0x3008488d, 
+    0xff7ff027, 0xe60b2004, 0xb510488a, 0xff76f027, 0x4c8bb200, 0xd0081c41, 0xf807f02a, 0x46232200, 
+    0xfe4ef029, 0xe9c24a87, 0x48820100, 0xf0271c80, 0xb200ff65, 0xd0081c41, 0xfff7f029, 0x46232200, 
+    0xfe3ef029, 0xe9c24a80, 0x487a0100, 0xf0271d00, 0x497eff55, 0x1da44c77, 0x46207008, 0xff4ef027, 
+    0x0a014a7c, 0x70112920, 0x2020d901, 0x46207010, 0xff44f027, 0x70084976, 0x3008486e, 0xff3ef027, 
+    0x70084975, 0xe5cb2004, 0xb5104874, 0x48697801, 0xff37f027, 0x78014872, 0x1c804866, 0xff31f027, 
+    0x78014870, 0x1d004863, 0xff2bf027, 0x7801486e, 0x1d804860, 0xff25f027, 0xe5b12004, 0xb510485d, 
+    0xff1cf027, 0x70084965, 0x1c80485a, 0xff16f027, 0xf0004963, 0x70080003, 0x1d004856, 0xff0ef027, 
+    0xf0004960, 0x70080003, 0x1d804852, 0xff06f027, 0x7008495d, 0xe5932004, 0xb510485c, 0x484d7801, 
+    0xfefff027, 0x7801485a, 0x1c80484a, 0xfef9f027, 0xe5852004, 0xb5104847, 0xfef0f027, 0x70084953, 
+    0x1c804844, 0xfeeaf027, 0x70084951, 0xe5772004, 0xb5104850, 0x483f7801, 0xfee3f027, 0xe56f2004, 
+    0xb510483c, 0xfedaf027, 0x7008494a, 0xe5672004, 0xb5104849, 0x48377801, 0xfed3f027, 0xe55f2004, 
+    0xb5104834, 0xfecaf027, 0x70084943, 0xe5572004, 0xb5104842, 0x482f7801, 0xfec3f027, 0x88014840, 
+    0x1c80482c, 0xfebdf027, 0x8801483e, 0x1d004829, 0xfeb7f027, 0xe5432004, 0xb5104826, 0xfeaef027, 
+    0x70084936, 0x1c804823, 0xfea8f027, 0x80084934, 0x1d004820, 0xfea2f027, 0x80084932, 0xe52f2004, 
+    0xb510481c, 0xfe9af027, 0xf0004a2f, 0x70110101, 0x0140f3c0, 0xf3c04a2d, 0x70110080, 0x7008492c, 
+    0xe51d2004, 0x48284929, 0x7809b510, 0xeb007800, 0x49270041, 0xeb007809, 0x480e0181, 0xfe81f027, 
+    0xe50d2004, 0xb510480b, 0xfe78f027, 0xb2c04921, 0x70082801, 0x2000d102, 0xfd55f005, 0xe4ff2004, 
+    0xb510481c, 0x48037801, 0xfe6bf027, 0xe4f72004, 0x00032369, 0xd03c8070, 0x0003236c, 0x00032365, 
+    0x40c38800, 0x000322c8, 0x000322d0, 0x000323fc, 0x000323fa, 0x000323f9, 0x000323fb, 0x00032367, 
+    0x00032430, 0x00032431, 0x00032368, 0x00032370, 0x00032371, 0x00032372, 0x00032378, 0x0003237c, 
+    0x0003237a, 0x0003237e, 0x0003238e, 0x0003238f, 0x00032390, 0x00032391, 0x2400b510, 0xfa94f01e, 
+    0x23042200, 0x20014611, 0xfd2df009, 0xf027480f, 0x2803fe25, 0x2001d003, 0xfcdbf01b, 0x480c4604, 
+    0xf027b2a1, 0x480afe1e, 0x38220c21, 0xfe19f027, 0xfb3df01b, 0xfd68f01b, 0xfbd6f017, 0xf8c8f000, 
+    0xfe39f000, 0xfbf1f023, 0xbd102001, 0xd0034006, 0xd03c80ba, 0x41f0e92d, 0xf64b48ff, 0xf02731b4, 
+    0x48fefe00, 0xf0272100, 0x48fdfdfc, 0x60042400, 0x600448fc, 0x700448fc, 0x800448fc, 0x800448fc, 
+    0x700448fc, 0x700448fc, 0x700448fc, 0xf0044620, 0x49fbfa1b, 0x48fb7008, 0x48fb7004, 0xb1007800, 
+    0x49fa2020, 0x80082201, 0x49fe48f9, 0x48f97004, 0x48f97004, 0x48f97002, 0x48f97004, 0xf5b08800, 
+    0xd01f7fa8, 0x7facf5b0, 0xf5b0d01c, 0xd0197fb0, 0x7fb4f5b0, 0xf5b0d016, 0xd0137fb8, 0x7fbcf5b0, 
+    0xf881d010, 0xf8812021, 0x26702022, 0x273848ee, 0x230c4dee, 0x0e3af04f, 0x0c04f04f, 0x28017800, 
+    0xe008d005, 0x4021f881, 0x4022f881, 0xf885e7ed, 0xf8852021, 0x73cc2022, 0xe010f881, 0xc011f881, 
+    0x74cc748c, 0x754e750c, 0x75cc758c, 0x764c760c, 0x76cc768e, 0x774c770c, 0x72cf728c, 0x734c730c, 
+    0x714c738c, 0x71cc718f, 0x724c720c, 0x77cc778b, 0x73ecd11c, 0xe010f885, 0xc011f885, 0x74ec74ac, 
+    0x756e752c, 0x75ec75ac, 0x766c762c, 0x76ec76ae, 0x776c772c, 0x72ef72ac, 0x736c732c, 0x716c73ac, 
+    0x71ec71af, 0x726c722c, 0x77ec77ab, 0x4300f241, 0x48c749c8, 0x60084dcc, 0x48c749c8, 0x49c86008, 
+    0x700a48c8, 0x802b7002, 0x4dc94bc8, 0x602b681b, 0x239ef44f, 0x602b4dc7, 0x681b4bc7, 0xd1052b03, 
+    0x701a4bc6, 0x48c67004, 0x7002700c, 0x81f0e8bd, 0xf007b510, 0x2201fe21, 0x20051e94, 0xf0044621, 
+    0x2201f951, 0x20004621, 0xf94cf004, 0xff6ef024, 0xff30f7ff, 0xffc1f7fc, 0xfcd3f00b, 0xfe36f024, 
+    0xfc96f017, 0xf00c2001, 0xf023fdcb, 0xf026fc69, 0xf004fab9, 0x4890fbbd, 0x384a2104, 0xfd21f027, 
+    0x4010e8bd, 0xba64f005, 0x47f0e92d, 0x92b4f8df, 0x461e2804, 0xf8dd4617, 0x460da020, 0xf6404604, 
+    0xd0174800, 0xd0272c05, 0xf0052000, 0x462bfc62, 0x46394632, 0xf0054620, 0x2100fcc1, 0xf0054620, 
+    0x2300fd2e, 0x220a4641, 0xf0274648, 0x2100fd14, 0xe0274608, 0xf0054608, 0x462bfc4c, 0x46394632, 
+    0xf0054620, 0xb12ffcab, 0x46202100, 0xfd17f005, 0xe0102302, 0xe7f84651, 0xf0054608, 0x462bfc3a, 
+    0x46394632, 0xf0054620, 0xb1b6fc99, 0x46202100, 0xfd05f005, 0x46412301, 0x4648220a, 0xfcebf027, 
+    0x46082101, 0xfdd2f01a, 0x7100f505, 0x47f0e8bd, 0x5280f04f, 0xf7fc1250, 0x4651bf32, 0xe92de7e7, 
+    0x000641f0, 0xf04f4880, 0x460d0700, 0x487f7007, 0x487f7007, 0x487f7007, 0x487f7007, 0x487f7007, 
+    0xd1247007, 0x4982487e, 0x487e7007, 0x487e7007, 0x487e7007, 0x20047007, 0x497e7008, 0x497e7008, 
+    0x497e7008, 0x487e7008, 0x487e7007, 0x487e7007, 0x487e7007, 0x487e7007, 0x487e7007, 0x487e7007, 
+    0x487e7007, 0x487e7007, 0x487e7007, 0x24017007, 0x7004487d, 0x7004487d, 0x7004487d, 0x7004487d, 
+    0x7004487d, 0x7004487d, 0x7004487d, 0x7004487d, 0x7007487d, 0x7007487d, 0x7007487d, 0x7007487d, 
+    0x7007487d, 0x7007487d, 0x7007487d, 0x7007487d, 0x7007487d, 0x8007487d, 0x8007487d, 0x7007487d, 
+    0x7007487d, 0x7007487d, 0x7007487d, 0x7007487d, 0x8007487d, 0xf00a2001, 0x2005fa0a, 0xfa27f00a, 
+    0x2000497a, 0x7010f821, 0xb2401c40, 0xdbf92804, 0xf00a2001, 0x2000fa3e, 0xfa3bf00a, 0x4874b936, 
+    0x48747801, 0xd0182903, 0x70012103, 0x2d044872, 0x4b31492f, 0x70044a34, 0x48304c2e, 0x6021d00f, 
+    0x60032d05, 0xf241d010, 0x80114100, 0x6809496b, 0xd1012912, 0x6001496a, 0x7004e6d8, 0x6021e7e6, 
+    0xf6446003, 0xe00170b8, 0x70dcf242, 0xe6cd8010, 0x4ffee92d, 0x48084606, 0x1e802100, 0xfc11f027, 
+    0x21004805, 0xf0273808, 0x485efc0c, 0x70042400, 0xf0054620, 0xe0b7f997, 0xd03c80b8, 0xd03c8322, 
+    0x00047f7c, 0x00047f80, 0x00032271, 0x00032272, 0x00032274, 0x00032276, 0x00032277, 0x0003227e, 
+    0x0003227f, 0x00032238, 0x000323bf, 0x0003227c, 0x000322b3, 0x000322b4, 0x00032308, 0x00032372, 
+    0x00032392, 0x0003fdfc, 0x00032362, 0x0003fe1f, 0x0003d090, 0x00032418, 0x1e8c2120, 0x0003241c, 
+    0x00032306, 0x00032307, 0x00032420, 0x00032218, 0x00032424, 0x00032428, 0x00032374, 0x00032305, 
+    0x00032337, 0xd0030802, 0x0003223b, 0x0003223c, 0x0003223d, 0x0003223e, 0x0003223f, 0x00032240, 
+    0x00032241, 0x00032242, 0x00032243, 0x00032244, 0x00032245, 0x00032246, 0x00032247, 0x00032248, 
+    0x00032249, 0x0003224a, 0x0003224b, 0x0003224c, 0x0003224d, 0x0003224e, 0x0003224f, 0x000322c1, 
+    0x00032cd7, 0x00032cd8, 0x00032250, 0x00032251, 0x00032252, 0x00032253, 0x00032254, 0x00032255, 
+    0x00032256, 0x00032257, 0x00032258, 0x00032259, 0x0003225a, 0x0003225b, 0x0003225c, 0x0003225d, 
+    0x0003225e, 0x0003225f, 0x00032260, 0x00032262, 0x00032264, 0x00032266, 0x00032267, 0x00032268, 
+    0x00032269, 0x0003223a, 0x000323e0, 0x000323e2, 0x00032270, 0x00032283, 0x00032280, 0x0003222c, 
+    0x2245cdc0, 0x00032b5c, 0xf8ddf00b, 0xf0074630, 0x2300fb85, 0x461a200f, 0x90004619, 0xf0074618, 
+    0xf015fba7, 0x2000fe19, 0xf7ff4631, 0xf8dffe78, 0x2e03a3f8, 0xb3f4f8df, 0xd02d4dfd, 0x0000f89a, 
+    0x1000f89b, 0xd11f4308, 0x780148fa, 0x780048fa, 0xf847f00d, 0x4afa49f9, 0x78127809, 0xe9cd4011, 
+    0x48f80100, 0x48f87803, 0x40037800, 0x780248f7, 0x780048f7, 0x48f74002, 0x48f77801, 0x40017800, 
+    0xf00d4630, 0x7028f818, 0x28017828, 0x2802d009, 0x2803d007, 0xe006d005, 0x202249f0, 0x8008702c, 
+    0x48efe001, 0x46a87004, 0x780048ee, 0x48ee9000, 0x78037829, 0x780248ed, 0xf7ff4630, 0x782bfdd5, 
+    0xf8df2701, 0x2b0393ac, 0xf889d101, 0x48e97000, 0x28126800, 0x2816d017, 0x48e7d015, 0x94002100, 
+    0x78004632, 0xb2400040, 0xf88af019, 0xfcf7f017, 0x4de248ce, 0x28037800, 0x2801d026, 0xf89ad008, 
+    0xb9e80000, 0x2100e010, 0x20044632, 0xe7eb9400, 0xfa7df017, 0x2100702f, 0x46329400, 0x3000f898, 
+    0xf0194608, 0xe012f86d, 0x780048d5, 0xd00b2802, 0xd0052801, 0x220048d3, 0xf0272101, 0xb118fada, 
+    0xfa65f017, 0xe002702f, 0xfa6ff017, 0xf04f702c, 0x48cd3aff, 0xf0274651, 0x49ccfa9e, 0xf8c12e03, 
+    0xd001a000, 0xe0042000, 0x780048c9, 0x48c9b3f0, 0xf0097800, 0x2701fc4f, 0x7400e9cd, 0x23007828, 
+    0x4619463a, 0xf005b240, 0x2002f825, 0xfab7f00c, 0x4ac248c1, 0x80c749c2, 0x80478087, 0x46478007, 
+    0x3000f898, 0xf84af006, 0xf44f2172, 0xf7fc0080, 0xf8dffcc0, 0x230082f0, 0xf241220c, 0x46400100, 
+    0xfa89f027, 0xf2422300, 0x220d0100, 0xf0274640, 0x2300fa82, 0x0100f244, 0x4640220e, 0xfa7bf027, 
+    0xf2482300, 0x220f0a00, 0xe0004651, 0x4640e013, 0xfa71f027, 0x28037838, 0x48abd00f, 0x220f2301, 
+    0xf0274651, 0x2023fa68, 0xf8b4f007, 0xd01a2e04, 0xd01a2e05, 0x2007e01c, 0x49a0e7ab, 0xf9912080, 
+    0xf82d3001, 0xf9910013, 0xf82d3000, 0xf9910013, 0xf82d0003, 0xf9914010, 0xf82d0002, 0x46684010, 
+    0xff60f005, 0x2008e7df, 0x200de000, 0xf892f007, 0x8258f8df, 0xf8df2000, 0xf8dfb258, 0xf8b8a258, 
+    0xf89b3000, 0xf99a2000, 0xf0061000, 0xf8b8f984, 0x20003000, 0x2000f89b, 0x1000f99a, 0xfe82f006, 
+    0xfbd6f002, 0x78004869, 0xd1042803, 0xb9487828, 0xf0064882, 0x7828fad7, 0x7839b920, 0x1000f240, 
+    0xfbd0f002, 0xf0072001, 0xf8b8f86b, 0xf89b3000, 0xf99a2000, 0x78381000, 0xf95df006, 0x3000f8b8, 
+    0x2000f89b, 0x1000f99a, 0xf0067838, 0x4857fe5b, 0x28037800, 0x7828d104, 0x4870b910, 0xfab2f006, 
+    0x22004868, 0x71fff240, 0xf0271f80, 0x4972fa02, 0x80082200, 0x71fff240, 0x1f004862, 0xf9f9f027, 
+    0x486eb201, 0x461a2300, 0x486b8001, 0x0000f9b0, 0xfffaf004, 0x23022101, 0x22084608, 0xfae0f004, 
+    0x46082140, 0xfab7f004, 0x22152104, 0xf0044608, 0x4855fa97, 0x220c2300, 0x0100f24f, 0xf0271d00, 
+    0x4851f9b3, 0x22082300, 0x7100f640, 0xf0271d00, 0x484df9ab, 0x22042300, 0x1d0021f0, 0xf9a4f027, 
+    0x23004849, 0x461a210f, 0xf0271d00, 0x4845f99d, 0x2200230f, 0x30524619, 0xf9adf027, 0x23004841, 
+    0x21802207, 0xf0273052, 0x483ef9a6, 0x22052300, 0x30522120, 0xf99ff027, 0xf01a2001, 0xf8b8fbad, 
+    0x90000000, 0xf89b2000, 0xf99a3000, 0x78392000, 0xfabbf01a, 0xfa36f01a, 0xf0042000, 0xf004f9e1, 
+    0xf004f9e5, 0x7828f9ff, 0xd10d2801, 0x68004829, 0xd1092810, 0x2200493a, 0xf7fc03c0, 0x2001fbd0, 
+    0xfef0f004, 0xf874f017, 0xff89f002, 0x46307839, 0xfb4af005, 0xfb66f006, 0x23014822, 0x46192200, 
+    0xf027382a, 0x482ff968, 0x20007801, 0xff2df004, 0x2301481c, 0x461a2102, 0xf027381c, 0x2000f95c, 
+    0xf9c2f01a, 0xe04f2300, 0x000322e4, 0x00032270, 0x00032411, 0x0003230b, 0x00032308, 0x0003230c, 
+    0x00032422, 0x0003240d, 0x0003240e, 0x0003240f, 0x00032410, 0x0003240b, 0x0003240c, 0x0003233a, 
+    0x00032333, 0x00032337, 0x00032307, 0x00032306, 0x00032283, 0x0003222c, 0x00032245, 0x00032396, 
+    0x00032237, 0xd0035040, 0xd1800048, 0x000322e8, 0x00032370, 0x00032371, 0x000323cc, 0x000323b4, 
+    0x000323e2, 0xd00305c0, 0xd0030412, 0x000322ac, 0x00032304, 0x00032228, 0x0003239e, 0x000323a0, 
+    0xdeaf0000, 0x0003227f, 0x22014ea0, 0x46302102, 0xf901f027, 0x8278f8df, 0x22012300, 0x46402102, 
+    0xf8f9f027, 0xa26cf8df, 0x22112300, 0x3100f44f, 0xf0274650, 0x2301f8d9, 0x22004650, 0xf0274619, 
+    0x2100f8d3, 0x0000f244, 0xfd0ef003, 0x46502300, 0x461a2101, 0xf8c8f027, 0x46302301, 0x461a2102, 
+    0xf8d9f027, 0x46402301, 0x461a2102, 0xf8d3f027, 0x20042100, 0xfc15f00b, 0xfb0af00b, 0x28007828, 
+    0x2002d07e, 0xfcf5f00b, 0x21864883, 0x43488800, 0xb2002100, 0xfaebf00b, 0xf00b2000, 0x2001fa92, 
+    0xfa8ff00b, 0xf00b2002, 0x2003fa8c, 0xfa89f00b, 0xf9954d7a, 0xf00b0000, 0xf995fa3b, 0xf00b0000, 
+    0x4877facf, 0xf02721c0, 0x4d76f88c, 0x0000f995, 0xf025b280, 0x2001fdb5, 0xff93f005, 0x2000f999, 
+    0x200c2100, 0xfefef005, 0xf00b2000, 0x2001fa63, 0x46039000, 0x46014602, 0xfadcf00b, 0xf0032003, 
+    0x7829fd73, 0x78382200, 0xfc1ff00c, 0x48674966, 0x78007809, 0x0100e9cd, 0x78034865, 0x78024865, 
+    0x78014865, 0x78004865, 0xfcfcf00c, 0xffa2f002, 0xf64f4863, 0xf02771ff, 0x4862f854, 0xb2818800, 
+    0x1c80485f, 0xf84df027, 0x8800485f, 0x485cb281, 0xf0273016, 0x485df846, 0xb2818800, 0x1d004858, 
+    0xf83ff027, 0x21004856, 0xf0273018, 0x4854f83a, 0x301a2100, 0xf835f027, 0x21004851, 0xe000301c, 
+    0xf027e011, 0x484ef82e, 0x301e2100, 0xf829f027, 0x2300484f, 0x21102204, 0xf83df027, 0x7800484d, 
+    0xd0112801, 0x2000e035, 0xfc63f00b, 0x46082100, 0xfa5df00b, 0x0000f999, 0xf00b464d, 0xf995fa02, 
+    0xf00b0000, 0xe780f9b5, 0x48432208, 0x01512300, 0xf821f027, 0x49424841, 0x78004d42, 0x42887809, 
+    0x7028d201, 0x7029e000, 0x4e3f231e, 0x94002100, 0xe9cd2001, 0x782a4601, 0xfac2f01a, 0x9602205e, 
+    0x231e2102, 0x1000e9cd, 0x2100782a, 0xf00b2001, 0x4936f90b, 0x106cf240, 0x48358008, 0x20027004, 
+    0xf811f016, 0x4833b003, 0x210f2300, 0xe8bd461a, 0xf0264ff0, 0xb510bff0, 0xfe0df013, 0xf8abf024, 
+    0xfb35f00d, 0xf8fdf00e, 0xfab3f00e, 0xff1ff00e, 0xfd4af010, 0xfd03f011, 0xf866f012, 0xfc06f012, 
+    0xfbd4f01c, 0xfe1ef01e, 0xfd4ef01c, 0xfceef01d, 0xfa0df022, 0xfb5bf01d, 0xf9c1f022, 0xf81ff024, 
+    0xfcc4f021, 0x4010e8bd, 0xba5cf01b, 0xd0031008, 0xd003000a, 0xd1800000, 0x00032298, 0x00032284, 
+    0xd0030864, 0x0003227e, 0x00032407, 0x00032408, 0x00032413, 0x00032412, 0x00032415, 0x00032414, 
+    0xd003513c, 0x00032cf0, 0x00032d1c, 0x00047f80, 0xd0035250, 0x00032333, 0xd0030480, 0x00032334, 
+    0x00032335, 0x00032336, 0x000323b4, 0x0003239a, 0x00032331, 0xd03c8316, 0xe92d500f, 0xe59f09b8, 
+    0xfb000e59, 0xe3a02103, 0xe3a01030, 0xe3a00010, 0xfbfff0e9, 0xe3a02103, 0xe3a01031, 0xe3a00010, 
+    0xfbfff0e5, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d4070, 0xe3a00003, 0xfa000e2a, 0xe3a00002, 
+    0xfa000e28, 0xe3a00001, 0xfa000e26, 0xe3a00011, 0xfa000e24, 0xe3a00012, 0xfa000e22, 0xe3a00001, 
+    0xfb000d94, 0xe3a00002, 0xfb000d92, 0xe3a00004, 0xfb000d90, 0xe59f0944, 0xfb000e3b, 0xe59f0940, 
+    0xe3a03001, 0xe3a0200c, 0xe3011000, 0xfb009ba0, 0xe59f0930, 0xe1d000d0, 0xe3700001, 0x0a00000f, 
+    0xe3a02000, 0xe3a01007, 0xe1a00002, 0xfb001635, 0xe59f1914, 0xe3a00001, 0xe59f2914, 0xe1c100b6, 
+    0xe1c100b4, 0xe1c100b2, 0xe1c100b0, 0xe59f08fc, 0xe59f1900, 0xe5d03000, 0xe59f08ec, 0xfa001666, 
+    0xe59f18f4, 0xe3a00000, 0xe59f58f0, 0xe3a02000, 0xe5c10000, 0xe3a0000f, 0xe1c500b0, 0xe2851000, 
+    0xe59f08dc, 0xe5900000, 0xfa0089b0, 0xe59f48d4, 0xe3a02000, 0xe5941000, 0xe0800001, 0xe5840000, 
+    0xe59f08c4, 0xe2851000, 0xe5900000, 0xfa0089a7, 0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 
+    0xe59f08a8, 0xe2851000, 0xe5900000, 0xfa00899f, 0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 
+    0xe59f088c, 0xe2851000, 0xe5900000, 0xfa008997, 0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 
+    0xe59f0870, 0xe2851000, 0xe5900000, 0xfa00898f, 0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 
+    0xe59f0854, 0xe2851000, 0xe5900000, 0xfa008987, 0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 
+    0xe59f0838, 0xe2851000, 0xe5900000, 0xfa00897f, 0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 
+    0xe59f081c, 0xe2851000, 0xe5900000, 0xfa008977, 0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 
+    0xe59f0800, 0xe2851000, 0xe5900000, 0xfa00896f, 0xe5941000, 0xe3a02000, 0xe0800001, 0xe5840000, 
+    0xe3a00007, 0xe1c500b0, 0xe59f07dc, 0xe2851000, 0xe5900000, 0xfa008965, 0xe5941000, 0xe0800001, 
+    0xe5840000, 0xe8bd8070, 0xe1a01000, 0xe59f07bc, 0xe92d4010, 0xe1d000b0, 0xe3500000, 0x13a02103, 
+    0x13011101, 0x1a00001e, 0xe59f27a4, 0xe59f07a4, 0xe59f47a4, 0xe1510002, 0x1a000005, 0xe3a02004, 
+    0xe3a01010, 0xfb009b29, 0xe20000ff, 0xe3a01011, 0xea00000d, 0xe59f2784, 0xe1510002, 0x1a000005, 
+    0xe3a02005, 0xe3a01020, 0xfb009b20, 0xe20000ff, 0xe3a01012, 0xea000004, 0xe3a02003, 0xe3a01008, 
+    0xfb009b1a, 0xe20000ff, 0xe3a01001, 0xe3500001, 0xe1c410b2, 0x0a000005, 0xebffff54, 0xe3a02103, 
+    0xe3a01001, 0xe8bd4010, 0xe3a00010, 0xeafff001, 0xe3a02103, 0xe3001101, 0xe3a00010, 0xfbfff02e, 
+    0xe1d400f2, 0xe3a02103, 0xe2801090, 0xe3a00010, 0xfbfff029, 0xe59f170c, 0xe3a02103, 0xe59f0700, 
+    0xe5d11000, 0xe5d00000, 0xe0800081, 0xe2801c02, 0xe3a00010, 0xfbfff020, 0xe3a00005, 0xe1c400b0, 
+    0xe59f06c4, 0xe3a02000, 0xe59f16cc, 0xe5900000, 0xfa00891e, 0xe59f168c, 0xe5912000, 0xe0800002, 
+    0xe5810000, 0xe3a00004, 0xfb000cd2, 0xe8bd4010, 0xe3a0000b, 0xea000d46, 0xe92d503f, 0xe59f463c, 
+    0xe1a00004, 0xfb000d78, 0xe3a02103, 0xe3a01032, 0xe3a00010, 0xfbfff008, 0xe1a00004, 0xebffffa9, 
+    0xe3a02103, 0xe3a01033, 0xe3a00010, 0xfbfff002, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d50ff, 
+    0xe59f0664, 0xfb000d68, 0xe3a02103, 0xe3a01034, 0xe3a00010, 0xfbffeff8, 0xe3a00002, 0xfa000d41, 
+    0xe59f0648, 0xe3a03000, 0xe3a02008, 0xe3001100, 0xfb009ac7, 0xe59f0614, 0xe1d000b0, 0xe3500000, 
+    0x13a02103, 0x13011102, 0x1a00003d, 0xe59f0620, 0xe3a07000, 0xe59f561c, 0xe59f45c8, 0xe5d00000, 
+    0xe3500000, 0x0a000023, 0xe59f060c, 0xe59f160c, 0xe59f660c, 0xe1d000d0, 0xe1d110d0, 0xe1800001, 
+    0xe1d610d0, 0xe1900001, 0x1a00002f, 0xe3a00005, 0xfa000ca0, 0xe59f15ec, 0xe240093d, 0xe2400d09, 
+    0xe3a02000, 0xe5810000, 0xe3a00001, 0xe5c60000, 0xe3a0003e, 0xe1c500b0, 0xe2851000, 0xe59f0560, 
+    0xe5900000, 0xfa0088d1, 0xe5941000, 0xe0800001, 0xe5840000, 0xe59f05b0, 0xe59f15b0, 0xe5d00000, 
+    0xe2800001, 0xe2000007, 0xe0800200, 0xe0810100, 0xe5807008, 0xea000014, 0xe59f0594, 0xe5900000, 
+    0xe3500000, 0x0a000000, 0xeafffffe, 0xe59f0508, 0xe3a02000, 0xe59f155c, 0xe5c07000, 0xe3a00009, 
+    0xe1c500b0, 0xe59f0520, 0xe5900000, 0xfa0088b7, 0xe5941000, 0xe3a02103, 0xe0800001, 0xe3a01002, 
+    0xe5840000, 0xe3a00010, 0xfbffefab, 0xe3a02103, 0xe3a01035, 0xe3a00010, 0xfbffefa7, 0xf57ff05f, 
+    0xe8bd50ff, 0xe25ef004, 0xe92d503f, 0xe59f0524, 0xfb000d0d, 0xe3a02103, 0xe3a01036, 0xe3a00010, 
+    0xfbffef9d, 0xe59f04c4, 0xe1d000b0, 0xe3500000, 0x0a00000a, 0xe3a02103, 0xe3011103, 0xe3a00010, 
+    0xfbffef95, 0xe3a02103, 0xe3a01037, 0xe3a00010, 0xfbffef91, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 
+    0xe59f04ac, 0xe5d00000, 0xe3500000, 0x0afffff4, 0xe59f04a4, 0xe59f24a4, 0xe1d010d0, 0xe1d220d0, 
+    0xe1911002, 0x1affffee, 0xe3a04001, 0xe5c04000, 0xe59f04a4, 0xe3a03000, 0xe1a02004, 0xe3a01002, 
+    0xfb009a53, 0xe3a00000, 0xfa000e9d, 0xe59f048c, 0xe5d00000, 0xe3500000, 0x1a000003, 0xe3a00802, 
+    0xe3001803, 0xfbffef4d, 0xfb002b22, 0xe3a00001, 0xfa0074ff, 0xe59f0450, 0xe59f1450, 0xe5d00000, 
+    0xe2800001, 0xe2000007, 0xe0800200, 0xe0810100, 0xe5804008, 0xe3a00005, 0xfa000c2e, 0xe59f1424, 
+    0xe240093d, 0xe2400d09, 0xe5810000, 0xe3a00000, 0xe59f13a4, 0xe5c10000, 0xe3a00002, 0xfa000ca9, 
+    0xe3a00003, 0xfa000ca7, 0xe59f03e0, 0xe3a03000, 0xe3a02008, 0xe3001100, 0xfb009a2d, 0xe3a02007, 
+    0xe3a01000, 0xe3a00001, 0xfb00163a, 0xe59f13f0, 0xe3a00043, 0xe3a02000, 0xe1c100b0, 0xe59f0360, 
+    0xe5900000, 0xfa008851, 0xe59f1358, 0xe5912000, 0xe0800002, 0xe5810000, 0xeaffffb1, 0xe92d5fff, 
+    0xe3a02103, 0xe3a01038, 0xe3a00010, 0xfbffef42, 0xe59f03b0, 0xe3a0200e, 0xe3041000, 0xfb009a1b, 
+    0xe59f43a4, 0xe3500000, 0xe59fb3a0, 0x13a00000, 0x1a000003, 0xe3a0200e, 0xe3041000, 0xe1a00004, 
+    0xfb009a12, 0xe5cb0000, 0xe59f0384, 0xfa0099fa, 0xe1a08000, 0xe3a0200c, 0xe3011000, 0xe1a00004, 
+    0xfb009a0a, 0xe59f936c, 0xe5c90000, 0xe59f0368, 0xfa0099f1, 0xe6bf6070, 0xe59f0360, 0xfa0099ee, 
+    0xe6bf4070, 0xe3140080, 0x159f1354, 0x13a00001, 0x15c10000, 0xe59f034c, 0xfa0099e7, 0xe6bf5070, 
+    0xe59f0344, 0xfa0099e4, 0xe6bf7070, 0xe3a02000, 0xe1a01004, 0xe3a00001, 0xfbffef17, 0xe3a02000, 
+    0xe1a01005, 0xe3a00001, 0xfbffef13, 0xe3a02000, 0xe1a01006, 0xe3a00001, 0xfbffef0f, 0xe59f030c, 
+    0xe5d00000, 0xe3500001, 0x1a00000d, 0xe3140004, 0x0a00000b, 0xe59fa2f8, 0xe3a02006, 0xe30011c0, 
+    0xe1a0000a, 0xfb0099e1, 0xe3500003, 0x1a000004, 0xe3a03006, 0xe30011c0, 0xe1a02003, 0xe1a0000a, 
+    0xfb0099d3, 0xe59fa244, 0xe5da0000, 0xe3100018, 0x0a000006, 0xe3e00000, 0xfa002c99, 0xe59f22b4, 
+    0xe3041004, 0xe3a00004, 0xfbffeef3, 0xea000042, 0xe5db1000, 0xe3a02000, 0xe3a00001, 0xfbffeeee, 
+    0xe5db1000, 0xe2043010, 0xe1da00b0, 0xe3510000, 0x13800080, 0x03c00080, 0xe1ca00b0, 0xe3150b01, 
+    0x13510000, 0xe2050c01, 0x03a02000, 0x13a02001, 0xe1933000, 0x13160010, 0x0a000003, 0xe5d93000, 
+    0xe3530000, 0x03a03001, 0x0a000000, 0xe3a03000, 0xe204c020, 0xe190000c, 0x13160020, 0x0a000003, 
+    0xe5d90000, 0xe3500000, 0x03a00001, 0x0a000000, 0xe3a00000, 0xe3520000, 0x1a000005, 0xe59f2218, 
+    0xe1d220d0, 0xe1911002, 0x1a000007, 0xe1900003, 0x0a000005, 0xe59f0204, 0xe1d010d0, 0xe3510003, 
+    0x13510004, 0x13510005, 0x0bfffde0, 0xe3180003, 0x0a000011, 0xe3e00000, 0xfa002c61, 0xe59f01e0, 
+    0xe3a0106d, 0xe3a02000, 0xe1c040b2, 0xe1c060b4, 0xe1c050b6, 0xe1c070b8, 0xe1c010b0, 0xe2801000, 
+    0xe59f01c0, 0xe5900000, 0xfa0087b8, 0xe59f10f4, 0xe5912000, 0xe0800002, 0xe5810000, 0xe3a02103, 
+    0xe3a01039, 0xe3a00010, 0xfbffeeab, 0xe59f0198, 0xfb000c15, 0xf57ff05f, 0xe8bd5fff, 0xe25ef004, 
+    0xe92d500f, 0xe59f0184, 0xfb000c0f, 0xe3a02103, 0xe3a0103a, 0xe3a00010, 0xfbffee9f, 0xe3a02103, 
+    0xe3a0103b, 0xe3a00010, 0xfbffee9b, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0150, 
+    0xfb000c01, 0xe3a02103, 0xe3a0103c, 0xe3a00010, 0xfbffee91, 0xe59f113c, 0xe3a00008, 0xe3a02000, 
+    0xe1c100b0, 0xe59f0080, 0xe5900000, 0xfa00878f, 0xe59f1050, 0xe5912000, 0xe0800002, 0xe5810000, 
+    0xe3a02103, 0xe3a0103d, 0xe3a00010, 0xfbffee82, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xc1000104, 
+    0xc1000114, 0xd003902c, 0x0003229e, 0x000323cc, 0x00032411, 0x000323b4, 0x000323e2, 0x000322c2, 
+    0x0003248c, 0x00032d0c, 0x00032230, 0x000324d8, 0x000324e8, 0x000324f8, 0x00032508, 0x00032520, 
+    0x00032534, 0x00032544, 0x00032554, 0x00032564, 0x0003227c, 0xc1000214, 0xd0035040, 0x00032494, 
+    0xc1000224, 0x0003230c, 0x00032422, 0xc1000124, 0xd0035126, 0x00032cd4, 0x00032444, 0x000322c1, 
+    0x00032cd7, 0x00032cd8, 0x000322a8, 0x00032cf0, 0x0003ab8c, 0x00047f70, 0xc1000134, 0xd0035114, 
+    0x00032396, 0x0003244c, 0xd0060000, 0xd28fffc0, 0x00032279, 0xd0039048, 0x00032278, 0xd0039026, 
+    0xd0039028, 0x0003227a, 0xd0039018, 0xd0039016, 0x00032362, 0xd0039034, 0xcccc0000, 0x00032271, 
+    0x0003227e, 0x0003fe88, 0x00032f54, 0xc1000144, 0xc1000154, 0xc1000164, 0x00032454, 0xe92d500f, 
+    0xe59f0cc8, 0xfb000ba8, 0xe3a02103, 0xe3a0103e, 0xe3a00010, 0xfbffee38, 0xebfffd54, 0xe3a02103, 
+    0xe3a01007, 0xe3a00402, 0xfbffee33, 0xe3a02103, 0xe3a0103f, 0xe3a00010, 0xfbffee2f, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0c80, 0xfb000b95, 0xe3a02103, 0xe3a01040, 0xe3a00010, 
+    0xfbffee25, 0xe3a02103, 0xe3a01041, 0xe3a00010, 0xfbffee21, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d50ff, 0xe59f0c4c, 0xfb000b87, 0xe59f0c48, 0xfa0098e1, 0xe3500000, 0x0a00001c, 0xe59f4c3c, 
+    0xe3a01001, 0xe1a00004, 0xfb0098dc, 0xe284000c, 0xe3a01000, 0xfb0098d9, 0xe30b1bbb, 0xe1a00004, 
+    0xfb0098d6, 0xe59f4c18, 0xe3a00062, 0xe1c400b0, 0xe59f0c10, 0xfa0098d0, 0xe1c400b2, 0xe2841000, 
+    0xe59f0c04, 0xe3a02000, 0xe5900000, 0xfa008707, 0xe51f11d0, 0xe5912000, 0xe0800002, 0xe5810000, 
+    0xe59f0be8, 0xe30f1fff, 0xfb0098c4, 0xea00003e, 0xe59f0bdc, 0xfa0098c0, 0xe3500000, 0x0a00003a, 
+    0xe59f6bd0, 0xe1a00006, 0xfa0098bb, 0xe51f122c, 0xe1b007a0, 0xe51f41ec, 0xe2865074, 0xe5c10000, 
+    0x0a00002b, 0xe3a03000, 0xe3a0200f, 0xe3081000, 0xe1a00006, 0xfb0098be, 0xe3a03001, 0xe3a0200b, 
+    0xe3001800, 0xe1a00006, 0xfb0098b9, 0xe59f0b88, 0xe5d00000, 0xe3500000, 0x1a000013, 0xe1a00006, 
+    0xfa0098a5, 0xe59f1b74, 0xe7e006d0, 0xe5c10000, 0xe1a00006, 0xfa0098a0, 0xe59f1b64, 0xe7e00550, 
+    0xe5c10000, 0xe1a00006, 0xfa00989b, 0xe59f1b54, 0xe7e203d0, 0xe5c10000, 0xe1a00006, 0xfa009896, 
+    0xe59f1b44, 0xe7e102d0, 0xe5c10000, 0xe3081000, 0xe1a00005, 0xfb009891, 0xe1d400b0, 0xe3800010, 
+    0xe1c400b0, 0xe3a00004, 0xfa000b0e, 0xebfffcdf, 0xea000005, 0xe30f1fff, 0xe1a00005, 0xfb009887, 
+    0xe1d400b0, 0xe3c00010, 0xe1c400b0, 0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xe92d500f, 0xe59f0aec, 
+    0xfb000b21, 0xe3a02103, 0xe3a01085, 0xe3a00010, 0xfbffedb1, 0xe3a0000a, 0xfa000afa, 0xe59f0ad0, 
+    0xe3a03000, 0xe3a0200a, 0xe3001400, 0xfa009875, 0xe59f0ac0, 0xe3a03000, 0xe3a0200a, 0xe3001400, 
+    0xfa009870, 0xebfffcc1, 0xe3a02103, 0xe3a01086, 0xe3a00010, 0xfbffeda0, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d503f, 0xe59f0a8c, 0xfb000b06, 0xe59f4a88, 0xe5d40000, 0xe3500001, 0x0a000002, 
+    0xe3500002, 0x0a00001e, 0xea00002a, 0xe3a02103, 0xe3a01042, 0xe3a00010, 0xfbffed8f, 0xe51f0374, 
+    0xe1d000b0, 0xe3500000, 0x0a000008, 0xe3a02103, 0xe3001176, 0xe3a00010, 0xfbffed87, 0xe3a02103, 
+    0xe3a01043, 0xe3a00010, 0xfbffed83, 0xea000019, 0xe59f0a2c, 0xfa009848, 0xe1a01000, 0xe3a02000, 
+    0xe3a00010, 0xfbffed7c, 0xe3a03001, 0xe59f0a14, 0xe3a02000, 0xe1a01003, 0xfb00984d, 0xebfffc93, 
+    0xeaffffed, 0xe3a00001, 0xfa001793, 0xe51f5398, 0xe3a03001, 0xe3a02000, 0xe1a01003, 0xe1a00005, 
+    0xfb009843, 0xe3a03001, 0xe3a01002, 0xe1a02003, 0xe1a00005, 0xfb00983e, 0xe59f09cc, 0xe1d000d0, 
+    0xe3500003, 0x13500005, 0x13500004, 0x059f09bc, 0x05d00000, 0x03500001, 0x0a000006, 0xe3a00000, 
+    0xe5c40000, 0xe3a0000b, 0xfa000aa6, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe5d40000, 0xe3500003, 
+    0x13500002, 0x051f1490, 0x03a00001, 0x05c10000, 0xeafffff1, 0xe92d500f, 0xe59f0974, 0xfb000aba, 
+    0xe3a02103, 0xe3a01087, 0xe3a00010, 0xfbffed4a, 0xe3a0000c, 0xfa000a93, 0xe59f0934, 0xe3a03000, 
+    0xe3a0200c, 0xe3011000, 0xfa00980e, 0xe59f0924, 0xe3a03000, 0xe3a0200c, 0xe3011000, 0xfa009809, 
+    0xebfffc5a, 0xe3a02103, 0xe3a01088, 0xe3a00010, 0xfbffed39, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f090c, 0xfb000a9f, 0xe3a02103, 0xe3a01044, 0xe3a00010, 0xfbffed2f, 0xe3a02103, 
+    0xe3a01045, 0xe3a00010, 0xfbffed2b, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe59f08d8, 
+    0xe3a01001, 0xfb0097ed, 0xe3a02103, 0xe3a0107f, 0xe3a00010, 0xfbffed20, 0xe59f48c0, 0xe3a0006f, 
+    0xe1c400b0, 0xe59f08b8, 0xfa0097e3, 0xe1a05000, 0xe59f08b0, 0xfa0097e0, 0xe0850800, 0xe5840004, 
+    0xe3a00001, 0xfa008c52, 0xe59f089c, 0xe2841000, 0xe3a02000, 0xe5900000, 0xfa008614, 0xe51f159c, 
+    0xe5912000, 0xe0800002, 0xe5810000, 0xe59f087c, 0xfb000a75, 0xe3a02103, 0xe3a01080, 0xe3a00010, 
+    0xfbffed05, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d500f, 0xe59f0858, 0xfb000a6b, 0xe3a02103, 
+    0xe3a0104a, 0xe3a00010, 0xfbffecfb, 0xe3a02103, 0xe3a0104b, 0xe3a00010, 0xfbffecf7, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0824, 0xfb000a5d, 0xe3a02103, 0xe3a01083, 0xe3a00010, 
+    0xfbffeced, 0xe3a02103, 0xe3a01084, 0xe3a00010, 0xfbffece9, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d503f, 0xe51f4618, 0xe1a00004, 0xfb000a4e, 0xe3a02103, 0xe3a01023, 0xe3a00010, 0xfbffecde, 
+    0xe1a00004, 0xebfffc7f, 0xe3a02103, 0xe3a01024, 0xe3a00010, 0xfbffecd8, 0xf57ff05f, 0xe8bd503f, 
+    0xe25ef004, 0xe92d503f, 0xe51f4650, 0xe1a00004, 0xfb000a3d, 0xe3a02103, 0xe3a01025, 0xe3a00010, 
+    0xfbffeccd, 0xe1a00004, 0xebfffc6e, 0xe3a02103, 0xe3a01026, 0xe3a00010, 0xfbffecc7, 0xf57ff05f, 
+    0xe8bd503f, 0xe25ef004, 0xe92d500f, 0xe59f0768, 0xfb000a2d, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f0754, 0xfb000a27, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0740, 
+    0xfb000a21, 0xe3a02103, 0xe3a01085, 0xe3a00010, 0xfbffecb1, 0xe3a02103, 0xe3a01086, 0xe3a00010, 
+    0xfbffecad, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f070c, 0xfb000a13, 0xe3a02103, 
+    0xe3a01058, 0xe3a00010, 0xfbffeca3, 0xe3a02103, 0xe3a01059, 0xe3a00010, 0xfbffec9f, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe59f06d8, 0xfb000a05, 0xe3a02103, 0xe3a0105e, 0xe3a00010, 
+    0xfbffec95, 0xe59f06c4, 0xfa009758, 0xe59f46c0, 0xe584000c, 0xe59f06bc, 0xfa009754, 0xe6ff2070, 
+    0xe1c420b6, 0xe594000c, 0xe1b01fa0, 0xe5c41002, 0x1a000057, 0xe7e11d50, 0xe5c41000, 0xe7e41850, 
+    0xe5c41001, 0xe1a01800, 0xe1c400b8, 0xe3a00010, 0xfbffec81, 0xe1d400d0, 0xe3500001, 0x0a000004, 
+    0xe3500003, 0x05d40001, 0x03500001, 0x0a000039, 0xea000047, 0xe1d410d1, 0xe3510007, 0x1a000024, 
+    0xe1d420f8, 0xe30f3ff8, 0xe6ff0072, 0xe1500003, 0x1309302a, 0x11500003, 0x1a00000f, 0xe1d400b6, 
+    0xe3a01007, 0xe1d11000, 0x0a000039, 0xe2001027, 0xe59f0624, 0xe3510022, 0x03a03001, 0x0a000002, 
+    0xe3510002, 0x03a03000, 0x1a000031, 0xe3a0200f, 0xe3081000, 0xfb009736, 0xea00002d, 0xe30f3fe0, 
+    0xe1500003, 0x1a000007, 0xe1d400b6, 0xe3100902, 0x0a000027, 0xe59f05e4, 0xe3a03001, 0xe3a02002, 
+    0xe3a01004, 0xeafffff2, 0xe1a00802, 0xe1b00820, 0x0a000002, 0xe351001e, 0x1a00001d, 0xea000004, 
+    0xe1d400b6, 0xe3100902, 0x13a00001, 0x1b009af3, 0xea000017, 0xe1d400b8, 0xe3041191, 0xe6ff0070, 
+    0xe1500001, 0x1a000012, 0xe5d40006, 0xe3100001, 0x0a00000f, 0xeafffffe, 0xe1d400b8, 0xe3a01001, 
+    0xe59f257c, 0xe6ff0070, 0xe3500089, 0x05c21000, 0x0a000007, 0xe350008a, 0x05c21001, 0x0a000004, 
+    0xe350008b, 0x05c21002, 0x0a000001, 0xe350008c, 0x05c21003, 0xe3a02103, 0xe3a0105f, 0xe3a00010, 
+    0xfbffec2d, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe92d500f, 0xe3a02103, 0xe3a01060, 0xe3a00010, 
+    0xfbffec25, 0xe59f051c, 0xe3a0107f, 0xfb0096eb, 0xe59f0514, 0xe3a01003, 0xfb0096e8, 0xe59f050c, 
+    0xfb000989, 0xe51f08d4, 0xe5d00000, 0xe3500001, 0x051f0948, 0x01d000b0, 0x03d00040, 0x1a00000a, 
+    0xe59f14ec, 0xe3a00074, 0xe3a02000, 0xe1c100b0, 0xe51f096c, 0xe5900000, 0xfa008514, 0xe51f199c, 
+    0xe5912000, 0xe0800002, 0xe5810000, 0xe3a02103, 0xe3a01061, 0xe3a00010, 0xfbffec07, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe3a02103, 0xe3a0107c, 0xe3a00010, 0xfbffebff, 0xfa001320, 
+    0xe59f0490, 0xfb000968, 0xe3a01001, 0xe3a00008, 0xfa0012ff, 0xe3a00000, 0xfb001325, 0xe3a0001e, 
+    0xfa000940, 0xe3a0001f, 0xfa00093e, 0xebfffb0f, 0xe3a02103, 0xe3a0107d, 0xe3a00010, 0xfbffebee, 
+    0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0444, 0xfb000954, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f0430, 0xfb00094e, 0xe3a0001f, 0xfb000933, 0xe59f1424, 0xe21000ff, 
+    0xe5c10000, 0x1a000004, 0xe59f0418, 0xe3a03000, 0xe3a0200a, 0xe3001400, 0xfb0096ad, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f03f8, 0xfb00093d, 0xe3a02103, 0xe3a0106a, 0xe3a00010, 
+    0xfbffebcd, 0xe3a02103, 0xe3a0106b, 0xe3a00010, 0xfbffebc9, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d503f, 0xe59f03c4, 0xfb00092f, 0xe3a02103, 0xe3a0104c, 0xe3a00010, 0xfbffebbf, 0xe3a00021, 
+    0xfb000910, 0xe59f13a8, 0xe6af0070, 0xe51f4ac4, 0xe3500000, 0xe5c10000, 0xe1d400b0, 0x0a00001a, 
+    0xe3500000, 0x0a00001e, 0xe59f1388, 0xe3a00023, 0xe3a02000, 0xe1c100b0, 0xe51f0af4, 0xe5900000, 
+    0xfa0084b2, 0xe51f1b24, 0xe5912000, 0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3001110, 
+    0xe3800002, 0xe1c400b0, 0xe3a00010, 0xfbffeba2, 0xe3a02103, 0xe3a0104d, 0xe3a00010, 0xfbffeb9e, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3d00002, 0xe1c400b0, 0x0bfffab5, 0xe3a02103, 0xe3a01010, 
+    0xeafffff0, 0xebfffab1, 0xeaffffe9, 0xe92d503f, 0xe59f0304, 0xfb0008fc, 0xe3a02103, 0xe3a01068, 
+    0xe3a00010, 0xfbffeb8c, 0xe51f0b28, 0xe3a0200e, 0xe3041000, 0xfb009665, 0xe51f4b04, 0xe3500000, 
+    0x13a00022, 0x1b009a2f, 0xe5c40000, 0xe31000ff, 0xe51f4ba8, 0xe1d400b0, 0x0a00001a, 0xe3500000, 
+    0x0a000022, 0xe59f12b4, 0xe3a00022, 0xe3a02000, 0xe1c100b0, 0xe51f0bd0, 0xe5900000, 0xfa00847b, 
+    0xe51f1c00, 0xe5912000, 0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3001111, 0xe3800001, 
+    0xe1c400b0, 0xe3a00201, 0xfbffeb6b, 0xe3a02103, 0xe3a01069, 0xe3a00010, 0xfbffeb67, 0xf57ff05f, 
+    0xe8bd503f, 0xe25ef004, 0xe3c00001, 0xe3a01011, 0xe3a02103, 0xe1c400b0, 0xe3a00201, 0xfbffeb5e, 
+    0xe1d400b0, 0xe3500000, 0x0bfffa78, 0xeaffffee, 0xebfffa76, 0xeaffffe5, 0xe92d500f, 0xe59f0220, 
+    0xfb0008c1, 0xe3a02103, 0xe3a01052, 0xe3a00010, 0xfbffeb51, 0xe3a02103, 0xe3a01053, 0xe3a00010, 
+    0xfbffeb4d, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d50ff, 0xe3a02103, 0xe3a0105a, 0xe3a00010, 
+    0xfbffeb45, 0xe59f01dc, 0xfb0008af, 0xe59f61d8, 0xe3a03001, 0xe1a02003, 0xe3a01002, 0xe1a00006, 
+    0xfb009613, 0xe59f51c4, 0xe3a00001, 0xe5c50000, 0xfb0054ce, 0xe59f01b8, 0xe3a02000, 0xe1d010b0, 
+    0xe3a00010, 0xfbffeb34, 0xe59f01a8, 0xe3a02005, 0xe51f4ce8, 0xe3a01020, 0xe5d00000, 0xe3500000, 
+    0xe1d400b0, 0x03a03000, 0x13a03001, 0x03c00020, 0x13800020, 0xe1c400b0, 0xe59f017c, 0xfb0095fc, 
+    0xe59f0178, 0xe5d00000, 0xe3500000, 0xe1d400b0, 0x03c00040, 0x13800040, 0xe1c400b0, 0xe6ff0070, 
+    0xe3d00060, 0x0a000056, 0xe3a02103, 0xe3a01022, 0xe3a00010, 0xfbffeb18, 0xe3a03000, 0xe3a02001, 
+    0xe3a01002, 0xe1a00006, 0xfb0095e9, 0xe3a00000, 0xe5c50000, 0xe3a02103, 0xe3a0105b, 0xe3a00010, 
+    0xfbffeb0d, 0xf57ff05f, 0xe8bd50ff, 0xe25ef004, 0xc1000174, 0xc1000184, 0xc1000194, 0xd03c8082, 
+    0xd03c806e, 0x0003245c, 0xd03c800a, 0x00032cc8, 0xd03c807e, 0xd03c8084, 0xd03c800c, 0x0003229f, 
+    0x000323dc, 0x000323dd, 0x000323de, 0x000323df, 0xc10001a4, 0xc1000030, 0xc1000034, 0xc10001b4, 
+    0x0003240a, 0xd28f0004, 0xd28f20e0, 0x00032238, 0x000323fc, 0xc10001c4, 0xc10001d4, 0xd03d101a, 
+    0x0003fe98, 0xd03d1028, 0xd03d102a, 0x0003302c, 0xc10001e4, 0xc10001f4, 0xc1000204, 0xc1000234, 
+    0xc1000244, 0xc1000254, 0xc1000274, 0xc10002a4, 0xd1800288, 0x00032434, 0xd180028c, 0xd03c8034, 
+    0xd03c830c, 0x0003238a, 0xd2154124, 0xd03d104e, 0xc10002b4, 0x00032464, 0xc10002c4, 0xc10002e4, 
+    0xc10002f4, 0x000322be, 0xd00350f6, 0xc1000304, 0xc1000314, 0x00032276, 0x0003246c, 0xc1000324, 
+    0x00032474, 0xc1000334, 0xc1000344, 0xd03c801c, 0x000323c2, 0x000323c0, 0x000323bf, 0xd28f2054, 
+    0x000323bd, 0xebfff9e1, 0xeaffffb1, 0xe92d503f, 0xe59f04a4, 0xfb00082c, 0xe3a02103, 0xe3a0104e, 
+    0xe3a00010, 0xfbffeabc, 0xe59f0490, 0xfa009582, 0xe59f148c, 0xe200001f, 0xe1c100b0, 0xe59f1484, 
+    0xe1d120f0, 0xe1500002, 0x0a000018, 0xe51f4ee4, 0xe3500000, 0xe1c100b0, 0xe1d400b0, 0x0a00001a, 
+    0xe3500000, 0x0a000022, 0xe59f145c, 0xe3a00021, 0xe3a02000, 0xe1c100b0, 0xe51f0f14, 0xe5900000, 
+    0xfa0083aa, 0xe51f1f44, 0xe5912000, 0xe0800002, 0xe5810000, 0xe1d400b0, 0xe3a02103, 0xe3a01012, 
+    0xe3800004, 0xe1c400b0, 0xe3a00201, 0xfbffea9a, 0xe3a02103, 0xe3a0104f, 0xe3a00010, 0xfbffea96, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3c00004, 0xe3001112, 0xe3a02103, 0xe1c400b0, 0xe3a00201, 
+    0xfbffea8d, 0xe1d400b0, 0xe3500000, 0x0bfff9a7, 0xeaffffee, 0xebfff9a5, 0xeaffffe5, 0xe92d5fff, 
+    0xe59f03c8, 0xfb0007f0, 0xe3a02103, 0xe3a01050, 0xe3a00010, 0xfbffea80, 0xe59f43b4, 0xe1a00004, 
+    0xfa009545, 0xe59f63ac, 0xe1a006a0, 0xe5c60000, 0xe1a00004, 0xfa009540, 0xe59f739c, 0xe7e22550, 
+    0xe51f51b4, 0xe51f4fdc, 0xe5c72000, 0xe5d51003, 0xe5d60000, 0xe1510000, 0x1a000004, 0xe3500004, 
+    0x1a000023, 0xe5d53004, 0xe1530002, 0x0a000025, 0xe59f9368, 0xe3510000, 0xe59f8364, 0x03500007, 
+    0x0a00002a, 0xe59fa35c, 0xe3a03000, 0xe3a0200c, 0xe3011000, 0xe1a0000a, 0xfb009535, 0xe3a03000, 
+    0xe3a0200b, 0xe3001800, 0xe1a0000a, 0xfb009530, 0xe1d400b0, 0xe3d00008, 0x0a000022, 0xe3a00006, 
+    0xe1c900b0, 0xe59f1314, 0xe3a02000, 0xe59f0318, 0xe5900000, 0xfa008355, 0xe5981000, 0xe0800001, 
+    0xe5880000, 0xe5d60000, 0xe5c50003, 0xe5d70000, 0xe5c50004, 0xe5d60000, 0xe3500000, 0x01d400b0, 
+    0x03c00008, 0x0a000001, 0xe1d400b0, 0xe3800008, 0xe3a01051, 0xe3a02103, 0xe1c400b0, 0xe3a00010, 
+    0xfbffea3d, 0xf57ff05f, 0xe8bd5fff, 0xe25ef004, 0xe3a0006e, 0xe1c900b0, 0xe59f12a0, 0xe3a02000, 
+    0xe59f02a8, 0xeaffffe1, 0xebfff950, 0xeaffffe4, 0xe92d500f, 0xe59f0298, 0xfb00079b, 0xe3a02103, 
+    0xe3a01074, 0xe3a00010, 0xfbffea2b, 0xe3a02103, 0xe3a01075, 0xe3a00010, 0xfbffea27, 0xf57ff05f, 
+    0xe8bd500f, 0xe25ef004, 0xe92d500f, 0xe59f0264, 0xfb00078d, 0xe3a02103, 0xe3a0106c, 0xe3a00010, 
+    0xfbffea1d, 0xe3a02103, 0xe3a0106d, 0xe3a00010, 0xfbffea19, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 
+    0xe92d500f, 0xe59f0230, 0xfb00077f, 0xe3a02103, 0xe3a01046, 0xe3a00010, 0xfbffea0f, 0xe3a02103, 
+    0xe3a01047, 0xe3a00010, 0xfbffea0b, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xe92d503f, 0xe3a02103, 
+    0xe3a01081, 0xe3a00010, 0xfbffea03, 0xe59f01ec, 0xe3a04000, 0xe59f21f0, 0xe1d010b0, 0xe3510001, 
+    0x03a01002, 0x01c010b0, 0xe59f01d4, 0xe59f11dc, 0xe1c040b6, 0xe1c040b4, 0xe1c040b2, 0xe1c040b0, 
+    0xe59f01c0, 0xe5d03000, 0xe59f01b4, 0xfa000fa2, 0xe3a00001, 0xfa001d88, 0xe3a01000, 0xe3a00040, 
+    0xfa0006d8, 0xe3a00000, 0xfa001d83, 0xe59f01a0, 0xe3a0100f, 0xfb0094b1, 0xe59f0198, 0xfb000752, 
+    0xe59f0194, 0xe1d000d0, 0xe3500003, 0x13500005, 0x13500004, 0x1a000019, 0xe59f0180, 0xe59f5184, 
+    0xe5901000, 0xe2811001, 0xe5801000, 0xe59f0170, 0xe5d00000, 0xe3500000, 0x0a000017, 0xe3a00501, 
+    0xe3a01071, 0xfbffe9c1, 0xe1d500b0, 0xe3500014, 0x9a00000a, 0xe3a02103, 0xe3a01081, 0xe3a00010, 
+    0xfbffe9cd, 0xe3a03000, 0xe59f013c, 0xe1a02003, 0xe3a01001, 0xfb00949e, 0xe1c540b0, 0xebfff8e3, 
+    0xe3a02103, 0xe3a01082, 0xe3a00010, 0xfbffe9c2, 0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xe3a00005, 
+    0xfa000684, 0xe59f1104, 0xe5911000, 0xe0400001, 0xe3500000, 0xc1d500b0, 0xc2800001, 0xc1c500b0, 
+    0xd1c540b0, 0xdaffffed, 0xeaffffde, 0xe92d500f, 0xe59f00dc, 0xfb00071c, 0xe3a02103, 0xe3a0105c, 
+    0xe3a00010, 0xfbffe9ac, 0xe3a02103, 0xe3a0105d, 0xe3a00010, 0xfbffe9a8, 0xf57ff05f, 0xe8bd500f, 
+    0xe25ef004, 0xe92d500f, 0xe59f00a8, 0xfb00070e, 0xe3a02103, 0xe3a01062, 0xe3a00010, 0xfbffe99e, 
+    0xe3a02103, 0xe3a01063, 0xe3a00010, 0xfbffe99a, 0xf57ff05f, 0xe8bd500f, 0xe25ef004, 0xc1000354, 
+    0xd0020012, 0x00032272, 0x00032274, 0x0003247c, 0xc1000364, 0xd0020108, 0x00032270, 0x000323bc, 
+    0x00032484, 0x00032230, 0xd28fffd2, 0x00032564, 0x00032c5c, 0xc1000374, 0xc1000394, 0xc10003a4, 
+    0x000322a4, 0x000323cc, 0x00032411, 0x000323b4, 0x000323e2, 0xd00305c4, 0xc10003b4, 0x0003227e, 
+    0x000322a0, 0x00032b5c, 0x000323e0, 0xd00305cc, 0x000322a8, 0xc10003c4, 0xc10003d4, 0x47f0e92d, 
+    0x469ab086, 0x46894617, 0xe9dd2200, 0xe02a850e, 0x0180eb00, 0xeb022f00, 0xdd010441, 0xe0002101, 
+    0x28002100, 0x2302dd01, 0x2308e000, 0x4103fb11, 0xf9334bfb, 0x23006011, 0xeb034271, 0xf9352c02, 
+    0x428c401c, 0x46a6dd01, 0x468ee000, 0xda0345b6, 0xdc02428c, 0xe000460c, 0x1c5b4634, 0xf8252bff, 
+    0xd9ea401c, 0x45421c52, 0xea4fd3d2, 0x4eed2148, 0xea4fb20c, 0xea41114a, 0xea4202c7, 0x43010149, 
+    0xf0414630, 0x46390780, 0xf835f025, 0x7100f447, 0xf0254630, 0x2000f830, 0x21019005, 0x1d33462a, 
+    0xe9cd9004, 0x46211002, 0x90019000, 0xfccaf000, 0x7180f447, 0xf0254630, 0x0275f81e, 0x126f2400, 
+    0x1c64e002, 0xd20642ac, 0x46392208, 0xf0254630, 0x2800f829, 0xb006d1f5, 0x87f0e8bd, 0x4fffe92d, 
+    0x4ed1b083, 0x469a2400, 0xf2404693, 0x9f121900, 0x5810e9dd, 0xeb00e00a, 0x464a2344, 0x2104eb07, 
+    0x2004eb08, 0xfe66f024, 0xb2241c64, 0x42ac6830, 0xe9cddbf1, 0xe9dd5000, 0x46530103, 0xf7ff465a, 
+    0xb007ff6d, 0x8ff0e8bd, 0x4fffe92d, 0x2000b083, 0xba10e9dd, 0x98039002, 0xd0072801, 0xb1389805, 
+    0xf8df2702, 0x260082e4, 0xe0404634, 0xe7f82701, 0xe7f62708, 0xf1ba48b5, 0xf8df0f00, 0xeb0092d4, 
+    0xd10b2584, 0xf2404628, 0xf0251100, 0x230cffb1, 0x22804629, 0x0046eb0b, 0xff8bf024, 0x48ad2108, 
+    0x4aae4bad, 0x0100e9cd, 0x46289902, 0xf8e6f025, 0x230848aa, 0x228049a8, 0x0200f8d0, 0x46296008, 
+    0xf02448a6, 0x48a4ff87, 0x22802308, 0xf0244649, 0xf8d8ff81, 0xf2400000, 0x46491200, 0x2344eb00, 
+    0xf0244628, 0x3680fe07, 0xb2361c64, 0x42bcb224, 0xf8d8dbc0, 0xac030000, 0x7000e9cd, 0x000fe894, 
+    0xff0cf7ff, 0xe92de79d, 0x00d247f0, 0xb0864f8d, 0x0541ea42, 0x4305025b, 0xa038f8dd, 0xf883fa0f, 
+    0xf4454638, 0xf0247180, 0x2400ff76, 0x1900f240, 0xe002027e, 0x42b41c64, 0x2208d206, 0x46384649, 
+    0xff80f024, 0xd1f52800, 0x7100f445, 0xf0244638, 0x2000ff62, 0x21014a7b, 0x1d129005, 0x90044653, 
+    0x0102e9cd, 0x90004641, 0x20019001, 0xfbfaf000, 0xe92de741, 0xf8df43f8, 0x461d81d0, 0x7608e9dd, 
+    0x3000f8d8, 0x462b9300, 0xffbdf7ff, 0xf2402400, 0xe00c1900, 0x0000f8d8, 0x2304eb06, 0x2204eb07, 
+    0xeb004649, 0xf0242044, 0x1c64fdda, 0x42acb224, 0xe8bddbf0, 0xe92d83f8, 0x469b4ffe, 0x28012300, 
+    0xd00f9302, 0x2302b182, 0xa17cf8df, 0xf8da4699, 0x93003000, 0xf7ff464b, 0x2600ff96, 0x816cf8df, 
+    0xe04c4634, 0xe7ef2301, 0xe7ed2308, 0xeb084f58, 0xf8da2584, 0x462a0000, 0xf240463b, 0xeb001100, 
+    0xf0242044, 0x4955fdac, 0x22802308, 0xf0244628, 0x4951fed0, 0x22802308, 0xf0244638, 0x4a4efeca, 
+    0x68104b4e, 0x0200f8c3, 0x60102000, 0x0200f8c2, 0xf5c02001, 0xf8537180, 0xf8437020, 0xf8527021, 
+    0x1c407020, 0x427fb200, 0xf8422880, 0xdbf07021, 0x48402108, 0x46479b02, 0xe9cd462a, 0x493e0100, 
+    0xf025483e, 0x980cfaf5, 0x2280b168, 0xeb074628, 0xf0242144, 0x3680fe4f, 0xb2361c64, 0x454cb224, 
+    0xe8bddbb4, 0x230c8ffe, 0x22804628, 0x0146eb0b, 0xfea0f024, 0xe92de7ef, 0x4a3141f0, 0x460c2500, 
+    0x1700eb02, 0x0000f994, 0xd0152880, 0xf3604240, 0xf9940607, 0x28800001, 0x4240d010, 0x260ff360, 
+    0xeb07b2b1, 0xf0240045, 0x1c6dfeac, 0x1ca4b22d, 0xdbe72d08, 0x81f0e8bd, 0xe7e8207f, 0xe7ed207f, 
+    0x460eb570, 0x2400491e, 0x1500eb01, 0x0044eb05, 0xfe94f024, 0xb241b200, 0xd00d2980, 0xeb064249, 
+    0x12000244, 0x70112880, 0x4240d008, 0x1c647050, 0x2c08b224, 0xbd70dbea, 0xe7f0217f, 0xe7f5207f, 
+    0x4d09b570, 0x68282120, 0xfe72f025, 0x68292400, 0xf7ffb260, 0x1c64ffb0, 0x2c04b224, 0xbd70dbf7, 
+    0x0003249c, 0xd1800100, 0x00032218, 0x0003627c, 0x0003827c, 0x0002e510, 0x00039a7c, 0x00038a7c, 
+    0xd00304a2, 0x41fce92d, 0x46074e32, 0x0100f640, 0xf0256830, 0x2500fe4d, 0x2f012400, 0xb1acd014, 
+    0x68312002, 0x46222300, 0x0100e9cd, 0x46384629, 0xfdc4f7ff, 0xb2641c64, 0xdbee2c04, 0xb26d1c6d, 
+    0xdbe92d04, 0x81fce8bd, 0xe7ea2001, 0xe7e82008, 0xb5102000, 0xffd6f7ff, 0xf7ff2001, 0xe8bdffd3, 
+    0xe7ad4010, 0x4e1bb57c, 0x46142200, 0xf8236833, 0x1c524012, 0xf823b212, 0x1c520012, 0x2affb212, 
+    0x2501ddf5, 0x29038018, 0x2400d00e, 0x23006830, 0xb261461a, 0x5000e9cd, 0xf7ff2001, 0x1c64fd8f, 
+    0x2c04b224, 0xbd7cdbf2, 0x20014c0b, 0x5300e9cd, 0x461a2300, 0x1000f994, 0xfd80f7ff, 0x23006830, 
+    0xe9cd461a, 0xf9945000, 0x20011001, 0xfd76f7ff, 0x0000bd7c, 0x00032218, 0x000323b4, 0x4fffe92d, 
+    0x48a6b085, 0xb298f8df, 0xf500460d, 0x4ea56a80, 0xf50b9002, 0x48a46980, 0x6880f506, 0x20009004, 
+    0xf2409003, 0x98044100, 0xfdd2f025, 0xf240489f, 0xf0251100, 0x4c9dfdbd, 0xf44f2000, 0x60273780, 
+    0x0280eb04, 0x1c405629, 0x60510289, 0xdbf72810, 0x49972508, 0x46534895, 0x1500e9cd, 0x2102e9dd, 
+    0xfeecf024, 0x01694891, 0xfda2f025, 0x60272000, 0xeb049907, 0x56090280, 0x02891c40, 0x28106051, 
+    0x2108dbf6, 0x464b488a, 0xe9cd465a, 0x48870100, 0xf0249903, 0x2400fed3, 0xf85b9902, 0xf8510024, 
+    0xf8595024, 0xf85a1024, 0xfb003024, 0xfb01f205, 0x43432203, 0xfb014340, 0xfb010001, 0x12073515, 
+    0x4639d00a, 0xf0254610, 0xf846fce3, 0x46390024, 0xf0254628, 0xe004fcdd, 0x1000f240, 0x0024f846, 
+    0xf8482000, 0x1c640024, 0xdbd52c81, 0xe0c39808, 0x1e409812, 0x486fe0b8, 0x28057800, 0xf1bad00d, 
+    0xd0200f01, 0x496c9805, 0x2540eb01, 0xf04f496b, 0xeb010b01, 0x23002440, 0x4d69e067, 0x0f01f1ba, 
+    0x46504c68, 0xf1b9d003, 0xd00a0f00, 0x464a2002, 0x5400e9cd, 0x46839905, 0x46504603, 0xfdf9f7ff, 
+    0x2008e7e9, 0x9805e7f3, 0xeb01495f, 0x495f2540, 0x01d9e7dd, 0x4f5e6830, 0x2011f935, 0xf8474350, 
+    0xf9340021, 0xf8d62011, 0x43500200, 0xf8424a59, 0x20010021, 0xf8561842, 0xf9357020, 0xf934c012, 
+    0xfb07e012, 0xf858f70c, 0xfb0cc020, 0x4f507c1e, 0xc022f847, 0x7020f856, 0xc012f934, 0xe012f935, 
+    0xf70cfb07, 0xc020f858, 0x28801c40, 0x7c0efb0c, 0xf8474f48, 0xdbddc022, 0x7800483e, 0xd1122805, 
+    0xe10cf8df, 0x18422000, 0x28801c40, 0xc022f85e, 0x2c2cea4f, 0xc012f825, 0xc022f857, 0x2c2cea4f, 
+    0xc012f824, 0x1c5bdbef, 0x455bb25b, 0x4831dbb1, 0x28057800, 0x4b37d047, 0x4a352400, 0xf8c26818, 
+    0x20810200, 0xf8c3601c, 0xf5c04200, 0xf8527180, 0xf8425021, 0xf8535020, 0x42491021, 0x1020f843, 
+    0x28ff1c40, 0x2108ddf1, 0x4a204821, 0xe9cd9b03, 0x49280100, 0xf0254826, 0x481cf8eb, 0x9904230c, 
+    0xf0242280, 0x9804fca7, 0xf5002180, 0xf0257080, 0x9804fcbf, 0xe9cd2300, 0x99050400, 0x4650461a, 
+    0xfcd2f7ff, 0x0001f1a9, 0xea5fb240, 0xf57f0900, 0xf10aaf42, 0xb2400001, 0x46822801, 0xaf38f77f, 
+    0xe8bdb009, 0xf8cd8ff0, 0x2300b000, 0x5401e9cd, 0x464a9905, 0xf7ff4650, 0xe7e3fc91, 0x000341ec, 
+    0x000331ec, 0x000339ec, 0x000349ec, 0x0003627c, 0x0002e510, 0x00032cd4, 0x0003cdfc, 0x0003d5fc, 
+    0x0003527c, 0x00035a7c, 0x0003bdfc, 0x0003c5fc, 0x00038a7c, 0x00039a7c, 0x43f8e92d, 0x2100460d, 
+    0x91002600, 0x4634b281, 0x48260c07, 0xfc79f024, 0x46394824, 0xf0241c80, 0x4822fc74, 0x1d004629, 
+    0xfc6ff024, 0x2100481f, 0xf0241d80, 0x4f1dfc6a, 0x0000f44f, 0x8070f8df, 0x90001f3f, 0x4642210e, 
+    0xf0014668, 0x2801f91b, 0xb2a3d027, 0x22044817, 0xf02421f0, 0x1c64fc70, 0x2c0fb264, 0x2400dd00, 
+    0x23014638, 0x210c2202, 0xfc65f024, 0x46382301, 0x46192200, 0xfc5ff024, 0x46382500, 0x21012200, 
+    0xfc67f024, 0x1c6db158, 0x2d04b22d, 0x2100dbf5, 0xf0244638, 0x2e00fc36, 0xe8bdd0d0, 0x260183f8, 
+    0x0000e7f5, 0xd03d1004, 0xd003517c, 0xd03c80c0, 0xea410589, 0x49620040, 0x4308b510, 0xfc1ef024, 
+    0xbd10b200, 0x0107f021, 0x485d4301, 0x3030b289, 0xbc17f024, 0x4c5ab510, 0xeb012107, 0xb2813000, 
+    0x46203430, 0xfc0df024, 0xf0244620, 0xb200fc07, 0xe92dbd10, 0x461d41f0, 0x460c4617, 0xf7ff4606, 
+    0x40bdffe9, 0x402543a0, 0xb2814328, 0xe8bd4630, 0xe7d741f0, 0x219ff360, 0xf440b288, 0x48484100, 
+    0xf0243038, 0xb510bbee, 0x06804c45, 0x34380c01, 0xf0244620, 0x4620fbe6, 0xfbe0f024, 0xbd10b200, 
+    0x41f0e92d, 0x4617461d, 0x4606460c, 0xffebf7ff, 0x43a040bd, 0x43284025, 0x4630b281, 0x41f0e8bd, 
+    0xb510e7d8, 0xf440460c, 0x48356170, 0xf024302e, 0x4833fbc8, 0xe8bd4621, 0x302a4010, 0xbbc1f024, 
+    0x460cb510, 0x482e4601, 0x6170f441, 0xea40302e, 0xf0245084, 0x482afbb6, 0xea40302a, 0xf0245084, 
+    0xb200fbad, 0xe92dbd10, 0x461d41f0, 0x460c4617, 0x21004606, 0xffe4f7ff, 0x43a040bd, 0x43284025, 
+    0x4630b281, 0x41f0e8bd, 0x0780e7cb, 0x010ff001, 0xea400c40, 0x481a2101, 0x4311b510, 0x302e461c, 
+    0xfb8ff024, 0x46214816, 0x4010e8bd, 0xf024302a, 0x0780bb88, 0x010ff001, 0xea400c40, 0x48102101, 
+    0x302e4311, 0xf024b510, 0x480dfb7c, 0xf024302a, 0xb200fb75, 0xe92dbd10, 0x461c47f0, 0x46884617, 
+    0xe9dd4681, 0xf7ff6508, 0x40b5ffe4, 0x463a43a0, 0x46414025, 0xb2834328, 0xe8bd4648, 0xe7c447f0, 
+    0xd28fffc0, 0x5ff0e92d, 0x461f4d53, 0x46902301, 0xb030f8dd, 0xf8dd460c, 0x2102a038, 0x9028f8dd, 
+    0x4628461a, 0xfb67f024, 0x20042100, 0xff8cf000, 0x2c404e4a, 0x7100f643, 0x0660dd08, 0x2310d406, 
+    0x22084630, 0xfb40f024, 0xe01f2310, 0xdd012c1f, 0xd5f406a0, 0xdd082c0f, 0xd40606e0, 0x46302304, 
+    0xf0242208, 0x2304fb31, 0x2c07e010, 0x0720dd08, 0x2302d406, 0x22084630, 0xfb26f024, 0xe0052302, 
+    0x46302301, 0xf0242208, 0x2301fb1f, 0x22004630, 0xf024213f, 0x4e31fb19, 0x21042202, 0x1d36464b, 
+    0xf0244630, 0x2201fb11, 0x2102465b, 0xf0244630, 0x2200fb0b, 0x21014653, 0xf0244630, 0x4e27fb05, 
+    0x9b0b2202, 0x36142104, 0xf0244630, 0x9b0dfafd, 0x21022201, 0xf0244630, 0x9b0ffaf7, 0x21012200, 
+    0xf0244630, 0x481dfaf1, 0x46232200, 0x71fff64f, 0xf0241f00, 0x4819fae9, 0x30084641, 0xfadbf024, 
+    0x46391d30, 0xfad7f024, 0x22002301, 0xf04f4619, 0xf0244040, 0x04b4fad9, 0x3e084e10, 0x4620e00e, 
+    0xff10f000, 0xdc091e04, 0x46204c0d, 0xfac6f024, 0x5180f440, 0xf0244620, 0xe004fac4, 0xf0244630, 
+    0x2801fab7, 0x4628d1eb, 0x5ff0e8bd, 0x22012300, 0xf0242102, 0x0000bad0, 0xd003529a, 0xc000000c, 
+    0xd003517c, 0x22004884, 0x31fff240, 0xf024b510, 0xb200fab9, 0xb5f8bd10, 0x20004605, 0xf7ff9000, 
+    0x4c7efff1, 0x80204e7e, 0x0000f44f, 0xe0099000, 0x46322108, 0xf0004668, 0x2801ff51, 0xf7ffd005, 
+    0x8020ffe1, 0x42a88820, 0xbdf8dcf2, 0x5fffe92d, 0x46044d74, 0x468a4e74, 0x46914f74, 0xf8df2202, 
+    0x782881d0, 0xb038f8dd, 0x0101f000, 0xea027830, 0x43010040, 0x22047838, 0x0080ea02, 0xf8984301, 
+    0x22080000, 0x00c0ea02, 0x486a4301, 0x78002210, 0x1000ea02, 0x48684301, 0x78002220, 0x1040ea02, 
+    0x48664301, 0x07807800, 0x6110ea41, 0x3808485a, 0xfa51f024, 0x01e04962, 0xea407809, 0xf04f1101, 
+    0xf0244048, 0x495ffa48, 0x10caea4f, 0xea407809, 0x48511101, 0xf0243810, 0x495bfa3e, 0x10c9ea4f, 
+    0xea407809, 0x484c1101, 0xf024380c, 0x484afa34, 0xb19c1f00, 0xf024210f, 0x4847fa2e, 0x1d077839, 
+    0x29011d3c, 0x7829d00c, 0xd0352901, 0x29017831, 0xf898d032, 0x29011000, 0xe011d02e, 0xe7ea2100, 
+    0x4a4b494a, 0x78127809, 0xea410189, 0x4a491102, 0xea417812, 0x4a480182, 0x43117812, 0xfa0bf024, 
+    0x46389903, 0xfa07f024, 0x46202300, 0x21062201, 0xfa0af024, 0x46202301, 0x46192200, 0xfa04f024, 
+    0x0f00f1bb, 0x482cd106, 0x21042202, 0xf0243010, 0xb1e0fa09, 0x9fffe8bd, 0x88094928, 0xf9ebf024, 
+    0x46389903, 0xf9e7f024, 0xe7de2301, 0xf0002002, 0x2801fde9, 0x4c22d00b, 0xf0244620, 0xb004f9df, 
+    0x7100f440, 0xe8bd4620, 0xf0245ff0, 0x2200b9da, 0x21014620, 0xf9e6f024, 0xd1e72800, 0xb5f8e7da, 
+    0x23012500, 0x4629462a, 0x95004628, 0xfa30f004, 0x24004e11, 0x46233610, 0x46302203, 0xf0242108, 
+    0x2301f9c3, 0x22024630, 0xf0242104, 0x2300f9bd, 0x461a9500, 0x46184619, 0xff28f7ff, 0xb2641c64, 
+    0xdbe82c02, 0x4630b001, 0x22022300, 0x40f0e8bd, 0xf0242104, 0x0000b9a9, 0xc8000014, 0x00032262, 
+    0xd003517a, 0x0003225f, 0x0003225d, 0x00032258, 0x0003225b, 0x0003223f, 0x0003223d, 0x0003223a, 
+    0x00032245, 0x00032243, 0x00032241, 0x00032250, 0x00032251, 0x00032252, 0x00032253, 0x41f0e92d, 
+    0x4d1c2301, 0x4607220a, 0x4628029c, 0xf0244621, 0x00a6f992, 0x46304639, 0xfdb6f000, 0x46212300, 
+    0x4628220a, 0xf987f024, 0x46304639, 0xfdacf000, 0x22012300, 0x1f282102, 0x41f0e8bd, 0xb97bf024, 
+    0xb1884b0d, 0x1002ea41, 0x0041ea40, 0x00c1ea40, 0x2001ea40, 0x2041ea40, 0x2081ea40, 0x20c1ea40, 
+    0x4618b281, 0xb94df024, 0xea400110, 0xea400041, 0xe7eb0081, 0xd00350f6, 0xd00352ac, 0x41f0e92d, 
+    0x48ff4607, 0xf2402f01, 0xd00a1200, 0x2f024bfd, 0x881e49fd, 0xf647880d, 0xd0162112, 0xd10b2f03, 
+    0x49fae02d, 0x1000f991, 0xd0012904, 0xd1032905, 0x680949f7, 0xd0012903, 0xe0002100, 0xf0244611, 
+    0x2600f920, 0x46344635, 0x4af2e021, 0xb9168814, 0xd200428d, 0xeb05460d, 0x42a14106, 0x1e49dc01, 
+    0xf240b28c, 0x428c4180, 0x460cd201, 0xf5b4e004, 0xd3016f00, 0x74fff240, 0x1104f240, 0x2400e005, 
+    0x428db916, 0x460dd200, 0xf0244611, 0x48dcf8fa, 0x1d004631, 0xf8f5f024, 0x462948d9, 0xf0241d80, 
+    0x48d7f8f0, 0x30084621, 0xf8ebf024, 0x382248d4, 0x2301b10f, 0x2300e000, 0x21022201, 0xf8fbf024, 
+    0x700748d5, 0x81f0e8bd, 0xb51048d0, 0x1000f990, 0x290348d2, 0x2904d005, 0x2905d012, 0x2000d008, 
+    0x2205e015, 0xf0242120, 0xb180f8f4, 0xe00548cc, 0x21102204, 0xf8edf024, 0x48cab148, 0xe0067800, 
+    0x21082203, 0xf8e5f024, 0x48c7b108, 0xe8bde7f6, 0xe7734010, 0xf24048ba, 0xb5702112, 0xf024381c, 
+    0x48b7f8b0, 0x011cf647, 0xf024381a, 0x48bff8aa, 0x2173f240, 0xf8a5f024, 0x210248b1, 0xf0243818, 
+    0x48aff8a0, 0x0400f243, 0x38144621, 0xf899f024, 0x212048ab, 0xf0243810, 0x48b5f894, 0xf0242100, 
+    0x48b3f890, 0x11fef240, 0xf0241c80, 0x48b0f88a, 0x220c2300, 0x38164621, 0xf89df024, 0x4cad48a3, 
+    0x78004dad, 0xd07d2803, 0x70a82001, 0x7020203c, 0x02017820, 0xf5a11e40, 0x43017180, 0xb2894898, 
+    0xf024380e, 0x4896f86e, 0x3103f240, 0xf024380c, 0x7820f868, 0xb2811e40, 0x1f804891, 0xf861f024, 
+    0x1e407820, 0x488eb281, 0xf0243808, 0x4897f85a, 0x7180f64f, 0xf0243808, 0x4894f854, 0x6170f64f, 
+    0xf0241f80, 0x4886f84e, 0x38222110, 0xf849f024, 0xf64a4883, 0x3820210a, 0xf843f024, 0x22094c8f, 
+    0xf2404e8f, 0x78202100, 0x1300f340, 0x1c5b4630, 0xf851f024, 0x22087820, 0xf3400151, 0x46301300, 
+    0xf0241c5b, 0x2300f848, 0x22044630, 0xf0242110, 0x2300f842, 0x21014630, 0xf024461a, 0x2300f83c, 
+    0x22014630, 0xf0242102, 0x2300f836, 0x22024630, 0xf0242104, 0x2300f830, 0x22034630, 0xf0242108, 
+    0x7820f82a, 0x00c0f3c0, 0xff21f002, 0x212878a8, 0x40c12214, 0x1db040c2, 0x2102ea41, 0xf801f024, 
+    0xe00078a8, 0x2168e109, 0x40c12254, 0x486c40c2, 0x2102ea41, 0xf0233008, 0x4859fff4, 0x0120f244, 
+    0xf023381e, 0x4866ffee, 0x0188f648, 0xf0233010, 0x4863ffe8, 0x30122100, 0xffe3f023, 0xf3c07820, 
+    0xf0020040, 0x4859ff35, 0x30a4210c, 0xffd9f023, 0xf6414d56, 0x23037400, 0x1cad4621, 0x46282208, 
+    0xffe9f023, 0x46282304, 0x211f2200, 0xffe3f023, 0x23054d4e, 0x46212208, 0x462835a0, 0xffdbf023, 
+    0x4628230a, 0x211f2200, 0xffd5f023, 0x23011cad, 0x22044628, 0xf0232170, 0x2300ffce, 0x21074628, 
+    0xf023461a, 0x4846ffc8, 0x38a42100, 0xffa9f023, 0x21004843, 0xf02338a2, 0x4841ffa4, 0x38b62102, 
+    0xff9ff023, 0x2100483e, 0xf0233878, 0xf7ffff9a, 0x482bfebb, 0x3844211b, 0xff93f023, 0xf2404e3a, 
+    0x49384580, 0x462b2210, 0xf0234630, 0x2200ff8d, 0xf64f462b, 0x463071ff, 0xff86f023, 0x1d304933, 
+    0xff79f023, 0x23004d2e, 0xf24c220e, 0x35160100, 0xf0234628, 0x2303ff90, 0x7100f643, 0x46282208, 
+    0xff89f023, 0x46282300, 0x21c02206, 0xff83f023, 0x46282303, 0x213f2200, 0xff7df023, 0x23024822, 
+    0x383c2218, 0x61e0f04f, 0xff5ef023, 0x23084d17, 0x4621461a, 0x462835a6, 0xff6df023, 0x46282302, 
+    0x21302204, 0xff67f023, 0x46282307, 0x210f2200, 0xff61f023, 0x21094812, 0xf0233014, 0xe027ff42, 
+    0xd0035114, 0x000322b8, 0x000322ba, 0x0003227e, 0x00032374, 0x000322bc, 0x000322b7, 0xd28f007c, 
+    0x000322b3, 0x0003230a, 0x00032309, 0xd003050a, 0xd0030818, 0x000322b6, 0x000324b8, 0x000322b5, 
+    0xd00352a0, 0xffff0000, 0xd1800040, 0x00080005, 0xf24448ff, 0xf023310c, 0x48feff14, 0x1111f241, 
+    0xff0ff023, 0x230e4dfc, 0x04212218, 0xf0234628, 0x230eff0b, 0x22104628, 0xf0230221, 0x230cff05, 
+    0x22084621, 0xf0234628, 0x4628feff, 0x4070e8bd, 0x2200230c, 0xf023211f, 0x207cbef7, 0x20007020, 
+    0xe67570a8, 0x5ffce92d, 0x260048ee, 0x46374ceb, 0x83acf8df, 0x78024bed, 0x4ded48eb, 0x0180f3c2, 
+    0xb3e87800, 0x706b789b, 0xc3a8f8df, 0xf3424bea, 0x1c521200, 0x469b46e2, 0xfd72f7ff, 0xf04f4de4, 
+    0xf8cd0900, 0x46439000, 0x7868464a, 0x2001b241, 0xff91f7fe, 0xf00248e1, 0x48e0fc72, 0xf8307869, 
+    0x81280011, 0xf9382501, 0x1e010015, 0x4248da00, 0xdd0442b0, 0xd5000008, 0x462f4248, 0x1c6db206, 
+    0x2d80b22d, 0x1fbfdbef, 0x9000b238, 0x007ff1c0, 0x1700f240, 0xf5a79001, 0xb2067080, 0xe0002000, 
+    0x4605e003, 0x0026f844, 0x781be01c, 0xf8df706b, 0x4bccc330, 0x9800e7bb, 0x44284659, 0xf980fa0f, 
+    0xf3c01b78, 0x46500245, 0xfffef022, 0xf85443c0, 0x07c02026, 0x0019f938, 0x4410d021, 0xb22d1c6d, 
+    0x0026f844, 0x42a89801, 0x1c7fdae5, 0xf5b7b23f, 0xdbd07fc0, 0xf06f2600, 0x46350804, 0x077ff06f, 
+    0x0025f854, 0xfbf0f026, 0xfa5cf026, 0xf0264642, 0xf025fd8a, 0x287ffe9d, 0x217fdb03, 0x1a10e002, 
+    0x4601e7dc, 0xdc0042b9, 0xb2494639, 0x1025f844, 0xfb011c6d, 0xb22d6600, 0xdbe12d80, 0x250048a4, 
+    0x4ea96106, 0x00c5eb04, 0xf8346841, 0xf3610035, 0xb281201f, 0x0045eb06, 0xfe43f023, 0xb22d1c6d, 
+    0xdbef2d40, 0x9ffce8bd, 0x47f0e92d, 0xf240489f, 0xf8df1890, 0x4e96927c, 0x28007800, 0x4897d16a, 
+    0xf0026934, 0x4895fbdc, 0xf8307871, 0x81700011, 0xf0264620, 0x4997fbc1, 0xf0264607, 0xf026fbd1, 
+    0x4c95fa11, 0x46232200, 0xff16f025, 0x050bf06f, 0xf026462a, 0xf025fd38, 0x1040fe4b, 0x210180b0, 
+    0xf0264638, 0xf026fd5e, 0x2200f9fd, 0xf0254623, 0x462aff03, 0xfd27f026, 0xfe3af025, 0x80f01040, 
+    0xfe5af002, 0xd2064540, 0x0000f8d9, 0xd8022811, 0xf0024640, 0x4f81fe4c, 0x462c2500, 0x4620703d, 
+    0xfa2cf003, 0x428c7871, 0x4605d100, 0x42887839, 0xb2c1dd00, 0x1c647039, 0x2c04b2e4, 0x1c6dd3ef, 
+    0x715ef641, 0xeba12200, 0xb2000065, 0x17c11ec0, 0x6191eb00, 0x013ff021, 0xb2831a40, 0x213f486a, 
+    0xf023380a, 0x486efde8, 0x220c2303, 0x0100f247, 0xfde1f023, 0x424088f0, 0x4863b281, 0xf023380e, 
+    0x88b0fdc0, 0xb2814240, 0x380c485f, 0xfdb9f023, 0x424088b0, 0x485cb281, 0xf0233090, 0x4861fdb2, 
+    0xb3607800, 0x0004f9b6, 0x0040eb00, 0x004ff3c0, 0xfdfdf002, 0x381c4854, 0xfda0f023, 0xd2064540, 
+    0x0000f8d9, 0xd8022811, 0xf0024640, 0x4854fdf0, 0x220a2300, 0x4100f240, 0xf023380a, 0x2101fdac, 
+    0xf0022008, 0x2000fe07, 0xfe55f002, 0xfe3af002, 0x7800484d, 0xd0052802, 0xd0032803, 0xf647e009, 
+    0xe7d570ff, 0x23004846, 0x21022201, 0xf0233014, 0x7870fd92, 0x87f0e8bd, 0x1060f24f, 0x0041ea40, 
+    0x4839b281, 0x3810b510, 0xfd6bf023, 0xf2404836, 0x1e804100, 0xfd65f023, 0x21012207, 0x4010e8bd, 
+    0xf0022000, 0xe92dbd9a, 0xf8df47fc, 0x23018098, 0x22004e36, 0x4f364d26, 0x0000f898, 0x7600e9cd, 
+    0x0980f3c0, 0xb2417828, 0xf7fe4618, 0x2400fdf2, 0xf8372076, 0xfb111010, 0xf836f201, 0x1c401010, 
+    0x287fb280, 0x2101fb11, 0xd9f2440c, 0x78294829, 0x4021f840, 0xf0024828, 0x4928fa40, 0xf8517828, 
+    0x1b193020, 0x460ed401, 0x424ee000, 0x4f224a10, 0x320c2400, 0x0fa3ebb6, 0x2900db46, 0x4249da00, 
+    0x0f63ebb1, 0xf857da3e, 0xf64b1020, 0xe03713f6, 0xd0030816, 0xd00352aa, 0xd1800010, 0x0003bdfc, 
+    0x0003c5fc, 0x000322b5, 0x00032396, 0x000323ac, 0x000324b8, 0x8365f253, 0x7425eef5, 0x000323d4, 
+    0xaf77a42e, 0xca4fa6c1, 0xd0030510, 0x00032cd4, 0x0003222c, 0x40e00000, 0x40220000, 0x000322bf, 
+    0xd0035100, 0x00032cd6, 0x000322b3, 0x00035a7c, 0x0003527c, 0x0003307c, 0x000331dc, 0x0003306c, 
+    0xd90f4299, 0xe00d5414, 0xda002900, 0xebb14249, 0xdb050fe3, 0x1020f857, 0x53bdf24a, 0xd2014299, 
+    0x54112101, 0x7800484a, 0xf898b318, 0x78131000, 0x4e494848, 0x1700f341, 0xb31b1c7f, 0xb30b7853, 
+    0xb1fb7893, 0xb1ea78d2, 0xd00d07c9, 0x78094943, 0xd0072904, 0x2200230f, 0xf023211f, 0x463afccc, 
+    0xe0034649, 0xe7f6231f, 0xe7f42300, 0xf7ff7830, 0x7828fb47, 0xb2c01c40, 0x28047028, 0x702cd300, 
+    0x87fce8bd, 0x211f2300, 0xf023461a, 0x2100fcb4, 0xe7eb463a, 0x4d32b57c, 0x4e322400, 0x22002301, 
+    0xb2614618, 0x6500e9cd, 0xfd33f7fe, 0x20762100, 0x2010f836, 0xf302fb12, 0x2010f835, 0xb2801c40, 
+    0xfb12287f, 0x44113202, 0x4827d9f2, 0x1024f840, 0xf8404826, 0x1c641024, 0x2c04b2e4, 0xbd7cd3de, 
+    0xb570481e, 0xf9902423, 0x28040000, 0x2805d002, 0xe002d002, 0xe0002408, 0x481d240d, 0x7161f641, 
+    0x76fff641, 0x78002200, 0xeba11c40, 0x48190550, 0xf0234631, 0x4420fc7e, 0x1b403008, 0x5000f500, 
+    0x17c1b200, 0x6191eb00, 0x013ff021, 0xd0011a40, 0x0040f1c0, 0x010af242, 0x1a081a28, 0xb2834631, 
+    0xe8bd480c, 0x22004070, 0xf0233096, 0x0000bc54, 0x0003229d, 0xd00352a0, 0x00032396, 0x0003227e, 
+    0x00035a7c, 0x0003527c, 0x0003306c, 0x0003307c, 0x000322bf, 0xd003504a, 0x460db570, 0xeb014929, 
+    0x21001000, 0xf0234604, 0x2001fc16, 0x0185eb00, 0xe8bd4620, 0xf0234070, 0x4922bc0e, 0x1000eb01, 
+    0xf0232102, 0x491fbc08, 0xeb01b510, 0xf0231000, 0xf3c0fbff, 0xbd100040, 0x310c491a, 0x1000eb01, 
+    0xbbf6f023, 0x4604b510, 0xd0091c40, 0xf7ff4620, 0xb118fff3, 0xf7ff4620, 0xb108ffe6, 0xbd102000, 
+    0xbd102001, 0x41f0e92d, 0x480e4605, 0x460f4616, 0x1405eb00, 0x46202102, 0xfbddf023, 0x46394809, 
+    0xeb003008, 0xf0231005, 0x2100fbd6, 0xf0234620, 0x2001fbd2, 0x0186eb00, 0xe8bd4620, 0xf02341f0, 
+    0x0000bbca, 0xc8000100, 0xd0052801, 0xd0032802, 0xd0032804, 0xd0032805, 0x47702000, 0x47702002, 
+    0x47702001, 0x47701e40, 0xe0004088, 0x28001e40, 0x4770d1fc, 0x41f0e92d, 0x460c4e44, 0x810cf8df, 
+    0x1d374605, 0x080cf108, 0x2201e00d, 0x21024630, 0xfbb8f023, 0xd00e2801, 0x46382200, 0xf0232101, 
+    0x2801fbb1, 0x4640d007, 0xfb92f023, 0x42a01a28, 0xe8bdd3eb, 0x4c3681f0, 0xf0234620, 0xf440fb8f, 
+    0x46206180, 0x41f0e8bd, 0xbb8bf023, 0x41f0e92d, 0x460e4615, 0x46984607, 0xf0234618, 0xf242fb7f, 
+    0xb1387410, 0xd0142d01, 0x44382000, 0x4640b281, 0xfb77f023, 0xf0234640, 0x2800fb71, 0x2d01d1fa, 
+    0x2400d000, 0xb28119a0, 0xe8bd4640, 0xf02341f0, 0x4620bb68, 0xe92de7e9, 0x461c41f0, 0x460e4615, 
+    0x20004607, 0xff58f7ff, 0xe0101b04, 0xf7ff2000, 0x1b00ff53, 0xdc0a2800, 0x46204c15, 0xfb4ef023, 
+    0x7100f440, 0xe8bd4620, 0xf02341f0, 0x4638bb4a, 0xfb44f023, 0x42a84030, 0xe7aad1e8, 0x4603b570, 
+    0x460c6800, 0x1e404615, 0x60182800, 0x4610dc0b, 0xfb34f023, 0x40a12101, 0xb2814308, 0xf0234628, 
+    0x2001fb30, 0x2000bd70, 0x0000bd70, 0xc8000120, 0xd003517e, 0xe28fc04d, 0xe12fff1c, 0x2101e7fe, 
+    0xd2042820, 0x23014081, 0x4853b242, 0x3820e004, 0x4081b242, 0x23014851, 0xbb16f023, 0xeb024a50, 
+    0xf0231000, 0x2101bb08, 0xd2052820, 0xb2424081, 0xf04f2300, 0xe0054041, 0xb2423820, 0x48474081, 
+    0x38082300, 0xbb00f023, 0x28202101, 0x4081d205, 0x2301b242, 0x4041f04f, 0x3820e005, 0x4081b242, 
+    0x2301483e, 0xf0233808, 0x2101baef, 0xd2042820, 0xb2424081, 0x301c4838, 0x3820e004, 0x4081b242, 
+    0x300c4836, 0xbaeef023, 0x41f0e92d, 0x4934460d, 0x4613461f, 0x9e063908, 0x1400eb01, 0x46202204, 
+    0xf0232130, 0x2203fad1, 0x21084620, 0xf023462b, 0x2202facb, 0x21044620, 0xf023463b, 0x4620fac5, 
+    0xe8bd4633, 0x220041f0, 0xf0232103, 0xb570babd, 0xe8bdb118, 0xf0234070, 0x4c21baab, 0x1f244d21, 
+    0xf0234620, 0x3410faa5, 0xd9f942ac, 0xe92dbd70, 0x240141f0, 0xd20e2820, 0xb2424e17, 0x36284084, 
+    0x23014615, 0x46304621, 0xfa9ef023, 0x46212301, 0x462a1d37, 0x3820e00e, 0xb2424e10, 0x36184084, 
+    0x23014615, 0x46304621, 0xfa8ef023, 0x46212301, 0x462a1d37, 0xf0234638, 0x2300fa87, 0x462a4621, 
+    0xf0234630, 0x4621fa81, 0x4638462a, 0x41f0e8bd, 0xf0232300, 0x0000ba79, 0xc1000008, 0xc1000508, 
+    0xc1000108, 0xc10003f4, 0xf04fb510, 0xf04f34ff, 0x46214041, 0xfa5ff023, 0x462148fe, 0xfa5bf023, 
+    0x462148fd, 0xfa57f023, 0x462148fa, 0xf0233008, 0x49fafa52, 0xf02348fa, 0x48f9fa4e, 0x301049f9, 
+    0xfa49f023, 0x49f848f6, 0xf0233020, 0x48f4fa44, 0x303049f6, 0xfa3ff023, 0x49f548f1, 0xf0233040, 
+    0x48effa3a, 0x305049f3, 0xfa35f023, 0x49f248ec, 0xf0233060, 0x48eafa30, 0x307049f0, 0xfa2bf023, 
+    0x49ef48e7, 0xf0233080, 0x48e5fa26, 0x309049ed, 0xfa21f023, 0x49ec48e2, 0xf02330a0, 0x48e0fa1c, 
+    0x30b049ea, 0xfa17f023, 0x49e948dd, 0xf02330c0, 0x48dbfa12, 0x30d049e7, 0xfa0df023, 0x49e648d8, 
+    0xf02330e0, 0x48d6fa08, 0x30f049e4, 0xfa03f023, 0x48e449e3, 0xf9fff023, 0x49e348e2, 0xf0233010, 
+    0x48e0f9fa, 0x302049e1, 0xf9f5f023, 0x49e048dd, 0xf0233030, 0x48dbf9f0, 0x304049de, 0xf9ebf023, 
+    0x49dd48d8, 0xf0233050, 0x48d6f9e6, 0x306049db, 0xf9e1f023, 0x49da48d3, 0xf0233070, 0x48d1f9dc, 
+    0x308049d6, 0xf9d7f023, 0x49d448ce, 0xf0233090, 0x48ccf9d2, 0x30a049d3, 0xf9cdf023, 0x49d248c9, 
+    0xf02330b0, 0x48c7f9c8, 0x30c049d0, 0xf9c3f023, 0x49ca48c4, 0xf02330d0, 0x48c2f9be, 0x30e049cc, 
+    0xf9b9f023, 0x49cb48bf, 0xf02330f0, 0x49caf9b4, 0xf02348ca, 0x48c9f9b0, 0x301049c9, 0xf9abf023, 
+    0x49c848c6, 0xf0233020, 0x48c4f9a6, 0x303049c6, 0xf9a1f023, 0x49c548c1, 0xf0233040, 0x48bff99c, 
+    0x305049c3, 0xf997f023, 0x49c248bc, 0xf0233060, 0x48baf992, 0x307049c0, 0xf98df023, 0x49af48b7, 
+    0xf0233080, 0x48b5f988, 0x309049bc, 0xf983f023, 0x49bb48b2, 0xf02330a0, 0x48b0f97e, 0x30b049b9, 
+    0xf979f023, 0x49b848ad, 0xf02330c0, 0x48abf974, 0x30d049b6, 0xf96ff023, 0x49a048a8, 0xf02330e0, 
+    0x48a6f96a, 0x4010e8bd, 0x30f0499c, 0xb963f023, 0x41fce92d, 0xfef8f7ff, 0xf7ff2000, 0xb662fea8, 
+    0x94002400, 0x46232201, 0x46212006, 0xfe7cf7ff, 0xf7ff2006, 0x2300fe48, 0x22019400, 0x20074619, 
+    0xfe72f7ff, 0xf7ff2007, 0x2300fe3e, 0x22039400, 0x20014619, 0xfe68f7ff, 0x94002300, 0x46192203, 
+    0xf7ff2011, 0x2300fe61, 0x22039400, 0x20124619, 0xfe5af7ff, 0xf7ff2001, 0x2011fe26, 0xfe23f7ff, 
+    0xf7ff2012, 0x2300fe20, 0x22029400, 0x46104619, 0xfe4af7ff, 0xf7ff2002, 0x2300fe27, 0x22039400, 
+    0x201e4619, 0xfe40f7ff, 0xf7ff201e, 0x2300fe0c, 0x22039400, 0x201f4619, 0xfe36f7ff, 0xf7ff201f, 
+    0x2201fe02, 0x23009400, 0x201c4611, 0xfe2cf7ff, 0x23014e7f, 0x461a2102, 0xf0234630, 0x487cf91c, 
+    0x75fff64f, 0x382a4629, 0xf8fbf023, 0x46294878, 0xf023382c, 0x2300f8f6, 0x22024630, 0xf0232104, 
+    0x4873f90a, 0x380a4629, 0xf8ebf023, 0x46294870, 0xf023380c, 0xf008f8e6, 0x1e67f809, 0xf0074638, 
+    0x2301fe91, 0x22004630, 0xf0234619, 0x2201f8f4, 0x23009400, 0x20044611, 0xfdf6f7ff, 0xf7ff2004, 
+    0x2300fdc2, 0x22039400, 0x20224619, 0xfdecf7ff, 0xf7ff2022, 0x2300fdb8, 0x22039400, 0x20214619, 
+    0xfde2f7ff, 0xf7ff2021, 0x2300fdae, 0x22019400, 0x20254619, 0xfdd8f7ff, 0xf7ff2025, 0x2300fda4, 
+    0x22019400, 0x20264619, 0xfdcef7ff, 0xf7ff2026, 0x4e50fd9a, 0x78304a50, 0xd0392801, 0x717ff647, 
+    0xf0234610, 0x2300f89e, 0x22019400, 0x20244619, 0xfdbaf7ff, 0xf7ff2024, 0x2300fd86, 0x22019400, 
+    0x20094619, 0xfdb0f7ff, 0x46294843, 0xf0233814, 0x4841f888, 0x38124629, 0xf883f023, 0xf248483e, 
+    0x46290500, 0xf0233818, 0x483bf87c, 0x38164629, 0xf877f023, 0xf7ff2009, 0x2300fd66, 0x70e0f64f, 
+    0x90002201, 0x90012107, 0xf01d4618, 0xe065fa19, 0x0000e0bd, 0xc1000500, 0xc1000008, 0x00004278, 
+    0xc1000108, 0x000045f8, 0x0000463c, 0x000047a8, 0x0000491c, 0x00004ba0, 0x00004bd8, 0x00004d3c, 
+    0x00004d88, 0x00004dc0, 0x00004f58, 0x00004fc4, 0x000050f4, 0x00005160, 0x00005198, 0x00005230, 
+    0x00005268, 0xc1000208, 0x000052a0, 0x000052e4, 0x00005328, 0x00005340, 0x00005358, 0x00007b1d, 
+    0x00005390, 0x000053c8, 0x00005590, 0x00005628, 0x0000568c, 0x000056a4, 0x000056e8, 0xc1000308, 
+    0x00005720, 0x000057ec, 0x000058d8, 0x00005910, 0x00005b2c, 0x00005c1c, 0x00005d70, 0x00005da8, 
+    0x00005de0, 0x00005e18, 0x00005f6c, 0x00005fa4, 0xd0039046, 0x00032362, 0xd03c8092, 0x94002201, 
+    0x46102300, 0x94012107, 0xf9aaf01d, 0x70f8f64f, 0x23009000, 0x22019001, 0x20022107, 0xf9a0f01d, 
+    0x002af249, 0x23009000, 0x22019001, 0x20032107, 0xf996f01d, 0x1091f244, 0x23009000, 0x22019001, 
+    0x2004211e, 0xf98cf01d, 0x208c2189, 0xe9cd2301, 0x22000100, 0x20054619, 0xf982f01d, 0x94002201, 
+    0x46112300, 0xf7ff201a, 0x201afcef, 0xfcbbf7ff, 0xfda8f006, 0x94002201, 0x46112300, 0xf7ff202b, 
+    0x202bfce3, 0xfcaff7ff, 0xf8bbf020, 0xf0204638, 0x2300f8a1, 0x22019400, 0x200e4619, 0xfcd4f7ff, 
+    0xf7ff200e, 0x7830fca0, 0xd0032801, 0xf647e00e, 0xe705617f, 0xfa87f021, 0x94002201, 0x46112300, 
+    0xf7ff201b, 0x201bfcc1, 0xfc8df7ff, 0x41fce8bd, 0xf64b4802, 0xf02231bb, 0x0000bf94, 0xd03c80b8, 
+    0x46032200, 0x2107481d, 0xbf8ef022, 0x4c1cb510, 0x22042300, 0x46202110, 0xff86f022, 0x46202301, 
+    0x21402206, 0xff80f022, 0x46202300, 0x21402206, 0xff7af022, 0x46202301, 0xe8bd2204, 0x21104010, 
+    0xbf72f022, 0x4c0eb510, 0x22052300, 0x46202120, 0xff6af022, 0x46202301, 0x21802207, 0xff64f022, 
+    0x46202300, 0x21802207, 0xff5ef022, 0x46202301, 0xe8bd2205, 0x21204010, 0xbf56f022, 0xd1800900, 
+    0xd1800800, 0x4e50b570, 0x21012200, 0xf6404605, 0x46030400, 0xf0224630, 0x2d01ff47, 0x4635d017, 
+    0x46280526, 0x4631221f, 0xff4cf022, 0xd00e2801, 0xb2241e64, 0xdcf42c00, 0x46204c44, 0xff2ef022, 
+    0x4100f440, 0xe8bd4620, 0xf0224070, 0xbd70bf2a, 0x2200483d, 0xb5102101, 0xff34f022, 0xbd10b240, 
+    0x4c39b570, 0x22104615, 0x1d24460e, 0xf44f4603, 0x4620017f, 0xff18f022, 0x46332200, 0x462021ff, 
+    0xff12f022, 0x4620462b, 0x4070e8bd, 0xf64f2208, 0xf0227100, 0xb570bf09, 0x22104c2b, 0x492c460d, 
+    0x46033420, 0xf0224620, 0x462bfeff, 0xe8bd4620, 0x22004070, 0x71fff64f, 0xbef6f022, 0x4c22b570, 
+    0x460d2204, 0x341c4603, 0x462021f0, 0xfeecf022, 0x4620462b, 0x4070e8bd, 0x210f2200, 0xbee4f022, 
+    0x41f0e92d, 0x461f4c18, 0x460e4615, 0x46033408, 0xf241220c, 0x46200100, 0xfed6f022, 0x46332208, 
+    0x01514620, 0xfed0f022, 0x462b2204, 0x462021f0, 0xfecaf022, 0x4620463b, 0x41f0e8bd, 0x21032200, 
+    0xbec2f022, 0x4c08b570, 0x21f0461d, 0x34184613, 0x46202204, 0xfeb8f022, 0x4620462b, 0x4070e8bd, 
+    0x210f2200, 0xbeb0f022, 0xd1800000, 0xd003517c, 0xffff0000, 0x41f0e92d, 0x460e1e52, 0xb2541e5b, 
+    0x4603b25d, 0xf04f2218, 0x4ffe51f8, 0xf0224638, 0x2210fe9b, 0xf44f4633, 0x463811f8, 0xfe94f022, 
+    0x46232208, 0x7100f641, 0xf0224638, 0x462bfe8d, 0xe8bd4638, 0x220041f0, 0xf022211f, 0xe92dbe85, 
+    0xf44f4ff8, 0x46802780, 0x461d2000, 0xa028f8dd, 0x460e4614, 0x0110f243, 0x46389000, 0xf891f7f8, 
+    0xf1041c70, 0xd0010001, 0xe011b188, 0x261ab108, 0x2100e00e, 0xf7f84638, 0x2100f873, 0xf7f84638, 
+    0x2100f86f, 0xf7f84638, 0xe8bdf86b, 0x241a8ff8, 0x9370f8df, 0xf1a92300, 0x2204090c, 0x21104648, 
+    0xfe52f022, 0x461a2300, 0xb270b261, 0xffa2f7ff, 0x461a2300, 0x46184619, 0xff84f7ff, 0x20012100, 
+    0xff4cf7ff, 0x464148cf, 0xf0223018, 0x48cdfe34, 0x22002301, 0x30244619, 0xfe36f022, 0x1f0048c9, 
+    0xfe26f022, 0x46384601, 0xf83af7f8, 0xf02248c5, 0x4601fe1f, 0xf7f84638, 0x4641f833, 0xf7f84638, 
+    0x4ec1f82f, 0x2000f240, 0xf7ff7831, 0xf8dffa5d, 0x4cbf82fc, 0x0000f898, 0xf994b948, 0xb1152000, 
+    0x4629980b, 0x2100e001, 0xf0014608, 0x2301fcd1, 0x2211464f, 0x04594648, 0xfe06f022, 0x46382301, 
+    0x46192200, 0xfe00f022, 0xb2c8f8df, 0x0000f44f, 0x4900f04f, 0xe0069000, 0x465a2101, 0xf7ff4668, 
+    0x2801faad, 0x221fd006, 0x46384649, 0xfdfaf022, 0xd0f12800, 0x0000f898, 0xf1bab970, 0xd0040f00, 
+    0x2000f994, 0x980b4629, 0xb12de004, 0xf9942100, 0x46082000, 0xfc9cf001, 0x46382301, 0x03d9220f, 
+    0xfdd2f022, 0xf2407831, 0xf7ff2000, 0xe76cfa0d, 0x43f8e92d, 0x2680f44f, 0x20004680, 0x460d4614, 
+    0x0120f243, 0x46309000, 0xffdbf7f7, 0xf1041c68, 0xd0010001, 0xe011b188, 0x251ab108, 0x2100e00e, 
+    0xf7f74630, 0x2100ffbd, 0xf7f74630, 0x2100ffb9, 0xf7f74630, 0xe8bdffb5, 0x241a83f8, 0x23004f81, 
+    0x22043f0c, 0x21104638, 0xfd9ef022, 0x46082100, 0xb26ab263, 0xfeeef7ff, 0x461a2300, 0x46184619, 
+    0xfed0f7ff, 0x20002101, 0xfe98f7ff, 0x46414875, 0xf0223018, 0x4873fd80, 0x22002301, 0x30244619, 
+    0xfd82f022, 0x1f00486f, 0xfd72f022, 0x46304601, 0xff86f7f7, 0xf022486b, 0x4601fd6b, 0xf7f74630, 
+    0x4641ff7f, 0xf7f74630, 0x4c67ff7b, 0x2800f240, 0x78214640, 0xf9a8f7ff, 0x46382301, 0x04592211, 
+    0xfd62f022, 0x46382301, 0x46192200, 0xfd5cf022, 0xf44f4d60, 0x90000000, 0x02061ead, 0x210fe006, 
+    0x4668462a, 0xfa0af7ff, 0xd0062801, 0x4631221f, 0xf0224638, 0x2800fd57, 0x2301d0f1, 0x220f4638, 
+    0xf02203d9, 0x7821fd41, 0xf7ff4640, 0xe792f97d, 0x4fffe92d, 0x469bb081, 0x46162000, 0x2980f44f, 
+    0xe9dd460f, 0xf8dd540e, 0xf2438044, 0x90000130, 0xf7f74648, 0x1c78ff46, 0x1c70d101, 0x1c68d002, 
+    0xe004d004, 0xd1021c68, 0xd0031c60, 0x1c60251a, 0xe010d010, 0x464c2100, 0xf7f74648, 0x2100ff21, 
+    0xf7f74620, 0x2100ff1d, 0xf7f74620, 0xb005ff19, 0x8ff0e8bd, 0xf8df241a, 0x2301a0cc, 0x0a0cf1aa, 
+    0x46502204, 0xf0222110, 0xb263fcff, 0xb271b26a, 0xf7ffb278, 0x2300fe4f, 0x4619461a, 0xf7ff4618, 
+    0x9810fe31, 0xfa4fb241, 0xf7fff08b, 0x4825fdf7, 0x30189901, 0xfcdff022, 0x23014822, 0x46192200, 
+    0xf0223024, 0x481ffce1, 0xf0221f00, 0x4601fcd1, 0x4648464c, 0xfee4f7f7, 0xf022481a, 0x4601fcc9, 
+    0xf7f74620, 0x9901fedd, 0xf7f74620, 0x4d16fed9, 0x2b00f240, 0x78294658, 0xf906f7ff, 0x4c144e13, 
+    0xb9587830, 0x2000f994, 0x0008ea5f, 0x4601d002, 0xe0019813, 0x46082100, 0xfb7af001, 0x46572301, 
+    0x46502211, 0xf0220459, 0x2301fcaf, 0x22004638, 0xf0224619, 0xf8dffca9, 0xf44fa01c, 0xf04f0000, 
+    0xe0094900, 0xd180000c, 0x0003227f, 0x00032396, 0x00032283, 0xd003517c, 0xe0069000, 0x46522100, 
+    0xf7ff4668, 0x2801f94b, 0x221fd006, 0x46384649, 0xfc98f022, 0xd0f12800, 0xb9787830, 0xb1209812, 
+    0x2000f994, 0x98134641, 0xf1b8e006, 0xd0050f00, 0xf9942100, 0x46082000, 0xfb3af001, 0x46382301, 
+    0x03d9220f, 0xfc70f022, 0x46587829, 0xf8acf7ff, 0xe92de75d, 0xf44f47f0, 0x461e2480, 0x46894617, 
+    0xf2434680, 0x46200160, 0xfe7bf7f7, 0x23014dcd, 0x21102204, 0xf0224628, 0xb27bfc57, 0xf188fa4f, 
+    0x4608461a, 0xfda6f7ff, 0x461a2300, 0x46184619, 0xfd88f7ff, 0xfa4fb271, 0xf7fff089, 0x48c1fd4f, 
+    0x21012300, 0x3030461a, 0xfc3ef022, 0x300848bd, 0xfc2ef022, 0x46204601, 0xfe42f7f7, 0x300c48b9, 
+    0xfc26f022, 0x46204601, 0xfe3af7f7, 0x46202100, 0xfe36f7f7, 0x46282300, 0x10612211, 0xfc24f022, 
+    0xe8bd4628, 0x230147f0, 0x46192200, 0xbc1cf022, 0xb51048ad, 0x7800b086, 0x2000b188, 0x21019004, 
+    0x22099005, 0xe9cd460b, 0x200b1002, 0x90004611, 0xf2409001, 0xf7ff2000, 0xb006fecb, 0x4ca3bd10, 
+    0x21012200, 0xf0224620, 0xb990fc24, 0x46202201, 0xf0222102, 0xb960fc1e, 0x46202202, 0xf0222104, 
+    0xb930fc18, 0x46202203, 0xf0222108, 0x2800fc12, 0x2001d0d4, 0x4894e7d2, 0xb087b530, 0xb9d07800, 
+    0x22004c92, 0x46202101, 0xfc03f022, 0x2201b988, 0x21024620, 0xfbfdf022, 0x2202b958, 0x21044620, 
+    0xfbf7f022, 0x2203b928, 0x21084620, 0xfbf1f022, 0x2401b108, 0x2400e000, 0x25019404, 0x9000200b, 
+    0x462b2209, 0x5402e9cd, 0x94054611, 0x02689001, 0xfe7ef7ff, 0x9000200c, 0x94042301, 0x9405220a, 
+    0x5402e9cd, 0x90014611, 0xf7ff02d8, 0xb007fe71, 0x220bbd30, 0x2000f240, 0xb5104611, 0xfdd8f7ff, 
+    0xf640220c, 0xe8bd0000, 0x46114010, 0x486ee5d0, 0x7800b51c, 0x4c6db9d0, 0x21012200, 0xf0224620, 
+    0xb988fbb8, 0x46202201, 0xf0222102, 0xb958fbb2, 0x46202202, 0xf0222104, 0xb928fbac, 0x46202203, 
+    0xf0222108, 0xb108fba6, 0xe0002401, 0xf2402400, 0x22092000, 0x46114623, 0x94019400, 0xfceff7ff, 
+    0x4623220a, 0xf6404611, 0x94000000, 0xf7ff9401, 0xbd1cfce6, 0x41ffe92d, 0x466c2300, 0x429a2200, 
+    0x2108d101, 0x2102e000, 0x1542eb00, 0xeb051e49, 0xe00305c3, 0xb91e5c6e, 0xb2491e49, 0xdaf92900, 
+    0x0582eb04, 0x1c521c49, 0x2a04b252, 0xdbe654e9, 0xb25b1c5b, 0xdbe12b04, 0x46182300, 0x0180eb04, 
+    0x42995609, 0x460bdd00, 0xb2401c40, 0xdbf52804, 0x22044d3c, 0x350821f0, 0xf0224628, 0x2300fb35, 
+    0x20004619, 0xd0054288, 0x0280eb04, 0x429a5652, 0x4613dd00, 0xb2401c40, 0xdbf32804, 0xb2491c49, 
+    0xdbee2904, 0x46282200, 0xf0222103, 0x4d2dfb1d, 0x46283548, 0xfb0cf022, 0x4601230f, 0x27012200, 
+    0xeb042000, 0x5cb60680, 0xfa07b916, 0x43b1f603, 0x1e5b1c40, 0x2804b240, 0x1c52dbf3, 0x2a04b252, 
+    0x4628dbee, 0xfaf7f022, 0x81ffe8bd, 0x41f0e92d, 0x46042300, 0x20004619, 0xd0054288, 0x0280eb04, 
+    0x429a5652, 0x4613dd00, 0xb2401c40, 0xdbf32804, 0xb2491c49, 0xdbee2904, 0x22084812, 0x30080151, 
+    0xfae2f022, 0x35484d0f, 0xf0224628, 0x231ffad1, 0x22004601, 0x20002601, 0x0780eb04, 0xb9175cbf, 
+    0xf703fa06, 0x1c4043b9, 0xb2401e5b, 0xdbf32804, 0xb2521c52, 0xdbee2a04, 0xe8bd4628, 0xf02241f0, 
+    0x0000baba, 0xd1800000, 0x00032396, 0xd0030024, 0x22002301, 0xb5104619, 0xf02248fe, 0x2300facc, 
+    0x210148fd, 0xf022461a, 0xe8bdfac6, 0x48fb4010, 0x0140f242, 0xbaa5f022, 0x4df7b570, 0x2203b28b, 
+    0x1ead4604, 0x46282108, 0xfab5f022, 0x4628b2a3, 0x4070e8bd, 0x21042202, 0xbaadf022, 0x4deeb570, 
+    0x2201b28b, 0x1ead4604, 0x46282102, 0xfaa3f022, 0x4628b2a3, 0x4070e8bd, 0x21012200, 0xba9bf022, 
+    0x4de5b570, 0x2206b283, 0x1ead460c, 0x46282140, 0xfa91f022, 0x4628b2a3, 0x4070e8bd, 0x21202205, 
+    0xba89f022, 0x48dcb283, 0xf2402208, 0x1e803100, 0xba81f022, 0x41f0e92d, 0x4690461f, 0x46084604, 
+    0x5606e9dd, 0xffeef7ff, 0x462043e1, 0xffd8f7ff, 0x46404639, 0xffc2f7ff, 0x46284631, 0x41f0e8bd, 
+    0xb570e7aa, 0x23014dcc, 0x03de220f, 0x46311ead, 0xf0224628, 0x2301fa60, 0x22074628, 0xf0222180, 
+    0x2001fa5a, 0xffcef7ff, 0xe00f0234, 0xf7fe4620, 0x1e04fe79, 0x4cc2dc0a, 0xf0224620, 0xf040fa2f, 
+    0x46200101, 0x4070e8bd, 0xba2bf022, 0x4631220f, 0xf0224628, 0x2800fa4e, 0xbd70d1e8, 0x230148b6, 
+    0x21102204, 0xf0221e80, 0xe92dba36, 0x4db241f0, 0x4000f500, 0xb281460f, 0x46283d14, 0xfa11f022, 
+    0x0400f44f, 0xe00e1226, 0xf7fe4620, 0x1e04fe4b, 0x4cabdc09, 0xf0224620, 0xf040fa01, 0x46200102, 
+    0xf9fff022, 0x220fe006, 0x46284631, 0xfa21f022, 0xd1e92800, 0xf2424639, 0xe8bd0000, 0xf7fe41f0, 
+    0xb570be33, 0x46164d9e, 0x4604220f, 0x460b3d9a, 0x0100f248, 0xf0224628, 0x220df9fe, 0xf2464633, 
+    0x46280100, 0xf9f7f022, 0x4628b2a3, 0x4070e8bd, 0xf6412200, 0xf02271ff, 0xb283b9ee, 0x2200488e, 
+    0x30602101, 0xb9e7f022, 0x41f0e92d, 0x461e4d8a, 0xf248b293, 0x35200400, 0x220f4688, 0x46214607, 
+    0xf0224628, 0xb2bbf9d8, 0x77fff240, 0x46392200, 0xf0224628, 0x4621f9d0, 0xb2b31eac, 0x220f4620, 
+    0xf9c9f022, 0xf388fa1f, 0x46204639, 0x41f0e8bd, 0xf0222200, 0xb570b9c0, 0x48794605, 0x46162301, 
+    0x460c3892, 0x461a2102, 0xf9b5f022, 0x0045ea44, 0xb2834c73, 0x71fff640, 0x22003c8e, 0xf0224620, 
+    0x2301f9aa, 0x220c4620, 0xf0220319, 0x4631f9a4, 0x4070e8bd, 0xf7fe2004, 0xb570bdc7, 0x48684605, 
+    0x46162301, 0x460c3898, 0x461a2102, 0xf993f022, 0x0045ea44, 0xb2834c62, 0x71fff640, 0x22003c96, 
+    0xf0224620, 0x2301f988, 0x220c4620, 0xf0220319, 0x4631f982, 0x4070e8bd, 0xf7fe2004, 0xe92dbda5, 
+    0x4d5847f0, 0x461f0004, 0x46894690, 0x0300f04f, 0xf240d418, 0x46282600, 0x46312209, 0xf96bf022, 
+    0x2301e00d, 0x22094631, 0xf0224628, 0x2300f964, 0x22094631, 0xf0224628, 0x1e64f95e, 0x2c00b224, 
+    0xe016dcef, 0x46282208, 0x46310156, 0xf953f022, 0x2301e00d, 0x22084631, 0xf0224628, 0x2300f94c, 
+    0x22084631, 0xf0224628, 0x1c64f946, 0x2c00b224, 0x2004dbef, 0xf7fe4639, 0x463afd67, 0x46484641, 
+    0x47f0e8bd, 0xb570e777, 0xb2834d33, 0x4604220b, 0xf6401cad, 0x46280100, 0xf92df022, 0x4628b2a3, 
+    0x4070e8bd, 0xf241220c, 0xf0220100, 0xe92db924, 0x4c2d41f0, 0x46062904, 0x2800f240, 0x4500f240, 
+    0x2905d002, 0xe009d004, 0x46032209, 0xe0024641, 0x4603220a, 0x46204629, 0xf90df022, 0x220c4f1e, 
+    0xf2414633, 0x1ebf0100, 0xf0224638, 0x220df904, 0xf2424633, 0x46380100, 0xf8fdf022, 0x4633220b, 
+    0x0100f640, 0xf0224638, 0x2202f8f6, 0x21044633, 0xf0221cb8, 0x4811f8f0, 0xf0223010, 0x220ff8cf, 
+    0x1d384633, 0x0100f248, 0xf8e5f022, 0x2300b98e, 0x220a4629, 0xf0224638, 0x2209f8de, 0x46414633, 
+    0xf0224620, 0x220af8d8, 0x46294633, 0xf0224620, 0xe00bf8d2, 0xd0020126, 0xd0035024, 0xd0020000, 
+    0xd003517e, 0xd0035092, 0xd0039000, 0xe8bd2001, 0xb57081f0, 0x23004df9, 0x46042203, 0x46282108, 
+    0xf8b9f022, 0x46282300, 0x21042202, 0xf8b3f022, 0x46282300, 0x461a2101, 0xf8adf022, 0x1cae2300, 
+    0x2101461a, 0xf0224630, 0xb374f8a6, 0xd0362c01, 0xd0342c02, 0xd1402c03, 0x46282300, 0x21102204, 
+    0xf899f022, 0x46302300, 0x21042202, 0xf893f022, 0x46282301, 0x21082203, 0xf88df022, 0x46282301, 
+    0x21042202, 0xf887f022, 0x46282301, 0x46192200, 0xf881f022, 0x22002301, 0x46304619, 0xf87bf022, 
+    0xe8bd2000, 0xf0154070, 0x2300b943, 0x22044628, 0xf0222110, 0x2300f870, 0x21042202, 0x2301e7ed, 
+    0x22044628, 0xf0222110, 0x2301f866, 0x22024630, 0xf0222104, 0x2001f860, 0xbd70e7e3, 0x5ff0e92d, 
+    0x48c64604, 0x4693469a, 0x46892200, 0xf240387c, 0xf24033c2, 0xf02271ff, 0xf8dff84e, 0x2c048300, 
+    0x0500f247, 0x1600f240, 0x087ef1a8, 0x6700f240, 0x2c05d002, 0xe01cd01a, 0x0f00f1b9, 0xf1bad119, 
+    0xd0160f03, 0x46402301, 0x46192200, 0xf833f022, 0x46402302, 0x21062201, 0xf82df022, 0x46312301, 
+    0x46402208, 0xf827f022, 0xe02f2302, 0x0f00f1bb, 0x2300d019, 0x22014640, 0xf0222106, 0x2300f81c, 
+    0x22094639, 0xf0224640, 0x2300f816, 0x22084631, 0xf0224640, 0x2300f810, 0x461a2101, 0xe8bd4640, 
+    0xf0225ff0, 0x2301b808, 0x22004640, 0xf0224619, 0x2303f802, 0x22014640, 0xf0212106, 0x2301fffc, 
+    0x22084631, 0xf0214640, 0x2303fff6, 0x22094639, 0xf0214640, 0x2301fff0, 0x220c4629, 0xe92de7de, 
+    0x4c8e5ff0, 0x4f8d4605, 0x3f503c5a, 0xf8dfb151, 0x2901822c, 0x76fff64f, 0x0836f1a8, 0x2902d00c, 
+    0xe060d020, 0x46202300, 0x461a2101, 0xffd3f021, 0x21012300, 0xe0cb461a, 0x46202301, 0x21042202, 
+    0xffc9f021, 0x46202300, 0x21082203, 0xffc3f021, 0x46402101, 0xffa5f021, 0x46314878, 0xf0213834, 
+    0xe040ffa0, 0x46202300, 0x21042202, 0xffb3f021, 0x46202301, 0x21082203, 0xffadf021, 0x1101f240, 
+    0xf0214640, 0x486dff8e, 0x38324631, 0xff89f021, 0x4631486a, 0xf0213830, 0x4868ff84, 0x382e4631, 
+    0xff7ff021, 0x46314865, 0xf021382c, 0x4863ff7a, 0x382a4631, 0xff75f021, 0x46314860, 0xf0213828, 
+    0x485eff70, 0x38264631, 0xff6bf021, 0x4631485b, 0xf0213824, 0x485aff66, 0xf2402208, 0x78037100, 
+    0xf0214638, 0x4e55ff78, 0x78fff640, 0xb14cf8df, 0x7afff240, 0x2d043e58, 0x0902f106, 0x0b7cf1ab, 
+    0x2d05d002, 0xe041d01f, 0xf6402200, 0x46413356, 0xf0214630, 0xf240ff60, 0x464135c2, 0x462b2200, 
+    0xf0214648, 0x2200ff58, 0x4651462b, 0xf0214658, 0x2303ff52, 0x0100f24f, 0x4638220c, 0xff4bf021, 
+    0x7394f240, 0x2200e01d, 0x439af640, 0x46304641, 0xff41f021, 0xf2402200, 0x46415304, 0xf0214648, 
+    0x2200ff3a, 0x2382f240, 0x46584651, 0xff33f021, 0xf24f2306, 0x220c0100, 0xf0214638, 0xf240ff2c, 
+    0x46417396, 0x46302200, 0xff25f021, 0x46202300, 0x21102204, 0xff1ff021, 0x46202301, 0x46192200, 
+    0xff19f021, 0x46382301, 0x46192200, 0xff13f021, 0x23204822, 0x213f2200, 0xf0213854, 0x2301ff0c, 
+    0x22024638, 0xf0212104, 0x2300ff06, 0x21102204, 0xe8bd4638, 0xf0215ff0, 0xe92dbefe, 0x4b1941f0, 
+    0x4c192802, 0x4e1a4d19, 0xd0044f1a, 0xd01e2801, 0x1c408808, 0x2a008008, 0x8819d030, 0xf0214816, 
+    0x4815fed0, 0x1c808821, 0xfecbf021, 0x88294812, 0xf0211d00, 0x4810fec6, 0x1d808831, 0xfec1f021, 
+    0xe8bd8839, 0x480c41f0, 0xf0213008, 0x2000beba, 0x80208018, 0x80308028, 0xe7dc8038, 0xd0035336, 
+    0x00032338, 0x00032380, 0x00032382, 0x00032384, 0x00032386, 0x00032388, 0xd0035164, 0xe92de5f7, 
+    0x4e4641f0, 0xf8df4604, 0x4f458114, 0x25013e16, 0x21014630, 0xfe95f021, 0xf0214640, 0x07c0fe8f, 
+    0x2100d00f, 0xf0214630, 0x2c01fe8c, 0xf7f6d1f0, 0xf000ffc3, 0xfa05010f, 0x7839f001, 0xfac4f7fe, 
+    0x4836e7e6, 0x0200f04f, 0xf04f4e34, 0x1e800101, 0xb1443e1a, 0xfe9df021, 0x0100ea25, 0xe8bd4630, 
+    0xf02141f0, 0xf021be6e, 0x4601fe94, 0x482be7f6, 0x38162100, 0xbe65f021, 0x41f0e92d, 0x88004605, 
+    0xf500460c, 0xb2814000, 0xf0214826, 0x8868fe5a, 0x4000f500, 0x4823b281, 0xf0211c80, 0x88a8fe52, 
+    0x4000f500, 0x481fb281, 0xf0211d00, 0x88e8fe4a, 0x4000f500, 0x481bb281, 0xf0211d80, 0x8820fe42, 
+    0xf5004d18, 0xb2814000, 0x46283508, 0xfe39f021, 0x1cae8860, 0x4000f500, 0x4630b281, 0xfe31f021, 
+    0x1d2f88a0, 0x4000f500, 0x4638b281, 0xfe29f021, 0x1dac88e0, 0x4000f500, 0x4620b281, 0xfe21f021, 
+    0xf0214628, 0x4630fe1b, 0xfe18f021, 0xf0214638, 0x4620fe15, 0x41f0e8bd, 0xbe10f021, 0xd0034024, 
+    0x0003227f, 0xd00351ac, 0x5ff0e92d, 0x460c2301, 0x46052102, 0x4efe461a, 0xf0214630, 0x48fdfe1c, 
+    0xb9287800, 0x46302301, 0x46192200, 0xfe13f021, 0xa3dcf8df, 0x220f2301, 0xf10a03df, 0x46390a02, 
+    0x465046d1, 0xfe07f021, 0x0800f246, 0x23014648, 0x220d4641, 0xfdfff021, 0x76fff641, 0x23294648, 
+    0x22004631, 0xfdf7f021, 0x0902f10a, 0x23004639, 0x220f4648, 0xfdeff021, 0x46412303, 0x4648220d, 
+    0xfde9f021, 0x46312305, 0x46482200, 0xfde3f021, 0x0902f109, 0x23014639, 0x220f4648, 0xfddbf021, 
+    0x46412301, 0x4648220d, 0xfdd5f021, 0x46312324, 0x46482200, 0xfdcff021, 0x0b02f109, 0x23014639, 
+    0x220f4658, 0xfdc7f021, 0x2c01b134, 0x2c02d006, 0x2c03d004, 0xe009d004, 0xe0022301, 0xe0002303, 
+    0x46412302, 0x4658220d, 0xfdb5f021, 0x46312300, 0x4658461a, 0xfdaff021, 0xb314f8df, 0x220f2300, 
+    0xf10b4639, 0x46580b0a, 0xfda5f021, 0x46442301, 0x4641220d, 0xf0214658, 0x2304fd9e, 0x22004631, 
+    0xf0214658, 0x4639fd98, 0x0702f10b, 0x46382300, 0xf021220f, 0x2301fd90, 0x220d4621, 0xf0214638, 
+    0x4cb3fd8a, 0xf6412200, 0x46317373, 0x462034f0, 0xfd81f021, 0xd0022d04, 0xd00f2d05, 0x230ee021, 
+    0x22004631, 0xf0214650, 0x2200fd76, 0x738ef641, 0x46204631, 0xfd6ff021, 0xe00d2309, 0x46312313, 
+    0x46502200, 0xfd67f021, 0xf6412200, 0x46317389, 0xf0214620, 0x230efd60, 0x22004631, 0xf0214648, 
+    0x489dfd5a, 0x28017800, 0x2300d114, 0x217f489b, 0xf021461a, 0x4c99fd50, 0x220823c8, 0x7100f64f, 
+    0x46201ca4, 0xfd47f021, 0x46202310, 0x21ff2200, 0xfd41f021, 0x5ff0e8bd, 0xf0002001, 0xe92dbc5a, 
+    0x4c8f47f0, 0x7100f641, 0xc234f8df, 0x35f0f240, 0xf24f3c96, 0x1ca70600, 0x0306f04f, 0xf04f2804, 
+    0xf10c0208, 0x46880902, 0xd02d4660, 0xfd23f021, 0x46202303, 0x210f2200, 0xfd1df021, 0x4629230c, 
+    0x46202204, 0xfd17f021, 0x46312304, 0x4620220c, 0xfd11f021, 0x46382303, 0x210f2200, 0xfd0bf021, 
+    0x4629230d, 0x46382204, 0xfd05f021, 0x46412302, 0x46482208, 0xfcfff021, 0x46384631, 0x47f0e8bd, 
+    0x220c2304, 0xbcf7f021, 0xfcf5f021, 0x46202303, 0x210f2200, 0xfceff021, 0x4629230b, 0x46202204, 
+    0xfce9f021, 0x46312304, 0x4620220c, 0xfce3f021, 0x46382303, 0x210f2200, 0xfcddf021, 0xe7d0230c, 
+    0x41fce92d, 0x20032400, 0xf7fe9401, 0x2002f9bd, 0xf9baf7fe, 0xf7fe2001, 0x2011f9b7, 0xf9b4f7fe, 
+    0xf7fe2012, 0x2001f9b1, 0xf897f7fe, 0xf7fe2002, 0x2004f894, 0xf891f7fe, 0x48522301, 0x0319220c, 
+    0xfcb9f021, 0x4d514850, 0x46287004, 0xfc96f021, 0x0102f020, 0xf0214628, 0x4628fc94, 0xfc8ef021, 
+    0x0104f020, 0xf0214628, 0x4849fc8c, 0x28016800, 0x4848d107, 0x0100f640, 0x48476004, 0xf0226800, 
+    0x4846fc67, 0xb1288800, 0x48452301, 0x46192200, 0xfc91f021, 0xff06f006, 0x78004842, 0x2001b910, 
+    0xfb51f7ff, 0xf6412200, 0x20040300, 0x94004611, 0xfccef001, 0x7801483c, 0xf7ff2000, 0x482cfb58, 
+    0x22012300, 0x38b02102, 0xfc75f021, 0x22084c28, 0x34522300, 0x46200151, 0xfc6df021, 0xf44f4d24, 
+    0x4f230100, 0x910135a8, 0x3fa8138e, 0x2103e00c, 0xa801462a, 0xf902f7fe, 0xd00c2801, 0x46312301, 
+    0x46202209, 0xfc57f021, 0x46382206, 0xf0212140, 0x2800fc60, 0x2200d1eb, 0x0400f242, 0x46104621, 
+    0xff92f014, 0x46212200, 0xf0054610, 0x4d1ffdac, 0x22032301, 0x46282108, 0xfc3df021, 0x46282300, 
+    0x21082203, 0xfc37f021, 0x78004819, 0xfa96f7fd, 0x23014d18, 0x4621220d, 0xf0214628, 0x2301fc2c, 
+    0x03de1daf, 0x220f4638, 0xf0214631, 0xe023fc24, 0xd00350d4, 0x00032396, 0x00032333, 0xd0030480, 
+    0xd0035332, 0xd003902c, 0x00032238, 0xd0034014, 0x00047f74, 0x00047ff0, 0x00032220, 0x0003227c, 
+    0xd28f20e0, 0x00032391, 0x0003227e, 0xd0036100, 0x0003227f, 0xd03c8306, 0x46312300, 0x4638220f, 
+    0xfbf9f021, 0x46212300, 0x4628220d, 0xfbf3f021, 0xf7ff2000, 0x2001f967, 0xf9c0f011, 0xfe60f011, 
+    0xf962f7f8, 0x23004c3d, 0x461a2101, 0xf0214620, 0x2300fbe2, 0x22014620, 0xf0212102, 0x2300fbdc, 
+    0x22024620, 0xf0212104, 0x2300fbd6, 0x22034620, 0xf0212108, 0xf647fbd0, 0x23007500, 0x22084629, 
+    0xf0211d20, 0x2300fbc8, 0x461a1da7, 0x4638217f, 0xfbc1f021, 0x46292300, 0x46382208, 0xfbbbf021, 
+    0x1ca021d2, 0xfb9df021, 0x46202100, 0xfb99f021, 0x23004823, 0x4631220f, 0xfbadf021, 0x81fce8bd, 
+    0xf04f2102, 0x0488422b, 0xf7f6b510, 0x2100fdf8, 0xf0042003, 0x2100ff29, 0xf0042006, 0xf001ff25, 
+    0x4818fb90, 0x28017800, 0x2301d107, 0x22024816, 0x4010e8bd, 0xf0212104, 0xbd10bb8e, 0xf04f2101, 
+    0x04c8422b, 0xf7f6b510, 0x2100fdda, 0xf0044608, 0x480cff0b, 0x28017800, 0x480bd10f, 0x22062303, 
+    0x11c0f240, 0xf0213008, 0x2300fb76, 0x22024806, 0x4010e8bd, 0xf0212104, 0xbd10bb6e, 0xd0035018, 
+    0xd28f201c, 0x00032362, 0xd003902c, 0x41f0e92d, 0x8464f8df, 0xb283461c, 0x22064615, 0x21c0460e, 
+    0x46404607, 0xfb57f021, 0x4640b2b3, 0x21302204, 0xfb51f021, 0x4640b2ab, 0x210c2202, 0xfb4bf021, 
+    0x4640b2a3, 0x21032200, 0xfb45f021, 0x8428f8df, 0x2206b2bb, 0x081cf108, 0x464021c0, 0xfb3bf021, 
+    0x4640b2b3, 0x21302204, 0xfb35f021, 0x4640b2ab, 0x210c2202, 0xfb2ff021, 0x4640b2a3, 0x21032200, 
+    0xfb29f021, 0x4ffdb2bb, 0x21032200, 0xf0214638, 0xb2b3fb22, 0x22024638, 0xf021210c, 0xb2abfb1c, 
+    0x22044638, 0xf0212130, 0xb2a3fb16, 0xe8bd4638, 0x220641f0, 0xf02121c0, 0xb570bb0e, 0x23014cee, 
+    0x46052200, 0x46193c40, 0xf0214620, 0x4aeafb04, 0x4620462b, 0x4070e8bd, 0x21013a2e, 0xba1bf022, 
+    0x460db570, 0xf7ff4604, 0x2200ffe8, 0x0022f854, 0xd90142a8, 0xbd702001, 0xb2521c52, 0xdbf52a04, 
+    0xbd702000, 0x4605b570, 0x230048db, 0x0100f248, 0x3834220f, 0xfadff021, 0x24004ed7, 0xf8353e12, 
+    0xf3c00014, 0xf4400009, 0xeb066180, 0xf0210044, 0x1c64fab8, 0x2c04b264, 0xbd70dbf1, 0x48ceb283, 
+    0x21012200, 0xf021383e, 0xe92dbac6, 0x4fca47f0, 0xf640b293, 0x46140800, 0x460d3f1e, 0x4606220b, 
+    0x46384641, 0xfab7f021, 0x0900f247, 0xb2ab4638, 0x220c4649, 0xfaaff021, 0x0a00f248, 0xb2b34638, 
+    0x220f4651, 0xfaa7f021, 0x46411cbf, 0x4638b2a3, 0xf021220b, 0xb2abfaa0, 0x220c4649, 0xf0214638, 
+    0xb2b3fa9a, 0x220f4651, 0xf0214638, 0x1cbffa94, 0xb2a34641, 0x220b4638, 0xfa8df021, 0x4649b2ab, 
+    0x4638220c, 0xfa87f021, 0x4651b2b3, 0x4638220f, 0xfa81f021, 0x4641b2a3, 0x220b1cbc, 0xf0214620, 
+    0xb2abfa7a, 0x220c4649, 0xf0214620, 0xb2b3fa74, 0x46204651, 0x47f0e8bd, 0xf021220f, 0xb510ba6c, 
+    0x489d4604, 0xf021380a, 0xf000fa49, 0x8020001f, 0x38084899, 0xfa42f021, 0x001ff000, 0x48968060, 
+    0xf0211f80, 0xf000fa3b, 0x80a0001f, 0x1f004892, 0xfa34f021, 0x001ff000, 0xbd1080e0, 0x41f0e92d, 
+    0x460c2b03, 0xd1084605, 0x1002f992, 0xf8252001, 0xf9920011, 0xf8251003, 0x48890011, 0x210f2200, 
+    0xfa47f021, 0x22008821, 0x80204408, 0x210f4885, 0xfa3ff021, 0x22008861, 0x80604408, 0x210f4882, 
+    0xfa37f021, 0x220088a1, 0x80a04408, 0x210f487f, 0xfa2ff021, 0x230188e1, 0x44082205, 0x4c7880e0, 
+    0x3c2e2120, 0xf0214620, 0x4e76fa16, 0x22052301, 0x21203e2e, 0xf0214630, 0x4f73fa0e, 0x22052301, 
+    0x21203f2e, 0xf0214638, 0xf8dffa06, 0x230181c0, 0xf1a82205, 0x2120082e, 0xf0214640, 0x2300f9fc, 
+    0x22054620, 0xf0212120, 0x2300f9f6, 0x22054630, 0xf0212120, 0x2300f9f0, 0x22054638, 0xf0212120, 
+    0x2300f9ea, 0x22054640, 0xf0212120, 0x4e5af9e4, 0x3e0a2400, 0x0014f815, 0x001ff000, 0x0120f040, 
+    0x0044eb06, 0xf9bdf021, 0xb2641c64, 0xdbf12c04, 0x81f0e8bd, 0x4605b5f0, 0xf5b52000, 0x46043f80, 
+    0x210fd301, 0x2107e000, 0x2701004a, 0xf302fa07, 0xfa001c4a, 0x4422f202, 0x42aa441a, 0xfa07d804, 
+    0xea46f601, 0x46140000, 0xea4fd003, 0xf1a10393, 0x29000101, 0x42aadb01, 0xbdf0d1ea, 0x460cb510, 
+    0x483d4601, 0xf0211e80, 0x4621f98c, 0xe8bd4840, 0xf0214010, 0x4838b986, 0x21022301, 0x3840461a, 
+    0xb999f021, 0x4d3bb570, 0x4614b283, 0x220c460e, 0x0100f24f, 0xf0214628, 0x2208f98e, 0xb2b34628, 
+    0xf0210151, 0x2c03f988, 0x2c02d013, 0x2c01d01b, 0x2c00d023, 0x2300d12b, 0x22044628, 0xf0212110, 
+    0x2300f97a, 0x461a2101, 0xe8bd4628, 0xf0214070, 0x2300b972, 0x22074628, 0xf0212180, 0x2300f96c, 
+    0x21082203, 0x2300e7f0, 0x22064628, 0xf0212140, 0x2300f962, 0x21042202, 0x2300e7e6, 0x22054628, 
+    0xf0212120, 0x2300f958, 0x21022201, 0xbd70e7dc, 0x4d18b570, 0x460c2a03, 0x2a02d013, 0x2a01d02c, 
+    0x2a00d034, 0xb283d13c, 0x22044628, 0xf0212110, 0x2200f942, 0x2101b2a3, 0xe8bd4628, 0xf0214070, 
+    0xb283b93a, 0x22074628, 0xf0212180, 0x2203f934, 0x2108b2a3, 0x0000e7f0, 0xd0030446, 0xd0035124, 
+    0xd003c2c2, 0xd003cac2, 0xd003d2c2, 0xd003dac2, 0xd0031012, 0xd0030024, 0x4628b283, 0x21402206, 
+    0xf919f021, 0xb2a32202, 0xe7d52104, 0x4628b283, 0x21202205, 0xf90ff021, 0xb2a32201, 0xe7cb2102, 
+    0x2200bd70, 0x48e5b283, 0xf0212101, 0xb570b904, 0x220c4ce3, 0x46034605, 0x0100f241, 0xf0214620, 
+    0x462bf8fa, 0xe8bd4620, 0x220a4070, 0x4100f240, 0xb8f1f021, 0x48da4603, 0x210f2200, 0xf0213048, 
+    0x48d7b8ea, 0x3048b510, 0xf8c8f021, 0x000ff000, 0x4603bd10, 0x220048d2, 0x31fff240, 0xf0211d00, 
+    0xb510b8da, 0x46042207, 0x46032180, 0xf02148cc, 0x48cbf8d2, 0x21012200, 0x30444623, 0xf8cbf021, 
+    0x46232200, 0x4010e8bd, 0x210148c6, 0xb8c3f021, 0x4cc3b570, 0x4605220d, 0xf2424603, 0x46200100, 
+    0xf8b9f021, 0x4620462b, 0x4070e8bd, 0xf640220b, 0xf0210100, 0xe92db8b0, 0x4db85fff, 0x46922301, 
+    0x3d20460c, 0x22064683, 0x21404628, 0xf8a3f021, 0x46282301, 0x21042202, 0xf89df021, 0x46282301, 
+    0x461a2102, 0xf897f021, 0x46282301, 0x46192200, 0xf891f021, 0x23011cae, 0x22064630, 0xf0212140, 
+    0x2301f88a, 0x22024630, 0xf0212104, 0x2301f884, 0x21024630, 0xf021461a, 0x2301f87e, 0x22004630, 
+    0xf0214619, 0xf105f878, 0x23010804, 0x22064647, 0x21404640, 0xf86ff021, 0x46382301, 0x21042202, 
+    0xf869f021, 0x46382301, 0x461a2102, 0xf863f021, 0x46382301, 0x46192200, 0xf85df021, 0x23011daf, 
+    0x22064638, 0xf0212140, 0x2301f856, 0x22024638, 0xf0212104, 0x2301f850, 0x21024638, 0xf021461a, 
+    0x2301f84a, 0x22004638, 0xf0214619, 0xf107f844, 0x23010904, 0x22024648, 0xf0212104, 0x2301f83c, 
+    0x21024648, 0xf021461a, 0x2301f836, 0x22004648, 0xf0214619, 0xf1bbf830, 0xd14c0f03, 0x2c02b10c, 
+    0xf1bad102, 0xd0260f01, 0xb2c09803, 0xd022281b, 0x46402100, 0xf805f021, 0x46382100, 0xf801f021, 
+    0x46282300, 0x21022201, 0xf815f021, 0x46282300, 0x461a2101, 0xf80ff021, 0x46302300, 0x21022201, 
+    0xf809f021, 0x46302300, 0x461a2101, 0xe8bdb004, 0xf0215ff0, 0x2100b800, 0xf0204628, 0x2100ffe2, 
+    0xf0204630, 0x2300ffde, 0x22024644, 0x21044640, 0xfff1f020, 0x46202300, 0x21022201, 0xffebf020, 
+    0x46382300, 0x21042202, 0xffe5f020, 0x46382300, 0x21022201, 0xe8bde7da, 0xb5709fff, 0x46144d50, 
+    0x460e2201, 0x460335f2, 0x46282102, 0xffd3f020, 0x46281e64, 0x2204b2a3, 0xf0202170, 0x4633ffcc, 
+    0xe8bd4628, 0x22004070, 0xf0202101, 0x4601bfc4, 0x30f44843, 0xbfa5f020, 0x30f44841, 0xbf9ef020, 
+    0x483fb283, 0xf2402200, 0x303071ff, 0xbfb3f020, 0x4c3bb510, 0x2200b283, 0x71fff643, 0x46203416, 
+    0xffa9f020, 0x46202301, 0xe8bd220e, 0x03994010, 0xbfa1f020, 0x460b2200, 0x46112801, 0x2802d00e, 
+    0x2804d009, 0x2808d004, 0x2203d109, 0xe0062108, 0x21042202, 0x2201e003, 0xe0002102, 0x482a2101, 
+    0xbf89f020, 0x460b2200, 0x46112801, 0x2802d010, 0x2804d00b, 0x2808d005, 0x220cd10b, 0x0100f247, 
+    0x2208e007, 0x7100f240, 0x2170e003, 0xe0002204, 0x481d2107, 0xf0201c80, 0x4601bf6e, 0x1d00481a, 
+    0xbf4ff020, 0x210f4818, 0xf0201f00, 0x4603bf4a, 0x22004815, 0x3828211f, 0xbf5df020, 0x48124601, 
+    0xf020382a, 0x4603bf3e, 0x2208480f, 0x7100f640, 0xf020382c, 0x4603bf50, 0x2200480b, 0x382c2101, 
+    0xbf49f020, 0xf04f7800, 0xb1100100, 0x38204803, 0x4802e001, 0xf020381a, 0x0000bf24, 0xd0030020, 
+    0xd0030400, 0xd0031012, 0xd00305de, 0x41f0e92d, 0x48fe4604, 0xfc21f7ff, 0x21004bfd, 0xf24a4dfd, 
+    0x4afa0700, 0x2662f249, 0xb9b05c60, 0x28126818, 0x2816d00d, 0xf995d00b, 0x28040000, 0x2805d007, 
+    0xf852d005, 0x42b00021, 0x2001d905, 0xf852e004, 0x42b80021, 0x2000d8f9, 0x1c495460, 0x2904b249, 
+    0xe8bddbe2, 0x200181f0, 0xf013b510, 0x2000ff6d, 0xfe27f7ff, 0xf2402100, 0xf7ff1000, 0x2201fd4f, 
+    0x20472100, 0xfcedf7fe, 0xf7ff204e, 0x48e2ff41, 0xf6407801, 0xe8bd0000, 0xf7fd4010, 0xe92dbb15, 
+    0xb0874ff3, 0x0b04f04f, 0x90022000, 0x90049003, 0x48da9005, 0x28037800, 0xf04fd101, 0x27000b02, 
+    0x48d7e081, 0x980857c4, 0xa802b1f8, 0x6014f930, 0xf930a804, 0xf2065014, 0xfb1612ff, 0xf240f006, 
+    0xfb1531fe, 0x428a0005, 0xf205d803, 0x428a12ff, 0x0100d921, 0xfceef7ff, 0x04f1b200, 0xf2f0fb91, 
+    0xfb9104e9, 0x1080f1f0, 0xf8dfe020, 0x23018318, 0x22004dc5, 0x46184621, 0x5800e9cd, 0xff39f7fb, 
+    0xf9b5a802, 0xf9b86040, 0xf8205040, 0xa8046014, 0x5014f820, 0x0280e7cf, 0xfcccf7ff, 0x05b1b200, 
+    0xf2f0fb91, 0xfb9105a9, 0x1140f1f0, 0xf44f4680, 0xea4f3000, 0xea4f1a62, 0xf6401961, 0xf7f60101, 
+    0xf44ff890, 0x46313000, 0xf87af7f6, 0x3000f44f, 0xf7f64629, 0xf44ff875, 0x46493000, 0xf870f7f6, 
+    0x3000f44f, 0xf7f64651, 0xf44ff86b, 0x46413000, 0xf866f7f6, 0xfa1f48a5, 0xeb00f18a, 0xf0200084, 
+    0x48a2fe50, 0xf189fa1f, 0xeb001c80, 0xf0200084, 0x489efe48, 0xf188fa1f, 0xeb003810, 0xf0200044, 
+    0x1c7ffe40, 0x455fb2ff, 0xaf7bf4ff, 0x23024c97, 0xf64f2208, 0x3c1e7100, 0xf0204620, 0x2201fe4c, 
+    0x210e4620, 0x234ff3c8, 0xfe45f020, 0x22009807, 0xb2832101, 0xf0204620, 0xb009fe3e, 0x8ff0e8bd, 
+    0xb5102000, 0xfec9f7ff, 0x20082101, 0xfe92f7ff, 0x20042101, 0xfe8ef7ff, 0x20022101, 0xfe8af7ff, 
+    0x46082101, 0xfe86f7ff, 0x20082103, 0xfe9af7ff, 0x20042103, 0xfe96f7ff, 0x20022103, 0xfe92f7ff, 
+    0x20012103, 0xfe8ef7ff, 0x3000f240, 0xfeb6f7ff, 0xf7ff2010, 0x2005feac, 0xfeb5f7ff, 0x4010e8bd, 
+    0xbea0f7ff, 0x21004872, 0xf020b510, 0xf7fffdea, 0xe8bdffc7, 0x201c4010, 0xbad5f7fd, 0x4ff0e92d, 
+    0xf8dfb087, 0x240091b0, 0x3bfff04f, 0x0814f10d, 0xae014625, 0x0a0cf10d, 0xf8d99500, 0x22003000, 
+    0x464f2001, 0xf7fbb261, 0xf828fe96, 0xf8265014, 0x683ab014, 0x46c42000, 0x1010f932, 0xda001e0b, 
+    0xf93c4259, 0x42b97014, 0x2b00dd06, 0x425bda00, 0x3014f82c, 0x0014f826, 0xb2001c40, 0xdbeb2880, 
+    0x0014f936, 0x46072300, 0xf932e008, 0x29001010, 0x4249da00, 0x44191c40, 0xb200b20b, 0xdbf42880, 
+    0x46d62000, 0x1ce3ea4f, 0xf82a4603, 0xe00d5014, 0x1010f932, 0xda002900, 0x44194249, 0x4563b20b, 
+    0xf82edd02, 0xe0030014, 0xb2001c40, 0xdcef4287, 0xb2241c64, 0xdbaf2c04, 0x22002001, 0xf9364611, 
+    0xf9363010, 0x42a34012, 0x4602dd00, 0x4010f93e, 0x5011f93e, 0xf9361b1b, 0x1b644011, 0xdd0042a3, 
+    0x1c404601, 0x2804b200, 0xf836dbe9, 0xf8360012, 0xf83a2011, 0xebc01011, 0x1a400042, 0xb2043808, 
+    0xdd6f2c00, 0xd00107e0, 0xb2241c64, 0x4e224d2a, 0xeb008828, 0x80280064, 0x10607831, 0xfb35f7fe, 
+    0x22017833, 0x1000f9b5, 0xf7fe4620, 0x7831fbe8, 0x1000f240, 0xf988f7fd, 0x0500f44f, 0x11f4f240, 
+    0xf7f54628, 0xf04fff5e, 0x46283134, 0xff48f7f5, 0x1004f9bd, 0xf7f54628, 0xf9bdff43, 0x46281006, 
+    0xff3ef7f5, 0x1008f9bd, 0xf7f54628, 0xf9bdff39, 0x4628100a, 0xff34f7f5, 0x100cf9bd, 0xf7f54628, 
+    0xf9bdff2f, 0x4628100e, 0x0000e018, 0x000331dc, 0x0003222c, 0x0003227e, 0x0003227f, 0x00032411, 
+    0x000323b4, 0x00035a7c, 0x0003527c, 0xd0030040, 0xd0030400, 0x00032224, 0x0003239a, 0xff10f7f5, 
+    0x1010f9bd, 0xf7f54628, 0xf9bdff0b, 0x46281012, 0xff06f7f5, 0x46284621, 0xff02f7f5, 0x462849ad, 
+    0xfefef7f5, 0xe6c9b007, 0x47fce92d, 0x92a8f8df, 0x46062500, 0x240046a8, 0xd10242ac, 0x0000f04f, 
+    0xda02e004, 0x0001f104, 0x4620e000, 0x7000f8d9, 0xfa80fa4f, 0x463b4629, 0xf04f4652, 0xf8cd0001, 
+    0xf7fb8000, 0xeb06fd98, 0x5d400084, 0x2180b958, 0xf0214638, 0x2300fcbd, 0x20014652, 0xe9cd4629, 
+    0xf7fb7800, 0x1c64fcd1, 0x2c04b264, 0x1c6ddbd4, 0x2d04b26d, 0x2400dbcf, 0x20004621, 0xd0044288, 
+    0x0280eb06, 0xb1025c52, 0x1c402401, 0x2804b240, 0x1c49dbf4, 0x2904b249, 0x4e88dbef, 0xf0204630, 
+    0xb200fc9d, 0xf040b16c, 0x24000507, 0xeb06b2a9, 0xf0200044, 0x1c64fc96, 0x2c04b264, 0xe8bddbf6, 
+    0xf02087fc, 0xe7f00507, 0x4ff0e92d, 0x275a487c, 0x21012200, 0xf020b087, 0xb240fc95, 0x20009005, 
+    0xfd30f7fd, 0x91d0f8df, 0xf10d2600, 0x46b00b04, 0x42b42400, 0xf04fd102, 0xe0040000, 0xf104da02, 
+    0xe0000001, 0xf8d94620, 0xb242a000, 0x46534631, 0x0001f04f, 0x8000f8cd, 0xfd2df7fb, 0x46502500, 
+    0x01e92280, 0xf8bcf015, 0xdc0342b8, 0xb26d1e6d, 0xdaf42d00, 0x0084eb0b, 0x42b41c6d, 0xd1015585, 
+    0x55812101, 0xb2641c64, 0xdbd22c04, 0xb2761c76, 0xdbcd2e04, 0xf7ffa801, 0xa801ff57, 0xf946f7fe, 
+    0xf7fd9805, 0xf44ffcef, 0xf2400400, 0x462011f4, 0xfe57f7f5, 0xf0204851, 0x4601fc31, 0xf7f54620, 
+    0x484efe3f, 0xf0201c80, 0x4601fc29, 0xf7f54620, 0x484afe37, 0xf0201d00, 0x4601fc21, 0xf7f54620, 
+    0x4846fe2f, 0xf0201d80, 0x4601fc19, 0xf7f54620, 0x4843fe27, 0xf0203008, 0x4601fc0b, 0xf7f54620, 
+    0x483ffe1f, 0xf0203048, 0x4601fc03, 0xf7f54620, 0x4938fe17, 0xf7f54620, 0xe713fe13, 0x4ff8e92d, 
+    0x90d4f8df, 0x46162400, 0x4607460d, 0xf04f46a0, 0xf8cd3aff, 0xf8d98000, 0x22003000, 0xb2612001, 
+    0xfcb9f7fb, 0x8014f825, 0xa014f827, 0x464a2000, 0xa014f826, 0xf9316811, 0x29001010, 0x460bdb01, 
+    0x424be000, 0xc014f935, 0xdd0d4563, 0xda002900, 0xf8254249, 0xf8271014, 0x68110014, 0x1010f831, 
+    0x31c0f3c1, 0x1014f826, 0xb2001c40, 0xdbe12880, 0xb2241c64, 0xdbcc2c04, 0x8ff8e8bd, 0x43f8e92d, 
+    0x21004d15, 0x9100460a, 0x2001b241, 0xf7fb682b, 0x2200fc82, 0x8000f8d5, 0x46104613, 0x46144611, 
+    0x5014f838, 0xf505fb15, 0x195217ee, 0xfba54173, 0x17e7ce04, 0xe604fb06, 0x6507fb05, 0x0000eb1c, 
+    0x1c644169, 0x2c80b224, 0xf01fdbea, 0xb200ed22, 0x83f8e8bd, 0xdcba01f5, 0x00032224, 0xd0030000, 
+    0xd1800000, 0x5fffe92d, 0x4df92301, 0x460c220e, 0x4628039f, 0xf0204639, 0xf241fb9e, 0x46280900, 
+    0x46492301, 0xf020220c, 0xf640fb96, 0x46280a00, 0x46512301, 0xf020220b, 0xf240fb8e, 0x46284b00, 
+    0x46592301, 0xf020220a, 0x2301fb86, 0x22094628, 0xf0200259, 0x2208fb80, 0x23014628, 0xf0200151, 
+    0x2301fb7a, 0x22074628, 0xf0202180, 0x2301fb74, 0x22064628, 0xf0202140, 0x1caefb6e, 0x23014639, 
+    0x220e4630, 0xfb67f020, 0x46492301, 0x4630220c, 0xfb61f020, 0x46512301, 0x4630220b, 0xfb5bf020, 
+    0x46592301, 0x4630220a, 0xfb55f020, 0x46302301, 0x02592209, 0xfb4ff020, 0x46302208, 0x01512301, 
+    0xfb49f020, 0x46302301, 0x21802207, 0xfb43f020, 0x46302301, 0x21402206, 0xfb3df020, 0x0804f105, 
+    0x23014639, 0x220e4640, 0xfb35f020, 0x46492301, 0x4640220c, 0xfb2ff020, 0x46512301, 0x4640220b, 
+    0xfb29f020, 0x46592301, 0x4640220a, 0xfb23f020, 0x46402301, 0x02592209, 0xfb1df020, 0x46402208, 
+    0x01512301, 0xfb17f020, 0x46402301, 0x21802207, 0xfb11f020, 0x46402301, 0x21402206, 0xfb0bf020, 
+    0x1daf4639, 0x46382301, 0xf020220e, 0x2301fb04, 0x220c4649, 0xf0204638, 0x2301fafe, 0x220b4651, 
+    0xf0204638, 0x2301faf8, 0x220a4659, 0xf0204638, 0x2301faf2, 0x22094638, 0xf0200259, 0x2208faec, 
+    0x23014638, 0xf0200151, 0x2301fae6, 0x22074638, 0xf0202180, 0x2301fae0, 0x22064638, 0xf0202140, 
+    0x2301fada, 0x22054628, 0xf0202120, 0x2301fad4, 0x22034628, 0xf0202108, 0x2301face, 0x21024628, 
+    0xf020461a, 0x2301fac8, 0x22054630, 0xf0202120, 0x2301fac2, 0x22034630, 0xf0202108, 0x2301fabc, 
+    0x21024630, 0xf020461a, 0x2301fab6, 0x22054640, 0xf0202120, 0x2301fab0, 0x22034640, 0xf0202108, 
+    0x2301faaa, 0x21024640, 0xf020461a, 0x2301faa4, 0x22054638, 0xf0202120, 0x2301fa9e, 0x22034638, 
+    0xf0202108, 0x2301fa98, 0x21024638, 0xf020461a, 0x2301fa92, 0x22044628, 0xf0202110, 0x2301fa8c, 
+    0x22024628, 0xf0202104, 0x2301fa86, 0x22004628, 0xf0204619, 0x2301fa80, 0x22044630, 0xf0202110, 
+    0x2301fa7a, 0x22024630, 0xf0202104, 0x2301fa74, 0x22004630, 0xf0204619, 0x2301fa6e, 0x22044640, 
+    0xf0202110, 0x2301fa68, 0x22024640, 0xf0202104, 0x2301fa62, 0x22004640, 0xf0204619, 0x2301fa5c, 
+    0x22044638, 0xf0202110, 0x2301fa56, 0x22024638, 0xf0202104, 0x2301fa50, 0x22004638, 0xf0204619, 
+    0x9800fa4a, 0xd1412803, 0x2c02b10c, 0x9802d102, 0xd0522801, 0xb2c09803, 0xd04e281b, 0x46282300, 
+    0x21082203, 0xfa37f020, 0x46282300, 0x21042202, 0xfa31f020, 0x46282300, 0x21022201, 0xfa2bf020, 
+    0x46282300, 0x461a2101, 0xfa25f020, 0x46302300, 0x21082203, 0xfa1ff020, 0x46302300, 0x21042202, 
+    0xfa19f020, 0x46302300, 0x21022201, 0xfa13f020, 0x46302300, 0x461a2101, 0xfa0df020, 0x46402100, 
+    0xf9eff020, 0x46382100, 0xf9ebf020, 0x23014c28, 0x34082202, 0x46202104, 0xf9fdf020, 0x46202301, 
+    0x461a2102, 0xf9f7f020, 0x4620b004, 0x22002301, 0xe8bd4619, 0xf0205ff0, 0x2100b9ee, 0xf0204628, 
+    0x2100f9d0, 0xf0204630, 0x2300f9cc, 0x22054644, 0x21204640, 0xf9dff020, 0x46202300, 0x21102204, 
+    0xf9d9f020, 0x46202300, 0x21082203, 0xf9d3f020, 0x46202300, 0x21042202, 0xf9cdf020, 0x46382300, 
+    0x21202205, 0xf9c7f020, 0x46382300, 0x21102204, 0xf9c1f020, 0x46382300, 0x21082203, 0xf9bbf020, 
+    0x46382300, 0x21042202, 0xf9b5f020, 0x0000e7ae, 0xd0031000, 0x46032200, 0x217f482d, 0xb9abf020, 
+    0x4604b510, 0xf64f482a, 0x302471ff, 0xf989f020, 0x21004827, 0xf0203026, 0x4825f984, 0x2200b2a3, 
+    0xe8bd2101, 0x30224010, 0xb995f020, 0x41f0e92d, 0x461d4c1f, 0x4616b283, 0x460f1ca4, 0x46202206, 
+    0xf02021c0, 0xb2bbf988, 0x22044620, 0xf0202130, 0xb2b3f982, 0x22024620, 0xf020210c, 0xb2abf97c, 
+    0xe8bd4620, 0x220041f0, 0xf0202103, 0xb283b974, 0x2200480f, 0x1d002101, 0xb96df020, 0x0004b570, 
+    0x2300d013, 0x22014d0a, 0x21023522, 0xf0204628, 0xb2a3f962, 0x22004628, 0xf0202101, 0x2104f95c, 
+    0xe8bd1da8, 0xf0204070, 0x2301b93c, 0x0000e7ea, 0xd003100e, 0x5fffe92d, 0xa248f8df, 0x46812500, 
+    0x489146ab, 0x0045eb00, 0xf0209003, 0xb207f927, 0x42ac2400, 0xf04fd102, 0xe0040000, 0xf104da02, 
+    0xe0000001, 0x42ac4620, 0x9002b240, 0xf04fd102, 0xe0010608, 0x0602f04f, 0xf04fd102, 0xe00b0106, 
+    0xf04fdd02, 0xe0010001, 0x0000f04f, 0x0000eba4, 0x0040ea4f, 0x0104f1c0, 0x0301f04f, 0x1244eb09, 
+    0x0001f1a6, 0x02c5eb02, 0x0c06eb01, 0x5c11e01e, 0xd01d2901, 0xdb102803, 0xd10e2c03, 0xd10c2d03, 
+    0x1000f819, 0xeb09b9a1, 0xf8910100, 0xf1bee028, 0xd10d0f00, 0x1050f891, 0xebacb951, 0x1e490100, 
+    0xf101fa03, 0x1e40438f, 0xb240b23f, 0xdade2800, 0xf8cd1c40, 0xfa4fb000, 0xf8daf880, 0x9a023000, 
+    0x46292000, 0xf997f7fb, 0xda1245b0, 0x0008eba6, 0x2000f8da, 0x01c14656, 0x2008eb02, 0xf8b8f021, 
+    0x23006831, 0x1b00e9cd, 0x46299a02, 0xf7fb4618, 0x1c64f8cb, 0x2c04b264, 0xb2b9db8b, 0xf0209803, 
+    0x1c6df8b0, 0x2d04b26d, 0xaf7bf6ff, 0x9fffe8bd, 0x4ff0e92d, 0xb0a1484d, 0x28507800, 0x2020d201, 
+    0x2010e000, 0x46802200, 0x21014849, 0xf8aaf020, 0xfb80fa4f, 0xf7fd2000, 0xf8dff945, 0x26009108, 
+    0x240046b2, 0xd10242b4, 0x0000f04f, 0xda02e004, 0x0001f104, 0x4620e000, 0xb24242b4, 0x2508d101, 
+    0x2502e000, 0xa000f8cd, 0x3000f8d9, 0x464f2000, 0xf7fb4631, 0xa801f940, 0xeb0046b9, 0x1e6d1044, 
+    0x07c6eb00, 0xf8d9e00d, 0x01e90000, 0xf0142280, 0x4540fcc7, 0x2001dd01, 0x2000e000, 0x1e6d5578, 
+    0x2d00b26d, 0x1c64daef, 0x2c04b264, 0x1c76dbca, 0x2e04b276, 0xa801dbc5, 0xff1cf7ff, 0xf7fda801, 
+    0x4658fce9, 0xf8fef7fd, 0x0400f44f, 0x11f4f240, 0xf7f54620, 0x481cfa66, 0xf840f020, 0x46204601, 
+    0xfa4ef7f5, 0x1c804818, 0xf838f020, 0x46204601, 0xfa46f7f5, 0x1d004814, 0xf830f020, 0x46204601, 
+    0xfa3ef7f5, 0x1d804810, 0xf828f020, 0x46204601, 0xfa36f7f5, 0x3008480e, 0xf81af020, 0x46204601, 
+    0xfa2ef7f5, 0x3048480a, 0xf812f020, 0x46204601, 0xfa26f7f5, 0x46204907, 0xfa22f7f5, 0xe8bdb021, 
+    0x00008ff0, 0x00032224, 0xd0031000, 0x00032398, 0xd1800000, 0xdcba01f5, 0x23004831, 0xf248220f, 
+    0xb5100100, 0xf817f020, 0x7801482e, 0xf7fc2040, 0x2300fc3b, 0x2201482c, 0x4010e8bd, 0xf0202102, 
+    0x210fb80a, 0x422bf04f, 0x2000f44f, 0xf7f5b508, 0xf7fffa56, 0x2100ffe1, 0xf0004608, 0x2300f8a2, 
+    0x21014822, 0xf01f461a, 0x2000fff6, 0x0200f242, 0x46014603, 0xf0009000, 0xbd08f83b, 0x481a4601, 
+    0x29043022, 0x2905d006, 0x2300d006, 0x21032200, 0xbfe1f01f, 0xe7f92303, 0xe7f72302, 0xf7ffb508, 
+    0x2101ffed, 0xf0004608, 0x2301f87c, 0x2102480e, 0xf01f461a, 0x2301ffd0, 0x2200480c, 0xf01f4619, 
+    0x2000ffca, 0x7203f247, 0xf6402317, 0x90004102, 0x1084f240, 0xf80cf000, 0x4008e8bd, 0xbd82f003, 
+    0xd0035026, 0x0003227f, 0xd03c8310, 0xd003529a, 0x47f0e92d, 0x460f4c88, 0x4698b281, 0x9020f8dd, 
+    0x46204616, 0xff8df01f, 0x0a02f104, 0x46502206, 0xf01f2140, 0xb2b9ffae, 0x46504605, 0xff81f01f, 
+    0x462b2206, 0x46502140, 0xff95f01f, 0xb2b11d25, 0xf01f4628, 0x1da6ff76, 0xf188fa1f, 0xf01f4630, 
+    0x1d2fff70, 0xf189fa1f, 0xf01f4638, 0xb672ff6a, 0xf8df2301, 0xf24891c4, 0xf1090800, 0x4641090c, 
+    0x4648220f, 0xff77f01f, 0x46412300, 0x4648220f, 0xff71f01f, 0x2100b662, 0xf01f4620, 0x2100ff52, 
+    0xf01f4650, 0x2100ff4e, 0xf01f4628, 0x2100ff4a, 0xf01f4630, 0x4638ff46, 0x47f0e8bd, 0xf01f2100, 
+    0xb570bf40, 0x220a4c5c, 0x4606460d, 0x46033410, 0x4100f240, 0xf01f4620, 0x2209ff4e, 0xf2404633, 
+    0x46202100, 0xff47f01f, 0x4620462b, 0x4070e8bd, 0x21042202, 0xbf3ff01f, 0x23004850, 0x21102204, 
+    0xf01fb510, 0x4c4cff38, 0x220e2301, 0x03993410, 0xf01f4620, 0x2301ff30, 0x22064620, 0xf01f2140, 
+    0x2301ff2a, 0x22004846, 0xf01f4619, 0x4c45ff24, 0x22042301, 0x46202110, 0xff1df01f, 0x46202301, 
+    0x21042202, 0xff17f01f, 0x46202301, 0x21082203, 0xff11f01f, 0x46202300, 0xe8bd2204, 0x21104010, 
+    0xbf09f01f, 0x5ff0e92d, 0x90dcf8df, 0x0a00ea5f, 0x461e4f36, 0x460c4615, 0x1b00f240, 0x7838d003, 
+    0xd00e2801, 0x2300e025, 0x22044648, 0xf01f2110, 0x7838fef2, 0xd14d2801, 0x482d2300, 0x46592208, 
+    0x482be044, 0x21012200, 0xf01f309e, 0xf8dffef2, 0x280180a4, 0x0700f248, 0x4825d017, 0x22082300, 
+    0xf01f4659, 0x2300fed8, 0x220f4639, 0xf01f4640, 0x2c03fed2, 0x2c05d015, 0x2c04d013, 0x2c02d011, 
+    0x2c01d00b, 0x2300d009, 0x4819e01d, 0x22082301, 0xf01f4659, 0x2301fec0, 0xf045e7e6, 0xf0460504, 
+    0x48150604, 0x07c07800, 0x4c14d10c, 0x21702204, 0x4620462b, 0xfeaff01f, 0x46332207, 0x01d14620, 
+    0xfea9f01f, 0x46484653, 0x21102204, 0x5ff0e8bd, 0xbea1f01f, 0x9ff0e8bd, 0xd03c8300, 0xd03c8004, 
+    0xd03d0004, 0xd003529a, 0xd03c809e, 0x00032362, 0xd2154082, 0xd213a124, 0x00032228, 0xd03d4098, 
+    0x41f0e92d, 0x28014cfe, 0x2800f240, 0x0500f248, 0x2100d051, 0xf01f4620, 0x2301fe64, 0x0100f641, 
+    0x4620220b, 0xfe77f01f, 0x46202301, 0x029e220a, 0xf01f4631, 0x2301fe70, 0x220e4620, 0x4639039f, 
+    0xfe69f01f, 0x46292301, 0x4620220f, 0xfe63f01f, 0x46292300, 0x4620220f, 0xfe5df01f, 0x210011ed, 
+    0xf7fc4628, 0x2300fa81, 0x220a4631, 0xf01f4620, 0x2100fe52, 0xf7fc4628, 0x2300fa77, 0x220e4639, 
+    0xf01f4620, 0x2300fe48, 0x22044620, 0xf01f2110, 0x2300fe42, 0x22034620, 0xf01f2108, 0x2100fe3c, 
+    0xf7fc4628, 0x2300fa61, 0x22094641, 0xe8bd4620, 0xf01f41f0, 0x2301be30, 0x22034620, 0xf01f2108, 
+    0x2300fe2a, 0x22044620, 0xf01f2110, 0x2301fe24, 0x22094641, 0xf01f4620, 0x2301fe1e, 0x220f4629, 
+    0x220be7e4, 0x48c74603, 0x0100f641, 0xbe13f01f, 0x220fb510, 0xf0004604, 0x48c20301, 0x0100f248, 
+    0xfe09f01f, 0x220048bf, 0xf3c42101, 0xe8bd0340, 0x1c804010, 0xbdfff01f, 0x41f0e92d, 0xf2404cb9, 
+    0xf2482800, 0x3c100500, 0xd0512801, 0x46202100, 0xfdd7f01f, 0xf6412301, 0x220b0100, 0xf01f4620, 
+    0x2301fdea, 0x220a4620, 0x4631029e, 0xfde3f01f, 0x46202301, 0x039f220e, 0xf01f4639, 0x2301fddc, 
+    0x220f4629, 0xf01f4620, 0x2300fdd6, 0x220f4629, 0xf01f4620, 0x11edfdd0, 0x46282100, 0xf9f4f7fc, 
+    0x46312300, 0x4620220a, 0xfdc5f01f, 0x46282100, 0xf9eaf7fc, 0x46392300, 0x4620220e, 0xfdbbf01f, 
+    0x46202300, 0x21102204, 0xfdb5f01f, 0x46202300, 0x21082203, 0xfdaff01f, 0x46282100, 0xf9d4f7fc, 
+    0x46412300, 0x46202209, 0x41f0e8bd, 0xbda3f01f, 0x46202301, 0x21082203, 0xfd9df01f, 0x46202300, 
+    0x21102204, 0xfd97f01f, 0x46412301, 0x46202209, 0xfd91f01f, 0x46292301, 0xe7e4220f, 0x46032209, 
+    0xf2404880, 0xf01f6100, 0x220dbd86, 0x487d4603, 0x0100f246, 0xbd7ff01f, 0x41f0e92d, 0x28014c7a, 
+    0x2800f240, 0x0500f248, 0x2100d051, 0xf01f4620, 0x2301fd58, 0x0100f641, 0x4620220b, 0xfd6bf01f, 
+    0x46202301, 0x029e220a, 0xf01f4631, 0x2301fd64, 0x220e4620, 0x4639039f, 0xfd5df01f, 0x46292301, 
+    0x4620220f, 0xfd57f01f, 0x46292300, 0x4620220f, 0xfd51f01f, 0x210011ed, 0xf7fc4628, 0x2300f975, 
+    0x220a4631, 0xf01f4620, 0x2100fd46, 0xf7fc4628, 0x2300f96b, 0x220e4639, 0xf01f4620, 0x2300fd3c, 
+    0x22044620, 0xf01f2110, 0x2300fd36, 0x22034620, 0xf01f2108, 0x2100fd30, 0xf7fc4628, 0x2300f955, 
+    0x22094641, 0xe8bd4620, 0xf01f41f0, 0x2301bd24, 0x22034620, 0xf01f2108, 0x2300fd1e, 0x22044620, 
+    0xf01f2110, 0x2301fd18, 0x22094641, 0xf01f4620, 0x2301fd12, 0x220f4629, 0x220be7e4, 0x48434603, 
+    0x0100f641, 0xbd07f01f, 0x220fb510, 0xf0004604, 0x483e0301, 0x0100f248, 0xfcfdf01f, 0x2200483b, 
+    0xf3c42101, 0xe8bd0340, 0x1c804010, 0xbcf3f01f, 0x41f0e92d, 0xf2404c35, 0xf2482800, 0x3c100500, 
+    0xd0512801, 0x46202100, 0xfccbf01f, 0xf6412301, 0x220b0100, 0xf01f4620, 0x2301fcde, 0x220a4620, 
+    0x4631029e, 0xfcd7f01f, 0x46202301, 0x039f220e, 0xf01f4639, 0x2301fcd0, 0x220f4629, 0xf01f4620, 
+    0x2300fcca, 0x220f4629, 0xf01f4620, 0x11edfcc4, 0x46282100, 0xf8e8f7fc, 0x46312300, 0x4620220a, 
+    0xfcb9f01f, 0x46282100, 0xf8def7fc, 0x46392300, 0x4620220e, 0xfcaff01f, 0x46202300, 0x21102204, 
+    0xfca9f01f, 0x46202300, 0x21082203, 0xfca3f01f, 0x46282100, 0xf8c8f7fc, 0x46412300, 0x46202209, 
+    0x41f0e8bd, 0xbc97f01f, 0x46202301, 0x21082203, 0xfc91f01f, 0x46202300, 0x21102204, 0x0000e008, 
+    0xd003d800, 0xd003d010, 0xd003c800, 0xd003c010, 0xfc81f01f, 0x46412301, 0x46202209, 0xfc7bf01f, 
+    0x46292301, 0xe7da220f, 0x46032209, 0xf24048ff, 0xf01f6100, 0x220dbc70, 0x48fc4603, 0x0100f246, 
+    0xbc69f01f, 0x43f8e92d, 0x00044df9, 0x2600f240, 0x2c04d001, 0x2300d114, 0x22094631, 0xf01f4628, 
+    0x2300fc5a, 0x22074628, 0xf01f2180, 0x2000fc54, 0xffe1f7ff, 0xf7ff2003, 0x2001ffd7, 0xff58f7ff, 
+    0xf2402c01, 0xf2404700, 0xd0011800, 0xd1142c04, 0x46392300, 0x4628220a, 0xfc3df01f, 0x46412300, 
+    0x46282208, 0xfc37f01f, 0xf7ff2000, 0x2003ff2d, 0xff23f7ff, 0xf7ff2001, 0x4ddefeaf, 0xd0012c02, 
+    0xd1142c04, 0x46312300, 0x46282209, 0xfc23f01f, 0x46282300, 0x21802207, 0xfc1df01f, 0xf7ff2000, 
+    0x2003fe94, 0xfe8af7ff, 0xf7ff2001, 0x2c03fe15, 0x2c04d001, 0x2300d11e, 0x220a4639, 0xf01f4628, 
+    0x2300fc0a, 0x22084641, 0xf01f4628, 0x2000fc04, 0xfdeef7ff, 0xf7ff2003, 0x2001fde4, 0xfd70f7ff, 
+    0xd1072c04, 0x90002000, 0x46032202, 0x20122101, 0xf986f011, 0x83f8e8bd, 0x5ff0e92d, 0x220d48be, 
+    0x0100f242, 0xfbf5f01f, 0x48bcb2c4, 0xf04f4fb9, 0xf8df0301, 0xf04f92e0, 0xf8df0209, 0x3f12a2e4, 
+    0xf1097800, 0xf8df0908, 0xf10ab2dc, 0xf8df0a1a, 0x280082d0, 0xf1ab4eb4, 0xf2400506, 0xd07c2100, 
+    0x381048aa, 0xfbc7f01f, 0x48b02301, 0x02592209, 0xfbc1f01f, 0xf2402300, 0x22092100, 0xf01f4638, 
+    0x2300fbba, 0x2100f240, 0x46402209, 0xfbb3f01f, 0x2301489e, 0x21102204, 0xf01f3810, 0x489bfbac, 
+    0x22032301, 0x38102108, 0xfba5f01f, 0x2301489f, 0x21102204, 0xfb9ff01f, 0x2301489c, 0x21082203, 
+    0xfb99f01f, 0x46382300, 0x21102204, 0xfb93f01f, 0x46382300, 0x21082203, 0xfb8df01f, 0x46402300, 
+    0x21102204, 0xfb87f01f, 0x46402300, 0x21082203, 0xfb81f01f, 0x23014886, 0x46192200, 0xf01f3008, 
+    0x488afb7a, 0x22002301, 0x301a4619, 0xfb73f01f, 0x46482300, 0x461a2101, 0xfb6df01f, 0x46502300, 
+    0x461a2101, 0xfb67f01f, 0x23014880, 0x21202205, 0xf01f3012, 0x487afb60, 0x22052300, 0x30122120, 
+    0xfb59f01f, 0x487a2301, 0x0359220d, 0xfb53f01f, 0x48782301, 0x0359220d, 0xe0f8e000, 0xfb4bf01f, 
+    0xf2422300, 0x220d0100, 0xf01f1da8, 0x2300fb44, 0x0100f242, 0x1db0220d, 0xfb3df01f, 0x2300486c, 
+    0x21022201, 0xf01f1f80, 0x4869fb36, 0x21012300, 0x1f80461a, 0xfb2ff01f, 0x23004866, 0x21022201, 
+    0xf01f1f80, 0x4863fb28, 0x21012300, 0x1f80461a, 0xfb21f01f, 0x46282300, 0x21022201, 0xfb1bf01f, 
+    0x46282300, 0x461a2101, 0xfb15f01f, 0x46302300, 0x21022201, 0xfb0ff01f, 0x46302300, 0x461a2101, 
+    0xfb09f01f, 0xf2484852, 0x23000900, 0x220f4649, 0xf01f380a, 0x484ffb00, 0x220f2300, 0x380a4649, 
+    0xfaf9f01f, 0x0a04f1a5, 0x23004649, 0x220f4650, 0xfaf1f01f, 0x0b04f1a6, 0x23004649, 0x220f4658, 
+    0xfae9f01f, 0x23014842, 0x4649220f, 0xf01f380c, 0x4840fae2, 0x220f2301, 0x380c4649, 0xfadbf01f, 
+    0x46492300, 0x1fa8220f, 0xfad5f01f, 0x46492300, 0x1fb0220f, 0xfacff01f, 0xf04f2c01, 0xf04f0301, 
+    0xf2400209, 0xd02c2100, 0xf01f4638, 0x2301fac4, 0x22044638, 0xf01f2110, 0x2301fabe, 0x22034638, 
+    0xf01f2108, 0x4823fab8, 0x22002301, 0x30084619, 0xfab1f01f, 0x220d2301, 0x1da80359, 0xfaabf01f, 
+    0x46282300, 0x21022201, 0xfaa5f01f, 0x46282300, 0x461a2101, 0xfa9ff01f, 0x46492300, 0x4650220f, 
+    0x4644e175, 0xf01f4640, 0x2301fa96, 0x22044620, 0xf01f2110, 0x2301fa90, 0x22034620, 0xf01f2108, 
+    0x480ffa8a, 0x22002301, 0x301a4619, 0xfa83f01f, 0x2301480d, 0x0359220d, 0xf01f1d80, 0x2300fa7c, 
+    0x22014630, 0xf01f2102, 0xe015fa76, 0xd003c010, 0xd003c012, 0xd003d012, 0xd28f2002, 0x000323b4, 
+    0xd003d800, 0xd003d292, 0xd003da8c, 0xd003c800, 0xd003c292, 0xd003ca92, 0x46302300, 0x461a2101, 
+    0xfa59f01f, 0x46492300, 0x4658220f, 0x4640e12f, 0xfa51f01f, 0x46382301, 0x02592209, 0xfa4bf01f, 
+    0xf2402300, 0x22092100, 0xf01f48fe, 0x48fefa44, 0x22092300, 0x2100f240, 0xfa3df01f, 0x230148fb, 
+    0x21102204, 0xfa37f01f, 0x230148f8, 0x21082203, 0xfa31f01f, 0x230148f6, 0x21102204, 0xfa2bf01f, 
+    0x230148f3, 0x21082203, 0xfa25f01f, 0x230048ed, 0x21102204, 0xfa1ff01f, 0x230048ea, 0x21082203, 
+    0xfa19f01f, 0x230048e8, 0x21102204, 0xfa13f01f, 0x230048e5, 0x21082203, 0xfa0df01f, 0x46502301, 
+    0x46192200, 0xfa07f01f, 0x46482301, 0x46192200, 0xfa01f01f, 0x230048db, 0x461a2101, 0xf01f301a, 
+    0x48d9f9fa, 0x21012300, 0x301a461a, 0xf9f3f01f, 0x230148d4, 0x21202205, 0xf01f3012, 0x48d3f9ec, 
+    0x22052300, 0x30122120, 0xf9e5f01f, 0x48d12301, 0x0359220d, 0xf9dff01f, 0x46582301, 0x0359220d, 
+    0xf9d9f01f, 0xa330f8df, 0x220d2300, 0x0100f242, 0xf01f4650, 0xf8dff9d0, 0x2300b324, 0xf242220d, 
+    0x46580100, 0xf9c7f01f, 0x0706f1ab, 0x46382300, 0x21022201, 0xf9bff01f, 0x46382300, 0x461a2101, 
+    0xf9b9f01f, 0x0806f1aa, 0x46402300, 0x21022201, 0xf9b1f01f, 0x46402300, 0x461a2101, 0xf9abf01f, 
+    0x46282300, 0x21022201, 0xf9a5f01f, 0x46282300, 0x461a2101, 0xf99ff01f, 0x46302300, 0x21022201, 
+    0xf999f01f, 0x46302300, 0x461a2101, 0xf993f01f, 0xf2481f3e, 0x23000500, 0x220f4629, 0xf01f4630, 
+    0xf1a8f98a, 0x46290904, 0x46482300, 0xf01f220f, 0x48a3f982, 0x220f2300, 0xf01f4629, 0x489df97c, 
+    0x220f2300, 0x380a4629, 0xf975f01f, 0x23014899, 0x4629220f, 0xf01f380c, 0x4899f96e, 0x220f2301, 
+    0x1e804629, 0xf967f01f, 0x46292300, 0xf1a8220f, 0xf01f0006, 0x2300f960, 0x220f4629, 0xf01f1eb0, 
+    0x2c01f95a, 0x0301f04f, 0x0209f04f, 0x2100f240, 0x4c84d031, 0xf01f4620, 0x2301f94e, 0x22044620, 
+    0xf01f2110, 0x2301f948, 0x22034620, 0xf01f2108, 0x487cf942, 0x22002301, 0x301a4619, 0xf93bf01f, 
+    0x46502301, 0x0359220d, 0xf935f01f, 0x46442300, 0x46402201, 0xf01f2102, 0x2300f92e, 0x21014620, 
+    0xf01f461a, 0x2300f928, 0x220f4629, 0xe8bd4648, 0xf01f5ff0, 0x4c6cb920, 0xf01f4620, 0x2301f91c, 
+    0x22044620, 0xf01f2110, 0x2301f916, 0x22034620, 0xf01f2108, 0x4864f910, 0x22002301, 0x301a4619, 
+    0xf909f01f, 0x46582301, 0x0359220d, 0xf903f01f, 0x46382300, 0x21022201, 0xf8fdf01f, 0x46382300, 
+    0x461a2101, 0xf8f7f01f, 0x46292300, 0x4630220f, 0xe92de7cd, 0x4c5341f0, 0x22054616, 0x3410460f, 
+    0x21204605, 0x46204603, 0xf8e5f01f, 0x4d4f462b, 0x35102205, 0x46282120, 0xf8ddf01f, 0x463b2203, 
+    0x46202108, 0xf8d7f01f, 0x463b2203, 0x46282108, 0xf8d1f01f, 0x46332202, 0x46202104, 0xf8cbf01f, 
+    0x46284633, 0x41f0e8bd, 0x21042202, 0xb8c3f01f, 0x47f0e92d, 0x46914d3c, 0x468a2208, 0x4680350a, 
+    0x46030154, 0x46284621, 0xf8b5f01f, 0x22084e35, 0x46214643, 0x4630360a, 0xf8adf01f, 0x22084f34, 
+    0x46214643, 0x4638370a, 0xf8a5f01f, 0x4c2f4621, 0x46432208, 0x4620340a, 0xf89df01f, 0x46532207, 
+    0x46282180, 0xf897f01f, 0x46532207, 0x46302180, 0xf891f01f, 0x46532207, 0x46382180, 0xf88bf01f, 
+    0x46532207, 0x46202180, 0xf885f01f, 0x464b2206, 0x46282140, 0xf87ff01f, 0x464b2206, 0x46302140, 
+    0xf879f01f, 0x464b2206, 0x46382140, 0xf873f01f, 0x4620464b, 0x47f0e8bd, 0x21402206, 0xb86bf01f, 
+    0x41f0e92d, 0xeb014d10, 0x21600440, 0x35084690, 0x22054623, 0xf01f4628, 0x4e0af85e, 0x21602205, 
+    0x36084623, 0xf01f4630, 0x4f09f856, 0x21602205, 0x37084623, 0xf01f4638, 0x2205f84e, 0x4c034623, 
+    0xe00f2160, 0xd003c800, 0xd003c000, 0xd003d800, 0xd003d000, 0xd003da92, 0xd003ca92, 0xd003c292, 
+    0xd003d288, 0x46203408, 0xf835f01f, 0x46432203, 0x46282108, 0xf82ff01f, 0x46432203, 0x46302108, 
+    0xf829f01f, 0x46432203, 0x46382108, 0xf823f01f, 0x46204643, 0x41f0e8bd, 0x21082203, 0xb81bf01f, 
+    0x47f0e92d, 0x0600f244, 0x220e4692, 0x46074689, 0x46314603, 0x46204cfe, 0xf80df01f, 0x220e4dfd, 
+    0x4631463b, 0xf01f4628, 0xf8dff806, 0x220e83ec, 0x4631463b, 0xf01e4640, 0x4631fffe, 0x220e4ef7, 
+    0x4630463b, 0xfff7f01e, 0x0700f242, 0x220d464b, 0x46204639, 0xffeff01e, 0x464b220d, 0x46284639, 
+    0xffe9f01e, 0x464b220d, 0x46404639, 0xffe3f01e, 0x464b220d, 0x46304639, 0xffddf01e, 0x4653107f, 
+    0x4639220c, 0xf01e4620, 0x220cffd6, 0x46394653, 0xf01e4628, 0x220cffd0, 0x46394653, 0xf01e4640, 
+    0x4653ffca, 0x46304639, 0x47f0e8bd, 0xf01e220c, 0xb570bfc2, 0x23004cd6, 0x1fa42205, 0x46202160, 
+    0xffb9f01e, 0x46202300, 0x21102204, 0xffb3f01e, 0x46202300, 0x21082203, 0xffadf01e, 0x23024ccc, 
+    0x34142205, 0x46202160, 0xffa5f01e, 0x46202301, 0x21102204, 0xff9ff01e, 0x46202301, 0x46192200, 
+    0xff99f01e, 0x23004cc3, 0x1fa42205, 0x46202160, 0xff91f01e, 0x46202300, 0x21102204, 0xff8bf01e, 
+    0x46202300, 0x21082203, 0xff85f01e, 0x23024cb9, 0x34142205, 0x46202160, 0xff7df01e, 0x46202301, 
+    0x21102204, 0xff77f01e, 0x46202301, 0x46192200, 0xff71f01e, 0x23004cb0, 0x1fa42205, 0x46202160, 
+    0xff69f01e, 0x46202300, 0x21102204, 0xff63f01e, 0x46202300, 0x21082203, 0xff5df01e, 0x23034ca6, 
+    0x34142205, 0x46202160, 0xff55f01e, 0x46202300, 0x21102204, 0xff4ff01e, 0x46202301, 0x46192200, 
+    0xff49f01e, 0x23014c9d, 0x1fa42205, 0x46202160, 0xff41f01e, 0x46202301, 0x21102204, 0xff3bf01e, 
+    0x46202301, 0x21082203, 0xff35f01e, 0x23024c93, 0x34142205, 0x46202160, 0xff2df01e, 0x46202300, 
+    0x21102204, 0xff27f01e, 0x46202301, 0x46192200, 0xff21f01e, 0x23004887, 0x21202205, 0xf01e300c, 
+    0x4886ff1a, 0x22052300, 0x300c2120, 0xff13f01e, 0xf2414e80, 0x23000400, 0x360a4621, 0x4630220c, 
+    0xff09f01e, 0x46301065, 0x46292300, 0xf01e220b, 0x4621ff02, 0x23004c79, 0x220c340a, 0xf01e4620, 
+    0x4629fefa, 0xe8bd4620, 0x23004070, 0xf01e220b, 0xb510bef2, 0x23004c6e, 0x1fa42205, 0x46202160, 
+    0xfee9f01e, 0x46202300, 0x21102204, 0xfee3f01e, 0x46202300, 0x21082203, 0xfeddf01e, 0x23024c64, 
+    0x34142205, 0x46202160, 0xfed5f01e, 0x46202301, 0x21102204, 0xfecff01e, 0x46202301, 0x46192200, 
+    0xfec9f01e, 0x23004c5b, 0x1fa42205, 0x46202160, 0xfec1f01e, 0x46202300, 0x21102204, 0xfebbf01e, 
+    0x46202300, 0x21082203, 0xfeb5f01e, 0x23034c51, 0x34142205, 0x46202160, 0xfeadf01e, 0x46202300, 
+    0x21102204, 0xfea7f01e, 0x46202301, 0x46192200, 0xfea1f01e, 0x23004c48, 0x1fa42205, 0x46202160, 
+    0xfe99f01e, 0x46202300, 0x21102204, 0xfe93f01e, 0x46202300, 0x21082203, 0xfe8df01e, 0x23024c3e, 
+    0x34142205, 0x46202160, 0xfe85f01e, 0x46202301, 0x21102204, 0xfe7ff01e, 0x46202301, 0x46192200, 
+    0xfe79f01e, 0x23004c35, 0x1fa42205, 0x46202160, 0xfe71f01e, 0x46202300, 0x21102204, 0xfe6bf01e, 
+    0x46202300, 0x21082203, 0xfe65f01e, 0x23034c2b, 0x34142205, 0x46202160, 0xfe5df01e, 0x46202300, 
+    0x21102204, 0xfe57f01e, 0x46202301, 0x4010e8bd, 0x46192200, 0xbe4ff01e, 0x4c1db570, 0x22052300, 
+    0x21601fa4, 0xf01e4620, 0x2300fe46, 0x22044620, 0xf01e2110, 0x2300fe40, 0x22034620, 0xf01e2108, 
+    0x4c13fe3a, 0x22052302, 0x21603414, 0xf01e4620, 0x2301fe32, 0x22044620, 0xf01e2110, 0x2301fe2c, 
+    0x22004620, 0xf01e4619, 0x4c0afe26, 0x22052301, 0x21601fa4, 0xf01e4620, 0x2301fe1e, 0x22044620, 
+    0xf01e2110, 0x2301fe18, 0x22034620, 0xe0072108, 0xd003c006, 0xd003c806, 0xd003d006, 0xd003d806, 
+    0xfe09f01e, 0x23024cff, 0x21602205, 0xf01e4620, 0x2300fe02, 0x22044620, 0xf01e2110, 0x2301fdfc, 
+    0x22004620, 0xf01e4619, 0x4cf7fdf6, 0x22052300, 0x46202160, 0xfdeff01e, 0x46202300, 0x21102204, 
+    0xfde9f01e, 0x46202300, 0x21082203, 0xfde3f01e, 0x23024ced, 0x341a2205, 0x46202160, 0xfddbf01e, 
+    0x46202301, 0x21102204, 0xfdd5f01e, 0x46202301, 0x46192200, 0xfdcff01e, 0x23014ce4, 0x21602205, 
+    0xf01e4620, 0x2301fdc8, 0x22044620, 0xf01e2110, 0x2301fdc2, 0x22034620, 0xf01e2108, 0x4cdbfdbc, 
+    0x22052302, 0x2160341a, 0xf01e4620, 0x2300fdb4, 0x22044620, 0xf01e2110, 0x2301fdae, 0x22004620, 
+    0xf01e4619, 0x48cffda8, 0x22052300, 0x38082120, 0xfda1f01e, 0x230048cd, 0x21202205, 0xf01e3012, 
+    0x4ec8fd9a, 0x0400f241, 0x46212300, 0x220c3e0a, 0xf01e4630, 0x1065fd90, 0x23004630, 0x220b4629, 
+    0xfd89f01e, 0x4cc14621, 0x34102300, 0x4620220c, 0xfd81f01e, 0x46204629, 0x4070e8bd, 0x220b2300, 
+    0xbd79f01e, 0x230048b7, 0x2205b570, 0x38082120, 0xfd71f01e, 0x230148b5, 0x21202205, 0xf01e3012, 
+    0x4eb0fd6a, 0x0400f241, 0x46212300, 0x220c3e0a, 0xf01e4630, 0x1065fd60, 0x23004630, 0x220b4629, 
+    0xfd59f01e, 0x4ca94621, 0x34102301, 0x4620220c, 0xfd51f01e, 0x46204629, 0x4070e8bd, 0x220b2301, 
+    0xbd49f01e, 0x41f0e92d, 0x230048a1, 0x21602205, 0xfd41f01e, 0x2300489e, 0x21102204, 0xfd3bf01e, 
+    0x2300489b, 0x21082203, 0xfd35f01e, 0x23004898, 0x21602205, 0xf01e301a, 0x4895fd2e, 0x22042300, 
+    0x301a2110, 0xfd27f01e, 0x23004891, 0x461a2101, 0xf01e301a, 0x488efd20, 0x22032300, 0x30122108, 
+    0xfd19f01e, 0x2100488a, 0xf01e301a, 0x4885fcfa, 0x22052300, 0x381a2160, 0xfd0df01e, 0x23004881, 
+    0x21102204, 0xf01e381a, 0x487efd06, 0x22032300, 0x381a2108, 0xfcfff01e, 0x2300487a, 0x21602205, 
+    0xfcf9f01e, 0x23004877, 0x21102204, 0xfcf3f01e, 0x48742300, 0x461a2101, 0xfcedf01e, 0x23004c71, 
+    0x3c082203, 0x46202108, 0xfce5f01e, 0x2100486d, 0xfcc7f01e, 0x2300486c, 0x21602205, 0xfcdbf01e, 
+    0x23004869, 0x21102204, 0xfcd5f01e, 0x23004866, 0x21082203, 0xfccff01e, 0x23004863, 0x21602205, 
+    0xf01e301a, 0x4860fcc8, 0x22042300, 0x301a2110, 0xfcc1f01e, 0x2300485c, 0x461a2101, 0xf01e301a, 
+    0x4859fcba, 0x22032300, 0x30122108, 0xfcb3f01e, 0x21004855, 0xf01e301a, 0x4854fc94, 0x22052300, 
+    0xf01e2160, 0x4851fca8, 0x22042300, 0xf01e2110, 0x484efca2, 0x22032300, 0xf01e2108, 0x484bfc9c, 
+    0x22052300, 0x301a2160, 0xfc95f01e, 0x23004847, 0x21102204, 0xf01e301a, 0x4844fc8e, 0x21012300, 
+    0x301a461a, 0xfc87f01e, 0x8100f8df, 0x22032300, 0x0812f108, 0x46402108, 0xfc7df01e, 0x2100483b, 
+    0xf01e301a, 0x2300fc5e, 0x22054620, 0xf01e2120, 0x2300fc72, 0x22054640, 0xf01e2120, 0x1ea6fc6c, 
+    0x0500f241, 0x46292300, 0x4630220c, 0xfc63f01e, 0x4630106f, 0x46392300, 0xf01e220b, 0x4629fc5c, 
+    0x0502f1a8, 0x46282300, 0xf01e220c, 0x2300fc54, 0x220b4639, 0xf01e4628, 0x10bdfc4e, 0x23004824, 
+    0x22094629, 0xfc47f01e, 0x2300481e, 0x46292209, 0xf01e381a, 0x481cfc40, 0x22092300, 0xf01e4629, 
+    0x481afc3a, 0x22092300, 0xf01e4629, 0x4818fc34, 0x22042300, 0xf01e2110, 0x4815fc2e, 0x22032300, 
+    0xf01e2108, 0x480ffc28, 0x22042300, 0x381a2110, 0xfc21f01e, 0x2300480b, 0x21082203, 0xf01e381a, 
+    0x4809fc1a, 0x22042300, 0xf01e2110, 0x4806fc14, 0x22032300, 0xf01e2108, 0x2300fc0e, 0x22044803, 
+    0xe0072110, 0xd003c81a, 0xd003d000, 0xd003d800, 0xd003c000, 0xfbfff01e, 0x230048f6, 0x21082203, 
+    0xfbf9f01e, 0x48f42300, 0x461a2101, 0xfbf3f01e, 0x48f22300, 0x461a2101, 0xfbedf01e, 0x48f02300, 
+    0x461a2101, 0xfbe7f01e, 0x230048ea, 0x461a2101, 0xf01e301a, 0x2300fbe0, 0x22054620, 0xf01e2120, 
+    0x2300fbda, 0x22054640, 0xf01e2120, 0x4ce5fbd4, 0x22012300, 0x46202102, 0xfbcdf01e, 0x46202300, 
+    0x461a2101, 0xfbc7f01e, 0x23004cdf, 0x21022201, 0xf01e4620, 0x2300fbc0, 0x21014620, 0xf01e461a, 
+    0x4cdafbba, 0x22012300, 0x46202102, 0xfbb3f01e, 0x46202300, 0x461a2101, 0xfbadf01e, 0x23004cd4, 
+    0x21022201, 0xf01e4620, 0x2300fba6, 0x21014620, 0xf01e461a, 0x48cbfba0, 0x230001ac, 0x220f4621, 
+    0xf01e1f00, 0x48c8fb98, 0x220f2300, 0x1f004621, 0xfb91f01e, 0x230048c5, 0x4621220f, 0xf01e1f00, 
+    0x48c3fb8a, 0x220f2300, 0x1f004621, 0xfb83f01e, 0x230048bc, 0x4621220f, 0xf01e1f80, 0x48bafb7c, 
+    0x220f2300, 0x1f804621, 0xfb75f01e, 0x230048b7, 0x4621220f, 0xf01e1f80, 0x48b5fb6e, 0x220f2300, 
+    0x1f804621, 0xfb67f01e, 0x230048ab, 0x21102204, 0xf01e381a, 0x48a8fb60, 0x22032300, 0x381a2108, 
+    0xfb59f01e, 0x230048a5, 0x21102204, 0xf01e381a, 0x48a2fb52, 0x22032300, 0x381a2108, 0xfb4bf01e, 
+    0x2300489f, 0x21102204, 0xf01e381a, 0x489cfb44, 0x22032300, 0x381a2108, 0xfb3df01e, 0x23004895, 
+    0x21102204, 0xfb37f01e, 0x23004892, 0x21082203, 0xfb31f01e, 0x23004890, 0x46292209, 0xf01e381a, 
+    0x488efb2a, 0x22092300, 0x381a4629, 0xfb23f01e, 0x2300488b, 0x46292209, 0xf01e381a, 0x4885fb1c, 
+    0x22092300, 0xf01e4629, 0x2300fb16, 0x21014882, 0xf01e461a, 0x2300fb10, 0x21014880, 0xf01e461a, 
+    0x2300fb0a, 0x2101487e, 0xf01e461a, 0x4879fb04, 0x21012300, 0x301a461a, 0xfafdf01e, 0x23004d76, 
+    0x1d2d2204, 0x46282110, 0xfaf5f01e, 0x23004e73, 0x1d362204, 0x46302110, 0xfaedf01e, 0x23004f70, 
+    0x1d3f2204, 0x46382110, 0xfae5f01e, 0x81a4f8df, 0x22042300, 0x081ef108, 0x46402110, 0xfadbf01e, 
+    0x46212300, 0x1ea8220f, 0xfad5f01e, 0x46212300, 0x1eb0220f, 0xfacff01e, 0x46212300, 0x1eb8220f, 
+    0xfac9f01e, 0x46212300, 0xf1a8220f, 0xf01e0002, 0x2300fac2, 0x210f4628, 0xf01e461a, 0x2300fabc, 
+    0x210f4630, 0xf01e461a, 0x2300fab6, 0x210f4638, 0xf01e461a, 0x4640fab0, 0x41f0e8bd, 0x210f2300, 
+    0xf01e461a, 0xb570baa8, 0x28054e52, 0x4605460c, 0x2d04d001, 0x6830d106, 0xd0022801, 0x7800484e, 
+    0x2400b100, 0x7005484d, 0x7004484d, 0xfd4af7ff, 0xd02c2d03, 0xd02a2d05, 0xd0282d04, 0xd0772d02, 
+    0xd0fc2d00, 0xd1742d01, 0x22012100, 0xf7ff4608, 0x2200fa67, 0x46102101, 0xfa12f7ff, 0x46112200, 
+    0xf7ff4610, 0x2200f9b5, 0x46104611, 0xf981f7ff, 0x28016830, 0x483bd003, 0x28007800, 0x483ad059, 
+    0xf9902108, 0xe8bd0000, 0xf7fe4070, 0xb35cbe75, 0xd03c2c01, 0xd06c2c02, 0xd07a2c03, 0xd0672c04, 
+    0xd0732c05, 0xd0722c06, 0xd0712c07, 0xd1402c08, 0x46112200, 0xf7ff4610, 0x2200fa33, 0x46104611, 
+    0xf9def7ff, 0x46112200, 0xf7ff4610, 0x2200f981, 0x46102101, 0xf94df7ff, 0xd07d2d04, 0xd07b2d05, 
+    0x4070e8bd, 0xba75f7ff, 0x46112200, 0xf7ff4610, 0x2200fa17, 0x46112001, 0xf9c2f7ff, 0x46112201, 
+    0xf7ff4610, 0x2201f965, 0x46102100, 0x2100e0ac, 0x46082201, 0xfa04f7ff, 0x21012200, 0xf7ff4610, 
+    0x2200f9af, 0x46102101, 0xf952f7ff, 0xe0992201, 0xe09de088, 0xd003d800, 0xd003c01a, 0xd003c81a, 
+    0xd003d01a, 0xd003c28c, 0xd003ca8c, 0xd003d28c, 0xd003da8c, 0x00032374, 0x0003238f, 0x00032346, 
+    0x00032347, 0x00032390, 0x00032228, 0xe010e001, 0x2200e01d, 0x46102101, 0xf9d2f7ff, 0x46112200, 
+    0xf7ff4610, 0x2200f97d, 0xe02c2101, 0xe030e028, 0x2100e03c, 0x46082201, 0xf9c2f7ff, 0x21012200, 
+    0xf7ff4610, 0x2200f96d, 0x46082101, 0x2100e00c, 0x46082201, 0xf9b4f7ff, 0x21012200, 0xf7ff4610, 
+    0x2200f95f, 0x46104611, 0xf902f7ff, 0x22012100, 0xf7ff4608, 0xe000f8ce, 0xe8bde030, 0xe4414070, 
+    0x21012200, 0x2000e007, 0xf8f2f7ff, 0x21012200, 0x2200e039, 0x20004611, 0xf992f7ff, 0x46112200, 
+    0xf7ff4610, 0x2200f93d, 0xe7ec4611, 0x46112200, 0xf7ff4610, 0x2200f985, 0x46104611, 0xf930f7ff, 
+    0x46112200, 0xf7ff4610, 0x2200f8d3, 0x46102101, 0xf89ff7ff, 0x4070e8bd, 0xbb3ef7ff, 0x4070e8bd, 
+    0xba97f7ff, 0x22012100, 0xf7ff4608, 0x2200f969, 0x46102101, 0xf914f7ff, 0x46112200, 0xf7ff4610, 
+    0x2200f8b7, 0x20002100, 0x4070e8bd, 0xb881f7ff, 0x220bbd70, 0x0100f641, 0x48feb510, 0xf979f01e, 
+    0xbd10b2c0, 0x220f48fb, 0x0100f248, 0xf01eb510, 0x4604f970, 0x220048f7, 0x1c802101, 0xf969f01e, 
+    0x0040eb04, 0xbd10b2c0, 0x220948f2, 0x6100f240, 0xf01eb510, 0xb2c0f95e, 0x48eebd10, 0xf246220d, 
+    0xb5100100, 0xf955f01e, 0xbd10b2c0, 0x220b48ea, 0x0100f641, 0xf01eb510, 0xb2c0f94c, 0x48e6bd10, 
+    0xf248220f, 0xb5100100, 0xf943f01e, 0x48e24604, 0x21012200, 0xf01e1c80, 0xeb04f93c, 0xb2c00040, 
+    0x48ddbd10, 0xf2402209, 0xb5106100, 0xf931f01e, 0xbd10b2c0, 0x220d48d8, 0x0100f246, 0xf01eb510, 
+    0xb2c0f928, 0xe92dbd10, 0x280147f0, 0x4614461e, 0xd17d460d, 0xa340f8df, 0x2900f240, 0x46492300, 
+    0x0a02f10a, 0x46502209, 0xf905f01e, 0x4800f240, 0x23004650, 0x220a4647, 0xf01e4641, 0x4649f8fc, 
+    0x9310f8df, 0xf1092300, 0x22090902, 0xf01e4648, 0x2300f8f2, 0x220a4639, 0xf01e4648, 0x2300f8ec, 
+    0x22074650, 0xf01e2180, 0x2208f8e6, 0x23004650, 0x46390157, 0xf8dff01e, 0x46482300, 0x21802207, 
+    0xf8d9f01e, 0x46392300, 0x46482208, 0xf8d3f01e, 0x0704ea45, 0x2e04b10e, 0x2d01d16a, 0x2c01d102, 
+    0xb3b4d020, 0xffa6f7ff, 0x2001b148, 0xfc53f7fe, 0x20042100, 0xfce8f7fa, 0xf7fe2000, 0xf7fffc4c, 
+    0x2803ff90, 0x2001d009, 0xfc3ef7fe, 0x20042100, 0xfcdaf7fa, 0xf7fe2003, 0x2d01fc37, 0x2c01d039, 
+    0xe039d037, 0xff7df7ff, 0x2001b148, 0xfc2cf7fe, 0x20042100, 0xfcc8f7fa, 0xf7fe2000, 0xf7fffc25, 
+    0xb330ff79, 0xf7fe2001, 0x2100fc26, 0xe0012004, 0xe003e186, 0xfcb8f7fa, 0xe0182000, 0xff61f7ff, 
+    0x2001b148, 0xfc10f7fe, 0x20042100, 0xfcacf7fa, 0xf7fe2000, 0xf7fffc09, 0x2803ff5d, 0x2001d009, 
+    0xfc09f7fe, 0x20042100, 0xfc9ef7fa, 0xf7fe2003, 0x2000fc02, 0xfb7cf7fe, 0x2000b917, 0xfc02f7fe, 
+    0x46402100, 0xfc90f7fa, 0x20802100, 0xfc8cf7fa, 0xd0012e01, 0xd1682e04, 0xd1022d01, 0xd0202c01, 
+    0xf7ffb3c4, 0xb148ff1c, 0xf7fe2001, 0x2100fb4d, 0xf7fa2004, 0x2000fc79, 0xfb46f7fe, 0xff06f7ff, 
+    0xd0092803, 0xf7fe2001, 0x2100fb38, 0xf7fa2004, 0x2003fc6b, 0xfb31f7fe, 0xd0372d01, 0xd0352c01, 
+    0xf7ffe037, 0xb148fef3, 0xf7fe2001, 0x2100fb26, 0xf7fa2004, 0x2000fc59, 0xfb1ff7fe, 0xfeeff7ff, 
+    0x2001b320, 0xfb20f7fe, 0x20042100, 0xfc4cf7fa, 0xe0192000, 0xf7ffe7ff, 0xb148fed9, 0xf7fe2001, 
+    0x2100fb0c, 0xf7fa2004, 0x2000fc3f, 0xfb05f7fe, 0xfed5f7ff, 0xd0092803, 0xf7fe2001, 0x2100fb05, 
+    0xf7fa2004, 0x2003fc31, 0xfafef7fe, 0xf7fe2000, 0xb917fa83, 0xf7fe2001, 0x2100fb95, 0xf7fa4640, 
+    0x2100fc23, 0xf7fa2080, 0x2e02fc1f, 0x2e04d001, 0x2d01d168, 0x2c01d102, 0xb3c4d020, 0xfe9df7ff, 
+    0x2001b148, 0xfa61f7fe, 0x20042100, 0xfc0cf7fa, 0xf7fe2000, 0xf7fffa5a, 0x2803fe87, 0x2001d009, 
+    0xfa4cf7fe, 0x20042100, 0xfbfef7fa, 0xf7fe2003, 0x2d01fa45, 0x2c01d037, 0xe037d035, 0xfe74f7ff, 
+    0x2001b148, 0xfa3af7fe, 0x20042100, 0xfbecf7fa, 0xf7fe2000, 0xf7fffa33, 0xb320fe70, 0xf7fe2001, 
+    0x2100fa34, 0xf7fa2004, 0x2000fbdf, 0xe7ffe019, 0xfe5af7ff, 0x2001b148, 0xfa20f7fe, 0x20042100, 
+    0xfbd2f7fa, 0xf7fe2000, 0xf7fffa19, 0x2803fe56, 0x2001d009, 0xfa19f7fe, 0x20042100, 0xfbc4f7fa, 
+    0xf7fe2003, 0x2000fa12, 0xf996f7fe, 0x2002b917, 0xfb28f7fe, 0x46402100, 0xfbb6f7fa, 0x20802100, 
+    0xfbb2f7fa, 0xd0012e03, 0xd16e2e04, 0xd1022d01, 0xd0262c01, 0xf7ffb3f4, 0xb148fe15, 0xf7fe2001, 
+    0x2100f967, 0xf7fa2004, 0x2000fb9f, 0xf960f7fe, 0x0000e004, 0xd003d010, 0xd003c010, 0xfdf9f7ff, 
+    0xd0092803, 0xf7fe2001, 0x2100f94c, 0xf7fa2004, 0x2003fb8b, 0xf945f7fe, 0xd0372d01, 0xd0352c01, 
+    0xf7ffe037, 0xb148fde6, 0xf7fe2001, 0x2100f93a, 0xf7fa2004, 0x2000fb79, 0xf933f7fe, 0xfde2f7ff, 
+    0x2001b320, 0xf934f7fe, 0x20042100, 0xfb6cf7fa, 0xe0192000, 0xf7ffe7ff, 0xb148fdcc, 0xf7fe2001, 
+    0x2100f920, 0xf7fa2004, 0x2000fb5f, 0xf919f7fe, 0xfdc8f7ff, 0xd0092803, 0xf7fe2001, 0x2100f919, 
+    0xf7fa2004, 0x2003fb51, 0xf912f7fe, 0xf7fe2000, 0xb917f897, 0xf7fe2003, 0x2100fab5, 0xf7fa4640, 
+    0x2100fb43, 0xf7fa2080, 0x2d01fb3f, 0x2c01d001, 0x48fed106, 0x48fe7801, 0xe8bd7800, 0xe46247f0, 
+    0x87f0e8bd, 0x4cfbb570, 0x2801b398, 0x2802d035, 0x2803d037, 0x2301d01f, 0x22004620, 0xf01d4619, 
+    0xf44ffefa, 0x21003580, 0xf7fa4628, 0x2301fb1d, 0x21024620, 0xf01d461a, 0x2100feee, 0xf7fa4628, 
+    0x2301fb13, 0x22024620, 0xf01d2104, 0x2100fee4, 0xf7fa4628, 0x2301fb09, 0x21082203, 0xf01d4620, 
+    0x2300feda, 0xe8bd48e4, 0x21014070, 0xf01d461a, 0x2301bed2, 0x46192200, 0x2301e7f0, 0x461a2102, 
+    0x2301e7ec, 0x21042202, 0xb570e7e8, 0xb3904cd9, 0xd0342801, 0xd0362802, 0xf04f2803, 0xd0360300, 
+    0x46202200, 0xf01d2101, 0xf44ffeb6, 0x21003580, 0xf7fa4628, 0x2300fad9, 0x22014620, 0xf01d2102, 
+    0x2100feaa, 0xf7fa4628, 0x2300facf, 0x22024620, 0xf01d2104, 0x2100fea0, 0xf7fa4628, 0x2300fac5, 
+    0x22034620, 0xf01d2108, 0x4628fe96, 0x4070e8bd, 0xf7fa2100, 0x2300bab9, 0x461a2101, 0x2300e009, 
+    0x21022201, 0x2300e005, 0x21042202, 0x2203e001, 0x46202108, 0x4070e8bd, 0xbe7df01d, 0x2204b510, 
+    0x21104604, 0x48b54603, 0xfe75f01d, 0x220448b4, 0x46232110, 0xfe6ff01d, 0x220448b2, 0x46232110, 
+    0xfe69f01d, 0x46232204, 0x4010e8bd, 0x211048ae, 0xbe61f01d, 0x4604b510, 0x1d0048a8, 0xfe3ef01d, 
+    0x300ff364, 0x4010e8bd, 0x48a84601, 0xbe39f01d, 0x41f0e92d, 0xf0004ea6, 0xf3c00401, 0x46230541, 
+    0x46302203, 0xf01d2108, 0x4fa2fe46, 0x21082203, 0x46384623, 0xfe3ff01d, 0x827cf8df, 0x21082203, 
+    0x46404623, 0xfe37f01d, 0x4c9c4623, 0x21082203, 0xf01d4620, 0x2204fe30, 0x2130462b, 0xf01d4630, 
+    0x2204fe2a, 0x2130462b, 0xf01d4638, 0x2204fe24, 0x2130462b, 0xf01d4640, 0x462bfe1e, 0xe8bd4620, 
+    0x220441f0, 0xf01d2130, 0xe92dbe16, 0x4d8341f0, 0x7400f240, 0x460e2208, 0x46073508, 0x46214603, 
+    0xf01d4628, 0x2204fe08, 0x21704633, 0xf01d4628, 0x2300fe02, 0x21014628, 0xf01d461a, 0x2301fdfc, 
+    0x22004628, 0xf01d4619, 0x2300fdf6, 0x21014628, 0xf01d461a, 0x4d72fdf0, 0x463b2208, 0x35084621, 
+    0xf01d4628, 0x2204fde8, 0x21704633, 0xf01d4628, 0x2300fde2, 0x21014628, 0xf01d461a, 0x2301fddc, 
+    0x22004628, 0xf01d4619, 0x2300fdd6, 0x21014628, 0xf01d461a, 0x4d63fdd0, 0x463b2208, 0x35084621, 
+    0xf01d4628, 0x2204fdc8, 0x21704633, 0xf01d4628, 0x2300fdc2, 0x21014628, 0xf01d461a, 0x2301fdbc, 
+    0x22004628, 0xf01d4619, 0x2300fdb6, 0x21014628, 0xf01d461a, 0x4621fdb0, 0x22084c53, 0x3408463b, 
+    0xf01d4620, 0x2204fda8, 0x21704633, 0xf01d4620, 0x2300fda2, 0x21014620, 0xf01d461a, 0x2301fd9c, 
+    0x22004620, 0xf01d4619, 0x2300fd96, 0x21014620, 0xf01d461a, 0x4841fd90, 0x14e0f240, 0x4621230d, 
+    0x1e802205, 0xfd87f01d, 0x230d483d, 0x46212205, 0xf01d1e80, 0x483bfd80, 0x2205230d, 0x1e804621, 
+    0xfd79f01d, 0x48384621, 0x41f0e8bd, 0x2205230d, 0xf01d1e80, 0xe92dbd70, 0x460441f0, 0x38084834, 
+    0x4d34b379, 0x29013d08, 0x4e33d031, 0x29023e08, 0x4f32d028, 0x29033f08, 0x2201d01e, 0x21024623, 
+    0xfd59f01d, 0x0800f241, 0x46402100, 0xf97cf7fa, 0x46232201, 0x46282102, 0xfd4df01d, 0x46402100, 
+    0xf972f7fa, 0x46232201, 0x46302102, 0xfd43f01d, 0x46402100, 0xf968f7fa, 0x46232201, 0x46382102, 
+    0xe009e00d, 0x46232201, 0x46302102, 0x2201e007, 0x21024623, 0xe0024628, 0x46232201, 0xe8bd2102, 
+    0xf01d41f0, 0x4770bd28, 0x4e11b570, 0x22050045, 0x36104604, 0x2160462b, 0xf01d4630, 0x2204fd1c, 
+    0x21104623, 0xf01d4630, 0xe019fd16, 0x00032347, 0x00032346, 0xd0034222, 0xd00305cc, 0xd003c286, 
+    0xd003ca86, 0xd003d286, 0xd003da86, 0xd003e28a, 0xd003c00a, 0xd003c80a, 0xd003d00a, 0xd003d80a, 
+    0x46232200, 0x46302101, 0xfcf5f01d, 0x23004efe, 0x21602205, 0xf01d4630, 0x2300fcee, 0x22044630, 
+    0xf01d2110, 0x2300fce8, 0x21014630, 0xf01d461a, 0x462bfce2, 0x22054df5, 0x46282160, 0xfcdbf01d, 
+    0x46232204, 0x46282110, 0xfcd5f01d, 0x46232200, 0x46282101, 0xfccff01d, 0x23004ced, 0x21602205, 
+    0xf01d4620, 0x2300fcc8, 0x22044620, 0xf01d2110, 0x2300fcc2, 0xe8bd4620, 0x21014070, 0xf01d461a, 
+    0xb510bcba, 0x46042200, 0x46032103, 0xf01d48e1, 0x48e1fcb2, 0x21032200, 0xf01d4623, 0x48dffcac, 
+    0x21032200, 0xf01d4623, 0x2200fca6, 0xe8bd4623, 0x48db4010, 0xf01d2103, 0xe92dbc9e, 0x4dd947f0, 
+    0x4fd54ed4, 0x8354f8df, 0xf8df362a, 0x372a9354, 0xf1087828, 0xf109082a, 0xb148092a, 0xb1587868, 
+    0xf04f78a8, 0xf04f0205, 0xb1680160, 0xe0064648, 0x46302205, 0xe0022160, 0x46382205, 0xf01d2160, 
+    0xb118fc88, 0xe0022401, 0xe7f84640, 0x78282400, 0xd0132801, 0x28017868, 0x78a8d014, 0x0205f04f, 
+    0x0160f04f, 0xd0112801, 0xf01d4648, 0xb100fc72, 0x44202001, 0xdb0b2802, 0xe5512001, 0x46302205, 
+    0xe7f22160, 0x46382205, 0xe7ee2160, 0xe7ec4640, 0xe5452000, 0x4605b570, 0x48ae4603, 0x0400f24c, 
+    0x4621220e, 0xf01d3008, 0x48abfc46, 0x462b220e, 0x30084621, 0xfc3ff01d, 0x220e48a8, 0x4621462b, 
+    0xf01d3008, 0x48a6fc38, 0x462b220e, 0x30084621, 0xfc31f01d, 0x23004c9f, 0x461a2103, 0x4620341c, 
+    0xfc29f01d, 0x46202301, 0x21032200, 0xfc23f01d, 0x23004c99, 0x461a2103, 0x4620341c, 0xfc1bf01d, 
+    0x46202301, 0x21032200, 0xfc15f01d, 0x23004c93, 0x461a2103, 0x4620341c, 0xfc0df01d, 0x46202301, 
+    0x21032200, 0xfc07f01d, 0x23004c8d, 0x461a2103, 0x4620341c, 0xfbfff01d, 0xe8bd4620, 0x23014070, 
+    0x21032200, 0xbbf7f01d, 0x4d87b570, 0x46042801, 0x0600f244, 0x2300d10c, 0x4100f643, 0x4628220a, 
+    0xfbe9f01d, 0x46312301, 0x4628220e, 0xfbe3f01d, 0x22004878, 0x46232101, 0xf01d1f80, 0x4876fbdc, 
+    0x21012200, 0x1f804623, 0xfbd5f01d, 0x22004873, 0x46232101, 0xf01d1f80, 0x4871fbce, 0x21012200, 
+    0x1f804623, 0xfbc7f01d, 0xd1072c00, 0x46284631, 0x4070e8bd, 0x220e2300, 0xbbbdf01d, 0xb510bd70, 
+    0x46034604, 0x22014863, 0x1f802102, 0xfbb3f01d, 0x22014861, 0x46232102, 0xf01d1f80, 0x485ffbac, 
+    0x21022201, 0x1f804623, 0xfba5f01d, 0x2201485c, 0x46232102, 0x4010e8bd, 0xf01d1f80, 0xb510bb9c, 
+    0x46034604, 0x22024853, 0x1f802104, 0xfb93f01d, 0x22024851, 0x46232104, 0xf01d1f80, 0x484ffb8c, 
+    0x21042202, 0x1f804623, 0xfb85f01d, 0x2202484c, 0x46232104, 0x4010e8bd, 0xf01d1f80, 0xb570bb7c, 
+    0x46034605, 0xf2474843, 0x220c0400, 0x388a4621, 0xfb71f01d, 0x220c4840, 0x4621462b, 0xf01d388a, 
+    0x483efb6a, 0x462b220c, 0x388a4621, 0xfb63f01d, 0x462b483b, 0xe8bd4621, 0x220c4070, 0xf01d388a, 
+    0xb570bb5a, 0x46052207, 0x48324603, 0x381601d4, 0xf01d4621, 0x4830fb50, 0x462b2207, 0x38164621, 
+    0xfb49f01d, 0x2207482d, 0x4621462b, 0xf01d3816, 0x482bfb42, 0x4621462b, 0x4070e8bd, 0x38162207, 
+    0xbb39f01d, 0x4605b570, 0x48224603, 0x4400f641, 0x4621220a, 0xf01d3816, 0x481ffb2e, 0x462b220a, 
+    0x38164621, 0xfb27f01d, 0x220a481c, 0x4621462b, 0xf01d3816, 0x481afb20, 0x4621462b, 0x4070e8bd, 
+    0x3816220a, 0xbb17f01d, 0x4604b510, 0x48114603, 0x21072200, 0xf01d3814, 0x480ffb0e, 0x21072200, 
+    0x38144623, 0xfb07f01d, 0x2200480c, 0x46232107, 0xf01d3814, 0x480afb00, 0x21072200, 0xe8bd4623, 
+    0x38144010, 0xbaf7f01d, 0xd003c81a, 0xd003d01a, 0xd003d81a, 0xd003c296, 0xd003ca96, 0xd003d296, 
+    0xd003da96, 0x000323b4, 0xd28f21f6, 0x2204b510, 0x21704604, 0x48fe4603, 0xfaddf01d, 0x220448fd, 
+    0x46232170, 0xfad7f01d, 0x220448fb, 0x46232170, 0xfad1f01d, 0x46232204, 0x4010e8bd, 0x217048f7, 
+    0xbac9f01d, 0x2208b570, 0x46034605, 0x015448f0, 0x4621387a, 0xfabff01d, 0x220848ee, 0x4621462b, 
+    0xf01d387a, 0x48ecfab8, 0x462b2208, 0x387a4621, 0xfab1f01d, 0x462b48e9, 0xe8bd4621, 0x22084070, 
+    0xf01d387a, 0xb570baa8, 0x46034605, 0xf24848e0, 0x220f0400, 0x302e4621, 0xfa9df01d, 0x220f48dd, 
+    0x4621462b, 0xf01d302e, 0x48dbfa96, 0x462b220f, 0x302e4621, 0xfa8ff01d, 0x462b48d8, 0xe8bd4621, 
+    0x220f4070, 0xf01d302e, 0xb570ba86, 0x46034605, 0xf24448cf, 0x220e0400, 0x302e4621, 0xfa7bf01d, 
+    0x220e48cc, 0x4621462b, 0xf01d302e, 0x48cafa74, 0x462b220e, 0x302e4621, 0xfa6df01d, 0x462b48c7, 
+    0xe8bd4621, 0x220e4070, 0xf01d302e, 0xb510ba64, 0x46034604, 0x220448be, 0x30122110, 0xfa5bf01d, 
+    0x220448bc, 0x46232110, 0xf01d3012, 0x48bafa54, 0x21102204, 0x30124623, 0xfa4df01d, 0x220448b7, 
+    0x46232110, 0x4010e8bd, 0xf01d3012, 0xb570ba44, 0x46034605, 0xf64048ae, 0x22096400, 0x30124621, 
+    0xfa39f01d, 0x220948ab, 0x4621462b, 0xf01d3012, 0x48a9fa32, 0x462b2209, 0x30124621, 0xfa2bf01d, 
+    0x462b48a6, 0xe8bd4621, 0x22094070, 0xf01d3012, 0xb510ba22, 0x46034604, 0x2205489d, 0x30122120, 
+    0xfa19f01d, 0x2205489b, 0x46232120, 0xf01d3012, 0x4899fa12, 0x21202205, 0x30124623, 0xfa0bf01d, 
+    0x22054896, 0x46232120, 0x4010e8bd, 0xf01d3012, 0xb570ba02, 0x22004c92, 0x46052101, 0x46204603, 
+    0xf9f9f01d, 0x462b2201, 0x46202102, 0xf9f3f01d, 0x462b2202, 0x46202104, 0xf9edf01d, 0x4620462b, 
+    0x4070e8bd, 0x21082203, 0xb9e5f01d, 0x4605b570, 0x487f4603, 0x14e0f240, 0x46212205, 0xf01d3872, 
+    0x487cf9da, 0x462b2205, 0x38724621, 0xf9d3f01d, 0x22054879, 0x4621462b, 0xf01d3872, 0x4877f9cc, 
+    0x4621462b, 0x4070e8bd, 0x38722205, 0xb9c3f01d, 0xeb014974, 0xf01d20c0, 0x4a72b9a1, 0xeb02b289, 
+    0xf01d20c0, 0xb570b99e, 0xf7ff2000, 0x2400ffcf, 0x1500f240, 0x46204629, 0xffeff7ff, 0xb2e41c64, 
+    0xd3f72c04, 0xe92dbd70, 0x250147f0, 0x43a54604, 0x22004865, 0x2101462b, 0xf99df01d, 0xf2484e62, 
+    0x220f0a00, 0x1eb6462b, 0x46304651, 0xf993f01d, 0x0700f244, 0x220e462b, 0x46304639, 0xf98bf01d, 
+    0x0800f242, 0x220d462b, 0x46304641, 0xf983f01d, 0x0900f241, 0x220c462b, 0x46304649, 0xf97bf01d, 
+    0x22004852, 0x462b2101, 0xf975f01d, 0x220f4e4f, 0x4651462b, 0x46301eb6, 0xf96df01d, 0x462b220e, 
+    0x46304639, 0xf967f01d, 0x462b220d, 0x46304641, 0xf961f01d, 0x462b220c, 0x46304649, 0xf95bf01d, 
+    0x22004843, 0x462b2101, 0xf955f01d, 0x220f4e40, 0x4651462b, 0x46301eb6, 0xf94df01d, 0x462b220e, 
+    0x46304639, 0xf947f01d, 0x462b220d, 0x46304641, 0xf941f01d, 0x462b220c, 0x46304649, 0xf93bf01d, 
+    0x22004834, 0x462b2101, 0xf935f01d, 0x220f4e31, 0x4651462b, 0x46301eb6, 0xf92df01d, 0x462b220e, 
+    0x46304639, 0xf927f01d, 0x462b220d, 0x46304641, 0xf921f01d, 0x462b220c, 0x46304649, 0xf91bf01d, 
+    0xb2a34821, 0x4651220f, 0xf01d1d00, 0x481ff914, 0x220fb2a3, 0x1d004651, 0xf90df01d, 0xb2a3481c, 
+    0x4651220f, 0xf01d1d00, 0x220ff906, 0xb2a34651, 0xe8bd1db0, 0xf01d47f0, 0xe92db8fe, 0x4c1241f0, 
+    0x22044615, 0x1da4460e, 0x21104607, 0x46204603, 0xf8f1f01d, 0x46332203, 0x46202108, 0xf8ebf01d, 
+    0x462b2202, 0x46202104, 0xf8e5f01d, 0xe013463b, 0xd003c282, 0xd003ca82, 0xd003d282, 0xd003da82, 
+    0xd0034224, 0xd003c3e8, 0xd003c00a, 0xd003c80a, 0xd003d00a, 0xd003d80a, 0x22044c59, 0x46202110, 
+    0xf8c9f01d, 0x46332203, 0x46202108, 0xf8c3f01d, 0x4620462b, 0x41f0e8bd, 0x21042202, 0xb8bbf01d, 
+    0x4c50b570, 0x460e2201, 0x21024605, 0x46204603, 0xf8b1f01d, 0x4d4c462b, 0x21022201, 0xf01d4628, 
+    0x2200f8aa, 0x21014633, 0xf01d4620, 0x4633f8a4, 0xe8bd4628, 0x22004070, 0xf01d2101, 0xb570b89c, 
+    0x0400f242, 0x220d4605, 0x48404603, 0xf01d4621, 0x483ff892, 0x462b220d, 0xf01d4621, 0x483df88c, 
+    0x462b220d, 0xf01d4621, 0x462bf886, 0xe8bd4621, 0x48394070, 0xf01d220d, 0xe92db87e, 0x4c3241f0, 
+    0x4e304d2f, 0x4f35340a, 0x360a350a, 0xd1132801, 0x0341220d, 0xf01d4832, 0x0001f87c, 0xd0014831, 
+    0xe0007840, 0xf2447800, 0xb3780100, 0xd02e2801, 0xd0202802, 0xd0132803, 0x46382300, 0x21082203, 
+    0xf859f01d, 0x46302300, 0x21082203, 0xf853f01d, 0x46282300, 0x21082203, 0xf84df01d, 0xe0062300, 
+    0x23014819, 0x3810220e, 0xf845f01d, 0x46202301, 0x21082203, 0x4812e020, 0x220e2301, 0xf01d3810, 
+    0x2301f83a, 0x22034628, 0xe0152108, 0x480de00a, 0x220e2301, 0xf01d3810, 0x2301f82e, 0x22034630, 
+    0xe0092108, 0x2301480d, 0x381a220e, 0xf823f01d, 0x46382301, 0x21082203, 0x41f0e8bd, 0xb81bf01d, 
+    0xd003d010, 0xd003c810, 0xd003d810, 0xd003c292, 0xd003ca92, 0xd003d292, 0xd003da92, 0xd003c01a, 
+    0xd28f2002, 0x000323b4, 0x22032301, 0xb5102108, 0xf01c48fe, 0x2000ffe9, 0xfc06f7ff, 0xf7ff2000, 
+    0x2001fc3e, 0xfc5bf7ff, 0x4010e8bd, 0xf7ff2005, 0x48f6bc76, 0x22032301, 0xb5102108, 0xffd4f01c, 
+    0xf7ff2000, 0x2000fbf1, 0xfc49f7ff, 0xf7ff2001, 0x2003fc26, 0xfcc8f7ff, 0xf7ff2003, 0x2005fcf7, 
+    0xfc5df7ff, 0xf7ff2003, 0x2003fc7c, 0xfc9af7ff, 0x4010e8bd, 0xf7ff2000, 0xe92dbd05, 0x460547f0, 
+    0xf7ff2000, 0x2301fdc6, 0x220c48e1, 0x4621031c, 0xffc1f01c, 0x230148df, 0x4621220c, 0xffbbf01c, 
+    0x230148dd, 0x4621220c, 0xffb5f01c, 0x230148db, 0x4621220c, 0xffaff01c, 0xf7ff2000, 0x2000fc95, 
+    0xfcc4f7ff, 0x230048d1, 0x21082203, 0xff8cf01c, 0xf7ff2000, 0x2001fcf8, 0xfd17f7ff, 0xf7ff2001, 
+    0x2000fba3, 0xfbdbf7ff, 0xf7ff2000, 0x2104fbf8, 0xf7ff2001, 0x2001fa20, 0xfa65f7ff, 0x462849c8, 
+    0xf7fe7809, 0x2000fce0, 0xfcbcf7ff, 0x23014cc5, 0x21402206, 0xf01c4620, 0xf240ff7e, 0x46201900, 
+    0x46492300, 0xf01c2208, 0x4cbfff76, 0x22092300, 0x2100f240, 0xf01c4620, 0x2300ff6e, 0x22084649, 
+    0xf01c4620, 0x2300ff68, 0x22074620, 0xf01c2180, 0x2300ff62, 0x22064620, 0xf01c2140, 0x4db3ff5c, 
+    0x22072300, 0x46282180, 0xff55f01c, 0x46282301, 0x21402206, 0xff4ff01c, 0x46282300, 0x21202205, 
+    0xff49f01c, 0x46282300, 0x21102204, 0xff43f01c, 0x46282301, 0x21082203, 0xff3df01c, 0x46282300, 
+    0x21022201, 0xff37f01c, 0x46282301, 0x46192200, 0xff31f01c, 0x23014d9b, 0x46192200, 0x46283d0e, 
+    0xff29f01c, 0x23014f97, 0x03de220f, 0x46311ebf, 0xf01c4638, 0xf8dfff20, 0x23018258, 0x46492208, 
+    0xf01c4640, 0x2300ff18, 0x22034640, 0xf01c2108, 0x2301ff12, 0x22054620, 0xf01c2120, 0x2301ff0c, 
+    0x22044620, 0xf01c2110, 0x2301ff06, 0x22034620, 0xf01c2108, 0x2301ff00, 0x22024620, 0xf01c2104, 
+    0x2300fefa, 0x220f4631, 0xf01c4638, 0x2300fef4, 0x21014628, 0xf01c461a, 0x2301feee, 0x22074620, 
+    0xf01c2180, 0x2301fee8, 0x22064620, 0xf01c2140, 0x2300fee2, 0x22084649, 0xf01c4640, 0x2301fedc, 
+    0x22034640, 0xf01c2108, 0xf7fffed6, 0x4870fd1c, 0x5468f64a, 0x30084621, 0xfeb3f01c, 0x4621486c, 
+    0xf01c300a, 0xe8bdfeae, 0x486947f0, 0x300c2100, 0xbea7f01c, 0x41f0e92d, 0x48664605, 0x460f4616, 
+    0xf0007800, 0xf7fa0001, 0x4863fffa, 0xfe96f01c, 0xd4390780, 0x220d485c, 0x0100f242, 0xf01c3812, 
+    0xb108feb8, 0xe0014c5d, 0x6480f04f, 0x22004b5c, 0x46394628, 0xfd64f01e, 0x22004b5a, 0xfca4f01e, 
+    0x460f4605, 0xf01e4620, 0x462aff27, 0xf01e463b, 0xf01eff73, 0xf3c0fedd, 0xf0815109, 0xb2810440, 
+    0x4503f3c0, 0xf01c4850, 0x462bfe6c, 0x22004d4e, 0x210f1cad, 0xf01c4628, 0x2204fe7e, 0xf6434623, 
+    0x462871f0, 0xfe77f01c, 0x4c43b14e, 0x46203c16, 0xfe54f01c, 0x0102f040, 0xf01c4620, 0xe8bdfe52, 
+    0xf7fa41f0, 0xe92dbfe4, 0x460541f0, 0x46164839, 0x7800460f, 0x0001f000, 0xffa1f7fa, 0xf01c4836, 
+    0x0740fe3d, 0x4830d449, 0xf242220d, 0x38120100, 0xfe5ff01c, 0x4c35b108, 0xf04fe001, 0x4b3064a0, 
+    0x46282200, 0xf01e4639, 0x4b2efd0b, 0xf01e2200, 0x4605fc4b, 0x4620460f, 0xfecef01e, 0x463b462a, 
+    0xff1af01e, 0xfe84f01e, 0x5104f3c0, 0x0510f081, 0x6144f3c0, 0x0308f3c0, 0x274af3c0, 0xf0814822, 
+    0xf64f0402, 0x22077180, 0xf01c1f80, 0x463bfe24, 0x22004f1d, 0x71fff240, 0x46381f3f, 0xfe1bf01c, 
+    0x462b220b, 0x0100f64f, 0xf01c4638, 0x2200fe14, 0x211f4623, 0xf01c1cb8, 0xb34efe0e, 0x3c164c0e, 
+    0xf01c4620, 0xf040fdeb, 0xe0220104, 0xd1800800, 0xd003c282, 0xd003ca82, 0xd003d282, 0xd003da82, 
+    0x00032330, 0xd03c830e, 0xd03c804a, 0xd0034228, 0xd0039000, 0x00032228, 0xd003402a, 0x03d70a3d, 
+    0x412e8480, 0x3ff00000, 0xd003e81e, 0x04cccccd, 0x4620e002, 0xfdc5f01c, 0x41f0e8bd, 0xbf57f7fa, 
+    0x47f0e92d, 0x20004604, 0xfbd3f7ff, 0xf7ff2000, 0x2000fb2a, 0xfb49f7ff, 0x2c044efe, 0xf2404ffe, 
+    0xf8df15e0, 0xf8df83f8, 0xd07d93f8, 0xd0fc2c05, 0x20002102, 0xffa9f7fe, 0x46292300, 0x46302205, 
+    0xfdb9f01c, 0x46292300, 0x46382205, 0xfdb3f01c, 0x46292300, 0x46402205, 0xfdadf01c, 0x46292300, 
+    0x46482205, 0xfda7f01c, 0x48ee2301, 0x039e220e, 0xf01c4631, 0x4decfda0, 0x220e2301, 0x46284631, 
+    0xfd99f01c, 0x230148e9, 0x4631220e, 0xfd93f01c, 0x4ee74631, 0x220e2301, 0xf01c4630, 0x2301fd8c, 
+    0x220d4628, 0x4639035f, 0xfd85f01c, 0x46392301, 0x4630220d, 0xfd7ff01c, 0x230048de, 0x21082203, 
+    0xfd62f01c, 0xf7ff2000, 0x2000f97f, 0xf9b7f7ff, 0xf7ff2000, 0x2000f9d4, 0xf9f1f7ff, 0xf7ff2000, 
+    0x2000fa10, 0xfa2ef7ff, 0xf7ff2000, 0x2000fa4d, 0xfa7cf7ff, 0xf7ff2001, 0x2104fa95, 0xf7fe2000, 
+    0x2000ffea, 0xf82ff7ff, 0x780148cb, 0xf7fe4620, 0x4ccafaaa, 0x22072300, 0x46202180, 0xfd4bf01c, 
+    0x22062300, 0xe0002140, 0x4620e070, 0xfd43f01c, 0x46202301, 0x21202205, 0xfd3df01c, 0x46202300, 
+    0x21102204, 0xfd37f01c, 0x46202300, 0x21082203, 0xfd31f01c, 0x46202300, 0x21022201, 0xfd2bf01c, 
+    0x46202300, 0x461a2101, 0xfd25f01c, 0x23004db4, 0x21402206, 0xf01c4628, 0x2208fd1e, 0x23014628, 
+    0x46210154, 0xfd17f01c, 0x00654eae, 0x46292300, 0x46302209, 0xfd0ff01c, 0x46212300, 0x46302208, 
+    0xfd09f01c, 0x46302300, 0x21802207, 0xfd03f01c, 0x46302300, 0x21402206, 0xfcfdf01c, 0x46302300, 
+    0x21202205, 0xfcf7f01c, 0x46302300, 0x21102204, 0xfcf1f01c, 0x46302300, 0x21082203, 0xfcebf01c, 
+    0x46302300, 0x21042202, 0xfce5f01c, 0x46292301, 0x46302209, 0xfcdff01c, 0x46212301, 0x46302208, 
+    0xfcd9f01c, 0x47f0e8bd, 0xbb1df7ff, 0x20032102, 0xfebbf7fe, 0x4629230d, 0x46302205, 0xfccbf01c, 
+    0x4629230d, 0x46382205, 0xfcc5f01c, 0x4629230d, 0x46402205, 0xfcbff01c, 0xe710230d, 0xb5104882, 
+    0xfc9cf01c, 0x48804604, 0xf01c1c80, 0x4044fc97, 0x1d00487d, 0xfc92f01c, 0x487b4044, 0xf01c1d80, 
+    0x4044fc8d, 0xf01c4879, 0x4044fc89, 0xf01c4878, 0x4044fc85, 0xf01c4877, 0x4044fc81, 0xf01c4876, 
+    0x4044fc7d, 0x38084871, 0xfc78f01c, 0x48704044, 0xf01c3808, 0x4044fc73, 0x3808486e, 0xfc6ef01c, 
+    0x486d4044, 0xf01c3808, 0x4044fc69, 0x2000406c, 0x2100f3c4, 0x2280f3c4, 0x1c404051, 0xeb012820, 
+    0xdbf50444, 0xbd10b2a0, 0x4ff3e92d, 0x46042200, 0x4611b081, 0xf7ff4610, 0x4e60fb70, 0x4f602c03, 
+    0x0a0ef06f, 0x817cf8df, 0x917cf8df, 0x2c04d042, 0x2c05d040, 0x2500d03e, 0xd0762c02, 0xd0742c01, 
+    0xd06d2c06, 0xd06c2c07, 0x2c08462a, 0x46114610, 0xf7ffd068, 0x2200fde8, 0x46114610, 0xfd8af7ff, 
+    0xf7ff2000, 0x2000fbca, 0xfde4f7fe, 0x46112201, 0xf7ff4610, 0xb2e0fb42, 0xfc6ff7ff, 0xf7fe2001, 
+    0x2000fde7, 0xfb9bf7ff, 0x23042101, 0x22004608, 0xfb19f7fe, 0x20182104, 0xfae2f00e, 0x95002300, 
+    0x46192201, 0xf00e4618, 0xe8bdf9bb, 0x20004ffe, 0xba79f7ff, 0x2200483d, 0xf01c2101, 0x2801fc2a, 
+    0x6830d107, 0xd0012801, 0xb1107838, 0x0000f898, 0x2000b1a0, 0x46019a02, 0xfd4cf7ff, 0xf7ff2001, 
+    0xb2e0fa62, 0xfe2cf7ff, 0x20142100, 0xfab8f00e, 0xd0182c03, 0xf7fe2006, 0xe15cfdab, 0xff3ef7ff, 
+    0xfc8af01e, 0x464b2200, 0xfee2f01e, 0xf01f4652, 0x4b27fafa, 0xf01e2200, 0x9a02fccf, 0xe004e7dc, 
+    0xe102e0eb, 0x2000e128, 0x2001e7e5, 0xfa3bf7ff, 0xb080f8df, 0x21022201, 0xf01c4658, 0xb108fbea, 
+    0xd1022c02, 0xf7ffb2e0, 0x2006fc08, 0xfd80f7fe, 0xe0312c02, 0xd003c284, 0xd003ca84, 0xd003d284, 
+    0xd003da84, 0xd003c01e, 0xd003c81e, 0xd003d01e, 0xd003d81e, 0xd1800800, 0x00032330, 0xd0034228, 
+    0xd03c830e, 0xd03c804a, 0xd28f2210, 0xd003c608, 0xd003ce08, 0xd003d608, 0xd003de08, 0x00032374, 
+    0x0003238e, 0x00032367, 0x40e00000, 0xd0035040, 0x40140000, 0xd28f007c, 0x6830d026, 0xd0012801, 
+    0xb1107838, 0x0000f898, 0x2000b3e8, 0x46019a02, 0xfd29f7ff, 0x20032100, 0xfa42f00e, 0x95002300, 
+    0x46192201, 0xf00e4610, 0x2102f91b, 0xf7fe2001, 0x220df8da, 0x0100f242, 0xf01c48fe, 0x0001fb8a, 
+    0xd04b48fd, 0xe04a7841, 0x220e48fc, 0x0100f244, 0xfb7ff01c, 0xd1072801, 0x28016830, 0x7838d001, 
+    0xf898b110, 0xb1b80000, 0x9a022000, 0xf7ff4601, 0x2100fcfa, 0xf00e200c, 0x2300fa13, 0x22029500, 
+    0x21014618, 0xe018e000, 0xf8eaf00e, 0x780148ec, 0xf7fe2002, 0xe025f8a8, 0xfe90f7ff, 0xfbdcf01e, 
+    0x464b2200, 0xfe34f01e, 0xf01f4652, 0x4be5fa4c, 0xf01e2200, 0x9a02fc21, 0xf7ffe7d9, 0xf01efe7f, 
+    0x2200fbcb, 0xf01e464b, 0x4652fe23, 0xfa3bf01f, 0x22004bdc, 0xfc10f01e, 0xe7999a02, 0x20017801, 
+    0xfdb9f7fe, 0xf7ff2001, 0x2300fa8a, 0x210148d6, 0xf01c461a, 0x2001fb20, 0xfca0f7fe, 0xd0062c02, 
+    0x46582201, 0xf01c2102, 0xb118fb24, 0x2304e008, 0xe0012201, 0x22002304, 0x46082101, 0xf9f3f7fe, 
+    0x46582201, 0xf01c2102, 0x2801fb14, 0x2c01d179, 0xe8bdd177, 0xf7ff4ffe, 0x2200ba80, 0x46114610, 
+    0xfc91f7ff, 0x46102200, 0xf7ff4611, 0x2200fc33, 0x46112304, 0xf7fe2001, 0x2004f9d6, 0xfbe2f7fe, 
+    0x4ffee8bd, 0xf7ff2001, 0x2200b8e4, 0x46114610, 0xfc79f7ff, 0x46102200, 0xf7ff4611, 0x4cb3fc1b, 
+    0x22072301, 0x46202180, 0xfad5f01c, 0x46202301, 0x02592209, 0xfacff01c, 0x46202208, 0x01512301, 
+    0xfac9f01c, 0x46202300, 0x21102204, 0xfac3f01c, 0x22002304, 0xe02e2101, 0xfc55f7ff, 0x46102200, 
+    0xf7ff4611, 0x4ca2fbf7, 0xf7ff7820, 0x2006fcd9, 0xfc5ef7fe, 0x20142100, 0xf962f00e, 0x7803489d, 
+    0x9500b163, 0x78222100, 0xf00e2000, 0x489af839, 0x28037800, 0x2304d00c, 0xe7db2201, 0x462b4897, 
+    0x95007800, 0xd1ed2801, 0x21017822, 0xe008e7ec, 0x22002304, 0xb0034611, 0xe8bd2001, 0xf7fe4ff0, 
+    0xe8bdb972, 0x21098ffe, 0x422bf04f, 0x2000f44f, 0xf7f1b510, 0x2001fcd4, 0x11f4f240, 0xfc81f7f1, 
+    0x78014887, 0xf7f12001, 0x4986fc6b, 0xf7f12001, 0x4885fc67, 0x22082300, 0x3100f240, 0xfa6bf01c, 
+    0x20004982, 0x80c84a74, 0x80488088, 0x48798008, 0x7803497f, 0xf7fb487d, 0x2172f811, 0x0080f44f, 
+    0xfc87f7f1, 0xf01c487b, 0xf020fa39, 0x487a0120, 0xfa37f01c, 0x1c804877, 0xfa30f01c, 0x48764601, 
+    0xf01c1c80, 0x2004fa2e, 0xfb7ff7fe, 0xf7fe2001, 0x2100fbc5, 0xf7f82040, 0xe8bdfe67, 0x20004010, 
+    0xbbbcf7fe, 0x4c60b570, 0x21012300, 0x4620461a, 0xfa31f01c, 0xf01c1fa0, 0x1ea5fa11, 0x46282302, 
+    0x21072200, 0xfa27f01c, 0x46282302, 0x21702204, 0xfa21f01c, 0xf2402302, 0x22087100, 0xf01c4628, 
+    0x2302fa1a, 0x0100f247, 0x4628220c, 0xfa13f01c, 0x1f202100, 0xf9f5f01c, 0x46202301, 0x46192200, 
+    0xfa09f01c, 0xf7fe2001, 0x2100fb89, 0xf7f82040, 0xe8bdfe2b, 0x20004070, 0xbb80f7fe, 0x4d4fb570, 
+    0x35204c4e, 0x46202140, 0xf9dbf01c, 0x42ac1ca4, 0x4c4ad9f8, 0x34804d49, 0x462035a0, 0xf01c2140, 
+    0x1ca4f9d0, 0xd9f842ac, 0x4c454d45, 0x2140351c, 0xf01c4620, 0x1ca4f9c6, 0xd9f842ac, 0x4d404c40, 
+    0x359a3480, 0x21404620, 0xf9bbf01c, 0x42ac1ca4, 0x4d3cd9f8, 0x35204c3b, 0x46202140, 0xf9b1f01c, 
+    0x42ac1ca4, 0x4c37d9f8, 0x34804d36, 0x462035a0, 0xf01c2140, 0x1ca4f9a6, 0xd9f842ac, 0x4c324d32, 
+    0x2140351c, 0xf01c4620, 0x1ca4f99c, 0xd9f842ac, 0x4d2d4c2d, 0x359a3480, 0x21404620, 0xf991f01c, 
+    0x42ac1ca4, 0x4d29d9f8, 0x35204c28, 0x46202140, 0xf987f01c, 0x42ac1ca4, 0x4c24d9f8, 0x34804d23, 
+    0x462035a0, 0xf01c2140, 0x1ca4f97c, 0xd9f842ac, 0x4c1f4d1f, 0x2140351c, 0xf01c4620, 0x1ca4f972, 
+    0xd9f842ac, 0x4d1a4c1a, 0x359a3480, 0x21404620, 0x0000e030, 0xd28f2002, 0x000323b4, 0xd28fffd4, 
+    0x00032330, 0x40140000, 0xd00305cc, 0xd03c804a, 0x0003227e, 0x00032411, 0x00032270, 0x00032372, 
+    0x00032396, 0xdcba01f5, 0xd0035022, 0x000323cc, 0x000323e2, 0xd003c286, 0xd003e286, 0xd003c400, 
+    0xd003c500, 0xd003cc00, 0xd003cd00, 0xd003d400, 0xd003d500, 0xf935f01c, 0x42ac1ca4, 0x4dd4d9c6, 
+    0x35204cd3, 0x46202140, 0xf92bf01c, 0x42ac1ca4, 0x4ccfd9f8, 0x34804dce, 0x462035a0, 0xf01c2140, 
+    0x1ca4f920, 0xd9f842ac, 0x4cca4dca, 0x2140351c, 0xf01c4620, 0x1ca4f916, 0xd9f842ac, 0x4dc54cc5, 
+    0x359a3480, 0x21404620, 0xf90bf01c, 0x42ac1ca4, 0xbd70d9f8, 0x41f0e92d, 0x48bf2301, 0x031c220c, 
+    0xf01c4621, 0x48bdf918, 0x220c2301, 0xf01c4621, 0x48bbf912, 0x220c2301, 0xf01c4621, 0x48b9f90c, 
+    0x220c2301, 0xf01c4621, 0x48b3f906, 0x230010a4, 0x220a4621, 0xf01c3024, 0x48b0f8fe, 0x220a2300, 
+    0x30244621, 0xf8f7f01c, 0x230048ad, 0x4621220a, 0xf01c3024, 0x48abf8f0, 0x220a2300, 0x30244621, 
+    0xf8e9f01c, 0x00e448a4, 0x46212300, 0x3058220d, 0xf8e1f01c, 0x230048a1, 0x4621220d, 0xf01c3058, 
+    0x489ff8da, 0x220d2300, 0x30584621, 0xf8d3f01c, 0x2300489c, 0x4621220d, 0xf01c3058, 0x4c96f8cc, 
+    0x22002301, 0x345c4619, 0xf01c4620, 0x4d93f8c4, 0x22002301, 0x355c4619, 0xf01c4628, 0x4e90f8bc, 
+    0x22002301, 0x365c4619, 0xf01c4630, 0x4f8df8b4, 0x22002301, 0x375c4619, 0xf01c4638, 0x2300f8ac, 
+    0x22054620, 0xf01c2120, 0x2300f8a6, 0x22054628, 0xf01c2120, 0x2300f8a0, 0x22054630, 0xf01c2120, 
+    0x2300f89a, 0x22054638, 0xf01c2120, 0x2300f894, 0x461a2107, 0xf01c1ca0, 0x2300f88e, 0x461a2107, 
+    0xf01c1ca8, 0x2300f888, 0x461a2107, 0xf01c1cb0, 0x2300f882, 0x461a2107, 0xe8bd1cb8, 0xf01c41f0, 
+    0xb538b87a, 0xf64b4870, 0xf01c31b5, 0x2301f85a, 0x220e486e, 0xf01c0399, 0x486bf86e, 0x22002301, 
+    0x386e4619, 0xf867f01c, 0x4869231f, 0x015c2205, 0xf01c4621, 0x4867f860, 0x2205231f, 0xf01c4621, 
+    0x4865f85a, 0x2205231f, 0xf01c4621, 0x4863f854, 0x2205231f, 0xf01c4621, 0x2200f84e, 0x46112304, 
+    0xf7fd2001, 0xf7ffff30, 0x200ffdbe, 0x0395f647, 0x0202f247, 0x0102f640, 0xf2439000, 0xf7fc1045, 
+    0x4857f887, 0xf01c2100, 0x484bf81c, 0x22022300, 0x30322104, 0xf82ff01c, 0x23004848, 0x21042202, 
+    0xf01c3032, 0x4846f828, 0x22022300, 0x30322104, 0xf821f01c, 0x23004843, 0x21042202, 0xf01c3032, 
+    0x4848f81a, 0x78004948, 0xf7fd7809, 0x2000fd6c, 0xfaeaf7fe, 0x46082101, 0xff52f7fe, 0xf2404836, 
+    0x23027400, 0x22084621, 0xf01c3062, 0x4833f804, 0x22082302, 0x30624621, 0xfffdf01b, 0x23024830, 
+    0x46212208, 0xf01b3062, 0x482efff6, 0x22082302, 0x30624621, 0xffeff01b, 0x10a4482d, 0x46212305, 
+    0x1e802206, 0xffe7f01b, 0x2305482a, 0x46212206, 0xf01b1e80, 0x4828ffe0, 0x22062305, 0x1e804621, 
+    0xffd9f01b, 0x23054825, 0x46212206, 0xf01b1e80, 0x481fffd2, 0x0400f641, 0x46212301, 0x381e220b, 
+    0xffc9f01b, 0x2301481b, 0x4621220b, 0xf01b381e, 0x4819ffc2, 0x220b2301, 0x381e4621, 0xffbbf01b, 
+    0x23014816, 0x4621220b, 0xf01b381e, 0x2100ffb4, 0xf7ff2003, 0x2001fb39, 0xfc6ff00b, 0x46082100, 
+    0xfb32f7ff, 0xfe86f7ff, 0x4038e8bd, 0x0000e5a6, 0xd003dc00, 0xd003dd00, 0xd003c22a, 0xd003ca2a, 
+    0xd003d22a, 0xd003da2a, 0xd03c80b8, 0xd03c830c, 0xd003c01e, 0xd003c81e, 0xd003d01e, 0xd003d81e, 
+    0xd0034224, 0x0003227e, 0x00032330, 0x41f0e92d, 0x461d4c84, 0x4616b283, 0x460f2206, 0x462021c0, 
+    0xff79f01b, 0x4620b2bb, 0x21302204, 0xff73f01b, 0x4620b2b3, 0x210c2202, 0xff6df01b, 0x4620b2ab, 
+    0x41f0e8bd, 0x21032200, 0xbf65f01b, 0x41f0e92d, 0x46142301, 0x4607460e, 0x21024873, 0xf01b461a, 
+    0x2100ff5a, 0x0000f241, 0xfb7ef7f8, 0x23014d6f, 0x0299220a, 0xf01b4628, 0x2204ff4e, 0xf240463b, 
+    0x462811f0, 0xff47f01b, 0x46332201, 0x46282102, 0xff41f01b, 0xf6401d2f, 0xf24c0100, 0xb1340600, 
+    0xd0062c01, 0xd0042c02, 0xd0092c03, 0x2300e013, 0x2301e000, 0x220b4628, 0xff2df01b, 0xe0052300, 
+    0x46282300, 0xf01b220b, 0x2301ff26, 0x220e4631, 0xf01b4638, 0x4628ff20, 0x41f0e8bd, 0x22022301, 
+    0xf01b2104, 0x4851bf18, 0xb5102100, 0xf01b3016, 0x484efef8, 0x30182100, 0xfef3f01b, 0x2100484b, 
+    0xf01b3012, 0x4849feee, 0x30142100, 0xfee9f01b, 0x21004846, 0xf01b301a, 0x4844fee4, 0xe8bd2100, 
+    0x301c4010, 0xbeddf01b, 0x47f0e92d, 0x46984d3f, 0x460e4614, 0x46073544, 0x46032200, 0x46282101, 
+    0x9a08e9dd, 0xfee7f01b, 0x463b2201, 0x46282102, 0xfee1f01b, 0x46332202, 0x46282104, 0xfedbf01b, 
+    0x46281e64, 0x2204b2a3, 0xf01b2170, 0x1cacfed4, 0x22084643, 0x7100f643, 0xf01b4620, 0x2303fecc, 
+    0x46191ca6, 0x46302200, 0xfec5f01b, 0x46302302, 0x461a210c, 0xfebff01b, 0x46302301, 0x21302204, 
+    0xfeb9f01b, 0x46302300, 0x21c02206, 0xfeb3f01b, 0x464b2208, 0x7100f640, 0xf01b4628, 0x2200feac, 
+    0x217f4653, 0xf01b4620, 0x2301fea6, 0x22034628, 0xf01b2108, 0x4628fea0, 0x47f0e8bd, 0x22032300, 
+    0xf01b2108, 0xb570be98, 0x460d4c10, 0x46014616, 0x46203444, 0xfe75f01b, 0x46291ca0, 0xfe71f01b, 
+    0x46311d20, 0xfe6df01b, 0x46202301, 0x21082203, 0xfe81f01b, 0xe8bd4620, 0x23004070, 0x21082203, 
+    0xbe79f01b, 0xd0030484, 0xd03c8310, 0xd0036100, 0x2801b158, 0x2802d00f, 0x2803d013, 0x2301d117, 
+    0x21024872, 0xf01b461a, 0x4870be66, 0x21022301, 0x3860461a, 0x486de7f7, 0x21022301, 0x3840461a, 
+    0x486ae7f1, 0x21022301, 0x3820461a, 0x4770e7eb, 0x4866b281, 0xf01b38e0, 0xb510be34, 0x23014c63, 
+    0x46192200, 0x46203ce0, 0xfe45f01b, 0x46202301, 0x461a2102, 0xfe3ff01b, 0x46202301, 0x21042202, 
+    0xfe39f01b, 0x46202301, 0xe8bd2203, 0x21084010, 0xbe31f01b, 0x4855b283, 0x21c02206, 0xf01b38de, 
+    0xb158be2a, 0xd00f2801, 0xd0132802, 0xd1172803, 0x484e2301, 0x46192200, 0xbe1df01b, 0x2301484b, 
+    0x46192200, 0xe7f73860, 0x23014848, 0x46192200, 0xe7f13840, 0x23014845, 0x46192200, 0xe7eb3820, 
+    0xb5704770, 0x36fff240, 0x1c754614, 0x2801b1a8, 0x2802d019, 0x2803d01d, 0xb28bd121, 0x4e3b4631, 
+    0x360e2200, 0xf01b4630, 0xb2a3fdf6, 0x46304629, 0x4070e8bd, 0xf01b220a, 0xb28bbdee, 0x4e334631, 
+    0x3e522200, 0xb28be7ee, 0x4e304631, 0x3e322200, 0xb28be7e8, 0x4e2d4631, 0x3e122200, 0xbd70e7e2, 
+    0x482ab283, 0x21032200, 0xf01b3880, 0xb283bdd4, 0xb5104826, 0x460c2200, 0xf64738d8, 0xf01b71ff, 
+    0x4822fdca, 0xe8bdb2a1, 0x38d64010, 0xbda9f01b, 0x4d1eb570, 0x220f2301, 0x3de003dc, 0x46284621, 
+    0xfdb9f01b, 0x46284621, 0x4070e8bd, 0x220f2300, 0xbdb1f01b, 0x41f0e92d, 0x4603461f, 0x46144813, 
+    0x22099e06, 0x460d387c, 0x2100f240, 0xfda3f01b, 0x2207480e, 0x462b2180, 0xf01b385e, 0x480bfd9c, 
+    0x21802207, 0x383e4623, 0xfd95f01b, 0x22074807, 0x463b2180, 0xf01b381e, 0x4633fd8e, 0xe8bd4803, 
+    0x220741f0, 0x1c802180, 0xbd85f01b, 0xd00308e0, 0x2100b51c, 0x91019100, 0x1010f82d, 0x1000f8bd, 
+    0xf01b48f8, 0x48f7fd5e, 0x1002f8bd, 0xf01b3020, 0x48f4fd58, 0x1004f8bd, 0xf01b3040, 0x48f1fd52, 
+    0x1006f8bd, 0xf01b3060, 0xbd1cfd4c, 0x220448ee, 0x4cecb510, 0xf9902130, 0x3c740000, 0x4620b283, 
+    0xfd59f01b, 0x46202304, 0x210f2200, 0xfd53f01b, 0x46202301, 0x21402206, 0xfd4df01b, 0xf01b1ca0, 
+    0x4604fd2d, 0x387048df, 0xfd28f01b, 0x4000eb04, 0xbd101040, 0xb50848dd, 0xf2447801, 0xf7f80000, 
+    0x48d8f963, 0x01c9f640, 0xf01b387e, 0x48d5fd1a, 0x1101f241, 0xf01b387c, 0x2000fd14, 0xff01f7ff, 
+    0xf7ff2001, 0x2002fefe, 0xfefbf7ff, 0xf7ff2003, 0x48ccfef8, 0x22062301, 0xf01b2140, 0x48c9fd1c, 
+    0x22062301, 0x30202140, 0xfd15f01b, 0x230148c5, 0x21402206, 0xf01b3040, 0x48c2fd0e, 0x22062301, 
+    0x30602140, 0xfd07f01b, 0x90002001, 0x46024603, 0xf7ff4601, 0xbd08ff4f, 0xf44fb570, 0xf6403400, 
+    0x46200102, 0xfefdf7f0, 0x1d0048b6, 0xfcd6f01b, 0x48b44605, 0xf01b1c80, 0xeb05fcd1, 0x46204100, 
+    0xfedef7f0, 0x302448af, 0xfcc8f01b, 0x48ad4605, 0xf01b3022, 0xeb05fcc3, 0x46204100, 0xfed0f7f0, 
+    0x304448a8, 0xfcbaf01b, 0x48a64605, 0xf01b3042, 0xeb05fcb5, 0x46204100, 0xfec2f7f0, 0x306448a1, 
+    0xfcacf01b, 0x489f4605, 0xf01b3062, 0xeb05fca7, 0x46204100, 0xfeb4f7f0, 0x4070e8bd, 0xf7ff20f0, 
+    0x2804be67, 0x2201d010, 0xf0824082, 0xb200000f, 0xd00b2901, 0x1000ea40, 0xb283b200, 0x22004891, 
+    0x388221ff, 0xbca7f01b, 0xe7f620ff, 0xeb012102, 0xf0401000, 0xe7ef000f, 0xf44fb570, 0xf6403400, 
+    0x46200102, 0xfe9df7f0, 0x1d004886, 0xfc76f01b, 0x48844605, 0xf01b1c80, 0xeb05fc71, 0x46204100, 
+    0xfe7ef7f0, 0x3024487f, 0xfc68f01b, 0x487d4605, 0xf01b3022, 0xeb05fc63, 0x46204100, 0xfe70f7f0, 
+    0x30444878, 0xfc5af01b, 0x48764605, 0xf01b3042, 0xeb05fc55, 0x46204100, 0xfe62f7f0, 0x30644871, 
+    0xfc4cf01b, 0x486f4605, 0xf01b3062, 0xeb05fc47, 0x46204100, 0xfe54f7f0, 0x2100486b, 0x0000f990, 
+    0x4070e8bd, 0xe92de79d, 0x460c47f0, 0x220f4965, 0x1940eb01, 0xeb014966, 0x200128c0, 0x75e4eb00, 
+    0x03c14603, 0x3880485f, 0xfc45f01b, 0x46482206, 0xf01b2140, 0xb246fc4e, 0xf01b4640, 0x2c00fc1f, 
+    0xda004607, 0x485b4264, 0xf990b224, 0x28040000, 0x2805d002, 0xe003d002, 0xe00000a0, 0xb2040060, 
+    0x2204462b, 0x21104640, 0xfc25f01b, 0xe0052500, 0x46482111, 0xfc05f01b, 0xb22d1c6d, 0xdbf742a5, 
+    0x4648b2b3, 0x21402206, 0xfc15f01b, 0x46404639, 0x47f0e8bd, 0xbbf5f01b, 0x4d42b570, 0x1cac3d7e, 
+    0x2801b120, 0x2802d00a, 0xe02ad10f, 0x46282306, 0x21f02204, 0xfbfff01b, 0xe0012303, 0xe0212307, 
+    0x46202204, 0xf01b2170, 0x2305fbf6, 0x22044628, 0xf01b21f0, 0x2302fbf0, 0x22044620, 0xf01b2170, 
+    0x2305fbea, 0x0100f24f, 0x4628220c, 0xfbe3f01b, 0xf2474620, 0xe8bd0100, 0x23024070, 0xf01b220c, 
+    0x2308bbda, 0x22044628, 0xf01b21f0, 0x2302fbd4, 0x4601e7d6, 0xb5704823, 0xf242387e, 0x1c854424, 
+    0x3613f241, 0xf2472908, 0xd22b4287, 0xf001e8df, 0x160a0704, 0x1f181610, 0x2163f245, 0xf247e00a, 
+    0xe0014185, 0x7187f247, 0xfb9bf01b, 0xe0144631, 0x418cf240, 0xfb95f01b, 0xe00e4621, 0xe7f34611, 
+    0x61a7f249, 0xfb8df01b, 0x2102f240, 0xf64be005, 0xf01b01c9, 0xf240fb86, 0x46281101, 0x4070e8bd, 
+    0xbb7ff01b, 0xb570bd70, 0x22004c06, 0x4605210f, 0x46203c7e, 0xfb9df01b, 0xb2401b40, 0xdd0b280f, 
+    0xe00c200f, 0xd0030882, 0x00032283, 0x0003227f, 0xd003c28c, 0x0003227e, 0xda002800, 0xb2832000, 
+    0xe8bd4620, 0x22004070, 0xf01b210f, 0xb430bb74, 0xb1419902, 0x2408f245, 0x1aa42100, 0xda094199, 
+    0x0409f06f, 0x2b00e02d, 0x2401da01, 0xf04fe029, 0xe02634ff, 0x0100f244, 0xf1731a51, 0xdb020100, 
+    0x0403f06f, 0xf242e01d, 0x1a510100, 0x0100f173, 0x0401f06f, 0x2b00da15, 0x0324da13, 0x1aa41361, 
+    0xdb044199, 0x13a14c68, 0x41991aa4, 0x2402da01, 0x4c66e007, 0x1aa213e1, 0xda014199, 0xe0002404, 
+    0xf64f240a, 0xb1500100, 0xd00d2801, 0xf04fb2a3, 0x2802020b, 0x485ed00d, 0xf01bbc30, 0x485cbb2c, 
+    0xb2a3220b, 0xe7f73860, 0x220b4859, 0x3840b2a3, 0x4857e7f2, 0xe7ef3820, 0x23074855, 0xf6402208, 
+    0x38ea7100, 0xf01bb510, 0x4851fb16, 0x22002301, 0x386e4619, 0xfb0ff01b, 0x2301484d, 0x46192200, 
+    0xf01b384e, 0x484afb08, 0x22002301, 0x382e4619, 0xfb01f01b, 0x23014846, 0x46192200, 0x4010e8bd, 
+    0xf01b380e, 0xb570baf8, 0xf6404605, 0xf44f0103, 0xf7f03000, 0xf7fffcf6, 0x4c3efca0, 0x46082100, 
+    0x2000f994, 0xf994f7fa, 0xfd80f7ff, 0x7025b201, 0x46101402, 0xfd0bf7ff, 0x0000f994, 0xfc68f7ff, 
+    0x0000f994, 0xfcadf7ff, 0x0000f994, 0xfcf8f7ff, 0x20012100, 0xfbe3f7fa, 0x2000f994, 0x200c2100, 
+    0xf930f7fa, 0xf9942101, 0x46082000, 0xf970f7fa, 0x4070e8bd, 0xe92de620, 0x46824ff8, 0x909cf8df, 
+    0x46e8a025, 0x462a2500, 0x90006800, 0x1000f999, 0x0001eb0d, 0xf81021ff, 0x481d3c03, 0xf01b3888, 
+    0x2704faaa, 0xf1ba2610, 0xd0230f00, 0xf7ff2400, 0x4138fd3d, 0xb2e41c64, 0x440542b4, 0xf44fd3f7, 
+    0x46293080, 0xfc8cf7f0, 0x2000f999, 0xeb081228, 0x22000102, 0x1c03f811, 0x49114348, 0xf1c17809, 
+    0x41080117, 0x31fff240, 0x0309f3c0, 0x38864808, 0xfa81f01b, 0x22024806, 0x46532104, 0xf01b388e, 
+    0xe8bdfa7a, 0x00008ff8, 0xffffc000, 0xffffadf8, 0xd00308ee, 0x00032283, 0x00b6b1b6, 0x0003227e, 
+    0x0003227f, 0x4cb0b510, 0x4620b281, 0xfa49f01b, 0x46202100, 0xfa45f01b, 0xf64f4cab, 0x3c1071ff, 
+    0xf01b4620, 0x4620fa3e, 0x4010e8bd, 0xf01b2100, 0xf04fba38, 0xb51030ff, 0xffe4f7ff, 0xf01b48a3, 
+    0xe8bdfa27, 0x20044010, 0xbf1df7f7, 0x9c02b510, 0x70427001, 0x70c47083, 0xe92dbd10, 0x250f41fc, 
+    0x260b2400, 0x220002ef, 0xe9cd463b, 0x46116500, 0xf7f6b2e0, 0x1c64fea0, 0xdbf42c04, 0x81fce8bd, 
+    0x41fce92d, 0xf6472400, 0x260b0700, 0x22004625, 0x4611463b, 0x6500e9cd, 0xf7f6b2e0, 0x1c64fe8c, 
+    0xdbf42c04, 0xb570e7ea, 0x46052400, 0x21012200, 0xf7f6b2e0, 0xf825fe6e, 0x1c640014, 0xdbf52c04, 
+    0xb570bd70, 0x46052400, 0x060ef06f, 0x21002202, 0xf7f6b2e0, 0xf01dfe5e, 0x4632fa78, 0xf903f01e, 
+    0x03c4eb05, 0x2c041c64, 0x0100e9c3, 0xbd70dbee, 0x46082101, 0xf7f6b510, 0x2101fdab, 0xf7f64608, 
+    0xf010fda7, 0xd0000020, 0xbd102001, 0x220d4870, 0x0100f242, 0xf01bb510, 0x2800f9ec, 0x2001d000, 
+    0xe92dbd10, 0xf24441f0, 0x460c0600, 0x4607220e, 0x48684603, 0xf01b4631, 0x4867f9ce, 0xf01b2100, 
+    0x4864f9b0, 0x38504d63, 0x2c023d44, 0x2c01d00e, 0x2300d013, 0x21012200, 0xf9bdf01b, 0x4631463b, 
+    0xe8bd4628, 0x220e41f0, 0xb9b5f01b, 0x463b2200, 0xf01b2101, 0x2300f9b0, 0x463be7f1, 0xe92de7ea, 
+    0x4c5441f0, 0x4615461f, 0x3422460e, 0x22004603, 0x21034620, 0xf99ff01b, 0x46332202, 0x4620210c, 
+    0xf999f01b, 0x462b2204, 0x46202130, 0xf993f01b, 0x463b2206, 0x462021c0, 0xf98df01b, 0xe8bd4620, 
+    0x220841f0, 0x01512301, 0xb985f01b, 0x4d41b570, 0x21032200, 0x46283522, 0xf98bf01b, 0x46042202, 
+    0x4628210c, 0xf985f01b, 0x0480ea44, 0x22044628, 0xf01b2130, 0xea44f97e, 0x46281400, 0x21c02206, 
+    0xf977f01b, 0x1080ea44, 0xbd70b280, 0x460db570, 0x48324604, 0xf01b4611, 0x4830f944, 0x1e804629, 
+    0xf93ff01b, 0x4621482d, 0x4070e8bd, 0xf01b1f00, 0xb5f0b938, 0x5408e9dd, 0x7606e9dd, 0xc014f8dd, 
+    0xf040b109, 0xb10a0002, 0x0001f040, 0xf040b10b, 0xf1bc0008, 0xd0010f00, 0x0004f040, 0xf040b10f, 
+    0xb10d0010, 0x0020f040, 0xf040b10e, 0x2c000040, 0xf040d001, 0xbdf00080, 0x20004601, 0xb5102901, 
+    0x2903d00c, 0x4816d115, 0x213c2202, 0xf931f01b, 0x2807b2c0, 0x2808d00e, 0xe00dd10a, 0x22024811, 
+    0xf01b213c, 0xb2c0f926, 0xd0032806, 0xd0032807, 0xbd102003, 0xbd102004, 0xbd102005, 0x46032200, 
+    0x21074809, 0xb907f01b, 0xd003902a, 0xc1000144, 0xd28fffd4, 0xd28f2050, 0xd28f2182, 0xd28e0030, 
+    0xd0060000, 0xd0020000, 0xd0070000, 0x220c2301, 0x0319b570, 0x46204cfe, 0xf8edf01b, 0x46202301, 
+    0x21402206, 0xf8e7f01b, 0x46202300, 0x21202205, 0xf8e1f01b, 0x46202300, 0x21102204, 0xf8dbf01b, 
+    0x46202301, 0x21802207, 0xf8d5f01b, 0x780949f1, 0xd1052901, 0x46202300, 0x21042202, 0xf8cbf01b, 
+    0xf2442300, 0x220e0100, 0xf01b4620, 0x2300f8c4, 0x22074620, 0xf01b2180, 0x4ce5f8be, 0x220a2300, 
+    0x4100f240, 0x46203c10, 0xf8b5f01b, 0x46202208, 0x01512300, 0xf8aff01b, 0xf2404ddd, 0x230014c0, 
+    0x1dad4621, 0x46282206, 0xf8a5f01b, 0x46282306, 0x21382203, 0xf89ff01b, 0x46282306, 0x21072200, 
+    0xf899f01b, 0x46282302, 0x00e12209, 0xf893f01b, 0x46212306, 0x461a1cad, 0xf01b4628, 0x1faef88c, 
+    0x46302302, 0x21072200, 0xf885f01b, 0x46282300, 0x461a2107, 0xf87ff01b, 0x46212306, 0x4630461a, 
+    0xf879f01b, 0x4cc24621, 0x3c0c2306, 0x4620461a, 0xf871f01b, 0xe8bd4620, 0x23064070, 0x21072200, 
+    0xb869f01b, 0x43f8e92d, 0x46942500, 0x460c2601, 0xf04f2703, 0x2b010802, 0x49b7d014, 0xf0017809, 
+    0xf3c10c03, 0x92001281, 0x1301f3c1, 0x0281f3c1, 0xf7ff4661, 0x7025fe0b, 0xf8847066, 0x70e78002, 
+    0x83f8e8bd, 0x0103f00c, 0xf3cc9100, 0xf3cc0381, 0xf3cc1201, 0xf7ff1181, 0x7027fdf9, 0x8001f884, 
+    0x70e570a6, 0xb538e7ec, 0x78204ca3, 0x7280f440, 0x802248a2, 0x48a26801, 0xf9902903, 0xd0030000, 
+    0x2802b3b8, 0xe003d036, 0xd10107c0, 0xe0002301, 0x489c2300, 0xf7ff4669, 0x7820ffb5, 0x1000f99d, 
+    0xf3c00782, 0x0f520381, 0xf99d4091, 0x005b2001, 0xf3c0409a, 0x43111301, 0x2002f99d, 0xf3c0005b, 
+    0x409a1081, 0xf99d4311, 0x00402003, 0x43114082, 0x2100b28c, 0x20054622, 0xfa51f7f0, 0x0003f004, 
+    0x1381f3c4, 0x1201f3c4, 0x0181f3c4, 0xfe47f7ff, 0xe7ffbd38, 0x78004884, 0xd1c92801, 0xb538e7c6, 
+    0xd0042801, 0xb1282403, 0x8800487b, 0xf7ffb138, 0xe026ffaa, 0x94002302, 0x21002201, 0x487ae01e, 
+    0x78022500, 0x2a014875, 0x48756801, 0x0000f990, 0x2903d002, 0xe04cd04b, 0x2802b120, 0x2903d002, 
+    0xe046d002, 0xd0442903, 0x22012300, 0x20032102, 0xfe15f7ff, 0x95002301, 0x21032202, 0xf7ff4869, 
+    0x486afd75, 0xf9904c67, 0x5c611000, 0xf9947001, 0xf9943003, 0xf9942002, 0xf9941001, 0xf7ff0000, 
+    0xf994f825, 0xf9943003, 0xf9942002, 0xf9941001, 0xf7f90000, 0xf994fc3b, 0xf9943003, 0xf9942002, 
+    0xf9941001, 0xf7fa0000, 0xf994fe01, 0xf9943003, 0xf9942002, 0xf9941001, 0xf00e0000, 0xf7fffa0c, 
+    0xe8bdfe05, 0x46014038, 0xf01a4851, 0x07c0bf6a, 0x2303d0ba, 0x21012202, 0xf7ff2000, 0xe799fdd0, 
+    0x5ff0e92d, 0x484a4681, 0x31b8f64b, 0xf01a30a6, 0x4c48ff58, 0x220e2301, 0x46200399, 0xff6bf01a, 
+    0x23004d45, 0x21042202, 0xf01a4628, 0x4843ff64, 0x22032301, 0xf01a2108, 0x4841ff5e, 0x0600f241, 
+    0xf5b28802, 0xd0087fac, 0x7fa4f5b2, 0xf5b2d005, 0xd0027fb4, 0x7fbcf5b2, 0x2300d105, 0x220c4631, 
+    0xf01a4628, 0x4f33ff48, 0x22022301, 0x21043760, 0xf01a4638, 0xf8dfff40, 0x230180c0, 0xf1a8220f, 
+    0x03d90820, 0xf01a4640, 0x2301ff36, 0x220c46b3, 0x46404631, 0xff2ff01a, 0x46402300, 0x21402206, 
+    0xff29f01a, 0x46402300, 0x21202205, 0xff23f01a, 0x23004824, 0x21402206, 0xff1df01a, 0x0f00f1b9, 
+    0x1600f240, 0x2301d017, 0x22084631, 0xf01a4628, 0x2301ff12, 0x22074628, 0xf01a2180, 0x2301ff0c, 
+    0x22064628, 0xf01a2140, 0x2301ff06, 0x22054628, 0xf01a2120, 0xf240ff00, 0x48134900, 0x46492300, 
+    0xf01a220a, 0x2301fef8, 0x0800f640, 0xe01d220b, 0xd003902c, 0x00032362, 0x000322ac, 0x00032374, 
+    0x00032228, 0x000323b4, 0x00032304, 0x00032283, 0xd03c8012, 0xd28f0000, 0xd28e0040, 0xd28f2070, 
+    0x00032392, 0xd003507c, 0xd28fffc0, 0xa40cf8df, 0x46504641, 0xfecff01a, 0xf7ff2002, 0x2300fee0, 
+    0x21802207, 0xf01a48fe, 0x48fefec6, 0x20017801, 0xfce7f7ff, 0x23014df9, 0x46312208, 0x46283d1c, 
+    0xfeb9f01a, 0x46282301, 0x21202205, 0xfeb3f01a, 0x46282301, 0x21102204, 0xfeadf01a, 0x210048f2, 
+    0xfe8ff01a, 0x46202301, 0x46192200, 0xfea3f01a, 0x46592301, 0x4620220c, 0xfe9df01a, 0x46202301, 
+    0x0359220d, 0xfe97f01a, 0x46312300, 0x46382208, 0xfe91f01a, 0xf24048e5, 0xf01a11d4, 0x48e3fe72, 
+    0x1129f240, 0xf01a1c80, 0x2301fe6c, 0x220b4641, 0xf01a4638, 0x2300fe80, 0x220a4649, 0xf01a4638, 
+    0x4cdafe7a, 0x220b2301, 0x3c404641, 0xf01a4620, 0x2301fe72, 0x220a4649, 0xf01a4620, 0x2301fe6c, 
+    0x21024620, 0xf01a461a, 0x2301fe66, 0x22004620, 0xf01a4619, 0x2300fe60, 0x22044650, 0xf01a2130, 
+    0x230ffe5a, 0x220048ca, 0xf01a4619, 0xe8bdfe54, 0x48c75ff0, 0x22002301, 0x305a4619, 0xbe4bf01a, 
+    0x210a4ac4, 0xb5102005, 0xf899f7f0, 0xf7f72004, 0x2002fa14, 0xfa11f7f7, 0xf00b2002, 0x49bef8eb, 
+    0x70082002, 0x780048bd, 0x22ffb920, 0x46112004, 0xfa9af7f2, 0x230148ba, 0x210f2200, 0xfe2bf01a, 
+    0x22002101, 0xf0094608, 0x230ffd8d, 0x220048b0, 0xf01a4619, 0x48adfe20, 0x21042202, 0xf01a3828, 
+    0x2801fe28, 0x2000d118, 0xf95bf7fd, 0x23004ca8, 0xf240220a, 0x34284100, 0xf01a4620, 0x2300fe0c, 
+    0x2100f240, 0x46202209, 0xfe05f01a, 0x46202208, 0x01512301, 0xfdfff01a, 0x23014898, 0x03d9220f, 
+    0xf01a3834, 0x489afdf8, 0xe8bd2100, 0x30124010, 0xbdd7f01a, 0x41f0e92d, 0x210b4a96, 0xf7f02005, 
+    0x2004f83e, 0xf9b9f7f7, 0xf7f72002, 0x2001f9b6, 0xf890f00b, 0x20014990, 0x46032200, 0x210f7008, 
+    0xf01a488f, 0x4d8afdd8, 0x0400f241, 0x46212300, 0x220c350a, 0xf01a4628, 0x2303fdce, 0x46191eae, 
+    0x46302200, 0xfdc7f01a, 0x46302301, 0x21042202, 0xfdc1f01a, 0x46302301, 0x03df220f, 0xf01a4639, 
+    0x2301fdba, 0x220c4621, 0xf01a4628, 0x2300fdb4, 0x220c4621, 0xf01a4628, 0x2300fdae, 0x220f4639, 
+    0xf01a4630, 0x2300fda8, 0x21034630, 0xf01a461a, 0x2300fda2, 0x22024630, 0xf01a2104, 0x2101fd9c, 
+    0x46082200, 0xfcfef009, 0x220e4865, 0x302600a1, 0xfd9ff01a, 0xd0032800, 0x41f0e8bd, 0xb8bdf00b, 
+    0x81f0e8bd, 0x20004967, 0x7008b510, 0xfb58f7ff, 0x2301485b, 0x0319220c, 0xf01a302c, 0x2002fd7c, 
+    0xf8bff7fd, 0xfb25f7ff, 0x21004854, 0xf01a1d80, 0x4c57fd58, 0x220a2301, 0x02993428, 0xf01a4620, 
+    0x2301fd6a, 0x22094620, 0xf01a0259, 0x2208fd64, 0x23014620, 0xf01a0151, 0xf00bfd5e, 0xf7f1f859, 
+    0x2200fad3, 0x46104611, 0xfcbcf009, 0x4a492109, 0x4010e8bd, 0xf7ef2005, 0x484bbfa2, 0x4d42b570, 
+    0xb1087800, 0xe0002301, 0x46282300, 0x21082203, 0xfd41f01a, 0x78214c45, 0xd02d0788, 0xd5010708, 
+    0xd5010748, 0xe0002301, 0x46282300, 0x21022201, 0xfd31f01a, 0x07087821, 0x0748d401, 0x2301d401, 
+    0x2300e000, 0x22024628, 0xf01a2104, 0x7820fd24, 0x0103f000, 0x3052482a, 0xd9012901, 0xe0002301, 
+    0x22002300, 0xf01a2101, 0x4831fd16, 0x1d244c26, 0xb1617801, 0xe00b2301, 0x46282300, 0x21042202, 
+    0xfd09f01a, 0x46282300, 0x21022201, 0x2300e7eb, 0x22004620, 0xf01a2101, 0x4926fcfe, 0xb1097809, 
+    0xe0002301, 0x46202300, 0x21022201, 0xfcf3f01a, 0x20014921, 0x49217008, 0x4921680a, 0xd0582a01, 
+    0x22017008, 0x4d10491f, 0x70083d38, 0x46282102, 0xfceff01a, 0x46042206, 0x46282140, 0xfce9f01a, 
+    0x46284304, 0x21202205, 0xfce3f01a, 0x48164304, 0x2204b2e3, 0x48157003, 0xe0297003, 0xd28f2050, 
+    0xd0039000, 0x00032340, 0xd28e0078, 0xd28f00a4, 0xd28f2278, 0xcccc0000, 0x00032238, 0x00032279, 
+    0xd03c8316, 0x00032348, 0x000322b3, 0x000322b4, 0x00032309, 0x0003230a, 0x0003240d, 0x00032374, 
+    0x0003240b, 0x0003240f, 0x00032404, 0x000323fd, 0x21104cf9, 0xf01a4620, 0x2300fc9e, 0x22034620, 
+    0xf01a2108, 0xe8bdfc98, 0x48f44070, 0xf01a2100, 0x2200bc78, 0xe7a4700a, 0xf3c04af1, 0x70111100, 
+    0x11c0f3c0, 0x70114aef, 0x780949ef, 0xd11b2901, 0xf3c04aee, 0x70110180, 0x01c0f3c0, 0x70114aec, 
+    0x1140f3c0, 0x70114aeb, 0x1180f3c0, 0x70114aea, 0x0201f000, 0xf3c049e9, 0x780b0040, 0x700a431a, 
+    0x780a49e7, 0x700a4302, 0xe92d4770, 0x4de55ff0, 0x4be52400, 0x4fdf4ee0, 0xf8df702c, 0x781b9390, 
+    0xf8dfb318, 0x2801c38c, 0xa364f8df, 0x835cf8df, 0xe00bf89c, 0x1cdeea4f, 0x2802d01e, 0x2000d02c, 
+    0x0000f888, 0x0000f88a, 0x70387030, 0x0000f889, 0xf8df2903, 0xf8df8360, 0xf8dfa360, 0xd024b360, 
+    0xd0362905, 0xd0472904, 0x48d5e058, 0x28186800, 0xf889d318, 0xe7eb3000, 0xd1e92a01, 0xc000f88a, 
+    0x1040f3ce, 0xc000f888, 0x70387030, 0x1080f3ce, 0x3000f889, 0xe7db7028, 0xd1032a01, 0xc000f88a, 
+    0xc000f888, 0x703b7033, 0x2201e7e3, 0x21024640, 0xfc1ff01a, 0xf88a2201, 0x21020000, 0xf01a4640, 
+    0xf88bfc18, 0x24050000, 0xf89948be, 0x70011000, 0x2206e024, 0x21404640, 0xfc0bf01a, 0xf88a2206, 
+    0x21400000, 0xf01a4640, 0xf88bfc04, 0x24040000, 0x783948b4, 0xe0117001, 0x46402205, 0xf01a2120, 
+    0x2205fbf8, 0x0000f88a, 0x46402120, 0xfbf1f01a, 0x0000f88b, 0x48ab2403, 0x70017831, 0xf89a2601, 
+    0x48a91000, 0x82a4f8df, 0x4fa92901, 0x9248f8df, 0x49a4d103, 0x29017809, 0xf89bd004, 0x29011000, 
+    0xe025d022, 0x6809499e, 0xd3082912, 0x70012102, 0xfa067829, 0x4308f004, 0x403cf440, 0x2103e007, 
+    0x78297001, 0xf004fa06, 0xf4404308, 0xb281406e, 0xf01a4640, 0x4648fb96, 0xe8bd703e, 0x23005ff0, 
+    0x21082203, 0xbba7f01a, 0x78094992, 0xd00e2901, 0x70042400, 0x46232203, 0x46482108, 0xfb9bf01a, 
+    0x46402100, 0xfb7df01a, 0xe8bd703c, 0x21059ff0, 0x23017001, 0x22034648, 0xf01a2108, 0x486ffb8c, 
+    0x22002301, 0x1e804619, 0xfb85f01a, 0xfa067829, 0x4308f004, 0xf440b280, 0x4640414f, 0xfb61f01a, 
+    0xe7e2703e, 0x47f0e92d, 0x48784604, 0x46154699, 0x460e2301, 0x21042202, 0xe9dd3816, 0xf01a7808, 
+    0x4623fb6a, 0x22084c71, 0x01513c40, 0xf01a4620, 0x2207fb62, 0x21804633, 0xf01a4620, 0x220afb5c, 
+    0xf240462b, 0x46204100, 0xfb55f01a, 0x464b2209, 0x2100f240, 0xf01a4620, 0x2206fb4e, 0x2140463b, 
+    0xf01a4620, 0x2205fb48, 0x21204643, 0xf01a4620, 0x2301fb42, 0x220f4620, 0x462903dd, 0xfb3bf01a, 
+    0x46204629, 0x47f0e8bd, 0x220f2300, 0xbb33f01a, 0x2801b51c, 0x494ed11e, 0x098a79c9, 0x2a014956, 
+    0xd117700a, 0x78094955, 0xfebff7ff, 0x48424941, 0x78007809, 0x0100e9cd, 0x7803483c, 0x7802483c, 
+    0x7801483e, 0x7800483e, 0xff9cf7ff, 0x401ce8bd, 0xba1af7f6, 0xb530bd1c, 0x5403e9dd, 0x2804b10c, 
+    0xb11dd002, 0xe004b95a, 0xbd302003, 0xb932b911, 0xb109e002, 0xbd302000, 0x2002b10b, 0x2001bd30, 
+    0x4308bd30, 0x2001d000, 0xb5704770, 0x21034c3c, 0xf01a4620, 0x2181fad6, 0xf01a1f20, 0x4833fad2, 
+    0x21012300, 0x3876461a, 0xfae5f01a, 0x220f4935, 0x780b4620, 0x0100f248, 0xfaddf01a, 0x78284d32, 
+    0x2301b328, 0x22064620, 0xf01a2140, 0x7828fad4, 0x4100f647, 0xb2831e40, 0x4620220a, 0xfacbf01a, 
+    0x2207482a, 0x78032180, 0xf01a4620, 0x2301fac4, 0x22054620, 0xf01a2120, 0xf010fabe, 0x2004fbb6, 
+    0xfe8bf7f6, 0x4070e8bd, 0xf7f6200b, 0x2300bf9d, 0x21402206, 0x0000e7e1, 0xd0035256, 0xd03c8026, 
+    0x00032422, 0x0003230b, 0x0003240c, 0x00032413, 0x00032412, 0x00032407, 0x00032408, 0x00032415, 
+    0x00032414, 0x000323ff, 0x00032409, 0x00032406, 0x000331cc, 0xd28e0040, 0x00032404, 0x000323fd, 
+    0x0003222c, 0x00032405, 0x00032cd6, 0xd28f0076, 0x00032cd5, 0x000323fe, 0x00032397, 0x0003227e, 
+    0xd28f2056, 0x00032341, 0x00032342, 0x00032343, 0x41f0e92d, 0x807cf8df, 0x0700f244, 0x4639220e, 
+    0xf01a4640, 0x2801fa76, 0x481bd02c, 0x0140f44f, 0xeb018800, 0x21005000, 0xfe86f7f6, 0x22004817, 
+    0x31fff240, 0xfa65f01a, 0xf3c04604, 0xf3c02640, 0x48130508, 0xfa32f01a, 0x46220401, 0xf7ef2005, 
+    0xb14efc9e, 0x8800480f, 0xd9054285, 0x4639220e, 0xf01a4640, 0xb130fa4e, 0x2201490b, 0xf7ef2005, 
+    0x2001fc8e, 0x4909e4ac, 0x20052200, 0xfc87f7ef, 0xe4a52000, 0xd28e0042, 0x0003237e, 0xd28f208e, 
+    0xd2cf2002, 0x0003237a, 0xffee0000, 0xfffe0000, 0x4ff0e92d, 0x92c4f8df, 0xb0872000, 0x8000f8d9, 
+    0xf93ff7f9, 0x4100f240, 0x0b01f04f, 0xf8cd2205, 0x104cb00c, 0xe9cd9400, 0xf8d92101, 0x1f920000, 
+    0xf2402103, 0xf2406500, 0xf24016df, 0x465b17a7, 0xfae6f00c, 0xf04f48a2, 0xf8df0100, 0x7800a288, 
+    0x46082803, 0xf8d9d013, 0xf9333000, 0x2a002011, 0x4252da00, 0x42a11c49, 0xdbf64410, 0x20001244, 
+    0xdd1242b4, 0x1464eba4, 0x1165eba5, 0xf99ae013, 0xeb082001, 0xf9332382, 0x2a002011, 0x4252da00, 
+    0x42a11c49, 0xdbf64410, 0x42bce7e8, 0xeb04da08, 0xeb051464, 0x1c401165, 0xb20db240, 0xdbdf2810, 
+    0x0800f44f, 0x11f4f240, 0xf7ef4640, 0x4986fbca, 0xf7ef4640, 0x4639fbb5, 0xf7ef4640, 0x4621fbb1, 
+    0xf7ef4640, 0x4631fbad, 0xf7ef4640, 0x4629fba9, 0xf7ef4640, 0x497dfba5, 0xf7ef4640, 0x2000fba1, 
+    0xfa40f7f7, 0xf2404e7a, 0x46404800, 0xf7f67831, 0x2001fdcb, 0xfb26f7f5, 0xf2404f76, 0x68381100, 
+    0xf976f01b, 0x10696838, 0x01a5eb01, 0xf8204249, 0x25005f60, 0x8041462c, 0x7800486f, 0xd0372803, 
+    0x23006838, 0x0500e9cd, 0x461a2001, 0xf7f5b261, 0x1c64f97b, 0x2c04b2a4, 0x2000d3f2, 0xfb02f7f5, 
+    0x78204c66, 0xd0322801, 0xf00d2002, 0x7831f9dd, 0xf7f62040, 0xf7fefd99, 0x7831fccf, 0x0000f244, 
+    0xfd92f7f6, 0x4640220b, 0x46112300, 0x95019500, 0xfac5f7f7, 0xf241220d, 0x23000000, 0x95004611, 
+    0xf7f79501, 0x4f56fabc, 0xb3e87838, 0xe04e2001, 0x23006838, 0x0500e9cd, 0x1004f91a, 0x461a2001, 
+    0xf942f7f5, 0xb2a41c64, 0xd3f12c03, 0x2000e7c5, 0xf9aaf00d, 0xf640220e, 0x46110900, 0xf7f74648, 
+    0x2002fb57, 0xf9a0f00d, 0x20407831, 0xfd5cf7f6, 0x9000200c, 0x465f220d, 0x46112301, 0xb502e9cd, 
+    0x95059504, 0x46409001, 0xfbd2f7f7, 0x9000200d, 0x46022301, 0x7502e9cd, 0x95044601, 0x90019505, 
+    0xf7f74648, 0xe000fbc5, 0x200ee00d, 0x23019000, 0xe9cd4602, 0x46017502, 0x95059504, 0x46489001, 
+    0xfbb6f7f7, 0x7820e7af, 0xd1af2801, 0xf00b2000, 0x4605fb8b, 0xf7f72000, 0x7831f995, 0x464046c1, 
+    0xfd22f7f6, 0xd0362d00, 0xd13407e8, 0xf2464d25, 0xf8df0a00, 0x220d8094, 0xf9954651, 0xb2830000, 
+    0xf01a4640, 0x2301f8e8, 0x220f4640, 0xf01a03d9, 0x2001f8e2, 0xf948f00d, 0x46487831, 0xfd04f7f6, 
+    0x481a7839, 0xf9952900, 0x5c411000, 0x7820d102, 0xd0012801, 0xe0002001, 0xf00b2000, 0x2300f9fa, 
+    0x220d4651, 0xf01a4640, 0xb007f8c6, 0xe8bd2000, 0xf00d4ff0, 0xb007b929, 0x8ff0e8bd, 0x00032218, 
+    0x00032411, 0x000323b4, 0x99339933, 0xdcba01f5, 0x0003227f, 0x00032224, 0x00032270, 0x00032396, 
+    0x000322e4, 0x0003226a, 0xd0035092, 0x000323b8, 0x41ffe92d, 0xf04f4efe, 0x15505200, 0x1000f996, 
+    0xfaedf7ef, 0xfe74f7ff, 0xf7f72000, 0xf44ff92b, 0xf2400500, 0x462811f4, 0xfa93f7ef, 0x462849f5, 
+    0xfa7ef7ef, 0xf9944cf4, 0xb2810000, 0xf7ef4628, 0x49f2fa88, 0xf7ef4628, 0x4668fa73, 0xfd6df7f8, 
+    0x0000f994, 0xd0011c40, 0xe0232007, 0xf2404dec, 0xf8df2700, 0xf99583b0, 0x1c400000, 0xeb0017c1, 
+    0xf0217191, 0x1a400103, 0x24007028, 0xb1087828, 0xe0004639, 0x46204641, 0xfc05f7fe, 0xb2641c64, 
+    0xdbf32c04, 0x28007828, 0x48dfd105, 0xf7f27800, 0x2003fc1f, 0xe8bd7030, 0xe92d81ff, 0x24005ffc, 
+    0x46a24615, 0xfd74f01c, 0xfa0f4ed8, 0xf8dff980, 0x27018360, 0x0b80f44f, 0x49d74ad6, 0x80374668, 
+    0xa006f8ad, 0xa002f8ad, 0xa004f8ad, 0xa000f8ad, 0x3000f898, 0xfde2f7f8, 0x46582172, 0xfa59f7ef, 
+    0x46482202, 0xf00d2107, 0x4668f895, 0xfdb7f7f8, 0x46692000, 0x2010f931, 0xdb0142aa, 0x5010f821, 
+    0xb2401c40, 0xdbf52804, 0x780048c4, 0xd1042803, 0xf99048c3, 0xf8210003, 0xf8987010, 0x46683000, 
+    0x49bd4abc, 0xfdbaf7f8, 0x46582172, 0xfa31f7ef, 0x28028830, 0x1c64d103, 0x2c0ab264, 0xf8a6dbbc, 
+    0xe8bda000, 0xe92d9ffc, 0x4fa947f0, 0x5200f04f, 0x60782050, 0xf9971550, 0xf7ef1000, 0x4eb1fa40, 
+    0xf8df2000, 0x4aab82ac, 0x80f049ab, 0x807080b0, 0x46308030, 0x3000f898, 0xfd90f7f8, 0x0980f44f, 
+    0x46482172, 0xfa05f7ef, 0xf2402202, 0x21071048, 0xf840f00d, 0x4630251e, 0xf7f82401, 0x2000fd60, 
+    0x1010f936, 0xdb0142a9, 0x5010f826, 0x1010f936, 0xdc0142a1, 0x4010f826, 0xb2401c40, 0xdbef2804, 
+    0x3000f898, 0x49944a93, 0xf7f84896, 0x2172fd67, 0xf7ef4648, 0x2060f9de, 0xe8bd6078, 0xb53887f0, 
+    0x20004c83, 0x20309000, 0x46686060, 0xf86ef7f9, 0x7801488a, 0x29034668, 0x4a89d104, 0xf9922101, 
+    0x54812003, 0x78094982, 0xd10c2903, 0xf9914981, 0xf9912000, 0x5c823002, 0xf99154c2, 0xf9912001, 
+    0x5c821003, 0xf89d5442, 0x4d7f0000, 0xf89db1b8, 0xb1e80001, 0x0002f89d, 0xf89db188, 0xb1700003, 
+    0xf2422040, 0x60600110, 0xf7ef0640, 0x2003f986, 0x23017020, 0x22004628, 0xf0194619, 0xf89dff6c, 
+    0xb1280001, 0x46282301, 0x461a2102, 0xff63f019, 0x0002f89d, 0x2301b128, 0x22024628, 0xf0192104, 
+    0xf89dff5a, 0x28000003, 0x2301d005, 0x22034628, 0xf0192108, 0xbd38ff50, 0x5ff0e92d, 0x8e804604, 
+    0x26014d53, 0x7f96f5b0, 0x1a05f240, 0x1b61f240, 0xdc35d07b, 0xf2a04550, 0xd0691105, 0x28f0dc18, 
+    0xdc06d074, 0x28ceb330, 0x28cfd075, 0x60aed170, 0x28f1e07c, 0xf5b0d05c, 0xd1697f82, 0x22004944, 
+    0x311068e8, 0xfb1ff015, 0x1d4060a8, 0xe050d07c, 0xd04d2910, 0x2907dc0f, 0x2908d077, 0x290fd048, 
+    0x493bd156, 0x68e82200, 0xf0153110, 0x60a8fb0c, 0xd06b1d40, 0x291fe03d, 0x2920d069, 0xe037d148, 
+    0xf2a04558, 0xd0331161, 0xf5b0dc1b, 0xd07d7fa6, 0xf111dc07, 0xd02b0034, 0xd0782813, 0xd1372814, 
+    0xf5a0e026, 0x384d7080, 0x2813d022, 0x4928d130, 0x68e82200, 0xf0153110, 0x60a8fae6, 0xd0671d40, 
+    0x291ae017, 0xdc0fd014, 0xd07d2911, 0xd00f2912, 0xd11d2919, 0x2200491e, 0x311068e8, 0xfad3f015, 
+    0x1d4060a8, 0xe004d071, 0xd06f2921, 0xd10f2922, 0xf04f60ae, 0x491632ff, 0x311068e8, 0xfaf2f015, 
+    0x1d0060a8, 0x68a8d005, 0xe159e00c, 0xe002e0a5, 0x20cee0d4, 0x490ee209, 0x68e82200, 0xf0153110, 
+    0x60a8fae1, 0xd0671d41, 0xd1e22801, 0xf2404f08, 0x37101000, 0x3000f9b7, 0xd05f2b0f, 0xf04f0542, 
+    0xf04f080a, 0xe0244c20, 0xe0cbe0b6, 0xe11be0ef, 0x000324cc, 0x99349934, 0x0003226a, 0xdcba01f5, 
+    0x0003239c, 0xfffffa00, 0x0003227e, 0x000322a4, 0x00032411, 0x000323b4, 0x000323e2, 0x00032270, 
+    0x000323ac, 0x000323cc, 0xd0035018, 0xe139e158, 0x2b10e17f, 0x2b0ad03a, 0xf995d1ab, 0xf8df1000, 
+    0xb3919420, 0xd06f2903, 0xd06e2906, 0xd06d2902, 0xd06c2904, 0xd06b290c, 0xd06a2907, 0xd0692905, 
+    0xd0682909, 0xe002290a, 0xe19de17c, 0xd06fe1a2, 0xd18e290b, 0x46624619, 0xf8b1f7ef, 0x8038200b, 
+    0xf04f48f8, 0x463932ff, 0xf0156800, 0x60a8fa4c, 0xd0731d00, 0xe19468a8, 0xe19620cf, 0x4222f04f, 
+    0xf7ef4619, 0x702ef89c, 0xe030e773, 0xf99149ee, 0x29031000, 0x2905d003, 0x2904d001, 0x49ebd102, 
+    0xb1217809, 0x702e210f, 0xf889f7ef, 0x4619e761, 0xf7ef4662, 0xf000f884, 0x2000fa72, 0xf8a77028, 
+    0x46028000, 0x68e849e2, 0xfa1df015, 0x1d0060a8, 0x68a8d001, 0x20f0e007, 0x49dde167, 0x68e82200, 
+    0xfa11f015, 0x1d4060a8, 0x20f1d1ce, 0xf7ffe15d, 0x2002fe66, 0xf9f6f7f6, 0xf899b920, 0x1e400000, 
+    0xd2092806, 0xe008200a, 0xe036e01a, 0xe086e052, 0xe0c2e0a1, 0xe0ffe0df, 0x8038200f, 0x220049cc, 
+    0xf01568e8, 0x60a8f9f0, 0xd0021d00, 0xe6cc68a8, 0xf240e113, 0xe1381004, 0xa034f8a4, 0x9ff0e8bd, 
+    0xfdf1f7ff, 0x70282006, 0x220049c1, 0xf01568e8, 0x60a8f9da, 0xd0021d00, 0xe00968a8, 0xf240e117, 
+    0xe122100c, 0x220049ba, 0xf01568e8, 0x60a8f9cc, 0xd1891d40, 0x100df240, 0x2370e117, 0xf7ef606b, 
+    0x49b4f81e, 0x48b4221e, 0xfd77f7ff, 0x60682080, 0x70282002, 0x220049ae, 0xf01568e8, 0x60a8f9b4, 
+    0xd0011d00, 0xe6a368a8, 0x1014f240, 0xf240e0fd, 0xe0fa1015, 0x606b2390, 0xf801f7ef, 0x22002101, 
+    0xf0084608, 0x2100fd0f, 0x1080f44f, 0xf9ccf7f6, 0x20012200, 0xf0084611, 0xf00cfd05, 0xf7f6fe43, 
+    0xf7f6fdf5, 0x20a0fe0f, 0x20046068, 0x49987028, 0x68e82200, 0xf987f015, 0x1d0060a8, 0x68a8d001, 
+    0xf240e008, 0xe0d01024, 0x22004991, 0xf01568e8, 0x60a8f97a, 0xd1ac1d40, 0x1025f240, 0xf000e0c5, 
+    0x200cf991, 0x498a7028, 0x68e82200, 0xf96bf015, 0x1d0060a8, 0x68a8d001, 0xf240e008, 0xe0b4102c, 
+    0x22004983, 0xf01568e8, 0x60a8f95e, 0xd1901d40, 0x102df240, 0xf7ffe0a9, 0x2002fcbb, 0xf942f7f6, 
+    0x200ab108, 0x200fe000, 0x49798038, 0x68e82200, 0xf949f015, 0x1d0060a8, 0x68a8d001, 0xf240e008, 
+    0xe0921040, 0x22004972, 0xf01568e8, 0x60a8f93c, 0xd1c01d40, 0x1041f240, 0xf7eee087, 0xf007ff90, 
+    0x2005fb71, 0x496a7028, 0x68e82200, 0xf92bf015, 0x1d0060a8, 0x68a8d001, 0xf240e008, 0xe074104c, 
+    0x22004963, 0xf01568e8, 0x60a8f91e, 0xd1a21d40, 0x104df240, 0xf000e069, 0xf899f8ff, 0x28030000, 
+    0x2002d005, 0xf8fef7f6, 0x200ab120, 0xf8a7e003, 0xe0018000, 0x8038200f, 0x22004955, 0xf01568e8, 
+    0x60a8f902, 0xd0011d00, 0xe61768a8, 0x1060f240, 0xf8a4e04b, 0xe711b034, 0xf8adf000, 0x0000f899, 
+    0xf43f2803, 0xf885add4, 0x22008000, 0x68e84948, 0xf8e9f015, 0x1d0060a8, 0x68a8d001, 0xf240e008, 
+    0xe0321072, 0x22004942, 0xf01568e8, 0x60a8f8dc, 0xd19e1d40, 0x1073f240, 0xf000e027, 0x2002f837, 
+    0xf8c0f7f6, 0x200ab108, 0x200fe000, 0x49388038, 0x68e82200, 0xf8c7f015, 0x1d0060a8, 0x68a8d001, 
+    0xf240e5ef, 0xe010107a, 0x107bf240, 0xf240e00d, 0xe00a1082, 0x2200482b, 0x6800492d, 0xf8b3f015, 
+    0x1d4060a8, 0xf240d193, 0x86a01083, 0x2200e6c6, 0xb5102101, 0x503ff2af, 0xfef0f014, 0x20032108, 
+    0xf84ef015, 0x39104922, 0xbd1060c8, 0xf00ab510, 0x4922fc61, 0xf0194822, 0x2801fa95, 0x1300f240, 
+    0x21e2d019, 0x4618461c, 0xfe9bf7ee, 0x46202100, 0xfe86f7ee, 0x01d0f242, 0xf7ee4620, 0x4819fe9e, 
+    0x28017800, 0x2100d034, 0xe8bd4817, 0xf2014010, 0xf019312b, 0x4812bc66, 0x79c04914, 0x1000f3c0, 
+    0x28007008, 0x4c0ad00a, 0x5200f04f, 0x3c104618, 0x1000f994, 0xfec3f7ee, 0x7020200b, 0x0000bd10, 
+    0x00032270, 0x00032564, 0x0003227e, 0x000322e4, 0x000324dc, 0x44b861ec, 0x43a4170a, 0x0002e2b0, 
+    0x000331cc, 0x00032396, 0xd03c80b8, 0x00032240, 0x7110f242, 0x4965e7c8, 0xb5082001, 0x48647008, 
+    0xb1487800, 0x78014863, 0x78034863, 0x78024863, 0x78004863, 0xfd36f7f9, 0x49634862, 0x0000f990, 
+    0xfd7ef7f4, 0x21044a61, 0xf019485f, 0x4860faf1, 0x5200f04f, 0x1000f990, 0xf7ee1550, 0x2004fe80, 
+    0xfb6cf00d, 0x7008495b, 0x46032000, 0x46014602, 0xf7f59000, 0xbd08f97b, 0x4c55b510, 0x5200f04f, 
+    0xf9941550, 0xf7ee1000, 0xf00afe6a, 0xb158ff29, 0x78004851, 0xd0022803, 0x70202009, 0x2004e79e, 
+    0xffdbf7f5, 0xe7f8200b, 0xf7f82000, 0x4841fb2a, 0xf7f17800, 0x4849ffcd, 0x70222203, 0x49412300, 
+    0x4000f990, 0xf990550b, 0x23014001, 0xf990550b, 0x23024002, 0xf990550b, 0x540a0003, 0x4010e8bd, 
+    0xbe7af00a, 0x4c3ab510, 0x5200f04f, 0x606020b0, 0xf9941550, 0xf7ee1000, 0x20b1fe32, 0xf00c6060, 
+    0xf7f6fc81, 0xf7f6fc33, 0x20bbfc4d, 0x48326060, 0xb1707800, 0xd00c2807, 0x606020e0, 0x22004830, 
+    0x20026801, 0xffbef7f5, 0xfe24f00b, 0x606020f0, 0x20c0e754, 0xf00b6060, 0x20d0fe1d, 0xb570e7f7, 
+    0x20104c23, 0x01052101, 0x46286060, 0xfdb9f7ee, 0x11f4f240, 0xf7ee4628, 0x4822fdb4, 0xf0406800, 
+    0x462841d0, 0xfd9cf7ee, 0x4628491f, 0xfd98f7ee, 0xf7f82000, 0xf7f8f8d3, 0x2020f9fe, 0x48176060, 
+    0x49102400, 0x2000f990, 0xf990548c, 0x22013001, 0xf99054ca, 0x22023002, 0xf99054ca, 0x22030003, 
+    0xf00a540a, 0x4811fe19, 0xbd707004, 0x0003223f, 0x00032368, 0x0003227e, 0x00032431, 0x00032430, 
+    0x00032367, 0x000323ac, 0x0003308c, 0x000330cc, 0x000324cc, 0x00032241, 0x00032270, 0x000323b4, 
+    0x0003241c, 0x00047f78, 0xdcba01f5, 0x0003239c, 0x4cffb510, 0x4280f04f, 0xf9b41510, 0xf7ee1000, 
+    0xf00afdae, 0xb160fe6d, 0x230048fa, 0xf44f2211, 0xf0193100, 0x2001fb39, 0xfbe4f7f6, 0x8020200e, 
+    0x2007bd10, 0x48f48020, 0x49f42200, 0x3000f990, 0xf99054ca, 0x22013001, 0xf99054ca, 0x22023002, 
+    0xf99054ca, 0x22030003, 0xe8bd540a, 0xf00a4010, 0x48e7bdc3, 0x4280f04f, 0xf9b0b510, 0x15101000, 
+    0xfd7df7ee, 0xf7f848e6, 0x49e5f8ba, 0x221e2000, 0xf9312301, 0x2c1e4010, 0xf821db01, 0xf9312010, 
+    0x2c014010, 0xf821dc01, 0x1c403010, 0x2804b240, 0x48dcdbef, 0x49dc4ad8, 0x48d97803, 0xf8bef7f8, 
+    0xf44f2172, 0xf7ee0080, 0xe8bdfd34, 0xf0074010, 0xe92db939, 0x4ece41f0, 0x4280f04f, 0xf9b61510, 
+    0xf7ee1000, 0xf7fffd4c, 0x2000f8d3, 0xfb8af7f6, 0xf99048ce, 0x1c400000, 0x2012d001, 0x4dcce01f, 
+    0x2700f240, 0x832cf8df, 0x0000f995, 0x17c11c40, 0x7191eb00, 0x0103f021, 0x70281a40, 0x78282400, 
+    0x4639b108, 0x4641e000, 0xf7fd4620, 0x1c64fe7c, 0x2c04b264, 0x7828dbf3, 0xd1012800, 0x80302007, 
+    0x81f0e8bd, 0x4ff0e92d, 0x4fbda0bb, 0xe9d0b08d, 0xe9cd1000, 0x48bb100b, 0x6800683d, 0xd3142812, 
+    0x409cf648, 0xf6469004, 0x900530ad, 0x707af242, 0xf2419006, 0x90071029, 0x3063f640, 0xf2409008, 
+    0x900940e7, 0x20a9f240, 0xf244e013, 0x900430a4, 0x401cf243, 0xf2419005, 0x90064016, 0x003df640, 
+    0xf2409007, 0x9008505b, 0x207ff240, 0xf2409009, 0xf8df104d, 0xf240b25c, 0x900a4a00, 0x4280f04f, 
+    0x46504656, 0x1000f9bb, 0xfcd9f7ee, 0xf44f2100, 0xf7f52000, 0x2101fea9, 0x02082405, 0xe9cd1e8a, 
+    0xe9cd6102, 0x68380400, 0x21082300, 0xfb58f00b, 0x46132200, 0x20004611, 0x2741eb05, 0x6010f937, 
+    0xb2801c40, 0xfbc628ff, 0xd9f72386, 0xb2c91c49, 0xd3f02904, 0x0c959804, 0xea454e8b, 0x42a83583, 
+    0x7034d801, 0x2000e033, 0x46047030, 0xeb00a804, 0x68490184, 0xd82242a9, 0x7024f850, 0x0084eb00, 
+    0x1a386840, 0xfad8f01b, 0x46894680, 0xf01b1b78, 0x4605fad3, 0xa80b460f, 0x5d041901, 0x1b087849, 
+    0xfab3f01b, 0x463b462a, 0xfb16f01b, 0x464b4642, 0xf8f6f01b, 0xfa7cf01b, 0x70304420, 0x1c64e003, 
+    0x2c06b2a4, 0x7830d3d3, 0x2064b908, 0x78307030, 0x0100f640, 0x30234654, 0x46507030, 0xfc21f7ee, 
+    0x46207831, 0xfc0cf7ee, 0x22002101, 0xf0084608, 0x4c66f979, 0x4e5b2500, 0x46204a57, 0x80e5495a, 
+    0x806580a5, 0x78338025, 0xffb8f7f7, 0x0880f44f, 0x46402172, 0xfc2df7ee, 0x22004f5d, 0x46382101, 
+    0xfa07f019, 0x2201b988, 0x21024638, 0xfa01f019, 0x2202b958, 0x21044638, 0xf9fbf019, 0x2203b928, 
+    0x21084638, 0xf9f5f019, 0x2001b110, 0xfb66f7fb, 0xf2402202, 0x210710c3, 0xfa4cf00c, 0xf7f7484b, 
+    0xf9bbff6e, 0x20001002, 0x2010f934, 0xdb01428a, 0x1010f824, 0xb2401c40, 0xdbf52804, 0x4a367833, 
+    0x48424939, 0xff7af7f7, 0x46402172, 0xfbf1f7ee, 0xf00c2002, 0x2000fa29, 0xf8e3f7f8, 0xf7f92000, 
+    0x2101f846, 0x46082200, 0xf91cf008, 0xf44f2100, 0xf7f52000, 0x2004fdd9, 0xf8f0f00d, 0x23004935, 
+    0x7008461a, 0x46184619, 0xf7f49500, 0x2200feff, 0x46112001, 0xf906f008, 0xe8bdb00d, 0x481c8ff0, 
+    0x4280f04f, 0x1000f9b0, 0xf7ee1510, 0x2101bbe8, 0x028cb510, 0xf7ee4620, 0xf240fb94, 0x462011f4, 
+    0xfb8ff7ee, 0x68084924, 0x41f0f040, 0xf7ee4620, 0x4922fb77, 0xf7ee4620, 0x490dfb73, 0x8048201e, 
+    0xf7f62001, 0x480cfeef, 0x490c2400, 0x2000f990, 0xf990548c, 0x22013001, 0xf99054ca, 0x22023002, 
+    0xf99054ca, 0x22030003, 0xf00a540a, 0xe027fbf5, 0x000324e4, 0xd1800000, 0x000323b4, 0x000323ac, 
+    0x000323d4, 0x00032411, 0x000323e2, 0x0003226a, 0x0003239c, 0xfffffa00, 0x321e0a05, 0x0064503c, 
+    0x00032218, 0x0003222c, 0x00032398, 0x000323cc, 0xd00305c2, 0x00032241, 0x00047f78, 0xdcba01f5, 
+    0x700448fa, 0xe92dbd10, 0x46045ff0, 0x4df88e80, 0x1b50f240, 0xa3dcf8df, 0xf2404558, 0xf2401801, 
+    0xd0741969, 0x4540dc32, 0x1101f2a0, 0xdc16d064, 0xd06d28e6, 0xb318dc05, 0xd06c28c4, 0xd16928c5, 
+    0x28e7e073, 0xf5b0d058, 0xd1637f80, 0x220049e8, 0x31086868, 0xfd07f014, 0xd07d1d40, 0x291ce04c, 
+    0xdc0ed04a, 0xd0782909, 0xd045290a, 0xd151291b, 0x220049df, 0x31086868, 0xfcf5f014, 0xd06d1d40, 
+    0x2945e03a, 0x2946d06b, 0xe035d144, 0xf2a04548, 0xd0311169, 0xf5b0dc1a, 0xd07d7fb0, 0xf111dc07, 
+    0xd0290018, 0xd0782807, 0xd1332808, 0xf5a0e024, 0x38617080, 0x2807d020, 0x49cdd12c, 0x68682200, 
+    0xf0143108, 0x1d40fcd0, 0xe015d068, 0xd0132910, 0x2907dc0e, 0x2908d070, 0x290fd00e, 0x49c4d11a, 
+    0x68682200, 0xf0143108, 0x1d40fcbe, 0xe003d07c, 0xd07a291b, 0xd10d291c, 0xf04f49bd, 0x686832ff, 
+    0xf0143108, 0x1d01fcdf, 0x20c4d10b, 0xe11fe1c7, 0xe000e080, 0x49b6e0aa, 0x68682200, 0xf0143108, 
+    0x1d41fcd1, 0x2801d046, 0x4eb1d1e6, 0xf2402700, 0x36084000, 0x1000f9b6, 0xd03e290f, 0x29110502, 
+    0x290ad041, 0xf9b5d1d8, 0x4fab1000, 0xd06b2902, 0xd07d2901, 0xe0032903, 0xe09ee086, 0xe0dde0bf, 
+    0x2904d077, 0x2905d076, 0x2906d075, 0x2907d074, 0x2910d073, 0x2912d072, 0x2908d071, 0x290ed070, 
+    0xf7eed1ba, 0xf242facc, 0x06c80170, 0xfa85f7ee, 0x8030200b, 0xe002200f, 0xe0f9e114, 0x8028e13f, 
+    0x32fff04f, 0x0000f8da, 0xf0144631, 0x1d01fc5c, 0xe170d072, 0xe17220c5, 0xf04fe142, 0xf7ee4224, 
+    0x802ffaae, 0x4b8de798, 0x3000f993, 0xd0032b03, 0xd0012b05, 0xd1022b04, 0x781b4b89, 0x2113b133, 
+    0xf7ee802f, 0xe787fa9c, 0xe14ee149, 0x4220f04f, 0xfa95f7ee, 0xfeabf7ff, 0x2002497d, 0x200a8028, 
+    0x22008030, 0x31086868, 0xfc2df014, 0xd1071d01, 0xe14420e6, 0x22004976, 0x31086868, 0xfc23f014, 
+    0xd1cf1d40, 0xe13a20e7, 0x28017838, 0x2002d102, 0xfbf3f7f5, 0xfe83f7ff, 0x2001496d, 0x22008028, 
+    0x31086868, 0xfc0ff014, 0xf47f1d01, 0xe008af05, 0xe02de00e, 0xe06ce046, 0xe0a4e085, 0xe0e1e0bd, 
+    0xf240e0f8, 0xe11a1000, 0x8034f8a4, 0x9ff0e8bd, 0xfa55f7ee, 0x22002101, 0xf0074608, 0x495cff63, 
+    0x80282003, 0x68682200, 0xf0143108, 0x1d01fbec, 0xf240d109, 0xe102100a, 0x4955e0f4, 0x68682200, 
+    0xf0143108, 0x1d40fbe0, 0xf240d18c, 0xe0f6100b, 0xfa35f7ee, 0xf44f2100, 0xf7f51080, 0xf006fc05, 
+    0x494bfa28, 0x80282004, 0x68682200, 0xf0143108, 0x1d01fbca, 0xaed2f47f, 0x101cf240, 0xf240e0df, 
+    0xe0dc101d, 0xfa1bf7ee, 0x20012200, 0xf0074611, 0x7838ff29, 0xd00a2801, 0x2005493d, 0x22008028, 
+    0x31086868, 0xfbaff014, 0xd0041d01, 0x2002e00c, 0xfb83f7f5, 0xf240e6f0, 0xe0c01046, 0x22004934, 
+    0x31086868, 0xfb9ff014, 0xd1f31d40, 0x1047f240, 0xf000e0b5, 0x492ef920, 0x80282006, 0x68682200, 
+    0xf0143108, 0x1d01fb90, 0xf8a4d108, 0xe78db034, 0x22004927, 0x31086868, 0xfb85f014, 0xd1d91d40, 
+    0x1051f240, 0xf000e09b, 0x2002f8ab, 0xfb6af7f5, 0x200ab108, 0x200fe000, 0x8030491d, 0x68682200, 
+    0xf0143108, 0x1d01fb70, 0xf240d108, 0xe0861058, 0x22004917, 0x31086868, 0xfb65f014, 0xd1b91d40, 
+    0x1059f240, 0xf7ffe07b, 0x4911fc9d, 0x80282010, 0x68682200, 0xf0143108, 0x1d01fb56, 0xf240d108, 
+    0xe06c1060, 0x2200490a, 0x31086868, 0xfb4bf014, 0xd19f1d40, 0x1061f240, 0xf7ffe061, 0x2002fc4a, 
+    0xfb30f7f5, 0x200ab170, 0x0000e00d, 0x0003239c, 0x000324e4, 0x00032564, 0x00032270, 0x0003227e, 
+    0x000322e4, 0x8030200f, 0x22004974, 0xf0146868, 0x1d01fb2a, 0xae57f47f, 0x1068f240, 0xf8a4e03f, 
+    0xe7239034, 0xfbf5f7ff, 0x80282008, 0x2200496b, 0xf0146868, 0x1d01fb18, 0xf240d107, 0xe02e1070, 
+    0x22004966, 0xf0146868, 0x1d40fb0e, 0xf240d187, 0xe0241071, 0xfbacf7ff, 0xf7f52002, 0xb108faf3, 
+    0xe000200a, 0x8030200f, 0x2200495c, 0xf0146868, 0x1d01fafa, 0xae39f47f, 0x1078f240, 0xf240e00f, 
+    0xe00c1079, 0x1084f240, 0x4954e009, 0xf8da2200, 0xf0140000, 0x1d40fae8, 0xf240d19b, 0x86a01085, 
+    0x2200e6e4, 0xb5102101, 0x40a5f2af, 0xf926f014, 0x20032108, 0xfa84f014, 0x39084948, 0xbd106048, 
+    0x2000b5f8, 0x46689000, 0xffa0f7f7, 0x78004844, 0xd1102803, 0xf9904843, 0xf9902000, 0xf81d3002, 
+    0xf80d2002, 0xf9902003, 0xf9902001, 0xf81d0003, 0xf80d2002, 0xf89d2000, 0x28000000, 0xf89dd03a, 
+    0x28000001, 0xf89dd036, 0x28000002, 0xf89dd032, 0x28000003, 0xf242d02e, 0x46210410, 0x462806e5, 
+    0xf8bbf7ee, 0xf7f52000, 0x4b2cff3d, 0x4e2e2207, 0x46303b08, 0x2301801a, 0x46192200, 0xfe9bf018, 
+    0x46302301, 0x461a2102, 0xfe95f018, 0x46302301, 0x21042202, 0xfe8ff018, 0x46302301, 0x21082203, 
+    0xfe89f018, 0x68004821, 0xd8032810, 0x46284621, 0xf893f7ee, 0x4819bdf8, 0x4280f04f, 0x3808b508, 
+    0x1000f9b0, 0xf7ee1510, 0x4919f8ca, 0x4a1c2000, 0x70082300, 0x70084917, 0x70084917, 0x70084917, 
+    0x70112101, 0x4917461a, 0x49177008, 0x46197008, 0x20019000, 0xfbbaf7f4, 0x0140f242, 0xf7ee0648, 
+    0xf7f7f86c, 0x2001fcb8, 0xfeecf7f5, 0x4008e8bd, 0xf44f2100, 0xf7f52000, 0x0000ba77, 0x000324ec, 
+    0x00032411, 0x000323b4, 0xd0035018, 0x0003222c, 0x0003225f, 0x0003225d, 0x00032258, 0x0003225b, 
+    0x0003223f, 0x0003223d, 0x0003223a, 0x5ff0e92d, 0x46044da9, 0x4ea98e80, 0x686b28c8, 0xdc15d070, 
+    0xd0342893, 0xb300dc0d, 0xd16a2892, 0x46182200, 0x0108f105, 0xfa46f014, 0xd0261d41, 0xd1192801, 
+    0x28b4e025, 0x28b5d06f, 0xe013d15b, 0xd01128d1, 0x28c9dc0c, 0x28d0d00e, 0x4997d153, 0x46182200, 
+    0xf0143108, 0x1d40fa00, 0xe003d07e, 0xd07c28da, 0xd14628db, 0xf04f4990, 0x686832ff, 0xf0143108, 
+    0x1d01fa21, 0x2092d1d8, 0x2093e0c0, 0xf8dfe0be, 0x27008228, 0x2000f240, 0x0808f108, 0x1000f9b8, 
+    0xd027290f, 0xf04f2912, 0xf04f090a, 0xf04f5240, 0xd0274b00, 0xd1dd290a, 0x1000f9b5, 0xf82ff7ee, 
+    0x0000f9b5, 0xd06d2802, 0xd077280a, 0xd1d12806, 0x0170f242, 0xf7ed4658, 0x200bffe0, 0x0000f8a8, 
+    0x80282007, 0x1e7a6830, 0xf0144641, 0x1d01f9bc, 0xe088d06f, 0x4223f04f, 0xf811f7ee, 0xe7b9802f, 
+    0xe084e05d, 0xf9934b6e, 0x2b033000, 0x2b05d003, 0x2b04d001, 0x4b6bd102, 0xb12b781b, 0x802f2109, 
+    0xfffdf7ed, 0xe033e7a6, 0x4a20f04f, 0x46524607, 0xfff5f7ed, 0x465221f1, 0xf7ed4638, 0xf242fff0, 
+    0x46580150, 0xffa9f7ed, 0xf7f52000, 0x485efe2b, 0xf44f7801, 0xf7f52080, 0xf44ff9b7, 0xf6403000, 
+    0xf7ed0103, 0xe001ff8e, 0xe046e043, 0xff35f7fc, 0xfb17f7f6, 0x20024950, 0x22008028, 0x9000f8a8, 
+    0x68683108, 0xf96ff014, 0xd1071d01, 0xe03d20b4, 0x22004949, 0x31084618, 0xf965f014, 0xd1ae1d40, 
+    0xe03320b5, 0x22004944, 0x9000f8a5, 0x31086868, 0xf959f014, 0xd1081d01, 0xe02720c8, 0x493ee00a, 
+    0x46182200, 0xf0143108, 0x1d40f94e, 0x20c9d197, 0xe010e01c, 0xf82bf000, 0x20064937, 0x22008028, 
+    0x31086868, 0xf93ff014, 0xf47f1d01, 0x20d0af3c, 0x20d1e00c, 0x20dae00a, 0x492fe008, 0x68302200, 
+    0xf0143108, 0x1d40f930, 0x20dbd18c, 0xe8bd86a0, 0x22009ff0, 0xb5102101, 0x200ff2af, 0xff6ef013, 
+    0x20032108, 0xf8ccf014, 0x60484923, 0x2101bd10, 0x2200b570, 0xf0074608, 0x2100fc85, 0x2000f44f, 
+    0xf942f7f5, 0x20012200, 0xf0074611, 0x4c1ffc7b, 0x46082100, 0x2000f994, 0xfbbaf7f7, 0x0550f242, 
+    0x06ee4629, 0xf7ed4630, 0xf005ff18, 0x4629ff52, 0xf7ed4630, 0x2100ff12, 0xf7f72001, 0xf994fe10, 
+    0x21002000, 0xf7f7200c, 0x2101fb5d, 0x2000f994, 0xf7f74608, 0xf7fdfb9d, 0x4629f84f, 0xf7ed4630, 
+    0x480bfefc, 0x22112300, 0xf0180bb1, 0xe8bdfccd, 0x20014070, 0xbd76f7f5, 0x000324f4, 0x00032564, 
+    0x0003227e, 0x000322e4, 0x0003227f, 0x00032283, 0xd1800000, 0x4ff8e92d, 0x4a00f04f, 0x0970f242, 
+    0x46492400, 0xf7ed4650, 0x2000fed8, 0xfd5af7f5, 0x260148f9, 0x46324df9, 0x83e4f8df, 0x70064631, 
+    0x80280270, 0x90002000, 0xf8d84630, 0xf7f43008, 0x49f4fa0d, 0x4bf74af4, 0x70107808, 0x4af648f3, 
+    0x70087800, 0x680949f2, 0xd91f2910, 0x4ff37811, 0xc3ccf8df, 0xd1112905, 0x29017819, 0xf8dfd006, 
+    0xf89ee3c4, 0xea51e000, 0xd107010e, 0x294b7839, 0xf89cd904, 0x29011000, 0x1e8cd100, 0x290f7839, 
+    0xf89cd204, 0x29011000, 0x1e64d100, 0x1000f992, 0x29039600, 0xeb04d00c, 0x781b0040, 0x2100b2ca, 
+    0xf00ab240, 0x4649fa0d, 0xf7ed4650, 0xe017fe86, 0x781b0040, 0x21012203, 0xe7f2b240, 0xf7f52002, 
+    0x2801f851, 0x4cd8d009, 0xf0184620, 0xf440fc47, 0x46207180, 0xfc45f018, 0xf7f4e005, 0x8028f993, 
+    0x28008828, 0xf9b8d1ea, 0xf04f1000, 0xe8bd42a0, 0xf6404ff8, 0xf7ed0000, 0xe92dbea2, 0x240043f8, 
+    0xfc08f009, 0x48ca49c9, 0xfa3cf018, 0xf6402801, 0xd0190900, 0x464c21e2, 0xf7ed4648, 0x2100fe42, 
+    0xf7ed4620, 0xf242fe2d, 0x462001d0, 0xfe45f7ed, 0x780048c0, 0xd07d2801, 0x48bf2100, 0x43f8e8bd, 
+    0x312ef201, 0xbc0df018, 0x78304eb2, 0xf8f0f7fe, 0x49ba4fb7, 0xf3c079f8, 0x700800c0, 0xd06a2800, 
+    0x0170f242, 0xf7ed06c8, 0x2000fe28, 0xfcaaf7f5, 0x3000f44f, 0x0103f640, 0xfe13f7ed, 0xfdbdf7fc, 
+    0x4daf7a39, 0xf0017a78, 0xea400103, 0x28402001, 0xd9508028, 0xf7f42002, 0x4601ffdf, 0xf8df48a9, 
+    0x680082ac, 0x49a81a43, 0x2000f9b1, 0xf1f2fbb3, 0xf8c81cc9, 0x1e891000, 0xf7f54351, 0x488ef81b, 
+    0x463a2701, 0x88297007, 0xf8b84d8c, 0xf8df0000, 0x1a088230, 0x80284639, 0x90002000, 0xf8d84638, 
+    0xf7f43008, 0x4987f933, 0x78084a87, 0x48877010, 0x78004a89, 0x49867008, 0x29106809, 0x7811d922, 
+    0xf8df4b86, 0x2905c21c, 0x7831d111, 0xd0062901, 0xe210f8df, 0xe000f89e, 0x010eea51, 0x7819d107, 
+    0xd904294b, 0x1000f89c, 0xd1002901, 0x78191e8c, 0xe001290f, 0xe038e03b, 0xf89cd204, 0x29011000, 
+    0x1e64d100, 0x1000f992, 0x29039700, 0xeb04d008, 0x78330040, 0x2100b2ca, 0xf00ab240, 0xe017f931, 
+    0x78330040, 0x21012203, 0xe7f6b240, 0xf7f42002, 0x2801ff79, 0x4c6cd009, 0xf0184620, 0xf040fb6f, 
+    0x46200180, 0xfb6df018, 0xf7f4e005, 0x8028f8bb, 0x28008828, 0xf9b8d1ea, 0xf04f1000, 0x464442a0, 
+    0xf7ed4648, 0x2007fdcc, 0xe8bd8020, 0xf24283f8, 0xe7427110, 0x41f0e92d, 0xfb2cf009, 0x485c495b, 
+    0xf960f018, 0x28014e5b, 0x0500f640, 0x21e2d017, 0xf7ed4628, 0x2100fd66, 0xf7ed4628, 0xf242fd51, 
+    0x462801d0, 0xfd69f7ed, 0x28017830, 0x2100d03f, 0xe8bd4851, 0xf50141f0, 0xf018714b, 0x4845bb32, 
+    0xf7fe7800, 0x4c3ef815, 0x42a0f04f, 0xf9b44628, 0xf7ed1000, 0x4846fd94, 0x0702f04f, 0x4d4d4a4c, 
+    0x09c87901, 0xd0017010, 0xb1387830, 0x28017830, 0x2004d11b, 0xfa72f00c, 0xe0157028, 0x1002f3c1, 
+    0x70084945, 0xf00c2004, 0xb2c0fa69, 0x78317028, 0x4942b951, 0x1c8a7809, 0xd9014290, 0xe003702a, 
+    0x42881e89, 0x7029da00, 0xe8bd8027, 0xf24281f0, 0xe7bd7110, 0x4ff8e92d, 0x68004825, 0xd3042812, 
+    0xf44f2100, 0xf7f41080, 0x4835ff2f, 0xf8df2701, 0x250080d4, 0x907cf8df, 0x70074c19, 0x5000f888, 
+    0x0000f899, 0xd00f2801, 0xd00d2802, 0x220060a5, 0x20019500, 0x461168a3, 0xf848f7f4, 0x492a4826, 
+    0x70087800, 0x8ff8e8bd, 0xf8df4e13, 0x7830a0a0, 0xd1052805, 0x46502201, 0xf0182102, 0xb940faea, 
+    0x28047830, 0x2200d144, 0x21014650, 0xfae1f018, 0x2001b108, 0xe03be03d, 0x0003225b, 0x00032262, 
+    0x00032504, 0x00032245, 0x00032246, 0x00032243, 0x0003222c, 0x00032411, 0x0003227e, 0x00032398, 
+    0x00032365, 0x00032372, 0xd003517c, 0x0002e2b0, 0x000331cc, 0x00032396, 0xd03c80b8, 0x0003225c, 
+    0x00032264, 0x0003226c, 0x00032420, 0x000323a8, 0x0003224e, 0x00032241, 0x00032247, 0x00032242, 
+    0x0003223a, 0x00032400, 0x00032248, 0xd28e007c, 0x01c02000, 0xf89960a0, 0x28010000, 0x68a0d001, 
+    0x7830e01e, 0x9440f8df, 0xd1052805, 0x46482206, 0xf0182140, 0xb940fa8e, 0x28047830, 0x2205d107, 
+    0x21204648, 0xfa85f018, 0x2001b108, 0x2000e000, 0xf88868a1, 0xea417000, 0xf0401040, 0x60a00040, 
+    0x60a00200, 0xe92de773, 0x46044ff8, 0x4dff8e80, 0x1b1df240, 0x7f80f5b0, 0xdc1bd07e, 0xd03828d3, 
+    0xb368dc0f, 0xd03f28a4, 0xd04728a5, 0xd17428d2, 0x22006868, 0x010cf105, 0xfe45f013, 0xd06d1d40, 
+    0x28e4e027, 0x28e5d06b, 0x28ecd023, 0x28edd068, 0xe01ed163, 0xf2a04558, 0xd01a111d, 0xf111dc11, 
+    0xd016001c, 0xd07c2813, 0xd0122814, 0xd154281b, 0x220049e6, 0x310c6868, 0xfe25f013, 0xd0711d40, 
+    0x2907e007, 0x2908d06f, 0x2911d003, 0x2912d06c, 0x49ded143, 0x32fff04f, 0x310c6868, 0xfe42f013, 
+    0xd1071d01, 0xe15020a4, 0x220049d8, 0x310c6868, 0xfe38f013, 0xd03b1d41, 0xd1ea2801, 0x27004ed3, 
+    0x0000f640, 0xf9b6360c, 0x290f1000, 0xf8dfd032, 0x29138340, 0x42a0f04f, 0x0901f04f, 0x0a03f04f, 
+    0x290ad02e, 0xf9b5d1d5, 0x29011000, 0x2903d05a, 0x2902d07b, 0x2904d075, 0x2905d074, 0x2906d073, 
+    0x2907d072, 0xf000d1c5, 0x200bf930, 0x20098030, 0x1e7a4631, 0xe0048028, 0xe0ede0aa, 0xe055e040, 
+    0x48bce078, 0xf0136800, 0x1d01fdce, 0xe108d071, 0xe10a20a5, 0x4225f04f, 0xfc21f7ed, 0xe7a8802f, 
+    0xf9934bb5, 0x2b033000, 0x2b05d003, 0x2b04d001, 0x4bb2d102, 0xb143781b, 0x802f210a, 0xfc0ff7ed, 
+    0xe0a6e797, 0xe0d7e0c6, 0xf04fe0e4, 0xf7ed4220, 0xf7fffc06, 0xf898fe9f, 0xb1700000, 0x9000f8a5, 
+    0x49a2200a, 0x80302200, 0x310c6868, 0xfd9bf013, 0xf47f1d01, 0x20d2af53, 0xf8a5e0d7, 0xe7efa000, 
+    0xe0d220d3, 0xfe26f7ff, 0xf7f42002, 0xb108fd7b, 0xe000200a, 0x4995200f, 0x22008030, 0x310c6868, 
+    0xfd81f013, 0xd1071d01, 0xe0be20e4, 0x2200498f, 0x310c6868, 0xfd77f013, 0xd1b01d40, 0xe0b420e5, 
+    0xe021e003, 0xe06fe04f, 0xf000e087, 0x2002f947, 0xfd58f7f4, 0x200ab108, 0x200fe000, 0x80304983, 
+    0x68682200, 0xf013310c, 0x1d01fd5e, 0x20ecd108, 0xe08ce09b, 0x2200497d, 0x310c6868, 0xfd53f013, 
+    0xd18c1d40, 0xe09020ed, 0xfba9f7ed, 0x2201497c, 0xf8814610, 0x497b9000, 0x9000f881, 0x97002100, 
+    0xf7f368ab, 0xf898fea3, 0x28010000, 0x2004d00a, 0x496e8028, 0x68682200, 0xf013310c, 0x1d01fd34, 
+    0xe00bd003, 0xa000f8a5, 0xf240e7f3, 0xe06c1000, 0x22004966, 0x310c6868, 0xfd25f013, 0xd1ac1d40, 
+    0x1001f240, 0xf000e061, 0xf898f89b, 0x28010000, 0x2005d00a, 0x8028495d, 0x68682200, 0xf013310c, 
+    0x1d01fd12, 0xe00ad002, 0xe7f32006, 0x1014f240, 0x4956e04b, 0x68682200, 0xf013310c, 0x1d40fd04, 
+    0xf240d18b, 0xe0401015, 0xfcb7f7ff, 0xf7f42002, 0xb108fce9, 0xe000200a, 0x494c200f, 0x22008030, 
+    0x310c6868, 0xfceff013, 0xf47f1d01, 0xf240aec7, 0xe02a101c, 0xb034f8a4, 0xf7ffe604, 0x4943fc1b, 
+    0x80282007, 0x68682200, 0xf013310c, 0x1d01fcdc, 0xf240d108, 0xe0181024, 0x2200493c, 0x310c6868, 
+    0xfcd1f013, 0xd1aa1d40, 0x1025f240, 0xf240e00d, 0xe00a102e, 0x22004837, 0x310c4934, 0xf0136800, 
+    0x1d40fcc2, 0xf240d19b, 0x86a0102f, 0x2200e5da, 0xb5102101, 0x3051f2af, 0xfb00f013, 0x20032108, 
+    0xfc5ef013, 0x60484929, 0x4828bd10, 0x42a0f04f, 0xf640b510, 0xf9b00400, 0x46201000, 0xfafff7ed, 
+    0x2101f240, 0xf7ed4620, 0x4827faac, 0x4a282400, 0x80c44928, 0x80448084, 0x48248004, 0x48227803, 
+    0xfe4cf7f6, 0xf44f2172, 0xf7ed0080, 0x4822fac2, 0x70042100, 0x3080f44f, 0x4010e8bd, 0xbcb4f7f4, 
+    0x4d12b5f8, 0x0600f640, 0x42a0f04f, 0xf9b54630, 0xf7ed1000, 0x10b1fad4, 0xf7ed4630, 0x4917fa82, 
+    0x4c182001, 0x70082201, 0x48154611, 0x70207800, 0x90002000, 0x68ab4610, 0xfdc8f7f3, 0x22034d12, 
+    0x21384f12, 0xe023782b, 0xd28e0040, 0x00032504, 0x00032396, 0x00032564, 0x0003227e, 0x000322e4, 
+    0x0003224d, 0x00032249, 0x000323cc, 0x00032411, 0x000323b4, 0x000323e2, 0x000323ea, 0x0003224b, 
+    0x00032242, 0x00032243, 0x00032241, 0xd003501a, 0xf0184638, 0x7823f840, 0x21072200, 0xf0184638, 
+    0x7821f83a, 0xf7ed4630, 0x7829fa2b, 0xf7ed4630, 0xe8bdfa27, 0x482540f8, 0xbdc1f7f6, 0x41f0e92d, 
+    0xffe8f008, 0x48234922, 0xfe1cf017, 0x28014c22, 0x0600f640, 0x21e2d017, 0xf7ed4630, 0x2100fa22, 
+    0xf7ed4630, 0xf242fa0d, 0x463001d0, 0xfa25f7ed, 0x28017820, 0x2100d026, 0xe8bd4818, 0xf20141f0, 
+    0xf017312d, 0x4816bfee, 0xf7fd7800, 0x4d11fcd1, 0x09c179a8, 0x70014813, 0x4f13d011, 0x42a0f04f, 
+    0xf9b74630, 0xf7ed1000, 0x4910fa4a, 0xf3c079a8, 0x70081002, 0x28017820, 0x2001d002, 0xe4d48038, 
+    0xe7fb2004, 0x7110f242, 0x0000e7d6, 0x000323c4, 0x0002e2b0, 0x000331cc, 0x00032396, 0xd03c80b8, 
+    0x00032411, 0x0003224a, 0x00032504, 0x00032242, 0x41fce92d, 0xf24148fa, 0xf04f0700, 0xf9b042c0, 
+    0x46381002, 0xfa1bf7ed, 0xf9954df6, 0x29051000, 0x2903d001, 0xf240d156, 0x463811f4, 0xf9c1f7ed, 
+    0x1111f241, 0xf7ed4638, 0xf8dff9ab, 0x260083bc, 0x1406eb08, 0x1001f994, 0x0000f994, 0xea4078e2, 
+    0xf9942101, 0x04000002, 0x6002ea40, 0x46384301, 0xf996f7ed, 0x1005f994, 0x0004f994, 0xea4079e2, 
+    0xf9942101, 0x04000006, 0x6002ea40, 0x46384301, 0xf986f7ed, 0x1009f994, 0x0008f994, 0xea407ae2, 
+    0xf9942101, 0x0400000a, 0x6002ea40, 0x46384301, 0xf976f7ed, 0x100df994, 0x000cf994, 0xea407be2, 
+    0xf9942101, 0x0400000e, 0x6002ea40, 0x46384301, 0xf966f7ed, 0xb2361c76, 0xdbb92e04, 0x463849cb, 
+    0xf95ef7ed, 0x200049ca, 0x46032201, 0x46117008, 0x46109000, 0xfcbaf7f3, 0xf6404cc6, 0x46400800, 
+    0xf7f47821, 0xf242fb81, 0x46310680, 0x46380637, 0xf963f7ed, 0x1000f995, 0xd0122902, 0x48beb1a1, 
+    0xd00b2903, 0xd0042905, 0xd1492903, 0x28007800, 0x2905d146, 0x2903d030, 0xe03ad035, 0x2a017802, 
+    0x2007d1f4, 0xfb9ef003, 0x46407821, 0xfb5cf7f4, 0x46384631, 0xf941f7ed, 0x1000f995, 0x29034caf, 
+    0x48afd00e, 0x28116800, 0x7820d80a, 0xd1072801, 0xf8ad2047, 0x48ab0000, 0x46686802, 0xfd92f011, 
+    0x28007820, 0xf7fcd11c, 0x48a7fb7e, 0x0000f990, 0x41fce8bd, 0xb8e5f7fc, 0xf8ad204d, 0x46680000, 
+    0xff7bf011, 0x204ae005, 0x0000f8ad, 0xf0114668, 0x2007fb9e, 0xfb66f003, 0x46407821, 0xfb24f7f4, 
+    0x81fce8bd, 0x4ff8e92d, 0xf04f4998, 0x4f8d0800, 0xf8812001, 0x498e8000, 0xf9977008, 0xb1580000, 
+    0x4c932140, 0xf04f4d93, 0xf64b7680, 0x802139ba, 0x29047829, 0xe012d003, 0x2100f240, 0xb328e7f1, 
+    0xf2402010, 0x802011f4, 0xf7ed4630, 0x4649f8da, 0xf7ed4630, 0x497df8c5, 0xf7ed4630, 0xf995f8c1, 
+    0x28050000, 0x2803d001, 0x7838d110, 0x2020b170, 0x11f4f240, 0x46308020, 0xf8c3f7ed, 0x46304649, 
+    0xf8aef7ed, 0x46304971, 0xf8aaf7ed, 0x7800487a, 0xd1012802, 0x802001c0, 0xa1c4f8df, 0x0000f8da, 
+    0xd8022810, 0xf7f42000, 0x2201ff3d, 0x8000f8cd, 0x46112300, 0xf7f34610, 0x2101fbf9, 0xf7f52000, 
+    0x7838fbed, 0x200fb910, 0xfbd5f7f3, 0x0b80f242, 0x4000f04f, 0xf7ed4659, 0xf8dff8a0, 0x4c67817c, 
+    0xf7f42002, 0x4605fa69, 0x0000f997, 0xd0432805, 0xd1022803, 0x0000f898, 0x2000b3e8, 0xfaa7f008, 
+    0xb1f07838, 0x11f4f240, 0xf7ed4630, 0xf64cf87a, 0x463041cc, 0xf864f7ed, 0x46307a61, 0xf860f7ed, 
+    0x46307a21, 0xf85cf7ed, 0x463079e1, 0xf858f7ed, 0x46304946, 0xf854f7ed, 0x4000f04f, 0xf7ed4659, 
+    0x79e0f86c, 0xd1cb2892, 0xf7f42002, 0x7a22fa35, 0xf8df1a28, 0x7a6190ec, 0x0203f002, 0xea414d48, 
+    0xf8d92102, 0x1a802004, 0x3010eba1, 0x20008028, 0xfed8f7f4, 0xe7ffe00a, 0xf0082001, 0xe7bffae0, 
+    0xf0082000, 0x8828fadc, 0x80281e40, 0x28018828, 0xf04fd8f6, 0x465c4500, 0x46284659, 0xf83df7ed, 
+    0x0000f8da, 0xd8032811, 0xf00a2003, 0xe002fe8d, 0xf00a2004, 0x46a3fe8b, 0x46aa4621, 0xf7ed4628, 
+    0x2001f82c, 0xfb57f7f3, 0x0000f997, 0xd0042805, 0xd1172803, 0x0000f898, 0x4f1bb9a0, 0x24002500, 
+    0x1605eb07, 0x46284621, 0xf00b5732, 0x1c64f846, 0x2c10b2e4, 0x1c6dd3f6, 0x2d04b2ed, 0x2003d3ef, 
+    0xf84cf00b, 0x46504659, 0xf807f7ed, 0x1002f9b9, 0x42c0f04f, 0x4ff8e8bd, 0x0000f241, 0xb83ff7ed, 
+    0x4ff8e92d, 0xf9964e07, 0xb3580000, 0x4f112420, 0x7580f04f, 0x38baf64b, 0x29047839, 0xe033d025, 
+    0x00032518, 0x00032cd4, 0x0003fea4, 0xdcba01f5, 0x0003225d, 0x0003227f, 0x00032400, 0x00032396, 
+    0x0003222c, 0x00032cf4, 0x00032283, 0x0003225b, 0x00032262, 0x0003227e, 0x000323ea, 0x000331cc, 
+    0x00032264, 0x2440e7ff, 0xb318e7d1, 0xf2402408, 0x462811f4, 0xffb5f7ec, 0x46284641, 0xffa0f7ec, 
+    0x462849f6, 0xff9cf7ec, 0x0000f997, 0xd0012805, 0xd10f2803, 0xb1687830, 0xf2402410, 0x462811f4, 
+    0xff9ff7ec, 0x46284641, 0xff8af7ec, 0x462849eb, 0xff86f7ec, 0xb3a8f8df, 0x0000f89b, 0xd1002802, 
+    0xf9962440, 0x4fe70000, 0xd07c2805, 0xd1022803, 0x28007838, 0x2000d077, 0xf9a9f008, 0x46b07830, 
+    0xb1f04ee1, 0x11f4f240, 0xf7ec4628, 0xf64cff7a, 0x462841cc, 0xff64f7ec, 0x46287a71, 0xff60f7ec, 
+    0x46287a31, 0xff5cf7ec, 0x462879f1, 0xff58f7ec, 0x462849d2, 0xff54f7ec, 0x0180f242, 0xf7ec0608, 
+    0x49d2ff6c, 0xf01748d0, 0x2801fb4d, 0x4cd0d05a, 0x0700f241, 0x682021e2, 0x60201c40, 0xf7ec4638, 
+    0x6821ff50, 0xf7ec4638, 0xf242ff3b, 0x463801d0, 0xff53f7ec, 0x11f4f240, 0xf7ec4628, 0xf64fff42, 
+    0x46282111, 0xff2cf7ec, 0x683178f0, 0x611ff360, 0xf7ec4628, 0x79f0ff25, 0xf3606871, 0x4628611f, 
+    0xff1ef7ec, 0x68b17af0, 0x611ff360, 0xf7ec4628, 0x7bf0ff17, 0xf36068f1, 0x4628611f, 0xff10f7ec, 
+    0x462849ae, 0xff0cf7ec, 0x780048b2, 0xd07d2801, 0x48b12100, 0x714cf501, 0xfcf3f017, 0x780048af, 
+    0x0007f000, 0xe009e000, 0xeb0049ad, 0xf8511000, 0x1c522020, 0x2020f841, 0x8ff8e8bd, 0xf0082001, 
+    0xe77bf99e, 0x929cf8df, 0xf3c079f0, 0xf8890140, 0xf8981000, 0xb1880000, 0x11f4f240, 0xf7ec4628, 
+    0xf64afef0, 0x462821ac, 0xfedaf7ec, 0x462879f1, 0xfed6f7ec, 0x46284991, 0xfed2f7ec, 0x0000f899, 
+    0xd1d92801, 0x9260f8df, 0x7a3246c2, 0xf0027a70, 0xea400203, 0xf8a92002, 0xf8980000, 0xb1c80000, 
+    0x11f4f240, 0xf7ec4628, 0xf64afecc, 0x462821ab, 0xfeb6f7ec, 0x46287a71, 0xfeb2f7ec, 0x46287a31, 
+    0xfeaef7ec, 0x462879f1, 0xfeaaf7ec, 0x4628497b, 0xfea6f7ec, 0x0000f8b9, 0x42a046c8, 0x2002ddac, 
+    0xf88af7f4, 0x48814601, 0x68004c82, 0x49801a43, 0x2000f9b1, 0xf1f2fbb3, 0x60211cc9, 0x43511e89, 
+    0xf8c8f7f4, 0x2001497c, 0xe0007008, 0xf8b8e0d3, 0x22010000, 0x1a408821, 0x80084978, 0x46032000, 
+    0x90004611, 0xf7f34610, 0x2101f9e1, 0xf7f52000, 0xf7f6f9d5, 0xf89afae0, 0x46540000, 0x200fb910, 
+    0xf9b9f7f3, 0x0180f242, 0xf7ec0608, 0x7820fe86, 0xb96046a1, 0x21004c6a, 0xf994200c, 0xf7f62000, 
+    0x2101fad1, 0x2000f994, 0xf7f64608, 0x2002fb11, 0xf842f7f4, 0xf9994604, 0x28050000, 0x2803d03d, 
+    0x7838d101, 0x2000b3c0, 0xf881f008, 0xf7f42002, 0x1a20f833, 0x46447a32, 0x8168f8df, 0xf0027a71, 
+    0xea410203, 0xf8d82102, 0x1a802004, 0x3010eba1, 0x11f4f240, 0x46288020, 0xfe43f7ec, 0x31bbf64b, 
+    0xf7ec4628, 0x7a71fe2d, 0xf7ec4628, 0x7a31fe29, 0xf7ec4628, 0x79f1fe25, 0xf7ec4628, 0x4937fe21, 
+    0xf7ec4628, 0xf44ffe1d, 0xf6403000, 0xf7ec0103, 0xf7fbfe28, 0xe00afdd2, 0x2001e7ff, 0xf8bff008, 
+    0x2000e7c4, 0xf8bbf008, 0x1e408820, 0x88208020, 0xd8f62801, 0x4a00f04f, 0x0480f242, 0x46554621, 
+    0xf7ec4650, 0x2004fe1a, 0xfc70f00a, 0x46284621, 0xfe13f7ec, 0xf7f32001, 0xf999f93e, 0x28050000, 
+    0x2803d003, 0x7838d116, 0x4f2fb9a0, 0x24002500, 0x1605eb07, 0x46284621, 0xf00a5732, 0x1c64fe2e, 
+    0x2c10b2e4, 0x1c6dd3f6, 0x2d04b2ed, 0x2003d3ef, 0xfe34f00a, 0x0000f89b, 0xd10b2802, 0xf6400400, 
+    0xf7ec0103, 0xf7fbfdde, 0x4820fd88, 0xfbb0f017, 0x6008491f, 0x0180f242, 0xf7ec4650, 0xf9b8fdde, 
+    0xf04f1002, 0x464442c0, 0x0000f241, 0xfe17f7ec, 0x8060200b, 0xf242e6c0, 0xe6aa7110, 0xdcba01f5, 
+    0x000323ea, 0x00032400, 0x000331cc, 0x0002e2b0, 0x000322dc, 0x00032396, 0xd03c80b8, 0x00032cf0, 
+    0x0003ab8c, 0x0003225e, 0x00032264, 0x0003226c, 0x00032420, 0x000323a8, 0x0003225d, 0x00032262, 
+    0x00032283, 0x00032518, 0x0003fea4, 0xc800012c, 0x000323ec, 0x5ff0e92d, 0x25004efb, 0x0000f996, 
+    0xd00f2805, 0xd1022803, 0x780048f8, 0x2001b150, 0xffadf007, 0x24014ff6, 0x83d8f8df, 0x28017838, 
+    0xe02ad004, 0xf0082001, 0xe7f3f81a, 0xbb207830, 0xf7f648f1, 0x48f1f862, 0x78004aef, 0xd1102803, 
+    0xf99048ef, 0xf9901000, 0xf8523002, 0xf8421021, 0xf9901023, 0xf9901001, 0xf8520003, 0xf8421021, 
+    0x49e81020, 0xf8522000, 0x428b3020, 0x2400d900, 0xb2c01c40, 0xd3f62804, 0x49e3b12c, 0xf01748e3, 
+    0x2801f941, 0x4ce2d008, 0x1c406820, 0xf3c06020, 0x28010008, 0xe106d07e, 0x24004fdc, 0x9374f8df, 
+    0x7a80f04f, 0x1bf4f240, 0xf3c079f8, 0xf8890280, 0x78312000, 0xd1162905, 0xd0142890, 0x46504659, 
+    0xfd2ff7ec, 0x21abf64a, 0xf7ec4650, 0x79f9fd19, 0xf7ec4650, 0x4621fd15, 0xf7ec4650, 0x49cefd11, 
+    0xf7ec4650, 0xf899fd0d, 0x28010000, 0x48cbd008, 0x28007800, 0x2108d002, 0x1002f8a8, 0x9ff0e8bd, 
+    0x46b17830, 0xd1152805, 0x46544659, 0xf7ec4650, 0xf64afd08, 0x462021ac, 0xfcf2f7ec, 0x46207a79, 
+    0xfceef7ec, 0x462079f9, 0xfceaf7ec, 0x462049ba, 0xfce6f7ec, 0x7a7849ba, 0xf8df4bbc, 0x0982a2f4, 
+    0x49b8700a, 0x1201f3c0, 0xb2e8f8df, 0xf3c0700a, 0x4ab50181, 0x0003f000, 0x70187011, 0x4000f89a, 
+    0xd10342a1, 0x4000f89b, 0xd06242a0, 0x1e491e40, 0xf0010780, 0x7ab90603, 0x20810f04, 0xd1002980, 
+    0x7af972b8, 0xd1002980, 0x7b3972f8, 0xd1002980, 0xe0007338, 0x7b79e078, 0xd1002980, 0xf9997378, 
+    0x28020000, 0xb328d026, 0xd1032803, 0x7800488f, 0xd01f2801, 0x42417ab8, 0xeb00489f, 0x55011006, 
+    0x7af94420, 0x70414249, 0x42497b39, 0x7b797081, 0x70c14249, 0x78184b91, 0xd02a2801, 0x25014892, 
+    0x78004992, 0x0000f88a, 0xf88b7809, 0x43081000, 0xe01ed01d, 0x46217ab8, 0xb2424240, 0xf00a4630, 
+    0x7af8fccc, 0x42401c61, 0x4630b242, 0xfcc5f00a, 0x1ca17b38, 0xb2424240, 0xf00a4630, 0x7b78fcbe, 
+    0x42401ce1, 0x4630b242, 0xfcb7f00a, 0x2001e7d2, 0x4f827018, 0x28017838, 0x4879d021, 0x78004c80, 
+    0x42887821, 0x4a77d11b, 0x78134e7e, 0x42937832, 0x4318d115, 0x1c52d007, 0x7030b2d0, 0x28042200, 
+    0x7032d304, 0x2001e00e, 0xe00b7038, 0xd1092801, 0xb2c81c49, 0x28047020, 0x7022d304, 0x2d00e002, 
+    0xaf3cf43f, 0xe7372107, 0x0500f241, 0x462821e2, 0xfc47f7ec, 0x46286821, 0xfc32f7ec, 0x01d0f242, 
+    0xf7ec4628, 0x7838fc4a, 0xd01e2801, 0x48662100, 0x312ff201, 0xfa15f017, 0x49654864, 0xf0007800, 
+    0xeb000007, 0xf8511000, 0x1c522020, 0x2020f841, 0x28007830, 0xaf12f47f, 0x280a6820, 0xaf0ef6ff, 
+    0x28017838, 0x2110d1f6, 0xf242e706, 0xe7de7110, 0xf04f4840, 0xb5f842c0, 0x1002f9b0, 0x0000f241, 
+    0xfc5df7ec, 0x25004e38, 0xb1687830, 0x0180f242, 0xf7ec0608, 0x484dfc12, 0x7800494d, 0x0007f000, 
+    0x1000eb00, 0x5020f841, 0x2001494a, 0x70084c4b, 0x70084949, 0x700d493e, 0x700d493e, 0x70084940, 
+    0x70084940, 0x0000f996, 0xd0382805, 0xd1022803, 0x78004826, 0x2000b390, 0xfa12f008, 0xb240493f, 
+    0xfb1ef7f2, 0xf0082001, 0x493cfa0b, 0x3110b240, 0xfb16f7f2, 0xf0082002, 0x4938fa03, 0x3120b240, 
+    0xfb0ef7f2, 0xf0082003, 0x4934f9fb, 0x3130b240, 0xfb06f7f2, 0x220178e0, 0x060078a1, 0x4001ea40, 
+    0xea407861, 0x78202301, 0x95004611, 0x46104303, 0xff0cf7f2, 0x4c2a7830, 0xe05fb1a0, 0xf8dfe7ff, 
+    0x2100c0a4, 0xeb0c2000, 0xeb041701, 0x5c3b1201, 0x1c405413, 0x2810b200, 0x1c49dbf9, 0x2904b2c9, 
+    0xe7d7d3f0, 0x0000e040, 0x00032cd4, 0x00032400, 0x00032396, 0x00032518, 0x000331dc, 0x00032411, 
+    0x000323b4, 0x0001a02b, 0x0002e2b0, 0x000331cc, 0x000322dc, 0x00032259, 0xdcba01f5, 0x00032269, 
+    0x00032254, 0x00032255, 0x00032256, 0x00032257, 0x00032250, 0x00032251, 0x0003fea4, 0x00032268, 
+    0x00032252, 0x00032253, 0xd03c80b8, 0x00032cf0, 0x0003ab8c, 0x0003223b, 0x00032258, 0x0003308c, 
+    0x000323ac, 0x0003523c, 0x0000f994, 0xf7f249fe, 0x4afefa97, 0x48fc2104, 0xf80af017, 0x0000f994, 
+    0x40f8e8bd, 0xbd1cf007, 0x43f0e92d, 0xf24148f8, 0xb0870900, 0x42c0f04f, 0x1002f9b0, 0xf7ec4648, 
+    0xf7f6fb8e, 0xf242fa30, 0x06cf0150, 0xf7ec4638, 0x48f0fb44, 0xf2422600, 0x78010570, 0x29030d38, 
+    0x4cedd013, 0x020cf04f, 0x29037821, 0xd0004611, 0xf7f410c0, 0x46a8fb3d, 0x463d4629, 0xf7ec4638, 
+    0x4fe6fb2c, 0xb1607838, 0x2300e00d, 0x1e5a9600, 0x210e9601, 0xfa73f7f4, 0xfc6ef7fb, 0x46384629, 
+    0xf7fbe038, 0x2001fc69, 0xe9cd9604, 0x200c0602, 0x23019000, 0x220e9605, 0x03589001, 0xf7f44611, 
+    0x4646fba7, 0x46284641, 0xfb07f7ec, 0xb9c87838, 0x2000f994, 0xd0012a04, 0xd1132a05, 0x780048d0, 
+    0x2100b980, 0xf7f62001, 0x4ccef9fa, 0x200c2100, 0x2000f994, 0xff46f7f5, 0xf9942101, 0x46082000, 
+    0xff86f7f5, 0x220c2301, 0x200e4619, 0xfc51f7f4, 0x46284631, 0xfae1f7ec, 0xf44f48c3, 0xf7f531b8, 
+    0x2800fdcf, 0xf240d010, 0x464c11f4, 0xf7ec4648, 0x49befac8, 0xf7ec4620, 0xb007fab3, 0x49bc4620, 
+    0x43f0e8bd, 0xbaacf7ec, 0xe8bdb007, 0x48b083f0, 0x42c0f04f, 0xf9b0b510, 0xf2411002, 0xf7ec0000, 
+    0x4caefafe, 0xb9087820, 0xfc22f004, 0xf8bef006, 0x28017820, 0xf004d101, 0xf7f6fc1b, 0xe8bdfa9f, 
+    0xf0044010, 0xe92dbc72, 0x4ca14ff0, 0xf04fb087, 0xf24142c0, 0xf9b40000, 0xf7ec1002, 0x4d9ffae0, 
+    0x28017828, 0x48a3d110, 0xf44f7801, 0xf7f32080, 0x2000fcab, 0xf916f7f4, 0x3000f44f, 0x0103f640, 
+    0xfa7ff7ec, 0xfa29f7fb, 0x4a00f04f, 0x0980f242, 0x46504649, 0xfa81f7ec, 0x27014897, 0xf04f260c, 
+    0x68000800, 0xd2022811, 0x28017828, 0x2301d111, 0x220d9600, 0x8010f8cd, 0x46110258, 0x7802e9cd, 
+    0x8014f8cd, 0xf7f49601, 0x4649fb03, 0xf7ec4650, 0x2101fa64, 0x46082200, 0xffb4f005, 0x46ab7828, 
+    0xf994b1f0, 0x23010000, 0x9600220d, 0x90044611, 0xe9cd9601, 0x90057002, 0xf7f40298, 0x4649fae9, 
+    0xf7ec4650, 0xf994fa4a, 0x23010000, 0x9600220e, 0x90044611, 0xe9cd9601, 0x90057002, 0xe0500358, 
+    0xfb8af7fb, 0x78014873, 0x3080f44f, 0xfc4cf7f3, 0x96002301, 0x4645220d, 0x46110298, 0x7802e9cd, 
+    0x8010f8cd, 0x8014f8cd, 0xf7f49601, 0x4649fac1, 0xf7ec4650, 0x220efa22, 0x0800f241, 0x23019600, 
+    0x7502e9cd, 0x46404611, 0x96019504, 0xf7f49505, 0x4649faaf, 0xf7ec4650, 0xf7fbfa10, 0x4858fb5d, 
+    0xb9907800, 0xb1807820, 0x20012100, 0xf907f7f6, 0x21004d54, 0xf995200c, 0xf7f52000, 0x2101fe53, 
+    0x2000f995, 0xf7f54608, 0xf994fe93, 0x220e0000, 0x23019600, 0x90044611, 0xe9cd9601, 0x90057002, 
+    0xf7f44640, 0x46c8fa85, 0x46554649, 0xf7ec4650, 0x2200f9e4, 0x46112001, 0xff34f005, 0x46284641, 
+    0xf9dbf7ec, 0x0000f89b, 0x020ef04f, 0xf04f46d9, 0x28000301, 0x0000f994, 0x46119600, 0x96019004, 
+    0x7002e9cd, 0xd0319005, 0xf7f40358, 0x4644fa61, 0x46284641, 0xf9c1f7ec, 0xf44f4833, 0xf7f53190, 
+    0xb178fcaf, 0x0600f241, 0x11f4f240, 0xf7ec4630, 0x492ef9a8, 0x1c494630, 0xf992f7ec, 0x4630492c, 
+    0xf98ef7ec, 0xf8992301, 0x220c0000, 0x200e4619, 0xfb0ff7f4, 0xf44f2100, 0xf7f31000, 0xb007fbb5, 
+    0x46284621, 0x4ff0e8bd, 0xb997f7ec, 0x0000f244, 0xe92de7cb, 0x4e165ff0, 0x42c0f04f, 0x0000f241, 
+    0x1002f9b6, 0xf9cbf7ec, 0x4900f04f, 0x0470f242, 0x46484621, 0xf981f7ec, 0xf04f4f10, 0x7838080e, 
+    0xd17c2801, 0xfb34f7f4, 0x23004814, 0xf44f2211, 0xf0163100, 0x2001ff49, 0xfff4f7f3, 0xf0164810, 
+    0x490dff37, 0xe01d6809, 0x0003308c, 0x000330cc, 0x00032518, 0x00032270, 0x0003227e, 0x00032396, 
+    0x00032cd4, 0x00032283, 0x000331dc, 0x77777771, 0xdcba01f5, 0x0003227f, 0x0003222c, 0xd1800000, 
+    0xc800012c, 0xd8012910, 0xe00049fb, 0xf8df2100, 0x46a2b3f0, 0x1a454cf9, 0x46484651, 0xf93df7ec, 
+    0xf7f32000, 0xf008ffbf, 0xb1a0f9e0, 0x4080f500, 0x10407821, 0xfce9f7f4, 0x220148f2, 0xf9b07823, 
+    0x20001000, 0xfd9bf7f4, 0xf7f32001, 0x7821ffab, 0x2080f44f, 0x2001e005, 0xffa4f7f3, 0xf44f7821, 
+    0xf7f33080, 0x2201fb31, 0x21024658, 0xfefaf016, 0xd01b2801, 0x220048e2, 0x1d002101, 0xfef2f016, 
+    0xd0132801, 0x300c48de, 0xfed2f016, 0xd8c342a8, 0xf7f32001, 0x7821ff87, 0x2080f44f, 0xe01be000, 
+    0xfb12f7f3, 0x28017838, 0xe015d00a, 0x46284dd6, 0xfec4f016, 0x0110f040, 0xf0164628, 0xe7e7fec2, 
+    0xfe98f007, 0x48d249d1, 0xfcccf016, 0xd0032801, 0x80702010, 0x9ff0e8bd, 0x8002f8a6, 0x48cde7fa, 
+    0x42c0f04f, 0x41f0e92d, 0x0400f241, 0x1002f9b0, 0xf7ec4620, 0xf242f914, 0x06ce0170, 0xf7ec4630, 
+    0x2100f8cc, 0xf7f30120, 0x4dc3fadf, 0x28017828, 0x2100d103, 0xf7f30500, 0xf242fad7, 0x46300180, 
+    0xf8bbf7ec, 0x11f4f240, 0x462046a0, 0xf8a9f7ec, 0x3137f243, 0xf7ec4640, 0x4eb8f893, 0x78314640, 
+    0xf88ef7ec, 0x46404fb6, 0x1000f997, 0xf888f7ec, 0x46404cb4, 0xf7ec6821, 0x49b3f883, 0xf7ec4640, 
+    0x7830f87f, 0xd8182805, 0x28057838, 0x6820d115, 0xd3122812, 0x200049ad, 0x80c84aae, 0x80488088, 
+    0x48ab8008, 0x780349ac, 0xf7f548a8, 0x2172fc27, 0x0080f44f, 0xf89df7ec, 0x49a8e004, 0x48a8221e, 
+    0xfe1bf7fc, 0x28007828, 0xe8bdd103, 0xf7fb41f0, 0xe8bdb9c3, 0xe92d81f0, 0x48a241f0, 0x4f982300, 
+    0x4da14c96, 0x4ea17802, 0x1000f997, 0x78202a01, 0x2a02d003, 0x2903d108, 0x2832d106, 0x7832d301, 
+    0x2201b112, 0xe000702a, 0x282d702b, 0x2904d201, 0x286ed019, 0x2905d201, 0x2000d015, 0x29017829, 
+    0x2800d001, 0x4883d0d5, 0x42c0f04f, 0x1002f9b0, 0x0000f241, 0xf883f7ec, 0xf7f32000, 0x487efec3, 
+    0xb1107800, 0x2001e009, 0xf44fe7e8, 0xf6403000, 0xf7ec0103, 0xf7faf826, 0x7828ffd0, 0xd0062801, 
+    0x0000f997, 0xd0112804, 0xd01b2805, 0x7830e021, 0x2801b130, 0x2802d004, 0x2803d002, 0xe018d003, 
+    0xfe17f7f9, 0xf7f9e015, 0xe012fdff, 0x280f7820, 0x2102d202, 0xe00a2006, 0x281e380f, 0x2102d209, 
+    0xe0042000, 0x280f7820, 0x2102d20f, 0xf7f82001, 0x2101ffdc, 0x46082200, 0xfd54f005, 0x41f0e8bd, 
+    0xf44f2100, 0xf7f32080, 0x380fba0f, 0xd3e6285f, 0xe77ee7ef, 0x4c57b538, 0x42c0f04f, 0x0000f241, 
+    0x1002f9b4, 0xf82bf7ec, 0x20004961, 0x46034a61, 0x21027008, 0x22017011, 0x90004611, 0xf7f24610, 
+    0x484dfb25, 0x7800495c, 0x1000f991, 0xd00f4308, 0x70202000, 0x3040f640, 0x48496060, 0x0000f990, 
+    0xd0072804, 0xd1022805, 0x6080f241, 0xbd386060, 0xe7ee2001, 0x5000f642, 0xe92de7f8, 0x4d3d5ff0, 
+    0x1b53f240, 0x46048e81, 0xa130f8df, 0x68ab4559, 0x1053f2a1, 0xdc4cd03d, 0x7f93f5b1, 0xdc20d058, 
+    0x1207f240, 0xf2a14291, 0xd0321007, 0xb381dc10, 0xd04e29d8, 0xd04d29d9, 0x7f83f5b1, 0x2200d14b, 
+    0xf1054618, 0xf012010c, 0x1d40f97e, 0xe09fd078, 0xd0762811, 0xd01c2812, 0xd0732819, 0xd13a281a, 
+    0xf240e096, 0x42911233, 0x1033f2a1, 0xdc11d011, 0x010cf110, 0x2905d00d, 0x2906d075, 0x290bd009, 
+    0x491cd129, 0x46182200, 0xf012310c, 0x1d40f95c, 0xe07dd06a, 0xd0682805, 0xd0792806, 0xd11a281f, 
+    0x22004914, 0x310c4618, 0xf94df012, 0xd0791d40, 0x2846e06e, 0xdc59d06c, 0xd0742829, 0x2807dc43, 
+    0x2808d072, 0x281fd064, 0x2820d06f, 0xe05fd103, 0xe06be143, 0xe0b9e073, 0x01e84800, 0x0003227f, 
+    0xc8000120, 0x0003239a, 0xd003517c, 0x0002e2b0, 0x000331cc, 0x00032518, 0x00032396, 0x00032398, 
+    0x0003227e, 0x0003222c, 0xdcba01f5, 0x000323cc, 0x00032411, 0x000323b4, 0x000323e2, 0x450f6429, 
+    0x43e187ae, 0x000322ec, 0x00032331, 0x000322ed, 0x0003225b, 0x0003223a, 0x00032cd4, 0x00032564, 
+    0xe0dbe0bd, 0x282ae0f3, 0x2831d022, 0x2832d07d, 0x2845d01e, 0x49f8d17a, 0x46182200, 0xf8f3f012, 
+    0xd0741d40, 0xe10ee014, 0xe136e128, 0xd06f2869, 0x2859dc08, 0x285ad06d, 0x2861d00a, 0x2862d06a, 
+    0xe005d164, 0xd003286a, 0xd07c2873, 0xd15d2874, 0xf04f49e9, 0x68a832ff, 0xf904f012, 0xd10a1d01, 
+    0xe23f20d8, 0xe188e135, 0xe16fe144, 0x220049e2, 0xf0124618, 0x1d41f8f7, 0x2801d04d, 0x4eded1e8, 
+    0xf2412700, 0xf9b60000, 0x290f1000, 0x4bdbd045, 0xf8df2914, 0xf04f836c, 0xf04f42c0, 0xd042090a, 
+    0xd1d5290a, 0x1002f9b5, 0xd06b2913, 0xd0772901, 0xd0762902, 0xd0752910, 0xd0742911, 0xd0732912, 
+    0xd0722903, 0xd071290e, 0xd070290f, 0x29042706, 0x2906d06e, 0x2907d06d, 0x2908d06c, 0x2909d06b, 
+    0x270bd06a, 0xd068290a, 0xd1b1290b, 0xfcc0f7fe, 0x200c8037, 0xf04f8068, 0xf8da32ff, 0x46310000, 
+    0xf881f012, 0xd0711d01, 0xe154e1e8, 0xe184e0e3, 0xe19be1d1, 0x20d9e1b8, 0xf04fe1e4, 0xf7eb4226, 
+    0x806ffece, 0xf993e794, 0x2b033000, 0x2b05d003, 0x2b04d001, 0x4bb3d102, 0xb12b781b, 0x806f210d, 
+    0xfebdf7eb, 0xe1c3e784, 0x4220f04f, 0xfeb7f7eb, 0xfe80f7ff, 0x0000f898, 0xd00e2803, 0x80682013, 
+    0x9000f8a6, 0x49a42200, 0xf01268a8, 0x1d01f84c, 0xaecbf47f, 0x1006f240, 0x200ee1b4, 0xf240e7ef, 
+    0xe1af1007, 0xfde7f7ff, 0x80682001, 0x2200499a, 0xf01268a8, 0x1d01f838, 0xf240d115, 0xe1a11018, 
+    0xe02ee016, 0xe058e043, 0xe080e06b, 0xe0abe094, 0xe0ece0d6, 0xe133e109, 0xe16fe152, 0x2200498e, 
+    0xf0124618, 0x1d40f820, 0xf240d1ac, 0xe1891019, 0xfd55f7ff, 0x80682002, 0x22004987, 0xf01268a8, 
+    0x1d01f812, 0xf240d108, 0xe17b1020, 0x4982e16d, 0x46182200, 0xf807f012, 0xd1931d40, 0x1021f240, 
+    0xf7ffe170, 0x497cfc86, 0x68a82200, 0xfffbf011, 0xd1071d01, 0x1026f240, 0x4977e164, 0x46182200, 
+    0xfff1f011, 0xd18d1d40, 0x1027f240, 0xf000e15a, 0x4971fa19, 0x68a82200, 0xffe5f011, 0xd1071d01, 
+    0x102cf240, 0x496ce14e, 0x46182200, 0xffdbf011, 0xd1b91d40, 0x102df240, 0xf7ebe144, 0xf004fe30, 
+    0x2012fa11, 0x49648068, 0x68a82200, 0xffcbf011, 0xf47f1d01, 0xf240ae6c, 0xe1331032, 0x1033f240, 
+    0xf000e130, 0x495cf9ce, 0x68a82200, 0xffbbf011, 0xd1071d01, 0x1038f240, 0x4957e124, 0x46182200, 
+    0xffb1f011, 0xd18f1d40, 0x1039f240, 0x7818e11a, 0xd1012803, 0xfb17f7ff, 0x80682004, 0x2200494e, 
+    0xf01168a8, 0x1d01ffa0, 0xae50f47f, 0x1052f240, 0xf8a4e108, 0xe4cdb034, 0xfae9f7ff, 0x8068200f, 
+    0x22004945, 0xf01168a8, 0x1d01ff8e, 0xf240d107, 0xe0f7105a, 0x22004940, 0xf0114618, 0x1d40ff84, 
+    0xf240d191, 0xe0ed105b, 0xfa3ef7ff, 0x0000f898, 0xd0092803, 0x80682003, 0x22004937, 0xf01168a8, 
+    0x1d01ff72, 0xe016d00f, 0xf7f22002, 0x4836ff46, 0xf44f7801, 0xf7f21080, 0x2000ff97, 0xfc02f7f3, 
+    0xfe0ef00a, 0xf240e684, 0xe0cb1072, 0x2200492a, 0xf0114618, 0x1d40ff58, 0xf240d1f4, 0xe0c11073, 
+    0xf946f7ff, 0x2200806f, 0x68a84923, 0xff4bf011, 0xd1071d01, 0x107cf240, 0x491fe0b4, 0x46182200, 
+    0xff41f011, 0xd1dd1d40, 0x107df240, 0xf7fee0aa, 0x2002ffb1, 0xff26f7f2, 0x200ab108, 0x200fe000, 
+    0x49158030, 0x68a82200, 0xff2df011, 0xd1071d01, 0x1084f240, 0x4910e096, 0x46182200, 0xff23f011, 
+    0xd1bf1d40, 0x1085f240, 0xf000e08c, 0x480ff8f1, 0x28017800, 0x480ed103, 0x28017800, 0x806fd01a, 
+    0x49052200, 0xf01168a8, 0x1d01ff0e, 0xae18f47f, 0x1098f240, 0x0000e076, 0x00032524, 0x0003227e, 
+    0x00032270, 0x000322e4, 0x0003227f, 0x00032268, 0x00032269, 0x80682008, 0xf240e7e2, 0xe0611099, 
+    0xf871f000, 0x780048aa, 0xd0092801, 0x80682009, 0x220049a8, 0xf01168a8, 0x1d01fee6, 0xe00ad003, 
+    0x9002f8a5, 0xf240e7f4, 0xe04b10ac, 0x220049a1, 0xf0114618, 0x1d40fed8, 0xf240d195, 0xe04110ad, 
+    0xfceef7fe, 0xf7f22002, 0xb108febd, 0xe000200a, 0x8030200f, 0x22004997, 0xf01168a8, 0x1d01fec4, 
+    0xf240d107, 0xe02d10b4, 0x22004992, 0xf0114618, 0x1d40feba, 0xf240d195, 0xe02310b5, 0xfbc2f7fe, 
+    0x2200806f, 0x68a8498b, 0xfeadf011, 0xd1071d01, 0x10bcf240, 0x4987e016, 0x46182200, 0xfea3f011, 
+    0xd1c91d40, 0x10bdf240, 0xf240e00c, 0xe00910c6, 0x22004980, 0x0000f8da, 0xfe95f011, 0xd1bb1d40, 
+    0x10c7f240, 0xe6f686a0, 0x21012200, 0xf2afb510, 0xf0116035, 0x2108fcd3, 0xf0112003, 0x4975fe31, 
+    0x6088390c, 0x4873bd10, 0x42c0f04f, 0x380cb538, 0x0400f241, 0x1002f9b0, 0xf7eb4620, 0x2104fcd0, 
+    0xf7eb4620, 0x496cfc7e, 0x78094620, 0xfe9cf7f2, 0xf0092000, 0x4869fc81, 0x0000f990, 0x2802b138, 
+    0x2803d005, 0x4866d106, 0x28017800, 0x2003d102, 0xfcb4f009, 0x0180f242, 0xf7eb0608, 0x4861fc6e, 
+    0x49612400, 0x70044d61, 0x70082001, 0x2002e00e, 0xfe38f7f2, 0xd0092801, 0x46284d5d, 0xfa2ef016, 
+    0x0140f040, 0xf0164628, 0xe006fa2c, 0x46282200, 0xf0162101, 0x2800fa37, 0x2201d1e9, 0x23009400, 
+    0x46104611, 0xff92f7f1, 0x4038e8bd, 0xbe2af006, 0xb5384850, 0x78004a51, 0x1e404d4c, 0x0103f000, 
+    0xeb02484d, 0x78001201, 0x07801e40, 0x18110f00, 0x78cb5c10, 0x7849788c, 0xea43061b, 0xea434304, 
+    0x43042401, 0x2002e00e, 0xfdfcf7f2, 0xd0092801, 0x46284d3f, 0xf9f2f016, 0x0120f040, 0xf0164628, 
+    0xe006f9f0, 0x46282200, 0xf0162101, 0x2800f9fb, 0x2001d1e9, 0x46024623, 0x90004601, 0xff56f7f1, 
+    0xb510bd38, 0xf04f4c2b, 0xf24142c0, 0x3c0c0000, 0x1002f9b4, 0xfc43f7eb, 0xfd02f007, 0x200eb110, 
+    0xbd108060, 0x80602010, 0x492e482d, 0x700a7802, 0x704a7842, 0x708a7882, 0x70c878c0, 0x4010e8bd, 
+    0xbc6af007, 0x41f0e92d, 0xf04f4c1a, 0xf24142c0, 0x3c0c0000, 0x1002f9b4, 0xfc21f7eb, 0xffa8f7fb, 
+    0xf7f32000, 0x4820fa5f, 0x0000f990, 0xd0031c40, 0x80602011, 0x81f0e8bd, 0xf2404d1c, 0x4f1c2600, 
+    0x0000f995, 0x17c11c40, 0x7191eb00, 0x0103f021, 0x70281a40, 0x78282400, 0x4631b108, 0x4639e000, 
+    0xf7fa4620, 0x1c64fd50, 0x2c04b264, 0xe7e1dbf3, 0x00032396, 0x00032524, 0x0003227f, 0x00032cd4, 
+    0x00032400, 0x00032258, 0x0003225a, 0xc800001c, 0xd003517c, 0x00032252, 0x00032253, 0x0003308c, 
+    0x000323b4, 0x000323ac, 0x0003226a, 0x0003239c, 0xfffffa00, 0xf04f48ff, 0xb5f842e0, 0x0400f242, 
+    0x1006f9b0, 0xf7eb4620, 0x2107fbca, 0xf7eb4620, 0x04a6fb78, 0x05a0f242, 0x46304629, 0xfb7df7eb, 
+    0x220048f5, 0x70024613, 0x22019200, 0x46104611, 0xfebcf7f1, 0x46304629, 0xfb6ff7eb, 0xf9944cef, 
+    0xb1222000, 0xd0082a02, 0xd0062a03, 0x2000e010, 0xf9e8f7f3, 0x220c2301, 0x2000e006, 0xf9e2f7f3, 
+    0x230148e7, 0x7800220d, 0x200e2101, 0xfcc1f7f3, 0x46304629, 0xfb51f7eb, 0xb9307820, 0x230048e1, 
+    0xf244220e, 0xf0160100, 0x49dff936, 0x70082001, 0xe92dbdf8, 0x4dd94ff8, 0x0b00f242, 0x28037828, 
+    0xf240d113, 0x465c11f4, 0xf7eb4658, 0xf243fb2a, 0x46203199, 0xfb14f7eb, 0x462049d4, 0xfb10f7eb, 
+    0x49d348d4, 0xf7f26800, 0x49cbfd45, 0xf04f2001, 0x70080800, 0xf88149d0, 0xf9958000, 0xb1580000, 
+    0x4ece2140, 0xf04f4fce, 0xf64b7480, 0x803139ba, 0x29047839, 0xe012d003, 0x2100f240, 0xb328e7f1, 
+    0xf2402010, 0x803011f4, 0xf7eb4620, 0x4649fafa, 0xf7eb4620, 0x49bdfae5, 0xf7eb4620, 0xf997fae1, 
+    0x28050000, 0x2803d001, 0x7828d110, 0x2020b170, 0x11f4f240, 0x46208030, 0xfae3f7eb, 0x46204649, 
+    0xfacef7eb, 0x462049b1, 0xfacaf7eb, 0x780048b5, 0xd1012802, 0x803001c0, 0xf8cd2201, 0x23008000, 
+    0x46104611, 0xfe22f7f1, 0xf7f32002, 0xf04ffe3b, 0xf2424a00, 0x46490990, 0xf7eb4650, 0xf7f2face, 
+    0x4e9cfa63, 0xf7f280b0, 0x7828fc2b, 0xb3504fa6, 0x11f4f240, 0xf7eb4620, 0xf64cfab4, 0x462041cc, 
+    0xfa9ef7eb, 0x46207a79, 0xfa9af7eb, 0x46207a39, 0xfa96f7eb, 0x462079f9, 0xfa92f7eb, 0x46204993, 
+    0xfa8ef7eb, 0x0180f242, 0xf7eb4650, 0x7828faa6, 0xd1082803, 0xf8f8f009, 0x2300488a, 0xf244220e, 
+    0xf0160100, 0x2005f888, 0xfdc5f7f1, 0x46504649, 0xfa93f7eb, 0xf0062001, 0x7a39fd22, 0x4c8b2301, 
+    0x7a78461a, 0x0103f001, 0xea404f89, 0x21022001, 0x46388020, 0xf86ff016, 0x46382300, 0x21022201, 
+    0xf869f016, 0x46382301, 0x46192200, 0xf863f016, 0x2001e005, 0xfd03f006, 0x1e408820, 0x88208020, 
+    0xd8f62801, 0x7800487b, 0xd00b2801, 0x7800487a, 0xd0072801, 0xd0052802, 0xf0092005, 0x7828f8b7, 
+    0xe00cb120, 0xf0092006, 0xe7f8f8af, 0xb1307830, 0x1e912201, 0xf7f22005, 0xf886fc35, 0x464c8000, 
+    0x46554649, 0xf7eb4650, 0x4869fa48, 0x22042301, 0x30aa2110, 0xf82ff016, 0x23014865, 0x03d9220f, 
+    0xf01630d4, 0xf9b6f828, 0x20001004, 0xfa94f7f2, 0x1006f9b6, 0x42e0f04f, 0xf7eb4658, 0x4621fa70, 
+    0xe8bd4628, 0xf7eb4ff8, 0xe92dba28, 0x4e4b4ff8, 0x0900f242, 0x1bf4f240, 0x28037830, 0x4659d112, 
+    0x4648464c, 0xfa0df7eb, 0x1199f241, 0xf7eb4620, 0x4946f9f7, 0xf7eb4620, 0x4846f9f3, 0x68004944, 
+    0xfc28f7f2, 0xf0062001, 0x7830fc9a, 0x7780f04f, 0xb1e84d45, 0x46384659, 0xf9f3f7eb, 0x41ccf64c, 
+    0xf7eb4638, 0x7a69f9dd, 0xf7eb4638, 0x7a29f9d9, 0xf7eb4638, 0x79e9f9d5, 0xf7eb4638, 0x4933f9d1, 
+    0xf7eb4638, 0xf242f9cd, 0x06080180, 0xf9e5f7eb, 0x4835493a, 0xfdc6f015, 0xd0292801, 0x21e24c38, 
+    0x6820464d, 0x60201c40, 0xf7eb4648, 0x6821f9ca, 0xf7eb4628, 0xf242f9b5, 0x462801d0, 0xf9cdf7eb, 
+    0x7800481f, 0xd0662801, 0x482e2100, 0x3132f201, 0xff97f015, 0x7800482c, 0x0007f000, 0x1100eb00, 
+    0xeb00482a, 0x68410081, 0x60411c49, 0x8ff8e8bd, 0x79e84c27, 0x0001f000, 0x78307020, 0x4659b180, 
+    0xf7eb4638, 0xf64af99e, 0x463821ac, 0xf988f7eb, 0x463879e9, 0xf984f7eb, 0x4638490c, 0xf980f7eb, 
+    0x28017820, 0xf996d1e2, 0xb3980000, 0xf8df2420, 0xe0318030, 0x0003252c, 0x0003225f, 0x00032cd4, 
+    0x00032396, 0xd0030416, 0x0003223d, 0xdcba01f5, 0x0066ff30, 0x000323ec, 0x0003225d, 0x00032262, 
+    0x0003227e, 0x000323ea, 0x000331cc, 0x00032264, 0xd003504c, 0x00032333, 0x00032411, 0x0002e2b0, 
+    0x000322e0, 0xd03c80b8, 0x00032cf0, 0x0003ab8c, 0x00032260, 0xe119e007, 0x1000f898, 0x3abaf64b, 
+    0xd0022904, 0x2440e00f, 0xb308e7c1, 0x46592408, 0xf7eb4638, 0x4651f946, 0xf7eb4638, 0x49fef931, 
+    0xf7eb4638, 0xf998f92d, 0x28050000, 0x2803d001, 0x7830d10e, 0x2410b160, 0x46384659, 0xf931f7eb, 
+    0x46384651, 0xf91cf7eb, 0x463849f3, 0xf918f7eb, 0x780048f2, 0xd1002802, 0xf8df2440, 0x7a2a83c4, 
+    0xf0027a68, 0xea400203, 0xf8a82002, 0x78300000, 0x4659b1c0, 0xf7eb4638, 0xf64af914, 0x463821ab, 
+    0xf8fef7eb, 0x46387a69, 0xf8faf7eb, 0x46387a29, 0xf8f6f7eb, 0x463879e9, 0xf8f2f7eb, 0x463849de, 
+    0xf8eef7eb, 0x0000f8b8, 0x42a04647, 0xaf4ef77f, 0xf7f22002, 0x4601fad1, 0xf8df48da, 0x68008370, 
+    0x49d91a43, 0x2000f9b1, 0xf1f2fbb3, 0xf8c81cc9, 0x1e891000, 0xf7f24351, 0x49d5fb0d, 0x4ad62001, 
+    0x0a00f04f, 0x70084654, 0xf88048d2, 0x8839a000, 0x0000f8b8, 0x80111a09, 0x48d0b281, 0xfeb1f015, 
+    0x94002201, 0x46112300, 0xf7f14610, 0x2002fc1f, 0xfc38f7f3, 0x4800f04f, 0x0b90f242, 0x46404659, 
+    0xf8cbf7eb, 0xf860f7f2, 0x80604cc5, 0xfa28f7f2, 0x28037830, 0xf008d108, 0x48c2ff17, 0x220e2300, 
+    0x0100f244, 0xfea7f015, 0xf7f12005, 0x4659fbe4, 0xf7eb4640, 0x2001f8b2, 0xfb41f006, 0x23017a29, 
+    0x461a7a68, 0x0103f001, 0xea404db7, 0x80382001, 0x46282102, 0xfe8ff015, 0x46282300, 0x21022201, 
+    0xfe89f015, 0x46282301, 0x46192200, 0xfe83f015, 0x2001e005, 0xfb23f006, 0x1e408838, 0x88388038, 
+    0xd8f62801, 0x780048a9, 0xd00b2801, 0x780048a8, 0xd0072801, 0xd0052802, 0xf0082005, 0x7830fed7, 
+    0xe00cb120, 0xf0082006, 0xe7f8fecf, 0xb1307820, 0x1e912201, 0xf7f22005, 0xf884fa55, 0x465da000, 
+    0x46464659, 0xf7eb4640, 0x4894f868, 0x22042301, 0x38a42110, 0xfe4ff015, 0x23014890, 0x03d9220f, 
+    0xf015387a, 0xf9b4fe48, 0x20011002, 0xf8b4f7f2, 0x1006f9b4, 0x42e0f04f, 0xf7eb4648, 0x4629f890, 
+    0xf7eb4630, 0x2006f84a, 0xe68f80e0, 0x7110f242, 0xb570e67b, 0xf0062001, 0x4986fad2, 0xf0154886, 
+    0x4e86fc21, 0xf2422801, 0xd0260500, 0x21e24c84, 0x1c406820, 0x46286020, 0xf823f7eb, 0x46286821, 
+    0xf80ef7eb, 0x01d0f242, 0xf7eb4628, 0x7830f826, 0xd0322801, 0x487b2100, 0x3131f201, 0xfdf1f015, 
+    0x78004879, 0x0007f000, 0x1100eb00, 0xeb004877, 0x68410081, 0x60411c49, 0x486fbd70, 0xf3c079c0, 
+    0x48731140, 0x48737001, 0x28017800, 0x2900d1f4, 0x4c63d0f2, 0x42e0f04f, 0xf9b44628, 0xf7eb1006, 
+    0x2106f83e, 0xf7ea4628, 0x7830ffec, 0xd0022801, 0x80e02004, 0x2005bd70, 0xf242e7fb, 0xe7ca7110, 
+    0x4ff0e92d, 0xb0874f56, 0x42e0f04f, 0x0000f242, 0x1006f9b7, 0xf823f7eb, 0xf04f4c5f, 0x4d570b01, 
+    0x78204e5e, 0x4858b1c8, 0x4a582100, 0xf0007800, 0xeb000007, 0xeb021000, 0x60410080, 0xb9087828, 
+    0xf91af7fa, 0x28027820, 0x7828d02b, 0x7831b998, 0x3080f44f, 0xf9d8f7f2, 0x7828e00d, 0xf7fab968, 
+    0x7831f90b, 0x2000f44f, 0xf9cef7f2, 0x0180f242, 0xf7ea0608, 0x7820ffb2, 0xf997b998, 0x23010001, 
+    0x220e9004, 0x46119005, 0xb002e9cd, 0x9000200c, 0x03989001, 0xf83cf7f3, 0x0190f242, 0xf7ea06c8, 
+    0x7828ff9c, 0xf99446a0, 0x43081000, 0x483cd143, 0xf7f42500, 0xf8dffa72, 0x4a39a0b8, 0x0000f89a, 
+    0xd1092803, 0x48374938, 0x3002f991, 0x0023f842, 0x1003f991, 0x0021f842, 0x24016811, 0x0024f852, 
+    0xd2014288, 0x46254601, 0xb2641c64, 0xdbf52c04, 0x3000f44f, 0x0103f640, 0xff63f7ea, 0xff0df7f9, 
+    0x21004c2a, 0xf9944608, 0xf7f42000, 0xf7f9fc01, 0x2203ffed, 0x48264607, 0x70252138, 0xfd59f015, 
+    0x9090f8df, 0xf899b130, 0x07400000, 0xf89ad54a, 0xe0410000, 0xe07fe046, 0xdcba01f5, 0x000323ea, 
+    0x00032264, 0x0003226c, 0x00032420, 0x000323a8, 0x0003225f, 0x0003225d, 0x00032262, 0xd003519a, 
+    0x0003252c, 0xd0030416, 0xd003504c, 0x00032333, 0x00032411, 0x0002e2b0, 0x000331cc, 0x00032396, 
+    0x000322e0, 0xd03c80b8, 0x00032cf0, 0x0003ab8c, 0x0003223e, 0x0003223d, 0x00032cd4, 0x0003227f, 
+    0x000331dc, 0x00029395, 0x000323b4, 0x00032283, 0xd28f007c, 0x000322b5, 0xd0032803, 0x780048fb, 
+    0xe0007020, 0xb2397025, 0xf7f91438, 0x49f8ff20, 0xf8812002, 0xf7fab000, 0xf994f91c, 0xf7f90000, 
+    0xf994fe77, 0xf7f90000, 0xf994febc, 0xf7f90000, 0x48f0ff07, 0x21382203, 0xfcebf015, 0xf899b128, 
+    0x07400000, 0xf7fad501, 0xf7faf9b7, 0x7831f835, 0x0000f242, 0xf8f8f7f2, 0x20012100, 0xfddff7f4, 
+    0x2000f994, 0x200c2100, 0xfb2cf7f4, 0xf9942101, 0x46082000, 0xfb6cf7f4, 0x0000f898, 0x28034644, 
+    0x48ddd102, 0xb1607800, 0x220c2301, 0x200e4619, 0xf82ff7f3, 0xb9207820, 0xf44f2100, 0xf7f20000, 
+    0xb007f8d3, 0x0190f242, 0xe8bd06c8, 0xf7ea4ff0, 0xe92dbeb4, 0x4dd14ff8, 0x8e804604, 0x1b0ff240, 
+    0x68ab28fe, 0xdc1bd07e, 0xd03928dd, 0xb370dc0f, 0xd04028b0, 0xd04828b1, 0xd17428dc, 0x46182200, 
+    0x010cf105, 0xf87ff011, 0xd06d1d40, 0x28eee028, 0x28efd06b, 0x28f6d024, 0x28f7d068, 0xe01fd163, 
+    0xf2a04558, 0xd01b110f, 0x28ffdc12, 0xf5b0d018, 0xd07d7f83, 0x0008f111, 0x2807d012, 0x49b7d153, 
+    0x46182200, 0xf011310c, 0x1d40f85e, 0xe007d071, 0xd06f2907, 0xd0032908, 0xd06c2911, 0xd1422912, 
+    0xf04f49ae, 0x68a832ff, 0xf011310c, 0x1d01f87b, 0x20b0d107, 0x49a9e171, 0x46182200, 0xf011310c, 
+    0x1d41f871, 0x2801d03b, 0x4fa4d1ea, 0xf2422600, 0x370c0000, 0x1000f9b7, 0xd032290f, 0xf04f2915, 
+    0xf04f0802, 0xf04f42e0, 0xf04f0901, 0xd02e0a03, 0xd1d5290a, 0x1006f9b5, 0xd0792901, 0xd0782909, 
+    0xd0772902, 0xd0762903, 0xd0752904, 0xd0742905, 0xd1c52906, 0xfa9ef7ff, 0x8038200b, 0x80e82007, 
+    0xe0041e72, 0xe0f6e0b5, 0xe078e068, 0x488ce08f, 0x68004639, 0xf807f011, 0xd06f1d01, 0x20b1e129, 
+    0xf04fe12b, 0xf7ea4227, 0x80eefe5a, 0x4b85e7a8, 0x3000f993, 0xd0032b03, 0xd0012b05, 0xd1022b04, 
+    0x781b4b81, 0x2108b143, 0xf7ea80ee, 0xe797fe48, 0xe0cee0ae, 0xe106e0df, 0x4220f04f, 0xf7ea4607, 
+    0x2105fe3e, 0xf7ea4638, 0x2101fdec, 0xf7f32000, 0x2004f923, 0xfc48f008, 0x49754874, 0xf9917800, 
+    0x43081000, 0x2000d012, 0x70684972, 0x23002201, 0xf8814610, 0x4611a000, 0xf7f19600, 0x486ef927, 
+    0x9006f8a5, 0x28027800, 0xe003d002, 0xe7eb2001, 0x8006f8a5, 0x4861210a, 0x300c2200, 0x46018001, 
+    0xf01068a8, 0x1d01ffb0, 0xaf2ef47f, 0xe0d420dc, 0xe01ee006, 0xe056e035, 0xe08de075, 0xe0cc20dd, 
+    0xfdcef7ff, 0x20094955, 0x220080e8, 0x310c68a8, 0xff99f010, 0xd1081d01, 0xe0be20ee, 0x494fe0b0, 
+    0x46182200, 0xf010310c, 0x1d40ff8e, 0x20efd18e, 0xf000e0b3, 0x4949f8c3, 0xf8a52200, 0x68a88006, 
+    0xf010310c, 0x1d01ff80, 0x20f6d107, 0x4943e0a5, 0x46182200, 0xf010310c, 0x1d40ff76, 0x20f7d187, 
+    0xf7eae09b, 0x4945fdcc, 0x23002201, 0xf8814610, 0x46119000, 0xf7f19600, 0x4938f8c9, 0xf8a52200, 
+    0x68a8a006, 0xf010310c, 0x1d01ff5e, 0x20fed107, 0x4932e083, 0x46182200, 0xf010310c, 0x1d40ff54, 
+    0x20ffd1c4, 0xf7ffe079, 0x2002fd24, 0xff3af7f1, 0x200ab108, 0x200fe000, 0x80384928, 0x68a82200, 
+    0xf010310c, 0x1d01ff40, 0xf240d108, 0xe0641006, 0x22004922, 0x310c4618, 0xff35f010, 0xd1a51d40, 
+    0x1007f240, 0xf7ffe059, 0x2002fb20, 0xff1af7f1, 0x200ab108, 0x200fe000, 0x80384918, 0x68a82200, 
+    0xf010310c, 0x1d01ff20, 0xaebff47f, 0x100ef240, 0xf8a4e043, 0xe4e8b034, 0xf9ebf7ff, 0x2006490f, 
+    0x220080e8, 0x310c68a8, 0xff0df010, 0xd1081d01, 0x1016f240, 0x4909e031, 0x46182200, 0xf010310c, 
+    0x1d40ff02, 0xf240d18a, 0xe0261017, 0x000324b9, 0x00032281, 0xd28f007c, 0x00032400, 0x0003252c, 
+    0x00032564, 0x0003227e, 0x000322e4, 0x00032396, 0x00032cd4, 0x0003223a, 0x000323ea, 0x0003223d, 
+    0x1020f240, 0x4827e009, 0x49252200, 0xf0106800, 0x1d40feda, 0xf240d184, 0x86a01021, 0x2200e4a5, 
+    0xb5102101, 0x3095f2af, 0xfd18f010, 0x20022108, 0xfe76f010, 0x390c491a, 0xbd106088, 0xb510481a, 
+    0xb3307800, 0x78004819, 0x4819bb18, 0x28037800, 0x4818d01f, 0x28037800, 0x4817d102, 0xb1c07800, 
+    0xf04f480f, 0x380c42e0, 0x1006f9b0, 0x0000f242, 0xfd05f7ea, 0xf7f22000, 0xf7f5fb45, 0xf7f4f9e9, 
+    0x2001fe03, 0xfb3ef7f2, 0xf44f2100, 0xf7f11000, 0xf242fecb, 0xe8bd0190, 0x06c84010, 0xbcadf7ea, 
+    0x00032538, 0x00032564, 0x000322ee, 0x00032cd4, 0x00032411, 0x0003227e, 0x00032331, 0x47f0e92d, 
+    0x0900f244, 0x4648210a, 0xfc8bf7ea, 0x23074cfd, 0xf24f220c, 0x46200100, 0xfa66f015, 0xf6402307, 
+    0x22087100, 0xf0154620, 0x48f7fa5f, 0xf0152104, 0x4ef6fa58, 0x4df62400, 0xb3807830, 0xb9807828, 
+    0x20012100, 0xfb7bf7f4, 0x21004ff2, 0xf997200c, 0xf7f42000, 0x2101f8c7, 0x2000f997, 0xf7f44608, 
+    0x4fedf907, 0x28017838, 0x2401d100, 0x11f4f240, 0x7880f04f, 0xf7ea4640, 0xf249fc54, 0x46402122, 
+    0xfc3ef7ea, 0x1000f997, 0xf7ea4640, 0x4621fc39, 0xf7ea4640, 0x49e1fc35, 0xf7ea4640, 0x49e0fc31, 
+    0x7809200d, 0xd1032905, 0x780949de, 0x200fb901, 0x780949dd, 0xd1002901, 0x78311c64, 0xd1032905, 
+    0xb1997829, 0xd0182901, 0x23011902, 0x000ef104, 0xf7f24619, 0xf242fd9e, 0x06c801b0, 0xfc2df7ea, 
+    0xe8bd4648, 0x210b47f0, 0xbc1bf7ea, 0x23011902, 0x46191c92, 0x0010f104, 0x1902e7eb, 0x1c522301, 
+    0xf1044619, 0xe7e4000f, 0x5ff0e92d, 0x46044ec7, 0xf5b08e80, 0x68737fc1, 0xdc12d07e, 0xd07c28e6, 
+    0xb318dc05, 0xd02c288c, 0xd177288d, 0x28e7e033, 0xf5b0d01c, 0xd0727fa3, 0x7080f5a0, 0xd16d3847, 
+    0xf5b0e014, 0xd06b7fc8, 0xf5a0dc08, 0x38837080, 0x2805d00c, 0x2806d065, 0xe007d160, 0x7080f5a0, 
+    0xd0033891, 0xd07d280d, 0xd157280e, 0xf04f49af, 0x687032ff, 0xf0103108, 0x1d01fdf5, 0x208cd107, 
+    0x49aae24f, 0x46182200, 0xf0103108, 0x1d41fdeb, 0x2801d028, 0x4fa5d1ea, 0x0a00f244, 0x0800f04f, 
+    0xf9b73708, 0x290f1000, 0x4da1d01e, 0xf04f2916, 0xd0214900, 0x1000f9b6, 0xd07d2901, 0xd1d52902, 
+    0x464a0388, 0xfbfbf7ea, 0xff18f7ff, 0x8038200b, 0xf04f4898, 0x463932ff, 0xf0106800, 0x1d01fd94, 
+    0xe21ad06b, 0xe21c208d, 0x4228f04f, 0xf7ea4650, 0xf8a6fbe6, 0xe7b98000, 0xb224f8df, 0x0000f99b, 
+    0xd0122803, 0xd0102805, 0xd00e2804, 0x464a2103, 0xf8a64650, 0xe0058000, 0xe05ce1b3, 0xe148e202, 
+    0xe1cbe1e8, 0xfbcbf7ea, 0xf04fe7a0, 0x46574220, 0xf7ea4650, 0x2109fbc4, 0xf7ea4638, 0xf242fb72, 
+    0x464801b0, 0xfb79f7ea, 0x78004877, 0xd01a2801, 0x28017828, 0x2802d017, 0x2005d015, 0xf9c4f008, 
+    0xe0004875, 0x7800e1d3, 0xd00e2801, 0x8000f8a6, 0x496e200a, 0x31082200, 0x68708008, 0xfd43f010, 
+    0xd0261d01, 0x2006e02d, 0x2301e7e8, 0x220a486b, 0xf0150299, 0x2000f940, 0xf9d4f7f2, 0x68004868, 
+    0xd8032811, 0x46382100, 0xfd5ef7f1, 0x1000f89b, 0x29042008, 0xe001d106, 0xe1a5e017, 0x29017829, 
+    0x2010d100, 0x2101782a, 0xf9c0f7f9, 0x80302001, 0x20e6e7ce, 0x4955e1a5, 0x46182200, 0xf0103108, 
+    0x1d40fd12, 0x20e7d187, 0xf242e19b, 0x06c801b0, 0xfb23f7ea, 0xf8df46c1, 0x4853814c, 0x9000f888, 
+    0xf2427801, 0xf7f10000, 0x484cfd2f, 0x21202205, 0xf015300a, 0xb2c0f90e, 0x0000f888, 0xd0702801, 
+    0x22054846, 0x300a2120, 0xf903f015, 0xf888b2c0, 0x78290000, 0x290346ab, 0x2801d117, 0xd0144645, 
+    0xf641483e, 0x220071ff, 0x30ba460b, 0xf8e3f015, 0x7801483d, 0x0000f248, 0xfd06f7f1, 0x22054837, 
+    0x300a2120, 0xf8e5f015, 0x482f7028, 0x28017800, 0xf898d004, 0x28010000, 0xe020d070, 0x48332500, 
+    0x22002310, 0xf01521ff, 0x4830f8c6, 0x23012208, 0x1e800151, 0xf8bff015, 0xf2422100, 0xf7f10000, 
+    0x4826fce3, 0x21202205, 0xf015300a, 0xb2c0f8c2, 0x0000f888, 0xd0512801, 0x2d101c6d, 0x2198dbdf, 
+    0xf7ea4650, 0x4822faae, 0xb1886800, 0xf7f22000, 0xf242f939, 0x06c801b0, 0xfaaff7ea, 0xf240480c, 
+    0xf8a63190, 0x4b1b9000, 0x1e487802, 0xfceef7f1, 0xf7f34819, 0xf89bfd82, 0x48171000, 0xd0632903, 
+    0xe02be073, 0xd180004c, 0xd0031034, 0x00032cd4, 0x00032396, 0x00032283, 0x00032d18, 0xdcba01f5, 
+    0x0003227e, 0x000322b7, 0x00032333, 0x00032540, 0x00032411, 0x00032564, 0x0003223d, 0xd0035022, 
+    0x0003222c, 0x00032267, 0x0003227f, 0xd0030482, 0x00047f70, 0xd03c80b8, 0x000331dc, 0x4200f04f, 
+    0x1000f9b6, 0xf7ea0c10, 0x4877faaa, 0xf830f015, 0x20024605, 0xfc30f7f1, 0x48741a29, 0xf0007800, 
+    0xeb000007, 0x48721200, 0x0082eb00, 0x62812200, 0x80302002, 0x6801486f, 0x60011c49, 0x8038200a, 
+    0x6870496d, 0xfc2ff010, 0xd1071d01, 0x1046f240, 0x4969e0b7, 0x46182200, 0xfc25f010, 0xf47f1d40, 
+    0xf240ae3f, 0xe0ac1047, 0xf9914964, 0xf9912000, 0xf8503002, 0xf8402022, 0xf9912023, 0xf9912001, 
+    0xf8501003, 0xf8402022, 0xe9d02021, 0xe9d03200, 0x189d1002, 0x0c00eb01, 0xf64f4465, 0xebbc5ce8, 
+    0xd9170f95, 0xd9014293, 0xe000461d, 0x42814615, 0x468cd901, 0x4684e000, 0xd9054565, 0xd9014293, 
+    0xe0044618, 0xe0024610, 0xd9004281, 0x494c4608, 0xd94d4288, 0x7800484b, 0x494bb370, 0x0000f9b1, 
+    0xda292814, 0x80081c40, 0x22004840, 0x1c407800, 0x0007f000, 0x1100eb00, 0xeb00483d, 0x68810081, 
+    0x6180f501, 0xf8a66081, 0x203f9000, 0x483f8038, 0x68004939, 0xfbc7f010, 0xd1081d01, 0x1082f240, 
+    0x483ae04f, 0x49342200, 0xf0106800, 0x1d40fbbc, 0xf240d195, 0xe0441083, 0xf7f12002, 0xb108fba3, 
+    0xe000200a, 0x8038200f, 0x2200492b, 0xf0106870, 0x1d01fbaa, 0xf240d107, 0xe0321088, 0x22004926, 
+    0xf0104618, 0x1d40fba0, 0xf240d1e2, 0xe0281089, 0xf7f12002, 0xb108fb87, 0xe000200a, 0x8038200f, 
+    0x2200491d, 0xf0106870, 0x1d01fb8e, 0xf240d107, 0xe0161090, 0x22004918, 0xf0104618, 0x1d40fb84, 
+    0xf240d1c6, 0xe00c1091, 0x109ef240, 0x4818e009, 0x49112200, 0xf0106800, 0x1d40fb76, 0xf240d1b8, 
+    0x86a0109f, 0x9ff0e8bd, 0x21012200, 0xf2afb510, 0xf0105027, 0x2108f9b3, 0xf0102003, 0x4906fb11, 
+    0x60483908, 0x0000bd10, 0xc8000128, 0x00032cf0, 0x0003ab8c, 0x00047f84, 0x00032548, 0x000323b4, 
+    0x00013880, 0x00032cd4, 0x00032cda, 0x00032d0c, 0x00032564, 0x5ffce92d, 0xf2482700, 0x210c0000, 
+    0xf94ff7ea, 0x220148fa, 0xf0142102, 0xb110ff52, 0xf7f22000, 0x4cf7fe08, 0xf7f37820, 0x7820fa00, 
+    0xf95ef005, 0xfa97f005, 0x83ccf8df, 0x0a04f640, 0x0000f898, 0xf8dfbbf0, 0xf04fb3c4, 0x4af00900, 
+    0xf89b4649, 0xf0000000, 0xeb000007, 0xeb021000, 0x22010080, 0x902cf8c0, 0xf7f32002, 0x2200f81e, 
+    0x46112001, 0xf819f7f3, 0x48e62400, 0x46212301, 0x2644eb00, 0x220048e4, 0x2544eb00, 0xe9cd4618, 
+    0xf7ef5600, 0x2100ff96, 0xf8352076, 0xfb122010, 0xf836f302, 0x1c402010, 0x287fb280, 0x3202fb12, 
+    0xd9f24411, 0xf84048d9, 0x48d91024, 0x1024f840, 0xe00048d8, 0x49d8e013, 0x2044eb00, 0xeb012200, 
+    0xe9cd2144, 0x23011000, 0x46104621, 0xff71f7ef, 0xb2641c64, 0xdbc82c04, 0x0000f898, 0x4ecfb368, 
+    0xf0144630, 0xea00febb, 0x4630040a, 0xfeb6f014, 0x0580f000, 0xf0144630, 0xf400feb1, 0x20045680, 
+    0xfee1f003, 0x46112201, 0xf0034610, 0xf8dffe2b, 0x49c49310, 0x0000f899, 0x4ac3b150, 0x0580f025, 
+    0x06927812, 0xf424d401, 0x4fc06400, 0xd81b2801, 0x78124abf, 0xd0152a01, 0xf8cbe022, 0x46499000, 
+    0x92f0f8df, 0x48bc2580, 0x016e4654, 0x1000f8c9, 0xfe87f014, 0x0000f8b9, 0x48b7b281, 0xf0143014, 
+    0xe7ccfe80, 0xd9012801, 0xe0002002, 0x70082003, 0x220049b2, 0xf7f12004, 0x200bfa85, 0xfb63f7f1, 
+    0xa2bcf8df, 0x0000f89a, 0xf899b920, 0xb1080000, 0xe0002001, 0xf7f92000, 0xf89afbbe, 0x46d11000, 
+    0x48a8b921, 0xb1087800, 0xe0002008, 0xf8982000, 0x2a052000, 0xb901d101, 0x432c2008, 0x433c4304, 
+    0xb2a04334, 0x61e0f440, 0xf0144894, 0x489efe4a, 0xf0142100, 0xf898fe46, 0xb9480000, 0x2001499b, 
+    0x499b7008, 0x499b7008, 0x20007008, 0x7008499a, 0xf7f92001, 0x4899fa41, 0x0000f990, 0xf821f7f9, 
+    0x0000f899, 0xd0112801, 0x48952100, 0xeb008800, 0xebc20240, 0xe8bd10c0, 0xeb015ffc, 0xf2a000c0, 
+    0xb28110e5, 0x1c80487d, 0xbe1bf014, 0x7110f242, 0xe92de7eb, 0x4e8b5ffc, 0x498b4604, 0x0a00f04f, 
+    0x68738e80, 0x7f8ff5b0, 0xd075680d, 0x28e2dc12, 0xdc05d073, 0x28b6b318, 0x28b7d02c, 0xe033d16e, 
+    0xd01c28e3, 0x7f89f5b0, 0xf5a0d069, 0x38137080, 0xe014d164, 0x7fd6f5b0, 0xdc08d072, 0x7080f5a0, 
+    0xd00c381f, 0xd06c2867, 0xd1572868, 0xf5a0e1d2, 0x38ad7080, 0x2821d003, 0x2822d078, 0x4971d14e, 
+    0x32fff04f, 0x31086870, 0xfa1cf010, 0xd1071d01, 0xe21820b6, 0x2200496b, 0x31084618, 0xfa12f010, 
+    0xd01f1d41, 0xd1ea2801, 0x27004d66, 0xf9b53508, 0x290f1000, 0x2917d018, 0x4210f04f, 0xf9b6d030, 
+    0xf2481000, 0xf7ea0000, 0xf9b6f82a, 0xf8df0000, 0x2801b108, 0x2802d055, 0x4851d1d1, 0x28017800, 
+    0xe1d8d075, 0xe1ee20b7, 0x4229f04f, 0x0000f248, 0xf815f7ea, 0x4a524955, 0x68088037, 0x42906812, 
+    0x1c40da01, 0x88086008, 0x4843b281, 0xf0141c80, 0x484ffd98, 0xe7b27007, 0xe028e106, 0xe0d0e1d4, 
+    0xf990482c, 0x28030000, 0x2805d00c, 0x2804d00a, 0x2103d008, 0x0000f248, 0xf7e98037, 0xe79efff0, 
+    0xe15fe192, 0x4220f04f, 0x0000f248, 0xffe7f7e9, 0x2001493c, 0x200a8030, 0x22008028, 0x31086870, 
+    0xf981f010, 0xd1081d01, 0xe1ac20e2, 0x4935e1a2, 0x46182200, 0xf0103108, 0x1d40f976, 0x20e3d1cb, 
+    0xf8dfe1a1, 0x230180d0, 0x461a2102, 0xf0144640, 0x2300fd72, 0x22014640, 0xf0142102, 0x2002fd6c, 
+    0xfa63f7f1, 0x90b0f8df, 0x482cb120, 0x28017800, 0xe0f9d07e, 0x0000f99b, 0x8020f8df, 0xb020f8df, 
+    0xd04d2805, 0xd0502802, 0xd04e2803, 0xe155e084, 0xd03d104a, 0x0003227e, 0x00032cd4, 0x00032cf0, 
+    0x0003ab8c, 0x0003c5fc, 0x0003bdfc, 0x0003306c, 0x0003307c, 0x0003d5fc, 0x0003cdfc, 0xd03c80b6, 
+    0x000322b7, 0x0003240a, 0x000322b5, 0xffff8000, 0x000323fc, 0x00032d1c, 0xd003513e, 0x0ee6b280, 
+    0x00032396, 0x00032d18, 0xd003086e, 0x00032281, 0x00032282, 0x0003229c, 0x0003229d, 0x00032283, 
+    0x00047f78, 0x00032550, 0x00032d0c, 0x00047f80, 0x00032b5c, 0xd03c8314, 0x00032cda, 0x00032369, 
+    0x0000f9b9, 0xdb042814, 0xf9b9e036, 0x28040000, 0x489eda32, 0xf2427801, 0xf7f10000, 0xf8b9f925, 
+    0x1c491000, 0x1000f8a9, 0x0000f898, 0xf0001c40, 0xeb000007, 0xeb0b1100, 0x68810081, 0x6180f501, 
+    0x80376081, 0x8028203f, 0x49912200, 0xe0004891, 0x6800e045, 0xf8d7f010, 0xd1071d01, 0x1012f240, 
+    0x498be101, 0x46282200, 0xf8cdf010, 0xf47f1d40, 0xf240aec0, 0xe0f61013, 0x68004887, 0x4888b148, 
+    0x319bf240, 0x4b858037, 0x1e487802, 0xf91ef7f1, 0xf898e6c5, 0x22000000, 0xf0001c40, 0xeb000007, 
+    0xeb0b1100, 0x68810081, 0x7100f501, 0x80376081, 0x80282009, 0x4976487b, 0xf0106800, 0x1d01f8a4, 
+    0xf240d108, 0xe0ce101e, 0x22004876, 0x68004970, 0xf899f010, 0xd1db1d40, 0x101ff240, 0xf89be0c3, 
+    0xbb880000, 0xf7f34870, 0xf8dff988, 0x220081c0, 0x0000f248, 0x1000f8d8, 0xfee1f7e9, 0xf8df2500, 
+    0x220081a8, 0x0000f248, 0x1025f858, 0xfed7f7e9, 0x20004967, 0x4b684a67, 0x0100e9cd, 0x0025f858, 
+    0xfe36f7e9, 0x48614602, 0x42826800, 0x4963d208, 0x0000f248, 0xf7e98037, 0xf04ffec2, 0xe66e0a01, 
+    0xb2ed1c6d, 0xd3da2d04, 0x0f00f1ba, 0xf8a9d1a0, 0xf89b7000, 0xb1380000, 0x68084959, 0x60081c40, 
+    0x4858b281, 0xfc3df014, 0xfd3df7f8, 0x20014d56, 0xf7f27829, 0x4955fb2c, 0x0000f995, 0x49547008, 
+    0xb1b98809, 0x22734953, 0x2201800a, 0x2200708a, 0x485170c8, 0xf0106800, 0x1d01f836, 0xf240d108, 
+    0xe0601086, 0x2200484c, 0x6800494a, 0xf82bf010, 0xd0231d40, 0xf0144849, 0x2301fc11, 0x220f4848, 
+    0xf01403d9, 0xf7ebfc28, 0x2002f99f, 0xf8fbf7f1, 0x20082100, 0xfc7ef7f3, 0xf7f32001, 0x2001fccc, 
+    0xfcabf7f3, 0x2002492a, 0x200a8030, 0x80082200, 0xf0106870, 0x1d01f808, 0xe00ad003, 0x1087f240, 
+    0xf240e031, 0xe02e10ac, 0x22004921, 0xf00f4618, 0x1d40fffa, 0xf240d193, 0xe02410ad, 0x0000f89b, 
+    0xf7f8b948, 0xf44ffeb7, 0xf6403000, 0xf7e90103, 0xf7f8fdf8, 0xf7fffda2, 0x203ffc9d, 0x48158028, 
+    0x49132200, 0xf00f6800, 0x1d01ffde, 0xf240d107, 0xe00810ce, 0x2200490e, 0xf00f4628, 0x1d40ffd4, 
+    0xf240d1d8, 0x86a010cf, 0x9ffce8bd, 0x21012200, 0xf2afb510, 0xf00f40c1, 0x2108fe11, 0xf00f2003, 
+    0x4903ff6f, 0x60483908, 0x0000bd10, 0x0003227f, 0x00032558, 0x00032d0c, 0x00047f70, 0xd03c80b8, 
+    0x00032396, 0x00032564, 0x000331dc, 0x0003236c, 0x40300000, 0xb573eab3, 0x4030ab15, 0xdead0000, 
+    0x00032d1c, 0xd0035152, 0x0003227e, 0x00032238, 0x0003233c, 0x0003fee4, 0x00032ca0, 0xd0060010, 
+    0xd003501a, 0x800849fe, 0xe92d4770, 0xf8df4ff8, 0x4604b3f4, 0xf04f8e80, 0xf8df0a00, 0x4df893e4, 
+    0x7f44f5b0, 0xf1094ef8, 0xf8db0908, 0xd07a3000, 0xf240dc7a, 0x429012c1, 0x11c1f2a0, 0xdc4ed04e, 
+    0x1273f240, 0xf2a04290, 0xd0251173, 0x28b5dc25, 0xdc11d011, 0xd0682800, 0xd06728ac, 0xd06c28ad, 
+    0xd17d28b4, 0x22006868, 0xf00f4649, 0x1d41ff8b, 0x2801d077, 0xe12dd161, 0x7fa7f5b0, 0xf5a0d072, 
+    0x384f7080, 0x2823d059, 0x49e0d1eb, 0x46182200, 0xff49f00f, 0xd0661d40, 0x292ae25d, 0xdc0fd00f, 
+    0xd07d2923, 0xd0f92924, 0xd1da2929, 0x220048d8, 0x310849d3, 0xf00f6800, 0x1d40ff36, 0xe0d5d071, 
+    0xd06f2943, 0xd06e2944, 0xd1ca294d, 0x220049cc, 0x31086868, 0xff27f00f, 0xd0751d40, 0x2981e2eb, 
+    0xdc12d073, 0xd071292f, 0x2909dc08, 0x290ad06f, 0x2929d06e, 0x292ad06d, 0xe3e8d1b3, 0xd0de2930, 
+    0xd0672963, 0xd1ac2964, 0xf240e3e1, 0x42911205, 0x1005f2a1, 0xdc0ad073, 0xd0712982, 0xd07029c9, 
+    0xd19e29ca, 0xe3fee3fe, 0xe0a9e008, 0x2801e0b8, 0x2808d068, 0x2809d067, 0xe0bbd193, 0xf2404fb5, 
+    0x429032d1, 0x31d1f2a0, 0xd028683f, 0xf8dfdc6b, 0xf2a0c2c8, 0xf2403195, 0xf8dc3295, 0xe003c000, 
+    0xe0b5e3ef, 0xe1f3e1cf, 0xd02c4290, 0xf240dc33, 0x4290327f, 0x317ff2a0, 0xdc15d011, 0x006ef111, 
+    0x282dd00d, 0x282ed073, 0x286dd009, 0x499cd18d, 0x46602200, 0xf00f3108, 0x1d40fec6, 0xe089d068, 
+    0xe225e21b, 0xe26ee268, 0xd076290d, 0xd075290e, 0xd18a2915, 0x22004899, 0x31084991, 0xf00f6800, 
+    0x1d40feb2, 0xe3f2d06b, 0xe375e272, 0xe284e2d4, 0xe2b7e28a, 0x2910e313, 0xdc15d00f, 0xd0752907, 
+    0xd0f02908, 0xd187290f, 0x2200488d, 0x31084984, 0xf00f6800, 0x1d40fe98, 0x2009d069, 0xe3fde3fd, 
+    0xe3cae362, 0xe3fbe3fb, 0xd07d2919, 0xd051291a, 0xd186293b, 0x2200497a, 0x31084638, 0xfe83f00f, 
+    0xd0721d40, 0xf240e046, 0x4291122d, 0x102df2a1, 0xdc12d06c, 0xd06a291d, 0x290ddc08, 0x290ed068, 
+    0x2915d067, 0x2916d066, 0xe3eed1a0, 0xd07d291e, 0xd07c29cf, 0xd19929d0, 0x2836e02c, 0xdc08d078, 
+    0xd0032801, 0xd074282a, 0xd18f282b, 0xe3f5e32f, 0x2837e3f5, 0x2850d0fa, 0x2851d06c, 0xe326d186, 
+    0xf8a92107, 0x495e1000, 0x68682200, 0xf00f3108, 0x1d01fe4a, 0x20acd10a, 0xe3f1e205, 0xe3f1e3f1, 
+    0x22004957, 0x31086868, 0xfe3df00f, 0xd1011d40, 0xe7f120ad, 0xf04f4952, 0x686832ff, 0xf00f3108, 
+    0x1d01fe61, 0xaed3f47f, 0xe7e520b4, 0xe3fde3fd, 0xe7e120b5, 0x2800f44f, 0x1000f9b9, 0x4220f04f, 
+    0x4640464f, 0xfc7bf7e9, 0x0000f9b7, 0xd0472807, 0xd0792806, 0xd0782805, 0xd0772870, 0xd0762871, 
+    0xd0752808, 0xe006280b, 0xe3fee3fe, 0xe3fee3fe, 0xe3fee3fe, 0xd06ce3fe, 0xd06b2809, 0xd06a2821, 
+    0xd0692822, 0xd0682823, 0xd0672820, 0x46b92874, 0x483cd1c0, 0x21042202, 0xfa0bf014, 0x48394607, 
+    0x21042202, 0xf0141d80, 0xe004fa04, 0xe3f3e3f3, 0xe3f3e3f3, 0x2800e3f3, 0x2000d051, 0x48324007, 
+    0x21012200, 0xf9f5f014, 0xea57b2c0, 0xd06a0100, 0xb117492e, 0x2a00780a, 0x2801d066, 0xe3fdd07e, 
+    0x7800482b, 0x0001f000, 0xfb19f7f2, 0x0800f241, 0x220c4828, 0xf0144641, 0xb130f9dc, 0x220c4825, 
+    0x1c804641, 0xf9d5f014, 0xf8dfb948, 0x4640808c, 0xf9a4f014, 0x4100f440, 0xf0144640, 0xf7f2f9a2, 
+    0x200bfb36, 0x46508028, 0xa000f886, 0xfdccf7f0, 0x2201491a, 0x21007008, 0xf7f22002, 0x4818faae, 
+    0xb3787800, 0xe0307831, 0xe281e098, 0xe3b1e357, 0xe3f3e3f3, 0xe3f3e3f3, 0xe3f3e3f3, 0xe3f3e3f3, 
+    0x00032560, 0x00032ca0, 0x0003227e, 0x0003fef0, 0x00032c5c, 0x00032520, 0x00032554, 0x000324f8, 
+    0x00032544, 0xd0039026, 0xd2154120, 0x00032363, 0x00032228, 0xd003e840, 0xd03c8098, 0x0003227f, 
+    0x00032368, 0xe3f4e009, 0x48fde3f4, 0x48fd7803, 0x48fd7802, 0xf7f47800, 0xf7f2fa65, 0x48fbfc91, 
+    0xb9108800, 0xf0122000, 0xf8dff9db, 0xf89883e4, 0x28010000, 0xf012d101, 0xe000f9d3, 0xf7f2e3fd, 
+    0x48f4fdaf, 0x22072300, 0xf0142180, 0x48f1f954, 0x22062301, 0xf0142140, 0x48eef94e, 0x22052301, 
+    0xf0142120, 0x48ebf948, 0x22042301, 0xf0142110, 0x48e8f942, 0x22032300, 0xf0142108, 0x48e5f93c, 
+    0x22012300, 0xf0142102, 0x2301f936, 0x220048e1, 0xf0144619, 0xf898f930, 0x28010000, 0x48ded104, 
+    0xf0308800, 0xd0090040, 0x80382006, 0x220049db, 0xf00f6868, 0x1d01fd18, 0xe009d002, 0xe7f42074, 
+    0x104ef240, 0x49d5e6c8, 0x68682200, 0xfd0bf00f, 0xf47f1d40, 0xf240ae12, 0xe6bd104f, 0x880048cb, 
+    0x48cfb1c8, 0x28017800, 0x48ced015, 0x22002173, 0xf8808001, 0x7831a002, 0x460170c1, 0x0000f8db, 
+    0xfcf1f00f, 0xf47f1d01, 0xf240ada5, 0xe6a31072, 0x1073f240, 0x200ce6a0, 0x48bf8028, 0xb9608800, 
+    0x780048c1, 0xd0082801, 0x780048c0, 0x48c0b128, 0xb9107800, 0x780048bf, 0x2201b120, 0x46102100, 
+    0xf9dbf7f2, 0xf7f82000, 0x48bbffc9, 0xf88046d4, 0x48baa000, 0x28017800, 0x48b9d011, 0xb3507800, 
+    0x216e48b8, 0x1000f8a9, 0x49ac2200, 0xf00f6800, 0x1d01fcba, 0xad81f47f, 0x109cf240, 0x48b2e073, 
+    0xf8a92166, 0x22001000, 0x680049a4, 0xfcabf00f, 0xd1081d01, 0x1096f240, 0x48abe065, 0x499f2200, 
+    0xf00f6800, 0x1d40fca0, 0xf240d176, 0xe05a1097, 0x109df240, 0x489ce057, 0x28017800, 0x4898d01b, 
+    0x28017800, 0x48a1d02b, 0x28018800, 0x48a0d03e, 0x28017800, 0x489fd037, 0x28017800, 0x489ed033, 
+    0x28017800, 0x489dd02f, 0x28017800, 0x4f8fd072, 0xb3c87838, 0x2100e0aa, 0xf7f74608, 0x2100fc05, 
+    0x3080f44f, 0xfca0f7f0, 0xf7f62000, 0xf7f9fbba, 0x4993fd7c, 0x06c22002, 0x211a8008, 0x2122e05d, 
+    0x1000f8a9, 0x2200497d, 0xf00f6868, 0x1d01fc5c, 0xf240d107, 0xe01610b6, 0x22004978, 0xf00f6868, 
+    0x1d40fc52, 0x4881d011, 0xb1a08800, 0xf8a92121, 0x49721000, 0x68682200, 0xfc45f00f, 0xf47f1d01, 
+    0xf240ad1b, 0xe24510c0, 0xf240e03c, 0xe24110b7, 0x10c1f240, 0x4876e23e, 0x28017800, 0x2123d114, 
+    0x1000f8a9, 0x22004965, 0xf00f6868, 0x1d01fc2c, 0xf240d108, 0xe22d10ca, 0x4960e023, 0x68682200, 
+    0xfc21f00f, 0xd0041d40, 0x7800486a, 0xd0032801, 0xf240e008, 0xe21d10cb, 0x5280f04f, 0x12502112, 
+    0xfa6df7e9, 0x78004864, 0xd10a2801, 0x21130702, 0xe7ffe003, 0xf04f2115, 0xf44f5280, 0xf7e92000, 
+    0xe0d4fa5e, 0x7800485f, 0x2170b1b0, 0x1000f8a9, 0x2200494a, 0xf00f6868, 0x1d01fbf6, 0xf240d107, 
+    0xe1f710ea, 0x22004945, 0xf00f6868, 0x1d40fbec, 0xf240d174, 0xe1ed10eb, 0x78004853, 0x2171b1b0, 
+    0x1000f8a9, 0x2200493d, 0xf00f6868, 0x1d01fbdc, 0xf240d107, 0xe1dd10f0, 0x22004938, 0xf00f6868, 
+    0x1d40fbd2, 0xf240d15a, 0xe1d310f1, 0xf9904838, 0x48381000, 0x43017800, 0x4b44d03b, 0xf8a92201, 
+    0x46492002, 0xc000f883, 0x4841b1e0, 0x09077800, 0xebb2d018, 0xd1011f10, 0xe0042011, 0xebb72702, 
+    0xd1021f10, 0x80482012, 0x2703e00c, 0x1f10ebb7, 0x2011d101, 0x2704e004, 0x1f10ebb7, 0x2012d102, 
+    0x701a8048, 0xf8a92005, 0x22000000, 0x6868491b, 0xfb99f00f, 0xd1071d01, 0x2024f240, 0x4917e19a, 
+    0x68682200, 0xfb8ff00f, 0xd1601d40, 0x2025f240, 0x2100e190, 0xf7f74608, 0x7838fb17, 0xd1562801, 
+    0x213a4824, 0x1000f8a9, 0x490c2200, 0xf00f6800, 0x1d01fb7a, 0xf240d146, 0xe17b2042, 0x0000e047, 
+    0x00032431, 0x00032430, 0x00032367, 0x0003233c, 0x00032362, 0xd0034228, 0x0003227c, 0x00032568, 
+    0x00032271, 0x0003fef0, 0x00032277, 0x00032278, 0x00032236, 0x000322e4, 0x00032366, 0x0003229e, 
+    0x00032270, 0x00032c5c, 0x00033020, 0x00032272, 0x00032276, 0x000323bd, 0x000323bf, 0x00032279, 
+    0x00032344, 0x00032235, 0x00032234, 0x00032411, 0x000322e5, 0x00032cac, 0x220048fc, 0x680049fa, 
+    0xfb31f00f, 0xd0101d40, 0x200149f9, 0x48f97008, 0x29017801, 0xac31f47f, 0xa000f880, 0x48f62300, 
+    0x21022201, 0xff27f013, 0xf240e4e4, 0xe1212043, 0x200d49ef, 0x48f18028, 0xa000f881, 0xb9887800, 
+    0x0002f9b7, 0xd01d2812, 0xd0272811, 0x880048ec, 0x7facf5b0, 0xf5b0d02e, 0xd02b7fa4, 0x7fb4f5b0, 
+    0xe001d028, 0xe10be049, 0x7fbcf5b0, 0x2003d022, 0x48e47030, 0xf99049e4, 0x78090000, 0xd0374308, 
+    0xe3f1e03b, 0x70302004, 0x49df48de, 0x0000f990, 0x43087809, 0x49ddd131, 0xe02b2200, 0x70302005, 
+    0x49d948d8, 0x0000f990, 0x43087809, 0x49d8d125, 0xe01f2200, 0x230048d7, 0xf241220c, 0xf0130100, 
+    0x2007feda, 0x49c88038, 0x68682200, 0xfacbf00f, 0xd1071d01, 0x208af240, 0x49c3e0cc, 0x68682200, 
+    0xfac1f00f, 0xd1081d40, 0x208bf240, 0xe202e0c2, 0x220049c9, 0xf7f12000, 0x7830ffc0, 0xfad4f7f0, 
+    0x700849c6, 0xf9962101, 0xf7f70000, 0xf7ebfa3d, 0x7830fb0d, 0xfda2f7f8, 0x680148c1, 0x60011c49, 
+    0xf7f02002, 0x49bffa89, 0x78306008, 0xfa70f7ec, 0x220048bd, 0x20026801, 0xe02de003, 0xe01ce016, 
+    0xf7f0e041, 0x48b9fa8f, 0x78312200, 0x212670c1, 0xa004f880, 0x46018001, 0x0000f8db, 0xfa83f00f, 
+    0xd1081d01, 0x20c6f240, 0xe269e084, 0x220049af, 0xf00f4618, 0x1d40fa78, 0x48a3d012, 0x28017800, 
+    0x48abd011, 0x68012200, 0xf7f02001, 0x48a9fa6b, 0x28017800, 0x2003d021, 0xe42b8028, 0xe163e0b3, 
+    0x20c7f240, 0x2120e066, 0x1000f8a9, 0x2200498e, 0xf00f6868, 0x1d01fa58, 0xf240d10a, 0xe05920ce, 
+    0xe182e17b, 0x4988e194, 0x68682200, 0xfa4bf00f, 0xd1e21d40, 0x20cff240, 0x2002e04c, 0xf7f7e7dc, 
+    0x4883fc4d, 0xf8804657, 0x2002a000, 0x48927030, 0xb9708800, 0x78004891, 0xd10a2801, 0x78004890, 
+    0x2200b938, 0x4610498f, 0xe183e001, 0xf7f1e19b, 0xf8dfff34, 0xf8988234, 0xb9200000, 0x20fe22ff, 
+    0xf7eb4611, 0x2101fa91, 0xf7f72002, 0xf898f9ad, 0xb9080000, 0xffd4f7f8, 0x21004884, 0xfe01f013, 
+    0x7830497a, 0xe00670c8, 0xe1c9e183, 0xe209e38b, 0xe1dde1d6, 0x710fe1ed, 0x800a2226, 0xfcfef7f8, 
+    0x22004972, 0x0000f8db, 0xf9fdf00f, 0xd10c1d01, 0x3010f240, 0xe1fde202, 0xe3fde2dc, 0xe3fce3e2, 
+    0x2200496a, 0xf00f4618, 0x1d40f9ee, 0xf240d185, 0xe1f33011, 0xfbf2f7f7, 0x46574855, 0xa000f880, 
+    0x70302001, 0x88004864, 0x4864b968, 0x28017800, 0x4863d109, 0xb9307800, 0xe0002200, 0x4964e360, 
+    0xf7f14610, 0x2101feda, 0xf7f74608, 0x485ef95d, 0xb9087800, 0xffdef7f8, 0x2100485c, 0xfdb1f013, 
+    0x22264952, 0x70c87830, 0x800a710f, 0xfcb6f7f8, 0x2200494e, 0x0000f8db, 0xf9b5f00f, 0xd1071d01, 
+    0x303ef240, 0x4949e3d4, 0x46182200, 0xf9abf00f, 0xd1bb1d40, 0x303ff240, 0xe006e3ca, 0xe1aee124, 
+    0xe1d5e1ba, 0xe292e291, 0xf04fe2d6, 0xf9b55280, 0x12501000, 0xfff3f7e8, 0x0000f9b5, 0x0817f04f, 
+    0xd005280a, 0x8809493c, 0x0108f031, 0xe08ed10c, 0x78004840, 0x2002b978, 0xfa87f7f0, 0x4836b158, 
+    0xf0308800, 0xd02c0008, 0x5280f04f, 0x12502119, 0xe2b4e107, 0xf003e2e1, 0x2000fff3, 0xfaf2f7f1, 
+    0x20014935, 0x60084a26, 0x68124934, 0x42906808, 0x1c40da01, 0x88086008, 0x482cb281, 0xf0133024, 
+    0x7831fd50, 0xf7f12000, 0x492dfc42, 0xf881201c, 0xf7f0a000, 0x2000fa49, 0xe2dee000, 0xfaf7f7f6, 
+    0x2002e168, 0xfa2ff7f0, 0x80282009, 0x22004825, 0x8000f8a7, 0x68004904, 0xf945f00f, 0xf47f1d01, 
+    0xf240aa7c, 0xe363307e, 0x00032568, 0x00032cac, 0x00032366, 0x000323c2, 0xd03c801c, 0x00032270, 
+    0x00032392, 0x00032236, 0x000322e4, 0x00032384, 0x00032382, 0xd28e0040, 0x00032380, 0x0003227f, 
+    0x00047f78, 0x000323ec, 0x0003241c, 0x0003fef0, 0x00032418, 0x00032396, 0x0003227c, 0x00032278, 
+    0x00032277, 0x00032386, 0x00032279, 0xd003511c, 0x00032388, 0x00032cd6, 0x00047f7c, 0x00047f80, 
+    0x00032238, 0x00032554, 0x307ff240, 0x2803e320, 0x2804d016, 0x2802d02e, 0x2808d03f, 0x2809d055, 
+    0xaf72f47f, 0xf7f02002, 0x48f9f8c8, 0xf8a72200, 0x49f68000, 0xf00f6800, 0x1d01f8e6, 0xe05dd056, 
+    0x80382010, 0x220048f3, 0x680049f0, 0xf8dbf00f, 0xd1081d01, 0x308cf240, 0x48eee2fa, 0x49eb2200, 
+    0xf00f6800, 0x1d40f8d0, 0x2004d001, 0xf240e664, 0xe2ed308d, 0x80382012, 0x220048e7, 0x680049e3, 
+    0xf8c1f00f, 0xf47f1d01, 0xf240aa0c, 0xe2df3094, 0x3095f240, 0x2005e2dc, 0x2011e64e, 0x48df8038, 
+    0x49da2200, 0xf00f6800, 0x1d01f8ae, 0xf240d108, 0xe2cd309c, 0x220048d9, 0x680049d4, 0xf8a3f00f, 
+    0xd1e81d40, 0x309df240, 0x2016e2c2, 0x48d48038, 0x49ce2200, 0xf00f6800, 0x1d01f896, 0xa9fbf47f, 
+    0x30a4f240, 0xf240e2b4, 0xe2b130a5, 0x30aef240, 0x49c6e2ae, 0x46602200, 0xf885f00f, 0xf47f1d40, 
+    0xf240ad63, 0xe2a330af, 0x1000f9b5, 0x5280f04f, 0xf7e84640, 0x48c3fed4, 0xf0308800, 0xd1120008, 
+    0xf7e8e002, 0xe54ffecc, 0x0000f9b5, 0x28042114, 0x2805d00e, 0x2806d027, 0x2807d03f, 0x2808d055, 
+    0x2809d00a, 0x2118d008, 0xf04f4640, 0xe7e85280, 0x780048b5, 0xd0062803, 0x220048b4, 0x20016801, 
+    0xf850f7f0, 0x48b2e530, 0x80392200, 0x680049a7, 0xf849f00f, 0xf47f1d01, 0xf240a9c3, 0xe26730d0, 
+    0x30d1f240, 0x2013e264, 0x48aa8038, 0x499f2200, 0xf00f6800, 0x1d01f838, 0xf240d108, 0xe25730de, 
+    0x220048a4, 0x68004999, 0xf82df00f, 0xd0011d40, 0xe5c12006, 0x30dff240, 0x489de24a, 0x80392200, 
+    0x68004992, 0xf81ff00f, 0xd1071d01, 0x30e6f240, 0x498ee23e, 0x46382200, 0xf815f00f, 0xd0011d40, 
+    0xe5a92007, 0x30e7f240, 0x2015e232, 0x48928038, 0x49862200, 0xf00f6800, 0x1d01f806, 0xf240d108, 
+    0xe22530ee, 0x2200488c, 0x68004980, 0xfffbf00e, 0xd0011d40, 0xe58f2008, 0x30eff240, 0x4887e218, 
+    0x0200f04f, 0xb1087800, 0xe0004985, 0x20014985, 0xffe8f7ef, 0xe57f200a, 0x820cf8df, 0x8028200e, 
+    0x0000f898, 0xd18d07c0, 0xf7f32101, 0x2000fc8a, 0x1000f9b8, 0x41391c47, 0xd10507c9, 0xb2c32201, 
+    0x46104611, 0xfabff7f5, 0x2804b238, 0xe4abdbf0, 0xf7f82003, 0xb240faa1, 0x28037030, 0x4873d115, 
+    0xf5b08800, 0xd0087fac, 0x7fa4f5b0, 0xf5b0d005, 0xd0027fb4, 0x7fbcf5b0, 0x2005d107, 0x486c7030, 
+    0x22022308, 0xf013213c, 0x7830fbb6, 0xffccf7ef, 0x23004968, 0x22064f68, 0x200f7008, 0x80282140, 
+    0xf0134638, 0x2300fba8, 0x22044638, 0xf0132110, 0x2300fba2, 0x22014638, 0xf0132102, 0x2300fb9c, 
+    0x21014638, 0xf013461a, 0x4f5cfb96, 0x22062301, 0x46382140, 0xfb8ff013, 0x46382300, 0x21042202, 
+    0xfb89f013, 0xf7f37830, 0x4955fb99, 0xa000f8cd, 0x780b7830, 0x780a4953, 0x78094953, 0xfe44f7eb, 
+    0xf7f82000, 0x484bfb8c, 0x46407801, 0xff9cf7ef, 0x21002700, 0xf7f14608, 0x2200f8af, 0x0300f647, 
+    0x46104611, 0xa000f8cd, 0xfbb2f7f3, 0x78014841, 0xf7ef4640, 0xf240ff89, 0x464011f4, 0xfd61f7e8, 
+    0x2200483b, 0x304221ff, 0xfb63f013, 0x46404601, 0xfd46f7e8, 0x4640493d, 0xfd42f7e8, 0xb23f1c7f, 
+    0xd01a2f40, 0x22004832, 0x304221ff, 0xfb51f013, 0xd0ce28ff, 0xf7f17830, 0x4835fe02, 0x78312200, 
+    0x212670c1, 0xa004f880, 0x46018001, 0x0000f8db, 0xff29f00e, 0xd00a1d01, 0x4f2ee011, 0xf0134638, 
+    0xf040fb0d, 0x46380104, 0xfb0bf013, 0xf240e7e2, 0xe13d40a0, 0x22004926, 0xf00e4618, 0x1d40ff14, 
+    0xacabf47f, 0x40a1f240, 0x2010e132, 0x2002e4a4, 0xfee3f7ef, 0xf7ef7830, 0x4916ff27, 0xf9967008, 
+    0xf0080000, 0xe498fddb, 0x0000e123, 0x00032568, 0x00032554, 0x000324d8, 0x000324f8, 0x000324e8, 
+    0x00032544, 0x0003227c, 0x00032270, 0x00032418, 0x00032520, 0x00032508, 0x00032534, 0x00032cd5, 
+    0x0094c5f0, 0x00b71b00, 0x00032272, 0x00032392, 0xd0060000, 0x0003227f, 0xd0034228, 0xd03c8310, 
+    0x00032307, 0x00032306, 0x00032411, 0xdcba01f5, 0x0003fef0, 0xd003517c, 0xf7ff2001, 0x211bb8df, 
+    0xf04f4647, 0x46405280, 0xfd19f7e8, 0x78004879, 0x2112b1d0, 0xf04f4638, 0xf7e85280, 0x4876fd10, 
+    0x21012200, 0xfac5f013, 0xf47f2800, 0x4f73ab80, 0x78382101, 0xff6af010, 0x78382301, 0x46192200, 
+    0xf939f011, 0xbb73f7ff, 0xff18f7f1, 0x2300486c, 0x21042202, 0xfa9ff013, 0x211ce7e1, 0xf04f4640, 
+    0xf7e85280, 0x2001fcec, 0xfb0af011, 0xf8a92006, 0x49640000, 0x68682200, 0xfe85f00e, 0xd1071d01, 
+    0x40fef240, 0x495fe0a4, 0x68682200, 0xfe7bf00e, 0xd1d71d40, 0x40fff240, 0x780ae09a, 0xd02b2a01, 
+    0x780ab117, 0xd0672a01, 0xd1cb2801, 0x28007808, 0x211fd1c8, 0xf04f4640, 0xf7e85280, 0x4852fcc0, 
+    0xb1407800, 0x78314851, 0x48517803, 0x48517802, 0xf7f37800, 0x4849fb57, 0x78012200, 0x70c1484e, 
+    0x71012101, 0x80012126, 0xf8db4601, 0xf00e0000, 0x1d01fe4a, 0xe067d060, 0x4640211d, 0x5280f04f, 
+    0xfc9df7e8, 0x2301483e, 0x21042202, 0xfa43f013, 0x2301483b, 0x21042202, 0xf0131e80, 0xf7f1fa3c, 
+    0xf7f1fd5f, 0x4838fe8d, 0xb1407800, 0x78314837, 0x48377803, 0x48377802, 0xf7f37800, 0x482ffb23, 
+    0x78012200, 0x70c14834, 0x71012101, 0x80012126, 0xf8db4601, 0xf00e0000, 0x1d01fe16, 0xf240d107, 
+    0xe0355028, 0x2200492c, 0xf00e4618, 0x1d40fe0c, 0xf240d18f, 0xe02b5029, 0x4640211e, 0x5280f04f, 
+    0xfc5df7e8, 0xf8a92006, 0x491e0000, 0x68682200, 0xfdf9f00e, 0xe0011d01, 0xe010e004, 0xf240d107, 
+    0xe0155034, 0x22004917, 0xf00e6868, 0x1d40fdec, 0xf240d1de, 0xe00b5035, 0x504ef240, 0x4916e008, 
+    0x46182200, 0xfddff00e, 0xd1d11d40, 0x504ff240, 0xe8bd86a0, 0x48118ff8, 0x21012200, 0xf00eb510, 
+    0x2108fc1d, 0xf00e2005, 0x4906fd7b, 0x60483908, 0x0000bd10, 0x000323bd, 0xd2154120, 0x00032364, 
+    0xd003902c, 0x00032568, 0x00032368, 0x00032431, 0x00032430, 0x00032367, 0x0003fef0, 0x00016a6b, 
+    0x4ff0e92d, 0x94dcf8df, 0xf8df2404, 0xb09384dc, 0x46832700, 0x0a08f10d, 0x464d2600, 0x46312301, 
+    0x46182200, 0x8900e9cd, 0xfa33f7ee, 0x00fcf8b8, 0xf100fb10, 0x00fcf8b5, 0x1100fb10, 0x00f6f8b8, 
+    0xf200fb10, 0x00f6f8b5, 0x2200fb10, 0x00f0f8b8, 0xfb104411, 0xf8b5f300, 0xfb1000f0, 0xf8b83300, 
+    0xfb1000ea, 0xf8b5fc00, 0x465500ea, 0xc000fb10, 0x44084418, 0x1106eb0a, 0x0027f841, 0xf2412100, 
+    0xf7ef0000, 0x1c76fda1, 0x2e04b276, 0x1c7fdbc5, 0x42a7b23f, 0x2700dbc0, 0xe0142100, 0xb2001c48, 
+    0x1207eb05, 0xe00b4684, 0x3021f852, 0x6020f852, 0xdd0342b3, 0x6021f842, 0x3020f842, 0xb2001c40, 
+    0xdbf142a0, 0x42a14661, 0x1c7fdbe8, 0x2f04b27f, 0xeb04dbe2, 0x200071d4, 0xeb05104a, 0xf8511100, 
+    0xf84b3022, 0x1c403020, 0x2804b240, 0xb013dbf5, 0x8ff0e8bd, 0x4ffee92d, 0xb3f0f8df, 0x20004682, 
+    0x46044689, 0x49f99002, 0xeb0a2308, 0x22812644, 0xf0134630, 0xeb09f8de, 0x49f52544, 0x46282308, 
+    0xf0132281, 0x4bf2f8d6, 0x465a2081, 0x7180f5c0, 0x7021f852, 0x7020f842, 0x1021f853, 0xf8434249, 
+    0x1c401020, 0x28ffb200, 0x2708ddf0, 0x83a4f8df, 0x49e74ae9, 0x9b0248e5, 0x8700e9cd, 0xfd08f013, 
+    0x218048e6, 0xf8d4f014, 0x4ae04be1, 0x990248e2, 0x8700e9cd, 0xfa12f013, 0x230848dc, 0x46312281, 
+    0xf8b8f013, 0x230848da, 0x46292281, 0xf8b2f013, 0xb2641c64, 0xdbb62c04, 0x8ffee8bd, 0x4bd8b57c, 
+    0x2540eb01, 0x781b4cd7, 0xeb027826, 0xf0032440, 0x2e030301, 0x2301d003, 0x22004601, 0xb2c1e017, 
+    0x4ad1b91b, 0x2a017812, 0x4ad0d008, 0x2a1b7812, 0x2802d004, 0x2803d007, 0xe005d005, 0x2801b108, 
+    0x2103d102, 0x2100e000, 0x22002301, 0x2001b249, 0x5400e9cd, 0xf94df7ee, 0xf8a58820, 0x20000100, 
+    0xf8a48020, 0xbd7c0100, 0xe92d48c2, 0xf99041f0, 0x48c11000, 0x29044fbe, 0xd0057800, 0xd00e2905, 
+    0xd2122841, 0xe0112001, 0xd90128be, 0xe00d2000, 0x200249b4, 0x29037809, 0x2005d108, 0x284be006, 
+    0x2006d201, 0x2008e002, 0x2004e000, 0xf8df4ab3, 0x2100c2a8, 0x00c0ebc0, 0x080cf06f, 0x0ec0eb02, 
+    0xeb072000, 0xe9c404c1, 0x46400000, 0xd5001a0b, 0x28001a43, 0x4242da01, 0x4602e000, 0x5023f85c, 
+    0x280e1c40, 0x6022f85e, 0x2300e9d4, 0x2306fbc5, 0x2300e9c4, 0x1c49dbea, 0xdbe12911, 0xeb072000, 
+    0x680a01c0, 0x040b8889, 0x4112ea43, 0x1020f84c, 0x28111c40, 0xf04fdbf3, 0xf8dc5100, 0x42880000, 
+    0xb1c8dc14, 0xf85c2000, 0x00522020, 0x2020f84c, 0x28111c40, 0xe7f0dbf7, 0xf85c2000, 0x10522020, 
+    0x2020f84c, 0x28111c40, 0xe001dbf7, 0x4180f04f, 0x0000f8dc, 0xdcef4288, 0xf85c2000, 0xf1011020, 
+    0xf84c5100, 0x1c401020, 0xdbf62811, 0x81f0e8bd, 0x47fce92d, 0x4c754605, 0x36fff04f, 0x0900f04f, 
+    0xa028f8dd, 0x2745eb01, 0x2245eb02, 0x46304698, 0xf837464b, 0xfb111013, 0xf832fc01, 0xfb111013, 
+    0xf844c101, 0x42811023, 0xb103dd01, 0x1c5b4608, 0x2b81b21b, 0x2800dbed, 0x2200d07e, 0x0100f44f, 
+    0x1c52e002, 0x1040b212, 0xdafa4288, 0xdd092a00, 0xf8542100, 0x41133021, 0x3021f844, 0xb2091c49, 
+    0xdbf62981, 0xf44f2100, 0xe0020280, 0xb2091c49, 0x42900040, 0x2900dbfa, 0x2000dd09, 0x2020f854, 
+    0xf844408a, 0x1c402020, 0x2881b200, 0x2100dbf6, 0xf8542040, 0x2a402021, 0xf844da01, 0x1c490021, 
+    0x2981b209, 0x4a49dbf5, 0x46302381, 0xf0134611, 0x2081ff4b, 0x7180f5c0, 0x1021f854, 0x1020f844, 
+    0xb2001c40, 0xddf528ff, 0x22814840, 0x2185eb08, 0xff20f012, 0x6180f04f, 0xf84a483d, 0x14891025, 
+    0xff86f013, 0x483b2108, 0x464b4a3b, 0x0100e9cd, 0x48364937, 0xfbacf013, 0xf04f4937, 0xe00a5200, 
+    0x2000b1f0, 0x3020f851, 0xf841005b, 0x1c403020, 0x281fb200, 0x6808dbf6, 0xddf14290, 0x4280f04f, 
+    0x42906808, 0x2000dd0c, 0x3020f851, 0xf841105b, 0x1c403020, 0xe000b200, 0x281fe00d, 0xe7efdbf4, 
+    0xf8512000, 0xf1022020, 0xf8415200, 0x1c402020, 0x281fb200, 0xe8bddbf5, 0xe92d87fc, 0xf5004ff7, 
+    0x460776c8, 0x08c8f100, 0x507ef04f, 0x68386030, 0xfcdaf015, 0x68784604, 0xf0154240, 0x4621fcd5, 
+    0xfbd4f015, 0x46046070, 0xf0156838, 0xf015fccd, 0x4689fb39, 0x46054621, 0xf0154608, 0xf015fcf1, 
+    0x4b17fb31, 0xf0152200, 0x464bf96b, 0xf015462a, 0xf014f833, 0x4682fd27, 0x24029802, 0x0b01f100, 
+    0x0000e078, 0x00035a7c, 0x0003527c, 0x00038a7c, 0x00039a7c, 0x0002e510, 0x0003627c, 0x0003647c, 
+    0x00032228, 0x00032411, 0x00032304, 0x000322ac, 0x00036a7c, 0x0003227e, 0x00032398, 0x00032578, 
+    0x3ff00000, 0xf04f2501, 0xe00e0900, 0x0025f857, 0xfc8af015, 0xf8561b61, 0xf0151021, 0x4649fcb1, 
+    0xfb1cf015, 0x46811c6d, 0x42a5b22d, 0xf857dbee, 0xf0150024, 0x4649fc79, 0xfb10f015, 0x4000f080, 
+    0xf0154651, 0x2501fb73, 0xe00d4681, 0xf8561b60, 0x46481020, 0xfc94f015, 0x1025f856, 0xfafef015, 
+    0x0025f848, 0xb22d1c6d, 0xdbef42a5, 0x46084649, 0x9024f848, 0xfc84f015, 0xfac4f015, 0x22004bfe, 
+    0xf8fef015, 0x46894605, 0xf0154650, 0x462afabb, 0xf014464b, 0xf014ffc1, 0x4682fcb5, 0x1c642001, 
+    0xf858e005, 0xf8461020, 0x1c401020, 0x42a0b200, 0xb224dbf7, 0xdba5455c, 0x24009d02, 0xe00b1cad, 
+    0x0024f856, 0xf015210f, 0xf015fdfc, 0x9901fbf1, 0x0024f841, 0xb2241c64, 0xdbf142ac, 0xe92de5cc, 
+    0x46815ffc, 0x460f48e5, 0xf46f4616, 0xf04f719a, 0x88000b00, 0xeb000440, 0x14054041, 0x2500d501, 
+    0x2defe002, 0x25efdd00, 0xa374f8df, 0x48dc2400, 0x1100f240, 0xfe6cf013, 0x1104eb04, 0x20004652, 
+    0x0181eb09, 0x0c05eb00, 0x3020f851, 0xb2001c40, 0x2811029b, 0x302cf842, 0x2108dbf4, 0x4bd248d1, 
+    0xe9cd4ad2, 0x48ce0100, 0xf0124659, 0xf06fff97, 0x48ce0809, 0x46432281, 0x2184eb07, 0xfde9f012, 
+    0x228148c9, 0x2184eb06, 0xf0124643, 0x1c64fde2, 0x2c04b264, 0xe8bddbcb, 0xe92d9ffc, 0xb0854fff, 
+    0xe9dd2500, 0xe9cd0112, 0x98050100, 0xeb002400, 0x90032045, 0xeb009806, 0x90022045, 0xeb009800, 
+    0x98082b85, 0x2a45eb00, 0xeb009801, 0x98072985, 0x2845eb00, 0x6024f85b, 0x1014f93a, 0x3024f859, 
+    0x0014f938, 0xf206fb00, 0x2203fb01, 0xfb104343, 0xfb01f000, 0xfb113316, 0x01520001, 0x10c7015e, 
+    0x46394610, 0xfd74f013, 0xf8219903, 0x46390014, 0xf0134630, 0x9902fd6d, 0x0014f821, 0xb2241c64, 
+    0xdbd72c81, 0xb26d1c6d, 0xdbbe2d04, 0x46012000, 0xeb029a05, 0x1c402240, 0x2804b240, 0xdbf78011, 
+    0x0105e9dd, 0xe8bdb009, 0xe4d34ff0, 0x4ffee92d, 0x460e4605, 0xe9dd2000, 0x9002980c, 0xf7ed2001, 
+    0x2000ff91, 0xff8ef7ed, 0xa240f8df, 0xf8df2400, 0x4f8bb238, 0x498d2308, 0xeb092281, 0xf0122044, 
+    0x4989fda8, 0x22812308, 0x2044eb08, 0xfda1f012, 0x46522081, 0xf5c0465b, 0xf8527180, 0xf842c021, 
+    0xf853c020, 0x42491021, 0x1020f843, 0xb2001c40, 0xddf028ff, 0x487b2108, 0x9b024a79, 0x0100e9cd, 
+    0x487a4979, 0xf9d4f013, 0x1ba92000, 0xf8571c49, 0x410a2020, 0x2020f847, 0xb2001c40, 0xdbf62881, 
+    0x217f4873, 0xfd94f013, 0x46212001, 0x461a2300, 0x7000e9cd, 0xfdb8f7ed, 0xb2641c64, 0xdbb92c04, 
+    0xd0042d01, 0xe8bd2007, 0xf7f14ffe, 0x2006bcc3, 0xb570e7f9, 0xf0052000, 0x4d66fe17, 0x22032300, 
+    0x46282108, 0xfda7f012, 0x78204c63, 0xd02d2801, 0x46282300, 0x21042202, 0xfd9df012, 0x46282301, 
+    0x46192200, 0xfd97f012, 0xf7f12001, 0x2301fcba, 0x2200485a, 0xf0124619, 0x4859fd8e, 0xf9904959, 
+    0x28050000, 0x780ad014, 0xf04f2804, 0xd0130101, 0xf7f02078, 0x2100fbe2, 0x1000f240, 0xf9a4f7ef, 
+    0xb1587820, 0x4070e8bd, 0xb9b3f7f0, 0xe7d02301, 0x2101780a, 0xe7ec2089, 0xe7ea208e, 0x4070e8bd, 
+    0xb969f7f0, 0x4ff0e92d, 0xb0894847, 0xc80f466d, 0x000fe88d, 0x90042000, 0xf8451e41, 0x1c401020, 
+    0x2804b240, 0x2000dbf9, 0xfdecf7ef, 0x24004f3a, 0x80f8f8df, 0x0b30f242, 0x90f4f8df, 0xf2402600, 
+    0x78382a00, 0xd0032801, 0x0000f998, 0xd0054286, 0xd0502c00, 0x46304651, 0xf8e5f7f7, 0xb2761c76, 
+    0xdbee2e04, 0xf904f7f0, 0x4a00f04f, 0x465946d9, 0xf7e74650, 0x482fff42, 0x22112300, 0x3100f44f, 
+    0xfd12f012, 0xf7ef2001, 0xa805fdbd, 0xfb68f7ff, 0xf7ef2000, 0x2000fdb7, 0xae04aa05, 0x3020f855, 
+    0x1020f852, 0xdd024299, 0xf8455434, 0x1c401020, 0x2804b240, 0x4649dbf2, 0xf7e74650, 0x1c64ff1e, 
+    0x2c04b264, 0x2000dbb8, 0x4480f04f, 0x1020f855, 0xda0042a1, 0x1c40460c, 0x2804b240, 0x46b9dbf6, 
+    0xa054f8df, 0xf8df4647, 0x25008054, 0x0000f899, 0xd0292801, 0xe02ee024, 0x3ff00000, 0x0003239a, 
+    0x0003627c, 0x0002e510, 0x00039a7c, 0x00038a7c, 0x00036480, 0xd00350e6, 0x00032396, 0xd0031012, 
+    0x0003227e, 0x0003227f, 0x0002e0b0, 0x00032283, 0xfffffd00, 0xd1800000, 0xfffffa00, 0xfffffe00, 
+    0x0000f997, 0xd0104285, 0xb1305770, 0xd0062801, 0xd0062802, 0x4649e009, 0x4651e77d, 0x49fae002, 
+    0x4641e000, 0xf7f74628, 0x1c6df85e, 0x2d04b26d, 0xf04fdbbc, 0x46594000, 0xfebff7e7, 0xf2432080, 
+    0xf7e701a0, 0xf89dfeae, 0xf99d1010, 0xf99d0013, 0xea402012, 0xf99d6101, 0x04000011, 0x2002ea40, 
+    0x20804301, 0xfe8cf7e7, 0x20809900, 0xfe88f7e7, 0x20809901, 0xfe84f7e7, 0x20809902, 0xfe80f7e7, 
+    0x20809903, 0xfe7cf7e7, 0x4620b009, 0x8ff0e8bd, 0x4edeb570, 0xb9087830, 0xf87df7f0, 0x22002101, 
+    0xf0014608, 0x2100fbdf, 0x2080f44f, 0xf89cf7ef, 0x22002101, 0xf0014608, 0x48d5fbd5, 0xb1387800, 
+    0xf0012001, 0x2101fdc7, 0x46082200, 0xfbcaf001, 0x682c4dd0, 0x20c0f424, 0x78306028, 0x49cfb9c0, 
+    0x780948cd, 0x6000f990, 0xd0232903, 0x17c81cf1, 0x7090eb01, 0x0003f020, 0xb2401a08, 0xf953f7f7, 
+    0xf7ff2001, 0xf7f0fedf, 0x4630f846, 0xf94bf7f7, 0xf7ff2001, 0xf7f0fed7, 0xf242f83e, 0x06480140, 
+    0xfe4bf7e7, 0x602c2200, 0x4070e8bd, 0x46082101, 0xbb98f001, 0x578849ba, 0xeb001c40, 0xf02272d0, 
+    0x1a800201, 0x5608b240, 0xe92de7d8, 0x20004ff0, 0xb2d4f8df, 0xf8df1e41, 0xb087a2d4, 0x0105e9cd, 
+    0x0102e9cd, 0x680448af, 0x46072000, 0x46064605, 0x4aaf9004, 0x49af4628, 0xfb20f7ff, 0x4baf48ae, 
+    0x49ac4aab, 0x46289000, 0xfbd2f7ff, 0x46592000, 0xf8514652, 0x1c403020, 0x3026f842, 0xb2001c76, 
+    0x281fb236, 0xf8dfdbf5, 0xeb058298, 0x489e1105, 0xeb082210, 0x46890181, 0xfc6ff7ff, 0xf06f2000, 
+    0xf859027e, 0xf5011020, 0xf3417180, 0x297f214f, 0x1010f824, 0x217fdd00, 0x45414690, 0x1010f824, 
+    0x4611da00, 0x1010f824, 0xb2001c40, 0xdde82810, 0x46012000, 0x2010f834, 0xb2001c40, 0xb2094411, 
+    0xdbf72811, 0xf04f8c20, 0xf8df0e10, 0x1a40923c, 0xeb09498c, 0x84201305, 0x1c05eb01, 0x2000498b, 
+    0x1105eb01, 0x0240eb04, 0x0f40ebbe, 0xb2527892, 0x541a540a, 0x2000f80c, 0x42badd02, 0x4617dd00, 
+    0xb2001c40, 0xdbed2810, 0xf7ed4628, 0x1c6dfcc4, 0x2d04b26d, 0xf7eedb8d, 0x487dfc95, 0x0000f990, 
+    0xd0042803, 0xd0062804, 0xd0092805, 0x4868e06d, 0xb1487800, 0x4877e069, 0x28967800, 0xe064d304, 
+    0x78004874, 0xd2602882, 0x78004873, 0x2500bbf0, 0x4659462e, 0x46532000, 0x2026f853, 0xb2361c76, 
+    0x5200f1a2, 0x2020f841, 0xb2001c40, 0xdbf3281f, 0xfabaf7ff, 0xeb054862, 0x22101105, 0x0781eb00, 
+    0x46394859, 0xfbe9f7ff, 0x46422000, 0x1020f857, 0x7180f501, 0x214ff341, 0xf824297f, 0xdd001010, 
+    0x4291217f, 0x1010f824, 0x4611da00, 0x1010f824, 0xb2001c40, 0xdde92810, 0x46012000, 0x2010f834, 
+    0xb2001c40, 0xb2094411, 0xe0002811, 0xdbf5e01d, 0xeb098c20, 0x1a401305, 0x8420494a, 0xeb012000, 
+    0x494a1705, 0x1105eb01, 0x0240eb04, 0x540a7892, 0x543a541a, 0xb2001c40, 0xdbf52810, 0xf7ed4628, 
+    0x1c6dfc4a, 0x2d04b26d, 0x2200dba3, 0x46112001, 0xfa88f001, 0x78004831, 0xd0062803, 0x7800483d, 
+    0xd80228fa, 0x7800483c, 0x2000b390, 0x22009002, 0x46112001, 0xfa76f001, 0x4c389a02, 0xdd762a00, 
+    0x23014837, 0xf00b9906, 0x9806faf9, 0x31c8f44f, 0x0c014348, 0xf0124620, 0xf8dffae4, 0x240080c8, 
+    0x464d4e2a, 0xeb082200, 0xeb051704, 0xeb061304, 0x5c881104, 0x549854b8, 0xb2121c52, 0xdbf82a10, 
+    0xf7ed4620, 0x1c64fc08, 0x2c04b264, 0xe053dbea, 0x4923e7ff, 0x23012044, 0x80082210, 0x46104619, 
+    0xfe57f7ef, 0x78014820, 0x2000f44f, 0xfefcf7ee, 0x9000a803, 0x2301481a, 0xa906aa02, 0xfbb9f00a, 
+    0xf7ef2000, 0xe7b2fb5f, 0xfffffc00, 0x00032396, 0x00032331, 0x00047ffc, 0x00032283, 0x00032411, 
+    0x000323b4, 0x00032224, 0x0003627c, 0x0003ddfc, 0x000339ec, 0x000331ec, 0x0003bdec, 0x0003adec, 
+    0x0003aa7c, 0x000402c4, 0x000351fc, 0x0003523c, 0x0003227e, 0x00032398, 0x000322e4, 0xd003513c, 
+    0x00032570, 0x0003308c, 0x0003227f, 0xf64fe7ff, 0x462071ff, 0xfa75f012, 0x49f84af7, 0xf7ff48f8, 
+    0x49f5fbce, 0x4af84bf7, 0xe9cd48f9, 0x49f7a100, 0xfc13f7ff, 0x780048f7, 0xf44fb938, 0xf6403000, 
+    0xf7e70103, 0xf7f6fc7e, 0x49f0fc28, 0x4bed48f0, 0xe9cd4aed, 0xe9dd0100, 0xf7ff1004, 0x2200fc57, 
+    0x46112001, 0xf9cef001, 0xe5dfb007, 0x4ff0e92d, 0xb09948ea, 0x0904f10d, 0x4ee94de7, 0xaf0e2400, 
+    0x0801f04f, 0xe889c80f, 0x4be5000f, 0x20012200, 0x8000f8cd, 0xf7edb261, 0x2000fafe, 0x0cc4eb07, 
+    0xe9cc4602, 0xf8560000, 0x1c401020, 0x3004f8dc, 0x2880b200, 0x2301fbc1, 0x2300e9cc, 0x1c64dbf3, 
+    0x2c04b2e4, 0xa816d3e1, 0xffc9f7f0, 0x46bb2400, 0x0a58f10d, 0xaf064626, 0x465046a1, 0x1014f93a, 
+    0xdd02291e, 0xf820211e, 0xf9301014, 0x29001014, 0xf820da01, 0xf93a9014, 0x48ca1014, 0x0011f830, 
+    0x0c810382, 0xce00fba2, 0xe000fb01, 0x0209fb02, 0x2100205d, 0x3e00fbac, 0xe000fb02, 0x0001fb0c, 
+    0xeb0b0d5a, 0x154301c4, 0x22c0ea42, 0x0100e9d1, 0xeb6ef011, 0x02c4eb07, 0x19864690, 0x48bac203, 
+    0x28017800, 0xf857d10c, 0xf7f10034, 0xb280f823, 0x0100f248, 0xe9c80fc2, 0x18400200, 0x0b02f825, 
+    0xf837a901, 0xf8510034, 0xf1041024, 0xb2e40401, 0x80082c04, 0x48add3b1, 0x28037800, 0x19b6d100, 
+    0xf7f14630, 0x49aaf807, 0x305db280, 0x29126809, 0x2916d001, 0x21a2d102, 0x0a004348, 0x600849a5, 
+    0xe543b019, 0x41f0e92d, 0xf7f12007, 0x2000f8d3, 0xfa2af005, 0x23004c98, 0x3cd02203, 0x46202108, 
+    0xf9b9f012, 0x78304e93, 0x489bb110, 0xb1087800, 0xe0002301, 0x46202300, 0x21042202, 0xf9abf012, 
+    0x46202301, 0x46192200, 0xf9a5f012, 0xf7f12001, 0x4c92f8c8, 0x22082301, 0x3100f240, 0xf0124620, 
+    0x2301f99a, 0x22004620, 0xf0124619, 0x2301f994, 0x2200488b, 0xf0124619, 0x488af98e, 0x78022101, 
+    0xf9b04889, 0xf7ef0000, 0xf240ffc6, 0x21001700, 0xf7ee4638, 0x2101fda9, 0x46082200, 0xf8e2f001, 
+    0x682c4d82, 0x20c0f424, 0x20016028, 0xfafaf7ed, 0x46382100, 0xfd98f7ee, 0x28017830, 0xf7efd018, 
+    0x487bfdb6, 0x22112300, 0x3100f44f, 0xf94cf012, 0xf7ef2001, 0xf242f9f7, 0x06c80130, 0xfb6df7e7, 
+    0x20012200, 0xf0014611, 0x602cf8bd, 0x81f0e8bd, 0xf7ed2000, 0xf7effad7, 0xe7e2fd4e, 0x5ff0e92d, 
+    0xfee4f7ff, 0xf04f496b, 0x48620891, 0x53aaf240, 0xf2404a70, 0x4e6855dc, 0x68007809, 0x29014f67, 
+    0xc19cf8df, 0xe19cf8df, 0x919cf8df, 0xa19cf8df, 0xb19cf8df, 0xf9924c68, 0xd0061000, 0xd0432903, 
+    0xd0272905, 0xd0752904, 0x2903e05f, 0x2905d004, 0x2904d020, 0xe058d02b, 0x7faff5b0, 0xf240dd0b, 
+    0x428841e2, 0x4608dd00, 0xeb004b5c, 0xf5a10140, 0x39ba5104, 0x287de00a, 0x207dda00, 0xeb004b58, 
+    0xebc101c0, 0xf5a11180, 0x39aa4139, 0x3000fb01, 0xe0390c00, 0x7fc3f5b0, 0x4298dd4f, 0xebc0dc4b, 
+    0xeb061140, 0xfb010181, 0x0d407000, 0xf5b0e02c, 0xdd507f9b, 0xdd0042a8, 0xf2404628, 0xfb001151, 
+    0xe0a29301, 0xe01f20fa, 0x7fa1f5b0, 0xf240db0d, 0x4288512c, 0x4608dd00, 0x21a94b42, 0x44194341, 
+    0xfb014b41, 0x0d803000, 0xeba0e00e, 0x493f1000, 0x0040eb00, 0x1000ebc0, 0x1040eb01, 0x4007f3c0, 
+    0x287b7020, 0x207bd901, 0x48207020, 0x28017800, 0x2802d070, 0x4936d06e, 0x43017809, 0x2803d06a, 
+    0xf992d068, 0x28040000, 0x2805d072, 0x2803d001, 0xe09ad06f, 0x4618e05f, 0xf240e7b1, 0xfb016151, 
+    0xfb01c100, 0xf3c0e000, 0x70205047, 0xd9dc2891, 0x8000f884, 0xe05de7d9, 0x0003edfc, 0x0003ddfc, 
+    0x0003aa7c, 0x000339ec, 0x000331ec, 0x000349ec, 0x000341ec, 0x00032396, 0xd00351bc, 0x0002e0c0, 
+    0x0003627c, 0x00032b5e, 0x000322d8, 0x00032411, 0x0003222c, 0x0003242c, 0x000322e4, 0xd0030444, 
+    0xd0031012, 0x0003227f, 0x0003239a, 0x00047ffc, 0xd1800000, 0x000322c0, 0xfffa6eca, 0x10133079, 
+    0xffe89b85, 0x1dcb8bb0, 0xfff063b3, 0x2ec83679, 0xffa22500, 0x0003227e, 0x00032398, 0x005d41c4, 
+    0x00c96ba6, 0xfff7c4ea, 0x18e997a9, 0x00a84018, 0x00032372, 0xf5b0e01c, 0xdd0b7f9b, 0xdd0042a8, 
+    0xf2404628, 0xfb001151, 0xfb039301, 0xe76aa000, 0xe025e037, 0x7185f641, 0xb301fb00, 0xfb03491a, 
+    0xf3c01000, 0x70205087, 0xf63f28fa, 0xe76caf4b, 0x0000f992, 0xd0082804, 0xf47f2805, 0x7820af78, 
+    0xd20b283c, 0xd303280c, 0x7820e006, 0xd2012819, 0xe00908c0, 0xe0073819, 0xe005380c, 0xe0031f40, 
+    0x28197820, 0x3010d300, 0xf6407020, 0x030d0100, 0xf7e74628, 0x7821fa16, 0xe8bd4628, 0xf7e75ff0, 
+    0x7820b9ff, 0x0000e7de, 0x61737224, 0x47f0e92d, 0x46894692, 0x46062200, 0x46032101, 0x46204cfe, 
+    0xffe2f011, 0x46331d25, 0x46282200, 0xf0112101, 0xf105ffdb, 0x46330804, 0x46402200, 0xf0112101, 
+    0x4633ffd3, 0x0604f108, 0x46302200, 0xf0112101, 0x2208ffcb, 0x4620464b, 0x46390157, 0xffc4f011, 
+    0x464b2208, 0x46284639, 0xffbef011, 0x464b2208, 0x46404639, 0xffb8f011, 0x464b2208, 0x46304639, 
+    0xffb2f011, 0x4653013f, 0x4639220c, 0xf0114620, 0x220cffab, 0x46394653, 0xf0114628, 0x220cffa5, 
+    0x46394653, 0xf0114640, 0x4653ff9f, 0x46304639, 0x47f0e8bd, 0xf011220c, 0xe92dbf97, 0x4ed75ff0, 
+    0xf8df2400, 0xf8df835c, 0x3680a35c, 0xf1084dd3, 0x4fd30880, 0x0a80f10a, 0x9348f8df, 0xb348f8df, 
+    0x19602140, 0xff7df011, 0x19a02140, 0xff79f011, 0x19e02140, 0xff75f011, 0xeb042140, 0xf0110008, 
+    0x2140ff70, 0x0009eb04, 0xff6bf011, 0xeb042140, 0xf011000a, 0x2140ff66, 0x000beb04, 0xff61f011, 
+    0x214048c1, 0x44203080, 0xff5bf011, 0x214048bf, 0xf0114420, 0x48bdff56, 0x30802140, 0xf0114420, 
+    0x48bbff50, 0x44202140, 0xff4bf011, 0x214048b8, 0x44203080, 0xff45f011, 0x214048b6, 0xf0114420, 
+    0x48b4ff40, 0x30802140, 0xf0114420, 0x48b2ff3a, 0x44202140, 0xff35f011, 0x214048af, 0x44203080, 
+    0xff2ff011, 0x2c201ca4, 0x4ea4d3aa, 0x4fa52400, 0x1500f240, 0x8294f8df, 0xf8df3e1c, 0x3f1c9298, 
+    0x081cf1a8, 0x091cf1a9, 0x19a04629, 0xff19f011, 0x462919e0, 0xff15f011, 0x0008eb04, 0xf0114629, 
+    0xeb04ff10, 0x46290009, 0xff0bf011, 0x2c081ca4, 0xf8dfd3ea, 0x27009244, 0xf1a94e98, 0xf1090984, 
+    0x25000804, 0x03202400, 0x2005ea40, 0x1107ea40, 0xf0114648, 0x7831fef0, 0xf7ee2040, 0x2100fb35, 
+    0xf0114640, 0x7831fee8, 0xf7ee2040, 0x1c64fb2d, 0xd3e82c04, 0x2d021c6d, 0x1c7fd3e4, 0xd3e02f02, 
+    0x24004d7d, 0x81f0f8df, 0x91ecf8df, 0xf1a83d74, 0xf1a9086c, 0xf1050964, 0xf1080a04, 0xe0370b04, 
+    0x2c01b3ac, 0x2c02d041, 0x0300f04f, 0x0204f04f, 0x0110f04f, 0x4648d044, 0xfec6f011, 0x2300486e, 
+    0x21102204, 0xf0113860, 0x1c64febf, 0x2c04b2e4, 0x2700d3e6, 0x03202400, 0x2107ea40, 0x38544866, 
+    0xfea9f011, 0x20407831, 0xfaeef7ee, 0x21004862, 0xf0113850, 0x7831fea0, 0xf7ee2040, 0x1c64fae5, 
+    0xd3e82c04, 0x2f021c7f, 0x2400d3e4, 0xe7ffe03b, 0x23004859, 0x21102204, 0xf011387c, 0x4856fe95, 
+    0x22042300, 0x38782110, 0x2300e7cd, 0x22044628, 0xf0112110, 0x2300fe89, 0x22044650, 0xe7c22110, 
+    0xf0114640, 0x2300fe81, 0x22044658, 0xe7ba2110, 0x2c01b1cc, 0x2c02d028, 0x0301f04f, 0x0204f04f, 
+    0x0110f04f, 0x4638d02b, 0xfe6ef011, 0x23014842, 0x21102204, 0xf0113860, 0x1c64fe67, 0x2c04b2e4, 
+    0xe8bdd3e6, 0x483c9ff0, 0x22042301, 0x387c2110, 0xfe5af011, 0x23014838, 0x21102204, 0xf0113878, 
+    0x4646fe53, 0xe7e8464f, 0x46282301, 0x21102204, 0xfe4af011, 0x46502301, 0x21102204, 0x4630e7db, 
+    0xfe42f011, 0x46582301, 0x21102204, 0xb430e7d3, 0x02c84604, 0xeb004929, 0xeb0010c2, 0x44080043, 
+    0xbc30b2a1, 0xbe2df011, 0x4605b570, 0x492302c8, 0x10c2eb00, 0x0043eb00, 0x46201844, 0xfe1ef011, 
+    0xf0114620, 0x8028fe1b, 0xe92dbd70, 0xb09f4ff0, 0x201e4923, 0x085ef04f, 0x223c2722, 0xa808901c, 
+    0xe828f011, 0x6800a01f, 0x2000901d, 0x25009018, 0xe001b246, 0xd2482d02, 0x4631b26a, 0x46142307, 
+    0xf7ffa817, 0xf9bdffd1, 0x4641005c, 0xda034540, 0xdc0242b8, 0xe0004638, 0x46224608, 0x46312307, 
+    0x005cf8ad, 0xffb3f7ff, 0x46222309, 0x4631a817, 0xffbaf7ff, 0x0000e018, 0xd18008f0, 0xd003c400, 
+    0xd003c500, 0xd003cc00, 0xd003cd00, 0xd003d400, 0xd003d500, 0xd003dc00, 0xd003dd00, 0x0003227f, 
+    0x0002e0d0, 0x0d0f0f0f, 0x005cf9bd, 0x45404641, 0x42b8da03, 0x4638dc02, 0x4608e000, 0x23094622, 
+    0xf8ad4631, 0xf7ff005c, 0xa81dff82, 0x2400a908, 0xb005f910, 0x1005ebc5, 0x901b4408, 0x901ab268, 
+    0x981be016, 0x9a1a4631, 0xa8175703, 0xff7cf7ff, 0x005cf9bd, 0x45404641, 0x42b8da03, 0x4638dc02, 
+    0x4608e000, 0x005cf8ad, 0x0014f82d, 0xb2e41c64, 0xdbe6455c, 0xf1ab2400, 0x901e0001, 0x4669e02e, 
+    0x0044eb01, 0xf93d9019, 0xf9b09014, 0xebbaa002, 0xd5000009, 0x991c4240, 0x4288b200, 0x1a40dd1b, 
+    0x70d0eb00, 0xf0131040, 0xf012fe10, 0xf013fe09, 0xb200fdaf, 0x45d14669, 0xeb09da06, 0xebaa0200, 
+    0xf8210000, 0xe0042014, 0x0200eba9, 0xf8214450, 0x99192014, 0x1c648048, 0xb2e4981e, 0xdbce4284, 
+    0x46e92400, 0x981be009, 0x9a1a4631, 0xf9395703, 0xf7ff0014, 0x1c64ff1c, 0x455cb2e4, 0x1c6ddbf3, 
+    0x2d04b2ed, 0xaf46f4ff, 0x1c409818, 0x9018b2c0, 0xf4ff2804, 0xb01faf3c, 0x8ff0e8bd, 0x22002301, 
+    0xb5104619, 0xf01148fe, 0x48fdfd3f, 0x22002301, 0x30084619, 0xfd38f011, 0x230148f9, 0x46192200, 
+    0xf0113010, 0x48f6fd31, 0x22002301, 0xe8bd4619, 0x30184010, 0xbd28f011, 0x4ff8e92d, 0x20004df1, 
+    0x46044ff1, 0xf6409000, 0xf8df4a00, 0xf24283c0, 0xf8df0b00, 0x802893bc, 0x2c00e055, 0x2c01d053, 
+    0x8828d07e, 0xf04f2c02, 0xf243020c, 0xb2830100, 0x48e7d077, 0xf011387a, 0x2303fd1e, 0x0100f247, 
+    0x464e220c, 0xf0114648, 0x48e1fd16, 0x22092301, 0x1c800259, 0xfd0ff011, 0x46302305, 0x21702204, 
+    0xfd09f011, 0x230148da, 0x4651220a, 0xf0113872, 0x48d7fd02, 0x210c2302, 0x3848461a, 0xfcfbf011, 
+    0x230148d3, 0x4659220d, 0xf011383a, 0x1c64fcf4, 0x2c04b264, 0x2101dbc1, 0x46082200, 0xfce6f7ff, 
+    0xfd3bf7ff, 0x221048c6, 0x03112300, 0xf0113068, 0x4dc5fccb, 0x4ec52400, 0x3d2c4fc5, 0xf8df3e2c, 
+    0x3f2c8314, 0x8828e09d, 0xb283220c, 0x029148c1, 0xf011384e, 0x4ebffcd0, 0x220c2303, 0x0100f247, 
+    0x4630362c, 0xfcc7f011, 0x22092301, 0x1cb00259, 0xfcc1f011, 0x46302305, 0x21702204, 0xfcbbf011, 
+    0x230148b4, 0x4651220a, 0xf0113846, 0x48b1fcb4, 0x210c2302, 0x381c461a, 0xfcadf011, 0xe0012301, 
+    0xe034e005, 0x220d48ab, 0x380e4659, 0x8828e7ad, 0xb283220c, 0x029148a4, 0xf011387a, 0x2303fc9c, 
+    0x0100f247, 0x4638220c, 0xfc95f011, 0x2301489e, 0x02592209, 0xf0111c80, 0x2305fc8e, 0x22044638, 
+    0xf0112170, 0x4898fc88, 0x220a2301, 0x38724651, 0xfc81f011, 0x23024894, 0x461a210c, 0xf0113848, 
+    0x4891fc7a, 0x220d2301, 0x383a4659, 0x488fe77d, 0xf011387a, 0x2303fc70, 0x0100f247, 0x4646220c, 
+    0xf0114640, 0x4889fc68, 0x22092301, 0x1c800259, 0xfc61f011, 0x46302305, 0x21702204, 0xfc5bf011, 
+    0x23014882, 0x4651220a, 0xf0113872, 0x487ffc54, 0x210c2302, 0x3848461a, 0xfc4df011, 0x2301487b, 
+    0x4659220d, 0xe750383a, 0x2c01b15c, 0x2c02d00e, 0x0300f04f, 0x0202f04f, 0x0104f04f, 0x4638d00b, 
+    0x2300e00a, 0x22024640, 0xe0052104, 0x46282300, 0x21042202, 0x4630e000, 0xfc2df011, 0xb2641c64, 
+    0xdbe12c04, 0x2140486c, 0xfc0bf011, 0xfec6f7ff, 0xb18cf8df, 0x0000f44f, 0x91a0f8df, 0xa180f8df, 
+    0xf10b0204, 0x90000b08, 0x2102e006, 0x4668464a, 0xf8b4f7ee, 0xd01d2801, 0x4621221f, 0xf0114650, 
+    0x2800fc01, 0x221fd0f1, 0x46584621, 0xfbfaf011, 0xd0ea2800, 0x221f4852, 0x30104621, 0xfbf2f011, 
+    0xd0e22800, 0x221f484e, 0x30184621, 0xfbeaf011, 0xd0da2800, 0xfdb9f7ff, 0x22104849, 0x03112301, 
+    0xf0113068, 0x2400fbd1, 0xb15ce00c, 0xd00e2c01, 0xf04f2c02, 0xf04f0301, 0xf04f0202, 0xd00b0104, 
+    0xe00a4638, 0x46402301, 0x21042202, 0x2301e005, 0x22024628, 0xe0002104, 0xf0114630, 0x1c64fbcc, 
+    0x2c04b264, 0x2200dbe1, 0x46104611, 0xfbbef7ff, 0x8ff8e8bd, 0x4604b510, 0x48314603, 0x21012200, 
+    0xf0113070, 0x482efba1, 0x21012200, 0x30744623, 0xfb9af011, 0x2200482a, 0x46232101, 0xf0113078, 
+    0x4827fb93, 0x21012200, 0x307c4623, 0xfb8cf011, 0x22004823, 0x46232101, 0xf0113080, 0x4820fb85, 
+    0x21012200, 0x30844623, 0xfb7ef011, 0x2200481c, 0x46232101, 0xf0113088, 0x4819fb77, 0x21012200, 
+    0xe8bd4623, 0x308c4010, 0xbb6ef011, 0x4604b510, 0x48134603, 0x21102204, 0xf0113070, 0x4810fb65, 
+    0x21102204, 0x30744623, 0xfb5ef011, 0x2204480c, 0x46232110, 0xf0113078, 0x4809fb57, 0x21102204, 
+    0x307c4623, 0xfb50f011, 0x22044805, 0x46232110, 0xf0113080, 0x2204fb49, 0x21104801, 0xe00f4623, 
+    0xd1800804, 0x00032770, 0xd003ca88, 0xd003d288, 0xd003da88, 0xd003c25c, 0xd003c424, 0xd003517a, 
+    0xf0113084, 0x48fbfb31, 0x21102204, 0xf0114623, 0x48f8fb2b, 0x21102204, 0xe8bd4623, 0x1d004010, 
+    0xbb22f011, 0x4605b570, 0x48f24603, 0x7400f240, 0x46212208, 0xf0113818, 0x48eefb17, 0x462b2208, 
+    0x38144621, 0xfb10f011, 0x220848ea, 0x4621462b, 0xf0113810, 0x48e7fb09, 0x462b2208, 0x380c4621, 
+    0xfb02f011, 0x220848e3, 0x4621462b, 0xf0113808, 0x48e0fafb, 0x462b2208, 0x1f004621, 0xfaf4f011, 
+    0x220848dc, 0x4621462b, 0xfaeef011, 0x462b48d9, 0xe8bd4621, 0x22084070, 0xf0111d00, 0xb510bae5, 
+    0x46034604, 0x220048d3, 0x38642101, 0xfadcf011, 0x220048d0, 0x46232101, 0xf011385c, 0x48cdfad5, 
+    0x21012200, 0x38544623, 0xfacef011, 0x220048c9, 0x46232101, 0xf011384c, 0x48c6fac7, 0x21012200, 
+    0x38444623, 0xfac0f011, 0x220048c2, 0x46232101, 0xf011383c, 0x48bffab9, 0x21012200, 0x38344623, 
+    0xfab2f011, 0x220048bb, 0x46232101, 0x4010e8bd, 0xf011382c, 0xb510baa9, 0x46034604, 0x220148b5, 
+    0x38642102, 0xfaa0f011, 0x220148b2, 0x46232102, 0xf011385c, 0x48affa99, 0x21022201, 0x38544623, 
+    0xfa92f011, 0x220148ab, 0x46232102, 0xf011384c, 0x48a8fa8b, 0x21022201, 0x38444623, 0xfa84f011, 
+    0x220148a4, 0x46232102, 0xf011383c, 0x48a1fa7d, 0x21022201, 0x38344623, 0xfa76f011, 0x2201489d, 
+    0x46232102, 0x4010e8bd, 0xf011382c, 0xb570ba6d, 0x46034605, 0xf6434897, 0x220474f0, 0x38644621, 
+    0xfa62f011, 0x22044893, 0x4621462b, 0xf011385c, 0x4890fa5b, 0x462b2204, 0x38544621, 0xfa54f011, 
+    0x2204488c, 0x4621462b, 0xf011384c, 0x4889fa4d, 0x462b2204, 0x38444621, 0xfa46f011, 0x22044885, 
+    0x4621462b, 0xf011383c, 0x4882fa3f, 0x462b2204, 0x38344621, 0xfa38f011, 0x462b487e, 0xe8bd4621, 
+    0x22044070, 0xf011382c, 0xb570ba2f, 0x46034605, 0xf44f4878, 0x221204f8, 0x38644621, 0xfa24f011, 
+    0x22124874, 0x4621462b, 0xf011385c, 0x4871fa1d, 0x462b2212, 0x38544621, 0xfa16f011, 0x2212486d, 
+    0x4621462b, 0xf011384c, 0x486afa0f, 0x462b2212, 0x38444621, 0xfa08f011, 0x22124866, 0x4621462b, 
+    0xf011383c, 0x4863fa01, 0x462b2212, 0x38344621, 0xf9faf011, 0x462b485f, 0xe8bd4621, 0x22124070, 
+    0xf011382c, 0xb570b9f1, 0x46034605, 0xf04f4859, 0x221854f8, 0x38644621, 0xf9e6f011, 0x22184855, 
+    0x4621462b, 0xf011385c, 0x4852f9df, 0x462b2218, 0x38544621, 0xf9d8f011, 0x2218484e, 0x4621462b, 
+    0xf011384c, 0x484bf9d1, 0x462b2218, 0x38444621, 0xf9caf011, 0x22184847, 0x4621462b, 0xf011383c, 
+    0x4844f9c3, 0x462b2218, 0x38344621, 0xf9bcf011, 0x462b4840, 0xe8bd4621, 0x22184070, 0xf011382c, 
+    0xb510b9b3, 0x46034604, 0x2200483a, 0x38682101, 0xf9aaf011, 0x22004837, 0x46232101, 0xf0113860, 
+    0x4834f9a3, 0x21012200, 0x38584623, 0xf99cf011, 0x22004830, 0x46232101, 0xf0113850, 0x482df995, 
+    0x21012200, 0x38484623, 0xf98ef011, 0x22004829, 0x46232101, 0xf0113840, 0x4826f987, 0x21012200, 
+    0x38384623, 0xf980f011, 0x22004822, 0x46232101, 0x4010e8bd, 0xf0113830, 0xb510b977, 0x46034604, 
+    0x2201481c, 0x38682102, 0xf96ef011, 0x22014819, 0x46232102, 0xf0113860, 0x4816f967, 0x21022201, 
+    0x38584623, 0xf960f011, 0x22014812, 0x46232102, 0xf0113850, 0x480ff959, 0x21022201, 0x38484623, 
+    0xf952f011, 0x2201480b, 0x46232102, 0xf0113840, 0x4808f94b, 0x21022201, 0x38384623, 0xf944f011, 
+    0x22014804, 0x46232102, 0x4010e8bd, 0xf0113830, 0x0000b93b, 0xd180088c, 0x4cfeb570, 0x46052204, 
+    0x48fd4603, 0xf0114621, 0x48fbf92f, 0x462b2204, 0x30084621, 0xf928f011, 0x220448f7, 0x4621462b, 
+    0xf0113010, 0x48f4f921, 0x462b2204, 0x30184621, 0xf91af011, 0x220448f0, 0x4621462b, 0xf0113020, 
+    0x48edf913, 0x462b2204, 0x30284621, 0xf90cf011, 0x220448e9, 0x4621462b, 0xf0113030, 0x48e6f905, 
+    0x4621462b, 0x4070e8bd, 0x30382204, 0xb8fcf011, 0xf44fb570, 0x460504f8, 0x46032212, 0x462148de, 
+    0xf8f2f011, 0x221248dc, 0x4621462b, 0xf0113008, 0x48d9f8eb, 0x462b2212, 0x30104621, 0xf8e4f011, 
+    0x221248d5, 0x4621462b, 0xf0113018, 0x48d2f8dd, 0x462b2212, 0x30204621, 0xf8d6f011, 0x221248ce, 
+    0x4621462b, 0xf0113028, 0x48cbf8cf, 0x462b2212, 0x30304621, 0xf8c8f011, 0x462b48c7, 0xe8bd4621, 
+    0x22124070, 0xf0113038, 0xb570b8bf, 0x54f8f04f, 0x22184605, 0x48c04603, 0xf0114621, 0x48bef8b5, 
+    0x462b2218, 0x30084621, 0xf8aef011, 0x221848ba, 0x4621462b, 0xf0113010, 0x48b7f8a7, 0x462b2218, 
+    0x30184621, 0xf8a0f011, 0x221848b3, 0x4621462b, 0xf0113020, 0x48b0f899, 0x462b2218, 0x30284621, 
+    0xf892f011, 0x221848ac, 0x4621462b, 0xf0113030, 0x48a9f88b, 0x4621462b, 0x4070e8bd, 0x30382218, 
+    0xb882f011, 0x4ff7e92d, 0x48a44604, 0x7800460d, 0xd1012804, 0x90022000, 0x46209a02, 0xf886f7ff, 
+    0xf7ff2014, 0x201fffb2, 0xff72f7ff, 0x0000f640, 0xff32f7ff, 0xf7ff2001, 0xb2e0fef0, 0xfeb1f7ff, 
+    0xf7ff2012, 0x201ffe70, 0xfe2ff7ff, 0x1000f240, 0xfdedf7ff, 0xf7ff2001, 0xb2e0fdae, 0xfd6ff7ff, 
+    0x7800488f, 0xf7ffb240, 0x2001fd2d, 0xfcdef7ff, 0xf7ffb2e8, 0xf8dffc9f, 0x2400b220, 0x5af8f04f, 
+    0x0b80f10b, 0x0504f10b, 0xf44f1d2e, 0xf1061970, 0xe02b0804, 0x2c01b354, 0x2c02d02e, 0x0309f04f, 
+    0x0218f04f, 0xd0444651, 0x46404647, 0xf82cf011, 0x4649230f, 0x46382212, 0xf826f011, 0x46382305, 
+    0x21302204, 0xf820f011, 0x46382301, 0x461a2102, 0xf81af011, 0x22009b02, 0x46382101, 0xf814f011, 
+    0xb2e41c64, 0xd3d52c04, 0x8ffee8bd, 0x46512309, 0x465f2218, 0xe7d94658, 0x46512309, 0x46282218, 
+    0xf802f011, 0x4649230f, 0x46282212, 0xfffcf010, 0x46282305, 0x21302204, 0xfff6f010, 0x46282301, 
+    0x461a2102, 0xfff0f010, 0x9b022200, 0x46282101, 0x4630e7d4, 0xffe8f010, 0x4649230f, 0x46302212, 
+    0xffe2f010, 0x46302305, 0x21302204, 0xffdcf010, 0x46302301, 0x461a2102, 0xffd6f010, 0x9b022200, 
+    0x46302101, 0x494ee7ba, 0x47707008, 0x4ff0e92d, 0x484cb0bb, 0xf8dfac2b, 0xf8dfb134, 0x9038a134, 
+    0x90364849, 0x9035484b, 0xc80e484b, 0x000ee884, 0xac28c80e, 0x000ee884, 0xac2ec80e, 0x000ee884, 
+    0xab31c807, 0x0007e883, 0x22304943, 0x3130a805, 0xe9c0f010, 0x78014841, 0xd0062901, 0x90372001, 
+    0x20029034, 0x903a2500, 0x2108e0ea, 0x21049137, 0x21009134, 0xe7f47001, 0x2000a924, 0xf8214680, 
+    0x983a0015, 0xfa4f9039, 0xe9ddf188, 0x22000335, 0xe9cd460e, 0xe9cda003, 0x98383b01, 0x4300f240, 
+    0x98399000, 0xf908f003, 0xb1242400, 0xd0052c01, 0xd17c2c02, 0x9f36e005, 0xe004465b, 0x4653465f, 
+    0x9b35e001, 0x20004657, 0x1e422110, 0x0c44f10d, 0x0e68f10d, 0x1010f82c, 0x2010f82e, 0x28101c40, 
+    0xa82bddf4, 0xf8502100, 0xf9379024, 0xf9330011, 0x45812011, 0xf10dda17, 0xf85c0ca0, 0x4584c024, 
+    0xf10ddd11, 0xf93e0e44, 0x4594c010, 0x4694db00, 0xc010f82e, 0x0e68f10d, 0xc010f93e, 0xdd004594, 
+    0xf82e4662, 0x1c492010, 0x6f80f5b1, 0xf109dbdd, 0xe0720701, 0x0001fff0, 0xd1800824, 0x0003227e, 
+    0x00032332, 0x0003627c, 0x0003527c, 0x00035a7c, 0x00038a7c, 0x00039a7c, 0x0002e10c, 0x00032280, 
+    0xa92ea811, 0x0017f930, 0x1024f851, 0xdc274288, 0x1104ebc4, 0x4408a805, 0x44384631, 0x4691b262, 
+    0x0c01f910, 0x46039000, 0xf7ffa823, 0xf8bdf8dd, 0x9834108c, 0xb2004408, 0x008cf8ad, 0xdb00287f, 
+    0xf8ad207f, 0x9b00008c, 0x4631464a, 0xe039e000, 0xf8bdf7ff, 0xf830a824, 0x1c491015, 0x1015f820, 
+    0xa931a81a, 0x0017f930, 0x1024f851, 0xdb234288, 0x1104ebc4, 0x4408a805, 0xb2624631, 0x57c04691, 
+    0x46039000, 0xf7ffa823, 0xf8bdf8af, 0x9834108c, 0xb2001a08, 0x008cf8ad, 0xdc002800, 0xf8ad2000, 
+    0x9b00008c, 0x4631464a, 0xf891f7ff, 0xf830a824, 0x1c491015, 0x1015f820, 0xa8281c7f, 0x0024f850, 
+    0xdc9d42b8, 0xb2e41c64, 0xf4ff2c03, 0xf108af3e, 0xf0000001, 0xf1b808ff, 0xf4ff0f04, 0x1c6daf24, 
+    0x42859837, 0xaf18f6ff, 0xf88ff7ff, 0xe8bdb03b, 0xb5708ff0, 0x220c4c64, 0x4603460d, 0x46200291, 
+    0xfea2f010, 0x462b2208, 0x01514620, 0xfe9cf010, 0x20402100, 0xfad8f7ed, 0xf6402200, 0x1d2071ff, 
+    0xfea0f010, 0x000af3c0, 0x6f80f5b0, 0xf5a0db01, 0xbd706000, 0x5ff0e92d, 0xf2400006, 0xd03c2b00, 
+    0x0000f44f, 0x11f4f240, 0xf89bf7e6, 0xf7f32003, 0x2101fcad, 0x46082200, 0xfdf4f7ff, 0xf2402500, 
+    0xf8df6800, 0x2701a128, 0x21002400, 0xf7ff4620, 0x2101ffc0, 0x46204681, 0xffbbf7ff, 0x7140f509, 
+    0xd8034541, 0x7040f500, 0xd9084540, 0xb2e04629, 0xfcb3f7f3, 0x46502140, 0xfe53f010, 0x1c642700, 
+    0x2c04b264, 0xb947dbe1, 0xf44f2100, 0xf7ed3080, 0x353ffa8b, 0x455db22d, 0xf8dfdbd3, 0x2500a0d4, 
+    0x39fff240, 0x2400e049, 0x0801f04f, 0x46202100, 0xff8ff7ff, 0x46072101, 0xf7ff4620, 0x4557ff8a, 
+    0x464fd100, 0xd1004550, 0x44384648, 0x1040b200, 0xf100b14e, 0xf5b10180, 0xd9207f80, 0xf04f10c7, 
+    0xd1090800, 0x2880e01b, 0x2701dd01, 0xf110e004, 0xda140f80, 0x37fff04f, 0xf7f3b2e0, 0x4438fc69, 
+    0x2900b201, 0x2100da00, 0xdb014559, 0x11fff240, 0xf7f3b2e0, 0x4815fc62, 0xf0102140, 0x1c64fe02, 
+    0x2c04b264, 0xf1b8dbc2, 0xd10c0f00, 0xf44f2100, 0xf7ed3080, 0x1c6dfa39, 0xb10eb22d, 0xe0002008, 
+    0x42a82001, 0x2e00dcaf, 0x2200d00b, 0x46112001, 0xfd68f7ff, 0x5ff0e8bd, 0xf44f4906, 0xf7e50000, 
+    0xe8bdbfef, 0x00009ff0, 0xd180089c, 0xd003c424, 0xfffffc00, 0xdcba01f5, 0x41f0e92d, 0x0800ea5f, 
+    0x0700f241, 0x0400f640, 0x4efe4dfd, 0x2300d025, 0x220c4639, 0xf0104628, 0x2300fdde, 0x220b4621, 
+    0xf0104628, 0x2300fdd8, 0x220c4639, 0xf0104630, 0x2300fdd2, 0x220b4621, 0xf0104630, 0x2203fdcc, 
+    0x21084643, 0xf0104628, 0x4643fdc6, 0xe8bd4630, 0x220341f0, 0xf0102108, 0x2301bdbe, 0x220c4639, 
+    0xf0104628, 0x2301fdb8, 0x220b4621, 0xf0104628, 0x2301fdb2, 0x220c4639, 0xf0104630, 0x2301fdac, 
+    0xe92de7d8, 0xf8df5ff0, 0xf04fa380, 0xf6470900, 0x464d6808, 0x3bf0f240, 0x02ee2400, 0x0144eb06, 
+    0x000aeb01, 0x22044659, 0xf0104607, 0xb200fda2, 0xdd05283c, 0x46414638, 0xfd73f010, 0x0901f04f, 
+    0xb2241c64, 0xdbe92c80, 0xb22d1c6d, 0xdbe32d04, 0xe8bd4648, 0xb5709ff0, 0x0400f244, 0x220e4605, 
+    0x48ca4603, 0xf0104621, 0x48c5fd76, 0x462b220e, 0x30084621, 0xfd6ff010, 0x220e48c5, 0x4621462b, 
+    0xfd69f010, 0x462b48bf, 0xe8bd4621, 0x220e4070, 0xf0103008, 0xb570bd60, 0x6400f240, 0x22094605, 
+    0x48ba4603, 0xf0104621, 0x48b5fd56, 0x462b2209, 0x30084621, 0xfd4ff010, 0x220948b5, 0x4621462b, 
+    0xfd49f010, 0x462b48af, 0xe8bd4621, 0x22094070, 0xf0103008, 0xe92dbd40, 0x21004ff8, 0xf7ff9100, 
+    0x2001ffda, 0xffb7f7ff, 0xf7ff2000, 0x2301ffb4, 0x220e4da6, 0x4628039c, 0xf0104621, 0x4ea0fd2c, 
+    0x220e2301, 0x36084621, 0xf0104630, 0x4fa0fd24, 0x220e2301, 0x46384621, 0xfd1df010, 0x8264f8df, 
+    0x220e2301, 0xf1084621, 0x46400808, 0xfd13f010, 0x46212300, 0x4628220e, 0xfd0df010, 0x46212300, 
+    0x4630220e, 0xfd07f010, 0x46212300, 0x4638220e, 0xfd01f010, 0x46212300, 0x4640220e, 0xfcfbf010, 
+    0x01602100, 0xf920f7ed, 0x4e8a0265, 0x11a44f8a, 0x8228f8df, 0xa228f8df, 0x9228f8df, 0xe0069500, 
+    0x46322103, 0xf7ed4668, 0x2801f989, 0x2208d01b, 0x46384621, 0xfcedf010, 0xd1f12800, 0x46212208, 
+    0xf0104640, 0x2800fce6, 0x2208d1ea, 0x46504621, 0xfcdff010, 0xd1e32800, 0x46212208, 0xf0104648, 
+    0x2800fcd8, 0xf240d1dc, 0x462811f4, 0xfec9f7e5, 0x46284975, 0xfeb4f7e5, 0xf0104869, 0x4601fc9f, 
+    0xf7e54628, 0x4867fead, 0xfc98f010, 0x46284601, 0xfea6f7e5, 0x4628496d, 0xfea2f7e5, 0x8ff8e8bd, 
+    0x47f0e92d, 0xb086486a, 0x0a0cf10d, 0x91a4f8df, 0xc80e2700, 0x000ee88d, 0xe88ac807, 0x24020007, 
+    0x28c7ea4f, 0x0144eb08, 0x0509eb01, 0x46282200, 0xf010210f, 0xb206fc9e, 0x0014f93a, 0xda0842b0, 
+    0x46282301, 0x03d9220f, 0xfc85f010, 0x46283e0b, 0xf93de00c, 0x42b00014, 0xdd0b4628, 0xf2442300, 
+    0x220e0100, 0xfc77f010, 0x4628360b, 0xb2b32200, 0xe003210f, 0xf24c2301, 0x220e0100, 0xfc6bf010, 
+    0xb2241c64, 0xdbcd2c05, 0xb23f1c7f, 0xdbc62f04, 0xe8bdb006, 0xe92d87f0, 0xf8df47f0, 0x270090ec, 
+    0xea4f2600, 0xeb0828c7, 0xeb010146, 0x22000409, 0x210f4620, 0xfc5df010, 0x2d0db205, 0x2301dd08, 
+    0x220f4620, 0xf01003d9, 0x3d0bfc46, 0xe00a4620, 0x46202d02, 0x2300da0b, 0x0100f244, 0xf010220e, 
+    0x350bfc3a, 0x22004620, 0x210fb2ab, 0x2301e003, 0x0100f24c, 0xf010220e, 0x1c76fc2e, 0x2e82b236, 
+    0x1c7fdbd1, 0x2f04b23f, 0xe7c2dbca, 0x8803b570, 0x48284604, 0x35c0f240, 0x46292206, 0xf010300a, 
+    0x8863fc1a, 0x48242206, 0xf0104629, 0x88a3fc14, 0x48222206, 0xf0104629, 0x88e3fc0e, 0xe8bd4629, 
+    0x481f4070, 0xf0102206, 0xb570bc06, 0x48194604, 0x35c0f240, 0x46292206, 0xf010300a, 0x8020fc0a, 
+    0x48152206, 0xf0104629, 0x80a0fc04, 0x48132206, 0xf0104629, 0x8120fbfe, 0x48112206, 0xe0214629, 
+    0xd003c810, 0xd003d810, 0xd003c600, 0xd003c018, 0xd003d018, 0xd003517a, 0xd003c2c0, 0xd003cac0, 
+    0xd003d2c0, 0xd003dac0, 0x00029ec5, 0xdcba01f5, 0x0002e16c, 0xd003c704, 0xd003cf0e, 0xd003d70e, 
+    0xd003df0e, 0xfbd5f010, 0x220681a0, 0x4629487e, 0xfbcff010, 0x22068060, 0x4629487c, 0xfbc9f010, 
+    0x220680e0, 0x4629487a, 0xfbc3f010, 0x22068160, 0x46294878, 0xfbbdf010, 0xbd7081e0, 0x47f0e92d, 
+    0x81d4f8df, 0xf06f2400, 0x46060960, 0x02e72500, 0x9014f826, 0x0145eb07, 0x0008eb01, 0x210f2200, 
+    0xfba7f010, 0x1014f836, 0xb22d1c6d, 0x2d824408, 0x0014f826, 0x1c64dbee, 0x2c04b224, 0xe728dbe6, 
+    0xf640b570, 0x46056400, 0x46032209, 0x46214863, 0xfb81f010, 0x2209485c, 0x4621462b, 0xf01030f8, 
+    0x485afb7a, 0x462b2209, 0x30f84621, 0xfb73f010, 0x462b4857, 0xe8bd4621, 0x22094070, 0xf01030f8, 
+    0xe92dbb6a, 0xf8df5ff0, 0x2500b140, 0xa148f8df, 0x6908f647, 0x0b0cf1ab, 0x2400464f, 0x02ee46d0, 
+    0x0144eb06, 0x0008eb01, 0xf0104639, 0x1c64fb3a, 0x2c82b224, 0x2400dbf4, 0x465f46b8, 0xeb064641, 
+    0x44380044, 0xfb2df010, 0xb2241c64, 0xdbf52c05, 0xb22d1c6d, 0xdbdf2d04, 0xe92de5bb, 0xb08841f0, 
+    0x27004604, 0x463b2203, 0x46384639, 0xf0029700, 0x2000f8c7, 0xfd40f7ff, 0xffc3f7ff, 0x2001b3ec, 
+    0xff9ef7ff, 0x25c32400, 0x080cf10d, 0x2002ae01, 0xfde1f7ff, 0xfd75f7ff, 0xf7ffa801, 0xa803ff6f, 
+    0xff13f7ff, 0x46412000, 0x2010f936, 0x3020f831, 0x32cff2a2, 0xfb924252, 0x441af2f5, 0x2a00b212, 
+    0x2010f826, 0x2200da00, 0xf8262a0f, 0xdd002010, 0xf826220f, 0x1c402010, 0x2804b200, 0xa801dbe4, 
+    0xfed4f7ff, 0xb2241c64, 0xdbd02c03, 0xf7ff2002, 0xf7fffdb2, 0xa801fd46, 0xe00be000, 0xfe8bf7ff, 
+    0xfe3ef7ff, 0xf7ff2003, 0xf7fffda6, 0x2801fd3a, 0xe00bd007, 0xf7ff2000, 0x2003ff53, 0xfd9bf7ff, 
+    0x2002e004, 0xfd97f7ff, 0xfd2bf7ff, 0x97002300, 0x46192203, 0xf0022008, 0x2001f863, 0xfcdcf7ff, 
+    0xe8bdb008, 0x000081f0, 0xd003c710, 0xd003cf10, 0xd003d710, 0xd003df10, 0xd003c600, 0xd003c008, 
+    0x4c39b570, 0x211f2300, 0x4620461a, 0xfab3f010, 0xf2404835, 0x220535e0, 0x301a4629, 0xfab9f010, 
+    0x46032205, 0x46204629, 0xfaa5f010, 0x46202301, 0x0299220a, 0xfa9ff010, 0x23024c2b, 0xf24f220c, 
+    0x34200100, 0xf0104620, 0x2304fa96, 0x22004620, 0xf010210f, 0x2301fa90, 0x210f2200, 0xf0101f20, 
+    0x2301fa8a, 0x210f2200, 0xe8bd1ea0, 0xf0104070, 0x481eba82, 0xf010b510, 0x491dfa61, 0x491d8008, 
+    0x491d680a, 0xd11c2a03, 0x78124a1c, 0xd01807d2, 0x02c0f3c0, 0x4a1a700a, 0x1180f3c0, 0x4a197011, 
+    0xf3c07011, 0x4a1811c0, 0xf3c07011, 0x4a172100, 0xf3c07011, 0x4a1621c0, 0x70110bc0, 0x70084915, 
+    0xf3c0bd10, 0xe7e51240, 0xf64b4808, 0xb51031b3, 0xf0103084, 0xf7fffa36, 0x490fffcc, 0x70082000, 
+    0x4010e8bd, 0x0000e78c, 0xd03c8204, 0xd03c8034, 0x000323c0, 0x00032374, 0x00032304, 0x00032228, 
+    0x000322ed, 0x000322ec, 0x000323bd, 0x00032363, 0x000323be, 0x000323bf, 0x000323f0, 0x4db8b570, 
+    0x2200b283, 0x21014604, 0xf0104628, 0xb2a3fa24, 0x22014628, 0xf0102102, 0xb2a3fa1e, 0x22024628, 
+    0xf0102104, 0x2301fa18, 0x22034628, 0xf0102108, 0xb2a3fa12, 0xe8bd4628, 0x22044070, 0xf0102110, 
+    0xe92dba0a, 0x48a741f0, 0xf0102100, 0x48a5f9ea, 0x1c802100, 0xf9e5f010, 0x210048a2, 0xf0101d00, 
+    0x48a0f9e0, 0x1d802100, 0xf9dbf010, 0x2100489d, 0xf0103008, 0x489bf9d6, 0x300a2100, 0xf9d1f010, 
+    0x21004898, 0xf010300c, 0x4896f9cc, 0x300e2100, 0xf9c7f010, 0x21004893, 0xf0103010, 0x4891f9c2, 
+    0x30122140, 0xf9bdf010, 0x2100488e, 0xf0103014, 0x488cf9b8, 0x30162104, 0xf9b3f010, 0x21004889, 
+    0xf0103018, 0x4887f9ae, 0x301a2100, 0xf9a9f010, 0x21004884, 0xf010301c, 0x2307f9a4, 0x22004882, 
+    0xf0104619, 0x4881f9b8, 0x1cad4d7d, 0x487d7801, 0x1c843020, 0x29001e86, 0x0100f04f, 0x4607d019, 
+    0xf98ff010, 0x46382301, 0x21202205, 0xf9a3f010, 0x46202100, 0xf985f010, 0x46282100, 0xf981f010, 
+    0x4100f240, 0xf0104630, 0xe8bdf97c, 0x200141f0, 0xf010e764, 0x2100f976, 0xf0104620, 0x2100f972, 
+    0xf0104628, 0xf242f96e, 0xe7eb4192, 0x460cb510, 0x78094966, 0xd1152900, 0x4862b283, 0x21032200, 
+    0xf010301e, 0x485ff978, 0x2200b2a3, 0x1d00210f, 0xf971f010, 0x485a2301, 0xe8bd2205, 0x21204010, 
+    0xb969f010, 0x4859bd10, 0x28007800, 0x4855d106, 0x21032300, 0x301e461a, 0xb95df010, 0xb5104770, 
+    0x4952460c, 0x29007809, 0xb283d115, 0x2203484d, 0x301e2118, 0xf94ff010, 0xb2a3484a, 0x210f2200, 
+    0xf010300a, 0x2301f948, 0x22064845, 0x4010e8bd, 0xf0102140, 0xbd10b940, 0x78004844, 0xd1062800, 
+    0x23004840, 0x21182203, 0xf010301e, 0x4770b934, 0x460cb510, 0x7809493d, 0xd1152900, 0x4839b283, 
+    0x21c02206, 0xf010301e, 0x4836f926, 0x2200b2a3, 0x3010210f, 0xf91ff010, 0x48312301, 0xe8bd2207, 
+    0x21804010, 0xb917f010, 0x4830bd10, 0x28007800, 0x482cd106, 0x22062300, 0x301e21c0, 0xb90bf010, 
+    0x48284770, 0x22062301, 0x30202140, 0xb903f010, 0x23004824, 0x21402206, 0xf0103020, 0xb510b8fc, 
+    0x4922460c, 0x29007809, 0xb283d115, 0x220c481d, 0x0291301e, 0xf8eff010, 0xb2a3481a, 0x210f2200, 
+    0xf010301c, 0x2301f8e8, 0x22094815, 0x4010e8bd, 0xf0100259, 0xbd10b8e0, 0x78004814, 0xd1062800, 
+    0x4810220c, 0x02912300, 0xf010301e, 0x4770b8d4, 0xf000b510, 0x2100f81d, 0xf7ff2001, 0x2100ff47, 
+    0xf7ff2001, 0x2100ff6c, 0xf7ff2001, 0x2100ff91, 0xf7ff2001, 0x2100ffb6, 0x4010e8bd, 0xe7be2001, 
+    0xd00351d8, 0xd0035058, 0xd03d1042, 0x000323be, 0xf7ffb510, 0x2301fea6, 0x220048ff, 0xf0104619, 
+    0x48fef8aa, 0x22042301, 0xf0102110, 0x4cfaf8a4, 0x22022301, 0x21041ca4, 0xf0104620, 0x2301f89c, 
+    0x22034620, 0xf0102108, 0x4cf4f896, 0x22022301, 0x21041da4, 0xf0104620, 0x2301f88e, 0x21024620, 
+    0xf010461a, 0x2301f888, 0x21402206, 0xf0101da0, 0x48eaf882, 0x22072301, 0x30122180, 0xf87bf010, 
+    0x23014ce5, 0x34082202, 0x46202104, 0xf873f010, 0x46202301, 0x21082203, 0xf86df010, 0x48df2301, 
+    0x03d9220f, 0x4010e8bd, 0xf0103018, 0x48dab864, 0x22002301, 0x1f004619, 0xf010b510, 0x2100f85c, 
+    0x4010e8bd, 0xf7ff2002, 0x48d3bed1, 0x21012300, 0x1f00461a, 0xf010b510, 0xe8bdf84e, 0xf7ff4010, 
+    0xe92dbee2, 0x4dce5ff0, 0x080ff001, 0x46142300, 0xf04f2202, 0x21040901, 0xf0104628, 0x2301f83c, 
+    0x22064628, 0xf0102140, 0x2301f836, 0x22074628, 0xf0102180, 0x2300f830, 0x22044628, 0xf0102110, 
+    0x2300f82a, 0x22054628, 0xf0102120, 0x2300f824, 0x22014628, 0xf0102102, 0x2300f81e, 0x22034628, 
+    0xf0102108, 0x4fb7f818, 0x080af1a8, 0xf8df4eb5, 0x3f18b2d4, 0xa2d0f8df, 0xf1b83e08, 0xd2760f05, 
+    0xf008e8df, 0xf6f7f903, 0xf8df00f5, 0x1c6082c0, 0x2300d011, 0x22064628, 0xf00f2140, 0xb3ecfffc, 
+    0x28091e60, 0x48a7d854, 0x0148ea4f, 0xf00f3810, 0x2130ffd2, 0x48a3e056, 0x46414644, 0xf00f3810, 
+    0x4621ffca, 0xf00f4658, 0x2300ffc6, 0x22064628, 0xf00f2140, 0x2300ffe0, 0x22074628, 0xf00f2180, 
+    0x2301ffda, 0x21024628, 0xf00f461a, 0x4894ffd4, 0x1c802118, 0xffb5f00f, 0x21184891, 0xf00f3008, 
+    0x2300ffb0, 0x21022201, 0xf00f4628, 0x2301ffc4, 0x461a2102, 0xf00f4628, 0xe1b0ffbe, 0x2301e7ff, 
+    0x21024638, 0xf00f461a, 0x2301ff9f, 0x21024630, 0xf00f461a, 0x2300ff99, 0x22014638, 0xf00f2102, 
+    0x2300ff93, 0x22014630, 0xf00f2102, 0xe185ff8d, 0x000bf1a4, 0xd80b2859, 0x497d487a, 0xf00f3810, 
+    0x212cff7a, 0x1c804876, 0xff7bf00f, 0xe183e187, 0x0065f1a4, 0x7fc8f5b0, 0x4872d206, 0x38104975, 
+    0xff69f00f, 0xe7ed2128, 0x10f5f2a4, 0x7ffaf5b0, 0x486cd206, 0x38104970, 0xff5df00f, 0xe7e12124, 
+    0x30e9f2a4, 0x6f7af5b0, 0x4866d206, 0x3810496b, 0xff51f00f, 0xe7d52120, 0x5098f5a4, 0x3187f241, 
+    0x42883889, 0x485fd806, 0x38104965, 0xff43f00f, 0xe7c7211c, 0x501cf5a4, 0x413ff649, 0x42883811, 
+    0x4858d806, 0x38104641, 0xff35f00f, 0xe7b92118, 0x4043f5a4, 0x314ff24c, 0x42883851, 0x4851d806, 
+    0x38104958, 0xff27f00f, 0xe7ab2114, 0xf5a44956, 0x38a130c3, 0xd8064288, 0x4954484a, 0xf00f3810, 
+    0x2110ff1a, 0x4852e79e, 0x44204952, 0xd8064288, 0x49514844, 0xf00f3810, 0x210cff0e, 0x484fe792, 
+    0x4420494f, 0xd8064288, 0x4651483e, 0xf00f3810, 0x2108ff02, 0x484be786, 0x4420494b, 0xd8854288, 
+    0x494a4838, 0xf00f3810, 0x2104fef6, 0xe050e77a, 0xe01ee041, 0x4833e7ff, 0x46514654, 0xf00f3810, 
+    0x4621feea, 0xf00f4658, 0x482dfee6, 0x1c802108, 0xfee7f00f, 0x2108482a, 0xf00f3008, 0x2300fee2, 
+    0x22064628, 0xf00f2140, 0x2300fef6, 0x21802207, 0x2301e72a, 0x21024638, 0xf00f461a, 0x2301fed5, 
+    0x21024630, 0xf00f461a, 0x2300fecf, 0x22014638, 0xf00f2102, 0x2300fec9, 0x22014630, 0xf00f2102, 
+    0x2300fec3, 0x22074628, 0xf00f2180, 0x2301fed4, 0x21202205, 0x2300e0b5, 0x22074628, 0xf00f2180, 
+    0x4923feca, 0xf00f4658, 0x480dfea6, 0x30082102, 0x4820e72a, 0x0000f990, 0xd03d2803, 0xd03b2805, 
+    0xd0392804, 0xd0702802, 0xf04f2801, 0xd0780301, 0x21402206, 0x0000e6ee, 0xd00351de, 0xd003505e, 
+    0xd03c80d8, 0xc8000178, 0x0501bd00, 0x0f053700, 0x1b898f80, 0x1908b100, 0x1687d280, 0x1406f400, 
+    0x11861580, 0x0c845880, 0x00061a7f, 0x0a037a00, 0xfff85edf, 0x0007a11f, 0x07829b80, 0xfff0bdbf, 
+    0x003d08ff, 0xffb3b4bf, 0x004c4b3f, 0x0280de80, 0x01406f40, 0x00032238, 0x46382301, 0x461a2102, 
+    0xfe62f00f, 0x46302301, 0x461a2102, 0xfe5cf00f, 0x48f949f8, 0xfe4ff00f, 0x46282300, 0x21402206, 
+    0xfe69f00f, 0x210548f5, 0xfe4bf00f, 0x210a48f3, 0xf00f1c80, 0x48f1fe46, 0x1d002105, 0xfe41f00f, 
+    0x46282301, 0x21042202, 0xfe55f00f, 0x46382300, 0x21022201, 0xfe38f00f, 0x46302300, 0x21022201, 
+    0xfe32f00f, 0xe000e03b, 0x49e2e00b, 0xf00f48e2, 0x2300fe22, 0x22064628, 0xf00f2140, 0x2105fe3c, 
+    0x2201e6a0, 0x21024638, 0xfe1ef00f, 0x46302301, 0x461a2102, 0xfe18f00f, 0x46382300, 0x21022201, 
+    0xfe12f00f, 0x46302300, 0x21022201, 0xfe0cf00f, 0x46282300, 0x21402206, 0xfe1df00f, 0x22042301, 
+    0x46282110, 0xfe17f00f, 0xe8bd4628, 0x23015ff0, 0x21082203, 0xbe0ff00f, 0x0f00f1b9, 0x2300d00d, 
+    0x22034630, 0xf00f2108, 0x4630fdef, 0x5ff0e8bd, 0x22032301, 0xf00f2108, 0xe8bdbde7, 0xb5109ff0, 
+    0x78204cbf, 0xd0052801, 0x230148be, 0x21102204, 0xfdf1f00f, 0x20012100, 0xfc91f7ff, 0x28027820, 
+    0x48b6d10d, 0xf00f380a, 0x280efdc9, 0x48b6d107, 0x210e2200, 0x0000f990, 0x4010e8bd, 0xbd10e591, 
+    0x4db2b570, 0x4caf2803, 0x2805d004, 0x2804d017, 0xe030d017, 0x46282300, 0x210c2202, 0xfdcbf00f, 
+    0x46202301, 0x21802207, 0xfdc5f00f, 0x46202300, 0x21102204, 0xfdbff00f, 0xfc7ef7ff, 0x2302e017, 
+    0x2301e000, 0x22024628, 0xf00f210c, 0x2300fdb4, 0x22074620, 0xf00f2180, 0x2300fdae, 0x22044620, 
+    0xf00f2110, 0x2100fda8, 0xf7ff2002, 0x2100fc48, 0xf7ff2002, 0x2100fca4, 0xf7ff2002, 0x4890fc92, 
+    0x28027800, 0x488dd10b, 0xf00f380a, 0xb241fd77, 0x2200488d, 0x0000f990, 0x4070e8bd, 0xbd70e541, 
+    0xf7ffb510, 0xf7fffc20, 0xf7fffc47, 0xf7fffc6e, 0xf7fffc7f, 0x4c85fca1, 0x21012300, 0x4620461a, 
+    0xfd79f00f, 0x46202300, 0x210c2202, 0xfd73f00f, 0x23004c7c, 0x21802207, 0xf00f4620, 0x2300fd6c, 
+    0x22044620, 0xf00f2110, 0x4875fd66, 0x28027800, 0x4c72d10f, 0x22062301, 0x21401ea4, 0xf00f4620, 
+    0x2301fd5a, 0x22074620, 0x4010e8bd, 0xf00f2180, 0xbd10bd52, 0xb510496a, 0x1000f991, 0x2901b189, 
+    0x2902d014, 0x4865d143, 0xf00f380a, 0x280efd27, 0x4865d13d, 0x210e2200, 0x0000f990, 0x4010e8bd, 
+    0xe8bde4ef, 0x20004010, 0xbb08f7ff, 0xb3004c5d, 0xd0202801, 0xd12a2802, 0x46202301, 0x21102204, 
+    0xfd29f00f, 0x46202301, 0x21082203, 0xfd23f00f, 0x220e4857, 0x0100f244, 0xfd2bf00f, 0x28014c53, 
+    0x2300d013, 0x21012200, 0xe8bd4620, 0xf00f4010, 0x2300bd12, 0x2301e000, 0x22044620, 0xf00f2110, 
+    0x2300fd0a, 0x21082203, 0x2301e7ee, 0xbd10e7ea, 0x4c43b570, 0x0000f994, 0x2801b110, 0xe010d004, 
+    0xf7ff2001, 0xe00cfacb, 0x23004d3e, 0x21102204, 0xf00f4628, 0x2300fcf0, 0x22034628, 0xf00f2108, 
+    0xf7fffcea, 0x2300fbe5, 0x21014838, 0xf00f461a, 0x7820fce2, 0xd10f2802, 0x23014c30, 0x1ea42206, 
+    0x46202140, 0xfcd7f00f, 0xe8bd4620, 0x23014070, 0x21802207, 0xbccff00f, 0x2100bd70, 0xb5102002, 
+    0xfbbff7ff, 0x78004826, 0xd10b2802, 0x380a4823, 0xfca4f00f, 0x4824b241, 0xf9902200, 0xe8bd0000, 
+    0xe46e4010, 0xb510bd10, 0xfbb2f7ff, 0x7800481c, 0xd10f2802, 0x23014c19, 0x1ea42206, 0x46202140, 
+    0xfca9f00f, 0x46202301, 0xe8bd2207, 0x21804010, 0xbca1f00f, 0x2100bd10, 0xf7ff2001, 0x2200bb69, 
+    0x4614b510, 0x1e43b128, 0xd20a2b09, 0x700c2000, 0x20ffbd10, 0xbd10700c, 0xf0f3fbb0, 0xb2d21c52, 
+    0x230ae000, 0xd8f7280a, 0xd3132805, 0x70082001, 0x0000e011, 0x1e0a6e00, 0xc8000168, 0xd03c80da, 
+    0x000323be, 0xd0035078, 0x0003227e, 0xd00351da, 0xd28fffd4, 0x4610700c, 0x0fc2bd10, 0x7fd1ebb2, 
+    0xf1c1d203, 0x440831ff, 0x1a404770, 0x48194770, 0xf990b510, 0x28030000, 0x2805d012, 0x2804d010, 
+    0x2101d00e, 0xf7eb4608, 0x0780f813, 0x2101d406, 0xf7eb2011, 0xb2c0f80d, 0xd0002800, 0xbd102001, 
+    0x22054c0d, 0x46202120, 0xfc53f00f, 0xd0f52800, 0x46202204, 0xf00f2110, 0x2801fc4c, 0x4807d0ee, 
+    0xfc1cf00f, 0xd1e92800, 0x1c804804, 0xfc16f00f, 0x0000e7e2, 0x00032238, 0xd003502c, 0xd03c80e6, 
+    0x4604b570, 0xea4048f9, 0x48f90144, 0xfc03f00f, 0x210048f7, 0xf00f3084, 0x48f6fbfe, 0xea404df4, 
+    0x357c3184, 0xf00f4628, 0x48f3fbf6, 0x20107801, 0xf83af7ec, 0xea4048f1, 0x46283184, 0xfbebf00f, 
+    0xbd702001, 0x210048ea, 0xf00fb510, 0xe8bdfbe4, 0xf0014010, 0xb510bcde, 0x4604b086, 0xfb26f001, 
+    0xd0222800, 0x308048e2, 0xfbd2f00f, 0x010bf3c0, 0xda022953, 0x31adf601, 0x3953e000, 0x0c810508, 
+    0x1d0048db, 0xfbc7f00f, 0x4ad92101, 0x90002000, 0x4623323c, 0x0102e9cd, 0x91059104, 0x5130f240, 
+    0x20019001, 0xf85ef7eb, 0xb0062001, 0xe92dbd10, 0x000741f0, 0xf8df48d2, 0x6805834c, 0xf998d103, 
+    0xf7ff0000, 0xf505ff9d, 0xf5057626, 0x463074a6, 0xffc1f7ff, 0xffb6f7ff, 0x46202200, 0x68334629, 
+    0xc0081c52, 0xb2126873, 0x2a533610, 0xdbf6c108, 0xd1032f01, 0x0000f998, 0xff82f7ff, 0x22012100, 
+    0xf8344608, 0xb10b3b02, 0xb2894311, 0x00521c40, 0xb212b200, 0xdbf42810, 0xf8df2200, 0xf8dfe2ec, 
+    0x3520c2ec, 0x20004690, 0x8002f80c, 0x030ff001, 0x1603f3c1, 0x0383eb0e, 0x0686eb0e, 0x30c0f8d3, 
+    0x6080f8d6, 0xf3c14433, 0xeb0e2603, 0x6c360686, 0x0b0e4433, 0x6026f85e, 0xf9354433, 0xeb036b02, 
+    0x429e03c3, 0x2301da01, 0x2300e000, 0x6002f81c, 0x7b02f814, 0x4087405f, 0x433e0849, 0xb2001c40, 
+    0x31c3ea41, 0x2808b289, 0x6002f80c, 0x4ba0dbce, 0x1c52549e, 0x2a10b212, 0xe8bddbc5, 0xb5f081f0, 
+    0xb0854e98, 0x46072500, 0x462c2101, 0xf6439500, 0xf996737a, 0x462a0000, 0xfba6f001, 0x21802001, 
+    0xe9cd2305, 0x90004001, 0xe9cd4618, 0xf9961403, 0x21072000, 0xfb59f001, 0xfa68f001, 0xf001b118, 
+    0x0005fa83, 0xb17fd110, 0x6480f04f, 0x11f4f240, 0xf7e44620, 0xf246fd36, 0x46206166, 0xfd20f7e4, 
+    0x46204984, 0xfd1cf7e4, 0xfc03f001, 0x24004e7f, 0xf0014620, 0xf846fa70, 0x1c640024, 0x2c04b264, 
+    0xb005dbf6, 0xbdf04628, 0x4ff3e92d, 0xb08b4874, 0xf6404689, 0x24100200, 0x90076800, 0x5180f500, 
+    0x49759109, 0x04498809, 0x719af1a1, 0x91061409, 0x91082100, 0x460e1e4d, 0x9f0b4688, 0x1504e9cd, 
+    0xf5074968, 0xf9916700, 0x99063000, 0x39161a79, 0xea4f2702, 0xeb017ce1, 0xf36f4c9c, 0xeba10c0d, 
+    0xf04f010c, 0xb2090c05, 0x1702e9cd, 0x2c00e9cd, 0x46612207, 0xfbc4f001, 0x22004860, 0x46934613, 
+    0x0000f990, 0x900a9202, 0x4f584610, 0x54392100, 0xb2001c40, 0xdbf82810, 0xeb094261, 0x30200004, 
+    0xe12b9003, 0x44089806, 0x98091907, 0x7017f830, 0x30fff04f, 0x0047eb00, 0xfa0f9f07, 0x980afa80, 
+    0x44204408, 0xc010f837, 0x0040eb07, 0x0c02f830, 0x0000ebac, 0xfa0f00c0, 0x2001f980, 0xea4f4f42, 
+    0xeb070c80, 0xfa231780, 0xfa22fe0c, 0xf00efc0c, 0xf00c0e0f, 0x1c400c0f, 0xe02ef837, 0xf837b200, 
+    0x2803702c, 0x0c07ebae, 0x0709eb0c, 0xf987fa0f, 0xf8dfdbe4, 0xf003e0d4, 0xf002070f, 0xf8cd0c0f, 
+    0xf83e9000, 0xf83e7027, 0xf00b002c, 0x1a3f0c0f, 0x0009eb07, 0xf980fa0f, 0xf0009802, 0xf83e070f, 
+    0xf83e002c, 0x1a3f7027, 0x45469800, 0xb2004438, 0xd9049000, 0x0008eba6, 0x0e00f04f, 0x2000e002, 
+    0x0e06eba8, 0x88374e26, 0xf60afb17, 0x9701b237, 0x0707eba9, 0x0609fb19, 0x0807fb07, 0x0700e9dd, 
+    0x1bc04691, 0xfb009f00, 0xfb17e000, 0x9f02ec07, 0x4566469e, 0xea4fd204, 0xea4f034e, 0xe0030249, 
+    0x4666007b, 0x024bea4f, 0xd22d4540, 0x0f01f1ba, 0x46504680, 0x2000d000, 0x3ffff1ba, 0x0047ea40, 
+    0xd01f9002, 0xea402000, 0xe02b004b, 0x20080038, 0xd1800404, 0x000c04e5, 0x0003227f, 0x000c14e5, 
+    0x00032218, 0x000323ac, 0x000330cc, 0x000331cc, 0x000351ec, 0xdcba01f5, 0x0003239a, 0x000323a2, 
+    0x000323a4, 0xe7de2001, 0x0f01f1ba, 0xd0004650, 0xf1ba2000, 0xea403fff, 0x9002004e, 0x2000d00a, 
+    0x0049ea40, 0x46834546, 0xfa23d20e, 0x07c0f004, 0xe001d105, 0xe7f32001, 0xf004fa22, 0x2001e00a, 
+    0xf04fe00a, 0xe00730ff, 0x40e09802, 0xd1f607c0, 0xf004fa2b, 0xd1f407c0, 0xda002800, 0x9f0b4240, 
+    0x1b3f440f, 0x7ce7ea4f, 0x6c1ceb07, 0x0cfff02c, 0x0e0ceba7, 0xc020f8dd, 0xd10145e6, 0x2000b178, 
+    0xdb3842a1, 0xc010f8dd, 0x0c5cea4f, 0x2001b100, 0x70c0ea4c, 0x98059004, 0xd0021c40, 0x2001e01b, 
+    0x9804e7ee, 0x4c27f5a0, 0x0cbbf1bc, 0xf643d113, 0x443870e1, 0x17c527bb, 0x4595eb00, 0x050df36f, 
+    0xb2001b40, 0x48e99005, 0x7007251f, 0x704727a7, 0x70872700, 0x1c6870c7, 0x2d80d00d, 0x48e4da09, 
+    0x28074028, 0x9804d105, 0x48e00e07, 0x00e5eb00, 0x1c6d7007, 0x9803b22d, 0xb2091c49, 0xdd024288, 
+    0xf6ff2d80, 0x9805aecf, 0xe8bdb00d, 0xe92d8ff0, 0x200043f8, 0x4dd84fd7, 0x90002200, 0x6680f507, 
+    0xf04f48d6, 0x463b34ff, 0x1000f990, 0xf7ea2001, 0x8838fa32, 0x20018030, 0x0240eb07, 0x1010f837, 
+    0x2c02f832, 0xb2091a89, 0xf8261c62, 0xd0051010, 0x460a2900, 0x4252da00, 0xdd054542, 0x46042900, 
+    0x4249da00, 0xf881fa0f, 0xb2001c40, 0xdbe32880, 0xda002c03, 0xea4f2403, 0xeb0601e8, 0xf9320244, 
+    0x28000c06, 0x4240da00, 0xdd014288, 0xe0101ee4, 0x0c04f932, 0xda002800, 0x42884240, 0x1ea4dd01, 
+    0xf932e007, 0x28000c02, 0x4240da00, 0xdd004288, 0x20001e64, 0x18c1b263, 0x1011f836, 0x1010f825, 
+    0xb2001c40, 0xdbf62811, 0x22004ead, 0x00c2eb05, 0x1008f9b0, 0x4006f9b0, 0x7002f9b0, 0xf9b04421, 
+    0x443c4004, 0xeb014421, 0xeb0604c1, 0x600c1182, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x443c7004, 
+    0x7002f9b0, 0xeb041be4, 0x604c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1be47004, 0x7002f9b0, 
+    0xeb04443c, 0x608c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1be47004, 0x7002f9b0, 0xeb041be4, 
+    0x60cc04c4, 0x4008f9b0, 0x7006f9b0, 0xc002f9b0, 0xf9b01be4, 0x44677004, 0xeb04443c, 0x610c04c4, 
+    0x4008f9b0, 0x7006f9b0, 0xf9b01be4, 0x443c7004, 0x7002f9b0, 0xeb041be4, 0x614c04c4, 0x4008f9b0, 
+    0x7006f9b0, 0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb04443c, 0x618c04c4, 0x4008f9b0, 0x7006f9b0, 
+    0xf9b01be4, 0x1be47004, 0x7002f9b0, 0xeb041be4, 0x61cc04c4, 0x4006f9b0, 0xf9b01c52, 0xb2127008, 
+    0xc002f9b0, 0xf9b01be4, 0x44677004, 0xeb04443c, 0x620c04c4, 0x4006f9b0, 0x7008f9b0, 0xf9b01be4, 
+    0x443c7004, 0x7002f9b0, 0xeb041be4, 0x624c04c4, 0x4006f9b0, 0x7008f9b0, 0xf9b01be4, 0x1be47004, 
+    0x7002f9b0, 0xeb04443c, 0x628c04c4, 0x4006f9b0, 0x7008f9b0, 0xf9b01be4, 0x1be47004, 0x7002f9b0, 
+    0xeb041be4, 0x62cc04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1b3c7004, 0x7002f9b0, 0xeb04443c, 
+    0x630c04c4, 0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x1b3c7004, 0x7002f9b0, 0xeb041be4, 0x634c04c4, 
+    0x4008f9b0, 0x7006f9b0, 0xf9b0443c, 0x443c7004, 0x7002f9b0, 0xeb041b3c, 0x638c04c4, 0x4008f9b0, 
+    0x7006f9b0, 0xf9b0443c, 0xf9b07004, 0x44380002, 0x42404420, 0xeb002a04, 0x63c800c0, 0xaf16f6ff, 
+    0x49388828, 0x00c0eb00, 0x80080040, 0x70034836, 0x83f8e8bd, 0xf7ffb510, 0x2002feaa, 0xfc1cf7eb, 
+    0xf2404604, 0xf6431100, 0xf7ff7060, 0x2002fd1d, 0xfc12f7eb, 0x1a20492d, 0x1000f9b1, 0xf0f1fbb0, 
+    0x6008492b, 0xe92dbd10, 0xf24041f0, 0xf7ff2500, 0x2400fe8e, 0x36fff04f, 0x6700f643, 0x0800f248, 
+    0x4629e02e, 0xf7ff4638, 0x1c41fcff, 0xf5a0d01e, 0xb200507e, 0x6480f04f, 0xeb000fc1, 0xf2403081, 
+    0xb20611f4, 0xf7e44620, 0x491afa0c, 0xf7e44620, 0x4919f9f7, 0xf7e44620, 0x4631f9f3, 0xf7e44620, 
+    0x4916f9ef, 0xf7e44620, 0xe00df9eb, 0x1c641979, 0xb22417c8, 0x4090eb01, 0x000df36f, 0xb2071a08, 
+    0xf0f5fb98, 0xdccc42a0, 0xe4864630, 0x000331cc, 0x80000007, 0x0003bdfc, 0x0003c7fc, 0x000323ac, 
+    0x000330cc, 0x000323a4, 0x000323a2, 0x00032420, 0x000323a8, 0xa5a55a5a, 0xdde50000, 0xdcba01f5, 
+    0x5c0849f8, 0x49f84770, 0x47f0e92d, 0x26007809, 0x250eb3f1, 0xb2834cf5, 0x0700f248, 0x4639220f, 
+    0xf00e4620, 0x2380ffb8, 0x31fff240, 0x46202200, 0xffb1f00e, 0x22002306, 0x1ca021ff, 0xffabf00e, 
+    0xf6412200, 0x217f73f8, 0xf00e1d20, 0xf1a4ffa4, 0x46390802, 0x46404644, 0xff83f00e, 0x0180f248, 
+    0xf00e4620, 0xf8dfff7e, 0x2400a384, 0x9380f8df, 0x0a0ef10a, 0x0204f04f, 0x01f0f04f, 0x0000f899, 
+    0x46502803, 0xf00ed009, 0x43c0ff94, 0xe0000700, 0xd01de001, 0x2507e006, 0xf00ee7bc, 0xea35ff8a, 
+    0xd0130000, 0x42bc1c64, 0x2301dbe4, 0x220a4644, 0x029d4640, 0xf00e4629, 0x2300ff6e, 0x220a4629, 
+    0xf00e4620, 0x4630ff68, 0x87f0e8bd, 0xe7ec2601, 0x46502200, 0xf00e210f, 0x49c6ff6c, 0x0201f000, 
+    0xf3c0700a, 0x704a0240, 0x0280f3c0, 0xf3c0708a, 0x70c800c0, 0x48bde7ea, 0xe92d2200, 0x303041f0, 
+    0x71fff643, 0xff55f00e, 0x4ebbb205, 0xd00e07e8, 0x46302301, 0x025c2209, 0xf00e4621, 0x2300ff3c, 
+    0x22094621, 0xf00e4630, 0x1e6dff36, 0xf240b22d, 0x24001700, 0x23014639, 0x22084630, 0xff2bf00e, 
+    0x46392300, 0x46302208, 0xff25f00e, 0x2c181c64, 0x49aadbf0, 0x005af105, 0x004cf3c0, 0xf7ec7809, 
+    0x4628fce4, 0x81f0e8bd, 0x43f0e92d, 0xb1434689, 0x4ca3b11a, 0x0584f1a4, 0x4ca2e00d, 0x0584f1a4, 
+    0xb122e009, 0x3ca84c9e, 0x0584f1a4, 0x4c9ce003, 0xf1a434a8, 0xf8900584, 0x6807e004, 0x2201b902, 
+    0x0c00f04f, 0x2300e01f, 0x46184619, 0xf600fa27, 0xd00707f6, 0x0820f1c0, 0x6008f814, 0xf8554073, 
+    0x40716028, 0xb2001c40, 0xdbef2820, 0x70ceea5f, 0x7820d003, 0x68284043, 0x469e4041, 0x0c01f10c, 
+    0xfa0f460f, 0x4594fc8c, 0xe9c9dbdd, 0xe8bd7e00, 0xe92d83f0, 0x468247fc, 0xf8df4883, 0x25019210, 
+    0x81f4f8df, 0x464a460f, 0x02a97001, 0xf00e4640, 0x4606ff8d, 0xf990487e, 0x28030000, 0x2802d017, 
+    0x2801d022, 0x4871d02d, 0xf00e3012, 0x9001fe97, 0x3014486e, 0xfe92f00e, 0x486c9000, 0xf00e3016, 
+    0x9900fe8d, 0xea402400, 0x90004001, 0x4867e02c, 0xf00e3024, 0x9001fe83, 0x30264864, 0xfe7ef00e, 
+    0x48629000, 0xe7ea3028, 0x301e4860, 0xfe76f00e, 0x485e9001, 0xf00e3020, 0x9000fe71, 0x3022485b, 
+    0x485ae7dd, 0xf00e3018, 0x9001fe69, 0x301a4857, 0xfe64f00e, 0x48559000, 0xe7d0301c, 0x22004669, 
+    0xf7ff4608, 0x1c64ff61, 0x42bc4653, 0x4669dbf6, 0x4608462a, 0xff58f7ff, 0xb2819800, 0x300a484b, 
+    0xfe4ff00e, 0x0c019800, 0x30084848, 0xfe49f00e, 0xb2819801, 0x1d804845, 0xfe43f00e, 0x0700f246, 
+    0x23004644, 0x220d4639, 0xf00e4640, 0x4849fe54, 0x3120f240, 0x0000f990, 0xd01e2804, 0xd01f2805, 
+    0x107af44f, 0x2210464b, 0xfb954345, 0x4621f0f1, 0x30201a30, 0xff1af00e, 0x46392300, 0x4620220d, 
+    0xfe39f00e, 0x22014835, 0x483b7803, 0x1000f9b0, 0xf7ec2000, 0xe8bdfcb4, 0xf44f87fc, 0xe7e1007a, 
+    0x00faf44f, 0x4a32e7de, 0xb570b283, 0x21ff4d27, 0x0400f248, 0x220f7011, 0x46284621, 0xfe1bf00e, 
+    0xf2402380, 0x220031ff, 0xf00e4628, 0x2306fe14, 0x21ff2200, 0xf00e1ca8, 0x2200fe0e, 0x73f8f641, 
+    0x1d28217f, 0xfe07f00e, 0x1eac4621, 0x46202301, 0xf00e220f, 0x2300fe00, 0x22064620, 0xf00e2140, 
+    0x2300fdfa, 0x22054620, 0xf00e2120, 0x2300fdf4, 0x22044620, 0xf00e2110, 0x2300fdee, 0x210f4620, 
+    0xf00e461a, 0x2300fde8, 0x22074620, 0xf00e2180, 0x4620fde2, 0x4070e8bd, 0x22072301, 0xf00e2180, 
+    0x0000bdda, 0x000323ac, 0x000323b4, 0xd0035094, 0x00032270, 0x000323b0, 0xd0035092, 0x0003227f, 
+    0x000328a0, 0x000329f0, 0x0003226b, 0xc800010c, 0x0003226a, 0x0003227e, 0x0003239a, 0x47f0e92d, 
+    0x46814efe, 0x28037830, 0x250fd00f, 0x83f0f8df, 0xf2482400, 0x22040700, 0x21f04640, 0xfdb9f00e, 
+    0xb2407831, 0xd0072903, 0x48f6e007, 0xb1087800, 0xe7eb250e, 0xe7e92507, 0xb9104028, 0x42bc1c64, 
+    0x2204dbe9, 0x21f04640, 0xfda3f00e, 0x48eeb204, 0xd5010721, 0xe00c2103, 0xd5010761, 0xe0082102, 
+    0xd50107a1, 0xe0042101, 0xd00107e1, 0xe0002100, 0x700121ff, 0x1c41b248, 0x49e4d004, 0x46485c09, 
+    0xfea7f7ff, 0xe60fb260, 0x4604b510, 0xff4bf7ff, 0xe8bd4620, 0xe7b14010, 0x4cddb510, 0x48db2100, 
+    0x2000f994, 0xf9945481, 0x21012001, 0xf9945481, 0x21022002, 0xf9945481, 0x21032003, 0xf9905481, 
+    0xf9903003, 0xf9902002, 0xf9901001, 0xf7ed0000, 0xf994f9ed, 0xf9943003, 0xf9942002, 0xf9941001, 
+    0xe8bd0000, 0xf7f24010, 0xb530bdc1, 0x2000b087, 0x9000aa04, 0x90029001, 0x48c69003, 0x1000e9d0, 
+    0x1004e9cd, 0x4668a902, 0xf918f7ee, 0x466b48c2, 0x28037800, 0x48bbd110, 0x1000f990, 0x2002f990, 
+    0x1011f833, 0x1012f823, 0x1001f990, 0x0003f990, 0x1011f833, 0x1010f823, 0x46082100, 0x2010f833, 
+    0xb2001c40, 0xb2094411, 0xdbf72804, 0x10881c89, 0x1000f9bd, 0xf0203840, 0x20010401, 0x2010f933, 
+    0xdd00428a, 0x1c404611, 0x2804b200, 0x4aabdbf6, 0xf0211c49, 0x88100101, 0xeb014243, 0xf5010143, 
+    0xb20d711f, 0xeba01b61, 0xb2010061, 0x801148a4, 0x78032201, 0xf7ec4628, 0xb007fb72, 0xbd304628, 
+    0x4ff0e92d, 0x499fb08b, 0x4e9f2000, 0xf10d4d97, 0x90000a08, 0x90034604, 0x1b00f240, 0x90029001, 
+    0x90059004, 0xf9919008, 0xf8df1000, 0x91078254, 0xaa049009, 0x4668a902, 0xf8b0f7ee, 0xf890488e, 
+    0xf1bee000, 0xd1100f03, 0xf9904886, 0xf9902000, 0xf83d3002, 0xf82d2012, 0xf9902013, 0xf9902001, 
+    0xf83d0003, 0xf82d2012, 0xf8962010, 0x2000c000, 0x4681af06, 0x0f01f1bc, 0xf807562a, 0xf93a9002, 
+    0xd0083010, 0x428b2140, 0xf93ddd09, 0x29801010, 0x2101da03, 0x4659e002, 0x2102e7f5, 0x1c4054b9, 
+    0x2804b2c0, 0x486dd3e6, 0x28037800, 0x2001d102, 0x001bf88d, 0x0f03f1be, 0xf89dd107, 0xf88d0018, 
+    0xf89d001a, 0xf88d0019, 0xf242001b, 0x06c80170, 0xfe93f7e3, 0x0900f44f, 0x11f4f240, 0xf7e34648, 
+    0x496afe80, 0xf7e34648, 0x4f61fe6b, 0x1003f997, 0x0000f997, 0x2001f997, 0x3001eb00, 0x1002f997, 
+    0xeb010209, 0x44011102, 0xf7e34648, 0x4860fe59, 0xfc44f00e, 0x46484601, 0xfe52f7e3, 0xf00e485d, 
+    0x4601fc37, 0xf7e34648, 0xf89dfe4b, 0xf89d101b, 0xf89d0018, 0xeb002019, 0xf89d3001, 0x0209101a, 
+    0x1102eb01, 0x46484401, 0xfe3af7e3, 0x0018f89d, 0x1019f89d, 0x2900b158, 0x101af89d, 0xb301d001, 
+    0x2900e022, 0x101bf89d, 0xb139d015, 0xb151e01c, 0x101af89d, 0xf89db9d1, 0xb168001b, 0x78797838, 
+    0x70787039, 0xf89de022, 0x2800001a, 0x001bf89d, 0xb908d01b, 0xb939e01a, 0x78797838, 0x70787039, 
+    0xf89de02a, 0xb189101b, 0xd0142802, 0x1019f89d, 0xd0102902, 0x201af89d, 0xd00c2a02, 0x301bf89d, 
+    0xd0082b02, 0xd1172801, 0xb1a8e010, 0x78f978b8, 0x70f870b9, 0x4829e010, 0xf8982201, 0xf9b03000, 
+    0xf06f1000, 0xf7ec000f, 0xe005fa7a, 0xd1032901, 0xd1012a01, 0xd0122b01, 0x46484927, 0xfde0f7e3, 
+    0xfe7af7ff, 0x28017830, 0xf9904817, 0x5c290000, 0x4822d003, 0x28017800, 0x2001d009, 0x491ee008, 
+    0x0000f44f, 0xfdccf7e3, 0x90092001, 0x2000e00d, 0xfcfff7ff, 0x1000f898, 0x2080f44f, 0xfff4f7ea, 
+    0xb2241c64, 0xf6ff2c03, 0xf995aef4, 0xac040003, 0xf640220b, 0xf8340100, 0xe0213010, 0x00032270, 
+    0xd00350a2, 0x000323b4, 0x0003226a, 0x000323b8, 0x000323ac, 0x0002e184, 0x00032411, 0x0003239a, 
+    0x0003227f, 0x00032283, 0x000322e4, 0x77777776, 0xd0030446, 0xd180000c, 0xdcba01f5, 0x00032396, 
+    0x9244f8df, 0x0988f1a9, 0x4648464e, 0xfb93f00e, 0x0002f995, 0xf240220a, 0xf8344100, 0x46303010, 
+    0xfb89f00e, 0x0001f995, 0xf2402209, 0xf8342100, 0x46303010, 0xfb7ff00e, 0x0000f995, 0x46592208, 
+    0x3010f834, 0xf00e4630, 0xf995fb76, 0xf6470001, 0xf9957a00, 0x466c2002, 0x1010f83d, 0x0000f995, 
+    0x2012f83d, 0x0010f83d, 0xf9951a17, 0x1a092003, 0x4651b28b, 0x2012f83d, 0x22081a16, 0x0002f109, 
+    0xfb59f00e, 0xf109b2bb, 0x22000704, 0x217f4638, 0xfb51f00e, 0x4651b2b3, 0x46382208, 0xfb4bf00e, 
+    0xf9964e6a, 0x5c280000, 0xf9962800, 0x5c280002, 0x2802d003, 0x2300d005, 0x2802e006, 0x2301d003, 
+    0x2302e002, 0x2303e000, 0x22064648, 0xf00e21c0, 0x9809fb32, 0xd07d2800, 0xfde7f7ff, 0xf7eb2000, 
+    0x4d5bfbc1, 0x28017828, 0xf7ebd00c, 0xf04fff70, 0xf2424a00, 0x46490970, 0xf7e34650, 0x7828fd2e, 
+    0xe015b118, 0xff17f7eb, 0x2100e7f1, 0xf7ed2001, 0x4f50fc26, 0x200c2100, 0x2000f997, 0xf972f7ed, 
+    0xf9972101, 0x46082000, 0xf9b2f7ed, 0xfe64f7f2, 0x46504649, 0xfd11f7e3, 0xfad5f7ff, 0x1c78b207, 
+    0x2001d07d, 0x20009008, 0xfb8cf7eb, 0xd00a07f8, 0x22014841, 0x3000f898, 0x1000f9b0, 0xf7ec4610, 
+    0x1c7ff96e, 0xf898b23f, 0x10781000, 0xf7ec4647, 0x783bf8ac, 0x4f382201, 0xf9b72000, 0xf7ec1000, 
+    0xaa04f95e, 0xa9024668, 0xfeb8f7ed, 0x78004833, 0xd10f2803, 0x0000f996, 0x1002f996, 0x0010f834, 
+    0x0011f824, 0x0001f996, 0x1003f996, 0x0010f834, 0x0011f824, 0x1000f9bd, 0xf9342001, 0x428a2010, 
+    0x4611da00, 0xb2c01c40, 0xd3f62804, 0xb2083908, 0xe0008839, 0xeba1e033, 0x38550060, 0x2201b200, 
+    0xf7ec2100, 0x2074f89e, 0xfaf2f7ed, 0x1000f898, 0x0000f640, 0xfec8f7ea, 0x28017828, 0x4815d016, 
+    0x0000f990, 0x1cc09007, 0xeb0017c1, 0xf0217191, 0x1a400103, 0xf7f2b240, 0xf7ebff96, 0x4649fed8, 
+    0xf7e34650, 0x7828fc9a, 0xe005b118, 0xfe50f7eb, 0x9807e7f5, 0xff87f7f2, 0xf7eb2001, 0x9808fb13, 
+    0xe8bdb00b, 0x00008ff0, 0xd00350a2, 0x000323b4, 0x00032396, 0x00032283, 0x0003239a, 0x00032411, 
+    0x5ff0e92d, 0xa214f8df, 0xf8dd2a05, 0xf89a9028, 0xf0066000, 0xd0040601, 0xd0022a04, 0xd00e2a03, 
+    0x2b01e012, 0x2b02d009, 0x4a7dd007, 0x78124b7d, 0x4313781b, 0x2a03d001, 0x1c80d106, 0x4a7ae003, 
+    0xb90a7812, 0xb2401c40, 0xb1112701, 0x0040eb07, 0x0040e000, 0x280cb240, 0x2400da03, 0x050cf1c0, 
+    0xf1a0e014, 0x290c010c, 0x2401d203, 0x0518f1c0, 0xf1a0e00c, 0x290c0118, 0x2402d203, 0x0524f1c0, 
+    0x2824e004, 0x2403db02, 0x0530f1c0, 0xb19cf8df, 0x46d82101, 0xf00e4658, 0x4864fa04, 0xf00e3016, 
+    0x07c0f9fd, 0x2100d010, 0xf00e4640, 0x2e00f9fa, 0xf7e3d0ee, 0xf000fb31, 0xfa07010f, 0x495cf001, 
+    0xf7ea7809, 0xe7e3fe31, 0xf04f4858, 0xf8df0200, 0xf04f815c, 0x30140101, 0xf1a82e00, 0xd0720804, 
+    0xfa07f00e, 0x0100ea27, 0xf00e4640, 0x4e51f9da, 0x22072300, 0x46302180, 0xf9edf00e, 0x1800f240, 
+    0x23004630, 0x22084641, 0xf9e5f00e, 0xf04fb2a3, 0xf1b90200, 0xf04f0f01, 0xd0580103, 0xf00e4846, 
+    0x4845f9da, 0x2200b2a3, 0x1c802103, 0xf9d3f00e, 0xb2a34841, 0x21032200, 0xf00e1d00, 0x483ef9cc, 
+    0x2200b2a3, 0x1d802103, 0xf9c5f00e, 0xb2ab483a, 0x210f2200, 0xf00e302e, 0x4f38f9be, 0x2202b2a3, 
+    0x4638210c, 0xf9b7f00e, 0x4638b2a3, 0x21032200, 0xf9b1f00e, 0xb2a31cbf, 0x22024638, 0xf00e210c, 
+    0xb2a3f9aa, 0x22004638, 0xf00e2103, 0xb2abf9a4, 0x210f2200, 0xf00e1cb8, 0xf99af99e, 0xb3a80000, 
+    0xd0342802, 0x46412301, 0x46302208, 0xf993f00e, 0x46582100, 0xf975f00e, 0x0f01f1b9, 0xe8bdd12b, 
+    0xf7eb5ff0, 0xf00ebf4b, 0x4601f994, 0x481ae78c, 0xf00e3008, 0x4818f980, 0x2200b2a3, 0x300a2103, 
+    0xf979f00e, 0xb2a34814, 0x21032200, 0xf00e300c, 0x4811f972, 0x2200b2a3, 0x300e2103, 0xf96bf00e, 
+    0x2200480d, 0xb2ab210f, 0xe7c43030, 0x2301e7ff, 0x21802207, 0xe8bde7c9, 0x00009ff0, 0x00032228, 
+    0x00032411, 0x00032372, 0x00032270, 0xd003400e, 0x0003227f, 0xd003e834, 0xd0034200, 0xd003900e, 
+    0x47f0e92d, 0x48334606, 0x468a4f33, 0x90c8f8df, 0x80c8f8df, 0x78003f16, 0xf0002501, 0x46380401, 
+    0xf00e2101, 0x4648f91e, 0xf918f00e, 0xd01007c0, 0x46382100, 0xf915f00e, 0xd0f02c00, 0xfa4cf7e3, 
+    0x010ff000, 0xf001fa05, 0x1000f898, 0xfd4cf7ea, 0x4821e7e5, 0x0200f04f, 0x807cf8df, 0x0101f04f, 
+    0x907cf8df, 0xf1a81e80, 0xb33c081a, 0xf921f00e, 0x0100ea25, 0xf00e4640, 0x08b3f8f4, 0x21072200, 
+    0x0002f109, 0xf907f00e, 0xf24c220e, 0xf0060100, 0x46480303, 0xf8fff00e, 0x46382100, 0xf8e1f00e, 
+    0x22044810, 0x46532170, 0xf8f5f00e, 0x480e4653, 0x47f0e8bd, 0x21702204, 0xb8edf00e, 0xf8f9f00e, 
+    0x46404601, 0xf8cdf00e, 0x46332209, 0x6100f643, 0x0000e7df, 0x00032228, 0xd0034024, 0x0003227f, 
+    0xd003e832, 0xd003c012, 0xd003d012, 0x4cfeb510, 0xf7eae002, 0xb160fcb7, 0xf00e4620, 0x0300f8a9, 
+    0x0002f04f, 0xf7ead4f5, 0x49f8fca7, 0x20016008, 0x4cf7bd10, 0xf00e4620, 0xf040f8a1, 0x46200110, 
+    0xf89ff00e, 0xbd102000, 0xb51048ef, 0xf00e1d00, 0x0fc0f88f, 0x49ecbd10, 0x0003f1c0, 0xeb01310c, 
+    0xf00e0080, 0xe92db885, 0xf8df41f0, 0x108d839c, 0x4604b086, 0x0840f1a8, 0x2b01b133, 0x2b02d014, 
+    0x2b03d06e, 0xe0a8d06f, 0x90052000, 0x90042201, 0x46239000, 0xe9cd9001, 0x00880202, 0xb2014642, 
+    0xf7e92001, 0xe098fd0f, 0xf04f2a07, 0xd0540600, 0x0745eb05, 0x4640e019, 0xf85af00e, 0x0026f844, 
+    0xf00e4640, 0x1971f855, 0x0021f844, 0xf00e4640, 0xeb06f84f, 0xf8440145, 0x46400021, 0xf848f00e, 
+    0x1c7619b9, 0xf844b236, 0x42ae0021, 0xe074dbe3, 0x46404647, 0xf83cf00e, 0x0202f000, 0x0101f000, 
+    0x31c2ea41, 0x1026f844, 0x0108f000, 0x0280f3c0, 0x3141ea42, 0xf8441972, 0xf0001022, 0xf3c00120, 
+    0xea421200, 0xeb0621c1, 0xf8440245, 0xf0001022, 0xf3c00180, 0xea401080, 0xeb052041, 0x44310145, 
+    0x0021f844, 0xf00e4638, 0x4638f813, 0xf810f00e, 0xf00e4638, 0x1c76f80d, 0x42aeb236, 0xe03cdbc8, 
+    0x46472600, 0xe015e013, 0xf00e4638, 0x1971f801, 0x0021f844, 0xf00d4638, 0xf844fffb, 0x46380026, 
+    0xfff6f00d, 0xf00d4638, 0x1c76fff3, 0x42aeb236, 0xe022dbea, 0x463e2700, 0x4640e01d, 0xffe8f00d, 
+    0x0027f844, 0x46401c7f, 0xf00db23f, 0xf844ffe1, 0x1c7f0027, 0xb23f4640, 0xffdaf00d, 0x0027f844, 
+    0x46401c7f, 0xf00db23f, 0xf844ffd3, 0x1c7f0027, 0xb23f1c76, 0x42aeb236, 0xb006dbdf, 0x2100488a, 
+    0xe8bd387c, 0xf00d41f0, 0xe92dbfc6, 0x27005ff0, 0x2b0b4698, 0xe9dd4692, 0xf8dd6b0d, 0x460c902c, 
+    0xd1044605, 0x46494880, 0xf00d301c, 0x1c60ffb4, 0x2c07d007, 0x2d05d106, 0x2d06d001, 0x2701d102, 
+    0x2400e000, 0xdd022e00, 0x1e401070, 0x4876b206, 0x30084631, 0xff9ff00d, 0xea4f980c, 0xea41718b, 
+    0xea417109, 0x980a5100, 0x40c0ea41, 0x4187ea40, 0x318aea41, 0x2088ea41, 0x1144ea40, 0x4329486a, 
+    0x5ff0e8bd, 0xbf87f00d, 0x460db570, 0x9c041059, 0xea410409, 0xea411142, 0xea4101c5, 0xf0400040, 
+    0x48610110, 0xf00d387c, 0x2c00ff76, 0x485ed006, 0xe8bd4621, 0x38784070, 0xbf6df00d, 0xb570bd70, 
+    0x48594606, 0x460d4614, 0xf6402200, 0x1d0071ff, 0xff78f00d, 0xb925b12e, 0x0064ebb0, 0xf500d501, 
+    0xf6436040, 0xe8bd71ff, 0x00834070, 0x2200484e, 0xf00d3878, 0xb5f0bf59, 0x56614c4e, 0x29013c10, 
+    0x2910d011, 0x2501da0f, 0x408d1e49, 0xf04f6065, 0x408d35ff, 0x6021b2a9, 0x040989a1, 0x892160e1, 
+    0x60a10409, 0x2100e001, 0x68676061, 0x2f00b132, 0x6826d01c, 0xe9d42100, 0xe0264502, 0xd0152f00, 
+    0x21006826, 0x4502e9d4, 0xf850e00d, 0x423a2021, 0x4332d002, 0x2021f840, 0xd002422a, 0xf8404322, 
+    0x1c492021, 0xebb1b209, 0xdbee0f43, 0xf850bdf0, 0x423a2021, 0x4332d002, 0x2021f840, 0xd002422a, 
+    0xf8404322, 0x1d092021, 0xebb1b209, 0xdbee0f43, 0x4825bdf0, 0x22032301, 0x30482108, 0xbf04f00d, 
+    0x4fffe92d, 0xf04fb081, 0x46980900, 0x460d4614, 0x0a01f04f, 0x464f9e0e, 0xb00fe9dd, 0x7f80f5b6, 
+    0x9000f8cd, 0x4430dc01, 0xf1bbb200, 0xd0050f05, 0x1c612000, 0x2c07d00e, 0xe00cd006, 0xf04f1040, 
+    0xf04f0901, 0xe7f40a00, 0xd0012d05, 0xd1022d06, 0xe0072701, 0x490f2400, 0x5d49310b, 0xd1012901, 
+    0x0800f04f, 0xea410401, 0xea411149, 0xf0400048, 0x48050118, 0xf00d387c, 0x4803febe, 0x30089900, 
+    0xfeb9f00d, 0xe00704b9, 0xd1800480, 0x0003226c, 0xd003517e, 0x00032a24, 0x3088ea41, 0x1144ea40, 
+    0x4329488e, 0x488e4301, 0xfea5f00d, 0x7801488d, 0x4000f240, 0xfae8f7ea, 0x700aea4f, 0x4187ea40, 
+    0x3188ea41, 0x208bea41, 0x1044ea40, 0xf4404328, 0x48832100, 0xfe8ff00d, 0xfdd8f7ff, 0xd0182800, 
+    0xf00d4881, 0xb204fe8b, 0x46329900, 0xf7ff4648, 0x0070ff16, 0xb2019b11, 0x462a9801, 0xfdf3f7ff, 
+    0xff77f7ff, 0x46339801, 0x4629463a, 0xff23f7ff, 0xb0054620, 0x8ff0e8bd, 0x4fffe92d, 0x4607b083, 
+    0x20004c72, 0x461d221d, 0x8613e9dd, 0xa911e9dd, 0xb040f8dd, 0x4160f04f, 0x20059002, 0x9001463b, 
+    0xf00d4620, 0x486afe61, 0x0100f24c, 0x0000f990, 0xd0042803, 0xd0042805, 0xd0042804, 0x2300e008, 
+    0x2301e002, 0x2302e000, 0x220e4620, 0xfe4cf00d, 0x9b04220c, 0x02914620, 0xfe46f00d, 0x22189b02, 
+    0x51f8f04f, 0xf00d4620, 0x9b01fe3f, 0xf44f2210, 0x4620017f, 0xfe38f00d, 0xd0052f07, 0x9b052208, 
+    0x01514620, 0xfe30f00d, 0x23014c50, 0x21202205, 0xf00d4620, 0x2301fe29, 0x22044620, 0xf00d2110, 
+    0x4847fe23, 0x3048211f, 0xfe15f00d, 0x1d004844, 0xfe0ef00d, 0x21004842, 0xf00d3880, 0x4c40fe0c, 
+    0x3c782100, 0xf00d4620, 0xf5c5fe06, 0x46205140, 0xfe01f00d, 0xf240483a, 0xf00d11ad, 0x1f24fdfc, 
+    0x46202118, 0xfdf7f00d, 0x46202119, 0xfdf3f00d, 0x0000f44f, 0xe0079000, 0x21064a33, 0x325e4668, 
+    0xfaacf7ea, 0xd0042801, 0xf00d4620, 0x07c0fde1, 0x482bd1f2, 0xf00d3878, 0xebc5fddb, 0xe0010180, 
+    0x5140f501, 0xdbfb2900, 0x0400f243, 0xdb0242a1, 0x5140f5a1, 0x4822e7fa, 0xf00d3878, 0x4820fdcc, 
+    0x3048211f, 0xfdc7f00d, 0x1d00481d, 0xfdc0f00d, 0x2300481e, 0xf04f221d, 0xf00d4160, 0x481bfdc5, 
+    0x220c2300, 0xf00d4621, 0x2f07fdbf, 0x2208d005, 0x23004816, 0xf00d0151, 0x4f11fdb7, 0x3f402400, 
+    0x4638e017, 0xfda4f00d, 0x5201f3c0, 0x2014f82b, 0x3203f3c0, 0x2014f82a, 0x2203f3c0, 0x2014f829, 
+    0x1203f3c0, 0x000ff000, 0x2014f828, 0x0014f826, 0x42ac1c64, 0xb007d3e5, 0x0000e71c, 0x00080400, 
+    0xd1800480, 0x0003227f, 0xd0035120, 0xd1800800, 0x0003227e, 0x4ff0e92d, 0x2000b089, 0x48fe9007, 
+    0x20099005, 0x48fd9004, 0x49fd6804, 0x49fd9106, 0xf8df9408, 0x7809b3f4, 0xd10a2904, 0x1000f89b, 
+    0xd1062903, 0x784949f9, 0xd0022901, 0x1c8949f4, 0xf8df9106, 0x22b183dc, 0x21014ff7, 0xf5044ef5, 
+    0xf5045a80, 0xf8c859c0, 0x46352000, 0x0000f997, 0xf8b7f7f2, 0x0000f997, 0xff92f7f1, 0xf8c821b2, 
+    0x20001000, 0xff36f7f1, 0xf7f22002, 0xf997f992, 0xf7f10000, 0x2100ff36, 0x0000f244, 0xff87f7f1, 
+    0x0000f997, 0xfee4f7f1, 0xf44f2100, 0xf7ea2000, 0x21b3f97b, 0x23c048e1, 0x1000f8c8, 0xf2402200, 
+    0xf00d11ff, 0xf997fd48, 0xf7f10000, 0x48d6ffc1, 0x0800f04f, 0x78004fda, 0xd03a2803, 0x21012300, 
+    0xe9cd461a, 0x46087800, 0xfd2ef7e8, 0x48cb2101, 0xf2402305, 0x028a2b00, 0xb000f8cd, 0xe9cd9103, 
+    0x1e8a3201, 0x460b6800, 0xf7ff2105, 0x48c6fe09, 0x0100f04f, 0x28037800, 0xd0234608, 0x46dc4abf, 
+    0xf9336813, 0x2a002011, 0x4252da00, 0xb2091c49, 0x44104561, 0x1240dbf5, 0x28102100, 0x1c49dd04, 
+    0xb2491040, 0xdbf82906, 0x780048be, 0xd01b2803, 0x48b6e01b, 0xe9cd2300, 0x461a7800, 0x1001f990, 
+    0xe7c12001, 0x46dc4ab1, 0xf9929b08, 0xeb032001, 0xf9332382, 0x2a002011, 0x4252da00, 0xb2091c49, 
+    0x44104561, 0xe7d6dbf5, 0x20002105, 0x2010f937, 0xf825410a, 0x1c402010, 0x2880b200, 0x4fa4dbf6, 
+    0x230020b4, 0x4619461a, 0x20016038, 0x5800e9cd, 0xfccaf7e8, 0x603820b5, 0x21012300, 0xe9cd461a, 
+    0x46085800, 0xfcc0f7e8, 0x603820b6, 0x21022300, 0x2001461a, 0x5800e9cd, 0xfcb6f7e8, 0x603820b7, 
+    0x21032300, 0x2001461a, 0x5800e9cd, 0xfcacf7e8, 0x464120b8, 0x20006038, 0x1020f846, 0xb2001c40, 
+    0x7f00f5b0, 0x2500dbf8, 0xf7ea2002, 0x4f8cf885, 0x3f204623, 0x20b961f8, 0x3105eb00, 0x60014884, 
+    0x0000f640, 0x21019000, 0x9a06487d, 0xf00e3846, 0x2002fb9b, 0xf870f7ea, 0xf64069f9, 0xf8df0200, 
+    0x1a08b208, 0x210061f8, 0x0814f10b, 0x1025f84b, 0xf8281e49, 0x21001015, 0xf8544608, 0x1c403020, 
+    0x4290b200, 0xdbf84419, 0x200012c9, 0x3020f854, 0xf8441a5b, 0x1c403020, 0x4290b200, 0x4869dbf6, 
+    0x0000f990, 0xd0082804, 0xd0082805, 0x22042700, 0x40ba2000, 0x6300f5c2, 0x2702e012, 0x2701e7f7, 
+    0xeb00e7f5, 0xf8540e01, 0x1c49c020, 0xf854b209, 0x44f4e02e, 0xc020f844, 0xdcf2428a, 0xb2001c40, 
+    0x0100f04f, 0xdcf74283, 0xf1c72000, 0xe0090e06, 0xc021f854, 0xb2094411, 0xfc0efa0c, 0xc020f844, 
+    0xb2001c40, 0xdcf3428b, 0xf2402100, 0x42902200, 0xf844da04, 0x1c401020, 0xe7f8b200, 0x464b20ba, 
+    0x3105eb00, 0x4652484a, 0xe9dd6001, 0xe9cd1004, 0x99070100, 0xf00d4620, 0x20bbfd31, 0xeb00465b, 
+    0x48433105, 0x070cf1c7, 0x200e6001, 0x2020f85a, 0x1020f859, 0x4352413a, 0xfb014139, 0xf8442101, 
+    0xf8561020, 0xeb022020, 0xf84601e1, 0xf8541020, 0xf8531020, 0x42912025, 0xf843dd03, 0xf8281025, 
+    0x1c400015, 0x28c3b200, 0xf938dbe0, 0x1e481015, 0x0c81eb04, 0x3021f854, 0x2020f854, 0xf8dc4408, 
+    0xf04fc004, 0xeba24120, 0x44670743, 0x12bb1ad2, 0xf2f3fb92, 0xeb022300, 0x4a292040, 0xfba03a20, 
+    0xea4f7e01, 0x61907ce0, 0xfb0c69d2, 0xfb00e101, 0x17d31103, 0xf00c4638, 0xf8dfed3c, 0xf04f808c, 
+    0x18804240, 0x0828f1a8, 0x31fff141, 0x07c5eb08, 0x3b00f44f, 0x0100e9c7, 0xf858481c, 0xf8401035, 
+    0xf2401025, 0x46581103, 0xfdbbf7e2, 0x79396838, 0xea400c00, 0xb2814001, 0xf7e24658, 0xf838fda1, 
+    0xb2810035, 0xf7e24658, 0x20bcfd9b, 0x3105eb00, 0x1c6d4807, 0xe01bb26d, 0x0002e910, 0x00032218, 
+    0xd003044c, 0x0003227e, 0x00032411, 0x000323b4, 0x000324d0, 0x0003bdfc, 0x00032283, 0xd0030864, 
+    0x00032a5c, 0x00032270, 0x00040298, 0x00033054, 0x60012d05, 0xaed8f6ff, 0x0228f108, 0x0314f102, 
+    0x1e682500, 0x80186015, 0xf856200e, 0xf8441020, 0xf8561020, 0xf8521020, 0x42b97025, 0xf842dd03, 
+    0xf8231025, 0x1c400015, 0x28c3b200, 0xf933dbed, 0x1e410015, 0x0480eb04, 0x3020f856, 0xf8564408, 
+    0x68642021, 0x0643eba2, 0x1ad24434, 0xfb9212a3, 0x4bfdf2f3, 0xeb022400, 0x61992140, 0x4220f04f, 
+    0xfba117ce, 0xfb060702, 0xfb017202, 0x69da2104, 0xf00c17d3, 0x4ef5ecae, 0x4240f04f, 0x4ff51880, 
+    0x31fff141, 0x04c5eb06, 0x3800f44f, 0x0100e9c4, 0xf85648ef, 0x61411035, 0xf24020bd, 0x60381103, 
+    0xf7e24640, 0x6820fd2e, 0x0c007921, 0x4001ea40, 0x4640b281, 0xfd14f7e2, 0x0035f836, 0x4640b281, 
+    0xfd0ef7e2, 0x0035f836, 0xb2017922, 0x0c006820, 0x4002ea40, 0xf7f1b200, 0x20befd3a, 0x48de6038, 
+    0x0000f990, 0xfc94f7f1, 0x603820bf, 0x2001b009, 0x4ff0e8bd, 0xbc86f7e8, 0x4ffee92d, 0x48d72500, 
+    0x462c2101, 0x9502462a, 0xfaecf00d, 0x28014ed2, 0x2301d009, 0x31fef240, 0x0000f996, 0xf7f12200, 
+    0xe8bdfce0, 0x22088ffe, 0x015148cd, 0xfaf1f00d, 0x23002208, 0xfa4f0151, 0x48c9fb80, 0xfadbf00d, 
+    0xf04f48c8, 0x4fc8090a, 0x0301f04f, 0x831cf8df, 0x0200f04f, 0x28017800, 0xe9cdd04b, 0xf9968700, 
+    0x20011000, 0xfb55f7e8, 0xc308f8df, 0xf8df2000, 0x4643a300, 0x0850f10c, 0xe030f85c, 0x1010f93a, 
+    0x2011f937, 0x1011f933, 0x2e0efba2, 0xf8581955, 0xf1002030, 0xb2c00001, 0x1202fba1, 0x4548190c, 
+    0x48b5d3ea, 0xf9961b2c, 0xf04f1000, 0x4fa60500, 0x0203f04f, 0x4021f840, 0xf04f6978, 0xf1000138, 
+    0x61780001, 0xf00d48ad, 0x2800faa4, 0xf8dfd07e, 0x23038290, 0xf1082202, 0x210c08c4, 0xf00d4640, 
+    0xf8dffa8a, 0xf44f927c, 0x90020000, 0x0956f109, 0x4899e09b, 0x8700e9cd, 0x1000f990, 0xf7e82001, 
+    0x2400fb08, 0x826cf8df, 0xf10821c9, 0xfb190850, 0x4897fa01, 0x3a284a97, 0x1014f930, 0xf8304893, 
+    0xf8220011, 0x4a900014, 0x5011f832, 0xfb114a91, 0x3a14f10a, 0x5014f822, 0xf200fb10, 0x2205fb15, 
+    0x2302fb81, 0x200004c1, 0x461f4616, 0xebc0f00c, 0x48880c02, 0x4201ea42, 0x1409463b, 0x00c4eb00, 
+    0x2100e9c0, 0x463204e9, 0xf00c2000, 0x0c02ebb2, 0x4201ea42, 0x00c4eb08, 0x1c641409, 0x454cb2e4, 
+    0x2100e9c0, 0x4c74d3c5, 0xf9942100, 0xf7f10000, 0x4974fd78, 0x23012000, 0x7008461a, 0xf9944601, 
+    0xf7f10000, 0x4875fc1e, 0x21382203, 0xfa31f00d, 0xd0322800, 0x23034c6a, 0x34c42202, 0x4620210c, 
+    0xfa19f00d, 0xf44f4d66, 0xe0000100, 0x3556e069, 0xe0069102, 0x462a210a, 0xf7e9a802, 0x2801feaf, 
+    0x2202d006, 0x210c4620, 0xfa13f00d, 0xd1f12800, 0x30cc485b, 0xf9e2f00d, 0x81604c53, 0x30ca4858, 
+    0xf9dcf00d, 0x485681a0, 0xf00d30d4, 0x81e0f9d7, 0x30d24853, 0xf9d2f00d, 0xe0758220, 0x464a210b, 
+    0xf7e9a802, 0x2801fe8b, 0x2202d006, 0x210c4640, 0xf9eff00d, 0xd1f12800, 0x30cc4849, 0xf9bef00d, 
+    0x48478078, 0xf00d30ca, 0x80b8f9b9, 0x30d44844, 0xf9b4f00d, 0x484280f8, 0xf00d30d2, 0xb200f9af, 
+    0xf9b78138, 0xf9b71002, 0x4291200a, 0xf9b7d10f, 0xf9b72004, 0x429a300c, 0xf9b7d109, 0xf9b72006, 
+    0x429a300e, 0xf9b7d103, 0x42902010, 0x697ad003, 0x1e522501, 0x8179617a, 0x81b988b9, 0x81f988f9, 
+    0x17e38238, 0x46229500, 0x0000f996, 0xfe2ff7f1, 0x0200f248, 0x10510055, 0xdd152c00, 0xdd0f4294, 
+    0x2200482f, 0xf00d213f, 0x281af9a4, 0xf240d202, 0xe00111ff, 0x31fef240, 0xdc0f42ac, 0xe00d0849, 
+    0xdd08428c, 0xe0092103, 0x42904260, 0x42a8dd05, 0x2105dd01, 0x2102e002, 0x2100e000, 0x0000f996, 
+    0x461a2301, 0xfb6df7f1, 0x48152208, 0xf38bfa1f, 0xf00d0151, 0xe684f970, 0x4ff0e92d, 0xf44fb089, 
+    0x90023000, 0x48171084, 0xf948f00d, 0x0003f010, 0x0100f241, 0x2801d005, 0x2802d026, 0x2803d028, 
+    0x9102d027, 0x0000e025, 0x00032a3c, 0x00040270, 0x00033054, 0x000324d0, 0x00032283, 0xd1800000, 
+    0xd0035126, 0x00032281, 0x00035a7c, 0x0003527c, 0x0002e09c, 0x0003ff28, 0x00033044, 0xd28f007c, 
+    0xd0034200, 0xd003086e, 0x0000f244, 0xe0009002, 0x22009402, 0x21019802, 0x70d0eb00, 0x90071040, 
+    0xf00d489b, 0x2801f91f, 0x489ad174, 0x0b0af04f, 0x28017800, 0x2400d005, 0x78004897, 0xd1712800, 
+    0xf8dfe06b, 0x2500a258, 0x21004895, 0x1045eb00, 0xf8f7f00d, 0x20004993, 0x22002301, 0x0015f821, 
+    0xf8304891, 0x1c491015, 0x1015f820, 0x4618498f, 0x1a00e9cd, 0xf7e8b269, 0x2400f98c, 0x488ce03f, 
+    0x4a8c23c9, 0x1014f930, 0xf8304888, 0xf8220011, 0x32140014, 0x6011f83a, 0x6014f822, 0xf203fb1b, 
+    0xf102fb11, 0xf200fb10, 0x2206fb16, 0x7302fb81, 0x200004c1, 0x463a4698, 0xea4af00c, 0x0c024b7d, 
+    0x0985eb05, 0xea423328, 0xeb034201, 0x46431009, 0xeb001409, 0xe9c000c4, 0x04f12100, 0x2000463a, 
+    0xea36f00c, 0x4b740c02, 0x4201ea42, 0x1009eb03, 0xeb001409, 0x1c6400c4, 0xe9c0b2e4, 0x455c2100, 
+    0x1c6dd3bd, 0x2d04b2ed, 0x4862d39e, 0x70012100, 0x7001486a, 0xe8bdb009, 0x48698ff0, 0x0000f990, 
+    0xd0784284, 0x78004867, 0xd0f32801, 0x78004866, 0xd0ef2801, 0x78004865, 0xd0eb2801, 0x23014e57, 
+    0xb2614d5a, 0x468a2200, 0xe9cd4618, 0xf7e85600, 0x4d58f920, 0xeb042000, 0x46010384, 0x46813528, 
+    0x1503eb05, 0x4d549508, 0x46804602, 0x1303eb05, 0xe02a9301, 0x4f499b08, 0x03c0eb03, 0x5600e9d3, 
+    0xf9334b4b, 0x93003010, 0x3013f937, 0xce03fba5, 0xfb0617df, 0xfb05e303, 0xeb1c3307, 0x4f430909, 
+    0x9b014159, 0x03c0eb03, 0x5600e9d3, 0xf9379b00, 0xfba53013, 0x17dfce03, 0xe303fb06, 0x3307fb05, 
+    0x0808eb1c, 0x1c40415a, 0x4558b2c0, 0xebb9d3d2, 0xeb610008, 0xf06f0102, 0x22004300, 0x418a1a1b, 
+    0xf06fda02, 0xe0054000, 0x1a824a39, 0x31fff171, 0x4837da00, 0x2800ad03, 0xf8454601, 0xda000024, 
+    0x9a024249, 0xdd0d4291, 0xda052800, 0xf04f482b, 0x700101ff, 0xe034e014, 0x4828dd2e, 0x0101f04f, 
+    0xe01b7001, 0xf9924a25, 0x00491000, 0x2800d022, 0xda004601, 0x9b074249, 0xdd1b4299, 0xda0c2800, 
+    0xf8304818, 0xf1a11014, 0xf8200102, 0xf06f1014, 0x46500101, 0xfbb7f7f1, 0xdd0de00e, 0x0102f04f, 
+    0xf7f14650, 0x480ffbb0, 0x1014f830, 0xf8201c89, 0xe0011014, 0x70102000, 0xf8554916, 0xf8410024, 
+    0x1c640024, 0x2c04b2e4, 0xaed6f4ff, 0x0000e742, 0xd1800000, 0x00032282, 0x00032396, 0x00035a7c, 
+    0xd0030882, 0x00032286, 0x0003228e, 0x0003527c, 0x0002e09c, 0x0003ffc8, 0x00040130, 0x00032a3c, 
+    0x00032283, 0x000322c1, 0x00032cd7, 0x00032cd8, 0x80000001, 0x00033044, 0x41f0e92d, 0x460e2400, 
+    0x46252809, 0xe8dfd215, 0x0705f000, 0x140c0a15, 0x0012100e, 0xe00d2409, 0x25012408, 0x2401e00a, 
+    0x2404e008, 0x2402e006, 0x2405e004, 0x2406e002, 0x2403e000, 0xb12e4f0e, 0xf00c4638, 0xf000ff8f, 
+    0xe000000f, 0x02314620, 0x1104ea41, 0x46384301, 0xf00cb289, 0x462bff86, 0xe8bd4805, 0x220041f0, 
+    0x30402101, 0xbf97f00c, 0xe7c52100, 0xe7c32101, 0xd0030460, 0x41f0e92d, 0x2a014e19, 0x0880f44f, 
+    0x46074614, 0xd001b24d, 0xd1112c02, 0x46402170, 0xf987f7e2, 0xf7eb4638, 0x2000ffc3, 0xfcaef7eb, 
+    0x46292001, 0x70302200, 0xfcaff7eb, 0xd0032c02, 0x2c02b13c, 0xe00fd005, 0xf44f2100, 0xf7e92080, 
+    0x2200fb93, 0x46104629, 0xfc9ff7eb, 0x70302000, 0x46402171, 0xf98df7e2, 0xe8bd2001, 0x000081f0, 
+    0x00032b5c, 0x4cfcb510, 0xf00c4620, 0xf64eff37, 0x400861ee, 0x1111f241, 0x46204401, 0x4010e8bd, 
+    0xbf2ff00c, 0x4cf4b510, 0xf00c4620, 0xf242ff27, 0x43012122, 0xf00c4620, 0x4620ff24, 0xff1ef00c, 
+    0x51ddf64d, 0x46204001, 0x4010e8bd, 0xbf19f00c, 0xf241b570, 0x46050400, 0x4603220c, 0x462148e7, 
+    0xff29f00c, 0x220c48e6, 0x4621462b, 0xff23f00c, 0x220c48e4, 0x4621462b, 0xff1df00c, 0x4621462b, 
+    0x4070e8bd, 0x220c48e0, 0xbf15f00c, 0x47f0e92d, 0xf6404cda, 0x220b0600, 0x46074689, 0x46314603, 
+    0xf00c4620, 0x4dd6ff08, 0x463b220b, 0x46284631, 0xff01f00c, 0x834cf8df, 0x463b220b, 0x46404631, 
+    0xfef9f00c, 0x4ed04631, 0x463b220b, 0xf00c4630, 0xf240fef2, 0x464b4700, 0x4639220a, 0xf00c4620, 
+    0x220afeea, 0x4639464b, 0xf00c4628, 0x220afee4, 0x4639464b, 0xf00c4640, 0x464bfede, 0x46304639, 
+    0x47f0e8bd, 0xf00c220a, 0xe92dbed6, 0xf8df5ff0, 0x461e92ec, 0x460d4614, 0x8028f8dd, 0x21e02205, 
+    0x46034607, 0xf00c4648, 0xf8dffec6, 0x2205a2d4, 0x463b21e0, 0xf00c4650, 0xf8dffebe, 0x2205b2c8, 
+    0x463b21e0, 0xf00c4658, 0x463bfeb6, 0x22054fae, 0x463821e0, 0xfeaff00c, 0xd1212d03, 0x2c02b10c, 
+    0x2e01d101, 0xf008d011, 0x281b00ff, 0x2304d00d, 0x22054658, 0xf00c21e0, 0x2304fe9e, 0x22054638, 
+    0xe8bd21e0, 0xf00c5ff0, 0x2304be96, 0x22054648, 0xf00c21e0, 0x2304fe90, 0x22054650, 0xe7f021e0, 
+    0x9ff0e8bd, 0x46032200, 0x21074898, 0xbe83f00c, 0x4d96b570, 0x0400f248, 0x46212300, 0x4628220f, 
+    0xfe79f00c, 0x46212301, 0x4628220f, 0xfe73f00c, 0x46284621, 0x4070e8bd, 0x220f2300, 0xbe6bf00c, 
+    0x2801b570, 0x460d4604, 0xb92cd000, 0x22044888, 0x2130460b, 0xfe5ff00c, 0xd0012c02, 0xd1082c00, 
+    0x462b4883, 0x4070e8bd, 0x21302204, 0xf00c3080, 0xbd70be52, 0x41f0e92d, 0x46150c17, 0x460c2801, 
+    0xd0004606, 0x2c01b9ce, 0xb94cd000, 0x46394878, 0xf00c1d00, 0x4876fe26, 0x1d80b2a9, 0xfe21f00c, 
+    0xd0002c02, 0x4872b94c, 0x30084639, 0xfe19f00c, 0xb2a9486f, 0xf00c300a, 0x2e02fe14, 0x2e00d001, 
+    0x2c01d11c, 0xb94cd000, 0x46394869, 0xf00c3084, 0x4867fe08, 0x3086b2a9, 0xfe03f00c, 0xd0012c02, 
+    0xd10b2c00, 0x46394862, 0xf00c3088, 0xb2a9fdfa, 0xe8bd485f, 0x308a41f0, 0xbdf3f00c, 0x81f0e8bd, 
+    0x21004b5c, 0xb130b510, 0xd0072801, 0xd00d2802, 0xd1092803, 0x2200e00d, 0xe0012103, 0x210c2202, 
+    0xf00c4618, 0xb241fe06, 0xbd10b2c8, 0x21302204, 0x2206e7f6, 0xe7f321c0, 0x4d48b570, 0x1cad4604, 
+    0xf00c4628, 0x4e4cfdcb, 0x0000f364, 0x46304601, 0xfdc7f00c, 0xd1092c00, 0xf00c4628, 0xf020fdbf, 
+    0x46300102, 0x4070e8bd, 0xbdbbf00c, 0xb570bd70, 0x1ca44c3a, 0xf00c4620, 0x4d3ffdb1, 0x0102f040, 
+    0xf00c4628, 0x4620fdae, 0xfda8f00c, 0x0102f020, 0xe8bd4628, 0xf00c4070, 0xb57fbda4, 0x46144b37, 
+    0xcb4e460d, 0x004ee88d, 0xffaaf7ff, 0x0020f85d, 0xeb00b2a1, 0xf00c0045, 0xbd7ffd94, 0x4604b510, 
+    0x1c804826, 0xfd8af00c, 0x7100f240, 0x2104ea01, 0x60e2f420, 0xe8bd4308, 0xf0404010, 0x48260110, 
+    0xbd7ff00c, 0x2801b510, 0xd0004604, 0x2301b92c, 0x2200481f, 0xf00c4619, 0x2c02fd8e, 0x2c00d001, 
+    0x481bd108, 0x22002301, 0xe8bd4619, 0x30804010, 0xbd81f00c, 0xe92dbd10, 0x4c1641f0, 0xb283461d, 
+    0x22004616, 0x2103460f, 0xf00c4620, 0xb2bbfd74, 0x22024620, 0xf00c210c, 0xb2b3fd6e, 0x22044620, 
+    0xf00c2130, 0xb2abfd68, 0xe8bd4620, 0x220641f0, 0xf00c21c0, 0x0000bd60, 0xd03c8000, 0xd0033040, 
+    0xd0033240, 0xd0033440, 0xd0033640, 0xd0033a00, 0xd0033b00, 0xd0035026, 0xd0033842, 0x0002e18c, 
+    0x5ff0e92d, 0x469a4e5a, 0x46894617, 0xb028f8dd, 0x9c0c4605, 0xf00c4630, 0xf8dffd21, 0xf0208158, 
+    0x43290101, 0xf00c4640, 0x4630fd1c, 0xfd16f00c, 0x0002f020, 0x0145ea40, 0xf00c4640, 0x4630fd12, 
+    0xfd0cf00c, 0x0104f020, 0xea414640, 0xf00c0189, 0x4630fd08, 0xfd02f00c, 0x010ff06f, 0x0070f020, 
+    0x1107eb01, 0xb2814308, 0xf00c4640, 0x4630fcfa, 0xfcf4f00c, 0x6170f420, 0xea414640, 0xf00c210b, 
+    0x1cb7fcf0, 0xf00c4638, 0xf420fce9, 0xf108517c, 0xea410502, 0x4628210a, 0xfce3f00c, 0xf00c4638, 
+    0xf020fcdd, 0x980b017f, 0x46284301, 0xfcd9f00c, 0x0000f994, 0x21032200, 0x1d30b283, 0xfcebf00c, 
+    0x0001f994, 0x21032200, 0x482bb283, 0xfce3f00c, 0x0002f994, 0x21032200, 0x4828b283, 0xfcdbf00c, 
+    0x0003f994, 0x21032200, 0x4825b283, 0xfcd3f00c, 0xf00c4630, 0xf020fcb3, 0xf4400008, 0x46405180, 
+    0xfcaff00c, 0xf00c4630, 0xf040fca9, 0x46400108, 0xfca7f00c, 0xf00c4630, 0xf020fca1, 0x46400108, 
+    0x5ff0e8bd, 0xbc9df00c, 0x4c12b570, 0x4616460d, 0x46204601, 0xfc95f00c, 0x46291ca0, 0xfc91f00c, 
+    0x46311d20, 0xfc8df00c, 0x46284d09, 0xfc86f00c, 0x0108f040, 0xf00c4620, 0x4628fc84, 0xfc7ef00c, 
+    0x0108f020, 0xe8bd4620, 0xf00c4070, 0x0000bc7a, 0xd0033180, 0xd0033980, 0xd0033384, 0xd0033584, 
+    0xd0033784, 0x21012300, 0xb510461a, 0xf00c48fe, 0x48fdfc82, 0x1103f240, 0x4010e8bd, 0xf00c1c80, 
+    0xe92dbc60, 0x4ef95ff0, 0x22062301, 0x46302140, 0xfc71f00c, 0x46302301, 0x21202205, 0xfc6bf00c, 
+    0x46302301, 0x21102204, 0xfc65f00c, 0x46302301, 0x21082203, 0xfc5ff00c, 0x46302300, 0x21402206, 
+    0xfc59f00c, 0x46302300, 0x21202205, 0xfc53f00c, 0x46302300, 0x21102204, 0xfc4df00c, 0x46302300, 
+    0x21082203, 0xfc47f00c, 0x9384f8df, 0x7100f240, 0xf00c4648, 0xf248fc26, 0xf1090a00, 0x46510004, 
+    0xfc1ff00c, 0x0800f242, 0x220d48da, 0xf00c4641, 0x4dd6fc40, 0xb3903d34, 0x46512301, 0x4630220f, 
+    0xfc29f00c, 0x462f2400, 0x46282100, 0xfc09f00c, 0x1cad1c64, 0x2c12b264, 0x48ccdbf6, 0x6180f246, 
+    0xf00c381c, 0x48c9fbfe, 0x6166f24e, 0xf00c381a, 0x48c6fbf8, 0x38182140, 0xfbf3f00c, 0xf64048c3, 
+    0x3816213d, 0xfbedf00c, 0xf24848c0, 0x381471d7, 0xfbe7f00c, 0x46382100, 0xfbe3f00c, 0xe7ffe010, 
+    0x46512300, 0x4630220f, 0xfbf5f00c, 0x46282400, 0xf00c2100, 0x1c64fbd6, 0xb2641cad, 0xdbf62c12, 
+    0xf24048b1, 0x1c801103, 0xfbcbf00c, 0x210048b2, 0xfbc7f00c, 0x48ac2300, 0x461a2101, 0xfbdbf00c, 
+    0xf44f4cae, 0x78213080, 0xfffef7e8, 0x230048ac, 0x21802207, 0xfbcff00c, 0x46457821, 0xf7e84640, 
+    0x4fa2fff3, 0x2209230e, 0x6100f643, 0x46381ebf, 0xfbc1f00c, 0xf24c2302, 0x220e0100, 0xf00c4638, 
+    0x2303fbba, 0x22004630, 0xf00c2107, 0x2301fbb4, 0x220e4630, 0xf00c0399, 0x2301fbae, 0x220d4629, 
+    0xf00c4630, 0x2301fba8, 0x22074630, 0xf00c2180, 0xf240fba2, 0x46301b00, 0x46592301, 0xf00c2208, 
+    0x7821fb9a, 0x4000f240, 0xffbef7e8, 0x46302300, 0x21802207, 0xfb8ff00c, 0x46592300, 0x46302208, 
+    0xfb89f00c, 0x464e2100, 0xf00c4648, 0x4880fb6a, 0x1d002100, 0xfb65f00c, 0x46287821, 0xffa4f7e8, 
+    0x23004879, 0x46592208, 0xf00c1c80, 0x487afb74, 0x220f2301, 0x46514657, 0xfb6df00c, 0x46592301, 
+    0x46302208, 0xfb67f00c, 0x2300486f, 0x21022201, 0xf00c1c80, 0x486cfb60, 0x21012300, 0x1c80461a, 
+    0xfb59f00c, 0x2800f240, 0x23014630, 0x22094641, 0xfb51f00c, 0x20047821, 0xff76f7e8, 0x23014862, 
+    0x46592208, 0xf00c1c80, 0x485ffb46, 0x21022301, 0x1c80461a, 0xfb3ff00c, 0x46287821, 0xff64f7e8, 
+    0x2300485d, 0x4639220f, 0xfb35f00c, 0x23014856, 0x46192200, 0xf00c1c80, 0x7821fb2e, 0x3080f44f, 
+    0xff52f7e8, 0x46592300, 0x46302208, 0xfb23f00c, 0x46412300, 0x46302209, 0xfb1df00c, 0x25014f4b, 
+    0x370c05ec, 0xf10712e6, 0xe00f0802, 0xf7e84620, 0x1e04ff39, 0x4c4bdc0a, 0x46202500, 0xfaeef00c, 
+    0x6180f440, 0xf00c4620, 0xe00dfaec, 0x4631220c, 0xf00c4638, 0x2800fb0e, 0x220cd0e8, 0x46404631, 
+    0xfb07f00c, 0xd0e12800, 0xe8bd4628, 0xe92d9ff0, 0x4c384ff8, 0x22002301, 0x210f3456, 0xf00c4620, 
+    0x2305faea, 0x22044620, 0xf00c21f0, 0x2305fae4, 0x7100f640, 0x46202208, 0xfaddf00c, 0xf24f2305, 
+    0x220c0100, 0xf00c4620, 0x2004fad6, 0xfe6af7ec, 0xf64b4828, 0x308031b1, 0xfab3f00c, 0x21004d22, 
+    0x4628350e, 0xfaadf00c, 0x0a00f241, 0x220c4821, 0xf00c4651, 0x07c0face, 0x0406f1a5, 0x2301d001, 
+    0x2300e000, 0x22014620, 0xf00c2102, 0xf8dffab4, 0x46a89078, 0xb050f8df, 0x4f182601, 0xf10b4d19, 
+    0xf8990b24, 0xf0000000, 0x46400401, 0xf00c2101, 0x4658fa88, 0xfa82f00c, 0xd02a07c0, 0x46402100, 
+    0xfa7ff00c, 0xf7e1b144, 0xf000fbb7, 0xfa06010f, 0x7839f001, 0xfeb8f7e8, 0xf00c4628, 0xf440fa6f, 
+    0x46286100, 0x0000e012, 0xd0034000, 0xd003e834, 0xd03c8308, 0xd03c8038, 0xd0039004, 0x0003227f, 
+    0xd0034228, 0xd003517a, 0x00032228, 0xfa59f00c, 0x4628e7cb, 0xfa52f00c, 0x6100f420, 0xf00c4628, 
+    0x4dc0fa50, 0x21012200, 0xf00c4628, 0x42a0fa72, 0xf7ffd00f, 0x48bbfdd7, 0x0200f04f, 0x0101f04f, 
+    0xb1dc3018, 0xfa65f00c, 0x0100ea26, 0xf00c4628, 0x48b5fa38, 0x4656220c, 0xf00c4651, 0x4cb1fa5a, 
+    0xb1a01f24, 0x220c48b0, 0x1c804631, 0xfa51f00c, 0x4620b168, 0xfa22f00c, 0xe01cb148, 0xfa49f00c, 
+    0xe7e34601, 0x46204631, 0xfa1bf00c, 0xf64de001, 0xf7ff66ad, 0x2800fdb6, 0x2200d0f4, 0x21014628, 
+    0xfa37f00c, 0x32084a9f, 0xd07c2800, 0x11e1f24d, 0xf00c4610, 0x2103fa06, 0xf00c4620, 0x489bfa02, 
+    0x31b2f64b, 0xf9fdf00c, 0x23014899, 0x21402206, 0xfa11f00c, 0x23004897, 0x21202205, 0xfa0bf00c, 
+    0x464d4c91, 0x0000f999, 0x28003c0c, 0x2802d07d, 0x2301d07b, 0x22044620, 0xf00c2110, 0x2301f9fc, 
+    0x21402206, 0xf00c4620, 0x200ff9f6, 0x498a9000, 0x3395f647, 0xf2474889, 0xf7ec0282, 0x2100fa39, 
+    0xf7e82004, 0x2001fe11, 0xf83df7ef, 0x0000f995, 0xd0702800, 0xd06e2802, 0x46202300, 0x21102204, 
+    0xf9d9f00c, 0x22062300, 0x46202140, 0xf9d3f00c, 0xf44f2100, 0xf7e83080, 0x2300fdf7, 0x22074620, 
+    0xf00c2180, 0x2208f9c8, 0x23004620, 0x46310156, 0xf9c1f00c, 0x20042100, 0xfde6f7e8, 0x0000f995, 
+    0x2802b3a0, 0x2301d051, 0x22084631, 0xf00c4620, 0x2100f9b2, 0xf00c4640, 0x2301f994, 0x220d4868, 
+    0x4621035c, 0xe028e000, 0xf9a5f00c, 0x23014865, 0x4621220d, 0xf99ff00c, 0x01e07839, 0xfdc4f7e8, 
+    0x23004c61, 0x21102204, 0xf00c4620, 0x2301f994, 0x22044620, 0xf00c2110, 0x2301f98e, 0x22074620, 
+    0xf00c2180, 0x7839f988, 0xe009e001, 0xe8bde01d, 0xf2404ff8, 0xf7e82000, 0xf24dbda7, 0xe75711e0, 
+    0x46202301, 0x21082203, 0xf975f00c, 0x22052301, 0xe7772120, 0x2300e7ff, 0x22034620, 0xf00c2108, 
+    0x2300f96a, 0x21202205, 0x2301e78f, 0x21802207, 0xe92de7ac, 0x460647f0, 0x25004844, 0xf0007800, 
+    0xf7ea0001, 0x4837fa9c, 0xf00c3020, 0x07c0f937, 0xf8dfd13b, 0x240090d4, 0x0801f04f, 0x0940f1a9, 
+    0x0044eb09, 0xf00c4607, 0xb138f929, 0x2100b11e, 0xf00c4638, 0xfa08f926, 0x4305f004, 0xb2e41c64, 
+    0xd3ed2c12, 0x90a0f8df, 0xf1a92400, 0xeb090910, 0x46070044, 0xf912f00c, 0xb11eb148, 0x46382100, 
+    0xf90ff00c, 0x0111f104, 0xf001fa08, 0x1c644305, 0x2c08b2e4, 0x4c1bd3eb, 0x4620340a, 0xf8fef00c, 
+    0x0101f040, 0xf00c4620, 0xf7eaf8fc, 0x4628fa90, 0x87f0e8bd, 0x47f0e92d, 0x481c4606, 0x78002500, 
+    0x0001f000, 0xfa4bf7ea, 0x803cf8df, 0xf04f2400, 0xf1a80901, 0xeb080840, 0x46070044, 0xf8def00c, 
+    0xb11eb140, 0x46382100, 0xf8dbf00c, 0xf004fa09, 0xb2854328, 0xb2e41c64, 0xd3ec2c0c, 0xfa67f7ea, 
+    0xe7d54628, 0xd003400a, 0xd003e840, 0xd03c80b8, 0xd03c830e, 0xd0034228, 0xffffaa02, 0xffffa14d, 
+    0xd003c81e, 0xd003d81e, 0xd0039000, 0x00032228, 0x4d09b570, 0x21002400, 0x0044eb05, 0xf8b1f00c, 
+    0x2c301c64, 0xbd70dbf7, 0xf7ffb510, 0xe8bdfff1, 0x20004010, 0xba5ef7ee, 0xd003e200, 0x41f0e92d, 
+    0xf7f92400, 0x4870ff6b, 0xf8df4f70, 0xf8dfe1c8, 0x7801c1c8, 0x4e71486e, 0x683a460d, 0x3000f990, 
+    0xd0042b03, 0xd0142b05, 0xd0262b04, 0x486ce031, 0x28126800, 0xf64dd302, 0xe00160f7, 0x60eaf64e, 
+    0xf89e4342, 0x14120000, 0x240ab108, 0x2409e021, 0x7830e01f, 0xd0092801, 0xd0072802, 0x4000f89c, 
+    0xd0034304, 0xd0012803, 0xe0122401, 0x0000f89e, 0x2404b108, 0x2403e00d, 0x7830e00b, 0xd0332801, 
+    0xd0312802, 0x4000f89c, 0xd02d4304, 0xd02b2803, 0xf6432402, 0x428270ff, 0x1e42db00, 0xe144f8df, 
+    0xeb0e2000, 0xf1c01404, 0xf9340e07, 0x4596e01e, 0x1c40dc03, 0x2808b200, 0x2807dbf5, 0x4a49dc05, 
+    0x0007f1c0, 0xf81232b0, 0x2b045010, 0xd0124a46, 0xd0282b05, 0xd23e2d0c, 0xb3b87810, 0xd336290f, 
+    0xd23a2919, 0xe0472406, 0x0000f89e, 0x2406b108, 0x2405e7cf, 0x7830e7cd, 0xd00e2801, 0xd00c2802, 
+    0x4000f89c, 0xd0084304, 0xd0062803, 0xd22e2d0c, 0x28007810, 0x2402d1e2, 0x2d2de03c, 0xe02ad314, 
+    0xd3112d4b, 0x7830e027, 0xd0052801, 0xd0032802, 0x4000f89c, 0xd1e94320, 0xd3122d23, 0xd3142d2d, 
+    0xd3162d41, 0xd2162d55, 0xe0152401, 0x2407e001, 0x2405e012, 0x2d23e01e, 0x2405d201, 0x2d2de00c, 
+    0x2404d201, 0x2d37e008, 0x2403d201, 0x2d41e004, 0x2402d2d6, 0x2400e000, 0x28017810, 0x2802d003, 
+    0x2b03d108, 0x2c06d106, 0x4818da04, 0x28017800, 0x2406d100, 0x2c002000, 0x4604da00, 0xf00b4814, 
+    0x8838ffd0, 0x4812b281, 0xf00b3020, 0x7831ffca, 0xeb000320, 0x44282001, 0x480db281, 0xf00b3026, 
+    0x4620ffc0, 0x81f0e8bd, 0x00032398, 0x0003242c, 0x0003227e, 0x00032396, 0x00032372, 0x00032411, 
+    0x0003222c, 0x00032b9c, 0x000322ec, 0x000322ed, 0xd0035182, 0xb50848fe, 0x90008800, 0x780348fd, 
+    0xf99048fd, 0x48fd2000, 0x20007801, 0xf8ddf7ff, 0x4008e8bd, 0xf7ee2004, 0xb57cb8e8, 0xf7f02001, 
+    0x4cf7fe7b, 0x2803b240, 0xd1157020, 0x880048f5, 0x7facf5b0, 0xf5b0d008, 0xd0057fa4, 0x7fb4f5b0, 
+    0xf5b0d002, 0xd1077fbc, 0x70202005, 0x230748ee, 0x213c2202, 0xff8ff00b, 0xf7e87820, 0x49ebfba5, 
+    0x21007008, 0xf7ef2008, 0x7820fb0f, 0xff96f7eb, 0x250049e2, 0x23019500, 0x461a7820, 0xf7e47809, 
+    0x2101fa43, 0xf7ec4608, 0xf640f81c, 0xf6474100, 0x23177203, 0x00889500, 0xffbaf7eb, 0x210248dc, 
+    0xff4ff00b, 0xf64048db, 0xf00b7131, 0x2001ff4a, 0x46022300, 0x0500e9cd, 0xf7e94619, 0x49d6fcdb, 
+    0x60082018, 0xe92dbd7c, 0x4fd45ffc, 0x8e804606, 0xb34cf8df, 0x834cf8df, 0x683b28e2, 0xdc05d079, 
+    0x289ab170, 0x289bd018, 0xe020d174, 0xd00628e3, 0x7f90f5b0, 0xf5a0d06f, 0x38217080, 0xe1c7d16a, 
+    0xf04f49c7, 0xf8db32ff, 0x1d090000, 0xfb5af007, 0xd1081d01, 0xe0ae209a, 0x220049c1, 0x0000f8db, 
+    0xf0071d09, 0x1d41fb4f, 0x2801d031, 0x48bcd1e8, 0xf9b01d00, 0x296e1000, 0xf04fd1e2, 0x46815580, 
+    0x4220f04f, 0xf7e14628, 0xf898f96a, 0xf04f1000, 0x46445290, 0xf7e14628, 0x7820f962, 0xd07b2800, 
+    0xf04f2500, 0x24010a05, 0xd0122801, 0xd04a2802, 0xd04d2803, 0x9288f8df, 0xf8df2804, 0xd07da280, 
+    0xd06b2805, 0xd06a2806, 0xd0692807, 0x209be187, 0xf7fbe071, 0xf7fffe8c, 0xf7ffff40, 0x489dff2b, 
+    0x220f2300, 0x0100f248, 0xf00b301a, 0x2201fee4, 0x46112300, 0x4500e9cd, 0xf7e94610, 0x489afc5b, 
+    0xfebcf00b, 0x80084999, 0x48990701, 0x8004d004, 0xe00ee003, 0xe044e050, 0x22008005, 0xf8a94990, 
+    0x6838a000, 0xf0071d09, 0x1d01fabe, 0x20e2d107, 0x498be041, 0x46182200, 0xf0071d09, 0x1d40fab4, 
+    0x20e3d178, 0xf7ffe037, 0xf7ffff08, 0xe133fef3, 0xff03f7ff, 0x23004d87, 0xf640220b, 0x46280100, 
+    0xfea9f00b, 0x46282301, 0x0319220c, 0xfea3f00b, 0xf6404878, 0xf00b1137, 0x487ffe84, 0x49782200, 
+    0x70041d09, 0xa000f8a9, 0xf0076838, 0x1d01fa8c, 0xf240d10d, 0xe00e1020, 0xe00fe118, 0xe102e06e, 
+    0x496fe113, 0x46182200, 0xf0071d09, 0x1d40fa7c, 0xf240d1c6, 0x86b01021, 0x9ffce8bd, 0xfecdf7ff, 
+    0xfeb8f7ff, 0x0000f999, 0xd0342805, 0xd0342804, 0x496a2000, 0x29017809, 0x2902d031, 0x2904d035, 
+    0x2905d039, 0x2906d03d, 0x2500d041, 0xf7fe462c, 0x484fffdf, 0x90008800, 0xf89a484e, 0x78031000, 
+    0xf990484d, 0x20032000, 0xff7ff7fe, 0xf7fe2004, 0x2100ffc9, 0xf7fe4608, 0x2101ffe3, 0x2000462a, 
+    0xfff8f7fe, 0x46222102, 0xf7fe2000, 0x2000fff3, 0xf8a8f7ff, 0x2001e0cc, 0x2002e7cb, 0xf241e7c9, 
+    0xf6417580, 0x40c52480, 0xf243e016, 0xf2432580, 0x40c53480, 0xf645e010, 0xf6451580, 0x40c52480, 
+    0xf648e00a, 0xf6482580, 0x40c54480, 0xf24ce004, 0xf64c6580, 0x40c50480, 0xe7b840c4, 0xfe6df7ff, 
+    0xfe58f7ff, 0xf843f7ff, 0x22402100, 0xf7ff4608, 0x220df854, 0x20002101, 0xf84ff7ff, 0x21022205, 
+    0xf7ff2000, 0x2240f84a, 0x20012100, 0xf845f7ff, 0x220d2101, 0xf7ff4608, 0x2205f840, 0x20012102, 
+    0xf83bf7ff, 0x21002240, 0xf7ff2002, 0x220df836, 0x20022101, 0xf831f7ff, 0x22052102, 0xf7ff4608, 
+    0x2240f82c, 0x20032100, 0xf827f7ff, 0x2101220d, 0xf7ff2003, 0x2205f822, 0x20032102, 0xf81df7ff, 
+    0xf7fe2000, 0x2003ffe9, 0xf828f7ff, 0x22002301, 0xe9cd4619, 0x46185400, 0xfb4cf7e9, 0x22002301, 
+    0x21024618, 0x5400e9cd, 0xfb44f7e9, 0xe027464c, 0x000322ac, 0x00032304, 0x00032228, 0x00032411, 
+    0x0003227e, 0x00032392, 0xd0020000, 0x0003227f, 0xd03c8304, 0xd003502a, 0x0003222c, 0x00032564, 
+    0x00032c5c, 0x00032270, 0xd0035136, 0x000322ae, 0x000322b0, 0xd28fffd2, 0x00032283, 0x000323bc, 
+    0x0000f999, 0xd0012805, 0xd1212804, 0x200c2100, 0xfc46f7fd, 0x21019500, 0x20007822, 0x3000f89a, 
+    0xfb1ef7fd, 0xf7ffe014, 0xf7fffdd8, 0x4838fdc3, 0x7131f640, 0xfd65f00b, 0x22012300, 0xe9cd4618, 
+    0x46114500, 0xfaf6f7e9, 0x2001e002, 0xfb85f7e9, 0x0000f898, 0xf43f2807, 0x2800ae33, 0xf7fed0fb, 
+    0xe62dfe21, 0x21012200, 0xf2afb510, 0xf00630e5, 0x2108ffa5, 0xf0072002, 0x4926f903, 0xbd106008, 
+    0x2000b57c, 0xfdeef7e8, 0x20142100, 0xfc08f7fd, 0x25004821, 0x46294c21, 0x78029500, 0x78234628, 
+    0xfadef7fd, 0xf7f02004, 0x481df974, 0x90008800, 0x7821481c, 0x481c7803, 0x2000f990, 0xf7fe2000, 
+    0x2000fe64, 0xfaaef7e9, 0x23002001, 0xe9cd4602, 0x46010500, 0xf7e94618, 0x4814faad, 0xf00b2100, 
+    0x4c13fd10, 0x0000f241, 0xf7e87821, 0xf242f94d, 0x46290550, 0x463006ee, 0xff2ff7e0, 0x0bf07821, 
+    0xf942f7e8, 0x46304629, 0x407ce8bd, 0xbf25f7e0, 0xd003502a, 0x00032c5c, 0x0003227e, 0x00032411, 
+    0x000322ac, 0x00032304, 0x00032228, 0xd0034220, 0x0003227f, 0x43f8e92d, 0x48ff4606, 0x600149fd, 
+    0xf00b48fe, 0x2000fcd8, 0xfd8cf7e8, 0xfea0f7e6, 0x83ecf8df, 0x2400f240, 0xf8984620, 0xf7e61000, 
+    0x48f8fea1, 0x71fff64f, 0xfcc5f00b, 0x20022100, 0xf8a2f7e8, 0x230048f4, 0x21022201, 0xfcdbf00b, 
+    0x93c8f8df, 0x22092300, 0x46484621, 0xfcd3f00b, 0x230148ee, 0x03d9220f, 0xf00b3012, 0x4fe6fccc, 
+    0x1d3f2500, 0xb2e12400, 0x0014f817, 0xb2424240, 0xf7feb2e8, 0x1c64ff02, 0xdbf42c10, 0x2d041c6d, 
+    0x2000dbf0, 0xfec8f7fe, 0xf7fe2003, 0x48dfff07, 0x21012300, 0x30a0461a, 0xfcadf00b, 0x46082100, 
+    0xf9fcf7e9, 0xf7eb201b, 0x2300faf5, 0x22074648, 0xf00b2180, 0x2300fca0, 0x210148d5, 0xf00b461a, 
+    0x2000fc9a, 0xf8989000, 0x22033000, 0x20084601, 0xfa26f7fd, 0x23004dcf, 0x21e02205, 0xf00b4628, 
+    0x4ccdfc8a, 0x22052300, 0x462021e0, 0xfc83f00b, 0x8328f8df, 0x22052300, 0x464021e0, 0xfc7bf00b, 
+    0x931cf8df, 0x22052300, 0x464821e0, 0xfc73f00b, 0xf7e92001, 0x2100f9e7, 0x2080f44f, 0xf894f7e8, 
+    0x46112201, 0xf7fa4610, 0x2202fbcd, 0x10c3f240, 0xf7fe2107, 0x48bbfccf, 0xf9f1f7ea, 0xf7fe2000, 
+    0x2100fcc3, 0x46082302, 0xf7e82208, 0x230cfd59, 0x461a2100, 0xf7e84608, 0x2300fd8d, 0x4619461a, 
+    0xf7e84618, 0x2101fd6f, 0xf7e82000, 0x48a5fd37, 0x22112300, 0xf44f3848, 0xf00b3100, 0x2001fc25, 
+    0xfcd0f7e8, 0x1700f44f, 0x46382100, 0xf85cf7e8, 0x2100230c, 0x4608461a, 0xfd6cf7e8, 0x46382100, 
+    0xf852f7e8, 0x2100230d, 0x4608461a, 0xfd62f7e8, 0x46382100, 0xf848f7e8, 0x220504f0, 0x21e010c0, 
+    0x46280f43, 0xfc17f00b, 0x220504b0, 0x21e010c0, 0x46200f43, 0xfc0ff00b, 0x22050470, 0x21e010c0, 
+    0x46400f43, 0xfc07f00b, 0x22050430, 0x21e010c0, 0x46480f43, 0xfbfff00b, 0x43f8e8bd, 0xf7e72002, 
+    0xe92dbfcc, 0xb08847f0, 0x20004605, 0x4601ae04, 0x1020f846, 0x28041c40, 0xf8dfdbfa, 0x240091f0, 
+    0xa1e8f8df, 0x0800f248, 0x0918f109, 0xf10a466f, 0x46400a06, 0xf7e82100, 0x2101f807, 0x464a466b, 
+    0xf00c4650, 0x2000faf8, 0x1020f856, 0x2020f857, 0xf8464411, 0x1c401020, 0xdbf52804, 0x2c401c64, 
+    0x2000dbe7, 0x1020f856, 0x11893120, 0x1020f845, 0x28041c40, 0xb008dbf6, 0x0010f105, 0x87f0e8bd, 
+    0x20004603, 0x188cb510, 0xf833e005, 0x1c492011, 0xf202fb12, 0x428c4410, 0xbd10dcf7, 0x4ff8e92d, 
+    0x46044d58, 0x46283d48, 0xfb82f00b, 0x46832300, 0x461a2101, 0xf00b4628, 0x46aafb87, 0xf00b4650, 
+    0x07c0fb77, 0x4858d1fa, 0x46a92500, 0x8000f8d0, 0xb2692200, 0x46434610, 0xf8cd460e, 0xf7e69000, 
+    0x2700fc3a, 0x46bc46be, 0xf938463a, 0x28000012, 0x4603db01, 0x4243e000, 0x42b9b219, 0x460fdd02, 
+    0x46944686, 0xb2121c52, 0xdbee2a80, 0x46402280, 0xe9c42100, 0xf7ffec00, 0x2280ffb3, 0x461160a0, 
+    0xf7ff4640, 0x2280ffad, 0x464060e0, 0xf7ff0051, 0x2280ffa7, 0x1180f240, 0x46406120, 0xffa0f7ff, 
+    0x61602280, 0x00914640, 0xff9af7ff, 0xf2402280, 0x61a02180, 0xf7ff4640, 0x2280ff93, 0x3100f240, 
+    0x464061e0, 0xff8cf7ff, 0xf2402280, 0x62203180, 0xf7ff4640, 0x2701ff85, 0x34286260, 0x20004643, 
+    0xb27a4631, 0x9000f8cd, 0xfbe5f7e6, 0x46402280, 0xf7ff2100, 0x2280ff75, 0x46116020, 0xf7ff4640, 
+    0x1c7fff6f, 0xb23f6060, 0x2f043408, 0x1c6ddbe6, 0x2d04b22d, 0x4659db8c, 0xf00b4650, 0x4620fafc, 
+    0x8ff8e8bd, 0x4ff0e92d, 0x7d0bf5ad, 0xfe12f7ff, 0xad402000, 0xf8454601, 0x1c401020, 0xdbfa2840, 
+    0xf06f2000, 0xaa86417f, 0xf8424690, 0x1c401020, 0xe01b2804, 0x0003ddfc, 0x00032c68, 0xc3000088, 
+    0x00032411, 0xd1800048, 0xd03c8310, 0xd0030400, 0xd0031012, 0xd0033040, 0xd0033240, 0xd0033440, 
+    0xd0033640, 0x000323cc, 0x00032224, 0x2400dbdc, 0xf50d46eb, 0xf2407a00, 0x26004700, 0x0900f1c7, 
+    0xd0642c00, 0xb2704649, 0xfe7df7ef, 0x2e041c76, 0x2100dbf6, 0x0000f44f, 0xfef6f7e7, 0xf7ff4668, 
+    0xa880ff1d, 0xfecdf7ff, 0x46dc2000, 0xeb0c0101, 0xeb050681, 0x68b30281, 0x42bb6897, 0xf85cdd06, 
+    0xf8457021, 0x68767021, 0x6301e9c2, 0x188e2203, 0x3026f85c, 0x7026f855, 0xdd0142bb, 0x3026f845, 
+    0x2a0f1c52, 0xf858ddf3, 0x46423020, 0x1020f85a, 0xdd01428b, 0x1020f842, 0x28041c40, 0x1c64dbd6, 
+    0xdbb82c02, 0x680448fe, 0xf8522000, 0x1c401020, 0xc4022804, 0xa884dbf9, 0xf821f7ea, 0xa9842000, 
+    0x2010f931, 0x28041c40, 0xdbf9c404, 0xf8552000, 0xf8441020, 0x1c401020, 0xdbf82840, 0xf44f2100, 
+    0xf7e71080, 0xf50dfea1, 0xe8bd7d0b, 0x46398ff0, 0xb510e799, 0x20004604, 0xe0074602, 0x3012f934, 
+    0xda012b00, 0xe0001ac0, 0x1c524418, 0xdbf5428a, 0xb5ffbd10, 0x466d2300, 0xf845461c, 0x1c5b4023, 
+    0xdbfa2b04, 0xe0162300, 0x6013f930, 0x44349c00, 0xeb009400, 0x9e010443, 0xf9b41d1b, 0x443e7002, 
+    0xf9b49601, 0x9e027004, 0x9602443e, 0x4006f9b4, 0x44349e03, 0x428b9403, 0x108bdbe6, 0xb2141e92, 
+    0xf8552100, 0xeb022021, 0x41220263, 0x2021f845, 0x29041c49, 0x2100dbf5, 0xf830e014, 0x9c002011, 
+    0xf8201b12, 0xeb002011, 0x9d010241, 0x1b648854, 0x88948054, 0x1b649d02, 0x88d48094, 0x1b649d03, 
+    0x1d0980d4, 0xdbe84299, 0xe92dbdff, 0xb0934ff0, 0xfd10f7ff, 0x9004200a, 0x4dba2300, 0x210148ba, 
+    0x4400f240, 0xf00b461a, 0x48b7f9ef, 0x21012300, 0x3830461a, 0xf9e8f00b, 0xf7fe2000, 0x2140fa65, 
+    0xf7e82000, 0x48aefad8, 0x090df04f, 0x20006807, 0x90094680, 0x49ad9012, 0x80c84aae, 0x80488088, 
+    0x48ab8008, 0x780349ac, 0xf7e948a8, 0xf44fff97, 0x21001680, 0xf7e74630, 0x2101fe07, 0x46082304, 
+    0xf7ed2200, 0x2100f8c0, 0xf7e74630, 0x12b1fdfd, 0x0b01f04f, 0x23009400, 0x46281e5a, 0xb101e9cd, 
+    0xf8cd2103, 0xf7fdb00c, 0x2600faab, 0x0a38f10d, 0xfb069a04, 0x4621f004, 0x0040eb05, 0xf7ff4684, 
+    0x4660ff58, 0xf7ff4621, 0xf84aff44, 0x1c760026, 0xdbed2e04, 0x4100f240, 0x23009400, 0x1e5a4628, 
+    0xb101e9cd, 0xf8cd2103, 0xf7fdb00c, 0x2600fa89, 0x46219a04, 0xf004fb06, 0x0040eb05, 0xf7ff4684, 
+    0x4660ff38, 0xf7ff4621, 0xf85aff24, 0x18812026, 0x1026f84a, 0x2e041c76, 0xf240dbea, 0x94004100, 
+    0x46282300, 0xe9cd1e5a, 0x2103b101, 0xb00cf8cd, 0xfa66f7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 
+    0x46840040, 0xff15f7ff, 0x46214660, 0xff01f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 0xdbea2e04, 
+    0x94002001, 0x02811e82, 0xe9cd2300, 0x21030101, 0x46289003, 0xfa44f7fd, 0x9a042600, 0xfb064621, 
+    0xeb05f004, 0x46840040, 0xfef3f7ff, 0x46214660, 0xfedff7ff, 0x2026f85a, 0x188146d3, 0x1026f84a, 
+    0x2e041c76, 0x2201dbe9, 0x46112304, 0xf7ed4610, 0x2100f82a, 0x1080f44f, 0xfd66f7e7, 0x48544953, 
+    0xf8a14a54, 0xf8a19006, 0xf8a19004, 0xf8a19002, 0x78039000, 0x484d4950, 0xfee0f7e9, 0x23022101, 
+    0x22084608, 0xfa2cf7e8, 0xf242220b, 0x46110600, 0xf7e84630, 0x220cfb3d, 0x46114630, 0xfb38f7e8, 
+    0x4630220d, 0xf7e84611, 0x2001fb33, 0x1e829400, 0x23000281, 0x0101e9cd, 0x90032103, 0xf7fd4628, 
+    0x2600f9ef, 0x0a28f10d, 0xfb069a04, 0x4621f004, 0x0040eb05, 0xf7ff4684, 0x4660fe9c, 0xf7ff4621, 
+    0xf84afe88, 0x1c760026, 0xdbed2e04, 0x94002001, 0x02811e82, 0xe9cd2300, 0x21030101, 0x46289003, 
+    0xf9cef7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 0x46840040, 0xfe7df7ff, 0x46214660, 0xfe69f7ff, 
+    0x2026f85a, 0xf84a1881, 0x1c761026, 0xdbea2e04, 0x94002001, 0x02811e82, 0xe9cd2300, 0x21030101, 
+    0x46289003, 0xf9acf7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 0x46840040, 0xfe5bf7ff, 0x46214660, 
+    0xfe47f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 0xdbea2e04, 0x94002001, 0x02811e82, 0xe9cd2300, 
+    0x21030101, 0x46289003, 0xf98af7fd, 0x9a042600, 0xfb064621, 0xeb05f004, 0x46840040, 0x0000e00e, 
+    0x00032c68, 0x000331ec, 0xd1800030, 0x000323cc, 0x00032411, 0x000323b4, 0x000323e2, 0xfe29f7ff, 
+    0x46214660, 0xfe15f7ff, 0x2026f85a, 0xf84a1881, 0x1c761026, 0xdbda2e04, 0xf7ffa805, 0x2000fc82, 
+    0xab054651, 0xf852465a, 0x603e6020, 0x6020f851, 0xf853607e, 0x1c406020, 0x370c60be, 0xdbf22804, 
+    0x21402600, 0xf7efb270, 0x1c76fc0e, 0xdbf82e04, 0x0801f108, 0x0f40f1b8, 0x9812da01, 0x2100e66b, 
+    0x1080f44f, 0xfc80f7e7, 0xea409809, 0xea412100, 0xea414100, 0x60386000, 0x2109ea49, 0x4109ea41, 
+    0x6009ea41, 0xb0136078, 0xe92de5cf, 0x250041f0, 0x4700f240, 0x21004efe, 0xf7e74638, 0x4630fc65, 
+    0xf81cf00b, 0x0720b204, 0x48f9d0f5, 0x1c80b2a1, 0xf817f00b, 0x000ff004, 0xd00f2801, 0xd0112802, 
+    0xd0132803, 0xf64f2501, 0xea0470f0, 0x46300100, 0xf807f00b, 0xd0de2d00, 0x81f0e8bd, 0xf7ff4620, 
+    0xe7f0fe04, 0xf7ff4620, 0xe7ecfcfd, 0xf7ff4620, 0xe7e8fb11, 0x4ff8e92d, 0xa398f8df, 0x71fff64f, 
+    0xf00a4650, 0x2100ffe8, 0xf7e72002, 0xf7f1fbc5, 0x4ee1fe6e, 0x94002400, 0x21012203, 0x7833200a, 
+    0xfd8ef7fc, 0xfe5bf7f1, 0x22002101, 0xf7f94608, 0xf7f8ff59, 0x2101fa3e, 0x46082200, 0xff52f7f9, 
+    0x210048d6, 0x68052201, 0x94004608, 0xf7e6462b, 0x2280f892, 0x21004628, 0xfc22f7ff, 0x46072201, 
+    0x462b2000, 0x94004611, 0xf885f7e6, 0x46282280, 0xf7ff2100, 0x2203fc15, 0x21024681, 0x2000462b, 
+    0xf7e69400, 0x2280f878, 0x21004628, 0xfc08f7ff, 0x46802203, 0x462b2000, 0x94004611, 0xf86bf7e6, 
+    0x46282280, 0xf7ff2100, 0x4cbdfbfb, 0x0200f242, 0xda054297, 0xda034591, 0xda014590, 0xdb014290, 
+    0xe0004db8, 0x46504db8, 0xf00a4629, 0x2000ff84, 0xf7e86025, 0xf7e6f837, 0xf7f1f94b, 0x4dacfcd3, 
+    0x35742400, 0xb2241c64, 0xfd72f7f0, 0xfdcaf7f8, 0xfaa6f7fc, 0xf249b110, 0xe003010d, 0xddf12c05, 
+    0x31adf640, 0xf00a4628, 0x2101ff6c, 0x46082200, 0xfee8f7f9, 0xfffdf7f3, 0xfec9f7f3, 0xfe34f7f3, 
+    0xfee1f7f3, 0xfd64f7f3, 0xf7e82000, 0x2000f80b, 0xffa6f7fb, 0xb240499d, 0xf8b2f7e6, 0xf7fb2001, 
+    0x499aff9f, 0x3110b240, 0xf8aaf7e6, 0xf7fb2002, 0x4996ff97, 0x3120b240, 0xf8a2f7e6, 0xf7fb2003, 
+    0x4992ff8f, 0x3130b240, 0xf89af7e6, 0x823cf8df, 0x24002500, 0x1705eb08, 0x5d384621, 0xb2424240, 
+    0xf7fe4628, 0x1c64f98a, 0x2c10b2e4, 0x1c6dd3f4, 0x2d04b2ed, 0x2000d3ed, 0xf94ef7fe, 0xf7fe2003, 
+    0x2300f98d, 0x21014882, 0xf00a461a, 0x2100ff34, 0xf7e84608, 0x4c7ffc83, 0x0500f241, 0x78214628, 
+    0xfb52f7e7, 0x22002101, 0xf7f94608, 0x2004fe8b, 0xff8af7fd, 0x46287821, 0xfb46f7e7, 0xf7e72001, 
+    0x7821ffb1, 0xf7e701e8, 0x2000fb3f, 0xffaaf7e7, 0xf7e82002, 0x4d70fc87, 0x22022300, 0x4628210c, 
+    0xff09f00a, 0xb1207830, 0xd0042801, 0xd0022802, 0x2005e004, 0x2006e000, 0xff68f7fd, 0x46282301, 
+    0x029f220a, 0xf00a4639, 0x7821fef6, 0xf7e74638, 0x2001fb1b, 0xff86f7e7, 0x01794855, 0xf00a3816, 
+    0x7832fed0, 0x20082101, 0xff80f7ee, 0x485b2300, 0x461a2101, 0xfedff00a, 0xffc5f7ee, 0x20014c58, 
+    0xf7e87821, 0x4957fdb4, 0x78202201, 0x21027008, 0xf00a4855, 0xb110fede, 0xf7e82000, 0x7820fd94, 
+    0xf98df7e9, 0xf7f92004, 0xe8bdfede, 0x22014ff8, 0x46104611, 0xbe26f7f9, 0x5ff0e92d, 0x20022100, 
+    0xfa7af7e7, 0x23014842, 0x02592209, 0xf00a38a0, 0x2000feb2, 0xff46f7e7, 0xf85af7e6, 0x483c2301, 
+    0x03dc220f, 0x4621388e, 0xfea5f00a, 0xf7e82001, 0x4837fc19, 0x38402100, 0xfe83f00a, 0x23014834, 
+    0x21802207, 0xf00a38a0, 0x4e32fe96, 0x46281165, 0xf7e77831, 0x4f30fab9, 0x220f2301, 0x37724621, 
+    0xf00a4638, 0x2380fe88, 0x22004638, 0xf00a1e69, 0x2306fe82, 0x21ff2200, 0xf00a1cb8, 0x2200fe7c, 
+    0x73f8f641, 0x1d38217f, 0xfe75f00a, 0x0902f1a7, 0x46484621, 0xfe55f00a, 0x0180f248, 0xf00a4648, 
+    0x7831fe50, 0xf7e74628, 0xf44ffa8f, 0xf2400800, 0x464711f4, 0xf7e04640, 0x491cf864, 0xf7e04638, 
+    0x4815f84f, 0xfe3af00a, 0x46384601, 0xf848f7e0, 0xa044f8df, 0x0a80f10a, 0xf00a4650, 0x4601fe2f, 
+    0xf7e04638, 0x4912f83d, 0xf7e04638, 0xe021f839, 0xd0035136, 0xd1800048, 0x00032411, 0x00032224, 
+    0x000322e8, 0x8421b7ed, 0x84217bde, 0x0003308c, 0xd00304a0, 0x0003227f, 0xd0035022, 0xd0036104, 
+    0x0003227e, 0x00032238, 0xd03d104a, 0x90010000, 0xdcba01f5, 0xf00a4650, 0x4601fe01, 0xf00a48ab, 
+    0x2300fe00, 0x220a4629, 0xf00a4648, 0x2301fe14, 0x220a4629, 0xf00a4648, 0x2300fe0e, 0x220a4629, 
+    0xf00a4648, 0x48a2fe08, 0xf246220d, 0xf9900100, 0xb2830000, 0xf00a4648, 0x2300fdfe, 0x22054648, 
+    0xf00a2120, 0x2301fdf8, 0x22054648, 0xf00a2120, 0xf8dffdf2, 0x2700b258, 0x0be6f1ab, 0x220f4621, 
+    0xf00a4658, 0xb918fdf6, 0xb23f1c7f, 0xdbf542a7, 0xfe91f7fb, 0xf2404682, 0x464711f4, 0xf7df4640, 
+    0x498cffe0, 0xf7df4638, 0x4658ffcb, 0xfdb6f00a, 0x46384601, 0xffc4f7df, 0x46384651, 0xffc0f7df, 
+    0x46384985, 0xffbcf7df, 0xf2402201, 0x2100102b, 0xfbb7f7e8, 0xf7e92074, 0x2301fe0b, 0x220f4621, 
+    0xf00a4648, 0x4f7dfdb8, 0x220b2300, 0x0100f640, 0xf00a4638, 0x2300fdb0, 0x220a4629, 0xf00a4638, 
+    0x2300fdaa, 0x2100f240, 0x46382209, 0xfda3f00a, 0x46382208, 0x01512300, 0xfd9df00a, 0x46382303, 
+    0x21c02206, 0xfd97f00a, 0xf647486c, 0x23007700, 0x22084639, 0xf00a1c80, 0xf8dffd8e, 0x230081a0, 
+    0x461a217f, 0x0804f108, 0xf00a4640, 0x2300fd84, 0x22084639, 0xf00a4640, 0x2002fd7e, 0xfaf2f7e8, 
+    0x46082100, 0xfab8f7e8, 0x78384f5d, 0x2801b120, 0x2802d004, 0xe004d002, 0xe0002005, 0xf7fd2006, 
+    0x4856fdd5, 0x220a2301, 0x30084629, 0xfd63f00a, 0x46287831, 0xf988f7e7, 0x4621484c, 0xf00a388a, 
+    0x783afd40, 0x20082101, 0xfdf0f7ee, 0x484d2300, 0x461a2101, 0xfd4ff00a, 0x46287831, 0xf974f7e7, 
+    0xfe31f7ee, 0x20014d48, 0xf7e87829, 0x4947fc20, 0x78282201, 0x21027008, 0xf00a4845, 0xb110fd4a, 
+    0xf7e82000, 0x7828fc00, 0xfff9f7e8, 0xe8bd4620, 0x21025ff0, 0x4210f04f, 0xbf81f7df, 0x4604b570, 
+    0xfa91f7e1, 0xf7e82000, 0x4d34fa9d, 0x220a2300, 0x4100f240, 0x46283508, 0xfd1df00a, 0x20012100, 
+    0xfa5af7e8, 0x20012100, 0xfa68f7e8, 0x46282301, 0x21402206, 0xfd0ff00a, 0x46282301, 0x21202205, 
+    0xfd09f00a, 0x2018492b, 0x60084a21, 0x492a2000, 0x3000f991, 0xf99154d0, 0x20013001, 0xf99154d0, 
+    0x20023002, 0xf99154d0, 0x20031003, 0xf7fb5450, 0x2000ff83, 0xfd64f008, 0xb2e02100, 0xf9a6f008, 
+    0x461a2300, 0xb2e04619, 0xfb75f008, 0x06ea481b, 0xf0007800, 0x1250010f, 0xd0042901, 0xd0082902, 
+    0xd00c2903, 0x2116e00d, 0xff29f7df, 0xfe14f7ff, 0x2117e007, 0xff23f7df, 0xfcbcf7ff, 0xf7ffe001, 
+    0xe8bdfc84, 0x20024070, 0xb897f7e7, 0xd00351aa, 0x000323ac, 0x90010001, 0xdcba01f5, 0xd003501a, 
+    0x00032411, 0xd0036104, 0x0003227e, 0x00032238, 0xd03d104a, 0x0003222c, 0x000323b4, 0x000322e5, 
+    0x4ff8e92d, 0x46044d58, 0xb1208e80, 0xd00d287e, 0xd136287f, 0x4954e014, 0x32fff04f, 0x31086868, 
+    0xf8c0f006, 0xd1071d01, 0xe029207e, 0x2200494e, 0x31086868, 0xf8b6f006, 0xd0201d41, 0xd1ea2801, 
+    0x30084849, 0x28298800, 0x4848d1e5, 0x21042202, 0xfc8ff00a, 0xb2c04b46, 0x28014f46, 0xf04f4e46, 
+    0xf44f59a8, 0xf6400a00, 0xf04f0100, 0xf04f0800, 0x4618020b, 0xf00ad007, 0xb1e8fc7c, 0x207fe03c, 
+    0xe8bd86a0, 0xf00a8ff8, 0x2801fc74, 0xf996d134, 0x28030000, 0x2805d006, 0x2804d004, 0x7838d002, 
+    0xd1292801, 0xf240464a, 0x46501160, 0xfea7f7df, 0xf7e82000, 0xe01ffb18, 0x0000f996, 0xd0062803, 
+    0xd0042805, 0xd0022804, 0x28017838, 0x464ad114, 0x1161f240, 0xf7df4650, 0x4828fe92, 0xb9107800, 
+    0xf7e82001, 0x2200fb00, 0x0300f641, 0x46104611, 0x8000f8cd, 0xfc7cf7ea, 0xf9a6f7e1, 0x22024820, 
+    0xf00a2104, 0x2201fc36, 0x481e4603, 0xf00a2102, 0xf996fc22, 0x28030000, 0x2805d003, 0x2804d001, 
+    0xf001d101, 0x4818f9aa, 0xb1587800, 0x1c407828, 0x7028b2c0, 0xd187280a, 0xf7e02000, 0xf885fd23, 
+    0xe7688000, 0xf7e02001, 0xe764fd1d, 0x21012200, 0xf2afb510, 0xf0051053, 0x2108fe41, 0xf0052003, 
+    0x4901ff9f, 0xbd106048, 0x00032c8c, 0xd2054084, 0xd0035026, 0x00032271, 0x00032238, 0x00032391, 
+    0xd0039026, 0xd03c801a, 0x000322d9, 0x4ff8e92d, 0x46044db4, 0x28ec8e80, 0xd07c686b, 0xb150dc05, 
+    0xd0122882, 0xd1772883, 0x28ede018, 0x28f4d003, 0x28f5d073, 0x49acd170, 0x32fff04f, 0xf0056868, 
+    0x1d01fff1, 0x2082d106, 0x49a7e0d0, 0x46182200, 0xffe8f005, 0xd0221d41, 0xd1ec2801, 0xf04f4ea2, 
+    0xf04f3aff, 0x46574220, 0xf9b64650, 0xf7df1000, 0xf996fe06, 0x46381004, 0xf7df4a9c, 0xf9b6fe00, 
+    0xf8df0000, 0xf8df826c, 0x2826b26c, 0xd0084f9a, 0xd1d02873, 0x0000f8d8, 0xd0702801, 0x2083e0eb, 
+    0x2000e0a4, 0xfc54f008, 0xf8df4894, 0x88009254, 0xd0122801, 0xf0082000, 0xf996fc03, 0x29001003, 
+    0xf04fddb9, 0x46504260, 0xfdd9f7df, 0x0003f996, 0xd0752804, 0xd0742805, 0x488ae09b, 0x21042202, 
+    0xfb87f00a, 0xf04f2801, 0xd1070a01, 0x22044885, 0x1f002110, 0xfb7df00a, 0xd01c2801, 0xf0082000, 
+    0x2100fbdf, 0xf0082003, 0x2100f821, 0xf8997933, 0x20032000, 0xe055e002, 0xe05fe069, 0xf9ebf008, 
+    0xf8d2f7e1, 0x22014877, 0xf8cd2104, 0xf44fa000, 0xf7e63380, 0xf997ffd0, 0x21000000, 0xfc67f008, 
+    0x4f724871, 0x28017800, 0x7838d012, 0xd00f2801, 0x46082100, 0xfe2bf008, 0x486d2208, 0xf00a0151, 
+    0x70b0fb48, 0xf8d82073, 0x29011000, 0xe010d008, 0x20012100, 0xfe1bf008, 0xa002f886, 0xe062e7f2, 
+    0x1000f89b, 0xd1042901, 0x290278f1, 0x7839d101, 0x8030b141, 0x49542200, 0xf0056868, 0x1d01ff14, 
+    0xe020d01a, 0x290078b1, 0xaf45f43f, 0x22008030, 0x6868494d, 0xff07f005, 0xd1081d01, 0xe01520ec, 
+    0xe023e017, 0x22004948, 0xf0054618, 0x1d40fefc, 0xaf31f47f, 0xe00920ed, 0xe00720f4, 0x22004942, 
+    0xf0054618, 0x1d40fef0, 0x20f5d1f2, 0xe8bd86a0, 0xf8998ff8, 0x28030000, 0x2100d10b, 0xf0072002, 
+    0x2300ffa5, 0x46192203, 0xe0102004, 0x78004841, 0x7838b180, 0xd1022804, 0x7800483f, 0x78f0b150, 
+    0xf0072100, 0x2200ff93, 0x78f07933, 0xf0084611, 0xe700f962, 0x20032100, 0xff88f007, 0x20032300, 
+    0x4619461a, 0xf89be7f3, 0x28010000, 0xf8dfd113, 0x038180cc, 0x4640220e, 0xfacbf00a, 0xd10a2801, 
+    0x46402204, 0xf00a2110, 0x2801fac4, 0xf7f0d103, 0xf008f83f, 0xf996fbab, 0xf9950002, 0x42881000, 
+    0xf997d105, 0xf9951000, 0x42912001, 0x7028d0d1, 0xf9962200, 0x70691003, 0xfc55f008, 0x481c2208, 
+    0xf00a0151, 0x4e1efaa6, 0x21202205, 0x46304603, 0xfa91f00a, 0x2202481b, 0x1001f995, 0x211c5c43, 
+    0xf00a4630, 0xe6b6fa88, 0x21012200, 0xf2afb510, 0xf00520c3, 0x2108fcc3, 0xf0052002, 0x4901fe21, 
+    0xbd106048, 0x00032c9c, 0x000402b8, 0xe0000100, 0x00032374, 0x0003237c, 0x0003227e, 0x0003233c, 
+    0x00032411, 0xd2054084, 0x00032271, 0x00032279, 0xd28f2002, 0x00032307, 0x00032306, 0xd0039026, 
+    0xd03c8028, 0x0002e096, 0x4ff0e92d, 0x9408f8df, 0xb0852001, 0x5298f04f, 0x1000f999, 0xfc9ff7df, 
+    0xf8df48fe, 0x7800a3fc, 0xf8dfb3a0, 0x2206b3f8, 0x46582140, 0xfa4df00a, 0x08fff000, 0x22054658, 
+    0xf00a2120, 0x4cf7fa46, 0x2201b2c7, 0x2102343c, 0xf00a4620, 0xb2c6fa3e, 0x22004620, 0xf00a2101, 
+    0x2208fa38, 0x4658b2c5, 0xf00a0151, 0xb2c4fa32, 0x22074658, 0xf00a2180, 0xb2c1fa2c, 0xf89a48ea, 
+    0x78032000, 0xe9cd9702, 0xe9cd8303, 0x462b6200, 0xe00c4622, 0x2201e7ff, 0x1000f89a, 0x46032000, 
+    0x1001e9cd, 0x0203e9cd, 0x46014602, 0xf2489000, 0xf7ef0000, 0x2200f8ae, 0xf7ef4611, 0x210ff897, 
+    0x1000f889, 0xe8bdb005, 0xf7e14ff0, 0x48d2bfcd, 0xb570212c, 0x5498f04f, 0x70414622, 0xf7df2001, 
+    0x48d2fc3e, 0x28126800, 0x2813d012, 0x2815d013, 0x2816d014, 0x2817d015, 0x2818d016, 0x2811d017, 
+    0x28ffd018, 0x2801d019, 0x2810d01a, 0xe01fd01b, 0x46222120, 0x2121e019, 0xe0164622, 0x46222123, 
+    0x2124e013, 0xe0104622, 0x46222133, 0x2136e00d, 0xe00a4622, 0x4622211f, 0x212fe007, 0xe0044622, 
+    0x46222130, 0x211ee001, 0x20014622, 0xfc07f7df, 0xf00a48b7, 0x2200f993, 0x20014601, 0xfbfff7df, 
+    0x380a48b0, 0xf98af00a, 0x48ae4604, 0xf00a380c, 0x4605f985, 0x380e48ab, 0xf980f00a, 0x46294622, 
+    0x4070e8bd, 0xbf8df7e1, 0x5ffce92d, 0x20014ea2, 0x5298f04f, 0x1001f996, 0xfbe1f7df, 0x380a48a1, 
+    0xf96cf00a, 0x489f4607, 0xf00a380c, 0xf8dff967, 0x46058274, 0x080ef1a8, 0xf00a4640, 0x4604f95f, 
+    0x4629463a, 0xff6df7e1, 0xf248220f, 0x46400100, 0xf97ff00a, 0x1002f996, 0x08fff000, 0xb254f8df, 
+    0x0a00f04f, 0x9250f8df, 0xd00e2904, 0xd05d2932, 0xf04f2905, 0xd0785298, 0x2001211c, 0xfbaff7df, 
+    0x0f01f1b8, 0x202bd070, 0x2001e0e6, 0x5298f04f, 0xfba5f7df, 0xf3c46970, 0x43082141, 0xf5b06170, 
+    0xd01f6f85, 0x42884985, 0x07a8d1ea, 0x2001d000, 0xf3c54983, 0x70080240, 0x0001f005, 0x1000f89b, 
+    0x4a804311, 0x1000f88b, 0x43187813, 0x4a7e7010, 0x4a7e7813, 0xe9cd7812, 0x4a7d2300, 0x3000f899, 
+    0xe03d7812, 0xf3c4497b, 0x4a7b1082, 0x4d7b2804, 0x4b7c4f7b, 0xf881d00c, 0x2100a000, 0xa000f882, 
+    0xa000f885, 0xa000f887, 0xf00a4618, 0xe7b7f8fa, 0x70082001, 0x0080f3c4, 0xf3c47010, 0x70280040, 
+    0x0001f004, 0x05e07038, 0xe7ed0c01, 0xf04f2001, 0xf7df5298, 0x4620fb54, 0xfc6ef7ef, 0x7800486a, 
+    0xd19d2801, 0x78014860, 0x78004860, 0x0100e9cd, 0xf899485f, 0xf89b3000, 0x78021000, 0x78004859, 
+    0xfd70f7ef, 0xe000e78c, 0x2001e075, 0xfb37f7df, 0x484e69b1, 0xf5a14a5d, 0x3b974358, 0x2310d005, 
+    0x4568f5a1, 0xd0363d6d, 0xf005e03c, 0x23ff0103, 0x141ff361, 0xf3c580b4, 0xf5b1018b, 0xd0046f80, 
+    0x7f60f415, 0x2111d010, 0x2c10e018, 0x2c20d00e, 0xb15cd00c, 0xd00e2c01, 0xd00e2c02, 0xd00f2c03, 
+    0xd00f2c04, 0xd00f2c05, 0xe00f6003, 0x60012112, 0x7030200f, 0x2113e017, 0x2115e000, 0xe0126001, 
+    0xe7fb2116, 0xe0002117, 0x60012118, 0xd00a0b78, 0x70100b78, 0xf3c4e009, 0x29021145, 0x0861d102, 
+    0xd0090709, 0xf8826003, 0x4839a000, 0xb1287800, 0xb1187810, 0xe0022001, 0xe7df2101, 0x49352000, 
+    0xf3c77008, 0x4834010b, 0xf86bf00a, 0x21004832, 0xf00a1c80, 0x8b30f866, 0x482fb281, 0xf00a1d00, 
+    0x69b0f860, 0x21ff2200, 0x4307f3c0, 0x1d80482a, 0xf871f00a, 0x2002e714, 0xe8bd7070, 0xe92d9ffc, 
+    0x4d0d47fc, 0x5a98f04f, 0x46522001, 0x1001f995, 0xfab5f7df, 0x380a480b, 0xf840f00a, 0x48094604, 
+    0xf00a380c, 0xf8dff83b, 0x4606901c, 0x090ef1a9, 0xf00a4648, 0xe031f833, 0x00032ca4, 0x0003240b, 
+    0x0003230c, 0xd28e0040, 0x00032308, 0x0003222c, 0xd28fffd0, 0x00032415, 0x00032413, 0x00fa073e, 
+    0x0003240e, 0x00032414, 0x00032407, 0x00032408, 0x00032412, 0x000323fe, 0x00032401, 0x00032402, 
+    0x00032403, 0xd03c8026, 0x0003240c, 0x00032335, 0x00032334, 0x00032333, 0xd003515c, 0x46314622, 
+    0xfe0ff7e1, 0xf248220f, 0x46480100, 0xf821f00a, 0x08fff000, 0x0100f242, 0x4648220d, 0xf819f00a, 
+    0xf240b2c7, 0x220071ff, 0xf00a4648, 0x2f01f812, 0xd108b2c0, 0xd0122809, 0x280b2703, 0x2805d03d, 
+    0x2806d050, 0x2129d05a, 0x20014652, 0xfa47f7df, 0x0f01f1b8, 0x202bd001, 0xe8bd7068, 0x212787fc, 
+    0x20014652, 0xfa3bf7df, 0x50c0f414, 0x2001d000, 0x4efe49fd, 0x70084ffe, 0x20c0f3c4, 0x703049fd, 
+    0x3000f3c4, 0xf3c47038, 0x700800c0, 0xea00200e, 0x48f91154, 0x48f97001, 0xffb3f009, 0x48f949f8, 
+    0x78007809, 0x0100e9cd, 0x783148f7, 0x48f77803, 0x78387802, 0xfc46f7ef, 0x2128e7ca, 0x20014652, 
+    0xfa0df7df, 0x4af2b2e0, 0xea4649f2, 0x61284000, 0xd1024290, 0x2000f3c4, 0x2000e000, 0x20327008, 
+    0xe015706f, 0x46522125, 0xf7df2001, 0x0370f9f8, 0x0084ea40, 0x20046168, 0xe009706f, 0x46522126, 
+    0xf7df2001, 0xea44f9ec, 0x61a820c6, 0x706f2005, 0xe79d70a8, 0x43f8e92d, 0xf04f4cdf, 0x20015898, 
+    0xf9944642, 0xf7df1001, 0x4fdcf9da, 0xf0094638, 0x2200ff65, 0x46014606, 0xf7df2001, 0x220cf9d0, 
+    0x0100f241, 0xf0094638, 0x2500ff84, 0xf7efb130, 0x200dfa24, 0x20027020, 0xe0167060, 0xf248220f, 
+    0x46380100, 0xff75f009, 0x2011b128, 0x20067020, 0x70e57060, 0x202de009, 0x202b7020, 0xb9267060, 
+    0x4642212e, 0xf7df2001, 0x48c5f9aa, 0x70052104, 0xf7fb2018, 0x2300fe05, 0x22019500, 0x46184619, 
+    0xfcdef7fb, 0x200149bf, 0x70082200, 0x49be2004, 0xfb38f7e6, 0x43f8e8bd, 0xf7e6200b, 0x49b6bc14, 
+    0x30fff04f, 0x70084ab9, 0x70887048, 0x61882000, 0x61086148, 0x60112110, 0x700849b5, 0x700849b5, 
+    0x700849b5, 0x700849b5, 0x700849b5, 0x700849a1, 0x700849b4, 0x700849a2, 0x700849a2, 0x700849a5, 
+    0x700849b1, 0x70084998, 0x7008499f, 0x7008499f, 0x70084997, 0x70084995, 0x700849ac, 0x700849ac, 
+    0x700849ac, 0x700849ac, 0xb57c4770, 0xffc7f7ff, 0x210848aa, 0xfee5f009, 0xf24148a9, 0x4c970500, 
+    0x8802341a, 0x7facf5b2, 0xf5b2d008, 0xd0057fa4, 0x7fb4f5b2, 0xf5b2d002, 0xd1057fbc, 0x46292300, 
+    0x4620220c, 0xfee7f009, 0x46202300, 0x21042202, 0xfee1f009, 0x23004889, 0x461a2101, 0xf0093052, 
+    0xf7effeda, 0x2000f98a, 0x46039000, 0x46014602, 0xf7ef9001, 0x4893fb57, 0xf0092100, 0x4877feb2, 
+    0x304a2100, 0xfeadf009, 0x21004874, 0xf009304c, 0x4872fea8, 0x304e2100, 0xfea3f009, 0x2300486f, 
+    0x461a21ff, 0xf0093050, 0x2001feb6, 0xfb8bf7e6, 0xf7e62011, 0x2012fb88, 0xfb85f7e6, 0xf7ee2002, 
+    0x4881febe, 0x21042202, 0xfeb3f009, 0x28012401, 0x486cd109, 0x496c2201, 0x20047004, 0xfa92f7e6, 
+    0xf7e6200b, 0x4979fb70, 0x2300201b, 0x7008220c, 0x48614629, 0x48747044, 0xf0091d80, 0xb002fe8c, 
+    0x20012102, 0x4070e8bd, 0x4270f04f, 0xb8d7f7df, 0x5ff0e92d, 0x46054c58, 0xf04f8e80, 0xb1300901, 
+    0xd01428f0, 0xd13428f1, 0x900cf8c4, 0xf7ffe01a, 0x4951ff36, 0x32fff04f, 0x311c68a0, 0xfa92f005, 
+    0x1d0060e0, 0x68e0d001, 0x20f0e008, 0x494ae020, 0x68a02200, 0xf005311c, 0x60e0fa85, 0xd0161d41, 
+    0xd1e62801, 0xf04f4f44, 0x20014620, 0x371c4632, 0x1000f9b7, 0xf8a3f7df, 0x1000f9b7, 0xd00a293a, 
+    0xd00e293b, 0x46322001, 0xf899f7df, 0x20f1e7d1, 0xe8bd86a8, 0xf7ff9ff0, 0x7862ff38, 0x78212001, 
+    0x484be1c2, 0x0a00f04f, 0x29017801, 0xf994d00c, 0x28010001, 0x2802d00c, 0x2803d00d, 0x2806d00e, 
+    0x2807d00f, 0xe011d010, 0x9001f884, 0xa000f880, 0xfe90f7ff, 0xf7ffe00a, 0xe007fdb2, 0xfc84f7ff, 
+    0xf000e004, 0xe001fa13, 0xf9d9f000, 0x282b7860, 0xf7ffd101, 0xf994fc1c, 0x290d1000, 0x290ed06e, 
+    0x2931d07d, 0x2934d069, 0x0605f24a, 0x2935d073, 0xf8dfd072, 0x290fb068, 0x0b06f10b, 0x262dd06d, 
+    0xd06b2910, 0x80acf8df, 0xf2422919, 0xd0790701, 0xd078291a, 0xd0772911, 0xd0762912, 0xd0752913, 
+    0xd074292d, 0xe049e160, 0x00032410, 0x00032415, 0x00032414, 0x00032409, 0x000322b2, 0xd0035112, 
+    0x00032407, 0x00032408, 0x00032413, 0x00032412, 0x002901d4, 0x0003240c, 0x00032ca4, 0xd28e0026, 
+    0x00032366, 0x0003240a, 0x684ee180, 0x0003222c, 0x00032401, 0x00032402, 0x00032403, 0x000323fe, 
+    0x00032405, 0x00032406, 0x0003240e, 0x00032422, 0x00032333, 0x00032335, 0x00032336, 0xd28f228a, 
+    0x00032392, 0xd28f0076, 0xd0039026, 0x00032239, 0x0003227a, 0xd28fffce, 0xe029e011, 0xf04f2001, 
+    0xf7de5298, 0x2200ffec, 0x0009f24a, 0xf7ee4611, 0x2034fc2d, 0xe01ee014, 0xe046e02b, 0x2001e056, 
+    0x5298f04f, 0xffdbf7de, 0x212948dc, 0xea417800, 0xf2402200, 0xf24a11d4, 0xf7ee000b, 0x2031fc17, 
+    0xe0587020, 0xe07fe061, 0xe0a3e0a1, 0xe0c9e0b1, 0xfb1af7ff, 0x2001e0e2, 0x5298f04f, 0xffbff7de, 
+    0x12cff240, 0x71d0f240, 0xf7ee4630, 0x2035fbff, 0x2001e7e6, 0x5298f04f, 0xffb1f7de, 0x20194fc8, 
+    0x70202207, 0x46382180, 0xfd63f009, 0x46062208, 0x01514638, 0xfd5df009, 0x0040ea46, 0xf248b281, 
+    0x22004000, 0xfbe2f7ee, 0x2001e025, 0x5298f04f, 0xff95f7de, 0x46584631, 0xfd23f009, 0xf2402100, 
+    0x4630120a, 0xfbd2f7ee, 0xe7b92010, 0xf04f2001, 0xf7de5298, 0x48b3ff84, 0x0200f04f, 0x46114fb2, 
+    0x28017800, 0x2000d00a, 0xfbc0f7ee, 0x46382100, 0xfd07f009, 0xf7e17026, 0xe08ffaf7, 0x1007f240, 
+    0xfbb4f7ee, 0x3180f248, 0x2001e7f1, 0x5298f04f, 0xff65f7de, 0x282c7860, 0x48a4d103, 0x28016800, 
+    0x2297d007, 0x0006f24a, 0xf7ee211b, 0x201afb9f, 0x2200e786, 0x46114638, 0xfb98f7ee, 0x46404639, 
+    0xfcdff009, 0xe06c7026, 0xf04f2001, 0xf7de5298, 0x4897ff46, 0xf2412105, 0x88000700, 0x707ef400, 
+    0x0040eb01, 0x4600f440, 0x1f80488f, 0xfcc6f009, 0x020bf3c0, 0xf64f488f, 0x780071ff, 0x3040ea01, 
+    0x43024639, 0xf7ee4630, 0x200efb71, 0xf000e758, 0xe043f86c, 0xf04f2001, 0xf7de5298, 0xf24aff20, 
+    0x4646010a, 0xf0094640, 0x2013fcac, 0x46307020, 0x2001e010, 0x5298f04f, 0xff11f7de, 0x30384878, 
+    0xfc9cf009, 0x010ef000, 0x46404647, 0xfc99f009, 0x70264638, 0xfc92f009, 0x46012200, 0xf7de2001, 
+    0xe01bfefe, 0xf04f2001, 0xf7de5298, 0x2100fef8, 0x2000f44f, 0xf8c8f7e6, 0x21004869, 0xf0093812, 
+    0x4867fc80, 0x38102100, 0xfc7bf009, 0x46584639, 0xfc77f009, 0x46404639, 0xfc73f009, 0x282d7820, 
+    0x7860d102, 0xd003282c, 0x20027862, 0xe00b7821, 0x20014961, 0x5298f04f, 0xa000f881, 0xf7de211d, 
+    0x7862fece, 0x78212003, 0xf8def7e1, 0x2200e601, 0xb5102101, 0x4027f2af, 0xfeb0f004, 0x20042108, 
+    0xf80ef005, 0x60884955, 0xb570bd10, 0x20014c53, 0x5298f04f, 0x1000f994, 0xfeb1f7de, 0x4d5078e2, 
+    0x2a01b132, 0x0100f248, 0x2a02d004, 0xe00ad006, 0x0108f24a, 0xf0094628, 0xe004fc34, 0xf0094628, 
+    0x2012fc30, 0x46287020, 0xfc28f009, 0x46012200, 0xf7de2001, 0x78e0fe94, 0x70e01c40, 0xe92dbd70, 
+    0x4c3e41f0, 0x5698f04f, 0x46322001, 0x1001f994, 0xfe85f7de, 0x220f4f3a, 0x0100f248, 0x46381cbf, 
+    0xfc37f009, 0x46052200, 0x71fff240, 0xf0094638, 0x4680fc30, 0xf0094638, 0x2200fc01, 0x20014601, 
+    0xfe6df7de, 0x1002f994, 0xd1092908, 0x46322001, 0xfe65f7de, 0x4641482b, 0xfbf3f009, 0x70602006, 
+    0xd1012d00, 0x7060202b, 0x81f0e8bd, 0x41f0e92d, 0x20014c22, 0x5298f04f, 0x1001f994, 0xfe4ff7de, 
+    0x220f4f1f, 0x0100f248, 0x46381cbf, 0xfc01f009, 0x4680220d, 0x0100f242, 0xf0094638, 0x2200fbfa, 
+    0xf2404606, 0x463871ff, 0xfbf3f009, 0x46384605, 0xfbc4f009, 0x46012200, 0xf7de2001, 0x2e01fe30, 
+    0x2d0ad105, 0x2008d103, 0x200770a0, 0xf1b87060, 0xd1c90f00, 0x7060202b, 0x0000e7c6, 0x0003240b, 
+    0xd28e0040, 0x000323fd, 0xd03c8024, 0x0003222c, 0x00032392, 0x00032334, 0x00032239, 0x00032ca4, 
+    0xd28fffce, 0xd0035112, 0x41f0e92d, 0x255c4847, 0xfb94f009, 0x48454604, 0xf0091e80, 0x4e44fb8f, 
+    0x717ff404, 0xf2454a43, 0x80311744, 0x0103f004, 0xf5a08011, 0x3902412e, 0x0403f024, 0xf5a4d115, 
+    0x384040a2, 0x3808d024, 0x42bcd022, 0x3808d020, 0x3808d01e, 0x3818d01c, 0x1f00d01a, 0x3014d018, 
+    0x3808d016, 0x3810d014, 0x2000d012, 0x4832b190, 0xf2402208, 0xf0093100, 0x4930fb8c, 0x7008b240, 
+    0xf5b18831, 0xd00e7fa8, 0x7facf5b1, 0xe013d00b, 0xe7eb2001, 0xfa9cf7f9, 0xf64b4827, 0x308031b0, 
+    0xfb4ff009, 0x07c0e7fe, 0xbf30d001, 0x4824e004, 0x0100f640, 0xfec0f7e4, 0x22004e21, 0x36082101, 
+    0xf0094630, 0x2801fb66, 0x2301d105, 0x22044630, 0xf0092110, 0x481afb50, 0x71fff64f, 0xf0093010, 
+    0x2301fb30, 0x22024630, 0xf0092104, 0x2301fb44, 0x21024630, 0xf009461a, 0x4912fb3e, 0x60086828, 
+    0x0133f643, 0x3818480c, 0xfb1bf009, 0xf245480a, 0x381a1103, 0xfb15f009, 0xf923f7f9, 0xd10242bc, 
+    0x20014909, 0xe8bd7008, 0x000081f0, 0xd0020006, 0x00032392, 0x00032394, 0xd03c8038, 0x00032228, 
+    0xd03c8310, 0x00032374, 0x00032362, 0x4d1eb570, 0x8e804604, 0x285eb120, 0x285fd00d, 0xe014d125, 
+    0xf04f4919, 0x682832ff, 0xf0041d09, 0x1d01ff2b, 0x205ed107, 0x4914e018, 0x68282200, 0xf0041d09, 
+    0x1d41ff21, 0x2801d00f, 0x4e0fd1ea, 0x88301d36, 0xd1e52862, 0x2102480d, 0xfad3f009, 0x0002f9b6, 
+    0xfd7ff7de, 0x205fe7dc, 0xbd7086a0, 0x21012200, 0xf2afb510, 0xf0040067, 0x2108fd21, 0xf0042003, 
+    0x4901fe7f, 0xbd106008, 0x00032cc8, 0xd03c806e, 0x41f0e92d, 0x22014df9, 0x46282106, 0xfad9f009, 
+    0x1cb74ef7, 0xb3201eb4, 0x46282201, 0xf0092106, 0x2801fad0, 0x2201d029, 0x21064628, 0xfac9f009, 
+    0xd1252802, 0x0100f243, 0xf0094630, 0x219cfa9a, 0xf0094638, 0x2301fa96, 0x22004620, 0xf009210f, 
+    0x4620faaa, 0x41f0e8bd, 0x22042301, 0xf0092110, 0xf240baa2, 0x46307507, 0xf0094629, 0x4629fa82, 
+    0xf0094638, 0x230ffa7e, 0xf240e7e6, 0xe7db1100, 0x81f0e8bd, 0x4604b570, 0xf00948d8, 0xf7fffa6f, 
+    0x2100ffb7, 0xf7e62001, 0x4dd5ffc7, 0x2200b2a3, 0x21013d24, 0xf0094628, 0x2003fa7e, 0xfff2f7e6, 
+    0x0301f04f, 0x2202b134, 0x46282104, 0x4070e8bd, 0xba71f009, 0x21022201, 0xb51fe7f7, 0x90002000, 
+    0x90029001, 0x46689003, 0xff57f7e7, 0xb2819800, 0xf00948c4, 0x9800fa46, 0x48c20c01, 0xf0091c80, 
+    0x9801fa40, 0x48bfb281, 0xf0091d00, 0x9801fa3a, 0x48bc0c01, 0xf0091d80, 0x9802fa34, 0x48b9b281, 
+    0xf0093008, 0x9802fa2e, 0x48b60c01, 0xf009300a, 0x9803fa28, 0x48b3b281, 0xf009300c, 0x9803fa22, 
+    0x48b00c01, 0xf009300e, 0xbd1ffa1c, 0x4caeb570, 0xf04f2001, 0xf24052a0, 0x06051103, 0x462870e0, 
+    0xfc7df7de, 0x11f4f240, 0xf7de4628, 0xf64efc2a, 0x462861ee, 0xfc14f7de, 0x462849a4, 0xfc10f7de, 
+    0x48a32300, 0x461a2101, 0xfa15f009, 0x200049a1, 0x70084aa1, 0x7f201369, 0xf0001c40, 0xeb000007, 
+    0xeb021000, 0x60810080, 0xf7e52002, 0xe8bdfeed, 0x20034070, 0xbee8f7e5, 0x4ff0e92d, 0xf04f469b, 
+    0xf8c20a00, 0xf240a000, 0x46902300, 0xf8ab4689, 0xf04f3000, 0x9a090c81, 0xf8a24656, 0x2500a000, 
+    0xeb06e02c, 0xf1be0e05, 0xd4040f02, 0x018eeb00, 0x7c08f851, 0x2700e000, 0x46544652, 0x33fff04f, 
+    0xd40618e9, 0xda044561, 0x0103eb0e, 0x1021f850, 0x2100e000, 0xda03428f, 0x463a4614, 0xe007460f, 
+    0xda02428a, 0x460a4614, 0x428ce002, 0x460cda00, 0x2b031c5b, 0x1c6ddbe4, 0x402ef849, 0xdbd04565, 
+    0xe01f2300, 0xf8d818f1, 0xf8505000, 0xf8594021, 0x1a611021, 0x1a6d17ca, 0x0402eb7a, 0x2a00da11, 
+    0x2100da01, 0xf04fe007, 0x24004580, 0x41941a6d, 0xf04fda01, 0xf8c85100, 0xf8ab1000, 0x99093000, 
+    0x1c5b800e, 0xdbdd4563, 0xebb64466, 0xdba60f8c, 0x8ff0e8bd, 0x43f8e92d, 0x460f2400, 0x4616461d, 
+    0xf04f9400, 0xf8dd52a0, 0xf9b08020, 0xf04f1000, 0xf7de7080, 0x4859fbd4, 0x48537004, 0x710470c4, 
+    0x68004857, 0x4857b178, 0x28017800, 0x2100d008, 0xf201484f, 0x30083102, 0xf953f009, 0x83f8e8bd, 
+    0x7110f242, 0x703ce7f4, 0x30fff04f, 0xf8c86030, 0x0c010000, 0x602c4843, 0xf0091f80, 0x4c41f942, 
+    0x23002208, 0x01513c1c, 0xf0094620, 0x4d3df954, 0x0100f44f, 0x35384f44, 0x138e9100, 0x2104e00c, 
+    0x4668462a, 0xfdeaf7e5, 0xd00c2801, 0x46312301, 0x46202209, 0xf93ff009, 0x46382206, 0xf0092140, 
+    0x2800f948, 0x482ed1eb, 0x22042300, 0x1e802110, 0xf931f009, 0xe92de7c2, 0x25004ff8, 0x4699460c, 
+    0xe9dd4690, 0x9500ab0a, 0x52a0f04f, 0x1000f9b0, 0x7080f04f, 0xfb73f7de, 0x4e23482c, 0x482c6005, 
+    0xf9967005, 0x1c400005, 0xf8dfd112, 0x2100c0a8, 0xe0a4f8df, 0xeb0c2000, 0xeb0e1701, 0x5c3b1201, 
+    0x1c405413, 0xdbfa2810, 0x29041c49, 0x7175dbf2, 0x7005481a, 0x713570f5, 0x5000f8c8, 0x5000f8c9, 
+    0x5000f8ca, 0x5000f8cb, 0x28007970, 0x7870d17e, 0xd07c2800, 0x78004819, 0xd27928fa, 0x0002f996, 
+    0x28007020, 0x4c07d072, 0x0000f44f, 0xf2404d05, 0x3c1c2800, 0x35384f0c, 0xe02e9000, 0xd0020126, 
+    0xd0035252, 0xd0035142, 0x00032cd4, 0xdcba01f5, 0xd03c80b0, 0x000322c2, 0x0003ab8c, 0x000322c1, 
+    0x00047f70, 0x00032396, 0xd003502c, 0x000323f4, 0x000323f8, 0x000351fc, 0x000402c4, 0x00032398, 
+    0x462a2105, 0xf7e54668, 0x2801fd59, 0x2301d00c, 0x22094641, 0xf0094620, 0x2206f8ae, 0x21404638, 
+    0xf8b7f009, 0xd1eb2800, 0x35fff240, 0x230148ff, 0x22004629, 0xf89ff009, 0x230f48fc, 0x46292200, 
+    0xf0091e80, 0x88f0f898, 0x2002bb28, 0xfd6bf7e5, 0x46202208, 0x01512301, 0xf88df009, 0x20402100, 
+    0xfcb2f7e5, 0xf7e52003, 0x2100fd5e, 0xf7e52040, 0x2100fcab, 0xf7e82008, 0x2001f8dd, 0xf92bf7e8, 
+    0x230048ea, 0x21102204, 0xe0023832, 0xe03de037, 0xf009e03a, 0x2101f870, 0x46082207, 0xf88df7e8, 
+    0x218c48e3, 0xf84df009, 0x23ff48e0, 0x46292200, 0xf0093818, 0x48ddf860, 0x2200233f, 0x11fff240, 
+    0xf0091f00, 0x48dbf858, 0x28017800, 0xf644d019, 0x48d96120, 0xeb008800, 0xebc20240, 0xeb0110c0, 
+    0x8bb100c0, 0xf5a04408, 0xb281707a, 0x301448d0, 0xf827f009, 0xb2818bb0, 0xf00948d0, 0xe8bdf822, 
+    0xf2478ff8, 0xe7e45130, 0xe7f87025, 0x70252141, 0x52a0f04f, 0x7080f04f, 0xfa81f7de, 0xe92de7ef, 
+    0xb0834fff, 0x20054607, 0x0b00f04f, 0xfc04f7e5, 0x60e04cc3, 0x780048c3, 0xd0372801, 0xd0352802, 
+    0xf00848c1, 0x4605fffb, 0x1c8048bf, 0xfff6f008, 0x4000ea45, 0x20006160, 0x636070e0, 0x90004680, 
+    0xf2402100, 0xf7e54000, 0x48b8fc2f, 0xb3287800, 0x20004cb3, 0x7580f04f, 0x11f4f240, 0x462870e0, 
+    0xf9fff7de, 0x462849b2, 0xf9eaf7de, 0x462849b1, 0xf9e6f7de, 0x1c407f20, 0x0007f000, 0x1100eb00, 
+    0xeb0048ad, 0x68810081, 0xe1853110, 0x1f0048a6, 0xffc4f008, 0x48a44605, 0xe7c71e80, 0xf7e52005, 
+    0x4c9ffbbb, 0x489f6120, 0x28017800, 0x2802d013, 0x489dd011, 0xffb2f008, 0x489b4605, 0xf0081c80, 
+    0xea45ffad, 0x61a04000, 0x0103e9d4, 0xd90a4281, 0x1c091a41, 0x4894e008, 0xf0081f00, 0x4605ff9f, 
+    0x1e804891, 0x1a41e7eb, 0xf04f4a94, 0xf04f0004, 0xf04f0a14, 0xf992091e, 0x2a052000, 0x2a04d002, 
+    0xe009d005, 0xf04f2005, 0x22140a0f, 0x2006e003, 0x0a0af04f, 0x4691220f, 0x488140c1, 0xe9d09101, 
+    0x42810105, 0x1a0cd202, 0xe0001c24, 0xf5b41a0c, 0xd3013f80, 0x3480f5a4, 0x44a09801, 0xf81cf00b, 
+    0x460e4605, 0xf00b4620, 0x4b7df817, 0xf00b2200, 0x462af863, 0xf00a4633, 0x4605fe43, 0x460e4879, 
+    0x2300e9d0, 0xf00b4628, 0x486df955, 0xd20d6b41, 0x63411c49, 0x46314874, 0x2300e9d0, 0xf00b4628, 
+    0xd207f949, 0x6b414866, 0xe0021c49, 0xda012900, 0x63412100, 0x46594862, 0x45836b40, 0x4608dd00, 
+    0xb1274683, 0xd30245d0, 0x200b495d, 0x1c786348, 0x45c8d004, 0x495ad302, 0x6348200b, 0x48624631, 
+    0x2300e9d0, 0xf00b4628, 0xd303f925, 0x6b414854, 0xdd7c290a, 0x9148f8df, 0xf9992101, 0x28020000, 
+    0x2803d008, 0xb3a7d006, 0xf889484a, 0x78001003, 0xe03bb380, 0x9805b36f, 0x7a80f04f, 0xf2407001, 
+    0x465011f4, 0xf92df7de, 0x41caf64a, 0xf7de4650, 0x4641f917, 0xf7de4650, 0x4b4cf913, 0x46282200, 
+    0xf00a4631, 0xf00afff9, 0x4601ff63, 0xf7de4650, 0xf8d9f907, 0x46501034, 0xf902f7de, 0xf9909805, 
+    0x46501000, 0xf8fcf7de, 0x4650493a, 0xf8f8f7de, 0xe009e00c, 0xf44fe7ff, 0xf6403000, 0xf7de0103, 
+    0xf7edf900, 0xe001f8aa, 0x70019806, 0x7a80f04f, 0x1bf4f240, 0x46594650, 0xf8f3f7de, 0x20aaf64a, 
+    0x46501839, 0xf8dcf7de, 0xf9909805, 0x46501000, 0xf8d6f7de, 0xf9909806, 0x46501000, 0xf8d0f7de, 
+    0xf008482b, 0x4601febb, 0xf7de4650, 0x4826f8c9, 0xe9d04631, 0x46282300, 0xf8acf00b, 0x4621d20a, 
+    0x46504654, 0xf8bcf7de, 0x46209901, 0xe08ae000, 0xf8b6f7de, 0x1010f8d9, 0x4655464c, 0xf7de4650, 
+    0x68e1f8af, 0xf7de4628, 0x4e12f8ab, 0x46314628, 0xf8a6f7de, 0x01c0f242, 0xf7de0648, 0x480bf8be, 
+    0xb3387800, 0x70e12100, 0xe025b32f, 0xd0035282, 0xd03c80a4, 0x00032396, 0x00047f78, 0xd003513e, 
+    0x00032cd4, 0x00032411, 0xd0036116, 0x000322c1, 0x0bbbdead, 0xdcba01f5, 0x0003ab8c, 0x0003227e, 
+    0x40140000, 0x000322c8, 0x000322d0, 0x40c38800, 0xd003502c, 0xe007e028, 0x0000f994, 0xd0012802, 
+    0xd1012803, 0x70019805, 0x46284659, 0xf879f7de, 0x21bbf64a, 0xf7de4628, 0x4631f863, 0xf7de4628, 
+    0x7f20f85f, 0xf0001c40, 0xeb000007, 0x48fd1100, 0x0081eb00, 0x31206881, 0x49fb6081, 0x60089804, 
+    0x0003f994, 0xe4c3b007, 0x0000f994, 0xd0042802, 0xd0022803, 0xf7e52003, 0x4659fb37, 0xf7de4628, 
+    0xf64bf850, 0x462831bb, 0xf83af7de, 0x46284641, 0xf836f7de, 0x46286b61, 0xf832f7de, 0x46284631, 
+    0xf82ef7de, 0x6981e009, 0x69016141, 0x980060c1, 0x90001c40, 0xf4ff2832, 0xb1c7ae23, 0x7480f04f, 
+    0x11f4f240, 0xf7de4620, 0xf64bf82c, 0x462031bd, 0xf816f7de, 0x46204641, 0xf812f7de, 0x462049db, 
+    0xf7de6b49, 0x49daf80d, 0xf7de4620, 0x48d7f809, 0x0003f990, 0xe92de7b6, 0x4cd34ffe, 0x0a00f04f, 
+    0x52a0f04f, 0xf88d4680, 0xf88da000, 0xf9b0a004, 0xf04f1000, 0x68267080, 0xf851f7de, 0x78e84dcb, 
+    0x2000b120, 0xa030f8c5, 0x8ffee8bd, 0x20016821, 0xf42146a3, 0x602121c0, 0xf7e56328, 0x9002fea9, 
+    0xf7e52000, 0x2000fe7f, 0xab01466a, 0xf7ff4631, 0x2002fdb6, 0x48bf6328, 0xb1907800, 0x7480f04f, 
+    0x11f4f240, 0xf8c54620, 0xf7dda030, 0xf64fffda, 0x462071ff, 0xffc4f7dd, 0x462049b5, 0xffc0f7dd, 
+    0x2003e19d, 0x20966328, 0xf89d62e8, 0x28000004, 0x2005d07e, 0x78286328, 0xd07a2800, 0xf04f2006, 
+    0xab01090a, 0x4631466a, 0x20016328, 0xfd87f7ff, 0x780048a8, 0xf8c5b110, 0xe180a030, 0x63282007, 
+    0xf99048a5, 0x28050000, 0x2804d002, 0x2003d101, 0xf89d4681, 0x28000000, 0xf04fd07e, 0xf2407480, 
+    0x462011f4, 0xff9df7dd, 0x0176f649, 0xf7dd4620, 0x4997ff87, 0xf7dd4620, 0x2400ff83, 0x4897e07e, 
+    0x28017800, 0x2802d014, 0x4895d012, 0xfd66f008, 0x48934607, 0xf0081c80, 0xea47fd61, 0x61a84000, 
+    0x1a416969, 0xd3134549, 0x7800488e, 0xe00fb140, 0x1f00488b, 0xfd52f008, 0x48894607, 0xe7ea1e80, 
+    0x3000f44f, 0x0103f640, 0xff6bf7dd, 0xff15f7ec, 0x1f406ae8, 0xd3174284, 0x7780f04f, 0x11f4f240, 
+    0xf7dd4638, 0xf246ff5e, 0x46387189, 0xff48f7dd, 0x46384621, 0xff44f7dd, 0x463869a9, 0xff40f7dd, 
+    0x46384973, 0xff3cf7dd, 0x1e406ae8, 0xe0014284, 0xe059e057, 0x2001d101, 0x210070e8, 0x4000f240, 
+    0xf962f7e5, 0x7800486b, 0xf04fb328, 0xf8857780, 0x4654a003, 0x11f4f240, 0xf88d4638, 0xf7dda000, 
+    0x4969ff30, 0xf7dd4638, 0x4961ff1b, 0xf7dd4638, 0x7f28ff17, 0xe0001c40, 0xf000e017, 0xeb000007, 
+    0x48581100, 0x0081eb00, 0x31306881, 0xf8cb6081, 0x632c6000, 0x69a8e0e3, 0x61681c64, 0x42846ae8, 
+    0xaf7df4ff, 0xf7e52003, 0x78e8f9ef, 0xf04fb1e0, 0xf2407480, 0x462011f4, 0xff03f7dd, 0x41ccf64c, 
+    0xf7dd4620, 0x494afeed, 0xf7dd4620, 0x7828fee9, 0x2143b118, 0x1000f8a8, 0x2009e006, 0x0000f8a8, 
+    0x9802e002, 0xfd7ef7e5, 0x63282008, 0x280078e8, 0x7828d177, 0xd0742800, 0xf7e59802, 0x4841fd73, 
+    0xb9087800, 0xf838f7ed, 0x46572002, 0xa004f885, 0xf9a9f7e5, 0x90f4f8df, 0x200a2208, 0x23016328, 
+    0x01514648, 0xfcc7f008, 0x63282009, 0x0400f44f, 0x1e64e012, 0xdc092c00, 0x46204c35, 0xfc98f008, 
+    0x0140f040, 0xf0084620, 0xe00dfc96, 0x46482301, 0x02592209, 0xfcaff008, 0x2206482c, 0x38fa2140, 
+    0xfcb7f008, 0xd1e42800, 0xf008482a, 0xb204fc87, 0x0101f004, 0xf0041e49, 0x43080002, 0x2001d072, 
+    0x200270e8, 0xf980f7e5, 0x7980f04f, 0x11f4f240, 0xf7dd4648, 0x4920fe96, 0xf7dd4648, 0x481bfe81, 
+    0xf00838fa, 0xea40fc6b, 0x46484104, 0xfe78f7dd, 0x4648490f, 0xfe74f7dd, 0x7800480e, 0xf240b380, 
+    0x464c11f4, 0x70ef4648, 0xfe7bf7dd, 0x46204913, 0xfe66f7dd, 0x46204906, 0xfe62f7dd, 0x1c407f28, 
+    0xe03fe01f, 0x0003ab8c, 0x00047ffc, 0x00032cd4, 0xdcba01f5, 0x000322c1, 0x0003227e, 0x00032411, 
+    0xd0036116, 0x00032396, 0x0ddddead, 0xd0035126, 0xc300006c, 0xd0060040, 0x00011104, 0x0eeedead, 
+    0xf000e00a, 0xeb000007, 0x48fe1100, 0x0081eb00, 0x31306881, 0xe00f6081, 0xb19878e8, 0xb1187828, 
+    0xf8a82043, 0xe0020000, 0xf8a82109, 0x200b1000, 0xf91af7e5, 0x700748f4, 0x6000f8cb, 0xf995632f, 
+    0xe6310003, 0x6000f8cb, 0xe92de675, 0x4def5ffc, 0x49fff240, 0x46044eee, 0xf2408e81, 0xf8df4bec, 
+    0xf240a3b4, 0x6bab48de, 0x68374549, 0x40fff2a1, 0xdc2ed06a, 0xf2a14559, 0xd07140ec, 0x4541dc12, 
+    0x40def2a1, 0xdc06d06d, 0xf110b311, 0xd06b0132, 0xd1682901, 0x2801e072, 0x2808d056, 0x2809d07e, 
+    0xe051d161, 0xd07a280c, 0x2801dc06, 0x2806d04c, 0x2807d076, 0xe047d157, 0xd045280d, 0xd1522812, 
+    0x220049d2, 0x313c4638, 0xffddf003, 0xd0681d40, 0x2818e03a, 0xdc20d038, 0xd035280c, 0x2805dc0e, 
+    0x2806d07e, 0x280bd030, 0x49c8d13d, 0x46382200, 0xf003313c, 0x1d40ffc8, 0xe025d073, 0xd0712811, 
+    0xd0212812, 0xd12e2817, 0x220049c0, 0x313c4638, 0xffb9f003, 0xd0661d40, 0x2826e016, 0xdc0fd014, 
+    0xd075281d, 0xd00f281e, 0xd11c2825, 0x220049b7, 0x0000f8da, 0xf003313c, 0x1d40ffa6, 0xe003d069, 
+    0xd0672829, 0xd10e282a, 0xf04f49b0, 0x6ba832ff, 0xf003313c, 0x1d01ffc7, 0xf240d10c, 0xe1df40ac, 
+    0xe09de0de, 0xe08fe000, 0x220049a8, 0x313c4618, 0xffb8f003, 0xd03e1d41, 0xd1e52801, 0x373c4fa3, 
+    0x0114f1a7, 0x0000f9b7, 0xd037280f, 0xd042283f, 0xd07b2843, 0xd07a2844, 0xe0032845, 0xe0fce0a1, 
+    0xe117e0db, 0x2846d074, 0x2848d073, 0x2849d072, 0x284ad071, 0x284cd070, 0x284dd06f, 0x2847d06e, 
+    0x283ed06d, 0xf995d1c0, 0x46381000, 0xfd53f7ff, 0xd0b92800, 0xf04f8838, 0x46390200, 0xe0032809, 
+    0xe137e11e, 0xe165e14c, 0x6ba8d079, 0xff4bf003, 0xd0751d01, 0xf240e190, 0xe19140ad, 0x91004b83, 
+    0x33244982, 0xf1011f1a, 0xf7ff003c, 0xe79bf9b3, 0xe176e163, 0x497de17b, 0x1f083118, 0xe9cd1f03, 
+    0x1f1a0100, 0x30283918, 0xfa05f7ff, 0xb92088e8, 0xf7e52002, 0x2800f82a, 0x4977d186, 0x28007808, 
+    0x8928d182, 0x81281c40, 0x70082001, 0x80382043, 0x0000f995, 0xd0012802, 0xd10b2803, 0x1c408968, 
+    0x486e8168, 0xf2487801, 0xf7e40000, 0x2000ff3d, 0xf880f7ff, 0x22004965, 0x313c6ba8, 0xff03f003, 
+    0xd1131d01, 0x8034f8a4, 0x9ffce8bd, 0xe033e013, 0xe06de051, 0xe0a0e08c, 0xe0dee0cc, 0xe10ce0fa, 
+    0x2200495a, 0x313c4618, 0xfeedf003, 0xd1ae1d40, 0x40dff240, 0x4b55e134, 0x49549100, 0x1f1a3324, 
+    0x003cf101, 0xf940f000, 0x22004950, 0x313c6ba8, 0xfed9f003, 0xd10a1d01, 0x40e6f240, 0xe106e120, 
+    0x494ae112, 0x46182200, 0xf003313c, 0x1d40fecc, 0xf240d18d, 0xe11340e7, 0x23004a44, 0x32249100, 
+    0xf1011f11, 0xf000001c, 0x4940fbb4, 0x6ba82200, 0xf003313c, 0x1d01feb8, 0xf8a4d108, 0xe7b3b034, 
+    0x2200493a, 0x313c4618, 0xfeadf003, 0xd1871d40, 0x40edf240, 0x4835e0f4, 0xe9d52300, 0x303c1208, 
+    0xfa9cf001, 0x22004931, 0x313c6ba8, 0xfe9bf003, 0xd1081d01, 0x40f2f240, 0x492ce0e2, 0x46182200, 
+    0xf003313c, 0x1d40fe90, 0xf240d1a1, 0xe0d740f3, 0xf9954b26, 0x33281000, 0x0208f1a3, 0x001cf102, 
+    0xfcfdf001, 0x22004921, 0x313c6ba8, 0xfe7bf003, 0xd1081d01, 0x40f8f240, 0x491ce0c2, 0x46182200, 
+    0xf003313c, 0x1d40fe70, 0xf240d1a2, 0xe0b740f9, 0xf9954816, 0x303c1000, 0xfe98f001, 0x22004913, 
+    0x313c6830, 0xfe5ff003, 0xf47f1d01, 0xf240ae7f, 0xe0a540fe, 0x9034f8a4, 0x4b0ce756, 0x1000f995, 
+    0xf1a33328, 0xf1020208, 0xf001001c, 0x4907fea7, 0x6ba82200, 0xf003313c, 0x1d01fe46, 0xf240d115, 
+    0xe08d5004, 0x0003ab8c, 0x000322c2, 0x00032cd4, 0x00032520, 0x00032564, 0x000322c1, 0x0003227f, 
+    0x22004948, 0xf0034618, 0x1d40fe2e, 0xf240d19c, 0xe0755005, 0x1000f995, 0xf0014842, 0x4941fec8, 
+    0x68302200, 0xfe1ff003, 0xf47f1d01, 0xf240ae54, 0xe065500a, 0x500bf240, 0x4b3ae062, 0x1000f995, 
+    0x48383b14, 0x0208f1a3, 0xffaaf001, 0x22004935, 0xf0036ba8, 0x1d01fe08, 0xf240d107, 0xe04f5010, 
+    0x22004930, 0xf0034618, 0x1d40fdfe, 0xf240d18c, 0xe0455011, 0x1000f995, 0xf002482a, 0x4929fa6e, 
+    0x68302200, 0xfdeff003, 0xf47f1d01, 0xf240ae33, 0xe0355016, 0x5017f240, 0xf995e032, 0x48211000, 
+    0xf0026a2a, 0x491ff85f, 0x6ba82200, 0xfddbf003, 0xd1071d01, 0x501cf240, 0x491ae022, 0x46182200, 
+    0xfdd1f003, 0xd1a11d40, 0x501df240, 0xf8dae018, 0xf0030000, 0x1d01fdc8, 0xae1ff47f, 0x5024f240, 
+    0xf240e00e, 0xe00b5025, 0x5028f240, 0x490de008, 0x46182200, 0xfdb7f003, 0xd1871d40, 0x5029f240, 
+    0xe6b186a0, 0x21012200, 0xf2afb510, 0xf00340e1, 0x2108fbf5, 0xf0032004, 0x4902fd53, 0x6388393c, 
+    0x0000bd10, 0x00032d10, 0x4fffe92d, 0xf04fb083, 0x460d0b00, 0x465f4681, 0x48fe9e10, 0x52a0f04f, 
+    0xb008f8cd, 0x1000f9b9, 0xf04f6804, 0x46a07080, 0x5480f504, 0xfbe3f7dd, 0xf7e52000, 0xf8dffa23, 
+    0x2300a3d8, 0xf24f220c, 0x46500100, 0xf96cf008, 0xf6402300, 0x22087100, 0xf0084650, 0x2300f965, 
+    0x22044650, 0xf00821f0, 0x2300f95f, 0x210f4650, 0xf008461a, 0x48e9f959, 0xf0082100, 0x2200f952, 
+    0x23109700, 0x46104611, 0xf9b2f7e8, 0x700748e4, 0x780048e4, 0x7828b988, 0xd00e2803, 0x3000f44f, 
+    0x0103f640, 0xfb5df7dd, 0xfb07f7ec, 0x210048de, 0x2000f990, 0xf7e64608, 0x4fdcfffb, 0x23002208, 
+    0x46380151, 0xf947f008, 0x0000f44f, 0x2a00f240, 0xe00d9002, 0x21074ad5, 0x3254a802, 0xfddef7e4, 
+    0xd00d2801, 0x46512301, 0x46382209, 0xf933f008, 0x220648ce, 0x38fa2140, 0xf93bf008, 0xd1e92800, 
+    0x270148cb, 0x0000f990, 0xd0012805, 0xd1002804, 0xf9952702, 0xf8df0000, 0x2803a31c, 0x2802d004, 
+    0x2805d005, 0xe019d015, 0x220049c3, 0xf9bae013, 0x28010000, 0x48c1da05, 0x21382203, 0xf919f008, 
+    0x49bfb110, 0xe0062200, 0x220048be, 0xf100fb07, 0x49bde001, 0x20022200, 0xfcf4f7e4, 0x20022100, 
+    0xfcbaf7e4, 0xf04f9805, 0x4fb831ff, 0x60014ab8, 0xf8c19906, 0x6838b000, 0x60381c40, 0x1c498811, 
+    0xb2818011, 0x301848a9, 0xf8cbf008, 0x1100f240, 0x100ef8aa, 0xf8aa2181, 0x78381010, 0xf8df4659, 
+    0xf000b2b4, 0xeb000007, 0xeb0b1200, 0x63010082, 0xf7e42005, 0x683afcb1, 0x0107f002, 0x1301eb01, 
+    0x0183eb0b, 0x020de9c1, 0x880048a3, 0x48a363c8, 0x64086800, 0xfed3f7e3, 0x220048a1, 0xf008213f, 
+    0x2811f8c8, 0x2001d301, 0x2000e000, 0xb23cf8df, 0xf8aa2301, 0xf1ab000c, 0x029f0b30, 0x220a4658, 
+    0xf0084639, 0x2300f8a8, 0x220a4639, 0xf0084658, 0x4894f8a2, 0xb9107800, 0xf7fe2000, 0x4884fe0b, 
+    0xf9957801, 0xf7e00000, 0x2301fbba, 0x220e488e, 0xf0080399, 0xf995f890, 0xf8df0000, 0x4f8cb230, 
+    0xd0042802, 0xd01f2803, 0xd0732805, 0x2001e0ad, 0xfa92f7fb, 0x20012100, 0xfdd0f7e5, 0x88004885, 
+    0x48859000, 0x3000f89b, 0xf9907839, 0x20072000, 0xf99bf7fb, 0x48812301, 0x46192200, 0xf86bf008, 
+    0xf7fb2000, 0xe08bf8d1, 0x000cf8ba, 0xd1142801, 0x2200487b, 0xf9902308, 0x46107000, 0x8400e9cd, 
+    0xf7e34639, 0x4977f8e6, 0x48772301, 0xe9cd2200, 0x46390100, 0xf7e34618, 0x4874f8dc, 0x28017800, 
+    0xf7fbd105, 0x2100fa59, 0xf7e52001, 0x4870fd97, 0x28017800, 0x2004d003, 0xf8a6f7fb, 0xf8dfe065, 
+    0x240081b4, 0xa1b0f8df, 0xb1b0f8df, 0xeb082100, 0xeb0b1304, 0xeb0a1004, 0x68321704, 0xd0171c52, 
+    0x54425c7a, 0xb2491c49, 0xdbf62910, 0x46204601, 0xf941f7e3, 0xb2641c64, 0xdbe72c04, 0xf7fb2001, 
+    0xf242f883, 0x064801c0, 0xfa27f7dd, 0xe001e03d, 0xe7e65c5a, 0x8800484f, 0x484f9000, 0x3000f89b, 
+    0xf9907839, 0x20072000, 0xf92ff7fb, 0x484b2301, 0x46192200, 0xfffff007, 0xf7e42002, 0x4950fbdd, 
+    0x20026008, 0x7008494f, 0xf7fb2000, 0x494ef85d, 0x484a2220, 0xff7ff007, 0x8108f8df, 0x4e422400, 
+    0xeb082301, 0xeb062144, 0x22002044, 0x0100e9cd, 0x46184621, 0xf86df7e3, 0xb2641c64, 0xdbef2c04, 
+    0xf2407839, 0xf7e31000, 0xf04ff98d, 0xf2407480, 0x463116f4, 0xf7dd4620, 0xf243f9d4, 0x46203100, 
+    0xf9bef7dd, 0xf9904839, 0x46201000, 0xf9b8f7dd, 0x68014837, 0xf7dd4620, 0x2112f9b3, 0xf7dd4620, 
+    0x482af9af, 0x46207801, 0xf9aaf7dd, 0x78014828, 0xf7dd4620, 0xf995f9a5, 0x46201000, 0xf9a0f7dd, 
+    0x7801482c, 0xf7dd4620, 0x4d2bf99b, 0x46294620, 0x0000e054, 0x00032224, 0xd180004c, 0xd0031034, 
+    0x00032b5c, 0x00032396, 0x00032283, 0xd0035126, 0x0003227e, 0x00032d28, 0x00aba950, 0xd28f007c, 
+    0x017d7840, 0x0094c5f0, 0x03b9aca0, 0x00032cf0, 0x00032d20, 0x0003ab8c, 0x000323e0, 0x000322a0, 
+    0xd0034200, 0x000322c1, 0xd0030416, 0x00032304, 0x00032411, 0x000322ac, 0x00032228, 0xd00305ae, 
+    0x000323ac, 0x00035a7c, 0x0003527c, 0x000323ff, 0x00032400, 0x000351fc, 0x0003523c, 0x0003308c, 
+    0x000323ec, 0x000323ea, 0x000402c4, 0x00032cd4, 0x0003222c, 0x00032402, 0xdcba01f5, 0xf940f7dd, 
+    0x46204631, 0xf94df7dd, 0x51ddf64d, 0xf7dd4620, 0x48fef937, 0x46207801, 0xf932f7dd, 0x46204629, 
+    0xf92ef7dd, 0xf8a92144, 0xb0071000, 0x8ff0e8bd, 0x41f0e92d, 0xe3d8f8df, 0xf04f4690, 0xeb0834ff, 
+    0xfa0f0c04, 0x2200f78c, 0x5010f9be, 0xfb026806, 0xf853c505, 0x42b55025, 0x6005d301, 0x1c52800f, 
+    0x2a04b212, 0x1c64dbf0, 0x2c01b224, 0xe8bddde7, 0xe92d81f0, 0xb0934fff, 0x2000460e, 0xf04f4de5, 
+    0x901152a0, 0x900648e4, 0x90092019, 0x680048e3, 0xf500900b, 0x900a5080, 0x680048e1, 0x98139008, 
+    0x1000f9b0, 0x7080f04f, 0xf949f7dd, 0xf24048d8, 0x81c11100, 0x82012181, 0xf44f2100, 0xf7e43080, 
+    0x48d8fb13, 0x9360f8df, 0x28037800, 0xf999d00a, 0x28050000, 0x2804d001, 0x2100d104, 0x3000f44f, 
+    0xfb02f7e4, 0x21002000, 0x1020f845, 0xb2001c40, 0x6f80f5b0, 0x9816dbf7, 0xd17d2800, 0x04c0f242, 
+    0x06604621, 0xf8d9f7dd, 0x78384fc6, 0xd1132803, 0xf2482100, 0xf7e40000, 0x48bcfae7, 0xb9087800, 
+    0xfa1af7ec, 0xf04f48ba, 0x89800100, 0xd0112801, 0x0000f248, 0xfad8f7e4, 0x4000f04f, 0xf7dd4621, 
+    0xf997f8bc, 0x28030000, 0x2802d007, 0x2805d005, 0xe067d003, 0x0000f244, 0x48b4e7ec, 0xfe7ef007, 
+    0x7838b204, 0x0100f04f, 0xd0112803, 0x3000f44f, 0xfabaf7e4, 0xd5150760, 0x70fbf64f, 0x0100ea04, 
+    0xf00748aa, 0xf899fe6e, 0x28030000, 0xe009d003, 0x3080f44f, 0x7838e7ec, 0xd1032802, 0x04002100, 
+    0xfaa2f7e4, 0x46204ca1, 0xfe58f007, 0x0608b201, 0xf64fd505, 0x4001707f, 0xf0074620, 0x4620fe52, 
+    0xfe4cf007, 0x04c8b201, 0xf64ed505, 0x400170ff, 0xf0074620, 0x7838fe46, 0xd1152805, 0x0000f999, 
+    0xd0012805, 0xd1162803, 0x3400f44f, 0x46202100, 0xfa7af7e4, 0xe0002100, 0x4620e006, 0xfa74f7e4, 
+    0x46202100, 0xfa70f7e4, 0xf9904886, 0x28020000, 0x2805d001, 0xf7e6d106, 0xb200fd54, 0x20089010, 
+    0xfd48f7e6, 0x01c0f242, 0xf7dd0648, 0xf04ff846, 0x27000900, 0x01c0f242, 0xf7dd0648, 0x4874f83e, 
+    0x21052301, 0xf9b0029a, 0xe88d000e, 0x4874000f, 0x23001f8a, 0x68002108, 0xff02f7f9, 0x496c2400, 
+    0x230c9808, 0x2044eb00, 0x200ef9b1, 0xf0074970, 0x2108fdc0, 0x4b70486f, 0xe9cd4a70, 0x486c0100, 
+    0xf0079911, 0xf8dfff1b, 0x2000e188, 0x496be017, 0x3020f851, 0xf8514968, 0xfb811020, 0xfbc31201, 
+    0xfb041203, 0xe9ce030c, 0x0d891206, 0xc023f855, 0x2182ea41, 0x44611c40, 0xf845b200, 0xf9be1023, 
+    0x4560c010, 0xf9bedbe3, 0x20001010, 0xf8454361, 0x49540021, 0x1000f991, 0xd0012902, 0xd1082905, 
+    0x1010f9be, 0x200ef9be, 0xeb014361, 0xf8450162, 0x99200021, 0xf9be680a, 0xebb2100e, 0xd1060fa1, 
+    0x2010f9be, 0xeb024362, 0xf84501a1, 0x1c640021, 0x2c04b264, 0x1c7fdba3, 0x2f02b23f, 0xf1b9db8a, 
+    0xd10f0f00, 0x9906a80d, 0x9000ab04, 0x4628aa07, 0xfbb2f7fe, 0xf9bd4836, 0xf9b01034, 0xfb912010, 
+    0x8141f1f2, 0x0001f109, 0xf980fa0f, 0x0f01f1b9, 0xaf6ff6ff, 0x01c0f242, 0xf7dc0648, 0x4831ffae, 
+    0x0000f990, 0xd0012802, 0xd1032805, 0xb2c09810, 0xfca0f7e6, 0x20004c26, 0x7780f04f, 0x1e409005, 
+    0x11f4f240, 0x463880a0, 0xff8bf7dc, 0x7171f240, 0xf7dc4638, 0xf9b4ff75, 0x46381000, 0xff70f7dc, 
+    0x46384927, 0xff6cf7dc, 0x68004826, 0xd37d2812, 0xbb489816, 0x78004815, 0x481abb30, 0x28027800, 
+    0xf04fd122, 0xf2407980, 0x464811f4, 0xff69f7dc, 0x1199f641, 0xf7dc4648, 0x4c1bff53, 0xf9944648, 
+    0xf7dc1000, 0xf9bdff4d, 0x46481034, 0xff48f7dc, 0x46484f07, 0x100af9b7, 0xff42f7dc, 0x0000f994, 
+    0x100af9b7, 0xe0214288, 0x0000e075, 0x00032396, 0x00032d28, 0x0003ddfc, 0x0003edfc, 0x00032224, 
+    0x00032218, 0x00032cd4, 0x0003227e, 0xd03c80b6, 0x0003627c, 0x0002e510, 0x00039a7c, 0x00038a7c, 
+    0xdcba01f5, 0x0003222c, 0x00032283, 0xf8ddd14e, 0x2000901c, 0x90004604, 0x1010f9b7, 0x0010f9bd, 
+    0x0001fb04, 0x1020f855, 0x7080f04f, 0xff08f7dc, 0x1010f9b7, 0x0010f9bd, 0x0001fb04, 0x0020f855, 
+    0xda014548, 0x94004681, 0xb2641c64, 0xdbe32c04, 0x7780f04f, 0x46389900, 0xfef2f7dc, 0x1010f9bd, 
+    0xf7dc4638, 0xf7ebfeed, 0xe000ff91, 0x4cfee0c0, 0x99001402, 0xb2017021, 0xf7eb4610, 0x49fbff18, 
+    0x70082001, 0xf7ec2002, 0xf994f914, 0xf7eb0000, 0xf994fe6f, 0xf7eb0000, 0xf994feb4, 0xf7eb0000, 
+    0xf994feff, 0x46381000, 0xfecaf7dc, 0xf04f49f0, 0xf7dc7080, 0x4ceffec5, 0xbbe88820, 0x0010f9bd, 
+    0x1d212703, 0xfb90462b, 0xb202f0f7, 0xf7ffa805, 0xf9b4fd8f, 0xf04f000e, 0xf9bd7980, 0x1a401010, 
+    0x11f4f240, 0xf0f7fb90, 0x4648b207, 0xfeb9f7dc, 0x4101f244, 0xf7dc4648, 0x4639fea3, 0xf7dc4648, 
+    0xf9b4fe9f, 0x46481004, 0xfe9af7dc, 0x464849d8, 0xfe96f7dc, 0x0010f9bd, 0x1d001a38, 0xd9052808, 
+    0x462b1d21, 0x463aa805, 0xfd62f7ff, 0x46a188a0, 0xb014f8dd, 0xe0008120, 0xf9bde01d, 0x462b0010, 
+    0xeb0049cc, 0x1d0970d0, 0xa8051042, 0xfd50f7ff, 0x100ef9b9, 0x0010f9bd, 0xeb011a09, 0x104971d1, 
+    0x1a10b20a, 0x28081d00, 0x49c2d905, 0x462ba805, 0xf7ff1d09, 0xf9b4fd3d, 0x98091004, 0xda034281, 
+    0x90052000, 0x80a01e40, 0x0010f9bd, 0x00412201, 0xf9b4b20f, 0xeb02100e, 0x428202a1, 0x4242dc03, 
+    0x0142eb01, 0x287db20f, 0x49b2dc06, 0x462ba805, 0x1d09463a, 0xfd1cf7ff, 0x970e9805, 0xf9bd900c, 
+    0x282b0010, 0x0140eb00, 0xdb04b20a, 0xeba089e2, 0x44110180, 0x2845b20a, 0xf9b4dc0a, 0xebb0100e, 
+    0xd0050fa1, 0xa80549a3, 0x1d09462b, 0xfd00f7ff, 0xf188fa1f, 0xf00748a0, 0x489ffc14, 0xf18afa1f, 
+    0xf0071c80, 0x980ffc0e, 0xb2811c40, 0x1d00489a, 0xfc07f007, 0xf3c09807, 0x4897214f, 0xf0071d80, 
+    0xf8bdfc00, 0xb2810010, 0x300a4893, 0xfbf9f007, 0x19f4f240, 0x7080f04f, 0xf7dc4649, 0xf04ffe12, 
+    0xf2407080, 0xf7dc7177, 0x4c8cfdfb, 0x7080f04f, 0xf7dc6821, 0xf9bdfdf5, 0xf04f1010, 0xf7dc7080, 
+    0x9807fdef, 0xf04f0a01, 0xf7dc7080, 0x4f80fde9, 0x7080f04f, 0xf7dc4639, 0xf04ffde3, 0x46497080, 
+    0xfdeff7dc, 0x7080f04f, 0x51ddf64d, 0xfdd8f7dc, 0x7801487b, 0x7080f04f, 0xfdd2f7dc, 0x7080f04f, 
+    0xf7dc4639, 0x7820fdcd, 0x91c8f8df, 0x0007f000, 0x1100eb00, 0xeb004873, 0xe9c00081, 0x990f8a03, 
+    0x0800f04f, 0xf9bd6141, 0x61c77010, 0x1034f9bd, 0x9c076201, 0x8024f8c0, 0x61830a63, 0x100ef9b9, 
+    0x0ca1ea4f, 0xc000f8c6, 0xc054f8dd, 0x8000f8cc, 0xc194f8df, 0x8002f8a9, 0x8006f8a9, 0x0000f99c, 
+    0xd0062803, 0x0204f04f, 0xd1059208, 0x12f4f240, 0xf04fe004, 0xe7f70232, 0x020af04f, 0xc020f8dd, 
+    0x2f54ebbc, 0x6037d215, 0x99152803, 0x9805600b, 0xebb2d006, 0xd8622f10, 0xf8a92101, 0xe05e1002, 
+    0x2f10ebb2, 0xf9b9d85b, 0x99092004, 0xdaf3428a, 0x2803e055, 0xf04fd025, 0xf2407a80, 0x465011f4, 
+    0xfd7ff7dc, 0x0180f648, 0xf7dc4650, 0x4c43fd69, 0x68214650, 0xfd64f7dc, 0x46504f44, 0xf7dc7839, 
+    0x6831fd5f, 0xf7dc4650, 0x4939fd5b, 0xf7dc4650, 0x6820fd57, 0xdb152801, 0x28237838, 0x2080d812, 
+    0x9820e012, 0x1c426800, 0x2880d009, 0x6030d007, 0xf8a91049, 0x21011004, 0x1002f8a9, 0x1048e017, 
+    0xe0146030, 0x30fff04f, 0x11f4f240, 0x60304654, 0xf7dc4650, 0x6831fd46, 0xf7dc4620, 0x4924fd31, 
+    0xf7dc4620, 0xf8a9fd2d, 0xf8a98002, 0x980f8006, 0x30b8f600, 0x4820b281, 0xf0071d00, 0x4824fb12, 
+    0x28126800, 0xf9b9d37e, 0xf9bd000e, 0xebb11010, 0xd1080fa0, 0x3002f8b9, 0xb923464a, 0x80931043, 
+    0xf8a92301, 0x4c183002, 0x2000f994, 0xd10f2a03, 0x0f60ebb1, 0xd004464b, 0xeb071f17, 0x428f0760, 
+    0x885fd106, 0x1080b927, 0x20018098, 0x0002f8a9, 0x42819809, 0xf8a9dc03, 0xf8a98002, 0x2a038006, 
+    0xd15846a2, 0xe0154648, 0x00032283, 0x00032281, 0xdcba01f5, 0x00032d28, 0xd03c80a8, 0x00032cf0, 
+    0x00032396, 0x0003ab8c, 0x00032cd4, 0x00032398, 0x0003222c, 0x1002f8b9, 0x9920b921, 0x80818809, 
+    0x80412101, 0x000cf8b9, 0xd1342801, 0xf99048fe, 0x88307000, 0xf04fb204, 0x2c800000, 0x4643d035, 
+    0xeb049a0b, 0x1c4011c0, 0xf822b200, 0x9a0a3011, 0xf8222808, 0xdbf33011, 0x210ae9dd, 0x23002008, 
+    0x0007e88d, 0x4639461a, 0xf7e24618, 0x48effa87, 0x4aef2c80, 0xf822d023, 0xf8208014, 0x21018014, 
+    0xe0002300, 0x9100e010, 0xe9cd4639, 0x20012001, 0xf7e2461a, 0xf9b9fa73, 0x464c0008, 0x1004f9b9, 
+    0xd03e4288, 0xb1698861, 0x4642e03b, 0xeb01990a, 0x1c402100, 0x2808b200, 0xdbf7800a, 0xf8a0e7cc, 
+    0xe7dc8000, 0x1000f89a, 0xd06c2903, 0x215bea5f, 0x9909d027, 0xdb244288, 0xf2402001, 0x80e011f4, 
+    0x46380607, 0xfc7df7dc, 0x5122f245, 0xf7dc4638, 0xf9b4fc67, 0x46381006, 0xfc62f7dc, 0x215bea4f, 
+    0xf7dc4638, 0xf9b4fc5d, 0x46381004, 0xfc58f7dc, 0x1008f9b4, 0xf7dc4638, 0x49c6fc53, 0xf7dc4638, 
+    0x9816fc4f, 0xf240b3f0, 0x970077d0, 0x7a80f04f, 0x46502400, 0xf7dc10b9, 0xf243fc54, 0x46503111, 
+    0xfc3ef7dc, 0x46504639, 0xfc3af7dc, 0x780148ba, 0xf7dc4650, 0x4639fc35, 0xf7dc4650, 0x49b5fc31, 
+    0xf7dc4650, 0xf9bdfc2d, 0x28190010, 0x0079da01, 0x99079100, 0x91019a00, 0x2f51ebb2, 0xf9b9d230, 
+    0x2103e010, 0xe008f8cd, 0xf9b946cc, 0xf1aea00e, 0x45700e08, 0xf8bcdc0e, 0x1843700a, 0xfb179a02, 
+    0xe0013302, 0xe048e09d, 0xf8529a06, 0x42a22023, 0x4614db00, 0x0f6aebb0, 0xebb0d002, 0xd10b0faa, 
+    0x300af8bc, 0xfb139a02, 0x9a061302, 0x0283eb02, 0x42a26c92, 0x4614db00, 0xb2091c89, 0xddd82907, 
+    0x200ef9b9, 0x464f2100, 0x0f62ebb0, 0xebb0d002, 0xd1000fa2, 0x897a2102, 0x1d498a3b, 0x0203fb12, 
+    0x2022f855, 0x42a2410a, 0xe9dddb04, 0xebb11200, 0xd3022f52, 0xf8c19915, 0x46418000, 0xa21cf8df, 
+    0x8000f88a, 0x68129a15, 0xdd162a00, 0x2808381c, 0x4883d813, 0xb1687800, 0x2205e00f, 0x2f5bebb2, 
+    0xaf32f63f, 0x42889909, 0xaf2ef6ff, 0xf8a92001, 0xe7660006, 0xf88a2001, 0x9a050000, 0x70d0f240, 
+    0x2f52ebb0, 0x8079d300, 0x2f5bebb0, 0x80f9d300, 0x7080f04f, 0x11f4f240, 0xfbb3f7dc, 0x7080f04f, 
+    0x1122f241, 0xfb9cf7dc, 0x1000f99a, 0x7080f04f, 0xfb96f7dc, 0xf04f9900, 0xf7dc7080, 0x9807fb91, 
+    0xf04f0a41, 0xf7dc7080, 0xf9bdfb8b, 0xf04f1010, 0xf7dc7080, 0xf04ffb85, 0x46217080, 0xfb80f7dc, 
+    0x1002f9b7, 0x7080f04f, 0xfb7af7dc, 0x1006f9b7, 0x7080f04f, 0xfb74f7dc, 0xf04f4956, 0xf7dc7080, 
+    0xe9ddfb6f, 0xebb10107, 0xd33f2f50, 0x7a80f04f, 0x11f4f240, 0xf7dc4650, 0xf648fb74, 0x46500181, 
+    0xfb5ef7dc, 0x46504c4f, 0xf7dc6821, 0x4f4afb59, 0x78394650, 0xfb54f7dc, 0x46506831, 0xfb50f7dc, 
+    0x46504944, 0xfb4cf7dc, 0x28016820, 0x7838db04, 0xd8012823, 0xe0012080, 0x30fff04f, 0x11f4f240, 
+    0x60304654, 0xf7dc4650, 0x6831fb4c, 0xf7dc4620, 0x9820fb37, 0x46206801, 0xfb32f7dc, 0x46204935, 
+    0xfb2ef7dc, 0x8002f8a9, 0x8006f8a9, 0x68019820, 0x42816830, 0x1c41d179, 0x2880d077, 0xf8b9d075, 
+    0x464c0000, 0x1c40492c, 0xf8a9b200, 0x78090000, 0xd3112946, 0xdb0d2802, 0x2b018863, 0x88e2d10a, 
+    0xd1072a01, 0x455b9b05, 0xf8a4d302, 0xe0018006, 0x8002f8a4, 0xd85a2946, 0xdb582801, 0x2232980c, 
+    0x2f50ebb2, 0x8861d20d, 0xf9b4b959, 0x46203004, 0x428b9909, 0x2101db05, 0x990e8041, 0x980c80a1, 
+    0x980c9005, 0x2f50ebb2, 0x88e0d241, 0xf9b4bb60, 0x98091004, 0xdb3a4281, 0x80e02001, 0xf04f980e, 
+    0x81207780, 0x11f4f240, 0xb030f8dd, 0xf7dc4638, 0xf245fae8, 0x46385111, 0xfad2f7dc, 0x1006f9b4, 
+    0xf7dc4638, 0xe011facd, 0x000323ac, 0x00035a7c, 0x0003527c, 0xdcba01f5, 0x00032398, 0x00032d19, 
+    0x00032396, 0x00032cf0, 0xe00ee011, 0x215bea4f, 0xf7dc4638, 0xf9b4fab5, 0x46381008, 0xfab0f7dc, 
+    0x463849fe, 0xfaacf7dc, 0xf8a9e001, 0x98168000, 0xa802bbf0, 0x8000f8cd, 0x8004f8cd, 0xfe3ff7e5, 
+    0x1c406830, 0x2700d025, 0x463c46e8, 0x9a066830, 0xf8554438, 0xf8521020, 0x42810020, 0x1a08db10, 
+    0x1080ebc0, 0xf7e50840, 0xa902fec5, 0xf9314aec, 0xf1c11014, 0xf832011f, 0x43411011, 0xe0000b88, 
+    0xf8282000, 0x37810014, 0xb2241c64, 0x2c04b23f, 0xf8bddbdc, 0x48e31000, 0xf863f007, 0xf8bd48e1, 
+    0x1c801002, 0xf85df007, 0x1004f8bd, 0xe00048dd, 0x1d00e008, 0xf855f007, 0xf8bd48da, 0x1d801006, 
+    0xf84ff007, 0x7780f04f, 0x15f4f240, 0x46384629, 0xfa67f7dc, 0x2122f240, 0xf7dc4638, 0x9820fa51, 
+    0x46386801, 0xfa4cf7dc, 0x46386831, 0xfa48f7dc, 0x0a019807, 0xf7dc4638, 0xf9b9fa43, 0x464c1002, 
+    0xf7dc4638, 0xf9b4fa3d, 0x46381004, 0xfa38f7dc, 0x0a019805, 0xf7dc4638, 0xf9b4fa33, 0x46381006, 
+    0xfa2ef7dc, 0x1008f9b4, 0xf7dc4638, 0xea4ffa29, 0x4638211b, 0xfa24f7dc, 0x46384cb8, 0xf7dc4621, 
+    0x4629fa1f, 0xf7dc4638, 0xf64dfa2c, 0x463851dd, 0xfa16f7dc, 0x780148b4, 0xf7dc4638, 0x4621fa11, 
+    0xf7dc4638, 0xf242fa0d, 0x064801c0, 0xfa25f7dc, 0x21459813, 0xb0178001, 0x8ff0e8bd, 0x4fffe92d, 
+    0x4681b085, 0x460f2000, 0x52a0f04f, 0x48a79003, 0x20196804, 0x48a69004, 0x1000f9b9, 0x8000f990, 
+    0x7080f04f, 0xfa4bf7dc, 0x98084da2, 0xf995bb08, 0x28050000, 0x2803d01d, 0x489fd01b, 0x28166800, 
+    0x2100d204, 0x3000f44f, 0xfc0ef7e3, 0x8800489b, 0x489b9000, 0x489b7803, 0x2000f990, 0x7801489a, 
+    0xf7fa2000, 0x2300f902, 0x21014898, 0xf006461a, 0xf8dfffd2, 0x4897a25c, 0x100ef9ba, 0xff98f007, 
+    0x2600488c, 0x0000f990, 0xd0042803, 0x91022104, 0xb1119908, 0x2101e007, 0x2805e7f9, 0x4646d103, 
+    0xb2401c70, 0x488c9002, 0x0587eb00, 0x488be15f, 0x28067800, 0x0000f04f, 0x4989d312, 0x3010f9ba, 
+    0x2c86eb01, 0xe0054984, 0x2020f85c, 0x2020f841, 0xb2001c40, 0xdbf74298, 0xf8504882, 0xe00e0026, 
+    0xf9ba497b, 0x4b7c2010, 0xe0053120, 0xc020f851, 0xc020f843, 0xb2001c40, 0xdbf74290, 0xf8556808, 
+    0xf8df1c08, 0xebb1c1d4, 0xdd000fe0, 0xf84510c1, 0xf8551c08, 0xebb11c04, 0xdd000fa0, 0xf8451081, 
+    0xf84c1c04, 0x68690027, 0x0fa0ebb1, 0x1081dd00, 0x68a96069, 0x0fe0ebb1, 0x10c1dd00, 0x495e60a9, 
+    0x29126809, 0xf8bad332, 0x46d61002, 0xd1142901, 0x3004f9be, 0x0183eb0c, 0x2c04f851, 0x0fa0ebb2, 
+    0x1082dd00, 0x2c04f841, 0xf84c1082, 0x684b2023, 0x0fa0ebb3, 0x461adc00, 0xf8be604a, 0x29011006, 
+    0xf9bad114, 0xeb0c3008, 0xf8510183, 0xebb22c04, 0xdd000fa0, 0xf8411082, 0x10822c04, 0x2023f84c, 
+    0xebb3684b, 0xdc000fa0, 0x604a461a, 0x001af1a7, 0xd917280a, 0x1004f9ba, 0x391a4650, 0xd802290a, 
+    0x29018841, 0xf9b0d00e, 0x391c1008, 0xd8032908, 0x0006f8ba, 0xd0052801, 0x48432100, 0x1c787001, 
+    0xe004d002, 0xe7f82101, 0x2102483f, 0xf9ba7001, 0xf9ba0010, 0xe006100e, 0xf85c1a0a, 0xf84c2022, 
+    0x1c402020, 0x4288b200, 0x2108dbf6, 0x4a384837, 0xe9cd9b03, 0x492f0100, 0xf007482f, 0x4934faf9, 
+    0x5200f04f, 0xb1e0e00a, 0xf8512000, 0x005b3020, 0x3020f841, 0xb2001c40, 0xdbf62811, 0x42906808, 
+    0xf04fddf1, 0x68084380, 0xdd0a4298, 0xf8512000, 0x10522020, 0x2020f841, 0xb2001c40, 0xdbf62811, 
+    0x2000e7f1, 0x2020f851, 0x5200f102, 0x2020f841, 0xb2001c40, 0xdbf52811, 0xeb06481e, 0x22101106, 
+    0x0181eb00, 0x468b481a, 0xff47f7f3, 0xf06f2000, 0xf85b027e, 0xf5011020, 0xe02d7180, 0xdcba01f5, 
+    0x00032b5e, 0xd0035154, 0x00032396, 0x00032224, 0x00032283, 0x00032cd4, 0x0003222c, 0x000322ac, 
+    0x00032304, 0x00032228, 0x00032411, 0xd00305ae, 0x00032d28, 0x00039a7c, 0x00038a7c, 0x00032398, 
+    0x0003adec, 0x0003bdec, 0x00032d18, 0x0002e510, 0x0003627c, 0x0003aa7c, 0x214ff341, 0xf8242980, 
+    0xdd001010, 0x42912180, 0x1010f824, 0x4611da00, 0x1010f824, 0xb2001c40, 0xddba2810, 0x46012000, 
+    0x2010f834, 0xb2001c40, 0xb2094411, 0xdbf72811, 0x42879804, 0x8c20db02, 0x84201a40, 0x200049fe, 
+    0x1106eb01, 0x0240eb04, 0x540a7892, 0xb2001c40, 0xdbf72810, 0x210148f9, 0x1c764af9, 0x7800b276, 
+    0x0007f000, 0x1000eb00, 0x0080eb02, 0x98026241, 0xf6ff4286, 0xf8baae9c, 0xb9880000, 0x21004ef1, 
+    0x20004ded, 0x1201eb06, 0x1301eb05, 0x54175c1f, 0xb2001c40, 0xdbf92810, 0xb2491c49, 0xdbf02904, 
+    0xbbe89808, 0x780048e8, 0xd1632805, 0xc388f8df, 0xf04f2200, 0x46103aff, 0x1308eb0c, 0x46154651, 
+    0x4249466e, 0xe000f913, 0x5435b209, 0xfb1e1c40, 0xb2002201, 0x2810b212, 0xf1c2dbf3, 0xb2000040, 
+    0x28082100, 0xf1a0dd03, 0xb2090108, 0xf1102701, 0xda030f08, 0x46573008, 0xb2014240, 0x2900427f, 
+    0x2910dd11, 0x2000dd0f, 0x4252463a, 0x5c35b212, 0x54354415, 0xb2001c40, 0xdbf62810, 0xe0003910, 
+    0xb209e028, 0x1e48e7eb, 0xd80a280f, 0xe0062000, 0xb217427a, 0x443a5c32, 0x1c405432, 0x4288b200, 
+    0x2000dbf6, 0x5c325c19, 0x54194411, 0xb2001c40, 0xdbf72810, 0x45412100, 0x2000d008, 0x1201eb0c, 
+    0x54155c1d, 0xb2001c40, 0xdbf92810, 0xb2491c49, 0xdbf02904, 0x78284db4, 0xd1102803, 0x21014eae, 
+    0xeb062000, 0xeb041201, 0x789b0340, 0x1c405413, 0x2810b200, 0x1c49dbf7, 0x2904b249, 0xf04fdbf0, 
+    0xf2407480, 0x462011f4, 0xffbbf7db, 0x51ddf64d, 0xf7db4620, 0x49a5ffa5, 0x78094620, 0xffa0f7db, 
+    0x462049a3, 0xff9cf7db, 0x01c0f242, 0xf7db0648, 0xf995ffb4, 0x21460000, 0xd0042802, 0xd0062803, 
+    0xd00a2805, 0xf8a9210f, 0xb0091000, 0x4899e584, 0x28007800, 0x2149d1f7, 0x214ce7f5, 0xe92de7f3, 
+    0xf04f4ff0, 0xf9b07780, 0x25001000, 0xb087461e, 0xf04f4614, 0x468252a0, 0xf7db4638, 0xf242ffd0, 
+    0x064801c0, 0xff89f7db, 0x60306820, 0x4a8a6820, 0xd0041c41, 0x31c8f44f, 0x0c014348, 0xf64fe001, 
+    0x461071ff, 0xfd4df006, 0x11f4f240, 0xf7db4638, 0xf243ff68, 0x46383133, 0xff52f7db, 0x46386831, 
+    0xff4ef7db, 0x46386821, 0xff4af7db, 0xf9b0487b, 0x4638100c, 0xff44f7db, 0x22004879, 0xf006213f, 
+    0x4601fd58, 0xf7db4638, 0x4876ff3b, 0x46387801, 0xff36f7db, 0x4638496e, 0xff32f7db, 0x7800486a, 
+    0xd1042802, 0x49704871, 0xf7e36800, 0xf8dff963, 0x240081c0, 0x91bcf8df, 0x20004f5f, 0x1c04eb08, 
+    0x1104eb09, 0x1304eb07, 0x1c526832, 0x5c1ad032, 0x1c40540a, 0x2810b240, 0x4620dbf6, 0xfe3bf7e1, 
+    0xb2641c64, 0xdbe82c04, 0xf7f92001, 0xf242fd7d, 0x064801c0, 0xff21f7db, 0xb17cf8df, 0x23002001, 
+    0x4000f99b, 0x46209000, 0x1204eb08, 0x1104eb09, 0xfef4f7e1, 0x20004e59, 0x1104eb07, 0x1204eb06, 
+    0x54135c0b, 0xb2401c40, 0xdbf92810, 0x78004847, 0xe004b118, 0x2000f81c, 0xf7ebe7ca, 0x2400f84d, 
+    0x46b846c3, 0x484c2701, 0x0000f990, 0xd0134284, 0x46202300, 0x1204eb0b, 0xeb099700, 0xf7e11104, 
+    0x2000fecd, 0x1104eb08, 0x1204eb06, 0x54135c0b, 0xb2401c40, 0xdbf92810, 0xb2641c64, 0xdbe22c04, 
+    0x80fcf8df, 0xf998493b, 0xf7e10000, 0x4a3dfe09, 0x48382104, 0xfb7cf006, 0x78204c2c, 0x483ab918, 
+    0xf7f97007, 0x4839f9b9, 0xf7f97007, 0x4838fb45, 0x21382203, 0xfcbdf006, 0xf7e2b108, 0xf04ffffb, 
+    0xf2424b00, 0x464909c0, 0xf7db4658, 0x4e1efeb6, 0xf04f200e, 0x46020301, 0x90007831, 0x46012903, 
+    0x7502e9cd, 0x95059504, 0xd00b9001, 0xf7e30218, 0x4649ff3f, 0xf7db4658, 0x4826fea0, 0x28037800, 
+    0xe00ed002, 0xe7f22080, 0x9000200f, 0x46022301, 0x7502e9cd, 0x95044601, 0x90019505, 0xf7e30258, 
+    0x4649ff27, 0xf7db4658, 0x481bfe88, 0xf965f7e5, 0x0000f998, 0xe0314918, 0x0003523c, 0x00032cf0, 
+    0x0003ab8c, 0x00040304, 0x00032cd4, 0x00032396, 0xdcba01f5, 0x00032400, 0xd003513c, 0x00032d28, 
+    0xd0034200, 0x00032398, 0x00167fc4, 0x000323ec, 0x000351fc, 0x0003308c, 0x00032283, 0x000402c4, 
+    0x000323ac, 0x000330cc, 0x00032281, 0x00032282, 0xd28f007c, 0x0003227e, 0x000331dc, 0x0020f851, 
+    0x3fc0f5b0, 0x4649d931, 0xf7db4658, 0x4d39fe46, 0x4a392000, 0x493a4b39, 0x0c40eb02, 0x7010f835, 
+    0x7010f822, 0x0740eb05, 0x7200f8b7, 0x7200f8ac, 0x0c40eb01, 0x7010f833, 0x7010f821, 0x0740eb03, 
+    0x28811c40, 0x7200f8b7, 0x7200f8ac, 0x4649dbe4, 0xf7db4658, 0x482bfe22, 0xb1306800, 0x31a6f240, 
+    0x78224b29, 0xf7e31e48, 0x2301f861, 0x4619220f, 0xf7e34610, 0x4825ff7e, 0x0000f9b0, 0xdb1b2801, 
+    0xb2452805, 0x2505db00, 0x28037830, 0x4f20d014, 0xf44f2400, 0xe00d3600, 0x46307839, 0xf814f7e3, 
+    0x46302100, 0xf810f7e3, 0x46302100, 0xf80cf7e3, 0xb2641c64, 0xdbef42ac, 0x46584649, 0xfdedf7db, 
+    0xf8aa2148, 0xb0071000, 0x8ff0e8bd, 0x21014a11, 0x4604b510, 0xf7ef7011, 0x480ffded, 0x80012104, 
+    0x8020200a, 0x01c0f242, 0x4010e8bd, 0xf7db0780, 0x0000bdd4, 0x0003cdfc, 0x0003527c, 0x0003d5fc, 
+    0x00035a7c, 0x00047f70, 0xd03c80b8, 0x00032d28, 0x0003227f, 0x0003223f, 0x0003251a, 0x47f0e92d, 
+    0x7780f04f, 0x1000f9b0, 0x4614461d, 0x52a0f04f, 0x46384606, 0xfdf3f7db, 0x4900f04f, 0x08c0f242, 
+    0x46484641, 0xfda9f7db, 0x60286820, 0x4a866820, 0xd0041c41, 0x31c8f44f, 0x0c014348, 0xf64fe001, 
+    0x461071ff, 0xfb6df006, 0x11f4f240, 0xf7db4638, 0xf243fd88, 0x46383133, 0xfd72f7db, 0x46386829, 
+    0xfd6ef7db, 0x46386821, 0xfd6af7db, 0x46384977, 0xfd66f7db, 0x49764877, 0xf7e26800, 0x4641ff9b, 
+    0xf7db4648, 0x2048fd7a, 0xe8bd8030, 0xe92d87f0, 0xf04f4ff0, 0xf9b07b80, 0x24001000, 0xb087465d, 
+    0xf04f4658, 0xf7db52a0, 0xf240fdaa, 0x462811f4, 0xfd57f7db, 0x0177f649, 0xf7db4628, 0x4966fd41, 
+    0xf9b14628, 0xf7db1000, 0x4960fd3b, 0xf7db4628, 0xf8dffd37, 0x4d62a188, 0x0000f89a, 0xf44fb968, 
+    0xf6403000, 0xf7db0103, 0xf7eafd3c, 0x2100fce6, 0x2000f995, 0xf7e54608, 0xf995f9db, 0x20016000, 
+    0x23009000, 0x46a84858, 0x9158f8df, 0x1106eb00, 0xeb094630, 0xf7e11206, 0x4d54fd11, 0x4f542000, 
+    0x1206eb05, 0x1106eb07, 0x540b5c13, 0xb2001c40, 0xdbf92810, 0x0000f89a, 0xf7eab908, 0x2600fe6d, 
+    0x250146a9, 0x0000f998, 0xd0154286, 0x23004845, 0xeb009500, 0x48441206, 0x1106eb00, 0xf7e14630, 
+    0x2000fced, 0x1106eb09, 0x1206eb07, 0x54135c0b, 0xb2001c40, 0xdbf92810, 0xb2761c76, 0xdbe12e04, 
+    0x06c0f242, 0x06774631, 0xf7db4638, 0x200efcf6, 0x23019000, 0xe9cd4602, 0x46015402, 0x94059404, 
+    0x02189001, 0xfd84f7e3, 0x46384631, 0xfce5f7db, 0x0000f89a, 0x2100b9a0, 0xf7e52001, 0xf998fbe0, 
+    0x21002000, 0x4644200c, 0xf92cf7e5, 0xf9942101, 0x46082000, 0xf96cf7e5, 0x70054826, 0xffbcf7f8, 
+    0x22034825, 0xf0062138, 0xb108fac4, 0xfe02f7e2, 0x220f2301, 0x46104619, 0xfe2bf7e3, 0x46384631, 
+    0xfcbbf7db, 0x88004814, 0xd11a2801, 0x491b4811, 0xf7e26800, 0xf240fecf, 0x465c11f4, 0xf7db4658, 
+    0xf241fc8f, 0x46201100, 0xfc8af7db, 0x46209906, 0xfc86f7db, 0x4620b007, 0xe8bd4904, 0xf7db4ff0, 
+    0xb007bc7f, 0x8ff0e8bd, 0xd003513c, 0xdcba01f5, 0x001312d0, 0x000323ec, 0x00032d34, 0x00032396, 
+    0x00032283, 0x000351fc, 0x0003308c, 0x0003523c, 0x000402c4, 0x00032281, 0xd28f007c, 0x005a000a, 
+    0x4ffee92d, 0x7980f04f, 0x1000f9b0, 0x4615461f, 0x52a0f04f, 0x464c4606, 0xf7db4648, 0xf242fcb0, 
+    0x064801c0, 0xfc69f7db, 0x11f4f240, 0xf7db4620, 0xf64dfc58, 0x462051dd, 0xfc42f7db, 0x83e0f8df, 
+    0xf8984620, 0xf7db1000, 0x49f6fc3b, 0xf7db4620, 0xf8dffc37, 0x2400b3d4, 0xa3d0f8df, 0xeb0b2001, 
+    0xeb0a2244, 0xe88d2144, 0x23000007, 0x461a4621, 0xfa04f7e1, 0xb2641c64, 0xdbef2c04, 0x49ec48ed, 
+    0xf7e26800, 0x2000fe57, 0x0100f640, 0x46024603, 0xf7e69000, 0x48e8fa6d, 0x90008800, 0x780348e7, 
+    0xf99048e7, 0x48e72000, 0x20007801, 0xfb3df7f9, 0x48e52300, 0x461a2101, 0xfa0df006, 0x780048e3, 
+    0xd1022801, 0xf7f92003, 0x2100fc59, 0xf7e34608, 0x2000ff55, 0xfc10f7f9, 0x60386828, 0x4adc6828, 
+    0xd0041c41, 0x31c8f44f, 0x0c014348, 0xf64fe001, 0x461071ff, 0xf9d5f006, 0x14f4f240, 0x46214648, 
+    0xfbeff7db, 0x3133f243, 0xf7db4648, 0x6839fbd9, 0xf7db4648, 0x6829fbd5, 0xf7db4648, 0x4dc1fbd1, 
+    0x46294648, 0xfbccf7db, 0x46484621, 0xfbd9f7db, 0x51ddf64d, 0xf7db4648, 0xf898fbc3, 0x46441000, 
+    0xf7db4648, 0x4629fbbd, 0xf7db4648, 0xf44ffbb9, 0x21003500, 0xf7e24628, 0x2100fde7, 0xf7e24628, 
+    0x2003fde3, 0xfa20f7f9, 0x01c0f242, 0xf7db0648, 0x48b8fbc4, 0x0000f990, 0xd0082805, 0xd0062803, 
+    0x78202505, 0x3780f44f, 0x2400b118, 0x250fe014, 0xf7eae7f7, 0x2400fd01, 0x2100e005, 0xf7e24638, 
+    0x1c64fdc3, 0x42acb264, 0xe007dbf7, 0x46382100, 0xfdbaf7e2, 0xb2641c64, 0xdbf742ac, 0x80302047, 
+    0x8ffee8bd, 0x4ffee92d, 0x7580f04f, 0x1000f9b0, 0x52a0f04f, 0x46284680, 0xfbd1f7db, 0x01c0f242, 
+    0xf7db0648, 0xf240fb8a, 0x462811f4, 0xfb79f7db, 0x51ddf64d, 0xf7db4628, 0x4c89fb63, 0x78214628, 
+    0xfb5ef7db, 0x46284987, 0xfb5af7db, 0xf8df7820, 0xb948b248, 0x0000f89b, 0x11e8b930, 0x0103f640, 
+    0xfb5ff7db, 0xfb09f7ea, 0xf7f92003, 0x2700f9bd, 0x240046a2, 0x78284655, 0x2000b120, 0xf983f7f7, 
+    0xe001b978, 0xe7f92001, 0x2c641c64, 0x4883dbf3, 0xb3586800, 0x21c2f240, 0x782a4b81, 0xf7e21e48, 
+    0x4880fd95, 0x4c7a220d, 0x0100f246, 0xf9903caa, 0xb2830000, 0xf0064620, 0x2300f92e, 0x22054620, 
+    0xf0062120, 0x2301f928, 0x22054620, 0xf0062120, 0xf04ff922, 0xf2480900, 0x464c0600, 0x220f486c, 
+    0x38784631, 0xf925f006, 0xe008b978, 0x0000f89b, 0xd1022805, 0xf7e4486c, 0x210ffe00, 0x1c64e178, 
+    0xdbeb42b4, 0x0f00f1b9, 0x4861d07e, 0xf6432200, 0x387871ff, 0xf90df006, 0xd07607c0, 0x01c0f242, 
+    0xf7db0648, 0xf04ffb0a, 0xf2407480, 0x462011f4, 0xfaf7f7db, 0x1111f241, 0xf7db4620, 0xf8dffae1, 
+    0x4620916c, 0x1000f999, 0xfadaf7db, 0x46204945, 0xfad6f7db, 0x46aa2400, 0x0000f89a, 0xd0042801, 
+    0xf9904853, 0x42840000, 0x4d52d021, 0x96002600, 0x46322001, 0x682b4621, 0xf97df7e1, 0x0000f899, 
+    0x28016829, 0x207fd05d, 0xeb01800e, 0xf8320240, 0xf8212c02, 0x1e402010, 0xdcf62800, 0x23006828, 
+    0x0600e9cd, 0x461a2001, 0xf7e14621, 0x1c64f8ad, 0x2c04b264, 0x4d3fdbd0, 0x46262400, 0x22009600, 
+    0x46104621, 0xf7e1682b, 0xf899f956, 0x68290000, 0xd0712801, 0x800e207f, 0x0240eb01, 0x2c02f832, 
+    0x2010f821, 0x28001e40, 0x6828dcf6, 0xe9cd2300, 0x461a0600, 0x46184621, 0xf886f7e1, 0xb2641c64, 
+    0xdbdb2c04, 0xe0014654, 0xe0ace004, 0x0000f89a, 0xe089b318, 0x1000f9b8, 0x52a0f04f, 0x7080f04f, 
+    0xfacdf7db, 0x0000f89b, 0xd0172805, 0x6800481b, 0xf240b1a0, 0x4b1a21c4, 0x1e48782a, 0xfcc6f7e2, 
+    0x2000e08d, 0x60fef8a1, 0x0240eb01, 0xf8218852, 0x1c402010, 0xdbf7287f, 0xe039e7a0, 0xe02be07f, 
+    0x00032396, 0xdcba01f5, 0x00035a7c, 0x0003527c, 0x00393870, 0x000323ec, 0x000322ac, 0x00032304, 
+    0x00032228, 0x00032411, 0xd00305ae, 0x00032401, 0xd003513c, 0x0003227e, 0x00032cd4, 0x00047f70, 
+    0xd03c80b8, 0x000323ac, 0x000331dc, 0x00032d1a, 0x00032283, 0x00032224, 0xf8a12000, 0xeb0160fe, 
+    0x88520240, 0x2010f821, 0x287f1c40, 0xe78cdbf7, 0x3000f44f, 0x0103f640, 0xfa23f7db, 0xf9cdf7ea, 
+    0x220048c9, 0x0000f990, 0x90029600, 0x682b4601, 0xf7e12001, 0xf899f8c0, 0x68290000, 0xd01b2801, 
+    0x800e207f, 0x0240eb01, 0x2c02f832, 0x2010f821, 0x28001e40, 0x6828dcf6, 0xe9cd2300, 0x99020600, 
+    0x461a2001, 0xfff0f7e0, 0x1000f899, 0xf8894249, 0x78201000, 0xe00db160, 0xf8a12000, 0xeb0160fe, 
+    0x88520240, 0x2010f821, 0x287f1c40, 0xe7e2dbf7, 0xfb42f7ea, 0x01c0f242, 0xf7db0648, 0x1c7ff9ee, 
+    0xf6ff2f04, 0xf7f7ae86, 0x2201f886, 0x20472100, 0xfdc7f7e3, 0xf7e5204e, 0x2301f81b, 0x220f48a3, 
+    0x463103de, 0xffc7f005, 0x0000f89b, 0x2805465c, 0xf89ad005, 0x46550000, 0xd0132801, 0xf44fe017, 
+    0x21002500, 0xf7e24628, 0x2100fbdf, 0xf7e24628, 0x4997fbdb, 0x29047809, 0x2100d116, 0xf7e24628, 
+    0xe011fbd3, 0xf2422100, 0xf7e20000, 0x2004fbcd, 0xf80af7f9, 0x46302100, 0xfbc6f7e2, 0xb9187828, 
+    0xfd2ff7e3, 0xfaf8f7ea, 0x28057820, 0x2149d003, 0x1000f8a8, 0x2148e604, 0xe92de7fa, 0xf9b04ff0, 
+    0x26001000, 0xf04fb089, 0xf04f52a0, 0xf7db7080, 0xf242f9d6, 0x064801c0, 0xf98ff7db, 0xf6494f7d, 
+    0x78384440, 0xf44fb938, 0xf6403000, 0xf7db0103, 0xf7eaf978, 0x2003f922, 0xffd6f7f8, 0x91c8f8df, 
+    0xf8df2300, 0xf04f81d4, 0x49740a04, 0x0000f999, 0xa000f8cd, 0x1200eb08, 0x1100eb01, 0xf94ef7e1, 
+    0x01c0f242, 0xf7db0648, 0x7838f968, 0x486db930, 0x6800496b, 0xfb7ef7e2, 0xfaaef7ea, 0x46c146cb, 
+    0x8198f8df, 0xf99b2500, 0x42850000, 0x2300d009, 0xeb094628, 0xf8cd1205, 0xeb08a000, 0xf7e11105, 
+    0x1c6df92d, 0x2d04b26d, 0xf242dbed, 0x064801c0, 0xf943f7db, 0x46bb7838, 0xd1162801, 0x04c02100, 
+    0xfb52f7e2, 0x3700f44f, 0x46382100, 0xfb4cf7e2, 0xfa22f7ea, 0x00782100, 0xfb46f7e2, 0x0103f640, 
+    0xf7db4638, 0xf7eaf91e, 0x2003f8c8, 0xff7cf7f8, 0xa134f8df, 0x250e2700, 0x0801f04f, 0x1900f240, 
+    0x220e9500, 0x23014648, 0xe9cd4611, 0x96048602, 0x95019605, 0xf9acf7e3, 0x01c0f242, 0xf7db0648, 
+    0x2f01f90c, 0x4840dd11, 0xfbe7f7e4, 0x1000f8da, 0x42a14650, 0x6841d209, 0xd20642a1, 0x42a16881, 
+    0xf8dad203, 0x42a0000c, 0x1c7fd303, 0x2f10b27f, 0xf89bdbd6, 0xb9200000, 0xf8814934, 0xf7f88000, 
+    0x4833fbdb, 0x21382203, 0xfee3f005, 0xf7e2b108, 0x2047fa21, 0x0018f8ad, 0x6802482e, 0xf990482e, 
+    0xa8061000, 0xfd3ef7ff, 0x46a846c3, 0x46552700, 0xf8cd220e, 0x23018000, 0xe9cd4611, 0x4648b602, 
+    0xf8cd9604, 0x96058004, 0xf962f7e3, 0xdd0e2f00, 0xf7e4481d, 0x6828fba2, 0xd20842a0, 0x42a06868, 
+    0x68a8d205, 0xd20242a0, 0x42a068e8, 0x1c7fd303, 0x2f10b27f, 0x4814dbdc, 0xfb8ff7e4, 0xf7f82003, 
+    0x2301ff03, 0x4619220f, 0xf7e34610, 0x4813fa12, 0x28116800, 0xb009d805, 0xe8bd2000, 0xf7e24ff0, 
+    0xb009bf21, 0x8ff0e8bd, 0x00032283, 0xd0035092, 0x0003227e, 0x00032396, 0x000402c4, 0x0003308c, 
+    0x001312d0, 0x000323ec, 0x000331dc, 0x00032281, 0xd28f007c, 0x00032cf4, 0x00032cd4, 0x0003222c, 
+    0x47f0e92d, 0x35e0f240, 0x4617461e, 0x22054688, 0x48134604, 0xe9dd4629, 0xf0059a08, 0xb2c0fe6a, 
+    0x011ff008, 0x1040ea05, 0xf2404301, 0xea004000, 0x43012087, 0x0000f640, 0x20c6ea00, 0x48094301, 
+    0x41a0f441, 0x00c4eb00, 0xfe25f005, 0xea4a4805, 0x1d004109, 0x00c4eb00, 0x47f0e8bd, 0xbe1bf005, 
+    0xd03c821e, 0xd1800200, 0x5ff0e92d, 0xf2404efd, 0x8e81124b, 0xf8df4604, 0xf04f93f0, 0xf8df0800, 
+    0x4291a3ec, 0xf2a14dfa, 0xf8df104b, 0x6833b3e8, 0xdc2bd019, 0x7f80f5b1, 0xdc15d07e, 0xd0562981, 
+    0xb381dc0d, 0xd1782980, 0x0008f8db, 0x46292200, 0xfa38f001, 0xd0481d41, 0xd13b2801, 0x29dee047, 
+    0x29dfd06c, 0xe2fbd169, 0x7180f5a1, 0xd0fa3901, 0xd0782913, 0xd0f62914, 0xd15e2949, 0x220049e4, 
+    0xf0014618, 0x1d40f9f0, 0xe2e9d06e, 0x285c49e2, 0xd0e8680f, 0x281ddc15, 0xdc05d067, 0xd07d2807, 
+    0xd14a2808, 0xe015e2dc, 0xd0dc281e, 0xd144285b, 0x220049d7, 0x31104638, 0xf9d5f001, 0xd06e1d40, 
+    0x2875e2ce, 0x2876d06c, 0x2887d0cd, 0x2888d069, 0xe2a5d133, 0xf04f49ce, 0xf8db32ff, 0xf0010008, 
+    0x1d01f9f1, 0x2080d1b6, 0x2081e2a9, 0xf9b5e2a7, 0x296d1000, 0x074ad1ee, 0xf7db17d0, 0x8868f810, 
+    0xf8ab465a, 0xf9b50000, 0xf8ab1004, 0xf9b51002, 0xf8ab0006, 0xb1d00004, 0xd4080543, 0xf8994fbf, 
+    0xf9973000, 0x433b7000, 0x05c0d111, 0x0689d50f, 0xf8a24640, 0xe0028000, 0xe281e0a8, 0xd502e05e, 
+    0x0020f040, 0xf040e001, 0xf8ab0010, 0xf89a0000, 0x28010000, 0x48b2d00a, 0x21402206, 0xfd99f005, 
+    0x2702b148, 0xe0b3e008, 0xe1a6e180, 0x464049ad, 0x8000f881, 0x2700e011, 0x220d48a9, 0x0100f242, 
+    0xfd87f005, 0x2001b100, 0x2f014307, 0x2000d01e, 0x2f0249a4, 0xd01b7008, 0xe0032000, 0xe1e6e16c, 
+    0xe236e209, 0x700849a0, 0xf9bb4659, 0x04c20000, 0xf420d533, 0xf2415080, 0xf8ab0700, 0x220c0000, 
+    0x4639489a, 0xfd65f005, 0xe021b120, 0xe7df2001, 0xe7e22001, 0x78004896, 0x4a96b1d0, 0x46392005, 
+    0xff9df7da, 0x8028203b, 0x22004893, 0x68004988, 0xf939f001, 0xd1071d01, 0xe22020de, 0x2200488e, 
+    0x68004983, 0xf92ff001, 0xd17c1d40, 0xe21620df, 0x20054a88, 0x0101f241, 0x4f88e220, 0xd5610682, 
+    0x0020f020, 0xf89b8008, 0x4a820002, 0xd5370680, 0xf2422005, 0xf7da0120, 0x4881ff72, 0x8000f887, 
+    0x28017800, 0x487fd00f, 0x28017800, 0x487ed00b, 0x28018800, 0x487dd007, 0x28017800, 0x486fd003, 
+    0x28017800, 0xf899d106, 0xb9180000, 0x0000f89a, 0xd0482800, 0x80282071, 0x22004965, 0xf0016830, 
+    0x1d01f8f2, 0xf240d107, 0xe1d81000, 0x22004960, 0xf0014618, 0x1d40f8e8, 0xf240d1b7, 0xe1ce1001, 
+    0x20052120, 0xff3bf7da, 0x0000f899, 0xd0e02801, 0x0000f89a, 0xd0dc2800, 0x80282007, 0x22004954, 
+    0xf0016830, 0x1d01f8d0, 0xf240d107, 0xe1b61014, 0x2200494f, 0xf0014618, 0x1d40f8c6, 0xf240d195, 
+    0xe1ac1015, 0xd57306c2, 0x0010f020, 0xf89b8008, 0x4a500002, 0xd56c06c0, 0xf2422005, 0xf7da0110, 
+    0x220eff0e, 0xe10be000, 0xf2444851, 0xf0050100, 0x4950fcc0, 0x20014602, 0xff01f7da, 0xf8874848, 
+    0x78008000, 0xd00f2801, 0x78004846, 0xd00b2801, 0x88004845, 0xd0072801, 0x78004844, 0xd0032801, 
+    0x78004836, 0xd1062801, 0x0000f899, 0xf89ab918, 0x28000000, 0x4840d08d, 0x28016800, 0x483fd10a, 
+    0x28017800, 0xf899d106, 0xb9180000, 0x6800483c, 0xd0092810, 0x80282070, 0x22004925, 0xf0016830, 
+    0x1d01f872, 0xe07cd075, 0x220e4831, 0x0100f244, 0xfc7ff005, 0xf04f4f2e, 0x1ebf0300, 0xd0192801, 
+    0xf248220f, 0x46380100, 0xfc65f005, 0x21004a2d, 0xf7da2001, 0x2070feb4, 0x49158028, 0x68302200, 
+    0xf851f001, 0xf47f1d01, 0xf240ae5e, 0xe136104a, 0xe05be07d, 0xf244220e, 0x46380100, 0xfc4bf005, 
+    0x46382301, 0x03d9220f, 0xfc45f005, 0x23014818, 0x02592209, 0xf0053842, 0x2100fc3e, 0x20014a1a, 
+    0xe036e12c, 0x00032564, 0x00032279, 0x00032278, 0x00040344, 0x00032f4c, 0x00032ca0, 0x00032271, 
+    0xd28fffc0, 0x00032234, 0x00032235, 0xd003902c, 0x00032239, 0xcccc0000, 0x00032cac, 0x00032366, 
+    0x000323bd, 0x000323bf, 0x00032272, 0x00032276, 0xd28e0042, 0x22222220, 0x00032374, 0x0003237c, 
+    0x0003222c, 0x4a12ec0f, 0xf0ce21a4, 0x104bf240, 0xf240e0e5, 0xe0e21052, 0x22004983, 0xf0004618, 
+    0x1d40fff2, 0xf240d14c, 0xe0d81053, 0x20052110, 0xfe45f7da, 0x0000f899, 0xd0412801, 0x0000f89a, 
+    0x2007b3f0, 0x49788028, 0x68302200, 0xffdbf000, 0xd1071d01, 0x1068f240, 0x4973e0c1, 0x46182200, 
+    0xffd1f000, 0xd12b1d40, 0x1069f240, 0x0442e0b7, 0xf420d57c, 0x80084080, 0x0002f8bb, 0x04404a6b, 
+    0x2102d548, 0xf7da2005, 0x2201fe1a, 0x8000f887, 0x20022100, 0xfcc1f7e3, 0x20012200, 0xf7e34611, 
+    0x4863fcbc, 0xb1487800, 0x78014862, 0x78034862, 0x78024862, 0x78004862, 0xfca4f7e5, 0xe0004861, 
+    0x4961e047, 0xf9917800, 0x43081000, 0xf991495f, 0x43081000, 0xf7dcd103, 0xf7f5f917, 0x485cfece, 
+    0xb3b08800, 0x21734850, 0x30102200, 0x21018001, 0x49507081, 0x70c17809, 0x48564601, 0xf0006800, 
+    0x1d01ff82, 0xadaaf47f, 0x10a6f240, 0xf240e067, 0xe06410a7, 0x20052103, 0xfdd1f7da, 0xf8f4f7dc, 
+    0xfec1f7f5, 0x8800484a, 0x483fb198, 0x22002173, 0x80013010, 0xf880493f, 0x78098002, 0x460170c1, 
+    0x68004844, 0xff5ff000, 0xd10a1d01, 0x10c0f240, 0xe055e045, 0x4934e00a, 0x46382200, 0xf0003110, 
+    0x1d40ff52, 0xf240d14c, 0xe03810c1, 0xd53c0742, 0x0004f020, 0x0000f8ab, 0x0000f89a, 0xd1042801, 
+    0x88004835, 0x0040f030, 0x4a28d002, 0xe0342108, 0x4a262104, 0xf7da4608, 0x2074fd92, 0x49228028, 
+    0x68302200, 0xff2ff000, 0xd1071d01, 0x10d2f240, 0x491de015, 0x46182200, 0xff25f000, 0xd00c1d40, 
+    0x22024826, 0xf0052104, 0x2801fb34, 0x2004d00a, 0xfef3f7e1, 0x21064a15, 0xf240e00f, 0x86a010d3, 
+    0x9ff0e8bd, 0x21054a11, 0x0602e007, 0x4a0fd508, 0xf020210c, 0xf8ab0080, 0x20040000, 0xfd5ff7da, 
+    0x0000f8bb, 0xf47f2800, 0xe533ad9f, 0x21012200, 0xf2afb510, 0xf000606b, 0x2108fd41, 0xf0002004, 
+    0x490ffe9f, 0xbd106088, 0x00040344, 0xcccc0000, 0x00032368, 0x0003227e, 0x00032431, 0x00032430, 
+    0x00032367, 0x000323bf, 0x000323bd, 0x00032271, 0x0003233c, 0x00032ca0, 0x0003227c, 0xd0039026, 
+    0x00032f4c, 0x4ff0e92d, 0x4605b09d, 0xf8df2400, 0xf88d942c, 0x9418406c, 0x8e80941c, 0x7f62f5b0, 
+    0xdc05d076, 0x28d8b170, 0x28d9d018, 0xe020d171, 0x7040f5a0, 0xd06d3889, 0x7080f5a0, 0xd06a383d, 
+    0xd1662801, 0xf04f49fd, 0xf8d932ff, 0x31280020, 0xfed8f000, 0xd1081d01, 0xe35f20d8, 0x220049f7, 
+    0x0020f8d9, 0xf0003128, 0x1d41fecd, 0x2801d018, 0x48f2d1e8, 0x88003028, 0xd1e32865, 0x230148f0, 
+    0x21042202, 0xfa97f005, 0x0000f899, 0xd009280d, 0xf8891c40, 0x48eb0000, 0x28027800, 0xe022d012, 
+    0xe33b20d9, 0xf8894ee8, 0x46304000, 0xfa66f005, 0x20014607, 0xf96ef7f9, 0x0100ea47, 0xf0054630, 
+    0xe7e8fa60, 0x780048e1, 0xd10c2801, 0xa380f8df, 0x0000f89a, 0x2801b300, 0x2802d028, 0x2803d02d, 
+    0xf88ad07e, 0x22084000, 0x015148da, 0xfa71f005, 0xd0762800, 0x0008f8b9, 0x1c40210a, 0xf8a9b280, 
+    0xfbb00008, 0xfb01f2f1, 0x28000012, 0xe1e4d06a, 0xe3b4e305, 0xe3f3e21b, 0xf822f7ea, 0xf88a2001, 
+    0x48cd0000, 0x48cd7004, 0xe7dc7004, 0xf850f7ea, 0x2002b108, 0x2001e0fb, 0xf7eae0f9, 0x2800f857, 
+    0xf7e9d0f7, 0x2100fffa, 0x3080f44f, 0xfe5cf7e1, 0xc30cf8df, 0x4ec32000, 0xeb062200, 0xe9c101c0, 
+    0xeb0c2200, 0x1c4001c0, 0xe9c12804, 0xdbf32200, 0xb2f4f8df, 0xa8192700, 0xf805f7ea, 0xf7ea4668, 
+    0x2600f810, 0xf830a819, 0xf0070016, 0x2200faa5, 0xf007465b, 0x4ab2f8d5, 0x03c6eb02, 0xcb0c4698, 
+    0xf812f007, 0x0100e9c8, 0x465b4668, 0x00c6eb00, 0xe9d02200, 0x46610c00, 0xf8c2f007, 0xeb024aa9, 
+    0x469803c6, 0xf006cb0c, 0x1c76ffff, 0xe9c82e04, 0xdbd70100, 0xf2402100, 0xf7e12000, 0xe002fe15, 
+    0xe171e008, 0x1c7fe0a6, 0xdbc42f64, 0xf88a2103, 0xe7781000, 0xab082000, 0x2600aa10, 0x01c0eb02, 
+    0x6600e9c1, 0x01c0eb03, 0x28041c40, 0x6600e9c1, 0xf8dfdbf3, 0x2700b254, 0xf7e9a819, 0x4668ffb4, 
+    0xffbff7e9, 0xa8192600, 0x0016f830, 0xfa54f007, 0x465b2200, 0xf884f007, 0xeb02aa08, 0x469803c6, 
+    0xf006cb0c, 0xe9c8ffc1, 0x46680100, 0xeb00465b, 0x220000c6, 0x0c00e9d0, 0xf0074661, 0xaa10f871, 
+    0x03c6eb02, 0xcb0c4698, 0xffaef006, 0x2e041c76, 0x0100e9c8, 0x2100dbd7, 0x2000f240, 0xfdc4f7e1, 
+    0x2f641c7f, 0x2700dbc8, 0xa808463e, 0x00c6eb00, 0x2300e9d0, 0xeb004872, 0xe9d101c6, 0x46800100, 
+    0xf007468b, 0xf007fc75, 0x2800f9a3, 0x4240da00, 0xf9fbf007, 0x465b4642, 0xf842f007, 0x486b4684, 
+    0x2300e9d0, 0xf0074660, 0xd206fb55, 0x78084962, 0xd00128ff, 0x70081c40, 0x48622701, 0x00c6eb00, 
+    0x2300e9d0, 0xeb00a810, 0xe9d101c6, 0xf0070100, 0x4684f827, 0xe9d0485e, 0x46602300, 0xfb3af007, 
+    0x4956d206, 0x28ff7808, 0x1c40d001, 0x27017008, 0x2e041c76, 0xb14fdbb9, 0xff22f7e9, 0xf44f2100, 
+    0xf7e13000, 0xf7e9fd71, 0xe702ff08, 0xf88a2003, 0xe6d80000, 0x7800484f, 0xd17c2802, 0x30164842, 
+    0xf91cf005, 0xf006b2c6, 0x280a000f, 0xf7f5d174, 0xf8dffcce, 0x28018124, 0x4848d037, 0x373a4f3a, 
+    0x0000f990, 0xd0422803, 0xd0402805, 0xd03e2804, 0x46382300, 0x21102204, 0xf91df005, 0x30344832, 
+    0xf8fcf005, 0x48304607, 0xf0053032, 0xea47f8f7, 0x482d4a00, 0xf0053038, 0x4607f8f1, 0x3036482a, 
+    0xf8ecf005, 0x4b00ea47, 0xebb02003, 0xd1201f16, 0x1018f8d9, 0xf7f54650, 0xf8d9fc90, 0x4607101c, 
+    0xf7f54658, 0x4438fc8a, 0xf88de024, 0x27fe406c, 0x1001f899, 0xd10729fe, 0x0003f899, 0xd1034286, 
+    0x0000f898, 0xd15c2801, 0x32fff04f, 0x2301e063, 0x2001e7bf, 0x1f16ebb0, 0xf8d9d103, 0x46501018, 
+    0x2002e006, 0x1f16ebb0, 0xf8d9d105, 0x4658101c, 0xfc63f7f5, 0xa91b9018, 0xab06e9c9, 0xf7f59818, 
+    0x4607fc2e, 0x0003f899, 0xd14342b0, 0x0000f898, 0xd03f2801, 0xe050e024, 0x0000e039, 0x00032f58, 
+    0xd03c8318, 0x0003227e, 0xd03c80ba, 0x00032360, 0x00032348, 0xd28f2002, 0x00032349, 0x0003234a, 
+    0x0003fe48, 0x0003fe68, 0x40590000, 0x00032350, 0x00032358, 0x000323be, 0x00032339, 0x00032238, 
+    0x1001f899, 0xd105428f, 0x106cf89d, 0x0002f899, 0xd0064281, 0xb27148fa, 0xf9909a18, 0xf7f50000, 
+    0xf889f840, 0xf89d7001, 0xf889106c, 0xf8891002, 0xe0126003, 0xb2719a18, 0xf99048f1, 0xf7f50000, 
+    0xf888f830, 0xe7ec4000, 0x4008f8a9, 0xf88921fd, 0xf8891003, 0xf8891001, 0x4eea1002, 0xf8df4fea, 
+    0x783083ac, 0xd0052801, 0x28016838, 0xf8a9d002, 0xe01b4016, 0x0016f8b9, 0xf8a91c40, 0x07000016, 
+    0xf003d11a, 0x7831fed0, 0x29014be1, 0x681ad102, 0xda2a4290, 0x2a01683a, 0x4aded023, 0xda0b4282, 
+    0xd0282901, 0x71fff647, 0xdd054281, 0x46402300, 0x21022201, 0xf83ff005, 0xf99048d7, 0x28030000, 
+    0x2805d01e, 0x2804d01c, 0xf8a9d01a, 0x27254014, 0x780048d2, 0xd07d2801, 0x1004f899, 0xd17a2900, 
+    0x4acfe1cf, 0x42906812, 0x2301dc01, 0x4ecde7df, 0x44326836, 0x4acce7d2, 0x68126819, 0xe7d31a89, 
+    0x1014f8b9, 0x1c4948c9, 0x1014f8a9, 0xfff6f004, 0x06004606, 0x48c6d518, 0x28017800, 0xf7f7d005, 
+    0x48c4fe9b, 0xb1387800, 0xf899e00b, 0x06c00014, 0xf7f7d10a, 0xe007fe91, 0x780048bf, 0x2001b108, 
+    0x2000e000, 0xfd37f7e9, 0xd5030730, 0x780048bb, 0xfcf2f7f7, 0xd5150430, 0x0014f8b9, 0x0580464f, 
+    0xf7e1d101, 0x7d38fa70, 0x0f05f010, 0x4fb4d10a, 0xb1387838, 0xfb2ef7e1, 0x200149b2, 0x7008703c, 
+    0xfa61f7e1, 0xd50b04f0, 0x0014f899, 0xd1070640, 0xffecf7f3, 0x780048ac, 0x2000b110, 0xf92af7f4, 
+    0x780048aa, 0xd1582801, 0x780048a9, 0xd1542801, 0x0007f899, 0x1c404aa7, 0xf889b2c0, 0x78120007, 
+    0xd94a4290, 0x46c848a4, 0x4007f889, 0x28017800, 0xe001d02b, 0xe071e06e, 0xd0262802, 0xf004489f, 
+    0x4607ff8d, 0x1c80489d, 0xff88f004, 0x1024f8d8, 0x4000ea47, 0x4a9b4f9a, 0xd0054288, 0x2101783b, 
+    0x68134099, 0x60114319, 0x4b977839, 0xb2c91c49, 0x781b7039, 0xd3004299, 0x2100703c, 0x0024f8c8, 
+    0x68174608, 0x0c01f04f, 0x488ce00f, 0xf0041f00, 0x4607ff65, 0x1e804889, 0xfa0ce7d6, 0x423af200, 
+    0x1c49d001, 0x1c40b2c9, 0x4298b2c0, 0x4887d3f5, 0x42817800, 0x2001d901, 0x0570901c, 0xf899d509, 
+    0x07000014, 0x4871d105, 0xf0041f80, 0x07c0ff47, 0x981cd103, 0xf47f2801, 0x2000af2a, 0xf7fb901c, 
+    0x487bfd25, 0x22002143, 0x46018001, 0x68004879, 0xfb49f000, 0xd1081d01, 0x3088f240, 0x4875e13b, 
+    0x49732200, 0xf0006800, 0x1d40fb3e, 0xf240d1e3, 0xe1303089, 0x0004f899, 0xb318464e, 0x0004f899, 
+    0x2801464e, 0xf7e7d049, 0x2200fa98, 0x3133f04f, 0x200171b0, 0xf983f7da, 0x220079b1, 0xf7da2001, 
+    0xf9b6f97e, 0x22001010, 0xf7da2001, 0x79b0f978, 0x28002123, 0x0010f9b6, 0x2825d05f, 0x2823d03c, 
+    0xe051d045, 0x1c407970, 0x7170b2c0, 0xd31b2828, 0x22054859, 0xf0042120, 0xb928ff1c, 0x384e483b, 
+    0xfeecf004, 0xd01007c0, 0x28258a30, 0x2104d00b, 0x20188237, 0xfdb4f7f6, 0x94002300, 0x46192201, 
+    0xf7f64618, 0x7174fc8d, 0x7972e09d, 0x494b2001, 0xf945f7da, 0x71302001, 0x2200e7f5, 0x3122f04f, 
+    0xf7da2001, 0x2003f93c, 0xfa2bf7e7, 0xf7e72001, 0x2002fa91, 0xe0867130, 0x82312014, 0xf7f62100, 
+    0x2300fd8f, 0x22019400, 0x46184619, 0x2022e00a, 0x21008230, 0xf7f62014, 0x2300fd83, 0x22019400, 
+    0x46104619, 0xfc5cf7f6, 0x1c408a70, 0x4817b281, 0x384c8271, 0xfea5f004, 0x2822e014, 0x2823d002, 
+    0xe00fd004, 0x21008231, 0xe0022014, 0x82372104, 0xf7f62018, 0x2300fd65, 0x22019400, 0x46184619, 
+    0xfc3ef7f6, 0xf7e72002, 0x2000f9ec, 0xfa52f7e7, 0x71342200, 0x20011e51, 0xf8f1f7da, 0xe08be043, 
+    0x0003227e, 0x000322ef, 0x000322f8, 0xd00351da, 0x000322f0, 0xffff8001, 0x00032238, 0x00032366, 
+    0x000322fc, 0x00032300, 0x000322f4, 0xd03c80b6, 0x00032282, 0x00032396, 0x000322b7, 0x00032281, 
+    0x0003229c, 0x0003229d, 0x00032331, 0x000323fc, 0x000322c2, 0x000323fb, 0x00032411, 0xd0036116, 
+    0x000323f8, 0x000323f4, 0x000323f9, 0x000323fa, 0x00032f80, 0x00032d0c, 0xd28f2034, 0x11111110, 
+    0xf889e03e, 0x482d4005, 0x28017800, 0xf8b9d12a, 0x464e000a, 0xb2801c40, 0x000af8a9, 0xd3212822, 
+    0x22044827, 0x817421f0, 0xfe53f004, 0xd1182804, 0xf0044824, 0xf3c0fe23, 0x280400c2, 0x89b0d111, 
+    0xb2801c40, 0x280481b0, 0x481fd30c, 0x0101f242, 0xfe17f004, 0x1c4089f0, 0x481cb281, 0xf00481f1, 
+    0x81b4fe10, 0x481a2129, 0x80012200, 0x48194601, 0xf0006800, 0x1d01fa18, 0xf240d108, 0xe00a40c6, 
+    0x22004814, 0x68004912, 0xfa0df000, 0xf47f1d40, 0xf240ab59, 0x86a840c7, 0xe8bdb01d, 0x22008ff0, 
+    0xb5102101, 0x10a3f6af, 0xf848f000, 0x200a2108, 0xf9a6f000, 0x39284906, 0xbd106208, 0x00032277, 
+    0xd28f0004, 0xd28f2056, 0xd28e002c, 0xd03c80bc, 0x00032f80, 0x00032c90, 0xb5082008, 0xfaaff7e1, 
+    0x90002000, 0x46032201, 0x20084601, 0xfaecf7e1, 0x20084908, 0xfab2f7e1, 0xf7e14807, 0x2008fb08, 
+    0xfab1f7e1, 0xf2462201, 0xe8bd11a8, 0x20034008, 0xb9c8f7e1, 0x00026f58, 0xc1000184, 0xf8bcf000, 
+    0x8e80e7fc, 0xd1012800, 0xbd72f005, 0x22004770, 0xf2af4611, 0xf0000011, 0x0000b801, 0x47f0e92d, 
+    0x460e4691, 0x20384682, 0xfc20f000, 0xd0440004, 0xf8df4f86, 0x6838821c, 0x2500b9d8, 0xeb05603c, 
+    0xeb080185, 0xf0000081, 0x1c6df905, 0xd3f62d02, 0x3028487f, 0xf8fef000, 0x303c487d, 0xf8faf000, 
+    0x3050487b, 0xf8f6f000, 0x30284879, 0x30146178, 0x2e0261b8, 0x2601d300, 0x86a02000, 0xa000f8c4, 
+    0xe9c41d20, 0xf000690b, 0xf104f8f0, 0xf0000018, 0x6124f8ec, 0x000af1c6, 0x61a06264, 0x68796ae0, 
+    0xd9004288, 0xeb006078, 0xeb080180, 0x1d210081, 0xf8def000, 0xe8bd2001, 0xf04f87f0, 0xe7fa30ff, 
+    0x4d62b570, 0x68a9460e, 0x6828180c, 0xf0001d00, 0x6829f8f5, 0x68a8604c, 0xd2014284, 0xe00069a8, 
+    0x1d096968, 0xf8d2f000, 0xd0062e00, 0x46306829, 0x4070e8bd, 0xf0003118, 0xbd70b8c9, 0xf000b570, 
+    0x4d52fb2d, 0x1a4068e9, 0xe02f6128, 0x0101f1a1, 0x1c406129, 0xd10360a8, 0x1005e9d5, 0x0105e9c5, 
+    0x69684e4b, 0xb1f16801, 0x68c468c0, 0x6860e01c, 0x428868a9, 0xb672d81a, 0xf0001d20, 0x6aa0f8bf, 
+    0xf104b118, 0xf0000018, 0xb662f8b9, 0x68696ae0, 0xd9004288, 0xeb006068, 0x1d210080, 0x0080eb06, 
+    0xf886f000, 0x2400e7dd, 0xd1e02c00, 0x68a86929, 0xd1cb2900, 0xbd7060e8, 0xf000b510, 0xf7fff840, 
+    0x4932ffbd, 0x68484a32, 0x2800e003, 0x1e40d01b, 0xeb006048, 0xf8520380, 0x2b003023, 0xeb00d0f5, 
+    0xeb020080, 0x68420080, 0xf1006852, 0x60420308, 0xd101429a, 0x60426852, 0x600868d0, 0x6b016802, 
+    0x4010e8bd, 0xbd104710, 0x6801b570, 0x68c0b111, 0xe00068c4, 0xf1042400, 0x46050018, 0xf86ef000, 
+    0x4629481b, 0xf0003050, 0x4918f843, 0x68096ae0, 0x42886ac9, 0x2001d301, 0x2000bd70, 0xe92dbd70, 
+    0x4d1341f0, 0x4f124e11, 0xe01a3550, 0x6828b672, 0x68e8b110, 0xe00068c4, 0xf1042400, 0xf0000018, 
+    0xb662f84d, 0xf0001d20, 0x6ae0f849, 0x42886871, 0x6070d900, 0x0080eb00, 0xeb071d21, 0xf0000080, 
+    0x6828f817, 0xd1e12800, 0x81f0e8bd, 0x00032f88, 0x00040360, 0x32fff04f, 0x0108f100, 0x1201e9c0, 
+    0x610160c1, 0x60012100, 0x21004770, 0x47706101, 0x68536842, 0x6843604b, 0x6853608b, 0x60516099, 
+    0x61086041, 0x1c496801, 0x47706001, 0x680bb510, 0xd0021c5a, 0x0208f100, 0x6902e002, 0x6852e004, 
+    0x68246854, 0xd9fa429c, 0x604b6853, 0x608a6099, 0x61086051, 0x1c496801, 0xbd106001, 0x1201e9d0, 
+    0xe9d0608a, 0x60511201, 0x684a6901, 0xd1014282, 0x604a6882, 0x61022200, 0x1e406808, 0x47706008, 
+    0x0005b570, 0xd028460e, 0xf000204c, 0x0004fabf, 0xfb05d023, 0x1c40f006, 0xfab8f000, 0xb1c86020, 
+    0x0106fb05, 0x21006061, 0x1e6963a1, 0xfb0160a0, 0x63e50006, 0xf04f60e0, 0xe9c430ff, 0x64a06010, 
+    0x0010f104, 0xff96f7ff, 0x0024f104, 0xff92f7ff, 0xbd704620, 0xf0004620, 0x2000faa5, 0xb510bd70, 
+    0x6c024613, 0xb16a4604, 0x68e0b183, 0xeddef003, 0x6c2068e1, 0x60e11a09, 0x42916822, 0x6861d202, 
+    0x60e01a08, 0x1c406ba0, 0xbd1063a0, 0xf00368a0, 0x6c21edce, 0x440868a0, 0x686160a0, 0xd3f14288, 
+    0x60a06820, 0xb570e7ee, 0x460e4615, 0xb6724604, 0xf875f000, 0xb145b160, 0x0110f104, 0xf7ff4628, 
+    0xb662fe8f, 0x0003f06f, 0xb662bd70, 0xbd702000, 0xbf00b662, 0x6ba0b672, 0x42886be1, 0x2200d20e, 
+    0x46204631, 0xffbbf7ff, 0x25016a60, 0xf104b138, 0xf7ff0024, 0xb110fef9, 0xe0001fad, 0xb6622500, 
+    0xbd704628, 0x460bb570, 0xb6724604, 0xb1f06b80, 0xbf00b662, 0x6ba0b672, 0x6c22b330, 0x441068e0, 
+    0x686160e0, 0xd3014288, 0x60e06820, 0x1e406ba0, 0x68e163a0, 0xf0034618, 0x6920ed7a, 0xb1a02501, 
+    0x0010f104, 0xfed0f7ff, 0x1fadb178, 0xb142e00d, 0x0124f104, 0xf7ff4610, 0xb662fe43, 0x0003f06f, 
+    0xb662bd70, 0xbd702000, 0xb6622500, 0xbd704628, 0x4604b570, 0x46156b80, 0x42906be2, 0x2200d20d, 
+    0xf7ff4620, 0xb945ff6c, 0xb1306a60, 0x0024f104, 0xfeaaf7ff, 0x2001b108, 0x4628bd70, 0xb510bd70, 
+    0xf0004604, 0x6ba0fa54, 0x42886be1, 0x2401d101, 0x2400e000, 0xfa51f000, 0xbd104620, 0x680148ed, 
+    0x6800b111, 0x47706b00, 0x47702000, 0x5ff0e92d, 0x4615469a, 0x46834689, 0xe9dd2058, 0xf000680a, 
+    0x0004f9d5, 0x00afd009, 0xf0004638, 0x6320f9cf, 0x22a5b3d8, 0xf0034639, 0x2c00fd8f, 0x6b21d07e, 
+    0x0003f06f, 0x0085eb00, 0x44084635, 0xf0204649, 0x22200707, 0x0034f104, 0xed86f003, 0xf8842000, 
+    0x2d0a0053, 0x2509d300, 0x1d2062e5, 0xfeadf7ff, 0x0018f104, 0xfea9f7ff, 0xf1c56124, 0x6264010a, 
+    0x46384652, 0x465961a1, 0xf9baf000, 0xf0006020, 0x4fc8f9fe, 0x1c4068b8, 0x68b860b8, 0x9318f8df, 
+    0xd0082801, 0xb35069b8, 0xe7ffe02e, 0xf0004620, 0x2400f999, 0x603ce7c1, 0xeb052500, 0xeb090185, 
+    0xf7ff0081, 0x1c6dfe77, 0xd3f62d0a, 0x30c848ba, 0xfe70f7ff, 0x30dc48b8, 0xfe6cf7ff, 0x30f048b6, 
+    0xfe68f7ff, 0xf7ff48b5, 0x48b4fe65, 0xf7ff3014, 0x48b2fe61, 0x63b8383c, 0x63f83014, 0x6838e004, 
+    0x42b06ac0, 0x603cd800, 0x69396ae0, 0xd9004288, 0x6af96138, 0x1c496561, 0x697962f9, 0xd9004288, 
+    0xeb006178, 0xeb090180, 0x1d210081, 0xfe50f7ff, 0xf0002501, 0xf1b8f9b2, 0xe0000f00, 0xd001e00c, 
+    0x4000f8c8, 0xb12069b8, 0x6ac06838, 0xd20042b0, 0x4628df00, 0x9ff0e8bd, 0x35fff04f, 0xb570e7f9, 
+    0x69e84d94, 0x6a28b118, 0x62281c40, 0x68e8bd70, 0x60e81c40, 0xb93068e8, 0x6be96ba8, 0x63e863a9, 
+    0x1c406aa8, 0x4e8c62a8, 0x6860e018, 0x428868e9, 0x1d20d8ec, 0xfe42f7ff, 0xb1186aa0, 0x0018f104, 
+    0xfe3cf7ff, 0x69696ae0, 0xd9004288, 0xeb006168, 0x1d210080, 0x0080eb06, 0xfe0af7ff, 0x68006ba8, 
+    0x6ba8b118, 0x68c468c0, 0x2400e000, 0xd1dc2c00, 0xe92dbd70, 0x270047f0, 0xf959f000, 0x69f04e75, 
+    0x61f01e40, 0xbb7869f0, 0xb36868b0, 0x81ccf8df, 0xf8df2500, 0xf1a891c4, 0xe0180814, 0x0018f104, 
+    0xfe0cf7ff, 0xf7ff1d20, 0x6ae0fe09, 0x42886971, 0x6170d900, 0x0180eb00, 0x0081eb09, 0xf7ff1d21, 
+    0x6ae0fdd7, 0x6ac96831, 0xd3004288, 0xf8d82501, 0x46401000, 0x68c0b111, 0xe00068c4, 0x2c002400, 
+    0x6a30d1dc, 0xe008b930, 0xf7ffe00f, 0x6a30ff88, 0x62301e40, 0x28006a30, 0xb915d1f7, 0x28016a70, 
+    0x2701d103, 0x62702000, 0xf000df00, 0x4638f916, 0x87f0e8bd, 0x69c1484f, 0x61c11c49, 0xf0004770, 
+    0xdf00f870, 0xfc6af7ff, 0xb51fe7f9, 0x484e2400, 0x4623a14b, 0x2200f240, 0x94019400, 0x94039402, 
+    0xfeb4f7ff, 0xd1082801, 0x2101b672, 0x61814841, 0xe8bd60c4, 0xf000401f, 0xbd1fb8e3, 0xf000b510, 
+    0x483cf8e6, 0xf00068c4, 0x4620f8e8, 0x4939bd10, 0x4a3969c8, 0x2001b120, 0x47706248, 0x61481e40, 
+    0xeb006948, 0xf8520080, 0x28000020, 0xd0f56948, 0x0080eb00, 0x0080eb02, 0x68526842, 0x0308f100, 
+    0x429a6042, 0x6852d101, 0x68d06042, 0x6b086008, 0xd0e22800, 0x6b4a6808, 0x42906d40, 0x6c08d0dd, 
+    0x30086c8a, 0xd20f4290, 0x6d406808, 0x68c86348, 0x60106c0a, 0x1d006c08, 0x6c0a6408, 0x60106b48, 
+    0x1d006c08, 0x47706408, 0x63082000, 0xb5104770, 0x6b004604, 0xf846f000, 0xe8bd4620, 0xf0004010, 
+    0xb570b841, 0x68684d13, 0xd0222800, 0xff82f7ff, 0x68304e12, 0x2400b158, 0xff2bf7ff, 0xd1182c00, 
+    0xf885f000, 0xb1206830, 0x68c468f0, 0x2401e002, 0x2400e7f2, 0xf7ff1d20, 0x68a8fd41, 0x60a81e40, 
+    0x1e406868, 0xf0006068, 0x4620f878, 0x4070e8bd, 0xbd70e7cd, 0x00032fa4, 0x000403c4, 0x000404c8, 
+    0x454c4449, 0x00000000, 0x00026d1f, 0x4604b510, 0xff50f7ff, 0xf0034620, 0x4604fa91, 0xfef9f7ff, 
+    0xbd104620, 0x0004b510, 0xf7ffd008, 0x4620ff43, 0xfab3f003, 0x4010e8bd, 0xbeebf7ff, 0x0000bd10, 
+    0x60011d09, 0xf04f1f01, 0x600b33aa, 0xf04f1f09, 0x60083312, 0x600b1f09, 0xf04f1f09, 0x600b3311, 
+    0xf04f1f09, 0x600b3310, 0xf04f1f09, 0x600b3309, 0xf04f1f09, 0x600b3308, 0xf04f1f09, 0x600b3307, 
+    0xf04f1f09, 0x600b3306, 0xf04f1f09, 0x600b3305, 0xf04f1f09, 0x600b3304, 0xf04f1f09, 0x600b3303, 
+    0xf04f1f09, 0x600b3302, 0x105b1f09, 0x1f09600b, 0x1f09600a, 0x600a223f, 0xf8402100, 0x47701d44, 
+    0xf7ffb510, 0xf004fb49, 0x2000e94e, 0xb672bd10, 0x68414808, 0x60411c49, 0x48064770, 0x29006841, 
+    0x6841d006, 0x60411e49, 0x28006840, 0xb662d100, 0x00004770, 0x00032ff0, 0xe92d503f, 0xe59f0068, 
+    0xfa00107d, 0xfbffff24, 0xe59f4060, 0xe1d400b0, 0xe2800001, 0xe6ff0070, 0xe1c400b0, 0xe3500b01, 
+    0x3a00000c, 0xe2841008, 0xe3a00065, 0xe3a02000, 0xe1c100b0, 0xe59f0038, 0xe5900000, 0xfafffeab, 
+    0xe59f1030, 0xe5912000, 0xe0800002, 0xe5810000, 0xe3a00000, 0xe1c400b0, 0xe59f001c, 0xfbff830a, 
+    0xf57ff05f, 0xe8bd503f, 0xe25ef004, 0xd03c824a, 0x00032ff0, 0x00032f78, 0x00032230, 0xc1000184, 
+    0x21012300, 0xb510461a, 0xf00448fe, 0x48fdf8d4, 0x220e2300, 0x0100f244, 0x4010e8bd, 0xf0043010, 
+    0xe92db8ca, 0x48f75ff0, 0x011af24a, 0xf004301e, 0x48f4f8a8, 0x3100f240, 0xf0043020, 0x48f1f8a2, 
+    0x302221ef, 0xf89df004, 0xf24948ee, 0x30263184, 0xf897f004, 0x210048eb, 0xf0043028, 0x48e9f892, 
+    0x0100f244, 0xf004302c, 0x48e6f88c, 0x0100f243, 0xf004302e, 0x4ce3f886, 0x111af241, 0x46203430, 
+    0xf87ff004, 0xf2411ca5, 0x46282112, 0xf879f004, 0x21131d26, 0xf0044630, 0x1da7f874, 0x46382100, 
+    0xf86ff004, 0x0806f105, 0x4121f247, 0xf0044640, 0xf106f868, 0x21000906, 0xf0044648, 0xf107f862, 
+    0xf2410b06, 0x46510a00, 0xf0044658, 0xf108f85a, 0xf64a0006, 0xf0042100, 0x48caf854, 0x01fff244, 
+    0xf004304e, 0x1fa0f84e, 0xf0044651, 0x2100f84a, 0xf0041fa0, 0x2100f846, 0xf0044620, 0x2100f842, 
+    0xf0044628, 0x2100f83e, 0xf0044630, 0x2100f83a, 0xf0044638, 0x2100f836, 0xf0044640, 0x2100f832, 
+    0xf0044648, 0x2100f82e, 0xf0044658, 0x2100f82a, 0x0006f108, 0xf825f004, 0x210048b2, 0xf004304e, 
+    0xf643f820, 0x4620412d, 0xf81bf004, 0x1128f642, 0xf0044628, 0x2174f816, 0xf0044630, 0x2100f812, 
+    0xf0044640, 0x2100f80e, 0xf0044648, 0x48a5f80a, 0x0137f248, 0xf004304e, 0x1fa0f804, 0xf0044651, 
+    0x2100f800, 0xf0031fa0, 0x2100fffc, 0xf0034620, 0x2100fff8, 0xf0034628, 0x2100fff4, 0xf0034630, 
+    0x2100fff0, 0xf0034640, 0x2100ffec, 0xf0034648, 0x4894ffe8, 0x304e2100, 0xffe3f003, 0x46202103, 
+    0xffdff003, 0x5140f240, 0xf0034628, 0xf640ffda, 0x46306140, 0xffd5f003, 0x0141f640, 0xf0034638, 
+    0xf241ffd0, 0x46403144, 0xffcbf003, 0x0006f108, 0x011cf245, 0xffc5f003, 0xf1092140, 0xf0030006, 
+    0xf10bffc0, 0xf6450006, 0xf003113b, 0x487dffba, 0x4100f240, 0xf0033044, 0x21d0ffb4, 0xe8bd1fa0, 
+    0xf0035ff0, 0xe92dbfae, 0x48765ff0, 0x011af24a, 0xf003301e, 0x4873ffa6, 0x3100f240, 0xf0033020, 
+    0x4870ffa0, 0x302221ef, 0xff9bf003, 0xf249486d, 0x30263184, 0xff95f003, 0x2100486a, 0xf0033028, 
+    0x4868ff90, 0x0100f244, 0xf003302c, 0x4865ff8a, 0x0100f243, 0xf003302e, 0x4c62ff84, 0x1110f241, 
+    0x46203430, 0xff7df003, 0xf2411ca5, 0x46282112, 0xff77f003, 0x21131d26, 0xf0034630, 0x1da7ff72, 
+    0x46382100, 0xff6df003, 0x0806f105, 0x4121f247, 0xf0034640, 0xf106ff66, 0x21000906, 0xf0034648, 
+    0xf107ff60, 0xf2410b06, 0x46510a00, 0xf0034658, 0xf108ff58, 0xf64a0006, 0xf0032100, 0x4849ff52, 
+    0x01fff244, 0xf003304e, 0x1fa0ff4c, 0xf0034651, 0x2100ff48, 0xf0031fa0, 0x2100ff44, 0xf0034620, 
+    0x2100ff40, 0xf0034628, 0x2100ff3c, 0xf0034630, 0x2100ff38, 0xf0034638, 0x2100ff34, 0xf0034640, 
+    0x2100ff30, 0xf0034648, 0x2100ff2c, 0xf0034658, 0x2100ff28, 0x0006f108, 0xff23f003, 0x21004831, 
+    0xf003304e, 0xf643ff1e, 0x4620412d, 0xff19f003, 0x1128f642, 0xf0034628, 0x2174ff14, 0xf0034630, 
+    0x2100ff10, 0xf0034640, 0x2100ff0c, 0xf0034648, 0x4824ff08, 0x0137f248, 0xf003304e, 0x1fa0ff02, 
+    0xf0034651, 0x2100fefe, 0xf0031fa0, 0x2100fefa, 0xf0034620, 0x2100fef6, 0xf0034628, 0x2100fef2, 
+    0xf0034630, 0x2100feee, 0xf0034640, 0x2100feea, 0xf0034648, 0x4813fee6, 0x304e2100, 0xfee1f003, 
+    0x46202105, 0xfeddf003, 0x5140f240, 0xf0034628, 0xf640fed8, 0x46306140, 0xfed3f003, 0x0141f640, 
+    0xf0034638, 0xf241fece, 0x46403144, 0xfec9f003, 0x0006f108, 0x011cf245, 0xfec3f003, 0xf1092140, 
+    0xe0010006, 0xd0039800, 0xfebbf003, 0x0006f10b, 0x113bf645, 0xfeb5f003, 0xf24048fc, 0xf0034100, 
+    0x21d0feb0, 0xe8bd1fa0, 0xf0035ff0, 0xe92dbeaa, 0x48f65ff0, 0x011af24a, 0xf0033826, 0x48f3fea2, 
+    0x3100f240, 0xf0033824, 0x48f0fe9c, 0x382221ef, 0xfe97f003, 0xf24948ed, 0x381e3184, 0xfe91f003, 
+    0x210048ea, 0xf003381c, 0x48e8fe8c, 0x0100f244, 0xf0033818, 0x48e5fe86, 0x0100f243, 0xf0033816, 
+    0x4ce2fe80, 0x1110f241, 0x46203c14, 0xfe79f003, 0xf2411ca5, 0x46282112, 0xfe73f003, 0x0904f104, 
+    0x46482113, 0xfe6df003, 0x0a06f104, 0x46502100, 0xfe67f003, 0x0b06f105, 0x4121f247, 0xf0034658, 
+    0xf109fe60, 0x21000806, 0xf0034640, 0xf108fe5a, 0xf2410702, 0x46310600, 0xf0034638, 0x1cb8fe52, 
+    0x2100f64a, 0xfe4df003, 0xf24448c8, 0x300a01ff, 0xfe47f003, 0x46311fa0, 0xfe43f003, 0x1fa02100, 
+    0xfe3ff003, 0x46202100, 0xfe3bf003, 0x46282100, 0xfe37f003, 0x46482100, 0xfe33f003, 0x46502100, 
+    0xfe2ff003, 0x46582100, 0xfe2bf003, 0x46402100, 0xfe27f003, 0x46382100, 0xfe23f003, 0x1cb82100, 
+    0xfe1ff003, 0x210048b1, 0xf003300a, 0xf643fe1a, 0x4620412d, 0xfe15f003, 0x1128f642, 0xf0034628, 
+    0x2174fe10, 0xf0034648, 0x48a8fe0c, 0x0107f248, 0xf003300a, 0x1fa0fe06, 0xf0034631, 0x2100fe02, 
+    0xf0031fa0, 0x2100fdfe, 0xf0034620, 0x2100fdfa, 0xf0034628, 0x2100fdf6, 0xf0034648, 0x2100fdf2, 
+    0xf0034658, 0x2100fdee, 0xf0034640, 0x2100fdea, 0xf0031cb8, 0x1dbefde6, 0x46302100, 0xfde1f003, 
+    0x21004892, 0xf003300a, 0x2103fddc, 0xf0034620, 0xf240fdd8, 0x46285140, 0xfdd3f003, 0x6140f640, 
+    0xf0034648, 0xf640fdce, 0x46500141, 0xfdc9f003, 0x3144f241, 0xf0034658, 0x1f30fdc4, 0x011cf245, 
+    0xfdbff003, 0x1eb02140, 0xfdbbf003, 0x113bf645, 0xf0034630, 0x1cb0fdb6, 0x4100f240, 0xfdb1f003, 
+    0x1fa021d0, 0x5ff0e8bd, 0xbdabf003, 0x4ff0e92d, 0xb0c34877, 0xc84eaf15, 0x004ee887, 0xaf19c84e, 
+    0x004ee887, 0xaf1dc84e, 0x004ee887, 0xaf21c84e, 0x004ee887, 0xaf25c84e, 0x004ee887, 0xaf29c84e, 
+    0x004ee887, 0xaf2dc84e, 0x004ee887, 0xae31c80f, 0x000fe886, 0x21004867, 0xf0007800, 0x20020601, 
+    0xf922f7e7, 0xf7e62001, 0x4863f99f, 0xf0032100, 0x4862fd78, 0xfd72f003, 0x2101485c, 0xf0033844, 
+    0x485ffd70, 0x0000f990, 0xd0642801, 0xf10d2802, 0xf10d0854, 0xaf1d0a64, 0x0984f10d, 0xf7ffd07e, 
+    0x46d3fcb0, 0x200046ca, 0xf10da903, 0xab0b091c, 0x0c3cf10d, 0x2020f858, 0x2020f841, 0xe020f85b, 
+    0xe020f849, 0x2020f857, 0x2020f843, 0x2020f85a, 0x2020f84c, 0xb2c01c40, 0xd9eb2803, 0x23004843, 
+    0xf240220a, 0x38344100, 0xfd55f003, 0x23014f3f, 0x3f16220c, 0x46380319, 0xfd4df003, 0x46382301, 
+    0x0359220d, 0xfd47f003, 0xf647483e, 0xf00371ff, 0xf8dffd28, 0xf04f80f4, 0xf8df0901, 0x4f3bb0ec, 
+    0x0816f1a8, 0x46402101, 0xfd1bf003, 0xf0034658, 0x07c0fd15, 0x2100d06c, 0xf0034640, 0x2e00fd12, 
+    0xf7d8d0f0, 0xf000fe49, 0xfa09010f, 0x7839f001, 0xf94af7e0, 0xf7ffe7e6, 0x2000fe5a, 0x0e94f10d, 
+    0x08a4f10d, 0x0ab4f10d, 0x0bc4f10d, 0x090cf10d, 0xaf0bab07, 0x0c3cf10d, 0x2020f85e, 0x2020f849, 
+    0x1020f858, 0x1020f843, 0x1020f85a, 0x1020f847, 0x1020f85b, 0x1020f84c, 0xe0001c40, 0xb2c0e003, 
+    0xd9e92803, 0xf7ffe79a, 0x46c3fd2e, 0x200046d0, 0xf10d46ca, 0xab07090c, 0x0c2cf10d, 0x0e3cf10d, 
+    0x2020f85b, 0x2020f849, 0x1020f858, 0x1020f843, 0x1020f857, 0x1020f84c, 0x1020f85a, 0x1020f84e, 
+    0xb2c01c40, 0xd9eb2803, 0xe011e778, 0xd0039844, 0x0002e19c, 0x00032228, 0xd003900c, 0xd03c804a, 
+    0x000323de, 0xd03c8310, 0xd0034024, 0x0003227f, 0xb3dcf8df, 0x48f62e00, 0x0200f04f, 0x0b18f1ab, 
+    0x0101f04f, 0xf003d07e, 0xea29fcc4, 0x46580100, 0xfc97f003, 0x48ef2208, 0x01512301, 0xfcabf003, 
+    0x230148ec, 0x461a2102, 0xf0031d00, 0x2100fca4, 0xf0034640, 0x2301fc86, 0x220048e7, 0xf0034619, 
+    0x2300fc9a, 0x210148e4, 0xf003461a, 0x2301fc94, 0x220048e2, 0xf0034619, 0x2301fc8e, 0x210248df, 
+    0xf003461a, 0x48defc88, 0xfc68f003, 0xf2404edd, 0x80301140, 0xf00348da, 0xf04ffc64, 0xf8cd0800, 
+    0x22028000, 0x46434640, 0xf7f54641, 0x48d6fa09, 0xfc54f003, 0x48d58070, 0xfc50f003, 0x48d480b0, 
+    0xfc4cf003, 0x48d280f0, 0xf0031d80, 0x8130fc47, 0x1c8048cf, 0xfc42f003, 0x48ce8170, 0xfc3ef003, 
+    0x48cc81b0, 0xf0031d80, 0x81f0fc39, 0x1c8048c9, 0xfc34f003, 0x48c88230, 0xfc30f003, 0x48c68270, 
+    0xf0031d80, 0x82b0fc2b, 0x1c8048c3, 0xfc26f003, 0x48c282f0, 0xfc22f003, 0x48c08330, 0xf0031d80, 
+    0xe000fc1d, 0xf8dfe0c6, 0x8370b2f4, 0x0b02f10b, 0xf0034658, 0x83b0fc13, 0xf00348b9, 0x83f0fc0f, 
+    0x48b12301, 0x21042202, 0xfc25f003, 0x230148af, 0x21042202, 0xfc1ff003, 0x48ad2301, 0x025e2209, 
+    0xf0034631, 0x48aafc18, 0x22002301, 0x1d804619, 0xfc11f003, 0x230048a6, 0x01b1220f, 0xf0031c80, 
+    0x2301fc0a, 0x220f48a2, 0xf00303d9, 0x48a1fc04, 0x22092301, 0xf0034631, 0x489efbfe, 0x22002301, 
+    0x1d804619, 0xfbf7f003, 0x2300489a, 0x01b1220f, 0xf0031c80, 0x2301fbf0, 0x220f4896, 0xf00303d9, 
+    0x4895fbea, 0x22092301, 0xf0034631, 0x4892fbe4, 0x22002301, 0x1d804619, 0xfbddf003, 0x2300488e, 
+    0x01b1220f, 0xf0031c80, 0x2301fbd6, 0x220f488a, 0xf00303d9, 0x4889fbd0, 0x22092301, 0xf0034631, 
+    0x2301fbca, 0x46192200, 0x0004f10b, 0xfbc3f003, 0x46582300, 0x01b1220f, 0xfbbdf003, 0x487f2301, 
+    0x03d9220f, 0xfbb7f003, 0x0b80f44f, 0x46587839, 0xffdaf7df, 0x48702301, 0x46192200, 0xfbabf003, 
+    0x486d2300, 0x461a2101, 0xfba5f003, 0x46587839, 0xffcaf7df, 0x23004e73, 0x21082203, 0xf0034630, 
+    0x7839fb9a, 0xf7df4658, 0x2301ffbf, 0x22034630, 0xf0032108, 0x7839fb90, 0xf7df4658, 0x486affb5, 
+    0xfb6cf003, 0x28e4b2c0, 0x2003d018, 0x23029000, 0x21002201, 0xf7e84865, 0x2000f939, 0x0801f04f, 
+    0xf360ae41, 0xf360040f, 0xf360050f, 0xf360441f, 0xe013451f, 0xfb7df003, 0xe6b84601, 0xf8cd2301, 
+    0x22028000, 0xe7e52103, 0x2801b2a0, 0x0c20d106, 0xb2a8d004, 0xd1012801, 0xd17d0c28, 0xf8df4854, 
+    0xf10aa11c, 0x78010a10, 0x0000f249, 0x3041ea40, 0x4650b281, 0xfb35f003, 0xf44f4f4e, 0x78392000, 
+    0xff72f7df, 0xe0074650, 0x7801484a, 0x2000f44f, 0xff6af7df, 0x30104839, 0xfb20f003, 0xd4f30500, 
+    0x30124836, 0xfb1af003, 0xf10d4940, 0x0b030be4, 0xf991468a, 0xf82b7003, 0xf9913017, 0xf3c07002, 
+    0xf82b2303, 0xf9913017, 0xf3c07001, 0xf0001303, 0xf82b000f, 0xf9913017, 0x27003000, 0x0013f82b, 
+    0x30144826, 0x0047eb00, 0xfaf8f003, 0x0203f1c7, 0x1c7fa93d, 0x2002f91a, 0x2f03b2ff, 0x0012f821, 
+    0xf1b8d9ee, 0xd0060f01, 0x0f02f1b8, 0x0420d054, 0xd0720c00, 0xf99ae0aa, 0xaf132003, 0x0012f83b, 
+    0x0012f827, 0x1002f99a, 0x0011f83b, 0x0011f827, 0x0001f99a, 0xc010f83b, 0xc010f827, 0xc000f99a, 
+    0x301cf83b, 0x301cf827, 0xf3632300, 0xf363040f, 0xf363050f, 0xe000441f, 0xf826e0d9, 0xf826301c, 
+    0xf8263010, 0xf3633011, 0xf826451f, 0xe0c63012, 0xd0034022, 0xd003e810, 0xd03c8300, 0xd0039800, 
+    0xd28fffc0, 0x00033000, 0xd003c810, 0xd003d810, 0xd003c286, 0xd003ca86, 0xd003d286, 0xd003da86, 
+    0xd28e0040, 0xd0039000, 0xd03c8012, 0x000323b4, 0x000323dc, 0x0003227f, 0x0000f99a, 0x4653aa13, 
+    0xf8324659, 0xf83bc010, 0x45bc7010, 0xf826d104, 0xf3697010, 0xe003040f, 0x0c04f10d, 0x7010f82c, 
+    0x0001f993, 0x7010f832, 0xc010f831, 0xd1054567, 0x441ff369, 0xc010f826, 0xe021e003, 0xf827af01, 
+    0xf993c010, 0xf8320002, 0xf8317010, 0x4567c010, 0xf826d104, 0xf369c010, 0xe002050f, 0xf827af01, 
+    0xf99ac010, 0xf8320003, 0xf83b2010, 0x428a1010, 0xf369d102, 0xe060451f, 0xf822aa01, 0xe05e1010, 
+    0x0000f99a, 0xf83baa01, 0xf8321010, 0x42912010, 0xaa13d004, 0x2010f832, 0xd1044291, 0x1010f826, 
+    0x040ff369, 0x2100e002, 0x1010f826, 0xd1150c20, 0x0001f99a, 0xf83baa01, 0xf8321010, 0x42912010, 
+    0xaa13d004, 0x2010f832, 0xd1044291, 0x441ff369, 0x1010f826, 0x2100e002, 0x1010f826, 0x0c000428, 
+    0xf99ad115, 0xaa010002, 0x1010f83b, 0x2010f832, 0xd0044291, 0xf832aa13, 0x42912010, 0xf826d104, 
+    0xf3691010, 0xe002050f, 0xf8262100, 0x0c281010, 0xf99ad115, 0xaa010003, 0x1010f83b, 0x2010f832, 
+    0xd0044291, 0xf832aa13, 0x42912010, 0xf369d104, 0xf826451f, 0xe0021010, 0xf8262100, 0xf1081010, 
+    0xf0000001, 0xf1b808ff, 0xf67f0f03, 0x2000ae9d, 0x46d84659, 0x2010f836, 0x2010f821, 0xb2c01c40, 
+    0xd9f62803, 0xf8ad2000, 0xf8ad00dc, 0x250100e0, 0x00d4f8ad, 0x0bd4f10d, 0x00d8f8ad, 0x00def8ad, 
+    0x00e2f8ad, 0x00d6f8ad, 0x00daf8ad, 0x70fff64f, 0x00ecf8ad, 0x00f0f8ad, 0x00eef8ad, 0x00f2f8ad, 
+    0x4eff48fe, 0xf2497801, 0xea400000, 0xb2813041, 0xf0034630, 0x4cfbf9b6, 0x2700f44f, 0x78214638, 
+    0xfdf2f7df, 0xf0034630, 0x46b1f9a9, 0xe006463e, 0x46307821, 0xfde8f7df, 0xf0034648, 0x0500f99f, 
+    0xf8dfd4f6, 0x240093bc, 0xf109af37, 0xae3d0904, 0x0044eb09, 0xf992f003, 0x0103f1c4, 0x1001f91a, 
+    0x0011f826, 0x3011f837, 0xf8274403, 0xf83b3011, 0x465bc011, 0xd9014560, 0x0011f823, 0x0cecf10d, 
+    0xe011f83c, 0xd2014570, 0x0011f82c, 0xb2e41c64, 0xd9dd2c03, 0xb2ed1c6d, 0xd9b12d04, 0xf8372000, 
+    0xf8331010, 0x1b094010, 0x4010f83c, 0xeb011b09, 0x084971d1, 0x1010f826, 0xb2c01c40, 0xd9ee2803, 
+    0x46c12400, 0x46d0af3f, 0x5004f918, 0x0015f839, 0xd0422802, 0xd0402803, 0xd03e2804, 0x0015f836, 
+    0xfeeaf005, 0xf851a90b, 0xf0051025, 0xa90ffef9, 0x1025f851, 0xfd62f005, 0xfea6f005, 0xb2e41c64, 
+    0xf8272c03, 0xd9df0015, 0x24004dbf, 0xf04f4ebf, 0xf8370864, 0x78281014, 0xfbb1b108, 0xeb06f1f8, 
+    0xf0030044, 0x1c64f92e, 0x2c03b2e4, 0xf8bdd9f1, 0xf8bd10e4, 0xf8bd00ea, 0xea4020e8, 0xf8bd3001, 
+    0x020910e6, 0x1102ea41, 0xb2814308, 0x1e8048af, 0xf917f003, 0xe8bdb043, 0xf8368ff0, 0xf0050015, 
+    0xa903feab, 0x1025f851, 0xfebaf005, 0xe7bfa907, 0x5ff0e92d, 0x8e804604, 0x8294f8df, 0x76ccf240, 
+    0x42b04da4, 0x71ccf2a0, 0x7799f240, 0x7998f240, 0xdc17d074, 0xf2a042b8, 0xd0377199, 0xb300dc0d, 
+    0xd12f4548, 0x22006a28, 0x0124f105, 0xfd2af7fe, 0xd0291d41, 0xd11a2801, 0x2925e028, 0x2926d07d, 
+    0xe014d120, 0xd012290d, 0x2901dc0c, 0x290cd00f, 0x4990d118, 0x6a282200, 0xf7fe3124, 0x1d40fce4, 
+    0xe004d06c, 0xd06a292a, 0xd10b292b, 0x4989e0b9, 0x32fff04f, 0x31246a28, 0xfd04f7fe, 0xd1d71d01, 
+    0x9034f8a4, 0x9ff0e8bd, 0xe7fb86a7, 0xf04f4b81, 0xf04f52c0, 0x33245000, 0x1000f9b3, 0xd02e2966, 
+    0xd05f2968, 0xd07b2969, 0xd1e02967, 0xf7d8469a, 0x4873fb16, 0x21012300, 0x3810461a, 0xf8bbf003, 
+    0x20004975, 0x22002301, 0x48747008, 0xf0218801, 0x80010110, 0x46194872, 0xf8adf003, 0xf7e82000, 
+    0x2107f92f, 0x1000f8aa, 0x2200496a, 0x0000f8d8, 0xf7fe3124, 0x1d01fc98, 0xe070d067, 0x469ae045, 
+    0xfaedf7d8, 0xb19cf8df, 0xf0034658, 0x1c40f877, 0x4658b281, 0xf875f003, 0xf7df2004, 0x4859fd75, 
+    0xf44f7801, 0xf7df2000, 0x2168fcaf, 0x1000f8aa, 0x22004958, 0x31246a28, 0xe008e002, 0xe047e042, 
+    0xfc71f7fe, 0xd1081d01, 0x70bef240, 0x4951e0c5, 0x6a282200, 0xf7fe3124, 0x1d40fc66, 0xf240d187, 
+    0xe0ba70bf, 0xf7d8469a, 0xf7fffaba, 0x2169fa9f, 0x1000f8aa, 0x22004947, 0x31246a28, 0xfc53f7fe, 
+    0xd1081d01, 0xe77d86a6, 0x4942e00a, 0x6a282200, 0xf7fe3124, 0x1d40fc48, 0xf240d187, 0xe09c70cd, 
+    0xf7d8469a, 0x2167fa9c, 0x1000f8aa, 0x22004939, 0x31246a28, 0xfc37f7fe, 0xf47f1d01, 0xf240af50, 
+    0xe08a70d8, 0x70d9f240, 0xf240e087, 0xe08470f6, 0x22004930, 0x0000f8d8, 0xf7fe3124, 0x1d40fc24, 
+    0xf7e7d079, 0x8829fdd6, 0xf003482f, 0x8be9f80a, 0xf003482e, 0x8869f806, 0xf003482d, 0x88a9f802, 
+    0xf002482c, 0x88e9fffe, 0xf002482b, 0x482afffa, 0x1d808929, 0xfff5f002, 0x89694827, 0xf0021c80, 
+    0x89a9fff0, 0xf0024825, 0x4824ffec, 0x1d8089e9, 0xffe7f002, 0x8a294821, 0xf0021c80, 0x8a69ffe2, 
+    0xf002481f, 0x481effde, 0x1d808aa9, 0xffd9f002, 0x8ae9481b, 0xf0021c80, 0x8b29ffd4, 0xf0024819, 
+    0x4818ffd0, 0x1d808b69, 0xffcbf002, 0x8ba94815, 0xf0021c80, 0x2300ffc6, 0xe026220b, 0x000323dc, 
+    0xd0039810, 0x0003227f, 0x000323dd, 0xd003512e, 0x00032564, 0x00033000, 0x0003229e, 0x0003227c, 
+    0xd28f20e0, 0xd0039ffe, 0xd28fffc0, 0xd28e0040, 0xd003c810, 0xd003d810, 0xd003c286, 0xd003ca86, 
+    0xd003d286, 0xd003da86, 0x480ce005, 0x0100f640, 0xffb1f002, 0xf240e6cb, 0x86a070f7, 0x2200e6d2, 
+    0xb5102101, 0x20f7f2af, 0xf9e8f7fe, 0x20022108, 0xfb46f7fe, 0x62084902, 0x0000bd10, 0xd03c800c, 
+    0x00033000, 0xb5104861, 0xff78f002, 0xd2082803, 0xb2c0495f, 0x0020f851, 0x46014780, 0x3816485b, 
+    0x485ae003, 0x1122f241, 0xe8bd3814, 0xf0024010, 0xe92dbf68, 0x4d5641f0, 0x8e804604, 0xb1201f2d, 
+    0xd00c288c, 0xd129288d, 0x4952e012, 0x32fff04f, 0xf7fe6828, 0x1d01fb97, 0x208cd106, 0x494de01d, 
+    0x68282200, 0xfb8ef7fe, 0xd0151d41, 0xd1ec2801, 0xf44f4e48, 0xf04f1700, 0x46384220, 0x1000f9b6, 
+    0xf9adf7d8, 0x286f8830, 0x2100d00a, 0xf04f4638, 0xf7d852d0, 0xe7d8f9a4, 0x86a0208d, 0x81f0e8bd, 
+    0x28016870, 0x4839d1d1, 0x38162102, 0xff29f002, 0xffa8f7ff, 0x2200e7c9, 0xb5102101, 0x008df2af, 
+    0xf97cf7fe, 0x2004210c, 0xfadaf7fe, 0x1f094930, 0xbd106008, 0x4c2db510, 0x3c1cb281, 0xf0024620, 
+    0x2100ff10, 0xf0024620, 0x1ca4ff0c, 0x71fff64f, 0xf0024620, 0x4620ff06, 0x4010e8bd, 0xf0022100, 
+    0x4822bf00, 0x38202101, 0xbefbf002, 0x2100481f, 0x3818b510, 0xfef5f002, 0x2104481c, 0x4010e8bd, 
+    0xf0023816, 0xb510beee, 0x48184604, 0xf0023812, 0x4816fee8, 0x38184621, 0xfee3f002, 0x23014813, 
+    0x46192200, 0x4010e8bd, 0xf0023824, 0x2100bef4, 0x52d0f04f, 0x1000f44f, 0xf7d8b510, 0x2004f940, 
+    0x2102bd10, 0x52d0f04f, 0xb5100508, 0xf937f7d8, 0x1d804806, 0xfec2f002, 0xfcbdf001, 0x4803b281, 
+    0xf0023814, 0x2004febe, 0x0000bd10, 0xd03d1030, 0x00033030, 0x00040524, 0x4cf9b570, 0x22002301, 
+    0x46204619, 0xfec7f002, 0x23014df6, 0x46192200, 0xf0024628, 0x2301fec0, 0x21024620, 0xf002461a, 
+    0x2301feba, 0x21024628, 0xf002461a, 0x2300feb4, 0x22024620, 0xf0022104, 0x4628feae, 0x4070e8bd, 
+    0x22022300, 0xf0022104, 0xb510bea6, 0xf44fb108, 0x4ce31080, 0x3c922301, 0x22054420, 0x21204604, 
+    0xfe99f002, 0x46202301, 0x21402206, 0xfe93f002, 0xe8bd2100, 0x20044010, 0xbab6f7df, 0xb108b510, 
+    0x1080f44f, 0x23014cd6, 0x44203c14, 0x46042204, 0xf0022110, 0x2303fe80, 0x22024620, 0xf002210c, 
+    0x2302fe7a, 0x22004620, 0x4010e8bd, 0xf0022103, 0xb510be72, 0xf44fb108, 0x4cc91080, 0x3c922301, 
+    0x22024420, 0x21044604, 0xfe65f002, 0x46202301, 0x461a2102, 0xfe5ff002, 0x46202301, 0x46192200, 
+    0xfe59f002, 0xe8bd2100, 0x20044010, 0xba7cf7df, 0x2800b5f8, 0xf44fd054, 0x20001480, 0x46029000, 
+    0x230148b7, 0x46193892, 0xf0024420, 0x48b6fe44, 0x21012300, 0x4420461a, 0xf0024605, 0x48b3fe3c, 
+    0x20047801, 0xfa60f7df, 0x46282301, 0x46192200, 0xfe31f002, 0x220048ac, 0x13f4f240, 0x31fff240, 
+    0x44201d80, 0xf0024606, 0x4fa9fe26, 0x31bcf64b, 0xf0024638, 0x4da7fe06, 0x9000200a, 0x462a2102, 
+    0xf7df4668, 0x2801fabb, 0x4620d007, 0xfcfaf001, 0xf0014620, 0x2800fdc2, 0x489fd0f0, 0x22042301, 
+    0x44202110, 0xfe07f002, 0x46302301, 0x03d9220f, 0xfe01f002, 0x0000f44f, 0x48989000, 0xe0084404, 
+    0xe7aa2400, 0x462a2103, 0xf7df4668, 0x2801fa97, 0x2207d006, 0x21804620, 0xfdfbf002, 0xd0f12800, 
+    0x31bdf64b, 0xf0024638, 0xbdf8fdcc, 0x4d88b570, 0x31b6f64b, 0xf0024628, 0x4e89fdc4, 0x21012200, 
+    0xf0024630, 0x4c87fde6, 0x2000b968, 0xff80f7ff, 0x28017820, 0xf7ffd101, 0x2301ff7b, 0x22004630, 
+    0xf0024619, 0xf64bfdc8, 0x462831b7, 0xfda9f002, 0xf7ff2000, 0x2000ff4e, 0xff30f7ff, 0xf7ff2000, 
+    0x7820ff14, 0xd10d2801, 0xff43f7ff, 0xf7ff2001, 0x2001ff25, 0xff09f7ff, 0x28017820, 0xe8bdd102, 
+    0xe6d94070, 0xe92dbd70, 0x460447f0, 0xf24f486e, 0x44200700, 0x23044639, 0x220c4605, 0xfd9bf002, 
+    0x46282308, 0x461a113e, 0xf0024631, 0x2308fd94, 0x22044628, 0xf00221f0, 0x4863fd8e, 0x220c2309, 
+    0x1c804639, 0x46054420, 0xfd85f002, 0x46312309, 0x46282208, 0xfd7ff002, 0x46282304, 0x461a21f0, 
+    0xfd79f002, 0x46282300, 0x461a210f, 0xfd73f002, 0xf6434855, 0x231979ff, 0x30d24649, 0x44202200, 
+    0xfd69f002, 0xf6414850, 0x23067aff, 0x30d44651, 0x44202200, 0xfd5ff002, 0xf64f484b, 0x23017600, 
+    0x30d64631, 0x22084420, 0xf0024605, 0x2300fd54, 0x21ff4628, 0xf002461a, 0x4843fd4e, 0x213f2300, 
+    0x30d8461a, 0xf0024420, 0x483ffd46, 0x18fff240, 0x46412305, 0x22003062, 0xf0024420, 0x483afd3c, 
+    0x2200237d, 0x30c84649, 0xf0024420, 0x4836fd34, 0x2200231f, 0x30ce4651, 0x46054420, 0xfd2bf002, 
+    0x23014831, 0x46312208, 0x442030ca, 0xf0024606, 0x2300fd22, 0x21ff4630, 0xf002461a, 0x482afd1c, 
+    0x0600f24e, 0x46312300, 0x442030d0, 0x4607220d, 0xfd11f002, 0x46312300, 0x4628220d, 0xfd0bf002, 
+    0x23324821, 0x46492200, 0x442030cc, 0xfd03f002, 0x46512331, 0x46382200, 0xfcfdf002, 0x231f481a, 
+    0x46412200, 0x44203060, 0x47f0e8bd, 0xbcf3f002, 0x4ff8e92d, 0x480e4604, 0xf04f460f, 0x38800800, 
+    0xfcccf002, 0xd0082c03, 0xd01f2c05, 0xd01d2c04, 0xd01e2c02, 0xd01c2c01, 0x0480e02c, 0xe04cd42a, 
+    0xd2054096, 0xd2154096, 0xd203a1e2, 0x0003227f, 0xd03c80b8, 0xd003517e, 0xd203a404, 0xd203a01a, 
+    0xd0034010, 0x00032362, 0xd2052402, 0xd4080480, 0x0481e00e, 0x780048f7, 0x2801d506, 0x2c02d101, 
+    0xf04fd008, 0xe0050802, 0xd1012801, 0xd0242c02, 0x0803f04f, 0x48f04af0, 0x0100f248, 0x443a32de, 
+    0x4aed9200, 0x3a08183c, 0xf1b818bd, 0xd0170f00, 0xeb071e80, 0x1f920b00, 0xeb071e80, 0x1c900a00, 
+    0xf1b818be, 0xeb070f01, 0xd0260900, 0x0f02f1b8, 0xf1b8d07d, 0xd17b0f03, 0xf04fe0ad, 0xe7d90801, 
+    0x46202300, 0xf002220f, 0x9800fc86, 0x2200230a, 0xf002210f, 0x2300fc80, 0x3100f240, 0x46282208, 
+    0xfc79f002, 0x46282301, 0x0399220e, 0xfc73f002, 0x4628220c, 0x02912302, 0x2301e067, 0x220f4620, 
+    0xfc69f002, 0xf64323ce, 0x220471f0, 0xf0024620, 0x2301fc62, 0x22004620, 0xf0022103, 0x2100fc5c, 
+    0xf0024658, 0xf244fc3e, 0x46200800, 0x46412300, 0xf002220e, 0x2300fc50, 0x22034620, 0xf0022108, 
+    0x2300fc4a, 0x22024620, 0xf0022104, 0x2301fc44, 0x220e4641, 0xf0024628, 0x220cfc3e, 0x23024628, 
+    0xf0020291, 0x2300fc38, 0x3100f240, 0x46282208, 0xfc31f002, 0x46302300, 0x21402206, 0xfc2bf002, 
+    0x46302300, 0x21802207, 0xfc25f002, 0x46502300, 0x21202205, 0xfc1ff002, 0x46302303, 0x21302204, 
+    0xfc19f002, 0x46302301, 0x21082203, 0xe00fe001, 0xf002e095, 0x2306fc10, 0x22014648, 0xf002211e, 
+    0x2301fc0a, 0x22004648, 0xf0024619, 0xe086fc04, 0x46202300, 0xf002220f, 0x9800fbfe, 0x2200230d, 
+    0xf002210f, 0x2301fbf8, 0x220e4628, 0xf0020399, 0x2300fbf2, 0x3100f240, 0x46282208, 0xfbebf002, 
+    0x4628220c, 0x02912302, 0xfbe5f002, 0x46302300, 0x21402206, 0x2301e05e, 0x220f4620, 0xfbdbf002, 
+    0xf64323fa, 0x220471f0, 0xf0024620, 0x2300fbd4, 0x21034620, 0xf002461a, 0x2100fbce, 0xf0024658, 
+    0xf244fbb0, 0x46200800, 0x46412300, 0xf002220e, 0x2300fbc2, 0x22034620, 0xf0022108, 0x2300fbbc, 
+    0x22024620, 0xf0022104, 0x2301fbb6, 0x220e4641, 0xf0024628, 0x220cfbb0, 0x23024628, 0xf0020291, 
+    0x2300fbaa, 0x3100f240, 0x46282208, 0xfba3f002, 0x46302300, 0x21402206, 0xfb9df002, 0x46302300, 
+    0x21802207, 0xfb97f002, 0x46502300, 0x21202205, 0xfb91f002, 0x46302300, 0x21302204, 0xfb8bf002, 
+    0x46302300, 0x21082203, 0xfb85f002, 0x46482301, 0x46192200, 0xfb7ff002, 0xf7ff4638, 0x4857fdd4, 
+    0xf242220d, 0xf0020100, 0x0001fb84, 0xf24e4854, 0x44380400, 0x2303d001, 0x2306e000, 0x220d4621, 
+    0xfb69f002, 0x2301484c, 0x461a2102, 0x3810b001, 0xe8bd4438, 0xf0024ff0, 0xb570bb5e, 0xb19a460d, 
+    0x1480f44f, 0x48444603, 0x21012200, 0x44203056, 0xfb51f002, 0x22004840, 0x462b2101, 0x44203036, 
+    0x4070e8bd, 0xbb47f002, 0xe7eb2400, 0x4ff3e92d, 0x4605b083, 0x28009804, 0xf44fd004, 0xd1041480, 
+    0xe0034838, 0x0400f04f, 0x4837e7f9, 0x46804621, 0xf7ff4628, 0x4835fe3d, 0x2d052100, 0xd0568001, 
+    0xd0542d04, 0x46232126, 0xf021b289, 0x80010101, 0x20502202, 0xf9d6f001, 0x46232201, 0x4611205f, 
+    0xf9d0f001, 0x23004824, 0x386e2201, 0x46824420, 0x46562102, 0xfb0ff002, 0x2301481f, 0x3078220d, 
+    0x44200359, 0xfb07f002, 0x46302300, 0x21022201, 0xfb01f002, 0x23004818, 0x461a2101, 0x44203854, 
+    0xf0024606, 0x481afaf8, 0x21012300, 0x4420461a, 0xf0024683, 0x4816faf0, 0x22012300, 0x44203848, 
+    0x46072102, 0xfae7f002, 0x46382300, 0x461a2101, 0xfae1f002, 0x46302301, 0x46192200, 0xfadbf002, 
+    0xf8df4804, 0x78009030, 0xd0152801, 0x2138e018, 0x0000e7a9, 0x00032305, 0xd203a170, 0xd03c8038, 
+    0xd2052200, 0x0003fdfc, 0x0003fe1f, 0x0003303c, 0xd20588ae, 0xd2058616, 0xd0222d03, 0xd0202d02, 
+    0x220848ff, 0x01512300, 0xf0024420, 0xeb04fab4, 0xf6400009, 0x23000100, 0x220b4606, 0xfaabf002, 
+    0x46302301, 0x21402206, 0xfaa5f002, 0xd07d2d03, 0xd07c2d05, 0xd07b2d04, 0xd07a2d02, 0xd0792d01, 
+    0x220ce0af, 0x0009eb04, 0x46062302, 0xf0020291, 0x48ecfa92, 0x01eef241, 0xf0024420, 0x48e9fa72, 
+    0x0100f24a, 0x44201c80, 0xfa6bf002, 0xf64048e5, 0x1d0031b8, 0xf0024420, 0x48e2fa64, 0x3100f641, 
+    0x44201d80, 0xfa5df002, 0xf24848de, 0x30082135, 0xf0024420, 0x48dbfa56, 0x2135f248, 0x4420300a, 
+    0xfa4ff002, 0xf24848d7, 0x300e2135, 0xf0024420, 0x48d4fa48, 0x3012210f, 0xf0024420, 0x48d0fa42, 
+    0x2205231c, 0x31e0f240, 0x4420300a, 0xf0029000, 0x2d03fa52, 0x2d02d002, 0xe01fd011, 0x4260f04f, 
+    0x1750210c, 0xfc9bf7d7, 0x230148c5, 0x300c2203, 0x44202108, 0xf0029001, 0x2300fa3e, 0x48c0e009, 
+    0x22032300, 0x2108300c, 0x90014420, 0xfa33f002, 0x98012301, 0x21202205, 0xfa2df002, 0x23019800, 
+    0x211f2200, 0xfa27f002, 0xe0042301, 0xe015e014, 0xe027e01e, 0x48b2e028, 0x01512208, 0xf0024420, 
+    0x2300fa1a, 0x0100f640, 0x4630220b, 0xfa13f002, 0x22062300, 0xe0212140, 0xe016230f, 0xf04f48aa, 
+    0x78014260, 0x31201750, 0xfc59f7d7, 0xe00c2310, 0xf04f48a6, 0x78014260, 0x31101750, 0xfc4ff7d7, 
+    0xe0022303, 0xe0002302, 0x46302301, 0x213f2200, 0xf9f1f002, 0xf2402300, 0x220a4100, 0xf0024630, 
+    0x2301f9ea, 0x21802207, 0x0009eb04, 0xf9e3f002, 0x23014897, 0x461a2102, 0xf0024420, 0xf898f9dc, 
+    0xf8981021, 0x9a040022, 0xfe77f7ff, 0x23004891, 0x21022201, 0xf0024420, 0x488ff9ce, 0x4e8f2100, 
+    0x78318001, 0xd1032901, 0xd0352d03, 0xd0332d02, 0x80012104, 0x46232202, 0x0250b289, 0xf872f001, 
+    0xb1087830, 0xd0042d03, 0x46299a04, 0xf0014640, 0x2301fa4a, 0x21024638, 0xf002461a, 0x2301f9ac, 
+    0x22004638, 0xf0024619, 0x2301f9a6, 0x21024650, 0xf002461a, 0x2301f9a0, 0x22004658, 0xf0024619, 
+    0x486ff99a, 0x22022301, 0xb0052104, 0x44203860, 0x4ff0e8bd, 0xb98ff002, 0x1103f240, 0xb570e7c9, 
+    0x46034605, 0x460c486e, 0xf244220e, 0x44200100, 0xf0024604, 0x220df980, 0xf242462b, 0x46200100, 
+    0xf979f002, 0x4620462b, 0x4070e8bd, 0xf241220c, 0xf0020100, 0xe92db970, 0x46905fff, 0xb1d14607, 
+    0x1680f44f, 0x2301485e, 0x22054430, 0x21204604, 0xf961f002, 0xf2404d5a, 0xf64071df, 0x1cad0a00, 
+    0xd00a2f03, 0xd00b2f05, 0xd0122f04, 0xd0392f02, 0xd0392f01, 0x2600e041, 0xf240e7e4, 0xe0344310, 
+    0xf2402200, 0x46202308, 0xf945f002, 0x46312001, 0x2200e031, 0x1304f240, 0x46204689, 0xf93bf002, 
+    0x46312001, 0xffabf7ff, 0x0f03f1b8, 0x2382d125, 0x22004649, 0xf0024620, 0x1970f92e, 0x2900f240, 
+    0x46492301, 0x46802209, 0xf925f002, 0x7801483d, 0xf7de4650, 0x2300fd49, 0x22094649, 0xf0024640, 
+    0xe00af91a, 0xe0002382, 0x46202341, 0xf0022200, 0x2000f912, 0xf7ff4631, 0x9803ff82, 0xd07d2801, 
+    0x46512300, 0x4620220b, 0xf905f002, 0x23011970, 0x22074604, 0xf0022180, 0x2300f8fe, 0x22064620, 
+    0xf0022140, 0x2301f8f8, 0x21202205, 0xf0021970, 0x4823f8f2, 0x22002301, 0x30104619, 0x46834430, 
+    0xf8e9f002, 0x2301481e, 0x46192200, 0x4430300a, 0xf0024682, 0x481af8e0, 0x22002301, 0x300e4619, 
+    0x46814430, 0xf8d7f002, 0x23014815, 0x46192200, 0x44303008, 0xf0024605, 0x4811f8ce, 0x22002301, 
+    0x300c4619, 0x46044430, 0xf8c5f002, 0x46582301, 0x21082203, 0xf8bff002, 0xf6412f03, 0xe0136800, 
+    0xd2058900, 0xd20524a6, 0x00032307, 0x00032306, 0xd203a1c6, 0xd202012c, 0x0003303e, 0x00032305, 
+    0xd2054080, 0x0003227f, 0x2f05d039, 0x2f04d03a, 0x4ef7d038, 0xd07d2f02, 0xd17c2f01, 0x0400f64f, 
+    0x23064650, 0x220b4621, 0xf895f002, 0x46212306, 0x4648220b, 0xf88ff002, 0xe0002300, 0x2205e010, 
+    0x21204650, 0xf887f002, 0x46482300, 0x21202205, 0xf881f002, 0x28017830, 0x2800d074, 0xe0d0d073, 
+    0x46512301, 0x4620220b, 0xf875f002, 0x23001970, 0x22074604, 0xf0022180, 0x2301f86e, 0x9803e76e, 
+    0xd02f2801, 0x46412302, 0x46282209, 0xf863f002, 0x46412302, 0x46202209, 0xf85df002, 0x16e0f240, 
+    0x23034628, 0x22054631, 0xf855f002, 0x46312303, 0x46202205, 0xf84ff002, 0x46282301, 0x21102204, 
+    0xf849f002, 0x46202301, 0x21102204, 0xf843f002, 0x46282303, 0x210e2201, 0xf83df002, 0x22012303, 
+    0xe06d210e, 0xf24e2304, 0x220d0100, 0xf0024658, 0x2301f832, 0x22064658, 0xf0022140, 0x2301f82c, 
+    0x22034658, 0xf0022108, 0x2301f826, 0x22024658, 0xe0012104, 0xe091e018, 0xf81df002, 0x46582300, 
+    0x461a2101, 0xf817f002, 0x230348b2, 0x44302200, 0x4604211f, 0xf80ff002, 0xf240230d, 0x220531e0, 
+    0xe0764620, 0xe050e049, 0x46412303, 0x46282209, 0xf801f002, 0x46412303, 0x46202209, 0xfffbf001, 
+    0x46282300, 0x21102204, 0xfff5f001, 0x46202300, 0x21102204, 0xffeff001, 0x28017830, 0xb140d001, 
+    0x2302e013, 0x22014628, 0xf001210e, 0x2304ffe4, 0x2300e006, 0x22014628, 0xf001210e, 0x2302ffdc, 
+    0x22014620, 0xf001210e, 0xf240ffd6, 0x462816e0, 0x46312303, 0xf0012205, 0x2303ffce, 0x22054631, 
+    0xf0014620, 0x2300ffc8, 0x21014628, 0xf001461a, 0x2300ffc2, 0x461a2101, 0x2304e7b2, 0x22014650, 
+    0xf001211e, 0x2304ffb8, 0x2302e006, 0x22014650, 0xf001211e, 0x2302ffb0, 0x22014648, 0xf001211e, 
+    0x2306ffaa, 0x74c0f240, 0x4621461a, 0xf0014650, 0x2306ffa2, 0x461a4621, 0xf0014648, 0x2300ff9c, 
+    0x21014650, 0xf001461a, 0x2300ff96, 0x21014648, 0xb004461a, 0x5ff0e8bd, 0xbf8df001, 0x9fffe8bd, 
+    0xf44fb570, 0xb3e01580, 0x2001462c, 0xf0004621, 0x4869ff88, 0x21012300, 0x4420461a, 0xf0014606, 
+    0x2301ff7a, 0x22004630, 0xf0014619, 0x4862ff74, 0x220f2301, 0x03d91d80, 0xf0014420, 0x2000ff6c, 
+    0xf0004621, 0x2100ff6e, 0xf7de4628, 0x2100fb8d, 0x2080f44f, 0xfb88f7de, 0x23014858, 0x46192200, 
+    0xf0014420, 0x4853ff58, 0x22042300, 0x4420388e, 0x46042110, 0xff4ff001, 0x46202301, 0x21102204, 
+    0xe003e000, 0x4070e8bd, 0xbf45f001, 0xe7bc2400, 0xb108b430, 0x1080f44f, 0x23004c46, 0x21082203, 
+    0x44203c8e, 0xf001bc30, 0x0002bf36, 0xb5704844, 0x0404f1a0, 0x0506f1a0, 0x2a01d00a, 0x2a02d00f, 
+    0x2901d123, 0x2104d01c, 0xff0bf001, 0xe00c2102, 0xd0152901, 0xf0012108, 0x2104ff04, 0x2901e005, 
+    0x210cd005, 0xfefdf001, 0x46282106, 0x2108e004, 0xfef7f001, 0x46202110, 0x4070e8bd, 0xbef1f001, 
+    0xf0012104, 0x2100feee, 0xbd70e7f5, 0x4d2cb570, 0x46042101, 0x46281fad, 0xfee3f001, 0x21011dae, 
+    0xf0014630, 0xb15cfede, 0xd10f2c01, 0x46282103, 0xfed7f001, 0x46302101, 0x4070e8bd, 0xbed1f001, 
+    0x46282103, 0xfecdf001, 0xe7f42105, 0xe92dbd70, 0x460441f0, 0xf44fb329, 0x48161680, 0x0800f244, 
+    0x2c043812, 0x2c05d01f, 0x2300d01d, 0x220e4641, 0xf0014430, 0x4812fed0, 0x220d2301, 0x44303808, 
+    0x46050359, 0xfec7f001, 0xf2412c01, 0xd00c0100, 0xd00a2c02, 0xd0152c03, 0xd0132c05, 0xd0112c04, 
+    0x2600e015, 0x2301e7d9, 0x2300e7e0, 0x0000e00b, 0x00032340, 0xd2054092, 0xd203a1e2, 0xd2052200, 
+    0xd2054188, 0x46282301, 0xf001220c, 0x2300fea4, 0x22034628, 0xf0012108, 0x2301fe9e, 0x22024628, 
+    0xf0012104, 0x2301fe98, 0x22004628, 0xf0014619, 0x48c6fe92, 0x22052301, 0x21204430, 0xf0014607, 
+    0x2301fe8a, 0x22044638, 0xf0012110, 0x2c01fe84, 0x2c02d001, 0x48bed112, 0x28016800, 0x48bdd108, 
+    0x28017800, 0x2c02d104, 0x48bbd102, 0xb1707800, 0x463248ba, 0x78004621, 0xff37f7ff, 0x230148b8, 
+    0x44302203, 0x41f0e8bd, 0xf0012108, 0x2300be64, 0x6100f640, 0x46282209, 0xfe5df001, 0x46282208, 
+    0x01512301, 0xfe57f001, 0xf7ff2001, 0x48adff4f, 0x4641220e, 0xfe5df001, 0xd1df2801, 0xfbd8f7e7, 
+    0xff44f7ff, 0xe92de7da, 0x2a005ff0, 0x4680460e, 0xf44fd066, 0x489d1580, 0x0400f248, 0x0a00f241, 
+    0xf2401d00, 0xf1b81b00, 0xf04f0f00, 0xf04f0300, 0xd057020f, 0x46a14428, 0x46044621, 0xfe2bf001, 
+    0x23004897, 0x307e2205, 0x21204428, 0xf0014607, 0x2301fe22, 0x220c4651, 0xf0014620, 0xb2b3fe1c, 
+    0x6100f640, 0x46202209, 0xfe15f001, 0x46592301, 0x46202208, 0xfe0ff001, 0x46202301, 0x46192200, 
+    0xfe09f001, 0x46492301, 0x4620220f, 0xfe03f001, 0x46382301, 0x21202205, 0xfdfdf001, 0x2301487b, 
+    0x1d802209, 0x02594428, 0xf0014604, 0x2300fdf4, 0x22084659, 0xf0014620, 0x2300fdee, 0x22034620, 
+    0xf0012108, 0x4878fde8, 0x28008800, 0x4f70d07e, 0x91c0f8df, 0xa1c0f8df, 0x28016838, 0xe027d01f, 
+    0xe7982500, 0x46214428, 0xf0014604, 0x2301fdd4, 0x220c4651, 0xf0014620, 0xb2b3fdce, 0x6100f640, 
+    0x46202209, 0xfdc7f001, 0x46592301, 0x46202208, 0xfdc1f001, 0x46202301, 0x46192200, 0xf899e7bc, 
+    0x28010000, 0x2e02d104, 0xf89ad102, 0xb3a00000, 0x46202300, 0x21082203, 0xfdadf001, 0x4620230b, 
+    0x21f02204, 0xfda7f001, 0x23004850, 0xf6402209, 0x1f806100, 0x46054428, 0xfd9df001, 0x46592301, 
+    0x46282208, 0xfd97f001, 0xf2402100, 0xf7de4000, 0x2300f9bb, 0x22024620, 0xf0012104, 0x2301fd8c, 
+    0x22024620, 0xf0012104, 0x2100fd86, 0xf7de2004, 0x6838f9ab, 0xd0092801, 0xe7ffe011, 0x46202301, 
+    0x21082203, 0xfd77f001, 0xe7c8230e, 0x0000f899, 0xd1042801, 0xd1022e02, 0x0000f89a, 0x2300b148, 
+    0x22084659, 0xe8bd4628, 0xe0005ff0, 0xf001e020, 0x4c2ebd62, 0x1da61f24, 0x0f00f1b8, 0x2300d010, 
+    0x22084659, 0xf0014628, 0x2300fd56, 0x21014620, 0xf001461a, 0x2300fd50, 0x22004630, 0xe7e22101, 
+    0x46202301, 0x46192200, 0xfd45f001, 0xe7f32301, 0x46202300, 0x21042202, 0xfd3df001, 0x46202300, 
+    0x21022201, 0x4821e7cf, 0x22002303, 0xb5102107, 0xfd31f001, 0x2301481d, 0x21042202, 0xf0011f80, 
+    0x481bfd2a, 0x22002306, 0xf0012107, 0x4818fd24, 0x21022301, 0x3012461a, 0xfd1df001, 0x23004814, 
+    0x461a2101, 0x4010e8bd, 0xf0013808, 0xb430bd14, 0xf44fb151, 0x46031480, 0x22044804, 0x1f802110, 
+    0xbc304420, 0xbd07f001, 0xe7f42400, 0xd2054186, 0x00032374, 0x0003237c, 0x00032279, 0x00032340, 
+    0xd2054004, 0xd0039026, 0x0003233e, 0xd03d1046, 0xd215412e, 0x47f0e92d, 0x23014cff, 0x46192200, 
+    0xf0014620, 0x2301fce8, 0x21024620, 0xf001461a, 0x48f9fce2, 0x5507f643, 0x76fff643, 0x2200462b, 
+    0x30424631, 0xfcd7f001, 0x1c7748f3, 0x463b2200, 0x46313044, 0xfccff001, 0xf64048ef, 0x22002888, 
+    0x30464643, 0xf0014631, 0x48ebfcc6, 0x09e2f241, 0x464b2200, 0x46313048, 0xfcbdf001, 0x220048e6, 
+    0x46314643, 0xf001304a, 0x48e3fcb6, 0x461a2300, 0x304c4631, 0xfcaff001, 0x220048df, 0x4631462b, 
+    0xf001304e, 0x48dcfca8, 0x463b2200, 0x30504631, 0xfca1f001, 0x220048d8, 0x4631462b, 0xf0013052, 
+    0x48d5fc9a, 0x463b2200, 0x30544631, 0xfc93f001, 0x220048d1, 0x46314643, 0xf0013056, 0x48cefc8c, 
+    0x464b2200, 0x30584631, 0xfc85f001, 0x220048ca, 0x46314643, 0xf001305a, 0x48c7fc7e, 0x461a2300, 
+    0x305c4631, 0xfc77f001, 0x220048c3, 0x4631462b, 0xf001305e, 0x48c0fc70, 0x463b2200, 0x30604631, 
+    0xfc69f001, 0x220048bc, 0x4631462b, 0xf0013062, 0x48b9fc62, 0x463b2200, 0x30644631, 0xfc5bf001, 
+    0x220048b5, 0x46314643, 0xf0013066, 0x48b2fc54, 0x464b2200, 0x30684631, 0xfc4df001, 0x220048ae, 
+    0x46314643, 0xf001306a, 0x48abfc46, 0x461a2300, 0x306c4631, 0xfc3ff001, 0x220048a7, 0x4631462b, 
+    0xf001306e, 0x48a4fc38, 0x463b2200, 0x30704631, 0xfc31f001, 0x220048a0, 0x4631462b, 0xf0013072, 
+    0x489dfc2a, 0x463b2200, 0x30744631, 0xfc23f001, 0x22004899, 0x46314643, 0xf0013076, 0x4896fc1c, 
+    0x464b2200, 0x30784631, 0xfc15f001, 0x22004892, 0x46314643, 0xf001307a, 0x488ffc0e, 0x461a2300, 
+    0x307c4631, 0xfc07f001, 0x2200488b, 0x4631462b, 0xf001307e, 0x4888fc00, 0x463b2200, 0x30804631, 
+    0xfbf9f001, 0xe8bd4620, 0x230147f0, 0x21042202, 0xbbf1f001, 0x41f0e92d, 0x23014c7f, 0x1f242202, 
+    0x46202104, 0xfbe7f001, 0x46202301, 0x21082203, 0xfbe1f001, 0xf6434878, 0xf6435407, 0x462375ff, 
+    0x46292200, 0xf0011c80, 0x4873fbd6, 0x22001c6e, 0x1d004633, 0xf0014629, 0x486ffbce, 0x2788f640, 
+    0x463b2200, 0x46291d80, 0xfbc5f001, 0xf241486a, 0x220008e2, 0x30084643, 0xf0014629, 0x4866fbbc, 
+    0x463b2200, 0x300a4629, 0xfbb5f001, 0x23004862, 0x4629461a, 0xf001300c, 0x485ffbae, 0x46232200, 
+    0x300e4629, 0xfba7f001, 0x2200485b, 0x46294633, 0xf0013010, 0x4858fba0, 0x46232200, 0x30124629, 
+    0xfb99f001, 0x22004854, 0x46294633, 0xf0013014, 0x4851fb92, 0x463b2200, 0x30164629, 0xfb8bf001, 
+    0x2200484d, 0x46294643, 0xf0013018, 0x484afb84, 0x463b2200, 0x301a4629, 0xfb7df001, 0x23004846, 
+    0x4629461a, 0xf001301c, 0x4843fb76, 0x46232200, 0x301e4629, 0xfb6ff001, 0x2200483f, 0x46294633, 
+    0xf0013020, 0x483cfb68, 0x46232200, 0x30224629, 0xfb61f001, 0x22004838, 0x46294633, 0xf0013024, 
+    0x4835fb5a, 0x463b2200, 0x30264629, 0xfb53f001, 0x22004831, 0x46294643, 0xf0013028, 0x482efb4c, 
+    0x463b2200, 0x302a4629, 0xfb45f001, 0x2300482a, 0x4629461a, 0xf001302c, 0x4827fb3e, 0x46232200, 
+    0x302e4629, 0xfb37f001, 0x22004823, 0x46294633, 0xf0013030, 0x4820fb30, 0x46232200, 0x30324629, 
+    0xfb29f001, 0x2200481c, 0x46294633, 0xf0013034, 0x4819fb22, 0x463b2200, 0x30364629, 0xfb1bf001, 
+    0x22004815, 0x46294643, 0xf0013038, 0x4812fb14, 0x463b2200, 0x303a4629, 0xfb0df001, 0x2300480e, 
+    0x4629461a, 0xf001303c, 0x480bfb06, 0x46232200, 0x303e4629, 0xfafff001, 0x22004807, 0x46294633, 
+    0xf0013040, 0xe8bdfaf8, 0x480341f0, 0x22002301, 0x1e804619, 0x0000e002, 0xd0030a04, 0xbaebf001, 
+    0x4c2fb570, 0xd0282803, 0x28051d25, 0x2804d035, 0x2301d154, 0x22024620, 0xf0012104, 0x2301fadc, 
+    0x22034620, 0xf0012108, 0x2301fad6, 0x21024628, 0xf001461a, 0x2301fad0, 0x22004628, 0xf0014619, 
+    0xf7fffaca, 0xf7fffed7, 0x2302fdd5, 0x21032200, 0xe8bd4620, 0xf0014070, 0x2300babe, 0x21034620, 
+    0xf001461a, 0x2300fab8, 0x22024620, 0xf0012104, 0x2300fab2, 0x21082203, 0x2301e7ea, 0x22024620, 
+    0xf0012104, 0x2301faa8, 0x22034620, 0xf0012108, 0x2300faa2, 0x22014628, 0xf0012102, 0x2300fa9c, 
+    0x21014628, 0xf001461a, 0x2301fa96, 0x22004620, 0xf0012103, 0xe8bdfa90, 0xe69b4070, 0x0000bd70, 
+    0xd0030a00, 0x488f2301, 0x46192200, 0xf001b510, 0x488dfa82, 0x0000f990, 0x2802b108, 0x4c8bd10e, 
+    0x21012300, 0x4620461a, 0xfa75f001, 0x46202301, 0x4010e8bd, 0x461a2102, 0xba6df001, 0xe92dbd10, 
+    0x460543f8, 0x46292000, 0x90004604, 0xf7fe2002, 0xf8dffb5a, 0xf44f91fc, 0x4f7d0000, 0x1622f241, 
+    0x81f0f8df, 0x0914f109, 0xe0109000, 0x46422109, 0xf7dd4668, 0x2801fef3, 0x4648d00e, 0xfa2ef001, 
+    0x2c04b204, 0x2c08d008, 0x42b4d006, 0x4638d004, 0xfa24f001, 0xd0e942a8, 0xf2402100, 0xf7dd4000, 
+    0x2c04fe63, 0x4638d115, 0xfa18f001, 0xd11042a8, 0x34164c67, 0xf0014620, 0x2200fa11, 0xf44f4601, 
+    0xf7d61000, 0x4620fc7c, 0xfa08f001, 0xe8bdb200, 0x200083f8, 0xe92de7fb, 0x4f5f5ff0, 0xf04f0004, 
+    0xd0050500, 0x46382301, 0x21102204, 0xfa13f001, 0x22024e56, 0x4623211c, 0xf0014630, 0x2301fa0c, 
+    0x22054630, 0xf0012120, 0xf240fa06, 0x21004800, 0xf7dd4640, 0x2301fe29, 0x21802207, 0xf0011cb0, 
+    0x2100f9fa, 0xf7dd4640, 0x2200fe1f, 0x31fff240, 0xf0011db0, 0x4f49f9fe, 0xf8dfb184, 0x2c039124, 
+    0xb120f8df, 0x0809f06f, 0x3a66f04f, 0x2c04d016, 0x2c05d014, 0x2c06d01e, 0xe033d049, 0xfa6cf003, 
+    0x4b424a41, 0xfab8f003, 0x463a4b41, 0xfbe8f003, 0xffa8f002, 0xfefcf003, 0xe0354605, 0xfa5cf003, 
+    0xf0044642, 0x2200f8d0, 0xf003464b, 0x4652faa5, 0xe00a465b, 0xfa50f003, 0xf0044642, 0x2200f8c4, 
+    0xf003464b, 0x4b33fa99, 0xf003463a, 0xf002f879, 0x4931ff89, 0xfe1af003, 0xf0034930, 0xf003ff41, 
+    0x4605fed7, 0x23004630, 0x211c2202, 0xf9a3f001, 0x46302301, 0x21202205, 0xf99df001, 0x2300481e, 
+    0x21102204, 0xf997f001, 0xe8bd4628, 0xf0039ff0, 0x4642fa23, 0xf897f004, 0x464b2200, 0xfa6cf003, 
+    0x463a4b1f, 0xb570e7d1, 0x480f4605, 0x0000f990, 0x2802b198, 0x4628d011, 0xff11f7ff, 0x46294604, 
+    0x1500f44f, 0x46282200, 0xfbc9f7d6, 0x46212200, 0xf7d64628, 0x4620fbc4, 0x4628bd70, 0xff4bf7ff, 
+    0xe7ecb204, 0xd03d0004, 0x00032228, 0xd03d408a, 0xd03d101e, 0xd003517c, 0xd03d408c, 0x9999999a, 
+    0x408b8000, 0x3fe66666, 0xd3c36113, 0x3fdf652b, 0x4079d599, 0x3fd99999, 0x447a0000, 0x461c4000, 
+    0x3fc99999, 0x41f0e92d, 0x461d2a02, 0x46804617, 0xd100460e, 0x48cbba4e, 0xf2402302, 0x44281180, 
+    0x46042207, 0xf937f001, 0xf2402f02, 0xd0172100, 0x46202301, 0xf0012209, 0x48c2f92e, 0x1e804641, 
+    0xf0014428, 0x48c0f90e, 0x20047801, 0xfd4cf7dd, 0x463148bc, 0x44281c80, 0x41f0e8bd, 0xb901f001, 
+    0xe7e62300, 0x4ff8e92d, 0x20504606, 0x22042300, 0x8000f8d0, 0x48b32110, 0x2990f44f, 0x46044430, 
+    0xf909f001, 0x230148af, 0x46192200, 0x44303016, 0xf0014605, 0x2301f900, 0x21024628, 0xf001461a, 
+    0x2300f8fa, 0x22014628, 0xf0012102, 0x2301f8f4, 0x21024628, 0xf001461a, 0x2300f8ee, 0x1180f240, 
+    0x46202207, 0xf8e7f001, 0xf2402300, 0x22092100, 0xf0014620, 0x489bf8e0, 0x1e802100, 0x46054430, 
+    0xf8bff001, 0x0a00f248, 0x23004620, 0x220f4657, 0xf0014651, 0x2301f8d0, 0x220f4639, 0xf0014620, 
+    0x2300f8ca, 0x220f4639, 0xf0014620, 0x488ef8c4, 0x46387801, 0xfce8f7dd, 0xf44f488a, 0xf8cd0b00, 
+    0x1d80b000, 0xe0061837, 0x21074a88, 0xf7dd4668, 0x2801fd55, 0x220fd006, 0x46384651, 0xf8b9f001, 
+    0xd0f12800, 0xfa1f487f, 0x1f00f188, 0xf0014430, 0x2100f888, 0xf0014628, 0x2300f884, 0x22014620, 
+    0xf0012102, 0x2301f898, 0x22034620, 0xf0012108, 0x2301f892, 0x22004620, 0xf0014619, 0x4871f88c, 
+    0xeb082500, 0x1c8078d8, 0xe0064406, 0x1015f839, 0xf0014630, 0x1c6df866, 0xebb5b2ad, 0xdbf50f68, 
+    0x46202300, 0x21082203, 0xf875f001, 0x46202300, 0x461a2101, 0xf86ff001, 0x46202301, 0x461a2102, 
+    0xf869f001, 0x46564d61, 0xb000f8cd, 0x2108e006, 0x4668462a, 0xfd02f7dd, 0xd0062801, 0x4631220f, 
+    0xf0014638, 0x2800f866, 0x2300d0f1, 0x22014620, 0xf0012102, 0xe8bdf850, 0xe92d8ff8, 0x460741f0, 
+    0xf44f2050, 0x68062890, 0x4f00f5b6, 0x484ddc27, 0x1f00b2b1, 0xf0014438, 0x484af824, 0x1e802100, 
+    0xf0014438, 0x4847f81e, 0x22022301, 0x21044438, 0xf0014605, 0x2301f830, 0x22004628, 0xf0014619, 
+    0x4840f82a, 0xeb062400, 0x1d0076d6, 0xe00b4407, 0xf0014638, 0xf838f803, 0x42811014, 0x2000d002, 
+    0x81f0e8bd, 0xb2a41c64, 0x0f66ebb4, 0x2300dbf0, 0x22024628, 0xf0012104, 0x2300f80e, 0x21014628, 
+    0xf001461a, 0x2301f808, 0x21024628, 0xf001461a, 0x2300f802, 0x22014628, 0xf0002102, 0x2001fffc, 
+    0xb570e7de, 0x4927460c, 0x49261866, 0x18653116, 0x4824b3a0, 0x1f002100, 0xf0004420, 0x4821ffd2, 
+    0x1e802100, 0xf0004420, 0x2100ffcc, 0xf0004630, 0x481cffc8, 0x1c802100, 0xf0004420, 0x4819ffc2, 
+    0x30122100, 0xf0004420, 0x4816ffbc, 0x300e2100, 0xf0004420, 0x4813ffb6, 0x010ff640, 0x44203010, 
+    0xffaff000, 0x2102480f, 0x44203014, 0xffa9f000, 0xe8bd4628, 0x21004070, 0xbfa3f000, 0x46282301, 
+    0x46192200, 0xffb7f000, 0x46282301, 0x461a2102, 0xffb1f000, 0xe8bd4630, 0x23014070, 0x21102204, 
+    0xbfa9f000, 0xd203a404, 0x0003227f, 0xd003517e, 0x41f0e92d, 0x46052400, 0x98062d20, 0xf240d301, 
+    0x29711401, 0xf444d301, 0x2a407481, 0xf444d301, 0xf1037482, 0x2e1f060f, 0xf444d301, 0x1dc67484, 
+    0xd3012e0f, 0x7488f444, 0x441e18ae, 0x1c764406, 0x0730f101, 0xdd0142be, 0x7490f444, 0x2b004429, 
+    0xdc004411, 0x2800425b, 0xdc004419, 0x44084240, 0xdd012870, 0x74a0f444, 0x46214836, 0xff51f000, 
+    0xe8bd4620, 0xe92d81f0, 0xb1f25ffc, 0x1480f44f, 0x0181eb01, 0x8001f910, 0xf9914401, 0xf9912003, 
+    0xf9919001, 0x4693a002, 0x6004f991, 0xf9904613, 0x4652101e, 0x46499101, 0x701ff990, 0x96004640, 
+    0xffa6f7ff, 0xd0020005, 0x2400e02c, 0x4822e7e0, 0xf388fa1f, 0x211f2200, 0x90004420, 0xff3bf000, 
+    0xfa1f481d, 0x2200f389, 0x44201c80, 0x4680217f, 0xff31f000, 0xf38afa1f, 0x22059800, 0x71e0f240, 
+    0xff29f000, 0xf38bfa1f, 0x7180f640, 0x46402207, 0xff21f000, 0xb2b34810, 0x30122200, 0x4420210f, 
+    0xff19f000, 0x22009801, 0xb283210f, 0x38dc480a, 0x46044420, 0xff0ff000, 0xdd072f03, 0xf246b2bb, 
+    0x220d0100, 0xf0004620, 0x2501ff06, 0xe8bd4628, 0x00009ffc, 0xd003519e, 0xd203a220, 0x4606b570, 
+    0xf968f000, 0xf1066805, 0xf020000b, 0x42b40407, 0x2000bf98, 0x462bd915, 0xb1ba686a, 0x42a06810, 
+    0xf104d310, 0x42880108, 0x6850bf3c, 0xd3076058, 0x19106851, 0x68116041, 0x60011b09, 0x60146058, 
+    0xbd701d10, 0x68524613, 0xd1e72a00, 0x46284621, 0xf948f000, 0xd1de2800, 0xb570bd70, 0x1f054604, 
+    0xf938f000, 0x2c006800, 0x6844bf18, 0x2c00d01b, 0x42acbf18, 0x4620bf3c, 0xd3f86864, 0x180a6801, 
+    0xbf1842aa, 0xd1036045, 0x4605682a, 0x60014411, 0x19416828, 0xbf1842a1, 0xd104606c, 0x60696861, 
+    0x44086821, 0xbd706028, 0x0320f1b2, 0xf1c2d50a, 0xfa200320, 0xfa01f002, 0xfa21f303, 0xea40f102, 
+    0x47700003, 0xf003fa21, 0x0100f04f, 0x00004770, 0xe92d4010, 0xe1b040c1, 0xe02440a3, 0x5a000002, 
+    0xe2700000, 0xe2611000, 0x32411001, 0xe1130003, 0x5a000002, 0xe2722000, 0xe2633000, 0x32433001, 
+    0xeb00009c, 0xe3140101, 0x0a000002, 0xe2700000, 0xe2611000, 0x32411001, 0xe3140102, 0x0a000002, 
+    0xe2722000, 0xe2633000, 0x32433001, 0xe8bd8010, 0xb510490b, 0x027cf1a1, 0xe9c24c0a, 0x21371237, 
+    0xeb00e006, 0xf8424310, 0x4b073021, 0x4003fb00, 0xf1a11e0b, 0xdcf40101, 0x2001bd10, 0x0000e7e8, 
+    0x000405ac, 0x66d619e1, 0x00010dcd, 0xe3520003, 0x9a000017, 0xe210c003, 0x0a000008, 0xe4d13001, 
+    0xe35c0002, 0xe082200c, 0x94d1c001, 0xe4c03001, 0x34d13001, 0x94c0c001, 0xe2422004, 0x34c03001, 
+    0xe2113003, 0x0a000012, 0xe2522008, 0x3a000004, 0xe4913004, 0xe2522008, 0xe491c004, 0xe8a01008, 
+    0xeafffff9, 0xe2922004, 0x54913004, 0x54803004, 0xe1a00000, 0xe1b02f82, 0x24d13001, 0x24d1c001, 
+    0x44d12001, 0x24c03001, 0x24c0c001, 0x44c02001, 0xe12fff1e, 0xe92d4010, 0xe2522020, 0x3a000005, 
+    0xe8b15018, 0xe2522020, 0xe8a05018, 0xe8b15018, 0xe8a05018, 0x2afffff9, 0xe1b0ce02, 0x28b15018, 
+    0x28a05018, 0x48b10018, 0x48a00018, 0xe8bd4010, 0xe1b0cf02, 0x24913004, 0x24803004, 0x012fff1e, 
+    0xe1b02f82, 0x20d130b2, 0x44d12001, 0x20c030b2, 0x44c02001, 0xe12fff1e, 0x03fff002, 0x2203ea43, 
+    0x4202ea42, 0xba2df000, 0xe3100003, 0xe92d4010, 0xe1a04000, 0x03110003, 0x1a00000a, 0xe59fe04c, 
+    0xe2522004, 0xba000006, 0xe4913004, 0xe043c00e, 0xe1ccc003, 0xe01cc38e, 0x04803004, 0x0afffff7, 
+    0xe2411004, 0xe2822004, 0xe2522001, 0xba000005, 0xe4d13001, 0xe3530000, 0xe4c03001, 0x1afffff9, 
+    0xe1a01002, 0xfb0000fc, 0xe1a00004, 0xe8bd8010, 0x01010101, 0x47704800, 0x0004061c, 0x47704770, 
+    0x47704770, 0x4604b538, 0x2000460a, 0xf0004669, 0x2800fa62, 0x4602d005, 0x99004620, 0xfa0af000, 
+    0xbd382001, 0xf0002001, 0xb5f8ba1d, 0xfa48f000, 0x20004605, 0x2010460c, 0x4606bf00, 0x42a019a8, 
+    0x4632d90d, 0x20004669, 0xfa45f000, 0xbf080007, 0xfa08f000, 0x42a09800, 0x4605bf18, 0xf7ff19c4, 
+    0x6005ffc9, 0x1df04607, 0x0007f020, 0x46281946, 0xf80af000, 0xd00642b4, 0x68384631, 0xe8bd1ba2, 
+    0xf00040f8, 0xbdf8b9d7, 0x60012100, 0x1001e9c0, 0x20104770, 0x00004770, 0xe92d4070, 0xe1a04003, 
+    0xe1a05002, 0xe1a03001, 0xe1a02000, 0xe3540000, 0x11a0c004, 0x01a0c005, 0xe16fef1c, 0xe28e0001, 
+    0xe1a0c01c, 0x127ee03f, 0x027ee01f, 0x4a000094, 0xe3530000, 0x116f1f13, 0x016f1f12, 0x1271103f, 
+    0x0271101f, 0xe051600e, 0x4a000092, 0x52760004, 0x5a000093, 0xe24e0020, 0xe3500004, 0xd1a01035, 
+    0xd18cc001, 0xe28f1f9f, 0xe1a0ce2c, 0xe35e001f, 0xe791c10c, 0x824ee020, 0xe26e6020, 0x8a000048, 
+    0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 0xe2611000, 0x32411001, 
+    0xe081019c, 0xe08cc001, 0xe081059c, 0xe1a04e30, 0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 
+    0xe2611000, 0x32411001, 0xe3530000, 0xe081019c, 0xe08cc001, 0x0a000009, 0xe081059c, 0xe1a04e30, 
+    0xe1a01611, 0xe1a00610, 0xe1811004, 0xe2700000, 0xe2611000, 0x32411001, 0xe081019c, 0xe08cc001, 
+    0xe080129c, 0xe3a01000, 0xe0a1039c, 0xe1a00e30, 0xe1a04611, 0xe1800004, 0xe1a01e31, 0xe0846590, 
+    0xe0522006, 0xe0244591, 0xe0c33004, 0xe3530001, 0x31520005, 0x38bd8070, 0xe086429c, 0xe3a04000, 
+    0xe0a4639c, 0xe26ec020, 0xe1a06e36, 0xe1a03c14, 0xe1866003, 0xe3a03000, 0xe1a04e34, 0xe08ce596, 
+    0xe0900006, 0xe0a11004, 0xe042200e, 0xe1520005, 0x38bd8070, 0xe2900001, 0xe2a11000, 0xe0422005, 
+    0xe052c005, 0x21a0200c, 0xe2b00000, 0xe2a11000, 0xe052c005, 0x21a0200c, 0xe2b00000, 0xe2a11000, 
+    0xe8bd8070, 0xe080159c, 0xe3a01000, 0xe0a1049c, 0xe1a01611, 0xe1a06e30, 0xe1811006, 0xe26e6020, 
+    0xe2611000, 0xe1a00610, 0xe2700000, 0x32411001, 0xe081019c, 0xe08cc001, 0xe080159c, 0xe3a01000, 
+    0xe0a1049c, 0xe1a01611, 0xe1a06e30, 0xe1811006, 0xe26e6020, 0xe2611000, 0xe1a00610, 0xe2700000, 
+    0x32411001, 0xe081019c, 0xe08cc001, 0xe24cc001, 0xe080129c, 0xe3a01000, 0xe0a1039c, 0xe1a00e31, 
+    0xe0816590, 0xe0522006, 0xe0211490, 0xe0c33001, 0xe1530004, 0x01520005, 0x33a01000, 0x38bd8070, 
+    0xe081629c, 0xe3a06000, 0xe0a6139c, 0xe3a01000, 0xe1a06e36, 0xe08ce596, 0xe0800006, 0xe052200e, 
+    0xe02ec496, 0xe0c3300e, 0xe1530004, 0x01520005, 0x38bd8070, 0xe2800001, 0xe0522005, 0xe0c33004, 
+    0xe8bd8070, 0xe92d000c, 0xe3a01000, 0xe3a00000, 0xe1a00000, 0xe8bd807c, 0xe3a01000, 0xe3a00000, 
+    0xe8bd8070, 0xe266e020, 0xe3a00000, 0xe3a01000, 0xe1a04614, 0xe1a0ce35, 0xe1a05615, 0xe184400c, 
+    0xe052e005, 0xe0d3c004, 0xe0a00000, 0x21a0300c, 0x21a0200e, 0xe2566001, 0x38bd8070, 0xe1b040a4, 
+    0xe1a05065, 0xeafffff5, 0xf0f0f0f0, 0xe38e38e3, 0xd79435e5, 0xcccccccc, 0xc30c30c3, 0xba2e8ba2, 
+    0xb21642c8, 0xaaaaaaaa, 0xa3d70a3d, 0x9d89d89d, 0x97b425ed, 0x92492492, 0x8d3dcb08, 0x88888888, 
+    0x84210842, 0x80000000, 0xf000b510, 0x6800f82f, 0xb510bd10, 0xf0004604, 0x6004f829, 0xf04fbd10, 
+    0x29040200, 0x8012f0c0, 0x0c03f010, 0x8043f000, 0x0c04f1cc, 0x0f02f1bc, 0xf800bf18, 0xbfa82b01, 
+    0x2b02f820, 0x010ceba1, 0xb835f000, 0x7cc1ea5f, 0xf800bf24, 0xf8002b01, 0xbf482b01, 0x2b01f800, 
+    0x00004770, 0x47704800, 0x00040614, 0x47704800, 0x00040614, 0x6843468c, 0xbf182b00, 0xbf38428b, 
+    0xd3f84618, 0x44186803, 0xd0074288, 0x0003f10c, 0x0007f020, 0x1a411d00, 0x46011a52, 0x600a1d08, 
+    0xbc8bf7ff, 0xf000b510, 0xe8bdf885, 0xf0004010, 0xf04fb87b, 0xb5000200, 0x46944613, 0x39204696, 
+    0xe8a0bf22, 0xe8a0500c, 0xf1b1500c, 0xf4bf0120, 0x0709aff7, 0xe8a0bf28, 0xbf48500c, 0xf85dc00c, 
+    0x0089eb04, 0xf840bf28, 0xbf082b04, 0xbf484770, 0x2b02f820, 0x4f80f011, 0xf800bf18, 0x47702b01, 
+    0x46694b12, 0x5280f500, 0x601a428a, 0x4611d801, 0x60194770, 0xb5304770, 0x466b4d0c, 0x5380f5a3, 
+    0x4422682c, 0xd80f429a, 0xf5021a9b, 0xeb035080, 0xeb0273d3, 0x42980363, 0x4618d900, 0xf0201dc0, 
+    0x600c0207, 0x602a1b10, 0x0000bd30, 0x00033040, 0x46754770, 0xff86f7ff, 0x000546ae, 0x46534669, 
+    0x0007f020, 0xb0184685, 0xf001b520, 0xe8bdea84, 0xf04f4020, 0xf04f0600, 0xf04f0700, 0xf04f0800, 
+    0xf0210b00, 0x46ac0107, 0x09c0e8ac, 0x09c0e8ac, 0x09c0e8ac, 0x09c0e8ac, 0x4770468d, 0xf3af4604, 
+    0x46208000, 0xfbf1f7d5, 0xd0012800, 0xb82af000, 0x00004770, 0x2801b510, 0x2100d005, 0xf000a003, 
+    0x2001f827, 0xa109bd10, 0x0000e7f8, 0x52474953, 0x4d454d54, 0x754f203a, 0x666f2074, 0x61656820, 
+    0x656d2070, 0x79726f6d, 0x00000000, 0x6548203a, 0x6d207061, 0x726f6d65, 0x6f632079, 0x70757272, 
+    0x00646574, 0x20184901, 0xe7fedfab, 0x00020026, 0x4605b570, 0x200a460c, 0x1c6de000, 0xf811f000, 
+    0x7828b135, 0xd1f82800, 0x1c64e002, 0xf809f000, 0x7820b114, 0xd1f82800, 0x4070e8bd, 0xf3af200a, 
+    0xb5088000, 0xf88d4669, 0x20030000, 0xbd08dfab, 0xe92d0003, 0xe59f0050, 0xe580e000, 0xe59f004c, 
+    0xe5901000, 0xe3510000, 0x1a000001, 0xe59f1040, 0xe5801000, 0xe2811001, 0xe5801000, 0xe59f0034, 
+    0xee151f10, 0xe5801000, 0xe59f002c, 0xee161f10, 0xe5801000, 0xe59f0024, 0xee151f11, 0xe5801000, 
+    0xe8bd0003, 0xe25ef008, 0xe320f000, 0xc300000c, 0xc3000010, 0xdead0000, 0xc3000020, 0xc3000024, 
+    0xc3000028, 0xf04fb500, 0xee116060, 0xea011f30, 0xee010100, 0xee111f30, 0xf3bf0f30, 0xf85d8f6f, 
+    0x4770eb04, 0xee15b500, 0xf3bf0f10, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f30, 0xf85d8f6f, 
+    0x4770eb04, 0xee15b500, 0xf3bf0f11, 0xf85d8f6f, 0x4770eb04, 0xee15b500, 0xf3bf0f31, 0xf85d8f6f, 
+    0x4770eb04, 0xee16b500, 0xf3bf0f10, 0xf85d8f6f, 0x4770eb04, 0xee16b500, 0xf3bf0f50, 0xf85d8f6f, 
+    0x4770eb04, 0x5ffce92d, 0x4601468a, 0x0000f04f, 0x2b01f811, 0x03bbf04f, 0xd128429a, 0x2b01f811, 
+    0x03a7f04f, 0xd122429a, 0x2b01f811, 0xd11e4282, 0x2b01f811, 0xd11a4282, 0xf04f4650, 0xf04f0a00, 
+    0x5c8c0200, 0x050aea84, 0x06fff005, 0x5016f830, 0x261aea4f, 0x0a06ea85, 0x0201f102, 0xdbf02a0a, 
+    0xf04f5a8c, 0x45540001, 0xf04fd001, 0xe8bd0000, 0x00009ffc, 0xe92d500f, 0xe14fc000, 0xe92d1000, 
+    0xe59f0024, 0xe5d01000, 0xe1a01201, 0xe59f201c, 0xe0822001, 0xe5920000, 0xe8bd1000, 0xe16ff00c, 
+    0xe8bd500f, 0xe25ef004, 0xe320f000, 0xc1000014, 0xc1000104, 0x5ff0e92d, 0x90d0f8df, 0x0a52ea4f, 
+    0x0b92ea4f, 0xf823880c, 0x88044b02, 0x4b02f823, 0x401bf831, 0x4b02f823, 0x401bf830, 0x4b02f823, 
+    0x0701f04f, 0x5007f819, 0x4015f831, 0x4b02f823, 0x4015f830, 0x4b02f823, 0x0505ebaa, 0x4015f831, 
+    0x0400f1c4, 0x4b02f823, 0x4015f830, 0x4b02f823, 0x0701f107, 0xf6ff455f, 0xe8bdafe5, 0xe92d9ff0, 
+    0xf8df5ff0, 0xea4f9068, 0xea4f0a51, 0xf04f0b91, 0xf9300700, 0x801c4b02, 0x4b02f930, 0xf1078014, 
+    0xf9300701, 0xf8234b02, 0xf930401b, 0xf8226b02, 0xf819601b, 0xf9305007, 0xf8234b02, 0xf9304015, 
+    0xf8226b02, 0xebaa6015, 0xf9300505, 0xf1c44b02, 0xf8230400, 0xf9304015, 0xf8226b02, 0xf1076015, 
+    0x455f0701, 0xafe5f6ff, 0x9ff0e8bd, 0x0002f110, 0x5ff0e92d, 0x0a00f04f, 0x4694468b, 0x1000f990, 
+    0x2001f990, 0x0302eb01, 0x5002f990, 0x6003f990, 0x0706eb05, 0x0806eba5, 0x0907eb03, 0x9b04f84c, 
+    0x0908eb03, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 
+    0x0402eba1, 0x0706eb05, 0x0806eba5, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0800f1c7, 
+    0x0705eba6, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 0x0301eba2, 0x0706eb05, 0x0806eba5, 
+    0x0907eb03, 0x9b04f84c, 0x0908eb03, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb03, 0x9b04f84c, 
+    0x0908eb03, 0x9b04f84c, 0x0302eb01, 0x0400f1c3, 0x0706eb05, 0x0806eba5, 0x0907eb04, 0x9b04f84c, 
+    0x0908eb04, 0x9b04f84c, 0x0800f1c7, 0x0705eba6, 0x0907eb04, 0x9b04f84c, 0x0908eb04, 0x9b04f84c, 
+    0x0004f100, 0x0a01f10a, 0xf6ff45da, 0xe8bdaf87, 0x00009ff0, 0xe92d500f, 0xe14fc000, 0xe92d1000, 
+    0xe59f0024, 0xe5d01000, 0xe1a01201, 0xe59f201c, 0xe0822001, 0xe5920000, 0xe8bd1000, 0xe16ff00c, 
+    0xe8bd500f, 0xe25ef004, 0xe320f000, 0xc100000c, 0xc1000104, 0x5ffce92d, 0x0300f04f, 0x4023f850, 
+    0x4023f841, 0x0301f103, 0xf6ff4293, 0xe8bdaff7, 0xe92d9ffc, 0xf04f5ffc, 0x2b000500, 0xf1c3da02, 
+    0xe00b0300, 0x4025f850, 0xf403fa04, 0x4025f841, 0x0501f105, 0xf6ff4295, 0xe00aaff5, 0x4025f850, 
+    0xf403fa44, 0x4025f841, 0x0501f105, 0xf6ff4295, 0xe8bdaff5, 0xe92d9ffc, 0xf04f5ffc, 0xf8300300, 
+    0xf8214013, 0xf1034013, 0x42930301, 0xaff7f6ff, 0x9ffce8bd, 0x5ffce92d, 0x0300f04f, 0x4013f930, 
+    0x4023f841, 0x0301f103, 0xf6ff4293, 0xe8bdaff7, 0xe92d9ffc, 0xf04f5ff0, 0xf9300500, 0xfa044b02, 
+    0xf841f403, 0xf1054b04, 0x42950501, 0xaff5f6ff, 0x9ff0e8bd, 0x5ffce92d, 0x0701f1a3, 0x0601f04f, 
+    0xf607fa06, 0x0500f04f, 0x4025f850, 0xfa444434, 0xf821f403, 0xf1054015, 0x42950501, 0xaff4f6ff, 
+    0x9ffce8bd, 0xe92d5ffc, 0xeafffffe, 0xe8bd9ffc, 0x6800b500, 0xb500bd00, 0xbd006001, 0x8800b500, 
+    0xb500bd00, 0xbd008001, 0x41f0e92d, 0xea246804, 0xfa030401, 0xea05f502, 0xea440501, 0x60040405, 
+    0x81f0e8bd, 0x41f0e92d, 0xea006800, 0xfa200001, 0xe8bdf002, 0xe92d81f0, 0x880441f0, 0x0401ea24, 
+    0xf502fa03, 0x0501ea05, 0x0405ea44, 0xe8bd8004, 0xe92d81f0, 0x880041f0, 0x0001ea00, 0xf002fa20, 
+    0x81f0e8bd, 0xe59f1150, 0xe5910000, 0xe590e000, 0xe59f0148, 0xe8be0002, 0xe5801000, 0xe8be0001, 
+    0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 0xef000000, 0xe12fff1e, 0xe28ee004, 
+    0xe92d0001, 0xe94d2000, 0xe320f000, 0xe24dd004, 0xe8bd0001, 0xe9204000, 0xe1a0e000, 0xe8bd0001, 
+    0xe94e7fff, 0xe320f000, 0xe24ee03c, 0xe14f0000, 0xe92e0001, 0xe59f00e4, 0xe5900000, 0xe92e0001, 
+    0xe59f10d4, 0xe5910000, 0xe580e000, 0xe59f00d0, 0xe1a0e00f, 0xe12fff10, 0xe59f10bc, 0xe5910000, 
+    0xe590e000, 0xe59f00b4, 0xe8be0002, 0xe5801000, 0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 
+    0xe59ee03c, 0xe25ef004, 0xe92d0001, 0xe94d2000, 0xe320f000, 0xe24dd004, 0xe8bd0001, 0xe9204000, 
+    0xe1a0e000, 0xe8bd0001, 0xe94e7fff, 0xe320f000, 0xe24ee03c, 0xe14f0000, 0xe92e0001, 0xe59f005c, 
+    0xe5900000, 0xe92e0001, 0xe59f104c, 0xe5910000, 0xe580e000, 0xe59f004c, 0xe1a0e00f, 0xe12fff10, 
+    0xe59f003c, 0xe1a0e00f, 0xe12fff10, 0xe59f1028, 0xe5910000, 0xe590e000, 0xe59f0020, 0xe8be0002, 
+    0xe5801000, 0xe8be0001, 0xe16ff000, 0xe8de7fff, 0xe320f000, 0xe59ee03c, 0xe25ef004, 0x00032fa4, 
+    0x00032ff4, 0x00026d6f, 0x00026bff, 0x41f0e92d, 0x460c4603, 0xea218819, 0x80190104, 0x0104ea41, 
+    0x42806810, 0x8019dcfc, 0x81f0e8bd, 0x41f0e92d, 0xea45880d, 0x800d0502, 0x0502ea25, 0x4284681c, 
+    0x800ddcfc, 0x81f0e8bd, 0xe92d0003, 0xe59f0034, 0xe59f1034, 0xe5801000, 0xe59f0030, 0xee151f31, 
+    0xe5801000, 0xe59f0028, 0xee151f30, 0xe5801000, 0xe59f0020, 0xee161f50, 0xe5801000, 0xe8bd0003, 
+    0xe25ef004, 0xe320f000, 0xc3000010, 0xfec0dead, 0xc300002c, 0xc3000030, 0xc3000034, 0x5ffce92d, 
+    0xf1a59d0d, 0xf04f0c05, 0xfa0b0b01, 0xea4ffa05, 0xb40c0a9a, 0x9a10b403, 0xf1009800, 0xf04f0104, 
+    0xf84d0e00, 0xf04fcd04, 0xb4040900, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 
+    0x0505eba3, 0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 
+    0xfb360600, 0xf8414413, 0xf840c03a, 0xeb02403a, 0xf84002cb, 0xf8417b08, 0xf1098b08, 0x45d10901, 
+    0xafd4f6ff, 0x00caeb00, 0x01caeb01, 0xf10ebc04, 0x45de0e01, 0xafc7f6ff, 0x0b4bea4f, 0x0a5aea4f, 
+    0xcb04f85d, 0x0c01f1ac, 0x0f00f1bc, 0x9800dcb4, 0x0104f100, 0x0e00f04f, 0x2982f645, 0x6803b404, 
+    0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 0xf8400606, 0xf841503a, 
+    0xf840603a, 0xf8417b08, 0xeb028b08, 0x680302cb, 0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 
+    0xeba30806, 0xeba40505, 0x68130606, 0x0545ea4f, 0x0646ea4f, 0xfc13fb35, 0xf403fb35, 0xcc03fb36, 
+    0x0600f1c6, 0x4413fb36, 0xc03af841, 0x403af840, 0x120beb02, 0x7b08f840, 0x8b08f841, 0xf8506803, 
+    0x680c503a, 0x603af851, 0x0705eba3, 0x0806eba4, 0x4426441d, 0x0307eb08, 0x0807eba8, 0x0343ea4f, 
+    0x0848ea4f, 0xf309fb33, 0xf809fb38, 0x303af840, 0x803af841, 0x5b08f840, 0x6b08f841, 0xf8506803, 
+    0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 0x0606eba4, 0xea4f6813, 0xea4f0545, 
+    0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 0xf8414413, 0xf840c03a, 0xeb02403a, 
+    0xf840120b, 0xf8417b08, 0x68038b08, 0x503af850, 0xf851680c, 0xeb03603a, 0xeb040705, 0xeba50806, 
+    0xeba40503, 0xf8410606, 0xf840503a, 0xf840603a, 0xf8417b08, 0x68038b08, 0x503af850, 0xf851680c, 
+    0xeb03603a, 0xeb040705, 0xeba30806, 0xeba40505, 0x68130606, 0x0545ea4f, 0x0646ea4f, 0xfc13fb35, 
+    0xf403fb35, 0xcc03fb36, 0x0600f1c6, 0x4413fb36, 0xc03af841, 0x403af840, 0x120beb02, 0x7b08f840, 
+    0x8b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0806eba4, 0x4426441d, 0x0307eb08, 
+    0x0807eba8, 0x0343ea4f, 0x0848ea4f, 0xf309fb33, 0xf809fb38, 0x0300f1c3, 0x803af840, 0x303af841, 
+    0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0806eb04, 0x0505eba3, 
+    0x0606eba4, 0xea4f6813, 0xea4f0545, 0xfb350646, 0xfb35fc13, 0xfb36f403, 0xf1c6cc03, 0xfb360600, 
+    0xf8414413, 0xf840c03a, 0xeb02403a, 0xf84002cb, 0xf8417b08, 0xeb008b08, 0xeb0100ca, 0xbc0401ca, 
+    0x0e01f10e, 0xf6ff45de, 0xea4faee9, 0xea4f0b4b, 0x98000a5a, 0x0104f100, 0x0800f04f, 0x2982f645, 
+    0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0206eb04, 0x0505eba3, 0x0606eba4, 0x503af840, 
+    0x603af841, 0x7b08f840, 0x2b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eba3, 0x0206eba4, 
+    0x4426441d, 0x0307eb02, 0x0207eba2, 0x0343ea4f, 0x0242ea4f, 0xf309fb33, 0xf209fb32, 0x303af840, 
+    0x203af841, 0x5b08f840, 0x6b08f841, 0xf8506803, 0x680c503a, 0x603af851, 0x0705eb03, 0x0206eb04, 
+    0x0503eba5, 0x0606eba4, 0x503af841, 0x603af840, 0x7b08f840, 0x2b08f841, 0xf8506803, 0x680c503a, 
+    0x603af851, 0x0705eba3, 0x0206eba4, 0x4426441d, 0x0307eb02, 0x0207eba2, 0x0343ea4f, 0x0242ea4f, 
+    0xf309fb33, 0xf209fb32, 0x0300f1c3, 0x203af840, 0x303af841, 0x5b08f840, 0x6b08f841, 0x00caeb00, 
+    0x01caeb01, 0x0801f108, 0xf6ff45d8, 0xea4faf89, 0x98000b4b, 0x0104f100, 0x0800f04f, 0x2b08f850, 
+    0x3b08f850, 0x4b08f850, 0xf8516805, 0xf8516b08, 0xf8517b08, 0xf8d19b08, 0xeb02a000, 0xeba20c04, 
+    0xeb060204, 0xeba60409, 0xeb030609, 0xeba30905, 0xeb070305, 0xeba7050a, 0xeb0c070a, 0xebac0a09, 
+    0xeb040c09, 0xeba40905, 0xeb020405, 0xeba20507, 0xeb060207, 0xeba60703, 0xf8400603, 0xf8402908, 
+    0xf8405908, 0xf840c908, 0xf841ab20, 0xf8417908, 0xf8416908, 0xf8414908, 0xf1089b20, 0x45d80801, 
+    0xafbcf6ff, 0x058bea4f, 0xf985fab5, 0x091ef1c9, 0x0c1ff1c9, 0x0b59ea4f, 0x0b01f10b, 0x0901f009, 
+    0xbc0344cb, 0xf850bc0c, 0xf8509b04, 0xf850ab04, 0xf8504b04, 0xeb09790c, 0xeba9060a, 0xf04f090a, 
+    0xfa460800, 0xfa49f60b, 0xfa44f90b, 0xfa47f40b, 0x6016f70b, 0x8000f8c3, 0x9025f842, 0x8025f843, 
+    0x0655ea4f, 0xf842442e, 0xf8434026, 0xf1c77026, 0xf8420700, 0xf8434015, 0xf8dd7015, 0xf04fe030, 
+    0xb4200402, 0x6034f850, 0x0004f100, 0x7034f850, 0x0004f100, 0xf90cfa04, 0xf9a9fa99, 0x0109eba5, 
+    0xf1a1fa91, 0xf10cfa21, 0x01fef001, 0x8031f850, 0x0004f100, 0x1031f850, 0x000cf1a0, 0x0a08eb06, 
+    0x0608eba6, 0x0801eb07, 0x0701eba7, 0x1029f85e, 0x0767ea4f, 0xf511fb36, 0x0600f1c6, 0x5501fb38, 
+    0xf601fb36, 0x0a6aea4f, 0x6611fb38, 0x0105eb0a, 0x0a05ebaa, 0x0806eb07, 0x0706eba7, 0xf10bfa41, 
+    0xf80bfa48, 0xfa0bfa4a, 0xf70bfa47, 0x1029f842, 0x8029f843, 0xeb09bc20, 0xf8420605, 0xf843a026, 
+    0xeba57026, 0xf1c70609, 0xf8420700, 0xf843a026, 0x442e7026, 0x0800f1c8, 0x1026f842, 0x8026f843, 
+    0x0402f104, 0xdb9c42ac, 0x5ffce8bd, 0x00004770, 0x5ffce92d, 0xf04f9e0d, 0xfa0b0b01, 0xea4ff506, 
+    0xf1a60555, 0xf1c90902, 0x68060c1f, 0x9025f850, 0x4015f850, 0x7015f851, 0x0700f1c7, 0x0a09eba6, 
+    0xea4f44b1, 0xea4f0a6a, 0xf8420969, 0xf8429b04, 0xf842ab04, 0xf8424b04, 0xf8dd790c, 0xf04fe030, 
+    0xfa040402, 0xfa99f90c, 0xf850f9a9, 0xf8513029, 0xeba58029, 0xf8500609, 0xf851a026, 0xeb037026, 
+    0xeba3060a, 0xeba8030a, 0x44b80a07, 0x7029f85e, 0x0a6aea4f, 0xfb07fb33, 0xf317fb33, 0xbb17fb38, 
+    0x0800f1c8, 0x0666ea4f, 0x3307fb38, 0x0806eb03, 0x0303eba6, 0x060aeb0b, 0x0b0aebab, 0x8034f842, 
+    0x0204f102, 0x6034f842, 0x0204f102, 0x0809eba5, 0xf8a8fa98, 0xf80cfa28, 0x08fef008, 0x3038f842, 
+    0x0204f102, 0xb038f842, 0x020cf1a2, 0x0402f104, 0xdbb642ac, 0xf1a59d0d, 0xf04f0c01, 0xfa0a0a01, 
+    0xea4ffb05, 0xb4040b9b, 0x98009a0d, 0x0e00f04f, 0x0b5bea4f, 0xcd04f84d, 0x1b08f850, 0x3b08f850, 
+    0x4b08f850, 0x5914f850, 0x6b08f850, 0x7b08f850, 0x8b08f850, 0x9904f850, 0x0c03eb01, 0x0103eba1, 
+    0x0307eb06, 0x0607eba6, 0x0705eb04, 0x0405eba4, 0x0509eb08, 0x0809eba8, 0x0907eb0c, 0x0c07ebac, 
+    0x0705eb03, 0x0305eba3, 0x0508eb01, 0x0108eba1, 0x0804eb06, 0x0604eba6, 0x5908f840, 0xc908f840, 
+    0x1908f840, 0x9b1cf840, 0x6908f840, 0x3908f840, 0x8908f840, 0x7b1cf840, 0x0e01f10e, 0xf6ff45de, 
+    0xf85dafbb, 0xea4fcb04, 0xea4f0b5b, 0xf1ac0a8a, 0x98000c02, 0x0104f100, 0x0e00f04f, 0x2982f645, 
+    0xf8506803, 0x680c503a, 0x603af851, 0x0805eb03, 0x0305eba3, 0x0506eb04, 0x0406eba4, 0x303af840, 
+    0x403af841, 0x8b08f840, 0x5b08f841, 0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0x680c6803, 
+    0x0806eba5, 0xfb384435, 0xfb35f809, 0xeb03f509, 0xeba30608, 0xeb040308, 0xeba40805, 0xf8400405, 
+    0xf841303a, 0xf840403a, 0xf8416b08, 0x680c8b08, 0x603af851, 0xf8506803, 0xeba3503a, 0x44330806, 
+    0x0605eb04, 0x0405eba4, 0x303af840, 0x403af841, 0x8b08f840, 0x6b08f841, 0x503af850, 0x603af851, 
+    0x0545ea4f, 0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 0x0506eba5, 0xf809fb38, 0xf509fb35, 
+    0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 
+    0x00caeb00, 0x01caeb01, 0x0e01f10e, 0xf6ff45de, 0xea4faf87, 0xea4f0b5b, 0xf1ac0a4a, 0x98000c01, 
+    0x0104f100, 0x0e00f04f, 0x6803b404, 0x503af850, 0xf851680c, 0xeb03603a, 0xeba30805, 0xeb040305, 
+    0xeba40506, 0xea4f0406, 0xea4f03e3, 0xea4f04e4, 0xea4f08e8, 0xf84005e5, 0xf841303a, 0xf840403a, 
+    0xf8418b08, 0xeb025b08, 0x680302cb, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 
+    0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 
+    0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 
+    0x8b08f841, 0x02cbeb02, 0x503af850, 0x603af851, 0x0545ea4f, 0x0646ea4f, 0x680c6803, 0x0806eba5, 
+    0xfb384435, 0xfb35f809, 0xeb03f509, 0xeba30608, 0xeb040308, 0xeba40805, 0xea4f0405, 0xea4f03e3, 
+    0xea4f04e4, 0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8416b08, 0xeb028b08, 0x680302cb, 
+    0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 
+    0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 
+    0x06e6ea4f, 0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0xf851680c, 
+    0x6803603a, 0x503af850, 0x0806eba3, 0xeb044433, 0xeba40605, 0xea4f0405, 0xea4f03e3, 0xea4f04e4, 
+    0xea4f06e6, 0xf84008e8, 0xf841303a, 0xf840403a, 0xf8418b08, 0xeb026b08, 0x680302cb, 0x503af850, 
+    0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 0xf517fb35, 0x8817fb36, 
+    0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 
+    0x08e8ea4f, 0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0x503af850, 0x603af851, 
+    0x0545ea4f, 0x0646ea4f, 0xeb056803, 0x680c0806, 0x0800f1c8, 0x0506eba5, 0xf809fb38, 0xf509fb35, 
+    0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x03e3ea4f, 0x04e4ea4f, 0x06e6ea4f, 0x08e8ea4f, 
+    0x303af840, 0x403af841, 0x6b08f840, 0x8b08f841, 0x02cbeb02, 0xf8506803, 0x680c503a, 0x603af851, 
+    0x0545ea4f, 0xea4f6817, 0xfb350646, 0xf1c5f807, 0xfb350500, 0xfb36f517, 0xfb368817, 0xeb035507, 
+    0xeba30608, 0xeb040308, 0xeba40805, 0xea4f0405, 0xea4f03e3, 0xea4f04e4, 0xea4f06e6, 0xf84008e8, 
+    0xf841303a, 0xf840403a, 0xf8416b08, 0xeb028b08, 0xeb0002cb, 0xeb0100ca, 0xbc0401ca, 0x0e01f10e, 
+    0xf6ff45de, 0xea4faea1, 0xea4f0b5b, 0xf1ac0a4a, 0x98000c01, 0x0104f100, 0x0e00f04f, 0x0900f04f, 
+    0x6803b404, 0x503af850, 0xf851680c, 0xea4f603a, 0x68170545, 0x0646ea4f, 0xf807fb35, 0x0500f1c5, 
+    0xf517fb35, 0x8817fb36, 0x5507fb36, 0x0608eb03, 0x0308eba3, 0x0805eb04, 0x0405eba4, 0x303af840, 
+    0x403af841, 0x02cbeb02, 0x6b08f840, 0x8b08f841, 0x0901f109, 0xf6ff45d1, 0xeb00afd4, 0xeb0100ca, 
+    0xbc0401ca, 0x0e01f10e, 0xf6ff45de, 0xea4fafc7, 0xea4f0b5b, 0xf1ac0a4a, 0xf1bc0c01, 0xdcb80f00, 
+    0xe8bdbc04, 0x47705ffc, 0x41f0e92d, 0x88079c06, 0x0701ea27, 0x0801ea47, 0x0500f04f, 0xf8a08007, 
+    0x88168000, 0x6025f843, 0x0501f105, 0xdbf542a5, 0xe8bdbf00, 0xe92d81f0, 0x880541f0, 0x0701ea25, 
+    0x0801ea45, 0xf8a08007, 0xf04f8000, 0xf04f0604, 0xf8320500, 0xf8327b02, 0xea488b02, 0xf8434707, 
+    0xf1057b04, 0x42b50501, 0xe8bddbf3, 0x000081f0, 0x5ffce92d, 0xf0f1fb90, 0x9ffce8bd, 0xe92d4001, 
+    0xe14f0000, 0xe3100020, 0x115e00b2, 0x13c00cff, 0x051e0004, 0x03c004ff, 0xe35000fe, 0x0a000007, 
+    0xe35000ff, 0x0a000009, 0xe3500000, 0x0a000001, 0xe8bd4001, 0xe1b0f00e, 0xe8bd4001, 0xeafffc66, 
+    0xe14f0000, 0xe38000c0, 0xe16ff000, 0xea000003, 0xe14f0000, 0xe3c000c0, 0xe16ff000, 0xeaffffff, 
+    0xe8bd4001, 0xe1b0f00e, 0x5ffce92d, 0x0400f04f, 0x5024f851, 0xf6f5fbb0, 0x6024f842, 0x0401f104, 
+    0xf6ff429c, 0xe8bdaff5, 0x00009ffc, 0x00040674, 0x00041c74, 0xe51f0010, 0xe12fff1e, 0xe92d0003, 
+    0xe59f0010, 0xe59f1010, 0xe5801000, 0xe8bd0003, 0xe25ef004, 0xe320f000, 0xc3000010, 0xdef0dead, 
+    0xe51ff004, 0x000102a1, 0xe51ff004, 0x00007b8b, 0x46c04778, 0xe92d41f0, 0xf10c0080, 0xe59f1028, 
+    0xe5910000, 0xe3500000, 0x0a000003, 0xe3a00000, 0xe5810000, 0xf1080080, 0xe8bd81f0, 0xf1080080, 
+    0xf57ff04f, 0xe320f003, 0xe8bd81f0, 0x00032230, 0x5ff0e92d, 0x0200f04f, 0x0300f04f, 0x3022f840, 
+    0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0x00009ff0, 0x5ff0e92d, 0x0200f04f, 0x0300f04f, 0x3012f820, 
+    0x0201f102, 0xf6ff428a, 0xe8bdaff9, 0x00499ff0, 0x20c1ea50, 0x2004bf18, 0xbf180d4a, 0x0001f040, 
+    0x72fff240, 0x5f51ebb2, 0xf040bf08, 0x28010002, 0x2005bf08, 0xe92d4770, 0x460441f0, 0x461e4615, 
+    0xf0371e4f, 0xeb000206, 0xe9d101c7, 0xd00d0100, 0x4633462a, 0xf8d0f001, 0xeb041e7f, 0xe9d303c7, 
+    0xf0002300, 0xf037fdf1, 0xd1f10206, 0xd0232f02, 0xd0112f04, 0xd1312f06, 0x4633462a, 0xf8bcf001, 
+    0x230ae9d4, 0xfde0f000, 0x4633462a, 0xf8b4f001, 0x2308e9d4, 0xfdd8f000, 0x4633462a, 0xf8acf001, 
+    0x2306e9d4, 0xfdd0f000, 0x4633462a, 0xf8a4f001, 0x2304e9d4, 0xfdc8f000, 0x4633462a, 0xf89cf001, 
+    0x2302e9d4, 0xfdc0f000, 0x4633462a, 0xf894f001, 0x2300e9d4, 0x41f0e8bd, 0xbdb6f000, 0x81f0e8bd, 
+    0x22004902, 0x46104613, 0xbe6af000, 0x3ff00000, 0xbdaaf000, 0x46132200, 0x46114610, 0xbe60f000, 
+    0xf2402000, 0xf04f3201, 0xf00141e0, 0x0000be9c, 0x20004a02, 0xf0010711, 0x0000be96, 0xfffffd01, 
+    0x41f0e92d, 0x4604460d, 0x5c0af3c1, 0x4b2d4a2c, 0x36fff2ac, 0xda2d2e14, 0xda122e00, 0xfd84f000, 
+    0x46132200, 0xf956f001, 0x2d00d245, 0xf04fbfbc, 0x24004500, 0xea55db3f, 0xbf180004, 0xd1174d22, 
+    0xf8dfe039, 0xfa2cc088, 0xea05f706, 0xea5c0c07, 0xd0320c04, 0xfd68f000, 0x46132200, 0xf93af001, 
+    0x2d00d229, 0xf44fdd03, 0x40f01080, 0x43bd4405, 0xe0202400, 0xdc202e33, 0x3cfff04f, 0x0714f1a6, 
+    0xf707fa2c, 0xd018423c, 0xf95af001, 0x46132200, 0xf920f001, 0x2d00d20f, 0x2e14dd0c, 0x1c6dbf08, 
+    0xf1c6d008, 0x20010134, 0x44204088, 0xbf3842a0, 0x46041c6d, 0x462943bc, 0xe8bd4620, 0x000081f0, 
+    0x8800759c, 0x7e37e43c, 0x3ff00000, 0x000fffff, 0x4df0e92d, 0x461c4616, 0x2800460f, 0xf021b094, 
+    0xf0234100, 0xbf144200, 0x25002501, 0xc410f8df, 0x0547eb05, 0xea4f4465, 0x429d036c, 0x0035d32b, 
+    0x2501bf18, 0x0544eb05, 0x44ac4bfe, 0xd322459c, 0x0306ea52, 0xd0024bfc, 0xd105429f, 0xb014b948, 
+    0x20004619, 0x8df0e8bd, 0xbf082800, 0x0c00f04f, 0xf04fd001, 0xeb0c0c01, 0xf5130347, 0xd80a1f00, 
+    0xbf142e00, 0x0c01f04f, 0x0c00f04f, 0x0344eb0c, 0x1f00f513, 0x4632d907, 0x46394623, 0xe8bdb014, 
+    0xf7ff4df0, 0xf8dfbf35, 0xf04f83a4, 0x2f000a00, 0x4542bfb8, 0x4be6da23, 0xbfa8429a, 0x0a02f04f, 
+    0x4be1da1d, 0xdc1a4293, 0xeb034be2, 0x2b145322, 0xf1c3dd08, 0xfa260c34, 0xfa03f30c, 0x45b4fc0c, 
+    0xe008d10d, 0xf1c3b95e, 0xfa220c14, 0xfa03f30c, 0x4594fc0c, 0xf003d103, 0xf1c30301, 0xea510a02, 
+    0xd11b0300, 0xda192c00, 0xbf182f00, 0x0f02f1ba, 0xf1bad002, 0xd0070f01, 0xf7fe2002, 0xb014fafa, 
+    0x4df0e8bd, 0xbeecf7ff, 0xf7fe2002, 0xf7fffaf2, 0xf081fee7, 0xb0144100, 0x8df0e8bd, 0xd16b0033, 
+    0xd1204542, 0x4280f107, 0x1280f512, 0x2800bf02, 0x49bd2000, 0x48bcd0ef, 0xdc054288, 0xbfa42c00, 
+    0x46214618, 0xe007dae7, 0xda051e20, 0xf080b014, 0x46184100, 0x8df0e8bd, 0x447949b7, 0x0100e9d1, 
+    0xe8bdb014, 0xf8df8df0, 0x4562c2c0, 0x2c00d12a, 0xb139da24, 0xd1174541, 0xbf042800, 0x46022000, 
+    0xe006d11c, 0x2002b140, 0xfab3f7fe, 0xfeb8f7ff, 0x4639460a, 0xbad2f000, 0x46394aa4, 0x2000b014, 
+    0x011ef362, 0x8df0e8bd, 0x463bda08, 0x46614602, 0x2000b014, 0x4df0e8bd, 0xbd02f000, 0xb0144639, 
+    0x8df0e8bd, 0xda174541, 0x4f80f1b4, 0xf1a4d00c, 0xf1b35300, 0xd10f53ff, 0xdb0d1e3b, 0xb0144619, 
+    0x4df0e8bd, 0xbbd8f000, 0x463bb014, 0x46194602, 0x4df0e8bd, 0xbf00f000, 0xf0270005, 0xd1384300, 
+    0x4541b1d1, 0x2f00d135, 0x2c00dd04, 0x2000bfa4, 0xdad44641, 0xdd012f00, 0xdb1f2c00, 0xda162f00, 
+    0xdb142c00, 0x0000f04f, 0x0f01f1ba, 0x497fbf14, 0xb0144982, 0x8df0e8bd, 0x0f02f1ba, 0x2f00bf18, 
+    0xf1bad00c, 0xd1090f01, 0xda072f00, 0x2f00e00b, 0x2c00bfb8, 0xf1bada0d, 0xd0040f01, 0x2000b014, 
+    0xe8bd4601, 0xb0148df0, 0xf04f2000, 0xe8bd4100, 0xf04f8df0, 0x46b80c01, 0x7ce7eb0c, 0xc044f8cd, 
+    0x0c0aea5c, 0xf8dfd00d, 0x4562c1b8, 0xf8dfdd7e, 0x4b6dc1b4, 0xdd124562, 0xdb0a428b, 0xdb182c00, 
+    0x2001e023, 0xfa25f7fe, 0xe8bdb014, 0xf7ff4df0, 0x4a5dbe21, 0xdc02428a, 0xdc0a2c00, 0x4299e015, 
+    0x2c00da02, 0xe004da11, 0x42994b57, 0x2c00dd19, 0x2002dd0b, 0xfa0df7fe, 0xfe12f7ff, 0xb0144a53, 
+    0x021ef361, 0xe8bd4611, 0x20028df0, 0xfa01f7fe, 0xfe0ef7ff, 0xb0144a4c, 0x021ef361, 0xe8bd4611, 
+    0x22008df0, 0xf0014641, 0xf06ff883, 0x46050201, 0xf001460f, 0x4b4dfc98, 0x3255f04f, 0xffa0f000, 
+    0x463b462a, 0xfe68f000, 0x22004b49, 0xff98f000, 0x463b462a, 0x468b4680, 0x46194610, 0xfe5cf000, 
+    0x465b4642, 0xfe58f000, 0x46804b42, 0xf04f4628, 0x910942c0, 0xf0004639, 0x9107fe4f, 0x46404683, 
+    0x4b3c4a3d, 0xf0009909, 0x4a3cfe47, 0x46284680, 0x91014b3b, 0xf0004639, 0x9b01fe3f, 0xf0014642, 
+    0x900cf847, 0x4602460d, 0xe000460b, 0x9907e00e, 0xf0004658, 0x9b07fb59, 0x465a4688, 0x46382700, 
+    0xf836f001, 0x462b9a0c, 0xb976f000, 0x1f80f5b1, 0x0000f04f, 0x4628da07, 0x22354619, 0xfc43f001, 
+    0xf06f4605, 0xeb000034, 0xf3c15221, 0x4b250013, 0x31fff2a2, 0x677ff040, 0xf0474298, 0x91015740, 
+    0xf04fbfd8, 0xdd0c0b00, 0x4281491f, 0xf04fbfc8, 0xdc060b01, 0x0b00f04f, 0xf5a79801, 0x1c401780, 
+    0x481a9001, 0x46394478, 0x00cbeb00, 0xe9d09704, 0x46282300, 0x93099212, 0xfffaf000, 0x0000e028, 
+    0x001fffff, 0x000fffff, 0x3ff00000, 0x7ff00000, 0x43400000, 0xfffffc01, 0x00001dea, 0xfff00000, 
+    0x41e00000, 0x43f00000, 0x3fefffff, 0x3fd55555, 0x3fe00000, 0x3ff71547, 0x652b82fe, 0xf85ddf44, 
+    0x3e54ae0b, 0x0003988e, 0x000bb67a, 0x00001ab8, 0x1007e9cd, 0x9b094628, 0x99049a12, 0xfae4f000, 
+    0x20004602, 0x49fe460b, 0xfb9af000, 0x46029100, 0x900c460b, 0x1007e9dd, 0xfdaef000, 0x46889006, 
+    0x447848f8, 0x68009a12, 0xf04f900e, 0xea405000, 0xeb000067, 0xf500408b, 0x9b092100, 0x2700980e, 
+    0xf0009102, 0x9b04ffa5, 0xf000462a, 0x463afec9, 0xf0004643, 0x9104fd91, 0x46384605, 0x9b024641, 
+    0xf0009a0e, 0xe9ddfd89, 0xf0003207, 0x9b04feb9, 0xf000462a, 0x9b00ff8d, 0xf0009a0c, 0x9a06fd7d, 
+    0x91094643, 0x900c4619, 0xf0004610, 0x4605fd75, 0x48dd4602, 0x9107460b, 0x44782106, 0xfc8bf7ff, 
+    0x462a9b07, 0x90009102, 0x46194610, 0xfd64f000, 0x9a009b02, 0xfd60f000, 0x46439a06, 0x46384605, 
+    0x46199100, 0xfa80f000, 0x9a0c9b09, 0xfd54f000, 0x462a9b00, 0xfa78f000, 0x4643463a, 0x90089100, 
+    0x46194610, 0xfd48f000, 0x22004bc8, 0x90049107, 0xfa6af000, 0x9a089b00, 0xfa66f000, 0x460d4bc3, 
+    0x4638463a, 0xff44f000, 0x9a049b07, 0xff40f000, 0x9a089b00, 0xfe64f000, 0x9104463a, 0x4641462b, 
+    0x4610900a, 0xfd28f000, 0x1007e9cd, 0x9a064643, 0x980a9904, 0xfd20f000, 0x4680462b, 0x460d980c, 
+    0x9909463a, 0xfd18f000, 0x462b4642, 0xfa3cf000, 0x46809100, 0x460b4602, 0x1007e9dd, 0xfa34f000, 
+    0x3207e9dd, 0x2000460f, 0xf0004605, 0x9b00ff11, 0xf0004642, 0x4ba6fe35, 0x46284680, 0x4260f04f, 
+    0x46399109, 0xfcf8f000, 0x90049102, 0x4aa14640, 0x99094b9f, 0xfcf0f000, 0x46804a9f, 0x4b9f4628, 
+    0x46399103, 0xfce8f000, 0x46429b03, 0xfa0cf000, 0x447a4a9b, 0x03cbeb02, 0x2300e9d3, 0xfa04f000, 
+    0x98014605, 0xf0009105, 0x9000fc70, 0xe9dd462a, 0x91030304, 0xf0009902, 0x4a92f9f7, 0xeb02447a, 
+    0xe9d303cb, 0x46932300, 0xf0009301, 0x9b03f9ed, 0xf0009a00, 0x9b03f9e9, 0x9a004688, 0x46382700, 
+    0xfec6f000, 0x465a9b01, 0xfec2f000, 0x9a049b02, 0xfebef000, 0x462a9b05, 0xfde2f000, 0x4d789b11, 
+    0xf1aa2200, 0xea530c01, 0x9206030c, 0x4d7ed101, 0xf04f9206, 0x46320a00, 0xf0004623, 0x4623fc9d, 
+    0x46839103, 0x46304652, 0xf0004619, 0x463afea1, 0xf0004643, 0x9b03fc91, 0xf000465a, 0x463af9b5, 
+    0x46064643, 0x4650468b, 0xf0004621, 0x4604fc85, 0x4632460f, 0xf000465b, 0x4a6cf9a7, 0x4291468a, 
+    0xebaadb21, 0xea530302, 0xd1100200, 0x463b4622, 0xfe7ef000, 0x46804a66, 0x4b664630, 0x46599101, 
+    0xf992f000, 0x46429b01, 0xfd64f000, 0x2002d22b, 0xffdff7fd, 0xfbe4f7ff, 0x4629460a, 0xf362b014, 
+    0xe8bd011e, 0x4b5c8df0, 0x4200f02a, 0xd31a429a, 0xeb0a4a5a, 0xea530302, 0xd1080200, 0x463b4622, 
+    0xfe56f000, 0x465b4632, 0xfd44f000, 0x2002d80b, 0xffbff7fd, 0xfbccf7ff, 0x5310ea4f, 0x4629460a, 
+    0x5303ea4f, 0x494ee7da, 0x0800f04f, 0xf02a4a4d, 0x42824000, 0x5120eb01, 0x484bda25, 0x1c80f44f, 
+    0x1c494478, 0xfa2c6802, 0x4450f001, 0x0301f1ac, 0x510af3c0, 0x31fff2a1, 0x0f00f1ba, 0xf301fa23, 
+    0x0c13f3c0, 0x0114f1c1, 0x1c80f44c, 0xf801fa2c, 0x0303ea20, 0xf1c8bfb8, 0x46200800, 0xf0004639, 
+    0x4604fe17, 0x4630460f, 0x46224659, 0xf000463b, 0x4b36f92b, 0x0a00f04f, 0x46529103, 0xf0004650, 
+    0xe9cdfbfb, 0x46501007, 0x4b324a31, 0xf0009903, 0x9102fbf3, 0x463b4622, 0x90049903, 0xf0004650, 
+    0x4632fdf7, 0xf000465b, 0x4a2bfd1b, 0xf0004b2b, 0x9b02fbe3, 0xf0009a04, 0x4607f907, 0x4602468a, 
+    0xe9dd460b, 0xf0001007, 0xe9ddf8ff, 0x46043207, 0xf000460e, 0x463afddd, 0xf0004653, 0x4622fd01, 
+    0x900c4633, 0x4610460f, 0xf0004619, 0x4682fbc5, 0x481b4602, 0x460b468b, 0x44782105, 0x0000e032, 
+    0x3ff00000, 0x00001aa2, 0x000019d2, 0x40080000, 0x3feec709, 0xdc3a03fd, 0x145b01f5, 0xbe3e2fe0, 
+    0x000018aa, 0x00001870, 0xbff00000, 0x40900000, 0x652b82fe, 0x3c971547, 0x4090cc00, 0x3f6f3400, 
+    0xfffffc01, 0x3fe00000, 0x000017a4, 0x3fe62e43, 0x0ca86c39, 0xbe205c61, 0xfefa39ef, 0x3fe62e42, 
+    0x000016a2, 0xfaa7f7ff, 0x465b4652, 0xfb84f000, 0x46334622, 0xfcb4f000, 0x46829a0c, 0x463b468b, 
+    0x46314620, 0xfb78f000, 0x463b9a0c, 0xf89cf000, 0x46072200, 0xf04f4650, 0x91004380, 0xf0004659, 
+    0x9103fd77, 0x465b4652, 0x900a4631, 0xf0004620, 0x9b03fb63, 0xf0009a0a, 0x9b00f943, 0xf000463a, 
+    0x4622fd67, 0xf0004633, 0x4b12fd63, 0xf0002200, 0x460efc87, 0x5108eb01, 0x15084604, 0xdc102800, 
+    0x46204642, 0xf0014631, 0xf7fff96e, 0x2804fa50, 0xf7ffbf08, 0x4642facd, 0x46314620, 0xf963f001, 
+    0x98064604, 0x4629460b, 0x4622b014, 0x4df0e8bd, 0xbb32f000, 0x3ff00000, 0x41f0e92d, 0x460f4606, 
+    0xfc6af000, 0x460d0004, 0x2001bf18, 0xf0204328, 0xf1c04000, 0xf100607f, 0x0fc040e0, 0x1c30d00e, 
+    0x2001bf18, 0xf0204338, 0xf1c04000, 0xf100607f, 0x0fc040e0, 0x2001bf04, 0xfe8bf7fd, 0x46294620, 
+    0x81f0e8bd, 0x4200f021, 0x5260f1a2, 0x1f80f5b2, 0x4300f001, 0xf1d2bf28, 0xd90b6c7f, 0x1c00ea5f, 
+    0x02c2ea43, 0x7050eb42, 0x4770bf18, 0xf020bf28, 0x47700001, 0x1f80f5b2, 0x4618bfbc, 0xea4f4770, 
+    0xf51c0c41, 0xd2021f00, 0xf0014608, 0xb570b860, 0xfb8cf000, 0x89000000, 0xbff6f7ff, 0x4000f04f, 
+    0x0080f5a0, 0x00004770, 0xea91b510, 0xbf480f03, 0x4300f083, 0x84e4f100, 0xeb711a84, 0xd2050c03, 
+    0xeb431912, 0x1b00030c, 0x010ceb61, 0xe124f8df, 0x5411ea4f, 0x5c13eba4, 0x0f43ea1e, 0xea9ebf18, 
+    0xd0735f44, 0x030eea23, 0x0e20f1dc, 0x5104ea21, 0x1380f443, 0xfa22d332, 0xeb10fe0c, 0xfa23000e, 
+    0xeb41fe0c, 0xf1cc010e, 0xfa030e20, 0xeb10fe0e, 0xf151000e, 0xf5b10100, 0xf1cc1f80, 0xd2320e20, 
+    0x5104eb01, 0xf20efa12, 0x4010e8bd, 0x4770bf58, 0xbf381c40, 0x0242ea5f, 0x4770bf18, 0xbf142800, 
+    0x0001f020, 0x0100f141, 0x0341ea4f, 0x1f00f513, 0x4770bf38, 0x41c0f1a1, 0xbb76f000, 0xeb432a01, 
+    0xf1ac0203, 0xf1dc0c20, 0xbf320e1f, 0x0e00f04f, 0xf30cfa23, 0x0003eb10, 0x5104eb41, 0x5f11ebb4, 
+    0xeba1d0d0, 0xf5015104, 0x08491180, 0x0030ea5f, 0x5104eb01, 0xf150d30e, 0xbf380000, 0xfe0efa12, 
+    0xe8bdd108, 0xe7c94010, 0xbf381c40, 0x0242ea5f, 0xe7c3d1ca, 0x4010e8bd, 0x0341ea4f, 0x1f00f513, 
+    0x4770bf38, 0x41c0f1a1, 0xbb3ef000, 0x5f44ea9e, 0xea11d008, 0xe8bd0f5e, 0xbf044010, 0x4100f001, 
+    0x47702000, 0x4010e8bd, 0xf000b570, 0xbf00fadf, 0x3ebefb64, 0xffe00000, 0xf04f4902, 0xf0010000, 
+    0xbf00b820, 0x7ff80000, 0xbf581049, 0x4140f1c1, 0xbf58105b, 0x4340f1c3, 0xf3ef428b, 0x47708000, 
+    0x41c0e92d, 0xf8dfb430, 0xea3cc2a0, 0xbf181411, 0x1413ea3c, 0x80ecf000, 0x0503ea81, 0x1411ea1c, 
+    0x74d5ea44, 0xea1cbf18, 0xf0001513, 0xeba480c7, 0xf04f0405, 0xea454500, 0xea4521c1, 0xea4123c3, 
+    0xea435150, 0xf1045352, 0x4299747f, 0x3400f504, 0x20c0ea4f, 0x22c2ea4f, 0x4290bf08, 0x809cf000, 
+    0x6513ea4f, 0x1640f20f, 0xea4f5d76, 0xfb064513, 0xf1c7f705, 0xfb067780, 0xea4ff707, 0xfba737d7, 
+    0x42766803, 0x3880f5c8, 0xce06fba7, 0xf1a8bf38, 0xfb070801, 0xf04fe608, 0xfba60e00, 0xfbe68c02, 
+    0xf1dcce03, 0xf1ce0c00, 0xbf384e00, 0x0e01f1ae, 0x580cfba6, 0x0700f04f, 0x0500f04f, 0x870efbe6, 
+    0xc608fba1, 0xce07fba0, 0x060eeb16, 0x0500f145, 0x6507fbe1, 0x4ee0f115, 0xf5a4bf7e, 0xea5f3480, 
+    0x416d0646, 0x0780f116, 0x0500f145, 0x2717ea4f, 0x6606ea4f, 0x6705ea47, 0x46def1a6, 0x5f80f1b6, 
+    0x2515ea4f, 0x4638d91f, 0x0c01f024, 0x71c4eb05, 0x6ffef1bc, 0x110ceb01, 0xbcf0d802, 0x8100e8bd, 
+    0xbf5c4224, 0x1e80f501, 0x7fc4ea9e, 0xbcf0d402, 0x8100e8bd, 0xd4384224, 0xf1a1bcf0, 0xe8bd41c0, 
+    0xf0004100, 0xea4fba71, 0xea4222d2, 0xea4f5243, 0xfba723d3, 0xea4f8602, 0xea4020d0, 0xfb075041, 
+    0xea1e6603, 0xea4f0f0e, 0xfb0521d1, 0xbf586602, 0x5600eba6, 0x5600ebb6, 0x0e52ea4f, 0x7ec3ea4e, 
+    0x0e0eeb18, 0x0e53eb56, 0xeb18d5bd, 0x415e0802, 0xf1551c7f, 0xe7b60500, 0x1580f44f, 0x0700f04f, 
+    0x0600f04f, 0x0800f04f, 0xbcf0e7ad, 0x0000f04f, 0x41c0f101, 0x4100f001, 0x8100e8bd, 0x1f0cea11, 
+    0x1513ea0c, 0xe00cd000, 0x1f0cea13, 0x8025f000, 0x0000f04f, 0xea81bcf0, 0xf0010103, 0xe8bd4100, 
+    0xbcf08100, 0x4100e8bd, 0x0103ea81, 0xba1cf000, 0xe8bdbcf0, 0xb5704100, 0xf9c8f000, 0x3efc7e09, 
+    0xb807f000, 0x0103ea81, 0x0000f04f, 0x4100f001, 0xea814770, 0xf0000103, 0xbcf0ba07, 0x4100e8bd, 
+    0x0000f04f, 0x47704921, 0xf9fbfdff, 0xf2f4f5f7, 0xebedeef0, 0xe4e6e8e9, 0xdee0e1e3, 0xd8dadbdd, 
+    0xd3d4d5d7, 0xcdcfd0d1, 0xc8cacbcc, 0xc4c5c6c7, 0xbfc0c1c2, 0xbbbcbdbe, 0xb7b8b9ba, 0xb3b4b5b6, 
+    0xafb0b1b2, 0xabacadae, 0xa8a8a9aa, 0xa4a5a6a7, 0xa1a2a3a3, 0x9e9f9fa0, 0x9b9c9c9d, 0x9899999a, 
+    0x95969797, 0x93939495, 0x90919192, 0x8e8e8f8f, 0x8b8c8c8d, 0x89898a8b, 0x87878888, 0x84858586, 
+    0x82838384, 0x80818182, 0x07ff0000, 0x7ff80000, 0x0341ea4f, 0x5353ea4f, 0x6380f5a3, 0x031ef1d3, 
+    0xf1d3bfc8, 0xdd0c0c21, 0x4200f04f, 0x22c1ea42, 0x5250ea42, 0xfc03fa32, 0x7ce1ea8c, 0x70e1ebac, 
+    0x2b104770, 0x2000bfc4, 0xf5034770, 0xf1bc7c78, 0xd0043fff, 0x4200f06f, 0x0021ea82, 0xb5704770, 
+    0xf944f000, 0x80249249, 0x47702000, 0x0000e7f2, 0x5311ea4f, 0x6380f5a3, 0x031ef1d3, 0xf1d3bfa8, 
+    0xdb080c20, 0x4200f04f, 0x22c1ea42, 0x5250ea52, 0xf003fa32, 0x42094770, 0x2b10d40b, 0x2000bfc4, 
+    0xf5034770, 0xf1bc7c78, 0xd0053fff, 0x30fff04f, 0xf04f4770, 0x47700000, 0xf000b570, 0xbf00f917, 
+    0x80249249, 0x47702000, 0xf010e7f0, 0xbf484200, 0xfab04240, 0xfa10f380, 0xd00af103, 0x031df1c3, 
+    0x6380f503, 0x5041ea4f, 0x5203eb02, 0x21d1eb02, 0xf04f4770, 0x47700000, 0xf380fab0, 0xf103fa10, 
+    0xf1c3d00a, 0xf503031d, 0xea4f6380, 0xea4f5041, 0xeb025203, 0x477021d1, 0x0000f04f, 0x00004770, 
+    0x0c03ea51, 0xf51cd417, 0xbf581f80, 0x1f80f5bc, 0x8006f100, 0xbf184299, 0xbf084770, 0x47704290, 
+    0xf511d707, 0xbf581f80, 0x1f80f513, 0x4299d419, 0x42894770, 0xf51c4770, 0xd5081f80, 0x1f80f5bc, 
+    0x428bd5f7, 0x4770bf18, 0x4282bf08, 0xf44f4770, 0xeb1c1c00, 0xbf380f41, 0x0f43eb1c, 0x428bd201, 
+    0xb5704770, 0xf8b2f000, 0x00492492, 0x5100f04f, 0x5380f04f, 0xbdd8f7ff, 0xc148f8df, 0xea1cb570, 
+    0xbf1e1e11, 0x1513ea1c, 0x0f0cea9e, 0x0f0cea95, 0x806ff000, 0x0403ea81, 0x134cea23, 0x7ed4ea4e, 
+    0x114cea21, 0x1180f441, 0x1380f443, 0xfba144ae, 0xfba04c02, 0xf1ae6503, 0x19367e7f, 0x050ceb55, 
+    0x4c03fba1, 0x0300f14c, 0x1c02fba0, 0x060ceb16, 0xf1534165, 0x42090300, 0xf046bf18, 0xf4130601, 
+    0xd10b7f00, 0x3103ea4f, 0x3005ea4f, 0xea410334, 0xea405115, 0xf06f5016, 0xe00a0203, 0x21c3ea4f, 
+    0x20c5ea4f, 0xea4102f4, 0xea405155, 0xf06f5056, 0xeb020202, 0xeb01422e, 0xea855502, 0xd00a71ce, 
+    0x0c44ea5f, 0xf024bf18, 0xf1504400, 0xf1410000, 0xea200100, 0xf24070d4, 0x45627cfe, 0xbd70d200, 
+    0xbf1442a8, 0x4480f04f, 0x4440f04f, 0xbf082e00, 0xf1be2400, 0xbfa86f80, 0x41c0f1a1, 0x4070e8bd, 
+    0x8082f280, 0x0000f04f, 0x41c0f101, 0x4100f001, 0xea9e4770, 0xea0c0f0c, 0xbf181513, 0x0f0cea95, 
+    0xf04fd006, 0xea810000, 0xf00e0e03, 0xbd704100, 0xf81cf000, 0x3e010089, 0xb807f000, 0xb809f000, 
+    0x0c43ea4f, 0x5c5cea5f, 0xea81d008, 0xf0000103, 0xea4fb85b, 0xea5f0c41, 0xd1f65c5c, 0x0000f04f, 
+    0x47704901, 0x07ff0000, 0x7ff80000, 0x0e02f10e, 0x0e03f02e, 0x6b04f85e, 0xd4054236, 0xeb432a01, 
+    0xf5150503, 0xd8121f00, 0xeb412801, 0xf51c0c01, 0xd80c1f00, 0xea4fd10e, 0xf5157cd1, 0xeb0c1f00, 
+    0xf10c0c4c, 0xbf080c02, 0x7cd3eb4c, 0xf04fe004, 0xe0010c08, 0x7cd3ea4f, 0x054ceb0c, 0xf605fa26, 
+    0x0607f006, 0x0c04f1b6, 0xeb0ed206, 0xe8bd0c86, 0xf04c4070, 0x47600c01, 0xf00ce8df, 0x02020b09, 
+    0x4100f04f, 0x0000f04f, 0x2100f5a1, 0x4619bd70, 0x28014610, 0x0401eb51, 0xf5d4bf18, 0xbf841400, 
+    0xf0012000, 0xbd704100, 0xf5a00808, 0xea4f1100, 0x47700131, 0x0c01ea53, 0xf51cd417, 0xbf581f80, 
+    0x1f80f5bc, 0x8006f100, 0xbf18428b, 0xbf084770, 0x47704282, 0xf513d707, 0xbf581f80, 0x1f80f511, 
+    0x428bd419, 0x429b4770, 0xf51c4770, 0xd5081f80, 0x1f80f5bc, 0x4299d5f7, 0x4770bf18, 0x4290bf08, 
+    0xf44f4770, 0xeb1c1c00, 0xbf380f43, 0x0f41eb1c, 0x4299d201, 0xb40f4770, 0xbc03bc0c, 0xbec1f7ff, 
+    0x0f03ea91, 0xf081b510, 0xf53f4100, 0xf083abf5, 0xf0004300, 0x0000b8d5, 0x41f0e92d, 0x1c80f501, 
+    0x1f00f5bc, 0x80a9f2c0, 0x5c11ea4f, 0x510cea21, 0x0cfdf10c, 0x1180f441, 0x0c5cea5f, 0x7cc0f50c, 
+    0x0040d301, 0xa4304149, 0xea410289, 0x02875190, 0x0c0a0e8e, 0xfb045da4, 0xfb02f604, 0xf1c6f606, 
+    0xfba44640, 0x0df66206, 0x2642ea46, 0xf406fb06, 0x2301fba4, 0xf1c34252, 0xbf384340, 0xfba61e5b, 
+    0x24004202, 0x2403fbe6, 0xea420bd2, 0xfba64644, 0xfba12306, 0xfba3e202, 0xfbe3e407, 0x42644261, 
+    0x4e40f1c2, 0xf1aebf38, 0xfba60e01, 0xf04f2304, 0xfbe60200, 0xfba2320e, 0x00344603, 0x6462fbe2, 
+    0xe606fba1, 0xe807fba4, 0x6861fbe4, 0xf1c84276, 0xbf385840, 0x0801f1a8, 0xe406fba2, 0xe508fba3, 
+    0x5468fbe2, 0xe605fba1, 0xe804fba7, 0x8664fbe1, 0x0520f118, 0x0600f156, 0xf1a809a8, 0x09b1081b, 
+    0x083ff008, 0x0f0af1b8, 0x6086ea40, 0xeb01d91c, 0xe8bd510c, 0xbf0081f0, 0xe8eef5fc, 0xd3d8dde2, 
+    0xc3c7cbcf, 0xb6b9bdc0, 0xacaeb1b4, 0xa3a5a7a9, 0x9b9d9fa1, 0x9596989a, 0x8f909293, 0x898b8c8d, 
+    0x85868788, 0x81828384, 0x6800fba0, 0xf201fb00, 0x0842eb08, 0x2887ebb8, 0x1834d507, 0x0401eb58, 
+    0x1c40d5d5, 0x0100f151, 0x1a34e7d1, 0x0401eb78, 0x1e40d4cd, 0x0100f171, 0xea5fe7c9, 0xea5f0c4c, 
+    0xd10d5c9c, 0xf04fd305, 0xf0010000, 0xe8bd4100, 0xe8bd81f0, 0xb57041f0, 0xfea8f7ff, 0xbeffdb6d, 
+    0x41f0e8bd, 0x0000f04f, 0x47704900, 0x7ff80000, 0xea91b510, 0xbf480f03, 0x4300f083, 0xab1cf53f, 
+    0xeb711a84, 0xd2070c03, 0xf08c1912, 0xeb434c00, 0x1b00030c, 0x010ceb61, 0xe1a4f8df, 0x5411ea4f, 
+    0x5c13eba4, 0x0f43ea1e, 0xea9ebf18, 0xf0005f44, 0xea2380b0, 0x4252036e, 0x5104ea21, 0x036eebc3, 
+    0x1e5bbf38, 0x0e20f1dc, 0xfa22d325, 0xeb10fe0c, 0xfa43000e, 0xeb41fe0c, 0xf1cc010e, 0xfa030e20, 
+    0xeb10fe0e, 0xf151000e, 0xf1cc0100, 0xd4290e20, 0xf20efa12, 0x5104eb01, 0x4010e8bd, 0x4770bf58, 
+    0xbf1c1c40, 0x4f00f1b2, 0x28004770, 0x1c49bf0c, 0x0001f020, 0xeb124770, 0xeb430e02, 0xbf180203, 
+    0x0e01f04f, 0x0242ea4e, 0x0c20f1ac, 0x0e1ef1dc, 0xfa43d954, 0xeb10fe0c, 0xf151000e, 0xf1cc31ff, 
+    0xd5d50e1e, 0x0e01f10e, 0xfe0efa12, 0xeb414140, 0xeb010101, 0xea5f5c44, 0xd9105c5c, 0x70deeb10, 
+    0x5104eb01, 0xf1bebf38, 0xe8bd4f00, 0xbf184010, 0x28004770, 0x1c49bf0c, 0x0001f020, 0xd2304770, 
+    0x2cd4ea4f, 0x1100f511, 0x6400f424, 0xfab1d01b, 0x3a0bf281, 0x1ea41aa4, 0x0320f1d2, 0xfa304091, 
+    0x4319f303, 0xeb014090, 0x2c0071cc, 0x5104eb01, 0x4010e8bd, 0x4770bfa8, 0x41c0f101, 0x0000f04f, 
+    0x4100f001, 0xfab04770, 0xfa10f380, 0xd100f103, 0x1ae4bd10, 0x05483c17, 0xe7e40ac9, 0x5104eb01, 
+    0x1049bd10, 0x5104eb01, 0x4010e8bd, 0x0030ea4f, 0xf04fe002, 0x47700100, 0xbf08004a, 0xd0f84200, 
+    0x1f00f5b2, 0x4770bf28, 0x4100f001, 0x0000f04f, 0xea9e4770, 0xd0075f44, 0x0f5eea11, 0x4010e8bd, 
+    0x2100bf04, 0x47702000, 0x4010e8bd, 0xf7ffb570, 0xbf00fdbd, 0x3ef6df40, 0x4100f083, 0x47704610, 
+    0xffe00000, 0xea4f0043, 0xea4f0cd3, 0x40430c3c, 0x0740bf1f, 0x5160f10c, 0x4ffef013, 0xf01c4770, 
+    0xd1036f00, 0xf00c2000, 0x47704100, 0x4300f00c, 0x7050ea43, 0xea40b510, 0xf00000cc, 0xbf00fa22, 
+    0x92000000, 0x0100ea4f, 0xbddef7ff, 0x4100f04f, 0x0000f04f, 0x2100f5a1, 0x00004770, 0x0f01ea90, 
+    0xf081bf48, 0xf1004100, 0x1a42825e, 0x1a80bf3c, 0xea4f1889, 0xf04f52d0, 0xea1c4c7f, 0xeba20f41, 
+    0xbf1853d1, 0x6f02ea9c, 0x803bf000, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 0xfc03fa21, 0x0c0ceb10, 
+    0xf102d21e, 0xea5f32ff, 0xeb40201c, 0xbf3850c2, 0xf01c4770, 0xea4f0f7f, 0xbf180c40, 0x4f7ff1bc, 
+    0x4770bf38, 0x0320f1c3, 0xbf084099, 0x0001f020, 0x4f7ff1bc, 0x4770bf38, 0x40c0f1a0, 0xba17f000, 
+    0x003cea4f, 0xeb400a00, 0xbf2850c2, 0x0ffff01c, 0x0c40ea4f, 0xbf18d0e6, 0x4f7ff1bc, 0x4770bf38, 
+    0xea9ce7ea, 0xd0056f02, 0x0f5cea10, 0xf000bf08, 0x47704000, 0xf000b510, 0xbf00f9b4, 0x3ebefb64, 
+    0xf0004801, 0xbf00ba6e, 0x7fc00000, 0x0c7ff44f, 0x12d0ea1c, 0xea1cbf1e, 0xea9213d1, 0xea930f0c, 
+    0xf0000f0c, 0xea908085, 0xbf480f01, 0x7280f442, 0x0c00f440, 0x0000f441, 0x417ff02c, 0x407ff020, 
+    0x4281b500, 0x0203eba2, 0x1c08f20f, 0x4e50ebac, 0x0000f1c0, 0xe000f89e, 0x0e4eea4f, 0xfc0efb00, 
+    0x0049bf38, 0x1c2cea4f, 0x02faf502, 0xf30efb0c, 0x1eceea4f, 0x2c11ea4f, 0x21c1ea4f, 0x5e63eb0e, 
+    0x4222eb42, 0xfc0cfb0e, 0x531cea4f, 0x1103fb00, 0x2c11ea4f, 0x3101ea4f, 0xfc0cfb0e, 0x4cdcea4f, 
+    0x110cfb00, 0xbf2842c1, 0xeb4c1809, 0xf85d3303, 0xeb10eb04, 0xeb430141, 0xf5b250c2, 0xbf380f7c, 
+    0xd5294770, 0x0ff0f012, 0xf100bf1c, 0xf00040c0, 0x47704000, 0x83828100, 0x87868584, 0x8c8b8988, 
+    0x918f8e8d, 0x96959392, 0x9c9a9997, 0xa2a09f9d, 0xa8a7a5a3, 0xb0aeacaa, 0xb7b5b3b2, 0xc0bebcb9, 
+    0xc9c7c5c2, 0xd4d1cecc, 0xdfdcd9d7, 0xece9e6e2, 0xfaf7f3f0, 0x000000fe, 0x0c40ea4f, 0x7c80f10c, 
+    0x4f7ef1bc, 0x4770bf28, 0x40c0f1b0, 0xb95ff000, 0x0f01ea90, 0x13d1ea0c, 0xf442bf48, 0x45627280, 
+    0x4563bf38, 0xf413d207, 0xd0160f7f, 0x0001ea80, 0x4000f000, 0xb5104770, 0xf903f000, 0x3efc7e09, 
+    0xb805f000, 0x0001ea80, 0x4000f000, 0xea804770, 0xf0000001, 0xf0004000, 0xf412b93a, 0xbf040f7f, 
+    0x47704802, 0x0001ea80, 0xb931f000, 0x7fc00000, 0x0e0b0041, 0x029ef1d3, 0xf450d908, 0xea4f0300, 
+    0xfa232303, 0xbf48f002, 0x47704240, 0xf000b510, 0xbf00f8d8, 0x80249249, 0x47702000, 0x4200f06f, 
+    0x0020ea82, 0x00004770, 0xf1d10dc1, 0xdb06029e, 0x2300ea4f, 0x4300f043, 0xf002fa23, 0x42004770, 
+    0xea4fd507, 0xf1b10140, 0xd2024ffe, 0x0000f04f, 0xb5104770, 0xf8b5f000, 0x80249249, 0x47702000, 
+    0x0020ea6f, 0x00004770, 0x4100f010, 0x4240bf48, 0xf380fab0, 0xf203fa10, 0x039df1c3, 0xea51d00b, 
+    0xeb0151c3, 0x06532012, 0x4770bf38, 0x0001f100, 0xf020bf08, 0x47700001, 0xf380fab0, 0xf203fa10, 
+    0x039df1c3, 0x05d9d00a, 0x2012eb01, 0xbf380653, 0xf1004770, 0xbf080001, 0x0001f020, 0x00004770, 
+    0x0c7ff44f, 0x12d0ea1c, 0xea1cbf1e, 0xea9213d1, 0xea930f0c, 0xf0000f0c, 0xea908047, 0xbf480f01, 
+    0x7280f442, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 0x0203eb02, 0x1301fba0, 0x0200f5a2, 0xbf182900, 
+    0x0301f043, 0xbf28005b, 0x0333ea4f, 0x4222eb42, 0x2c13ea5f, 0x50c2eb4c, 0xebbcbf2e, 0xf5b26f43, 
+    0x47700f7c, 0x6c03ea4f, 0x4f00f1bc, 0xf020bf08, 0xf5b20001, 0xbf380f7c, 0xd50b4770, 0x02fff082, 
+    0x3f80f512, 0x4770bfc8, 0x40c0f100, 0xf000bfd8, 0x47704000, 0x0c00f500, 0x0c4cea5f, 0x4770bf48, 
+    0x40c0f1b0, 0xb873f000, 0x0f01ea90, 0x13d1ea0c, 0xf442bf48, 0x45627280, 0x4563bf38, 0xea80d204, 
+    0xf0000001, 0x47704000, 0xf000b510, 0xbf00f81a, 0x3e010089, 0xb807f000, 0xb809f000, 0x0c41ea5f, 
+    0x6c1cea5f, 0xea80d008, 0xf0000001, 0xea5fb850, 0xea5f0c40, 0xd1f66c1c, 0x4000f04f, 0x0080f5a0, 
+    0xf10e4770, 0xf02e0e02, 0xf85e0e03, 0x42244b04, 0xea4fd404, 0xf1b20241, 0xd8114f7f, 0x0340ea4f, 
+    0x4f7ff1b3, 0xd10ed80c, 0x7cd0ea4f, 0x4f7ff1b2, 0x0c4ceb0c, 0x0c02f10c, 0xeb4cbf08, 0xe0047cd1, 
+    0x0c08f04f, 0xea4fe001, 0xeb0c7cd1, 0xfa24034c, 0xf004f403, 0xf1b40407, 0xd2060c04, 0x0c84eb0e, 
+    0x4010e8bd, 0x0c01f04c, 0xe8df4760, 0x0807f00c, 0xf04f0202, 0xf5a04000, 0xbd100080, 0x00424608, 
+    0xf1d2bf18, 0xbf887280, 0x4000f000, 0x21ffbd10, 0x50d0ea41, 0x477005c0, 0x0f01ea90, 0xf081bf48, 
+    0xf53f4100, 0x1a42ada2, 0xf082d804, 0xeba04200, 0x44110002, 0x52d0ea4f, 0x4c7ff04f, 0x0f41ea1c, 
+    0x53d1eba2, 0xea9cbf18, 0xd04a6f02, 0x4c00f04f, 0x2000ea4c, 0x2101ea4c, 0xfc03fa21, 0x0c0cebb0, 
+    0xf012d40f, 0xd0360ffe, 0x004cea5f, 0x1200d51d, 0x50c2eb40, 0x4770bf38, 0x0f3ff01c, 0x4770bf18, 
+    0xf1a2e00b, 0xea5f0201, 0xeb40201c, 0xbf3850c2, 0xf01c4770, 0xbf180f7f, 0xf1c34770, 0x40990320, 
+    0x1e40bf14, 0x0001f020, 0x08804770, 0x2312ea4f, 0x4770bf08, 0xfc80fab0, 0x020ceba2, 0x0c28f1cc, 
+    0xf00cfa60, 0x2f12ea93, 0xeb00bf04, 0x477050c2, 0x70c3ea4f, 0x0a134770, 0x10dcea5f, 0x4770bf08, 
+    0xea9ce7f6, 0xd0046f02, 0x0f5cea10, 0x2000bf08, 0xb5104770, 0xff45f7ff, 0x3ef6df40, 0x4000f081, 
+    0xf00c4770, 0x2b09030f, 0x2008bf08, 0x807ff000, 0xd00b2b0a, 0xbf182b08, 0xbf084770, 0x0f40f01c, 
+    0xf04fd00a, 0xf04f0000, 0x47700100, 0x0f40f01c, 0xf04fbf18, 0x47704000, 0x0f10f01c, 0xf020d008, 
+    0xf0004370, 0xea42427f, 0xea4f01d3, 0x47707043, 0x4060f000, 0x427ff021, 0x0200ea42, 0x407ff001, 
+    0x7072ea40, 0xf04f4770, 0xf44c0cff, 0xea1c6ce0, 0xbf1c5311, 0x0c03ea9c, 0xbfc24594, 0xeb0142da, 
+    0x47705102, 0xd00d2b00, 0x0f00f1bc, 0x2a00d00f, 0x4100f001, 0xf041bfa4, 0xf04141e0, 0xf04f617f, 
+    0x47700000, 0x4100f001, 0x0000f04f, 0xea504770, 0xf04f3301, 0xbf180c9b, 0x6c80f04c, 0xaf7cf47e, 
+    0xf04f4770, 0xea1202ff, 0xbf1c52d0, 0x03fff092, 0xbfc2428b, 0xeb0042d1, 0x477050c1, 0xd00a2a00, 
+    0xd00b2b00, 0xf0002900, 0xbfa44000, 0x40fef040, 0x0000f440, 0xf0004770, 0x47704000, 0xf04f0243, 
+    0xbf180c0b, 0x6c80f04c, 0xad0af47f, 0xf41c4770, 0xd0111f80, 0x2fe0f41c, 0xea6fd003, 0x004931cc, 
+    0xf04f4770, 0xf3ef5040, 0xf0228200, 0xea424270, 0xf3820200, 0x47708800, 0x0000f04f, 0xfb904770, 
+    0xfb02f2f1, 0x46100111, 0xfbb04770, 0xfb02f2f1, 0x46100111, 0x02004770, 0x03010604, 0x00160011, 
+    0x0020001b, 0x002a0025, 0x0034002f, 0x003c0039, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 
+    0xd0035190, 0xd0035192, 0xd0035194, 0xd0035196, 0x03020100, 0x08060504, 0x0d0c0b0a, 0x00100f0e, 
+    0x04030201, 0x0a080605, 0x0e0d0c0b, 0x0100100f, 0x05040302, 0x09080706, 0x0d0c0b0a, 0x0201000e, 
+    0x06050403, 0x0a090807, 0x0e0d0c0b, 0x00000000, 0x00000000, 0x00000001, 0x0000000f, 0x0000000f, 
+    0x0000000e, 0x00000003, 0x00000002, 0x00000002, 0x0000000b, 0x0000000c, 0x0000000d, 0x03020100, 
+    0x08060504, 0x0d0c0b0a, 0x00100f0e, 0x04030201, 0x0a080605, 0x0e0d0c0b, 0x0100100f, 0x05040302, 
+    0x09080706, 0x0d0c0b0a, 0x0000000e, 0x00040004, 0x00040004, 0x00000002, 0x000c000c, 0x000c000c, 
+    0x0000000d, 0x0000ffff, 0x00000000, 0xd0033070, 0xd0033270, 0xd0033470, 0xd0033670, 0x3f7d97f6, 
+    0x3f7b295f, 0x3f7b089a, 0x3f7d4fdf, 0x431170a4, 0xc2ba1eb8, 0xc3209eb8, 0x429bcccd, 0x3f76a7f0, 
+    0x3f730be1, 0x3f72f1aa, 0x3f756d5d, 0xc3a9b0a4, 0xc4001a3d, 0xc41b3b85, 0xc3b743d7, 0x3f80ded3, 
+    0x3f80a3d7, 0x3f805532, 0x3f80624e, 0xc2670000, 0xc1ec51ec, 0xc1aa0000, 0xc215f5c3, 0x3f79fbe7, 
+    0x3f79c0ec, 0x3f79d495, 0x3f7902de, 0xc3fee3d7, 0xc3eb63d7, 0xc3f8c8f6, 0xc3f02000, 0x00000000, 
+    0x00000000, 0x3ff00000, 0x00000000, 0x3ff80000, 0x00000000, 0x00000000, 0x40000000, 0x3fe2b803, 
+    0x00000000, 0x00000000, 0x43cfd006, 0x3e4cfdeb, 0x33333303, 0x3fe33333, 0xdb6fabff, 0x3fdb6db6, 
+    0x518f264d, 0x3fd55555, 0xa91d4101, 0x3fd17460, 0x93c9db65, 0x3fcd864a, 0x4a454eef, 0x3fca7e28, 
+    0x5555553e, 0x3fc55555, 0x16bebd93, 0xbf66c16c, 0xaf25de2c, 0x3f11566a, 0xc5d26bf1, 0xbebbbd41, 
+    0x72bea4d0, 0x3e663769, 0x00000000, 0x00000000, 0xc0c10000, 0x0140c181, 0x03c0c301, 0xc2410280, 
+    0x06c0c601, 0xc7410780, 0xc5c10500, 0x0440c481, 0x0cc0cc01, 0xcd410d80, 0xcfc10f00, 0x0e40ce81, 
+    0xcac10a00, 0x0b40cb81, 0x09c0c901, 0xc8410880, 0x18c0d801, 0xd9411980, 0xdbc11b00, 0x1a40da81, 
+    0xdec11e00, 0x1f40df81, 0x1dc0dd01, 0xdc411c80, 0xd4c11400, 0x1540d581, 0x17c0d701, 0xd6411680, 
+    0x12c0d201, 0xd3411380, 0xd1c11100, 0x1040d081, 0x30c0f001, 0xf1413180, 0xf3c13300, 0x3240f281, 
+    0xf6c13600, 0x3740f781, 0x35c0f501, 0xf4413480, 0xfcc13c00, 0x3d40fd81, 0x3fc0ff01, 0xfe413e80, 
+    0x3ac0fa01, 0xfb413b80, 0xf9c13900, 0x3840f881, 0xe8c12800, 0x2940e981, 0x2bc0eb01, 0xea412a80, 
+    0x2ec0ee01, 0xef412f80, 0xedc12d00, 0x2c40ec81, 0x24c0e401, 0xe5412580, 0xe7c12700, 0x2640e681, 
+    0xe2c12200, 0x2340e381, 0x21c0e101, 0xe0412080, 0x60c0a001, 0xa1416180, 0xa3c16300, 0x6240a281, 
+    0xa6c16600, 0x6740a781, 0x65c0a501, 0xa4416480, 0xacc16c00, 0x6d40ad81, 0x6fc0af01, 0xae416e80, 
+    0x6ac0aa01, 0xab416b80, 0xa9c16900, 0x6840a881, 0xb8c17800, 0x7940b981, 0x7bc0bb01, 0xba417a80, 
+    0x7ec0be01, 0xbf417f80, 0xbdc17d00, 0x7c40bc81, 0x74c0b401, 0xb5417580, 0xb7c17700, 0x7640b681, 
+    0xb2c17200, 0x7340b381, 0x71c0b101, 0xb0417080, 0x90c15000, 0x51409181, 0x53c09301, 0x92415280, 
+    0x56c09601, 0x97415780, 0x95c15500, 0x54409481, 0x5cc09c01, 0x9d415d80, 0x9fc15f00, 0x5e409e81, 
+    0x9ac15a00, 0x5b409b81, 0x59c09901, 0x98415880, 0x48c08801, 0x89414980, 0x8bc14b00, 0x4a408a81, 
+    0x8ec14e00, 0x4f408f81, 0x4dc08d01, 0x8c414c80, 0x84c14400, 0x45408581, 0x47c08701, 0x86414680, 
+    0x42c08201, 0x83414380, 0x81c14100, 0x40408081, 0x0002f150, 0x00032000, 0x00001044, 0x00000310, 
+    0x0002f9e4, 0x00047f70, 0x00000018, 0x0000036c, 0x0002f9fc, 0x00047ff0, 0x00000010, 0x0000036c, 
+    0x0002f9e4, 0x00033044, 0x0000d5d0, 0x00000388, 0x0002f9e4, 0x00040614, 0x00000060, 0x00000388, 
+    0x0002f9e4, 0x00047800, 0x00000490, 0x00000388, 0x00007fff, 0xfcdc7ff6, 0xf9b87fd9, 0xf6957fa7, 
+    0xf3747f62, 0xf0557f0a, 0xed387e9d, 0xea1e7e1e, 0xe7077d8a, 0xe3f47ce4, 0xe0e67c2a, 0xdddc7b5d, 
+    0xdad87a7d, 0xd7d9798a, 0xd4e17885, 0xd1ef776c, 0xcf047642, 0xcc217505, 0xc94673b6, 0xc6737255, 
+    0xc3a970e3, 0xc0e96f5f, 0xbe326dca, 0xbb856c24, 0xb8e36a6e, 0xb64c68a7, 0xb3c066d0, 0xb14064e9, 
+    0xaecc62f2, 0xac6560ec, 0xaa0a5ed7, 0xa7bd5cb4, 0xa57e5a82, 0xa34c5843, 0xa12955f6, 0x9f14539b, 
+    0x9d0e5134, 0x9b174ec0, 0x99304c40, 0x975949b4, 0x9592471d, 0x93dc447b, 0x923641ce, 0x90a13f17, 
+    0x8f1d3c57, 0x8dab398d, 0x8c4a36ba, 0x8afb33df, 0x89be30fc, 0x88942e11, 0x877b2b1f, 0x86762827, 
+    0x85832528, 0x84a32224, 0x83d61f1a, 0x831c1c0c, 0x827618f9, 0x81e215e2, 0x816312c8, 0x80f60fab, 
+    0x809e0c8c, 0x8059096b, 0x80270648, 0x800a0324, 0x80000000, 0x800afcdc, 0x8027f9b8, 0x8059f695, 
+    0x809ef374, 0x80f6f055, 0x8163ed38, 0x81e2ea1e, 0x8276e707, 0x831ce3f4, 0x83d6e0e6, 0x84a3dddc, 
+    0x8583dad8, 0x8676d7d9, 0x877bd4e1, 0x8894d1ef, 0x89becf04, 0x8afbcc21, 0x8c4ac946, 0x8dabc673, 
+    0x8f1dc3a9, 0x90a1c0e9, 0x9236be32, 0x93dcbb85, 0x9592b8e3, 0x9759b64c, 0x9930b3c0, 0x9b17b140, 
+    0x9d0eaecc, 0x9f14ac65, 0xa129aa0a, 0xa34ca7bd, 0xa57ea57e, 0xa7bda34c, 0xaa0aa129, 0xac659f14, 
+    0xaecc9d0e, 0xb1409b17, 0xb3c09930, 0xb64c9759, 0xb8e39592, 0xbb8593dc, 0xbe329236, 0xc0e990a1, 
+    0xc3a98f1d, 0xc6738dab, 0xc9468c4a, 0xcc218afb, 0xcf0489be, 0xd1ef8894, 0xd4e1877b, 0xd7d98676, 
+    0xdad88583, 0xdddc84a3, 0xe0e683d6, 0xe3f4831c, 0xe7078276, 0xea1e81e2, 0xed388163, 0xf05580f6, 
+    0xf374809e, 0xf6958059, 0xf9b88027, 0xfcdc800a, 0x00008000, 0x0324800a, 0x06488027, 0x096b8059, 
+    0x0c8c809e, 0x0fab80f6, 0x12c88163, 0x15e281e2, 0x18f98276, 0x1c0c831c, 0x1f1a83d6, 0x222484a3, 
+    0x25288583, 0x28278676, 0x2b1f877b, 0x2e118894, 0x30fc89be, 0x33df8afb, 0x36ba8c4a, 0x398d8dab, 
+    0x3c578f1d, 0x3f1790a1, 0x41ce9236, 0x447b93dc, 0x471d9592, 0x49b49759, 0x4c409930, 0x4ec09b17, 
+    0x51349d0e, 0x539b9f14, 0x55f6a129, 0x5843a34c, 0x5a82a57e, 0x5cb4a7bd, 0x5ed7aa0a, 0x60ecac65, 
+    0x62f2aecc, 0x64e9b140, 0x66d0b3c0, 0x68a7b64c, 0x6a6eb8e3, 0x6c24bb85, 0x6dcabe32, 0x6f5fc0e9, 
+    0x70e3c3a9, 0x7255c673, 0x73b6c946, 0x7505cc21, 0x7642cf04, 0x776cd1ef, 0x7885d4e1, 0x798ad7d9, 
+    0x7a7ddad8, 0x7b5ddddc, 0x7c2ae0e6, 0x7ce4e3f4, 0x7d8ae707, 0x7e1eea1e, 0x7e9ded38, 0x7f0af055, 
+    0x7f62f374, 0x7fa7f695, 0x7fd9f9b8, 0x7ff6fcdc, 0x7fff0000, 0x7ff60324, 0x7fd90648, 0x7fa7096b, 
+    0x7f620c8c, 0x7f0a0fab, 0x7e9d12c8, 0x7e1e15e2, 0x7d8a18f9, 0x7ce41c0c, 0x7c2a1f1a, 0x7b5d2224, 
+    0x7a7d2528, 0x798a2827, 0x78852b1f, 0x776c2e11, 0x764230fc, 0x750533df, 0x73b636ba, 0x7255398d, 
+    0x70e33c57, 0x6f5f3f17, 0x6dca41ce, 0x6c24447b, 0x6a6e471d, 0x68a749b4, 0x66d04c40, 0x64e94ec0, 
+    0x62f25134, 0x60ec539b, 0x5ed755f6, 0x5cb45843, 0x5a825a82, 0x58435cb4, 0x55f65ed7, 0x539b60ec, 
+    0x513462f2, 0x4ec064e9, 0x4c4066d0, 0x49b468a7, 0x471d6a6e, 0x447b6c24, 0x41ce6dca, 0x3f176f5f, 
+    0x3c5770e3, 0x398d7255, 0x36ba73b6, 0x33df7505, 0x30fc7642, 0x2e11776c, 0x2b1f7885, 0x2827798a, 
+    0x25287a7d, 0x22247b5d, 0x1f1a7c2a, 0x1c0c7ce4, 0x18f97d8a, 0x15e27e1e, 0x12c87e9d, 0x0fab7f0a, 
+    0x0c8c7f62, 0x096b7fa7, 0x06487fd9, 0x03247ff6, 0x00007fff, 0xfe6e7ffe, 0xfcdc7ff6, 0xfb4a7fea, 
+    0xf9b87fd9, 0xf8277fc2, 0xf6957fa7, 0xf5057f87, 0xf3747f62, 0xf1e47f38, 0xf0557f0a, 0xeec67ed6, 
+    0xed387e9d, 0xebab7e60, 0xea1e7e1e, 0xe8927dd6, 0xe7077d8a, 0xe57d7d3a, 0xe3f47ce4, 0xe26d7c89, 
+    0xe0e67c2a, 0xdf617bc6, 0xdddc7b5d, 0xdc597aef, 0xdad87a7d, 0xd9587a06, 0xd7d9798a, 0xd65c790a, 
+    0xd4e17885, 0xd36777fb, 0xd1ef776c, 0xd07976d9, 0xcf047642, 0xcd9275a6, 0xcc217505, 0xcab27460, 
+    0xc94673b6, 0xc7db7308, 0xc6737255, 0xc50d719e, 0xc3a970e3, 0xc2487023, 0xc0e96f5f, 0xbf8c6e97, 
+    0xbe326dca, 0xbcda6cf9, 0xbb856c24, 0xba336b4b, 0xb8e36a6e, 0xb796698c, 0xb64c68a7, 0xb50567bd, 
+    0xb3c066d0, 0xb27f65de, 0xb14064e9, 0xb00563ef, 0xaecc62f2, 0xad9761f1, 0xac6560ec, 0xab365fe4, 
+    0xaa0a5ed7, 0xa8e25dc8, 0xa7bd5cb4, 0xa69c5b9d, 0xa57e5a82, 0xa4635964, 0xa34c5843, 0xa238571e, 
+    0xa12955f6, 0xa01c54ca, 0x9f14539b, 0x9e0f5269, 0x9d0e5134, 0x9c114ffb, 0x9b174ec0, 0x9a224d81, 
+    0x99304c40, 0x98434afb, 0x975949b4, 0x9674486a, 0x9592471d, 0x94b545cd, 0x93dc447b, 0x93074326, 
+    0x923641ce, 0x91694074, 0x90a13f17, 0x8fdd3db8, 0x8f1d3c57, 0x8e623af3, 0x8dab398d, 0x8cf83825, 
+    0x8c4a36ba, 0x8ba0354e, 0x8afb33df, 0x8a5a326e, 0x89be30fc, 0x89272f87, 0x88942e11, 0x88052c99, 
+    0x877b2b1f, 0x86f629a4, 0x86762827, 0x85fa26a8, 0x85832528, 0x851123a7, 0x84a32224, 0x843a209f, 
+    0x83d61f1a, 0x83771d93, 0x831c1c0c, 0x82c61a83, 0x827618f9, 0x822a176e, 0x81e215e2, 0x81a01455, 
+    0x816312c8, 0x812a113a, 0x80f60fab, 0x80c80e1c, 0x809e0c8c, 0x80790afb, 0x8059096b, 0x803e07d9, 
+    0x80270648, 0x801604b6, 0x800a0324, 0x80020192, 0x80000000, 0x8002fe6e, 0x800afcdc, 0x8016fb4a, 
+    0x8027f9b8, 0x803ef827, 0x8059f695, 0x8079f505, 0x809ef374, 0x80c8f1e4, 0x80f6f055, 0x812aeec6, 
+    0x8163ed38, 0x81a0ebab, 0x81e2ea1e, 0x822ae892, 0x8276e707, 0x82c6e57d, 0x831ce3f4, 0x8377e26d, 
+    0x83d6e0e6, 0x843adf61, 0x84a3dddc, 0x8511dc59, 0x8583dad8, 0x85fad958, 0x8676d7d9, 0x86f6d65c, 
+    0x877bd4e1, 0x8805d367, 0x8894d1ef, 0x8927d079, 0x89becf04, 0x8a5acd92, 0x8afbcc21, 0x8ba0cab2, 
+    0x8c4ac946, 0x8cf8c7db, 0x8dabc673, 0x8e62c50d, 0x8f1dc3a9, 0x8fddc248, 0x90a1c0e9, 0x9169bf8c, 
+    0x9236be32, 0x9307bcda, 0x93dcbb85, 0x94b5ba33, 0x9592b8e3, 0x9674b796, 0x9759b64c, 0x9843b505, 
+    0x9930b3c0, 0x9a22b27f, 0x9b17b140, 0x9c11b005, 0x9d0eaecc, 0x9e0fad97, 0x9f14ac65, 0xa01cab36, 
+    0xa129aa0a, 0xa238a8e2, 0xa34ca7bd, 0xa463a69c, 0xa57ea57e, 0xa69ca463, 0xa7bda34c, 0xa8e2a238, 
+    0xaa0aa129, 0xab36a01c, 0xac659f14, 0xad979e0f, 0xaecc9d0e, 0xb0059c11, 0xb1409b17, 0xb27f9a22, 
+    0xb3c09930, 0xb5059843, 0xb64c9759, 0xb7969674, 0xb8e39592, 0xba3394b5, 0xbb8593dc, 0xbcda9307, 
+    0xbe329236, 0xbf8c9169, 0xc0e990a1, 0xc2488fdd, 0xc3a98f1d, 0xc50d8e62, 0xc6738dab, 0xc7db8cf8, 
+    0xc9468c4a, 0xcab28ba0, 0xcc218afb, 0xcd928a5a, 0xcf0489be, 0xd0798927, 0xd1ef8894, 0xd3678805, 
+    0xd4e1877b, 0xd65c86f6, 0xd7d98676, 0xd95885fa, 0xdad88583, 0xdc598511, 0xdddc84a3, 0xdf61843a, 
+    0xe0e683d6, 0xe26d8377, 0xe3f4831c, 0xe57d82c6, 0xe7078276, 0xe892822a, 0xea1e81e2, 0xebab81a0, 
+    0xed388163, 0xeec6812a, 0xf05580f6, 0xf1e480c8, 0xf374809e, 0xf5058079, 0xf6958059, 0xf827803e, 
+    0xf9b88027, 0xfb4a8016, 0xfcdc800a, 0xfe6e8002, 0x00008000, 0x01928002, 0x0324800a, 0x04b68016, 
+    0x06488027, 0x07d9803e, 0x096b8059, 0x0afb8079, 0x0c8c809e, 0x0e1c80c8, 0x0fab80f6, 0x113a812a, 
+    0x12c88163, 0x145581a0, 0x15e281e2, 0x176e822a, 0x18f98276, 0x1a8382c6, 0x1c0c831c, 0x1d938377, 
+    0x1f1a83d6, 0x209f843a, 0x222484a3, 0x23a78511, 0x25288583, 0x26a885fa, 0x28278676, 0x29a486f6, 
+    0x2b1f877b, 0x2c998805, 0x2e118894, 0x2f878927, 0x30fc89be, 0x326e8a5a, 0x33df8afb, 0x354e8ba0, 
+    0x36ba8c4a, 0x38258cf8, 0x398d8dab, 0x3af38e62, 0x3c578f1d, 0x3db88fdd, 0x3f1790a1, 0x40749169, 
+    0x41ce9236, 0x43269307, 0x447b93dc, 0x45cd94b5, 0x471d9592, 0x486a9674, 0x49b49759, 0x4afb9843, 
+    0x4c409930, 0x4d819a22, 0x4ec09b17, 0x4ffb9c11, 0x51349d0e, 0x52699e0f, 0x539b9f14, 0x54caa01c, 
+    0x55f6a129, 0x571ea238, 0x5843a34c, 0x5964a463, 0x5a82a57e, 0x5b9da69c, 0x5cb4a7bd, 0x5dc8a8e2, 
+    0x5ed7aa0a, 0x5fe4ab36, 0x60ecac65, 0x61f1ad97, 0x62f2aecc, 0x63efb005, 0x64e9b140, 0x65deb27f, 
+    0x66d0b3c0, 0x67bdb505, 0x68a7b64c, 0x698cb796, 0x6a6eb8e3, 0x6b4bba33, 0x6c24bb85, 0x6cf9bcda, 
+    0x6dcabe32, 0x6e97bf8c, 0x6f5fc0e9, 0x7023c248, 0x70e3c3a9, 0x719ec50d, 0x7255c673, 0x7308c7db, 
+    0x73b6c946, 0x7460cab2, 0x7505cc21, 0x75a6cd92, 0x7642cf04, 0x76d9d079, 0x776cd1ef, 0x77fbd367, 
+    0x7885d4e1, 0x790ad65c, 0x798ad7d9, 0x7a06d958, 0x7a7ddad8, 0x7aefdc59, 0x7b5ddddc, 0x7bc6df61, 
+    0x7c2ae0e6, 0x7c89e26d, 0x7ce4e3f4, 0x7d3ae57d, 0x7d8ae707, 0x7dd6e892, 0x7e1eea1e, 0x7e60ebab, 
+    0x7e9ded38, 0x7ed6eec6, 0x7f0af055, 0x7f38f1e4, 0x7f62f374, 0x7f87f505, 0x7fa7f695, 0x7fc2f827, 
+    0x7fd9f9b8, 0x7feafb4a, 0x7ff6fcdc, 0x7ffefe6e, 0x7fff0000, 0x7ffe0192, 0x7ff60324, 0x7fea04b6, 
+    0x7fd90648, 0x7fc207d9, 0x7fa7096b, 0x7f870afb, 0x7f620c8c, 0x7f380e1c, 0x7f0a0fab, 0x7ed6113a, 
+    0x7e9d12c8, 0x7e601455, 0x7e1e15e2, 0x7dd6176e, 0x7d8a18f9, 0x7d3a1a83, 0x7ce41c0c, 0x7c891d93, 
+    0x7c2a1f1a, 0x7bc6209f, 0x7b5d2224, 0x7aef23a7, 0x7a7d2528, 0x7a0626a8, 0x798a2827, 0x790a29a4, 
+    0x78852b1f, 0x77fb2c99, 0x776c2e11, 0x76d92f87, 0x764230fc, 0x75a6326e, 0x750533df, 0x7460354e, 
+    0x73b636ba, 0x73083825, 0x7255398d, 0x719e3af3, 0x70e33c57, 0x70233db8, 0x6f5f3f17, 0x6e974074, 
+    0x6dca41ce, 0x6cf94326, 0x6c24447b, 0x6b4b45cd, 0x6a6e471d, 0x698c486a, 0x68a749b4, 0x67bd4afb, 
+    0x66d04c40, 0x65de4d81, 0x64e94ec0, 0x63ef4ffb, 0x62f25134, 0x61f15269, 0x60ec539b, 0x5fe454ca, 
+    0x5ed755f6, 0x5dc8571e, 0x5cb45843, 0x5b9d5964, 0x5a825a82, 0x59645b9d, 0x58435cb4, 0x571e5dc8, 
+    0x55f65ed7, 0x54ca5fe4, 0x539b60ec, 0x526961f1, 0x513462f2, 0x4ffb63ef, 0x4ec064e9, 0x4d8165de, 
+    0x4c4066d0, 0x4afb67bd, 0x49b468a7, 0x486a698c, 0x471d6a6e, 0x45cd6b4b, 0x447b6c24, 0x43266cf9, 
+    0x41ce6dca, 0x40746e97, 0x3f176f5f, 0x3db87023, 0x3c5770e3, 0x3af3719e, 0x398d7255, 0x38257308, 
+    0x36ba73b6, 0x354e7460, 0x33df7505, 0x326e75a6, 0x30fc7642, 0x2f8776d9, 0x2e11776c, 0x2c9977fb, 
+    0x2b1f7885, 0x29a4790a, 0x2827798a, 0x26a87a06, 0x25287a7d, 0x23a77aef, 0x22247b5d, 0x209f7bc6, 
+    0x1f1a7c2a, 0x1d937c89, 0x1c0c7ce4, 0x1a837d3a, 0x18f97d8a, 0x176e7dd6, 0x15e27e1e, 0x14557e60, 
+    0x12c87e9d, 0x113a7ed6, 0x0fab7f0a, 0x0e1c7f38, 0x0c8c7f62, 0x0afb7f87, 0x096b7fa7, 0x07d97fc2, 
+    0x06487fd9, 0x04b67fea, 0x03247ff6, 0x01927ffe, 0x50102000, 0x68284808, 0x64244404, 0x74345414, 
+    0x62224202, 0x72325212, 0x6a2a4a0a, 0x7a3a5a1a, 0x61214101, 0x71315111, 0x69294909, 0x79395919, 
+    0x65254505, 0x75355515, 0x6d2d4d0d, 0x7d3d5d1d, 0xffff1603, 0x412380f2, 0x04611a07, 0x1a04255a, 
+    0x8f1a0479, 0x04a11a04, 0x1a04cb1a, 0x692304ef, 0x04df1a08, 0x2409234b, 0x1a08d91a, 0x032304f1, 
+    0x04151a0a, 0x2304411a, 0x1d2332e9, 0x0c8d1a33, 0x1a0b1323, 0xe11a04c3, 0x04ff1a04, 0x1a0c3323, 
+    0x23230445, 0x0e8b230d, 0x1a04ab1a, 0x731b04f7, 0x04196c0f, 0x1a04ab1a, 0x091b04d7, 0x04196011, 
+    0x232dab23, 0x831a2e67, 0x1a702904, 0x611a1c4f, 0x1c4d1a04, 0x23127523, 0x471a131b, 0x04811a04, 
+    0x4c14751b, 0x0d230419, 0x04351a15, 0x1a04611a, 0xbb230489, 0x19652318, 0x1a449f1a, 0xa12304d1, 
+    0x04bf1a31, 0x1a04db1a, 0xff1a04ef, 0xb4691a04, 0x231ce11a, 0xb71a2f79, 0x04c91a34, 0x2304db1a, 
+    0x591a1737, 0x04751acc, 0x1a04911a, 0xb11a04a1, 0x04c11a04, 0x04a99029, 0x1a14d11a, 0x211b04f9, 
+    0x0419e434, 0x046920e9, 0x9a1c651a, 0x29232081, 0x1c171b1b, 0x1a081934, 0x16090477, 0x04120938, 
+    0x1a30a91a, 0xf91a04d9, 0x20fb2304, 0x2304df1a, 0x671a1a39, 0x1de32350, 0x281e014b, 0x1a08591a, 
+    0x8d1a1c7d, 0x049d1a04, 0x1104bd1a, 0x1a048023, 0xd01a04c0, 0x04f01a04, 0x82103231, 0x1affb201, 
+    0x5a710104, 0x12010101, 0x8101ff3a, 0x01122169, 0x03013203, 0x48697c92, 0x01999a2b, 0x333fa93c, 
+    0x3fd3d301, 0x7c492519, 0x69971109, 0x292301b6, 0x12087244, 0x5a225207, 0x38810402, 0x8ce70410, 
+    0xae0ded28, 0x8ef34d3f, 0xf4247453, 0x1be16988, 0x6266ffff, 0x01486907, 0x1f1d01ff, 0x07ff3fff, 
+    0x3a0203ff, 0x1b110201, 0x1a0c0fff, 0x03e20a0f, 0x8101011a, 0xaeae5a03, 0x44016579, 0xda238022, 
+    0x1a190814, 0xffffd475, 0xffffe80d, 0xfffff580, 0xfffffb0b, 0xfffffe74, 0xffffffa2, 0x38851a38, 
+    0xc75c1218, 0xe6caffff, 0xf8ceffff, 0xfdb2ffff, 0x9d4affff, 0x1a021c23, 0x4f1a04e6, 0x483b1a04, 
+    0xbb1a38e9, 0xcf2b1e2c, 0x684effff, 0x2304be1a, 0x5e1a0479, 0x40361a38, 0x1a34641a, 0xf8327894, 
+    0x1a18ae1a, 0x9b192055, 0x2338ff2a, 0x0a18082a, 0xffffc868, 0xfffff10e, 0xe41a14b4, 0x244a1a2c, 
+    0x1e3c581a, 0xfffffacf, 0x1d2340ed, 0x18b81a03, 0x2a0cc01a, 0x38197cd1, 0x18160423, 0xfff6b70a, 
+    0xfff499ff, 0x367c42ff, 0xfffffc7d, 0x28561ad0, 0x1a30971a, 0x781a44c5, 0x0cc31a04, 0x1a4cd41a, 
+    0x3829183e, 0x1e400a1a, 0xffffcc92, 0x22111871, 0x3c6a1a09, 0xfff92527, 0x1a11a3ff, 0xa91e3077, 
+    0xb7fffff7, 0x0b1c231c, 0x1a38ef1a, 0x3829acc1, 0x181a8f23, 0xffd0490e, 0xffe845ff, 0xfff578ff, 
+    0x1a7cf9ff, 0x341ab0e0, 0x28351ac0, 0xeb1a9732, 0x196dc238, 0x3e342338, 0xe5ab0a18, 0xd3afffff, 
+    0x3cbaffff, 0x1a60181a, 0xcf1a549b, 0x8c2e1acc, 0x1ab8bd1a, 0x501a0cf2, 0x04f81a44, 0x23e0165a, 
+    0x0a180e94, 0xffffd232, 0xfffff25e, 0x091aa0fe, 0x28281a18, 0x3d328a32, 0x1a7c361a, 0x791a3cc9, 
+    0x1ac63204, 0x18413c69, 0x7154c721, 0xb8aa63e7, 0xdc553173, 0xee2a9839, 0x77154c1c, 0x3b8aa60e, 
+    0x9dc55307, 0xcee2a983, 0x601a1fc1, 0x1fb01a1f, 0x1a1f581a, 0x22181fac, 0x766f4d56, 0x3b37a64c, 
+    0x1d9bd3a6, 0x8ecde953, 0xc766f4a9, 0x63b37a54, 0x31d9bdaa, 0x98ecde55, 0x151a1f2a, 0x1f8a1a1f, 
+    0x1a1fc51a, 0x711a1fe2, 0x1fb81a1f, 0x1a1fdc1a, 0x771a1fee, 0x1f3b1a1f, 0x521f9d1a, 0x010113ce, 
+    0x07490239, 0x0d291029, 0x05390a19, 0x0d202811, 0x06f6d9c4, 0x037b6ce2, 0x81bdb671, 0x40dedb38, 
+    0x206f6d9c, 0x1037b6ce, 0x881bdb67, 0x1a1fedb3, 0xc31a1f86, 0x1f611a1f, 0x1a1fb01a, 0x2c1a1f58, 
+    0x1f961a1f, 0x1a1fcb1a, 0x721a1fe5, 0x1f392a1f, 0xab601618, 0xd5b03881, 0x6ad89c40, 0x356cce20, 
+    0x1ab66710, 0x465bb388, 0x1a65ad1a, 0x1f196556, 0x1a1fdb1a, 0xb61a1f6d, 0x1fdb1a1f, 0x699ded2a, 
+    0x499c79aa, 0x29ac39b3, 0x250d181e, 0x12421084, 0x09210842, 0x0b108421, 0x1a0b081a, 0x421a0b84, 
+    0x0b211a0b, 0x041a1469, 0x0b021a0b, 0x1114011a, 0x94a12018, 0x4a504252, 0xa5282129, 0x52941094, 
+    0x294a084a, 0x94a58425, 0x4a524212, 0xa5292109, 0x421a1484, 0x14211a14, 0x1b14101a, 0x1a1f2108, 
+    0x081a1f10, 0x1f841a1f, 0x1a1f421a, 0x101a1f21, 0x1f081a1f, 0xc1a4842a, 0x05c9b649, 0x1a2c801a, 
+    0x100a2c40, 0xb0a99c20, 0x1a0b901a, 0xa41a0b48, 0x14521a14, 0x1a14291a, 0x4a1a1494, 0x1fa51a14, 
+    0x481a1419, 0x94a41414, 0x42101404, 0x21081402, 0x10842301, 0x19084223, 0x11651988, 0x19116519, 
+    0x1a1f1965, 0x841a1f08, 0x1f421a1f, 0x6a1f211a, 0x019a8e10, 0x01a5b905, 0x100a1813, 0x0f100f0e, 
+    0x10011010, 0x39353904, 0x143a0101, 0x1c01ffff, 0x0802fffe, 0xfd144e29, 0xfb1a04ff, 0xfffe1604, 
+    0x1406ffff, 0x1c0dfff6, 0x0e09fff3, 0x11fff914, 0x1dffe714, 0x0fffe614, 0xea140212, 0xc8142aff, 
+    0xd2143aff, 0x111214ff, 0x5effc514, 0x6dff8f14, 0x121cb51a, 0xff6f143f, 0xff1014d3, 0xff8116d8, 
+    0x10ecffe5, 0xdcfe1f18, 0x69fc4202, 0xc4fb3c04, 0xbefb9704, 0xe1fd2403, 0x1bff1401, 0x28147f12, 
+    0x2d14f0ff, 0xc11691ff, 0x4bfff1ff, 0x71ff9314, 0x3bffa214, 0xecffef16, 0xc6142eff, 0xd61c38ff, 
+    0x147816ff, 0x1c1afff1, 0x1819ffe3, 0x3a78071a, 0x0a1290f7, 0x12b4fa1a, 0xfffc1c02, 0x035a0405, 
+    0x02c449ba, 0x1b10011b, 0x20131e48, 0x23fd21fa, 0x2862261f, 0x2d4f2ac6, 0x32d62ffe, 0x390a35d9, 
+    0x20283c6b, 0xcf43cb40, 0x924c1047, 0x67555850, 0x6f5fc25a, 0xcf6b7265, 0xb2788e71, 0x4787437f, 
+    0x0297c58f, 0x3fff1010, 0x01d5024d, 0x015e0197, 0x01090136, 0xff2018f0, 0x52029a3f, 0xb4020902, 
+    0x58018b01, 0xff013a01, 0xaf02fb3f, 0x21026602, 0x9301e602, 0x1c106f01, 0x1ce90237, 0x01620818, 
+    0x012d0157, 0x0e1e1006, 0x8601da02, 0x01511c2c, 0x1018422e, 0x028b3fff, 0x01ef0242, 0x017f01a4, 
+    0x10270150, 0x183c651a, 0x9e01d90a, 0x4b017b01, 0x18102a01, 0x9202e80e, 0xf8024f02, 0x9d01c901, 
+    0x15106001, 0x0131016b, 0x12dd0113, 0x1ab612c2, 0x0a1880a0, 0x01cc022f, 0x013f01bd, 0xd21a4e08, 
+    0x02081e10, 0x8a9a01ab, 0x3202061a, 0x122312d1, 0x1237122d, 0x124b1241, 0x5f110255, 0x8002dd16, 
+    0x1b001e01, 0x5eff7d10, 0x78ff71ff, 0x6aff6bff, 0x93ff80ff, 0x66ff81ff, 0xa3ff73ff, 0xfaffdfff, 
+    0x2b0112ff, 0x1a3c1909, 0x086901ff, 0x0a961902, 0x176f012c, 0x6503ffff, 0x74230102, 0x23302348, 
+    0x23157c23, 0x1e230ed8, 0x08c9230b, 0x23073c23, 0x4e23061a, 0x04b32305, 0x23043e1a, 0x8d1a03db, 
+    0x044f1a04, 0x2304231a, 0xd51a02f4, 0x04b91a04, 0x1a049c1a, 0x781a0489, 0x04691a04, 0x1a04611a, 
+    0x4d1a045b, 0x044e1a04, 0x1a044b1a, 0x461a0441, 0x04441a04, 0x5a08405a, 0x581a044c, 0x04631a04, 
+    0x1a04711a, 0x8c1a0483, 0x04931a04, 0x29609a5a, 0x04b81a04, 0x1a04c71a, 0xef1a04d3, 0x04f91a04, 
+    0x1a880a1a, 0x481a0425, 0x04541a04, 0x1a04831a, 0xb71a04a6, 0x04df1a04, 0x1a04fd1a, 0x541abc1b, 
+    0x04711a04, 0x1a04a31a, 0xf41a04d0, 0xdc1f1a04, 0x1a045d1a, 0xdc1a0493, 0xf02a1a04, 0x1a047f1a, 
+    0x472304e9, 0x04a01a07, 0x2304f91a, 0xc41a085a, 0x09252304, 0x23049e1a, 0xc21a0a1b, 0x0b592304, 
+    0x2304ce1a, 0x4f230c7e, 0x0e3d230d, 0x230f3223, 0x6c231026, 0x128f2311, 0x2313e023, 0x9c231542, 
+    0x17af1b16, 0x2c191a40, 0xa7231b22, 0x1ea9231c, 0x23212723, 0x2c232365, 0x29372326, 0x232c1823, 
+    0x38232ea5, 0x36042332, 0x23393923, 0x3c1b3e4c, 0x4722c042, 0x234acc23, 0x68235075, 0x5b032355, 
+    0x1b610223, 0x22cc6497, 0x70fb236b, 0x23778e23, 0xb01b7dd8, 0x871a7c83, 0x238e22a8, 0xe52391ab, 
+    0x98d92397, 0x239e1423, 0xddf39f72, 0xfdfdc49d, 0x256f02fd, 0x03ff1b02, 0x3c270f3a, 0x040283af, 
+    0x8104c31a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 
+    0x00000000, 0x0004c000, 0xffffffff, 0xe594f000, 0x02388175, 0x38e5566b, 0x58123170, 0xcb7212d0, 
+    0xe0600090, 0x5411e030, 0x0090f0fe, 0xf004e067, 0x00900670, 0xf004e066, 0xe0660090, 0xa30cffb4, 
+    0x07ffb4e0, 0x167ffde4, 0xe4b93112, 0x11f510f5, 0xe0830490, 0x1e7ff0a3, 0x8e807412, 0xe50f8f0e, 
+    0x1313130e, 0x04901f54, 0x54eff083, 0xe5117010, 0xce05780f, 0x13ce13c3, 0x3f54f9d8, 0x3b0a12ff, 
+    0xe0110490, 0x01642f60, 0x0a020370, 0x1104903a, 0x0302b4e0, 0x90843a02, 0xb4e01104, 0x35020303, 
+    0x11049060, 0x0304b4e0, 0x90ce1102, 0xb4e01104, 0x4f020305, 0x0490e40b, 0x0490f048, 0x13c3e000, 
+    0x2013e0a3, 0x04905fe0, 0x13c3e000, 0x9056e030, 0xd3e08304, 0x4d400394, 0xe0890490, 0x1a7f4760, 
+    0xefb37412, 0x3d700154, 0xa8dd6212, 0xaa05a904, 0xff74c306, 0x740df59f, 0x0cf59aff, 0xf599ff74, 
+    0x98ff740b, 0x607f0af5, 0xff7dea7e, 0x0dabff7c, 0x0ba90caa, 0x2612c3f8, 0x7d0a4018, 0x121e7f02, 
+    0x0402b931, 0x840490c9, 0x900d70e0, 0x60e08304, 0x7f027d07, 0xb9311203, 0xe0830490, 0x02037014, 
+    0x60044403, 0x10040203, 0xe0840490, 0x027d0760, 0x3112017f, 0x12897fb9, 0x54efb374, 0xff13c307, 
+    0x041c6014, 0x02020360, 0x3f0490a8, 0x120360e0, 0xa575e171, 0xffa67510, 0x75efa775, 0x7d22109a, 
+    0x12d17f18, 0x13efa774, 0x703f5413, 0x04a4751d, 0x7503a675, 0x9e75ffa7, 0x189c75d1, 0x007e0d7f, 
+    0x007c007d, 0x02a36b12, 0x187dcb73, 0x7412d17f, 0x1313efa7, 0x01643f54, 0x74121870, 0x0370ef9f, 
+    0x753a0a02, 0xa67550a4, 0xffa77503, 0x75d19e75, 0x867f189c, 0xefb37412, 0x09f50154, 0x74121a60, 
+    0x3c0490bf, 0x01e030e0, 0xa4f5e422, 0x75fea675, 0x9a75ffa7, 0x0a721286, 0x7502a475, 0xa775fda6, 
+    0x859a75ff, 0x90e17112, 0x30e00104, 0x6d1203e0, 0x128b7f90, 0x54efb374, 0x000e750f, 0x967d0ff5, 
+    0x7412ffe4, 0x0354efa7, 0xf07513c3, 0xf0aea410, 0x42ee0f42, 0x7d0faf0e, 0xba3d1202, 0x12000490, 
+    0x3d12b63d, 0x7f027db2, 0xb9311202, 0x90af2112, 0xc3e00004, 0x13e0a313, 0x9023e020, 0x60e08904, 
+    0x01a4751d, 0x75fea675, 0x9a75ffa7, 0xd0a47563, 0x7503a675, 0x9e75ffa7, 0x189c75d1, 0xa4751b80, 
+    0x03a67550, 0x75ffa775, 0x9c75d19e, 0xa4f5e418, 0x75fea675, 0x9a75ffa7, 0x01a47563, 0x75fea675, 
+    0x9a75ffa7, 0x10a57585, 0x75ffa675, 0x9a75efa7, 0x0b049010, 0x22f004e0, 0xe03f0490, 0x71120360, 
+    0x480490e1, 0x7ff00174, 0xb37412f6, 0xf50154ef, 0x12f87f09, 0x54efb374, 0x6413c307, 0x75527001, 
+    0xa67502a4, 0xffa775fd, 0xe4f59a75, 0xf0640090, 0xe0500090, 0x12017dff, 0x0090ba3d, 0xffe0a350, 
+    0x3d12017d, 0x7ffde4ba, 0xb9311205, 0x036009e5, 0x12c27412, 0x0090ef72, 0xe030e051, 0xbe741203, 
+    0x753c6412, 0xa67501a4, 0xffa775fe, 0x80f59a75, 0x6400900f, 0x040970e0, 0x7ffde4f0, 0xb9311204, 
+    0x037009e5, 0xe43a0a02, 0xa675a4f5, 0xffa775fe, 0x22f69a75, 0xe03f0490, 0x04905f60, 0x0670e002, 
+    0xe03e0490, 0x71125370, 0x000490e1, 0xa313c3e0, 0xe02013e0, 0xe4967d3b, 0xa77412ff, 0xc30354ef, 
+    0x752d6013, 0xa67501a4, 0xffa775fe, 0x75d19e75, 0xa475179c, 0xfea67501, 0xe4ffa775, 0x9c759ef5, 
+    0xa4f5e496, 0x75fea675, 0x9e75ffa7, 0x179c75d1, 0xe03d0490, 0x80f00144, 0x0490e405, 0xa575f040, 
+    0xffa67520, 0x75dfa775, 0x1e7f109a, 0xefae7412, 0x54131313, 0x6001641f, 0x0a04901f, 0x7ff004e0, 
+    0xb374121d, 0x750754ef, 0x0ff5000e, 0x12027dff, 0x027dba3d, 0x1f80077f, 0xe0840490, 0x1a600164, 
+    0x74121d7f, 0x0754efb3, 0xf5000e75, 0x027dff0f, 0x7dba3d12, 0x12067f02, 0x0490b931, 0x8b050248, 
+    0xe0830490, 0x1f700264, 0xe0400490, 0x04901960, 0xf001743f, 0x027f027d, 0x7dba3d12, 0x12157f02, 
+    0x0080b931, 0x90c90402, 0xb4e04004, 0x76500025, 0xf8470490, 0x02732828, 0x0502d604, 0xd1090280, 
+    0x02a40502, 0x0502a405, 0xce0502a4, 0x02ce0502, 0x0702ce05, 0xe4050214, 0x026f0602, 0x0702e309, 
+    0x4c070231, 0x02600702, 0x0802b307, 0x320902e1, 0x02420902, 0x0a028106, 0xb308020f, 0x026b0702, 
+    0x04026b07, 0x6b0702b6, 0x026b0702, 0x07026b07, 0x6b07026b, 0x026b0702, 0x07026b07, 0x2709026b, 
+    0x028b0802, 0x04908b08, 0xf001743f, 0x12ff027d, 0x027dba3d, 0x3112157f, 0x01a475b9, 0x75fea675, 
+    0x9a75ffa7, 0x04902219, 0xf001743f, 0xe03d0490, 0x7ff0fe54, 0x7dff7eff, 0x12ff7cff, 0x7312a36b, 
+    0x3f0490cb, 0x901160e0, 0x70e00204, 0x3e049006, 0x120570e0, 0x0f808643, 0x75a4f5e4, 0xa775dfa6, 
+    0x109a75ff, 0x7fb56e12, 0xb374128b, 0x750f54ef, 0x0ff5000e, 0xffe4967d, 0xefa77412, 0x13c30354, 
+    0xa410f075, 0x0f42f0ae, 0xaf0e42ee, 0x12027d0f, 0x0490ba3d, 0xb63d1200, 0x7db23d12, 0x121a7f02, 
+    0x0090b931, 0xb63d1250, 0x12500090, 0x027db53d, 0x3112197f, 0x40a575b9, 0x75ffa675, 0x9a75bfa7, 
+    0x121e7f10, 0x13efae74, 0x1f541313, 0xf0830490, 0xe0830490, 0x07600764, 0x74400490, 0x9022f001, 
+    0x70e00204, 0x3e04900f, 0x900960e0, 0x13744004, 0x420902f0, 0xef285a12, 0x03700264, 0x753a0a02, 
+    0xa67580a4, 0xffa7757f, 0xe4019a75, 0xa675a4f5, 0xffa7757f, 0x90019a75, 0x06744004, 0x571222f0, 
+    0x0264ef61, 0x0a020370, 0x6157123a, 0x700164ef, 0x3a0a0203, 0xef076b12, 0x03700264, 0x903a0a02, 
+    0x60e04904, 0x6001641a, 0x81060203, 0xe0000490, 0x78e0a3fe, 0x13c3ce02, 0xf9d813ce, 0x9072e030, 
+    0xfee00004, 0x0778e0a3, 0xce13c3ce, 0x20f9d813, 0x1e7f5fe0, 0x12546f12, 0x0090c86c, 0x0490e05f, 
+    0xa3fee000, 0xce0278e0, 0x13ce13c3, 0x0490f9d8, 0x08e03020, 0x74a3f0e4, 0x0680f005, 0x74a3f0e4, 
+    0x097ff014, 0x7dba6f12, 0x12267f04, 0x7412b931, 0x5604908b, 0x7112f0ef, 0x4004900e, 0x12f00b74, 
+    0x70ef7474, 0x3a0a0203, 0x90536312, 0x60e04d04, 0x0490e4e5, 0x0490f048, 0x0490f04a, 0x94c3e04a, 
+    0x02034004, 0x0490f407, 0x2864e041, 0xb4e00460, 0x04900b29, 0x0164e04a, 0x07020370, 0x490490f4, 
+    0xb41660e0, 0x04902c01, 0xa3fee000, 0xce0278e0, 0x13ce13c3, 0xe030f9d8, 0x00049019, 0xe0a3fee0, 
+    0xc3ce0778, 0xd813ce13, 0x06e020f9, 0x5c0490e4, 0x04900580, 0xf001745c, 0xf05e0490, 0xe0490490, 
+    0x400294c3, 0x02a4753c, 0x75f0a675, 0x9a75ffa7, 0x03a57518, 0x75ffa675, 0x9a75fca7, 0x40049018, 
+    0x22f00974, 0x400490e4, 0xa4f5e4f0, 0x75f0a675, 0x9a75ffa7, 0xa5f5e418, 0x75ffa675, 0x9a75fca7, 
+    0x7d6c1218, 0x020360ef, 0x04903a0a, 0x01b4e05c, 0x5e04900b, 0x700164e0, 0xe3070203, 0xefec6b12, 
+    0x03700264, 0x903a0a02, 0x60e08a04, 0xfb080203, 0xeff36012, 0x03700264, 0x7d3a0a02, 0x12277f04, 
+    0x0490b931, 0x13ffe03c, 0x303f5413, 0x04900fe0, 0x0164e04c, 0x65120760, 0x0c02bf96, 0xd2441222, 
+    0x700264ef, 0x3a0a0203, 0xe07b0490, 0x08020360, 0x5c04908b, 0x0502b4e0, 0x80f00174, 0x5c049018, 
+    0x7d1270e0, 0x12287f04, 0x3712b931, 0x0264ef24, 0x0a020370, 0x5c04903a, 0x600164e0, 0x3a070203, 
+    0xe05e0490, 0x740602b4, 0x0702f001, 0xe638123a, 0x903a0702, 0x64e04c04, 0x90096001, 0x04e04a04, 
+    0x8a0602f0, 0xe0490490, 0x08020360, 0x0004909f, 0xe0a3fee0, 0xc3ce0278, 0xd813ce13, 0x03e020f9, 
+    0x909f0802, 0x30e00404, 0x7f540ce7, 0x450490ff, 0x9f5e12f0, 0x04907980, 0xf8c4e000, 0xa3c8f054, 
+    0x0f54c4e0, 0x64035448, 0x90646002, 0xfee00004, 0x0778e0a3, 0xce13c3ce, 0x20f9d813, 0x049051e0, 
+    0xc4ffe087, 0xe0200f54, 0x7f049046, 0x13c4ffe0, 0xe0300754, 0x50009013, 0xa313c3e0, 0x1f5413e0, 
+    0xe41094d3, 0x13500094, 0xe0500090, 0xe0a313c3, 0xd31f5413, 0x94e41694, 0x12144000, 0x64ef6429, 
+    0x02037002, 0x04903a0a, 0x0360e07b, 0x90600702, 0x60e08904, 0x4104901c, 0x602c64e0, 0x40049014, 
+    0x12f01674, 0x0490c32d, 0x2c64e041, 0x0a020360, 0x4c04903a, 0x600164e0, 0x00049037, 0xe0a3fee0, 
+    0xc3ce0778, 0xd813ce13, 0x24e020f9, 0x5d0490e4, 0x795b12f0, 0x700264ef, 0x3a0a0203, 0xe05d0490, 
+    0x0490ef60, 0xf001748a, 0xe44c0702, 0xf08a0490, 0xefb87412, 0x04902c60, 0xa3fee000, 0xce0778e0, 
+    0x13ce13c3, 0xe020f9d8, 0x4c049019, 0x600164e0, 0x40049011, 0x12f02274, 0x64ef035e, 0x02037002, 
+    0x047d3a0a, 0x3112297f, 0xb74912b9, 0x020360ef, 0x1a7f3a0a, 0xefb37412, 0x03600154, 0xe4d10902, 
+    0xa675a4f5, 0xffa775df, 0x75109a75, 0xa67520a4, 0xffa775df, 0x12109a75, 0x74c3dd62, 0x74ff9fff, 
+    0x74fe9eff, 0x74fd9dff, 0x78fc9cff, 0x29261203, 0x0c8e0d8f, 0x0a8c0b8d, 0x7dfeffe4, 0x0dabfc01, 
+    0x0ba90caa, 0x12c30aa8, 0x06401826, 0xff7fff7e, 0x0cae0480, 0x04900daf, 0xa3f0ee12, 0x0490f0ef, 
+    0xf004e00c, 0x743e0490, 0x027df001, 0x31120e7f, 0x0490e4b9, 0x0490f085, 0x90f00448, 0xf0044004, 
+    0x7f049022, 0x1313ffe0, 0xe0303f54, 0x49049015, 0x120870e0, 0x64ef7061, 0x904f6002, 0x54e07f04, 
+    0x1f7ff0fb, 0x90b77112, 0x15744004, 0x80a475f0, 0x757fa675, 0x9a75ffa7, 0x83049010, 0x90f0ff74, 
+    0x01744804, 0x747412f0, 0x901f60ef, 0xffe00804, 0x131313c4, 0xe0200154, 0x8b0490d4, 0x90ce70e0, 
+    0xf0044c04, 0x02a67212, 0xef228106, 0x400015b4, 0xcd110203, 0xf84b0a90, 0x02732828, 0x0a028a0a, 
+    0xcd110297, 0x02cd1102, 0x0b02ee0a, 0x2c0d025a, 0x02640d02, 0x0d029c0d, 0xdf0d02c0, 0x023c0e02, 
+    0x0e028b0e, 0xcd1102c3, 0x02040f02, 0x1002ed0f, 0x1d1102c5, 0x02881002, 0xa475bb11, 0x3fa67580, 
+    0x75ffa775, 0x7f220d9a, 0xae74120d, 0x70e4007e, 0x6014ef48, 0x17601412, 0x3d700224, 0xe0480490, 
+    0x11020370, 0x900080cd, 0x01741104, 0x906e0c02, 0x01743f04, 0x0490e4f0, 0x7212f011, 0x121a7fa6, 
+    0x54efb374, 0x02037001, 0xa475610d, 0xdfa67520, 0x75ffa775, 0x0d02109a, 0x02017f61, 0x0d7f3610, 
+    0x7eae7412, 0x5f70e400, 0x326014ef, 0x143d6014, 0x03244660, 0x90d35170, 0x94e05300, 0x52009000, 
+    0x400094e0, 0xa3fee00b, 0xeea4f5e0, 0x3480a5f5, 0xef3f7412, 0x7412a4f5, 0xa5f5ee3f, 0x72122680, 
+    0xa4f5efcb, 0xeecb7212, 0x1880a5f5, 0x07ad38af, 0xe4a4f5ed, 0x0c80a5f5, 0xefdd6212, 0x6212a4f5, 
+    0xa5f5eedd, 0x020e9a75, 0x0d7f610d, 0x7eae7412, 0x0360e400, 0xefcd1102, 0x0370fe24, 0x14030c02, 
+    0x0c020370, 0x03701429, 0x14720c02, 0x0c020370, 0x036014cb, 0x90cd1102, 0xffe01104, 0x400194d3, 
+    0xc044ef07, 0x361002ff, 0xe0490490, 0x400194d3, 0x02d27f05, 0x04903610, 0x0c70e048, 0xe0110490, 
+    0x500094d3, 0xcd110203, 0xe0110490, 0x7f0094d3, 0x7f024000, 0x4e049001, 0x0e7ff0ef, 0x90807412, 
+    0xf0ee2404, 0x12f0efa3, 0x158fff4b, 0x94d315e5, 0xe5084000, 0xff604415, 0x90361002, 0x05741104, 
+    0x240490f0, 0xe0a3fee0, 0xf5eea4f5, 0x0e9a75a5, 0x90610d02, 0x70e04804, 0x1104900c, 0x0094d3e0, 
+    0x11020350, 0x110490cd, 0x4e0490e0, 0x110490f0, 0x12f00174, 0x0d02e173, 0x3f049061, 0x90f00174, 
+    0xd3e01104, 0x20400194, 0x5a0090e4, 0x90f0a3f0, 0xa3f05800, 0x7f027ef0, 0x017bfdf8, 0x0079017a, 
+    0xe4892612, 0xf0650090, 0x90867012, 0xd3e04e04, 0x80948064, 0x0240007f, 0x0490017f, 0x02f0ef11, 
+    0x0490610d, 0xd3ffe011, 0x10400194, 0xe0650090, 0x44f054c4, 0x4eeffec0, 0x361002ff, 0xe0490490, 
+    0x400194d3, 0x02d27f05, 0x04903610, 0x0c70e048, 0xe0110490, 0x500094d3, 0xcd110203, 0x74650090, 
+    0x0490f001, 0x94d3e011, 0x40007f00, 0x90017f02, 0xf0ef4e04, 0x74110490, 0x90578002, 0xffe01104, 
+    0x400194d3, 0x65009010, 0xf054c4e0, 0xeffec044, 0x1002ff4e, 0x49049036, 0x0194d3e0, 0xd27f0540, 
+    0x90361002, 0x70e04804, 0x1104900c, 0x0094d3e0, 0x11020350, 0x650090cd, 0x90f00174, 0xd3e01104, 
+    0x007f0094, 0x017f0240, 0xef4e0490, 0x110490f0, 0x12f00374, 0x7112b069, 0x8510020e, 0x74120d7f, 
+    0x14f5efae, 0x7e8094c3, 0x50017b00, 0x2f007409, 0x0434eef9, 0x80740880, 0xeef91425, 0x12fa0434, 
+    0x128ea325, 0x13e513f5, 0x12e5a4f5, 0x9a75a5f5, 0x8510020e, 0x74120d7f, 0x14f5efae, 0x74120e7f, 
+    0x00127580, 0x14e5138f, 0xe58094c3, 0x7b007c14, 0x240a5001, 0x34ecf900, 0x80effa04, 0xf9802409, 
+    0xfa0434ec, 0x251213e5, 0x851002de, 0x74120d7f, 0x007eefae, 0x5024017b, 0x0034eef9, 0xa32512fa, 
+    0x13f5128e, 0x12e5a4f5, 0x9a75a5f5, 0x8510020e, 0x74120e7f, 0x00127580, 0x07c0138f, 0x74120d7f, 
+    0x007eefae, 0x5024017b, 0x0034eef9, 0x7ffb0e02, 0xae74120d, 0xc314f5ef, 0x1e508094, 0x007cfdef, 
+    0x0024017b, 0x0434ecf9, 0xa32512fa, 0xf5001375, 0x2d017412, 0x0434ecf9, 0x14e51d80, 0x7b007cfd, 
+    0xf9802401, 0xfa0434ec, 0x75a32512, 0x12f50013, 0xf92d8174, 0xfa0434ec, 0x42a32512, 0x13e5e413, 
+    0x12e5a4f5, 0x9a75a5f5, 0x8510020e, 0x74120e7f, 0x8f128e80, 0x120d7f13, 0xf5efae74, 0x8094c314, 
+    0xe5ff12e5, 0x007cfd14, 0x1450017b, 0xecf90024, 0xeffa0434, 0x74de2512, 0xecf92d01, 0x12800434, 
+    0xecf98024, 0xeffa0434, 0x74de2512, 0xecf92d81, 0xe5fa0434, 0xde251213, 0x7f851002, 0xae74120d, 
+    0xfd14f5ef, 0x017b007c, 0xecf95024, 0x12fa0034, 0x1375a325, 0x7412f500, 0xecf92d51, 0x12fa0034, 
+    0x1342a325, 0xf513e5e4, 0xf512e5a4, 0x0e9a75a5, 0x7f851002, 0x8074120e, 0x138f128e, 0xc0ff12e5, 
+    0x120d7f07, 0x7eefae74, 0x24017b00, 0x34eef950, 0xe0d0fa00, 0xafde2512, 0x7f07c013, 0xae74120d, 
+    0x7b007eef, 0xf9512401, 0xfa0034ee, 0x2512e0d0, 0xb91102de, 0xe0110490, 0x400194d3, 0xe90f0203, 
+    0x74120d7f, 0xe4007eae, 0x11020360, 0x6014efcd, 0x03701444, 0x24c50f02, 0x02036002, 0xfde4cd11, 
+    0x3112117f, 0x650090b9, 0x90f00174, 0xfee05a00, 0x4effe0a3, 0x027c0a70, 0x027ef77d, 0x0880f77f, 
+    0xffff24ef, 0xfeff34ee, 0xee580090, 0xf0efa3f0, 0x0f02ffe4, 0x580090e6, 0xe0a3fee0, 0x0024017b, 
+    0x3e0174f9, 0xa32512fa, 0xf5001275, 0xe5a4f513, 0x75a5f512, 0x00900e9a, 0xa3fee05a, 0x0090ffe0, 
+    0x06b5e058, 0xb5e0a309, 0x017f0407, 0xffe40280, 0x904d7412, 0xfee05800, 0x4effe0a3, 0x027e0670, 
+    0x0880f77f, 0xffff24ef, 0xfeff34ee, 0xee580090, 0xf0efa3f0, 0x0090e422, 0x0090f065, 0xf0a3f05a, 
+    0xf0580090, 0x027ef0a3, 0x7bfdf87f, 0x79017a01, 0x89261200, 0x7402017f, 0x80557f4d, 0x11049049, 
+    0x94d3ffe0, 0x900f4001, 0xc4e06500, 0x4044f054, 0xff4eeffe, 0x0d7f3080, 0xefae7412, 0x7f1ce230, 
+    0xb37412d9, 0x640154ef, 0x7f106001, 0xb37412d9, 0xc40154ef, 0x8044f054, 0x900b80ff, 0xd3e04904, 
+    0x05400194, 0x7402d27f, 0x4804902e, 0x900c70e0, 0xd3e01104, 0x03500094, 0x90cd1102, 0x01746500, 
+    0x110490f0, 0x0094d3e0, 0x0240007f, 0x0490017f, 0x90f0ef4e, 0x04741104, 0x120d7ff0, 0x90efae74, 
+    0x12f01704, 0x04901c46, 0xa3fee024, 0xeea4f5e0, 0x9a75a5f5, 0xb911020e, 0x743f0490, 0x90e4f001, 
+    0xa3f05a00, 0x580090f0, 0x7ef0a3f0, 0xfdf87f02, 0x017a017b, 0x26120079, 0x0090e489, 0x7012f065, 
+    0x4e049086, 0x8064d3e0, 0x007f8094, 0x017f0240, 0x80110490, 0x02f07553, 0x24a438e5, 0xe582f5c1, 
+    0xf57734f0, 0xfe93e483, 0xff930174, 0xe0160490, 0xef007cfd, 0x3eecff2d, 0x2f0074fe, 0x017482f5, 
+    0xe083f53e, 0xf5001275, 0xe5a4f513, 0x75a5f512, 0x04900e9a, 0xc3ffe016, 0x0640ff94, 0x007f007e, 
+    0x04ef0380, 0x160490ff, 0x1102f0ef, 0x02f075ca, 0x24a438e5, 0xe582f5c1, 0xf57734f0, 0xfe93e483, 
+    0xff930174, 0xe0160490, 0x007cfdf9, 0xecff2def, 0x0074fe3e, 0x7482f52f, 0x83f53e01, 0xc3e9fde0, 
+    0x0440ff94, 0x06800079, 0xe0160490, 0x0490f904, 0x75f0e916, 0x38e502f0, 0xf5c124a4, 0x34f0e582, 
+    0xe483f577, 0x0174fe93, 0xfbe9ff93, 0x2bef007a, 0xfe3eeaff, 0xf52f0074, 0x3e017482, 0x75e083f5, 
+    0x13f50012, 0xff94c3e9, 0x007f0440, 0x04900680, 0xff04e016, 0xef160490, 0xe505aff0, 0xeda4f513, 
+    0xeefe1245, 0x9a75a5f5, 0x120f800e, 0xf5efef68, 0xef6812a4, 0x75a5f5ee, 0x74120e9a, 0xf5e42295, 
+    0x1404901a, 0x03e730e0, 0x75b21502, 0xa67520a4, 0xffa775df, 0x90119a75, 0x70e04904, 0x007afb12, 
+    0x66121a79, 0x8e158f74, 0x8c138d14, 0x90728012, 0xfee02404, 0xc3ffe0a3, 0x64eef094, 0x407f9480, 
+    0x94efd30b, 0x8064ee0f, 0x07408094, 0xe0170490, 0x7f1ce120, 0x80741234, 0xe09533ee, 0x0a78fcfd, 
+    0xc03c2612, 0xc005c004, 0x7f07c006, 0x7f1a8035, 0x80741236, 0xe09533ee, 0x0a78fcfd, 0xc03c2612, 
+    0xc005c004, 0x7f07c006, 0xb3741237, 0x02d003d0, 0x00d001d0, 0x15f54feb, 0xe914f5ea, 0xf5e813f5, 
+    0x7a007b12, 0x12167900, 0x1b756c53, 0x901c8f00, 0xfee03804, 0xe4ffe0a3, 0x1078fdfc, 0xa83c2612, 
+    0xaa05a904, 0xa307ab06, 0xe0a3fee0, 0xff4febff, 0xe9fe4eea, 0xeffce8fd, 0xeeff1525, 0xedfe1435, 
+    0xecfd1335, 0xabfc1235, 0xa914aa15, 0xd312a813, 0x40182612, 0xffff7408, 0x80fcfdfe, 0x38049038, 
+    0xe0a3fee0, 0xfdfce4ff, 0x26121078, 0xa904a83c, 0xab06aa05, 0xfee0a307, 0xebffe0a3, 0x4eeaff4f, 
+    0xe8fde9fe, 0x1525effc, 0x1435eeff, 0x1335edfe, 0x1235ecfd, 0x8e158ffc, 0x8c138d14, 0x641ce512, 
+    0x601b4501, 0x2404900a, 0xa30270e0, 0x122e70e0, 0x1ae5e34a, 0x017f0470, 0x007f0280, 0x3333c4ef, 
+    0x8044c054, 0xc41ce5fc, 0x4ce05433, 0x770490fe, 0xffedfde0, 0xee140490, 0xf0efa3f0, 0x62009022, 
+    0xfce4ffe0, 0x0478fefd, 0xab3c2612, 0xa914aa15, 0xd312a813, 0x50182612, 0x66150203, 0x277effe4, 
+    0x19abfcfd, 0x17a918aa, 0x12d316a8, 0x1f501826, 0x7ecc7fe4, 0xa8fcfd07, 0x18261216, 0x15020350, 
+    0x17049066, 0xd34054e0, 0x03500094, 0x12661502, 0x0490e34a, 0x0154e017, 0x400094d3, 0x2404901e, 
+    0xe0a3fee0, 0x8064eeff, 0x09508094, 0xff0124ef, 0x80fe3ee4, 0x7f007e26, 0x90208000, 0xfee02404, 
+    0xd3ffe0a3, 0x64ee0094, 0x40809480, 0xff24ef0a, 0xff34eeff, 0x7e0480fe, 0x90007f00, 0xf0ee2404, 
+    0x90f0efa3, 0xffe01704, 0x94d30254, 0x02035000, 0x04908714, 0x7060e049, 0xd30454ef, 0x02400094, 
+    0x04906680, 0x0154e017, 0x400094d3, 0x2404902d, 0x0470f4e0, 0xf064e0a3, 0xc17f1270, 0x7f5f6a12, 
+    0x5f6a1201, 0x7504a575, 0x2a80ffa6, 0x7502a575, 0xa775ffa6, 0x049a75fd, 0x04902e80, 0x0470e024, 
+    0x0f64e0a3, 0x3f7f1670, 0x7f5f6a12, 0x5f6a12ff, 0x7504a575, 0x9a75ffa6, 0x36150232, 0x7502a575, 
+    0xa775ffa6, 0x049a75fd, 0x7502a575, 0xa775ffa6, 0x049a75fd, 0x90361502, 0xffe01704, 0x94d30454, 
+    0x02035000, 0xc4ef2d15, 0x60140354, 0x59601449, 0x24696014, 0x02036003, 0x04903615, 0xa3fee026, 
+    0x94c3ffe0, 0x8064ee04, 0x0a408094, 0x13e7a2ee, 0x007e13ef, 0x007e0680, 0xe0270490, 0xc3ff0154, 
+    0xe0270490, 0x04900494, 0x8064e026, 0x007d8094, 0x017d0240, 0x04904280, 0x0154e017, 0x7f0094d3, 
+    0x7f024000, 0x80fde401, 0x1704902f, 0xd30154e0, 0x007f0094, 0x017f0240, 0x1c80017d, 0xe0260490, 
+    0xa313e7a2, 0x015413e0, 0x12017dff, 0x04908848, 0x54e0a326, 0xfde4ff01, 0x80884812, 0x24049009, 
+    0x12ffe0a3, 0x7312546f, 0x0490e457, 0xf0a3f038, 0xf0a3f0a3, 0x7b0e7112, 0x79007a00, 0x7466121a, 
+    0x148e158f, 0x128c138d, 0x75a4f5e4, 0xa775dfa6, 0x119a75ff, 0x15af2c80, 0x13ad14ae, 0x107812ac, 
+    0x90292612, 0xf0ee3804, 0xa3f0efa3, 0xa3f014e5, 0x12f015e5, 0xf5e40e71, 0xdfa675a4, 0x75ffa775, 
+    0x0490119a, 0x54e0a324, 0x751bf57f, 0x0490001c, 0xe5ffe077, 0x1ce5fe1b, 0x0490ff4f, 0xa3f0ee14, 
+    0x8f22f0ef, 0xe1147512, 0x751f1575, 0xe5d3ff13, 0x94806412, 0x7f1c4080, 0xb3741246, 0xff3f54ef, 
+    0x207d007e, 0x7312007c, 0x9533efb4, 0x7f168fe0, 0xc33f8045, 0x806412e5, 0x1c508094, 0x7412487f, 
+    0x3f54efb3, 0x7d007eff, 0x12007c20, 0x33efb473, 0x168fe095, 0x1a80477f, 0x7412447f, 0x3f54efb3, 
+    0x7d007eff, 0x12007c20, 0x33efb473, 0x168fe095, 0x7412437f, 0x3f54efb3, 0x7d007eff, 0x12007c20, 
+    0x33efb473, 0x178fe095, 0xe0530490, 0x17020360, 0x12347f80, 0x1a8e8074, 0x04901b8f, 0x90fbe04e, 
+    0xf5e01c04, 0xf5e0a320, 0x22148521, 0x85231585, 0x1bad2413, 0x16af1aac, 0x8fba5112, 0x62049018, 
+    0x904d60e0, 0xfbe04e04, 0xe01c0490, 0xe0a320f5, 0x148521f5, 0x23158522, 0xad241885, 0xaf1aac1b, 
+    0xb8401216, 0xef510490, 0x12e5d3f0, 0x80948064, 0x90e00740, 0x80f06704, 0x12e5c317, 0x80948064, 
+    0xe0510490, 0x04900650, 0x0480f065, 0xf0630490, 0xe54e0490, 0x0490f016, 0xf01ae51c, 0xf01be5a3, 
+    0xe0620490, 0xf0530490, 0x6412e5d3, 0x40809480, 0xef18af14, 0xefe09533, 0xa675a4f5, 0xffa775c0, 
+    0x80469a75, 0x12e5c32f, 0x80948064, 0x18af1450, 0xe09533ef, 0x75a4f5ef, 0xa775c0a6, 0x489a75ff, 
+    0x18af1280, 0xe09533ef, 0x75a4f5ef, 0xa775c0a6, 0x449a75ff, 0xe0620490, 0xe5d35660, 0x94806412, 
+    0x7d124080, 0x12207f05, 0x0490356c, 0x7dfbe061, 0x80207f05, 0x12e5c336, 0x80948064, 0xe0600490, 
+    0x50007afb, 0x7f017d14, 0x12007e02, 0x04903e6c, 0x7dfbe061, 0x80027f01, 0x7f037d12, 0x12007e08, 
+    0x04903e6c, 0x7dfbe061, 0x7e087f03, 0x516d1200, 0xe0540490, 0x18020360, 0x12367fbc, 0x1a8e8074, 
+    0x04901b8f, 0x90fbe04f, 0xf5e01e04, 0xf5e0a320, 0x22148521, 0x85231585, 0x1bad2413, 0x17af1aac, 
+    0x8fba5112, 0x62049019, 0x904d60e0, 0xfbe04f04, 0xe01e0490, 0xe0a320f5, 0x148521f5, 0x23158522, 
+    0xad241985, 0xaf1aac1b, 0xb8401217, 0xef500490, 0x12e5d3f0, 0x80948064, 0x90e00740, 0x80f06804, 
+    0x12e5c317, 0x80948064, 0xe0500490, 0x04900650, 0x0480f066, 0xf0640490, 0xe54f0490, 0x0490f017, 
+    0xf01ae51e, 0xf01be5a3, 0xe0620490, 0xf0540490, 0x6412e5d3, 0x40809480, 0xef19af10, 0xa675a4f5, 
+    0xffa775c0, 0x80459a75, 0x12e5c327, 0x80948064, 0x19af1050, 0x75a4f5ef, 0xa775c0a6, 0x479a75ff, 
+    0x19af0e80, 0x75a4f5ef, 0xa775c0a6, 0x439a75ff, 0xe0620490, 0xe5d35660, 0x94806412, 0x7d124080, 
+    0x12107f04, 0x0490356c, 0x7dfbe061, 0x80107f04, 0x12e5c336, 0x80948064, 0xe0600490, 0x50007afb, 
+    0x7ffde414, 0x6c12fe01, 0x6104903e, 0xfde4fbe0, 0x80fe017f, 0x7f027d14, 0x12007e04, 0x04903e6c, 
+    0x7dfbe061, 0x7e047f02, 0x516d1200, 0xe0530490, 0xe0a30b60, 0x04900760, 0xf001744d, 0x0490e422, 
+    0x9022f04d, 0xffe05004, 0x8ffde0a3, 0x90138d12, 0xb4e04904, 0x347f0401, 0x00905d80, 0x13c3e050, 
+    0x7e13e0a3, 0xff1f5400, 0xee1094d3, 0x45400094, 0xe07f0490, 0x0f54c4fd, 0xd309e020, 0xee1694ef, 
+    0x31400094, 0x01b412e5, 0x8804900b, 0x5413c4e0, 0x12e03007, 0x026412e5, 0x04901b70, 0x13c4e088, 
+    0x20035413, 0x13e50fe0, 0x347f0470, 0x367f0280, 0x80807412, 0x12387f05, 0x148e8074, 0x7412158f, 
+    0x1060efb8, 0x04b412e5, 0x05127503, 0x05b412e5, 0x04127503, 0xfe2412e5, 0x70146260, 0x831a0203, 
+    0x02037014, 0x70149f1a, 0xbc1a0203, 0x03600424, 0xe5d71a02, 0x703b7f13, 0xb374121c, 0xff3f54ef, 
+    0x06c0007e, 0x3b7f07c0, 0xefae7412, 0x13133f54, 0x801f5413, 0xb3741215, 0xff3f54ef, 0x06c0007e, 
+    0x3b7f07c0, 0xefae7412, 0xd0fd0754, 0xd0ff2de0, 0xe4168fe0, 0x177518f5, 0xda1a0246, 0x5b7013e5, 
+    0x74123c7f, 0x7f54efb3, 0x541313c4, 0x603c7f03, 0xb3741227, 0xff1f54ef, 0x06c0007e, 0x3c7f07c0, 
+    0xefae7412, 0x13133f54, 0xfd1f5413, 0xff2de0d0, 0xe4c3e0d0, 0x7180ff9f, 0xefb37412, 0x7eff1f54, 
+    0xc006c000, 0x123c7f07, 0x54efae74, 0x1313133f, 0xd0fd1f54, 0xd0ff2de0, 0x7f4e80e0, 0xb374123c, 
+    0xc43f54ef, 0x7f075413, 0x1222603c, 0x54efb374, 0x007eff1f, 0x07c006c0, 0x74123c7f, 0x0754efae, 
+    0x2de0d0fd, 0xc3e0d0ff, 0x80ff9fe4, 0xb374121c, 0xff1f54ef, 0x06c0007e, 0x3c7f07c0, 0xefae7412, 
+    0xd0fd0754, 0xd0ff2de0, 0x75168fe0, 0x1775da18, 0x7f578026, 0xb374123d, 0xff3f54ef, 0x207d007e, 
+    0x7312007c, 0x75168fb4, 0x1775e118, 0x7f3b801f, 0x8074123d, 0xfe0754ee, 0x047c007d, 0xefb47312, 
+    0xa2ce0678, 0x13ce13e7, 0x1080f8d8, 0x74123d7f, 0x0b78ef80, 0x13e7a2ce, 0xf8d813ce, 0x75168fff, 
+    0x1775f118, 0xe403800f, 0x049016f5, 0xf016e54f, 0xfffe0470, 0xe5c31380, 0x94806416, 0x7e064080, 
+    0x80017f00, 0x7fff7e04, 0x15e5c3ff, 0xe515f59f, 0x14f59e14, 0xe04b0490, 0x400094d3, 0x4e04902b, 
+    0x0490fbe0, 0x20f5e01e, 0x21f5e0a3, 0x85221885, 0x24752317, 0xac15adff, 0x1216af14, 0x168fba51, 
+    0xe0620490, 0xf04d0490, 0x01b412e5, 0xb516e51f, 0xe5c31518, 0xe5ff9415, 0x94806414, 0x9008507f, 
+    0x01747c04, 0xe40580f0, 0xf07c0490, 0xe04c0490, 0x08600164, 0xe04a0490, 0x31700364, 0x01b412e5, 
+    0x6516e506, 0xe5136017, 0x0194d312, 0x16e51f40, 0x06601765, 0x186516e5, 0xa4751370, 0xfea67501, 
+    0x75ffa775, 0x017d199a, 0x31121c7f, 0x490490b9, 0x0901b4e0, 0x12af16ad, 0x80a52b12, 0x4f04900f, 
+    0xab1cf5e0, 0xaf13ad16, 0xd51b1212, 0xe51e0490, 0xe5a3f014, 0x0490f015, 0x0490e04f, 0x0490f04e, 
+    0xf004e04b, 0x8d198f22, 0xc31b8b1a, 0x1c951be5, 0x19e51df5, 0x0370fe24, 0x04f81c02, 0x1e020360, 
+    0x123b7fc9, 0x54efae74, 0x1313133f, 0x20f51f54, 0x74123b7f, 0x0754efae, 0x3b7f21f5, 0xefb37412, 
+    0x22f53f54, 0xe53f2375, 0x6960141a, 0x02036004, 0x2778aa1c, 0x007d007c, 0x007a007b, 0x007e1e79, 
+    0x2512067f, 0xaf017d5b, 0x5069121d, 0x1e7803c0, 0xd01d007c, 0x7f007e03, 0x5b251206, 0xe0500090, 
+    0xe0a313c3, 0x54007e13, 0x94d3ff1f, 0x0094ee10, 0x04901e40, 0x54c4e07f, 0x09e0200f, 0x1694efd3, 
+    0x400094ee, 0x8804900b, 0x5413c4e0, 0x2ae03007, 0x80212085, 0x7c277825, 0x7b007d00, 0x79007a00, 
+    0x7f007e1e, 0x5b251206, 0x1daffde4, 0x78506912, 0x7e007c1e, 0x12067f00, 0x21af5b25, 0xf5ed07ad, 
+    0xf50474a4, 0xc0a775a5, 0x752b9a75, 0xa67580a5, 0x7fa775ff, 0xaf2b9a75, 0xed07ad20, 0x0674a4f5, 
+    0xa775a5f5, 0x2b9a75c0, 0x7580a575, 0xa775ffa6, 0x2b9a757f, 0x07ad22af, 0x74a4f5ed, 0x75a5f502, 
+    0x9a75c0a7, 0xbc1e022b, 0x74123c7f, 0x7f54efb3, 0x541313c4, 0x7f1ef503, 0xb374123c, 0xc43f54ef, 
+    0xf5075413, 0x123c7f1f, 0x54efae74, 0x1313133f, 0x20f51f54, 0x74123c7f, 0x0754efae, 0x3c7f21f5, 
+    0xefb37412, 0x22f51f54, 0xe51f2375, 0x0370141a, 0x04e11d02, 0x1e020360, 0x2520e537, 0x33e4ff22, 
+    0xe508704f, 0x03ffb41d, 0xaf011e75, 0x7c007e1e, 0x12fe7dff, 0x04eff025, 0xa4f01d85, 0x277824f5, 
+    0x007d007c, 0x007a007b, 0x007e1e79, 0x2512067f, 0xaf017d5b, 0x50691224, 0x1e7803c0, 0xd01d007c, 
+    0x7f007e03, 0x5b251206, 0x222520e5, 0x4f33e4ff, 0x1ef50270, 0xe0500090, 0xe0a313c3, 0x54007e13, 
+    0x94d3ff1f, 0x0094ee10, 0x04901f40, 0x54c4e07f, 0x09e0200f, 0x1694efd3, 0x400094ee, 0x8804900c, 
+    0x1313c4e0, 0xe0300354, 0x2120855e, 0x801f1e85, 0x2521e556, 0x33e4ff22, 0xe508704f, 0x03ffb41d, 
+    0xaf011f75, 0x7c007e1f, 0x12fe7dff, 0x04eff025, 0xa4f01d85, 0x277824f5, 0x007d007c, 0x007a007b, 
+    0x007e1e79, 0x2512067f, 0xaffde45b, 0x50691224, 0x007c1e78, 0x067f007e, 0xe55b2512, 0xff222521, 
+    0x704f33e4, 0xaf1ff502, 0xed07ad21, 0x0a74a4f5, 0xa775a5f5, 0x2b9a75c0, 0x7580a575, 0xa775ffa6, 
+    0x2b9a757f, 0x07ad20af, 0x74a4f5ed, 0x75a5f50c, 0x9a75c0a7, 0x80a5752b, 0x75ffa675, 0x9a757fa7, 
+    0xad22af2b, 0xa4f5ed07, 0xa5f50874, 0x75c0a775, 0xa5752b9a, 0xffa67580, 0x757fa775, 0x1eaf2b9a, 
+    0xf5ed07ad, 0xf51474a4, 0xc0a775a5, 0x752b9a75, 0xa67580a5, 0x7fa775ff, 0xaf2b9a75, 0xed07ad1f, 
+    0x1674a4f5, 0xa775a5f5, 0x2b9a75c0, 0x7580a575, 0xa775ffa6, 0x2b9a757f, 0xaf1bad22, 0xa52b1219, 
+    0x75128f22, 0x0490031a, 0x0960e049, 0x744d0490, 0x027ff001, 0x15f5e422, 0x14f513f5, 0x18f517f5, 
+    0x16f519f5, 0x7412387f, 0x1c049080, 0xefa3f0ee, 0x12397ff0, 0x54ee8074, 0x1e049003, 0xf0efa3f0, 
+    0x900a7412, 0xf0ef5104, 0x02b412e5, 0x6f049005, 0x12e51b80, 0x900503b4, 0x11807004, 0x01b412e5, 
+    0x71049005, 0x12e50780, 0x04900670, 0x16f5e072, 0x0490fde4, 0x0270e01c, 0x2570e0a3, 0xe01e0490, 
+    0xffe0a3fe, 0xee0094d3, 0x80948064, 0xa2ee3a40, 0xeffe13e7, 0x0490ff13, 0xa3f0ee1e, 0x800df0ef, 
+    0x900a7ddb, 0xfee01c04, 0xd3ffe0a3, 0x64ee0094, 0x40809480, 0xe7a2ee13, 0x13effe13, 0x1c0490ff, 
+    0xefa3f0ee, 0xdb800df0, 0xf5fc24ed, 0x9533ff15, 0x78effee0, 0xce33c307, 0xf9d8ce33, 0xa2ce0378, 
+    0x13ce13e7, 0xacfdf8d8, 0x22049006, 0xe0a3fee0, 0xc3ce0378, 0xd813ce13, 0xf59dc3f9, 0xf59cee14, 
+    0xb412e513, 0xe5d30f02, 0xe5009414, 0x94806413, 0x8002409f, 0xb412e539, 0xe5d30f03, 0xe5009414, 
+    0x94806413, 0x8002409f, 0xb412e525, 0xe5d30f01, 0xe5009414, 0x94806413, 0x8002409f, 0x7012e511, 
+    0x14e5d313, 0x13e50094, 0x9f948064, 0x13750640, 0x0014751f, 0x13ae14e5, 0x33c30378, 0xd8ce33ce, 
+    0x230490f9, 0x0490eef0, 0x16e5f022, 0xa408f075, 0x1425f0ae, 0x35ee14f5, 0xe513f513, 0x0f02b412, 
+    0x9414e5d3, 0x6413e500, 0x409f9480, 0xe5398002, 0x0f03b412, 0x9414e5d3, 0x6413e500, 0x409f9480, 
+    0xe5258002, 0x0f01b412, 0x9414e5d3, 0x6413e500, 0x409f9480, 0xe5118002, 0xd3137012, 0x009414e5, 
+    0x806413e5, 0x06409f94, 0x751f1375, 0x13ae0014, 0x037814e5, 0x33ce33c3, 0xf5f9d8ce, 0xe5178e18, 
+    0xfe075417, 0x037818e5, 0xce13c3ce, 0xf5f9d813, 0x6012e516, 0x0b03b403, 0x131317e5, 0xf51f5413, 
+    0xe50d8019, 0x13131317, 0xf0751f54, 0x19f5a4ff, 0x036012e5, 0xd32601b4, 0x806419e5, 0x05409f94, 
+    0x80510490, 0x19e5c32f, 0x61948064, 0x04900550, 0xe5328051, 0x903b6019, 0x80f05104, 0x6412e535, 
+    0xe5056002, 0x2a03b412, 0x6419e5d3, 0x409f9480, 0x50049008, 0x80f01f74, 0x19e5c319, 0x61948064, 
+    0x04900850, 0xf0e17450, 0x19e50880, 0x04900460, 0x0490f050, 0xf001744d, 0x167012e5, 0xe0220490, 
+    0xf00f0490, 0xa3220490, 0x750490e0, 0x720490f0, 0x12e54780, 0x901601b4, 0x90e02204, 0x90f01004, 
+    0xe0a32204, 0xf0760490, 0x80710490, 0x9012e52c, 0x02b42204, 0x0490e013, 0x0490f00d, 0x90e0a322, 
+    0x90f07304, 0x11806f04, 0x0e0490e0, 0x220490f0, 0x0490e0a3, 0x0490f074, 0xf016e570, 0x7f22007f, 
+    0xb374128b, 0x900f54ef, 0x12f04904, 0x0490a672, 0xa3fee000, 0xce0278e0, 0x13ce13c3, 0xe030f9d8, 
+    0x90198002, 0x70e04904, 0x50009018, 0xa313c3e0, 0x1f5413e0, 0xe40694c3, 0x05400094, 0x80a4f5e4, 
+    0x04a47503, 0x75fba675, 0x9a75ffa7, 0x00049040, 0xe0a3fee0, 0xc3ce0278, 0xd813ce13, 0x1ee020f9, 
+    0xe0490490, 0x00901870, 0x13c3e050, 0x5413e0a3, 0x0e94d31f, 0x400094e4, 0x80a47505, 0xf5e40380, 
+    0x7fa675a4, 0x75ffa775, 0x0490409a, 0xa3fce000, 0xc4ecfde0, 0xc8f054f8, 0x0f54c4ed, 0x64035448, 
+    0xed0c7002, 0x027804ae, 0xce13c3ce, 0x90f9d813, 0xfee00004, 0x0278e0a3, 0xce13c3ce, 0x20f9d813, 
+    0x230203e0, 0x01a57514, 0x75ffa675, 0x9a75fea7, 0x49049040, 0x020360e0, 0x00903823, 0x13c3e050, 
+    0x7e13e0a3, 0xff1f5400, 0xee0a94c3, 0x03500094, 0xef382302, 0x94ee0e94, 0x75115000, 0xa67501a4, 
+    0xffa775fc, 0x75909a75, 0x738002a5, 0x1294efc3, 0x500094ee, 0x02a47511, 0x75fca675, 0x9a75ffa7, 
+    0x04a57590, 0xa4755980, 0xfca67503, 0x75ffa775, 0xa575909a, 0xffa67506, 0x75f9a775, 0x0090929a, 
+    0x13c3e050, 0x5413e0a3, 0x1594d31f, 0x400094e4, 0x20a57505, 0xf5e40380, 0xffa675a5, 0x75dfa775, 
+    0x2480909a, 0x75a5f5e4, 0xa775ffa6, 0x409a75fe, 0x75a4f5e4, 0xa775fca6, 0x909a75ff, 0x75a5f5e4, 
+    0xa775ffa6, 0x929a75f9, 0xf512f5e4, 0x50009013, 0xa313c3e0, 0x1f5413e0, 0xe40594c3, 0x06500094, 
+    0x75041375, 0x13e50612, 0x13c30254, 0xe025e025, 0xe5ff0454, 0x13045413, 0x333f5413, 0x08543333, 
+    0x13e5ff4f, 0xe0250154, 0xf54f0254, 0xf1a675a4, 0x75ffa775, 0x12e5919a, 0x13c30254, 0xff1054c4, 
+    0x045412e5, 0x3f541313, 0x205433c4, 0x12e5ff4f, 0x33330154, 0x4f085433, 0xa675a4f5, 0xffa775c7, 
+    0xe5929a75, 0xc3025413, 0x1054c413, 0x5413e5ff, 0x54131304, 0x5433c43f, 0xe5ff4f20, 0xfe015413, 
+    0x54333333, 0xa4f54f08, 0x75c7a675, 0x9a75ffa7, 0x49049093, 0x700164e0, 0x01a47505, 0xf5e40380, 
+    0xfea675a4, 0x75ffa775, 0x0490a89a, 0x0464e049, 0xa4750570, 0xe4038001, 0xa675a4f5, 0xffa775fe, 
+    0x7da09a75, 0x12ffe496, 0x54efa774, 0x13c3ff03, 0xf0890490, 0xa5750560, 0x7503801b, 0xa67511a5, 
+    0xe0a775ff, 0x75c09a75, 0xa67501a4, 0xffa775fe, 0x90019a75, 0x24e04904, 0x0008b4fe, 0x24903050, 
+    0x03f0755c, 0x2583c5a4, 0x7383c5f0, 0x02742402, 0x24027424, 0x79240274, 0x02792402, 0x24027424, 
+    0x79240274, 0x8001a575, 0x02a57508, 0xf5e40380, 0xffa675a5, 0x75fca775, 0xe722039a, 0xdf08f609, 
+    0xe74680fa, 0xdf08f209, 0x883e80fa, 0xe7838c82, 0xdfa3f009, 0xe33280fa, 0xdf08f609, 0xe37880fa, 
+    0xdf08f209, 0x887080fa, 0xe3838c82, 0xdfa3f009, 0x896480fa, 0xe0838a82, 0xdf08f6a3, 0x895880fa, 
+    0xe0838a82, 0xdf08f2a3, 0x804c80fa, 0x80fa80d2, 0x80d480c6, 0x80f28069, 0x80108033, 0x80ea80a6, 
+    0x80a8809a, 0x80e280da, 0x893380ca, 0xec838a82, 0xa393e4fa, 0xc882c5c8, 0xcc83c5cc, 0xc5c8a3f0, 
+    0xc5ccc882, 0xe9dfcc83, 0x0d80e7de, 0x838a8289, 0xf6a393e4, 0xecf9df08, 0xedf0a9fa, 0x828922fb, 
+    0xfaec838a, 0xc5c8a3e0, 0xc5ccc882, 0xa3f0cc83, 0xc882c5c8, 0xcc83c5cc, 0xe8deeadf, 0x8289db80, 
+    0x93e4838a, 0xdf08f2a3, 0x88cc80f9, 0x0160eff0, 0xc3604e0e, 0x24edf088, 0x0004b402, 0x82f5b950, 
+    0xb40224eb, 0xaf500004, 0x82452323, 0xdb249023, 0x30d5c273, 0xd5b207f7, 0x05fff063, 0x0ce730f0, 
+    0x04f4d5b2, 0xfff06384, 0x0180f005, 0x02d53084, 0xbb2204f4, 0x82890601, 0x22e0838a, 0x22e70250, 
+    0xe302febb, 0x8a828922, 0x2293e483, 0x890901bb, 0xf8838a82, 0x22f028e0, 0xf7270350, 0x05febb22, 
+    0xf328e3f8, 0x89838a22, 0x93e4f882, 0x01bb2228, 0x8a828906, 0x5022f083, 0xbb22f702, 0x22f301fe, 
+    0xa4f08def, 0x8ccff0a8, 0xce28a4f0, 0x2ea4f08d, 0x9feb22fe, 0x9eeaf0f5, 0x9de9f042, 0x64ecf042, 
+    0x8064c880, 0x22f04598, 0xf0f59feb, 0xf0429eea, 0xf0429de9, 0xf0459ce8, 0x0f60e822, 0xfc13c3ec, 
+    0xeefd13ed, 0x13effe13, 0x22f1d8ff, 0xef0f60e8, 0xeeff33c3, 0x33edfe33, 0xfc33ecfd, 0xbb22f1d8, 
+    0x82890701, 0x2602838a, 0xe90550c1, 0xb52602f8, 0xe905febb, 0xcd2602f8, 0x838a8289, 0xbbd92602, 
+    0x82890701, 0x2602838a, 0xe90550f5, 0xe92602f8, 0xe905febb, 0x012702f8, 0x604eef22, 0x0160ef12, 
+    0x01bbed0e, 0x8a82890b, 0xdfa3f083, 0x22fadefc, 0x0750f089, 0xfcdf09f7, 0xbb22f0a9, 0x09f3fcfe, 
+    0xf0a9fcdf, 0x08fce622, 0xe608fde6, 0xffe608fe, 0xa3fce022, 0xe0a3fde0, 0xffe0a3fe, 0x08fce222, 
+    0xe208fde2, 0xffe208fe, 0xfc93e422, 0xfd930174, 0xfe930274, 0xff930374, 0x08f6ec22, 0xee08f6ed, 
+    0xf6ef08f6, 0xa3f0ec22, 0xeea3f0ed, 0xf0efa3f0, 0x08f2ec22, 0xee08f2ed, 0xf2ef08f2, 0x75128f22, 
+    0x12e5031e, 0x14750770, 0x8013f51f, 0xb412e51a, 0x0d800201, 0x03b412e5, 0x1f147508, 0x8013f5e4, 
+    0x14f5e406, 0x90e11375, 0xfee01c04, 0xeeffe0a3, 0xfde09533, 0x120a78fc, 0x04a83c26, 0x06aa05a9, 
+    0xe0a307ab, 0xffe0a3fe, 0xe09533ee, 0x4febfcfd, 0xfe4eeaff, 0xe8fd4de9, 0x24effc4c, 0xee18f5f1, 
+    0x17f5ff34, 0xf5ff34ed, 0xff34ec16, 0x387f15f5, 0x90807412, 0xf0ee1c04, 0x7ff0efa3, 0x80741239, 
+    0x900354ee, 0xa3f01e04, 0x0490f0ef, 0xa3fee01c, 0x33eeffe0, 0xfcfde095, 0x26120a78, 0xa904a83c, 
+    0xab06aa05, 0xfee0a307, 0xeeffe0a3, 0xfde09533, 0xff4febfc, 0xe9fe4eea, 0x4ce8fd4d, 0xf124effc, 
+    0x34ee1cf5, 0xed1bf5ff, 0x1af5ff34, 0xf5ff34ec, 0x4f049019, 0x64d3ffe0, 0x40809480, 0x90078002, 
+    0xf4e04f04, 0xefd3ff04, 0x81948064, 0x04900840, 0xe7a2e04f, 0x0490f013, 0xf004e053, 0xe0530490, 
+    0x500594d3, 0x231c8538, 0x85221b85, 0x1985211a, 0x51049020, 0x8524f5e0, 0x17852818, 0x26168527, 
+    0x85251585, 0x14852913, 0x4f04902a, 0xe42bf5e0, 0xe0a32cf5, 0x195812ff, 0x80e41d8f, 0x53049042, 
+    0x0794d3e0, 0x1c853f50, 0x221b8523, 0x85211a85, 0x04902019, 0x24f5e051, 0x85281885, 0x16852717, 
+    0x25158526, 0x85291385, 0x04902a14, 0x2bf5e04f, 0xa3012c75, 0x5812ffe0, 0x901d8f19, 0x90e06204, 
+    0x80f04d04, 0x5004900c, 0x901df5e0, 0x01744d04, 0x500490f0, 0x90f0a3e0, 0x1de55004, 0x6012e5f0, 
+    0x0a01b403, 0xe0500490, 0x546f12ff, 0x04900880, 0x12ffe050, 0x0490d25a, 0x0164e04d, 0x29020360, 
+    0x7012e561, 0x50049021, 0x64d3ffe0, 0x40809480, 0x90078002, 0xf4e05004, 0x33efff04, 0xf8543333, 
+    0xf00f0490, 0x12e56b80, 0x902101b4, 0xffe05004, 0x948064d3, 0x80024080, 0x50049007, 0xff04f4e0, 
+    0x333333ef, 0x0490f854, 0x4580f010, 0x02b412e5, 0x50049021, 0x64d3ffe0, 0x40809480, 0x90078002, 
+    0xf4e05004, 0x33efff04, 0xf8543333, 0xf00d0490, 0x04901f80, 0xd3ffe050, 0x80948064, 0x07800240, 
+    0xe0500490, 0xefff04f4, 0x54333333, 0x0e0490f8, 0x22007ff0, 0x75001275, 0x04902013, 0xdd24e040, 
+    0x2a020370, 0x03701408, 0x802e2a02, 0x49049000, 0x901370e0, 0xfee00004, 0x0278e0a3, 0xce13c3ce, 
+    0x20f9d813, 0x007f03e0, 0x0490e422, 0xf0a3f020, 0xe07b0490, 0x05600164, 0x4b0490e4, 0x7c0490f0, 
+    0x904560e0, 0xffe04504, 0xfee09533, 0x1395efc3, 0x1295eeff, 0x94efd3fe, 0x8064ee00, 0x03408094, 
+    0x90f014e0, 0xffe04504, 0xfee09533, 0x1395efc3, 0xc31295ee, 0x80948064, 0x04e00350, 0x200490f0, 
+    0x04a3f0e4, 0x692b02f0, 0xe0030490, 0x12fff824, 0x0490d25a, 0xf0237440, 0xbf205c12, 0x027f0302, 
+    0x53049022, 0x0490ffe0, 0xa3f0e424, 0x0490f0ef, 0x0824e003, 0xd25a12ff, 0x74400490, 0x5c12f024, 
+    0x0302bf20, 0x9022027f, 0xffe05304, 0xe0240490, 0xfde0a3fc, 0xfe9defc3, 0x04909ce4, 0xcea3f024, 
+    0x240490f0, 0xe0a3fee0, 0x903d604e, 0xd3e04b04, 0x03500094, 0xee232b02, 0x80948064, 0x007e0640, 
+    0x0480017f, 0xff7fff7e, 0xe0520490, 0x948064c3, 0x7c064080, 0x80017d00, 0x7dff7c04, 0x706defff, 
+    0x706cee02, 0x232b0203, 0xe4200490, 0xf004a3f0, 0xe0240490, 0xffe0a3fe, 0xee0094d3, 0x80948064, 
+    0x0f800240, 0xe0240490, 0xffe0a3fe, 0xff9fe4c3, 0x90fe9ee4, 0xfde05204, 0x948064d3, 0x80024080, 
+    0x52049007, 0xfd04f4e0, 0xe09533ed, 0x9defd3fc, 0xf88064ec, 0x988064ee, 0x04907640, 0x0164e07a, 
+    0x04902660, 0x33ffe045, 0x90fee095, 0xc3e05204, 0x80948064, 0x007c0640, 0x0480017d, 0xff7dff7c, 
+    0xecff2fed, 0x4380fe3e, 0xe0450490, 0xe09533ff, 0x903880fe, 0x64e07a04, 0xc3276001, 0xe0240490, 
+    0x80948064, 0x007e0640, 0x0480017f, 0xff7fff7e, 0xe0450490, 0xe09533fd, 0x9fedc3fc, 0xfe9eecff, 
+    0x04900980, 0x33ffe045, 0x90fee095, 0xf0ef4504, 0xa3240490, 0x520490e0, 0x450490f0, 0x5e12ffe0, 
+    0x4b04909f, 0x90f004e0, 0x70e02004, 0x64e0a304, 0x90116001, 0xc3e04b04, 0x08501094, 0x747b0490, 
+    0x0580f001, 0x7b0490e4, 0x0490e4f0, 0x12fff040, 0x007fd25a, 0xfe24ef22, 0x2c020370, 0x0370144c, 
+    0x146f2d02, 0x2d020370, 0x03701487, 0x249f2d02, 0x02036004, 0xedd3c22d, 0xc6948064, 0x467d0240, 
+    0x8064edd3, 0x0640bf94, 0xffc124ed, 0x007f0280, 0xffec07ac, 0xfee09533, 0xeea4f5ef, 0x04440154, 
+    0xa775a5f5, 0x2b9a75c0, 0x7580a575, 0xa775ffa6, 0x2b9a757f, 0x9533ffec, 0xf5effee0, 0x0154eea4, 
+    0xa5f50644, 0x75c0a775, 0xa5752b9a, 0xffa67580, 0x757fa775, 0xffec2b9a, 0xfee09533, 0x9533fbed, 
+    0xebc3fae0, 0x9eeaff9f, 0xa4f5effe, 0x440154ee, 0x75a5f502, 0x9a75c0a7, 0xb52d022b, 0x8064edd3, 
+    0x04408094, 0x048005af, 0xff04f4ed, 0x8064efd3, 0x16409f94, 0x8064edd3, 0x04408094, 0x048005af, 
+    0xff04f4ed, 0xffe124ef, 0x007f0280, 0xffec07ac, 0xfee09533, 0xeea4f5ef, 0x0a440154, 0xa775a5f5, 
+    0x2b9a75c0, 0x7580a575, 0xa775ffa6, 0x2b9a757f, 0x9533ffec, 0xf5effee0, 0x0154eea4, 0xa5f50c44, 
+    0x75c0a775, 0xa5752b9a, 0xffa67580, 0x757fa775, 0xedd32b9a, 0x80948064, 0x05af0440, 0xf4ed0480, 
+    0x33efff04, 0xfbece095, 0xfae09533, 0xff9befc3, 0xd3a4f5ef, 0x948064ed, 0xaf044080, 0xed048005, 
+    0xefff04f4, 0xfee09533, 0xee9befc3, 0x4401549a, 0x75a5f508, 0x9a75c0a7, 0x80a5752b, 0x75ffa675, 
+    0x9a757fa7, 0x64edc32b, 0x50809480, 0x80017f04, 0xef007f02, 0xedc3a4f5, 0x80948064, 0x54ee007e, 
+    0xf5144401, 0xc0a775a5, 0x752b9a75, 0xa67580a5, 0x7fa775ff, 0xc32b9a75, 0x948064ed, 0x7f045080, 
+    0x7f028001, 0xa4f5ef00, 0x8064edc3, 0x007e8094, 0x440154ee, 0x75a5f516, 0x9a75c0a7, 0xed46802b, 
+    0xe09533ff, 0xa4f5effe, 0x440154ee, 0x75a5f50e, 0x9a75c0a7, 0xed2e802b, 0xe09533ff, 0xa4f5effe, 
+    0x440154ee, 0x75a5f510, 0x9a75c0a7, 0xed16802b, 0xe09533ff, 0xa4f5effe, 0x440154ee, 0x75a5f512, 
+    0x9a75c0a7, 0x80a5752b, 0x75ffa675, 0x9a757fa7, 0x9022222b, 0x70e06e04, 0x8604901e, 0x7d1860e0, 
+    0x12ffe499, 0x30ee5b74, 0x04900de7, 0xf001746e, 0x107f027d, 0x90b93112, 0x24e04104, 0x0007b4db, 
+    0x2e902350, 0x03f07500, 0x2583c5a4, 0x7383c5f0, 0x02382e02, 0x2f02032f, 0x1d2f0253, 0x026a2f02, 
+    0x2f02902f, 0x02a475b3, 0x75fda675, 0x9a75ffa7, 0x7f027d51, 0xb9311208, 0x90dd6212, 0xf0ee2004, 
+    0xe4f0efa3, 0xf04e0490, 0x7412657f, 0x0154efb3, 0x6f7012f5, 0xc3dd6212, 0xe0210490, 0x0490ff9f, 
+    0xfe9ee020, 0x6494efc3, 0x400094ee, 0x4e04904f, 0x900770e0, 0x20e00004, 0x027d15e0, 0x31120f7f, 
+    0x01a475b9, 0x75fea675, 0x9a75ffa7, 0x7f2d8019, 0xb37412d3, 0x640154ef, 0x75a4f501, 0xa775fea6, 
+    0xd39a75ff, 0x90dd6212, 0xf0ee2004, 0x90f0efa3, 0x01744e04, 0x7f027df0, 0xb931121d, 0x74410490, 
+    0x9022f025, 0x01748604, 0xe4997df0, 0x5b7412ff, 0x148f138e, 0x12037def, 0x3112ba3d, 0xa4f5e4b5, 
+    0x9a75a5f5, 0xa4f5e460, 0x7580a575, 0xf5e4609a, 0x75a5f5a4, 0x0490609a, 0xf0267441, 0xf513f5e4, 
+    0xae14af14, 0xd1551213, 0x600164ef, 0x41049039, 0x7ff02674, 0xb3741265, 0xf50154ef, 0x02037012, 
+    0x0490bf2f, 0xf0147440, 0xf02874a3, 0x12507f22, 0x138e8074, 0x7def148f, 0xba3d1203, 0x90b53112, 
+    0xb4e06904, 0x0490bb01, 0xf0277441, 0xf513f5e4, 0xae14af14, 0xeb611213, 0x600164ef, 0x41049036, 
+    0x7ff02774, 0xb3741265, 0xf50154ef, 0x90606012, 0x14744004, 0x2974a3f0, 0x507f22f0, 0x8e807412, 
+    0xef148f13, 0x3d12037d, 0xb53112ba, 0xe06a0490, 0x90be01b4, 0x44e03d04, 0x0490f004, 0xf02a7441, 
+    0xe03c0490, 0xe02013c3, 0xa4752201, 0xfea67501, 0x75ffa775, 0x027d619a, 0x31120c7f, 0x410490b9, 
+    0x90f02b74, 0x60e06e04, 0x41049006, 0x22f02c74, 0xf5a4f5e4, 0x7fa675a5, 0x75f8a775, 0xa475019a, 
+    0x06a57590, 0x7501a675, 0xf5e4029a, 0xfea675a4, 0x75ffa775, 0xf5e4039a, 0x75a5f5a4, 0xa77580a6, 
+    0x049a7581, 0xf5a4f5e4, 0x3fa675a5, 0x75bfa775, 0xf5e4109a, 0xcfa675a4, 0x75ffa775, 0xa575119a, 
+    0xffa67534, 0x7583a775, 0xa475149a, 0xe0a6750d, 0x75ffa775, 0xa475159a, 0xa5f5e401, 0x75f0a675, 
+    0x9a75fca7, 0xa5f5e418, 0x75ffa675, 0x9a753fa7, 0xa4f5e420, 0xa675a5f5, 0x13a775fd, 0xe4219a75, 
+    0xa5f5a4f5, 0x75c0a675, 0x9a75c0a7, 0xa4f5e422, 0xa675a5f5, 0x13a775fd, 0xe4239a75, 0xa5f5a4f5, 
+    0x75c0a675, 0x9a75c0a7, 0xa5f5e424, 0x75ffa675, 0x9a7513a7, 0xa4f5e425, 0xa675a5f5, 0xc0a775c0, 
+    0xe4269a75, 0xa675a5f5, 0x13a775ff, 0xe4279a75, 0xa5f5a4f5, 0x75c0a675, 0x9a75c0a7, 0xa5f5e428, 
+    0x75ffa675, 0x9a7513a7, 0xa4f5e429, 0xa675a5f5, 0xc0a775c0, 0xe42a9a75, 0xa5f5a4f5, 0x7540a775, 
+    0xf5e42b9a, 0x75a5f5a4, 0xa77503a6, 0x309a7501, 0xf5a4f5e4, 0x319a75a5, 0xf5a4f5e4, 0x329a75a5, 
+    0xf5a4f5e4, 0x339a75a5, 0x75a4f5e4, 0xa775f6a6, 0x409a75ff, 0x75a4f5e4, 0xa775f0a6, 0x419a75ff, 
+    0x75a4f5e4, 0xa775f8a6, 0x429a75ff, 0x75a4f5e4, 0xa775c0a6, 0x439a75ff, 0x75a4f5e4, 0xa775c0a6, 
+    0x449a75ff, 0x75a4f5e4, 0xa775c0a6, 0x459a75ff, 0x75a4f5e4, 0xa775c0a6, 0x469a75ff, 0x75a4f5e4, 
+    0xa775c0a6, 0x479a75ff, 0x75a4f5e4, 0xa775c0a6, 0x489a75ff, 0x75a4f5e4, 0xa77580a6, 0x499a75ff, 
+    0x75a4f5e4, 0xa775fda6, 0x519a75ff, 0xf5a4f5e4, 0x609a75a5, 0x75a4f5e4, 0xa775fea6, 0x619a75ff, 
+    0x75a4f5e4, 0xa7757fa6, 0x909a75ff, 0x75a4f5e4, 0xa775fea6, 0x989a75ff, 0x75a5f5e4, 0xa775ffa6, 
+    0xd19a75fb, 0x7f037d22, 0x901a8f09, 0xf5e05a00, 0xf5e0a31b, 0x041d751c, 0x941ce5c3, 0x941be5f8, 
+    0x02034002, 0x1ae59133, 0x03500094, 0xe5913302, 0x4033941a, 0x91330203, 0xe0650090, 0x03700164, 
+    0x90913302, 0xc3e00504, 0x0203509d, 0x00909133, 0xffb4e05d, 0x241ce515, 0x35e4ff08, 0xefd3fe1b, 
+    0x94eef894, 0x02034002, 0x33e59133, 0x32020360, 0xcb7212e3, 0x358f348e, 0xe0600090, 0x5411e030, 
+    0x0090f0fe, 0xf004e067, 0x00900670, 0xf004e066, 0x670090d3, 0x900094e0, 0x94e06600, 0x02035000, 
+    0x0274e332, 0x82f51c25, 0x1b350174, 0xff7483f5, 0x660090f0, 0xe0a3fce0, 0x74ffecfd, 0xf51c2501, 
+    0x35017482, 0xef83f51b, 0x250074f0, 0x7482f51c, 0xf51b3501, 0x74f0ed83, 0xf51c2503, 0x1b35e41c, 
+    0xe5c31bf5, 0xe5f8941c, 0x4002941b, 0x1ef5e43f, 0x08241ce5, 0x341be5ff, 0xe5c3fefd, 0x9ee49f1e, 
+    0xf8741e50, 0x82f51e25, 0xf50334e4, 0x74ffe083, 0xf51e2500, 0x0134e482, 0xf0ef83f5, 0xd0801e05, 
+    0x1c250874, 0xfd741cf5, 0x1bf51b35, 0x660090e4, 0xe5f0a3f0, 0xc433251d, 0x45e05433, 0x0374ff38, 
+    0x82f51c25, 0x1b350174, 0xf0ef83f5, 0x74ff34e5, 0xf51c2502, 0x35017482, 0xef83f51b, 0x250174f0, 
+    0x7482f51c, 0xf51b3501, 0xf035e583, 0x1c250074, 0x017482f5, 0x83f51b35, 0x74f01ae5, 0xf51c2504, 
+    0x1b35e41c, 0xe5c31bf5, 0xe5f8941c, 0x4002941b, 0x1ef5e43f, 0x08241ce5, 0x341be5ff, 0xe5c3fefd, 
+    0x9ee49f1e, 0xf8741e50, 0x82f51e25, 0xf50334e4, 0x74ffe083, 0xf51e2500, 0x0134e482, 0xf0ef83f5, 
+    0xd0801e05, 0x1c250874, 0xfd741cf5, 0x1bf51b35, 0xf534f5e4, 0x9033f535, 0x1be55a00, 0x1ce5a3f0, 
+    0x3b7f22f0, 0xefae7412, 0x7eff0754, 0xc006c000, 0x123b7f07, 0x54efae74, 0x1313133f, 0xd0fd1f54, 
+    0xd0ff2de0, 0xc30034e0, 0x13effe13, 0xc006c0ff, 0x123b7f07, 0x54efb374, 0xe0d0fd3f, 0xd014f52d, 
+    0xf50034e0, 0x123c7f13, 0x54efb374, 0x007eff1f, 0x07c006c0, 0x74123c7f, 0x3f54efae, 0x54131313, 
+    0xe0d0fd1f, 0xd01ef52d, 0xf50034e0, 0x123c7f1d, 0x54efb374, 0x1313c47f, 0x01640354, 0x95c30a70, 
+    0x95e4ff1e, 0x0480fe1d, 0x1eaf1dae, 0x188f178e, 0x74123c7f, 0x1f54efb3, 0xc0007eff, 0x7f07c006, 
+    0xae74123c, 0xfd0754ef, 0xf52de0d0, 0x34e0d020, 0x7f1ff500, 0xb374123c, 0xc43f54ef, 0x64075413, 
+    0xc30a7001, 0xe4ff2095, 0x80fe1f95, 0xaf1fae04, 0x2f18e520, 0x3e17e5ff, 0xf513e7a2, 0xf513ef15, 
+    0x123d7f16, 0x54efb374, 0x007eff3f, 0x007c207d, 0xefb47312, 0xf5e09533, 0x7f1a8f19, 0x8074123d, 
+    0xfe0754ee, 0x047c007d, 0xefb47312, 0xa2ce0678, 0x13ce13e7, 0x33fff8d8, 0x1bf5e095, 0x3d7f1c8f, 
+    0xef807412, 0xa2ce0b78, 0x13ce13e7, 0x33fff8d8, 0xd3fee095, 0x009416e5, 0x806415e5, 0x06408094, 
+    0x16ad15ac, 0xe4c30980, 0xe4fd1695, 0xd3fc1595, 0x009414e5, 0x806413e5, 0x06408094, 0x14ab13aa, 
+    0xe4c30980, 0xe4fb1495, 0xebfa1395, 0x3ceafd2d, 0x1ae5d3fc, 0x19e50094, 0x80948064, 0x19aa0640, 
+    0x09801aab, 0x1a95e4c3, 0x1995e4fb, 0xfd2bedfa, 0xd3fc3aec, 0x00941ce5, 0x80641be5, 0x06408094, 
+    0x1cab1baa, 0xe4c30980, 0xe4fb1c95, 0xedfa1b95, 0x3aecfd2b, 0x94efd3fc, 0x8064ee00, 0x02408094, 
+    0xe4c30780, 0x9ee4ff9f, 0xff2fedfe, 0x22fe3eec, 0x8fba6712, 0x74741212, 0x020370ef, 0x04902337, 
+    0x94c3e015, 0x0094e4fb, 0x37020340, 0x24049023, 0xa30470e0, 0x706364e0, 0x23370203, 0xe0490490, 
+    0x387f3070, 0xee807412, 0xfde09533, 0x120a78fc, 0x04c03c26, 0x06c005c0, 0x397f07c0, 0xee807412, 
+    0xd0fe0354, 0xd002d003, 0xeb00d001, 0x4eeaff4f, 0x04907180, 0xa3fee024, 0x94c3ffe0, 0x8064eef0, 
+    0x36407f94, 0x0f94efd3, 0x948064ee, 0x7f2b5080, 0x80741234, 0xe09533ee, 0x0a78fcfd, 0xc03c2612, 
+    0xc005c004, 0x7f07c006, 0xb3741235, 0x02d003d0, 0x00d001d0, 0xeaff4feb, 0x367f2980, 0xee807412, 
+    0xfde09533, 0x120a78fc, 0x04c03c26, 0x06c005c0, 0x377f07c0, 0xd0b37412, 0xd002d003, 0xeb00d001, 
+    0xfeeaff4f, 0xfce8fde9, 0x75d15f12, 0x38e502f0, 0xf5c124a4, 0x34f0e582, 0xe483f577, 0x0174fc93, 
+    0x0490fd93, 0x7afbe077, 0xfd2bed00, 0x74fc3cea, 0x82f52d00, 0xf53c0174, 0xc3f0ef83, 0xe0250490, 
+    0x04901f94, 0x8064e024, 0x0d508094, 0x12056612, 0x04900e71, 0xf012e577, 0x0a741222, 0x8064efd3, 
+    0x03506194, 0x901a3702, 0x70e04904, 0x12c17f0c, 0x017f5f6a, 0x805f6a12, 0x12047f0e, 0xa5755f6a, 
+    0xffa67502, 0x90329a75, 0xff742404, 0xe174a3f0, 0x0a7412f0, 0x12ff14ef, 0x7112546f, 0x7704900e, 
+    0x75f012e5, 0x38e502f0, 0xf5c124a4, 0x34f0e582, 0xe483f577, 0x0174fe93, 0x0490ff93, 0x7cfde077, 
+    0xff2def00, 0x74fe3eec, 0x82f52f00, 0xf53e0174, 0xe5f0e483, 0xff94c312, 0x007f0440, 0x04900680, 
+    0xff04e077, 0xef770490, 0x049022f0, 0xa3f0e424, 0x22f06374, 0xe0400490, 0x0370f024, 0x80f23702, 
+    0x49049000, 0x020360e0, 0x04906538, 0xe030e087, 0x65380203, 0x90c86c12, 0xfee00004, 0x0278e0a3, 
+    0xce13c3ce, 0x20f9d813, 0x0c7f05e0, 0x90ed6f12, 0xfee00004, 0x0278e0a3, 0xce13c3ce, 0x30f9d813, 
+    0x049064e0, 0x0164e04c, 0x04901e60, 0x0b60e07c, 0x0490ff74, 0xf0a3f028, 0x12103802, 0x04901f42, 
+    0xa3f0ee28, 0x7880f0ef, 0xe0550490, 0x04900670, 0xf0a3f028, 0xe07c0490, 0x04901060, 0xff24e029, 
+    0x280490f0, 0xf0ff34e0, 0x42120f80, 0x2904901f, 0x90f02fe0, 0x3ee02804, 0x550490f0, 0xe0f004e0, 
+    0x70700864, 0x04906680, 0xa3fee000, 0xce0278e0, 0x13ce13c3, 0xe020f9d8, 0x0e71125b, 0x74400490, 
+    0x7412f010, 0x0370ef74, 0x9022027f, 0x64e04c04, 0x7f126001, 0x80741238, 0xee280490, 0xf0efa3f0, 
+    0x80d65012, 0x5504902f, 0x900670e0, 0xa3f02804, 0x12387ff0, 0x04908074, 0xf02fe029, 0xe0280490, 
+    0x0490f03e, 0xf004e055, 0x0808b4e0, 0xe4d65012, 0xf0550490, 0xe0000490, 0x78e0a3fe, 0x13c3ce02, 
+    0xf9d813ce, 0x0203e030, 0x0490dd38, 0x0370e05c, 0x805f3702, 0x49049078, 0x700164e0, 0x8704906a, 
+    0x63e020e0, 0x90c86c12, 0x64e04c04, 0x12106001, 0x0490c25c, 0xa3f0ee28, 0x5012f0ef, 0x902d80d6, 
+    0x70e05504, 0x28049006, 0x12f0a3f0, 0x0490c25c, 0xf02fe029, 0xe0280490, 0x0490f03e, 0xf004e055, 
+    0x0808b4e0, 0xe4d65012, 0xf0550490, 0xe0000490, 0x78e0a3fe, 0x13c3ce02, 0xf9d813ce, 0x900ee020, 
+    0x60e05c04, 0x900680a2, 0x01745c04, 0x400490f0, 0x7ff03374, 0xf5e42200, 0x49049012, 0x1960ffe0, 
+    0x901301b4, 0xfee00004, 0x0278e0a3, 0xce13c3ce, 0x20f9d813, 0x3a0203e0, 0x87049028, 0x1313ffe0, 
+    0xe0303f54, 0x283a0203, 0xe05f0090, 0xe0000490, 0x78e0a3fe, 0x13c3ce02, 0xf9d813ce, 0x30530490, 
+    0x057405e0, 0x740380f0, 0x0490f014, 0xa3fee000, 0xce0278e0, 0x13ce13c3, 0xe030f9d8, 0x7873120b, 
+    0xee200490, 0xf0efa3f0, 0x90b06412, 0xf0ee2404, 0x12f0efa3, 0x04908b74, 0xf5f0ef56, 0x5f009012, 
+    0x000490e0, 0xe0a3fee0, 0xc3ce0278, 0xd813ce13, 0x66e030f9, 0xe07c0490, 0x04900b60, 0x94c3e056, 
+    0x8002500f, 0x20049065, 0xe0a3fee0, 0x250490ff, 0x90fd2fe0, 0x3ee02404, 0x94edc3fc, 0x0294ecee, 
+    0x04901a50, 0x1470e082, 0x7794efc3, 0x500194ee, 0x5604900b, 0x2d94c3e0, 0x2e800250, 0x3994edd3, 
+    0x500394ec, 0x82049006, 0x903760e0, 0xffe05304, 0xe0560490, 0x2a409fd3, 0x04902580, 0x70ffe082, 
+    0x5604900e, 0x2d94c3e0, 0x04e01850, 0xef1380f0, 0x04901060, 0x90ffe053, 0xd3e05604, 0xe003409f, 
+    0x0490f014, 0x12ffe056, 0xfee0bb74, 0x08601265, 0xe05e0490, 0x0901b4fd, 0x745e0490, 0x007ff001, 
+    0x95d3ee22, 0xed234012, 0x07600464, 0xe04c0490, 0x900801b4, 0x02745e04, 0x900680f0, 0x03745e04, 
+    0x560490f0, 0x1295c3e0, 0x049022ff, 0x0364e05e, 0x04900760, 0x01b4e04c, 0x5e049008, 0x80f00274, 
+    0x5e049006, 0x90f00474, 0xffe05604, 0x9f12e5c3, 0x22ff04f4, 0x8fba6712, 0x74741212, 0x020370ef, 
+    0x04901f3c, 0x94c3e015, 0x0094e4fb, 0x3c020340, 0x2404901f, 0xa30470e0, 0x706364e0, 0x1f3c0203, 
+    0xe0490490, 0x387f3070, 0xee807412, 0xfde09533, 0x120a78fc, 0x04c03c26, 0x06c005c0, 0x397f07c0, 
+    0xee807412, 0xd0fe0354, 0xd002d003, 0xeb00d001, 0x4eeaff4f, 0x04907180, 0xa3fee024, 0x94c3ffe0, 
+    0x8064eef0, 0x36407f94, 0x0f94efd3, 0x948064ee, 0x7f2b5080, 0x80741234, 0xe09533ee, 0x0a78fcfd, 
+    0xc03c2612, 0xc005c004, 0x7f07c006, 0xb3741235, 0x02d003d0, 0x00d001d0, 0xeaff4feb, 0x367f2980, 
+    0xee807412, 0xfde09533, 0x120a78fc, 0x04c03c26, 0x06c005c0, 0x377f07c0, 0xd0b37412, 0xd002d003, 
+    0xeb00d001, 0xfeeaff4f, 0xfce8fde9, 0x75d15f12, 0x38e502f0, 0xf5c124a4, 0x34f0e582, 0xe483f577, 
+    0x0174fc93, 0x0490fd93, 0x7afbe077, 0xfd2bed00, 0x74fc3cea, 0x82f52d00, 0xf53c0174, 0x12f0ef83, 
+    0xefd30a74, 0x61948064, 0x90c37350, 0x94e02504, 0x2404901f, 0x948064e0, 0x12585080, 0x1f7f0566, 
+    0x12546f12, 0x04900e71, 0xf012e577, 0xe502f075, 0xc124a438, 0xf0e582f5, 0x83f57734, 0x74fe93e4, 
+    0x90ff9301, 0xfde07704, 0x2def007c, 0xfe3eecff, 0xf52f0074, 0x3e017482, 0xf0e483f5, 0x94c312e5, 
+    0x7f0440ff, 0x90068000, 0x04e07704, 0x770490ff, 0x9022f0ef, 0xf0e42404, 0xf06374a3, 0x0a741222, 
+    0x12ff14ef, 0x7112546f, 0x7704900e, 0x22f012e5, 0x7501a575, 0xa775ffa6, 0x409a75fe, 0x75c0a575, 
+    0xa775ffa6, 0x209a753f, 0xe0500090, 0xe0a313c3, 0x54007e13, 0x94d3ff1f, 0x0094ee10, 0x04901e40, 
+    0x54c4e07f, 0x09e0200f, 0x1694efd3, 0x400094ee, 0x8804900b, 0x5413c4e0, 0x04e03007, 0x0280017f, 
+    0x25ef007f, 0xf50254e0, 0x500090a4, 0xa313c3e0, 0x007e13e0, 0xd3ff1f54, 0x94ee1094, 0x90204000, 
+    0xc4e07f04, 0xe0200f54, 0x94efd309, 0x0094ee16, 0x04900d40, 0x13c4e088, 0xe0300754, 0x74008002, 
+    0x75a5f504, 0xa775fda6, 0x219a7593, 0x7520a475, 0xa67520a5, 0xc0a775c0, 0x90229a75, 0xc3e05000, 
+    0x13e0a313, 0x1f54007e, 0x1094d3ff, 0x400094ee, 0x7f04901f, 0x0f54c4e0, 0xd309e020, 0xee1694ef, 
+    0x0c400094, 0xe0880490, 0x541313c4, 0x04e03003, 0x0280017f, 0x25ef007f, 0xf50254e0, 0x500090a4, 
+    0xa313c3e0, 0x007e13e0, 0xd3ff1f54, 0x94ee1094, 0x90214000, 0xc4e07f04, 0xe0200f54, 0x94efd309, 
+    0x0094ee16, 0x04900e40, 0x13c4e088, 0x30035413, 0x008002e0, 0xa5f50474, 0x75fda675, 0x9a7593a7, 
+    0x20a47523, 0x7520a575, 0xa775c0a6, 0x249a75c0, 0x7504a575, 0xa775ffa6, 0x259a7593, 0x7520a475, 
+    0xa67520a5, 0xc0a775c0, 0x75269a75, 0xa67504a5, 0x93a775ff, 0x75279a75, 0xa57520a4, 0xc0a67520, 
+    0x75c0a775, 0xa575289a, 0xffa67504, 0x7593a775, 0xa475299a, 0x20a57520, 0x75c0a675, 0x9a75c0a7, 
+    0x0490222a, 0xffe0a300, 0x1a8f027d, 0xe05a0090, 0xe0a31bf5, 0xe5c31cf5, 0xe5f8941c, 0x4002941b, 
+    0x3a3f0203, 0xe0650090, 0x03700164, 0x903a3f02, 0xc3e00504, 0x0203509d, 0x00903a3f, 0xffb4e05d, 
+    0x241ce515, 0x35e4ff0c, 0xefd3fe1b, 0x94eef894, 0x02034002, 0x33e53a3f, 0x3e020360, 0xcb7212cf, 
+    0x358f348e, 0xe0600090, 0x5411e030, 0x0090f0fe, 0xf004e067, 0x00900670, 0xf004e066, 0x670090d3, 
+    0x900094e0, 0x94e06600, 0x02035000, 0x0274cf3e, 0x82f51c25, 0x1b350174, 0xff7483f5, 0x660090f0, 
+    0xe0a3fce0, 0x74ffecfd, 0xf51c2501, 0x35017482, 0xef83f51b, 0x250074f0, 0x7482f51c, 0xf51b3501, 
+    0x74f0ed83, 0xf51c2503, 0x1b35e41c, 0xe5c31bf5, 0xe5f8941c, 0x4002941b, 0x1df5e43f, 0x08241ce5, 
+    0x341be5ff, 0xe5c3fefd, 0x9ee49f1d, 0xf8741e50, 0x82f51d25, 0xf50334e4, 0x74ffe083, 0xf51d2500, 
+    0x0134e482, 0xf0ef83f5, 0xd0801d05, 0x1c250874, 0xfd741cf5, 0x1bf51b35, 0x660090e4, 0x74f0a3f0, 
+    0xf51c2500, 0x35017482, 0xe583f51b, 0x1c05f01a, 0x02701ce5, 0x94c31b05, 0x941be5f8, 0xe43f4002, 
+    0x1ce51df5, 0xe5ff0824, 0xfefd341b, 0x9f1de5c3, 0x1e509ee4, 0x1d25f874, 0x34e482f5, 0xe083f503, 
+    0x250074ff, 0xe482f51d, 0x83f50134, 0x1d05f0ef, 0x0874d080, 0x1cf51c25, 0x1b35fd74, 0x33051bf5, 
+    0xe55a0090, 0xe5a3f01b, 0x9022f01c, 0x90e04504, 0x90f04f04, 0xffe00d04, 0x9fc3e0a3, 0x0094e4ff, 
+    0xfe13e7a2, 0x90ff13ef, 0xf0ee2404, 0x90f0efa3, 0x64e04c04, 0x90367001, 0xc3e07d04, 0x51400794, 
+    0x0490f0e4, 0xa3fce024, 0x94d3fde0, 0x8064ec0c, 0x07408094, 0xe0450490, 0xc3328014, 0xecf494ed, 
+    0x7f948064, 0x04902b50, 0x8004e045, 0x25049020, 0xff0424e0, 0xe0240490, 0xeffe0034, 0xa2ce0378, 
+    0x13ce13e7, 0x90fff8d8, 0xc3e04504, 0x4f04909f, 0x4f0490f0, 0x64c3ffe0, 0x50989480, 0xf0187405, 
+    0xefd30e80, 0xac948064, 0x04900640, 0xf02c744f, 0xe04f0490, 0x450490ff, 0x706ffee0, 0xb5400203, 
+    0x9533fdee, 0x33effce0, 0xc3fee095, 0xeeff9def, 0x78effe9c, 0xce33c303, 0xf9d8ce33, 0x240490ff, 
+    0xefa3f0ee, 0x4f0490f0, 0x0490ffe0, 0x5e12f045, 0x0e04909f, 0x0490ffe0, 0xff2fe025, 0xe0240490, 
+    0x90fe0034, 0xa3f02604, 0xeec3f0ef, 0x80948064, 0x90e40950, 0xa3f02604, 0xd31780f0, 0xe0270490, 
+    0x0490f894, 0x8064e026, 0x06408094, 0x74a3f0e4, 0x0490f0f8, 0x90e0a326, 0x90f00e04, 0xffe00d04, 
+    0xe0240490, 0xfde0a3fc, 0xff9defc3, 0xa3fe9ce4, 0xf0efa3f0, 0x8064eec3, 0x09508094, 0x260490e4, 
+    0x80f0a3f0, 0x0490d317, 0xf894e027, 0xe0260490, 0x80948064, 0xf0e40640, 0xf0f874a3, 0xa3260490, 
+    0x0d0490e0, 0x22007ff0, 0x838c828d, 0x047907ad, 0x017afce4, 0x6423e5d3, 0x64edf880, 0x22509880, 
+    0x806423e5, 0x8064ebf8, 0xc3175098, 0x806422e5, 0x8064edf8, 0xe50b4098, 0xf8806422, 0x988064eb, 
+    0x007f0350, 0x6d24e522, 0x82e55370, 0x02708345, 0xebd322ff, 0xedf88064, 0x40988064, 0xd3ff7a02, 
+    0x009482e5, 0x806483e5, 0x06408094, 0x82af83ae, 0xe4c30980, 0xe4ff8295, 0x8efe8395, 0xd3268f25, 
+    0x009421e5, 0x806420e5, 0x06408094, 0x21af20ae, 0xe4c36180, 0xe4ff2195, 0x80fe2095, 0x6b24e556, 
+    0x21e55770, 0x02702045, 0xedd322ff, 0xebf88064, 0x40988064, 0xd3ff7a02, 0x009421e5, 0x806420e5, 
+    0x06408094, 0x21af20ae, 0xe4c30980, 0xe4ff2195, 0x8efe2095, 0xd3268f25, 0x009482e5, 0x806483e5, 
+    0x06408094, 0x82af83ae, 0xe4c30980, 0xe4ff8295, 0x8efe8395, 0x80288f27, 0x22007f03, 0xd3edfde4, 
+    0xc3505099, 0x289526e5, 0x806427e5, 0x6425e5f8, 0x50ec9880, 0xfce0251e, 0x9528e5c3, 0x27e5cf26, 
+    0x24cf2595, 0x0034cf01, 0xf513e7a2, 0xf513ef27, 0x251d8028, 0xc3fc04e0, 0x289526e5, 0x9525e5cf, 
+    0x0124cf27, 0xa20034cf, 0x25f513e7, 0x26f513ef, 0xecab800d, 0xe09533ff, 0x0124effe, 0xa23ee4ff, 
+    0x13ef13e7, 0x04ffbafc, 0x22ff04f4, 0x7f2204af, 0xae74123b, 0xff0754ef, 0x06c0007e, 0x3b7f07c0, 
+    0xefae7412, 0x13133f54, 0xfd1f5413, 0xff2de0d0, 0x0034e0d0, 0xeffe13c3, 0x06c0ff13, 0x3b7f07c0, 
+    0xefb37412, 0xd0fd3f54, 0x13f52de0, 0x0034e0d0, 0x3c7f12f5, 0xefb37412, 0x7eff1f54, 0xc006c000, 
+    0x123c7f07, 0x54efae74, 0x1313133f, 0xd0fd1f54, 0x1bf52de0, 0x0034e0d0, 0x3c7f1af5, 0xefb37412, 
+    0x13c47f54, 0x64035413, 0xc30a7001, 0xe4ff1b95, 0x80fe1a95, 0xaf1aae04, 0x8f168e1b, 0x123c7f17, 
+    0x54efb374, 0x007eff1f, 0x07c006c0, 0x74123c7f, 0x0754efae, 0x2de0d0fd, 0xe0d01df5, 0x1cf50034, 
+    0x74123c7f, 0x3f54efb3, 0x075413c4, 0x0a700164, 0xff1d95c3, 0xfe1c95e4, 0x1cae0480, 0x17e51daf, 
+    0x16e5ff2f, 0x13e7a23e, 0x13ef14f5, 0x3d7f15f5, 0xefb37412, 0x7eff3f54, 0x7c207d00, 0xb4731200, 
+    0xe09533ef, 0x198f18f5, 0x192515e5, 0x14e51ff5, 0x1ef51835, 0x74123d7f, 0x0754ee80, 0x7c007dfe, 
+    0xb4731204, 0xce0678ef, 0xce13e7a2, 0xfff8d813, 0xfee09533, 0xfde025ef, 0xe5fc33ee, 0xffe02519, 
+    0xfe3318e5, 0xcf2f1fe5, 0xcf3e1ee5, 0xfe3ccf2d, 0x07c006c0, 0x74123d7f, 0x0b78ef80, 0x13e7a2ce, 
+    0xf8d813ce, 0xe09533fd, 0x2de0d0fc, 0x3ce0d0ff, 0x5f0090fe, 0x2d7f22e0, 0x12bb7412, 0x04908b74, 
+    0x75f0ef56, 0xa67508a4, 0xffa775f6, 0xe4409a75, 0x546f12ff, 0xe0000490, 0xfde0a3fc, 0x077804ae, 
+    0xce13c3ce, 0x20f9d813, 0x049032e0, 0xe020e006, 0x04aeed2b, 0xc3ce0278, 0xd813ce13, 0x10e030f9, 
+    0xe0890490, 0xa4750560, 0x75088001, 0x038004a4, 0x7507a475, 0xa775f0a6, 0x419a75ff, 0xe0490490, 
+    0x60142460, 0x60fb2418, 0x60fe2408, 0x70052404, 0x4504904a, 0xa3f02a74, 0x80f01574, 0x0490e447, 
+    0xf0a3f045, 0x04903e80, 0x30ffe004, 0x7f5408e7, 0xf0450490, 0x04901e80, 0xa3fee000, 0xce0278e0, 
+    0x13ce13c3, 0x0490f9d8, 0x05e03045, 0x80f02474, 0xf0207403, 0x460490e4, 0x900980f0, 0x20744504, 
+    0xf0a3e4f0, 0xe0500090, 0xe0a313c3, 0xc31f5413, 0x94e40594, 0x6d049000, 0xff740550, 0x740380f0, 
+    0x0490f0fe, 0x12ffe045, 0x04909f5e, 0x12ffe046, 0x0490d25a, 0xa3fee000, 0xce0278e0, 0x13ce13c3, 
+    0xe030f9d8, 0x203c1203, 0xe0490490, 0x1f700164, 0xe0000490, 0x78e0a3fe, 0x13c3ce02, 0xf9d813ce, 
+    0x750ce030, 0xa67501a4, 0xffa775fe, 0x75989a75, 0xa67520a4, 0xffa775df, 0x90109a75, 0x01744404, 
+    0x049022f0, 0xe024e040, 0x70145360, 0xf4450203, 0x6c120080, 0x490490c8, 0x020360e0, 0x0490b045, 
+    0xa3fee000, 0xce0278e0, 0x13ce13c3, 0xe020f9d8, 0xb0450203, 0x74500490, 0xa3e4f001, 0x500490f0, 
+    0x6612ffe0, 0x2760efe3, 0xe48d6812, 0xf04d0490, 0xf04b0490, 0x900e7112, 0x20744004, 0x747412f0, 
+    0x7f0370ef, 0x18122202, 0x4d0490d3, 0x90e560e0, 0xc3e05000, 0x13e0a313, 0x1f54007e, 0x1094d3ff, 
+    0x400094ee, 0x7f049040, 0x0f54c4e0, 0xd309e020, 0xee1694ef, 0x2d400094, 0xe0500490, 0x0b01b4ff, 
+    0xe0880490, 0x075413c4, 0xef10e030, 0x901602b4, 0xc4e08804, 0x03541313, 0x900ae020, 0x70e05104, 
+    0x80f00404, 0x0490e40b, 0x0490f051, 0xf004e050, 0xe0500490, 0x948064c3, 0x02035086, 0x65800d45, 
+    0xe0490490, 0x5d700164, 0xe0000490, 0x78e0a3fe, 0x13c3ce02, 0xf9d813ce, 0x904ae030, 0x02745004, 
+    0xf0a3e4f0, 0xe0500490, 0xe36612ff, 0x122760ef, 0x90e48d68, 0x90f04d04, 0x12f04b04, 0x04900e71, 
+    0xf0217440, 0xef747412, 0x027f0370, 0xd3181222, 0xe04d0490, 0x0490e560, 0x0224e050, 0x64c3e0f0, 
+    0x40859480, 0x0490e4bf, 0x22fff040, 0x900a7412, 0xf0ef4f04, 0x140490e4, 0x90f0a3f0, 0x54e01704, 
+    0x0094d308, 0xf5e40540, 0x750380a4, 0xa67508a4, 0xffa775f7, 0x90409a75, 0x54e01704, 0x0008b407, 
+    0x46020340, 0x5c4690f8, 0x732828f8, 0x02744602, 0x46028346, 0xad460292, 0x02c84602, 0x4602ca46, 
+    0xe44602cf, 0x6f121f7f, 0x46049054, 0x5a12ffe0, 0x7f5680d2, 0x546f12e1, 0xe0460490, 0xd25a12ff, 
+    0xffe45c80, 0x90546f12, 0x70e04904, 0x12207f09, 0xff7f5f6a, 0xfe7f0280, 0x805f6a12, 0x12ffe42c, 
+    0x0490546f, 0x0970e049, 0x6a12e07f, 0x80017f5f, 0x12027f02, 0x26805f6a, 0x47120080, 0x7f298053, 
+    0x096a1220, 0x6a12ff7f, 0x24049009, 0x74a3f0e4, 0x1480f01f, 0x6a12e07f, 0x12017f09, 0x0490096a, 
+    0xf0ff7424, 0xf0e174a3, 0xe0170490, 0x1234e220, 0x04909673, 0x94d3e049, 0x90254000, 0xffe01704, 
+    0x94d30254, 0xef194000, 0x94d30154, 0x75084001, 0xa67502a5, 0x750680ff, 0xa67508a5, 0x329a75ff, 
+    0x120e7112, 0x017beb6e, 0x5479047a, 0xe4746612, 0xf0160490, 0xf0770490, 0xf0380490, 0xf0a3f0a3, 
+    0xe422f0a3, 0xf0260490, 0x447ff0a3, 0xefb37412, 0x7eff3f54, 0x7c207d00, 0xb4731200, 0xe09533ef, 
+    0x90c07412, 0xf0ef7804, 0x7412437f, 0x3f54efb3, 0x7d007eff, 0x12007c20, 0x7412b473, 0x790490c0, 
+    0x64d3f0ef, 0x40809480, 0x80ffe004, 0x79049007, 0xff04f4e0, 0xe0780490, 0x8064d3fe, 0x02408094, 
+    0x04900780, 0x04f4e078, 0x64efd3fe, 0x64eef880, 0x07409880, 0xe0270490, 0x90f00444, 0xd3e07804, 
+    0x80948064, 0x04900740, 0x0244e027, 0x790490f0, 0x8064d3e0, 0x07408094, 0xe0270490, 0x90f00144, 
+    0xc4e01704, 0x60140354, 0x59601449, 0x24696014, 0x02036003, 0x04908748, 0xa3fee026, 0x94c3ffe0, 
+    0x8064ee04, 0x0a408094, 0x13e7a2ee, 0x007e13ef, 0x007e0680, 0xe0270490, 0xc3ff0154, 0xe0270490, 
+    0x04900494, 0x8064e026, 0x007d8094, 0x017d0240, 0x04904280, 0x0154e017, 0x7f0094d3, 0x7f024000, 
+    0x80fde401, 0x1704902f, 0xd30154e0, 0x007f0094, 0x017f0240, 0x1c80017d, 0xe0260490, 0xa313e7a2, 
+    0x015413e0, 0x12017dff, 0x04903c54, 0x54e0a326, 0xfde4ff01, 0x223c5412, 0x04901d8f, 0xa3f0e424, 
+    0xedf00e74, 0x49020370, 0x601de527, 0x12447f3a, 0x54efb374, 0x007eff3f, 0x007c207d, 0x12b47312, 
+    0x0490c074, 0x64c3e078, 0x64eff880, 0x17509880, 0x7412447f, 0x3f54efb3, 0x7d007eff, 0x12007c20, 
+    0x24efb473, 0xe5428001, 0x0203601d, 0x447faf49, 0xefb37412, 0x7eff3f54, 0x7c207d00, 0xb4731200, 
+    0x90c07412, 0xd3e07804, 0xeff88064, 0x50988064, 0xaf490203, 0x7412447f, 0x3f54efb3, 0x7d007eff, 
+    0x12007c20, 0x24efb473, 0xf5efffff, 0xc0a675a4, 0x75ffa775, 0xe522449a, 0x7f3a601d, 0xb3741243, 
+    0xff3f54ef, 0x207d007e, 0x7312007c, 0xc07412b4, 0xe0790490, 0xf88064c3, 0x988064ef, 0x437f1750, 
+    0xefb37412, 0x7eff3f54, 0x7c207d00, 0xb4731200, 0x800124ef, 0x701de53c, 0x12437f46, 0x54efb374, 
+    0x007eff3f, 0x007c207d, 0x12b47312, 0x0490c074, 0x64d3e079, 0x64eff880, 0x23409880, 0x7412437f, 
+    0x3f54efb3, 0x7d007eff, 0x12007c20, 0x24efb473, 0xf5efffff, 0xc0a675a4, 0x75ffa775, 0xe422439a, 
+    0xf0240490, 0x9022f0a3, 0x24e04004, 0x805d60ee, 0x49049000, 0x020360e0, 0x04909b4a, 0xc4ffe087, 
+    0x03541313, 0x0203e030, 0x6c129b4a, 0x0a7412c8, 0xef4e0490, 0x460490f0, 0x520490e0, 0x120f7ff0, 
+    0x90e47f6e, 0x90f04b04, 0xffe04b04, 0x500494c3, 0xb4e0a34c, 0x59120501, 0x9008807d, 0xffe04b04, 
+    0x12c86312, 0x04900e71, 0xf0127440, 0xef747412, 0x027f0370, 0x4c049022, 0x0b01b4e0, 0xe04b0490, 
+    0xd11e12ff, 0x900880ef, 0xffe04b04, 0x900d2712, 0x60e04d04, 0x4b0490ce, 0x80f004e0, 0x520490aa, 
+    0x5a12ffe0, 0x4e0490d2, 0x6f12ffe0, 0x456e1254, 0x700164ef, 0x06049036, 0x13c4ffe0, 0x20035413, 
+    0x017d29e0, 0x31121b7f, 0x7f0490b9, 0x1313ffe0, 0x201f5413, 0xa4750fe0, 0xfea67501, 0x75ffa775, 
+    0x017f199a, 0x8b049022, 0x90f00174, 0x30744004, 0x7d0490f0, 0x90f004e0, 0x70e04904, 0x00049033, 
+    0xe0a3fce0, 0x7804aefd, 0x13c3ce02, 0xf9d813ce, 0xed1de020, 0x077804ae, 0xce13c3ce, 0x20f9d813, 
+    0x04900ee0, 0xc4ffe087, 0xe0200f54, 0x3b3f0203, 0x7522007f, 0x21750020, 0x16227500, 0x007a007b, 
+    0x1d8b1279, 0x1f891e8a, 0x21aa20ab, 0x261222a9, 0x1203784f, 0x007b2926, 0x2379007a, 0x75925212, 
+    0x38e502f0, 0xf5c124a4, 0x34f0e582, 0xe483f577, 0x0174fc93, 0x0490fd93, 0xfbfee077, 0x2bed007a, 
+    0xfc3ceafd, 0xf52d0074, 0x3c017482, 0xf0ef83f5, 0xff94c3ee, 0x007e0640, 0x0780ff7f, 0xff0124eb, 
+    0x90fe3ae4, 0xf0ef7704, 0x1eaa1dab, 0x26121fa9, 0x7a007b4f, 0x12247900, 0x07a99252, 0x54c423e5, 
+    0xff2445f0, 0xe502f075, 0xc124a438, 0xf0e582f5, 0x83f57734, 0x74fc93e4, 0x90fd9301, 0xfee07704, 
+    0xed007afb, 0x3ceafd2b, 0x2d0074fc, 0x017482f5, 0xef83f53c, 0x94c3eef0, 0x7f0440ff, 0xeb0680ff, 
+    0xe4ff0124, 0x7704903a, 0xf075f0ef, 0xa438e502, 0x82f5c124, 0x7734f0e5, 0x93e483f5, 0x930174fe, 
+    0x770490ff, 0x7afbfde0, 0xff2bef00, 0x74fe3eea, 0x82f52f00, 0xf53e0174, 0xedf0e983, 0x40ff94c3, 
+    0x80ff7f04, 0x0124eb04, 0x770490ff, 0x9022f0ef, 0xfce02404, 0xecfde0a3, 0xed188fff, 0xd3178fff, 
+    0x806417e5, 0x1b509f94, 0x6417e5c3, 0x40619480, 0x18e5d312, 0x9f948064, 0xe5c30950, 0x94806418, 
+    0x74155061, 0x14049080, 0x18e5a3f0, 0x780490f0, 0x17e5a3f0, 0x22017ff0, 0x900a7412, 0xf0ef4f04, 
+    0x6f1217af, 0x96731254, 0xe0490490, 0x18af0870, 0xe09533ef, 0xe5c37780, 0x94806418, 0xaf2a5070, 
+    0x9533ef18, 0x24effee0, 0x3ee4ff1f, 0xe025effe, 0xfe33eeff, 0xff0224ef, 0x04903ee4, 0xefa3f024, 
+    0x02a575f0, 0x80ffa675, 0x18e5d332, 0x8f948064, 0x18af2e40, 0xe09533ef, 0xe124effe, 0xff34eeff, 
+    0xe025effe, 0xfe33eeff, 0xff0224ef, 0x04903ee4, 0xefa3f024, 0x08a575f0, 0x75ffa675, 0x1480329a, 
+    0x33ef18af, 0xeffee095, 0xeeffe025, 0x24049033, 0xf0efa3f0, 0xa3240490, 0x6a12ffe0, 0x7a007b5f, 
+    0x12167900, 0x6e127466, 0x0e7112eb, 0xe4140490, 0xf004a3f0, 0xe5780490, 0xe5a3f018, 0x007ff017, 
+    0xf5fde422, 0x9014f513, 0xfee00004, 0x0278e0a3, 0xce13c3ce, 0x20f9d813, 0x4d0203e0, 0x4e0490d9, 
+    0x64d3ffe0, 0x40809480, 0x90078002, 0xf4e04e04, 0xefc3ff04, 0x88948064, 0xfde40850, 0xf0580490, 
+    0x04907380, 0xd3ffe04e, 0x80948064, 0x07800240, 0xe04e0490, 0xc3ff04f4, 0x948064ef, 0x7d0a5090, 
+    0x58049010, 0x80f00474, 0x4e04904c, 0x64d3ffe0, 0x40809480, 0x90078002, 0xf4e04e04, 0xefc3ff04, 
+    0x98948064, 0x207d0a50, 0x74580490, 0x2580f008, 0xe04e0490, 0x8064d3ff, 0x02408094, 0x04900780, 
+    0x04f4e04e, 0x64efc3ff, 0x50a09480, 0x90307d08, 0x0c745804, 0x12017ff0, 0x0490a52b, 0xa4f5e058, 
+    0x75f0a675, 0x9a75ffa7, 0x4e049041, 0x8064c3e0, 0x06508094, 0xff7f3f7e, 0xc07e0480, 0x138e007f, 
+    0x25ef148f, 0xe5a4f5e0, 0xe5e02514, 0xa5f53313, 0x7501a675, 0xa475029a, 0x7fa67580, 0x75ffa775, 
+    0xf5e4019a, 0x7fa675a4, 0x75ffa775, 0x007f019a, 0xe1157522, 0x751f1675, 0x387fff14, 0x8e807412, 
+    0xd3138f12, 0x1f9413e5, 0x806412e5, 0x08408094, 0x757f1275, 0x2c80ff13, 0x9413e5c3, 0x6412e5e0, 
+    0x507f9480, 0xf5ff7408, 0x8013f512, 0x12397f17, 0x54ee8074, 0x07adfc03, 0xe02513e5, 0xf54ce025, 
+    0x13f5ed12, 0xe0460490, 0x049017f5, 0x90fbe04e, 0xf5e01e04, 0xf5e0a320, 0x22158521, 0x85231685, 
+    0x13ad2414, 0x17af12ac, 0x8fba5112, 0x62049018, 0xef4b60e0, 0xfee09533, 0x54f8c4ef, 0xff68c80f, 
+    0xf054c4ee, 0x32049048, 0xf0efa3f0, 0xe04e0490, 0x1e0490fb, 0xa320f5e0, 0x8521f5e0, 0x16852215, 
+    0x24188523, 0x12ac13ad, 0x401217af, 0x9533efb8, 0x0490fee0, 0xf02fe033, 0xe0320490, 0x0490f03e, 
+    0xf017e54e, 0xe51e0490, 0xe5a3f012, 0x0490f013, 0x0490e062, 0x18aff04d, 0x90d25a02, 0xa3e01404, 
+    0x0203e730, 0xa475f34f, 0xdfa67520, 0x75ffa775, 0x007b119a, 0x1279007a, 0x756c5312, 0x1b8f001a, 
+    0x01641be5, 0x03601a45, 0x12e64f02, 0x04904f67, 0xf0017411, 0xe0490490, 0x04900d70, 0xf0a3f018, 
+    0xf0a3f0a3, 0x90d94f02, 0xffe07804, 0x948064c3, 0xd3244070, 0x948064ef, 0x7f1c508f, 0x80741234, 
+    0xe09533ee, 0x0a78fcfd, 0xc03c2612, 0xc005c004, 0x7f07c006, 0x7f1a8035, 0x80741236, 0xe09533ee, 
+    0x0a78fcfd, 0xc03c2612, 0xc005c004, 0x7f07c006, 0xb3741237, 0x02d003d0, 0x00d001d0, 0x19f54feb, 
+    0xe918f5ea, 0xf5e817f5, 0xae19af16, 0xfc17ad18, 0x26121078, 0x18049029, 0xefa3f0ee, 0xff19e5f0, 
+    0xa3fe18e5, 0xefa3f0ee, 0x441ae5f0, 0x140490ec, 0xa31be5f0, 0xf5e422f0, 0xdfa675a4, 0x75ffa775, 
+    0x2222119a, 0x75e11575, 0x04901f16, 0x90ffe063, 0xc3e06704, 0xd312f59f, 0x78948064, 0x13750550, 
+    0xc3118001, 0x806412e5, 0x05408894, 0x80ff1375, 0x13f5e403, 0x7412467f, 0x3f54efb3, 0x7d007eff, 
+    0x12007c20, 0x13e5b473, 0xc314f52f, 0x806415e5, 0x6414e5f8, 0x03509880, 0xd3141585, 0x806416e5, 
+    0x6414e5f8, 0x03409880, 0x90141685, 0xffe06404, 0xe0680490, 0x12f59fc3, 0x948064d3, 0x75055078, 
+    0x11800113, 0x6412e5c3, 0x40889480, 0xff137505, 0xf5e40380, 0x12457f13, 0x54efb374, 0x007eff3f, 
+    0x007c207d, 0xe5b47312, 0xc3ff2f13, 0x806415e5, 0x8064eff8, 0xaf025098, 0x16e5d315, 0xeff88064, 
+    0x40988064, 0xef16af02, 0xa4f53f54, 0x75c0a675, 0x9a75ffa7, 0xef14af45, 0xa4f53f54, 0x75c0a675, 
+    0x9a75ffa7, 0x417f2246, 0xefb37412, 0x90ff0f54, 0x90f05804, 0xf0e42204, 0x90f0efa3, 0xfee02804, 
+    0xd3ffe0a3, 0x64ee0094, 0x40809480, 0x900f8002, 0xfee02804, 0xc3ffe0a3, 0xe4ff9fe4, 0xefd3fe9e, 
+    0x64ee0494, 0x50809480, 0x4c049008, 0x600164e0, 0x58049058, 0x0490ffe0, 0xa3fce028, 0x0490fde0, 
+    0xfbfee05a, 0xe02a0490, 0xe0a320f5, 0xf5e421f5, 0x0f237522, 0x90b75112, 0xf0ef5804, 0xa3220490, 
+    0x5a0490e0, 0x620490f0, 0x1601b4e0, 0xe05a0490, 0x580490ff, 0x5c0490e0, 0x800207b5, 0xf0027418, 
+    0x90e41680, 0x80f05c04, 0x2204900f, 0x0490e0a3, 0x0490f05a, 0xf001745c, 0xe0280490, 0xa3e0a3ff, 
+    0xefa3f0cf, 0x4c0490f0, 0x0b01b4e0, 0xe05c0490, 0x03600164, 0x90f00274, 0xf5e05804, 0xf0a675a4, 
+    0x75ffa775, 0x7522419a, 0x1c8fff24, 0x1e8d1d8c, 0xf5e41f8b, 0xe527f526, 0x701d451e, 0x251c850a, 
+    0x04620490, 0xc37580f0, 0x80641de5, 0x0c508094, 0x009421e5, 0x806420e5, 0x15508094, 0x941ee5d3, 
+    0x641de500, 0x40809480, 0x6420e535, 0x50809480, 0xae21af2d, 0x1d741220, 0x07c006c0, 0x1dae1eaf, 
+    0xd01d7412, 0xc304d005, 0x9cee9def, 0x1c850550, 0x85038025, 0x0490251f, 0xf0017462, 0xe5c31e80, 
+    0x9480641d, 0x40ff7f80, 0xef017f02, 0xa4f02485, 0x1ce5c3ff, 0xe425f59f, 0xf0620490, 0x6423e5d3, 
+    0x25e5f880, 0x40988064, 0x25238505, 0xe5c31080, 0xf8806422, 0x806425e5, 0x850c5098, 0x26752522, 
+    0x62049001, 0xe5f00174, 0x60236525, 0xb525e505, 0x27750322, 0x60049001, 0xa3f026e5, 0xaff027e5, 
+    0x288f2225, 0x268d278e, 0x298b258c, 0x2b892a8a, 0xfdfeffe4, 0xaa28abfc, 0xa826a927, 0x2612c325, 
+    0xab0b7018, 0xa92aaa29, 0xde25122b, 0xf5e422ff, 0x7eff7f2c, 0xfc7f7dff, 0x27aa28ab, 0x25a826a9, 
+    0x182612d3, 0x28750c40, 0xff2775ff, 0x757f2675, 0x28af0025, 0x26ad27ae, 0x017825ac, 0x8f3c2612, 
+    0x8d278e28, 0x05258c26, 0xfeffe42c, 0x5425e5fd, 0xfbe4fc80, 0xc3f8f9fa, 0x60182612, 0x752ce5d5, 
+    0x251220f0, 0xc3f0af81, 0xab9f1f74, 0xa92aaa29, 0xde25122b, 0x2aaa29ab, 0x25122ba9, 0x94c3fba3, 
+    0xe41d5008, 0xe5fdfeff, 0xf4ebfc25, 0xf91f2404, 0x292612f8, 0x29ab2d8f, 0x12e42ba9, 0x1980de25, 
+    0xfdfeffe4, 0x78fc25e5, 0x29261218, 0x29ab2d8f, 0x2ba92aaa, 0x2512f974, 0x222dafbc, 0x1e8a1d8b, 
+    0x6d121f89, 0x8e238f0c, 0x8c218d22, 0x20049020, 0xe0a3fee0, 0xfdfce4ff, 0x26121078, 0xa904a83c, 
+    0xab06aa05, 0xfee0a307, 0xebffe0a3, 0x4eeafb4f, 0x23e5c3fa, 0x22e5ff9b, 0x21e5fe9a, 0x20e5fd99, 
+    0x1dabfc98, 0x1fa91eaa, 0x906f2612, 0xfee03404, 0xe4ffe0a3, 0x1078fdfc, 0xa83c2612, 0xaa05a904, 
+    0xa307ab06, 0xe0a3fee0, 0xfb4febff, 0xc3fa4eea, 0xf59b23e5, 0x9a22e527, 0x21e526f5, 0xe525f599, 
+    0x24f59820, 0xe0110490, 0x901f05b4, 0xffe06100, 0xfefdfce4, 0x26120778, 0xaa27ab3c, 0xa825a926, 
+    0x2612d324, 0x7f224018, 0x00902201, 0xe4ffe061, 0x78fefdfc, 0x3c261211, 0x26aa27ab, 0x24a825a9, 
+    0x182612d3, 0x017f0340, 0x22007f22, 0x60ed168f, 0x6016e54f, 0x12f17f27, 0x33efc174, 0xf5efe095, 
+    0xc0a675a4, 0x75ffa775, 0x0490449a, 0x54c4e017, 0x70036403, 0x06550203, 0x3f80447f, 0x74120f7f, 
+    0x9533efc1, 0xa4f5efe0, 0x75c0a675, 0x9a75ffa7, 0x17049044, 0x0354c4e0, 0x7a600364, 0x5380447f, 
+    0x386016e5, 0x7412f17f, 0x9533efc1, 0xa4f5efe0, 0x75c0a675, 0x9a75ffa7, 0x12437f43, 0x54efb374, 
+    0x007eff3f, 0x007c207d, 0xefb47312, 0xfee09533, 0x9ff174c3, 0xf0250490, 0x3580ff74, 0x74120f7f, 
+    0x9533efc1, 0xa4f5efe0, 0x75c0a675, 0x9a75ffa7, 0x12437f43, 0x54efb374, 0x007eff3f, 0x007c207d, 
+    0xefb47312, 0xfee09533, 0x9f0f74c3, 0xf0250490, 0x04909ee4, 0x1222f024, 0x90e4c86c, 0xa3f02e04, 
+    0xa3f0a3f0, 0x830490f0, 0x90f0a3f0, 0x90f08604, 0xa3f03e04, 0xa3f0a3f0, 0x90f0a3f0, 0x90f08a04, 
+    0xa3f04404, 0xe4f02074, 0x0490f0a3, 0x0490f06d, 0xf0a3f07b, 0xf07e0490, 0xf04a0490, 0xf04c0490, 
+    0xf05a0490, 0x0490f0a3, 0x0490f082, 0x0490f055, 0xf0a3f028, 0xf05c0490, 0xf0a3f0a3, 0xf02a0490, 
+    0xf0a3f0a3, 0x0490f0a3, 0x0490f05f, 0x0490f06a, 0x0490f069, 0xf0a3f06b, 0xf06f0490, 0xf0a3f0a3, 
+    0x0490f0a3, 0xf0a3f012, 0xf00d0490, 0xf0a3f0a3, 0x0490f0a3, 0xf0a3f073, 0xf0a3f0a3, 0xf06e0490, 
+    0xf07d0490, 0xf0320490, 0x0490f0a3, 0x0490f08b, 0xf0a3f014, 0xf0a3f0a3, 0xf0a3f0a3, 0xf0a3f0a3, 
+    0xaa07ab22, 0x5c009006, 0x7012ffe0, 0xe4198fe1, 0x16f515f5, 0x188b178a, 0xad0b6e12, 0x95d3ed07, 
+    0x902d5019, 0xc3e06b04, 0x24501995, 0x18af17ae, 0x54f8c4ee, 0xc4efc8f0, 0x54480f54, 0x60036403, 
+    0xaf15ae0f, 0xcf54ef16, 0x1044158e, 0x548016f5, 0x1995d3ed, 0x04904840, 0x95ffe06b, 0xed3f5019, 
+    0x33e4fb2f, 0x2519e5fa, 0x33e4ffe0, 0x9febd3fe, 0xf88064ee, 0x988064ea, 0x17ae2440, 0xc4ee18af, 
+    0xc8f054f8, 0x0f54c4ef, 0x64035448, 0xae0f6002, 0xef16af15, 0x158ecf54, 0x16f52044, 0x04900080, 
+    0xf0017469, 0xed6b0490, 0xaf15aef0, 0xf8c4ee16, 0xefc8f054, 0x480f54c4, 0x07600354, 0x15ae16af, 
+    0x90807212, 0xffe06904, 0xc1157522, 0x753f1675, 0x0490ff14, 0x0470e049, 0x0d80387f, 0xe0490490, 
+    0x7f0401b4, 0x7f028036, 0x80741238, 0x138f128e, 0x7412497f, 0x7f54efb3, 0x7d007eff, 0x12007c40, 
+    0x178fb473, 0xe04e0490, 0x1e0490fb, 0xa320f5e0, 0x8521f5e0, 0x16852215, 0x24148523, 0x12ac13ad, 
+    0xa9ba5112, 0x4e049007, 0x90f017e5, 0x12e51e04, 0x13e5a3f0, 0x620490f0, 0x4d0490e0, 0x700164f0, 
+    0x6004901e, 0x007afbe0, 0x407f067d, 0x6c12007e, 0x6104903e, 0x067dfbe0, 0x007e407f, 0xe9516d12, 
+    0xa4f5efff, 0x7580a675, 0x9a75ffa7, 0x64e9d349, 0x40809480, 0x8001af04, 0x04f4e904, 0x64efc3ff, 
+    0x90bf9480, 0x40e03d04, 0xf0024404, 0xf0fd5422, 0x12f5e422, 0xe07f0490, 0x0203e030, 0x04901058, 
+    0xf924e040, 0x60140c60, 0xe4008012, 0xf04e0490, 0x6f12f0a3, 0x40049020, 0x12f00874, 0x70ef7474, 
+    0x22027f03, 0x8f367312, 0x6012e512, 0x4e049073, 0xf01225e0, 0xf004e0a3, 0xe04e0490, 0x8064c3ff, 
+    0x007ea094, 0x017e0250, 0x8064eed3, 0x0d408094, 0x948064ef, 0x50007fa0, 0x80017f02, 0x4e049013, 
+    0x8064c3e0, 0x007fa094, 0x017f0250, 0xff04f4ef, 0x901760ef, 0xc3e04f04, 0xb0948064, 0x4d120c50, 
+    0x40049011, 0x7ff00774, 0xa4752202, 0xfea67501, 0x75ffa775, 0x017d199a, 0x3112177f, 0x22017fb9, 
+    0x4e0490e4, 0xfff0a3f0, 0xe51f8f22, 0x7001642c, 0xae23af69, 0xac21ad22, 0x4e4dec20, 0x850a704f, 
+    0x04902d1f, 0x80f00462, 0x5033ec6c, 0xfeffe412, 0x28abfcfd, 0x26a927aa, 0x261225a8, 0xe4195002, 
+    0xfcfdfeff, 0x22aa23ab, 0x20a821a9, 0x022612d3, 0x25ac1c40, 0x165033ec, 0x33ec20ac, 0x1f850550, 
+    0x8503802d, 0x04902d24, 0xf0017462, 0x20ac2780, 0xff7f33ec, 0x017f0240, 0x20ac0a80, 0xff7f33ec, 
+    0x017f0240, 0xf02b85ef, 0xe5c3ffa4, 0x2df59f1f, 0x620490e4, 0x2ae5d3f0, 0xe5f88064, 0x9880642d, 
+    0x2a850540, 0xc310802d, 0x806429e5, 0x642de5f8, 0x09509880, 0x902d2985, 0x01746204, 0x222daff0, 
+    0xe0520090, 0xffe0a3fe, 0x8002604e, 0x3f741203, 0x07ad06ac, 0xe0560090, 0x78e0a3fe, 0x13c3ce03, 
+    0xf9d813ce, 0x9fedc3ff, 0xfe9eecff, 0xe0570090, 0x0090f02f, 0xf03ee056, 0x630090e4, 0x5c0090f0, 
+    0x94d3ffe0, 0xef2b4000, 0xc324e025, 0x34e482f5, 0x7483f576, 0x50249301, 0x3493e4ff, 0x90d3fe00, 
+    0x9fe05700, 0xe0560090, 0x9007409e, 0x14e05c00, 0x00903380, 0xc3ffe05c, 0x30501494, 0x24e025ef, 
+    0xe482f5c3, 0x83f57634, 0x24930174, 0x93e4ffb0, 0xc3feff34, 0xe0570090, 0x5600909f, 0x0c509ee0, 
+    0xe05c0090, 0x0090f004, 0xf0017463, 0xe407ad22, 0xf04d0490, 0x901770ed, 0x13e00f04, 0x1f541313, 
+    0xf0510490, 0xe00f0490, 0x750490fe, 0x01bd1a80, 0x10049028, 0x131313e0, 0x04f41f54, 0xf0510490, 
+    0xe0100490, 0x760490fe, 0x24007ae0, 0x3eeaff00, 0xf0220490, 0x80f0efa3, 0x0490e405, 0x02bdf051, 
+    0x0d049019, 0x131313e0, 0x04f41f54, 0xf0500490, 0xe00d0490, 0x730490fe, 0x03bd1880, 0x0e049026, 
+    0x131313e0, 0x04901f54, 0x0490f050, 0x90fee00e, 0x7ce07404, 0xff002400, 0x04903eec, 0xefa3f022, 
+    0xe40580f0, 0xf0500490, 0xe0510490, 0x546f12ff, 0xe0500490, 0xd25a02ff, 0xe0400490, 0x0370fd24, 
+    0x14b55a02, 0x60142960, 0x7f00804d, 0xf7731201, 0x7510a475, 0xa775efa6, 0x409a75ff, 0x6c12ff7f, 
+    0x12097fc5, 0x71126371, 0x4004900e, 0x12f00474, 0x70ef7474, 0x22027f03, 0x1512ff7f, 0x4d0490b3, 
+    0xe4e360e0, 0xc56c12ff, 0x7112097f, 0x0e71128d, 0x74400490, 0x7412f005, 0x0370ef74, 0xe422027f, 
+    0xb31512ff, 0xe04d0490, 0xffe4e360, 0x7f546f12, 0x24681201, 0x7fc86c12, 0x39711209, 0x900e7112, 
+    0x03744004, 0x747412f0, 0x7f0370ef, 0x017f2202, 0x90b31512, 0x60e04d04, 0xf44f12e3, 0x7312ffe4, 
+    0x1f8f22f7, 0x74120a7f, 0xe5ffee80, 0x90ff2f1f, 0x2fe06d04, 0xe7a2e025, 0xa575ff13, 0xffa67520, 
+    0x758fa775, 0x30ef049a, 0xf5e412e7, 0xffa675a5, 0x75fba775, 0xf4ef049a, 0x0c80ff04, 0x7504a575, 
+    0xa775ffa6, 0x049a75fb, 0xe0440490, 0xa4752860, 0x80a67501, 0x75ffa775, 0xfee4049a, 0x8064efc3, 
+    0x8064eef8, 0x753b5098, 0xa67502a5, 0xfda775ff, 0x0e049a75, 0xfdefe680, 0xf57f54ed, 0xf50874a4, 
+    0x80a675a5, 0x75f7a775, 0xa575049a, 0xffa67502, 0x75fda775, 0xf5e4049a, 0xffa675a5, 0x75f7a775, 
+    0x0490049a, 0xf01fe546, 0x40049022, 0x60ef24e0, 0x9000804b, 0x60e04904, 0x115c0203, 0xe0000490, 
+    0xf054f8c4, 0xc4e0a3c8, 0x54480f54, 0x60026403, 0xc86c1270, 0x72120c7f, 0x0490e459, 0xf0a3f024, 
+    0x744b0490, 0x0490f006, 0xc3ffe04b, 0x4c501694, 0x12b56a12, 0x04900e71, 0xf0117440, 0xef747412, 
+    0x027f0370, 0x12387f22, 0x4eef8074, 0x387f2660, 0xd3807412, 0xee0094ef, 0x80948064, 0x007e0640, 
+    0x0480017f, 0xff7fff7e, 0xe0250490, 0x0490f02f, 0xf03ee024, 0xe04b0490, 0xaa80f004, 0x80236512, 
+    0x5d049006, 0x90f00174, 0x31744004, 0x22007ff0, 0xe0430490, 0x5360d324, 0x801f6014, 0x57049000, 
+    0x8c0490e0, 0x12147ff0, 0x90e42070, 0xa3f01e04, 0x0e7112f0, 0x74430490, 0x7412f02e, 0x0370ef74, 
+    0xe422027f, 0x646012ff, 0xe04d0490, 0x0490e360, 0x0490e057, 0x147ff053, 0xe4537012, 0xf01e0490, 
+    0x7112f0a3, 0x4304900e, 0x12f02d74, 0x70ef7474, 0x22027f03, 0x6012ffe4, 0x4d049064, 0xe4e360e0, 
+    0xf0430490, 0xe0570490, 0x9533fdff, 0x0490fce0, 0xd3fee053, 0x8064ec9d, 0x988074f8, 0x06af0450, 
+    0x04900080, 0x90f0ef53, 0xffe08c04, 0x7f546f12, 0x3c7f2200, 0xefb37412, 0x7eff1f54, 0xc006c000, 
+    0x123c7f07, 0x54efae74, 0x1313133f, 0xd0fd1f54, 0x15f52de0, 0x0034e0d0, 0x3c7f14f5, 0xefb37412, 
+    0x13c47f54, 0x64035413, 0xc30a7001, 0xe4ff1595, 0x80fe1495, 0xaf14ae04, 0x8f128e15, 0x123c7f13, 
+    0x54efb374, 0x007eff1f, 0x07c006c0, 0x74123c7f, 0x0754efae, 0x2de0d0fd, 0xe0d017f5, 0x16f50034, 
+    0x74123c7f, 0x3f54efb3, 0x075413c4, 0x0a700164, 0xff1795c3, 0xfe1695e4, 0x16ae0480, 0x13e517af, 
+    0x12e5ff2f, 0x13e7a23e, 0x2413effe, 0x34eeffef, 0x7e22feff, 0x7d407f00, 0x7a017b00, 0x12507900, 
+    0x90e48926, 0xa3f05000, 0x500090f0, 0x74a3f0e4, 0xa3e4f026, 0xa3f0a3f0, 0xa3f0d174, 0x90f00f74, 
+    0x12745e00, 0x5c0090f0, 0xe4f00b74, 0xf0630090, 0xf0a3f0a3, 0xf0a3f0a3, 0xf0a3f0a3, 0x04a3f0a3, 
+    0x3f7412f0, 0xc30378ef, 0xce33ce33, 0x90fff9d8, 0xf0ee5600, 0xe4f0efa3, 0x581209f5, 0xe50905d0, 
+    0x0894c309, 0x90e4f440, 0xa3f05f00, 0x5d0090f0, 0x90e4f004, 0xa3f05800, 0xa3f0a3f0, 0x7f027ef0, 
+    0x017bfdf8, 0x0079017a, 0xe4892612, 0x34f533f5, 0x902235f5, 0x24e04204, 0x144160e3, 0x00807460, 
+    0xe0490490, 0x5e020360, 0x00049098, 0xe0a3fee0, 0xc3ce0278, 0xd813ce13, 0x6ce030f9, 0xe0880490, 
+    0x131313ff, 0xe0201f54, 0xc86c1229, 0x047f107d, 0x12946812, 0x04900e71, 0xf01d7442, 0xef747412, 
+    0x027f0370, 0x7f017d22, 0xdb181205, 0xe04d0490, 0x0490e160, 0x13ffe088, 0x1f541313, 0x1229e020, 
+    0x107dc86c, 0x6812057f, 0x0e711294, 0x74420490, 0x7412f01e, 0x0370ef74, 0x7d22027f, 0x12047f01, 
+    0x0490db18, 0xe160e04d, 0x420490e4, 0x8f22fff0, 0x120a7f1c, 0x1ce5b374, 0xa2e0252f, 0x75ff13e7, 
+    0xa67540a5, 0x8fa775ff, 0xef049a75, 0xe412e730, 0xa675a5f5, 0xfba775ff, 0xef049a75, 0x80ff04f4, 
+    0x04a5750c, 0x75ffa675, 0x9a75fba7, 0x44049004, 0x752860e0, 0xa67501a4, 0xffa77580, 0xe4049a75, 
+    0x64efc3fe, 0x64eef880, 0x3c509880, 0x7502a575, 0xa775ffa6, 0x049a75fd, 0xefe6800e, 0x7f54edfd, 
+    0x0874a4f5, 0xa675a5f5, 0xf7a77580, 0x75049a75, 0xa67502a5, 0xfda775ff, 0xe4049a75, 0xa675a5f5, 
+    0xf7a775ff, 0x22049a75, 0xe025ef22, 0xa5f5e025, 0x75ffa675, 0x9a7583a7, 0xa5f5e414, 0x75ffa675, 
+    0x9a757fa7, 0xa5f5e421, 0x75ffa675, 0x9a757fa7, 0xa5f5e423, 0x75ffa675, 0x9a757fa7, 0xa5f5e425, 
+    0x75ffa675, 0x9a757fa7, 0xa5f5e427, 0x75ffa675, 0x9a757fa7, 0x88049029, 0x0ce020e0, 0x7580a575, 
+    0xa775ffa6, 0x219a757f, 0xe0880490, 0xe02013c3, 0x80a5750c, 0x75ffa675, 0x9a757fa7, 0x88049023, 
+    0x541313e0, 0x0ce0203f, 0x7580a575, 0xa775ffa6, 0x259a757f, 0x7540a475, 0xa775bfa6, 0x109a75ff, 
+    0x8e168f22, 0x8c148d15, 0xfeffe413, 0x16abfcfd, 0x14a915aa, 0x12c313a8, 0x02701826, 0x7fe422ff, 
+    0xfcfdfe01, 0x15aa16ab, 0x13a814a9, 0x182612c3, 0xe07f0370, 0x17f5e422, 0x16f516e5, 0x15f515e5, 
+    0x14f514e5, 0x7f5413e5, 0x16af13f5, 0x14ad15ae, 0x017813ac, 0x8f3c2612, 0x8d158e16, 0x05138c14, 
+    0xfeffe417, 0x5413e5fd, 0xfbe4fc80, 0xc3f8f9fa, 0x60182612, 0xfeffe4d5, 0x5413e5fd, 0x1778fc70, 
+    0xe5292612, 0x20f07517, 0xae812512, 0x1f74c3f0, 0x22ff2f9e, 0x0490148f, 0x01b4e049, 0x80347f04, 
+    0x12387f02, 0x007c8074, 0xff1425ef, 0x04903eec, 0xefa3f01c, 0x570490f0, 0x9533fee0, 0x260490e0, 
+    0xf0cea3f0, 0x1c0490ff, 0xe0a3fce0, 0x4e0490fd, 0x0490fbe0, 0x20f5e01e, 0x21f5e0a3, 0x7522f5e4, 
+    0x51121f23, 0x570490b7, 0x0490f0ef, 0x90e0a326, 0x90f04e04, 0x90e06204, 0x90f04d04, 0xffe01c04, 
+    0xcfa3e0a3, 0xf0efa3f0, 0xe0570490, 0x546f12ff, 0xe0600490, 0x04900760, 0xf0017482, 0x0490e422, 
+    0x9022f082, 0xffe04904, 0x01b41960, 0x00049013, 0xe0a3fee0, 0xc3ce0278, 0xd813ce13, 0x03e020f9, 
+    0x9022007f, 0x24e04004, 0x803860f1, 0x87049000, 0x13c4ffe0, 0xe0200754, 0xc86c123e, 0x5a12ffe4, 
+    0x12097fd2, 0xa475ba6f, 0xdfa67520, 0x75ffa775, 0x7412309a, 0x5704900a, 0x7112f0ef, 0x4004900e, 
+    0x12f00f74, 0x70ef7474, 0x22027f03, 0x60123c7f, 0x4d049064, 0x90e360e0, 0x32744004, 0x22007ff0, 
+    0xe0400490, 0x3960f424, 0x6c120080, 0x460490c8, 0x4f0490e0, 0x0a7412f0, 0xef500490, 0x12ffe4f0, 
+    0xffe4d25a, 0x75546f12, 0xa67501a4, 0xffa775fe, 0x7f039a75, 0x876f1209, 0x900e7112, 0x0c744004, 
+    0x747412f0, 0x7f0370ef, 0x4e122202, 0x4d049021, 0x900970e0, 0xc3e04b04, 0xdc402094, 0x75a4f5e4, 
+    0xa775fea6, 0x039a75ff, 0xe04f0490, 0xd25a12ff, 0xe0500490, 0x546f12ff, 0xe422007f, 0x16f515f5, 
+    0x188f178e, 0xe05c0090, 0xb47012ff, 0xe0560490, 0x45509fc3, 0xe06c0490, 0x948064ff, 0x80024080, 
+    0x6c049007, 0xff04f4e0, 0x8064efc3, 0x29508194, 0x18af17ae, 0xce0278ef, 0x13ce13c3, 0x0354f9d8, 
+    0x15600264, 0x16af15ae, 0x8ef354ef, 0xf5084415, 0x6c049016, 0x80f014e0, 0x6a049006, 0x90f00174, 
+    0x64e06a04, 0xaf076001, 0x1215ae16, 0x04908072, 0x22ffe06a, 0x807f007e, 0x017b007d, 0x0079047a, 
+    0x7e892612, 0x7d207f00, 0x7a017b00, 0x12807904, 0x90e48926, 0xa3f00004, 0x3c0490f0, 0xe4f00274, 
+    0x0490f0a3, 0x0490f00b, 0x0490f00a, 0xf0a3f00c, 0x0490f0a3, 0x0490f010, 0x0490f00f, 0xf0a3f012, 
+    0xf0110490, 0xf0480490, 0xf0040490, 0xf0030490, 0xf0060490, 0xf0a3f0a3, 0x0490f0a3, 0xf0027405, 
+    0x14020490, 0x0490e4f0, 0x5502f07f, 0x06e09007, 0x8fe4ffe0, 0xf518f519, 0xa316f517, 0xfce4ffe0, 
+    0x0878fefd, 0xe53c2612, 0x19f54f19, 0xf54e18e5, 0x4d17e518, 0x16e517f5, 0xa316f54c, 0xfce4ffe0, 
+    0x1078fefd, 0xe53c2612, 0x19f54f19, 0xf54e18e5, 0x4d17e518, 0x16e517f5, 0xa316f54c, 0xfce4ffe0, 
+    0x1878fefd, 0xe53c2612, 0x19f54f19, 0xf54e18e5, 0x4d17e518, 0x16e517f5, 0xaf16f54c, 0xad18ae19, 
+    0x9022fc17, 0xb4e04904, 0x347f0401, 0x387f0280, 0x90807412, 0xf0ee1c04, 0x90f0efa3, 0xffe05604, 
+    0xe4220490, 0xf0efa3f0, 0xe01c0490, 0xfde0a3fc, 0xe04e0490, 0x1e0490fb, 0xa320f5e0, 0xa321f5e0, 
+    0x22f5e0a3, 0x752d2375, 0x51120124, 0x560490ba, 0x0490f0ef, 0x90e0a322, 0x90f04e04, 0x90e06204, 
+    0x90f04d04, 0xffe01c04, 0xcfa3e0a3, 0xf0efa3f0, 0xe0560490, 0xbb7402ff, 0x4d0490e4, 0x530490f0, 
+    0x620490f0, 0x1c0490f0, 0xa3f0a3f0, 0xeff0a3f0, 0x12750970, 0x7504900f, 0xbf1080f0, 0x12750a01, 
+    0x0490e4f0, 0x0380f076, 0xbf12f5e4, 0x13750502, 0xbf0e80f0, 0x13750503, 0x9006800f, 0xf5e04604, 
+    0x0264ef13, 0x03bf0360, 0x4f049008, 0x80f013e5, 0x4f049006, 0xe4f012e5, 0xf0510490, 0xe04f0490, 
+    0x12aff0a3, 0xaf546f12, 0xd25a0213, 0xfbfcfde4, 0xe0500090, 0xe0a313c3, 0xc31f5413, 0x94e40594, 
+    0x7d055000, 0x0b047c04, 0xf50154eb, 0xfea675a4, 0x75ffa775, 0x54ecb09a, 0x2513c302, 0xff0254e0, 
+    0x130454ec, 0x253f5413, 0x54e025e0, 0xecff4f04, 0xff4f0154, 0x130454ed, 0xc43f5413, 0x4f205433, 
+    0x0254edff, 0x54c413c3, 0xedff4f10, 0x33330154, 0x4f085433, 0xa675a4f5, 0xffa775c0, 0x22b39a75, 
+    0x1215f5e4, 0x33ef0a74, 0x13f5e095, 0x64c3148f, 0x50809480, 0x95e4c30e, 0xe414f514, 0x13f51395, 
+    0x7f011575, 0xb3741240, 0x130f54ef, 0x1f541313, 0x14e51260, 0xe5ffe025, 0x74fe3313, 0x82f52f2d, 
+    0x10807774, 0xe02514e5, 0x3313e5ff, 0x2fed74fe, 0x767482f5, 0xe483f53e, 0x7416f593, 0x17f59301, 
+    0x0a6015e5, 0x1795e4c3, 0x1695e4ff, 0x16ae22fe, 0x7f2217af, 0xb3741242, 0xff0754ef, 0xf0590490, 
+    0xe4220490, 0xf0efa3f0, 0xe0590490, 0x240490ff, 0xe0a3fce0, 0x5b0490fd, 0x90fbfee0, 0xf5e02c04, 
+    0xf5e0a320, 0x22f5e421, 0x75072375, 0x5112ff24, 0x590490ba, 0x0490f0ef, 0x90e0a322, 0x90f05b04, 
+    0x90e06204, 0x90f05d04, 0xffe02404, 0x0490e0a3, 0xa3f0cf2c, 0x0490f0ef, 0xa4f5e059, 0x75f8a675, 
+    0x9a75ffa7, 0x04902242, 0xe924e040, 0x60143b60, 0x90008052, 0x70e04904, 0x00049053, 0xe0a3fee0, 
+    0xc3ce0278, 0xd813ce13, 0x40e030f9, 0xe05f0490, 0x097f2070, 0x90ce6d12, 0x01745f04, 0x400490f0, 
+    0x90f01774, 0xff748304, 0x747412f0, 0x7f0370ef, 0x097f2202, 0x90395f12, 0x18744004, 0x830490f0, 
+    0x12f0ff74, 0x70ef7474, 0x22027f03, 0x74400490, 0x007ff019, 0x49049022, 0x800270e0, 0x2404904c, 
+    0x0470f4e0, 0xef64e0a3, 0xc17f1270, 0x7f5f6a12, 0x5f6a1201, 0x7504a575, 0x1c80ffa6, 0xe0240490, 
+    0xe0a30470, 0x15700f64, 0x6a12c17f, 0x12017f5f, 0xa5755f6a, 0xffa67508, 0x80329a75, 0x02a57518, 
+    0x75ffa675, 0x9a75fda7, 0x02a57504, 0x75ffa675, 0x9a75fda7, 0x25049004, 0x70f004e0, 0x24049006, 
+    0x22f004e0, 0x1e8a1d8b, 0xda7f1f89, 0xee807412, 0xe4fe7f54, 0x228e238f, 0x20f521f5, 0x20ac21ad, 
+    0x26120f78, 0xaa1dab29, 0xef1fa91e, 0x7fde2512, 0x807412db, 0xc0fdfce4, 0xc005c004, 0xaf07c006, 
+    0xad22ae23, 0x7820ac21, 0x3c261210, 0x02d003d0, 0x00d001d0, 0x23f54bef, 0x22f54aee, 0x21f549ed, 
+    0x20f548ec, 0xe5ff23e5, 0x21e5fe22, 0x5420e5fd, 0xef22fc7f, 0x1c60fe24, 0x142a6014, 0x60143a60, 
+    0x7004244b, 0x88049057, 0x20007fe0, 0x017f02e0, 0x488007ae, 0xe0880490, 0x007f13c3, 0x7f02e020, 
+    0x8007ae01, 0x88049037, 0x541313e0, 0x20007f3f, 0x017f02e0, 0x248007ae, 0xe0880490, 0x54131313, 
+    0x20007f1f, 0x017f02e0, 0x108007ae, 0xe0880490, 0x7f0f54c4, 0x02e02000, 0x07ae017f, 0x902206af, 
+    0x30e01704, 0xe1203fe2, 0x79049032, 0x7412ffe0, 0x9533efc1, 0x3f54efe0, 0xa675a4f5, 0xffa775c0, 
+    0x90439a75, 0xffe07804, 0xefc17412, 0xa4f53f54, 0x75c0a675, 0x9a75ffa7, 0x901a8044, 0xffe04504, 
+    0x809f5e12, 0x4f049010, 0x6f12ffe0, 0x46049054, 0x5a12ffe0, 0x170490d2, 0x0de330e0, 0x7508a475, 
+    0xa775f7a6, 0x409a75ff, 0xffe42222, 0x160490fe, 0x0490fde0, 0xc3fce077, 0xec05409d, 0x0b80fd9d, 
+    0xe0160490, 0xff74c3fd, 0x90fd2c9d, 0x70e02404, 0x64e0a304, 0x43037063, 0x04908006, 0xc3fce077, 
+    0x0440ff94, 0x0380007c, 0x90fc04ec, 0xb5e01604, 0x06430304, 0x16049040, 0x0490fbe0, 0x03b5e077, 
+    0x20064303, 0x4febfbed, 0x140490ff, 0xefa3f0ee, 0x2204aff0, 0xfce407ad, 0x8064edd3, 0x1b408094, 
+    0x75a4f5ec, 0xa775c0a6, 0x459a75ff, 0xf53f54ec, 0xc0a675a4, 0x75ffa775, 0xc322469a, 0x948064ed, 
+    0xec1d5080, 0xa4f53f54, 0x75c0a675, 0x9a75ffa7, 0x3f54ec47, 0xa675a4f5, 0xffa775c0, 0x22489a75, 
+    0xf53f54ec, 0xc0a675a4, 0x75ffa775, 0x54ec439a, 0x75a4f53f, 0xa775c0a6, 0x449a75ff, 0x50049022, 
+    0x067dffe0, 0x60fe24ef, 0x12601411, 0x14136014, 0x04241460, 0x087c1470, 0x107c1280, 0x207c0e80, 
+    0x407c0a80, 0x807c0680, 0xfce40280, 0xed327212, 0xa4f51f54, 0x75e0a675, 0x9a75ffa7, 0x20a47515, 
+    0x75a5f5e4, 0xa775d3a6, 0x309a758b, 0x7520a475, 0x9a7520a5, 0xa5f5ec31, 0x75ffa675, 0x7422329a, 
+    0xf518f5ff, 0x120e7f19, 0x1a8e8074, 0xf5e41b8f, 0xf51df51c, 0xc317f516, 0x1b9517e5, 0x1a9516e5, 
+    0x18e53950, 0x251de5ff, 0xe582f517, 0xf516351c, 0x6f93e483, 0xfe19e5fd, 0xed02f075, 0xf5c324a4, 
+    0x34f0e582, 0xe483f574, 0x18f56e93, 0xf5930174, 0xe5170519, 0x05c07017, 0xaebc8016, 0x2219af18, 
+    0x2aac29ae, 0x2caa2bab, 0xae0470ed, 0xbf29ac2a, 0xc3ee1801, 0x03500794, 0xec29800e, 0x400094d3, 
+    0xc3eb1c01, 0x0b1d509a, 0xffbf1a80, 0x94d3ee17, 0x1e034000, 0xc3ec0e80, 0x01500794, 0x94d3eb0c, 
+    0x1b014000, 0x70ed318b, 0x8c308e06, 0x8e04802f, 0x85308c2f, 0x28852d27, 0x7a007b2e, 0x222d7900, 
+    0x900a7412, 0xf0ef4f04, 0x6f121f7f, 0x24049054, 0xa3f0ff74, 0x90f0e174, 0x70e04904, 0x12e07f09, 
+    0x017f5f6a, 0x027f0280, 0xe45f6a12, 0xf0260490, 0x0490f0a3, 0x0490f077, 0x1f7ff016, 0x907f6e12, 
+    0xd3e04904, 0x09400094, 0x7502a575, 0x9a75ffa6, 0x0490e432, 0xf0a3f014, 0x7507ad22, 0xedd301a4, 
+    0x80948064, 0x017f0440, 0x007f0280, 0x25e025ef, 0x440454e0, 0xf5eefe40, 0x80a675a5, 0x758ba775, 
+    0xffe4049a, 0x8064edd3, 0x04408094, 0x048005ae, 0xfe04f4ed, 0x8064eec3, 0x8064eff8, 0x750f5098, 
+    0xa67502a5, 0xfda775ff, 0x0f049a75, 0xad22d680, 0x01a47507, 0x8064edd3, 0x04408094, 0x0280017f, 
+    0x25ef007f, 0x54e025e0, 0xfe204404, 0x75a5f5ee, 0xa77580a6, 0x049a758b, 0xedd3ffe4, 0x80948064, 
+    0x05ae0440, 0xf4ed0480, 0xeec3fe04, 0xeff88064, 0x50988064, 0x02a5750f, 0x75ffa675, 0x9a75fda7, 
+    0xd6800f04, 0xed07ad22, 0x500d94d3, 0xfa24ed21, 0x7e0174ff, 0x0807a800, 0x33c30580, 0xd8ce33ce, 
+    0x75a5f5f9, 0x9a75ffa6, 0x04a47532, 0x24ed1f80, 0x0174fff2, 0x07a8007e, 0xc3058008, 0xce33ce33, 
+    0xa5f5f9d8, 0x75ffa675, 0xa475329a, 0xf3a67508, 0x75ffa775, 0x9022309a, 0x24e04004, 0x803260f6, 
+    0x87049000, 0x13c3ffe0, 0xe438e020, 0xa675a4f5, 0xffa77580, 0x90499a75, 0xd3e04904, 0x23500194, 
+    0x7fc86c12, 0x63711210, 0x900e7112, 0x0a744004, 0x747412f0, 0x7f0370ef, 0x56122202, 0x4d049099, 
+    0x7fe560e0, 0xf5e42200, 0x1237f536, 0xf47f6874, 0xefae7412, 0x131313c4, 0xf2600154, 0x7412fa7f, 
+    0x54c4efae, 0x1208f50f, 0xf5e4635d, 0xc338e538, 0x0a500895, 0x12b13885, 0x38056462, 0xf5e4ef80, 
+    0xb1388538, 0x05060012, 0xb538e538, 0xf5e4f308, 0x8fee8038, 0x8d148e15, 0x90128c13, 0x047400e0, 
+    0x02e090f0, 0x0878f0ef, 0xa3292612, 0x15aff0ef, 0x13ad14ae, 0x107812ac, 0xa3292612, 0x15aff0ef, 
+    0x13ad14ae, 0x187812ac, 0xa3292612, 0xe090f0ef, 0xf0057400, 0xe000e090, 0x22f9e020, 0xe0400490, 
+    0x2660f224, 0x04900080, 0xc3ffe087, 0x2ce02013, 0xe0490490, 0x500194d3, 0xc86c1223, 0x7112107f, 
+    0x0e711263, 0x74400490, 0x7412f00e, 0x0370ef74, 0x1222027f, 0x04909956, 0xe560e04d, 0x74400490, 
+    0x007ff02f, 0x60049022, 0x007afbe0, 0x828f007e, 0x05af838e, 0xa802aeeb, 0x05800807, 0x33ce33c3, 
+    0xfff9d8ce, 0xfe8355ee, 0xff8255ef, 0xfdf482e5, 0xfcf483e5, 0xe02e0490, 0xe0a3fc5c, 0x4eecfd5d, 
+    0xff4fedfe, 0xee2e0490, 0xf0efa3f0, 0x7f049022, 0x13c3ffe0, 0x7f03e030, 0x04902200, 0xf324e040, 
+    0x00800b60, 0x90206f12, 0x0d744004, 0x747412f0, 0x7f0370ef, 0x73122202, 0x1660ef36, 0x7501a475, 
+    0xa775fea6, 0x199a75ff, 0x177f017d, 0x7fb93112, 0x007f2201, 0x24681222, 0x1c0490e4, 0xa3f0a3f0, 
+    0x90f0a3f0, 0x90f04b04, 0xa3f04d04, 0xa3f0a3f0, 0x90f0a3f0, 0xa3f05304, 0x7b0490f0, 0x600164e0, 
+    0x0490e40d, 0xf0a3f020, 0xf0240490, 0x90e4f0a3, 0xa3f02204, 0x260490f0, 0x22f0a3f0, 0xe4cb7212, 
+    0x2a8e2b8f, 0x28f529f5, 0xe0600090, 0x5411e030, 0x0090f0fe, 0xf004e067, 0x00900670, 0xf004e066, 
+    0xe0660090, 0xffe0a3fe, 0x78fdfce4, 0x3c261210, 0xff2b45ef, 0xfe2a45ee, 0xfd2945ed, 0xfc2845ec, 
+    0x8e828f22, 0xeb05af83, 0x07a802ae, 0xc3058008, 0xce33ce33, 0xeefff9d8, 0xeffe8355, 0xe5ff8255, 
+    0xe5fdf482, 0x90fcf483, 0x5ce03004, 0x5de0a3fc, 0xfe4eecfd, 0x90ff4fed, 0xf0ee3004, 0x22f0efa3, 
+    0x7412887f, 0x0f64ef80, 0x751a704e, 0xa67502a4, 0xffa775fd, 0x759ef5e4, 0x0490969c, 0xa3f0e000, 
+    0xf00444e0, 0xa4f5e422, 0x75fda675, 0x9ef5ffa7, 0x90969c75, 0xf0e00004, 0xfb54e0a3, 0x25ef22f0, 
+    0xf5e025e0, 0xffa675a5, 0x7583a775, 0xf5e4149a, 0xffa675a5, 0x757fa775, 0x0490219a, 0xe020e088, 
+    0x80a57519, 0x75ffa675, 0x9a757fa7, 0x40a47521, 0x75bfa675, 0x9a75ffa7, 0x7f222210, 0xae74123b, 
+    0xff0754ef, 0x06c0007e, 0x3b7f07c0, 0xefae7412, 0x13133f54, 0xfd1f5413, 0xff2de0d0, 0x0034e0d0, 
+    0x13ef13c3, 0x7f07c0ff, 0xb374123b, 0xfe3f54ef, 0xff2ee0d0, 0x0f049022, 0x131313e0, 0x94d31f54, 
+    0xa3294001, 0x131313e0, 0x94d31f54, 0x901d4001, 0x13e00d04, 0x1f541313, 0x400194d3, 0x13e0a30f, 
+    0x1f541313, 0x400194d3, 0x22007f03, 0x1222017f, 0x54ef3272, 0x75a4f51f, 0xa775e0a6, 0x159a75ff, 
+    0x75a4f5e4, 0xa67530a5, 0x8fa775f3, 0x75309a75, 0xa67504a5, 0x329a75ff, 0x7503a475, 0xa775fca6, 
+    0x339a75ff, 0x56049022, 0x7412ffe0, 0x570490bb, 0x6f12ffe0, 0x0490e454, 0xe0a3f044, 0x9f5e12ff, 
+    0xe0460490, 0xd25a12ff, 0x7520a475, 0xa775dfa6, 0x109a75ff, 0x74440490, 0x1222f001, 0x1c8f0c6d, 
+    0x1a8d1b8e, 0x1baa198c, 0x04901cab, 0xa3f0ea36, 0x1078f0eb, 0x90292612, 0xf0ee3404, 0x90f0efa3, 
+    0xf0ea2204, 0x90f0eba3, 0xf0ee2004, 0x22f0efa3, 0x7502a575, 0xa775ffa6, 0x019a75f8, 0x7412067f, 
+    0x0154efae, 0x721213f5, 0x10a47532, 0x75e0a675, 0x9a75ffa7, 0x80a57515, 0x75ffa675, 0x9a757fa7, 
+    0x0e710230, 0xffed07ad, 0xfee09533, 0xc30378ef, 0xce33ce33, 0xa4f5f9d8, 0x440154ee, 0x75a5f51a, 
+    0x9a75c0a7, 0x80a5752b, 0x75ffa675, 0x9a757fa7, 0x5704902b, 0x1222f0ed, 0x54ef3272, 0x75a4f51f, 
+    0xa775e0a6, 0x159a75ff, 0x7520a475, 0xa675a0a5, 0x0fa775d3, 0x75309a75, 0xa57520a4, 0x319a7520, 
+    0x7504a575, 0x9a75ffa6, 0x72122232, 0x1f54ef32, 0xa675a4f5, 0xffa775e0, 0x75159a75, 0xa5750ca4, 
+    0xf3a67530, 0x758fa775, 0xa475309a, 0x20a57520, 0x75319a75, 0xa67504a5, 0x329a75ff, 0x32721222, 
+    0xf51f54ef, 0xe0a675a4, 0x75ffa775, 0xf5e4159a, 0x24a575a4, 0x75f3a675, 0x9a758ba7, 0x60a47530, 
+    0x7520a575, 0xa575319a, 0xffa67538, 0x22329a75, 0xef327212, 0xa4f51f54, 0x75e0a675, 0x9a75ffa7, 
+    0x0ca47515, 0x7530a575, 0xa775f3a6, 0x309a758f, 0x7560a475, 0x9a7560a5, 0x04a57531, 0x75ffa675, 
+    0x1222329a, 0x54ef3272, 0x75a4f51f, 0xa775e0a6, 0x159a75ff, 0x750ca475, 0xa67530a5, 0x8fa775f3, 
+    0x75309a75, 0xa57560a4, 0x319a7520, 0x7504a575, 0x9a75ffa6, 0x67122232, 0x3272124f, 0x75a4f5e4, 
+    0xa775cfa6, 0x119a75ff, 0x75a5f5e4, 0xa775ffa6, 0xd19a75fb, 0x170490e4, 0x160490f0, 0x140490f0, 
+    0x22f0a3f0, 0x049007ad, 0x54c4e07f, 0x13e0200f, 0xe0500090, 0xe0a313c3, 0xd31f5413, 0x94e41694, 
+    0xed074000, 0x93827790, 0x90ed22ff, 0xff936d77, 0x9007ad22, 0xc4e07f04, 0xe0200f54, 0x50009013, 
+    0xa313c3e0, 0x1f5413e0, 0xe41694d3, 0x07400094, 0xac7790ed, 0xed22ff93, 0x93977790, 0xf5e422ff, 
+    0xffa675a5, 0x757fa775, 0xa575309a, 0xffa67580, 0x757fa775, 0xa475309a, 0x7fa67580, 0x75ffa775, 
+    0x0490109a, 0xf0ff7483, 0x32721222, 0xf51f54ef, 0xe0a675a4, 0x75ffa775, 0xa475159a, 0xb0a5750c, 
+    0x75f3a675, 0x9a750fa7, 0x04a57530, 0x75ffa675, 0x1222329a, 0x54ef3272, 0x75a4f51f, 0xa775e0a6, 
+    0x159a75ff, 0x750ca475, 0xa675a0a5, 0x0fa775f3, 0x75309a75, 0xa67504a5, 0x329a75ff, 0x32721222, 
+    0xf51f54ef, 0xe0a675a4, 0x75ffa775, 0xf5e4159a, 0x90a575a4, 0x75f3a675, 0x9a750fa7, 0x04a57530, 
+    0x75ffa675, 0x1222329a, 0x54ef3272, 0x75a4f51f, 0xa775e0a6, 0x159a75ff, 0x7580a575, 0xa775ffa6, 
+    0x309a757f, 0x7580a475, 0xa7757fa6, 0x109a75ff, 0xc02f1222, 0xe4075512, 0x12017ffd, 0xfde4a52b, 
+    0x2b12027f, 0x7ffde4a5, 0xa52b1203, 0x047ffde4, 0xe4a52b12, 0x02057ffd, 0xa475a52b, 0xe0a67506, 
+    0x75ffa775, 0xa475d09a, 0xefa67510, 0x75ffa775, 0xa475409a, 0x03a67550, 0x75ffa775, 0x9c75d19e, 
+    0xf5e42218, 0x75a5f5a4, 0xa77503a6, 0x309a7501, 0xf5a4f5e4, 0x319a75a5, 0xf5a4f5e4, 0x329a75a5, 
+    0xf5a4f5e4, 0x339a75a5, 0x32721222, 0xf51f54ef, 0xe0a675a4, 0x75ffa775, 0xa575159a, 0xffa67524, 
+    0x758ba775, 0xa475309a, 0x20a57560, 0x22319a75, 0x06ac07ad, 0xf5a4f5e4, 0x609a75a5, 0xeca4f5ed, 
+    0xa5f58044, 0xaf609a75, 0x027ded05, 0x7dba3d12, 0x020a7f02, 0x0490b931, 0x01b4e04c, 0x0804900d, 
+    0x870490e0, 0x090490f0, 0x04900b80, 0x0490e006, 0x0490f087, 0x0490e007, 0x8522f088, 0xcbaf2cbf, 
+    0xcaadfeef, 0xc306aced, 0x95ec3795, 0x90075036, 0x44e06000, 0x368cf001, 0x04ae378d, 0x7f2205af, 
+    0xae7412a9, 0xff0f54ef, 0x400394c3, 0x94d3ef06, 0x9008400d, 0x44e06000, 0x9022f010, 0x54e06000, 
+    0xad22f0ef, 0xf075ed07, 0xf0aea408, 0x54eea4f5, 0x75a5f501, 0x9a75c0a7, 0x80a5752b, 0x75ffa675, 
+    0x9a757fa7, 0x067f222b, 0xefae7412, 0x13f50154, 0x7412057f, 0x6013e580, 0x64eec30b, 0x50809480, 
+    0xff137503, 0x122213af, 0x208f0c6d, 0x1e8d1f8e, 0x04901d8c, 0xa3f0ee22, 0x1078f0ef, 0x90292612, 
+    0xf0ee2004, 0x22f0efa3, 0xad923312, 0xed06ac07, 0xecfbe025, 0x78edfa33, 0xce33c302, 0xf9d8ce33, 
+    0x3aeeff2b, 0x1f7f22fe, 0x757f6e12, 0xa67510a4, 0xffa775cf, 0x75119a75, 0xa67504a5, 0xfba775ff, 
+    0x22d19a75, 0x06aa07ab, 0xebfe5cea, 0xffe0255d, 0xc3fe33ee, 0xeaff9feb, 0x9022fe9e, 0x047400e0, 
+    0x90f004f0, 0x20e000e0, 0xe090f9e0, 0xf0067400, 0x0a741222, 0xef4f0490, 0x0490e4f0, 0x0490f077, 
+    0x1c7ff016, 0xef397102, 0x333333c4, 0xa4f58054, 0x757fa675, 0x9a75ffa7, 0x3a7f2290, 0xee807412, 
+    0x7dfe3f54, 0x12207c00, 0xffeeb473, 0x64eec322, 0x50809480, 0xfff4ef08, 0x80fef4ee, 0x07ad2200, 
+    0xedc0a475, 0xa5f5eefe, 0x753fa675, 0xaf220d9a, 0xe507adbc, 0xfc0354bd, 0x05af04ae, 0x7507ad22, 
+    0xfeed80a4, 0x75a5f5ee, 0x8f220d9a, 0xad9d8d9e, 0xefaaafa9, 0x22ffedfe, 0xc9d2c8d2, 0xf5e4cbd2, 
+    0x22cad2bf, 0xe0830490, 0x07b4007f, 0x22017f02, 0xa9ad9b8f, 0xfeefaaaf, 0x7f22ffed, 0xb374123a, 
+    0xff3f54ef, 0x80a47522, 0x75a5f5e4, 0x90220d9a, 0x54e001e0, 0x8f22ff01, 0xaf9d8d9e, 0x9b8f22a9, 
+    0x8f22aaaf, 0x22a9af9b, 0x0222007f, 0x22221373, 0x00222222, 0x20211000, 0x40633042, 0x60a55084, 
+    0x81e770c6, 0xa1299108, 0xc16bb14a, 0xe1add18c, 0x12eff1ce, 0x32100231, 0x52522273, 0x729442b5, 
+    0x93d662f7, 0xb3188339, 0xd35aa37b, 0xf39cc3bd, 0x24dee3ff, 0x04433462, 0x64011420, 0x44c774e6, 
+    0xa58554a4, 0x854bb56a, 0xe5099528, 0xc5cff5ee, 0x368dd5ac, 0x16722653, 0x76300611, 0x56f666d7, 
+    0xb7b44695, 0x977aa75b, 0xf7388719, 0xd7fee7df, 0x48bcc79d, 0x68e558c4, 0x08a77886, 0x28611840, 
+    0xc9233802, 0xe9edd9cc, 0x89aff98e, 0xa9699948, 0x5a2bb90a, 0x7ad44af5, 0x1a966ab7, 0x3a500a71, 
+    0xdb122a33, 0xfbdccbfd, 0x9b9eebbf, 0xbb588b79, 0x6c1aab3b, 0x4c877ca6, 0x2cc55ce4, 0x0c033c22, 
+    0xed411c60, 0xcd8ffdae, 0xadcdddec, 0x8d0bbd2a, 0x7e499d68, 0x5eb66e97, 0x3ef44ed5, 0x1e322e13, 
+    0xff700e51, 0xdfbeef9f, 0xbffccfdd, 0x9f3aaf1b, 0x91788f59, 0xb1a98188, 0xd1eba1ca, 0xf12dc10c, 
+    0x106fe14e, 0x30a10080, 0x50e320c2, 0x70254004, 0x83676046, 0xa39893b9, 0xc3dab3fb, 0xe31cd33d, 
+    0x025ef37f, 0x229012b1, 0x42d232f3, 0x62145235, 0xb5567277, 0x95cba5ea, 0xf58985a8, 0xd54fe56e, 
+    0x340dc52c, 0x14c324e2, 0x748104a0, 0x54476466, 0xa7054424, 0x87fab7db, 0xe7b89799, 0xc77ef75f, 
+    0x263cd71d, 0x06f236d3, 0x66b01691, 0x46767657, 0xd9345615, 0xf96dc94c, 0x992fe90e, 0xb9e989c8, 
+    0x58aba98a, 0x78654844, 0x18276806, 0x38e108c0, 0xcba32882, 0xeb5cdb7d, 0x8b1efb3f, 0xabd89bf9, 
+    0x4a9abbbb, 0x6a545a75, 0x0a167a37, 0x2ad01af1, 0xfd923ab3, 0xdd0fed2e, 0xbd4dcd6c, 0x9d8badaa, 
+    0x7cc98de8, 0x5c076c26, 0x3c454c64, 0x1c832ca2, 0xefc10ce0, 0xcf3eff1f, 0xaf7cdf5d, 0x8fbabf9b, 
+    0x6ef89fd9, 0x4e367e17, 0x2e745e55, 0x0eb23e93, 0x1cf01ed1, 0x1b181ca0, 0x1a181b98, 0x19101a90, 
+    0x18081988, 0x17001880, 0x16f81680, 0x15f01578, 0x14e81470, 0x13e81368, 0x12e01260, 0x00000058, 
+    0x00130009, 0x0026001c, 0x0038002f, 0x004b0042, 0x005e0054, 0x00710067, 0x0083007a, 0x0096008d, 
+    0x00a9009f, 0x00bc00b2, 0x00ce00c5, 0x01f400e1, 0x01190107, 0x013f012c, 0x01640152, 0x00000077, 
+    0x001f0010, 0x003f002f, 0x005e004e, 0x007d006d, 0x009c008d, 0x00bc00ac, 0x00db00cb, 0x01fa00ea, 
+    0x0119010a, 0x01390129, 0x01580148, 0x01960177, 0x01d501b6, 0x021302f4, 0x02520233, 0x1b1a1a71, 
+    0x1e1d1c1b, 0x2221201f, 0x26252423, 0x29292827, 0x16152a2a, 0x18171716, 0x1a191918, 0x1c1c1b1a, 
+    0x1e1e1d1d, 0x22201f1f, 0x26252423, 0x28272726, 0x2a292928, 0x2c2b2b2a, 0x2f2e2d2c, 0x23232221, 
+    0x26262524, 0x29282827, 0x2c2b2a2a, 0x2f2e2d2d, 0x0000002f, 0x00000000, 0xfa6d7b48, 0x00000000
+};
diff --git a/drivers/net/bcmbca/phy/os_dep.h b/drivers/net/bcmbca/phy/os_dep.h
new file mode 100644
index 0000000000..d416b7d825
--- /dev/null
+++ b/drivers/net/bcmbca/phy/os_dep.h
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#ifndef __OS_DEP_H__
+#define __OS_DEP_H__
+
+/* uint32_t types */
+#ifdef __UBOOT__
+#include "linux/types.h"
+#else
+#include "linux/types.h"
+#endif
+
+/* udelay */
+#ifdef __UBOOT__
+extern uint32_t jiffies;
+#else
+#include <asm/delay.h>
+#endif
+
+/* NULL */
+#if !defined(NULL)
+#define NULL 0
+#endif
+
+/* memset */
+#ifdef __UBOOT__
+#include <string.h>
+#else
+#include "linux/string.h"
+#endif
+
+/* printk */
+#ifdef __UBOOT__
+#include <stdio.h>
+#include "linux/printk.h"
+#else
+#include "linux/printk.h"
+#endif
+
+/* spinlock */
+#ifdef __UBOOT__
+#define spin_lock_bh(x) *x = 1
+#define spin_unlock_bh(x) *x = 0
+#define DEFINE_SPINLOCK(x) int x
+#else
+#include <linux/spinlock.h>
+#endif
+
+/* EXPORT_SYMBOL */
+#ifdef __UBOOT__
+#include "linux/compat.h"
+#else
+#include "linux/export.h"
+#endif
+
+#endif
diff --git a/drivers/net/bcmbca/phy/phy_drv.c b/drivers/net/bcmbca/phy/phy_drv.c
new file mode 100644
index 0000000000..12e7b524fc
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv.c
@@ -0,0 +1,1258 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#include "phy_drv.h"
+#include "phy_drv_mii.h"
+#ifdef PHY_LINK_CHANGE_NOTIFY
+#include <linux/workqueue.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/slab.h>
+#endif
+#ifdef PHY_PROC_FS
+#include "proc_cmd.h"
+#endif
+#ifdef MACSEC_SUPPORT
+#include "phy_macsec_api.h"
+#include "phy_macsec_common.h"
+#endif
+
+#define MAX_PHY_DEVS 31     /* value should be < 32 */ 
+
+extern phy_drv_t phy_drv_6858_egphy;
+extern phy_drv_t phy_drv_6846_egphy;
+extern phy_drv_t phy_drv_6856_sgmii;
+extern phy_drv_t phy_drv_ext1;
+extern phy_drv_t phy_drv_ext2;
+extern phy_drv_t phy_drv_ext3;
+extern phy_drv_t phy_drv_lport_serdes;
+extern phy_drv_t phy_drv_53125_gphy;
+extern phy_drv_t phy_drv_sf2_gphy;      //TODO_DSL? create 4 different phy types for 138,148,4908, don't know if above types can be reused ...
+extern phy_drv_t phy_drv_sf2_cl45_phy;
+extern phy_drv_t phy_drv_sf2_serdes;
+extern phy_drv_t phy_drv_sf2_xgae;
+extern phy_drv_t phy_drv_crossbar;
+extern phy_drv_t phy_drv_mac2mac;
+extern phy_drv_t phy_drv_63146_egphy;
+
+phy_drv_t *phy_drivers[PHY_TYPE_MAX] = {};
+
+#if defined(CONFIG_BCM_ETH_PWRSAVE)
+int apd_enabled = 1;
+#else
+int apd_enabled = 0;
+#endif
+EXPORT_SYMBOL(apd_enabled);
+
+#if defined(CONFIG_BCM_ENERGY_EFFICIENT_ETHERNET)
+int eee_enabled = 1;
+#else
+int eee_enabled = 0;
+#endif
+EXPORT_SYMBOL(eee_enabled);
+
+int phy_driver_set(phy_drv_t *phy_drv)
+{
+    if (phy_drivers[phy_drv->phy_type])
+    {
+        printk("Failed adding phy driver %s: already set\n", phy_drv->name);
+        return -1;
+    }
+    else
+    {
+        phy_drivers[phy_drv->phy_type] = phy_drv;
+        return 0;
+    }
+}
+EXPORT_SYMBOL(phy_driver_set);
+
+int phy_driver_init(phy_type_t phy_type)
+{
+    phy_drv_t *phy_drv;
+
+    if (!(phy_drv = phy_drivers[phy_type]))
+        return 0;
+
+    return phy_drv_init(phy_drv);
+}
+EXPORT_SYMBOL(phy_driver_init);
+
+int phy_drivers_set(void)
+{
+    int ret = 0;
+
+#ifdef PHY_6858_EGPHY
+    ret |= phy_driver_set(&phy_drv_6858_egphy);
+#endif
+#ifdef PHY_6846_EGPHY
+    ret |= phy_driver_set(&phy_drv_6846_egphy);
+#endif
+#ifdef PHY_6856_SGMII
+    ret |= phy_driver_set(&phy_drv_6856_sgmii);
+#endif
+#ifdef PHY_EXT1
+    ret |= phy_driver_set(&phy_drv_ext1);
+#endif
+#ifdef PHY_EXT2
+    ret |= phy_driver_set(&phy_drv_ext2);
+#endif
+#ifdef PHY_EXT3
+    ret |= phy_driver_set(&phy_drv_ext3);
+#endif
+#ifdef PHY_LPORT_SERDES
+    ret |= phy_driver_set(&phy_drv_lport_serdes);
+#endif
+#ifdef PHY_53125
+    ret |= phy_driver_set(&phy_drv_53125_gphy);
+#endif
+#ifdef PHY_SF2
+    ret |= phy_driver_set(&phy_drv_sf2_gphy);
+#endif
+#ifdef PHY_SF2_SERDES
+    ret |= phy_driver_set(&phy_drv_sf2_serdes);
+#if defined(PHY_SERDES_10G_CAPABLE)
+    ret |= phy_driver_set(&phy_drv_sf2_xgae);
+#endif
+#endif
+#ifdef PHY_63146_EGPHY
+    ret |= phy_driver_set(&phy_drv_63146_egphy);
+#endif
+#ifdef PHY_CROSSBAR
+    ret |= phy_driver_set(&phy_drv_crossbar);
+#endif
+#ifdef PHY_M2M
+    ret |= phy_driver_set(&phy_drv_mac2mac);
+#endif
+    return ret;
+}
+EXPORT_SYMBOL(phy_drivers_set);
+
+int phy_drivers_init(void)
+{
+    int ret = 0;
+
+#ifndef CONFIG_BRCM_QEMU
+    ret |= phy_driver_init(PHY_TYPE_6858_EGPHY);
+    ret |= phy_driver_init(PHY_TYPE_6846_EGPHY);
+    ret |= phy_driver_init(PHY_TYPE_6856_SGMII);
+    ret |= phy_driver_init(PHY_TYPE_EXT1);
+    ret |= phy_driver_init(PHY_TYPE_EXT2);
+    ret |= phy_driver_init(PHY_TYPE_EXT3);
+    ret |= phy_driver_init(PHY_TYPE_LPORT_SERDES);
+    ret |= phy_driver_init(PHY_TYPE_53125);
+    ret |= phy_driver_init(PHY_TYPE_CROSSBAR);
+    ret |= phy_driver_init(PHY_TYPE_SF2_GPHY);
+    ret |= phy_driver_init(PHY_TYPE_MAC2MAC);
+    ret |= phy_driver_init(PHY_TYPE_63146_EGPHY);
+#endif    
+    return ret;
+}
+EXPORT_SYMBOL(phy_drivers_init);
+
+void phy_dev_prog(phy_dev_t *phy_dev, prog_entry_t *prog_entry)
+{
+    while (prog_entry->desc)
+    {
+#ifdef DEBUG
+        printk("Configuring addr %d: ", phy_dev->addr);
+        printk("%s - Writing 0x%04x to register 0x%02x\n", prog_entry->desc, prog_entry->val, prog_entry->reg);
+#endif
+
+        if (phy_dev_write(phy_dev, prog_entry->reg, prog_entry->val) != 0)
+            break;
+
+        prog_entry++;
+    }
+}
+
+char *phy_dev_mii_type_to_str(phy_mii_type_t mii_type)
+{
+	switch (mii_type)
+    {
+	case PHY_MII_TYPE_MII:
+        return "MII";
+	case PHY_MII_TYPE_TMII:
+        return "TMII";
+	case PHY_MII_TYPE_GMII:
+        return "GMII";
+	case PHY_MII_TYPE_RGMII:
+        return "RGMII";
+	case PHY_MII_TYPE_SGMII:
+        return "SGMII";
+	case PHY_MII_TYPE_HSGMII:
+        return "HSGMII";
+	case PHY_MII_TYPE_XFI:
+        return "XFI";
+	case PHY_MII_TYPE_SERDES:
+        return "SERDES";
+	default:
+		return "Unknown";
+	}
+}
+
+char *phy_dev_speed_to_str(phy_speed_t speed)
+{
+	switch (speed)
+    {
+	case PHY_SPEED_10:
+		return "10 Mbps";
+	case PHY_SPEED_100:
+		return "100 Mbps";
+	case PHY_SPEED_1000:
+		return "1000 Mbps";
+	case PHY_SPEED_2500:
+		return "2.5 Gbps";
+	case PHY_SPEED_5000:
+		return "5 Gbps";
+	case PHY_SPEED_10000:
+		return "10 Gbps";
+	default:
+		return "Unknown";
+	}
+}
+
+char *phy_dev_duplex_to_str(phy_duplex_t duplex)
+{
+	switch (duplex)
+    {
+	case PHY_DUPLEX_HALF:
+		return "Half";
+	case PHY_DUPLEX_FULL:
+		return "Full";
+	default:
+		return "Unknown";
+    }
+}
+
+char *phy_dev_flowctrl_to_str(int pause_rx, int pause_tx)
+{
+    if (pause_rx && pause_tx)
+        return "TXRX";
+    else if (pause_rx)
+        return "RX";
+    else if (pause_tx)
+        return "TX";
+    else
+        return "";
+}
+
+void phy_dev_print_status(phy_dev_t *phy_dev)
+{
+    if (phy_dev->link)
+    {
+        printk("%s:%s:0x%x - Link Up %s %s duplex\n", 
+            phy_dev->phy_drv->name, phy_dev_mii_type_to_str(phy_dev->mii_type), phy_dev->addr,
+            phy_dev_speed_to_str(phy_dev->speed),
+            phy_dev_duplex_to_str(phy_dev->duplex));
+    }
+    else
+    {
+        printk("%s:%s:0x%x - Link Down\n", phy_dev->phy_drv->name, phy_dev_mii_type_to_str(phy_dev->mii_type), phy_dev->addr);
+	}
+}
+EXPORT_SYMBOL(phy_dev_print_status);
+
+static phy_dev_t phy_devices[MAX_PHY_DEVS] = {};
+
+phy_dev_t *phy_dev_get(phy_type_t phy_type, uint32_t addr)
+{
+    uint32_t i;
+    phy_dev_t *phy_dev = NULL;
+
+    for (i = 0; i < MAX_PHY_DEVS; i++)
+    {
+        phy_dev_t *phy = &phy_devices[i];
+        
+        if (phy->phy_drv == NULL)
+            continue;
+
+        if ((phy_type != PHY_TYPE_UNKNOWN) &&       // for ioctl use
+            (phy->phy_drv->phy_type != phy_type))
+            continue;
+
+        if (phy->addr != addr)
+            continue;
+
+        phy_dev = phy;
+        break;
+    }
+
+    return phy_dev;
+}
+EXPORT_SYMBOL(phy_dev_get);
+
+phy_dev_t *phy_dev_get_by_i2c(int bus_num)
+{
+    uint32_t i;
+    phy_dev_t *phy_dev = NULL;
+
+    for (i = 0; i < MAX_PHY_DEVS; i++)
+    {
+        phy_dev_t *phy = &phy_devices[i];
+        
+        if (phy->phy_drv == NULL)
+            continue;
+
+        if (phy->phy_drv->phy_type != PHY_TYPE_I2C_PHY)
+            continue;
+
+        if ((phy->addr != bus_num) || (phy->flag & PHY_FLAG_NOT_PRESENTED))
+            continue;
+
+        phy_dev = phy;
+        break;
+    }
+
+    return phy_dev;
+}
+EXPORT_SYMBOL(phy_dev_get_by_i2c);
+
+phy_dev_t *phy_dev_add(phy_type_t phy_type, uint32_t addr, void *priv)
+{
+    uint32_t i;
+    phy_drv_t *phy_drv;
+    phy_dev_t *phy_dev;
+
+    if (!(phy_drv = phy_drivers[phy_type]))
+    {
+        printk("Failed to find phy driver: phy_type=%d\n", phy_type);
+        return NULL;
+    }
+
+    if ((phy_dev = phy_dev_get(phy_type, addr)))
+    {
+        printk("Phy device already exists: %s:%d\n", phy_drv->name, addr);
+        return NULL;
+    }
+
+    for (i = 0; i < MAX_PHY_DEVS && phy_devices[i].phy_drv != NULL; i++);
+
+    if (i ==  MAX_PHY_DEVS)
+    {
+        printk("Failed adding phy device: %s:%d\n", phy_drv->name, addr);
+        return NULL;
+    }
+
+    phy_dev = &phy_devices[i];
+
+    phy_dev->phy_drv = phy_drv;
+    phy_dev->addr = addr;
+    phy_dev->priv = priv;
+
+    return phy_dev;
+}
+EXPORT_SYMBOL(phy_dev_add);
+
+int phy_dev_del(phy_dev_t *phy_dev)
+{
+    phy_drv_dev_del(phy_dev);
+#ifdef PHY_LINK_CHANGE_NOTIFY
+    phy_dev_link_change_unregister(phy_dev);
+#endif
+    memset(phy_dev, 0, sizeof(phy_dev_t));
+
+    return 0;
+}
+EXPORT_SYMBOL(phy_dev_del);
+
+phy_dev_t *phy_drv_find_device(dt_handle_t dt_handle)
+{
+    int i;
+
+    for (i = 0; i < MAX_PHY_DEVS; i++)
+    {
+        if (phy_devices[i].phy_drv == NULL)
+            continue;
+
+        if (dt_is_equal(dt_handle, phy_devices[i].dt_handle))
+            return &phy_devices[i];
+    }
+
+    return NULL;
+}
+EXPORT_SYMBOL(phy_drv_find_device);
+
+/* For internal use only by proc interface */
+int phy_devices_internal_index(phy_dev_t *phy_dev)
+{
+    uint32_t i;
+
+    for (i = 0; i < MAX_PHY_DEVS; i++)
+    {
+        if (&phy_devices[i] == phy_dev && phy_dev->phy_drv)
+            return i;
+    }
+
+    return -1;
+}
+EXPORT_SYMBOL(phy_devices_internal_index);
+
+#ifdef PHY_LINK_CHANGE_NOTIFY
+void phy_dev_link_change_notify(phy_dev_t *phy_dev)
+{
+    int old_link = phy_dev->link;
+
+    phy_dev_read_status(phy_dev);
+
+    if (phy_dev->link != old_link && phy_dev->link_change_cb)
+        phy_dev->link_change_cb(phy_dev->link_change_ctx);
+}
+EXPORT_SYMBOL(phy_dev_link_change_notify);
+
+static void phy_devices_link_change_notify(void)
+{
+    uint32_t i;
+
+    for (i = 0; i < MAX_PHY_DEVS; i++)
+    {
+        if (phy_devices[i].phy_drv == NULL)
+            continue;
+
+        if (phy_devices[i].phy_drv->link_change_register)
+            continue;
+
+        phy_dev_link_change_notify(&phy_devices[i]);
+    }
+}
+
+static struct timer_list phy_link_timer;
+static int phy_link_timer_refs = 0;
+
+static void phy_link_work_cb(struct work_struct *work)
+{
+    phy_devices_link_change_notify();
+    mod_timer(&phy_link_timer, jiffies + msecs_to_jiffies(1000));
+}
+
+DECLARE_WORK(_work, phy_link_work_cb);
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0)
+static void phy_link_timer_cb(unsigned long data)
+#else
+static void phy_link_timer_cb(struct timer_list *tl)
+#endif
+{
+    schedule_work(&_work);
+}
+
+static void phy_link_timer_start(void)
+{
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0)
+    init_timer(&phy_link_timer);
+    phy_link_timer.function = phy_link_timer_cb;
+#else
+    timer_setup(&phy_link_timer, phy_link_timer_cb, 0);
+#endif
+    phy_link_timer.expires = jiffies + msecs_to_jiffies(1000);
+    add_timer(&phy_link_timer);
+}
+
+static void phy_link_timer_stop(void)
+{
+    del_timer(&phy_link_timer);
+}
+
+void phy_dev_link_change_register(phy_dev_t *phy_dev, link_change_cb_t cb, void *ctx)
+{
+    if (phy_dev->link_change_cb != NULL)
+        return;
+
+    phy_dev->link_change_cb = cb;
+    phy_dev->link_change_ctx = ctx;
+
+    if (phy_dev->phy_drv->link_change_register)
+    {
+        phy_dev->phy_drv->link_change_register(phy_dev);
+        return;
+    }
+
+    if (phy_link_timer_refs == 0)
+        phy_link_timer_start();
+
+    phy_link_timer_refs++;
+}
+EXPORT_SYMBOL(phy_dev_link_change_register);
+
+void phy_dev_link_change_unregister(phy_dev_t *phy_dev)
+{
+    if (phy_dev->link_change_cb == NULL)
+        return;
+
+    phy_dev->link_change_cb = NULL;
+    phy_dev->link_change_ctx = NULL;
+
+    if (phy_dev->phy_drv->link_change_unregister)
+    {
+        phy_dev->phy_drv->link_change_unregister(phy_dev);
+        return;
+    }
+
+    phy_link_timer_refs--;
+
+    if (phy_link_timer_refs == 0)
+        phy_link_timer_stop();
+}
+EXPORT_SYMBOL(phy_dev_link_change_unregister);
+
+typedef struct
+{
+    struct work_struct base_work;
+    phy_dev_t *phy_dev;
+    phy_dev_work_func_t func;
+} phy_dev_work_t;
+
+static void phy_dev_work_cb(struct work_struct *work)
+{
+    phy_dev_work_t *phy_dev_work = container_of(work, phy_dev_work_t, base_work);
+    phy_dev_t *phy_dev = phy_dev_work->phy_dev;
+    phy_dev_work_func_t func = phy_dev_work->func;
+
+    func(phy_dev); 
+    kfree(phy_dev_work);
+}
+
+int phy_dev_queue_work(phy_dev_t *phy_dev, phy_dev_work_func_t func)
+{
+    phy_dev_work_t *phy_dev_work = kmalloc(sizeof(phy_dev_work_t), GFP_ATOMIC);
+    if (!phy_dev_work)
+    {
+        printk("phy_dev_queue_work: kmalloc failed to allocate work struct\n");
+        return -1;
+    }
+
+    INIT_WORK(&phy_dev_work->base_work, phy_dev_work_cb);
+    phy_dev_work->phy_dev = phy_dev;
+    phy_dev_work->func = func;
+
+    queue_work(system_unbound_wq, &phy_dev_work->base_work);
+
+    return 0;
+}
+#endif
+
+#ifdef PHY_PROC_FS
+
+#define PROC_DIR           "driver/phy"
+#define CMD_PROC_FILE      "cmd"
+
+static struct proc_dir_entry *proc_dir;
+static struct proc_dir_entry *cmd_proc_file;
+
+static int phy_proc_cmd_status(int argc, char *argv[])
+{
+    int id;
+    phy_dev_t *phy_dev;
+
+    if (argc < 2)
+        goto Error;
+
+    if (kstrtos32(argv[1], 10, &id) || id < 0 || id >= MAX_PHY_DEVS)
+        goto Error;
+
+    phy_dev = &phy_devices[id];
+    if (phy_dev->phy_drv == NULL)
+        goto Error;
+
+    printk("Phy %d status:\n", id);
+    printk("\tDriver: %s\n", phy_dev->phy_drv->name);
+    printk("\tMII: %s\n", phy_dev_mii_type_to_str(phy_dev->mii_type));
+    printk("\tAddress: 0x%02x\n", phy_dev->addr);
+    printk("\tLink: %s\n", phy_dev->link ? "Up" : "Down");
+    printk("\tSpeed: %s\n", phy_dev_speed_to_str(phy_dev->speed));
+    printk("\tDuplex: %s\n", phy_dev_duplex_to_str(phy_dev->duplex));
+    printk("\tFlowctrl: %s\n", phy_dev_flowctrl_to_str(phy_dev->pause_rx, phy_dev->pause_tx));
+
+    return 0;
+
+Error:
+    printk("Usage: status <id>\n");
+    return 0;
+}
+
+static int phy_proc_cmd_init(int argc, char *argv[])
+{
+    int id;
+    phy_dev_t *phy_dev;
+
+    if (argc < 2)
+        goto Error;
+
+    if (kstrtos32(argv[1], 10, &id) || id < 0 || id >= MAX_PHY_DEVS)
+        goto Error;
+
+    phy_dev = &phy_devices[id];
+    if (phy_dev->phy_drv == NULL)
+        goto Error;
+
+    if (phy_dev_init(phy_dev))
+        goto Error;
+
+    return 0;
+
+Error:
+    printk("Usage: init <id>\n");
+    return 0;
+}
+
+static int phy_proc_cmd_list(int argc, char *argv[])
+{
+    int id;
+    uint32_t phyid;
+    phy_dev_t *phy_dev;
+
+    printk("|====================================================================================|\n");
+    printk("|  Id |  State  |   Phy   |   Bus  | Addr |   Speed   | Duplex | Flowctl |   PHYID   |\n");
+    printk("|====================================================================================|\n"); 
+
+    for (id = 0; id < MAX_PHY_DEVS; id++)
+    {
+        phy_dev = &phy_devices[id];
+        if (phy_dev->phy_drv == NULL)
+            continue;
+
+        printk("| %2d  ", id);
+
+        phy_dev_phyid_get(phy_dev, &phyid);
+
+        pr_cont("| %s  ", phy_dev->link ? " Up   " : " Down ");
+        pr_cont("| %7s ", phy_dev->phy_drv->name);
+        pr_cont("| %6s ", phy_dev->mii_type == PHY_MII_TYPE_UNKNOWN ? "" : phy_dev_mii_type_to_str(phy_dev->mii_type));
+        pr_cont("| 0x%02x ", phy_dev->addr);
+        pr_cont("| %9s ", phy_dev->speed == PHY_SPEED_UNKNOWN ? "" : phy_dev_speed_to_str(phy_dev->speed));
+        pr_cont("| %5s  ", phy_dev->duplex == PHY_DUPLEX_UNKNOWN ? "" : phy_dev_duplex_to_str(phy_dev->duplex));
+        pr_cont("|  %4s   ", phy_dev_flowctrl_to_str(phy_dev->pause_rx, phy_dev->pause_tx));
+        pr_cont("| %04x:%04x ", phyid >> 16, phyid & 0xffff); 
+        pr_cont("|\n");
+    }
+    printk("|====================================================================================|\n"); 
+
+    return 0;
+}
+
+static int phy_proc_cmd_read(int argc, char *argv[])
+{
+    int id;
+    uint16_t reg, val;
+    phy_dev_t *phy_dev;
+
+    if (argc < 3)
+        goto Error;
+
+    if (kstrtos32(argv[1], 10, &id) || id < 0 || id >= MAX_PHY_DEVS)
+        goto Error;
+
+    if (kstrtou16(argv[2], 16, &reg))
+        goto Error;
+
+    phy_dev = &phy_devices[id];
+    if (phy_dev->phy_drv == NULL)
+        goto Error;
+
+    if (phy_dev_read(phy_dev, reg, &val))
+        goto Error;
+
+    printk("Read register 0x%04x=0x%04x\n", reg, val);
+
+    return 0;
+
+Error:
+    printk("Usage: read <id> <reg>\n");
+    return 0;
+}
+
+static int phy_proc_cmd_write(int argc, char *argv[])
+{
+    int id;
+    uint16_t reg, val;
+    phy_dev_t *phy_dev;
+
+    if (argc < 4)
+        goto Error;
+
+    if (kstrtos32(argv[1], 10, &id) || id < 0 || id >= MAX_PHY_DEVS)
+        goto Error;
+
+    if (kstrtou16(argv[2], 16, &reg))
+        goto Error;
+
+    if (kstrtou16(argv[3], 16, &val))
+        goto Error;
+
+    phy_dev = &phy_devices[id];
+    if (phy_dev->phy_drv == NULL)
+        goto Error;
+
+    if (phy_dev_write(phy_dev, reg, val))
+        goto Error;
+
+    printk("Write register 0x%04x=0x%04x\n", reg, val);
+
+    return 0;
+
+Error:
+    printk("Usage: write <id> <reg> <val>\n");
+    return 0;
+}
+
+static int phy_proc_cmd_read45(int argc, char *argv[])
+{
+    int id;
+    uint16_t dev, reg, val;
+    phy_dev_t *phy_dev;
+
+    if (argc < 4)
+        goto Error;
+
+    if (kstrtos32(argv[1], 10, &id) || id < 0 || id >= MAX_PHY_DEVS)
+        goto Error;
+
+    if (kstrtou16(argv[2], 16, &dev))
+        goto Error;
+
+    if (kstrtou16(argv[3], 16, &reg))
+        goto Error;
+
+    phy_dev = &phy_devices[id];
+    if (phy_dev->phy_drv == NULL)
+        goto Error;
+
+    if (phy_bus_c45_read(phy_dev, dev, reg, &val))
+        goto Error;
+
+    printk("Read45 dev=%d register 0x%04x=0x%04x\n", dev, reg, val);
+
+    return 0;
+
+Error:
+    printk("Usage: read45 <id> <dev> <reg>\n");
+    return 0;
+}
+
+static int phy_proc_cmd_write45(int argc, char *argv[])
+{
+    int id;
+    uint16_t dev, reg, val;
+    phy_dev_t *phy_dev;
+
+    if (argc < 5)
+        goto Error;
+
+    if (kstrtos32(argv[1], 10, &id) || id < 0 || id >= MAX_PHY_DEVS)
+        goto Error;
+
+    if (kstrtou16(argv[2], 16, &dev))
+        goto Error;
+
+    if (kstrtou16(argv[3], 16, &reg))
+        goto Error;
+
+    if (kstrtou16(argv[4], 16, &val))
+        goto Error;
+
+    phy_dev = &phy_devices[id];
+    if (phy_dev->phy_drv == NULL)
+        goto Error;
+
+    if (phy_bus_c45_write(phy_dev, dev, reg, val))
+        goto Error;
+
+    printk("Write45 dev=%d register 0x%04x=0x%04x\n", dev, reg, val);
+
+    return 0;
+
+Error:
+    printk("Usage: write45 <id> <dev> <reg> <val>\n");
+    return 0;
+}
+
+static int phy_proc_cmd_read_indirect(int argc, char *argv[])
+{
+    int id;
+    uint16_t temp=0;
+    uint32_t reg, val;
+    phy_dev_t *phy_dev;
+
+    if (argc < 3)
+        goto Error;
+
+    if (kstrtos32(argv[1], 10, &id) || id < 0 || id >= MAX_PHY_DEVS)
+        goto Error;
+
+    if (kstrtou32(argv[2], 16, &reg))
+        goto Error;
+
+    phy_dev = &phy_devices[id];
+    if (phy_dev->phy_drv == NULL)
+        goto Error;
+
+
+    temp = (uint16_t)(reg & 0xffff);
+    if (phy_bus_c45_write(phy_dev, 0x01, 0xa819, temp))
+        goto Error;
+
+    temp = (uint16_t)(reg >> 16);
+    if (phy_bus_c45_write(phy_dev, 0x01, 0xa81a, temp))
+        goto Error;
+
+    if (phy_bus_c45_write(phy_dev, 0x01, 0xa817, 0x000a))
+        goto Error;
+
+    if (phy_bus_c45_read(phy_dev, 0x01, 0xa81b, (uint16_t*)(&val)))
+        goto Error;
+
+    if (phy_bus_c45_read(phy_dev, 0x01, 0xa81c, &temp))
+        goto Error;
+
+    val |= (uint32_t)(temp<<16);
+
+    printk("Read32 register 0x%08x=0x%08x\n", reg, val);
+
+    return 0;
+
+Error:
+    printk("Usage: read32 <id> <reg>\n");
+    return 0;
+}
+
+static int phy_proc_cmd_write_indirect(int argc, char *argv[])
+{
+    int id;
+    uint32_t reg, val;
+    uint16_t temp=0;
+    phy_dev_t *phy_dev;
+
+    if (argc < 4)
+        goto Error;
+
+    if (kstrtos32(argv[1], 10, &id) || id < 0 || id >= MAX_PHY_DEVS)
+        goto Error;
+
+    if (kstrtou32(argv[2], 16, &reg))
+        goto Error;
+
+    if (kstrtou32(argv[3], 16, &val))
+        goto Error;
+
+    phy_dev = &phy_devices[id];
+    if (phy_dev->phy_drv == NULL)
+        goto Error;
+
+
+    temp = (uint16_t)(reg & 0xffff);
+    if (phy_bus_c45_write(phy_dev, 0x01, 0xa819, temp))
+        goto Error;
+
+    temp = (uint16_t)(reg >> 16);
+    if (phy_bus_c45_write(phy_dev, 0x01, 0xa81a, temp))
+        goto Error;
+
+    temp = (uint16_t)(val & 0xffff);
+    if (phy_bus_c45_write(phy_dev, 0x01, 0xa81b, temp))
+        goto Error;
+
+    temp = (uint16_t)(val >> 16);
+    if (phy_bus_c45_write(phy_dev, 0x01, 0xa81c, temp))
+        goto Error;
+
+    if (phy_bus_c45_write(phy_dev, 0x01, 0xa817, 0x0009))
+        goto Error;
+
+    return 0;
+
+Error:
+    printk("Usage: write32 <id> <reg> <val>\n");
+    return 0;
+}
+
+#ifdef MACSEC_SUPPORT
+static int phy_proc_macsec_enable64(int argc, char *argv[])
+{
+    int id, ret, enable;
+    phy_dev_t *phy_dev;
+    macsec_api_data macsec_data = {};
+    macsec_api_settings_t settings = {0,0,0,0,0,0,0,0,1,0,0,0,1};
+    macsec_api_sa_t sa_egress = {{0xde, 0xad, 0xbe, 0xef, 0xa5, 0x5a, 0x00, 0x01}, {0x7A, 0x30, 0xC1, 0x18}, {0xE6, 0x30, 0xE8, 0x1A, 0x48, 0xDE, 0x86, 0xA2, 0x1C, 0x66, 0xFA, 0x6D},
+                                 {0xad, 0x7a, 0x2b, 0xd0, 0x3e, 0xac, 0x83, 0x5a, 0x6f, 0x62, 0x0f, 0xdc, 0xb5, 0x06, 0xb3, 0x45, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 
+                                 {0x73, 0xa2, 0x3d, 0x80, 0x12, 0x1d, 0xe2, 0xd5, 0xa8, 0x50, 0x25, 0x3f, 0xcf, 0x43, 0x12, 0x0e}, 
+                                 16, 1, {{0,1,1,0,0,0,1,1,1}}, MACSEC_SA_ACTION_EGRESS};
+    macsec_api_sa_t sa_ingress = {{0xde, 0xad, 0xbe, 0xef, 0xa5, 0x5a, 0x00, 0x01}, {0x7A, 0x30, 0xC1, 0x18}, {0xE6, 0x30, 0xE8, 0x1A, 0x48, 0xDE, 0x86, 0xA2, 0x1C, 0x66, 0xFA, 0x6D},
+                                 {0xad, 0x7a, 0x2b, 0xd0, 0x3e, 0xac, 0x83, 0x5a, 0x6f, 0x62, 0x0f, 0xdc, 0xb5, 0x06, 0xb3, 0x45, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 
+                                 {0x73, 0xa2, 0x3d, 0x80, 0x12, 0x1d, 0xe2, 0xd5, 0xa8, 0x50, 0x25, 0x3f, 0xcf, 0x43, 0x12, 0x0e}, 
+                                 16, 1, {{0,0,MACSEC_FRAME_VALIDATE_STRICT,0,1,0,0,0}}, MACSEC_SA_ACTION_INGRESS};
+
+    if (argc < 3)
+        goto Error;
+
+    if (kstrtos32(argv[1], 10, &id) || id < 0 || id >= MAX_PHY_DEVS)
+        goto Error;
+
+    if (kstrtou32(argv[2], 10, &enable))
+        goto Error;
+
+    phy_dev = &phy_devices[id];
+    if (phy_dev->phy_drv == NULL)
+        goto Error;
+
+    if (phy_dev->phy_drv->macsec_oper == NULL)
+        goto Error;
+
+    macsec_data.op = MACSEC_OPER_INIT;
+    memcpy(&macsec_data.ext_data.secy_conf, &settings, sizeof(macsec_api_settings_t));
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    /* Egress */
+    macsec_data.direction = 0;
+
+    macsec_data.op = MACSEC_OPER_VPORT_ADD;
+    macsec_data.index1 = 0;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    macsec_data.op = MACSEC_OPER_SA_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    memcpy(&macsec_data.ext_data.sa_conf, &sa_egress, sizeof(macsec_api_sa_t));
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    macsec_data.ext_data.rule_conf.num_tags = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ENABLE;
+    macsec_data.index1 = 0;
+    macsec_data.data1 = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    /* Ingress */
+    macsec_data.direction = 1;
+
+    macsec_data.op = MACSEC_OPER_VPORT_ADD;
+    macsec_data.index1 = 0;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    macsec_data.op = MACSEC_OPER_SA_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    memcpy(&macsec_data.ext_data.sa_conf, &sa_ingress, sizeof(macsec_api_sa_t));
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    macsec_data.ext_data.rule_conf.num_tags = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ENABLE;
+    macsec_data.index1 = 0;
+    macsec_data.data1 = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+Error:
+    printk("Usage: macsecenable64 <id> <1/0>\n");
+    return 0;
+}
+
+static int phy_proc_macsec_enable(int argc, char *argv[])
+{
+    int id, ret, enable;
+    phy_dev_t *phy_dev;
+    macsec_api_data macsec_data = {};
+    macsec_api_settings_t settings = {0,0,0,0,0,0,0,0,1,0,0,0,1};
+    macsec_api_sa_t sa_egress = {{0xde, 0xad, 0xbe, 0xef, 0xa5, 0x5a, 0x00, 0x01}, {}, {},
+                                 {0xad, 0x7a, 0x2b, 0xd0, 0x3e, 0xac, 0x83, 0x5a, 0x6f, 0x62, 0x0f, 0xdc, 0xb5, 0x06, 0xb3, 0x45, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 
+                                 {0x73, 0xa2, 0x3d, 0x80, 0x12, 0x1d, 0xe2, 0xd5, 0xa8, 0x50, 0x25, 0x3f, 0xcf, 0x43, 0x12, 0x0e}, 
+                                 16, 0, {{0,1,1,0,0,0,1,1,0}}, MACSEC_SA_ACTION_EGRESS};
+    macsec_api_sa_t sa_ingress = {{0xde, 0xad, 0xbe, 0xef, 0xa5, 0x5a, 0x00, 0x01}, {}, {},
+                                 {0xad, 0x7a, 0x2b, 0xd0, 0x3e, 0xac, 0x83, 0x5a, 0x6f, 0x62, 0x0f, 0xdc, 0xb5, 0x06, 0xb3, 0x45, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 
+                                 {0x73, 0xa2, 0x3d, 0x80, 0x12, 0x1d, 0xe2, 0xd5, 0xa8, 0x50, 0x25, 0x3f, 0xcf, 0x43, 0x12, 0x0e}, 
+                                 16, 0, {{0,0,MACSEC_FRAME_VALIDATE_STRICT,0,1,0,0,1}}, MACSEC_SA_ACTION_INGRESS};
+
+    if (argc < 3)
+        goto Error;
+
+    if (kstrtos32(argv[1], 10, &id) || id < 0 || id >= MAX_PHY_DEVS)
+        goto Error;
+
+    if (kstrtou32(argv[2], 10, &enable))
+        goto Error;
+
+    phy_dev = &phy_devices[id];
+    if (phy_dev->phy_drv == NULL)
+        goto Error;
+
+    if (phy_dev->phy_drv->macsec_oper == NULL)
+        goto Error;
+
+    macsec_data.op = MACSEC_OPER_INIT;
+    memcpy(&macsec_data.ext_data.secy_conf, &settings, sizeof(macsec_api_settings_t));
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    /* Egress */
+    macsec_data.direction = 0;
+
+    macsec_data.op = MACSEC_OPER_VPORT_ADD;
+    macsec_data.index1 = 0;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    macsec_data.op = MACSEC_OPER_SA_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    memcpy(&macsec_data.ext_data.sa_conf, &sa_egress, sizeof(macsec_api_sa_t));
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    macsec_data.ext_data.rule_conf.num_tags = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ENABLE;
+    macsec_data.index1 = 0;
+    macsec_data.data1 = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    /* Ingress */
+    macsec_data.direction = 1;
+
+    macsec_data.op = MACSEC_OPER_VPORT_ADD;
+    macsec_data.index1 = 0;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    macsec_data.op = MACSEC_OPER_SA_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    memcpy(&macsec_data.ext_data.sa_conf, &sa_ingress, sizeof(macsec_api_sa_t));
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    macsec_data.ext_data.rule_conf.num_tags = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ENABLE;
+    macsec_data.index1 = 0;
+    macsec_data.data1 = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+Error:
+    printk("Usage: macsecenable <id> <1/0>\n");
+    return 0;
+}
+
+static int phy_proc_macsec_enablebp(int argc, char *argv[])
+{
+    int id, ret, enable;
+    phy_dev_t *phy_dev;
+    macsec_api_data macsec_data = {};
+    macsec_api_settings_t settings = {0,0,0,0,0,0,0,0,1,0,0,0,1};
+    macsec_api_sa_bd_t sa_bp = {};
+
+    if (argc < 3)
+        goto Error;
+
+    if (kstrtos32(argv[1], 10, &id) || id < 0 || id >= MAX_PHY_DEVS)
+        goto Error;
+
+    if (kstrtou32(argv[2], 10, &enable))
+        goto Error;
+
+    phy_dev = &phy_devices[id];
+    if (phy_dev->phy_drv == NULL)
+        goto Error;
+
+    if (phy_dev->phy_drv->macsec_oper == NULL)
+        goto Error;
+
+    macsec_data.op = MACSEC_OPER_INIT;
+    memcpy(&macsec_data.ext_data.secy_conf, &settings, sizeof(macsec_api_settings_t));
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    /* Egress */
+    macsec_data.direction = 0;
+
+    macsec_data.op = MACSEC_OPER_VPORT_ADD;
+    macsec_data.index1 = 0;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    macsec_data.op = MACSEC_OPER_SA_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    memcpy(&macsec_data.ext_data.sa_conf, &sa_bp, sizeof(macsec_api_sa_t));
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    macsec_data.ext_data.rule_conf.num_tags = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ENABLE;
+    macsec_data.index1 = 0;
+    macsec_data.data1 = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    /* Ingress */
+    macsec_data.direction = 1;
+
+    macsec_data.op = MACSEC_OPER_VPORT_ADD;
+    macsec_data.index1 = 0;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    macsec_data.op = MACSEC_OPER_SA_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    memcpy(&macsec_data.ext_data.sa_conf, &sa_bp, sizeof(macsec_api_sa_t));
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ADD;
+    macsec_data.index1 = 0;
+    macsec_data.index2 = 0;
+    macsec_data.ext_data.rule_conf.num_tags = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+    memset(&macsec_data.ext_data, 0, sizeof(macsec_api_ext_data));
+
+    macsec_data.op = MACSEC_OPER_RULE_ENABLE;
+    macsec_data.index1 = 0;
+    macsec_data.data1 = 1;
+    ret = phy_dev->phy_drv->macsec_oper(phy_dev, &macsec_data);
+
+Error:
+    printk("Usage: macsecenable <id> <1/0>\n");
+    return 0;
+}
+#endif
+
+#if defined(PHY_SF2_SERDES)
+extern void phy_drv_sfp_group_list(void);
+static int phy_proc_cmd_sfp_list(int argc, char *argv[])
+{
+    phy_drv_sfp_group_list();
+    return 0;
+}
+#endif
+
+#ifdef PHY_CROSSBAR
+extern void phy_drv_crossbar_group_list(void);
+
+static int phy_proc_cmd_crossbar_list(int argc, char *argv[])
+{
+    phy_drv_crossbar_group_list();
+
+    return 0;
+}
+#endif
+  
+static struct proc_cmd_ops command_entries[] = {
+    { .name = "status", .do_command	= phy_proc_cmd_status},
+    { .name = "init", .do_command	= phy_proc_cmd_init},
+    { .name = "list", .do_command	= phy_proc_cmd_list},
+    { .name = "read", .do_command	= phy_proc_cmd_read},
+    { .name = "write", .do_command	= phy_proc_cmd_write},
+    { .name = "read45", .do_command	= phy_proc_cmd_read45},
+    { .name = "write45", .do_command = phy_proc_cmd_write45},
+    { .name = "read32", .do_command	= phy_proc_cmd_read_indirect},
+    { .name = "write32", .do_command = phy_proc_cmd_write_indirect},
+#ifdef MACSEC_SUPPORT
+    { .name = "macsecenable", .do_command = phy_proc_macsec_enable},
+    { .name = "macsecenable64", .do_command = phy_proc_macsec_enable64},
+    { .name = "macsecenablebp", .do_command = phy_proc_macsec_enablebp},
+#endif
+#ifdef PHY_CROSSBAR
+    { .name = "crossbars", .do_command = phy_proc_cmd_crossbar_list},
+#endif
+#if defined(PHY_SF2_SERDES)
+    { .name = "sfp", .do_command	= phy_proc_cmd_sfp_list},
+#endif
+};
+
+static struct proc_cmd_table phy_command_table = {
+    .module_name = "PHY",
+    .size = ARRAY_SIZE(command_entries),
+    .ops = command_entries
+};
+
+static void phy_proc_exit(void)
+{
+    if (cmd_proc_file) 
+    {
+        remove_proc_entry(CMD_PROC_FILE, proc_dir);
+        cmd_proc_file = NULL;
+    }	
+    if (proc_dir)
+    {
+        remove_proc_entry(PROC_DIR, NULL);
+        proc_dir = NULL;
+    }	
+}
+
+int __init phy_proc_init(void)
+{
+    int status = 0;
+
+    proc_dir = proc_mkdir(PROC_DIR, NULL);
+    if (!proc_dir) 
+    {
+        pr_err("Failed to create PROC directory %s.\n",
+            PROC_DIR);
+        goto error;
+    }
+    cmd_proc_file = proc_create_cmd(CMD_PROC_FILE, proc_dir,
+        &phy_command_table);
+    if (!cmd_proc_file) 
+    {
+        pr_err("Failed to create %s\n", CMD_PROC_FILE);
+        goto error;
+    }
+
+    return status;
+
+error:
+    if (proc_dir)
+        phy_proc_exit();
+
+    status = -EIO;
+    return status;
+}
+postcore_initcall(phy_proc_init);
+#endif
diff --git a/drivers/net/bcmbca/phy/phy_drv.h b/drivers/net/bcmbca/phy/phy_drv.h
new file mode 100644
index 0000000000..a79e0525f2
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv.h
@@ -0,0 +1,1129 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#ifndef __PHY_DRV_H__
+#define __PHY_DRV_H__
+
+#include "bus_drv.h"
+#include "dt_access.h"
+
+#define PHY_CAP_10_HALF         (1 << 0)
+#define PHY_CAP_10_FULL         (1 << 1)
+#define PHY_CAP_100_HALF        (1 << 2)
+#define PHY_CAP_100_FULL        (1 << 3)
+#define PHY_CAP_1000_HALF       (1 << 4)
+#define PHY_CAP_1000_FULL       (1 << 5)
+#define PHY_CAP_2500            (1 << 6)
+#define PHY_CAP_5000            (1 << 7)
+#define PHY_CAP_10000           (1 << 8)
+#define PHY_CAP_AUTONEG         (1 << 9)
+#define PHY_CAP_PAUSE           (1 << 10)
+#define PHY_CAP_PAUSE_ASYM      (1 << 11)
+#define PHY_CAP_REPEATER        (1 << 12)
+#define PHY_CAP_LAST            (1 << 13)
+#define PHY_CAP_ALL             (PHY_CAP_LAST -1)
+
+typedef enum
+{
+    PHY_SPEED_UNKNOWN,
+    PHY_SPEED_AUTO = PHY_SPEED_UNKNOWN,
+    PHY_SPEED_10,
+    PHY_SPEED_100,
+    PHY_SPEED_1000,
+    PHY_SPEED_2500,
+    PHY_SPEED_5000,
+    PHY_SPEED_10000,
+} phy_speed_t;
+
+typedef enum
+{
+    PHY_DUPLEX_UNKNOWN,
+    PHY_DUPLEX_HALF,
+    PHY_DUPLEX_FULL,
+} phy_duplex_t;
+
+typedef enum
+{
+    PHY_MII_TYPE_UNKNOWN,
+    PHY_MII_TYPE_MII,
+    PHY_MII_TYPE_TMII,
+    PHY_MII_TYPE_GMII,
+    PHY_MII_TYPE_RGMII,
+    PHY_MII_TYPE_SGMII,
+    PHY_MII_TYPE_HSGMII,
+    PHY_MII_TYPE_XFI,
+    PHY_MII_TYPE_SERDES,
+    PHY_MII_TYPE_LAST,
+} phy_mii_type_t;
+
+static inline const char *phy_mii_type(phy_mii_type_t interface)
+{
+	switch (interface) {
+	case PHY_MII_TYPE_UNKNOWN:
+		return "";
+	case PHY_MII_TYPE_MII:
+		return "mii";
+	case PHY_MII_TYPE_TMII:
+		return "tmii";
+	case PHY_MII_TYPE_GMII:
+		return "gmii";
+	case PHY_MII_TYPE_RGMII:
+		return "rgmii";
+	case PHY_MII_TYPE_SGMII:
+		return "sgmii";
+	case PHY_MII_TYPE_HSGMII:
+		return "hsgmii";
+	case PHY_MII_TYPE_XFI:
+		return "xfi";
+	case PHY_MII_TYPE_SERDES:
+		return "serdes";
+	default:
+		return "unknown";
+	}
+}
+
+typedef enum
+{
+    PHY_TYPE_UNKNOWN,
+    PHY_TYPE_6858_EGPHY,
+    PHY_TYPE_6846_EGPHY,
+    PHY_TYPE_6856_SGMII,
+    PHY_TYPE_EXT1,
+    PHY_TYPE_EXT2,
+    PHY_TYPE_EXT3,
+    PHY_TYPE_LPORT_SERDES,
+    PHY_TYPE_53125,
+    PHY_TYPE_PON,
+    PHY_TYPE_SF2_GPHY,
+    PHY_TYPE_SF2_CL45_PHY,
+    PHY_TYPE_SF2_SERDES,
+    PHY_TYPE_I2C_PHY,
+    PHY_TYPE_XGAE,
+    PHY_TYPE_CROSSBAR,
+    PHY_TYPE_MAC2MAC,
+    PHY_TYPE_G9991,
+    PHY_TYPE_63146_EGPHY,
+    PHY_TYPE_MAX,
+} phy_type_t;
+
+typedef void (*link_change_cb_t)(void *ctx);
+
+/* Phy device */
+typedef struct phy_dev_s
+{
+    struct phy_drv_s *phy_drv;
+    bus_drv_t *bus_drv;
+    phy_mii_type_t mii_type;
+    link_change_cb_t link_change_cb;
+    void *link_change_ctx;
+    uint32_t addr;          // contains phy address only
+    uint32_t meta_id;       // contains extra phyId info from board param
+    void *priv;
+    int link;
+    phy_speed_t speed;
+    phy_duplex_t duplex;
+    int caps_mask;
+    int pause_rx;
+    int pause_tx;
+    int delay_rx;
+    int delay_tx;
+    int swap_pair;
+    int flag;
+    int loopback_save;
+    int reset_gpio;
+    int reset_gpio_active_hi;
+    int idle_stuffing;
+    void *macsec_dev;
+    /* For cascaded PHY */
+    void *sw_port;
+    struct phy_dev_s *cascade_next;
+    struct phy_dev_s *cascade_prev;
+    dt_handle_t dt_handle;
+    dt_gpio_desc reset_gpiod;
+} phy_dev_t;
+
+#define PHY_FLAG_NOT_PRESENTED      (1<<0)      /* for SFP module indicating not inserted */
+#define PHY_FLAG_POWER_SET_ENABLED  (1<<1)
+#define PHY_FLAG_DYNAMIC            (1<<2)
+#define PHY_FLAG_CABLE_DIAG_ENABLED (1<<3)
+#define PHY_FLAG_TO_EXTSW           (1<<4)
+#define PHY_FLAG_CABLE_DIAG_INITED  (1<<5)
+
+#define CAPS_TYPE_ADVERTISE      0
+#define CAPS_TYPE_SUPPORTED      1
+#define CAPS_TYPE_LP_ADVERTISED  2
+
+typedef enum {
+    INTER_PHY_TYPE_100MBASE_X,
+    INTER_PHY_TYPE_1GBASE_X,
+    INTER_PHY_TYPE_2P5GBASE_X,
+    INTER_PHY_TYPE_2P5GBASE_R, 
+
+    INTER_PHY_TYPE_2P5GIDLE,
+    INTER_PHY_TYPE_5GBASE_R,
+    INTER_PHY_TYPE_5GBASE_X,
+    INTER_PHY_TYPE_5GIDLE,
+
+    INTER_PHY_TYPE_10GBASE_R,
+    INTER_PHY_TYPE_SGMII,
+    INTER_PHY_TYPE_USXGMII,
+
+    INTER_PHY_TYPE_UNKNOWN,
+} inter_phy_type_t;
+
+static uint32_t inter_phy_supported_speed_caps[] = {
+    [INTER_PHY_TYPE_100MBASE_X] = PHY_CAP_100_FULL,
+    [INTER_PHY_TYPE_1GBASE_X]   = PHY_CAP_1000_FULL,
+    [INTER_PHY_TYPE_2P5GBASE_X] = PHY_CAP_2500,
+    [INTER_PHY_TYPE_2P5GBASE_R] = PHY_CAP_2500,
+
+    [INTER_PHY_TYPE_2P5GIDLE]   = PHY_CAP_2500,
+    [INTER_PHY_TYPE_5GBASE_R]   = PHY_CAP_5000,
+    [INTER_PHY_TYPE_5GBASE_X]   = PHY_CAP_5000,
+    [INTER_PHY_TYPE_5GIDLE]     = PHY_CAP_5000,
+
+    [INTER_PHY_TYPE_10GBASE_R]  = PHY_CAP_10000,
+    [INTER_PHY_TYPE_SGMII]      = PHY_CAP_100_FULL | PHY_CAP_1000_FULL,
+    [INTER_PHY_TYPE_USXGMII]    = PHY_CAP_100_FULL | PHY_CAP_1000_FULL | PHY_CAP_2500 | PHY_CAP_5000, PHY_CAP_10000,
+};
+
+#define INTER_PHY_TYPE_100MBASE_X_M      (1<<INTER_PHY_TYPE_100MBASE_X)
+#define INTER_PHY_TYPE_1GBASE_X_M       (1<<INTER_PHY_TYPE_1GBASE_X)
+#define INTER_PHY_TYPE_2P5GBASE_X_M     (1<<INTER_PHY_TYPE_2P5GBASE_X)
+#define INTER_PHY_TYPE_2P5GBASE_R_M     (1<<INTER_PHY_TYPE_2P5GBASE_R)      
+
+#define INTER_PHY_TYPE_2P5GIDLE_M       (1<<INTER_PHY_TYPE_2P5GIDLE)
+#define INTER_PHY_TYPE_5GBASE_R_M       (1<<INTER_PHY_TYPE_5GBASE_R)
+#define INTER_PHY_TYPE_5GBASE_X_M       (1<<INTER_PHY_TYPE_5GBASE_X)
+#define INTER_PHY_TYPE_5GIDLE_M         (1<<INTER_PHY_TYPE_5GIDLE)
+
+#define INTER_PHY_TYPE_10GBASE_R_M      (1<<INTER_PHY_TYPE_10GBASE_R)
+#define INTER_PHY_TYPE_SGMII_M          (1<<INTER_PHY_TYPE_SGMII)
+#define INTER_PHY_TYPE_USXGMII_M        (1<<INTER_PHY_TYPE_USXGMII)
+
+/* 
+    INTER_PHY_TYPES Naming rule:
+    o First letter and second letter: S: SGMII; U: USXGMII; US: USXGMII and SGMII
+    o Letters after first one is [SPEED] : 1, 2P5, 5, 10 means 1G, 2.5G, 5G, 10G
+    o Letters after [SPEED]: X: Base-X; I: Idle Stuffing; R: Base-R
+    ex: INTER_PHY_TYPES_US2P5XIR5XIR10R_M means: 
+        USXGMII, SGMII, 2.5GBase-X, 2.5G Idle Stuffing, 2.5GBase-R, 
+        5GBase-X, 5G Idle Stuffing, 5GBase-R, 10GBase-R capable
+*/
+#define INTER_PHY_TYPES_S1X_M \
+    ( INTER_PHY_TYPE_SGMII_M | INTER_PHY_TYPE_100MBASE_X_M | INTER_PHY_TYPE_1GBASE_X_M )
+
+#define INTER_PHY_TYPES_S2P5X_M ( INTER_PHY_TYPES_S1X_M | INTER_PHY_TYPE_2P5GBASE_X_M )
+
+#define INTER_PHY_TYPES_S2P5X5R10R_M ( \
+    INTER_PHY_TYPES_S2P5X_M | INTER_PHY_TYPE_5GBASE_R_M | INTER_PHY_TYPE_10GBASE_R_M )
+
+#define INTER_PHY_TYPES_S2P5XI5XI_M ( \
+    INTER_PHY_TYPES_S1X_M | INTER_PHY_TYPE_2P5GBASE_X_M | INTER_PHY_TYPE_2P5GIDLE_M | \
+    INTER_PHY_TYPE_5GBASE_X_M | INTER_PHY_TYPE_5GIDLE_M )
+
+#define INTER_PHY_TYPES_US2P5XI5XI_M ( \
+    INTER_PHY_TYPE_USXGMII_M | INTER_PHY_TYPES_S2P5XI5XI_M )
+
+#define INTER_PHY_TYPES_US2P5XI5XI10R_M ( \
+    INTER_PHY_TYPES_US2P5XI5XI_M | INTER_PHY_TYPE_10GBASE_R_M )
+
+#define INTER_PHY_TYPES_US2P5XIR_M ( \
+    INTER_PHY_TYPE_USXGMII_M | INTER_PHY_TYPES_S2P5X_M | \
+    INTER_PHY_TYPE_2P5GIDLE_M | INTER_PHY_TYPE_2P5GBASE_R_M )
+
+#define INTER_PHY_TYPES_US2P5XIR5XIR_M ( \
+    INTER_PHY_TYPES_US2P5XIR_M | \
+    INTER_PHY_TYPE_5GBASE_X_M | INTER_PHY_TYPE_5GIDLE_M | INTER_PHY_TYPE_5GBASE_R_M )
+
+#define INTER_PHY_TYPES_US2P5XIR5XIR10R_M ( \
+    INTER_PHY_TYPES_US2P5XIR5XIR_M | INTER_PHY_TYPE_10GBASE_R_M )
+
+#define INTER_PHY_TYPES_UNKNOWN_M ((1<<INTER_PHY_TYPE_UNKNOWN)-1)
+
+typedef enum {
+    INTER_PHY_TYPE_UP,      /* interface type on upword toward MAC */
+    INTER_PHY_TYPE_DOWN,    /* interface types on downward away from MAC */
+} inter_phy_types_dir_t;
+
+static inline int get_inter_phy_supported_speed_caps(int inter_phy_types, uint32_t *supported_speed_caps)
+{
+    int i;
+
+    *supported_speed_caps = 0;
+    for (i=0; i<INTER_PHY_TYPE_UNKNOWN; i++)
+    {
+        if (!(inter_phy_types & (1<<i)))
+            continue;
+
+        *supported_speed_caps |= inter_phy_supported_speed_caps[i];
+    }
+    return 0;
+}
+
+/* Phy driver */
+typedef struct phy_drv_s
+{
+    phy_type_t phy_type;
+    char *name;
+    int initialized;
+    int (*read)(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val);
+    int (*write)(phy_dev_t *phy_dev, uint16_t reg, uint16_t val);
+    int (*power_get)(phy_dev_t *phy_dev, int *enable);
+    int (*power_set)(phy_dev_t *phy_dev, int enable);
+    int (*apd_get)(phy_dev_t *phy_dev, int *enable);
+    int (*apd_set)(phy_dev_t *phy_dev, int enable);
+    int (*eee_get)(phy_dev_t *phy_dev, int *enable);
+    int (*eee_set)(phy_dev_t *phy_dev, int enable);
+    int (*eee_resolution_get)(phy_dev_t *phy_dev, int *enable);
+    int (*read_status)(phy_dev_t *phy_dev);
+    int (*speed_set)(phy_dev_t *phy_dev, phy_speed_t speed, phy_duplex_t duplex);
+    int (*config_speed_get)(phy_dev_t *phy_dev, phy_speed_t *speed, phy_duplex_t *duplex);
+    int (*caps_get)(phy_dev_t *phy_dev, int caps_type, uint32_t *caps);
+    int (*caps_set)(phy_dev_t *phy_dev, uint32_t caps);
+    int (*inter_phy_types_get)(phy_dev_t *phy_dev, inter_phy_types_dir_t if_dir, uint32_t *types);
+    int (*inter_phy_types_set)(phy_dev_t *phy_dev, inter_phy_types_dir_t if_dir, uint32_t types);
+    int (*phyid_get)(phy_dev_t *phy_dev, uint32_t *phyid);
+    int (*init)(phy_dev_t *phy_dev);
+    int (*link_change_register)(phy_dev_t *phy_dev);
+    int (*link_change_unregister)(phy_dev_t *phy_dev);
+    int (*dev_add)(phy_dev_t *phy_dev);
+    int (*dev_del)(phy_dev_t *phy_dev);
+    int (*drv_init)(struct phy_drv_s *phy_drv);
+    int (*isolate_phy)(phy_dev_t *phy_dev, int isolate);
+    int (*super_isolate_phy)(phy_dev_t *phy_dev, int isolate);
+    int (*loopback_get) (phy_dev_t *phy_dev, int *enable, phy_speed_t *speed);
+    int (*loopback_set) (phy_dev_t *phy_dev, int enable, phy_speed_t speed);
+    int (*pair_swap_set)(phy_dev_t *phy_dev, int enable);
+    int (*cable_diag_run) (phy_dev_t *phy_dev, int *result, int *pair_len);
+    int (*cable_diag_set) (phy_dev_t *phy_dev, int enable);
+    int (*cable_diag_get) (phy_dev_t *phy_dev, int *enable);
+    int (*auto_mdix_set) (phy_dev_t *phy_dev, int enable);
+    int (*auto_mdix_get) (phy_dev_t *phy_dev, int *enable);
+    int (*wirespeed_set) (phy_dev_t *phy_dev, int enable);
+    int (*wirespeed_get) (phy_dev_t *phy_dev, int *enable);
+    int (*macsec_oper) (phy_dev_t *phy_dev, void *data);
+    int (*dt_priv)(dt_handle_t handle, uint32_t addr, uint32_t phy_mode, void **_priv);
+    int (*leds_init) (phy_dev_t *phy_dev, void *leds_info);
+} phy_drv_t;
+
+typedef struct
+{
+    char *desc;
+    uint16_t reg;
+    uint16_t val;
+} prog_entry_t;
+
+phy_dev_t *phy_dev_get(phy_type_t phy_type, uint32_t addr);
+phy_dev_t *phy_dev_add(phy_type_t phy_type, uint32_t addr, void *priv);
+int phy_dev_del(phy_dev_t *phy_dev);
+phy_dev_t *phy_dev_get_by_i2c(int bus_num);
+
+int phy_drivers_set(void);
+int phy_drivers_init(void);
+int phy_driver_set(phy_drv_t *phy_drv);
+int phy_driver_init(phy_type_t phy_type);
+
+char *phy_dev_mii_type_to_str(phy_mii_type_t mii_type);
+char *phy_dev_speed_to_str(phy_speed_t speed);
+char *phy_dev_duplex_to_str(phy_duplex_t duplex);
+char *phy_dev_flowctrl_to_str(int pause_rx, int pause_tx);
+
+void phy_dev_print_status(phy_dev_t *phy_dev);
+void phy_dev_prog(phy_dev_t *phy_dev, prog_entry_t *prog_entry);
+
+void phy_dev_link_change_register(phy_dev_t *phy_dev, link_change_cb_t cb, void *ctx);
+void phy_dev_link_change_unregister(phy_dev_t *phy_dev);
+void phy_dev_link_change_notify(phy_dev_t *phy_dev);
+
+typedef void (*phy_dev_work_func_t)(phy_dev_t *phy_dev);
+int phy_dev_queue_work(phy_dev_t *phy_dev, phy_dev_work_func_t func);
+
+phy_dev_t *phy_drv_find_device(dt_handle_t handle);
+void phy_dev_attach(phy_dev_t *phy_dev, uint32_t phy_mode, int delay_rx, int delay_tx);
+
+#define is_cascade_phy(phy) (phy->cascade_prev || phy->cascade_next)
+#define cascade_phy_get_next(phy)   ((phy->cascade_next && !(phy->cascade_next->flag & PHY_FLAG_NOT_PRESENTED))? phy->cascade_next : NULL)
+#define cascade_phy_get_prev(phy)   (phy->cascade_prev? phy->cascade_prev : NULL)
+
+static inline phy_dev_t *cascade_phy_get_first(phy_dev_t *phy_dev)
+{
+    phy_dev_t *phy;
+
+    for(phy=phy_dev; phy->cascade_prev; phy=phy->cascade_prev);
+    return phy;
+}
+
+static inline phy_dev_t *cascade_phy_get_last(phy_dev_t *phy_dev)
+{
+    phy_dev_t *phy;
+
+    if (!phy_dev) return NULL;
+    for(phy=phy_dev;
+        phy->cascade_next && !(phy->cascade_next->flag & PHY_FLAG_NOT_PRESENTED);
+        phy=phy->cascade_next);
+    return phy;
+}
+
+static inline int phy_bus_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val)
+{
+    if (!phy_dev->bus_drv)
+        return 0;
+
+    return phy_dev->bus_drv->c22_read(phy_dev->addr, reg, val);
+}
+
+static inline int phy_bus_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val)
+{
+    if (!phy_dev->bus_drv)
+        return 0;
+
+    return phy_dev->bus_drv->c22_write(phy_dev->addr, reg, val);
+}
+
+static inline int phy_bus_c45_read(phy_dev_t *phy_dev, uint16_t dev, uint16_t reg, uint16_t *val)
+{
+    if (!phy_dev->bus_drv)
+        return 0;
+
+    return phy_dev->bus_drv->c45_read(phy_dev->addr, dev, reg, val);
+}
+
+static inline int phy_bus_c45_write(phy_dev_t *phy_dev, uint16_t dev, uint16_t reg, uint16_t val)
+{
+    if (!phy_dev->bus_drv)
+        return 0;
+
+    return phy_dev->bus_drv->c45_write(phy_dev->addr, dev, reg, val);
+}
+
+static inline int phy_dev_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val)
+{
+    if (phy_dev->phy_drv->read)
+        return phy_dev->phy_drv->read(phy_dev, reg, val);
+    else
+        return phy_bus_read(phy_dev, reg, val);
+}
+
+static inline int phy_dev_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val)
+{
+    if (phy_dev->phy_drv->write)
+        return phy_dev->phy_drv->write(phy_dev, reg, val);
+    else
+        return phy_bus_write(phy_dev, reg, val);
+}
+
+static inline int phy_dev_isolate_phy(phy_dev_t *phy_dev, int isolate)
+{
+    if (!phy_dev->phy_drv->isolate_phy)
+        return 0;
+
+    return phy_dev->phy_drv->isolate_phy(phy_dev, isolate);
+}
+
+static inline int phy_dev_super_isolate_phy(phy_dev_t *phy_dev, int isolate)
+{
+    if (!phy_dev->phy_drv->super_isolate_phy)
+        return 0;
+
+    return phy_dev->phy_drv->super_isolate_phy(phy_dev, isolate);
+}
+
+static inline int phy_dev_pair_swap_set(phy_dev_t *phy_dev, int enable)
+{
+    if (!phy_dev->phy_drv->pair_swap_set)
+        return 0;
+
+    return phy_dev->phy_drv->pair_swap_set(phy_dev, enable);
+}
+
+static inline int phy_dev_power_get(phy_dev_t *phy_dev, int *enable)
+{
+    *enable = 0;
+
+    if (!phy_dev->phy_drv->power_get)
+        return 0;
+
+    return phy_dev->phy_drv->power_get(phy_dev, enable);
+}
+
+static inline int phy_dev_power_set(phy_dev_t *phy_dev, int enable)
+{
+    if (is_cascade_phy(phy_dev))
+    {
+        phy_dev_t *cascade;
+        for (cascade = cascade_phy_get_first(phy_dev); cascade; cascade = cascade_phy_get_next(cascade))
+        {
+            //printk("phy %s:%d power_set=%d\n", (phy_dev->phy_drv) ? cascade->phy_drv->name : NULL, cascade->addr, enable);
+            if (enable)
+                cascade->flag |= PHY_FLAG_POWER_SET_ENABLED;
+            else
+                cascade->flag &= ~PHY_FLAG_POWER_SET_ENABLED;
+
+            if (cascade->phy_drv->power_set)
+                cascade->phy_drv->power_set(cascade, enable);
+        }
+        return 0;
+    }
+    //printk("phy %s:%d power_set=%d\n", (phy_dev->phy_drv) ? phy_dev->phy_drv->name : NULL, phy_dev->addr, enable);
+    if (enable)
+        phy_dev->flag |= PHY_FLAG_POWER_SET_ENABLED;
+    else
+        phy_dev->flag &= ~PHY_FLAG_POWER_SET_ENABLED;
+
+    if (!phy_dev->phy_drv->power_set)
+        return 0;
+
+    return phy_dev->phy_drv->power_set(phy_dev, enable);
+}
+
+static inline int phy_dev_apd_get(phy_dev_t *phy_dev, int *enable)
+{
+    *enable = 0;
+
+    if (!phy_dev->phy_drv->apd_get)
+        return 0;
+
+    return phy_dev->phy_drv->apd_get(phy_dev, enable);
+}
+
+static inline int phy_dev_apd_set(phy_dev_t *phy_dev, int enable)
+{
+    if (!phy_dev->phy_drv->apd_set)
+        return 0;
+
+    return phy_dev->phy_drv->apd_set(phy_dev, enable);
+}
+
+static inline int phy_dev_cable_diag_run(phy_dev_t *phy_dev, int *result, int *pair_len)
+{
+    if (!phy_dev->phy_drv->cable_diag_run)
+        return -1;
+    return phy_dev->phy_drv->cable_diag_run(phy_dev, result, pair_len);
+}
+
+static inline int phy_dev_cable_diag_is_supported(phy_dev_t *phy_dev)
+{
+    return phy_dev->phy_drv->cable_diag_run != NULL;
+}
+
+static inline int phy_dev_cable_diag_is_enabled(phy_dev_t *phy_dev)
+{
+    return (phy_dev->flag & PHY_FLAG_CABLE_DIAG_ENABLED) > 0;
+}
+
+static inline int phy_dev_cable_diag_set(phy_dev_t *phy_dev, int enable)
+{
+    if (!phy_dev->phy_drv->cable_diag_run)
+        return -1;
+
+    phy_dev->flag &= ~PHY_FLAG_CABLE_DIAG_ENABLED;
+    phy_dev->flag |= enable? PHY_FLAG_CABLE_DIAG_ENABLED: 0;
+
+    if (!phy_dev->phy_drv->cable_diag_set)
+        return 0;
+
+    return phy_dev->phy_drv->cable_diag_set(phy_dev, enable);
+}
+
+static inline int phy_dev_cable_diag_get(phy_dev_t *phy_dev, int *enable)
+{
+    if (!phy_dev->phy_drv->cable_diag_run)
+        return -1;
+
+    *enable = (phy_dev->flag & PHY_FLAG_CABLE_DIAG_ENABLED) > 0;
+    return 0;
+}
+
+static inline int phy_dev_eee_get(phy_dev_t *phy_dev, int *enable)
+{
+    *enable = 0;
+
+    if (!phy_dev->phy_drv->eee_get)
+        return 0;
+
+    return phy_dev->phy_drv->eee_get(phy_dev, enable);
+}
+
+static inline int phy_dev_eee_set(phy_dev_t *phy_dev, int enable)
+{
+    if (!phy_dev->phy_drv->eee_set)
+        return 0;
+
+    return phy_dev->phy_drv->eee_set(phy_dev, enable);
+}
+
+static inline int phy_dev_eee_resolution_get(phy_dev_t *phy_dev, int *enable)
+{
+    *enable = 0;
+
+    if (!phy_dev->phy_drv->eee_resolution_get)
+        return 0;
+
+    return phy_dev->phy_drv->eee_resolution_get(phy_dev, enable);
+}
+
+static inline int phy_dev_read_status(phy_dev_t *phy_dev)
+{
+    int ret = 0;
+#if !defined(DSL_DEVICES)
+    phy_speed_t speed = phy_dev->speed;
+#endif
+
+    if (!phy_dev->phy_drv->read_status)
+        goto Exit;
+
+    if ((ret = phy_dev->phy_drv->read_status(phy_dev)))
+        goto Exit;
+
+#if !defined(DSL_DEVICES) /* DSL product has revert chain direction due to dyanmic module support */
+    if (phy_dev->speed == speed)
+        goto Exit;
+
+    if (!phy_dev->cascade_prev)
+        goto Exit;
+
+    if (!phy_dev->cascade_prev->phy_drv->speed_set)
+        goto Exit;
+
+    if ((ret = phy_dev->cascade_prev->phy_drv->speed_set(phy_dev->cascade_prev, phy_dev->speed, phy_dev->duplex)))
+        goto Exit;
+#endif
+
+#if defined(DSL_DEVICES)
+    // administratively force link down if ethernet phy is not in power enable state
+    if (phy_dev->phy_drv->phy_type != PHY_TYPE_PON &&
+        !(phy_dev->flag & PHY_FLAG_POWER_SET_ENABLED) &&
+        !(phy_dev->flag & PHY_FLAG_TO_EXTSW)) {
+        phy_dev->link = 0;
+    }
+#endif
+Exit:
+    return ret;
+}
+
+static inline int phy_dev_config_speed_get(phy_dev_t *phy_dev, phy_speed_t *speed, phy_duplex_t *duplex)
+{
+    if (!phy_dev->phy_drv->config_speed_get)
+        return 0;
+
+    return phy_dev->phy_drv->config_speed_get(phy_dev, speed, duplex);
+}
+
+static inline int phy_dev_speed_set(phy_dev_t *phy_dev, phy_speed_t speed, phy_duplex_t duplex)
+{
+    if (!phy_dev->phy_drv->speed_set)
+        return 0;
+
+    return phy_dev->phy_drv->speed_set(phy_dev, speed, duplex);
+}
+
+static inline int phy_dev_auto_mdix_set(phy_dev_t *phy_dev, int enable)
+{
+    if (!phy_dev->phy_drv->auto_mdix_set)
+        return -1;
+
+    return phy_dev->phy_drv->auto_mdix_set(phy_dev, enable);
+}
+
+static inline int phy_dev_auto_mdix_get(phy_dev_t *phy_dev, int *enable)
+{
+    if (!phy_dev->phy_drv->auto_mdix_get)
+        return -1;
+
+    return phy_dev->phy_drv->auto_mdix_get(phy_dev, enable);
+}
+
+static inline int phy_dev_wirespeed_set(phy_dev_t *phy_dev, int enable)
+{
+    if (!phy_dev->phy_drv->wirespeed_set)
+        return -1;
+
+    return phy_dev->phy_drv->wirespeed_set(phy_dev, enable);
+}
+
+static inline int phy_dev_wirespeed_get(phy_dev_t *phy_dev, int *enable)
+{
+    if (!phy_dev->phy_drv->wirespeed_get)
+        return -1;
+
+    return phy_dev->phy_drv->wirespeed_get(phy_dev, enable);
+}
+
+
+static inline void phy_dev_status_propagate(phy_dev_t *end_phy)
+{
+    phy_dev_t *phy_dev;
+
+    for (phy_dev = end_phy->cascade_prev; phy_dev; phy_dev = phy_dev->cascade_prev)
+    {
+        phy_dev_speed_set(phy_dev, end_phy->speed, end_phy->duplex);
+        phy_dev->link = end_phy->link;
+        phy_dev->speed = end_phy->speed;
+        phy_dev->duplex = end_phy->duplex;
+    }
+}
+
+/* For propagating status toward end PHY for
+    status only without changing configuration during the link up
+    due to the status call-back is done in internal PHY */
+static inline void phy_dev_status_reverse_propagate(phy_dev_t *end_phy)
+{
+    phy_dev_t *phy_dev;
+
+    for (phy_dev = end_phy->cascade_next;
+        phy_dev && !(phy_dev->flag & PHY_FLAG_NOT_PRESENTED);
+        phy_dev = phy_dev->cascade_next)
+    {
+        phy_dev->link = end_phy->link;
+        phy_dev->speed = end_phy->speed;
+        phy_dev->duplex = end_phy->duplex;
+    }
+}
+
+static inline int phy_dev_caps_set(phy_dev_t *phy_dev, uint32_t caps)
+{
+    if (!phy_dev->phy_drv->caps_set)
+        return 0;
+
+    if (phy_dev->caps_mask)
+        caps &= phy_dev->caps_mask;
+
+    return phy_dev->phy_drv->caps_set(phy_dev, caps);
+}
+
+static inline int phy_dev_caps_get(phy_dev_t *phy_dev, int caps_type, uint32_t *caps)
+{
+    int ret;
+    *caps = 0;
+
+    if (!phy_dev->phy_drv->caps_get)
+        return 0;
+
+    ret = phy_dev->phy_drv->caps_get(phy_dev, caps_type, caps);
+
+    if (caps_type == CAPS_TYPE_SUPPORTED && phy_dev->caps_mask)
+        *caps &= phy_dev->caps_mask;
+
+    return ret;
+}
+
+static inline int phy_dev_inter_phy_types_get(phy_dev_t *phy_dev, inter_phy_types_dir_t if_dir, uint32_t *types)
+{
+    *types = INTER_PHY_TYPES_UNKNOWN_M;
+
+    if (!phy_dev->phy_drv->inter_phy_types_get)
+        return 0;
+
+    return phy_dev->phy_drv->inter_phy_types_get(phy_dev, if_dir, types);
+}
+
+static inline int phy_dev_inter_phy_types_set(phy_dev_t *phy_dev, inter_phy_types_dir_t if_dir, uint32_t types)
+{
+    if (!phy_dev->phy_drv->inter_phy_types_set)
+        return 0;
+
+    return phy_dev->phy_drv->inter_phy_types_set(phy_dev, if_dir, types);
+}
+
+static inline phy_speed_t phy_caps_to_max_speed(uint32_t caps)
+{
+    int i;
+    static int speed[] = {PHY_CAP_10000, PHY_SPEED_10000, PHY_CAP_5000, PHY_SPEED_5000, PHY_CAP_2500, PHY_SPEED_2500,
+        PHY_CAP_1000_FULL, PHY_SPEED_1000, PHY_CAP_1000_HALF, PHY_SPEED_1000,
+        PHY_CAP_100_FULL, PHY_SPEED_100, PHY_CAP_100_HALF, PHY_SPEED_100,
+        PHY_CAP_10_FULL, PHY_SPEED_10, PHY_CAP_10_HALF, PHY_SPEED_10};
+
+    for (i=0; i<sizeof(speed)/sizeof(speed[0]); i+=2) {
+        if (caps & speed[i])
+            return speed[i+1];
+    }
+    return PHY_SPEED_UNKNOWN;
+}
+
+static inline uint32_t phy_speed_to_caps(phy_speed_t speed, phy_duplex_t duplex)
+{
+    static uint32_t caps[] = {
+        [PHY_SPEED_AUTO] = PHY_CAP_AUTONEG, 
+        [PHY_SPEED_10] = PHY_CAP_10_FULL, 
+        [PHY_SPEED_100] = PHY_CAP_100_FULL,
+        [PHY_SPEED_1000] = PHY_CAP_1000_FULL, 
+        [PHY_SPEED_2500] = PHY_CAP_2500, 
+        [PHY_SPEED_5000] = PHY_CAP_5000, 
+        [PHY_SPEED_10000] = PHY_CAP_10000};
+    uint32_t cap;
+
+    cap = caps[speed];
+    if (speed <= PHY_SPEED_1000 && speed != PHY_SPEED_AUTO && duplex != PHY_DUPLEX_FULL)
+        cap >>= 1;
+    return cap;
+}
+
+static inline int phy_dev_phyid_get(phy_dev_t *phy_dev, uint32_t *phyid)
+{
+    *phyid = 0;
+
+    if (!phy_dev->phy_drv->phyid_get)
+        return 0;
+
+    return phy_dev->phy_drv->phyid_get(phy_dev, phyid);
+}
+
+static inline int phy_dev_init(phy_dev_t *first_phy)
+{
+    int rc = 0;
+    phy_dev_t *phy_dev;
+
+    for (phy_dev = cascade_phy_get_first(first_phy); phy_dev; phy_dev = phy_dev->cascade_next)
+    {
+        phy_dev->link = 0;
+        phy_dev->speed = PHY_SPEED_UNKNOWN;
+        phy_dev->duplex = PHY_DUPLEX_UNKNOWN;
+
+        if (phy_dev->phy_drv->init != NULL)
+            rc |= phy_dev->phy_drv->init(phy_dev);
+
+        if (phy_dev->phy_drv->phy_type != PHY_TYPE_CROSSBAR)
+        {
+            if (phy_dev->phy_drv->phy_type != PHY_TYPE_SF2_SERDES &&
+                phy_dev->phy_drv->phy_type != PHY_TYPE_SF2_CL45_PHY)
+                rc |= phy_dev_apd_set(phy_dev, 1);
+
+            rc |= phy_dev_eee_set(phy_dev, 1);
+        }
+    }
+
+    return rc;
+}
+
+static inline int phy_dev_leds_init(phy_dev_t *first_phy, void *leds_info)
+{
+    int rc = 0;
+    phy_dev_t *phy_dev;
+
+    for (phy_dev = cascade_phy_get_first(first_phy); phy_dev; phy_dev = phy_dev->cascade_next)
+    {
+        if (phy_dev->phy_drv->leds_init != NULL)
+            rc |= phy_dev->phy_drv->leds_init(phy_dev, leds_info);
+    }
+
+    return rc;
+}
+
+static inline int cascade_phy_dev_isolate_phy(phy_dev_t *phy_dev, int isolate)
+{
+    if (is_cascade_phy(phy_dev))
+    {
+        int rc = 0;
+        phy_dev_t *cascade;
+        for (cascade = cascade_phy_get_first(phy_dev); cascade; cascade = cascade_phy_get_next(cascade))
+            rc |= phy_dev_isolate_phy(cascade, isolate);
+        return rc;
+    }
+    return phy_dev_isolate_phy(phy_dev, isolate);
+}
+
+static inline int cascade_phy_dev_apd_set(phy_dev_t *phy_dev, int enable)
+{
+    if (is_cascade_phy(phy_dev))
+    {
+        int rc = 0;
+        phy_dev_t *cascade;
+        for (cascade = cascade_phy_get_first(phy_dev); cascade; cascade = cascade_phy_get_next(cascade))
+            rc |= phy_dev_apd_set(cascade, enable);
+        return rc;
+    }
+    return phy_dev_apd_set(phy_dev, enable);
+}
+
+static inline int cascade_phy_dev_eee_set(phy_dev_t *phy_dev, int enable)
+{
+    if (is_cascade_phy(phy_dev))
+    {
+        int rc = 0;
+        phy_dev_t *cascade;
+        for (cascade = cascade_phy_get_first(phy_dev); cascade; cascade = cascade_phy_get_next(cascade))
+            rc |= phy_dev_eee_set(cascade, enable);
+        return rc;
+    }
+    return phy_dev_eee_set(phy_dev, enable);
+}
+
+static inline int cascade_phy_dev_eee_get(phy_dev_t *phy_dev, int *enable)
+{
+    int val;
+    if (is_cascade_phy(phy_dev))
+    {
+        int rc = 0;
+        phy_dev_t *cascade;
+        *enable = 0;
+        for (cascade = cascade_phy_get_first(phy_dev); cascade; cascade = cascade_phy_get_next(cascade))
+        {
+            rc |= phy_dev_eee_get(cascade, &val);
+            *enable |= val;
+        }
+        return rc;
+    }
+    return phy_dev_eee_get(phy_dev, enable);
+}
+
+static inline int cascade_phy_dev_eee_resolution_get(phy_dev_t *phy_dev, int *enable)
+{
+    int val;
+    if (is_cascade_phy(phy_dev))
+    {
+        int rc = 0;
+        phy_dev_t *cascade;
+        *enable = 0;
+        for (cascade = cascade_phy_get_first(phy_dev); cascade; cascade = cascade_phy_get_next(cascade))
+        {
+            rc |= phy_dev_eee_resolution_get(cascade, &val);
+            *enable |= val;
+        }
+        return rc;
+    }
+    return phy_dev_eee_resolution_get(phy_dev, enable);
+}
+
+static inline int cascade_phy_dev_speed_set(phy_dev_t *phy_dev, phy_speed_t speed, phy_duplex_t duplex)
+{
+    if (is_cascade_phy(phy_dev))
+    {
+        int rc = 0;
+        phy_dev_t *cascade;
+        for (cascade = cascade_phy_get_first(phy_dev); cascade; cascade = cascade_phy_get_next(cascade))
+        {
+            rc |= phy_dev_speed_set(cascade, speed, duplex);
+        }
+        return rc;
+    }
+    return phy_dev_speed_set(phy_dev, speed, duplex);
+}
+
+// find minimum caps
+static inline int cascade_phy_dev_caps_get(phy_dev_t *phy_dev, int caps_type, uint32_t *caps)
+{
+    int rc = 0;
+    phy_dev_t *cascade;
+    uint32_t cascade_caps;
+    uint32_t inter_phy_types, inter_phy_types_last;
+    uint32_t inter_phy_supported_speed_caps;
+
+    *caps = 0;
+    inter_phy_types = inter_phy_types_last = 0;
+    if (is_cascade_phy(phy_dev))
+    {
+        for (cascade = cascade_phy_get_first(phy_dev), *caps = 0; cascade; cascade = cascade_phy_get_next(cascade))
+        {
+            if (cascade->phy_drv->caps_get)
+            {
+                rc |= cascade->phy_drv->caps_get(cascade, caps_type, &cascade_caps);
+                if (cascade_caps)
+                {
+                    *caps = (*caps) ? ((*caps & cascade_caps) | (cascade_caps & (PHY_CAP_PAUSE|PHY_CAP_PAUSE_ASYM))) : cascade_caps;
+
+                    if (!inter_phy_types_last)
+                    {
+                        rc |= phy_dev_inter_phy_types_get(cascade, INTER_PHY_TYPE_DOWN, &inter_phy_types);
+                        inter_phy_types_last = inter_phy_types;
+                    }
+                    else
+                    {
+                        rc |= phy_dev_inter_phy_types_get(cascade, INTER_PHY_TYPE_UP, &inter_phy_types);
+                        inter_phy_types &= inter_phy_types_last;
+                    }
+
+                    rc |= get_inter_phy_supported_speed_caps(inter_phy_types, &inter_phy_supported_speed_caps);
+                    *caps = (*caps & inter_phy_supported_speed_caps) | (*caps & PHY_CAP_AUTONEG);
+                }
+            }
+        }
+        return rc;
+    }
+    return phy_dev_caps_get(phy_dev, caps_type, caps);
+}
+
+static inline int cascade_phy_dev_caps_set(phy_dev_t *phy_dev, uint32_t caps)
+{
+    if (is_cascade_phy(phy_dev))
+    {
+        int rc = 0;
+        phy_dev_t *cascade;
+        for (cascade = cascade_phy_get_first(phy_dev); cascade; cascade = cascade_phy_get_next(cascade))
+            rc |= phy_dev_caps_set(cascade, caps);
+        return rc;
+    }
+    return phy_dev_caps_set(phy_dev, caps);
+}
+
+/* Return if the phy_speed_t is covered by the PHY Speed CAP */
+static inline int phy_dev_cap_speed_match(uint32_t caps, phy_speed_t speed)
+{
+    switch (speed)
+    {
+        case PHY_SPEED_10000:
+            return ((caps & PHY_CAP_10000)>0);
+        case PHY_SPEED_5000:
+            return ((caps & PHY_CAP_5000)>0);
+        case PHY_SPEED_2500:
+            return ((caps & PHY_CAP_2500)>0);
+        case PHY_SPEED_1000:
+            return ((caps & PHY_CAP_1000_FULL)>0);
+        case PHY_SPEED_100:
+            return ((caps & PHY_CAP_100_FULL)>0);
+        case PHY_SPEED_10:
+            return ((caps & PHY_CAP_10_FULL)>0);
+        default:
+            break;
+    }
+    return 0;
+}
+
+static inline phy_speed_t cascade_phy_max_speed_get(phy_dev_t *phy_dev)
+{
+    uint32_t caps;
+
+    if (cascade_phy_dev_caps_get(phy_dev, CAPS_TYPE_SUPPORTED, &caps))
+        return 0;
+
+    return phy_caps_to_max_speed(caps);
+}
+
+static inline phy_speed_t phy_max_speed_get(phy_dev_t *phy_dev)
+{
+    uint32_t caps;
+
+    if (phy_dev_caps_get(phy_dev, CAPS_TYPE_SUPPORTED, &caps))
+        return 0;
+
+    return phy_caps_to_max_speed(caps);
+}
+
+static inline int cascade_phy_dev_power_set(phy_dev_t *phy_dev, int enable)
+{
+    // current phy_dev_power_set() already handle cascade
+    return phy_dev_power_set(phy_dev, enable);
+}
+
+/* Get last non dynamic PHY */
+static inline phy_dev_t *cascade_phy_get_last_active(phy_dev_t *phy_dev)
+{
+    phy_dev_t *phy = cascade_phy_get_last(phy_dev);
+    if (phy && (phy->flag & PHY_FLAG_DYNAMIC))
+        phy = phy->cascade_prev;
+    return phy;
+}
+
+static inline void _phy_register_polling_timer(phy_dev_t *phy, link_change_cb_t cb, int _register)
+{
+    phy_dev_t *end_phy = cascade_phy_get_last_active(phy);
+    if (_register)
+        phy_dev_link_change_register(end_phy, cb, end_phy);
+    else
+        phy_dev_link_change_unregister(end_phy);
+}
+#define phy_register_polling_timer(phy, cb) _phy_register_polling_timer(phy, cb, 1)
+#define phy_unregister_polling_timer(phy) _phy_register_polling_timer(phy, 0, 0)
+
+static inline int phy_drv_dev_add(phy_dev_t *phy_dev)
+{
+    if (phy_dev->phy_drv->initialized)
+        return 0;
+
+    if (!phy_dev->phy_drv->dev_add)
+        return 0;
+
+    return phy_dev->phy_drv->dev_add(phy_dev);
+}
+
+static inline int phy_drv_dev_del(phy_dev_t *phy_dev)
+{
+    if (phy_dev->phy_drv->initialized)
+        return 0;
+
+    if (!phy_dev->phy_drv->dev_del)
+        return 0;
+
+    return phy_dev->phy_drv->dev_del(phy_dev);
+}
+
+static inline int phy_drv_init(phy_drv_t *phy_drv)
+{
+    if (phy_drv->initialized)
+        return 0;
+
+    if (!phy_drv->drv_init)
+        return 0;
+
+    return phy_drv->drv_init(phy_drv);
+}
+
+static inline int phy_loopback_set(phy_dev_t *phy_dev, int enable, phy_speed_t speed)
+{
+    phy_drv_t *phy_drv = phy_dev->phy_drv;
+
+    if(!phy_drv->loopback_set)
+        return 0;
+    return phy_drv->loopback_set(phy_dev, enable, speed);
+}
+
+static inline int phy_loopback_get(phy_dev_t *phy_dev, int *enable, phy_speed_t *speed)
+{
+    phy_drv_t *phy_drv = phy_dev->phy_drv;
+
+    if(!phy_drv->loopback_get)
+        return 0;
+    return phy_drv->loopback_get(phy_dev, enable, speed);
+}
+
+static inline int phy_speed_2_mbps(phy_speed_t speed)
+{
+    int i;
+    int speeds[] = {PHY_SPEED_10000, 10000, PHY_SPEED_5000, 5000, PHY_SPEED_2500, 2500,
+         PHY_SPEED_1000, 1000, PHY_SPEED_100, 100, PHY_SPEED_10, 10};
+
+    for (i=0; i<sizeof(speeds)/sizeof(speeds[0]); i+=2) {
+        if ((int)speed == speeds[i])
+            return speeds[i+1];
+    }
+    return 0;
+}
+
+static inline phy_speed_t phy_mbps_2_speed(uint32_t speed_mbps)
+{
+    int i;
+    int speeds[] = {PHY_SPEED_10000, 10000, PHY_SPEED_5000, 5000, PHY_SPEED_2500, 2500,
+         PHY_SPEED_1000, 1000, PHY_SPEED_100, 100, PHY_SPEED_10, 10};
+
+    for (i=0; i<sizeof(speeds)/sizeof(speeds[0]); i+=2) {
+        if (speed_mbps ==  speeds[i+1])
+            return (phy_speed_t)speeds[i];
+    }
+    return 0;
+}
+
+static inline char *phy_get_speed_string(phy_speed_t speed)
+{
+    static char *speedStr[] = {"Auto", "10M", "100M", "1G", "2.5G", "5G", "10G"};
+    return speedStr[speed];
+}
+
+static inline int phy_dev_macsec_oper(phy_dev_t *phy_dev, void *data)
+{
+    if (!phy_dev->phy_drv->macsec_oper)
+        return 0;
+
+    return phy_dev->phy_drv->macsec_oper(phy_dev, data);
+}
+
+#endif
diff --git a/drivers/net/bcmbca/phy/phy_drv_63146_egphy.c b/drivers/net/bcmbca/phy/phy_drv_63146_egphy.c
new file mode 100644
index 0000000000..760e494813
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_63146_egphy.c
@@ -0,0 +1,791 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+	
+*/
+
+/*
+ *  Created on: Aug 2016
+ *	  Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Phy driver for 63146 and 4912 internal QGPHY and SGPHY
+ */
+
+#include "bus_drv.h"
+#include "phy_drv.h"
+#include "phy_drv_mii.h"
+#include "phy_drv_brcm.h"
+#include "access_macros.h"
+#include "dt_access.h"
+
+static uintptr_t egphy_base;
+
+static int egphy_probe(dt_device_t *pdev)
+{
+	int ret;
+
+	egphy_base = dt_dev_remap_resource(pdev, 0);
+	if (IS_ERR(egphy_base)) {
+		ret = PTR_ERR(egphy_base);
+		egphy_base = NULL;
+		dev_err(&pdev->dev, "Missing egphy_base entry\n");
+		goto Exit;
+	}
+
+	dev_dbg(&pdev->dev, "egphy_base=0x%lx\n", egphy_base);
+	dev_info(&pdev->dev, "registered\n");
+
+	return 0;
+
+Exit:
+	return ret;
+}
+
+#ifdef __UBOOT__
+static const struct udevice_id egphy_ids[] = {
+	{ .compatible = "brcm,egphy" },
+	{ /* end of list */ },
+};
+
+U_BOOT_DRIVER(brcm_egphy) = {
+	.name	= "brcm-egphy",
+	.id	= UCLASS_MISC,
+	.of_match = egphy_ids,
+	.probe = egphy_probe,
+};
+#else
+static const struct of_device_id of_platform_table[] = {
+	{ .compatible = "brcm,egphy" },
+	{ /* end of list */ },
+};
+
+static struct platform_driver of_platform_driver = {
+	.driver = {
+		.name = "brcm-egphy",
+		.of_match_table = of_platform_table,
+	},
+	.probe = egphy_probe,
+};
+module_platform_driver(of_platform_driver);
+#endif
+
+#define QGPHY_TEST_CTRL_REG	(void *)(egphy_base + 0x0004)
+#define QGPHY_CTRL_REG		(void *)(egphy_base + 0x0008)
+#define SGPHY_TEST_CTRL_REG	(void *)(egphy_base + 0x0014)
+#define SGPHY_CTRL_REG		(void *)(egphy_base + 0x0018)
+
+#define CORE_SHD1C_09		0x0019 /* LED Control */
+#define CORE_SHD1C_0D		0x001d /* LED Selector 1 */
+#define CORE_SHD1C_0E		0x001e /* LED Selector 2 */
+#define CORE_EXP04		0x0034 /* Bicollor Led Selector */
+
+#define QGPHY_ADDR	1
+#define QGPHY_MAX	4
+#define SGPHY_ADDR	5
+
+static uint32_t enabled_ports;
+
+#pragma pack(push,1)
+typedef struct {
+	uint32_t IDDQ_BIAS:1;
+	uint32_t EXT_PWR_DOWN:4;
+	uint32_t FORCE_DLL_EN:1;
+	uint32_t IDDQ_GLOBAL_PWR:4;
+	uint32_t CK25_DIS:1;
+	uint32_t PHY_RESET:1;
+	uint32_t PHY_PHYAD:5;
+	uint32_t PLL_REFCLK_SEL:2;
+	uint32_t PLL_CLK125_250_SEL:1;
+	uint32_t Reserved1:12;
+} qgphy_ctrl_t;
+
+typedef struct {
+	uint32_t IDDQ_BIAS:1;
+	uint32_t EXT_PWR_DOWN:1;
+	uint32_t FORCE_DLL_EN:1;
+	uint32_t IDDQ_GLOBAL_PWR:1;
+	uint32_t CK25_DIS:1;
+	uint32_t PHY_RESET:1;
+	uint32_t reserved0:2;
+	uint32_t PHY_PHYAD:5;
+	uint32_t PLL_REFCLK_SEL:2;
+	uint32_t PLL_CLK125_250_SEL:1;
+	uint32_t Reserved1:16;
+} sgphy_ctrl_t;
+#pragma pack(pop)
+
+
+#define PHY_ID_51F1_MASK 0x51F1
+#define PHY_ID_5321_MASK 0x5321
+#define PHY_ID_5220_MASK 0x5220
+
+#define CORE_SHD18_000		0x0028 /* Auxiliary Control Register */
+#define CORE_EXPB0		0x00b0 /* Bias Control 0 */
+#define DSP_TAP10		0x0125 /* PLL Bandwidth Control */
+#define DSP_TAP33_C2		0x0152 /* EEE LPI Timers */
+#define DSP_TAP34_C2		0x0156 /* EEE 100TX Mode BW control */
+#define DSP_FFE_ZERO_DET_CTL	0x0166 /* FFE Zero Detection Control */
+#define AFE_TX_IQ_RX_LP		0x01e4 /* AFE_TX_IQ_RX_LP */
+#define AFE_TX_CONFIG_0		0x01e5 /* AFE_TX_CONFIG_0 */
+#define AFE_TX_CONFIG_1		0x01ea /* AFE_TX_CONFIG_1 */
+#define AFE_TEMPSEN_OTHERS	0x01ec /* AFE_TEMPSEN_OTHERS */
+
+static void _phy_write_reg(phy_dev_t *phy_dev, uint32_t phy_id, uint16_t reg,
+			   uint16_t data)
+{
+	phy_dev->bus_drv->c22_write(phy_id, reg, data);
+}
+
+static void _phy_read_reg(phy_dev_t *phy_dev, uint32_t phy_id, uint16_t reg,
+			  uint16_t *data_ptr)
+{
+	phy_dev->bus_drv->c22_read(phy_id, reg, data_ptr);
+}
+
+#define EXP_REG_BASE	0x0f00
+static void _phy_write_exp_reg(phy_dev_t *phy_dev, uint32_t phy_id,
+			       uint16_t reg, uint16_t data)
+{
+	_phy_write_reg(phy_dev, phy_id, 0x17, reg | 0xf00);
+	_phy_write_reg(phy_dev, phy_id, 0x15, data);
+}
+
+static void _phy_read_exp_reg(phy_dev_t *phy_dev, uint32_t phy_id,
+			      uint16_t reg, uint16_t *data_ptr)
+{
+	_phy_write_reg(phy_dev, phy_id, 0x17, reg | 0xf00);
+	_phy_read_reg(phy_dev, phy_id, 0x15, data_ptr);
+}
+
+static void _phy_write_misc_reg(phy_dev_t *phy_dev, uint32_t phy_id,
+				uint16_t reg, uint16_t chn, uint16_t data)
+{
+	uint16_t val;
+
+	_phy_write_reg(phy_dev, phy_id, 0x18, 0x7);
+	_phy_read_reg(phy_dev, phy_id, 0x18, &val);
+	val |= 0x800;
+	_phy_write_reg(phy_dev, phy_id, 0x18, val);
+
+	val = (chn << 13) | reg;
+	_phy_write_reg(phy_dev, phy_id, 0x17, val);
+	_phy_write_reg(phy_dev, phy_id, 0x15, data);
+}
+
+static void _phy_read_misc_reg(phy_dev_t *phy_dev, uint32_t phy_id,
+			       uint16_t reg, uint16_t chn, uint16_t *data_ptr)
+{
+	uint16_t val;
+
+	_phy_write_reg(phy_dev, phy_id, 0x18, 0x7);
+	_phy_read_reg(phy_dev, phy_id, 0x18, &val);
+	val |= 0x800;
+	_phy_write_reg(phy_dev, phy_id, 0x18, val);
+
+	val = (chn << 13) | reg;
+	_phy_write_reg(phy_dev, phy_id, 0x17, val);
+	_phy_read_reg(phy_dev, phy_id, 0x15, data_ptr);
+}
+
+static void _phy_run_cal(phy_dev_t *phy_dev, uint32_t phy_id,
+			 uint16_t *rcalnewcode11_p)
+{
+	uint16_t expa9, rcalcode, rcalnewcodelp;
+
+	/* Run RCAL on AFE_CAL_CONFIG_2 = 0x3 */
+	/* enable max averaging */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x39, 0x3, 0x38);
+	/* no reset, analog powerup */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x39, 0x3, 0x3b);
+	udelay(1000);
+	/* start calibration */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x39, 0x3, 0x3f);
+	udelay(1000);
+
+	/* Run RCCAL on AFE_CAL_CONFIG_0 = 0x1 */
+	/* Vref=1000, Target=10, averaging enabled */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x39, 0x1, 0x1c82);
+	/* no reset, analog powerup */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x39, 0x1, 0x9e82);
+	udelay(1000);
+	/* start calibration */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x39, 0x1, 0x9f82);
+	udelay(1000);
+	/* clear start calibration, set HiBW */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x39, 0x1, 0x9e86);
+	udelay(1000);
+	/* start calibration with hi BW mode set */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x39, 0x1, 0x9f86);
+	udelay(1000);
+
+	/* TX Amplitude finetune */
+	/* AFE_BIAS_CONFIG_0, Adjust 10BT amplitude additional +7% and 100BT +2% */  
+	_phy_write_misc_reg(phy_dev, phy_id, 0x38, 0x1, 0xe7ea);
+	/* AFE_BIAS_CONFIG_1, Adjust 1G mode amplitude and 1G testmode1 */  
+	_phy_write_misc_reg(phy_dev, phy_id, 0x38, 0x2, 0xede0);
+
+	/* Adjust 10BT bias and RCAL settings */
+	/* read CORE_EXPA9 */
+	_phy_read_exp_reg(phy_dev, phy_id, 0xa9, &expa9);
+	/* expA9<6:1> is rcalcode<5:0> */
+	rcalcode = (expa9 & 0x007e) >> 1;
+	rcalnewcodelp = rcalcode + 16;
+	*rcalnewcode11_p = rcalcode + 10;
+	/* saturate RCAL code if necessary */
+	if (rcalnewcodelp > 0x003f) 
+		rcalnewcodelp = 0x003f; 
+	/* saturate RCAL code if necessary */
+	if (*rcalnewcode11_p > 0x003f)
+		*rcalnewcode11_p = 0x003f;
+
+	/* AFE_BIAS_CONFIG_0 */
+	/* REXT=1 BYP=1 RCAL_st1<5:0>=new rcal code */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x39, 0x3, (rcalnewcodelp << 8) + 0xf8);
+	/* AFE_BIAS_CONFIG_0 10BT bias code, bias = 0xea */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x38, 0x1, 0xe7ea);
+}
+
+static void _phy_afe_cfg(phy_dev_t *phy_dev, int phy_id, uint16_t rcalnewcode11)
+{
+	uint16_t txcfgch0, txcfg2;
+
+	/* AFE_RXCONFIG_3
+	 * invert adc clock output and 'adc refp ldo current To correct default */
+	_phy_write_misc_reg(phy_dev, phy_dev->addr, 0x003b, 0x0000, 0x8002);
+
+	/* AFE_TX_CONFIG_1
+	 * 100BT stair case, high BW, 1G stair case, alternate encode */
+	_phy_write_misc_reg(phy_dev, phy_dev->addr, 0x003c, 0x0003, 0xf882);
+
+	/* AFE_TX_CONFIG_2
+	 * 1000BT DAC transition method per Erol, bits[32],
+	 * DAC Shuffle sequence 1 + 10BT imp adjust bits */
+	_phy_write_misc_reg(phy_dev, phy_dev->addr, 0x003d, 0x0000, 0x3201);
+
+	/* AFE_RXCONFIG_1
+	 * some non-overlap fix per Erol */
+	_phy_write_misc_reg(phy_dev, phy_dev->addr, 0x003a, 0x0002, 0x0c00);
+
+	/* RX Full scale calibration */
+	/* pwdb override (rxconfig<5>) to turn on RX LDO indpendent of pwdb
+	 * controls from DSP */
+	/* AFE_RXCONFIG_0 */
+	_phy_write_misc_reg(phy_dev, phy_dev->addr, 0x003a, 0x0001, 0x0020);
+
+	/* Specify target offset for each channel */
+	/* AFE_RXCONFIG_CH0 */
+	_phy_write_misc_reg(phy_dev, phy_dev->addr, 0x003b, 0x0002, 0x0000);
+	/* AFE_RXCONFIG_CH1 */
+	_phy_write_misc_reg(phy_dev, phy_dev->addr, 0x003b, 0x0003, 0x0000);
+	/* AFE_RXCONFIG_CH2 */
+	_phy_write_misc_reg(phy_dev, phy_dev->addr, 0x003c, 0x0000, 0x0000);
+	/* AFE_RXCONFIG_CH3 */
+	_phy_write_misc_reg(phy_dev, phy_dev->addr, 0x003c, 0x0001, 0x0000);
+
+	/* Set cal_bypassb bit rxconfig<43> */
+	/* AFE_RXCONFIG_2 */
+	_phy_write_misc_reg(phy_dev, phy_dev->addr, 0x003a, 0x0003, 0x0800);
+
+	/* At least 2us delay needed  before this line is executed. */
+	udelay(1000);
+
+	/* Revert pwdb_override (rxconfig<5>) to 0 so that the RX pwr is
+	 * controlled by DSP. */
+	/* AFE_RXCONFIG_0 */
+	_phy_write_misc_reg(phy_dev, phy_dev->addr, 0x003a, 0x0001, 0x0000);
+
+	/* Adjust 10BT bias and RCAL settings */
+	/* AFE_TX_CONFIG_CH0 */
+	/* read AFE_TX_CONFIG_CH0 */
+	_phy_read_misc_reg(phy_dev, phy_id, 0x3d, 0x1, &txcfgch0);
+	/* clear bits <11:5>, set txcfg_ch0<5>=1 (enable + set local rcal) */
+	txcfgch0 = (txcfgch0 & ~(0xfe0)) | 0x0020 | (rcalnewcode11 << 5);
+	/* write AFE_TX_CONFIG_CH0 */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x3d, 0x1, txcfgch0);
+
+	/* AFE_TX_CONFIG_2 */
+	_phy_read_misc_reg(phy_dev, phy_id, 0x3d, 0x0, &txcfg2);
+	/* set txcfg<45:44>=11 (enable Rextra + invert fullscaledetect) */
+	txcfg2 = (txcfg2 & ~(0x3000)) | 0x3000;
+	_phy_write_misc_reg(phy_dev, phy_id, 0x3d, 0x0, txcfg2);
+
+	/*
+	 * Note that the following Registers are not set by default on our GPHY
+	 * DVT Boards (GPHY Standalone Mode)
+	 * AutoNeg Advert (10/100/1000BT) And Restart AutoNeg, which is required
+	 * For the GPHY Standalone Boards */
+	_phy_write_reg(phy_dev, phy_id, 0x4, 0x1e1);
+	_phy_write_reg(phy_dev, phy_id, 0x9, 0x300);
+	/* MII Control */
+	_phy_write_reg(phy_dev, phy_id, 0x0, 0x1340);
+}
+
+static int qgphy_afe_pll_done = 0;
+
+static void _xgphy_afe_pll_set(phy_dev_t *phy_dev, int phy_id)
+{
+	int i;
+	uint16_t rcalnewcode11;
+
+	if ((phy_id == QGPHY_ADDR) && qgphy_afe_pll_done)
+		return;
+
+	if (phy_id == QGPHY_ADDR) {
+		/* all phy reset */
+		for (i = QGPHY_ADDR; i <= QGPHY_MAX; i++)
+			_phy_write_reg(phy_dev, i, 0x0, 0x9140);
+	} else /* if (phy_id == SGPHY_ADDR) */
+		_phy_write_reg(phy_dev, phy_id, 0x0, 0x9140);
+	udelay(100);
+
+	/* reset AFE and PLL, then release reset*/
+	if (phy_id == QGPHY_ADDR) {
+		for (i = QGPHY_ADDR; i <= QGPHY_MAX; i++) {
+			_phy_write_exp_reg(phy_dev, i, 0x3, 0x6);
+			udelay(1000);
+			_phy_write_exp_reg(phy_dev, i, 0x3, 0x0);
+		}
+	} else { /* if (phy_id == SGPHY_ADDR) */
+		_phy_write_exp_reg(phy_dev, phy_id, 0x3, 0x6);
+		udelay(1000);
+		_phy_write_exp_reg(phy_dev, phy_id, 0x3, 0x0);
+	}
+
+	/* config PLL AFE control registers */
+	/* reset PLL */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x30, 0x1, 0x0);
+	/* ndiv_intger */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x31, 0x0, 0x50);
+	/* pdiv=0; auto-configured */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x33, 0x2, 0x1);
+	/* ndiv_fraction */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x31, 0x1, 0x0);
+	/* freequency nudge factor */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x31, 0x2, 0x0);
+	/* reference frequency, mode 0 */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x30, 0x3, 0x32);
+	/* init bypass mode - default setting */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x32, 0x3, 0x0);
+	/* bypass code - default, vcoclk enabled */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x33, 0x0, 0x2);
+	/* LDOs at default settings */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x30, 0x2, 0x1c0);
+	/* release PLL reset */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x30, 0x1, 0x1);
+
+	/* AFE_BG_CONFIG */
+	_phy_write_misc_reg(phy_dev, phy_id, 0x38, 0x0, 0x10);
+
+	/* RCAL and RCCAL */
+	_phy_run_cal(phy_dev, phy_id, &rcalnewcode11);
+
+	if (phy_id == QGPHY_ADDR) {
+		for (i = QGPHY_ADDR; i <= QGPHY_MAX; i++)
+			_phy_afe_cfg(phy_dev, i, rcalnewcode11);
+	} else /* if (phy_id == SGPHY_ADDR) */
+		_phy_afe_cfg(phy_dev, phy_id, rcalnewcode11);
+
+	if (phy_id == QGPHY_ADDR)
+		qgphy_afe_pll_done = 1;
+}
+
+static int _phy_init(phy_dev_t *phy_dev)
+{
+	int ret = 0;
+
+	if ((phy_dev->addr >= QGPHY_ADDR) &&
+	    (phy_dev->addr <= QGPHY_MAX))
+		_xgphy_afe_pll_set(phy_dev, QGPHY_ADDR);
+
+#ifdef PHY_63146_EGPHY_WITH_SGPHY
+	if (phy_dev->addr == SGPHY_ADDR)
+		_xgphy_afe_pll_set(phy_dev, SGPHY_ADDR);
+#endif
+
+#if 0
+	/* TODO! check if mii_init is needed */
+	if ((ret = mii_init(phy_dev)))
+		goto Exit;
+
+	if ((ret = brcm_egphy_force_auto_mdix_set(phy_dev, 1)))
+		goto Exit;
+
+	if ((ret = brcm_egphy_eth_wirespeed_set(phy_dev, 1)))
+		goto Exit;
+#endif
+
+Exit:
+	return ret;
+}
+
+#ifdef PHY_63146_EGPHY_WITH_SGPHY
+static int _sgphy_cfg(void)
+{
+	sgphy_ctrl_t sgphy_ctrl;
+	uint32_t val;
+
+	/* Assert reset_n (active low) */
+	READ_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	sgphy_ctrl.PHY_RESET = 1;
+	WRITE_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	udelay(1000);
+
+	val = 0;
+	WRITE_32(SGPHY_TEST_CTRL_REG, val);
+
+	/* Deassert iddq_global_pwr and iddq_bias */
+	READ_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	sgphy_ctrl.IDDQ_BIAS = 0;
+	sgphy_ctrl.IDDQ_GLOBAL_PWR = 0;
+	WRITE_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	udelay(1000);
+
+	/* assert iddq_global_pwr and iddq_bias */
+	READ_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	sgphy_ctrl.IDDQ_BIAS = 1;
+	sgphy_ctrl.IDDQ_GLOBAL_PWR = 1;
+	WRITE_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	udelay(1000);
+
+	/* Deassert reset_n */
+	READ_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	sgphy_ctrl.PHY_RESET = 0;
+	WRITE_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	udelay(1000);
+
+	/* end workaround */
+	val = 0;
+	WRITE_32(SGPHY_TEST_CTRL_REG, val);
+
+	/* real power up */
+	/* Deassert ext_pwr_down and iddq_bias */
+	/* Assert reset_n (active low) */
+	READ_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	sgphy_ctrl.IDDQ_BIAS = 0;
+	sgphy_ctrl.EXT_PWR_DOWN = 0;
+	sgphy_ctrl.PHY_RESET = 1;
+	WRITE_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	udelay(10);
+
+	/* Deassert iddq_global_pwr */
+	sgphy_ctrl.IDDQ_GLOBAL_PWR = 0;
+	WRITE_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	udelay(1000);
+
+	/* Deassert reset_n */
+	READ_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	sgphy_ctrl.PHY_RESET = 0;
+	WRITE_32(SGPHY_CTRL_REG, sgphy_ctrl);
+	udelay(1000);
+
+	return 0;
+}
+#endif
+
+static int _qgphy_cfg(uint32_t port_map)
+{
+	qgphy_ctrl_t qgphy_ctrl;
+	uint32_t val;
+
+	/* Assert reset_n (active low) */
+	READ_32(QGPHY_CTRL_REG, qgphy_ctrl);
+	qgphy_ctrl.PHY_RESET = 1;
+	WRITE_32(QGPHY_CTRL_REG, qgphy_ctrl);
+	udelay(1000);
+
+	val = 1;
+	WRITE_32(QGPHY_TEST_CTRL_REG, val);
+
+	/* Deassert iddq_global_pwr and iddq_bias */
+	READ_32(QGPHY_CTRL_REG, qgphy_ctrl);
+	qgphy_ctrl.IDDQ_GLOBAL_PWR = 0;
+	qgphy_ctrl.IDDQ_BIAS = 0;
+	WRITE_32(QGPHY_CTRL_REG, qgphy_ctrl);
+	udelay(1000);
+
+	/* assert iddq_global_pwr and iddq_bias */
+	READ_32(QGPHY_CTRL_REG, qgphy_ctrl);
+	qgphy_ctrl.IDDQ_GLOBAL_PWR = 0xf;
+	qgphy_ctrl.IDDQ_BIAS = 1;
+	WRITE_32(QGPHY_CTRL_REG, qgphy_ctrl);
+	udelay(1000);
+
+	/* Deassert reset_n */
+	READ_32(QGPHY_CTRL_REG, qgphy_ctrl);
+	qgphy_ctrl.PHY_RESET = 0;
+	WRITE_32(QGPHY_CTRL_REG, qgphy_ctrl);
+	udelay(1000);
+
+	/* end workaround */
+	val = 0;
+	WRITE_32(QGPHY_TEST_CTRL_REG, val);
+
+	/* real power up */
+	qgphy_ctrl.IDDQ_BIAS = 0;
+	qgphy_ctrl.EXT_PWR_DOWN = ~port_map;
+	qgphy_ctrl.IDDQ_GLOBAL_PWR = 0;
+	qgphy_ctrl.PHY_RESET = 1;
+	WRITE_32(QGPHY_CTRL_REG, qgphy_ctrl);
+	udelay(1000);
+
+	/* Deassert reset_n */
+	READ_32(QGPHY_CTRL_REG, qgphy_ctrl);
+	qgphy_ctrl.PHY_RESET = 0;
+	WRITE_32(QGPHY_CTRL_REG, qgphy_ctrl);
+	udelay(1000);
+
+	return 0;
+}
+
+static int _phy_cfg(uint32_t port_map)
+{
+	if (port_map & 0xf)
+		_qgphy_cfg(port_map & 0xf);
+
+#ifdef PHY_63146_EGPHY_WITH_SGPHY
+	if (port_map & 0x10)
+		_sgphy_cfg();
+#endif
+
+	return 0;
+}
+
+static int _phy_dev_add(phy_dev_t *phy_dev)
+{
+	uint32_t port = (unsigned long)phy_dev->priv;
+
+	enabled_ports |= (1 << port);
+
+	return 0;
+}
+
+static int _phy_dev_del(phy_dev_t *phy_dev)
+{
+	uint32_t port = (unsigned long)phy_dev->priv;
+
+	enabled_ports &= ~(1 << port);
+
+	return 0;
+}
+
+static int _phy_drv_init(phy_drv_t *phy_drv)
+{
+	if (_phy_cfg(enabled_ports & 0x1f))
+	{
+		printk("Failed to initialize the egphy driver\n");
+		return -1;
+	}
+
+	udelay(2000);
+	phy_drv->initialized = 1;
+
+	return 0;
+}
+
+static int _phy_drv_dt_priv(const dt_handle_t handle, uint32_t addr, uint32_t phy_mode, void **_priv)
+{
+	*_priv = (void*)(unsigned long)addr - QGPHY_ADDR;
+
+	return 0;
+}
+
+#include "bcm_bca_leds_dt_bindings.h"
+#include "bcm_bca_leds.h"
+
+#define MAX_LEDS_PER_PORT 2
+
+static int _phy_leds_init_51XX(phy_dev_t *phy_dev, void *_leds_info, uint8_t is_shifted)
+{
+	bca_leds_info_t *leds_info = (bca_leds_info_t *)_leds_info;
+	int ret = 0;
+	int j;
+	uint16_t led_shd1c_09 = 0;
+	uint16_t led_core_exp_04 = 0;
+	uint16_t led_shd1c_0d = 0, led_shd1c_0e = 0;
+
+	for (j = 0; j < MAX_LEDS_PER_PORT; j++)
+	{
+		uint32_t led_mux = leds_info->link[j];
+		uint32_t led_activity = leds_info->activity[j];
+		uint32_t val = 0;
+
+		if (led_mux == led_activity)
+		{
+			if (led_mux == LED_SPEED_ALL || led_mux == LED_SPEED_GBE)
+			{
+				val = 0x18;
+			}
+			else if (led_mux == (LED_SPEED_1G | LED_SPEED_100))
+			{
+				val = 0x108;
+			}
+			else if (led_mux == (LED_SPEED_1G | LED_SPEED_10))
+			{
+				val = 0x108;
+			}
+			else if (led_mux == LED_SPEED_1G)
+			{
+				val = 0x118;
+			}
+			else if (led_mux == LED_SPEED_100)
+			{
+				val = 0x118;
+			}
+			else if (led_mux == LED_SPEED_10)
+			{
+				val = 0x118;
+			}
+			else if (led_mux == (LED_SPEED_100 | LED_SPEED_10))
+			{
+				val = 0x118;
+			}
+
+			if( val > led_shd1c_09)
+				led_shd1c_09 = val;
+		}
+	}
+
+	for (j = 0; j < MAX_LEDS_PER_PORT; j++)
+	{
+		uint16_t led_sel = 0;
+		uint32_t led_mux = leds_info->link[j];
+		uint32_t led_activity = leds_info->activity[j];
+		uint16_t val, val2;
+
+		if (led_mux == led_activity)
+		{
+			if (led_mux == LED_SPEED_ALL || led_mux == LED_SPEED_GBE)
+			{
+				val = 0x3;
+				if (led_shd1c_09 == 0x118)
+				{
+					val = 0xa;
+					led_core_exp_04 |= 0x500;
+				}
+			}
+			else if (led_mux == (LED_SPEED_1G | LED_SPEED_100))
+			{
+				val = 0x1;
+			}
+			else if (led_mux == (LED_SPEED_1G | LED_SPEED_10))
+			{
+				val = 0x0;
+			}
+			else if (led_mux == LED_SPEED_1G)
+			{
+				val = 0x3;
+			}
+			else if (led_mux == LED_SPEED_100)
+			{
+				val = 0x1;
+			}
+			else if (led_mux == LED_SPEED_10)
+			{
+				val = 0x0;
+			}
+			else if (led_mux == (LED_SPEED_100 | LED_SPEED_10))
+			{
+				val = 0xa;
+				led_core_exp_04 |= 0x504;
+			}
+			else 
+			{
+				val = 0xe;
+			}
+		}
+		else
+		{
+			if (led_mux == LED_SPEED_ALL || led_mux == LED_SPEED_GBE)
+			{
+				val = 0xa;
+				val2 = 0x2;
+			}
+			else if (led_activity == LED_SPEED_ALL || led_activity == LED_SPEED_GBE)
+			{
+				val = 0xa;
+				val2 = 0x8;
+			}
+			else 
+			{
+				val=0xe;
+				val2 = 0x0;
+			}
+			led_core_exp_04 |= (0x100 | val2<<(4*(j%2)));
+		}
+ 
+		
+		led_sel = (val<<(4*((j+is_shifted)%2)));
+
+		if (j < (2 - is_shifted))
+			led_shd1c_0d |= led_sel;
+		else
+			led_shd1c_0e |= led_sel;
+	}
+
+	ret = ret ? ret : phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD1C_0D, led_shd1c_0d);
+	ret = ret ? ret : phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD1C_0E, led_shd1c_0e);
+	if (led_shd1c_09 && !ret)
+		ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD1C_09, led_shd1c_09);
+	if (led_core_exp_04 && !ret)
+		ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_EXP04, led_core_exp_04);
+
+	printk("CORE_SHD1C_09: 0x%x CORE_SHD1C_0D: 0x%x CORE_SHD1C_0E: 0x%x CORE_EXP04: 0x%x\n", 
+		led_shd1c_09, led_shd1c_0d, led_shd1c_0e, led_core_exp_04);
+
+Exit:
+	return ret;
+}
+
+static int _phy_leds_init_xrdp(phy_dev_t *phy_dev, void *leds_info)
+{
+	return ephy_leds_init(leds_info);
+}
+
+static int _phy_leds_init(phy_dev_t *phy_dev, void *leds_info)
+{
+	uint32_t phyid = 0;	
+	
+	mii_phyid_get(phy_dev, &phyid);
+
+
+	if ((phyid & PHY_ID_5321_MASK) == PHY_ID_5321_MASK || (phyid & PHY_ID_5220_MASK) == PHY_ID_5220_MASK)
+		return _phy_leds_init_xrdp(phy_dev, leds_info);
+	else if ((phyid & PHY_ID_51F1_MASK) == PHY_ID_51F1_MASK)
+		return _phy_leds_init_51XX(phy_dev, leds_info, 1);
+	else
+		return _phy_leds_init_51XX(phy_dev, leds_info, 0);
+}
+
+phy_drv_t phy_drv_63146_egphy =
+{
+	.phy_type = PHY_TYPE_63146_EGPHY,
+	.name = "EGPHY",
+	.read = brcm_egphy_read,
+	.write = brcm_egphy_write,
+	.power_get = mii_power_get,
+	.power_set = mii_power_set,
+	.apd_get = brcm_egphy_apd_get,
+	.apd_set = brcm_egphy_apd_set,
+	.eee_get = brcm_egphy_eee_get,
+	.eee_set = brcm_egphy_eee_set,
+	.eee_resolution_get = brcm_egphy_eee_resolution_get,
+	.read_status = brcm_read_status,
+	.speed_set = mii_speed_set,
+	.caps_get = mii_caps_get,
+	.caps_set = mii_caps_set,
+	.phyid_get = mii_phyid_get,
+	.auto_mdix_set = brcm_egphy_force_auto_mdix_set,
+	.auto_mdix_get = brcm_egphy_force_auto_mdix_get,
+	.init = _phy_init,
+	.dev_add = _phy_dev_add,
+	.dev_del = _phy_dev_del,
+	.drv_init = _phy_drv_init,
+	.dt_priv = _phy_drv_dt_priv,
+	.leds_init = _phy_leds_init,
+	.cable_diag_run = brcm_cable_diag_run,
+};
+
diff --git a/drivers/net/bcmbca/phy/phy_drv_6846_egphy.c b/drivers/net/bcmbca/phy/phy_drv_6846_egphy.c
new file mode 100644
index 0000000000..c0c95eeebc
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_6846_egphy.c
@@ -0,0 +1,510 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Aug 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Phy driver for 6846, 6856 internal quad 1G phy
+ */
+
+#include "bus_drv.h"
+#include "phy_drv.h"
+#include "phy_drv_mii.h"
+#include "phy_drv_brcm.h"
+#include "access_macros.h"
+#include "xrdp_led_init.h"
+#include "dt_access.h"
+
+static uintptr_t qegphy_base;
+static uint16_t base_addr = 1;
+
+static int egphy_probe(dt_device_t *pdev)
+{
+    int ret;
+    dt_handle_t node = dt_dev_get_handle(pdev);
+
+    qegphy_base = dt_dev_remap_resource(pdev, 0);
+    if (IS_ERR(qegphy_base))
+    {
+        ret = PTR_ERR(qegphy_base);
+        qegphy_base = NULL;
+        dev_err(&pdev->dev, "Missing qegphy_base entry\n");
+        goto Exit;
+    }
+
+    base_addr = dt_property_read_u32_default(node, "base-addr", base_addr);
+
+    dev_dbg(&pdev->dev, "qegphy_base=0x%lx\n", qegphy_base);
+    dev_dbg(&pdev->dev, "base_addr=%d\n", base_addr);
+    dev_info(&pdev->dev, "registered\n");
+
+    return 0;
+
+Exit:
+    return ret;
+}
+
+#ifdef __UBOOT__
+static const struct udevice_id egphy_ids[] = {
+    { .compatible = "brcm,egphy" },
+    { /* end of list */ },
+};
+
+U_BOOT_DRIVER(brcm_egphy) = {
+    .name	= "brcm-egphy",
+    .id	= UCLASS_MISC,
+    .of_match = egphy_ids,
+    .probe = egphy_probe,
+};
+#else
+static const struct of_device_id of_platform_table[] = {
+    { .compatible = "brcm,egphy" },
+    { /* end of list */ },
+};
+
+static struct platform_driver of_platform_driver = {
+    .driver = {
+        .name = "brcm-egphy",
+        .of_match_table = of_platform_table,
+    },
+    .probe = egphy_probe,
+};
+module_platform_driver(of_platform_driver);
+#endif
+
+#define QEGPHY_BASE             (void *)qegphy_base
+#define QEGPHY_CTRL_REG         QEGPHY_BASE + 0x0008
+
+#define CORE_SHD1C_09			0x0019 /* LED Control */
+#define CORE_SHD1C_0D			0x001d /* LED Selector 1 */
+#define CORE_SHD1C_0E			0x001e /* LED Selector 2 */
+#define CORE_EXP04              0x0034 /* Bicollor Led Selector */
+
+static uint32_t enabled_addrs = 0;
+
+#pragma pack(push,1)
+typedef struct
+{
+    uint32_t IDDQ_BIAS:1;
+    uint32_t EXT_PWR_DOWN:4;
+    uint32_t FORCE_DLL_EN:1;
+    uint32_t IDDQ_GLOBAL_PWR:1;
+    uint32_t CK25_DIS:1;
+    uint32_t PHY_RESET:1;
+    uint32_t Reserved0:3;
+    uint32_t PHY_PHYAD:5;
+    uint32_t PLL_REFCLK_SEL:2;
+    uint32_t PLL_SEL_DIV5:2;
+    uint32_t PLL_CLK125_250_SEL:1;
+    uint32_t Reserved1:10;
+} qegphy_ctrl_t;
+#pragma pack(pop)
+
+
+#define PHY_ID_51F1_MASK 0x51F1
+#define PHY_ID_5321_MASK 0x5321
+
+#define CORE_SHD18_000          0x0028 /* Auxiliary Control Register */
+#define CORE_EXPB0              0x00b0 /* Bias Control 0 */
+#define DSP_TAP10               0x0125 /* PLL Bandwidth Control */
+#define DSP_TAP33_C2            0x0152 /* EEE LPI Timers */
+#define DSP_TAP34_C2            0x0156 /* EEE 100TX Mode BW control */
+#define DSP_FFE_ZERO_DET_CTL    0x0166 /* FFE Zero Detection Control */
+#define AFE_TX_IQ_RX_LP         0x01e4 /* AFE_TX_IQ_RX_LP */
+#define AFE_TX_CONFIG_0         0x01e5 /* AFE_TX_CONFIG_0 */
+#define AFE_TX_CONFIG_1         0x01ea /* AFE_TX_CONFIG_1 */
+#define AFE_TEMPSEN_OTHERS      0x01ec /* AFE_TEMPSEN_OTHERS */
+
+static int _phy_afe(phy_dev_t *phy_dev)
+{
+    int ret;
+
+    /* Enable the DSP clock */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD18_000, 0x0c30)))
+        goto Exit;
+
+    /* Turn off AOF */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | AFE_TX_CONFIG_0, 0x0000)))
+        goto Exit;
+
+    /* 1g AB symmetry Iq */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | AFE_TX_CONFIG_1, 0x0bcc)))
+        goto Exit;
+
+    /* LPF BW */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | AFE_TX_IQ_RX_LP, 0x233f)))
+        goto Exit;
+
+    /* RCAL +6LSB to make impedance from 112 to 100ohm */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | AFE_TEMPSEN_OTHERS, 0xad40)))
+        goto Exit;
+
+    /* since rcal make R smaller, make master current -4% */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | DSP_TAP10, 0x091b)))
+        goto Exit;
+
+    /* rx_on_tune 8 -> 0xf */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | DSP_TAP33_C2, 0x87f6)))
+        goto Exit;
+
+    /* From EEE excel config file for Vitesse fix */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | DSP_TAP34_C2, 0x017d)))
+        goto Exit;
+
+    /* Enable ffe zero det for Vitesse interop */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | DSP_FFE_ZERO_DET_CTL, 0x0015)))
+        goto Exit;
+
+    /* Reset R_CAL/RC_CAL Engine */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_EXPB0, 0x0010)))
+        goto Exit;
+
+    /* Disable Reset R_CAL/RC_CAL Engine */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_EXPB0, 0x0000)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_init(phy_dev_t *phy_dev)
+{
+    int ret;
+
+    if ((ret = mii_init(phy_dev)))
+        goto Exit;
+
+    /* AFE workaround */
+    if ((ret = _phy_afe(phy_dev)))
+        goto Exit;
+    
+    if ((ret = brcm_egphy_force_auto_mdix_set(phy_dev, 1)))
+        goto Exit;
+
+    if ((ret = brcm_egphy_eth_wirespeed_set(phy_dev, 1)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_cfg(uint32_t port_map)
+{
+    qegphy_ctrl_t qegphy_ctrl;
+
+    READ_32(QEGPHY_CTRL_REG, qegphy_ctrl);
+
+    /* Assert reset_n (active low) */
+    qegphy_ctrl.PHY_RESET = 1;
+    WRITE_32(QEGPHY_CTRL_REG, qegphy_ctrl);
+    udelay(1000);
+
+    /* Set GPHY's pll_clk125_250_sel to 250MHz */
+    qegphy_ctrl.PLL_CLK125_250_SEL = 1;
+    WRITE_32(QEGPHY_CTRL_REG, qegphy_ctrl);
+    udelay(1000);
+
+    /* Deassert iddq_global_pwr and iddq_bias */
+    qegphy_ctrl.IDDQ_GLOBAL_PWR = 0;
+    qegphy_ctrl.IDDQ_BIAS = 0;
+    WRITE_32(QEGPHY_CTRL_REG, qegphy_ctrl);
+    udelay(1000);
+
+    if (!port_map)
+    {
+        /* Assert iddq_global_pwr and iddq_bias */
+        qegphy_ctrl.IDDQ_GLOBAL_PWR = 1;
+        qegphy_ctrl.IDDQ_BIAS = 1;
+        WRITE_32(QEGPHY_CTRL_REG, qegphy_ctrl);
+        udelay(1000);
+
+        /* Deassert reset_n */
+        qegphy_ctrl.PHY_RESET = 0;
+        WRITE_32(QEGPHY_CTRL_REG, qegphy_ctrl);
+        udelay(1000);
+
+       /* Set GPHY's pll_clk125_250_sel to 125MHz */
+        qegphy_ctrl.PLL_CLK125_250_SEL = 0;
+        WRITE_32(QEGPHY_CTRL_REG, qegphy_ctrl);
+        udelay(1000);
+
+        /* Assert reset_n (active low) */
+        qegphy_ctrl.PHY_RESET = 1;
+        WRITE_32(QEGPHY_CTRL_REG, qegphy_ctrl);
+        udelay(1000);
+
+        return 0;
+    }
+
+    /* Set QGPHY base address */
+    qegphy_ctrl.PHY_PHYAD = base_addr;
+
+    /* Power only enabled ports */
+    qegphy_ctrl.EXT_PWR_DOWN = ~port_map;
+    WRITE_32(QEGPHY_CTRL_REG, qegphy_ctrl);
+    udelay(1000);
+
+    /* Set GPHY's pll_clk125_250_sel to 125MHz */
+    qegphy_ctrl.PLL_CLK125_250_SEL = 0;
+    WRITE_32(QEGPHY_CTRL_REG, qegphy_ctrl);
+
+    /* Deassert reset_n */
+    qegphy_ctrl.PHY_RESET = 0;
+    WRITE_32(QEGPHY_CTRL_REG, qegphy_ctrl);
+    udelay(1000);
+
+    return 0;
+}
+
+extern phy_drv_t phy_drv_6846_egphy;
+
+static int _phy_afe_all(void)
+{
+    int i, ret = 0;
+    phy_dev_t phy_dev = {};
+    phy_dev.phy_drv = &phy_drv_6846_egphy;
+
+    for (i = 0; i < 4; i++)
+    {
+        phy_dev.addr = base_addr + i;
+        ret |= _phy_afe(&phy_dev);
+    }
+
+    return ret;
+}
+
+static int _phy_dev_add(phy_dev_t *phy_dev)
+{
+    enabled_addrs |= (1 << phy_dev->addr);
+
+    return 0;
+}
+
+static int _phy_dev_del(phy_dev_t *phy_dev)
+{
+    enabled_addrs &= ~(1 << phy_dev->addr);
+
+    return 0;
+}
+
+static int _phy_drv_init(phy_drv_t *phy_drv)
+{
+    if (_phy_cfg((enabled_addrs >> base_addr) & 0xf))
+    {
+        printk("Failed to initialize the egphy driver\n");
+        return -1;
+    }
+
+    if (_phy_afe_all())
+    {
+        printk("Failed to initialize the phy AFE settings\n");
+        return -1;
+    }
+
+    phy_drv->initialized = 1;
+
+    return 0;
+}
+
+#include "bcm_bca_leds_dt_bindings.h"
+#include "bcm_bca_leds.h"
+
+#define MAX_LEDS_PER_PORT 2
+
+static int _phy_leds_init_51XX(phy_dev_t *phy_dev, void *_leds_info, uint8_t is_shifted)
+{
+    bca_leds_info_t *leds_info = (bca_leds_info_t *)_leds_info;
+    int ret = 0;
+    int j;
+    uint16_t led_shd1c_09 = 0;
+    uint16_t led_core_exp_04 = 0;
+    uint16_t led_shd1c_0d = 0, led_shd1c_0e = 0;
+
+    for (j = 0; j < MAX_LEDS_PER_PORT; j++)
+    {
+        uint32_t led_mux = leds_info->link[j];
+        uint32_t led_activity = leds_info->activity[j];
+        uint32_t val = 0;
+
+        if (led_mux == led_activity)
+        {
+            if (led_mux == LED_SPEED_ALL || led_mux == LED_SPEED_GBE)
+            {
+                val = 0x18;
+            }
+            else if (led_mux == (LED_SPEED_1G | LED_SPEED_100))
+            {
+                val = 0x108;
+            }
+            else if (led_mux == (LED_SPEED_1G | LED_SPEED_10))
+            {
+                val = 0x108;
+            }
+            else if (led_mux == LED_SPEED_1G)
+            {
+                val = 0x118;
+            }
+            else if (led_mux == LED_SPEED_100)
+            {
+                val = 0x118;
+            }
+            else if (led_mux == LED_SPEED_10)
+            {
+                val = 0x118;
+            }
+            else if (led_mux == (LED_SPEED_100 | LED_SPEED_10))
+            {
+                val = 0x118;
+            }
+
+            if( val > led_shd1c_09)
+                led_shd1c_09 = val;
+        }
+    }
+
+    for (j = 0; j < MAX_LEDS_PER_PORT; j++)
+    {
+        uint16_t led_sel = 0;
+        uint32_t led_mux = leds_info->link[j];
+        uint32_t led_activity = leds_info->activity[j];
+        uint16_t val, val2;
+
+        if (led_mux == led_activity)
+        {
+            if (led_mux == LED_SPEED_ALL || led_mux == LED_SPEED_GBE)
+            {
+                val = 0x3;
+                if (led_shd1c_09 == 0x118)
+                {
+                    val = 0xa;
+                    led_core_exp_04 |= 0x500;
+                }
+            }
+            else if (led_mux == (LED_SPEED_1G | LED_SPEED_100))
+            {
+                val = 0x1;
+            }
+            else if (led_mux == (LED_SPEED_1G | LED_SPEED_10))
+            {
+                val = 0x0;
+            }
+            else if (led_mux == LED_SPEED_1G)
+            {
+                val = 0x3;
+            }
+            else if (led_mux == LED_SPEED_100)
+            {
+                val = 0x1;
+            }
+            else if (led_mux == LED_SPEED_10)
+            {
+                val = 0x0;
+            }
+            else if (led_mux == (LED_SPEED_100 | LED_SPEED_10))
+            {
+                val = 0xa;
+                led_core_exp_04 |= 0x504;
+            }
+            else 
+            {
+                val = 0xe;
+            }
+        }
+        else
+        {
+            if (led_mux == LED_SPEED_ALL || led_mux == LED_SPEED_GBE)
+            {
+                val = 0xa;
+                val2 = 0x2;
+            }
+            else if (led_activity == LED_SPEED_ALL || led_activity == LED_SPEED_GBE)
+            {
+                val = 0xa;
+                val2 = 0x8;
+            }
+            else 
+            {
+                val=0xe;
+                val2 = 0x0;
+            }
+            led_core_exp_04 |= (0x100 | val2<<(4*(j%2)));
+        }
+ 
+        
+        led_sel = (val<<(4*((j+is_shifted)%2)));
+
+        if (j < (2 - is_shifted))
+            led_shd1c_0d |= led_sel;
+        else
+            led_shd1c_0e |= led_sel;
+    }
+
+    ret = ret ? ret : phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD1C_0D, led_shd1c_0d);
+    ret = ret ? ret : phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD1C_0E, led_shd1c_0e);
+    if (led_shd1c_09 && !ret)
+        ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD1C_09, led_shd1c_09);
+    if (led_core_exp_04 && !ret)
+        ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_EXP04, led_core_exp_04);
+
+    printk("CORE_SHD1C_09: 0x%x CORE_SHD1C_0D: 0x%x CORE_SHD1C_0E: 0x%x CORE_EXP04: 0x%x\n", 
+        led_shd1c_09, led_shd1c_0d, led_shd1c_0e, led_core_exp_04);
+
+    return ret;
+}
+
+static int _phy_leds_init_xrdp(phy_dev_t *phy_dev, void *leds_info)
+{
+    return xrdp_leds_init(leds_info);
+}
+
+static int _phy_leds_init(phy_dev_t *phy_dev, void *leds_info)
+{
+    uint32_t phyid = 0;    
+    
+    mii_phyid_get(phy_dev, &phyid);
+
+    if ((phyid & PHY_ID_5321_MASK) == PHY_ID_5321_MASK)
+        return _phy_leds_init_xrdp(phy_dev, leds_info);
+    else if ((phyid & PHY_ID_51F1_MASK) == PHY_ID_51F1_MASK)
+        return _phy_leds_init_51XX(phy_dev, leds_info, 1);
+    else
+        return _phy_leds_init_51XX(phy_dev, leds_info, 0);
+}
+
+phy_drv_t phy_drv_6846_egphy =
+{
+    .phy_type = PHY_TYPE_6846_EGPHY,
+    .name = "EGPHY",
+    .read = brcm_egphy_read,
+    .write = brcm_egphy_write,
+    .power_get = mii_power_get,
+    .power_set = mii_power_set,
+    .apd_get = brcm_egphy_apd_get,
+    .apd_set = brcm_egphy_apd_set,
+    .eee_get = brcm_egphy_eee_get,
+    .eee_set = brcm_egphy_eee_set,
+    .eee_resolution_get = brcm_egphy_eee_resolution_get,
+    .read_status = brcm_read_status,
+    .speed_set = mii_speed_set,
+    .caps_get = mii_caps_get,
+    .caps_set = mii_caps_set,
+    .phyid_get = mii_phyid_get,
+    .auto_mdix_set = brcm_egphy_force_auto_mdix_set,
+    .auto_mdix_get = brcm_egphy_force_auto_mdix_get,
+    .wirespeed_set = brcm_egphy_eth_wirespeed_set,
+    .wirespeed_get = brcm_egphy_eth_wirespeed_get,
+    .init = _phy_init,
+    .dev_add = _phy_dev_add,
+    .dev_del = _phy_dev_del,
+    .drv_init = _phy_drv_init,
+    .leds_init = _phy_leds_init,
+    .cable_diag_run = brcm_cable_diag_run,
+};
diff --git a/drivers/net/bcmbca/phy/phy_drv_6856_sgmii.c b/drivers/net/bcmbca/phy/phy_drv_6856_sgmii.c
new file mode 100644
index 0000000000..06dc165a02
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_6856_sgmii.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Aug 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Phy driver for 6856 SGMII/HSGMII
+ */
+
+#include "bus_drv.h"
+#include "phy_drv.h"
+#include "phy_drv_mii.h"
+#include "phy_drv_sgmii_plus2.h"
+#include "access_macros.h"
+#include "dt_access.h"
+
+#include "asm/arch/pmc_addr.h"
+
+static uintptr_t sgmii_base;
+
+static int sgmii_probe(dt_device_t *pdev)
+{
+    int ret;
+
+    sgmii_base = dt_dev_remap_resource(pdev, 0);
+    if (IS_ERR(sgmii_base))
+    {
+        ret = PTR_ERR(sgmii_base);
+        sgmii_base = NULL;
+        dev_err(&pdev->dev, "Missing sgmii_base entry\n");
+        goto Exit;
+    }
+
+    dev_dbg(&pdev->dev, "sgmii_base=0x%lx\n", sgmii_base);
+    dev_info(&pdev->dev, "registered\n");
+
+    return 0;
+
+Exit:
+    return ret;
+}
+
+#ifdef __UBOOT__
+static const struct udevice_id sgmii_ids[] = {
+    { .compatible = "brcm,sgmii" },
+    { /* end of list */ },
+};
+
+U_BOOT_DRIVER(brcm_sgmii) = {
+    .name	= "brcm-sgmii",
+    .id	= UCLASS_MISC,
+    .of_match = sgmii_ids,
+    .probe = sgmii_probe,
+};
+#else
+static const struct of_device_id of_platform_table[] = {
+    { .compatible = "brcm,sgmii" },
+    { /* end of list */ },
+};
+
+static struct platform_driver of_platform_driver = {
+    .driver = {
+        .name = "brcm-sgmii",
+        .of_match_table = of_platform_table,
+    },
+    .probe = sgmii_probe,
+};
+module_platform_driver(of_platform_driver);
+#endif
+
+#define SGMII_BASE      (void *)sgmii_base
+
+#define SGMII_CTRL      SGMII_BASE + 0x0004
+#define SGMII_STAT      SGMII_BASE + 0x0008
+
+int ReadBPCMRegister(int devAddr, int wordOffset, uint32_t * value);
+int WriteBPCMRegister(int devAddr, int wordOffset, uint32_t value);
+
+static uint32_t phy_addr;
+
+#pragma pack(push,1)
+typedef struct
+{
+    uint32_t IDDQ:1;
+    uint32_t PWRDWN:1;
+    uint32_t Reserved0:1;
+    uint32_t RESET_PLL:1;
+    uint32_t RESET_MDIOREGS:1;
+    uint32_t SERDES_RESET:1;
+    uint32_t Reserved1:2;
+    uint32_t SERDES_PRTAD:5;
+    uint32_t SERDES_DEVAD:5;
+    uint32_t MDIO_ST:1;
+    uint32_t SERDES_TEST_EN:1;
+    uint32_t LINK_DOWN_TX_DIS:1;
+    uint32_t SERDES_PRTAD_BCST:5;
+    uint32_t Reserved2:6;
+} sgmii_ctrl_t;
+#pragma pack(pop)
+
+#pragma pack(push,1)
+typedef struct
+{
+    uint32_t LINK_STATUS:1;
+    uint32_t RX_SIGDET:1;
+    uint32_t RXSEQDONE1G:1;
+    uint32_t SGMII:1;
+    uint32_t SYNC_STATUS:1;
+    uint32_t PLL_LOCK:1;
+    uint32_t DEB_SIG_DETECT:1;
+    uint32_t APD_STATE:3;
+    uint32_t Reserved:22;
+} sgmii_stat_t;
+#pragma pack(pop)
+
+static int _phy_speed_set(phy_dev_t *phy_dev, phy_speed_t speed, phy_duplex_t duplex)
+{
+    int ret;
+
+    if ((ret = sgmii_speed_set(phy_dev, speed)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_init(phy_dev_t *phy_dev)
+{
+    int ret;
+    phy_speed_t speed;;
+
+    if (phy_dev->mii_type == PHY_MII_TYPE_HSGMII)
+        speed = PHY_SPEED_2500;
+    else
+        speed = PHY_SPEED_1000;
+
+    if ((ret = sgmii_speed_set(phy_dev, speed)))
+        return ret;
+
+    return 0;
+}
+
+static int sgmii_bpcm_init(void)
+{
+    uint32_t data;
+
+    ReadBPCMRegister(PMB_ADDR_WAN, 0x10, &data);
+    data |= (1 << 5); // sgmii_z2_serdes_reset_n
+    WriteBPCMRegister(PMB_ADDR_WAN, 0x10, data);
+
+    return 0;
+}
+
+static void sgmii_ctrl_init(void)
+{
+    sgmii_ctrl_t sgmii_ctrl;
+
+    sgmii_ctrl.SERDES_PRTAD = phy_addr;
+    WRITE_32(SGMII_CTRL, sgmii_ctrl);
+    udelay(1000);
+
+    READ_32(SGMII_CTRL, sgmii_ctrl);
+    sgmii_ctrl.RESET_PLL = 1;
+    sgmii_ctrl.RESET_MDIOREGS = 1;
+    sgmii_ctrl.SERDES_RESET = 1;
+    sgmii_ctrl.IDDQ = 0;
+    sgmii_ctrl.PWRDWN = 0;
+    WRITE_32(SGMII_CTRL, sgmii_ctrl);
+    udelay(1000);
+
+    sgmii_ctrl.RESET_PLL = 0;
+    sgmii_ctrl.RESET_MDIOREGS = 0;
+    sgmii_ctrl.SERDES_RESET = 0;
+    WRITE_32(SGMII_CTRL, sgmii_ctrl);
+    udelay(1000);
+}
+
+static void wait_for_pll_lock(void)
+{
+    uint32_t retry = 20;
+    sgmii_stat_t sgmii_stat;
+
+    do {
+        READ_32(SGMII_STAT, sgmii_stat);
+        if (sgmii_stat.PLL_LOCK)
+            break;
+        udelay(1000);
+    } while (--retry);
+
+    if (!retry)
+        printk("SGMII Error: wait_for_pll_lock() reached maximum retries\n");
+    else
+        printk("SGMII PLL locked\n");
+}
+
+static int sgmii_cfg(void)
+{
+    sgmii_bpcm_init();
+    sgmii_ctrl_init();
+    wait_for_pll_lock();
+
+    return 0;
+}
+
+static int _phy_dev_add(phy_dev_t *phy_dev)
+{
+    phy_addr = phy_dev->addr;
+
+    return 0;
+}
+
+static int _phy_dev_del(phy_dev_t *phy_dev)
+{
+    phy_addr = 0;
+
+    return 0;
+}
+
+static int _phy_drv_init(phy_drv_t *phy_drv)
+{
+    if (phy_addr && sgmii_cfg())
+    {
+        printk("Failed to initialize the sgmii driver\n");
+        return -1;
+    }
+
+    phy_drv->initialized = 1;
+
+    return 0;
+}
+
+static int _phy_caps_get(phy_dev_t *phy_dev, int caps_type,  uint32_t *pcaps)
+{
+    *pcaps = PHY_CAP_AUTONEG | PHY_CAP_10_FULL | PHY_CAP_100_FULL | PHY_CAP_1000_FULL | PHY_CAP_2500;
+
+    return 0;
+}
+
+static int _phy_caps_set(phy_dev_t *phy_dev, uint32_t caps)
+{
+    return 0;
+}
+
+phy_drv_t phy_drv_6856_sgmii =
+{
+    .phy_type = PHY_TYPE_6856_SGMII,
+    .name = "SGMII",
+    .read = sgmii_read,
+    .write = sgmii_write,
+    .power_get = mii_power_get,
+    .power_set = mii_power_set,
+    .read_status = sgmii_read_status,
+    .speed_set = _phy_speed_set,
+    .caps_get = _phy_caps_get,
+    .caps_set = _phy_caps_set,
+    .phyid_get = mii_phyid_get,
+    .init = _phy_init,
+    .dev_add = _phy_dev_add,
+    .dev_del = _phy_dev_del,
+    .drv_init = _phy_drv_init,
+};
diff --git a/drivers/net/bcmbca/phy/phy_drv_6858_egphy.c b/drivers/net/bcmbca/phy/phy_drv_6858_egphy.c
new file mode 100644
index 0000000000..6e770652fc
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_6858_egphy.c
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ *  Phy driver for 6858 internal quad 1G phy
+ */
+
+#include "bus_drv.h"
+#include "phy_drv.h"
+#include "phy_drv_mii.h"
+#include "phy_drv_brcm.h"
+
+#define CORE_SHD18_000          0x0028 /* Auxiliary Control */
+#define CORE_BASE1E             0x000e /* Test1_Register */
+#define CORE_EXPB0              0x00b0 /* Bias Control 0 */
+#define DSP_TAP10               0x0125 /* PLL Bandwidth Control */
+#define AFE_RXCONFIG_2          0x01e2 /* AFE RXCONFIG 2 */
+#define AFE_HPF_TRIM_OTHERS     0x01e8 /* HPF trim and RXCONFIG 49:48 and reserved bits */
+#define DSP_TAP33_C2            0x0152 /* EEE LPI Timers */
+#define DSP_TAP34_C2            0x0156 /* EEE 100TX Mode BW control */
+#define DSP_FFE_ZERO_DET_CTL    0x0166 /* FFE Zero Detection Control */
+
+static int _phy_afe(phy_dev_t *phy_dev)
+{
+    int ret;
+
+    /* Enable the dsp clock */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD18_000, 0x0c30)))
+        goto Exit;
+
+    /* +1 RCAL codes for RL centering for both LT and HT conditions; default was -2 */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | AFE_RXCONFIG_2, 0xd003)))
+        goto Exit;
+
+    /* Cut master bias current by 2% to compensate for RCAL code offset */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | DSP_TAP10, 0x791b)))
+        goto Exit;
+
+    /* Improve hybrid leakage */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | AFE_HPF_TRIM_OTHERS, 0x10e3)))
+        goto Exit;
+
+    /* rx_on_tune 8 -> 0xf */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | DSP_TAP33_C2, 0x87f6)))
+        goto Exit;
+
+    /* 100tx EEE bandwidth */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | DSP_TAP34_C2, 0x017d)))
+        goto Exit;
+
+    /* Enable ffe zero det for Vitesse interop */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | DSP_FFE_ZERO_DET_CTL, 0x0015)))
+        goto Exit;
+
+    /* Reset R_CAL/RC_CAL Engine */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_EXPB0, 0x0010)))
+        goto Exit;
+
+    /* Disable Reset R_CAL/RC_CAL Engine */
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_EXPB0, 0x0000)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_init(phy_dev_t *phy_dev)
+{
+    int ret;
+
+    if ((ret = mii_init(phy_dev)))
+        goto Exit;
+
+    /* AFE workaround */
+    if ((ret = _phy_afe(phy_dev)))
+        goto Exit;
+
+    if ((ret = brcm_egphy_force_auto_mdix_set(phy_dev, 1)))
+        goto Exit;
+
+    if ((ret = brcm_egphy_eth_wirespeed_set(phy_dev, 1)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+extern int lport_led_init(void *leds_info);
+
+static int _phy_leds_init(phy_dev_t *phy_dev, void *leds_info)
+{
+    return lport_led_init(leds_info);
+}
+
+extern uint16_t lport_qgphy_base_addr_get(void);
+extern phy_drv_t phy_drv_6858_egphy;
+
+static int _phy_afe_all(void)
+{
+    int i, ret = 0;
+    phy_dev_t phy_dev = {};
+    phy_dev.phy_drv = &phy_drv_6858_egphy;
+    uint16_t base_addr = lport_qgphy_base_addr_get();
+
+    for (i = 0; i < 4; i++)
+    {
+        phy_dev.addr = base_addr + i;
+        ret |= _phy_afe(&phy_dev);
+    }
+
+    return ret;
+}
+
+static int _phy_drv_init(phy_drv_t *phy_drv)
+{
+    if (_phy_afe_all())
+    {
+        printk("Failed to initialize the phy AFE settings\n");
+        return -1;
+    }
+
+    phy_drv->initialized = 1;
+
+    return 0;
+}
+
+phy_drv_t phy_drv_6858_egphy =
+{
+    .phy_type = PHY_TYPE_6858_EGPHY,
+    .name = "EGPHY",
+    .read = brcm_egphy_read,
+    .write = brcm_egphy_write,
+    .power_get = mii_power_get,
+    .power_set = mii_power_set,
+    .apd_get = brcm_egphy_apd_get,
+    .apd_set = brcm_egphy_apd_set,
+    .eee_get = brcm_egphy_eee_get,
+    .eee_set = brcm_egphy_eee_set,
+    .eee_resolution_get = brcm_egphy_eee_resolution_get,
+    .read_status = brcm_read_status,
+    .speed_set = mii_speed_set,
+    .caps_get = mii_caps_get,
+    .caps_set = mii_caps_set,
+    .phyid_get = mii_phyid_get,
+    .auto_mdix_set = brcm_egphy_force_auto_mdix_set,
+    .auto_mdix_get = brcm_egphy_force_auto_mdix_get,
+    .wirespeed_set = brcm_egphy_eth_wirespeed_set,
+    .wirespeed_get = brcm_egphy_eth_wirespeed_get,
+    .leds_init = _phy_leds_init,
+    .cable_diag_run = brcm_cable_diag_run,
+    .init = _phy_init,
+    .drv_init = _phy_drv_init,
+};
diff --git a/drivers/net/bcmbca/phy/phy_drv_brcm.c b/drivers/net/bcmbca/phy/phy_drv_brcm.c
new file mode 100644
index 0000000000..5f0932e42c
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_brcm.c
@@ -0,0 +1,1170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Jan 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Common functions for Broadcom phy drivers
+ */
+
+#include "bus_drv.h"
+#include "phy_drv.h"
+#include "phy_drv_mii.h"
+#include "phy_drv_brcm.h"
+
+#define AUXSTAT                     0x19
+#define BRCM_MIIEXT_BANK            0x1f
+
+#define EXP_REG_BASE                0x0f00
+#define EXP_REG_ADDRESS             0x17
+#define EXP_REG_VALUE               0x15
+#define RDB_REG_ADDRESS             0x1e
+#define RDB_REG_VALUE               0x1f
+
+#define CORE_SHD18_111              0x002f /* Miscellanous Control Register */
+#define CORE_SHD1C_0A               0x001a /* Auto-Power Down */
+#define CORE_SHD1C_05               0x0015 /* Reserved Control 3 */
+
+#define EEE_CONTROL                 0x803d /* EEE Control */
+#define EEE_RES_STAT                0x803e /* EEE Resolution Status */
+#define EEE_ADV                     0x003c /* EEE Advertisement */
+#define EEE_LP_ADV                  0x003d /* EEE Link Partner Advertisement */
+
+#define REG_18                      0x18
+#define REG_1C                      0x1c
+
+#define REG_18_SHIFT                12
+#define REG_1C_SHIFT                10
+
+#define REG_18_MISC_CTRL            0x07
+
+#define REG_1C_APD                  0x0a
+#define REG_1C_SPARE_CTRL           0x05
+#define REG_1C_CLK_ALIGN_CTRL       0x03
+
+#define WRITE_ENABLE                0x8000
+
+#define BRCM_PHY_REG_FORCE_LINK     (0x1<<12)
+#define BRCM_PHY_TEST_REG           0x1e
+
+int brcm_read_status(phy_dev_t *phy_dev)
+{
+    int ret, mode;
+    uint16_t val;
+    phy_dev->link = 0;
+    phy_dev->speed = PHY_SPEED_UNKNOWN;
+    phy_dev->duplex = PHY_DUPLEX_UNKNOWN;
+    phy_dev->pause_rx = 0;
+    phy_dev->pause_tx = 0;
+
+    if ((ret = phy_bus_read(phy_dev, AUXSTAT, &val)))
+        return ret;
+
+    phy_dev->link = ((val >> 2) & 0x1);
+
+    if (!phy_dev->link)
+        return 0;
+
+    mode = ((val >> 8) & 0x7);
+
+    if (mode == 1)
+    {
+        phy_dev->speed = PHY_SPEED_10;
+        phy_dev->duplex = PHY_DUPLEX_HALF;
+    }
+    else if (mode == 2)
+    {
+        phy_dev->speed = PHY_SPEED_10;
+        phy_dev->duplex = PHY_DUPLEX_FULL;
+    }
+    else if (mode == 3)
+    {
+        phy_dev->speed = PHY_SPEED_100;
+        phy_dev->duplex = PHY_DUPLEX_HALF;
+    }
+    else if (mode == 5)
+    {
+        phy_dev->speed = PHY_SPEED_100;
+        phy_dev->duplex = PHY_DUPLEX_FULL;
+    }
+    else if (mode == 6)
+    {
+        phy_dev->speed = PHY_SPEED_1000;
+        phy_dev->duplex = PHY_DUPLEX_HALF;
+    }
+    else if (mode == 7)
+    {
+        phy_dev->speed = PHY_SPEED_1000;
+        phy_dev->duplex = PHY_DUPLEX_FULL;
+    }
+    else
+    {
+        phy_dev->link = 0;
+        return 0;
+    }
+
+    phy_dev->pause_rx = ((val >> 1) & 0x1);
+    phy_dev->pause_tx = ((val >> 0) & 0x1);
+
+    return 0;
+}
+
+int brcm_loopback_set(phy_dev_t *phy_dev, int enable, phy_speed_t speed)
+{
+    int rc; 
+    uint32_t caps;
+    uint16_t v16;
+    int cur_loopback;
+    phy_speed_t cur_speed;
+
+    brcm_loopback_get(phy_dev, &cur_loopback, &cur_speed);
+
+    if ((rc = phy_bus_read(phy_dev, MII_BMCR, &v16)))
+        return rc;
+
+    if(enable) {
+        if (cur_loopback) {
+            printk("Disable loop back first before enabling it.\n");
+            return -1;
+        }
+
+        if (phy_dev->link) {
+            printk("Disconnect the port before renabling loopback.\n");
+            return -1;
+        }
+
+        if (speed == PHY_SPEED_UNKNOWN)
+            speed = cascade_phy_max_speed_get(phy_dev);
+
+        cascade_phy_dev_caps_get(phy_dev, CAPS_TYPE_ADVERTISE, &caps);
+        if (!phy_dev_cap_speed_match(caps, speed)) {
+            printk("Error: Speed %d Mbps is not supported by this PHY.\n", phy_speed_2_mbps(speed));
+            return -1;
+        }
+
+        rc += phy_bus_read(phy_dev, MII_BMCR, &v16);
+        phy_dev->loopback_save = v16;
+        v16 &= ~(BMCR_SPEED1000|BMCR_SPEED100|BMCR_ANENABLE);
+        v16 |= (speed==PHY_SPEED_1000?BMCR_SPEED1000:BMCR_SPEED100)|BMCR_LOOPBACK|BMCR_FULLDPLX;
+        rc += phy_bus_write(phy_dev, MII_BMCR, v16);
+
+        rc += phy_bus_read(phy_dev, BRCM_PHY_TEST_REG, &v16);
+        v16 |= BRCM_PHY_REG_FORCE_LINK;
+        rc += phy_bus_write(phy_dev, BRCM_PHY_TEST_REG, v16);
+    }
+    else {
+        /* Only do disable if enable is done by the same API, not direct register operation */
+        if (!phy_dev->loopback_save) {
+            printk("Error: Loopback is not enabled\n");
+            return -1;
+        }
+
+        rc += phy_bus_write(phy_dev, MII_BMCR, phy_dev->loopback_save);
+        phy_dev->loopback_save = 0;
+
+        rc += phy_bus_read(phy_dev, BRCM_PHY_TEST_REG, &v16);
+        v16 &= ~BRCM_PHY_REG_FORCE_LINK;
+        rc += phy_bus_write(phy_dev, BRCM_PHY_TEST_REG, v16);
+    }
+    return rc;
+}
+
+int brcm_loopback_get(phy_dev_t *phy_dev, int *enable, phy_speed_t *speed)
+{
+    int rc;
+    uint16_t v16;
+
+    if ((rc = phy_bus_read(phy_dev, MII_BMCR, &v16)))
+        return rc;
+
+    *enable = 0;
+    if (phy_dev->loopback_save == 0)
+        return 0;
+
+    *enable = 1;
+    rc += phy_bus_read(phy_dev, MII_BMCR, &v16);
+    *speed = (v16&BMCR_SPEED1000)? PHY_SPEED_1000:PHY_SPEED_100;
+ 
+    return rc;
+}
+
+static int brcm_shadow_rw(phy_dev_t *phy_dev, int write, int bank, uint16_t reg, uint16_t *val)
+{
+    int ret = 0;
+
+    switch (bank)
+    {
+    case 1: 
+        if ((ret = phy_bus_write(phy_dev, BRCM_MIIEXT_BANK, 0x8b)))
+            goto Exit;
+        break;
+    case 2:
+    case 3:
+        if ((ret = phy_bus_write(phy_dev, BRCM_MIIEXT_BANK, 0x0f)))
+            goto Exit;
+        break;
+    }
+
+    if (bank == 3)
+    {
+        if (write)
+        {
+            if ((ret = phy_bus_write(phy_dev, 0x0e, reg)))
+                goto Exit;
+
+            if ((ret = phy_bus_write(phy_dev, 0x0f, *val)))
+                goto Exit;
+        }
+        else
+        {
+            if ((ret = phy_bus_write(phy_dev, 0x0e, reg)))
+                goto Exit;
+            if ((ret = phy_bus_read(phy_dev, 0x0f, val)))
+                goto Exit;
+        }
+    }
+    else
+    {
+        if (write)
+        {
+            if ((ret = phy_bus_write(phy_dev, reg, *val)))
+                goto Exit;
+        }
+        else 
+        {
+            if ((ret = phy_bus_read(phy_dev, reg, val)))
+                goto Exit;
+        }
+    }
+
+    if ((ret = phy_bus_write(phy_dev, BRCM_MIIEXT_BANK, 0x0b)))
+            goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_shadow_read(phy_dev_t *phy_dev, int bank, uint16_t reg, uint16_t *val)
+{
+    return brcm_shadow_rw(phy_dev, 0, bank, reg, val);
+}
+
+int brcm_shadow_write(phy_dev_t *phy_dev, int bank, uint16_t reg, uint16_t val)
+{
+    return brcm_shadow_rw(phy_dev, 1, bank, reg, &val);
+}
+
+int brcm_exp_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val)
+{
+    if (phy_bus_write(phy_dev, EXP_REG_ADDRESS, EXP_REG_BASE | reg))
+        return -1;
+
+    if (phy_bus_read(phy_dev, EXP_REG_VALUE, val))
+        return -1;
+
+    return 0;
+}
+
+int brcm_exp_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val)
+{
+    if (phy_bus_write(phy_dev, EXP_REG_ADDRESS, EXP_REG_BASE | reg))
+        return -1;
+
+    if (phy_bus_write(phy_dev, EXP_REG_VALUE, val))
+        return -1;
+
+    return 0;
+}
+
+int brcm_rdb_set(phy_dev_t *phy_dev, int enable)
+{
+    if (enable)
+        return brcm_exp_write(phy_dev, 0x7e, 0x0000);
+    else
+        return brcm_rdb_write(phy_dev, 0x87, 0x8000);
+}
+
+int brcm_rdb_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val)
+{
+    if (phy_bus_write(phy_dev, RDB_REG_ADDRESS, reg))
+        return -1;
+
+    if (phy_bus_read(phy_dev, RDB_REG_VALUE, val))
+        return -1;
+
+    return 0;
+}
+
+int brcm_rdb_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val)
+{
+    if (phy_bus_write(phy_dev, RDB_REG_ADDRESS, reg))
+        return -1;
+
+    if (phy_bus_write(phy_dev, RDB_REG_VALUE, val))
+        return -1;
+
+    return 0;
+}
+
+int brcm_egphy_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val)
+{
+    int ret;
+
+    if (reg & RDB_ACCESS)
+    {
+        if ((ret = brcm_rdb_set(phy_dev, 1)))
+            goto Exit;
+
+        if ((ret = brcm_rdb_read(phy_dev, reg & ~RDB_ACCESS, val))) 
+            goto Exit;
+
+        if ((ret = brcm_rdb_set(phy_dev, 0)))
+            goto Exit;
+    }
+    else
+    {
+        if ((ret = phy_bus_read(phy_dev, reg, val)))
+            goto Exit;
+    }
+
+Exit:
+    return ret;
+}
+
+int brcm_egphy_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val)
+{
+    int ret;
+
+    if (reg & RDB_ACCESS)
+    {
+        if ((ret = brcm_rdb_set(phy_dev, 1)))
+            goto Exit;
+
+        if ((ret = brcm_rdb_write(phy_dev, reg & ~RDB_ACCESS, val))) 
+            goto Exit;
+
+        if ((ret = brcm_rdb_set(phy_dev, 0)))
+            goto Exit;
+    }
+    else
+    {
+        if ((ret = phy_bus_write(phy_dev, reg, val)))
+            goto Exit;
+    }
+
+Exit:
+    return ret;
+}
+
+int brcm_egphy_force_auto_mdix_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t val;
+
+    if ((ret = phy_dev_read(phy_dev, RDB_ACCESS | CORE_SHD18_111, &val)))
+        goto Exit;
+
+    if (enable)
+        val |= (1 << 9); /* Enable Force Auto MDIX */
+    else
+        val &= ~(1 << 9); /* Disable  Force Auto MDIX */
+
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD18_111, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_egphy_force_auto_mdix_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    if ((ret = phy_dev_read(phy_dev, RDB_ACCESS | CORE_SHD18_111, &val)))
+        goto Exit;
+
+    *enable = val & (1 << 9) ? 1 : 0; /* Force Auto MDIX Enabled */
+
+Exit:
+    return ret;
+}
+
+int brcm_egphy_eth_wirespeed_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    if ((ret = phy_dev_read(phy_dev, RDB_ACCESS | CORE_SHD18_111, &val)))
+        goto Exit;
+
+    *enable = val & (1 << 4) ? 1 : 0; /* Ethernet@Wirespeed Enabled */
+
+Exit:
+    return ret;
+}
+
+
+int brcm_egphy_eth_wirespeed_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t val;
+
+    if ((ret = phy_dev_read(phy_dev, RDB_ACCESS | CORE_SHD18_111, &val)))
+        goto Exit;
+
+    if (enable)
+        val |= (1 << 4); /* Enable Ethernet@Wirespeed */
+    else
+        val &= ~(1 << 4); /* Disable Ethernet@Wirespeed */
+
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD18_111, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_egphy_apd_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    val = 0;
+
+    if ((ret = phy_dev_read(phy_dev, RDB_ACCESS | CORE_SHD1C_0A, &val)))
+        goto Exit;
+
+#if defined(CONFIG_BCM963146) || defined(CONFIG_BCM94912)   
+    *enable = (val & (1 << 5)) && (val & (1 << 6)) ? 1 : 0;
+#else
+    *enable = val & (1 << 5) ? 1 : 0;
+#endif
+
+Exit:
+    return ret;
+}
+int brcm_egphy_apd_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t val;
+
+    /* Auto-Power Down */
+    val = 0;
+    val |= (1 << 0); /* Counter for wakeup timer = 84 ms */
+
+    if (enable)
+    {
+#if defined(CONFIG_BCM963146) || defined(CONFIG_BCM94912)   
+        val |= (1 << 5); /* Enable auto powerdown for 16nm chips */
+        val |= (1 << 6); /* Bits 6, 5 = ON for AUTO_PWRD, Bit 8 = OFF */
+#else
+        val |= (1 << 5); /* Enable auto powerdown */
+        val |= (1 << 8); /* Enable energy detect single link pulse */
+#endif
+    }
+
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD1C_0A, val)))
+        goto Exit;
+
+    /* Reserved Control 3 */
+    if ((ret = phy_dev_read(phy_dev, RDB_ACCESS | CORE_SHD1C_05, &val)))
+        goto Exit;
+
+    if (enable)
+    {
+        val |= (1 << 0); /* Disable CLK125 output */
+        val &= ~(1 << 1); /* Enable powering down of dll during auto-power down */
+    }
+    else
+    {
+        val &= ~(1 << 0); /* Enable CLK125 output */
+        val |= (1 << 1); /* Disable powering down of dll during auto-power down */
+    }
+
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | CORE_SHD1C_05, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_egphy_eee_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    /* local EEE Status */
+    if ((ret = phy_bus_c45_read(phy_dev, 7, EEE_ADV, &val)))
+        goto Exit;
+
+    *enable = (val & (1 << 1) || val & (1 << 2));
+
+Exit:
+    return ret;
+}
+
+int brcm_egphy_eee_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t val;
+
+    /* EEE Control */
+    val = 0;
+    if (enable)
+    {
+        val |= (1 << 14); /* Enable EEE capability using SGMII auto-negotiation */
+        val |= (1 << 15); /* Enable EEE LPI feature */
+    }
+
+    if ((ret = phy_bus_c45_write(phy_dev, 7, EEE_CONTROL, val)))
+        goto Exit;
+
+    /* EEE Advertisement */
+    val = 0;
+    if (enable)
+    {
+        val |= (1 << 1); /* EEE support for 100BASE-TX */
+        val |= (1 << 2); /* EEE support for 1000BASE-T */
+    }
+
+    if ((ret = phy_bus_c45_write(phy_dev, 7, EEE_ADV, val)))
+        goto Exit;
+
+    if ((ret = mii_autoneg_restart(phy_dev)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_egphy_eee_resolution_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    /* EEE Resolution Status */
+    if ((ret = phy_bus_c45_read(phy_dev, 7, EEE_RES_STAT, &val)))
+        goto Exit;
+
+    /* Check if the link partner auto-negotiated EEE capability for 100BASE-TX or 1000BASE-T */
+    *enable = (val & (1 << 1) || val & (1 << 2));
+
+Exit:
+    return ret;
+}
+
+int brcm_ephy_apd_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    /* Auxiliary Status 2 Register */
+    if ((ret = brcm_shadow_read(phy_dev, 1, 0x1b, &val)))
+        goto Exit;
+
+    *enable = val & (1 << 5) ? 1 : 0; /* APD Enabled */
+
+Exit:
+    return ret;
+}
+
+int brcm_ephy_apd_set(phy_dev_t *phy_dev, int enable)
+{
+    uint16_t val;
+
+    /* Auxiliary Status 2 Register */
+    val = 0;
+    val |= (1 << 0); /* Wake-up timer = 40 milliseconds */
+    val |= (7 << 12); /* Cable Length > 140 meters */
+
+    if (enable)
+        val |= (1 << 5); /* APD Enable */
+
+    return brcm_shadow_write(phy_dev, 1, 0x1b, val);
+}
+
+int brcm_ephy_eee_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    /* Auto-Negotiation EEE Advertisement */
+    if ((ret = brcm_shadow_read(phy_dev, 3, 0x03, &val)))
+        goto Exit;
+
+    *enable = val & (1 << 1);
+
+Exit:
+    return ret;
+}
+
+int brcm_ephy_eee_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t val;
+
+    if (enable)
+    {
+        /* Auto-Negotiation EEE Advertisement */
+        val = 0;
+        val |= (1 << 1); /* EEE Auto-negotiation advertise */
+        if ((ret = brcm_shadow_write(phy_dev, 3, 0x03, val)))
+            goto Exit;
+
+        /* PCS Control */
+        val = 0;
+        val |= (2 << 9); /* TACF Phase Track Mode = 2 */
+        val |= (1 << 14); /* TACF Beta Control = 0.5 */
+        if ((ret = brcm_shadow_write(phy_dev, 3, 0x06, val)))
+            goto Exit;
+
+        /* EEE Phase Search MSE Threshold */
+        val = 0;
+        val |= (0x50 << 0); /* MSE error threshold = 0x50 */
+        if ((ret = brcm_shadow_write(phy_dev, 3, 0x0e, val)))
+            goto Exit;
+
+        /* Auto-Negotiation Status Register */
+        val = 0;
+        val |= (1 << 0); /* Null message enabled for auto-negotiation */
+        val |= (1 << 1); /* EEE auto-negotiation enabled */
+        if ((ret = brcm_shadow_write(phy_dev, 3, 0x0b, val)))
+            goto Exit;
+    }
+    else
+    {
+        /* Auto-Negotiation EEE Advertisement */
+        val = 0;
+        if ((ret = brcm_shadow_write(phy_dev, 3, 0x03, val)))
+            goto Exit;
+
+        /* Auto-Negotiation Status Register */
+        val = 0;
+        if ((ret = brcm_shadow_write(phy_dev, 3, 0x0b, val)))
+            goto Exit;
+    }
+
+    if ((ret = mii_autoneg_restart(phy_dev)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_ephy_eee_resolution_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    /* Auto-Negotiation Status Register */
+    if ((ret = brcm_shadow_read(phy_dev, 3, 0x0b, &val)))
+        goto Exit;
+
+    /* Auto-negotiation EEE Enable, Auto-negotiation EEE Resolution */
+    *enable = (val & (1 << 1) && val & (1 << 8));
+
+Exit:
+    return ret;
+}
+
+int brcm_shadow_18_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val)
+{
+    int ret;
+
+    *val = REG_18_MISC_CTRL | reg << REG_18_SHIFT;
+    
+    if ((ret = phy_bus_write(phy_dev, REG_18, *val)))
+        goto Exit;
+
+    if ((ret = phy_bus_read(phy_dev, REG_18, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_shadow_18_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val)
+{
+    int ret;
+
+    val |= ((reg == REG_18_MISC_CTRL) ? WRITE_ENABLE : 0) | reg;
+    
+    if ((ret = phy_bus_write(phy_dev, REG_18, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_shadow_1c_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val)
+{
+    int ret;
+
+    *val = reg << REG_1C_SHIFT;
+    
+    if ((ret = phy_bus_write(phy_dev, REG_1C, *val)))
+        goto Exit;
+
+    if ((ret = phy_bus_read(phy_dev, REG_1C, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_shadow_1c_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val)
+{
+    int ret;
+
+    val |= WRITE_ENABLE | reg << REG_1C_SHIFT;
+    
+    if ((ret = phy_bus_write(phy_dev, REG_1C, val)))
+        goto Exit;
+Exit:
+    return ret;
+}
+
+
+int brcm_shadow_18_force_auto_mdix_set(phy_dev_t *phy_dev, int enable)
+{
+    uint16_t val;
+    int ret;
+
+    if ((ret = brcm_shadow_18_read(phy_dev, REG_18_MISC_CTRL, &val)))
+        goto Exit;
+
+    if (enable)
+        val |= (1 << 9); /* Enable Force Auto MDIX */
+    else
+        val &= ~(1 << 9); /* Disable  Force Auto MDIX */
+
+    if ((ret = brcm_shadow_18_write(phy_dev, REG_18_MISC_CTRL, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_shadow_18_force_auto_mdix_get(phy_dev_t *phy_dev, int *enable)
+{
+    uint16_t val;
+    int ret;
+
+    if ((ret = brcm_shadow_18_read(phy_dev, REG_18_MISC_CTRL, &val)))
+        goto Exit;
+
+    *enable = val & (1 << 9) ? 1 : 0; /* Force Auto MDIX Enabled */
+
+Exit:
+    return ret;
+}
+
+int brcm_shadow_18_eth_wirespeed_get(phy_dev_t *phy_dev, int *enable)
+{
+    uint16_t val;
+    int ret;
+
+    if ((ret = brcm_shadow_18_read(phy_dev, REG_18_MISC_CTRL, &val)))
+        goto Exit;
+
+    *enable = val & (1 << 4) ? 1 : 0; /* Ethernet@Wirespeed Enabled */
+
+Exit:
+    return ret;
+}
+
+int brcm_shadow_18_eth_wirespeed_set(phy_dev_t *phy_dev, int enable)
+{
+    uint16_t val;
+    int ret;
+
+    if ((ret = brcm_shadow_18_read(phy_dev, REG_18_MISC_CTRL, &val)))
+        goto Exit;
+
+    if (enable)
+        val |= (1 << 4); /* Enable Ethernet@Wirespeed */
+    else
+        val &= ~(1 << 4); /* Disable Ethernet@Wirespeed */
+
+    if ((ret = brcm_shadow_18_write(phy_dev, REG_18_MISC_CTRL, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_shadow_1c_apd_get(phy_dev_t *phy_dev, int *enable)
+{
+    uint16_t val;
+    int ret;
+
+    if ((ret = brcm_shadow_1c_read(phy_dev, REG_1C_APD, &val)))
+        goto Exit;
+
+    *enable = val & (1 << 5) ? 1 : 0; /* APD Enabled */
+
+Exit:
+    return ret;
+}
+
+int brcm_shadow_1c_apd_set(phy_dev_t *phy_dev, int enable)
+{
+    uint16_t val;
+    int ret;
+
+    val = (1 << 0); /* APD Wakeup timer */
+    if (enable)
+    {
+        val |= (1 << 5); /* APD Enable */
+        val |= (1 << 8); /* APD Compatibility */
+    }
+
+    if ((ret = brcm_shadow_1c_write(phy_dev, REG_1C_APD, val)))
+        goto Exit;
+
+    if ((ret = brcm_shadow_1c_read(phy_dev, REG_1C_SPARE_CTRL, &val)))
+        goto Exit;
+
+    if (enable)
+    {
+        val &= ~(1 << 0); /* Disable CLK125 Output */
+        val &= ~(1 << 1); /* Enable CLK125 APD */
+    }
+    else
+    {
+        val |= (1 << 0); /* Enable CLK125 Output */
+        val |= (1 << 1); /* Disable CLK125 APD */
+    }
+
+    if ((ret = brcm_shadow_1c_write(phy_dev, REG_1C_SPARE_CTRL, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int brcm_shadow_rgmii_init(phy_dev_t *phy_dev)
+{
+    uint16_t val;
+    int ret;
+
+    if ((ret = brcm_shadow_18_read(phy_dev, REG_18_MISC_CTRL, &val)))
+        goto Exit;
+
+    val |= (1 << 5); /* Disable RGMII Out of Band Status */;
+    val |= (1 << 7); /* Enable RGMII Mode */
+
+    if (phy_dev->delay_rx)
+        val |= (1 << 8); /* Enable RGMII RXC Delay */
+    else
+        val &= ~(1 << 8); /* Disable RGMII RXC Delay */
+
+    if ((ret = brcm_shadow_18_write(phy_dev, REG_18_MISC_CTRL, val)))
+        goto Exit;
+
+    if ((ret = brcm_shadow_1c_read(phy_dev, REG_1C_CLK_ALIGN_CTRL, &val)))
+        goto Exit;
+
+    if (phy_dev->delay_tx)
+        val |= (1 << 9); /* Enable GTXCLK Delay */
+    else
+        val &= ~(1 << 9); /* Disable GTXCLK Delay */
+
+    if ((ret = brcm_shadow_1c_write(phy_dev, REG_1C_CLK_ALIGN_CTRL, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int mii_exp_write(phy_dev_t *phy_dev, int reg, int val)
+{
+    int ret;
+    ret = phy_bus_write(phy_dev, MII_EXPAND_REG_REG, reg|MII_EXPAND_REG_MARK);
+    ret |= phy_bus_write(phy_dev, MII_EXPAND_REG_VAL, val);
+    return ret;
+}
+
+static int mii_exp_read(phy_dev_t *phy_dev, int reg, uint16_t *val)
+{
+    int ret;
+    ret = phy_bus_write(phy_dev, MII_EXPAND_REG_REG, reg|MII_EXPAND_REG_MARK);
+    ret |= phy_bus_read(phy_dev, MII_EXPAND_REG_VAL, val);
+    return ret;
+}
+
+static void phy_cable_diag_init(phy_dev_t *phy_dev)
+{
+#define TH_1_0	0x0102
+#define TH_3_2	0x0208
+#define TH_5_4	0x380F
+#define PPW_1_0	0x5700
+/* #define PPW_5_4_3_2	0x738E '4 probe setting */
+#define PPW_5_4_3_2	0x92AC
+/* #define PPWI_5_4_3_2_1_0	0x1000 */
+#define PPWI_5_4_3_2_1_0	0x5000
+#define PROBE_TYPE_6_5_4_3_2_1_0	0x9000
+
+#define OFFSET_1_0	0x0E00
+#define OFFSET_3_2	0x390B
+/* #define OFFSET_3_2	0x3F18 */
+#define OFFSET_5_4	0x0078
+
+#define RX_CONFIG_1	0x0540
+#define RX_CONFIG_2	0x0440
+/* #define RX_CONFIG_3	0x0841 */
+#define RX_CONFIG_3	0x0F40
+#define RX_CONFIG_4	0x1345
+#define RX_CONFIG_5	0x1523
+
+#define START_0	0x0C00
+#define START_3_2_1	0xC590
+/* #define START_3_2_1	0x86C0 */
+/* #define START_4_3	0x4B33 'old setting */
+/* #define START_4_3	0x622E */
+#define START_4_3	0x5C2E
+#define START_5_4	0x2278
+    uint16_t v16;
+
+    if (phy_dev->flag & PHY_FLAG_CABLE_DIAG_INITED)
+        return;
+
+    mii_exp_write(phy_dev, 0xC0, 0x0000);    /* disable Autoneg ECD */
+    mii_exp_write(phy_dev, 0xC7, 0xA01A);    /* EXPC7 frct_i_2 = 240, frct_i_1 = 4 */
+    mii_exp_write(phy_dev, 0xC8, 0x0300);    /* EXPC8 th_silent = 1 for 54382 ADC */
+    mii_exp_write(phy_dev, 0xC9, 0x00EF);    /* EXPC9 silent_c_th = 13, block_width_i = 9 */
+    mii_exp_write(phy_dev, 0xCB, 0x1304);    /* EXPCB  */
+    mii_exp_write(phy_dev, 0xCC, 0x0000);    /* EXPCC temp using 5 probe */
+    mii_exp_write(phy_dev, 0xCE, 0x4000);    /* EXPCE lp_drop_wait = 1, lp_safe_time = 5 */
+    mii_exp_write(phy_dev, 0xCF, 0x3000);    /* EXPCF disable both types of random starts */
+
+    /* --------------------------------------------------------------------------------- */
+    /* ------- page '01' */
+    /* --------------------------------------------------------------------------------- */
+    mii_exp_write(phy_dev, 0xE0, TH_1_0);    /* EXPE0 set th[1] and th[0] value */
+    mii_exp_write(phy_dev, 0xE1, TH_3_2);    /* EXPE1 set th[3] & th[2] value */
+    mii_exp_write(phy_dev, 0xE2, TH_5_4);    /* EXPE2 restore exp. E2 */
+
+    mii_exp_write(phy_dev, 0xE3, PPW_1_0);    /* EXPE3 increase ppw[1] to 3, keep ppw[0] To 3 */
+    mii_exp_write(phy_dev, 0xE4, PPW_5_4_3_2);    /* EXPE4 default ppw[3] to 6 and default ppw[2] to 4 */
+    mii_exp_write(phy_dev, 0xE5, PPWI_5_4_3_2_1_0);    /* EXPE5  */
+    mii_exp_write(phy_dev, 0xE6, PROBE_TYPE_6_5_4_3_2_1_0);    /* EXPE6  */
+    mii_exp_write(phy_dev, 0xE7, 0xAA00);    /* EXPE7  */
+    /* --------------------------------------------------------------------------------- */
+    /* --- Now load values */
+    mii_exp_write(phy_dev, 0xEF, 0x40FF);    /* EXPEF write to shadow page 01' word 'E7', 'E6', 'E5', 'E4', 'E3', 'E2', 'E1', & ' E0' */
+    mii_exp_write(phy_dev, 0xCD, 0x1000);    /* EXPCD write strobe 1 */
+    mii_exp_write(phy_dev, 0xCD, 0x0000);    /* EXPCD write strobe 0 */
+    mii_exp_write(phy_dev, 0xE0, 0x0000);    /* EXPE0 restore exp. E0 */
+    mii_exp_write(phy_dev, 0xE1, 0x0000);    /* EXPE1 restore exp. E1 */
+    mii_exp_write(phy_dev, 0xE2, 0x0000);    /* EXPE2 restore exp. E2 */
+    mii_exp_write(phy_dev, 0xE3, 0x0000);    /* EXPE3 restore exp. E3 */
+    mii_exp_write(phy_dev, 0xE4, 0x0000);    /* EXPE4 restore exp. E4 */
+    mii_exp_write(phy_dev, 0xE5, 0x0000);    /* EXPE5 restore exp. E5 */
+    mii_exp_write(phy_dev, 0xE6, 0x0000);    /* EXPE6 restore exp. E6 */
+    mii_exp_write(phy_dev, 0xE7, 0x0000);    /* EXPE7 restore exp. E7 */
+    mii_exp_write(phy_dev, 0xEF, 0x0000);    /* EXPEF restore exp. EF */
+
+    /* --------------------------------------------------------------------------------- */
+    /* ------- page '10' */
+    /* --------------------------------------------------------------------------------- */
+
+    mii_exp_write(phy_dev, 0xE0, OFFSET_1_0);    /* EXPE0  */
+    mii_exp_write(phy_dev, 0xE1, OFFSET_3_2);    /* EXPE1  */
+    mii_exp_write(phy_dev, 0xE2, OFFSET_5_4);    /* EXPE2  */
+    /* --------------------------------------------------------------------------------- */
+    /* --- Now load values */
+    mii_exp_write(phy_dev, 0xEF, 0x8007);    /* EXPEF write to shadow page */
+    mii_exp_write(phy_dev, 0xCD, 0x1000);    /* EXPCD write strobe 1 */
+    mii_exp_write(phy_dev, 0xCD, 0x0000);    /* EXPCD write strobe 0 */
+
+    mii_exp_write(phy_dev, 0xE0, 0x0000);    /* EXPE0 restore exp. E0 */
+    mii_exp_write(phy_dev, 0xE1, 0x0000);    /* EXPE1 restore exp. E1 */
+    mii_exp_write(phy_dev, 0xE2, 0x0000);    /* EXPE2 restore exp. E2 */
+    mii_exp_write(phy_dev, 0xEF, 0x0000);    /* EXPEF restore exp. EF */
+    /* --------------------------------------------------------------------------------- */
+    /* ------- page '00' */
+    /* --------------------------------------------------------------------------------- */
+    mii_exp_write(phy_dev, 0xE0, 0x0001);    /* EXPE0  */
+    mii_exp_write(phy_dev, 0xE1, RX_CONFIG_1);    /* EXPE1  */
+    mii_exp_write(phy_dev, 0xE2, RX_CONFIG_2);    /* EXPE2  */
+    mii_exp_write(phy_dev, 0xE3, RX_CONFIG_3);    /* EXPE3  */
+    mii_exp_write(phy_dev, 0xE4, RX_CONFIG_4);    /* EXPE4  */
+    mii_exp_write(phy_dev, 0xE5, RX_CONFIG_5);    /* EXPE5  */
+    /* App.WrExp 0, 0x00E7, START_0 */
+    mii_exp_write(phy_dev, 0xE8, START_3_2_1);    /* EXPE8  */
+    mii_exp_write(phy_dev, 0xE9, START_4_3);    /* EXPE9  */
+    mii_exp_write(phy_dev, 0xEA, START_5_4);    /* EXPEA  */
+    /* --------------------------------------------------------------------------------- */
+    mii_exp_write(phy_dev, 0xCD, 0x00D0);    /* EXPCD  */
+    /* --------------------------------------------------------------------------------- */
+    /* --Now we have finished ECD parameter loading. */
+    /* flush out old results */
+    mii_exp_read(phy_dev, 0xC0, &v16);    /* dummy read to flush out sticky bit in exp.C0 */
+    mii_exp_write(phy_dev, 0xC0, 0x0000);    /* EXPC0 disable Autoneg ECD */
+
+    phy_dev->flag |= PHY_FLAG_CABLE_DIAG_INITED;
+}
+
+/* 
+   Work around some hardware inconsistency
+   Pick up the most popular length from 4 pairs
+ */
+static void cable_length_pick_link_up(int *pair_len, int excluded_pair)
+{
+    int len[4]={0};
+    int i, j, k, m;
+
+    for (i=0, k=0; i<4; i++) {
+        if (excluded_pair & (1<<i))  /* Exclude failed CD pair */
+            continue;
+        
+        for(j=0; j<k; j++) 
+            if (pair_len[j] == pair_len[i]) 
+                break;
+        if (j==k)
+            k++;
+        len[j]++;
+    }
+
+    for (i=0, j=0, m=0; i<k; i++) {
+        if (len[i] == 0)    /* If result is zero, exclude the pair from picking */
+            continue;
+        
+        if(len[i]>j) {
+            j=len[i];
+            m=i;
+        }
+    }
+
+    m = pair_len[m];
+    for (i=0; i<4; i++)
+        pair_len[i] = m; 
+}
+
+#ifdef __UBOOT__
+static unsigned long _jiffies;
+#define jiffies (_jiffies++)
+#define msecs_to_jiffies(j) ((j)*10)
+#endif
+
+int brcm_cable_diag_run(phy_dev_t *phy_dev, int *result, int *pair_len)
+{
+    uint16_t v16;
+    int i, j, ret = 0, excluded_pair = 0;
+    int apd_enabled, phy_link;
+    unsigned long jiffie;
+    int retries = 0;
+#define ECD_CHECK_SECS 3
+#define ECD_MAX_RETRIES 3
+
+    phy_dev_apd_get(phy_dev, &apd_enabled);
+    if (apd_enabled)
+        phy_dev_apd_set(phy_dev, 0);
+
+    phy_cable_diag_init(phy_dev);
+
+TryAgain:
+    if (retries) for(i=0, jiffie = jiffies; jiffies < (jiffie + msecs_to_jiffies(2*1000)););
+    if (++retries > ECD_MAX_RETRIES)  /* If we did retry more than certain time, declares it as faiure */
+        goto end;
+
+    v16 = ECD_RUN_IMMEDIATE;
+    if ((phy_link = phy_dev->link))
+        v16 |= ECD_BREAK_LINK; 
+    mii_exp_write(phy_dev, MII_ECD_CTRL_STATUS, v16);
+
+    if (phy_link) { /* If link is up, Write RUN first and wait until link goes down */
+        for(;;) {
+            phy_dev_read_status(phy_dev);
+            if (!phy_dev->link) break;
+        }
+    }
+
+    for(i=0, jiffie = jiffies; jiffies < (jiffie + msecs_to_jiffies(ECD_CHECK_SECS*1000)); ) {
+        mii_exp_read(phy_dev, MII_ECD_CTRL_STATUS, &v16);
+        if (!(v16 & ECD_DIAG_IN_PROG)) {
+            i = 1;
+            break;
+        }
+    }
+
+    if (!i) {
+        *result = PA_CD_CODE_INVALID;
+        ret = -1;
+        goto TryAgain;
+    }
+
+    for(i=0, jiffie = jiffies; jiffies < (jiffie + msecs_to_jiffies(ECD_CHECK_SECS*1000)); ) { /* Check if all four pairs of diags are done */
+        ret = mii_exp_read(phy_dev, MII_ECD_CTRL_FAULT_TYPE, &v16);
+        *result = v16;
+        excluded_pair = 0;
+        for(j=0; j<4; j++) { /* Check if all four pairs of diags are done */
+            if( PA_CD_CODE_PAIR_GET(*result, j) > PA_CD_CODE_PAIR_INTER_SHORT) 
+                break;
+
+            /* If link is up, excluded failed measuring result */
+            if( phy_link && ( PA_CD_CODE_PAIR_GET(*result, j) != PA_CD_CODE_PAIR_OK))
+                excluded_pair |= (1<<j); 
+        }
+
+        /* If all pair of diags finish, check the results */
+        if (j==4) {
+            /* If in link up, all pair diag failed, try again */
+            if (*result == PA_CD_CODE_INVALID || excluded_pair == 0xf ) 
+                goto TryAgain;
+            /* Otherwise, we are done with CD */
+            i=1;
+            break;
+        }
+    }
+
+    if (phy_link)
+        *result = PA_CD_CODE_PAIR_ALL_OK;
+
+    if (*result == PA_CD_CODE_INVALID || !i) {
+        *result = PA_CD_CODE_INVALID;
+        ret = -1;
+        goto TryAgain;
+    }
+
+#define CABLE_LEN_OFFSET_LINK_DOWN 100
+    for(i=0; i<4; i++) {
+        ret |= mii_exp_read(phy_dev, MII_ECD_CABLE_LEN+i, &v16);
+        if (*result == PA_CD_CODE_PAIR_ALL_OPEN)
+            pair_len[i] = (v16> CABLE_LEN_OFFSET_LINK_DOWN ? v16 - CABLE_LEN_OFFSET_LINK_DOWN : 0); /* To guarrantee no cable result correct based on testing */
+        else
+            pair_len[i] = v16;
+    }
+
+    /* If link is up, but alll pair length is zero, try again */
+    if (phy_link && (pair_len[0] + pair_len[1] + pair_len[2] + pair_len[3] == 0))
+        goto TryAgain;
+
+end:
+    /* If link was up, poll until link comes back due to CD */
+    if (phy_dev->link) {
+        for(jiffie = jiffies; jiffies < (jiffie + msecs_to_jiffies(3*ECD_CHECK_SECS*1000)); ) {
+            phy_dev_read_status(phy_dev);
+            if (phy_dev->link) break;
+        }
+    }
+            
+    if (*result == PA_CD_CODE_PAIR_ALL_OK || phy_dev->link)
+        cable_length_pick_link_up(pair_len, excluded_pair);
+
+    if (apd_enabled)
+        phy_dev_apd_set(phy_dev, apd_enabled);
+
+    return ret;
+}
+
diff --git a/drivers/net/bcmbca/phy/phy_drv_brcm.h b/drivers/net/bcmbca/phy/phy_drv_brcm.h
new file mode 100644
index 0000000000..7fbad8be29
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_brcm.h
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Jan 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#ifndef __PHY_DRV_BRCM_H__
+#define __PHY_DRV_BRCM_H__
+
+#include "phy_drv.h"
+
+#define RDB_ACCESS              0x8000
+
+#define MII_EXPAND_REG_REG      0x17
+    #define MII_EXPAND_REG_MARK     (0xf<<8)
+#define MII_EXPAND_REG_VAL      0x15
+
+#define MII_ECD_CTRL_STATUS     0xc0
+    #define ECD_RUN_IMMEDIATE   (1<<15)
+    #define ECD_BREAK_LINK      (1<<12)
+    #define ECD_DIAG_IN_PROG    (1<<11)
+
+#define MII_ECD_CTRL_FAULT_TYPE 0xc1
+    #define PA_CD_CODE_SHIFT            4
+    #define PA_CD_CODE_MASK             0xf
+    #define PA_CD_CODE_INVALID          0x0
+    #define PA_CD_CODE_PAIR_OK          0x1
+    #define PA_CD_CODE_PAIR_OPEN        0x2
+    #define PA_CD_CODE_PAIR_INTRA_SHORT 0x3
+    #define PA_CD_CODE_PAIR_INTER_SHORT 0x4
+    #define PA_CD_CODE_PAIR_GET(v, p)          (((v)>>((p)*4))&0xf)
+    #define PA_CD_CODE_PAIR_SET(v, p)          (((v)&0xf)<<((p)*4))
+    #define PA_CD_CODE_PAIR_ALL_OK      0x1111
+    #define PA_CD_CODE_PAIR_ALL_OPEN    0x2222
+
+#define MII_ECD_CABLE_LEN 0xc2
+
+int brcm_cable_diag_run(phy_dev_t *phy_dev, int *result, int *pair_len);
+int brcm_read_status(phy_dev_t *phy_dev);
+
+int brcm_shadow_read(phy_dev_t *phy_dev, int bank, uint16_t reg, uint16_t *val);
+int brcm_shadow_write(phy_dev_t *phy_dev, int bank, uint16_t reg, uint16_t val);
+
+int brcm_exp_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val);
+int brcm_exp_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val);
+
+int brcm_rdb_set(phy_dev_t *phy_dev, int enable);
+int brcm_rdb_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val);
+int brcm_rdb_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val);
+
+int brcm_egphy_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val);
+int brcm_egphy_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val);
+
+int brcm_egphy_force_auto_mdix_set(phy_dev_t *phy_dev, int enable);
+int brcm_egphy_force_auto_mdix_get(phy_dev_t *phy_dev, int *enable);
+
+int brcm_egphy_eth_wirespeed_get(phy_dev_t *phy_dev, int *enable);
+int brcm_egphy_eth_wirespeed_set(phy_dev_t *phy_dev, int enable);
+
+int brcm_egphy_apd_get(phy_dev_t *phy_dev, int *enable);
+int brcm_egphy_apd_set(phy_dev_t *phy_dev, int enable);
+
+int brcm_egphy_eee_get(phy_dev_t *phy_dev, int *enable);
+int brcm_egphy_eee_set(phy_dev_t *phy_dev, int enable);
+int brcm_egphy_eee_resolution_get(phy_dev_t *phy_dev, int *enable);
+
+int brcm_ephy_apd_get(phy_dev_t *phy_dev, int *enable);
+int brcm_ephy_apd_set(phy_dev_t *phy_dev, int enable);
+int brcm_ephy_eee_get(phy_dev_t *phy_dev, int *enable);
+int brcm_ephy_eee_set(phy_dev_t *phy_dev, int enable);
+int brcm_ephy_eee_resolution_get(phy_dev_t *phy_dev, int *enable);
+
+int brcm_shadow_18_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val);
+int brcm_shadow_18_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val);
+int brcm_shadow_1c_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val);
+int brcm_shadow_1c_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val);
+
+int brcm_shadow_18_force_auto_mdix_set(phy_dev_t *phy_dev, int enable);
+int brcm_shadow_18_force_auto_mdix_get(phy_dev_t *phy_dev, int *enable);
+
+int brcm_shadow_18_eth_wirespeed_get(phy_dev_t *phy_dev, int *enable);
+int brcm_shadow_18_eth_wirespeed_set(phy_dev_t *phy_dev, int enable);
+
+int brcm_shadow_1c_apd_get(phy_dev_t *phy_dev, int *enable);
+int brcm_shadow_1c_apd_set(phy_dev_t *phy_dev, int enable);
+int brcm_shadow_rgmii_init(phy_dev_t *phy_dev);
+
+int brcm_loopback_set(phy_dev_t *phy_dev, int enable, phy_speed_t speed);
+int brcm_loopback_get(phy_dev_t *phy_dev, int *enable, phy_speed_t *speed);
+
+#endif
+
diff --git a/drivers/net/bcmbca/phy/phy_drv_ext1.c b/drivers/net/bcmbca/phy/phy_drv_ext1.c
new file mode 100644
index 0000000000..9d3bf4f7df
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_ext1.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Phy driver for external 1G phys: BCM5461S, BCM54810
+ */
+
+#include "bus_drv.h"
+#include "phy_drv.h"
+#include "phy_drv_mii.h"
+#include "phy_drv_brcm.h"
+
+static int _phy_init(phy_dev_t *phy_dev)
+{
+    int ret;
+
+    /* Access IEEE register set instead of LRE */
+    if ((ret = phy_bus_write(phy_dev, 0x0e, 0x06)))
+        goto Exit;
+
+    if ((ret = mii_init(phy_dev)))
+        goto Exit;
+
+    /* Disable BroadR-Reach function */
+    if ((ret = brcm_exp_write(phy_dev, 0x90, 0x00)))
+        goto Exit;
+
+    if ((phy_dev->mii_type == PHY_MII_TYPE_RGMII) && (ret = brcm_shadow_rgmii_init(phy_dev)))
+        goto Exit;
+
+    if ((ret = brcm_shadow_18_force_auto_mdix_set(phy_dev, 1)))
+        goto Exit;
+
+    if ((ret = brcm_shadow_18_eth_wirespeed_set(phy_dev, 1)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+phy_drv_t phy_drv_ext1 =
+{
+    .phy_type = PHY_TYPE_EXT1,
+    .name = "EXT1",
+    .power_get = mii_power_get,
+    .power_set = mii_power_set,
+    .apd_get = brcm_shadow_1c_apd_get,
+    .apd_set = brcm_shadow_1c_apd_set,
+    .read_status = brcm_read_status,
+    .speed_set = mii_speed_set,
+    .caps_get = mii_caps_get,
+    .caps_set = mii_caps_set,
+    .phyid_get = mii_phyid_get,
+    .auto_mdix_set = brcm_shadow_18_force_auto_mdix_set,
+    .auto_mdix_get = brcm_shadow_18_force_auto_mdix_get,
+    .wirespeed_set = brcm_shadow_18_eth_wirespeed_set,
+    .wirespeed_get = brcm_shadow_18_eth_wirespeed_get,
+    .init = _phy_init,
+};
diff --git a/drivers/net/bcmbca/phy/phy_drv_ext2.c b/drivers/net/bcmbca/phy/phy_drv_ext2.c
new file mode 100644
index 0000000000..c85d14a9c7
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_ext2.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Phy driver for external 1G phy: BCM50210, BCM54210
+ */
+
+#include "bus_drv.h"
+#include "phy_drv.h"
+#include "phy_drv_mii.h"
+#include "phy_drv_brcm.h"
+
+#define MODE_CTRL           0x0021 /* Mode Control */
+#define COPPER_MISC_CTRL    0x002f /* Copper Miscellaneous Control */
+#define CLOCK_ALIGN_CTRL    0x0013 /* Clock Alignment Control Regsiter */
+
+static int _phy_access_sgmii_registers(phy_dev_t *phy_dev, int enable)
+{
+    uint16_t val;
+    int ret;
+
+    if ((ret = phy_dev_read(phy_dev, RDB_ACCESS | MODE_CTRL, &val)))
+        goto Exit;
+
+    if (enable)
+        val |= (1 << 0); /* Select SGMII overlay registers */
+    else
+        val &= ~(1 << 0); /* Select copper overlay registers */
+
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | MODE_CTRL, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_sgmii_init(phy_dev_t *phy_dev)
+{
+    uint16_t val = 0x1140;
+    int ret;
+
+    /* Select SGMII overlay registers */
+    if ((ret = _phy_access_sgmii_registers(phy_dev, 1)))
+        goto Exit;
+
+    /* Initialize the SGMII Control register */
+    if ((ret = phy_dev_write(phy_dev, MII_BMCR, val)))
+        goto Exit;
+
+    /* Select copper overlay registers */
+    if ((ret = _phy_access_sgmii_registers(phy_dev, 0)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_rgmii_init(phy_dev_t *phy_dev)
+{
+    uint16_t val;
+    int ret;
+
+    /* Copper Miscellaneous Control */
+    if ((ret = phy_dev_read(phy_dev, RDB_ACCESS | COPPER_MISC_CTRL, &val)))
+        goto Exit;
+
+    val |= (1 << 5); /* Disable RGMII Out of Band Status */;
+    val |= (1 << 7); /* Enable RGMII interface */
+
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | COPPER_MISC_CTRL, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_set_delay(phy_dev_t *phy_dev)
+{
+    uint16_t val;
+    int ret;
+
+    /* Copper Miscellaneous Control */
+    if ((ret = phy_dev_read(phy_dev, RDB_ACCESS | COPPER_MISC_CTRL, &val)))
+        goto Exit;
+
+    if (phy_dev->delay_rx)
+        val |= (1 << 8); /* Enable RGMII RXC delay */
+    else
+        val &= ~(1 << 8); /* Disable RGMII RXC delay */
+
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | COPPER_MISC_CTRL, val)))
+        goto Exit;
+
+    /* Clock Alignment Control Regsiter */
+    if ((ret = phy_dev_read(phy_dev, RDB_ACCESS | CLOCK_ALIGN_CTRL, &val)))
+        goto Exit;
+
+    if (phy_dev->delay_tx)
+        val |= (1 << 9); /* Enable GTXCLK delay */
+    else
+        val &= ~(1 << 9); /* Disable GTXCLK delay */
+
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | CLOCK_ALIGN_CTRL, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_mode_select(phy_dev_t *phy_dev)
+{
+    uint16_t val;
+    int ret;
+
+    /* Mode Control */
+    if ((ret = phy_dev_read(phy_dev, RDB_ACCESS | MODE_CTRL, &val)))
+        goto Exit;
+
+    val &= ~(3 << 1); /* Clear Mode select bits */
+
+    if (phy_dev->mii_type == PHY_MII_TYPE_RGMII)
+        val |= (0 << 1); /* RGMII to Copper */
+    if (phy_dev->mii_type == PHY_MII_TYPE_SGMII)
+        val |= (2 << 1); /* SGMII to Copper */
+
+    if ((ret = phy_dev_write(phy_dev, RDB_ACCESS | MODE_CTRL, val)))
+        goto Exit;
+
+    /* Enable SGMII auto-negotiation */
+    if ((phy_dev->mii_type == PHY_MII_TYPE_SGMII) && (ret = _phy_sgmii_init(phy_dev)))
+        goto Exit;
+
+    /* Enable RGMII interface */
+    if ((phy_dev->mii_type == PHY_MII_TYPE_RGMII) && (ret = _phy_rgmii_init(phy_dev)))
+        goto Exit;
+
+    /* Restart auto-negotiation */
+    if ((ret = phy_dev_read(phy_dev, MII_BMCR, &val)))
+        goto Exit;
+
+    val |= (1 << 12); /* Enable auto negotiation */
+    val |= (1 << 9); /* Restart auto negotiation */
+
+    if ((ret = phy_dev_write(phy_dev, MII_BMCR, val)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_init(phy_dev_t *phy_dev)
+{
+    int ret;
+
+    if ((ret = mii_init(phy_dev)))
+        goto Exit;
+
+    if ((ret = _phy_set_delay(phy_dev)))
+        goto Exit;
+
+    if ((ret = _phy_mode_select(phy_dev)))
+        goto Exit;
+
+    if ((ret = brcm_egphy_force_auto_mdix_set(phy_dev, 1)))
+        goto Exit;
+
+    if ((ret = brcm_egphy_eth_wirespeed_set(phy_dev, 1)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+phy_drv_t phy_drv_ext2 =
+{
+    .phy_type = PHY_TYPE_EXT2,
+    .name = "EXT2",
+    .read = brcm_egphy_read,
+    .write = brcm_egphy_write,
+    .power_get = mii_power_get,
+    .power_set = mii_power_set,
+    .apd_get = brcm_egphy_apd_get,
+    .apd_set = brcm_egphy_apd_set,
+    .eee_get = brcm_egphy_eee_get,
+    .eee_set = brcm_egphy_eee_set,
+    .eee_resolution_get = brcm_egphy_eee_resolution_get,
+    .read_status = brcm_read_status,
+    .speed_set = mii_speed_set,
+    .caps_get = mii_caps_get,
+    .caps_set = mii_caps_set,
+    .auto_mdix_set = brcm_egphy_force_auto_mdix_set,
+    .auto_mdix_get = brcm_egphy_force_auto_mdix_get,
+    .wirespeed_set = brcm_egphy_eth_wirespeed_set,
+    .wirespeed_get = brcm_egphy_eth_wirespeed_get,
+    .phyid_get = mii_phyid_get,
+    .init = _phy_init,
+};
diff --git a/drivers/net/bcmbca/phy/phy_drv_ext3.c b/drivers/net/bcmbca/phy/phy_drv_ext3.c
new file mode 100644
index 0000000000..e3e0167013
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_ext3.c
@@ -0,0 +1,2156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Jan 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Phy driver for external 1G/2.5G/5G/10G phys: BCM8486x, BCM8488x, BCM8489x, BCM5499x
+ */
+
+#include "phy_drv.h"
+#include "phy_drv_mii.h"
+#ifdef MACSEC_SUPPORT
+#include "phy_macsec_api.h"
+#endif
+
+typedef struct firmware_s firmware_t;
+typedef struct phy_desc_s phy_desc_t;
+
+struct firmware_s {
+    char *version;
+    uint32_t *data;
+    uint32_t size;
+    int (*load)(firmware_t *firmware);
+    uint32_t map;
+    uint8_t macsec_capable;
+};
+
+struct phy_desc_s {
+    uint16_t phyid1;
+    uint16_t phyid2;
+    char *name;
+    firmware_t *firmware;
+    uint32_t inter_phy_types;
+};
+
+#ifndef CONFIG_BCM_SELECTIVE_PHYS
+#define CONFIG_BCM_PHY_MAKO_A0
+#define CONFIG_BCM_PHY_ORCA_A0
+#define CONFIG_BCM_PHY_ORCA_B0
+#define CONFIG_BCM_PHY_BLACKFIN_A0
+#define CONFIG_BCM_PHY_BLACKFIN_B0
+#define CONFIG_BCM_PHY_LONGFIN_A0 
+#define CONFIG_BCM_PHY_LONGFIN_B0 
+#endif
+
+#if defined(CONFIG_BCM_PHY_MAKO_A0)
+static int load_mako(firmware_t *firmware);
+#endif
+#if defined(CONFIG_BCM_PHY_ORCA_A0) || defined(CONFIG_BCM_PHY_ORCA_B0)
+static int load_orca(firmware_t *firmware);
+#endif
+#if defined(CONFIG_BCM_PHY_BLACKFIN_A0) || defined(CONFIG_BCM_PHY_BLACKFIN_B0) || defined(CONFIG_BCM_PHY_LONGFIN_A0) || defined(CONFIG_BCM_PHY_LONGFIN_B0)
+static int load_blackfin(firmware_t *firmware);
+#endif
+
+#ifdef CONFIG_BCM_PHY_MAKO_A0
+#include "mako_a0_firmware.h"
+firmware_t mako_a0 = { mako_a0_version, mako_a0_firmware, sizeof(mako_a0_firmware), &load_mako, 0, 0 };
+#endif
+#ifdef CONFIG_BCM_PHY_ORCA_A0
+#include "orca_a0_firmware.h"
+firmware_t orca_a0 = { orca_a0_version, orca_a0_firmware, sizeof(orca_a0_firmware), &load_orca, 0, 0 };
+#endif
+#ifdef CONFIG_BCM_PHY_ORCA_B0
+#include "orca_b0_firmware.h"
+firmware_t orca_b0 = { orca_b0_version, orca_b0_firmware, sizeof(orca_b0_firmware), &load_orca, 0, 0 };
+#endif
+#ifdef CONFIG_BCM_PHY_BLACKFIN_A0 
+#include "blackfin_a0_firmware.h"
+firmware_t blackfin_a0 = { blackfin_a0_version, blackfin_a0_firmware, sizeof(blackfin_a0_firmware), &load_blackfin, 0, 0 };
+#endif
+#ifdef CONFIG_BCM_PHY_BLACKFIN_B0 
+#include "blackfin_b0_firmware.h"
+firmware_t blackfin_b0 = { blackfin_b0_version, blackfin_b0_firmware, sizeof(blackfin_b0_firmware), &load_blackfin, 0, 0 };
+#endif
+#if defined(CONFIG_BCM_PHY_LONGFIN_A0) || defined(CONFIG_BCM_PHY_LONGFIN_B0)
+// longfin A0 and B0 use same firmware dated April 2020 or later 
+#include "longfin_a0_firmware.h"
+firmware_t longfin_a0 = { longfin_a0_version, longfin_a0_firmware, sizeof(longfin_a0_firmware), &load_blackfin, 0, 1 };
+#endif
+
+static firmware_t *firmware_list[] = {
+#ifdef CONFIG_BCM_PHY_MAKO_A0
+    &mako_a0,
+#endif
+#ifdef CONFIG_BCM_PHY_ORCA_A0
+    &orca_a0,
+#endif
+#ifdef CONFIG_BCM_PHY_ORCA_B0
+    &orca_b0,
+#endif
+#ifdef CONFIG_BCM_PHY_BLACKFIN_A0 
+    &blackfin_a0,
+#endif
+#ifdef CONFIG_BCM_PHY_BLACKFIN_B0 
+    &blackfin_b0,
+#endif
+#if defined(CONFIG_BCM_PHY_LONGFIN_A0) || defined(CONFIG_BCM_PHY_LONGFIN_B0)
+    &longfin_a0,
+#endif
+};
+
+static phy_desc_t phy_desc[] = {
+#ifdef CONFIG_BCM_PHY_MAKO_A0
+    { 0xae02, 0x5048, "84860    A0", &mako_a0, INTER_PHY_TYPES_S2P5XI5XI_M },
+    { 0xae02, 0x5040, "84861    A0", &mako_a0, INTER_PHY_TYPES_S2P5XI5XI_M },
+#endif
+#ifdef CONFIG_BCM_PHY_ORCA_A0
+    { 0xae02, 0x5158, "84880    A0", &orca_a0, INTER_PHY_TYPES_US2P5XI5XI_M },
+    { 0xae02, 0x5150, "84881    A0", &orca_a0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+    { 0xae02, 0x5148, "84884    A0", &orca_a0, INTER_PHY_TYPES_US2P5XI5XI_M },
+    { 0xae02, 0x5168, "84884E   A0", &orca_a0, INTER_PHY_TYPES_US2P5XI5XI_M },
+    { 0xae02, 0x5178, "84885    A0", &orca_a0, INTER_PHY_TYPES_US2P5XI5XI_M },
+    { 0xae02, 0x5170, "84886    A0", &orca_a0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+    { 0xae02, 0x5144, "84887    A0", &orca_a0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+    { 0xae02, 0x5140, "84888    A0", &orca_a0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+    { 0xae02, 0x5160, "84888E   A0", &orca_a0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+    { 0xae02, 0x5174, "84888S   A0", &orca_a0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+#endif
+#ifdef CONFIG_BCM_PHY_ORCA_B0
+    { 0xae02, 0x5159, "84880    B0", &orca_b0, INTER_PHY_TYPES_US2P5XI5XI_M },
+    { 0xae02, 0x5151, "84881    B0", &orca_b0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+    { 0xae02, 0x5149, "84884    B0", &orca_b0, INTER_PHY_TYPES_US2P5XI5XI_M },
+    { 0xae02, 0x5169, "84884E   B0", &orca_b0, INTER_PHY_TYPES_US2P5XI5XI_M },
+    { 0xae02, 0x5179, "84885    B0", &orca_b0, INTER_PHY_TYPES_US2P5XI5XI_M },
+    { 0xae02, 0x5171, "84886    B0", &orca_b0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+    { 0xae02, 0x5145, "84887    B0", &orca_b0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+    { 0xae02, 0x5141, "84888    B0", &orca_b0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+    { 0xae02, 0x5161, "84888E   B0", &orca_b0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+    { 0xae02, 0x5175, "84888S   B0", &orca_b0, INTER_PHY_TYPES_US2P5XI5XI10R_M },
+#endif
+#ifdef CONFIG_BCM_PHY_BLACKFIN_A0
+    { 0x3590, 0x5090, "84891    A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x5094, "54991    A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR_M },
+    { 0x3590, 0x5098, "54991E   A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR_M },
+    { 0x3590, 0x5080, "84891L   A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x5084, "54991L   A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR_M },
+    { 0x3590, 0x5088, "54991EL  A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR_M },
+    { 0x3590, 0x50a0, "84892    A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x50a4, "54992    A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR_M },
+    { 0x3590, 0x50a8, "54992E   A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR_M },
+    { 0x3590, 0x50b0, "84894    A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x50b4, "54994    A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR_M },
+    { 0x3590, 0x50b8, "54994E   A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR_M },
+    { 0x3590, 0x50d0, "54991H   A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x50f0, "54994H   A0", &blackfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+#endif
+#ifdef CONFIG_BCM_PHY_BLACKFIN_B0
+    { 0x3590, 0x5091, "84891    B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x5095, "54991    B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR5XIR_M },
+    { 0x3590, 0x5099, "54991E   B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR_M },
+    { 0x3590, 0x5081, "84891L   B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x5085, "54991L   B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR5XIR_M },
+    { 0x3590, 0x5089, "54991EL  B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR_M },
+    { 0x3590, 0x50a1, "84892    B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x50a5, "54992    B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR5XIR_M },
+    { 0x3590, 0x50a9, "54992E   B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR_M },
+    { 0x3590, 0x50b1, "84894    B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x50b5, "54994    B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR5XIR_M },
+    { 0x3590, 0x50b9, "54994E   B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR_M },
+    { 0x3590, 0x50d1, "54991H   B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x50f1, "54994H   B0", &blackfin_b0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+#endif
+#ifdef CONFIG_BCM_PHY_LONGFIN_A0
+    { 0x3590, 0x5180, "84891LM  A0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x5184, "54991LM  A0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x5190, "84891M   A0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x5194, "54991M   A0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR_M },
+    { 0x3590, 0x5198, "54991EM  A0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR_M },
+    { 0x3590, 0x5188, "54991ELM A0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR_M },
+#endif
+#ifdef CONFIG_BCM_PHY_LONGFIN_B0
+    { 0x3590, 0x5181, "84891LM  B0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x5185, "54991LM  B0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x5191, "84891M   B0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR10R_M },
+    { 0x3590, 0x5195, "54991M   B0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR5XIR_M },
+    { 0x3590, 0x5199, "54991EM  B0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR_M },
+    { 0x3590, 0x5189, "54991ELM B0", &longfin_a0, INTER_PHY_TYPES_US2P5XIR_M },
+#endif
+};
+
+static uint32_t enabled_phys;
+static uint32_t macsec_phys;
+bus_drv_t *bus_drv;
+
+#define BUS_WRITE(a, b, c, d)       if ((ret = _bus_write(a, b, c, d))) goto Exit;
+#define BUS_WRITE_ALL(a, b, c, d)   if ((ret = _bus_write_all(a, b, c, d))) goto Exit;
+#define BUS_WRITE_AND_VERIFY_ALL(a, b, c, d, e)   if ((ret = _bus_write_and_verify_all(a, b, c, d, e))) goto Exit;
+
+#define PHY_READ(a, b, c, d)        if ((ret = phy_bus_c45_read(a, b, c, d))) goto Exit;
+#define PHY_WRITE(a, b, c, d)       if ((ret = phy_bus_c45_write(a, b, c, d))) goto Exit;
+
+/* Command codes */
+#define CMD_GET_PAIR_SWAP                           0x8000
+#define CMD_SET_PAIR_SWAP                           0x8001
+#define CMD_GET_1588_ENABLE                         0x8004
+#define CMD_SET_1588_ENABLE                         0x8005
+#define CMD_GET_SHORT_REACH_MODE_ENABLE             0x8006
+#define CMD_SET_SHORT_REACH_MODE_ENABLE             0x8007
+#define CMD_GET_EEE_MODE                            0x8008
+#define CMD_SET_EEE_MODE                            0x8009
+#define CMD_GET_EMI_MODE_ENABLE                     0x800A
+#define CMD_SET_EMI_MODE_ENABLE                     0x800B
+#define CMD_GET_SUB_LF_RF_STATUS                    0x800D
+#define CMD_GET_SERDES_KR_MODE_ENABLE               0x800E
+#define CMD_SET_SERDES_KR_MODE_ENABLE               0x800F
+#define CMD_CLEAR_SUB_LF_RF                         0x8010
+#define CMD_SET_SUB_LF_RF                           0x8011
+#define CMD_READ_INDIRECT_GPHY_REG_BITS             0x8014
+#define CMD_WRITE_INDIRECT_GPHY_REG_BITS            0x8015
+#define CMD_GET_XFI_2P5G_5G_MODE                    0x8016
+#define CMD_SET_XFI_2P5G_5G_MODE                    0x8017
+#define CMD_GET_TWO_PAIR_1G_MODE                    0x8018
+#define CMD_SET_TWO_PAIR_1G_MODE                    0x8019
+#define CMD_SET_EEE_STATISTICS                      0x801A
+#define CMD_GET_EEE_STATISTICS                      0x801B
+#define CMD_SET_JUMBO_PACKET                        0x801C
+#define CMD_GET_JUMBO_PACKET                        0x801D
+#define CMD_GET_MSE                                 0x801E
+#define CMD_GET_PAUSE_FRAME_MODE                    0x801F
+#define CMD_SET_PAUSE_FRAME_MODE                    0x8020
+#define CMD_GET_LED_TYPE                            0x8021
+#define CMD_SET_LED_TYPE                            0x8022
+#define CMD_GET_MGBASE_T_802_3BZ_TYPE               0x8023
+#define CMD_SET_MGBASE_T_802_3BZ_TYPE               0x8024
+#define CMD_GET_MSE_GPHY                            0x8025
+#define CMD_SET_USXGMII                             0x8026
+#define CMD_GET_USXGMII                             0x8027
+#define CMD_GET_XL_MODE                             0x8029
+#define CMD_SET_XL_MODE                             0x802A
+#define CMD_GET_XFI_TX_FILTERS                      0x802B
+#define CMD_SET_XFI_TX_FILTERS                      0x802C
+#define CMD_GET_XFI_POLARITY                        0x802D
+#define CMD_SET_XFI_POLARITY                        0x802E
+#define CMD_GET_CURRENT_VOLTAGE                     0x802F
+#define CMD_GET_SNR                                 0x8030
+#define CMD_GET_CURRENT_TEMP                        0x8031
+#define CMD_SET_UPPER_TEMP_WARNING_LEVEL            0x8032
+#define CMD_GET_UPPER_TEMP_WARNING_LEVEL            0x8033
+#define CMD_SET_LOWER_TEMP_WARNING_LEVEL            0x8034
+#define CMD_GET_LOWER_TEMP_WARNING_LEVEL            0x8035
+#define CMD_GET_HW_FR_EMI_MODE_ENABLE               0x803A
+#define CMD_SET_HW_FR_EMI_MODE_ENABLE               0x803B
+#define CMD_GET_CUSTOMER_REQUESTED_TX_PWR_ADJUST    0x8040
+#define CMD_SET_CUSTOMER_REQUESTED_TX_PWR_ADJUST    0x8041
+#define CMD_GET_DYNAMIC_PARTITION_SELECT            0x8042
+#define CMD_SET_DYNAMIC_PARTITION_SELECT            0x8043
+#define CMD_RESET_STAT_LOG                          0xC017
+
+/* Command hanlder status codes */
+#define CMD_RECEIVED                                0x0001
+#define CMD_IN_PROGRESS                             0x0002
+#define CMD_COMPLETE_PASS                           0x0004
+#define CMD_COMPLETE_ERROR                          0x0008
+#define CMD_SYSTEM_BUSY                             0xBBBB
+
+/* Fixups for 5499x phys */
+#define ID1_5499X                                   0x35900000
+#define ID1_MASK                                    0xffff0000
+#define SUPER_I_DEFAULT                             (1<<15)
+#define SUPER_I_BLACKFIN                            (1<<8)
+#define CHANGE_STRAP_STATUS                         (1<<1)
+
+static int _wait_for_cmd_ready(phy_dev_t *phy_dev)
+{ 
+    int ret, i;
+    uint16_t val;
+
+    for (i = 0; i < 1000; i++)
+    {
+        /* Read status of command */
+        PHY_READ(phy_dev, 0x1e, 0x4037, &val);
+
+        if (val != CMD_IN_PROGRESS && val != CMD_SYSTEM_BUSY)
+            return 0;
+
+        udelay(2000);
+    }
+
+    printk("Timed out waiting for command ready");
+
+Exit:
+    return -1;
+}
+
+static uint16_t _wait_for_cmd_complete(phy_dev_t *phy_dev)
+{ 
+    int ret, i;
+    uint16_t val = 0;
+
+    for (i = 0; i < 1000; i++)
+    {
+        /* Read status of command */
+        PHY_READ(phy_dev, 0x1e, 0x4037, &val);
+
+        if (val == CMD_COMPLETE_PASS || val == CMD_COMPLETE_ERROR)
+            goto Exit;
+
+        udelay(2000);
+    }
+
+    printk("Timed out waiting for command complete\n");
+
+Exit:
+    return val;
+}
+
+static int cmd_handler(phy_dev_t *phy_dev, uint16_t cmd_code, uint16_t *data1, uint16_t *data2, uint16_t *data3, uint16_t *data4, uint16_t *data5)
+{
+    int ret;
+    uint16_t cmd_status = 0;
+
+    /* Make sure command interface is open */
+    if ((ret = _wait_for_cmd_ready(phy_dev)))
+        goto Exit;
+
+    switch (cmd_code)
+    {
+    case CMD_SET_PAIR_SWAP:
+    case CMD_SET_1588_ENABLE:
+    case CMD_SET_SHORT_REACH_MODE_ENABLE:
+    case CMD_SET_EEE_MODE:
+    case CMD_SET_EMI_MODE_ENABLE:
+    case CMD_SET_SERDES_KR_MODE_ENABLE:
+    case CMD_CLEAR_SUB_LF_RF:
+    case CMD_SET_SUB_LF_RF:
+    case CMD_WRITE_INDIRECT_GPHY_REG_BITS:
+    case CMD_SET_XFI_2P5G_5G_MODE:
+    case CMD_SET_TWO_PAIR_1G_MODE:
+    case CMD_SET_PAUSE_FRAME_MODE:
+    case CMD_SET_LED_TYPE:
+    case CMD_SET_MGBASE_T_802_3BZ_TYPE:
+    case CMD_SET_USXGMII:
+    case CMD_SET_EEE_STATISTICS:
+    case CMD_SET_JUMBO_PACKET:
+    case CMD_SET_XL_MODE:
+    case CMD_SET_XFI_TX_FILTERS:
+    case CMD_SET_XFI_POLARITY:
+    case CMD_SET_UPPER_TEMP_WARNING_LEVEL:
+    case CMD_SET_LOWER_TEMP_WARNING_LEVEL:
+    case CMD_SET_HW_FR_EMI_MODE_ENABLE:
+    case CMD_SET_CUSTOMER_REQUESTED_TX_PWR_ADJUST:
+    case CMD_SET_DYNAMIC_PARTITION_SELECT:
+    {
+        if (data1)
+            PHY_WRITE(phy_dev, 0x1e, 0x4038, *data1);
+        if (data2)
+            PHY_WRITE(phy_dev, 0x1e, 0x4039, *data2);
+        if (data3)
+            PHY_WRITE(phy_dev, 0x1e, 0x403a, *data3);
+        if (data4)
+            PHY_WRITE(phy_dev, 0x1e, 0x403b, *data4);
+        if (data5)
+            PHY_WRITE(phy_dev, 0x1e, 0x403c, *data5);
+
+        PHY_WRITE(phy_dev, 0x1e, 0x4005, cmd_code);
+        cmd_status = _wait_for_cmd_complete(phy_dev);
+
+        break;
+    }
+    case CMD_GET_PAIR_SWAP:
+    case CMD_GET_1588_ENABLE:
+    case CMD_GET_SHORT_REACH_MODE_ENABLE:
+    case CMD_GET_EEE_MODE:
+    case CMD_GET_EMI_MODE_ENABLE:
+    case CMD_GET_SERDES_KR_MODE_ENABLE:
+    case CMD_GET_SUB_LF_RF_STATUS:
+    case CMD_GET_XFI_2P5G_5G_MODE:
+    case CMD_GET_TWO_PAIR_1G_MODE:
+    case CMD_GET_PAUSE_FRAME_MODE:
+    case CMD_GET_LED_TYPE:
+    case CMD_GET_MGBASE_T_802_3BZ_TYPE:
+    case CMD_GET_MSE_GPHY:
+    case CMD_GET_USXGMII:
+    case CMD_GET_JUMBO_PACKET:
+    case CMD_GET_MSE:
+    case CMD_GET_XL_MODE:
+    case CMD_GET_XFI_TX_FILTERS:
+    case CMD_GET_XFI_POLARITY:
+    case CMD_GET_CURRENT_VOLTAGE:
+    case CMD_GET_SNR:
+    case CMD_GET_CURRENT_TEMP:
+    case CMD_GET_UPPER_TEMP_WARNING_LEVEL:
+    case CMD_GET_LOWER_TEMP_WARNING_LEVEL:
+    case CMD_GET_HW_FR_EMI_MODE_ENABLE:
+    case CMD_GET_CUSTOMER_REQUESTED_TX_PWR_ADJUST:
+    case CMD_GET_DYNAMIC_PARTITION_SELECT:
+    case CMD_RESET_STAT_LOG:
+    {
+        PHY_WRITE(phy_dev, 0x1e, 0x4005, cmd_code);
+        cmd_status = _wait_for_cmd_complete(phy_dev);
+
+        if (data1)
+            PHY_READ(phy_dev, 0x1e, 0x4038, data1);
+        if (data2)
+            PHY_READ(phy_dev, 0x1e, 0x4039, data2);
+        if (data3)
+            PHY_READ(phy_dev, 0x1e, 0x403a, data3);
+        if (data4)
+            PHY_READ(phy_dev, 0x1e, 0x403b, data4);
+        if (data5)
+            PHY_READ(phy_dev, 0x1e, 0x403c, data5);
+
+        break;
+    }
+    case CMD_READ_INDIRECT_GPHY_REG_BITS:
+    {
+        if (data1)
+            PHY_WRITE(phy_dev, 0x1e, 0x4038, *data1);
+        if (data2)
+            PHY_WRITE(phy_dev, 0x1e, 0x4039, *data2);
+        if (data3)
+            PHY_WRITE(phy_dev, 0x1e, 0x403a, *data3);
+        if (data4)
+            PHY_WRITE(phy_dev, 0x1e, 0x403b, *data4);
+
+        PHY_WRITE(phy_dev, 0x1e, 0x4005, cmd_code);
+        cmd_status = _wait_for_cmd_complete(phy_dev);
+
+        if (data5)
+            PHY_READ(phy_dev, 0x1e, 0x403c, data5);
+
+        break;
+    }
+    case CMD_GET_EEE_STATISTICS:
+    {
+        if (data1)
+            PHY_WRITE(phy_dev, 0x1e, 0x4038, *data1);
+
+        PHY_WRITE(phy_dev, 0x1e, 0x4005, cmd_code);
+        cmd_status = _wait_for_cmd_complete(phy_dev);
+
+        if (data2)
+            PHY_READ(phy_dev, 0x1e, 0x4039, data2);
+        if (data3)
+            PHY_READ(phy_dev, 0x1e, 0x403a, data3);
+        if (data4)
+            PHY_READ(phy_dev, 0x1e, 0x403b, data4);
+        if (data5)
+            PHY_READ(phy_dev, 0x1e, 0x403c, data5);
+
+        break;
+    }
+    default:
+        printk("Unsupported cmd code: 0x%x\n", cmd_code);
+        break;
+    }
+
+    if (cmd_status != CMD_COMPLETE_PASS)
+    {
+        printk("Failed to execute cmd code: 0x%x\n", cmd_code);
+        return -1;
+    }
+
+Exit:
+    return ret;
+}
+
+static int _phy_power_get(phy_dev_t *phy_dev, int *enable)
+{
+    uint16_t val;
+    int ret;
+
+    PHY_READ(phy_dev, 0x01, 0x0000, &val);
+
+    *enable = (val & (1 << 11)) ? 0 : 1;
+
+Exit:
+    return ret;
+}
+
+static int _phy_power_set(phy_dev_t *phy_dev, int enable)
+{
+    uint16_t val;
+    int ret;
+
+    PHY_READ(phy_dev, 0x01, 0x0000, &val);
+
+    if (enable)
+        val &= ~(1 << 11); /* Power up */
+    else
+        val |= (1 << 11); /* Power down */
+
+    PHY_WRITE(phy_dev, 0x01, 0x0000, val);
+
+Exit:
+    return ret;
+}
+
+#define XFI_MODE_IDLE_STUFFING           0 /* Idle Stuffing mode over XFI interface */
+#define XFI_MODE_BASE_X                  1 /* 2.5GBase-X or 5GBase-X */                  
+#define XFI_MODE_BASE_R                  2 /* 2.5GBase-R or 5GBase-R */                  
+
+static int _phy_idle_stuffing_mode_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t data1; /* XFI mode in 2.5G speed */
+    uint16_t data2; /* XFI mode in 5G speed */
+
+    /* In current implementation, 2.5G mode is always Base-X and 5G mode is idle stuffing if enabled */
+    data1 = XFI_MODE_BASE_X;
+    data2 = enable ? XFI_MODE_IDLE_STUFFING : XFI_MODE_BASE_X;
+
+    /* Set XFI modes for 2.5G and 5G */
+    if ((ret = cmd_handler(phy_dev, CMD_SET_XFI_2P5G_5G_MODE, &data1, &data2, NULL, NULL, NULL)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+static int _phy_led_control_mode_set(phy_dev_t *phy_dev, int user_control)
+{
+    int ret = 0;
+    /* uint16_t val = user_control ? 1 : 0; */
+
+    /* Set led control to user or firmware */
+    /*if ((ret = cmd_handler(phy_dev, CMD_SET_LED_TYPE, &val, NULL, NULL, NULL, NULL)))
+        goto Exit;
+
+Exit:*/
+    return ret;
+}
+
+static int _inter_phy_types_set(phy_dev_t *phy_dev, inter_phy_types_dir_t if_dir, uint32_t types)
+{
+    int rc = 0;
+    uint16_t data1, data2;
+
+    rc = cmd_handler(phy_dev, CMD_GET_XFI_2P5G_5G_MODE, &data1, &data2, NULL, NULL, NULL);
+
+    if (types & (INTER_PHY_TYPE_2P5GIDLE_M))
+        data1 = 0;
+    else if (types & (INTER_PHY_TYPE_2P5GBASE_X_M))
+        data1 = 1;
+    else if (types & (INTER_PHY_TYPE_2P5GBASE_R_M))
+        data1 = 2;
+        
+    if (types & (INTER_PHY_TYPE_5GIDLE_M))
+        data2 = 0;
+    else if (types & (INTER_PHY_TYPE_5GBASE_X_M))
+        data2 = 1;
+    else if (types & (INTER_PHY_TYPE_5GBASE_R_M))
+        data2 = 2;
+        
+    rc += cmd_handler(phy_dev, CMD_SET_XFI_2P5G_5G_MODE, &data1, &data2, NULL, NULL, NULL);
+
+    return rc;
+}
+
+static int _phy_force_auto_mdix_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t val;
+
+    PHY_READ(phy_dev, 0x07, 0x902f, &val);
+    
+    if (enable)
+        val |= (1 << 9); /* Auto-MDIX enabled */
+    else
+        val &= ~(1 << 9); /* Auto-MDIX disabled */
+
+    PHY_WRITE(phy_dev, 0x07, 0x902f, val);
+
+Exit:
+    return ret;
+}
+
+static int _phy_force_auto_mdix_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    PHY_READ(phy_dev, 0x07, 0x902f, &val);
+    
+    *enable = val & (1 << 9) ? 1 : 0; /* Force Auto MDIX Enabled */
+
+Exit:
+    return ret;
+}
+
+static int _phy_eth_wirespeed_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t val;
+
+    PHY_READ(phy_dev, 0x07, 0x902f, &val);
+
+    if (enable)
+        val |= (1 << 4); /* Ethernet@Wirespeed enabled */
+    else
+        val &= ~(1 << 4); /* Ethernet@Wirespeed disabled */
+
+    PHY_WRITE(phy_dev, 0x07, 0x902f, val);
+
+Exit:
+    return ret;
+}
+
+static int _phy_eth_wirespeed_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    PHY_READ(phy_dev, 0x07, 0x902f, &val);
+
+    *enable = val & (1 << 4) ? 1 : 0; /* Ethernet@Wirespeed Enabled */
+
+Exit:
+    return ret;
+}
+
+static int _phy_pair_swap_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t data;
+
+    if (enable)
+        data = 0x1b;
+    else
+        data = 0xe4;
+
+    if ((ret = cmd_handler(phy_dev, CMD_SET_PAIR_SWAP, NULL, &data, NULL, NULL, NULL)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_xfi_polarity_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t data = enable ? 1 : 0;
+    uint16_t type = 0;
+
+    if ((ret = cmd_handler(phy_dev, CMD_SET_XFI_POLARITY, &type, &data, &data, NULL, NULL)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_apd_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    PHY_READ(phy_dev, 0x07, 0x901a, &val);
+    *enable = val & (1 << 5) ? 1 : 0; /* Auto power-down mode enabled */
+
+Exit:
+    return ret;
+}
+
+static int _phy_apd_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t val;
+
+    /* Auto-Power Down */
+    PHY_READ(phy_dev, 0x07, 0x901a, &val);
+
+    if (enable)
+    {
+        val |= (1 << 5); /* Auto power-down mode enabled */
+        val |= (1 << 8); /* Enable energy detect single link pulse */
+    }
+    else
+    {
+        val &= ~(1 << 5); /* Auto power-down mode disabled */
+        val &= ~(1 << 8); /* Disable energy detect single link pulse */
+    }
+
+    PHY_WRITE(phy_dev, 0x07, 0x901a, val);
+
+   /* Reserved Control 3 */
+    PHY_READ(phy_dev, 0x07, 0x9015, &val);
+
+    if (enable)
+    {
+        val |= (1 << 0); /* Disable CLK125 output */
+        val &= ~(1 << 1); /* Enable powering down of dll during auto-power down */
+    }
+    else
+    {
+        val &= ~(1 << 0); /* Enable CLK125 output */
+        val |= (1 << 1); /* Disable powering down of dll during auto-power down */
+    }
+
+    PHY_WRITE(phy_dev, 0x07, 0x9015, val);
+
+Exit:
+    return ret;
+}
+
+static int _phy_eee_mode_get(phy_dev_t *phy_dev, uint16_t *mode);
+
+static int _phy_eee_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    /* local EEE Status */
+    if ((ret = _phy_eee_mode_get(phy_dev, &val)))
+        goto Exit;
+
+    *enable = !!val;
+
+Exit:
+    return ret;
+}
+
+static int _phy_eee_resolution_get(phy_dev_t *phy_dev, int *enable)
+{
+    int ret;
+    uint16_t val;
+
+    /* EEE Resolution Status */
+    PHY_READ(phy_dev, 7, 0x803e, &val);
+
+    /* Check if the link partner auto-negotiated EEE capability */
+    *enable = val & 0x3e ? 1 : 0;
+
+Exit:
+    return ret;
+}
+
+static int _phy_eee_mode_get(phy_dev_t *phy_dev, uint16_t *mode)
+{
+    int ret;
+    uint16_t data1, data2, data3, data4;
+
+    /* Get EEE mode */
+    if ((ret = cmd_handler(phy_dev, CMD_GET_EEE_MODE, &data1, &data2, &data3, &data4, NULL)))
+        goto Exit;
+
+    *mode = data1;
+
+Exit:
+    return ret;
+}
+
+#define EEE_MODE_DISABLED               0 /* EEE Disabled*/
+#define EEE_MODE_NATIVE_EEE             1 /* Native EEE */
+#define EEE_MODE_AUTOGREEEN_FIXED       2 /* AutoGrEEEn Fixed Latency */
+#define EEE_MODE_AUTOGREEEN_VARIABLE    3 /* AutoGrEEEn Variable Latency */
+
+/* Note: AutoGrEEEn mode is not supported when idle stuffing is enabled on 2.5/5G rates */
+
+static int _phy_eee_mode_set(phy_dev_t *phy_dev, uint32_t caps)
+{
+    int ret;
+    uint16_t val = 0, data1, data2, data3, data4;
+    uint8_t mode = EEE_MODE_AUTOGREEEN_FIXED;
+
+    val = 0;
+    mode = 2; /* AutoGrEEEn */
+
+    /* 10G          bits 0:1 */
+    /* 100M/1G      bits 2:3 */
+    /* 2.5G         bits 4:5 */
+    /* 5G           bits 6:7 */
+    val |= ((caps & PHY_CAP_100_HALF) || (caps & PHY_CAP_100_FULL)) ? (mode << 2) : 0;
+    val |= ((caps & PHY_CAP_1000_HALF) || (caps & PHY_CAP_1000_FULL)) ? (mode << 2) : 0;
+    val |= ((caps & PHY_CAP_2500) ? ((data1 == XFI_MODE_IDLE_STUFFING ? EEE_MODE_NATIVE_EEE : mode) << 4) : 0);
+    val |= ((caps & PHY_CAP_5000) ? ((data2 == XFI_MODE_IDLE_STUFFING ? EEE_MODE_NATIVE_EEE : mode) << 6) : 0);
+    val |= ((caps & PHY_CAP_10000)) ? (mode << 0) : 0;
+
+    data1 = val;    /* Bitmap of EEE modes per speed */
+    data2 = 0;      /* AutoGrEEEn High Threshold */
+    data3 = 0x7a12; /* AutoGrEEEn Low Threshold */
+    data4 = 0x0480; /* AutoGrEEEn Latency */
+
+    /* Set EEE mode */
+    if ((ret = cmd_handler(phy_dev, CMD_SET_EEE_MODE, &data1, &data2, &data3, &data4, NULL)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_eee_set(phy_dev_t *phy_dev, int enable)
+{
+    int ret;
+    uint16_t val;
+    uint32_t caps;
+
+    if ((ret = phy_dev_caps_get(phy_dev, CAPS_TYPE_ADVERTISE, &caps)))
+        goto Exit;
+
+    if ((ret = _phy_eee_mode_set(phy_dev, enable ? caps : 0)))
+        goto Exit;
+
+    /* Restart auto negotiation to kick off EEE settings */
+    PHY_READ(phy_dev, 0x07, 0xffe0, &val);
+    val |= (1 << 9);
+    PHY_WRITE(phy_dev, 0x07, 0xffe0, val);
+
+Exit:
+    return ret;
+}
+
+static int _phy_read_status(phy_dev_t *phy_dev)
+{
+    int ret, mode;
+    uint16_t val;
+
+    phy_dev->link = 0;
+    phy_dev->speed = PHY_SPEED_UNKNOWN;
+    phy_dev->duplex = PHY_DUPLEX_UNKNOWN;
+    phy_dev->pause_rx = 0;
+    phy_dev->pause_tx = 0;
+
+    /* Read the status register */
+    PHY_READ(phy_dev, 0x1e, 0x400d, &val);
+
+    /* Copper link status */
+    phy_dev->link = ((val >> 5) & 0x1);
+
+    if (!phy_dev->link)
+        goto Exit;
+
+    /* Copper speed */
+    mode = ((val >> 2) & 0x7);
+
+    if (mode == 0)
+        phy_dev->speed = PHY_SPEED_10;
+    else if (mode == 1)
+        phy_dev->speed = PHY_SPEED_2500;
+    else if (mode == 2)
+        phy_dev->speed = PHY_SPEED_100;
+    else if (mode == 3)
+        phy_dev->speed = PHY_SPEED_5000;
+    else if (mode == 4)
+        phy_dev->speed = PHY_SPEED_1000;
+    else if (mode == 6)
+        phy_dev->speed = PHY_SPEED_10000;
+    else
+        goto Exit;
+
+    /* Read the 1000BASE-T auxiliary status summary register */
+    PHY_READ(phy_dev, 0x07, 0xfff9, &val);
+
+    if (phy_dev->speed > PHY_SPEED_1000)
+    {
+        phy_dev->duplex = PHY_DUPLEX_FULL;
+    }
+    else
+    {
+        mode = ((val >> 8) & 0x7);
+
+        if (mode == 3 || mode == 6)
+            phy_dev->duplex = PHY_DUPLEX_HALF;
+        else if (mode == 5 || mode == 7)
+            phy_dev->duplex = PHY_DUPLEX_FULL;
+    }
+
+    phy_dev->pause_rx = ((val >> 1) & 0x1);
+    phy_dev->pause_tx = ((val >> 0) & 0x1);
+
+Exit:
+    return ret;
+}
+
+int _phy_caps_get(phy_dev_t *phy_dev, int caps_type, uint32_t *pcaps)
+{
+    int ret = 0;
+    uint16_t val = 0;
+    uint32_t caps = 0;
+
+    if ((caps_type != CAPS_TYPE_ADVERTISE) 
+        && (caps_type != CAPS_TYPE_SUPPORTED))
+        goto Exit;
+
+    if (caps_type == CAPS_TYPE_SUPPORTED)
+    {
+        caps |= PHY_CAP_AUTONEG | PHY_CAP_PAUSE | PHY_CAP_PAUSE_ASYM | PHY_CAP_REPEATER;
+        caps |= PHY_CAP_100_HALF | PHY_CAP_100_FULL;
+        caps |= PHY_CAP_1000_HALF | PHY_CAP_1000_FULL;
+        caps |= PHY_CAP_2500 | PHY_CAP_5000  | PHY_CAP_10000;
+
+        *pcaps = caps;
+
+        return 0;
+    }
+
+    /* 1000Base-T/100Base-TX MII control */
+    PHY_READ(phy_dev, 0x07, 0xffe0, &val);
+
+    if (val & (1 << 12))
+        caps |= PHY_CAP_AUTONEG;
+
+    /* Copper auto-negotiation advertisement */
+    PHY_READ(phy_dev, 0x07, 0xffe4, &val);
+
+    if (val & (1 << 10))
+        caps |= PHY_CAP_PAUSE;
+
+    if (val & (1 << 11))
+        caps |= PHY_CAP_PAUSE_ASYM;
+
+    if (val & (1 << 7))
+        caps |= PHY_CAP_100_HALF;
+
+    if (val & (1 << 8))
+        caps |= PHY_CAP_100_FULL;
+
+    /* 1000Base-T control */
+    PHY_READ(phy_dev, 0x07, 0xffe9, &val);
+
+    if (val & (1 << 8))
+        caps |= PHY_CAP_1000_HALF;
+
+    if (val & (1 << 9))
+        caps |= PHY_CAP_1000_FULL;
+
+    if (val & (1 << 10))
+        caps |= PHY_CAP_REPEATER;
+
+    /* 10GBase-T AN control */
+    PHY_READ(phy_dev, 0x07, 0x0020, &val);
+
+    if (val & (1 << 7))
+        caps |= PHY_CAP_2500;
+
+    if (val & (1 << 8))
+        caps |= PHY_CAP_5000;
+
+    if (val & (1 << 12))
+        caps |= PHY_CAP_10000;
+
+    *pcaps = caps;
+
+Exit:
+    return ret;
+}
+
+int _phy_caps_set(phy_dev_t *phy_dev, uint32_t caps)
+{
+    int ret;
+    uint16_t val, mode;
+
+    caps |= PHY_CAP_AUTONEG;
+
+    /* Copper auto-negotiation advertisement */
+    PHY_READ(phy_dev, 0x07, 0xffe4, &val);
+
+    val &= ~((1 << 7) | (1 << 8) | (1 << 10));
+
+    if (caps & PHY_CAP_100_HALF)
+        val |= (1 << 7);
+
+    if (caps & PHY_CAP_100_FULL)
+        val |= (1 << 8);
+
+    if (caps & PHY_CAP_PAUSE)
+        val |= (1 << 10);
+
+    if (caps & PHY_CAP_PAUSE_ASYM)
+        val |= (1 << 11);
+
+    PHY_WRITE(phy_dev, 0x07, 0xffe4, val);
+
+    /* 1000Base-T control */
+    PHY_READ(phy_dev, 0x07, 0xffe9, &val);
+
+    val &= ~((1 << 8) | (1 << 9) | (1 << 10));
+
+    if (caps & PHY_CAP_1000_HALF)
+        val |= (1 << 8);
+
+    if (caps & PHY_CAP_1000_FULL)
+        val |= (1 << 9);
+
+    if (caps & PHY_CAP_REPEATER)
+        val |= (1 << 10);
+
+    PHY_WRITE(phy_dev, 0x07, 0xffe9, val);
+
+    /* 10GBase-T AN control */
+    PHY_READ(phy_dev, 0x07, 0x0020, &val);
+
+    val &= ~((1 << 7) | (1 << 8) | (1 << 12));
+
+    if (caps & PHY_CAP_2500)
+        val |= (1 << 7);
+
+    if (caps & PHY_CAP_5000)
+        val |= (1 << 8);
+
+    if (caps & PHY_CAP_10000)
+        val |= (1 << 12);
+
+    PHY_WRITE(phy_dev, 0x07, 0x0020, val);
+
+    /* 1000Base-T/100Base-TX MII control */
+    PHY_READ(phy_dev, 0x07, 0xffe0, &val);
+
+    val &= ~(1 << 12);
+
+    if (caps & PHY_CAP_AUTONEG)
+        val |= (1 << 12);
+
+    PHY_WRITE(phy_dev, 0x07, 0xffe0, val);
+
+    if (!(caps & PHY_CAP_AUTONEG))
+        goto Exit;
+
+    /* Check if EEE mode is configured */
+    if ((ret = _phy_eee_mode_get(phy_dev, &mode)))
+        goto Exit;
+
+    /* Reset the EEE mode according to the phy capabilites, if it was set before */
+    if (mode && (ret = _phy_eee_mode_set(phy_dev, caps)))
+        goto Exit;
+
+    /* Restart auto negotiation */
+    val |= (1 << 9);
+    PHY_WRITE(phy_dev, 0x07, 0xffe0, val);
+
+Exit:
+    return ret;
+}
+
+static int _phy_speed_set(phy_dev_t *phy_dev, phy_speed_t speed, phy_duplex_t duplex)
+{
+    int ret;
+    uint32_t caps;
+
+    if (speed == PHY_SPEED_UNKNOWN)
+    {
+        speed = PHY_SPEED_10000;
+        duplex = PHY_DUPLEX_FULL;
+    }
+
+    if ((ret = phy_dev_caps_get(phy_dev, CAPS_TYPE_ADVERTISE, &caps)))
+        goto Exit;
+
+    caps &= ~(PHY_CAP_100_HALF | PHY_CAP_100_FULL |
+        PHY_CAP_1000_HALF | PHY_CAP_1000_FULL |
+        PHY_CAP_2500 | PHY_CAP_5000 | PHY_CAP_10000);
+
+    switch (speed)
+    {
+    case PHY_SPEED_10000:
+        caps |= PHY_CAP_10000;
+    case PHY_SPEED_5000:
+        caps |= PHY_CAP_5000;
+    case PHY_SPEED_2500:
+        caps |= PHY_CAP_2500;
+    case PHY_SPEED_1000:
+        caps |= PHY_CAP_1000_HALF | ((duplex == PHY_DUPLEX_FULL) ? PHY_CAP_1000_FULL : 0);
+    case PHY_SPEED_100:
+        caps |= PHY_CAP_100_HALF | ((duplex == PHY_DUPLEX_FULL) ? PHY_CAP_100_FULL : 0);
+        break;
+    default:
+        printk("Ignoring unsupported speed\n");
+        goto Exit;
+        break;
+    }
+
+    if ((ret = phy_dev_caps_set(phy_dev, caps)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+static int _phy_phyid_get(phy_dev_t *phy_dev, uint32_t *phyid)
+{
+    int ret;
+    uint16_t phyid1, phyid2;
+
+    PHY_READ(phy_dev, 0x01, 0x0002, &phyid1);
+    PHY_READ(phy_dev, 0x01, 0x0003, &phyid2);
+
+    *phyid = phyid1 << 16 | phyid2;
+
+Exit:
+    return ret;
+}
+
+static int _phy_super_isolate_5499x(phy_dev_t *phy_dev, int isolate)
+{
+    int ret;
+    uint16_t data;
+
+    /* Read the status register */
+    PHY_READ(phy_dev, 0x1e, 0x401c, &data);
+
+    if (isolate)
+        data |= SUPER_I_BLACKFIN;
+    else
+        data &= ~SUPER_I_BLACKFIN;
+
+    PHY_WRITE(phy_dev, 0x1e, 0x401c, data);
+
+    return 0;
+Exit:
+    return ret;
+}
+
+static int _phy_super_isolate_default(phy_dev_t *phy_dev, int isolate)
+{
+    int ret;
+    uint16_t data;
+
+    /* Read the status register */
+    PHY_READ(phy_dev, 0x1e, 0x401a, &data);
+
+    if (isolate)
+        data |= SUPER_I_DEFAULT;
+    else
+        data &= ~SUPER_I_DEFAULT;
+
+    PHY_WRITE(phy_dev, 0x1e, 0x401a, data);
+
+    return 0;
+Exit:
+    return ret;
+}
+
+static int _phy_isolate(phy_dev_t *phy_dev, int isolate)
+{
+    uint16_t val;
+    int ret;
+
+    PHY_READ(phy_dev, 0x7, 0xffe0, &val);
+    if (isolate) {
+        val |= BMCR_ISOLATE;
+    } else {
+        val &= ~BMCR_ISOLATE;
+    }
+    PHY_WRITE(phy_dev, 0x7, 0xffe0, val);
+
+Exit:
+    return ret;
+}
+
+static int _phy_super_isolate(phy_dev_t *phy_dev, int isolate)
+{
+    int ret, i = 1000;
+    uint16_t data;
+    uint32_t phyid;
+
+    _phy_phyid_get(phy_dev, &phyid);
+
+    if ((phyid & ID1_MASK) == ID1_5499X)
+        ret = _phy_super_isolate_5499x(phy_dev, isolate);
+    else
+        ret = _phy_super_isolate_default(phy_dev, isolate);
+
+    if (ret)
+        goto Exit;
+    do {
+        udelay(1000);
+        PHY_READ(phy_dev, 0x1e, 0x400e, &data);
+    } while (i-- && (data & CHANGE_STRAP_STATUS));
+
+    if (data & CHANGE_STRAP_STATUS)
+        printk("ERROR: PHY address: %d, hardware failed to clear SUPER_I boot strap status 0x%x\n", 
+                phy_dev->addr, data);
+
+    return 0;
+Exit:
+    return ret;
+}
+
+static int _phy_set_mode(phy_dev_t *phy_dev, int line_side)
+{
+    int ret;
+    uint16_t val1, val2, val3;
+
+    val1 = line_side ? 0x0001 : 0x2004;
+    val2 = line_side ? 0x0001 : 0x2004;
+    val3 = line_side ? 0x1002 : 0x2004;
+
+    /* Set base-pointer mode */
+    PHY_WRITE(phy_dev, 0x1e, 0x4110, val1);
+    PHY_WRITE(phy_dev, 0x1e, 0x4111, val2);
+    PHY_WRITE(phy_dev, 0x1e, 0x4113, val3);
+
+Exit:
+    return ret;
+}
+
+static int _phy_init(phy_dev_t *phy_dev)
+{
+    int ret, i;
+    uint16_t val;
+    phy_speed_t speed = PHY_SPEED_UNKNOWN;
+
+    /* Reset the phy */
+    PHY_WRITE(phy_dev, 0x01, 0x0000, 0x8000);
+
+    /* Verify that the processor is running */
+    i = 1000;
+    do
+    {
+        udelay(2000);
+        PHY_READ(phy_dev, 0x01, 0x0000, &val);
+        ret = (val != 0x2040);
+    } while (ret && i--);
+
+    if (ret)
+        goto Exit;
+
+    /* Set base-pointer mode to line side to access PMD/PCS/AN for BASE-T */
+    if ((ret = _phy_set_mode(phy_dev, 1)))
+        goto Exit;
+
+    /* Set idle stuffing mode */
+    if ((ret = _phy_idle_stuffing_mode_set(phy_dev, phy_dev->idle_stuffing)))
+        goto Exit;
+
+    /* Enable Force Auto-MDIX mode */
+    if ((ret = _phy_force_auto_mdix_set(phy_dev, 1)))
+        goto Exit;
+
+    /* Enable Ethernet@Wirespeed mode */
+    if ((ret = _phy_eth_wirespeed_set(phy_dev, 1)))
+        goto Exit;
+
+    /* Set pair-swap mode */
+    if ((ret = _phy_pair_swap_set(phy_dev, phy_dev->swap_pair)))
+        goto Exit;
+
+    /* Set XFI polarity */
+    if ((ret = _phy_xfi_polarity_set(phy_dev, 0)))
+        goto Exit;
+
+    if ((ret = phy_dev_caps_set(phy_dev, PHY_CAP_PAUSE | PHY_CAP_REPEATER)))
+        goto Exit;
+
+    /* Set led control type */
+    if ((ret = _phy_led_control_mode_set(phy_dev, 0)))
+        goto Exit;
+
+    
+    switch (phy_dev->mii_type)
+    {
+    case PHY_MII_TYPE_SGMII:
+        speed = PHY_SPEED_1000;
+        break;
+    case PHY_MII_TYPE_HSGMII:
+        speed = PHY_SPEED_2500;
+        break;
+    case PHY_MII_TYPE_XFI:
+        speed = PHY_SPEED_10000;
+        break;
+    default:
+        printk("Unsupported MII type: %d\n", phy_dev->mii_type);
+        break;
+    }
+
+    if ((ret = _phy_speed_set(phy_dev, speed, PHY_DUPLEX_FULL)))
+        goto Exit;
+
+#ifdef MACSEC_SUPPORT
+    if (macsec_phys & (1 << (phy_dev->addr)))
+    {
+        printk("phy 0x%x is macsec capable, initializing macsec module\n", phy_dev->addr);
+        ret = phy_macsec_pu_init(phy_dev);
+    }
+#endif    
+
+Exit:
+    return ret;
+}
+
+static int inline _bus_read(uint32_t addr, uint16_t dev, uint16_t reg, uint16_t *val)
+{
+    return bus_drv && bus_drv->c45_read(addr, dev, reg, val);
+}
+
+static int inline _bus_write(uint32_t addr, uint16_t dev, uint16_t reg, uint16_t val)
+{
+    return bus_drv && bus_drv->c45_write(addr, dev, reg, val);
+}
+
+static uint32_t _bus_read_all(uint32_t phy_map, uint16_t dev, uint16_t reg, uint16_t val, uint32_t mask)
+{
+    uint32_t i, ret = 0;
+    uint16_t _val;
+
+    for (i = 0; i < 32; i++)
+    {
+        if (!(phy_map & (1 << i)))
+            continue;
+
+        if ((_bus_read(i, dev, reg, &_val)))
+            continue;
+
+        if ((_val & mask) == val)
+            ret |= (1 << i);
+    }
+
+    return ret;
+}
+
+static int _bus_write_all(uint32_t phy_map, uint16_t dev, uint16_t reg, uint16_t val)
+{
+    int ret;
+    uint32_t i;
+
+    for (i = 0; i < 32; i++)
+    {
+        if (!(phy_map & (1 << i)))
+            continue;
+
+        if ((ret = _bus_write(i, dev, reg, val)))
+            return ret;
+    }
+
+    return 0;
+}
+
+static int _bus_write_and_verify_all(uint32_t phy_map, uint16_t dev, uint16_t reg, uint16_t val, uint32_t mask)
+{
+    int ret;
+    uint32_t i, j;
+    uint16_t _val;
+
+    for (i = 0; i < 32; i++)
+    {
+        if (!(phy_map & (1 << i)))
+            continue;
+
+                j = 1000;
+                do
+                {
+                    udelay(1000);
+                    if ((ret = _bus_write(i, dev, reg, val)))
+                        return ret;
+                
+                    if ((ret = _bus_read(i, dev, reg, &_val)))
+                        return ret;
+            } while (((_val & 0xffff) != val) && j--);
+            
+            if (j == 0)
+            {
+                printk("MDIO Bus Write and Verify is failed \n");
+                return -1;
+            }
+    }
+
+    return 0;
+}
+
+static int phy_count (uint32_t phy_map)
+{
+    int cnt;
+    for (cnt = 0; phy_map != 0; phy_map &= (phy_map - 1))
+        cnt++;
+
+    return cnt;
+}
+
+static uint32_t get_base_phy_addr(uint32_t phy_map)
+{
+    int flag = 1;
+    int cnt = 0;
+    while ((flag & phy_map) == 0)
+        {
+            flag <<= 1;
+            cnt ++;
+        }
+    
+    return cnt;
+}
+
+static uint32_t bcast_phy_map(uint32_t phy_map)
+{
+    return (phy_map & ~(1 << get_base_phy_addr(phy_map)));
+}
+
+#if defined(CONFIG_BCM_PHY_MAKO_A0)
+static int load_mako(firmware_t *firmware)
+{
+    int i, cnt, step, ret, base_phy_addr, phy_cnt;
+    uint32_t phy_map, *firmware_data, firmware_size, b_phy_map;
+
+    phy_map = firmware->map;
+    base_phy_addr = get_base_phy_addr(phy_map); /* select the min PHY address for broadcast operation */
+    b_phy_map = bcast_phy_map(phy_map); /* phy map for broadcast configuration - exclude the min PHY address */
+    phy_cnt = phy_count(phy_map);
+
+    firmware_data = firmware->data;
+    firmware_size = firmware->size;
+
+    cnt = firmware_size / sizeof(uint32_t);
+    step = cnt / 100;
+
+    /* 1. If more than one PHY, turn on broadcast mode to accept write operations for addr = base_phy_addr */
+    if (phy_cnt > 1)
+    {
+        printk("Turn on broadcast mode to accept write operations\n");
+        BUS_WRITE_ALL(b_phy_map, 0x1e, 0x4107, 0x0401 | ((base_phy_addr & 0x1f) << 5));
+        BUS_WRITE_ALL(b_phy_map, 0x1e, 0x4117, 0xf001);
+    }
+
+    /* 2. Halt the BCM8486X processors operation */
+    printk("Halt the PHYs processors operation\n");
+
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4188, 0x48f0);
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4186, 0x8000);
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4181, 0x017c);
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4181, 0x0040);
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0xc300);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81b, 0x0010);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81c, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0xffff);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81b, 0x1018);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81c, 0xe59f);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0004);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0xffff);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81b, 0x1f11);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81c, 0xee09);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0008);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0xffff);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81b, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81c, 0xe3a0);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x000c);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0xffff);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81b, 0x1806);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81c, 0xe3a0);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0010);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0xffff);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81b, 0x0002);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81c, 0xe8a0);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0014);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0xffff);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81b, 0x0001);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81c, 0xe150);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0018);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0xffff);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81b, 0xfffc);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81c, 0x3aff);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x001c);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0xffff);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81b, 0xfffe);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81c, 0xeaff);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0020);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0xffff);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81b, 0x0021);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81c, 0x0004);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4181, 0x0000);
+
+    /* 3. Upload the firmware into the on-chip memory of the devices */
+    printk("Upload the firmware into the on-chip memory\n");
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0038);
+
+    for (i = 0; i < cnt; i++)
+    {
+        BUS_WRITE(base_phy_addr, 0x01, 0xa81c, firmware_data[i] >> 16); /* upper 16 bits */
+        BUS_WRITE(base_phy_addr, 0x01, 0xa81b, firmware_data[i] & 0xffff); /* lower 16 bits */
+
+        if (i == i / step * step)
+            printk("\r%d%%", i / step);
+    }
+    printk("\n");
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0xc300);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81b, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81c, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0009);
+
+    /* 4. Reset the processors to start execution of the code in the on-chip memory */
+    printk("Reset the processors to start execution of the code in the on-chip memory\n");
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa008, 0x0000);
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x8004, 0x5555);
+    BUS_WRITE(base_phy_addr, 0x01, 0x0000, 0x8000);
+
+    /* 5. Verify that the processors are running */
+    printk("Verify that the processors are running: ");
+
+    i = 1000;
+    do
+    {
+        udelay(2000);
+        ret = _bus_read_all(phy_map, 0x01, 0x0000, 0x2040, 0xffff);
+    } while ((ret != phy_map) && i--);
+
+    printk("%s\n", ret != phy_map ? "Failed" : "OK");
+
+    ret = ret != phy_map;
+    if (ret)
+        goto Exit;
+
+    /* 6. Verify that the firmware has been loaded into the on-chip memory with a good CRC */
+    printk("Verify that the firmware has been loaded with good CRC: ");
+
+    i = 1000;
+    do
+    {
+        udelay(2000);
+        ret = _bus_read_all(phy_map, 0x1e, 0x400d, 0x4000, 0xc000);
+    } while ((ret != phy_map) && i--);
+
+    printk("%s\n", ret != phy_map ? "Failed" : "OK");
+
+    ret = ret != phy_map;
+    if (ret)
+        goto Exit;
+
+    printk("Firmware loading completed successfully\n\n");
+
+Exit:
+    return ret;
+}
+#endif
+
+#if defined(CONFIG_BCM_PHY_ORCA_A0) || defined(CONFIG_BCM_PHY_ORCA_B0)
+static int load_orca(firmware_t *firmware)
+{
+    int i, cnt, step, ret, base_phy_addr, phy_cnt;
+    uint32_t phy_map, *firmware_data, firmware_size, b_phy_map;
+
+    phy_map = firmware->map;
+    base_phy_addr = get_base_phy_addr(phy_map); /* select the min PHY address for broadcast operation */
+    b_phy_map = bcast_phy_map(phy_map); /* phy map for broadcast configuration - exclude the min PHY address */
+    phy_cnt = phy_count(phy_map);
+
+    firmware_data = firmware->data;
+    firmware_size = firmware->size;
+
+    cnt = firmware_size / sizeof(uint32_t);
+    step = cnt / 100;
+
+    /* 1. Halt the BCM8488X processors operation */
+    printk("Halt the PHYs processors operation\n");
+
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x418c, 0x0000);
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4188, 0x48f0);
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4181, 0x017c);
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4186, 0x8000);
+
+    BUS_WRITE_AND_VERIFY_ALL(phy_map, 0x1e, 0x4181, 0x0040, 0xffff);
+
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4186, 0x8000);
+
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa819, 0x0000);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa81a, 0xc300);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa81b, 0x0001);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa81c, 0x0000);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4181, 0x0000);
+
+    /* 2. If more than one PHY, turn on broadcast mode to accept write operations for addr = base_phy_addr */
+    if (phy_cnt > 1)
+    {
+        printk("Turn on broadcast mode to accept write operations\n");
+        BUS_WRITE_ALL(b_phy_map, 0x1e, 0x4107, 0x0401 | ((base_phy_addr & 0x1f) << 5));
+        BUS_WRITE_ALL(b_phy_map, 0x1e, 0x4117, 0xf001);
+    }
+
+    /* 3. Upload the firmware into the on-chip memory of the devices */
+    printk("Upload the firmware into the on-chip memory\n");
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0038);
+
+    for (i = 0; i < cnt; i++)
+    {
+        BUS_WRITE(base_phy_addr, 0x01, 0xa81c, firmware_data[i] >> 16); /* upper 16 bits */
+        BUS_WRITE(base_phy_addr, 0x01, 0xa81b, firmware_data[i] & 0xffff); /* lower 16 bits */
+
+        if (i == i / step * step)
+            printk("\r%d%%", i / step);
+    }
+    printk("\n");
+
+    /* 4. Reset the processors to start execution of the code in the on-chip memory */
+    printk("Reset the processors to start execution of the code in the on-chip memory\n");
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa008, 0x0000);
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x8004, 0x5555);
+    BUS_WRITE(base_phy_addr, 0x1, 0x8003, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0x0000, 0x8000);
+
+    /* 5. Verify that the processors are running */
+    printk("Verify that the processors are running: ");
+
+    i = 1000;
+    do
+    {
+        udelay(2000);
+        ret = _bus_read_all(phy_map, 0x01, 0x0000, 0x2040, 0xffff);
+    } while ((ret != phy_map) && i--);
+
+    printk("%s\n", ret != phy_map ? "Failed" : "OK");
+
+    ret = ret != phy_map;
+    if (ret)
+        goto Exit;
+
+    /* 6. Verify that the firmware has been loaded into the on-chip memory with a good CRC */
+    printk("Verify that the firmware has been loaded with good CRC: ");
+
+    i = 1000;
+    do
+    {
+        udelay(2000);
+        ret = _bus_read_all(phy_map, 0x1e, 0x400d, 0x4000, 0xc000);
+    } while ((ret != phy_map) && i--);
+
+    printk("%s\n", ret != phy_map ? "Failed" : "OK");
+
+    ret = ret != phy_map;
+    if (ret)
+        goto Exit;
+
+    printk("Firmware loading completed successfully\n\n");
+
+Exit:
+    return ret;
+}
+#endif
+
+#if defined(CONFIG_BCM_PHY_BLACKFIN_A0) || defined(CONFIG_BCM_PHY_BLACKFIN_B0) || defined(CONFIG_BCM_PHY_LONGFIN_A0) || defined(CONFIG_BCM_PHY_LONGFIN_B0)
+static int load_blackfin(firmware_t *firmware)
+{
+    int i, cnt, step, ret, base_phy_addr, phy_cnt;
+    uint32_t phy_map, *firmware_data, firmware_size, b_phy_map;
+
+    phy_map = firmware->map;
+    base_phy_addr = get_base_phy_addr(phy_map); /* select the min PHY address for broadcast operation */
+    b_phy_map = bcast_phy_map(phy_map); /* phy map for broadcast configuration - exclude the min PHY address */
+    phy_cnt = phy_count(phy_map);
+
+    firmware_data = firmware->data;
+    firmware_size = firmware->size;
+
+    cnt = firmware_size / sizeof(uint32_t);
+    step = cnt / 100;
+
+    /* 1. Halt the BCM5499X processors operation */
+    printk("Halt the PHYs processors operation\n");
+
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4110, 0x0001);
+
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x418c, 0x0000);
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4188, 0x48f0);
+
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa81a, 0xf000);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa819, 0x3000);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa81c, 0x0000);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa81b, 0x0121);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa817, 0x0009);
+
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x80a6, 0x0000);
+    BUS_WRITE_ALL(phy_map, 0x1, 0xa010, 0x0000);
+    BUS_WRITE_ALL(phy_map, 0x1, 0x0000, 0x8000);
+
+    udelay(1000);
+    BUS_WRITE_ALL(phy_map, 0x1e, 0x4110, 0x0001);
+    udelay(1000);
+
+    /* 2. If more than one PHY, turn on broadcast mode to accept write operations for addr = base_phy_addr */
+    if (phy_cnt > 1)
+    {
+        printk("Turn on broadcast mode to accept write operations\n");
+        BUS_WRITE_ALL(b_phy_map, 0x1e, 0x4107, 0x0401 | ((base_phy_addr & 0x1f) << 5));
+        BUS_WRITE_ALL(b_phy_map, 0x1e, 0x4117, 0xf001);
+    }
+
+    /* 3. Upload the firmware into the on-chip memory of the devices */
+    printk("Upload the firmware into the on-chip memory\n");
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa81a, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa819, 0x0000);
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0038);
+
+    for (i = 0; i < cnt; i++)
+    {
+        BUS_WRITE(base_phy_addr, 0x01, 0xa81c, firmware_data[i] >> 16); /* upper 16 bits */
+        BUS_WRITE(base_phy_addr, 0x01, 0xa81b, firmware_data[i] & 0xffff); /* lower 16 bits */
+
+        if (i == i / step * step)
+            printk("\r%d%%", i / step);
+    }
+    printk("\n");
+
+    BUS_WRITE(base_phy_addr, 0x01, 0xa817, 0x0000);
+
+    /* 4. Disable broadcast if phy cnt > 1 */
+    if (phy_cnt > 1)
+    {
+        BUS_WRITE_ALL(b_phy_map, 0x1e, 0x4107, 0x0000);
+        BUS_WRITE_ALL(b_phy_map, 0x1e, 0x4117, 0x0000);
+    }
+
+    /* 5. Reset the processors to start execution of the code in the on-chip memory */
+    printk("Reset the processors to start execution of the code in the on-chip memory\n");
+
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa81a, 0xf000);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa819, 0x3000);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa81c, 0x0000);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa81b, 0x0020);
+    BUS_WRITE_ALL(phy_map, 0x01, 0xa817, 0x0009);
+
+    udelay(2000);
+    
+    /* 6. Verify that the processors are running */
+    printk("Verify that the processors are running: ");
+
+    i = 1000;
+    do
+    {
+        udelay(2000);
+        ret = _bus_read_all(phy_map, 0x01, 0x0000, 0x2040, 0xffff);
+    } while ((ret != phy_map) && i--);
+
+    printk("%s\n", ret != phy_map ? "Failed" : "OK");
+
+    ret = ret != phy_map;
+    if (ret)
+        goto Exit;
+
+    /* 7. Verify that the firmware has been loaded into the on-chip memory with a good CRC */
+    printk("Verify that the firmware has been loaded with good CRC: ");
+
+    i = 1000;
+    do
+    {
+        udelay(2000);
+        ret = _bus_read_all(phy_map, 0x1e, 0x400d, 0x4000, 0xc000);
+    } while ((ret != phy_map) && i--);
+
+    printk("%s\n", ret != phy_map ? "Failed" : "OK");
+
+    ret = ret != phy_map;
+    if (ret)
+        goto Exit;
+
+    printk("Firmware loading completed successfully\n\n");
+
+Exit:
+    return ret;
+}
+#endif
+
+#ifdef PHY_GPIO
+static void phy_reset_lift(phy_dev_t *phy_dev)
+{
+    if (!dt_gpio_exists(phy_dev->reset_gpiod))
+        return;
+
+    dt_gpio_set_direction_output(phy_dev->reset_gpiod, 1);
+    printk(" Lift PHY at address %d out of Reset\n", phy_dev->addr);
+    dt_gpio_set_value(phy_dev->reset_gpiod, 1);
+    udelay(2000);
+    dt_gpio_set_value(phy_dev->reset_gpiod, 0);
+    udelay(2000);
+} 
+
+static void phys_reset_lift(uint32_t phy_map)
+{
+    int i;
+    phy_dev_t *phy_dev;
+
+    for (i = 0; i < 32; i++) {
+        if (!(phy_map & (1 << i)))
+            continue;
+        phy_dev = phy_dev_get(PHY_TYPE_EXT3, i);
+        phy_reset_lift(phy_dev);
+    }
+}
+#endif
+
+static int _phy_cfg(uint32_t enabled_phys)
+{
+    int i, j, k, ret = 0;
+    uint32_t phy_map;
+
+    if (!enabled_phys)
+        return 0;
+
+    printk("\nDetecting PHYs...\n");
+
+#ifdef PHY_GPIO
+	phys_reset_lift(enabled_phys);
+#endif
+
+    for (i = 0; i < sizeof(firmware_list)/sizeof(firmware_list[0]); i++)
+    {
+        for (j = 0; j < sizeof(phy_desc)/sizeof(phy_desc[0]); j++)
+        {
+            if (phy_desc[j].firmware != firmware_list[i])
+                continue;
+
+            phy_map = (_bus_read_all(enabled_phys, 0x01, 0x0002, phy_desc[j].phyid1, 0xffff)) &
+                (_bus_read_all(enabled_phys, 0x01, 0x0003, phy_desc[j].phyid2, 0xffff));
+
+            firmware_list[i]->map |= phy_map;
+
+            if (phy_map)
+            {
+                printk("%s %x:%x --> ", phy_desc[j].name, phy_desc[j].phyid1, phy_desc[j].phyid2);
+                for (k = 0; k < 32 ; k++)
+                {
+                    if (!(phy_map & (1 << k)))
+                        continue;
+
+                    printk("0x%x ", k);
+                }
+                printk("\n");
+            }
+        }
+    }
+
+    printk("\nLoading firmware into detected PHYs...\n\n");
+
+    for (i = 0; i < sizeof(firmware_list)/sizeof(firmware_list[0]); i++)
+    {
+        phy_map = firmware_list[i]->map;
+
+        if (!phy_map)
+            continue;
+
+        if (firmware_list[i]->macsec_capable)
+            macsec_phys |= phy_map;
+
+        printk("Firmware version: %s\n", firmware_list[i]->version);
+        printk("Loading firmware into PHYs: map=0x%x count=%d\n", phy_map, phy_count(phy_map));
+
+        firmware_list[i]->load(firmware_list[i]);
+    }
+
+    return ret;
+}
+
+static int _phy_dev_add(phy_dev_t *phy_dev)
+{
+    bus_drv = phy_dev->bus_drv;
+    enabled_phys |= (1 << (phy_dev->addr));
+    return 0;
+}
+
+static int _phy_dev_del(phy_dev_t *phy_dev)
+{
+    enabled_phys &= ~(1 << (phy_dev->addr));
+
+    return 0;
+}
+
+static int _phy_drv_init(phy_drv_t *phy_drv)
+{
+    if (_phy_cfg(enabled_phys))
+    {
+        printk("Failed to initialize the driver\n");
+        return -1;
+    }
+
+    phy_drv->initialized = 1;
+
+    return 0;
+}
+
+int _inter_phy_types_get(phy_dev_t *phy_dev, inter_phy_types_dir_t if_dir, uint32_t *inter_phy_types)
+{
+    uint16_t phyid1, phyid2;
+    int j, ret;
+
+    *inter_phy_types = INTER_PHY_TYPES_UNKNOWN_M;
+    PHY_READ(phy_dev, 0x01, 0x0002, &phyid1);
+    PHY_READ(phy_dev, 0x01, 0x0003, &phyid2);
+
+    for (j = 0; j < sizeof(phy_desc)/sizeof(phy_desc[0]); j++)
+    {
+        if (phy_desc[j].phyid1 != phyid1 || phy_desc[j].phyid2 != phyid2)
+            continue;
+        *inter_phy_types = phy_desc[j].inter_phy_types;
+    }
+
+    return 0;
+
+Exit:
+    return ret;
+}
+
+#ifdef __UBOOT__
+static unsigned long _jiffies;
+#define jiffies (_jiffies++)
+#define msecs_to_jiffies(j) ((j)*10)
+#endif
+
+#define EXT3_ECD_CTRL_STATUS_D  0x1e
+#define EXT3_ECD_CTRL_STATUS_R  0x4006
+    #define EXT3_ECDRUN_IMMEDIATE   (1<<15)
+    #define EXT3_ECDBREAK_LINK      (1<<12)
+    #define EXT3_ECDDIAG_IN_PROG    (1<<11)
+
+#define EXT3_ECD_RESULTS_D      0x1
+#define EXT3_ECD_RESULTS_R      0xa896
+    #define EXT3_PACD_CODE_SHIFT            4
+    #define EXT3_PACD_CODE_MASK             0xf
+    #define EXT3_PACD_CODE_INVALID          0x0
+    #define EXT3_PACD_CODE_PAIR_OK          0x1
+    #define EXT3_PACD_CODE_PAIR_OPEN        0x2
+    #define EXT3_PACD_CODE_PAIR_INTRA_SHORT 0x3
+    #define EXT3_PACD_CODE_PAIR_INTER_SHORT 0x4
+    #define EXT3_PACD_CODE_PAIR_GET(v, p)          (((v)>>((p)*4))&0xf)
+    #define EXT3_PACD_CODE_PAIR_SET(v, p)          (((v)&0xf)<<((p)*4))
+    #define EXT3_PACD_CODE_PAIR_ALL_OK      0x1111
+    #define EXT3_PACD_CODE_PAIR_ALL_OPEN    0x2222
+
+#define EXT3_ECD_CABLE_LEN_D 0x1
+#define EXT3_ECD_CABLE_LEN_R 0xa897
+
+/* 
+    Work around some hardware inconsistency
+    Pick up the most popular length from 4 pairs
+*/
+static void cable_length_pick_link_up(int *pair_len, int excluded_pair)
+{
+    int len[4]={0};
+    int i, j, k, m;
+
+    for (i=0, k=0; i<4; i++) {
+        if (excluded_pair & (1<<i))  /* Exclude failed CD pair */
+            continue;
+
+        for(j=0; j<k; j++) 
+            if (pair_len[j] == pair_len[i]) 
+                break;
+
+        if (j==k)
+            k++;
+        len[j]++;
+    }
+
+    for (i=0, j=0, m=0; i<k; i++) {
+        if (len[i] == 0)    /* If result is zero, exclude the pair from picking */
+            continue;
+
+        if(len[i]>j) {
+            j=len[i];
+            m=i;
+        }
+    }
+
+    m = pair_len[m];
+    for (i=0; i<4; i++)
+        pair_len[i] = m; 
+}
+
+int _phy_enhanced_cable_diag_run(phy_dev_t *phy_dev, int *result, int *pair_len)
+{
+    uint16_t v16, ctl_reg;
+    int i, j, ret = 0, excluded_pair = 0;
+    int apd_enabled, phy_link;
+    unsigned long jiffie;
+    int retries = 0;
+#define EXT3_ECDCHECK_SECS 3
+#define EXT3_ECDMAX_RETRIES 3
+
+    phy_dev_apd_get(phy_dev, &apd_enabled);
+    if (apd_enabled)
+        phy_dev_apd_set(phy_dev, 0);
+
+    v16 = EXT3_ECDRUN_IMMEDIATE;
+    if ((phy_link = phy_dev->link)) {  /* Save initial PHY link status */
+        PHY_READ(phy_dev, 0x07, 0xffe0, &ctl_reg);
+    }
+
+    if (phy_link) { /* If link is up, Write RUN first and wait until link goes down */
+        PHY_WRITE(phy_dev, EXT3_ECD_CTRL_STATUS_D, EXT3_ECD_CTRL_STATUS_R, v16);
+        for(;;) {
+            phy_dev_read_status(phy_dev);
+            if (!phy_dev->link) break;
+        }
+    }
+
+TryAgain:
+    if (retries) for(i=0, jiffie = jiffies; jiffies < (jiffie + msecs_to_jiffies(2*1000)););
+    if (++retries > EXT3_ECDMAX_RETRIES)  /* If we did retry more than certain time, declares it as faiure */
+        goto end;
+
+    PHY_WRITE(phy_dev, EXT3_ECD_CTRL_STATUS_D, EXT3_ECD_CTRL_STATUS_R, v16);
+    ret = phy_bus_c45_read(phy_dev, EXT3_ECD_CTRL_STATUS_D, EXT3_ECD_CTRL_STATUS_R, &v16);
+    for(i=0, jiffie = jiffies; jiffies < (jiffie + msecs_to_jiffies(EXT3_ECDCHECK_SECS*1000)); ) {
+        PHY_READ(phy_dev, EXT3_ECD_CTRL_STATUS_D, EXT3_ECD_CTRL_STATUS_R, &v16);
+        if (!(v16 & EXT3_ECDDIAG_IN_PROG)) {
+            ret = 0;
+            i = 1;
+            break;
+        }
+    }
+
+    if (!i) {    /* If CD is still in progress after certain time, retry it */
+        *result = EXT3_PACD_CODE_INVALID;
+        ret = -1;
+        goto TryAgain;
+    }
+
+    for(i=0, jiffie = jiffies; jiffies < (jiffie + msecs_to_jiffies(EXT3_ECDCHECK_SECS*1000)); ) {
+        PHY_READ(phy_dev, EXT3_ECD_RESULTS_D, EXT3_ECD_RESULTS_R, &v16);
+        *result = v16;
+        excluded_pair = 0;
+        for(j=0; j<4; j++) { /* Check if all four pairs of diags are done */
+            if( EXT3_PACD_CODE_PAIR_GET(*result, j) > EXT3_PACD_CODE_PAIR_INTER_SHORT) 
+                break;
+
+            /* If link is up, excluded failed measuring result */
+            if( phy_link && ( EXT3_PACD_CODE_PAIR_GET(*result, j) != EXT3_PACD_CODE_PAIR_OK))
+                excluded_pair |= (1<<j); 
+        }
+
+        /* If all pair of diags finish, check the results */
+        if (j==4) {
+            /* If in link up, all pair diag failed, try again */
+            if (*result == EXT3_PACD_CODE_INVALID || excluded_pair == 0xf ) 
+                goto TryAgain;
+            /* Otherwise, we are done with CD */
+            i=1;
+            break;
+        }
+    }
+
+    if (phy_link)
+        *result = EXT3_PACD_CODE_PAIR_ALL_OK;
+
+    if (*result == EXT3_PACD_CODE_INVALID || !i) {  /* If CD ends with INVALID result, retry it */
+        *result = EXT3_PACD_CODE_INVALID;
+        ret = -1;
+        goto TryAgain;
+    }
+
+#define EXT3_CABLE_LEN_OFFSET_LINK_DOWN 200
+    for(i=0; i<4; i++) {
+        PHY_READ(phy_dev, EXT3_ECD_CABLE_LEN_D, (EXT3_ECD_CABLE_LEN_R + i), &v16);
+        if (*result == EXT3_PACD_CODE_PAIR_ALL_OPEN)
+            pair_len[i] = (v16> EXT3_CABLE_LEN_OFFSET_LINK_DOWN ? v16 - EXT3_CABLE_LEN_OFFSET_LINK_DOWN : 0); /* To guarrantee no cable result correct based on testing */
+        else if (*result == EXT3_PACD_CODE_PAIR_ALL_OK)
+            pair_len[i] = v16 + EXT3_CABLE_LEN_OFFSET_LINK_DOWN;
+        else
+            pair_len[i] = v16;
+    }
+
+    /* If link is up, but alll pair length is zero, try again */
+    if (phy_link && (pair_len[0] + pair_len[1] + pair_len[2] + pair_len[3] == 0))
+        goto TryAgain;
+
+end:
+    /* Reset PHY after CD */
+    ctl_reg |= (1<<15);
+    if (ctl_reg & (1<<12))
+        ctl_reg |= (1<<9);  /* If AN is on, set AN restart bit */
+    PHY_WRITE(phy_dev, 0x07, 0xffe0, ctl_reg);
+
+    /* Wait the link come back up */
+    if (phy_link) {
+        for(jiffie = jiffies; jiffies < (jiffie + msecs_to_jiffies(3*EXT3_ECDCHECK_SECS*1000)); ) {
+            phy_dev_read_status(phy_dev);
+            if (phy_dev->link) break;
+        }
+    }
+            
+    if (phy_link)
+        cable_length_pick_link_up(pair_len, excluded_pair);
+
+    if (apd_enabled)
+        phy_dev_apd_set(phy_dev, apd_enabled);
+
+    return ret;
+Exit:
+    return -1;
+}
+#if defined (MAC_LPORT)
+extern int lport_led_init(void *leds_info);
+#endif
+
+static int _phy_leds_init(phy_dev_t *phy_dev, void *leds_info)
+{
+#if defined (MAC_LPORT)
+    return lport_led_init(leds_info);
+#else
+    return 0; /* TBD */
+#endif
+}
+
+phy_drv_t phy_drv_ext3 =
+{
+    .phy_type = PHY_TYPE_EXT3,
+    .name = "EXT3",
+    .power_get = _phy_power_get,
+    .power_set = _phy_power_set,
+    .apd_get = _phy_apd_get,
+    .apd_set = _phy_apd_set,
+    .eee_get = _phy_eee_get,
+    .eee_set = _phy_eee_set,
+    .eee_resolution_get = _phy_eee_resolution_get,
+    .read_status = _phy_read_status,
+    .speed_set = _phy_speed_set,
+    .caps_get = _phy_caps_get,
+    .caps_set = _phy_caps_set,
+    .phyid_get = _phy_phyid_get,
+    .auto_mdix_set = _phy_force_auto_mdix_set,
+    .auto_mdix_get = _phy_force_auto_mdix_get,
+    .wirespeed_set = _phy_eth_wirespeed_set,
+    .wirespeed_get = _phy_eth_wirespeed_get,
+    .init = _phy_init,
+    .dev_add = _phy_dev_add,
+    .dev_del = _phy_dev_del,
+    .drv_init = _phy_drv_init,
+    .pair_swap_set = _phy_pair_swap_set,
+    .isolate_phy = _phy_isolate,
+    .super_isolate_phy = _phy_super_isolate,
+#ifdef MACSEC_SUPPORT
+    .macsec_oper = phy_macsec_oper,
+#endif    
+    .inter_phy_types_get = _inter_phy_types_get,
+    .inter_phy_types_set = _inter_phy_types_set,
+    .cable_diag_run = _phy_enhanced_cable_diag_run,
+    .leds_init = _phy_leds_init,
+};
diff --git a/drivers/net/bcmbca/phy/phy_drv_lport.c b/drivers/net/bcmbca/phy/phy_drv_lport.c
new file mode 100644
index 0000000000..18c4835bca
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_lport.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Jan 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Common functions for lport connected phy drivers
+ */
+
+#include "phy_drv.h"
+#include "lport_intr.h"
+
+static void lport_link_change_handler(phy_dev_t *phy_dev)
+{
+    uint32_t port = (uint64_t)phy_dev->priv;
+
+    phy_dev_link_change_notify(phy_dev);
+    lport_intr_enable(LPORT_PORT_LINK, port, 1);
+}
+
+static void lport_intr_cb(const lport_intr_info_s *info, void *priv)
+{
+    phy_dev_t *phy_dev = priv;
+    uint32_t port = (uint64_t)phy_dev->priv;
+
+    lport_intr_enable(LPORT_PORT_LINK, port, 0);
+    lport_intr_clear(LPORT_PORT_LINK, port);
+
+    phy_dev_queue_work(phy_dev, lport_link_change_handler);
+}
+
+int lport_link_change_register(phy_dev_t *phy_dev)
+{
+    int ret;
+    uint32_t port = (uint64_t)phy_dev->priv;
+
+    if ((ret = lport_intr_register(LPORT_PORT_LINK, port, lport_intr_cb, phy_dev)))
+    {
+        printk("Failed to register link interrupt for port %d\n", port);
+        return ret;
+    }
+
+    lport_intr_enable(LPORT_PORT_LINK, port, 1);
+
+    return 0;
+}
+
+int lport_link_change_unregister(phy_dev_t *phy_dev)
+{
+    uint32_t port = (uint64_t)phy_dev->priv;
+
+    lport_intr_enable(LPORT_PORT_LINK, port, 0);
+    lport_intr_unregister(LPORT_PORT_LINK, port);
+
+    return 0;
+}
diff --git a/drivers/net/bcmbca/phy/phy_drv_lport.h b/drivers/net/bcmbca/phy/phy_drv_lport.h
new file mode 100644
index 0000000000..7f168b7743
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_lport.h
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Jan 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#ifndef __PHY_DRV_LPORT_H__
+#define __PHY_DRV_LPORT_H__
+
+#include "phy_drv.h"
+
+int lport_link_change_register(phy_dev_t *phy_dev);
+int lport_link_change_unregister(phy_dev_t *phy_dev);
+
+#endif
diff --git a/drivers/net/bcmbca/phy/phy_drv_lport_serdes.c b/drivers/net/bcmbca/phy/phy_drv_lport_serdes.c
new file mode 100644
index 0000000000..e9db74dfce
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_lport_serdes.c
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Phy driver for lport SerDes: SGMII/HSGMII/XFI
+ */
+
+#include "bus_drv.h"
+#include "phy_drv.h"
+#include "bcm6858_lport_srds_ag.h"
+#include "serdes_access.h"
+#include "lport_drv.h"
+
+static uint32_t enabled_ports = 0xffffffff;
+
+static int _phy_power_get(phy_dev_t *phy_dev, int *enable)
+{
+    uint32_t port = (uint64_t)phy_dev->priv;
+
+    *enable = enabled_ports & (1 << port);
+
+    return 0;
+}
+
+static int _phy_power_set(phy_dev_t *phy_dev, int enable)
+{
+    uint32_t port = (uint64_t)phy_dev->priv;
+
+    if (enable)
+        enabled_ports |= (1 << port);
+    else
+        enabled_ports &= ~(1 << port);
+
+    return 0;
+}
+
+static int _get_serdes_link(uint32_t port, int *sig, int *lnk)
+{
+    int rc = LPORT_ERR_OK;
+    uint8_t msk = 0x2;
+    lport_srds_dual_serdes_0_status srds_0_status = {};
+    lport_srds_dual_serdes_1_status srds_1_status = {};
+
+    switch (port)
+    {
+    case 0:
+    case 7:
+        msk = 0x1;
+    case 1:
+    case 4:
+        rc = ag_drv_lport_srds_dual_serdes_0_status_get(&srds_0_status);
+        *sig = !(srds_0_status.ext_sig_det & msk) ? 1 : 0; 
+        *lnk = (srds_0_status.link_status & msk) ? 1 : 0; 
+        break;
+    case 2:
+    case 5:
+        msk = 0x1;
+    case 3:
+    case 6:
+        rc = ag_drv_lport_srds_dual_serdes_1_status_get(&srds_1_status);
+        *sig = !(srds_1_status.ext_sig_det & msk) ? 1 : 0; 
+        *lnk = (srds_1_status.link_status & msk) ? 1 : 0; 
+        break;
+    }
+
+    return rc;
+}
+
+static int _get_serdes_speed(uint32_t port, phy_speed_t *speed)
+{
+    lport_port_status_s port_status;
+    int ret;
+
+    if ((ret = lport_serdes_get_status(port, &port_status)))
+        return ret;
+
+    if (!port_status.port_up)
+        return 1;
+
+    if (port_status.rate == LPORT_RATE_10G)
+        *speed = PHY_SPEED_10000;
+    else if (port_status.rate == LPORT_RATE_2500MB)
+        *speed = PHY_SPEED_2500;
+    else if (port_status.rate == LPORT_RATE_1000MB)
+        *speed = PHY_SPEED_1000;
+    else if (port_status.rate == LPORT_RATE_100MB)
+        *speed = PHY_SPEED_100;
+    else if (port_status.rate == LPORT_RATE_10MB)
+        *speed = PHY_SPEED_10;
+
+    return 0;
+}
+
+#if defined(LPORT_SERDES_SPEED_DETECT)
+static LPORT_PORT_MUX_SELECT _get_next_mux(phy_dev_t *phy_dev, LPORT_PORT_MUX_SELECT mux)
+{
+    if (mux != PORT_UNAVAIL)
+        return mux -1;
+
+    if (phy_dev->mii_type == PHY_MII_TYPE_XFI)
+        return PORT_XFI;
+    if (phy_dev->mii_type == PHY_MII_TYPE_HSGMII)
+        return PORT_HSGMII;
+    if (phy_dev->mii_type == PHY_MII_TYPE_SGMII)
+        return PORT_SGMII_AN_MASTER;
+
+    return PORT_UNAVAIL;
+}
+
+static int _set_next_mux(uint32_t port, phy_dev_t *phy_dev)
+{
+    int ret;
+    LPORT_PORT_MUX_SELECT prt_mux_sel;
+
+    if ((ret = lport_get_port_mux(port, &prt_mux_sel)))
+        return ret;
+
+    prt_mux_sel = _get_next_mux(phy_dev, prt_mux_sel);
+
+    if ((ret = lport_set_port_mux(port, prt_mux_sel)))
+        return ret;
+
+    return 0;
+}
+#elif defined(LPORT_SERDES_EXTERNAL_SIGNAL_DETECT)
+static int _get_phy_speed(phy_dev_t *phy_dev, phy_speed_t *speed)
+{
+    if (phy_dev->mii_type == PHY_MII_TYPE_XFI)
+        *speed = PHY_SPEED_10000;
+    else if (phy_dev->mii_type == PHY_MII_TYPE_HSGMII)
+        *speed = PHY_SPEED_2500;
+    if (phy_dev->mii_type == PHY_MII_TYPE_SGMII)
+        *speed = PHY_SPEED_1000;
+
+    return 0;
+}
+#endif
+
+static int _phy_read_status(phy_dev_t *phy_dev)
+{
+    uint32_t port = (uint64_t)phy_dev->priv;
+    int sig = 0, lnk = 0, ret;
+
+    phy_dev->link = 0;
+    phy_dev->speed = PHY_SPEED_UNKNOWN;
+    phy_dev->duplex = PHY_DUPLEX_UNKNOWN;
+
+    if (!(enabled_ports & (1 << port)))
+        return 0;
+
+    if ((ret = _get_serdes_link(port, &sig, &lnk)))
+        return ret;
+
+#if defined(LPORT_SERDES_EXTERNAL_SIGNAL_DETECT)
+    if (!sig)
+        return 0;
+#endif
+
+    if (lnk)
+    {
+        if ((ret = _get_serdes_speed(port, &phy_dev->speed)))
+            return ret;
+
+        phy_dev->link = 1;
+        phy_dev->duplex = PHY_DUPLEX_FULL;
+    }
+    else
+    {
+#if defined(LPORT_SERDES_SPEED_DETECT)
+        if ((ret = _set_next_mux(port, phy_dev)))
+            return ret;
+#elif defined(LPORT_SERDES_EXTERNAL_SIGNAL_DETECT)
+        phy_dev->link = 1;
+        phy_dev->duplex = PHY_DUPLEX_FULL;
+
+        if ((ret = _get_phy_speed(phy_dev, &phy_dev->speed)))
+            return ret;
+#endif
+    }
+
+    return 0;
+}
+
+static int _phy_caps_get(phy_dev_t *phy_dev, int caps_type, uint32_t *pcaps)
+{
+    uint32_t caps = 0;
+    uint32_t port = (uint64_t)phy_dev->priv;
+    LPORT_PORT_RATE port_rate;
+
+    if ((caps_type != CAPS_TYPE_ADVERTISE) 
+        && (caps_type != CAPS_TYPE_SUPPORTED))
+        return 0;
+
+    port_rate = lport_speed_get(port);
+    switch (port_rate)
+    {
+    case LPORT_RATE_10MB: /* 10M */
+        caps |= PHY_CAP_10_HALF | PHY_CAP_10_FULL;
+        break;
+    case LPORT_RATE_100MB: /* 100Mbps */
+        caps |= PHY_CAP_100_HALF | PHY_CAP_100_FULL;
+        break;
+    case LPORT_RATE_1000MB: /* 1000Mbps */
+        caps |= PHY_CAP_1000_HALF | PHY_CAP_1000_FULL;
+        break;
+    case LPORT_RATE_2500MB: /* 2500Mbps */
+        caps |= PHY_CAP_2500;
+        break;
+    case LPORT_RATE_10G: /* 5000/10000Mbps */
+        caps |= PHY_CAP_10000;
+        break;
+    default:
+        break;
+    }
+
+    if (phy_dev->pause_rx && phy_dev->pause_tx)
+        caps |= PHY_CAP_PAUSE;
+    else if (phy_dev->pause_rx)
+        caps |= PHY_CAP_PAUSE | PHY_CAP_PAUSE_ASYM;
+    else if (phy_dev->pause_tx)
+        caps |= PHY_CAP_PAUSE_ASYM;
+
+    *pcaps = caps;
+    return 0;
+}
+
+static int _phy_caps_set(phy_dev_t *phy_dev, uint32_t caps)
+{
+    phy_dev->link = 0;
+    phy_dev->pause_rx = 0; 
+    phy_dev->pause_tx = 0; 
+
+    if (caps & PHY_CAP_PAUSE)
+    {
+        phy_dev->pause_rx = 1; 
+        phy_dev->pause_tx = (caps & PHY_CAP_PAUSE_ASYM) ? 0 : 1;
+    }
+    else if (caps & PHY_CAP_PAUSE_ASYM)
+    {
+        phy_dev->pause_tx = 1; 
+    }
+
+    return 0;
+}
+
+static dt_gpio_desc tx_dis_gpiod[LPORT_NUM_OF_PORTS];
+
+extern int lport_serdes_tx_disable_gpio_assign(int port, void *priv);
+extern void lport_serdes_tx_disable_gpio_ctrl_set(void (*_tx_disable_gpio_ctrl)(void *priv, int value));
+
+static void _lport_gpio_set_value(void *priv, int value)
+{
+    phy_dev_t *phy_dev = priv;
+    dt_gpio_desc desc;
+
+    if (!phy_dev)
+        return;
+
+    desc = tx_dis_gpiod[phy_dev->addr];
+    if (dt_gpio_exists(desc))
+        dt_gpio_set_value(desc, value);
+}
+
+static int _phy_drv_dt_priv(const dt_handle_t handle, uint32_t addr, uint32_t phy_mode, void **_priv)
+{
+    int rc = 0;
+
+    dt_gpio_desc desc;
+
+    rc = dt_gpio_request_by_name_optional(handle, "tx-disable", 0, "TX disable", &desc);
+    if (rc)
+        return rc;
+
+    if (dt_gpio_exists(desc))
+    {
+        tx_dis_gpiod[addr] = desc;
+    }
+
+    *_priv = (void*)(uint64_t)addr;
+
+    return rc;
+}
+
+static int _phy_drv_init(phy_drv_t *phy_drv)
+{
+    lport_serdes_tx_disable_gpio_ctrl_set(_lport_gpio_set_value);
+
+    return 0;
+}
+
+static int _phy_init(phy_dev_t *phy_dev)
+{
+    if (phy_dev->addr < LPORT_NUM_OF_PORTS)
+        lport_serdes_tx_disable_gpio_assign(phy_dev->addr, phy_dev);
+
+    return 0;
+}
+
+extern int lport_led_init(void *leds_info);
+
+static int _phy_leds_init(phy_dev_t *phy_dev, void *leds_info)
+{
+    return lport_led_init(leds_info);
+}
+
+phy_drv_t phy_drv_lport_serdes =
+{
+    .phy_type = PHY_TYPE_LPORT_SERDES,
+    .name = "SERDES",
+    .power_get = _phy_power_get,
+    .power_set = _phy_power_set,
+    .read_status = _phy_read_status,
+    .caps_get = _phy_caps_get,
+    .caps_set = _phy_caps_set,
+    .init = _phy_init,
+    .dt_priv = _phy_drv_dt_priv,
+    .leds_init = _phy_leds_init,
+    .drv_init = _phy_drv_init,
+};
diff --git a/drivers/net/bcmbca/phy/phy_drv_mii.c b/drivers/net/bcmbca/phy/phy_drv_mii.c
new file mode 100644
index 0000000000..7758456e08
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_mii.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#include "bus_drv.h"
+#include "phy_drv.h"
+#include "phy_drv_mii.h"
+
+int mii_phyid_get(phy_dev_t *phy_dev, uint32_t *phyid)
+{
+    int ret;
+    uint16_t phyid1, phyid2;
+
+    if ((ret = phy_bus_read(phy_dev, MII_PHYSID1, &phyid1)))
+        goto Exit;
+
+    if ((ret = phy_bus_read(phy_dev, MII_PHYSID2, &phyid2)))
+        goto Exit;
+
+    *phyid = phyid1 << 16 | phyid2;
+
+Exit:
+    return ret;
+}
+
+int mii_autoneg_restart(phy_dev_t *phy_dev)
+{
+    uint16_t val;
+    int ret;
+
+    if ((ret = phy_bus_read(phy_dev, MII_BMCR, &val)))
+        goto Exit;
+
+    if ((ret = phy_bus_write(phy_dev, MII_BMCR, val | BMCR_ANRESTART)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int mii_power_get(phy_dev_t *phy_dev, int *enable)
+{
+    uint16_t val;
+    int ret;
+
+    if ((ret = phy_bus_read(phy_dev, MII_BMCR, &val)))
+        goto Exit;
+
+    *enable = (val & BMCR_POWERDOWN) ? 0 : 1;
+
+Exit:
+    return ret;
+}
+
+int mii_power_set(phy_dev_t *phy_dev, int enable)
+{
+    uint16_t val;
+    int ret;
+
+    if ((ret = phy_bus_read(phy_dev, MII_BMCR, &val)))
+        goto Exit;
+
+    if (!enable || (val & BMCR_POWERDOWN))
+        val |= BMCR_ANRESTART;
+
+    if (enable)
+        val &= ~BMCR_POWERDOWN;
+    else
+        val |= BMCR_POWERDOWN;
+
+    if ((ret = phy_bus_write(phy_dev, MII_BMCR, val))) 
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int mii_caps_get(phy_dev_t *phy_dev, int caps_type,  uint32_t *pcaps)
+{
+    int ret;
+    uint32_t caps = 0;
+
+    if (caps_type == CAPS_TYPE_ADVERTISE)
+    {
+        int speed = 0;
+        uint16_t bmcr, ctrl1000, adv;
+
+        if ((ret = phy_bus_read(phy_dev, MII_BMCR, &bmcr)))
+            goto Exit;
+
+        if ((ret = phy_bus_read(phy_dev, MII_CTRL1000, &ctrl1000)))
+            goto Exit;
+
+        if ((ret = phy_bus_read(phy_dev, MII_ADVERTISE, &adv)))
+            goto Exit;
+
+        if (bmcr & BMCR_ANENABLE)
+        {
+            caps |= PHY_CAP_AUTONEG;
+
+            if (adv & ADVERTISE_PAUSE_CAP)      caps |= PHY_CAP_PAUSE;
+            if (adv & ADVERTISE_PAUSE_ASYM)     caps |= PHY_CAP_PAUSE_ASYM;
+            if (adv & ADVERTISE_10HALF)         caps |= PHY_CAP_10_HALF;
+            if (adv & ADVERTISE_10FULL)         caps |= PHY_CAP_10_FULL;
+            if (adv & ADVERTISE_100HALF)        caps |= PHY_CAP_100_HALF;
+            if (adv & ADVERTISE_100FULL)        caps |= PHY_CAP_100_FULL;
+            if (ctrl1000 & ADVERTISE_1000HALF)  caps |= PHY_CAP_1000_HALF;
+            if (ctrl1000 & ADVERTISE_1000FULL)  caps |= PHY_CAP_1000_FULL;
+            if (ctrl1000 & ADVERTISE_REPEATER)  caps |= PHY_CAP_REPEATER;
+        }
+        else
+        {
+            speed = (bmcr & BMCR_SPEED100) >> 13 | (bmcr & BMCR_SPEED1000) >> 5;
+
+            if (speed == 0) caps |= bmcr & BMCR_FULLDPLX ? PHY_CAP_10_FULL : PHY_CAP_10_HALF;
+            if (speed == 1) caps |= bmcr & BMCR_FULLDPLX ? PHY_CAP_100_FULL : PHY_CAP_100_HALF;
+            if (speed == 2) caps |= bmcr & BMCR_FULLDPLX ? PHY_CAP_1000_FULL : PHY_CAP_1000_HALF;
+        }
+        
+    }
+    else if (caps_type == CAPS_TYPE_SUPPORTED)
+    {
+        uint16_t estatus = 0;
+        uint16_t bmsr    = 0;
+
+        if ((ret = phy_bus_read(phy_dev, MII_BMSR, &bmsr)))
+            goto Exit;
+
+        if ((phy_dev->mii_type != PHY_MII_TYPE_MII)
+            && (phy_dev->mii_type != PHY_MII_TYPE_TMII))
+        {
+            if ((ret = phy_bus_read(phy_dev, MII_ESTATUS, &estatus)))
+                goto Exit;
+        }
+        
+        if (bmsr & BMSR_ANEGCAPABLE)        caps |= PHY_CAP_AUTONEG;
+        if (bmsr & BMSR_10HALF)             caps |= PHY_CAP_10_HALF;
+        if (bmsr & BMSR_10FULL)             caps |= PHY_CAP_10_FULL;
+        if (bmsr & BMSR_100HALF)            caps |= PHY_CAP_100_HALF;
+        if (bmsr & BMSR_100FULL)            caps |= PHY_CAP_100_FULL;
+        if (estatus & ESTATUS_1000_THALF)   caps |=  PHY_CAP_1000_HALF;
+        if (estatus & ESTATUS_1000_TFULL)   caps |=  PHY_CAP_1000_FULL;
+    }
+    else if (caps_type == CAPS_TYPE_LP_ADVERTISED)
+    {
+        uint16_t stat1000, lpa;
+
+        if ((ret = phy_bus_read(phy_dev, MII_STAT1000, &stat1000)))
+            goto Exit;
+
+        if ((ret = phy_bus_read(phy_dev, MII_LPA, &lpa)))
+            goto Exit;
+
+        if (lpa & LPA_LPACK)
+        {
+            caps |= PHY_CAP_AUTONEG;
+            if (lpa & LPA_PAUSE_CAP)        caps |= PHY_CAP_PAUSE;
+            if (lpa & LPA_PAUSE_ASYM)       caps |= PHY_CAP_PAUSE_ASYM;
+            if (lpa & LPA_10HALF)           caps |= PHY_CAP_10_HALF;
+            if (lpa & LPA_10FULL)           caps |= PHY_CAP_10_FULL;
+            if (lpa & LPA_100HALF)          caps |= PHY_CAP_100_HALF;
+            if (lpa & LPA_100FULL)          caps |= PHY_CAP_100_FULL;
+            if (stat1000 & LPA_1000HALF)    caps |= PHY_CAP_1000_HALF;
+            if (stat1000 & LPA_1000FULL)    caps |= PHY_CAP_1000_FULL;
+        }
+    }
+
+    *pcaps = caps;
+
+Exit:
+    return ret;
+}
+
+int mii_caps_set(phy_dev_t *phy_dev, uint32_t caps)
+{
+    int ret;
+    uint16_t bmcr, ctrl1000, adv;
+
+    if ((ret = phy_bus_read(phy_dev, MII_BMCR, &bmcr)))
+        goto Exit;
+
+    if ((ret = phy_bus_read(phy_dev, MII_CTRL1000, &ctrl1000)))
+        goto Exit;
+
+    if ((ret = phy_bus_read(phy_dev, MII_ADVERTISE, &adv)))
+        goto Exit;
+
+    bmcr &= ~(BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000);
+    ctrl1000 &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL | ADVERTISE_REPEATER);
+    adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM | ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | ADVERTISE_100FULL);
+
+    if (caps & (PHY_CAP_1000_HALF | PHY_CAP_1000_FULL))
+        bmcr |= BMCR_SPEED1000;
+    else if (caps & (PHY_CAP_100_HALF | PHY_CAP_100_FULL))
+        bmcr |= BMCR_SPEED100;
+
+    if (caps & (PHY_CAP_10_FULL | PHY_CAP_100_FULL | PHY_CAP_1000_FULL))
+        bmcr |= BMCR_FULLDPLX;
+
+    if (caps & (PHY_CAP_1000_HALF | PHY_CAP_1000_FULL))
+        caps |= PHY_CAP_AUTONEG;
+
+    if (caps & PHY_CAP_AUTONEG)
+    {
+        bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
+
+        if (caps & PHY_CAP_PAUSE)
+            adv |= ADVERTISE_PAUSE_CAP;
+
+        if (caps & PHY_CAP_PAUSE_ASYM)
+            adv |= ADVERTISE_PAUSE_ASYM;
+
+        if (caps & PHY_CAP_10_HALF)
+            adv |= ADVERTISE_10HALF;
+
+        if (caps & PHY_CAP_10_FULL)
+            adv |= ADVERTISE_10FULL;
+
+        if (caps & PHY_CAP_100_HALF)
+            adv |= ADVERTISE_100HALF;
+
+        if (caps & PHY_CAP_100_FULL)
+            adv |= ADVERTISE_100FULL;
+
+        if (caps & PHY_CAP_1000_HALF)
+            ctrl1000 |= ADVERTISE_1000HALF;
+
+        if (caps & PHY_CAP_1000_FULL)
+            ctrl1000 |= ADVERTISE_1000FULL;
+
+        if (caps & PHY_CAP_REPEATER)
+            ctrl1000 |= ADVERTISE_REPEATER;
+    }
+
+    if ((ret = phy_bus_write(phy_dev, MII_ADVERTISE, adv)))
+        goto Exit;
+
+    if ((ret = phy_bus_write(phy_dev, MII_CTRL1000, ctrl1000)))
+        goto Exit;
+
+    if ((ret = phy_bus_write(phy_dev, MII_BMCR, bmcr)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int mii_speed_set(phy_dev_t *phy_dev, phy_speed_t speed, phy_duplex_t duplex)
+{
+    int ret;
+    uint32_t caps;
+
+    if (speed == PHY_SPEED_UNKNOWN)
+    {
+        speed = PHY_SPEED_1000;
+        duplex = PHY_DUPLEX_FULL;
+    }
+
+    if ((ret = mii_caps_get(phy_dev, CAPS_TYPE_ADVERTISE, &caps)))
+        goto Exit;
+
+    caps &= ~(PHY_CAP_10_HALF | PHY_CAP_10_FULL |
+        PHY_CAP_100_HALF | PHY_CAP_100_FULL |
+        PHY_CAP_1000_HALF | PHY_CAP_1000_FULL);
+    caps |= PHY_CAP_AUTONEG;
+
+    switch (speed)
+    {
+    case PHY_SPEED_1000:
+        caps |= PHY_CAP_1000_HALF | ((duplex == PHY_DUPLEX_FULL) ? PHY_CAP_1000_FULL : 0);
+    case PHY_SPEED_100:
+        caps |= PHY_CAP_100_HALF | ((duplex == PHY_DUPLEX_FULL) ? PHY_CAP_100_FULL : 0);
+    case PHY_SPEED_10:
+        caps |= PHY_CAP_10_HALF | ((duplex == PHY_DUPLEX_FULL) ? PHY_CAP_10_FULL : 0);
+        break;
+    default:
+        break;
+    }
+
+    if ((ret = mii_caps_set(phy_dev, caps)))
+        goto Exit;
+
+Exit:
+    return ret;
+}
+
+int mii_init(phy_dev_t *phy_dev)
+{
+    int ret;
+    phy_speed_t speed = PHY_SPEED_100;
+    phy_duplex_t duplex = PHY_DUPLEX_FULL;
+
+    /* Reset phy */
+    if ((ret = phy_bus_write(phy_dev, MII_BMCR, BMCR_RESET)))
+        goto Exit;
+
+    if ((ret = mii_caps_set(phy_dev, PHY_CAP_AUTONEG | PHY_CAP_PAUSE | PHY_CAP_REPEATER)))
+        goto Exit;
+
+    /* Set supported speed */
+    if ((phy_dev->mii_type != PHY_MII_TYPE_MII) &&  (phy_dev->mii_type != PHY_MII_TYPE_TMII))
+        speed = PHY_SPEED_1000;
+
+    ret = mii_speed_set(phy_dev, speed, duplex);
+
+Exit:
+    return ret;
+}
+
+int mii_isolate_phy(phy_dev_t *phy, int isolate)
+{
+    uint16_t val;
+    int ret;
+    int enabled;
+
+    ret = phy_dev_power_get(phy, &enabled);
+    if (!enabled)
+        return -1;
+
+    ret += phy_bus_read(phy, MII_BMCR, &val);
+    if (isolate) {
+        val |= BMCR_ISOLATE;
+    } else {
+        val &= ~BMCR_ISOLATE;
+    }
+    ret += phy_bus_write(phy, MII_BMCR, val);
+    return ret;
+}
+
diff --git a/drivers/net/bcmbca/phy/phy_drv_mii.h b/drivers/net/bcmbca/phy/phy_drv_mii.h
new file mode 100644
index 0000000000..552ed98d92
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_mii.h
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Dec 2015
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+#ifndef __PHY_DRV_MII_H__
+#define __PHY_DRV_MII_H__
+
+#include "phy_drv.h"
+
+/* Generic MII registers shared by kernel and uboot network drivers */
+#define MII_BMCR                0x00    /* Basic mode control register          */
+#define MII_BMSR                0x01    /* Basic mode status register           */
+#define MII_PHYSID1             0x02    /* PHYS ID 1                            */
+#define MII_PHYSID2             0x03    /* PHYS ID 2                            */
+#define MII_ADVERTISE           0x04    /* Advertisement control reg            */
+#define MII_LPA                 0x05    /* Link partner ability reg             */
+#define MII_EXPANSION           0x06    /* Expansion register                   */
+#define MII_CTRL1000            0x09    /* 1000BASE-T control                   */
+#define MII_XCTL                0x10    /* PHY_Extended_ctl_Register            */
+#define MII_STAT1000            0x0a    /* 1000BASE-T status                    */
+#define MII_ESTATUS             0x0f    /* Extended Status                      */
+#define MII_DCOUNTER            0x12    /* Disconnect counter                   */
+#define MII_FCSCOUNTER          0x13    /* False carrier counter                */
+#define MII_NWAYTEST            0x14    /* N-way auto-neg test reg              */
+#define MII_RERRCOUNTER         0x15    /* Receive error counter                */
+#define MII_SREVISION           0x16    /* Silicon revision                     */
+#define MII_RESV1               0x17    /* Reserved...                          */
+#define MII_LBRERROR            0x18    /* Lpback, rx, bypass error             */
+#define MII_PHYADDR             0x19    /* PHY address                          */
+#define MII_RESV2               0x1a    /* Reserved...                          */
+#define MII_TPISTATUS           0x1b    /* TPI status for 10mbps                */
+#define MII_NCONFIG             0x1c    /* Network interface config             */
+#define MII_PTEST1_RDBRW        0x1f    /* Test register                        */
+
+/* Basic mode control register */
+#define BMCR_RESV               0x003f  /* Unused...                            */
+#define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)                  */
+#define BMCR_CTST               0x0080  /* Collision test                       */
+#define BMCR_FULLDPLX           0x0100  /* Full duplex                          */
+#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart             */
+#define BMCR_ISOLATE            0x0400  /* Isolate data paths from MII          */
+#define BMCR_POWERDOWN          0x0800  /* Enable low power state               */
+#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation              */
+#define BMCR_SPEED100           0x2000  /* Select 100Mbps                       */
+#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits                    */
+#define BMCR_RESET              0x8000  /* Reset to default state               */
+
+/* Basic mode status register */
+#define BMSR_ERCAP              0x0001  /* Ext-reg capability                   */
+#define BMSR_JCD                0x0002  /* Jabber detected                      */
+#define BMSR_LSTATUS            0x0004  /* Link status                          */
+#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation          */
+#define BMSR_RFAULT             0x0010  /* Remote fault detected                */
+#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete            */
+#define BMSR_RESV               0x00c0  /* Unused...                            */
+#define BMSR_ESTATEN            0x0100  /* Extended Status in R15               */
+#define BMSR_100HALF2           0x0200  /* Can do 100BASE-T2 HDX                */
+#define BMSR_100FULL2           0x0400  /* Can do 100BASE-T2 FDX                */
+#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex           */
+#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex           */
+#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex          */
+#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex          */
+#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets           */
+
+/* Advertisement control register */
+#define ADVERTISE_SLCT          0x001f  /* Selector bits                        */
+#define ADVERTISE_CSMA          0x0001  /* Only selector supported              */
+#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex           */
+#define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex       */
+#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex           */
+#define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex       */
+#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex          */
+#define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause             */
+#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex          */
+#define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause        */
+#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets           */
+#define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause                        */
+#define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause              */
+#define ADVERTISE_RESV          0x1000  /* Unused...                            */
+#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults             */
+#define ADVERTISE_LPACK         0x4000  /* Ack link partners response           */
+#define ADVERTISE_NPAGE         0x8000  /* Next page bit                        */
+
+#define ADVERTISE_FULL          (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)
+#define ADVERTISE_ALL           (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register */
+#define LPA_SLCT                0x001f  /* Same as advertise selector           */
+#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex            */
+#define LPA_1000XFULL           0x0020  /* Can do 1000BASE-X full-duplex        */
+#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex            */
+#define LPA_1000XHALF           0x0040  /* Can do 1000BASE-X half-duplex        */
+#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex           */
+#define LPA_1000XPAUSE          0x0080  /* Can do 1000BASE-X pause              */
+#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex           */
+#define LPA_1000XPAUSE_ASYM     0x0100  /* Can do 1000BASE-X pause asym         */
+#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets            */
+#define LPA_PAUSE_CAP           0x0400  /* Can pause                            */
+#define LPA_PAUSE_ASYM          0x0800  /* Can pause asymetrically              */
+#define LPA_RESV                0x1000  /* Unused...                            */
+#define LPA_RFAULT              0x2000  /* Link partner faulted                 */
+#define LPA_LPACK               0x4000  /* Link partner acked us                */
+#define LPA_NPAGE               0x8000  /* Next page bit                        */
+
+#define LPA_DUPLEX              (LPA_10FULL | LPA_100FULL)
+#define LPA_100                 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation */
+#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego               */
+#define EXPANSION_LCWP          0x0002  /* Got new RX page code word            */
+#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words             */
+#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage          */
+#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected             */
+#define EXPANSION_RESV          0xffe0  /* Unused...                            */
+
+#define ESTATUS_1000_TFULL      0x2000  /* Can do 1000BT Full                   */
+#define ESTATUS_1000_THALF      0x1000  /* Can do 1000BT Half                   */
+
+/* N-way test register */
+#define NWAYTEST_RESV1          0x00ff  /* Unused...                            */
+#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way            */
+#define NWAYTEST_RESV2          0xfe00  /* Unused...                            */
+
+/* 1000BASE-T Control register */
+#define ADVERTISE_REPEATER      0x0400  /* Advertise Repeater mode              */
+#define ADVERTISE_1000FULL      0x0200  /* Advertise 1000BASE-T full duplex     */
+#define ADVERTISE_1000HALF      0x0100  /* Advertise 1000BASE-T half duplex     */
+#define CTL1000_AS_MASTER       0x0800
+#define CTL1000_ENABLE_MASTER   0x1000
+
+/* 1000BASE-T Status register */
+#define LPA_1000LOCALRXOK       0x2000  /* Link partner local receiver status   */
+#define LPA_1000REMRXOK         0x1000  /* Link partner remote receiver status  */
+#define LPA_1000FULL            0x0800  /* Link partner 1000BASE-T full duplex  */
+#define LPA_1000HALF            0x0400  /* Link partner 1000BASE-T half duplex  */
+
+int mii_phyid_get(phy_dev_t *phy_dev, uint32_t *phyid);
+int mii_autoneg_restart(phy_dev_t *phy_dev);
+int mii_power_get(phy_dev_t *phy_dev, int *enable);
+int mii_power_set(phy_dev_t *phy_dev, int enable);
+int mii_speed_set(phy_dev_t *phy_dev, phy_speed_t speed, phy_duplex_t duplex);
+int mii_caps_get(phy_dev_t *phy_dev, int caps_type, uint32_t *caps);
+int mii_caps_set(phy_dev_t *phy_dev, uint32_t caps);
+int mii_init(phy_dev_t *phy_dev);
+int mii_stat_get(phy_dev_t *phy_dev, uint32_t *stat);
+int mii_isolate_phy(phy_dev_t *phy, int isolate);
+
+#endif
+
diff --git a/drivers/net/bcmbca/phy/phy_drv_sgmii_plus2.c b/drivers/net/bcmbca/phy/phy_drv_sgmii_plus2.c
new file mode 100644
index 0000000000..9dfed91ed1
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_sgmii_plus2.c
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Aug 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Common functions for SGMIIPLUS2 core
+ */
+
+#include "bus_drv.h"
+#include "phy_drv.h"
+#include "phy_drv_mii.h"
+#include "phy_drv_sgmii_plus2.h"
+
+#define XGXS_STATUS1     0x8122
+
+static prog_entry_t toggle_pll75[] = {
+    { "XGXSBlk2 Block Address",         0x1f, 0x8100 },
+    { "Override pin, use mdio",         0x16, 0x0020 },
+    { "TxPLL Block Address",            0x1f, 0x8050 },
+    { "Toggle mmd_resetb to 0",         0x14, 0x8021 },
+    { "Toggle mmd_resetb to 1",         0x14, 0x8821 },
+    { "BLK0 Block Address",             0x1f, 0x8000 },
+    { NULL,                             0x00, 0x0000 }
+};
+
+static prog_entry_t refclk50m_vco6p25g[] = {
+    { "Digital Block Address",          0x1f, 0x8300 },
+    { "refclk_sel=3'h6 (50 MHz)",       0x18, 0xc000 },
+    { "PLL AFE Block Address",          0x1f, 0x8050 },
+    { "pll_afectrl0",                   0x10, 0x5740 },
+    { "pll_afectrl1",                   0x11, 0x01d0 },
+    { "pll_afectrl2",                   0x12, 0x19f0 },
+    { "pll_afectrl3",                   0x13, 0xaab0 },
+    { "pll_afectrl4",                   0x14, 0x8821 },
+    { "pll_afectrl5",                   0x15, 0x0044 },
+    { "pll_afectrl6",                   0x16, 0x8000 },
+    { "pll_afectrl7",                   0x17, 0x0872 },
+    { "pll_afectrl8",                   0x18, 0x0000 },
+    { "BLK0 Block Address",             0x1f, 0x8000 },
+    { NULL,                             0x00, 0x0000 }
+};
+
+static prog_entry_t refclk80m_vco6p25g[] = {
+    { "Digital Block Address",          0x1f, 0x8300 },
+    { "refclk_sel=3'h7 (80 MHz)",       0x18, 0xe000 },
+    { "PLL AFE Block Address",          0x1f, 0x8050 },
+    { "pll_afectrl0",                   0x10, 0x5740 },
+    { "pll_afectrl1",                   0x11, 0x01d0 },
+    { "pll_afectrl2",                   0x12, 0x59f0 },
+    { "pll_afectrl3",                   0x13, 0xaa80 },
+    { "pll_afectrl4",                   0x14, 0x8821 },
+    { "pll_afectrl5",                   0x15, 0x0044 },
+    { "pll_afectrl6",                   0x16, 0x8800 },
+    { "pll_afectrl7",                   0x17, 0x0813 },
+    { "pll_afectrl8",                   0x18, 0x0000 },
+    { "BLK0 Block Address",             0x1f, 0x8000 },
+    { NULL,                             0x00, 0x0000 }
+};
+
+static prog_entry_t refclk125m_vco6p25g[] = {
+    { "Digital Block Address",          0x1f, 0x8300 },
+    { "refclk_sel=3'h2 (125 MHz)",      0x18, 0x4000 },
+    { "PLL AFE Block Address",          0x1f, 0x8050 },
+    { "pll_afectrl0",                   0x10, 0x5740 },
+    { "pll_afectrl1",                   0x11, 0x01d0 },
+    { "pll_afectrl2",                   0x12, 0x19f0 },
+    { "pll_afectrl3",                   0x13, 0x2b00 },
+    { "pll_afectrl4",                   0x14, 0x0023 },
+    { "pll_afectrl5",                   0x15, 0x0044 },
+    { "pll_afectrl6",                   0x16, 0x0000 },
+    { "pll_afectrl7",                   0x17, 0x0000 },
+    { "pll_afectrl8",                   0x18, 0x0000 },
+    { "BLK0 Block Address",             0x1f, 0x8000 },
+    { NULL,                             0x00, 0x0000 }
+};
+
+static prog_entry_t disable_afe_limit_amp[] = {
+    { "RX3 Slicer",                     0x1f, 0x8480 },
+    { "disable lmtcal",                 0x12, 0x83f8 },
+    { "BLK0 Block Address",             0x1f, 0x8000 },
+    { NULL,                             0x00, 0x0000 }
+};
+
+static prog_entry_t disable_pll[] = {
+    { "BLK0 Block Address",             0x1f, 0x8000 },
+    { "disable pll start sequencer",    0x10, 0x0c2f },
+    { NULL,                             0x00, 0x0000 }
+}; 
+
+static prog_entry_t enable_pll[] = {
+    { "BLK0 Block Address",             0x1f, 0x8000 },
+    { "enable pll start sequencer",     0x10, 0x2c2f },
+    { NULL,                             0x00, 0x0000 }
+}; 
+
+static prog_entry_t forced_speed_sgmii_os5[] = {
+    { "Digital Block Address",          0x1f, 0x8300 },
+    { "enable sgmii mode",              0x10, 0x0100 },
+    { "RX2 Block Address",              0x1f, 0x8470 },
+    { "Set step_one[1:0]",              0x13, 0x1251 },
+    { "Digital5 Block Address",         0x1f, 0x8340 },
+    { "set oversampling mode",          0x1a, 0x0003 },
+    { "BLK0 Block Address",             0x1f, 0x8000 },
+    { NULL,                             0x00, 0x0000 }
+}; 
+
+static prog_entry_t forced_speed_2p5g_phy[] = {
+    { "Digital Block Address",          0x1f, 0x8300 },
+    { "enable fiber mode",              0x10, 0x0101 },
+    { "Force 2.5G Fiber, 50MHz refclk", 0x18, 0xc010 },
+    { "Digital5 Block Address",         0x1f, 0x8340 },
+    { "Set os2 mode",                   0x1a, 0x0001 },
+    { "BLK0 Block Address",             0x1f, 0x8000 },
+    { NULL,                             0x00, 0x0000 }
+};
+
+int sgmii_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val)
+{
+    int ret;
+
+    if (reg & 0x8000)
+    {
+        if ((ret = phy_bus_write(phy_dev, 0x1f, reg & 0xfff0)))
+            goto Exit;
+
+        if ((ret = phy_bus_read(phy_dev,  0x10 | (reg & 0x000f), val)))
+            goto Exit;
+
+        if ((ret = phy_bus_write(phy_dev, 0x1f, 0x8000)))
+            goto Exit;
+    }
+    else
+    {
+        if ((ret = phy_bus_read(phy_dev,  reg, val)))
+            goto Exit;
+    }
+
+Exit:
+    return ret;
+}
+
+int sgmii_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val)
+{
+    int ret;
+
+    if (reg & 0x8000)
+    {
+        if ((ret = phy_bus_write(phy_dev, 0x1f, reg & 0xfff0)))
+            goto Exit;
+
+        if ((ret = phy_bus_write(phy_dev,  0x10 | (reg & 0x000f), val)))
+            goto Exit;
+
+        if ((ret = phy_bus_write(phy_dev, 0x1f, 0x8000)))
+            goto Exit;
+    }
+    else
+    {
+        if ((ret = phy_bus_write(phy_dev,  reg, val)))
+            goto Exit;
+    }
+
+Exit:
+    return ret;
+}
+
+int sgmii_read_status(phy_dev_t *phy_dev)
+{
+    uint16_t val;
+    int ret, speed, duplex;
+
+    phy_dev->link = 0;
+    phy_dev->speed = PHY_SPEED_UNKNOWN;
+    phy_dev->duplex = PHY_DUPLEX_UNKNOWN;
+
+    if ((ret = sgmii_read(phy_dev, XGXS_STATUS1, &val)))
+        return ret;
+
+    phy_dev->link = ((val >> 8) & 0x1);
+
+    if (!phy_dev->link)
+        return 0;
+
+    speed = val & 0x3;
+    duplex = 1; /* ??? */
+
+    if (speed == 0)
+        phy_dev->speed = PHY_SPEED_10;
+    else if (speed == 1)
+        phy_dev->speed = PHY_SPEED_100;
+    else if (speed == 2)
+        phy_dev->speed = PHY_SPEED_1000;
+    else if (speed == 3)
+        phy_dev->speed = PHY_SPEED_2500;
+
+    phy_dev->duplex = duplex ? PHY_DUPLEX_FULL : PHY_DUPLEX_HALF;
+
+    return 0;
+}
+
+int sgmii_refclk_init(phy_dev_t *phy_dev, sgmii_refclk_t refclk)
+{
+    if (refclk == SGMII_REFCLK_50)
+        phy_dev_prog(phy_dev, refclk50m_vco6p25g);
+
+    if (refclk == SGMII_REFCLK_80)
+        phy_dev_prog(phy_dev, refclk80m_vco6p25g);
+
+    if (refclk == SGMII_REFCLK_125)
+        phy_dev_prog(phy_dev, refclk125m_vco6p25g);
+
+    return 0;
+}
+
+int sgmii_speed_set(phy_dev_t *phy_dev, phy_speed_t speed)
+{
+    int ret = 0;
+    uint16_t bmcr;
+    prog_entry_t *prog = NULL;
+
+    switch (speed)
+    {
+    case PHY_SPEED_UNKNOWN:
+    {
+        bmcr = 0x1140;
+        prog = forced_speed_sgmii_os5; 
+        break;
+    }
+    case PHY_SPEED_10:
+    {
+        bmcr = 0x0100;
+        prog = forced_speed_sgmii_os5; 
+        break;
+    }
+    case PHY_SPEED_100:
+    {
+        bmcr = 0x2100;
+        prog = forced_speed_sgmii_os5; 
+        break;
+    }
+    case PHY_SPEED_1000:
+    {
+        bmcr = 0x0140;
+        prog = forced_speed_sgmii_os5; 
+        break;
+    }
+    case PHY_SPEED_2500:
+    {
+        bmcr = 0x0140;
+        prog = forced_speed_2p5g_phy; 
+        break;
+    }
+    default:
+        goto Exit;
+    }
+
+    if ((ret = sgmii_write(phy_dev, 0x00, 0x8000)))
+        goto Exit;
+
+    udelay(10000);
+
+    phy_dev_prog(phy_dev, disable_pll);
+    phy_dev_prog(phy_dev, refclk50m_vco6p25g);
+    phy_dev_prog(phy_dev, toggle_pll75);
+    phy_dev_prog(phy_dev, disable_afe_limit_amp);
+    phy_dev_prog(phy_dev, prog);
+
+    if ((ret = sgmii_write(phy_dev, 0x00, bmcr)))
+        goto Exit;
+
+    phy_dev_prog(phy_dev, enable_pll);
+
+    udelay(10000);
+    udelay(10000);
+
+Exit:
+    return ret;
+}
diff --git a/drivers/net/bcmbca/phy/phy_drv_sgmii_plus2.h b/drivers/net/bcmbca/phy/phy_drv_sgmii_plus2.h
new file mode 100644
index 0000000000..a95dd98166
--- /dev/null
+++ b/drivers/net/bcmbca/phy/phy_drv_sgmii_plus2.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Aug 2016
+ *      Author: yuval.raviv@broadcom.com
+ */
+
+/*
+ * Common functions for SGMIIPLUS2 core
+ */
+
+#ifndef __PHY_DRV_SGMII_PLUS2_H__
+#define __PHY_DRV_SGMII_PLUS2_H__
+
+#include "phy_drv.h"
+
+typedef enum
+{
+    SGMII_REFCLK_UNKNOWN,
+    SGMII_REFCLK_50,
+    SGMII_REFCLK_80,
+    SGMII_REFCLK_125,
+} sgmii_refclk_t;
+
+int sgmii_read(phy_dev_t *phy_dev, uint16_t reg, uint16_t *val);
+int sgmii_write(phy_dev_t *phy_dev, uint16_t reg, uint16_t val);
+
+int sgmii_speed_set(phy_dev_t *phy_dev, phy_speed_t speed);
+int sgmii_refclk_init(phy_dev_t *phy_dev, sgmii_refclk_t refclk);
+int sgmii_read_status(phy_dev_t *phy_dev);
+
+#endif
+
diff --git a/drivers/net/bcmbca/phy/unimac_drv.h b/drivers/net/bcmbca/phy/unimac_drv.h
new file mode 100644
index 0000000000..bb6ad24d7a
--- /dev/null
+++ b/drivers/net/bcmbca/phy/unimac_drv.h
@@ -0,0 +1,586 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2013 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the definition for the Unimac block 			          */
+/*                                                                            */
+/******************************************************************************/
+#ifndef __UNIMAC_DRV_H
+#define __UNIMAC_DRV_H
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+
+#include "os_dep.h"
+#include "hwapi_mac.h"
+#if defined(CONFIG_BCM947622)
+#define WRITE_32(a, r)			( *(volatile uint32_t*)(a) = *(uint32_t*)&(r) )
+#define READ_32(a, r)			( *(volatile uint32_t*)&(r) = *(volatile uint32_t*) (a) )
+#define VAL32(_a)               ( *(volatile uint32_t*)(_a))
+#else
+#include "access_macros.h"
+#endif
+
+#if !defined(CONFIG_BCM963138) && !defined(CONFIG_BCM963148) && !defined(CONFIG_BCM94908)
+#define swap4bytes(x)    (x)
+#endif
+
+extern uintptr_t unimac_conf_base;
+extern uintptr_t unimac_mib_base;
+extern uintptr_t unimac_top_base;
+extern uint32_t conf_offset;
+extern uint32_t mib_offset;
+extern uint32_t top_offset;
+extern uint32_t mib_step;
+
+#define UNIMAC_CFG_BASE                     unimac_conf_base     
+#define UNIMAC_MIB_BASE                     unimac_mib_base
+#define UNIMAC_TOP_BASE                     unimac_top_base
+
+#define MAX_NUM_OF_EMACS                    8
+#define UNIMAC_CONF_INSTANCE_OFFSET(e)      ((e) * conf_offset)
+#define UNIMAC_MIB_INSTANCE_OFFSET(e)       ((e) * mib_offset)
+#define UNIMAC_MISC_INSTANCE_OFFSET(e)      ((e) * top_offset)
+#define MIB_STEP                            mib_step
+
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+
+#define UNIMAC_CONFIGURATION_UMAC_0_UMAC_DUMMY              UNIMAC_CFG_BASE + 0x0000    /* UniMAC Dummy Register */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_HD_BKP_CNTL         UNIMAC_CFG_BASE + 0x0004    /* UniMAC Half Duplex Backpressure Control Register */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD                 UNIMAC_CFG_BASE + 0x0008    /* UniMAC Command Register */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_MAC0                UNIMAC_CFG_BASE + 0x000c    /* UniMAC MAC address first 4 bytes*/
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_MAC1                UNIMAC_CFG_BASE + 0x0010    /* UniMAC MAC address 2 last bytes*/
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_FRM_LEN             UNIMAC_CFG_BASE + 0x0014    /* UniMAC Frame Length */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_QUNAT         UNIMAC_CFG_BASE + 0x0018    /* UniMAC Pause Quanta */
+#define UNIMAC_CONFIGURATION_UMAC_0_SFD_OFFSET              UNIMAC_CFG_BASE + 0x0040    /* UniMAC EFM Preamble Length */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_MODE                UNIMAC_CFG_BASE + 0x0044    /* UniMAC Mode */
+#define UNIMAC_CONFIGURATION_UMAC_0_FRM_TAG0                UNIMAC_CFG_BASE + 0x0048    /* UniMAC Preamble Outer TAG 0 */
+#define UNIMAC_CONFIGURATION_UMAC_0_FRM_TAG1                UNIMAC_CFG_BASE + 0x004c    /* UniMAC Preamble Outer TAG 1 */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_TX_IPG_LEN          UNIMAC_CFG_BASE + 0x005c    /* UniMAC Inter Packet Gap */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_CTRL            UNIMAC_CFG_BASE + 0x0064    /* UniMAC Energy Efficient Ethernet Control */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_LPI_TIMER       UNIMAC_CFG_BASE + 0x0068    /* EEE LPI timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_WAKE_TIMER      UNIMAC_CFG_BASE + 0x006c    /* EEE wakeup timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_REF_COUNT       UNIMAC_CFG_BASE + 0x0070    /* UniMAC Energy Efficient Ethernet Ref Clock Speed */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_MII_LPI_TIMER   UNIMAC_CFG_BASE + 0x0068    /* MII EEE LPI timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_GMII_LPI_TIMER  UNIMAC_CFG_BASE + 0x006c    /* GMII EEE LPI timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_MII_WAKE_TIMER  UNIMAC_CFG_BASE + 0x0080    /* MII EEE wakeup timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_EEE_GMII_WAKE_TIMER UNIMAC_CFG_BASE + 0x0084    /* GMII EEE wakeup timer */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_CNTRL         UNIMAC_CFG_BASE + 0x0330    /* UniMAC Repetitive Pause Control in TX direction */
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_RX_MAX_PKT_SIZE     UNIMAC_CFG_BASE + 0x0608    /* UniMAC RX MAX packet Size Register */
+
+
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR64      UNIMAC_MIB_BASE + 0x0000*MIB_STEP   /* Receive 64B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR127     UNIMAC_MIB_BASE + 0x0004*MIB_STEP   /* Receive 65B to 127B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR255     UNIMAC_MIB_BASE + 0x0008*MIB_STEP   /* Receive 128B to 255B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR511     UNIMAC_MIB_BASE + 0x000c*MIB_STEP   /* Receive 256B to 511B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR1023    UNIMAC_MIB_BASE + 0x0010*MIB_STEP   /* Receive 512B to 1023B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR1518    UNIMAC_MIB_BASE + 0x0014*MIB_STEP   /* Receive 1024B to 1518B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRMGV     UNIMAC_MIB_BASE + 0x0018*MIB_STEP   /* Receive 1519B to 1522B Good VLAN Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR2047    UNIMAC_MIB_BASE + 0x001c*MIB_STEP   /* Receive 1519B to 2047B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR4095    UNIMAC_MIB_BASE + 0x0020*MIB_STEP   /* Receive 2048B to 4095B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GR9216    UNIMAC_MIB_BASE + 0x0024*MIB_STEP   /* Receive 4096B to 9216B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRPKT     UNIMAC_MIB_BASE + 0x0028*MIB_STEP   /* Receive Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRBYT     UNIMAC_MIB_BASE + 0x002c*MIB_STEP   /* Receive Byte Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRMCA     UNIMAC_MIB_BASE + 0x0030*MIB_STEP   /* Receive Multicast Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRBCA     UNIMAC_MIB_BASE + 0x0034*MIB_STEP   /* Receive Broadcast Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRFCS     UNIMAC_MIB_BASE + 0x0038*MIB_STEP   /* Receive FCS Error Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRXCF     UNIMAC_MIB_BASE + 0x003c*MIB_STEP   /* Receive Control Frame Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRXPF     UNIMAC_MIB_BASE + 0x0040*MIB_STEP   /* Receive Pause Frame Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRXUO     UNIMAC_MIB_BASE + 0x0044*MIB_STEP   /* Receive Unknown OP Code Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRALN     UNIMAC_MIB_BASE + 0x0048*MIB_STEP   /* Receive Alignmenet Error Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRFLR     UNIMAC_MIB_BASE + 0x004c*MIB_STEP   /* Receive Frame Length Out Of Range Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRCDE     UNIMAC_MIB_BASE + 0x0050*MIB_STEP   /* Receive Code Error Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRFCR     UNIMAC_MIB_BASE + 0x0054*MIB_STEP   /* Receive Carrier Sense Error Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GROVR     UNIMAC_MIB_BASE + 0x0058*MIB_STEP   /* Receive Oversize Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRJBR     UNIMAC_MIB_BASE + 0x005c*MIB_STEP   /* Receive Jabber Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRMTUE    UNIMAC_MIB_BASE + 0x0060*MIB_STEP   /* Receive MTU Error Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRPOK     UNIMAC_MIB_BASE + 0x0064*MIB_STEP   /* Receive Good Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRUC      UNIMAC_MIB_BASE + 0x0068*MIB_STEP   /* Receive Unicast Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRPPP     UNIMAC_MIB_BASE + 0x006c*MIB_STEP   /* Receive PPP Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GRCRC     UNIMAC_MIB_BASE + 0x0070*MIB_STEP   /* Receive CRC Match Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR64      UNIMAC_MIB_BASE + 0x0080*MIB_STEP   /* Transmit 64B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR127     UNIMAC_MIB_BASE + 0x0084*MIB_STEP   /* Transmit 65B to 127B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR255     UNIMAC_MIB_BASE + 0x0088*MIB_STEP   /* Transmit 128B to 255B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR511     UNIMAC_MIB_BASE + 0x008c*MIB_STEP   /* Transmit 256B to 511B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR1023    UNIMAC_MIB_BASE + 0x0090*MIB_STEP   /* Transmit 512B to 1023B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR1518    UNIMAC_MIB_BASE + 0x0094*MIB_STEP   /* Transmit 1024B to 1518B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TRMGV     UNIMAC_MIB_BASE + 0x0098*MIB_STEP   /* Transmit 1519B to 1522B Good VLAN Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR2047    UNIMAC_MIB_BASE + 0x009c*MIB_STEP   /* Transmit 1519B to 2047B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR4095    UNIMAC_MIB_BASE + 0x00a0*MIB_STEP   /* Transmit 2048B to 4095B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_TR9216    UNIMAC_MIB_BASE + 0x00a4*MIB_STEP   /* Transmit 4096B to 9216B Frame Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTPKT     UNIMAC_MIB_BASE + 0x00a8*MIB_STEP   /* Transmit Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTMCA     UNIMAC_MIB_BASE + 0x00ac*MIB_STEP   /* Transmit Multicast Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTBCA     UNIMAC_MIB_BASE + 0x00b0*MIB_STEP   /* Transmit Broadcast Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTXPF     UNIMAC_MIB_BASE + 0x00b4*MIB_STEP   /* Transmit Pause Frame Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTXCF     UNIMAC_MIB_BASE + 0x00b8*MIB_STEP   /* Transmit Control Frame Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTFCS     UNIMAC_MIB_BASE + 0x00bc*MIB_STEP   /* Transmit FCS Error Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTOVR     UNIMAC_MIB_BASE + 0x00c0*MIB_STEP   /* Transmit Oversize Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTDRF     UNIMAC_MIB_BASE + 0x00c4*MIB_STEP   /* Transmit Deferral Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTEDF     UNIMAC_MIB_BASE + 0x00c8*MIB_STEP   /* Transmit Excessive Deferral Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTSCL     UNIMAC_MIB_BASE + 0x00cc*MIB_STEP   /* Transmit Single Collision Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTMCL     UNIMAC_MIB_BASE + 0x00d0*MIB_STEP   /* Transmit Multiple Collision Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTLCL     UNIMAC_MIB_BASE + 0x00d4*MIB_STEP   /* Transmit Late Collision Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTXCL     UNIMAC_MIB_BASE + 0x00d8*MIB_STEP   /* Transmit Excessive Collision Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTFRG     UNIMAC_MIB_BASE + 0x00dc*MIB_STEP   /* Transmit Fragments Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTNCL     UNIMAC_MIB_BASE + 0x00e0*MIB_STEP   /* Transmit Total Collision Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTJBR     UNIMAC_MIB_BASE + 0x00e4*MIB_STEP   /* Transmit Jabber Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTBYT     UNIMAC_MIB_BASE + 0x00e8*MIB_STEP   /* Transmit Byte Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTPOK     UNIMAC_MIB_BASE + 0x00ec*MIB_STEP   /* Transmit Good Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_GTUC      UNIMAC_MIB_BASE + 0x00f0*MIB_STEP   /* Transmit Unicast Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_RRPKT     UNIMAC_MIB_BASE + 0x0100*MIB_STEP   /* Receive RUNT Packet Counter */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_RRUND     UNIMAC_MIB_BASE + 0x0104*MIB_STEP   /* Receive RUNT Packet And Contain A Valid FCS */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_RRFRG     UNIMAC_MIB_BASE + 0x0108*MIB_STEP   /* Receive RUNT Packet And Contain Invalid FCS or Alignment Error */
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_RRBYT     UNIMAC_MIB_BASE + 0x010c*MIB_STEP   /* Receive RUNT Packet Byte Counter */
+#if defined(CONFIG_BCM963146) || defined(CONFIG_BCM94912)
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_MIB_CNTRL UNIMAC_MIB_BASE + 0x0140*MIB_STEP   /* MIB Control Register */
+#else
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_MIB_CNTRL UNIMAC_MIB_BASE + 0x0180*MIB_STEP   /* MIB Control Register */
+#endif
+
+#if defined(CONFIG_BCM947622)
+#define UNIMAC_TOPCTRL_MIB_MAX_PKT_SIZE                     SYSPORT_0_BASE  + 0x0028    /* Value by MIB to differentiate regular and oversized packets */
+#else
+#define UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG                   UNIMAC_TOP_BASE + 0x0000    /* UNIMAC_CFG Register */
+#define UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1              UNIMAC_TOP_BASE + 0x0004    /* UNIMAC_EXT_CFG1 Register */
+#define UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2              UNIMAC_TOP_BASE + 0x0008    /* UNIMAC_EXT_CFG2 Register */
+#endif
+
+
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_HD_BKP_CNTL_ipg_config_rx_MASK          0x0000007c
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_HD_BKP_CNTL_ipg_config_rx_SHIFT         2
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_HD_BKP_CNTL_hd_fc_ena_MASK              0x00000001
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_HD_BKP_CNTL_hd_fc_ena_SHIFT             0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_txrx_en_config_MASK                 0x20000000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_txrx_en_config_SHIFT                29
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_tx_pause_ignore_MASK                0x10000000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_tx_pause_ignore_SHIFT               28
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rmt_loop_ena_MASK                   0x02000000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rmt_loop_ena_SHIFT                  25
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_cntl_frm_ena_MASK                   0x00800000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_cntl_frm_ena_SHIFT                  23
+#if defined(CONFIG_BCM947622)
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_override_rx_MASK                 0x00040000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_override_rx_SHIFT                18
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_override_tx_MASK                 0x00020000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_override_tx_SHIFT                17
+#endif
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_lcl_loop_ena_MASK                   0x00008000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_lcl_loop_ena_SHIFT                  15
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_reset_MASK                       0x00002000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_sw_reset_SHIFT                      13
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_hd_ena_MASK                         0x00000400
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_hd_ena_SHIFT                        10
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rx_pause_ignore_MASK                0x00000100
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rx_pause_ignore_SHIFT               8
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_pause_fwd_MASK                      0x00000080
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_pause_fwd_SHIFT                     7
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_crc_fwd_MASK                        0x00000040
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_crc_fwd_SHIFT                       6
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_pad_en_MASK                         0x00000020
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_pad_en_SHIFT                        5
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_eth_speed_MASK                      0x0000000c
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_eth_speed_SHIFT                     2
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rx_ena_MASK                         0x00000002
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_rx_ena_SHIFT                        1
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_tx_ena_MASK                         0x00000001
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_CMD_tx_ena_SHIFT                        0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_FRM_LEN_frame_length_MASK               0x00003fff
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_FRM_LEN_frame_length_SHIFT              0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_TX_IPG_LEN_tx_ipg_len_MASK              0x0000007f
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_TX_IPG_LEN_tx_ipg_len_SHIFT             0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_TX_IPG_LEN_tx_min_pkt_size_MASK         0x00007F00
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_TX_IPG_LEN_tx_min_pkt_size_SHIFT        8
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_RX_MAX_PKT_SIZE_max_pkt_size_MASK       0x00003fff
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_RX_MAX_PKT_SIZE_max_pkt_size_SHIFT      0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_CNTRL_pause_control_en_MASK       0x00020000
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_CNTRL_pause_control_en_SHIFT      17
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_CNTRL_pause_timer_MASK            0x0001ffff
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_CNTRL_pause_timer_SHIFT           0
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_QUNAT_pause_quant_MASK            0x0000ffff
+#define UNIMAC_CONFIGURATION_UMAC_0_RDP_PAUSE_QUNAT_pause_quant_SHIFT           0
+
+#define UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT          1 << 16
+
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_MIB_CNTRL_rx_cnt_st_MASK      0x00000001
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_MIB_CNTRL_rx_cnt_st_SHIFT     0
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_MIB_CNTRL_tx_cnt_rst_MASK     0x00000004
+#define UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_MIB_CNTRL_tx_cnt_rst_SHIFT    2
+
+/* Macros for reading and writing UNIMAC_CONFIGURATION registers*/
+
+#define UNIMAC_READ32_REG(e,r,o) READ_32( UNIMAC_CONFIGURATION_UMAC_0_RDP_##r + UNIMAC_CONF_INSTANCE_OFFSET(e) , (o) )
+
+#define UNIMAC_WRITE32_REG(e,r,i) WRITE_32( UNIMAC_CONFIGURATION_UMAC_0_RDP_##r  + UNIMAC_CONF_INSTANCE_OFFSET(e) , (i) )
+
+#define UNIMAC_READ_FIELD(e,r,f,o) \
+	 ( *(volatile uint32_t*)&(o) = (swap4bytes(VAL32(UNIMAC_CONFIGURATION_UMAC_0_RDP_##r + UNIMAC_CONF_INSTANCE_OFFSET(e) ))   & \
+		 UNIMAC_CONFIGURATION_UMAC_0_RDP_##r##_##f##_MASK ) >> UNIMAC_CONFIGURATION_UMAC_0_RDP_##r##_##f##_SHIFT  )
+
+#define UNIMAC_WRITE_FIELD(e,r,f,i) \
+	    ( ( VAL32(UNIMAC_CONFIGURATION_UMAC_0_RDP_##r + UNIMAC_CONF_INSTANCE_OFFSET(e) ) ) = \
+		( VAL32(UNIMAC_CONFIGURATION_UMAC_0_RDP_##r +  UNIMAC_CONF_INSTANCE_OFFSET(e))  & swap4bytes(~UNIMAC_CONFIGURATION_UMAC_0_RDP_##r##_##f##_MASK) ) | \
+		( swap4bytes(( (i) << UNIMAC_CONFIGURATION_UMAC_0_RDP_##r##_##f##_SHIFT ) & UNIMAC_CONFIGURATION_UMAC_0_RDP_##r##_##f##_MASK)) )
+
+/*Macros for reading and Writing UNIMAC_MIB counters*/
+
+#define UNIMAC_READ32_MIB(e,r,o) READ_32( UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r + UNIMAC_MIB_INSTANCE_OFFSET(e) , (o) )
+
+#define UNIMAC_WRITE32_MIB(e,r,i) WRITE_32( UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r  + UNIMAC_MIB_INSTANCE_OFFSET(e) , (i) )
+
+#define UNIMAC_READ_MIB_FIELD(e,r,f,o) \
+	 ( *(volatile uint32_t*)&(o) = (* ((volatile uint32_t*) DEVICE_ADDRESS(UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r + UNIMAC_MIB_INSTANCE_OFFSET(e) ) )  & \
+		 UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r##_##f##_MASK ) >> UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r##_##f##_SHIFT  )
+
+#define UNIMAC_WRITE_MIB_FIELD(e,r,f,i) \
+	    ( ( VAL32(UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r + UNIMAC_MIB_INSTANCE_OFFSET(e)) ) = \
+		( VAL32(UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r +  UNIMAC_MIB_INSTANCE_OFFSET(e))  & swap4bytes(~UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r##_##f##_MASK) ) | \
+		( swap4bytes(( (i) << UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r##_##f##_SHIFT ) & UNIMAC_CONFIGURATION_UMAC_MIB_0Module_RDP_##r##_##f##_MASK)) )
+
+
+typedef enum
+{
+	UNIMAC_SPEED_10,
+	UNIMAC_SPEED_100,
+	UNIMAC_SPEED_1000,
+	UNIMAC_SPEED_2500
+}UNIMAC_SPEED;
+
+typedef enum
+{
+	UNIMAC_DUPLEX_HALF,
+	UNIMAC_DUPLEX_FULL
+}UNIMAC_DUPLEX;
+
+
+#ifndef _BYTE_ORDER_LITTLE_ENDIAN_
+typedef struct 
+{
+	/*Reserved bit must be written with 0.  A read returns an unknown value.*/
+	uint32_t	reserved3:1;
+	/*Disable RX side RUNT filtering. 0: Enable  RUNT filtering.Reset value is 0x0. */
+	uint32_t	runt_filter_dis:1;
+	/*	This mode only works in auto-config mode: 
+		0: After auto-config, TX_ENA and RX_ENA bits are set to 1. 1: After auto-config, TX_ENA and RX_ENA bits are set to 0,    
+		meaning SW will have to come in and enable TX and RX.Reset value is 0x0. */
+	uint32_t	txrx_en_config:1;
+	/*Ignore TX PAUSE frame transmit request.Reset value is 0x0. */
+	uint32_t	tx_pause_ignore:1;
+	/*Enable extract/insert of EFM headers.Reset value is 0x0. */
+	uint32_t	prbl_ena:1;
+	/*This bit currently not used.Reset value is 0x0.*/
+	uint32_t	rx_err_disc:1;  
+	/*Enable remote loopback at the fifo system side. 0: Normal operation.Reset value is 0x0. */
+	uint32_t	rmt_loop_ena:1;
+	/*Payload length check. 0: Check payload length with Length/Type field. 1: Check disabled.Reset value is 0x1. */
+	uint32_t	no_lgth_check:1;
+	/*	MAC control frame enable. 1: MAC control frames with opcode other than 0x0001 are accepted and forwarded to the client interface.
+		0: MAC control frames with opcode other than 0x0000 and 0x0001 are silently discarded.
+		Reset value is 0x0.
+	*/
+	uint32_t	cntl_frm_ena:1; 
+	/*Enable/Disable auto-configuration. 1: Enable  0: Disable Reset value is 0x0. */
+	uint32_t	ena_ext_config:1;
+	/*Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved2:6;
+	/*Enable GMII/MII loopback 1: Loopback enabled. 0: Normal operation.Reset value is 0x0. */
+	uint32_t 	lcl_loop_ena:1;
+	/*Reserved bit must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved1:1;
+	/*RX and RX engines are put in reset. 0: come out of SW reset.Reset value is 0x0. */
+	uint32_t	sw_reset:1; 
+	/* Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved0:2;
+	/* Ignored when RTH_SPEED[1]==1, gigabit mode. 1: half duplex 0: full duplex Reset value is 0x0.*/
+	uint32_t	hd_ena:1;
+	/*	The MAC overwrites the source MAC address with a programmed MAC address in register MAC_0 and MAC_1." 
+		0: Not modify the source address received from the transmit application client.
+		Reset value is 0x0.
+	*/
+	uint32_t	tx_addr_ins:1;
+	/*	Receive PAUSE frames are ignored by the MAC. 
+		0: The tramsmit process is stiooed for the amount of time specified in the pause wuanta received within the PAUSE frame.
+		Reset value is 0x0. 
+	*/
+	uint32_t	rx_pause_ignore:1;
+	/* 	PAUSE frames are forwarded to the user application. 
+		0: The PAUSE frames are terminated and discarded in the MAC.Reset value is 0x1. 
+	*/
+	uint32_t	pause_fwd:1;
+	/*	The CRC field of received frames is transmitted to the user application. 
+		0: The CRC field is stripped from the frame.Reset value is 0x1. 
+	*/
+	uint32_t	crc_fwd:1;
+	/*  Padding is removed along with crc field before the frame is sent to the user application. 
+		0: No padding is removed by the MAC.
+		Reset value is 0x0.
+	*/
+	uint32_t	pad_en:1; 
+	/* All frames are received without Unicast address filtering. 
+	   0: Reset value is 0x1. */
+	uint32_t 	promis_en:1;
+	/*00: 10Mbps, 01: 100Mbps, 10: 1000Mbps, 11: 2500Mbps Reset value is 0x2. */
+	uint32_t	eth_speed:2;
+	/* 	The MAC receive function is enabled. 0: The MAC receive function is disabled. 
+		The enable works on packet boundary meaning that only on the assertion on the bit during every 0->1 transition of rx_dv.
+		Reset value is 0x0. 
+	*/	
+	uint32_t	rx_ena:1;
+	/*	The MAC transmit function is enabled. 0: The MAC transmit function is disabled.
+		The enable works on packet boundary meaning that only on the assertion of the bit during every SOP.
+		Reset value is 0x0. 
+	*/
+	uint32_t    tx_ena:1;
+
+}S_UNIMAC_CMD_REG;
+
+typedef struct
+{
+
+	/* Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved:26;
+	/*Link status indication.Reset value is 0x0. */
+	uint32_t	mac_link_stat:1; 
+	/* 1: MAC Tx pause enabled. 0: MAC Tx pause disabled.Reset value is 0x1. */
+	uint32_t	mac_tx_pause:1;
+	/*1: MAC Rx pause enabled. 0: MAC Rx pause disabled.Reset value is 0x1. */
+	uint32_t	mac_rx_pause:1; 
+	/*1: Half duplex. 0: Full duplex. Reset value is 0x0. */
+	uint32_t	mac_duplex:1;
+	/* 00: 10Mbps, 01: 100Mbps, 10: 1Gbps, 11: 2.5Gbps Reset value is 0x2. 	*/
+	uint32_t	mac_speed:2;
+
+}S_UNIMAC_STAT_REG;
+
+typedef struct
+{
+	uint32_t	reserved:15;
+	uint32_t	pp_gen:1; 
+	uint32_t	pp_pse_en:8; 
+	uint32_t	launch_en:1; 
+	uint32_t	ext_tx_flow:1; 
+	uint32_t	mac_crc_owrt:1; 
+	uint32_t	mac_crc_fwd:1; 
+	uint32_t	txcrcerr:1;
+	uint32_t	ss_mode_mii:1; 
+	uint32_t	gport_mode:1;
+	uint32_t	gmii_direct:1;
+
+}S_UNIMAC_CFG_REG;
+
+typedef struct
+{
+    uint32_t    reserved:7;
+    uint32_t    rxfifo_congestion_threshold:9;
+    uint32_t    reserved1:2;
+    uint32_t    max_pkt_size:14;
+
+}S_UNIMAC_TOP_CFG1_REG;
+
+typedef struct
+{
+	uint32_t	reserved:24;
+	uint32_t	lp_idle_prediction_mode:1; 
+	uint32_t	dis_eee_10m:1; 
+	uint32_t	eee_txclk_dis:1; 
+	uint32_t	rx_fifo_check:1; 
+	uint32_t	eee_en:1;
+	uint32_t	en_lpi_tx_pause:1; 
+	uint32_t	en_lpi_tx_pfc:1;
+	uint32_t	en_lpi_rx_pause:1;
+}S_UNIMAC_EEE_CTRL_REG;
+
+#else /* little endian */
+
+typedef struct 
+{
+	/*	The MAC transmit function is enabled. 0: The MAC transmit function is disabled.
+		The enable works on packet boundary meaning that only on the assertion of the bit during every SOP.
+		Reset value is 0x0. 
+	*/
+	uint32_t    tx_ena:1;
+	/* 	The MAC receive function is enabled. 0: The MAC receive function is disabled. 
+		The enable works on packet boundary meaning that only on the assertion on the bit during every 0->1 transition of rx_dv.
+		Reset value is 0x0. 
+	*/	
+	uint32_t	rx_ena:1;
+	/*00: 10Mbps, 01: 100Mbps, 10: 1000Mbps, 11: 2500Mbps Reset value is 0x2. */
+	uint32_t	eth_speed:2;
+	/* All frames are received without Unicast address filtering. 
+	   0: Reset value is 0x1. */
+	uint32_t 	promis_en:1;
+	/*  Padding is removed along with crc field before the frame is sent to the user application. 
+		0: No padding is removed by the MAC.
+		Reset value is 0x0.
+	*/
+	uint32_t	pad_en:1; 
+	/*	The CRC field of received frames is transmitted to the user application. 
+		0: The CRC field is stripped from the frame.Reset value is 0x1. 
+	*/
+	uint32_t	crc_fwd:1;
+	/* 	PAUSE frames are forwarded to the user application. 
+		0: The PAUSE frames are terminated and discarded in the MAC.Reset value is 0x1. 
+	*/
+	uint32_t	pause_fwd:1;
+	/*	Receive PAUSE frames are ignored by the MAC. 
+		0: The tramsmit process is stiooed for the amount of time specified in the pause wuanta received within the PAUSE frame.
+		Reset value is 0x0. 
+	*/
+	uint32_t	rx_pause_ignore:1;
+	/*	The MAC overwrites the source MAC address with a programmed MAC address in register MAC_0 and MAC_1." 
+		0: Not modify the source address received from the transmit application client.
+		Reset value is 0x0.
+	*/
+	uint32_t	tx_addr_ins:1;
+	/* Ignored when RTH_SPEED[1]==1, gigabit mode. 1: half duplex 0: full duplex Reset value is 0x0.*/
+	uint32_t	hd_ena:1;
+	/* Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved0:2;
+	/*RX and RX engines are put in reset. 0: come out of SW reset.Reset value is 0x0. */
+	uint32_t	sw_reset:1; 
+	/*Reserved bit must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved1:1;
+	/*Enable GMII/MII loopback 1: Loopback enabled. 0: Normal operation.Reset value is 0x0. */
+	uint32_t 	lcl_loop_ena:1;
+#if defined(CONFIG_BCM947622) || defined(CONFIG_BCM63146) || defined(CONFIG_BCM4912)
+    uint32_t    mac_loop_con:1;
+    uint32_t    sw_override_tx:1;
+    uint32_t    sw_override_rx:1;
+    uint32_t    reserved2:2;
+    uint32_t    en_internal_tx_crs:1;
+#else
+	/*Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved2:6;
+#endif
+	/*Enable/Disable auto-configuration. 1: Enable  0: Disable Reset value is 0x0. */
+	uint32_t	ena_ext_config:1;
+	/*	MAC control frame enable. 1: MAC control frames with opcode other than 0x0001 are accepted and forwarded to the client interface.
+		0: MAC control frames with opcode other than 0x0000 and 0x0001 are silently discarded.
+		Reset value is 0x0.
+	*/
+	uint32_t	cntl_frm_ena:1; 
+	/*Payload length check. 0: Check payload length with Length/Type field. 1: Check disabled.Reset value is 0x1. */
+	uint32_t	no_lgth_check:1;
+	/*Enable remote loopback at the fifo system side. 0: Normal operation.Reset value is 0x0. */
+	uint32_t	rmt_loop_ena:1;
+	/*This bit currently not used.Reset value is 0x0.*/
+	uint32_t	rx_err_disc:1;  
+	/*Enable extract/insert of EFM headers.Reset value is 0x0. */
+	uint32_t	prbl_ena:1;
+	/*Ignore TX PAUSE frame transmit request.Reset value is 0x0. */
+	uint32_t	tx_pause_ignore:1;
+	/*	This mode only works in auto-config mode: 
+		0: After auto-config, TX_ENA and RX_ENA bits are set to 1. 1: After auto-config, TX_ENA and RX_ENA bits are set to 0,    
+		meaning SW will have to come in and enable TX and RX.Reset value is 0x0. */
+	uint32_t	txrx_en_config:1;
+	/*Disable RX side RUNT filtering. 0: Enable  RUNT filtering.Reset value is 0x0. */
+	uint32_t	runt_filter_dis:1;
+	/*Reserved bit must be written with 0.  A read returns an unknown value.*/
+	uint32_t	reserved3:1;
+
+}S_UNIMAC_CMD_REG;
+
+typedef struct
+{
+
+	/* 00: 10Mbps, 01: 100Mbps, 10: 1Gbps, 11: 2.5Gbps Reset value is 0x2. 	*/
+	uint32_t	mac_speed:2;
+	/*1: Half duplex. 0: Full duplex. Reset value is 0x0. */
+	uint32_t	mac_duplex:1;
+	/*1: MAC Rx pause enabled. 0: MAC Rx pause disabled.Reset value is 0x1. */
+	uint32_t	mac_rx_pause:1; 
+	/* 1: MAC Tx pause enabled. 0: MAC Tx pause disabled.Reset value is 0x1. */
+	uint32_t	mac_tx_pause:1;
+	/*Link status indication.Reset value is 0x0. */
+	uint32_t	mac_link_stat:1; 
+	/* Reserved bits must be written with 0.  A read returns an unknown value. */
+	uint32_t	reserved:26;
+
+}S_UNIMAC_STAT_REG;
+
+#if defined(CONFIG_BCM947622)
+typedef struct
+{
+    uint32_t    max_pkt_size:14;
+    uint32_t    reserved1:18;
+
+}S_UNIMAC_TOPCTRL_MAX_PKT_SZ_REG;
+
+#else   //!47622
+typedef struct
+{
+	uint32_t	gmii_direct:1;
+	uint32_t	gport_mode:1;
+	uint32_t	ss_mode_mii:1; 
+	uint32_t	txcrcerr:1;
+	uint32_t	mac_crc_fwd:1; 
+	uint32_t	mac_crc_owrt:1; 
+	uint32_t	ext_tx_flow:1; 
+	uint32_t	launch_en:1; 
+	uint32_t	pp_pse_en:8; 
+	uint32_t	pp_gen:1; 
+	uint32_t	reserved:15;
+
+}S_UNIMAC_CFG_REG;
+
+typedef struct
+{
+    uint32_t    max_pkt_size:14;
+    uint32_t    reserved1:2;
+    uint32_t    rxfifo_congestion_threshold:9;
+    uint32_t    reserved:7;
+
+}S_UNIMAC_TOP_CFG1_REG;
+
+typedef struct
+{
+    /* RX FIFO Threshold - This is the fifo located between the UNIMAC IP and BBH.
+       Once the threshold is reached pause is sent. This configuration is in
+       16-byte resolution the number of bytes in a FIFO line */
+    uint32_t    rxfifo_pause_threshod:9;
+    uint32_t    reserved1:7;
+    /* Backpressure enable for internal unimac */
+    uint32_t    backpressure_enable_int:1;
+    /* Backpressure enable for external switch */
+    uint32_t    backpressure_enable_ext:1;
+    /* Enable the mechanism for always receiving data from UNIMAC IP and
+       dropping overrun words in the unimac glue FIFO. */
+    uint32_t    fifo_overrun_ctl_en:1;
+    /* When setting this bit RX recovered clock will also input the
+       clk25 pll ref clk in the UNIMAC.*/
+    uint32_t    remote_loopback_en:1;
+    uint32_t    reserved2:12;
+
+}S_UNIMAC_TOP_CFG2_REG;
+#endif //!47622
+
+typedef struct
+{
+	uint32_t	en_lpi_rx_pause:1;
+	uint32_t	en_lpi_tx_pfc:1;
+	uint32_t	en_lpi_tx_pause:1; 
+	uint32_t	eee_en:1;
+	uint32_t	rx_fifo_check:1; 
+	uint32_t	eee_txclk_dis:1; 
+	uint32_t	dis_eee_10m:1; 
+	uint32_t	lp_idle_prediction_mode:1; 
+	uint32_t	reserved:24;
+}S_UNIMAC_EEE_CTRL_REG;
+
+#endif
+
+#endif
+
diff --git a/drivers/net/bcmbca/phy/unimac_drv_impl1.c b/drivers/net/bcmbca/phy/unimac_drv_impl1.c
new file mode 100644
index 0000000000..9666b12184
--- /dev/null
+++ b/drivers/net/bcmbca/phy/unimac_drv_impl1.c
@@ -0,0 +1,1782 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2013 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+
+#include "dt_access.h"
+
+uintptr_t unimac_conf_base;
+uintptr_t unimac_mib_base;
+uintptr_t unimac_top_base;
+uint32_t conf_offset;
+uint32_t mib_offset;
+uint32_t top_offset;
+uint32_t mib_step;
+
+static int unimac_probe(dt_device_t *pdev)
+{
+    int ret;
+    dt_handle_t node = dt_dev_get_handle(pdev);
+
+    unimac_conf_base = dt_dev_remap_resource(pdev, 0);
+    if (IS_ERR(unimac_conf_base))
+    {
+        ret = PTR_ERR(unimac_conf_base);
+        unimac_conf_base = NULL;
+        dev_err(&pdev->dev, "Missing unimac_conf_base entry\n");
+        goto Exit;
+    }
+
+    unimac_mib_base = dt_dev_remap_resource(pdev, 1);
+    if (IS_ERR(unimac_mib_base))
+    {
+        ret = PTR_ERR(unimac_mib_base);
+        unimac_mib_base = NULL;
+        dev_err(&pdev->dev, "Missing unimac_mib_base entry\n");
+        goto Exit;
+    }
+
+    unimac_top_base = dt_dev_remap_resource(pdev, 2);
+    if (IS_ERR(unimac_top_base))
+    {
+        ret = PTR_ERR(unimac_top_base);
+        unimac_top_base = NULL;
+        dev_err(&pdev->dev, "Missing unimac_top_base entry\n");
+        goto Exit;
+    }
+
+    conf_offset = dt_property_read_u32(node, "conf_offset");
+    if (conf_offset == (uint32_t)(-1))
+    {
+        ret = -1;
+        dev_err(&pdev->dev, "Missing conf_offset entry\n");
+        goto Exit;
+    }
+
+    mib_offset = dt_property_read_u32(node, "mib_offset");
+    if (mib_offset == (uint32_t)(-1))
+    {
+        ret = -1;
+        dev_err(&pdev->dev, "Missing mib_offset entry\n");
+        goto Exit;
+    }
+
+    top_offset = dt_property_read_u32(node, "top_offset");
+    if (top_offset == (uint32_t)(-1))
+    {
+        ret = -1;
+        dev_err(&pdev->dev, "Missing top_offset entry\n");
+        goto Exit;
+    }
+
+    mib_step = dt_property_read_u32(node, "mib_step");
+    if (mib_step == (uint32_t)(-1))
+    {
+        ret = -1;
+        dev_err(&pdev->dev, "Missing mib_step entry\n");
+        goto Exit;
+    }
+
+    dev_dbg(&pdev->dev, "unimac_conf_base=0x%lx\n", unimac_conf_base);
+    dev_dbg(&pdev->dev, "unimac_mib_base=0x%lx\n", unimac_mib_base);
+    dev_dbg(&pdev->dev, "unimac_top_base=0x%lx\n", unimac_top_base);
+    dev_dbg(&pdev->dev, "conf_offset=0x%x\n", conf_offset);
+    dev_dbg(&pdev->dev, "mib_offset=0x%x\n", mib_offset);
+    dev_dbg(&pdev->dev, "top_offset=0x%x\n", top_offset);
+    dev_dbg(&pdev->dev, "mib_step=0x%x\n", mib_step);
+
+    dev_info(&pdev->dev, "registered\n");
+
+    return 0;
+
+Exit:
+    return ret;
+}
+
+#ifdef __UBOOT__
+static const struct udevice_id unimac_ids[] = {
+    { .compatible = "brcm,unimac" },
+    { /* end of list */ },
+};
+
+U_BOOT_DRIVER(brcm_unimac) = {
+    .name	= "brcm-unimac",
+    .id	= UCLASS_MISC,
+    .of_match = unimac_ids,
+    .probe = unimac_probe,
+};
+#else
+static const struct of_device_id of_platform_table[] = {
+    { .compatible = "brcm,unimac" },
+    { /* end of list */ },
+};
+
+static struct platform_driver of_platform_driver = {
+    .driver = {
+        .name = "brcm-unimac",
+        .of_match_table = of_platform_table,
+    },
+    .probe = unimac_probe,
+};
+module_platform_driver(of_platform_driver);
+#endif
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the implementation of the HwApiMac for unimac           */
+/*                                                                            */
+/******************************************************************************/
+
+
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+#if !(defined(CONFIG_BCM963158) || defined(CONFIG_BCM96846) || defined(CONFIG_BCM96856) || defined(CONFIG_BCM947622) || defined(CONFIG_BCM96878) || defined(CONFIG_BCM963146) || defined(CONFIG_BCM94912))
+#ifdef __UBOOT__
+static void get_rdp_freq(unsigned int *rdp_freq) {}
+#else
+#include "clk_rst.h"
+#endif
+#endif
+
+#if defined(CONFIG_BCM963138) || defined(CONFIG_BCM963148)
+#include "rdp_drv_bbh.h"
+#endif
+
+#include "unimac_drv.h"
+
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+#define UNIMAC_SWRESET_ON  			1
+#define UNIMAC_SWRESET_OFF 			0
+#define UNIMAC_DEFAULT_IPG 			12
+#define UNIMAC_DEFAULT_PAUSE_QUANTA 0xffff
+#define UNIMAC_DEFAULT_PAUSE_TIMER 	0x1ffff
+#define UNIMAC_MAX_FRAME_LENGHT		0xffff
+
+#ifdef __UBOOT__
+#define  mac_unlikely(a) a      
+#else
+#define  mac_unlikely(a) unlikely(a)
+#endif
+
+#define UNIMAC_NUMBER_OF_SPEEDS 	( UNIMAC_SPEED_2500 + 1 )
+#define UNIMAC_NUMBER_OF_DUPLEXES	( UNIMAC_DUPLEX_FULL + 1 )
+
+static uint32_t ipgSpeedTable[UNIMAC_NUMBER_OF_SPEEDS][UNIMAC_NUMBER_OF_DUPLEXES] =
+{
+    {0x000a,0x000a},
+    {0x000a,0x000a},
+    {0x0005,0x0005},
+    {0x0005,0x0005}
+};
+
+static uint32_t enabled_emac;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_configuration                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get configuration                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   get the configuratin of a mac port	,note that current status of emac	  */
+/*   might be different than configuration when working in autoneg			  */
+/*	to get the current status use mac_hwapi_get_mac_status API				  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    emac_cfg -  structure holds the current configuration of the mac  port  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_configuration(rdpa_emac emacNum,rdpa_emac_cfg_t *emac_cfg)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    emac_cfg->allow_too_long		=	0;//no such
+    emac_cfg->back2back_gap			=	0;//no such
+    emac_cfg->check_length			=	!mCfgReg.no_lgth_check;
+    emac_cfg->full_duplex			=	!mCfgReg.hd_ena;
+    emac_cfg->generate_crc			=	0;
+    emac_cfg->loopback				=	mCfgReg.rmt_loop_ena;
+    emac_cfg->non_back2back_gap		= 	0;//no such
+    emac_cfg->pad_short				= 	0;//no such
+    emac_cfg->rate					=	mCfgReg.eth_speed;
+    emac_cfg->rx_flow_control		=	!mCfgReg.rx_pause_ignore;
+    emac_cfg->tx_flow_control		=	!mCfgReg.tx_pause_ignore;
+
+    UNIMAC_READ_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,emac_cfg->min_interframe_gap);
+    UNIMAC_READ_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,emac_cfg->preamble_length);
+}
+EXPORT_SYMBOL(mac_hwapi_get_configuration);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_configuration                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set configuration                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   set the configuratin of a mac port                                       */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   emac_cfg -  structure holds the current configuration of the mac  port   */
+/*                                                                            */
+/* Output:                                                                    */
+/*      																	  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_configuration(rdpa_emac emacNum,rdpa_emac_cfg_t *emac_cfg)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*first put the mac in reset to enable config change*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,1);
+
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+
+    /*now mac configuration can be changed */
+    if(!mCfgReg.ena_ext_config) /* Change only if auto_config is not set */
+    {
+        mCfgReg.eth_speed           = emac_cfg->rate;
+        mCfgReg.hd_ena	            = !emac_cfg->full_duplex;
+        mCfgReg.rx_pause_ignore     = !emac_cfg->rx_flow_control;
+        mCfgReg.tx_pause_ignore     = !emac_cfg->tx_flow_control;
+        /*set the interframe gap*/
+        UNIMAC_WRITE_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,ipgSpeedTable[emac_cfg->rate][(unsigned)emac_cfg->full_duplex]);
+    }
+    else
+    {
+        /*set the interframe gap*/
+        UNIMAC_WRITE_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,emac_cfg->min_interframe_gap);
+    }
+
+    mCfgReg.no_lgth_check	      =	!emac_cfg->check_length;
+    mCfgReg.pad_en                = emac_cfg->pad_short;
+    mCfgReg.rmt_loop_ena	      =	emac_cfg->loopback;
+
+
+    UNIMAC_WRITE32_REG(emacNum,CMD,mCfgReg);
+
+
+    /* set the preamble length */
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,emac_cfg->preamble_length);
+
+    /* when link up at 10M, hold unimac reset longer per ASIC team */
+    if (emac_cfg->rate == rdpa_emac_rate_10m)
+        udelay(1000);
+
+    /*release the sw_reset bit*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,0);
+}
+EXPORT_SYMBOL(mac_hwapi_set_configuration);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_duplex		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port duplex                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the dulplex of a port												  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    full_duples  :  1 = full dulplex,0 = half_duplex						  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_duplex(rdpa_emac emacNum,int32_t *full_duplex)
+{
+    /*read field and reverse polarity*/
+    int32_t fieldData;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,hd_ena,fieldData);
+    *full_duplex = !fieldData;
+}
+EXPORT_SYMBOL(mac_hwapi_get_duplex);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_duplex		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port duplex                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the dulplex of a port												  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    full_duples  :  1 = full dulplex,0 = half_duplex						  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_duplex(rdpa_emac emacNum,int32_t full_duplex)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    if (!mCfgReg.ena_ext_config) /* Change only if auto_config is not set */
+    {
+        /*write the dulplex field in reverse polarity,must be set in sw_reset state*/
+        S_HWAPI_MAC_STATUS  macMode;
+
+        UNIMAC_READ32_REG(emacNum,MODE,macMode);
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,hd_ena,full_duplex ?  0 : 1);
+
+        /*when setting the duplex we have to set new IPG value*/
+        //UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN ,tx_ipg_len,ipgSpeedTable[macMode.mac_speed][macMode.mac_duplex]);
+
+        /*take the mac out of sw_reset*/
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+    }
+}
+EXPORT_SYMBOL(mac_hwapi_set_duplex);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_speed		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port speed rate                                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the speed of a port													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                              							                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*      rate -   enum of the speed                                            */
+/******************************************************************************/
+void mac_hwapi_get_speed(rdpa_emac emacNum,rdpa_emac_rate *rate)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*read the speed field*/
+    UNIMAC_READ_FIELD(emacNum,CMD,eth_speed,*rate);
+}
+EXPORT_SYMBOL(mac_hwapi_get_speed);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_speed		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port speed rate                                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the speed of a port													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*      rate -   enum of the speed   						                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                   							              */
+/******************************************************************************/
+
+void mac_hwapi_set_speed(rdpa_emac emacNum,rdpa_emac_rate rate)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    if (!mCfgReg.ena_ext_config) /* Change only if auto_config is not set */
+    {
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,eth_speed,rate);
+
+
+        UNIMAC_WRITE_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,ipgSpeedTable[rate][0]);
+
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+    }
+}
+EXPORT_SYMBOL(mac_hwapi_set_speed);
+
+void mac_hwapi_set_external_conf(rdpa_emac emacNum, int enable)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    mCfgReg.ena_ext_config = enable;
+    UNIMAC_WRITE32_REG(emacNum,CMD,mCfgReg);
+}
+EXPORT_SYMBOL(mac_hwapi_set_external_conf);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rxtx_enable                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx and rx enable                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get tx and rx enable													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                             								  */
+/*                                                                            */
+/* Output:                                                                    */
+/*       rxtxEnable  - boolean enable   	                                  */
+/******************************************************************************/
+void mac_hwapi_get_rxtx_enable(rdpa_emac emacNum,int32_t *rxEnable,int32_t *txEnable)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,tx_ena,*txEnable);
+    UNIMAC_READ_FIELD(emacNum,CMD,rx_ena,*rxEnable);
+}
+EXPORT_SYMBOL(mac_hwapi_get_rxtx_enable);
+
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_rxtx_enable                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx and rx enable                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set tx and rx enable													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    rxtxEnable  - boolean enable                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_rxtx_enable(rdpa_emac emacNum,int32_t rxEnable,int32_t txEnable)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,tx_ena,txEnable);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,rx_ena,rxEnable);
+}
+EXPORT_SYMBOL(mac_hwapi_set_rxtx_enable);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_sw_reset		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port software reset                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the sw reset bit of emac port										  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    swReset  :  1 = reset,0 = not reset									  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_sw_reset(rdpa_emac emacNum,int32_t *swReset)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,sw_reset,*swReset);
+}
+EXPORT_SYMBOL(mac_hwapi_get_sw_reset);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_sw_reset		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port software reset                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the sw reset bit of emac port										  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   swReset  :  1 = reset,0 = not reset	                                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*    								  										  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_sw_reset(rdpa_emac emacNum,int32_t swReset)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,swReset);
+}
+EXPORT_SYMBOL(mac_hwapi_set_sw_reset);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_min_pkt_size                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get tx minimum packet size                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*  Get the unimac configuration for minimum tx packet size                   */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    min_pkt_size  :  14...125                                               */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_min_pkt_size(rdpa_emac emacNum,int32_t *min_pkt_size)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,TX_IPG_LEN,tx_min_pkt_size,*min_pkt_size);
+}
+EXPORT_SYMBOL(mac_hwapi_get_tx_min_pkt_size);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_min_pkt_size                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx minimum packet size                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*  Set the unimac configuration for minimum tx packet size                   */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*   min_pkt_size  :  14...125                                                */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_min_pkt_size(rdpa_emac emacNum,int32_t min_pkt_size)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+#if defined(CONFIG_BCM94908) || defined(CONFIG_BCM963158) || defined(CONFIG_BCM947622)
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_min_pkt_size,min_pkt_size);
+#endif
+}
+EXPORT_SYMBOL(mac_hwapi_set_tx_min_pkt_size);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_max_frame_len                                           */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port TX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the port maximum transmit unit size in bytes						  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                              										      */
+/*                                                                            */
+/* Output:                                                                    */
+/*    maxTxFrameLen - size of frame in bytes 								  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_get_tx_max_frame_len(rdpa_emac emacNum,uint32_t *maxTxFrameLen )
+{
+    S_UNIMAC_TOPCTRL_MAX_PKT_SZ_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOPCTRL_MIB_MAX_PKT_SIZE + UNIMAC_TOPCTRL_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(address,cfgreg);
+
+    *maxTxFrameLen = cfgreg.max_pkt_size;
+}
+#else //!47622
+void mac_hwapi_get_tx_max_frame_len(rdpa_emac emacNum,uint32_t *maxTxFrameLen )
+{
+    S_UNIMAC_TOP_CFG1_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(address,cfgreg);
+
+    *maxTxFrameLen = cfgreg.max_pkt_size;
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_get_tx_max_frame_len);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port TX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the port maximum transmit unit size in bytes						  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    maxTxFrameLen - size of frame in bytes                         	      */
+/*                                                                            */
+/* Output:                                                                    */
+/*   																		  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_set_tx_max_frame_len(rdpa_emac emacNum,uint32_t maxTxFrameLen )
+{
+
+    S_UNIMAC_TOPCTRL_MAX_PKT_SZ_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOPCTRL_MIB_MAX_PKT_SIZE + UNIMAC_TOPCTRL_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxTxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,FRM_LEN,frame_length,UNIMAC_MAX_FRAME_LENGHT);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#else //!47622
+void mac_hwapi_set_tx_max_frame_len(rdpa_emac emacNum,uint32_t maxTxFrameLen )
+{
+
+    S_UNIMAC_TOP_CFG1_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxTxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,FRM_LEN,frame_length,UNIMAC_MAX_FRAME_LENGHT);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_set_tx_max_frame_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port RX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the port maximum receive unit size in bytes							  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                           	     										  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   maxRxFrameLen - size of current MRU									  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_get_rx_max_frame_len(rdpa_emac emacNum,uint32_t *maxRxFrameLen )
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,FRM_LEN,frame_length,*maxRxFrameLen );
+}
+#else //!47622
+void mac_hwapi_get_rx_max_frame_len(rdpa_emac emacNum,uint32_t *maxRxFrameLen )
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,RX_MAX_PKT_SIZE,max_pkt_size,*maxRxFrameLen );
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_get_rx_max_frame_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_rx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port RX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the port maximum receive unit size in bytes							  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    maxRxFrameLen - size of current MRU        							  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   									  									  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_set_rx_max_frame_len(rdpa_emac emacNum,uint32_t maxRxFrameLen )
+{
+    S_UNIMAC_TOPCTRL_MAX_PKT_SZ_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOPCTRL_MIB_MAX_PKT_SIZE + UNIMAC_TOPCTRL_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxRxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,FRM_LEN,frame_length,maxRxFrameLen);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#else //!47622
+void mac_hwapi_set_rx_max_frame_len(rdpa_emac emacNum,uint32_t maxRxFrameLen )
+{
+    S_UNIMAC_TOP_CFG1_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxRxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,RX_MAX_PKT_SIZE,max_pkt_size,maxRxFrameLen);
+
+    /*put emac out sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_set_rx_max_frame_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_igp_len	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port inter frame gap                                 	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the inter frame gap	size in bytes									  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   txIpgLen - length in bytes                                               */
+/*                                                                            */
+/* Output:                                                                    */
+/*    																		  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_igp_len(rdpa_emac emacNum,uint32_t txIpgLen )
+{
+    /*we assume that txIpgLen called with bits time resolution*/
+    uint32_t	newIpg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    txIpgLen += 7;
+    newIpg = txIpgLen / 8;
+
+    if (newIpg < 8)
+    {
+        newIpg = 8;
+    } else if (newIpg > 27)
+    {
+        newIpg = 27;
+    }
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,newIpg );
+
+    /*put emac out sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+
+}
+EXPORT_SYMBOL(mac_hwapi_set_tx_igp_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_igp_len	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port inter frame gap                                 	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the inter frame gap	size in bytes									  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                      							          */
+/*                                                                            */
+/* Output:                                                                    */
+/*    txIpgLen - length in bytes    										  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_igp_len(rdpa_emac emacNum,uint32_t *txIpgLen )
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,*txIpgLen );
+
+}
+EXPORT_SYMBOL(mac_hwapi_get_tx_igp_len);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_mac_status	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port status                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the status of mac													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    macStatus  :  														  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_mac_status(rdpa_emac emacNum,S_HWAPI_MAC_STATUS *macStatus)
+{
+
+}
+EXPORT_SYMBOL(mac_hwapi_get_mac_status);
+
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_flow_control                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*           																  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   flowControl - structure with parameters of tx and rx flow control		  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_get_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    uint32_t	rxFlow, txFlow;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,rx_pause_ignore,rxFlow);
+    UNIMAC_READ_FIELD(emacNum,CMD,tx_pause_ignore,txFlow);
+    flowControl->rxFlowEnable	= !rxFlow;
+    flowControl->txFlowEnable	= !txFlow;
+}
+#else //!47622
+void mac_hwapi_get_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    uint32_t	rxFlow, txFlow, value;
+    uintptr_t	misc_top_address;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    misc_top_address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+    READ_32(misc_top_address, value);
+
+
+    if(value & UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT)
+    {
+        UNIMAC_READ_FIELD(emacNum,CMD,rx_pause_ignore,rxFlow);
+        UNIMAC_READ_FIELD(emacNum,CMD,tx_pause_ignore,txFlow);
+        flowControl->rxFlowEnable	= !rxFlow;
+        flowControl->txFlowEnable	= !txFlow;
+    }
+    else
+    {
+        flowControl->rxFlowEnable = 0;
+        flowControl->txFlowEnable = 0;
+    }
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_get_flow_control);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_pause_params                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   flowControl - structure with parameters of tx and rx flow control        */
+/*                                                                            */
+/* Output:                                                                    */
+/*   						  												  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_pause_params(rdpa_emac emacNum,int32_t pauseCtrlEnable,uint32_t pauseTimer,uint32_t pauseQuanta)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_control_en,pauseCtrlEnable );
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_timer,pauseTimer );
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_QUNAT,pause_quant,pauseQuanta );
+}
+EXPORT_SYMBOL(mac_hwapi_set_pause_params);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_flow_control                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   flowControl - structure with parameters of tx and rx flow control        */
+/*                                                                            */
+/* Output:                                                                    */
+/*   						  												  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_set_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_override_rx, 1);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_override_tx, 1);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,rx_pause_ignore, !flowControl->rxFlowEnable);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,tx_pause_ignore, !flowControl->txFlowEnable);
+}
+#else //!47622
+void mac_hwapi_set_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    uintptr_t misc_top_address;
+    uint32_t value;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,rx_pause_ignore, !flowControl->rxFlowEnable);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,tx_pause_ignore, !flowControl->txFlowEnable);
+    misc_top_address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+    READ_32(misc_top_address, value);
+
+    if(flowControl->rxFlowEnable || flowControl->txFlowEnable)
+        value |= UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT;
+    else
+        value &= ~UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT;
+
+    WRITE_32(misc_top_address, value);
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_set_flow_control);
+
+
+static rdpa_emac_rx_stat_t rxCountersLast[MAX_NUM_OF_EMACS];
+#define UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, param) \
+    do{\
+        uint32_t  paramCurrent = rxCounters->param; \
+        if(mac_unlikely(rxCounters->param < rxCountersLast[emacNum].param)){    \
+            rxCounters->param += (0xFFFFFFFF-rxCountersLast[emacNum].param)+1;    \
+        }else{  \
+            rxCounters->param -= rxCountersLast[emacNum].param; \
+        }   \
+        rxCountersLast[emacNum].param   = paramCurrent; \
+    }while(0)
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rx_counters	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	get the rx counters of port                           	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the rx counters of port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    rxCounters  :  structure filled with counters							  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_rx_counters(rdpa_emac emacNum,rdpa_emac_rx_stat_t *rxCounters)
+{
+    uint32_t		tempVal;
+
+    if (!(enabled_emac & (1 << emacNum)))
+    {
+        memset(rxCounters, 0, sizeof(rdpa_emac_rx_stat_t));
+        return;
+    }
+
+    UNIMAC_READ32_MIB(emacNum,GRALN,rxCounters->alignment_error);
+    UNIMAC_READ32_MIB(emacNum,GRBCA,rxCounters->broadcast_packet);
+    UNIMAC_READ32_MIB(emacNum,GRUC, rxCounters->unicast_packet);
+    UNIMAC_READ32_MIB(emacNum,GRBYT,rxCounters->byte);
+    UNIMAC_READ32_MIB(emacNum,RRBYT,tempVal);
+    rxCounters->byte                    +=	tempVal;
+    UNIMAC_READ32_MIB(emacNum,GRFCR,rxCounters->carrier_sense_error);
+    UNIMAC_READ32_MIB(emacNum,GRCDE,rxCounters->code_error);
+    UNIMAC_READ32_MIB(emacNum,GRXCF,rxCounters->control_frame);
+    UNIMAC_READ32_MIB(emacNum,GRFCS,rxCounters->fcs_error);
+    rxCounters->fragments				=	0;//?????
+    UNIMAC_READ32_MIB(emacNum,GR255,rxCounters->frame_128_255);
+    UNIMAC_READ32_MIB(emacNum,GR2047,tempVal);
+    rxCounters->frame_1519_mtu			=	tempVal;
+    UNIMAC_READ32_MIB(emacNum,GR4095,tempVal);
+    rxCounters->frame_1519_mtu			+=	tempVal;
+    UNIMAC_READ32_MIB(emacNum,GR9216,tempVal);
+    rxCounters->frame_1519_mtu			+=	tempVal;
+
+    UNIMAC_READ32_MIB(emacNum,GR511,rxCounters->frame_256_511);
+
+    UNIMAC_READ32_MIB(emacNum,GR1023,rxCounters->frame_512_1023);
+
+    UNIMAC_READ32_MIB(emacNum,GR1518,rxCounters->frame_1024_1518);
+
+    UNIMAC_READ32_MIB(emacNum,GR64,rxCounters->frame_64);
+
+    UNIMAC_READ32_MIB(emacNum,GR127,rxCounters->frame_65_127);
+
+    UNIMAC_READ32_MIB(emacNum,GRFLR,rxCounters->frame_length_error);
+
+    UNIMAC_READ32_MIB(emacNum,GRJBR,rxCounters->jabber);
+
+    UNIMAC_READ32_MIB(emacNum,GRMCA,rxCounters->multicast_packet);
+
+    rxCounters->overflow				=	0;//no matched counter
+    UNIMAC_READ32_MIB(emacNum,GROVR,rxCounters->oversize_packet);
+	
+    UNIMAC_READ32_MIB(emacNum,RRPKT,rxCounters->undersize_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GRPKT,rxCounters->packet);
+    
+    UNIMAC_READ32_MIB(emacNum,GRXPF,rxCounters->pause_control_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GRXUO,rxCounters->unknown_opcode);
+
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, alignment_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, broadcast_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, unicast_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, byte);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, carrier_sense_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, code_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, control_frame);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, fcs_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_64);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_65_127);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_128_255);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_256_511);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_512_1023);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_1024_1518);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_1519_mtu);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_length_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, jabber);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, multicast_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, oversize_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, undersize_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, pause_control_frame);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, unknown_opcode);
+}
+EXPORT_SYMBOL(mac_hwapi_get_rx_counters);
+
+
+static rdpa_emac_tx_stat_t txCountersLast[MAX_NUM_OF_EMACS];
+#define UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, param) \
+    do{\
+        uint32_t  paramCurrent = txCounters->param; \
+        if(mac_unlikely(txCounters->param < txCountersLast[emacNum].param)){    \
+            txCounters->param += (0xFFFFFFFF-txCountersLast[emacNum].param)+1;    \
+        }else{  \
+            txCounters->param -= txCountersLast[emacNum].param; \
+        }   \
+        txCountersLast[emacNum].param   = paramCurrent; \
+    }while(0)
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_counters	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	get the tx counters of port                           	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the tx counters of port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    txCounters  :  structure filled with counters							  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_counters(rdpa_emac emacNum,rdpa_emac_tx_stat_t *txCounters)
+{
+    /*fill the rdpa counters structure*/
+    uint32_t		tempVal;
+
+    if (!(enabled_emac & (1 << emacNum)))
+    {
+        memset(txCounters, 0, sizeof(rdpa_emac_tx_stat_t));
+        return;
+    }
+
+    UNIMAC_READ32_MIB(emacNum,GTBYT,txCounters->byte);
+
+    UNIMAC_READ32_MIB(emacNum,GTBCA,txCounters->broadcast_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTMCA, txCounters->multicast_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTUC, txCounters->unicast_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTXCF,txCounters->control_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTDRF,txCounters->deferral_packet);
+
+
+    UNIMAC_READ32_MIB(emacNum,GTNCL,tempVal);
+    txCounters->error						= tempVal;
+    UNIMAC_READ32_MIB(emacNum,GTOVR,tempVal);
+    txCounters->error						+= tempVal;
+    UNIMAC_READ32_MIB(emacNum,GTFCS,tempVal);
+    txCounters->error						+= tempVal;
+    UNIMAC_READ32_MIB(emacNum,GTEDF,txCounters->excessive_deferral_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTFCS,txCounters->fcs_error	);
+
+    UNIMAC_READ32_MIB(emacNum,GTFRG,txCounters->fragments_frame);
+
+    UNIMAC_READ32_MIB(emacNum,TR1518,txCounters->frame_1024_1518);
+
+    UNIMAC_READ32_MIB(emacNum,TR255,  txCounters->frame_128_255);
+
+    UNIMAC_READ32_MIB(emacNum,TR2047,  tempVal);
+    txCounters->frame_1519_mtu			=   tempVal;
+    UNIMAC_READ32_MIB(emacNum,TR4095,  tempVal);
+    txCounters->frame_1519_mtu			+=   tempVal;
+    UNIMAC_READ32_MIB(emacNum,TR9216,  tempVal);
+    txCounters->frame_1519_mtu			+=   tempVal;
+    UNIMAC_READ32_MIB(emacNum,TR511,  txCounters->frame_256_511);
+
+    UNIMAC_READ32_MIB(emacNum,TR1023, txCounters->frame_512_1023);
+
+    UNIMAC_READ32_MIB(emacNum,TR64,txCounters->frame_64);
+
+    UNIMAC_READ32_MIB(emacNum,TR127, txCounters->frame_65_127);
+
+    UNIMAC_READ32_MIB(emacNum,GTJBR, txCounters->jabber_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTLCL, txCounters->late_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTMCL, txCounters->multiple_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTOVR,txCounters->oversize_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTPOK, txCounters->packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTXPF, txCounters->pause_control_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTSCL, txCounters->single_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTNCL, txCounters->total_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTXCL, txCounters->excessive_collision);
+
+    txCounters->underrun					=	0;
+    txCounters->undersize_frame				=	0;
+
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, byte);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, broadcast_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, multicast_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, unicast_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, deferral_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, excessive_deferral_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, control_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, jabber_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, oversize_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, pause_control_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, fragments_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, error);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, fcs_error);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_64);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_65_127);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_128_255);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_256_511);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_512_1023);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_1024_1518);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_1519_mtu);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, single_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, total_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, late_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, multiple_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, excessive_collision);
+}
+EXPORT_SYMBOL(mac_hwapi_get_tx_counters);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_init_emac	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_init_emac(rdpa_emac emacNum)
+{
+    /*configure the emac and put it in automatic speed mode*/
+    S_UNIMAC_CMD_REG	mCfgReg;
+    uint32_t max_frame_length = UNIMAC_MAX_FRAME_LENGHT;
+
+    /*before calling this function make sure you pull out of reset the emac */
+
+    /*put the emac in sw_reset state*/
+    //UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    /* Do the initialization */
+    mCfgReg.tx_ena          =   0;
+    mCfgReg.rx_ena          =   0;
+    /* for 63138 - even though the EMAC_1 is connected to SF2 @ 2Gbps, we still set the link to 1G.
+     * Actual speed of the link is derived from SF2 based on the speed set for IMP port#8.  */
+    mCfgReg.eth_speed		=	UNIMAC_SPEED_1000;
+    mCfgReg.promis_en		=	1;
+    mCfgReg.pad_en			=	0;
+    mCfgReg.pause_fwd		=	1;
+    mCfgReg.crc_fwd			=	1;
+    mCfgReg.ena_ext_config	=	0;
+    mCfgReg.rx_pause_ignore	=	0;
+    mCfgReg.tx_pause_ignore	=	0;
+    mCfgReg.tx_addr_ins		=	0;
+    mCfgReg.lcl_loop_ena	=	0;
+    mCfgReg.cntl_frm_ena	=	1;
+    mCfgReg.no_lgth_check	=	1;
+    mCfgReg.rmt_loop_ena	=	0;
+    mCfgReg.rx_err_disc		=	0;
+    mCfgReg.prbl_ena		=	0;
+    mCfgReg.cntl_frm_ena	=	1;
+
+    /*write the configuration */
+    UNIMAC_WRITE32_REG(emacNum,CMD,mCfgReg);
+    UNIMAC_WRITE32_REG(emacNum,FRM_LEN, max_frame_length);
+
+    /*take out the emac from sw_reset state*/
+    //UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+#if 0
+    /*configure the pause control*/
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_timer,UNIMAC_DEFAULT_PAUSE_TIMER);
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_control_en,1);
+
+    /*configure the pause quanta*/
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_QUNAT,pause_quant,UNIMAC_DEFAULT_PAUSE_QUANTA);
+
+    /*write default ipg*/
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,UNIMAC_DEFAULT_IPG);
+#endif
+    memset(&rxCountersLast, 0, MAX_NUM_OF_EMACS*sizeof(rdpa_emac_rx_stat_t));
+    memset(&txCountersLast, 0, MAX_NUM_OF_EMACS*sizeof(rdpa_emac_tx_stat_t));
+
+    enabled_emac |= (1 << emacNum);
+
+    /*emac is ready to go!*/
+}
+EXPORT_SYMBOL(mac_hwapi_init_emac);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_loopback	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_loopback(rdpa_emac emacNum,MAC_LPBK *loopback)
+{
+    S_UNIMAC_CMD_REG	mCmdReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCmdReg);
+
+    if (mCmdReg.lcl_loop_ena && mCmdReg.rmt_loop_ena)
+    {
+        *loopback = MAC_LPBK_BOTH;
+    }
+    else if (mCmdReg.lcl_loop_ena)
+    {
+        *loopback = MAC_LPBK_LOCAL;
+    }
+    else if (mCmdReg.rmt_loop_ena)
+    {
+        *loopback = MAC_LPBK_REMOTE;
+    }
+    else
+    {
+        *loopback = MAC_LPBK_NONE;
+    }
+
+}
+EXPORT_SYMBOL(mac_hwapi_get_loopback);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_loopback	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	set loopback type of the mac	                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_loopback(rdpa_emac emacNum,MAC_LPBK loopback)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put the emac in sw_reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+    switch(loopback)
+    {
+        case MAC_LPBK_BOTH:
+            UNIMAC_WRITE_FIELD(emacNum,CMD,rmt_loop_ena,1);
+            UNIMAC_WRITE_FIELD(emacNum,CMD, lcl_loop_ena,1);
+            break;
+        case MAC_LPBK_LOCAL:
+            UNIMAC_WRITE_FIELD(emacNum,CMD, lcl_loop_ena,1);
+            break;
+        case MAC_LPBK_REMOTE:
+            UNIMAC_WRITE_FIELD(emacNum,CMD,rmt_loop_ena,1);
+            break;
+        case MAC_LPBK_NONE:
+            UNIMAC_WRITE_FIELD(emacNum,CMD,rmt_loop_ena,0);
+            UNIMAC_WRITE_FIELD(emacNum,CMD, lcl_loop_ena,0);
+            break;
+        default:
+
+            break;
+    }
+    /* take out the emac from sw_reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+
+}
+EXPORT_SYMBOL(mac_hwapi_set_loopback);
+
+void mac_hwapi_set_unimac_cfg(rdpa_emac emacNum, int32_t enabled)
+{
+#if !defined(CONFIG_BCM947622) && !defined(CONFIG_BCM963146) && !defined(CONFIG_BCM94912)
+    S_UNIMAC_CFG_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(address,cfgreg);
+    cfgreg.gmii_direct = enabled ? 1 : 0;
+    WRITE_32(address,cfgreg);
+#endif
+}
+EXPORT_SYMBOL(mac_hwapi_set_unimac_cfg);
+
+void mac_hwapi_modify_flow_control_pause_pkt_addr ( rdpa_emac emacNum,bdmf_mac_t mac)
+{
+    uint32_t value = *(uint32_t*)(&(mac.b[4])) >> 16 ;
+    uintptr_t mac_address = (uintptr_t)UNIMAC_CONFIGURATION_UMAC_0_RDP_MAC0 + UNIMAC_CONF_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    WRITE_32(mac_address, *(uint32_t*)mac.b);
+
+    mac_address = (uintptr_t)UNIMAC_CONFIGURATION_UMAC_0_RDP_MAC1 + UNIMAC_CONF_INSTANCE_OFFSET(emacNum);
+    WRITE_32(mac_address, value);
+
+}
+EXPORT_SYMBOL(mac_hwapi_modify_flow_control_pause_pkt_addr);
+
+void mac_hwapi_set_backpressure_ext(rdpa_emac emacNum,int32_t enable)
+{
+#if defined(CONFIG_BCM963138) || defined(CONFIG_BCM963148) || defined(CONFIG_BCM94908) || defined(CONFIG_BCM963158)
+    S_UNIMAC_TOP_CFG2_REG cfgreg;
+    uintptr_t misc_top_address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(misc_top_address,cfgreg);
+    cfgreg.backpressure_enable_ext = (enable ? 1 : 0);
+    WRITE_32(misc_top_address,cfgreg);
+#endif
+}
+EXPORT_SYMBOL(mac_hwapi_set_backpressure_ext);
+
+void mac_hwapi_set_eee(rdpa_emac emacNum, int32_t enable)
+{
+    uint32_t eee_ref_count = 0;
+    uint32_t eee_wake_timer = 0;
+    uint32_t eee_lpi_timer = 0;
+
+    S_UNIMAC_EEE_CTRL_REG eee_ctrl;
+    S_HWAPI_MAC_STATUS  mac_mode;
+
+    /* Determine EEE timers only when EEE is enabled */
+    if (enable)
+    {
+#if defined(CONFIG_BCM963158) || defined(CONFIG_BCM96846) || defined(CONFIG_BCM96856) || defined(CONFIG_BCM947622) || defined(CONFIG_BCM96878) || defined(CONFIG_BCM963146) || defined(CONFIG_BCM94912)
+        eee_ref_count = 0xfa; /* 250 Mhz */;
+#else
+        get_rdp_freq(&eee_ref_count);
+        eee_ref_count /= 2;
+#endif
+
+        /* Read actual mac speed */
+        UNIMAC_READ32_REG(emacNum, MODE, mac_mode);
+
+        switch (mac_mode.mac_speed) {
+        case rdpa_emac_rate_100m: /* 100Mbps */
+            {
+                eee_lpi_timer = 0x3c; /* 60 uS */
+                eee_wake_timer = 0x1e; /* 30 uS */
+                break;
+            }
+        case rdpa_emac_rate_1g: /* 1000Mbps */
+            {
+                eee_lpi_timer = 0x22; /* 34 uS */
+                eee_wake_timer = 0x11; /* 17 uS */
+                break;
+            }
+        case rdpa_emac_rate_2_5g: /* 2500Mbps */
+            {
+                eee_lpi_timer = 0x3c; /* 60 uS */
+                eee_wake_timer = 0x1e; /* 30 uS */
+                break;
+            }
+        default:
+            break;
+        }
+    }
+
+    UNIMAC_READ32_REG(emacNum, EEE_CTRL, eee_ctrl);
+    eee_ctrl.eee_en = enable ? 1 : 0;
+    UNIMAC_WRITE32_REG(emacNum, EEE_CTRL, eee_ctrl);
+    UNIMAC_WRITE32_REG(emacNum, EEE_REF_COUNT, eee_ref_count);
+
+#if defined(CONFIG_BCM96856) || defined(CONFIG_BCM947622)
+    if (mac_mode.mac_speed == rdpa_emac_rate_100m)
+    {
+        UNIMAC_WRITE32_REG(emacNum, EEE_MII_LPI_TIMER, eee_lpi_timer);
+        UNIMAC_WRITE32_REG(emacNum, EEE_MII_WAKE_TIMER, eee_wake_timer);
+    }
+    else
+    {
+        UNIMAC_WRITE32_REG(emacNum, EEE_GMII_LPI_TIMER, eee_lpi_timer);
+        UNIMAC_WRITE32_REG(emacNum, EEE_GMII_WAKE_TIMER, eee_wake_timer);
+    }
+#else
+    UNIMAC_WRITE32_REG(emacNum, EEE_LPI_TIMER, eee_lpi_timer);
+    UNIMAC_WRITE32_REG(emacNum, EEE_WAKE_TIMER, eee_wake_timer);
+#endif
+}
+EXPORT_SYMBOL(mac_hwapi_set_eee);
diff --git a/drivers/net/bcmbca/phy/unimac_drv_impl2.c b/drivers/net/bcmbca/phy/unimac_drv_impl2.c
new file mode 100644
index 0000000000..99418b874d
--- /dev/null
+++ b/drivers/net/bcmbca/phy/unimac_drv_impl2.c
@@ -0,0 +1,1782 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2013 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+
+#include "dt_access.h"
+
+/* impl2 has mib counter as in part of conf,
+ * so mib_base is conf_base + mib_offset.
+ * however, the original mib_offset is meant for the difference
+ * between each unimac's mib register area, which in this case
+ * is the same as conf_offset. */
+uintptr_t unimac_conf_base;
+uintptr_t unimac_mib_base;
+uintptr_t unimac_top_base;
+uint32_t conf_offset;
+uint32_t mib_offset;
+uint32_t top_offset;
+uint32_t mib_step;
+
+static int unimac_probe(dt_device_t *pdev)
+{
+    int ret;
+    dt_handle_t node = dt_dev_get_handle(pdev);
+
+    unimac_conf_base = dt_dev_remap_resource(pdev, 0);
+    if (IS_ERR(unimac_conf_base))
+    {
+        ret = PTR_ERR(unimac_conf_base);
+        unimac_conf_base = NULL;
+        dev_err(&pdev->dev, "Missing unimac_conf_base entry\n");
+        goto Exit;
+    }
+
+    unimac_top_base = dt_dev_remap_resource(pdev, 1);
+    if (IS_ERR(unimac_top_base))
+    {
+        ret = PTR_ERR(unimac_top_base);
+        unimac_top_base = NULL;
+        dev_err(&pdev->dev, "Missing unimac_top_base entry\n");
+        goto Exit;
+    }
+
+    conf_offset = dt_property_read_u32(node, "conf_offset");
+    if (conf_offset == (uint32_t)(-1))
+    {
+        ret = -1;
+        dev_err(&pdev->dev, "Missing conf_offset entry\n");
+        goto Exit;
+    }
+
+    mib_offset = dt_property_read_u32(node, "mib_offset");
+    if (mib_offset == (uint32_t)(-1))
+    {
+        ret = -1;
+        dev_err(&pdev->dev, "Missing mib_offset entry\n");
+        goto Exit;
+    }
+
+    unimac_mib_base = unimac_conf_base + mib_offset;
+    mib_offset = conf_offset;
+
+    top_offset = dt_property_read_u32(node, "top_offset");
+    if (top_offset == (uint32_t)(-1))
+    {
+        ret = -1;
+        dev_err(&pdev->dev, "Missing top_offset entry\n");
+        goto Exit;
+    }
+
+    mib_step = dt_property_read_u32(node, "mib_step");
+    if (mib_step == (uint32_t)(-1))
+    {
+        ret = -1;
+        dev_err(&pdev->dev, "Missing mib_step entry\n");
+        goto Exit;
+    }
+
+    dev_dbg(&pdev->dev, "unimac_conf_base=0x%lx\n", unimac_conf_base);
+    dev_dbg(&pdev->dev, "unimac_mib_base=0x%lx\n", unimac_mib_base);
+    dev_dbg(&pdev->dev, "unimac_top_base=0x%lx\n", unimac_top_base);
+    dev_dbg(&pdev->dev, "conf_offset=0x%x\n", conf_offset);
+    dev_dbg(&pdev->dev, "mib_offset=0x%x\n", mib_offset);
+    dev_dbg(&pdev->dev, "top_offset=0x%x\n", top_offset);
+    dev_dbg(&pdev->dev, "mib_step=0x%x\n", mib_step);
+
+    dev_info(&pdev->dev, "registered\n");
+
+    return 0;
+
+Exit:
+    return ret;
+}
+
+#ifdef __UBOOT__
+static const struct udevice_id unimac_ids[] = {
+    { .compatible = "brcm,unimac" },
+    { .compatible = "brcm,unimac3" },
+    { /* end of list */ },
+};
+
+U_BOOT_DRIVER(brcm_unimac) = {
+    .name	= "brcm-unimac",
+    .id	= UCLASS_MISC,
+    .of_match = unimac_ids,
+    .probe = unimac_probe,
+};
+#else
+static const struct of_device_id of_platform_table[] = {
+    { .compatible = "brcm,unimac" },
+    { /* end of list */ },
+};
+
+static struct platform_driver of_platform_driver = {
+    .driver = {
+        .name = "brcm-unimac",
+        .of_match_table = of_platform_table,
+    },
+    .probe = unimac_probe,
+};
+module_platform_driver(of_platform_driver);
+#endif
+
+/******************************************************************************/
+/*                                                                            */
+/* File Description:                                                          */
+/*                                                                            */
+/* This file contains the implementation of the HwApiMac for unimac           */
+/*                                                                            */
+/******************************************************************************/
+
+
+
+/*****************************************************************************/
+/*                                                                           */
+/* Include files                                                             */
+/*                                                                           */
+/*****************************************************************************/
+#if !(defined(CONFIG_BCM963158) || defined(CONFIG_BCM96846) || defined(CONFIG_BCM96856) || defined(CONFIG_BCM947622) || defined(CONFIG_BCM96878) || defined(CONFIG_BCM963146) || defined(CONFIG_BCM94912))
+#ifdef __UBOOT__
+static void get_rdp_freq(unsigned int *rdp_freq) {}
+#else
+#include "clk_rst.h"
+#endif
+#endif
+
+#if defined(CONFIG_BCM963138) || defined(CONFIG_BCM963148)
+#include "rdp_drv_bbh.h"
+#endif
+
+#include "unimac_drv.h"
+
+/******************************************************************************/
+/*                                                                            */
+/* Types and values definitions                                               */
+/*                                                                            */
+/******************************************************************************/
+#define UNIMAC_SWRESET_ON  			1
+#define UNIMAC_SWRESET_OFF 			0
+#define UNIMAC_DEFAULT_IPG 			12
+#define UNIMAC_DEFAULT_PAUSE_QUANTA 0xffff
+#define UNIMAC_DEFAULT_PAUSE_TIMER 	0x1ffff
+#define UNIMAC_MAX_FRAME_LENGHT		0xffff
+
+#ifdef __UBOOT__
+#define  mac_unlikely(a) a      
+#else
+#define  mac_unlikely(a) unlikely(a)
+#endif
+
+#define UNIMAC_NUMBER_OF_SPEEDS 	( UNIMAC_SPEED_2500 + 1 )
+#define UNIMAC_NUMBER_OF_DUPLEXES	( UNIMAC_DUPLEX_FULL + 1 )
+
+static uint32_t ipgSpeedTable[UNIMAC_NUMBER_OF_SPEEDS][UNIMAC_NUMBER_OF_DUPLEXES] =
+{
+    {0x000a,0x000a},
+    {0x000a,0x000a},
+    {0x0005,0x0005},
+    {0x0005,0x0005}
+};
+
+static uint32_t enabled_emac;
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_configuration                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get configuration                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   get the configuratin of a mac port	,note that current status of emac	  */
+/*   might be different than configuration when working in autoneg			  */
+/*	to get the current status use mac_hwapi_get_mac_status API				  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    emac_cfg -  structure holds the current configuration of the mac  port  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_configuration(rdpa_emac emacNum,rdpa_emac_cfg_t *emac_cfg)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    emac_cfg->allow_too_long		=	0;//no such
+    emac_cfg->back2back_gap			=	0;//no such
+    emac_cfg->check_length			=	!mCfgReg.no_lgth_check;
+    emac_cfg->full_duplex			=	!mCfgReg.hd_ena;
+    emac_cfg->generate_crc			=	0;
+    emac_cfg->loopback				=	mCfgReg.rmt_loop_ena;
+    emac_cfg->non_back2back_gap		= 	0;//no such
+    emac_cfg->pad_short				= 	0;//no such
+    emac_cfg->rate					=	mCfgReg.eth_speed;
+    emac_cfg->rx_flow_control		=	!mCfgReg.rx_pause_ignore;
+    emac_cfg->tx_flow_control		=	!mCfgReg.tx_pause_ignore;
+
+    UNIMAC_READ_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,emac_cfg->min_interframe_gap);
+    UNIMAC_READ_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,emac_cfg->preamble_length);
+}
+EXPORT_SYMBOL(mac_hwapi_get_configuration);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_configuration                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set configuration                                           */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*   set the configuratin of a mac port                                       */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   emac_cfg -  structure holds the current configuration of the mac  port   */
+/*                                                                            */
+/* Output:                                                                    */
+/*      																	  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_configuration(rdpa_emac emacNum,rdpa_emac_cfg_t *emac_cfg)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*first put the mac in reset to enable config change*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,1);
+
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+
+    /*now mac configuration can be changed */
+    if(!mCfgReg.ena_ext_config) /* Change only if auto_config is not set */
+    {
+        mCfgReg.eth_speed           = emac_cfg->rate;
+        mCfgReg.hd_ena	            = !emac_cfg->full_duplex;
+        mCfgReg.rx_pause_ignore     = !emac_cfg->rx_flow_control;
+        mCfgReg.tx_pause_ignore     = !emac_cfg->tx_flow_control;
+        /*set the interframe gap*/
+        UNIMAC_WRITE_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,ipgSpeedTable[emac_cfg->rate][(unsigned)emac_cfg->full_duplex]);
+    }
+    else
+    {
+        /*set the interframe gap*/
+        UNIMAC_WRITE_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,emac_cfg->min_interframe_gap);
+    }
+
+    mCfgReg.no_lgth_check	      =	!emac_cfg->check_length;
+    mCfgReg.pad_en                = emac_cfg->pad_short;
+    mCfgReg.rmt_loop_ena	      =	emac_cfg->loopback;
+
+
+    UNIMAC_WRITE32_REG(emacNum,CMD,mCfgReg);
+
+
+    /* set the preamble length */
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,emac_cfg->preamble_length);
+
+    /* when link up at 10M, hold unimac reset longer per ASIC team */
+    if (emac_cfg->rate == rdpa_emac_rate_10m)
+        udelay(1000);
+
+    /*release the sw_reset bit*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,0);
+}
+EXPORT_SYMBOL(mac_hwapi_set_configuration);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_duplex		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port duplex                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the dulplex of a port												  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    full_duples  :  1 = full dulplex,0 = half_duplex						  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_duplex(rdpa_emac emacNum,int32_t *full_duplex)
+{
+    /*read field and reverse polarity*/
+    int32_t fieldData;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,hd_ena,fieldData);
+    *full_duplex = !fieldData;
+}
+EXPORT_SYMBOL(mac_hwapi_get_duplex);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_duplex		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port duplex                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the dulplex of a port												  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    full_duples  :  1 = full dulplex,0 = half_duplex						  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_duplex(rdpa_emac emacNum,int32_t full_duplex)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    if (!mCfgReg.ena_ext_config) /* Change only if auto_config is not set */
+    {
+        /*write the dulplex field in reverse polarity,must be set in sw_reset state*/
+        S_HWAPI_MAC_STATUS  macMode;
+
+        UNIMAC_READ32_REG(emacNum,MODE,macMode);
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,hd_ena,full_duplex ?  0 : 1);
+
+        /*when setting the duplex we have to set new IPG value*/
+        //UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN ,tx_ipg_len,ipgSpeedTable[macMode.mac_speed][macMode.mac_duplex]);
+
+        /*take the mac out of sw_reset*/
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+    }
+}
+EXPORT_SYMBOL(mac_hwapi_set_duplex);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_speed		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port speed rate                                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the speed of a port													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                              							                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*      rate -   enum of the speed                                            */
+/******************************************************************************/
+void mac_hwapi_get_speed(rdpa_emac emacNum,rdpa_emac_rate *rate)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*read the speed field*/
+    UNIMAC_READ_FIELD(emacNum,CMD,eth_speed,*rate);
+}
+EXPORT_SYMBOL(mac_hwapi_get_speed);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_speed		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port speed rate                                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the speed of a port													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*      rate -   enum of the speed   						                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                   							              */
+/******************************************************************************/
+
+void mac_hwapi_set_speed(rdpa_emac emacNum,rdpa_emac_rate rate)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    if (!mCfgReg.ena_ext_config) /* Change only if auto_config is not set */
+    {
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,eth_speed,rate);
+
+
+        UNIMAC_WRITE_FIELD(emacNum,HD_BKP_CNTL,ipg_config_rx,ipgSpeedTable[rate][0]);
+
+
+        UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+    }
+}
+EXPORT_SYMBOL(mac_hwapi_set_speed);
+
+void mac_hwapi_set_external_conf(rdpa_emac emacNum, int enable)
+{
+    S_UNIMAC_CMD_REG  mCfgReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    mCfgReg.ena_ext_config = enable;
+    UNIMAC_WRITE32_REG(emacNum,CMD,mCfgReg);
+}
+EXPORT_SYMBOL(mac_hwapi_set_external_conf);
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rxtx_enable                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx and rx enable                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get tx and rx enable													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                             								  */
+/*                                                                            */
+/* Output:                                                                    */
+/*       rxtxEnable  - boolean enable   	                                  */
+/******************************************************************************/
+void mac_hwapi_get_rxtx_enable(rdpa_emac emacNum,int32_t *rxEnable,int32_t *txEnable)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,tx_ena,*txEnable);
+    UNIMAC_READ_FIELD(emacNum,CMD,rx_ena,*rxEnable);
+}
+EXPORT_SYMBOL(mac_hwapi_get_rxtx_enable);
+
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_rxtx_enable                                                */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx and rx enable                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set tx and rx enable													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    rxtxEnable  - boolean enable                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_rxtx_enable(rdpa_emac emacNum,int32_t rxEnable,int32_t txEnable)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,tx_ena,txEnable);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,rx_ena,rxEnable);
+}
+EXPORT_SYMBOL(mac_hwapi_set_rxtx_enable);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_sw_reset		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port software reset                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the sw reset bit of emac port										  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    swReset  :  1 = reset,0 = not reset									  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_sw_reset(rdpa_emac emacNum,int32_t *swReset)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,sw_reset,*swReset);
+}
+EXPORT_SYMBOL(mac_hwapi_get_sw_reset);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_sw_reset		                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port software reset                                  	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the sw reset bit of emac port										  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   swReset  :  1 = reset,0 = not reset	                                  */
+/*                                                                            */
+/* Output:                                                                    */
+/*    								  										  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_sw_reset(rdpa_emac emacNum,int32_t swReset)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,swReset);
+}
+EXPORT_SYMBOL(mac_hwapi_set_sw_reset);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_min_pkt_size                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get tx minimum packet size                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*  Get the unimac configuration for minimum tx packet size                   */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    min_pkt_size  :  14...125                                               */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_min_pkt_size(rdpa_emac emacNum,int32_t *min_pkt_size)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,TX_IPG_LEN,tx_min_pkt_size,*min_pkt_size);
+}
+EXPORT_SYMBOL(mac_hwapi_get_tx_min_pkt_size);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_min_pkt_size                                            */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set tx minimum packet size                                  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/*  Set the unimac configuration for minimum tx packet size                   */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index                                                */
+/*   min_pkt_size  :  14...125                                                */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_min_pkt_size(rdpa_emac emacNum,int32_t min_pkt_size)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+#if defined(CONFIG_BCM94908) || defined(CONFIG_BCM963158) || defined(CONFIG_BCM947622)
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_min_pkt_size,min_pkt_size);
+#endif
+}
+EXPORT_SYMBOL(mac_hwapi_set_tx_min_pkt_size);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_max_frame_len                                           */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port TX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the port maximum transmit unit size in bytes						  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                              										      */
+/*                                                                            */
+/* Output:                                                                    */
+/*    maxTxFrameLen - size of frame in bytes 								  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_get_tx_max_frame_len(rdpa_emac emacNum,uint32_t *maxTxFrameLen )
+{
+    S_UNIMAC_TOPCTRL_MAX_PKT_SZ_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOPCTRL_MIB_MAX_PKT_SIZE + UNIMAC_TOPCTRL_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(address,cfgreg);
+
+    *maxTxFrameLen = cfgreg.max_pkt_size;
+}
+#else //!47622
+void mac_hwapi_get_tx_max_frame_len(rdpa_emac emacNum,uint32_t *maxTxFrameLen )
+{
+    S_UNIMAC_TOP_CFG1_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(address,cfgreg);
+
+    *maxTxFrameLen = cfgreg.max_pkt_size;
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_get_tx_max_frame_len);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port TX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the port maximum transmit unit size in bytes						  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    maxTxFrameLen - size of frame in bytes                         	      */
+/*                                                                            */
+/* Output:                                                                    */
+/*   																		  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_set_tx_max_frame_len(rdpa_emac emacNum,uint32_t maxTxFrameLen )
+{
+
+    S_UNIMAC_TOPCTRL_MAX_PKT_SZ_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOPCTRL_MIB_MAX_PKT_SIZE + UNIMAC_TOPCTRL_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxTxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,FRM_LEN,frame_length,UNIMAC_MAX_FRAME_LENGHT);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#else //!47622
+void mac_hwapi_set_tx_max_frame_len(rdpa_emac emacNum,uint32_t maxTxFrameLen )
+{
+
+    S_UNIMAC_TOP_CFG1_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxTxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,FRM_LEN,frame_length,UNIMAC_MAX_FRAME_LENGHT);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_set_tx_max_frame_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port RX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the port maximum receive unit size in bytes							  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                           	     										  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   maxRxFrameLen - size of current MRU									  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_get_rx_max_frame_len(rdpa_emac emacNum,uint32_t *maxRxFrameLen )
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,FRM_LEN,frame_length,*maxRxFrameLen );
+}
+#else //!47622
+void mac_hwapi_get_rx_max_frame_len(rdpa_emac emacNum,uint32_t *maxRxFrameLen )
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,RX_MAX_PKT_SIZE,max_pkt_size,*maxRxFrameLen );
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_get_rx_max_frame_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_rx_max_frame_len		                                      */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port RX MTU                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the port maximum receive unit size in bytes							  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*    maxRxFrameLen - size of current MRU        							  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   									  									  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_set_rx_max_frame_len(rdpa_emac emacNum,uint32_t maxRxFrameLen )
+{
+    S_UNIMAC_TOPCTRL_MAX_PKT_SZ_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOPCTRL_MIB_MAX_PKT_SIZE + UNIMAC_TOPCTRL_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxRxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,FRM_LEN,frame_length,maxRxFrameLen);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#else //!47622
+void mac_hwapi_set_rx_max_frame_len(rdpa_emac emacNum,uint32_t maxRxFrameLen )
+{
+    S_UNIMAC_TOP_CFG1_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    READ_32(address,cfgreg);
+    cfgreg.max_pkt_size = maxRxFrameLen;
+    WRITE_32(address,cfgreg);
+
+    UNIMAC_WRITE_FIELD(emacNum,RX_MAX_PKT_SIZE,max_pkt_size,maxRxFrameLen);
+
+    /*put emac out sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_set_rx_max_frame_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_tx_igp_len	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port inter frame gap                                 	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the inter frame gap	size in bytes									  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   txIpgLen - length in bytes                                               */
+/*                                                                            */
+/* Output:                                                                    */
+/*    																		  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_tx_igp_len(rdpa_emac emacNum,uint32_t txIpgLen )
+{
+    /*we assume that txIpgLen called with bits time resolution*/
+    uint32_t	newIpg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put emac in sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON );
+
+    txIpgLen += 7;
+    newIpg = txIpgLen / 8;
+
+    if (newIpg < 8)
+    {
+        newIpg = 8;
+    } else if (newIpg > 27)
+    {
+        newIpg = 27;
+    }
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,newIpg );
+
+    /*put emac out sw reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF );
+
+}
+EXPORT_SYMBOL(mac_hwapi_set_tx_igp_len);
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_igp_len	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port inter frame gap                                 	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the inter frame gap	size in bytes									  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                      							          */
+/*                                                                            */
+/* Output:                                                                    */
+/*    txIpgLen - length in bytes    										  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_igp_len(rdpa_emac emacNum,uint32_t *txIpgLen )
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,*txIpgLen );
+
+}
+EXPORT_SYMBOL(mac_hwapi_get_tx_igp_len);
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_mac_status	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port status                                         	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the status of mac													  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    macStatus  :  														  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_mac_status(rdpa_emac emacNum,S_HWAPI_MAC_STATUS *macStatus)
+{
+
+}
+EXPORT_SYMBOL(mac_hwapi_get_mac_status);
+
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_flow_control                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - get port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*           																  */
+/*                                                                            */
+/* Output:                                                                    */
+/*   flowControl - structure with parameters of tx and rx flow control		  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_get_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    uint32_t	rxFlow, txFlow;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ_FIELD(emacNum,CMD,rx_pause_ignore,rxFlow);
+    UNIMAC_READ_FIELD(emacNum,CMD,tx_pause_ignore,txFlow);
+    flowControl->rxFlowEnable	= !rxFlow;
+    flowControl->txFlowEnable	= !txFlow;
+}
+#else //!47622
+void mac_hwapi_get_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    uint32_t	rxFlow, txFlow, value;
+    uintptr_t	misc_top_address;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    misc_top_address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+    READ_32(misc_top_address, value);
+
+
+    if(value & UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT)
+    {
+        UNIMAC_READ_FIELD(emacNum,CMD,rx_pause_ignore,rxFlow);
+        UNIMAC_READ_FIELD(emacNum,CMD,tx_pause_ignore,txFlow);
+        flowControl->rxFlowEnable	= !rxFlow;
+        flowControl->txFlowEnable	= !txFlow;
+    }
+    else
+    {
+        flowControl->rxFlowEnable = 0;
+        flowControl->txFlowEnable = 0;
+    }
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_get_flow_control);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_pause_params                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   flowControl - structure with parameters of tx and rx flow control        */
+/*                                                                            */
+/* Output:                                                                    */
+/*   						  												  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_pause_params(rdpa_emac emacNum,int32_t pauseCtrlEnable,uint32_t pauseTimer,uint32_t pauseQuanta)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_control_en,pauseCtrlEnable );
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_timer,pauseTimer );
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_QUNAT,pause_quant,pauseQuanta );
+}
+EXPORT_SYMBOL(mac_hwapi_set_pause_params);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_flow_control                                               */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - set port flow control                                    	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	set the flow control of a port											  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*   flowControl - structure with parameters of tx and rx flow control        */
+/*                                                                            */
+/* Output:                                                                    */
+/*   						  												  */
+/*                                                                            */
+/******************************************************************************/
+#if defined(CONFIG_BCM947622)
+void mac_hwapi_set_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_override_rx, 1);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_override_tx, 1);
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,rx_pause_ignore, !flowControl->rxFlowEnable);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,tx_pause_ignore, !flowControl->txFlowEnable);
+}
+#else //!47622
+void mac_hwapi_set_flow_control(rdpa_emac emacNum,S_MAC_HWAPI_FLOW_CTRL *flowControl)
+{
+    uintptr_t misc_top_address;
+    uint32_t value;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_WRITE_FIELD(emacNum,CMD,rx_pause_ignore, !flowControl->rxFlowEnable);
+    UNIMAC_WRITE_FIELD(emacNum,CMD,tx_pause_ignore, !flowControl->txFlowEnable);
+    misc_top_address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+    READ_32(misc_top_address, value);
+
+    if(flowControl->rxFlowEnable || flowControl->txFlowEnable)
+        value |= UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT;
+    else
+        value &= ~UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT;
+
+    WRITE_32(misc_top_address, value);
+}
+#endif //!47622
+EXPORT_SYMBOL(mac_hwapi_set_flow_control);
+
+
+static rdpa_emac_rx_stat_t rxCountersLast[MAX_NUM_OF_EMACS];
+#define UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, param) \
+    do{\
+        uint32_t  paramCurrent = rxCounters->param; \
+        if(mac_unlikely(rxCounters->param < rxCountersLast[emacNum].param)){    \
+            rxCounters->param += (0xFFFFFFFF-rxCountersLast[emacNum].param)+1;    \
+        }else{  \
+            rxCounters->param -= rxCountersLast[emacNum].param; \
+        }   \
+        rxCountersLast[emacNum].param   = paramCurrent; \
+    }while(0)
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_rx_counters	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	get the rx counters of port                           	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the rx counters of port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    rxCounters  :  structure filled with counters							  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_rx_counters(rdpa_emac emacNum,rdpa_emac_rx_stat_t *rxCounters)
+{
+    uint32_t		tempVal;
+
+    if (!(enabled_emac & (1 << emacNum)))
+    {
+        memset(rxCounters, 0, sizeof(rdpa_emac_rx_stat_t));
+        return;
+    }
+
+    UNIMAC_READ32_MIB(emacNum,GRALN,rxCounters->alignment_error);
+    UNIMAC_READ32_MIB(emacNum,GRBCA,rxCounters->broadcast_packet);
+    UNIMAC_READ32_MIB(emacNum,GRUC, rxCounters->unicast_packet);
+    UNIMAC_READ32_MIB(emacNum,GRBYT,rxCounters->byte);
+    UNIMAC_READ32_MIB(emacNum,RRBYT,tempVal);
+    rxCounters->byte                    +=	tempVal;
+    UNIMAC_READ32_MIB(emacNum,GRFCR,rxCounters->carrier_sense_error);
+    UNIMAC_READ32_MIB(emacNum,GRCDE,rxCounters->code_error);
+    UNIMAC_READ32_MIB(emacNum,GRXCF,rxCounters->control_frame);
+    UNIMAC_READ32_MIB(emacNum,GRFCS,rxCounters->fcs_error);
+    rxCounters->fragments				=	0;//?????
+    UNIMAC_READ32_MIB(emacNum,GR255,rxCounters->frame_128_255);
+    UNIMAC_READ32_MIB(emacNum,GR2047,tempVal);
+    rxCounters->frame_1519_mtu			=	tempVal;
+    UNIMAC_READ32_MIB(emacNum,GR4095,tempVal);
+    rxCounters->frame_1519_mtu			+=	tempVal;
+    UNIMAC_READ32_MIB(emacNum,GR9216,tempVal);
+    rxCounters->frame_1519_mtu			+=	tempVal;
+
+    UNIMAC_READ32_MIB(emacNum,GR511,rxCounters->frame_256_511);
+
+    UNIMAC_READ32_MIB(emacNum,GR1023,rxCounters->frame_512_1023);
+
+    UNIMAC_READ32_MIB(emacNum,GR1518,rxCounters->frame_1024_1518);
+
+    UNIMAC_READ32_MIB(emacNum,GR64,rxCounters->frame_64);
+
+    UNIMAC_READ32_MIB(emacNum,GR127,rxCounters->frame_65_127);
+
+    UNIMAC_READ32_MIB(emacNum,GRFLR,rxCounters->frame_length_error);
+
+    UNIMAC_READ32_MIB(emacNum,GRJBR,rxCounters->jabber);
+
+    UNIMAC_READ32_MIB(emacNum,GRMCA,rxCounters->multicast_packet);
+
+    rxCounters->overflow				=	0;//no matched counter
+    UNIMAC_READ32_MIB(emacNum,GROVR,rxCounters->oversize_packet);
+	
+    UNIMAC_READ32_MIB(emacNum,RRPKT,rxCounters->undersize_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GRPKT,rxCounters->packet);
+    
+    UNIMAC_READ32_MIB(emacNum,GRXPF,rxCounters->pause_control_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GRXUO,rxCounters->unknown_opcode);
+
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, alignment_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, broadcast_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, unicast_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, byte);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, carrier_sense_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, code_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, control_frame);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, fcs_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_64);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_65_127);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_128_255);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_256_511);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_512_1023);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_1024_1518);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_1519_mtu);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, frame_length_error);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, jabber);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, multicast_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, oversize_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, undersize_packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, packet);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, pause_control_frame);
+    UNIMAC_CURRENT_RX_COUNTERS(emacNum, rxCounters, unknown_opcode);
+}
+EXPORT_SYMBOL(mac_hwapi_get_rx_counters);
+
+
+static rdpa_emac_tx_stat_t txCountersLast[MAX_NUM_OF_EMACS];
+#define UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, param) \
+    do{\
+        uint32_t  paramCurrent = txCounters->param; \
+        if(mac_unlikely(txCounters->param < txCountersLast[emacNum].param)){    \
+            txCounters->param += (0xFFFFFFFF-txCountersLast[emacNum].param)+1;    \
+        }else{  \
+            txCounters->param -= txCountersLast[emacNum].param; \
+        }   \
+        txCountersLast[emacNum].param   = paramCurrent; \
+    }while(0)
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_tx_counters	                                              */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	get the tx counters of port                           	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	get the tx counters of port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*    txCounters  :  structure filled with counters							  */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_tx_counters(rdpa_emac emacNum,rdpa_emac_tx_stat_t *txCounters)
+{
+    /*fill the rdpa counters structure*/
+    uint32_t		tempVal;
+
+    if (!(enabled_emac & (1 << emacNum)))
+    {
+        memset(txCounters, 0, sizeof(rdpa_emac_tx_stat_t));
+        return;
+    }
+
+    UNIMAC_READ32_MIB(emacNum,GTBYT,txCounters->byte);
+
+    UNIMAC_READ32_MIB(emacNum,GTBCA,txCounters->broadcast_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTMCA, txCounters->multicast_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTUC, txCounters->unicast_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTXCF,txCounters->control_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTDRF,txCounters->deferral_packet);
+
+
+    UNIMAC_READ32_MIB(emacNum,GTNCL,tempVal);
+    txCounters->error						= tempVal;
+    UNIMAC_READ32_MIB(emacNum,GTOVR,tempVal);
+    txCounters->error						+= tempVal;
+    UNIMAC_READ32_MIB(emacNum,GTFCS,tempVal);
+    txCounters->error						+= tempVal;
+    UNIMAC_READ32_MIB(emacNum,GTEDF,txCounters->excessive_deferral_packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTFCS,txCounters->fcs_error	);
+
+    UNIMAC_READ32_MIB(emacNum,GTFRG,txCounters->fragments_frame);
+
+    UNIMAC_READ32_MIB(emacNum,TR1518,txCounters->frame_1024_1518);
+
+    UNIMAC_READ32_MIB(emacNum,TR255,  txCounters->frame_128_255);
+
+    UNIMAC_READ32_MIB(emacNum,TR2047,  tempVal);
+    txCounters->frame_1519_mtu			=   tempVal;
+    UNIMAC_READ32_MIB(emacNum,TR4095,  tempVal);
+    txCounters->frame_1519_mtu			+=   tempVal;
+    UNIMAC_READ32_MIB(emacNum,TR9216,  tempVal);
+    txCounters->frame_1519_mtu			+=   tempVal;
+    UNIMAC_READ32_MIB(emacNum,TR511,  txCounters->frame_256_511);
+
+    UNIMAC_READ32_MIB(emacNum,TR1023, txCounters->frame_512_1023);
+
+    UNIMAC_READ32_MIB(emacNum,TR64,txCounters->frame_64);
+
+    UNIMAC_READ32_MIB(emacNum,TR127, txCounters->frame_65_127);
+
+    UNIMAC_READ32_MIB(emacNum,GTJBR, txCounters->jabber_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTLCL, txCounters->late_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTMCL, txCounters->multiple_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTOVR,txCounters->oversize_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTPOK, txCounters->packet);
+
+    UNIMAC_READ32_MIB(emacNum,GTXPF, txCounters->pause_control_frame);
+
+    UNIMAC_READ32_MIB(emacNum,GTSCL, txCounters->single_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTNCL, txCounters->total_collision);
+
+    UNIMAC_READ32_MIB(emacNum,GTXCL, txCounters->excessive_collision);
+
+    txCounters->underrun					=	0;
+    txCounters->undersize_frame				=	0;
+
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, byte);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, broadcast_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, multicast_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, unicast_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, deferral_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, excessive_deferral_packet);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, control_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, jabber_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, oversize_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, pause_control_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, fragments_frame);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, error);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, fcs_error);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_64);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_65_127);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_128_255);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_256_511);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_512_1023);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_1024_1518);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, frame_1519_mtu);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, single_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, total_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, late_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, multiple_collision);
+    UNIMAC_CURRENT_TX_COUNTERS(emacNum, txCounters, excessive_collision);
+}
+EXPORT_SYMBOL(mac_hwapi_get_tx_counters);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_init_emac	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_init_emac(rdpa_emac emacNum)
+{
+    /*configure the emac and put it in automatic speed mode*/
+    S_UNIMAC_CMD_REG	mCfgReg;
+    uint32_t max_frame_length = UNIMAC_MAX_FRAME_LENGHT;
+
+    /*before calling this function make sure you pull out of reset the emac */
+
+    /*put the emac in sw_reset state*/
+    //UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCfgReg);
+    /* Do the initialization */
+    mCfgReg.tx_ena          =   0;
+    mCfgReg.rx_ena          =   0;
+    /* for 63138 - even though the EMAC_1 is connected to SF2 @ 2Gbps, we still set the link to 1G.
+     * Actual speed of the link is derived from SF2 based on the speed set for IMP port#8.  */
+    mCfgReg.eth_speed		=	UNIMAC_SPEED_1000;
+    mCfgReg.promis_en		=	1;
+    mCfgReg.pad_en			=	0;
+    mCfgReg.pause_fwd		=	1;
+    mCfgReg.crc_fwd			=	1;
+    mCfgReg.ena_ext_config	=	0;
+    mCfgReg.rx_pause_ignore	=	0;
+    mCfgReg.tx_pause_ignore	=	0;
+    mCfgReg.tx_addr_ins		=	0;
+    mCfgReg.lcl_loop_ena	=	0;
+    mCfgReg.cntl_frm_ena	=	1;
+    mCfgReg.no_lgth_check	=	1;
+    mCfgReg.rmt_loop_ena	=	0;
+    mCfgReg.rx_err_disc		=	0;
+    mCfgReg.prbl_ena		=	0;
+    mCfgReg.cntl_frm_ena	=	1;
+
+    /*write the configuration */
+    UNIMAC_WRITE32_REG(emacNum,CMD,mCfgReg);
+    UNIMAC_WRITE32_REG(emacNum,FRM_LEN, max_frame_length);
+
+    /*take out the emac from sw_reset state*/
+    //UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+#if 0
+    /*configure the pause control*/
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_timer,UNIMAC_DEFAULT_PAUSE_TIMER);
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_CNTRL,pause_control_en,1);
+
+    /*configure the pause quanta*/
+    UNIMAC_WRITE_FIELD(emacNum,PAUSE_QUNAT,pause_quant,UNIMAC_DEFAULT_PAUSE_QUANTA);
+
+    /*write default ipg*/
+    UNIMAC_WRITE_FIELD(emacNum,TX_IPG_LEN,tx_ipg_len,UNIMAC_DEFAULT_IPG);
+#endif
+    memset(&rxCountersLast, 0, MAX_NUM_OF_EMACS*sizeof(rdpa_emac_rx_stat_t));
+    memset(&txCountersLast, 0, MAX_NUM_OF_EMACS*sizeof(rdpa_emac_tx_stat_t));
+
+    enabled_emac |= (1 << emacNum);
+
+    /*emac is ready to go!*/
+}
+EXPORT_SYMBOL(mac_hwapi_init_emac);
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_get_loopback	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	init the emac to well known state                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_get_loopback(rdpa_emac emacNum,MAC_LPBK *loopback)
+{
+    S_UNIMAC_CMD_REG	mCmdReg;
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    UNIMAC_READ32_REG(emacNum,CMD,mCmdReg);
+
+    if (mCmdReg.lcl_loop_ena && mCmdReg.rmt_loop_ena)
+    {
+        *loopback = MAC_LPBK_BOTH;
+    }
+    else if (mCmdReg.lcl_loop_ena)
+    {
+        *loopback = MAC_LPBK_LOCAL;
+    }
+    else if (mCmdReg.rmt_loop_ena)
+    {
+        *loopback = MAC_LPBK_REMOTE;
+    }
+    else
+    {
+        *loopback = MAC_LPBK_NONE;
+    }
+
+}
+EXPORT_SYMBOL(mac_hwapi_get_loopback);
+
+
+/******************************************************************************/
+/*                                                                            */
+/* Name:                                                                      */
+/*                                                                            */
+/*   mac_hwapi_set_loopback	                         	                     */
+/*                                                                            */
+/* Title:                                                                     */
+/*                                                                            */
+/*   MAC Driver - 	set loopback type of the mac	                      	  */
+/*                                                                            */
+/* Abstract:                                                                  */
+/*                                                                            */
+/* 	initialized the emac port				  								  */
+/*                                                                            */
+/* Input:                                                                     */
+/*                                                                            */
+/*   emacNum - emac Port index           	                                  */
+/*                                                                            */
+/*                                                                            */
+/* Output:                                                                    */
+/*                                                                            */
+/******************************************************************************/
+void mac_hwapi_set_loopback(rdpa_emac emacNum,MAC_LPBK loopback)
+{
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    /*put the emac in sw_reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_ON);
+
+    switch(loopback)
+    {
+        case MAC_LPBK_BOTH:
+            UNIMAC_WRITE_FIELD(emacNum,CMD,rmt_loop_ena,1);
+            UNIMAC_WRITE_FIELD(emacNum,CMD, lcl_loop_ena,1);
+            break;
+        case MAC_LPBK_LOCAL:
+            UNIMAC_WRITE_FIELD(emacNum,CMD, lcl_loop_ena,1);
+            break;
+        case MAC_LPBK_REMOTE:
+            UNIMAC_WRITE_FIELD(emacNum,CMD,rmt_loop_ena,1);
+            break;
+        case MAC_LPBK_NONE:
+            UNIMAC_WRITE_FIELD(emacNum,CMD,rmt_loop_ena,0);
+            UNIMAC_WRITE_FIELD(emacNum,CMD, lcl_loop_ena,0);
+            break;
+        default:
+
+            break;
+    }
+    /* take out the emac from sw_reset state*/
+    UNIMAC_WRITE_FIELD(emacNum,CMD,sw_reset,UNIMAC_SWRESET_OFF);
+
+}
+EXPORT_SYMBOL(mac_hwapi_set_loopback);
+
+void mac_hwapi_set_unimac_cfg(rdpa_emac emacNum, int32_t enabled)
+{
+#if !defined(CONFIG_BCM947622) && !defined(CONFIG_BCM963146) && !defined(CONFIG_BCM94912)
+    S_UNIMAC_CFG_REG cfgreg;
+    uintptr_t address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(address,cfgreg);
+    cfgreg.gmii_direct = enabled ? 1 : 0;
+    WRITE_32(address,cfgreg);
+#endif
+}
+EXPORT_SYMBOL(mac_hwapi_set_unimac_cfg);
+
+void mac_hwapi_modify_flow_control_pause_pkt_addr ( rdpa_emac emacNum,bdmf_mac_t mac)
+{
+    uint32_t value = *(uint32_t*)(&(mac.b[4])) >> 16 ;
+    uintptr_t mac_address = (uintptr_t)UNIMAC_CONFIGURATION_UMAC_0_RDP_MAC0 + UNIMAC_CONF_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    WRITE_32(mac_address, *(uint32_t*)mac.b);
+
+    mac_address = (uintptr_t)UNIMAC_CONFIGURATION_UMAC_0_RDP_MAC1 + UNIMAC_CONF_INSTANCE_OFFSET(emacNum);
+    WRITE_32(mac_address, value);
+
+}
+EXPORT_SYMBOL(mac_hwapi_modify_flow_control_pause_pkt_addr);
+
+void mac_hwapi_set_backpressure_ext(rdpa_emac emacNum,int32_t enable)
+{
+#if defined(CONFIG_BCM963138) || defined(CONFIG_BCM963148) || defined(CONFIG_BCM94908) || defined(CONFIG_BCM963158)
+    S_UNIMAC_TOP_CFG2_REG cfgreg;
+    uintptr_t misc_top_address = (uintptr_t)UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2 + UNIMAC_MISC_INSTANCE_OFFSET(emacNum);
+
+    if (!(enabled_emac & (1 << emacNum)))
+        return;
+
+    READ_32(misc_top_address,cfgreg);
+    cfgreg.backpressure_enable_ext = (enable ? 1 : 0);
+    WRITE_32(misc_top_address,cfgreg);
+#endif
+}
+EXPORT_SYMBOL(mac_hwapi_set_backpressure_ext);
+
+void mac_hwapi_set_eee(rdpa_emac emacNum, int32_t enable)
+{
+    uint32_t eee_ref_count = 0;
+    uint32_t eee_wake_timer = 0;
+    uint32_t eee_lpi_timer = 0;
+
+    S_UNIMAC_EEE_CTRL_REG eee_ctrl;
+    S_HWAPI_MAC_STATUS  mac_mode;
+
+    /* Determine EEE timers only when EEE is enabled */
+    if (enable)
+    {
+#if defined(CONFIG_BCM963158) || defined(CONFIG_BCM96846) || defined(CONFIG_BCM96856) || defined(CONFIG_BCM947622) || defined(CONFIG_BCM96878) || defined(CONFIG_BCM963146) || defined(CONFIG_BCM94912)
+        eee_ref_count = 0xfa; /* 250 Mhz */;
+#else
+        get_rdp_freq(&eee_ref_count);
+        eee_ref_count /= 2;
+#endif
+
+        /* Read actual mac speed */
+        UNIMAC_READ32_REG(emacNum, MODE, mac_mode);
+
+        switch (mac_mode.mac_speed) {
+        case rdpa_emac_rate_100m: /* 100Mbps */
+            {
+                eee_lpi_timer = 0x3c; /* 60 uS */
+                eee_wake_timer = 0x1e; /* 30 uS */
+                break;
+            }
+        case rdpa_emac_rate_1g: /* 1000Mbps */
+            {
+                eee_lpi_timer = 0x22; /* 34 uS */
+                eee_wake_timer = 0x11; /* 17 uS */
+                break;
+            }
+        case rdpa_emac_rate_2_5g: /* 2500Mbps */
+            {
+                eee_lpi_timer = 0x3c; /* 60 uS */
+                eee_wake_timer = 0x1e; /* 30 uS */
+                break;
+            }
+        default:
+            break;
+        }
+    }
+
+    UNIMAC_READ32_REG(emacNum, EEE_CTRL, eee_ctrl);
+    eee_ctrl.eee_en = enable ? 1 : 0;
+    UNIMAC_WRITE32_REG(emacNum, EEE_CTRL, eee_ctrl);
+    UNIMAC_WRITE32_REG(emacNum, EEE_REF_COUNT, eee_ref_count);
+
+#if defined(CONFIG_BCM96856) || defined(CONFIG_BCM947622)
+    if (mac_mode.mac_speed == rdpa_emac_rate_100m)
+    {
+        UNIMAC_WRITE32_REG(emacNum, EEE_MII_LPI_TIMER, eee_lpi_timer);
+        UNIMAC_WRITE32_REG(emacNum, EEE_MII_WAKE_TIMER, eee_wake_timer);
+    }
+    else
+    {
+        UNIMAC_WRITE32_REG(emacNum, EEE_GMII_LPI_TIMER, eee_lpi_timer);
+        UNIMAC_WRITE32_REG(emacNum, EEE_GMII_WAKE_TIMER, eee_wake_timer);
+    }
+#else
+    UNIMAC_WRITE32_REG(emacNum, EEE_LPI_TIMER, eee_lpi_timer);
+    UNIMAC_WRITE32_REG(emacNum, EEE_WAKE_TIMER, eee_wake_timer);
+#endif
+}
+EXPORT_SYMBOL(mac_hwapi_set_eee);
diff --git a/drivers/net/bcmbca/phy/xrdp_led_init.c b/drivers/net/bcmbca/phy/xrdp_led_init.c
new file mode 100644
index 0000000000..d0fd82bbae
--- /dev/null
+++ b/drivers/net/bcmbca/phy/xrdp_led_init.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2016 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+
+/*
+ *  Created on: Apr 2019
+ *      Author: samyon.furman@broadcom.com
+ */
+
+#include "os_dep.h"
+#include "bcm_bca_leds_dt_bindings.h"
+#include "bcm_bca_leds.h"
+#include "dt_access.h"
+
+static uintptr_t xrdpled_base;
+
+static int xrdpled_probe(dt_device_t *pdev)
+{
+    int ret;
+
+    xrdpled_base = dt_dev_remap_resource(pdev, 0);
+    if (IS_ERR(xrdpled_base))
+    {
+        ret = PTR_ERR(xrdpled_base);
+        xrdpled_base = NULL;
+        dev_err(&pdev->dev, "Missing xrdpled_base entry\n");
+        goto Exit;
+    }
+
+    dev_dbg(&pdev->dev, "xrdpled_base=0x%lx\n", xrdpled_base);
+    dev_info(&pdev->dev, "registered\n");
+
+    return 0;
+
+Exit:
+    return ret;
+}
+
+#ifdef __UBOOT__
+static const struct udevice_id xrdpled_ids[] = {
+    { .compatible = "brcm,xrdp-led" },
+    { /* end of list */ },
+};
+
+U_BOOT_DRIVER(brcm_xrdpled) = {
+    .name	= "brcm-xrdpled",
+    .id	= UCLASS_MISC,
+    .of_match = xrdpled_ids,
+    .probe = xrdpled_probe,
+};
+#else
+static const struct of_device_id of_platform_table[] = {
+    { .compatible = "brcm,xrdp-led" },
+    { /* end of list */ },
+};
+
+static struct platform_driver of_platform_driver = {
+    .driver = {
+        .name = "brcm-xrdpled",
+        .of_match_table = of_platform_table,
+    },
+    .probe = xrdpled_probe,
+};
+module_platform_driver(of_platform_driver);
+#endif
+
+typedef union {
+    struct {
+        uint32_t rx_act_en                 :1 ; // [00:00]
+        uint32_t tx_act_en                 :1 ; // [01:01]
+        uint32_t spdlnk_led0_act_sel       :1 ; // [02:02]
+        uint32_t spdlnk_led1_act_sel       :1 ; // [03:03]
+        uint32_t spdlnk_led2_act_sel       :1 ; // [04:04]
+        uint32_t act_led_act_sel           :1 ; // [05:05]
+        uint32_t spdlnk_led0_act_pol_sel   :1 ; // [06:06]
+        uint32_t spdlnk_led1_act_pol_sel   :1 ; // [07:07]
+        uint32_t spdlnk_led2_act_pol_sel   :1 ; // [08:08]
+        uint32_t act_led_pol_sel           :1 ; // [09:09]
+        uint32_t led_spd_ovrd              :3 ; // [12:10]
+        uint32_t lnk_status_ovrd           :1 ; // [13:13]
+        uint32_t spd_ovrd_en               :1 ; // [14:14]
+        uint32_t lnk_ovrd_en               :1 ; // [15:15]
+        uint32_t r1                        :16; // [31:16]
+    }Bits;
+    uint32_t Reg32;
+}XRDP_LED_CTRL;
+
+typedef union {
+    struct {
+        uint32_t sel_no_link_encode        :3 ; // [02:00] 
+        uint32_t sel_10m_encode            :3 ; // [05:03]
+        uint32_t sel_100m_encode           :3 ; // [08:06]
+        uint32_t sel_1000m_encode          :3 ; // [11:09]
+        uint32_t sel_2500m_encode          :3 ; // [14:12]
+        uint32_t sel_10g_encode            :3 ; // [17:15]
+        uint32_t r1                        :14; // [31:18]
+    }Bits;
+    uint32_t Reg32;
+}XRDP_LED_LINK_SPEED_ENC_SEL;
+
+typedef union {
+    struct {
+        uint32_t no_link_encode            :3 ; // [02:00]
+        uint32_t m10_encode                :3 ; // [05:03]
+        uint32_t m100_encode               :3 ; // [08:06]
+        uint32_t m1000_encode              :3 ; // [11:09]
+        uint32_t m2500_encode              :3 ; // [14:12]
+        uint32_t m10g_encode               :3 ; // [17:15]
+        uint32_t r1                        :14; // [31:18]
+    }Bits;
+    uint32_t Reg32;
+}XRDP_LED_LINK_SPEED_ENC;
+
+typedef union {
+    struct {
+        uint32_t port_en                   :16; // [15:00]
+        uint32_t act_sel                   :1 ; // [16:16]
+        uint32_t act_pol_sel               :1 ; // [17:17]
+        uint32_t lnk_pol_sel               :1 ; // [18:18]
+        uint32_t r1                        :13; // [31:19]
+    }Bits;
+    uint32_t Reg32;
+}XRDP_LED_AGGREGATE_CTRL;
+
+typedef struct XrdpLedRegs {
+    XRDP_LED_CTRL                   led_ctrl[5];
+    uint32_t                          reserved0[3];
+    XRDP_LED_LINK_SPEED_ENC_SEL     led_link_speed_enc_sel[5];
+    uint32_t                          reserved1[3];
+    XRDP_LED_LINK_SPEED_ENC         led_link_speed_enc[5];
+    uint32_t                          reserved2[3];
+    uint32_t                          led_blink_rate_ctrl;
+    uint32_t                          led_pwm_ctrl;
+    uint32_t                          led_intensity_ctrl;
+    XRDP_LED_AGGREGATE_CTRL         led_aggregate_ctrl;
+    uint32_t                          led_aggregate_blink_rate_ctrl;
+    uint32_t                          led_aggregate_pwm_ctrl;
+    uint32_t                          led_aggregate_intensity_ctrl;
+    uint32_t                          led_sw_init_ctrl;
+} XrdpLedRegs;
+
+#define XRDP_LED_BASE       (void *)xrdpled_base
+#define XRDP_LED            ((volatile XrdpLedRegs * const) XRDP_LED_BASE)
+
+int xrdp_leds_init(void *_leds_info)
+{
+    bca_leds_info_t *leds_info = (bca_leds_info_t *)_leds_info;
+    int ret = 0;
+    int j;
+    XRDP_LED_CTRL led_ctrl;
+    XRDP_LED_LINK_SPEED_ENC_SEL spdlnk_sel;
+    XRDP_LED_LINK_SPEED_ENC spdlnk;
+    uint32_t port = leds_info->port_id;
+    XRDP_LED_AGGREGATE_CTRL agg_ctrl;
+
+    uint8_t activity;
+
+    if(port == 0xff)
+    {
+        /* No Led info provided */
+        return 0;
+    }
+
+    spdlnk_sel.Bits.sel_10g_encode = 0;
+    spdlnk_sel.Bits.sel_1000m_encode = 0;
+    spdlnk_sel.Bits.sel_100m_encode = 0;
+    spdlnk_sel.Bits.sel_2500m_encode = 0;
+    spdlnk_sel.Bits.sel_10m_encode = 0;
+    spdlnk_sel.Bits.sel_no_link_encode = 0;
+
+    spdlnk.Bits.m10g_encode = 7;
+    spdlnk.Bits.m2500_encode = 7;
+    spdlnk.Bits.m1000_encode = 7;
+    spdlnk.Bits.m100_encode = 7;
+    spdlnk.Bits.m10_encode = 7;
+    spdlnk.Bits.no_link_encode = 7;
+
+    led_ctrl.Reg32 = XRDP_LED->led_ctrl[port].Reg32;
+
+    agg_ctrl.Reg32 = XRDP_LED->led_aggregate_ctrl.Reg32;
+    agg_ctrl.Bits.act_sel = 1;
+    agg_ctrl.Bits.act_pol_sel = 0;
+    agg_ctrl.Bits.lnk_pol_sel = 1;
+
+    if (!leds_info->skip_in_aggregate)
+        agg_ctrl.Bits.port_en |= 1<<port;
+    XRDP_LED->led_aggregate_ctrl.Reg32 = agg_ctrl.Reg32;
+
+    if (!leds_info->skip_in_aggregate)
+        XRDP_LED->led_aggregate_ctrl.Bits.port_en |= 1<<port;
+
+    for (j = 0; j < 3; j++)
+    {
+        uint32_t led_mux = leds_info->link[j];
+        uint32_t led_activity = leds_info->activity[j];
+        activity = 0;
+
+        if (led_mux & LED_SPEED_10G)
+            spdlnk.Bits.m10g_encode &= ~(1<<j);
+        if (led_mux & LED_SPEED_2500)
+            spdlnk.Bits.m2500_encode &= ~(1<<j);
+        if (led_mux & LED_SPEED_1G)
+            spdlnk.Bits.m1000_encode &= ~(1<<j);
+        if (led_mux & LED_SPEED_100)
+            spdlnk.Bits.m100_encode &= ~(1<<j);
+        if (led_mux & LED_SPEED_10)
+            spdlnk.Bits.m10_encode &= ~(1<<j);
+
+        if (led_activity & LED_SPEED_10G)
+            spdlnk_sel.Bits.sel_10g_encode |= (1<<j);
+        if (led_activity & LED_SPEED_2500)
+            spdlnk_sel.Bits.sel_2500m_encode |= (1<<j);
+        if (led_activity & LED_SPEED_1G)
+            spdlnk_sel.Bits.sel_1000m_encode |= (1<<j);
+        if (led_activity & LED_SPEED_100)
+            spdlnk_sel.Bits.sel_100m_encode |= (1<<j);
+        if (led_activity & LED_SPEED_10)
+            spdlnk_sel.Bits.sel_10m_encode |= (1<<j);
+
+        /* to configure the speed led to show activity only for specified
+           speeds */
+        if (led_activity && !(led_mux & led_activity))
+            activity = 1;
+
+        switch (j)
+        {
+        case 0:
+            led_ctrl.Bits.spdlnk_led0_act_sel = activity;
+            break;
+        case 1:
+            led_ctrl.Bits.spdlnk_led1_act_sel = activity;
+            break;
+        case 2:
+            led_ctrl.Bits.spdlnk_led2_act_sel = activity;
+            break;
+        }
+    }
+            
+    if (leds_info->activity[3] || leds_info->link[3])
+        led_ctrl.Bits.act_led_act_sel = leds_info->link[3] ? 0 : 1;
+
+    XRDP_LED->led_link_speed_enc_sel[port].Reg32 = spdlnk_sel.Reg32;
+    XRDP_LED->led_link_speed_enc[port].Reg32 = spdlnk.Reg32;
+    XRDP_LED->led_ctrl[port].Reg32 = led_ctrl.Reg32;
+    printk("%s Port %d configured \n", __FUNCTION__, port);
+
+    return ret;
+}
diff --git a/drivers/net/bcmbca/phy/xrdp_led_init.h b/drivers/net/bcmbca/phy/xrdp_led_init.h
new file mode 100644
index 0000000000..ad58f0751b
--- /dev/null
+++ b/drivers/net/bcmbca/phy/xrdp_led_init.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom Corporation
+   All Rights Reserved
+
+    
+*/
+/*
+ * xrdp_led_init.h
+ *
+ *  Created on: April 2019
+ *      Author: samyon.furman@broadcom.com
+ */
+
+#ifndef _XRDP_LED_INIT_H_
+#define _XRDP_LED_INIT_H_
+
+int xrdp_led_init(int port);
+
+#if !defined(XRDP_LED)
+static inline
+#endif
+int xrdp_leds_init(void * _leds_info)
+#if !defined(XRDP_LED)
+{ return 0; }
+#endif
+;
+
+#endif
diff --git a/drivers/net/bcmbca/xrdp/Makefile b/drivers/net/bcmbca/xrdp/Makefile
new file mode 100644
index 0000000000..356744a1ea
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/Makefile
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+CHIP_ID = $(patsubst "bcm%",%,$(CONFIG_SYS_SOC))
+KBUILD_CPPFLAGS += -DCONFIG_BCM9$(CHIP_ID)
+KBUILD_CPPFLAGS += -Werror
+
+obj-y += \
+	bcmbca_xrdp_api.o \
+	access_logging.o \
+	data_path_$(CHIP_ID).o
+
+ifdef CONFIG_BCMBCA_XRDP_PON
+KBUILD_CPPFLAGS += -DXRDP_SBPM -DGEN45
+obj-y += rdp_drv_sbpm.o
+else # CONFIG_BCMBCA_XRDP_DSL
+KBUILD_CPPFLAGS += -DXRDP_DIRECT
+endif
diff --git a/drivers/net/bcmbca/xrdp/access_logging.c b/drivers/net/bcmbca/xrdp/access_logging.c
new file mode 100644
index 0000000000..653ddfa22f
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/access_logging.c
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+/*
+ * access_logging.c
+ */
+
+#include <common.h>
+#include "access_macros.h"
+#include "access_logging.h"
+
+#define xrdp_usleep(_a) udelay(_a)
+
+#define ACCESS_LOG_PRINT(_args...)  printf(_args);
+
+/* #define ACCESS_LOG_DEBUG_ENABLE */
+
+#ifdef ACCESS_LOG_DEBUG_ENABLE
+#define ACCESS_LOG_DEBUG(_args...)  ACCESS_LOG_PRINT(_args)
+#else
+#define ACCESS_LOG_DEBUG(_args...)
+#endif
+
+uintptr_t rdp_runner_core_addr[1];
+
+extern int access_log_restore(const access_log_tuple_t *entry_array)
+{
+	int rc = 0;
+	int i;
+	volatile uint32_t *p_addr;
+	uint32_t start_val;
+	uint32_t adaptive_val;
+	const access_log_tuple_t *entry = entry_array;
+	uint32_t addr;
+	uint32_t op;
+	uint32_t size;
+	uint32_t value;
+	addr_op_size_st addr_op_size;
+
+	while (1) {
+		addr_op_size.value = entry->addr_op_size;
+		op = addr_op_size.op_code;
+		size = addr_op_size.size;
+		addr = addr_op_size.addr + 0x82000000;
+		if ((op == ACCESS_LOG_OP_WRITE) || (op == ACCESS_LOG_OP_MWRITE)
+			|| (op == ACCESS_LOG_OP_WRITE_6BYTE_ADDR)) {
+			if (op == ACCESS_LOG_OP_WRITE_6BYTE_ADDR)
+				addr-= 0x82000000;
+
+			if (size == 4)
+				*(volatile uint32_t *)((uintptr_t)addr) = (uint32_t)(entry->value);
+			else if (size == 2)
+				*(volatile uint16_t *)((uintptr_t)addr) = (uint16_t)(entry->value);
+			else if (size == 1)
+				*(volatile uint8_t *)((uintptr_t)addr) = (uint8_t)(entry->value);
+			else {
+				ACCESS_LOG_PRINT("!!!!!!! op=%d: invalid entry size %u\n", op, size);
+				rc = -1;
+				break;
+			}
+			ACCESS_LOG_DEBUG("write op(%d) size(%d) addr 0x%x "\
+				"data 0x%x\n", op, size, addr, entry->value);
+		}
+		else if (op == ACCESS_LOG_OP_SLEEP) {
+			ACCESS_LOG_PRINT("Sleep %u...\n", entry->value);
+			xrdp_usleep(entry->value);
+		}
+		else if (op == ACCESS_LOG_OP_MEMSET) {
+			size = entry->value;
+			++entry;
+			addr = entry->addr_op_size;
+			value = entry->value;
+			ACCESS_LOG_DEBUG("MEMSET(0x%x, %u, %u)\n", addr, value,
+				size);
+			MEMSET((void *)(uintptr_t)addr, value, size);
+		}
+		else if (op == ACCESS_LOG_OP_MEMSET_32) {
+			size = entry->value;
+			++entry;
+			addr = entry->addr_op_size;
+			value = entry->value;
+			ACCESS_LOG_DEBUG("MEMSET_32(0x%x, %u, %u)\n", addr,
+				value, size);
+			MEMSET_32((void *)(uintptr_t)addr, value, size);
+		}
+		else if (op == ACCESS_LOG_OP_MEMSET_ADAPTIVE_32) {
+			size = entry->value;
+			++entry;
+			addr = entry->addr_op_size;
+			value = entry->value;
+			p_addr = (volatile uint32_t *)(uintptr_t)addr;
+			start_val = value & 0xffff;
+			adaptive_val = (value >> 16) & 0xffff;;
+			ACCESS_LOG_DEBUG("MEMSET_ADAPTIVE_32(0x%lx, %u %u, %u)\n",
+				addr, start_val, adaptive_val, size);
+
+			for (i = 0; i < size; i++) {
+				p_addr[i] = (uint32_t)start_val;
+				start_val += adaptive_val;
+			}
+		}
+		else if (op == ACCESS_LOG_OP_SET_CORE_ADDR) {
+			ACCESS_LOG_DEBUG("SET_CORE_ADDR[%u] = 0x%lx\n",
+				entry->value, addr);
+			rdp_runner_core_addr[entry->value] = addr;
+		}
+		else if (op == ACCESS_LOG_OP_STOP) {
+			break;
+		}
+		else {
+			ACCESS_LOG_PRINT("!!!!!!! op=%d: invalid operation\n",
+				op);
+			rc = -1;
+			break;
+		}
+		++entry;
+	}
+
+	if (entry) {
+		ACCESS_LOG_PRINT("%s: %d entries processed\n", __FUNCTION__,
+			(int)(entry - entry_array));
+	}
+
+	return rc;
+}
diff --git a/drivers/net/bcmbca/xrdp/access_logging.h b/drivers/net/bcmbca/xrdp/access_logging.h
new file mode 100644
index 0000000000..eefac9fd3d
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/access_logging.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _ACCESS_LOGGING_H_
+#define _ACCESS_LOGGING_H_
+
+#include <linux/types.h>
+
+typedef enum
+{
+    ACCESS_LOG_OP_WRITE,
+    ACCESS_LOG_OP_MWRITE,
+    ACCESS_LOG_OP_MEMSET,
+    ACCESS_LOG_OP_MEMSET_32,
+    ACCESS_LOG_OP_SLEEP,
+    ACCESS_LOG_OP_SET_CORE_ADDR,
+    ACCESS_LOG_OP_STOP,
+    ACCESS_LOG_OP_MEMSET_ADAPTIVE_32,
+    ACCESS_LOG_OP_WRITE_6BYTE_ADDR,
+} access_log_op_t;
+
+typedef union os_size_st_union {
+    uint32_t value;
+    struct {
+        uint32_t addr:24;
+        uint32_t op_code : 4;
+        uint32_t size : 4;
+    };
+} addr_op_size_st;
+
+typedef struct access_log_tuple
+{
+    uint32_t addr_op_size;
+    uint32_t value;
+} access_log_tuple_t;
+
+extern int access_log_restore(const access_log_tuple_t *entry_array);
+
+#endif /* _ACCESS_LOGGING_H_ */
+
diff --git a/drivers/net/bcmbca/xrdp/access_macros.h b/drivers/net/bcmbca/xrdp/access_macros.h
new file mode 100644
index 0000000000..ecc227c4d9
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/access_macros.h
@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef __ACCESS_MACROS_H_INCLUDED
+#define __ACCESS_MACROS_H_INCLUDED
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <linux/types.h>
+
+#define swap2bytes cpu_to_be16
+#define swap4bytes cpu_to_be32
+
+#define DEVICE_ADDRESS(_a) ((volatile uint8_t * const)(_a))
+
+#if defined(DUAL_ISSUE)
+#define MEMSET(a, v, sz)                _xrdp__memset(a, v, sz)
+#else
+#define MEMSET(a, v, sz)                memset_io(a, v, sz)
+#endif
+
+#define WMB()  /* */
+
+#define VAL32(_a) (*(volatile uint32_t *)(DEVICE_ADDRESS(_a)))
+#define READ_32(a, r) (*(volatile uint32_t *)&(r) = readl(DEVICE_ADDRESS(a)))
+#define WRITE_32(a, r) writel(*(uint32_t *)&(r), DEVICE_ADDRESS(a))
+
+#define MGET_8(a)               readb(a)
+#define MGET_16(a)              swap2bytes(readw(a))
+#define MGET_32(a)              swap4bytes(readl(a))
+
+#define MWRITE_8(a, r) writeb((uint8_t)(r), a)
+#define MWRITE_16(a, r) writew(swap2bytes((uint16_t)(r)), a)
+#define MWRITE_32(a, r) MWRITE_I_32(a, 0, r)
+#define MWRITE_I_32(a, i, r) \
+	do {\
+		(*((volatile uint32_t *)(a) + (i)) = swap4bytes((uint32_t)(r))); \
+	} while (0)
+
+#define MREAD_8(a, r)           ((r) = MGET_8(a))
+#define MREAD_16(a, r)          ((r) = MGET_16(a))
+#define MREAD_32(a, r)          ((r) = MGET_32(a))
+
+#define MEMSET_32(a, v_32, sz_32)  \
+	do { \
+		int __i;\
+		for (__i=0; __i<sz_32; __i++)\
+		MWRITE_I_32(a, __i, v_32);\
+	} while (0)
+
+/**************************/
+/* Bit-field access macros
+: v     -  value
+: lsbn  - ls_bit_number
+: fw    - field_width
+: a     - address
+: rv    - read_value      */
+/**************************/
+#define FIELD_GET(v, lsbn, fw)          (((v)>>(lsbn)) & ((unsigned)(1 << (fw)) - 1))
+#define FIELD_MGET_32(a, lsbn, fw)      (FIELD_GET(MGET_32(a), (lsbn), (fw)))
+#define FIELD_MGET_16(a, lsbn, fw)      (FIELD_GET(MGET_16(a), (lsbn), (fw)))
+#define FIELD_MGET_8(a, lsbn, fw)       (FIELD_GET(MGET_8(a) , (lsbn), (fw)))
+
+#define FIELD_MREAD_16(a, lsbn, fw, rv) (rv = FIELD_MGET_16((a),   (lsbn), (fw)))
+
+#define FIELD_SET(value, ls_bit_number, field_width, write_value) \
+	do { \
+		uint32_t  mask; \
+		mask = ((1 << (field_width)) - 1) << (ls_bit_number); \
+		value &=  ~mask; \
+		value |= (write_value) << (ls_bit_number); \
+	} while (0)
+
+#define FIELD_MWRITE_32(address, ls_bit_number, field_width, write_value) \
+	do { \
+		uint32_t current_value = MGET_32(address); \
+		FIELD_SET(current_value, ls_bit_number, field_width, write_value); \
+		MWRITE_32(address, current_value); \
+	} while (0)
+
+#define FIELD_MWRITE_16(address, ls_bit_number, field_width, write_value) \
+	do { \
+		uint16_t current_value = MGET_16(address); \
+		FIELD_SET(current_value, ls_bit_number, field_width, write_value); \
+		MWRITE_16(address, current_value); \
+	} while (0)
+
+#define FIELD_MWRITE_8(address, ls_bit_number, field_width, write_value) \
+	do { \
+		uint8_t  current_value = MGET_8(address); \
+		FIELD_SET(current_value, ls_bit_number, field_width, write_value); \
+		MWRITE_8(address, current_value); \
+	} while (0)
+
+#if defined(DUAL_ISSUE)
+static inline void *_xrdp__memcpy(void *dst, void const *src, size_t len)
+{
+	uint8_t *u8dst_ptr = (uint8_t *)dst;
+	uint8_t const *u8src_ptr = (uint8_t const *)src;
+	uint src_alignment =
+		(uint)((uintptr_t)src & (uintptr_t)(sizeof(uint32_t) - 1));
+	uint dst_alignment =
+		(uint)((uintptr_t)dst & (uintptr_t)(sizeof(uint32_t) - 1));
+	uint32_t *u32dst_ptr;
+	uint32_t const *u32src_ptr;
+
+	if (len >= sizeof(uint32_t) &&  src_alignment == dst_alignment ) {
+		while (((uintptr_t)u8src_ptr &
+			(uintptr_t)(sizeof(uint32_t) - 1)) != 0) {
+			*u8dst_ptr++ = *u8src_ptr++;
+			len--;
+		}
+
+		{
+			u32dst_ptr = (uint32_t *)u8dst_ptr;
+			u32src_ptr = (uint32_t const *)u8src_ptr;
+
+			while (len >= sizeof(uint32_t)) {
+				*u32dst_ptr++ = *u32src_ptr++;
+				len -= sizeof(uint32_t);
+			}
+
+			u8dst_ptr = (uint8_t *)u32dst_ptr;
+			u8src_ptr = (uint8_t const *)u32src_ptr;
+		}
+	}
+
+	while (len--)
+		*u8dst_ptr++ = *u8src_ptr++;
+
+	return dst;
+}
+
+static inline void *_xrdp__memset(void *dst, int v, size_t len)
+{
+	uint8_t *u8dst_ptr = (uint8_t *)dst;
+	uint8_t c_val = (uint8_t)v;
+	uint32_t u32_val = c_val<<24 || c_val<<16 || c_val<<8 || c_val<<24;
+	uint32_t *u32dst_ptr;
+
+	while (len &&(((uintptr_t)u8dst_ptr &
+		(uintptr_t)(sizeof(uint32_t) - 1)) != 0)) {
+		*u8dst_ptr++ = c_val;
+		len--;
+	}
+
+	u32dst_ptr = (uint32_t *)u8dst_ptr;
+	while (len >= sizeof(uint32_t)) {
+		*u32dst_ptr++ = u32_val;
+		len -= sizeof(uint32_t);
+	}
+
+	while (len) {
+		*u8dst_ptr++ = c_val;
+		len--;
+	}
+
+	return dst;
+}
+#endif
+
+#endif
+
diff --git a/drivers/net/bcmbca/xrdp/bcmbca_xrdp_api.c b/drivers/net/bcmbca/xrdp/bcmbca_xrdp_api.c
new file mode 100644
index 0000000000..ba70048acd
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/bcmbca_xrdp_api.c
@@ -0,0 +1,437 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *	Copyright 2020 Broadcom Ltd.
+ *	Ido Brezel <ido.brezel@broadcom.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "rdd_data_structures.h"
+
+#ifdef XRDP_SBPM
+extern int drv_sbpm_copy_list(uint16_t bn, uint8_t *dest_buffer);
+extern int drv_sbpm_free_list(uint16_t head_bn);
+extern int drv_sbpm_alloc_list(uint32_t size, uint32_t headroom, uint8_t *data,
+	uint16_t *bn0, uint16_t *bn1, uint8_t *bns_num);
+#endif
+
+#define cfe_core_runner_image 0
+#define IMAGE_0_CFE_CORE_CPU_TX_THREAD_NUMBER 1
+
+// #define DEBUG_DUMP_PACKET
+
+#define INV_RANGE(_addr, _size) invalidate_dcache_range((unsigned long)_addr,\
+	(unsigned long)(_addr + _size))
+#define FLUSH_RANGE(_addr, _size) flush_dcache_range((unsigned long)_addr,\
+	(unsigned long)(_addr + _size))
+
+typedef struct
+{
+	union {
+		struct {
+			uint32_t word0;
+			uint32_t word1;
+		};
+		struct {
+			uint32_t reserved0:14;
+			uint32_t fpm_idx:18;
+			uint32_t reserved2:1;
+			uint32_t is_chksum_verified:1;
+			uint32_t packet_length:14;
+			uint32_t abs:1;
+			uint32_t reserved1:15;
+		} fpm;
+		struct {
+			uint32_t reserved0:14;
+			uint32_t bn0:18;
+			uint32_t reserved2:1;
+			uint32_t is_chksum_verified:1;
+			uint32_t packet_length:14;
+			uint32_t abs:1;
+			uint32_t reserved1:15;
+		} sbpm;
+	};
+	union {
+		uint32_t word2;
+		struct {
+			uint32_t reason:6;
+			uint32_t data_offset:7;
+			uint32_t reserved3:12;
+			uint32_t source_port:5; /* LAN */
+			uint32_t reserved7:1;
+			uint32_t is_src_lan:1;
+		} lan;
+	};
+	uint32_t word3;
+}
+CPU_RX_DESCRIPTOR;
+
+struct cpu_rx_params {
+	uint8_t *data_ptr;
+	uint8_t data_offset;
+	uint16_t packet_size;
+	uint16_t reason;
+	uint16_t src_bridge_port;
+};
+
+#ifdef XRDP_DIRECT
+static int cpu_ring_read_packet(uint32_t ring_id,
+	struct cpu_rx_params *rx_params)
+{
+	CPU_RX_DESCRIPTOR rx_desc;
+	uint32_t *desc_addr = (uint32_t *)RDD_SRAM_PD_FIFO_PTR(0);
+	static int idx;
+	volatile void *last_read_idx_ptr = RDD_CPU_RX_LAST_READ_INDEX_PTR(0);
+	uint8_t *rx_buffer;
+
+	rx_params->reason = 0;
+	rx_params->packet_size = 0;
+
+	desc_addr += idx;
+	rx_desc.word2 = swap4bytes(readl(desc_addr + 2));
+	rx_desc.word3 = swap4bytes(readl(desc_addr + 3));
+	rx_desc.word1 = swap4bytes(readl(desc_addr + 1));
+	rx_desc.word0 = swap4bytes(readl(desc_addr));
+
+	if ((rx_desc.word2 == 0) || (rx_desc.word1 == 0))
+		return -ENOSR;
+
+	/* The place of data_ofset is the same in all structures in this union
+	 * we could use any
+	 */
+	rx_params->data_offset = rx_desc.lan.data_offset;
+	rx_params->packet_size = rx_desc.fpm.packet_length;
+	rx_params->src_bridge_port = rx_desc.lan.source_port;
+	rx_params->reason = (uint16_t)rx_desc.lan.reason;
+
+	rx_buffer = (uint8_t *)((unsigned long)rx_desc.word0);
+	INV_RANGE(rx_buffer, rx_params->packet_size + rx_params->data_offset);
+	memcpy(rx_params->data_ptr, rx_buffer, rx_params->packet_size + rx_params->data_offset);
+
+	MWRITE_16(last_read_idx_ptr, ((uintptr_t)desc_addr & 0xffff));
+	idx = (idx + 4) % (RDD_SRAM_PD_FIFO_SIZE * 4);
+
+	return 0;
+}
+#else /* if defined(XRDP_SBPM) */
+static int GetPdFromRamFifo(uint32_t *word0, uint32_t *word1, uint32_t *word2,
+	uint32_t *word3)
+{
+	uint32_t *desc_addr = (uint32_t *)RDD_SRAM_PD_FIFO_PTR(0);
+	static int idx;
+
+	INV_RANGE((uintptr_t)desc_addr, (64 * 16));
+
+	desc_addr += idx;
+	*word1 = swap4bytes(readl(desc_addr + 1));
+	*word0 = swap4bytes(readl(desc_addr));
+	*word2 = swap4bytes(readl(desc_addr + 2));
+	*word3 = swap4bytes(readl(desc_addr + 3));
+
+	if (*word1 == 0)
+		return -1;
+
+	writel(0, desc_addr + 3);
+	writel(0, desc_addr + 2);
+	writel(0, desc_addr);
+	writel(0, desc_addr + 1);
+	idx = (idx + 4) % (RDD_SRAM_PD_FIFO_SIZE * 4);
+
+	return 0;
+}
+
+static int cpu_ring_read_packet(uint32_t ring_id,
+	struct cpu_rx_params *rx_params)
+{
+	CPU_RX_DESCRIPTOR rx_desc;
+
+	rx_params->reason = 0;
+	rx_params->packet_size = 0;
+	if (GetPdFromRamFifo(&rx_desc.word0, &rx_desc.word1, &rx_desc.word2,
+		&rx_desc.word3)) {
+		return -ENOSR;
+	}
+
+	/* The place of data_ofset is the same in all structures in this union
+	 * we could use any
+	 */
+	rx_params->data_offset = rx_desc.lan.data_offset;
+	rx_params->packet_size = rx_desc.fpm.packet_length;
+	rx_params->src_bridge_port = rx_desc.lan.source_port;
+	rx_params->reason = (uint16_t)rx_desc.lan.reason;
+
+	if (drv_sbpm_copy_list(rx_desc.sbpm.bn0, rx_params->data_ptr)) {
+		printf("copy sbpm failed\n");
+		return -ENOSR;
+	}
+
+	if (drv_sbpm_free_list(rx_desc.sbpm.bn0)) {
+		printf("free sbpm failed\n");
+		return -ENOSR;
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef XRDP_BBH_PER_LAN_PORT
+#define EGRESS_COUNTER_SIZE 8
+#else
+#define EGRESS_COUNTER_SIZE 1
+#endif
+
+static volatile void *bbh_pd_table;
+static void *counters_table;
+static volatile void *bb_dest_table;
+static uint8_t bbh_ingress_counter[8];
+
+
+#define RDD_CPU_TX_MAX_ITERS	2
+#define RDD_CPU_TX_ITER_DELAY	1000
+#define RDD_CPU_TX_MAX_BUF_SIZE 2048
+
+static int __rdd_cpu_tx_poll(uint8_t tx_port)
+{
+	volatile void *tx_pd;
+	void *counter_id;
+	int old_packet_size;
+	int iter;
+	int egress_counter_val;
+
+	/* Init when first called */
+	if (!bbh_pd_table) {
+		bbh_pd_table = RDD_BBH_TX_RING_TABLE_PTR(cfe_core_runner_image);
+		counters_table =
+			(uint32_t *)RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_PTR(
+			cfe_core_runner_image);
+		bb_dest_table = RDD_BBH_TX_BB_DESTINATION_TABLE_PTR(
+			cfe_core_runner_image);
+	}
+
+	tx_pd = bbh_pd_table;
+	/* First counter index */
+	counter_id = counters_table;
+	/* egress counters are either 8 or 64 bit alignment */
+	counter_id += tx_port * EGRESS_COUNTER_SIZE;
+
+	/* Wait until TX_PD becomes available */
+	RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ(old_packet_size, tx_pd);
+
+	RDD_BBH_TX_EGRESS_COUNTER_ENTRY_COUNTER_READ(egress_counter_val,
+		counter_id);
+
+	for (iter = 0; ((old_packet_size != 0) ||
+		((bbh_ingress_counter[tx_port] - egress_counter_val) >= 8)
+		/*BBH_TX_FIFO_SIZE*/) && (iter < RDD_CPU_TX_MAX_ITERS);
+		iter++) {
+		udelay(RDD_CPU_TX_ITER_DELAY);
+		RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ(old_packet_size,
+			tx_pd);
+		RDD_BBH_TX_EGRESS_COUNTER_ENTRY_COUNTER_READ(egress_counter_val,
+			counter_id);
+	}
+	if (iter == RDD_CPU_TX_MAX_ITERS) {
+		printf("non empty at bbh full(ingress=%d,egress=%d,diff=%d)\n",
+			bbh_ingress_counter[tx_port],
+			egress_counter_val,
+			bbh_ingress_counter[tx_port] - egress_counter_val);
+		return -1;
+	}
+
+	return 0;
+}
+
+#ifdef XRDP_DIRECT
+static int rdd_cpu_tx(uint8_t *buffer, uint32_t length, uint8_t tx_port)
+{
+	volatile void *tx_pd;
+	volatile void *bb_dest;
+	uint32_t bb_id;
+	uint32_t *tx_buffer_ptr = (uint32_t *)PACKET_BUFFER_POOL_TABLE_ADDR_TX;
+	int rc;
+
+	if (length >= RDD_CPU_TX_MAX_BUF_SIZE) {
+		printf("ERR: can't transmit buffer with length %u longer "
+			"than %d\n", length, RDD_CPU_TX_MAX_BUF_SIZE);
+		return -1;
+	}
+
+	rc = __rdd_cpu_tx_poll(tx_port);
+	if (rc)
+		return rc;
+
+	tx_pd = bbh_pd_table;
+	bb_dest = bb_dest_table;
+
+	/* copy buffer to the fix location */
+	memcpy(tx_buffer_ptr, buffer, length);
+	FLUSH_RANGE(tx_buffer_ptr, length);
+
+	/* complete TX descriptor */
+	RDD_BBH_TX_DESCRIPTOR_LAST_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_ABS_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_0_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_1_WRITE(1, tx_pd);
+
+	bb_id = __rdd_cpu_tx_get_bb_id(tx_port);
+	RDD_BB_DESTINATION_ENTRY_BB_DESTINATION_WRITE(bb_id, bb_dest);
+
+	/* must be latest write */
+	if (length < ETH_ZLEN)
+		length = ETH_ZLEN;
+	RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(length, tx_pd);
+
+	WMB();
+
+	/* update ingress counter */
+	bbh_ingress_counter[tx_port] += 1;
+	rnr_regs_cfg_cpu_wakeup_set(cfe_core_runner_image,
+		IMAGE_0_CFE_CORE_CPU_TX_THREAD_NUMBER);
+
+	return 0;
+}
+#endif
+
+#ifdef XRDP_SBPM
+static int rdd_cpu_tx_sbpm(uint32_t length, uint16_t bn0, uint16_t bn1,
+	uint8_t bns_num, uint8_t tx_port)
+{
+	volatile void *tx_pd;
+	volatile void *bb_dest;
+	uint32_t bb_id;
+	int rc;
+
+	if (length >= RDD_CPU_TX_MAX_BUF_SIZE) {
+		printf("ERR: can't transmit buffer with length %u longer than"\
+			"%d\n", length, RDD_CPU_TX_MAX_BUF_SIZE);
+		return -1;
+	}
+
+	rc = __rdd_cpu_tx_poll(tx_port);
+	if (rc)
+		return rc;
+
+	tx_pd = bbh_pd_table;
+	bb_dest = bb_dest_table;
+
+	/* transmit */
+#define CPU_TX_DESCRIPTOR_STRUCT_SIZE 32
+	memset((void *)tx_pd, 0, CPU_TX_DESCRIPTOR_STRUCT_SIZE);
+	RDD_BBH_TX_DESCRIPTOR_SOF_WRITE(0, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_LAST_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_AGG_PD_WRITE(0, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_ABS_WRITE(0, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_SOP_WRITE(0, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_BN0_FIRST_WRITE(bn0, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_BN1_FIRST_WRITE(bn1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_0_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_1_WRITE(1, tx_pd);
+	RDD_BBH_TX_DESCRIPTOR_BN_NUM_WRITE(bns_num, tx_pd);
+
+	bb_id = __rdd_cpu_tx_get_bb_id(tx_port);
+	RDD_BB_DESTINATION_ENTRY_BB_DESTINATION_WRITE(bb_id, bb_dest);
+
+	/* must be latest write */
+	RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(length, tx_pd);
+
+	bbh_ingress_counter[tx_port] += 1;
+
+	rnr_regs_cfg_cpu_wakeup_set(cfe_core_runner_image,
+		IMAGE_0_CFE_CORE_CPU_TX_THREAD_NUMBER);
+
+	return 0;
+}
+
+static int rdd_cpu_tx(uint8_t *buffer, uint32_t length, uint8_t tx_port)
+{
+	uint16_t bn0, bn1;
+	uint8_t bns_num;
+	int rc;
+
+	rc = drv_sbpm_alloc_list(length, 0, buffer, &bn0, &bn1, &bns_num);
+	if (rc) {
+		printf("%s: Failed to allocate sbpm (%d)\n", __func__, rc);
+		return rc;
+	}
+
+	return rdd_cpu_tx_sbpm(length, bn0, bn1, bns_num, tx_port);
+}
+#endif
+
+int bcmbca_xrdp_init(void)
+{
+	int rc = 0;
+
+	printf("%s: Restore HW configuration\n", __func__);
+	rc = xrdp_data_path_init();
+	printf("%s: Restore HW configuration done. rc=%d\n", __func__, rc);
+
+	return rc;
+}
+
+#ifdef DEBUG_DUMP_PACKET
+static void dump_packet(uint8_t *data_ptr, uint16_t size)
+{
+	int i;
+
+	for (i = 0; i < size; i++) {
+		if ((i & 0xf) == 0)
+			printf("0x%x:", i);
+		if ((i & 0x3) == 0)
+			printf(" ");
+		printf("%02x ", data_ptr[i]);
+		if ((i & 0xf) == 0xf)
+			printf("\n");
+	}
+	if ((i & 0xf) != 0)
+		printf("\n");
+}
+#endif
+
+int bcmbca_xrdp_send(void *buffer, uint16_t length, uint8_t tx_port)
+{
+#ifdef DEBUG_DUMP_PACKET
+	printf("%s:%d:send to port %d, buffer is @0x%p, size = %d\n", __func__,
+		__LINE__, tx_port, buffer, length);
+	dump_packet((uint8_t *)buffer, length);
+#endif
+
+	return rdd_cpu_tx(buffer, length, tx_port);
+}
+
+int bcmbca_xrdp_recv(uint8_t **buffer, uint16_t *length, uint8_t *rx_port)
+{
+	int rc;
+	struct cpu_rx_params rx_params;
+
+	rx_params.data_ptr = *buffer;
+	rc = cpu_ring_read_packet(0, &rx_params);
+	if (rc) {
+#ifdef DEBUG_DUMP_PACKET // XXX check what should be printed here
+		printf("NET: RDD error receive: %d len=%d reason=%d\n",
+			rc, (int)rx_params.packet_size, rx_params.reason);
+#endif
+		return -EAGAIN;
+	}
+
+#ifdef DEBUG_DUMP_PACKET
+	printf("Dumping received packet: port %d, size %d, "\
+		"data_ptr %p, data_offset %d, "\
+		"reason %d\n",
+		rx_params.src_bridge_port, rx_params.packet_size,
+		rx_params.data_ptr, rx_params.data_offset,
+		rx_params.reason);
+	dump_packet(rx_params.data_ptr, rx_params.packet_size);
+#endif
+
+	if (!rx_params.packet_size) {
+		printf("NET: Get zero length packet\n");
+		return -EAGAIN;
+	}
+
+	*buffer = rx_params.data_ptr;
+	*rx_port = rx_params.src_bridge_port;
+	*length = rx_params.packet_size;
+
+	return 0;
+}
diff --git a/drivers/net/bcmbca/xrdp/bcmbca_xrdp_api.h b/drivers/net/bcmbca/xrdp/bcmbca_xrdp_api.h
new file mode 100644
index 0000000000..6f4c537d3f
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/bcmbca_xrdp_api.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *	Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _BCMBCA_XRD_API_H_
+#define _BCMBCA_XRD_API_H_
+
+int bcmbca_xrdp_init(void);
+int bcmbca_xrdp_send(void *buffer, int length, uint8_t tx_port);
+int bcmbca_xrdp_recv(uint8_t **buffer, uint16_t *length, uint8_t *rx_port);
+
+extern int dt_probe(void);
+extern uint32_t dt_get_ports_num(void);
+extern mac_dev_t *dt_get_mac_dev(uint32_t port);
+extern phy_dev_t *dt_get_phy_dev(uint32_t port);
+
+#endif
diff --git a/drivers/net/bcmbca/xrdp/bdmf_data_types.h b/drivers/net/bcmbca/xrdp/bdmf_data_types.h
new file mode 100644
index 0000000000..3f46672495
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/bdmf_data_types.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+/*******************************************************************
+ * bdmf_types.h
+ *
+ * Broadcom Device Management Framework - built-in attribute types
+ *
+ *******************************************************************/
+
+#ifndef BDMF_DATA_TYPES_H_
+#define BDMF_DATA_TYPES_H_
+
+typedef struct {
+    uint8_t b[6];  /**< Address bytes */
+} bdmf_mac_t;
+
+#endif /* BDMF_DATA_TYPES_H_ */
diff --git a/drivers/net/bcmbca/xrdp/data_path_4912.c b/drivers/net/bcmbca/xrdp/data_path_4912.c
new file mode 100644
index 0000000000..fa9b58ed35
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/data_path_4912.c
@@ -0,0 +1,748 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include "access_logging.h"
+
+const access_log_tuple_t init_data[] = {
+	{ 0x408a0014 , 0x82a00000 },
+	{ 0x408a0018 , 0x82c00000 },
+	{ 0x408a001c , 0x82c00000 },
+	{ 0x408a0020 , 0x82c80000 },
+	{ 0x408a0024 , 0x82c80000 },
+	{ 0x408a0028 , 0x82d00000 },
+	{ 0x408a0004 , 0x82700000 },
+	{ 0x408a0008 , 0x82900000 },
+	{ 0x408a000c , 0x82900000 },
+	{ 0x408a0010 , 0x82a00000 },
+	{ 0x4089c008 , 0x20002 },
+	{ 0x4089d008 , 0x20002 },
+	{ 0x4089e008 , 0x20002 },
+	{ 0x5700000 , 0x0 },
+	{ 0x40800030 , 0x3000d },
+	{ 0x4000000 , 0x5 },
+	{ 0x3000000 , 0x2000 },
+	{ 0x82710000 , 0xfc000000 },
+	{ 0x41710000 , 0x6008006 },
+	{ 0x4171000c , 0x19008006 },
+	{ 0x41710018 , 0x26 },
+	{ 0x41710020 , 0x6f80a0a },
+	{ 0x41710024 , 0xc43aac },
+	{ 0x41710028 , 0x40020b0 },
+	{ 0x4171002c , 0x21008004 },
+	{ 0x41710030 , 0x740110b0 },
+	{ 0x41710034 , 0x638000cc },
+	{ 0x41710038 , 0xb83aac },
+	{ 0x4171003c , 0xf4ff73b0 },
+	{ 0x41710040 , 0xe0a00184 },
+	{ 0x41710044 , 0x18800006 },
+	{ 0x41710048 , 0xe1831a8 },
+	{ 0x4171004c , 0x2100c004 },
+	{ 0x41710050 , 0x840370b0 },
+	{ 0x41710054 , 0x40020b0 },
+	{ 0x41710058 , 0x46a003cc },
+	{ 0x41710060 , 0x21000004 },
+	{ 0x41710064 , 0x2ec0036 },
+	{ 0x41710068 , 0x42ec1036 },
+	{ 0x4171006c , 0x83ec2036 },
+	{ 0x41710070 , 0x3ed4036 },
+	{ 0x41710074 , 0x83ed6036 },
+	{ 0x41710078 , 0x3ee8036 },
+	{ 0x4171007c , 0x83eea036 },
+	{ 0x41710080 , 0x3efc036 },
+	{ 0x41710084 , 0x83efe036 },
+	{ 0x41710088 , 0x3f00037 },
+	{ 0x4171008c , 0x83f02037 },
+	{ 0x41710090 , 0x3f14037 },
+	{ 0x41710094 , 0x83f16037 },
+	{ 0x41710098 , 0x3f28037 },
+	{ 0x4171009c , 0x83f2a037 },
+	{ 0x417100a0 , 0x3f3c037 },
+	{ 0x417100a4 , 0x83f3e037 },
+	{ 0x417100a8 , 0x820010c6 },
+	{ 0x417100ac , 0x9610ac },
+	{ 0x417100b0 , 0xc2dd1036 },
+	{ 0x417100b4 , 0x2e602002 },
+	{ 0x417100b8 , 0x2f602002 },
+	{ 0x417100bc , 0x30602002 },
+	{ 0x417100c0 , 0xc2 },
+	{ 0x417100c4 , 0x32602002 },
+	{ 0x417100c8 , 0x33602002 },
+	{ 0x417100cc , 0x34602002 },
+	{ 0x417100d0 , 0x2ec0032 },
+	{ 0x417100d4 , 0x42ec1032 },
+	{ 0x417100d8 , 0x83ec2032 },
+	{ 0x417100dc , 0x3ed4032 },
+	{ 0x417100e0 , 0x83ed6032 },
+	{ 0x417100e4 , 0x3ee8032 },
+	{ 0x417100e8 , 0x83eea032 },
+	{ 0x417100ec , 0x3efc032 },
+	{ 0x417100f0 , 0x83efe032 },
+	{ 0x417100f4 , 0x3f00033 },
+	{ 0x417100f8 , 0x83f02033 },
+	{ 0x417100fc , 0x3f14033 },
+	{ 0x41710100 , 0x83f16033 },
+	{ 0x41710104 , 0x3f28033 },
+	{ 0x41710108 , 0x83f2a033 },
+	{ 0x4171010c , 0x3f3c033 },
+	{ 0x41710110 , 0x83f3e033 },
+	{ 0x41710120 , 0x1008022 },
+	{ 0x41710130 , 0x440030b0 },
+	{ 0x41710134 , 0x4d820b0 },
+	{ 0x41710138 , 0x81319e },
+	{ 0x4171013c , 0x60003180 },
+	{ 0x41710140 , 0x140040b0 },
+	{ 0x41710144 , 0x2802130 },
+	{ 0x41710148 , 0x80002180 },
+	{ 0x4171014c , 0x2802134 },
+	{ 0x41710150 , 0x22802138 },
+	{ 0x41710154 , 0x80002182 },
+	{ 0x41710158 , 0x2280213c },
+	{ 0x4171015c , 0x43004839 },
+	{ 0x41710160 , 0x300e830 },
+	{ 0x41710164 , 0xcd7cca0a },
+	{ 0x41710168 , 0x60262aac },
+	{ 0x4171016c , 0xc0aa57ac },
+	{ 0x41710170 , 0x20006196 },
+	{ 0x41710174 , 0x40030b0 },
+	{ 0x41710178 , 0x4d820b0 },
+	{ 0x4171017c , 0x81319e },
+	{ 0x41710180 , 0x60002180 },
+	{ 0x41710184 , 0x2003130 },
+	{ 0x41710188 , 0x80803180 },
+	{ 0x4171018c , 0xb887ac },
+	{ 0x41710190 , 0x2003134 },
+	{ 0x41710194 , 0x22003138 },
+	{ 0x41710198 , 0x813180 },
+	{ 0x4171019c , 0x80803182 },
+	{ 0x417101a0 , 0x2200313c },
+	{ 0x417101a4 , 0xc1c03431 },
+	{ 0x417101a8 , 0x400e0b0 },
+	{ 0x417101ac , 0x40070b0 },
+	{ 0x417101b0 , 0x6481 },
+	{ 0x417101b4 , 0x40020b0 },
+	{ 0x417101b8 , 0x40030b0 },
+	{ 0x417101bc , 0x40060b0 },
+	{ 0x417101c0 , 0xc1df7033 },
+	{ 0x417101c4 , 0x40a20b84 },
+	{ 0x417101c8 , 0x90809006 },
+	{ 0x417101cc , 0x41080b0 },
+	{ 0x417101d0 , 0x4200093c },
+	{ 0x417101d4 , 0x22983 },
+	{ 0x417101d8 , 0x8012989 },
+	{ 0x417101dc , 0x300c930 },
+	{ 0x417101e0 , 0x40b8d6ac },
+	{ 0x417101e4 , 0xa00684 },
+	{ 0x417101e8 , 0x8c80c006 },
+	{ 0x417101ec , 0x2080d686 },
+	{ 0x417101f0 , 0xe180d696 },
+	{ 0x417101f4 , 0x2080d682 },
+	{ 0x417101f8 , 0xa001d294 },
+	{ 0x417101fc , 0x20808687 },
+	{ 0x41710200 , 0xc20d8b0 },
+	{ 0x41710204 , 0xdcb0 },
+	{ 0x41710208 , 0xa001c684 },
+	{ 0x4171020c , 0xe014d6ac },
+	{ 0x41710210 , 0xa0018c95 },
+	{ 0x41710214 , 0x8009c6ac },
+	{ 0x41710218 , 0x4dfd0b0 },
+	{ 0x4171021c , 0x4000c696 },
+	{ 0x41710220 , 0x8081c680 },
+	{ 0x41710224 , 0x200d630 },
+	{ 0x41710228 , 0x883d688 },
+	{ 0x4171022c , 0x200d634 },
+	{ 0x41710230 , 0x40a20b84 },
+	{ 0x41710234 , 0x7580a006 },
+	{ 0x41710238 , 0x4200093c },
+	{ 0x4171023c , 0x3000934 },
+	{ 0x41710240 , 0x200b84 },
+	{ 0x41710244 , 0xfc80d006 },
+	{ 0x41710248 , 0xb8c7ac },
+	{ 0x4171024c , 0x20008686 },
+	{ 0x41710250 , 0xe1008496 },
+	{ 0x41710254 , 0x2000c482 },
+	{ 0x41710258 , 0x4df90b1 },
+	{ 0x4171025c , 0x400d0b0 },
+	{ 0x41710260 , 0x280ac31 },
+	{ 0x41710264 , 0x40080b0 },
+	{ 0x41710268 , 0x2017da1 },
+	{ 0x4171026c , 0x818b85 },
+	{ 0x41710270 , 0x80210c84 },
+	{ 0x41710274 , 0xaa003106 },
+	{ 0x41710278 , 0x20808b82 },
+	{ 0x4171027c , 0x240486 },
+	{ 0x41710280 , 0x9a009106 },
+	{ 0x41710284 , 0xe0027295 },
+	{ 0x41710288 , 0xe802ad89 },
+	{ 0x4171028c , 0x2080d682 },
+	{ 0x41710290 , 0xf48b7617 },
+	{ 0x41710294 , 0x80809c83 },
+	{ 0x41710298 , 0x61c8026 },
+	{ 0x4171029c , 0x240080b0 },
+	{ 0x417102a0 , 0x22e04c2 },
+	{ 0x417102a8 , 0x80012294 },
+	{ 0x417102ac , 0x20002186 },
+	{ 0x417102b0 , 0x2803c30 },
+	{ 0x417102b4 , 0x12194 },
+	{ 0x417102b8 , 0x40802180 },
+	{ 0x417102bc , 0x2802c34 },
+	{ 0x417102c0 , 0x41660b0 },
+	{ 0x417102c4 , 0xc03aac },
+	{ 0x417102c8 , 0xb8c7ac },
+	{ 0x417102cc , 0x40820b0 },
+	{ 0x417102d0 , 0x4e570b0 },
+	{ 0x417102d4 , 0x40090b1 },
+	{ 0x417102d8 , 0x6381 },
+	{ 0x417102dc , 0x101c30a8 },
+	{ 0x417102e0 , 0x3681 },
+	{ 0x417102e4 , 0x7185 },
+	{ 0x417102e8 , 0xe0a20984 },
+	{ 0x417102ec , 0xcc802106 },
+	{ 0x417102f0 , 0xe0c261d1 },
+	{ 0x417102f4 , 0x22032080 },
+	{ 0x417102f8 , 0x101c30a8 },
+	{ 0x417102fc , 0x68ac23a8 },
+	{ 0x41710300 , 0xe0823985 },
+	{ 0x41710304 , 0x840380b1 },
+	{ 0x41710308 , 0xe0026b81 },
+	{ 0x4171030c , 0x2280318e },
+	{ 0x41710310 , 0x1e0422a8 },
+	{ 0x41710314 , 0x6328026 },
+	{ 0x41710318 , 0x40870b1 },
+	{ 0x4171031c , 0x40200ccc },
+	{ 0x41710320 , 0xba008006 },
+	{ 0x41710324 , 0x31802338 },
+	{ 0x41710328 , 0x203831ac },
+	{ 0x41710330 , 0x63c261d1 },
+	{ 0x41710340 , 0xe008007 },
+	{ 0x41710344 , 0xf40120b0 },
+	{ 0x41710350 , 0xa0802696 },
+	{ 0x41710354 , 0x41830b0 },
+	{ 0x41710358 , 0x12180 },
+	{ 0x4171035c , 0x60003180 },
+	{ 0x41710360 , 0x1660b0 },
+	{ 0x41710364 , 0x7680 },
+	{ 0x41710368 , 0x40820b0 },
+	{ 0x4171036c , 0x40a00384 },
+	{ 0x41710370 , 0xe2802106 },
+	{ 0x41710374 , 0x40c061d4 },
+	{ 0x41710378 , 0xdb00c006 },
+	{ 0x4171037c , 0x40807384 },
+	{ 0x41710380 , 0x40006380 },
+	{ 0x41710384 , 0x20803182 },
+	{ 0x41710388 , 0xf3c061d4 },
+	{ 0x41710398 , 0xc2038b0 },
+	{ 0x4171039c , 0xe0002496 },
+	{ 0x417103a0 , 0x3cb0 },
+	{ 0x417103a4 , 0xc8826a8 },
+	{ 0x417103a8 , 0x60008180 },
+	{ 0x417103ac , 0x60266aac },
+	{ 0x417103b0 , 0x40020b0 },
+	{ 0x417103b4 , 0x20006396 },
+	{ 0x417103b8 , 0x40030b0 },
+	{ 0x417103bc , 0xc1c03431 },
+	{ 0x417103c0 , 0x40070b0 },
+	{ 0x417103c4 , 0x6a0a4a8 },
+	{ 0x417103c8 , 0x1f0422a8 },
+	{ 0x417103cc , 0x61c20a8 },
+	{ 0x417103d0 , 0x1f0430a8 },
+	{ 0x417103d4 , 0x7a4e5a8 },
+	{ 0x417103d8 , 0x6480 },
+	{ 0x417103dc , 0x2b877a8 },
+	{ 0x417103e0 , 0x6a8a2a8 },
+	{ 0x417103e4 , 0x799529a8 },
+	{ 0x417103e8 , 0x1820a8 },
+	{ 0x417103ec , 0x1d0430a8 },
+	{ 0x417103f0 , 0x40a20884 },
+	{ 0x417103f4 , 0x16811006 },
+	{ 0x417103f8 , 0x380683c },
+	{ 0x417103fc , 0x4380283c },
+	{ 0x41710400 , 0x41020b0 },
+	{ 0x41710404 , 0x821883 },
+	{ 0x41710408 , 0x140030b0 },
+	{ 0x4171040c , 0x48801889 },
+	{ 0x41710410 , 0x81319e },
+	{ 0x41710414 , 0x4d820b0 },
+	{ 0x41710418 , 0x60002180 },
+	{ 0x4171041c , 0x2003130 },
+	{ 0x41710420 , 0x80803180 },
+	{ 0x41710424 , 0x2003134 },
+	{ 0x41710428 , 0x22003138 },
+	{ 0x4171042c , 0x80813180 },
+	{ 0x41710430 , 0x80803182 },
+	{ 0x41710434 , 0x2200313c },
+	{ 0x41710438 , 0x6a0a4a8 },
+	{ 0x4171043c , 0x90005cc },
+	{ 0x41710440 , 0x1f0442a9 },
+	{ 0x41710444 , 0x779d59a9 },
+	{ 0x41710448 , 0x7138026 },
+	{ 0x4171044c , 0x6a8a2a8 },
+	{ 0x41710450 , 0xc84145cd },
+	{ 0x41710458 , 0x3400d0b0 },
+	{ 0x4171045c , 0x4d880b0 },
+	{ 0x41710460 , 0x81d69e },
+	{ 0x41710464 , 0xa0018480 },
+	{ 0x41710468 , 0x200d430 },
+	{ 0x4171046c , 0x8080d680 },
+	{ 0x41710470 , 0x200d434 },
+	{ 0x41710474 , 0x2200d438 },
+	{ 0x41710478 , 0x8081c680 },
+	{ 0x4171047c , 0x8000c682 },
+	{ 0x41710480 , 0x2200c43c },
+	{ 0x41710484 , 0x240080b0 },
+	{ 0x41710488 , 0x61c8026 },
+	{ 0x4171048c , 0x40060b1 },
+	{ 0x41710490 , 0x22e04c2 },
+	{ 0x41710498 , 0x240030b0 },
+	{ 0x4171049c , 0x4d820b0 },
+	{ 0x417104a0 , 0x81319e },
+	{ 0x417104a4 , 0x60002180 },
+	{ 0x417104a8 , 0x2003130 },
+	{ 0x417104ac , 0xc1c03431 },
+	{ 0x417104b0 , 0x80803180 },
+	{ 0x417104b4 , 0x2003134 },
+	{ 0x417104b8 , 0x22003138 },
+	{ 0x417104bc , 0x80803182 },
+	{ 0x417104c0 , 0xe008007 },
+	{ 0x417104c4 , 0x2200313c },
+	{ 0x417104c8 , 0x240120b0 },
+	{ 0x417104d0 , 0xe010006 },
+	{ 0x417104d8 , 0x40010b0 },
+	{ 0x417104dc , 0x4e020b0 },
+	{ 0x417104e0 , 0x81109e },
+	{ 0x417104e4 , 0x20001180 },
+	{ 0x417104e8 , 0x140040b0 },
+	{ 0x417104ec , 0x2802030 },
+	{ 0x417104f0 , 0x80002180 },
+	{ 0x417104f4 , 0x2802034 },
+	{ 0x417104f8 , 0x22802038 },
+	{ 0x417104fc , 0x80002182 },
+	{ 0x41710500 , 0x2280203c },
+	{ 0x41710504 , 0x3002430 },
+	{ 0x41710508 , 0x6cc510a },
+	{ 0x4171050c , 0x43004439 },
+	{ 0x41710510 , 0x2801430 },
+	{ 0x41710514 , 0x874d8026 },
+	{ 0x41710518 , 0x41c040cd },
+	{ 0x4171051c , 0x2200043c },
+	{ 0x41710520 , 0x47610b0 },
+	{ 0x41710524 , 0x41e50b0 },
+	{ 0x41710528 , 0xb841ac },
+	{ 0x4171052c , 0x40860b0 },
+	{ 0x41710530 , 0xc0200284 },
+	{ 0x41710534 , 0x54812106 },
+	{ 0x41710538 , 0xc0c012d0 },
+	{ 0x4171053c , 0x4c01c006 },
+	{ 0x41710540 , 0xc0004284 },
+	{ 0x41710544 , 0xc0801080 },
+	{ 0x41710548 , 0x20805282 },
+	{ 0x41710550 , 0x83c012d0 },
+	{ 0x41710560 , 0x47610b0 },
+	{ 0x41710564 , 0xb871ac },
+	{ 0x41710568 , 0x806080 },
+	{ 0x4171056c , 0x400a0b0 },
+	{ 0x41710570 , 0x801380 },
+	{ 0x41710574 , 0x84e540b0 },
+	{ 0x41710578 , 0x400b0b0 },
+	{ 0x4171057c , 0x810a4b0 },
+	{ 0x41710580 , 0x40870b0 },
+	{ 0x41710584 , 0x40018b1 },
+	{ 0x41710588 , 0x40050b0 },
+	{ 0x4171058c , 0xe080 },
+	{ 0x41710590 , 0xe18b0a8 },
+	{ 0x41710594 , 0x682ca2a8 },
+	{ 0x41710598 , 0x80f384 },
+	{ 0x4171059c , 0x2200023c },
+	{ 0x417105a0 , 0x65b8026 },
+	{ 0x417105a4 , 0x840370b0 },
+	{ 0x417105a8 , 0x41a103cc },
+	{ 0x417105b0 , 0x22007238 },
+	{ 0x417105b4 , 0x1a80230a },
+	{ 0x417105b8 , 0x4bc680a },
+	{ 0x417105bc , 0x20b803ad },
+	{ 0x417105c0 , 0x78014006 },
+	{ 0x417105c4 , 0x4058a8 },
+	{ 0x417105c8 , 0x400d0b0 },
+	{ 0x417105cc , 0x400c0b0 },
+	{ 0x417105d0 , 0x840370b0 },
+	{ 0x417105d4 , 0xb8d8a8 },
+	{ 0x417105d8 , 0x1038d8a8 },
+	{ 0x417105dc , 0x84a103cc },
+	{ 0x417105e0 , 0xe0a10084 },
+	{ 0x417105e4 , 0x82816106 },
+	{ 0x417105e8 , 0x101c07a9 },
+	{ 0x417105ec , 0xe04168d4 },
+	{ 0x417105f0 , 0xe0811084 },
+	{ 0x417105f4 , 0xe0016380 },
+	{ 0x417105f8 , 0x6701c006 },
+	{ 0x417105fc , 0x1881 },
+	{ 0x41710600 , 0x400e0b0 },
+	{ 0x41710604 , 0x408f0b0 },
+	{ 0x41710608 , 0x334068d4 },
+	{ 0x41710618 , 0x1881 },
+	{ 0x4171061c , 0x22001238 },
+	{ 0x41710620 , 0x880e00a },
+	{ 0x41710624 , 0x130430a8 },
+	{ 0x41710628 , 0xc052a9 },
+	{ 0x4171062c , 0xcc48a9 },
+	{ 0x41710630 , 0x2801430 },
+	{ 0x41710634 , 0x874d8026 },
+	{ 0x41710638 , 0x41c040cd },
+	{ 0x4171063c , 0x2200043c },
+	{ 0x41710640 , 0x4bc080a },
+	{ 0x41710644 , 0x8004007 },
+	{ 0x41710648 , 0x40220b0 },
+	{ 0x41710650 , 0x874d4026 },
+	{ 0x41710654 , 0x2200043c },
+	{ 0x4080004c , 0x4 },
+	{ 0x40800040 , 0x800000 },
+	{ 0x40800044 , 0x820 },
+	{ 0x41718000 , 0x30010000 },
+	{ 0x41718024 , 0x10 },
+	{ 0x41718028 , 0x12000000 },
+	{ 0x4171802c , 0x0 },
+	{ 0x41718040 , 0x40010000 },
+	{ 0x41718044 , 0x0 },
+	{ 0x41718048 , 0xf0000000 },
+	{ 0x41718080 , 0xd8040000 },
+	{ 0x417180a0 , 0x600d0000 },
+	{ 0x417180a4 , 0x7c0d0000 },
+	{ 0x21700dfc , 0xf000 },
+	{ 0x1170123e , 0x0 },
+	{ 0x11701242 , 0x8 },
+	{ 0x11701246 , 0x10 },
+	{ 0x1170124a , 0x18 },
+	{ 0x1170124e , 0x20 },
+	{ 0x11701252 , 0x28 },
+	{ 0x11701256 , 0x30 },
+	{ 0x1170125a , 0x38 },
+	{ 0x40800000 , 0x1027000 },
+	{ 0x40801000 , 0x1027000 },
+	{ 0x40808500 , 0xd8000420 },
+	{ 0x40808840 , 0x8 },
+	{ 0x40808844 , 0x8 },
+	{ 0x40808848 , 0x8 },
+	{ 0x4080884c , 0x8 },
+	{ 0x40898020 , 0x404 },
+	{ 0x40898004 , 0x0 },
+	{ 0x40898024 , 0x10101040 },
+	{ 0x40898028 , 0x3fff05ee },
+	{ 0x40898024 , 0x10104040 },
+	{ 0x40898028 , 0x5ee05ee },
+	{ 0x40898024 , 0x10404040 },
+	{ 0x4089802c , 0x3fff05ee },
+	{ 0x40898024 , 0x40404040 },
+	{ 0x4089802c , 0x5ee05ee },
+	{ 0x40898030 , 0x0 },
+	{ 0x40898044 , 0xff },
+	{ 0x40898034 , 0x0 },
+	{ 0x40898420 , 0x404 },
+	{ 0x40898404 , 0x101 },
+	{ 0x40898424 , 0x10101040 },
+	{ 0x40898428 , 0x3fff05ee },
+	{ 0x40898424 , 0x10104040 },
+	{ 0x40898428 , 0x5ee05ee },
+	{ 0x40898424 , 0x10404040 },
+	{ 0x4089842c , 0x3fff05ee },
+	{ 0x40898424 , 0x40404040 },
+	{ 0x4089842c , 0x5ee05ee },
+	{ 0x40898430 , 0x0 },
+	{ 0x40898444 , 0xff },
+	{ 0x40898434 , 0x0 },
+	{ 0x40898820 , 0x404 },
+	{ 0x40898804 , 0x202 },
+	{ 0x40898824 , 0x10101040 },
+	{ 0x40898828 , 0x3fff05ee },
+	{ 0x40898824 , 0x10104040 },
+	{ 0x40898828 , 0x5ee05ee },
+	{ 0x40898824 , 0x10404040 },
+	{ 0x4089882c , 0x3fff05ee },
+	{ 0x40898824 , 0x40404040 },
+	{ 0x4089882c , 0x5ee05ee },
+	{ 0x40898830 , 0x0 },
+	{ 0x40898844 , 0xff },
+	{ 0x40898834 , 0x0 },
+	{ 0x40898c20 , 0x404 },
+	{ 0x40898c04 , 0x303 },
+	{ 0x40898c24 , 0x10101040 },
+	{ 0x40898c28 , 0x3fff05ee },
+	{ 0x40898c24 , 0x10104040 },
+	{ 0x40898c28 , 0x5ee05ee },
+	{ 0x40898c24 , 0x10404040 },
+	{ 0x40898c2c , 0x3fff05ee },
+	{ 0x40898c24 , 0x40404040 },
+	{ 0x40898c2c , 0x5ee05ee },
+	{ 0x40898c30 , 0x0 },
+	{ 0x40898c44 , 0xff },
+	{ 0x40898c34 , 0x0 },
+	{ 0x40899020 , 0x404 },
+	{ 0x40899004 , 0x404 },
+	{ 0x40899024 , 0x10101040 },
+	{ 0x40899028 , 0x3fff05ee },
+	{ 0x40899024 , 0x10104040 },
+	{ 0x40899028 , 0x5ee05ee },
+	{ 0x40899024 , 0x10404040 },
+	{ 0x4089902c , 0x3fff05ee },
+	{ 0x40899024 , 0x40404040 },
+	{ 0x4089902c , 0x5ee05ee },
+	{ 0x40899030 , 0x0 },
+	{ 0x40899044 , 0xff },
+	{ 0x40899034 , 0x0 },
+	{ 0x40899420 , 0xc0c },
+	{ 0x40899404 , 0x505 },
+	{ 0x40899424 , 0x10101040 },
+	{ 0x40899428 , 0x3fff05ee },
+	{ 0x40899424 , 0x10104040 },
+	{ 0x40899428 , 0x5ee05ee },
+	{ 0x40899424 , 0x10404040 },
+	{ 0x4089942c , 0x3fff05ee },
+	{ 0x40899424 , 0x40404040 },
+	{ 0x4089942c , 0x5ee05ee },
+	{ 0x40899430 , 0x0 },
+	{ 0x40899444 , 0xff },
+	{ 0x40899434 , 0x0 },
+	{ 0x40899820 , 0x1010 },
+	{ 0x40899804 , 0x606 },
+	{ 0x40899824 , 0x10101040 },
+	{ 0x40899828 , 0x3fff05ee },
+	{ 0x40899824 , 0x10104040 },
+	{ 0x40899828 , 0x5ee05ee },
+	{ 0x40899824 , 0x10404040 },
+	{ 0x4089982c , 0x3fff05ee },
+	{ 0x40899824 , 0x40404040 },
+	{ 0x4089982c , 0x5ee05ee },
+	{ 0x40899830 , 0x0 },
+	{ 0x40899844 , 0xff },
+	{ 0x40899834 , 0x0 },
+	{ 0x40899c20 , 0xc0c },
+	{ 0x40899c04 , 0x707 },
+	{ 0x40899c24 , 0x10101040 },
+	{ 0x40899c28 , 0x3fff05ee },
+	{ 0x40899c24 , 0x10104040 },
+	{ 0x40899c28 , 0x5ee05ee },
+	{ 0x40899c24 , 0x10404040 },
+	{ 0x40899c2c , 0x3fff05ee },
+	{ 0x40899c24 , 0x40404040 },
+	{ 0x40899c2c , 0x5ee05ee },
+	{ 0x40899c30 , 0x0 },
+	{ 0x40899c44 , 0xff },
+	{ 0x40899c34 , 0x0 },
+	{ 0x40890024 , 0x100410 },
+	{ 0x4089000c , 0x20200000 },
+	{ 0x40890010 , 0x0 },
+	{ 0x40890018 , 0x101d0 },
+	{ 0x408900a0 , 0x0 },
+	{ 0x40890400 , 0x0 },
+	{ 0x40890450 , 0x0 },
+	{ 0x408904b0 , 0x0 },
+	{ 0x408904a0 , 0x70007 },
+	{ 0x408904a4 , 0x0 },
+	{ 0x408904a8 , 0x0 },
+	{ 0x40890908 , 0x1000000 },
+	{ 0x40890920 , 0x1400000 },
+	{ 0x40890940 , 0x13f013f },
+	{ 0x40890960 , 0x280000 },
+	{ 0x40890980 , 0x270027 },
+	{ 0x408900bc , 0x3 },
+	{ 0x408907a0 , 0x70007 },
+	{ 0x408907a4 , 0x0 },
+	{ 0x408907a8 , 0xfff0fff },
+	{ 0x40890908 , 0x1000001 },
+	{ 0x40890924 , 0x3c00280 },
+	{ 0x40890944 , 0x13f013f },
+	{ 0x40890964 , 0x780050 },
+	{ 0x40890984 , 0x270027 },
+	{ 0x40890908 , 0x1000002 },
+	{ 0x40890928 , 0x6400500 },
+	{ 0x40890948 , 0x13f013f },
+	{ 0x40890968 , 0xc800a0 },
+	{ 0x40890988 , 0x270027 },
+	{ 0x408907b8 , 0x2 },
+	{ 0x40890908 , 0x1000003 },
+	{ 0x4089092c , 0x0 },
+	{ 0x4089094c , 0x13f013f },
+	{ 0x4089096c , 0x0 },
+	{ 0x4089098c , 0x270027 },
+	{ 0x40890600 , 0x0 },
+	{ 0x40890604 , 0x1 },
+	{ 0x4089090c , 0x3f },
+	{ 0x4089003c , 0x52047c5e },
+	{ 0x408a1000 , 0x5fc000 },
+	{ 0x408a1050 , 0x14015f },
+	{ 0x408a118c , 0x60000001 },
+	{ 0x408a1864 , 0x44 },
+	{ 0x408a1868 , 0x4 },
+	{ 0x408a186c , 0x4 },
+	{ 0x408a1870 , 0x4 },
+	{ 0x408a1854 , 0x406 },
+	{ 0x408a1874 , 0x4 },
+	{ 0x408a1878 , 0x0 },
+	{ 0x408a18b8 , 0x0 },
+	{ 0x408a187c , 0x0 },
+	{ 0x408a18bc , 0x0 },
+	{ 0x408a18f4 , 0x30c0a },
+	{ 0x408a18f4 , 0xc0a },
+	{ 0x408a1c40 , 0x203 },
+	{ 0x408a1c04 , 0xc },
+	{ 0x408a1c44 , 0x406 },
+	{ 0x408a1c64 , 0x44 },
+	{ 0x408a1c68 , 0x0 },
+	{ 0x408a1c6c , 0x0 },
+	{ 0x408a1c70 , 0x0 },
+	{ 0x408a1c74 , 0x0 },
+	{ 0x408a1c78 , 0x0 },
+	{ 0x408a1c7c , 0x0 },
+	{ 0x408a1cf4 , 0x30c0a },
+	{ 0x408a1cf4 , 0xc0a },
+	{ 0x408a2000 , 0x10 },
+	{ 0x408a2060 , 0x80 },
+	{ 0x408a2064 , 0x40 },
+	{ 0x408a2068 , 0x0 },
+	{ 0x408a206c , 0x0 },
+	{ 0x408a2070 , 0x0 },
+	{ 0x408a2074 , 0x0 },
+	{ 0x408a2078 , 0x0 },
+	{ 0x408a207c , 0x0 },
+	{ 0x408a20f4 , 0x30c01 },
+	{ 0x408a20f4 , 0xc01 },
+	{ 0x3000000 , 0x20 },
+	{ 0x82880080 , 0xfff00f3f },
+	{ 0x3000000 , 0x20 },
+	{ 0x82880100 , 0xfff00f3f },
+	{ 0x40880180 , 0x7f1ff1ff },
+	{ 0x40880184 , 0xa0c80a8 },
+	{ 0x7000000 , 0x1ff },
+	{ 0x82883000 , 0x40004 },
+	{ 0x4088270c , 0x1ff },
+	{ 0x40882714 , 0x200 },
+	{ 0x40882708 , 0x200 },
+	{ 0x40880080 , 0x7f1ff1ff },
+	{ 0x40880100 , 0x7f1ff1ff },
+	{ 0x40880400 , 0x2001f },
+	{ 0x40880620 , 0x1 },
+	{ 0x40880300 , 0x41b1 },
+	{ 0x40880380 , 0x400 },
+	{ 0x40882700 , 0x1 },
+	{ 0x40882704 , 0x1 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880084 , 0x7f1ff1ff },
+	{ 0x40880104 , 0x7f1ff1ff },
+	{ 0x40880404 , 0x20021 },
+	{ 0x40880620 , 0x3 },
+	{ 0x40880304 , 0x41b1 },
+	{ 0x40880384 , 0x400 },
+	{ 0x40882020 , 0x1 },
+	{ 0x4088202c , 0x1 },
+	{ 0x40882700 , 0x2 },
+	{ 0x40882704 , 0x2 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880088 , 0x7f1ff1ff },
+	{ 0x40880108 , 0x7f1ff1ff },
+	{ 0x40880408 , 0x20023 },
+	{ 0x40880620 , 0x7 },
+	{ 0x40880308 , 0x41b1 },
+	{ 0x40880388 , 0x400 },
+	{ 0x40882040 , 0x2 },
+	{ 0x4088204c , 0x2 },
+	{ 0x40882700 , 0x3 },
+	{ 0x40882704 , 0x3 },
+	{ 0x40880990 , 0x1f },
+	{ 0x4088008c , 0x7f1ff1ff },
+	{ 0x4088010c , 0x7f1ff1ff },
+	{ 0x4088040c , 0x20025 },
+	{ 0x40880620 , 0xf },
+	{ 0x4088030c , 0x41b1 },
+	{ 0x4088038c , 0x400 },
+	{ 0x40882060 , 0x3 },
+	{ 0x4088206c , 0x3 },
+	{ 0x40882700 , 0x4 },
+	{ 0x40882704 , 0x4 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880090 , 0x7f1ff1ff },
+	{ 0x40880110 , 0x7f1ff1ff },
+	{ 0x40880410 , 0x20027 },
+	{ 0x40880620 , 0x1f },
+	{ 0x40880310 , 0x41b1 },
+	{ 0x40880390 , 0x400 },
+	{ 0x40882080 , 0x4 },
+	{ 0x4088208c , 0x4 },
+	{ 0x40882700 , 0x5 },
+	{ 0x40882704 , 0x5 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880094 , 0x7f1ff1ff },
+	{ 0x40880114 , 0x7f1ff1ff },
+	{ 0x40880414 , 0x20029 },
+	{ 0x40880620 , 0x3f },
+	{ 0x40880314 , 0x41b1 },
+	{ 0x40880394 , 0x400 },
+	{ 0x408820a0 , 0x5 },
+	{ 0x408820ac , 0x5 },
+	{ 0x40882700 , 0x6 },
+	{ 0x40882704 , 0x6 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880098 , 0x7f1ff1ff },
+	{ 0x40880118 , 0x7f1ff1ff },
+	{ 0x40880418 , 0x2002b },
+	{ 0x40880620 , 0x7f },
+	{ 0x40880318 , 0x41b1 },
+	{ 0x40880398 , 0x400 },
+	{ 0x408820c0 , 0x6 },
+	{ 0x408820cc , 0x6 },
+	{ 0x40882700 , 0x7 },
+	{ 0x40882704 , 0x7 },
+	{ 0x40880990 , 0x1f },
+	{ 0x4088009c , 0x7f1ff1ff },
+	{ 0x4088011c , 0x7f1ff1ff },
+	{ 0x4088041c , 0x2002d },
+	{ 0x40880620 , 0xff },
+	{ 0x4088031c , 0x41b1 },
+	{ 0x4088039c , 0x400 },
+	{ 0x408820e0 , 0x7 },
+	{ 0x408820ec , 0x7 },
+	{ 0x40882700 , 0x8 },
+	{ 0x40882704 , 0x8 },
+	{ 0x40880990 , 0x1f },
+	{ 0x408800a0 , 0x0 },
+	{ 0x40880120 , 0x0 },
+	{ 0x40880624 , 0x100 },
+	{ 0x40882100 , 0x8 },
+	{ 0x4088210c , 0x8 },
+	{ 0x40882700 , 0x9 },
+	{ 0x40882704 , 0x9 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880520 , 0x1 },
+	{ 0x40880604 , 0x7f },
+	{ 0x40880900 , 0x1 },
+	{ 0x40880480 , 0x28 },
+	{ 0x408804d0 , 0x1e3 },
+	{ 0x408804d8 , 0x1d },
+	{ 0x408804d4 , 0x1e3 },
+	{ 0x408804dc , 0x1d },
+	{ 0x40880980 , 0x100 },
+	{ 0x40880004 , 0xff },
+	{ 0x40880850 , 0x201 },
+	{ 0x4089803c , 0x3 },
+	{ 0x4089843c , 0x3 },
+	{ 0x4089883c , 0x3 },
+	{ 0x40898c3c , 0x3 },
+	{ 0x4089903c , 0x3 },
+	{ 0x4089943c , 0x3 },
+	{ 0x4089983c , 0x3 },
+	{ 0x40899c3c , 0x3 },
+	{ 0x40880000 , 0x11 },
+	{ 0x40c00000 , 0x307 },
+	{ 0x4089c000 , 0x1 },
+	{ 0x4089d000 , 0x1 },
+	{ 0x40800000 , 0x1027001 },
+	{ 0x1170123e , 0x0 },
+	{ 0x11701242 , 0x8 },
+	{ 0x11701246 , 0x10 },
+	{ 0x1170124a , 0x18 },
+	{ 0x1170124e , 0x20 },
+	{ 0x11701252 , 0x28 },
+	{ 0x11701256 , 0x30 },
+	{ 0x1170125a , 0x38 },
+	{ 0x1170125e , 0x40 },
+    { (ACCESS_LOG_OP_STOP << 24), 0 }
+};
diff --git a/drivers/net/bcmbca/xrdp/data_path_63146.c b/drivers/net/bcmbca/xrdp/data_path_63146.c
new file mode 100644
index 0000000000..ef72f27e42
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/data_path_63146.c
@@ -0,0 +1,786 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include "access_logging.h"
+
+const access_log_tuple_t init_data[] = {
+	{ 0x408a0014 , 0x82a00000 },
+	{ 0x408a0018 , 0x82c00000 },
+	{ 0x408a001c , 0x82c00000 },
+	{ 0x408a0020 , 0x82c80000 },
+	{ 0x408a0024 , 0x82c80000 },
+	{ 0x408a0028 , 0x82d00000 },
+	{ 0x408a0004 , 0x82700000 },
+	{ 0x408a0008 , 0x82900000 },
+	{ 0x408a000c , 0x82900000 },
+	{ 0x408a0010 , 0x82a00000 },
+	{ 0x4089c008 , 0x20002 },
+	{ 0x4089d008 , 0x20002 },
+	{ 0x5700000 , 0x0 },
+	{ 0x40800030 , 0x3000d },
+	{ 0x4000000 , 0x5 },
+	{ 0x3000000 , 0x2000 },
+	{ 0x82710000 , 0xfc000000 },
+	{ 0x41710000 , 0x6008006 },
+	{ 0x4171000c , 0x19008006 },
+	{ 0x41710018 , 0x26 },
+	{ 0x41710020 , 0x6f80a0a },
+	{ 0x41710024 , 0xc43aac },
+	{ 0x41710028 , 0x40020b0 },
+	{ 0x4171002c , 0x21008004 },
+	{ 0x41710030 , 0x740110b0 },
+	{ 0x41710034 , 0x638000cc },
+	{ 0x41710038 , 0xb83aac },
+	{ 0x4171003c , 0xf4ff73b0 },
+	{ 0x41710040 , 0xe0a00184 },
+	{ 0x41710044 , 0x18800006 },
+	{ 0x41710048 , 0xe1831a8 },
+	{ 0x4171004c , 0x2100c004 },
+	{ 0x41710050 , 0x840370b0 },
+	{ 0x41710054 , 0x40020b0 },
+	{ 0x41710058 , 0x46a003cc },
+	{ 0x41710060 , 0x21000004 },
+	{ 0x41710064 , 0x2ec0036 },
+	{ 0x41710068 , 0x42ec1036 },
+	{ 0x4171006c , 0x83ec2036 },
+	{ 0x41710070 , 0x3ed4036 },
+	{ 0x41710074 , 0x83ed6036 },
+	{ 0x41710078 , 0x3ee8036 },
+	{ 0x4171007c , 0x83eea036 },
+	{ 0x41710080 , 0x3efc036 },
+	{ 0x41710084 , 0x83efe036 },
+	{ 0x41710088 , 0x3f00037 },
+	{ 0x4171008c , 0x83f02037 },
+	{ 0x41710090 , 0x3f14037 },
+	{ 0x41710094 , 0x83f16037 },
+	{ 0x41710098 , 0x3f28037 },
+	{ 0x4171009c , 0x83f2a037 },
+	{ 0x417100a0 , 0x3f3c037 },
+	{ 0x417100a4 , 0x83f3e037 },
+	{ 0x417100a8 , 0x820010c6 },
+	{ 0x417100ac , 0x9610ac },
+	{ 0x417100b0 , 0xc2dd1036 },
+	{ 0x417100b4 , 0x2e602002 },
+	{ 0x417100b8 , 0x2f602002 },
+	{ 0x417100bc , 0x30602002 },
+	{ 0x417100c0 , 0xc2 },
+	{ 0x417100c4 , 0x32602002 },
+	{ 0x417100c8 , 0x33602002 },
+	{ 0x417100cc , 0x34602002 },
+	{ 0x417100d0 , 0x2ec0032 },
+	{ 0x417100d4 , 0x42ec1032 },
+	{ 0x417100d8 , 0x83ec2032 },
+	{ 0x417100dc , 0x3ed4032 },
+	{ 0x417100e0 , 0x83ed6032 },
+	{ 0x417100e4 , 0x3ee8032 },
+	{ 0x417100e8 , 0x83eea032 },
+	{ 0x417100ec , 0x3efc032 },
+	{ 0x417100f0 , 0x83efe032 },
+	{ 0x417100f4 , 0x3f00033 },
+	{ 0x417100f8 , 0x83f02033 },
+	{ 0x417100fc , 0x3f14033 },
+	{ 0x41710100 , 0x83f16033 },
+	{ 0x41710104 , 0x3f28033 },
+	{ 0x41710108 , 0x83f2a033 },
+	{ 0x4171010c , 0x3f3c033 },
+	{ 0x41710110 , 0x83f3e033 },
+	{ 0x41710120 , 0x1008022 },
+	{ 0x41710130 , 0x440030b0 },
+	{ 0x41710134 , 0x4d820b0 },
+	{ 0x41710138 , 0x81319e },
+	{ 0x4171013c , 0x60003180 },
+	{ 0x41710140 , 0x140040b0 },
+	{ 0x41710144 , 0x2802130 },
+	{ 0x41710148 , 0x80002180 },
+	{ 0x4171014c , 0x2802134 },
+	{ 0x41710150 , 0x22802138 },
+	{ 0x41710154 , 0x80002182 },
+	{ 0x41710158 , 0x2280213c },
+	{ 0x4171015c , 0x43004839 },
+	{ 0x41710160 , 0x300e830 },
+	{ 0x41710164 , 0xcd7cca0a },
+	{ 0x41710168 , 0x60262aac },
+	{ 0x4171016c , 0xc0aa57ac },
+	{ 0x41710170 , 0x20006196 },
+	{ 0x41710174 , 0x40030b0 },
+	{ 0x41710178 , 0x4d820b0 },
+	{ 0x4171017c , 0x81319e },
+	{ 0x41710180 , 0x60002180 },
+	{ 0x41710184 , 0x2003130 },
+	{ 0x41710188 , 0x80803180 },
+	{ 0x4171018c , 0xb887ac },
+	{ 0x41710190 , 0x2003134 },
+	{ 0x41710194 , 0x22003138 },
+	{ 0x41710198 , 0x813180 },
+	{ 0x4171019c , 0x80803182 },
+	{ 0x417101a0 , 0x2200313c },
+	{ 0x417101a4 , 0xc1c03431 },
+	{ 0x417101a8 , 0x400e0b0 },
+	{ 0x417101ac , 0x40070b0 },
+	{ 0x417101b0 , 0x6481 },
+	{ 0x417101b4 , 0x40020b0 },
+	{ 0x417101b8 , 0x40030b0 },
+	{ 0x417101bc , 0x40060b0 },
+	{ 0x417101c0 , 0xc1df7033 },
+	{ 0x417101c4 , 0x40a20b84 },
+	{ 0x417101c8 , 0x90809006 },
+	{ 0x417101cc , 0x41080b0 },
+	{ 0x417101d0 , 0x4200093c },
+	{ 0x417101d4 , 0x22983 },
+	{ 0x417101d8 , 0x8012989 },
+	{ 0x417101dc , 0x300c930 },
+	{ 0x417101e0 , 0x40b8d6ac },
+	{ 0x417101e4 , 0xa00684 },
+	{ 0x417101e8 , 0x8c80c006 },
+	{ 0x417101ec , 0x2080d686 },
+	{ 0x417101f0 , 0xe180d696 },
+	{ 0x417101f4 , 0x2080d682 },
+	{ 0x417101f8 , 0xa001d294 },
+	{ 0x417101fc , 0x20808687 },
+	{ 0x41710200 , 0xc20d8b0 },
+	{ 0x41710204 , 0xdcb0 },
+	{ 0x41710208 , 0xa001c684 },
+	{ 0x4171020c , 0xe014d6ac },
+	{ 0x41710210 , 0xa0018c95 },
+	{ 0x41710214 , 0x8009c6ac },
+	{ 0x41710218 , 0x4dfd0b0 },
+	{ 0x4171021c , 0x4000c696 },
+	{ 0x41710220 , 0x8081c680 },
+	{ 0x41710224 , 0x200d630 },
+	{ 0x41710228 , 0x883d688 },
+	{ 0x4171022c , 0x200d634 },
+	{ 0x41710230 , 0x40a20b84 },
+	{ 0x41710234 , 0x7580a006 },
+	{ 0x41710238 , 0x4200093c },
+	{ 0x4171023c , 0x3000934 },
+	{ 0x41710240 , 0x200b84 },
+	{ 0x41710244 , 0xfc80d006 },
+	{ 0x41710248 , 0xb8c7ac },
+	{ 0x4171024c , 0x20008686 },
+	{ 0x41710250 , 0xe1008496 },
+	{ 0x41710254 , 0x2000c482 },
+	{ 0x41710258 , 0x4df90b1 },
+	{ 0x4171025c , 0x400d0b0 },
+	{ 0x41710260 , 0x280ac31 },
+	{ 0x41710264 , 0x40080b0 },
+	{ 0x41710268 , 0x2017da1 },
+	{ 0x4171026c , 0x818b85 },
+	{ 0x41710270 , 0x80210c84 },
+	{ 0x41710274 , 0xaa003106 },
+	{ 0x41710278 , 0x20808b82 },
+	{ 0x4171027c , 0x240486 },
+	{ 0x41710280 , 0x9a009106 },
+	{ 0x41710284 , 0xe0027295 },
+	{ 0x41710288 , 0xe802ad89 },
+	{ 0x4171028c , 0x2080d682 },
+	{ 0x41710290 , 0xf48b7617 },
+	{ 0x41710294 , 0x80809c83 },
+	{ 0x41710298 , 0x61c8026 },
+	{ 0x4171029c , 0x240080b0 },
+	{ 0x417102a0 , 0x22e04c2 },
+	{ 0x417102a8 , 0x80012294 },
+	{ 0x417102ac , 0x20002186 },
+	{ 0x417102b0 , 0x2803c30 },
+	{ 0x417102b4 , 0x12194 },
+	{ 0x417102b8 , 0x40802180 },
+	{ 0x417102bc , 0x2802c34 },
+	{ 0x417102c0 , 0x41660b0 },
+	{ 0x417102c4 , 0xc03aac },
+	{ 0x417102c8 , 0xb8c7ac },
+	{ 0x417102cc , 0x40820b0 },
+	{ 0x417102d0 , 0x4e570b0 },
+	{ 0x417102d4 , 0x40090b1 },
+	{ 0x417102d8 , 0x6381 },
+	{ 0x417102dc , 0x101c30a8 },
+	{ 0x417102e0 , 0x3681 },
+	{ 0x417102e4 , 0x7185 },
+	{ 0x417102e8 , 0xe0a20984 },
+	{ 0x417102ec , 0xcc802106 },
+	{ 0x417102f0 , 0xe0c261d1 },
+	{ 0x417102f4 , 0x22032080 },
+	{ 0x417102f8 , 0x101c30a8 },
+	{ 0x417102fc , 0x68ac23a8 },
+	{ 0x41710300 , 0xe0823985 },
+	{ 0x41710304 , 0x840380b1 },
+	{ 0x41710308 , 0xe0026b81 },
+	{ 0x4171030c , 0x2280318e },
+	{ 0x41710310 , 0x1e0422a8 },
+	{ 0x41710314 , 0x6328026 },
+	{ 0x41710318 , 0x40870b1 },
+	{ 0x4171031c , 0x40200ccc },
+	{ 0x41710320 , 0xba008006 },
+	{ 0x41710324 , 0x31802338 },
+	{ 0x41710328 , 0x203831ac },
+	{ 0x41710330 , 0x63c261d1 },
+	{ 0x41710340 , 0xe008007 },
+	{ 0x41710344 , 0xf40120b0 },
+	{ 0x41710350 , 0xa0802696 },
+	{ 0x41710354 , 0x41830b0 },
+	{ 0x41710358 , 0x12180 },
+	{ 0x4171035c , 0x60003180 },
+	{ 0x41710360 , 0x1660b0 },
+	{ 0x41710364 , 0x7680 },
+	{ 0x41710368 , 0x40820b0 },
+	{ 0x4171036c , 0x40a00384 },
+	{ 0x41710370 , 0xe2802106 },
+	{ 0x41710374 , 0x40c061d4 },
+	{ 0x41710378 , 0xdb00c006 },
+	{ 0x4171037c , 0x40807384 },
+	{ 0x41710380 , 0x40006380 },
+	{ 0x41710384 , 0x20803182 },
+	{ 0x41710388 , 0xf3c061d4 },
+	{ 0x41710398 , 0xc2038b0 },
+	{ 0x4171039c , 0xe0002496 },
+	{ 0x417103a0 , 0x3cb0 },
+	{ 0x417103a4 , 0xc8826a8 },
+	{ 0x417103a8 , 0x60008180 },
+	{ 0x417103ac , 0x60266aac },
+	{ 0x417103b0 , 0x40020b0 },
+	{ 0x417103b4 , 0x20006396 },
+	{ 0x417103b8 , 0x40030b0 },
+	{ 0x417103bc , 0xc1c03431 },
+	{ 0x417103c0 , 0x40070b0 },
+	{ 0x417103c4 , 0x6a0a4a8 },
+	{ 0x417103c8 , 0x1f0422a8 },
+	{ 0x417103cc , 0x61c20a8 },
+	{ 0x417103d0 , 0x1f0430a8 },
+	{ 0x417103d4 , 0x7a4e5a8 },
+	{ 0x417103d8 , 0x6480 },
+	{ 0x417103dc , 0x2b877a8 },
+	{ 0x417103e0 , 0x6a8a2a8 },
+	{ 0x417103e4 , 0x799529a8 },
+	{ 0x417103e8 , 0x1820a8 },
+	{ 0x417103ec , 0x1d0430a8 },
+	{ 0x417103f0 , 0x40a20884 },
+	{ 0x417103f4 , 0x16811006 },
+	{ 0x417103f8 , 0x380683c },
+	{ 0x417103fc , 0x4380283c },
+	{ 0x41710400 , 0x41020b0 },
+	{ 0x41710404 , 0x821883 },
+	{ 0x41710408 , 0x140030b0 },
+	{ 0x4171040c , 0x48801889 },
+	{ 0x41710410 , 0x81319e },
+	{ 0x41710414 , 0x4d820b0 },
+	{ 0x41710418 , 0x60002180 },
+	{ 0x4171041c , 0x2003130 },
+	{ 0x41710420 , 0x80803180 },
+	{ 0x41710424 , 0x2003134 },
+	{ 0x41710428 , 0x22003138 },
+	{ 0x4171042c , 0x80813180 },
+	{ 0x41710430 , 0x80803182 },
+	{ 0x41710434 , 0x2200313c },
+	{ 0x41710438 , 0x6a0a4a8 },
+	{ 0x4171043c , 0x90005cc },
+	{ 0x41710440 , 0x1f0442a9 },
+	{ 0x41710444 , 0x779d59a9 },
+	{ 0x41710448 , 0x7138026 },
+	{ 0x4171044c , 0x6a8a2a8 },
+	{ 0x41710450 , 0xc84145cd },
+	{ 0x41710458 , 0x3400d0b0 },
+	{ 0x4171045c , 0x4d880b0 },
+	{ 0x41710460 , 0x81d69e },
+	{ 0x41710464 , 0xa0018480 },
+	{ 0x41710468 , 0x200d430 },
+	{ 0x4171046c , 0x8080d680 },
+	{ 0x41710470 , 0x200d434 },
+	{ 0x41710474 , 0x2200d438 },
+	{ 0x41710478 , 0x8081c680 },
+	{ 0x4171047c , 0x8000c682 },
+	{ 0x41710480 , 0x2200c43c },
+	{ 0x41710484 , 0x240080b0 },
+	{ 0x41710488 , 0x61c8026 },
+	{ 0x4171048c , 0x40060b1 },
+	{ 0x41710490 , 0x22e04c2 },
+	{ 0x41710498 , 0x240030b0 },
+	{ 0x4171049c , 0x4d820b0 },
+	{ 0x417104a0 , 0x81319e },
+	{ 0x417104a4 , 0x60002180 },
+	{ 0x417104a8 , 0x2003130 },
+	{ 0x417104ac , 0xc1c03431 },
+	{ 0x417104b0 , 0x80803180 },
+	{ 0x417104b4 , 0x2003134 },
+	{ 0x417104b8 , 0x22003138 },
+	{ 0x417104bc , 0x80803182 },
+	{ 0x417104c0 , 0xe008007 },
+	{ 0x417104c4 , 0x2200313c },
+	{ 0x417104c8 , 0x240120b0 },
+	{ 0x417104d0 , 0xe010006 },
+	{ 0x417104d8 , 0x40010b0 },
+	{ 0x417104dc , 0x4e020b0 },
+	{ 0x417104e0 , 0x81109e },
+	{ 0x417104e4 , 0x20001180 },
+	{ 0x417104e8 , 0x140040b0 },
+	{ 0x417104ec , 0x2802030 },
+	{ 0x417104f0 , 0x80002180 },
+	{ 0x417104f4 , 0x2802034 },
+	{ 0x417104f8 , 0x22802038 },
+	{ 0x417104fc , 0x80002182 },
+	{ 0x41710500 , 0x2280203c },
+	{ 0x41710504 , 0x3002430 },
+	{ 0x41710508 , 0x6cc510a },
+	{ 0x4171050c , 0x43004439 },
+	{ 0x41710510 , 0x2801430 },
+	{ 0x41710514 , 0x874d8026 },
+	{ 0x41710518 , 0x41c040cd },
+	{ 0x4171051c , 0x2200043c },
+	{ 0x41710520 , 0x47610b0 },
+	{ 0x41710524 , 0x41e50b0 },
+	{ 0x41710528 , 0xb841ac },
+	{ 0x4171052c , 0x40860b0 },
+	{ 0x41710530 , 0xc0200284 },
+	{ 0x41710534 , 0x54812106 },
+	{ 0x41710538 , 0xc0c012d0 },
+	{ 0x4171053c , 0x4c01c006 },
+	{ 0x41710540 , 0xc0004284 },
+	{ 0x41710544 , 0xc0801080 },
+	{ 0x41710548 , 0x20805282 },
+	{ 0x41710550 , 0x83c012d0 },
+	{ 0x41710560 , 0x47610b0 },
+	{ 0x41710564 , 0xb871ac },
+	{ 0x41710568 , 0x806080 },
+	{ 0x4171056c , 0x400a0b0 },
+	{ 0x41710570 , 0x801380 },
+	{ 0x41710574 , 0x84e540b0 },
+	{ 0x41710578 , 0x400b0b0 },
+	{ 0x4171057c , 0x810a4b0 },
+	{ 0x41710580 , 0x40870b0 },
+	{ 0x41710584 , 0x40018b1 },
+	{ 0x41710588 , 0x40050b0 },
+	{ 0x4171058c , 0xe080 },
+	{ 0x41710590 , 0xe18b0a8 },
+	{ 0x41710594 , 0x682ca2a8 },
+	{ 0x41710598 , 0x80f384 },
+	{ 0x4171059c , 0x2200023c },
+	{ 0x417105a0 , 0x65b8026 },
+	{ 0x417105a4 , 0x840370b0 },
+	{ 0x417105a8 , 0x41a103cc },
+	{ 0x417105b0 , 0x22007238 },
+	{ 0x417105b4 , 0x1a80230a },
+	{ 0x417105b8 , 0x4bc680a },
+	{ 0x417105bc , 0x20b803ad },
+	{ 0x417105c0 , 0x78014006 },
+	{ 0x417105c4 , 0x4058a8 },
+	{ 0x417105c8 , 0x400d0b0 },
+	{ 0x417105cc , 0x400c0b0 },
+	{ 0x417105d0 , 0x840370b0 },
+	{ 0x417105d4 , 0xb8d8a8 },
+	{ 0x417105d8 , 0x1038d8a8 },
+	{ 0x417105dc , 0x84a103cc },
+	{ 0x417105e0 , 0xe0a10084 },
+	{ 0x417105e4 , 0x82816106 },
+	{ 0x417105e8 , 0x101c07a9 },
+	{ 0x417105ec , 0xe04168d4 },
+	{ 0x417105f0 , 0xe0811084 },
+	{ 0x417105f4 , 0xe0016380 },
+	{ 0x417105f8 , 0x6701c006 },
+	{ 0x417105fc , 0x1881 },
+	{ 0x41710600 , 0x400e0b0 },
+	{ 0x41710604 , 0x408f0b0 },
+	{ 0x41710608 , 0x334068d4 },
+	{ 0x41710618 , 0x1881 },
+	{ 0x4171061c , 0x22001238 },
+	{ 0x41710620 , 0x880e00a },
+	{ 0x41710624 , 0x130430a8 },
+	{ 0x41710628 , 0xc052a9 },
+	{ 0x4171062c , 0xcc48a9 },
+	{ 0x41710630 , 0x2801430 },
+	{ 0x41710634 , 0x874d8026 },
+	{ 0x41710638 , 0x41c040cd },
+	{ 0x4171063c , 0x2200043c },
+	{ 0x41710640 , 0x4bc080a },
+	{ 0x41710644 , 0x8004007 },
+	{ 0x41710648 , 0x40220b0 },
+	{ 0x41710650 , 0x874d4026 },
+	{ 0x41710654 , 0x2200043c },
+	{ 0x4080004c , 0x4 },
+	{ 0x40800040 , 0x800000 },
+	{ 0x40800044 , 0x820 },
+	{ 0x41718000 , 0x30010000 },
+	{ 0x41718024 , 0x10 },
+	{ 0x41718028 , 0x12000000 },
+	{ 0x4171802c , 0x0 },
+	{ 0x41718040 , 0x40010000 },
+	{ 0x41718044 , 0x0 },
+	{ 0x41718048 , 0xf0000000 },
+	{ 0x41718080 , 0xd8040000 },
+	{ 0x417180a0 , 0x600d0000 },
+	{ 0x417180a4 , 0x7c0d0000 },
+	{ 0x21700dfc , 0xf000 },
+	{ 0x1170123e , 0x0 },
+	{ 0x11701242 , 0x8 },
+	{ 0x11701246 , 0x10 },
+	{ 0x1170124a , 0x18 },
+	{ 0x1170124e , 0x20 },
+	{ 0x11701252 , 0x28 },
+	{ 0x11701256 , 0x30 },
+	{ 0x1170125a , 0x38 },
+	{ 0x40800000 , 0x1027000 },
+	{ 0x40801000 , 0x1027000 },
+	{ 0x40808500 , 0x420 },
+	{ 0x40808840 , 0x8 },
+	{ 0x40808844 , 0x8 },
+	{ 0x40808848 , 0x8 },
+	{ 0x4080884c , 0x8 },
+	{ 0x40898020 , 0x404 },
+	{ 0x40898004 , 0x0 },
+	{ 0x40898028 , 0x5ee05ee },
+	{ 0x40898024 , 0x40404040 },
+	{ 0x4089802c , 0x5ee05ee },
+	{ 0x40898030 , 0x0 },
+	{ 0x40898044 , 0xff },
+	{ 0x40898034 , 0x0 },
+	{ 0x40898420 , 0x404 },
+	{ 0x40898404 , 0x101 },
+	{ 0x40898428 , 0x5ee05ee },
+	{ 0x40898424 , 0x40404040 },
+	{ 0x4089842c , 0x5ee05ee },
+	{ 0x40898430 , 0x0 },
+	{ 0x40898444 , 0xff },
+	{ 0x40898434 , 0x0 },
+	{ 0x40898820 , 0x404 },
+	{ 0x40898804 , 0x202 },
+	{ 0x40898828 , 0x5ee05ee },
+	{ 0x40898824 , 0x40404040 },
+	{ 0x4089882c , 0x5ee05ee },
+	{ 0x40898830 , 0x0 },
+	{ 0x40898844 , 0xff },
+	{ 0x40898834 , 0x0 },
+	{ 0x40898c20 , 0x404 },
+	{ 0x40898c04 , 0x303 },
+	{ 0x40898c28 , 0x5ee05ee },
+	{ 0x40898c24 , 0x40404040 },
+	{ 0x40898c2c , 0x5ee05ee },
+	{ 0x40898c30 , 0x0 },
+	{ 0x40898c44 , 0xff },
+	{ 0x40898c34 , 0x0 },
+	{ 0x40899020 , 0x404 },
+	{ 0x40899004 , 0x404 },
+	{ 0x40899028 , 0x5ee05ee },
+	{ 0x40899024 , 0x40404040 },
+	{ 0x4089902c , 0x5ee05ee },
+	{ 0x40899030 , 0x0 },
+	{ 0x40899044 , 0xff },
+	{ 0x40899034 , 0x0 },
+	{ 0x40899420 , 0x404 },
+	{ 0x40899404 , 0x505 },
+	{ 0x40899428 , 0x5ee05ee },
+	{ 0x40899424 , 0x40404040 },
+	{ 0x4089942c , 0x5ee05ee },
+	{ 0x40899430 , 0x0 },
+	{ 0x40899444 , 0xff },
+	{ 0x40899434 , 0x0 },
+	{ 0x40899820 , 0x404 },
+	{ 0x40899804 , 0x606 },
+	{ 0x40899828 , 0x5ee05ee },
+	{ 0x40899824 , 0x40404040 },
+	{ 0x4089982c , 0x5ee05ee },
+	{ 0x40899830 , 0x0 },
+	{ 0x40899844 , 0xff },
+	{ 0x40899834 , 0x0 },
+	{ 0x40899c20 , 0x404 },
+	{ 0x40899c04 , 0x707 },
+	{ 0x40899c28 , 0x5ee05ee },
+	{ 0x40899c24 , 0x40404040 },
+	{ 0x40899c2c , 0x5ee05ee },
+	{ 0x40899c30 , 0x0 },
+	{ 0x40899c44 , 0xff },
+	{ 0x40899c34 , 0x0 },
+	{ 0x40890020 , 0x80400 },
+	{ 0x40890024 , 0x80410 },
+	{ 0x4089000c , 0x20200000 },
+	{ 0x40890018 , 0x101d0 },
+	{ 0x40890400 , 0x0 },
+	{ 0x40890450 , 0x0 },
+	{ 0x408904b0 , 0x0 },
+	{ 0x408904a0 , 0x70007 },
+	{ 0x408904a4 , 0x0 },
+	{ 0x408904a8 , 0x0 },
+	{ 0x40890908 , 0x1000000 },
+	{ 0x40890920 , 0x1400000 },
+	{ 0x40890940 , 0x13f013f },
+	{ 0x40890960 , 0x280000 },
+	{ 0x40890980 , 0x270027 },
+	{ 0x408900bc , 0x3 },
+	{ 0x408907a4 , 0x0 },
+	{ 0x408907a8 , 0xfff0fff },
+	{ 0x40890908 , 0x1000001 },
+	{ 0x40890924 , 0x3c00280 },
+	{ 0x40890944 , 0x13f013f },
+	{ 0x40890964 , 0x780050 },
+	{ 0x40890984 , 0x270027 },
+	{ 0x40890908 , 0x1000002 },
+	{ 0x40890928 , 0x6400500 },
+	{ 0x40890948 , 0x13f013f },
+	{ 0x40890968 , 0xc800a0 },
+	{ 0x40890988 , 0x270027 },
+	{ 0x408907b8 , 0x2 },
+	{ 0x40890908 , 0x1000003 },
+	{ 0x4089094c , 0x13f013f },
+	{ 0x4089096c , 0x0 },
+	{ 0x4089098c , 0x270027 },
+	{ 0x40890600 , 0x0 },
+	{ 0x40890604 , 0x1 },
+	{ 0x4089090c , 0x3f },
+	{ 0x40890020 , 0xc0400 },
+	{ 0x40890024 , 0xc0410 },
+	{ 0x4089003c , 0x12047c5e },
+	{ 0x408a1000 , 0x5fc000 },
+	{ 0x408a1050 , 0xa015f },
+	{ 0x408a118c , 0x60000001 },
+	{ 0x408a1868 , 0x4 },
+	{ 0x408a186c , 0x4 },
+	{ 0x408a1870 , 0x4 },
+	{ 0x408a1874 , 0x4 },
+	{ 0x408a1878 , 0x4 },
+	{ 0x408a187c , 0x4 },
+	{ 0x408a18f4 , 0x30807 },
+	{ 0x408a18f4 , 0x807 },
+	{ 0x408a1c64 , 0x80 },
+	{ 0x408a1c68 , 0x80 },
+	{ 0x408a1c6c , 0x80 },
+	{ 0x408a1c70 , 0x0 },
+	{ 0x408a1c74 , 0x0 },
+	{ 0x408a1c78 , 0x0 },
+	{ 0x408a1c7c , 0x0 },
+	{ 0x408a1cf4 , 0x30807 },
+	{ 0x408a1cf4 , 0x807 },
+	{ 0x3000000 , 0x20 },
+	{ 0x82880080 , 0xfff00f3f },
+	{ 0x3000000 , 0x20 },
+	{ 0x82880100 , 0xfff00f3f },
+	{ 0x40880180 , 0x7f1ff1ff },
+	{ 0x40880184 , 0xa0c80a8 },
+	{ 0x7000000 , 0x1ff },
+	{ 0x82883000 , 0x40004 },
+	{ 0x4088270c , 0x1ff },
+	{ 0x40882714 , 0x200 },
+	{ 0x40882708 , 0x200 },
+	{ 0x40880080 , 0x7f1ff1ff },
+	{ 0x40880100 , 0x7f1ff1ff },
+	{ 0x40880400 , 0x2001f },
+	{ 0x40880620 , 0x1 },
+	{ 0x40880300 , 0x41c1 },
+	{ 0x40880380 , 0x400 },
+	{ 0x40882700 , 0x1 },
+	{ 0x40882704 , 0x1 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880084 , 0x7f1ff1ff },
+	{ 0x40880104 , 0x7f1ff1ff },
+	{ 0x40880404 , 0x20021 },
+	{ 0x40880620 , 0x3 },
+	{ 0x40880304 , 0x41c1 },
+	{ 0x40880384 , 0x400 },
+	{ 0x40882020 , 0x1 },
+	{ 0x4088202c , 0x1 },
+	{ 0x40882700 , 0x2 },
+	{ 0x40882704 , 0x2 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880088 , 0x7f1ff1ff },
+	{ 0x40880108 , 0x7f1ff1ff },
+	{ 0x40880408 , 0x20023 },
+	{ 0x40880620 , 0x7 },
+	{ 0x40880308 , 0x41c1 },
+	{ 0x40880388 , 0x400 },
+	{ 0x40882040 , 0x2 },
+	{ 0x4088204c , 0x2 },
+	{ 0x40882700 , 0x3 },
+	{ 0x40882704 , 0x3 },
+	{ 0x40880990 , 0x1f },
+	{ 0x4088008c , 0x7f1ff1ff },
+	{ 0x4088010c , 0x7f1ff1ff },
+	{ 0x4088040c , 0x20025 },
+	{ 0x40880620 , 0xf },
+	{ 0x4088030c , 0x41c1 },
+	{ 0x4088038c , 0x400 },
+	{ 0x40882060 , 0x3 },
+	{ 0x4088206c , 0x3 },
+	{ 0x40882700 , 0x4 },
+	{ 0x40882704 , 0x4 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880090 , 0x7f1ff1ff },
+	{ 0x40880110 , 0x7f1ff1ff },
+	{ 0x40880410 , 0x20027 },
+	{ 0x40880620 , 0x1f },
+	{ 0x40880310 , 0x41c1 },
+	{ 0x40880390 , 0x400 },
+	{ 0x40882080 , 0x4 },
+	{ 0x4088208c , 0x4 },
+	{ 0x40882700 , 0x5 },
+	{ 0x40882704 , 0x5 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880094 , 0x7f1ff1ff },
+	{ 0x40880114 , 0x7f1ff1ff },
+	{ 0x40880414 , 0x20029 },
+	{ 0x40880620 , 0x3f },
+	{ 0x40880314 , 0x41c1 },
+	{ 0x40880394 , 0x400 },
+	{ 0x408820a0 , 0x5 },
+	{ 0x408820ac , 0x5 },
+	{ 0x40882700 , 0x6 },
+	{ 0x40882704 , 0x6 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880098 , 0x7f1ff1ff },
+	{ 0x40880118 , 0x7f1ff1ff },
+	{ 0x40880418 , 0x2002b },
+	{ 0x40880620 , 0x7f },
+	{ 0x40880318 , 0x41c1 },
+	{ 0x40880398 , 0x400 },
+	{ 0x408820c0 , 0x6 },
+	{ 0x408820cc , 0x6 },
+	{ 0x40882700 , 0x7 },
+	{ 0x40882704 , 0x7 },
+	{ 0x40880990 , 0x1f },
+	{ 0x4088009c , 0x7f1ff1ff },
+	{ 0x4088011c , 0x7f1ff1ff },
+	{ 0x4088041c , 0x2002d },
+	{ 0x40880620 , 0xff },
+	{ 0x4088031c , 0x41c1 },
+	{ 0x4088039c , 0x400 },
+	{ 0x408820e0 , 0x7 },
+	{ 0x408820ec , 0x7 },
+	{ 0x40882700 , 0x8 },
+	{ 0x40882704 , 0x8 },
+	{ 0x40880990 , 0x1f },
+	{ 0x408800a0 , 0x7f1ff1ff },
+	{ 0x40880120 , 0x7f1ff1ff },
+	{ 0x40880420 , 0x20035 },
+	{ 0x40880620 , 0x1ff },
+	{ 0x40880320 , 0x41c1 },
+	{ 0x408803a0 , 0x400 },
+	{ 0x40882100 , 0x8 },
+	{ 0x4088210c , 0x8 },
+	{ 0x40882700 , 0x9 },
+	{ 0x40882704 , 0x9 },
+	{ 0x40880990 , 0x1f },
+	{ 0x408800a4 , 0x7f1ff1ff },
+	{ 0x40880124 , 0x7f1ff1ff },
+	{ 0x40880424 , 0x3001f },
+	{ 0x40880620 , 0x3ff },
+	{ 0x40880324 , 0x1c1 },
+	{ 0x408803a4 , 0x400 },
+	{ 0x40882120 , 0x9 },
+	{ 0x4088212c , 0x9 },
+	{ 0x40882700 , 0xa },
+	{ 0x40882704 , 0xa },
+	{ 0x40880990 , 0x1f },
+	{ 0x408800a8 , 0x7f1ff1ff },
+	{ 0x40880128 , 0x7f1ff1ff },
+	{ 0x40880428 , 0x30021 },
+	{ 0x40880620 , 0x7ff },
+	{ 0x40880328 , 0x1c1 },
+	{ 0x408803a8 , 0x400 },
+	{ 0x40882140 , 0xa },
+	{ 0x4088214c , 0xa },
+	{ 0x40882700 , 0xb },
+	{ 0x40882704 , 0xb },
+	{ 0x40880990 , 0x1f },
+	{ 0x408800ac , 0x7f1ff1ff },
+	{ 0x4088012c , 0x7f1ff1ff },
+	{ 0x4088042c , 0x30023 },
+	{ 0x40880620 , 0xfff },
+	{ 0x4088032c , 0x1c1 },
+	{ 0x408803ac , 0x400 },
+	{ 0x40882160 , 0xb },
+	{ 0x4088216c , 0xb },
+	{ 0x40882700 , 0xc },
+	{ 0x40882704 , 0xc },
+	{ 0x40880990 , 0x1f },
+	{ 0x408800b0 , 0x7f1ff1ff },
+	{ 0x40880130 , 0x7f1ff1ff },
+	{ 0x40880430 , 0x11ae0000 },
+	{ 0x408804c0 , 0x1000 },
+	{ 0x40880620 , 0x1fff },
+	{ 0x40880330 , 0x41c1 },
+	{ 0x40882180 , 0xc },
+	{ 0x4088218c , 0xc },
+	{ 0x40882700 , 0xd },
+	{ 0x40882704 , 0xd },
+	{ 0x40880990 , 0x1f },
+	{ 0x408800b4 , 0x7f1ff1ff },
+	{ 0x40880134 , 0x7f1ff1ff },
+	{ 0x40880434 , 0x30027 },
+	{ 0x40880620 , 0x3fff },
+	{ 0x40880334 , 0x1c1 },
+	{ 0x408803b4 , 0x400 },
+	{ 0x408821a0 , 0xd },
+	{ 0x408821ac , 0xd },
+	{ 0x40882700 , 0xe },
+	{ 0x40882704 , 0xe },
+	{ 0x40880990 , 0x1f },
+	{ 0x408800b8 , 0x7f1ff1ff },
+	{ 0x40880138 , 0x7f1ff1ff },
+	{ 0x40880438 , 0x30029 },
+	{ 0x40880620 , 0x7fff },
+	{ 0x40880338 , 0x1c1 },
+	{ 0x408803b8 , 0x400 },
+	{ 0x408821c0 , 0xe },
+	{ 0x408821cc , 0xe },
+	{ 0x40882700 , 0xf },
+	{ 0x40882704 , 0xf },
+	{ 0x40880990 , 0x1f },
+	{ 0x408800bc , 0x7f1ff1ff },
+	{ 0x4088013c , 0x7f1ff1ff },
+	{ 0x4088043c , 0x3002b },
+	{ 0x40880620 , 0xffff },
+	{ 0x4088033c , 0x1c1 },
+	{ 0x408803bc , 0x400 },
+	{ 0x408821e0 , 0xf },
+	{ 0x408821ec , 0xf },
+	{ 0x40882700 , 0x10 },
+	{ 0x40882704 , 0x10 },
+	{ 0x40880990 , 0x1f },
+	{ 0x408800c0 , 0x7f1ff1ff },
+	{ 0x40880140 , 0x7f1ff1ff },
+	{ 0x40880440 , 0x3002d },
+	{ 0x40880620 , 0x1ffff },
+	{ 0x40880340 , 0x1c1 },
+	{ 0x408803c0 , 0x400 },
+	{ 0x40882200 , 0x10 },
+	{ 0x4088220c , 0x10 },
+	{ 0x40882700 , 0x11 },
+	{ 0x40882704 , 0x11 },
+	{ 0x40880990 , 0x1f },
+	{ 0x408800c4 , 0x0 },
+	{ 0x40880144 , 0x0 },
+	{ 0x40880624 , 0x20000 },
+	{ 0x40882220 , 0x11 },
+	{ 0x4088222c , 0x11 },
+	{ 0x40882700 , 0x12 },
+	{ 0x40882704 , 0x12 },
+	{ 0x40880990 , 0x1f },
+	{ 0x40880520 , 0x1 },
+	{ 0x40880604 , 0x3f },
+	{ 0x40880900 , 0x1 },
+	{ 0x40880480 , 0x28 },
+	{ 0x408804d0 , 0x15a },
+	{ 0x408804d8 , 0xa6 },
+	{ 0x408804d4 , 0x15a },
+	{ 0x408804dc , 0xa6 },
+	{ 0x40880980 , 0x100 },
+	{ 0x40880004 , 0x1feff },
+	{ 0x40880850 , 0x201 },
+	{ 0x4089803c , 0x3 },
+	{ 0x4089843c , 0x3 },
+	{ 0x4089883c , 0x3 },
+	{ 0x40898c3c , 0x3 },
+	{ 0x4089903c , 0x3 },
+	{ 0x4089943c , 0x3 },
+	{ 0x4089983c , 0x3 },
+	{ 0x40899c3c , 0x3 },
+	{ 0x40880000 , 0x11 },
+	{ 0x40c00000 , 0x307 },
+	{ 0x4089c000 , 0x1 },
+	{ 0x4089d000 , 0x1 },
+	{ 0x40800000 , 0x1027001 },
+	{ 0x1170123e , 0x0 },
+	{ 0x11701242 , 0x8 },
+	{ 0x11701246 , 0x10 },
+	{ 0x1170124a , 0x18 },
+	{ 0x1170124e , 0x20 },
+	{ 0x11701252 , 0x28 },
+	{ 0x11701256 , 0x30 },
+	{ 0x1170125a , 0x38 },
+    { (ACCESS_LOG_OP_STOP << 24), 0 }
+};
diff --git a/drivers/net/bcmbca/xrdp/data_path_6846.c b/drivers/net/bcmbca/xrdp/data_path_6846.c
new file mode 100644
index 0000000000..ba669d7a07
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/data_path_6846.c
@@ -0,0 +1,1025 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include "access_logging.h"
+
+const access_log_tuple_t init_data[] = {
+    { 0x40d97004 , 0x82d00000 },
+    { 0x40d97008 , 0xffe00000 },
+    { 0x40d9700c , 0x82e00000 },
+    { 0x40d97010 , 0xffe00000 },
+    { 0x40d96008 , 0x20002 },
+    { 0x40140004 , 0x82140000 },
+    { 0x40140008 , 0xc0000 },
+    { 0x4014000c , 0x82100000 },
+    { 0x40140010 , 0xc0000 },
+    { 0x40140014 , 0x82180000 },
+    { 0x40140018 , 0xc0000 },
+    { 0x5c00000 , 0x0 },
+    { 0x2000000 , 0x4000 },
+    { 0x82c00000 , 0x0 },
+    { 0x2000000 , 0x800 },
+    { 0x82c18000 , 0x0 },
+    { 0x3000000 , 0x2000 },
+    { 0x82c10000 , 0xfc000000 },
+    { 0x41c10000 , 0x6008006 },
+    { 0x41c1000c , 0x1a008006 },
+    { 0x41c10018 , 0x42061032 },
+    { 0x41c1001c , 0x83062032 },
+    { 0x41c10020 , 0x24 },
+    { 0x41c10024 , 0x3074032 },
+    { 0x41c10028 , 0x83076032 },
+    { 0x41c1002c , 0x5f8040a },
+    { 0x41c10030 , 0xc094ac },
+    { 0x41c10034 , 0x8020 },
+    { 0x41c10038 , 0x740180b0 },
+    { 0x41c1003c , 0x230104cc },
+    { 0x41c10040 , 0xb8d9ac },
+    { 0x41c10044 , 0xf4ffc3b0 },
+    { 0x41c10048 , 0x80a10684 },
+    { 0x41c1004c , 0x19800006 },
+    { 0x41c10050 , 0xe18d4a8 },
+    { 0x41c10054 , 0x400c0b0 },
+    { 0x41c10058 , 0x8020 },
+    { 0x41c1005c , 0x40380b0 },
+    { 0x41c10060 , 0x862104cc },
+    { 0x41c10064 , 0x20 },
+    { 0x41c10068 , 0x21c0036 },
+    { 0x41c1006c , 0x421c1036 },
+    { 0x41c10070 , 0x831c2036 },
+    { 0x41c10074 , 0x31d4036 },
+    { 0x41c10078 , 0x831d6036 },
+    { 0x41c1007c , 0x31e8036 },
+    { 0x41c10080 , 0x831ea036 },
+    { 0x41c10084 , 0x31fc036 },
+    { 0x41c10088 , 0x831fe036 },
+    { 0x41c1008c , 0x3200037 },
+    { 0x41c10090 , 0x83202037 },
+    { 0x41c10094 , 0x3214037 },
+    { 0x41c10098 , 0x83216037 },
+    { 0x41c1009c , 0x3228037 },
+    { 0x41c100a0 , 0x8322a037 },
+    { 0x41c100a4 , 0x323c037 },
+    { 0x41c100a8 , 0x8323e037 },
+    { 0x41c100ac , 0x820080c6 },
+    { 0x41c100b0 , 0x1684ac },
+    { 0x41c100b4 , 0xc20e8036 },
+    { 0x41c100d4 , 0xc2 },
+    { 0x41c100f4 , 0x21c0032 },
+    { 0x41c100f8 , 0x421c1032 },
+    { 0x41c100fc , 0x831c2032 },
+    { 0x41c10100 , 0x31d4032 },
+    { 0x41c10104 , 0x831d6032 },
+    { 0x41c10108 , 0x31e8032 },
+    { 0x41c1010c , 0x831ea032 },
+    { 0x41c10110 , 0x31fc032 },
+    { 0x41c10114 , 0x831fe032 },
+    { 0x41c10118 , 0x3200033 },
+    { 0x41c1011c , 0x83202033 },
+    { 0x41c10120 , 0x3214033 },
+    { 0x41c10124 , 0x83216033 },
+    { 0x41c10128 , 0x3228033 },
+    { 0x41c1012c , 0x8322a033 },
+    { 0x41c10130 , 0x323c033 },
+    { 0x41c10134 , 0x8323e033 },
+    { 0x41c10144 , 0x1008022 },
+    { 0x41c10154 , 0x4400c0b0 },
+    { 0x41c10158 , 0x40080b0 },
+    { 0x41c1015c , 0x1c69e },
+    { 0x41c10160 , 0x8001c480 },
+    { 0x41c10164 , 0x140040b0 },
+    { 0x41c1016c , 0x2008630 },
+    { 0x41c10170 , 0x80008480 },
+    { 0x41c10174 , 0x2008634 },
+    { 0x41c10178 , 0x26008632 },
+    { 0x41c1017c , 0x80008482 },
+    { 0x41c10180 , 0x26008636 },
+    { 0x41c10184 , 0x47002833 },
+    { 0x41c10188 , 0x300e830 },
+    { 0x41c1018c , 0x402689ac },
+    { 0x41c10190 , 0x4f7c890a },
+    { 0x41c10194 , 0xc0aa87ad },
+    { 0x41c10198 , 0x20004497 },
+    { 0x41c1019c , 0x400d0b0 },
+    { 0x41c101a0 , 0x40080b0 },
+    { 0x41c101a4 , 0x81d69e },
+    { 0x41c101a8 , 0xa0018480 },
+    { 0x41c101ac , 0xb8c7ac },
+    { 0x41c101b0 , 0x40060b1 },
+    { 0x41c101b4 , 0x200d430 },
+    { 0x41c101b8 , 0x8080d680 },
+    { 0x41c101bc , 0x200d434 },
+    { 0x41c101c0 , 0x2600d432 },
+    { 0x41c101c4 , 0x8081d680 },
+    { 0x41c101c8 , 0x8080d682 },
+    { 0x41c101cc , 0x2600d436 },
+    { 0x41c101d0 , 0x40070b1 },
+    { 0x41c101d4 , 0x400e0b0 },
+    { 0x41c101d8 , 0x6a0a4a8 },
+    { 0x41c101dc , 0x1f0462a9 },
+    { 0x41c101e0 , 0x61c60a9 },
+    { 0x41c101e4 , 0x85c24431 },
+    { 0x41c101e8 , 0x40080b0 },
+    { 0x41c101ec , 0x400d0b0 },
+    { 0x41c101f0 , 0x1f0470a9 },
+    { 0x41c101f4 , 0x7a4e5a8 },
+    { 0x41c101f8 , 0x628aca8 },
+    { 0x41c101fc , 0x1860a9 },
+    { 0x41c10200 , 0x79156aa9 },
+    { 0x41c10204 , 0xec889a8 },
+    { 0x41c10208 , 0x2b8d7a8 },
+    { 0x41c1020c , 0x1d0470a9 },
+    { 0x41c10210 , 0x26805833 },
+    { 0x41c10218 , 0xa2e03a02 },
+    { 0x41c1021c , 0x47806837 },
+    { 0x41c10220 , 0x6808836 },
+    { 0x41c10224 , 0x2680d836 },
+    { 0x41c10228 , 0x44080b0 },
+    { 0x41c1022c , 0x821883 },
+    { 0x41c10230 , 0x1400d0b0 },
+    { 0x41c10234 , 0x8811889 },
+    { 0x41c10238 , 0x40080b0 },
+    { 0x41c1023c , 0x81d69e },
+    { 0x41c10240 , 0xa0018480 },
+    { 0x41c1024c , 0x200d430 },
+    { 0x41c10250 , 0x8080d680 },
+    { 0x41c10254 , 0x200d434 },
+    { 0x41c10258 , 0x2600d432 },
+    { 0x41c1025c , 0x8081c680 },
+    { 0x41c10260 , 0x8000c682 },
+    { 0x41c10264 , 0x2600c436 },
+    { 0x41c10268 , 0x6a0a4a8 },
+    { 0x41c1026c , 0x90005cc },
+    { 0x41c10270 , 0x1f0422a9 },
+    { 0x41c10274 , 0x6e1dfaa8 },
+    { 0x41c10278 , 0x628aca8 },
+    { 0x41c1027c , 0x47150024 },
+    { 0x41c10280 , 0xc84125cd },
+    { 0x41c10288 , 0x340090b1 },
+    { 0x41c1028c , 0x40050b1 },
+    { 0x41c10290 , 0x819c9f },
+    { 0x41c10294 , 0x20835a81 },
+    { 0x41c102a0 , 0x2809a31 },
+    { 0x41c102a4 , 0x80809c81 },
+    { 0x41c102a8 , 0x2809a35 },
+    { 0x41c102ac , 0x26809a33 },
+    { 0x41c102b0 , 0x80819c81 },
+    { 0x41c102b4 , 0x80809c83 },
+    { 0x41c102b8 , 0x26809a37 },
+    { 0x41c102bc , 0x240050b1 },
+    { 0x41c102c0 , 0x6210024 },
+    { 0x41c102c4 , 0x2ae0ac2 },
+    { 0x41c102cc , 0x2400c0b0 },
+    { 0x41c102d0 , 0x40080b0 },
+    { 0x41c102d4 , 0x1c69e },
+    { 0x41c102d8 , 0x80018480 },
+    { 0x41c102dc , 0x85c24431 },
+    { 0x41c102e4 , 0x200c430 },
+    { 0x41c102e8 , 0x8000c680 },
+    { 0x41c102ec , 0x200c434 },
+    { 0x41c102f0 , 0x2600c432 },
+    { 0x41c102f4 , 0x8000c682 },
+    { 0x41c102f8 , 0x10008007 },
+    { 0x41c102fc , 0x2600c436 },
+    { 0x41c10300 , 0x240180b0 },
+    { 0x41c10304 , 0x9a000006 },
+    { 0x41c10308 , 0x400a0b0 },
+    { 0x41c1030c , 0x408b0b0 },
+    { 0x41c10310 , 0x1a59e },
+    { 0x41c10314 , 0x4081a580 },
+    { 0x41c10318 , 0x140040b0 },
+    { 0x41c10320 , 0x200b530 },
+    { 0x41c10324 , 0x8080b580 },
+    { 0x41c10328 , 0x200b534 },
+    { 0x41c1032c , 0x2600b532 },
+    { 0x41c10330 , 0x8080b582 },
+    { 0x41c10334 , 0x2600b536 },
+    { 0x41c10338 , 0x300c430 },
+    { 0x41c1033c , 0x4700a432 },
+    { 0x41c10340 , 0x280e430 },
+    { 0x41c10344 , 0x8141a7cc },
+    { 0x41c10348 , 0x87300024 },
+    { 0x41c1034c , 0x26000436 },
+    { 0x40d0004c , 0x4 },
+    { 0x48f92ab8 , 0x2 },
+    { 0x48f92ab8 , 0x2 },
+    { 0x40d00040 , 0xf0 },
+    { 0x40d00044 , 0x826 },
+    { 0x41c00060 , 0x0 },
+    { 0x41c00064 , 0x1000000 },
+    { 0x41c00068 , 0x0 },
+    { 0x41c0006c , 0x0 },
+    { 0x41c00070 , 0x0 },
+    { 0x41c00074 , 0x0 },
+    { 0x41c00078 , 0x0 },
+    { 0x41c0007c , 0x0 },
+    { 0x41c18000 , 0x0 },
+    { 0x41c18004 , 0x4 },
+    { 0x41c18008 , 0x12000000 },
+    { 0x41c1800c , 0x0 },
+    { 0x41c18010 , 0x0 },
+    { 0x41c18014 , 0x0 },
+    { 0x41c18018 , 0x0 },
+    { 0x41c1801c , 0x0 },
+    { 0x41c18020 , 0x40015401 },
+    { 0x41c18024 , 0x80000 },
+    { 0x41c18028 , 0x0 },
+    { 0x41c1802c , 0x0 },
+    { 0x41c18030 , 0x0 },
+    { 0x41c18034 , 0x0 },
+    { 0x41c18038 , 0x0 },
+    { 0x41c1803c , 0x0 },
+    { 0x41c18040 , 0x0 },
+    { 0x41c18044 , 0x0 },
+    { 0x41c18048 , 0x0 },
+    { 0x41c1804c , 0x0 },
+    { 0x41c18050 , 0x0 },
+    { 0x41c18054 , 0x0 },
+    { 0x41c18058 , 0x0 },
+    { 0x41c1805c , 0x0 },
+    { 0x41c18060 , 0x50000000 },
+    { 0x41c18064 , 0xdc000000 },
+    { 0x41c18068 , 0x0 },
+    { 0x41c1806c , 0x0 },
+    { 0x41c18070 , 0x0 },
+    { 0x41c18074 , 0x0 },
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+    { 0x40d90968 , 0xc800a0 },
+    { 0x40d90988 , 0x270027 },
+    { 0x40d90708 , 0x280020 },
+    { 0x40d90758 , 0x70007 },
+    { 0x40d90808 , 0x0 },
+    { 0x40d90858 , 0xfff0fff },
+    { 0x40d90908 , 0x1000003 },
+    { 0x40d9094c , 0x13f013f },
+    { 0x40d9096c , 0x0 },
+    { 0x40d9098c , 0x270027 },
+    { 0x40d9070c , 0x380030 },
+    { 0x40d9075c , 0x70007 },
+    { 0x40d9080c , 0x0 },
+    { 0x40d9085c , 0xfff0fff },
+    { 0x40d90600 , 0x0 },
+    { 0x40d90604 , 0x1 },
+    { 0x40d9090c , 0x3f },
+    { 0x40d90020 , 0xc0380 },
+    { 0x40d90024 , 0xc0380 },
+    { 0x40d9003c , 0x12047c5e },
+    { 0x40d98000 , 0x17fc000 },
+    { 0x40d98050 , 0xa01fd },
+    { 0x40d9809c , 0xa01e0 },
+    { 0x40d98104 , 0x1401c0 },
+    { 0x40d98054 , 0xa0400 },
+    { 0x40d98100 , 0xa03c0 },
+    { 0x40d98108 , 0x140200 },
+    { 0x40d988d4 , 0x10 },
+    { 0x40d98824 , 0xe },
+    { 0x40d98844 , 0x203 },
+    { 0x40d98864 , 0x84 },
+    { 0x40d98884 , 0x201f },
+    { 0x40d98828 , 0xe },
+    { 0x40d98848 , 0x203 },
+    { 0x40d98868 , 0x84 },
+    { 0x40d98888 , 0x2e21 },
+    { 0x40d9884c , 0x203 },
+    { 0x40d9886c , 0x84 },
+    { 0x40d9888c , 0x2023 },
+    { 0x40d98850 , 0x203 },
+    { 0x40d98870 , 0x84 },
+    { 0x40d98890 , 0x2025 },
+    { 0x40d98854 , 0x203 },
+    { 0x40d98874 , 0x84 },
+    { 0x40d98894 , 0x2027 },
+    { 0x40d98858 , 0x608 },
+    { 0x40d98878 , 0x84 },
+    { 0x40d98898 , 0x202d },
+    { 0x40d98cd4 , 0x8 },
+    { 0x40d98c04 , 0x7 },
+    { 0x40d98c24 , 0xe },
+    { 0x40d98c44 , 0x203 },
+    { 0x40d98c64 , 0x84 },
+    { 0x40d98c84 , 0x201f },
+    { 0x40d98c08 , 0x7 },
+    { 0x40d98c28 , 0xe },
+    { 0x40d98c48 , 0x203 },
+    { 0x40d98c68 , 0x84 },
+    { 0x40d98c88 , 0x2e21 },
+    { 0x40d98c0c , 0x7 },
+    { 0x40d98c4c , 0x203 },
+    { 0x40d98c6c , 0x84 },
+    { 0x40d98c8c , 0x2023 },
+    { 0x40d98c10 , 0x7 },
+    { 0x40d98c50 , 0x203 },
+    { 0x40d98c70 , 0x84 },
+    { 0x40d98c90 , 0x2025 },
+    { 0x40d98c14 , 0x7 },
+    { 0x40d98c54 , 0x203 },
+    { 0x40d98c74 , 0x84 },
+    { 0x40d98c94 , 0x2027 },
+    { 0x40d98c18 , 0xd },
+    { 0x40d98c58 , 0x608 },
+    { 0x40d98c78 , 0x84 },
+    { 0x40d98c98 , 0x202d },
+    { 0x3000000 , 0x20 },
+    { 0x82d80080 , 0xfff00f3f },
+    { 0x3000000 , 0x20 },
+    { 0x82d80100 , 0xfff00f3f },
+    { 0x40d80180 , 0x7f1ff1ff },
+    { 0x40d80184 , 0xa0c80bc },
+    { 0x7000000 , 0x1ff },
+    { 0x82d83000 , 0x40004 },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d80080 , 0x7f1ff1ff },
+    { 0x40d80100 , 0x7f1ff1ff },
+    { 0x40d80400 , 0x2001f },
+    { 0x40d80620 , 0x1 },
+    { 0x40d80300 , 0x4191 },
+    { 0x40d80380 , 0x400 },
+    { 0x40d82700 , 0x1 },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0x1 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80084 , 0x7f1ff1ff },
+    { 0x40d80104 , 0x7f1ff1ff },
+    { 0x40d80404 , 0x20021 },
+    { 0x40d80620 , 0x3 },
+    { 0x40d80304 , 0x4191 },
+    { 0x40d80384 , 0x400 },
+    { 0x40d82020 , 0x1 },
+    { 0x40d8202c , 0x1 },
+    { 0x40d82700 , 0x2 },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0x2 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80088 , 0x7f1ff1ff },
+    { 0x40d80108 , 0x7f1ff1ff },
+    { 0x40d80408 , 0x20023 },
+    { 0x40d80620 , 0x7 },
+    { 0x40d80308 , 0x4191 },
+    { 0x40d80388 , 0x400 },
+    { 0x40d82040 , 0x2 },
+    { 0x40d8204c , 0x2 },
+    { 0x40d82700 , 0x3 },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0x3 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d8008c , 0x7f1ff1ff },
+    { 0x40d8010c , 0x7f1ff1ff },
+    { 0x40d8040c , 0x20025 },
+    { 0x40d80620 , 0xf },
+    { 0x40d8030c , 0x4191 },
+    { 0x40d8038c , 0x400 },
+    { 0x40d82060 , 0x3 },
+    { 0x40d8206c , 0x3 },
+    { 0x40d82700 , 0x4 },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0x4 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80090 , 0x7f1ff1ff },
+    { 0x40d80110 , 0x7f1ff1ff },
+    { 0x40d80410 , 0x20027 },
+    { 0x40d80620 , 0x1f },
+    { 0x40d80310 , 0x4191 },
+    { 0x40d80390 , 0x400 },
+    { 0x40d82080 , 0x4 },
+    { 0x40d8208c , 0x4 },
+    { 0x40d82700 , 0x5 },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0x5 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80094 , 0x7f1ff1ff },
+    { 0x40d80114 , 0x7f1ff1ff },
+    { 0x40d80414 , 0x2002d },
+    { 0x40d80620 , 0x3f },
+    { 0x40d80314 , 0x4191 },
+    { 0x40d80394 , 0x400 },
+    { 0x40d820a0 , 0x5 },
+    { 0x40d820ac , 0x5 },
+    { 0x40d82700 , 0x6 },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0x6 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80098 , 0x7f1ff1ff },
+    { 0x40d80118 , 0x7f1ff1ff },
+    { 0x40d80418 , 0x3001f },
+    { 0x40d80620 , 0x7f },
+    { 0x40d80318 , 0x191 },
+    { 0x40d80398 , 0x400 },
+    { 0x40d820c0 , 0x6 },
+    { 0x40d820cc , 0x6 },
+    { 0x40d82700 , 0x7 },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0x7 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d8009c , 0x7f1ff1ff },
+    { 0x40d8011c , 0x7f1ff1ff },
+    { 0x40d8041c , 0x30021 },
+    { 0x40d80620 , 0xff },
+    { 0x40d8031c , 0x191 },
+    { 0x40d8039c , 0x400 },
+    { 0x40d820e0 , 0x7 },
+    { 0x40d820ec , 0x7 },
+    { 0x40d82700 , 0x8 },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0x8 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800a0 , 0x7f1ff1ff },
+    { 0x40d80120 , 0x7f1ff1ff },
+    { 0x40d80420 , 0x30023 },
+    { 0x40d80620 , 0x1ff },
+    { 0x40d80320 , 0x191 },
+    { 0x40d803a0 , 0x400 },
+    { 0x40d82100 , 0x8 },
+    { 0x40d8210c , 0x8 },
+    { 0x40d82700 , 0x9 },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0x9 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800a4 , 0x7f1ff1ff },
+    { 0x40d80124 , 0x7f1ff1ff },
+    { 0x40d80424 , 0x30025 },
+    { 0x40d80620 , 0x3ff },
+    { 0x40d80324 , 0x191 },
+    { 0x40d803a4 , 0x400 },
+    { 0x40d82120 , 0x9 },
+    { 0x40d8212c , 0x9 },
+    { 0x40d82700 , 0xa },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0xa },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800a8 , 0x7f1ff1ff },
+    { 0x40d80128 , 0x7f1ff1ff },
+    { 0x40d80428 , 0x30027 },
+    { 0x40d80620 , 0x7ff },
+    { 0x40d80328 , 0x191 },
+    { 0x40d803a8 , 0x400 },
+    { 0x40d82140 , 0xa },
+    { 0x40d8214c , 0xa },
+    { 0x40d82700 , 0xb },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0xb },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800ac , 0x7f1ff1ff },
+    { 0x40d8012c , 0x7f1ff1ff },
+    { 0x40d8042c , 0x3002d },
+    { 0x40d80620 , 0xfff },
+    { 0x40d8032c , 0x1191 },
+    { 0x40d803ac , 0x400 },
+    { 0x40d82160 , 0xb },
+    { 0x40d8216c , 0xb },
+    { 0x40d82700 , 0xc },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0xc },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800b0 , 0x7f1ff1ff },
+    { 0x40d80130 , 0x7f1ff1ff },
+    { 0x40d80430 , 0x101a0000 },
+    { 0x40d804c0 , 0x1000 },
+    { 0x40d80620 , 0x1fff },
+    { 0x40d80330 , 0x4191 },
+    { 0x40d82180 , 0xc },
+    { 0x40d8218c , 0xc },
+    { 0x40d82700 , 0xd },
+    { 0x40d8270c , 0x1ff },
+    { 0x40d82714 , 0x200 },
+    { 0x40d82708 , 0x200 },
+    { 0x40d82704 , 0xd },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80520 , 0x1 },
+    { 0x40d80604 , 0x3f },
+    { 0x40d80900 , 0x1 },
+    { 0x40d80480 , 0x28 },
+    { 0x40d804d0 , 0x17f },
+    { 0x40d804d8 , 0x81 },
+    { 0x40d804d4 , 0x17f },
+    { 0x40d804dc , 0x81 },
+    { 0x40d80980 , 0x100 },
+    { 0x40d80004 , 0x17df },
+    { 0x40d80850 , 0x201 },
+    { 0x40d9403c , 0x3 },
+    { 0x40d9443c , 0x3 },
+    { 0x40d9483c , 0x3 },
+    { 0x40d94c3c , 0x3 },
+    { 0x40d9503c , 0x3 },
+    { 0x40d80000 , 0x101 },
+    { 0x40100000 , 0x307 },
+    { 0x40d96000 , 0x1 },
+    { 0x40d00000 , 0x102bb01 },
+    { 0x40d01000 , 0x102bb01 },
+    { 0x40d02000 , 0x102bb01 },
+    { 0x11c0063e , 0x0 },
+    { 0x11c00642 , 0x8 },
+    { 0x11c00646 , 0x10 },
+    { 0x11c0064a , 0x18 },
+    { 0x11c0064e , 0x20 },
+    { (ACCESS_LOG_OP_STOP << 24), 0 }
+};
diff --git a/drivers/net/bcmbca/xrdp/data_path_6856.c b/drivers/net/bcmbca/xrdp/data_path_6856.c
new file mode 100644
index 0000000000..4eb8892339
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/data_path_6856.c
@@ -0,0 +1,1142 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include "access_logging.h"
+
+const access_log_tuple_t init_data[] = {
+    { 0x40d98300 , 0x1e0d },
+    { 0x40d98308 , 0x28 },
+    { 0x40db2284 , 0x1090608 },
+    { 0x40db2284 , 0x1090638 },
+    { 0x40db2284 , 0x1090600 },
+    { 0x40d98004 , 0x82d00000 },
+    { 0x40d98008 , 0xffe00000 },
+    { 0x40d9800c , 0x82e00000 },
+    { 0x40d98010 , 0xffe00000 },
+    { 0x40d96008 , 0x20002 },
+    { 0x40d97008 , 0x20002 },
+    { 0x40140004 , 0x82140000 },
+    { 0x40140008 , 0xc0000 },
+    { 0x4014000c , 0x82100000 },
+    { 0x40140010 , 0xc0000 },
+    { 0x40140014 , 0x82180000 },
+    { 0x40140018 , 0xc0000 },
+    { 0x5c00000 , 0x0 },
+    { 0x2000000 , 0x4000 },
+    { 0x82c00000 , 0x0 },
+    { 0x2000000 , 0x800 },
+    { 0x82c18000 , 0x0 },
+    { 0x3000000 , 0x2000 },
+    { 0x82c10000 , 0xfc000000 },
+    { 0x41c10000 , 0x6008006 },
+    { 0x41c1000c , 0x1a008006 },
+    { 0x41c10018 , 0x42061032 },
+    { 0x41c1001c , 0x83062032 },
+    { 0x41c10020 , 0x24 },
+    { 0x41c10024 , 0x3074032 },
+    { 0x41c10028 , 0x83076032 },
+    { 0x41c1002c , 0x5f8040a },
+    { 0x41c10030 , 0xc094ac },
+    { 0x41c10034 , 0x8020 },
+    { 0x41c10038 , 0x740180b0 },
+    { 0x41c1003c , 0x230104cc },
+    { 0x41c10040 , 0xb8d9ac },
+    { 0x41c10044 , 0xf4ffc3b0 },
+    { 0x41c10048 , 0x80a10684 },
+    { 0x41c1004c , 0x19800006 },
+    { 0x41c10050 , 0xe18d4a8 },
+    { 0x41c10054 , 0x400c0b0 },
+    { 0x41c10058 , 0x8020 },
+    { 0x41c1005c , 0x40380b0 },
+    { 0x41c10060 , 0x862104cc },
+    { 0x41c10064 , 0x20 },
+    { 0x41c10068 , 0x21c0036 },
+    { 0x41c1006c , 0x421c1036 },
+    { 0x41c10070 , 0x831c2036 },
+    { 0x41c10074 , 0x31d4036 },
+    { 0x41c10078 , 0x831d6036 },
+    { 0x41c1007c , 0x31e8036 },
+    { 0x41c10080 , 0x831ea036 },
+    { 0x41c10084 , 0x31fc036 },
+    { 0x41c10088 , 0x831fe036 },
+    { 0x41c1008c , 0x3200037 },
+    { 0x41c10090 , 0x83202037 },
+    { 0x41c10094 , 0x3214037 },
+    { 0x41c10098 , 0x83216037 },
+    { 0x41c1009c , 0x3228037 },
+    { 0x41c100a0 , 0x8322a037 },
+    { 0x41c100a4 , 0x323c037 },
+    { 0x41c100a8 , 0x8323e037 },
+    { 0x41c100ac , 0x820080c6 },
+    { 0x41c100b0 , 0x1684ac },
+    { 0x41c100b4 , 0xc20e8036 },
+    { 0x41c100d4 , 0xc2 },
+    { 0x41c100f4 , 0x21c0032 },
+    { 0x41c100f8 , 0x421c1032 },
+    { 0x41c100fc , 0x831c2032 },
+    { 0x41c10100 , 0x31d4032 },
+    { 0x41c10104 , 0x831d6032 },
+    { 0x41c10108 , 0x31e8032 },
+    { 0x41c1010c , 0x831ea032 },
+    { 0x41c10110 , 0x31fc032 },
+    { 0x41c10114 , 0x831fe032 },
+    { 0x41c10118 , 0x3200033 },
+    { 0x41c1011c , 0x83202033 },
+    { 0x41c10120 , 0x3214033 },
+    { 0x41c10124 , 0x83216033 },
+    { 0x41c10128 , 0x3228033 },
+    { 0x41c1012c , 0x8322a033 },
+    { 0x41c10130 , 0x323c033 },
+    { 0x41c10134 , 0x8323e033 },
+    { 0x41c10144 , 0x1008022 },
+    { 0x41c10154 , 0x4400c0b0 },
+    { 0x41c10158 , 0x40080b0 },
+    { 0x41c1015c , 0x1c69e },
+    { 0x41c10160 , 0x8001c480 },
+    { 0x41c10164 , 0x140040b0 },
+    { 0x41c1016c , 0x2008630 },
+    { 0x41c10170 , 0x80008480 },
+    { 0x41c10174 , 0x2008634 },
+    { 0x41c10178 , 0x26008632 },
+    { 0x41c1017c , 0x80008482 },
+    { 0x41c10180 , 0x26008636 },
+    { 0x41c10184 , 0x47002833 },
+    { 0x41c10188 , 0x300e830 },
+    { 0x41c1018c , 0x402689ac },
+    { 0x41c10190 , 0x4f7c890a },
+    { 0x41c10194 , 0xc0aa87ad },
+    { 0x41c10198 , 0x20004497 },
+    { 0x41c1019c , 0x400d0b0 },
+    { 0x41c101a0 , 0x40080b0 },
+    { 0x41c101a4 , 0x81d69e },
+    { 0x41c101a8 , 0xa0018480 },
+    { 0x41c101ac , 0xb8c7ac },
+    { 0x41c101b0 , 0x40060b1 },
+    { 0x41c101b4 , 0x200d430 },
+    { 0x41c101b8 , 0x8080d680 },
+    { 0x41c101bc , 0x200d434 },
+    { 0x41c101c0 , 0x2600d432 },
+    { 0x41c101c4 , 0x8081d680 },
+    { 0x41c101c8 , 0x8080d682 },
+    { 0x41c101cc , 0x2600d436 },
+    { 0x41c101d0 , 0x40070b1 },
+    { 0x41c101d4 , 0x400e0b0 },
+    { 0x41c101d8 , 0x6a0a4a8 },
+    { 0x41c101dc , 0x1f0462a9 },
+    { 0x41c101e0 , 0x61c60a9 },
+    { 0x41c101e4 , 0x85c24431 },
+    { 0x41c101e8 , 0x40080b0 },
+    { 0x41c101ec , 0x400d0b0 },
+    { 0x41c101f0 , 0x1f0470a9 },
+    { 0x41c101f4 , 0x7a4e5a8 },
+    { 0x41c101f8 , 0x628aca8 },
+    { 0x41c101fc , 0x1860a9 },
+    { 0x41c10200 , 0x79156aa9 },
+    { 0x41c10204 , 0xec889a8 },
+    { 0x41c10208 , 0x2b8d7a8 },
+    { 0x41c1020c , 0x1d0470a9 },
+    { 0x41c10210 , 0x26805833 },
+    { 0x41c10218 , 0xa2e03a02 },
+    { 0x41c1021c , 0x47806837 },
+    { 0x41c10220 , 0x6808836 },
+    { 0x41c10224 , 0x2680d836 },
+    { 0x41c10228 , 0x44080b0 },
+    { 0x41c1022c , 0x821883 },
+    { 0x41c10230 , 0x1400d0b0 },
+    { 0x41c10234 , 0x8811889 },
+    { 0x41c10238 , 0x40080b0 },
+    { 0x41c1023c , 0x81d69e },
+    { 0x41c10240 , 0xa0018480 },
+    { 0x41c1024c , 0x200d430 },
+    { 0x41c10250 , 0x8080d680 },
+    { 0x41c10254 , 0x200d434 },
+    { 0x41c10258 , 0x2600d432 },
+    { 0x41c1025c , 0x8081c680 },
+    { 0x41c10260 , 0x8000c682 },
+    { 0x41c10264 , 0x2600c436 },
+    { 0x41c10268 , 0x6a0a4a8 },
+    { 0x41c1026c , 0x90005cc },
+    { 0x41c10270 , 0x1f0422a9 },
+    { 0x41c10274 , 0x6e1dfaa8 },
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+    { 0x40d9442c , 0x5ee05ee },
+    { 0x40d94430 , 0x12 },
+    { 0x40d94444 , 0xff },
+    { 0x40d94434 , 0x1000 },
+    { 0x40d94434 , 0x0 },
+    { 0x40d94464 , 0xf },
+    { 0x40d94820 , 0x505 },
+    { 0x40d9481c , 0xa0a },
+    { 0x40d94800 , 0x15 },
+    { 0x40d94800 , 0x301215 },
+    { 0x40d94804 , 0x202 },
+    { 0x40d94824 , 0x40404040 },
+    { 0x40d94828 , 0x60005ee },
+    { 0x40d94824 , 0x40404040 },
+    { 0x40d94828 , 0x5ee05ee },
+    { 0x40d94824 , 0x40404040 },
+    { 0x40d9482c , 0x60005ee },
+    { 0x40d94824 , 0x40404040 },
+    { 0x40d9482c , 0x5ee05ee },
+    { 0x40d94830 , 0x12 },
+    { 0x40d94844 , 0xff },
+    { 0x40d94834 , 0x1000 },
+    { 0x40d94834 , 0x0 },
+    { 0x40d94864 , 0xf },
+    { 0x40d94c20 , 0x505 },
+    { 0x40d94c1c , 0xf0f },
+    { 0x40d94c00 , 0x15 },
+    { 0x40d94c00 , 0x301215 },
+    { 0x40d94c04 , 0x303 },
+    { 0x40d94c24 , 0x40404040 },
+    { 0x40d94c28 , 0x60005ee },
+    { 0x40d94c24 , 0x40404040 },
+    { 0x40d94c28 , 0x5ee05ee },
+    { 0x40d94c24 , 0x40404040 },
+    { 0x40d94c2c , 0x60005ee },
+    { 0x40d94c24 , 0x40404040 },
+    { 0x40d94c2c , 0x5ee05ee },
+    { 0x40d94c30 , 0x12 },
+    { 0x40d94c44 , 0xff },
+    { 0x40d94c34 , 0x1000 },
+    { 0x40d94c34 , 0x0 },
+    { 0x40d94c64 , 0xf },
+    { 0x40d95020 , 0x505 },
+    { 0x40d9501c , 0x1414 },
+    { 0x40d95000 , 0x15 },
+    { 0x40d95000 , 0x301215 },
+    { 0x40d95004 , 0x404 },
+    { 0x40d95024 , 0x40404040 },
+    { 0x40d95028 , 0x60005ee },
+    { 0x40d95024 , 0x40404040 },
+    { 0x40d95028 , 0x5ee05ee },
+    { 0x40d95024 , 0x40404040 },
+    { 0x40d9502c , 0x60005ee },
+    { 0x40d95024 , 0x40404040 },
+    { 0x40d9502c , 0x5ee05ee },
+    { 0x40d95030 , 0x12 },
+    { 0x40d95044 , 0xff },
+    { 0x40d95034 , 0x1000 },
+    { 0x40d95034 , 0x0 },
+    { 0x40d95064 , 0xf },
+    { 0x40d95420 , 0x707 },
+    { 0x40d9541c , 0x1919 },
+    { 0x40d95400 , 0x15 },
+    { 0x40d95400 , 0x301215 },
+    { 0x40d95404 , 0x505 },
+    { 0x40d95424 , 0x40404040 },
+    { 0x40d95428 , 0x60005ee },
+    { 0x40d95424 , 0x40404040 },
+    { 0x40d95428 , 0x5ee05ee },
+    { 0x40d95424 , 0x40404040 },
+    { 0x40d9542c , 0x60005ee },
+    { 0x40d95424 , 0x40404040 },
+    { 0x40d9542c , 0x5ee05ee },
+    { 0x40d95430 , 0x12 },
+    { 0x40d95444 , 0xff },
+    { 0x40d95434 , 0x1000 },
+    { 0x40d95434 , 0x0 },
+    { 0x40d95464 , 0xf },
+    { 0x40d90000 , 0x1 },
+    { 0x40d90004 , 0x17300000 },
+    { 0x40d90004 , 0x17300013 },
+    { 0x40d90020 , 0x80780 },
+    { 0x40d90004 , 0x17301513 },
+    { 0x40d90024 , 0x80780 },
+    { 0x40d9000c , 0x20200007 },
+    { 0x40d90018 , 0x10030 },
+    { 0x40d90400 , 0x80000 },
+    { 0x40d90450 , 0x70007 },
+    { 0x40d90500 , 0x0 },
+    { 0x40d90550 , 0x0 },
+    { 0x40d90908 , 0x1000000 },
+    { 0x40d90920 , 0x1400000 },
+    { 0x40d90940 , 0x13f013f },
+    { 0x40d90960 , 0x280000 },
+    { 0x40d90980 , 0x270027 },
+    { 0x40d90700 , 0x80000 },
+    { 0x40d90750 , 0x70007 },
+    { 0x40d90800 , 0x0 },
+    { 0x40d90850 , 0xfff0fff },
+    { 0x40d90908 , 0x1000001 },
+    { 0x40d90924 , 0x3c00280 },
+    { 0x40d90944 , 0x13f013f },
+    { 0x40d90964 , 0x780050 },
+    { 0x40d90984 , 0x270027 },
+    { 0x40d90704 , 0x180010 },
+    { 0x40d90754 , 0x70007 },
+    { 0x40d90804 , 0x0 },
+    { 0x40d90854 , 0xfff0fff },
+    { 0x40d90908 , 0x1000002 },
+    { 0x40d90928 , 0x6400500 },
+    { 0x40d90948 , 0x13f013f },
+    { 0x40d90968 , 0xc800a0 },
+    { 0x40d90988 , 0x270027 },
+    { 0x40d90708 , 0x280020 },
+    { 0x40d90758 , 0x70007 },
+    { 0x40d90808 , 0x0 },
+    { 0x40d90858 , 0xfff0fff },
+    { 0x40d90908 , 0x1000003 },
+    { 0x40d9094c , 0x13f013f },
+    { 0x40d9096c , 0x0 },
+    { 0x40d9098c , 0x270027 },
+    { 0x40d9070c , 0x380030 },
+    { 0x40d9075c , 0x70007 },
+    { 0x40d9080c , 0x0 },
+    { 0x40d9085c , 0xfff0fff },
+    { 0x40d90600 , 0x0 },
+    { 0x40d90604 , 0x1 },
+    { 0x40d9090c , 0x3f },
+    { 0x40d90020 , 0xc0780 },
+    { 0x40d90024 , 0xc0780 },
+    { 0x40d9003c , 0x12047c5e },
+    { 0x40d99000 , 0x1ffc000 },
+    { 0x40d998d4 , 0x10 },
+    { 0x40d99824 , 0x1e },
+    { 0x40d99844 , 0x203 },
+    { 0x40d99864 , 0x84 },
+    { 0x40d99884 , 0x201f },
+    { 0x40d99828 , 0x1e },
+    { 0x40d99848 , 0x203 },
+    { 0x40d99868 , 0x84 },
+    { 0x40d99888 , 0x21 },
+    { 0x40d9984c , 0x203 },
+    { 0x40d9986c , 0x84 },
+    { 0x40d9988c , 0x23 },
+    { 0x40d99850 , 0x203 },
+    { 0x40d99870 , 0x84 },
+    { 0x40d99890 , 0x25 },
+    { 0x40d99854 , 0x203 },
+    { 0x40d99874 , 0x84 },
+    { 0x40d99894 , 0x27 },
+    { 0x40d99858 , 0x203 },
+    { 0x40d99878 , 0x84 },
+    { 0x40d99898 , 0x29 },
+    { 0x40d9985c , 0x608 },
+    { 0x40d9987c , 0x84 },
+    { 0x40d9989c , 0x2d },
+    { 0x40d99cd4 , 0x8 },
+    { 0x40d99c04 , 0x5 },
+    { 0x40d99c24 , 0x1e },
+    { 0x40d99c44 , 0x203 },
+    { 0x40d99c64 , 0x84 },
+    { 0x40d99c84 , 0x2e1f },
+    { 0x40d99c08 , 0x5 },
+    { 0x40d99c28 , 0x1e },
+    { 0x40d99c48 , 0x203 },
+    { 0x40d99c68 , 0x84 },
+    { 0x40d99c88 , 0x21 },
+    { 0x40d99c0c , 0x5 },
+    { 0x40d99c4c , 0x203 },
+    { 0x40d99c6c , 0x84 },
+    { 0x40d99c8c , 0x23 },
+    { 0x40d99c10 , 0x5 },
+    { 0x40d99c50 , 0x203 },
+    { 0x40d99c70 , 0x84 },
+    { 0x40d99c90 , 0x25 },
+    { 0x40d99c14 , 0x5 },
+    { 0x40d99c54 , 0x203 },
+    { 0x40d99c74 , 0x84 },
+    { 0x40d99c94 , 0x27 },
+    { 0x40d99c18 , 0x7 },
+    { 0x40d99c58 , 0x203 },
+    { 0x40d99c78 , 0x84 },
+    { 0x40d99c98 , 0x29 },
+    { 0x40d99c1c , 0x20 },
+    { 0x40d99c5c , 0x608 },
+    { 0x40d99c7c , 0x84 },
+    { 0x40d99c9c , 0x2d },
+    { 0x40d9a0d4 , 0x8 },
+    { 0x40d9a004 , 0x5 },
+    { 0x40d9a024 , 0x1e },
+    { 0x40d9a044 , 0x203 },
+    { 0x40d9a064 , 0x84 },
+    { 0x40d9a084 , 0x201f },
+    { 0x40d9a008 , 0x5 },
+    { 0x40d9a028 , 0x1e },
+    { 0x40d9a048 , 0x203 },
+    { 0x40d9a068 , 0x84 },
+    { 0x40d9a088 , 0x21 },
+    { 0x40d9a00c , 0x5 },
+    { 0x40d9a04c , 0x203 },
+    { 0x40d9a06c , 0x84 },
+    { 0x40d9a08c , 0x23 },
+    { 0x40d9a010 , 0x5 },
+    { 0x40d9a050 , 0x203 },
+    { 0x40d9a070 , 0x84 },
+    { 0x40d9a090 , 0x25 },
+    { 0x40d9a014 , 0x5 },
+    { 0x40d9a054 , 0x203 },
+    { 0x40d9a074 , 0x84 },
+    { 0x40d9a094 , 0x27 },
+    { 0x40d9a018 , 0x7 },
+    { 0x40d9a058 , 0x203 },
+    { 0x40d9a078 , 0x84 },
+    { 0x40d9a098 , 0x29 },
+    { 0x40d9a01c , 0x20 },
+    { 0x40d9a05c , 0x608 },
+    { 0x40d9a07c , 0x84 },
+    { 0x40d9a09c , 0x2d },
+    { 0x40d9a4d4 , 0x8 },
+    { 0x40d9a404 , 0x5 },
+    { 0x40d9a424 , 0x1e },
+    { 0x40d9a444 , 0x203 },
+    { 0x40d9a464 , 0x84 },
+    { 0x40d9a484 , 0x2e1f },
+    { 0x40d9a408 , 0x5 },
+    { 0x40d9a428 , 0x1e },
+    { 0x40d9a448 , 0x203 },
+    { 0x40d9a468 , 0x84 },
+    { 0x40d9a488 , 0x21 },
+    { 0x40d9a40c , 0x5 },
+    { 0x40d9a44c , 0x203 },
+    { 0x40d9a46c , 0x84 },
+    { 0x40d9a48c , 0x23 },
+    { 0x40d9a410 , 0x5 },
+    { 0x40d9a450 , 0x203 },
+    { 0x40d9a470 , 0x84 },
+    { 0x40d9a490 , 0x25 },
+    { 0x40d9a414 , 0x5 },
+    { 0x40d9a454 , 0x203 },
+    { 0x40d9a474 , 0x84 },
+    { 0x40d9a494 , 0x27 },
+    { 0x40d9a418 , 0x7 },
+    { 0x40d9a458 , 0x203 },
+    { 0x40d9a478 , 0x84 },
+    { 0x40d9a498 , 0x29 },
+    { 0x40d9a41c , 0x20 },
+    { 0x40d9a45c , 0x608 },
+    { 0x40d9a47c , 0x84 },
+    { 0x40d9a49c , 0x2d },
+    { 0x3000000 , 0x20 },
+    { 0x82d80080 , 0xfff00f3f },
+    { 0x3000000 , 0x20 },
+    { 0x82d80100 , 0xfff00f3f },
+    { 0x40d80180 , 0xff3ff3ff },
+    { 0x40d80184 , 0xa0c80a8 },
+    { 0x7000000 , 0x3ff },
+    { 0x82d83000 , 0x40004 },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d80080 , 0xff3ff3ff },
+    { 0x40d80100 , 0xff3ff3ff },
+    { 0x40d80400 , 0x2001f },
+    { 0x40d80620 , 0x1 },
+    { 0x40d80300 , 0x43a1 },
+    { 0x40d80380 , 0x400 },
+    { 0x40d82700 , 0x1 },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0x1 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80084 , 0xff3ff3ff },
+    { 0x40d80104 , 0xff3ff3ff },
+    { 0x40d80404 , 0x20021 },
+    { 0x40d80620 , 0x3 },
+    { 0x40d80304 , 0x43a1 },
+    { 0x40d80384 , 0x400 },
+    { 0x40d82020 , 0x1 },
+    { 0x40d8202c , 0x1 },
+    { 0x40d82700 , 0x2 },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0x2 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80088 , 0xff3ff3ff },
+    { 0x40d80108 , 0xff3ff3ff },
+    { 0x40d80408 , 0x20023 },
+    { 0x40d80620 , 0x7 },
+    { 0x40d80308 , 0x43a1 },
+    { 0x40d80388 , 0x400 },
+    { 0x40d82040 , 0x2 },
+    { 0x40d8204c , 0x2 },
+    { 0x40d82700 , 0x3 },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0x3 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d8008c , 0xff3ff3ff },
+    { 0x40d8010c , 0xff3ff3ff },
+    { 0x40d8040c , 0x20025 },
+    { 0x40d80620 , 0xf },
+    { 0x40d8030c , 0x43a1 },
+    { 0x40d8038c , 0x400 },
+    { 0x40d82060 , 0x3 },
+    { 0x40d8206c , 0x3 },
+    { 0x40d82700 , 0x4 },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0x4 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80090 , 0xff3ff3ff },
+    { 0x40d80110 , 0xff3ff3ff },
+    { 0x40d80410 , 0x20027 },
+    { 0x40d80620 , 0x1f },
+    { 0x40d80310 , 0x43a1 },
+    { 0x40d80390 , 0x400 },
+    { 0x40d82080 , 0x4 },
+    { 0x40d8208c , 0x4 },
+    { 0x40d82700 , 0x5 },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0x5 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80094 , 0xff3ff3ff },
+    { 0x40d80114 , 0xff3ff3ff },
+    { 0x40d80414 , 0x20029 },
+    { 0x40d80620 , 0x3f },
+    { 0x40d80314 , 0x43a1 },
+    { 0x40d80394 , 0x400 },
+    { 0x40d820a0 , 0x5 },
+    { 0x40d820ac , 0x5 },
+    { 0x40d82700 , 0x6 },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0x6 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80098 , 0xff3ff3ff },
+    { 0x40d80118 , 0xff3ff3ff },
+    { 0x40d80418 , 0x2002d },
+    { 0x40d80620 , 0x7f },
+    { 0x40d80318 , 0x43a1 },
+    { 0x40d80398 , 0x400 },
+    { 0x40d820c0 , 0x6 },
+    { 0x40d820cc , 0x6 },
+    { 0x40d82700 , 0x7 },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0x7 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d8009c , 0xff3ff3ff },
+    { 0x40d8011c , 0xff3ff3ff },
+    { 0x40d8041c , 0x3001f },
+    { 0x40d80620 , 0xff },
+    { 0x40d8031c , 0x3a1 },
+    { 0x40d8039c , 0x400 },
+    { 0x40d820e0 , 0x7 },
+    { 0x40d820ec , 0x7 },
+    { 0x40d82700 , 0x8 },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0x8 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800a0 , 0xff3ff3ff },
+    { 0x40d80120 , 0xff3ff3ff },
+    { 0x40d80420 , 0x30021 },
+    { 0x40d80620 , 0x1ff },
+    { 0x40d80320 , 0x3a1 },
+    { 0x40d803a0 , 0x400 },
+    { 0x40d82100 , 0x8 },
+    { 0x40d8210c , 0x8 },
+    { 0x40d82700 , 0x9 },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0x9 },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800a4 , 0xff3ff3ff },
+    { 0x40d80124 , 0xff3ff3ff },
+    { 0x40d80424 , 0x30023 },
+    { 0x40d80620 , 0x3ff },
+    { 0x40d80324 , 0x3a1 },
+    { 0x40d803a4 , 0x400 },
+    { 0x40d82120 , 0x9 },
+    { 0x40d8212c , 0x9 },
+    { 0x40d82700 , 0xa },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0xa },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800a8 , 0xff3ff3ff },
+    { 0x40d80128 , 0xff3ff3ff },
+    { 0x40d80428 , 0x30025 },
+    { 0x40d80620 , 0x7ff },
+    { 0x40d80328 , 0x3a1 },
+    { 0x40d803a8 , 0x400 },
+    { 0x40d82140 , 0xa },
+    { 0x40d8214c , 0xa },
+    { 0x40d82700 , 0xb },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0xb },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800ac , 0xff3ff3ff },
+    { 0x40d8012c , 0xff3ff3ff },
+    { 0x40d8042c , 0x30027 },
+    { 0x40d80620 , 0xfff },
+    { 0x40d8032c , 0x3a1 },
+    { 0x40d803ac , 0x400 },
+    { 0x40d82160 , 0xb },
+    { 0x40d8216c , 0xb },
+    { 0x40d82700 , 0xc },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0xc },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800b0 , 0xff3ff3ff },
+    { 0x40d80130 , 0xff3ff3ff },
+    { 0x40d80430 , 0x101a0000 },
+    { 0x40d804c0 , 0x1000 },
+    { 0x40d80620 , 0x1fff },
+    { 0x40d80330 , 0x43a1 },
+    { 0x40d82180 , 0xc },
+    { 0x40d8218c , 0xc },
+    { 0x40d82700 , 0xd },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0xd },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800b4 , 0xff3ff3ff },
+    { 0x40d80134 , 0xff3ff3ff },
+    { 0x40d80434 , 0x3002d },
+    { 0x40d804c0 , 0x1000 },
+    { 0x40d80620 , 0x3fff },
+    { 0x40d80334 , 0x13a1 },
+    { 0x40d803b4 , 0x400 },
+    { 0x40d821a0 , 0xd },
+    { 0x40d821ac , 0xd },
+    { 0x40d82700 , 0xe },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0xe },
+    { 0x40d80990 , 0x1f },
+    { 0x40d800b8 , 0x0 },
+    { 0x40d80138 , 0x0 },
+    { 0x40d804c0 , 0x1000 },
+    { 0x40d80624 , 0x4000 },
+    { 0x40d821c0 , 0xe },
+    { 0x40d821cc , 0xe },
+    { 0x40d82700 , 0xf },
+    { 0x40d8270c , 0x3ff },
+    { 0x40d82714 , 0x400 },
+    { 0x40d82708 , 0x400 },
+    { 0x40d82704 , 0xf },
+    { 0x40d80990 , 0x1f },
+    { 0x40d80520 , 0x1 },
+    { 0x40d80604 , 0x3f },
+    { 0x40d80900 , 0x1 },
+    { 0x40d80480 , 0x28 },
+    { 0x40d804d0 , 0x36d },
+    { 0x40d804d8 , 0x93 },
+    { 0x40d804d4 , 0x36d },
+    { 0x40d804dc , 0x93 },
+    { 0x40d80980 , 0x100 },
+    { 0x40d80004 , 0x5fbf },
+    { 0x40d80850 , 0x201 },
+    { 0x40d9403c , 0x3 },
+    { 0x40d9443c , 0x3 },
+    { 0x40d9483c , 0x3 },
+    { 0x40d94c3c , 0x3 },
+    { 0x40d9503c , 0x3 },
+    { 0x40d9543c , 0x3 },
+    { 0x40d80000 , 0x101 },
+    { 0x40100000 , 0x307 },
+    { 0x40d96000 , 0x1 },
+    { 0x40d97000 , 0x1 },
+    { 0x40d00000 , 0x102bb01 },
+    { 0x11c0063e , 0x0 },
+    { 0x11c00642 , 0x8 },
+    { 0x11c00646 , 0x10 },
+    { 0x11c0064a , 0x18 },
+    { 0x11c0064e , 0x20 },
+    { 0x11c00652 , 0x28 },
+    { (ACCESS_LOG_OP_STOP << 24), 0 }
+};
diff --git a/drivers/net/bcmbca/xrdp/data_path_6858.c b/drivers/net/bcmbca/xrdp/data_path_6858.c
new file mode 100644
index 0000000000..7874deb97e
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/data_path_6858.c
@@ -0,0 +1,2399 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include "access_logging.h"
+
+const access_log_tuple_t init_data[] = {
+    { 0x40d2a004 , 0x82d00000 },
+    { 0x40d2a008 , 0xffe00000 },
+    { 0x40d2a00c , 0x82e00000 },
+    { 0x40d2a010 , 0xffe00000 },
+    { 0x40d28008 , 0x20002 },
+    { 0x40d29008 , 0x20002 },
+    { 0x40140004 , 0x82140000 },
+    { 0x40140008 , 0xc0000 },
+    { 0x4014000c , 0x82100000 },
+    { 0x40140010 , 0xc0000 },
+    { 0x40140014 , 0x82180000 },
+    { 0x40140018 , 0xc0000 },
+    { 0x5200000 , 0x0 },
+    { 0x2000000 , 0x4000 },
+    { 0x82200000 , 0x0 },
+    { 0x2000000 , 0x800 },
+    { 0x82218000 , 0x0 },
+    { 0x3000000 , 0x2000 },
+    { 0x82210000 , 0xfc000000 },
+    { 0x41210000 , 0x6008006 },
+    { 0x4121000c , 0x1a008006 },
+    { 0x41210018 , 0x42061032 },
+    { 0x4121001c , 0x83062032 },
+    { 0x41210020 , 0x24 },
+    { 0x41210024 , 0x3074032 },
+    { 0x41210028 , 0x83076032 },
+    { 0x4121002c , 0x5f8040a },
+    { 0x41210030 , 0xc094ac },
+    { 0x41210034 , 0x8020 },
+    { 0x41210038 , 0x740180b0 },
+    { 0x4121003c , 0x230104cc },
+    { 0x41210040 , 0xb8d9ac },
+    { 0x41210044 , 0xf4ffc3b0 },
+    { 0x41210048 , 0x80a10684 },
+    { 0x4121004c , 0x19800006 },
+    { 0x41210050 , 0xe18d4a8 },
+    { 0x41210054 , 0x400c0b0 },
+    { 0x41210058 , 0x8020 },
+    { 0x4121005c , 0x40380b0 },
+    { 0x41210060 , 0x862104cc },
+    { 0x41210064 , 0x20 },
+    { 0x41210068 , 0x21c0036 },
+    { 0x4121006c , 0x421c1036 },
+    { 0x41210070 , 0x831c2036 },
+    { 0x41210074 , 0x31d4036 },
+    { 0x41210078 , 0x831d6036 },
+    { 0x4121007c , 0x31e8036 },
+    { 0x41210080 , 0x831ea036 },
+    { 0x41210084 , 0x31fc036 },
+    { 0x41210088 , 0x831fe036 },
+    { 0x4121008c , 0x3200037 },
+    { 0x41210090 , 0x83202037 },
+    { 0x41210094 , 0x3214037 },
+    { 0x41210098 , 0x83216037 },
+    { 0x4121009c , 0x3228037 },
+    { 0x412100a0 , 0x8322a037 },
+    { 0x412100a4 , 0x323c037 },
+    { 0x412100a8 , 0x8323e037 },
+    { 0x412100ac , 0x820080c6 },
+    { 0x412100b0 , 0x1684ac },
+    { 0x412100b4 , 0xc20e8036 },
+    { 0x412100d4 , 0xc2 },
+    { 0x412100f4 , 0x21c0032 },
+    { 0x412100f8 , 0x421c1032 },
+    { 0x412100fc , 0x831c2032 },
+    { 0x41210100 , 0x31d4032 },
+    { 0x41210104 , 0x831d6032 },
+    { 0x41210108 , 0x31e8032 },
+    { 0x4121010c , 0x831ea032 },
+    { 0x41210110 , 0x31fc032 },
+    { 0x41210114 , 0x831fe032 },
+    { 0x41210118 , 0x3200033 },
+    { 0x4121011c , 0x83202033 },
+    { 0x41210120 , 0x3214033 },
+    { 0x41210124 , 0x83216033 },
+    { 0x41210128 , 0x3228033 },
+    { 0x4121012c , 0x8322a033 },
+    { 0x41210130 , 0x323c033 },
+    { 0x41210134 , 0x8323e033 },
+    { 0x41210144 , 0x1008022 },
+    { 0x41210154 , 0x4400c0b0 },
+    { 0x41210158 , 0x40080b0 },
+    { 0x4121015c , 0x1c69e },
+    { 0x41210160 , 0x8001c480 },
+    { 0x41210164 , 0x140040b0 },
+    { 0x4121016c , 0x2008630 },
+    { 0x41210170 , 0x80008480 },
+    { 0x41210174 , 0x2008634 },
+    { 0x41210178 , 0x26008632 },
+    { 0x4121017c , 0x80008482 },
+    { 0x41210180 , 0x26008636 },
+    { 0x41210184 , 0x47002833 },
+    { 0x41210188 , 0x300e830 },
+    { 0x4121018c , 0x402689ac },
+    { 0x41210190 , 0x4f7c890a },
+    { 0x41210194 , 0xc0aa87ad },
+    { 0x41210198 , 0x20004497 },
+    { 0x4121019c , 0x400d0b0 },
+    { 0x412101a0 , 0x40080b0 },
+    { 0x412101a4 , 0x81d69e },
+    { 0x412101a8 , 0xa0018480 },
+    { 0x412101ac , 0xb8c7ac },
+    { 0x412101b0 , 0x40060b1 },
+    { 0x412101b4 , 0x200d430 },
+    { 0x412101b8 , 0x8080d680 },
+    { 0x412101bc , 0x200d434 },
+    { 0x412101c0 , 0x2600d432 },
+    { 0x412101c4 , 0x8081d680 },
+    { 0x412101c8 , 0x8080d682 },
+    { 0x412101cc , 0x2600d436 },
+    { 0x412101d0 , 0x40070b1 },
+    { 0x412101d4 , 0x400e0b0 },
+    { 0x412101d8 , 0x6a0a4a8 },
+    { 0x412101dc , 0x1f0462a9 },
+    { 0x412101e0 , 0x61c60a9 },
+    { 0x412101e4 , 0x85c24431 },
+    { 0x412101e8 , 0x40080b0 },
+    { 0x412101ec , 0x400d0b0 },
+    { 0x412101f0 , 0x1f0470a9 },
+    { 0x412101f4 , 0x7a4e5a8 },
+    { 0x412101f8 , 0x628aca8 },
+    { 0x412101fc , 0x1860a9 },
+    { 0x41210200 , 0x79156aa9 },
+    { 0x41210204 , 0xec889a8 },
+    { 0x41210208 , 0x2b8d7a8 },
+    { 0x4121020c , 0x1d0470a9 },
+    { 0x41210210 , 0x26805833 },
+    { 0x41210218 , 0xa2e03a02 },
+    { 0x4121021c , 0x47806837 },
+    { 0x41210220 , 0x6808836 },
+    { 0x41210224 , 0x2680d836 },
+    { 0x41210228 , 0x44080b0 },
+    { 0x4121022c , 0x821883 },
+    { 0x41210230 , 0x1400d0b0 },
+    { 0x41210234 , 0x8811889 },
+    { 0x41210238 , 0x40080b0 },
+    { 0x4121023c , 0x81d69e },
+    { 0x41210240 , 0xa0018480 },
+    { 0x4121024c , 0x200d430 },
+    { 0x41210250 , 0x8080d680 },
+    { 0x41210254 , 0x200d434 },
+    { 0x41210258 , 0x2600d432 },
+    { 0x4121025c , 0x8081c680 },
+    { 0x41210260 , 0x8000c682 },
+    { 0x41210264 , 0x2600c436 },
+    { 0x41210268 , 0x6a0a4a8 },
+    { 0x4121026c , 0x90005cc },
+    { 0x41210270 , 0x1f0422a9 },
+    { 0x41210274 , 0x6e1dfaa8 },
+    { 0x41210278 , 0x628aca8 },
+    { 0x4121027c , 0x47150024 },
+    { 0x41210280 , 0xc84125cd },
+    { 0x41210288 , 0x340090b1 },
+    { 0x4121028c , 0x40050b1 },
+    { 0x41210290 , 0x819c9f },
+    { 0x41210294 , 0x20835a81 },
+    { 0x412102a0 , 0x2809a31 },
+    { 0x412102a4 , 0x80809c81 },
+    { 0x412102a8 , 0x2809a35 },
+    { 0x412102ac , 0x26809a33 },
+    { 0x412102b0 , 0x80819c81 },
+    { 0x412102b4 , 0x80809c83 },
+    { 0x412102b8 , 0x26809a37 },
+    { 0x412102bc , 0x240050b1 },
+    { 0x412102c0 , 0x6210024 },
+    { 0x412102c4 , 0x2ae0ac2 },
+    { 0x412102cc , 0x2400c0b0 },
+    { 0x412102d0 , 0x40080b0 },
+    { 0x412102d4 , 0x1c69e },
+    { 0x412102d8 , 0x80018480 },
+    { 0x412102dc , 0x85c24431 },
+    { 0x412102e4 , 0x200c430 },
+    { 0x412102e8 , 0x8000c680 },
+    { 0x412102ec , 0x200c434 },
+    { 0x412102f0 , 0x2600c432 },
+    { 0x412102f4 , 0x8000c682 },
+    { 0x412102f8 , 0x10008007 },
+    { 0x412102fc , 0x2600c436 },
+    { 0x41210300 , 0x240180b0 },
+    { 0x41210304 , 0x9a000006 },
+    { 0x41210308 , 0x400a0b0 },
+    { 0x4121030c , 0x408b0b0 },
+    { 0x41210310 , 0x1a59e },
+    { 0x41210314 , 0x4081a580 },
+    { 0x41210318 , 0x140040b0 },
+    { 0x41210320 , 0x200b530 },
+    { 0x41210324 , 0x8080b580 },
+    { 0x41210328 , 0x200b534 },
+    { 0x4121032c , 0x2600b532 },
+    { 0x41210330 , 0x8080b582 },
+    { 0x41210334 , 0x2600b536 },
+    { 0x41210338 , 0x300c430 },
+    { 0x4121033c , 0x4700a432 },
+    { 0x41210340 , 0x280e430 },
+    { 0x41210344 , 0x8141a7cc },
+    { 0x41210348 , 0x87300024 },
+    { 0x4121034c , 0x26000436 },
+    { 0x4028004c , 0x4 },
+    { 0x40280040 , 0xf0 },
+    { 0x40280044 , 0x826 },
+    { 0x41200060 , 0x0 },
+    { 0x41200064 , 0x1000000 },
+    { 0x41200068 , 0x0 },
+    { 0x4120006c , 0x0 },
+    { 0x41200070 , 0x0 },
+    { 0x41200074 , 0x0 },
+    { 0x41200078 , 0x0 },
+    { 0x4120007c , 0x0 },
+    { 0x41218000 , 0x0 },
+    { 0x41218004 , 0x4 },
+    { 0x41218008 , 0x12000000 },
+    { 0x41218010 , 0x0 },
+    { 0x41218014 , 0x0 },
+    { 0x41218018 , 0x0 },
+    { 0x41218020 , 0x0 },
+    { 0x41218024 , 0x0 },
+    { 0x41218028 , 0x40015401 },
+    { 0x41218030 , 0x80000 },
+    { 0x41218034 , 0x0 },
+    { 0x41218038 , 0x0 },
+    { 0x41218040 , 0x0 },
+    { 0x41218044 , 0x0 },
+    { 0x41218048 , 0x0 },
+    { 0x41218050 , 0x0 },
+    { 0x41218054 , 0x0 },
+    { 0x41218058 , 0x0 },
+    { 0x41218060 , 0x0 },
+    { 0x41218064 , 0x0 },
+    { 0x41218068 , 0x0 },
+    { 0x41218070 , 0x0 },
+    { 0x41218074 , 0x0 },
+    { 0x41218078 , 0x0 },
+    { 0x41218080 , 0x50000000 },
+    { 0x41218084 , 0xdc000000 },
+    { 0x41218088 , 0x0 },
+    { 0x41218090 , 0x0 },
+    { 0x41218094 , 0x0 },
+    { 0x41218098 , 0x0 },
+    { 0x412180a0 , 0x0 },
+    { 0x412180a4 , 0x0 },
+    { 0x412180a8 , 0x803 },
+    { 0x412180b0 , 0x0 },
+    { 0x412180b4 , 0x0 },
+    { 0x412180b8 , 0x0 },
+    { 0x412180c0 , 0x0 },
+    { 0x412180c4 , 0x0 },
+    { 0x412180c8 , 0x0 },
+    { 0x412180d0 , 0x0 },
+    { 0x412180d4 , 0x0 },
+    { 0x412180d8 , 0x0 },
+    { 0x412180e0 , 0x0 },
+    { 0x412180e4 , 0x0 },
+    { 0x412180e8 , 0x0 },
+    { 0x412180f0 , 0x0 },
+    { 0x412180f4 , 0x0 },
+    { 0x412180f8 , 0x0 },
+    { 0x41218100 , 0x0 },
+    { 0x41218104 , 0x0 },
+    { 0x41218108 , 0x0 },
+    { 0x41218110 , 0x0 },
+    { 0x41218114 , 0x0 },
+    { 0x41218118 , 0x0 },
+    { 0x41218120 , 0x0 },
+    { 0x41218124 , 0x0 },
+    { 0x41218128 , 0x0 },
+    { 0x41218130 , 0x0 },
+    { 0x41218134 , 0x0 },
+    { 0x41218138 , 0x0 },
+    { 0x41218140 , 0x0 },
+    { 0x41218144 , 0x0 },
+    { 0x41218148 , 0x0 },
+    { 0x41218150 , 0x0 },
+    { 0x41218154 , 0x0 },
+    { 0x41218158 , 0x0 },
+    { 0x41218160 , 0x0 },
+    { 0x41218164 , 0x0 },
+    { 0x41218168 , 0x0 },
+    { 0x41218170 , 0x0 },
+    { 0x41218174 , 0x0 },
+    { 0x41218178 , 0x0 },
+    { 0x41218180 , 0x0 },
+    { 0x41218184 , 0x0 },
+    { 0x41218188 , 0x0 },
+    { 0x41218190 , 0x0 },
+    { 0x41218194 , 0x0 },
+    { 0x41218198 , 0x0 },
+    { 0x412181a0 , 0x0 },
+    { 0x412181a4 , 0x0 },
+    { 0x412181a8 , 0x0 },
+    { 0x412181b0 , 0x0 },
+    { 0x412181b4 , 0x0 },
+    { 0x412181b8 , 0x0 },
+    { 0x412181c0 , 0x0 },
+    { 0x412181c4 , 0x0 },
+    { 0x412181c8 , 0x0 },
+    { 0x412181d0 , 0x0 },
+    { 0x412181d4 , 0x0 },
+    { 0x412181d8 , 0x0 },
+    { 0x412181e0 , 0x0 },
+    { 0x412181e4 , 0x0 },
+    { 0x412181e8 , 0x0 },
+    { 0x412181f0 , 0x0 },
+    { 0x412181f4 , 0x0 },
+    { 0x412181f8 , 0x0 },
+    { 0x41218200 , 0x0 },
+    { 0x41218204 , 0x0 },
+    { 0x41218208 , 0x0 },
+    { 0x41218210 , 0x0 },
+    { 0x41218214 , 0x0 },
+    { 0x41218218 , 0x0 },
+    { 0x41218220 , 0x0 },
+    { 0x41218224 , 0x0 },
+    { 0x41218228 , 0x0 },
+    { 0x41218230 , 0x0 },
+    { 0x41218234 , 0x0 },
+    { 0x41218238 , 0x0 },
+    { 0x41218240 , 0x0 },
+    { 0x41218244 , 0x0 },
+    { 0x41218248 , 0x0 },
+    { 0x41218250 , 0x0 },
+    { 0x41218254 , 0x0 },
+    { 0x41218258 , 0x0 },
+    { 0x41218260 , 0x0 },
+    { 0x41218264 , 0x0 },
+    { 0x41218268 , 0x0 },
+    { 0x41218270 , 0x0 },
+    { 0x41218274 , 0x0 },
+    { 0x41218278 , 0x0 },
+    { 0x41218280 , 0x0 },
+    { 0x41218284 , 0x0 },
+    { 0x41218288 , 0x0 },
+    { 0x41218290 , 0x0 },
+    { 0x41218294 , 0x0 },
+    { 0x41218298 , 0x0 },
+    { 0x412182a0 , 0x0 },
+    { 0x412182a4 , 0x0 },
+    { 0x412182a8 , 0x0 },
+    { 0x412182b0 , 0x0 },
+    { 0x412182b4 , 0x0 },
+    { 0x412182b8 , 0x0 },
+    { 0x412182c0 , 0x0 },
+    { 0x412182c4 , 0x0 },
+    { 0x412182c8 , 0x0 },
+    { 0x412182d0 , 0x0 },
+    { 0x412182d4 , 0x0 },
+    { 0x412182d8 , 0x0 },
+    { 0x412182e0 , 0x0 },
+    { 0x412182e4 , 0x0 },
+    { 0x412182e8 , 0x0 },
+    { 0x412182f0 , 0x0 },
+    { 0x412182f4 , 0x0 },
+    { 0x412182f8 , 0x0 },
+    { 0x41218300 , 0x0 },
+    { 0x41218304 , 0x0 },
+    { 0x41218308 , 0x0 },
+    { 0x41218310 , 0x0 },
+    { 0x41218314 , 0x0 },
+    { 0x41218318 , 0x0 },
+    { 0x41218320 , 0x0 },
+    { 0x41218324 , 0x0 },
+    { 0x41218328 , 0x0 },
+    { 0x41218330 , 0x0 },
+    { 0x41218334 , 0x0 },
+    { 0x41218338 , 0x0 },
+    { 0x41218340 , 0x0 },
+    { 0x41218344 , 0x0 },
+    { 0x41218348 , 0x0 },
+    { 0x41218350 , 0x0 },
+    { 0x41218354 , 0x0 },
+    { 0x41218358 , 0x0 },
+    { 0x41218360 , 0x0 },
+    { 0x41218364 , 0x0 },
+    { 0x41218368 , 0x0 },
+    { 0x41218370 , 0x0 },
+    { 0x41218374 , 0x0 },
+    { 0x41218378 , 0x0 },
+    { 0x41218380 , 0x0 },
+    { 0x41218384 , 0x0 },
+    { 0x41218388 , 0x0 },
+    { 0x41218390 , 0x0 },
+    { 0x41218394 , 0x0 },
+    { 0x41218398 , 0x0 },
+    { 0x412183a0 , 0x0 },
+    { 0x412183a4 , 0x0 },
+    { 0x412183a8 , 0x0 },
+    { 0x412183b0 , 0x0 },
+    { 0x412183b4 , 0x0 },
+    { 0x412183b8 , 0x0 },
+    { 0x412183c0 , 0x0 },
+    { 0x412183c4 , 0x0 },
+    { 0x412183c8 , 0x0 },
+    { 0x412183d0 , 0x0 },
+    { 0x412183d4 , 0x0 },
+    { 0x412183d8 , 0x0 },
+    { 0x412183e0 , 0x0 },
+    { 0x412183e4 , 0x0 },
+    { 0x412183e8 , 0x0 },
+    { 0x412183f0 , 0x0 },
+    { 0x412183f4 , 0x0 },
+    { 0x412183f8 , 0x0 },
+    { 0x41218400 , 0x0 },
+    { 0x41218404 , 0x0 },
+    { 0x41218408 , 0x0 },
+    { 0x41218410 , 0x0 },
+    { 0x41218414 , 0x0 },
+    { 0x41218418 , 0x0 },
+    { 0x41218420 , 0x0 },
+    { 0x41218424 , 0x0 },
+    { 0x41218428 , 0x0 },
+    { 0x41218430 , 0x0 },
+    { 0x41218434 , 0x0 },
+    { 0x41218438 , 0x0 },
+    { 0x41218440 , 0x0 },
+    { 0x41218444 , 0x0 },
+    { 0x41218448 , 0x0 },
+    { 0x41218450 , 0x0 },
+    { 0x41218454 , 0x0 },
+    { 0x41218458 , 0x0 },
+    { 0x41218460 , 0x0 },
+    { 0x41218464 , 0x0 },
+    { 0x41218468 , 0x0 },
+    { 0x41218470 , 0x0 },
+    { 0x41218474 , 0x0 },
+    { 0x41218478 , 0x0 },
+    { 0x41218480 , 0x0 },
+    { 0x41218484 , 0x0 },
+    { 0x41218488 , 0x0 },
+    { 0x41218490 , 0x0 },
+    { 0x41218494 , 0x0 },
+    { 0x41218498 , 0x0 },
+    { 0x412184a0 , 0x0 },
+    { 0x412184a4 , 0x0 },
+    { 0x412184a8 , 0x0 },
+    { 0x412184b0 , 0x0 },
+    { 0x412184b4 , 0x0 },
+    { 0x412184b8 , 0x0 },
+    { 0x412184c0 , 0x0 },
+    { 0x412184c4 , 0x0 },
+    { 0x412184c8 , 0x0 },
+    { 0x412184d0 , 0x0 },
+    { 0x412184d4 , 0x0 },
+    { 0x412184d8 , 0x0 },
+    { 0x412184e0 , 0x0 },
+    { 0x412184e4 , 0x0 },
+    { 0x412184e8 , 0x0 },
+    { 0x412184f0 , 0x0 },
+    { 0x412184f4 , 0x0 },
+    { 0x412184f8 , 0x0 },
+    { 0x41218500 , 0x0 },
+    { 0x41218504 , 0x0 },
+    { 0x41218508 , 0x0 },
+    { 0x41218510 , 0x0 },
+    { 0x41218514 , 0x0 },
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+    { 0x40d2cc68 , 0x84 },
+    { 0x40d2cc88 , 0x2221 },
+    { 0x40d2cc2c , 0xc },
+    { 0x40d2cc4c , 0x203 },
+    { 0x40d2cc6c , 0x84 },
+    { 0x40d2cc8c , 0x2423 },
+    { 0x40d2cc30 , 0xc },
+    { 0x40d2cc50 , 0x203 },
+    { 0x40d2cc70 , 0x84 },
+    { 0x40d2cc90 , 0x2827 },
+    { 0x40d2d0d4 , 0x8 },
+    { 0x40d2d004 , 0x5 },
+    { 0x40d2d024 , 0xa },
+    { 0x40d2d044 , 0x203 },
+    { 0x40d2d064 , 0x84 },
+    { 0x40d2d084 , 0x2625 },
+    { 0x40d2d008 , 0x5 },
+    { 0x40d2d028 , 0xa },
+    { 0x40d2d048 , 0x203 },
+    { 0x40d2d068 , 0x84 },
+    { 0x40d2d088 , 0x2a29 },
+    { 0x40d2d00c , 0x5 },
+    { 0x40d2d02c , 0xa },
+    { 0x40d2d04c , 0x203 },
+    { 0x40d2d06c , 0x84 },
+    { 0x40d2d08c , 0x2c2b },
+    { 0x40d2d010 , 0x5 },
+    { 0x40d2d030 , 0xa },
+    { 0x40d2d050 , 0x203 },
+    { 0x40d2d070 , 0x84 },
+    { 0x40d2d090 , 0x3433 },
+    { 0x40d2d014 , 0xc },
+    { 0x40d2d034 , 0x18 },
+    { 0x40d2d054 , 0x608 },
+    { 0x40d2d074 , 0x84 },
+    { 0x40d2d094 , 0x2e2d },
+    { 0x40d2d4d4 , 0x8 },
+    { 0x40d2d404 , 0xe },
+    { 0x40d2d424 , 0x1c },
+    { 0x40d2d444 , 0x608 },
+    { 0x40d2d464 , 0x84 },
+    { 0x40d2d484 , 0x201f },
+    { 0x40d2d408 , 0x6 },
+    { 0x40d2d428 , 0xc },
+    { 0x40d2d448 , 0x203 },
+    { 0x40d2d468 , 0x84 },
+    { 0x40d2d488 , 0x2221 },
+    { 0x40d2d40c , 0x6 },
+    { 0x40d2d42c , 0xc },
+    { 0x40d2d44c , 0x203 },
+    { 0x40d2d46c , 0x84 },
+    { 0x40d2d48c , 0x2423 },
+    { 0x40d2d410 , 0x6 },
+    { 0x40d2d430 , 0xc },
+    { 0x40d2d450 , 0x203 },
+    { 0x40d2d470 , 0x84 },
+    { 0x40d2d490 , 0x2827 },
+    { 0x40d20080 , 0xff3ff3ff },
+    { 0x40d20100 , 0xff3ff3ff },
+    { 0x40d20084 , 0xff3ff3ff },
+    { 0x40d20104 , 0xff3ff3ff },
+    { 0x40d20088 , 0xff3ff3ff },
+    { 0x40d20108 , 0xff3ff3ff },
+    { 0x40d2008c , 0xff3ff3ff },
+    { 0x40d2010c , 0xff3ff3ff },
+    { 0x40d20090 , 0xff3ff3ff },
+    { 0x40d20110 , 0xff3ff3ff },
+    { 0x40d20094 , 0xff3ff3ff },
+    { 0x40d20114 , 0xff3ff3ff },
+    { 0x40d20098 , 0xff3ff3ff },
+    { 0x40d20118 , 0xff3ff3ff },
+    { 0x40d2009c , 0xff3ff3ff },
+    { 0x40d2011c , 0xff3ff3ff },
+    { 0x40d200a0 , 0xff3ff3ff },
+    { 0x40d20120 , 0xff3ff3ff },
+    { 0x40d200a4 , 0xff3ff3ff },
+    { 0x40d20124 , 0xff3ff3ff },
+    { 0x40d200a8 , 0xff3ff3ff },
+    { 0x40d20128 , 0xff3ff3ff },
+    { 0x40d200ac , 0xff3ff3ff },
+    { 0x40d2012c , 0xff3ff3ff },
+    { 0x40d200b0 , 0xff3ff3ff },
+    { 0x40d20130 , 0xff3ff3ff },
+    { 0x40d200b4 , 0xff3ff3ff },
+    { 0x40d20134 , 0xff3ff3ff },
+    { 0x40d200b8 , 0xff3ff3ff },
+    { 0x40d20138 , 0xff3ff3ff },
+    { 0x40d200bc , 0xff3ff3ff },
+    { 0x40d2013c , 0xff3ff3ff },
+    { 0x40d200c0 , 0xff3ff3ff },
+    { 0x40d20140 , 0xff3ff3ff },
+    { 0x40d200c4 , 0xff3ff3ff },
+    { 0x40d20144 , 0xff3ff3ff },
+    { 0x40d200c8 , 0xff3ff3ff },
+    { 0x40d20148 , 0xff3ff3ff },
+    { 0x40d200cc , 0xff3ff3ff },
+    { 0x40d2014c , 0xff3ff3ff },
+    { 0x40d200d0 , 0xff3ff3ff },
+    { 0x40d20150 , 0xff3ff3ff },
+    { 0x40d200d4 , 0xff3ff3ff },
+    { 0x40d20154 , 0xff3ff3ff },
+    { 0x40d200d8 , 0xff3ff3ff },
+    { 0x40d20158 , 0xff3ff3ff },
+    { 0x40d200dc , 0xff3ff3ff },
+    { 0x40d2015c , 0xff3ff3ff },
+    { 0x40d200e0 , 0xff3ff3ff },
+    { 0x40d20160 , 0xff3ff3ff },
+    { 0x40d200e4 , 0xff3ff3ff },
+    { 0x40d20164 , 0xff3ff3ff },
+    { 0x40d200e8 , 0xff3ff3ff },
+    { 0x40d20168 , 0xff3ff3ff },
+    { 0x40d200ec , 0xff3ff3ff },
+    { 0x40d2016c , 0xff3ff3ff },
+    { 0x40d200f0 , 0xff3ff3ff },
+    { 0x40d20170 , 0xff3ff3ff },
+    { 0x40d200f4 , 0xff3ff3ff },
+    { 0x40d20174 , 0xff3ff3ff },
+    { 0x40d200f8 , 0xff3ff3ff },
+    { 0x40d20178 , 0xff3ff3ff },
+    { 0x40d200fc , 0xff3ff3ff },
+    { 0x40d2017c , 0xff3ff3ff },
+    { 0x40d20180 , 0xff3ff3ff },
+    { 0x40d20184 , 0xa1c2162 },
+    { 0x40d23000 , 0x4 },
+    { 0x40d23004 , 0x8 },
+    { 0x40d23008 , 0xc },
+    { 0x40d2300c , 0x10 },
+    { 0x40d23010 , 0x14 },
+    { 0x40d23014 , 0x18 },
+    { 0x40d23018 , 0x1c },
+    { 0x40d2301c , 0x20 },
+    { 0x40d23020 , 0x24 },
+    { 0x40d23024 , 0x28 },
+    { 0x40d23028 , 0x2c },
+    { 0x40d2302c , 0x30 },
+    { 0x40d23030 , 0x34 },
+    { 0x40d23034 , 0x38 },
+    { 0x40d23038 , 0x3c },
+    { 0x40d2303c , 0x40 },
+    { 0x40d23040 , 0x44 },
+    { 0x40d23044 , 0x48 },
+    { 0x40d23048 , 0x4c },
+    { 0x40d2304c , 0x50 },
+    { 0x40d23050 , 0x54 },
+    { 0x40d23054 , 0x58 },
+    { 0x40d23058 , 0x5c },
+    { 0x40d2305c , 0x60 },
+    { 0x40d23060 , 0x64 },
+    { 0x40d23064 , 0x68 },
+    { 0x40d23068 , 0x6c },
+    { 0x40d2306c , 0x70 },
+    { 0x40d23070 , 0x74 },
+    { 0x40d23074 , 0x78 },
+    { 0x40d23078 , 0x7c },
+    { 0x40d2307c , 0x80 },
+    { 0x40d23080 , 0x84 },
+    { 0x40d23084 , 0x88 },
+    { 0x40d23088 , 0x8c },
+    { 0x40d2308c , 0x90 },
+    { 0x40d23090 , 0x94 },
+    { 0x40d23094 , 0x98 },
+    { 0x40d23098 , 0x9c },
+    { 0x40d2309c , 0xa0 },
+    { 0x40d230a0 , 0xa4 },
+    { 0x40d230a4 , 0xa8 },
+    { 0x40d230a8 , 0xac },
+    { 0x40d230ac , 0xb0 },
+    { 0x40d230b0 , 0xb4 },
+    { 0x40d230b4 , 0xb8 },
+    { 0x40d230b8 , 0xbc },
+    { 0x40d230bc , 0xc0 },
+    { 0x40d230c0 , 0xc4 },
+    { 0x40d230c4 , 0xc8 },
+    { 0x40d230c8 , 0xcc },
+    { 0x40d230cc , 0xd0 },
+    { 0x40d230d0 , 0xd4 },
+    { 0x40d230d4 , 0xd8 },
+    { 0x40d230d8 , 0xdc },
+    { 0x40d230dc , 0xe0 },
+    { 0x40d230e0 , 0xe4 },
+    { 0x40d230e4 , 0xe8 },
+    { 0x40d230e8 , 0xec },
+    { 0x40d230ec , 0xf0 },
+    { 0x40d230f0 , 0xf4 },
+    { 0x40d230f4 , 0xf8 },
+    { 0x40d230f8 , 0xfc },
+    { 0x40d230fc , 0x100 },
+    { 0x40d23100 , 0x104 },
+    { 0x40d23104 , 0x108 },
+    { 0x40d23108 , 0x10c },
+    { 0x40d2310c , 0x110 },
+    { 0x40d23110 , 0x114 },
+    { 0x40d23114 , 0x118 },
+    { 0x40d23118 , 0x11c },
+    { 0x40d2311c , 0x120 },
+    { 0x40d23120 , 0x124 },
+    { 0x40d23124 , 0x128 },
+    { 0x40d23128 , 0x12c },
+    { 0x40d2312c , 0x130 },
+    { 0x40d23130 , 0x134 },
+    { 0x40d23134 , 0x138 },
+    { 0x40d23138 , 0x13c },
+    { 0x40d2313c , 0x140 },
+    { 0x40d23140 , 0x144 },
+    { 0x40d23144 , 0x148 },
+    { 0x40d23148 , 0x14c },
+    { 0x40d2314c , 0x150 },
+    { 0x40d23150 , 0x154 },
+    { 0x40d23154 , 0x158 },
+    { 0x40d23158 , 0x15c },
+    { 0x40d2315c , 0x160 },
+    { 0x40d23160 , 0x164 },
+    { 0x40d23164 , 0x168 },
+    { 0x40d23168 , 0x16c },
+    { 0x40d2316c , 0x170 },
+    { 0x40d23170 , 0x174 },
+    { 0x40d23174 , 0x178 },
+    { 0x40d23178 , 0x17c },
+    { 0x40d2317c , 0x180 },
+    { 0x40d23180 , 0x184 },
+    { 0x40d23184 , 0x188 },
+    { 0x40d23188 , 0x18c },
+    { 0x40d2318c , 0x190 },
+    { 0x40d23190 , 0x194 },
+    { 0x40d23194 , 0x198 },
+    { 0x40d23198 , 0x19c },
+    { 0x40d2319c , 0x1a0 },
+    { 0x40d231a0 , 0x1a4 },
+    { 0x40d231a4 , 0x1a8 },
+    { 0x40d231a8 , 0x1ac },
+    { 0x40d231ac , 0x1b0 },
+    { 0x40d231b0 , 0x1b4 },
+    { 0x40d231b4 , 0x1b8 },
+    { 0x40d231b8 , 0x1bc },
+    { 0x40d231bc , 0x1c0 },
+    { 0x40d231c0 , 0x1c4 },
+    { 0x40d231c4 , 0x1c8 },
+    { 0x40d231c8 , 0x1cc },
+    { 0x40d231cc , 0x1d0 },
+    { 0x40d231d0 , 0x1d4 },
+    { 0x40d231d4 , 0x1d8 },
+    { 0x40d231d8 , 0x1dc },
+    { 0x40d231dc , 0x1e0 },
+    { 0x40d231e0 , 0x1e4 },
+    { 0x40d231e4 , 0x1e8 },
+    { 0x40d231e8 , 0x1ec },
+    { 0x40d231ec , 0x1f0 },
+    { 0x40d231f0 , 0x1f4 },
+    { 0x40d231f4 , 0x1f8 },
+    { 0x40d231f8 , 0x1fc },
+    { 0x40d231fc , 0x200 },
+    { 0x40d23200 , 0x204 },
+    { 0x40d23204 , 0x208 },
+    { 0x40d23208 , 0x20c },
+    { 0x40d2320c , 0x210 },
+    { 0x40d23210 , 0x214 },
+    { 0x40d23214 , 0x218 },
+    { 0x40d23218 , 0x21c },
+    { 0x40d2321c , 0x220 },
+    { 0x40d23220 , 0x224 },
+    { 0x40d23224 , 0x228 },
+    { 0x40d23228 , 0x22c },
+    { 0x40d2322c , 0x230 },
+    { 0x40d23230 , 0x234 },
+    { 0x40d23234 , 0x238 },
+    { 0x40d23238 , 0x23c },
+    { 0x40d2323c , 0x240 },
+    { 0x40d23240 , 0x244 },
+    { 0x40d23244 , 0x248 },
+    { 0x40d23248 , 0x24c },
+    { 0x40d2324c , 0x250 },
+    { 0x40d23250 , 0x254 },
+    { 0x40d23254 , 0x258 },
+    { 0x40d23258 , 0x25c },
+    { 0x40d2325c , 0x260 },
+    { 0x40d23260 , 0x264 },
+    { 0x40d23264 , 0x268 },
+    { 0x40d23268 , 0x26c },
+    { 0x40d2326c , 0x270 },
+    { 0x40d23270 , 0x274 },
+    { 0x40d23274 , 0x278 },
+    { 0x40d23278 , 0x27c },
+    { 0x40d2327c , 0x280 },
+    { 0x40d23280 , 0x284 },
+    { 0x40d23284 , 0x288 },
+    { 0x40d23288 , 0x28c },
+    { 0x40d2328c , 0x290 },
+    { 0x40d23290 , 0x294 },
+    { 0x40d23294 , 0x298 },
+    { 0x40d23298 , 0x29c },
+    { 0x40d2329c , 0x2a0 },
+    { 0x40d232a0 , 0x2a4 },
+    { 0x40d232a4 , 0x2a8 },
+    { 0x40d232a8 , 0x2ac },
+    { 0x40d232ac , 0x2b0 },
+    { 0x40d232b0 , 0x2b4 },
+    { 0x40d232b4 , 0x2b8 },
+    { 0x40d232b8 , 0x2bc },
+    { 0x40d232bc , 0x2c0 },
+    { 0x40d232c0 , 0x2c4 },
+    { 0x40d232c4 , 0x2c8 },
+    { 0x40d232c8 , 0x2cc },
+    { 0x40d232cc , 0x2d0 },
+    { 0x40d232d0 , 0x2d4 },
+    { 0x40d232d4 , 0x2d8 },
+    { 0x40d232d8 , 0x2dc },
+    { 0x40d232dc , 0x2e0 },
+    { 0x40d232e0 , 0x2e4 },
+    { 0x40d232e4 , 0x2e8 },
+    { 0x40d232e8 , 0x2ec },
+    { 0x40d232ec , 0x2f0 },
+    { 0x40d232f0 , 0x2f4 },
+    { 0x40d232f4 , 0x2f8 },
+    { 0x40d232f8 , 0x2fc },
+    { 0x40d232fc , 0x300 },
+    { 0x40d23300 , 0x304 },
+    { 0x40d23304 , 0x308 },
+    { 0x40d23308 , 0x30c },
+    { 0x40d2330c , 0x310 },
+    { 0x40d23310 , 0x314 },
+    { 0x40d23314 , 0x318 },
+    { 0x40d23318 , 0x31c },
+    { 0x40d2331c , 0x320 },
+    { 0x40d23320 , 0x324 },
+    { 0x40d23324 , 0x328 },
+    { 0x40d23328 , 0x32c },
+    { 0x40d2332c , 0x330 },
+    { 0x40d23330 , 0x334 },
+    { 0x40d23334 , 0x338 },
+    { 0x40d23338 , 0x33c },
+    { 0x40d2333c , 0x340 },
+    { 0x40d23340 , 0x344 },
+    { 0x40d23344 , 0x348 },
+    { 0x40d23348 , 0x34c },
+    { 0x40d2334c , 0x350 },
+    { 0x40d23350 , 0x354 },
+    { 0x40d23354 , 0x358 },
+    { 0x40d23358 , 0x35c },
+    { 0x40d2335c , 0x360 },
+    { 0x40d23360 , 0x364 },
+    { 0x40d23364 , 0x368 },
+    { 0x40d23368 , 0x36c },
+    { 0x40d2336c , 0x370 },
+    { 0x40d23370 , 0x374 },
+    { 0x40d23374 , 0x378 },
+    { 0x40d23378 , 0x37c },
+    { 0x40d2337c , 0x380 },
+    { 0x40d23380 , 0x384 },
+    { 0x40d23384 , 0x388 },
+    { 0x40d23388 , 0x38c },
+    { 0x40d2338c , 0x390 },
+    { 0x40d23390 , 0x394 },
+    { 0x40d23394 , 0x398 },
+    { 0x40d23398 , 0x39c },
+    { 0x40d2339c , 0x3a0 },
+    { 0x40d233a0 , 0x3a4 },
+    { 0x40d233a4 , 0x3a8 },
+    { 0x40d233a8 , 0x3ac },
+    { 0x40d233ac , 0x3b0 },
+    { 0x40d233b0 , 0x3b4 },
+    { 0x40d233b4 , 0x3b8 },
+    { 0x40d233b8 , 0x3bc },
+    { 0x40d233bc , 0x3c0 },
+    { 0x40d233c0 , 0x3c4 },
+    { 0x40d233c4 , 0x3c8 },
+    { 0x40d233c8 , 0x3cc },
+    { 0x40d233cc , 0x3d0 },
+    { 0x40d233d0 , 0x3d4 },
+    { 0x40d233d4 , 0x3d8 },
+    { 0x40d233d8 , 0x3dc },
+    { 0x40d233dc , 0x3e0 },
+    { 0x40d233e0 , 0x3e4 },
+    { 0x40d233e4 , 0x3e8 },
+    { 0x40d233e8 , 0x3ec },
+    { 0x40d233ec , 0x3f0 },
+    { 0x40d233f0 , 0x3f4 },
+    { 0x40d233f4 , 0x3f8 },
+    { 0x40d233f8 , 0x3fc },
+    { 0x40d233fc , 0x400 },
+    { 0x40d23400 , 0x404 },
+    { 0x40d23404 , 0x408 },
+    { 0x40d23408 , 0x40c },
+    { 0x40d2340c , 0x410 },
+    { 0x40d23410 , 0x414 },
+    { 0x40d23414 , 0x418 },
+    { 0x40d23418 , 0x41c },
+    { 0x40d2341c , 0x420 },
+    { 0x40d23420 , 0x424 },
+    { 0x40d23424 , 0x428 },
+    { 0x40d23428 , 0x42c },
+    { 0x40d2342c , 0x430 },
+    { 0x40d23430 , 0x434 },
+    { 0x40d23434 , 0x438 },
+    { 0x40d23438 , 0x43c },
+    { 0x40d2343c , 0x440 },
+    { 0x40d23440 , 0x444 },
+    { 0x40d23444 , 0x448 },
+    { 0x40d23448 , 0x44c },
+    { 0x40d2344c , 0x450 },
+    { 0x40d23450 , 0x454 },
+    { 0x40d23454 , 0x458 },
+    { 0x40d23458 , 0x45c },
+    { 0x40d2345c , 0x460 },
+    { 0x40d23460 , 0x464 },
+    { 0x40d23464 , 0x468 },
+    { 0x40d23468 , 0x46c },
+    { 0x40d2346c , 0x470 },
+    { 0x40d23470 , 0x474 },
+    { 0x40d23474 , 0x478 },
+    { 0x40d23478 , 0x47c },
+    { 0x40d2347c , 0x480 },
+    { 0x40d23480 , 0x484 },
+    { 0x40d23484 , 0x488 },
+    { 0x40d23488 , 0x48c },
+    { 0x40d2348c , 0x490 },
+    { 0x40d23490 , 0x494 },
+    { 0x40d23494 , 0x498 },
+    { 0x40d23498 , 0x49c },
+    { 0x40d2349c , 0x4a0 },
+    { 0x40d234a0 , 0x4a4 },
+    { 0x40d234a4 , 0x4a8 },
+    { 0x40d234a8 , 0x4ac },
+    { 0x40d234ac , 0x4b0 },
+    { 0x40d234b0 , 0x4b4 },
+    { 0x40d234b4 , 0x4b8 },
+    { 0x40d234b8 , 0x4bc },
+    { 0x40d234bc , 0x4c0 },
+    { 0x40d234c0 , 0x4c4 },
+    { 0x40d234c4 , 0x4c8 },
+    { 0x40d234c8 , 0x4cc },
+    { 0x40d234cc , 0x4d0 },
+    { 0x40d234d0 , 0x4d4 },
+    { 0x40d234d4 , 0x4d8 },
+    { 0x40d234d8 , 0x4dc },
+    { 0x40d234dc , 0x4e0 },
+    { 0x40d234e0 , 0x4e4 },
+    { 0x40d234e4 , 0x4e8 },
+    { 0x40d234e8 , 0x4ec },
+    { 0x40d234ec , 0x4f0 },
+    { 0x40d234f0 , 0x4f4 },
+    { 0x40d234f4 , 0x4f8 },
+    { 0x40d234f8 , 0x4fc },
+    { 0x40d234fc , 0x500 },
+    { 0x40d23500 , 0x504 },
+    { 0x40d23504 , 0x508 },
+    { 0x40d23508 , 0x50c },
+    { 0x40d2350c , 0x510 },
+    { 0x40d23510 , 0x514 },
+    { 0x40d23514 , 0x518 },
+    { 0x40d23518 , 0x51c },
+    { 0x40d2351c , 0x520 },
+    { 0x40d23520 , 0x524 },
+    { 0x40d23524 , 0x528 },
+    { 0x40d23528 , 0x52c },
+    { 0x40d2352c , 0x530 },
+    { 0x40d23530 , 0x534 },
+    { 0x40d23534 , 0x538 },
+    { 0x40d23538 , 0x53c },
+    { 0x40d2353c , 0x540 },
+    { 0x40d23540 , 0x544 },
+    { 0x40d23544 , 0x548 },
+    { 0x40d23548 , 0x54c },
+    { 0x40d2354c , 0x550 },
+    { 0x40d23550 , 0x554 },
+    { 0x40d23554 , 0x558 },
+    { 0x40d23558 , 0x55c },
+    { 0x40d2355c , 0x560 },
+    { 0x40d23560 , 0x564 },
+    { 0x40d23564 , 0x568 },
+    { 0x40d23568 , 0x56c },
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+    { 0x40d23660 , 0x664 },
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+    { 0x40d23670 , 0x674 },
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+    { 0x40d23680 , 0x684 },
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+    { 0x40d2368c , 0x690 },
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+    { 0x40d23698 , 0x69c },
+    { 0x40d2369c , 0x6a0 },
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+    { 0x40d23708 , 0x70c },
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+    { 0x40d23710 , 0x714 },
+    { 0x40d23714 , 0x718 },
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+    { 0x40d2371c , 0x720 },
+    { 0x40d23720 , 0x724 },
+    { 0x40d23724 , 0x728 },
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+    { 0x40d2372c , 0x730 },
+    { 0x40d23730 , 0x734 },
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+    { 0x40d2373c , 0x740 },
+    { 0x40d23740 , 0x744 },
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+    { 0x40d2374c , 0x750 },
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+    { 0x40d2375c , 0x760 },
+    { 0x40d23760 , 0x764 },
+    { 0x40d23764 , 0x768 },
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+    { 0x40d2376c , 0x770 },
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+    { 0x40d2377c , 0x780 },
+    { 0x40d23780 , 0x784 },
+    { 0x40d23784 , 0x788 },
+    { 0x40d23788 , 0x78c },
+    { 0x40d2378c , 0x790 },
+    { 0x40d23790 , 0x794 },
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+    { 0x40d2379c , 0x7a0 },
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+    { 0x40d23860 , 0x864 },
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+    { 0x40d23870 , 0x874 },
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+    { 0x40d23884 , 0x888 },
+    { 0x40d23888 , 0x88c },
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+    { 0x40d23894 , 0x898 },
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+    { 0x40d2393c , 0x940 },
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+    { 0x40d2396c , 0x970 },
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+    { 0x40d23cac , 0xcb0 },
+    { 0x40d23cb0 , 0xcb4 },
+    { 0x40d23cb4 , 0xcb8 },
+    { 0x40d23cb8 , 0xcbc },
+    { 0x40d23cbc , 0xcc0 },
+    { 0x40d23cc0 , 0xcc4 },
+    { 0x40d23cc4 , 0xcc8 },
+    { 0x40d23cc8 , 0xccc },
+    { 0x40d23ccc , 0xcd0 },
+    { 0x40d23cd0 , 0xcd4 },
+    { 0x40d23cd4 , 0xcd8 },
+    { 0x40d23cd8 , 0xcdc },
+    { 0x40d23cdc , 0xce0 },
+    { 0x40d23ce0 , 0xce4 },
+    { 0x40d23ce4 , 0xce8 },
+    { 0x40d23ce8 , 0xcec },
+    { 0x40d23cec , 0xcf0 },
+    { 0x40d23cf0 , 0xcf4 },
+    { 0x40d23cf4 , 0xcf8 },
+    { 0x40d23cf8 , 0xcfc },
+    { 0x40d23cfc , 0xd00 },
+    { 0x40d23d00 , 0xd04 },
+    { 0x40d23d04 , 0xd08 },
+    { 0x40d23d08 , 0xd0c },
+    { 0x40d23d0c , 0xd10 },
+    { 0x40d23d10 , 0xd14 },
+    { 0x40d23d14 , 0xd18 },
+    { 0x40d23d18 , 0xd1c },
+    { 0x40d23d1c , 0xd20 },
+    { 0x40d23d20 , 0xd24 },
+    { 0x40d23d24 , 0xd28 },
+    { 0x40d23d28 , 0xd2c },
+    { 0x40d23d2c , 0xd30 },
+    { 0x40d23d30 , 0xd34 },
+    { 0x40d23d34 , 0xd38 },
+    { 0x40d23d38 , 0xd3c },
+    { 0x40d23d3c , 0xd40 },
+    { 0x40d23d40 , 0xd44 },
+    { 0x40d23d44 , 0xd48 },
+    { 0x40d23d48 , 0xd4c },
+    { 0x40d23d4c , 0xd50 },
+    { 0x40d23d50 , 0xd54 },
+    { 0x40d23d54 , 0xd58 },
+    { 0x40d23d58 , 0xd5c },
+    { 0x40d23d5c , 0xd60 },
+    { 0x40d23d60 , 0xd64 },
+    { 0x40d23d64 , 0xd68 },
+    { 0x40d23d68 , 0xd6c },
+    { 0x40d23d6c , 0xd70 },
+    { 0x40d23d70 , 0xd74 },
+    { 0x40d23d74 , 0xd78 },
+    { 0x40d23d78 , 0xd7c },
+    { 0x40d23d7c , 0xd80 },
+    { 0x40d23d80 , 0xd84 },
+    { 0x40d23d84 , 0xd88 },
+    { 0x40d23d88 , 0xd8c },
+    { 0x40d23d8c , 0xd90 },
+    { 0x40d23d90 , 0xd94 },
+    { 0x40d23d94 , 0xd98 },
+    { 0x40d23d98 , 0xd9c },
+    { 0x40d23d9c , 0xda0 },
+    { 0x40d23da0 , 0xda4 },
+    { 0x40d23da4 , 0xda8 },
+    { 0x40d23da8 , 0xdac },
+    { 0x40d23dac , 0xdb0 },
+    { 0x40d23db0 , 0xdb4 },
+    { 0x40d23db4 , 0xdb8 },
+    { 0x40d23db8 , 0xdbc },
+    { 0x40d23dbc , 0xdc0 },
+    { 0x40d23dc0 , 0xdc4 },
+    { 0x40d23dc4 , 0xdc8 },
+    { 0x40d23dc8 , 0xdcc },
+    { 0x40d23dcc , 0xdd0 },
+    { 0x40d23dd0 , 0xdd4 },
+    { 0x40d23dd4 , 0xdd8 },
+    { 0x40d23dd8 , 0xddc },
+    { 0x40d23ddc , 0xde0 },
+    { 0x40d23de0 , 0xde4 },
+    { 0x40d23de4 , 0xde8 },
+    { 0x40d23de8 , 0xdec },
+    { 0x40d23dec , 0xdf0 },
+    { 0x40d23df0 , 0xdf4 },
+    { 0x40d23df4 , 0xdf8 },
+    { 0x40d23df8 , 0xdfc },
+    { 0x40d23dfc , 0xe00 },
+    { 0x40d23e00 , 0xe04 },
+    { 0x40d23e04 , 0xe08 },
+    { 0x40d23e08 , 0xe0c },
+    { 0x40d23e0c , 0xe10 },
+    { 0x40d23e10 , 0xe14 },
+    { 0x40d23e14 , 0xe18 },
+    { 0x40d23e18 , 0xe1c },
+    { 0x40d23e1c , 0xe20 },
+    { 0x40d23e20 , 0xe24 },
+    { 0x40d23e24 , 0xe28 },
+    { 0x40d23e28 , 0xe2c },
+    { 0x40d23e2c , 0xe30 },
+    { 0x40d23e30 , 0xe34 },
+    { 0x40d23e34 , 0xe38 },
+    { 0x40d23e38 , 0xe3c },
+    { 0x40d23e3c , 0xe40 },
+    { 0x40d23e40 , 0xe44 },
+    { 0x40d23e44 , 0xe48 },
+    { 0x40d23e48 , 0xe4c },
+    { 0x40d23e4c , 0xe50 },
+    { 0x40d23e50 , 0xe54 },
+    { 0x40d23e54 , 0xe58 },
+    { 0x40d23e58 , 0xe5c },
+    { 0x40d23e5c , 0xe60 },
+    { 0x40d23e60 , 0xe64 },
+    { 0x40d23e64 , 0xe68 },
+    { 0x40d23e68 , 0xe6c },
+    { 0x40d23e6c , 0xe70 },
+    { 0x40d23e70 , 0xe74 },
+    { 0x40d23e74 , 0xe78 },
+    { 0x40d23e78 , 0xe7c },
+    { 0x40d23e7c , 0xe80 },
+    { 0x40d23e80 , 0xe84 },
+    { 0x40d23e84 , 0xe88 },
+    { 0x40d23e88 , 0xe8c },
+    { 0x40d23e8c , 0xe90 },
+    { 0x40d23e90 , 0xe94 },
+    { 0x40d23e94 , 0xe98 },
+    { 0x40d23e98 , 0xe9c },
+    { 0x40d23e9c , 0xea0 },
+    { 0x40d23ea0 , 0xea4 },
+    { 0x40d23ea4 , 0xea8 },
+    { 0x40d23ea8 , 0xeac },
+    { 0x40d23eac , 0xeb0 },
+    { 0x40d23eb0 , 0xeb4 },
+    { 0x40d23eb4 , 0xeb8 },
+    { 0x40d23eb8 , 0xebc },
+    { 0x40d23ebc , 0xec0 },
+    { 0x40d23ec0 , 0xec4 },
+    { 0x40d23ec4 , 0xec8 },
+    { 0x40d23ec8 , 0xecc },
+    { 0x40d23ecc , 0xed0 },
+    { 0x40d23ed0 , 0xed4 },
+    { 0x40d23ed4 , 0xed8 },
+    { 0x40d23ed8 , 0xedc },
+    { 0x40d23edc , 0xee0 },
+    { 0x40d23ee0 , 0xee4 },
+    { 0x40d23ee4 , 0xee8 },
+    { 0x40d23ee8 , 0xeec },
+    { 0x40d23eec , 0xef0 },
+    { 0x40d23ef0 , 0xef4 },
+    { 0x40d23ef4 , 0xef8 },
+    { 0x40d23ef8 , 0xefc },
+    { 0x40d23efc , 0xf00 },
+    { 0x40d23f00 , 0xf04 },
+    { 0x40d23f04 , 0xf08 },
+    { 0x40d23f08 , 0xf0c },
+    { 0x40d23f0c , 0xf10 },
+    { 0x40d23f10 , 0xf14 },
+    { 0x40d23f14 , 0xf18 },
+    { 0x40d23f18 , 0xf1c },
+    { 0x40d23f1c , 0xf20 },
+    { 0x40d23f20 , 0xf24 },
+    { 0x40d23f24 , 0xf28 },
+    { 0x40d23f28 , 0xf2c },
+    { 0x40d23f2c , 0xf30 },
+    { 0x40d23f30 , 0xf34 },
+    { 0x40d23f34 , 0xf38 },
+    { 0x40d23f38 , 0xf3c },
+    { 0x40d23f3c , 0xf40 },
+    { 0x40d23f40 , 0xf44 },
+    { 0x40d23f44 , 0xf48 },
+    { 0x40d23f48 , 0xf4c },
+    { 0x40d23f4c , 0xf50 },
+    { 0x40d23f50 , 0xf54 },
+    { 0x40d23f54 , 0xf58 },
+    { 0x40d23f58 , 0xf5c },
+    { 0x40d23f5c , 0xf60 },
+    { 0x40d23f60 , 0xf64 },
+    { 0x40d23f64 , 0xf68 },
+    { 0x40d23f68 , 0xf6c },
+    { 0x40d23f6c , 0xf70 },
+    { 0x40d23f70 , 0xf74 },
+    { 0x40d23f74 , 0xf78 },
+    { 0x40d23f78 , 0xf7c },
+    { 0x40d23f7c , 0xf80 },
+    { 0x40d23f80 , 0xf84 },
+    { 0x40d23f84 , 0xf88 },
+    { 0x40d23f88 , 0xf8c },
+    { 0x40d23f8c , 0xf90 },
+    { 0x40d23f90 , 0xf94 },
+    { 0x40d23f94 , 0xf98 },
+    { 0x40d23f98 , 0xf9c },
+    { 0x40d23f9c , 0xfa0 },
+    { 0x40d23fa0 , 0xfa4 },
+    { 0x40d23fa4 , 0xfa8 },
+    { 0x40d23fa8 , 0xfac },
+    { 0x40d23fac , 0xfb0 },
+    { 0x40d23fb0 , 0xfb4 },
+    { 0x40d23fb4 , 0xfb8 },
+    { 0x40d23fb8 , 0xfbc },
+    { 0x40d23fbc , 0xfc0 },
+    { 0x40d23fc0 , 0xfc4 },
+    { 0x40d23fc4 , 0xfc8 },
+    { 0x40d23fc8 , 0xfcc },
+    { 0x40d23fcc , 0xfd0 },
+    { 0x40d23fd0 , 0xfd4 },
+    { 0x40d23fd4 , 0xfd8 },
+    { 0x40d23fd8 , 0xfdc },
+    { 0x40d23fdc , 0xfe0 },
+    { 0x40d23fe0 , 0xfe4 },
+    { 0x40d23fe4 , 0xfe8 },
+    { 0x40d23fe8 , 0xfec },
+    { 0x40d23fec , 0xff0 },
+    { 0x40d23ff0 , 0xff4 },
+    { 0x40d23ff4 , 0xff8 },
+    { 0x40d23ff8 , 0xffc },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d20080 , 0xff3ff3ff },
+    { 0x40d20100 , 0xff3ff3ff },
+    { 0x40d20400 , 0x20027 },
+    { 0x40d20620 , 0x1 },
+    { 0x40d20300 , 0x43c1 },
+    { 0x40d20380 , 0x400 },
+    { 0x40d22700 , 0x1 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x1 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d20084 , 0xff3ff3ff },
+    { 0x40d20104 , 0xff3ff3ff },
+    { 0x40d20404 , 0x20021 },
+    { 0x40d20620 , 0x3 },
+    { 0x40d20304 , 0x43c1 },
+    { 0x40d20384 , 0x400 },
+    { 0x40d22020 , 0x1 },
+    { 0x40d2202c , 0x1 },
+    { 0x40d22700 , 0x2 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x2 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d20088 , 0xff3ff3ff },
+    { 0x40d20108 , 0xff3ff3ff },
+    { 0x40d20408 , 0x20023 },
+    { 0x40d20620 , 0x7 },
+    { 0x40d20308 , 0x43c1 },
+    { 0x40d20388 , 0x400 },
+    { 0x40d22040 , 0x2 },
+    { 0x40d2204c , 0x2 },
+    { 0x40d22700 , 0x3 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x3 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d2008c , 0xff3ff3ff },
+    { 0x40d2010c , 0xff3ff3ff },
+    { 0x40d2040c , 0x20025 },
+    { 0x40d20620 , 0xf },
+    { 0x40d2030c , 0x43c1 },
+    { 0x40d2038c , 0x400 },
+    { 0x40d22060 , 0x3 },
+    { 0x40d2206c , 0x3 },
+    { 0x40d22700 , 0x4 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x4 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d20090 , 0xff3ff3ff },
+    { 0x40d20110 , 0xff3ff3ff },
+    { 0x40d20410 , 0x2001f },
+    { 0x40d20620 , 0x1f },
+    { 0x40d20310 , 0x43c1 },
+    { 0x40d20390 , 0x400 },
+    { 0x40d22080 , 0x4 },
+    { 0x40d2208c , 0x4 },
+    { 0x40d22700 , 0x5 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x5 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d20094 , 0xff3ff3ff },
+    { 0x40d20114 , 0xff3ff3ff },
+    { 0x40d20414 , 0x20029 },
+    { 0x40d20620 , 0x3f },
+    { 0x40d20314 , 0x43c1 },
+    { 0x40d20394 , 0x400 },
+    { 0x40d220a0 , 0x5 },
+    { 0x40d220ac , 0x5 },
+    { 0x40d22700 , 0x6 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x6 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d20098 , 0xff3ff3ff },
+    { 0x40d20118 , 0xff3ff3ff },
+    { 0x40d20418 , 0x2002b },
+    { 0x40d20620 , 0x7f },
+    { 0x40d20318 , 0x43c1 },
+    { 0x40d20398 , 0x400 },
+    { 0x40d220c0 , 0x6 },
+    { 0x40d220cc , 0x6 },
+    { 0x40d22700 , 0x7 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x7 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d2009c , 0xff3ff3ff },
+    { 0x40d2011c , 0xff3ff3ff },
+    { 0x40d2041c , 0x20033 },
+    { 0x40d20620 , 0xff },
+    { 0x40d2031c , 0x43c1 },
+    { 0x40d2039c , 0x400 },
+    { 0x40d220e0 , 0x7 },
+    { 0x40d220ec , 0x7 },
+    { 0x40d22700 , 0x8 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x8 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d200a0 , 0xff3ff3ff },
+    { 0x40d20120 , 0xff3ff3ff },
+    { 0x40d20420 , 0x2002d },
+    { 0x40d20620 , 0x1ff },
+    { 0x40d20320 , 0x43c1 },
+    { 0x40d203a0 , 0x400 },
+    { 0x40d22100 , 0x8 },
+    { 0x40d2210c , 0x8 },
+    { 0x40d22700 , 0x9 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x9 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d200a4 , 0xff3ff3ff },
+    { 0x40d20124 , 0xff3ff3ff },
+    { 0x40d20424 , 0x3001f },
+    { 0x40d20620 , 0x3ff },
+    { 0x40d20324 , 0x3c1 },
+    { 0x40d203a4 , 0x400 },
+    { 0x40d22120 , 0x9 },
+    { 0x40d2212c , 0x9 },
+    { 0x40d22700 , 0xa },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0xa },
+    { 0x40d20990 , 0x1f },
+    { 0x40d200a8 , 0xff3ff3ff },
+    { 0x40d20128 , 0xff3ff3ff },
+    { 0x40d20428 , 0x30021 },
+    { 0x40d20620 , 0x7ff },
+    { 0x40d20328 , 0x3c1 },
+    { 0x40d203a8 , 0x400 },
+    { 0x40d22140 , 0xa },
+    { 0x40d2214c , 0xa },
+    { 0x40d22700 , 0xb },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0xb },
+    { 0x40d20990 , 0x1f },
+    { 0x40d200ac , 0xff3ff3ff },
+    { 0x40d2012c , 0xff3ff3ff },
+    { 0x40d2042c , 0x30023 },
+    { 0x40d20620 , 0xfff },
+    { 0x40d2032c , 0x3c1 },
+    { 0x40d203ac , 0x400 },
+    { 0x40d22160 , 0xb },
+    { 0x40d2216c , 0xb },
+    { 0x40d22700 , 0xc },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0xc },
+    { 0x40d20990 , 0x1f },
+    { 0x40d200b0 , 0xff3ff3ff },
+    { 0x40d20130 , 0xff3ff3ff },
+    { 0x40d20430 , 0x101a0000 },
+    { 0x40d204c0 , 0x1000 },
+    { 0x40d20620 , 0x1fff },
+    { 0x40d20330 , 0x43c1 },
+    { 0x40d22180 , 0xc },
+    { 0x40d2218c , 0xc },
+    { 0x40d22700 , 0xd },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0xd },
+    { 0x40d20990 , 0x1f },
+    { 0x40d200b4 , 0xff3ff3ff },
+    { 0x40d20134 , 0xff3ff3ff },
+    { 0x40d20434 , 0x30027 },
+    { 0x40d204c0 , 0x1000 },
+    { 0x40d20620 , 0x3fff },
+    { 0x40d20334 , 0x3c1 },
+    { 0x40d203b4 , 0x400 },
+    { 0x40d221a0 , 0xd },
+    { 0x40d221ac , 0xd },
+    { 0x40d22700 , 0xe },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0xe },
+    { 0x40d20990 , 0x1f },
+    { 0x40d200b8 , 0xff3ff3ff },
+    { 0x40d20138 , 0xff3ff3ff },
+    { 0x40d20438 , 0x30029 },
+    { 0x40d204c0 , 0x1000 },
+    { 0x40d20620 , 0x7fff },
+    { 0x40d20338 , 0x3c1 },
+    { 0x40d203b8 , 0x400 },
+    { 0x40d221c0 , 0xe },
+    { 0x40d221cc , 0xe },
+    { 0x40d22700 , 0xf },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0xf },
+    { 0x40d20990 , 0x1f },
+    { 0x40d200bc , 0xff3ff3ff },
+    { 0x40d2013c , 0xff3ff3ff },
+    { 0x40d2043c , 0x3002b },
+    { 0x40d204c0 , 0x1000 },
+    { 0x40d20620 , 0xffff },
+    { 0x40d2033c , 0x3c1 },
+    { 0x40d203bc , 0x400 },
+    { 0x40d221e0 , 0xf },
+    { 0x40d221ec , 0xf },
+    { 0x40d22700 , 0x10 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x10 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d200c0 , 0xff3ff3ff },
+    { 0x40d20140 , 0xff3ff3ff },
+    { 0x40d20440 , 0x30033 },
+    { 0x40d204c0 , 0x1000 },
+    { 0x40d20620 , 0x1ffff },
+    { 0x40d20340 , 0x3c1 },
+    { 0x40d203c0 , 0x400 },
+    { 0x40d22200 , 0x10 },
+    { 0x40d2220c , 0x10 },
+    { 0x40d22700 , 0x11 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x11 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d200c4 , 0xff3ff3ff },
+    { 0x40d20144 , 0xff3ff3ff },
+    { 0x40d20444 , 0x3002d },
+    { 0x40d204c0 , 0x1000 },
+    { 0x40d20620 , 0x3ffff },
+    { 0x40d20344 , 0x13c1 },
+    { 0x40d203c4 , 0x400 },
+    { 0x40d22220 , 0x11 },
+    { 0x40d2222c , 0x11 },
+    { 0x40d22700 , 0x12 },
+    { 0x40d2270c , 0x3ff },
+    { 0x40d22714 , 0x400 },
+    { 0x40d22708 , 0x400 },
+    { 0x40d22704 , 0x12 },
+    { 0x40d20990 , 0x1f },
+    { 0x40d20520 , 0x1 },
+    { 0x40d20604 , 0x1ff },
+    { 0x40d20900 , 0x1 },
+    { 0x40d20480 , 0x28 },
+    { 0x40d204d0 , 0x35a },
+    { 0x40d204d8 , 0xa6 },
+    { 0x40d204d4 , 0x35a },
+    { 0x40d204dc , 0xa6 },
+    { 0x40d20980 , 0x100 },
+    { 0x40d20004 , 0x1feff },
+    { 0x40d20850 , 0x201 },
+    { 0x40d2b000 , 0x0 },
+    { 0x40d2b040 , 0x0 },
+    { 0x40d2b054 , 0xc },
+    { 0x40d2b200 , 0x0 },
+    { 0x40d2b240 , 0x0 },
+    { 0x40d2b254 , 0xc },
+    { 0x40d2b400 , 0x0 },
+    { 0x40d2b440 , 0x0 },
+    { 0x40d2b454 , 0xc },
+    { 0x40d2b600 , 0x0 },
+    { 0x40d2b640 , 0x0 },
+    { 0x40d2b654 , 0xc },
+    { 0x40d2b800 , 0x0 },
+    { 0x40d2b840 , 0x0 },
+    { 0x40d2b854 , 0xc },
+    { 0x40d2ba00 , 0x0 },
+    { 0x40d2ba40 , 0x0 },
+    { 0x40d2ba54 , 0xc },
+    { 0x40d2bc00 , 0x0 },
+    { 0x40d2bc40 , 0x0 },
+    { 0x40d2bc54 , 0xc },
+    { 0x40d2be00 , 0x0 },
+    { 0x40d2be40 , 0x0 },
+    { 0x40d2be54 , 0xc },
+    { 0x40d0203c , 0x3 },
+    { 0x40d0603c , 0x3 },
+    { 0x40d0a03c , 0x3 },
+    { 0x40d0e03c , 0x3 },
+    { 0x40d1203c , 0x3 },
+    { 0x40d1603c , 0x3 },
+    { 0x40d1a03c , 0x3 },
+    { 0x40d1e03c , 0x3 },
+    { 0x40d20000 , 0x50101 },
+    { 0x40100000 , 0x307 },
+    { 0x40d28000 , 0x1 },
+    { 0x40d29000 , 0x1 },
+    { 0x40280000 , 0x1ffe701 },
+    { 0x1120064e , 0x0 },
+    { 0x11200642 , 0x8 },
+    { 0x11200646 , 0x10 },
+    { 0x1120064a , 0x18 },
+    { 0x1120063e , 0x20 },
+    { 0x11200652 , 0x28 },
+    { 0x11200656 , 0x30 },
+    { (ACCESS_LOG_OP_STOP << 24), 0 }
+};
diff --git a/drivers/net/bcmbca/xrdp/data_path_6878.c b/drivers/net/bcmbca/xrdp/data_path_6878.c
new file mode 100644
index 0000000000..911d50e10a
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/data_path_6878.c
@@ -0,0 +1,637 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include "access_logging.h"
+
+const access_log_tuple_t init_data[] = {
+	{ 0x40d98014 , 0x82a00000 },
+	{ 0x40d98018 , 0xffe00000 },
+	{ 0x40d9801c , 0x82100000 },
+	{ 0x40d98020 , 0xfff80000 },
+	{ 0x40d98024 , 0x82180000 },
+	{ 0x40d98028 , 0xfff80000 },
+	{ 0x40d98004 , 0x82d00000 },
+	{ 0x40d98008 , 0xffe00000 },
+	{ 0x40d9800c , 0x82e00000 },
+	{ 0x40d98010 , 0xffe00000 },
+	{ 0x40d96008 , 0x20002 },
+	{ 0x41020a10 , 0x82a000 },
+	{ 0x41020a14 , 0x82a000 },
+	{ 0x41020a18 , 0x31509 },
+	{ 0x41020a1c , 0x821000 },
+	{ 0x41020a20 , 0x821000 },
+	{ 0x41020a24 , 0x31409 },
+	{ 0x5c00000 , 0x0 },
+	{ 0x2000000 , 0x4000 },
+	{ 0x82c00000 , 0x0 },
+	{ 0x2000000 , 0x800 },
+	{ 0x82c18000 , 0x0 },
+	{ 0x3000000 , 0x2000 },
+	{ 0x82c10000 , 0xfc000000 },
+	{ 0x41c10000 , 0x6008006 },
+	{ 0x41c1000c , 0x19008006 },
+	{ 0x41c10018 , 0x26 },
+	{ 0x41c10020 , 0x6f8010a },
+	{ 0x41c10024 , 0xc031ac },
+	{ 0x41c10028 , 0x40020b0 },
+	{ 0x41c1002c , 0x21008004 },
+	{ 0x41c10030 , 0x740110b0 },
+	{ 0x41c10034 , 0x638000cc },
+	{ 0x41c10038 , 0xb8d3ac },
+	{ 0x41c1003c , 0xf4ff53b0 },
+	{ 0x41c10040 , 0xa0a00684 },
+	{ 0x41c10044 , 0x18800006 },
+	{ 0x41c10048 , 0xe98d0a8 },
+	{ 0x41c1004c , 0x400c0b0 },
+	{ 0x41c10050 , 0x21008004 },
+	{ 0x41c10054 , 0x40310b0 },
+	{ 0x41c10058 , 0x86a100cc },
+	{ 0x41c10060 , 0x21000004 },
+	{ 0x41c10064 , 0x21c0036 },
+	{ 0x41c10068 , 0x421c1036 },
+	{ 0x41c1006c , 0x831c2036 },
+	{ 0x41c10070 , 0x31d4036 },
+	{ 0x41c10074 , 0x831d6036 },
+	{ 0x41c10078 , 0x31e8036 },
+	{ 0x41c1007c , 0x831ea036 },
+	{ 0x41c10080 , 0x31fc036 },
+	{ 0x41c10084 , 0x831fe036 },
+	{ 0x41c10088 , 0x3200037 },
+	{ 0x41c1008c , 0x83202037 },
+	{ 0x41c10090 , 0x3214037 },
+	{ 0x41c10094 , 0x83216037 },
+	{ 0x41c10098 , 0x3228037 },
+	{ 0x41c1009c , 0x8322a037 },
+	{ 0x41c100a0 , 0x323c037 },
+	{ 0x41c100a4 , 0x8323e037 },
+	{ 0x41c100a8 , 0x820010c6 },
+	{ 0x41c100ac , 0x9610ac },
+	{ 0x41c100b0 , 0xc20e1036 },
+	{ 0x41c100b4 , 0x2e602002 },
+	{ 0x41c100b8 , 0x2f602002 },
+	{ 0x41c100bc , 0x30602002 },
+	{ 0x41c100c0 , 0xc2 },
+	{ 0x41c100c4 , 0x32602002 },
+	{ 0x41c100c8 , 0x33602002 },
+	{ 0x41c100cc , 0x34602002 },
+	{ 0x41c100d0 , 0x21c0032 },
+	{ 0x41c100d4 , 0x421c1032 },
+	{ 0x41c100d8 , 0x831c2032 },
+	{ 0x41c100dc , 0x31d4032 },
+	{ 0x41c100e0 , 0x831d6032 },
+	{ 0x41c100e4 , 0x31e8032 },
+	{ 0x41c100e8 , 0x831ea032 },
+	{ 0x41c100ec , 0x31fc032 },
+	{ 0x41c100f0 , 0x831fe032 },
+	{ 0x41c100f4 , 0x3200033 },
+	{ 0x41c100f8 , 0x83202033 },
+	{ 0x41c100fc , 0x3214033 },
+	{ 0x41c10100 , 0x83216033 },
+	{ 0x41c10104 , 0x3228033 },
+	{ 0x41c10108 , 0x8322a033 },
+	{ 0x41c1010c , 0x323c033 },
+	{ 0x41c10110 , 0x8323e033 },
+	{ 0x41c10120 , 0x1008022 },
+	{ 0x41c10130 , 0x440020b0 },
+	{ 0x41c10134 , 0x40010b0 },
+	{ 0x41c10138 , 0x1219e },
+	{ 0x41c1013c , 0x40802080 },
+	{ 0x41c10140 , 0x140040b0 },
+	{ 0x41c10144 , 0x2001130 },
+	{ 0x41c10148 , 0x80801080 },
+	{ 0x41c1014c , 0x2001134 },
+	{ 0x41c10150 , 0x22001138 },
+	{ 0x41c10154 , 0x80801082 },
+	{ 0x41c10158 , 0x2200113c },
+	{ 0x41c1015c , 0x43006838 },
+	{ 0x41c10160 , 0x3002830 },
+	{ 0x41c10164 , 0x497cc30a },
+	{ 0x41c10168 , 0x402613ac },
+	{ 0x41c1016c , 0xc0aaf1ac },
+	{ 0x41c10170 , 0x20808096 },
+	{ 0x41c10174 , 0x40050b0 },
+	{ 0x41c10178 , 0x40020b0 },
+	{ 0x41c1017c , 0x81529e },
+	{ 0x41c10180 , 0xa0002180 },
+	{ 0x41c10184 , 0x2005130 },
+	{ 0x41c10188 , 0x80805280 },
+	{ 0x41c1018c , 0x2005134 },
+	{ 0x41c10190 , 0xb811ac },
+	{ 0x41c10194 , 0x22005138 },
+	{ 0x41c10198 , 0x20805280 },
+	{ 0x41c1019c , 0x80805282 },
+	{ 0x41c101a0 , 0x2200513c },
+	{ 0x41c101a4 , 0x400c0b0 },
+	{ 0x41c101a8 , 0x400d0b0 },
+	{ 0x41c101ac , 0x40040b1 },
+	{ 0x41c101b0 , 0x6a0a4a8 },
+	{ 0x41c101b4 , 0x1c18430 },
+	{ 0x41c101b8 , 0x40020b0 },
+	{ 0x41c101bc , 0x40050b0 },
+	{ 0x41c101c0 , 0x1f04c2a8 },
+	{ 0x41c101c4 , 0x61cc0a8 },
+	{ 0x41c101c8 , 0x1f04d0a8 },
+	{ 0x41c101cc , 0xec843a9 },
+	{ 0x41c101d0 , 0x6a8a7a8 },
+	{ 0x41c101d4 , 0x7a425a8 },
+	{ 0x41c101d8 , 0x2b851a8 },
+	{ 0x41c101dc , 0x7915c4a8 },
+	{ 0x41c101e0 , 0x18c0a8 },
+	{ 0x41c101e4 , 0x1d04d0a8 },
+	{ 0x41c101e8 , 0x2280e838 },
+	{ 0x41c101ec , 0x94603702 },
+	{ 0x41c101f0 , 0x4380c83c },
+	{ 0x41c101f4 , 0x280483d },
+	{ 0x41c101f8 , 0x2280583c },
+	{ 0x41c101fc , 0x44050b0 },
+	{ 0x41c10200 , 0x821883 },
+	{ 0x41c10204 , 0x1400c0b0 },
+	{ 0x41c10208 , 0xa8801889 },
+	{ 0x41c1020c , 0x1c69e },
+	{ 0x41c10210 , 0x40050b0 },
+	{ 0x41c10214 , 0x80815280 },
+	{ 0x41c10218 , 0x280c230 },
+	{ 0x41c1021c , 0x8000c680 },
+	{ 0x41c10220 , 0x280c234 },
+	{ 0x41c10224 , 0x2280c238 },
+	{ 0x41c10228 , 0x20001680 },
+	{ 0x41c1022c , 0x80801082 },
+	{ 0x41c10230 , 0x2280123c },
+	{ 0x41c10234 , 0x6a0a4a8 },
+	{ 0x41c10238 , 0x90005cc },
+	{ 0x41c1023c , 0x1f0462a8 },
+	{ 0x41c10240 , 0x6e1d34a8 },
+	{ 0x41c10244 , 0x7138026 },
+	{ 0x41c10248 , 0x6a8a7a8 },
+	{ 0x41c1024c , 0x484065cc },
+	{ 0x41c10250 , 0x340020b1 },
+	{ 0x41c10254 , 0x400e0b0 },
+	{ 0x41c10258 , 0x1299f },
+	{ 0x41c1025c , 0x4002e780 },
+	{ 0x41c10260 , 0x2002731 },
+	{ 0x41c10264 , 0x80002981 },
+	{ 0x41c10268 , 0x2002735 },
+	{ 0x41c1026c , 0x22002739 },
+	{ 0x41c10270 , 0x20002981 },
+	{ 0x41c10274 , 0x80002983 },
+	{ 0x41c10278 , 0x2200273d },
+	{ 0x41c1027c , 0x861e8026 },
+	{ 0x41c10280 , 0x2400e0b0 },
+	{ 0x41c10284 , 0x22e07c2 },
+	{ 0x41c10288 , 0x240050b0 },
+	{ 0x41c1028c , 0x40010b0 },
+	{ 0x41c10290 , 0x81529e },
+	{ 0x41c10294 , 0xa0801080 },
+	{ 0x41c10298 , 0x2805030 },
+	{ 0x41c1029c , 0x1c18430 },
+	{ 0x41c102a0 , 0x80805280 },
+	{ 0x41c102a4 , 0x2805034 },
+	{ 0x41c102a8 , 0x22805038 },
+	{ 0x41c102ac , 0x80805282 },
+	{ 0x41c102b0 , 0x2280503c },
+	{ 0x41c102b4 , 0x240110b0 },
+	{ 0x41c102b8 , 0xe008007 },
+	{ 0x41c102c8 , 0x8d000006 },
+	{ 0x41c102d0 , 0x40010b0 },
+	{ 0x41c102d4 , 0x40820b0 },
+	{ 0x41c102d8 , 0x81109e },
+	{ 0x41c102dc , 0x20001180 },
+	{ 0x41c102e0 , 0x140040b0 },
+	{ 0x41c102e4 , 0x2802030 },
+	{ 0x41c102e8 , 0x80002180 },
+	{ 0x41c102ec , 0x2802034 },
+	{ 0x41c102f0 , 0x22802038 },
+	{ 0x41c102f4 , 0x80002182 },
+	{ 0x41c102f8 , 0x2280203c },
+	{ 0x41c102fc , 0x3004430 },
+	{ 0x41c10300 , 0x43002438 },
+	{ 0x41c10304 , 0x2801430 },
+	{ 0x41c10308 , 0x72d8026 },
+	{ 0x41c1030c , 0x81c020cc },
+	{ 0x41c10310 , 0x2200043c },
+	{ 0x40d0004c , 0x4 },
+	{ 0x48fac9c0 , 0x2 },
+	{ 0x48fac9c0 , 0x2 },
+	{ 0x40d00044 , 0x826 },
+	{ 0x41c18000 , 0x30010000 },
+	{ 0x41c18024 , 0x4 },
+	{ 0x41c18028 , 0x12000000 },
+	{ 0x41c1802c , 0x0 },
+	{ 0x41c18040 , 0x40010000 },
+	{ 0x41c18044 , 0x80000 },
+	{ 0x41c18080 , 0xd0020000 },
+	{ 0x41c180a0 , 0x50000000 },
+	{ 0x41c180a4 , 0xdc000000 },
+	{ 0x40d00000 , 0x101f300 },
+	{ 0x40d01000 , 0x101f300 },
+	{ 0x40d02000 , 0x101f300 },
+	{ 0x40d08500 , 0x701f0420 },
+	{ 0x40d08840 , 0x8 },
+	{ 0x40d08844 , 0x8 },
+	{ 0x40d08848 , 0x8 },
+	{ 0x40d0884c , 0x8 },
+	{ 0x40d94020 , 0x404 },
+	{ 0x40d94000 , 0x15 },
+	{ 0x40d94000 , 0x301215 },
+	{ 0x40d94024 , 0x40404040 },
+	{ 0x40d94028 , 0x60005ee },
+	{ 0x40d94024 , 0x40404040 },
+	{ 0x40d94028 , 0x5ee05ee },
+	{ 0x40d94024 , 0x40404040 },
+	{ 0x40d9402c , 0x60005ee },
+	{ 0x40d94024 , 0x40404040 },
+	{ 0x40d9402c , 0x5ee05ee },
+	{ 0x40d94030 , 0x12 },
+	{ 0x40d94044 , 0xff },
+	{ 0x40d94034 , 0x1000 },
+	{ 0x40d94034 , 0x0 },
+	{ 0x40d94064 , 0xf },
+	{ 0x40d94420 , 0x404 },
+	{ 0x40d9441c , 0x404 },
+	{ 0x40d94400 , 0x15 },
+	{ 0x40d94400 , 0x301215 },
+	{ 0x40d94404 , 0x101 },
+	{ 0x40d94424 , 0x40404040 },
+	{ 0x40d94428 , 0x60005ee },
+	{ 0x40d94424 , 0x40404040 },
+	{ 0x40d94428 , 0x5ee05ee },
+	{ 0x40d94424 , 0x40404040 },
+	{ 0x40d9442c , 0x60005ee },
+	{ 0x40d94424 , 0x40404040 },
+	{ 0x40d9442c , 0x5ee05ee },
+	{ 0x40d94430 , 0x12 },
+	{ 0x40d94444 , 0xff },
+	{ 0x40d94434 , 0x1000 },
+	{ 0x40d94434 , 0x0 },
+	{ 0x40d94464 , 0xf },
+	{ 0x40d94820 , 0x404 },
+	{ 0x40d9481c , 0x808 },
+	{ 0x40d94800 , 0x15 },
+	{ 0x40d94800 , 0x301215 },
+	{ 0x40d94804 , 0x202 },
+	{ 0x40d94824 , 0x40404040 },
+	{ 0x40d94828 , 0x60005ee },
+	{ 0x40d94824 , 0x40404040 },
+	{ 0x40d94828 , 0x5ee05ee },
+	{ 0x40d94824 , 0x40404040 },
+	{ 0x40d9482c , 0x60005ee },
+	{ 0x40d94824 , 0x40404040 },
+	{ 0x40d9482c , 0x5ee05ee },
+	{ 0x40d94830 , 0x12 },
+	{ 0x40d94844 , 0xff },
+	{ 0x40d94834 , 0x1000 },
+	{ 0x40d94834 , 0x0 },
+	{ 0x40d94864 , 0xf },
+	{ 0x40d94c20 , 0x404 },
+	{ 0x40d94c1c , 0xc0c },
+	{ 0x40d94c00 , 0x15 },
+	{ 0x40d94c00 , 0x301215 },
+	{ 0x40d94c04 , 0x303 },
+	{ 0x40d94c24 , 0x40404040 },
+	{ 0x40d94c28 , 0x60005ee },
+	{ 0x40d94c24 , 0x40404040 },
+	{ 0x40d94c28 , 0x5ee05ee },
+	{ 0x40d94c24 , 0x40404040 },
+	{ 0x40d94c2c , 0x60005ee },
+	{ 0x40d94c24 , 0x40404040 },
+	{ 0x40d94c2c , 0x5ee05ee },
+	{ 0x40d94c30 , 0x12 },
+	{ 0x40d94c44 , 0xff },
+	{ 0x40d94c34 , 0x1000 },
+	{ 0x40d94c34 , 0x0 },
+	{ 0x40d94c64 , 0xf },
+	{ 0x40d95020 , 0x404 },
+	{ 0x40d9501c , 0x1010 },
+	{ 0x40d95000 , 0x15 },
+	{ 0x40d95000 , 0x301215 },
+	{ 0x40d95004 , 0x404 },
+	{ 0x40d95024 , 0x40404040 },
+	{ 0x40d95028 , 0x60005ee },
+	{ 0x40d95024 , 0x40404040 },
+	{ 0x40d95028 , 0x5ee05ee },
+	{ 0x40d95024 , 0x40404040 },
+	{ 0x40d9502c , 0x60005ee },
+	{ 0x40d95024 , 0x40404040 },
+	{ 0x40d9502c , 0x5ee05ee },
+	{ 0x40d95030 , 0x12 },
+	{ 0x40d95044 , 0xff },
+	{ 0x40d95034 , 0x1000 },
+	{ 0x40d95034 , 0x0 },
+	{ 0x40d95064 , 0xf },
+	{ 0x40d90000 , 0x1 },
+	{ 0x40d90004 , 0x17300000 },
+	{ 0x40d90004 , 0x17300015 },
+	{ 0x40d90020 , 0x80400 },
+	{ 0x40d90004 , 0x17301515 },
+	{ 0x40d90024 , 0x80410 },
+	{ 0x40d9000c , 0x20200004 },
+	{ 0x40d90018 , 0x10030 },
+	{ 0x40d90400 , 0x0 },
+	{ 0x40d90450 , 0x0 },
+	{ 0x40d904b0 , 0x0 },
+	{ 0x40d904a0 , 0x70007 },
+	{ 0x40d904a4 , 0x0 },
+	{ 0x40d904a8 , 0x0 },
+	{ 0x40d90908 , 0x1000000 },
+	{ 0x40d90920 , 0x1400000 },
+	{ 0x40d90940 , 0x13f013f },
+	{ 0x40d90960 , 0x280000 },
+	{ 0x40d90980 , 0x270027 },
+	{ 0x40d900bc , 0x3 },
+	{ 0x40d907a0 , 0x70007 },
+	{ 0x40d907a4 , 0x0 },
+	{ 0x40d907a8 , 0xfff0fff },
+	{ 0x40d90908 , 0x1000001 },
+	{ 0x40d90924 , 0x3c00280 },
+	{ 0x40d90944 , 0x13f013f },
+	{ 0x40d90964 , 0x780050 },
+	{ 0x40d90984 , 0x270027 },
+	{ 0x40d900bc , 0x3 },
+	{ 0x40d907a0 , 0x70007 },
+	{ 0x40d907a8 , 0xfff0fff },
+	{ 0x40d90908 , 0x1000002 },
+	{ 0x40d90928 , 0x6400500 },
+	{ 0x40d90948 , 0x13f013f },
+	{ 0x40d90968 , 0xc800a0 },
+	{ 0x40d90988 , 0x270027 },
+	{ 0x40d900bc , 0x3 },
+	{ 0x40d907b8 , 0x2 },
+	{ 0x40d907a0 , 0x70007 },
+	{ 0x40d907a8 , 0xfff0fff },
+	{ 0x40d90908 , 0x1000003 },
+	{ 0x40d9094c , 0x13f013f },
+	{ 0x40d9096c , 0x0 },
+	{ 0x40d9098c , 0x270027 },
+	{ 0x40d900bc , 0x3 },
+	{ 0x40d907a0 , 0x70007 },
+	{ 0x40d907a8 , 0xfff0fff },
+	{ 0x40d90600 , 0x0 },
+	{ 0x40d90604 , 0x1 },
+	{ 0x40d9090c , 0x3f },
+	{ 0x40d90020 , 0xc0400 },
+	{ 0x40d90024 , 0xc0410 },
+	{ 0x40d9003c , 0x12047c5e },
+	{ 0x40d99000 , 0xffc000 },
+	{ 0x40d9a000 , 0x4 },
+	{ 0x40d9a040 , 0x203 },
+	{ 0x40d9a060 , 0x84 },
+	{ 0x40d9a020 , 0x10 },
+	{ 0x40d9a0a0 , 0x201f },
+	{ 0x40d9a004 , 0x4 },
+	{ 0x40d9a044 , 0x203 },
+	{ 0x40d9a064 , 0x44 },
+	{ 0x40d9a024 , 0x10 },
+	{ 0x40d9a0a4 , 0x2021 },
+	{ 0x40d9a008 , 0x4 },
+	{ 0x40d9a048 , 0x203 },
+	{ 0x40d9a068 , 0x84 },
+	{ 0x40d9a028 , 0x10 },
+	{ 0x40d9a0a8 , 0x2e23 },
+	{ 0x40d9a00c , 0x4 },
+	{ 0x40d9a04c , 0x203 },
+	{ 0x40d9a06c , 0x44 },
+	{ 0x40d9a02c , 0x10 },
+	{ 0x40d9a0ac , 0x2e25 },
+	{ 0x40d9a010 , 0x4 },
+	{ 0x40d9a050 , 0x203 },
+	{ 0x40d9a070 , 0x4 },
+	{ 0x40d9a0b0 , 0x27 },
+	{ 0x40d9a014 , 0x4 },
+	{ 0x40d9a054 , 0x608 },
+	{ 0x40d9a074 , 0x4 },
+	{ 0x40d9a0b4 , 0x2d },
+	{ 0x40d9a018 , 0x4 },
+	{ 0x40d9a058 , 0x608 },
+	{ 0x40d9a078 , 0x4 },
+	{ 0x40d9a0c0 , 0x1 },
+	{ 0x40d9a0c4 , 0x101 },
+	{ 0x40d9a0c8 , 0x1 },
+	{ 0x40d9a0cc , 0x101 },
+	{ 0x40d9a0d0 , 0x1 },
+	{ 0x40d9a0d4 , 0x101 },
+	{ 0x40d9a0d8 , 0x1 },
+	{ 0x40d9a0dc , 0x101 },
+	{ 0x40d9a0f0 , 0x100010 },
+	{ 0x40d9a0f4 , 0x30807 },
+	{ 0x40d9a0f4 , 0x807 },
+	{ 0x40d9a0f0 , 0xffff05dc },
+	{ 0x3000000 , 0x20 },
+	{ 0x82d80080 , 0xfff00f3f },
+	{ 0x3000000 , 0x20 },
+	{ 0x82d80100 , 0xfff00f3f },
+	{ 0x40d80180 , 0x3f0ff0ff },
+	{ 0x40d80184 , 0xa064058 },
+	{ 0x7000000 , 0xff },
+	{ 0x82d83000 , 0x40004 },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d80080 , 0x3f0ff0ff },
+	{ 0x40d80100 , 0x3f0ff0ff },
+	{ 0x40d80400 , 0x2001f },
+	{ 0x40d80620 , 0x1 },
+	{ 0x40d80300 , 0x4091 },
+	{ 0x40d80380 , 0x400 },
+	{ 0x40d82700 , 0x1 },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0x1 },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d80084 , 0x3f0ff0ff },
+	{ 0x40d80104 , 0x3f0ff0ff },
+	{ 0x40d80404 , 0x20021 },
+	{ 0x40d80620 , 0x3 },
+	{ 0x40d80304 , 0x4091 },
+	{ 0x40d80384 , 0x400 },
+	{ 0x40d82020 , 0x1 },
+	{ 0x40d8202c , 0x1 },
+	{ 0x40d82700 , 0x2 },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0x2 },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d80088 , 0x3f0ff0ff },
+	{ 0x40d80108 , 0x3f0ff0ff },
+	{ 0x40d80408 , 0x20023 },
+	{ 0x40d80620 , 0x7 },
+	{ 0x40d80308 , 0x4091 },
+	{ 0x40d80388 , 0x400 },
+	{ 0x40d82040 , 0x2 },
+	{ 0x40d8204c , 0x2 },
+	{ 0x40d82700 , 0x3 },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0x3 },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d8008c , 0x3f0ff0ff },
+	{ 0x40d8010c , 0x3f0ff0ff },
+	{ 0x40d8040c , 0x20025 },
+	{ 0x40d80620 , 0xf },
+	{ 0x40d8030c , 0x4091 },
+	{ 0x40d8038c , 0x400 },
+	{ 0x40d82060 , 0x3 },
+	{ 0x40d8206c , 0x3 },
+	{ 0x40d82700 , 0x4 },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0x4 },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d80090 , 0x3f0ff0ff },
+	{ 0x40d80110 , 0x3f0ff0ff },
+	{ 0x40d80410 , 0x20027 },
+	{ 0x40d80620 , 0x1f },
+	{ 0x40d80310 , 0x4091 },
+	{ 0x40d80390 , 0x400 },
+	{ 0x40d82080 , 0x4 },
+	{ 0x40d8208c , 0x4 },
+	{ 0x40d82700 , 0x5 },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0x5 },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d80094 , 0x3f0ff0ff },
+	{ 0x40d80114 , 0x3f0ff0ff },
+	{ 0x40d80414 , 0x2002d },
+	{ 0x40d80620 , 0x3f },
+	{ 0x40d80314 , 0x4091 },
+	{ 0x40d80394 , 0x400 },
+	{ 0x40d820a0 , 0x5 },
+	{ 0x40d820ac , 0x5 },
+	{ 0x40d82700 , 0x6 },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0x6 },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d80098 , 0x3f0ff0ff },
+	{ 0x40d80118 , 0x3f0ff0ff },
+	{ 0x40d80418 , 0x3001f },
+	{ 0x40d80620 , 0x7f },
+	{ 0x40d80318 , 0x91 },
+	{ 0x40d80398 , 0x400 },
+	{ 0x40d820c0 , 0x6 },
+	{ 0x40d820cc , 0x6 },
+	{ 0x40d82700 , 0x7 },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0x7 },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d8009c , 0x3f0ff0ff },
+	{ 0x40d8011c , 0x3f0ff0ff },
+	{ 0x40d8041c , 0x30021 },
+	{ 0x40d80620 , 0xff },
+	{ 0x40d8031c , 0x91 },
+	{ 0x40d8039c , 0x400 },
+	{ 0x40d820e0 , 0x7 },
+	{ 0x40d820ec , 0x7 },
+	{ 0x40d82700 , 0x8 },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0x8 },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d800a0 , 0x3f0ff0ff },
+	{ 0x40d80120 , 0x3f0ff0ff },
+	{ 0x40d80420 , 0x30023 },
+	{ 0x40d80620 , 0x1ff },
+	{ 0x40d80320 , 0x91 },
+	{ 0x40d803a0 , 0x400 },
+	{ 0x40d82100 , 0x8 },
+	{ 0x40d8210c , 0x8 },
+	{ 0x40d82700 , 0x9 },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0x9 },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d800a4 , 0x3f0ff0ff },
+	{ 0x40d80124 , 0x3f0ff0ff },
+	{ 0x40d80424 , 0x30025 },
+	{ 0x40d80620 , 0x3ff },
+	{ 0x40d80324 , 0x91 },
+	{ 0x40d803a4 , 0x400 },
+	{ 0x40d82120 , 0x9 },
+	{ 0x40d8212c , 0x9 },
+	{ 0x40d82700 , 0xa },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0xa },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d800a8 , 0x3f0ff0ff },
+	{ 0x40d80128 , 0x3f0ff0ff },
+	{ 0x40d80428 , 0x30027 },
+	{ 0x40d80620 , 0x7ff },
+	{ 0x40d80328 , 0x91 },
+	{ 0x40d803a8 , 0x400 },
+	{ 0x40d82140 , 0xa },
+	{ 0x40d8214c , 0xa },
+	{ 0x40d82700 , 0xb },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0xb },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d800ac , 0x3f0ff0ff },
+	{ 0x40d8012c , 0x3f0ff0ff },
+	{ 0x40d8042c , 0x3002d },
+	{ 0x40d80620 , 0xfff },
+	{ 0x40d8032c , 0x1091 },
+	{ 0x40d803ac , 0x400 },
+	{ 0x40d82160 , 0xb },
+	{ 0x40d8216c , 0xb },
+	{ 0x40d82700 , 0xc },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0xc },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d800b0 , 0x3f0ff0ff },
+	{ 0x40d80130 , 0x3f0ff0ff },
+	{ 0x40d80430 , 0x101a0000 },
+	{ 0x40d804c0 , 0x1000 },
+	{ 0x40d80620 , 0x1fff },
+	{ 0x40d80330 , 0x4091 },
+	{ 0x40d82180 , 0xc },
+	{ 0x40d8218c , 0xc },
+	{ 0x40d82700 , 0xd },
+	{ 0x40d8270c , 0xff },
+	{ 0x40d82714 , 0x100 },
+	{ 0x40d82708 , 0x100 },
+	{ 0x40d82704 , 0xd },
+	{ 0x40d80990 , 0x1f },
+	{ 0x40d80520 , 0x1 },
+	{ 0x40d80604 , 0x3f },
+	{ 0x40d80900 , 0x1 },
+	{ 0x40d80480 , 0x28 },
+	{ 0x40d804d0 , 0x7f },
+	{ 0x40d804d8 , 0x81 },
+	{ 0x40d804d4 , 0x7f },
+	{ 0x40d804dc , 0x81 },
+	{ 0x40d80980 , 0x100 },
+	{ 0x40d80004 , 0x17df },
+	{ 0x40d80850 , 0x201 },
+	{ 0x40d9403c , 0x3 },
+	{ 0x40d9443c , 0x3 },
+	{ 0x40d9483c , 0x3 },
+	{ 0x40d94c3c , 0x3 },
+	{ 0x40d9503c , 0x3 },
+	{ 0x40d80000 , 0x101 },
+	{ 0x40100000 , 0x307 },
+	{ 0x40d96000 , 0x1 },
+	{ 0x40d00000 , 0x101f301 },
+	{ 0x11c0063e , 0x0 },
+	{ 0x11c00642 , 0x8 },
+	{ 0x11c00646 , 0x10 },
+	{ 0x11c0064a , 0x18 },
+	{ 0x11c0064e , 0x20 },
+    { (ACCESS_LOG_OP_STOP << 24), 0 }
+};
diff --git a/drivers/net/bcmbca/xrdp/rdd_data_structures.h b/drivers/net/bcmbca/xrdp/rdd_data_structures.h
new file mode 100644
index 0000000000..972a3e600e
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/rdd_data_structures.h
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+   Copyright (c) 2015 Broadcom
+   All Rights Reserved
+*/
+
+#ifndef _RDD_DATA_STRUCTURES_AUTO__
+#define _RDD_DATA_STRUCTURES_AUTO__
+
+#ifndef NO_ACCESS_LOGGING
+#include "access_macros.h"
+
+#if defined(CONFIG_BCM6858)
+#define XRDP_BBH_PER_LAN_PORT
+#endif
+
+extern uintptr_t rdp_runner_core_addr[];
+
+/* RNR_REGS_ADDRS */
+#if defined(CONFIG_BCM6878) || defined(CONFIG_BCM6846) || defined(CONFIG_BCM6856)
+#define RNR_REGS_ADDR_CORE0 0x82d00000
+#elif defined(CONFIG_BCM6858)
+#define RNR_REGS_ADDR_CORE0 0x82280000
+#elif defined(CONFIG_BCM63146) || defined(CONFIG_BCM4912)
+#define RNR_REGS_ADDR_CORE0 0x82800000
+#endif
+
+#ifdef XRDP_SBPM
+#ifdef CONFIG_BCM6878
+#define SBPM_ADDRS 0x82d99000
+#define PSRAM_MEM_ADDRS 0x82600000
+#define SBPM_MAX_BUFFER_NUMBER 0x3FF
+#elif defined(CONFIG_BCM6858)
+#define SBPM_ADDRS 0x82d2c000
+#define PSRAM_MEM_ADDRS 0x82600000
+#define SBPM_MAX_BUFFER_NUMBER 0xFFF
+#elif defined(CONFIG_BCM6846)
+#define SBPM_ADDRS 0x82d98000
+#define PSRAM_MEM_ADDRS 0x82600000
+#define SBPM_MAX_BUFFER_NUMBER 0x5FF
+#elif defined(CONFIG_BCM6856) 
+#define SBPM_ADDRS 0x82d99000
+#define PSRAM_MEM_ADDRS 0x82600000
+#define SBPM_MAX_BUFFER_NUMBER 0x7FF
+#elif defined(CONFIG_BCM63146) || defined(CONFIG_BCM4912)
+#define SBPM_MAX_BUFFER_NUMBER 0x17F
+#endif
+#endif
+
+#if defined(CONFIG_BCMBCA_XRDP_DSL)
+#if defined(CONFIG_BCM63146) || defined(CONFIG_BCM4912)
+#define PACKET_BUFFER_POOL_TABLE_ADDR_TX 2181099520
+#endif
+#endif
+
+#ifdef GEN45
+#define RDD_BBH_TX_DESCRIPTOR_SOF_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_LAST_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_BN_NUM_WRITE(v, p)                        FIELD_MWRITE_32((uint8_t *)p + 4, 14, 7, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_1_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_BN1_FIRST_WRITE(v, p)                     FIELD_MWRITE_32((uint8_t *)p + 8, 0, 18, v)
+#define RDD_BBH_TX_DESCRIPTOR_AGG_PD_WRITE(v, p)                        FIELD_MWRITE_8((uint8_t *)p + 12, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_0_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 12, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 12, 5, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_SOP_WRITE(v, p)                           FIELD_MWRITE_16((uint8_t *)p + 12, 2, 11, v)
+#define RDD_BBH_TX_DESCRIPTOR_BN0_FIRST_WRITE(v, p)                     FIELD_MWRITE_32((uint8_t *)p + 12, 0, 18, v)
+
+#define RDD_BBH_TX_RING_TABLE_PTR(core_id) (DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + 0x50))
+
+#define RDD_BB_DESTINATION_ENTRY_BB_DESTINATION_WRITE(v, p)                MWRITE_32((uint8_t *)p, v)
+#define RDD_BBH_TX_BB_DESTINATION_TABLE_PTR(core_id) (DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + 0xdc))
+
+#define RDD_BBH_TX_EGRESS_COUNTER_ENTRY_COUNTER_READ(r, p)                   MREAD_8((uint8_t *)p, r)
+#define RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_PTR(core_id) (DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + 0x180 ))
+
+#define RDD_SRAM_PD_FIFO_SIZE     64
+#define RDD_SRAM_PD_FIFO_PTR(core_id) (DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + 0x800))
+#endif
+
+#ifdef CONFIG_BCMBCA_XRDP_DSL
+#define RDD_BBH_TX_DESCRIPTOR_LAST_WRITE(v, p)                          FIELD_MWRITE_8((uint8_t *)p + 4, 7, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_ABS_WRITE(v, p)                           FIELD_MWRITE_8((uint8_t *)p + 5, 3, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_READ(r, p)                  FIELD_MREAD_16((uint8_t *)p + 6, 0, 14, r)
+#define RDD_BBH_TX_DESCRIPTOR_PACKET_LENGTH_WRITE(v, p)                 FIELD_MWRITE_16((uint8_t *)p + 6, 0, 14, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_1_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 8, 6, 1, v)
+#define RDD_BBH_TX_DESCRIPTOR_TARGET_MEM_0_WRITE(v, p)                  FIELD_MWRITE_8((uint8_t *)p + 12, 6, 1, v)
+#define RDD_BBH_TX_RING_TABLE_PTR(core_id) (DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + 0xd60))
+
+#define RDD_BB_DESTINATION_ENTRY_BB_DESTINATION_WRITE(v, p)                MWRITE_32((uint8_t *)p, v)
+#define RDD_BBH_TX_EGRESS_COUNTER_ENTRY_COUNTER_READ(r, p)                   MREAD_8((uint8_t *)p, r)
+
+#define RDD_CPU_RX_LAST_READ_INDEX_PTR(core_id) DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + 0xdfc)
+
+#define RDD_BBH_TX_BB_DESTINATION_TABLE_PTR(core_id) (DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + 0xd7c))
+
+#define RDD_DS_TM_BBH_TX_EGRESS_COUNTER_TABLE_PTR(core_id) (DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + 0xe80 ))
+
+#define RDD_SRAM_PD_FIFO_SIZE     16
+#define RDD_SRAM_PD_FIFO_PTR(core_id) (DEVICE_ADDRESS( rdp_runner_core_addr[core_id] + 0x0))
+#endif
+
+typedef enum
+{
+#if defined(CONFIG_BCM6878) || defined(CONFIG_BCM6846) || defined(CONFIG_BCM6856)
+	BB_ID_RX_BBH_0              = 31,
+	BB_ID_TX_LAN                = 32,
+	BB_ID_RX_BBH_1              = 33,
+	BB_ID_RX_BBH_2              = 35,
+	BB_ID_RX_BBH_3              = 37,
+	BB_ID_RX_BBH_4              = 39,
+	BB_ID_RX_BBH_5              = 41,
+#elif defined(CONFIG_BCM6858)
+	BB_ID_RX_BBH_0              = 31,
+	BB_ID_TX_BBH_0              = 32,
+	BB_ID_RX_BBH_1              = 33,
+	BB_ID_TX_BBH_1              = 34,
+	BB_ID_RX_BBH_2              = 35,
+	BB_ID_TX_BBH_2              = 36,
+	BB_ID_RX_BBH_3              = 37,
+	BB_ID_TX_BBH_3              = 38,
+	BB_ID_RX_BBH_4              = 39,
+	BB_ID_TX_BBH_4              = 40,
+	BB_ID_RX_BBH_5              = 41,
+	BB_ID_TX_BBH_5              = 42,
+	BB_ID_RX_BBH_6              = 43,
+	BB_ID_TX_BBH_6              = 44,
+	BB_ID_RX_BBH_7              = 51,
+	BB_ID_TX_BBH_7              = 52,
+#elif defined(CONFIG_BCM4912)
+	BB_ID_RX_BBH_0              = 31,
+	BB_ID_TX_LAN                = 32,
+	BB_ID_RX_BBH_1              = 33,
+	BB_ID_RX_BBH_2              = 35,
+	BB_ID_RX_BBH_3              = 37,
+	BB_ID_RX_BBH_4              = 39,
+	BB_ID_RX_BBH_5              = 41,
+	BB_ID_RX_BBH_6              = 43,
+	BB_ID_RX_BBH_7              = 45,
+	BB_ID_RX_BBH_8              = 47,
+#elif defined(CONFIG_BCM63146)
+	BB_ID_RX_BBH_0              = 31,
+	BB_ID_TX_LAN                = 32,
+	BB_ID_RX_BBH_1              = 33,
+	BB_ID_RX_BBH_2              = 35,
+	BB_ID_RX_BBH_3              = 37,
+	BB_ID_RX_BBH_4              = 39,
+	BB_ID_RX_BBH_5              = 41,
+	BB_ID_RX_BBH_6              = 43,
+	BB_ID_RX_BBH_7              = 45,
+#endif
+} rdd_bb_id;
+
+static inline void rnr_regs_cfg_cpu_wakeup_set(uint8_t rnr_id,
+	uint8_t thread_num)
+{
+	writel(thread_num, RNR_REGS_ADDR_CORE0+0x4);
+}
+
+#include "access_logging.h"
+
+extern const access_log_tuple_t init_data[];
+	
+static inline int xrdp_data_path_init(void)
+{
+    return access_log_restore(init_data);
+}
+#else
+
+#include <rdd.h>
+#include <rdp_drv_rnr.h>
+
+extern int xrdp_data_path_init(void);
+
+#define rnr_regs_cfg_cpu_wakeup_set(rnr_id, thread_num) \
+	ag_drv_rnr_regs_cfg_cpu_wakeup_set(rnr_id, thread_num)
+#endif
+
+static inline uint32_t __rdd_cpu_tx_get_bb_id(uint8_t tx_port)
+{
+#if defined(CONFIG_BCM6858)
+	uint32_t tx_map[] = {BB_ID_TX_BBH_4, BB_ID_TX_BBH_1, BB_ID_TX_BBH_2,
+		BB_ID_TX_BBH_3, BB_ID_TX_BBH_0, BB_ID_TX_BBH_5, BB_ID_TX_BBH_6};
+
+	if (tx_port < sizeof(tx_map)/sizeof(tx_map[0]))
+		return tx_map[tx_port];
+
+	return tx_map[0];
+#else
+	return (BB_ID_TX_LAN + (tx_port << 6));
+#endif
+}
+
+#endif
diff --git a/drivers/net/bcmbca/xrdp/rdp_drv_sbpm.c b/drivers/net/bcmbca/xrdp/rdp_drv_sbpm.c
new file mode 100644
index 0000000000..6de9162cc9
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/rdp_drv_sbpm.c
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "rdd_data_structures.h"
+
+typedef char bdmf_boolean;
+
+#define SBPM_INIT_OFFSET                    (SBPM_MAX_BUFFER_NUMBER)
+#define SBPM_MAX_NUM_OF_BNS                 (SBPM_MAX_BUFFER_NUMBER + 1)
+
+#define MIN(a, b) ((a) >= (b) ? (b) : (a))
+
+#define SBPM_BUF_SIZE 128
+#define SBPM_MAX_NUM_OF_ITERS 1000
+#define HEADROOM_SIZE 18
+
+#define SBPM_REGS_BN_ALLOC_RPLY_REG_OFFSET 0x00000008
+#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_REG_OFFSET 0x00000038
+#define SBPM_REGS_BN_CONNECT_RPLY_REG_OFFSET 0x00000020
+#define SBPM_REGS_BN_ALLOC_REG_OFFSET 0x00000004
+#define SBPM_REGS_BN_CONNECT_REG_OFFSET 0x0000001c
+#define SBPM_INVALID_BUFFER_NUMBER 16383
+
+static void _ag_drv_sbpm_regs_get_next_set(uint16_t bn)
+{
+	writel(bn << 0, SBPM_ADDRS+0x00000024);
+}
+
+static void _ag_drv_sbpm_regs_bn_alloc_set(uint8_t sa)
+{
+	writel(sa << 14, SBPM_ADDRS+SBPM_REGS_BN_ALLOC_REG_OFFSET);
+}
+
+static void _ag_drv_sbpm_regs_bn_connect_set(uint16_t bn, bdmf_boolean ack_req,
+	bdmf_boolean wr_req, uint16_t pointed_bn)
+{
+	writel(bn << 0 | ack_req << 14 | wr_req << 15 | pointed_bn << 16,
+		SBPM_ADDRS+SBPM_REGS_BN_CONNECT_REG_OFFSET);
+}
+
+static void _ag_drv_sbpm_regs_bn_free_without_contxt_set(uint16_t head_bn,
+	uint8_t sa, bdmf_boolean ack_req)
+{
+	writel(head_bn << 0 | sa << 14 | ack_req << 31,
+		SBPM_ADDRS+SBPM_REGS_BN_FREE_WITHOUT_CONTXT_REG_OFFSET);
+}
+
+static void _ag_drv_sbpm_regs_bn_free_without_contxt_rply_get(
+	bdmf_boolean *free_ack, bdmf_boolean *rdy)
+{
+	uint32_t reg_regs_bn_free_without_contxt_rply =
+		readl(SBPM_ADDRS+0x0000003c);
+
+	*free_ack =
+		(((reg_regs_bn_free_without_contxt_rply) & 0x00000001) >> 0);
+	*rdy = (((reg_regs_bn_free_without_contxt_rply) & 0x80000000) >> 31);
+}
+
+static void _ag_drv_sbpm_regs_bn_alloc_rply_get(bdmf_boolean *alloc_bn_valid,
+	uint16_t *alloc_bn, bdmf_boolean *rdy)
+{
+	uint32_t reg_regs_bn_alloc_rply =
+		readl(SBPM_ADDRS+SBPM_REGS_BN_ALLOC_RPLY_REG_OFFSET);
+
+	*alloc_bn_valid = (((reg_regs_bn_alloc_rply) & 0x00000001) >> 0);
+	*alloc_bn = (((reg_regs_bn_alloc_rply) & 0x00007ffe) >> 1);
+	*rdy = (((reg_regs_bn_alloc_rply) & 0x80000000) >> 31);
+}
+
+static void _ag_drv_sbpm_regs_bn_connect_rply_get(bdmf_boolean *connect_ack,
+	bdmf_boolean *busy, bdmf_boolean *rdy)
+{
+	uint32_t reg_regs_bn_connect_rply =
+		readl(SBPM_ADDRS+SBPM_REGS_BN_CONNECT_RPLY_REG_OFFSET);
+
+	*connect_ack = (((reg_regs_bn_connect_rply) & 0x00000001) >> 0);
+	*busy = (((reg_regs_bn_connect_rply) & 0x40000000) >> 30);
+	*rdy = (((reg_regs_bn_connect_rply) & 0x80000000) >> 31);
+}
+
+struct sbpm_regs_get_next_rply
+{
+	bdmf_boolean bn_valid;
+	uint16_t next_bn;
+	bdmf_boolean bn_null;
+	uint8_t mcnt_val;
+	bdmf_boolean busy;
+	bdmf_boolean rdy;
+};
+
+static void _ag_drv_sbpm_regs_get_next_rply_get(
+	struct sbpm_regs_get_next_rply *regs_get_next_rply)
+{
+	uint32_t get_next_rply = readl(SBPM_ADDRS+0x00000028);
+
+	regs_get_next_rply->bn_valid = (((get_next_rply) & 0x00000001) >> 0);
+	regs_get_next_rply->bn_null = (((get_next_rply) & 0x00008000) >> 15);
+	regs_get_next_rply->next_bn = (((get_next_rply) & 0x00007ffe) >> 1);
+	regs_get_next_rply->mcnt_val = (((get_next_rply) & 0x00ff0000) >> 16);
+	regs_get_next_rply->busy = (((get_next_rply) & 0x40000000) >> 30);
+}
+
+int drv_sbpm_free_list(uint16_t head_bn)
+{
+	int num_of_iters;
+	bdmf_boolean free_ack;
+	bdmf_boolean rdy;
+
+	_ag_drv_sbpm_regs_bn_free_without_contxt_set(head_bn, HEADROOM_SIZE, 1);
+	for (num_of_iters = 0; num_of_iters < SBPM_MAX_NUM_OF_ITERS;
+		num_of_iters++) {
+		_ag_drv_sbpm_regs_bn_free_without_contxt_rply_get(&free_ack,
+			&rdy);
+		if (rdy)
+			break;
+	}
+
+	if (free_ack == 0) {
+		printf("Failed to release bn =%d free_ack=0\n", head_bn);
+		return EFAULT;
+	}
+
+	if (num_of_iters == SBPM_MAX_NUM_OF_ITERS) {
+		printf("Failed to release bn=%d max_iter\n", head_bn);
+		return EFAULT;
+	}
+
+	return 0;
+}
+
+static void drv_sbpm_copy_buf_to_bn(uint16_t bn, uint32_t headroom,
+	uint8_t *data, uint32_t size)
+{
+	void *foo = (void *)(unsigned long)(PSRAM_MEM_ADDRS + bn*SBPM_BUF_SIZE);
+
+	memcpy(foo + headroom, data, MIN(size, SBPM_BUF_SIZE - headroom));
+}
+
+static int drv_sbpm_alloc_single(uint32_t size, uint32_t headroom,
+	uint8_t *data, uint16_t *bn)
+{
+	int rc, num_of_iters;
+	bdmf_boolean alloc_bn_valid;
+	uint16_t alloc_bn;
+	bdmf_boolean rdy;
+
+	_ag_drv_sbpm_regs_bn_alloc_set(30);
+	for (num_of_iters = 0; num_of_iters < SBPM_MAX_NUM_OF_ITERS;
+		num_of_iters++) {
+		_ag_drv_sbpm_regs_bn_alloc_rply_get(&alloc_bn_valid, &alloc_bn,
+			&rdy);
+		if (rdy && alloc_bn_valid)
+			break;
+	}
+
+	if (num_of_iters == SBPM_MAX_NUM_OF_ITERS) {
+		printf("%s: alloc single\n", __FUNCTION__);
+		rc = -EFAULT;
+		goto error;
+	}
+
+	drv_sbpm_copy_buf_to_bn(alloc_bn, headroom, data, size);
+	*bn = alloc_bn;
+	return 0;
+
+error:
+	*bn = SBPM_INVALID_BUFFER_NUMBER;
+	return rc;
+}
+
+static int drv_sbpm_connect_single(uint16_t bn, uint16_t next_bn)
+{
+	int num_of_iters;
+	bdmf_boolean connect_ack, busy, rdy;
+
+	_ag_drv_sbpm_regs_bn_connect_set(bn, 1, 0, next_bn);
+	for (num_of_iters = 0; num_of_iters < SBPM_MAX_NUM_OF_ITERS;
+			num_of_iters++) {
+	    _ag_drv_sbpm_regs_bn_connect_rply_get(&connect_ack, &busy, &rdy);
+	    if (rdy && connect_ack)
+		    break;
+    }
+
+    if (num_of_iters == SBPM_MAX_NUM_OF_ITERS)
+	    return -EFAULT;
+
+    return 0;
+}
+
+int drv_sbpm_alloc_list(uint32_t size, uint32_t headroom, uint8_t *data,
+	uint16_t *bn0, uint16_t *bn1, uint8_t *bns_num)
+{
+	uint16_t head_bn = SBPM_INVALID_BUFFER_NUMBER, new_bn, curr_bn;
+	int rc, _size, sbpm_buf_size_wo_headroom;
+	uint8_t _bns_num = 1;
+
+	_size = (int)size;
+	sbpm_buf_size_wo_headroom = SBPM_BUF_SIZE - headroom;
+
+	/* Allocate first; then in loop, copy and allocate next as long as
+	 * needed. */
+	rc = drv_sbpm_alloc_single(_size, headroom, data, &head_bn);
+	if (rc)
+		goto error;
+
+	if (_size <= sbpm_buf_size_wo_headroom) {
+		/* We are done, short packet */
+		new_bn = head_bn; /* Last BN = head BN */
+		goto exit;
+	}
+
+	for (_size -= sbpm_buf_size_wo_headroom,
+		data += sbpm_buf_size_wo_headroom, curr_bn = head_bn;
+		_size > 0;
+		_size -= SBPM_BUF_SIZE, data += SBPM_BUF_SIZE,
+		curr_bn = new_bn) {
+		rc = drv_sbpm_alloc_single(_size, 0, data, &new_bn);
+		if (rc)
+			goto error;
+
+		rc = drv_sbpm_connect_single(curr_bn, new_bn);
+		if (rc) {
+			drv_sbpm_free_list(new_bn);
+			goto error;
+		}
+
+		_bns_num++;
+	}
+
+exit:
+	if (bn0)
+		*bn0 = head_bn;
+	if (bn1)
+		*bn1 = new_bn;
+	if (bns_num)
+		*bns_num = _bns_num;
+
+	return 0;
+
+error:
+	if (head_bn != SBPM_INVALID_BUFFER_NUMBER)
+		drv_sbpm_free_list(head_bn);
+
+	if (bn0)
+		*bn0 = SBPM_INVALID_BUFFER_NUMBER;
+	if (bn1)
+		*bn1 = SBPM_INVALID_BUFFER_NUMBER;
+	if (bns_num)
+		*bns_num = 0;
+
+	return rc;
+}
+
+uint16_t drv_sbpm_get_next_bn(int16_t bn)
+{
+	int rc = 0;
+	struct sbpm_regs_get_next_rply next_rply = {};
+	uint32_t next_bn = SBPM_INVALID_BUFFER_NUMBER;
+
+	_ag_drv_sbpm_regs_get_next_set(bn);
+	while (1) {
+		_ag_drv_sbpm_regs_get_next_rply_get(&next_rply);
+		if (!next_rply.busy)
+			break;
+	}
+
+	if (rc)
+		return SBPM_INVALID_BUFFER_NUMBER;
+
+	if (next_rply.bn_valid) {
+		if (!next_rply.bn_null)
+			next_bn = next_rply.next_bn;
+	}
+	else
+		printf(" ### BN_NULL (0x%x)\n", next_rply.next_bn);
+
+	if (next_rply.mcnt_val != 0)
+		printf("bn: %d, mcast value: %d\n", bn, next_rply.mcnt_val);
+
+	return next_bn;
+}
+
+static void _drv_sbpm_copy_single(int bn, uint8_t **data, int skip)
+{
+	void *foo = (void *)(unsigned long)(PSRAM_MEM_ADDRS + bn*SBPM_BUF_SIZE);
+
+	memcpy(*data, foo + skip, SBPM_BUF_SIZE - skip);
+	*data += SBPM_BUF_SIZE - skip;
+}
+
+/* this funnction copy list of sbpm to buffer */
+int drv_sbpm_copy_list(uint16_t bn, uint8_t *dest_buffer)
+{
+	uint16_t next_bn;
+	int i;
+
+	_drv_sbpm_copy_single(bn, &dest_buffer, HEADROOM_SIZE);
+
+	for (i = 0; i < SBPM_MAX_NUM_OF_BNS; i++) {
+		next_bn = drv_sbpm_get_next_bn(bn);
+		if (next_bn == SBPM_INVALID_BUFFER_NUMBER)
+			break;
+
+		bn = next_bn;
+		_drv_sbpm_copy_single(bn, &dest_buffer, 0);
+	}
+
+	if (i == SBPM_MAX_NUM_OF_BNS) {
+		printf("===== BAD LIST ALLOCATED, STOP SCANNING...., original "\
+			"bn is %d\n", bn);
+		return -EFAULT;
+	}
+
+	return 0;
+}
diff --git a/drivers/net/bcmbca/xrdp/rdpa_types.h b/drivers/net/bcmbca/xrdp/rdpa_types.h
new file mode 100644
index 0000000000..10d4da19a1
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp/rdpa_types.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#ifndef _RDPA_TYPES_H_
+#define _RDPA_TYPES_H_
+
+/** \defgroup types Commonly used types and constants
+ * @{
+ */
+
+#include <bdmf_data_types.h>
+
+
+/** EMAC id */
+typedef enum
+{
+    rdpa_emac0,             /**< EMAC0 */
+    rdpa_emac1,             /**< EMAC1 */
+    rdpa_emac2,             /**< EMAC2 */
+    rdpa_emac3,             /**< EMAC3 */
+    rdpa_emac4,             /**< EMAC4 */
+    rdpa_emac5,             /**< EMAC5 */
+    rdpa_emac6,             /**< EMAC6 */
+    rdpa_emac7,             /**< EMAC7 */
+    rdpa_emac__num_of,      /* Max number of EMACs */
+    rdpa_emac_none,      /**< Indicates virtual port */
+} rdpa_emac;
+/** EMAC rates */
+typedef enum
+{
+    rdpa_emac_rate_10m,     /**< 10 Mbps */
+    rdpa_emac_rate_100m,    /**< 100 Mbps */
+    rdpa_emac_rate_1g,      /**< 1 Gbps */
+    rdpa_emac_rate_2_5g,    /**< 2.5 Gbps */
+
+    rdpa_emac_rate__num_of, /* Number of rates */
+} rdpa_emac_rate;
+
+/** EMAC configuration */
+typedef struct
+{
+    char loopback;      /**< 1 = line loopback */
+    rdpa_emac_rate rate;       /**< EMAC rate */
+    char generate_crc;  /**< 1 = generate CRC */
+    char full_duplex;   /**< 1 = full duplex */
+    char pad_short;     /**< 1 = pad short frames */
+    char allow_too_long;/**< 1 = allow long frames */
+    char check_length;  /**< 1 = check frame length */
+    uint32_t preamble_length;   /**< Preamble length */
+    uint32_t back2back_gap;     /**< Back2Back inter-packet gap */
+    uint32_t non_back2back_gap; /**< Non Back2Back inter-packet gap */
+    uint32_t min_interframe_gap; /**< Min inter-frame gap */
+    char rx_flow_control;/**< 1 = enable RX flow control */
+    char tx_flow_control;/**< 1 = enable TX flow control */
+} rdpa_emac_cfg_t;
+/** RX RMON counters.
+ * Underlying type for emac_rx_stat aggregate type.
+ */
+typedef struct
+{
+    uint32_t byte;              /**< Receive Byte Counter */
+    uint32_t packet;            /**< Receive Packet Counter */
+    uint32_t frame_64;          /**< Receive 64 Byte Frame Counter */
+    uint32_t frame_65_127;      /**< Receive 65 to 127 Byte Frame Counter */
+    uint32_t frame_128_255;     /**< Receive 128 to 255 Byte Frame Counter */
+    uint32_t frame_256_511;     /**< Receive 256 to 511 Byte Frame Counter */
+    uint32_t frame_512_1023;    /**< Receive 512 to 1023 Byte Frame Counter */
+    uint32_t frame_1024_1518;   /**< Receive 1024 to 1518 Byte Frame Counter */
+    uint32_t frame_1519_mtu;    /**< Receive 1519 to MTU Frame Counter */
+    uint32_t multicast_packet;  /**< Receive Multicast Packet */
+    uint32_t broadcast_packet;  /**< Receive Broadcast Packet */
+    uint32_t unicast_packet;    /**< Receive Unicast Packet */
+    uint32_t alignment_error;   /**< Receive Alignment error */
+    uint32_t frame_length_error;/**< Receive Frame Length Error Counter */
+    uint32_t code_error;        /**< Receive Code Error Counter */
+    uint32_t carrier_sense_error;/**< Receive Carrier sense error */
+    uint32_t fcs_error;         /**< Receive FCS Error Counter */
+    uint32_t control_frame;     /**< Receive Control Frame Counter */
+    uint32_t pause_control_frame;/**< Receive Pause Control Frame */
+    uint32_t unknown_opcode;    /**< Receive Unknown opcode */
+    uint32_t undersize_packet;  /**< Receive Undersize Packet */
+    uint32_t oversize_packet;   /**< Receive Oversize Packet */
+    uint32_t fragments;         /**< Receive Fragments */
+    uint32_t jabber;            /**< Receive Jabber counter */
+    uint32_t overflow;          /**< Receive Overflow counter */
+} rdpa_emac_rx_stat_t;
+/** Tx RMON counters.
+ * Underlying type for emac_tx_stat aggregate type.
+ */
+typedef struct
+{
+    uint32_t byte;              /**< Transmit Byte Counter */
+    uint32_t packet;            /**< Transmit Packet Counter */
+    uint32_t frame_64;          /**< Transmit 64 Byte Frame Counter */
+    uint32_t frame_65_127;      /**< Transmit 65 to 127 Byte Frame Counter */
+    uint32_t frame_128_255;     /**< Transmit 128 to 255 Byte Frame Counter */
+    uint32_t frame_256_511;     /**< Transmit 256 to 511 Byte Frame Counter */
+    uint32_t frame_512_1023;    /**< Transmit 512 to 1023 Byte Frame Counter */
+    uint32_t frame_1024_1518;   /**< Transmit 1024 to 1518 Byte Frame Counter */
+    uint32_t frame_1519_mtu;    /**< Transmit 1519 to MTU Frame Counter */
+    uint32_t fcs_error;         /**< Transmit FCS Error */
+    uint32_t multicast_packet;  /**< Transmit Multicast Packet */
+    uint32_t broadcast_packet;  /**< Transmit Broadcast Packet */
+    uint32_t unicast_packet;    /**< Transmit Unicast Packet */
+    uint32_t excessive_collision; /**< Transmit Excessive collision counter */
+    uint32_t late_collision;    /**< Transmit Late collision counter */
+    uint32_t single_collision;  /**< Transmit Single collision frame counter */
+    uint32_t multiple_collision;/**< Transmit Multiple collision frame counter */
+    uint32_t total_collision;   /**< Transmit Total Collision Counter */
+    uint32_t pause_control_frame; /**< Transmit PAUSE Control Frame */
+    uint32_t deferral_packet;   /**< Transmit Deferral Packet */
+    uint32_t excessive_deferral_packet; /**< Transmit Excessive Deferral Packet */
+    uint32_t jabber_frame;      /**< Transmit Jabber Frame */
+    uint32_t control_frame;     /**< Transmit Control Frame */
+    uint32_t oversize_frame;    /**< Transmit Oversize Frame counter */
+    uint32_t undersize_frame;   /**< Transmit Undersize Frame */
+    uint32_t fragments_frame;   /**< Transmit Fragments Frame counter */
+    uint32_t error;             /**< Transmission errors*/
+    uint32_t underrun;          /**< Transmission underrun */
+} rdpa_emac_tx_stat_t;
+/** Emac statistics */
+typedef struct
+{
+    rdpa_emac_rx_stat_t rx; /**< Emac Receive Statistics */
+    rdpa_emac_tx_stat_t tx; /**< Emac Transmit Statistics */
+} rdpa_emac_stat_t;
+#endif /* _RDPA_TYPES_H_ */
+
diff --git a/drivers/net/bcmbca/xrdp_full/Makefile b/drivers/net/bcmbca/xrdp_full/Makefile
new file mode 100755
index 0000000000..6135301d17
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp_full/Makefile
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2019 Broadcom Ltd
+#
+
+ifdef CONFIG_BCMBCA_PMC
+EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/mach-bcmbca/pmc
+endif
+
+obj-y += ../xrdp/bcmbca_xrdp_api.o
+EXTRA_CFLAGS += -DNO_ACCESS_LOGGING
+# Flags for bcmbca_xrdp_api
+ifdef CONFIG_BCMBCA_XRDP_PON
+EXTRA_CFLAGS += -DXRDP_SBPM -DGEN45
+#obj-y += rdp_drv_sbpm.o
+else # CONFIG_BCMBCA_XRDP_DSL
+EXTRA_CFLAGS += -DXRDP_DIRECT
+endif
+
+BRCM_CHIP = $(patsubst "bcm%",%,$(CONFIG_SYS_SOC))
+CUR_DIR := $(dir $(lastword $(MAKEFILE_LIST)))
+BLD_DIR = $(shell pwd)
+BLD_DIR :=$(subst /bootloaders/, /bootloaders/,$(BLD_DIR))$
+BLD_DIR :=$(word 1,$(BLD_DIR))
+TOP_DIR :=$(BLD_DIR)/rdp
+RDP_PROJECT = XRDP_CFE2
+PROJECTS_DIR := $(TOP_DIR)/projects
+PROJECT_DIR := $(PROJECTS_DIR)/$(RDP_PROJECT)
+
+ifeq ($(strip $(BRCM_CHIP)),6858)
+CHIP_VER = B0
+else
+CHIP_VER = A0
+endif
+
+PROJ_DRV_SRC_LIST := $(PROJECT_DIR)/BCM$(BRCM_CHIP)_$(CHIP_VER)_sources.list
+PROJ_FW_SRC_LIST := $(PROJECT_DIR)/BCM$(BRCM_CHIP)_$(CHIP_VER)_fw_sources.list
+
+ifdef CONFIG_BCMBCA_IKOS
+KBUILD_CPPFLAGS += -DCONFIG_BRCM_IKOS
+endif
+
+LN = ln -sf
+MV = mv -f
+RM = rm -rf
+
+include $(PROJECT_DIR)/make.proj_flags
+
+EXTRA_CFLAGS += -I$(PROJECT_DIR)/ -I$(PROJECT_DIR)/drivers/rdp_subsystem/
+EXTRA_CFLAGS += -I$(PROJECT_DIR)/drivers/rdp_subsystem/BCM$(BRCM_CHIP) -I$(TOP_DIR)/drivers/bdmf/shell
+EXTRA_CFLAGS += -I$(TOP_DIR)/drivers/rdpa_gpl/include/ -I$(TOP_DIR)/drivers/bdmf/system/sim
+EXTRA_CFLAGS += -I$(TOP_DIR)/drivers/bdmf/system
+EXTRA_CFLAGS += -I$(TOP_DIR)/drivers/bdmf/framework
+EXTRA_CFLAGS += -I$(TOP_DIR)/drivers/bdmf/interface
+EXTRA_CFLAGS += -I$(BLD_DIR)/shared/opensource/include/bcm963xx
+EXTRA_CFLAGS += -I$(BLD_DIR)/bcmdrivers/opensource/include/bcm963xx
+
+EXTRA_CFLAGS += -include bdmf_errno.h -include stdio.h 
+EXTRA_CFLAGS += -DBDMF_SESSION_H -D_BDMF_INTERFACE_H_ -D_BDMF_SYSTEM_H_ -DBDMF_MON_H -UBDMF_DEBUG -UBDMF_SYSTEM_SIM -UUSE_BDMF_SHELL -DBDMF_NO_TRACE 
+EXTRA_CFLAGS += -DRU_USE_STDC -DRU_INCLUDE_DESC=0 -DRU_INCLUDE_FIELD_DB=0 -DRU_FIELD_CHECK_ENABLE=0 -DRU_INCLUDE_ACCESS=0 
+EXTRA_CFLAGS += -DXRDP -DXRDP_NO_SWAP -DFIRMWARE_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_BCM9$(BRCM_CHIP) $(PROJ_DEFS) -UVALIDATE_PARMS -Dbdmf_trace=printf -D__BCM_MAP_PART_H
+
+ifneq ($(findstring _$(strip $(BRCM_CHIP))_,_6858_6856_),)
+EXTRA_CFLAGS += -DPHYS_ADDR_64BIT
+endif
+
+ifeq ("$(CONFIG_XRDP_GPL_GEN)", "1")
+EXTRA_CFLAGS += -DCONFIG_GPL_RDP_GEN
+endif
+
+xrdp_full-objs := $(patsubst %.c, %.o, $(shell cd $(CUR_DIR) && ls *.c))
+obj-y += xrdp_full.o
+
+$(obj)/xrdp_full.o: prepare_links
+#	$(CC) $(KBUILD_CPPFLAGS) $(EXTRA_CFLAGS) $(shell ls $(CUR_DIR)*.c) $(LDFLAGS) -o $(obj)/xrdp_full.o
+
+.PHONY: clean
+clean:
+	$(RM) *.o;
+	find . -name "*.[c,h]" | grep -v Makefile | grep -v bcmbca_xrdp_api_full.c | xargs $(RM)
+
+.PHONY: prepare_links
+prepare_links:
+	$(foreach file,$(shell grep "\.h" $(PROJ_FW_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(file) $(CUR_DIR)))
+	$(foreach file,$(shell grep "drivers/rdd" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(file) $(CUR_DIR)))
+	$(foreach file,$(shell grep "firmware/.*\.h" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(file) $(CUR_DIR)))
+	$(foreach file,$(shell grep "firmware/.*rdd_.*\.c" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(file) $(CUR_DIR)))
+	$(foreach file,$(shell grep "drivers/rdp_subsystem" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(file) $(CUR_DIR)))
+	$(foreach file,$(shell grep "firmware_bin/" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(file) $(CUR_DIR)))
+	$(foreach file,$(shell grep "rdp_drv" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(file) $(CUR_DIR)))
+	$(foreach file,$(shell grep "drivers/bdmf" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile" | grep -v "*.c"),$(shell $(LN) $(TOP_DIR)/$(file) $(CUR_DIR)))
+	$(foreach file,$(shell grep "drivers/rdpa_gpl/include" $(PROJ_DRV_SRC_LIST) | grep -v "^#" | grep -v "Makefile"),$(shell $(LN) $(TOP_DIR)/$(file) $(CUR_DIR)))
+
diff --git a/drivers/net/bcmbca/xrdp_full/REDUCED_XRDP_README b/drivers/net/bcmbca/xrdp_full/REDUCED_XRDP_README
new file mode 100644
index 0000000000..9023a119bd
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp_full/REDUCED_XRDP_README
@@ -0,0 +1,59 @@
+REDUCED XRDP UBOOT README
+
+1) The XRDP_ETH driver can be compiled in two modes, GPL and FULL mode, the
+   first compiles with bare minimum of RDP souces, and the later is used for
+   generating new GPL FW access_logging.
+   The main difference in compilation, is that GPL mode compiles against
+   xrdp/ folder, and recorded data_path_$(CHIP_ID).c files, and FULL mode
+   compiles the xrdp_full/ folder and sources from the XRDP_CFE2 project.
+
+   XRDP datapath logic is implemented in two files: xrdp/bcmbca_xrdp_api.o,
+   used in both modes, and xrdp/bcmbca_xrdp_api_full.o used only in FULL mode.
+
+2) New devices:
+   When a new device is migrated, make sure the xdp Makefiles are enabling the
+   correct operation mode, either XRDP_DIRECT or XRDP_SBPM.
+
+   a) FULL mode with REDUCED_XRDP support is implemented by linking files from
+      rdp XRDP_CFE2 project according to BRCM_CHIP and CHIP_VER.
+      This is done in u-boot-2019.07/drivers/net/bcmbca/xrdp_full/Makefile:
+      BCM$(BRCM_CHIP)_$(CHIP_VER)_sources.list and
+      BCM$(BRCM_CHIP)_$(CHIP_VER)_fw_sources.list will be used as input files
+      for compilation of the project, and make.proj_flags will be include for
+      project flags.
+
+    b) GPL mode support:
+       - Add base addresses in rdp_data_structure.h
+       - If a register map is different, consider adding new GEN macro's for
+         new platform
+
+3) Compiling
+   a. Compile a regular full image (not just uboot); this will build the GPL
+      by default
+   > make PROFILE=<target>
+
+   GPL mode is the default, but full mode with GPL_GEN can be compiled using:
+   b. clean uboot
+   > make uboot_clean
+
+   c. Built with XRDP_FULL
+   > make CONFIG_XRDP_FULL=1 CONFIG_XRDP_GPL_GEN=1 PROFILE=<target> uboot
+
+   XXX: until fixed, FULL mode requires to run make twice for the first time so
+        linked files depencency exists
+
+4) Create access logging for GPL mode:
+   In XRDP in FULL mode, all register and SRAM accesses will be logged to the
+   console.
+   Using gen_data_path_init_data.sh tool, it can be converted to a
+   data_path_<chip_id>.c file, which should be submitted into the GPL folder.
+
+   Usage:
+    1) Compile uboot with XRDP in FULL mode with GPL_GEN, as mentioned in (3)
+       and boot the image into uboot.
+    2) Clear Terminal console, power up the board and stop in U-Boot.
+    3) Save console log to a file (e.g., /tmp/session.log)
+    4) Generate GPL access_logging by running:
+       gen_data_path_init_data.sh /tmp/session.log data_path_<chip_id>.c 
+       and move it to the xrdp GPL folder.
+
diff --git a/drivers/net/bcmbca/xrdp_full/bcmbca_xrdp_api_full.c b/drivers/net/bcmbca/xrdp_full/bcmbca_xrdp_api_full.c
new file mode 100644
index 0000000000..467a6d9aff
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp_full/bcmbca_xrdp_api_full.c
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include "data_path_init_basic.h"
+#include "access_logging.h"
+
+static int cpu_ring_and_scheduler_init(void)
+{
+    int i;
+#if defined(CONFIG_BCM6858)
+    uint32_t flow_map[] = {BB_ID_RX_BBH_4, BB_ID_RX_BBH_1, BB_ID_RX_BBH_2, BB_ID_RX_BBH_3, BB_ID_RX_BBH_0, BB_ID_RX_BBH_5, BB_ID_RX_BBH_6};
+#elif defined(CONFIG_BCM6846) || defined(CONFIG_BCM6878)
+    uint32_t flow_map[] = { BB_ID_RX_BBH_0, BB_ID_RX_BBH_1, BB_ID_RX_BBH_2, BB_ID_RX_BBH_3, BB_ID_RX_BBH_4 };
+#elif defined(CONFIG_BCM6856)
+    uint32_t flow_map[] = { BB_ID_RX_BBH_0, BB_ID_RX_BBH_1, BB_ID_RX_BBH_2, BB_ID_RX_BBH_3, BB_ID_RX_BBH_4, BB_ID_RX_BBH_5 };
+#elif defined(CONFIG_BCM63146)
+	uint32_t flow_map[] = {BB_ID_RX_BBH_0, BB_ID_RX_BBH_1, BB_ID_RX_BBH_2,
+			       BB_ID_RX_BBH_3, BB_ID_RX_BBH_4, BB_ID_RX_BBH_5,
+			       BB_ID_RX_BBH_6, BB_ID_RX_BBH_7};
+#elif defined(CONFIG_BCM4912)
+	uint32_t flow_map[] = {BB_ID_RX_BBH_0, BB_ID_RX_BBH_1, BB_ID_RX_BBH_2,
+			       BB_ID_RX_BBH_3, BB_ID_RX_BBH_4, BB_ID_RX_BBH_5,
+			       BB_ID_RX_BBH_6, BB_ID_RX_BBH_7, BB_ID_RX_BBH_8};
+#endif
+    uint32_t num_of_queues = sizeof(flow_map)/sizeof(flow_map[0]);
+
+    for (i = 0; i < num_of_queues; i++) {
+        /* basic scheduler configuration */
+        rdd_rx_flow_cfg((256 + flow_map[i]), 0, i, 0);
+    }
+
+    return 0;
+}
+
+int xrdp_data_path_init(void)
+{
+    int rc;
+    dpi_params_t xrdp_init_params;
+
+    memset(&xrdp_init_params,0,sizeof(xrdp_init_params));
+
+    ACCESS_LOG_ENABLE_SET(1);
+
+    xrdp_init_params.mtu_size = 1518;
+
+#ifndef CONFIG_BCMBCA_IKOS
+    rc = get_rdp_freq(&xrdp_init_params.runner_freq);
+    if (rc) {
+        printf("Failed to get runner frequency %d\n", rc);
+        goto exit;
+    }
+#endif
+
+    rc = data_path_init_basic(&xrdp_init_params); 
+    if (rc) {
+        printf("data path init failed\n");
+        goto exit;
+    }
+
+    rc = cpu_ring_and_scheduler_init();
+    if (rc) {
+        printf("scheduler configuration failed\n");
+        goto exit;
+    }
+
+    ACCESS_LOG_ENABLE_SET(0);
+
+exit:
+    return rc;
+}
diff --git a/drivers/net/bcmbca/xrdp_full/gen_data_path_init_data.sh b/drivers/net/bcmbca/xrdp_full/gen_data_path_init_data.sh
new file mode 100755
index 0000000000..1e70e64c1f
--- /dev/null
+++ b/drivers/net/bcmbca/xrdp_full/gen_data_path_init_data.sh
@@ -0,0 +1,24 @@
+#!/bin/bash
+
+if [[ $# != 2 ]]; then
+   echo "$0 console_output_file_name data_path_<chip_id>.c"
+   exit -1
+fi
+dos2unix $1
+cat <<EOT > $2
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include "access_logging.h"
+
+const access_log_tuple_t init_data[] = {
+EOT
+
+grep '^>>>' $1 | awk '{print "\t{", $2, ",", $3,"},"}' >> $2
+
+cat <<EOT >> $2
+    { (ACCESS_LOG_OP_STOP << 24), 0 }
+};
+EOT
diff --git a/drivers/pinctrl/broadcom/Kconfig b/drivers/pinctrl/broadcom/Kconfig
index b01b725583..9297fde4f6 100644
--- a/drivers/pinctrl/broadcom/Kconfig
+++ b/drivers/pinctrl/broadcom/Kconfig
@@ -13,3 +13,11 @@ config PINCTRL_BCM6838
 	help
 	   Support pin multiplexing and pin configuration control on
 	   Broadcom's 6838 family of SoCs.
+
+config PINCTRL_BCMBCA
+	depends on ARCH_BCMBCA && PINCTRL_FULL && OF_CONTROL
+	default n
+	bool "Broadcom BCA pin control driver"
+	help
+	   Support pin multiplexing and pin configuration control on
+	   Broadcom's BCA SOCs.
diff --git a/drivers/pinctrl/broadcom/Makefile b/drivers/pinctrl/broadcom/Makefile
index f94f3ce7c9..13a747b712 100644
--- a/drivers/pinctrl/broadcom/Makefile
+++ b/drivers/pinctrl/broadcom/Makefile
@@ -6,3 +6,5 @@
 
 obj-$(CONFIG_PINCTRL_BCM283X) += pinctrl-bcm283x.o
 obj-$(CONFIG_PINCTRL_BCM6838) += pinctrl-bcm6838.o
+obj-$(CONFIG_PINCTRL_BCMBCA) += pinctrl-bcmbca.o
+
diff --git a/drivers/pinctrl/broadcom/pinctrl-bcmbca.c b/drivers/pinctrl/broadcom/pinctrl-bcmbca.c
new file mode 100644
index 0000000000..49ca745b24
--- /dev/null
+++ b/drivers/pinctrl/broadcom/pinctrl-bcmbca.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <dm/pinctrl.h>
+#include "pinctrl.h"
+
+#define MAX_PIN_COUNT   50
+
+struct bcmbca_pinctrl_priv {
+	volatile struct pinctrl_reg *regp;
+    unsigned int gpio_mux;
+};
+
+int bcmbca_pinctrl_probe(struct udevice *dev)
+{
+	struct bcmbca_pinctrl_priv *priv = dev_get_priv(dev);
+    int ret;
+
+	priv->regp = (struct pinctrl_reg *)dev_remap_addr(dev);
+    ret = ofnode_read_u32(dev->node, "gpio-mux", &priv->gpio_mux);
+
+	return 0;
+}
+
+/*
+ * bcmbca_pinctrl_set_state_simple: pinctrl for a peripheral device.
+ * @dev: the pinctrl device
+ * @periph: the device to be configured
+ * @return: 0 in success
+ */
+static int bcmbca_pinctrl_set_state_simple(struct udevice *dev, struct udevice *periph)
+{
+	struct bcmbca_pinctrl_priv *priv = dev_get_priv(dev);
+
+	int size, len, i, ret;
+	uint32_t pin_arr[MAX_PIN_COUNT];
+	uint32_t phandle, function;
+	const fdt32_t *list;
+	ofnode arg;
+
+	/* check if the device specify what pins to configure */
+	list = dev_read_prop(periph, "pinctrl-0", &size);
+
+	if (list)
+	{
+		size /= sizeof (*list);
+
+		while(size--)
+		{
+			phandle = fdt32_to_cpu(*list++);
+
+			arg = ofnode_get_by_phandle(phandle);
+
+			if (ofnode_valid(arg))
+			{
+				ofnode_get_property(arg, "pins", &len);
+				len /= sizeof(u32);
+				ret = ofnode_read_u32_array(arg, "pins", pin_arr, len);
+				ret |= ofnode_read_u32(arg, "function", &function);
+				if (!ret)
+				{
+					for (i=0; i < len; i++)
+					{
+						bcmbca_pinmux_set(priv->regp, pin_arr[i], function);
+					}
+				}
+			}
+		}
+	}
+	else
+	{
+		if(dev_read_prop(periph, "pins", &len))
+		{
+			len /= sizeof(u32);
+			ret = dev_read_u32_array(periph, "pins", pin_arr, len);
+			ret |= dev_read_u32(periph, "function", &function);
+			if (!ret)
+			{
+				for (i=0; i < len; i++)
+				{
+					bcmbca_pinmux_set(priv->regp, pin_arr[i], function);
+				}
+			}
+		}
+	}
+	
+	return 0;
+
+}
+
+/*
+ * bcmbca_gpio_request: set pinctrl for a pin to gpio function.
+ * @dev: the pinctrl device
+ * @periph: the device to be configured
+ * @return: 0 in success
+ */
+static int bcmbca_gpio_request(struct udevice *dev, unsigned int selector)
+{
+	struct bcmbca_pinctrl_priv *priv = dev_get_priv(dev);
+    return bcmbca_pinmux_set(priv->regp, selector, priv->gpio_mux);
+}
+
+const struct pinctrl_ops bcmbca_pinctrl_ops = {
+	.set_state = pinctrl_generic_set_state,
+	.set_state_simple = bcmbca_pinctrl_set_state_simple,
+    .gpio_request_enable = bcmbca_gpio_request,
+};
+
+static const struct udevice_id bcmbca_pinctrl_match[] = {
+	{
+		.compatible = "brcm,bcmbca-pinctrl",
+	},
+};
+
+U_BOOT_DRIVER(bcmbca_pinctrl) = {
+	.name = "bcmbca_pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = bcmbca_pinctrl_match,
+	.ops = &bcmbca_pinctrl_ops,
+	.priv_auto_alloc_size = sizeof(struct bcmbca_pinctrl_priv),
+	.probe = bcmbca_pinctrl_probe,
+};
+
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9469147152..e350b1f1a6 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -59,7 +59,7 @@ config ATMEL_SPI
 
 config BCM63XX_HSSPI
 	bool "BCM63XX HSSPI driver"
-	depends on ARCH_BMIPS
+	depends on (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158 || ARCH_BCMBCA)
 	help
 	  Enable the BCM6328 HSSPI driver. This driver can be used to
 	  access the SPI NOR flash on platforms embedding this Broadcom
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 4f527fa74a..dfdcaf190f 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -75,6 +75,7 @@
 #define SPI_PFL_MODE_MDWRSZ_MASK	(1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
 #define SPI_PFL_MODE_3WIRE_SHIFT	20
 #define SPI_PFL_MODE_3WIRE_MASK		(1 << SPI_PFL_MODE_3WIRE_SHIFT)
+#define SPI_PFL_MODE_PREPEND_CNT_SHIFT	24
 
 /* SPI Ping-Pong FIFO registers */
 #define HSSPI_FIFO_SIZE			0x200
@@ -93,12 +94,17 @@
 #define HSSPI_FIFO_OP_CODE_W		(2 << HSSPI_FIFO_OP_CODE_SHIFT)
 #define HSSPI_FIFO_OP_CODE_R		(3 << HSSPI_FIFO_OP_CODE_SHIFT)
 
+#define HSSPI_MAX_DATA_SIZE		(HSSPI_FIFO_SIZE - HSSPI_FIFO_OP_SIZE)
+
 struct bcm63xx_hsspi_priv {
 	void __iomem *regs;
 	ulong clk_rate;
 	uint8_t num_cs;
 	uint8_t cs_pols;
 	uint speed;
+	uint max_speed;
+	int use_cswar;
+	uint32_t prepend_bytes;
 };
 
 static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
@@ -120,9 +126,9 @@ static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode)
 
 	/* clock polarity */
 	if (mode & SPI_CPOL)
-		setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
+		setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
 	else
-		clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
+		clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
 
 	return 0;
 }
@@ -131,7 +137,10 @@ static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed)
 {
 	struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
 
-	priv->speed = speed;
+	if (priv->max_speed && speed > priv->max_speed) {
+		priv->speed = priv->max_speed;
+	} else
+		priv->speed = speed;
 
 	return 0;
 }
@@ -146,7 +155,7 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
 	set = DIV_ROUND_UP(2048, set);
 	set &= SPI_PFL_CLK_FREQ_MASK;
 	set |= SPI_PFL_CLK_RSTLOOP_MASK;
-	writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
+	writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
 
 	/* profile signal */
 	set = 0;
@@ -164,34 +173,156 @@ static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
 	if (priv->speed > SPI_MAX_SYNC_CLOCK)
 		set |= SPI_PFL_SIG_ASYNCIN_MASK;
 
-	clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
+	clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
 
 	/* global control */
 	set = 0;
 	clr = 0;
 
-	/* invert cs polarity */
-	if (priv->cs_pols & BIT(plat->cs))
-		clr |= BIT(plat->cs);
-	else
-		set |= BIT(plat->cs);
-
-	/* invert dummy cs polarity */
-	if (priv->cs_pols & BIT(!plat->cs))
-		clr |= BIT(!plat->cs);
-	else
-		set |= BIT(!plat->cs);
+	if (priv->use_cswar) {
+		/* invert cs polarity */
+		if (priv->cs_pols & BIT(plat->cs))
+			clr |= BIT(plat->cs);
+		else
+			set |= BIT(plat->cs);
+
+		/* invert dummy cs polarity */
+		if (priv->cs_pols & BIT(!plat->cs))
+			clr |= BIT(!plat->cs);
+		else
+			set |= BIT(!plat->cs);
+	} else {
+		if (priv->cs_pols & BIT(plat->cs))
+			set |= BIT(plat->cs);
+		else
+			clr |= BIT(plat->cs);
+	}
 
-	clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set);
+	clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);
 }
 
 static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
 {
 	/* restore cs polarities */
-	clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
+	clrsetbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
 			priv->cs_pols);
 }
 
+static int bcm63xx_hsspi_prepend_xfer(struct udevice *dev,
+				      unsigned int bitlen, const void *dout,
+				      void *din, unsigned long flags)
+{
+	struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
+	struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+	uint16_t opcode = 0;
+	uint32_t val;
+	size_t data_bytes = bitlen / 8;	
+	int ret;
+
+	/*
+	 * only support multiple half duplex write transfer + optional
+	 * full duplex read/write at the end.
+	 */  
+	if (flags & SPI_XFER_BEGIN) {
+		/* clear prepends */
+		priv->prepend_bytes = 0;
+	}
+
+	if (din) {
+		/* buffering reads not possible since cs is hw controlled */
+		if (!(flags & SPI_XFER_END)) {
+			printf("unable to buffer reads\n");
+			printf("set use_cs_workaround in dts to enable cs workaround\n");			
+			return -EINVAL;
+		}
+
+		/* check rx size */
+		if (data_bytes > HSSPI_MAX_DATA_SIZE) {
+			printf("max rx bytes exceeded\n");
+			return -EMSGSIZE;
+		}
+	}
+
+	if (dout) {
+		/* check tx size */
+		if (priv->prepend_bytes + data_bytes > HSSPI_MAX_DATA_SIZE) {
+			printf("max tx bytes exceeded\n");
+			return -EMSGSIZE;
+		}
+
+		/* copy tx data */
+		memcpy_toio(priv->regs + HSSPI_FIFO_BASE + HSSPI_FIFO_OP_SIZE + priv->prepend_bytes,
+			    dout, data_bytes);
+		priv->prepend_bytes += data_bytes;
+	}
+
+	if (flags & SPI_XFER_END) {
+		bcm63xx_hsspi_activate_cs(priv, plat);
+		if (dout && !din) {
+			/* all half-duplex write. merge to single write */
+			data_bytes = priv->prepend_bytes;
+			opcode = HSSPI_FIFO_OP_CODE_W;
+			priv->prepend_bytes = 0;
+		} else if (!dout && din) {
+			/* half-duplex read with prepend write */
+			opcode = HSSPI_FIFO_OP_CODE_R;
+		} else {
+			/* full duplex read/write */
+			opcode = HSSPI_FIFO_OP_READ_WRITE;
+			priv->prepend_bytes -= data_bytes;
+		}
+
+		/* profile mode */
+		val = SPI_PFL_MODE_FILL_MASK;
+		if (plat->mode & SPI_3WIRE)
+			val |= SPI_PFL_MODE_3WIRE_MASK;
+				
+		/* dual mode */
+		if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
+		    (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL)) {
+			opcode |= HSSPI_FIFO_OP_MBIT_MASK;
+			if (plat->mode == SPI_RX_DUAL)
+				val |= SPI_PFL_MODE_MDRDSZ_MASK;
+			if (plat->mode == SPI_TX_DUAL)
+				val |= SPI_PFL_MODE_MDWRSZ_MASK;		  
+		}
+		val |= (priv->prepend_bytes << SPI_PFL_MODE_PREPEND_CNT_SHIFT);
+		writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
+
+		/* set fifo operation */
+		val = opcode | (data_bytes & HSSPI_FIFO_OP_BYTES_MASK);
+		writew(cpu_to_be16(val),
+		       priv->regs + HSSPI_FIFO_OP_REG);
+
+		/* issue the transfer */
+		val = SPI_CMD_OP_START;
+		val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
+		       SPI_CMD_PFL_MASK;
+		val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) &
+		       SPI_CMD_SLAVE_MASK;
+		writel(val, priv->regs + SPI_CMD_REG);
+
+		/* wait for completion */
+		ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
+					SPI_STAT_SRCBUSY_MASK, false,
+					1000, false);
+		if (ret) {
+			bcm63xx_hsspi_deactivate_cs(priv);		  
+			printf("spi polling timeout\n");
+			return ret;
+		}
+
+		/* copy rx data */
+		if (din)
+			memcpy_fromio(din, priv->regs + HSSPI_FIFO_BASE,
+				data_bytes);
+		bcm63xx_hsspi_deactivate_cs(priv);
+	}
+
+	return 0;
+}
+
+
 /*
  * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
  * because they are controlled by HW.
@@ -222,6 +353,10 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
 	const uint8_t *tx = dout;
 	uint8_t *rx = din;
 
+	if (!priv->use_cswar)
+		return bcm63xx_hsspi_prepend_xfer(dev, bitlen,
+		    dout, din, flags);
+
 	if (flags & SPI_XFER_BEGIN)
 		bcm63xx_hsspi_activate_cs(priv, plat);
 
@@ -247,7 +382,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
 	      SPI_PFL_MODE_MDWRSZ_MASK;
 	if (plat->mode & SPI_3WIRE)
 		val |= SPI_PFL_MODE_3WIRE_MASK;
-	writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
+	writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
 
 	/* transfer loop */
 	while (data_bytes > 0) {
@@ -262,7 +397,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
 		}
 
 		/* set fifo operation */
-		writew_be(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK),
+		writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),
 			  priv->regs + HSSPI_FIFO_OP_REG);
 
 		/* issue the transfer */
@@ -271,10 +406,10 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
 		       SPI_CMD_PFL_MASK;
 		val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &
 		       SPI_CMD_SLAVE_MASK;
-		writel_be(val, priv->regs + SPI_CMD_REG);
+		writel(val, priv->regs + SPI_CMD_REG);
 
 		/* wait for completion */
-		ret = wait_for_bit_be32(priv->regs + SPI_STAT_REG,
+		ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
 					SPI_STAT_SRCBUSY_MASK, false,
 					1000, false);
 		if (ret) {
@@ -314,6 +449,7 @@ static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
 {
 	struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
 	struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+	struct spi_slave *slave = dev_get_parent_priv(dev);
 
 	/* check cs */
 	if (plat->cs >= priv->num_cs) {
@@ -327,6 +463,15 @@ static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
 	else
 		priv->cs_pols &= ~BIT(plat->cs);
 
+	/* 
+	 * set the max read/write size to make sure each xfer are within the
+	 * prepend limit
+	 */
+	if (priv->use_cswar == 0) {	
+		slave->max_read_size = HSSPI_MAX_DATA_SIZE;
+		slave->max_write_size = HSSPI_MAX_DATA_SIZE;
+	}
+
 	return 0;
 }
 
@@ -336,12 +481,30 @@ static int bcm63xx_hsspi_probe(struct udevice *dev)
 	struct reset_ctl rst_ctl;
 	struct clk clk;
 	int ret;
-
+	u32 freq = 0;
+	
 	priv->regs = dev_remap_addr(dev);
 	if (!priv->regs)
 		return -EINVAL;
 
 	priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
+	/* 
+	 * on the board that does not brought dummy cs1 and not
+	 * pinmux to cs function, spi bus does not work at fast
+	 * clock. max-uboot-freq property limits the bus speed to
+	 * workaroud this problem.
+	 */
+	if (dev_read_u32(dev, "max-uboot-freq", &freq) == 0) {
+		priv->max_speed = freq;
+		if (priv->max_speed > SPI_MAX_SYNC_CLOCK)
+			priv->max_speed = SPI_MAX_SYNC_CLOCK;
+		printf("limit spi bus speed to %dHz\n", priv->max_speed);
+	}
+	else
+		priv->max_speed = 0;
+
+	/* check if dummy cs workaround is enforced */
+	priv->use_cswar = dev_read_u32_default(dev, "use_cs_workaround", 0);
 
 	/* enable clock */
 	ret = clk_get_by_name(dev, "hsspi", &clk);
@@ -349,48 +512,47 @@ static int bcm63xx_hsspi_probe(struct udevice *dev)
 		return ret;
 
 	ret = clk_enable(&clk);
-	if (ret < 0)
+	if (ret < 0 && ret != -ENOSYS)
 		return ret;
 
 	ret = clk_free(&clk);
-	if (ret < 0)
+	if (ret < 0 && ret != -ENOSYS)
 		return ret;
 
 	/* get clock rate */
 	ret = clk_get_by_name(dev, "pll", &clk);
-	if (ret < 0)
+	if (ret < 0 && ret != -ENOSYS)
 		return ret;
 
 	priv->clk_rate = clk_get_rate(&clk);
 
 	ret = clk_free(&clk);
-	if (ret < 0)
+	if (ret < 0 && ret != -ENOSYS)
 		return ret;
 
 	/* perform reset */
 	ret = reset_get_by_index(dev, 0, &rst_ctl);
-	if (ret < 0)
-		return ret;
-
-	ret = reset_deassert(&rst_ctl);
-	if (ret < 0)
-		return ret;
+	if (ret >= 0) {
+		ret = reset_deassert(&rst_ctl);
+		if (ret < 0)
+			return ret;
+	}
 
 	ret = reset_free(&rst_ctl);
 	if (ret < 0)
 		return ret;
 
 	/* initialize hardware */
-	writel_be(0, priv->regs + SPI_IR_MASK_REG);
+	writel(0, priv->regs + SPI_IR_MASK_REG);
 
 	/* clear pending interrupts */
-	writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
+	writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
 
 	/* enable clk gate */
-	setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
+	setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
 
 	/* read default cs polarities */
-	priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) &
+	priv->cs_pols = readl(priv->regs + SPI_CTL_REG) &
 			SPI_CTL_CS_POL_MASK;
 
 	return 0;
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index b86eee75bc..6e2ecd22cc 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -201,7 +201,11 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
 	unsigned int pos = 0;
 	const u8 *tx_buf = NULL;
 	u8 *rx_buf = NULL;
+#if CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE)
+	u8 op_buf[32];
+#else	
 	u8 *op_buf;
+#endif
 	int op_len;
 	u32 flag;
 	int ret;
@@ -338,8 +342,18 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
 	}
 
 	op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+#if CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE)
+	/* When simple malloc is enabled for SPL, free is a NOP. Use local 
+	 * stack to avoid running out heap memory. All spi mem operations
+	 * has small addr and dummy bytes. 32 bytes buf is good enough
+	 */
+	if (op_len > 32 )
+ 		return -ENOMEM;
+	else
+		memset(op_buf, 0x0, 32);
+#else	
 	op_buf = calloc(1, op_len);
-
+#endif
 	op_buf[pos++] = op->cmd.opcode;
 
 	if (op->addr.nbytes) {
@@ -382,7 +396,9 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
 		debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]);
 	debug("[ret %d]\n", ret);
 
+#if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE)	
 	free(op_buf);
+#endif
 
 	if (ret < 0)
 		return ret;
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 5f4bc6edb6..2cf4c1726c 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -181,4 +181,11 @@ config MTK_TIMER
 	  Select this to enable support for the timer found on
 	  MediaTek devices.
 
+config BCM6XXX_TIMER
+	bool "Broadcom 6XXX SoC timer support"
+	depends on TIMER
+	help
+	  Select this to enable peripheral timer support for Broadcom
+	  6XXX SoC devices
+
 endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index fa35bea6c5..5499f11cb0 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_STI_TIMER)		+= sti-timer.o
 obj-$(CONFIG_STM32_TIMER)	+= stm32_timer.o
 obj-$(CONFIG_X86_TSC_TIMER)	+= tsc_timer.o
 obj-$(CONFIG_MTK_TIMER)		+= mtk_timer.o
+obj-$(CONFIG_BCM6XXX_TIMER)	+= bcm6xxx_timer.o
diff --git a/drivers/timer/bcm6xxx_timer.c b/drivers/timer/bcm6xxx_timer.c
new file mode 100644
index 0000000000..54f157321c
--- /dev/null
+++ b/drivers/timer/bcm6xxx_timer.c
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <timer.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+
+// periph timer registers
+#define TIMER_CTL 0
+#define TIMER_CNT 0x10
+
+#define BCM6XXX_TIMER_ENABLE		BIT(31)
+#define BCM6XXX_TIMER_CNT_MASK		0x3fffffff
+#define BCM6XXX_TIMER_CNT_HIGH_SHIFT	30
+
+struct bcm6xxx_timer_priv {
+	void __iomem *reg_base;
+  	u64 cnt_high;
+  	u32 cnt_low;
+};
+
+static int bcm6xxx_timer_get_count(struct udevice *dev, u64 *count)
+{
+	struct bcm6xxx_timer_priv *priv = dev_get_priv(dev);
+	u32 val = readl(priv->reg_base + TIMER_CNT) & BCM6XXX_TIMER_CNT_MASK;
+
+	/* hardware counter overflow */
+	if (val < priv->cnt_low)
+		priv->cnt_high++;
+	priv->cnt_low = val;
+	
+	*count = priv->cnt_high<<BCM6XXX_TIMER_CNT_HIGH_SHIFT | 
+			priv->cnt_low;
+
+	return 0;
+}
+
+static void bcm6xxx_timer_start(struct udevice *dev)
+{
+	struct bcm6xxx_timer_priv *priv = dev_get_priv(dev);
+
+	writel(BCM6XXX_TIMER_ENABLE | BCM6XXX_TIMER_CNT_MASK, priv->reg_base + TIMER_CTL);
+
+	return;
+}
+
+static int bcm6xxx_timer_probe(struct udevice *dev)
+{
+	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct bcm6xxx_timer_priv *priv = dev_get_priv(dev);
+	struct clk clk;
+	struct resource res;
+	int ret;
+
+	priv->reg_base = dev_remap_addr(dev);
+	printf("timer reg_base = %p\n", priv->reg_base);
+	if (priv->reg_base == NULL)
+		return -ENOENT;
+
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret)
+		return ret;
+
+	uc_priv->clock_rate = clk_get_rate(&clk);
+	if (!uc_priv->clock_rate)
+		return -EINVAL;
+
+	priv->cnt_high = 0;
+	priv->cnt_low = 0;
+	bcm6xxx_timer_start(dev);
+
+	return 0;
+}
+
+static const struct timer_ops bcm6xxx_timer_ops = {
+	.get_count = bcm6xxx_timer_get_count,
+};
+
+static const struct udevice_id bcm6xxx_timer_ids[] = {
+	{ .compatible = "brcm,bcm6xxx-timer" },
+	{ }
+};
+
+U_BOOT_DRIVER(bcm6xxx_timer) = {
+	.name = "bcm6xxx_timer",
+	.id = UCLASS_TIMER,
+	.of_match = bcm6xxx_timer_ids,
+	.priv_auto_alloc_size = sizeof(struct bcm6xxx_timer_priv),
+	.probe = bcm6xxx_timer_probe,
+	.ops = &bcm6xxx_timer_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index b1188bcbf5..2f46657da2 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -221,6 +221,13 @@ config USB_EHCI_FSL
 	select  CONFIG_EHCI_HCD_INIT_AFTER_RESET
 	---help---
 	  Enables support for the on-chip EHCI controller on FSL chips.
+
+config USB_EHCI_BCMBCA
+	bool  "Support for Broadcom BCA on-chip EHCI USB controller"
+	default n
+	depends on ARCH_BCMBCA
+	---help---
+	  Enables support for the on-chip EHCI controller on Broadcom BCA chips.
 endif # USB_EHCI_HCD
 
 config USB_OHCI_HCD
@@ -251,6 +258,13 @@ config USB_OHCI_DA8XX
 	help
 	  Enable support for the da850 USB controller.
 
+config USB_OHCI_BCMBCA
+	bool  "Support for Broadcom BCA on-chip OHCI USB controller"
+	default n
+	depends on ARCH_BCMBCA
+	---help---
+	  Enables support for the on-chip OHCI controller on Broadcom BCA chips.
+
 endif # USB_OHCI_HCD
 
 config USB_UHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 6aa574f6f7..8ab13108be 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o
 obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o
 obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
 obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
+obj-$(CONFIG_USB_OHCI_BCMBCA) += ohci-bcmbca.o
 
 # echi
 obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
@@ -41,6 +42,7 @@ obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
 obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
 obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
+obj-$(CONFIG_USB_EHCI_BCMBCA) += ehci-bcmbca.o
 
 # xhci
 obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
diff --git a/drivers/usb/host/ehci-bcmbca.c b/drivers/usb/host/ehci-bcmbca.c
new file mode 100644
index 0000000000..542cd41ad0
--- /dev/null
+++ b/drivers/usb/host/ehci-bcmbca.c
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <dm/ofnode.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include "ehci.h"
+#include <dm/device-internal.h>
+
+#if defined(CONFIG_BCMBCA_PMC)
+#include "pmc_drv.h"
+#endif
+
+#define MDIO_USB2   0
+
+/* USB Host contorl regs */
+typedef struct usb_ctrl{
+	uint32_t setup;
+#define USBH_IPP                (1<<5)
+#define USBH_IOC                (1<<4)
+#define USBH_STRAP_IPP_SEL      (1<<25)
+#define USB2_OC_DISABLE_PORT0   (1<<28)
+#define USB2_OC_DISABLE_PORT1   (1<<29)
+#define USB3_OC_DISABLE_PORT0   (1<<30)
+#define USB3_OC_DISABLE_PORT1   (1<<31)
+	uint32_t pll_ctl;
+	uint32_t fladj_value;
+	uint32_t bridge_ctl;
+#define USB_BRCTL_OHCI_MEM_REQ_DIS (1<<16)
+	uint32_t spare1;
+	uint32_t mdio;
+	uint32_t mdio2;
+	uint32_t test_port_control;
+	uint32_t usb_simctl;
+#define USBH_OHCI_MEM_REQ_DIS   (1<<1)
+	uint32_t usb_testctl;
+	uint32_t usb_testmon;
+	uint32_t utmi_ctl_1;
+	uint32_t utmi_ctl_2;
+	uint32_t usb_pm;
+#define XHC_SOFT_RESETB         (1<<22)
+#define USB_PWRDWN              (1<<31)
+	uint32_t usb_pm_status;
+	uint32_t spare3;
+	uint32_t pll_ldo_ctl;
+	uint32_t pll_ldo_pllbias;
+	uint32_t pll_afe_bg_cntl;
+	uint32_t afe_usbio_tst;
+	uint32_t pll_ndiv_frac;
+	uint32_t tp_diag;
+	uint32_t ahb_capture_fifo;
+	uint32_t spare4;
+	uint32_t usb30_ctl1;
+#define PHY3_PLL_SEQ_START      (1<<4)
+	uint32_t usb30_ctl2;
+	uint32_t usb30_ctl3;
+	uint32_t usb30_ctl4;
+	uint32_t usb30_pctl;
+	uint32_t usb30_ctl5;
+	uint32_t spare5;
+	uint32_t spare6;
+	uint32_t spare7;
+	uint32_t unsused1[3];
+	uint32_t usb_device_ctl1;
+	uint32_t usb_device_ctl2;
+	uint32_t unsused2[22];
+	uint32_t usb20_id;
+	uint32_t usb30_id;
+	uint32_t bdc_coreid;
+	uint32_t usb_revid;
+} usb_ctrl;
+
+struct bcmbca_usb_ctrl {
+	volatile struct usb_ctrl *regp;
+};
+
+struct bcmbca_ehci {
+	struct ehci_ctrl ctrl;
+};
+
+static void usb_mdio_write(volatile uint32_t *mdio, uint32_t reg, uint32_t val, int mode)
+{
+	uint32_t data;
+	data = (reg << 16) | val | mode;
+	*mdio = data;
+	data |= (1 << 25);
+	*mdio = data;
+	mdelay(1);
+	data &= ~(1 << 25);
+	*mdio = data;
+}
+
+static void usb2_eye_fix(volatile struct usb_ctrl *regp)
+{
+	/* Updating USB 2.0 PHY registers */
+	usb_mdio_write((void *)&regp->mdio, 0x1f, 0x80a0, MDIO_USB2);
+	usb_mdio_write((void *)&regp->mdio, 0x0a, 0xc6a0, MDIO_USB2);
+}
+
+#if defined (CONFIG_BCM63138)
+static void bcm63138B0_manual_usb_ldo_start(volatile struct usb_ctrl *regp)
+{
+	regp->pll_ctl &= ~(1 << 30); /*pll_resetb=0*/
+	regp->utmi_ctl_1 = 0; 
+	regp->pll_ldo_ctl = 4; /*ldo_ctl=core_rdy */
+	regp->pll_ctl |= ( 1 << 31); /*pll_iddq=1*/
+	mdelay(10);
+	regp->pll_ctl &= ~( 1 << 31); /*pll_iddq=0*/
+	regp->pll_ldo_ctl |= 1; /*ldo_ctl.AFE_LDO_PWRDWNB=1*/
+	regp->pll_ldo_ctl |= 2; /*ldo_ctl.AFE_BG_PWRDWNB=1*/
+	mdelay(1);
+	regp->utmi_ctl_1 = 0x00020002;/* utmi_resetb &ref_clk_sel=0; */ 
+	regp->pll_ctl |= ( 1 << 30); /*pll_resetb=1*/
+	mdelay(10);
+}    
+#endif
+
+static int ehci_usb_probe (struct udevice *dev)
+{
+	struct ehci_hccr *hccr;
+	struct ehci_hcor *hcor;
+	int ret;
+	struct resource res;
+	struct udevice *ctrl_dev;
+
+	uclass_get_device_by_driver(UCLASS_NOP, DM_GET_DRIVER(ctrl_bcmbca_drv), &ctrl_dev);
+
+	ret = dev_read_resource_byname (dev, "usb-ehci", &res);
+	if (ret)
+	{
+		dev_err(dev, "can't get usb-ehci register for usb (ret=%d)\n", ret);
+		return ret;
+	}
+
+	hccr = devm_ioremap (dev, res.start, resource_size(&res));
+	hcor = (struct ehci_hcor *)((uint64_t)hccr +
+			HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
+	debug("dev %p usb %d hccr %p hcor %p\n", dev, dev->seq, hccr, hcor);
+
+	ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+
+	return 0;
+}
+
+static int ehci_usb_remove(struct udevice *dev)
+{
+	int ret;
+	struct udevice *next_devp = dev;
+	struct udevice *ctrl_dev;
+
+	debug ("remove bcmbca ehci dev %p seq %d\n", dev, dev->seq);
+	ret = ehci_deregister(dev);
+
+	if (ret)
+	{
+		printf("failed to deregister bcmbca ehci seq %d\n", dev->seq);
+		return ret;
+	}
+	ret = uclass_find_next_device (&next_devp);
+	if (!ret && !next_devp) {
+		uclass_get_device_by_driver(UCLASS_NOP, DM_GET_DRIVER(ctrl_bcmbca_drv), &ctrl_dev);
+		if (ctrl_dev)
+			device_remove(ctrl_dev, DM_REMOVE_NORMAL);
+	}
+
+	return 0;
+}
+
+
+static const struct udevice_id ehci_usb_ids[] = {
+	{ .compatible = "brcm,bcmbca-ehci" },
+	{ }
+};
+
+U_BOOT_DRIVER(ehci_bcmbca) = {
+	.name	= "ehci-bcmbca",
+	.id	= UCLASS_USB,
+	.of_match = ehci_usb_ids,
+	.probe = ehci_usb_probe,
+	.remove = ehci_usb_remove,
+	.ops	= &ehci_usb_ops,
+	.priv_auto_alloc_size = sizeof(struct bcmbca_ehci),
+	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+/* definition of the dummy driver for usb ctrl */
+static int bcmbca_usb_ctrl_probe (struct udevice *dev)
+{
+	int ret;
+	uint32_t val;
+	struct resource res;
+	volatile struct usb_ctrl *regp;
+	struct bcmbca_usb_ctrl *priv = dev_get_priv (dev);
+
+	debug("bcmbca_usb_ctrl_probe called....\n");
+
+	//usb-ctrl drive probe function is expected to be called once
+
+#if defined(CONFIG_BCMBCA_PMC)
+	// Power On USB, EHCI with index 0 has to be the first USB device 
+#if defined(CONFIG_BCM47622) || defined(CONFIG_BCM6756) 
+	if (PowerOnDevice(PMB_ADDR_USB31_20))  // replace with pmc_usb call later on
+	{
+		printf("Failed to Power Up USB Host\n");
+		return -1;
+	}
+#elif defined(CONFIG_BCM6846) || defined(CONFIG_BCM6878)
+	if (PowerOnDevice(PMB_ADDR_USB20_2X))  // replace with pmc_usb call later on
+	{
+		printf("Failed to Power Up USB Host\n");
+		return -1;
+	}
+#else
+	if (PowerOnDevice(PMB_ADDR_USB30_2X))  // replace with pmc_usb call later on
+	{
+		printf("Failed to Power Up USB Host\n");
+		return -1;
+	}
+#endif
+	mdelay(1);
+#endif
+	priv->regp = NULL;
+	ret = dev_read_resource_byname (dev, "usb-ctrl", &res);
+	if (ret)
+	{
+		dev_err(dev, "can't get usb-ctrl register (ret=%d)\n", ret);
+		return ret;
+	}
+	regp = devm_ioremap (dev, res.start, resource_size(&res));
+	priv->regp = regp;
+	debug("usb-ctrl reg %p\n", priv->regp);
+
+	/* adjust over current & port power polarity */
+	regp->setup |= (USBH_IOC);
+	if (dev_read_bool(dev, "pwrflt-bias-pull-up"))
+		regp->setup &= ~(USBH_IOC);
+
+	/*overide strap for IPP*/
+	val = regp->setup;
+	val &= ~(USBH_STRAP_IPP_SEL);
+	val |= (USBH_IPP);
+	regp->setup = val;
+
+	if (dev_read_bool(dev, "pwron-bias-pull-up"))
+		regp->setup &= ~(USBH_IPP);
+
+#if defined (CONFIG_BCM63138)
+	mdelay(300);
+	bcm63138B0_manual_usb_ldo_start(regp);
+#endif
+	/*enable USB PHYs*/
+	mdelay(1);
+	regp->usb_pm &= ~(USB_PWRDWN);
+	mdelay(300);
+	regp->usb_pm &= ~XHC_SOFT_RESETB;
+	/*adjust the default AFE settings for better eye diagrams */
+	usb2_eye_fix(regp);
+
+	/*initialize EHCI & OHCI settings*/
+	/* no swap for data & desciptors */    
+	regp->bridge_ctl &= ~(0xf); /*clear lower 4 bits */
+
+	/* reset host controllers for possible fake overcurrent indications */ 
+	val = regp->usb_pm;
+	regp->usb_pm = 0;
+	regp->usb_pm = val;
+	mdelay(1);
+
+	return 0;
+}
+
+static int bcmbca_usb_ctrl_remove(struct udevice *dev)
+{
+	debug("bcmbca_usb_ctrl_remove called\n");
+#if defined(CONFIG_BCMBCA_PMC)
+#if defined(CONFIG_BCM47622) || defined(CONFIG_BCM6756) 
+	if (PowerOffDevice(PMB_ADDR_USB31_20, 0))  // replace with pmc_usb call later on
+	{
+		printf("Failed to Power Down USB Host\n");
+		return -1;
+	}
+#elif defined(CONFIG_BCM6846) || defined(CONFIG_BCM6878)
+	if (PowerOffDevice(PMB_ADDR_USB20_2X, 0))  // replace with pmc_usb call later on
+	{
+		printf("Failed to Power Down USB Host\n");
+		return -1;
+	}
+#else
+	if (PowerOffDevice(PMB_ADDR_USB30_2X, 0))  // replace with pmc_usb call later on
+	{
+		printf("Failed to Power Down USB Host\n");
+		return -1;
+	}
+#endif
+#endif
+
+	return 0;
+}
+
+static const struct udevice_id bcmbca_usb_ctrl_ids[] = {
+	{ .compatible = "brcm,bcmbca-usb-ctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(ctrl_bcmbca_drv) = {
+	.name = "bcmbca-usbctrl",
+	.id = UCLASS_NOP,
+	.of_match = bcmbca_usb_ctrl_ids,
+	.probe = bcmbca_usb_ctrl_probe,
+	.remove = bcmbca_usb_ctrl_remove,
+	.priv_auto_alloc_size = sizeof(struct bcmbca_usb_ctrl),
+};
diff --git a/drivers/usb/host/ohci-bcmbca.c b/drivers/usb/host/ohci-bcmbca.c
new file mode 100644
index 0000000000..5dd755dadf
--- /dev/null
+++ b/drivers/usb/host/ohci-bcmbca.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <dm/ofnode.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+
+#include "ohci.h"
+
+struct bcmbca_ohci {
+	ohci_t ohci;
+};
+
+static int ohci_usb_probe (struct udevice *dev)
+{
+	struct ohci_regs *regs;
+	int ret;
+	struct resource res;
+
+	ret = dev_read_resource_byname (dev, "usb-ohci", &res);
+	if (ret)
+	{
+		dev_err(dev, "can't get usb-ohci register for usb (ret=%d)\n", ret);
+		return ret;
+	}
+
+	regs = devm_ioremap (dev, res.start, resource_size(&res));
+	debug("bcmbca ohci device regs %p\n", regs);
+	
+	ohci_register(dev, regs);
+
+	return 0;
+}
+
+static int ohci_usb_remove(struct udevice *dev)
+{
+	int ret;
+	struct udevice *next_devp = dev;
+	struct udevice *ctrl_dev;
+
+	debug("remove bcmbca-ohci %p seq %d\n", dev, dev->seq);
+
+	ret = ohci_deregister(dev);
+
+	if (ret)
+	{
+		printf("failed to deregister bcmbca ohci seq %d\n", dev->seq);
+		return ret;
+	}
+
+	ret = uclass_find_next_device (&next_devp);
+	if (!ret && !next_devp)
+	{
+		uclass_get_device_by_driver(UCLASS_NOP, DM_GET_DRIVER(ctrl_bcmbca_drv), &ctrl_dev);
+		if (ctrl_dev)
+			device_remove(ctrl_dev, DM_REMOVE_NORMAL);
+	}
+	return ret;
+}
+
+
+static const struct udevice_id ohci_usb_ids[] = {
+	{ .compatible = "brcm,bcmbca-ohci" },
+	{ }
+};
+
+U_BOOT_DRIVER(ohci_bcmbca) = {
+	.name	= "ohci-bcmbca",
+	.id	= UCLASS_USB,
+	.of_match = ohci_usb_ids,
+	.probe = ohci_usb_probe,
+	.remove = ohci_usb_remove,
+	.ops	= &ohci_usb_ops,
+	.priv_auto_alloc_size = sizeof(struct bcmbca_ohci),
+	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index ee0ddffe73..1fc303c209 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -86,7 +86,7 @@ config WDT_AT91
 
 config WDT_BCM6345
 	bool "BCM6345 watchdog timer support"
-	depends on WDT && (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158)
+	depends on WDT && (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158 || ARCH_BCMBCA)
 	help
 	  Select this to enable watchdog timer for BCM6345 SoCs.
 	  The watchdog timer is stopped when initialized.
diff --git a/env/Kconfig b/env/Kconfig
index b9439171fd..1a4ee18422 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -7,7 +7,7 @@ config ENV_IS_NOWHERE
 		     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
 		     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
 		     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
-		     !ENV_IS_IN_UBI
+		     !ENV_IS_IN_UBI && !ENV_IS_IN_BOOT_MAGIC
 	help
 	  Define this if you don't want to or can't have an environment stored
 	  on a storage medium. In this case the environment will still exist
@@ -370,6 +370,12 @@ config ENV_SPI_MODE
 	  Value of the SPI work mode for environment.
 	  See include/spi.h for value.
 
+config ENV_IS_IN_BOOT_MAGIC
+	bool "Environment in the boot device preceded by magic number and length"
+	help
+	  Boot device will be any MTD device for now
+
+
 config ENV_IS_IN_UBI
 	bool "Environment in a UBI volume"
 	depends on !CHAIN_OF_TRUST
diff --git a/env/Makefile b/env/Makefile
index 90144d6caf..02479edca8 100644
--- a/env/Makefile
+++ b/env/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ENV_IS_IN_ONENAND) += onenand.o
 obj-$(CONFIG_ENV_IS_IN_SATA) += sata.o
 obj-$(CONFIG_ENV_IS_IN_REMOTE) += remote.o
 obj-$(CONFIG_ENV_IS_IN_UBI) += ubi.o
+obj-$(CONFIG_ENV_IS_IN_BOOT_MAGIC) += boot_magic.o
 else
 obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += attr.o
 obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += flags.o
diff --git a/env/boot_magic.c b/env/boot_magic.c
new file mode 100644
index 0000000000..06f8e4413d
--- /dev/null
+++ b/env/boot_magic.c
@@ -0,0 +1,428 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2019 Broadcom Corporation
+ * Joel Peshkin, Broadcom Corporation, joel.peshkin@broadcom.com
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <hexdump.h>
+#include <linux/stddef.h>
+#include <nand.h>
+#include <mmc.h>
+#include <nand.h>
+#include <search.h>
+#include <errno.h>
+#include <bca_sdk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak uint32_t env_boot_magic_search_size(void)
+{
+	return 2*1024*1024;
+}
+
+__weak int env_override_import(void *ep)
+{
+	return 0;
+}
+
+#ifdef CONFIG_SPI_FLASH
+static int env_dev_read_spinor( int addr, size_t * len, char * buffer )
+{
+	int ret= -1;
+	struct mtd_info *mtd;
+	size_t retlen;	
+
+	mtd = get_mtd_device_nm(LOADER_PART);
+	if (IS_ERR_OR_NULL(mtd)){
+		debug("%s:MTD device %s not found, ret %ld\n",__func__, LOADER_PART,
+		   PTR_ERR(mtd));
+		return ret;
+	}
+	ret = mtd_read(mtd,addr,*len,&retlen,buffer);
+	put_mtd_device(mtd);
+	return ret;
+}
+static int env_dev_write_spinor( int addr, size_t * len, char * buffer )
+{
+	int ret= -1;
+	struct mtd_info *mtd;
+	struct erase_info ei;
+	size_t retlen;	
+	u_char * tempbuff = NULL;
+	size_t erase_bytes;
+	u32 start_offset;
+	u32 start_sector;
+	u32 end_sector;
+	
+	mtd = get_mtd_device_nm(LOADER_PART);
+	if (IS_ERR_OR_NULL(mtd)){
+		debug("%s:MTD device %s not found, ret %ld\n",__func__, LOADER_PART,
+	   		PTR_ERR(mtd));
+		return ret;
+	}
+
+	start_sector = addr/mtd->erasesize;
+	end_sector = ( addr + *len + mtd->erasesize - 1)/mtd->erasesize;
+	start_offset = start_sector * mtd->erasesize;
+	erase_bytes = (end_sector - start_sector)*mtd->erasesize;
+	tempbuff = malloc(erase_bytes);
+	if (!tempbuff){
+		debug("%s malloc %d failed\n",__func__, erase_bytes);
+		goto done;
+ 	}
+	
+	ret = mtd_read(mtd,start_offset,erase_bytes,&retlen,tempbuff);
+	if (ret){
+		debug("%s:read MTD device %s fail, ret %d\n",__func__, LOADER_PART,
+	   		ret);
+		goto done;
+	}
+
+	memcpy(tempbuff + addr%mtd->erasesize, buffer, *len);
+	memset(&ei, 0, sizeof(ei));
+	ei.mtd = mtd;
+	ei.addr = start_offset;
+	ei.len = erase_bytes;
+	ret = mtd_erase(mtd, &ei);
+	if (ret){
+		debug("%s:erase MTD device %s fail, ret %d\n",__func__, LOADER_PART,
+	   		ret);
+		goto done;
+	}
+
+	ret = mtd_write(mtd, start_offset, erase_bytes, &retlen, tempbuff);
+	if (ret){
+		debug("%s:write MTD device %s fail, ret %d\n",__func__, LOADER_PART,
+	   		ret);
+	}
+
+done:	
+	free(tempbuff);
+	put_mtd_device(mtd);
+	return ret;
+	
+}
+#endif
+#ifdef CONFIG_NAND	
+static int env_dev_read_nand( int addr, size_t * len, char * buffer )
+{
+	int ret= -1;
+	struct mtd_info *mtd;
+	mtd = get_nand_dev_by_index(0);
+	if (!mtd)
+		return ret;
+	ret = nand_read(mtd, addr, len, (void *)buffer);
+	return ret;
+}
+static int env_dev_write_nand( int addr, size_t * len, char * buffer )
+{
+	int blocknum, off;
+	size_t blocksize;
+	int ret = -1;
+
+	struct mtd_info *mtd;
+	char * block = NULL;
+	mtd = get_nand_dev_by_index(0);
+	if (!mtd)
+		return ret;
+	
+	block = malloc(mtd->erasesize);
+	if (!block)
+		return ret;
+
+	blocksize = mtd->erasesize;
+	blocknum = addr / mtd->erasesize;
+	off = addr % mtd->erasesize;
+	ret = nand_read(mtd, (off_t) (blocknum * mtd->erasesize),
+		      &blocksize, (void *)block);
+	if (ret < 0) {
+		debug("read error %d on block %d\n", ret, blocknum);
+	}
+	memcpy(block + off, buffer, *len);
+	nand_erase(mtd, blocknum * blocksize, blocksize);
+	ret = nand_write(mtd, blocknum * blocksize, &blocksize,
+			       (void *)block);
+	if (ret < 0) {
+		debug("write error %d on block %d\n", ret, blocknum);
+	}
+	free(block);
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_MMC
+
+#define ENV_DEV_MMC_READ 		0
+#define ENV_DEV_MMC_WRITE		1
+#define ENV_DEV_MMC_DEV_NUM 		0
+#define ENV_DEV_MMC_BOOT_HWPART 	1
+#define ENV_DEV_MMC_USERDATA_PART 	0
+
+static int env_dev_read_write_mmc( int addr, size_t * len, char * buffer, int mode)
+{
+	uint64_t blocksize, start_blocknum, start_offset, num_blocks;
+	int ret = -1;
+	char * block_data_ptr = NULL;
+	struct mmc *mmc = NULL;
+	struct blk_desc * block_dev = NULL;
+
+	/* Initialize MMC */
+	mmc = find_mmc_device(ENV_DEV_MMC_DEV_NUM);
+	if (!mmc)
+		return ret;
+	mmc_init(mmc);
+
+	/* Point to BOOT partition */
+	blk_select_hwpart_devnum(IF_TYPE_MMC, ENV_DEV_MMC_DEV_NUM, ENV_DEV_MMC_BOOT_HWPART);
+
+	/* Get block device */
+	block_dev = mmc_get_blk_desc(mmc);
+	if (!block_dev)
+		goto mmc_err;
+	
+	/* Calculate block numbers and offsets */
+	blocksize = mmc->read_bl_len;
+	start_blocknum = addr/blocksize; 
+	start_offset = addr %  blocksize;
+	num_blocks = (start_offset+*len)/blocksize + ((start_offset+*len)%blocksize?1:0);
+	block_data_ptr = memalign(ARCH_DMA_MINALIGN, num_blocks*blocksize);
+	if( !block_data_ptr ) {
+		printf("%s: ERROR! Cannot allocate memory for blockdata\n", __FUNCTION__);
+		goto mmc_err;
+	}
+
+	ret = blk_dread(block_dev, start_blocknum, num_blocks, (void *)block_data_ptr);
+	if (ret < 0) {
+		printf("%s: read error %d on block %llu, num_blocks %llu\n", __FUNCTION__, ret, start_blocknum, num_blocks);
+		goto mmc_err;
+	}
+		
+	if( mode == ENV_DEV_MMC_WRITE ) {
+		memcpy(block_data_ptr + start_offset, buffer, *len);
+		ret = blk_dwrite(block_dev, start_blocknum, num_blocks, (void *)block_data_ptr);
+
+		if (ret < 0) {
+			printf("%s: write error %d on block %llu, num_blocks %llu\n", __FUNCTION__, ret, start_blocknum, num_blocks);
+			goto mmc_err;
+		}
+	} else	{
+		memcpy(buffer, block_data_ptr + start_offset, *len);
+	}	
+
+	ret = 0;
+mmc_err:
+	if( block_data_ptr )
+		free(block_data_ptr);
+
+	/* Point to USERDATA partition */
+	blk_select_hwpart_devnum(IF_TYPE_MMC, ENV_DEV_MMC_DEV_NUM, ENV_DEV_MMC_USERDATA_PART);
+	return ret;
+}
+#endif	
+
+static int get_env_flashtype( char ** flashtype )
+{
+	*flashtype = get_loader_media();
+	return 0;
+}
+
+static int env_dev_read( int addr, size_t * len, char * buffer )
+{
+	char * pflashtype_str = NULL;
+	if( get_env_flashtype(&pflashtype_str) == 0 ) {
+		if( pflashtype_str != NULL ) {
+#ifdef CONFIG_NAND	
+			if( strcasecmp(pflashtype_str,FLASH_DEV_STR_NAND) == 0 )  {
+				return (env_dev_read_nand(addr, len, buffer));
+			}
+#endif
+		
+#ifdef CONFIG_MMC		
+			if( strcasecmp(pflashtype_str,FLASH_DEV_STR_EMMC) == 0 ) {
+				return (env_dev_read_write_mmc(addr, len, buffer, ENV_DEV_MMC_READ));
+			}
+#endif		
+		
+#ifdef CONFIG_SPI_FLASH		
+			if( strcasecmp(pflashtype_str,FLASH_DEV_STR_SPINOR) == 0 ) {
+				return (env_dev_read_spinor(addr, len, buffer));
+			}
+#endif		
+
+			printf("%s: Error: Unsupported env storage media %s!\n", __FUNCTION__, pflashtype_str);
+		} else {
+			printf("%s: Error: Environment storage media invalid!\n", __FUNCTION__);
+		}
+	} else {
+		printf("%s: Error: Cannot find environment storage media!\n", __FUNCTION__);
+	}
+	return -1;
+}
+
+static int env_dev_write( int addr, size_t * len, char * buffer )
+{
+	char * pflashtype_str = NULL;
+	if( get_env_flashtype(&pflashtype_str) == 0 )
+	{
+		if( pflashtype_str != NULL ) {
+#ifdef CONFIG_NAND	
+			if( strcasecmp(pflashtype_str,FLASH_DEV_STR_NAND) == 0 ) {
+				return (env_dev_write_nand(addr, len, buffer));
+			}
+#endif
+			
+#ifdef CONFIG_MMC		
+			if( strcasecmp(pflashtype_str,FLASH_DEV_STR_EMMC) == 0 ) {
+				return (env_dev_read_write_mmc(addr, len, buffer, ENV_DEV_MMC_WRITE));
+			}
+#endif		
+
+#ifdef CONFIG_SPI_FLASH		
+			if( strcasecmp(pflashtype_str,FLASH_DEV_STR_SPINOR) == 0 ) {
+				return (env_dev_write_spinor(addr, len, buffer));
+			}
+#endif		
+		}
+	}
+	printf("%s: Error: Cannot find environment storage media!\n", __FUNCTION__);
+	return -1;
+}
+
+static int env_boot_magic_load(void)
+{
+
+	uint32_t crc, new;
+	int ret;
+	loff_t off, copies[10];
+	int copies_found = 0;
+	int found_size;
+	size_t rdlen;
+	env_t *ep;
+	uint32_t magichdr[3];
+	char *ebuff = NULL;
+
+	printf("ENV_BOOT_MAGIC_LOAD\n");
+
+	for (off = 0; off < (loff_t)env_boot_magic_search_size(); off += 4096) {
+		rdlen = 12;
+		env_dev_read( off, &rdlen, (void *)magichdr);
+		if (magichdr[0] != BOOT_MAGIC_MAGIC) {
+			continue;
+		}
+		printf("found magic at %lx\n", (long)off);
+		rdlen = magichdr[1] + 12;
+		if (ebuff == NULL) {
+			ebuff = malloc(max((int)rdlen, CONFIG_ENV_SIZE + 12));
+		}
+		env_dev_read( off, &rdlen, (void *)ebuff);
+		ep = (env_t *) & ebuff[8];
+		memcpy(&crc, &ep->crc, sizeof(crc));
+
+		new = crc32(0, ep->data, rdlen - 16);
+		if (new != crc) {
+			debug("CRC mismatch len = %d\n", (int)rdlen - 16);
+			debug("computed %x \n", new);
+			debug("expected %x \n", crc);
+		} else {
+			debug("good crc\n");
+			gd->env_valid = ENV_VALID;
+			/* FIXME -- may need to grow instead of shrink */
+			debug("resize from %ld to %d\n", rdlen - 12,
+			      CONFIG_ENV_SIZE);
+			new = crc32(0, ep->data, CONFIG_ENV_SIZE - 4);
+			memcpy(&ep->crc, &new, sizeof(new));
+			copies[copies_found++] = off;
+			found_size = rdlen - 12;
+			if (!env_override_import((void *)ep))
+			{
+				ret = env_import((void *)ep, 1);
+			}
+		}
+		free(ebuff);
+		ebuff = NULL;
+		if (NULL != env_get("env_boot_magic")) {
+			break;
+		}
+	}
+
+	if (copies_found > 0) {
+		if (NULL == env_get("env_boot_magic")) {
+			char found[256];
+			int i;
+			sprintf(found, "%d@", found_size);
+			for (i = 0; i < copies_found; i++) {
+				sprintf(found + strlen(found), "0x%llx,",
+					copies[i]);
+			}
+			found[strlen(found) - 1] = '\0';
+			env_set("env_boot_magic", found);
+		}
+		return (ret);
+	} else {
+		set_default_env("import not done", 0);
+		return (-1);
+	}
+
+}
+
+static int env_boot_magic_save(void)
+{
+	env_t *ep;
+	char *envbuf = NULL;
+	uint32_t *envintp;
+	char *c;
+	int ret = -2;
+	int elen;
+	size_t wr_len;
+	char *config;
+	uint32_t new;
+	int i;
+	char *found = NULL;
+
+	config = env_get("env_boot_magic");
+	if (NULL == config)
+		return (-1);
+	elen = simple_strtoul(config, NULL, 0);
+	found = malloc(strlen(config) + 1);
+	if (!found)
+		goto err;
+	strcpy(found, config);
+	envbuf = malloc(max(elen + 12, CONFIG_ENV_SIZE + 12));
+	ep = (env_t *) (envbuf + 8);
+	envintp = (uint32_t *) envbuf;
+	ret = env_export(ep);
+	for (i = CONFIG_ENV_SIZE; i < elen; i++) {
+		envbuf[12 + i] = 0xff;
+	}
+	new = crc32(0, ep->data, elen - 4);
+	memcpy(&ep->crc, &new, sizeof(new));
+	envintp[0] = BOOT_MAGIC_MAGIC;
+	envintp[1] = elen;
+	strtok(found, "@");
+	while ((c = strtok(NULL, ","))) {
+		i = simple_strtoul(c, NULL, 0);
+		printf("save to %x\n", i);
+		wr_len = elen+12;
+                ret = env_dev_write( i, &wr_len, envbuf );
+	}
+
+err:	free(envbuf);
+	free(found);
+	return ret;
+
+}
+
+U_BOOT_ENV_LOCATION(boot_magic) = {
+	.location = ENVL_BOOT_MAGIC,
+	.load = env_boot_magic_load,
+	.save = env_save_ptr(env_boot_magic_save), 
+	ENV_NAME("BOOT_MAGIC")
+};
diff --git a/env/env.c b/env/env.c
index 4b417b90a2..eda03081e9 100644
--- a/env/env.c
+++ b/env/env.c
@@ -77,6 +77,9 @@ static enum env_location env_locations[] = {
 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 	ENVL_SPI_FLASH,
 #endif
+#ifdef CONFIG_ENV_IS_IN_BOOT_MAGIC
+	ENVL_BOOT_MAGIC,
+#endif
 #ifdef CONFIG_ENV_IS_IN_UBI
 	ENVL_UBI,
 #endif
diff --git a/include/_exports.h b/include/_exports.h
index c15050e30b..e510760260 100644
--- a/include/_exports.h
+++ b/include/_exports.h
@@ -29,10 +29,16 @@
 	EXPORT_FUNC(udelay, void, udelay, unsigned long)
 	EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long)
 	EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list)
+#if !defined(CONFIG_SPL_STANDALONE)
 	EXPORT_FUNC(do_reset, int, do_reset, cmd_tbl_t *,
 		    int , int , char * const [])
 	EXPORT_FUNC(env_get, char  *, env_get, const char*)
 	EXPORT_FUNC(env_set, int, env_set, const char *, const char *)
+#else
+	EXPORT_FUNC(dummy, void, do_reset, void)
+	EXPORT_FUNC(dummy, void, env_get, void)
+	EXPORT_FUNC(dummy, void, env_set, void)
+#endif
 	EXPORT_FUNC(simple_strtoul, unsigned long, simple_strtoul,
 		    const char *, char **, unsigned int)
 	EXPORT_FUNC(strict_strtoul, int, strict_strtoul,
diff --git a/include/bcm_bca_leds.h b/include/bcm_bca_leds.h
new file mode 100644
index 0000000000..f0887a5153
--- /dev/null
+++ b/include/bcm_bca_leds.h
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+
+*/
+
+#ifndef __BCM_BCA_LEDCTRL_H
+#define __BCM_BCA_LEDCTRL_H
+
+#if defined(CONFIG_BCM_BCA_LED)
+
+#include <dm.h>
+#include <dm/ofnode.h>
+
+typedef struct
+{
+    uint32_t port_id;
+    uint32_t skip_in_aggregate;
+    uint32_t link[4];
+    uint32_t activity[4];
+}bca_leds_info_t;
+
+struct udevice * bca_led_request_sw_led(ofnode dn, const char *consumer_led_name);
+void bca_led_request_network_leds(ofnode dn, bca_leds_info_t *leds_info);
+#endif
+#endif
diff --git a/include/cli.h b/include/cli.h
index 39b913743b..9d6e52e4d7 100644
--- a/include/cli.h
+++ b/include/cli.h
@@ -107,6 +107,8 @@ int cli_readline_into_buffer(const char *const prompt, char *buffer,
  */
 int cli_simple_parse_line(char *line, char *argv[]);
 
+extern void (*cli_jobs_cb)(void);
+
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 /**
  * cli_process_fdt() - process the boot command from the FDT
diff --git a/include/configs/bcm947622.h b/include/configs/bcm947622.h
new file mode 100644
index 0000000000..94f858285f
--- /dev/null
+++ b/include/configs/bcm947622.h
@@ -0,0 +1,117 @@
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,voiceboardid:voiceboardid,"
+
+/*
+ * 47622
+ */
+
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+
+#define CONFIG_SYS_INIT_STD_32K_ADDR    0xfff80000 
+#define CONFIG_SYS_SEC_CRED_ADDR        (CONFIG_SYS_INIT_STD_32K_ADDR + 0x7000)
+/* U-Boot */
+#if defined(CONFIG_TPL_BUILD)
+/* CONFIG_TPL_TEXT_BASE=0x00020000 */
+/* #define CONFIG_SPL_MAX_SIZE		0x00100000 */
+#define CONFIG_SPL_MAX_SIZE		0x00040000
+#define CONFIG_SPL_BSS_START_ADDR	0x00120000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_TPL_TEXT_BASE + SZ_1M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x00004000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x85200000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x000a0000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+
+/* CONFIG_SPL_TEXT_BASE=0x80820000 */
+#define CONFIG_SPL_MAX_SIZE		0x00040000
+//#define CONFIG_SPL_BSS_START_ADDR	0x85240000
+//#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+#define CONFIG_SYS_PAGETBL_BASE		0x85290000
+#define CONFIG_SYS_PAGETBL_SIZE		0x4000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	(CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024) // max possible size
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_IMG_OFFSET	0x100000
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#ifdef CONFIG_TPL_BUILD
+#elif CONFIG_SPL_BUILD
+#endif
+#endif /* CONFIG_MMC */
+
+#ifdef CONFIG_USB_OHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  2
+#endif /* CONFIG_USB_OHCI_HCD */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/*
+ * bcm947622
+ */
+#define CONFIG_ARCH_CPU_INIT
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		(8 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
diff --git a/include/configs/bcm94908.h b/include/configs/bcm94908.h
new file mode 100644
index 0000000000..4311aa5220
--- /dev/null
+++ b/include/configs/bcm94908.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ *
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CPU_RELEASE_ADDR		0x1000
+#define CONFIG_GICV2			1
+#define GICD_BASE                       0x81001000
+#define GICC_BASE                       0x81002000
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,voiceboardid:voiceboardid,"
+
+/*
+ * 4908
+ */
+
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+
+#define CONFIG_SYS_SEC_CRED_ADDR	0xfff87000
+#define CONFIG_SYS_INIT_STD_32K_ADDR	0xfff80000
+/* U-Boot */
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+
+#elif CONFIG_SPL_BUILD
+
+#define CONFIG_SYS_INIT_RAM_ADDR		0x82200000
+#define CONFIG_SYS_INIT_RAM_OFFSET		0x000a0000
+#define CONFIG_SYS_INIT_RAM_32K_OFFSET		0x00000000
+#define CONFIG_SYS_INIT_RAM_48K_0_OFFSET	0x00010000
+#define CONFIG_SYS_INIT_RAM_48K_1_OFFSET	0x00050000
+#define CONFIG_SYS_INIT_RAM_128K_OFFSET		0x000a0000
+#define CONFIG_SYS_INIT_RAM_ADDR_VIRT		0x822c0000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00040000
+/*
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR_VIRT + CONFIG_SYS_INIT_SP_OFFSET)
+#define CONFIG_SYS_INIT_SP_OFFSET	0x0
+*/
+#define CONFIG_SYS_INIT_SP_ADDR		0x822bfff0 /*0x822b9000+0x8000+0x9800*/
+#define CONFIG_SYS_PAGETBL_BASE		0x7fff0000
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+
+#define CONFIG_SPL_MAX_SIZE		0x00019000
+/* framing bss right after bss text+data*/
+#define CONFIG_SPL_BSS_START_ADDR	0x822b9000
+/*#define CONFIG_SPL_BSS_START_ADDR	0x822c0000*/
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+#define CONFIG_SYS_MALLOC_SIMPLE
+/*STACK_LEN +  CONFIG_SPL_SYS_R_MALLOC_SIMPLE_LEN + GLB DATA 
+ * 0x1000   +  0x8000  + 0x800 (GLB?) = 0x9800
+ * */
+#define CONFIG_SPL_STACK_R_ADDR		0x822ccf00 /*0x822b9000+0x8000+0x9800*/
+	
+#else
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	(CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024) // max possible size
+
+/*
+ * bcm94908
+ */
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#ifdef CONFIG_TPL_BUILD
+#elif CONFIG_SPL_BUILD
+#endif
+#endif /* CONFIG_MMC */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+#define CONFIG_ARCH_CPU_INIT
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		(8 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
+
+#define CONFIG_SYS_NONCACHED_MEMORY	(6*SZ_1M) /* 2MB extra for alignment */
+
+#ifdef CONFIG_USB_OHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  1
+#endif /* CONFIG_USB_OHCI_HCD */
+
diff --git a/include/configs/bcm94912.h b/include/configs/bcm94912.h
new file mode 100644
index 0000000000..5e7443a793
--- /dev/null
+++ b/include/configs/bcm94912.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *
+ * Copyright 2020 Broadcom Ltd.
+ */
+
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,active_port:active_port,voiceboardid:voiceboardid,"
+
+#define CPU_RELEASE_ADDR		0x1000
+#define CONFIG_GICV2			1
+#define GICD_BASE                       0x81001000
+#define GICC_BASE                       0x81002000
+/*
+ * 4912
+ */
+
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_2			0x100000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define PHYS_SDRAM_2_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 1 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_STD_32K_ADDR    0xfff80000 
+#define CONFIG_SYS_INIT_STD_32K_SIZE    0x8000 
+#define CONFIG_SYS_SEC_CRED_ADDR        ( (CONFIG_SYS_INIT_STD_32K_ADDR + CONFIG_SYS_INIT_STD_32K_SIZE) - 0x830)
+/* U-Boot */
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+#elif CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_RAM_ADDR	0x82000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x30000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_PAGETBL_BASE		0x17fff0000ULL
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+
+#define CONFIG_SPL_MAX_SIZE		0x00018000
+#define CONFIG_SPL_BSS_START_ADDR	0x82028000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x800
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	(CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024) // max possible size
+
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_IMG_OFFSET	0x100000
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	4096
+#define CONFIG_SPL_UBI_LEB_START	8192
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#ifdef CONFIG_TPL_BUILD
+#elif CONFIG_SPL_BUILD
+#endif
+#endif /* CONFIG_MMC */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/*
+ * bcm94912
+ */
+
+#define CONFIG_ARCH_CPU_INIT
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		(8 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h
new file mode 100644
index 0000000000..2f6f426025
--- /dev/null
+++ b/include/configs/bcm963138.h
@@ -0,0 +1,112 @@
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(32*1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,voiceboardid:voiceboardid,"
+
+/*
+ * 63138
+ */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80700000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00070000
+
+#define CONFIG_SYS_SEC_CRED_ADDR	(CONFIG_SYS_INIT_RAM_ADDR+0x3f000)
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* U-Boot */
+#if defined(CONFIG_TPL_BUILD)
+/*#define CONFIG_SPL_MAX_SIZE		0x00040000
+#define CONFIG_SPL_BSS_START_ADDR	0x00120000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000*/
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_TPL_TEXT_BASE + SZ_1M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x00004000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#elif defined(CONFIG_SPL_BUILD)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+
+/* CONFIG_SPL_TEXT_BASE=0x80700000 */
+#define CONFIG_SPL_MAX_SIZE		0x00040000
+//#define CONFIG_SPL_BSS_START_ADDR	0x80740000
+//#define CONFIG_SPL_BSS_MAX_SIZE	0x8000
+#define CONFIG_SYS_PAGETBL_BASE		0x80770000
+#define CONFIG_SYS_PAGETBL_SIZE		0x4000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_TEXT_BASE)
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	(CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xfffea000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024) // max possible size
+
+#endif /* CONFIG_NAND */
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_IMG_OFFSET	0x100000
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+
+#ifdef CONFIG_USB_OHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  1
+#endif /* CONFIG_USB_OHCI_HCD */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/*
+ * bcm963138
+ */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(128 << 20)
+#define CONFIG_SYS_FDT_PAD		0x80000
+#define CONFIG_SYS_NONCACHED_MEMORY	(26*SZ_1M) /* 2MB extra for alignment */
+
+#define CONFIG_JFFS2_NAND 1
+
+
diff --git a/include/configs/bcm963146.h b/include/configs/bcm963146.h
new file mode 100644
index 0000000000..916890eb67
--- /dev/null
+++ b/include/configs/bcm963146.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ *
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,active_port:active_port,voiceboardid:voiceboardid,"
+
+#define CPU_RELEASE_ADDR		0x1000
+#define CONFIG_GICV2			1
+#define GICD_BASE                       0x81001000
+#define GICC_BASE                       0x81002000
+/*
+ * 63146
+ */
+
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_2			0x100000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define PHYS_SDRAM_2_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 1 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_STD_32K_ADDR    0xfff80000 
+#define CONFIG_SYS_INIT_STD_32K_SIZE    0x8000 
+#define CONFIG_SYS_SEC_CRED_ADDR        ( (CONFIG_SYS_INIT_STD_32K_ADDR + CONFIG_SYS_INIT_STD_32K_SIZE) - 0x830)
+/* U-Boot */
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+#elif CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_RAM_ADDR	0x82000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x30000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_PAGETBL_BASE		0x17fff0000ULL
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+
+#define CONFIG_SPL_MAX_SIZE		0x00018000
+#define CONFIG_SPL_BSS_START_ADDR	0x82028000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x800
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_TEXT_BASE)
+
+#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	(CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024) // max possible size
+
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_IMG_OFFSET	0x100000
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	4096
+#define CONFIG_SPL_UBI_LEB_START	8192
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#ifdef CONFIG_TPL_BUILD
+#elif CONFIG_SPL_BUILD
+#endif
+#endif /* CONFIG_MMC */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/*
+ * bcm963146
+ */
+
+#define CONFIG_ARCH_CPU_INIT
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		(8 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
diff --git a/include/configs/bcm963148.h b/include/configs/bcm963148.h
new file mode 100644
index 0000000000..2b5cb2fdb2
--- /dev/null
+++ b/include/configs/bcm963148.h
@@ -0,0 +1,112 @@
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(32*1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN		(16 * 1024 * 1024)
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,voiceboardid:voiceboardid,"
+
+/*
+ * 631138
+ */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80700000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00070000
+#define CONFIG_SYS_SEC_CRED_ADDR	(CONFIG_SYS_INIT_RAM_ADDR+0x3f000)
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* U-Boot */
+#if defined(CONFIG_TPL_BUILD)
+/*#define CONFIG_SPL_MAX_SIZE		0x00040000
+#define CONFIG_SPL_BSS_START_ADDR	0x00120000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000*/
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_TPL_TEXT_BASE + SZ_1M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x00004000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#elif defined(CONFIG_SPL_BUILD)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+
+/* CONFIG_SPL_TEXT_BASE=0x80700000 */
+#define CONFIG_SPL_MAX_SIZE		0x00040000
+//#define CONFIG_SPL_BSS_START_ADDR	0x80740000
+//#define CONFIG_SPL_BSS_MAX_SIZE	0x8000
+#define CONFIG_SYS_PAGETBL_BASE		0x80770000
+#define CONFIG_SYS_PAGETBL_SIZE		0x4000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_TEXT_BASE)
+
+/* #define CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	(CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xfffea000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024) // max possible size
+
+#endif /* CONFIG_NAND */
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_IMG_OFFSET	0x100000
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+
+#ifdef CONFIG_USB_OHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  1
+#endif /* CONFIG_USB_OHCI_HCD */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/*
+ * bcm963148
+ */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(128 << 20)
+#define CONFIG_SYS_FDT_PAD		0x80000
+#define CONFIG_SYS_NONCACHED_MEMORY	(26*SZ_1M) /* 2MB extra for alignment */
+
+#if !defined(CONFIG_TPL_ATF)
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_SMP_PEN_ADDR		0x0
+#endif
diff --git a/include/configs/bcm963158.h b/include/configs/bcm963158.h
new file mode 100644
index 0000000000..845c867c0d
--- /dev/null
+++ b/include/configs/bcm963158.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ *
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CPU_RELEASE_ADDR		0x1000
+#define CONFIG_GICV2			1
+#define GICD_BASE                       0x81001000
+#define GICC_BASE                       0x81002000
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,voiceboardid:voiceboardid,"
+
+/*
+ * 63158
+ */
+
+#define CONFIG_SYS_INIT_STD_32K_ADDR    0xfff80000 
+#define CONFIG_SYS_SEC_CRED_ADDR        (CONFIG_SYS_INIT_STD_32K_ADDR + 0x7000)
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_2			0x100000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define PHYS_SDRAM_2_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 1 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* U-Boot */
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+#elif CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80800000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x000a0000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_PAGETBL_BASE		0x808a0000
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+
+#define CONFIG_SPL_MAX_SIZE		0x00020000
+#define CONFIG_SPL_BSS_START_ADDR	0x80840000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_TEXT_BASE)
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	(CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024) // max possible size
+
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_IMG_OFFSET	0x100000
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	4096
+#define CONFIG_SPL_UBI_LEB_START	8192
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#ifdef CONFIG_TPL_BUILD
+#elif CONFIG_SPL_BUILD
+#endif
+#endif /* CONFIG_MMC */
+
+#ifdef CONFIG_USB_OHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  2
+#endif /* CONFIG_USB_OHCI_HCD */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/*
+ * bcm963158
+ */
+
+#define CONFIG_ARCH_CPU_INIT
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		(8 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
diff --git a/include/configs/bcm963178.h b/include/configs/bcm963178.h
new file mode 100644
index 0000000000..6bdce47e66
--- /dev/null
+++ b/include/configs/bcm963178.h
@@ -0,0 +1,105 @@
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,voiceboardid:voiceboardid,"
+
+/*
+ * 63178
+ */
+
+#define CONFIG_SYS_INIT_STD_32K_ADDR    0xfff80000 
+#define CONFIG_SYS_SEC_CRED_ADDR        (CONFIG_SYS_INIT_STD_32K_ADDR + 0x7000)
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* U-Boot */
+#if defined(CONFIG_TPL_BUILD)
+/* CONFIG_TPL_TEXT_BASE=0x00020000 */
+/* #define CONFIG_SPL_MAX_SIZE		0x00100000 */
+#define CONFIG_SPL_MAX_SIZE		0x00040000
+#define CONFIG_SPL_BSS_START_ADDR	0x00120000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_TPL_TEXT_BASE + SZ_1M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x00004000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x84200000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x000a0000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+
+/* CONFIG_SPL_TEXT_BASE=0x80820000 */
+#define CONFIG_SPL_MAX_SIZE		0x00040000
+//#define CONFIG_SPL_BSS_START_ADDR	0x84240000
+//#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+#define CONFIG_SYS_PAGETBL_BASE		0x84290000
+#define CONFIG_SYS_PAGETBL_SIZE		0x4000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_TEXT_BASE)
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	(CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024) // max possible size
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_IMG_OFFSET	0x100000
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+#endif /* CONFIG_NAND */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/*
+ * bcm963178
+ */
+#define CONFIG_ARCH_CPU_INIT
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		(8 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
diff --git a/include/configs/bcm96756.h b/include/configs/bcm96756.h
new file mode 100644
index 0000000000..92229d704e
--- /dev/null
+++ b/include/configs/bcm96756.h
@@ -0,0 +1,122 @@
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,voiceboardid:voiceboardid,"
+
+/*
+ * 6756
+ */
+
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+
+#define CONFIG_SYS_INIT_STD_32K_ADDR    0xfff80000 
+#define CONFIG_SYS_SEC_CRED_ADDR        (CONFIG_SYS_INIT_STD_32K_ADDR + 0x7000)
+/* U-Boot */
+#if defined(CONFIG_TPL_BUILD)
+/* CONFIG_TPL_TEXT_BASE=0x00020000 */
+/* #define CONFIG_SPL_MAX_SIZE		0x00100000 */
+#define CONFIG_SPL_MAX_SIZE		0x00040000
+#define CONFIG_SPL_BSS_START_ADDR	0x00120000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_TPL_TEXT_BASE + SZ_1M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x00004000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x85200000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x000a0000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+
+/* CONFIG_SPL_TEXT_BASE=0x80820000 */
+#define CONFIG_SPL_MAX_SIZE		0x00040000
+//#define CONFIG_SPL_BSS_START_ADDR	0x85240000
+//#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+#define CONFIG_SYS_PAGETBL_BASE		0x85290000
+#define CONFIG_SYS_PAGETBL_SIZE		0x4000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	(CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024) // max possible size
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_IMG_OFFSET	0x100000
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#ifdef CONFIG_TPL_BUILD
+#elif CONFIG_SPL_BUILD
+#endif
+#endif /* CONFIG_MMC */
+
+#ifdef CONFIG_USB_OHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  2
+#endif /* CONFIG_USB_OHCI_HCD */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/*
+ * bcm96756
+ */
+#define CONFIG_ARCH_CPU_INIT
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		(8 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
+
+#if !defined(CONFIG_TPL_ATF)
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_SMP_PEN_ADDR 0x0
+#endif
diff --git a/include/configs/bcm96846.h b/include/configs/bcm96846.h
new file mode 100644
index 0000000000..3ff54d889f
--- /dev/null
+++ b/include/configs/bcm96846.h
@@ -0,0 +1,120 @@
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,active_port:active_port,voiceboardid:voiceboardid,"
+
+/*
+ * 6846
+ */
+
+/* RAM */
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_STD_32K_ADDR    0xfff80000 
+#define CONFIG_SYS_SEC_CRED_ADDR        (CONFIG_SYS_INIT_STD_32K_ADDR + 0x7000)
+/* U-Boot */
+#if defined(CONFIG_TPL_BUILD)
+#define CONFIG_SPL_MAX_SIZE		0x00040000
+#define CONFIG_SPL_BSS_START_ADDR	0x00120000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_TPL_TEXT_BASE + SZ_1M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x00004000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_INIT_RAM_ADDR	0x82600000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00030000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SPL_MAX_SIZE		0x00020000
+#define CONFIG_SYS_PAGETBL_BASE		0x7fff0000
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_TEXT_BASE)
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS (CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST  0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE  (256*1024) // max possible size
+#endif /* CONFIG_NAND */
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_IMG_OFFSET	0x100000
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+//#define CONFIG_UBI_SILENCE_MSG
+
+#ifdef CONFIG_MMC
+#ifdef CONFIG_TPL_BUILD
+#elif CONFIG_SPL_BUILD
+#endif
+#endif /* CONFIG_MMC */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/*
+ * bcm96846
+ */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BROM_REG_ADDR	0xff800600
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		(8 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
+
+#ifdef CONFIG_USB_OHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  1
+#endif /* CONFIG_USB_OHCI_HCD */
+
+#if !defined(CONFIG_TPL_ATF)
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_SMP_PEN_ADDR 0x0
+#endif
+
diff --git a/include/configs/bcm96855.h b/include/configs/bcm96855.h
new file mode 100644
index 0000000000..dcdb799b67
--- /dev/null
+++ b/include/configs/bcm96855.h
@@ -0,0 +1,114 @@
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,active_port:active_port,"
+
+/*
+ * 6855
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x82000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00040000
+#define CONFIG_SYS_SEC_CRED_ADDR	((CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_SIZE)-0x400)
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* U-Boot */
+#if defined(CONFIG_TPL_BUILD)
+#define CONFIG_SPL_MAX_SIZE		0x00040000
+#define CONFIG_SPL_BSS_START_ADDR	0x00120000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_TPL_TEXT_BASE + SZ_1M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x00004000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#elif defined(CONFIG_SPL_BUILD)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SPL_MAX_SIZE		0x00020000
+#define CONFIG_SYS_PAGETBL_BASE		0x82700000
+#define CONFIG_SYS_PAGETBL_SIZE		0x4000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_TEXT_BASE)
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS (CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST  0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE  (256*1024) // max possible size
+#endif /* CONFIG_NAND */
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_IMG_OFFSET	0x100000
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+//#define CONFIG_UBI_SILENCE_MSG
+
+#ifdef CONFIG_MMC
+#ifdef CONFIG_TPL_BUILD
+#elif CONFIG_SPL_BUILD
+#endif
+#endif /* CONFIG_MMC */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/*
+ * bcm96855
+ */
+
+#define CONFIG_ARCH_CPU_INIT
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		(8 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
+
+#if !defined(CONFIG_TPL_ATF)
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_SMP_PEN_ADDR 0x0
+#endif
+#ifdef CONFIG_USB_OHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  2
+#endif /* CONFIG_USB_OHCI_HCD */
diff --git a/include/configs/bcm96856.h b/include/configs/bcm96856.h
new file mode 100644
index 0000000000..d8beac8f8f
--- /dev/null
+++ b/include/configs/bcm96856.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ *
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CPU_RELEASE_ADDR		0x1000
+#define CONFIG_GICV2			1
+#define GICD_BASE				0x81001000
+#define GICC_BASE				0x81002000
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,active_port:active_port,voiceboardid:voiceboardid,"
+
+/*
+ * 6856
+ */
+
+#define CONFIG_SYS_INIT_STD_32K_ADDR    0xfff80000 
+#define CONFIG_SYS_SEC_CRED_ADDR        (CONFIG_SYS_INIT_STD_32K_ADDR + 0x7000)
+
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* U-Boot */
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+#elif CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_RAM_ADDR	0x82600000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00080000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_PAGETBL_BASE		0x7fff0000
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+
+#define CONFIG_SPL_MAX_SIZE		0x00020000
+#define CONFIG_SPL_BSS_START_ADDR	0x82640000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_TEXT_BASE)
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	(CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024) // max possible size
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#ifdef CONFIG_TPL_BUILD
+#elif CONFIG_SPL_BUILD
+#endif
+#endif /* CONFIG_MMC */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+#define CONFIG_ARCH_CPU_INIT
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		(8 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
+
+#ifdef CONFIG_USB_OHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  2
+#endif /* CONFIG_USB_OHCI_HCD */
diff --git a/include/configs/bcm96858.h b/include/configs/bcm96858.h
new file mode 100644
index 0000000000..8c3a194fb5
--- /dev/null
+++ b/include/configs/bcm96858.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ *
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CPU_RELEASE_ADDR		0x1000
+#define CONFIG_GICV2			1
+#define GICD_BASE				0x81001000
+#define GICC_BASE				0x81002000
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,active_port:active_port,voiceboardid:voiceboardid,"
+
+/*
+ * 6858
+ */
+#define CONFIG_SYS_INIT_STD_32K_ADDR    0xfff80000 
+#define CONFIG_SYS_SEC_CRED_ADDR        (CONFIG_SYS_INIT_STD_32K_ADDR + 0x7000)
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* U-Boot */
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+#elif CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_RAM_ADDR	0x82600000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00080000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_PAGETBL_BASE		0x7fff0000
+#define CONFIG_SYS_PAGETBL_SIZE		0x10000
+
+#define CONFIG_SPL_MAX_SIZE		0x00020000
+#define CONFIG_SPL_BSS_START_ADDR	0x82640000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_TEXT_BASE)
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	(CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024) // max possible size
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#ifdef CONFIG_TPL_BUILD
+#elif CONFIG_SPL_BUILD
+#endif
+#endif /* CONFIG_MMC */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+#define CONFIG_ARCH_CPU_INIT
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		8 * 1024
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
+
+#ifdef CONFIG_USB_OHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  2
+#endif /* CONFIG_USB_OHCI_HCD */
diff --git a/include/configs/bcm96878.h b/include/configs/bcm96878.h
new file mode 100644
index 0000000000..86b533e7d6
--- /dev/null
+++ b/include/configs/bcm96878.h
@@ -0,0 +1,123 @@
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 * 32)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+#define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,active_port:active_port,voiceboardid:voiceboardid,"
+
+/*
+ * 6878
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x82600000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00020000
+#define CONFIG_SYS_SEC_CRED_ADDR	((CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_SIZE)-0x400)
+/* RAM */
+#define PHYS_SDRAM_1			0x00000000UL
+#define PHYS_SDRAM_1_SIZE		(2UL * SZ_1G) /* Maximum possible bnk 0 size */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* U-Boot */
+#if defined(CONFIG_TPL_BUILD)
+#define CONFIG_SPL_MAX_SIZE		0x00040000
+#define CONFIG_SPL_BSS_START_ADDR	0x00120000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_TPL_TEXT_BASE + SZ_1M)
+#define CONFIG_SYS_PAGETBL_BASE		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_PAGETBL_SIZE		0x00004000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+#elif defined(CONFIG_SPL_BUILD)
+
+#if !defined(CONFIG_BCMBCA_BOARD_TK_PROG)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#define CONFIG_SPL_MAX_SIZE		0x00010000
+
+#else
+/* special layout for TKMFG framework */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SEC_CRED_ADDR-GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SPL_MAX_SIZE		0x00014000
+
+#endif
+
+#define CONFIG_SYS_PAGETBL_BASE		0x82c10000
+#define CONFIG_SYS_PAGETBL_SIZE		0x8000
+
+#define CONFIG_SYS_MALLOC_SIMPLE
+
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_TEXT_BASE)
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS (CONFIG_TPL_TEXT_BASE + 0x2000000)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE            0xff801800
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* dummy definition to make spl nand image loader happy */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
+#define CONFIG_SYS_NAND_U_BOOT_DST  0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_BLOCK_SIZE  (256*1024) // max possible size
+#endif /* CONFIG_NAND */
+
+#define CONFIG_TPL_UBI
+#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
+#define CONFIG_SPL_UBI_MAX_PEB_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_SPL_UBI_IMG_OFFSET	0x100000
+#define CONFIG_SPL_UBI_MAX_PEBS 	4096
+#define CONFIG_SPL_UBI_VOL_IDS		8
+#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
+#define CONFIG_SPL_UBI_PEB_OFFSET	4
+#define CONFIG_SPL_UBI_VID_OFFSET	512
+#define CONFIG_SPL_UBI_LEB_START	2048
+#define CONFIG_SPL_UBI_INFO_ADDR	(CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
+//#define CONFIG_UBI_SILENCE_MSG
+
+#ifdef CONFIG_MMC
+#ifdef CONFIG_TPL_BUILD
+#elif CONFIG_SPL_BUILD
+#endif
+#endif /* CONFIG_MMC */
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/*
+ * bcm96878
+ */
+
+#define CONFIG_ARCH_CPU_INIT
+#define COUNTER_FREQUENCY       50000000
+#define CONFIG_ENV_SIZE		(8 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ	(128 << 20)
+#define CONFIG_SYS_FDT_PAD	0x80000
+
+#if !defined(CONFIG_TPL_ATF)
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_SMP_PEN_ADDR 0x0
+#endif
+#ifdef CONFIG_USB_OHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  2
+#endif /* CONFIG_USB_OHCI_HCD */
diff --git a/include/dni_common.h b/include/dni_common.h
new file mode 100755
index 0000000000..64d9b6afbd
--- /dev/null
+++ b/include/dni_common.h
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DNI_COMMON_H_
+#define __DNI_COMMON_H_	1
+
+#define CONFIG_SYS_FLASH_SECTOR_SIZE 0x20000
+#define BOARD_MODEL_ID_LENGTH                    18
+#define CONFIG_SYS_IMAGE_BASE_ADDR  0xb80000
+#define CONFIG_SYS_IMAGE_ADDR_BEGIN (CONFIG_SYS_IMAGE_BASE_ADDR)
+#define CONFIG_SYS_IMAGE_LEN   0x4000000
+#define CONFIG_SYS_STRING_TABLE_LEN  0x40000  /* Each string table takes 256KB to save.  */
+#define CONFIG_SYS_STRING_TABLE_NUMBER 7
+#define CONFIG_SYS_STRING_TABLE_TOTAL_LEN  0x100000  /* Totally allocate 3584KB to save all string tables. */
+#define CONFIG_SYS_STRING_TABLE_BASE_ADDR  0x5680000
+#define CONFIG_SYS_STRING_TABLE_ADDR_BEGIN (CONFIG_SYS_STRING_TABLE_BASE_ADDR)
+#define CONFIG_SYS_STRING_TABLE_ADDR_END   (CONFIG_SYS_STRING_TABLE_ADDR_BEGIN + CONFIG_SYS_STRING_TABLE_TOTAL_LEN)
+
+#ifdef DNI_NAND
+#include <nand.h>
+
+void update_data(ulong, int, ulong, size_t, int, int);
+//size_t get_len_incl_bad (nand_info_t *, loff_t, const size_t);
+#endif
+
+void get_board_data(int offset, int len, u8* buf);
+int set_board_data(int offset, int len, u8 *buf);
+
+#ifdef NETGEAR_BOARD_ID_SUPPORT
+int board_match_image_hw_id(ulong);
+int board_match_image_model_id(ulong);
+void board_update_image_model_id(ulong);
+#endif
+
+#if defined(NETGEAR_BOARD_ID_SUPPORT) && \
+    defined(OPEN_SOURCE_ROUTER_SUPPORT) && defined(OPEN_SOURCE_ROUTER_ID)
+extern int board_model_id_match_open_source_id(void);
+extern int image_match_open_source_fw_id(ulong);
+extern int board_image_reserved_length(void);
+#else
+static inline int board_model_id_match_open_source_id(void)
+{
+	return 0;
+}
+static inline int image_match_open_source_fw_id(ulong fw_image_addr)
+{
+	return 0;
+}
+static inline int board_image_reserved_length(void)
+{
+	return 0;
+}
+#endif  /* NETGEAR_BOARD_ID_SUPPORT && OPEN_SOURCE_ROUTER */
+
+#if defined(WORKAROUND_QCA8337_GMAC_NMRP_HANG)
+#define workaround_qca8337_gmac_nmrp_hang_action()  do {  \
+	DECLARE_GLOBAL_DATA_PTR;  \
+	eth_halt();  \
+	eth_init(gd->bd);  \
+} while (0)
+#else
+#define workaround_qca8337_gmac_nmrp_hang_action()  do {} while (0)
+#endif
+
+#if defined(WORKAROUND_DUPLICATE_TFTP_DATA_PACKET_BUG_OF_NMRP_SERVER)
+#define workaround_duplicate_tftp_data_packet_bug_of_nmrp_server()  do {  \
+	timeout = 1000UL;  \
+} while (0)
+#else
+#define workaround_duplicate_tftp_data_packet_bug_of_nmrp_server()  do {  \
+} while (0)
+#endif
+
+#if defined(WORKAROUND_IPQ40XX_GMAC_NMRP_HANG)
+#define workaround_ipq40xx_gmac_nmrp_hang_action()  do {  \
+	DECLARE_GLOBAL_DATA_PTR;  \
+	eth_halt();  \
+	eth_init(gd->bd);  \
+} while (0)
+#else
+#define workaround_ipq40xx_gmac_nmrp_hang_action()  do {} while (0)
+#endif
+
+#endif	/* __DNI_COMMON_H_ */
diff --git a/include/dt-bindings/leds/bcm_bca_leds_dt_bindings.h b/include/dt-bindings/leds/bcm_bca_leds_dt_bindings.h
new file mode 100644
index 0000000000..137efb8973
--- /dev/null
+++ b/include/dt-bindings/leds/bcm_bca_leds_dt_bindings.h
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Broadcom
+ */
+/*
+*  
+*/
+
+#ifndef BCM_BCA_LED_DT_BINDINGS_H
+#define BCM_BCA_LED_DT_BINDINGS_H
+
+#define LED_SPEED_10   0x00000001
+#define LED_SPEED_100  0x00000002
+#define LED_SPEED_1G   0x00000004
+#define LED_SPEED_2500 0x00000008
+#define LED_SPEED_10G  0x00000010
+
+#define LED_SPEED_FAE  (LED_SPEED_10 | LED_SPEED_100)
+#define LED_SPEED_GBE  (LED_SPEED_FAE | LED_SPEED_1G)
+#define LED_SPEED_ALL  (LED_SPEED_GBE | LED_SPEED_2500 | LED_SPEED_10G)
+
+#define STATE_ON  1
+#define STATE_OFF 1
+#endif
diff --git a/include/environment.h b/include/environment.h
index cd96676141..62e14cfb00 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -189,6 +189,7 @@ enum env_location {
 	ENVL_REMOTE,
 	ENVL_SPI_FLASH,
 	ENVL_UBI,
+	ENVL_BOOT_MAGIC,
 	ENVL_NOWHERE,
 
 	ENVL_COUNT,
diff --git a/include/image.h b/include/image.h
index bb7089ef5d..e7dc949a18 100644
--- a/include/image.h
+++ b/include/image.h
@@ -64,7 +64,7 @@ struct fdt_region;
 #  ifdef CONFIG_SPL_MD5_SUPPORT
 #   define IMAGE_ENABLE_MD5	1
 #  endif
-#  ifdef CONFIG_SPL_SHA1_SUPPORT
+#  if CONFIG_IS_ENABLED(SHA1_SUPPORT)
 #   define IMAGE_ENABLE_SHA1	1
 #  endif
 # else
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 13e8dd1103..fa5889722d 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -11,6 +11,7 @@
 #define __LINUX_MTD_NAND_H
 
 #include <linux/mtd/mtd.h>
+#include <linux/bitops.h>
 
 /**
  * struct nand_memory_organization - Memory organization structure
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index be01e1e82e..45fa9b0274 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -205,6 +205,7 @@ extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
 extern const struct spinand_manufacturer macronix_spinand_manufacturer;
 extern const struct spinand_manufacturer micron_spinand_manufacturer;
 extern const struct spinand_manufacturer winbond_spinand_manufacturer;
+extern const struct spinand_manufacturer broadcom_spinand_manufacturer;
 
 /**
  * struct spinand_op_variants - SPI NAND operation variants
diff --git a/include/linux/mtd/spinand_mini.h b/include/linux/mtd/spinand_mini.h
new file mode 100644
index 0000000000..2948aa07bd
--- /dev/null
+++ b/include/linux/mtd/spinand_mini.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ *  Copyright 2020 Broadcom Ltd.
+ */
+
+#ifndef _SPINAND_MINI_H
+#define _SPINAND_MINI_H
+
+#include <spi.h>
+#include <spi-mem.h>
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_WINBOND		0xEF
+#define SPINAND_MFR_GIGADEVICE_ESMT	0xC8
+#define SPINAND_MFR_MACRONIX		0xC2
+#define SPINAND_MFR_TOSHIBA		0x98
+#define SPINAND_MFR_MICRON		0x2C
+#define SPINAND_MFR_PARAGON		0xA1
+
+
+#define SPINAND_READID_OP_EXT(naddr, ndummy, buf, len)		\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),			\
+		   SPI_MEM_OP_ADDR(naddr, 0, 1),		\
+		   SPI_MEM_OP_DUMMY(ndummy, 1),			\
+		   SPI_MEM_OP_DATA_IN(len, buf, 1))
+
+
+#define SPINAND_READID_OP_ONLY(buf, len)			\
+	SPINAND_READID_OP_EXT(0, 0, buf, len)
+
+#define SPINAND_READID_OP_ADDR(buf, len)			\
+	SPINAND_READID_OP_EXT(1, 0, buf, len)
+
+#define SPINAND_READID_OP_DUMMY(buf, len)			\
+	SPINAND_READID_OP_EXT(0, 1, buf, len)
+
+#pragma pack(push,1)
+struct spinandmini_mem_org {
+	u8 bits_per_cell;
+	u16 pagesize;
+	u16 pages_per_eraseblock;
+	u16 eraseblocks_per_lun;
+	u8 planes_per_lun;
+	u8 luns_per_target;
+	u8 ntargets;
+};
+
+#define SPINANDMINI_MEMORG(bpc, ps, os, ppe, epl, ppl, lpt, nt)	\
+	{							\
+		.bits_per_cell = (bpc),				\
+		.pagesize = (ps),				\
+		.pages_per_eraseblock = (ppe),			\
+		.eraseblocks_per_lun = (epl),			\
+		.planes_per_lun = (ppl),			\
+		.luns_per_target = (lpt),			\
+		.ntargets = (nt),				\
+	}
+
+struct spinandmini_info {
+	u8 id[SPINAND_MAX_ID_LEN];
+	u8 id_len;
+	struct spinandmini_mem_org memorg;
+};
+#pragma pack(pop)
+
+struct spinandmini_device {
+	struct spi_slave *slave;  
+	struct spinand_id id;
+	const struct spinandmini_mem_org* memorg;
+	u32 page_shift;
+	u32 block_shift;
+  	u64 target_shift; /* die shift */
+	u32 block_size;
+	u32 page_size;
+	u64 total_size;
+	int (*select_target)(struct spinandmini_device *spinand,
+			     unsigned int target);
+	unsigned int cur_target;
+	u8 *cfg_cache;
+};
+
+void spinandmini_init(void);
+u32 spinandmini_get_block_size(void);
+u32 spinandmini_get_page_size(void);
+u64 spinandmini_get_total_size(void);
+int spinandmini_read_buf(int block, int offset, u8 *dst, u32 len);
+int spinandmini_is_bad_block(int block);
+
+#endif
diff --git a/include/net.h b/include/net.h
index 44b32385c4..cf8b3f8e02 100644
--- a/include/net.h
+++ b/include/net.h
@@ -344,6 +344,8 @@ struct vlan_ethernet_hdr {
 #define PROT_IPV6	0x86dd		/* IPv6 over bluebook		*/
 #define PROT_PPP_SES	0x8864		/* PPPoE session messages	*/
 
+#define PROT_NMRP       0x0912
+
 #define IPPROTO_ICMP	 1	/* Internet Control Message Protocol	*/
 #define IPPROTO_UDP	17	/* User Datagram Protocol		*/
 
@@ -528,9 +530,43 @@ extern ushort		net_native_vlan;	/* Our Native VLAN */
 
 extern int		net_restart_wrap;	/* Tried all network devices */
 
+#ifdef FIRMWARE_RECOVER_FROM_TFTP_SERVER
+extern uchar NetOurTftpIP[4];
+extern int NetRunTftpServer;
+extern uchar TftpClientEther[6];    /* TFTP Client enet address      */
+extern struct in_addr TftpClientIP;       /* Client IP addr (0 = unknown)  */
+extern void StartTftpServerToRecoveFirmware(void);
+#if defined(CONFIG_SYS_NMRP) && defined(CONFIG_SYS_SINGLE_FIRMWARE)
+extern void UpgradeFirmwareFromNmrpServer(void);
+extern void CheckNmrpAliveTimerExpire(int send_nmrp_alive);
+#endif
+extern void ResetTftpServer(void);
+#endif
+
+#define IP_ADDR_LEN 4
+typedef struct{
+        ushort type;
+
+        ushort len;
+        uchar value;
+}NMRP_OPT;
+typedef struct {
+        ushort reserved;
+        uchar code;
+        uchar id;
+        ushort length;
+        NMRP_OPT opt;
+}nmrp_t;
+extern int NmrpState;
+extern struct in_addr NmrpClientIP;
+extern uchar NmrpClientEther[6];
+extern uchar NmrpServerEther[6];
+#define NMRP_HDR_LEN (sizeof(nmrp_t) - sizeof(NMRP_OPT))
+#define MIN_ETHER_NMRP_LEN (sizeof(struct ethernet_hdr) + NMRP_HDR_LEN)
+
 enum proto_t {
 	BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
-	TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL
+	TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, NMRP
 };
 
 extern char	net_boot_file_name[1024];/* Boot File name */
@@ -874,4 +910,6 @@ int update_tftp(ulong addr, char *interface, char *devstring);
 
 /**********************************************************************/
 
+extern int (*ip_tap)(uchar *in_packet, int len, struct ip_udp_hdr *ip);
+
 #endif /* __NET_H__ */
diff --git a/include/uboot_aes.h b/include/uboot_aes.h
index 2fda384e3b..d2583bed99 100644
--- a/include/uboot_aes.h
+++ b/include/uboot_aes.h
@@ -18,16 +18,24 @@ typedef unsigned int u32;
  * AES encryption library, with small code size, supporting only 128-bit AES
  *
  * AES is a stream cipher which works a block at a time, with each block
- * in this case being AES_KEY_LENGTH bytes.
+ * in this case being AES_BLOCK_LENGTH bytes.
  */
 
 enum {
 	AES_STATECOLS	= 4,	/* columns in the state & expanded key */
-	AES_KEYCOLS	= 4,	/* columns in a key */
-	AES_ROUNDS	= 10,	/* rounds in encryption */
-
-	AES_KEY_LENGTH	= 128 / 8,
-	AES_EXPAND_KEY_LENGTH	= 4 * AES_STATECOLS * (AES_ROUNDS + 1),
+	AES128_KEYCOLS	= 4,	/* columns in a key for aes128 */
+	AES192_KEYCOLS	= 6,	/* columns in a key for aes128 */
+	AES256_KEYCOLS	= 8,	/* columns in a key for aes128 */
+	AES128_ROUNDS	= 10,	/* rounds in encryption for aes128 */
+	AES192_ROUNDS	= 12,	/* rounds in encryption for aes192 */
+	AES256_ROUNDS	= 14,	/* rounds in encryption for aes256 */
+	AES128_KEY_LENGTH	= 128 / 8,
+	AES192_KEY_LENGTH	= 192 / 8,
+	AES256_KEY_LENGTH	= 256 / 8,
+	AES128_EXPAND_KEY_LENGTH = 4 * AES_STATECOLS * (AES128_ROUNDS + 1),
+	AES192_EXPAND_KEY_LENGTH = 4 * AES_STATECOLS * (AES192_ROUNDS + 1),
+	AES256_EXPAND_KEY_LENGTH = 4 * AES_STATECOLS * (AES256_ROUNDS + 1),
+	AES_BLOCK_LENGTH	= 128 / 8,
 };
 
 /**
@@ -36,33 +44,36 @@ enum {
  * Expand a key into a key schedule, which is then used for the other
  * operations.
  *
- * @key		Key, of length AES_KEY_LENGTH bytes
+ * @key		Key
+ * @key_size	Size of the key (in bits)
  * @expkey	Buffer to place expanded key, AES_EXPAND_KEY_LENGTH
  */
-void aes_expand_key(u8 *key, u8 *expkey);
+void aes_expand_key(u8 *key, u32 key_size, u8 *expkey);
 
 /**
  * aes_encrypt() - Encrypt single block of data with AES 128
  *
+ * @key_size	Size of the aes key (in bits)
  * @in		Input data
  * @expkey	Expanded key to use for encryption (from aes_expand_key())
  * @out		Output data
  */
-void aes_encrypt(u8 *in, u8 *expkey, u8 *out);
+void aes_encrypt(u32 key_size, u8 *in, u8 *expkey, u8 *out);
 
 /**
  * aes_decrypt() - Decrypt single block of data with AES 128
  *
+ * @key_size	Size of the aes key (in bits)
  * @in		Input data
  * @expkey	Expanded key to use for decryption (from aes_expand_key())
  * @out		Output data
  */
-void aes_decrypt(u8 *in, u8 *expkey, u8 *out);
+void aes_decrypt(u32 key_size, u8 *in, u8 *expkey, u8 *out);
 
 /**
  * Apply chain data to the destination using EOR
  *
- * Each array is of length AES_KEY_LENGTH.
+ * Each array is of length AES_BLOCK_LENGTH.
  *
  * @cbc_chain_data	Chain data
  * @src			Source data
@@ -73,25 +84,27 @@ void aes_apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst);
 /**
  * aes_cbc_encrypt_blocks() - Encrypt multiple blocks of data with AES CBC.
  *
+ * @key_size		Size of the aes key (in bits)
  * @key_exp		Expanded key to use
  * @iv			Initialization vector
  * @src			Source data to encrypt
  * @dst			Destination buffer
  * @num_aes_blocks	Number of AES blocks to encrypt
  */
-void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+void aes_cbc_encrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
 			    u32 num_aes_blocks);
 
 /**
  * Decrypt multiple blocks of data with AES CBC.
  *
+ * @key_size		Size of the aes key (in bits)
  * @key_exp		Expanded key to use
  * @iv			Initialization vector
  * @src			Source data to decrypt
  * @dst			Destination buffer
  * @num_aes_blocks	Number of AES blocks to decrypt
  */
-void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+void aes_cbc_decrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
 			    u32 num_aes_blocks);
 
 #endif /* _AES_REF_H_ */
diff --git a/include/wait_bit.h b/include/wait_bit.h
index 82e09da5ca..79da0811fe 100644
--- a/include/wait_bit.h
+++ b/include/wait_bit.h
@@ -72,10 +72,12 @@ static inline int wait_for_bit_##sfx(const void *reg,			\
 
 BUILD_WAIT_FOR_BIT(8, u8, readb)
 BUILD_WAIT_FOR_BIT(le16, u16, readw)
+BUILD_WAIT_FOR_BIT(16, u16, readw)
 #ifdef readw_be
 BUILD_WAIT_FOR_BIT(be16, u16, readw_be)
 #endif
 BUILD_WAIT_FOR_BIT(le32, u32, readl)
+BUILD_WAIT_FOR_BIT(32, u32, readl)
 #ifdef readl_be
 BUILD_WAIT_FOR_BIT(be32, u32, readl_be)
 #endif
diff --git a/lib/Makefile b/lib/Makefile
index 2fffd68f94..81dadc0f4a 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -117,4 +117,8 @@ else
 obj-y += vsprintf.o strto.o strmhz.o
 endif
 
+#ifdef CONFIG_TPL_BUILD
+obj-$(CONFIG_AES) += aes.o
+#endif
+
 subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
diff --git a/lib/aes.c b/lib/aes.c
index a12a192084..ce53c9f1f3 100644
--- a/lib/aes.c
+++ b/lib/aes.c
@@ -508,50 +508,79 @@ static u8 rcon[11] = {
 	0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
 };
 
+static u32 aes_get_rounds(u32 key_len)
+{
+	u32 rounds = AES128_ROUNDS;
+
+	if (key_len == AES192_KEY_LENGTH)
+		rounds = AES192_ROUNDS;
+	else if (key_len == AES256_KEY_LENGTH)
+		rounds = AES256_ROUNDS;
+
+	return rounds;
+}
+
+static u32 aes_get_keycols(u32 key_len)
+{
+	u32 keycols = AES128_KEYCOLS;
+
+	if (key_len == AES192_KEY_LENGTH)
+		keycols = AES192_KEYCOLS;
+	else if (key_len == AES256_KEY_LENGTH)
+		keycols = AES256_KEYCOLS;
+
+	return keycols;
+}
+
 /* produce AES_STATECOLS bytes for each round */
-void aes_expand_key(u8 *key, u8 *expkey)
+void aes_expand_key(u8 *key, u32 key_len, u8 *expkey)
 {
 	u8 tmp0, tmp1, tmp2, tmp3, tmp4;
-	u32 idx;
+	u32 idx, aes_rounds, aes_keycols;
 
-	memcpy(expkey, key, AES_KEYCOLS * 4);
+	aes_rounds = aes_get_rounds(key_len);
+	aes_keycols = aes_get_keycols(key_len);
 
-	for (idx = AES_KEYCOLS; idx < AES_STATECOLS * (AES_ROUNDS + 1); idx++) {
+	memcpy(expkey, key, key_len);
+
+	for (idx = aes_keycols; idx < AES_STATECOLS * (aes_rounds + 1); idx++) {
 		tmp0 = expkey[4*idx - 4];
 		tmp1 = expkey[4*idx - 3];
 		tmp2 = expkey[4*idx - 2];
 		tmp3 = expkey[4*idx - 1];
-		if (!(idx % AES_KEYCOLS)) {
+		if (!(idx % aes_keycols)) {
 			tmp4 = tmp3;
 			tmp3 = sbox[tmp0];
-			tmp0 = sbox[tmp1] ^ rcon[idx / AES_KEYCOLS];
+			tmp0 = sbox[tmp1] ^ rcon[idx / aes_keycols];
 			tmp1 = sbox[tmp2];
 			tmp2 = sbox[tmp4];
-		} else if ((AES_KEYCOLS > 6) && (idx % AES_KEYCOLS == 4)) {
+		} else if ((aes_keycols > 6) && (idx % aes_keycols == 4)) {
 			tmp0 = sbox[tmp0];
 			tmp1 = sbox[tmp1];
 			tmp2 = sbox[tmp2];
 			tmp3 = sbox[tmp3];
 		}
 
-		expkey[4*idx+0] = expkey[4*idx - 4*AES_KEYCOLS + 0] ^ tmp0;
-		expkey[4*idx+1] = expkey[4*idx - 4*AES_KEYCOLS + 1] ^ tmp1;
-		expkey[4*idx+2] = expkey[4*idx - 4*AES_KEYCOLS + 2] ^ tmp2;
-		expkey[4*idx+3] = expkey[4*idx - 4*AES_KEYCOLS + 3] ^ tmp3;
+		expkey[4*idx+0] = expkey[4*idx - 4*aes_keycols + 0] ^ tmp0;
+		expkey[4*idx+1] = expkey[4*idx - 4*aes_keycols + 1] ^ tmp1;
+		expkey[4*idx+2] = expkey[4*idx - 4*aes_keycols + 2] ^ tmp2;
+		expkey[4*idx+3] = expkey[4*idx - 4*aes_keycols + 3] ^ tmp3;
 	}
 }
 
 /* encrypt one 128 bit block */
-void aes_encrypt(u8 *in, u8 *expkey, u8 *out)
+void aes_encrypt(u32 key_len, u8 *in, u8 *expkey, u8 *out)
 {
 	u8 state[AES_STATECOLS * 4];
-	u32 round;
+	u32 round, aes_rounds;
+
+	aes_rounds = aes_get_rounds(key_len);
 
 	memcpy(state, in, AES_STATECOLS * 4);
 	add_round_key((u32 *)state, (u32 *)expkey);
 
-	for (round = 1; round < AES_ROUNDS + 1; round++) {
-		if (round < AES_ROUNDS)
+	for (round = 1; round < aes_rounds + 1; round++) {
+		if (round < aes_rounds)
 			mix_sub_columns(state);
 		else
 			shift_rows(state);
@@ -563,18 +592,20 @@ void aes_encrypt(u8 *in, u8 *expkey, u8 *out)
 	memcpy(out, state, sizeof(state));
 }
 
-void aes_decrypt(u8 *in, u8 *expkey, u8 *out)
+void aes_decrypt(u32 key_len, u8 *in, u8 *expkey, u8 *out)
 {
 	u8 state[AES_STATECOLS * 4];
-	int round;
+	int round, aes_rounds;
+
+	aes_rounds = aes_get_rounds(key_len);
 
 	memcpy(state, in, sizeof(state));
 
 	add_round_key((u32 *)state,
-		      (u32 *)expkey + AES_ROUNDS * AES_STATECOLS);
+		      (u32 *)expkey + aes_rounds * AES_STATECOLS);
 	inv_shift_rows(state);
 
-	for (round = AES_ROUNDS; round--; ) {
+	for (round = aes_rounds; round--; ) {
 		add_round_key((u32 *)state,
 			      (u32 *)expkey + round * AES_STATECOLS);
 		if (round)
@@ -596,62 +627,62 @@ void aes_apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst)
 {
 	int i;
 
-	for (i = 0; i < AES_KEY_LENGTH; i++)
+	for (i = 0; i < AES_BLOCK_LENGTH; i++)
 		*dst++ = *src++ ^ *cbc_chain_data++;
 }
 
-void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+void aes_cbc_encrypt_blocks(u32 key_len, u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
 			    u32 num_aes_blocks)
 {
-	u8 tmp_data[AES_KEY_LENGTH];
+	u8 tmp_data[AES_BLOCK_LENGTH];
 	u8 *cbc_chain_data = iv;
 	u32 i;
 
 	for (i = 0; i < num_aes_blocks; i++) {
 		debug("encrypt_object: block %d of %d\n", i, num_aes_blocks);
-		debug_print_vector("AES Src", AES_KEY_LENGTH, src);
+		debug_print_vector("AES Src", AES_BLOCK_LENGTH, src);
 
 		/* Apply the chain data */
 		aes_apply_cbc_chain_data(cbc_chain_data, src, tmp_data);
-		debug_print_vector("AES Xor", AES_KEY_LENGTH, tmp_data);
+		debug_print_vector("AES Xor", AES_BLOCK_LENGTH, tmp_data);
 
 		/* Encrypt the AES block */
-		aes_encrypt(tmp_data, key_exp, dst);
-		debug_print_vector("AES Dst", AES_KEY_LENGTH, dst);
+		aes_encrypt(key_len, tmp_data, key_exp, dst);
+		debug_print_vector("AES Dst", AES_BLOCK_LENGTH, dst);
 
 		/* Update pointers for next loop. */
 		cbc_chain_data = dst;
-		src += AES_KEY_LENGTH;
-		dst += AES_KEY_LENGTH;
+		src += AES_BLOCK_LENGTH;
+		dst += AES_BLOCK_LENGTH;
 	}
 }
 
-void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+void aes_cbc_decrypt_blocks(u32 key_len, u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
 			    u32 num_aes_blocks)
 {
-	u8 tmp_data[AES_KEY_LENGTH], tmp_block[AES_KEY_LENGTH];
+	u8 tmp_data[AES_BLOCK_LENGTH], tmp_block[AES_BLOCK_LENGTH];
 	/* Convenient array of 0's for IV */
-	u8 cbc_chain_data[AES_KEY_LENGTH];
+	u8 cbc_chain_data[AES_BLOCK_LENGTH];
 	u32 i;
 
-	memcpy(cbc_chain_data, iv, AES_KEY_LENGTH);
+	memcpy(cbc_chain_data, iv, AES_BLOCK_LENGTH);
 	for (i = 0; i < num_aes_blocks; i++) {
 		debug("encrypt_object: block %d of %d\n", i, num_aes_blocks);
-		debug_print_vector("AES Src", AES_KEY_LENGTH, src);
+		debug_print_vector("AES Src", AES_BLOCK_LENGTH, src);
 
-		memcpy(tmp_block, src, AES_KEY_LENGTH);
+		memcpy(tmp_block, src, AES_BLOCK_LENGTH);
 
 		/* Decrypt the AES block */
-		aes_decrypt(src, key_exp, tmp_data);
-		debug_print_vector("AES Xor", AES_KEY_LENGTH, tmp_data);
+		aes_decrypt(key_len, src, key_exp, tmp_data);
+		debug_print_vector("AES Xor", AES_BLOCK_LENGTH, tmp_data);
 
 		/* Apply the chain data */
 		aes_apply_cbc_chain_data(cbc_chain_data, tmp_data, dst);
-		debug_print_vector("AES Dst", AES_KEY_LENGTH, dst);
+		debug_print_vector("AES Dst", AES_BLOCK_LENGTH, dst);
 
 		/* Update pointers for next loop. */
-		memcpy(cbc_chain_data, tmp_block, AES_KEY_LENGTH);
-		src += AES_KEY_LENGTH;
-		dst += AES_KEY_LENGTH;
+		memcpy(cbc_chain_data, tmp_block, AES_BLOCK_LENGTH);
+		src += AES_BLOCK_LENGTH;
+		dst += AES_BLOCK_LENGTH;
 	}
 }
diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile
index a51c6e1685..bc9c8af848 100644
--- a/lib/rsa/Makefile
+++ b/lib/rsa/Makefile
@@ -5,5 +5,5 @@
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
-obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o
+obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o
 obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o
diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index 287fcc4d23..157166d622 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -190,7 +190,8 @@ int padding_pss_verify(struct image_sign_info *info,
 	uint8_t *db_mask = NULL;
 	int db_mask_len = masked_db_len;
 	uint8_t *db = NULL, *salt = NULL;
-	int db_len = masked_db_len, salt_len = msg_len - hash_len - 2;
+	int db_len = masked_db_len, 
+		salt_len = SHA256_SUM_LEN;
 	uint8_t pad_zero[8] = { 0 };
 	int ret, i, leftmost_bits = 1;
 	uint8_t leftmost_mask;
@@ -219,7 +220,7 @@ int padding_pss_verify(struct image_sign_info *info,
 	/* step 5 */
 	memcpy(masked_db, msg, masked_db_len);
 	memcpy(h, msg + masked_db_len, h_len);
-
+	
 	/* step 6 */
 	leftmost_mask = (0xff >> (8 - leftmost_bits)) << (8 - leftmost_bits);
 	if (masked_db[0] & leftmost_mask) {
@@ -231,16 +232,16 @@ int padding_pss_verify(struct image_sign_info *info,
 
 	/* step 7 */
 	mask_generation_function1(checksum, h, h_len, db_mask, db_mask_len);
-
+	
 	/* step 8 */
 	for (i = 0; i < db_len; i++)
 		db[i] = masked_db[i] ^ db_mask[i];
-
+	
 	/* step 9 */
-	db[0] &= 0xff >> leftmost_bits;
+	db[db_len - (salt_len+1)] &= 0xff >> leftmost_bits;
 
 	/* step 10 */
-	if (db[0] != 0x01) {
+	if (db[db_len-(salt_len+1)] != 0x01) {
 		printf("%s: invalid pss padding ", __func__);
 		printf("(leftmost byte of db isn't 0x01)\n");
 		ret = EINVAL;
@@ -248,13 +249,13 @@ int padding_pss_verify(struct image_sign_info *info,
 	}
 
 	/* step 11 */
-	memcpy(salt, &db[1], salt_len);
+	memcpy(salt, &db[db_len-salt_len], salt_len);
 
 	/* step 12 & 13 */
 	compute_hash_prime(checksum, pad_zero, 8,
 			   (uint8_t *)hash, hash_len,
 			   salt, salt_len, hprime);
-
+	
 	/* step 14 */
 	ret = memcmp(h, hprime, hash_len);
 
diff --git a/net/Makefile b/net/Makefile
index ce36362168..f680e5d88d 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_CMD_SNTP) += sntp.o
 obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o
 obj-$(CONFIG_UDP_FUNCTION_FASTBOOT)  += fastboot.o
 obj-$(CONFIG_CMD_WOL)  += wol.o
+obj-y  += nmrp.o
 
 # Disable this warning as it is triggered by:
 # sprintf(buf, index ? "foo%d" : "foo", index)
diff --git a/net/net.c b/net/net.c
index 58b0417cbe..be11b1a131 100644
--- a/net/net.c
+++ b/net/net.c
@@ -109,6 +109,9 @@
 #endif
 #include "link_local.h"
 #include "nfs.h"
+#if defined(CONFIG_SYS_NMRP)
+#include "nmrp.h"
+#endif
 #include "ping.h"
 #include "rarp.h"
 #if defined(CONFIG_CMD_SNTP)
@@ -177,6 +180,20 @@ u32 net_boot_file_size;
 /* Boot file size in blocks as reported by the DHCP server */
 u32 net_boot_file_expected_size_in_blocks;
 
+#ifdef FIRMWARE_RECOVER_FROM_TFTP_SERVER
+uchar NetOurTftpIP[4] = { 192, 168, 1, 1 };
+int NetRunTftpServer = 0;
+uchar TftpClientEther[6] = { 0, 0, 0, 0, 0, 0};
+//extern int read_board_data(uchar *board_data)
+struct in_addr TftpClientIP;
+#ifdef DNI_NAND
+#include <nand.h>
+#else
+extern flash_info_t flash_info[];
+#endif
+#endif
+#include <dni_common.h>
+
 #if defined(CONFIG_CMD_SNTP)
 /* NTP server IP address */
 struct in_addr	net_ntp_server;
@@ -210,6 +227,8 @@ static int net_try_count;
 
 int __maybe_unused net_busy_flag;
 
+int (*ip_tap)(uchar *in_packet, int len, struct ip_udp_hdr *ip) = NULL;
+
 /**********************************************************************/
 
 static int on_ipaddr(const char *name, const char *value, enum env_op op,
@@ -454,8 +473,28 @@ restart:
 		case TFTPPUT:
 #endif
 			/* always use ARP to get server ethernet address */
+#ifdef FIRMWARE_RECOVER_FROM_TFTP_SERVER
+			if(NetRunTftpServer)
+			{
+#ifdef CONFIG_SYS_NMRP
+				if (NmrpState != 0) {
+					net_server_ip.s_addr = 1;
+					memcpy(&(net_ip.s_addr), NetOurTftpIP,4);
+					net_gateway.s_addr = 0;
+				}
+#endif
+				TftpServerStart();
+			}
+			else
+#endif
 			tftp_start(protocol);
 			break;
+#ifdef CONFIG_SYS_NMRP
+		case NMRP:
+			NmrpStart();
+			break;
+#endif
+
 #ifdef CONFIG_CMD_TFTPSRV
 		case TFTPSRV:
 			tftp_start_server();
@@ -555,6 +594,7 @@ restart:
 	 *	Main packet reception loop.  Loop receiving packets until
 	 *	someone sets `net_state' to a state that terminates.
 	 */
+skip_netloop:
 	for (;;) {
 		WATCHDOG_RESET();
 #ifdef CONFIG_SHOW_ACTIVITY
@@ -630,6 +670,10 @@ restart:
 			goto restart;
 
 		case NETLOOP_SUCCESS:
+#ifdef CONFIG_SYS_NMRP
+			if (NmrpState == STATE_CLOSING)
+				goto skip_netloop;
+#endif
 			net_cleanup_loop();
 			if (net_boot_file_size > 0) {
 				printf("Bytes transferred = %d (%x hex)\n",
@@ -1075,6 +1119,7 @@ void net_process_received_packet(uchar *in_packet, int len)
 	struct ip_udp_hdr *ip;
 	struct in_addr dst_ip;
 	struct in_addr src_ip;
+	struct in_addr zero_ip;
 	int eth_proto;
 #if defined(CONFIG_CMD_CDP)
 	int iscdp;
@@ -1171,18 +1216,44 @@ void net_process_received_packet(uchar *in_packet, int len)
 	}
 
 	switch (eth_proto) {
+
+#ifdef CONFIG_SYS_NMRP
+		case PROT_NMRP:
+			if(len <= MIN_ETHER_NMRP_LEN){
+				printf("bad packet len@!\n");
+				return;
+			}
+			memcpy(NmrpServerEther,et->et_src,6);
+            zero_ip.s_addr = 0;
+			(*udp_packet_handler)((uchar *)ip, 0, zero_ip, 0, PROT_NMRP);
+			break;
+#endif
 	case PROT_ARP:
 		arp_receive(et, ip, len);
 		break;
 
 #ifdef CONFIG_CMD_RARP
 	case PROT_RARP:
+
+#ifdef FIRMWARE_RECOVER_FROM_TFTP_SERVER
+		if(NetRunTftpServer == 1 )
+		{
+			debug("Got RARP\n");
+			return;
+		}
+#endif
 		rarp_receive(ip, len);
 		break;
 #endif
 	case PROT_IP:
 		debug_cond(DEBUG_NET_PKT, "Got IP\n");
-		/* Before we start poking the header, make sure it is there */
+
+		if(ip_tap)
+		{
+			if(ip_tap(net_rx_packet, net_rx_packet_len, ip))
+				return;
+		}
+        /* Before we start poking the header, make sure it is there */
 		if (len < IP_UDP_HDR_SIZE) {
 			debug("len bad %d < %lu\n", len,
 			      (ulong)IP_UDP_HDR_SIZE);
@@ -1212,10 +1283,17 @@ void net_process_received_packet(uchar *in_packet, int len)
 		dst_ip = net_read_ip(&ip->ip_dst);
 		if (net_ip.s_addr && dst_ip.s_addr != net_ip.s_addr &&
 		    dst_ip.s_addr != 0xFFFFFFFF) {
+#ifdef CONFIG_MCAST_TFTP
+			if (net_mcast_addr != dst_ip)
+#endif
 				return;
 		}
 		/* Read source IP address for later use */
 		src_ip = net_read_ip(&ip->ip_src);
+#ifdef FIRMWARE_RECOVER_FROM_TFTP_SERVER
+		/* Saved the Client IP address anyway for future use */
+		TftpClientIP = net_read_ip(&ip->ip_src);
+#endif
 		/*
 		 * The function returns the unchanged packet if it's not
 		 * a fragment, and either the complete packet or NULL if
@@ -1252,6 +1330,9 @@ void net_process_received_packet(uchar *in_packet, int len)
 			return;
 		}
 
+		if (ntohs(ip->udp_len) < UDP_HDR_SIZE || ntohs(ip->udp_len) > ntohs(ip->ip_len))
+			return;
+
 		debug_cond(DEBUG_DEV_PKT,
 			   "received UDP (to=%pI4, from=%pI4, len=%d)\n",
 			   &dst_ip, &src_ip, len);
@@ -1613,3 +1694,651 @@ ushort env_get_vlan(char *var)
 {
 	return string_to_vlan(env_get(var));
 }
+
+#ifdef FIRMWARE_RECOVER_FROM_TFTP_SERVER
+extern int flash_sect_erase (ulong, ulong);
+
+void SendNmrpAlive(void)
+{
+    if (NmrpState == STATE_KEEP_ALIVE) 
+        NmrpSend();
+}
+
+/* Check if Alive-timer expires? */
+void CheckNmrpAliveTimerExpire(int send_nmrp_alive)
+{
+	ulong passed;
+
+	passed = get_timer(NmrpAliveTimerStart);
+	if ((passed / CONFIG_SYS_HZ) + NmrpAliveTimerBase > NMRP_TIMEOUT_ACTIVE) {
+		printf("Active-timer expires\n");
+		if (send_nmrp_alive) NmrpSend();
+		NmrpAliveTimerBase = NMRP_TIMEOUT_ACTIVE / 4;
+		NmrpAliveTimerStart = get_timer(0);
+	} else {
+		printf("Alive-timer %u\n", (passed / CONFIG_SYS_HZ) + NmrpAliveTimerBase);
+		/* If passed 1/4 NMRP_TIMEOUT_ACTIVE,
+		 * add 1/4 NMRP_TIMEOUT_ACTIVE to NmrpAliveTimerBase.
+		 * This is for avoiding "passed" overflow.
+		 */
+		if ((passed / CONFIG_SYS_HZ) >= (NMRP_TIMEOUT_ACTIVE / 4)) {
+			NmrpAliveTimerBase += NMRP_TIMEOUT_ACTIVE / 4;
+			NmrpAliveTimerStart = get_timer(0);
+			printf("NmrpAliveTimerBase %u\n", NmrpAliveTimerBase);
+		}
+	}
+}
+
+#ifdef DNI_NAND
+#if 0
+/**
+ * handle_nand_modify_error:
+ *
+ * Handle erase or write error occured in a NAND erase block.
+ *
+ * For now, following method is adopted:
+ *
+ *     * Read the block again. If error, mark the block as bad and reset
+ *       board.
+ *
+ *     * Optionally, if original data which is supposed to be written into the
+ *       block is provided, compare read data with it. If 2 data are
+ *       different, mark the block as bad and reset board.
+ *
+ *     * "mark the block as bad and reset board" above takes effect only when
+ *       markbad function is implemented in NAND flash driver. If markbad is
+ *       not implemented, nothing happens so that behaviors in old version of
+ *       code are preserved.
+ *
+ * @param nand       NAND device
+ * @param offset     offset in flash
+ * @param orig_data  buffer containing data before being written.
+ *                   pass NULL if you do not want to verify written data.
+ * @return           never return if block is being tried to be marked as bad
+ */
+static void handle_nand_modify_error(nand_info_t *nand, ulong offset,
+                                     uchar *orig_data)
+{
+	int rval;
+	size_t read_length = CONFIG_SYS_FLASH_SECTOR_SIZE;
+	uchar buffer[CONFIG_SYS_FLASH_SECTOR_SIZE];
+
+	printf("Try to read block 0x%lx ... ", offset);
+	rval = nand_read(nand, offset, &read_length, buffer);
+
+	/* ECC-correctable block */
+	if (rval == -EUCLEAN) {
+		rval = 0;
+	}
+	printf("%s\n", rval ? "ERROR" : "OK");
+
+	if (rval == 0 && orig_data != NULL) {
+		puts("Compare written data with original data ... ");
+		rval = memcmp(orig_data, buffer,
+		              CONFIG_SYS_FLASH_SECTOR_SIZE);
+		printf("%s\n", rval ? "DIFFERENT" : "SAME");
+	}
+
+	if (rval && nand->block_markbad != NULL) {
+		printf("Marking block 0x%lx as bad block ... ", offset);
+		rval = nand->block_markbad(nand, offset);
+		printf("%s\n", rval ? "FAILED" : "SUCCESS");
+
+		do_reset(NULL, 0, 0, NULL);
+	}
+}
+
+void update_data(ulong addr, int data_size, ulong target_addr_begin, size_t target_addr_len, int send_nmrp_alive, int mark_bad_reset)
+{
+	int offset_num;
+	uchar *src_addr;
+	ulong target_addr;
+
+	if (data_size <= 1) {
+		printf("Incorrect data size\n");
+		return;
+	}
+
+	target_addr = target_addr_begin;
+	for (offset_num = 0;
+	     offset_num < (((data_size - 1) / CONFIG_SYS_FLASH_SECTOR_SIZE) + 1);
+	     offset_num++) {
+		nand_erase_options_t nand_erase_options;
+		size_t write_size;
+		int ret = 0;
+
+		/* erase 64K */
+		while (nand_block_isbad(&nand_info[0], target_addr)) {
+			printf("Skipping erasing bad block at 0x%08lx\n", target_addr);
+			target_addr += CONFIG_SYS_FLASH_SECTOR_SIZE;
+		}
+		if (target_addr >= target_addr_begin + target_addr_len)
+			goto bad_nand;
+
+		printf("Erasing: off %x, size %x\n", target_addr, CONFIG_SYS_FLASH_SECTOR_SIZE);
+		memset(&nand_erase_options, 0, sizeof(nand_erase_options));
+		nand_erase_options.length = CONFIG_SYS_FLASH_SECTOR_SIZE;
+		nand_erase_options.quiet = 0;
+		nand_erase_options.jffs2 = 1;
+		nand_erase_options.scrub = 0;
+		nand_erase_options.offset = target_addr;
+		ret = nand_erase_opts(&nand_info[0], &nand_erase_options);
+		printf("%s\n", ret ? "ERROR" : "OK");
+
+		if (mark_bad_reset && ret) {
+			handle_nand_modify_error(
+				&nand_info[0], target_addr, NULL);
+		}
+
+		src_addr = addr + offset_num * CONFIG_SYS_FLASH_SECTOR_SIZE;
+
+		printf("Writing: from RAM addr %x, to NAND off %x, size %x\n", src_addr, target_addr, CONFIG_SYS_FLASH_SECTOR_SIZE);
+		write_size = CONFIG_SYS_FLASH_SECTOR_SIZE;
+		ret = nand_write_skip_bad(&nand_info[0], target_addr, &write_size, (u_char *)src_addr, 0);
+		printf(" %zu bytes written: %s\n", write_size,
+		       ret ? "ERROR" : "OK");
+
+		if (mark_bad_reset && ret) {
+			handle_nand_modify_error(
+				&nand_info[0], target_addr, src_addr);
+		}
+
+		CheckNmrpAliveTimerExpire(send_nmrp_alive);
+		target_addr += CONFIG_SYS_FLASH_SECTOR_SIZE;
+	}
+	return;
+bad_nand:
+	printf("** FAIL !! too many bad blocks, no enough space for data.\n");
+}
+#endif
+void update_firmware(ulong addr, int firmware_size)
+{
+    int ret = -1;
+    int img_index = get_img_index_for_upgrade(0);
+    ret = flash_upgrade_img_bundle(addr, img_index, NULL);
+
+		if( ret ) {
+			printf("ERROR: HTTP Image upgrade failed!!\n");
+		} else {
+			printf("INFO: HTTP Image upgrade successfull!!\n");		
+			//FIXME: Check boot once flag before committing?
+			commit_image( img_index );
+		}
+#ifdef CONFIG_SYS_NMRP
+	if(NmrpState != 0)
+		return;
+#endif
+	printf ("Done\nRebooting...\n");
+	
+	do_reset(NULL,0,0,NULL);
+}
+#endif
+
+#if 0 //ndef DNI_NAND
+void update_firmware(ulong addr, int firmware_size)
+{
+	if (firmware_size <= 0) {
+		printf("Incorrect firmware size\n");
+		return;
+	}
+	int offset_num;
+	uchar *src_addr;
+	ulong target_addr;
+
+	target_addr = CONFIG_SYS_IMAGE_ADDR_BEGIN;
+	for (offset_num = 0;
+	     offset_num < ((firmware_size / CONFIG_SYS_FLASH_SECTOR_SIZE) + 1);
+	     offset_num++) {
+
+		/* erase 64K */
+		flash_sect_erase(CONFIG_SYS_IMAGE_ADDR_BEGIN +
+				 offset_num * CONFIG_SYS_FLASH_SECTOR_SIZE,
+				 CONFIG_SYS_IMAGE_ADDR_BEGIN +
+				 ((offset_num + 1) * CONFIG_SYS_FLASH_SECTOR_SIZE) - 1);
+
+		CheckNmrpAliveTimerExpire(1);
+		target_addr += CONFIG_SYS_FLASH_SECTOR_SIZE;
+	}
+	printf ("Copy image to Flash... ");
+	target_addr = CONFIG_SYS_IMAGE_ADDR_BEGIN;
+	for (offset_num = 0;
+	     offset_num < ((firmware_size / CONFIG_SYS_FLASH_SECTOR_SIZE) + 1);
+	     offset_num++) {
+
+		src_addr = addr + offset_num * CONFIG_SYS_FLASH_SECTOR_SIZE;
+		flash_write(src_addr, target_addr, CONFIG_SYS_FLASH_SECTOR_SIZE);
+
+		CheckNmrpAliveTimerExpire(1);
+		target_addr += CONFIG_SYS_FLASH_SECTOR_SIZE;
+	}
+#ifdef CONFIG_SYS_NMRP
+	if(NmrpState != 0)
+		return;
+#endif
+	printf ("Done\nRebooting...\n");
+
+	do_reset(NULL,0,0,NULL);
+}
+#endif
+
+void StartTftpServerToRecoveFirmware (void)
+{
+#if 0//todo
+	NetRunTftpServer = 1;
+	ulong addr;
+	image_header_t *hdr;
+	int file_size;
+	char *s;
+	/* pre-set load_addr from CONFIG_SYS_LOAD_ADDR */
+	load_addr = CONFIG_SYS_LOAD_ADDR;//bosheng_add 
+	load_addr = load_addr+2;//bosheng_add memory error modify 0x84000000=>0x84000002
+	//printf("load_addr=0x%08x\n",load_addr);
+	//printf("CONFIG_SYS_LOAD_ADDR=0x%08x\n",CONFIG_SYS_LOAD_ADDR);
+	//printf("load_addr_2=0x%08x\n",load_addr);
+	/* pre-set load_addr from $loadaddr */
+	if ((s = getenv("loadaddr")) != NULL) {
+		load_addr = simple_strtoul(s, NULL, 16);
+	}
+
+tftpstart:
+	addr = load_addr;
+	file_size = net_loop(TFTPGET);
+	if (file_size < 1)
+	{
+		printf ("\nFirmware recovering from TFTP server is stopped or failed! :( \n");
+		NetRunTftpServer = 0;
+		return;
+	}
+
+	//  copy Image to flash
+
+#ifdef CONFIG_SYS_NMRP
+	if (NmrpState == STATE_CLOSED)
+		return;
+	else if ( NmrpState !=0 )
+		NmrpState = STATE_CLOSING;
+#endif
+	//hdr = (image_header_t *)(addr + HEADER_LEN);
+	hdr = (image_header_t *)(addr + HEADER_LEN);
+	printf("hdr=0x%08x\n",hdr);
+	printf("addr=0x%08x\n",addr);
+	printf("addr=0x%08x\n",addr);
+	//printf("(image_header_t *)(addr=0x%08x\n",(image_header_t *)(addr);
+	//printf("(image_header_t *)(addr=0x%08x\n",(image_header_t *)(addr);
+	//printf("(image_header_t +1*)(addr=0x%08x\n",(image_header_t *)(addr+1);
+	//printf("(image_header_t -1*)(addr=0x%08x\n",(image_header_t *)(addr-1);
+	printf("HEA_d=%d\n",HEADER_LEN);
+	printf("HEA_x=0x%08x\n",HEADER_LEN);
+
+
+/***************************************************************///bosheng_board match_test
+#if 1
+	if (!board_match_image_board_id(addr))
+	{
+		printf("board model id mismatch with image id, updating board ID\n");
+		ResetTftpServer();
+		goto tftpstart;
+	}
+#endif
+/***************************************************************/
+
+	//memcpy(add,(add+1),1)
+	/* bosheng_rm
+	if (!board_model_id_match_open_source_id() &&
+	    !image_match_open_source_fw_id(addr) &&
+	    ntohl(hdr->ih_magic) != IH_MAGIC) {
+		puts ("Bad Magic Number,it is forbidden to be written to flash!!\n");
+		ResetTftpServer();
+		goto tftpstart;
+	}
+	*/
+#ifdef NETGEAR_BOARD_ID_SUPPORT
+	if (!board_match_image_hw_id(addr)) {
+		puts ("Board HW ID mismatch,it is forbidden to be written to flash!!\n");
+		ResetTftpServer();
+		goto tftpstart;
+	}
+/*
+	if (!board_model_id_match_open_source_id() &&
+	    (!board_match_image_model_id(addr) &&
+	     !image_match_open_source_fw_id(addr))) {
+		puts ("Board MODEL ID mismatch,it is forbidden to be written to flash!!\n");
+		ResetTftpServer();
+		goto tftpstart;
+	}
+	if (!board_match_image_model_id(addr)) {
+		printf("board model id mismatch with image id, updating board ID\n");
+		board_update_image_model_id(addr);
+	}
+*/
+#endif
+	update_firmware(addr + HEADER_LEN, file_size - HEADER_LEN);
+#ifdef CONFIG_SYS_NMRP
+	if (NmrpState == STATE_CLOSING)
+	{
+		net_set_udp_handler(NmrpHandler);
+		NmrpSend();
+	}
+#endif
+	/*
+	 *  It indicates that tftp server would leave running state when
+	 *  this function returns.
+	 */
+	NetRunTftpServer = 0;
+#endif //todo
+}
+
+int do_fw_recovery (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	StartTftpServerToRecoveFirmware();
+	return 0;
+}
+
+U_BOOT_CMD(
+	fw_recovery,	1,	0,	do_fw_recovery,
+	"start tftp server to recovery dni firmware image.",
+	"- start tftp server to recovery dni firmware image."
+);
+
+#if defined(CONFIG_SYS_NMRP) && defined(CONFIG_SYS_SINGLE_FIRMWARE)
+void UpgradeFirmwareFromNmrpServer(void)
+{
+	NetRunTftpServer = 1;
+	ulong addr;
+	image_header_t *hdr;
+	int file_size;
+	char *s;
+	/* pre-set load_addr from CONFIG_SYS_LOAD_ADDR */
+	load_addr = 0x1000000; //CONFIG_SYS_LOAD_ADDR;
+	load_addr = load_addr+2;//bosheng_add memory error modify 0x84000000=>0x84000002
+	/* pre-set load_addr from $loadaddr */
+
+	if ((s = env_get("loadaddr")) != NULL) {
+		load_addr = simple_strtoul(s, NULL, 16);
+	}
+
+	addr = load_addr;
+	file_size = net_loop(TFTPGET);
+	if (file_size < 1)
+	{
+		printf ("\nFirmware recovering from TFTP server is stopped or failed! :( \n");
+		NetRunTftpServer = 0;
+		return;
+	}
+
+#if defined(CONFIG_SYS_SINGLE_FIRMWARE)
+	NmrpState = STATE_TFTPUPLOADING;
+	net_set_udp_handler(NmrpHandler);
+	NmrpSend();
+#endif
+
+	printf("Ignore Magic number checking when upgrade via NMRP,Magic number is %x!\n", IH_MAGIC);
+	//  copy Image to flash
+#ifdef NETGEAR_BOARD_ID_SUPPORT
+	if (board_match_image_hw_id(addr)) {
+		update_firmware(addr + HEADER_LEN, file_size - HEADER_LEN);
+		board_update_image_model_id(addr);
+	}
+	else {
+		puts ("Board HW ID mismatch,it is forbidden to be written to flash!!\n");
+	}
+#else
+/*******************************************///[bosheng]check the  board id
+	if(board_match_image_board_id(addr)){
+	    NmrpState = STATE_KEEP_ALIVE;
+	    net_set_udp_handler(NmrpHandler);
+		eth_halt();
+        mdelay(1000);
+		eth_init();
+        mdelay(500);
+	    NmrpSend();
+		update_firmware(addr + HEADER_LEN, file_size - HEADER_LEN);
+	}else{
+		puts ("Board HW ID mismatch,it is forbidden to be written to flash!!\n");
+	}
+/******************************************/
+#endif
+
+#if defined(CONFIG_SYS_SINGLE_FIRMWARE)
+	/* firmware write to flash done */
+	NmrpFwUPOption = 0;
+	if (NmrpSTUPOption == 1) {
+		NmrpState = STATE_CONFIGING;
+	} else {
+		NmrpState = STATE_CLOSING;
+	}
+#else
+	NmrpState = STATE_CLOSING;
+#endif
+	net_set_udp_handler(NmrpHandler);
+	NmrpSend();
+	NetRunTftpServer = 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_NMRP) && defined(CONFIG_SYS_SINGLE_FIRMWARE)
+void UpgradeStringTableFromNmrpServer(int table_num)
+{
+#if 0
+	NetRunTftpServer = 1;
+	ulong addr;
+	image_header_t *hdr;
+	int file_size;
+	char *s;
+
+	/* pre-set load_addr from CONFIG_SYS_LOAD_ADDR */
+	load_addr = CONFIG_SYS_LOAD_ADDR;
+
+	/* pre-set load_addr from $loadaddr */
+	if ((s = getenv("loadaddr")) != NULL) {
+		load_addr = simple_strtoul(s, NULL, 16);
+	}
+
+	addr = load_addr;
+	memset(addr, 0, CONFIG_SYS_STRING_TABLE_LEN);
+	file_size = net_loop(TFTPGET);
+	if (file_size < 1)
+	{
+		printf ("\nUpdating string table %d from TFTP server \
+			is stopped or failed! :( \n", table_num);
+		NetRunTftpServer = 0;
+		return;
+	}
+
+	/* TFTP Uploading done */
+	NmrpState = STATE_TFTPUPLOADING;
+	net_set_udp_handler(NmrpHandler);
+	NmrpSend();
+
+	/* Write String Table to flash */
+	board_upgrade_string_table((uchar *)addr, table_num, file_size);//bosheng_modify
+
+	/* upgrade string table done, check if more files */
+	NmrpStringTableUpdateIndex++;
+	if (NmrpStringTableUpdateIndex == NmrpStringTableUpdateCount)
+		NmrpSTUPOption = 0;
+	if (NmrpFwUPOption == 0 && NmrpSTUPOption == 0) {
+		workaround_qca8337_gmac_nmrp_hang_action();
+		printf("Upgrading all done\n");
+		NmrpState = STATE_CLOSING;
+		net_set_udp_handler(NmrpHandler);
+		NmrpSend();
+	} else {
+		printf("More files to be upgrading\n");
+		workaround_qca8337_gmac_nmrp_hang_action();
+		NmrpState = STATE_CONFIGING;
+		net_set_udp_handler(NmrpHandler);
+		NmrpSend();
+	}
+	NetRunTftpServer = 0;
+#endif
+}
+#endif
+
+void ResetTftpServer(void)
+{
+	time_handler = 0;
+#ifdef CONFIG_SYS_NMRP
+	if(NmrpState != 0)
+	{
+		NmrpState = STATE_CONFIGING;
+		NmrpSend();
+	}
+	else
+#endif
+	net_set_state(NETLOOP_RESTART);
+}
+#endif
+#ifdef CONFIG_SYS_NMRP
+void StartNmrpClient(void)
+{
+    //i2c_led_ctrl(LED_LP5562_WHITE, 3, 100);
+    mdelay(4000);
+    if( net_loop(NMRP) < 1)
+    {
+                printf("\n nmrp server is stopped or failed !\n");
+                return;
+    }
+}
+void ResetBootup_usual(void)
+{
+        time_handler = 0;
+        net_set_state(NETLOOP_SUCCESS);
+}
+
+#if 1// defined(CONFIG_SYS_NMRP) && defined(CONFIG_CMD_NMRP)
+int do_nmrp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	StartNmrpClient();
+	return 0;
+}
+
+U_BOOT_CMD(
+	nmrp,	1,	0,	do_nmrp,
+	"start nmrp mechanism to upgrade firmware-image or string-table.",
+	"- start nmrp mechanism to upgrade firmware-image or string-table."
+);
+#endif
+#endif
+/* This image header is not completeness, it lack Board ID files */
+typedef struct imageHdr_s
+{
+    unsigned char magic[4];     /* magic */
+    unsigned char header_len[4];        /* Length of header */
+    unsigned char reserved[8];
+    unsigned char kernel_chksum[4];
+    unsigned char rootfs_chksum[4];
+    unsigned char kernel_len[4];        /* Length of kernel */
+    unsigned char rootfs_len[4];        /* Length of rootfs */
+    unsigned char image_chksum[4];      /* checksum across length of image */
+    unsigned char header_chksum[4];     /* checksum across length of header */
+} imageHdr_s;
+
+
+int board_match_image_board_id(ulong fw_image_addr)
+{
+	int ret;
+ 	char board_model_id[BOARD_MODEL_ID_LENGTH+1];
+ 	char image_model_id[BOARD_MODEL_ID_LENGTH+1];
+	unsigned long headeroffset = 0;
+
+	headeroffset=sizeof(imageHdr_s); 
+	printf("offfset=%d\n",headeroffset);
+	printf("fw_image=0x%08x\n",fw_image_addr);
+	
+    memset(board_model_id, 0, BOARD_MODEL_ID_LENGTH+1);
+    memset(image_model_id, 0, BOARD_MODEL_ID_LENGTH+1);
+    memcpy(board_model_id, env_get("Netgear_boardid"),
+           BOARD_MODEL_ID_LENGTH);
+    memcpy(image_model_id, (char *)fw_image_addr+headeroffset,
+           BOARD_MODEL_ID_LENGTH);//[bosheng_add]image id board_id_offset=> fw_image_addr+40 = image_board_id_offset
+    printf("MODEL ID on board: %s\n", board_model_id);
+    printf("image ID on board: %s\n", image_model_id);
+    if (strcmp(board_model_id, image_model_id) != 0) {
+            printf("Firmware Image HW ID do not match Board HW ID\n");
+            return 0;
+    }
+    printf("Firmware Image HW ID matched Board HW ID\n\n");
+    return 1;
+}
+#if defined(CONFIG_SYS_SINGLE_FIRMWARE)
+extern int nand_env_device;;
+void board_upgrade_string_table(unsigned char *load_addr, int table_number, unsigned int file_size)
+{
+#if 0 //todo
+    unsigned char *string_table_addr, *addr2;
+    unsigned long offset;
+    unsigned int table_length;
+    unsigned char high_bit, low_bit;
+    unsigned long passed;
+    int offset_num;
+    uchar *src_addr;
+    ulong target_addr;
+
+/**************************************************/
+	nand_erase_options_t nand_erase_options;
+	size_t end = CONFIG_SYS_STRING_TABLE_ADDR_BEGIN + ((table_number)* CONFIG_SYS_STRING_TABLE_TOTAL_LEN) ;
+	size_t amount_saved = 0;
+	size_t blocksize, len;
+    u32 start_blocks;
+	u32 size_blocks;
+	u_char *char_ptr;
+	
+	blocksize = nand_info[nand_env_device].erasesize;
+	if (!blocksize)
+		return 1;
+	len = min(blocksize, CONFIG_SYS_STRING_TABLE_TOTAL_LEN);
+	memset(&nand_erase_options, 0, sizeof(nand_erase_options));
+    offset = CONFIG_SYS_STRING_TABLE_ADDR_BEGIN + ((table_number - 1)* CONFIG_SYS_STRING_TABLE_TOTAL_LEN);
+
+	nand_erase_options.length = CONFIG_SYS_STRING_TABLE_TOTAL_LEN;
+	nand_erase_options.offset = offset;
+	
+	printf("Erasing Nand...\n");
+
+	printf("offset=0x%08x\n",offset);
+	printf("file_size=0x%08x\n",file_size);
+	printf("load_addr=0x%08x\n",load_addr);
+	printf("load_addr=0x%08x\n",*load_addr);
+	if (nand_erase_opts(&nand_info[nand_env_device], &nand_erase_options))
+		return 1;
+    printf("Writing to Nand... ");
+	while (amount_saved < file_size && offset < end) {
+		if (nand_block_isbad(&nand_info[nand_env_device], offset)) {
+			offset += blocksize;
+		} else {
+			//char_ptr = &buf[amount_saved];
+			if (nand_write(&nand_info[nand_env_device],
+				       offset, &len, load_addr))
+
+			offset += blocksize;
+			amount_saved += len;
+		}
+	}
+	
+	//if (amount_saved != CONFIG_ENV_SIZE)//bosheng_rm 
+	//	return 1;
+
+    /* Check if Alive-timer expires? */
+    passed = get_timer(NmrpAliveTimerStart);
+        if ((passed / CONFIG_SYS_HZ) + NmrpAliveTimerBase > NmrpAliveTimerTimeout) {
+            printf("Active-timer expires\n");
+            NmrpSend();
+            NmrpAliveTimerBase = NmrpAliveTimerTimeout / 4;
+            NmrpAliveTimerStart = get_timer(0);
+        } else {
+            printf("Alive-timer %u\n",(passed / CONFIG_SYS_HZ) + NmrpAliveTimerBase);
+            /* If passed 1/4 NmrpAliveTimerTimeout,
+             * add 1/4 NmrpAliveTimerTimeout to NmrpAliveTimerBase.
+             * This is for avoiding "passed" overflow.
+             */
+            if ((passed) / CONFIG_SYS_HZ >= (NmrpAliveTimerTimeout / 4)) {
+                NmrpAliveTimerBase += NmrpAliveTimerTimeout / 4;
+                NmrpAliveTimerStart = get_timer(0);
+            }
+        }
+    //}
+#endif //todo
+    return;
+}
+#endif
\ No newline at end of file
diff --git a/net/nmrp.c b/net/nmrp.c
new file mode 100755
index 0000000000..3e603fd58d
--- /dev/null
+++ b/net/nmrp.c
@@ -0,0 +1,592 @@
+/*
+ *     Copyright (C) 2008 Delta Networks Inc.
+ */
+#include <common.h>
+#include <command.h>
+#include <net.h>
+//#include "tftp.h"
+#include "bootp.h"
+#include "nmrp.h"
+#include <dni_common.h>
+
+typedef void nmrp_thand_f(void);
+ulong NmrpOuripaddr;
+ulong NmrpOuripSubnetMask;
+ulong NmrpFwOption;
+int NmrpFwUPOption = 0;
+int NmrpSTUPOption = 0;
+int NmrpStringTableUpdateCount = 0;
+int NmrpStringTableUpdateIndex = 0;
+int NmrpState = 0;
+ulong Nmrp_active_start=0;
+static ulong NmrpBlock;
+static ulong NmrpLastBlock = 0;
+int Nmrp_Listen_TimeoutCount = 0;
+int Nmrp_REQ_TimeoutCount = 0;
+static ulong NmrptimeStart;
+static ulong NmrptimeDelta;
+static nmrp_thand_f *NmrptimeHandler;
+static uchar Nmrpproto;
+static int Nmrp_Closing_TimeoutCount = 0;
+struct in_addr NmrpClientIP;
+uchar NmrpClientEther[6] = { 0, 0, 0, 0, 0, 0 };
+uchar NmrpServerEther[6] = { 0, 0, 0, 0, 0, 0 };
+static u16 NmrpDevRegionOption = 0;
+static uchar NmrpFirmwareFilename[FIRMWARE_FILENAME_LEN] = FIRMWARE_FILENAME;
+static u32 NmrpStringTableBitmask = 0;
+static uchar NmrpStringTableFilename[STRING_TABLE_FILENAME_LEN] = {0};
+static int NmrpStringTableUpdateList[STRING_TABLE_NUMBER_MAX] = {0};
+ulong NmrpAliveTimerStart = 0;
+ulong NmrpAliveTimerBase = 0;
+int NmrpAliveTimerTimeout = NMRP_TIMEOUT_ACTIVE;
+int NmrpAliveWaitACK = 0;
+
+static void Nmrp_Listen_Timeout(void);
+void NmrpSend(void);
+
+void NmrpStart(void);
+
+void NmrpSetTimeout(unchar, ulong, nmrp_thand_f *);
+
+void Nmrp_Led_Flashing_Timeout();
+
+extern void board_reset_default();
+
+static int MyNetSetEther(volatile uchar * xet, uchar * addr, uint prot)
+{
+	struct ethernet_hdr *et = (struct ethernet_hdr *) xet;
+	ushort myvlanid;
+	myvlanid = ntohs(net_our_vlan);
+	if (myvlanid == (ushort) - 1)
+		myvlanid = VLAN_NONE;
+	memcpy(et->et_dest, addr, 6);
+    eth_env_get_enetaddr("ethaddr", net_server_ethaddr);
+	memcpy(et->et_src, net_server_ethaddr, 6);
+	if ((myvlanid & VLAN_IDMASK) == VLAN_NONE) {
+		et->et_protlen = htons(prot);
+		return ETHER_HDR_SIZE;
+	} else {
+		struct vlan_ethernet_hdr *vet =
+				(struct vlan_ethernet_hdr *) xet;
+		vet->vet_vlan_type = htons(PROT_VLAN);
+		vet->vet_tag = htons((0 << 5) | (myvlanid & VLAN_IDMASK));
+		vet->vet_type = htons(prot);
+		return VLAN_ETHER_HDR_SIZE;
+	}
+
+	return ETHER_HDR_SIZE;
+}
+
+static void Nmrp_Conf_Timeout(void)
+{
+	if (++Nmrp_REQ_TimeoutCount > NMRP_MAX_RETRY_CONF) {
+		puts("\n retry conf count exceeded;\n");
+		Nmrp_REQ_TimeoutCount = 0;
+		NmrpStart();
+	} else {
+		puts("T");
+		NmrpSetTimeout(NMRP_CODE_CONF_ACK,
+			       (NMRP_TIMEOUT_REQ * CONFIG_SYS_HZ) / 2,
+			       Nmrp_Conf_Timeout);
+		NmrpSend();
+	}
+}
+
+void Nmrp_Closing_Timeout()
+{
+
+	if (++Nmrp_Closing_TimeoutCount > NMRP_MAX_RETRY_CLOSE) {
+		puts("\n close retry count exceed;stay idle and blink\n");
+		Nmrp_Closing_TimeoutCount = 0;
+		//board_reset_default(); toso Silver
+
+		puts("\nNMRP is complete. Please switch OFF power.\n");
+
+		Nmrp_Led_Flashing_Timeout();
+		/* Unreachable */
+
+		ctrlc();
+		console_assign(stdout, "nulldev");
+		console_assign(stderr, "nulldev");
+		NmrpState = STATE_CLOSED;
+		net_set_state(NETLOOP_SUCCESS);
+	} else {
+		puts("T");
+		NmrpSetTimeout(NMRP_CODE_CLOSE_ACK,
+			       (CONFIG_SYS_HZ * NMRP_TIMEOUT_REQ) / 2,
+			       Nmrp_Closing_Timeout);
+		NmrpSend();
+	}
+}
+
+#define LED_REG_IN_OUT		0xff800500
+#define LED_TEST_MASK		0x08000000
+#define LED_AL_AH_REG		0xff800528
+
+void board_test_led(int status)
+{
+	volatile uint32_t *cled_al_ah_reg = (void *)(LED_AL_AH_REG);
+	volatile uint32_t *cled_in_out_reg = (void *)(LED_REG_IN_OUT);
+	uint32_t val32;
+
+	val32 = *cled_in_out_reg;
+	val32 |= LED_TEST_MASK;
+	*cled_in_out_reg = val32;
+
+	val32 = *cled_al_ah_reg;
+    if( status == 0 )
+	    val32 &= ~LED_TEST_MASK;
+    else
+	    val32 |= LED_TEST_MASK;
+	*cled_al_ah_reg = val32;
+}
+
+void Nmrp_Led_Flashing_Timeout()
+{
+	static int NmrpLedCount = 0;
+	while (1) {
+		NmrpLedCount++;
+		if ((NmrpLedCount % 2) == 1) {
+			board_test_led(0);
+			udelay(500000);
+		} else {
+			board_test_led(1);
+			udelay(500000);
+		}
+	}
+	/* Unreachable */
+
+	/*press ctl+c, turn on test led,then normally boot*/
+	board_test_led(0);
+}
+
+extern void NmrpSend(void)
+{
+	volatile u8 *pkt;
+	volatile u8 *xp;
+	int len = 0;
+	int eth_len = 0;
+	pkt = (u8 *) net_tx_packet;
+	pkt += MyNetSetEther(pkt, NmrpServerEther, PROT_NMRP);
+	eth_len = pkt - net_tx_packet;
+
+	switch (NmrpState) {
+	case STATE_LISTENING:
+		xp = pkt;
+		*((u16 *) pkt) = 0;
+		pkt += 2;
+		*((u8 *) pkt) = (NMRP_CODE_CONF_REQ);
+		pkt++;
+		*((u8 *) pkt) = 0;
+		pkt++;
+		*((u16 *) pkt) = htons(6);
+		pkt += 2;
+
+		len = pkt - xp;
+
+		(void)net_send_packet((u8 *) net_tx_packet, eth_len + len);
+		net_set_timeout_handler((NMRP_TIMEOUT_REQ * CONFIG_SYS_HZ) / 2,
+			      Nmrp_Conf_Timeout);
+		NmrpSetTimeout(NMRP_CODE_CONF_ACK,
+			       (NMRP_TIMEOUT_REQ * CONFIG_SYS_HZ) / 2,
+			       Nmrp_Conf_Timeout);
+		break;
+	case STATE_CONFIGING:
+		xp = pkt;
+		*((u16 *) pkt) = 0;
+		pkt += 2;
+		*((u8 *) pkt) = (NMRP_CODE_TFTP_UL_REQ);
+		pkt++;
+		*((u8 *) pkt) = 0;
+		pkt++;
+		/* Recv ST-UP option, upgrade string table.
+		 * add FILE-NAME option to TFTP-UL-REQ
+		 * value of FILE-NAME would like "string table 01"*/
+		if (NmrpSTUPOption == 1) {
+			/* Append the total length to packet
+			 * NMRP_HEADER_LEN for the length of "Reserved", "Code", "Identifier", "Length"
+			 * STRING_TABLE_FILENAME_OPT_LEN for the length of "Options". */
+			*((u16 *) pkt) = htons((NMRP_HEADER_LEN + STRING_TABLE_FILENAME_OPT_LEN));
+			pkt += 2;
+
+			/* Append NMRP option type FILE-NAME */
+			*((u16 *) pkt) = htons(NMRP_OPT_FILE_NAME);
+			pkt += 2;
+
+			/* Append the total length of NMRP option FILE-NAME */
+			*((u16 *) pkt) = htons(STRING_TABLE_FILENAME_OPT_LEN);
+			pkt += 2;
+
+			/* Append the string table filename to FILE-NAME option value */
+			int i;
+			sprintf(NmrpStringTableFilename, "%s%02d", STRING_TABLE_FILENAME_PREFIX,\
+				NmrpStringTableUpdateList[NmrpStringTableUpdateIndex]);
+			for (i = 0; i < STRING_TABLE_FILENAME_LEN; i++) {
+				*((u8 *) pkt) = NmrpStringTableFilename[i];
+				pkt++;
+			}
+			printf("\nReq %s\n", NmrpStringTableFilename);
+		/* No string table updates, or all string table updates finished.
+		 * And received FW-UP option, upgrading firmware,
+		 * add FILE-NAME option to TFTP-UL-REQ */
+		} else {
+			/* Append the total length to packet
+			 * NMRP_HEADER_LEN for the length of "Reserved", "Code", "Identifier", "Length"
+			 * STRING_TABLE_FILENAME_OPT_LEN for the length of "Options". */
+			*((u16 *) pkt) = htons((NMRP_HEADER_LEN + FIRMWARE_FILENAME_OPT_LEN));
+			pkt += 2;
+
+			/* Append NMRP option type FILE-NAME */
+			*((u16 *) pkt) = htons(NMRP_OPT_FILE_NAME);
+			pkt += 2;
+
+			/* Append the total length of NMRP option FILE-NAME for firmware*/
+			*((u16 *) pkt) = htons(FIRMWARE_FILENAME_OPT_LEN);
+			pkt += 2;
+
+			/* Append the firmware filename to FILE-NAME option value */
+			sprintf(NmrpFirmwareFilename, "%s\n", FIRMWARE_FILENAME);
+			int i;
+			for (i = 0; i < FIRMWARE_FILENAME_LEN; i++) {
+				*((u8 *) pkt) = NmrpFirmwareFilename[i];
+				pkt++;
+			}
+		}
+		len = pkt - xp;
+		(void)net_send_packet((u8 *) net_tx_packet, eth_len + len);
+		int update_table_num = NmrpStringTableUpdateList[NmrpStringTableUpdateIndex];
+		if (NmrpSTUPOption == 1)
+			UpgradeStringTableFromNmrpServer(update_table_num);
+		else
+			UpgradeFirmwareFromNmrpServer();
+		break;
+	case STATE_TFTPUPLOADING:
+		printf("TFTP upload done\n");
+		NmrpAliveTimerStart = get_timer(0);
+		NmrpAliveTimerBase = NMRP_TIMEOUT_ACTIVE / 4;
+		NmrpState = STATE_KEEP_ALIVE;
+		break;
+	case STATE_KEEP_ALIVE:
+		printf("NMRP Send Keep alive REQ\n");
+		//workaround_ipq40xx_gmac_nmrp_hang_action();
+		xp = pkt;
+		*((u16 *) pkt) = 0;
+		pkt += 2;
+		*((u8 *) pkt) = (NMRP_CODE_KEEP_ALIVE_REQ);
+		pkt++;
+		*((u8 *) pkt) = 0;
+		pkt++;
+		*((u16 *) pkt) = htons(6);
+		pkt += 2;
+		len = pkt - xp;
+		(void)net_send_packet((u8 *) net_tx_packet, eth_len + len);
+		NmrpAliveWaitACK = 1;
+		break;
+	case STATE_CLOSING:
+		printf("NMRP Send Closing REQ\n");
+		//workaround_qca8337_gmac_nmrp_hang_action();
+		//workaround_ipq40xx_gmac_nmrp_hang_action();
+		eth_halt();
+        mdelay(1000);
+		eth_init();
+        mdelay(500);
+		xp = pkt;
+		*((u16 *) pkt) = 0;
+		pkt += 2;
+		*((u8 *) pkt) = (NMRP_CODE_CLOSE_REQ);
+		pkt++;
+		*((u8 *) pkt) = 0;
+		pkt++;
+		*((u16 *) pkt) = htons(6);
+		pkt += 2;
+		len = pkt - xp;
+		NmrpSetTimeout(NMRP_CODE_CLOSE_ACK, (1 * CONFIG_SYS_HZ),
+			       Nmrp_Closing_Timeout);
+		(void)net_send_packet((u8 *) net_tx_packet, eth_len + len);
+		break;
+
+	case STATE_CLOSED:
+		run_command("sdk restoredefault", 0); //board_reset_default();
+#if defined(CONFIG_HW29765352P32P4000P512P2X2P2X2P4X4) || \
+	defined(CONFIG_HW29765352P0P4096P512P2X2P2X2P4X4) || \
+	defined(CONFIG_HW29765515P0P4096P512P2X2P2X2P2X2)
+		char runcmd[256];
+		printf ("boot_partition_set 1\n");
+		snprintf(runcmd, sizeof(runcmd), "boot_partition_set 1");
+		run_command(runcmd, 0);
+#endif
+		NmrptimeHandler=NULL;
+		puts("\nNMRP is complete. Please switch OFF power.\n");
+
+		Nmrp_Led_Flashing_Timeout();
+		/* Unreachable */
+
+		ctrlc();
+		console_assign(stdout, "nulldev");
+		console_assign(stderr, "nulldev");
+		net_set_state(NETLOOP_SUCCESS);
+		break;
+	default:
+		break;
+
+	}
+
+}
+
+static void Nmrp_Listen_Timeout(void)
+{
+	if (++Nmrp_Listen_TimeoutCount > NMRP_TIMEOUT_LISTEN) {
+		puts("\nRetry count exceeded; boot the image as usual\n");
+		Nmrp_Listen_TimeoutCount = 0;
+		ResetBootup_usual();
+	} else {
+		puts("T");
+		net_set_timeout_handler(CONFIG_SYS_HZ, Nmrp_Listen_Timeout);
+	}
+}
+
+static NMRP_PARSED_OPT *Nmrp_Parse(uchar * pkt, ushort optType)
+{
+	NMRP_PARSED_MSG *msg = (NMRP_PARSED_MSG *) pkt;
+	NMRP_PARSED_OPT *opt, *optEnd;
+	optEnd = &msg->options[msg->numOptions];
+	for (opt = msg->options; opt != optEnd; opt++)
+		if (opt->type == ntohs(optType))
+			break;
+	return msg->numOptions == 0 ? NULL : (opt == optEnd ? NULL : opt);
+}
+
+void NmrpSetTimeout(unchar proto, ulong iv, nmrp_thand_f * f)
+{
+	if (iv == 0) {
+		NmrptimeHandler = (nmrp_thand_f *) 0;
+		Nmrpproto = 0;
+	} else {
+
+		NmrptimeHandler = f;
+		NmrptimeStart = get_timer(0);
+		NmrptimeDelta = iv;
+		Nmrpproto = proto;
+	}
+}
+/*
+  Function to parse the NMRP options inside packet.
+  If all options are parsed correctly, it returns 0.
+ */
+static int Nmrp_Parse_Opts(uchar *pkt, NMRP_PARSED_MSG *nmrp_parsed)
+{
+	nmrp_t *nmrphdr= (nmrp_t*) pkt;
+	NMRP_OPT *nmrp_opt;
+	int remain_len, opt_index = 0;
+
+	nmrp_parsed->reserved = nmrphdr->reserved;
+	nmrp_parsed->code     = nmrphdr->code;
+	nmrp_parsed->id       = nmrphdr->id;
+	nmrp_parsed->length   = nmrphdr->length;
+
+	remain_len = ntohs(nmrphdr->length) - NMRP_HDR_LEN;
+
+	nmrp_opt = &nmrphdr->opt;
+	while (remain_len > 0){
+		memcpy(&nmrp_parsed->options[opt_index], nmrp_opt, ntohs(nmrp_opt->len));
+		remain_len -= ntohs(nmrp_opt->len);
+		nmrp_opt = ((uchar *)nmrp_opt) + ntohs(nmrp_opt->len);
+		opt_index++;
+	}
+	nmrp_parsed->numOptions=opt_index;
+	return remain_len;
+}
+
+void string_table_bitmask_check()
+{
+	int update_bit;
+
+	/* find string tables need to be update, begin with smallest bit */
+	for (update_bit = 0; update_bit < STRING_TABLE_BITMASK_LEN; update_bit++) {
+		if ((NmrpStringTableBitmask & (1 << update_bit)) != 0) {
+			//if bit 0 is set, update ST 1, ... etc
+			NmrpStringTableUpdateList[NmrpStringTableUpdateCount] = update_bit + 1;
+			NmrpStringTableUpdateCount++;
+		}
+	}
+}
+
+void set_region(u16 RegionOption)
+{
+	uchar region[8];
+	sprintf(region, "%04x", RegionOption);
+	env_set("region", region);
+	run_command("saveenv", 0);
+}
+
+void NmrpHandler(uchar * pkt, unsigned dest, struct in_addr src_ip, unsigned src,
+                 unsigned type)
+{
+	nmrp_t *nmrphdr= (nmrp_t*) pkt;
+	uchar proto;
+	unchar *xp = pkt;
+	int fwUpgrade;
+	NMRP_PARSED_MSG nmrp_parsed;
+	NMRP_PARSED_OPT *opt;
+	proto = nmrphdr->code;
+	if (type!=PROT_NMRP)
+		return;
+
+	/* check for timeout,and run the timeout handler
+	   if we have one
+	 */
+
+	if (NmrptimeHandler && ((get_timer(0) - NmrptimeStart) > NmrptimeDelta)
+	    && (proto != Nmrpproto)) {
+		nmrp_thand_f *x;
+		x = NmrptimeHandler;
+		NmrptimeHandler = (nmrp_thand_f *) 0;
+		(*x) ();
+	}
+
+	/*
+	   Check if Reserved field is zero. Per the specification, the reserved
+	   must be all zero in a valid NMRP packet.
+	 */
+	if (nmrphdr->reserved != 0){
+		return;
+	}
+	memset(&nmrp_parsed, 0, sizeof(NMRP_PARSED_MSG));
+
+	/*
+	   Parse the options inside the packet and save it into nmrp_parsed for
+	   future reference.
+	 */
+	if (Nmrp_Parse_Opts(pkt, &nmrp_parsed) != 0){
+		/* Some wrong inside the packet, just discard it */
+		return;
+	}
+
+	NmrpBlock = proto;
+
+	// ignore same packet
+	if (NmrpBlock == NmrpLastBlock)
+		return;
+	NmrpLastBlock = NmrpBlock;
+
+	switch (proto) {
+	case NMRP_CODE_ADVERTISE:	/*listening state * */
+		if (NmrpState == 0) {
+			/*
+			   Check if we get the MAGIC-NO option and the content is match
+			   with the MAGICNO.
+			 */
+			if ((opt = Nmrp_Parse(&nmrp_parsed, NMRP_OPT_MAGIC_NO)) != NULL){
+				int opt_hdr_len = sizeof(opt->type) + sizeof(opt->len);
+				if (memcmp(opt->value.magicno, MAGICNO, ntohs(opt->len) - opt_hdr_len) == 0){
+					NmrpState = STATE_LISTENING;
+					board_test_led(0);
+					printf("\nNMRP CONFIGING");
+					NmrpSend();
+				}
+			}
+		}
+		break;
+	case NMRP_CODE_CONF_ACK:
+		if (NmrpState == STATE_LISTENING) {
+			/*
+			   If there is no DEV-IP option inside the packet, it must be
+			   something wrong in the packet, so just ignore this packet
+			   without any action taken.
+			 */
+			if ((opt = Nmrp_Parse(&nmrp_parsed, NMRP_OPT_DEV_IP)) != NULL){
+				memcpy(NetOurTftpIP, opt->value.ip.addr,IP_ADDR_LEN);
+				/* Do we need the subnet mask? */
+				memcpy(&NmrpOuripSubnetMask, opt->value.ip.mask,IP_ADDR_LEN);
+				/*
+				   FW-UP option is optional for CONF-ACK and it has no effect no
+				   matter what is the content of this option, so we just skip the
+				   process of this option for now, and will add it back when
+				   this option is defined as mandatory.
+				   The process for FW-UP would be similar as the action taken for
+				   DEV-IP and MAGIC-NO.
+				 */
+
+				/*When NMRP Client get CONF-ACK with DEV-REGION option*/
+				if ((opt = Nmrp_Parse(&nmrp_parsed, NMRP_OPT_DEV_REGION)) != NULL) {
+					/* Save DEV-REGION value to board */
+					printf("Get DEV-REGION option, value:0x%04x\n", opt->value.region);
+					NmrpDevRegionOption = ntohs(opt->value.region);
+					printf("Write Region Number 0x%04x to board\n", NmrpDevRegionOption);
+					set_region(NmrpDevRegionOption);
+				}
+				/*Check if NMRP Client get CONF-ACK with FW-UP option*/
+				if ((opt = Nmrp_Parse(&nmrp_parsed, NMRP_OPT_FW_UP)) != NULL) {
+					printf("\nRecv FW-UP option\n");
+					NmrpFwUPOption = 1;
+				} else {
+					printf("\nNo FW-UP option\n");
+					NmrpFwUPOption = 0;
+				}
+
+				/*When NMRP Client get CONF-ACK with ST-UP option*/
+				if ((opt = Nmrp_Parse(&nmrp_parsed, NMRP_OPT_ST_UP)) != NULL) {
+					printf("\nRecv ST-UP option\n");
+					NmrpSTUPOption = 1;
+					/* Reset string tables' update related variables. */
+					NmrpStringTableUpdateCount = 0;
+					NmrpStringTableUpdateIndex = 0;
+					memset(NmrpStringTableUpdateList, 0,\
+						sizeof(NmrpStringTableUpdateList));
+
+					/* Save from network byte-order to host byte-order. */
+					NmrpStringTableBitmask = ntohl(opt->value.string_table_bitmask);
+
+					string_table_bitmask_check();
+					printf("\nTotal %d String Table need updating\n",\
+						NmrpStringTableUpdateCount);
+				} else {
+					printf("\nNo ST-UP option\n");
+					NmrpSTUPOption = 0;
+				}
+				if (NmrpFwUPOption == 0 && NmrpSTUPOption == 0) {
+					NmrpState = STATE_CLOSING;
+					printf("\nNo firmware update, nor string table update\n");
+					NmrpSend();
+				} else {
+					NmrpState = STATE_CONFIGING;
+					printf("\nNMRP WAITING FOR UPLOAD FIRMWARE or STRING TABLES!\n");
+					NmrpSend();
+				}
+			}else
+				break;
+		}
+		break;
+	case NMRP_CODE_KEEP_ALIVE_ACK:
+		if (NmrpState == STATE_KEEP_ALIVE) {
+			if (NmrpAliveWaitACK == 1) {
+				NmrpAliveTimerBase += NMRP_TIMEOUT_ACTIVE / 4;
+				NmrpAliveWaitACK = 0;
+			}
+		}
+		break;
+	case NMRP_CODE_CLOSE_ACK:
+		if (NmrpState == STATE_CLOSING) {
+			NmrpState = STATE_CLOSED;
+			printf("\nNMRP CLOSED");
+			NmrpSend();
+		}
+		break;
+	default:
+		break;
+	}
+
+}
+
+void NmrpStart(void)
+{
+	printf("\n Client starts...[Listening] for ADVERTISE...");
+
+	net_set_timeout_handler(CONFIG_SYS_HZ / 10, Nmrp_Listen_Timeout);
+	net_set_udp_handler(NmrpHandler);
+
+	NmrpState = 0;
+	Nmrp_Listen_TimeoutCount = 0;
+	memset(NmrpClientEther, 0, 6);
+	NmrpClientIP.s_addr = 0;
+}
diff --git a/net/nmrp.h b/net/nmrp.h
new file mode 100755
index 0000000000..1320ed31b9
--- /dev/null
+++ b/net/nmrp.h
@@ -0,0 +1,117 @@
+/*
+ *     Copyright (C) 2008 Delta Networks Inc.
+ */
+
+extern void NmrpConfig(void);
+
+extern void NmrpHandler(uchar * pkt, unsigned dest, struct in_addr src_ip,
+                        unsigned src, unsigned type);
+extern int NmrpState;
+extern int NmrpFwUPOption;
+extern int NmrpSTUPOption;
+extern int NmrpStringTableUpdateCount;
+extern int NmrpStringTableUpdateIndex;
+extern ulong NmrpAliveTimerStart;
+extern ulong NmrpAliveTimerBase;
+extern int NmrpAliveTimerTimeout;
+extern ulong Nmrp_active_start;
+/* NMRP codes */
+enum _nmrp_codes_ {
+	NMRP_CODE_ADVERTISE = 0x01,
+	NMRP_CODE_CONF_REQ = 0x02,
+	NMRP_CODE_CONF_ACK = 0x03,
+	NMRP_CODE_CLOSE_REQ = 0x04,
+	NMRP_CODE_CLOSE_ACK = 0x05,
+	NMRP_CODE_KEEP_ALIVE_REQ = 0x06,
+	NMRP_CODE_KEEP_ALIVE_ACK = 0x07,
+	NMRP_CODE_TFTP_UL_REQ = 0x10
+};
+
+/* NMRP option types */
+enum _nmrp_option_types_ {
+	NMRP_OPT_MAGIC_NO = 0x0001,
+	NMRP_OPT_DEV_IP = 0x0002,
+	NMRP_OPT_DEV_REGION = 0x0004,
+	NMRP_OPT_FW_UP = 0x0101,
+	NMRP_OPT_ST_UP = 0x0102,
+	NMRP_OPT_FILE_NAME = 0x0181
+};
+
+/* NMRP Region value */
+enum _nmrp_region_values_ {
+	NMRP_REGION_NA = 0x0001,
+	NMRP_REGION_WW = 0x0002,
+	NMRP_REGION_GR = 0x0003,
+	NMRP_REGION_PR = 0x0004,
+	NMRP_REGION_RU = 0x0005,
+	NMRP_REGION_BZ = 0x0006,
+	NMRP_REGION_IN = 0x0007,
+	NMRP_REGION_KO = 0x0008,
+	NMRP_REGION_JP = 0x0009
+};
+
+/*  NMRP REQ max retries */
+enum _nmrp_req_max_retries_ {
+	NMRP_MAX_RETRY_CONF = 5,
+	NMRP_MAX_RETRY_CLOSE = 2,
+	NMRP_MAX_RETRY_TFTP_UL = 4
+};
+
+/* NMRP timeouts */
+enum _nmrp_timeouts_ {
+	NMRP_TIMEOUT_REQ = 1,	/* 0.5 sec */
+	NMRP_TIMEOUT_LISTEN = 3,	/* 3 sec */
+	NMRP_TIMEOUT_ACTIVE = 60,	/* 1 minute */
+	NMRP_TIMEOUT_CLOSE = 6,	/* 6 sec */
+	NMRP_TIMEOUT_ADVERTISE = 1	/* 0.5 sec */
+};
+
+#define HEADER_LEN 0x3a
+
+#define STATE_LISTENING 1
+#define STATE_CONFIGING 2
+#define STATE_TFTPWAITING 3
+#define STATE_TFTPUPLOADING 4
+#define STATE_CLOSING 5
+#define STATE_CLOSED 6
+#define STATE_KEEP_ALIVE 7
+#define NMRP_HEADER_LEN 6
+#define NMRP_OPT_HEADER_LEN 4
+#define MAGICNO "NTGR"
+#define IP_LEN 4
+#define MAGIC_NO_LEN 4
+#define DEV_REGION_LEN 2
+#define FIRMWARE_FILENAME "firmware"
+#define FIRMWARE_FILENAME_LEN 8
+#define FIRMWARE_FILENAME_OPT_LEN (NMRP_OPT_HEADER_LEN + FIRMWARE_FILENAME_LEN)
+#define STRING_TABLE_BITMASK_LEN 32
+#define STRING_TABLE_NUMBER_MAX STRING_TABLE_BITMASK_LEN
+#define STRING_TABLE_FILENAME_PREFIX "string table "
+#define STRING_TABLE_FILENAME_PREFIX_LEN 13
+#define STRING_TABLE_FILENAME_EXAMPLE "string table 01"
+#define STRING_TABLE_FILENAME_LEN (STRING_TABLE_FILENAME_PREFIX_LEN + 2)
+#define STRING_TABLE_FILENAME_OPT_LEN (NMRP_OPT_HEADER_LEN + STRING_TABLE_FILENAME_LEN)
+
+#define NMRP_MAX_OPT_PER_MSG 6
+typedef struct {
+	ushort type;
+	ushort len;
+	union {
+		uchar magicno[MAGIC_NO_LEN];
+		struct{
+			uchar addr[IP_LEN];
+			uchar mask[IP_LEN];
+		}ip;
+		u16 region;
+		u32 string_table_bitmask;
+	} value;
+}__attribute__ ((packed)) NMRP_PARSED_OPT;
+
+typedef struct {
+	ushort reserved;
+	uchar code;
+	uchar id;
+	ushort length;
+	int numOptions;
+	NMRP_PARSED_OPT options[NMRP_MAX_OPT_PER_MSG];
+}__attribute__ ((packed)) NMRP_PARSED_MSG;
diff --git a/net/tftp.c b/net/tftp.c
index 34488b76c8..bdd0a66c7a 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -19,6 +19,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_NMRP
+#include "nmrp.h"
+#endif
+
 /* Well known TFTP port # */
 #define WELL_KNOWN_PORT	69
 /* Millisecs to timeout for lost pkt */
@@ -110,6 +114,20 @@ static int	tftp_put_final_block_sent;
 #define STATE_RECV_WRQ	6
 #define STATE_SEND_WRQ	7
 
+#ifdef CONFIG_SYS_NMRP
+uchar TestNmrpIP[2] = {192,168};
+static int Nmrp_Waiting_TimeoutCount = 0;
+static int nmrpconfflag = 1;
+#endif
+
+#ifdef FIRMWARE_RECOVER_FROM_TFTP_SERVER
+#define STATE_WRQ 10
+#define STATE_BAD_IMAGE_TYPE 11
+#define STATE_BAD_IMAGE_CHKSUM 12
+static int TftpClientPort;
+static uchar ImageCheckSum = 0;
+#endif
+
 /* default TFTP block size */
 #define TFTP_BLOCK_SIZE		512
 /* sequence number is 16 bit */
@@ -145,6 +163,7 @@ static inline int store_block(int block, uchar *src, unsigned int len)
 	ulong offset = block * tftp_block_size + tftp_block_wrap_offset;
 	ulong newsize = offset + len;
 	ulong store_addr = tftp_load_addr + offset;
+#ifndef CONFIG_SYS_NMRP
 #ifdef CONFIG_SYS_DIRECT_FLASH_TFTP
 	int i, rc = 0;
 
@@ -166,9 +185,11 @@ static inline int store_block(int block, uchar *src, unsigned int len)
 		}
 	} else
 #endif /* CONFIG_SYS_DIRECT_FLASH_TFTP */
+#endif
 	{
 		void *ptr;
 
+#ifndef CONFIG_SYS_NMRP
 #ifdef CONFIG_LMB
 		if (store_addr < tftp_load_addr ||
 		    store_addr + len > tftp_load_addr + tftp_load_size) {
@@ -176,8 +197,21 @@ static inline int store_block(int block, uchar *src, unsigned int len)
 			puts("trying to overwrite reserved memory...\n");
 			return -1;
 		}
+#endif
 #endif
 		ptr = map_sysmem(store_addr, len);
+#ifdef FIRMWARE_RECOVER_FROM_TFTP_SERVER
+		if(NetRunTftpServer)
+		{
+			uchar *dest=(uchar *)(load_addr + offset);
+			while(len--)
+			{
+				ImageCheckSum = (ImageCheckSum + (*src)) & 0xFF;
+				*dest++=*src++;
+			}
+		}
+		else
+#endif
 		memcpy(ptr, src, len);
 		unmap_sysmem(ptr);
 	}
@@ -393,8 +427,47 @@ static void tftp_send(void)
 		pkt += 18 /*strlen("File has bad magic")*/ + 1;
 		len = pkt - xp;
 		break;
+#ifdef FIRMWARE_RECOVER_FROM_TFTP_SERVER
+		case STATE_BAD_IMAGE_TYPE:
+			xp = pkt;
+			s = (ushort *)pkt;
+			*s++=htons(TFTP_ERROR);
+			*s++=htons(2);
+			pkt = (uchar *)s;
+			strcpy ((char *)pkt, "No binary mode used");
+			pkt += 19/*strlen("No binary mode used")*/ + 1;
+			len = pkt - xp;
+			break;
+		case STATE_BAD_IMAGE_CHKSUM:
+			xp = pkt;
+			s=(ushort *)pkt;
+			*s++=htons(TFTP_ERROR);
+			*s++=htons(2);
+			pkt = (uchar *)s;
+			strcpy ((char *)pkt, "File has bad checksum");
+			pkt += 21 /*"File has bad checksum"*/ +1;
+			len = pkt -xp;
+			break;
+#endif
 	}
 
+#ifdef FIRMWARE_RECOVER_FROM_TFTP_SERVER
+	if (NetRunTftpServer)
+	{
+		net_send_udp_packet(TftpClientEther, TftpClientIP, TftpClientPort,tftp_our_port,len);
+		if (tftp_state == STATE_BAD_IMAGE_TYPE)
+		{
+			puts("\nNo binary mode used!\n");
+			ResetTftpServer();
+		}
+		else if (tftp_state == STATE_BAD_IMAGE_CHKSUM)
+		{
+			puts("File has bad checksum!\n");
+			ResetTftpServer();
+		}
+	}
+	else
+#endif
 	net_send_udp_packet(net_server_ethaddr, tftp_remote_ip,
 			    tftp_remote_port, tftp_our_port, len);
 }
@@ -803,3 +876,223 @@ void tftp_start_server(void)
 }
 #endif /* CONFIG_CMD_TFTPSRV */
 
+#ifdef FIRMWARE_RECOVER_FROM_TFTP_SERVER
+static int TftpServerWaiting = 1;
+static uint TftpLedCount = 0;
+
+static void
+TftpServerTimeout (void)
+{
+	ulong timeout = TIMEOUT;
+
+	//workaround_duplicate_tftp_data_packet_bug_of_nmrp_server();
+	if(TftpServerWaiting)
+	{
+#ifdef CONFIG_SYS_NMRP
+		if(NmrpState == STATE_CONFIGING )
+		{
+			if(nmrpconfflag){
+				puts("\nwaiting nmrp server to upload firmware!\n");
+				nmrpconfflag = 0;
+			}
+			if( ++Nmrp_Waiting_TimeoutCount > NMRP_MAX_RETRY_TFTP_UL)
+			{
+				puts("\n retry tftp_upload count exceeded;\n");
+				Nmrp_Waiting_TimeoutCount = 0;
+				NmrpState = STATE_LISTENING;
+				NmrpSend();
+			}else{
+				puts("T");
+				NmrpSend();
+				net_set_timeout_handler((NMRP_TIMEOUT_REQ*CONFIG_SYS_HZ)/2,TftpServerTimeout);
+			}
+		}else{
+#endif
+		TftpLedCount++;
+		if ((TftpLedCount % 2)== 1)
+		{
+			printf("Upgrade Mode\b\b\b\b\b\b\b\b\b\b\b\b");
+			/*power LED (GREEN) 0.25 second on */
+			//board_power_led(0);//bosheng_rm_led
+			net_set_timeout_handler ((CONFIG_SYS_HZ*1)/4, TftpServerTimeout);
+		}else{
+			/* power LED (GREEN) 0.75 second off */
+			//board_power_led(1);_bosheng_rm_led
+			printf("            \b\b\b\b\b\b\b\b\b\b\b\b");
+			net_set_timeout_handler ((CONFIG_SYS_HZ*3)/4, TftpServerTimeout);
+		}
+#ifdef CONFIG_SYS_NMRP
+	}
+#endif
+	}
+	else{
+		if (++timeout_count > TIMEOUT_COUNT) {
+			puts ("\nRetry to wait TFTP Client's Data count exceeded; starting again\n");
+			ResetTftpServer ();
+		} else {
+			puts ("T ");
+			net_set_timeout_handler (timeout, TftpServerTimeout);
+			tftp_send ();
+		}
+	}
+}
+
+static void
+TftpServerHandler(uchar * pkt, unsigned dest, struct in_addr sip, unsigned src,
+                  unsigned len)
+{
+	ushort  proto;
+	ushort *s;
+	ulong timeout = TIMEOUT;
+	//workaround_duplicate_tftp_data_packet_bug_of_nmrp_server();
+	if (dest != tftp_our_port) {
+		return;
+	}
+	if (tftp_state != STATE_WRQ && src != TftpClientPort) {
+		return;
+	}
+
+	if (len < 2) {
+		return;
+	}
+	len -= 2;
+	/* warning: don't use increment (++) in ntohs() macros!! */
+	s = (ushort *)pkt;
+	proto = *s++;
+	pkt = (uchar *)s;
+	switch(ntohs(proto)){
+		case TFTP_RRQ:
+		case TFTP_ACK:
+		case TFTP_OACK:
+			break;
+
+		case TFTP_WRQ:
+			TftpClientPort = src;
+			TftpServerWaiting = 0;
+
+			pkt += strlen((char *)pkt) + 1;
+
+			if(strcmp(pkt, "octet"))
+			{
+				tftp_state = STATE_BAD_IMAGE_TYPE;
+			}
+			else
+			{
+				tftp_state = STATE_OACK;
+				puts ("\nRcv:\n\t");
+			}
+			tftp_send (); /* Send ACK */
+			break;
+
+		case TFTP_DATA:
+			if (len < 2)
+				return;
+			len -= 2;
+			tftp_cur_block = ntohs(*(ushort *)pkt);
+
+			if (tftp_cur_block == 0)
+			{
+				tftp_block_wrap++;
+				tftp_block_wrap_offset += TFTP_BLOCK_SIZE * TFTP_SEQUENCE_SIZE;
+				printf ("\n\t %lu MB reveived\n\t ", tftp_block_wrap_offset>>20);
+			}
+
+			else
+			{
+				if (((tftp_cur_block - 1) % 10) == 0)
+				{
+					putc ('.');
+				}
+				else if ((tftp_cur_block % (10 * HASHES_PER_LINE)) == 0)
+				{
+					puts ("\n\t");
+				}
+			}
+			if (tftp_state == STATE_OACK)
+			{
+				/* first block received */
+				tftp_state = STATE_DATA;
+				tftp_prev_block = 0;
+				tftp_block_wrap = 0;
+				tftp_block_wrap_offset = 0;
+
+				if (tftp_cur_block != 1)
+				{
+					/* Assertion */
+					printf ("\nTFTP error: "
+						"First block is not block 1 (%ld)\n"
+						"Starting again\n\n",
+						tftp_cur_block);
+					ResetTftpServer ();
+					break;
+				}
+			}
+
+			if (tftp_cur_block == tftp_prev_block)
+			{
+				break;
+			}
+
+			tftp_prev_block = tftp_cur_block;
+			net_set_timeout_handler (timeout, TftpServerTimeout);
+
+			store_block (tftp_cur_block - 1, pkt + 2, len);
+	/*bosheng_rm
+			if(len < TFTP_BLOCK_SIZE)
+			{
+				ImageCheckSum = ~ImageCheckSum;
+				if (ImageCheckSum != 0x00 &&
+				    (!image_match_open_source_fw_id(
+						load_addr) &&
+				     !board_model_id_match_open_source_id()))
+				{
+					tftp_state = STATE_BAD_IMAGE_CHKSUM;
+				}
+			}
+	*/
+			tftp_send ();
+			if (len < TFTP_BLOCK_SIZE && tftp_state == STATE_DATA)
+			{
+				puts ("\nDone!\n");
+				net_set_state(NETLOOP_SUCCESS);
+			}
+
+			break;
+
+		case TFTP_ERROR:
+			printf ("\nTFTP error: '%s' (%d)\n", pkt + 2, ntohs(*(ushort *)pkt));
+			puts ("Starting again\n\n");
+			ResetTftpServer();
+			break;
+	}
+}
+
+void
+TftpServerStart(void)
+{
+#ifdef CONFIG_SYS_NMRP
+	if(NmrpState != STATE_CONFIGING)
+#endif
+	puts ("\nThe Router is in TFTP Server Firmware Recovery mode NOW!\n");
+printf("TftpServerStart()\n");
+	printf("Listening on Port : 69, IP Address: %pI4 ...\n", &net_ip);
+	net_set_timeout_handler (CONFIG_SYS_HZ/10, TftpServerTimeout);
+	net_set_udp_handler(TftpServerHandler);
+
+	tftp_our_port  = WELL_KNOWN_PORT;
+	timeout_count = 0;
+	TftpClientPort = 0;
+	tftp_state = STATE_WRQ;
+	tftp_cur_block = 0;
+
+	TftpServerWaiting = 1;
+	TftpLedCount = 0;
+
+	ImageCheckSum = 0;
+
+	/* zero out client ether in case the client ip has changed */
+	memset(TftpClientEther, 0, 6);
+	TftpClientIP.s_addr = 0;
+}
+#endif
+
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 7af6b120b6..e595b88360 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -81,10 +81,11 @@ libs-$(CONFIG_TPL_LIBGENERIC_SUPPORT) += lib/
 else
 libs-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ cmd/ env/
 libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/
+endif
+
 ifdef CONFIG_SPL_FRAMEWORK
 libs-$(CONFIG_PARTITIONS) += disk/
 endif
-endif
 
 libs-y += drivers/
 libs-$(CONFIG_SPL_USB_GADGET) += drivers/usb/dwc3/
diff --git a/scripts/dump_pkgtb b/scripts/dump_pkgtb
new file mode 100755
index 0000000000..e15862153b
--- /dev/null
+++ b/scripts/dump_pkgtb
@@ -0,0 +1,46 @@
+#!/usr/bin/env perl
+
+use FindBin qw[$Bin];
+use lib "$Bin/../../../hostTools/PerlLib";
+use YAML;
+use Digest::SHA qw[sha256 sha256_hex];
+use Digest::CRC qw(crc32);
+use Getopt::Long;
+use File::Basename;
+use bytes;
+
+my $pkgtb = shift @ARGV;
+open( F, "<$pkgtb" ) or die("cant open $pkgtb");
+my $img;
+{
+    local $/;
+    $img = <F>;
+}
+close(F);
+my @a = unpack( "NN", $img );
+die("bad magic number") unless $a[0] == 0xd00dfeed;
+my $len = $a[1];
+open( D, "dtc -O dts $pkgtb |" );
+my $dts;
+{
+    local $/;
+    $dts = <D>;
+}
+close(D);
+print $dts;
+
+while ( $dts =~ /^(?:.*?)(\S+)\s+{\s+(data-size[^{}]*)(.*)$/ms ) {
+    # print "capture $1 $2\n";
+    my $cap  = $2;
+    my $name = $1;
+    $dts = $3;
+    $cap =~ /data-offset\s+=\s+<(\w+)>/ or die("parse error in $cap");
+    my $soff = $len + hex($1);
+    $cap =~ /data-size\s+=\s+<(\w+)>/ or die("parse error in $cap");
+    my $siz = hex($1);
+    my $fnam = "file_$name.bin";
+    open( O, ">$fnam" );
+    print O substr( $img, $soff, $siz );
+    print "extracted $fnam size = $siz\n";
+}
+
diff --git a/tools/Makefile b/tools/Makefile
index 33e90a8025..1719dbfbec 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -50,6 +50,12 @@ HOSTCFLAGS_img2srec.o := -pedantic
 hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes
 HOSTCFLAGS_xway-swap-bytes.o := -pedantic
 
+hostprogs-y += passwd_gen
+passwd_gen-objs := passwd_gen.o lib/sha256.o 
+
+hostprogs-y += swapenvimage
+swapenvimage-objs := swapenvimage.o os_support.o lib/crc32.o
+
 hostprogs-y += mkenvimage
 mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o
 
diff --git a/tools/image-host.c b/tools/image-host.c
index 88b329502c..0eae0f86d2 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -31,7 +31,7 @@ static int fit_set_hash_value(void *fit, int noffset, uint8_t *value,
 				int value_len)
 {
 	int ret;
-
+	(void)fdt_delprop(fit, noffset, FIT_VALUE_PROP);
 	ret = fdt_setprop(fit, noffset, FIT_VALUE_PROP, value, value_len);
 	if (ret) {
 		printf("Can't set hash '%s' property for '%s' node(%s)\n",
diff --git a/tools/img2brec.sh b/tools/img2brec.sh
index 0fcdba27d4..97b20b4b80 100755
--- a/tools/img2brec.sh
+++ b/tools/img2brec.sh
@@ -66,41 +66,43 @@ FILESIZE=`filesize $INFILE`
 output_init()
 {
 echo "\
-********************************************
-* Initialize I/O Pad Driving Strength      *
-********************************************
-0021B80CC4000003AB
-********************************************
-* Initialize SDRAM                         *
-********************************************
-00221000C492120200   ; pre-charge command
-08200000E4   ; special read
-
-00221000C4A2120200   ; auto-refresh command
-08000000E4   ; 8 special read
-08000000E4   ; 8 special read
-08000000E4   ; 8 special read
-08000000E4   ; 8 special read
-08000000E4   ; 8 special read
-08000000E4   ; 8 special read
-08000000E4   ; 8 special read
-08000000E4   ; 8 special read
-
-00221000C4B2120200   ; set mode register
-08111800E4   ; special read
-
-00221000C482124200   ; set normal mode
-
"
+********************************************
+* Initialize I/O Pad Driving Strength      *
+********************************************
+0021B80CC4000003AB
+********************************************
+* Initialize SDRAM                         *
+********************************************
+00221000C492120200   ; pre-charge command
+08200000E4   ; special read
+
+00221000C4A2120200   ; auto-refresh command
+08000000E4   ; 8 special read
+08000000E4   ; 8 special read
+08000000E4   ; 8 special read
+08000000E4   ; 8 special read
+08000000E4   ; 8 special read
+08000000E4   ; 8 special read
+08000000E4   ; 8 special read
+08000000E4   ; 8 special read
+
+00221000C4B2120200   ; set mode register
+08111800E4   ; special read
+
+00221000C482124200   ; set normal mode
+
+"
 }
 
 output_uboot()
 {
 echo "\
-********************************************
-* U-Boot image as bootstrap records        *
-*   will be stored in SDRAM at 0x0A000000  *
-********************************************
-
"
+********************************************
+* U-Boot image as bootstrap records        *
+*   will be stored in SDRAM at 0x0A000000  *
+********************************************
+
+"
 
 cat $INFILE | \
 hexdump -v -e "\"0A0%05.5_ax10\" 16/1 \"%02x\"\"\r\n\"" | \
@@ -110,269 +112,271 @@ tr [:lower:] [:upper:]
 output_flashprog()
 {
 echo "\
-********************************************
-* Address of arguments to flashProg        *
-* ---------------------------------------- *
-* Source      : 0x0A000000                 *
-* Destination : 0x0C000000                 *
"
+********************************************
+* Address of arguments to flashProg        *
+* ---------------------------------------- *
+* Source      : 0x0A000000                 *
+* Destination : 0x0C000000                 *
+"
 
 # get the real size of the U-Boot image
 printf "* Size        : 0x%08X                 *\r\n" $FILESIZE
 printf "********************************************\r\n"
 printf "0AFE0000CC0A0000000C000000%08X\r\n" $FILESIZE
 
-#;0AFE0000CC0A0000000C00000000006000
+#;0AFE0000CC0A0000000C00000000006000
 
 echo "\
-********************************************
-* Flash Program                            *
-********************************************
-0AFE10001008D09FE5AC0000EA00F0A0E1A42DFE0A
-0AFE1010100080FE0A0DC0A0E100D82DE904B04CE2
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-0AFE10401000A81BE9A01DFE0A0DC0A0E100D82DE9
-0AFE10501004B04CE204D04DE20030A0E10D304BE5
-0AFE1060109820A0E330309FE5003093E5033082E0
-0AFE107010003093E5013903E2000053E3F7FFFF0A
-0AFE1080104020A0E310309FE5003093E5032082E0
-0AFE1090100D305BE5003082E500A81BE9A01DFE0A
-0AFE10A0100DC0A0E100D82DE904B04CE20000A0E1
-0AFE10B010D7FFFFEB0030A0E1FF3003E2000053E3
-0AFE10C010FAFFFF0A10309FE5003093E5003093E5
-0AFE10D010FF3003E20300A0E100A81BE9A01DFE0A
-0AFE10E0100DC0A0E100D82DE904B04CE204D04DE2
-0AFE10F0100030A0E10D304BE50D305BE52332A0E1
-0AFE1100100E304BE50E305BE5090053E30300009A
-0AFE1110100E305BE5373083E20E304BE5020000EA
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-0AFE1140100E304BE50E305BE5090053E30300009A
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-0AFE1170100300A0E1B3FFFFEB00A81BE90DC0A0E1
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-0AFE1E34107800000053697A652020202020202020
-0AFE1E44102020202873746F72656420696E203078
-0AFE1E54103041464530303038293A203078000000
-0AFE1E6410507265737320616E79206B657920746F
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-0AFE1F3410202E2E2E000000002073756363656564
-0AFE1F44102E0A0000206661696C656420210A0000
-0AFE100000
-
"
+********************************************
+* Flash Program                            *
+********************************************
+0AFE10001008D09FE5AC0000EA00F0A0E1A42DFE0A
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+0AFE1ED410612720746F20636F6E74696E7565202E
+0AFE1EE4102E2E2E000A0D566572696679696E6720
+0AFE1EF410666C617368202E2E2E0000000A0D426C
+0AFE1F0410616E6B20636865636B696E67202E2E2E
+0AFE1F1410000000000A45726173696E67202E2E2E
+0AFE1F2410000000000A50726F6772616D6D696E67
+0AFE1F3410202E2E2E000000002073756363656564
+0AFE1F44102E0A0000206661696C656420210A0000
+0AFE100000
+
+"
 }
 
 #########################################################
diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c
index 75967d0c2d..9e69ccd1ea 100644
--- a/tools/mkenvimage.c
+++ b/tools/mkenvimage.c
@@ -10,6 +10,7 @@
 
 #include <errno.h>
 #include <fcntl.h>
+#include <getopt.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <stdint.h>
@@ -25,6 +26,8 @@
 #include <version.h>
 
 #define CRC_SIZE sizeof(uint32_t)
+#define UBOOT_ENV_MAGIC  (0x75456e76)
+
 
 static void usage(const char *exec_name)
 {
@@ -40,6 +43,8 @@ static void usage(const char *exec_name)
 	       "\tcolumn are treated as comments (also skipped).\n"
 	       "\t-r : the environment has multiple copies in flash\n"
 	       "\t-b : the target is big endian (default is little endian)\n"
+	       "\t--bootmagic : Prepend headers for boot_magic environment\n"
+	       "\t--metadata : Prepend headers for Metadata\n"
 	       "\t-p <byte> : fill the image with <byte> bytes instead of 0xff bytes\n"
 	       "\t-V : print version information and exit\n"
 	       "\n"
@@ -47,6 +52,15 @@ static void usage(const char *exec_name)
 	       exec_name);
 }
 
+static int bootmagic = 0;
+static int metadata = 0;
+
+static struct option long_opts[] = {
+	{"bootmagic",0,&bootmagic,1},
+	{"metadata",0,&metadata,1},
+	{0,0,0,0},
+};
+
 long int xstrtol(const char *s)
 {
 	long int tmp;
@@ -91,7 +105,7 @@ int main(int argc, char **argv)
 	opterr = 0;
 
 	/* Parse the cmdline */
-	while ((option = getopt(argc, argv, ":s:o:rbp:hV")) != -1) {
+	while ((option = getopt_long(argc, argv, ":s:o:rbp:hV",long_opts,NULL)) != -1) {
 		switch (option) {
 		case 's':
 			datasize = xstrtol(optarg);
@@ -123,6 +137,8 @@ int main(int argc, char **argv)
 				optopt);
 			usage(prg);
 			return EXIT_FAILURE;
+		case 0:
+			break;
 		default:
 			fprintf(stderr, "Wrong option -%c\n", optopt);
 			usage(prg);
@@ -302,6 +318,20 @@ int main(int argc, char **argv)
 		}
 	}
 
+	if (bootmagic || metadata) {
+		uint32_t magichdr[2];
+		magichdr[0] = bigendian ? cpu_to_be32(UBOOT_ENV_MAGIC) : cpu_to_le32(UBOOT_ENV_MAGIC);
+		magichdr[1] = bigendian ? cpu_to_be32(datasize) : cpu_to_le32(datasize);
+		if (metadata) {
+			magichdr[0] = magichdr[1]; 
+		}
+		if (write(bin_fd, magichdr, sizeof(magichdr)) !=
+				sizeof(magichdr)) {
+			fprintf(stderr, "write() failed: %s\n", strerror(errno));
+			return EXIT_FAILURE;
+		}
+	}
+	
 	if (write(bin_fd, dataptr, sizeof(*dataptr) * datasize) !=
 			sizeof(*dataptr) * datasize) {
 		fprintf(stderr, "write() failed: %s\n", strerror(errno));
diff --git a/tools/passwd_gen.c b/tools/passwd_gen.c
new file mode 100644
index 0000000000..da16289402
--- /dev/null
+++ b/tools/passwd_gen.c
@@ -0,0 +1,29 @@
+#include <u-boot/sha256.h>
+#include <string.h>
+
+int main(int argc, char **argv)
+{
+	char combined[256];
+	char sha[32];
+	char password[32];
+	int i;
+	char cset[] =
+	    "abcdefghijk#mnopqrstuvwxyzABCDEFGHIJKLMN-PQRSTUVWXYZ@!23456789_*";
+	long long pass;
+	if (argc != 3) {
+		printf("must have exactly 2 args\n");
+		printf("usage:   %s secret serialnum\n", argv[0]);
+		printf("example:  %s password12345 16777216\n", argv[0]);
+		printf(" would generate the password for device sernum 16777216 if the secret is password12345\n");
+		exit(1);
+	}
+	strcpy(combined, argv[1]);
+	strcat(combined, argv[2]);
+	sha256_csum_wd(combined, strlen(combined), sha, 1024);
+	memcpy(&pass, sha, sizeof(pass));
+	for (i = 0; i < 8; i++) {
+		password[i] = cset[(pass >> (6 * i)) & 0x3f];
+	}
+	password[8] = 0;
+	printf("password:%s\n", password);
+}
diff --git a/tools/swapenvimage.c b/tools/swapenvimage.c
new file mode 100644
index 0000000000..723f5bab6b
--- /dev/null
+++ b/tools/swapenvimage.c
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Broadcom
+ *
+ * (C) Copyright 2011 Free Electrons
+ * David Wagner <david.wagner@free-electrons.com>
+ *
+ * Inspired from envcrc.c:
+ * (C) Copyright 2001
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <getopt.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <unistd.h>
+#include <libgen.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+
+#include "compiler.h"
+#include <u-boot/crc.h>
+#include <version.h>
+
+#define CRC_SIZE sizeof(uint32_t)
+#define UBOOT_ENV_MAGIC  (0x75456e76)
+
+char *exclude[] = {
+	"env_boot_magic=",
+	"stdin=",
+	"stdout=",
+	"stderr=",
+	"fileaddr=",
+	"filesize=",
+	"ethact=",
+	"partition=",
+	"mtddevname=",
+	"fdtcontroladdr=",
+	NULL
+};
+
+static void usage(const char *exec_name)
+{
+	fprintf(stderr, "%s [-h] <input image file>  <input environment value file>\n"
+	       "\n"
+	       "This tool takes a key=value input file (same as would a `printenv' show) and replaces the environment boot_magic_env in an existing image with the new environment.\n"
+	       "\n"
+	       "\tThe input file is in format:\n"
+	       "\t\tkey1=value1\n"
+	       "\t\tkey2=value2\n"
+	       "\t\t...\n"
+	       "\tEmpty lines are skipped, and lines with a # in the first\n"
+	       "\tcolumn are treated as comments (also skipped).\n"
+	       "\t-V : print version information and exit\n"
+	       "\n"
+	       "If the input file is \"-\", data is read from standard input\n",
+	       exec_name);
+}
+
+
+static struct option long_opts[] = {
+	{0,0,0,0},
+};
+
+long int xstrtol(const char *s)
+{
+	long int tmp;
+
+	errno = 0;
+	tmp = strtol(s, NULL, 0);
+	if (!errno)
+		return tmp;
+
+	if (errno == ERANGE)
+		fprintf(stderr, "Bad integer format: %s\n",  s);
+	else
+		fprintf(stderr, "Error while parsing %s: %s\n", s,
+				strerror(errno));
+
+	exit(EXIT_FAILURE);
+}
+
+static int check_excluded(char *evar, int max)
+{
+	int i = 0;
+	int n;
+	while (NULL != exclude[i]) {
+		n = strlen(exclude[i]);
+		if (0 == strncmp(evar, exclude[i], n < max ? n : max))
+		{
+			return(1);
+		}
+		i++;
+	}
+	return(0);
+}
+
+int main(int argc, char **argv)
+{
+	uint32_t crc, havecrc, targetendian_crc;
+	const char *input_img_filename = NULL,*txt_filename = NULL;
+	int input_img_fd, txt_fd;
+	char *dataptr = NULL, *envptr;
+	char *filebuf = NULL;
+	unsigned int filesize = 0, envsize = 0, datasize = 0, tmpdatasize = 0;
+	int bigendian = 0;
+	unsigned char padbyte = 0xff;
+	uint32_t header[3];
+	int offsets[16];
+	int found = 0;
+	int i;
+
+	int option;
+	int ret = EXIT_SUCCESS;
+
+	struct stat txt_file_stat;
+	struct stat input_img_file_stat;
+	unsigned img_filesize = 0;
+
+	int fp, ep;
+	const char *prg;
+
+	prg = basename(argv[0]);
+
+	/* Turn off getopt()'s internal error message */
+	opterr = 0;
+
+	/* Parse the cmdline */
+	while ((option = getopt_long(argc, argv, "hV",long_opts,NULL)) != -1) {
+		switch (option) {
+		case 'h':
+			usage(prg);
+			return EXIT_SUCCESS;
+		case 'V':
+			printf("%s version %s\n", prg, PLAIN_VERSION);
+			return EXIT_SUCCESS;
+		case ':':
+			fprintf(stderr, "Missing argument for option -%c\n",
+				optopt);
+			usage(prg);
+			return EXIT_FAILURE;
+		case 0:
+			break;
+		default:
+			fprintf(stderr, "Wrong option -%c\n", optopt);
+			usage(prg);
+			return EXIT_FAILURE;
+		}
+	}
+
+	if (argc > optind) {
+		input_img_filename = argv[optind];
+		input_img_fd = open(input_img_filename, O_RDWR);
+		ret = fstat(input_img_fd, &input_img_file_stat);
+		if (ret == -1) {
+			fprintf(stderr, "Can't stat() on \"%s\": %s\n",
+					input_img_filename, strerror(errno));
+			return EXIT_FAILURE;
+		}
+
+		img_filesize = input_img_file_stat.st_size;
+	} else {
+		fprintf(stderr,"finame is required\n");
+		exit(1);
+	}
+
+	for (i = 0 ; i < img_filesize ; i += 4096) {
+		lseek(input_img_fd, i, SEEK_SET);
+		read(input_img_fd, header, sizeof(header));
+		if ( UBOOT_ENV_MAGIC == header[0] ) {
+			printf("found magic at %x size %d\n",i,header[1]);
+		} else {
+			continue;
+		}
+		tmpdatasize = header[1];
+		if (tmpdatasize > 65536) {
+			fprintf(stderr,"datasize > 64K not allowed\n");
+			exit(1);
+		}
+		if (dataptr == NULL) {
+			dataptr = malloc(tmpdatasize + 4);
+		} else {
+			dataptr = realloc(dataptr,tmpdatasize + 4);
+		}
+		lseek(input_img_fd, i+8, SEEK_SET);
+		read(input_img_fd, dataptr, tmpdatasize + 4);
+		crc = crc32(0, (const unsigned char *)dataptr+4, tmpdatasize-4);
+		havecrc = header[2];
+		if (crc == havecrc) {
+			printf("CRC ok\n");
+			offsets[found++] = i;
+			datasize = tmpdatasize;
+		} else {
+			printf("CRC FAIL\n");
+		}
+	}
+
+	/* Check datasize and allocate the data */
+	if (datasize == 0) {
+		fprintf(stderr, "No header found\n");
+		return EXIT_FAILURE;
+	}
+
+	/*
+	 * envptr points to the beginning of the actual environment (after the
+	 * crc and possible `redundant' byte
+	 */
+	envsize = datasize - CRC_SIZE;
+	envptr = dataptr + CRC_SIZE;
+
+	/* Pad the environment with the padding byte */
+	memset(envptr, padbyte, envsize);
+
+	/* Open the input file ... */
+	if (optind+1 < argc ) {
+		txt_filename = argv[optind+1];
+		txt_fd = open(txt_filename, O_RDONLY);
+		if (txt_fd == -1) {
+			fprintf(stderr, "Can't open \"%s\": %s\n",
+					txt_filename, strerror(errno));
+			return EXIT_FAILURE;
+		}
+		/* ... and check it */
+		ret = fstat(txt_fd, &txt_file_stat);
+		if (ret == -1) {
+			fprintf(stderr, "Can't stat() on \"%s\": %s\n",
+					txt_filename, strerror(errno));
+			return EXIT_FAILURE;
+		}
+
+		filesize = txt_file_stat.st_size;
+
+		filebuf = mmap(NULL, sizeof(*envptr) * filesize, PROT_READ,
+			       MAP_PRIVATE, txt_fd, 0);
+		if (filebuf == MAP_FAILED) {
+			fprintf(stderr, "mmap (%zu bytes) failed: %s\n",
+					sizeof(*envptr) * filesize,
+					strerror(errno));
+			fprintf(stderr, "Falling back to read()\n");
+
+			filebuf = malloc(sizeof(*envptr) * filesize);
+			ret = read(txt_fd, filebuf, sizeof(*envptr) * filesize);
+			if (ret != sizeof(*envptr) * filesize) {
+				fprintf(stderr, "Can't read the whole input file (%zu bytes): %s\n",
+					sizeof(*envptr) * filesize,
+					strerror(errno));
+
+				return EXIT_FAILURE;
+			}
+		}
+		ret = close(txt_fd);
+	}
+
+	/* Parse a byte at time until reaching the file OR until the environment fills
+	 * up. Check ep against envsize - 1 to allow for extra trailing '\0'. */
+	for (fp = 0, ep = 0 ; fp < filesize && ep < envsize - 1; fp++) {
+		if (filebuf[fp] == '\n') {
+			if (fp == 0 || filebuf[fp-1] == '\n') {
+				/*
+				 * Skip empty lines.
+				 */
+				continue;
+			} else if (filebuf[fp-1] == '\\') {
+				/*
+				 * Embedded newline in a variable.
+				 *
+				 * The backslash was added to the envptr; rewind
+				 * and replace it with a newline
+				 */
+				ep--;
+				envptr[ep++] = '\n';
+			} else {
+				/* End of a variable */
+				envptr[ep++] = '\0';
+			}
+		} else if ((fp == 0 || filebuf[fp-1] == '\n') && (filebuf[fp] == '#' || check_excluded(&filebuf[fp],filesize-fp) != 0)) {
+			/* Comment or excluded, skip the line. */
+			while (++fp < filesize && filebuf[fp] != '\n')
+			continue;
+		} else {
+			envptr[ep++] = filebuf[fp];
+		}
+	}
+	/* If there are more bytes in the file still, it means the env filled up
+	 * before parsing the whole file.  Eat comments & whitespace here to see if
+	 * there was anything meaning full left in the file, and if so, throw a error
+	 * and exit. */
+	for( ; fp < filesize; fp++ )
+	{
+		if (filebuf[fp] == '\n') {
+			if (fp == 0 || filebuf[fp-1] == '\n') {
+				/* Ignore blank lines */
+				continue;
+			}
+		} else if ((fp == 0 || filebuf[fp-1] == '\n') && filebuf[fp] == '#') {
+			while (++fp < filesize && filebuf[fp] != '\n')
+			continue;
+		} else {
+			fprintf(stderr, "The environment file is too large for the target environment storage\n");
+			return EXIT_FAILURE;
+		}
+	}
+	/*
+	 * Make sure there is a final '\0'
+	 * And do it again on the next byte to mark the end of the environment.
+	 */
+	if (envptr[ep-1] != '\0') {
+		envptr[ep++] = '\0';
+		/*
+		 * The text file doesn't have an ending newline.  We need to
+		 * check the env size again to make sure we have room for two \0
+		 */
+		if (ep >= envsize) {
+			fprintf(stderr, "The environment file is too large for the target environment storage\n");
+			return EXIT_FAILURE;
+		}
+		envptr[ep] = '\0';
+	} else {
+		envptr[ep] = '\0';
+	}
+
+	/* Computes the CRC and put it at the beginning of the data */
+	crc = crc32(0, (const unsigned char *)envptr, envsize);
+	targetendian_crc = bigendian ? cpu_to_be32(crc) : cpu_to_le32(crc);
+
+	memcpy(dataptr, &targetendian_crc, sizeof(targetendian_crc));
+	for (i = 0 ; i < found ; i++) {
+
+		lseek(input_img_fd, offsets[i]+8, SEEK_SET);
+		if (write(input_img_fd, dataptr, datasize) !=
+			sizeof(*dataptr) * datasize) {
+			fprintf(stderr, "write() failed: %s\n", strerror(errno));
+			return EXIT_FAILURE;
+		}
+	}
+
+	ret = close(input_img_fd);
+
+	return ret;
+}